From 6f6f656aa75c66c2ba377b060f5bb4da3ec1497a Mon Sep 17 00:00:00 2001
From: "Mr. Jake" <norbertzpilicy@gmail.com>
Date: Sun, 16 Jul 2023 00:16:31 +0200
Subject: [PATCH 001/424] Fixed compile options polluting project (#694)

* Fixed compile options polluting project

Moved add_library higher

* Apply suggestions from code review

Co-authored-by: Paul Bartell <paul.bartell@gmail.com>

* fixed cmakelists keeping in mind the suggestions

---------

Co-authored-by: Paul Bartell <paul.bartell@gmail.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Co-authored-by: Aniruddha Kanhere <60444055+AniruddhaKanhere@users.noreply.github.com>
---
 CMakeLists.txt | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/CMakeLists.txt b/CMakeLists.txt
index a68b652ca..c57d46402 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -228,6 +228,9 @@ elseif((FREERTOS_PORT STREQUAL "A_CUSTOM_PORT") AND (NOT TARGET freertos_kernel_
     "       freertos_kernel_include)")
 endif()
 
+
+add_library(freertos_kernel STATIC)
+
 ########################################################################
 # Overall Compile Options
 # Note the compile option strategy is to error on everything and then
@@ -248,7 +251,7 @@ endif()
 #   MSVC        | MSVC # Note only for MinGW?
 #   Renesas     | ?TBD?
 
-add_compile_options(
+target_compile_options(freertos_kernel PRIVATE
     ### Gnu/Clang C Options
     $<$<COMPILE_LANG_AND_ID:C,GNU>:-fdiagnostics-color=always>
     $<$<COMPILE_LANG_AND_ID:C,Clang>:-fcolor-diagnostics>
@@ -267,7 +270,7 @@ add_compile_options(
 add_subdirectory(include)
 add_subdirectory(portable)
 
-add_library(freertos_kernel STATIC
+target_sources(freertos_kernel PRIVATE
     croutine.c
     event_groups.c
     list.c
@@ -280,6 +283,7 @@ add_library(freertos_kernel STATIC
     $<IF:$<BOOL:$<FILTER:${FREERTOS_HEAP},EXCLUDE,^[1-5]$>>,${FREERTOS_HEAP},portable/MemMang/heap_${FREERTOS_HEAP}.c>
 )
 
+
 target_link_libraries(freertos_kernel
     PUBLIC
         freertos_kernel_port

From 54b13568e43bbe2ef57bda0e97e322d1e28fa385 Mon Sep 17 00:00:00 2001
From: Soren Ptak <Skptak@outlook.com>
Date: Mon, 17 Jul 2023 02:18:31 -0700
Subject: [PATCH 002/424] Fix the comments in the CM3 and CM4 MPU Ports about
 the MPU Region numbers being loaded (#707)

Co-authored-by: Soren Ptak <skptak@amazon.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
---
 portable/GCC/ARM_CM3/port.c         |  0
 portable/GCC/ARM_CM3_MPU/port.c     |  8 ++++----
 portable/GCC/ARM_CM4F/port.c        |  0
 portable/GCC/ARM_CM4_MPU/port.c     | 20 ++++++++++----------
 portable/IAR/ARM_CM4F_MPU/portasm.s | 16 ++++++++--------
 portable/RVDS/ARM_CM4_MPU/port.c    | 16 ++++++++--------
 6 files changed, 30 insertions(+), 30 deletions(-)
 mode change 100755 => 100644 portable/GCC/ARM_CM3/port.c
 mode change 100755 => 100644 portable/GCC/ARM_CM3_MPU/port.c
 mode change 100755 => 100644 portable/GCC/ARM_CM4F/port.c
 mode change 100755 => 100644 portable/GCC/ARM_CM4_MPU/port.c

diff --git a/portable/GCC/ARM_CM3/port.c b/portable/GCC/ARM_CM3/port.c
old mode 100755
new mode 100644
diff --git a/portable/GCC/ARM_CM3_MPU/port.c b/portable/GCC/ARM_CM3_MPU/port.c
old mode 100755
new mode 100644
index d29b31d74..844b2ce1f
--- a/portable/GCC/ARM_CM3_MPU/port.c
+++ b/portable/GCC/ARM_CM3_MPU/port.c
@@ -736,8 +736,8 @@ static void prvRestoreContextOfFirstTask( void )
         " str r3, [r0]                          \n" /* Disable MPU. */
         "                                       \n"
         " ldr r0, =0xe000ed9c                   \n" /* Region Base Address register. */
-        " ldmia r2!, {r4-r11}                   \n" /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
-        " stmia r0, {r4-r11}                    \n" /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
+        " ldmia r2!, {r4-r11}                   \n" /* Read 4 sets of MPU registers [MPU Region # 0 - 3]. */
+        " stmia r0, {r4-r11}                    \n" /* Write 4 sets of MPU registers [MPU Region # 0 - 3]. */
         "                                       \n"
         " ldr r0, =0xe000ed94                   \n" /* MPU_CTRL register. */
         " ldr r3, [r0]                          \n" /* Read the value of MPU_CTRL. */
@@ -1011,8 +1011,8 @@ void xPortPendSVHandler( void )
         " str r3, [r0]                          \n" /* Disable MPU. */
         "                                       \n"
         " ldr r0, =0xe000ed9c                   \n" /* Region Base Address register. */
-        " ldmia r2!, {r4-r11}                   \n" /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
-        " stmia r0, {r4-r11}                    \n" /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
+        " ldmia r2!, {r4-r11}                   \n" /* Read 4 sets of MPU registers [MPU Region # 0 - 3]. */
+        " stmia r0, {r4-r11}                    \n" /* Write 4 sets of MPU registers [MPU Region # 0 - 3]. */
         "                                       \n"
         " ldr r0, =0xe000ed94                   \n" /* MPU_CTRL register. */
         " ldr r3, [r0]                          \n" /* Read the value of MPU_CTRL. */
diff --git a/portable/GCC/ARM_CM4F/port.c b/portable/GCC/ARM_CM4F/port.c
old mode 100755
new mode 100644
diff --git a/portable/GCC/ARM_CM4_MPU/port.c b/portable/GCC/ARM_CM4_MPU/port.c
old mode 100755
new mode 100644
index bbcf733b8..548187db3
--- a/portable/GCC/ARM_CM4_MPU/port.c
+++ b/portable/GCC/ARM_CM4_MPU/port.c
@@ -818,14 +818,14 @@ static void prvRestoreContextOfFirstTask( void )
         " str r3, [r0]                          \n" /* Disable MPU. */
         "                                       \n"
         " ldr r0, =0xe000ed9c                   \n" /* Region Base Address register. */
-        " ldmia r2!, {r4-r11}                   \n" /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
-        " stmia r0, {r4-r11}                    \n" /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
+        " ldmia r2!, {r4-r11}                   \n" /* Read 4 sets of MPU registers [MPU Region # 0 - 3]. */
+        " stmia r0, {r4-r11}                    \n" /* Write 4 sets of MPU registers [MPU Region # 0 - 3]. */
         "                                       \n"
     #if ( configTOTAL_MPU_REGIONS == 16 )
-        " ldmia r2!, {r4-r11}                   \n" /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
-        " stmia r0, {r4-r11}                    \n" /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
-        " ldmia r2!, {r4-r11}                   \n" /* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
-        " stmia r0, {r4-r11}                    \n" /* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
+        " ldmia r2!, {r4-r11}                   \n" /* Read 4 sets of MPU registers [MPU Region # 4 - 8]. */
+        " stmia r0, {r4-r11}                    \n" /* Write 4 sets of MPU registers. [MPU Region # 4 - 8]. */
+        " ldmia r2!, {r4-r11}                   \n" /* Read 4 sets of MPU registers [MPU Region # 9 - 12]. */
+        " stmia r0, {r4-r11}                    \n" /* Write 4 sets of MPU registers. [MPU Region # 9 - 12]. */
     #endif /* configTOTAL_MPU_REGIONS == 16. */
         "                                       \n"
         " ldr r0, =0xe000ed94                   \n" /* MPU_CTRL register. */
@@ -1137,14 +1137,14 @@ void xPortPendSVHandler( void )
         " str r3, [r0]                          \n" /* Disable MPU. */
         "                                       \n"
         " ldr r0, =0xe000ed9c                   \n" /* Region Base Address register. */
-        " ldmia r2!, {r4-r11}                   \n" /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
-        " stmia r0, {r4-r11}                    \n" /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
+        " ldmia r2!, {r4-r11}                   \n" /* Read 4 sets of MPU registers [MPU Region # 0 - 3]. */
+        " stmia r0, {r4-r11}                    \n" /* Write 4 sets of MPU registers [MPU Region # 0 - 3]. */
         "                                       \n"
     #if ( configTOTAL_MPU_REGIONS == 16 )
+        " ldmia r2!, {r4-r11}                   \n" /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
+        " stmia r0, {r4-r11}                    \n" /* Write 4 sets of MPU registers. [MPU Region # 4 - 7]. */
         " ldmia r2!, {r4-r11}                   \n" /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
         " stmia r0, {r4-r11}                    \n" /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
-        " ldmia r2!, {r4-r11}                   \n" /* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
-        " stmia r0, {r4-r11}                    \n" /* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
     #endif /* configTOTAL_MPU_REGIONS == 16. */
         "                                       \n"
         " ldr r0, =0xe000ed94                   \n" /* MPU_CTRL register. */
diff --git a/portable/IAR/ARM_CM4F_MPU/portasm.s b/portable/IAR/ARM_CM4F_MPU/portasm.s
index 3cbe5e0f5..a0cf8baa2 100644
--- a/portable/IAR/ARM_CM4F_MPU/portasm.s
+++ b/portable/IAR/ARM_CM4F_MPU/portasm.s
@@ -114,15 +114,15 @@ xPortPendSVHandler:
     str r3, [r0]                           /* Disable MPU. */
 
     ldr r0, =0xe000ed9c                    /* Region Base Address register. */
-    ldmia r2!, {r4-r11}                    /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
-    stmia r0, {r4-r11}                     /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
+    ldmia r2!, {r4-r11}                    /* Read 4 sets of MPU registers [MPU Region # 0 - 3]. */
+    stmia r0, {r4-r11}                     /* Write 4 sets of MPU registers [MPU Region # 0 - 3]. */
 
 #ifdef configTOTAL_MPU_REGIONS
     #if ( configTOTAL_MPU_REGIONS == 16 )
+        ldmia r2!, {r4-r11}                 /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
+        stmia r0, {r4-r11}                  /* Write 4 sets of MPU registers. [MPU Region # 4 - 7]. */
         ldmia r2!, {r4-r11}                 /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
         stmia r0, {r4-r11}                  /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
-        ldmia r2!, {r4-r11}                 /* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
-        stmia r0, {r4-r11}                  /* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
     #endif /* configTOTAL_MPU_REGIONS == 16. */
 #endif
 
@@ -240,15 +240,15 @@ vPortRestoreContextOfFirstTask:
     str r3, [r0]                           /* Disable MPU. */
 
     ldr r0, =0xe000ed9c                    /* Region Base Address register. */
-    ldmia r2!, {r4-r11}                    /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
-    stmia r0, {r4-r11}                     /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
+    ldmia r2!, {r4-r11}                    /* Read 4 sets of MPU registers [MPU Region # 0 - 3]. */
+    stmia r0, {r4-r11}                     /* Write 4 sets of MPU registers [MPU Region # 0 - 3]. */
 
 #ifdef configTOTAL_MPU_REGIONS
     #if ( configTOTAL_MPU_REGIONS == 16 )
+        ldmia r2!, {r4-r11}                /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
+        stmia r0, {r4-r11}                 /* Write 4 sets of MPU registers. [MPU Region # 4 - 7]. */
         ldmia r2!, {r4-r11}                /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
         stmia r0, {r4-r11}                 /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
-        ldmia r2!, {r4-r11}                /* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
-        stmia r0, {r4-r11}                 /* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
     #endif /* configTOTAL_MPU_REGIONS == 16. */
 #endif
 
diff --git a/portable/RVDS/ARM_CM4_MPU/port.c b/portable/RVDS/ARM_CM4_MPU/port.c
index beb52ea22..7bcf6bc88 100755
--- a/portable/RVDS/ARM_CM4_MPU/port.c
+++ b/portable/RVDS/ARM_CM4_MPU/port.c
@@ -796,14 +796,14 @@ __asm void prvRestoreContextOfFirstTask( void )
     str r3, [r0]                /* Disable MPU. */
 
     ldr r0, =0xe000ed9c         /* Region Base Address register. */
-    ldmia r2!, {r4-r11}         /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
-    stmia r0, {r4-r11}          /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
+    ldmia r2!, {r4-r11}         /* Read 4 sets of MPU registers [MPU Region # 0 - 3]. */
+    stmia r0, {r4-r11}          /* Write 4 sets of MPU registers [MPU Region # 0 - 3]. */
 
     #if ( configTOTAL_MPU_REGIONS == 16 )
+        ldmia r2!, {r4-r11}     /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
+        stmia r0, {r4-r11}      /* Write 4 sets of MPU registers. [MPU Region # 4 - 7]. */
         ldmia r2!, {r4-r11}     /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
         stmia r0, {r4-r11}      /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
-        ldmia r2!, {r4-r11}     /* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
-        stmia r0, {r4-r11}      /* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
     #endif /* configTOTAL_MPU_REGIONS == 16. */
 
     ldr r0, =0xe000ed94         /* MPU_CTRL register. */
@@ -1132,14 +1132,14 @@ __asm void xPortPendSVHandler( void )
     str r3, [r0]                        /* Disable MPU. */
 
     ldr r0, =0xe000ed9c                 /* Region Base Address register. */
-    ldmia r2!, {r4-r11}                 /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
-    stmia r0, {r4-r11}                  /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
+    ldmia r2!, {r4-r11}                 /* Read 4 sets of MPU registers [MPU Region # 0 - 3]. */
+    stmia r0, {r4-r11}                  /* Write 4 sets of MPU registers [MPU Region # 0 - 3]. */
 
 #if ( configTOTAL_MPU_REGIONS == 16 )
+    ldmia r2!, {r4-r11}                 /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
+    stmia r0, {r4-r11}                  /* Write 4 sets of MPU registers. [MPU Region # 4 - 7]. */
     ldmia r2!, {r4-r11}                 /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
     stmia r0, {r4-r11}                  /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
-    ldmia r2!, {r4-r11}                 /* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
-    stmia r0, {r4-r11}                  /* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
 #endif /* configTOTAL_MPU_REGIONS == 16. */
 
     ldr r0, =0xe000ed94                 /* MPU_CTRL register. */

From c3dc20fdb4f15115fcaf8ad3f71fdf5696a30415 Mon Sep 17 00:00:00 2001
From: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Date: Mon, 17 Jul 2023 18:42:05 +0800
Subject: [PATCH 003/424] Update xSemaphoreGetStaticBuffer prototype in comment
 (#704)

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
---
 include/semphr.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/include/semphr.h b/include/semphr.h
index 740be5a5d..e93b708c5 100644
--- a/include/semphr.h
+++ b/include/semphr.h
@@ -1193,7 +1193,8 @@ typedef QueueHandle_t SemaphoreHandle_t;
 /**
  * semphr.h
  * @code{c}
- * BaseType_t xSemaphoreGetStaticBuffer( SemaphoreHandle_t xSemaphore );
+ * BaseType_t xSemaphoreGetStaticBuffer( SemaphoreHandle_t xSemaphore,
+ *                                       StaticSemaphore_t ** ppxSemaphoreBuffer );
  * @endcode
  *
  * Retrieve pointer to a statically created binary semaphore, counting semaphore,

From 71662b5b5abf4c83974de20c9f6d38636ac930b5 Mon Sep 17 00:00:00 2001
From: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Date: Tue, 18 Jul 2023 11:09:52 +0530
Subject: [PATCH 004/424] Correct the misspelled name (#708)

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 History.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/History.txt b/History.txt
index 1bf7ea045..98f9822d4 100644
--- a/History.txt
+++ b/History.txt
@@ -61,7 +61,7 @@ Changes between FreeRTOS V10.5.1 and FreeRTOS 10.6.0 released July 13, 2023
 	      China.
 	    - Xinwen Fu of Department of Computer Science, University of
 	      Massachusetts Lowell, USA.
-	    - Yuequi Chen, Zicheng Wang, Minghao Lin of University of Colorado
+	    - Yueqi Chen, Zicheng Wang, Minghao Lin of University of Colorado
 	      Boulder, USA.
 	+ Add Cortex-M35P port. Contributed by @urutva.
 	+ Add embedded extension (RV32E) support to the IAR RISC-V port.

From 0d03a938cc5b3a3a0fc8c05e943a6552f21b56af Mon Sep 17 00:00:00 2001
From: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Date: Wed, 19 Jul 2023 14:59:08 +0530
Subject: [PATCH 005/424] Fic clang compiler warnings (#711)

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 CMakeLists.txt                                       |  7 ++++++-
 croutine.c                                           | 12 ++++++------
 portable/ThirdParty/GCC/Posix/utils/wait_for_event.h |  6 +++---
 3 files changed, 15 insertions(+), 10 deletions(-)

diff --git a/CMakeLists.txt b/CMakeLists.txt
index c57d46402..6faa93167 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -262,7 +262,12 @@ target_compile_options(freertos_kernel PRIVATE
     $<$<COMPILE_LANG_AND_ID:C,Clang,GNU>:-Werror>
     $<$<COMPILE_LANG_AND_ID:C,Clang>:-Weverything>
 
-    # TODO: Add in other Compilers here.
+    # Suppressions required to build clean with clang.
+    $<$<COMPILE_LANG_AND_ID:C,Clang>:-Wno-unused-macros>
+    $<$<COMPILE_LANG_AND_ID:C,Clang>:-Wno-padded>
+    $<$<COMPILE_LANG_AND_ID:C,Clang>:-Wno-missing-variable-declarations>
+    $<$<COMPILE_LANG_AND_ID:C,Clang>:-Wno-covered-switch-default>
+    $<$<COMPILE_LANG_AND_ID:C,Clang>:-Wno-cast-align>
 )
 
 
diff --git a/croutine.c b/croutine.c
index f38e96247..8969dc89b 100644
--- a/croutine.c
+++ b/croutine.c
@@ -43,12 +43,12 @@
 
 
 /* Lists for ready and blocked co-routines. --------------------*/
-    static List_t pxReadyCoRoutineLists[ configMAX_CO_ROUTINE_PRIORITIES ]; /*< Prioritised ready co-routines. */
-    static List_t xDelayedCoRoutineList1;                                   /*< Delayed co-routines. */
-    static List_t xDelayedCoRoutineList2;                                   /*< Delayed co-routines (two lists are used - one for delays that have overflowed the current tick count. */
-    static List_t * pxDelayedCoRoutineList = NULL;                          /*< Points to the delayed co-routine list currently being used. */
-    static List_t * pxOverflowDelayedCoRoutineList = NULL;                  /*< Points to the delayed co-routine list currently being used to hold co-routines that have overflowed the current tick count. */
-    static List_t xPendingReadyCoRoutineList;                               /*< Holds co-routines that have been readied by an external event.  They cannot be added directly to the ready lists as the ready lists cannot be accessed by interrupts. */
+    static List_t pxReadyCoRoutineLists[ configMAX_CO_ROUTINE_PRIORITIES ]; /**< Prioritised ready co-routines. */
+    static List_t xDelayedCoRoutineList1;                                   /**< Delayed co-routines. */
+    static List_t xDelayedCoRoutineList2;                                   /**< Delayed co-routines (two lists are used - one for delays that have overflowed the current tick count. */
+    static List_t * pxDelayedCoRoutineList = NULL;                          /**< Points to the delayed co-routine list currently being used. */
+    static List_t * pxOverflowDelayedCoRoutineList = NULL;                  /**< Points to the delayed co-routine list currently being used to hold co-routines that have overflowed the current tick count. */
+    static List_t xPendingReadyCoRoutineList;                               /**< Holds co-routines that have been readied by an external event.  They cannot be added directly to the ready lists as the ready lists cannot be accessed by interrupts. */
 
 /* Other file private variables. --------------------------------*/
     CRCB_t * pxCurrentCoRoutine = NULL;
diff --git a/portable/ThirdParty/GCC/Posix/utils/wait_for_event.h b/portable/ThirdParty/GCC/Posix/utils/wait_for_event.h
index 65e3e5481..6f6efa3ea 100644
--- a/portable/ThirdParty/GCC/Posix/utils/wait_for_event.h
+++ b/portable/ThirdParty/GCC/Posix/utils/wait_for_event.h
@@ -26,8 +26,8 @@
  *
  */
 
-#ifndef _WAIT_FOR_EVENT_H_
-#define _WAIT_FOR_EVENT_H_
+#ifndef WAIT_FOR_EVENT_H_
+#define WAIT_FOR_EVENT_H_
 
 #include <stdbool.h>
 #include <time.h>
@@ -43,4 +43,4 @@ void event_signal( struct event * ev );
 
 
 
-#endif /* ifndef _WAIT_FOR_EVENT_H_ */
+#endif /* ifndef WAIT_FOR_EVENT_H_ */

From b375458aabda5c4b2c2822f05fb73509d8ee1fff Mon Sep 17 00:00:00 2001
From: Jeff Tenney <jeff.tenney@gmail.com>
Date: Wed, 19 Jul 2023 05:38:05 -0700
Subject: [PATCH 006/424] Add port-optimised task selection for ARMv8-M (#703)

Add port-optimised task selection for ARMv8-M
---
 portable/ARMv8M/non_secure/port.c             |  12 +-
 .../portable/GCC/ARM_CM23/portmacro.h         |   6 +-
 .../portable/GCC/ARM_CM23_NTZ/portmacro.h     |   6 +-
 .../portable/GCC/ARM_CM33/portmacro.h         |   2 +-
 .../portable/GCC/ARM_CM33_NTZ/portmacro.h     |   2 +-
 .../portable/GCC/ARM_CM35P/portmacro.h        |   2 +-
 .../portable/GCC/ARM_CM55/portmacro.h         |   2 +-
 .../portable/GCC/ARM_CM85/portmacro.h         |   2 +-
 .../portable/IAR/ARM_CM23/portmacro.h         |   6 +-
 .../portable/IAR/ARM_CM23_NTZ/portmacro.h     |   6 +-
 .../portable/IAR/ARM_CM33/portmacro.h         |   2 +-
 .../portable/IAR/ARM_CM33_NTZ/portmacro.h     |   2 +-
 .../portable/IAR/ARM_CM35P/portmacro.h        |   2 +-
 .../portable/IAR/ARM_CM55/portmacro.h         |   2 +-
 .../portable/IAR/ARM_CM85/portmacro.h         |   2 +-
 portable/ARMv8M/non_secure/portmacrocommon.h  | 118 +++++++++++++-----
 portable/GCC/ARM_CM23/non_secure/port.c       |  12 +-
 portable/GCC/ARM_CM23/non_secure/portmacro.h  |   6 +-
 .../GCC/ARM_CM23/non_secure/portmacrocommon.h | 118 +++++++++++++-----
 portable/GCC/ARM_CM23_NTZ/non_secure/port.c   |  12 +-
 .../GCC/ARM_CM23_NTZ/non_secure/portmacro.h   |   6 +-
 .../ARM_CM23_NTZ/non_secure/portmacrocommon.h | 118 +++++++++++++-----
 portable/GCC/ARM_CM33/non_secure/port.c       |  12 +-
 portable/GCC/ARM_CM33/non_secure/portmacro.h  |   2 +-
 .../GCC/ARM_CM33/non_secure/portmacrocommon.h | 118 +++++++++++++-----
 portable/GCC/ARM_CM33_NTZ/non_secure/port.c   |  12 +-
 .../GCC/ARM_CM33_NTZ/non_secure/portmacro.h   |   2 +-
 .../ARM_CM33_NTZ/non_secure/portmacrocommon.h | 118 +++++++++++++-----
 portable/GCC/ARM_CM35P/non_secure/port.c      |  12 +-
 portable/GCC/ARM_CM35P/non_secure/portmacro.h |   2 +-
 .../ARM_CM35P/non_secure/portmacrocommon.h    | 118 +++++++++++++-----
 portable/GCC/ARM_CM35P_NTZ/non_secure/port.c  |  12 +-
 .../GCC/ARM_CM35P_NTZ/non_secure/portmacro.h  |   2 +-
 .../non_secure/portmacrocommon.h              | 118 +++++++++++++-----
 portable/GCC/ARM_CM55/non_secure/port.c       |  12 +-
 portable/GCC/ARM_CM55/non_secure/portmacro.h  |   2 +-
 .../GCC/ARM_CM55/non_secure/portmacrocommon.h | 118 +++++++++++++-----
 portable/GCC/ARM_CM55_NTZ/non_secure/port.c   |  12 +-
 .../GCC/ARM_CM55_NTZ/non_secure/portmacro.h   |   2 +-
 .../ARM_CM55_NTZ/non_secure/portmacrocommon.h | 118 +++++++++++++-----
 portable/GCC/ARM_CM85/non_secure/port.c       |  12 +-
 portable/GCC/ARM_CM85/non_secure/portmacro.h  |   2 +-
 .../GCC/ARM_CM85/non_secure/portmacrocommon.h | 118 +++++++++++++-----
 portable/GCC/ARM_CM85_NTZ/non_secure/port.c   |  12 +-
 .../GCC/ARM_CM85_NTZ/non_secure/portmacro.h   |   2 +-
 .../ARM_CM85_NTZ/non_secure/portmacrocommon.h | 118 +++++++++++++-----
 portable/IAR/ARM_CM23/non_secure/port.c       |  12 +-
 portable/IAR/ARM_CM23/non_secure/portmacro.h  |   6 +-
 .../IAR/ARM_CM23/non_secure/portmacrocommon.h | 118 +++++++++++++-----
 portable/IAR/ARM_CM23_NTZ/non_secure/port.c   |  12 +-
 .../IAR/ARM_CM23_NTZ/non_secure/portmacro.h   |   6 +-
 .../ARM_CM23_NTZ/non_secure/portmacrocommon.h | 118 +++++++++++++-----
 portable/IAR/ARM_CM33/non_secure/port.c       |  12 +-
 portable/IAR/ARM_CM33/non_secure/portmacro.h  |   2 +-
 .../IAR/ARM_CM33/non_secure/portmacrocommon.h | 118 +++++++++++++-----
 portable/IAR/ARM_CM33_NTZ/non_secure/port.c   |  12 +-
 .../IAR/ARM_CM33_NTZ/non_secure/portmacro.h   |   2 +-
 .../ARM_CM33_NTZ/non_secure/portmacrocommon.h | 118 +++++++++++++-----
 portable/IAR/ARM_CM35P/non_secure/port.c      |  12 +-
 portable/IAR/ARM_CM35P/non_secure/portmacro.h |   2 +-
 .../ARM_CM35P/non_secure/portmacrocommon.h    | 118 +++++++++++++-----
 portable/IAR/ARM_CM35P_NTZ/non_secure/port.c  |  12 +-
 .../IAR/ARM_CM35P_NTZ/non_secure/portmacro.h  |   2 +-
 .../non_secure/portmacrocommon.h              | 118 +++++++++++++-----
 portable/IAR/ARM_CM55/non_secure/port.c       |  12 +-
 portable/IAR/ARM_CM55/non_secure/portmacro.h  |   2 +-
 .../IAR/ARM_CM55/non_secure/portmacrocommon.h | 118 +++++++++++++-----
 portable/IAR/ARM_CM55_NTZ/non_secure/port.c   |  12 +-
 .../IAR/ARM_CM55_NTZ/non_secure/portmacro.h   |   2 +-
 .../ARM_CM55_NTZ/non_secure/portmacrocommon.h | 118 +++++++++++++-----
 portable/IAR/ARM_CM85/non_secure/port.c       |  12 +-
 portable/IAR/ARM_CM85/non_secure/portmacro.h  |   2 +-
 .../IAR/ARM_CM85/non_secure/portmacrocommon.h | 118 +++++++++++++-----
 portable/IAR/ARM_CM85_NTZ/non_secure/port.c   |  12 +-
 .../IAR/ARM_CM85_NTZ/non_secure/portmacro.h   |   2 +-
 .../ARM_CM85_NTZ/non_secure/portmacrocommon.h | 118 +++++++++++++-----
 76 files changed, 1940 insertions(+), 890 deletions(-)

diff --git a/portable/ARMv8M/non_secure/port.c b/portable/ARMv8M/non_secure/port.c
index cab1b3668..04901015f 100644
--- a/portable/ARMv8M/non_secure/port.c
+++ b/portable/ARMv8M/non_secure/port.c
@@ -495,13 +495,13 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
  * FreeRTOS API functions are not called from interrupts that have been assigned
  * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
  */
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
 
     static uint8_t ucMaxSysCallPriority = 0;
     static uint32_t ulMaxPRIGROUPValue = 0;
     static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
 
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
 
@@ -1614,7 +1614,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
 
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
-    #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+    #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
     {
         volatile uint32_t ulOriginalPriority;
         volatile uint32_t ulImplementedPrioBits = 0;
@@ -1695,7 +1695,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          * value. */
         portNVIC_SHPR2_REG = ulOriginalPriority;
     }
-    #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+    #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
     /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
     portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
@@ -1936,7 +1936,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 }
 /*-----------------------------------------------------------*/
 
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
 
     void vPortValidateInterruptPriority( void )
     {
@@ -1994,5 +1994,5 @@ BaseType_t xPortIsInsideInterrupt( void )
         configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
     }
 
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h
index 5fd94c1c3..233ea5a57 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h
@@ -48,9 +48,9 @@
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME         "Cortex-M23"
-#define portHAS_BASEPRI       0
-#define portDONT_DISCARD      __attribute__( ( used ) )
+#define portARCH_NAME                       "Cortex-M23"
+#define portHAS_ARMV8M_MAIN_EXTENSION       0
+#define portDONT_DISCARD                    __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
 /* ARMv8-M common port configurations. */
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h
index 5fd94c1c3..233ea5a57 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h
@@ -48,9 +48,9 @@
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME         "Cortex-M23"
-#define portHAS_BASEPRI       0
-#define portDONT_DISCARD      __attribute__( ( used ) )
+#define portARCH_NAME                       "Cortex-M23"
+#define portHAS_ARMV8M_MAIN_EXTENSION       0
+#define portDONT_DISCARD                    __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
 /* ARMv8-M common port configurations. */
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h
index b9efb07dd..428d38f0a 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h
@@ -49,7 +49,7 @@
  * Architecture specifics.
  */
 #define portARCH_NAME                       "Cortex-M33"
-#define portHAS_BASEPRI                     1
+#define portHAS_ARMV8M_MAIN_EXTENSION       1
 #define portDONT_DISCARD                    __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h
index b9efb07dd..428d38f0a 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h
@@ -49,7 +49,7 @@
  * Architecture specifics.
  */
 #define portARCH_NAME                       "Cortex-M33"
-#define portHAS_BASEPRI                     1
+#define portHAS_ARMV8M_MAIN_EXTENSION       1
 #define portDONT_DISCARD                    __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM35P/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM35P/portmacro.h
index 9545737c5..6e4fe5a3d 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM35P/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM35P/portmacro.h
@@ -49,7 +49,7 @@
  * Architecture specifics.
  */
 #define portARCH_NAME                       "Cortex-M35P"
-#define portHAS_BASEPRI                     1
+#define portHAS_ARMV8M_MAIN_EXTENSION       1
 #define portDONT_DISCARD                    __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM55/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM55/portmacro.h
index 12bb5e7c4..cce022882 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM55/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM55/portmacro.h
@@ -54,7 +54,7 @@
  * Architecture specifics.
  */
 #define portARCH_NAME                       "Cortex-M55"
-#define portHAS_BASEPRI                     1
+#define portHAS_ARMV8M_MAIN_EXTENSION       1
 #define portDONT_DISCARD                    __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM85/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM85/portmacro.h
index 99f913d34..d14448927 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM85/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM85/portmacro.h
@@ -54,7 +54,7 @@
  * Architecture specifics.
  */
 #define portARCH_NAME                       "Cortex-M85"
-#define portHAS_BASEPRI                     1
+#define portHAS_ARMV8M_MAIN_EXTENSION       1
 #define portDONT_DISCARD                    __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h
index 9cf0e87fb..76ba7172e 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h
@@ -48,9 +48,9 @@
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME         "Cortex-M23"
-#define portHAS_BASEPRI       0
-#define portDONT_DISCARD      __root
+#define portARCH_NAME                       "Cortex-M23"
+#define portHAS_ARMV8M_MAIN_EXTENSION       0
+#define portDONT_DISCARD                    __root
 /*-----------------------------------------------------------*/
 
 /* ARMv8-M common port configurations. */
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h
index 9cf0e87fb..76ba7172e 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h
@@ -48,9 +48,9 @@
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME         "Cortex-M23"
-#define portHAS_BASEPRI       0
-#define portDONT_DISCARD      __root
+#define portARCH_NAME                       "Cortex-M23"
+#define portHAS_ARMV8M_MAIN_EXTENSION       0
+#define portDONT_DISCARD                    __root
 /*-----------------------------------------------------------*/
 
 /* ARMv8-M common port configurations. */
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h
index 380768fc0..145f5246e 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h
@@ -49,7 +49,7 @@
  * Architecture specifics.
  */
 #define portARCH_NAME                       "Cortex-M33"
-#define portHAS_BASEPRI                     1
+#define portHAS_ARMV8M_MAIN_EXTENSION       1
 #define portDONT_DISCARD                    __root
 /*-----------------------------------------------------------*/
 
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h
index 815dca086..445f0765a 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h
@@ -49,7 +49,7 @@
  * Architecture specifics.
  */
 #define portARCH_NAME                       "Cortex-M33"
-#define portHAS_BASEPRI                     1
+#define portHAS_ARMV8M_MAIN_EXTENSION       1
 #define portDONT_DISCARD                    __root
 /*-----------------------------------------------------------*/
 
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM35P/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM35P/portmacro.h
index 46bc4e24b..5669c1f60 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM35P/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM35P/portmacro.h
@@ -49,7 +49,7 @@
  * Architecture specifics.
  */
 #define portARCH_NAME                       "Cortex-M35P"
-#define portHAS_BASEPRI                     1
+#define portHAS_ARMV8M_MAIN_EXTENSION       1
 #define portDONT_DISCARD                    __root
 /*-----------------------------------------------------------*/
 
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM55/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM55/portmacro.h
index 7829ee618..10596e8e5 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM55/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM55/portmacro.h
@@ -54,7 +54,7 @@
  * Architecture specifics.
  */
 #define portARCH_NAME                       "Cortex-M55"
-#define portHAS_BASEPRI                     1
+#define portHAS_ARMV8M_MAIN_EXTENSION       1
 #define portDONT_DISCARD                    __root
 /*-----------------------------------------------------------*/
 
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM85/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM85/portmacro.h
index 3b51cb5ff..374150262 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM85/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM85/portmacro.h
@@ -54,7 +54,7 @@
  * Architecture specifics.
  */
 #define portARCH_NAME                       "Cortex-M85"
-#define portHAS_BASEPRI                     1
+#define portHAS_ARMV8M_MAIN_EXTENSION       1
 #define portDONT_DISCARD                    __root
 /*-----------------------------------------------------------*/
 
diff --git a/portable/ARMv8M/non_secure/portmacrocommon.h b/portable/ARMv8M/non_secure/portmacrocommon.h
index 65ac109c8..e5ffdb48b 100644
--- a/portable/ARMv8M/non_secure/portmacrocommon.h
+++ b/portable/ARMv8M/non_secure/portmacrocommon.h
@@ -81,8 +81,8 @@ typedef unsigned long    UBaseType_t;
     typedef uint32_t     TickType_t;
     #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
+    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+     * not need to be guarded with a critical section. */
     #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -307,7 +307,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * system calls.
  */
 #ifdef configASSERT
-    #if ( portHAS_BASEPRI == 1 )
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
         void vPortValidateInterruptPriority( void );
         #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
     #endif
@@ -364,49 +364,49 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-/**
- * @brief Allocate a secure context for the task.
- *
- * Tasks are not created with a secure context. Any task that is going to call
- * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
- * secure context before it calls any secure function.
- *
- * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
- */
+    /**
+     * @brief Allocate a secure context for the task.
+     *
+     * Tasks are not created with a secure context. Any task that is going to call
+     * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+     * secure context before it calls any secure function.
+     *
+     * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+     */
     #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
 
-/**
- * @brief Called when a task is deleted to delete the task's secure context,
- * if it has one.
- *
- * @param[in] pxTCB The TCB of the task being deleted.
- */
+    /**
+     * @brief Called when a task is deleted to delete the task's secure context,
+     * if it has one.
+     *
+     * @param[in] pxTCB The TCB of the task being deleted.
+     */
     #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
 #endif /* configENABLE_TRUSTZONE */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
+    /**
+     * @brief Checks whether or not the processor is privileged.
+     *
+     * @return 1 if the processor is already privileged, 0 otherwise.
+     */
     #define portIS_PRIVILEGED()      xIsPrivileged()
 
-/**
- * @brief Raise an SVC request to raise privilege.
- *
- * The SVC handler checks that the SVC was raised from a system call and only
- * then it raises the privilege. If this is called from any other place,
- * the privilege is not raised.
- */
+    /**
+     * @brief Raise an SVC request to raise privilege.
+     *
+     * The SVC handler checks that the SVC was raised from a system call and only
+     * then it raises the privilege. If this is called from any other place,
+     * the privilege is not raised.
+     */
     #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
 
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- */
+    /**
+     * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+     * register.
+     */
     #define portRESET_PRIVILEGE()    vResetPrivilege()
 #else
     #define portIS_PRIVILEGED()
@@ -435,6 +435,56 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
 /*-----------------------------------------------------------*/
 
+/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION
+ * based on whether or not Mainline extension is implemented. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+    #else
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+    #endif
+#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/**
+ * @brief Port-optimised task selection.
+ */
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+
+    /**
+     * @brief Count the number of leading zeros in a 32-bit value.
+     */
+    static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
+    {
+        uint32_t ulReturn;
+
+        __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" );
+
+        return ulReturn;
+    }
+
+    /* Check the configuration. */
+    #if ( configMAX_PRIORITIES > 32 )
+        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
+    #endif
+
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 )
+        #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection.  Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
+    #endif
+
+    /**
+     * @brief Store/clear the ready priorities in a bit map.
+     */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+    /**
+     * @brief Get the priority of the highest-priority task that is ready to execute.
+     */
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )   uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+/*-----------------------------------------------------------*/
+
 /* *INDENT-OFF* */
 #ifdef __cplusplus
     }
diff --git a/portable/GCC/ARM_CM23/non_secure/port.c b/portable/GCC/ARM_CM23/non_secure/port.c
index cab1b3668..04901015f 100644
--- a/portable/GCC/ARM_CM23/non_secure/port.c
+++ b/portable/GCC/ARM_CM23/non_secure/port.c
@@ -495,13 +495,13 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
  * FreeRTOS API functions are not called from interrupts that have been assigned
  * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
  */
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
 
     static uint8_t ucMaxSysCallPriority = 0;
     static uint32_t ulMaxPRIGROUPValue = 0;
     static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
 
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
 
@@ -1614,7 +1614,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
 
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
-    #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+    #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
     {
         volatile uint32_t ulOriginalPriority;
         volatile uint32_t ulImplementedPrioBits = 0;
@@ -1695,7 +1695,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          * value. */
         portNVIC_SHPR2_REG = ulOriginalPriority;
     }
-    #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+    #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
     /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
     portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
@@ -1936,7 +1936,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 }
 /*-----------------------------------------------------------*/
 
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
 
     void vPortValidateInterruptPriority( void )
     {
@@ -1994,5 +1994,5 @@ BaseType_t xPortIsInsideInterrupt( void )
         configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
     }
 
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM23/non_secure/portmacro.h b/portable/GCC/ARM_CM23/non_secure/portmacro.h
index 5fd94c1c3..233ea5a57 100644
--- a/portable/GCC/ARM_CM23/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM23/non_secure/portmacro.h
@@ -48,9 +48,9 @@
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME         "Cortex-M23"
-#define portHAS_BASEPRI       0
-#define portDONT_DISCARD      __attribute__( ( used ) )
+#define portARCH_NAME                       "Cortex-M23"
+#define portHAS_ARMV8M_MAIN_EXTENSION       0
+#define portDONT_DISCARD                    __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
 /* ARMv8-M common port configurations. */
diff --git a/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h
index 65ac109c8..e5ffdb48b 100644
--- a/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h
@@ -81,8 +81,8 @@ typedef unsigned long    UBaseType_t;
     typedef uint32_t     TickType_t;
     #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
+    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+     * not need to be guarded with a critical section. */
     #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -307,7 +307,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * system calls.
  */
 #ifdef configASSERT
-    #if ( portHAS_BASEPRI == 1 )
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
         void vPortValidateInterruptPriority( void );
         #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
     #endif
@@ -364,49 +364,49 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-/**
- * @brief Allocate a secure context for the task.
- *
- * Tasks are not created with a secure context. Any task that is going to call
- * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
- * secure context before it calls any secure function.
- *
- * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
- */
+    /**
+     * @brief Allocate a secure context for the task.
+     *
+     * Tasks are not created with a secure context. Any task that is going to call
+     * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+     * secure context before it calls any secure function.
+     *
+     * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+     */
     #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
 
-/**
- * @brief Called when a task is deleted to delete the task's secure context,
- * if it has one.
- *
- * @param[in] pxTCB The TCB of the task being deleted.
- */
+    /**
+     * @brief Called when a task is deleted to delete the task's secure context,
+     * if it has one.
+     *
+     * @param[in] pxTCB The TCB of the task being deleted.
+     */
     #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
 #endif /* configENABLE_TRUSTZONE */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
+    /**
+     * @brief Checks whether or not the processor is privileged.
+     *
+     * @return 1 if the processor is already privileged, 0 otherwise.
+     */
     #define portIS_PRIVILEGED()      xIsPrivileged()
 
-/**
- * @brief Raise an SVC request to raise privilege.
- *
- * The SVC handler checks that the SVC was raised from a system call and only
- * then it raises the privilege. If this is called from any other place,
- * the privilege is not raised.
- */
+    /**
+     * @brief Raise an SVC request to raise privilege.
+     *
+     * The SVC handler checks that the SVC was raised from a system call and only
+     * then it raises the privilege. If this is called from any other place,
+     * the privilege is not raised.
+     */
     #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
 
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- */
+    /**
+     * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+     * register.
+     */
     #define portRESET_PRIVILEGE()    vResetPrivilege()
 #else
     #define portIS_PRIVILEGED()
@@ -435,6 +435,56 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
 /*-----------------------------------------------------------*/
 
+/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION
+ * based on whether or not Mainline extension is implemented. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+    #else
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+    #endif
+#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/**
+ * @brief Port-optimised task selection.
+ */
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+
+    /**
+     * @brief Count the number of leading zeros in a 32-bit value.
+     */
+    static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
+    {
+        uint32_t ulReturn;
+
+        __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" );
+
+        return ulReturn;
+    }
+
+    /* Check the configuration. */
+    #if ( configMAX_PRIORITIES > 32 )
+        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
+    #endif
+
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 )
+        #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection.  Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
+    #endif
+
+    /**
+     * @brief Store/clear the ready priorities in a bit map.
+     */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+    /**
+     * @brief Get the priority of the highest-priority task that is ready to execute.
+     */
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )   uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+/*-----------------------------------------------------------*/
+
 /* *INDENT-OFF* */
 #ifdef __cplusplus
     }
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
index cab1b3668..04901015f 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
@@ -495,13 +495,13 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
  * FreeRTOS API functions are not called from interrupts that have been assigned
  * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
  */
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
 
     static uint8_t ucMaxSysCallPriority = 0;
     static uint32_t ulMaxPRIGROUPValue = 0;
     static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
 
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
 
@@ -1614,7 +1614,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
 
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
-    #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+    #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
     {
         volatile uint32_t ulOriginalPriority;
         volatile uint32_t ulImplementedPrioBits = 0;
@@ -1695,7 +1695,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          * value. */
         portNVIC_SHPR2_REG = ulOriginalPriority;
     }
-    #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+    #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
     /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
     portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
@@ -1936,7 +1936,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 }
 /*-----------------------------------------------------------*/
 
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
 
     void vPortValidateInterruptPriority( void )
     {
@@ -1994,5 +1994,5 @@ BaseType_t xPortIsInsideInterrupt( void )
         configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
     }
 
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h b/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h
index 5fd94c1c3..233ea5a57 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h
@@ -48,9 +48,9 @@
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME         "Cortex-M23"
-#define portHAS_BASEPRI       0
-#define portDONT_DISCARD      __attribute__( ( used ) )
+#define portARCH_NAME                       "Cortex-M23"
+#define portHAS_ARMV8M_MAIN_EXTENSION       0
+#define portDONT_DISCARD                    __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
 /* ARMv8-M common port configurations. */
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h
index 65ac109c8..e5ffdb48b 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h
@@ -81,8 +81,8 @@ typedef unsigned long    UBaseType_t;
     typedef uint32_t     TickType_t;
     #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
+    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+     * not need to be guarded with a critical section. */
     #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -307,7 +307,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * system calls.
  */
 #ifdef configASSERT
-    #if ( portHAS_BASEPRI == 1 )
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
         void vPortValidateInterruptPriority( void );
         #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
     #endif
@@ -364,49 +364,49 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-/**
- * @brief Allocate a secure context for the task.
- *
- * Tasks are not created with a secure context. Any task that is going to call
- * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
- * secure context before it calls any secure function.
- *
- * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
- */
+    /**
+     * @brief Allocate a secure context for the task.
+     *
+     * Tasks are not created with a secure context. Any task that is going to call
+     * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+     * secure context before it calls any secure function.
+     *
+     * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+     */
     #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
 
-/**
- * @brief Called when a task is deleted to delete the task's secure context,
- * if it has one.
- *
- * @param[in] pxTCB The TCB of the task being deleted.
- */
+    /**
+     * @brief Called when a task is deleted to delete the task's secure context,
+     * if it has one.
+     *
+     * @param[in] pxTCB The TCB of the task being deleted.
+     */
     #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
 #endif /* configENABLE_TRUSTZONE */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
+    /**
+     * @brief Checks whether or not the processor is privileged.
+     *
+     * @return 1 if the processor is already privileged, 0 otherwise.
+     */
     #define portIS_PRIVILEGED()      xIsPrivileged()
 
-/**
- * @brief Raise an SVC request to raise privilege.
- *
- * The SVC handler checks that the SVC was raised from a system call and only
- * then it raises the privilege. If this is called from any other place,
- * the privilege is not raised.
- */
+    /**
+     * @brief Raise an SVC request to raise privilege.
+     *
+     * The SVC handler checks that the SVC was raised from a system call and only
+     * then it raises the privilege. If this is called from any other place,
+     * the privilege is not raised.
+     */
     #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
 
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- */
+    /**
+     * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+     * register.
+     */
     #define portRESET_PRIVILEGE()    vResetPrivilege()
 #else
     #define portIS_PRIVILEGED()
@@ -435,6 +435,56 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
 /*-----------------------------------------------------------*/
 
+/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION
+ * based on whether or not Mainline extension is implemented. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+    #else
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+    #endif
+#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/**
+ * @brief Port-optimised task selection.
+ */
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+
+    /**
+     * @brief Count the number of leading zeros in a 32-bit value.
+     */
+    static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
+    {
+        uint32_t ulReturn;
+
+        __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" );
+
+        return ulReturn;
+    }
+
+    /* Check the configuration. */
+    #if ( configMAX_PRIORITIES > 32 )
+        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
+    #endif
+
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 )
+        #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection.  Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
+    #endif
+
+    /**
+     * @brief Store/clear the ready priorities in a bit map.
+     */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+    /**
+     * @brief Get the priority of the highest-priority task that is ready to execute.
+     */
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )   uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+/*-----------------------------------------------------------*/
+
 /* *INDENT-OFF* */
 #ifdef __cplusplus
     }
diff --git a/portable/GCC/ARM_CM33/non_secure/port.c b/portable/GCC/ARM_CM33/non_secure/port.c
index cab1b3668..04901015f 100644
--- a/portable/GCC/ARM_CM33/non_secure/port.c
+++ b/portable/GCC/ARM_CM33/non_secure/port.c
@@ -495,13 +495,13 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
  * FreeRTOS API functions are not called from interrupts that have been assigned
  * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
  */
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
 
     static uint8_t ucMaxSysCallPriority = 0;
     static uint32_t ulMaxPRIGROUPValue = 0;
     static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
 
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
 
@@ -1614,7 +1614,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
 
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
-    #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+    #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
     {
         volatile uint32_t ulOriginalPriority;
         volatile uint32_t ulImplementedPrioBits = 0;
@@ -1695,7 +1695,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          * value. */
         portNVIC_SHPR2_REG = ulOriginalPriority;
     }
-    #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+    #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
     /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
     portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
@@ -1936,7 +1936,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 }
 /*-----------------------------------------------------------*/
 
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
 
     void vPortValidateInterruptPriority( void )
     {
@@ -1994,5 +1994,5 @@ BaseType_t xPortIsInsideInterrupt( void )
         configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
     }
 
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM33/non_secure/portmacro.h b/portable/GCC/ARM_CM33/non_secure/portmacro.h
index b9efb07dd..428d38f0a 100644
--- a/portable/GCC/ARM_CM33/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM33/non_secure/portmacro.h
@@ -49,7 +49,7 @@
  * Architecture specifics.
  */
 #define portARCH_NAME                       "Cortex-M33"
-#define portHAS_BASEPRI                     1
+#define portHAS_ARMV8M_MAIN_EXTENSION       1
 #define portDONT_DISCARD                    __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h
index 65ac109c8..e5ffdb48b 100644
--- a/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h
@@ -81,8 +81,8 @@ typedef unsigned long    UBaseType_t;
     typedef uint32_t     TickType_t;
     #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
+    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+     * not need to be guarded with a critical section. */
     #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -307,7 +307,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * system calls.
  */
 #ifdef configASSERT
-    #if ( portHAS_BASEPRI == 1 )
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
         void vPortValidateInterruptPriority( void );
         #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
     #endif
@@ -364,49 +364,49 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-/**
- * @brief Allocate a secure context for the task.
- *
- * Tasks are not created with a secure context. Any task that is going to call
- * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
- * secure context before it calls any secure function.
- *
- * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
- */
+    /**
+     * @brief Allocate a secure context for the task.
+     *
+     * Tasks are not created with a secure context. Any task that is going to call
+     * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+     * secure context before it calls any secure function.
+     *
+     * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+     */
     #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
 
-/**
- * @brief Called when a task is deleted to delete the task's secure context,
- * if it has one.
- *
- * @param[in] pxTCB The TCB of the task being deleted.
- */
+    /**
+     * @brief Called when a task is deleted to delete the task's secure context,
+     * if it has one.
+     *
+     * @param[in] pxTCB The TCB of the task being deleted.
+     */
     #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
 #endif /* configENABLE_TRUSTZONE */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
+    /**
+     * @brief Checks whether or not the processor is privileged.
+     *
+     * @return 1 if the processor is already privileged, 0 otherwise.
+     */
     #define portIS_PRIVILEGED()      xIsPrivileged()
 
-/**
- * @brief Raise an SVC request to raise privilege.
- *
- * The SVC handler checks that the SVC was raised from a system call and only
- * then it raises the privilege. If this is called from any other place,
- * the privilege is not raised.
- */
+    /**
+     * @brief Raise an SVC request to raise privilege.
+     *
+     * The SVC handler checks that the SVC was raised from a system call and only
+     * then it raises the privilege. If this is called from any other place,
+     * the privilege is not raised.
+     */
     #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
 
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- */
+    /**
+     * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+     * register.
+     */
     #define portRESET_PRIVILEGE()    vResetPrivilege()
 #else
     #define portIS_PRIVILEGED()
@@ -435,6 +435,56 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
 /*-----------------------------------------------------------*/
 
+/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION
+ * based on whether or not Mainline extension is implemented. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+    #else
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+    #endif
+#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/**
+ * @brief Port-optimised task selection.
+ */
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+
+    /**
+     * @brief Count the number of leading zeros in a 32-bit value.
+     */
+    static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
+    {
+        uint32_t ulReturn;
+
+        __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" );
+
+        return ulReturn;
+    }
+
+    /* Check the configuration. */
+    #if ( configMAX_PRIORITIES > 32 )
+        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
+    #endif
+
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 )
+        #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection.  Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
+    #endif
+
+    /**
+     * @brief Store/clear the ready priorities in a bit map.
+     */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+    /**
+     * @brief Get the priority of the highest-priority task that is ready to execute.
+     */
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )   uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+/*-----------------------------------------------------------*/
+
 /* *INDENT-OFF* */
 #ifdef __cplusplus
     }
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
index cab1b3668..04901015f 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
@@ -495,13 +495,13 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
  * FreeRTOS API functions are not called from interrupts that have been assigned
  * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
  */
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
 
     static uint8_t ucMaxSysCallPriority = 0;
     static uint32_t ulMaxPRIGROUPValue = 0;
     static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
 
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
 
@@ -1614,7 +1614,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
 
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
-    #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+    #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
     {
         volatile uint32_t ulOriginalPriority;
         volatile uint32_t ulImplementedPrioBits = 0;
@@ -1695,7 +1695,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          * value. */
         portNVIC_SHPR2_REG = ulOriginalPriority;
     }
-    #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+    #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
     /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
     portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
@@ -1936,7 +1936,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 }
 /*-----------------------------------------------------------*/
 
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
 
     void vPortValidateInterruptPriority( void )
     {
@@ -1994,5 +1994,5 @@ BaseType_t xPortIsInsideInterrupt( void )
         configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
     }
 
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h b/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h
index b9efb07dd..428d38f0a 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h
@@ -49,7 +49,7 @@
  * Architecture specifics.
  */
 #define portARCH_NAME                       "Cortex-M33"
-#define portHAS_BASEPRI                     1
+#define portHAS_ARMV8M_MAIN_EXTENSION       1
 #define portDONT_DISCARD                    __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h
index 65ac109c8..e5ffdb48b 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h
@@ -81,8 +81,8 @@ typedef unsigned long    UBaseType_t;
     typedef uint32_t     TickType_t;
     #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
+    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+     * not need to be guarded with a critical section. */
     #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -307,7 +307,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * system calls.
  */
 #ifdef configASSERT
-    #if ( portHAS_BASEPRI == 1 )
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
         void vPortValidateInterruptPriority( void );
         #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
     #endif
@@ -364,49 +364,49 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-/**
- * @brief Allocate a secure context for the task.
- *
- * Tasks are not created with a secure context. Any task that is going to call
- * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
- * secure context before it calls any secure function.
- *
- * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
- */
+    /**
+     * @brief Allocate a secure context for the task.
+     *
+     * Tasks are not created with a secure context. Any task that is going to call
+     * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+     * secure context before it calls any secure function.
+     *
+     * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+     */
     #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
 
-/**
- * @brief Called when a task is deleted to delete the task's secure context,
- * if it has one.
- *
- * @param[in] pxTCB The TCB of the task being deleted.
- */
+    /**
+     * @brief Called when a task is deleted to delete the task's secure context,
+     * if it has one.
+     *
+     * @param[in] pxTCB The TCB of the task being deleted.
+     */
     #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
 #endif /* configENABLE_TRUSTZONE */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
+    /**
+     * @brief Checks whether or not the processor is privileged.
+     *
+     * @return 1 if the processor is already privileged, 0 otherwise.
+     */
     #define portIS_PRIVILEGED()      xIsPrivileged()
 
-/**
- * @brief Raise an SVC request to raise privilege.
- *
- * The SVC handler checks that the SVC was raised from a system call and only
- * then it raises the privilege. If this is called from any other place,
- * the privilege is not raised.
- */
+    /**
+     * @brief Raise an SVC request to raise privilege.
+     *
+     * The SVC handler checks that the SVC was raised from a system call and only
+     * then it raises the privilege. If this is called from any other place,
+     * the privilege is not raised.
+     */
     #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
 
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- */
+    /**
+     * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+     * register.
+     */
     #define portRESET_PRIVILEGE()    vResetPrivilege()
 #else
     #define portIS_PRIVILEGED()
@@ -435,6 +435,56 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
 /*-----------------------------------------------------------*/
 
+/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION
+ * based on whether or not Mainline extension is implemented. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+    #else
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+    #endif
+#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/**
+ * @brief Port-optimised task selection.
+ */
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+
+    /**
+     * @brief Count the number of leading zeros in a 32-bit value.
+     */
+    static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
+    {
+        uint32_t ulReturn;
+
+        __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" );
+
+        return ulReturn;
+    }
+
+    /* Check the configuration. */
+    #if ( configMAX_PRIORITIES > 32 )
+        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
+    #endif
+
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 )
+        #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection.  Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
+    #endif
+
+    /**
+     * @brief Store/clear the ready priorities in a bit map.
+     */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+    /**
+     * @brief Get the priority of the highest-priority task that is ready to execute.
+     */
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )   uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+/*-----------------------------------------------------------*/
+
 /* *INDENT-OFF* */
 #ifdef __cplusplus
     }
diff --git a/portable/GCC/ARM_CM35P/non_secure/port.c b/portable/GCC/ARM_CM35P/non_secure/port.c
index cab1b3668..04901015f 100644
--- a/portable/GCC/ARM_CM35P/non_secure/port.c
+++ b/portable/GCC/ARM_CM35P/non_secure/port.c
@@ -495,13 +495,13 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
  * FreeRTOS API functions are not called from interrupts that have been assigned
  * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
  */
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
 
     static uint8_t ucMaxSysCallPriority = 0;
     static uint32_t ulMaxPRIGROUPValue = 0;
     static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
 
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
 
@@ -1614,7 +1614,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
 
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
-    #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+    #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
     {
         volatile uint32_t ulOriginalPriority;
         volatile uint32_t ulImplementedPrioBits = 0;
@@ -1695,7 +1695,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          * value. */
         portNVIC_SHPR2_REG = ulOriginalPriority;
     }
-    #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+    #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
     /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
     portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
@@ -1936,7 +1936,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 }
 /*-----------------------------------------------------------*/
 
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
 
     void vPortValidateInterruptPriority( void )
     {
@@ -1994,5 +1994,5 @@ BaseType_t xPortIsInsideInterrupt( void )
         configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
     }
 
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM35P/non_secure/portmacro.h b/portable/GCC/ARM_CM35P/non_secure/portmacro.h
index 9545737c5..6e4fe5a3d 100644
--- a/portable/GCC/ARM_CM35P/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM35P/non_secure/portmacro.h
@@ -49,7 +49,7 @@
  * Architecture specifics.
  */
 #define portARCH_NAME                       "Cortex-M35P"
-#define portHAS_BASEPRI                     1
+#define portHAS_ARMV8M_MAIN_EXTENSION       1
 #define portDONT_DISCARD                    __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h
index 65ac109c8..e5ffdb48b 100644
--- a/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h
@@ -81,8 +81,8 @@ typedef unsigned long    UBaseType_t;
     typedef uint32_t     TickType_t;
     #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
+    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+     * not need to be guarded with a critical section. */
     #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -307,7 +307,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * system calls.
  */
 #ifdef configASSERT
-    #if ( portHAS_BASEPRI == 1 )
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
         void vPortValidateInterruptPriority( void );
         #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
     #endif
@@ -364,49 +364,49 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-/**
- * @brief Allocate a secure context for the task.
- *
- * Tasks are not created with a secure context. Any task that is going to call
- * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
- * secure context before it calls any secure function.
- *
- * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
- */
+    /**
+     * @brief Allocate a secure context for the task.
+     *
+     * Tasks are not created with a secure context. Any task that is going to call
+     * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+     * secure context before it calls any secure function.
+     *
+     * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+     */
     #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
 
-/**
- * @brief Called when a task is deleted to delete the task's secure context,
- * if it has one.
- *
- * @param[in] pxTCB The TCB of the task being deleted.
- */
+    /**
+     * @brief Called when a task is deleted to delete the task's secure context,
+     * if it has one.
+     *
+     * @param[in] pxTCB The TCB of the task being deleted.
+     */
     #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
 #endif /* configENABLE_TRUSTZONE */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
+    /**
+     * @brief Checks whether or not the processor is privileged.
+     *
+     * @return 1 if the processor is already privileged, 0 otherwise.
+     */
     #define portIS_PRIVILEGED()      xIsPrivileged()
 
-/**
- * @brief Raise an SVC request to raise privilege.
- *
- * The SVC handler checks that the SVC was raised from a system call and only
- * then it raises the privilege. If this is called from any other place,
- * the privilege is not raised.
- */
+    /**
+     * @brief Raise an SVC request to raise privilege.
+     *
+     * The SVC handler checks that the SVC was raised from a system call and only
+     * then it raises the privilege. If this is called from any other place,
+     * the privilege is not raised.
+     */
     #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
 
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- */
+    /**
+     * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+     * register.
+     */
     #define portRESET_PRIVILEGE()    vResetPrivilege()
 #else
     #define portIS_PRIVILEGED()
@@ -435,6 +435,56 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
 /*-----------------------------------------------------------*/
 
+/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION
+ * based on whether or not Mainline extension is implemented. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+    #else
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+    #endif
+#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/**
+ * @brief Port-optimised task selection.
+ */
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+
+    /**
+     * @brief Count the number of leading zeros in a 32-bit value.
+     */
+    static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
+    {
+        uint32_t ulReturn;
+
+        __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" );
+
+        return ulReturn;
+    }
+
+    /* Check the configuration. */
+    #if ( configMAX_PRIORITIES > 32 )
+        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
+    #endif
+
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 )
+        #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection.  Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
+    #endif
+
+    /**
+     * @brief Store/clear the ready priorities in a bit map.
+     */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+    /**
+     * @brief Get the priority of the highest-priority task that is ready to execute.
+     */
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )   uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+/*-----------------------------------------------------------*/
+
 /* *INDENT-OFF* */
 #ifdef __cplusplus
     }
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c b/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
index cab1b3668..04901015f 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
@@ -495,13 +495,13 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
  * FreeRTOS API functions are not called from interrupts that have been assigned
  * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
  */
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
 
     static uint8_t ucMaxSysCallPriority = 0;
     static uint32_t ulMaxPRIGROUPValue = 0;
     static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
 
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
 
@@ -1614,7 +1614,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
 
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
-    #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+    #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
     {
         volatile uint32_t ulOriginalPriority;
         volatile uint32_t ulImplementedPrioBits = 0;
@@ -1695,7 +1695,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          * value. */
         portNVIC_SHPR2_REG = ulOriginalPriority;
     }
-    #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+    #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
     /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
     portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
@@ -1936,7 +1936,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 }
 /*-----------------------------------------------------------*/
 
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
 
     void vPortValidateInterruptPriority( void )
     {
@@ -1994,5 +1994,5 @@ BaseType_t xPortIsInsideInterrupt( void )
         configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
     }
 
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacro.h b/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacro.h
index 9545737c5..6e4fe5a3d 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacro.h
@@ -49,7 +49,7 @@
  * Architecture specifics.
  */
 #define portARCH_NAME                       "Cortex-M35P"
-#define portHAS_BASEPRI                     1
+#define portHAS_ARMV8M_MAIN_EXTENSION       1
 #define portDONT_DISCARD                    __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
index 65ac109c8..e5ffdb48b 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
@@ -81,8 +81,8 @@ typedef unsigned long    UBaseType_t;
     typedef uint32_t     TickType_t;
     #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
+    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+     * not need to be guarded with a critical section. */
     #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -307,7 +307,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * system calls.
  */
 #ifdef configASSERT
-    #if ( portHAS_BASEPRI == 1 )
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
         void vPortValidateInterruptPriority( void );
         #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
     #endif
@@ -364,49 +364,49 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-/**
- * @brief Allocate a secure context for the task.
- *
- * Tasks are not created with a secure context. Any task that is going to call
- * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
- * secure context before it calls any secure function.
- *
- * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
- */
+    /**
+     * @brief Allocate a secure context for the task.
+     *
+     * Tasks are not created with a secure context. Any task that is going to call
+     * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+     * secure context before it calls any secure function.
+     *
+     * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+     */
     #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
 
-/**
- * @brief Called when a task is deleted to delete the task's secure context,
- * if it has one.
- *
- * @param[in] pxTCB The TCB of the task being deleted.
- */
+    /**
+     * @brief Called when a task is deleted to delete the task's secure context,
+     * if it has one.
+     *
+     * @param[in] pxTCB The TCB of the task being deleted.
+     */
     #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
 #endif /* configENABLE_TRUSTZONE */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
+    /**
+     * @brief Checks whether or not the processor is privileged.
+     *
+     * @return 1 if the processor is already privileged, 0 otherwise.
+     */
     #define portIS_PRIVILEGED()      xIsPrivileged()
 
-/**
- * @brief Raise an SVC request to raise privilege.
- *
- * The SVC handler checks that the SVC was raised from a system call and only
- * then it raises the privilege. If this is called from any other place,
- * the privilege is not raised.
- */
+    /**
+     * @brief Raise an SVC request to raise privilege.
+     *
+     * The SVC handler checks that the SVC was raised from a system call and only
+     * then it raises the privilege. If this is called from any other place,
+     * the privilege is not raised.
+     */
     #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
 
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- */
+    /**
+     * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+     * register.
+     */
     #define portRESET_PRIVILEGE()    vResetPrivilege()
 #else
     #define portIS_PRIVILEGED()
@@ -435,6 +435,56 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
 /*-----------------------------------------------------------*/
 
+/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION
+ * based on whether or not Mainline extension is implemented. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+    #else
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+    #endif
+#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/**
+ * @brief Port-optimised task selection.
+ */
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+
+    /**
+     * @brief Count the number of leading zeros in a 32-bit value.
+     */
+    static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
+    {
+        uint32_t ulReturn;
+
+        __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" );
+
+        return ulReturn;
+    }
+
+    /* Check the configuration. */
+    #if ( configMAX_PRIORITIES > 32 )
+        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
+    #endif
+
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 )
+        #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection.  Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
+    #endif
+
+    /**
+     * @brief Store/clear the ready priorities in a bit map.
+     */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+    /**
+     * @brief Get the priority of the highest-priority task that is ready to execute.
+     */
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )   uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+/*-----------------------------------------------------------*/
+
 /* *INDENT-OFF* */
 #ifdef __cplusplus
     }
diff --git a/portable/GCC/ARM_CM55/non_secure/port.c b/portable/GCC/ARM_CM55/non_secure/port.c
index cab1b3668..04901015f 100644
--- a/portable/GCC/ARM_CM55/non_secure/port.c
+++ b/portable/GCC/ARM_CM55/non_secure/port.c
@@ -495,13 +495,13 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
  * FreeRTOS API functions are not called from interrupts that have been assigned
  * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
  */
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
 
     static uint8_t ucMaxSysCallPriority = 0;
     static uint32_t ulMaxPRIGROUPValue = 0;
     static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
 
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
 
@@ -1614,7 +1614,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
 
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
-    #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+    #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
     {
         volatile uint32_t ulOriginalPriority;
         volatile uint32_t ulImplementedPrioBits = 0;
@@ -1695,7 +1695,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          * value. */
         portNVIC_SHPR2_REG = ulOriginalPriority;
     }
-    #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+    #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
     /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
     portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
@@ -1936,7 +1936,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 }
 /*-----------------------------------------------------------*/
 
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
 
     void vPortValidateInterruptPriority( void )
     {
@@ -1994,5 +1994,5 @@ BaseType_t xPortIsInsideInterrupt( void )
         configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
     }
 
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM55/non_secure/portmacro.h b/portable/GCC/ARM_CM55/non_secure/portmacro.h
index 12bb5e7c4..cce022882 100644
--- a/portable/GCC/ARM_CM55/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM55/non_secure/portmacro.h
@@ -54,7 +54,7 @@
  * Architecture specifics.
  */
 #define portARCH_NAME                       "Cortex-M55"
-#define portHAS_BASEPRI                     1
+#define portHAS_ARMV8M_MAIN_EXTENSION       1
 #define portDONT_DISCARD                    __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h
index 65ac109c8..e5ffdb48b 100644
--- a/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h
@@ -81,8 +81,8 @@ typedef unsigned long    UBaseType_t;
     typedef uint32_t     TickType_t;
     #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
+    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+     * not need to be guarded with a critical section. */
     #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -307,7 +307,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * system calls.
  */
 #ifdef configASSERT
-    #if ( portHAS_BASEPRI == 1 )
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
         void vPortValidateInterruptPriority( void );
         #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
     #endif
@@ -364,49 +364,49 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-/**
- * @brief Allocate a secure context for the task.
- *
- * Tasks are not created with a secure context. Any task that is going to call
- * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
- * secure context before it calls any secure function.
- *
- * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
- */
+    /**
+     * @brief Allocate a secure context for the task.
+     *
+     * Tasks are not created with a secure context. Any task that is going to call
+     * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+     * secure context before it calls any secure function.
+     *
+     * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+     */
     #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
 
-/**
- * @brief Called when a task is deleted to delete the task's secure context,
- * if it has one.
- *
- * @param[in] pxTCB The TCB of the task being deleted.
- */
+    /**
+     * @brief Called when a task is deleted to delete the task's secure context,
+     * if it has one.
+     *
+     * @param[in] pxTCB The TCB of the task being deleted.
+     */
     #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
 #endif /* configENABLE_TRUSTZONE */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
+    /**
+     * @brief Checks whether or not the processor is privileged.
+     *
+     * @return 1 if the processor is already privileged, 0 otherwise.
+     */
     #define portIS_PRIVILEGED()      xIsPrivileged()
 
-/**
- * @brief Raise an SVC request to raise privilege.
- *
- * The SVC handler checks that the SVC was raised from a system call and only
- * then it raises the privilege. If this is called from any other place,
- * the privilege is not raised.
- */
+    /**
+     * @brief Raise an SVC request to raise privilege.
+     *
+     * The SVC handler checks that the SVC was raised from a system call and only
+     * then it raises the privilege. If this is called from any other place,
+     * the privilege is not raised.
+     */
     #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
 
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- */
+    /**
+     * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+     * register.
+     */
     #define portRESET_PRIVILEGE()    vResetPrivilege()
 #else
     #define portIS_PRIVILEGED()
@@ -435,6 +435,56 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
 /*-----------------------------------------------------------*/
 
+/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION
+ * based on whether or not Mainline extension is implemented. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+    #else
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+    #endif
+#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/**
+ * @brief Port-optimised task selection.
+ */
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+
+    /**
+     * @brief Count the number of leading zeros in a 32-bit value.
+     */
+    static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
+    {
+        uint32_t ulReturn;
+
+        __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" );
+
+        return ulReturn;
+    }
+
+    /* Check the configuration. */
+    #if ( configMAX_PRIORITIES > 32 )
+        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
+    #endif
+
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 )
+        #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection.  Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
+    #endif
+
+    /**
+     * @brief Store/clear the ready priorities in a bit map.
+     */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+    /**
+     * @brief Get the priority of the highest-priority task that is ready to execute.
+     */
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )   uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+/*-----------------------------------------------------------*/
+
 /* *INDENT-OFF* */
 #ifdef __cplusplus
     }
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/port.c b/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
index cab1b3668..04901015f 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
@@ -495,13 +495,13 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
  * FreeRTOS API functions are not called from interrupts that have been assigned
  * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
  */
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
 
     static uint8_t ucMaxSysCallPriority = 0;
     static uint32_t ulMaxPRIGROUPValue = 0;
     static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
 
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
 
@@ -1614,7 +1614,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
 
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
-    #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+    #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
     {
         volatile uint32_t ulOriginalPriority;
         volatile uint32_t ulImplementedPrioBits = 0;
@@ -1695,7 +1695,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          * value. */
         portNVIC_SHPR2_REG = ulOriginalPriority;
     }
-    #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+    #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
     /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
     portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
@@ -1936,7 +1936,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 }
 /*-----------------------------------------------------------*/
 
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
 
     void vPortValidateInterruptPriority( void )
     {
@@ -1994,5 +1994,5 @@ BaseType_t xPortIsInsideInterrupt( void )
         configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
     }
 
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/portmacro.h b/portable/GCC/ARM_CM55_NTZ/non_secure/portmacro.h
index 12bb5e7c4..cce022882 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/portmacro.h
@@ -54,7 +54,7 @@
  * Architecture specifics.
  */
 #define portARCH_NAME                       "Cortex-M55"
-#define portHAS_BASEPRI                     1
+#define portHAS_ARMV8M_MAIN_EXTENSION       1
 #define portDONT_DISCARD                    __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h
index 65ac109c8..e5ffdb48b 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h
@@ -81,8 +81,8 @@ typedef unsigned long    UBaseType_t;
     typedef uint32_t     TickType_t;
     #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
+    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+     * not need to be guarded with a critical section. */
     #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -307,7 +307,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * system calls.
  */
 #ifdef configASSERT
-    #if ( portHAS_BASEPRI == 1 )
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
         void vPortValidateInterruptPriority( void );
         #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
     #endif
@@ -364,49 +364,49 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-/**
- * @brief Allocate a secure context for the task.
- *
- * Tasks are not created with a secure context. Any task that is going to call
- * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
- * secure context before it calls any secure function.
- *
- * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
- */
+    /**
+     * @brief Allocate a secure context for the task.
+     *
+     * Tasks are not created with a secure context. Any task that is going to call
+     * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+     * secure context before it calls any secure function.
+     *
+     * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+     */
     #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
 
-/**
- * @brief Called when a task is deleted to delete the task's secure context,
- * if it has one.
- *
- * @param[in] pxTCB The TCB of the task being deleted.
- */
+    /**
+     * @brief Called when a task is deleted to delete the task's secure context,
+     * if it has one.
+     *
+     * @param[in] pxTCB The TCB of the task being deleted.
+     */
     #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
 #endif /* configENABLE_TRUSTZONE */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
+    /**
+     * @brief Checks whether or not the processor is privileged.
+     *
+     * @return 1 if the processor is already privileged, 0 otherwise.
+     */
     #define portIS_PRIVILEGED()      xIsPrivileged()
 
-/**
- * @brief Raise an SVC request to raise privilege.
- *
- * The SVC handler checks that the SVC was raised from a system call and only
- * then it raises the privilege. If this is called from any other place,
- * the privilege is not raised.
- */
+    /**
+     * @brief Raise an SVC request to raise privilege.
+     *
+     * The SVC handler checks that the SVC was raised from a system call and only
+     * then it raises the privilege. If this is called from any other place,
+     * the privilege is not raised.
+     */
     #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
 
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- */
+    /**
+     * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+     * register.
+     */
     #define portRESET_PRIVILEGE()    vResetPrivilege()
 #else
     #define portIS_PRIVILEGED()
@@ -435,6 +435,56 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
 /*-----------------------------------------------------------*/
 
+/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION
+ * based on whether or not Mainline extension is implemented. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+    #else
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+    #endif
+#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/**
+ * @brief Port-optimised task selection.
+ */
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+
+    /**
+     * @brief Count the number of leading zeros in a 32-bit value.
+     */
+    static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
+    {
+        uint32_t ulReturn;
+
+        __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" );
+
+        return ulReturn;
+    }
+
+    /* Check the configuration. */
+    #if ( configMAX_PRIORITIES > 32 )
+        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
+    #endif
+
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 )
+        #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection.  Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
+    #endif
+
+    /**
+     * @brief Store/clear the ready priorities in a bit map.
+     */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+    /**
+     * @brief Get the priority of the highest-priority task that is ready to execute.
+     */
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )   uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+/*-----------------------------------------------------------*/
+
 /* *INDENT-OFF* */
 #ifdef __cplusplus
     }
diff --git a/portable/GCC/ARM_CM85/non_secure/port.c b/portable/GCC/ARM_CM85/non_secure/port.c
index cab1b3668..04901015f 100644
--- a/portable/GCC/ARM_CM85/non_secure/port.c
+++ b/portable/GCC/ARM_CM85/non_secure/port.c
@@ -495,13 +495,13 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
  * FreeRTOS API functions are not called from interrupts that have been assigned
  * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
  */
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
 
     static uint8_t ucMaxSysCallPriority = 0;
     static uint32_t ulMaxPRIGROUPValue = 0;
     static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
 
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
 
@@ -1614,7 +1614,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
 
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
-    #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+    #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
     {
         volatile uint32_t ulOriginalPriority;
         volatile uint32_t ulImplementedPrioBits = 0;
@@ -1695,7 +1695,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          * value. */
         portNVIC_SHPR2_REG = ulOriginalPriority;
     }
-    #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+    #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
     /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
     portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
@@ -1936,7 +1936,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 }
 /*-----------------------------------------------------------*/
 
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
 
     void vPortValidateInterruptPriority( void )
     {
@@ -1994,5 +1994,5 @@ BaseType_t xPortIsInsideInterrupt( void )
         configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
     }
 
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM85/non_secure/portmacro.h b/portable/GCC/ARM_CM85/non_secure/portmacro.h
index 99f913d34..d14448927 100644
--- a/portable/GCC/ARM_CM85/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM85/non_secure/portmacro.h
@@ -54,7 +54,7 @@
  * Architecture specifics.
  */
 #define portARCH_NAME                       "Cortex-M85"
-#define portHAS_BASEPRI                     1
+#define portHAS_ARMV8M_MAIN_EXTENSION       1
 #define portDONT_DISCARD                    __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h
index 65ac109c8..e5ffdb48b 100644
--- a/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h
@@ -81,8 +81,8 @@ typedef unsigned long    UBaseType_t;
     typedef uint32_t     TickType_t;
     #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
+    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+     * not need to be guarded with a critical section. */
     #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -307,7 +307,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * system calls.
  */
 #ifdef configASSERT
-    #if ( portHAS_BASEPRI == 1 )
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
         void vPortValidateInterruptPriority( void );
         #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
     #endif
@@ -364,49 +364,49 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-/**
- * @brief Allocate a secure context for the task.
- *
- * Tasks are not created with a secure context. Any task that is going to call
- * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
- * secure context before it calls any secure function.
- *
- * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
- */
+    /**
+     * @brief Allocate a secure context for the task.
+     *
+     * Tasks are not created with a secure context. Any task that is going to call
+     * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+     * secure context before it calls any secure function.
+     *
+     * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+     */
     #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
 
-/**
- * @brief Called when a task is deleted to delete the task's secure context,
- * if it has one.
- *
- * @param[in] pxTCB The TCB of the task being deleted.
- */
+    /**
+     * @brief Called when a task is deleted to delete the task's secure context,
+     * if it has one.
+     *
+     * @param[in] pxTCB The TCB of the task being deleted.
+     */
     #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
 #endif /* configENABLE_TRUSTZONE */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
+    /**
+     * @brief Checks whether or not the processor is privileged.
+     *
+     * @return 1 if the processor is already privileged, 0 otherwise.
+     */
     #define portIS_PRIVILEGED()      xIsPrivileged()
 
-/**
- * @brief Raise an SVC request to raise privilege.
- *
- * The SVC handler checks that the SVC was raised from a system call and only
- * then it raises the privilege. If this is called from any other place,
- * the privilege is not raised.
- */
+    /**
+     * @brief Raise an SVC request to raise privilege.
+     *
+     * The SVC handler checks that the SVC was raised from a system call and only
+     * then it raises the privilege. If this is called from any other place,
+     * the privilege is not raised.
+     */
     #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
 
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- */
+    /**
+     * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+     * register.
+     */
     #define portRESET_PRIVILEGE()    vResetPrivilege()
 #else
     #define portIS_PRIVILEGED()
@@ -435,6 +435,56 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
 /*-----------------------------------------------------------*/
 
+/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION
+ * based on whether or not Mainline extension is implemented. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+    #else
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+    #endif
+#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/**
+ * @brief Port-optimised task selection.
+ */
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+
+    /**
+     * @brief Count the number of leading zeros in a 32-bit value.
+     */
+    static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
+    {
+        uint32_t ulReturn;
+
+        __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" );
+
+        return ulReturn;
+    }
+
+    /* Check the configuration. */
+    #if ( configMAX_PRIORITIES > 32 )
+        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
+    #endif
+
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 )
+        #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection.  Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
+    #endif
+
+    /**
+     * @brief Store/clear the ready priorities in a bit map.
+     */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+    /**
+     * @brief Get the priority of the highest-priority task that is ready to execute.
+     */
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )   uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+/*-----------------------------------------------------------*/
+
 /* *INDENT-OFF* */
 #ifdef __cplusplus
     }
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/port.c b/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
index cab1b3668..04901015f 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
@@ -495,13 +495,13 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
  * FreeRTOS API functions are not called from interrupts that have been assigned
  * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
  */
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
 
     static uint8_t ucMaxSysCallPriority = 0;
     static uint32_t ulMaxPRIGROUPValue = 0;
     static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
 
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
 
@@ -1614,7 +1614,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
 
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
-    #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+    #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
     {
         volatile uint32_t ulOriginalPriority;
         volatile uint32_t ulImplementedPrioBits = 0;
@@ -1695,7 +1695,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          * value. */
         portNVIC_SHPR2_REG = ulOriginalPriority;
     }
-    #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+    #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
     /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
     portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
@@ -1936,7 +1936,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 }
 /*-----------------------------------------------------------*/
 
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
 
     void vPortValidateInterruptPriority( void )
     {
@@ -1994,5 +1994,5 @@ BaseType_t xPortIsInsideInterrupt( void )
         configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
     }
 
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/portmacro.h b/portable/GCC/ARM_CM85_NTZ/non_secure/portmacro.h
index 99f913d34..d14448927 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/portmacro.h
@@ -54,7 +54,7 @@
  * Architecture specifics.
  */
 #define portARCH_NAME                       "Cortex-M85"
-#define portHAS_BASEPRI                     1
+#define portHAS_ARMV8M_MAIN_EXTENSION       1
 #define portDONT_DISCARD                    __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h
index 65ac109c8..e5ffdb48b 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h
@@ -81,8 +81,8 @@ typedef unsigned long    UBaseType_t;
     typedef uint32_t     TickType_t;
     #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
+    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+     * not need to be guarded with a critical section. */
     #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -307,7 +307,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * system calls.
  */
 #ifdef configASSERT
-    #if ( portHAS_BASEPRI == 1 )
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
         void vPortValidateInterruptPriority( void );
         #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
     #endif
@@ -364,49 +364,49 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-/**
- * @brief Allocate a secure context for the task.
- *
- * Tasks are not created with a secure context. Any task that is going to call
- * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
- * secure context before it calls any secure function.
- *
- * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
- */
+    /**
+     * @brief Allocate a secure context for the task.
+     *
+     * Tasks are not created with a secure context. Any task that is going to call
+     * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+     * secure context before it calls any secure function.
+     *
+     * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+     */
     #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
 
-/**
- * @brief Called when a task is deleted to delete the task's secure context,
- * if it has one.
- *
- * @param[in] pxTCB The TCB of the task being deleted.
- */
+    /**
+     * @brief Called when a task is deleted to delete the task's secure context,
+     * if it has one.
+     *
+     * @param[in] pxTCB The TCB of the task being deleted.
+     */
     #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
 #endif /* configENABLE_TRUSTZONE */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
+    /**
+     * @brief Checks whether or not the processor is privileged.
+     *
+     * @return 1 if the processor is already privileged, 0 otherwise.
+     */
     #define portIS_PRIVILEGED()      xIsPrivileged()
 
-/**
- * @brief Raise an SVC request to raise privilege.
- *
- * The SVC handler checks that the SVC was raised from a system call and only
- * then it raises the privilege. If this is called from any other place,
- * the privilege is not raised.
- */
+    /**
+     * @brief Raise an SVC request to raise privilege.
+     *
+     * The SVC handler checks that the SVC was raised from a system call and only
+     * then it raises the privilege. If this is called from any other place,
+     * the privilege is not raised.
+     */
     #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
 
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- */
+    /**
+     * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+     * register.
+     */
     #define portRESET_PRIVILEGE()    vResetPrivilege()
 #else
     #define portIS_PRIVILEGED()
@@ -435,6 +435,56 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
 /*-----------------------------------------------------------*/
 
+/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION
+ * based on whether or not Mainline extension is implemented. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+    #else
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+    #endif
+#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/**
+ * @brief Port-optimised task selection.
+ */
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+
+    /**
+     * @brief Count the number of leading zeros in a 32-bit value.
+     */
+    static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
+    {
+        uint32_t ulReturn;
+
+        __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" );
+
+        return ulReturn;
+    }
+
+    /* Check the configuration. */
+    #if ( configMAX_PRIORITIES > 32 )
+        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
+    #endif
+
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 )
+        #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection.  Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
+    #endif
+
+    /**
+     * @brief Store/clear the ready priorities in a bit map.
+     */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+    /**
+     * @brief Get the priority of the highest-priority task that is ready to execute.
+     */
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )   uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+/*-----------------------------------------------------------*/
+
 /* *INDENT-OFF* */
 #ifdef __cplusplus
     }
diff --git a/portable/IAR/ARM_CM23/non_secure/port.c b/portable/IAR/ARM_CM23/non_secure/port.c
index cab1b3668..04901015f 100644
--- a/portable/IAR/ARM_CM23/non_secure/port.c
+++ b/portable/IAR/ARM_CM23/non_secure/port.c
@@ -495,13 +495,13 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
  * FreeRTOS API functions are not called from interrupts that have been assigned
  * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
  */
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
 
     static uint8_t ucMaxSysCallPriority = 0;
     static uint32_t ulMaxPRIGROUPValue = 0;
     static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
 
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
 
@@ -1614,7 +1614,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
 
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
-    #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+    #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
     {
         volatile uint32_t ulOriginalPriority;
         volatile uint32_t ulImplementedPrioBits = 0;
@@ -1695,7 +1695,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          * value. */
         portNVIC_SHPR2_REG = ulOriginalPriority;
     }
-    #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+    #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
     /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
     portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
@@ -1936,7 +1936,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 }
 /*-----------------------------------------------------------*/
 
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
 
     void vPortValidateInterruptPriority( void )
     {
@@ -1994,5 +1994,5 @@ BaseType_t xPortIsInsideInterrupt( void )
         configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
     }
 
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM23/non_secure/portmacro.h b/portable/IAR/ARM_CM23/non_secure/portmacro.h
index 9cf0e87fb..76ba7172e 100644
--- a/portable/IAR/ARM_CM23/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM23/non_secure/portmacro.h
@@ -48,9 +48,9 @@
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME         "Cortex-M23"
-#define portHAS_BASEPRI       0
-#define portDONT_DISCARD      __root
+#define portARCH_NAME                       "Cortex-M23"
+#define portHAS_ARMV8M_MAIN_EXTENSION       0
+#define portDONT_DISCARD                    __root
 /*-----------------------------------------------------------*/
 
 /* ARMv8-M common port configurations. */
diff --git a/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h
index 65ac109c8..e5ffdb48b 100644
--- a/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h
@@ -81,8 +81,8 @@ typedef unsigned long    UBaseType_t;
     typedef uint32_t     TickType_t;
     #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
+    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+     * not need to be guarded with a critical section. */
     #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -307,7 +307,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * system calls.
  */
 #ifdef configASSERT
-    #if ( portHAS_BASEPRI == 1 )
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
         void vPortValidateInterruptPriority( void );
         #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
     #endif
@@ -364,49 +364,49 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-/**
- * @brief Allocate a secure context for the task.
- *
- * Tasks are not created with a secure context. Any task that is going to call
- * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
- * secure context before it calls any secure function.
- *
- * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
- */
+    /**
+     * @brief Allocate a secure context for the task.
+     *
+     * Tasks are not created with a secure context. Any task that is going to call
+     * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+     * secure context before it calls any secure function.
+     *
+     * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+     */
     #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
 
-/**
- * @brief Called when a task is deleted to delete the task's secure context,
- * if it has one.
- *
- * @param[in] pxTCB The TCB of the task being deleted.
- */
+    /**
+     * @brief Called when a task is deleted to delete the task's secure context,
+     * if it has one.
+     *
+     * @param[in] pxTCB The TCB of the task being deleted.
+     */
     #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
 #endif /* configENABLE_TRUSTZONE */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
+    /**
+     * @brief Checks whether or not the processor is privileged.
+     *
+     * @return 1 if the processor is already privileged, 0 otherwise.
+     */
     #define portIS_PRIVILEGED()      xIsPrivileged()
 
-/**
- * @brief Raise an SVC request to raise privilege.
- *
- * The SVC handler checks that the SVC was raised from a system call and only
- * then it raises the privilege. If this is called from any other place,
- * the privilege is not raised.
- */
+    /**
+     * @brief Raise an SVC request to raise privilege.
+     *
+     * The SVC handler checks that the SVC was raised from a system call and only
+     * then it raises the privilege. If this is called from any other place,
+     * the privilege is not raised.
+     */
     #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
 
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- */
+    /**
+     * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+     * register.
+     */
     #define portRESET_PRIVILEGE()    vResetPrivilege()
 #else
     #define portIS_PRIVILEGED()
@@ -435,6 +435,56 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
 /*-----------------------------------------------------------*/
 
+/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION
+ * based on whether or not Mainline extension is implemented. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+    #else
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+    #endif
+#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/**
+ * @brief Port-optimised task selection.
+ */
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+
+    /**
+     * @brief Count the number of leading zeros in a 32-bit value.
+     */
+    static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
+    {
+        uint32_t ulReturn;
+
+        __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" );
+
+        return ulReturn;
+    }
+
+    /* Check the configuration. */
+    #if ( configMAX_PRIORITIES > 32 )
+        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
+    #endif
+
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 )
+        #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection.  Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
+    #endif
+
+    /**
+     * @brief Store/clear the ready priorities in a bit map.
+     */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+    /**
+     * @brief Get the priority of the highest-priority task that is ready to execute.
+     */
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )   uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+/*-----------------------------------------------------------*/
+
 /* *INDENT-OFF* */
 #ifdef __cplusplus
     }
diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
index cab1b3668..04901015f 100644
--- a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
@@ -495,13 +495,13 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
  * FreeRTOS API functions are not called from interrupts that have been assigned
  * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
  */
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
 
     static uint8_t ucMaxSysCallPriority = 0;
     static uint32_t ulMaxPRIGROUPValue = 0;
     static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
 
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
 
@@ -1614,7 +1614,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
 
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
-    #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+    #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
     {
         volatile uint32_t ulOriginalPriority;
         volatile uint32_t ulImplementedPrioBits = 0;
@@ -1695,7 +1695,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          * value. */
         portNVIC_SHPR2_REG = ulOriginalPriority;
     }
-    #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+    #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
     /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
     portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
@@ -1936,7 +1936,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 }
 /*-----------------------------------------------------------*/
 
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
 
     void vPortValidateInterruptPriority( void )
     {
@@ -1994,5 +1994,5 @@ BaseType_t xPortIsInsideInterrupt( void )
         configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
     }
 
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h b/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h
index 9cf0e87fb..76ba7172e 100644
--- a/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h
@@ -48,9 +48,9 @@
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME         "Cortex-M23"
-#define portHAS_BASEPRI       0
-#define portDONT_DISCARD      __root
+#define portARCH_NAME                       "Cortex-M23"
+#define portHAS_ARMV8M_MAIN_EXTENSION       0
+#define portDONT_DISCARD                    __root
 /*-----------------------------------------------------------*/
 
 /* ARMv8-M common port configurations. */
diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h
index 65ac109c8..e5ffdb48b 100644
--- a/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h
@@ -81,8 +81,8 @@ typedef unsigned long    UBaseType_t;
     typedef uint32_t     TickType_t;
     #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
+    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+     * not need to be guarded with a critical section. */
     #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -307,7 +307,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * system calls.
  */
 #ifdef configASSERT
-    #if ( portHAS_BASEPRI == 1 )
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
         void vPortValidateInterruptPriority( void );
         #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
     #endif
@@ -364,49 +364,49 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-/**
- * @brief Allocate a secure context for the task.
- *
- * Tasks are not created with a secure context. Any task that is going to call
- * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
- * secure context before it calls any secure function.
- *
- * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
- */
+    /**
+     * @brief Allocate a secure context for the task.
+     *
+     * Tasks are not created with a secure context. Any task that is going to call
+     * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+     * secure context before it calls any secure function.
+     *
+     * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+     */
     #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
 
-/**
- * @brief Called when a task is deleted to delete the task's secure context,
- * if it has one.
- *
- * @param[in] pxTCB The TCB of the task being deleted.
- */
+    /**
+     * @brief Called when a task is deleted to delete the task's secure context,
+     * if it has one.
+     *
+     * @param[in] pxTCB The TCB of the task being deleted.
+     */
     #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
 #endif /* configENABLE_TRUSTZONE */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
+    /**
+     * @brief Checks whether or not the processor is privileged.
+     *
+     * @return 1 if the processor is already privileged, 0 otherwise.
+     */
     #define portIS_PRIVILEGED()      xIsPrivileged()
 
-/**
- * @brief Raise an SVC request to raise privilege.
- *
- * The SVC handler checks that the SVC was raised from a system call and only
- * then it raises the privilege. If this is called from any other place,
- * the privilege is not raised.
- */
+    /**
+     * @brief Raise an SVC request to raise privilege.
+     *
+     * The SVC handler checks that the SVC was raised from a system call and only
+     * then it raises the privilege. If this is called from any other place,
+     * the privilege is not raised.
+     */
     #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
 
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- */
+    /**
+     * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+     * register.
+     */
     #define portRESET_PRIVILEGE()    vResetPrivilege()
 #else
     #define portIS_PRIVILEGED()
@@ -435,6 +435,56 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
 /*-----------------------------------------------------------*/
 
+/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION
+ * based on whether or not Mainline extension is implemented. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+    #else
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+    #endif
+#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/**
+ * @brief Port-optimised task selection.
+ */
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+
+    /**
+     * @brief Count the number of leading zeros in a 32-bit value.
+     */
+    static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
+    {
+        uint32_t ulReturn;
+
+        __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" );
+
+        return ulReturn;
+    }
+
+    /* Check the configuration. */
+    #if ( configMAX_PRIORITIES > 32 )
+        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
+    #endif
+
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 )
+        #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection.  Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
+    #endif
+
+    /**
+     * @brief Store/clear the ready priorities in a bit map.
+     */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+    /**
+     * @brief Get the priority of the highest-priority task that is ready to execute.
+     */
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )   uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+/*-----------------------------------------------------------*/
+
 /* *INDENT-OFF* */
 #ifdef __cplusplus
     }
diff --git a/portable/IAR/ARM_CM33/non_secure/port.c b/portable/IAR/ARM_CM33/non_secure/port.c
index cab1b3668..04901015f 100644
--- a/portable/IAR/ARM_CM33/non_secure/port.c
+++ b/portable/IAR/ARM_CM33/non_secure/port.c
@@ -495,13 +495,13 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
  * FreeRTOS API functions are not called from interrupts that have been assigned
  * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
  */
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
 
     static uint8_t ucMaxSysCallPriority = 0;
     static uint32_t ulMaxPRIGROUPValue = 0;
     static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
 
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
 
@@ -1614,7 +1614,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
 
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
-    #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+    #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
     {
         volatile uint32_t ulOriginalPriority;
         volatile uint32_t ulImplementedPrioBits = 0;
@@ -1695,7 +1695,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          * value. */
         portNVIC_SHPR2_REG = ulOriginalPriority;
     }
-    #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+    #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
     /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
     portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
@@ -1936,7 +1936,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 }
 /*-----------------------------------------------------------*/
 
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
 
     void vPortValidateInterruptPriority( void )
     {
@@ -1994,5 +1994,5 @@ BaseType_t xPortIsInsideInterrupt( void )
         configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
     }
 
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM33/non_secure/portmacro.h b/portable/IAR/ARM_CM33/non_secure/portmacro.h
index 380768fc0..145f5246e 100644
--- a/portable/IAR/ARM_CM33/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM33/non_secure/portmacro.h
@@ -49,7 +49,7 @@
  * Architecture specifics.
  */
 #define portARCH_NAME                       "Cortex-M33"
-#define portHAS_BASEPRI                     1
+#define portHAS_ARMV8M_MAIN_EXTENSION       1
 #define portDONT_DISCARD                    __root
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h
index 65ac109c8..e5ffdb48b 100644
--- a/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h
@@ -81,8 +81,8 @@ typedef unsigned long    UBaseType_t;
     typedef uint32_t     TickType_t;
     #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
+    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+     * not need to be guarded with a critical section. */
     #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -307,7 +307,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * system calls.
  */
 #ifdef configASSERT
-    #if ( portHAS_BASEPRI == 1 )
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
         void vPortValidateInterruptPriority( void );
         #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
     #endif
@@ -364,49 +364,49 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-/**
- * @brief Allocate a secure context for the task.
- *
- * Tasks are not created with a secure context. Any task that is going to call
- * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
- * secure context before it calls any secure function.
- *
- * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
- */
+    /**
+     * @brief Allocate a secure context for the task.
+     *
+     * Tasks are not created with a secure context. Any task that is going to call
+     * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+     * secure context before it calls any secure function.
+     *
+     * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+     */
     #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
 
-/**
- * @brief Called when a task is deleted to delete the task's secure context,
- * if it has one.
- *
- * @param[in] pxTCB The TCB of the task being deleted.
- */
+    /**
+     * @brief Called when a task is deleted to delete the task's secure context,
+     * if it has one.
+     *
+     * @param[in] pxTCB The TCB of the task being deleted.
+     */
     #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
 #endif /* configENABLE_TRUSTZONE */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
+    /**
+     * @brief Checks whether or not the processor is privileged.
+     *
+     * @return 1 if the processor is already privileged, 0 otherwise.
+     */
     #define portIS_PRIVILEGED()      xIsPrivileged()
 
-/**
- * @brief Raise an SVC request to raise privilege.
- *
- * The SVC handler checks that the SVC was raised from a system call and only
- * then it raises the privilege. If this is called from any other place,
- * the privilege is not raised.
- */
+    /**
+     * @brief Raise an SVC request to raise privilege.
+     *
+     * The SVC handler checks that the SVC was raised from a system call and only
+     * then it raises the privilege. If this is called from any other place,
+     * the privilege is not raised.
+     */
     #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
 
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- */
+    /**
+     * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+     * register.
+     */
     #define portRESET_PRIVILEGE()    vResetPrivilege()
 #else
     #define portIS_PRIVILEGED()
@@ -435,6 +435,56 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
 /*-----------------------------------------------------------*/
 
+/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION
+ * based on whether or not Mainline extension is implemented. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+    #else
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+    #endif
+#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/**
+ * @brief Port-optimised task selection.
+ */
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+
+    /**
+     * @brief Count the number of leading zeros in a 32-bit value.
+     */
+    static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
+    {
+        uint32_t ulReturn;
+
+        __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" );
+
+        return ulReturn;
+    }
+
+    /* Check the configuration. */
+    #if ( configMAX_PRIORITIES > 32 )
+        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
+    #endif
+
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 )
+        #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection.  Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
+    #endif
+
+    /**
+     * @brief Store/clear the ready priorities in a bit map.
+     */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+    /**
+     * @brief Get the priority of the highest-priority task that is ready to execute.
+     */
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )   uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+/*-----------------------------------------------------------*/
+
 /* *INDENT-OFF* */
 #ifdef __cplusplus
     }
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
index cab1b3668..04901015f 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
@@ -495,13 +495,13 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
  * FreeRTOS API functions are not called from interrupts that have been assigned
  * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
  */
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
 
     static uint8_t ucMaxSysCallPriority = 0;
     static uint32_t ulMaxPRIGROUPValue = 0;
     static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
 
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
 
@@ -1614,7 +1614,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
 
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
-    #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+    #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
     {
         volatile uint32_t ulOriginalPriority;
         volatile uint32_t ulImplementedPrioBits = 0;
@@ -1695,7 +1695,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          * value. */
         portNVIC_SHPR2_REG = ulOriginalPriority;
     }
-    #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+    #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
     /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
     portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
@@ -1936,7 +1936,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 }
 /*-----------------------------------------------------------*/
 
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
 
     void vPortValidateInterruptPriority( void )
     {
@@ -1994,5 +1994,5 @@ BaseType_t xPortIsInsideInterrupt( void )
         configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
     }
 
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h b/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h
index 815dca086..445f0765a 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h
@@ -49,7 +49,7 @@
  * Architecture specifics.
  */
 #define portARCH_NAME                       "Cortex-M33"
-#define portHAS_BASEPRI                     1
+#define portHAS_ARMV8M_MAIN_EXTENSION       1
 #define portDONT_DISCARD                    __root
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h
index 65ac109c8..e5ffdb48b 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h
@@ -81,8 +81,8 @@ typedef unsigned long    UBaseType_t;
     typedef uint32_t     TickType_t;
     #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
+    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+     * not need to be guarded with a critical section. */
     #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -307,7 +307,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * system calls.
  */
 #ifdef configASSERT
-    #if ( portHAS_BASEPRI == 1 )
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
         void vPortValidateInterruptPriority( void );
         #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
     #endif
@@ -364,49 +364,49 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-/**
- * @brief Allocate a secure context for the task.
- *
- * Tasks are not created with a secure context. Any task that is going to call
- * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
- * secure context before it calls any secure function.
- *
- * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
- */
+    /**
+     * @brief Allocate a secure context for the task.
+     *
+     * Tasks are not created with a secure context. Any task that is going to call
+     * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+     * secure context before it calls any secure function.
+     *
+     * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+     */
     #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
 
-/**
- * @brief Called when a task is deleted to delete the task's secure context,
- * if it has one.
- *
- * @param[in] pxTCB The TCB of the task being deleted.
- */
+    /**
+     * @brief Called when a task is deleted to delete the task's secure context,
+     * if it has one.
+     *
+     * @param[in] pxTCB The TCB of the task being deleted.
+     */
     #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
 #endif /* configENABLE_TRUSTZONE */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
+    /**
+     * @brief Checks whether or not the processor is privileged.
+     *
+     * @return 1 if the processor is already privileged, 0 otherwise.
+     */
     #define portIS_PRIVILEGED()      xIsPrivileged()
 
-/**
- * @brief Raise an SVC request to raise privilege.
- *
- * The SVC handler checks that the SVC was raised from a system call and only
- * then it raises the privilege. If this is called from any other place,
- * the privilege is not raised.
- */
+    /**
+     * @brief Raise an SVC request to raise privilege.
+     *
+     * The SVC handler checks that the SVC was raised from a system call and only
+     * then it raises the privilege. If this is called from any other place,
+     * the privilege is not raised.
+     */
     #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
 
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- */
+    /**
+     * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+     * register.
+     */
     #define portRESET_PRIVILEGE()    vResetPrivilege()
 #else
     #define portIS_PRIVILEGED()
@@ -435,6 +435,56 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
 /*-----------------------------------------------------------*/
 
+/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION
+ * based on whether or not Mainline extension is implemented. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+    #else
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+    #endif
+#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/**
+ * @brief Port-optimised task selection.
+ */
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+
+    /**
+     * @brief Count the number of leading zeros in a 32-bit value.
+     */
+    static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
+    {
+        uint32_t ulReturn;
+
+        __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" );
+
+        return ulReturn;
+    }
+
+    /* Check the configuration. */
+    #if ( configMAX_PRIORITIES > 32 )
+        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
+    #endif
+
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 )
+        #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection.  Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
+    #endif
+
+    /**
+     * @brief Store/clear the ready priorities in a bit map.
+     */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+    /**
+     * @brief Get the priority of the highest-priority task that is ready to execute.
+     */
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )   uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+/*-----------------------------------------------------------*/
+
 /* *INDENT-OFF* */
 #ifdef __cplusplus
     }
diff --git a/portable/IAR/ARM_CM35P/non_secure/port.c b/portable/IAR/ARM_CM35P/non_secure/port.c
index cab1b3668..04901015f 100644
--- a/portable/IAR/ARM_CM35P/non_secure/port.c
+++ b/portable/IAR/ARM_CM35P/non_secure/port.c
@@ -495,13 +495,13 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
  * FreeRTOS API functions are not called from interrupts that have been assigned
  * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
  */
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
 
     static uint8_t ucMaxSysCallPriority = 0;
     static uint32_t ulMaxPRIGROUPValue = 0;
     static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
 
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
 
@@ -1614,7 +1614,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
 
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
-    #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+    #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
     {
         volatile uint32_t ulOriginalPriority;
         volatile uint32_t ulImplementedPrioBits = 0;
@@ -1695,7 +1695,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          * value. */
         portNVIC_SHPR2_REG = ulOriginalPriority;
     }
-    #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+    #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
     /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
     portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
@@ -1936,7 +1936,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 }
 /*-----------------------------------------------------------*/
 
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
 
     void vPortValidateInterruptPriority( void )
     {
@@ -1994,5 +1994,5 @@ BaseType_t xPortIsInsideInterrupt( void )
         configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
     }
 
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM35P/non_secure/portmacro.h b/portable/IAR/ARM_CM35P/non_secure/portmacro.h
index 46bc4e24b..5669c1f60 100644
--- a/portable/IAR/ARM_CM35P/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM35P/non_secure/portmacro.h
@@ -49,7 +49,7 @@
  * Architecture specifics.
  */
 #define portARCH_NAME                       "Cortex-M35P"
-#define portHAS_BASEPRI                     1
+#define portHAS_ARMV8M_MAIN_EXTENSION       1
 #define portDONT_DISCARD                    __root
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h
index 65ac109c8..e5ffdb48b 100644
--- a/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h
@@ -81,8 +81,8 @@ typedef unsigned long    UBaseType_t;
     typedef uint32_t     TickType_t;
     #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
+    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+     * not need to be guarded with a critical section. */
     #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -307,7 +307,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * system calls.
  */
 #ifdef configASSERT
-    #if ( portHAS_BASEPRI == 1 )
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
         void vPortValidateInterruptPriority( void );
         #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
     #endif
@@ -364,49 +364,49 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-/**
- * @brief Allocate a secure context for the task.
- *
- * Tasks are not created with a secure context. Any task that is going to call
- * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
- * secure context before it calls any secure function.
- *
- * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
- */
+    /**
+     * @brief Allocate a secure context for the task.
+     *
+     * Tasks are not created with a secure context. Any task that is going to call
+     * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+     * secure context before it calls any secure function.
+     *
+     * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+     */
     #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
 
-/**
- * @brief Called when a task is deleted to delete the task's secure context,
- * if it has one.
- *
- * @param[in] pxTCB The TCB of the task being deleted.
- */
+    /**
+     * @brief Called when a task is deleted to delete the task's secure context,
+     * if it has one.
+     *
+     * @param[in] pxTCB The TCB of the task being deleted.
+     */
     #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
 #endif /* configENABLE_TRUSTZONE */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
+    /**
+     * @brief Checks whether or not the processor is privileged.
+     *
+     * @return 1 if the processor is already privileged, 0 otherwise.
+     */
     #define portIS_PRIVILEGED()      xIsPrivileged()
 
-/**
- * @brief Raise an SVC request to raise privilege.
- *
- * The SVC handler checks that the SVC was raised from a system call and only
- * then it raises the privilege. If this is called from any other place,
- * the privilege is not raised.
- */
+    /**
+     * @brief Raise an SVC request to raise privilege.
+     *
+     * The SVC handler checks that the SVC was raised from a system call and only
+     * then it raises the privilege. If this is called from any other place,
+     * the privilege is not raised.
+     */
     #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
 
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- */
+    /**
+     * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+     * register.
+     */
     #define portRESET_PRIVILEGE()    vResetPrivilege()
 #else
     #define portIS_PRIVILEGED()
@@ -435,6 +435,56 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
 /*-----------------------------------------------------------*/
 
+/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION
+ * based on whether or not Mainline extension is implemented. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+    #else
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+    #endif
+#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/**
+ * @brief Port-optimised task selection.
+ */
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+
+    /**
+     * @brief Count the number of leading zeros in a 32-bit value.
+     */
+    static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
+    {
+        uint32_t ulReturn;
+
+        __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" );
+
+        return ulReturn;
+    }
+
+    /* Check the configuration. */
+    #if ( configMAX_PRIORITIES > 32 )
+        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
+    #endif
+
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 )
+        #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection.  Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
+    #endif
+
+    /**
+     * @brief Store/clear the ready priorities in a bit map.
+     */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+    /**
+     * @brief Get the priority of the highest-priority task that is ready to execute.
+     */
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )   uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+/*-----------------------------------------------------------*/
+
 /* *INDENT-OFF* */
 #ifdef __cplusplus
     }
diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c b/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
index cab1b3668..04901015f 100644
--- a/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
@@ -495,13 +495,13 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
  * FreeRTOS API functions are not called from interrupts that have been assigned
  * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
  */
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
 
     static uint8_t ucMaxSysCallPriority = 0;
     static uint32_t ulMaxPRIGROUPValue = 0;
     static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
 
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
 
@@ -1614,7 +1614,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
 
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
-    #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+    #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
     {
         volatile uint32_t ulOriginalPriority;
         volatile uint32_t ulImplementedPrioBits = 0;
@@ -1695,7 +1695,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          * value. */
         portNVIC_SHPR2_REG = ulOriginalPriority;
     }
-    #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+    #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
     /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
     portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
@@ -1936,7 +1936,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 }
 /*-----------------------------------------------------------*/
 
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
 
     void vPortValidateInterruptPriority( void )
     {
@@ -1994,5 +1994,5 @@ BaseType_t xPortIsInsideInterrupt( void )
         configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
     }
 
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacro.h b/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacro.h
index 46bc4e24b..5669c1f60 100644
--- a/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacro.h
@@ -49,7 +49,7 @@
  * Architecture specifics.
  */
 #define portARCH_NAME                       "Cortex-M35P"
-#define portHAS_BASEPRI                     1
+#define portHAS_ARMV8M_MAIN_EXTENSION       1
 #define portDONT_DISCARD                    __root
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
index 65ac109c8..e5ffdb48b 100644
--- a/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
@@ -81,8 +81,8 @@ typedef unsigned long    UBaseType_t;
     typedef uint32_t     TickType_t;
     #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
+    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+     * not need to be guarded with a critical section. */
     #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -307,7 +307,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * system calls.
  */
 #ifdef configASSERT
-    #if ( portHAS_BASEPRI == 1 )
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
         void vPortValidateInterruptPriority( void );
         #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
     #endif
@@ -364,49 +364,49 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-/**
- * @brief Allocate a secure context for the task.
- *
- * Tasks are not created with a secure context. Any task that is going to call
- * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
- * secure context before it calls any secure function.
- *
- * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
- */
+    /**
+     * @brief Allocate a secure context for the task.
+     *
+     * Tasks are not created with a secure context. Any task that is going to call
+     * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+     * secure context before it calls any secure function.
+     *
+     * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+     */
     #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
 
-/**
- * @brief Called when a task is deleted to delete the task's secure context,
- * if it has one.
- *
- * @param[in] pxTCB The TCB of the task being deleted.
- */
+    /**
+     * @brief Called when a task is deleted to delete the task's secure context,
+     * if it has one.
+     *
+     * @param[in] pxTCB The TCB of the task being deleted.
+     */
     #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
 #endif /* configENABLE_TRUSTZONE */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
+    /**
+     * @brief Checks whether or not the processor is privileged.
+     *
+     * @return 1 if the processor is already privileged, 0 otherwise.
+     */
     #define portIS_PRIVILEGED()      xIsPrivileged()
 
-/**
- * @brief Raise an SVC request to raise privilege.
- *
- * The SVC handler checks that the SVC was raised from a system call and only
- * then it raises the privilege. If this is called from any other place,
- * the privilege is not raised.
- */
+    /**
+     * @brief Raise an SVC request to raise privilege.
+     *
+     * The SVC handler checks that the SVC was raised from a system call and only
+     * then it raises the privilege. If this is called from any other place,
+     * the privilege is not raised.
+     */
     #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
 
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- */
+    /**
+     * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+     * register.
+     */
     #define portRESET_PRIVILEGE()    vResetPrivilege()
 #else
     #define portIS_PRIVILEGED()
@@ -435,6 +435,56 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
 /*-----------------------------------------------------------*/
 
+/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION
+ * based on whether or not Mainline extension is implemented. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+    #else
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+    #endif
+#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/**
+ * @brief Port-optimised task selection.
+ */
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+
+    /**
+     * @brief Count the number of leading zeros in a 32-bit value.
+     */
+    static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
+    {
+        uint32_t ulReturn;
+
+        __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" );
+
+        return ulReturn;
+    }
+
+    /* Check the configuration. */
+    #if ( configMAX_PRIORITIES > 32 )
+        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
+    #endif
+
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 )
+        #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection.  Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
+    #endif
+
+    /**
+     * @brief Store/clear the ready priorities in a bit map.
+     */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+    /**
+     * @brief Get the priority of the highest-priority task that is ready to execute.
+     */
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )   uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+/*-----------------------------------------------------------*/
+
 /* *INDENT-OFF* */
 #ifdef __cplusplus
     }
diff --git a/portable/IAR/ARM_CM55/non_secure/port.c b/portable/IAR/ARM_CM55/non_secure/port.c
index cab1b3668..04901015f 100644
--- a/portable/IAR/ARM_CM55/non_secure/port.c
+++ b/portable/IAR/ARM_CM55/non_secure/port.c
@@ -495,13 +495,13 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
  * FreeRTOS API functions are not called from interrupts that have been assigned
  * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
  */
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
 
     static uint8_t ucMaxSysCallPriority = 0;
     static uint32_t ulMaxPRIGROUPValue = 0;
     static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
 
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
 
@@ -1614,7 +1614,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
 
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
-    #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+    #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
     {
         volatile uint32_t ulOriginalPriority;
         volatile uint32_t ulImplementedPrioBits = 0;
@@ -1695,7 +1695,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          * value. */
         portNVIC_SHPR2_REG = ulOriginalPriority;
     }
-    #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+    #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
     /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
     portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
@@ -1936,7 +1936,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 }
 /*-----------------------------------------------------------*/
 
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
 
     void vPortValidateInterruptPriority( void )
     {
@@ -1994,5 +1994,5 @@ BaseType_t xPortIsInsideInterrupt( void )
         configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
     }
 
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM55/non_secure/portmacro.h b/portable/IAR/ARM_CM55/non_secure/portmacro.h
index 7829ee618..10596e8e5 100644
--- a/portable/IAR/ARM_CM55/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM55/non_secure/portmacro.h
@@ -54,7 +54,7 @@
  * Architecture specifics.
  */
 #define portARCH_NAME                       "Cortex-M55"
-#define portHAS_BASEPRI                     1
+#define portHAS_ARMV8M_MAIN_EXTENSION       1
 #define portDONT_DISCARD                    __root
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h
index 65ac109c8..e5ffdb48b 100644
--- a/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h
@@ -81,8 +81,8 @@ typedef unsigned long    UBaseType_t;
     typedef uint32_t     TickType_t;
     #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
+    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+     * not need to be guarded with a critical section. */
     #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -307,7 +307,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * system calls.
  */
 #ifdef configASSERT
-    #if ( portHAS_BASEPRI == 1 )
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
         void vPortValidateInterruptPriority( void );
         #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
     #endif
@@ -364,49 +364,49 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-/**
- * @brief Allocate a secure context for the task.
- *
- * Tasks are not created with a secure context. Any task that is going to call
- * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
- * secure context before it calls any secure function.
- *
- * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
- */
+    /**
+     * @brief Allocate a secure context for the task.
+     *
+     * Tasks are not created with a secure context. Any task that is going to call
+     * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+     * secure context before it calls any secure function.
+     *
+     * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+     */
     #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
 
-/**
- * @brief Called when a task is deleted to delete the task's secure context,
- * if it has one.
- *
- * @param[in] pxTCB The TCB of the task being deleted.
- */
+    /**
+     * @brief Called when a task is deleted to delete the task's secure context,
+     * if it has one.
+     *
+     * @param[in] pxTCB The TCB of the task being deleted.
+     */
     #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
 #endif /* configENABLE_TRUSTZONE */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
+    /**
+     * @brief Checks whether or not the processor is privileged.
+     *
+     * @return 1 if the processor is already privileged, 0 otherwise.
+     */
     #define portIS_PRIVILEGED()      xIsPrivileged()
 
-/**
- * @brief Raise an SVC request to raise privilege.
- *
- * The SVC handler checks that the SVC was raised from a system call and only
- * then it raises the privilege. If this is called from any other place,
- * the privilege is not raised.
- */
+    /**
+     * @brief Raise an SVC request to raise privilege.
+     *
+     * The SVC handler checks that the SVC was raised from a system call and only
+     * then it raises the privilege. If this is called from any other place,
+     * the privilege is not raised.
+     */
     #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
 
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- */
+    /**
+     * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+     * register.
+     */
     #define portRESET_PRIVILEGE()    vResetPrivilege()
 #else
     #define portIS_PRIVILEGED()
@@ -435,6 +435,56 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
 /*-----------------------------------------------------------*/
 
+/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION
+ * based on whether or not Mainline extension is implemented. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+    #else
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+    #endif
+#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/**
+ * @brief Port-optimised task selection.
+ */
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+
+    /**
+     * @brief Count the number of leading zeros in a 32-bit value.
+     */
+    static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
+    {
+        uint32_t ulReturn;
+
+        __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" );
+
+        return ulReturn;
+    }
+
+    /* Check the configuration. */
+    #if ( configMAX_PRIORITIES > 32 )
+        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
+    #endif
+
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 )
+        #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection.  Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
+    #endif
+
+    /**
+     * @brief Store/clear the ready priorities in a bit map.
+     */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+    /**
+     * @brief Get the priority of the highest-priority task that is ready to execute.
+     */
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )   uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+/*-----------------------------------------------------------*/
+
 /* *INDENT-OFF* */
 #ifdef __cplusplus
     }
diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/port.c b/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
index cab1b3668..04901015f 100644
--- a/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
@@ -495,13 +495,13 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
  * FreeRTOS API functions are not called from interrupts that have been assigned
  * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
  */
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
 
     static uint8_t ucMaxSysCallPriority = 0;
     static uint32_t ulMaxPRIGROUPValue = 0;
     static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
 
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
 
@@ -1614,7 +1614,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
 
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
-    #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+    #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
     {
         volatile uint32_t ulOriginalPriority;
         volatile uint32_t ulImplementedPrioBits = 0;
@@ -1695,7 +1695,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          * value. */
         portNVIC_SHPR2_REG = ulOriginalPriority;
     }
-    #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+    #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
     /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
     portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
@@ -1936,7 +1936,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 }
 /*-----------------------------------------------------------*/
 
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
 
     void vPortValidateInterruptPriority( void )
     {
@@ -1994,5 +1994,5 @@ BaseType_t xPortIsInsideInterrupt( void )
         configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
     }
 
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/portmacro.h b/portable/IAR/ARM_CM55_NTZ/non_secure/portmacro.h
index 7829ee618..10596e8e5 100644
--- a/portable/IAR/ARM_CM55_NTZ/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM55_NTZ/non_secure/portmacro.h
@@ -54,7 +54,7 @@
  * Architecture specifics.
  */
 #define portARCH_NAME                       "Cortex-M55"
-#define portHAS_BASEPRI                     1
+#define portHAS_ARMV8M_MAIN_EXTENSION       1
 #define portDONT_DISCARD                    __root
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h
index 65ac109c8..e5ffdb48b 100644
--- a/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h
@@ -81,8 +81,8 @@ typedef unsigned long    UBaseType_t;
     typedef uint32_t     TickType_t;
     #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
+    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+     * not need to be guarded with a critical section. */
     #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -307,7 +307,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * system calls.
  */
 #ifdef configASSERT
-    #if ( portHAS_BASEPRI == 1 )
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
         void vPortValidateInterruptPriority( void );
         #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
     #endif
@@ -364,49 +364,49 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-/**
- * @brief Allocate a secure context for the task.
- *
- * Tasks are not created with a secure context. Any task that is going to call
- * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
- * secure context before it calls any secure function.
- *
- * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
- */
+    /**
+     * @brief Allocate a secure context for the task.
+     *
+     * Tasks are not created with a secure context. Any task that is going to call
+     * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+     * secure context before it calls any secure function.
+     *
+     * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+     */
     #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
 
-/**
- * @brief Called when a task is deleted to delete the task's secure context,
- * if it has one.
- *
- * @param[in] pxTCB The TCB of the task being deleted.
- */
+    /**
+     * @brief Called when a task is deleted to delete the task's secure context,
+     * if it has one.
+     *
+     * @param[in] pxTCB The TCB of the task being deleted.
+     */
     #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
 #endif /* configENABLE_TRUSTZONE */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
+    /**
+     * @brief Checks whether or not the processor is privileged.
+     *
+     * @return 1 if the processor is already privileged, 0 otherwise.
+     */
     #define portIS_PRIVILEGED()      xIsPrivileged()
 
-/**
- * @brief Raise an SVC request to raise privilege.
- *
- * The SVC handler checks that the SVC was raised from a system call and only
- * then it raises the privilege. If this is called from any other place,
- * the privilege is not raised.
- */
+    /**
+     * @brief Raise an SVC request to raise privilege.
+     *
+     * The SVC handler checks that the SVC was raised from a system call and only
+     * then it raises the privilege. If this is called from any other place,
+     * the privilege is not raised.
+     */
     #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
 
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- */
+    /**
+     * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+     * register.
+     */
     #define portRESET_PRIVILEGE()    vResetPrivilege()
 #else
     #define portIS_PRIVILEGED()
@@ -435,6 +435,56 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
 /*-----------------------------------------------------------*/
 
+/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION
+ * based on whether or not Mainline extension is implemented. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+    #else
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+    #endif
+#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/**
+ * @brief Port-optimised task selection.
+ */
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+
+    /**
+     * @brief Count the number of leading zeros in a 32-bit value.
+     */
+    static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
+    {
+        uint32_t ulReturn;
+
+        __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" );
+
+        return ulReturn;
+    }
+
+    /* Check the configuration. */
+    #if ( configMAX_PRIORITIES > 32 )
+        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
+    #endif
+
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 )
+        #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection.  Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
+    #endif
+
+    /**
+     * @brief Store/clear the ready priorities in a bit map.
+     */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+    /**
+     * @brief Get the priority of the highest-priority task that is ready to execute.
+     */
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )   uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+/*-----------------------------------------------------------*/
+
 /* *INDENT-OFF* */
 #ifdef __cplusplus
     }
diff --git a/portable/IAR/ARM_CM85/non_secure/port.c b/portable/IAR/ARM_CM85/non_secure/port.c
index cab1b3668..04901015f 100644
--- a/portable/IAR/ARM_CM85/non_secure/port.c
+++ b/portable/IAR/ARM_CM85/non_secure/port.c
@@ -495,13 +495,13 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
  * FreeRTOS API functions are not called from interrupts that have been assigned
  * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
  */
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
 
     static uint8_t ucMaxSysCallPriority = 0;
     static uint32_t ulMaxPRIGROUPValue = 0;
     static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
 
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
 
@@ -1614,7 +1614,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
 
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
-    #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+    #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
     {
         volatile uint32_t ulOriginalPriority;
         volatile uint32_t ulImplementedPrioBits = 0;
@@ -1695,7 +1695,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          * value. */
         portNVIC_SHPR2_REG = ulOriginalPriority;
     }
-    #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+    #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
     /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
     portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
@@ -1936,7 +1936,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 }
 /*-----------------------------------------------------------*/
 
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
 
     void vPortValidateInterruptPriority( void )
     {
@@ -1994,5 +1994,5 @@ BaseType_t xPortIsInsideInterrupt( void )
         configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
     }
 
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM85/non_secure/portmacro.h b/portable/IAR/ARM_CM85/non_secure/portmacro.h
index 3b51cb5ff..374150262 100644
--- a/portable/IAR/ARM_CM85/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM85/non_secure/portmacro.h
@@ -54,7 +54,7 @@
  * Architecture specifics.
  */
 #define portARCH_NAME                       "Cortex-M85"
-#define portHAS_BASEPRI                     1
+#define portHAS_ARMV8M_MAIN_EXTENSION       1
 #define portDONT_DISCARD                    __root
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h
index 65ac109c8..e5ffdb48b 100644
--- a/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h
@@ -81,8 +81,8 @@ typedef unsigned long    UBaseType_t;
     typedef uint32_t     TickType_t;
     #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
+    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+     * not need to be guarded with a critical section. */
     #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -307,7 +307,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * system calls.
  */
 #ifdef configASSERT
-    #if ( portHAS_BASEPRI == 1 )
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
         void vPortValidateInterruptPriority( void );
         #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
     #endif
@@ -364,49 +364,49 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-/**
- * @brief Allocate a secure context for the task.
- *
- * Tasks are not created with a secure context. Any task that is going to call
- * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
- * secure context before it calls any secure function.
- *
- * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
- */
+    /**
+     * @brief Allocate a secure context for the task.
+     *
+     * Tasks are not created with a secure context. Any task that is going to call
+     * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+     * secure context before it calls any secure function.
+     *
+     * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+     */
     #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
 
-/**
- * @brief Called when a task is deleted to delete the task's secure context,
- * if it has one.
- *
- * @param[in] pxTCB The TCB of the task being deleted.
- */
+    /**
+     * @brief Called when a task is deleted to delete the task's secure context,
+     * if it has one.
+     *
+     * @param[in] pxTCB The TCB of the task being deleted.
+     */
     #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
 #endif /* configENABLE_TRUSTZONE */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
+    /**
+     * @brief Checks whether or not the processor is privileged.
+     *
+     * @return 1 if the processor is already privileged, 0 otherwise.
+     */
     #define portIS_PRIVILEGED()      xIsPrivileged()
 
-/**
- * @brief Raise an SVC request to raise privilege.
- *
- * The SVC handler checks that the SVC was raised from a system call and only
- * then it raises the privilege. If this is called from any other place,
- * the privilege is not raised.
- */
+    /**
+     * @brief Raise an SVC request to raise privilege.
+     *
+     * The SVC handler checks that the SVC was raised from a system call and only
+     * then it raises the privilege. If this is called from any other place,
+     * the privilege is not raised.
+     */
     #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
 
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- */
+    /**
+     * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+     * register.
+     */
     #define portRESET_PRIVILEGE()    vResetPrivilege()
 #else
     #define portIS_PRIVILEGED()
@@ -435,6 +435,56 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
 /*-----------------------------------------------------------*/
 
+/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION
+ * based on whether or not Mainline extension is implemented. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+    #else
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+    #endif
+#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/**
+ * @brief Port-optimised task selection.
+ */
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+
+    /**
+     * @brief Count the number of leading zeros in a 32-bit value.
+     */
+    static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
+    {
+        uint32_t ulReturn;
+
+        __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" );
+
+        return ulReturn;
+    }
+
+    /* Check the configuration. */
+    #if ( configMAX_PRIORITIES > 32 )
+        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
+    #endif
+
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 )
+        #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection.  Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
+    #endif
+
+    /**
+     * @brief Store/clear the ready priorities in a bit map.
+     */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+    /**
+     * @brief Get the priority of the highest-priority task that is ready to execute.
+     */
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )   uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+/*-----------------------------------------------------------*/
+
 /* *INDENT-OFF* */
 #ifdef __cplusplus
     }
diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/port.c b/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
index cab1b3668..04901015f 100644
--- a/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
@@ -495,13 +495,13 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
  * FreeRTOS API functions are not called from interrupts that have been assigned
  * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
  */
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
 
     static uint8_t ucMaxSysCallPriority = 0;
     static uint32_t ulMaxPRIGROUPValue = 0;
     static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
 
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
 
@@ -1614,7 +1614,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
 
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
-    #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+    #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
     {
         volatile uint32_t ulOriginalPriority;
         volatile uint32_t ulImplementedPrioBits = 0;
@@ -1695,7 +1695,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          * value. */
         portNVIC_SHPR2_REG = ulOriginalPriority;
     }
-    #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+    #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
     /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
     portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
@@ -1936,7 +1936,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 }
 /*-----------------------------------------------------------*/
 
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
 
     void vPortValidateInterruptPriority( void )
     {
@@ -1994,5 +1994,5 @@ BaseType_t xPortIsInsideInterrupt( void )
         configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
     }
 
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/portmacro.h b/portable/IAR/ARM_CM85_NTZ/non_secure/portmacro.h
index 3b51cb5ff..374150262 100644
--- a/portable/IAR/ARM_CM85_NTZ/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM85_NTZ/non_secure/portmacro.h
@@ -54,7 +54,7 @@
  * Architecture specifics.
  */
 #define portARCH_NAME                       "Cortex-M85"
-#define portHAS_BASEPRI                     1
+#define portHAS_ARMV8M_MAIN_EXTENSION       1
 #define portDONT_DISCARD                    __root
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h
index 65ac109c8..e5ffdb48b 100644
--- a/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h
@@ -81,8 +81,8 @@ typedef unsigned long    UBaseType_t;
     typedef uint32_t     TickType_t;
     #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
+    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+     * not need to be guarded with a critical section. */
     #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -307,7 +307,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * system calls.
  */
 #ifdef configASSERT
-    #if ( portHAS_BASEPRI == 1 )
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
         void vPortValidateInterruptPriority( void );
         #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
     #endif
@@ -364,49 +364,49 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-/**
- * @brief Allocate a secure context for the task.
- *
- * Tasks are not created with a secure context. Any task that is going to call
- * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
- * secure context before it calls any secure function.
- *
- * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
- */
+    /**
+     * @brief Allocate a secure context for the task.
+     *
+     * Tasks are not created with a secure context. Any task that is going to call
+     * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+     * secure context before it calls any secure function.
+     *
+     * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+     */
     #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
 
-/**
- * @brief Called when a task is deleted to delete the task's secure context,
- * if it has one.
- *
- * @param[in] pxTCB The TCB of the task being deleted.
- */
+    /**
+     * @brief Called when a task is deleted to delete the task's secure context,
+     * if it has one.
+     *
+     * @param[in] pxTCB The TCB of the task being deleted.
+     */
     #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
 #endif /* configENABLE_TRUSTZONE */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
+    /**
+     * @brief Checks whether or not the processor is privileged.
+     *
+     * @return 1 if the processor is already privileged, 0 otherwise.
+     */
     #define portIS_PRIVILEGED()      xIsPrivileged()
 
-/**
- * @brief Raise an SVC request to raise privilege.
- *
- * The SVC handler checks that the SVC was raised from a system call and only
- * then it raises the privilege. If this is called from any other place,
- * the privilege is not raised.
- */
+    /**
+     * @brief Raise an SVC request to raise privilege.
+     *
+     * The SVC handler checks that the SVC was raised from a system call and only
+     * then it raises the privilege. If this is called from any other place,
+     * the privilege is not raised.
+     */
     #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
 
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- */
+    /**
+     * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+     * register.
+     */
     #define portRESET_PRIVILEGE()    vResetPrivilege()
 #else
     #define portIS_PRIVILEGED()
@@ -435,6 +435,56 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
 /*-----------------------------------------------------------*/
 
+/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION
+ * based on whether or not Mainline extension is implemented. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+    #else
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+    #endif
+#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/**
+ * @brief Port-optimised task selection.
+ */
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+
+    /**
+     * @brief Count the number of leading zeros in a 32-bit value.
+     */
+    static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
+    {
+        uint32_t ulReturn;
+
+        __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" );
+
+        return ulReturn;
+    }
+
+    /* Check the configuration. */
+    #if ( configMAX_PRIORITIES > 32 )
+        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
+    #endif
+
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 )
+        #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection.  Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
+    #endif
+
+    /**
+     * @brief Store/clear the ready priorities in a bit map.
+     */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+    /**
+     * @brief Get the priority of the highest-priority task that is ready to execute.
+     */
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )   uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+/*-----------------------------------------------------------*/
+
 /* *INDENT-OFF* */
 #ifdef __cplusplus
     }

From 50b2d8fb66abda31d33376e9840cc93d12edaa56 Mon Sep 17 00:00:00 2001
From: kar-rahul-aws <118818625+kar-rahul-aws@users.noreply.github.com>
Date: Thu, 20 Jul 2023 09:49:05 +0530
Subject: [PATCH 007/424] Update mpu_wrappers_v2.c (#709)

* Update mpu_wrappers_v2.c

* Initialize Internal QueueSet Handle to NULL

---------

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
---
 portable/Common/mpu_wrappers_v2.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/portable/Common/mpu_wrappers_v2.c b/portable/Common/mpu_wrappers_v2.c
index 1e28d8e4e..1a976cb50 100644
--- a/portable/Common/mpu_wrappers_v2.c
+++ b/portable/Common/mpu_wrappers_v2.c
@@ -2133,7 +2133,7 @@
         {
             BaseType_t xReturn = pdFAIL;
             QueueSetMemberHandle_t xInternalQueueSetMemberHandle = NULL;
-            QueueSetHandle_t xInternalQueueSetHandle;
+            QueueSetHandle_t xInternalQueueSetHandle = NULL;
             int32_t lIndexQueueSet, lIndexQueueSetMember;
 
             lIndexQueueSet = ( int32_t ) xQueueSet;
@@ -2215,7 +2215,7 @@
 
         const char * MPU_pcQueueGetNameImpl( QueueHandle_t xQueue ) /* PRIVILEGED_FUNCTION */
         {
-            const char * pcReturn;
+            const char * pcReturn = NULL;
             QueueHandle_t xInternalQueueHandle = NULL;
             int32_t lIndex;
 
@@ -2519,7 +2519,7 @@
         {
             BaseType_t xReturn = pdFAIL;
             QueueSetMemberHandle_t xInternalQueueSetMemberHandle = NULL;
-            QueueSetHandle_t xInternalQueueSetHandle;
+            QueueSetHandle_t xInternalQueueSetHandle = NULL;
             int32_t lIndexQueueSet, lIndexQueueSetMember;
 
             lIndexQueueSet = ( int32_t ) xQueueSet;
@@ -3330,7 +3330,7 @@
                                          const EventBits_t uxBitsToWaitFor,
                                          TickType_t xTicksToWait ) /* PRIVILEGED_FUNCTION */
     {
-        EventBits_t xReturn;
+        EventBits_t xReturn = 0;
         EventGroupHandle_t xInternalEventGroupHandle = NULL;
         int32_t lIndex;
 

From 2cdd0e5e55b8fae5c80943ec09dc960457aef34a Mon Sep 17 00:00:00 2001
From: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Date: Thu, 20 Jul 2023 16:21:17 +0530
Subject: [PATCH 008/424] Add `-Wconversion` in CMakeLists.txt (#712)

Also fix warnings generated by this flag.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 CMakeLists.txt            | 1 +
 portable/MemMang/heap_4.c | 2 +-
 portable/MemMang/heap_5.c | 8 ++++----
 3 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/CMakeLists.txt b/CMakeLists.txt
index 6faa93167..678b6a6f5 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -260,6 +260,7 @@ target_compile_options(freertos_kernel PRIVATE
     $<$<COMPILE_LANG_AND_ID:C,Clang,GNU>:-Wextra>
     $<$<COMPILE_LANG_AND_ID:C,Clang,GNU>:-Wpedantic>
     $<$<COMPILE_LANG_AND_ID:C,Clang,GNU>:-Werror>
+    $<$<COMPILE_LANG_AND_ID:C,Clang,GNU>:-Wconversion>
     $<$<COMPILE_LANG_AND_ID:C,Clang>:-Weverything>
 
     # Suppressions required to build clean with clang.
diff --git a/portable/MemMang/heap_4.c b/portable/MemMang/heap_4.c
index c7a8209ed..c82933e66 100644
--- a/portable/MemMang/heap_4.c
+++ b/portable/MemMang/heap_4.c
@@ -421,7 +421,7 @@ static void prvHeapInit( void ) /* PRIVILEGED_FUNCTION */
     /* pxEnd is used to mark the end of the list of free blocks and is inserted
      * at the end of the heap space. */
     uxAddress = ( portPOINTER_SIZE_TYPE ) ( pucAlignedHeap + xTotalHeapSize );
-    uxAddress -= xHeapStructSize;
+    uxAddress -= ( portPOINTER_SIZE_TYPE ) xHeapStructSize;
     uxAddress &= ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK );
     pxEnd = ( BlockLink_t * ) uxAddress;
     pxEnd->xBlockSize = 0;
diff --git a/portable/MemMang/heap_5.c b/portable/MemMang/heap_5.c
index db9e1eb37..bd641dcdf 100644
--- a/portable/MemMang/heap_5.c
+++ b/portable/MemMang/heap_5.c
@@ -508,7 +508,7 @@ void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions )
             configASSERT( pxEnd != NULL );
 
             /* Check blocks are passed in with increasing start addresses. */
-            configASSERT( xAddress > ( size_t ) pxEnd );
+            configASSERT( ( size_t ) xAddress > ( size_t ) pxEnd );
         }
 
         /* Remember the location of the end marker in the previous region, if
@@ -517,9 +517,9 @@ void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions )
 
         /* pxEnd is used to mark the end of the list of free blocks and is
          * inserted at the end of the region space. */
-        xAddress = xAlignedHeap + xTotalRegionSize;
-        xAddress -= xHeapStructSize;
-        xAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
+        xAddress = xAlignedHeap + ( portPOINTER_SIZE_TYPE ) xTotalRegionSize;
+        xAddress -= ( portPOINTER_SIZE_TYPE ) xHeapStructSize;
+        xAddress &= ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK );
         pxEnd = ( BlockLink_t * ) xAddress;
         pxEnd->xBlockSize = 0;
         pxEnd->pxNextFreeBlock = NULL;

From 83da5fc95810de7b3340bcc0f0713e55d24d21cb Mon Sep 17 00:00:00 2001
From: kar-rahul-aws <118818625+kar-rahul-aws@users.noreply.github.com>
Date: Thu, 20 Jul 2023 18:02:03 +0530
Subject: [PATCH 009/424] Update portSTACK_REGION macro for continuity with
 user Regions (#713)

---
 portable/GCC/ARM_CM3_MPU/portmacro.h  | 4 ++--
 portable/GCC/ARM_CM4_MPU/portmacro.h  | 4 ++--
 portable/IAR/ARM_CM4F_MPU/portmacro.h | 4 ++--
 portable/RVDS/ARM_CM4_MPU/portmacro.h | 4 ++--
 4 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/portable/GCC/ARM_CM3_MPU/portmacro.h b/portable/GCC/ARM_CM3_MPU/portmacro.h
index d1f659e37..322e41a6c 100644
--- a/portable/GCC/ARM_CM3_MPU/portmacro.h
+++ b/portable/GCC/ARM_CM3_MPU/portmacro.h
@@ -86,8 +86,8 @@
     #define portMPU_REGION_CACHEABLE_BUFFERABLE                      ( 0x07UL << 16UL )
     #define portMPU_REGION_EXECUTE_NEVER                             ( 0x01UL << 28UL )
 
-    #define portGENERAL_PERIPHERALS_REGION                           ( 3UL )
-    #define portSTACK_REGION                                         ( 4UL )
+    #define portSTACK_REGION                                         ( 3UL )
+    #define portGENERAL_PERIPHERALS_REGION                           ( 4UL )
     #define portUNPRIVILEGED_FLASH_REGION                            ( 5UL )
     #define portPRIVILEGED_FLASH_REGION                              ( 6UL )
     #define portPRIVILEGED_RAM_REGION                                ( 7UL )
diff --git a/portable/GCC/ARM_CM4_MPU/portmacro.h b/portable/GCC/ARM_CM4_MPU/portmacro.h
index 5417feaef..45eaaa7b8 100644
--- a/portable/GCC/ARM_CM4_MPU/portmacro.h
+++ b/portable/GCC/ARM_CM4_MPU/portmacro.h
@@ -175,8 +175,8 @@ typedef unsigned long    UBaseType_t;
     #define configTEX_S_C_B_SRAM          ( 0x07UL )
 #endif
 
-#define portGENERAL_PERIPHERALS_REGION    ( configTOTAL_MPU_REGIONS - 5UL )
-#define portSTACK_REGION                  ( configTOTAL_MPU_REGIONS - 4UL )
+#define portSTACK_REGION                  ( configTOTAL_MPU_REGIONS - 5UL )
+#define portGENERAL_PERIPHERALS_REGION    ( configTOTAL_MPU_REGIONS - 4UL )
 #define portUNPRIVILEGED_FLASH_REGION     ( configTOTAL_MPU_REGIONS - 3UL )
 #define portPRIVILEGED_FLASH_REGION       ( configTOTAL_MPU_REGIONS - 2UL )
 #define portPRIVILEGED_RAM_REGION         ( configTOTAL_MPU_REGIONS - 1UL )
diff --git a/portable/IAR/ARM_CM4F_MPU/portmacro.h b/portable/IAR/ARM_CM4F_MPU/portmacro.h
index 4bb8abcde..bf8cad0bb 100644
--- a/portable/IAR/ARM_CM4F_MPU/portmacro.h
+++ b/portable/IAR/ARM_CM4F_MPU/portmacro.h
@@ -177,8 +177,8 @@ typedef unsigned long    UBaseType_t;
     #define configTEX_S_C_B_SRAM          ( 0x07UL )
 #endif
 
-#define portGENERAL_PERIPHERALS_REGION    ( configTOTAL_MPU_REGIONS - 5UL )
-#define portSTACK_REGION                  ( configTOTAL_MPU_REGIONS - 4UL )
+#define portSTACK_REGION                  ( configTOTAL_MPU_REGIONS - 5UL )
+#define portGENERAL_PERIPHERALS_REGION    ( configTOTAL_MPU_REGIONS - 4UL )
 #define portUNPRIVILEGED_FLASH_REGION     ( configTOTAL_MPU_REGIONS - 3UL )
 #define portPRIVILEGED_FLASH_REGION       ( configTOTAL_MPU_REGIONS - 2UL )
 #define portPRIVILEGED_RAM_REGION         ( configTOTAL_MPU_REGIONS - 1UL )
diff --git a/portable/RVDS/ARM_CM4_MPU/portmacro.h b/portable/RVDS/ARM_CM4_MPU/portmacro.h
index cc4e136d6..0afe11b82 100644
--- a/portable/RVDS/ARM_CM4_MPU/portmacro.h
+++ b/portable/RVDS/ARM_CM4_MPU/portmacro.h
@@ -174,8 +174,8 @@ typedef unsigned long    UBaseType_t;
     #define configTEX_S_C_B_SRAM          ( 0x07UL )
 #endif
 
-#define portGENERAL_PERIPHERALS_REGION    ( configTOTAL_MPU_REGIONS - 5UL )
-#define portSTACK_REGION                  ( configTOTAL_MPU_REGIONS - 4UL )
+#define portSTACK_REGION                  ( configTOTAL_MPU_REGIONS - 5UL )
+#define portGENERAL_PERIPHERALS_REGION    ( configTOTAL_MPU_REGIONS - 4UL )
 #define portUNPRIVILEGED_FLASH_REGION     ( configTOTAL_MPU_REGIONS - 3UL )
 #define portPRIVILEGED_FLASH_REGION       ( configTOTAL_MPU_REGIONS - 2UL )
 #define portPRIVILEGED_RAM_REGION         ( configTOTAL_MPU_REGIONS - 1UL )

From ae3a498e435cecdb25b889f2740ea99027dd0cb1 Mon Sep 17 00:00:00 2001
From: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Date: Mon, 24 Jul 2023 19:24:15 +0800
Subject: [PATCH 010/424] Merge SMP feature to main (#716)
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

FreeRTOS SMP feature is developed in a separate SMP branch. This commit merges the SMP branch to main along with some fixes. User of SMP branch needs to apply the following changes in the port:

* Rename configNUM_CORES to configNUMBER_OF_CORES
* Define portSET/CLEAR_INTERRUPT_MASK for SMP
* Define portENTER/EXIT_CRITICAL_FROM_ISR for SMP. vTaskEnterCriticalFromISR and vTaskExitCriticalFromISR should be used for these port macros
* Update portSET/CLEAR_INTERRUPT_MASK_FROM_ISR implementation to mask interrupt only Call xTaskIncrementTick in critical section in port

History of the development branch:
* Add vTaskYieldWithinAPI for taskYIELD_IF_USING_PREEMPTION

* Add configNUM_CORES config for SMP
* Add portGET_CORE_ID porting config and default return 0 to compatible
  with single core demos
* Replace xYieldPending with xYieldPendings for multiple cores
* Add vTaskYieldWithinAPI function for yield pending if the task is in
  criticial section. This check are enabled only when portCRITICAL_NESTING_IN_TCB
  is enabled
* taskYIELD_IF_USING_PREEMPTION use vTaskYieldWithinAPI when
  configUSE_PREEMPTION is set to 1

The following sections will be updated in other commits
* taskYIELD_IF_USING_PREEMPTION usage in multiple cores
* xYieldPendings usage in multiple cores

* Use portYIELD_WITHIN_API for portYIELD_WITHIN_API for single core

* Add xTaskRunState and xIsIdle in TCB

* Add xTaskRunState and xIsIdle in TCB
* Use xTaskAttribute to replace the xIsIdle in SMP TCB

* Add pxCurrentTCBs for multiple cores

* Keep pxCurrentTCB for single core
* Add pxCurrentTCBs for SMP
* Add xTaskGetCurrentTaskHandle for SMP
* Replace taskSELECT_HIGHEST_PRIORITY_TASK with temporary prvSelectHighestPriorityTask

* Add SMP critical section functions

* Update vTaskEnterCritical and vTaskExitCritical functions for SMP
* Add vTaskEnterCriticalFromISR and vTaskExitCriticalFromISR for SMP

* Add SMP prvYieldCore and prvYieldForTask

* Add idle tasks for SMP

* Add minimal idle task function declaration
* Align to use 0x00 for null terminator

* Merge vTaskSuspendAll and xTaskResumeAll from SMP branch

* Merge vTaskResume and xTaskResumeFromISR from SMP

* Merge xTaskIncrementTick from SMP

* Update prvYieldForTask usage in kernel APIs

* Merge prvAddNewTaskToReadyList from SMP

* Merge vTaskSwitchContext from SMP

* Add vTaskSwitchContextForCore APIs to switch context for specific core
* vTaskSwitchContext will switch context for current core

* Merge vTaskDelete from SMP

* Add prvYeildCore for single core to reduce multicore macros
* Add taskTASK_IS_RUNNING for single core
* Add taskTASK_IS_YIELDING

* Merge vTaskSuspend from SMP

* Set minimal idle task idle attribute

* Set minimal idle task idle attribute in prvInitialiseNewTask

* Move prvCreateIdleTasks forward and check return value

* Add minimal idle hook config check

* Fix xTaskResumeAll in SMP

* xTaskRusmeAll do nothing when scheduler not running in SMP

* check scheduler suspended when scheduler is running

* Move suspend scheduler inside critical section

* Update comment for uxSchedulerSuspended

* Add back xPendingReadyList for single core

* Use critical section for SMP

* Add in ISR check in prvCheckForRunStateChange function

* Add critical section protect for context switch

* Add vTaskSwitchContextForCore declaration

* Fix missing macro and check for single core

* Fix task delete condition

* Latest kernel move out the prvDeleteTask and the check condition should be
  TASK_IS_RUNNING

* Use critical section to protect more in SMP for vTaskDelete

* The condition task is running is not thread safe in SMP
* Once we add the task to termination the task is still running and may
  add it back to other list. Which cause memory corruption.

* Merge SMP prvSelectHighestPriorityTask to main

* Merge prvCheckTasksWaitingTermination from SMP branch

* Move prvDeleteTCB outside of critical section

* Add NULL pointer check in prvCheckTasksWaitingTermination

* Update for performance

* Remove prvSelectHighestPriorityTask and vTaskSwitchContextForCore for
  -O0 performance in single core

* Update prvSelectHighestPriorityTask

* Merge vTaskYieldWithinAPI from SMP

Update vTaskYieldWithinAPI from SMP
* xTaskDelayUntil
* xTaskDelay
* ulTaskGenericNotifyTake
* xTaskGenericNotifyWait
* event_groups.c
* queue.c
* timers.c

Add critical section protection
* xTaskGetSchedulerState

Update state check macro
* vTaskGetInfo
* eTaskGetState

* Merge vTaskPrioritySet from SMP branch

* Void prvYieldForTask return value in vTaskPrioritySet

* Yield for SMP when set priority

* Move vTaskDelay check uxSchedulerSuspended

* Update code logic for performance

* Fix yield for task in single core

* Merge timer change from SMP branch

* Split xTimerGenericCommand into xTimerGenericCommandFromTask and
  xTimerGenericCommandFromISR to remove the recursion path when called from ISRs.
* Add portTIMER_CALLBACK_ATTRIBUTE for timer callback function

* Add RP2040 SMP porting support

* Seperate task state for SMP and single core

* Merge configRUN_MULTIPLE_PRIORITIES from SMP branch

* Merge configUSE_TASK_PREEMPTION_DISABLE from SMP

* Merge configUSE_CORE_AFFINITY from SMP

* Update pxYieldSpinLocks to per-cpu variable in SMP

* Remove TODO log

* Add suppport for ARM CM55 (#494)

* Add supposrt for ARM CM55

* Fix file header

* Remove duplicate code

* Refactor portmacro.h

1. portmacro.h is re-factored into 2 parts - portmacrocommon.h which is
   common to all ARMv8-M ports and portmacro.h which is different for
   different compiler and architecture. This enables us to provide
   Cortex-M55 ports without code duplication.
2. Update copy_files.py so that it copies Cortex-M55 ports correctly -
   all files except portmacro.h are used from Cortex-M33 ports.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>

* add extra check for compiler time (#499)

minor change to add extra check for compiler time to prevent bad config

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

* Update feature_request.md (#500)

* Update feature_request.md

* Remove trailing spaces

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>

* Add callback overrides for stream buffer and message buffers (#437)

* Let each stream/message can use its own sbSEND_COMPLETED

In FreeRTOS.h, set the default value of configUSE_SB_COMPLETED_CALLBACK
to zero, and add additional space for the function pointer when
the buffer created statically.

In stream_buffer.c, modify the macro of sbSEND_COMPLETED which let
the stream buffer to use its own implementation, and then add an
pointer to the stream buffer's structure, and modify the
implementation of the buffer creating and initializing

Co-authored-by: eddie9712 <qw1562435@gmail.com>

* Add configUSE_MUTEXES to function declarations in header (#504)

This commit adds the configUSE_MUTEXES guard to the function
declarations in semphr.h which are only available when configUSE_MUTEXES
is set to 1.

It was reported here - https://forums.freertos.org/t/mutex-missing-reference-to-configuse-mutexes-on-the-online-documentation/15231

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* RP2040: Remove incorrect assertion (#508)

After the xEventGroupWaitBits in vProtLockInternalSpinUnlockWithWait there was an assertion about
pxYiledSpinLock being NULL, however when xEventGroupWaitBits returns, IRQs have been re-enabled
and so it is no longer safe to assert on the state which is protected by IRQs being disabled.

Co-authored-by: graham sanderson <graham.sanderson@raspeberryi.com>

* Ensure that xTaskGetCurrentTaskHandle is included (#507)

This commits adds a check that INCLUDE_xTaskGetCurrentTaskHandle is
set to 1. A compile time error message is produced if it is not set to
1. This is needed because stream_buffer.c uses xTaskGetCurrentTaskHandle.

This was reported here - https://forums.freertos.org/t/xstreambufferreceive-include-xtaskgetcur/15283

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* RP2040: Allow FreeRTOS to be added to the parent CMake project post initialization of the Pico SDK (#497)

Co-authored-by: graham sanderson <graham.sanderson@raspeberryi.com>

* Update to TF-M version TF-Mv1.6.0 (#517)

Signed-off-by: Xinyu Zhang <xinyu.zhang@arm.com>
Change-Id: I0c15564b342873f9bd7a8240822e770950a0563e

* Update submodule pointer of Community Supported Ports (#486)

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

Co-authored-by: Paul Bartell <pbartell@amazon.com>
Co-authored-by: Joseph Julicher <jjulicher@mac.com>

* Add Cortex M7 r0p1 Errata 837070 workaround to CM4_MPU ports (#513)

* Clarify Cortex M7 r0p1 errata number in r0p1 specific port.

* Add ARM Cortex M7 r0p0 / r0p1 Errata 837070 workaround to CM4 MPU ports.

Optionally, enable the errata workaround by defining configTARGET_ARM_CM7_r0p0 or configTARGET_ARM_CM7_r0p1 in FreeRTOSConfig.h.

* Add r0p1 errata support to IAR port as well

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Change macro name to configENABLE_ERRATA_837070_WORKAROUND

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>

* RP2040: Use indirect reference for pxCurrentTCB (#525)

* Posix: Removed unused signal set from port (#528)

Co-authored-by: Jakob Hasse <0xjakob@users.noreply.github.com>

* Add SBOM Generation in auto_release.yml (#524)

* add portDONT_DISCARD to pxCurrentTCB (#479)

This fixes link failures with LTO:

/tmp/ccJbaKaD.ltrans0.ltrans.o: in function `pxCurrentTCBConst2':
/root/project/FreeRTOS/portable/GCC/ARM_CM4F/port.c:249: undefined reference to `pxCurrentTCB'
/usr/lib/gcc/arm-none-eabi/11.2.0/../../../../arm-none-eabi/bin/ld: /tmp/ccJbaKaD.ltrans0.ltrans.o: in function `pxCurrentTCBConst':
/root/project/FreeRTOS/portable/GCC/ARM_CM4F/port.c:443: undefined reference to `pxCurrentTCB'

* Implement MicroBlazeV9 stack protection (#523)

* Implement stack protection for MicroBlaze (without MPU wrappers)

* Update codecov action to v3.1.0

* Add vPortRemoveInterruptHandler API (#533)

* Add xPortRemoveInterruptHandler API

This API is added to the MicroBlazeV9 port. It enables the application
writer to remove an interrupt handler.

This was originally contributed in this PR - https://github.com/FreeRTOS/FreeRTOS-Kernel/pull/523

* Change API signature to return void

This makes the API similar to vPortDisableInterrupt.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

Co-authored-by: Gavin Lambert <uecasm@users.noreply.github.com>

* Fix NULL pointer dereference in vPortGetHeapStats

When the heap is exhausted (no free block), start and end markers are
the only blocks present in the free block list:

     +---------------+     +-----------> NULL
     |               |     |
     |               V     |
+ ----- +            + ----- +
|   |   |            |   |   |
|   |   |            |   |   |
+ ----- +            + ----- +
  xStart               pxEnd

The code block which traverses the list of free blocks to calculate heap
stats used a do..while loop that moved past the end marker when the heap
had no free block resulting in a NULL pointer dereference. This commit
changes the do..while loop to while loop thereby ensuring that we never
move past the end marker.

This was reported here - https://github.com/FreeRTOS/FreeRTOS-Kernel/issues/534

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Change type of message buffer handle (#537)

* Block SIG_RESUME in the main thread of the Posix port so that sigwait works as expected (#532)

Co-authored-by: alfred gedeon <28123637+alfred2g@users.noreply.github.com>

* Update History.txt (#535)

* Update History.txt

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Add .syntax unified to GCC assembly functions (#538)

This fixes the compilation issue with XC32 compiler.

It was reported here - https://forums.freertos.org/t/xc32-v4-00-error-with-building-freertos-portasm-c/14357/4

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

Co-authored-by: Paul Bartell <pbartell@amazon.com>

* Generalize Thread Local Storage (TLS) support (#540)

* Generalize Thread Local Storage (TLS) support

FreeRTOS's Thread Local Storage (TLS) support used variables and
functions from newlib, thereby making the TLS support specific to
newlib. This commit generalizes the TLS support so that it can be used
with other c-runtime libraries also. The default behavior for newlib
support is still kept same for backward compatibility.

The application writer would need to set configUSE_C_RUNTIME_TLS_SUPPORT
to 1 in their FreeRTOSConfig.h and define the following macros to
support TLS for a c-runtime library:

1. configTLS_BLOCK_TYPE - Type used to define the TLS block in TCB.
2. configINIT_TLS_BLOCK( xTLSBlock ) - Allocate and initialize memory
   block for the task's TLS Block.
3. configSET_TLS_BLOCK( xTLSBlock ) - Switch C-Runtime's TLS Block to
   point to xTLSBlock.
4. configDEINIT_TLS_BLOCK( xTLSBlock ) - Free up the memory allocated
   for the task's TLS Block.

The following is an example to support TLS for picolibc:

 #define configUSE_C_RUNTIME_TLS_SUPPORT        1
 #define configTLS_BLOCK_TYPE                   void*
 #define configINIT_TLS_BLOCK( xTLSBlock )      _init_tls( xTLSBlock )
 #define configSET_TLS_BLOCK( xTLSBlock )       _set_tls( xTLSBlock )
 #define configDEINIT_TLS_BLOCK( xTLSBlock )

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Change default value of INCLUDE_xTaskGetCurrentTaskHandle (#542)

* Include string.h at the top of portable/GCC/ARM_CA9/port.c to prevent memset() generating a warning. (#430)

Co-authored-by: none <unknown>

* Move some of the complex pre-processor guards on prvWriteNameToBuffer() to compile time checks in FreeRTOS.h.

Co-authored-by: Paul Bartell <pbartell@amazon.com>

* Fix formatting of FreeRTOS.h

* correct grammar in include/FreeRTOS.h

Co-authored-by: Aniruddha Kanhere <60444055+AniruddhaKanhere@users.noreply.github.com>

* Fix warnings in posix port (#544)

Fixes warnings about unused parameters and variables when built with
`-Wall -Wextra`.

* Add support for MISRA rule 20.7 (#546)

Misra rule 20.7 requires parenthesis to all parameter names
in macro definitions.

The issue was reported here : https://forums.freertos.org/t/misra-20-7-compatibility/15385

* Add FreeRTOS config directory to include dirs (#548)

This allows the application write to set FREERTOS_CONFIG_FILE_DIRECTORY
to whichever directory the FreeRTOSConfig.h file exists in.

This was reported here - https://github.com/FreeRTOS/FreeRTOS-Kernel/issues/545

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* [Fix] Type for pointers operations (#550)

* fix type for pointers operations in some places: size_t -> portPOINTER_SIZE_TYPE

* fix pointer arithmetics

* fix xAddress type

* RISC-V: Add support for RV32E extension in GCC port (#543)

Co-authored-by: Joseph Julicher <jjulicher@mac.com>

* Added checks for index in ThreadLocalStorage APIs (#552)

Added checks for ( xIndex >= 0 ) in ThreadLocalStorage APIs

* Update of three badly terminated macro definitions (#555)

* Update of three badly terminated macro definitions
- vTaskDelayUntil() to conform to usual pattern do { ... } while(0)
- vTaskNotifyGiveFromISR() and
- vTaskGenericNotifyGiveFromISR() to remove extra terminating semicolons
- This PR addresses issues #553 and #554

* Adjust formatting of task.h

Co-authored-by: Paul Bartell <pbartell@amazon.com>

* M85 support (#556)

* Extend support to Arm Cortex-M85

Signed-off-by: Gabor Toth <gabor.toth@arm.com>
Change-Id: I679ba8e193638126b683b651513f08df445f9fe6

* Add generated Cortex-M85 support files

Signed-off-by: Gabor Toth <gabor.toth@arm.com>
Change-Id: Ib329d88623c2936ffe3e9a24f5d6e07655e4e5c8

* Extend Trusted Firmware M port

Extend Trusted Firmware M port to Cortex-M23,
Cortex-M55 and Cortex-M85.

Signed-off-by: Gabor Toth <gabor.toth@arm.com>
Change-Id: If8f1081acfd04e547b3227579e70e355a6adffe3

* Re-run copy_files.py script

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

Signed-off-by: Gabor Toth <gabor.toth@arm.com>
Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>

* portable-RP2040: Fix typo in README.md (#559)

Replace "import" with "include" in cmake code sample.

* Update CMakeLists.txt for Cortex-M55 and Cortex-M85 ports (#560)

* Annotate ports CMakeLists.txt with port details

* CMake: Add Cortex-M55 and Cortex-M85 ports

* Use highest numbered MPU regions for kernel

ARMv7-M allows overlapping MPU regions. When 2 MPU regions overlap, the
MPU configuration of the higher numbered MPU region is applied. For
example, if a memory area is covered by 2 MPU regions 0 and 1, the
memory permissions for MPU region 1 are applied.

We use 5 MPU regions for kernel code and kernel data protections and
leave the remaining for the application writer. We were using lowest
numbered MPU regions (0-4) for kernel protections and leaving the
remaining for the application writer. The application writer could
configure those higher numbered MPU regions to override kernel
protections.

This commit changes the code to use highest numbered MPU regions for
kernel protections and leave the remaining for the application writer.
This ensures that the application writer cannot override kernel
protections.

We thank the SecLab team at Northeastern University for reporting this
issue.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Make RAM regions non-executable

This commit makes the privileged RAM and stack regions non-executable.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Remove local stack variable form MPU wrappers

It was possible for a third party that had already independently gained
the ability to execute injected code to achieve further privilege
escalation by branching directly inside a FreeRTOS MPU API wrapper
function with a manually crafted stack frame. This commit removes the
local stack variable `xRunningPrivileged` so that a manually crafted
stack frame cannot be used for privilege escalation by branching
directly inside a FreeRTOS MPU API wrapper.

We thank Certibit Consulting, LLC, Huazhong University of Science and
Technology and the SecLab team at Northeastern University for reporting
this issue.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Restrict unpriv task to invoke code with privilege

It was possible for an unprivileged task to invoke any function with
privilege by passing it as a parameter to MPU_xTaskCreate,
MPU_xTaskCreateStatic, MPU_xTimerCreate, MPU_xTimerCreateStatic, or
MPU_xTimerPendFunctionCall.

This commit ensures that MPU_xTaskCreate and MPU_xTaskCreateStatic can
only create unprivileged tasks. It also removes the following APIs:
1. MPU_xTimerCreate
2. MPU_xTimerCreateStatic
3. MPU_xTimerPendFunctionCall

We thank Huazhong University of Science and Technology for reporting
this issue.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Update History.txt

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Update History.txt as per the PR feedback

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Update RISC-V IAR port to support vector mode. (#458)

* Update RISC-V IAR port to support vector mode.

* uncrustify

Co-authored-by: David Chalco <david@chalco.io>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Co-authored-by: alfred gedeon <28123637+alfred2g@users.noreply.github.com>

* Added better pointer declaration readability (#567)

* Add better pointer declaration readability

I revised the declaration of single-line pointers by splitting it into
multiple lines. Now, every pointer is declared (and initialized
accordingly) on its own line. This refactoring should enhance
readability and decrease the probability of error when a new pointer is
added/removed or a current one has its initialization value modified.

Signed-off-by: Cristian Cristea <cristiancristea00@gmail.com>

* Remove unnecessary whitespace characters and lines

It removes whitespace characters at the end of lines (empty or
othwerwise) and clear lines at the end of the file (only one remains).
It is an automatic operation done by git.

Signed-off-by: Cristian Cristea <cristiancristea00@gmail.com>

Signed-off-by: Cristian Cristea <cristiancristea00@gmail.com>

* Update doc comments in task.h (#570)

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Tickless idle fixes/improvement (#59)

* Fix tickless idle when stopping systick on zero...

...and don't stop SysTick at all in the eAbortSleep case.

Prior to this commit, if vPortSuppressTicksAndSleep() happens to stop
the SysTick on zero, then after tickless idle ends, xTickCount advances
one full tick more than the time that actually elapsed as measured by
the SysTick.  See "bug 1" in this forum post:
https://forums.freertos.org/t/ultasknotifytake-timeout-accuracy/9629/40

SysTick
-------
The SysTick is the hardware timer that provides the OS tick interrupt
in the official ports for Cortex M.  SysTick starts counting down from
the value stored in its reload register.  When SysTick reaches zero, it
requests an interrupt.  On the next SysTick clock cycle, it loads the
counter again from the reload register.  To get periodic interrupts
every N SysTick clock cycles, the reload register must be N - 1.

Bug Example
-----------
- Idle task calls vPortSuppressTicksAndSleep(xExpectedIdleTime = 2).
  [Doesn't have to be "2" -- could be any number.]
- vPortSuppressTicksAndSleep() stops SysTick, and the current-count
  register happens to stop on zero.
- SysTick ISR executes, setting xPendedTicks = 1
- vPortSuppressTicksAndSleep() masks interrupts and calls
  eTaskConfirmSleepModeStatus() which confirms the sleep operation. ***
- vPortSuppressTicksAndSleep() configures SysTick for 1 full tick
  (xExpectedIdleTime - 1) plus the current-count register (which is 0)
- One tick period elapses in sleep.
- SysTick wakes CPU, ISR executes and increments xPendedTicks to 2.
- vPortSuppressTicksAndSleep() calls vTaskStepTick(1), then returns.
- Idle task resumes scheduler, which increments xTickCount twice (for
  xPendedTicks = 2)

In the end, two ticks elapsed as measured by SysTick, but the code
increments xTickCount three times.  The root cause is that the code
assumes the SysTick current-count register always contains the number of
SysTick counts remaining in the current tick period.  However, when the
current-count register is zero, there are ulTimerCountsForOneTick
counts remaining, not zero.  This error is not the kind of time slippage
normally associated with tickless idle.

*** Note that a recent commit https://github.com/FreeRTOS/FreeRTOS-Kernel/commit/e1b98f0
results in eAbortSleep in this case, due to xPendedTicks != 0.  That
commit does mostly resolve this bug without specifically mentioning
it, and without this commit.  But that resolution allows the code in
port.c not to directly address the special case of stopping SysTick on
zero in any code or comments.  That commit also generates additional
instances of eAbortSleep, and a second purpose of this commit is to
optimize how vPortSuppressTicksAndSleep() behaves for eAbortSleep, as
noted below.

This commit also includes an optimization to avoid stopping the SysTick
when eTaskConfirmSleepModeStatus() returns eAbortSleep.  This
optimization belongs with this fix because the method of handling the
SysTick being stopped on zero changes with this optimization.

* Fix imminent tick rescheduled after tickless idle

Prior to this commit, if something other than systick wakes the CPU from
tickless idle, vPortSuppressTicksAndSleep() might cause xTickCount to
increment once too many times.  See "bug 2" in this forum post:
https://forums.freertos.org/t/ultasknotifytake-timeout-accuracy/9629/40

SysTick
-------
The SysTick is the hardware timer that provides the OS tick interrupt
in the official ports for Cortex M.  SysTick starts counting down from
the value stored in its reload register.  When SysTick reaches zero, it
requests an interrupt.  On the next SysTick clock cycle, it loads the
counter again from the reload register.  To get periodic interrupts
every N SysTick clock cycles, the reload register must be N - 1.

Bug Example
-----------
- CPU is sleeping in vPortSuppressTicksAndSleep()
- Something other than the SysTick wakes the CPU.
- vPortSuppressTicksAndSleep() calculates the number of SysTick counts
  until the next tick.  The bug occurs only if this number is small.
- vPortSuppressTicksAndSleep() puts this small number into the SysTick
  reload register, and starts SysTick.
- vPortSuppressTicksAndSleep() calls vTaskStepTick()
- While vTaskStepTick() executes, the SysTick expires.  The ISR pends
  because interrupts are masked, and SysTick starts a 2nd period still
  based on the small number of counts in its reload register.  This 2nd
  period is undesirable and is likely to cause the error noted below.
- vPortSuppressTicksAndSleep() puts the normal tick duration into the
  SysTick's reload register.
- vPortSuppressTicksAndSleep() unmasks interrupts before the SysTick
  starts a new period based on the new value in the reload register.
  [This is a race condition that can go either way, but for the bug
  to occur, the race must play out this way.]
- The pending SysTick ISR executes and increments xPendedTicks.
- The SysTick expires again, finishing the second very small period, and
  starts a new period this time based on the full tick duration.
- The SysTick ISR increments xPendedTicks (or xTickCount) even though
  only a tiny fraction of a tick period has elapsed since the previous
  tick.

The bug occurs when *two* consecutive small periods of the SysTick are
both counted as ticks.  The root cause is a race caused by the small
SysTick period.  If vPortSuppressTicksAndSleep() unmasks interrupts
*after* the small period expires but *before* the SysTick starts a
period based on the full tick period, then two small periods are
counted as ticks when only one should be counted.

The end result is xTickCount advancing nearly one full tick more than
time actually elapsed as measured by the SysTick.  This is not the kind
of time slippage normally associated with tickless idle.

After this commit the code starts the SysTick and then immediately
modifies the reload register to ensure the very short cycle (if any) is
conducted only once.  This strategy requires special consideration for
the build option that configures SysTick to use a divided clock.  To
avoid waiting around for the SysTick to load value from the reload
register, the new code temporarily configures the SysTick to use the
undivided clock.  The resulting timing error is typical for tickless
idle.  The error (commonly known as drift or slippage in kernel time)
caused by this strategy is equivalent to one or two counts in
ulStoppedTimerCompensation.

This commit also updates comments and #define symbols related to the
SysTick clock option.  The SysTick can optionally be clocked by a
divided version of the CPU clock (commonly divide-by-8).  The new code
in this commit adjusts these comments and symbols to make them clearer
and more useful in configurations that use the divided clock.  The fix
made in this commit requires the use of these symbols, as noted in the
code comments.

* Fix tickless idle with alternate systick clocking

Prior to this commit, in configurations using the alternate SysTick
clocking, vPortSuppressTicksAndSleep() might cause xTickCount to jump
ahead as much as the entire expected idle time or fall behind as much
as one full tick compared to time as measured by the SysTick.

SysTick
-------
The SysTick is the hardware timer that provides the OS tick interrupt
in the official ports for Cortex M. SysTick starts counting down from
the value stored in its reload register. When SysTick reaches zero, it
requests an interrupt. On the next SysTick clock cycle, it loads the
counter again from the reload register. The SysTick has a configuration
option to be clocked by an alternate clock besides the core clock.
This alternate clock is MCU dependent.

Scenarios Fixed
---------------
The new code in this commit handles the following scenarios that were
not handled correctly prior to this commit.

1. Before the sleep, vPortSuppressTicksAndSleep() stops the SysTick on
zero, long after SysTick reached zero.  Prior to this commit, this
scenario caused xTickCount to jump ahead one full tick for the same
reason documented here: https://github.com/FreeRTOS/FreeRTOS-Kernel/pull/59/commits/0c7b04bd3a745c52151abebc882eed3f811c4c81

2. After the sleep, vPortSuppressTicksAndSleep() stops the SysTick
before it loads the counter from the reload register.  Prior to this
commit, this scenario caused xTickCount to jump ahead by the entire
expected idle time (xExpectedIdleTime) because the current-count
register is zero before it loads from the reload register.

3. Prior to return, vPortSuppressTicksAndSleep() attempts to start a
short SysTick period when the current SysTick clock cycle has a lot of
time remaining.  Prior to this commit, this scenario could cause
xTickCount to fall behind by as much as nearly one full tick because the
short SysTick cycle never started.

Note that #3 is partially fixed by https://github.com/FreeRTOS/FreeRTOS-Kernel/pull/59/commits/967acc9b200d3d4beeb289d9da9e88798074b431
even though that commit addresses a different issue.  So this commit
completes the partial fix.

* Improve comments and name of preprocessor symbol

Add a note in the code comments that SysTick requests an interrupt when
decrementing from 1 to 0, so that's why stopping SysTick on zero is a
special case.  Readers might unknowingly assume that SysTick requests
an interrupt when wrapping from 0 back to the load-register value.

Reconsider new "_SETTING" suffix since "_CONFIG" suffix seems more
descriptive.  The code relies on *both* of these preprocessor symbols:

portNVIC_SYSTICK_CLK_BIT
portNVIC_SYSTICK_CLK_BIT_CONFIG  **new**

A meaningful suffix is really helpful to distinguish the two symbols.

* Revert introduction of 2nd name for NVIC register

When I added portNVIC_ICSR_REG I didn't realize there was already a
portNVIC_INT_CTRL_REG, which identifies the same register.  Not good
to have both.  Note that portNVIC_INT_CTRL_REG is defined in portmacro.h
and is already used in this file (port.c).

* Replicate to other Cortex M ports

Also set a new fiddle factor based on tests with a CM4F.  I used gcc,
optimizing at -O1.  Users can fine-tune as needed.

Also add configSYSTICK_CLOCK_HZ to the CM0 ports to be just like the
other Cortex M ports.  This change allowed uniformity in the default
tickless implementations across all Cortex M ports.  And CM0 is likely
to benefit from configSYSTICK_CLOCK_HZ, especially considering new CM0
devices with very fast CPU clock speeds.

* Revert changes to IAR-CM0-portmacro.h

portNVIC_INT_CTRL_REG was already defined in port.c.  No need to define
it in portmacro.h.

* Handle edge cases with slow SysTick clock

Co-authored-by: Cobus van Eeden <35851496+cobusve@users.noreply.github.com>
Co-authored-by: abhidixi11 <44424462+abhidixi11@users.noreply.github.com>
Co-authored-by: Joseph Julicher <jjulicher@mac.com>
Co-authored-by: alfred gedeon <28123637+alfred2g@users.noreply.github.com>

* Merge SMP commit 45dd83a8e

* 45dd83a8e | 2022-06-09 | Fix RP2040 assertion due to yield spin lock info being wrongly shared between multiple cores (#501)

* Merge SMP b87dfa3e9

* b87dfa3e9 | 2022-06-04 | RP2040: Allow FreeRTOS to be added to the parent CMake project post initialization of the Pico SDK

* Merge SMP 13f034eb7

* 13f034eb7 | 2022-06-24 | RP2040: Fix compiler warning and comment (#509)

* Fix compiler warning and spelling

* Fix Add new task for single core when scheduler not running

* Fix priority set when task is not in ready list for single core

* Fix vTaskResume when task is not running

* Fix uncrustify formating warning

* Add portCHECK_IF_IN_ISR for SMP

* Format vTaskSwitchContext

* Fix vTaskSwitchContextForCore bug due to uncrustify

* First review - did not build yet

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Corresponding changes in FreeRTOS.h and task.h

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Fix the single core compilation

* vTaskSwtichContextForCore rename vTaskSwitchContext
* vTaskYieldWithinAPI for single core
* pxCurrentTCBs for single core in xTaskIncrementTick

* Fix compilation warning

* Update xTaskGetCurrentTaskHandleCPU API

* Use BaseType_t instead of UBaseType_t

* Make the list traverse loop more readable

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Remove unnecessary loop in xTaskIncrementTick for single core

* Update uxSchedulerSuspended with ISR lock in prvCheckForRunStateChange

* Updated ESP32 port-layer to ESP-IDF `v4.4.2` (#572)

* Xtensa_ESP32: Added esp-idf v4.4.2 specific changes

* Xtensa_ESP32: Updated SPDX license identifiers

* Add warning message to ensure min stack size (#575)

Co-authored-by: alfred gedeon <28123637+alfred2g@users.noreply.github.com>

* Removed the 'configASSERT( xInheritanceOccurred == pdFALSE )' assertion from xQueueSemaphoreTake as the reasoning behind it is wrong; it can trigger on wrongly on highly-contested semaphores on multicore systems. See https://forums.freertos.org/t/15967 (#576)

Co-authored-by: Niklas Gürtler <niklas.guertler@tacterion.com>

* Update the NIOSII port to enable longer jumps (#578)

Update the NIOSII port so it works on systems with more RAM as
per https://forums.freertos.org/t/nios-ii-r-nios2-call26-noat-linker-error/16028

* Update Cortex-M55 and Cortex-M85 ports (#579)

These were missed when PR #59 was merged.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Fix context switch when time slicing is off (#568)

* Fix context switch when time slicing is off

When time slicing is off, context switch should only happen when a
task with priority higher than the currently executing one is unblocked.
Earlier the code was invoking a context switch even when a task with
priority equal the currently executing task was unblocked. This commit
fixes the code to only do a context switch when a higher priority
task is unblocked.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Merge commit "Add support for retrieving a task's uxCoreAffinityMask
with the vTaskGetInfo() API"

* Merge commit 8128208bdee1f997f83cae631b861f36aeea9b1f

* Use taskENTER/EXIT_CRITICAL_FROM_ISR (#38)

* Enter critical section from is implemented differently for single core
  and smp. Use taskENTER/EXIT_CRITICAL_FROM_ISR in source.

* Improve single core unit test coverage (#42)

* prvCreateIldeTask use configNUM_CORES
* First time yield in idle task in SMP only
* prvCheckTasksWaitingTermination check pxTCB NULL pointer for SMP only.
  Single core won't have to check the pxTCB

* Yield for task when core affinity changed (#41)

* Yield for task when the task is linked to new allowed cores

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>

* Remove builtin clz in prvSelectHighestPriorityTask (#37)

* Remove builtin clz in prvSelectHighestPriorityTask

* Move critical nesting count to port (#47)

* Move the critical nesting management to port layer

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Move critical nesting in TCB macro to tasks.c

* Add RP2040 support maintain critical nesting count in TCB

* Fix formatting

* RP2040 maintain critical nesting count in port

* Fix constant type

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>

* Rename config num cores (#48)

* Rename configNUM_CORES to configNUMBER_OF_CORES

* Fix the task selection when task yields (#54)

* Move xTaskIncrementTick critical section to port (#55)

* Port should use taskENTER/EXIT_CRITICAL_FROM_ISR

* Not preempt equal priority task in the following functions (#56)

Not to preempt equal priority task in the following functions
* vTaskResume
* vTaskResumeFromISR
* vTaskPrioritySet
* vTaskCoreAffinitySet

* Remove implicit test (#49)

* Remove taskTASK_IS_RUNNING implicit test
* Remove portCHECK_IF_IN_ISR implicit test
* Fix taskVALID_CORE_ID implicit test
* Remove configASSERT implicit test

* Fix preempt equal priority task in xTaskIncrementTick (#58)

* Not preempt equal priority when a task is removed from delay list.
  Process time sharing is handle in the logic below.
* Remove the xPreemptEqualPriority parameter of prvYieldForTask

* Remove prvSelectHighestPriorityTask call in vTaskSuspend (#59)

* Every core starts with an idle task in SMP implementation and
  taskTASK_IS_RUNNING only return ture when the task is idle task before
  scheduler started. So prvSelectHighestPriorityTask won't be called in
  vTaskSuspend before scheduler started.
* Update prvSelectHighestPriorityTask to ensure that this function is
  called only when scheduler started.

* Adding portIDLE_TASK_TEST_MOCK in idle task function (#66)

* Adding configIDLE_TASK_HOOK in idle task function

* Add INFINITE_LOOP macro to test idle task function (#67)

* Remove configIDLE_TASK_HOOK
* Add INFINIT_LOOP. Unit test can redefine this macro to mock the
function.

* portYield is not called when exit critical section from ISR (#60)

* Reference SMP branch

* Fix list index is moved in prvSearchForNameWithinSingleList (#61)

* index pointer should not be moved in SMP

* Yield for priority inherit and disinherit (#64)

* Yield the core runs the task with prority changed when priority
  inheritance and disinheritance.

* fix performance counting for SMP (#65)

* performance counting: ulTaskSwitchedInTime and ulTotalRunTime must be (#618)

arrays, index is core number

---------

Co-authored-by: Hardy Griech <ntbox@gmx.net>

* Remomve unreachable assert in prvCheckForRunStateChange (#68)

* Previous assert already ensure this assert won't be triggered

* Remove unreachable code in preYieldForTask (#69)

* xLowestPriorityCore index can't be greater than configNUMBER_OF_CORES

* Add first version of XCOREAI port (#63)

* xTaskIncrementTick need to be called in critical section
* Rename configNUM_CORES to configNUMBER_OF_CORES
* Define portENTER/EXIT_CRITICAL_FROM_ISR for SMP
* portSET/CLEAR_INTERRUPT_MASK_FROM_ISR is not used in SMP

* Fix configDEINIT_TLS_BLOCK (#73)

configDEINIT_TLS_BLOCK() should deinit the TLS block of the task to being
deleted instead of the currently running task.

* Sync with main branch (#71)

* Fix array-bounds compiler warning on gcc11+ in list.h (#580)

listGET_OWNER_OF_NEXT_ENTRY computes `( pxConstList )->pxIndex->pxNext` after
verifying that `( pxConstList )->pxIndex` points to `xListEnd`, which due to
being a MiniListItem_t, can be shorter than a ListItem_t. Thus,
`( pxConstList )->pxIndex` is a `ListItem_t *` that extends past the end of the
`List_t` whose `xListEnd` it points to. This is fixed by accessing `pxNext`
through a `MiniListItem_t` instead.

* move the prototype for vApplicationIdleHook to task.h. (#600)

Co-authored-by: pluess <pluess@faulhorn.mw.iap.unibe.ch>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

* Update equal priority task preemption (#603)

* vTaskResume and vTaskPrioritySet don't preempt equal priority task

* Update vTaskResumeAll not to preempt task with equal priority

* Fix in xTaskResumeFromISR

* Update FreeRTOS/FreeRTOS build checks (#613)

This is needed to be compatible with the refactoring done in this
PR - https://github.com/FreeRTOS/FreeRTOS/pull/889

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Add ulTaskGetRunTimeCounter and ulTaskGetRunTimePercent (#611)

Allow ulTaskGetIdleRunTimeCounter and ulTaskGetIdleRunTimePercent to be
used whenever configGENERATE_RUN_TIME_STATS is enabled, as this is the
only requirement for these functions to work.

* Fix some CMake documentation typos (#616)

The quick start instructions for CMake mention the "master"
git branch which has been replaced by "main" in the current
repo.

The main CMakeLists.txt documents how to integrate a
custom port. Fix a typo in the suggested CMake code.

* Added support of 64bit events. (#597)

* Added support of 64bit even

Signed-off-by: Cervenka Dusan <cervenka@acrios.com>

* Added missing brackets

Signed-off-by: Cervenka Dusan <cervenka@acrios.com>

* Made proper name for tick macro.

Signed-off-by: Cervenka Dusan <cervenka@acrios.com>

* Improved macro evaluation

Signed-off-by: Cervenka Dusan <cervenka@acrios.com>

* Fixed missed port files  + documentation

Signed-off-by: Cervenka Dusan <cervenka@acrios.com>

* Changes made on PR

Signed-off-by: Cervenka Dusan <cervenka@acrios.com>

* Fix macro definition.

Signed-off-by: Cervenka Dusan <cervenka@acrios.com>

* Formatted code with uncrustify

Signed-off-by: Cervenka Dusan <cervenka@acrios.com>

---------

Signed-off-by: Cervenka Dusan <cervenka@acrios.com>

* Introduce portMEMORY_BARRIER for Microblaze port. (#621)

The introduction of `portMEMORY_BARRIER` will ensure
the places in the kernel use a barrier will work.
For example, `xTaskResumeAll` has a memory barrier
to ensure its correctness when compiled with optimization
enabled. Without the barrier `xTaskResumeAll` can fail
(e.g. start reading and writing to address 0 and/or
infinite looping) when `xPendingReadyList` contains more
than one task to restore.

In `xTaskResumeAll` the compiler chooses to cache the
`pxTCB` the first time through the loop for use
in every subsequent loop. This is incorrect as the
removal of `pxTCB->xEventListItem` will actually
change the value of `pxTCB` if it was read again
at the top of the loop. The barrier forces the compiler
to read `pxTCB` again at the top of the loop.

The compiler is operating correctly. The removal
`pxTCB->xEventListItem` executes on a `List_t *`
and `ListItem_t *`.  This means that the compiler
can assume that any `MiniListItem_t` values are
unchanged by the loop (i.e. "strict-aliasing").
This allows the compiler to cache `pxTCB` as it
is obtained via a `MiniListItem_t`. This is incorrect
in this case because it is possible for a `ListItem_t *`
to actually alias a `MiniListItem_t`. This is technically
a "violation of aliasing rules" so we use the the barrier
to disable the strict-aliasing optimization in this loop.

* Do not call exit() on MSVC Port when calling vPortEndScheduler (#624)

* make port exitable

* correctly set xPortRunning to False

* add suggestions from Review

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

* add suggestions from Review

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

---------

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

* Update PR template to include checkbox for Unit Test related changes (#627)

* Fix build failure introduced in PR #597 (#629)

The PR #597 introduced a new config option configTICK_TYPE_WIDTH_IN_BITS
which can be defined to one of the following:
* TICK_TYPE_WIDTH_16_BITS - Tick type is 16 bit wide.
* TICK_TYPE_WIDTH_32_BITS - Tick type is 32 bit wide.
* TICK_TYPE_WIDTH_64_BITS - Tick type is 64 bit wide.

Earlier we supported 16 and 32 bit width for tick type which was
controlled using the config option configUSE_16_BIT_TICKS. The PR
tried to maintain backward compatibility by honoring
configUSE_16_BIT_TICKS. The backward compatibility did not work as
expected though, as the macro configTICK_TYPE_WIDTH_IN_BITS was used
before it was defined. This PR addresses it by ensuring that the macro
configTICK_TYPE_WIDTH_IN_BITS is defined before it is used.

Testing
1. configUSE_16_BIT_TICKS is defined to 0.

Source (function xTaskIncrementTick in tasks.c):
```
const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
```

Assembly:
```
109e:       4b50            ldr     r3, [pc, #320]  ; (11e0 <xTaskIncrementTick+0x150>)
10a0:       f8d3 4134       ldr.w   r4, [r3, #308]  ; 0x134
10a4:       3401            adds    r4, #1
10a6:       f8c3 4134       str.w   r4, [r3, #308]  ; 0x134
```

It is clear from assembly that the tick type is 32 bit.

2. configUSE_16_BIT_TICKS is defined to 1.

Source (function xTaskIncrementTick in tasks.c):
```
const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
```

Assembly:
```
10e2:       4b53            ldr     r3, [pc, #332]  ; (1230 <xTaskIncrementTick+0x15c>)
10e4:       f8b3 4134       ldrh.w  r4, [r3, #308]  ; 0x134
10e8:       b2a4            uxth    r4, r4
10ea:       3401            adds    r4, #1
10ec:       b2a4            uxth    r4, r4
10ee:       f8a3 4134       strh.w  r4, [r3, #308]  ; 0x134
```

It is clear from assembly that the tick type is 16 bit.

3. configTICK_TYPE_WIDTH_IN_BITS is defined to TICK_TYPE_WIDTH_16_BITS.

Source (function xTaskIncrementTick in tasks.c):
```
const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
```

Assembly:
```
10e2:       4b53            ldr     r3, [pc, #332]  ; (1230 <xTaskIncrementTick+0x15c>)
10e4:       f8b3 4134       ldrh.w  r4, [r3, #308]  ; 0x134
10e8:       b2a4            uxth    r4, r4
10ea:       3401            adds    r4, #1
10ec:       b2a4            uxth    r4, r4
10ee:       f8a3 4134       strh.w  r4, [r3, #308]  ; 0x134
```

It is clear from assembly that the tick type is 16 bit.

4. configTICK_TYPE_WIDTH_IN_BITS is defined to TICK_TYPE_WIDTH_32_BITS.

Source (function xTaskIncrementTick in tasks.c):
```
const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
```

Assembly:
```
109e:       4b50            ldr     r3, [pc, #320]  ; (11e0 <xTaskIncrementTick+0x150>)
10a0:       f8d3 4134       ldr.w   r4, [r3, #308]  ; 0x134
10a4:       3401            adds    r4, #1
10a6:       f8c3 4134       str.w   r4, [r3, #308]  ; 0x134
```

It is clear from assembly that the tick type is 32 bit.

5. configTICK_TYPE_WIDTH_IN_BITS is defined to TICK_TYPE_WIDTH_64_BITS.

```
 #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
```

The testing was done for GCC/ARM_CM3 port which does not support 64 bit
tick type.

6. Neither configUSE_16_BIT_TICKS nor configTICK_TYPE_WIDTH_IN_BITS
defined.

```
 #error Missing definition:  One of configUSE_16_BIT_TICKS and
 configTICK_TYPE_WIDTH_IN_BITS must be defined in FreeRTOSConfig.h.
 See the Configuration section of the FreeRTOS API documentation for
 details.
```

7. Both configUSE_16_BIT_TICKS and configTICK_TYPE_WIDTH_IN_BITS defined.

```
 #error Only one of configUSE_16_BIT_TICKS and
 configTICK_TYPE_WIDTH_IN_BITS must be defined in FreeRTOSConfig.h.
 See the Configuration section of the FreeRTOS API documentation for
 details.
```

Related issue - https://github.com/FreeRTOS/FreeRTOS-Kernel/issues/628

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Feature/fixing clang gnu compiler warnings (#620)

* Adding in ability to support a library for freertos_config and a custom freertos_kernel_port (#558)

* Using single name definition for libraries everywhere. (#558)

* Supporting backwards compatibility with FREERTOS_CONFIG_FILE_DIRECTORY (#571)

* Removing compiler warnings for GNU and Clang. (#571)

* Added in documentation on how to consume from a main project. Added default PORT selection for native POSIX and MINGW platforms.

* Only adding freertos_config if it exists. Removing auto generation of it from a FREERTOS_CONFIG_FILE_DIRECTORY.

* Fixing clang and gnu compiler warnings.

* Adding in project information and how to compile for GNU/clang

* Fixing compiler issue with unused variable - no need to declare variable.

* Adding in compile warnings for linux builds that kernel is okay with using.

* Fixing more extra-semi-stmt clang warnings.

* Moving definition of hooks into header files if features are enabled.

* Fixing formatting with uncrustify.

* Fixing merge conflicts with main merge.

* Fixing compiler errors due to merge issues and formatting.

* Fixing Line feeds.

* Adding 'portNORETURN' into portmacros.h. Other Updates based on PR request

* Further clean-up of clang and clang-tidy issues.

* Removing compiler specific pragmas from common c files.

* Fixing missing lexicon entry and uncrustify formatting changes.

* Resolving merge issue multiple defnitions of proto for prvIdleTask

* Fixing formatting issues that are not covered by uncrustify. Use clang-tidy instead if you want this level of control.

* More uncrustify formatting issues.

* Fixing extra bracket in #if statement.

---------

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

* POSIX port fixes (#626)

* Fix types in POSIX port

Use TaskFunction_t and StackType_t as other ports do.

* Fix portTICK_RATE_MICROSECONDS in POSIX port

---------

Co-authored-by: Jacques GUILLOU <jacques.guillou.job@gmail.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

* Cortex-M35P: Add Cortex-M35P port (#631)

* Cortex-M35P: Add Cortex-M35P port

The Cortex-M35P support added to kernel. The port hasn't been
validated yet with TF-M. Hence TF-M support is not included in this
port.

Signed-off-by: Devaraj Ranganna <devaraj.ranganna@arm.com>

* Add portNORETURN to the newly added portmacro.h

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Devaraj Ranganna <devaraj.ranganna@arm.com>
Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: kar-rahul-aws <118818625+kar-rahul-aws@users.noreply.github.com>

* Introduced Github Status Badge for Unit Tests (#634)

* Introduced Github Status Badge for Unit Tests

* Github status badge to point to latest run

* Github status badge UT points to latest results

* Fixed URL for Github Status badge

---------

Co-authored-by: kar-rahul-aws <118818625+kar-rahul-aws@users.noreply.github.com>

* Remove C99 requirement from CMake file (#633)

* Remove C99 requirement from CMake file

The kernel source is C89 compliant and does not need C99.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Explicitly set C89 requirement for kernel

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Add Thread Local Storage (TLS) support using Picolibc functions (#343)

* Pass top of stack to configINIT_TLS_BLOCK

Picolibc wants to allocate the per-task TLS block within the stack
segment, so it will need to modify the top of stack value. Pass the
pxTopOfStack variable to make this explicit.

Signed-off-by: Keith Packard <keithpac@amazon.com>

* Move newlib-specific definitions to separate file

This reduces the clutter in FreeRTOS.h caused by having newlib-specific
macros present there.

Signed-off-by: Keith Packard <keithpac@amazon.com>

* Make TLS code depend only on configUSE_C_RUNTIME_TLS_SUPPORT

Remove reference to configUSE_NEWLIB_REENTRANT as that only works
when using newlib. configUSE_C_RUNTIME_TLS_SUPPORT is always
set when configUSE_NEWLIB_REENTRANT is set, so using both was
redundant in that case.

Signed-off-by: Keith Packard <keithpac@amazon.com>

* portable-ARC: Adapt ARC support to use generalized TLS support

With generalized thread local storage (TLS) support present in the
core, the two ARC ports need to have the changes to the TCB mirrored
to them.

Signed-off-by: Keith Packard <keithpac@amazon.com>

* Add Thread Local Storage (TLS) support using Picolibc functions

This patch provides definitions of the general TLS support macros in
terms of the Picolibc TLS support functions.

Picolibc is normally configured to use TLS internally for all
variables that are intended to be task-local, so these changes are
necessary for picolibc to work correctly with FreeRTOS.

The picolibc helper functions rely on elements within the linker
script to arrange the TLS data in memory and define some symbols.
Applications wanting to use this mechanism will need changes in their
linker script when migrating to picolibc.

Signed-off-by: Keith Packard <keithpac@amazon.com>

---------

Signed-off-by: Keith Packard <keithpac@amazon.com>
Co-authored-by: Keith Packard <keithpac@amazon.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

* Interrupt priority assert improvements for CM3/4/7 (#602)

* Interrupt priority assert improvements for CM3/4/7

In the ARM_CM3, ARM_CM4, and ARM_CM7 ports, change the assertion that
`configMAX_SYSCALL_INTERRUPT_PRIORITY` is nonzero to account for the
number of priority bits implemented by the hardware.

Change these ports to also use the lowest priority for PendSV and
SysTick, ignoring `configKERNEL_INTERRUPT_PRIORITY`.

* Remove not needed configKERNEL_INTERRUPT_PRIORITY define

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>

* Introduced code coverage status badge (#635)

* Introduced code coverage status badge

* Trying to fix the URL checker issue

* Fix URL check

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

* added portPOINTER_SIZE_TYPE and SIZE_MAX definition to PIC24/dsPIC port (#636)

* added portPOINTER_SIZE_TYPE definition to PIC24/dsPIC port

* Added SIZE_MAX definition to PIC24/dsPIC33

* Fix TLS and stack alignment when using picolibc (#637)

Both the TLS block and stack must be correctly aligned when using
picolibc. The architecture stack alignment is represented by the
portBYTE_ALIGNMENT_MASK and the TLS block alignment is provided by the
Picolibc _tls_align() inline function for Picolibc version 1.8 and
above. For older versions of Picolibc, we'll assume that the TLS block
requires the same alignment as the stack.

For downward growing stacks, this requires aligning the start of the
TLS block to the maximum of the stack alignment and the TLS
alignment. With this, both the TLS block and stack will now be
correctly aligned.

For upward growing stacks, the two areas must be aligned
independently; the TLS block is aligned from the start of the stack,
then the tls space is allocated, and then the stack is aligned above
that.

It's probably useful to know here that the linker ensures that
variables within the TLS block are assigned offsets that match their
alignment requirements. If the TLS block itself is correctly aligned,
then everything within will also be.

I have only tested the downward growing stack branch of this patch.

Signed-off-by: Keith Packard <keithpac@amazon.com>
Co-authored-by: Keith Packard <keithpac@amazon.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

* Enable building the GCC Cortex-R5 port without an FPU (#586)

* Ensure configUSE_TASK_FPU_SUPPORT option is set correctly

If one does enable the FPU of the Cortex-R5 processor, then the GCC
compiler will define the macro __ARM_FP. This can be used to ensure,
that the configUSE_TASK_FPU_SUPPORT is set accordingly.

* Enable the implementation of vPortTaskUsesFPU only if configUSE_TASK_FPU_SUPPORT is set to 1

* Remove error case in pxPortInitialiseStack

The case of configUSE_TASK_FPU_SUPPORT is 0 is now handled

* Enable access to FPU registers only if FPU is enabled

* Make minor formating changes

* Format ARM Cortex-R5 port

* Address review comments from @ChristosZosi

* Minor code review suggestions

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Christos Zosimidis <christos.zosimidis@gmail.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>

* Fix freertos_kernel cmake property, Posix Port (#640)

* Fix freertos_kernel cmake property, Posix Port

* Moves the `set_property()` call below the target definition in top level CMakeLists file
* Corrects billion value from `ULL` suffix (not C90 compliant) to `UL` suffix with cast to uint64_t

* Add blank line to CMakeLists.txt

* Add missing FreeRTOS+ defines

* Run kernel demos and unit tests for PR changes (#645)

* Run kernel demos and unit tests for PR changes

Kernel demos check builds multiple demos from FreeRTOS/FreeRTOS and
unit tests check runs unit tests in FreeRTOS/FreeRTOS. Both of these
checks currently use main branch of FreeRTOS-Kernel. This commits
updates these checks to use the changes in the PR.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Do not specify PR SHA explicitly as that is default

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Remove explicit PR SHA from kernel checks

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Add functions to get the buffers of statically created objects (#641)

Added various ...GetStaticBuffer() functions to get the buffers of statically
created objects.
---------
Co-authored-by: Paul Bartell <pbartell@amazon.com>
Co-authored-by: Nikhil Kamath <110539926+amazonKamath@users.noreply.github.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>

* Cortex-M Assert when NVIC implements 8 PRIO bits (#639)

* Cortex-M Assert when NVIC implements 8 PRIO bits

* Fix CM3 ports

* Fix ARM_CM3_MPU

* Fix ARM CM3

* Fix ARM_CM4_MPU

* Fix ARM_CM4

* Fix GCC ARM_CM7

* Fix IAR ARM ports

* Uncrustify changes

* Fix MikroC_ARM_CM4F port

* Fix MikroC_ARM_CM4F port-(2)

* Fix RVDS ARM ports

* Revert changes for Tasking/ARM_CM4F port

* Revert changes for Tasking/ARM_CM4F port-(2)

* Update port.c

Fix GCC/ARM_CM4F port

* Update port.c

* update GCC\ARM_CM4F port

* update port.c

* Assert to check configMAX_SYSCALL_INTERRUPT_PRIORITY is set to higher priority

* Fix merge error: remove duplicate code

* Fix typos

---------

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Co-authored-by: Ubuntu <ubuntu@ip-172-31-17-174.ec2.internal>

* Remove C90 requirement from CMakeLists (#649)

This is needed as it is breaking projects - https://forums.freertos.org/t/freertos-gcc-cmake/16984

We will re-evaluate and accordingly add this later.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Only add alignment padding when needed (#650)

Heap 4 and Heap 5 add some padding to ensure that the allocated blocks
are always aligned to portBYTE_ALIGNMENT bytes. The code until now was
adding padding always even if the resulting block was already aligned.
This commits updates the code to only add padding if the resulting block
is not aligned.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* add a missing comma (#651)

* fix conversion warning (#658)

FreeRTOS-Kernel/portable/GCC/ARM_CM4F/port.c:399:41: error: conversion from 'uint32_t' {aka 'long unsigned int'} to 'uint8_t' {aka 'unsigned char'} may change value [-Werror=conversion]

Signed-off-by: Vo Trung Chi <chi.votrung@vn.bosch.com>

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Signed-off-by: Cervenka Dusan <cervenka@acrios.com>
Signed-off-by: Devaraj Ranganna <devaraj.ranganna@arm.com>
Signed-off-by: Keith Packard <keithpac@amazon.com>
Signed-off-by: Vo Trung Chi <chi.votrung@vn.bosch.com>
Co-authored-by: Archit Gupta <71798289+archigup@users.noreply.github.com>
Co-authored-by: tcpluess <tpluess@ieee.org>
Co-authored-by: pluess <pluess@faulhorn.mw.iap.unibe.ch>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Co-authored-by: Chris Copeland <chris@chrisnc.net>
Co-authored-by: David J. Fiddes <35607151+davefiddes@users.noreply.github.com>
Co-authored-by: Dusan Cervenka <cervenka@acrios.com>
Co-authored-by: bbain <16752579+bbain@users.noreply.github.com>
Co-authored-by: Ju1He1 <93189163+Ju1He1@users.noreply.github.com>
Co-authored-by: Aniruddha Kanhere <60444055+AniruddhaKanhere@users.noreply.github.com>
Co-authored-by: phelter <paulheltera@gmail.com>
Co-authored-by: jacky309 <jacques.guillou@gmail.com>
Co-authored-by: Jacques GUILLOU <jacques.guillou.job@gmail.com>
Co-authored-by: Devaraj Ranganna <devaraj.ranganna@arm.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: kar-rahul-aws <118818625+kar-rahul-aws@users.noreply.github.com>
Co-authored-by: Nikhil Kamath <110539926+amazonKamath@users.noreply.github.com>
Co-authored-by: Keith Packard <keithp@keithp.com>
Co-authored-by: Keith Packard <keithpac@amazon.com>
Co-authored-by: Joseph Julicher <jjulicher@mac.com>
Co-authored-by: Paul Bartell <pbartell@amazon.com>
Co-authored-by: Christos Zosimidis <christos.zosimidis@gmail.com>
Co-authored-by: Kody Stribrny <89810515+kstribrnAmzn@users.noreply.github.com>
Co-authored-by: Holden <holden-zenithaerotech.com>
Co-authored-by: Darian <32921628+Dazza0@users.noreply.github.com>
Co-authored-by: Ubuntu <ubuntu@ip-172-31-17-174.ec2.internal>
Co-authored-by: Nicolas <nicolas.brunner@heig-vd.ch>
Co-authored-by: Vo Trung Chi <chi.votrung@vn.bosch.com>

* Smp dev merge main 20230410 (#74)

* Fix array-bounds compiler warning on gcc11+ in list.h (#580)

listGET_OWNER_OF_NEXT_ENTRY computes `( pxConstList )->pxIndex->pxNext` after
verifying that `( pxConstList )->pxIndex` points to `xListEnd`, which due to
being a MiniListItem_t, can be shorter than a ListItem_t. Thus,
`( pxConstList )->pxIndex` is a `ListItem_t *` that extends past the end of the
`List_t` whose `xListEnd` it points to. This is fixed by accessing `pxNext`
through a `MiniListItem_t` instead.

* move the prototype for vApplicationIdleHook to task.h. (#600)

Co-authored-by: pluess <pluess@faulhorn.mw.iap.unibe.ch>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

* Update equal priority task preemption (#603)

* vTaskResume and vTaskPrioritySet don't preempt equal priority task

* Update vTaskResumeAll not to preempt task with equal priority

* Fix in xTaskResumeFromISR

* Update FreeRTOS/FreeRTOS build checks (#613)

This is needed to be compatible with the refactoring done in this
PR - https://github.com/FreeRTOS/FreeRTOS/pull/889

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Add ulTaskGetRunTimeCounter and ulTaskGetRunTimePercent (#611)

Allow ulTaskGetIdleRunTimeCounter and ulTaskGetIdleRunTimePercent to be
used whenever configGENERATE_RUN_TIME_STATS is enabled, as this is the
only requirement for these functions to work.

* Fix some CMake documentation typos (#616)

The quick start instructions for CMake mention the "master"
git branch which has been replaced by "main" in the current
repo.

The main CMakeLists.txt documents how to integrate a
custom port. Fix a typo in the suggested CMake code.

* Added support of 64bit events. (#597)

* Added support of 64bit even

Signed-off-by: Cervenka Dusan <cervenka@acrios.com>

* Added missing brackets

Signed-off-by: Cervenka Dusan <cervenka@acrios.com>

* Made proper name for tick macro.

Signed-off-by: Cervenka Dusan <cervenka@acrios.com>

* Improved macro evaluation

Signed-off-by: Cervenka Dusan <cervenka@acrios.com>

* Fixed missed port files  + documentation

Signed-off-by: Cervenka Dusan <cervenka@acrios.com>

* Changes made on PR

Signed-off-by: Cervenka Dusan <cervenka@acrios.com>

* Fix macro definition.

Signed-off-by: Cervenka Dusan <cervenka@acrios.com>

* Formatted code with uncrustify

Signed-off-by: Cervenka Dusan <cervenka@acrios.com>

---------

Signed-off-by: Cervenka Dusan <cervenka@acrios.com>

* Introduce portMEMORY_BARRIER for Microblaze port. (#621)

The introduction of `portMEMORY_BARRIER` will ensure
the places in the kernel use a barrier will work.
For example, `xTaskResumeAll` has a memory barrier
to ensure its correctness when compiled with optimization
enabled. Without the barrier `xTaskResumeAll` can fail
(e.g. start reading and writing to address 0 and/or
infinite looping) when `xPendingReadyList` contains more
than one task to restore.

In `xTaskResumeAll` the compiler chooses to cache the
`pxTCB` the first time through the loop for use
in every subsequent loop. This is incorrect as the
removal of `pxTCB->xEventListItem` will actually
change the value of `pxTCB` if it was read again
at the top of the loop. The barrier forces the compiler
to read `pxTCB` again at the top of the loop.

The compiler is operating correctly. The removal
`pxTCB->xEventListItem` executes on a `List_t *`
and `ListItem_t *`.  This means that the compiler
can assume that any `MiniListItem_t` values are
unchanged by the loop (i.e. "strict-aliasing").
This allows the compiler to cache `pxTCB` as it
is obtained via a `MiniListItem_t`. This is incorrect
in this case because it is possible for a `ListItem_t *`
to actually alias a `MiniListItem_t`. This is technically
a "violation of aliasing rules" so we use the the barrier
to disable the strict-aliasing optimization in this loop.

* Do not call exit() on MSVC Port when calling vPortEndScheduler (#624)

* make port exitable

* correctly set xPortRunning to False

* add suggestions from Review

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

* add suggestions from Review

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

---------

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

* Update PR template to include checkbox for Unit Test related changes (#627)

* Fix build failure introduced in PR #597 (#629)

The PR #597 introduced a new config option configTICK_TYPE_WIDTH_IN_BITS
which can be defined to one of the following:
* TICK_TYPE_WIDTH_16_BITS - Tick type is 16 bit wide.
* TICK_TYPE_WIDTH_32_BITS - Tick type is 32 bit wide.
* TICK_TYPE_WIDTH_64_BITS - Tick type is 64 bit wide.

Earlier we supported 16 and 32 bit width for tick type which was
controlled using the config option configUSE_16_BIT_TICKS. The PR
tried to maintain backward compatibility by honoring
configUSE_16_BIT_TICKS. The backward compatibility did not work as
expected though, as the macro configTICK_TYPE_WIDTH_IN_BITS was used
before it was defined. This PR addresses it by ensuring that the macro
configTICK_TYPE_WIDTH_IN_BITS is defined before it is used.

Testing
1. configUSE_16_BIT_TICKS is defined to 0.

Source (function xTaskIncrementTick in tasks.c):
```
const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
```

Assembly:
```
109e:       4b50            ldr     r3, [pc, #320]  ; (11e0 <xTaskIncrementTick+0x150>)
10a0:       f8d3 4134       ldr.w   r4, [r3, #308]  ; 0x134
10a4:       3401            adds    r4, #1
10a6:       f8c3 4134       str.w   r4, [r3, #308]  ; 0x134
```

It is clear from assembly that the tick type is 32 bit.

2. configUSE_16_BIT_TICKS is defined to 1.

Source (function xTaskIncrementTick in tasks.c):
```
const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
```

Assembly:
```
10e2:       4b53            ldr     r3, [pc, #332]  ; (1230 <xTaskIncrementTick+0x15c>)
10e4:       f8b3 4134       ldrh.w  r4, [r3, #308]  ; 0x134
10e8:       b2a4            uxth    r4, r4
10ea:       3401            adds    r4, #1
10ec:       b2a4            uxth    r4, r4
10ee:       f8a3 4134       strh.w  r4, [r3, #308]  ; 0x134
```

It is clear from assembly that the tick type is 16 bit.

3. configTICK_TYPE_WIDTH_IN_BITS is defined to TICK_TYPE_WIDTH_16_BITS.

Source (function xTaskIncrementTick in tasks.c):
```
const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
```

Assembly:
```
10e2:       4b53            ldr     r3, [pc, #332]  ; (1230 <xTaskIncrementTick+0x15c>)
10e4:       f8b3 4134       ldrh.w  r4, [r3, #308]  ; 0x134
10e8:       b2a4            uxth    r4, r4
10ea:       3401            adds    r4, #1
10ec:       b2a4            uxth    r4, r4
10ee:       f8a3 4134       strh.w  r4, [r3, #308]  ; 0x134
```

It is clear from assembly that the tick type is 16 bit.

4. configTICK_TYPE_WIDTH_IN_BITS is defined to TICK_TYPE_WIDTH_32_BITS.

Source (function xTaskIncrementTick in tasks.c):
```
const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
```

Assembly:
```
109e:       4b50            ldr     r3, [pc, #320]  ; (11e0 <xTaskIncrementTick+0x150>)
10a0:       f8d3 4134       ldr.w   r4, [r3, #308]  ; 0x134
10a4:       3401            adds    r4, #1
10a6:       f8c3 4134       str.w   r4, [r3, #308]  ; 0x134
```

It is clear from assembly that the tick type is 32 bit.

5. configTICK_TYPE_WIDTH_IN_BITS is defined to TICK_TYPE_WIDTH_64_BITS.

```
 #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
```

The testing was done for GCC/ARM_CM3 port which does not support 64 bit
tick type.

6. Neither configUSE_16_BIT_TICKS nor configTICK_TYPE_WIDTH_IN_BITS
defined.

```
 #error Missing definition:  One of configUSE_16_BIT_TICKS and
 configTICK_TYPE_WIDTH_IN_BITS must be defined in FreeRTOSConfig.h.
 See the Configuration section of the FreeRTOS API documentation for
 details.
```

7. Both configUSE_16_BIT_TICKS and configTICK_TYPE_WIDTH_IN_BITS defined.

```
 #error Only one of configUSE_16_BIT_TICKS and
 configTICK_TYPE_WIDTH_IN_BITS must be defined in FreeRTOSConfig.h.
 See the Configuration section of the FreeRTOS API documentation for
 details.
```

Related issue - https://github.com/FreeRTOS/FreeRTOS-Kernel/issues/628

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Feature/fixing clang gnu compiler warnings (#620)

* Adding in ability to support a library for freertos_config and a custom freertos_kernel_port (#558)

* Using single name definition for libraries everywhere. (#558)

* Supporting backwards compatibility with FREERTOS_CONFIG_FILE_DIRECTORY (#571)

* Removing compiler warnings for GNU and Clang. (#571)

* Added in documentation on how to consume from a main project. Added default PORT selection for native POSIX and MINGW platforms.

* Only adding freertos_config if it exists. Removing auto generation of it from a FREERTOS_CONFIG_FILE_DIRECTORY.

* Fixing clang and gnu compiler warnings.

* Adding in project information and how to compile for GNU/clang

* Fixing compiler issue with unused variable - no need to declare variable.

* Adding in compile warnings for linux builds that kernel is okay with using.

* Fixing more extra-semi-stmt clang warnings.

* Moving definition of hooks into header files if features are enabled.

* Fixing formatting with uncrustify.

* Fixing merge conflicts with main merge.

* Fixing compiler errors due to merge issues and formatting.

* Fixing Line feeds.

* Adding 'portNORETURN' into portmacros.h. Other Updates based on PR request

* Further clean-up of clang and clang-tidy issues.

* Removing compiler specific pragmas from common c files.

* Fixing missing lexicon entry and uncrustify formatting changes.

* Resolving merge issue multiple defnitions of proto for prvIdleTask

* Fixing formatting issues that are not covered by uncrustify. Use clang-tidy instead if you want this level of control.

* More uncrustify formatting issues.

* Fixing extra bracket in #if statement.

---------

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

* POSIX port fixes (#626)

* Fix types in POSIX port

Use TaskFunction_t and StackType_t as other ports do.

* Fix portTICK_RATE_MICROSECONDS in POSIX port

---------

Co-authored-by: Jacques GUILLOU <jacques.guillou.job@gmail.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

* Cortex-M35P: Add Cortex-M35P port (#631)

* Cortex-M35P: Add Cortex-M35P port

The Cortex-M35P support added to kernel. The port hasn't been
validated yet with TF-M. Hence TF-M support is not included in this
port.

Signed-off-by: Devaraj Ranganna <devaraj.ranganna@arm.com>

* Add portNORETURN to the newly added portmacro.h

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Devaraj Ranganna <devaraj.ranganna@arm.com>
Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: kar-rahul-aws <118818625+kar-rahul-aws@users.noreply.github.com>

* Introduced Github Status Badge for Unit Tests (#634)

* Introduced Github Status Badge for Unit Tests

* Github status badge to point to latest run

* Github status badge UT points to latest results

* Fixed URL for Github Status badge

---------

Co-authored-by: kar-rahul-aws <118818625+kar-rahul-aws@users.noreply.github.com>

* Remove C99 requirement from CMake file (#633)

* Remove C99 requirement from CMake file

The kernel source is C89 compliant and does not need C99.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Explicitly set C89 requirement for kernel

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Add Thread Local Storage (TLS) support using Picolibc functions (#343)

* Pass top of stack to configINIT_TLS_BLOCK

Picolibc wants to allocate the per-task TLS block within the stack
segment, so it will need to modify the top of stack value. Pass the
pxTopOfStack variable to make this explicit.

Signed-off-by: Keith Packard <keithpac@amazon.com>

* Move newlib-specific definitions to separate file

This reduces the clutter in FreeRTOS.h caused by having newlib-specific
macros present there.

Signed-off-by: Keith Packard <keithpac@amazon.com>

* Make TLS code depend only on configUSE_C_RUNTIME_TLS_SUPPORT

Remove reference to configUSE_NEWLIB_REENTRANT as that only works
when using newlib. configUSE_C_RUNTIME_TLS_SUPPORT is always
set when configUSE_NEWLIB_REENTRANT is set, so using both was
redundant in that case.

Signed-off-by: Keith Packard <keithpac@amazon.com>

* portable-ARC: Adapt ARC support to use generalized TLS support

With generalized thread local storage (TLS) support present in the
core, the two ARC ports need to have the changes to the TCB mirrored
to them.

Signed-off-by: Keith Packard <keithpac@amazon.com>

* Add Thread Local Storage (TLS) support using Picolibc functions

This patch provides definitions of the general TLS support macros in
terms of the Picolibc TLS support functions.

Picolibc is normally configured to use TLS internally for all
variables that are intended to be task-local, so these changes are
necessary for picolibc to work correctly with FreeRTOS.

The picolibc helper functions rely on elements within the linker
script to arrange the TLS data in memory and define some symbols.
Applications wanting to use this mechanism will need changes in their
linker script when migrating to picolibc.

Signed-off-by: Keith Packard <keithpac@amazon.com>

---------

Signed-off-by: Keith Packard <keithpac@amazon.com>
Co-authored-by: Keith Packard <keithpac@amazon.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

* Interrupt priority assert improvements for CM3/4/7 (#602)

* Interrupt priority assert improvements for CM3/4/7

In the ARM_CM3, ARM_CM4, and ARM_CM7 ports, change the assertion that
`configMAX_SYSCALL_INTERRUPT_PRIORITY` is nonzero to account for the
number of priority bits implemented by the hardware.

Change these ports to also use the lowest priority for PendSV and
SysTick, ignoring `configKERNEL_INTERRUPT_PRIORITY`.

* Remove not needed configKERNEL_INTERRUPT_PRIORITY define

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>

* Introduced code coverage status badge (#635)

* Introduced code coverage status badge

* Trying to fix the URL checker issue

* Fix URL check

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

* added portPOINTER_SIZE_TYPE and SIZE_MAX definition to PIC24/dsPIC port (#636)

* added portPOINTER_SIZE_TYPE definition to PIC24/dsPIC port

* Added SIZE_MAX definition to PIC24/dsPIC33

* Fix TLS and stack alignment when using picolibc (#637)

Both the TLS block and stack must be correctly aligned when using
picolibc. The architecture stack alignment is represented by the
portBYTE_ALIGNMENT_MASK and the TLS block alignment is provided by the
Picolibc _tls_align() inline function for Picolibc version 1.8 and
above. For older versions of Picolibc, we'll assume that the TLS block
requires the same alignment as the stack.

For downward growing stacks, this requires aligning the start of the
TLS block to the maximum of the stack alignment and the TLS
alignment. With this, both the TLS block and stack will now be
correctly aligned.

For upward growing stacks, the two areas must be aligned
independently; the TLS block is aligned from the start of the stack,
then the tls space is allocated, and then the stack is aligned above
that.

It's probably useful to know here that the linker ensures that
variables within the TLS block are assigned offsets that match their
alignment requirements. If the TLS block itself is correctly aligned,
then everything within will also be.

I have only tested the downward growing stack branch of this patch.

Signed-off-by: Keith Packard <keithpac@amazon.com>
Co-authored-by: Keith Packard <keithpac@amazon.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

* Enable building the GCC Cortex-R5 port without an FPU (#586)

* Ensure configUSE_TASK_FPU_SUPPORT option is set correctly

If one does enable the FPU of the Cortex-R5 processor, then the GCC
compiler will define the macro __ARM_FP. This can be used to ensure,
that the configUSE_TASK_FPU_SUPPORT is set accordingly.

* Enable the implementation of vPortTaskUsesFPU only if configUSE_TASK_FPU_SUPPORT is set to 1

* Remove error case in pxPortInitialiseStack

The case of configUSE_TASK_FPU_SUPPORT is 0 is now handled

* Enable access to FPU registers only if FPU is enabled

* Make minor formating changes

* Format ARM Cortex-R5 port

* Address review comments from @ChristosZosi

* Minor code review suggestions

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Christos Zosimidis <christos.zosimidis@gmail.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>

* Fix freertos_kernel cmake property, Posix Port (#640)

* Fix freertos_kernel cmake property, Posix Port

* Moves the `set_property()` call below the target definition in top level CMakeLists file
* Corrects billion value from `ULL` suffix (not C90 compliant) to `UL` suffix with cast to uint64_t

* Add blank line to CMakeLists.txt

* Add missing FreeRTOS+ defines

* Run kernel demos and unit tests for PR changes (#645)

* Run kernel demos and unit tests for PR changes

Kernel demos check builds multiple demos from FreeRTOS/FreeRTOS and
unit tests check runs unit tests in FreeRTOS/FreeRTOS. Both of these
checks currently use main branch of FreeRTOS-Kernel. This commits
updates these checks to use the changes in the PR.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Do not specify PR SHA explicitly as that is default

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Remove explicit PR SHA from kernel checks

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Add functions to get the buffers of statically created objects (#641)

Added various ...GetStaticBuffer() functions to get the buffers of statically
created objects.
---------
Co-authored-by: Paul Bartell <pbartell@amazon.com>
Co-authored-by: Nikhil Kamath <110539926+amazonKamath@users.noreply.github.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>

* Cortex-M Assert when NVIC implements 8 PRIO bits (#639)

* Cortex-M Assert when NVIC implements 8 PRIO bits

* Fix CM3 ports

* Fix ARM_CM3_MPU

* Fix ARM CM3

* Fix ARM_CM4_MPU

* Fix ARM_CM4

* Fix GCC ARM_CM7

* Fix IAR ARM ports

* Uncrustify changes

* Fix MikroC_ARM_CM4F port

* Fix MikroC_ARM_CM4F port-(2)

* Fix RVDS ARM ports

* Revert changes for Tasking/ARM_CM4F port

* Revert changes for Tasking/ARM_CM4F port-(2)

* Update port.c

Fix GCC/ARM_CM4F port

* Update port.c

* update GCC\ARM_CM4F port

* update port.c

* Assert to check configMAX_SYSCALL_INTERRUPT_PRIORITY is set to higher priority

* Fix merge error: remove duplicate code

* Fix typos

---------

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Co-authored-by: Ubuntu <ubuntu@ip-172-31-17-174.ec2.internal>

* Remove C90 requirement from CMakeLists (#649)

This is needed as it is breaking projects - https://forums.freertos.org/t/freertos-gcc-cmake/16984

We will re-evaluate and accordingly add this later.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Only add alignment padding when needed (#650)

Heap 4 and Heap 5 add some padding to ensure that the allocated blocks
are always aligned to portBYTE_ALIGNMENT bytes. The code until now was
adding padding always even if the resulting block was already aligned.
This commits updates the code to only add padding if the resulting block
is not aligned.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* add a missing comma (#651)

* fix conversion warning (#658)

FreeRTOS-Kernel/portable/GCC/ARM_CM4F/port.c:399:41: error: conversion from 'uint32_t' {aka 'long unsigned int'} to 'uint8_t' {aka 'unsigned char'} may change value [-Werror=conversion]

Signed-off-by: Vo Trung Chi <chi.votrung@vn.bosch.com>

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Signed-off-by: Cervenka Dusan <cervenka@acrios.com>
Signed-off-by: Devaraj Ranganna <devaraj.ranganna@arm.com>
Signed-off-by: Keith Packard <keithpac@amazon.com>
Signed-off-by: Vo Trung Chi <chi.votrung@vn.bosch.com>
Co-authored-by: Archit Gupta <71798289+archigup@users.noreply.github.com>
Co-authored-by: tcpluess <tpluess@ieee.org>
Co-authored-by: pluess <pluess@faulhorn.mw.iap.unibe.ch>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Co-authored-by: Chris Copeland <chris@chrisnc.net>
Co-authored-by: David J. Fiddes <35607151+davefiddes@users.noreply.github.com>
Co-authored-by: Dusan Cervenka <cervenka@acrios.com>
Co-authored-by: bbain <16752579+bbain@users.noreply.github.com>
Co-authored-by: Ju1He1 <93189163+Ju1He1@users.noreply.github.com>
Co-authored-by: Aniruddha Kanhere <60444055+AniruddhaKanhere@users.noreply.github.com>
Co-authored-by: phelter <paulheltera@gmail.com>
Co-authored-by: jacky309 <jacques.guillou@gmail.com>
Co-authored-by: Jacques GUILLOU <jacques.guillou.job@gmail.com>
Co-authored-by: Devaraj Ranganna <devaraj.ranganna@arm.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: kar-rahul-aws <118818625+kar-rahul-aws@users.noreply.github.com>
Co-authored-by: Nikhil Kamath <110539926+amazonKamath@users.noreply.github.com>
Co-authored-by: Keith Packard <keithp@keithp.com>
Co-authored-by: Keith Packard <keithpac@amazon.com>
Co-authored-by: Joseph Julicher <jjulicher@mac.com>
Co-authored-by: Paul Bartell <pbartell@amazon.com>
Co-authored-by: Christos Zosimidis <christos.zosimidis@gmail.com>
Co-authored-by: Kody Stribrny <89810515+kstribrnAmzn@users.noreply.github.com>
Co-authored-by: Holden <holden-zenithaerotech.com>
Co-authored-by: Darian <32921628+Dazza0@users.noreply.github.com>
Co-authored-by: Ubuntu <ubuntu@ip-172-31-17-174.ec2.internal>
Co-authored-by: Nicolas <nicolas.brunner@heig-vd.ch>
Co-authored-by: Vo Trung Chi <chi.votrung@vn.bosch.com>

* Not yield for running task in prvYieldForTask (#72)

* Raise priority of a running task should not alter other cores

* Remove unreachable code in prvSelectHighestPriorityTask (#70)

* Remove unreachable code in prvSelectHighestPriorityTask

* Remove unreachable assert condition

* Update comment

* Move static idle task memory to global scope (#75)

* Update XMOS AICORE conflict (#77)

* Define portBASE_TYPE in XMOS AICORE porting

* Update enter critical from ISR API

* Fix run time stats for SMP (#76)

* Update get idle tasks stats

* Fix get task stats

* Fix missing configNUM_CORES

* Update the uxSchedulerSuspended after prvCheckForRunStateChange (#62)

* Update the uxSchedulerSuspended after the prvCheckForRunStateChange to
  prevent race condition in fromISR APIs

* Fix SMP dev branch CI errors (#79)

* Fix uncrustify

* Update lexicon

* Remove tailing space

* Ignore XMOS AICORE header check

* Fix ulTotalRunTime and ulTaskSwitchedInTime (#80)

* SMP has multiple ulTotalRunTime and ulTaskSwitchedInTime

* Smp dev compelete merge main 20230424 (#78)

* Fix array-bounds compiler warning on gcc11+ in list.h (#580)

listGET_OWNER_OF_NEXT_ENTRY computes `( pxConstList )->pxIndex->pxNext` after
verifying that `( pxConstList )->pxIndex` points to `xListEnd`, which due to
being a MiniListItem_t, can be shorter than a ListItem_t. Thus,
`( pxConstList )->pxIndex` is a `ListItem_t *` that extends past the end of the
`List_t` whose `xListEnd` it points to. This is fixed by accessing `pxNext`
through a `MiniListItem_t` instead.

* move the prototype for vApplicationIdleHook to task.h. (#600)

Co-authored-by: pluess <pluess@faulhorn.mw.iap.unibe.ch>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

* Update equal priority task preemption (#603)

* vTaskResume and vTaskPrioritySet don't preempt equal priority task

* Update vTaskResumeAll not to preempt task with equal priority

* Fix in xTaskResumeFromISR

* Update FreeRTOS/FreeRTOS build checks (#613)

This is needed to be compatible with the refactoring done in this
PR - https://github.com/FreeRTOS/FreeRTOS/pull/889

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Add ulTaskGetRunTimeCounter and ulTaskGetRunTimePercent (#611)

Allow ulTaskGetIdleRunTimeCounter and ulTaskGetIdleRunTimePercent to be
used whenever configGENERATE_RUN_TIME_STATS is enabled, as this is the
only requirement for these functions to work.

* Fix some CMake documentation typos (#616)

The quick start instructions for CMake mention the "master"
git branch which has been replaced by "main" in the current
repo.

The main CMakeLists.txt documents how to integrate a
custom port. Fix a typo in the suggested CMake code.

* Added support of 64bit events. (#597)

* Added support of 64bit even

Signed-off-by: Cervenka Dusan <cervenka@acrios.com>

* Added missing brackets

Signed-off-by: Cervenka Dusan <cervenka@acrios.com>

* Made proper name for tick macro.

Signed-off-by: Cervenka Dusan <cervenka@acrios.com>

* Improved macro evaluation

Signed-off-by: Cervenka Dusan <cervenka@acrios.com>

* Fixed missed port files  + documentation

Signed-off-by: Cervenka Dusan <cervenka@acrios.com>

* Changes made on PR

Signed-off-by: Cervenka Dusan <cervenka@acrios.com>

* Fix macro definition.

Signed-off-by: Cervenka Dusan <cervenka@acrios.com>

* Formatted code with uncrustify

Signed-off-by: Cervenka Dusan <cervenka@acrios.com>

---------

Signed-off-by: Cervenka Dusan <cervenka@acrios.com>

* Introduce portMEMORY_BARRIER for Microblaze port. (#621)

The introduction of `portMEMORY_BARRIER` will ensure
the places in the kernel use a barrier will work.
For example, `xTaskResumeAll` has a memory barrier
to ensure its correctness when compiled with optimization
enabled. Without the barrier `xTaskResumeAll` can fail
(e.g. start reading and writing to address 0 and/or
infinite looping) when `xPendingReadyList` contains more
than one task to restore.

In `xTaskResumeAll` the compiler chooses to cache the
`pxTCB` the first time through the loop for use
in every subsequent loop. This is incorrect as the
removal of `pxTCB->xEventListItem` will actually
change the value of `pxTCB` if it was read again
at the top of the loop. The barrier forces the compiler
to read `pxTCB` again at the top of the loop.

The compiler is operating correctly. The removal
`pxTCB->xEventListItem` executes on a `List_t *`
and `ListItem_t *`.  This means that the compiler
can assume that any `MiniListItem_t` values are
unchanged by the loop (i.e. "strict-aliasing").
This allows the compiler to cache `pxTCB` as it
is obtained via a `MiniListItem_t`. This is incorrect
in this case because it is possible for a `ListItem_t *`
to actually alias a `MiniListItem_t`. This is technically
a "violation of aliasing rules" so we use the the barrier
to disable the strict-aliasing optimization in this loop.

* Do not call exit() on MSVC Port when calling vPortEndScheduler (#624)

* make port exitable

* correctly set xPortRunning to False

* add suggestions from Review

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

* add suggestions from Review

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

---------

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

* Update PR template to include checkbox for Unit Test related changes (#627)

* Fix build failure introduced in PR #597 (#629)

The PR #597 introduced a new config option configTICK_TYPE_WIDTH_IN_BITS
which can be defined to one of the following:
* TICK_TYPE_WIDTH_16_BITS - Tick type is 16 bit wide.
* TICK_TYPE_WIDTH_32_BITS - Tick type is 32 bit wide.
* TICK_TYPE_WIDTH_64_BITS - Tick type is 64 bit wide.

Earlier we supported 16 and 32 bit width for tick type which was
controlled using the config option configUSE_16_BIT_TICKS. The PR
tried to maintain backward compatibility by honoring
configUSE_16_BIT_TICKS. The backward compatibility did not work as
expected though, as the macro configTICK_TYPE_WIDTH_IN_BITS was used
before it was defined. This PR addresses it by ensuring that the macro
configTICK_TYPE_WIDTH_IN_BITS is defined before it is used.

Testing
1. configUSE_16_BIT_TICKS is defined to 0.

Source (function xTaskIncrementTick in tasks.c):
```
const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
```

Assembly:
```
109e:       4b50            ldr     r3, [pc, #320]  ; (11e0 <xTaskIncrementTick+0x150>)
10a0:       f8d3 4134       ldr.w   r4, [r3, #308]  ; 0x134
10a4:       3401            adds    r4, #1
10a6:       f8c3 4134       str.w   r4, [r3, #308]  ; 0x134
```

It is clear from assembly that the tick type is 32 bit.

2. configUSE_16_BIT_TICKS is defined to 1.

Source (function xTaskIncrementTick in tasks.c):
```
const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
```

Assembly:
```
10e2:       4b53            ldr     r3, [pc, #332]  ; (1230 <xTaskIncrementTick+0x15c>)
10e4:       f8b3 4134       ldrh.w  r4, [r3, #308]  ; 0x134
10e8:       b2a4            uxth    r4, r4
10ea:       3401            adds    r4, #1
10ec:       b2a4            uxth    r4, r4
10ee:       f8a3 4134       strh.w  r4, [r3, #308]  ; 0x134
```

It is clear from assembly that the tick type is 16 bit.

3. configTICK_TYPE_WIDTH_IN_BITS is defined to TICK_TYPE_WIDTH_16_BITS.

Source (function xTaskIncrementTick in tasks.c):
```
const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
```

Assembly:
```
10e2:       4b53            ldr     r3, [pc, #332]  ; (1230 <xTaskIncrementTick+0x15c>)
10e4:       f8b3 4134       ldrh.w  r4, [r3, #308]  ; 0x134
10e8:       b2a4            uxth    r4, r4
10ea:       3401            adds    r4, #1
10ec:       b2a4            uxth    r4, r4
10ee:       f8a3 4134       strh.w  r4, [r3, #308]  ; 0x134
```

It is clear from assembly that the tick type is 16 bit.

4. configTICK_TYPE_WIDTH_IN_BITS is defined to TICK_TYPE_WIDTH_32_BITS.

Source (function xTaskIncrementTick in tasks.c):
```
const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
```

Assembly:
```
109e:       4b50            ldr     r3, [pc, #320]  ; (11e0 <xTaskIncrementTick+0x150>)
10a0:       f8d3 4134       ldr.w   r4, [r3, #308]  ; 0x134
10a4:       3401            adds    r4, #1
10a6:       f8c3 4134       str.w   r4, [r3, #308]  ; 0x134
```

It is clear from assembly that the tick type is 32 bit.

5. configTICK_TYPE_WIDTH_IN_BITS is defined to TICK_TYPE_WIDTH_64_BITS.

```
 #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
```

The testing was done for GCC/ARM_CM3 port which does not support 64 bit
tick type.

6. Neither configUSE_16_BIT_TICKS nor configTICK_TYPE_WIDTH_IN_BITS
defined.

```
 #error Missing definition:  One of configUSE_16_BIT_TICKS and
 configTICK_TYPE_WIDTH_IN_BITS must be defined in FreeRTOSConfig.h.
 See the Configuration section of the FreeRTOS API documentation for
 details.
```

7. Both configUSE_16_BIT_TICKS and configTICK_TYPE_WIDTH_IN_BITS defined.

```
 #error Only one of configUSE_16_BIT_TICKS and
 configTICK_TYPE_WIDTH_IN_BITS must be defined in FreeRTOSConfig.h.
 See the Configuration section of the FreeRTOS API documentation for
 details.
```

Related issue - https://github.com/FreeRTOS/FreeRTOS-Kernel/issues/628

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Feature/fixing clang gnu compiler warnings (#620)

* Adding in ability to support a library for freertos_config and a custom freertos_kernel_port (#558)

* Using single name definition for libraries everywhere. (#558)

* Supporting backwards compatibility with FREERTOS_CONFIG_FILE_DIRECTORY (#571)

* Removing compiler warnings for GNU and Clang. (#571)

* Added in documentation on how to consume from a main project. Added default PORT selection for native POSIX and MINGW platforms.

* Only adding freertos_config if it exists. Removing auto generation of it from a FREERTOS_CONFIG_FILE_DIRECTORY.

* Fixing clang and gnu compiler warnings.

* Adding in project information and how to compile for GNU/clang

* Fixing compiler issue with unused variable - no need to declare variable.

* Adding in compile warnings for linux builds that kernel is okay with using.

* Fixing more extra-semi-stmt clang warnings.

* Moving definition of hooks into header files if features are enabled.

* Fixing formatting with uncrustify.

* Fixing merge conflicts with main merge.

* Fixing compiler errors due to merge issues and formatting.

* Fixing Line feeds.

* Adding 'portNORETURN' into portmacros.h. Other Updates based on PR request

* Further clean-up of clang and clang-tidy issues.

* Removing compiler specific pragmas from common c files.

* Fixing missing lexicon entry and uncrustify formatting changes.

* Resolving merge issue multiple defnitions of proto for prvIdleTask

* Fixing formatting issues that are not covered by uncrustify. Use clang-tidy instead if you want this level of control.

* More uncrustify formatting issues.

* Fixing extra bracket in #if statement.

---------

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

* POSIX port fixes (#626)

* Fix types in POSIX port

Use TaskFunction_t and StackType_t as other ports do.

* Fix portTICK_RATE_MICROSECONDS in POSIX port

---------

Co-authored-by: Jacques GUILLOU <jacques.guillou.job@gmail.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

* Cortex-M35P: Add Cortex-M35P port (#631)

* Cortex-M35P: Add Cortex-M35P port

The Cortex-M35P support added to kernel. The port hasn't been
validated yet with TF-M. Hence TF-M support is not included in this
port.

Signed-off-by: Devaraj Ranganna <devaraj.ranganna@arm.com>

* Add portNORETURN to the newly added portmacro.h

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Devaraj Ranganna <devaraj.ranganna@arm.com>
Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: kar-rahul-aws <118818625+kar-rahul-aws@users.noreply.github.com>

* Introduced Github Status Badge for Unit Tests (#634)

* Introduced Github Status Badge for Unit Tests

* Github status badge to point to latest run

* Github status badge UT points to latest results

* Fixed URL for Github Status badge

---------

Co-authored-by: kar-rahul-aws <118818625+kar-rahul-aws@users.noreply.github.com>

* Remove C99 requirement from CMake file (#633)

* Remove C99 requirement from CMake file

The kernel source is C89 compliant and does not need C99.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Explicitly set C89 requirement for kernel

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Add Thread Local Storage (TLS) support using Picolibc functions (#343)

* Pass top of stack to configINIT_TLS_BLOCK

Picolibc wants to allocate the per-task TLS block within the stack
segment, so it will need to modify the top of stack value. Pass the
pxTopOfStack variable to make this explicit.

Signed-off-by: Keith Packard <keithpac@amazon.com>

* Move newlib-specific definitions to separate file

This reduces the clutter in FreeRTOS.h caused by having newlib-specific
macros present there.

Signed-off-by: Keith Packard <keithpac@amazon.com>

* Make TLS code depend only on configUSE_C_RUNTIME_TLS_SUPPORT

Remove reference to configUSE_NEWLIB_REENTRANT as that only works
when using newlib. configUSE_C_RUNTIME_TLS_SUPPORT is always
set when configUSE_NEWLIB_REENTRANT is set, so using both was
redundant in that case.

Signed-off-by: Keith Packard <keithpac@amazon.com>

* portable-ARC: Adapt ARC support to use generalized TLS support

With generalized thread local storage (TLS) support present in the
core, the two ARC ports need to have the changes to the TCB mirrored
to them.

Signed-off-by: Keith Packard <keithpac@amazon.com>

* Add Thread Local Storage (TLS) support using Picolibc functions

This patch provides definitions of the general TLS support macros in
terms of the Picolibc TLS support functions.

Picolibc is normally configured to use TLS internally for all
variables that are intended to be task-local, so these changes are
necessary for picolibc to work correctly with FreeRTOS.

The picolibc helper functions rely on elements within the linker
script to arrange the TLS data in memory and define some symbols.
Applications wanting to use this mechanism will need changes in their
linker script when migrating to picolibc.

Signed-off-by: Keith Packard <keithpac@amazon.com>

---------

Signed-off-by: Keith Packard <keithpac@amazon.com>
Co-authored-by: Keith Packard <keithpac@amazon.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

* Interrupt priority assert improvements for CM3/4/7 (#602)

* Interrupt priority assert improvements for CM3/4/7

In the ARM_CM3, ARM_CM4, and ARM_CM7 ports, change the assertion that
`configMAX_SYSCALL_INTERRUPT_PRIORITY` is nonzero to account for the
number of priority bits implemented by the hardware.

Change these ports to also use the lowest priority for PendSV and
SysTick, ignoring `configKERNEL_INTERRUPT_PRIORITY`.

* Remove not needed configKERNEL_INTERRUPT_PRIORITY define

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>

* Introduced code coverage status badge (#635)

* Introduced code coverage status badge

* Trying to fix the URL checker issue

* Fix URL check

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

* added portPOINTER_SIZE_TYPE and SIZE_MAX definition to PIC24/dsPIC port (#636)

* added portPOINTER_SIZE_TYPE definition to PIC24/dsPIC port

* Added SIZE_MAX definition to PIC24/dsPIC33

* Fix TLS and stack alignment when using picolibc (#637)

Both the TLS block and stack must be correctly aligned when using
picolibc. The architecture stack alignment is represented by the
portBYTE_ALIGNMENT_MASK and the TLS block alignment is provided by the
Picolibc _tls_align() inline function for Picolibc version 1.8 and
above. For older versions of Picolibc, we'll assume that the TLS block
requires the same alignment as the stack.

For downward growing stacks, this requires aligning the start of the
TLS block to the maximum of the stack alignment and the TLS
alignment. With this, both the TLS block and stack will now be
correctly aligned.

For upward growing stacks, the two areas must be aligned
independently; the TLS block is aligned from the start of the stack,
then the tls space is allocated, and then the stack is aligned above
that.

It's probably useful to know here that the linker ensures that
variables within the TLS block are assigned offsets that match their
alignment requirements. If the TLS block itself is correctly aligned,
then everything within will also be.

I have only tested the downward growing stack branch of this patch.

Signed-off-by: Keith Packard <keithpac@amazon.com>
Co-authored-by: Keith Packard <keithpac@amazon.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

* Enable building the GCC Cortex-R5 port without an FPU (#586)

* Ensure configUSE_TASK_FPU_SUPPORT option is set correctly

If one does enable the FPU of the Cortex-R5 processor, then the GCC
compiler will define the macro __ARM_FP. This can be used to ensure,
that the configUSE_TASK_FPU_SUPPORT is set accordingly.

* Enable the implementation of vPortTaskUsesFPU only if configUSE_TASK_FPU_SUPPORT is set to 1

* Remove error case in pxPortInitialiseStack

The case of configUSE_TASK_FPU_SUPPORT is 0 is now handled

* Enable access to FPU registers only if FPU is enabled

* Make minor formating changes

* Format ARM Cortex-R5 port

* Address review comments from @ChristosZosi

* Minor code review suggestions

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Christos Zosimidis <christos.zosimidis@gmail.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>

* Fix freertos_kernel cmake property, Posix Port (#640)

* Fix freertos_kernel cmake property, Posix Port

* Moves the `set_property()` call below the target definition in top level CMakeLists file
* Corrects billion value from `ULL` suffix (not C90 compliant) to `UL` suffix with cast to uint64_t

* Add blank line to CMakeLists.txt

* Add missing FreeRTOS+ defines

* Run kernel demos and unit tests for PR changes (#645)

* Run kernel demos and unit tests for PR changes

Kernel demos check builds multiple demos from FreeRTOS/FreeRTOS and
unit tests check runs unit tests in FreeRTOS/FreeRTOS. Both of these
checks currently use main branch of FreeRTOS-Kernel. This commits
updates these checks to use the changes in the PR.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Do not specify PR SHA explicitly as that is default

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Remove explicit PR SHA from kernel checks

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Add functions to get the buffers of statically created objects (#641)

Added various ...GetStaticBuffer() functions to get the buffers of statically
created objects.
---------
Co-authored-by: Paul Bartell <pbartell@amazon.com>
Co-authored-by: Nikhil Kamath <110539926+amazonKamath@users.noreply.github.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>

* Cortex-M Assert when NVIC implements 8 PRIO bits (#639)

* Cortex-M Assert when NVIC implements 8 PRIO bits

* Fix CM3 ports

* Fix ARM_CM3_MPU

* Fix ARM CM3

* Fix ARM_CM4_MPU

* Fix ARM_CM4

* Fix GCC ARM_CM7

* Fix IAR ARM ports

* Uncrustify changes

* Fix MikroC_ARM_CM4F port

* Fix MikroC_ARM_CM4F port-(2)

* Fix RVDS ARM ports

* Revert changes for Tasking/ARM_CM4F port

* Revert changes for Tasking/ARM_CM4F port-(2)

* Update port.c

Fix GCC/ARM_CM4F port

* Update port.c

* update GCC\ARM_CM4F port

* update port.c

* Assert to check configMAX_SYSCALL_INTERRUPT_PRIORITY is set to higher priority

* Fix merge error: remove duplicate code

* Fix typos

---------

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Co-authored-by: Ubuntu <ubuntu@ip-172-31-17-174.ec2.internal>

* Remove C90 requirement from CMakeLists (#649)

This is needed as it is breaking projects - https://forums.freertos.org/t/freertos-gcc-cmake/16984

We will re-evaluate and accordingly add this later.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Only add alignment padding when needed (#650)

Heap 4 and Heap 5 add some padding to ensure that the allocated blocks
are always aligned to portBYTE_ALIGNMENT bytes. The code until now was
adding padding always even if the resulting block was already aligned.
This commits updates the code to only add padding if the resulting block
is not aligned.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* add a missing comma (#651)

* fix conversion warning (#658)

FreeRTOS-Kernel/portable/GCC/ARM_CM4F/port.c:399:41: error: conversion from 'uint32_t' {aka 'long unsigned int'} to 'uint8_t' {aka 'unsigned char'} may change value [-Werror=conversion]

Signed-off-by: Vo Trung Chi <chi.votrung@vn.bosch.com>

* ARMv7M: Adjust implemented priority bit assertions (#665)

Adjust assertions related to the CMSIS __NVIC_PRIO_BITS and FreeRTOS
configPRIO_BITS configuration macros such that these macros specify the
minimum number of implemented priority bits supported by a config
build rather than the exact number of implemented priority bits.

Related to Qemu issue #1122

* Format portmacro.h in arm CM0 ports

* portable/ARM_CM0: Add xPortIsInsideInterrupt

Add missing xPortIsInsideInterrupt function to Cortex-M0 port.

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Signed-off-by: Cervenka Dusan <cervenka@acrios.com>
Signed-off-by: Devaraj Ranganna <devaraj.ranganna@arm.com>
Signed-off-by: Keith Packard <keithpac@amazon.com>
Signed-off-by: Vo Trung Chi <chi.votrung@vn.bosch.com>
Co-authored-by: Archit Gupta <71798289+archigup@users.noreply.github.com>
Co-authored-by: tcpluess <tpluess@ieee.org>
Co-authored-by: pluess <pluess@faulhorn.mw.iap.unibe.ch>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Co-authored-by: Chris Copeland <chris@chrisnc.net>
Co-authored-by: David J. Fiddes <35607151+davefiddes@users.noreply.github.com>
Co-authored-by: Dusan Cervenka <cervenka@acrios.com>
Co-authored-by: bbain <16752579+bbain@users.noreply.github.com>
Co-authored-by: Ju1He1 <93189163+Ju1He1@users.noreply.github.com>
Co-authored-by: Aniruddha Kanhere <60444055+AniruddhaKanhere@users.noreply.github.com>
Co-authored-by: phelter <paulheltera@gmail.com>
Co-authored-by: jacky309 <jacques.guillou@gmail.com>
Co-authored-by: Jacques GUILLOU <jacques.guillou.job@gmail.com>
Co-authored-by: Devaraj Ranganna <devaraj.ranganna@arm.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: kar-rahul-aws <118818625+kar-rahul-aws@users.noreply.github.com>
Co-authored-by: Nikhil Kamath <110539926+amazonKamath@users.noreply.github.com>
Co-authored-by: Keith Packard <keithp@keithp.com>
Co-authored-by: Keith Packard <keithpac@amazon.com>
Co-authored-by: Joseph Julicher <jjulicher@mac.com>
Co-authored-by: Paul Bartell <pbartell@amazon.com>
Co-authored-by: Christos Zosimidis <christos.zosimidis@gmail.com>
Co-authored-by: Kody Stribrny <89810515+kstribrnAmzn@users.noreply.github.com>
Co-authored-by: Holden <holden-zenithaerotech.com>
Co-authored-by: Darian <32921628+Dazza0@users.noreply.github.com>
Co-authored-by: Ubuntu <ubuntu@ip-172-31-17-174.ec2.internal>
Co-authored-by: Nicolas <nicolas.brunner@heig-vd.ch>
Co-authored-by: Vo Trung Chi <chi.votrung@vn.bosch.com>

* Update coverity violation for SMP (#81)

* Update coverity violation for SMP ( code surrounded by configNUMBER_OF_CORES > 1 ).
* Single core and common code are still scanned by lint tool.

* Smp dev merge main 0527 (#82)

* Fix array-bounds compiler warning on gcc11+ in list.h (#580)

listGET_OWNER_OF_NEXT_ENTRY computes `( pxConstList )->pxIndex->pxNext` after
verifying that `( pxConstList )->pxIndex` points to `xListEnd`, which due to
being a MiniListItem_t, can be shorter than a ListItem_t. Thus,
`( pxConstList )->pxIndex` is a `ListItem_t *` that extends past the end of the
`List_t` whose `xListEnd` it points to. This is fixed by accessing `pxNext`
through a `MiniListItem_t` instead.

* move the prototype for vApplicationIdleHook to task.h. (#600)

Co-authored-by: pluess <pluess@faulhorn.mw.iap.unibe.ch>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

* Update equal priority task preemption (#603)

* vTaskResume and vTaskPrioritySet don't preempt equal priority task

* Update vTaskResumeAll not to preempt task with equal priority

* Fix in xTaskResumeFromISR

* Update FreeRTOS/FreeRTOS build checks (#613)

This is needed to be compatible with the refactoring done in this
PR - https://github.com/FreeRTOS/FreeRTOS/pull/889

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Add ulTaskGetRunTimeCounter and ulTaskGetRunTimePercent (#611)

Allow ulTaskGetIdleRunTimeCounter and ulTaskGetIdleRunTimePercent to be
used whenever configGENERATE_RUN_TIME_STATS is enabled, as this is the
only requirement for these functions to work.

* Fix some CMake documentation typos (#616)

The quick start instructions for CMake mention the "master"
git branch which has been replaced by "main" in the current
repo.

The main CMakeLists.txt documents how to integrate a
custom port. Fix a typo in the suggested CMake code.

* Added support of 64bit events. (#597)

* Added support of 64bit even

Signed-off-by: Cervenka Dusan <cervenka@acrios.com>

* Added missing brackets

Signed-off-by: Cervenka Dusan <cervenka@acrios.com>

* Made proper name for tick macro.

Signed-off-by: Cervenka Dusan <cervenka@acrios.com>

* Improved macro evaluation

Signed-off-by: Cervenka Dusan <cervenka@acrios.com>

* Fixed missed port files  + documentation

Signed-off-by: Cervenka Dusan <cervenka@acrios.com>

* Changes made on PR

Signed-off-by: Cervenka Dusan <cervenka@acrios.com>

* Fix macro definition.

Signed-off-by: Cervenka Dusan <cervenka@acrios.com>

* Formatted code with uncrustify

Signed-off-by: Cervenka Dusan <cervenka@acrios.com>

---------

Signed-off-by: Cervenka Dusan <cervenka@acrios.com>

* Introduce portMEMORY_BARRIER for Microblaze port. (#621)

The introduction of `portMEMORY_BARRIER` will ensure
the places in the kernel use a barrier will work.
For example, `xTaskResumeAll` has a memory barrier
to ensure its correctness when compiled with optimization
enabled. Without the barrier `xTaskResumeAll` can fail
(e.g. start reading and writing to address 0 and/or
infinite looping) when `xPendingReadyList` contains more
than one task to restore.

In `xTaskResumeAll` the compiler chooses to cache the
`pxTCB` the first time through the loop for use
in every subsequent loop. This is incorrect as the
removal of `pxTCB->xEventListItem` will actually
change the value of `pxTCB` if it was read again
at the top of the loop. The barrier forces the compiler
to read `pxTCB` again at the top of the loop.

The compiler is operating correctly. The removal
`pxTCB->xEventListItem` executes on a `List_t *`
and `ListItem_t *`.  This means that the compiler
can assume that any `MiniListItem_t` values are
unchanged by the loop (i.e. "strict-aliasing").
This allows the compiler to cache `pxTCB` as it
is obtained via a `MiniListItem_t`. This is incorrect
in this case because it is possible for a `ListItem_t *`
to actually alias a `MiniListItem_t`. This is technically
a "violation of aliasing rules" so we use the the barrier
to disable the strict-aliasing optimization in this loop.

* Do not call exit() on MSVC Port when calling vPortEndScheduler (#624)

* make port exitable

* correctly set xPortRunning to False

* add suggestions from Review

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

* add suggestions from Review

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

---------

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

* Update PR template to include checkbox for Unit Test related changes (#627)

* Fix build failure introduced in PR #597 (#629)

The PR #597 introduced a new config option configTICK_TYPE_WIDTH_IN_BITS
which can be defined to one of the following:
* TICK_TYPE_WIDTH_16_BITS - Tick type is 16 bit wide.
* TICK_TYPE_WIDTH_32_BITS - Tick type is 32 bit wide.
* TICK_TYPE_WIDTH_64_BITS - Tick type is 64 bit wide.

Earlier we supported 16 and 32 bit width for tick type which was
controlled using the config option configUSE_16_BIT_TICKS. The PR
tried to maintain backward compatibility by honoring
configUSE_16_BIT_TICKS. The backward compatibility did not work as
expected though, as the macro configTICK_TYPE_WIDTH_IN_BITS was used
before it was defined. This PR addresses it by ensuring that the macro
configTICK_TYPE_WIDTH_IN_BITS is defined before it is used.

Testing
1. configUSE_16_BIT_TICKS is defined to 0.

Source (function xTaskIncrementTick in tasks.c):
```
const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
```

Assembly:
```
109e:       4b50            ldr     r3, [pc, #320]  ; (11e0 <xTaskIncrementTick+0x150>)
10a0:       f8d3 4134       ldr.w   r4, [r3, #308]  ; 0x134
10a4:       3401            adds    r4, #1
10a6:       f8c3 4134       str.w   r4, [r3, #308]  ; 0x134
```

It is clear from assembly that the tick type is 32 bit.

2. configUSE_16_BIT_TICKS is defined to 1.

Source (function xTaskIncrementTick in tasks.c):
```
const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
```

Assembly:
```
10e2:       4b53            ldr     r3, [pc, #332]  ; (1230 <xTaskIncrementTick+0x15c>)
10e4:       f8b3 4134       ldrh.w  r4, [r3, #308]  ; 0x134
10e8:       b2a4            uxth    r4, r4
10ea:       3401            adds    r4, #1
10ec:       b2a4            uxth    r4, r4
10ee:       f8a3 4134       strh.w  r4, [r3, #308]  ; 0x134
```

It is clear from assembly that the tick type is 16 bit.

3. configTICK_TYPE_WIDTH_IN_BITS is defined to TICK_TYPE_WIDTH_16_BITS.

Source (function xTaskIncrementTick in tasks.c):
```
const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
```

Assembly:
```
10e2:       4b53            ldr     r3, [pc, #332]  ; (1230 <xTaskIncrementTick+0x15c>)
10e4:       f8b3 4134       ldrh.w  r4, [r3, #308]  ; 0x134
10e8:       b2a4            uxth    r4, r4
10ea:       3401            adds    r4, #1
10ec:       b2a4            uxth    r4, r4
10ee:       f8a3 4134       strh.w  r4, [r3, #308]  ; 0x134
```

It is clear from assembly that the tick type is 16 bit.

4. configTICK_TYPE_WIDTH_IN_BITS is defined to TICK_TYPE_WIDTH_32_BITS.

Source (function xTaskIncrementTick in tasks.c):
```
const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
```

Assembly:
```
109e:       4b50            ldr     r3, [pc, #320]  ; (11e0 <xTaskIncrementTick+0x150>)
10a0:       f8d3 4134       ldr.w   r4, [r3, #308]  ; 0x134
10a4:       3401            adds    r4, #1
10a6:       f8c3 4134       str.w   r4, [r3, #308]  ; 0x134
```

It is clear from assembly that the tick type is 32 bit.

5. configTICK_TYPE_WIDTH_IN_BITS is defined to TICK_TYPE_WIDTH_64_BITS.

```
 #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
```

The testing was done for GCC/ARM_CM3 port which does not support 64 bit
tick type.

6. Neither configUSE_16_BIT_TICKS nor configTICK_TYPE_WIDTH_IN_BITS
defined.

```
 #error Missing definition:  One of configUSE_16_BIT_TICKS and
 configTICK_TYPE_WIDTH_IN_BITS must be defined in FreeRTOSConfig.h.
 See the Configuration section of the FreeRTOS API documentation for
 details.
```

7. Both configUSE_16_BIT_TICKS and configTICK_TYPE_WIDTH_IN_BITS defined.

```
 #error Only one of configUSE_16_BIT_TICKS and
 configTICK_TYPE_WIDTH_IN_BITS must be defined in FreeRTOSConfig.h.
 See the Configuration section of the FreeRTOS API documentation for
 details.
```

Related issue - https://github.com/FreeRTOS/FreeRTOS-Kernel/issues/628

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Feature/fixing clang gnu compiler warnings (#620)

* Adding in ability to support a library for freertos_config and a custom freertos_kernel_port (#558)

* Using single name definition for libraries everywhere. (#558)

* Supporting backwards compatibility with FREERTOS_CONFIG_FILE_DIRECTORY (#571)

* Removing compiler warnings for GNU and Clang. (#571)

* Added in documentation on how to consume from a main project. Added default PORT selection for native POSIX and MINGW platforms.

* Only adding freertos_config if it exists. Removing auto generation of it from a FREERTOS_CONFIG_FILE_DIRECTORY.

* Fixing clang and gnu compiler warnings.

* Adding in project information and how to compile for GNU/clang

* Fixing compiler issue with unused variable - no need to declare variable.

* Adding in compile warnings for linux builds that kernel is okay with using.

* Fixing more extra-semi-stmt clang warnings.

* Moving definition of hooks into header files if features are enabled.

* Fixing formatting with uncrustify.

* Fixing merge conflicts with main merge.

* Fixing compiler errors due to merge issues and formatting.

* Fixing Line feeds.

* Adding 'portNORETURN' into portmacros.h. Other Updates based on PR request

* Further clean-up of clang and clang-tidy issues.

* Removing compiler specific pragmas from common c files.

* Fixing missing lexicon entry and uncrustify formatting changes.

* Resolving merge issue multiple defnitions of proto for prvIdleTask

* Fixing formatting issues that are not covered by uncrustify. Use clang-tidy instead if you want this level of control.

* More uncrustify formatting issues.

* Fixing extra bracket in #if statement.

---------

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

* POSIX port fixes (#626)

* Fix types in POSIX port

Use TaskFunction_t and StackType_t as other ports do.

* Fix portTICK_RATE_MICROSECONDS in POSIX port

---------

Co-authored-by: Jacques GUILLOU <jacques.guillou.job@gmail.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

* Cortex-M35P: Add Cortex-M35P port (#631)

* Cortex-M35P: Add Cortex-M35P port

The Cortex-M35P support added to kernel. The port hasn't been
validated yet with TF-M. Hence TF-M support is not included in this
port.

Signed-off-by: Devaraj Ranganna <devaraj.ranganna@arm.com>

* Add portNORETURN to the newly added portmacro.h

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Devaraj Ranganna <devaraj.ranganna@arm.com>
Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: kar-rahul-aws <118818625+kar-rahul-aws@users.noreply.github.com>

* Introduced Github Status Badge for Unit Tests (#634)

* Introduced Github Status Badge for Unit Tests

* Github status badge to point to latest run

* Github status badge UT points to latest results

* Fixed URL for Github Status badge

---------

Co-authored-by: kar-rahul-aws <118818625+kar-rahul-aws@users.noreply.github.com>

* Remove C99 requirement from CMake file (#633)

* Remove C99 requirement from CMake file

The kernel source is C89 compliant and does not need C99.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Explicitly set C89 requirement for kernel

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Add Thread Local Storage (TLS) support using Picolibc functions (#343)

* Pass top of stack to configINIT_TLS_BLOCK

Picolibc wants to allocate the per-task TLS block within the stack
segment, so it will need to modify the top of stack value. Pass the
pxTopOfStack variable to make this explicit.

Signed-off-by: Keith Packard <keithpac@amazon.com>

* Move newlib-specific definitions to separate file

This reduces the clutter in FreeRTOS.h caused by having newlib-specific
macros present there.

Signed-off-by: Keith Packard <keithpac@amazon.com>

* Make TLS code depend only on configUSE_C_RUNTIME_TLS_SUPPORT

Remove reference to configUSE_NEWLIB_REENTRANT as that only works
when using newlib. configUSE_C_RUNTIME_TLS_SUPPORT is always
set when configUSE_NEWLIB_REENTRANT is set, so using both was
redundant in that case.

Signed-off-by: Keith Packard <keithpac@amazon.com>

* portable-ARC: Adapt ARC support to use generalized TLS support

With generalized thread local storage (TLS) support present in the
core, the two ARC ports need to have the changes to the TCB mirrored
to them.

Signed-off-by: Keith Packard <keithpac@amazon.com>

* Add Thread Local Storage (TLS) support using Picolibc functions

This patch provides definitions of the general TLS support macros in
terms of the Picolibc TLS support functions.

Picolibc is normally configured to use TLS internally for all
variables that are intended to be task-local, so these changes are
necessary for picolibc to work correctly with FreeRTOS.

The picolibc helper functions rely on elements within the linker
script to arrange the TLS data in memory and define some symbols.
Applications wanting to use this mechanism will need changes in their
linker script when migrating to picolibc.

Signed-off-by: Keith Packard <keithpac@amazon.com>

---------

Signed-off-by: Keith Packard <keithpac@amazon.com>
Co-authored-by: Keith Packard <keithpac@amazon.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

* Interrupt priority assert improvements for CM3/4/7 (#602)

* Interrupt priority assert improvements for CM3/4/7

In the ARM_CM3, ARM_CM4, and ARM_CM7 ports, change the assertion that
`configMAX_SYSCALL_INTERRUPT_PRIORITY` is nonzero to account for the
number of priority bits implemented by the hardware.

Change these ports to also use the lowest priority for PendSV and
SysTick, ignoring `configKERNEL_INTERRUPT_PRIORITY`.

* Remove not needed configKERNEL_INTERRUPT_PRIORITY define

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>

* Introduced code coverage status badge (#635)

* Introduced code coverage status badge

* Trying to fix the URL checker issue

* Fix URL check

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

* added portPOINTER_SIZE_TYPE and SIZE_MAX definition to PIC24/dsPIC port (#636)

* added portPOINTER_SIZE_TYPE definition to PIC24/dsPIC port

* Added SIZE_MAX definition to PIC24/dsPIC33

* Fix TLS and stack alignment when using picolibc (#637)

Both the TLS block and stack must be correctly aligned when using
picolibc. The architecture stack alignment is represented by the
portBYTE_ALIGNMENT_MASK and the TLS block alignment is provided by the
Picolibc _tls_align() inline function for Picolibc version 1.8 and
above. For older versions of Picolibc, we'll assume that the TLS block
requires the same alignment as the stack.

For downward growing stacks, this requires aligning the start of the
TLS block to the maximum of the stack alignment and the TLS
alignment. With this, both the TLS block and stack will now be
correctly aligned.

For upward growing stacks, the two areas must be aligned
independently; the TLS block is aligned from the start of the stack,
then the tls space is allocated, and then the stack is aligned above
that.

It's probably useful to know here that the linker ensures that
variables within the TLS block are assigned offsets that match their
alignment requirements. If the TLS block itself is correctly aligned,
then everything within will also be.

I have only tested the downward growing stack branch of this patch.

Signed-off-by: Keith Packard <keithpac@amazon.com>
Co-authored-by: Keith Packard <keithpac@amazon.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

* Enable building the GCC Cortex-R5 port without an FPU (#586)

* Ensure configUSE_TASK_FPU_SUPPORT option is set correctly

If one does enable the FPU of the Cortex-R5 processor, then the GCC
compiler will define the macro __ARM_FP. This can be used to ensure,
that the configUSE_TASK_FPU_SUPPORT is set accordingly.

* Enable the implementation of vPortTaskUsesFPU only if configUSE_TASK_FPU_SUPPORT is set to 1

* Remove error case in pxPortInitialiseStack

The case of configUSE_TASK_FPU_SUPPORT is 0 is now handled

* Enable access to FPU registers only if FPU is enabled

* Make minor formating changes

* Format ARM Cortex-R5 port

* Address review comments from @ChristosZosi

* Minor code review suggestions

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Christos Zosimidis <christos.zosimidis@gmail.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>

* Fix freertos_kernel cmake property, Posix Port (#640)

* Fix freertos_kernel cmake property, Posix Port

* Moves the `set_property()` call below the target definition in top level CMakeLists file
* Corrects billion value from `ULL` suffix (not C90 compliant) to `UL` suffix with cast to uint64_t

* Add blank line to CMakeLists.txt

* Add missing FreeRTOS+ defines

* Run kernel demos and unit tests for PR changes (#645)

* Run kernel demos and unit tests for PR changes

Kernel demos check builds multiple demos from FreeRTOS/FreeRTOS and
unit tests check runs unit tests in FreeRTOS/FreeRTOS. Both of these
checks currently use main branch of FreeRTOS-Kernel. This commits
updates these checks to use the changes in the PR.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Do not specify PR SHA explicitly as that is default

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Remove explicit PR SHA from kernel checks

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Add functions to get the buffers of statically created objects (#641)

Added various ...GetStaticBuffer() functions to get the buffers of statically
created objects.
---------
Co-authored-by: Paul Bartell <pbartell@amazon.com>
Co-authored-by: Nikhil Kamath <110539926+amazonKamath@users.noreply.github.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>

* Cortex-M Assert when NVIC implements 8 PRIO bits (#639)

* Cortex-M Assert when NVIC implements 8 PRIO bits

* Fix CM3 ports

* Fix ARM_CM3_MPU

* Fix ARM CM3

* Fix ARM_CM4_MPU

* Fix ARM_CM4

* Fix GCC ARM_CM7

* Fix IAR ARM ports

* Uncrustify changes

* Fix MikroC_ARM_CM4F port

* Fix MikroC_ARM_CM4F port-(2)

* Fix RVDS ARM ports

* Revert changes for Tasking/ARM_CM4F port

* Revert changes for Tasking/ARM_CM4F port-(2)

* Update port.c

Fix GCC/ARM_CM4F port

* Update port.c

* update GCC\ARM_CM4F port

* update port.c

* Assert to check configMAX_SYSCALL_INTERRUPT_PRIORITY is set to higher priority

* Fix merge error: remove duplicate code

* Fix typos

---------

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Co-authored-by: Ubuntu <ubuntu@ip-172-31-17-174.ec2.internal>

* Remove C90 requirement from CMakeLists (#649)

This is needed as it is breaking projects - https://forums.freertos.org/t/freertos-gcc-cmake/16984

We will re-evaluate and accordingly add this later.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Only add alignment padding when needed (#650)

Heap 4 and Heap 5 add some padding to ensure that the allocated blocks
are always aligned to portBYTE_ALIGNMENT bytes. The code until now was
adding padding always even if the resulting block was already aligned.
This commits updates the code to only add padding if the resulting block
is not aligned.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* add a missing comma (#651)

* fix conversion warning (#658)

FreeRTOS-Kernel/portable/GCC/ARM_CM4F/port.c:399:41: error: conversion from 'uint32_t' {aka 'long unsigned int'} to 'uint8_t' {aka 'unsigned char'} may change value [-Werror=conversion]

Signed-off-by: Vo Trung Chi <chi.votrung@vn.bosch.com>

* ARMv7M: Adjust implemented priority bit assertions (#665)

Adjust assertions related to the CMSIS __NVIC_PRIO_BITS and FreeRTOS
configPRIO_BITS configuration macros such that these macros specify the
minimum number of implemented priority bits supported by a config
build rather than the exact number of implemented priority bits.

Related to Qemu issue #1122

* Format portmacro.h in arm CM0 ports

* portable/ARM_CM0: Add xPortIsInsideInterrupt

Add missing xPortIsInsideInterrupt function to Cortex-M0 port.

* tree-wide: Unify formatting of __cplusplus ifdefs

* Paranthesize expression-like macro (#668)

* Updated tasks.c checks for scheduler suspension (#670)

This commit updates the checks for the variable uxSchedulerSuspended in
tasks.c module to use a uniform format.

Signed-off-by: Sudeep Mohanty <sudp.mohanty@gmail.com>

* Fix cast alignment warning (#669)

* Fix cast alignment warning

Without this change, the code produces the following warning when
compiled with `-Wcast-align` flag:

```
cast increases required alignment of target type
```

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Align StackSize and StackAddress for macOS (#674)

* Armv8-M (except Cortex-M23) interrupt priority checking (#673)

* Armv8-M: Formatting changes

Signed-off-by: Devaraj Ranganna <devaraj.ranganna@arm.com>

* Armv8-M: Add support for interrupt priority check

FreeRTOS provides `FromISR` system calls which can be called directly
from interrupt service routines. It is crucial that the priority of
these ISRs is set to same or lower value (numerically higher) than that
of `configMAX_SYSCALL_INTERRUPT_PRIORITY`. For more information refer
to https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html.

Add a check to trigger an assert when an ISR with priority higher
(numerically lower) than `configMAX_SYSCALL_INTERRUPT_PRIORITY` calls
`FromISR` system calls if `configASSERT` macro is defined.

In addition, add a config option
`configQEMU_DISABLE_INTERRUPT_PRIO_BITS_CHECK` to disable interrupt
priority check while running on QEMU. Based on the discussion
https://gitlab.com/qemu-project/qemu/-/issues/1122, The interrupt
priority bits in QEMU do not match the real hardware. Therefore the
assert that checks the number of implemented bits and __NVIC_PRIO_BITS
will always fail. The config option
 `configQEMU_DISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the
`FreeRTOSConfig.h` for QEMU targets.

Signed-off-by: Devaraj Ranganna <devaraj.ranganna@arm.com>

* Use SHPR2 for calculating interrupt priority bits

This removes the dependency on the secure software to mark the interrupt
as non-secure.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Devaraj Ranganna <devaraj.ranganna@arm.com>
Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

* Use the extended movx instruction instead of mov (#676)

The following is from the MSP430X instruction set -

```
MOVX.W Move source word to destination word.

The source operand is copied to the destination. The source operand is
not affected. Both operands may be located in the full address space.
```

The movx instruction allows both the operands to be located in the full
address space and therefore, works with large data model as well.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Signed-off-by: Cervenka Dusan <cervenka@acrios.com>
Signed-off-by: Devaraj Ranganna <devaraj.ranganna@arm.com>
Signed-off-by: Keith Packard <keithpac@amazon.com>
Signed-off-by: Vo Trung Chi <chi.votrung@vn.bosch.com>
Signed-off-by: Sudeep Mohanty <sudp.mohanty@gmail.com>
Co-authored-by: Archit Gupta <71798289+archigup@users.noreply.github.com>
Co-authored-by: tcpluess <tpluess@ieee.org>
Co-authored-by: pluess <pluess@faulhorn.mw.iap.unibe.ch>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Co-authored-by: Chris Copeland <chris@chrisnc.net>
Co-authored-by: David J. Fiddes <35607151+davefiddes@users.noreply.github.com>
Co-authored-by: Dusan Cervenka <cervenka@acrios.com>
Co-authored-by: bbain <16752579+bbain@users.noreply.github.com>
Co-authored-by: Ju1He1 <93189163+Ju1He1@users.noreply.github.com>
Co-authored-by: Aniruddha Kanhere <60444055+AniruddhaKanhere@users.noreply.github.com>
Co-authored-by: phelter <paulheltera@gmail.com>
Co-authored-by: jacky309 <jacques.guillou@gmail.com>
Co-authored-by: Jacques GUILLOU <jacques.guillou.job@gmail.com>
Co-authored-by: Devaraj Ranganna <devaraj.ranganna@arm.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: kar-rahul-aws <118818625+kar-rahul-aws@users.noreply.github.com>
Co-authored-by: Nikhil Kamath <110539926+amazonKamath@users.noreply.github.com>
Co-authored-by: Keith Packard <keithp@keithp.com>
Co-authored-by: Keith Packard <keithpac@amazon.com>
Co-authored-by: Joseph Julicher <jjulicher@mac.com>
Co-authored-by: Paul Bartell <pbartell@amazon.com>
Co-authored-by: Christos Zosimidis <christos.zosimidis@gmail.com>
Co-authored-by: Kody Stribrny <89810515+kstribrnAmzn@users.noreply.github.com>
Co-authored-by: Holden <holden-zenithaerotech.com>
Co-authored-by: Darian <32921628+Dazza0@users.noreply.github.com>
Co-authored-by: Ubuntu <ubuntu@ip-172-31-17-174.ec2.internal>
Co-authored-by: Nicolas <nicolas.brunner@heig-vd.ch>
Co-authored-by: Vo Trung Chi <chi.votrung@vn.bosch.com>
Co-authored-by: Sudeep Mohanty <91244425+sudeep-mohanty@users.noreply.github.com>
Co-authored-by: Monika Singh <108652024+moninom1@users.noreply.github.com>

* Merge main to SMP branch (#86)

* Fix array-bounds compiler warning on gcc11+ in list.h (#580)

listGET_OWNER_OF_NEXT_ENTRY computes `( pxConstList )->pxIndex->pxNext` after
verifying that `( pxConstList )->pxIndex` points to `xListEnd`, which due to
being a MiniListItem_t, can be shorter than a ListItem_t. Thus,
`( pxConstList )->pxIndex` is a `ListItem_t *` that extends past the end of the
`List_t` whose `xListEnd` it points to. This is fixed by accessing `pxNext`
through a `MiniListItem_t` instead.

* move the prototype for vApplicationIdleHook to task.h. (#600)

Co-authored-by: pluess <pluess@faulhorn.mw.iap.unibe.ch>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

* Update equal priority task preemption (#603)

* vTaskResume and vTaskPrioritySet don't preempt equal priority task

* Update vTaskResumeAll not to preempt task with equal priority

* Fix in xTaskResumeFromISR

* Update FreeRTOS/FreeRTOS build checks (#613)

This is needed to be compatible with the refactoring done in this
PR - https://github.com/FreeRTOS/FreeRTOS/pull/889

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Add ulTaskGetRunTimeCounter and ulTaskGetRunTimePercent (#611)

Allow ulTaskGetIdleRunTimeCounter and ulTaskGetIdleRunTimePercent to be
used whenever configGENERATE_RUN_TIME_STATS is enabled, as this is the
only requirement for these functions to work.

* Fix some CMake documentation typos (#616)

The quick start instructions for CMake mention the "master"
git branch which has been replaced by "main" in the current
repo.

The main CMakeLists.txt documents how to integrate a
custom port. Fix a typo in the suggested CMake code.

* Added support of 64bit events. (#597)

* Added support of 64bit even

Signed-off-by: Cervenka Dusan <cervenka@acrios.com>

* Added missing brackets

Signed-off-by: Cervenka Dusan <cervenka@acrios.com>

* Made proper name for tick macro.

Signed-off-by: Cervenka Dusan <cervenka@acrios.com>

* Improved macro evaluation

Signed-off-by: Cervenka Dusan <cervenka@acrios.com>

* Fixed missed port files  + documentation

Signed-off-by: Cervenka Dusan <cervenka@acrios.com>

* Changes made on PR

Signed-off-by: Cervenka Dusan <cervenka@acrios.com>

* Fix macro definition.

Signed-off-by: Cervenka Dusan <cervenka@acrios.com>

* Formatted code with uncrustify

Signed-off-by: Cervenka Dusan <cervenka@acrios.com>

---------

Signed-off-by: Cervenka Dusan <cervenka@acrios.com>

* Introduce portMEMORY_BARRIER for Microblaze port. (#621)

The introduction of `portMEMORY_BARRIER` will ensure
the places in the kernel use a barrier will work.
For example, `xTaskResumeAll` has a memory barrier
to ensure its correctness when compiled with optimization
enabled. Without the barrier `xTaskResumeAll` can fail
(e.g. start reading and writing to address 0 and/or
infinite looping) when `xPendingReadyList` contains more
than one task to restore.

In `xTaskResumeAll` the compiler chooses to cache the
`pxTCB` the first time through the loop for use
in every subsequent loop. This is incorrect as the
removal of `pxTCB->xEventListItem` will actually
change the value of `pxTCB` if it was read again
at the top of the loop. The barrier forces the compiler
to read `pxTCB` again at the top of the loop.

The compiler is operating correctly. The removal
`pxTCB->xEventListItem` executes on a `List_t *`
and `ListItem_t *`.  This means that the compiler
can assume that any `MiniListItem_t` values are
unchanged by the loop (i.e. "strict-aliasing").
This allows the compiler to cache `pxTCB` as it
is obtained via a `MiniListItem_t`. This is incorrect
in this case because it is possible for a `ListItem_t *`
to actually alias a `MiniListItem_t`. This is technically
a "violation of aliasing rules" so we use the the barrier
to disable the strict-aliasing optimization in this loop.

* Do not call exit() on MSVC Port when calling vPortEndScheduler (#624)

* make port exitable

* correctly set xPortRunning to False

* add suggestions from Review

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

* add suggestions from Review

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

---------

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

* Update PR template to include checkbox for Unit Test related changes (#627)

* Fix build failure introduced in PR #597 (#629)

The PR #597 introduced a new config option configTICK_TYPE_WIDTH_IN_BITS
which can be defined to one of the following:
* TICK_TYPE_WIDTH_16_BITS - Tick type is 16 bit wide.
* TICK_TYPE_WIDTH_32_BITS - Tick type is 32 bit wide.
* TICK_TYPE_WIDTH_64_BITS - Tick type is 64 bit wide.

Earlier we supported 16 and 32 bit width for tick type which was
controlled using the config option configUSE_16_BIT_TICKS. The PR
tried to maintain backward compatibility by honoring
configUSE_16_BIT_TICKS. The backward compatibility did not work as
expected though, as the macro configTICK_TYPE_WIDTH_IN_BITS was used
before it was defined. This PR addresses it by ensuring that the macro
configTICK_TYPE_WIDTH_IN_BITS is defined before it is used.

Testing
1. configUSE_16_BIT_TICKS is defined to 0.

Source (function xTaskIncrementTick in tasks.c):
```
const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
```

Assembly:
```
109e:       4b50            ldr     r3, [pc, #320]  ; (11e0 <xTaskIncrementTick+0x150>)
10a0:       f8d3 4134       ldr.w   r4, [r3, #308]  ; 0x134
10a4:       3401            adds    r4, #1
10a6:       f8c3 4134       str.w   r4, [r3, #308]  ; 0x134
```

It is clear from assembly that the tick type is 32 bit.

2. configUSE_16_BIT_TICKS is defined to 1.

Source (function xTaskIncrementTick in tasks.c):
```
const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
```

Assembly:
```
10e2:       4b53            ldr     r3, [pc, #332]  ; (1230 <xTaskIncrementTick+0x15c>)
10e4:       f8b3 4134       ldrh.w  r4, [r3, #308]  ; 0x134
10e8:       b2a4            uxth    r4, r4
10ea:       3401            adds    r4, #1
10ec:       b2a4            uxth    r4, r4
10ee:       f8a3 4134       strh.w  r4, [r3, #308]  ; 0x134
```

It is clear from assembly that the tick type is 16 bit.

3. configTICK_TYPE_WIDTH_IN_BITS is defined to TICK_TYPE_WIDTH_16_BITS.

Source (function xTaskIncrementTick in tasks.c):
```
const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
```

Assembly:
```
10e2:       4b53            ldr     r3, [pc, #332]  ; (1230 <xTaskIncrementTick+0x15c>)
10e4:       f8b3 4134       ldrh.w  r4, [r3, #308]  ; 0x134
10e8:       b2a4            uxth    r4, r4
10ea:       3401            adds    r4, #1
10ec:       b2a4            uxth    r4, r4
10ee:       f8a3 4134       strh.w  r4, [r3, #308]  ; 0x134
```

It is clear from assembly that the tick type is 16 bit.

4. configTICK_TYPE_WIDTH_IN_BITS is defined to TICK_TYPE_WIDTH_32_BITS.

Source (function xTaskIncrementTick in tasks.c):
```
const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
```

Assembly:
```
109e:       4b50            ldr     r3, [pc, #320]  ; (11e0 <xTaskIncrementTick+0x150>)
10a0:       f8d3 4134       ldr.w   r4, [r3, #308]  ; 0x134
10a4:       3401            adds    r4, #1
10a6:       f8c3 4134       str.w   r4, [r3, #308]  ; 0x134
```

It is clear from assembly that the tick type is 32 bit.

5. configTICK_TYPE_WIDTH_IN_BITS is defined to TICK_TYPE_WIDTH_64_BITS.

```
 #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
```

The testing was done for GCC/ARM_CM3 port which does not support 64 bit
tick type.

6. Neither configUSE_16_BIT_TICKS nor configTICK_TYPE_WIDTH_IN_BITS
defined.

```
 #error Missing definition:  One of configUSE_16_BIT_TICKS and
 configTICK_TYPE_WIDTH_IN_BITS must be defined in FreeRTOSConfig.h.
 See the Configuration section of the FreeRTOS API documentation for
 details.
```

7. Both configUSE_16_BIT_TICKS and configTICK_TYPE_WIDTH_IN_BITS defined.

```
 #error Only one of configUSE_16_BIT_TICKS and
 configTICK_TYPE_WIDTH_IN_BITS must be defined in FreeRTOSConfig.h.
 See the Configuration section of the FreeRTOS API documentation for
 details.
```

Related issue - https://github.com/FreeRTOS/FreeRTOS-Kernel/issues/628

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Feature/fixing clang gnu compiler warnings (#620)

* Adding in ability to support a library for freertos_config and a custom freertos_kernel_port (#558)

* Using single name definition for libraries everywhere. (#558)

* Supporting backwards compatibility with FREERTOS_CONFIG_FILE_DIRECTORY (#571)

* Removing compiler warnings for GNU and Clang. (#571)

* Added in documentation on how to consume from a main project. Added default PORT selection for native POSIX and MINGW platforms.

* Only adding freertos_config if it exists. Removing auto generation of it from a FREERTOS_CONFIG_FILE_DIRECTORY.

* Fixing clang and gnu compiler warnings.

* Adding in project information and how to compile for GNU/clang

* Fixing compiler issue with unused variable - no need to declare variable.

* Adding in compile warnings for linux builds that kernel is okay with using.

* Fixing more extra-semi-stmt clang warnings.

* Moving definition of hooks into header files if features are enabled.

* Fixing formatting with uncrustify.

* Fixing merge conflicts with main merge.

* Fixing compiler errors due to merge issues and formatting.

* Fixing Line feeds.

* Adding 'portNORETURN' into portmacros.h. Other Updates based on PR request

* Further clean-up of clang and clang-tidy issues.

* Removing compiler specific pragmas from common c files.

* Fixing missing lexicon entry and uncrustify formatting changes.

* Resolving merge issue multiple defnitions of proto for prvIdleTask

* Fixing formatting issues that are not covered by uncrustify. Use clang-tidy instead if you want this level of control.

* More uncrustify formatting issues.

* Fixing extra bracket in #if statement.

---------

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

* POSIX port fixes (#626)

* Fix types in POSIX port

Use TaskFunction_t and StackType_t as other ports do.

* Fix portTICK_RATE_MICROSECONDS in POSIX port

---------

Co-authored-by: Jacques GUILLOU <jacques.guillou.job@gmail.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

* Cortex-M35P: Add Cortex-M35P port (#631)

* Cortex-M35P: Add Cortex-M35P port

The Cortex-M35P support added to kernel. The port hasn't been
validated yet with TF-M. Hence TF-M support is not included in this
port.

Signed-off-by: Devaraj Ranganna <devaraj.ranganna@arm.com>

* Add portNORETURN to the newly added portmacro.h

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Devaraj Ranganna <devaraj.ranganna@arm.com>
Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: kar-rahul-aws <118818625+kar-rahul-aws@users.noreply.github.com>

* Introduced Github Status Badge for Unit Tests (#634)

* Introduced Github Status Badge for Unit Tests

* Github status badge to point to latest run

* Github status badge UT points to latest results

* Fixed URL for Github Status badge

---------

Co-authored-by: kar-rahul-aws <118818625+kar-rahul-aws@users.noreply.github.com>

* Remove C99 requirement from CMake file (#633)

* Remove C99 requirement from CMake file

The kernel source is C89 compliant and does not need C99.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Explicitly set C89 requirement for kernel

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Add Thread Local Storage (TLS) support using Picolibc functions (#343)

* Pass top of stack to configINIT_TLS_BLOCK

Picolibc wants to allocate the per-task TLS block within the stack
segment, so it will need to modify the top of stack value. Pass the
pxTopOfStack variable to make this explicit.

Signed-off-by: Keith Packard <keithpac@amazon.com>

* Move newlib-specific definitions to separate file

This reduces the clutter in FreeRTOS.h caused by having newlib-specific
macros present there.

Signed-off-by: Keith Packard <keithpac@amazon.com>

* Make TLS code depend only on configUSE_C_RUNTIME_TLS_SUPPORT

Remove reference to configUSE_NEWLIB_REENTRANT as that only works
when using newlib. configUSE_C_RUNTIME_TLS_SUPPORT is always
set when configUSE_NEWLIB_REENTRANT is set, so using both was
redundant in that case.

Signed-off-by: Keith Packard <keithpac@amazon.com>

* portable-ARC: Adapt ARC support to use generalized TLS support

With generalized thread local storage (TLS) support present in the
core, the two ARC ports need to have the changes to the TCB mirrored
to them.

Signed-off-by: Keith Packard <keithpac@amazon.com>

* Add Thread Local Storage (TLS) support using Picolibc functions

This patch provides definitions of the general TLS support macros in
terms of the Picolibc TLS support functions.

Picolibc is normally configured to use TLS internally for all
variables that are intended to be task-local, so these changes are
necessary for picolibc to work correctly with FreeRTOS.

The picolibc helper functions rely on elements within the linker
script to arrange the TLS data in memory and define some symbols.
Applications wanting to use this mechanism will need changes in their
linker script when migrating to picolibc.

Signed-off-by: Keith Packard <keithpac@amazon.com>

---------

Signed-off-by: Keith Packard <keithpac@amazon.com>
Co-authored-by: Keith Packard <keithpac@amazon.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

* Interrupt priority assert improvements for CM3/4/7 (#602)

* Interrupt priority assert improvements for CM3/4/7

In the ARM_CM3, ARM_CM4, and ARM_CM7 ports, change the assertion that
`configMAX_SYSCALL_INTERRUPT_PRIORITY` is nonzero to account for the
number of priority bits implemented by the hardware.

Change these ports to also use the lowest priority for PendSV and
SysTick, ignoring `configKERNEL_INTERRUPT_PRIORITY`.

* Remove not needed configKERNEL_INTERRUPT_PRIORITY define

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>

* Introduced code coverage status badge (#635)

* Introduced code coverage status badge

* Trying to fix the URL checker issue

* Fix URL check

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

* added portPOINTER_SIZE_TYPE and SIZE_MAX definition to PIC24/dsPIC port (#636)

* added portPOINTER_SIZE_TYPE definition to PIC24/dsPIC port

* Added SIZE_MAX definition to PIC24/dsPIC33

* Fix TLS and stack alignment when using picolibc (#637)

Both the TLS block and stack must be correctly aligned when using
picolibc. The architecture stack alignment is represented by the
portBYTE_ALIGNMENT_MASK and the TLS block alignment is provided by the
Picolibc _tls_align() inline function for Picolibc version 1.8 and
above. For older versions of Picolibc, we'll assume that the TLS block
requires the same alignment as the stack.

For downward growing stacks, this requires aligning the start of the
TLS block to the maximum of the stack alignment and the TLS
alignment. With this, both the TLS block and stack will now be
correctly aligned.

For upward growing stacks, the two areas must be aligned
independently; the TLS block is aligned from the start of the stack,
then the tls space is allocated, and then the stack is aligned above
that.

It's probably useful to know here that the linker ensures that
variables within the TLS block are assigned offsets that match their
alignment requirements. If the TLS block itself is correctly aligned,
then everything within will also be.

I have only tested the downward growing stack branch of this patch.

Signed-off-by: Keith Packard <keithpac@amazon.com>
Co-authored-by: Keith Packard <keithpac@amazon.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

* Enable building the GCC Cortex-R5 port without an FPU (#586)

* Ensure configUSE_TASK_FPU_SUPPORT option is set correctly

If one does enable the FPU of the Cortex-R5 processor, then the GCC
compiler will define the macro __ARM_FP. This can be used to ensure,
that the configUSE_TASK_FPU_SUPPORT is set accordingly.

* Enable the implementation of vPortTaskUsesFPU only if configUSE_TASK_FPU_SUPPORT is set to 1

* Remove error case in pxPortInitialiseStack

The case of configUSE_TASK_FPU_SUPPORT is 0 is now handled

* Enable access to FPU registers only if FPU is enabled

* Make minor formating changes

* Format ARM Cortex-R5 port

* Address review comments from @ChristosZosi

* Minor code review suggestions

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Christos Zosimidis <christos.zosimidis@gmail.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>

* Fix freertos_kernel cmake property, Posix Port (#640)

* Fix freertos_kernel cmake property, Posix Port

* Moves the `set_property()` call below the target definition in top level CMakeLists file
* Corrects billion value from `ULL` suffix (not C90 compliant) to `UL` suffix with cast to uint64_t

* Add blank line to CMakeLists.txt

* Add missing FreeRTOS+ defines

* Run kernel demos and unit tests for PR changes (#645)

* Run kernel demos and unit tests for PR changes

Kernel demos check builds multiple demos from FreeRTOS/FreeRTOS and
unit tests check runs unit tests in FreeRTOS/FreeRTOS. Both of these
checks currently use main branch of FreeRTOS-Kernel. This commits
updates these checks to use the changes in the PR.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Do not specify PR SHA explicitly as that is default

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Remove explicit PR SHA from kernel checks

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Add functions to get the buffers of statically created objects (#641)

Added various ...GetStaticBuffer() functions to get the buffers of statically
created objects.
---------
Co-authored-by: Paul Bartell <pbartell@amazon.com>
Co-authored-by: Nikhil Kamath <110539926+amazonKamath@users.noreply.github.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>

* Cortex-M Assert when NVIC implements 8 PRIO bits (#639)

* Cortex-M Assert when NVIC implements 8 PRIO bits

* Fix CM3 ports

* Fix ARM_CM3_MPU

* Fix ARM CM3

* Fix ARM_CM4_MPU

* Fix ARM_CM4

* Fix GCC ARM_CM7

* Fix IAR ARM ports

* Uncrustify changes

* Fix MikroC_ARM_CM4F port

* Fix MikroC_ARM_CM4F port-(2)

* Fix RVDS ARM ports

* Revert changes for Tasking/ARM_CM4F port

* Revert changes for Tasking/ARM_CM4F port-(2)

* Update port.c

Fix GCC/ARM_CM4F port

* Update port.c

* update GCC\ARM_CM4F port

* update port.c

* Assert to check configMAX_SYSCALL_INTERRUPT_PRIORITY is set to higher priority

* Fix merge error: remove duplicate code

* Fix typos

---------

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Co-authored-by: Ubuntu <ubuntu@ip-172-31-17-174.ec2.internal>

* Remove C90 requirement from CMakeLists (#649)

This is needed as it is breaking projects - https://forums.freertos.org/t/freertos-gcc-cmake/16984

We will re-evaluate and accordingly add this later.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Only add alignment padding when needed (#650)

Heap 4 and Heap 5 add some padding to ensure that the allocated blocks
are always aligned to portBYTE_ALIGNMENT bytes. The code until now was
adding padding always even if the resulting block was already aligned.
This commits updates the code to only add padding if the resulting block
is not aligned.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* add a missing comma (#651)

* fix conversion warning (#658)

FreeRTOS-Kernel/portable/GCC/ARM_CM4F/port.c:399:41: error: conversion from 'uint32_t' {aka 'long unsigned int'} to 'uint8_t' {aka 'unsigned char'} may change value [-Werror=conversion]

Signed-off-by: Vo Trung Chi <chi.votrung@vn.bosch.com>

* ARMv7M: Adjust implemented priority bit assertions (#665)

Adjust assertions related to the CMSIS __NVIC_PRIO_BITS and FreeRTOS
configPRIO_BITS configuration macros such that these macros specify the
minimum number of implemented priority bits supported by a config
build rather than the exact number of implemented priority bits.

Related to Qemu issue #1122

* Format portmacro.h in arm CM0 ports

* portable/ARM_CM0: Add xPortIsInsideInterrupt

Add missing xPortIsInsideInterrupt function to Cortex-M0 port.

* tree-wide: Unify formatting of __cplusplus ifdefs

* Paranthesize expression-like macro (#668)

* Updated tasks.c checks for scheduler suspension (#670)

This commit updates the checks for the variable uxSchedulerSuspended in
tasks.c module to use a uniform format.

Signed-off-by: Sudeep Mohanty <sudp.mohanty@gmail.com>

* Fix cast alignment warning (#669)

* Fix cast alignment warning

Without this change, the code produces the following warning when
compiled with `-Wcast-align` flag:

```
cast increases required alignment of target type
```

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Align StackSize and StackAddress for macOS (#674)

* Armv8-M (except Cortex-M23) interrupt priority checking (#673)

* Armv8-M: Formatting changes

Signed-off-by: Devaraj Ranganna <devaraj.ranganna@arm.com>

* Armv8-M: Add support for interrupt priority check

FreeRTOS provides `FromISR` system calls which can be called directly
from interrupt service routines. It is crucial that the priority of
these ISRs is set to same or lower value (numerically higher) than that
of `configMAX_SYSCALL_INTERRUPT_PRIORITY`. For more information refer
to https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html.

Add a check to trigger an assert when an ISR with priority higher
(numerically lower) than `configMAX_SYSCALL_INTERRUPT_PRIORITY` calls
`FromISR` system calls if `configASSERT` macro is defined.

In addition, add a config option
`configQEMU_DISABLE_INTERRUPT_PRIO_BITS_CHECK` to disable interrupt
priority check while running on QEMU. Based on the discussion
https://gitlab.com/qemu-project/qemu/-/issues/1122, The interrupt
priority bits in QEMU do not match the real hardware. Therefore the
assert that checks the number of implemented bits and __NVIC_PRIO_BITS
will always fail. The config option
 `configQEMU_DISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the
`FreeRTOSConfig.h` for QEMU targets.

Signed-off-by: Devaraj Ranganna <devaraj.ranganna@arm.com>

* Use SHPR2 for calculating interrupt priority bits

This removes the dependency on the secure software to mark the interrupt
as non-secure.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Devaraj Ranganna <devaraj.ranganna@arm.com>
Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

* Use the extended movx instruction instead of mov (#676)

The following is from the MSP430X instruction set -

```
MOVX.W Move source word to destination word.

The source operand is copied to the destination. The source operand is
not affected. Both operands may be located in the full address space.
```

The movx instruction allows both the operands to be located in the full
address space and therefore, works with large data model as well.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Fix eTaskGetState for pending ready tasks (#679)

This commit fixes eTaskGetState so that eReady is returned for pending ready
tasks.

Co-authored-by: Darian Leung <darian@espressif.com>

* Generates SBOM after source files are updated with release tag (#680)

* update source file with release version info before SBOM generation

* delete tag branch during cleanup

* Add back croutines by reverting PR#590 (#685)

* Add croutines to the code base

* Add croutine changes to cmake, lexicon and readme

* Add croutine file to portable cmake file

* Add back more references from PR 591

* Remove __NVIC_PRIO_BITS and configPRIO_BITS check in port (#683)

* Remove __NVIC_PRIO_BITS and configPRIO_BITS check in CM3, CM4 and ARMv8.
* Add hardware not implemented bits check. These bits should be zero.

---------

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

* Use UBaseType_t as interrupt mask (#689)

* Use UBaseType_t as interrupt mask
* Update GCC posix port to use UBaseType_t as interrupt mask

* Fix clang warning in croutine and stream buffer (#686)

* Fix document warning in croutine
* Fix cast-qual warning in stream buffer

* Use portTASK_FUNCTION_PROTO to replace portNORETURN (#688)

* Use portTASK_FUNCTION_PROTO to replace portNORETURN

* Fix typo in check comment of configMAX_SYSCALL_INTERRUPT_PRIORITY (#690)

* Add constant type for portMAX_DELAY in port (#691)

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

* Update static stream buffer size check (#693)

* Use volatile size instead of sizeof directly to prevent always
  true/false warning

* Fix typos in comments for the AT91SAM7S port (#695)

Co-authored-by: RichardBarry <3073890+RichardBarry@users.noreply.github.com>

* Fix #697: Missing portPOINTER_SIZE_TYPE definition for ATmega port (#698)

* Remove empty expression statement compiler warning (#692)

* Add do while( 0 ) loop for empty expression statement compiler warning

* Update uxTaskGetSystemState for tasks in pending ready list (#702)

* Update uxTaskGetSystemState to sync with eTaskGetState
* Update in vTaskGetInfo for tasks in pending ready list should be in
  ready state.

* Fix circular dependency in CMake project (#700)

* Fix circular dependency in cmake project

Fix for https://github.com/FreeRTOS/FreeRTOS-Kernel/issues/687
In order for custom ports to also break the cycle, they must link
against freertos_kernel_include instead of freertos_kernel.

* Simplify include path

* Memory Protection Unit (MPU) Enhancements (#705)

Memory Protection Unit (MPU) Enhancements

This commit introduces a new MPU wrapper that places additional
restrictions on unprivileged tasks. The following is the list of changes
introduced with the new MPU wrapper:

1. Opaque and indirectly verifiable integers for kernel object handles:
   All the kernel object handles (for example, queue handles) are now
   opaque integers. Previously object handles were raw pointers.

2. Saving the task context in Task Control Block (TCB): When a task is
   swapped out by the scheduler, the task's context is now saved in its
   TCB. Previously the task's context was saved on its stack.

3. Execute system calls on a separate privileged only stack: FreeRTOS
   system calls, which execute with elevated privilege, now use a
   separate privileged only stack. Previously system calls used the
   calling task's stack. The application writer can control the size of
   the system call stack using new configSYSTEM_CALL_STACK_SIZE config
   macro.

4. Memory bounds checks: FreeRTOS system calls which accept a pointer
   and de-reference it, now verify that the calling task has required
   permissions to access the memory location referenced by the pointer.

5. System call restrictions: The following system calls are no longer
   available to unprivileged tasks:
    - vQueueDelete
    - xQueueCreateMutex
    - xQueueCreateMutexStatic
    - xQueueCreateCountingSemaphore
    - xQueueCreateCountingSemaphoreStatic
    - xQueueGenericCreate
    - xQueueGenericCreateStatic
    - xQueueCreateSet
    - xQueueRemoveFromSet
    - xQueueGenericReset
    - xTaskCreate
    - xTaskCreateStatic
    - vTaskDelete
    - vTaskPrioritySet
    - vTaskSuspendAll
    - xTaskResumeAll
    - xTaskGetHandle
    - xTaskCallApplicationTaskHook
    - vTaskList
    - vTaskGetRunTimeStats
    - xTaskCatchUpTicks
    - xEventGroupCreate
    - xEventGroupCreateStatic
    - vEventGroupDelete
    - xStreamBufferGenericCreate
    - xStreamBufferGenericCreateStatic
    - vStreamBufferDelete
    - xStreamBufferReset
   Also, an unprivileged task can no longer use vTaskSuspend to suspend
   any task other than itself.

We thank the following people for their inputs in these enhancements:
- David Reiss of Meta Platforms, Inc.
- Lan Luo, Xinhui Shao, Yumeng Wei, Zixia Liu, Huaiyu Yan and Zhen Ling
  of School of Computer Science and Engineering, Southeast University,
  China.
- Xinwen Fu of Department of Computer Science, University of
  Massachusetts Lowell, USA.
- Yuequi Chen, Zicheng Wang, Minghao Lin of University of Colorado
  Boulder, USA.

* Update History for Version 10.6.0 (#706)

Signed-off-by: kar-rahul-aws <karahulx@amazon.com>

* Fixed compile options polluting project (#694)

* Fixed compile options polluting project

Moved add_library higher

* Apply suggestions from code review

Co-authored-by: Paul Bartell <paul.bartell@gmail.com>

* fixed cmakelists keeping in mind the suggestions

---------

Co-authored-by: Paul Bartell <paul.bartell@gmail.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Co-authored-by: Aniruddha Kanhere <60444055+AniruddhaKanhere@users.noreply.github.com>

* Fix the comments in the CM3 and CM4 MPU Ports about the MPU Region numbers being loaded (#707)

Co-authored-by: Soren Ptak <skptak@amazon.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

* Update xSemaphoreGetStaticBuffer prototype in comment (#704)

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

* Correct the misspelled name (#708)

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Signed-off-by: Cervenka Dusan <cervenka@acrios.com>
Signed-off-by: Devaraj Ranganna <devaraj.ranganna@arm.com>
Signed-off-by: Keith Packard <keithpac@amazon.com>
Signed-off-by: Vo Trung Chi <chi.votrung@vn.bosch.com>
Signed-off-by: Sudeep Mohanty <sudp.mohanty@gmail.com>
Signed-off-by: kar-rahul-aws <karahulx@amazon.com>
Co-authored-by: Archit Gupta <71798289+archigup@users.noreply.github.com>
Co-authored-by: tcpluess <tpluess@ieee.org>
Co-authored-by: pluess <pluess@faulhorn.mw.iap.unibe.ch>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Co-authored-by: Chris Copeland <chris@chrisnc.net>
Co-authored-by: David J. Fiddes <35607151+davefiddes@users.noreply.github.com>
Co-authored-by: Dusan Cervenka <cervenka@acrios.com>
Co-authored-by: bbain <16752579+bbain@users.noreply.github.com>
Co-authored-by: Ju1He1 <93189163+Ju1He1@users.noreply.github.com>
Co-authored-by: Aniruddha Kanhere <60444055+AniruddhaKanhere@users.noreply.github.com>
Co-authored-by: phelter <paulheltera@gmail.com>
Co-authored-by: jacky309 <jacques.guillou@gmail.com>
Co-authored-by: Jacques GUILLOU <jacques.guillou.job@gmail.com>
Co-authored-by: Devaraj Ranganna <devaraj.ranganna@arm.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: kar-rahul-aws <118818625+kar-rahul-aws@users.noreply.github.com>
Co-authored-by: Nikhil Kamath <110539926+amazonKamath@users.noreply.github.com>
Co-authored-by: Keith Packard <keithp@keithp.com>
Co-authored-by: Keith Packard <keithpac@amazon.com>
Co-authored-by: Joseph Julicher <jjulicher@mac.com>
Co-authored-by: Paul Bartell <pbartell@amazon.com>
Co-authored-by: Christos Zosimidis <christos.zosimidis@gmail.com>
Co-authored-by: Kody Stribrny <89810515+kstribrnAmzn@users.noreply.github.com>
Co-authored-by: Holden <holden-zenithaerotech.com>
Co-authored-by: Darian <32921628+Dazza0@users.noreply.github.com>
Co-authored-by: Ubuntu <ubuntu@ip-172-31-17-174.ec2.internal>
Co-authored-by: Nicolas <nicolas.brunner@heig-vd.ch>
Co-authored-by: Vo Trung Chi <chi.votrung@vn.bosch.com>
Co-authored-by: Sudeep Mohanty <91244425+sudeep-mohanty@users.noreply.github.com>
Co-authored-by: Monika Singh <108652024+moninom1@users.noreply.github.com>
Co-authored-by: Darian Leung <darian@espressif.com>
Co-authored-by: Tony Josi <tonyjosi@amazon.com>
Co-authored-by: Evgeny Ermakov <22344340+unspecd@users.noreply.github.com>
Co-authored-by: RichardBarry <3073890+RichardBarry@users.noreply.github.com>
Co-authored-by: Joris Putcuyps <joris.putcuyps@gmail.com>
Co-authored-by: Patrick Cook <114708437+cookpate@users.noreply.github.com>
Co-authored-by: Mr. Jake <norbertzpilicy@gmail.com>
Co-authored-by: Paul Bartell <paul.bartell@gmail.com>
Co-authored-by: Soren Ptak <Skptak@outlook.com>
Co-authored-by: Soren Ptak <skptak@amazon.com>

* Merge main to SMP branch 0721 (#90)

* Fix array-bounds compiler warning on gcc11+ in list.h (#580)

listGET_OWNER_OF_NEXT_ENTRY computes `( pxConstList )->pxIndex->pxNext` after
verifying that `( pxConstList )->pxIndex` points to `xListEnd`, which due to
being a MiniListItem_t, can be shorter than a ListItem_t. Thus,
`( pxConstList )->pxIndex` is a `ListItem_t *` that extends past the end of the
`List_t` whose `xListEnd` it points to. This is fixed by accessing `pxNext`
through a `MiniListItem_t` instead.

* move the prototype for vApplicationIdleHook to task.h. (#600)

Co-authored-by: pluess <pluess@faulhorn.mw.iap.unibe.ch>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

* Update equal priority task preemption (#603)

* vTaskResume and vTaskPrioritySet don't preempt equal priority task

* Update vTaskResumeAll not to preempt task with equal priority

* Fix in xTaskResumeFromISR

* Update FreeRTOS/FreeRTOS build checks (#613)

This is needed to be compatible with the refactoring done in this
PR - https://github.com/FreeRTOS/FreeRTOS/pull/889

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Add ulTaskGetRunTimeCounter and ulTaskGetRunTimePercent (#611)

Allow ulTaskGetIdleRunTimeCounter and ulTaskGetIdleRunTimePercent to be
used whenever configGENERATE_RUN_TIME_STATS is enabled, as this is the
only requirement for these functions to work.

* Fix some CMake documentation typos (#616)

The quick start instructions for CMake mention the "master"
git branch which has been replaced by "main" in the current
repo.

The main CMakeLists.txt documents how to integrate a
custom port. Fix a typo in the suggested CMake code.

* Added support of 64bit events. (#597)

* Added support of 64bit even

Signed-off-by: Cervenka Dusan <cervenka@acrios.com>

* Added missing brackets

Signed-off-by: Cervenka Dusan <cervenka@acrios.com>

* Made proper name for tick macro.

Signed-off-by: Cervenka Dusan <cervenka@acrios.com>

* Improved macro evaluation

Signed-off-by: Cervenka Dusan <cervenka@acrios.com>

* Fixed missed port files  + documentation

Signed-off-by: Cervenka Dusan <cervenka@acrios.com>

* Changes made on PR

Signed-off-by: Cervenka Dusan <cervenka@acrios.com>

* Fix macro definition.

Signed-off-by: Cervenka Dusan <cervenka@acrios.com>

* Formatted code with uncrustify

Signed-off-by: Cervenka Dusan <cervenka@acrios.com>

---------

Signed-off-by: Cervenka Dusan <cervenka@acrios.com>

* Introduce portMEMORY_BARRIER for Microblaze port. (#621)

The introduction of `portMEMORY_BARRIER` will ensure
the places in the kernel use a barrier will work.
For example, `xTaskResumeAll` has a memory barrier
to ensure its correctness when compiled with optimization
enabled. Without the barrier `xTaskResumeAll` can fail
(e.g. start reading and writing to address 0 and/or
infinite looping) when `xPendingReadyList` contains more
than one task to restore.

In `xTaskResumeAll` the compiler chooses to cache the
`pxTCB` the first time through the loop for use
in every subsequent loop. This is incorrect as the
removal of `pxTCB->xEventListItem` will actually
change the value of `pxTCB` if it was read again
at the top of the loop. The barrier forces the compiler
to read `pxTCB` again at the top of the loop.

The compiler is operating correctly. The removal
`pxTCB->xEventListItem` executes on a `List_t *`
and `ListItem_t *`.  This means that the compiler
can assume that any `MiniListItem_t` values are
unchanged by the loop (i.e. "strict-aliasing").
This allows the compiler to cache `pxTCB` as it
is obtained via a `MiniListItem_t`. This is incorrect
in this case because it is possible for a `ListItem_t *`
to actually alias a `MiniListItem_t`. This is technically
a "violation of aliasing rules" so we use the the barrier
to disable the strict-aliasing optimization in this loop.

* Do not call exit() on MSVC Port when calling vPortEndScheduler (#624)

* make port exitable

* correctly set xPortRunning to False

* add suggestions from Review

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

* add suggestions from Review

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

---------

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

* Update PR template to include checkbox for Unit Test related changes (#627)

* Fix build failure introduced in PR #597 (#629)

The PR #597 introduced a new config option configTICK_TYPE_WIDTH_IN_BITS
which can be defined to one of the following:
* TICK_TYPE_WIDTH_16_BITS - Tick type is 16 bit wide.
* TICK_TYPE_WIDTH_32_BITS - Tick type is 32 bit wide.
* TICK_TYPE_WIDTH_64_BITS - Tick type is 64 bit wide.

Earlier we supported 16 and 32 bit width for tick type which was
controlled using the config option configUSE_16_BIT_TICKS. The PR
tried to maintain backward compatibility by honoring
configUSE_16_BIT_TICKS. The backward compatibility did not work as
expected though, as the macro configTICK_TYPE_WIDTH_IN_BITS was used
before it was defined. This PR addresses it by ensuring that the macro
configTICK_TYPE_WIDTH_IN_BITS is defined before it is used.

Testing
1. configUSE_16_BIT_TICKS is defined to 0.

Source (function xTaskIncrementTick in tasks.c):
```
const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
```

Assembly:
```
109e:       4b50            ldr     r3, [pc, #320]  ; (11e0 <xTaskIncrementTick+0x150>)
10a0:       f8d3 4134       ldr.w   r4, [r3, #308]  ; 0x134
10a4:       3401            adds    r4, #1
10a6:       f8c3 4134       str.w   r4, [r3, #308]  ; 0x134
```

It is clear from assembly that the tick type is 32 bit.

2. configUSE_16_BIT_TICKS is defined to 1.

Source (function xTaskIncrementTick in tasks.c):
```
const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
```

Assembly:
```
10e2:       4b53            ldr     r3, [pc, #332]  ; (1230 <xTaskIncrementTick+0x15c>)
10e4:       f8b3 4134       ldrh.w  r4, [r3, #308]  ; 0x134
10e8:       b2a4            uxth    r4, r4
10ea:       3401            adds    r4, #1
10ec:       b2a4            uxth    r4, r4
10ee:       f8a3 4134       strh.w  r4, [r3, #308]  ; 0x134
```

It is clear from assembly that the tick type is 16 bit.

3. configTICK_TYPE_WIDTH_IN_BITS is defined to TICK_TYPE_WIDTH_16_BITS.

Source (function xTaskIncrementTick in tasks.c):
```
const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
```

Assembly:
```
10e2:       4b53            ldr     r3, [pc, #332]  ; (1230 <xTaskIncrementTick+0x15c>)
10e4:       f8b3 4134       ldrh.w  r4, [r3, #308]  ; 0x134
10e8:       b2a4            uxth    r4, r4
10ea:       3401            adds    r4, #1
10ec:       b2a4            uxth    r4, r4
10ee:       f8a3 4134       strh.w  r4, [r3, #308]  ; 0x134
```

It is clear from assembly that the tick type is 16 bit.

4. configTICK_TYPE_WIDTH_IN_BITS is defined to TICK_TYPE_WIDTH_32_BITS.

Source (function xTaskIncrementTick in tasks.c):
```
const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
```

Assembly:
```
109e:       4b50            ldr     r3, [pc, #320]  ; (11e0 <xTaskIncrementTick+0x150>)
10a0:       f8d3 4134       ldr.w   r4, [r3, #308]  ; 0x134
10a4:       3401            adds    r4, #1
10a6:       f8c3 4134       str.w   r4, [r3, #308]  ; 0x134
```

It is clear from assembly that the tick type is 32 bit.

5. configTICK_TYPE_WIDTH_IN_BITS is defined to TICK_TYPE_WIDTH_64_BITS.

```
 #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
```

The testing was done for GCC/ARM_CM3 port which does not support 64 bit
tick type.

6. Neither configUSE_16_BIT_TICKS nor configTICK_TYPE_WIDTH_IN_BITS
defined.

```
 #error Missing definition:  One of configUSE_16_BIT_TICKS and
 configTICK_TYPE_WIDTH_IN_BITS must be defined in FreeRTOSConfig.h.
 See the Configuration section of the FreeRTOS API documentation for
 details.
```

7. Both configUSE_16_BIT_TICKS and configTICK_TYPE_WIDTH_IN_BITS defined.

```
 #error Only one of configUSE_16_BIT_TICKS and
 configTICK_TYPE_WIDTH_IN_BITS must be defined in FreeRTOSConfig.h.
 See the Configuration section of the FreeRTOS API documentation for
 details.
```

Related issue - https://github.com/FreeRTOS/FreeRTOS-Kernel/issues/628

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Feature/fixing clang gnu compiler warnings (#620)

* Adding in ability to support a library for freertos_config and a custom freertos_kernel_port (#558)

* Using single name definition for libraries everywhere. (#558)

* Supporting backwards compatibility with FREERTOS_CONFIG_FILE_DIRECTORY (#571)

* Removing compiler warnings for GNU and Clang. (#571)

* Added in documentation on how to consume from a main project. Added default PORT selection for native POSIX and MINGW platforms.

* Only adding freertos_config if it exists. Removing auto generation of it from a FREERTOS_CONFIG_FILE_DIRECTORY.

* Fixing clang and gnu compiler warnings.

* Adding in project information and how to compile for GNU/clang

* Fixing compiler issue with unused variable - no need to declare variable.

* Adding in compile warnings for linux builds that kernel is okay with using.

* Fixing more extra-semi-stmt clang warnings.

* Moving definition of hooks into header files if features are enabled.

* Fixing formatting with uncrustify.

* Fixing merge conflicts with main merge.

* Fixing compiler errors due to merge issues and formatting.

* Fixing Line feeds.

* Adding 'portNORETURN' into portmacros.h. Other Updates based on PR request

* Further clean-up of clang and clang-tidy issues.

* Removing compiler specific pragmas from common c files.

* Fixing missing lexicon entry and uncrustify formatting changes.

* Resolving merge issue multiple defnitions of proto for prvIdleTask

* Fixing formatting issues that are not covered by uncrustify. Use clang-tidy instead if you want this level of control.

* More uncrustify formatting issues.

* Fixing extra bracket in #if statement.

---------

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

* POSIX port fixes (#626)

* Fix types in POSIX port

Use TaskFunction_t and StackType_t as other ports do.

* Fix portTICK_RATE_MICROSECONDS in POSIX port

---------

Co-authored-by: Jacques GUILLOU <jacques.guillou.job@gmail.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

* Cortex-M35P: Add Cortex-M35P port (#631)

* Cortex-M35P: Add Cortex-M35P port

The Cortex-M35P support added to kernel. The port hasn't been
validated yet with TF-M. Hence TF-M support is not included in this
port.

Signed-off-by: Devaraj Ranganna <devaraj.ranganna@arm.com>

* Add portNORETURN to the newly added portmacro.h

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Devaraj Ranganna <devaraj.ranganna@arm.com>
Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: kar-rahul-aws <118818625+kar-rahul-aws@users.noreply.github.com>

* Introduced Github Status Badge for Unit Tests (#634)

* Introduced Github Status Badge for Unit Tests

* Github status badge to point to latest run

* Github status badge UT points to latest results

* Fixed URL for Github Status badge

---------

Co-authored-by: kar-rahul-aws <118818625+kar-rahul-aws@users.noreply.github.com>

* Remove C99 requirement from CMake file (#633)

* Remove C99 requirement from CMake file

The kernel source is C89 compliant and does not need C99.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Explicitly set C89 requirement for kernel

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Add Thread Local Storage (TLS) support using Picolibc functions (#343)

* Pass top of stack to configINIT_TLS_BLOCK

Picolibc wants to allocate the per-task TLS block within the stack
segment, so it will need to modify the top of stack value. Pass the
pxTopOfStack variable to make this explicit.

Signed-off-by: Keith Packard <keithpac@amazon.com>

* Move newlib-specific definitions to separate file

This reduces the clutter in FreeRTOS.h caused by having newlib-specific
macros present there.

Signed-off-by: Keith Packard <keithpac@amazon.com>

* Make TLS code depend only on configUSE_C_RUNTIME_TLS_SUPPORT

Remove reference to configUSE_NEWLIB_REENTRANT as that only works
when using newlib. configUSE_C_RUNTIME_TLS_SUPPORT is always
set when configUSE_NEWLIB_REENTRANT is set, so using both was
redundant in that case.

Signed-off-by: Keith Packard <keithpac@amazon.com>

* portable-ARC: Adapt ARC support to use generalized TLS support

With generalized thread local storage (TLS) support present in the
core, the two ARC ports need to have the changes to the TCB mirrored
to them.

Signed-off-by: Keith Packard <keithpac@amazon.com>

* Add Thread Local Storage (TLS) support using Picolibc functions

This patch provides definitions of the general TLS support macros in
terms of the Picolibc TLS support functions.

Picolibc is normally configured to use TLS internally for all
variables that are intended to be task-local, so these changes are
necessary for picolibc to work correctly with FreeRTOS.

The picolibc helper functions rely on elements within the linker
script to arrange the TLS data in memory and define some symbols.
Applications wanting to use this mechanism will need changes in their
linker script when migrating to picolibc.

Signed-off-by: Keith Packard <keithpac@amazon.com>

---------

Signed-off-by: Keith Packard <keithpac@amazon.com>
Co-authored-by: Keith Packard <keithpac@amazon.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

* Interrupt priority assert improvements for CM3/4/7 (#602)

* Interrupt priority assert improvements for CM3/4/7

In the ARM_CM3, ARM_CM4, and ARM_CM7 ports, change the assertion that
`configMAX_SYSCALL_INTERRUPT_PRIORITY` is nonzero to account for the
number of priority bits implemented by the hardware.

Change these ports to also use the lowest priority for PendSV and
SysTick, ignoring `configKERNEL_INTERRUPT_PRIORITY`.

* Remove not needed configKERNEL_INTERRUPT_PRIORITY define

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>

* Introduced code coverage status badge (#635)

* Introduced code coverage status badge

* Trying to fix the URL checker issue

* Fix URL check

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

* added portPOINTER_SIZE_TYPE and SIZE_MAX definition to PIC24/dsPIC port (#636)

* added portPOINTER_SIZE_TYPE definition to PIC24/dsPIC port

* Added SIZE_MAX definition to PIC24/dsPIC33

* Fix TLS and stack alignment when using picolibc (#637)

Both the TLS block and stack must be correctly aligned when using
picolibc. The architecture stack alignment is represented by the
portBYTE_ALIGNMENT_MASK and the TLS block alignment is provided by the
Picolibc _tls_align() inline function for Picolibc version 1.8 and
above. For older versions of Picolibc, we'll assume that the TLS block
requires the same alignment as the stack.

For downward growing stacks, this requires aligning the start of the
TLS block to the maximum of the stack alignment and the TLS
alignment. With this, both the TLS block and stack will now be
correctly aligned.

For upward growing stacks, the two areas must be aligned
independently; the TLS block is aligned from the start of the stack,
then the tls space is allocated, and then the stack is aligned above
that.

It's probably useful to know here that the linker ensures that
variables within the TLS block are assigned offsets that match their
alignment requirements. If the TLS block itself is correctly aligned,
then everything within will also be.

I have only tested the downward growing stack branch of this patch.

Signed-off-by: Keith Packard <keithpac@amazon.com>
Co-authored-by: Keith Packard <keithpac@amazon.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

* Enable building the GCC Cortex-R5 port without an FPU (#586)

* Ensure configUSE_TASK_FPU_SUPPORT option is set correctly

If one does enable the FPU of the Cortex-R5 processor, then the GCC
compiler will define the macro __ARM_FP. This can be used to ensure,
that the configUSE_TASK_FPU_SUPPORT is set accordingly.

* Enable the implementation of vPortTaskUsesFPU only if configUSE_TASK_FPU_SUPPORT is set to 1

* Remove error case in pxPortInitialiseStack

The case of configUSE_TASK_FPU_SUPPORT is 0 is now handled

* Enable access to FPU registers only if FPU is enabled

* Make minor formating changes

* Format ARM Cortex-R5 port

* Address review comments from @ChristosZosi

* Minor code review suggestions

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Christos Zosimidis <christos.zosimidis@gmail.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>

* Fix freertos_kernel cmake property, Posix Port (#640)

* Fix freertos_kernel cmake property, Posix Port

* Moves the `set_property()` call below the target definition in top level CMakeLists file
* Corrects billion value from `ULL` suffix (not C90 compliant) to `UL` suffix with cast to uint64_t

* Add blank line to CMakeLists.txt

* Add missing FreeRTOS+ defines

* Run kernel demos and unit tests for PR changes (#645)

* Run kernel demos and unit tests for PR changes

Kernel demos check builds multiple demos from FreeRTOS/FreeRTOS and
unit tests check runs unit tests in FreeRTOS/FreeRTOS. Both of these
checks currently use main branch of FreeRTOS-Kernel. This commits
updates these checks to use the changes in the PR.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Do not specify PR SHA explicitly as that is default

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Remove explicit PR SHA from kernel checks

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Add functions to get the buffers of statically created objects (#641)

Added various ...GetStaticBuffer() functions to get the buffers of statically
created objects.
---------
Co-authored-by: Paul Bartell <pbartell@amazon.com>
Co-authored-by: Nikhil Kamath <110539926+amazonKamath@users.noreply.github.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>

* Cortex-M Assert when NVIC implements 8 PRIO bits (#639)

* Cortex-M Assert when NVIC implements 8 PRIO bits

* Fix CM3 ports

* Fix ARM_CM3_MPU

* Fix ARM CM3

* Fix ARM_CM4_MPU

* Fix ARM_CM4

* Fix GCC ARM_CM7

* Fix IAR ARM ports

* Uncrustify changes

* Fix MikroC_ARM_CM4F port

* Fix MikroC_ARM_CM4F port-(2)

* Fix RVDS ARM ports

* Revert changes for Tasking/ARM_CM4F port

* Revert changes for Tasking/ARM_CM4F port-(2)

* Update port.c

Fix GCC/ARM_CM4F port

* Update port.c

* update GCC\ARM_CM4F port

* update port.c

* Assert to check configMAX_SYSCALL_INTERRUPT_PRIORITY is set to higher priority

* Fix merge error: remove duplicate code

* Fix typos

---------

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Co-authored-by: Ubuntu <ubuntu@ip-172-31-17-174.ec2.internal>

* Remove C90 requirement from CMakeLists (#649)

This is needed as it is breaking projects - https://forums.freertos.org/t/freertos-gcc-cmake/16984

We will re-evaluate and accordingly add this later.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Only add alignment padding when needed (#650)

Heap 4 and Heap 5 add some padding to ensure that the allocated blocks
are always aligned to portBYTE_ALIGNMENT bytes. The code until now was
adding padding always even if the resulting block was already aligned.
This commits updates the code to only add padding if the resulting block
is not aligned.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* add a missing comma (#651)

* fix conversion warning (#658)

FreeRTOS-Kernel/portable/GCC/ARM_CM4F/port.c:399:41: error: conversion from 'uint32_t' {aka 'long unsigned int'} to 'uint8_t' {aka 'unsigned char'} may change value [-Werror=conversion]

Signed-off-by: Vo Trung Chi <chi.votrung@vn.bosch.com>

* ARMv7M: Adjust implemented priority bit assertions (#665)

Adjust assertions related to the CMSIS __NVIC_PRIO_BITS and FreeRTOS
configPRIO_BITS configuration macros such that these macros specify the
minimum number of implemented priority bits supported by a config
build rather than the exact number of implemented priority bits.

Related to Qemu issue #1122

* Format portmacro.h in arm CM0 ports

* portable/ARM_CM0: Add xPortIsInsideInterrupt

Add missing xPortIsInsideInterrupt function to Cortex-M0 port.

* tree-wide: Unify formatting of __cplusplus ifdefs

* Paranthesize expression-like macro (#668)

* Updated tasks.c checks for scheduler suspension (#670)

This commit updates the checks for the variable uxSchedulerSuspended in
tasks.c module to use a uniform format.

Signed-off-by: Sudeep Mohanty <sudp.mohanty@gmail.com>

* Fix cast alignment warning (#669)

* Fix cast alignment warning

Without this change, the code produces the following warning when
compiled with `-Wcast-align` flag:

```
cast increases required alignment of target type
```

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Align StackSize and StackAddress for macOS (#674)

* Armv8-M (except Cortex-M23) interrupt priority checking (#673)

* Armv8-M: Formatting changes

Signed-off-by: Devaraj Ranganna <devaraj.ranganna@arm.com>

* Armv8-M: Add support for interrupt priority check

FreeRTOS provides `FromISR` system calls which can be called directly
from interrupt service routines. It is crucial that the priority of
these ISRs is set to same or lower value (numerically higher) than that
of `configMAX_SYSCALL_INTERRUPT_PRIORITY`. For more information refer
to https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html.

Add a check to trigger an assert when an ISR with priority higher
(numerically lower) than `configMAX_SYSCALL_INTERRUPT_PRIORITY` calls
`FromISR` system calls if `configASSERT` macro is defined.

In addition, add a config option
`configQEMU_DISABLE_INTERRUPT_PRIO_BITS_CHECK` to disable interrupt
priority check while running on QEMU. Based on the discussion
https://gitlab.com/qemu-project/qemu/-/issues/1122, The interrupt
priority bits in QEMU do not match the real hardware. Therefore the
assert that checks the number of implemented bits and __NVIC_PRIO_BITS
will always fail. The config option
 `configQEMU_DISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the
`FreeRTOSConfig.h` for QEMU targets.

Signed-off-by: Devaraj Ranganna <devaraj.ranganna@arm.com>

* Use SHPR2 for calculating interrupt priority bits

This removes the dependency on the secure software to mark the interrupt
as non-secure.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Devaraj Ranganna <devaraj.ranganna@arm.com>
Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

* Use the extended movx instruction instead of mov (#676)

The following is from the MSP430X instruction set -

```
MOVX.W Move source word to destination word.

The source operand is copied to the destination. The source operand is
not affected. Both operands may be located in the full address space.
```

The movx instruction allows both the operands to be located in the full
address space and therefore, works with large data model as well.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Fix eTaskGetState for pending ready tasks (#679)

This commit fixes eTaskGetState so that eReady is returned for pending ready
tasks.

Co-authored-by: Darian Leung <darian@espressif.com>

* Generates SBOM after source files are updated with release tag (#680)

* update source file with release version info before SBOM generation

* delete tag branch during cleanup

* Add back croutines by reverting PR#590 (#685)

* Add croutines to the code base

* Add croutine changes to cmake, lexicon and readme

* Add croutine file to portable cmake file

* Add back more references from PR 591

* Remove __NVIC_PRIO_BITS and configPRIO_BITS check in port (#683)

* Remove __NVIC_PRIO_BITS and configPRIO_BITS check in CM3, CM4 and ARMv8.
* Add hardware not implemented bits check. These bits should be zero.

---------

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

* Use UBaseType_t as interrupt mask (#689)

* Use UBaseType_t as interrupt mask
* Update GCC posix port to use UBaseType_t as interrupt mask

* Fix clang warning in croutine and stream buffer (#686)

* Fix document warning in croutine
* Fix cast-qual warning in stream buffer

* Use portTASK_FUNCTION_PROTO to replace portNORETURN (#688)

* Use portTASK_FUNCTION_PROTO to replace portNORETURN

* Fix typo in check comment of configMAX_SYSCALL_INTERRUPT_PRIORITY (#690)

* Add constant type for portMAX_DELAY in port (#691)

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

* Update static stream buffer size check (#693)

* Use volatile size instead of sizeof directly to prevent always
  true/false warning

* Fix typos in comments for the AT91SAM7S port (#695)

Co-authored-by: RichardBarry <3073890+RichardBarry@users.noreply.github.com>

* Fix #697: Missing portPOINTER_SIZE_TYPE definition for ATmega port (#698)

* Remove empty expression statement compiler warning (#692)

* Add do while( 0 ) loop for empty expression statement compiler warning

* Update uxTaskGetSystemState for tasks in pending ready list (#702)

* Update uxTaskGetSystemState to sync with eTaskGetState
* Update in vTaskGetInfo for tasks in pending ready list should be in
  ready state.

* Fix circular dependency in CMake project (#700)

* Fix circular dependency in cmake project

Fix for https://github.com/FreeRTOS/FreeRTOS-Kernel/issues/687
In order for custom ports to also break the cycle, they must link
against freertos_kernel_include instead of freertos_kernel.

* Simplify include path

* Memory Protection Unit (MPU) Enhancements (#705)

Memory Protection Unit (MPU) Enhancements

This commit introduces a new MPU wrapper that places additional
restrictions on unprivileged tasks. The following is the list of changes
introduced with the new MPU wrapper:

1. Opaque and indirectly verifiable integers for kernel object handles:
   All the kernel object handles (for example, queue handles) are now
   opaque integers. Previously object handles were raw pointers.

2. Saving the task context in Task Control Block (TCB): When a task is
   swapped out by the scheduler, the task's context is now saved in its
   TCB. Previously the task's context was saved on its stack.

3. Execute system calls on a separate privileged only stack: FreeRTOS
   system calls, which execute with elevated privilege, now use a
   separate privileged only stack. Previously system calls used the
   calling task's stack. The application writer can control the size of
   the system call stack using new configSYSTEM_CALL_STACK_SIZE config
   macro.

4. Memory bounds checks: FreeRTOS system calls which accept a pointer
   and de-reference it, now verify that the calling task has required
   permissions to access the memory location referenced by the pointer.

5. System call restrictions: The following system calls are no longer
   available to unprivileged tasks:
    - vQueueDelete
    - xQueueCreateMutex
    - xQueueCreateMutexStatic
    - xQueueCreateCountingSemaphore
    - xQueueCreateCountingSemaphoreStatic
    - xQueueGenericCreate
    - xQueueGenericCreateStatic
    - xQueueCreateSet
    - xQueueRemoveFromSet
    - xQueueGenericReset
    - xTaskCreate
    - xTaskCreateStatic
    - vTaskDelete
    - vTaskPrioritySet
    - vTaskSuspendAll
    - xTaskResumeAll
    - xTaskGetHandle
    - xTaskCallApplicationTaskHook
    - vTaskList
    - vTaskGetRunTimeStats
    - xTaskCatchUpTicks
    - xEventGroupCreate
    - xEventGroupCreateStatic
    - vEventGroupDelete
    - xStreamBufferGenericCreate
    - xStreamBufferGenericCreateStatic
    - vStreamBufferDelete
    - xStreamBufferReset
   Also, an unprivileged task can no longer use vTaskSuspend to suspend
   any task other than itself.

We thank the following people for their inputs in these enhancements:
- David Reiss of Meta Platforms, Inc.
- Lan Luo, Xinhui Shao, Yumeng Wei, Zixia Liu, Huaiyu Yan and Zhen Ling
  of School of Computer Science and Engineering, Southeast University,
  China.
- Xinwen Fu of Department of Computer Science, University of
  Massachusetts Lowell, USA.
- Yuequi Chen, Zicheng Wang, Minghao Lin of University of Colorado
  Boulder, USA.

* Update History for Version 10.6.0 (#706)

Signed-off-by: kar-rahul-aws <karahulx@amazon.com>

* Fixed compile options polluting project (#694)

* Fixed compile options polluting project

Moved add_library higher

* Apply suggestions from code review

Co-authored-by: Paul Bartell <paul.bartell@gmail.com>

* fixed cmakelists keeping in mind the suggestions

---------

Co-authored-by: Paul Bartell <paul.bartell@gmail.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Co-authored-by: Aniruddha Kanhere <60444055+AniruddhaKanhere@users.noreply.github.com>

* Fix the comments in the CM3 and CM4 MPU Ports about the MPU Region numbers being loaded (#707)

Co-authored-by: Soren Ptak <skptak@amazon.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

* Update xSemaphoreGetStaticBuffer prototype in comment (#704)

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

* Correct the misspelled name (#708)

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Signed-off-by: Cervenka Dusan <cervenka@acrios.com>
Signed-off-by: Devaraj Ranganna <devaraj.ranganna@arm.com>
Signed-off-by: Keith Packard <keithpac@amazon.com>
Signed-off-by: Vo Trung Chi <chi.votrung@vn.bosch.com>
Signed-off-by: Sudeep Mohanty <sudp.mohanty@gmail.com>
Signed-off-by: kar-rahul-aws <karahulx@amazon.com>
Co-authored-by: Archit Gupta <71798289+archigup@users.noreply.github.com>
Co-authored-by: tcpluess <tpluess@ieee.org>
Co-authored-by: pluess <pluess@faulhorn.mw.iap.unibe.ch>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Co-authored-by: Chris Copeland <chris@chrisnc.net>
Co-authored-by: David J. Fiddes <35607151+davefiddes@users.noreply.github.com>
Co-authored-by: Dusan Cervenka <cervenka@acrios.com>
Co-authored-by: bbain <16752579+bbain@users.noreply.github.com>
Co-authored-by: Ju1He1 <93189163+Ju1He1@users.noreply.github.com>
Co-authored-by: Aniruddha Kanhere <60444055+AniruddhaKanhere@users.noreply.github.com>
Co-authored-by: phelter <paulheltera@gmail.com>
Co-authored-by: jacky309 <jacques.guillou@gmail.com>
Co-authored-by: Jacques GUILLOU <jacques.guillou.job@gmail.com>
Co-authored-by: Devaraj Ranganna <devaraj.ranganna@arm.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: kar-rahul-aws <118818625+kar-rahul-aws@users.noreply.github.com>
Co-authored-by: Nikhil Kamath <110539926+amazonKamath@users.noreply.github.com>
Co-authored-by: Keith Packard <keithp@keithp.com>
Co-authored-by: Keith Packard <keithpac@amazon.com>
Co-authored-by: Joseph Julicher <jjulicher@mac.com>
Co-authored-by: Paul Bartell <pbartell@amazon.com>
Co-authored-by: Christos Zosimidis <christos.zosimidis@gmail.com>
Co-authored-by: Kody Stribrny <89810515+kstribrnAmzn@users.noreply.github.com>
Co-authored-by: Holden <holden-zenithaerotech.com>
Co-authored-by: Darian <32921628+Dazza0@users.noreply.github.com>
Co-authored-by: Ubuntu <ubuntu@ip-172-31-17-174.ec2.internal>
Co-authored-by: Nicolas <nicolas.brunner@heig-vd.ch>
Co-authored-by: Vo Trung Chi <chi.votrung@vn.bosch.com>
Co-authored-by: Sudeep Mohanty <91244425+sudeep-mohanty@users.noreply.github.com>
Co-authored-by: Monika Singh <108652024+moninom1@users.noreply.github.com>
Co-authored-by: Darian Leung <darian@espressif.com>
Co-authored-by: Tony Josi <tonyjosi@amazon.com>
Co-authored-by: Evgeny Ermakov <22344340+unspecd@users.noreply.github.com>
Co-authored-by: RichardBarry <3073890+RichardBarry@users.noreply.github.com>
Co-authored-by: Joris Putcuyps <joris.putcuyps@gmail.com>
Co-authored-by: Patrick Cook <114708437+cookpate@users.noreply.github.com>
Co-authored-by: Mr. Jake <norbertzpilicy@gmail.com>
Co-authored-by: Paul Bartell <paul.bartell@gmail.com>
Co-authored-by: Soren Ptak <Skptak@outlook.com>
Co-authored-by: Soren Ptak <skptak@amazon.com>

* Move default configNUMBER_OF_CORES definition forward in FreeRTOSConfig.h (#88)

* Move default configNUMBER_OF_CORES definition forward in FreeRTOSConfig.h.

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Signed-off-by: Xinyu Zhang <xinyu.zhang@arm.com>
Signed-off-by: Gabor Toth <gabor.toth@arm.com>
Signed-off-by: Cristian Cristea <cristiancristea00@gmail.com>
Signed-off-by: Cervenka Dusan <cervenka@acrios.com>
Signed-off-by: Devaraj Ranganna <devaraj.ranganna@arm.com>
Signed-off-by: Keith Packard <keithpac@amazon.com>
Signed-off-by: Vo Trung Chi <chi.votrung@vn.bosch.com>
Signed-off-by: Sudeep Mohanty <sudp.mohanty@gmail.com>
Signed-off-by: kar-rahul-aws <karahulx@amazon.com>
Co-authored-by: alfred gedeon <28123637+alfred2g@users.noreply.github.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: AndreiCherniaev <dungeonlords789@yandex.ru>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Co-authored-by: Tanmoy Sen <33438891+tanmoysen@users.noreply.github.com>
Co-authored-by: Ravishankar Bhagavandas <bhagavar@amazon.com>
Co-authored-by: eddie9712 <qw1562435@gmail.com>
Co-authored-by: Graham Sanderson <graham.sanderson@raspberrypi.com>
Co-authored-by: graham sanderson <graham.sanderson@raspeberryi.com>
Co-authored-by: Xinyu Zhang <68640626+xinyu-tfm@users.noreply.github.com>
Co-authored-by: Paul Bartell <pbartell@amazon.com>
Co-authored-by: Joseph Julicher <jjulicher@mac.com>
Co-authored-by: NomiChirps <70026509+NomiChirps@users.noreply.github.com>
Co-authored-by: 0xjakob <18257824+0xjakob@users.noreply.github.com>
Co-authored-by: Jakob Hasse <0xjakob@users.noreply.github.com>
Co-authored-by: Xin Lin <47510956+xlin7799@users.noreply.github.com>
Co-authored-by: Patrick Oppenlander <patrick.oppenlander@gmail.com>
Co-authored-by: Gavin Lambert <uecasm@users.noreply.github.com>
Co-authored-by: Chris Copeland <chris@chrisnc.net>
Co-authored-by: RichardBarry <3073890+RichardBarry@users.noreply.github.com>
Co-authored-by: Paul Bartell <paul.bartell@gmail.com>
Co-authored-by: Aniruddha Kanhere <60444055+AniruddhaKanhere@users.noreply.github.com>
Co-authored-by: Archit Gupta <71798289+archigup@users.noreply.github.com>
Co-authored-by: Monika Singh <108652024+moninom1@users.noreply.github.com>
Co-authored-by: Octaviarius <gomanchuk.as@gmail.com>
Co-authored-by: Jakub Lužný <jakub@luzny.cz>
Co-authored-by: newbrain <17814222+newbrain@users.noreply.github.com>
Co-authored-by: Gabor Toth <gabor.toth@arm.com>
Co-authored-by: Ming Yue <mingyue86010@gmail.com>
Co-authored-by: David Chalco <david@chalco.io>
Co-authored-by: Cristian Cristea <cristiancristea00@gmail.com>
Co-authored-by: Jeff Tenney <jeff.tenney@gmail.com>
Co-authored-by: Cobus van Eeden <35851496+cobusve@users.noreply.github.com>
Co-authored-by: abhidixi11 <44424462+abhidixi11@users.noreply.github.com>
Co-authored-by: Laukik Hase <laukik.hase@espressif.com>
Co-authored-by: arshi016 <arshilife16@gmail.com>
Co-authored-by: Niklas Gürtler <Erlkoenig90@users.noreply.github.com>
Co-authored-by: Niklas Gürtler <niklas.guertler@tacterion.com>
Co-authored-by: Hardy Griech <ntbox@gmx.net>
Co-authored-by: Darian <32921628+Dazza0@users.noreply.github.com>
Co-authored-by: tcpluess <tpluess@ieee.org>
Co-authored-by: pluess <pluess@faulhorn.mw.iap.unibe.ch>
Co-authored-by: David J. Fiddes <35607151+davefiddes@users.noreply.github.com>
Co-authored-by: Dusan Cervenka <cervenka@acrios.com>
Co-authored-by: bbain <16752579+bbain@users.noreply.github.com>
Co-authored-by: Ju1He1 <93189163+Ju1He1@users.noreply.github.com>
Co-authored-by: phelter <paulheltera@gmail.com>
Co-authored-by: jacky309 <jacques.guillou@gmail.com>
Co-authored-by: Jacques GUILLOU <jacques.guillou.job@gmail.com>
Co-authored-by: Devaraj Ranganna <devaraj.ranganna@arm.com>
Co-authored-by: kar-rahul-aws <118818625+kar-rahul-aws@users.noreply.github.com>
Co-authored-by: Nikhil Kamath <110539926+amazonKamath@users.noreply.github.com>
Co-authored-by: Keith Packard <keithp@keithp.com>
Co-authored-by: Keith Packard <keithpac@amazon.com>
Co-authored-by: Christos Zosimidis <christos.zosimidis@gmail.com>
Co-authored-by: Kody Stribrny <89810515+kstribrnAmzn@users.noreply.github.com>
Co-authored-by: Ubuntu <ubuntu@ip-172-31-17-174.ec2.internal>
Co-authored-by: Nicolas <nicolas.brunner@heig-vd.ch>
Co-authored-by: Vo Trung Chi <chi.votrung@vn.bosch.com>
Co-authored-by: Sudeep Mohanty <91244425+sudeep-mohanty@users.noreply.github.com>
Co-authored-by: Darian Leung <darian@espressif.com>
Co-authored-by: Tony Josi <tonyjosi@amazon.com>
Co-authored-by: Evgeny Ermakov <22344340+unspecd@users.noreply.github.com>
Co-authored-by: Joris Putcuyps <joris.putcuyps@gmail.com>
Co-authored-by: Patrick Cook <114708437+cookpate@users.noreply.github.com>
Co-authored-by: Mr. Jake <norbertzpilicy@gmail.com>
Co-authored-by: Soren Ptak <Skptak@outlook.com>
Co-authored-by: Soren Ptak <skptak@amazon.com>
---
 .github/lexicon.txt                           |   50 +-
 .github/scripts/kernel_checker.py             |    3 +-
 MISRA.md                                      |   72 +
 event_groups.c                                |   24 +-
 include/FreeRTOS.h                            |  146 +-
 include/task.h                                |  283 +-
 include/timers.h                              |   27 +-
 portable/ThirdParty/GCC/RP2040/README.md      |    9 +-
 .../ThirdParty/GCC/RP2040/include/portmacro.h |  115 +-
 .../GCC/RP2040/include/rp2040_config.h        |   19 +
 portable/ThirdParty/GCC/RP2040/library.cmake  |    7 +-
 portable/ThirdParty/GCC/RP2040/port.c         |  458 ++-
 portable/ThirdParty/xClang/XCOREAI/port.c     |  254 ++
 portable/ThirdParty/xClang/XCOREAI/port.xc    |   26 +
 portable/ThirdParty/xClang/XCOREAI/portasm.S  |  189 +
 .../ThirdParty/xClang/XCOREAI/portmacro.h     |  215 ++
 .../xClang/XCOREAI/rtos_support_rtos_config.h |   95 +
 queue.c                                       |   62 +-
 stream_buffer.c                               |   16 +-
 tasks.c                                       | 3321 ++++++++++++++---
 timers.c                                      |   79 +-
 21 files changed, 4694 insertions(+), 776 deletions(-)
 create mode 100644 MISRA.md
 create mode 100644 portable/ThirdParty/xClang/XCOREAI/port.c
 create mode 100644 portable/ThirdParty/xClang/XCOREAI/port.xc
 create mode 100644 portable/ThirdParty/xClang/XCOREAI/portasm.S
 create mode 100644 portable/ThirdParty/xClang/XCOREAI/portmacro.h
 create mode 100644 portable/ThirdParty/xClang/XCOREAI/rtos_support_rtos_config.h

diff --git a/.github/lexicon.txt b/.github/lexicon.txt
index ec6577e9e..853c73f22 100644
--- a/.github/lexicon.txt
+++ b/.github/lexicon.txt
@@ -319,6 +319,7 @@ coprocessor
 coprocessors
 coreid
 coroutinehandle
+coverity
 covfs
 cp
 cpacr
@@ -340,31 +341,20 @@ cprivilegedonlyaccessarray
 cpsid
 cpsie
 cpsr
-cpsr
-cpstored
 cpstored
 cpu
-cpu
 cr
-cr
-crc
 crc
 crcb
 crcoroutine
-crcoroutine
-crdelay
 crdelay
 creadonlyarray
 creadwritearray
 createevent
 crend
-crend
 crgint
 croutine
-croutine
 crqueue
-crqueue
-crstart
 crstart
 crt
 crtv
@@ -1110,6 +1100,7 @@ mikroc
 min
 mingw
 minilistitem
+minimalidle
 mips
 misadd
 misc
@@ -1539,12 +1530,11 @@ prstc
 prttc
 prv
 prvaddcurrenttasktodelayedlist
+prvcheckforrunstatechange
 prvcheckinterfaces
 prvchecktaskswaitingtermination
 prvcopydatatoqueue
 prvcoroutineflashtask
-prvcoroutineflashtask
-prvcoroutineflashworktask
 prvcoroutineflashworktask
 prvdeletetcb
 prvexitfunction
@@ -1552,12 +1542,12 @@ prvgettimens
 prvheapinit
 prvidletask
 prvinitialisecoroutinelists
-prvinitialisecoroutinelists
 prvinitialisemutex
 prvinitialisenewstreambuffer
 prvinitialisenewtimer
 prvinsertblockintofreelist
 prvlockqueue
+prvminimalidletask
 prvnotifyqueuesetcontainer
 prvportmalloc
 prvportresetpic
@@ -1575,6 +1565,7 @@ prvtickcount
 prvtimercallback
 prvwritebytestobuffer
 prvwritemessagetobuffer
+prvyieldfortask
 prvyieldhandler
 ps
 psp
@@ -1668,13 +1659,10 @@ pxcallbackfunction
 pxcode
 pxcontainer
 pxcoroutinecode
-pxcoroutinecode
-pxcoroutinewoken
 pxcoroutinewoken
 pxcrcb
 pxcreatedtask
 pxcurrentcoroutine
-pxcurrentcoroutine
 pxcurrenttcb
 pxcurrenttcbconst
 pxcurrenttimerlist
@@ -1795,6 +1783,7 @@ rdc
 rdr
 rdrf
 rdy
+reacquisition
 readbit
 readme
 readvalue
@@ -2439,6 +2428,7 @@ uxbitstoset
 uxbitstowait
 uxbitstowaitfor
 uxcontrolbits
+uxcoreaffinitymask
 uxcriticalnesting
 uxcurrenteventbits
 uxcurrentnumberoftasks
@@ -2462,9 +2452,12 @@ uxlength
 uxlistremove
 uxmaxcount
 uxmessageswaiting
+uxnetworkingcoreaffinitymask
 uxnewpriority
 uxoriginalpriority
+uxpendedcounts
 uxportcomparesetextram
+uxprevschedulersuspended
 uxpriority
 uxprioritytouse
 uxqueue
@@ -2483,6 +2476,7 @@ uxsemaphoregetcount
 uxsemaphoregetcountfromisr
 uxstate
 uxstreambuffernumber
+uxtaskattributes
 uxtaskgetnumberoftasks
 uxtaskgetstackhighwatermark
 uxtaskgetsystemstate
@@ -2516,6 +2510,7 @@ vapplicationgettimertaskmemory
 vapplicationidlehook
 vapplicationirqhandler
 vapplicationmallocfailedhook
+vapplicationminimalidlehook
 vapplicationsetuptickinterrupt
 vapplicationsetupticktimerinterrupt
 vapplicationsetuptimerinterrupt
@@ -2618,12 +2613,15 @@ vstreambufferdelete
 vtask
 vtaskallocatempuregions
 vtaskcode
+vtaskcoreaffinityget
+vtaskcoreaffinityset
 vtaskdelay
 vtaskdelayuntil
 vtaskdelete
 vtaskendscheduler
 vtaskentercritical
 vtaskexitcritical
+vtaskexitcriticalfromisr
 vtaskfunction
 vtaskgetinfo
 vtaskgetruntimestats
@@ -2632,6 +2630,8 @@ vtasknotify
 vtasknotifygivefromisr
 vtasknotifygiveindexedfromisr
 vtaskplaceoneventlist
+vtaskpreemptiondisable
+vtaskpreemptionenable
 vtaskpriorityset
 vtaskremovefromunorderedeventlist
 vtaskresume
@@ -2645,6 +2645,7 @@ vtasksteptick
 vtasksuspend
 vtasksuspendall
 vtaskswitchcontext
+vtaskswitchcontextforcore
 vtaskusesdpfpu
 vtickisr
 vtimercallback
@@ -2742,6 +2743,8 @@ xcommandtime
 xcommsrxqueue
 xconsttickcount
 xcopyposition
+xcore
+xcoreid
 xcoroutinecreate
 xcoroutinepreviouslywoken
 xcoroutinequeue
@@ -2824,6 +2827,8 @@ xhigherpriorittaskwoken
 xhigherprioritytaskwoken
 xhigherprioritytaskwokenbypost
 xidletaskhandle
+xidletaskhandles
+xidletcbbuffers
 xilinx
 xindex
 xinheritanceoccurred
@@ -2843,6 +2848,9 @@ xlastwaketime
 xlength
 xlist
 xlistend
+xlowestpriority
+xlowestprioritycore
+xlowestprioritytopreempt
 xmair
 xmaxcount
 xmaxexpirycountbeforestopping
@@ -2881,6 +2889,7 @@ xmutexbuffer
 xmutexholder
 xn
 xnearstartscheduler
+xnetworkingtaskhandle
 xnewperiod
 xnewqueue
 xnextexpiretime
@@ -2913,6 +2922,7 @@ xportregistercinterrupthandler
 xportregisterdump
 xportstartfirsttask
 xportstartscheduler
+xpreemptiondisable
 xpsr
 xqueue
 xqueueaddtoset
@@ -3026,6 +3036,7 @@ xtail
 xtal
 xtask
 xtaskabortdelay
+xtaskattribute
 xtaskbuffer
 xtaskcallapplicationtaskhook
 xtaskcatchupticks
@@ -3072,6 +3083,7 @@ xtasknumber
 xtaskremovefromeventlist
 xtaskresumeall
 xtaskresumefromisr
+xtaskrunstate
 xtaskswaitingforbits
 xtaskswaitingtermination
 xtaskswaitingtoreceive
@@ -3108,6 +3120,7 @@ xtimercreate
 xtimercreated
 xtimercreatestatic
 xtimerdelete
+xtimergenericcommand
 xtimergetexpirytime
 xtimergetperiod
 xtimergetreloadmode
@@ -3143,5 +3156,8 @@ xwantedsize
 xwasdelayed
 xwritevalue
 xxr
+xyieldfortask
 xyieldpending
+xyieldpendings
 xzr
+yeilding
diff --git a/.github/scripts/kernel_checker.py b/.github/scripts/kernel_checker.py
index f24bbf257..a0706932f 100755
--- a/.github/scripts/kernel_checker.py
+++ b/.github/scripts/kernel_checker.py
@@ -87,7 +87,8 @@ KERNEL_IGNORED_PATTERNS = [
     r'.*\.git.*',
     r'.*portable/IAR/AtmelSAM7S64/.*AT91SAM7.*',
     r'.*portable/GCC/ARM7_AT91SAM7S/.*',
-    r'.*portable/MPLAB/PIC18F/stdio.h'
+    r'.*portable/MPLAB/PIC18F/stdio.h',
+    r'.*portable/ThirdParty/xClang/XCOREAI/*'
 ]
 
 KERNEL_THIRD_PARTY_PATTERNS = [
diff --git a/MISRA.md b/MISRA.md
new file mode 100644
index 000000000..e7ebf77ea
--- /dev/null
+++ b/MISRA.md
@@ -0,0 +1,72 @@
+# MISRA Compliance
+
+FreeRTOS-Kernel conforms to [MISRA C:2012](https://www.misra.org.uk/misra-c)
+guidelines, with the deviations listed below. Compliance is checked with
+Coverity static analysis. Since the FreeRTOS kernel is designed for
+small-embedded devices, it needs to have a very small memory footprint and
+has to be efficient. To achieve that and to increase the performance, it
+deviates from some MISRA rules. The specific deviations, suppressed inline,
+are listed below.
+
+Additionally, [MISRA configuration](#misra-configuration) contains project
+wide deviations.
+
+### Suppressed with Coverity Comments
+To find the violation references in the source files run grep on the source code
+with ( Assuming rule 8.4 violation; with justification in point 1 ):
+```
+grep 'MISRA Ref 8.4.1' . -rI
+```
+
+#### Rule 8.4
+
+_Ref 8.4.1_
+
+- MISRA C:2012 Rule 8.4: A compatible declaration shall be visible when an
+        object or function with external linkage is defined.
+        This rule requires that a compatible declaration is made available
+        in a header file when an object with external linkage is defined.
+        pxCurrentTCB(s) is defined with external linkage but it is only
+        referenced from the assembly code in the port files. Therefore, adding
+        a declaration in header file is not useful as the assembly code will
+        still need to declare it separately.
+
+### MISRA configuration
+
+Copy below content to `misra.conf` to run Coverity on FreeRTOS-Kernel.
+
+```
+// MISRA C-2012 Rules
+{
+    version : "2.0",
+    standard : "c2012",
+    title: "Coverity MISRA Configuration",
+    deviations : [
+        // Disable the following rules.
+        {
+            deviation: "Directive 4.8",
+            reason: "HeapRegion_t and HeapStats_t are used only in heap files but declared in portable.h which is included in multiple source files. As a result, these definitions appear in multiple source files where they are not used."
+        },
+        {
+            deviation: "Directive 4.9",
+            reason: "FreeRTOS-Kernel is optimised to work on small micro-controllers. To achieve that, function-like macros are used."
+        },
+        {
+            deviation: "Rule 1.2",
+            reason: "The __attribute__ tags are used via macros which are defined in port files."
+        },
+        {
+            deviation: "Rule 3.1",
+            reason: "We post HTTP links in code comments which contain // inside comments blocks."
+        },
+        {
+            deviation: "Rule 8.7",
+            reason: "API functions are not used by the library outside of the files they are defined; however, they must be externally visible in order to be used by an application."
+        },
+        {
+            deviation: "Rule 11.5",
+            reason: "Allow casts from `void *`. List owner, pvOwner, is stored as `void *` and are cast to various types for use in functions."
+        }
+    ]
+}
+```
\ No newline at end of file
diff --git a/event_groups.c b/event_groups.c
index d7238d89a..ea4c79f4b 100644
--- a/event_groups.c
+++ b/event_groups.c
@@ -263,7 +263,15 @@ EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup,
     {
         if( xAlreadyYielded == pdFALSE )
         {
-            portYIELD_WITHIN_API();
+            #if ( configNUMBER_OF_CORES == 1 )
+            {
+                portYIELD_WITHIN_API();
+            }
+            #else /* #if ( configNUMBER_OF_CORES == 1 ) */
+            {
+                vTaskYieldWithinAPI();
+            }
+            #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
         }
         else
         {
@@ -415,7 +423,15 @@ EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
     {
         if( xAlreadyYielded == pdFALSE )
         {
-            portYIELD_WITHIN_API();
+            #if ( configNUMBER_OF_CORES == 1 )
+            {
+                portYIELD_WITHIN_API();
+            }
+            #else /* #if ( configNUMBER_OF_CORES == 1 ) */
+            {
+                vTaskYieldWithinAPI();
+            }
+            #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
         }
         else
         {
@@ -525,11 +541,11 @@ EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup )
     EventGroup_t const * const pxEventBits = xEventGroup;
     EventBits_t uxReturn;
 
-    uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+    uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
     {
         uxReturn = pxEventBits->uxEventBits;
     }
-    portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+    taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
 
     return uxReturn;
 } /*lint !e818 EventGroupHandle_t is a typedef used in other functions to so can't be pointer to const. */
diff --git a/include/FreeRTOS.h b/include/FreeRTOS.h
index 831ed037b..5016ebf5e 100644
--- a/include/FreeRTOS.h
+++ b/include/FreeRTOS.h
@@ -86,6 +86,11 @@
     #define configUSE_MPU_WRAPPERS_V1    0
 #endif
 
+/* Set default value of configNUMBER_OF_CORES to 1 to use single core FreeRTOS. */
+#ifndef configNUMBER_OF_CORES
+    #define configNUMBER_OF_CORES    1
+#endif
+
 /* Basic FreeRTOS definitions. */
 #include "projdefs.h"
 
@@ -164,6 +169,12 @@
     #error Missing definition:  configUSE_IDLE_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.
 #endif
 
+#if ( configNUMBER_OF_CORES > 1 )
+    #ifndef configUSE_MINIMAL_IDLE_HOOK
+        #error Missing definition:  configUSE_MINIMAL_IDLE_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.
+    #endif
+#endif
+
 #ifndef configUSE_TICK_HOOK
     #error Missing definition:  configUSE_TICK_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.
 #endif
@@ -306,6 +317,10 @@
     #define configUSE_COUNTING_SEMAPHORES    0
 #endif
 
+#ifndef configUSE_TASK_PREEMPTION_DISABLE
+    #define configUSE_TASK_PREEMPTION_DISABLE    0
+#endif
+
 #ifndef configUSE_ALTERNATIVE_API
     #define configUSE_ALTERNATIVE_API    0
 #endif
@@ -353,6 +368,110 @@
     #define portSOFTWARE_BARRIER()
 #endif
 
+#ifndef configRUN_MULTIPLE_PRIORITIES
+    #define configRUN_MULTIPLE_PRIORITIES    0
+#endif
+
+#ifndef portGET_CORE_ID
+
+    #if ( configNUMBER_OF_CORES == 1 )
+        #define portGET_CORE_ID()    0
+    #else
+        #error configNUMBER_OF_CORES is set to more than 1 then portGET_CORE_ID must also be defined.
+    #endif /* configNUMBER_OF_CORES */
+
+#endif /* portGET_CORE_ID */
+
+#ifndef portYIELD_CORE
+
+    #if ( configNUMBER_OF_CORES == 1 )
+        #define portYIELD_CORE( x )    portYIELD()
+    #else
+        #error configNUMBER_OF_CORES is set to more than 1 then portYIELD_CORE must also be defined.
+    #endif /* configNUMBER_OF_CORES */
+
+#endif /* portYIELD_CORE */
+
+#ifndef portSET_INTERRUPT_MASK
+
+    #if ( configNUMBER_OF_CORES > 1 )
+        #error portSET_INTERRUPT_MASK is required in SMP
+    #endif
+
+#endif /* portSET_INTERRUPT_MASK */
+
+#ifndef portCLEAR_INTERRUPT_MASK
+
+    #if ( configNUMBER_OF_CORES > 1 )
+        #error portCLEAR_INTERRUPT_MASK is required in SMP
+    #endif
+
+#endif /* portCLEAR_INTERRUPT_MASK */
+
+#ifndef portRELEASE_TASK_LOCK
+
+    #if ( configNUMBER_OF_CORES == 1 )
+        #define portRELEASE_TASK_LOCK()
+    #else
+        #error portRELEASE_TASK_LOCK is required in SMP
+    #endif
+
+#endif /* portRELEASE_TASK_LOCK */
+
+#ifndef portGET_TASK_LOCK
+
+    #if ( configNUMBER_OF_CORES == 1 )
+        #define portGET_TASK_LOCK()
+    #else
+        #error portGET_TASK_LOCK is required in SMP
+    #endif
+
+#endif /* portGET_TASK_LOCK */
+
+#ifndef portRELEASE_ISR_LOCK
+
+    #if ( configNUMBER_OF_CORES == 1 )
+        #define portRELEASE_ISR_LOCK()
+    #else
+        #error portRELEASE_ISR_LOCK is required in SMP
+    #endif
+
+#endif /* portRELEASE_ISR_LOCK */
+
+#ifndef portGET_ISR_LOCK
+
+    #if ( configNUMBER_OF_CORES == 1 )
+        #define portGET_ISR_LOCK()
+    #else
+        #error portGET_ISR_LOCK is required in SMP
+    #endif
+
+#endif /* portGET_ISR_LOCK */
+
+#ifndef portCHECK_IF_IN_ISR
+
+    #if ( configNUMBER_OF_CORES > 1 )
+        #error portCHECK_IF_IN_ISR is required in SMP
+    #endif
+
+#endif /* portCHECK_IF_IN_ISR */
+
+#ifndef portENTER_CRITICAL_FROM_ISR
+
+    #if ( configNUMBER_OF_CORES > 1 )
+        #error portENTER_CRITICAL_FROM_ISR is required in SMP
+    #endif
+
+#endif
+
+#ifndef portEXIT_CRITICAL_FROM_ISR
+
+    #if ( configNUMBER_OF_CORES > 1 )
+        #error portEXIT_CRITICAL_FROM_ISR is required in SMP
+    #endif
+
+#endif
+
 /* The timers module relies on xTaskGetSchedulerState(). */
 #if configUSE_TIMERS == 1
 
@@ -368,6 +487,10 @@
         #error If configUSE_TIMERS is set to 1 then configTIMER_TASK_STACK_DEPTH must also be defined.
     #endif /* configTIMER_TASK_STACK_DEPTH */
 
+    #ifndef portTIMER_CALLBACK_ATTRIBUTE
+        #define portTIMER_CALLBACK_ATTRIBUTE
+    #endif /* portTIMER_CALLBACK_ATTRIBUTE */
+
 #endif /* configUSE_TIMERS */
 
 #ifndef portSET_INTERRUPT_MASK_FROM_ISR
@@ -1018,6 +1141,18 @@
     #error configUSE_MUTEXES must be set to 1 to use recursive mutexes
 #endif
 
+#if ( ( configRUN_MULTIPLE_PRIORITIES == 0 ) && ( configUSE_TASK_PREEMPTION_DISABLE != 0 ) )
+    #error configRUN_MULTIPLE_PRIORITIES must be set to 1 to use task preemption disable
+#endif
+
+#if ( ( configUSE_PREEMPTION == 0 ) && ( configUSE_TASK_PREEMPTION_DISABLE != 0 ) )
+    #error configUSE_PREEMPTION must be set to 1 to use task preemption disable
+#endif
+
+#if ( ( configNUMBER_OF_CORES == 1 ) && ( configUSE_TASK_PREEMPTION_DISABLE != 0 ) )
+    #error configUSE_TASK_PREEMPTION_DISABLE is not supported in single core FreeRTOS
+#endif
+
 #ifndef configINITIAL_TICK_COUNT
     #define configINITIAL_TICK_COUNT    0
 #endif
@@ -1156,7 +1291,6 @@
     #define configRUN_ADDITIONAL_TESTS    0
 #endif
 
-
 /* Sometimes the FreeRTOSConfig.h settings only allow a task to be created using
  * dynamically allocated RAM, in which case when any task is deleted it is known
  * that both the task's stack and TCB need to be freed.  Sometimes the
@@ -1274,10 +1408,20 @@ typedef struct xSTATIC_TCB
     #if ( portUSING_MPU_WRAPPERS == 1 )
         xMPU_SETTINGS xDummy2;
     #endif
+    #if ( configUSE_CORE_AFFINITY == 1 ) && ( configNUMBER_OF_CORES > 1 )
+        UBaseType_t uxDummy26;
+    #endif
     StaticListItem_t xDummy3[ 2 ];
     UBaseType_t uxDummy5;
     void * pxDummy6;
+    #if ( configNUMBER_OF_CORES > 1 )
+        BaseType_t xDummy23;
+        UBaseType_t uxDummy24;
+    #endif
     uint8_t ucDummy7[ configMAX_TASK_NAME_LEN ];
+    #if ( configUSE_TASK_PREEMPTION_DISABLE == 1 )
+        BaseType_t xDummy25;
+    #endif
     #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) )
         void * pxDummy8;
     #endif
diff --git a/include/task.h b/include/task.h
index af17ced17..a7e1c795e 100644
--- a/include/task.h
+++ b/include/task.h
@@ -89,7 +89,8 @@
  * \ingroup Tasks
  */
 struct tskTaskControlBlock; /* The old naming convention is used to prevent breaking kernel aware debuggers. */
-typedef struct tskTaskControlBlock * TaskHandle_t;
+typedef struct tskTaskControlBlock         * TaskHandle_t;
+typedef const struct tskTaskControlBlock   * ConstTaskHandle_t;
 
 /*
  * Defines the prototype to which the application task hook function must
@@ -171,6 +172,9 @@ typedef struct xTASK_STATUS
         StackType_t * pxEndOfStack;               /* Points to the end address of the task's stack area. */
     #endif
     configSTACK_DEPTH_TYPE usStackHighWaterMark;  /* The minimum amount of stack space that has remained for the task since the task was created.  The closer this value is to zero the closer the task has come to overflowing its stack. */
+    #if ( ( configUSE_CORE_AFFINITY == 1 ) && ( configNUMBER_OF_CORES > 1 ) )
+        UBaseType_t uxCoreAffinityMask;           /* The core affinity mask for the task */
+    #endif
 } TaskStatus_t;
 
 /* Possible return values for eTaskConfirmSleepModeStatus(). */
@@ -190,6 +194,13 @@ typedef enum
  */
 #define tskIDLE_PRIORITY    ( ( UBaseType_t ) 0U )
 
+/**
+ * Defines affinity to all available cores.
+ *
+ * \ingroup TaskUtils
+ */
+#define tskNO_AFFINITY      ( ( UBaseType_t ) -1 )
+
 /**
  * task. h
  *
@@ -198,7 +209,7 @@ typedef enum
  * \defgroup taskYIELD taskYIELD
  * \ingroup SchedulerControl
  */
-#define taskYIELD()                        portYIELD()
+#define taskYIELD()                          portYIELD()
 
 /**
  * task. h
@@ -212,8 +223,12 @@ typedef enum
  * \defgroup taskENTER_CRITICAL taskENTER_CRITICAL
  * \ingroup SchedulerControl
  */
-#define taskENTER_CRITICAL()               portENTER_CRITICAL()
-#define taskENTER_CRITICAL_FROM_ISR()      portSET_INTERRUPT_MASK_FROM_ISR()
+#define taskENTER_CRITICAL()                 portENTER_CRITICAL()
+#if ( configNUMBER_OF_CORES == 1 )
+    #define taskENTER_CRITICAL_FROM_ISR()    portSET_INTERRUPT_MASK_FROM_ISR()
+#else
+    #define taskENTER_CRITICAL_FROM_ISR()    portENTER_CRITICAL_FROM_ISR()
+#endif
 
 /**
  * task. h
@@ -227,8 +242,12 @@ typedef enum
  * \defgroup taskEXIT_CRITICAL taskEXIT_CRITICAL
  * \ingroup SchedulerControl
  */
-#define taskEXIT_CRITICAL()                portEXIT_CRITICAL()
-#define taskEXIT_CRITICAL_FROM_ISR( x )    portCLEAR_INTERRUPT_MASK_FROM_ISR( x )
+#define taskEXIT_CRITICAL()                    portEXIT_CRITICAL()
+#if ( configNUMBER_OF_CORES == 1 )
+    #define taskEXIT_CRITICAL_FROM_ISR( x )    portCLEAR_INTERRUPT_MASK_FROM_ISR( x )
+#else
+    #define taskEXIT_CRITICAL_FROM_ISR( x )    portEXIT_CRITICAL_FROM_ISR( x )
+#endif
 
 /**
  * task. h
@@ -238,7 +257,7 @@ typedef enum
  * \defgroup taskDISABLE_INTERRUPTS taskDISABLE_INTERRUPTS
  * \ingroup SchedulerControl
  */
-#define taskDISABLE_INTERRUPTS()           portDISABLE_INTERRUPTS()
+#define taskDISABLE_INTERRUPTS()    portDISABLE_INTERRUPTS()
 
 /**
  * task. h
@@ -248,7 +267,7 @@ typedef enum
  * \defgroup taskENABLE_INTERRUPTS taskENABLE_INTERRUPTS
  * \ingroup SchedulerControl
  */
-#define taskENABLE_INTERRUPTS()            portENABLE_INTERRUPTS()
+#define taskENABLE_INTERRUPTS()     portENABLE_INTERRUPTS()
 
 /* Definitions returned by xTaskGetSchedulerState().  taskSCHEDULER_SUSPENDED is
  * 0 to generate more optimal code when configASSERT() is defined as the constant
@@ -257,6 +276,8 @@ typedef enum
 #define taskSCHEDULER_NOT_STARTED    ( ( BaseType_t ) 1 )
 #define taskSCHEDULER_RUNNING        ( ( BaseType_t ) 2 )
 
+/* Checks if core ID is valid. */
+#define taskVALID_CORE_ID( xCoreID )    ( ( ( ( ( BaseType_t ) 0 <= ( xCoreID ) ) && ( ( xCoreID ) < ( BaseType_t ) configNUMBER_OF_CORES ) ) ) ? ( pdTRUE ) : ( pdFALSE ) )
 
 /*-----------------------------------------------------------
 * TASK CREATION API
@@ -365,6 +386,16 @@ typedef enum
                             TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION;
 #endif
 
+#if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
+    BaseType_t xTaskCreateAffinitySet( TaskFunction_t pxTaskCode,
+                                       const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+                                       const configSTACK_DEPTH_TYPE usStackDepth,
+                                       void * const pvParameters,
+                                       UBaseType_t uxPriority,
+                                       UBaseType_t uxCoreAffinityMask,
+                                       TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION;
+#endif
+
 /**
  * task. h
  * @code{c}
@@ -483,6 +514,17 @@ typedef enum
                                     StaticTask_t * const pxTaskBuffer ) PRIVILEGED_FUNCTION;
 #endif /* configSUPPORT_STATIC_ALLOCATION */
 
+#if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
+    TaskHandle_t xTaskCreateStaticAffinitySet( TaskFunction_t pxTaskCode,
+                                               const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+                                               const uint32_t ulStackDepth,
+                                               void * const pvParameters,
+                                               UBaseType_t uxPriority,
+                                               StackType_t * const puxStackBuffer,
+                                               StaticTask_t * const pxTaskBuffer,
+                                               UBaseType_t uxCoreAffinityMask ) PRIVILEGED_FUNCTION;
+#endif
+
 /**
  * task. h
  * @code{c}
@@ -561,6 +603,12 @@ typedef enum
                                       TaskHandle_t * pxCreatedTask ) PRIVILEGED_FUNCTION;
 #endif
 
+#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
+    BaseType_t xTaskCreateRestrictedAffinitySet( const TaskParameters_t * const pxTaskDefinition,
+                                                 UBaseType_t uxCoreAffinityMask,
+                                                 TaskHandle_t * pxCreatedTask ) PRIVILEGED_FUNCTION;
+#endif
+
 /**
  * task. h
  * @code{c}
@@ -651,6 +699,12 @@ typedef enum
                                             TaskHandle_t * pxCreatedTask ) PRIVILEGED_FUNCTION;
 #endif
 
+#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
+    BaseType_t xTaskCreateRestrictedStaticAffinitySet( const TaskParameters_t * const pxTaskDefinition,
+                                                       UBaseType_t uxCoreAffinityMask,
+                                                       TaskHandle_t * pxCreatedTask ) PRIVILEGED_FUNCTION;
+#endif
+
 /**
  * task. h
  * @code{c}
@@ -698,7 +752,7 @@ typedef enum
  * \defgroup vTaskAllocateMPURegions vTaskAllocateMPURegions
  * \ingroup Tasks
  */
-void vTaskAllocateMPURegions( TaskHandle_t xTask,
+void vTaskAllocateMPURegions( TaskHandle_t xTaskToModify,
                               const MemoryRegion_t * const pxRegions ) PRIVILEGED_FUNCTION;
 
 /**
@@ -1228,6 +1282,164 @@ void vTaskResume( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION;
  */
 BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION;
 
+#if ( configUSE_CORE_AFFINITY == 1 )
+
+/**
+ * @brief Sets the core affinity mask for a task.
+ *
+ * It sets the cores on which a task can run. configUSE_CORE_AFFINITY must
+ * be defined as 1 for this function to be available.
+ *
+ * @param xTask The handle of the task to set the core affinity mask for.
+ * Passing NULL will set the core affinity mask for the calling task.
+ *
+ * @param uxCoreAffinityMask A bitwise value that indicates the cores on
+ * which the task can run. Cores are numbered from 0 to configNUMBER_OF_CORES - 1.
+ * For example, to ensure that a task can run on core 0 and core 1, set
+ * uxCoreAffinityMask to 0x03.
+ *
+ * Example usage:
+ *
+ * // The function that creates task.
+ * void vAFunction( void )
+ * {
+ * TaskHandle_t xHandle;
+ * UBaseType_t uxCoreAffinityMask;
+ *
+ *      // Create a task, storing the handle.
+ *      xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &( xHandle ) );
+ *
+ *      // Define the core affinity mask such that this task can only run
+ *      // on core 0 and core 2.
+ *      uxCoreAffinityMask = ( ( 1 << 0 ) | ( 1 << 2 ) );
+ *
+ *      //Set the core affinity mask for the task.
+ *      vTaskCoreAffinitySet( xHandle, uxCoreAffinityMask );
+ * }
+ */
+    void vTaskCoreAffinitySet( const TaskHandle_t xTask,
+                               UBaseType_t uxCoreAffinityMask );
+#endif
+
+#if ( configUSE_CORE_AFFINITY == 1 )
+
+/**
+ * @brief Gets the core affinity mask for a task.
+ *
+ * configUSE_CORE_AFFINITY must be defined as 1 for this function to be
+ * available.
+ *
+ * @param xTask The handle of the task to get the core affinity mask for.
+ * Passing NULL will get the core affinity mask for the calling task.
+ *
+ * @return The core affinity mask which is a bitwise value that indicates
+ * the cores on which a task can run. Cores are numbered from 0 to
+ * configNUMBER_OF_CORES - 1. For example, if a task can run on core 0 and core 1,
+ * the core affinity mask is 0x03.
+ *
+ * Example usage:
+ *
+ * // Task handle of the networking task - it is populated elsewhere.
+ * TaskHandle_t xNetworkingTaskHandle;
+ *
+ * void vAFunction( void )
+ * {
+ * TaskHandle_t xHandle;
+ * UBaseType_t uxNetworkingCoreAffinityMask;
+ *
+ *     // Create a task, storing the handle.
+ *     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &( xHandle ) );
+ *
+ *     //Get the core affinity mask for the networking task.
+ *     uxNetworkingCoreAffinityMask = vTaskCoreAffinityGet( xNetworkingTaskHandle );
+ *
+ *     // Here is a hypothetical scenario, just for the example. Assume that we
+ *     // have 2 cores - Core 0 and core 1. We want to pin the application task to
+ *     // the core different than the networking task to ensure that the
+ *     // application task does not interfere with networking.
+ *     if( ( uxNetworkingCoreAffinityMask & ( 1 << 0 ) ) != 0 )
+ *     {
+ *         // The networking task can run on core 0, pin our task to core 1.
+ *         vTaskCoreAffinitySet( xHandle, ( 1 << 1 ) );
+ *     }
+ *     else
+ *     {
+ *         // Otherwise, pin our task to core 0.
+ *         vTaskCoreAffinitySet( xHandle, ( 1 << 0 ) );
+ *     }
+ * }
+ */
+    UBaseType_t vTaskCoreAffinityGet( ConstTaskHandle_t xTask );
+#endif
+
+#if ( configUSE_TASK_PREEMPTION_DISABLE == 1 )
+
+/**
+ * @brief Disables preemption for a task.
+ *
+ * @param xTask The handle of the task to disable preemption. Passing NULL
+ * disables preemption for the calling task.
+ *
+ * Example usage:
+ *
+ * void vTaskCode( void *pvParameters )
+ * {
+ *     // Silence warnings about unused parameters.
+ *     ( void ) pvParameters;
+ *
+ *     for( ;; )
+ *     {
+ *         // ... Perform some function here.
+ *
+ *         // Disable preemption for this task.
+ *         vTaskPreemptionDisable( NULL );
+ *
+ *         // The task will not be preempted when it is executing in this portion ...
+ *
+ *         // ... until the preemption is enabled again.
+ *         vTaskPreemptionEnable( NULL );
+ *
+ *         // The task can be preempted when it is executing in this portion.
+ *     }
+ * }
+ */
+    void vTaskPreemptionDisable( const TaskHandle_t xTask );
+#endif
+
+#if ( configUSE_TASK_PREEMPTION_DISABLE == 1 )
+
+/**
+ * @brief Enables preemption for a task.
+ *
+ * @param xTask The handle of the task to enable preemption. Passing NULL
+ * enables preemption for the calling task.
+ *
+ * Example usage:
+ *
+ * void vTaskCode( void *pvParameters )
+ * {
+ *     // Silence warnings about unused parameters.
+ *     ( void ) pvParameters;
+ *
+ *     for( ;; )
+ *     {
+ *         // ... Perform some function here.
+ *
+ *         // Disable preemption for this task.
+ *         vTaskPreemptionDisable( NULL );
+ *
+ *         // The task will not be preempted when it is executing in this portion ...
+ *
+ *         // ... until the preemption is enabled again.
+ *         vTaskPreemptionEnable( NULL );
+ *
+ *         // The task can be preempted when it is executing in this portion.
+ *     }
+ * }
+ */
+    void vTaskPreemptionEnable( const TaskHandle_t xTask );
+#endif
+
 /*-----------------------------------------------------------
 * SCHEDULER CONTROL
 *----------------------------------------------------------*/
@@ -3099,7 +3311,11 @@ void vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem,
  * Sets the pointer to the current TCB to the TCB of the highest priority task
  * that is ready to run.
  */
-portDONT_DISCARD void vTaskSwitchContext( void ) PRIVILEGED_FUNCTION;
+#if ( configNUMBER_OF_CORES == 1 )
+    portDONT_DISCARD void vTaskSwitchContext( void ) PRIVILEGED_FUNCTION;
+#else
+    portDONT_DISCARD void vTaskSwitchContext( BaseType_t xCoreID ) PRIVILEGED_FUNCTION;
+#endif
 
 /*
  * THESE FUNCTIONS MUST NOT BE USED FROM APPLICATION CODE.  THEY ARE USED BY
@@ -3112,6 +3328,11 @@ TickType_t uxTaskResetEventItemValue( void ) PRIVILEGED_FUNCTION;
  */
 TaskHandle_t xTaskGetCurrentTaskHandle( void ) PRIVILEGED_FUNCTION;
 
+/*
+ * Return the handle of the task running on specified core.
+ */
+TaskHandle_t xTaskGetCurrentTaskHandleCPU( BaseType_t xCoreID ) PRIVILEGED_FUNCTION;
+
 /*
  * Shortcut used by the queue implementation to prevent unnecessary call to
  * taskYIELD();
@@ -3197,6 +3418,48 @@ TaskHandle_t pvTaskIncrementMutexHeldCount( void ) PRIVILEGED_FUNCTION;
  */
 void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION;
 
+/*
+ * For internal use only. Same as portYIELD_WITHIN_API() in single core FreeRTOS.
+ * For SMP this is not defined by the port.
+ */
+void vTaskYieldWithinAPI( void );
+
+/*
+ * This function is only intended for use when implementing a port of the scheduler
+ * and is only available when portCRITICAL_NESTING_IN_TCB is set to 1 or configNUMBER_OF_CORES
+ * is greater than 1. This function can be used in the implementation of portENTER_CRITICAL
+ * if port wants to maintain critical nesting count in TCB in single core FreeRTOS.
+ * It should be used in the implementation of portENTER_CRITICAL if port is running a
+ * multiple core FreeRTOS.
+ */
+void vTaskEnterCritical( void );
+
+/*
+ * This function is only intended for use when implementing a port of the scheduler
+ * and is only available when portCRITICAL_NESTING_IN_TCB is set to 1 or configNUMBER_OF_CORES
+ * is greater than 1. This function can be used in the implementation of portEXIT_CRITICAL
+ * if port wants to maintain critical nesting count in TCB in single core FreeRTOS.
+ * It should be used in the implementation of portEXIT_CRITICAL if port is running a
+ * multiple core FreeRTOS.
+ */
+void vTaskExitCritical( void );
+
+/*
+ * This function is only intended for use when implementing a port of the scheduler
+ * and is only available when configNUMBER_OF_CORES is greater than 1. This function
+ * should be used in the implementation of portENTER_CRITICAL_FROM_ISR if port is
+ * running a multiple core FreeRTOS.
+ */
+UBaseType_t vTaskEnterCriticalFromISR( void );
+
+/*
+ * This function is only intended for use when implementing a port of the scheduler
+ * and is only available when configNUMBER_OF_CORES is greater than 1. This function
+ * should be used in the implementation of portEXIT_CRITICAL_FROM_ISR if port is
+ * running a multiple core FreeRTOS.
+ */
+void vTaskExitCriticalFromISR( UBaseType_t uxSavedInterruptStatus );
+
 #if ( portUSING_MPU_WRAPPERS == 1 )
 
 /*
diff --git a/include/timers.h b/include/timers.h
index 2967a4674..054ec097f 100644
--- a/include/timers.h
+++ b/include/timers.h
@@ -1348,12 +1348,29 @@ TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
  * for use by the kernel only.
  */
 BaseType_t xTimerCreateTimerTask( void ) PRIVILEGED_FUNCTION;
-BaseType_t xTimerGenericCommand( TimerHandle_t xTimer,
-                                 const BaseType_t xCommandID,
-                                 const TickType_t xOptionalValue,
-                                 BaseType_t * const pxHigherPriorityTaskWoken,
-                                 const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
 
+/*
+ * Splitting the xTimerGenericCommand into two sub functions and making it a macro
+ * removes a recursion path when called from ISRs. This is primarily for the XCore
+ * XCC port which detects the recursion path and throws an error during compilation
+ * when this is not split.
+ */
+BaseType_t xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                         const BaseType_t xCommandID,
+                                         const TickType_t xOptionalValue,
+                                         BaseType_t * const pxHigherPriorityTaskWoken,
+                                         const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+BaseType_t xTimerGenericCommandFromISR( TimerHandle_t xTimer,
+                                        const BaseType_t xCommandID,
+                                        const TickType_t xOptionalValue,
+                                        BaseType_t * const pxHigherPriorityTaskWoken,
+                                        const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+#define xTimerGenericCommand( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait )         \
+    ( ( xCommandID ) < tmrFIRST_FROM_ISR_COMMAND ?                                                                  \
+      xTimerGenericCommandFromTask( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait ) : \
+      xTimerGenericCommandFromISR( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait ) )
 #if ( configUSE_TRACE_FACILITY == 1 )
     void vTimerSetTimerNumber( TimerHandle_t xTimer,
                                UBaseType_t uxTimerNumber ) PRIVILEGED_FUNCTION;
diff --git a/portable/ThirdParty/GCC/RP2040/README.md b/portable/ThirdParty/GCC/RP2040/README.md
index c50cb4e38..7c4dbe23a 100644
--- a/portable/ThirdParty/GCC/RP2040/README.md
+++ b/portable/ThirdParty/GCC/RP2040/README.md
@@ -1,12 +1,13 @@
 ## Overview
 
-This directory provides a FreeRTOS-Kernel port that can be used with the Raspberry Pi Pico SDK. It supports:
+This directory provides an SMP FreeRTOS-Kernel port that can be used with the Raspberry Pi Pico SDK. It supports:
 
  * Simple CMake INTERFACE libraries, to provide the FreeRTOS-Kernel and also the individual allocator types, without copying code into the user's project.
- * Running the FreeRTOS-Kernel and tasks on either core 0 or core 1
- * Use of SDK synchronization primitives (such as mutexes, semaphores, queues from pico_sync) between FreeRTOS tasks and code executing on the other core, or in IRQ handlers.
+ * Running the FreeRTOS-Kernel and tasks on either core 0 or core 1, or both.
+ * Use of SDK synchronization primitives (such as mutexes, semaphores, queues from pico_sync) between FreeRTOS tasks and code executing on a non FreeRTOS core, or in IRQ handlers.
 
-Note that a FreeRTOS SMP version of this port is also available in the FreeRTOS-Kernel smp branch, which additionally supports utilizing both RP2040 CPU cores for FreeRTOS tasks simultaneously.
+Note that whilst this SMP version can be run on just a single (either) core, it is probably
+more efficient to use the non SMP version in the main FreeRTOS-Kernel branch in that case.
 
 ## Using this port
 
diff --git a/portable/ThirdParty/GCC/RP2040/include/portmacro.h b/portable/ThirdParty/GCC/RP2040/include/portmacro.h
index 973ac39f0..655b8ec74 100644
--- a/portable/ThirdParty/GCC/RP2040/include/portmacro.h
+++ b/portable/ThirdParty/GCC/RP2040/include/portmacro.h
@@ -37,6 +37,8 @@
 /* *INDENT-ON* */
 
     #include "pico.h"
+    #include "hardware/sync.h"
+
 /*-----------------------------------------------------------
  * Port specific definitions.
  *
@@ -108,14 +110,56 @@
         #define xPortSysTickHandler isr_systick
     #endif
 
+/*-----------------------------------------------------------*/
+
+/* Multi-core */
+    #define portMAX_CORE_COUNT            2
+
+    /* Check validity of number of cores specified in config */
+    #if ( configNUMBER_OF_CORES < 1 || portMAX_CORE_COUNT < configNUMBER_OF_CORES )
+        #error "Invalid number of cores specified in config!"
+    #endif
+
+    #if ( configTICK_CORE < 0 || configTICK_CORE > configNUMBER_OF_CORES )
+        #error "Invalid tick core specified in config!"
+    #endif
+    /* FreeRTOS core id is always zero based, so always 0 if we're running on only one core */
+    #if configNUMBER_OF_CORES == portMAX_CORE_COUNT
+        #define portGET_CORE_ID() get_core_num()
+    #else
+        #define portGET_CORE_ID() 0
+    #endif
+
     #define portCHECK_IF_IN_ISR() ({ \
         uint32_t ulIPSR;                                                  \
        __asm volatile ("mrs %0, IPSR" : "=r" (ulIPSR)::);             \
        ((uint8_t)ulIPSR)>0;})
 
+    void vYieldCore(int xCoreID);
+    #define portYIELD_CORE(a) vYieldCore(a)
+    #define portRESTORE_INTERRUPTS(ulState) __asm volatile ("msr PRIMASK,%0"::"r" (ulState) : )
+
+/*-----------------------------------------------------------*/
+
+/* Critical nesting count management. */
+    extern UBaseType_t uxCriticalNestings[ configNUMBER_OF_CORES ];
+    #define portGET_CRITICAL_NESTING_COUNT()        ( uxCriticalNestings[ portGET_CORE_ID() ] )
+    #define portSET_CRITICAL_NESTING_COUNT( x )     ( uxCriticalNestings[ portGET_CORE_ID() ] = ( x ) )
+    #define portINCREMENT_CRITICAL_NESTING_COUNT()  ( uxCriticalNestings[ portGET_CORE_ID() ]++ )
+    #define portDECREMENT_CRITICAL_NESTING_COUNT()  ( uxCriticalNestings[ portGET_CORE_ID() ]-- )
+
 /*-----------------------------------------------------------*/
 
 /* Critical section management. */
+
+    #define portSET_INTERRUPT_MASK()                     ({               \
+       uint32_t ulState;                                                  \
+       __asm volatile ("mrs %0, PRIMASK" : "=r" (ulState)::);             \
+       __asm volatile ( " cpsid i " ::: "memory" );                       \
+       ulState;})
+
+    #define portCLEAR_INTERRUPT_MASK(ulState) __asm volatile ("msr PRIMASK,%0"::"r" (ulState) : )
+
     extern uint32_t ulSetInterruptMaskFromISR( void ) __attribute__( ( naked ) );
     extern void vClearInterruptMaskFromISR( uint32_t ulMask )  __attribute__( ( naked ) );
     #define portSET_INTERRUPT_MASK_FROM_ISR()         ulSetInterruptMaskFromISR()
@@ -126,10 +170,73 @@
     extern void vPortEnableInterrupts();
     #define portENABLE_INTERRUPTS()                   vPortEnableInterrupts()
 
-    extern void vPortEnterCritical( void );
-    extern void vPortExitCritical( void );
-    #define portENTER_CRITICAL()                      vPortEnterCritical()
-    #define portEXIT_CRITICAL()                       vPortExitCritical()
+    #if ( configNUMBER_OF_CORES == 1 )
+        extern void vPortEnterCritical( void );
+        extern void vPortExitCritical( void );
+        #define portENTER_CRITICAL()                      vPortEnterCritical()
+        #define portEXIT_CRITICAL()                       vPortExitCritical()
+    #else
+        extern void vTaskEnterCritical( void );
+        extern void vTaskExitCritical( void );
+        extern UBaseType_t vTaskEnterCriticalFromISR( void );
+        extern void vTaskExitCriticalFromISR( UBaseType_t uxSavedInterruptStatus );
+        #define portENTER_CRITICAL()                      vTaskEnterCritical()
+        #define portEXIT_CRITICAL()                       vTaskExitCritical()
+        #define portENTER_CRITICAL_FROM_ISR()             vTaskEnterCriticalFromISR()
+        #define portEXIT_CRITICAL_FROM_ISR( x )           vTaskExitCriticalFromISR( x )
+    #endif
+
+	#define portRTOS_SPINLOCK_COUNT 2
+
+    /* Note this is a single method with uxAcquire parameter since we have
+     * static vars, the method is always called with a compile time constant for
+     * uxAcquire, and the compiler should dothe right thing! */
+    static inline void vPortRecursiveLock(uint32_t ulLockNum, spin_lock_t *pxSpinLock, BaseType_t uxAcquire) {
+        static uint8_t ucOwnedByCore[ portMAX_CORE_COUNT ];
+        static uint8_t ucRecursionCountByLock[ portRTOS_SPINLOCK_COUNT ];
+        configASSERT(ulLockNum >= 0 && ulLockNum < portRTOS_SPINLOCK_COUNT );
+        uint32_t ulCoreNum = get_core_num();
+        uint32_t ulLockBit = 1u << ulLockNum;
+        configASSERT(ulLockBit < 256u );
+        if( uxAcquire )
+        {
+            if( __builtin_expect( !*pxSpinLock, 0 ) )
+            {
+                if( ucOwnedByCore[ulCoreNum] & ulLockBit )
+                {
+                    configASSERT(ucRecursionCountByLock[ulLockNum] != 255u );
+                    ucRecursionCountByLock[ulLockNum]++;
+                    return;
+                }
+                while ( __builtin_expect( !*pxSpinLock, 0 ) );
+            }
+            __mem_fence_acquire();
+            configASSERT(ucRecursionCountByLock[ulLockNum] == 0 );
+            ucRecursionCountByLock[ulLockNum] = 1;
+            ucOwnedByCore[ulCoreNum] |= ulLockBit;
+        } else {
+            configASSERT((ucOwnedByCore[ulCoreNum] & ulLockBit) != 0 );
+            configASSERT(ucRecursionCountByLock[ulLockNum] != 0 );
+            if( !--ucRecursionCountByLock[ulLockNum] )
+            {
+                ucOwnedByCore[ulCoreNum] &= ~ulLockBit;
+                __mem_fence_release();
+                *pxSpinLock = 1;
+            }
+        }
+    }
+
+    #if ( configNUMBER_OF_CORES == 1 )
+        #define portGET_ISR_LOCK()
+        #define portRELEASE_ISR_LOCK()
+        #define portGET_TASK_LOCK()
+        #define portRELEASE_TASK_LOCK()
+    #else
+        #define portGET_ISR_LOCK()      vPortRecursiveLock(0, spin_lock_instance(configSMP_SPINLOCK_0), pdTRUE)
+        #define portRELEASE_ISR_LOCK()  vPortRecursiveLock(0, spin_lock_instance(configSMP_SPINLOCK_0), pdFALSE)
+        #define portGET_TASK_LOCK()     vPortRecursiveLock(1, spin_lock_instance(configSMP_SPINLOCK_1), pdTRUE)
+        #define portRELEASE_TASK_LOCK() vPortRecursiveLock(1, spin_lock_instance(configSMP_SPINLOCK_1), pdFALSE)
+    #endif
 
 /*-----------------------------------------------------------*/
 
diff --git a/portable/ThirdParty/GCC/RP2040/include/rp2040_config.h b/portable/ThirdParty/GCC/RP2040/include/rp2040_config.h
index 2406bd921..35c6f2463 100644
--- a/portable/ThirdParty/GCC/RP2040/include/rp2040_config.h
+++ b/portable/ThirdParty/GCC/RP2040/include/rp2040_config.h
@@ -65,6 +65,25 @@
     #endif
 #endif
 
+#if ( configNUMBER_OF_CORES > 1 )
+    /* configTICK_CORE indicates which core should handle the SysTick
+     * interrupts */
+    #ifndef configTICK_CORE
+        #define configTICK_CORE 0
+    #endif
+#endif
+
+/* This SMP port requires two spin locks, which are claimed from the SDK.
+ * the spin lock numbers to be used are defined statically and defaulted here
+ * to the values nominally set aside for RTOS by the SDK */
+#ifndef configSMP_SPINLOCK_0
+    #define configSMP_SPINLOCK_0 PICO_SPINLOCK_ID_OS1
+#endif
+
+#ifndef configSMP_SPINLOCK_1
+    #define configSMP_SPINLOCK_1 PICO_SPINLOCK_ID_OS2
+#endif
+
 /* *INDENT-OFF* */
 #ifdef __cplusplus
     }
diff --git a/portable/ThirdParty/GCC/RP2040/library.cmake b/portable/ThirdParty/GCC/RP2040/library.cmake
index 902a21766..1db96517a 100644
--- a/portable/ThirdParty/GCC/RP2040/library.cmake
+++ b/portable/ThirdParty/GCC/RP2040/library.cmake
@@ -33,11 +33,14 @@ target_include_directories(FreeRTOS-Kernel INTERFACE
 target_link_libraries(FreeRTOS-Kernel INTERFACE
         FreeRTOS-Kernel-Core
         pico_base_headers
-        hardware_exception)
+        hardware_clocks
+        hardware_exception
+        pico_multicore
+)
 
 target_compile_definitions(FreeRTOS-Kernel INTERFACE
         LIB_FREERTOS_KERNEL=1
-        FREERTOS_KERNEL_SMP=0
+        FREE_RTOS_KERNEL_SMP=1
 )
 
 add_library(FreeRTOS-Kernel-Static INTERFACE)
diff --git a/portable/ThirdParty/GCC/RP2040/port.c b/portable/ThirdParty/GCC/RP2040/port.c
index 41dd114a0..73452e068 100644
--- a/portable/ThirdParty/GCC/RP2040/port.c
+++ b/portable/ThirdParty/GCC/RP2040/port.c
@@ -46,6 +46,9 @@
     #include "pico/multicore.h"
 #endif /* LIB_PICO_MULTICORE */
 
+/* TODO : consider to remove this macro. */
+#define portRUNNING_ON_BOTH_CORES ( configNUMBER_OF_CORES == portMAX_CORE_COUNT )
+
 /* Constants required to manipulate the NVIC. */
 #define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )
 #define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )
@@ -112,7 +115,11 @@ static void prvTaskExitError( void );
 /* Each task maintains its own interrupt status in the critical nesting
  * variable. This is initialized to 0 to allow vPortEnter/ExitCritical
  * to be called before the scheduler is started */
-static UBaseType_t uxCriticalNesting;
+#if ( configNUMBER_OF_CORES == 1 )
+    static UBaseType_t uxCriticalNesting;
+#else /* #if ( configNUMBER_OF_CORES == 1 ) */
+    UBaseType_t uxCriticalNestings[ configNUMBER_OF_CORES ] = { 0 };
+#endif /* #if ( configNUMBER_OF_CORES == 1 ) */
 
 /*-----------------------------------------------------------*/
 
@@ -125,13 +132,13 @@ static UBaseType_t uxCriticalNesting;
         #define pEventGroup (&xStaticEventGroup)
     #endif /* configSUPPORT_STATIC_ALLOCATION */
     static EventGroupHandle_t xEventGroup;
-    #if ( LIB_PICO_MULTICORE == 1 )
+    #if ( portRUNNING_ON_BOTH_CORES == 0 )
         static EventBits_t uxCrossCoreEventBits;
         static spin_lock_t * pxCrossCoreSpinLock;
-    #endif /* LIB_PICO_MULTICORE */
+    #endif
 
-    static spin_lock_t * pxYieldSpinLock;
-    static uint32_t ulYieldSpinLockSaveValue;
+    static spin_lock_t * pxYieldSpinLock[ configNUMBER_OF_CORES ];
+    static uint32_t ulYieldSpinLockSaveValue[ configNUMBER_OF_CORES ];
 #endif /* configSUPPORT_PICO_SYNC_INTEROP */
 
 /*
@@ -159,9 +166,16 @@ static UBaseType_t uxCriticalNesting;
 
 /*-----------------------------------------------------------*/
 
-#define INVALID_LAUNCH_CORE_NUM 0xffu
-static uint8_t ucLaunchCoreNum = INVALID_LAUNCH_CORE_NUM;
-#define portIS_FREE_RTOS_CORE() ( ucLaunchCoreNum == get_core_num() )
+#define INVALID_PRIMARY_CORE_NUM 0xffu
+/* The primary core number (the own which has the SysTick handler) */
+static uint8_t ucPrimaryCoreNum = INVALID_PRIMARY_CORE_NUM;
+
+/* Note: portIS_FREE_RTOS_CORE() also returns false until the scheduler is started */
+#if ( portRUNNING_ON_BOTH_CORES == 1 )
+    #define portIS_FREE_RTOS_CORE() (ucPrimaryCoreNum != INVALID_PRIMARY_CORE_NUM)
+#else
+    #define portIS_FREE_RTOS_CORE() (ucPrimaryCoreNum == get_core_num())
+#endif
 
 /*
  * See header file for description.
@@ -204,6 +218,7 @@ void vPortSVCHandler( void )
 
 void vPortStartFirstTask( void )
 {
+#if ( configNUMBER_OF_CORES == 1 )
     __asm volatile (
         "   .syntax unified             \n"
         "   ldr  r2, pxCurrentTCBConst1 \n"/* Obtain location of pxCurrentTCB. */
@@ -220,9 +235,49 @@ void vPortStartFirstTask( void )
         "   pop  {r2}                   \n"/* Pop and discard XPSR. */
         "   cpsie i                     \n"/* The first task has its context and interrupts can be enabled. */
         "   bx   r3                     \n"/* Finally, jump to the user defined task code. */
-    "   .align 4                       \n"
-    "pxCurrentTCBConst1: .word pxCurrentTCB\n"
+	"   .align 4                       \n"
+	"pxCurrentTCBConst1: .word pxCurrentTCB\n"
     );
+#else
+    __asm volatile (
+        "    .syntax unified                    \n"
+        #if configRESET_STACK_POINTER
+            "   ldr  r0, =0xE000ED08            \n" /* Use the NVIC offset register to locate the stack. */
+            "   ldr r0, [r0]                    \n"
+            "   ldr r0, [r0]                    \n"
+            "   msr msp, r0                     \n" /* Set the msp back to the start of the stack. */
+        #endif /* configRESET_STACK_POINTER */
+        #if portRUNNING_ON_BOTH_CORES
+            "   adr r1, ulAsmLocals             \n"/* Get the location of the current TCB for the current core. */
+            "   ldmia r1!, {r2, r3}             \n"
+            "   ldr r2, [r2]                    \n"/* r2 = Core number */
+            "   lsls r2, #2                     \n"
+            "   ldr r3, [r3, r2]                \n"/* r3 = pxCurrentTCBs[get_core_num()] */
+        #else
+            "   ldr r3, =pxCurrentTCBs          \n"
+            "   ldr r3, [r3]                    \n" /* r3 = pxCurrentTCBs[0] */
+        #endif /* portRUNNING_ON_BOTH_CORES */
+        "    ldr  r0, [r3]                       \n"/* The first item in pxCurrentTCB is the task top of stack. */
+        "    adds r0, #32                        \n"/* Discard everything up to r0. */
+        "    msr  psp, r0                        \n"/* This is now the new top of stack to use in the task. */
+        "    movs r0, #2                         \n"/* Switch to the psp stack. */
+        "    msr  CONTROL, r0                    \n"
+        "    isb                                 \n"
+        "    pop  {r0-r5}                        \n"/* Pop the registers that are saved automatically. */
+        "    mov  lr, r5                         \n"/* lr is now in r5. */
+        "    pop  {r3}                           \n"/* Return address is now in r3. */
+        "    pop  {r2}                           \n"/* Pop and discard XPSR. */
+        "    cpsie i                             \n"/* The first task has its context and interrupts can be enabled. */
+        "    bx   r3                             \n"/* Finally, jump to the user defined task code. */
+        #if portRUNNING_ON_BOTH_CORES
+            "                                   \n"
+            "     .align 4                      \n"
+            "ulAsmLocals:                       \n"
+            "    .word 0xD0000000               \n"/* SIO */
+            "    .word pxCurrentTCBs            \n"
+        #endif /* portRUNNING_ON_BOTH_CORES */
+    );
+#endif
 }
 /*-----------------------------------------------------------*/
 
@@ -232,66 +287,158 @@ void vPortStartFirstTask( void )
         /* We must remove the contents (which we don't care about)
          * to clear the IRQ */
         multicore_fifo_drain();
+
+        /* And explicitly clear any other IRQ flags. */
         multicore_fifo_clear_irq();
-        BaseType_t xHigherPriorityTaskWoken = pdFALSE;
-        uint32_t ulSave = spin_lock_blocking( pxCrossCoreSpinLock );
-        EventBits_t ulBits = uxCrossCoreEventBits;
-        uxCrossCoreEventBits &= ~ulBits;
-        spin_unlock( pxCrossCoreSpinLock, ulSave );
-        xEventGroupSetBitsFromISR( xEventGroup, ulBits, &xHigherPriorityTaskWoken );
-        portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+
+        #if ( portRUNNING_ON_BOTH_CORES == 1 )
+            portYIELD_FROM_ISR( pdTRUE );
+        #elif ( configSUPPORT_PICO_SYNC_INTEROP == 1 )
+            BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+            uint32_t ulSave = spin_lock_blocking( pxCrossCoreSpinLock );
+            EventBits_t ulBits = uxCrossCoreEventBits;
+            uxCrossCoreEventBits &= ~ulBits;
+            spin_unlock( pxCrossCoreSpinLock, ulSave );
+            xEventGroupSetBitsFromISR( xEventGroup, ulBits, &xHigherPriorityTaskWoken );
+            portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+        #endif /* portRUNNING_ON_BOTH_CORES */
     }
 #endif
 
-/*
- * See header file for description.
- */
-BaseType_t xPortStartScheduler( void )
-{
-    /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
-    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
-    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+#if ( configNUMBER_OF_CORES > 1 )
+    /*
+     * See header file for description.
+     */
+    static BaseType_t xPortStartSchedulerOnCore()
+    {
+        if( ucPrimaryCoreNum == get_core_num())
+        {
+            /* Start the timer that generates the tick ISR.  Interrupts are disabled
+             * here already. */
+            vPortSetupTimerInterrupt();
 
-    #if (configUSE_DYNAMIC_EXCEPTION_HANDLERS == 1)
-        exception_set_exclusive_handler( PENDSV_EXCEPTION, xPortPendSVHandler );
-        exception_set_exclusive_handler( SYSTICK_EXCEPTION, xPortSysTickHandler );
-        exception_set_exclusive_handler( SVCALL_EXCEPTION, vPortSVCHandler );
-    #endif
+            /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+            portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+            #if ( configUSE_DYNAMIC_EXCEPTION_HANDLERS == 1 )
+                exception_set_exclusive_handler( SYSTICK_EXCEPTION, xPortSysTickHandler );
+            #endif
+        }
 
-    /* Start the timer that generates the tick ISR.  Interrupts are disabled
-     * here already. */
-    vPortSetupTimerInterrupt();
+        portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
 
-    /* Initialise the critical nesting count ready for the first task. */
-    uxCriticalNesting = 0;
-
-    ucLaunchCoreNum = get_core_num();
-    #if (LIB_PICO_MULTICORE == 1)
-        #if ( configSUPPORT_PICO_SYNC_INTEROP == 1)
-            multicore_fifo_clear_irq();
-            multicore_fifo_drain();
-            uint32_t irq_num = 15 + get_core_num();
-            irq_set_priority( irq_num, portMIN_INTERRUPT_PRIORITY );
-            irq_set_exclusive_handler( irq_num, prvFIFOInterruptHandler );
-            irq_set_enabled( irq_num, 1 );
+        #if ( configUSE_DYNAMIC_EXCEPTION_HANDLERS == 1 )
+            exception_set_exclusive_handler( PENDSV_EXCEPTION, xPortPendSVHandler );
+            exception_set_exclusive_handler( SVCALL_EXCEPTION, vPortSVCHandler );
         #endif
+
+        /* Install FIFO handler to receive interrupt from other core */
+        multicore_fifo_clear_irq();
+        multicore_fifo_drain();
+        uint32_t ulIRQNum = SIO_IRQ_PROC0 + get_core_num();
+        irq_set_priority( ulIRQNum, portMIN_INTERRUPT_PRIORITY );
+        irq_set_exclusive_handler( ulIRQNum, prvFIFOInterruptHandler );
+        irq_set_enabled( ulIRQNum, 1 );
+
+        /* Start the first task. */
+        vPortStartFirstTask();
+
+        /* Should never get here as the tasks will now be executing!  Call the task
+         * exit error function to prevent compiler warnings about a static function
+         * not being called in the case that the application writer overrides this
+         * functionality by defining configTASK_RETURN_ADDRESS.  Call
+         * vTaskSwitchContext() so link time optimisation does not remove the
+         * symbol. */
+        vTaskSwitchContext( portGET_CORE_ID() );
+        prvTaskExitError();
+
+        /* Should not get here! */
+        return 0;
+    }
+
+    #if portRUNNING_ON_BOTH_CORES
+        static void prvDisableInterruptsAndPortStartSchedulerOnCore( void )
+        {
+            portDISABLE_INTERRUPTS();
+            xPortStartSchedulerOnCore();
+        }
     #endif
 
-    /* Start the first task. */
-    vPortStartFirstTask();
+    /*
+     * See header file for description.
+     */
+    BaseType_t xPortStartScheduler( void )
+    {
+        configASSERT( ucPrimaryCoreNum == INVALID_PRIMARY_CORE_NUM );
 
-    /* Should never get here as the tasks will now be executing!  Call the task
-     * exit error function to prevent compiler warnings about a static function
-     * not being called in the case that the application writer overrides this
-     * functionality by defining configTASK_RETURN_ADDRESS.  Call
-     * vTaskSwitchContext() so link time optimisation does not remove the
-     * symbol. */
-    vTaskSwitchContext();
-    prvTaskExitError();
+        /* No one else should use these! */
+        spin_lock_claim( configSMP_SPINLOCK_0 );
+        spin_lock_claim( configSMP_SPINLOCK_1 );
+
+        #if portRUNNING_ON_BOTH_CORES
+            ucPrimaryCoreNum = configTICK_CORE;
+            configASSERT( get_core_num() == 0) ; // we must be started on core 0
+            multicore_launch_core1( prvDisableInterruptsAndPortStartSchedulerOnCore );
+        #else
+            ucPrimaryCoreNum = get_core_num();
+        #endif
+        xPortStartSchedulerOnCore();
+
+        /* Should not get here! */
+        return 0;
+    }
+
+#else
+    /*
+     * See header file for description.
+     */
+    BaseType_t xPortStartScheduler( void )
+    {
+        /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+        portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
+        portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+
+        #if (configUSE_DYNAMIC_EXCEPTION_HANDLERS == 1)
+            exception_set_exclusive_handler( PENDSV_EXCEPTION, xPortPendSVHandler );
+            exception_set_exclusive_handler( SYSTICK_EXCEPTION, xPortSysTickHandler );
+            exception_set_exclusive_handler( SVCALL_EXCEPTION, vPortSVCHandler );
+        #endif
+
+        /* Start the timer that generates the tick ISR.  Interrupts are disabled
+         * here already. */
+        vPortSetupTimerInterrupt();
+
+        /* Initialise the critical nesting count ready for the first task. */
+        uxCriticalNesting = 0;
+
+        ucPrimaryCoreNum = get_core_num();
+        #if (LIB_PICO_MULTICORE == 1)
+            #if ( configSUPPORT_PICO_SYNC_INTEROP == 1)
+                multicore_fifo_clear_irq();
+                multicore_fifo_drain();
+                uint32_t irq_num = 15 + get_core_num();
+                irq_set_priority( irq_num, portMIN_INTERRUPT_PRIORITY );
+                irq_set_exclusive_handler( irq_num, prvFIFOInterruptHandler );
+                irq_set_enabled( irq_num, 1 );
+            #endif
+        #endif
+
+        /* Start the first task. */
+        vPortStartFirstTask();
+
+        /* Should never get here as the tasks will now be executing!  Call the task
+         * exit error function to prevent compiler warnings about a static function
+         * not being called in the case that the application writer overrides this
+         * functionality by defining configTASK_RETURN_ADDRESS.  Call
+         * vTaskSwitchContext() so link time optimisation does not remove the
+         * symbol. */
+        vTaskSwitchContext();
+        prvTaskExitError();
+
+        /* Should not get here! */
+        return 0;
+    }
+#endif
 
-    /* Should not get here! */
-    return 0;
-}
 /*-----------------------------------------------------------*/
 
 void vPortEndScheduler( void )
@@ -305,8 +452,8 @@ void vPortYield( void )
 {
     #if ( configSUPPORT_PICO_SYNC_INTEROP == 1 )
         /* We are not in an ISR, and pxYieldSpinLock is always dealt with and
-         * cleared interrupts are re-enabled, so should be NULL */
-        configASSERT( pxYieldSpinLock == NULL );
+         * cleared when interrupts are re-enabled, so should be NULL */
+        configASSERT( pxYieldSpinLock[ portGET_CORE_ID() ] == NULL );
     #endif /* configSUPPORT_PICO_SYNC_INTEROP */
 
     /* Set a PendSV to request a context switch. */
@@ -320,31 +467,38 @@ void vPortYield( void )
 
 /*-----------------------------------------------------------*/
 
-void vPortEnterCritical( void )
-{
-    portDISABLE_INTERRUPTS();
-    uxCriticalNesting++;
-    __asm volatile ( "dsb" ::: "memory" );
-    __asm volatile ( "isb" );
-}
+#if ( configNUMBER_OF_CORES == 1 )
+    void vPortEnterCritical( void )
+    {
+        portDISABLE_INTERRUPTS();
+        uxCriticalNesting++;
+        __asm volatile ( "dsb" ::: "memory" );
+        __asm volatile ( "isb" );
+    }
+#endif /* #if ( configNUMBER_OF_CORES == 1 ) */
 /*-----------------------------------------------------------*/
 
-void vPortExitCritical( void )
-{
-    configASSERT( uxCriticalNesting );
-    uxCriticalNesting--;
-    if( uxCriticalNesting == 0 )
+#if ( configNUMBER_OF_CORES == 1 )
+    void vPortExitCritical( void )
     {
-        portENABLE_INTERRUPTS();
-    }
-}
-
-void vPortEnableInterrupts() {
-    #if ( configSUPPORT_PICO_SYNC_INTEROP == 1 )
-        if( pxYieldSpinLock )
+        configASSERT( uxCriticalNesting );
+        uxCriticalNesting--;
+        if( uxCriticalNesting == 0 )
         {
-            spin_unlock(pxYieldSpinLock, ulYieldSpinLockSaveValue);
-            pxYieldSpinLock = NULL;
+            portENABLE_INTERRUPTS();
+        }
+    }
+#endif /* #if ( configNUMBER_OF_CORES == 1 ) */
+
+void vPortEnableInterrupts( void )
+{
+    #if ( configSUPPORT_PICO_SYNC_INTEROP == 1 )
+        int xCoreID = portGET_CORE_ID();
+        if( pxYieldSpinLock[xCoreID] )
+        {
+            spin_lock_t* const pxTmpLock = pxYieldSpinLock[xCoreID];
+            pxYieldSpinLock[xCoreID] = NULL;
+            spin_unlock( pxTmpLock, ulYieldSpinLockSaveValue[xCoreID] );
         }
     #endif
     __asm volatile ( " cpsie i " ::: "memory" );
@@ -371,12 +525,25 @@ void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask )
         ::: "memory"
         );
 }
+
+/*-----------------------------------------------------------*/
+
+void vYieldCore( int xCoreID )
+{
+    configASSERT(xCoreID != portGET_CORE_ID());
+    #if portRUNNING_ON_BOTH_CORES
+        /* Non blocking, will cause interrupt on other core if the queue isn't already full,
+        in which case an IRQ must be pending */
+        sio_hw->fifo_wr = 0;
+    #endif
+}
+
 /*-----------------------------------------------------------*/
 
 void xPortPendSVHandler( void )
 {
     /* This is a naked function. */
-
+#if ( configNUMBER_OF_CORES == 1 )
     __asm volatile
     (
         "   .syntax unified                     \n"
@@ -452,9 +619,103 @@ void xPortPendSVHandler( void )
         "   ldmia r0!, {r4-r7}                  \n"/* Pop low registers.  */
         "                                       \n"
         "   bx r3                               \n"
-    "   .align 4                            \n"
-    "pxCurrentTCBConst2: .word pxCurrentTCB \n"
+	"   .align 4                            \n"
+	"pxCurrentTCBConst2: .word pxCurrentTCB \n"
     );
+#else
+    __asm volatile
+    (
+        "   .syntax unified                     \n"
+        "   mrs r1, psp                         \n"
+        "                                       \n"
+        "   adr    r0, ulAsmLocals2             \n"/* Get the location of the current TCB for the current core. */
+        "   ldmia r0!, {r2, r3}                 \n"
+        #if portRUNNING_ON_BOTH_CORES
+            "   ldr r0, [r2]                    \n"/* r0 = Core number */
+            "   lsls r0, r0, #2                 \n"
+            "   adds r3, r0                     \n"/* r3 = &pxCurrentTCBs[get_core_num()] */
+        #else
+            "                                   \n"/* r3 = &pxCurrentTCBs[0] */
+        #endif /* portRUNNING_ON_BOTH_CORES */
+        "   ldr    r0, [r3]                     \n"/* r0 = pxCurrentTCB */
+        "                                       \n"
+        "   subs r1, r1, #32                    \n"/* Make space for the remaining low registers. */
+        "   str r1, [r0]                        \n"/* Save the new top of stack. */
+        "   stmia r1!, {r4-r7}                  \n"/* Store the low registers that are not saved automatically. */
+        "   mov r4, r8                          \n"/* Store the high registers. */
+        "   mov r5, r9                          \n"
+        "   mov r6, r10                         \n"
+        "   mov r7, r11                         \n"
+        "   stmia r1!, {r4-r7}                  \n"
+        #if portUSE_DIVIDER_SAVE_RESTORE
+            /* We expect that the divider is ready at this point (which is
+             * necessary to safely save/restore), because:
+             * a) if we have not been interrupted since we entered this method,
+             *    then >8 cycles have clearly passed, so the divider is done
+             * b) if we were interrupted in the interim, then any "safe" - i.e.
+             *    does the right thing in an IRQ - use of the divider should
+             *    have waited for any in-process divide to complete, saved and
+             *    then fully restored the result, thus the result is ready in
+             *    that case too. */
+            "   ldr r4, [r2, #0x60]             \n"/* SIO_DIV_UDIVIDEND_OFFSET */
+            "   ldr r5, [r2, #0x64]             \n"/* SIO_DIV_UDIVISOR_OFFSET */
+            "   ldr r6, [r2, #0x74]             \n"/* SIO_DIV_REMAINDER_OFFSET */
+            "   ldr r7, [r2, #0x70]             \n"/* SIO_DIV_QUOTIENT_OFFSET */
+            /* We actually save the divider state in the 4 words below
+             * our recorded stack pointer, so as not to disrupt the stack
+             * frame expected by debuggers - this is addressed by
+             * portEXTRA_STACK_SIZE */
+            "   subs r1, r1, #48                \n"
+            "   stmia r1!, {r4-r7}              \n"
+        #endif /* portUSE_DIVIDER_SAVE_RESTORE */
+        #if portRUNNING_ON_BOTH_CORES
+            "   ldr r0, [r2]                    \n"/* r0 = Core number */
+        #else
+            "   movs r0, #0                     \n"
+        #endif /* portRUNNING_ON_BOTH_CORES */
+        "   push {r3, r14}                      \n"
+        "   cpsid i                             \n"
+        "   bl vTaskSwitchContext               \n"
+        "   cpsie i                             \n"
+        "   pop {r2, r3}                        \n"/* lr goes in r3. r2 now holds tcb pointer. */
+        "                                       \n"
+        "   ldr r1, [r2]                        \n"
+        "   ldr r0, [r1]                        \n"/* The first item in pxCurrentTCB is the task top of stack. */
+        "   adds r0, r0, #16                    \n"/* Move to the high registers. */
+        "   ldmia r0!, {r4-r7}                  \n"/* Pop the high registers. */
+        "    mov r8, r4                         \n"
+        "    mov r9, r5                         \n"
+        "    mov r10, r6                        \n"
+        "    mov r11, r7                        \n"
+        "                                       \n"
+        "   msr psp, r0                         \n"/* Remember the new top of stack for the task. */
+        "                                       \n"
+        #if portUSE_DIVIDER_SAVE_RESTORE
+        "   movs r2, #0xd                       \n"/* Pop the divider state. */
+        "   lsls r2, #28                        \n"
+        "   subs r0, r0, #48                    \n"/* Go back for the divider state */
+        "   ldmia r0!, {r4-r7}                  \n"/* Pop the divider state. */
+        /* Note always restore via SIO_DIV_UDIVI*, because we will overwrite the
+         * results stopping the calculation anyway, however the sign of results
+         * is adjusted by the h/w at read time based on whether the last started
+         * division was signed and the inputs' signs differed */
+        "   str r4, [r2, #0x60]                \n"/* SIO_DIV_UDIVIDEND_OFFSET */
+        "   str r5, [r2, #0x64]                \n"/* SIO_DIV_UDIVISOR_OFFSET */
+        "   str r6, [r2, #0x74]                \n"/* SIO_DIV_REMAINDER_OFFSET */
+        "   str r7, [r2, #0x70]                \n"/* SIO_DIV_QUOTIENT_OFFSET */
+        #else
+        "   subs r0, r0, #32                   \n"/* Go back for the low registers that are not automatically restored. */
+        #endif /* portUSE_DIVIDER_SAVE_RESTORE */
+        "   ldmia r0!, {r4-r7}                 \n"/* Pop low registers.  */
+        "                                      \n"
+        "   bx r3                              \n"
+        "                                      \n"
+        "   .align 4                           \n"
+        "ulAsmLocals2:                         \n"
+        "   .word 0xD0000000                   \n"/* SIO */
+        "   .word pxCurrentTCBs                \n"
+    );
+#endif
 }
 /*-----------------------------------------------------------*/
 
@@ -462,7 +723,7 @@ void xPortSysTickHandler( void )
 {
     uint32_t ulPreviousMask;
 
-    ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+    ulPreviousMask = taskENTER_CRITICAL_FROM_ISR();
     {
         /* Increment the RTOS tick. */
         if( xTaskIncrementTick() != pdFALSE )
@@ -471,7 +732,7 @@ void xPortSysTickHandler( void )
             portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
         }
     }
-    portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
+    taskEXIT_CRITICAL_FROM_ISR( ulPreviousMask );
 }
 /*-----------------------------------------------------------*/
 
@@ -729,6 +990,7 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
     void vPortLockInternalSpinUnlockWithWait( struct lock_core * pxLock, uint32_t ulSave )
     {
         configASSERT( !portCHECK_IF_IN_ISR() );
+        // note no need to check LIB_PICO_MULTICORE, as this is always returns true if that is not defined
         if( !portIS_FREE_RTOS_CORE() )
         {
             spin_unlock(pxLock->spin_lock, ulSave );
@@ -736,14 +998,15 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
         }
         else
         {
-            configASSERT( pxYieldSpinLock == NULL );
+            configASSERT( pxYieldSpinLock[ portGET_CORE_ID() ] == NULL );
 
             // we want to hold the lock until the event bits have been set; since interrupts are currently disabled
             // by the spinlock, we can defer until portENABLE_INTERRUPTS is called which is always called when
             // the scheduler is unlocked during this call
             configASSERT(pxLock->spin_lock);
-            pxYieldSpinLock = pxLock->spin_lock;
-            ulYieldSpinLockSaveValue = ulSave;
+            int xCoreID = portGET_CORE_ID();
+            pxYieldSpinLock[xCoreID] = pxLock->spin_lock;
+            ulYieldSpinLockSaveValue[xCoreID] = ulSave;
             xEventGroupWaitBits( xEventGroup, prvGetEventGroupBit(pxLock->spin_lock),
                                  pdTRUE, pdFALSE, portMAX_DELAY);
         }
@@ -771,7 +1034,7 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
         else
         {
             __sev();
-            #if ( LIB_PICO_MULTICORE == 1)
+            #if ( portRUNNING_ON_BOTH_CORES == 0 )
                 /* We could sent the bits across the FIFO which would have required us to block here if the FIFO was full,
                  * or we could have just set all bits on the other side, however it seems reasonable instead to take
                  * the hit of another spin lock to protect an accurate bit set. */
@@ -787,7 +1050,7 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
                 }
                 /* This causes fifo irq on the other (FreeRTOS) core which will do the set the event bits */
                 sio_hw->fifo_wr = 0;
-            #endif /* LIB_PICO_MULTICORE */
+            #endif /* portRUNNING_ON_BOTH_CORES == 0 */
             spin_unlock(pxLock->spin_lock, ulSave);
         }
     }
@@ -803,7 +1066,8 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
         }
         else
         {
-            configASSERT( pxYieldSpinLock == NULL );
+            configASSERT( portIS_FREE_RTOS_CORE() );
+            configASSERT( pxYieldSpinLock[ portGET_CORE_ID() ] == NULL );
 
             TickType_t uxTicksToWait = prvGetTicksToWaitBefore( uxUntil );
             if( uxTicksToWait )
@@ -812,14 +1076,12 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
                  * by the spinlock, we can defer until portENABLE_INTERRUPTS is called which is always called when
                  * the scheduler is unlocked during this call */
                 configASSERT(pxLock->spin_lock);
-                pxYieldSpinLock = pxLock->spin_lock;
-                ulYieldSpinLockSaveValue = ulSave;
+                int xCoreID = portGET_CORE_ID();
+                pxYieldSpinLock[xCoreID] = pxLock->spin_lock;
+                ulYieldSpinLockSaveValue[xCoreID] = ulSave;
                 xEventGroupWaitBits( xEventGroup,
                                      prvGetEventGroupBit(pxLock->spin_lock), pdTRUE,
                                      pdFALSE, uxTicksToWait );
-                /* sanity check that interrupts were disabled, then re-enabled during the call, which will have
-                 * taken care of the yield */
-                configASSERT( pxYieldSpinLock == NULL );
             }
             else
             {
@@ -845,7 +1107,7 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
         {
             /* This must be done even before the scheduler is started, as the spin lock
              * is used by the overrides of the SDK wait/notify primitives */
-            #if ( LIB_PICO_MULTICORE == 1 )
+            #if ( portRUNNING_ON_BOTH_CORES == 0 )
                 pxCrossCoreSpinLock = spin_lock_instance( next_striped_spin_lock_num() );
             #endif /* portRUNNING_ON_BOTH_CORES */
 
diff --git a/portable/ThirdParty/xClang/XCOREAI/port.c b/portable/ThirdParty/xClang/XCOREAI/port.c
new file mode 100644
index 000000000..0d7307383
--- /dev/null
+++ b/portable/ThirdParty/xClang/XCOREAI/port.c
@@ -0,0 +1,254 @@
+// Copyright (c) 2019, XMOS Ltd, All rights reserved
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include <string.h>
+#include <xs1.h>
+#include <xcore/hwtimer.h>
+#include <xcore/triggerable.h>
+
+static hwtimer_t xKernelTimer;
+
+uint32_t ulPortYieldRequired[ portMAX_CORE_COUNT ] = { pdFALSE };
+
+/*-----------------------------------------------------------*/
+
+void vIntercoreInterruptISR( void )
+{
+	int xCoreID;
+
+//	debug_printf( "In KCALL: %u\n", ulData );
+	xCoreID = rtos_core_id_get();
+	ulPortYieldRequired[ xCoreID ] = pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+DEFINE_RTOS_INTERRUPT_CALLBACK( pxKernelTimerISR, pvData )
+{
+	uint32_t ulLastTrigger;
+	uint32_t ulNow;
+	int xCoreID;
+    UBaseType_t uxSavedInterruptStatus;
+
+	xCoreID = 0;
+
+	configASSERT( xCoreID == rtos_core_id_get() );
+
+	/* Need the next interrupt to be scheduled relative to
+	 * the current trigger time, rather than the current
+	 * time. */
+	ulLastTrigger = hwtimer_get_trigger_time( xKernelTimer );
+
+	/* Check to see if the ISR is late. If it is, we don't
+	 * want to schedule the next interrupt to be in the past. */
+	ulNow = hwtimer_get_time( xKernelTimer );
+	if( ulNow - ulLastTrigger >= configCPU_CLOCK_HZ / configTICK_RATE_HZ )
+	{
+		ulLastTrigger = ulNow;
+	}
+
+	ulLastTrigger += configCPU_CLOCK_HZ / configTICK_RATE_HZ;
+	hwtimer_change_trigger_time( xKernelTimer, ulLastTrigger );
+
+#if configUPDATE_RTOS_TIME_FROM_TICK_ISR == 1
+	rtos_time_increment( RTOS_TICK_PERIOD( configTICK_RATE_HZ ) );
+#endif
+
+    uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
+	if( xTaskIncrementTick() != pdFALSE )
+	{
+		ulPortYieldRequired[ xCoreID ] = pdTRUE;
+	}
+    taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
+}
+/*-----------------------------------------------------------*/
+
+void vPortYieldOtherCore( int xOtherCoreID )
+{
+	int xCoreID;
+
+	/*
+	 * This function must be called from within a critical section.
+	 */
+
+	xCoreID = rtos_core_id_get();
+
+//	debug_printf("%d->%d\n", xCoreID, xOtherCoreID);
+
+//	debug_printf("Yield core %d from %d\n", xOtherCoreID, xCoreID );
+
+	rtos_irq( xOtherCoreID, xCoreID );
+}
+/*-----------------------------------------------------------*/
+
+static int prvCoreInit( void )
+{
+	int xCoreID;
+
+	xCoreID = rtos_core_register();
+	debug_printf( "Logical Core %d initializing as FreeRTOS Core %d\n", get_logical_core_id(), xCoreID );
+
+	asm volatile (
+			"ldap r11, kexcept\n\t"
+			"set kep, r11\n\t"
+			:
+			:
+			: "r11"
+	);
+
+	rtos_irq_enable( configNUMBER_OF_CORES );
+
+	/*
+	 * All threads wait here until all have enabled IRQs
+	 */
+	while( rtos_irq_ready() == pdFALSE );
+
+	if( xCoreID == 0 )
+	{
+		uint32_t ulNow;
+		ulNow = hwtimer_get_time( xKernelTimer );
+//		debug_printf( "The time is now (%u)\n", ulNow );
+
+		ulNow += configCPU_CLOCK_HZ / configTICK_RATE_HZ;
+
+		triggerable_setup_interrupt_callback( xKernelTimer, NULL, RTOS_INTERRUPT_CALLBACK( pxKernelTimerISR ) );
+		hwtimer_set_trigger_time( xKernelTimer, ulNow );
+		triggerable_enable_trigger( xKernelTimer );
+	}
+
+	return xCoreID;
+}
+/*-----------------------------------------------------------*/
+
+DEFINE_RTOS_KERNEL_ENTRY( void, vPortStartSchedulerOnCore, void )
+{
+	int xCoreID;
+
+	xCoreID = prvCoreInit();
+
+	#if( configUSE_CORE_INIT_HOOK == 1 )
+	{
+		extern void vApplicationCoreInitHook( BaseType_t xCoreID );
+
+		vApplicationCoreInitHook( xCoreID );
+	}
+	#endif
+
+	debug_printf( "FreeRTOS Core %d initialized\n", xCoreID );
+
+	/*
+	 * Restore the context of the first thread
+	 * to run and jump into it.
+	 */
+	asm volatile (
+			"mov r6, %0\n\t" /* R6 must be the FreeRTOS core ID*/
+			"ldaw r5, dp[pxCurrentTCBs]\n\t" /* R5 must be the TCB list which is indexed by R6 */
+			"bu _freertos_restore_ctx\n\t"
+			: /* no outputs */
+			: "r"(xCoreID)
+			: "r5", "r6"
+	);
+}
+/*-----------------------------------------------------------*/
+
+/*-----------------------------------------------------------*/
+/* Public functions required by all ports below:             */
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	//debug_printf( "Top of stack was %p for task %p\n", pxTopOfStack, pxCode );
+	/*
+	 * Grow the thread's stack by portTHREAD_CONTEXT_STACK_GROWTH
+	 * so we can push the context onto it.
+	 */
+	pxTopOfStack -= portTHREAD_CONTEXT_STACK_GROWTH;
+
+	uint32_t dp;
+	uint32_t cp;
+
+	/*
+	 * We need to get the current CP and DP pointers.
+	 */
+	asm volatile (
+			"ldaw r11, cp[0]\n\t" /* get CP into R11 */
+			"mov %0, r11\n\t" /* get R11 (CP) into cp */
+			"ldaw r11, dp[0]\n\t" /* get DP into R11 */
+			"mov %1, r11\n\t" /* get R11 (DP) into dp */
+			: "=r"(cp), "=r"(dp) /* output 0 is cp, output 1 is dp */
+			: /* there are no inputs */
+			: "r11" /* R11 gets clobbered */
+	);
+
+	/*
+	 * Push the thread context onto the stack.
+	 * Saved PC will point to the new thread's
+	 * entry pointer.
+	 * Interrupts will default to enabled.
+	 * KEDI is also set to enable dual issue mode
+	 * upon kernel entry.
+	 */
+	pxTopOfStack[ 1 ] = ( StackType_t ) pxCode;       /* SP[1]  := SPC */
+    pxTopOfStack[ 2 ] = XS1_SR_IEBLE_MASK
+                      | XS1_SR_KEDI_MASK;             /* SP[2]  := SSR */
+	pxTopOfStack[ 3 ] = 0x00000000;                   /* SP[3]  := SED */
+	pxTopOfStack[ 4 ] = 0x00000000;                   /* SP[4]  := ET */
+	pxTopOfStack[ 5 ] = dp;                           /* SP[5]  := DP */
+	pxTopOfStack[ 6 ] = cp;                           /* SP[6]  := CP */
+	pxTopOfStack[ 7 ] = 0x00000000;                   /* SP[7]  := LR */
+	pxTopOfStack[ 8 ] = ( StackType_t ) pvParameters; /* SP[8]  := R0 */
+	pxTopOfStack[ 9 ] = 0x01010101;                   /* SP[9]  := R1 */
+	pxTopOfStack[ 10 ] = 0x02020202;                  /* SP[10] := R2 */
+	pxTopOfStack[ 11 ] = 0x03030303;                  /* SP[11] := R3 */
+	pxTopOfStack[ 12 ] = 0x04040404;                  /* SP[12] := R4 */
+	pxTopOfStack[ 13 ] = 0x05050505;                  /* SP[13] := R5 */
+	pxTopOfStack[ 14 ] = 0x06060606;                  /* SP[14] := R6 */
+	pxTopOfStack[ 15 ] = 0x07070707;                  /* SP[15] := R7 */
+	pxTopOfStack[ 16 ] = 0x08080808;                  /* SP[16] := R8 */
+	pxTopOfStack[ 17 ] = 0x09090909;                  /* SP[17] := R9 */
+	pxTopOfStack[ 18 ] = 0x10101010;                  /* SP[18] := R10 */
+	pxTopOfStack[ 19 ] = 0x11111111;                  /* SP[19] := R11 */
+	pxTopOfStack[ 20 ] = 0x00000000;                  /* SP[20] := vH and vSR */
+	memset(&pxTopOfStack[21], 0, 32);                 /* SP[21 - 28] := vR   */
+	memset(&pxTopOfStack[29], 1, 32);                 /* SP[29 - 36] := vD   */
+	memset(&pxTopOfStack[37], 2, 32);                 /* SP[37 - 44] := vC   */
+
+	//debug_printf( "Top of stack is now %p for task %p\n", pxTopOfStack, pxCode );
+
+	/*
+	 * Returns the new top of the stack
+	 */
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+void vPortStartSMPScheduler( void );
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+	if( ( configNUMBER_OF_CORES > portMAX_CORE_COUNT ) || ( configNUMBER_OF_CORES <= 0 ) )
+	{
+		return pdFAIL;
+	}
+
+	rtos_locks_initialize();
+	xKernelTimer = hwtimer_alloc();
+
+	vPortStartSMPScheduler();
+
+	return pdPASS;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Do not implement. */
+}
+/*-----------------------------------------------------------*/
diff --git a/portable/ThirdParty/xClang/XCOREAI/port.xc b/portable/ThirdParty/xClang/XCOREAI/port.xc
new file mode 100644
index 000000000..926b15086
--- /dev/null
+++ b/portable/ThirdParty/xClang/XCOREAI/port.xc
@@ -0,0 +1,26 @@
+/*
+ * port.xc
+ *
+ *  Created on: Jul 31, 2019
+ *      Author: mbruno
+ */
+
+//#include "rtos_support.h"
+
+extern "C" {
+
+#include "FreeRTOSConfig.h" /* to get configNUMBER_OF_CORES */
+#ifndef configNUMBER_OF_CORES
+#define configNUMBER_OF_CORES 1
+#endif
+
+void __xcore_interrupt_permitted_ugs_vPortStartSchedulerOnCore(void);
+
+} /* extern "C" */
+
+void vPortStartSMPScheduler( void )
+{
+    par (int i = 0; i < configNUMBER_OF_CORES; i++) {
+        __xcore_interrupt_permitted_ugs_vPortStartSchedulerOnCore();
+    }
+}
diff --git a/portable/ThirdParty/xClang/XCOREAI/portasm.S b/portable/ThirdParty/xClang/XCOREAI/portasm.S
new file mode 100644
index 000000000..7445672a0
--- /dev/null
+++ b/portable/ThirdParty/xClang/XCOREAI/portasm.S
@@ -0,0 +1,189 @@
+// Copyright (c) 2020, XMOS Ltd, All rights reserved
+
+#include "rtos_support_rtos_config.h"
+
+/* The FreeRTOS interrupt code calls vTaskSwitchContext.
+Therfore it must be added to the rtos_isr group with the
+rest of the ISR callback functions. */
+.weak _fptrgroup.rtos_isr.nstackwords.group
+.add_to_set _fptrgroup.rtos_isr.nstackwords.group, vTaskSwitchContext.nstackwords, vTaskSwitchContext
+
+.globl kexcept
+.align 128              /* align the kernel section to 128 bytes */
+.type  kexcept,@function
+.issue_mode dual
+.cc_top kexcept.function, kexcept
+kexcept:
+  ldc r11, 0x0008
+  shl r11, r11, 16
+  ldc r9, 0x0080
+  or  r11, r11, r9
+  bau r11 //_TrapHandler is at 0x00080080. TODO: Is it always? Why can't I access the symbol _TrapHandler?
+
+_yield:
+ {set    sp,     r4                  /* Restore the task's SP to save the rest of its context. */
+  get    r11,    id}                 /* Get the logical core ID into r11. */
+  ldaw   r0,     dp[rtos_core_map]
+  ldw    r0,     r0[r11]             /* Translate to the RTOS core ID into r0 */
+  bu _yield_continue                 /* Skip the ulPortYieldRequired check and jump right to */
+                                     /* the context save and switch. Also skips saving SPC */
+                                     /* since the kcall handler has already saved it. */
+
+.align 64
+kcall:
+  /* start saving the thread's context */
+  extsp RTOS_SUPPORT_INTERRUPT_STACK_GROWTH
+  stw    r1,     sp[9]
+  stw    r11,    sp[19]
+
+  /* kcall sets SPC to the instruction of the kcall rather than the next instruction */
+  /* so we need to adjust the SPC value that we save to the stack: */
+  stw    spc,    sp[1]   /* save the saved program counter onto the stack... */
+  ldw    r1,     sp[1]   /* so that we can load it into r1 (which we have already saved). */
+  add    r1,     r1,   4 /* Add 4 to the spc to make it point to the instruction after the kcall. */
+ {stw    r1,     sp[1]   /* Now save it to the stack. */
+
+  /* kcall uses the same common function as interrupt callbacks. */
+  /* tell it to call _yield above. */
+  ldap   r11,    _yield}
+  mov    r1,     r11
+
+  /* fall into rtos_interrupt_callback_common */
+
+.globl rtos_interrupt_callback_common
+rtos_interrupt_callback_common:
+  /* This is the body of the RTOS _xcore_c_interrupt_callback_XXX functions. */
+  /* r1 = interrupt_callback_t function */
+
+  /* Save the thread's context onto the thread's stack. */
+  /* The stack was extended for this by the wrapper function. */
+  /* Begin only by saving some registers. The rest will be saved */
+  /* later if vTaskSwitchContext() needs to be called. */
+  /* DP and CP need to be saved because these are restored for the kernel ISR. */
+  /* LR needs to be saved because it is clobbered when calling the callback. */
+  /* r0-r3, and r11 need to be saved because the callback may clobber them. */
+  /* r4 is saved because it is used here to hold the task SP. */
+
+  stw    dp,     sp[5]
+  stw    cp,     sp[6]
+  stw    lr,     sp[7]
+  stw    r0,     sp[8]
+/*stw    r1,     sp[9]      already saved by the wrapper function. */
+  stw    r2,     sp[10]
+  stw    r3,     sp[11]
+ {stw    r4,     sp[12]
+/*stw    r11,    sp[19]     already saved by the wrapper function. */
+
+  ldaw   r4,     sp[0]}  /* Get value of current stackpointer into r4. */
+
+ {kentsp 0               /* switch to the kernel stack. */
+                         /* The value 0 is safe to use since we don't need the SP */
+                         /* that it saves to KSP[0]. We already have it in r4. */
+
+  get    r11,    ed}     /* Get the event data... */
+  ldw    dp,     sp[3]   /* (Restore CP and DP required for the RTOS ISR */
+  ldw    cp,     sp[4]   /* in case the active thread has modified them.) */
+ {mov    r0,     r11     /* ...into the first argument for the callback function, */
+  bla    r1}             /* and call the callback function. */
+
+ {set    sp,     r4      /* Restore the task's SP now. */
+
+  get    r11,    id}                           /* Get the logical core ID into r11. */
+  ldaw   r0,     dp[rtos_core_map]
+  ldw    r0,     r0[r11]                       /* Translate to the RTOS core ID into r0. */
+  ldaw   r2,     dp[ulPortYieldRequired]       /* Get the yield required array into r2. */
+  ldw    r1,     r2[r0]                        /* Is a yield required for this core? */
+ {bf     r1,     _freertos_restore_ctx_partial /* If not, restore the context now. */
+  ldc    r1,     0}
+  stw    r1,     r2[r0]                        /* Otherwise, clear the yield required flag. */
+
+  /* Save the rest of the current task's context. */
+
+  /* Save standard xs2 regs */
+  stw    spc,    sp[1]
+_yield_continue:
+  stw    ssr,    sp[2]
+  stw    sed,    sp[3]
+  stw    et,     sp[4]
+  stw    r5,     sp[13]
+  stw    r6,     sp[14]
+  stw    r7,     sp[15]
+  stw    r8,     sp[16]
+  stw    r9,     sp[17]
+  stw    r10,    sp[18]
+#if 1
+  /* Save VPU status and headroom */
+  vgetc  r11
+ {stw    r11,    sp[20]
+  /* Save VPU regs */
+  ldaw   r11,    sp[21]}
+ {vstr   r11[0]
+  ldaw   r11,    sp[29]}
+ {vstd   r11[0]
+  ldaw   r11,    sp[37]}
+  vstc   r11[0]
+#endif
+  ldaw   r5,     dp[pxCurrentTCBs] /* Get the current TCB array into r5. */
+  ldw    r1,     r5[r0]            /* Get this core's current TCB pointer into r1. */
+  stw    r4,     r1[0x0]           /* Save the current task's SP to the first */
+                                   /* word (top of stack) in the current TCB. */
+
+ {kentsp 0                         /* switch back to the kernel stack. */
+
+  mov    r6,     r0}               /* copy the RTOS core ID into r6 so we don't lose it. */
+  ldap   r11,    vTaskSwitchContext
+  bla    r11             /* Finally call vTaskSwitchContext(core_id) now that the task's */
+                         /* entire context is saved. Note the core id in r0 is the argument. */
+
+//krestsp 0              /* unnecessary since KSP is already set and the SP */
+                         /* is being restored next from the current TCB. */
+
+.globl _freertos_restore_ctx
+_freertos_restore_ctx:
+
+  ldw    r0,     r5[r6]  /* get this core's current TCB pointer into r0 */
+  ldw    r0,     r0[0x0] /* Get the top of the stack from the current TCB... */
+  set    sp,     r0      /* into the stack pointer register. */
+
+  /* Restore the current task's context */
+#if 1
+  /* Restore VPU regs */
+  ldaw   r11,    sp[37]
+ {vldc   r11[0]
+  ldaw   r11,    sp[29]}
+ {vldd   r11[0]
+  ldaw   r11,    sp[21]}
+  vldr   r11[0]
+  /* Restore VPU status and headroom */
+  ldw    r11,    sp[20]
+  vsetc  r11
+#endif
+  /* Restore standard xs2 regs */
+  ldw    spc,    sp[1]
+  ldw    ssr,    sp[2]
+  ldw    sed,    sp[3]
+  ldw    et,     sp[4]
+  ldw    r5,     sp[13]
+  ldw    r6,     sp[14]
+  ldw    r7,     sp[15]
+  ldw    r8,     sp[16]
+  ldw    r9,     sp[17]
+  ldw    r10,    sp[18]
+_freertos_restore_ctx_partial:
+  ldw    dp,     sp[5]
+  ldw    cp,     sp[6]
+  ldw    lr,     sp[7]
+  ldw    r0,     sp[8]
+  ldw    r1,     sp[9]
+  ldw    r2,     sp[10]
+  ldw    r3,     sp[11]
+  ldw    r4,     sp[12]
+ {ldw    r11,    sp[19]
+
+  /* shrink the stack by the size of the context just restored */
+  ldaw   sp,     sp[RTOS_SUPPORT_INTERRUPT_STACK_GROWTH]}
+
+  kret                   /* exit kernel mode and return to the thread */
+
+.cc_bottom kexcept.function
+
diff --git a/portable/ThirdParty/xClang/XCOREAI/portmacro.h b/portable/ThirdParty/xClang/XCOREAI/portmacro.h
new file mode 100644
index 000000000..36907b258
--- /dev/null
+++ b/portable/ThirdParty/xClang/XCOREAI/portmacro.h
@@ -0,0 +1,215 @@
+// Copyright (c) 2020, XMOS Ltd, All rights reserved
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifndef __ASSEMBLER__
+
+/* Inclusion of xc1.h will result in clock being defined as a type.
+ * By default, FreeRTOS will require standard time.h, where clock is a function.
+ */
+#ifndef USE_XCORE_CLOCK_TYPE
+#define _clock_defined
+#endif
+
+#include <xs1.h>
+#include "rtos_support.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Type definitions. */
+#define portSTACK_TYPE	uint32_t
+typedef portSTACK_TYPE StackType_t;
+typedef double portDOUBLE;
+typedef int32_t BaseType_t;
+typedef uint32_t UBaseType_t;
+
+#define portBASE_TYPE   BaseType_t
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+#endif /* __ASSEMBLER__ */
+
+/* Architecture specifics. These can be used by assembly files as well. */
+#define portSTACK_GROWTH			  ( -1 )
+#define portTICK_PERIOD_MS			  ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			  8
+#define portCRITICAL_NESTING_IN_TCB   1
+#define portMAX_CORE_COUNT            8
+#ifndef configNUMBER_OF_CORES
+#define configNUMBER_OF_CORES         1
+#endif
+
+/* This may be set to zero in the config file if the rtos_time
+functions are not needed or if it is incremented elsewhere. */
+#ifndef configUPDATE_RTOS_TIME_FROM_TICK_ISR
+#define configUPDATE_RTOS_TIME_FROM_TICK_ISR 1
+#endif
+
+/*
+ * When entering an ISR we need to grow the stack by one more word than
+ * we actually need to save the thread context. This is because there are
+ * some functions, written in assembly *cough* memcpy() *cough*, that think
+ * it is OK to store words at SP[0]. Therefore the ISR must leave SP[0] alone
+ * even though it is normally not necessary to do so.
+ */
+#define portTHREAD_CONTEXT_STACK_GROWTH RTOS_SUPPORT_INTERRUPT_STACK_GROWTH
+
+#ifndef __ASSEMBLER__
+
+/* Check validity of number of cores specified in config */
+#if ( configNUMBER_OF_CORES < 1 || portMAX_CORE_COUNT < configNUMBER_OF_CORES )
+#error "Invalid number of cores specified in config!"
+#endif
+
+#define portMEMORY_BARRIER() RTOS_MEMORY_BARRIER()
+#define portTASK_STACK_DEPTH(pxTaskCode) RTOS_THREAD_STACK_SIZE(pxTaskCode)
+/*-----------------------------------------------------------*/
+
+/* Scheduler utilities. */
+#define portYIELD() 	asm volatile( "KCALLI_lu6 0" ::: "memory" )
+
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+do \
+{ \
+	if( xSwitchRequired != pdFALSE ) \
+	{ \
+		extern uint32_t ulPortYieldRequired[ portMAX_CORE_COUNT ]; \
+	    ulPortYieldRequired[ portGET_CORE_ID() ] = pdTRUE; \
+	} \
+} while( 0 )
+
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/* SMP utilities. */
+#define portGET_CORE_ID() rtos_core_id_get()
+
+void vPortYieldOtherCore( int xOtherCoreID );
+#define portYIELD_CORE( x ) vPortYieldOtherCore( x )
+/*-----------------------------------------------------------*/
+
+/* Architecture specific optimisations. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+    /* Store/clear the ready priorities in a bit map. */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+    /*-----------------------------------------------------------*/
+
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __builtin_clz( uxReadyPriorities ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+
+#define portGET_INTERRUPT_STATE() rtos_interrupt_mask_get()
+
+/*
+ * This differs from the standard portDISABLE_INTERRUPTS()
+ * in that it also returns what the interrupt state was
+ * before it disabling interrupts.
+ */
+#define portDISABLE_INTERRUPTS() rtos_interrupt_mask_all()
+
+#define portENABLE_INTERRUPTS() rtos_interrupt_unmask_all()
+
+/*
+ * Port set interrupt mask and clear interrupt mask.
+ */
+#define portSET_INTERRUPT_MASK()                rtos_interrupt_mask_all()
+#define portCLEAR_INTERRUPT_MASK( ulState )     rtos_interrupt_mask_set( ulState )
+
+#define portSET_INTERRUPT_MASK_FROM_ISR()       ( 0 )
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)    ( (void) x )
+
+/*
+ * Will enable interrupts if ulState is non-zero.
+ */
+#define portRESTORE_INTERRUPTS(ulState) rtos_interrupt_mask_set(ulState)
+
+/*
+ * Returns non-zero if currently running in an
+ * ISR or otherwise in kernel mode.
+ */
+#define portCHECK_IF_IN_ISR() rtos_isr_running()
+
+#define portASSERT_IF_IN_ISR() configASSERT( portCHECK_IF_IN_ISR() == 0 )
+
+#define portGET_ISR_LOCK()      rtos_lock_acquire(0)
+#define portRELEASE_ISR_LOCK()  rtos_lock_release(0)
+#define portGET_TASK_LOCK()     rtos_lock_acquire(1)
+#define portRELEASE_TASK_LOCK() rtos_lock_release(1)
+
+void vTaskEnterCritical(void);
+void vTaskExitCritical(void);
+#define portENTER_CRITICAL()                   vTaskEnterCritical()
+#define portEXIT_CRITICAL()                    vTaskExitCritical()
+
+extern UBaseType_t vTaskEnterCriticalFromISR( void );
+extern void vTaskExitCriticalFromISR( UBaseType_t uxSavedInterruptStatus );
+#define portENTER_CRITICAL_FROM_ISR             vTaskEnterCriticalFromISR
+#define portEXIT_CRITICAL_FROM_ISR              vTaskExitCriticalFromISR
+
+/*-----------------------------------------------------------*/
+
+/* Runtime stats support */
+#if ( configGENERATE_RUN_TIME_STATS == 1 )
+int xscope_gettime( void );
+#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() 	/* nothing needed here */
+#define portGET_RUN_TIME_COUNTER_VALUE()			xscope_gettime()
+#endif
+/*-----------------------------------------------------------*/
+
+/* Maps sprintf and snprintf to the lite version in lib_rtos_support */
+#if ( configUSE_DEBUG_SPRINTF == 1 )
+#define sprintf(...) rtos_sprintf(__VA_ARGS__)
+#define snprintf(...) rtos_snprintf(__VA_ARGS__)
+#endif
+
+/* Attribute for the pxCallbackFunction member of the Timer_t struct.
+Required by xcc to calculate stack usage. */
+#define portTIMER_CALLBACK_ATTRIBUTE __attribute__((fptrgroup("timerCallbackGroup")))
+
+/* Timer callback function macros. For xcc this ensures they get added to the timer callback
+group so that stack usage for certain functions in timers.c can be calculated. */
+#define portTIMER_CALLBACK_FUNCTION_PROTO( vFunction, xTimer ) void vFunction( TimerHandle_t xTimer )
+#define portTIMER_CALLBACK_FUNCTION( vFunction, xTimer ) portTIMER_CALLBACK_ATTRIBUTE void vFunction( TimerHandle_t xTimer )
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+not necessary for to use this port.  They are defined so the common demo files
+(which build with all the ports) will build. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* PORTMACRO_H */
+
diff --git a/portable/ThirdParty/xClang/XCOREAI/rtos_support_rtos_config.h b/portable/ThirdParty/xClang/XCOREAI/rtos_support_rtos_config.h
new file mode 100644
index 000000000..8b8d1054d
--- /dev/null
+++ b/portable/ThirdParty/xClang/XCOREAI/rtos_support_rtos_config.h
@@ -0,0 +1,95 @@
+// Copyright (c) 2020, XMOS Ltd, All rights reserved
+
+#ifndef RTOS_SUPPORT_RTOS_CONFIG_H_
+#define RTOS_SUPPORT_RTOS_CONFIG_H_
+
+/**
+ * Lets the application know that the RTOS in use is FreeRTOS.
+ */
+#define RTOS_FREERTOS 1
+
+/**
+ * The number of words to extend the stack by when entering an ISR.
+ *
+ * When entering an ISR we need to grow the stack by one more word than
+ * we actually need to save the thread context. This is because there are
+ * some functions, written in assembly *cough* memcpy() *cough*, that think
+ * it is OK to store words at SP[0]. Therefore the ISR must leave SP[0] alone
+ * even though it is normally not necessary to do so.
+ */
+#define RTOS_SUPPORT_INTERRUPT_STACK_GROWTH ( 44 + 1 )
+
+/**
+ * The word offset into the stack where R1 is to be stored after it
+ * is extended when saving a thread's context.
+ */
+#define RTOS_SUPPORT_INTERRUPT_R1_STACK_OFFSET 9
+
+/**
+ * The word offset into the stack where R11 is to be stored after it
+ * is extended when saving a thread's context.
+ */
+#define RTOS_SUPPORT_INTERRUPT_R11_STACK_OFFSET 19
+
+/**
+ * The RTOS provided handler that should run when a
+ * core receives an intercore interrupt request.
+ */
+#define RTOS_INTERCORE_INTERRUPT_ISR() do { \
+	void vIntercoreInterruptISR( void ); \
+	vIntercoreInterruptISR(); \
+} while ( 0 )
+
+/**
+ * The number of hardware locks that the RTOS
+ * requires. For a single core RTOS this could be
+ * zero. Locks are recursive.
+ *
+ * Note that the IRQ routines require a lock and
+ * will share the first one with the RTOS.
+ */
+#define RTOS_LOCK_COUNT 2
+
+/**
+ * Remaps all calls to debug_printf() to rtos_printf().
+ * When this is on, files should not include both rtos_support.h
+ * and debug_print.h.
+ */
+#define RTOS_DEBUG_PRINTF_REMAP 1
+
+
+#ifdef configENABLE_DEBUG_PRINTF
+	#if configENABLE_DEBUG_PRINTF
+
+		/* ensure that debug_printf is enabled */
+		#ifdef DEBUG_PRINT_ENABLE
+			#undef DEBUG_PRINT_ENABLE
+		#endif
+		#define DEBUG_PRINT_ENABLE 1
+
+		#ifndef configTASKS_DEBUG
+			#define configTASKS_DEBUG 0
+		#endif
+		#if configTASKS_DEBUG == 1
+			#define DEBUG_PRINT_ENABLE_FREERTOS_TASKS 1
+		#else
+			#define DEBUG_PRINT_DISABLE_FREERTOS_TASKS 1
+		#endif
+
+	#else /* configENABLE_DEBUG_PRINTF */
+
+		/* ensure that debug_printf is disabled */
+		#ifdef DEBUG_UNIT
+			#undef DEBUG_UNIT
+		#endif
+		#ifdef DEBUG_PRINT_ENABLE
+			#undef DEBUG_PRINT_ENABLE
+		#endif
+
+		#define DEBUG_PRINT_ENABLE 0
+
+	#endif /* configENABLE_DEBUG_PRINTF */
+#endif
+
+#endif /* RTOS_SUPPORT_RTOS_CONFIG_H_ */
+
diff --git a/queue.c b/queue.c
index 29765a54f..e87db0f45 100644
--- a/queue.c
+++ b/queue.c
@@ -89,7 +89,11 @@ typedef struct SemaphoreData
  * performed just because a higher priority task has been woken. */
     #define queueYIELD_IF_USING_PREEMPTION()
 #else
-    #define queueYIELD_IF_USING_PREEMPTION()    portYIELD_WITHIN_API()
+    #if ( configNUMBER_OF_CORES == 1 )
+        #define queueYIELD_IF_USING_PREEMPTION()    portYIELD_WITHIN_API()
+    #else /* #if ( configNUMBER_OF_CORES == 1 ) */
+        #define queueYIELD_IF_USING_PREEMPTION()    vTaskYieldWithinAPI()
+    #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
 #endif
 
 /*
@@ -1070,7 +1074,15 @@ BaseType_t xQueueGenericSend( QueueHandle_t xQueue,
                  * is also a higher priority task in the pending ready list. */
                 if( xTaskResumeAll() == pdFALSE )
                 {
-                    portYIELD_WITHIN_API();
+                    #if ( configNUMBER_OF_CORES == 1 )
+                    {
+                        portYIELD_WITHIN_API();
+                    }
+                    #else /* #if ( configNUMBER_OF_CORES == 1 ) */
+                    {
+                        vTaskYieldWithinAPI();
+                    }
+                    #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
                 }
             }
             else
@@ -1127,7 +1139,7 @@ BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue,
      * read, instead return a flag to say whether a context switch is required or
      * not (i.e. has a task with a higher priority than us been woken by this
      * post). */
-    uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+    uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
     {
         if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
         {
@@ -1252,7 +1264,7 @@ BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue,
             xReturn = errQUEUE_FULL;
         }
     }
-    portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+    taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
 
     return xReturn;
 }
@@ -1298,7 +1310,7 @@ BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue,
      * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
     portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
 
-    uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+    uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
     {
         const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
 
@@ -1418,7 +1430,7 @@ BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue,
             xReturn = errQUEUE_FULL;
         }
     }
-    portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+    taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
 
     return xReturn;
 }
@@ -1531,7 +1543,15 @@ BaseType_t xQueueReceive( QueueHandle_t xQueue,
 
                 if( xTaskResumeAll() == pdFALSE )
                 {
-                    portYIELD_WITHIN_API();
+                    #if ( configNUMBER_OF_CORES == 1 )
+                    {
+                        portYIELD_WITHIN_API();
+                    }
+                    #else /* #if ( configNUMBER_OF_CORES == 1 ) */
+                    {
+                        vTaskYieldWithinAPI();
+                    }
+                    #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
                 }
                 else
                 {
@@ -1714,7 +1734,15 @@ BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue,
 
                 if( xTaskResumeAll() == pdFALSE )
                 {
-                    portYIELD_WITHIN_API();
+                    #if ( configNUMBER_OF_CORES == 1 )
+                    {
+                        portYIELD_WITHIN_API();
+                    }
+                    #else /* #if ( configNUMBER_OF_CORES == 1 ) */
+                    {
+                        vTaskYieldWithinAPI();
+                    }
+                    #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
                 }
                 else
                 {
@@ -1892,7 +1920,15 @@ BaseType_t xQueuePeek( QueueHandle_t xQueue,
 
                 if( xTaskResumeAll() == pdFALSE )
                 {
-                    portYIELD_WITHIN_API();
+                    #if ( configNUMBER_OF_CORES == 1 )
+                    {
+                        portYIELD_WITHIN_API();
+                    }
+                    #else /* #if ( configNUMBER_OF_CORES == 1 ) */
+                    {
+                        vTaskYieldWithinAPI();
+                    }
+                    #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
                 }
                 else
                 {
@@ -1955,7 +1991,7 @@ BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue,
      * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
     portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
 
-    uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+    uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
     {
         const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
 
@@ -2015,7 +2051,7 @@ BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue,
             traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue );
         }
     }
-    portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+    taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
 
     return xReturn;
 }
@@ -2049,7 +2085,7 @@ BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue,
      * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
     portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
 
-    uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+    uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
     {
         /* Cannot block in an ISR, so check there is data available. */
         if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
@@ -2070,7 +2106,7 @@ BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue,
             traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue );
         }
     }
-    portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+    taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
 
     return xReturn;
 }
diff --git a/stream_buffer.c b/stream_buffer.c
index 30093f1af..b7410fc06 100644
--- a/stream_buffer.c
+++ b/stream_buffer.c
@@ -98,7 +98,7 @@
     do {                                                                             \
         UBaseType_t uxSavedInterruptStatus;                                          \
                                                                                      \
-        uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();                  \
+        uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();                      \
         {                                                                            \
             if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )                     \
             {                                                                        \
@@ -109,7 +109,7 @@
                 ( pxStreamBuffer )->xTaskWaitingToSend = NULL;                       \
             }                                                                        \
         }                                                                            \
-        portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );                 \
+        taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );                        \
     } while( 0 )
 #endif /* sbRECEIVE_COMPLETED_FROM_ISR */
 
@@ -175,7 +175,7 @@
     do {                                                                                \
         UBaseType_t uxSavedInterruptStatus;                                             \
                                                                                         \
-        uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();                     \
+        uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();                         \
         {                                                                               \
             if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )                     \
             {                                                                           \
@@ -186,7 +186,7 @@
                 ( pxStreamBuffer )->xTaskWaitingToReceive = NULL;                       \
             }                                                                           \
         }                                                                               \
-        portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );                    \
+        taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );                           \
     } while( 0 )
 #endif /* sbSEND_COMPLETE_FROM_ISR */
 
@@ -1220,7 +1220,7 @@ BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer
 
     configASSERT( pxStreamBuffer );
 
-    uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+    uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
     {
         if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )
         {
@@ -1236,7 +1236,7 @@ BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer
             xReturn = pdFALSE;
         }
     }
-    portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+    taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
 
     return xReturn;
 }
@@ -1251,7 +1251,7 @@ BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuf
 
     configASSERT( pxStreamBuffer );
 
-    uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+    uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
     {
         if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )
         {
@@ -1267,7 +1267,7 @@ BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuf
             xReturn = pdFALSE;
         }
     }
-    portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+    taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
 
     return xReturn;
 }
diff --git a/tasks.c b/tasks.c
index 72200ec4f..b991b7da4 100644
--- a/tasks.c
+++ b/tasks.c
@@ -58,14 +58,16 @@
     #include <stdio.h>
 #endif /* configUSE_STATS_FORMATTING_FUNCTIONS == 1 ) */
 
-#if ( configUSE_PREEMPTION == 0 )
+#if ( configNUMBER_OF_CORES == 1 )
+    #if ( configUSE_PREEMPTION == 0 )
 
 /* If the cooperative scheduler is being used then a yield should not be
  * performed just because a higher priority task has been woken. */
-    #define taskYIELD_IF_USING_PREEMPTION()
-#else
-    #define taskYIELD_IF_USING_PREEMPTION()    portYIELD_WITHIN_API()
-#endif
+        #define taskYIELD_IF_USING_PREEMPTION()
+    #else
+        #define taskYIELD_IF_USING_PREEMPTION()    portYIELD_WITHIN_API()
+    #endif
+#endif /* if ( configNUMBER_OF_CORES == 1 ) */
 
 /* Values that can be assigned to the ucNotifyState member of the TCB. */
 #define taskNOT_WAITING_NOTIFICATION              ( ( uint8_t ) 0 ) /* Must be zero as it is the initialised value. */
@@ -133,7 +135,8 @@
 
 /*-----------------------------------------------------------*/
 
-    #define taskSELECT_HIGHEST_PRIORITY_TASK()                                \
+    #if ( configNUMBER_OF_CORES == 1 )
+        #define taskSELECT_HIGHEST_PRIORITY_TASK()                            \
     do {                                                                      \
         UBaseType_t uxTopPriority = uxTopReadyPriority;                       \
                                                                               \
@@ -149,6 +152,7 @@
         listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) ); \
         uxTopReadyPriority = uxTopPriority;                                                   \
     } while( 0 ) /* taskSELECT_HIGHEST_PRIORITY_TASK */
+    #endif /* if ( configNUMBER_OF_CORES == 1 ) */
 
 /*-----------------------------------------------------------*/
 
@@ -160,6 +164,10 @@
 
 #else /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 
+    #if ( configNUMBER_OF_CORES > 1 )
+        #error configUSE_PORT_OPTIMISED_TASK_SELECTION not supported in FreeRTOS SMP.
+    #endif
+
 /* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 1 then task selection is
  * performed in a way that is tailored to the particular microcontroller
  * architecture being used. */
@@ -251,6 +259,38 @@
     #define taskEVENT_LIST_ITEM_VALUE_IN_USE    0x8000000000000000ULL
 #endif
 
+/* Task state. */
+typedef BaseType_t TaskRunning_t;
+
+/* Indicates that the task is not actively running on any core. */
+#define taskTASK_NOT_RUNNING    ( TaskRunning_t ) ( -1 )
+
+/* Indicates that the task is actively running but scheduled to yield. */
+#define taskTASK_YIELDING       ( TaskRunning_t ) ( -2 )
+
+/* Returns pdTRUE if the task is actively running and not scheduled to yield. */
+#if ( configNUMBER_OF_CORES == 1 )
+    #define taskTASK_IS_RUNNING( pxTCB )    ( ( ( pxTCB ) == pxCurrentTCB ) ? ( pdTRUE ) : ( pdFALSE ) )
+#else
+    #define taskTASK_IS_RUNNING( pxTCB )    ( ( ( ( pxTCB )->xTaskRunState >= ( BaseType_t ) 0 ) && ( ( pxTCB )->xTaskRunState < ( BaseType_t ) configNUMBER_OF_CORES ) ) ? ( pdTRUE ) : ( pdFALSE ) )
+#endif
+
+/* Indicates that the task is an Idle task. */
+#define taskATTRIBUTE_IS_IDLE    ( UBaseType_t ) ( 1UL << 0UL )
+
+#if ( ( configNUMBER_OF_CORES > 1 ) && ( portCRITICAL_NESTING_IN_TCB == 1 ) )
+    #define portGET_CRITICAL_NESTING_COUNT()          ( pxCurrentTCBs[ portGET_CORE_ID() ]->uxCriticalNesting )
+    #define portSET_CRITICAL_NESTING_COUNT( x )       ( pxCurrentTCBs[ portGET_CORE_ID() ]->uxCriticalNesting = ( x ) )
+    #define portINCREMENT_CRITICAL_NESTING_COUNT()    ( pxCurrentTCBs[ portGET_CORE_ID() ]->uxCriticalNesting++ )
+    #define portDECREMENT_CRITICAL_NESTING_COUNT()    ( pxCurrentTCBs[ portGET_CORE_ID() ]->uxCriticalNesting-- )
+#endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( portCRITICAL_NESTING_IN_TCB == 1 ) ) */
+
+/* Code below here allows infinite loop controlling, especially for the infinite loop
+ * in idle task function (for example when performing unit tests). */
+#ifndef INFINITE_LOOP
+    #define INFINITE_LOOP()    1
+#endif
+
 /*
  * Task control block.  A task control block (TCB) is allocated for each task,
  * and stores task state information, including a pointer to the task's context
@@ -264,12 +304,24 @@ typedef struct tskTaskControlBlock       /* The old naming convention is used to
         xMPU_SETTINGS xMPUSettings; /**< The MPU settings are defined as part of the port layer.  THIS MUST BE THE SECOND MEMBER OF THE TCB STRUCT. */
     #endif
 
+    #if ( configUSE_CORE_AFFINITY == 1 ) && ( configNUMBER_OF_CORES > 1 )
+        UBaseType_t uxCoreAffinityMask; /*< Used to link the task to certain cores.  UBaseType_t must have greater than or equal to the number of bits as confNUM_CORES. */
+    #endif
+
     ListItem_t xStateListItem;                  /**< The list that the state list item of a task is reference from denotes the state of that task (Ready, Blocked, Suspended ). */
     ListItem_t xEventListItem;                  /**< Used to reference a task from an event list. */
     UBaseType_t uxPriority;                     /**< The priority of the task.  0 is the lowest priority. */
     StackType_t * pxStack;                      /**< Points to the start of the stack. */
+    #if ( configNUMBER_OF_CORES > 1 )
+        volatile TaskRunning_t xTaskRunState;   /**< Used to identify the core the task is running on, if the task is running. Otherwise, identifies the task's state - not running or yielding. */
+        UBaseType_t uxTaskAttributes;           /**< Task's attributes - currently used to identify the idle tasks. */
+    #endif
     char pcTaskName[ configMAX_TASK_NAME_LEN ]; /**< Descriptive name given to the task when created.  Facilitates debugging only. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
 
+    #if ( configUSE_TASK_PREEMPTION_DISABLE == 1 )
+        BaseType_t xPreemptionDisable; /**< Used to prevent the task from being preempted. */
+    #endif
+
     #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) )
         StackType_t * pxEndOfStack; /**< Points to the highest valid address for the stack. */
     #endif
@@ -330,7 +382,15 @@ typedef tskTCB TCB_t;
 
 /*lint -save -e956 A manual analysis and inspection has been used to determine
  * which static variables must be declared volatile. */
-portDONT_DISCARD PRIVILEGED_DATA TCB_t * volatile pxCurrentTCB = NULL;
+#if ( configNUMBER_OF_CORES == 1 )
+    portDONT_DISCARD PRIVILEGED_DATA TCB_t * volatile pxCurrentTCB = NULL;
+#else
+    /* MISRA Ref 8.4.1 [Declaration shall be visible] */
+    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-84 */
+    /* coverity[misra_c_2012_rule_8_4_violation] */
+    portDONT_DISCARD PRIVILEGED_DATA TCB_t * volatile pxCurrentTCBs[ configNUMBER_OF_CORES ];
+    #define pxCurrentTCB    xTaskGetCurrentTaskHandle()
+#endif
 
 /* Lists for ready and blocked tasks. --------------------
  * xDelayedTaskList1 and xDelayedTaskList2 could be moved to function scope but
@@ -368,11 +428,11 @@ PRIVILEGED_DATA static volatile TickType_t xTickCount = ( TickType_t ) configINI
 PRIVILEGED_DATA static volatile UBaseType_t uxTopReadyPriority = tskIDLE_PRIORITY;
 PRIVILEGED_DATA static volatile BaseType_t xSchedulerRunning = pdFALSE;
 PRIVILEGED_DATA static volatile TickType_t xPendedTicks = ( TickType_t ) 0U;
-PRIVILEGED_DATA static volatile BaseType_t xYieldPending = pdFALSE;
+PRIVILEGED_DATA static volatile BaseType_t xYieldPendings[ configNUMBER_OF_CORES ] = { pdFALSE };
 PRIVILEGED_DATA static volatile BaseType_t xNumOfOverflows = ( BaseType_t ) 0;
 PRIVILEGED_DATA static UBaseType_t uxTaskNumber = ( UBaseType_t ) 0U;
 PRIVILEGED_DATA static volatile TickType_t xNextTaskUnblockTime = ( TickType_t ) 0U; /* Initialised to portMAX_DELAY before the scheduler starts. */
-PRIVILEGED_DATA static TaskHandle_t xIdleTaskHandle = NULL;                          /**< Holds the handle of the idle task.  The idle task is created automatically when the scheduler is started. */
+PRIVILEGED_DATA static TaskHandle_t xIdleTaskHandles[ configNUMBER_OF_CORES ];       /**< Holds the handles of the idle tasks.  The idle tasks are created automatically when the scheduler is started. */
 
 /* Improve support for OpenOCD. The kernel tracks Ready tasks via priority lists.
  * For tracking the state of remote threads, OpenOCD uses uxTopUsedPriority
@@ -386,24 +446,76 @@ const volatile UBaseType_t uxTopUsedPriority = configMAX_PRIORITIES - 1U;
  * moves the task's event list item into the xPendingReadyList, ready for the
  * kernel to move the task from the pending ready list into the real ready list
  * when the scheduler is unsuspended.  The pending ready list itself can only be
- * accessed from a critical section. */
+ * accessed from a critical section.
+ *
+ * Updates to uxSchedulerSuspended must be protected by both the task lock and the ISR lock
+ * and must not be done from an ISR. Reads must be protected by either lock and may be done
+ * from either an ISR or a task. */
 PRIVILEGED_DATA static volatile UBaseType_t uxSchedulerSuspended = ( UBaseType_t ) 0U;
 
 #if ( configGENERATE_RUN_TIME_STATS == 1 )
 
 /* Do not move these variables to function scope as doing so prevents the
  * code working with debuggers that need to remove the static qualifier. */
-    PRIVILEGED_DATA static configRUN_TIME_COUNTER_TYPE ulTaskSwitchedInTime = 0UL;    /**< Holds the value of a timer/counter the last time a task was switched in. */
-    PRIVILEGED_DATA static volatile configRUN_TIME_COUNTER_TYPE ulTotalRunTime = 0UL; /**< Holds the total amount of execution time as defined by the run time counter clock. */
+PRIVILEGED_DATA static configRUN_TIME_COUNTER_TYPE ulTaskSwitchedInTime[ configNUMBER_OF_CORES ] = { 0U };    /**< Holds the value of a timer/counter the last time a task was switched in. */
+PRIVILEGED_DATA static volatile configRUN_TIME_COUNTER_TYPE ulTotalRunTime[ configNUMBER_OF_CORES ] = { 0U }; /**< Holds the total amount of execution time as defined by the run time counter clock. */
 
 #endif
 
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configNUMBER_OF_CORES > 1 )
+
+/* Do not move these variables to function scope as doing so prevents the
+ * code working with debuggers that need to remove the static qualifier. */
+    static StaticTask_t xIdleTCBBuffers[ configNUMBER_OF_CORES - 1 ];
+    static StackType_t xIdleTaskStackBuffers[ configNUMBER_OF_CORES - 1 ][ configMINIMAL_STACK_SIZE ];
+
+#endif /* #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configNUMBER_OF_CORES > 1 ) */
+
 /*lint -restore */
 
 /*-----------------------------------------------------------*/
 
 /* File private functions. --------------------------------*/
 
+/*
+ * Creates the idle tasks during scheduler start.
+ */
+static BaseType_t prvCreateIdleTasks( void );
+
+#if ( configNUMBER_OF_CORES > 1 )
+
+/*
+ * Checks to see if another task moved the current task out of the ready
+ * list while it was waiting to enter a critical section and yields, if so.
+ */
+    static void prvCheckForRunStateChange( void );
+#endif /* #if ( configNUMBER_OF_CORES > 1 ) */
+
+#if ( configNUMBER_OF_CORES > 1 )
+
+/*
+ * Yields the given core.
+ */
+    static void prvYieldCore( BaseType_t xCoreID );
+#endif /* #if ( configNUMBER_OF_CORES > 1 ) */
+
+#if ( configNUMBER_OF_CORES > 1 )
+
+/*
+ * Yields a core, or cores if multiple priorities are not allowed to run
+ * simultaneously, to allow the task pxTCB to run.
+ */
+    static void prvYieldForTask( const TCB_t * pxTCB );
+#endif /* #if ( configNUMBER_OF_CORES > 1 ) */
+
+#if ( configNUMBER_OF_CORES > 1 )
+
+/*
+ * Selects the highest priority available task for the given core.
+ */
+    static void prvSelectHighestPriorityTask( BaseType_t xCoreID );
+#endif /* #if ( configNUMBER_OF_CORES > 1 ) */
+
 /**
  * Utility task that simply returns pdTRUE if the task referenced by xTask is
  * currently in the Suspended state, or pdFALSE if the task referenced by xTask
@@ -426,13 +538,21 @@ static void prvInitialiseTaskLists( void ) PRIVILEGED_FUNCTION;
  * The idle task is automatically created and added to the ready lists upon
  * creation of the first user task.
  *
+ * In the FreeRTOS SMP, configNUMBER_OF_CORES - 1 minimal idle tasks are also
+ * created to ensure that each core has an idle task to run when no other
+ * task is available to run.
+ *
  * The portTASK_FUNCTION_PROTO() macro is used to allow port/compiler specific
- * language extensions.  The equivalent prototype for this function is:
+ * language extensions.  The equivalent prototype for these functions are:
  *
  * void prvIdleTask( void *pvParameters );
+ * void prvMinimalIdleTask( void *pvParameters );
  *
  */
 static portTASK_FUNCTION_PROTO( prvIdleTask, pvParameters ) PRIVILEGED_FUNCTION;
+#if ( configNUMBER_OF_CORES > 1 )
+    static portTASK_FUNCTION_PROTO( prvMinimalIdleTask, pvParameters ) PRIVILEGED_FUNCTION;
+#endif
 
 /*
  * Utility to free all memory allocated by the scheduler to hold a TCB,
@@ -561,6 +681,471 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
 
 #endif
 
+#if ( configUSE_MINIMAL_IDLE_HOOK == 1 )
+    extern void vApplicationMinimalIdleHook( void );
+#endif /* #if ( configUSE_MINIMAL_IDLE_HOOK == 1 ) */
+
+/*-----------------------------------------------------------*/
+
+#if ( configNUMBER_OF_CORES > 1 )
+    static void prvCheckForRunStateChange( void )
+    {
+        UBaseType_t uxPrevCriticalNesting;
+        const TCB_t * pxThisTCB;
+
+        /* This should be skipped if called from an ISR. If the task on the current
+         * core is no longer running, then vTaskSwitchContext() probably should
+         * be run before returning, but we don't have a way to force that to happen
+         * from here. */
+        if( portCHECK_IF_IN_ISR() == pdFALSE )
+        {
+            /* This function is always called with interrupts disabled
+             * so this is safe. */
+            pxThisTCB = pxCurrentTCBs[ portGET_CORE_ID() ];
+
+            while( pxThisTCB->xTaskRunState == taskTASK_YIELDING )
+            {
+                /* We are only here if we just entered a critical section
+                * or if we just suspended the scheduler, and another task
+                * has requested that we yield.
+                *
+                * This is slightly complicated since we need to save and restore
+                * the suspension and critical nesting counts, as well as release
+                * and reacquire the correct locks. And then, do it all over again
+                * if our state changed again during the reacquisition. */
+                uxPrevCriticalNesting = portGET_CRITICAL_NESTING_COUNT();
+
+                if( uxPrevCriticalNesting > 0U )
+                {
+                    portSET_CRITICAL_NESTING_COUNT( 0U );
+                    portRELEASE_ISR_LOCK();
+                }
+                else
+                {
+                    /* The scheduler is suspended. uxSchedulerSuspended is updated
+                     * only when the task is not requested to yield. */
+                    mtCOVERAGE_TEST_MARKER();
+                }
+
+                portRELEASE_TASK_LOCK();
+
+                portMEMORY_BARRIER();
+                configASSERT( pxThisTCB->xTaskRunState == taskTASK_YIELDING );
+
+                portENABLE_INTERRUPTS();
+
+                /* Enabling interrupts should cause this core to immediately
+                 * service the pending interrupt and yield. If the run state is still
+                 * yielding here then that is a problem. */
+                configASSERT( pxThisTCB->xTaskRunState != taskTASK_YIELDING );
+
+                portDISABLE_INTERRUPTS();
+                portGET_TASK_LOCK();
+                portGET_ISR_LOCK();
+
+                portSET_CRITICAL_NESTING_COUNT( uxPrevCriticalNesting );
+
+                if( uxPrevCriticalNesting == 0U )
+                {
+                    portRELEASE_ISR_LOCK();
+                }
+            }
+        }
+    }
+#endif /* #if ( configNUMBER_OF_CORES > 1 ) */
+
+/*-----------------------------------------------------------*/
+
+#if ( configNUMBER_OF_CORES > 1 )
+    static void prvYieldCore( BaseType_t xCoreID )
+    {
+        /* This must be called from a critical section and xCoreID must be valid. */
+        if( ( portCHECK_IF_IN_ISR() == pdTRUE ) && ( xCoreID == portGET_CORE_ID() ) )
+        {
+            xYieldPendings[ xCoreID ] = pdTRUE;
+        }
+        else
+        {
+            if( pxCurrentTCBs[ xCoreID ]->xTaskRunState != taskTASK_YIELDING )
+            {
+                if( xCoreID == portGET_CORE_ID() )
+                {
+                    xYieldPendings[ xCoreID ] = pdTRUE;
+                }
+                else
+                {
+                    portYIELD_CORE( xCoreID );
+                    pxCurrentTCBs[ xCoreID ]->xTaskRunState = taskTASK_YIELDING;
+                }
+            }
+        }
+    }
+#endif /* #if ( configNUMBER_OF_CORES > 1 ) */
+/*-----------------------------------------------------------*/
+
+#if ( configNUMBER_OF_CORES > 1 )
+    static void prvYieldForTask( const TCB_t * pxTCB )
+    {
+        BaseType_t xLowestPriorityToPreempt;
+        BaseType_t xCurrentCoreTaskPriority;
+        BaseType_t xLowestPriorityCore = ( BaseType_t ) -1;
+        BaseType_t xCoreID;
+
+        #if ( configRUN_MULTIPLE_PRIORITIES == 0 )
+            BaseType_t xYieldCount = 0;
+        #endif /* #if ( configRUN_MULTIPLE_PRIORITIES == 0 ) */
+
+        /* This must be called from a critical section. */
+        configASSERT( portGET_CRITICAL_NESTING_COUNT() > 0U );
+
+        #if ( configRUN_MULTIPLE_PRIORITIES == 0 )
+
+            /* No task should yield for this one if it is a lower priority
+             * than priority level of currently ready tasks. */
+            if( pxTCB->uxPriority >= uxTopReadyPriority )
+        #else
+            /* Yield is not required for a task which is already running. */
+            if( taskTASK_IS_RUNNING( pxTCB ) == pdFALSE )
+        #endif
+        {
+            xLowestPriorityToPreempt = ( BaseType_t ) pxTCB->uxPriority;
+
+            /* xLowestPriorityToPreempt will be decremented to -1 if the priority of pxTCB
+             * is 0. This is ok as we will give system idle tasks a priority of -1 below. */
+            --xLowestPriorityToPreempt;
+
+            for( xCoreID = ( BaseType_t ) 0; xCoreID < ( BaseType_t ) configNUMBER_OF_CORES; xCoreID++ )
+            {
+                xCurrentCoreTaskPriority = ( BaseType_t ) pxCurrentTCBs[ xCoreID ]->uxPriority;
+
+                /* System idle tasks are being assigned a priority of tskIDLE_PRIORITY - 1 here. */
+                if( ( pxCurrentTCBs[ xCoreID ]->uxTaskAttributes & taskATTRIBUTE_IS_IDLE ) != 0U )
+                {
+                    xCurrentCoreTaskPriority = xCurrentCoreTaskPriority - 1;
+                }
+
+                if( ( taskTASK_IS_RUNNING( pxCurrentTCBs[ xCoreID ] ) != pdFALSE ) && ( xYieldPendings[ xCoreID ] == pdFALSE ) )
+                {
+                    #if ( configRUN_MULTIPLE_PRIORITIES == 0 )
+                        if( taskTASK_IS_RUNNING( pxTCB ) == pdFALSE )
+                    #endif
+                    {
+                        if( xCurrentCoreTaskPriority <= xLowestPriorityToPreempt )
+                        {
+                            #if ( configUSE_CORE_AFFINITY == 1 )
+                                if( ( pxTCB->uxCoreAffinityMask & ( ( UBaseType_t ) 1U << ( UBaseType_t ) xCoreID ) ) != 0U )
+                            #endif
+                            {
+                                #if ( configUSE_TASK_PREEMPTION_DISABLE == 1 )
+                                    if( pxCurrentTCBs[ xCoreID ]->xPreemptionDisable == pdFALSE )
+                                #endif
+                                {
+                                    xLowestPriorityToPreempt = xCurrentCoreTaskPriority;
+                                    xLowestPriorityCore = xCoreID;
+                                }
+                            }
+                        }
+                        else
+                        {
+                            mtCOVERAGE_TEST_MARKER();
+                        }
+                    }
+
+                    #if ( configRUN_MULTIPLE_PRIORITIES == 0 )
+                    {
+                        /* Yield all currently running non-idle tasks with a priority lower than
+                         * the task that needs to run. */
+                        if( ( xCurrentCoreTaskPriority > ( ( BaseType_t ) tskIDLE_PRIORITY - 1 ) ) &&
+                            ( xCurrentCoreTaskPriority < ( BaseType_t ) pxTCB->uxPriority ) )
+                        {
+                            prvYieldCore( xCoreID );
+                            xYieldCount++;
+                        }
+                        else
+                        {
+                            mtCOVERAGE_TEST_MARKER();
+                        }
+                    }
+                    #endif /* #if ( configRUN_MULTIPLE_PRIORITIES == 0 ) */
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+
+            #if ( configRUN_MULTIPLE_PRIORITIES == 0 )
+                if( ( xYieldCount == 0 ) && ( xLowestPriorityCore >= 0 ) )
+            #else /* #if ( configRUN_MULTIPLE_PRIORITIES == 0 ) */
+                if( xLowestPriorityCore >= 0 )
+            #endif /* #if ( configRUN_MULTIPLE_PRIORITIES == 0 ) */
+            {
+                prvYieldCore( xLowestPriorityCore );
+            }
+
+            #if ( configRUN_MULTIPLE_PRIORITIES == 0 )
+                /* Verify that the calling core always yields to higher priority tasks. */
+                if( ( ( pxCurrentTCBs[ portGET_CORE_ID() ]->uxTaskAttributes & taskATTRIBUTE_IS_IDLE ) == 0 ) &&
+                    ( pxTCB->uxPriority > pxCurrentTCBs[ portGET_CORE_ID() ]->uxPriority ) )
+                {
+                    configASSERT( ( xYieldPendings[ portGET_CORE_ID() ] == pdTRUE ) ||
+                                  ( taskTASK_IS_RUNNING( pxCurrentTCBs[ portGET_CORE_ID() ] ) == pdFALSE ) );
+                }
+            #endif
+        }
+    }
+#endif /* #if ( configNUMBER_OF_CORES > 1 ) */
+/*-----------------------------------------------------------*/
+
+#if ( configNUMBER_OF_CORES > 1 )
+    static void prvSelectHighestPriorityTask( BaseType_t xCoreID )
+    {
+        UBaseType_t uxCurrentPriority = uxTopReadyPriority;
+        BaseType_t xTaskScheduled = pdFALSE;
+        BaseType_t xDecrementTopPriority = pdTRUE;
+
+        #if ( configUSE_CORE_AFFINITY == 1 )
+            const TCB_t * pxPreviousTCB = NULL;
+        #endif
+        #if ( configRUN_MULTIPLE_PRIORITIES == 0 )
+            BaseType_t xPriorityDropped = pdFALSE;
+        #endif
+
+        /* This function should be called when scheduler is running. */
+        configASSERT( xSchedulerRunning == pdTRUE );
+
+        /* A new task is created and a running task with the same priority yields
+         * itself to run the new task. When a running task yields itself, it is still
+         * in the ready list. This running task will be selected before the new task
+         * since the new task is always added to the end of the ready list.
+         * The other problem is that the running task still in the same position of
+         * the ready list when it yields itself. It is possible that it will be selected
+         * earlier then other tasks which waits longer than this task.
+         *
+         * To fix these problems, the running task should be put to the end of the
+         * ready list before searching for the ready task in the ready list. */
+        if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxCurrentTCBs[ xCoreID ]->uxPriority ] ),
+                                     &pxCurrentTCBs[ xCoreID ]->xStateListItem ) == pdTRUE )
+        {
+            ( void ) uxListRemove( &pxCurrentTCBs[ xCoreID ]->xStateListItem );
+            vListInsertEnd( &( pxReadyTasksLists[ pxCurrentTCBs[ xCoreID ]->uxPriority ] ),
+                            &pxCurrentTCBs[ xCoreID ]->xStateListItem );
+        }
+
+        while( xTaskScheduled == pdFALSE )
+        {
+            #if ( configRUN_MULTIPLE_PRIORITIES == 0 )
+            {
+                if( uxCurrentPriority < uxTopReadyPriority )
+                {
+                    /* We can't schedule any tasks, other than idle, that have a
+                     * priority lower than the priority of a task currently running
+                     * on another core. */
+                    uxCurrentPriority = tskIDLE_PRIORITY;
+                }
+            }
+            #endif
+
+            if( listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxCurrentPriority ] ) ) == pdFALSE )
+            {
+                const List_t * const pxReadyList = &( pxReadyTasksLists[ uxCurrentPriority ] );
+                const ListItem_t * pxEndMarker = listGET_END_MARKER( pxReadyList );
+                ListItem_t * pxIterator;
+
+                /* The ready task list for uxCurrentPriority is not empty, so uxTopReadyPriority
+                 * must not be decremented any further. */
+                xDecrementTopPriority = pdFALSE;
+
+                for( pxIterator = listGET_HEAD_ENTRY( pxReadyList ); pxIterator != pxEndMarker; pxIterator = listGET_NEXT( pxIterator ) )
+                {
+                    TCB_t * pxTCB = ( TCB_t * ) listGET_LIST_ITEM_OWNER( pxIterator );
+
+                    #if ( configRUN_MULTIPLE_PRIORITIES == 0 )
+                    {
+                        /* When falling back to the idle priority because only one priority
+                         * level is allowed to run at a time, we should ONLY schedule the true
+                         * idle tasks, not user tasks at the idle priority. */
+                        if( uxCurrentPriority < uxTopReadyPriority )
+                        {
+                            if( ( pxTCB->uxTaskAttributes & taskATTRIBUTE_IS_IDLE ) == 0 )
+                            {
+                                continue;
+                            }
+                        }
+                    }
+                    #endif /* #if ( configRUN_MULTIPLE_PRIORITIES == 0 ) */
+
+                    if( pxTCB->xTaskRunState == taskTASK_NOT_RUNNING )
+                    {
+                        #if ( configUSE_CORE_AFFINITY == 1 )
+                            if( ( pxTCB->uxCoreAffinityMask & ( ( UBaseType_t ) 1U << ( UBaseType_t ) xCoreID ) ) != 0U )
+                        #endif
+                        {
+                            /* If the task is not being executed by any core swap it in. */
+                            pxCurrentTCBs[ xCoreID ]->xTaskRunState = taskTASK_NOT_RUNNING;
+                            #if ( configUSE_CORE_AFFINITY == 1 )
+                                pxPreviousTCB = pxCurrentTCBs[ xCoreID ];
+                            #endif
+                            pxTCB->xTaskRunState = ( TaskRunning_t ) xCoreID;
+                            pxCurrentTCBs[ xCoreID ] = pxTCB;
+                            xTaskScheduled = pdTRUE;
+                        }
+                    }
+                    else if( pxTCB == pxCurrentTCBs[ xCoreID ] )
+                    {
+                        configASSERT( ( pxTCB->xTaskRunState == xCoreID ) || ( pxTCB->xTaskRunState == taskTASK_YIELDING ) );
+
+                        #if ( configUSE_CORE_AFFINITY == 1 )
+                            if( ( pxTCB->uxCoreAffinityMask & ( ( UBaseType_t ) 1U << ( UBaseType_t ) xCoreID ) ) != 0U )
+                        #endif
+                        {
+                            /* The task is already running on this core, mark it as scheduled. */
+                            pxTCB->xTaskRunState = ( TaskRunning_t ) xCoreID;
+                            xTaskScheduled = pdTRUE;
+                        }
+                    }
+                    else
+                    {
+                        /* This task is running on the core other than xCoreID. */
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+
+                    if( xTaskScheduled != pdFALSE )
+                    {
+                        /* A task has been selected to run on this core. */
+                        break;
+                    }
+                }
+            }
+            else
+            {
+                if( xDecrementTopPriority != pdFALSE )
+                {
+                    uxTopReadyPriority--;
+                    #if ( configRUN_MULTIPLE_PRIORITIES == 0 )
+                    {
+                        xPriorityDropped = pdTRUE;
+                    }
+                    #endif
+                }
+            }
+
+            /* There are configNUMBER_OF_CORES Idle tasks created when scheduler started.
+             * The scheduler should be able to select a task to run when uxCurrentPriority
+             * is tskIDLE_PRIORITY. uxCurrentPriority is never decreased to value blow
+             * tskIDLE_PRIORITY. */
+            if( uxCurrentPriority > tskIDLE_PRIORITY )
+            {
+                uxCurrentPriority--;
+            }
+            else
+            {
+                /* This function is called when idle task is not created. Break the
+                 * loop to prevent uxCurrentPriority overrun. */
+                break;
+            }
+        }
+
+        #if ( configRUN_MULTIPLE_PRIORITIES == 0 )
+        {
+            if( xTaskScheduled == pdTRUE )
+            {
+                if( xPriorityDropped != pdFALSE )
+                {
+                    /* There may be several ready tasks that were being prevented from running because there was
+                     * a higher priority task running. Now that the last of the higher priority tasks is no longer
+                     * running, make sure all the other idle tasks yield. */
+                    BaseType_t x;
+
+                    for( x = ( BaseType_t ) 0; x < ( BaseType_t ) configNUMBER_OF_CORES; x++ )
+                    {
+                        if( ( pxCurrentTCBs[ x ]->uxTaskAttributes & taskATTRIBUTE_IS_IDLE ) != 0 )
+                        {
+                            prvYieldCore( x );
+                        }
+                    }
+                }
+            }
+        }
+        #endif /* #if ( configRUN_MULTIPLE_PRIORITIES == 0 ) */
+
+        #if ( configUSE_CORE_AFFINITY == 1 )
+        {
+            if( xTaskScheduled == pdTRUE )
+            {
+                if( ( pxPreviousTCB != NULL ) && ( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxPreviousTCB->uxPriority ] ), &( pxPreviousTCB->xStateListItem ) ) != pdFALSE ) )
+                {
+                    /* A ready task was just evicted from this core. See if it can be
+                     * scheduled on any other core. */
+                    UBaseType_t uxCoreMap = pxPreviousTCB->uxCoreAffinityMask;
+                    BaseType_t xLowestPriority = ( BaseType_t ) pxPreviousTCB->uxPriority;
+                    BaseType_t xLowestPriorityCore = -1;
+                    BaseType_t x;
+
+                    if( ( pxPreviousTCB->uxTaskAttributes & taskATTRIBUTE_IS_IDLE ) != 0U )
+                    {
+                        xLowestPriority = xLowestPriority - 1;
+                    }
+
+                    if( ( uxCoreMap & ( ( UBaseType_t ) 1U << ( UBaseType_t ) xCoreID ) ) != 0U )
+                    {
+                        /* The ready task that was removed from this core is not excluded from it.
+                         * Only look at the intersection of the cores the removed task is allowed to run
+                         * on with the cores that the new task is excluded from. It is possible that the
+                         * new task was only placed onto this core because it is excluded from another.
+                         * Check to see if the previous task could run on one of those cores. */
+                        uxCoreMap &= ~( pxCurrentTCBs[ xCoreID ]->uxCoreAffinityMask );
+                    }
+                    else
+                    {
+                        /* The ready task that was removed from this core is excluded from it. */
+                    }
+
+                    uxCoreMap &= ( ( 1U << configNUMBER_OF_CORES ) - 1U );
+
+                    for( x = ( ( BaseType_t ) configNUMBER_OF_CORES - 1 ); x >= ( BaseType_t ) 0; x-- )
+                    {
+                        UBaseType_t uxCore = ( UBaseType_t ) x;
+                        BaseType_t xTaskPriority;
+
+                        if( ( uxCoreMap & ( ( UBaseType_t ) 1U << uxCore ) ) != 0U )
+                        {
+                            xTaskPriority = ( BaseType_t ) pxCurrentTCBs[ uxCore ]->uxPriority;
+
+                            if( ( pxCurrentTCBs[ uxCore ]->uxTaskAttributes & taskATTRIBUTE_IS_IDLE ) != 0U )
+                            {
+                                xTaskPriority = xTaskPriority - ( BaseType_t ) 1;
+                            }
+
+                            uxCoreMap &= ~( ( UBaseType_t ) 1U << uxCore );
+
+                            if( ( xTaskPriority < xLowestPriority ) &&
+                                ( taskTASK_IS_RUNNING( pxCurrentTCBs[ uxCore ] ) != pdFALSE ) &&
+                                ( xYieldPendings[ uxCore ] == pdFALSE ) )
+                            {
+                                #if ( configUSE_TASK_PREEMPTION_DISABLE == 1 )
+                                    if( pxCurrentTCBs[ uxCore ]->xPreemptionDisable == pdFALSE )
+                                #endif
+                                {
+                                    xLowestPriority = xTaskPriority;
+                                    xLowestPriorityCore = ( BaseType_t ) uxCore;
+                                }
+                            }
+                        }
+                    }
+
+                    if( xLowestPriorityCore >= 0 )
+                    {
+                        prvYieldCore( xLowestPriorityCore );
+                    }
+                }
+            }
+        }
+        #endif /* #if ( configUSE_CORE_AFFINITY == 1 ) */
+    }
+
+#endif /* ( configNUMBER_OF_CORES > 1 ) */
+
 /*-----------------------------------------------------------*/
 
 #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
@@ -572,6 +1157,20 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
                                     UBaseType_t uxPriority,
                                     StackType_t * const puxStackBuffer,
                                     StaticTask_t * const pxTaskBuffer )
+    #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
+    {
+        return xTaskCreateStaticAffinitySet( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer, tskNO_AFFINITY );
+    }
+
+    TaskHandle_t xTaskCreateStaticAffinitySet( TaskFunction_t pxTaskCode,
+                                               const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+                                               const uint32_t ulStackDepth,
+                                               void * const pvParameters,
+                                               UBaseType_t uxPriority,
+                                               StackType_t * const puxStackBuffer,
+                                               StaticTask_t * const pxTaskBuffer,
+                                               UBaseType_t uxCoreAffinityMask )
+    #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */
     {
         TCB_t * pxNewTCB;
         TaskHandle_t xReturn;
@@ -595,7 +1194,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
             /* The memory used for the task's TCB and stack are passed into this
              * function - use them. */
             pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
-            memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) );
+            ( void ) memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) );
             pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer;
 
             #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
@@ -607,6 +1206,14 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
             #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
 
             prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL );
+
+            #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
+            {
+                /* Set the task's affinity before scheduling it. */
+                pxNewTCB->uxCoreAffinityMask = uxCoreAffinityMask;
+            }
+            #endif
+
             prvAddNewTaskToReadyList( pxNewTCB );
         }
         else
@@ -624,6 +1231,15 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
 
     BaseType_t xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition,
                                             TaskHandle_t * pxCreatedTask )
+    #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
+    {
+        return xTaskCreateRestrictedStaticAffinitySet( pxTaskDefinition, tskNO_AFFINITY, pxCreatedTask );
+    }
+
+    BaseType_t xTaskCreateRestrictedStaticAffinitySet( const TaskParameters_t * const pxTaskDefinition,
+                                                       UBaseType_t uxCoreAffinityMask,
+                                                       TaskHandle_t * pxCreatedTask )
+    #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */
     {
         TCB_t * pxNewTCB;
         BaseType_t xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
@@ -637,7 +1253,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
              * on the implementation of the port malloc function and whether or
              * not static allocation is being used. */
             pxNewTCB = ( TCB_t * ) pxTaskDefinition->pxTaskBuffer;
-            memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) );
+            ( void ) memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) );
 
             /* Store the stack location in the TCB. */
             pxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer;
@@ -658,6 +1274,13 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
                                   pxCreatedTask, pxNewTCB,
                                   pxTaskDefinition->xRegions );
 
+            #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
+            {
+                /* Set the task's affinity before scheduling it. */
+                pxNewTCB->uxCoreAffinityMask = uxCoreAffinityMask;
+            }
+            #endif
+
             prvAddNewTaskToReadyList( pxNewTCB );
             xReturn = pdPASS;
         }
@@ -672,6 +1295,15 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
 
     BaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition,
                                       TaskHandle_t * pxCreatedTask )
+    #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
+    {
+        return xTaskCreateRestrictedAffinitySet( pxTaskDefinition, tskNO_AFFINITY, pxCreatedTask );
+    }
+
+    BaseType_t xTaskCreateRestrictedAffinitySet( const TaskParameters_t * const pxTaskDefinition,
+                                                 UBaseType_t uxCoreAffinityMask,
+                                                 TaskHandle_t * pxCreatedTask )
+    #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */
     {
         TCB_t * pxNewTCB;
         BaseType_t xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
@@ -680,14 +1312,11 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
 
         if( pxTaskDefinition->puxStackBuffer != NULL )
         {
-            /* Allocate space for the TCB.  Where the memory comes from depends
-             * on the implementation of the port malloc function and whether or
-             * not static allocation is being used. */
             pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) );
 
             if( pxNewTCB != NULL )
             {
-                memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) );
+                ( void ) memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) );
 
                 /* Store the stack location in the TCB. */
                 pxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer;
@@ -709,6 +1338,13 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
                                       pxCreatedTask, pxNewTCB,
                                       pxTaskDefinition->xRegions );
 
+                #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
+                {
+                    /* Set the task's affinity before scheduling it. */
+                    pxNewTCB->uxCoreAffinityMask = uxCoreAffinityMask;
+                }
+                #endif
+
                 prvAddNewTaskToReadyList( pxNewTCB );
                 xReturn = pdPASS;
             }
@@ -728,6 +1364,19 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
                             void * const pvParameters,
                             UBaseType_t uxPriority,
                             TaskHandle_t * const pxCreatedTask )
+    #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
+    {
+        return xTaskCreateAffinitySet( pxTaskCode, pcName, usStackDepth, pvParameters, uxPriority, tskNO_AFFINITY, pxCreatedTask );
+    }
+
+    BaseType_t xTaskCreateAffinitySet( TaskFunction_t pxTaskCode,
+                                       const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+                                       const configSTACK_DEPTH_TYPE usStackDepth,
+                                       void * const pvParameters,
+                                       UBaseType_t uxPriority,
+                                       UBaseType_t uxCoreAffinityMask,
+                                       TaskHandle_t * const pxCreatedTask )
+    #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */
     {
         TCB_t * pxNewTCB;
         BaseType_t xReturn;
@@ -744,7 +1393,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
 
             if( pxNewTCB != NULL )
             {
-                memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) );
+                ( void ) memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) );
 
                 /* Allocate space for the stack used by the task being created.
                  * The base of the stack memory stored in the TCB so the task can
@@ -773,7 +1422,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
 
                 if( pxNewTCB != NULL )
                 {
-                    memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) );
+                    ( void ) memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) );
 
                     /* Store the stack location in the TCB. */
                     pxNewTCB->pxStack = pxStack;
@@ -803,6 +1452,14 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
             #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
 
             prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL );
+
+            #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
+            {
+                /* Set the task's affinity before scheduling it. */
+                pxNewTCB->uxCoreAffinityMask = uxCoreAffinityMask;
+            }
+            #endif
+
             prvAddNewTaskToReadyList( pxNewTCB );
             xReturn = pdPASS;
         }
@@ -962,6 +1619,18 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
     }
     #endif
 
+    #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
+    {
+        pxNewTCB->uxCoreAffinityMask = tskNO_AFFINITY;
+    }
+    #endif
+
+    #if ( configUSE_TASK_PREEMPTION_DISABLE == 1 )
+    {
+        pxNewTCB->xPreemptionDisable = 0;
+    }
+    #endif
+
     /* Initialize the TCB stack to look as if the task was already running,
      * but had been interrupted by the scheduler.  The return address is set
      * to the start of the task function. Once the stack has been initialised
@@ -1014,6 +1683,19 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
     }
     #endif /* portUSING_MPU_WRAPPERS */
 
+    /* Initialize task state and task attributes. */
+    #if ( configNUMBER_OF_CORES > 1 )
+    {
+        pxNewTCB->xTaskRunState = taskTASK_NOT_RUNNING;
+
+        /* Is this an idle task? */
+        if( ( ( TaskFunction_t ) pxTaskCode == ( TaskFunction_t ) prvIdleTask ) || ( ( TaskFunction_t ) pxTaskCode == ( TaskFunction_t ) prvMinimalIdleTask ) )
+        {
+            pxNewTCB->uxTaskAttributes |= taskATTRIBUTE_IS_IDLE;
+        }
+    }
+    #endif /* #if ( configNUMBER_OF_CORES > 1 ) */
+
     if( pxCreatedTask != NULL )
     {
         /* Pass the handle out in an anonymous way.  The handle can be used to
@@ -1027,42 +1709,28 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
 }
 /*-----------------------------------------------------------*/
 
-static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB )
-{
-    /* Ensure interrupts don't access the task lists while the lists are being
-     * updated. */
-    taskENTER_CRITICAL();
+#if ( configNUMBER_OF_CORES == 1 )
+
+    static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB )
     {
-        uxCurrentNumberOfTasks++;
-
-        if( pxCurrentTCB == NULL )
+        /* Ensure interrupts don't access the task lists while the lists are being
+         * updated. */
+        taskENTER_CRITICAL();
         {
-            /* There are no other tasks, or all the other tasks are in
-             * the suspended state - make this the current task. */
-            pxCurrentTCB = pxNewTCB;
+            uxCurrentNumberOfTasks++;
 
-            if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 )
+            if( pxCurrentTCB == NULL )
             {
-                /* This is the first task to be created so do the preliminary
-                 * initialisation required.  We will not recover if this call
-                 * fails, but we will report the failure. */
-                prvInitialiseTaskLists();
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
-        }
-        else
-        {
-            /* If the scheduler is not already running, make this task the
-             * current task if it is the highest priority task to be created
-             * so far. */
-            if( xSchedulerRunning == pdFALSE )
-            {
-                if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority )
+                /* There are no other tasks, or all the other tasks are in
+                 * the suspended state - make this the current task. */
+                pxCurrentTCB = pxNewTCB;
+
+                if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 )
                 {
-                    pxCurrentTCB = pxNewTCB;
+                    /* This is the first task to be created so do the preliminary
+                     * initialisation required.  We will not recover if this call
+                     * fails, but we will report the failure. */
+                    prvInitialiseTaskLists();
                 }
                 else
                 {
@@ -1070,45 +1738,143 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB )
                 }
             }
             else
+            {
+                /* If the scheduler is not already running, make this task the
+                 * current task if it is the highest priority task to be created
+                 * so far. */
+                if( xSchedulerRunning == pdFALSE )
+                {
+                    if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority )
+                    {
+                        pxCurrentTCB = pxNewTCB;
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+
+            uxTaskNumber++;
+
+            #if ( configUSE_TRACE_FACILITY == 1 )
+            {
+                /* Add a counter into the TCB for tracing only. */
+                pxNewTCB->uxTCBNumber = uxTaskNumber;
+            }
+            #endif /* configUSE_TRACE_FACILITY */
+            traceTASK_CREATE( pxNewTCB );
+
+            prvAddTaskToReadyList( pxNewTCB );
+
+            portSETUP_TCB( pxNewTCB );
+        }
+        taskEXIT_CRITICAL();
+
+        if( xSchedulerRunning != pdFALSE )
+        {
+            /* If the created task is of a higher priority than the current task
+             * then it should run now. */
+            if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority )
+            {
+                taskYIELD_IF_USING_PREEMPTION();
+            }
+            else
             {
                 mtCOVERAGE_TEST_MARKER();
             }
         }
-
-        uxTaskNumber++;
-
-        #if ( configUSE_TRACE_FACILITY == 1 )
-        {
-            /* Add a counter into the TCB for tracing only. */
-            pxNewTCB->uxTCBNumber = uxTaskNumber;
-        }
-        #endif /* configUSE_TRACE_FACILITY */
-        traceTASK_CREATE( pxNewTCB );
-
-        prvAddTaskToReadyList( pxNewTCB );
-
-        portSETUP_TCB( pxNewTCB );
-    }
-    taskEXIT_CRITICAL();
-
-    if( xSchedulerRunning != pdFALSE )
-    {
-        /* If the created task is of a higher priority than the current task
-         * then it should run now. */
-        if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority )
-        {
-            taskYIELD_IF_USING_PREEMPTION();
-        }
         else
         {
             mtCOVERAGE_TEST_MARKER();
         }
     }
-    else
+
+#else /* #if ( configNUMBER_OF_CORES == 1 ) */
+
+    static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB )
     {
-        mtCOVERAGE_TEST_MARKER();
+        /* Ensure interrupts don't access the task lists while the lists are being
+         * updated. */
+        taskENTER_CRITICAL();
+        {
+            uxCurrentNumberOfTasks++;
+
+            if( xSchedulerRunning == pdFALSE )
+            {
+                if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 )
+                {
+                    /* This is the first task to be created so do the preliminary
+                     * initialisation required.  We will not recover if this call
+                     * fails, but we will report the failure. */
+                    prvInitialiseTaskLists();
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+
+                if( ( pxNewTCB->uxTaskAttributes & taskATTRIBUTE_IS_IDLE ) != 0U )
+                {
+                    BaseType_t xCoreID;
+
+                    /* Check if a core is free. */
+                    for( xCoreID = ( BaseType_t ) 0; xCoreID < ( BaseType_t ) configNUMBER_OF_CORES; xCoreID++ )
+                    {
+                        if( pxCurrentTCBs[ xCoreID ] == NULL )
+                        {
+                            pxNewTCB->xTaskRunState = xCoreID;
+                            pxCurrentTCBs[ xCoreID ] = pxNewTCB;
+                            break;
+                        }
+                        else
+                        {
+                            mtCOVERAGE_TEST_MARKER();
+                        }
+                    }
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+
+            uxTaskNumber++;
+
+            #if ( configUSE_TRACE_FACILITY == 1 )
+            {
+                /* Add a counter into the TCB for tracing only. */
+                pxNewTCB->uxTCBNumber = uxTaskNumber;
+            }
+            #endif /* configUSE_TRACE_FACILITY */
+            traceTASK_CREATE( pxNewTCB );
+
+            prvAddTaskToReadyList( pxNewTCB );
+
+            portSETUP_TCB( pxNewTCB );
+
+            if( xSchedulerRunning != pdFALSE )
+            {
+                /* If the created task is of a higher priority than another
+                 * currently running task and preemption is on then it should
+                 * run now. */
+                #if ( configUSE_PREEMPTION == 1 )
+                    prvYieldForTask( pxNewTCB );
+                #endif
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        taskEXIT_CRITICAL();
     }
-}
+
+#endif /* #if ( configNUMBER_OF_CORES == 1 ) */
 /*-----------------------------------------------------------*/
 
 #if ( INCLUDE_vTaskDelete == 1 )
@@ -1149,9 +1915,16 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB )
              * not return. */
             uxTaskNumber++;
 
-            if( pxTCB == pxCurrentTCB )
+            /* If the task is running (or yielding), we must add it to the
+             * termination list so that an idle task can delete it when it is
+             * no longer running. */
+            #if ( configNUMBER_OF_CORES == 1 )
+                if( pxTCB == pxCurrentTCB )
+            #else
+                if( pxTCB->xTaskRunState != taskTASK_NOT_RUNNING )
+            #endif
             {
-                /* A task is deleting itself.  This cannot complete within the
+                /* A running task is being deleted.  This cannot complete within the
                  * task itself, as a context switch to another task is required.
                  * Place the task in the termination list.  The idle task will
                  * check the termination list and free up any memory allocated by
@@ -1172,7 +1945,11 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB )
                  * after which it is not possible to yield away from this task -
                  * hence xYieldPending is used to latch that a context switch is
                  * required. */
-                portPRE_TASK_DELETE_HOOK( pxTCB, &xYieldPending );
+                #if ( configNUMBER_OF_CORES == 1 )
+                    portPRE_TASK_DELETE_HOOK( pxTCB, &xYieldPendings[ 0 ] );
+                #else
+                    portPRE_TASK_DELETE_HOOK( pxTCB, &xYieldPendings[ pxTCB->xTaskRunState ] );
+                #endif
             }
             else
             {
@@ -1184,30 +1961,61 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB )
                 prvResetNextTaskUnblockTime();
             }
         }
-        taskEXIT_CRITICAL();
 
-        /* If the task is not deleting itself, call prvDeleteTCB from outside of
-         * critical section. If a task deletes itself, prvDeleteTCB is called
-         * from prvCheckTasksWaitingTermination which is called from Idle task. */
-        if( pxTCB != pxCurrentTCB )
+        #if ( configNUMBER_OF_CORES == 1 )
         {
-            prvDeleteTCB( pxTCB );
-        }
+            taskEXIT_CRITICAL();
 
-        /* Force a reschedule if it is the currently running task that has just
-         * been deleted. */
-        if( xSchedulerRunning != pdFALSE )
-        {
-            if( pxTCB == pxCurrentTCB )
+            /* If the task is not deleting itself, call prvDeleteTCB from outside of
+             * critical section. If a task deletes itself, prvDeleteTCB is called
+             * from prvCheckTasksWaitingTermination which is called from Idle task. */
+            if( pxTCB != pxCurrentTCB )
             {
-                configASSERT( uxSchedulerSuspended == ( UBaseType_t ) 0U );
-                portYIELD_WITHIN_API();
+                prvDeleteTCB( pxTCB );
             }
-            else
+
+            /* Force a reschedule if it is the currently running task that has just
+             * been deleted. */
+            if( xSchedulerRunning != pdFALSE )
             {
-                mtCOVERAGE_TEST_MARKER();
+                if( pxTCB == pxCurrentTCB )
+                {
+                    configASSERT( uxSchedulerSuspended == 0 );
+                    portYIELD_WITHIN_API();
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
             }
         }
+        #else /* #if ( configNUMBER_OF_CORES == 1 ) */
+        {
+            /* If a running task is not deleting itself, call prvDeleteTCB. If a running
+             * task deletes itself, prvDeleteTCB is called from prvCheckTasksWaitingTermination
+             * which is called from Idle task. */
+            if( pxTCB->xTaskRunState == taskTASK_NOT_RUNNING )
+            {
+                prvDeleteTCB( pxTCB );
+            }
+
+            /* Force a reschedule if the task that has just been deleted was running. */
+            if( ( xSchedulerRunning != pdFALSE ) && ( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE ) )
+            {
+                if( pxTCB->xTaskRunState == portGET_CORE_ID() )
+                {
+                    configASSERT( uxSchedulerSuspended == 0 );
+                    vTaskYieldWithinAPI();
+                }
+                else
+                {
+                    prvYieldCore( pxTCB->xTaskRunState );
+                }
+            }
+
+            taskEXIT_CRITICAL();
+        }
+        #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
     }
 
 #endif /* INCLUDE_vTaskDelete */
@@ -1223,7 +2031,6 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB )
 
         configASSERT( pxPreviousWakeTime );
         configASSERT( ( xTimeIncrement > 0U ) );
-        configASSERT( uxSchedulerSuspended == ( UBaseType_t ) 0U );
 
         vTaskSuspendAll();
         {
@@ -1231,6 +2038,8 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB )
              * block. */
             const TickType_t xConstTickCount = xTickCount;
 
+            configASSERT( uxSchedulerSuspended == 1U );
+
             /* Generate the tick time at which the task wants to wake. */
             xTimeToWake = *pxPreviousWakeTime + xTimeIncrement;
 
@@ -1287,7 +2096,11 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB )
          * have put ourselves to sleep. */
         if( xAlreadyYielded == pdFALSE )
         {
-            portYIELD_WITHIN_API();
+            #if ( configNUMBER_OF_CORES == 1 )
+                portYIELD_WITHIN_API();
+            #else
+                vTaskYieldWithinAPI();
+            #endif
         }
         else
         {
@@ -1309,9 +2122,10 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB )
         /* A delay time of zero just forces a reschedule. */
         if( xTicksToDelay > ( TickType_t ) 0U )
         {
-            configASSERT( uxSchedulerSuspended == ( UBaseType_t ) 0U );
             vTaskSuspendAll();
             {
+                configASSERT( uxSchedulerSuspended == 1U );
+
                 traceTASK_DELAY();
 
                 /* A task that is removed from the event list while the
@@ -1334,7 +2148,11 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB )
          * have put ourselves to sleep. */
         if( xAlreadyYielded == pdFALSE )
         {
-            portYIELD_WITHIN_API();
+            #if ( configNUMBER_OF_CORES == 1 )
+                portYIELD_WITHIN_API();
+            #else
+                vTaskYieldWithinAPI();
+            #endif
         }
         else
         {
@@ -1358,12 +2176,14 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB )
 
         configASSERT( pxTCB );
 
-        if( pxTCB == pxCurrentTCB )
-        {
-            /* The task calling this function is querying its own state. */
-            eReturn = eRunning;
-        }
-        else
+        #if ( configNUMBER_OF_CORES == 1 )
+            if( pxTCB == pxCurrentTCB )
+            {
+                /* The task calling this function is querying its own state. */
+                eReturn = eRunning;
+            }
+            else
+        #endif
         {
             taskENTER_CRITICAL();
             {
@@ -1407,7 +2227,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB )
                              * suspended. */
                             eReturn = eSuspended;
 
-                            for( x = 0; x < configTASK_NOTIFICATION_ARRAY_ENTRIES; x++ )
+                            for( x = ( BaseType_t ) 0; x < ( BaseType_t ) configTASK_NOTIFICATION_ARRAY_ENTRIES; x++ )
                             {
                                 if( pxTCB->ucNotifyState[ x ] == taskWAITING_NOTIFICATION )
                                 {
@@ -1441,9 +2261,27 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB )
 
             else /*lint !e525 Negative indentation is intended to make use of pre-processor clearer. */
             {
-                /* If the task is not in any other state, it must be in the
-                 * Ready (including pending ready) state. */
-                eReturn = eReady;
+                #if ( configNUMBER_OF_CORES == 1 )
+                {
+                    /* If the task is not in any other state, it must be in the
+                     * Ready (including pending ready) state. */
+                    eReturn = eReady;
+                }
+                #else /* #if ( configNUMBER_OF_CORES == 1 ) */
+                {
+                    if( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE )
+                    {
+                        /* Is it actively running on a core? */
+                        eReturn = eRunning;
+                    }
+                    else
+                    {
+                        /* If the task is not in any other state, it must be in the
+                         * Ready (including pending ready) state. */
+                        eReturn = eReady;
+                    }
+                }
+                #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
             }
         }
 
@@ -1481,7 +2319,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB )
     {
         TCB_t const * pxTCB;
         UBaseType_t uxReturn;
-        UBaseType_t uxSavedInterruptState;
+        UBaseType_t uxSavedInterruptStatus;
 
         /* RTOS ports that support interrupt nesting have the concept of a
          * maximum  system call (or maximum API call) interrupt priority.
@@ -1501,14 +2339,14 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB )
          * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
         portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
 
-        uxSavedInterruptState = portSET_INTERRUPT_MASK_FROM_ISR();
+        uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
         {
             /* If null is passed in here then it is the priority of the calling
              * task that is being queried. */
             pxTCB = prvGetTCBFromHandle( xTask );
             uxReturn = pxTCB->uxPriority;
         }
-        portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptState );
+        taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
 
         return uxReturn;
     }
@@ -1525,6 +2363,10 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB )
         UBaseType_t uxCurrentBasePriority, uxPriorityUsedOnEntry;
         BaseType_t xYieldRequired = pdFALSE;
 
+        #if ( configNUMBER_OF_CORES > 1 )
+            BaseType_t xYieldForTask = pdFALSE;
+        #endif
+
         configASSERT( uxNewPriority < configMAX_PRIORITIES );
 
         /* Ensure the new priority is valid. */
@@ -1558,36 +2400,51 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB )
             if( uxCurrentBasePriority != uxNewPriority )
             {
                 /* The priority change may have readied a task of higher
-                 * priority than the calling task. */
+                 * priority than a running task. */
                 if( uxNewPriority > uxCurrentBasePriority )
                 {
-                    if( pxTCB != pxCurrentTCB )
+                    #if ( configNUMBER_OF_CORES == 1 )
                     {
-                        /* The priority of a task other than the currently
-                         * running task is being raised.  Is the priority being
-                         * raised above that of the running task? */
-                        if( uxNewPriority > pxCurrentTCB->uxPriority )
+                        if( pxTCB != pxCurrentTCB )
                         {
-                            xYieldRequired = pdTRUE;
+                            /* The priority of a task other than the currently
+                             * running task is being raised.  Is the priority being
+                             * raised above that of the running task? */
+                            if( uxNewPriority > pxCurrentTCB->uxPriority )
+                            {
+                                xYieldRequired = pdTRUE;
+                            }
+                            else
+                            {
+                                mtCOVERAGE_TEST_MARKER();
+                            }
                         }
                         else
                         {
-                            mtCOVERAGE_TEST_MARKER();
+                            /* The priority of the running task is being raised,
+                             * but the running task must already be the highest
+                             * priority task able to run so no yield is required. */
                         }
                     }
-                    else
+                    #else /* #if ( configNUMBER_OF_CORES == 1 ) */
                     {
-                        /* The priority of the running task is being raised,
-                         * but the running task must already be the highest
-                         * priority task able to run so no yield is required. */
+                        /* The priority of a task is being raised so
+                         * perform a yield for this task later. */
+                        xYieldForTask = pdTRUE;
                     }
+                    #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
                 }
-                else if( pxTCB == pxCurrentTCB )
+                else if( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE )
                 {
-                    /* Setting the priority of the running task down means
+                    /* Setting the priority of a running task down means
                      * there may now be another task of higher priority that
                      * is ready to execute. */
-                    xYieldRequired = pdTRUE;
+                    #if ( configUSE_TASK_PREEMPTION_DISABLE == 1 )
+                        if( pxTCB->xPreemptionDisable == pdFALSE )
+                    #endif
+                    {
+                        xYieldRequired = pdTRUE;
+                    }
                 }
                 else
                 {
@@ -1659,17 +2516,51 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB )
                 }
                 else
                 {
-                    mtCOVERAGE_TEST_MARKER();
+                    #if ( configNUMBER_OF_CORES == 1 )
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+                    #else
+                    {
+                        /* It's possible that xYieldForTask was already set to pdTRUE because
+                         * its priority is being raised. However, since it is not in a ready list
+                         * we don't actually need to yield for it. */
+                        xYieldForTask = pdFALSE;
+                    }
+                    #endif
                 }
 
-                if( xYieldRequired != pdFALSE )
+                #if ( configNUMBER_OF_CORES == 1 )
                 {
-                    taskYIELD_IF_USING_PREEMPTION();
+                    if( xYieldRequired != pdFALSE )
+                    {
+                        taskYIELD_IF_USING_PREEMPTION();
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
                 }
-                else
+                #else /* #if ( configNUMBER_OF_CORES == 1 ) */
                 {
-                    mtCOVERAGE_TEST_MARKER();
+                    #if ( configUSE_PREEMPTION == 1 )
+                    {
+                        if( xYieldRequired != pdFALSE )
+                        {
+                            prvYieldCore( pxTCB->xTaskRunState );
+                        }
+                        else if( xYieldForTask != pdFALSE )
+                        {
+                            prvYieldForTask( pxTCB );
+                        }
+                        else
+                        {
+                            mtCOVERAGE_TEST_MARKER();
+                        }
+                    }
+                    #endif /* #if ( configUSE_PREEMPTION == 1 ) */
                 }
+                #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
 
                 /* Remove compiler warning about unused variables when the port
                  * optimised task selection is not being used. */
@@ -1682,12 +2573,142 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB )
 #endif /* INCLUDE_vTaskPrioritySet */
 /*-----------------------------------------------------------*/
 
+#if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
+    void vTaskCoreAffinitySet( const TaskHandle_t xTask,
+                               UBaseType_t uxCoreAffinityMask )
+    {
+        TCB_t * pxTCB;
+        BaseType_t xCoreID;
+        UBaseType_t uxPrevCoreAffinityMask;
+
+        #if ( configUSE_PREEMPTION == 1 )
+            UBaseType_t uxPrevNotAllowedCores;
+        #endif
+
+        taskENTER_CRITICAL();
+        {
+            pxTCB = prvGetTCBFromHandle( xTask );
+
+            uxPrevCoreAffinityMask = pxTCB->uxCoreAffinityMask;
+            pxTCB->uxCoreAffinityMask = uxCoreAffinityMask;
+
+            if( xSchedulerRunning != pdFALSE )
+            {
+                if( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE )
+                {
+                    xCoreID = ( BaseType_t ) pxTCB->xTaskRunState;
+
+                    /* If the task can no longer run on the core it was running,
+                     * request the core to yield. */
+                    if( ( uxCoreAffinityMask & ( ( UBaseType_t ) 1U << ( UBaseType_t ) xCoreID ) ) == 0U )
+                    {
+                        prvYieldCore( xCoreID );
+                    }
+                }
+                else
+                {
+                    #if ( configUSE_PREEMPTION == 1 )
+                    {
+                        /* Calculate the cores on which this task was not allowed to
+                         * run previously. */
+                        uxPrevNotAllowedCores = ( ~uxPrevCoreAffinityMask ) & ( ( 1U << configNUMBER_OF_CORES ) - 1U );
+
+                        /* Does the new core mask enables this task to run on any of the
+                         * previously not allowed cores? If yes, check if this task can be
+                         * scheduled on any of those cores. */
+                        if( ( uxPrevNotAllowedCores & uxCoreAffinityMask ) != 0U )
+                        {
+                            prvYieldForTask( pxTCB );
+                        }
+                    }
+                    #else /* #if( configUSE_PREEMPTION == 1 ) */
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+                    #endif /* #if( configUSE_PREEMPTION == 1 ) */
+                }
+            }
+        }
+        taskEXIT_CRITICAL();
+    }
+#endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
+    UBaseType_t vTaskCoreAffinityGet( ConstTaskHandle_t xTask )
+    {
+        const TCB_t * pxTCB;
+        UBaseType_t uxCoreAffinityMask;
+
+        taskENTER_CRITICAL();
+        {
+            pxTCB = prvGetTCBFromHandle( xTask );
+            uxCoreAffinityMask = pxTCB->uxCoreAffinityMask;
+        }
+        taskEXIT_CRITICAL();
+
+        return uxCoreAffinityMask;
+    }
+#endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */
+
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TASK_PREEMPTION_DISABLE == 1 )
+
+    void vTaskPreemptionDisable( const TaskHandle_t xTask )
+    {
+        TCB_t * pxTCB;
+
+        taskENTER_CRITICAL();
+        {
+            pxTCB = prvGetTCBFromHandle( xTask );
+
+            pxTCB->xPreemptionDisable = pdTRUE;
+        }
+        taskEXIT_CRITICAL();
+    }
+
+#endif /* #if ( configUSE_TASK_PREEMPTION_DISABLE == 1 ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TASK_PREEMPTION_DISABLE == 1 )
+
+    void vTaskPreemptionEnable( const TaskHandle_t xTask )
+    {
+        TCB_t * pxTCB;
+        BaseType_t xCoreID;
+
+        taskENTER_CRITICAL();
+        {
+            pxTCB = prvGetTCBFromHandle( xTask );
+
+            pxTCB->xPreemptionDisable = pdFALSE;
+
+            if( xSchedulerRunning != pdFALSE )
+            {
+                if( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE )
+                {
+                    xCoreID = ( BaseType_t ) pxTCB->xTaskRunState;
+                    prvYieldCore( xCoreID );
+                }
+            }
+        }
+        taskEXIT_CRITICAL();
+    }
+
+#endif /* #if ( configUSE_TASK_PREEMPTION_DISABLE == 1 ) */
+/*-----------------------------------------------------------*/
+
 #if ( INCLUDE_vTaskSuspend == 1 )
 
     void vTaskSuspend( TaskHandle_t xTaskToSuspend )
     {
         TCB_t * pxTCB;
 
+        #if ( configNUMBER_OF_CORES > 1 )
+            TaskRunning_t xTaskRunningOnCore;
+        #endif
+
         taskENTER_CRITICAL();
         {
             /* If null is passed in here then it is the running task that is
@@ -1696,6 +2717,10 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB )
 
             traceTASK_SUSPEND( pxTCB );
 
+            #if ( configNUMBER_OF_CORES > 1 )
+                xTaskRunningOnCore = pxTCB->xTaskRunState;
+            #endif
+
             /* Remove task from the ready/delayed list and place in the
              * suspended list. */
             if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
@@ -1723,7 +2748,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB )
             {
                 BaseType_t x;
 
-                for( x = 0; x < configTASK_NOTIFICATION_ARRAY_ENTRIES; x++ )
+                for( x = ( BaseType_t ) 0; x < ( BaseType_t ) configTASK_NOTIFICATION_ARRAY_ENTRIES; x++ )
                 {
                     if( pxTCB->ucNotifyState[ x ] == taskWAITING_NOTIFICATION )
                     {
@@ -1735,54 +2760,104 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB )
             }
             #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
         }
-        taskEXIT_CRITICAL();
 
-        if( xSchedulerRunning != pdFALSE )
+        #if ( configNUMBER_OF_CORES == 1 )
         {
-            /* Reset the next expected unblock time in case it referred to the
-             * task that is now in the Suspended state. */
-            taskENTER_CRITICAL();
-            {
-                prvResetNextTaskUnblockTime();
-            }
             taskEXIT_CRITICAL();
-        }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
-        }
 
-        if( pxTCB == pxCurrentTCB )
-        {
             if( xSchedulerRunning != pdFALSE )
             {
-                /* The current task has just been suspended. */
-                configASSERT( uxSchedulerSuspended == ( UBaseType_t ) 0U );
-                portYIELD_WITHIN_API();
+                /* Reset the next expected unblock time in case it referred to the
+                 * task that is now in the Suspended state. */
+                taskENTER_CRITICAL();
+                {
+                    prvResetNextTaskUnblockTime();
+                }
+                taskEXIT_CRITICAL();
             }
             else
             {
-                /* The scheduler is not running, but the task that was pointed
-                 * to by pxCurrentTCB has just been suspended and pxCurrentTCB
-                 * must be adjusted to point to a different task. */
-                if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == uxCurrentNumberOfTasks ) /*lint !e931 Right has no side effect, just volatile. */
+                mtCOVERAGE_TEST_MARKER();
+            }
+
+            if( pxTCB == pxCurrentTCB )
+            {
+                if( xSchedulerRunning != pdFALSE )
                 {
-                    /* No other tasks are ready, so set pxCurrentTCB back to
-                     * NULL so when the next task is created pxCurrentTCB will
-                     * be set to point to it no matter what its relative priority
-                     * is. */
-                    pxCurrentTCB = NULL;
+                    /* The current task has just been suspended. */
+                    configASSERT( uxSchedulerSuspended == 0 );
+                    portYIELD_WITHIN_API();
                 }
                 else
                 {
-                    vTaskSwitchContext();
+                    /* The scheduler is not running, but the task that was pointed
+                     * to by pxCurrentTCB has just been suspended and pxCurrentTCB
+                     * must be adjusted to point to a different task. */
+                    if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == uxCurrentNumberOfTasks ) /*lint !e931 Right has no side effect, just volatile. */
+                    {
+                        /* No other tasks are ready, so set pxCurrentTCB back to
+                         * NULL so when the next task is created pxCurrentTCB will
+                         * be set to point to it no matter what its relative priority
+                         * is. */
+                        pxCurrentTCB = NULL;
+                    }
+                    else
+                    {
+                        vTaskSwitchContext();
+                    }
                 }
             }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
         }
-        else
+        #else /* #if ( configNUMBER_OF_CORES == 1 ) */
         {
-            mtCOVERAGE_TEST_MARKER();
+            if( xSchedulerRunning != pdFALSE )
+            {
+                /* Reset the next expected unblock time in case it referred to the
+                 * task that is now in the Suspended state. */
+                prvResetNextTaskUnblockTime();
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+
+            if( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE )
+            {
+                if( xSchedulerRunning != pdFALSE )
+                {
+                    if( xTaskRunningOnCore == portGET_CORE_ID() )
+                    {
+                        /* The current task has just been suspended. */
+                        configASSERT( uxSchedulerSuspended == 0 );
+                        vTaskYieldWithinAPI();
+                    }
+                    else
+                    {
+                        prvYieldCore( xTaskRunningOnCore );
+                    }
+                }
+                else
+                {
+                    /* This code path is not possible because only Idle tasks are
+                     * assigned a core before the scheduler is started ( i.e.
+                     * taskTASK_IS_RUNNING is only true for idle tasks before
+                     * the scheduler is started ) and idle tasks cannot be
+                     * suspended. */
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+
+            taskEXIT_CRITICAL();
         }
+        #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
     }
 
 #endif /* INCLUDE_vTaskSuspend */
@@ -1843,9 +2918,20 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB )
         /* It does not make sense to resume the calling task. */
         configASSERT( xTaskToResume );
 
-        /* The parameter cannot be NULL as it is impossible to resume the
-         * currently executing task. */
-        if( ( pxTCB != pxCurrentTCB ) && ( pxTCB != NULL ) )
+        #if ( configNUMBER_OF_CORES == 1 )
+
+            /* The parameter cannot be NULL as it is impossible to resume the
+             * currently executing task. */
+            if( ( pxTCB != pxCurrentTCB ) && ( pxTCB != NULL ) )
+        #else
+
+            /* The parameter cannot be NULL as it is impossible to resume the
+             * currently executing task. It is also impossible to resume a task
+             * that is actively running on another core but it is not safe
+             * to check their run state here. Therefore, we get into a critical
+             * section and check if the task is actually suspended or not. */
+            if( pxTCB != NULL )
+        #endif
         {
             taskENTER_CRITICAL();
             {
@@ -1858,18 +2944,30 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB )
                     ( void ) uxListRemove( &( pxTCB->xStateListItem ) );
                     prvAddTaskToReadyList( pxTCB );
 
-                    /* A higher priority task may have just been resumed. */
-                    if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+                    #if ( configNUMBER_OF_CORES == 1 )
                     {
-                        /* This yield may not cause the task just resumed to run,
-                         * but will leave the lists in the correct state for the
-                         * next yield. */
-                        taskYIELD_IF_USING_PREEMPTION();
+                        /* A higher priority task may have just been resumed. */
+                        if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+                        {
+                            /* This yield may not cause the task just resumed to run,
+                             * but will leave the lists in the correct state for the
+                             * next yield. */
+                            taskYIELD_IF_USING_PREEMPTION();
+                        }
+                        else
+                        {
+                            mtCOVERAGE_TEST_MARKER();
+                        }
                     }
-                    else
+                    #else /* #if ( configNUMBER_OF_CORES == 1 ) */
                     {
-                        mtCOVERAGE_TEST_MARKER();
+                        #if ( configUSE_PREEMPTION == 1 )
+                        {
+                            prvYieldForTask( pxTCB );
+                        }
+                        #endif /* #if ( configUSE_PREEMPTION == 1 ) */
                     }
+                    #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
                 }
                 else
                 {
@@ -1916,7 +3014,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB )
          * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
         portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
 
-        uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+        uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
         {
             if( prvTaskIsTaskSuspended( pxTCB ) != pdFALSE )
             {
@@ -1925,21 +3023,25 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB )
                 /* Check the ready lists can be accessed. */
                 if( uxSchedulerSuspended == ( UBaseType_t ) 0U )
                 {
-                    /* Ready lists can be accessed so move the task from the
-                     * suspended list to the ready list directly. */
-                    if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+                    #if ( configNUMBER_OF_CORES == 1 )
                     {
-                        xYieldRequired = pdTRUE;
+                        /* Ready lists can be accessed so move the task from the
+                         * suspended list to the ready list directly. */
+                        if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+                        {
+                            xYieldRequired = pdTRUE;
 
-                        /* Mark that a yield is pending in case the user is not
-                         * using the return value to initiate a context switch
-                         * from the ISR using portYIELD_FROM_ISR. */
-                        xYieldPending = pdTRUE;
-                    }
-                    else
-                    {
-                        mtCOVERAGE_TEST_MARKER();
+                            /* Mark that a yield is pending in case the user is not
+                             * using the return value to initiate a context switch
+                             * from the ISR using portYIELD_FROM_ISR. */
+                            xYieldPendings[ 0 ] = pdTRUE;
+                        }
+                        else
+                        {
+                            mtCOVERAGE_TEST_MARKER();
+                        }
                     }
+                    #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
 
                     ( void ) uxListRemove( &( pxTCB->xStateListItem ) );
                     prvAddTaskToReadyList( pxTCB );
@@ -1951,13 +3053,24 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB )
                      * unsuspended. */
                     vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
                 }
+
+                #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_PREEMPTION == 1 ) )
+                {
+                    prvYieldForTask( pxTCB );
+
+                    if( xYieldPendings[ portGET_CORE_ID() ] != pdFALSE )
+                    {
+                        xYieldRequired = pdTRUE;
+                    }
+                }
+                #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_PREEMPTION == 1 ) ) */
             }
             else
             {
                 mtCOVERAGE_TEST_MARKER();
             }
         }
-        portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+        taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
 
         return xYieldRequired;
     }
@@ -1965,48 +3078,184 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB )
 #endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */
 /*-----------------------------------------------------------*/
 
+static BaseType_t prvCreateIdleTasks( void )
+{
+    BaseType_t xReturn = pdPASS;
+
+    #if ( configNUMBER_OF_CORES == 1 )
+    {
+        /* Add the idle task at the lowest priority. */
+        #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+        {
+            StaticTask_t * pxIdleTaskTCBBuffer = NULL;
+            StackType_t * pxIdleTaskStackBuffer = NULL;
+            uint32_t ulIdleTaskStackSize;
+
+            /* The Idle task is created using user provided RAM - obtain the
+             * address of the RAM then create the idle task. */
+            vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize );
+            xIdleTaskHandles[ 0 ] = xTaskCreateStatic( prvIdleTask,
+                                                       configIDLE_TASK_NAME,
+                                                       ulIdleTaskStackSize,
+                                                       ( void * ) NULL,       /*lint !e961.  The cast is not redundant for all compilers. */
+                                                       portPRIVILEGE_BIT,     /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
+                                                       pxIdleTaskStackBuffer,
+                                                       pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
+
+            if( xIdleTaskHandles[ 0 ] != NULL )
+            {
+                xReturn = pdPASS;
+            }
+            else
+            {
+                xReturn = pdFAIL;
+            }
+        }
+        #else /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+        {
+            /* The Idle task is being created using dynamically allocated RAM. */
+            xReturn = xTaskCreate( prvIdleTask,
+                                   configIDLE_TASK_NAME,
+                                   configMINIMAL_STACK_SIZE,
+                                   ( void * ) NULL,
+                                   portPRIVILEGE_BIT,        /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
+                                   &xIdleTaskHandles[ 0 ] ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
+        }
+        #endif /* configSUPPORT_STATIC_ALLOCATION */
+    }
+    #else /* #if ( configNUMBER_OF_CORES == 1 ) */
+    {
+        BaseType_t xCoreID;
+        char cIdleName[ configMAX_TASK_NAME_LEN ];
+
+        /* Add each idle task at the lowest priority. */
+        for( xCoreID = ( BaseType_t ) 0; xCoreID < ( BaseType_t ) configNUMBER_OF_CORES; xCoreID++ )
+        {
+            BaseType_t x;
+
+            if( xReturn == pdFAIL )
+            {
+                break;
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+
+            for( x = ( BaseType_t ) 0; x < ( BaseType_t ) configMAX_TASK_NAME_LEN; x++ )
+            {
+                cIdleName[ x ] = configIDLE_TASK_NAME[ x ];
+
+                /* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than
+                 * configMAX_TASK_NAME_LEN characters just in case the memory after the
+                 * string is not accessible (extremely unlikely). */
+                if( cIdleName[ x ] == ( char ) 0x00 )
+                {
+                    break;
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+
+            /* Append the idle task number to the end of the name if there is space. */
+            if( x < ( BaseType_t ) configMAX_TASK_NAME_LEN )
+            {
+                cIdleName[ x ] = ( char ) ( xCoreID + '0' );
+                x++;
+
+                /* And append a null character if there is space. */
+                if( x < ( BaseType_t ) configMAX_TASK_NAME_LEN )
+                {
+                    cIdleName[ x ] = '\0';
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+
+            #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+            {
+                if( xCoreID == 0 )
+                {
+                    StaticTask_t * pxIdleTaskTCBBuffer = NULL;
+                    StackType_t * pxIdleTaskStackBuffer = NULL;
+                    uint32_t ulIdleTaskStackSize;
+
+                    /* The Idle task is created using user provided RAM - obtain the
+                     * address of the RAM then create the idle task. */
+                    vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize );
+                    xIdleTaskHandles[ xCoreID ] = xTaskCreateStatic( prvIdleTask,
+                                                                     cIdleName,
+                                                                     ulIdleTaskStackSize,
+                                                                     ( void * ) NULL,       /*lint !e961.  The cast is not redundant for all compilers. */
+                                                                     portPRIVILEGE_BIT,     /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
+                                                                     pxIdleTaskStackBuffer,
+                                                                     pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
+                }
+                else
+                {
+                    xIdleTaskHandles[ xCoreID ] = xTaskCreateStatic( prvMinimalIdleTask,
+                                                                     cIdleName,
+                                                                     configMINIMAL_STACK_SIZE,
+                                                                     ( void * ) NULL,                   /*lint !e961.  The cast is not redundant for all compilers. */
+                                                                     portPRIVILEGE_BIT,                 /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
+                                                                     xIdleTaskStackBuffers[ xCoreID - 1 ],
+                                                                     &xIdleTCBBuffers[ xCoreID - 1 ] ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
+                }
+
+                if( xIdleTaskHandles[ xCoreID ] != NULL )
+                {
+                    xReturn = pdPASS;
+                }
+                else
+                {
+                    xReturn = pdFAIL;
+                }
+            }
+            #else /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+            {
+                if( xCoreID == 0 )
+                {
+                    /* The Idle task is being created using dynamically allocated RAM. */
+                    xReturn = xTaskCreate( prvIdleTask,
+                                           cIdleName,
+                                           configMINIMAL_STACK_SIZE,
+                                           ( void * ) NULL,
+                                           portPRIVILEGE_BIT,              /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
+                                           &xIdleTaskHandles[ xCoreID ] ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
+                }
+                else
+                {
+                    xReturn = xTaskCreate( prvMinimalIdleTask,
+                                           cIdleName,
+                                           configMINIMAL_STACK_SIZE,
+                                           ( void * ) NULL,
+                                           portPRIVILEGE_BIT,              /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
+                                           &xIdleTaskHandles[ xCoreID ] ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
+                }
+            }
+            #endif /* configSUPPORT_STATIC_ALLOCATION */
+        }
+    }
+    #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
+
+    return xReturn;
+}
+
+/*-----------------------------------------------------------*/
+
 void vTaskStartScheduler( void )
 {
     BaseType_t xReturn;
 
-    /* Add the idle task at the lowest priority. */
-    #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
-    {
-        StaticTask_t * pxIdleTaskTCBBuffer = NULL;
-        StackType_t * pxIdleTaskStackBuffer = NULL;
-        uint32_t ulIdleTaskStackSize;
-
-        /* The Idle task is created using user provided RAM - obtain the
-         * address of the RAM then create the idle task. */
-        vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize );
-        xIdleTaskHandle = xTaskCreateStatic( prvIdleTask,
-                                             configIDLE_TASK_NAME,
-                                             ulIdleTaskStackSize,
-                                             ( void * ) NULL,       /*lint !e961.  The cast is not redundant for all compilers. */
-                                             portPRIVILEGE_BIT,     /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
-                                             pxIdleTaskStackBuffer,
-                                             pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
-
-        if( xIdleTaskHandle != NULL )
-        {
-            xReturn = pdPASS;
-        }
-        else
-        {
-            xReturn = pdFAIL;
-        }
-    }
-    #else /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
-    {
-        /* The Idle task is being created using dynamically allocated RAM. */
-        xReturn = xTaskCreate( prvIdleTask,
-                               configIDLE_TASK_NAME,
-                               configMINIMAL_STACK_SIZE,
-                               ( void * ) NULL,
-                               portPRIVILEGE_BIT,  /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
-                               &xIdleTaskHandle ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
-    }
-    #endif /* configSUPPORT_STATIC_ALLOCATION */
+    xReturn = prvCreateIdleTasks();
 
     #if ( configUSE_TIMERS == 1 )
     {
@@ -2081,8 +3330,8 @@ void vTaskStartScheduler( void )
     }
 
     /* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0,
-     * meaning xIdleTaskHandle is not used anywhere else. */
-    ( void ) xIdleTaskHandle;
+     * meaning xIdleTaskHandles are not used anywhere else. */
+    ( void ) xIdleTaskHandles;
 
     /* OpenOCD makes use of uxTopUsedPriority for thread debugging. Prevent uxTopUsedPriority
      * from getting optimized out as it is no longer used by the kernel. */
@@ -2103,23 +3352,83 @@ void vTaskEndScheduler( void )
 
 void vTaskSuspendAll( void )
 {
-    /* A critical section is not required as the variable is of type
-     * BaseType_t.  Please read Richard Barry's reply in the following link to a
-     * post in the FreeRTOS support forum before reporting this as a bug! -
-     * https://goo.gl/wu4acr */
+    #if ( configNUMBER_OF_CORES == 1 )
+    {
+        /* A critical section is not required as the variable is of type
+         * BaseType_t.  Please read Richard Barry's reply in the following link to a
+         * post in the FreeRTOS support forum before reporting this as a bug! -
+         * https://goo.gl/wu4acr */
 
-    /* portSOFTWARE_BARRIER() is only implemented for emulated/simulated ports that
-     * do not otherwise exhibit real time behaviour. */
-    portSOFTWARE_BARRIER();
+        /* portSOFTWARE_BARRIER() is only implemented for emulated/simulated ports that
+         * do not otherwise exhibit real time behaviour. */
+        portSOFTWARE_BARRIER();
 
-    /* The scheduler is suspended if uxSchedulerSuspended is non-zero.  An increment
-     * is used to allow calls to vTaskSuspendAll() to nest. */
-    ++uxSchedulerSuspended;
+        /* The scheduler is suspended if uxSchedulerSuspended is non-zero.  An increment
+         * is used to allow calls to vTaskSuspendAll() to nest. */
+        ++uxSchedulerSuspended;
 
-    /* Enforces ordering for ports and optimised compilers that may otherwise place
-     * the above increment elsewhere. */
-    portMEMORY_BARRIER();
+        /* Enforces ordering for ports and optimised compilers that may otherwise place
+         * the above increment elsewhere. */
+        portMEMORY_BARRIER();
+    }
+    #else /* #if ( configNUMBER_OF_CORES == 1 ) */
+    {
+        UBaseType_t ulState;
+
+        /* This must only be called from within a task. */
+        portASSERT_IF_IN_ISR();
+
+        if( xSchedulerRunning != pdFALSE )
+        {
+            /* Writes to uxSchedulerSuspended must be protected by both the task AND ISR locks.
+             * We must disable interrupts before we grab the locks in the event that this task is
+             * interrupted and switches context before incrementing uxSchedulerSuspended.
+             * It is safe to re-enable interrupts after releasing the ISR lock and incrementing
+             * uxSchedulerSuspended since that will prevent context switches. */
+            ulState = portSET_INTERRUPT_MASK();
+
+            /* portSOFRWARE_BARRIER() is only implemented for emulated/simulated ports that
+             * do not otherwise exhibit real time behaviour. */
+            portSOFTWARE_BARRIER();
+
+            portGET_TASK_LOCK();
+
+            /* uxSchedulerSuspended is increased after prvCheckForRunStateChange. The
+             * purpose is to prevent altering the variable when fromISR APIs are readying
+             * it. */
+            if( uxSchedulerSuspended == 0U )
+            {
+                if( portGET_CRITICAL_NESTING_COUNT() == 0U )
+                {
+                    prvCheckForRunStateChange();
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+
+            portGET_ISR_LOCK();
+
+            /* The scheduler is suspended if uxSchedulerSuspended is non-zero. An increment
+             * is used to allow calls to vTaskSuspendAll() to nest. */
+            ++uxSchedulerSuspended;
+            portRELEASE_ISR_LOCK();
+
+            portCLEAR_INTERRUPT_MASK( ulState );
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+    #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
 }
+
 /*----------------------------------------------------------*/
 
 #if ( configUSE_TICKLESS_IDLE != 0 )
@@ -2190,108 +3499,139 @@ BaseType_t xTaskResumeAll( void )
     TCB_t * pxTCB = NULL;
     BaseType_t xAlreadyYielded = pdFALSE;
 
-    /* If uxSchedulerSuspended is zero then this function does not match a
-     * previous call to vTaskSuspendAll(). */
-    configASSERT( uxSchedulerSuspended != ( UBaseType_t ) 0U );
-
-    /* It is possible that an ISR caused a task to be removed from an event
-     * list while the scheduler was suspended.  If this was the case then the
-     * removed task will have been added to the xPendingReadyList.  Once the
-     * scheduler has been resumed it is safe to move all the pending ready
-     * tasks from this list into their appropriate ready list. */
-    taskENTER_CRITICAL();
+    #if ( configNUMBER_OF_CORES > 1 )
+        if( xSchedulerRunning != pdFALSE )
+    #endif
     {
-        --uxSchedulerSuspended;
-
-        if( uxSchedulerSuspended == ( UBaseType_t ) 0U )
+        /* It is possible that an ISR caused a task to be removed from an event
+         * list while the scheduler was suspended.  If this was the case then the
+         * removed task will have been added to the xPendingReadyList.  Once the
+         * scheduler has been resumed it is safe to move all the pending ready
+         * tasks from this list into their appropriate ready list. */
+        taskENTER_CRITICAL();
         {
-            if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U )
+            BaseType_t xCoreID;
+            xCoreID = portGET_CORE_ID();
+
+            /* If uxSchedulerSuspended is zero then this function does not match a
+             * previous call to vTaskSuspendAll(). */
+            configASSERT( uxSchedulerSuspended != 0U );
+
+            --uxSchedulerSuspended;
+            portRELEASE_TASK_LOCK();
+
+            if( uxSchedulerSuspended == ( UBaseType_t ) 0U )
             {
-                /* Move any readied tasks from the pending list into the
-                 * appropriate ready list. */
-                while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
+                if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U )
                 {
-                    pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
-                    listREMOVE_ITEM( &( pxTCB->xEventListItem ) );
-                    portMEMORY_BARRIER();
-                    listREMOVE_ITEM( &( pxTCB->xStateListItem ) );
-                    prvAddTaskToReadyList( pxTCB );
-
-                    /* If the moved task has a priority higher than the current
-                     * task then a yield must be performed. */
-                    if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+                    /* Move any readied tasks from the pending list into the
+                     * appropriate ready list. */
+                    while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
                     {
-                        xYieldPending = pdTRUE;
-                    }
-                    else
-                    {
-                        mtCOVERAGE_TEST_MARKER();
-                    }
-                }
+                        pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+                        listREMOVE_ITEM( &( pxTCB->xEventListItem ) );
+                        portMEMORY_BARRIER();
+                        listREMOVE_ITEM( &( pxTCB->xStateListItem ) );
+                        prvAddTaskToReadyList( pxTCB );
 
-                if( pxTCB != NULL )
-                {
-                    /* A task was unblocked while the scheduler was suspended,
-                     * which may have prevented the next unblock time from being
-                     * re-calculated, in which case re-calculate it now.  Mainly
-                     * important for low power tickless implementations, where
-                     * this can prevent an unnecessary exit from low power
-                     * state. */
-                    prvResetNextTaskUnblockTime();
-                }
-
-                /* If any ticks occurred while the scheduler was suspended then
-                 * they should be processed now.  This ensures the tick count does
-                 * not  slip, and that any delayed tasks are resumed at the correct
-                 * time. */
-                {
-                    TickType_t xPendedCounts = xPendedTicks; /* Non-volatile copy. */
-
-                    if( xPendedCounts > ( TickType_t ) 0U )
-                    {
-                        do
+                        #if ( configNUMBER_OF_CORES == 1 )
                         {
-                            if( xTaskIncrementTick() != pdFALSE )
+                            /* If the moved task has a priority higher than the current
+                             * task then a yield must be performed. */
+                            if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
                             {
-                                xYieldPending = pdTRUE;
+                                xYieldPendings[ xCoreID ] = pdTRUE;
                             }
                             else
                             {
                                 mtCOVERAGE_TEST_MARKER();
                             }
+                        }
+                        #else /* #if ( configNUMBER_OF_CORES == 1 ) */
+                        {
+                            /* All appropriate tasks yield at the moment a task is added to xPendingReadyList.
+                             * If the current core yielded then vTaskSwitchContext() has already been called
+                             * which sets xYieldPendings for the current core to pdTRUE. */
+                        }
+                        #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
+                    }
 
-                            --xPendedCounts;
-                        } while( xPendedCounts > ( TickType_t ) 0U );
+                    if( pxTCB != NULL )
+                    {
+                        /* A task was unblocked while the scheduler was suspended,
+                         * which may have prevented the next unblock time from being
+                         * re-calculated, in which case re-calculate it now.  Mainly
+                         * important for low power tickless implementations, where
+                         * this can prevent an unnecessary exit from low power
+                         * state. */
+                        prvResetNextTaskUnblockTime();
+                    }
 
-                        xPendedTicks = 0;
+                    /* If any ticks occurred while the scheduler was suspended then
+                     * they should be processed now.  This ensures the tick count does
+                     * not  slip, and that any delayed tasks are resumed at the correct
+                     * time.
+                     *
+                     * It should be safe to call xTaskIncrementTick here from any core
+                     * since we are in a critical section and xTaskIncrementTick itself
+                     * protects itself within a critical section. Suspending the scheduler
+                     * from any core causes xTaskIncrementTick to increment uxPendedCounts. */
+                    {
+                        TickType_t xPendedCounts = xPendedTicks; /* Non-volatile copy. */
+
+                        if( xPendedCounts > ( TickType_t ) 0U )
+                        {
+                            do
+                            {
+                                if( xTaskIncrementTick() != pdFALSE )
+                                {
+                                    /* Other cores are interrupted from
+                                     * within xTaskIncrementTick(). */
+                                    xYieldPendings[ xCoreID ] = pdTRUE;
+                                }
+                                else
+                                {
+                                    mtCOVERAGE_TEST_MARKER();
+                                }
+
+                                --xPendedCounts;
+                            } while( xPendedCounts > ( TickType_t ) 0U );
+
+                            xPendedTicks = 0;
+                        }
+                        else
+                        {
+                            mtCOVERAGE_TEST_MARKER();
+                        }
+                    }
+
+                    if( xYieldPendings[ xCoreID ] != pdFALSE )
+                    {
+                        #if ( configUSE_PREEMPTION != 0 )
+                        {
+                            xAlreadyYielded = pdTRUE;
+                        }
+                        #endif /* #if ( configUSE_PREEMPTION != 0 ) */
+
+                        #if ( configNUMBER_OF_CORES == 1 )
+                        {
+                            taskYIELD_IF_USING_PREEMPTION();
+                        }
+                        #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
                     }
                     else
                     {
                         mtCOVERAGE_TEST_MARKER();
                     }
                 }
-
-                if( xYieldPending != pdFALSE )
-                {
-                    #if ( configUSE_PREEMPTION != 0 )
-                    {
-                        xAlreadyYielded = pdTRUE;
-                    }
-                    #endif
-                    taskYIELD_IF_USING_PREEMPTION();
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
             }
         }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
-        }
+        taskEXIT_CRITICAL();
     }
-    taskEXIT_CRITICAL();
 
     return xAlreadyYielded;
 }
@@ -2365,71 +3705,137 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char
 
 #if ( INCLUDE_xTaskGetHandle == 1 )
 
-    static TCB_t * prvSearchForNameWithinSingleList( List_t * pxList,
-                                                     const char pcNameToQuery[] )
-    {
-        TCB_t * pxNextTCB;
-        TCB_t * pxFirstTCB;
-        TCB_t * pxReturn = NULL;
-        UBaseType_t x;
-        char cNextChar;
-        BaseType_t xBreakLoop;
-
-        /* This function is called with the scheduler suspended. */
-
-        if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )
+    #if ( configNUMBER_OF_CORES == 1 )
+        static TCB_t * prvSearchForNameWithinSingleList( List_t * pxList,
+                                                         const char pcNameToQuery[] )
         {
-            listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+            TCB_t * pxNextTCB;
+            TCB_t * pxFirstTCB;
+            TCB_t * pxReturn = NULL;
+            UBaseType_t x;
+            char cNextChar;
+            BaseType_t xBreakLoop;
 
-            do
+            /* This function is called with the scheduler suspended. */
+
+            if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )
             {
-                listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+                listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 
-                /* Check each character in the name looking for a match or
-                 * mismatch. */
-                xBreakLoop = pdFALSE;
-
-                for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
+                do
                 {
-                    cNextChar = pxNextTCB->pcTaskName[ x ];
+                    listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 
-                    if( cNextChar != pcNameToQuery[ x ] )
+                    /* Check each character in the name looking for a match or
+                     * mismatch. */
+                    xBreakLoop = pdFALSE;
+
+                    for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
                     {
-                        /* Characters didn't match. */
-                        xBreakLoop = pdTRUE;
-                    }
-                    else if( cNextChar == ( char ) 0x00 )
-                    {
-                        /* Both strings terminated, a match must have been
-                         * found. */
-                        pxReturn = pxNextTCB;
-                        xBreakLoop = pdTRUE;
-                    }
-                    else
-                    {
-                        mtCOVERAGE_TEST_MARKER();
+                        cNextChar = pxNextTCB->pcTaskName[ x ];
+
+                        if( cNextChar != pcNameToQuery[ x ] )
+                        {
+                            /* Characters didn't match. */
+                            xBreakLoop = pdTRUE;
+                        }
+                        else if( cNextChar == ( char ) 0x00 )
+                        {
+                            /* Both strings terminated, a match must have been
+                             * found. */
+                            pxReturn = pxNextTCB;
+                            xBreakLoop = pdTRUE;
+                        }
+                        else
+                        {
+                            mtCOVERAGE_TEST_MARKER();
+                        }
+
+                        if( xBreakLoop != pdFALSE )
+                        {
+                            break;
+                        }
                     }
 
-                    if( xBreakLoop != pdFALSE )
+                    if( pxReturn != NULL )
                     {
+                        /* The handle has been found. */
+                        break;
+                    }
+                } while( pxNextTCB != pxFirstTCB );
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+
+            return pxReturn;
+        }
+    #else /* if ( configNUMBER_OF_CORES == 1 ) */
+        static TCB_t * prvSearchForNameWithinSingleList( List_t * pxList,
+                                                         const char pcNameToQuery[] )
+        {
+            TCB_t * pxReturn = NULL;
+            UBaseType_t x;
+            char cNextChar;
+            BaseType_t xBreakLoop;
+            const ListItem_t * pxEndMarker = listGET_END_MARKER( pxList );
+            ListItem_t * pxIterator;
+
+            /* This function is called with the scheduler suspended. */
+
+            if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )
+            {
+                for( pxIterator = listGET_HEAD_ENTRY( pxList ); pxIterator != pxEndMarker; pxIterator = listGET_NEXT( pxIterator ) )
+                {
+                    TCB_t * pxTCB = listGET_LIST_ITEM_OWNER( pxIterator );
+
+                    /* Check each character in the name looking for a match or
+                     * mismatch. */
+                    xBreakLoop = pdFALSE;
+
+                    for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
+                    {
+                        cNextChar = pxTCB->pcTaskName[ x ];
+
+                        if( cNextChar != pcNameToQuery[ x ] )
+                        {
+                            /* Characters didn't match. */
+                            xBreakLoop = pdTRUE;
+                        }
+                        else if( cNextChar == ( char ) 0x00 )
+                        {
+                            /* Both strings terminated, a match must have been
+                             * found. */
+                            pxReturn = pxTCB;
+                            xBreakLoop = pdTRUE;
+                        }
+                        else
+                        {
+                            mtCOVERAGE_TEST_MARKER();
+                        }
+
+                        if( xBreakLoop != pdFALSE )
+                        {
+                            break;
+                        }
+                    }
+
+                    if( pxReturn != NULL )
+                    {
+                        /* The handle has been found. */
                         break;
                     }
                 }
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
 
-                if( pxReturn != NULL )
-                {
-                    /* The handle has been found. */
-                    break;
-                }
-            } while( pxNextTCB != pxFirstTCB );
+            return pxReturn;
         }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
-        }
-
-        return pxReturn;
-    }
+    #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
 
 #endif /* INCLUDE_xTaskGetHandle */
 /*-----------------------------------------------------------*/
@@ -2622,12 +4028,14 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char
 
 #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
 
+/* SMP_TODO : This function returns only idle task handle for core 0.
+ * Consider to add another function to return the idle task handles. */
     TaskHandle_t xTaskGetIdleTaskHandle( void )
     {
         /* If xTaskGetIdleTaskHandle() is called before the scheduler has been
-         * started, then xIdleTaskHandle will be NULL. */
-        configASSERT( ( xIdleTaskHandle != NULL ) );
-        return xIdleTaskHandle;
+         * started, then xIdleTaskHandles will be NULL. */
+        configASSERT( ( xIdleTaskHandles[ 0 ] != NULL ) );
+        return xIdleTaskHandles[ 0 ];
     }
 
 #endif /* INCLUDE_xTaskGetIdleTaskHandle */
@@ -2749,21 +4157,33 @@ BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp )
                  * switch if preemption is turned off. */
                 #if ( configUSE_PREEMPTION == 1 )
                 {
-                    /* Preemption is on, but a context switch should only be
-                     * performed if the unblocked task has a priority that is
-                     * higher than the currently executing task. */
-                    if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+                    #if ( configNUMBER_OF_CORES == 1 )
                     {
-                        /* Pend the yield to be performed when the scheduler
-                         * is unsuspended. */
-                        xYieldPending = pdTRUE;
+                        /* Preemption is on, but a context switch should only be
+                         * performed if the unblocked task has a priority that is
+                         * higher than the currently executing task. */
+                        if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+                        {
+                            /* Pend the yield to be performed when the scheduler
+                             * is unsuspended. */
+                            xYieldPendings[ 0 ] = pdTRUE;
+                        }
+                        else
+                        {
+                            mtCOVERAGE_TEST_MARKER();
+                        }
                     }
-                    else
+                    #else /* #if ( configNUMBER_OF_CORES == 1 ) */
                     {
-                        mtCOVERAGE_TEST_MARKER();
+                        taskENTER_CRITICAL();
+                        {
+                            prvYieldForTask( pxTCB );
+                        }
+                        taskEXIT_CRITICAL();
                     }
+                    #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
                 }
-                #endif /* configUSE_PREEMPTION */
+                #endif /* #if ( configUSE_PREEMPTION == 1 ) */
             }
             else
             {
@@ -2784,11 +4204,19 @@ BaseType_t xTaskIncrementTick( void )
     TickType_t xItemValue;
     BaseType_t xSwitchRequired = pdFALSE;
 
+    #if ( configUSE_PREEMPTION == 1 ) && ( configNUMBER_OF_CORES > 1 )
+    BaseType_t xYieldRequiredForCore[ configNUMBER_OF_CORES ] = { pdFALSE };
+    #endif /* #if ( configUSE_PREEMPTION == 1 ) && ( configNUMBER_OF_CORES > 1 ) */
+
     /* Called by the portable layer each time a tick interrupt occurs.
      * Increments the tick then checks to see if the new tick value will cause any
      * tasks to be unblocked. */
     traceTASK_INCREMENT_TICK( xTickCount );
 
+    /* Tick increment should occur on every kernel timer event. Core 0 has the
+     * responsibility to increment the tick, or increment the pended ticks if the
+     * scheduler is suspended.  If pended ticks is greater than zero, the core that
+     * calls xTaskResumeAll has the responsibility to increment the tick. */
     if( uxSchedulerSuspended == ( UBaseType_t ) 0U )
     {
         /* Minor optimisation.  The tick count cannot change in this
@@ -2872,24 +4300,32 @@ BaseType_t xTaskIncrementTick( void )
                      * context switch if preemption is turned off. */
                     #if ( configUSE_PREEMPTION == 1 )
                     {
-                        /* Preemption is on, but a context switch should
-                         * only be performed if the unblocked task's
-                         * priority is higher than the currently executing
-                         * task.
-                         * The case of equal priority tasks sharing
-                         * processing time (which happens when both
-                         * preemption and time slicing are on) is
-                         * handled below.*/
-                        if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+                        #if ( configNUMBER_OF_CORES == 1 )
                         {
-                            xSwitchRequired = pdTRUE;
+                            /* Preemption is on, but a context switch should
+                             * only be performed if the unblocked task's
+                             * priority is higher than the currently executing
+                             * task.
+                             * The case of equal priority tasks sharing
+                             * processing time (which happens when both
+                             * preemption and time slicing are on) is
+                             * handled below.*/
+                            if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+                            {
+                                xSwitchRequired = pdTRUE;
+                            }
+                            else
+                            {
+                                mtCOVERAGE_TEST_MARKER();
+                            }
                         }
-                        else
+                        #else /* #if( configNUMBER_OF_CORES == 1 ) */
                         {
-                            mtCOVERAGE_TEST_MARKER();
+                            prvYieldForTask( pxTCB );
                         }
+                        #endif /* #if( configNUMBER_OF_CORES == 1 ) */
                     }
-                    #endif /* configUSE_PREEMPTION */
+                    #endif /* #if ( configUSE_PREEMPTION == 1 ) */
                 }
             }
         }
@@ -2899,16 +4335,36 @@ BaseType_t xTaskIncrementTick( void )
          * writer has not explicitly turned time slicing off. */
         #if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) )
         {
-            if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 )
+            #if ( configNUMBER_OF_CORES == 1 )
             {
-                xSwitchRequired = pdTRUE;
+                if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 )
+                {
+                    xSwitchRequired = pdTRUE;
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
             }
-            else
+            #else /* #if ( configNUMBER_OF_CORES == 1 ) */
             {
-                mtCOVERAGE_TEST_MARKER();
+                BaseType_t xCoreID;
+
+                for( xCoreID = 0; xCoreID < ( ( BaseType_t ) configNUMBER_OF_CORES ); xCoreID++ )
+                {
+                    if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCBs[ xCoreID ]->uxPriority ] ) ) > 1 )
+                    {
+                        xYieldRequiredForCore[ xCoreID ] = pdTRUE;
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+                }
             }
+            #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
         }
-        #endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) */
+        #endif /* #if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) */
 
         #if ( configUSE_TICK_HOOK == 1 )
         {
@@ -2927,16 +4383,50 @@ BaseType_t xTaskIncrementTick( void )
 
         #if ( configUSE_PREEMPTION == 1 )
         {
-            if( xYieldPending != pdFALSE )
+            #if ( configNUMBER_OF_CORES == 1 )
             {
-                xSwitchRequired = pdTRUE;
+                /* For single core the core ID is always 0. */
+                if( xYieldPendings[ 0 ] != pdFALSE )
+                {
+                    xSwitchRequired = pdTRUE;
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
             }
-            else
+            #else /* #if ( configNUMBER_OF_CORES == 1 ) */
             {
-                mtCOVERAGE_TEST_MARKER();
+                BaseType_t xCoreID, xCurrentCoreID;
+                xCurrentCoreID = portGET_CORE_ID();
+
+                for( xCoreID = 0; xCoreID < ( BaseType_t ) configNUMBER_OF_CORES; xCoreID++ )
+                {
+                    #if ( configUSE_TASK_PREEMPTION_DISABLE == 1 )
+                        if( pxCurrentTCBs[ xCoreID ]->xPreemptionDisable == pdFALSE )
+                    #endif
+                    {
+                        if( ( xYieldRequiredForCore[ xCoreID ] != pdFALSE ) || ( xYieldPendings[ xCoreID ] != pdFALSE ) )
+                        {
+                            if( xCoreID == xCurrentCoreID )
+                            {
+                                xSwitchRequired = pdTRUE;
+                            }
+                            else
+                            {
+                                prvYieldCore( xCoreID );
+                            }
+                        }
+                        else
+                        {
+                            mtCOVERAGE_TEST_MARKER();
+                        }
+                    }
+                }
             }
+            #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
         }
-        #endif /* configUSE_PREEMPTION */
+        #endif /* #if ( configUSE_PREEMPTION == 1 ) */
     }
     else
     {
@@ -3022,11 +4512,11 @@ BaseType_t xTaskIncrementTick( void )
 
         /* Save the hook function in the TCB.  A critical section is required as
          * the value can be accessed from an interrupt. */
-        uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+        uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
         {
             xReturn = pxTCB->pxTaskTag;
         }
-        portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+        taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
 
         return xReturn;
     }
@@ -3067,78 +4557,171 @@ BaseType_t xTaskIncrementTick( void )
 #endif /* configUSE_APPLICATION_TASK_TAG */
 /*-----------------------------------------------------------*/
 
-void vTaskSwitchContext( void )
-{
-    if( uxSchedulerSuspended != ( UBaseType_t ) 0U )
+#if ( configNUMBER_OF_CORES == 1 )
+    void vTaskSwitchContext( void )
     {
-        /* The scheduler is currently suspended - do not allow a context
-         * switch. */
-        xYieldPending = pdTRUE;
-    }
-    else
-    {
-        xYieldPending = pdFALSE;
-        traceTASK_SWITCHED_OUT();
-
-        #if ( configGENERATE_RUN_TIME_STATS == 1 )
+        if( uxSchedulerSuspended != ( UBaseType_t ) 0U )
         {
-            #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
-                portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalRunTime );
-            #else
-                ulTotalRunTime = ( configRUN_TIME_COUNTER_TYPE ) portGET_RUN_TIME_COUNTER_VALUE();
+            /* The scheduler is currently suspended - do not allow a context
+             * switch. */
+            xYieldPendings[ 0 ] = pdTRUE;
+        }
+        else
+        {
+            xYieldPendings[ 0 ] = pdFALSE;
+            traceTASK_SWITCHED_OUT();
+
+            #if ( configGENERATE_RUN_TIME_STATS == 1 )
+            {
+                #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
+                    portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalRunTime[ 0 ] );
+                #else
+                    ulTotalRunTime[ 0 ] = portGET_RUN_TIME_COUNTER_VALUE();
+                #endif
+
+                /* Add the amount of time the task has been running to the
+                 * accumulated time so far.  The time the task started running was
+                 * stored in ulTaskSwitchedInTime.  Note that there is no overflow
+                 * protection here so count values are only valid until the timer
+                 * overflows.  The guard against negative values is to protect
+                 * against suspect run time stat counter implementations - which
+                 * are provided by the application, not the kernel. */
+                if( ulTotalRunTime[ 0 ] > ulTaskSwitchedInTime[ 0 ] )
+                {
+                    pxCurrentTCB->ulRunTimeCounter += ( ulTotalRunTime[ 0 ] - ulTaskSwitchedInTime[ 0 ] );
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+
+                ulTaskSwitchedInTime[ 0 ] = ulTotalRunTime[ 0 ];
+            }
+            #endif /* configGENERATE_RUN_TIME_STATS */
+
+            /* Check for stack overflow, if configured. */
+            taskCHECK_FOR_STACK_OVERFLOW();
+
+            /* Before the currently running task is switched out, save its errno. */
+            #if ( configUSE_POSIX_ERRNO == 1 )
+            {
+                pxCurrentTCB->iTaskErrno = FreeRTOS_errno;
+            }
             #endif
 
-            /* Add the amount of time the task has been running to the
-             * accumulated time so far.  The time the task started running was
-             * stored in ulTaskSwitchedInTime.  Note that there is no overflow
-             * protection here so count values are only valid until the timer
-             * overflows.  The guard against negative values is to protect
-             * against suspect run time stat counter implementations - which
-             * are provided by the application, not the kernel. */
-            if( ulTotalRunTime > ulTaskSwitchedInTime )
+            /* Select a new task to run using either the generic C or port
+             * optimised asm code. */
+            taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+            traceTASK_SWITCHED_IN();
+
+            /* After the new task is switched in, update the global errno. */
+            #if ( configUSE_POSIX_ERRNO == 1 )
             {
-                pxCurrentTCB->ulRunTimeCounter += ( ulTotalRunTime - ulTaskSwitchedInTime );
+                FreeRTOS_errno = pxCurrentTCB->iTaskErrno;
+            }
+            #endif
+
+            #if ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 )
+            {
+                /* Switch C-Runtime's TLS Block to point to the TLS
+                 * Block specific to this task. */
+                configSET_TLS_BLOCK( pxCurrentTCB->xTLSBlock );
+            }
+            #endif
+        }
+    }
+#else /* if ( configNUMBER_OF_CORES == 1 ) */
+    void vTaskSwitchContext( BaseType_t xCoreID )
+    {
+        /* Acquire both locks:
+         * - The ISR lock protects the ready list from simultaneous access by
+         *   both other ISRs and tasks.
+         * - We also take the task lock to pause here in case another core has
+         *   suspended the scheduler. We don't want to simply set xYieldPending
+         *   and move on if another core suspended the scheduler. We should only
+         *   do that if the current core has suspended the scheduler. */
+
+        portGET_TASK_LOCK(); /* Must always acquire the task lock first. */
+        portGET_ISR_LOCK();
+        {
+            /* vTaskSwitchContext() must never be called from within a critical section.
+             * This is not necessarily true for single core FreeRTOS, but it is for this
+             * SMP port. */
+            configASSERT( portGET_CRITICAL_NESTING_COUNT() == 0 );
+
+            if( uxSchedulerSuspended != ( UBaseType_t ) 0U )
+            {
+                /* The scheduler is currently suspended - do not allow a context
+                 * switch. */
+                xYieldPendings[ xCoreID ] = pdTRUE;
             }
             else
             {
-                mtCOVERAGE_TEST_MARKER();
+                xYieldPendings[ xCoreID ] = pdFALSE;
+                traceTASK_SWITCHED_OUT();
+
+                #if ( configGENERATE_RUN_TIME_STATS == 1 )
+                {
+                    #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
+                        portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalRunTime[ xCoreID ] );
+                    #else
+                        ulTotalRunTime[ xCoreID ] = portGET_RUN_TIME_COUNTER_VALUE();
+                    #endif
+
+                    /* Add the amount of time the task has been running to the
+                     * accumulated time so far.  The time the task started running was
+                     * stored in ulTaskSwitchedInTime.  Note that there is no overflow
+                     * protection here so count values are only valid until the timer
+                     * overflows.  The guard against negative values is to protect
+                     * against suspect run time stat counter implementations - which
+                     * are provided by the application, not the kernel. */
+                    if( ulTotalRunTime[ xCoreID ] > ulTaskSwitchedInTime[ xCoreID ] )
+                    {
+                        pxCurrentTCB->ulRunTimeCounter += ( ulTotalRunTime[ xCoreID ] - ulTaskSwitchedInTime[ xCoreID ] );
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+
+                    ulTaskSwitchedInTime[ xCoreID ] = ulTotalRunTime[ xCoreID ];
+                }
+                #endif /* configGENERATE_RUN_TIME_STATS */
+
+                /* Check for stack overflow, if configured. */
+                taskCHECK_FOR_STACK_OVERFLOW();
+
+                /* Before the currently running task is switched out, save its errno. */
+                #if ( configUSE_POSIX_ERRNO == 1 )
+                {
+                    pxCurrentTCB->iTaskErrno = FreeRTOS_errno;
+                }
+                #endif
+
+                /* Select a new task to run. */
+                prvSelectHighestPriorityTask( xCoreID );
+                traceTASK_SWITCHED_IN();
+
+                /* After the new task is switched in, update the global errno. */
+                #if ( configUSE_POSIX_ERRNO == 1 )
+                {
+                    FreeRTOS_errno = pxCurrentTCB->iTaskErrno;
+                }
+                #endif
+
+                #if ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 )
+                {
+                    /* Switch C-Runtime's TLS Block to point to the TLS
+                     * Block specific to this task. */
+                    configSET_TLS_BLOCK( pxCurrentTCB->xTLSBlock );
+                }
+                #endif
             }
-
-            ulTaskSwitchedInTime = ulTotalRunTime;
         }
-        #endif /* configGENERATE_RUN_TIME_STATS */
-
-        /* Check for stack overflow, if configured. */
-        taskCHECK_FOR_STACK_OVERFLOW();
-
-        /* Before the currently running task is switched out, save its errno. */
-        #if ( configUSE_POSIX_ERRNO == 1 )
-        {
-            pxCurrentTCB->iTaskErrno = FreeRTOS_errno;
-        }
-        #endif
-
-        /* Select a new task to run using either the generic C or port
-         * optimised asm code. */
-        taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
-        traceTASK_SWITCHED_IN();
-
-        /* After the new task is switched in, update the global errno. */
-        #if ( configUSE_POSIX_ERRNO == 1 )
-        {
-            FreeRTOS_errno = pxCurrentTCB->iTaskErrno;
-        }
-        #endif
-
-        #if ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 )
-        {
-            /* Switch C-Runtime's TLS Block to point to the TLS
-             * Block specific to this task. */
-            configSET_TLS_BLOCK( pxCurrentTCB->xTLSBlock );
-        }
-        #endif
+        portRELEASE_ISR_LOCK();
+        portRELEASE_TASK_LOCK();
     }
-}
+#endif /* if ( configNUMBER_OF_CORES > 1 ) */
 /*-----------------------------------------------------------*/
 
 void vTaskPlaceOnEventList( List_t * const pxEventList,
@@ -3275,21 +4858,40 @@ BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList )
         listINSERT_END( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) );
     }
 
-    if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
+    #if ( configNUMBER_OF_CORES == 1 )
     {
-        /* Return true if the task removed from the event list has a higher
-         * priority than the calling task.  This allows the calling task to know if
-         * it should force a context switch now. */
-        xReturn = pdTRUE;
+        if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
+        {
+            /* Return true if the task removed from the event list has a higher
+             * priority than the calling task.  This allows the calling task to know if
+             * it should force a context switch now. */
+            xReturn = pdTRUE;
 
-        /* Mark that a yield is pending in case the user is not using the
-         * "xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */
-        xYieldPending = pdTRUE;
+            /* Mark that a yield is pending in case the user is not using the
+             * "xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */
+            xYieldPendings[ 0 ] = pdTRUE;
+        }
+        else
+        {
+            xReturn = pdFALSE;
+        }
     }
-    else
+    #else /* #if ( configNUMBER_OF_CORES == 1 ) */
     {
         xReturn = pdFALSE;
+
+        #if ( configUSE_PREEMPTION == 1 )
+        {
+            prvYieldForTask( pxUnblockedTCB );
+
+            if( xYieldPendings[ portGET_CORE_ID() ] != pdFALSE )
+            {
+                xReturn = pdTRUE;
+            }
+        }
+        #endif /* #if ( configUSE_PREEMPTION == 1 ) */
     }
+    #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
 
     return xReturn;
 }
@@ -3333,14 +4935,30 @@ void vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem,
     listREMOVE_ITEM( &( pxUnblockedTCB->xStateListItem ) );
     prvAddTaskToReadyList( pxUnblockedTCB );
 
-    if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
+    #if ( configNUMBER_OF_CORES == 1 )
     {
-        /* The unblocked task has a priority above that of the calling task, so
-         * a context switch is required.  This function is called with the
-         * scheduler suspended so xYieldPending is set so the context switch
-         * occurs immediately that the scheduler is resumed (unsuspended). */
-        xYieldPending = pdTRUE;
+        if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
+        {
+            /* The unblocked task has a priority above that of the calling task, so
+             * a context switch is required.  This function is called with the
+             * scheduler suspended so xYieldPending is set so the context switch
+             * occurs immediately that the scheduler is resumed (unsuspended). */
+            xYieldPendings[ 0 ] = pdTRUE;
+        }
     }
+    #else /* #if ( configNUMBER_OF_CORES == 1 ) */
+    {
+        #if ( configUSE_PREEMPTION == 1 )
+        {
+            taskENTER_CRITICAL();
+            {
+                prvYieldForTask( pxUnblockedTCB );
+            }
+            taskEXIT_CRITICAL();
+        }
+        #endif
+    }
+    #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
 }
 /*-----------------------------------------------------------*/
 
@@ -3431,7 +5049,8 @@ BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
 
 void vTaskMissedYield( void )
 {
-    xYieldPending = pdTRUE;
+    /* Must be called from within a critical section. */
+    xYieldPendings[ portGET_CORE_ID() ] = pdTRUE;
 }
 /*-----------------------------------------------------------*/
 
@@ -3473,6 +5092,81 @@ void vTaskMissedYield( void )
     }
 
 #endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+/*
+ * -----------------------------------------------------------
+ * The MinimalIdle task.
+ * ----------------------------------------------------------
+ *
+ * The minimal idle task is used for all the additional cores in a SMP
+ * system. There must be only 1 idle task and the rest are minimal idle
+ * tasks.
+ *
+ * The portTASK_FUNCTION() macro is used to allow port/compiler specific
+ * language extensions.  The equivalent prototype for this function is:
+ *
+ * void prvMinimalIdleTask( void *pvParameters );
+ */
+
+#if ( configNUMBER_OF_CORES > 1 )
+    static portTASK_FUNCTION( prvMinimalIdleTask, pvParameters )
+    {
+        ( void ) pvParameters;
+
+        taskYIELD();
+
+        while( INFINITE_LOOP() )
+        {
+            #if ( configUSE_PREEMPTION == 0 )
+            {
+                /* If we are not using preemption we keep forcing a task switch to
+                 * see if any other task has become available.  If we are using
+                 * preemption we don't need to do this as any task becoming available
+                 * will automatically get the processor anyway. */
+                taskYIELD();
+            }
+            #endif /* configUSE_PREEMPTION */
+
+            #if ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) )
+            {
+                /* When using preemption tasks of equal priority will be
+                 * timesliced.  If a task that is sharing the idle priority is ready
+                 * to run then the idle task should yield before the end of the
+                 * timeslice.
+                 *
+                 * A critical region is not required here as we are just reading from
+                 * the list, and an occasional incorrect value will not matter.  If
+                 * the ready list at the idle priority contains one more task than the
+                 * number of idle tasks, which is equal to the configured numbers of cores
+                 * then a task other than the idle task is ready to execute. */
+                if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) configNUMBER_OF_CORES )
+                {
+                    taskYIELD();
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            #endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) ) */
+
+            #if ( configUSE_MINIMAL_IDLE_HOOK == 1 )
+            {
+                /* Call the user defined function from within the idle task.  This
+                 * allows the application designer to add background functionality
+                 * without the overhead of a separate task.
+                 *
+                 * This hook is intended to manage core activity such as disabling cores that go idle.
+                 *
+                 * NOTE: vApplicationMinimalIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES,
+                 * CALL A FUNCTION THAT MIGHT BLOCK. */
+                vApplicationMinimalIdleHook();
+            }
+            #endif /* configUSE_MINIMAL_IDLE_HOOK */
+        }
+    }
+#endif /* #if ( configNUMBER_OF_CORES > 1 ) */
 
 /*
  * -----------------------------------------------------------
@@ -3499,7 +5193,15 @@ static portTASK_FUNCTION( prvIdleTask, pvParameters )
      * any. */
     portALLOCATE_SECURE_CONTEXT( configMINIMAL_SECURE_STACK_SIZE );
 
-    for( ; ; )
+    #if ( configNUMBER_OF_CORES > 1 )
+    {
+        /* SMP all cores start up in the idle task. This initial yield gets the application
+         * tasks started. */
+        taskYIELD();
+    }
+    #endif /* #if ( configNUMBER_OF_CORES > 1 ) */
+
+    while( INFINITE_LOOP() )
     {
         /* See if any tasks have deleted themselves - if so then the idle task
          * is responsible for freeing the deleted task's TCB and stack. */
@@ -3524,9 +5226,10 @@ static portTASK_FUNCTION( prvIdleTask, pvParameters )
              *
              * A critical region is not required here as we are just reading from
              * the list, and an occasional incorrect value will not matter.  If
-             * the ready list at the idle priority contains more than one task
+             * the ready list at the idle priority contains one more task than the
+             * number of idle tasks, which is equal to the configured numbers of cores
              * then a task other than the idle task is ready to execute. */
-            if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 )
+            if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) configNUMBER_OF_CORES )
             {
                 taskYIELD();
             }
@@ -3593,6 +5296,20 @@ static portTASK_FUNCTION( prvIdleTask, pvParameters )
             }
         }
         #endif /* configUSE_TICKLESS_IDLE */
+
+        #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_MINIMAL_IDLE_HOOK == 1 ) )
+        {
+            /* Call the user defined function from within the idle task.  This
+             * allows the application designer to add background functionality
+             * without the overhead of a separate task.
+             *
+             * This hook is intended to manage core activity such as disabling cores that go idle.
+             *
+             * NOTE: vApplicationMinimalIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES,
+             * CALL A FUNCTION THAT MIGHT BLOCK. */
+            vApplicationMinimalIdleHook();
+        }
+        #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_MINIMAL_IDLE_HOOK == 1 ) ) */
     }
 }
 /*-----------------------------------------------------------*/
@@ -3615,7 +5332,7 @@ static portTASK_FUNCTION( prvIdleTask, pvParameters )
             /* A task was made ready while the scheduler was suspended. */
             eReturn = eAbortSleep;
         }
-        else if( xYieldPending != pdFALSE )
+        else if( xYieldPendings[ portGET_CORE_ID() ] != pdFALSE )
         {
             /* A yield was pended while the scheduler was suspended. */
             eReturn = eAbortSleep;
@@ -3657,7 +5374,7 @@ static portTASK_FUNCTION( prvIdleTask, pvParameters )
         TCB_t * pxTCB;
 
         if( ( xIndex >= 0 ) &&
-            ( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS ) )
+            ( xIndex < ( BaseType_t ) configNUM_THREAD_LOCAL_STORAGE_POINTERS ) )
         {
             pxTCB = prvGetTCBFromHandle( xTaskToSet );
             configASSERT( pxTCB != NULL );
@@ -3677,7 +5394,7 @@ static portTASK_FUNCTION( prvIdleTask, pvParameters )
         TCB_t * pxTCB;
 
         if( ( xIndex >= 0 ) &&
-            ( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS ) )
+            ( xIndex < ( BaseType_t ) configNUM_THREAD_LOCAL_STORAGE_POINTERS ) )
         {
             pxTCB = prvGetTCBFromHandle( xTaskToQuery );
             pvReturn = pxTCB->pvThreadLocalStoragePointers[ xIndex ];
@@ -3696,7 +5413,7 @@ static portTASK_FUNCTION( prvIdleTask, pvParameters )
 #if ( portUSING_MPU_WRAPPERS == 1 )
 
     void vTaskAllocateMPURegions( TaskHandle_t xTaskToModify,
-                                  const MemoryRegion_t * const xRegions )
+                                  const MemoryRegion_t * const pxRegions )
     {
         TCB_t * pxTCB;
 
@@ -3704,7 +5421,7 @@ static portTASK_FUNCTION( prvIdleTask, pvParameters )
          * the calling task. */
         pxTCB = prvGetTCBFromHandle( xTaskToModify );
 
-        vPortStoreTaskMPUSettings( &( pxTCB->xMPUSettings ), xRegions, NULL, 0 );
+        vPortStoreTaskMPUSettings( &( pxTCB->xMPUSettings ), pxRegions, NULL, 0 );
     }
 
 #endif /* portUSING_MPU_WRAPPERS */
@@ -3754,16 +5471,58 @@ static void prvCheckTasksWaitingTermination( void )
          * being called too often in the idle task. */
         while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
         {
-            taskENTER_CRITICAL();
+            #if ( configNUMBER_OF_CORES == 1 )
             {
-                pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
-                ( void ) uxListRemove( &( pxTCB->xStateListItem ) );
-                --uxCurrentNumberOfTasks;
-                --uxDeletedTasksWaitingCleanUp;
-            }
-            taskEXIT_CRITICAL();
+                taskENTER_CRITICAL();
+                {
+                    {
+                        pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+                        ( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+                        --uxCurrentNumberOfTasks;
+                        --uxDeletedTasksWaitingCleanUp;
+                    }
+                }
+                taskEXIT_CRITICAL();
 
-            prvDeleteTCB( pxTCB );
+                prvDeleteTCB( pxTCB );
+            }
+            #else /* #if( configNUMBER_OF_CORES == 1 ) */
+            {
+                pxTCB = NULL;
+
+                taskENTER_CRITICAL();
+                {
+                    /* For SMP, multiple idles can be running simultaneously
+                     * and we need to check that other idles did not cleanup while we were
+                     * waiting to enter the critical section. */
+                    if( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
+                    {
+                        pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+
+                        if( pxTCB->xTaskRunState == taskTASK_NOT_RUNNING )
+                        {
+                            ( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+                            --uxCurrentNumberOfTasks;
+                            --uxDeletedTasksWaitingCleanUp;
+                        }
+                        else
+                        {
+                            /* The TCB to be deleted still has not yet been switched out
+                             * by the scheduler, so we will just exit this loop early and
+                             * try again next time. */
+                            taskEXIT_CRITICAL();
+                            break;
+                        }
+                    }
+                }
+                taskEXIT_CRITICAL();
+
+                if( pxTCB != NULL )
+                {
+                    prvDeleteTCB( pxTCB );
+                }
+            }
+            #endif /* #if( configNUMBER_OF_CORES == 1 ) */
         }
     }
     #endif /* INCLUDE_vTaskDelete */
@@ -3792,6 +5551,12 @@ static void prvCheckTasksWaitingTermination( void )
         #endif
         pxTaskStatus->xTaskNumber = pxTCB->uxTCBNumber;
 
+        #if ( ( configUSE_CORE_AFFINITY == 1 ) && ( configNUMBER_OF_CORES > 1 ) )
+        {
+            pxTaskStatus->uxCoreAffinityMask = pxTCB->uxCoreAffinityMask;
+        }
+        #endif
+
         #if ( configUSE_MUTEXES == 1 )
         {
             pxTaskStatus->uxBasePriority = pxTCB->uxBasePriority;
@@ -3817,7 +5582,7 @@ static void prvCheckTasksWaitingTermination( void )
          * state is just set to whatever is passed in. */
         if( eState != eInvalid )
         {
-            if( pxTCB == pxCurrentTCB )
+            if( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE )
             {
                 pxTaskStatus->eCurrentState = eRunning;
             }
@@ -4021,7 +5786,7 @@ static void prvCheckTasksWaitingTermination( void )
         #if ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 )
         {
             /* Free up the memory allocated for the task's TLS Block. */
-            configDEINIT_TLS_BLOCK( pxCurrentTCB->xTLSBlock );
+            configDEINIT_TLS_BLOCK( pxTCB->xTLSBlock );
         }
         #endif
 
@@ -4085,19 +5850,47 @@ static void prvResetNextTaskUnblockTime( void )
 }
 /*-----------------------------------------------------------*/
 
-#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
+#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) || ( configNUMBER_OF_CORES > 1 )
 
-    TaskHandle_t xTaskGetCurrentTaskHandle( void )
-    {
-        TaskHandle_t xReturn;
+    #if ( configNUMBER_OF_CORES == 1 )
+        TaskHandle_t xTaskGetCurrentTaskHandle( void )
+        {
+            TaskHandle_t xReturn;
 
-        /* A critical section is not required as this is not called from
-         * an interrupt and the current TCB will always be the same for any
-         * individual execution thread. */
-        xReturn = pxCurrentTCB;
+            /* A critical section is not required as this is not called from
+             * an interrupt and the current TCB will always be the same for any
+             * individual execution thread. */
+            xReturn = pxCurrentTCB;
 
-        return xReturn;
-    }
+            return xReturn;
+        }
+    #else /* #if ( configNUMBER_OF_CORES == 1 ) */
+        TaskHandle_t xTaskGetCurrentTaskHandle( void )
+        {
+            TaskHandle_t xReturn;
+            UBaseType_t uxSavedInterruptStatus;
+
+            uxSavedInterruptStatus = portSET_INTERRUPT_MASK();
+            {
+                xReturn = pxCurrentTCBs[ portGET_CORE_ID() ];
+            }
+            portCLEAR_INTERRUPT_MASK( uxSavedInterruptStatus );
+
+            return xReturn;
+        }
+
+        TaskHandle_t xTaskGetCurrentTaskHandleCPU( BaseType_t xCoreID )
+        {
+            TaskHandle_t xReturn = NULL;
+
+            if( taskVALID_CORE_ID( xCoreID ) != pdFALSE )
+            {
+                xReturn = pxCurrentTCBs[ xCoreID ];
+            }
+
+            return xReturn;
+        }
+    #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
 
 #endif /* ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
 /*-----------------------------------------------------------*/
@@ -4114,14 +5907,22 @@ static void prvResetNextTaskUnblockTime( void )
         }
         else
         {
-            if( uxSchedulerSuspended == ( UBaseType_t ) 0U )
+            #if ( configNUMBER_OF_CORES > 1 )
+                taskENTER_CRITICAL();
+            #endif
             {
-                xReturn = taskSCHEDULER_RUNNING;
-            }
-            else
-            {
-                xReturn = taskSCHEDULER_SUSPENDED;
+                if( uxSchedulerSuspended == ( UBaseType_t ) 0U )
+                {
+                    xReturn = taskSCHEDULER_RUNNING;
+                }
+                else
+                {
+                    xReturn = taskSCHEDULER_SUSPENDED;
+                }
             }
+            #if ( configNUMBER_OF_CORES > 1 )
+                taskEXIT_CRITICAL();
+            #endif
         }
 
         return xReturn;
@@ -4178,6 +5979,16 @@ static void prvResetNextTaskUnblockTime( void )
                     /* Inherit the priority before being moved into the new list. */
                     pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
                     prvAddTaskToReadyList( pxMutexHolderTCB );
+                    #if ( configNUMBER_OF_CORES > 1 )
+                    {
+                        /* The priority of the task is raised. Yield for this task
+                         * if it is not running. */
+                        if( taskTASK_IS_RUNNING( pxMutexHolderTCB ) != pdTRUE )
+                        {
+                            prvYieldForTask( pxMutexHolderTCB );
+                        }
+                    }
+                    #endif /* if ( configNUMBER_OF_CORES > 1 ) */
                 }
                 else
                 {
@@ -4268,6 +6079,16 @@ static void prvResetNextTaskUnblockTime( void )
                      * running to give back the mutex. */
                     listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
                     prvAddTaskToReadyList( pxTCB );
+                    #if ( configNUMBER_OF_CORES > 1 )
+                    {
+                        /* The priority of the task is dropped. Yield the core on
+                         * which the task is running. */
+                        if( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE )
+                        {
+                            prvYieldCore( pxTCB->xTaskRunState );
+                        }
+                    }
+                    #endif /* if ( configNUMBER_OF_CORES > 1 ) */
 
                     /* Return true to indicate that a context switch is required.
                      * This is only actually required in the corner case whereby
@@ -4381,6 +6202,16 @@ static void prvResetNextTaskUnblockTime( void )
                         }
 
                         prvAddTaskToReadyList( pxTCB );
+                        #if ( configNUMBER_OF_CORES > 1 )
+                        {
+                            /* The priority of the task is dropped. Yield the core on
+                             * which the task is running. */
+                            if( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE )
+                            {
+                                prvYieldCore( pxTCB->xTaskRunState );
+                            }
+                        }
+                        #endif /* if ( configNUMBER_OF_CORES > 1 ) */
                     }
                     else
                     {
@@ -4406,7 +6237,28 @@ static void prvResetNextTaskUnblockTime( void )
 #endif /* configUSE_MUTEXES */
 /*-----------------------------------------------------------*/
 
-#if ( portCRITICAL_NESTING_IN_TCB == 1 )
+#if ( configNUMBER_OF_CORES > 1 )
+
+/* If not in a critical section then yield immediately.
+ * Otherwise set xYieldPendings to true to wait to
+ * yield until exiting the critical section.
+ */
+    void vTaskYieldWithinAPI( void )
+    {
+        if( portGET_CRITICAL_NESTING_COUNT() == 0U )
+        {
+            portYIELD();
+        }
+        else
+        {
+            xYieldPendings[ portGET_CORE_ID() ] = pdTRUE;
+        }
+    }
+#endif /* #if ( configNUMBER_OF_CORES > 1 ) */
+
+/*-----------------------------------------------------------*/
+
+#if ( ( portCRITICAL_NESTING_IN_TCB == 1 ) && ( configNUMBER_OF_CORES == 1 ) )
 
     void vTaskEnterCritical( void )
     {
@@ -4433,15 +6285,97 @@ static void prvResetNextTaskUnblockTime( void )
         }
     }
 
-#endif /* portCRITICAL_NESTING_IN_TCB */
+#endif /* #if ( ( portCRITICAL_NESTING_IN_TCB == 1 ) && ( configNUMBER_OF_CORES == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( portCRITICAL_NESTING_IN_TCB == 1 )
+#if ( configNUMBER_OF_CORES > 1 )
+
+    void vTaskEnterCritical( void )
+    {
+        portDISABLE_INTERRUPTS();
+
+        if( xSchedulerRunning != pdFALSE )
+        {
+            if( portGET_CRITICAL_NESTING_COUNT() == 0U )
+            {
+                portGET_TASK_LOCK();
+                portGET_ISR_LOCK();
+            }
+
+            portINCREMENT_CRITICAL_NESTING_COUNT();
+
+            /* This is not the interrupt safe version of the enter critical
+             * function so  assert() if it is being called from an interrupt
+             * context.  Only API functions that end in "FromISR" can be used in an
+             * interrupt.  Only assert if the critical nesting count is 1 to
+             * protect against recursive calls if the assert function also uses a
+             * critical section. */
+            if( portGET_CRITICAL_NESTING_COUNT() == 1U )
+            {
+                portASSERT_IF_IN_ISR();
+
+                if( uxSchedulerSuspended == 0U )
+                {
+                    /* The only time there would be a problem is if this is called
+                     * before a context switch and vTaskExitCritical() is called
+                     * after pxCurrentTCB changes. Therefore this should not be
+                     * used within vTaskSwitchContext(). */
+                    prvCheckForRunStateChange();
+                }
+            }
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+
+#endif /* #if ( configNUMBER_OF_CORES > 1 ) */
+
+/*-----------------------------------------------------------*/
+
+#if ( configNUMBER_OF_CORES > 1 )
+
+    UBaseType_t vTaskEnterCriticalFromISR( void )
+    {
+        UBaseType_t uxSavedInterruptStatus = 0;
+
+        if( xSchedulerRunning != pdFALSE )
+        {
+            uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+
+            if( portGET_CRITICAL_NESTING_COUNT() == 0U )
+            {
+                portGET_ISR_LOCK();
+            }
+
+            portINCREMENT_CRITICAL_NESTING_COUNT();
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        return uxSavedInterruptStatus;
+    }
+
+#endif /* #if ( configNUMBER_OF_CORES > 1 ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( portCRITICAL_NESTING_IN_TCB == 1 ) && ( configNUMBER_OF_CORES == 1 ) )
 
     void vTaskExitCritical( void )
     {
         if( xSchedulerRunning != pdFALSE )
         {
+            /* If pxCurrentTCB->uxCriticalNesting is zero then this function
+             * does not match a previous call to vTaskEnterCritical(). */
+            configASSERT( pxCurrentTCB->uxCriticalNesting > 0U );
+
+            /* This function should not be called in ISR. Use vTaskExitCriticalFromISR
+             * to exit critical section from ISR. */
+            portASSERT_IF_IN_ISR();
+
             if( pxCurrentTCB->uxCriticalNesting > 0U )
             {
                 ( pxCurrentTCB->uxCriticalNesting )--;
@@ -4466,7 +6400,102 @@ static void prvResetNextTaskUnblockTime( void )
         }
     }
 
-#endif /* portCRITICAL_NESTING_IN_TCB */
+#endif /* #if ( ( portCRITICAL_NESTING_IN_TCB == 1 ) && ( configNUMBER_OF_CORES == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( configNUMBER_OF_CORES > 1 )
+
+    void vTaskExitCritical( void )
+    {
+        if( xSchedulerRunning != pdFALSE )
+        {
+            /* If critical nesting count is zero then this function
+             * does not match a previous call to vTaskEnterCritical(). */
+            configASSERT( portGET_CRITICAL_NESTING_COUNT() > 0U );
+
+            /* This function should not be called in ISR. Use vTaskExitCriticalFromISR
+             * to exit critical section from ISR. */
+            portASSERT_IF_IN_ISR();
+
+            if( portGET_CRITICAL_NESTING_COUNT() > 0U )
+            {
+                portDECREMENT_CRITICAL_NESTING_COUNT();
+
+                if( portGET_CRITICAL_NESTING_COUNT() == 0U )
+                {
+                    BaseType_t xYieldCurrentTask;
+
+                    /* Get the xYieldPending stats inside the critical section. */
+                    xYieldCurrentTask = xYieldPendings[ portGET_CORE_ID() ];
+
+                    portRELEASE_ISR_LOCK();
+                    portRELEASE_TASK_LOCK();
+                    portENABLE_INTERRUPTS();
+
+                    /* When a task yields in a critical section it just sets
+                     * xYieldPending to true. So now that we have exited the
+                     * critical section check if xYieldPending is true, and
+                     * if so yield. */
+                    if( xYieldCurrentTask != pdFALSE )
+                    {
+                        portYIELD();
+                    }
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+
+#endif /* #if ( configNUMBER_OF_CORES > 1 ) */
+/*-----------------------------------------------------------*/
+
+#if ( configNUMBER_OF_CORES > 1 )
+
+    void vTaskExitCriticalFromISR( UBaseType_t uxSavedInterruptStatus )
+    {
+        if( xSchedulerRunning != pdFALSE )
+        {
+            /* If critical nesting count is zero then this function
+             * does not match a previous call to vTaskEnterCritical(). */
+            configASSERT( portGET_CRITICAL_NESTING_COUNT() > 0U );
+
+            if( portGET_CRITICAL_NESTING_COUNT() > 0U )
+            {
+                portDECREMENT_CRITICAL_NESTING_COUNT();
+
+                if( portGET_CRITICAL_NESTING_COUNT() == 0U )
+                {
+                    portRELEASE_ISR_LOCK();
+                    portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+
+#endif /* #if ( configNUMBER_OF_CORES > 1 ) */
 /*-----------------------------------------------------------*/
 
 #if ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 )
@@ -4477,11 +6506,11 @@ static void prvResetNextTaskUnblockTime( void )
         size_t x;
 
         /* Start by copying the entire string. */
-        strcpy( pcBuffer, pcTaskName );
+        ( void ) strcpy( pcBuffer, pcTaskName );
 
         /* Pad the end of the string with spaces to ensure columns line up when
          * printed out. */
-        for( x = strlen( pcBuffer ); x < ( size_t ) ( configMAX_TASK_NAME_LEN - 1 ); x++ )
+        for( x = strlen( pcBuffer ); x < ( size_t ) ( ( size_t ) configMAX_TASK_NAME_LEN - 1U ); x++ )
         {
             pcBuffer[ x ] = ' ';
         }
@@ -4741,14 +6770,18 @@ TickType_t uxTaskResetEventItemValue( void )
 
     TaskHandle_t pvTaskIncrementMutexHeldCount( void )
     {
+        TCB_t * pxTCB;
+
+        pxTCB = pxCurrentTCB;
+
         /* If xSemaphoreCreateMutex() is called before any tasks have been created
          * then pxCurrentTCB will be NULL. */
-        if( pxCurrentTCB != NULL )
+        if( pxTCB != NULL )
         {
-            ( pxCurrentTCB->uxMutexesHeld )++;
+            ( pxTCB->uxMutexesHeld )++;
         }
 
-        return pxCurrentTCB;
+        return pxTCB;
     }
 
 #endif /* configUSE_MUTEXES */
@@ -4756,32 +6789,40 @@ TickType_t uxTaskResetEventItemValue( void )
 
 #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-    uint32_t ulTaskGenericNotifyTake( UBaseType_t uxIndexToWait,
+    uint32_t ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
                                       BaseType_t xClearCountOnExit,
                                       TickType_t xTicksToWait )
     {
         uint32_t ulReturn;
 
-        configASSERT( uxIndexToWait < configTASK_NOTIFICATION_ARRAY_ENTRIES );
+        configASSERT( uxIndexToWaitOn < configTASK_NOTIFICATION_ARRAY_ENTRIES );
 
         taskENTER_CRITICAL();
         {
             /* Only block if the notification count is not already non-zero. */
-            if( pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] == 0UL )
+            if( pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ] == 0UL )
             {
                 /* Mark this task as waiting for a notification. */
-                pxCurrentTCB->ucNotifyState[ uxIndexToWait ] = taskWAITING_NOTIFICATION;
+                pxCurrentTCB->ucNotifyState[ uxIndexToWaitOn ] = taskWAITING_NOTIFICATION;
 
                 if( xTicksToWait > ( TickType_t ) 0 )
                 {
                     prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
-                    traceTASK_NOTIFY_TAKE_BLOCK( uxIndexToWait );
+                    traceTASK_NOTIFY_TAKE_BLOCK( uxIndexToWaitOn );
 
                     /* All ports are written to allow a yield in a critical
                      * section (some will yield immediately, others wait until the
                      * critical section exits) - but it is not something that
                      * application code should ever do. */
-                    portYIELD_WITHIN_API();
+                    #if ( configNUMBER_OF_CORES == 1 )
+                    {
+                        portYIELD_WITHIN_API();
+                    }
+                    #else
+                    {
+                        vTaskYieldWithinAPI();
+                    }
+                    #endif
                 }
                 else
                 {
@@ -4797,18 +6838,18 @@ TickType_t uxTaskResetEventItemValue( void )
 
         taskENTER_CRITICAL();
         {
-            traceTASK_NOTIFY_TAKE( uxIndexToWait );
-            ulReturn = pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ];
+            traceTASK_NOTIFY_TAKE( uxIndexToWaitOn );
+            ulReturn = pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ];
 
             if( ulReturn != 0UL )
             {
                 if( xClearCountOnExit != pdFALSE )
                 {
-                    pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] = 0UL;
+                    pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ] = 0UL;
                 }
                 else
                 {
-                    pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] = ulReturn - ( uint32_t ) 1;
+                    pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ] = ulReturn - ( uint32_t ) 1;
                 }
             }
             else
@@ -4816,7 +6857,7 @@ TickType_t uxTaskResetEventItemValue( void )
                 mtCOVERAGE_TEST_MARKER();
             }
 
-            pxCurrentTCB->ucNotifyState[ uxIndexToWait ] = taskNOT_WAITING_NOTIFICATION;
+            pxCurrentTCB->ucNotifyState[ uxIndexToWaitOn ] = taskNOT_WAITING_NOTIFICATION;
         }
         taskEXIT_CRITICAL();
 
@@ -4828,7 +6869,7 @@ TickType_t uxTaskResetEventItemValue( void )
 
 #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-    BaseType_t xTaskGenericNotifyWait( UBaseType_t uxIndexToWait,
+    BaseType_t xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
                                        uint32_t ulBitsToClearOnEntry,
                                        uint32_t ulBitsToClearOnExit,
                                        uint32_t * pulNotificationValue,
@@ -4836,31 +6877,39 @@ TickType_t uxTaskResetEventItemValue( void )
     {
         BaseType_t xReturn;
 
-        configASSERT( uxIndexToWait < configTASK_NOTIFICATION_ARRAY_ENTRIES );
+        configASSERT( uxIndexToWaitOn < configTASK_NOTIFICATION_ARRAY_ENTRIES );
 
         taskENTER_CRITICAL();
         {
             /* Only block if a notification is not already pending. */
-            if( pxCurrentTCB->ucNotifyState[ uxIndexToWait ] != taskNOTIFICATION_RECEIVED )
+            if( pxCurrentTCB->ucNotifyState[ uxIndexToWaitOn ] != taskNOTIFICATION_RECEIVED )
             {
                 /* Clear bits in the task's notification value as bits may get
                  * set  by the notifying task or interrupt.  This can be used to
                  * clear the value to zero. */
-                pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] &= ~ulBitsToClearOnEntry;
+                pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ] &= ~ulBitsToClearOnEntry;
 
                 /* Mark this task as waiting for a notification. */
-                pxCurrentTCB->ucNotifyState[ uxIndexToWait ] = taskWAITING_NOTIFICATION;
+                pxCurrentTCB->ucNotifyState[ uxIndexToWaitOn ] = taskWAITING_NOTIFICATION;
 
                 if( xTicksToWait > ( TickType_t ) 0 )
                 {
                     prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
-                    traceTASK_NOTIFY_WAIT_BLOCK( uxIndexToWait );
+                    traceTASK_NOTIFY_WAIT_BLOCK( uxIndexToWaitOn );
 
                     /* All ports are written to allow a yield in a critical
                      * section (some will yield immediately, others wait until the
                      * critical section exits) - but it is not something that
                      * application code should ever do. */
-                    portYIELD_WITHIN_API();
+                    #if ( configNUMBER_OF_CORES == 1 )
+                    {
+                        portYIELD_WITHIN_API();
+                    }
+                    #else
+                    {
+                        vTaskYieldWithinAPI();
+                    }
+                    #endif
                 }
                 else
                 {
@@ -4876,20 +6925,20 @@ TickType_t uxTaskResetEventItemValue( void )
 
         taskENTER_CRITICAL();
         {
-            traceTASK_NOTIFY_WAIT( uxIndexToWait );
+            traceTASK_NOTIFY_WAIT( uxIndexToWaitOn );
 
             if( pulNotificationValue != NULL )
             {
                 /* Output the current notification value, which may or may not
                  * have changed. */
-                *pulNotificationValue = pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ];
+                *pulNotificationValue = pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ];
             }
 
             /* If ucNotifyValue is set then either the task never entered the
              * blocked state (because a notification was already pending) or the
              * task unblocked because of a notification.  Otherwise the task
              * unblocked because of a timeout. */
-            if( pxCurrentTCB->ucNotifyState[ uxIndexToWait ] != taskNOTIFICATION_RECEIVED )
+            if( pxCurrentTCB->ucNotifyState[ uxIndexToWaitOn ] != taskNOTIFICATION_RECEIVED )
             {
                 /* A notification was not received. */
                 xReturn = pdFALSE;
@@ -4898,11 +6947,11 @@ TickType_t uxTaskResetEventItemValue( void )
             {
                 /* A notification was already pending or a notification was
                  * received while the task was waiting. */
-                pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] &= ~ulBitsToClearOnExit;
+                pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ] &= ~ulBitsToClearOnExit;
                 xReturn = pdTRUE;
             }
 
-            pxCurrentTCB->ucNotifyState[ uxIndexToWait ] = taskNOT_WAITING_NOTIFICATION;
+            pxCurrentTCB->ucNotifyState[ uxIndexToWaitOn ] = taskNOT_WAITING_NOTIFICATION;
         }
         taskEXIT_CRITICAL();
 
@@ -5011,16 +7060,28 @@ TickType_t uxTaskResetEventItemValue( void )
                 }
                 #endif
 
-                if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+                #if ( configNUMBER_OF_CORES == 1 )
                 {
-                    /* The notified task has a priority above the currently
-                     * executing task so a yield is required. */
-                    taskYIELD_IF_USING_PREEMPTION();
+                    if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+                    {
+                        /* The notified task has a priority above the currently
+                         * executing task so a yield is required. */
+                        taskYIELD_IF_USING_PREEMPTION();
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
                 }
-                else
+                #else /* #if ( configNUMBER_OF_CORES == 1 ) */
                 {
-                    mtCOVERAGE_TEST_MARKER();
+                    #if ( configUSE_PREEMPTION == 1 )
+                    {
+                        prvYieldForTask( pxTCB );
+                    }
+                    #endif
                 }
+                #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
             }
             else
             {
@@ -5072,7 +7133,7 @@ TickType_t uxTaskResetEventItemValue( void )
 
         pxTCB = xTaskToNotify;
 
-        uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+        uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
         {
             if( pulPreviousNotificationValue != NULL )
             {
@@ -5146,27 +7207,47 @@ TickType_t uxTaskResetEventItemValue( void )
                     listINSERT_END( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
                 }
 
-                if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+                #if ( configNUMBER_OF_CORES == 1 )
                 {
-                    /* The notified task has a priority above the currently
-                     * executing task so a yield is required. */
-                    if( pxHigherPriorityTaskWoken != NULL )
+                    if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
                     {
-                        *pxHigherPriorityTaskWoken = pdTRUE;
-                    }
+                        /* The notified task has a priority above the currently
+                         * executing task so a yield is required. */
+                        if( pxHigherPriorityTaskWoken != NULL )
+                        {
+                            *pxHigherPriorityTaskWoken = pdTRUE;
+                        }
 
-                    /* Mark that a yield is pending in case the user is not
-                     * using the "xHigherPriorityTaskWoken" parameter to an ISR
-                     * safe FreeRTOS function. */
-                    xYieldPending = pdTRUE;
+                        /* Mark that a yield is pending in case the user is not
+                         * using the "xHigherPriorityTaskWoken" parameter to an ISR
+                         * safe FreeRTOS function. */
+                        xYieldPendings[ 0 ] = pdTRUE;
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
                 }
-                else
+                #else /* #if ( configNUMBER_OF_CORES == 1 ) */
                 {
-                    mtCOVERAGE_TEST_MARKER();
+                    #if ( configUSE_PREEMPTION == 1 )
+                    {
+                        prvYieldForTask( pxTCB );
+
+                        if( xYieldPendings[ portGET_CORE_ID() ] == pdTRUE )
+                        {
+                            if( pxHigherPriorityTaskWoken != NULL )
+                            {
+                                *pxHigherPriorityTaskWoken = pdTRUE;
+                            }
+                        }
+                    }
+                    #endif /* if ( configUSE_PREEMPTION == 1 ) */
                 }
+                #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
             }
         }
-        portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+        taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
 
         return xReturn;
     }
@@ -5207,7 +7288,7 @@ TickType_t uxTaskResetEventItemValue( void )
 
         pxTCB = xTaskToNotify;
 
-        uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+        uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
         {
             ucOriginalNotifyState = pxTCB->ucNotifyState[ uxIndexToNotify ];
             pxTCB->ucNotifyState[ uxIndexToNotify ] = taskNOTIFICATION_RECEIVED;
@@ -5237,27 +7318,47 @@ TickType_t uxTaskResetEventItemValue( void )
                     listINSERT_END( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
                 }
 
-                if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+                #if ( configNUMBER_OF_CORES == 1 )
                 {
-                    /* The notified task has a priority above the currently
-                     * executing task so a yield is required. */
-                    if( pxHigherPriorityTaskWoken != NULL )
+                    if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
                     {
-                        *pxHigherPriorityTaskWoken = pdTRUE;
-                    }
+                        /* The notified task has a priority above the currently
+                         * executing task so a yield is required. */
+                        if( pxHigherPriorityTaskWoken != NULL )
+                        {
+                            *pxHigherPriorityTaskWoken = pdTRUE;
+                        }
 
-                    /* Mark that a yield is pending in case the user is not
-                     * using the "xHigherPriorityTaskWoken" parameter in an ISR
-                     * safe FreeRTOS function. */
-                    xYieldPending = pdTRUE;
+                        /* Mark that a yield is pending in case the user is not
+                         * using the "xHigherPriorityTaskWoken" parameter in an ISR
+                         * safe FreeRTOS function. */
+                        xYieldPendings[ 0 ] = pdTRUE;
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
                 }
-                else
+                #else /* #if ( configNUMBER_OF_CORES == 1 ) */
                 {
-                    mtCOVERAGE_TEST_MARKER();
+                    #if ( configUSE_PREEMPTION == 1 )
+                    {
+                        prvYieldForTask( pxTCB );
+
+                        if( xYieldPendings[ portGET_CORE_ID() ] == pdTRUE )
+                        {
+                            if( pxHigherPriorityTaskWoken != NULL )
+                            {
+                                *pxHigherPriorityTaskWoken = pdTRUE;
+                            }
+                        }
+                    }
+                    #endif /* #if ( configUSE_PREEMPTION == 1 ) */
                 }
+                #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
             }
         }
-        portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+        taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
     }
 
 #endif /* configUSE_TASK_NOTIFICATIONS */
@@ -5362,24 +7463,56 @@ TickType_t uxTaskResetEventItemValue( void )
 #endif /* if ( configGENERATE_RUN_TIME_STATS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configGENERATE_RUN_TIME_STATS == 1 )
+#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
 
     configRUN_TIME_COUNTER_TYPE ulTaskGetIdleRunTimeCounter( void )
     {
-        return ulTaskGetRunTimeCounter( xIdleTaskHandle );
+        configRUN_TIME_COUNTER_TYPE ulReturn = 0;
+        BaseType_t i;
+
+        for( i = 0; i < ( BaseType_t ) configNUMBER_OF_CORES; i++ )
+        {
+            ulReturn += xIdleTaskHandles[ i ]->ulRunTimeCounter;
+        }
+
+        return ulReturn;
     }
 
-#endif
+#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( configGENERATE_RUN_TIME_STATS == 1 )
+#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
 
     configRUN_TIME_COUNTER_TYPE ulTaskGetIdleRunTimePercent( void )
     {
-        return ulTaskGetRunTimePercent( xIdleTaskHandle );
+        configRUN_TIME_COUNTER_TYPE ulTotalTime, ulReturn;
+        configRUN_TIME_COUNTER_TYPE ulRunTimeCounter = 0;
+        BaseType_t i;
+
+        ulTotalTime = portGET_RUN_TIME_COUNTER_VALUE() * configNUMBER_OF_CORES;
+
+        /* For percentage calculations. */
+        ulTotalTime /= ( configRUN_TIME_COUNTER_TYPE ) 100;
+
+        /* Avoid divide by zero errors. */
+        if( ulTotalTime > ( configRUN_TIME_COUNTER_TYPE ) 0 )
+        {
+            for( i = 0; i < ( BaseType_t ) configNUMBER_OF_CORES; i++ )
+            {
+                ulRunTimeCounter += xIdleTaskHandles[ i ]->ulRunTimeCounter;
+            }
+
+            ulReturn = ulRunTimeCounter / ulTotalTime;
+        }
+        else
+        {
+            ulReturn = 0;
+        }
+
+        return ulReturn;
     }
 
-#endif
+#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
 /*-----------------------------------------------------------*/
 
 static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait,
diff --git a/timers.c b/timers.c
index 457ab8f8f..0028c3348 100644
--- a/timers.c
+++ b/timers.c
@@ -72,17 +72,17 @@
     #define tmrSTATUS_IS_AUTORELOAD              ( ( uint8_t ) 0x04 )
 
 /* The definition of the timers themselves. */
-    typedef struct tmrTimerControl                  /* The old naming convention is used to prevent breaking kernel aware debuggers. */
+    typedef struct tmrTimerControl                                               /* The old naming convention is used to prevent breaking kernel aware debuggers. */
     {
-        const char * pcTimerName;                   /**< Text name.  This is not used by the kernel, it is included simply to make debugging easier. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-        ListItem_t xTimerListItem;                  /**< Standard linked list item as used by all kernel features for event management. */
-        TickType_t xTimerPeriodInTicks;             /**< How quickly and often the timer expires. */
-        void * pvTimerID;                           /**< An ID to identify the timer.  This allows the timer to be identified when the same callback is used for multiple timers. */
-        TimerCallbackFunction_t pxCallbackFunction; /**< The function that will be called when the timer expires. */
+        const char * pcTimerName;                                                /**< Text name.  This is not used by the kernel, it is included simply to make debugging easier. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+        ListItem_t xTimerListItem;                                               /**< Standard linked list item as used by all kernel features for event management. */
+        TickType_t xTimerPeriodInTicks;                                          /**< How quickly and often the timer expires. */
+        void * pvTimerID;                                                        /**< An ID to identify the timer.  This allows the timer to be identified when the same callback is used for multiple timers. */
+        portTIMER_CALLBACK_ATTRIBUTE TimerCallbackFunction_t pxCallbackFunction; /**< The function that will be called when the timer expires. */
         #if ( configUSE_TRACE_FACILITY == 1 )
-            UBaseType_t uxTimerNumber;              /**< An ID assigned by trace tools such as FreeRTOS+Trace */
+            UBaseType_t uxTimerNumber;                                           /**< An ID assigned by trace tools such as FreeRTOS+Trace */
         #endif
-        uint8_t ucStatus;                           /**< Holds bits to say if the timer was statically allocated or not, and if it is active or not. */
+        uint8_t ucStatus;                                                        /**< Holds bits to say if the timer was statically allocated or not, and if it is active or not. */
     } xTIMER;
 
 /* The old xTIMER name is maintained above then typedefed to the new Timer_t
@@ -103,6 +103,7 @@
 
     typedef struct tmrCallbackParameters
     {
+        portTIMER_CALLBACK_ATTRIBUTE
         PendedFunction_t pxCallbackFunction; /* << The callback function to execute. */
         void * pvParameter1;                 /* << The value that will be used as the callback functions first parameter. */
         uint32_t ulParameter2;               /* << The value that will be used as the callback functions second parameter. */
@@ -383,15 +384,17 @@
     }
 /*-----------------------------------------------------------*/
 
-    BaseType_t xTimerGenericCommand( TimerHandle_t xTimer,
-                                     const BaseType_t xCommandID,
-                                     const TickType_t xOptionalValue,
-                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                     const TickType_t xTicksToWait )
+    BaseType_t xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                             const BaseType_t xCommandID,
+                                             const TickType_t xOptionalValue,
+                                             BaseType_t * const pxHigherPriorityTaskWoken,
+                                             const TickType_t xTicksToWait )
     {
         BaseType_t xReturn = pdFAIL;
         DaemonTaskMessage_t xMessage;
 
+        ( void ) pxHigherPriorityTaskWoken;
+
         configASSERT( xTimer );
 
         /* Send a message to the timer service task to perform a particular action
@@ -403,6 +406,8 @@
             xMessage.u.xTimerParameters.xMessageValue = xOptionalValue;
             xMessage.u.xTimerParameters.pxTimer = xTimer;
 
+            configASSERT( xCommandID < tmrFIRST_FROM_ISR_COMMAND );
+
             if( xCommandID < tmrFIRST_FROM_ISR_COMMAND )
             {
                 if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING )
@@ -414,7 +419,43 @@
                     xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY );
                 }
             }
-            else
+
+            traceTIMER_COMMAND_SEND( xTimer, xCommandID, xOptionalValue, xReturn );
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        return xReturn;
+    }
+/*-----------------------------------------------------------*/
+
+    BaseType_t xTimerGenericCommandFromISR( TimerHandle_t xTimer,
+                                            const BaseType_t xCommandID,
+                                            const TickType_t xOptionalValue,
+                                            BaseType_t * const pxHigherPriorityTaskWoken,
+                                            const TickType_t xTicksToWait )
+    {
+        BaseType_t xReturn = pdFAIL;
+        DaemonTaskMessage_t xMessage;
+
+        ( void ) xTicksToWait;
+
+        configASSERT( xTimer );
+
+        /* Send a message to the timer service task to perform a particular action
+         * on a particular timer definition. */
+        if( xTimerQueue != NULL )
+        {
+            /* Send a command to the timer service task to start the xTimer timer. */
+            xMessage.xMessageID = xCommandID;
+            xMessage.u.xTimerParameters.xMessageValue = xOptionalValue;
+            xMessage.u.xTimerParameters.pxTimer = xTimer;
+
+            configASSERT( xCommandID >= tmrFIRST_FROM_ISR_COMMAND );
+
+            if( xCommandID >= tmrFIRST_FROM_ISR_COMMAND )
             {
                 xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );
             }
@@ -669,7 +710,15 @@
                          * block time to expire.  If a command arrived between the
                          * critical section being exited and this yield then the yield
                          * will not cause the task to block. */
-                        portYIELD_WITHIN_API();
+                        #if ( configNUMBER_OF_CORES == 1 )
+                        {
+                            portYIELD_WITHIN_API();
+                        }
+                        #else /* #if ( configNUMBER_OF_CORES == 1 ) */
+                        {
+                            vTaskYieldWithinAPI();
+                        }
+                        #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
                     }
                     else
                     {

From a33ba8e646cbee4f66b99f2d11124c24f6493fb8 Mon Sep 17 00:00:00 2001
From: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Date: Mon, 24 Jul 2023 18:03:49 +0530
Subject: [PATCH 011/424] Define (U)BaseType_t to 64-bit types on Windows
 (#715)

Define (U)BaseType_t to 64-bit types on Windows

This ensures that BaseType_t and UBaseType_t are correctly defined to
64-bit types on 64-bit Windows.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 portable/MSVC-MingW/portmacro.h | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/portable/MSVC-MingW/portmacro.h b/portable/MSVC-MingW/portmacro.h
index b1282b3d7..652792317 100644
--- a/portable/MSVC-MingW/portmacro.h
+++ b/portable/MSVC-MingW/portmacro.h
@@ -42,12 +42,19 @@
 #define portLONG        long
 #define portSHORT       short
 #define portSTACK_TYPE  size_t
-#define portBASE_TYPE   long
 #define portPOINTER_SIZE_TYPE size_t
 
 typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
+
+#if defined( __x86_64__) || defined( _M_X64 )
+    #define portBASE_TYPE   long long
+    typedef long long BaseType_t;
+    typedef unsigned long long UBaseType_t;
+#else
+    #define portBASE_TYPE   long
+    typedef long BaseType_t;
+    typedef unsigned long UBaseType_t;
+#endif
 
 
 #if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )

From cfd4c73b5b5f5f2b41c07074481f13d2173a5002 Mon Sep 17 00:00:00 2001
From: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Date: Tue, 25 Jul 2023 20:00:41 +0530
Subject: [PATCH 012/424] Fix compilation warnings with Clang (#721)

Fix compilation warnings with Clang

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 .github/lexicon.txt                       | 1 +
 include/FreeRTOS.h                        | 8 ++++++++
 include/task.h                            | 4 ++--
 portable/MemMang/heap_5.c                 | 4 ++--
 portable/ThirdParty/GCC/Posix/port.c      | 4 ++--
 portable/ThirdParty/GCC/Posix/portmacro.h | 3 ++-
 6 files changed, 17 insertions(+), 7 deletions(-)

diff --git a/.github/lexicon.txt b/.github/lexicon.txt
index 853c73f22..76443884e 100644
--- a/.github/lexicon.txt
+++ b/.github/lexicon.txt
@@ -3089,6 +3089,7 @@ xtaskswaitingtermination
 xtaskswaitingtoreceive
 xtaskswaitingtosend
 xtasktodelete
+xtasktomodify
 xtasktonotify
 xtasktoquery
 xtasktoresume
diff --git a/include/FreeRTOS.h b/include/FreeRTOS.h
index 5016ebf5e..34a14ca63 100644
--- a/include/FreeRTOS.h
+++ b/include/FreeRTOS.h
@@ -472,6 +472,14 @@
 
 #endif
 
+#ifndef configUSE_CORE_AFFINITY
+    #define configUSE_CORE_AFFINITY    0
+#endif /* configUSE_CORE_AFFINITY */
+
+#ifndef configUSE_MINIMAL_IDLE_HOOK
+    #define configUSE_MINIMAL_IDLE_HOOK    0
+#endif /* configUSE_MINIMAL_IDLE_HOOK */
+
 /* The timers module relies on xTaskGetSchedulerState(). */
 #if configUSE_TIMERS == 1
 
diff --git a/include/task.h b/include/task.h
index a7e1c795e..d0441f439 100644
--- a/include/task.h
+++ b/include/task.h
@@ -715,7 +715,7 @@ typedef enum
  * a call to xTaskCreateRestricted().  These regions can be redefined using
  * vTaskAllocateMPURegions().
  *
- * @param xTask The handle of the task being updated.
+ * @param xTaskToModify The handle of the task being updated.
  *
  * @param[in] pxRegions A pointer to a MemoryRegion_t structure that contains the
  * new memory region definitions.
@@ -1321,7 +1321,7 @@ BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION;
                                UBaseType_t uxCoreAffinityMask );
 #endif
 
-#if ( configUSE_CORE_AFFINITY == 1 )
+#if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
 
 /**
  * @brief Gets the core affinity mask for a task.
diff --git a/portable/MemMang/heap_5.c b/portable/MemMang/heap_5.c
index bd641dcdf..24a7adac9 100644
--- a/portable/MemMang/heap_5.c
+++ b/portable/MemMang/heap_5.c
@@ -120,8 +120,8 @@
  * of their memory address. */
 typedef struct A_BLOCK_LINK
 {
-    struct A_BLOCK_LINK * pxNextFreeBlock; /*<< The next free block in the list. */
-    size_t xBlockSize;                     /*<< The size of the free block. */
+    struct A_BLOCK_LINK * pxNextFreeBlock; /**< The next free block in the list. */
+    size_t xBlockSize;                     /**< The size of the free block. */
 } BlockLink_t;
 
 /*-----------------------------------------------------------*/
diff --git a/portable/ThirdParty/GCC/Posix/port.c b/portable/ThirdParty/GCC/Posix/port.c
index 23aec6552..54134873f 100644
--- a/portable/ThirdParty/GCC/Posix/port.c
+++ b/portable/ThirdParty/GCC/Posix/port.c
@@ -584,12 +584,12 @@ static void prvSetupSignalsAndSchedulerPolicy( void )
 }
 /*-----------------------------------------------------------*/
 
-unsigned long ulPortGetRunTime( void )
+uint32_t ulPortGetRunTime( void )
 {
     struct tms xTimes;
 
     times( &xTimes );
 
-    return ( unsigned long ) xTimes.tms_utime;
+    return ( uint32_t ) xTimes.tms_utime;
 }
 /*-----------------------------------------------------------*/
diff --git a/portable/ThirdParty/GCC/Posix/portmacro.h b/portable/ThirdParty/GCC/Posix/portmacro.h
index 154a03975..5e57a050a 100644
--- a/portable/ThirdParty/GCC/Posix/portmacro.h
+++ b/portable/ThirdParty/GCC/Posix/portmacro.h
@@ -37,6 +37,7 @@
 /* *INDENT-ON* */
 
 #include <limits.h>
+#include <stdint.h>
 
 /*-----------------------------------------------------------
  * Port specific definitions.
@@ -126,7 +127,7 @@ extern void vPortCancelThread( void *pxTaskToDelete );
  */
 #define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
 
-extern unsigned long ulPortGetRunTime( void );
+extern uint32_t ulPortGetRunTime( void );
 #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() /* no-op */
 #define portGET_RUN_TIME_COUNTER_VALUE()         ulPortGetRunTime()
 

From dbef667bf43f10c8f82d809341053887602a2ca7 Mon Sep 17 00:00:00 2001
From: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Date: Wed, 26 Jul 2023 11:12:16 +0530
Subject: [PATCH 013/424] Update attribution in History.txt (#722)

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 History.txt | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/History.txt b/History.txt
index 98f9822d4..d1dba2546 100644
--- a/History.txt
+++ b/History.txt
@@ -61,8 +61,8 @@ Changes between FreeRTOS V10.5.1 and FreeRTOS 10.6.0 released July 13, 2023
 	      China.
 	    - Xinwen Fu of Department of Computer Science, University of
 	      Massachusetts Lowell, USA.
-	    - Yueqi Chen, Zicheng Wang, Minghao Lin of University of Colorado
-	      Boulder, USA.
+	    - Yueqi Chen, Zicheng Wang, Minghao Lin, Jiahe Wang of University of
+	      Colorado Boulder, USA.
 	+ Add Cortex-M35P port. Contributed by @urutva.
 	+ Add embedded extension (RV32E) support to the IAR RISC-V port.
 	+ Add ulTaskGetRunTimeCounter and ulTaskGetRunTimePercent APIs. Contributed by

From d02ab775f321e5f3b59e5a3c609ea6c06c0199c1 Mon Sep 17 00:00:00 2001
From: kar-rahul-aws <118818625+kar-rahul-aws@users.noreply.github.com>
Date: Wed, 26 Jul 2023 14:50:27 +0530
Subject: [PATCH 014/424] Fix warning issue for warning in arithmetic
 conversion for UBaseType_t (#720)

* Fix warning issue for warnign in arithmnetic conversion for UBaseType_t

* Fix warning in streamBuffer

* Add cast to queue.c file changes

* Minor fix to cast

* Fix formatting

* Revert minor fix to cast

---------

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
---
 queue.c         | 16 ++++++++--------
 stream_buffer.c |  2 +-
 tasks.c         | 10 +++++-----
 3 files changed, 14 insertions(+), 14 deletions(-)
 mode change 100644 => 100755 queue.c

diff --git a/queue.c b/queue.c
old mode 100644
new mode 100755
index e87db0f45..76006d05d
--- a/queue.c
+++ b/queue.c
@@ -490,7 +490,7 @@ BaseType_t xQueueGenericReset( QueueHandle_t xQueue,
             /* Check for multiplication overflow. */
             ( ( SIZE_MAX / uxQueueLength ) >= uxItemSize ) &&
             /* Check for addition overflow. */
-            ( ( SIZE_MAX - sizeof( Queue_t ) ) >= ( uxQueueLength * uxItemSize ) ) )
+            ( ( UBaseType_t ) ( SIZE_MAX - sizeof( Queue_t ) ) >= ( uxQueueLength * uxItemSize ) ) )
         {
             /* Allocate enough space to hold the maximum number of items that
              * can be in the queue at any time.  It is valid for uxItemSize to be
@@ -1329,7 +1329,7 @@ BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue,
              * can be assumed there is no mutex holder and no need to determine if
              * priority disinheritance is needed.  Simply increase the count of
              * messages (semaphores) available. */
-            pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
+            pxQueue->uxMessagesWaiting = ( UBaseType_t ) ( uxMessagesWaiting + ( UBaseType_t ) 1 );
 
             /* The event list is not altered if the queue is locked.  This will
              * be done when the queue is unlocked later. */
@@ -1474,7 +1474,7 @@ BaseType_t xQueueReceive( QueueHandle_t xQueue,
                 /* Data available, remove one item. */
                 prvCopyDataFromQueue( pxQueue, pvBuffer );
                 traceQUEUE_RECEIVE( pxQueue );
-                pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
+                pxQueue->uxMessagesWaiting = ( UBaseType_t ) ( uxMessagesWaiting - ( UBaseType_t ) 1 );
 
                 /* There is now space in the queue, were any tasks waiting to
                  * post to the queue?  If so, unblock the highest priority waiting
@@ -1631,7 +1631,7 @@ BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue,
 
                 /* Semaphores are queues with a data size of zero and where the
                  * messages waiting is the semaphore's count.  Reduce the count. */
-                pxQueue->uxMessagesWaiting = uxSemaphoreCount - ( UBaseType_t ) 1;
+                pxQueue->uxMessagesWaiting = ( UBaseType_t ) ( uxSemaphoreCount - ( UBaseType_t ) 1 );
 
                 #if ( configUSE_MUTEXES == 1 )
                 {
@@ -2003,7 +2003,7 @@ BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue,
             traceQUEUE_RECEIVE_FROM_ISR( pxQueue );
 
             prvCopyDataFromQueue( pxQueue, pvBuffer );
-            pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
+            pxQueue->uxMessagesWaiting = ( UBaseType_t ) ( uxMessagesWaiting - ( UBaseType_t ) 1 );
 
             /* If the queue is locked the event list will not be modified.
              * Instead update the lock count so the task that unlocks the queue
@@ -2137,7 +2137,7 @@ UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue )
 
     taskENTER_CRITICAL();
     {
-        uxReturn = pxQueue->uxLength - pxQueue->uxMessagesWaiting;
+        uxReturn = ( UBaseType_t ) ( pxQueue->uxLength - pxQueue->uxMessagesWaiting );
     }
     taskEXIT_CRITICAL();
 
@@ -2250,7 +2250,7 @@ UBaseType_t uxQueueGetQueueItemSize( QueueHandle_t xQueue ) /* PRIVILEGED_FUNCTI
          * mutex. */
         if( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0U )
         {
-            uxHighestPriorityOfWaitingTasks = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) );
+            uxHighestPriorityOfWaitingTasks = ( UBaseType_t ) ( ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) ) );
         }
         else
         {
@@ -2340,7 +2340,7 @@ static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue,
         }
     }
 
-    pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
+    pxQueue->uxMessagesWaiting = ( UBaseType_t ) ( uxMessagesWaiting + ( UBaseType_t ) 1 );
 
     return xReturn;
 }
diff --git a/stream_buffer.c b/stream_buffer.c
index b7410fc06..80975bdc8 100644
--- a/stream_buffer.c
+++ b/stream_buffer.c
@@ -1448,7 +1448,7 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
 
     uint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer )
     {
-        return( xStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER );
+        return( ( uint8_t ) ( xStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) );
     }
 
 #endif /* configUSE_TRACE_FACILITY */
diff --git a/tasks.c b/tasks.c
index b991b7da4..d08bb2cdc 100644
--- a/tasks.c
+++ b/tasks.c
@@ -3969,19 +3969,19 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char
                 do
                 {
                     uxQueue--;
-                    uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &( pxReadyTasksLists[ uxQueue ] ), eReady );
+                    uxTask = ( UBaseType_t ) ( uxTask + prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &( pxReadyTasksLists[ uxQueue ] ), eReady ) );
                 } while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
 
                 /* Fill in an TaskStatus_t structure with information on each
                  * task in the Blocked state. */
-                uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxDelayedTaskList, eBlocked );
-                uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxOverflowDelayedTaskList, eBlocked );
+                uxTask = ( UBaseType_t ) ( uxTask + prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxDelayedTaskList, eBlocked ) );
+                uxTask = ( UBaseType_t ) ( uxTask + prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxOverflowDelayedTaskList, eBlocked ) );
 
                 #if ( INCLUDE_vTaskDelete == 1 )
                 {
                     /* Fill in an TaskStatus_t structure with information on
                      * each task that has been deleted but not yet cleaned up. */
-                    uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xTasksWaitingTermination, eDeleted );
+                    uxTask = ( UBaseType_t ) ( uxTask + prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xTasksWaitingTermination, eDeleted ) );
                 }
                 #endif
 
@@ -3989,7 +3989,7 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char
                 {
                     /* Fill in an TaskStatus_t structure with information on
                      * each task in the Suspended state. */
-                    uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xSuspendedTaskList, eSuspended );
+                    uxTask = ( UBaseType_t ) ( uxTask + prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xSuspendedTaskList, eSuspended ) );
                 }
                 #endif
 

From b13e2698bb1dc0778bb4b5078c03a34097108497 Mon Sep 17 00:00:00 2001
From: Jeff Tenney <jeff.tenney@gmail.com>
Date: Wed, 26 Jul 2023 21:52:13 -0700
Subject: [PATCH 015/424] Work around SysTick bug for QEMU ARMv8-M (#724)

* Set SysTick CLKSOURCE bit before enabling SysTick

* Use portNVIC_SYSTICK_CLK_BIT_CONFIG

The workaround now uses portNVIC_SYSTICK_CLK_BIT_CONFIG instead of
portNVIC_SYSTICK_CLK_BIT, which saves us from having to explain in the
comments why it's OK to temporarily set the CLKSOURCE bit even if the
user's FreeRTOS configuration clears the CLKSOURCE bit.

Using portNVIC_SYSTICK_CLK_BIT_CONFIG here still correctly prevents the
firmware from triggering the QEMU bug.
---
 portable/ARMv8M/non_secure/port.c            | 11 +++++++++--
 portable/GCC/ARM_CM23/non_secure/port.c      | 11 +++++++++--
 portable/GCC/ARM_CM23_NTZ/non_secure/port.c  | 11 +++++++++--
 portable/GCC/ARM_CM33/non_secure/port.c      | 11 +++++++++--
 portable/GCC/ARM_CM33_NTZ/non_secure/port.c  | 11 +++++++++--
 portable/GCC/ARM_CM35P/non_secure/port.c     | 11 +++++++++--
 portable/GCC/ARM_CM35P_NTZ/non_secure/port.c | 11 +++++++++--
 portable/GCC/ARM_CM55/non_secure/port.c      | 11 +++++++++--
 portable/GCC/ARM_CM55_NTZ/non_secure/port.c  | 11 +++++++++--
 portable/GCC/ARM_CM85/non_secure/port.c      | 11 +++++++++--
 portable/GCC/ARM_CM85_NTZ/non_secure/port.c  | 11 +++++++++--
 portable/IAR/ARM_CM23/non_secure/port.c      | 11 +++++++++--
 portable/IAR/ARM_CM23_NTZ/non_secure/port.c  | 11 +++++++++--
 portable/IAR/ARM_CM33/non_secure/port.c      | 11 +++++++++--
 portable/IAR/ARM_CM33_NTZ/non_secure/port.c  | 11 +++++++++--
 portable/IAR/ARM_CM35P/non_secure/port.c     | 11 +++++++++--
 portable/IAR/ARM_CM35P_NTZ/non_secure/port.c | 11 +++++++++--
 portable/IAR/ARM_CM55/non_secure/port.c      | 11 +++++++++--
 portable/IAR/ARM_CM55_NTZ/non_secure/port.c  | 11 +++++++++--
 portable/IAR/ARM_CM85/non_secure/port.c      | 11 +++++++++--
 portable/IAR/ARM_CM85_NTZ/non_secure/port.c  | 11 +++++++++--
 21 files changed, 189 insertions(+), 42 deletions(-)

diff --git a/portable/ARMv8M/non_secure/port.c b/portable/ARMv8M/non_secure/port.c
index 04901015f..e027b21e1 100644
--- a/portable/ARMv8M/non_secure/port.c
+++ b/portable/ARMv8M/non_secure/port.c
@@ -754,8 +754,15 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FU
     }
     #endif /* configUSE_TICKLESS_IDLE */
 
-    /* Stop and reset the SysTick. */
-    portNVIC_SYSTICK_CTRL_REG = 0UL;
+    /* Stop and reset SysTick.
+     *
+     * QEMU versions older than 7.0.0 contain a bug which causes an error if we
+     * enable SysTick without first selecting a valid clock source. We trigger
+     * the bug if we change clock sources from a clock with a zero clock period
+     * to one with a nonzero clock period and enable Systick at the same time.
+     * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit.
+     * This workaround avoids the bug in QEMU versions older than 7.0.0. */
+    portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG;
     portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
 
     /* Configure SysTick to interrupt at the requested rate. */
diff --git a/portable/GCC/ARM_CM23/non_secure/port.c b/portable/GCC/ARM_CM23/non_secure/port.c
index 04901015f..e027b21e1 100644
--- a/portable/GCC/ARM_CM23/non_secure/port.c
+++ b/portable/GCC/ARM_CM23/non_secure/port.c
@@ -754,8 +754,15 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FU
     }
     #endif /* configUSE_TICKLESS_IDLE */
 
-    /* Stop and reset the SysTick. */
-    portNVIC_SYSTICK_CTRL_REG = 0UL;
+    /* Stop and reset SysTick.
+     *
+     * QEMU versions older than 7.0.0 contain a bug which causes an error if we
+     * enable SysTick without first selecting a valid clock source. We trigger
+     * the bug if we change clock sources from a clock with a zero clock period
+     * to one with a nonzero clock period and enable Systick at the same time.
+     * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit.
+     * This workaround avoids the bug in QEMU versions older than 7.0.0. */
+    portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG;
     portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
 
     /* Configure SysTick to interrupt at the requested rate. */
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
index 04901015f..e027b21e1 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
@@ -754,8 +754,15 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FU
     }
     #endif /* configUSE_TICKLESS_IDLE */
 
-    /* Stop and reset the SysTick. */
-    portNVIC_SYSTICK_CTRL_REG = 0UL;
+    /* Stop and reset SysTick.
+     *
+     * QEMU versions older than 7.0.0 contain a bug which causes an error if we
+     * enable SysTick without first selecting a valid clock source. We trigger
+     * the bug if we change clock sources from a clock with a zero clock period
+     * to one with a nonzero clock period and enable Systick at the same time.
+     * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit.
+     * This workaround avoids the bug in QEMU versions older than 7.0.0. */
+    portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG;
     portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
 
     /* Configure SysTick to interrupt at the requested rate. */
diff --git a/portable/GCC/ARM_CM33/non_secure/port.c b/portable/GCC/ARM_CM33/non_secure/port.c
index 04901015f..e027b21e1 100644
--- a/portable/GCC/ARM_CM33/non_secure/port.c
+++ b/portable/GCC/ARM_CM33/non_secure/port.c
@@ -754,8 +754,15 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FU
     }
     #endif /* configUSE_TICKLESS_IDLE */
 
-    /* Stop and reset the SysTick. */
-    portNVIC_SYSTICK_CTRL_REG = 0UL;
+    /* Stop and reset SysTick.
+     *
+     * QEMU versions older than 7.0.0 contain a bug which causes an error if we
+     * enable SysTick without first selecting a valid clock source. We trigger
+     * the bug if we change clock sources from a clock with a zero clock period
+     * to one with a nonzero clock period and enable Systick at the same time.
+     * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit.
+     * This workaround avoids the bug in QEMU versions older than 7.0.0. */
+    portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG;
     portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
 
     /* Configure SysTick to interrupt at the requested rate. */
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
index 04901015f..e027b21e1 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
@@ -754,8 +754,15 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FU
     }
     #endif /* configUSE_TICKLESS_IDLE */
 
-    /* Stop and reset the SysTick. */
-    portNVIC_SYSTICK_CTRL_REG = 0UL;
+    /* Stop and reset SysTick.
+     *
+     * QEMU versions older than 7.0.0 contain a bug which causes an error if we
+     * enable SysTick without first selecting a valid clock source. We trigger
+     * the bug if we change clock sources from a clock with a zero clock period
+     * to one with a nonzero clock period and enable Systick at the same time.
+     * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit.
+     * This workaround avoids the bug in QEMU versions older than 7.0.0. */
+    portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG;
     portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
 
     /* Configure SysTick to interrupt at the requested rate. */
diff --git a/portable/GCC/ARM_CM35P/non_secure/port.c b/portable/GCC/ARM_CM35P/non_secure/port.c
index 04901015f..e027b21e1 100644
--- a/portable/GCC/ARM_CM35P/non_secure/port.c
+++ b/portable/GCC/ARM_CM35P/non_secure/port.c
@@ -754,8 +754,15 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FU
     }
     #endif /* configUSE_TICKLESS_IDLE */
 
-    /* Stop and reset the SysTick. */
-    portNVIC_SYSTICK_CTRL_REG = 0UL;
+    /* Stop and reset SysTick.
+     *
+     * QEMU versions older than 7.0.0 contain a bug which causes an error if we
+     * enable SysTick without first selecting a valid clock source. We trigger
+     * the bug if we change clock sources from a clock with a zero clock period
+     * to one with a nonzero clock period and enable Systick at the same time.
+     * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit.
+     * This workaround avoids the bug in QEMU versions older than 7.0.0. */
+    portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG;
     portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
 
     /* Configure SysTick to interrupt at the requested rate. */
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c b/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
index 04901015f..e027b21e1 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
@@ -754,8 +754,15 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FU
     }
     #endif /* configUSE_TICKLESS_IDLE */
 
-    /* Stop and reset the SysTick. */
-    portNVIC_SYSTICK_CTRL_REG = 0UL;
+    /* Stop and reset SysTick.
+     *
+     * QEMU versions older than 7.0.0 contain a bug which causes an error if we
+     * enable SysTick without first selecting a valid clock source. We trigger
+     * the bug if we change clock sources from a clock with a zero clock period
+     * to one with a nonzero clock period and enable Systick at the same time.
+     * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit.
+     * This workaround avoids the bug in QEMU versions older than 7.0.0. */
+    portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG;
     portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
 
     /* Configure SysTick to interrupt at the requested rate. */
diff --git a/portable/GCC/ARM_CM55/non_secure/port.c b/portable/GCC/ARM_CM55/non_secure/port.c
index 04901015f..e027b21e1 100644
--- a/portable/GCC/ARM_CM55/non_secure/port.c
+++ b/portable/GCC/ARM_CM55/non_secure/port.c
@@ -754,8 +754,15 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FU
     }
     #endif /* configUSE_TICKLESS_IDLE */
 
-    /* Stop and reset the SysTick. */
-    portNVIC_SYSTICK_CTRL_REG = 0UL;
+    /* Stop and reset SysTick.
+     *
+     * QEMU versions older than 7.0.0 contain a bug which causes an error if we
+     * enable SysTick without first selecting a valid clock source. We trigger
+     * the bug if we change clock sources from a clock with a zero clock period
+     * to one with a nonzero clock period and enable Systick at the same time.
+     * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit.
+     * This workaround avoids the bug in QEMU versions older than 7.0.0. */
+    portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG;
     portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
 
     /* Configure SysTick to interrupt at the requested rate. */
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/port.c b/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
index 04901015f..e027b21e1 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
@@ -754,8 +754,15 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FU
     }
     #endif /* configUSE_TICKLESS_IDLE */
 
-    /* Stop and reset the SysTick. */
-    portNVIC_SYSTICK_CTRL_REG = 0UL;
+    /* Stop and reset SysTick.
+     *
+     * QEMU versions older than 7.0.0 contain a bug which causes an error if we
+     * enable SysTick without first selecting a valid clock source. We trigger
+     * the bug if we change clock sources from a clock with a zero clock period
+     * to one with a nonzero clock period and enable Systick at the same time.
+     * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit.
+     * This workaround avoids the bug in QEMU versions older than 7.0.0. */
+    portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG;
     portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
 
     /* Configure SysTick to interrupt at the requested rate. */
diff --git a/portable/GCC/ARM_CM85/non_secure/port.c b/portable/GCC/ARM_CM85/non_secure/port.c
index 04901015f..e027b21e1 100644
--- a/portable/GCC/ARM_CM85/non_secure/port.c
+++ b/portable/GCC/ARM_CM85/non_secure/port.c
@@ -754,8 +754,15 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FU
     }
     #endif /* configUSE_TICKLESS_IDLE */
 
-    /* Stop and reset the SysTick. */
-    portNVIC_SYSTICK_CTRL_REG = 0UL;
+    /* Stop and reset SysTick.
+     *
+     * QEMU versions older than 7.0.0 contain a bug which causes an error if we
+     * enable SysTick without first selecting a valid clock source. We trigger
+     * the bug if we change clock sources from a clock with a zero clock period
+     * to one with a nonzero clock period and enable Systick at the same time.
+     * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit.
+     * This workaround avoids the bug in QEMU versions older than 7.0.0. */
+    portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG;
     portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
 
     /* Configure SysTick to interrupt at the requested rate. */
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/port.c b/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
index 04901015f..e027b21e1 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
@@ -754,8 +754,15 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FU
     }
     #endif /* configUSE_TICKLESS_IDLE */
 
-    /* Stop and reset the SysTick. */
-    portNVIC_SYSTICK_CTRL_REG = 0UL;
+    /* Stop and reset SysTick.
+     *
+     * QEMU versions older than 7.0.0 contain a bug which causes an error if we
+     * enable SysTick without first selecting a valid clock source. We trigger
+     * the bug if we change clock sources from a clock with a zero clock period
+     * to one with a nonzero clock period and enable Systick at the same time.
+     * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit.
+     * This workaround avoids the bug in QEMU versions older than 7.0.0. */
+    portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG;
     portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
 
     /* Configure SysTick to interrupt at the requested rate. */
diff --git a/portable/IAR/ARM_CM23/non_secure/port.c b/portable/IAR/ARM_CM23/non_secure/port.c
index 04901015f..e027b21e1 100644
--- a/portable/IAR/ARM_CM23/non_secure/port.c
+++ b/portable/IAR/ARM_CM23/non_secure/port.c
@@ -754,8 +754,15 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FU
     }
     #endif /* configUSE_TICKLESS_IDLE */
 
-    /* Stop and reset the SysTick. */
-    portNVIC_SYSTICK_CTRL_REG = 0UL;
+    /* Stop and reset SysTick.
+     *
+     * QEMU versions older than 7.0.0 contain a bug which causes an error if we
+     * enable SysTick without first selecting a valid clock source. We trigger
+     * the bug if we change clock sources from a clock with a zero clock period
+     * to one with a nonzero clock period and enable Systick at the same time.
+     * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit.
+     * This workaround avoids the bug in QEMU versions older than 7.0.0. */
+    portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG;
     portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
 
     /* Configure SysTick to interrupt at the requested rate. */
diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
index 04901015f..e027b21e1 100644
--- a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
@@ -754,8 +754,15 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FU
     }
     #endif /* configUSE_TICKLESS_IDLE */
 
-    /* Stop and reset the SysTick. */
-    portNVIC_SYSTICK_CTRL_REG = 0UL;
+    /* Stop and reset SysTick.
+     *
+     * QEMU versions older than 7.0.0 contain a bug which causes an error if we
+     * enable SysTick without first selecting a valid clock source. We trigger
+     * the bug if we change clock sources from a clock with a zero clock period
+     * to one with a nonzero clock period and enable Systick at the same time.
+     * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit.
+     * This workaround avoids the bug in QEMU versions older than 7.0.0. */
+    portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG;
     portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
 
     /* Configure SysTick to interrupt at the requested rate. */
diff --git a/portable/IAR/ARM_CM33/non_secure/port.c b/portable/IAR/ARM_CM33/non_secure/port.c
index 04901015f..e027b21e1 100644
--- a/portable/IAR/ARM_CM33/non_secure/port.c
+++ b/portable/IAR/ARM_CM33/non_secure/port.c
@@ -754,8 +754,15 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FU
     }
     #endif /* configUSE_TICKLESS_IDLE */
 
-    /* Stop and reset the SysTick. */
-    portNVIC_SYSTICK_CTRL_REG = 0UL;
+    /* Stop and reset SysTick.
+     *
+     * QEMU versions older than 7.0.0 contain a bug which causes an error if we
+     * enable SysTick without first selecting a valid clock source. We trigger
+     * the bug if we change clock sources from a clock with a zero clock period
+     * to one with a nonzero clock period and enable Systick at the same time.
+     * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit.
+     * This workaround avoids the bug in QEMU versions older than 7.0.0. */
+    portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG;
     portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
 
     /* Configure SysTick to interrupt at the requested rate. */
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
index 04901015f..e027b21e1 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
@@ -754,8 +754,15 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FU
     }
     #endif /* configUSE_TICKLESS_IDLE */
 
-    /* Stop and reset the SysTick. */
-    portNVIC_SYSTICK_CTRL_REG = 0UL;
+    /* Stop and reset SysTick.
+     *
+     * QEMU versions older than 7.0.0 contain a bug which causes an error if we
+     * enable SysTick without first selecting a valid clock source. We trigger
+     * the bug if we change clock sources from a clock with a zero clock period
+     * to one with a nonzero clock period and enable Systick at the same time.
+     * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit.
+     * This workaround avoids the bug in QEMU versions older than 7.0.0. */
+    portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG;
     portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
 
     /* Configure SysTick to interrupt at the requested rate. */
diff --git a/portable/IAR/ARM_CM35P/non_secure/port.c b/portable/IAR/ARM_CM35P/non_secure/port.c
index 04901015f..e027b21e1 100644
--- a/portable/IAR/ARM_CM35P/non_secure/port.c
+++ b/portable/IAR/ARM_CM35P/non_secure/port.c
@@ -754,8 +754,15 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FU
     }
     #endif /* configUSE_TICKLESS_IDLE */
 
-    /* Stop and reset the SysTick. */
-    portNVIC_SYSTICK_CTRL_REG = 0UL;
+    /* Stop and reset SysTick.
+     *
+     * QEMU versions older than 7.0.0 contain a bug which causes an error if we
+     * enable SysTick without first selecting a valid clock source. We trigger
+     * the bug if we change clock sources from a clock with a zero clock period
+     * to one with a nonzero clock period and enable Systick at the same time.
+     * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit.
+     * This workaround avoids the bug in QEMU versions older than 7.0.0. */
+    portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG;
     portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
 
     /* Configure SysTick to interrupt at the requested rate. */
diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c b/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
index 04901015f..e027b21e1 100644
--- a/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
@@ -754,8 +754,15 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FU
     }
     #endif /* configUSE_TICKLESS_IDLE */
 
-    /* Stop and reset the SysTick. */
-    portNVIC_SYSTICK_CTRL_REG = 0UL;
+    /* Stop and reset SysTick.
+     *
+     * QEMU versions older than 7.0.0 contain a bug which causes an error if we
+     * enable SysTick without first selecting a valid clock source. We trigger
+     * the bug if we change clock sources from a clock with a zero clock period
+     * to one with a nonzero clock period and enable Systick at the same time.
+     * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit.
+     * This workaround avoids the bug in QEMU versions older than 7.0.0. */
+    portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG;
     portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
 
     /* Configure SysTick to interrupt at the requested rate. */
diff --git a/portable/IAR/ARM_CM55/non_secure/port.c b/portable/IAR/ARM_CM55/non_secure/port.c
index 04901015f..e027b21e1 100644
--- a/portable/IAR/ARM_CM55/non_secure/port.c
+++ b/portable/IAR/ARM_CM55/non_secure/port.c
@@ -754,8 +754,15 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FU
     }
     #endif /* configUSE_TICKLESS_IDLE */
 
-    /* Stop and reset the SysTick. */
-    portNVIC_SYSTICK_CTRL_REG = 0UL;
+    /* Stop and reset SysTick.
+     *
+     * QEMU versions older than 7.0.0 contain a bug which causes an error if we
+     * enable SysTick without first selecting a valid clock source. We trigger
+     * the bug if we change clock sources from a clock with a zero clock period
+     * to one with a nonzero clock period and enable Systick at the same time.
+     * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit.
+     * This workaround avoids the bug in QEMU versions older than 7.0.0. */
+    portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG;
     portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
 
     /* Configure SysTick to interrupt at the requested rate. */
diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/port.c b/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
index 04901015f..e027b21e1 100644
--- a/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
@@ -754,8 +754,15 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FU
     }
     #endif /* configUSE_TICKLESS_IDLE */
 
-    /* Stop and reset the SysTick. */
-    portNVIC_SYSTICK_CTRL_REG = 0UL;
+    /* Stop and reset SysTick.
+     *
+     * QEMU versions older than 7.0.0 contain a bug which causes an error if we
+     * enable SysTick without first selecting a valid clock source. We trigger
+     * the bug if we change clock sources from a clock with a zero clock period
+     * to one with a nonzero clock period and enable Systick at the same time.
+     * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit.
+     * This workaround avoids the bug in QEMU versions older than 7.0.0. */
+    portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG;
     portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
 
     /* Configure SysTick to interrupt at the requested rate. */
diff --git a/portable/IAR/ARM_CM85/non_secure/port.c b/portable/IAR/ARM_CM85/non_secure/port.c
index 04901015f..e027b21e1 100644
--- a/portable/IAR/ARM_CM85/non_secure/port.c
+++ b/portable/IAR/ARM_CM85/non_secure/port.c
@@ -754,8 +754,15 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FU
     }
     #endif /* configUSE_TICKLESS_IDLE */
 
-    /* Stop and reset the SysTick. */
-    portNVIC_SYSTICK_CTRL_REG = 0UL;
+    /* Stop and reset SysTick.
+     *
+     * QEMU versions older than 7.0.0 contain a bug which causes an error if we
+     * enable SysTick without first selecting a valid clock source. We trigger
+     * the bug if we change clock sources from a clock with a zero clock period
+     * to one with a nonzero clock period and enable Systick at the same time.
+     * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit.
+     * This workaround avoids the bug in QEMU versions older than 7.0.0. */
+    portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG;
     portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
 
     /* Configure SysTick to interrupt at the requested rate. */
diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/port.c b/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
index 04901015f..e027b21e1 100644
--- a/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
@@ -754,8 +754,15 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FU
     }
     #endif /* configUSE_TICKLESS_IDLE */
 
-    /* Stop and reset the SysTick. */
-    portNVIC_SYSTICK_CTRL_REG = 0UL;
+    /* Stop and reset SysTick.
+     *
+     * QEMU versions older than 7.0.0 contain a bug which causes an error if we
+     * enable SysTick without first selecting a valid clock source. We trigger
+     * the bug if we change clock sources from a clock with a zero clock period
+     * to one with a nonzero clock period and enable Systick at the same time.
+     * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit.
+     * This workaround avoids the bug in QEMU versions older than 7.0.0. */
+    portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG;
     portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
 
     /* Configure SysTick to interrupt at the requested rate. */

From 1544768719c7346817d7e6b6b17457d845985604 Mon Sep 17 00:00:00 2001
From: Nuno Guterres Nogueira <38976366+nguterresn@users.noreply.github.com>
Date: Thu, 27 Jul 2023 12:11:22 +0200
Subject: [PATCH 016/424] Updated README.md for cross-compilation (#723)

* Update README.md
---
 README.md | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/README.md b/README.md
index dd79eee6c..38cb58622 100644
--- a/README.md
+++ b/README.md
@@ -25,6 +25,13 @@ FetchContent_Declare( freertos_kernel
 )
 ```
 
+In case you prefer to add it as a git submodule, do:
+
+```bash
+$ git submodule add https://github.com/FreeRTOS/FreeRTOS-Kernel.git <path of the submodule>
+$ git submodule update --init
+```
+
 - Add a freertos_config library (typically an INTERFACE library) The following assumes the directory structure:
   - `include/FreeRTOSConfig.h`
 ```cmake
@@ -41,6 +48,12 @@ target_compile_definitions(freertos_config
 )
 ```
 
+In case you installed FreeRTOS-Kernel as a submodule, you will have to add it as a subdirectory:
+
+```cmake
+add_subdirectory(${FREERTOS_PATH})
+```
+
 - Configure the FreeRTOS-Kernel and make it available
   - this particular example supports a native and cross-compiled build option.
 
@@ -56,6 +69,13 @@ endif()
 FetchContent_MakeAvailable(freertos_kernel)
 ```
 
+- In case of cross compilation, you should also add the following to `freertos_config`:
+
+```cmake
+target_compile_definitions(freertos_config INTERFACE ${definitions})
+target_compile_options(freertos_config INTERFACE ${options})
+```
+
 ### Consuming stand-alone - Cloning this repository
 
 To clone using HTTPS:

From 95c638b39b1a0df721797d3b72528da21cb7312b Mon Sep 17 00:00:00 2001
From: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Date: Fri, 28 Jul 2023 11:20:31 +0800
Subject: [PATCH 017/424] Update GNU ARM Toolchain demo workflow (#726)

* Update GNU ARM Toolchain demo workflow
---------

Co-authored-by: Paul Bartell <paul.bartell@gmail.com>
---
 .github/workflows/kernel-demos.yml | 17 +++++++++++++++--
 1 file changed, 15 insertions(+), 2 deletions(-)

diff --git a/.github/workflows/kernel-demos.yml b/.github/workflows/kernel-demos.yml
index 96a4c5975..865f4eefb 100644
--- a/.github/workflows/kernel-demos.yml
+++ b/.github/workflows/kernel-demos.yml
@@ -123,9 +123,22 @@ jobs:
         with:
           ref: main
           repository: FreeRTOS/FreeRTOS
-          submodules: 'recursive'
           fetch-depth: 1
 
+      - name: Fetch Community-Supported-Demos Submodule
+        shell: bash
+        run: |
+          # Fetch Community-Supported-Demos Submodule
+          echo "::group::Fetch Community-Supported-Demos Submodule"
+          git submodule update --checkout --init --depth 1 FreeRTOS/Demo/ThirdParty/Community-Supported-Demos
+          echo "::engdroup::"
+          if [ "$?" = "0" ]; then
+            echo -e "\033[32;3mCloned the Community-Supported-Demos\033[0m"
+          else
+            echo -e "\033[32;31mCommunity-Supported-Demos Clone Failed...\033[0m"
+            exit 1
+          fi
+
       # Checkout user pull request changes
       - name: Checkout Pull Request
         uses: actions/checkout@v2
@@ -169,7 +182,7 @@ jobs:
 
       - name: Build CORTEX_M0+_RP2040 Demos
         shell: bash
-        working-directory: FreeRTOS/Demo/ThirdParty/Community-Supported/CORTEX_M0+_RP2040
+        working-directory: FreeRTOS/Demo/ThirdParty/Community-Supported-Demos/CORTEX_M0+_RP2040
         run: |
           git clone https://github.com/raspberrypi/pico-sdk.git
           cmake -B build -DPICO_SDK_PATH=pico-sdk -GNinja

From 3786856b723d2d77873016504ff7a5af012f8467 Mon Sep 17 00:00:00 2001
From: kar-rahul-aws <118818625+kar-rahul-aws@users.noreply.github.com>
Date: Fri, 28 Jul 2023 11:41:59 +0530
Subject: [PATCH 018/424] Remove stdint.h in stream buffer file (#725)

* Remove stdint.h in stream buffer file

Signed-off-by: kar-rahul-aws <karahulx@amazon.com>
---
 stream_buffer.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/stream_buffer.c b/stream_buffer.c
index 80975bdc8..3a82ba31c 100644
--- a/stream_buffer.c
+++ b/stream_buffer.c
@@ -27,7 +27,6 @@
  */
 
 /* Standard includes. */
-#include <stdint.h>
 #include <string.h>
 
 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining

From 785250de4529a93e86f51bd3526dc89331921ea5 Mon Sep 17 00:00:00 2001
From: Zim Kalinowski <zim.kalinowski@espressif.com>
Date: Fri, 28 Jul 2023 10:42:18 +0200
Subject: [PATCH 019/424] Align some Linux and RL78 port types with other ports
 (#727)

---
 portable/GCC/RL78/port.c             |  2 +-
 portable/ThirdParty/GCC/Posix/port.c | 16 ++++++++--------
 2 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/portable/GCC/RL78/port.c b/portable/GCC/RL78/port.c
index 35ff7df53..5525b1014 100644
--- a/portable/GCC/RL78/port.c
+++ b/portable/GCC/RL78/port.c
@@ -136,7 +136,7 @@ uint32_t *pulLocal;
 }
 /*-----------------------------------------------------------*/
 
-portBASE_TYPE xPortStartScheduler( void )
+BaseType_t xPortStartScheduler( void )
 {
     /* Setup the hardware to generate the tick.  Interrupts are disabled when
     this function is called. */
diff --git a/portable/ThirdParty/GCC/Posix/port.c b/portable/ThirdParty/GCC/Posix/port.c
index 54134873f..a8cb25734 100644
--- a/portable/ThirdParty/GCC/Posix/port.c
+++ b/portable/ThirdParty/GCC/Posix/port.c
@@ -100,10 +100,10 @@ static pthread_once_t hSigSetupThread = PTHREAD_ONCE_INIT;
 static sigset_t xAllSignals;
 static sigset_t xSchedulerOriginalSignalMask;
 static pthread_t hMainThread = ( pthread_t ) NULL;
-static volatile portBASE_TYPE uxCriticalNesting;
+static volatile BaseType_t uxCriticalNesting;
 /*-----------------------------------------------------------*/
 
-static portBASE_TYPE xSchedulerEnd = pdFALSE;
+static BaseType_t xSchedulerEnd = pdFALSE;
 /*-----------------------------------------------------------*/
 
 static void prvSetupSignalsAndSchedulerPolicy( void );
@@ -131,10 +131,10 @@ void prvFatalError( const char * pcCall,
 /*
  * See header file for description.
  */
-portSTACK_TYPE * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                        StackType_t * pxEndOfStack,
-                                        TaskFunction_t pxCode,
-                                        void * pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     StackType_t * pxEndOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
     Thread_t * thread;
     pthread_attr_t xThreadAttributes;
@@ -147,7 +147,7 @@ portSTACK_TYPE * pxPortInitialiseStack( StackType_t * pxTopOfStack,
      * Store the additional thread data at the start of the stack.
      */
     thread = ( Thread_t * ) ( pxTopOfStack + 1 ) - 1;
-    pxTopOfStack = ( portSTACK_TYPE * ) thread - 1;
+    pxTopOfStack = ( StackType_t * ) thread - 1;
     ulStackSize = ( size_t )( pxTopOfStack + 1 - pxEndOfStack ) * sizeof( *pxTopOfStack );
 
     #ifdef __APPLE__
@@ -197,7 +197,7 @@ void vPortStartFirstTask( void )
 /*
  * See header file for description.
  */
-portBASE_TYPE xPortStartScheduler( void )
+BaseType_t xPortStartScheduler( void )
 {
     int iSignal;
     sigset_t xSignals;

From da2428fbb1053e79b00bfe6cb62580ee0416481a Mon Sep 17 00:00:00 2001
From: vinceburns <38167699+vinceburns@users.noreply.github.com>
Date: Mon, 31 Jul 2023 00:29:11 -0500
Subject: [PATCH 020/424] Feature: Add top/end of stack to task info report
 whenever it is available. (#729) (#730)

pxTopOfStack is always available and pxEndOfStack is available whenever you have:
(portSTACK_GROWTH > 0) or ( configRECORD_STACK_HIGH_ADDRESS == 1)

Include it in the info report whenever it is available to the tcb.

Co-authored-by: Vince Burns <vburns@sensata.com>
---
 include/task.h | 2 +-
 tasks.c        | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/task.h b/include/task.h
index d0441f439..97809fc33 100644
--- a/include/task.h
+++ b/include/task.h
@@ -167,7 +167,7 @@ typedef struct xTASK_STATUS
     UBaseType_t uxBasePriority;                   /* The priority to which the task will return if the task's current priority has been inherited to avoid unbounded priority inversion when obtaining a mutex.  Only valid if configUSE_MUTEXES is defined as 1 in FreeRTOSConfig.h. */
     configRUN_TIME_COUNTER_TYPE ulRunTimeCounter; /* The total run time allocated to the task so far, as defined by the run time stats clock.  See https://www.FreeRTOS.org/rtos-run-time-stats.html.  Only valid when configGENERATE_RUN_TIME_STATS is defined as 1 in FreeRTOSConfig.h. */
     StackType_t * pxStackBase;                    /* Points to the lowest address of the task's stack area. */
-    #if ( ( portSTACK_GROWTH > 0 ) && ( configRECORD_STACK_HIGH_ADDRESS == 1 ) )
+    #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) )
         StackType_t * pxTopOfStack;               /* Points to the top address of the task's stack area. */
         StackType_t * pxEndOfStack;               /* Points to the end address of the task's stack area. */
     #endif
diff --git a/tasks.c b/tasks.c
index d08bb2cdc..6670faa95 100644
--- a/tasks.c
+++ b/tasks.c
@@ -5545,7 +5545,7 @@ static void prvCheckTasksWaitingTermination( void )
         pxTaskStatus->pcTaskName = ( const char * ) &( pxTCB->pcTaskName[ 0 ] );
         pxTaskStatus->uxCurrentPriority = pxTCB->uxPriority;
         pxTaskStatus->pxStackBase = pxTCB->pxStack;
-        #if ( ( portSTACK_GROWTH > 0 ) && ( configRECORD_STACK_HIGH_ADDRESS == 1 ) )
+        #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) )
             pxTaskStatus->pxTopOfStack = pxTCB->pxTopOfStack;
             pxTaskStatus->pxEndOfStack = pxTCB->pxEndOfStack;
         #endif

From 8d80cf697a6630a2c75988d85afeee05f4257277 Mon Sep 17 00:00:00 2001
From: ActoryOu <jay2002824@gmail.com>
Date: Mon, 31 Jul 2023 16:38:26 +0800
Subject: [PATCH 021/424] Fix Pico compile warning (#732)

* Fix Pico compile warning

* Add type cast for portGET_CORE_ID

---------

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
---
 portable/ThirdParty/GCC/RP2040/include/portmacro.h |  2 +-
 tasks.c                                            | 12 ++++++------
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/portable/ThirdParty/GCC/RP2040/include/portmacro.h b/portable/ThirdParty/GCC/RP2040/include/portmacro.h
index 655b8ec74..7880a9903 100644
--- a/portable/ThirdParty/GCC/RP2040/include/portmacro.h
+++ b/portable/ThirdParty/GCC/RP2040/include/portmacro.h
@@ -194,7 +194,7 @@
     static inline void vPortRecursiveLock(uint32_t ulLockNum, spin_lock_t *pxSpinLock, BaseType_t uxAcquire) {
         static uint8_t ucOwnedByCore[ portMAX_CORE_COUNT ];
         static uint8_t ucRecursionCountByLock[ portRTOS_SPINLOCK_COUNT ];
-        configASSERT(ulLockNum >= 0 && ulLockNum < portRTOS_SPINLOCK_COUNT );
+        configASSERT( ulLockNum < portRTOS_SPINLOCK_COUNT );
         uint32_t ulCoreNum = get_core_num();
         uint32_t ulLockBit = 1u << ulLockNum;
         configASSERT(ulLockBit < 256u );
diff --git a/tasks.c b/tasks.c
index 6670faa95..f08215adf 100644
--- a/tasks.c
+++ b/tasks.c
@@ -760,7 +760,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
     static void prvYieldCore( BaseType_t xCoreID )
     {
         /* This must be called from a critical section and xCoreID must be valid. */
-        if( ( portCHECK_IF_IN_ISR() == pdTRUE ) && ( xCoreID == portGET_CORE_ID() ) )
+        if( ( portCHECK_IF_IN_ISR() == pdTRUE ) && ( xCoreID == ( BaseType_t ) portGET_CORE_ID() ) )
         {
             xYieldPendings[ xCoreID ] = pdTRUE;
         }
@@ -768,7 +768,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
         {
             if( pxCurrentTCBs[ xCoreID ]->xTaskRunState != taskTASK_YIELDING )
             {
-                if( xCoreID == portGET_CORE_ID() )
+                if( xCoreID == ( BaseType_t ) portGET_CORE_ID() )
                 {
                     xYieldPendings[ xCoreID ] = pdTRUE;
                 }
@@ -2002,7 +2002,7 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
             /* Force a reschedule if the task that has just been deleted was running. */
             if( ( xSchedulerRunning != pdFALSE ) && ( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE ) )
             {
-                if( pxTCB->xTaskRunState == portGET_CORE_ID() )
+                if( pxTCB->xTaskRunState == ( TaskRunning_t ) portGET_CORE_ID() )
                 {
                     configASSERT( uxSchedulerSuspended == 0 );
                     vTaskYieldWithinAPI();
@@ -2829,7 +2829,7 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
             {
                 if( xSchedulerRunning != pdFALSE )
                 {
-                    if( xTaskRunningOnCore == portGET_CORE_ID() )
+                    if( xTaskRunningOnCore == ( TaskRunning_t ) portGET_CORE_ID() )
                     {
                         /* The current task has just been suspended. */
                         configASSERT( uxSchedulerSuspended == 0 );
@@ -3511,7 +3511,7 @@ BaseType_t xTaskResumeAll( void )
         taskENTER_CRITICAL();
         {
             BaseType_t xCoreID;
-            xCoreID = portGET_CORE_ID();
+            xCoreID = ( BaseType_t ) portGET_CORE_ID();
 
             /* If uxSchedulerSuspended is zero then this function does not match a
              * previous call to vTaskSuspendAll(). */
@@ -4398,7 +4398,7 @@ BaseType_t xTaskIncrementTick( void )
             #else /* #if ( configNUMBER_OF_CORES == 1 ) */
             {
                 BaseType_t xCoreID, xCurrentCoreID;
-                xCurrentCoreID = portGET_CORE_ID();
+                xCurrentCoreID = ( BaseType_t ) portGET_CORE_ID();
 
                 for( xCoreID = 0; xCoreID < ( BaseType_t ) configNUMBER_OF_CORES; xCoreID++ )
                 {

From 225bace85cde0854f0d79d96a98d5fbae2af3a68 Mon Sep 17 00:00:00 2001
From: Ju1He1 <93189163+Ju1He1@users.noreply.github.com>
Date: Mon, 31 Jul 2023 11:35:17 +0200
Subject: [PATCH 022/424] Enable MSVC Port to leave the
 prvProcessSimulatedInterrupts loop when scheduler is stopped (#728)

* allow to leave loop

* add missing brace

* Code review suggestions

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 portable/MSVC-MingW/port.c | 171 +++++++++++++++++++------------------
 1 file changed, 90 insertions(+), 81 deletions(-)

diff --git a/portable/MSVC-MingW/port.c b/portable/MSVC-MingW/port.c
index f39f0ecbb..c85cfc193 100644
--- a/portable/MSVC-MingW/port.c
+++ b/portable/MSVC-MingW/port.c
@@ -340,6 +340,9 @@ SYSTEM_INFO xSystemInfo;
         /* Start the first task. */
         ResumeThread( pxThreadState->pvThread );
 
+        /* The scheduler is now running. */
+        xPortRunning = pdTRUE;
+
         /* Handle all simulated interrupts - including yield requests and
         simulated ticks. */
         prvProcessSimulatedInterrupts();
@@ -376,6 +379,8 @@ uint32_t ulSwitchRequired, i;
 ThreadState_t *pxThreadState;
 void *pvObjectList[ 2 ];
 CONTEXT xContext;
+DWORD xWinApiResult;
+const DWORD xTimeoutMilliseconds = 1000;
 
     /* Going to block on the mutex that ensured exclusive access to the simulated
     interrupt objects, and the event that signals that a simulated interrupt
@@ -388,105 +393,109 @@ CONTEXT xContext;
     ulPendingInterrupts |= ( 1 << portINTERRUPT_TICK );
     SetEvent( pvInterruptEvent );
 
-    xPortRunning = pdTRUE;
-
-    for(;;)
+    while( xPortRunning == pdTRUE )
     {
         xInsideInterrupt = pdFALSE;
-        WaitForMultipleObjects( sizeof( pvObjectList ) / sizeof( void * ), pvObjectList, TRUE, INFINITE );
 
-        /* Cannot be in a critical section to get here.  Tasks that exit a
-        critical section will block on a yield mutex to wait for an interrupt to
-        process if an interrupt was set pending while the task was inside the
-        critical section.  xInsideInterrupt prevents interrupts that contain
-        critical sections from doing the same. */
-        xInsideInterrupt = pdTRUE;
+        /* Wait with timeout so that we can exit from this loop when
+         * the scheduler is stopped by calling vPortEndScheduler. */
+        xWinApiResult = WaitForMultipleObjects( sizeof( pvObjectList ) / sizeof( void * ), pvObjectList, TRUE, xTimeoutMilliseconds );
 
-        /* Used to indicate whether the simulated interrupt processing has
-        necessitated a context switch to another task/thread. */
-        ulSwitchRequired = pdFALSE;
-
-        /* For each interrupt we are interested in processing, each of which is
-        represented by a bit in the 32bit ulPendingInterrupts variable. */
-        for( i = 0; i < portMAX_INTERRUPTS; i++ )
+        if( xWinApiResult != WAIT_TIMEOUT )
         {
-            /* Is the simulated interrupt pending? */
-            if( ( ulPendingInterrupts & ( 1UL << i ) ) != 0 )
+            /* Cannot be in a critical section to get here.  Tasks that exit a
+            critical section will block on a yield mutex to wait for an interrupt to
+            process if an interrupt was set pending while the task was inside the
+            critical section.  xInsideInterrupt prevents interrupts that contain
+            critical sections from doing the same. */
+            xInsideInterrupt = pdTRUE;
+
+            /* Used to indicate whether the simulated interrupt processing has
+            necessitated a context switch to another task/thread. */
+            ulSwitchRequired = pdFALSE;
+
+            /* For each interrupt we are interested in processing, each of which is
+            represented by a bit in the 32bit ulPendingInterrupts variable. */
+            for( i = 0; i < portMAX_INTERRUPTS; i++ )
             {
-                /* Is a handler installed? */
-                if( ulIsrHandler[ i ] != NULL )
+                /* Is the simulated interrupt pending? */
+                if( ( ulPendingInterrupts & ( 1UL << i ) ) != 0 )
                 {
-                    /* Run the actual handler.  Handlers return pdTRUE if they
-                    necessitate a context switch. */
-                    if( ulIsrHandler[ i ]() != pdFALSE )
+                    /* Is a handler installed? */
+                    if( ulIsrHandler[ i ] != NULL )
                     {
-                        /* A bit mask is used purely to help debugging. */
-                        ulSwitchRequired |= ( 1 << i );
+                        /* Run the actual handler.  Handlers return pdTRUE if they
+                        necessitate a context switch. */
+                        if( ulIsrHandler[ i ]() != pdFALSE )
+                        {
+                            /* A bit mask is used purely to help debugging. */
+                            ulSwitchRequired |= ( 1 << i );
+                        }
                     }
+
+                    /* Clear the interrupt pending bit. */
+                    ulPendingInterrupts &= ~( 1UL << i );
                 }
-
-                /* Clear the interrupt pending bit. */
-                ulPendingInterrupts &= ~( 1UL << i );
             }
-        }
 
-        if( ulSwitchRequired != pdFALSE )
-        {
-            void *pvOldCurrentTCB;
-
-            pvOldCurrentTCB = pxCurrentTCB;
-
-            /* Select the next task to run. */
-            vTaskSwitchContext();
-
-            /* If the task selected to enter the running state is not the task
-            that is already in the running state. */
-            if( pvOldCurrentTCB != pxCurrentTCB )
+            if( ulSwitchRequired != pdFALSE )
             {
-                /* Suspend the old thread.  In the cases where the (simulated)
-                interrupt is asynchronous (tick event swapping a task out rather
-                than a task blocking or yielding) it doesn't matter if the
-                'suspend' operation doesn't take effect immediately - if it
-                doesn't it would just be like the interrupt occurring slightly
-                later.  In cases where the yield was caused by a task blocking
-                or yielding then the task will block on a yield event after the
-                yield operation in case the 'suspend' operation doesn't take
-                effect immediately.  */
-                pxThreadState = ( ThreadState_t *) *( ( size_t * ) pvOldCurrentTCB );
-                SuspendThread( pxThreadState->pvThread );
+                void *pvOldCurrentTCB;
 
-                /* Ensure the thread is actually suspended by performing a
-                synchronous operation that can only complete when the thread is
-                actually suspended.  The below code asks for dummy register
-                data.  Experimentation shows that these two lines don't appear
-                to do anything now, but according to
-                https://devblogs.microsoft.com/oldnewthing/20150205-00/?p=44743
-                they do - so as they do not harm (slight run-time hit). */
-                xContext.ContextFlags = CONTEXT_INTEGER;
-                ( void ) GetThreadContext( pxThreadState->pvThread, &xContext );
+                pvOldCurrentTCB = pxCurrentTCB;
 
-                /* Obtain the state of the task now selected to enter the
-                Running state. */
-                pxThreadState = ( ThreadState_t * ) ( *( size_t *) pxCurrentTCB );
+                /* Select the next task to run. */
+                vTaskSwitchContext();
 
-                /* pxThreadState->pvThread can be NULL if the task deleted
-                itself - but a deleted task should never be resumed here. */
-                configASSERT( pxThreadState->pvThread != NULL );
-                ResumeThread( pxThreadState->pvThread );
+                /* If the task selected to enter the running state is not the task
+                that is already in the running state. */
+                if( pvOldCurrentTCB != pxCurrentTCB )
+                {
+                    /* Suspend the old thread.  In the cases where the (simulated)
+                    interrupt is asynchronous (tick event swapping a task out rather
+                    than a task blocking or yielding) it doesn't matter if the
+                    'suspend' operation doesn't take effect immediately - if it
+                    doesn't it would just be like the interrupt occurring slightly
+                    later.  In cases where the yield was caused by a task blocking
+                    or yielding then the task will block on a yield event after the
+                    yield operation in case the 'suspend' operation doesn't take
+                    effect immediately.  */
+                    pxThreadState = ( ThreadState_t *) *( ( size_t * ) pvOldCurrentTCB );
+                    SuspendThread( pxThreadState->pvThread );
+
+                    /* Ensure the thread is actually suspended by performing a
+                    synchronous operation that can only complete when the thread is
+                    actually suspended.  The below code asks for dummy register
+                    data.  Experimentation shows that these two lines don't appear
+                    to do anything now, but according to
+                    https://devblogs.microsoft.com/oldnewthing/20150205-00/?p=44743
+                    they do - so as they do not harm (slight run-time hit). */
+                    xContext.ContextFlags = CONTEXT_INTEGER;
+                    ( void ) GetThreadContext( pxThreadState->pvThread, &xContext );
+
+                    /* Obtain the state of the task now selected to enter the
+                    Running state. */
+                    pxThreadState = ( ThreadState_t * ) ( *( size_t *) pxCurrentTCB );
+
+                    /* pxThreadState->pvThread can be NULL if the task deleted
+                    itself - but a deleted task should never be resumed here. */
+                    configASSERT( pxThreadState->pvThread != NULL );
+                    ResumeThread( pxThreadState->pvThread );
+                }
             }
-        }
 
-        /* If the thread that is about to be resumed stopped running
-        because it yielded then it will wait on an event when it resumed
-        (to ensure it does not continue running after the call to
-        SuspendThread() above as SuspendThread() is asynchronous).
-        Signal the event to ensure the thread can proceed now it is
-        valid for it to do so.  Signaling the event is benign in the case that
-        the task was switched out asynchronously by an interrupt as the event
-        is reset before the task blocks on it. */
-        pxThreadState = ( ThreadState_t * ) ( *( size_t *) pxCurrentTCB );
-        SetEvent( pxThreadState->pvYieldEvent );
-        ReleaseMutex( pvInterruptEventMutex );
+            /* If the thread that is about to be resumed stopped running
+            because it yielded then it will wait on an event when it resumed
+            (to ensure it does not continue running after the call to
+            SuspendThread() above as SuspendThread() is asynchronous).
+            Signal the event to ensure the thread can proceed now it is
+            valid for it to do so.  Signaling the event is benign in the case that
+            the task was switched out asynchronously by an interrupt as the event
+            is reset before the task blocks on it. */
+            pxThreadState = ( ThreadState_t * ) ( *( size_t *) pxCurrentTCB );
+            SetEvent( pxThreadState->pvYieldEvent );
+            ReleaseMutex( pvInterruptEventMutex );
+        }
     }
 }
 /*-----------------------------------------------------------*/

From 0066c28cb2602e195940afd6c5bf028e84f5ad0b Mon Sep 17 00:00:00 2001
From: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Date: Mon, 31 Jul 2023 19:42:59 +0530
Subject: [PATCH 023/424] Update submodule pointer for contributed Ports (#733)

Update submodule pointer for partners supported and community supported
ports.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 portable/ThirdParty/Community-Supported-Ports | 2 +-
 portable/ThirdParty/Partner-Supported-Ports   | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/portable/ThirdParty/Community-Supported-Ports b/portable/ThirdParty/Community-Supported-Ports
index 4273ca321..d4cccca29 160000
--- a/portable/ThirdParty/Community-Supported-Ports
+++ b/portable/ThirdParty/Community-Supported-Ports
@@ -1 +1 @@
-Subproject commit 4273ca3211b99914f31518378fb590fbff064953
+Subproject commit d4cccca2971d6ffca581564f8142069cb854bd15
diff --git a/portable/ThirdParty/Partner-Supported-Ports b/portable/ThirdParty/Partner-Supported-Ports
index 3f9c99a68..d38f59dbc 160000
--- a/portable/ThirdParty/Partner-Supported-Ports
+++ b/portable/ThirdParty/Partner-Supported-Ports
@@ -1 +1 @@
-Subproject commit 3f9c99a682c5c796bb7eb89fd9c4385688fce27a
+Subproject commit d38f59dbcdfabbe71361764e194e1ad6202f902c

From b51a37314cac084b4c5753f1dfcebd3caf967390 Mon Sep 17 00:00:00 2001
From: kar-rahul-aws <118818625+kar-rahul-aws@users.noreply.github.com>
Date: Tue, 1 Aug 2023 20:12:58 +0530
Subject: [PATCH 024/424] Update MPU wrapper for xTimerGenericCommand API
 (#734)

* Update xTimerGenericCommand API as per SMP branch

Signed-off-by: kar-rahul-aws <karahulx@amazon.com>

* Fix formatting

* Code review changes

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Fix Formatting

---------

Signed-off-by: kar-rahul-aws <karahulx@amazon.com>
Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 include/mpu_prototypes.h                      | 15 +++--
 include/mpu_wrappers.h                        | 11 ++--
 .../GCC/ARM_CM23/mpu_wrappers_v2_asm.c        | 59 +++++++++--------
 .../GCC/ARM_CM23_NTZ/mpu_wrappers_v2_asm.c    | 59 +++++++++--------
 .../GCC/ARM_CM33/mpu_wrappers_v2_asm.c        | 58 ++++++++---------
 .../GCC/ARM_CM33_NTZ/mpu_wrappers_v2_asm.c    | 58 ++++++++---------
 .../IAR/ARM_CM23/mpu_wrappers_v2_asm.S        | 28 ++++-----
 .../IAR/ARM_CM23_NTZ/mpu_wrappers_v2_asm.S    | 28 ++++-----
 .../IAR/ARM_CM33/mpu_wrappers_v2_asm.S        | 28 ++++-----
 .../IAR/ARM_CM33_NTZ/mpu_wrappers_v2_asm.S    | 28 ++++-----
 portable/Common/mpu_wrappers.c                | 14 ++---
 portable/Common/mpu_wrappers_v2.c             | 63 +++++++++++++++----
 .../ARM_CM23/non_secure/mpu_wrappers_v2_asm.c | 59 +++++++++--------
 .../non_secure/mpu_wrappers_v2_asm.c          | 59 +++++++++--------
 .../ARM_CM33/non_secure/mpu_wrappers_v2_asm.c | 58 ++++++++---------
 .../non_secure/mpu_wrappers_v2_asm.c          | 58 ++++++++---------
 .../non_secure/mpu_wrappers_v2_asm.c          | 58 ++++++++---------
 .../non_secure/mpu_wrappers_v2_asm.c          | 58 ++++++++---------
 .../GCC/ARM_CM3_MPU/mpu_wrappers_v2_asm.c     | 58 ++++++++---------
 .../GCC/ARM_CM4_MPU/mpu_wrappers_v2_asm.c     | 58 ++++++++---------
 .../ARM_CM55/non_secure/mpu_wrappers_v2_asm.c | 58 ++++++++---------
 .../non_secure/mpu_wrappers_v2_asm.c          | 58 ++++++++---------
 .../ARM_CM85/non_secure/mpu_wrappers_v2_asm.c | 58 ++++++++---------
 .../non_secure/mpu_wrappers_v2_asm.c          | 58 ++++++++---------
 .../ARM_CM23/non_secure/mpu_wrappers_v2_asm.S | 28 ++++-----
 .../non_secure/mpu_wrappers_v2_asm.S          | 28 ++++-----
 .../ARM_CM33/non_secure/mpu_wrappers_v2_asm.S | 28 ++++-----
 .../non_secure/mpu_wrappers_v2_asm.S          | 28 ++++-----
 .../non_secure/mpu_wrappers_v2_asm.S          | 28 ++++-----
 .../non_secure/mpu_wrappers_v2_asm.S          | 28 ++++-----
 .../IAR/ARM_CM4F_MPU/mpu_wrappers_v2_asm.S    | 28 ++++-----
 .../ARM_CM55/non_secure/mpu_wrappers_v2_asm.S | 28 ++++-----
 .../non_secure/mpu_wrappers_v2_asm.S          | 28 ++++-----
 .../ARM_CM85/non_secure/mpu_wrappers_v2_asm.S | 28 ++++-----
 .../non_secure/mpu_wrappers_v2_asm.S          | 28 ++++-----
 .../RVDS/ARM_CM4_MPU/mpu_wrappers_v2_asm.c    | 37 +++++------
 36 files changed, 693 insertions(+), 799 deletions(-)

diff --git a/include/mpu_prototypes.h b/include/mpu_prototypes.h
index 633efd4a8..2b6b6cb82 100644
--- a/include/mpu_prototypes.h
+++ b/include/mpu_prototypes.h
@@ -223,11 +223,11 @@ void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
                            void * pvNewID ) FREERTOS_SYSTEM_CALL;
 BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
 TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer,
-                                     const BaseType_t xCommandID,
-                                     const TickType_t xOptionalValue,
-                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                     const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                             const BaseType_t xCommandID,
+                                             const TickType_t xOptionalValue,
+                                             BaseType_t * const pxHigherPriorityTaskWoken,
+                                             const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
 const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
 void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
                               const UBaseType_t uxAutoReload ) FREERTOS_SYSTEM_CALL;
@@ -252,6 +252,11 @@ TimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName,
                                       StaticTimer_t * pxTimerBuffer ) PRIVILEGED_FUNCTION;
 BaseType_t MPU_xTimerGetStaticBuffer( TimerHandle_t xTimer,
                                       StaticTimer_t ** ppxTimerBuffer ) PRIVILEGED_FUNCTION;
+BaseType_t MPU_xTimerGenericCommandFromISR( TimerHandle_t xTimer,
+                                            const BaseType_t xCommandID,
+                                            const TickType_t xOptionalValue,
+                                            BaseType_t * const pxHigherPriorityTaskWoken,
+                                            const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
 
 /* MPU versions of event_group.h API functions. */
 EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
diff --git a/include/mpu_wrappers.h b/include/mpu_wrappers.h
index 020efc3ef..a0ebf6030 100644
--- a/include/mpu_wrappers.h
+++ b/include/mpu_wrappers.h
@@ -156,7 +156,7 @@
         #define vTimerSetTimerID                  MPU_vTimerSetTimerID
         #define xTimerIsTimerActive               MPU_xTimerIsTimerActive
         #define xTimerGetTimerDaemonTaskHandle    MPU_xTimerGetTimerDaemonTaskHandle
-        #define xTimerGenericCommand              MPU_xTimerGenericCommand
+        #define xTimerGenericCommandFromTask      MPU_xTimerGenericCommandFromTask
         #define pcTimerGetName                    MPU_pcTimerGetName
         #define vTimerSetReloadMode               MPU_vTimerSetReloadMode
         #define uxTimerGetReloadMode              MPU_uxTimerGetReloadMode
@@ -167,10 +167,11 @@
  * the application can use opaque handles maintained in mpu_wrappers.c
  * with all the APIs. */
         #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
-            #define xTimerGetReloadMode      MPU_xTimerGetReloadMode
-            #define xTimerCreate             MPU_xTimerCreate
-            #define xTimerCreateStatic       MPU_xTimerCreateStatic
-            #define xTimerGetStaticBuffer    MPU_xTimerGetStaticBuffer
+            #define xTimerGetReloadMode            MPU_xTimerGetReloadMode
+            #define xTimerCreate                   MPU_xTimerCreate
+            #define xTimerCreateStatic             MPU_xTimerCreateStatic
+            #define xTimerGetStaticBuffer          MPU_xTimerGetStaticBuffer
+            #define xTimerGenericCommandFromISR    MPU_xTimerGenericCommandFromISR
         #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 /* Map standard event_group.h API functions to the MPU equivalents. */
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/mpu_wrappers_v2_asm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/mpu_wrappers_v2_asm.c
index a1e5ce082..795f2195c 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/mpu_wrappers_v2_asm.c
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/mpu_wrappers_v2_asm.c
@@ -1726,41 +1726,38 @@ TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( nake
 
 #if ( configUSE_TIMERS == 1 )
 
-BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer,
-                                     const BaseType_t xCommandID,
-                                     const TickType_t xOptionalValue,
-                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                     const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                             const BaseType_t xCommandID,
+                                             const TickType_t xOptionalValue,
+                                             BaseType_t * const pxHigherPriorityTaskWoken,
+                                             const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer,
-                                     const BaseType_t xCommandID,
-                                     const TickType_t xOptionalValue,
-                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                     const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                             const BaseType_t xCommandID,
+                                             const TickType_t xOptionalValue,
+                                             BaseType_t * const pxHigherPriorityTaskWoken,
+                                             const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
 {
     __asm volatile
     (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGenericCommandImpl                  \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, ipsr                                          \n"
-        " cmp r0, #0                                            \n"
-        " bne MPU_xTimerGenericCommand_Priv                     \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " beq MPU_xTimerGenericCommand_Priv                     \n"
-        " MPU_xTimerGenericCommand_Unpriv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGenericCommandImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        " MPU_xTimerGenericCommand_Priv:                        \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTimerGenericCommandImpl                    \n"
-        "                                                       \n"
+        " .syntax unified                                               \n"
+        " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
+        "                                                               \n"
+        " push {r0, r1}                                                 \n"
+        " mrs r0, control                                               \n"
+        " movs r1, #1                                                   \n"
+        " tst r0, r1                                                    \n"
+        " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
+        " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
+        "     pop {r0, r1}                                              \n"
+        "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
+        " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
+        "     pop {r0, r1}                                              \n"
+        "     svc %0                                                    \n"
+        "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
+        "     svc %1                                                    \n"
+        "     bx lr                                                     \n"
+        "                                                               \n"
         : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
     );
 }
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/mpu_wrappers_v2_asm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/mpu_wrappers_v2_asm.c
index a1e5ce082..795f2195c 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/mpu_wrappers_v2_asm.c
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/mpu_wrappers_v2_asm.c
@@ -1726,41 +1726,38 @@ TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( nake
 
 #if ( configUSE_TIMERS == 1 )
 
-BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer,
-                                     const BaseType_t xCommandID,
-                                     const TickType_t xOptionalValue,
-                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                     const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                             const BaseType_t xCommandID,
+                                             const TickType_t xOptionalValue,
+                                             BaseType_t * const pxHigherPriorityTaskWoken,
+                                             const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer,
-                                     const BaseType_t xCommandID,
-                                     const TickType_t xOptionalValue,
-                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                     const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                             const BaseType_t xCommandID,
+                                             const TickType_t xOptionalValue,
+                                             BaseType_t * const pxHigherPriorityTaskWoken,
+                                             const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
 {
     __asm volatile
     (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGenericCommandImpl                  \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, ipsr                                          \n"
-        " cmp r0, #0                                            \n"
-        " bne MPU_xTimerGenericCommand_Priv                     \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " beq MPU_xTimerGenericCommand_Priv                     \n"
-        " MPU_xTimerGenericCommand_Unpriv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGenericCommandImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        " MPU_xTimerGenericCommand_Priv:                        \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTimerGenericCommandImpl                    \n"
-        "                                                       \n"
+        " .syntax unified                                               \n"
+        " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
+        "                                                               \n"
+        " push {r0, r1}                                                 \n"
+        " mrs r0, control                                               \n"
+        " movs r1, #1                                                   \n"
+        " tst r0, r1                                                    \n"
+        " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
+        " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
+        "     pop {r0, r1}                                              \n"
+        "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
+        " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
+        "     pop {r0, r1}                                              \n"
+        "     svc %0                                                    \n"
+        "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
+        "     svc %1                                                    \n"
+        "     bx lr                                                     \n"
+        "                                                               \n"
         : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
     );
 }
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/mpu_wrappers_v2_asm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/mpu_wrappers_v2_asm.c
index 6e2043427..9e1b9ed85 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/mpu_wrappers_v2_asm.c
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/mpu_wrappers_v2_asm.c
@@ -1676,41 +1676,37 @@ TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( nake
 
 #if ( configUSE_TIMERS == 1 )
 
-BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer,
-                                     const BaseType_t xCommandID,
-                                     const TickType_t xOptionalValue,
-                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                     const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                             const BaseType_t xCommandID,
+                                             const TickType_t xOptionalValue,
+                                             BaseType_t * const pxHigherPriorityTaskWoken,
+                                             const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer,
-                                     const BaseType_t xCommandID,
-                                     const TickType_t xOptionalValue,
-                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                     const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                             const BaseType_t xCommandID,
+                                             const TickType_t xOptionalValue,
+                                             BaseType_t * const pxHigherPriorityTaskWoken,
+                                             const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
 {
     __asm volatile
     (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGenericCommandImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, ipsr                                          \n"
-        " cmp r0, #0                                            \n"
-        " bne MPU_xTimerGenericCommand_Priv                     \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " beq MPU_xTimerGenericCommand_Priv                     \n"
-        " MPU_xTimerGenericCommand_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGenericCommandImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        " MPU_xTimerGenericCommand_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerGenericCommandImpl                    \n"
-        "                                                       \n"
-        "                                                       \n"
+        " .syntax unified                                               \n"
+        " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
+        "                                                               \n"
+        " push {r0}                                                     \n"
+        " mrs r0, control                                               \n"
+        " tst r0, #1                                                    \n"
+        " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
+        " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
+        "     pop {r0}                                                  \n"
+        "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
+        " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
+        "     pop {r0}                                                  \n"
+        "     svc %0                                                    \n"
+        "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
+        "     svc %1                                                    \n"
+        "     bx lr                                                     \n"
+        "                                                               \n"
         : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
     );
 }
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/mpu_wrappers_v2_asm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/mpu_wrappers_v2_asm.c
index 6e2043427..9e1b9ed85 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/mpu_wrappers_v2_asm.c
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/mpu_wrappers_v2_asm.c
@@ -1676,41 +1676,37 @@ TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( nake
 
 #if ( configUSE_TIMERS == 1 )
 
-BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer,
-                                     const BaseType_t xCommandID,
-                                     const TickType_t xOptionalValue,
-                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                     const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                             const BaseType_t xCommandID,
+                                             const TickType_t xOptionalValue,
+                                             BaseType_t * const pxHigherPriorityTaskWoken,
+                                             const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer,
-                                     const BaseType_t xCommandID,
-                                     const TickType_t xOptionalValue,
-                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                     const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                             const BaseType_t xCommandID,
+                                             const TickType_t xOptionalValue,
+                                             BaseType_t * const pxHigherPriorityTaskWoken,
+                                             const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
 {
     __asm volatile
     (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGenericCommandImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, ipsr                                          \n"
-        " cmp r0, #0                                            \n"
-        " bne MPU_xTimerGenericCommand_Priv                     \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " beq MPU_xTimerGenericCommand_Priv                     \n"
-        " MPU_xTimerGenericCommand_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGenericCommandImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        " MPU_xTimerGenericCommand_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerGenericCommandImpl                    \n"
-        "                                                       \n"
-        "                                                       \n"
+        " .syntax unified                                               \n"
+        " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
+        "                                                               \n"
+        " push {r0}                                                     \n"
+        " mrs r0, control                                               \n"
+        " tst r0, #1                                                    \n"
+        " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
+        " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
+        "     pop {r0}                                                  \n"
+        "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
+        " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
+        "     pop {r0}                                                  \n"
+        "     svc %0                                                    \n"
+        "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
+        "     svc %1                                                    \n"
+        "     bx lr                                                     \n"
+        "                                                               \n"
         : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
     );
 }
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/mpu_wrappers_v2_asm.S b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/mpu_wrappers_v2_asm.S
index 867642b5e..f2098b57d 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/mpu_wrappers_v2_asm.S
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/mpu_wrappers_v2_asm.S
@@ -945,28 +945,22 @@ MPU_xTimerGetTimerDaemonTaskHandle:
         bx lr
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xTimerGenericCommand
-MPU_xTimerGenericCommand:
+    PUBLIC MPU_xTimerGenericCommandFromTask
+MPU_xTimerGenericCommandFromTask:
     push {r0, r1}
-    /* This function can be called from ISR also and therefore, we need a check
-     * to take privileged path, if called from ISR. */
-    mrs r0, ipsr
-    cmp r0, #0
-    bne MPU_xTimerGenericCommand_Priv
     mrs r0, control
     movs r1, #1
     tst r0, r1
-    beq MPU_xTimerGenericCommand_Priv
-    MPU_xTimerGenericCommand_Unpriv:
+    bne MPU_xTimerGenericCommandFromTask_Unpriv
+    MPU_xTimerGenericCommandFromTask_Priv:
+        pop {r0, r1}
+        b MPU_xTimerGenericCommandFromTaskImpl
+    MPU_xTimerGenericCommandFromTask_Unpriv:
         pop {r0, r1}
         svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTimerGenericCommandImpl
+        bl MPU_xTimerGenericCommandFromTaskImpl
         svc #portSVC_SYSTEM_CALL_EXIT
         bx lr
-    MPU_xTimerGenericCommand_Priv:
-        pop {r0, r1}
-        b MPU_xTimerGenericCommandImpl
-
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pcTimerGetName
@@ -1532,9 +1526,9 @@ MPU_xTimerIsTimerActiveImpl:
 MPU_xTimerGetTimerDaemonTaskHandleImpl:
     b MPU_xTimerGetTimerDaemonTaskHandleImpl
 
-    PUBWEAK MPU_xTimerGenericCommandImpl
-MPU_xTimerGenericCommandImpl:
-    b MPU_xTimerGenericCommandImpl
+    PUBWEAK MPU_xTimerGenericCommandFromTaskImpl
+MPU_xTimerGenericCommandFromTaskImpl:
+    b MPU_xTimerGenericCommandFromTaskImpl
 
     PUBWEAK MPU_pcTimerGetNameImpl
 MPU_pcTimerGetNameImpl:
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/mpu_wrappers_v2_asm.S b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/mpu_wrappers_v2_asm.S
index 867642b5e..f2098b57d 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/mpu_wrappers_v2_asm.S
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/mpu_wrappers_v2_asm.S
@@ -945,28 +945,22 @@ MPU_xTimerGetTimerDaemonTaskHandle:
         bx lr
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xTimerGenericCommand
-MPU_xTimerGenericCommand:
+    PUBLIC MPU_xTimerGenericCommandFromTask
+MPU_xTimerGenericCommandFromTask:
     push {r0, r1}
-    /* This function can be called from ISR also and therefore, we need a check
-     * to take privileged path, if called from ISR. */
-    mrs r0, ipsr
-    cmp r0, #0
-    bne MPU_xTimerGenericCommand_Priv
     mrs r0, control
     movs r1, #1
     tst r0, r1
-    beq MPU_xTimerGenericCommand_Priv
-    MPU_xTimerGenericCommand_Unpriv:
+    bne MPU_xTimerGenericCommandFromTask_Unpriv
+    MPU_xTimerGenericCommandFromTask_Priv:
+        pop {r0, r1}
+        b MPU_xTimerGenericCommandFromTaskImpl
+    MPU_xTimerGenericCommandFromTask_Unpriv:
         pop {r0, r1}
         svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTimerGenericCommandImpl
+        bl MPU_xTimerGenericCommandFromTaskImpl
         svc #portSVC_SYSTEM_CALL_EXIT
         bx lr
-    MPU_xTimerGenericCommand_Priv:
-        pop {r0, r1}
-        b MPU_xTimerGenericCommandImpl
-
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pcTimerGetName
@@ -1532,9 +1526,9 @@ MPU_xTimerIsTimerActiveImpl:
 MPU_xTimerGetTimerDaemonTaskHandleImpl:
     b MPU_xTimerGetTimerDaemonTaskHandleImpl
 
-    PUBWEAK MPU_xTimerGenericCommandImpl
-MPU_xTimerGenericCommandImpl:
-    b MPU_xTimerGenericCommandImpl
+    PUBWEAK MPU_xTimerGenericCommandFromTaskImpl
+MPU_xTimerGenericCommandFromTaskImpl:
+    b MPU_xTimerGenericCommandFromTaskImpl
 
     PUBWEAK MPU_pcTimerGetNameImpl
 MPU_pcTimerGetNameImpl:
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/mpu_wrappers_v2_asm.S b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/mpu_wrappers_v2_asm.S
index f051a6073..9cb9a9d72 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/mpu_wrappers_v2_asm.S
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/mpu_wrappers_v2_asm.S
@@ -895,27 +895,21 @@ MPU_xTimerGetTimerDaemonTaskHandle:
         bx lr
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xTimerGenericCommand
-MPU_xTimerGenericCommand:
+    PUBLIC MPU_xTimerGenericCommandFromTask
+MPU_xTimerGenericCommandFromTask:
     push {r0}
-    /* This function can be called from ISR also and therefore, we need a check
-     * to take privileged path, if called from ISR. */
-    mrs r0, ipsr
-    cmp r0, #0
-    bne MPU_xTimerGenericCommand_Priv
     mrs r0, control
     tst r0, #1
-    beq MPU_xTimerGenericCommand_Priv
-    MPU_xTimerGenericCommand_Unpriv:
+    bne MPU_xTimerGenericCommandFromTask_Unpriv
+    MPU_xTimerGenericCommandFromTask_Priv:
+        pop {r0}
+        b MPU_xTimerGenericCommandFromTaskImpl
+    MPU_xTimerGenericCommandFromTask_Unpriv:
         pop {r0}
         svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTimerGenericCommandImpl
+        bl MPU_xTimerGenericCommandFromTaskImpl
         svc #portSVC_SYSTEM_CALL_EXIT
         bx lr
-    MPU_xTimerGenericCommand_Priv:
-        pop {r0}
-        b MPU_xTimerGenericCommandImpl
-
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pcTimerGetName
@@ -1461,9 +1455,9 @@ MPU_xTimerIsTimerActiveImpl:
 MPU_xTimerGetTimerDaemonTaskHandleImpl:
     b MPU_xTimerGetTimerDaemonTaskHandleImpl
 
-    PUBWEAK MPU_xTimerGenericCommandImpl
-MPU_xTimerGenericCommandImpl:
-    b MPU_xTimerGenericCommandImpl
+    PUBWEAK MPU_xTimerGenericCommandFromTaskImpl
+MPU_xTimerGenericCommandFromTaskImpl:
+    b MPU_xTimerGenericCommandFromTaskImpl
 
     PUBWEAK MPU_pcTimerGetNameImpl
 MPU_pcTimerGetNameImpl:
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/mpu_wrappers_v2_asm.S b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/mpu_wrappers_v2_asm.S
index f051a6073..9cb9a9d72 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/mpu_wrappers_v2_asm.S
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/mpu_wrappers_v2_asm.S
@@ -895,27 +895,21 @@ MPU_xTimerGetTimerDaemonTaskHandle:
         bx lr
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xTimerGenericCommand
-MPU_xTimerGenericCommand:
+    PUBLIC MPU_xTimerGenericCommandFromTask
+MPU_xTimerGenericCommandFromTask:
     push {r0}
-    /* This function can be called from ISR also and therefore, we need a check
-     * to take privileged path, if called from ISR. */
-    mrs r0, ipsr
-    cmp r0, #0
-    bne MPU_xTimerGenericCommand_Priv
     mrs r0, control
     tst r0, #1
-    beq MPU_xTimerGenericCommand_Priv
-    MPU_xTimerGenericCommand_Unpriv:
+    bne MPU_xTimerGenericCommandFromTask_Unpriv
+    MPU_xTimerGenericCommandFromTask_Priv:
+        pop {r0}
+        b MPU_xTimerGenericCommandFromTaskImpl
+    MPU_xTimerGenericCommandFromTask_Unpriv:
         pop {r0}
         svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTimerGenericCommandImpl
+        bl MPU_xTimerGenericCommandFromTaskImpl
         svc #portSVC_SYSTEM_CALL_EXIT
         bx lr
-    MPU_xTimerGenericCommand_Priv:
-        pop {r0}
-        b MPU_xTimerGenericCommandImpl
-
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pcTimerGetName
@@ -1461,9 +1455,9 @@ MPU_xTimerIsTimerActiveImpl:
 MPU_xTimerGetTimerDaemonTaskHandleImpl:
     b MPU_xTimerGetTimerDaemonTaskHandleImpl
 
-    PUBWEAK MPU_xTimerGenericCommandImpl
-MPU_xTimerGenericCommandImpl:
-    b MPU_xTimerGenericCommandImpl
+    PUBWEAK MPU_xTimerGenericCommandFromTaskImpl
+MPU_xTimerGenericCommandFromTaskImpl:
+    b MPU_xTimerGenericCommandFromTaskImpl
 
     PUBWEAK MPU_pcTimerGetNameImpl
 MPU_pcTimerGetNameImpl:
diff --git a/portable/Common/mpu_wrappers.c b/portable/Common/mpu_wrappers.c
index c9951956f..e877dcea9 100644
--- a/portable/Common/mpu_wrappers.c
+++ b/portable/Common/mpu_wrappers.c
@@ -1943,11 +1943,11 @@
 /*-----------------------------------------------------------*/
 
     #if ( configUSE_TIMERS == 1 )
-        BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer,
-                                             const BaseType_t xCommandID,
-                                             const TickType_t xOptionalValue,
-                                             BaseType_t * const pxHigherPriorityTaskWoken,
-                                             const TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                                     const BaseType_t xCommandID,
+                                                     const TickType_t xOptionalValue,
+                                                     BaseType_t * const pxHigherPriorityTaskWoken,
+                                                     const TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
         {
             BaseType_t xReturn;
 
@@ -1956,7 +1956,7 @@
                 portRAISE_PRIVILEGE();
                 portMEMORY_BARRIER();
 
-                xReturn = xTimerGenericCommand( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait );
+                xReturn = xTimerGenericCommandFromTask( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait );
                 portMEMORY_BARRIER();
 
                 portRESET_PRIVILEGE();
@@ -1964,7 +1964,7 @@
             }
             else
             {
-                xReturn = xTimerGenericCommand( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait );
+                xReturn = xTimerGenericCommandFromTask( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait );
             }
 
             return xReturn;
diff --git a/portable/Common/mpu_wrappers_v2.c b/portable/Common/mpu_wrappers_v2.c
index 1a976cb50..91a2e7055 100644
--- a/portable/Common/mpu_wrappers_v2.c
+++ b/portable/Common/mpu_wrappers_v2.c
@@ -2917,17 +2917,17 @@
 
     #if ( configUSE_TIMERS == 1 )
 
-        BaseType_t MPU_xTimerGenericCommandImpl( TimerHandle_t xTimer,
-                                                 const BaseType_t xCommandID,
-                                                 const TickType_t xOptionalValue,
-                                                 BaseType_t * const pxHigherPriorityTaskWoken,
-                                                 const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+        BaseType_t MPU_xTimerGenericCommandFromTaskImpl( TimerHandle_t xTimer,
+                                                         const BaseType_t xCommandID,
+                                                         const TickType_t xOptionalValue,
+                                                         BaseType_t * const pxHigherPriorityTaskWoken,
+                                                         const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
 
-        BaseType_t MPU_xTimerGenericCommandImpl( TimerHandle_t xTimer,
-                                                 const BaseType_t xCommandID,
-                                                 const TickType_t xOptionalValue,
-                                                 BaseType_t * const pxHigherPriorityTaskWoken,
-                                                 const TickType_t xTicksToWait ) /* PRIVILEGED_FUNCTION */
+        BaseType_t MPU_xTimerGenericCommandFromTaskImpl( TimerHandle_t xTimer,
+                                                         const BaseType_t xCommandID,
+                                                         const TickType_t xOptionalValue,
+                                                         BaseType_t * const pxHigherPriorityTaskWoken,
+                                                         const TickType_t xTicksToWait ) /* PRIVILEGED_FUNCTION */
         {
             BaseType_t xReturn = pdFALSE;
             TimerHandle_t xInternalTimerHandle = NULL;
@@ -2951,7 +2951,7 @@
 
                     if( xInternalTimerHandle != NULL )
                     {
-                        xReturn = xTimerGenericCommand( xInternalTimerHandle, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait );
+                        xReturn = xTimerGenericCommandFromTask( xInternalTimerHandle, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait );
                     }
                 }
             }
@@ -3232,6 +3232,47 @@
     #endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_TIMERS == 1 ) */
 /*-----------------------------------------------------------*/
 
+    #if ( configUSE_TIMERS == 1 )
+
+        BaseType_t MPU_xTimerGenericCommandFromISR( TimerHandle_t xTimer,
+                                                    const BaseType_t xCommandID,
+                                                    const TickType_t xOptionalValue,
+                                                    BaseType_t * const pxHigherPriorityTaskWoken,
+                                                    const TickType_t xTicksToWait ) /* PRIVILEGED_FUNCTION */
+        {
+            BaseType_t xReturn = pdFALSE;
+            TimerHandle_t xInternalTimerHandle = NULL;
+            int32_t lIndex;
+            BaseType_t xIsHigherPriorityTaskWokenWriteable = pdFALSE;
+
+            if( pxHigherPriorityTaskWoken != NULL )
+            {
+                xIsHigherPriorityTaskWokenWriteable = xPortIsAuthorizedToAccessBuffer( pxHigherPriorityTaskWoken,
+                                                                                       sizeof( BaseType_t ),
+                                                                                       tskMPU_WRITE_PERMISSION );
+            }
+
+            if( ( pxHigherPriorityTaskWoken == NULL ) || ( xIsHigherPriorityTaskWokenWriteable == pdTRUE ) )
+            {
+                lIndex = ( int32_t ) xTimer;
+
+                if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+                {
+                    xInternalTimerHandle = MPU_GetTimerHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                    if( xInternalTimerHandle != NULL )
+                    {
+                        xReturn = xTimerGenericCommandFromISR( xInternalTimerHandle, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait );
+                    }
+                }
+            }
+
+            return xReturn;
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
 /*-----------------------------------------------------------*/
 /*           MPU wrappers for event group APIs.              */
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM23/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM23/non_secure/mpu_wrappers_v2_asm.c
index a1e5ce082..795f2195c 100644
--- a/portable/GCC/ARM_CM23/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM23/non_secure/mpu_wrappers_v2_asm.c
@@ -1726,41 +1726,38 @@ TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( nake
 
 #if ( configUSE_TIMERS == 1 )
 
-BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer,
-                                     const BaseType_t xCommandID,
-                                     const TickType_t xOptionalValue,
-                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                     const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                             const BaseType_t xCommandID,
+                                             const TickType_t xOptionalValue,
+                                             BaseType_t * const pxHigherPriorityTaskWoken,
+                                             const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer,
-                                     const BaseType_t xCommandID,
-                                     const TickType_t xOptionalValue,
-                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                     const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                             const BaseType_t xCommandID,
+                                             const TickType_t xOptionalValue,
+                                             BaseType_t * const pxHigherPriorityTaskWoken,
+                                             const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
 {
     __asm volatile
     (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGenericCommandImpl                  \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, ipsr                                          \n"
-        " cmp r0, #0                                            \n"
-        " bne MPU_xTimerGenericCommand_Priv                     \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " beq MPU_xTimerGenericCommand_Priv                     \n"
-        " MPU_xTimerGenericCommand_Unpriv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGenericCommandImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        " MPU_xTimerGenericCommand_Priv:                        \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTimerGenericCommandImpl                    \n"
-        "                                                       \n"
+        " .syntax unified                                               \n"
+        " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
+        "                                                               \n"
+        " push {r0, r1}                                                 \n"
+        " mrs r0, control                                               \n"
+        " movs r1, #1                                                   \n"
+        " tst r0, r1                                                    \n"
+        " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
+        " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
+        "     pop {r0, r1}                                              \n"
+        "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
+        " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
+        "     pop {r0, r1}                                              \n"
+        "     svc %0                                                    \n"
+        "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
+        "     svc %1                                                    \n"
+        "     bx lr                                                     \n"
+        "                                                               \n"
         : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
     );
 }
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.c
index a1e5ce082..795f2195c 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.c
@@ -1726,41 +1726,38 @@ TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( nake
 
 #if ( configUSE_TIMERS == 1 )
 
-BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer,
-                                     const BaseType_t xCommandID,
-                                     const TickType_t xOptionalValue,
-                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                     const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                             const BaseType_t xCommandID,
+                                             const TickType_t xOptionalValue,
+                                             BaseType_t * const pxHigherPriorityTaskWoken,
+                                             const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer,
-                                     const BaseType_t xCommandID,
-                                     const TickType_t xOptionalValue,
-                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                     const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                             const BaseType_t xCommandID,
+                                             const TickType_t xOptionalValue,
+                                             BaseType_t * const pxHigherPriorityTaskWoken,
+                                             const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
 {
     __asm volatile
     (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGenericCommandImpl                  \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, ipsr                                          \n"
-        " cmp r0, #0                                            \n"
-        " bne MPU_xTimerGenericCommand_Priv                     \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " beq MPU_xTimerGenericCommand_Priv                     \n"
-        " MPU_xTimerGenericCommand_Unpriv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGenericCommandImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        " MPU_xTimerGenericCommand_Priv:                        \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTimerGenericCommandImpl                    \n"
-        "                                                       \n"
+        " .syntax unified                                               \n"
+        " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
+        "                                                               \n"
+        " push {r0, r1}                                                 \n"
+        " mrs r0, control                                               \n"
+        " movs r1, #1                                                   \n"
+        " tst r0, r1                                                    \n"
+        " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
+        " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
+        "     pop {r0, r1}                                              \n"
+        "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
+        " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
+        "     pop {r0, r1}                                              \n"
+        "     svc %0                                                    \n"
+        "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
+        "     svc %1                                                    \n"
+        "     bx lr                                                     \n"
+        "                                                               \n"
         : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
     );
 }
diff --git a/portable/GCC/ARM_CM33/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM33/non_secure/mpu_wrappers_v2_asm.c
index 6e2043427..9e1b9ed85 100644
--- a/portable/GCC/ARM_CM33/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM33/non_secure/mpu_wrappers_v2_asm.c
@@ -1676,41 +1676,37 @@ TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( nake
 
 #if ( configUSE_TIMERS == 1 )
 
-BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer,
-                                     const BaseType_t xCommandID,
-                                     const TickType_t xOptionalValue,
-                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                     const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                             const BaseType_t xCommandID,
+                                             const TickType_t xOptionalValue,
+                                             BaseType_t * const pxHigherPriorityTaskWoken,
+                                             const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer,
-                                     const BaseType_t xCommandID,
-                                     const TickType_t xOptionalValue,
-                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                     const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                             const BaseType_t xCommandID,
+                                             const TickType_t xOptionalValue,
+                                             BaseType_t * const pxHigherPriorityTaskWoken,
+                                             const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
 {
     __asm volatile
     (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGenericCommandImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, ipsr                                          \n"
-        " cmp r0, #0                                            \n"
-        " bne MPU_xTimerGenericCommand_Priv                     \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " beq MPU_xTimerGenericCommand_Priv                     \n"
-        " MPU_xTimerGenericCommand_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGenericCommandImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        " MPU_xTimerGenericCommand_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerGenericCommandImpl                    \n"
-        "                                                       \n"
-        "                                                       \n"
+        " .syntax unified                                               \n"
+        " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
+        "                                                               \n"
+        " push {r0}                                                     \n"
+        " mrs r0, control                                               \n"
+        " tst r0, #1                                                    \n"
+        " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
+        " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
+        "     pop {r0}                                                  \n"
+        "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
+        " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
+        "     pop {r0}                                                  \n"
+        "     svc %0                                                    \n"
+        "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
+        "     svc %1                                                    \n"
+        "     bx lr                                                     \n"
+        "                                                               \n"
         : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
     );
 }
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.c
index 6e2043427..9e1b9ed85 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.c
@@ -1676,41 +1676,37 @@ TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( nake
 
 #if ( configUSE_TIMERS == 1 )
 
-BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer,
-                                     const BaseType_t xCommandID,
-                                     const TickType_t xOptionalValue,
-                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                     const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                             const BaseType_t xCommandID,
+                                             const TickType_t xOptionalValue,
+                                             BaseType_t * const pxHigherPriorityTaskWoken,
+                                             const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer,
-                                     const BaseType_t xCommandID,
-                                     const TickType_t xOptionalValue,
-                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                     const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                             const BaseType_t xCommandID,
+                                             const TickType_t xOptionalValue,
+                                             BaseType_t * const pxHigherPriorityTaskWoken,
+                                             const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
 {
     __asm volatile
     (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGenericCommandImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, ipsr                                          \n"
-        " cmp r0, #0                                            \n"
-        " bne MPU_xTimerGenericCommand_Priv                     \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " beq MPU_xTimerGenericCommand_Priv                     \n"
-        " MPU_xTimerGenericCommand_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGenericCommandImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        " MPU_xTimerGenericCommand_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerGenericCommandImpl                    \n"
-        "                                                       \n"
-        "                                                       \n"
+        " .syntax unified                                               \n"
+        " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
+        "                                                               \n"
+        " push {r0}                                                     \n"
+        " mrs r0, control                                               \n"
+        " tst r0, #1                                                    \n"
+        " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
+        " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
+        "     pop {r0}                                                  \n"
+        "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
+        " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
+        "     pop {r0}                                                  \n"
+        "     svc %0                                                    \n"
+        "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
+        "     svc %1                                                    \n"
+        "     bx lr                                                     \n"
+        "                                                               \n"
         : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
     );
 }
diff --git a/portable/GCC/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.c
index 6e2043427..9e1b9ed85 100644
--- a/portable/GCC/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.c
@@ -1676,41 +1676,37 @@ TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( nake
 
 #if ( configUSE_TIMERS == 1 )
 
-BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer,
-                                     const BaseType_t xCommandID,
-                                     const TickType_t xOptionalValue,
-                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                     const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                             const BaseType_t xCommandID,
+                                             const TickType_t xOptionalValue,
+                                             BaseType_t * const pxHigherPriorityTaskWoken,
+                                             const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer,
-                                     const BaseType_t xCommandID,
-                                     const TickType_t xOptionalValue,
-                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                     const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                             const BaseType_t xCommandID,
+                                             const TickType_t xOptionalValue,
+                                             BaseType_t * const pxHigherPriorityTaskWoken,
+                                             const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
 {
     __asm volatile
     (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGenericCommandImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, ipsr                                          \n"
-        " cmp r0, #0                                            \n"
-        " bne MPU_xTimerGenericCommand_Priv                     \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " beq MPU_xTimerGenericCommand_Priv                     \n"
-        " MPU_xTimerGenericCommand_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGenericCommandImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        " MPU_xTimerGenericCommand_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerGenericCommandImpl                    \n"
-        "                                                       \n"
-        "                                                       \n"
+        " .syntax unified                                               \n"
+        " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
+        "                                                               \n"
+        " push {r0}                                                     \n"
+        " mrs r0, control                                               \n"
+        " tst r0, #1                                                    \n"
+        " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
+        " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
+        "     pop {r0}                                                  \n"
+        "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
+        " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
+        "     pop {r0}                                                  \n"
+        "     svc %0                                                    \n"
+        "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
+        "     svc %1                                                    \n"
+        "     bx lr                                                     \n"
+        "                                                               \n"
         : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
     );
 }
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.c
index 6e2043427..9e1b9ed85 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.c
@@ -1676,41 +1676,37 @@ TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( nake
 
 #if ( configUSE_TIMERS == 1 )
 
-BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer,
-                                     const BaseType_t xCommandID,
-                                     const TickType_t xOptionalValue,
-                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                     const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                             const BaseType_t xCommandID,
+                                             const TickType_t xOptionalValue,
+                                             BaseType_t * const pxHigherPriorityTaskWoken,
+                                             const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer,
-                                     const BaseType_t xCommandID,
-                                     const TickType_t xOptionalValue,
-                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                     const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                             const BaseType_t xCommandID,
+                                             const TickType_t xOptionalValue,
+                                             BaseType_t * const pxHigherPriorityTaskWoken,
+                                             const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
 {
     __asm volatile
     (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGenericCommandImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, ipsr                                          \n"
-        " cmp r0, #0                                            \n"
-        " bne MPU_xTimerGenericCommand_Priv                     \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " beq MPU_xTimerGenericCommand_Priv                     \n"
-        " MPU_xTimerGenericCommand_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGenericCommandImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        " MPU_xTimerGenericCommand_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerGenericCommandImpl                    \n"
-        "                                                       \n"
-        "                                                       \n"
+        " .syntax unified                                               \n"
+        " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
+        "                                                               \n"
+        " push {r0}                                                     \n"
+        " mrs r0, control                                               \n"
+        " tst r0, #1                                                    \n"
+        " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
+        " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
+        "     pop {r0}                                                  \n"
+        "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
+        " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
+        "     pop {r0}                                                  \n"
+        "     svc %0                                                    \n"
+        "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
+        "     svc %1                                                    \n"
+        "     bx lr                                                     \n"
+        "                                                               \n"
         : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
     );
 }
diff --git a/portable/GCC/ARM_CM3_MPU/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM3_MPU/mpu_wrappers_v2_asm.c
index df9239a41..d9aa1a3fd 100644
--- a/portable/GCC/ARM_CM3_MPU/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM3_MPU/mpu_wrappers_v2_asm.c
@@ -1676,41 +1676,37 @@ TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( nake
 
 #if ( configUSE_TIMERS == 1 )
 
-BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer,
-                                     const BaseType_t xCommandID,
-                                     const TickType_t xOptionalValue,
-                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                     const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                             const BaseType_t xCommandID,
+                                             const TickType_t xOptionalValue,
+                                             BaseType_t * const pxHigherPriorityTaskWoken,
+                                             const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer,
-                                     const BaseType_t xCommandID,
-                                     const TickType_t xOptionalValue,
-                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                     const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                             const BaseType_t xCommandID,
+                                             const TickType_t xOptionalValue,
+                                             BaseType_t * const pxHigherPriorityTaskWoken,
+                                             const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
 {
     __asm volatile
     (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGenericCommandImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, ipsr                                          \n"
-        " cmp r0, #0                                            \n"
-        " bne MPU_xTimerGenericCommand_Priv                     \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " beq MPU_xTimerGenericCommand_Priv                     \n"
-        " MPU_xTimerGenericCommand_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGenericCommandImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        " MPU_xTimerGenericCommand_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerGenericCommandImpl                    \n"
-        "                                                       \n"
-        "                                                       \n"
+        " .syntax unified                                               \n"
+        " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
+        "                                                               \n"
+        " push {r0}                                                     \n"
+        " mrs r0, control                                               \n"
+        " tst r0, #1                                                    \n"
+        " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
+        " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
+        "     pop {r0}                                                  \n"
+        "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
+        " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
+        "     pop {r0}                                                  \n"
+        "     svc %0                                                    \n"
+        "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
+        "     svc %1                                                    \n"
+        "     bx lr                                                     \n"
+        "                                                               \n"
         : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
     );
 }
diff --git a/portable/GCC/ARM_CM4_MPU/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM4_MPU/mpu_wrappers_v2_asm.c
index df9239a41..d9aa1a3fd 100644
--- a/portable/GCC/ARM_CM4_MPU/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM4_MPU/mpu_wrappers_v2_asm.c
@@ -1676,41 +1676,37 @@ TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( nake
 
 #if ( configUSE_TIMERS == 1 )
 
-BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer,
-                                     const BaseType_t xCommandID,
-                                     const TickType_t xOptionalValue,
-                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                     const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                             const BaseType_t xCommandID,
+                                             const TickType_t xOptionalValue,
+                                             BaseType_t * const pxHigherPriorityTaskWoken,
+                                             const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer,
-                                     const BaseType_t xCommandID,
-                                     const TickType_t xOptionalValue,
-                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                     const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                             const BaseType_t xCommandID,
+                                             const TickType_t xOptionalValue,
+                                             BaseType_t * const pxHigherPriorityTaskWoken,
+                                             const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
 {
     __asm volatile
     (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGenericCommandImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, ipsr                                          \n"
-        " cmp r0, #0                                            \n"
-        " bne MPU_xTimerGenericCommand_Priv                     \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " beq MPU_xTimerGenericCommand_Priv                     \n"
-        " MPU_xTimerGenericCommand_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGenericCommandImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        " MPU_xTimerGenericCommand_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerGenericCommandImpl                    \n"
-        "                                                       \n"
-        "                                                       \n"
+        " .syntax unified                                               \n"
+        " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
+        "                                                               \n"
+        " push {r0}                                                     \n"
+        " mrs r0, control                                               \n"
+        " tst r0, #1                                                    \n"
+        " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
+        " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
+        "     pop {r0}                                                  \n"
+        "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
+        " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
+        "     pop {r0}                                                  \n"
+        "     svc %0                                                    \n"
+        "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
+        "     svc %1                                                    \n"
+        "     bx lr                                                     \n"
+        "                                                               \n"
         : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
     );
 }
diff --git a/portable/GCC/ARM_CM55/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM55/non_secure/mpu_wrappers_v2_asm.c
index 6e2043427..9e1b9ed85 100644
--- a/portable/GCC/ARM_CM55/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM55/non_secure/mpu_wrappers_v2_asm.c
@@ -1676,41 +1676,37 @@ TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( nake
 
 #if ( configUSE_TIMERS == 1 )
 
-BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer,
-                                     const BaseType_t xCommandID,
-                                     const TickType_t xOptionalValue,
-                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                     const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                             const BaseType_t xCommandID,
+                                             const TickType_t xOptionalValue,
+                                             BaseType_t * const pxHigherPriorityTaskWoken,
+                                             const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer,
-                                     const BaseType_t xCommandID,
-                                     const TickType_t xOptionalValue,
-                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                     const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                             const BaseType_t xCommandID,
+                                             const TickType_t xOptionalValue,
+                                             BaseType_t * const pxHigherPriorityTaskWoken,
+                                             const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
 {
     __asm volatile
     (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGenericCommandImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, ipsr                                          \n"
-        " cmp r0, #0                                            \n"
-        " bne MPU_xTimerGenericCommand_Priv                     \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " beq MPU_xTimerGenericCommand_Priv                     \n"
-        " MPU_xTimerGenericCommand_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGenericCommandImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        " MPU_xTimerGenericCommand_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerGenericCommandImpl                    \n"
-        "                                                       \n"
-        "                                                       \n"
+        " .syntax unified                                               \n"
+        " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
+        "                                                               \n"
+        " push {r0}                                                     \n"
+        " mrs r0, control                                               \n"
+        " tst r0, #1                                                    \n"
+        " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
+        " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
+        "     pop {r0}                                                  \n"
+        "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
+        " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
+        "     pop {r0}                                                  \n"
+        "     svc %0                                                    \n"
+        "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
+        "     svc %1                                                    \n"
+        "     bx lr                                                     \n"
+        "                                                               \n"
         : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
     );
 }
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.c
index 6e2043427..9e1b9ed85 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.c
@@ -1676,41 +1676,37 @@ TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( nake
 
 #if ( configUSE_TIMERS == 1 )
 
-BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer,
-                                     const BaseType_t xCommandID,
-                                     const TickType_t xOptionalValue,
-                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                     const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                             const BaseType_t xCommandID,
+                                             const TickType_t xOptionalValue,
+                                             BaseType_t * const pxHigherPriorityTaskWoken,
+                                             const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer,
-                                     const BaseType_t xCommandID,
-                                     const TickType_t xOptionalValue,
-                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                     const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                             const BaseType_t xCommandID,
+                                             const TickType_t xOptionalValue,
+                                             BaseType_t * const pxHigherPriorityTaskWoken,
+                                             const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
 {
     __asm volatile
     (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGenericCommandImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, ipsr                                          \n"
-        " cmp r0, #0                                            \n"
-        " bne MPU_xTimerGenericCommand_Priv                     \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " beq MPU_xTimerGenericCommand_Priv                     \n"
-        " MPU_xTimerGenericCommand_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGenericCommandImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        " MPU_xTimerGenericCommand_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerGenericCommandImpl                    \n"
-        "                                                       \n"
-        "                                                       \n"
+        " .syntax unified                                               \n"
+        " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
+        "                                                               \n"
+        " push {r0}                                                     \n"
+        " mrs r0, control                                               \n"
+        " tst r0, #1                                                    \n"
+        " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
+        " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
+        "     pop {r0}                                                  \n"
+        "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
+        " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
+        "     pop {r0}                                                  \n"
+        "     svc %0                                                    \n"
+        "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
+        "     svc %1                                                    \n"
+        "     bx lr                                                     \n"
+        "                                                               \n"
         : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
     );
 }
diff --git a/portable/GCC/ARM_CM85/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM85/non_secure/mpu_wrappers_v2_asm.c
index 6e2043427..9e1b9ed85 100644
--- a/portable/GCC/ARM_CM85/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM85/non_secure/mpu_wrappers_v2_asm.c
@@ -1676,41 +1676,37 @@ TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( nake
 
 #if ( configUSE_TIMERS == 1 )
 
-BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer,
-                                     const BaseType_t xCommandID,
-                                     const TickType_t xOptionalValue,
-                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                     const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                             const BaseType_t xCommandID,
+                                             const TickType_t xOptionalValue,
+                                             BaseType_t * const pxHigherPriorityTaskWoken,
+                                             const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer,
-                                     const BaseType_t xCommandID,
-                                     const TickType_t xOptionalValue,
-                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                     const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                             const BaseType_t xCommandID,
+                                             const TickType_t xOptionalValue,
+                                             BaseType_t * const pxHigherPriorityTaskWoken,
+                                             const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
 {
     __asm volatile
     (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGenericCommandImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, ipsr                                          \n"
-        " cmp r0, #0                                            \n"
-        " bne MPU_xTimerGenericCommand_Priv                     \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " beq MPU_xTimerGenericCommand_Priv                     \n"
-        " MPU_xTimerGenericCommand_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGenericCommandImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        " MPU_xTimerGenericCommand_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerGenericCommandImpl                    \n"
-        "                                                       \n"
-        "                                                       \n"
+        " .syntax unified                                               \n"
+        " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
+        "                                                               \n"
+        " push {r0}                                                     \n"
+        " mrs r0, control                                               \n"
+        " tst r0, #1                                                    \n"
+        " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
+        " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
+        "     pop {r0}                                                  \n"
+        "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
+        " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
+        "     pop {r0}                                                  \n"
+        "     svc %0                                                    \n"
+        "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
+        "     svc %1                                                    \n"
+        "     bx lr                                                     \n"
+        "                                                               \n"
         : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
     );
 }
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.c
index 6e2043427..9e1b9ed85 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.c
@@ -1676,41 +1676,37 @@ TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( nake
 
 #if ( configUSE_TIMERS == 1 )
 
-BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer,
-                                     const BaseType_t xCommandID,
-                                     const TickType_t xOptionalValue,
-                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                     const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                             const BaseType_t xCommandID,
+                                             const TickType_t xOptionalValue,
+                                             BaseType_t * const pxHigherPriorityTaskWoken,
+                                             const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer,
-                                     const BaseType_t xCommandID,
-                                     const TickType_t xOptionalValue,
-                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                     const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                             const BaseType_t xCommandID,
+                                             const TickType_t xOptionalValue,
+                                             BaseType_t * const pxHigherPriorityTaskWoken,
+                                             const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
 {
     __asm volatile
     (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGenericCommandImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, ipsr                                          \n"
-        " cmp r0, #0                                            \n"
-        " bne MPU_xTimerGenericCommand_Priv                     \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " beq MPU_xTimerGenericCommand_Priv                     \n"
-        " MPU_xTimerGenericCommand_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGenericCommandImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        " MPU_xTimerGenericCommand_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerGenericCommandImpl                    \n"
-        "                                                       \n"
-        "                                                       \n"
+        " .syntax unified                                               \n"
+        " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
+        "                                                               \n"
+        " push {r0}                                                     \n"
+        " mrs r0, control                                               \n"
+        " tst r0, #1                                                    \n"
+        " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
+        " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
+        "     pop {r0}                                                  \n"
+        "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
+        " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
+        "     pop {r0}                                                  \n"
+        "     svc %0                                                    \n"
+        "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
+        "     svc %1                                                    \n"
+        "     bx lr                                                     \n"
+        "                                                               \n"
         : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
     );
 }
diff --git a/portable/IAR/ARM_CM23/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM23/non_secure/mpu_wrappers_v2_asm.S
index 867642b5e..f2098b57d 100644
--- a/portable/IAR/ARM_CM23/non_secure/mpu_wrappers_v2_asm.S
+++ b/portable/IAR/ARM_CM23/non_secure/mpu_wrappers_v2_asm.S
@@ -945,28 +945,22 @@ MPU_xTimerGetTimerDaemonTaskHandle:
         bx lr
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xTimerGenericCommand
-MPU_xTimerGenericCommand:
+    PUBLIC MPU_xTimerGenericCommandFromTask
+MPU_xTimerGenericCommandFromTask:
     push {r0, r1}
-    /* This function can be called from ISR also and therefore, we need a check
-     * to take privileged path, if called from ISR. */
-    mrs r0, ipsr
-    cmp r0, #0
-    bne MPU_xTimerGenericCommand_Priv
     mrs r0, control
     movs r1, #1
     tst r0, r1
-    beq MPU_xTimerGenericCommand_Priv
-    MPU_xTimerGenericCommand_Unpriv:
+    bne MPU_xTimerGenericCommandFromTask_Unpriv
+    MPU_xTimerGenericCommandFromTask_Priv:
+        pop {r0, r1}
+        b MPU_xTimerGenericCommandFromTaskImpl
+    MPU_xTimerGenericCommandFromTask_Unpriv:
         pop {r0, r1}
         svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTimerGenericCommandImpl
+        bl MPU_xTimerGenericCommandFromTaskImpl
         svc #portSVC_SYSTEM_CALL_EXIT
         bx lr
-    MPU_xTimerGenericCommand_Priv:
-        pop {r0, r1}
-        b MPU_xTimerGenericCommandImpl
-
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pcTimerGetName
@@ -1532,9 +1526,9 @@ MPU_xTimerIsTimerActiveImpl:
 MPU_xTimerGetTimerDaemonTaskHandleImpl:
     b MPU_xTimerGetTimerDaemonTaskHandleImpl
 
-    PUBWEAK MPU_xTimerGenericCommandImpl
-MPU_xTimerGenericCommandImpl:
-    b MPU_xTimerGenericCommandImpl
+    PUBWEAK MPU_xTimerGenericCommandFromTaskImpl
+MPU_xTimerGenericCommandFromTaskImpl:
+    b MPU_xTimerGenericCommandFromTaskImpl
 
     PUBWEAK MPU_pcTimerGetNameImpl
 MPU_pcTimerGetNameImpl:
diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.S
index 867642b5e..f2098b57d 100644
--- a/portable/IAR/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.S
+++ b/portable/IAR/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.S
@@ -945,28 +945,22 @@ MPU_xTimerGetTimerDaemonTaskHandle:
         bx lr
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xTimerGenericCommand
-MPU_xTimerGenericCommand:
+    PUBLIC MPU_xTimerGenericCommandFromTask
+MPU_xTimerGenericCommandFromTask:
     push {r0, r1}
-    /* This function can be called from ISR also and therefore, we need a check
-     * to take privileged path, if called from ISR. */
-    mrs r0, ipsr
-    cmp r0, #0
-    bne MPU_xTimerGenericCommand_Priv
     mrs r0, control
     movs r1, #1
     tst r0, r1
-    beq MPU_xTimerGenericCommand_Priv
-    MPU_xTimerGenericCommand_Unpriv:
+    bne MPU_xTimerGenericCommandFromTask_Unpriv
+    MPU_xTimerGenericCommandFromTask_Priv:
+        pop {r0, r1}
+        b MPU_xTimerGenericCommandFromTaskImpl
+    MPU_xTimerGenericCommandFromTask_Unpriv:
         pop {r0, r1}
         svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTimerGenericCommandImpl
+        bl MPU_xTimerGenericCommandFromTaskImpl
         svc #portSVC_SYSTEM_CALL_EXIT
         bx lr
-    MPU_xTimerGenericCommand_Priv:
-        pop {r0, r1}
-        b MPU_xTimerGenericCommandImpl
-
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pcTimerGetName
@@ -1532,9 +1526,9 @@ MPU_xTimerIsTimerActiveImpl:
 MPU_xTimerGetTimerDaemonTaskHandleImpl:
     b MPU_xTimerGetTimerDaemonTaskHandleImpl
 
-    PUBWEAK MPU_xTimerGenericCommandImpl
-MPU_xTimerGenericCommandImpl:
-    b MPU_xTimerGenericCommandImpl
+    PUBWEAK MPU_xTimerGenericCommandFromTaskImpl
+MPU_xTimerGenericCommandFromTaskImpl:
+    b MPU_xTimerGenericCommandFromTaskImpl
 
     PUBWEAK MPU_pcTimerGetNameImpl
 MPU_pcTimerGetNameImpl:
diff --git a/portable/IAR/ARM_CM33/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM33/non_secure/mpu_wrappers_v2_asm.S
index f051a6073..9cb9a9d72 100644
--- a/portable/IAR/ARM_CM33/non_secure/mpu_wrappers_v2_asm.S
+++ b/portable/IAR/ARM_CM33/non_secure/mpu_wrappers_v2_asm.S
@@ -895,27 +895,21 @@ MPU_xTimerGetTimerDaemonTaskHandle:
         bx lr
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xTimerGenericCommand
-MPU_xTimerGenericCommand:
+    PUBLIC MPU_xTimerGenericCommandFromTask
+MPU_xTimerGenericCommandFromTask:
     push {r0}
-    /* This function can be called from ISR also and therefore, we need a check
-     * to take privileged path, if called from ISR. */
-    mrs r0, ipsr
-    cmp r0, #0
-    bne MPU_xTimerGenericCommand_Priv
     mrs r0, control
     tst r0, #1
-    beq MPU_xTimerGenericCommand_Priv
-    MPU_xTimerGenericCommand_Unpriv:
+    bne MPU_xTimerGenericCommandFromTask_Unpriv
+    MPU_xTimerGenericCommandFromTask_Priv:
+        pop {r0}
+        b MPU_xTimerGenericCommandFromTaskImpl
+    MPU_xTimerGenericCommandFromTask_Unpriv:
         pop {r0}
         svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTimerGenericCommandImpl
+        bl MPU_xTimerGenericCommandFromTaskImpl
         svc #portSVC_SYSTEM_CALL_EXIT
         bx lr
-    MPU_xTimerGenericCommand_Priv:
-        pop {r0}
-        b MPU_xTimerGenericCommandImpl
-
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pcTimerGetName
@@ -1461,9 +1455,9 @@ MPU_xTimerIsTimerActiveImpl:
 MPU_xTimerGetTimerDaemonTaskHandleImpl:
     b MPU_xTimerGetTimerDaemonTaskHandleImpl
 
-    PUBWEAK MPU_xTimerGenericCommandImpl
-MPU_xTimerGenericCommandImpl:
-    b MPU_xTimerGenericCommandImpl
+    PUBWEAK MPU_xTimerGenericCommandFromTaskImpl
+MPU_xTimerGenericCommandFromTaskImpl:
+    b MPU_xTimerGenericCommandFromTaskImpl
 
     PUBWEAK MPU_pcTimerGetNameImpl
 MPU_pcTimerGetNameImpl:
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.S
index f051a6073..9cb9a9d72 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.S
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.S
@@ -895,27 +895,21 @@ MPU_xTimerGetTimerDaemonTaskHandle:
         bx lr
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xTimerGenericCommand
-MPU_xTimerGenericCommand:
+    PUBLIC MPU_xTimerGenericCommandFromTask
+MPU_xTimerGenericCommandFromTask:
     push {r0}
-    /* This function can be called from ISR also and therefore, we need a check
-     * to take privileged path, if called from ISR. */
-    mrs r0, ipsr
-    cmp r0, #0
-    bne MPU_xTimerGenericCommand_Priv
     mrs r0, control
     tst r0, #1
-    beq MPU_xTimerGenericCommand_Priv
-    MPU_xTimerGenericCommand_Unpriv:
+    bne MPU_xTimerGenericCommandFromTask_Unpriv
+    MPU_xTimerGenericCommandFromTask_Priv:
+        pop {r0}
+        b MPU_xTimerGenericCommandFromTaskImpl
+    MPU_xTimerGenericCommandFromTask_Unpriv:
         pop {r0}
         svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTimerGenericCommandImpl
+        bl MPU_xTimerGenericCommandFromTaskImpl
         svc #portSVC_SYSTEM_CALL_EXIT
         bx lr
-    MPU_xTimerGenericCommand_Priv:
-        pop {r0}
-        b MPU_xTimerGenericCommandImpl
-
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pcTimerGetName
@@ -1461,9 +1455,9 @@ MPU_xTimerIsTimerActiveImpl:
 MPU_xTimerGetTimerDaemonTaskHandleImpl:
     b MPU_xTimerGetTimerDaemonTaskHandleImpl
 
-    PUBWEAK MPU_xTimerGenericCommandImpl
-MPU_xTimerGenericCommandImpl:
-    b MPU_xTimerGenericCommandImpl
+    PUBWEAK MPU_xTimerGenericCommandFromTaskImpl
+MPU_xTimerGenericCommandFromTaskImpl:
+    b MPU_xTimerGenericCommandFromTaskImpl
 
     PUBWEAK MPU_pcTimerGetNameImpl
 MPU_pcTimerGetNameImpl:
diff --git a/portable/IAR/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.S
index f051a6073..9cb9a9d72 100644
--- a/portable/IAR/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.S
+++ b/portable/IAR/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.S
@@ -895,27 +895,21 @@ MPU_xTimerGetTimerDaemonTaskHandle:
         bx lr
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xTimerGenericCommand
-MPU_xTimerGenericCommand:
+    PUBLIC MPU_xTimerGenericCommandFromTask
+MPU_xTimerGenericCommandFromTask:
     push {r0}
-    /* This function can be called from ISR also and therefore, we need a check
-     * to take privileged path, if called from ISR. */
-    mrs r0, ipsr
-    cmp r0, #0
-    bne MPU_xTimerGenericCommand_Priv
     mrs r0, control
     tst r0, #1
-    beq MPU_xTimerGenericCommand_Priv
-    MPU_xTimerGenericCommand_Unpriv:
+    bne MPU_xTimerGenericCommandFromTask_Unpriv
+    MPU_xTimerGenericCommandFromTask_Priv:
+        pop {r0}
+        b MPU_xTimerGenericCommandFromTaskImpl
+    MPU_xTimerGenericCommandFromTask_Unpriv:
         pop {r0}
         svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTimerGenericCommandImpl
+        bl MPU_xTimerGenericCommandFromTaskImpl
         svc #portSVC_SYSTEM_CALL_EXIT
         bx lr
-    MPU_xTimerGenericCommand_Priv:
-        pop {r0}
-        b MPU_xTimerGenericCommandImpl
-
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pcTimerGetName
@@ -1461,9 +1455,9 @@ MPU_xTimerIsTimerActiveImpl:
 MPU_xTimerGetTimerDaemonTaskHandleImpl:
     b MPU_xTimerGetTimerDaemonTaskHandleImpl
 
-    PUBWEAK MPU_xTimerGenericCommandImpl
-MPU_xTimerGenericCommandImpl:
-    b MPU_xTimerGenericCommandImpl
+    PUBWEAK MPU_xTimerGenericCommandFromTaskImpl
+MPU_xTimerGenericCommandFromTaskImpl:
+    b MPU_xTimerGenericCommandFromTaskImpl
 
     PUBWEAK MPU_pcTimerGetNameImpl
 MPU_pcTimerGetNameImpl:
diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.S
index f051a6073..9cb9a9d72 100644
--- a/portable/IAR/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.S
+++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.S
@@ -895,27 +895,21 @@ MPU_xTimerGetTimerDaemonTaskHandle:
         bx lr
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xTimerGenericCommand
-MPU_xTimerGenericCommand:
+    PUBLIC MPU_xTimerGenericCommandFromTask
+MPU_xTimerGenericCommandFromTask:
     push {r0}
-    /* This function can be called from ISR also and therefore, we need a check
-     * to take privileged path, if called from ISR. */
-    mrs r0, ipsr
-    cmp r0, #0
-    bne MPU_xTimerGenericCommand_Priv
     mrs r0, control
     tst r0, #1
-    beq MPU_xTimerGenericCommand_Priv
-    MPU_xTimerGenericCommand_Unpriv:
+    bne MPU_xTimerGenericCommandFromTask_Unpriv
+    MPU_xTimerGenericCommandFromTask_Priv:
+        pop {r0}
+        b MPU_xTimerGenericCommandFromTaskImpl
+    MPU_xTimerGenericCommandFromTask_Unpriv:
         pop {r0}
         svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTimerGenericCommandImpl
+        bl MPU_xTimerGenericCommandFromTaskImpl
         svc #portSVC_SYSTEM_CALL_EXIT
         bx lr
-    MPU_xTimerGenericCommand_Priv:
-        pop {r0}
-        b MPU_xTimerGenericCommandImpl
-
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pcTimerGetName
@@ -1461,9 +1455,9 @@ MPU_xTimerIsTimerActiveImpl:
 MPU_xTimerGetTimerDaemonTaskHandleImpl:
     b MPU_xTimerGetTimerDaemonTaskHandleImpl
 
-    PUBWEAK MPU_xTimerGenericCommandImpl
-MPU_xTimerGenericCommandImpl:
-    b MPU_xTimerGenericCommandImpl
+    PUBWEAK MPU_xTimerGenericCommandFromTaskImpl
+MPU_xTimerGenericCommandFromTaskImpl:
+    b MPU_xTimerGenericCommandFromTaskImpl
 
     PUBWEAK MPU_pcTimerGetNameImpl
 MPU_pcTimerGetNameImpl:
diff --git a/portable/IAR/ARM_CM4F_MPU/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM4F_MPU/mpu_wrappers_v2_asm.S
index a0541f790..f18d7410e 100644
--- a/portable/IAR/ARM_CM4F_MPU/mpu_wrappers_v2_asm.S
+++ b/portable/IAR/ARM_CM4F_MPU/mpu_wrappers_v2_asm.S
@@ -899,27 +899,21 @@ MPU_xTimerGetTimerDaemonTaskHandle:
         bx lr
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xTimerGenericCommand
-MPU_xTimerGenericCommand:
+    PUBLIC MPU_xTimerGenericCommandFromTask
+MPU_xTimerGenericCommandFromTask:
     push {r0}
-    /* This function can be called from ISR also and therefore, we need a check
-     * to take privileged path, if called from ISR. */
-    mrs r0, ipsr
-    cmp r0, #0
-    bne MPU_xTimerGenericCommand_Priv
     mrs r0, control
     tst r0, #1
-    beq MPU_xTimerGenericCommand_Priv
-    MPU_xTimerGenericCommand_Unpriv:
+    bne MPU_xTimerGenericCommandFromTask_Unpriv
+    MPU_xTimerGenericCommandFromTask_Priv:
+        pop {r0}
+        b MPU_xTimerGenericCommandFromTaskImpl
+    MPU_xTimerGenericCommandFromTask_Unpriv:
         pop {r0}
         svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTimerGenericCommandImpl
+        bl MPU_xTimerGenericCommandFromTaskImpl
         svc #portSVC_SYSTEM_CALL_EXIT
         bx lr
-    MPU_xTimerGenericCommand_Priv:
-        pop {r0}
-        b MPU_xTimerGenericCommandImpl
-
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pcTimerGetName
@@ -1465,9 +1459,9 @@ MPU_xTimerIsTimerActiveImpl:
 MPU_xTimerGetTimerDaemonTaskHandleImpl:
     b MPU_xTimerGetTimerDaemonTaskHandleImpl
 
-    PUBWEAK MPU_xTimerGenericCommandImpl
-MPU_xTimerGenericCommandImpl:
-    b MPU_xTimerGenericCommandImpl
+    PUBWEAK MPU_xTimerGenericCommandFromTaskImpl
+MPU_xTimerGenericCommandFromTaskImpl:
+    b MPU_xTimerGenericCommandFromTaskImpl
 
     PUBWEAK MPU_pcTimerGetNameImpl
 MPU_pcTimerGetNameImpl:
diff --git a/portable/IAR/ARM_CM55/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM55/non_secure/mpu_wrappers_v2_asm.S
index f051a6073..9cb9a9d72 100644
--- a/portable/IAR/ARM_CM55/non_secure/mpu_wrappers_v2_asm.S
+++ b/portable/IAR/ARM_CM55/non_secure/mpu_wrappers_v2_asm.S
@@ -895,27 +895,21 @@ MPU_xTimerGetTimerDaemonTaskHandle:
         bx lr
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xTimerGenericCommand
-MPU_xTimerGenericCommand:
+    PUBLIC MPU_xTimerGenericCommandFromTask
+MPU_xTimerGenericCommandFromTask:
     push {r0}
-    /* This function can be called from ISR also and therefore, we need a check
-     * to take privileged path, if called from ISR. */
-    mrs r0, ipsr
-    cmp r0, #0
-    bne MPU_xTimerGenericCommand_Priv
     mrs r0, control
     tst r0, #1
-    beq MPU_xTimerGenericCommand_Priv
-    MPU_xTimerGenericCommand_Unpriv:
+    bne MPU_xTimerGenericCommandFromTask_Unpriv
+    MPU_xTimerGenericCommandFromTask_Priv:
+        pop {r0}
+        b MPU_xTimerGenericCommandFromTaskImpl
+    MPU_xTimerGenericCommandFromTask_Unpriv:
         pop {r0}
         svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTimerGenericCommandImpl
+        bl MPU_xTimerGenericCommandFromTaskImpl
         svc #portSVC_SYSTEM_CALL_EXIT
         bx lr
-    MPU_xTimerGenericCommand_Priv:
-        pop {r0}
-        b MPU_xTimerGenericCommandImpl
-
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pcTimerGetName
@@ -1461,9 +1455,9 @@ MPU_xTimerIsTimerActiveImpl:
 MPU_xTimerGetTimerDaemonTaskHandleImpl:
     b MPU_xTimerGetTimerDaemonTaskHandleImpl
 
-    PUBWEAK MPU_xTimerGenericCommandImpl
-MPU_xTimerGenericCommandImpl:
-    b MPU_xTimerGenericCommandImpl
+    PUBWEAK MPU_xTimerGenericCommandFromTaskImpl
+MPU_xTimerGenericCommandFromTaskImpl:
+    b MPU_xTimerGenericCommandFromTaskImpl
 
     PUBWEAK MPU_pcTimerGetNameImpl
 MPU_pcTimerGetNameImpl:
diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.S
index f051a6073..9cb9a9d72 100644
--- a/portable/IAR/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.S
+++ b/portable/IAR/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.S
@@ -895,27 +895,21 @@ MPU_xTimerGetTimerDaemonTaskHandle:
         bx lr
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xTimerGenericCommand
-MPU_xTimerGenericCommand:
+    PUBLIC MPU_xTimerGenericCommandFromTask
+MPU_xTimerGenericCommandFromTask:
     push {r0}
-    /* This function can be called from ISR also and therefore, we need a check
-     * to take privileged path, if called from ISR. */
-    mrs r0, ipsr
-    cmp r0, #0
-    bne MPU_xTimerGenericCommand_Priv
     mrs r0, control
     tst r0, #1
-    beq MPU_xTimerGenericCommand_Priv
-    MPU_xTimerGenericCommand_Unpriv:
+    bne MPU_xTimerGenericCommandFromTask_Unpriv
+    MPU_xTimerGenericCommandFromTask_Priv:
+        pop {r0}
+        b MPU_xTimerGenericCommandFromTaskImpl
+    MPU_xTimerGenericCommandFromTask_Unpriv:
         pop {r0}
         svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTimerGenericCommandImpl
+        bl MPU_xTimerGenericCommandFromTaskImpl
         svc #portSVC_SYSTEM_CALL_EXIT
         bx lr
-    MPU_xTimerGenericCommand_Priv:
-        pop {r0}
-        b MPU_xTimerGenericCommandImpl
-
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pcTimerGetName
@@ -1461,9 +1455,9 @@ MPU_xTimerIsTimerActiveImpl:
 MPU_xTimerGetTimerDaemonTaskHandleImpl:
     b MPU_xTimerGetTimerDaemonTaskHandleImpl
 
-    PUBWEAK MPU_xTimerGenericCommandImpl
-MPU_xTimerGenericCommandImpl:
-    b MPU_xTimerGenericCommandImpl
+    PUBWEAK MPU_xTimerGenericCommandFromTaskImpl
+MPU_xTimerGenericCommandFromTaskImpl:
+    b MPU_xTimerGenericCommandFromTaskImpl
 
     PUBWEAK MPU_pcTimerGetNameImpl
 MPU_pcTimerGetNameImpl:
diff --git a/portable/IAR/ARM_CM85/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM85/non_secure/mpu_wrappers_v2_asm.S
index f051a6073..9cb9a9d72 100644
--- a/portable/IAR/ARM_CM85/non_secure/mpu_wrappers_v2_asm.S
+++ b/portable/IAR/ARM_CM85/non_secure/mpu_wrappers_v2_asm.S
@@ -895,27 +895,21 @@ MPU_xTimerGetTimerDaemonTaskHandle:
         bx lr
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xTimerGenericCommand
-MPU_xTimerGenericCommand:
+    PUBLIC MPU_xTimerGenericCommandFromTask
+MPU_xTimerGenericCommandFromTask:
     push {r0}
-    /* This function can be called from ISR also and therefore, we need a check
-     * to take privileged path, if called from ISR. */
-    mrs r0, ipsr
-    cmp r0, #0
-    bne MPU_xTimerGenericCommand_Priv
     mrs r0, control
     tst r0, #1
-    beq MPU_xTimerGenericCommand_Priv
-    MPU_xTimerGenericCommand_Unpriv:
+    bne MPU_xTimerGenericCommandFromTask_Unpriv
+    MPU_xTimerGenericCommandFromTask_Priv:
+        pop {r0}
+        b MPU_xTimerGenericCommandFromTaskImpl
+    MPU_xTimerGenericCommandFromTask_Unpriv:
         pop {r0}
         svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTimerGenericCommandImpl
+        bl MPU_xTimerGenericCommandFromTaskImpl
         svc #portSVC_SYSTEM_CALL_EXIT
         bx lr
-    MPU_xTimerGenericCommand_Priv:
-        pop {r0}
-        b MPU_xTimerGenericCommandImpl
-
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pcTimerGetName
@@ -1461,9 +1455,9 @@ MPU_xTimerIsTimerActiveImpl:
 MPU_xTimerGetTimerDaemonTaskHandleImpl:
     b MPU_xTimerGetTimerDaemonTaskHandleImpl
 
-    PUBWEAK MPU_xTimerGenericCommandImpl
-MPU_xTimerGenericCommandImpl:
-    b MPU_xTimerGenericCommandImpl
+    PUBWEAK MPU_xTimerGenericCommandFromTaskImpl
+MPU_xTimerGenericCommandFromTaskImpl:
+    b MPU_xTimerGenericCommandFromTaskImpl
 
     PUBWEAK MPU_pcTimerGetNameImpl
 MPU_pcTimerGetNameImpl:
diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.S
index f051a6073..9cb9a9d72 100644
--- a/portable/IAR/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.S
+++ b/portable/IAR/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.S
@@ -895,27 +895,21 @@ MPU_xTimerGetTimerDaemonTaskHandle:
         bx lr
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xTimerGenericCommand
-MPU_xTimerGenericCommand:
+    PUBLIC MPU_xTimerGenericCommandFromTask
+MPU_xTimerGenericCommandFromTask:
     push {r0}
-    /* This function can be called from ISR also and therefore, we need a check
-     * to take privileged path, if called from ISR. */
-    mrs r0, ipsr
-    cmp r0, #0
-    bne MPU_xTimerGenericCommand_Priv
     mrs r0, control
     tst r0, #1
-    beq MPU_xTimerGenericCommand_Priv
-    MPU_xTimerGenericCommand_Unpriv:
+    bne MPU_xTimerGenericCommandFromTask_Unpriv
+    MPU_xTimerGenericCommandFromTask_Priv:
+        pop {r0}
+        b MPU_xTimerGenericCommandFromTaskImpl
+    MPU_xTimerGenericCommandFromTask_Unpriv:
         pop {r0}
         svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTimerGenericCommandImpl
+        bl MPU_xTimerGenericCommandFromTaskImpl
         svc #portSVC_SYSTEM_CALL_EXIT
         bx lr
-    MPU_xTimerGenericCommand_Priv:
-        pop {r0}
-        b MPU_xTimerGenericCommandImpl
-
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pcTimerGetName
@@ -1461,9 +1455,9 @@ MPU_xTimerIsTimerActiveImpl:
 MPU_xTimerGetTimerDaemonTaskHandleImpl:
     b MPU_xTimerGetTimerDaemonTaskHandleImpl
 
-    PUBWEAK MPU_xTimerGenericCommandImpl
-MPU_xTimerGenericCommandImpl:
-    b MPU_xTimerGenericCommandImpl
+    PUBWEAK MPU_xTimerGenericCommandFromTaskImpl
+MPU_xTimerGenericCommandFromTaskImpl:
+    b MPU_xTimerGenericCommandFromTaskImpl
 
     PUBWEAK MPU_pcTimerGetNameImpl
 MPU_pcTimerGetNameImpl:
diff --git a/portable/RVDS/ARM_CM4_MPU/mpu_wrappers_v2_asm.c b/portable/RVDS/ARM_CM4_MPU/mpu_wrappers_v2_asm.c
index aa1e825fc..0de1b53bf 100644
--- a/portable/RVDS/ARM_CM4_MPU/mpu_wrappers_v2_asm.c
+++ b/portable/RVDS/ARM_CM4_MPU/mpu_wrappers_v2_asm.c
@@ -1426,37 +1426,34 @@ MPU_xTimerGetTimerDaemonTaskHandle_Unpriv
 
 #if ( configUSE_TIMERS == 1 )
 
-BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer,
-                                     const BaseType_t xCommandID,
-                                     const TickType_t xOptionalValue,
-                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                     const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                             const BaseType_t xCommandID,
+                                             const TickType_t xOptionalValue,
+                                             BaseType_t * const pxHigherPriorityTaskWoken,
+                                             const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
 
-__asm BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer,
-                                           const BaseType_t xCommandID,
-                                           const TickType_t xOptionalValue,
-                                           BaseType_t * const pxHigherPriorityTaskWoken,
-                                           const TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+__asm BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                                   const BaseType_t xCommandID,
+                                                   const TickType_t xOptionalValue,
+                                                   BaseType_t * const pxHigherPriorityTaskWoken,
+                                                   const TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
 {
     PRESERVE8
-    extern MPU_xTimerGenericCommandImpl
+    extern MPU_xTimerGenericCommandFromTaskImpl
 
     push {r0}
-    mrs r0, ipsr
-    cmp r0, #0
-    bne MPU_xTimerGenericCommand_Priv
     mrs r0, control
     tst r0, #1
-    beq MPU_xTimerGenericCommand_Priv
-MPU_xTimerGenericCommand_Unpriv
+    bne MPU_xTimerGenericCommandFromTask_Unpriv
+MPU_xTimerGenericCommandFromTask_Priv
+        pop {r0}
+        b MPU_xTimerGenericCommandFromTaskImpl
+MPU_xTimerGenericCommandFromTask_Unpriv
         pop {r0}
         svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTimerGenericCommandImpl
+        bl MPU_xTimerGenericCommandFromTaskImpl
         svc #portSVC_SYSTEM_CALL_EXIT
         bx lr
-MPU_xTimerGenericCommand_Priv
-        pop {r0}
-        b MPU_xTimerGenericCommandImpl
 }
 
 #endif /* if ( configUSE_TIMERS == 1 ) */

From 85d2cba801156e507c586621b67d132c6237fec3 Mon Sep 17 00:00:00 2001
From: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Date: Wed, 2 Aug 2023 14:42:45 +0530
Subject: [PATCH 025/424] Fix warning introduced in PR 730 (#735)

The change addresses the following warning:

```
tasks.c:5549:40: warning: assignment discards 'volatile' qualifier from
pointer target type [-Wdiscarded-qualifiers]
 5549 |             pxTaskStatus->pxTopOfStack = pxTCB->pxTopOfStack;
      |
```

Also add the "Build Posix_GCC Demo for Coverage Test" in the PR checks
as coverage test target treats warnings as errors and therefore, will
catch such warnings in PR checks.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 .github/workflows/kernel-demos.yml | 5 +++++
 tasks.c                            | 2 +-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/.github/workflows/kernel-demos.yml b/.github/workflows/kernel-demos.yml
index 865f4eefb..79ed8ca02 100644
--- a/.github/workflows/kernel-demos.yml
+++ b/.github/workflows/kernel-demos.yml
@@ -85,6 +85,11 @@ jobs:
         working-directory: FreeRTOS/Demo/Posix_GCC
         run: make -j
 
+      - name: Build Posix_GCC Demo for Coverage Test
+        shell: bash
+        working-directory: FreeRTOS/Demo/Posix_GCC
+        run: make -j COVERAGE_TEST=1
+
   MSP430-GCC:
     name: GNU MSP430 Toolchain
     runs-on: ubuntu-latest
diff --git a/tasks.c b/tasks.c
index f08215adf..c4e8bd424 100644
--- a/tasks.c
+++ b/tasks.c
@@ -5546,7 +5546,7 @@ static void prvCheckTasksWaitingTermination( void )
         pxTaskStatus->uxCurrentPriority = pxTCB->uxPriority;
         pxTaskStatus->pxStackBase = pxTCB->pxStack;
         #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) )
-            pxTaskStatus->pxTopOfStack = pxTCB->pxTopOfStack;
+            pxTaskStatus->pxTopOfStack = ( StackType_t * ) pxTCB->pxTopOfStack;
             pxTaskStatus->pxEndOfStack = pxTCB->pxEndOfStack;
         #endif
         pxTaskStatus->xTaskNumber = pxTCB->uxTCBNumber;

From 20300df3c33ee48cccc2fbef1f0f58d12ad16812 Mon Sep 17 00:00:00 2001
From: Nikhil Kamath <110539926+amazonKamath@users.noreply.github.com>
Date: Thu, 3 Aug 2023 12:26:59 +0530
Subject: [PATCH 026/424] PR Process for Open Source Contribution (#717)

* Initial Version Pull Request Workflow

* Updated Contributing.md

* Improved contributing.md

* added pr process image and some edits based on peer feedback

* fixed links to image

* Fixed truncation

* Updated reviewer description

* Review feedback

---------

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
---
 .github/CONTRIBUTING.md         |   2 +-
 .github/media/pr_process.png    | Bin 0 -> 183384 bytes
 .github/pull_request_process.md | 115 ++++++++++++++++++++++++++++++++
 3 files changed, 116 insertions(+), 1 deletion(-)
 create mode 100644 .github/media/pr_process.png
 create mode 100644 .github/pull_request_process.md

diff --git a/.github/CONTRIBUTING.md b/.github/CONTRIBUTING.md
index ec5d6e54d..39d075d55 100644
--- a/.github/CONTRIBUTING.md
+++ b/.github/CONTRIBUTING.md
@@ -55,7 +55,7 @@ GitHub provides additional document on [forking a repository](https://help.githu
 
 
 ## Getting your pull request merged
-All pull requests must be approved by our review team before it can be merged in. We appreciate your patience while pull requests are reviewed. The time it takes to review will depend on complexity and consideration of wider implications.
+All pull requests must be approved by our review team before it can be merged in. We appreciate your patience while pull requests are reviewed. The time it takes to review will depend on complexity and consideration of wider implications. For more information on the pull request process, please see the documentation [here](pull_request_process.md).
 
 
 ## Finding contributions to work on
diff --git a/.github/media/pr_process.png b/.github/media/pr_process.png
new file mode 100644
index 0000000000000000000000000000000000000000..0d964c1281a7499481d87cd3a1ebe9ef794418a8
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diff --git a/.github/pull_request_process.md b/.github/pull_request_process.md
new file mode 100644
index 000000000..5e7fedafd
--- /dev/null
+++ b/.github/pull_request_process.md
@@ -0,0 +1,115 @@
+# Pull Request Process
+
+This document explains the stages that a Pull Request (PR) goes through when a pull request is submitted to a git repository in the FreeRTOS organization in Github. Before you start a PR, please read and familiarize yourself with [CONTRIBUTING.md](.github/CONTRIBUTING.md)
+
+## ****Terminologies****
+
+**FreeRTOS Partner Contributors**: These are selected developers and experts from community. 
+
+**FreeRTOS Team**: The FreeRTOS team consists of “AWS employees”. 
+
+**CODEOWNERS**: For all the FreeRTOS repositories, “FreeRTOS Team” and/or “FreeRTOS Partner contributors” will be CODEOWNER.
+
+**Contributor**: The Contributor is the person who submitted the pull request.
+
+**Assignee**: The Assignee is an AWS Employee who is responsible for identifying reviewers  and managing the PR. They track the progress of pull requests and ensure that they are reviewed and merged in a timely manner. 
+
+**Reviewer**: Reviewers are responsible for reviewing pull requests and providing feedback to the contributor. Two approving reviews, one of which must be from the CODEOWNER of the reposiroty, are required for a PR to be merged. 
+
+
+## ****Pull Request Life-Cycle****
+
+Once a pull request (PR) is submitted, it goes through the following stages:
+
+1. Open
+    1. The PR is created.
+    2. All the GitHub Actions pass and the PR is ready to be reviewed. 
+2. Triage
+    1. The PR is assigned to an assignee.
+    2. The assignee assigns a reviewer from the FreeRTOS Team to the PR.
+3. Review
+    1. The reviewer provides feedback and discusses open questions with the contributor, if needed.
+    2. If the contributor and the reviewer conclude, after discussion, that the PR will not be merged, then the PR is closed.
+    3. The PR contributor addresses the feedback and makes changes to the PR, if needed.
+    4. The reviewer approves the PR and assigns a second reviewer.
+4. Second Review
+    1. The second reviewer reviews the PR and provides feedback, if needed.
+    2. The PR contributor addresses the feedback and makes changes to the PR, if needed.
+    3. The second reviewer approves the PR.
+5. Testing
+    1. One of the reviewers tests the PR to ensure that it works correctly.
+6. Ready to Merge  
+   A PR becomes Ready to Merge when all the branch protection rules are satisfied. We have branch protection rules which require the following:
+    1. At least 2 reviews. 
+    2. One review from the CODEOWNER of the given repository. 
+    3. All PR checks must pass.
+7. Merge
+    1. The PR is merged.
+
+</br>
+
+The status of a PR is indicated through GitHub labels added by Reviewers/Assignees. The following are the most common status indicators: Triaged, Reviewer Assigned, Concept ACK/NACK, First Code Review In Progress, First Code Review Complete, Second Code Review In Progress, Second Code Review Complete, Testing In Progress and Testing Complete.
+
+Please note that we may decide to skip some stages depending on the type of PR. For example, a PR with a simple doc update will likely not go through all the above stages, however every PR is required to get approvals from 2 reviewers.
+
+The pictorial representation of our PR process is shown below.
+
+![PR Process](media/pr_process.png)
+
+
+</br>
+
+## **Turnaround Times**
+
+The length of time required to review a PR is unpredictable and varies from PR to PR since it depends on the complexity of the changes, availability of reviewers, and overall workload of the team. We generally attempt to resolve each PR in accordance with the timeframes below, excluding weekends and public holidays:
+
+* Triage: < 24 hours
+* Concept ACK/NACK: 1-2 weeks
+* Code Review: 1-2 weeks
+* Testing: 1-2 weeks
+
+
+## **Addressing the changes requested by reviewers**
+
+The author should address any review comments in 4 weeks or less. If the author is unable to address the comments in that time, we will do one of the following:
+
+* Make the required changes ourselves and merge the pull request.
+* Close the pull request.
+
+</br>
+
+### **Best Practices for Faster Reviews**
+
+Here are some best practices to follow so that your PR gets reviewed quickly. 
+
+1. If you plan to contribute a new feature to FreeRTOS, please get confirmation beforehand that the FreeRTOS team and community want, and will accept, this feature. This is true especially when you plan to make large or significant changes.  To get confirmation and feedback from FreeRTOS Team and  community, create a post in the FreeRTOS forums. 
+2. Smaller is better. Small, focused PR’s are reviewed more quickly and thoroughly, are simpler to rollback, and involve less wasted effort if rejected.  Avoid opening pull requests that span the whole repository.
+3. Don’t mix refactoring, bug fixes and feature development into a single PR. Lets say you are developing feature-x  and you come across poorly named variables or incomplete/incorrect comments. You should consider fixing those, but in a separate PR, not in the same PR as feature-x. 
+4. Comments matter. The code you develop will need to be maintained for a long time. Well placed comments provide context to your reviewers, maintainers and users, and also prevent them from misunderstanding the purpose of the code.  However, DO NOT add comments to explain things which are obvious by just glancing at the code. [Good Read: https://stackoverflow.blog/2021/12/23/best-practices-for-writing-code-comments/]
+5. Test your PR. In your PR, please accompany your changes with suitable unit tests and any other tests that will be helpful, and include descriptions of how to perform any manual tests. Instructions for unit tests can be found at [freertos.org](https://freertos.org/FreeRTOS-Coding-Standard-and-Style-Guide.html#Testing) and [Github](https://github.com/FreeRTOS/FreeRTOS/blob/main/FreeRTOS/Test/CMock/Readme.md)
+
+
+**Push Back its ok:**
+Sometimes reviewers make mistakes. If a reviewer has requested you to make changes and you feel strongly about doing it a certain way, you are free to debate the merits of the requested change with the reviewer, while still following the code of conduct. You might be overruled, but you might also prevail. 
+
+**Be Pragmatic**
+Put a bit of thought into how your PR can be made easier to review and merge. No document can replace common sense and good taste. The best practices shared here and the contribution guidelines, if followed, will help you get your code reviewed and merged with less friction. 
+
+</br>
+
+### **Why is  my PR closed?** 
+
+Pull requests older than 120 days or not in-line with scope of the project will be closed. Exceptions can be made for pull requests that have active review comments, or that are awaiting other dependent pull requests. Closed pull requests are easy to recreate, and little work is lost by closing a pull request that is subsequently reopened. We want to limit the total number of pull requests in flight to:
+
+* Maintain a clean project
+* Remove old pull requests that would be difficult to rebase since the underlying code has changed over time
+* Encourage code velocity
+
+### **Why is my PR not getting reviewed/merged?**
+
+* It may be because of a feature freeze due to an upcoming release. During this time, only bug fixes are taken into consideration. If your pull request is a new feature, it will not be prioritised until after the release. Wait for the release.
+* It could be related to best practices (see contributing.md) not being followed. One common issue is that the pull request is too big to review. Let’s say you’ve touched 21 files and have 9347 insertions. When your would-be reviewers pull up the diffs, they run away - this pull request is going to take a few hours to review and they don’t have a few hours right now. They’ll get to it later, just as soon as they have more free time (ha!).
+* If you think the above two situations are not the reason, and you are not getting some pull request love,  please drop a couple of reminders on the PR comments. If everything else fails, please create a post on FreeRTOS forums with link to PR. 
+
+
+

From dd1b87dae9e6ca358e67b56a045a5737c696720e Mon Sep 17 00:00:00 2001
From: ActoryOu <jay2002824@gmail.com>
Date: Thu, 3 Aug 2023 16:56:42 +0800
Subject: [PATCH 027/424] Fix RP2040 compile warning (#736)

* Fix Pico compile warning -- port layer

* Warning resolved for volatile discard task.c (#5)

---------

Co-authored-by: Pranjal Chanda <40349163+pranjalchanda08@users.noreply.github.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
---
 portable/ThirdParty/GCC/RP2040/port.c | 13 +++++++++----
 tasks.c                               |  2 +-
 2 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/portable/ThirdParty/GCC/RP2040/port.c b/portable/ThirdParty/GCC/RP2040/port.c
index 73452e068..bf0dcf4aa 100644
--- a/portable/ThirdParty/GCC/RP2040/port.c
+++ b/portable/ThirdParty/GCC/RP2040/port.c
@@ -493,7 +493,7 @@ void vPortYield( void )
 void vPortEnableInterrupts( void )
 {
     #if ( configSUPPORT_PICO_SYNC_INTEROP == 1 )
-        int xCoreID = portGET_CORE_ID();
+        int xCoreID = ( int ) portGET_CORE_ID();
         if( pxYieldSpinLock[xCoreID] )
         {
             spin_lock_t* const pxTmpLock = pxYieldSpinLock[xCoreID];
@@ -530,7 +530,12 @@ void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask )
 
 void vYieldCore( int xCoreID )
 {
-    configASSERT(xCoreID != portGET_CORE_ID());
+    /* Remove warning if configASSERT is not defined.
+     * xCoreID is not used in this function due to this is a dual-core system. The yielding core must be different from the current core. */
+    ( void ) xCoreID;
+
+    configASSERT( xCoreID != ( int ) portGET_CORE_ID() );
+
     #if portRUNNING_ON_BOTH_CORES
         /* Non blocking, will cause interrupt on other core if the queue isn't already full,
         in which case an IRQ must be pending */
@@ -1004,7 +1009,7 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
             // by the spinlock, we can defer until portENABLE_INTERRUPTS is called which is always called when
             // the scheduler is unlocked during this call
             configASSERT(pxLock->spin_lock);
-            int xCoreID = portGET_CORE_ID();
+            int xCoreID = ( int ) portGET_CORE_ID();
             pxYieldSpinLock[xCoreID] = pxLock->spin_lock;
             ulYieldSpinLockSaveValue[xCoreID] = ulSave;
             xEventGroupWaitBits( xEventGroup, prvGetEventGroupBit(pxLock->spin_lock),
@@ -1076,7 +1081,7 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
                  * by the spinlock, we can defer until portENABLE_INTERRUPTS is called which is always called when
                  * the scheduler is unlocked during this call */
                 configASSERT(pxLock->spin_lock);
-                int xCoreID = portGET_CORE_ID();
+                int xCoreID = ( int ) portGET_CORE_ID();
                 pxYieldSpinLock[xCoreID] = pxLock->spin_lock;
                 ulYieldSpinLockSaveValue[xCoreID] = ulSave;
                 xEventGroupWaitBits( xEventGroup,
diff --git a/tasks.c b/tasks.c
index c4e8bd424..b63073056 100644
--- a/tasks.c
+++ b/tasks.c
@@ -5541,7 +5541,7 @@ static void prvCheckTasksWaitingTermination( void )
         /* xTask is NULL then get the state of the calling task. */
         pxTCB = prvGetTCBFromHandle( xTask );
 
-        pxTaskStatus->xHandle = ( TaskHandle_t ) pxTCB;
+        pxTaskStatus->xHandle = pxTCB;
         pxTaskStatus->pcTaskName = ( const char * ) &( pxTCB->pcTaskName[ 0 ] );
         pxTaskStatus->uxCurrentPriority = pxTCB->uxPriority;
         pxTaskStatus->pxStackBase = pxTCB->pxStack;

From a5bf4d9a7f5fbbb6110ee329c8517641efb9f563 Mon Sep 17 00:00:00 2001
From: Moral-Hao <sihunzhilei@126.com>
Date: Thu, 3 Aug 2023 20:16:12 +0800
Subject: [PATCH 028/424] Improve the speed of split memory. (#738)

Co-authored-by: moral-hao <405197809@qq.com>
Co-authored-by: Nikhil Kamath <110539926+amazonKamath@users.noreply.github.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
---
 portable/ARMv8M/secure/heap/secure_heap.c   | 3 ++-
 portable/GCC/ARM_CM23/secure/secure_heap.c  | 3 ++-
 portable/GCC/ARM_CM33/secure/secure_heap.c  | 3 ++-
 portable/GCC/ARM_CM35P/secure/secure_heap.c | 3 ++-
 portable/GCC/ARM_CM55/secure/secure_heap.c  | 3 ++-
 portable/GCC/ARM_CM85/secure/secure_heap.c  | 3 ++-
 portable/IAR/ARM_CM23/secure/secure_heap.c  | 3 ++-
 portable/IAR/ARM_CM33/secure/secure_heap.c  | 3 ++-
 portable/IAR/ARM_CM35P/secure/secure_heap.c | 3 ++-
 portable/IAR/ARM_CM55/secure/secure_heap.c  | 3 ++-
 portable/IAR/ARM_CM85/secure/secure_heap.c  | 3 ++-
 portable/MemMang/heap_2.c                   | 3 ++-
 portable/MemMang/heap_4.c                   | 3 ++-
 portable/MemMang/heap_5.c                   | 3 ++-
 14 files changed, 28 insertions(+), 14 deletions(-)

diff --git a/portable/ARMv8M/secure/heap/secure_heap.c b/portable/ARMv8M/secure/heap/secure_heap.c
index 157fdbf0e..990125a2a 100644
--- a/portable/ARMv8M/secure/heap/secure_heap.c
+++ b/portable/ARMv8M/secure/heap/secure_heap.c
@@ -334,7 +334,8 @@ void * pvPortMalloc( size_t xWantedSize )
                     pxBlock->xBlockSize = xWantedSize;
 
                     /* Insert the new block into the list of free blocks. */
-                    prvInsertBlockIntoFreeList( pxNewBlockLink );
+                    pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock;
+                    pxPreviousBlock->pxNextFreeBlock = pxNewBlockLink;
                 }
                 else
                 {
diff --git a/portable/GCC/ARM_CM23/secure/secure_heap.c b/portable/GCC/ARM_CM23/secure/secure_heap.c
index 157fdbf0e..990125a2a 100644
--- a/portable/GCC/ARM_CM23/secure/secure_heap.c
+++ b/portable/GCC/ARM_CM23/secure/secure_heap.c
@@ -334,7 +334,8 @@ void * pvPortMalloc( size_t xWantedSize )
                     pxBlock->xBlockSize = xWantedSize;
 
                     /* Insert the new block into the list of free blocks. */
-                    prvInsertBlockIntoFreeList( pxNewBlockLink );
+                    pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock;
+                    pxPreviousBlock->pxNextFreeBlock = pxNewBlockLink;
                 }
                 else
                 {
diff --git a/portable/GCC/ARM_CM33/secure/secure_heap.c b/portable/GCC/ARM_CM33/secure/secure_heap.c
index 157fdbf0e..990125a2a 100644
--- a/portable/GCC/ARM_CM33/secure/secure_heap.c
+++ b/portable/GCC/ARM_CM33/secure/secure_heap.c
@@ -334,7 +334,8 @@ void * pvPortMalloc( size_t xWantedSize )
                     pxBlock->xBlockSize = xWantedSize;
 
                     /* Insert the new block into the list of free blocks. */
-                    prvInsertBlockIntoFreeList( pxNewBlockLink );
+                    pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock;
+                    pxPreviousBlock->pxNextFreeBlock = pxNewBlockLink;
                 }
                 else
                 {
diff --git a/portable/GCC/ARM_CM35P/secure/secure_heap.c b/portable/GCC/ARM_CM35P/secure/secure_heap.c
index 157fdbf0e..990125a2a 100644
--- a/portable/GCC/ARM_CM35P/secure/secure_heap.c
+++ b/portable/GCC/ARM_CM35P/secure/secure_heap.c
@@ -334,7 +334,8 @@ void * pvPortMalloc( size_t xWantedSize )
                     pxBlock->xBlockSize = xWantedSize;
 
                     /* Insert the new block into the list of free blocks. */
-                    prvInsertBlockIntoFreeList( pxNewBlockLink );
+                    pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock;
+                    pxPreviousBlock->pxNextFreeBlock = pxNewBlockLink;
                 }
                 else
                 {
diff --git a/portable/GCC/ARM_CM55/secure/secure_heap.c b/portable/GCC/ARM_CM55/secure/secure_heap.c
index 157fdbf0e..990125a2a 100644
--- a/portable/GCC/ARM_CM55/secure/secure_heap.c
+++ b/portable/GCC/ARM_CM55/secure/secure_heap.c
@@ -334,7 +334,8 @@ void * pvPortMalloc( size_t xWantedSize )
                     pxBlock->xBlockSize = xWantedSize;
 
                     /* Insert the new block into the list of free blocks. */
-                    prvInsertBlockIntoFreeList( pxNewBlockLink );
+                    pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock;
+                    pxPreviousBlock->pxNextFreeBlock = pxNewBlockLink;
                 }
                 else
                 {
diff --git a/portable/GCC/ARM_CM85/secure/secure_heap.c b/portable/GCC/ARM_CM85/secure/secure_heap.c
index 157fdbf0e..990125a2a 100644
--- a/portable/GCC/ARM_CM85/secure/secure_heap.c
+++ b/portable/GCC/ARM_CM85/secure/secure_heap.c
@@ -334,7 +334,8 @@ void * pvPortMalloc( size_t xWantedSize )
                     pxBlock->xBlockSize = xWantedSize;
 
                     /* Insert the new block into the list of free blocks. */
-                    prvInsertBlockIntoFreeList( pxNewBlockLink );
+                    pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock;
+                    pxPreviousBlock->pxNextFreeBlock = pxNewBlockLink;
                 }
                 else
                 {
diff --git a/portable/IAR/ARM_CM23/secure/secure_heap.c b/portable/IAR/ARM_CM23/secure/secure_heap.c
index 157fdbf0e..990125a2a 100644
--- a/portable/IAR/ARM_CM23/secure/secure_heap.c
+++ b/portable/IAR/ARM_CM23/secure/secure_heap.c
@@ -334,7 +334,8 @@ void * pvPortMalloc( size_t xWantedSize )
                     pxBlock->xBlockSize = xWantedSize;
 
                     /* Insert the new block into the list of free blocks. */
-                    prvInsertBlockIntoFreeList( pxNewBlockLink );
+                    pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock;
+                    pxPreviousBlock->pxNextFreeBlock = pxNewBlockLink;
                 }
                 else
                 {
diff --git a/portable/IAR/ARM_CM33/secure/secure_heap.c b/portable/IAR/ARM_CM33/secure/secure_heap.c
index 157fdbf0e..990125a2a 100644
--- a/portable/IAR/ARM_CM33/secure/secure_heap.c
+++ b/portable/IAR/ARM_CM33/secure/secure_heap.c
@@ -334,7 +334,8 @@ void * pvPortMalloc( size_t xWantedSize )
                     pxBlock->xBlockSize = xWantedSize;
 
                     /* Insert the new block into the list of free blocks. */
-                    prvInsertBlockIntoFreeList( pxNewBlockLink );
+                    pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock;
+                    pxPreviousBlock->pxNextFreeBlock = pxNewBlockLink;
                 }
                 else
                 {
diff --git a/portable/IAR/ARM_CM35P/secure/secure_heap.c b/portable/IAR/ARM_CM35P/secure/secure_heap.c
index 157fdbf0e..990125a2a 100644
--- a/portable/IAR/ARM_CM35P/secure/secure_heap.c
+++ b/portable/IAR/ARM_CM35P/secure/secure_heap.c
@@ -334,7 +334,8 @@ void * pvPortMalloc( size_t xWantedSize )
                     pxBlock->xBlockSize = xWantedSize;
 
                     /* Insert the new block into the list of free blocks. */
-                    prvInsertBlockIntoFreeList( pxNewBlockLink );
+                    pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock;
+                    pxPreviousBlock->pxNextFreeBlock = pxNewBlockLink;
                 }
                 else
                 {
diff --git a/portable/IAR/ARM_CM55/secure/secure_heap.c b/portable/IAR/ARM_CM55/secure/secure_heap.c
index 157fdbf0e..990125a2a 100644
--- a/portable/IAR/ARM_CM55/secure/secure_heap.c
+++ b/portable/IAR/ARM_CM55/secure/secure_heap.c
@@ -334,7 +334,8 @@ void * pvPortMalloc( size_t xWantedSize )
                     pxBlock->xBlockSize = xWantedSize;
 
                     /* Insert the new block into the list of free blocks. */
-                    prvInsertBlockIntoFreeList( pxNewBlockLink );
+                    pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock;
+                    pxPreviousBlock->pxNextFreeBlock = pxNewBlockLink;
                 }
                 else
                 {
diff --git a/portable/IAR/ARM_CM85/secure/secure_heap.c b/portable/IAR/ARM_CM85/secure/secure_heap.c
index 157fdbf0e..990125a2a 100644
--- a/portable/IAR/ARM_CM85/secure/secure_heap.c
+++ b/portable/IAR/ARM_CM85/secure/secure_heap.c
@@ -334,7 +334,8 @@ void * pvPortMalloc( size_t xWantedSize )
                     pxBlock->xBlockSize = xWantedSize;
 
                     /* Insert the new block into the list of free blocks. */
-                    prvInsertBlockIntoFreeList( pxNewBlockLink );
+                    pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock;
+                    pxPreviousBlock->pxNextFreeBlock = pxNewBlockLink;
                 }
                 else
                 {
diff --git a/portable/MemMang/heap_2.c b/portable/MemMang/heap_2.c
index 67f1c3aed..5c3cb55b1 100644
--- a/portable/MemMang/heap_2.c
+++ b/portable/MemMang/heap_2.c
@@ -230,7 +230,8 @@ void * pvPortMalloc( size_t xWantedSize )
                         pxBlock->xBlockSize = xWantedSize;
 
                         /* Insert the new block into the list of free blocks. */
-                        prvInsertBlockIntoFreeList( ( pxNewBlockLink ) );
+                        pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock;
+                        pxPreviousBlock->pxNextFreeBlock = pxNewBlockLink;
                     }
 
                     xFreeBytesRemaining -= pxBlock->xBlockSize;
diff --git a/portable/MemMang/heap_4.c b/portable/MemMang/heap_4.c
index c82933e66..63eb94d49 100644
--- a/portable/MemMang/heap_4.c
+++ b/portable/MemMang/heap_4.c
@@ -243,7 +243,8 @@ void * pvPortMalloc( size_t xWantedSize )
                         pxBlock->xBlockSize = xWantedSize;
 
                         /* Insert the new block into the list of free blocks. */
-                        prvInsertBlockIntoFreeList( pxNewBlockLink );
+                        pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock;
+                        pxPreviousBlock->pxNextFreeBlock = pxNewBlockLink;
                     }
                     else
                     {
diff --git a/portable/MemMang/heap_5.c b/portable/MemMang/heap_5.c
index 24a7adac9..198bc611a 100644
--- a/portable/MemMang/heap_5.c
+++ b/portable/MemMang/heap_5.c
@@ -253,7 +253,8 @@ void * pvPortMalloc( size_t xWantedSize )
                         pxBlock->xBlockSize = xWantedSize;
 
                         /* Insert the new block into the list of free blocks. */
-                        prvInsertBlockIntoFreeList( ( pxNewBlockLink ) );
+                        pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock;
+                        pxPreviousBlock->pxNextFreeBlock = pxNewBlockLink;
                     }
                     else
                     {

From 02be485e0452313d347678f32edaf79525de7b9a Mon Sep 17 00:00:00 2001
From: kar-rahul-aws <118818625+kar-rahul-aws@users.noreply.github.com>
Date: Fri, 4 Aug 2023 12:22:28 +0530
Subject: [PATCH 029/424] Update MPU wrapper for pcTaskGetName API (#737)

* Update MPU wrapper for pcTaskGetName

* Fix Formatting

* Fix mpu wrappers V1

---------

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
---
 include/mpu_prototypes.h                      |  2 +-
 include/mpu_wrappers.h                        |  2 +-
 .../GCC/ARM_CM23/mpu_wrappers_v2_asm.c        | 29 ---------
 .../GCC/ARM_CM23_NTZ/mpu_wrappers_v2_asm.c    | 29 ---------
 .../GCC/ARM_CM33/mpu_wrappers_v2_asm.c        | 28 ---------
 .../GCC/ARM_CM33_NTZ/mpu_wrappers_v2_asm.c    | 28 ---------
 .../IAR/ARM_CM23/mpu_wrappers_v2_asm.S        | 22 -------
 .../IAR/ARM_CM23_NTZ/mpu_wrappers_v2_asm.S    | 22 -------
 .../IAR/ARM_CM33/mpu_wrappers_v2_asm.S        | 21 -------
 .../IAR/ARM_CM33_NTZ/mpu_wrappers_v2_asm.S    | 21 -------
 portable/Common/mpu_wrappers.c                | 24 --------
 portable/Common/mpu_wrappers_v2.c             | 60 +++++++++----------
 .../ARM_CM23/non_secure/mpu_wrappers_v2_asm.c | 29 ---------
 .../non_secure/mpu_wrappers_v2_asm.c          | 29 ---------
 .../ARM_CM33/non_secure/mpu_wrappers_v2_asm.c | 28 ---------
 .../non_secure/mpu_wrappers_v2_asm.c          | 28 ---------
 .../non_secure/mpu_wrappers_v2_asm.c          | 28 ---------
 .../non_secure/mpu_wrappers_v2_asm.c          | 28 ---------
 .../GCC/ARM_CM3_MPU/mpu_wrappers_v2_asm.c     | 28 ---------
 .../GCC/ARM_CM4_MPU/mpu_wrappers_v2_asm.c     | 28 ---------
 .../ARM_CM55/non_secure/mpu_wrappers_v2_asm.c | 28 ---------
 .../non_secure/mpu_wrappers_v2_asm.c          | 28 ---------
 .../ARM_CM85/non_secure/mpu_wrappers_v2_asm.c | 28 ---------
 .../non_secure/mpu_wrappers_v2_asm.c          | 28 ---------
 .../ARM_CM23/non_secure/mpu_wrappers_v2_asm.S | 22 -------
 .../non_secure/mpu_wrappers_v2_asm.S          | 22 -------
 .../ARM_CM33/non_secure/mpu_wrappers_v2_asm.S | 21 -------
 .../non_secure/mpu_wrappers_v2_asm.S          | 21 -------
 .../non_secure/mpu_wrappers_v2_asm.S          | 21 -------
 .../non_secure/mpu_wrappers_v2_asm.S          | 21 -------
 .../IAR/ARM_CM4F_MPU/mpu_wrappers_v2_asm.S    | 21 -------
 .../ARM_CM55/non_secure/mpu_wrappers_v2_asm.S | 21 -------
 .../non_secure/mpu_wrappers_v2_asm.S          | 21 -------
 .../ARM_CM85/non_secure/mpu_wrappers_v2_asm.S | 21 -------
 .../non_secure/mpu_wrappers_v2_asm.S          | 21 -------
 .../RVDS/ARM_CM4_MPU/mpu_wrappers_v2_asm.c    | 23 -------
 36 files changed, 31 insertions(+), 851 deletions(-)

diff --git a/include/mpu_prototypes.h b/include/mpu_prototypes.h
index 2b6b6cb82..239e640bd 100644
--- a/include/mpu_prototypes.h
+++ b/include/mpu_prototypes.h
@@ -53,7 +53,6 @@ void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) FREERTOS_SYSTEM_CALL;
 void MPU_vTaskResume( TaskHandle_t xTaskToResume ) FREERTOS_SYSTEM_CALL;
 TickType_t MPU_xTaskGetTickCount( void ) FREERTOS_SYSTEM_CALL;
 UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) FREERTOS_SYSTEM_CALL;
-char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) FREERTOS_SYSTEM_CALL;
 UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
 configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
 void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
@@ -118,6 +117,7 @@ void MPU_vTaskPrioritySet( TaskHandle_t xTask,
 TaskHandle_t MPU_xTaskGetHandle( const char * pcNameToQuery ) PRIVILEGED_FUNCTION;
 BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask,
                                              void * pvParameter ) PRIVILEGED_FUNCTION;
+char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION;
 BaseType_t MPU_xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition,
                                       TaskHandle_t * pxCreatedTask ) PRIVILEGED_FUNCTION;
 BaseType_t MPU_xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition,
diff --git a/include/mpu_wrappers.h b/include/mpu_wrappers.h
index a0ebf6030..9d1d867e2 100644
--- a/include/mpu_wrappers.h
+++ b/include/mpu_wrappers.h
@@ -57,7 +57,6 @@
         #define vTaskResume                           MPU_vTaskResume
         #define xTaskGetTickCount                     MPU_xTaskGetTickCount
         #define uxTaskGetNumberOfTasks                MPU_uxTaskGetNumberOfTasks
-        #define pcTaskGetName                         MPU_pcTaskGetName
         #define uxTaskGetStackHighWaterMark           MPU_uxTaskGetStackHighWaterMark
         #define uxTaskGetStackHighWaterMark2          MPU_uxTaskGetStackHighWaterMark2
         #define vTaskSetApplicationTaskTag            MPU_vTaskSetApplicationTaskTag
@@ -94,6 +93,7 @@
         #define xTaskCallApplicationTaskHook             MPU_xTaskCallApplicationTaskHook
 
         #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+            #define pcTaskGetName                        MPU_pcTaskGetName
             #define xTaskCreateRestricted                MPU_xTaskCreateRestricted
             #define xTaskCreateRestrictedStatic          MPU_xTaskCreateRestrictedStatic
             #define vTaskAllocateMPURegions              MPU_vTaskAllocateMPURegions
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/mpu_wrappers_v2_asm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/mpu_wrappers_v2_asm.c
index 795f2195c..f6fb0e778 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/mpu_wrappers_v2_asm.c
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/mpu_wrappers_v2_asm.c
@@ -407,35 +407,6 @@ UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREE
 }
 /*-----------------------------------------------------------*/
 
-char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pcTaskGetNameImpl                         \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_pcTaskGetName_Unpriv                          \n"
-        " MPU_pcTaskGetName_Priv:                               \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_pcTaskGetNameImpl                           \n"
-        " MPU_pcTaskGetName_Unpriv:                             \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pcTaskGetNameImpl                          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
 #if ( configGENERATE_RUN_TIME_STATS == 1 )
 
 configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/mpu_wrappers_v2_asm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/mpu_wrappers_v2_asm.c
index 795f2195c..f6fb0e778 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/mpu_wrappers_v2_asm.c
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/mpu_wrappers_v2_asm.c
@@ -407,35 +407,6 @@ UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREE
 }
 /*-----------------------------------------------------------*/
 
-char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pcTaskGetNameImpl                         \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_pcTaskGetName_Unpriv                          \n"
-        " MPU_pcTaskGetName_Priv:                               \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_pcTaskGetNameImpl                           \n"
-        " MPU_pcTaskGetName_Unpriv:                             \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pcTaskGetNameImpl                          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
 #if ( configGENERATE_RUN_TIME_STATS == 1 )
 
 configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/mpu_wrappers_v2_asm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/mpu_wrappers_v2_asm.c
index 9e1b9ed85..2d1218a95 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/mpu_wrappers_v2_asm.c
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/mpu_wrappers_v2_asm.c
@@ -396,34 +396,6 @@ UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREE
 }
 /*-----------------------------------------------------------*/
 
-char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pcTaskGetNameImpl                         \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_pcTaskGetName_Unpriv                          \n"
-        " MPU_pcTaskGetName_Priv:                               \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_pcTaskGetNameImpl                           \n"
-        " MPU_pcTaskGetName_Unpriv:                             \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pcTaskGetNameImpl                          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
 #if ( configGENERATE_RUN_TIME_STATS == 1 )
 
 configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/mpu_wrappers_v2_asm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/mpu_wrappers_v2_asm.c
index 9e1b9ed85..2d1218a95 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/mpu_wrappers_v2_asm.c
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/mpu_wrappers_v2_asm.c
@@ -396,34 +396,6 @@ UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREE
 }
 /*-----------------------------------------------------------*/
 
-char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pcTaskGetNameImpl                         \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_pcTaskGetName_Unpriv                          \n"
-        " MPU_pcTaskGetName_Priv:                               \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_pcTaskGetNameImpl                           \n"
-        " MPU_pcTaskGetName_Unpriv:                             \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pcTaskGetNameImpl                          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
 #if ( configGENERATE_RUN_TIME_STATS == 1 )
 
 configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/mpu_wrappers_v2_asm.S b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/mpu_wrappers_v2_asm.S
index f2098b57d..5300a99ec 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/mpu_wrappers_v2_asm.S
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/mpu_wrappers_v2_asm.S
@@ -243,24 +243,6 @@ MPU_uxTaskGetNumberOfTasks:
         bx lr
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_pcTaskGetName
-MPU_pcTaskGetName:
-    push {r0, r1}
-    mrs r0, control
-    movs r1, #1
-    tst r0, r1
-    bne MPU_pcTaskGetName_Unpriv
-    MPU_pcTaskGetName_Priv:
-        pop {r0, r1}
-        b MPU_pcTaskGetNameImpl
-    MPU_pcTaskGetName_Unpriv:
-        pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pcTaskGetNameImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-/*-----------------------------------------------------------*/
-
     PUBLIC MPU_ulTaskGetRunTimeCounter
 MPU_ulTaskGetRunTimeCounter:
     push {r0, r1}
@@ -1370,10 +1352,6 @@ MPU_xTaskGetTickCountImpl:
 MPU_uxTaskGetNumberOfTasksImpl:
     b MPU_uxTaskGetNumberOfTasksImpl
 
-    PUBWEAK MPU_pcTaskGetNameImpl
-MPU_pcTaskGetNameImpl:
-    b MPU_pcTaskGetNameImpl
-
     PUBWEAK MPU_ulTaskGetRunTimeCounterImpl
 MPU_ulTaskGetRunTimeCounterImpl:
     b MPU_ulTaskGetRunTimeCounterImpl
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/mpu_wrappers_v2_asm.S b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/mpu_wrappers_v2_asm.S
index f2098b57d..5300a99ec 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/mpu_wrappers_v2_asm.S
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/mpu_wrappers_v2_asm.S
@@ -243,24 +243,6 @@ MPU_uxTaskGetNumberOfTasks:
         bx lr
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_pcTaskGetName
-MPU_pcTaskGetName:
-    push {r0, r1}
-    mrs r0, control
-    movs r1, #1
-    tst r0, r1
-    bne MPU_pcTaskGetName_Unpriv
-    MPU_pcTaskGetName_Priv:
-        pop {r0, r1}
-        b MPU_pcTaskGetNameImpl
-    MPU_pcTaskGetName_Unpriv:
-        pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pcTaskGetNameImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-/*-----------------------------------------------------------*/
-
     PUBLIC MPU_ulTaskGetRunTimeCounter
 MPU_ulTaskGetRunTimeCounter:
     push {r0, r1}
@@ -1370,10 +1352,6 @@ MPU_xTaskGetTickCountImpl:
 MPU_uxTaskGetNumberOfTasksImpl:
     b MPU_uxTaskGetNumberOfTasksImpl
 
-    PUBWEAK MPU_pcTaskGetNameImpl
-MPU_pcTaskGetNameImpl:
-    b MPU_pcTaskGetNameImpl
-
     PUBWEAK MPU_ulTaskGetRunTimeCounterImpl
 MPU_ulTaskGetRunTimeCounterImpl:
     b MPU_ulTaskGetRunTimeCounterImpl
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/mpu_wrappers_v2_asm.S b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/mpu_wrappers_v2_asm.S
index 9cb9a9d72..1005dad33 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/mpu_wrappers_v2_asm.S
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/mpu_wrappers_v2_asm.S
@@ -232,23 +232,6 @@ MPU_uxTaskGetNumberOfTasks:
         bx lr
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_pcTaskGetName
-MPU_pcTaskGetName:
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_pcTaskGetName_Unpriv
-    MPU_pcTaskGetName_Priv:
-        pop {r0}
-        b MPU_pcTaskGetNameImpl
-    MPU_pcTaskGetName_Unpriv:
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pcTaskGetNameImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-/*-----------------------------------------------------------*/
-
     PUBLIC MPU_ulTaskGetRunTimeCounter
 MPU_ulTaskGetRunTimeCounter:
     push {r0}
@@ -1299,10 +1282,6 @@ MPU_xTaskGetTickCountImpl:
 MPU_uxTaskGetNumberOfTasksImpl:
     b MPU_uxTaskGetNumberOfTasksImpl
 
-    PUBWEAK MPU_pcTaskGetNameImpl
-MPU_pcTaskGetNameImpl:
-    b MPU_pcTaskGetNameImpl
-
     PUBWEAK MPU_ulTaskGetRunTimeCounterImpl
 MPU_ulTaskGetRunTimeCounterImpl:
     b MPU_ulTaskGetRunTimeCounterImpl
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/mpu_wrappers_v2_asm.S b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/mpu_wrappers_v2_asm.S
index 9cb9a9d72..1005dad33 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/mpu_wrappers_v2_asm.S
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/mpu_wrappers_v2_asm.S
@@ -232,23 +232,6 @@ MPU_uxTaskGetNumberOfTasks:
         bx lr
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_pcTaskGetName
-MPU_pcTaskGetName:
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_pcTaskGetName_Unpriv
-    MPU_pcTaskGetName_Priv:
-        pop {r0}
-        b MPU_pcTaskGetNameImpl
-    MPU_pcTaskGetName_Unpriv:
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pcTaskGetNameImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-/*-----------------------------------------------------------*/
-
     PUBLIC MPU_ulTaskGetRunTimeCounter
 MPU_ulTaskGetRunTimeCounter:
     push {r0}
@@ -1299,10 +1282,6 @@ MPU_xTaskGetTickCountImpl:
 MPU_uxTaskGetNumberOfTasksImpl:
     b MPU_uxTaskGetNumberOfTasksImpl
 
-    PUBWEAK MPU_pcTaskGetNameImpl
-MPU_pcTaskGetNameImpl:
-    b MPU_pcTaskGetNameImpl
-
     PUBWEAK MPU_ulTaskGetRunTimeCounterImpl
 MPU_ulTaskGetRunTimeCounterImpl:
     b MPU_ulTaskGetRunTimeCounterImpl
diff --git a/portable/Common/mpu_wrappers.c b/portable/Common/mpu_wrappers.c
index e877dcea9..a0d7ee0aa 100644
--- a/portable/Common/mpu_wrappers.c
+++ b/portable/Common/mpu_wrappers.c
@@ -477,30 +477,6 @@
     }
 /*-----------------------------------------------------------*/
 
-    char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* FREERTOS_SYSTEM_CALL */
-    {
-        char * pcReturn;
-
-        if( portIS_PRIVILEGED() == pdFALSE )
-        {
-            portRAISE_PRIVILEGE();
-            portMEMORY_BARRIER();
-
-            pcReturn = pcTaskGetName( xTaskToQuery );
-            portMEMORY_BARRIER();
-
-            portRESET_PRIVILEGE();
-            portMEMORY_BARRIER();
-        }
-        else
-        {
-            pcReturn = pcTaskGetName( xTaskToQuery );
-        }
-
-        return pcReturn;
-    }
-/*-----------------------------------------------------------*/
-
     #if ( INCLUDE_xTaskGetHandle == 1 )
         TaskHandle_t MPU_xTaskGetHandle( const char * pcNameToQuery ) /* FREERTOS_SYSTEM_CALL */
         {
diff --git a/portable/Common/mpu_wrappers_v2.c b/portable/Common/mpu_wrappers_v2.c
index 91a2e7055..3cebd56c7 100644
--- a/portable/Common/mpu_wrappers_v2.c
+++ b/portable/Common/mpu_wrappers_v2.c
@@ -646,37 +646,6 @@
     }
 /*-----------------------------------------------------------*/
 
-    char * MPU_pcTaskGetNameImpl( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION;
-
-    char * MPU_pcTaskGetNameImpl( TaskHandle_t xTaskToQuery ) /* PRIVILEGED_FUNCTION */
-    {
-        char * pcReturn = NULL;
-        int32_t lIndex;
-        TaskHandle_t xInternalTaskHandle = NULL;
-
-        if( xTaskToQuery == NULL )
-        {
-            pcReturn = pcTaskGetName( xTaskToQuery );
-        }
-        else
-        {
-            lIndex = ( int32_t ) xTaskToQuery;
-
-            if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
-            {
-                xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
-
-                if( xInternalTaskHandle != NULL )
-                {
-                    pcReturn = pcTaskGetName( xInternalTaskHandle );
-                }
-            }
-        }
-
-        return pcReturn;
-    }
-/*-----------------------------------------------------------*/
-
     #if ( configGENERATE_RUN_TIME_STATS == 1 )
 
         configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounterImpl( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
@@ -1646,6 +1615,35 @@
     #endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
 /*-----------------------------------------------------------*/
 
+    char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* PRIVILEGED_FUNCTION */
+    {
+        char * pcReturn = NULL;
+        int32_t lIndex;
+        TaskHandle_t xInternalTaskHandle = NULL;
+
+        if( xTaskToQuery == NULL )
+        {
+            pcReturn = pcTaskGetName( xTaskToQuery );
+        }
+        else
+        {
+            lIndex = ( int32_t ) xTaskToQuery;
+
+            if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+            {
+                xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                if( xInternalTaskHandle != NULL )
+                {
+                    pcReturn = pcTaskGetName( xInternalTaskHandle );
+                }
+            }
+        }
+
+        return pcReturn;
+    }
+/*-----------------------------------------------------------*/
+
     #if ( INCLUDE_uxTaskPriorityGet == 1 )
 
         UBaseType_t MPU_uxTaskPriorityGetFromISR( const TaskHandle_t xTask ) /* PRIVILEGED_FUNCTION */
diff --git a/portable/GCC/ARM_CM23/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM23/non_secure/mpu_wrappers_v2_asm.c
index 795f2195c..f6fb0e778 100644
--- a/portable/GCC/ARM_CM23/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM23/non_secure/mpu_wrappers_v2_asm.c
@@ -407,35 +407,6 @@ UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREE
 }
 /*-----------------------------------------------------------*/
 
-char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pcTaskGetNameImpl                         \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_pcTaskGetName_Unpriv                          \n"
-        " MPU_pcTaskGetName_Priv:                               \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_pcTaskGetNameImpl                           \n"
-        " MPU_pcTaskGetName_Unpriv:                             \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pcTaskGetNameImpl                          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
 #if ( configGENERATE_RUN_TIME_STATS == 1 )
 
 configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.c
index 795f2195c..f6fb0e778 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.c
@@ -407,35 +407,6 @@ UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREE
 }
 /*-----------------------------------------------------------*/
 
-char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pcTaskGetNameImpl                         \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_pcTaskGetName_Unpriv                          \n"
-        " MPU_pcTaskGetName_Priv:                               \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_pcTaskGetNameImpl                           \n"
-        " MPU_pcTaskGetName_Unpriv:                             \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pcTaskGetNameImpl                          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
 #if ( configGENERATE_RUN_TIME_STATS == 1 )
 
 configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
diff --git a/portable/GCC/ARM_CM33/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM33/non_secure/mpu_wrappers_v2_asm.c
index 9e1b9ed85..2d1218a95 100644
--- a/portable/GCC/ARM_CM33/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM33/non_secure/mpu_wrappers_v2_asm.c
@@ -396,34 +396,6 @@ UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREE
 }
 /*-----------------------------------------------------------*/
 
-char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pcTaskGetNameImpl                         \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_pcTaskGetName_Unpriv                          \n"
-        " MPU_pcTaskGetName_Priv:                               \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_pcTaskGetNameImpl                           \n"
-        " MPU_pcTaskGetName_Unpriv:                             \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pcTaskGetNameImpl                          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
 #if ( configGENERATE_RUN_TIME_STATS == 1 )
 
 configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.c
index 9e1b9ed85..2d1218a95 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.c
@@ -396,34 +396,6 @@ UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREE
 }
 /*-----------------------------------------------------------*/
 
-char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pcTaskGetNameImpl                         \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_pcTaskGetName_Unpriv                          \n"
-        " MPU_pcTaskGetName_Priv:                               \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_pcTaskGetNameImpl                           \n"
-        " MPU_pcTaskGetName_Unpriv:                             \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pcTaskGetNameImpl                          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
 #if ( configGENERATE_RUN_TIME_STATS == 1 )
 
 configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
diff --git a/portable/GCC/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.c
index 9e1b9ed85..2d1218a95 100644
--- a/portable/GCC/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.c
@@ -396,34 +396,6 @@ UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREE
 }
 /*-----------------------------------------------------------*/
 
-char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pcTaskGetNameImpl                         \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_pcTaskGetName_Unpriv                          \n"
-        " MPU_pcTaskGetName_Priv:                               \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_pcTaskGetNameImpl                           \n"
-        " MPU_pcTaskGetName_Unpriv:                             \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pcTaskGetNameImpl                          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
 #if ( configGENERATE_RUN_TIME_STATS == 1 )
 
 configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.c
index 9e1b9ed85..2d1218a95 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.c
@@ -396,34 +396,6 @@ UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREE
 }
 /*-----------------------------------------------------------*/
 
-char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pcTaskGetNameImpl                         \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_pcTaskGetName_Unpriv                          \n"
-        " MPU_pcTaskGetName_Priv:                               \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_pcTaskGetNameImpl                           \n"
-        " MPU_pcTaskGetName_Unpriv:                             \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pcTaskGetNameImpl                          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
 #if ( configGENERATE_RUN_TIME_STATS == 1 )
 
 configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
diff --git a/portable/GCC/ARM_CM3_MPU/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM3_MPU/mpu_wrappers_v2_asm.c
index d9aa1a3fd..76c6029af 100644
--- a/portable/GCC/ARM_CM3_MPU/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM3_MPU/mpu_wrappers_v2_asm.c
@@ -396,34 +396,6 @@ UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREE
 }
 /*-----------------------------------------------------------*/
 
-char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pcTaskGetNameImpl                         \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_pcTaskGetName_Unpriv                          \n"
-        " MPU_pcTaskGetName_Priv:                               \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_pcTaskGetNameImpl                           \n"
-        " MPU_pcTaskGetName_Unpriv:                             \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pcTaskGetNameImpl                          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
 #if ( configGENERATE_RUN_TIME_STATS == 1 )
 
 configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
diff --git a/portable/GCC/ARM_CM4_MPU/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM4_MPU/mpu_wrappers_v2_asm.c
index d9aa1a3fd..76c6029af 100644
--- a/portable/GCC/ARM_CM4_MPU/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM4_MPU/mpu_wrappers_v2_asm.c
@@ -396,34 +396,6 @@ UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREE
 }
 /*-----------------------------------------------------------*/
 
-char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pcTaskGetNameImpl                         \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_pcTaskGetName_Unpriv                          \n"
-        " MPU_pcTaskGetName_Priv:                               \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_pcTaskGetNameImpl                           \n"
-        " MPU_pcTaskGetName_Unpriv:                             \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pcTaskGetNameImpl                          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
 #if ( configGENERATE_RUN_TIME_STATS == 1 )
 
 configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
diff --git a/portable/GCC/ARM_CM55/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM55/non_secure/mpu_wrappers_v2_asm.c
index 9e1b9ed85..2d1218a95 100644
--- a/portable/GCC/ARM_CM55/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM55/non_secure/mpu_wrappers_v2_asm.c
@@ -396,34 +396,6 @@ UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREE
 }
 /*-----------------------------------------------------------*/
 
-char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pcTaskGetNameImpl                         \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_pcTaskGetName_Unpriv                          \n"
-        " MPU_pcTaskGetName_Priv:                               \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_pcTaskGetNameImpl                           \n"
-        " MPU_pcTaskGetName_Unpriv:                             \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pcTaskGetNameImpl                          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
 #if ( configGENERATE_RUN_TIME_STATS == 1 )
 
 configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.c
index 9e1b9ed85..2d1218a95 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.c
@@ -396,34 +396,6 @@ UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREE
 }
 /*-----------------------------------------------------------*/
 
-char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pcTaskGetNameImpl                         \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_pcTaskGetName_Unpriv                          \n"
-        " MPU_pcTaskGetName_Priv:                               \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_pcTaskGetNameImpl                           \n"
-        " MPU_pcTaskGetName_Unpriv:                             \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pcTaskGetNameImpl                          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
 #if ( configGENERATE_RUN_TIME_STATS == 1 )
 
 configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
diff --git a/portable/GCC/ARM_CM85/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM85/non_secure/mpu_wrappers_v2_asm.c
index 9e1b9ed85..2d1218a95 100644
--- a/portable/GCC/ARM_CM85/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM85/non_secure/mpu_wrappers_v2_asm.c
@@ -396,34 +396,6 @@ UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREE
 }
 /*-----------------------------------------------------------*/
 
-char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pcTaskGetNameImpl                         \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_pcTaskGetName_Unpriv                          \n"
-        " MPU_pcTaskGetName_Priv:                               \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_pcTaskGetNameImpl                           \n"
-        " MPU_pcTaskGetName_Unpriv:                             \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pcTaskGetNameImpl                          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
 #if ( configGENERATE_RUN_TIME_STATS == 1 )
 
 configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.c
index 9e1b9ed85..2d1218a95 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.c
@@ -396,34 +396,6 @@ UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREE
 }
 /*-----------------------------------------------------------*/
 
-char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pcTaskGetNameImpl                         \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_pcTaskGetName_Unpriv                          \n"
-        " MPU_pcTaskGetName_Priv:                               \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_pcTaskGetNameImpl                           \n"
-        " MPU_pcTaskGetName_Unpriv:                             \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pcTaskGetNameImpl                          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
 #if ( configGENERATE_RUN_TIME_STATS == 1 )
 
 configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
diff --git a/portable/IAR/ARM_CM23/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM23/non_secure/mpu_wrappers_v2_asm.S
index f2098b57d..5300a99ec 100644
--- a/portable/IAR/ARM_CM23/non_secure/mpu_wrappers_v2_asm.S
+++ b/portable/IAR/ARM_CM23/non_secure/mpu_wrappers_v2_asm.S
@@ -243,24 +243,6 @@ MPU_uxTaskGetNumberOfTasks:
         bx lr
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_pcTaskGetName
-MPU_pcTaskGetName:
-    push {r0, r1}
-    mrs r0, control
-    movs r1, #1
-    tst r0, r1
-    bne MPU_pcTaskGetName_Unpriv
-    MPU_pcTaskGetName_Priv:
-        pop {r0, r1}
-        b MPU_pcTaskGetNameImpl
-    MPU_pcTaskGetName_Unpriv:
-        pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pcTaskGetNameImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-/*-----------------------------------------------------------*/
-
     PUBLIC MPU_ulTaskGetRunTimeCounter
 MPU_ulTaskGetRunTimeCounter:
     push {r0, r1}
@@ -1370,10 +1352,6 @@ MPU_xTaskGetTickCountImpl:
 MPU_uxTaskGetNumberOfTasksImpl:
     b MPU_uxTaskGetNumberOfTasksImpl
 
-    PUBWEAK MPU_pcTaskGetNameImpl
-MPU_pcTaskGetNameImpl:
-    b MPU_pcTaskGetNameImpl
-
     PUBWEAK MPU_ulTaskGetRunTimeCounterImpl
 MPU_ulTaskGetRunTimeCounterImpl:
     b MPU_ulTaskGetRunTimeCounterImpl
diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.S
index f2098b57d..5300a99ec 100644
--- a/portable/IAR/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.S
+++ b/portable/IAR/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.S
@@ -243,24 +243,6 @@ MPU_uxTaskGetNumberOfTasks:
         bx lr
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_pcTaskGetName
-MPU_pcTaskGetName:
-    push {r0, r1}
-    mrs r0, control
-    movs r1, #1
-    tst r0, r1
-    bne MPU_pcTaskGetName_Unpriv
-    MPU_pcTaskGetName_Priv:
-        pop {r0, r1}
-        b MPU_pcTaskGetNameImpl
-    MPU_pcTaskGetName_Unpriv:
-        pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pcTaskGetNameImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-/*-----------------------------------------------------------*/
-
     PUBLIC MPU_ulTaskGetRunTimeCounter
 MPU_ulTaskGetRunTimeCounter:
     push {r0, r1}
@@ -1370,10 +1352,6 @@ MPU_xTaskGetTickCountImpl:
 MPU_uxTaskGetNumberOfTasksImpl:
     b MPU_uxTaskGetNumberOfTasksImpl
 
-    PUBWEAK MPU_pcTaskGetNameImpl
-MPU_pcTaskGetNameImpl:
-    b MPU_pcTaskGetNameImpl
-
     PUBWEAK MPU_ulTaskGetRunTimeCounterImpl
 MPU_ulTaskGetRunTimeCounterImpl:
     b MPU_ulTaskGetRunTimeCounterImpl
diff --git a/portable/IAR/ARM_CM33/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM33/non_secure/mpu_wrappers_v2_asm.S
index 9cb9a9d72..1005dad33 100644
--- a/portable/IAR/ARM_CM33/non_secure/mpu_wrappers_v2_asm.S
+++ b/portable/IAR/ARM_CM33/non_secure/mpu_wrappers_v2_asm.S
@@ -232,23 +232,6 @@ MPU_uxTaskGetNumberOfTasks:
         bx lr
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_pcTaskGetName
-MPU_pcTaskGetName:
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_pcTaskGetName_Unpriv
-    MPU_pcTaskGetName_Priv:
-        pop {r0}
-        b MPU_pcTaskGetNameImpl
-    MPU_pcTaskGetName_Unpriv:
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pcTaskGetNameImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-/*-----------------------------------------------------------*/
-
     PUBLIC MPU_ulTaskGetRunTimeCounter
 MPU_ulTaskGetRunTimeCounter:
     push {r0}
@@ -1299,10 +1282,6 @@ MPU_xTaskGetTickCountImpl:
 MPU_uxTaskGetNumberOfTasksImpl:
     b MPU_uxTaskGetNumberOfTasksImpl
 
-    PUBWEAK MPU_pcTaskGetNameImpl
-MPU_pcTaskGetNameImpl:
-    b MPU_pcTaskGetNameImpl
-
     PUBWEAK MPU_ulTaskGetRunTimeCounterImpl
 MPU_ulTaskGetRunTimeCounterImpl:
     b MPU_ulTaskGetRunTimeCounterImpl
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.S
index 9cb9a9d72..1005dad33 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.S
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.S
@@ -232,23 +232,6 @@ MPU_uxTaskGetNumberOfTasks:
         bx lr
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_pcTaskGetName
-MPU_pcTaskGetName:
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_pcTaskGetName_Unpriv
-    MPU_pcTaskGetName_Priv:
-        pop {r0}
-        b MPU_pcTaskGetNameImpl
-    MPU_pcTaskGetName_Unpriv:
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pcTaskGetNameImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-/*-----------------------------------------------------------*/
-
     PUBLIC MPU_ulTaskGetRunTimeCounter
 MPU_ulTaskGetRunTimeCounter:
     push {r0}
@@ -1299,10 +1282,6 @@ MPU_xTaskGetTickCountImpl:
 MPU_uxTaskGetNumberOfTasksImpl:
     b MPU_uxTaskGetNumberOfTasksImpl
 
-    PUBWEAK MPU_pcTaskGetNameImpl
-MPU_pcTaskGetNameImpl:
-    b MPU_pcTaskGetNameImpl
-
     PUBWEAK MPU_ulTaskGetRunTimeCounterImpl
 MPU_ulTaskGetRunTimeCounterImpl:
     b MPU_ulTaskGetRunTimeCounterImpl
diff --git a/portable/IAR/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.S
index 9cb9a9d72..1005dad33 100644
--- a/portable/IAR/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.S
+++ b/portable/IAR/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.S
@@ -232,23 +232,6 @@ MPU_uxTaskGetNumberOfTasks:
         bx lr
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_pcTaskGetName
-MPU_pcTaskGetName:
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_pcTaskGetName_Unpriv
-    MPU_pcTaskGetName_Priv:
-        pop {r0}
-        b MPU_pcTaskGetNameImpl
-    MPU_pcTaskGetName_Unpriv:
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pcTaskGetNameImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-/*-----------------------------------------------------------*/
-
     PUBLIC MPU_ulTaskGetRunTimeCounter
 MPU_ulTaskGetRunTimeCounter:
     push {r0}
@@ -1299,10 +1282,6 @@ MPU_xTaskGetTickCountImpl:
 MPU_uxTaskGetNumberOfTasksImpl:
     b MPU_uxTaskGetNumberOfTasksImpl
 
-    PUBWEAK MPU_pcTaskGetNameImpl
-MPU_pcTaskGetNameImpl:
-    b MPU_pcTaskGetNameImpl
-
     PUBWEAK MPU_ulTaskGetRunTimeCounterImpl
 MPU_ulTaskGetRunTimeCounterImpl:
     b MPU_ulTaskGetRunTimeCounterImpl
diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.S
index 9cb9a9d72..1005dad33 100644
--- a/portable/IAR/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.S
+++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.S
@@ -232,23 +232,6 @@ MPU_uxTaskGetNumberOfTasks:
         bx lr
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_pcTaskGetName
-MPU_pcTaskGetName:
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_pcTaskGetName_Unpriv
-    MPU_pcTaskGetName_Priv:
-        pop {r0}
-        b MPU_pcTaskGetNameImpl
-    MPU_pcTaskGetName_Unpriv:
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pcTaskGetNameImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-/*-----------------------------------------------------------*/
-
     PUBLIC MPU_ulTaskGetRunTimeCounter
 MPU_ulTaskGetRunTimeCounter:
     push {r0}
@@ -1299,10 +1282,6 @@ MPU_xTaskGetTickCountImpl:
 MPU_uxTaskGetNumberOfTasksImpl:
     b MPU_uxTaskGetNumberOfTasksImpl
 
-    PUBWEAK MPU_pcTaskGetNameImpl
-MPU_pcTaskGetNameImpl:
-    b MPU_pcTaskGetNameImpl
-
     PUBWEAK MPU_ulTaskGetRunTimeCounterImpl
 MPU_ulTaskGetRunTimeCounterImpl:
     b MPU_ulTaskGetRunTimeCounterImpl
diff --git a/portable/IAR/ARM_CM4F_MPU/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM4F_MPU/mpu_wrappers_v2_asm.S
index f18d7410e..8d88af630 100644
--- a/portable/IAR/ARM_CM4F_MPU/mpu_wrappers_v2_asm.S
+++ b/portable/IAR/ARM_CM4F_MPU/mpu_wrappers_v2_asm.S
@@ -236,23 +236,6 @@ MPU_uxTaskGetNumberOfTasks:
         bx lr
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_pcTaskGetName
-MPU_pcTaskGetName:
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_pcTaskGetName_Unpriv
-    MPU_pcTaskGetName_Priv:
-        pop {r0}
-        b MPU_pcTaskGetNameImpl
-    MPU_pcTaskGetName_Unpriv:
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pcTaskGetNameImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-/*-----------------------------------------------------------*/
-
     PUBLIC MPU_ulTaskGetRunTimeCounter
 MPU_ulTaskGetRunTimeCounter:
     push {r0}
@@ -1303,10 +1286,6 @@ MPU_xTaskGetTickCountImpl:
 MPU_uxTaskGetNumberOfTasksImpl:
     b MPU_uxTaskGetNumberOfTasksImpl
 
-    PUBWEAK MPU_pcTaskGetNameImpl
-MPU_pcTaskGetNameImpl:
-    b MPU_pcTaskGetNameImpl
-
     PUBWEAK MPU_ulTaskGetRunTimeCounterImpl
 MPU_ulTaskGetRunTimeCounterImpl:
     b MPU_ulTaskGetRunTimeCounterImpl
diff --git a/portable/IAR/ARM_CM55/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM55/non_secure/mpu_wrappers_v2_asm.S
index 9cb9a9d72..1005dad33 100644
--- a/portable/IAR/ARM_CM55/non_secure/mpu_wrappers_v2_asm.S
+++ b/portable/IAR/ARM_CM55/non_secure/mpu_wrappers_v2_asm.S
@@ -232,23 +232,6 @@ MPU_uxTaskGetNumberOfTasks:
         bx lr
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_pcTaskGetName
-MPU_pcTaskGetName:
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_pcTaskGetName_Unpriv
-    MPU_pcTaskGetName_Priv:
-        pop {r0}
-        b MPU_pcTaskGetNameImpl
-    MPU_pcTaskGetName_Unpriv:
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pcTaskGetNameImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-/*-----------------------------------------------------------*/
-
     PUBLIC MPU_ulTaskGetRunTimeCounter
 MPU_ulTaskGetRunTimeCounter:
     push {r0}
@@ -1299,10 +1282,6 @@ MPU_xTaskGetTickCountImpl:
 MPU_uxTaskGetNumberOfTasksImpl:
     b MPU_uxTaskGetNumberOfTasksImpl
 
-    PUBWEAK MPU_pcTaskGetNameImpl
-MPU_pcTaskGetNameImpl:
-    b MPU_pcTaskGetNameImpl
-
     PUBWEAK MPU_ulTaskGetRunTimeCounterImpl
 MPU_ulTaskGetRunTimeCounterImpl:
     b MPU_ulTaskGetRunTimeCounterImpl
diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.S
index 9cb9a9d72..1005dad33 100644
--- a/portable/IAR/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.S
+++ b/portable/IAR/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.S
@@ -232,23 +232,6 @@ MPU_uxTaskGetNumberOfTasks:
         bx lr
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_pcTaskGetName
-MPU_pcTaskGetName:
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_pcTaskGetName_Unpriv
-    MPU_pcTaskGetName_Priv:
-        pop {r0}
-        b MPU_pcTaskGetNameImpl
-    MPU_pcTaskGetName_Unpriv:
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pcTaskGetNameImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-/*-----------------------------------------------------------*/
-
     PUBLIC MPU_ulTaskGetRunTimeCounter
 MPU_ulTaskGetRunTimeCounter:
     push {r0}
@@ -1299,10 +1282,6 @@ MPU_xTaskGetTickCountImpl:
 MPU_uxTaskGetNumberOfTasksImpl:
     b MPU_uxTaskGetNumberOfTasksImpl
 
-    PUBWEAK MPU_pcTaskGetNameImpl
-MPU_pcTaskGetNameImpl:
-    b MPU_pcTaskGetNameImpl
-
     PUBWEAK MPU_ulTaskGetRunTimeCounterImpl
 MPU_ulTaskGetRunTimeCounterImpl:
     b MPU_ulTaskGetRunTimeCounterImpl
diff --git a/portable/IAR/ARM_CM85/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM85/non_secure/mpu_wrappers_v2_asm.S
index 9cb9a9d72..1005dad33 100644
--- a/portable/IAR/ARM_CM85/non_secure/mpu_wrappers_v2_asm.S
+++ b/portable/IAR/ARM_CM85/non_secure/mpu_wrappers_v2_asm.S
@@ -232,23 +232,6 @@ MPU_uxTaskGetNumberOfTasks:
         bx lr
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_pcTaskGetName
-MPU_pcTaskGetName:
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_pcTaskGetName_Unpriv
-    MPU_pcTaskGetName_Priv:
-        pop {r0}
-        b MPU_pcTaskGetNameImpl
-    MPU_pcTaskGetName_Unpriv:
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pcTaskGetNameImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-/*-----------------------------------------------------------*/
-
     PUBLIC MPU_ulTaskGetRunTimeCounter
 MPU_ulTaskGetRunTimeCounter:
     push {r0}
@@ -1299,10 +1282,6 @@ MPU_xTaskGetTickCountImpl:
 MPU_uxTaskGetNumberOfTasksImpl:
     b MPU_uxTaskGetNumberOfTasksImpl
 
-    PUBWEAK MPU_pcTaskGetNameImpl
-MPU_pcTaskGetNameImpl:
-    b MPU_pcTaskGetNameImpl
-
     PUBWEAK MPU_ulTaskGetRunTimeCounterImpl
 MPU_ulTaskGetRunTimeCounterImpl:
     b MPU_ulTaskGetRunTimeCounterImpl
diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.S
index 9cb9a9d72..1005dad33 100644
--- a/portable/IAR/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.S
+++ b/portable/IAR/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.S
@@ -232,23 +232,6 @@ MPU_uxTaskGetNumberOfTasks:
         bx lr
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_pcTaskGetName
-MPU_pcTaskGetName:
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_pcTaskGetName_Unpriv
-    MPU_pcTaskGetName_Priv:
-        pop {r0}
-        b MPU_pcTaskGetNameImpl
-    MPU_pcTaskGetName_Unpriv:
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pcTaskGetNameImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-/*-----------------------------------------------------------*/
-
     PUBLIC MPU_ulTaskGetRunTimeCounter
 MPU_ulTaskGetRunTimeCounter:
     push {r0}
@@ -1299,10 +1282,6 @@ MPU_xTaskGetTickCountImpl:
 MPU_uxTaskGetNumberOfTasksImpl:
     b MPU_uxTaskGetNumberOfTasksImpl
 
-    PUBWEAK MPU_pcTaskGetNameImpl
-MPU_pcTaskGetNameImpl:
-    b MPU_pcTaskGetNameImpl
-
     PUBWEAK MPU_ulTaskGetRunTimeCounterImpl
 MPU_ulTaskGetRunTimeCounterImpl:
     b MPU_ulTaskGetRunTimeCounterImpl
diff --git a/portable/RVDS/ARM_CM4_MPU/mpu_wrappers_v2_asm.c b/portable/RVDS/ARM_CM4_MPU/mpu_wrappers_v2_asm.c
index 0de1b53bf..e9d0d34a0 100644
--- a/portable/RVDS/ARM_CM4_MPU/mpu_wrappers_v2_asm.c
+++ b/portable/RVDS/ARM_CM4_MPU/mpu_wrappers_v2_asm.c
@@ -341,29 +341,6 @@ MPU_uxTaskGetNumberOfTasks_Unpriv
 }
 /*-----------------------------------------------------------*/
 
-char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) FREERTOS_SYSTEM_CALL;
-
-__asm char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_pcTaskGetNameImpl
-
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_pcTaskGetName_Unpriv
-MPU_pcTaskGetName_Priv
-        pop {r0}
-        b MPU_pcTaskGetNameImpl
-MPU_pcTaskGetName_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pcTaskGetNameImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-}
-/*-----------------------------------------------------------*/
-
 #if ( configGENERATE_RUN_TIME_STATS == 1 )
 
 configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;

From ee0a82be1b9e0c4892f53b571b3b61a2b193edb9 Mon Sep 17 00:00:00 2001
From: Moral-Hao <sihunzhilei@126.com>
Date: Sun, 6 Aug 2023 14:07:44 +0800
Subject: [PATCH 030/424] Fix bug of heap_2 introduced by pr738. (#743)

* Fix bug of heap_2 introduced by pr738.
* Fix formatting check

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: moral-hao <405197809@qq.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 portable/MemMang/heap_2.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/portable/MemMang/heap_2.c b/portable/MemMang/heap_2.c
index 5c3cb55b1..c04144395 100644
--- a/portable/MemMang/heap_2.c
+++ b/portable/MemMang/heap_2.c
@@ -229,9 +229,10 @@ void * pvPortMalloc( size_t xWantedSize )
                         pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
                         pxBlock->xBlockSize = xWantedSize;
 
-                        /* Insert the new block into the list of free blocks. */
-                        pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock;
-                        pxPreviousBlock->pxNextFreeBlock = pxNewBlockLink;
+                        /* Insert the new block into the list of free blocks.
+                         * The list of free blocks is sorted by their size, we have to
+                         * iterate to find the right place to insert new block. */
+                        prvInsertBlockIntoFreeList( ( pxNewBlockLink ) );
                     }
 
                     xFreeBytesRemaining -= pxBlock->xBlockSize;

From 4689d8ff86f9d1730afd790dd9b5c40d71c437dd Mon Sep 17 00:00:00 2001
From: Leonardo de Araujo <46436462+araujo88@users.noreply.github.com>
Date: Mon, 7 Aug 2023 00:42:05 -0300
Subject: [PATCH 031/424] fix: typos in README.md (#744)

Co-authored-by: ActoryOu <jay2002824@gmail.com>
---
 README.md | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/README.md b/README.md
index 38cb58622..540902118 100644
--- a/README.md
+++ b/README.md
@@ -102,15 +102,15 @@ See the readme file in the ```./portable``` directory for more information.
 FreeRTOS files are formatted using the "uncrustify" tool. The configuration file used by uncrustify can be found in the [.github/uncrustify.cfg](.github/uncrustify.cfg) file.
 
 ### Line Endings
-File checked into the FreeRTOS-Kernel repository use unix-style LF line endings for the best compatbility with git.
+File checked into the FreeRTOS-Kernel repository use unix-style LF line endings for the best compatibility with git.
 
-For optmial compatibility with Microsoft Windows tools, it is best to enable the git autocrlf feature. You can eanble this setting for the current repository using the following command:
+For optimal compatibility with Microsoft Windows tools, it is best to enable the git autocrlf feature. You can enable this setting for the current repository using the following command:
 ```
 git config core.autocrlf true
 ```
 
 ### Git History Optimizations
-Some commits in this repository perform large refactors which touch many lines and lead to unwanted behavior when using the `git blame` command. You can configure git to ignore the list of large refactor commits in this repository with the followig command:
+Some commits in this repository perform large refactors which touch many lines and lead to unwanted behavior when using the `git blame` command. You can configure git to ignore the list of large refactor commits in this repository with the following command:
 ```
 git config blame.ignoreRevsFile .git-blame-ignore-revs
 ```

From 05d93e09900e81945600e89a275b182166963eb9 Mon Sep 17 00:00:00 2001
From: kar-rahul-aws <118818625+kar-rahul-aws@users.noreply.github.com>
Date: Mon, 7 Aug 2023 10:27:54 +0530
Subject: [PATCH 032/424] Fix API for NULL task parameter (#741)

* Fix API for NULL task parameter

* Fix uncrustify

---------

Co-authored-by: Ching-Hsin Lee <chinglee@amazon.com>
---
 tasks.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/tasks.c b/tasks.c
index b63073056..f9bb48930 100644
--- a/tasks.c
+++ b/tasks.c
@@ -7430,16 +7430,21 @@ TickType_t uxTaskResetEventItemValue( void )
 
     configRUN_TIME_COUNTER_TYPE ulTaskGetRunTimeCounter( const TaskHandle_t xTask )
     {
-        return xTask->ulRunTimeCounter;
+        TCB_t * pxTCB;
+
+        pxTCB = prvGetTCBFromHandle( xTask );
+
+        return pxTCB->ulRunTimeCounter;
     }
 
-#endif
+#endif /* if ( configGENERATE_RUN_TIME_STATS == 1 ) */
 /*-----------------------------------------------------------*/
 
 #if ( configGENERATE_RUN_TIME_STATS == 1 )
 
     configRUN_TIME_COUNTER_TYPE ulTaskGetRunTimePercent( const TaskHandle_t xTask )
     {
+        TCB_t * pxTCB;
         configRUN_TIME_COUNTER_TYPE ulTotalTime, ulReturn;
 
         ulTotalTime = ( configRUN_TIME_COUNTER_TYPE ) portGET_RUN_TIME_COUNTER_VALUE();
@@ -7450,7 +7455,8 @@ TickType_t uxTaskResetEventItemValue( void )
         /* Avoid divide by zero errors. */
         if( ulTotalTime > ( configRUN_TIME_COUNTER_TYPE ) 0 )
         {
-            ulReturn = xTask->ulRunTimeCounter / ulTotalTime;
+            pxTCB = prvGetTCBFromHandle( xTask );
+            ulReturn = pxTCB->ulRunTimeCounter / ulTotalTime;
         }
         else
         {

From b5f670f826f71414c56d6f05172531ca0adbf5bd Mon Sep 17 00:00:00 2001
From: bebebib-rs <141373055+bebebib-rs@users.noreply.github.com>
Date: Sun, 6 Aug 2023 23:22:52 -0700
Subject: [PATCH 033/424] Fix pxTopOfStack calculation in configINIT_TLS_BLOCK
 for picolib (#739)

The pxTopOfStack calculation in configINIT_TLS_BLOCK for picolib needs
to decrement pxTopOfStack in order to meet the expectation of
 pxPortInitialiseStack function.
---
 include/picolibc-freertos.h | 21 +++++++++++----------
 1 file changed, 11 insertions(+), 10 deletions(-)

diff --git a/include/picolibc-freertos.h b/include/picolibc-freertos.h
index 467f7a970..ef6b7570c 100644
--- a/include/picolibc-freertos.h
+++ b/include/picolibc-freertos.h
@@ -58,18 +58,19 @@
 #endif
 
 /* Allocate thread local storage block off the end of the
-* stack. The _tls_size() function returns the size (in
-* bytes) of the total TLS area used by the application */
+ * stack. The picolibcTLS_SIZE macro returns the size (in
+ * bytes) of the total TLS area used by the application.
+ * Calculate the top of stack address. */
 #if ( portSTACK_GROWTH < 0 )
 
-    #define configINIT_TLS_BLOCK( xTLSBlock, pxTopOfStack )                             \
-    do {                                                                                \
-        pxTopOfStack = ( StackType_t * ) ( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) \
-                                             - picolibcTLS_SIZE ) & ~                   \
-                                           configMAX( picolibcSTACK_ALIGNMENT_MASK,     \
-                                                      picolibcTLS_ALIGNMENT_MASK ) );   \
-        xTLSBlock = pxTopOfStack;                                                       \
-        _init_tls( xTLSBlock );                                                         \
+    #define configINIT_TLS_BLOCK( xTLSBlock, pxTopOfStack )                                  \
+    do {                                                                                     \
+        xTLSBlock = ( void * ) ( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) -              \
+                                   picolibcTLS_SIZE ) &                                      \
+                                 ~picolibcTLS_ALIGNMENT_MASK );                              \
+        pxTopOfStack = ( StackType_t * ) ( ( ( ( portPOINTER_SIZE_TYPE ) xTLSBlock ) - 1 ) & \
+                                           ~picolibcSTACK_ALIGNMENT_MASK );                  \
+        _init_tls( xTLSBlock );                                                              \
     } while( 0 )
 #else /* portSTACK_GROWTH */
     #define configINIT_TLS_BLOCK( xTLSBlock, pxTopOfStack )                                          \

From 6f3586516a42f556db04ae8c1f9394ef9f7e78c5 Mon Sep 17 00:00:00 2001
From: kar-rahul-aws <118818625+kar-rahul-aws@users.noreply.github.com>
Date: Tue, 8 Aug 2023 12:18:34 +0530
Subject: [PATCH 034/424] fix MPU wrapper for vTaskDelete for calling task
 deletion (#745)

---
 portable/Common/mpu_wrappers_v2.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/portable/Common/mpu_wrappers_v2.c b/portable/Common/mpu_wrappers_v2.c
index 3cebd56c7..a9c317055 100644
--- a/portable/Common/mpu_wrappers_v2.c
+++ b/portable/Common/mpu_wrappers_v2.c
@@ -1360,12 +1360,12 @@
                 xInternalTaskHandle = xTaskGetCurrentTaskHandle();
                 lIndex = MPU_GetIndexForTaskHandle( xInternalTaskHandle );
 
-                vTaskDelete( xInternalTaskHandle );
-
                 if( lIndex != -1 )
                 {
                     MPU_SetIndexFreeInKernelObjectPool( lIndex );
                 }
+
+                vTaskDelete( xInternalTaskHandle );
             }
             else
             {
@@ -1377,8 +1377,8 @@
 
                     if( xInternalTaskHandle != NULL )
                     {
-                        vTaskDelete( xInternalTaskHandle );
                         MPU_SetIndexFreeInKernelObjectPool( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                        vTaskDelete( xInternalTaskHandle );
                     }
                 }
             }

From bcd6dbd77293596e3bd69cae68f8b3b3de9f5d4d Mon Sep 17 00:00:00 2001
From: Moral-Hao <sihunzhilei@126.com>
Date: Thu, 17 Aug 2023 00:01:17 +0800
Subject: [PATCH 035/424] Move size calculation out of critical section (#748)

The size calculation in pvPortMalloc uses only parameters and read
only constants and therefore, can be moved out of critical section
to make the critical section as small as possible.
---
 portable/MemMang/heap_2.c | 66 ++++++++++++++++++++++-----------
 portable/MemMang/heap_4.c | 78 +++++++++++++++++++--------------------
 portable/MemMang/heap_5.c | 46 +++++++++++------------
 3 files changed, 106 insertions(+), 84 deletions(-)

diff --git a/portable/MemMang/heap_2.c b/portable/MemMang/heap_2.c
index c04144395..fffcb9ca3 100644
--- a/portable/MemMang/heap_2.c
+++ b/portable/MemMang/heap_2.c
@@ -103,8 +103,8 @@ typedef struct A_BLOCK_LINK
 } BlockLink_t;
 
 
-static const uint16_t heapSTRUCT_SIZE = ( ( sizeof( BlockLink_t ) + ( portBYTE_ALIGNMENT - 1 ) ) & ~( ( size_t ) portBYTE_ALIGNMENT_MASK ) );
-#define heapMINIMUM_BLOCK_SIZE    ( ( size_t ) ( heapSTRUCT_SIZE * 2 ) )
+static const size_t xHeapStructSize = ( ( sizeof( BlockLink_t ) + ( size_t ) ( portBYTE_ALIGNMENT - 1 ) ) & ~( ( size_t ) portBYTE_ALIGNMENT_MASK ) );
+#define heapMINIMUM_BLOCK_SIZE    ( ( size_t ) ( xHeapStructSize * 2 ) )
 
 /* Create a couple of list links to mark the start and end of the list. */
 PRIVILEGED_DATA static BlockLink_t xStart, xEnd;
@@ -159,6 +159,45 @@ void * pvPortMalloc( size_t xWantedSize )
     void * pvReturn = NULL;
     size_t xAdditionalRequiredSize;
 
+    if( xWantedSize > 0 )
+    {
+        /* The wanted size must be increased so it can contain a BlockLink_t
+         * structure in addition to the requested amount of bytes. */
+        if( heapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 )
+        {
+            xWantedSize += xHeapStructSize;
+
+            /* Ensure that blocks are always aligned to the required number
+             * of bytes. */
+            if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
+            {
+                /* Byte alignment required. */
+                xAdditionalRequiredSize = portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK );
+
+                if( heapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 )
+                {
+                    xWantedSize += xAdditionalRequiredSize;
+                }
+                else
+                {
+                    xWantedSize = 0;
+                }
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        else
+        {
+            xWantedSize = 0;
+        }
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+
     vTaskSuspendAll();
     {
         /* If this is the first call to malloc then the heap will require
@@ -169,23 +208,6 @@ void * pvPortMalloc( size_t xWantedSize )
             xHeapHasBeenInitialised = pdTRUE;
         }
 
-        if( xWantedSize > 0 )
-        {
-            /* The wanted size must be increased so it can contain a BlockLink_t
-             * structure in addition to the requested amount of bytes. Some
-             * additional increment may also be needed for alignment. */
-            xAdditionalRequiredSize = heapSTRUCT_SIZE + portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK );
-
-            if( heapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 )
-            {
-                xWantedSize += xAdditionalRequiredSize;
-            }
-            else
-            {
-                xWantedSize = 0;
-            }
-        }
-
         /* Check the block size we are trying to allocate is not so large that the
          * top bit is set.  The top bit of the block size member of the BlockLink_t
          * structure is used to determine who owns the block - the application or
@@ -210,7 +232,7 @@ void * pvPortMalloc( size_t xWantedSize )
                 {
                     /* Return the memory space - jumping over the BlockLink_t structure
                      * at its start. */
-                    pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + heapSTRUCT_SIZE );
+                    pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
 
                     /* This block is being returned for use so must be taken out of the
                      * list of free blocks. */
@@ -271,7 +293,7 @@ void vPortFree( void * pv )
     {
         /* The memory being freed will have an BlockLink_t structure immediately
          * before it. */
-        puc -= heapSTRUCT_SIZE;
+        puc -= xHeapStructSize;
 
         /* This unexpected casting is to keep some compilers from issuing
          * byte alignment warnings. */
@@ -289,7 +311,7 @@ void vPortFree( void * pv )
                 heapFREE_BLOCK( pxLink );
                 #if ( configHEAP_CLEAR_MEMORY_ON_FREE == 1 )
                 {
-                    ( void ) memset( puc + heapSTRUCT_SIZE, 0, pxLink->xBlockSize - heapSTRUCT_SIZE );
+                    ( void ) memset( puc + xHeapStructSize, 0, pxLink->xBlockSize - xHeapStructSize );
                 }
                 #endif
 
diff --git a/portable/MemMang/heap_4.c b/portable/MemMang/heap_4.c
index 63eb94d49..b1053ba40 100644
--- a/portable/MemMang/heap_4.c
+++ b/portable/MemMang/heap_4.c
@@ -143,6 +143,45 @@ void * pvPortMalloc( size_t xWantedSize )
     void * pvReturn = NULL;
     size_t xAdditionalRequiredSize;
 
+    if( xWantedSize > 0 )
+    {
+        /* The wanted size must be increased so it can contain a BlockLink_t
+         * structure in addition to the requested amount of bytes. */
+        if( heapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 )
+        {
+            xWantedSize += xHeapStructSize;
+
+            /* Ensure that blocks are always aligned to the required number
+             * of bytes. */
+            if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
+            {
+                /* Byte alignment required. */
+                xAdditionalRequiredSize = portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK );
+
+                if( heapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 )
+                {
+                    xWantedSize += xAdditionalRequiredSize;
+                }
+                else
+                {
+                    xWantedSize = 0;
+                }
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        else
+        {
+            xWantedSize = 0;
+        }
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+
     vTaskSuspendAll();
     {
         /* If this is the first call to malloc then the heap will require
@@ -156,45 +195,6 @@ void * pvPortMalloc( size_t xWantedSize )
             mtCOVERAGE_TEST_MARKER();
         }
 
-        if( xWantedSize > 0 )
-        {
-            /* The wanted size must be increased so it can contain a BlockLink_t
-             * structure in addition to the requested amount of bytes. */
-            if( heapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 )
-            {
-                xWantedSize += xHeapStructSize;
-
-                /* Ensure that blocks are always aligned to the required number
-                 * of bytes. */
-                if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
-                {
-                    /* Byte alignment required. */
-                    xAdditionalRequiredSize = portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK );
-
-                    if( heapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 )
-                    {
-                        xWantedSize += xAdditionalRequiredSize;
-                    }
-                    else
-                    {
-                        xWantedSize = 0;
-                    }
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
-            }
-            else
-            {
-                xWantedSize = 0;
-            }
-        }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
-        }
-
         /* Check the block size we are trying to allocate is not so large that the
          * top bit is set.  The top bit of the block size member of the BlockLink_t
          * structure is used to determine who owns the block - the application or
diff --git a/portable/MemMang/heap_5.c b/portable/MemMang/heap_5.c
index 198bc611a..618dcf827 100644
--- a/portable/MemMang/heap_5.c
+++ b/portable/MemMang/heap_5.c
@@ -165,47 +165,47 @@ void * pvPortMalloc( size_t xWantedSize )
      * prvPortMalloc(). */
     configASSERT( pxEnd );
 
-    vTaskSuspendAll();
+    if( xWantedSize > 0 )
     {
-        if( xWantedSize > 0 )
+        /* The wanted size must be increased so it can contain a BlockLink_t
+         * structure in addition to the requested amount of bytes. */
+        if( heapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 )
         {
-            /* The wanted size must be increased so it can contain a BlockLink_t
-             * structure in addition to the requested amount of bytes. */
-            if( heapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 )
+            xWantedSize += xHeapStructSize;
+
+            /* Ensure that blocks are always aligned to the required number
+             * of bytes. */
+            if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
             {
-                xWantedSize += xHeapStructSize;
+                /* Byte alignment required. */
+                xAdditionalRequiredSize = portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK );
 
-                /* Ensure that blocks are always aligned to the required number
-                 * of bytes. */
-                if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
+                if( heapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 )
                 {
-                    /* Byte alignment required. */
-                    xAdditionalRequiredSize = portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK );
-
-                    if( heapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 )
-                    {
-                        xWantedSize += xAdditionalRequiredSize;
-                    }
-                    else
-                    {
-                        xWantedSize = 0;
-                    }
+                    xWantedSize += xAdditionalRequiredSize;
                 }
                 else
                 {
-                    mtCOVERAGE_TEST_MARKER();
+                    xWantedSize = 0;
                 }
             }
             else
             {
-                xWantedSize = 0;
+                mtCOVERAGE_TEST_MARKER();
             }
         }
         else
         {
-            mtCOVERAGE_TEST_MARKER();
+            xWantedSize = 0;
         }
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
 
+    vTaskSuspendAll();
+    {
         /* Check the block size we are trying to allocate is not so large that the
          * top bit is set.  The top bit of the block size member of the BlockLink_t
          * structure is used to determine who owns the block - the application or

From bd720c316a39cba26ef7e619a70f87f9017224df Mon Sep 17 00:00:00 2001
From: Moral-Hao <sihunzhilei@126.com>
Date: Thu, 17 Aug 2023 00:26:58 +0800
Subject: [PATCH 036/424] Bring the heap_4 improvements to secure_heap (#749)

This includes improvements like addition overflow checks,
readability improvements.
---
 portable/ARMv8M/secure/heap/secure_heap.c   | 75 +++++++++++++--------
 portable/GCC/ARM_CM23/secure/secure_heap.c  | 75 +++++++++++++--------
 portable/GCC/ARM_CM33/secure/secure_heap.c  | 75 +++++++++++++--------
 portable/GCC/ARM_CM35P/secure/secure_heap.c | 75 +++++++++++++--------
 portable/GCC/ARM_CM55/secure/secure_heap.c  | 75 +++++++++++++--------
 portable/GCC/ARM_CM85/secure/secure_heap.c  | 75 +++++++++++++--------
 portable/IAR/ARM_CM23/secure/secure_heap.c  | 75 +++++++++++++--------
 portable/IAR/ARM_CM33/secure/secure_heap.c  | 75 +++++++++++++--------
 portable/IAR/ARM_CM35P/secure/secure_heap.c | 75 +++++++++++++--------
 portable/IAR/ARM_CM55/secure/secure_heap.c  | 75 +++++++++++++--------
 portable/IAR/ARM_CM85/secure/secure_heap.c  | 75 +++++++++++++--------
 11 files changed, 528 insertions(+), 297 deletions(-)

diff --git a/portable/ARMv8M/secure/heap/secure_heap.c b/portable/ARMv8M/secure/heap/secure_heap.c
index 990125a2a..f3b80df54 100644
--- a/portable/ARMv8M/secure/heap/secure_heap.c
+++ b/portable/ARMv8M/secure/heap/secure_heap.c
@@ -62,6 +62,22 @@
 
 /* Assumes 8bit bytes! */
 #define secureheapBITS_PER_BYTE         ( ( size_t ) 8 )
+
+/* Max value that fits in a size_t type. */
+#define secureheapSIZE_MAX              ( ~( ( size_t ) 0 ) )
+
+/* Check if adding a and b will result in overflow. */
+#define secureheapADD_WILL_OVERFLOW( a, b )         ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) )
+
+/* MSB of the xBlockSize member of an BlockLink_t structure is used to track
+ * the allocation status of a block.  When MSB of the xBlockSize member of
+ * an BlockLink_t structure is set then the block belongs to the application.
+ * When the bit is free the block is still part of the free heap space. */
+#define secureheapBLOCK_ALLOCATED_BITMASK    ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ) )
+#define secureheapBLOCK_SIZE_IS_VALID( xBlockSize )    ( ( ( xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) == 0 )
+#define secureheapBLOCK_IS_ALLOCATED( pxBlock )        ( ( ( pxBlock->xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) != 0 )
+#define secureheapALLOCATE_BLOCK( pxBlock )            ( ( pxBlock->xBlockSize ) |= secureheapBLOCK_ALLOCATED_BITMASK )
+#define secureheapFREE_BLOCK( pxBlock )                ( ( pxBlock->xBlockSize ) &= ~secureheapBLOCK_ALLOCATED_BITMASK )
 /*-----------------------------------------------------------*/
 
 /* Allocate the memory for the heap. */
@@ -123,14 +139,6 @@ static BlockLink_t * pxEnd = NULL;
 static size_t xFreeBytesRemaining = 0U;
 static size_t xMinimumEverFreeBytesRemaining = 0U;
 
-/**
- * @brief Gets set to the top bit of an size_t type.
- *
- * When this bit in the xBlockSize member of an BlockLink_t structure is set
- * then the block belongs to the application. When the bit is free the block is
- * still part of the free heap space.
- */
-static size_t xBlockAllocatedBit = 0;
 /*-----------------------------------------------------------*/
 
 static void prvHeapInit( void )
@@ -175,9 +183,6 @@ static void prvHeapInit( void )
     /* Only one block exists - and it covers the entire usable heap space. */
     xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
     xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
-
-    /* Work out the position of the top bit in a size_t variable. */
-    xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );
 }
 /*-----------------------------------------------------------*/
 
@@ -250,6 +255,7 @@ void * pvPortMalloc( size_t xWantedSize )
     BlockLink_t * pxPreviousBlock;
     BlockLink_t * pxNewBlockLink;
     void * pvReturn = NULL;
+    size_t xAdditionalRequiredSize;
 
     /* If this is the first call to malloc then the heap will require
      * initialisation to setup the list of free blocks. */
@@ -262,25 +268,29 @@ void * pvPortMalloc( size_t xWantedSize )
         mtCOVERAGE_TEST_MARKER();
     }
 
-    /* Check the requested block size is not so large that the top bit is set.
-     * The top bit of the block size member of the BlockLink_t structure is used
-     * to determine who owns the block - the application or the kernel, so it
-     * must be free. */
-    if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+    if( xWantedSize > 0 )
     {
-        /* The wanted size is increased so it can contain a BlockLink_t
+        /* The wanted size must be increased so it can contain a BlockLink_t
          * structure in addition to the requested amount of bytes. */
-        if( xWantedSize > 0 )
+        if( secureheapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 )
         {
             xWantedSize += xHeapStructSize;
 
-            /* Ensure that blocks are always aligned to the required number of
-             * bytes. */
+            /* Ensure that blocks are always aligned to the required number
+             * of bytes. */
             if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )
             {
                 /* Byte alignment required. */
-                xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );
-                secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+                xAdditionalRequiredSize = secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK );
+
+                if( secureheapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 )
+                {
+                    xWantedSize += xAdditionalRequiredSize;
+                }
+                else
+                {
+                    xWantedSize = 0;
+                }
             }
             else
             {
@@ -289,9 +299,20 @@ void * pvPortMalloc( size_t xWantedSize )
         }
         else
         {
-            mtCOVERAGE_TEST_MARKER();
+            xWantedSize = 0;
         }
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
 
+    /* Check the requested block size is not so large that the top bit is set.
+     * The top bit of the block size member of the BlockLink_t structure is used
+     * to determine who owns the block - the application or the kernel, so it
+     * must be free. */
+    if( secureheapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 )
+    {
         if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
         {
             /* Traverse the list from the start (lowest address) block until
@@ -355,7 +376,7 @@ void * pvPortMalloc( size_t xWantedSize )
 
                 /* The block is being returned - it is allocated and owned by
                  * the application and has no "next" block. */
-                pxBlock->xBlockSize |= xBlockAllocatedBit;
+                secureheapALLOCATE_BLOCK( pxBlock );
                 pxBlock->pxNextFreeBlock = NULL;
             }
             else
@@ -409,16 +430,16 @@ void vPortFree( void * pv )
         pxLink = ( void * ) puc;
 
         /* Check the block is actually allocated. */
-        secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+        secureportASSERT( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 );
         secureportASSERT( pxLink->pxNextFreeBlock == NULL );
 
-        if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+        if( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 )
         {
             if( pxLink->pxNextFreeBlock == NULL )
             {
                 /* The block is being returned to the heap - it is no longer
                  * allocated. */
-                pxLink->xBlockSize &= ~xBlockAllocatedBit;
+                secureheapFREE_BLOCK( pxLink );
 
                 secureportDISABLE_NON_SECURE_INTERRUPTS();
                 {
diff --git a/portable/GCC/ARM_CM23/secure/secure_heap.c b/portable/GCC/ARM_CM23/secure/secure_heap.c
index 990125a2a..f3b80df54 100644
--- a/portable/GCC/ARM_CM23/secure/secure_heap.c
+++ b/portable/GCC/ARM_CM23/secure/secure_heap.c
@@ -62,6 +62,22 @@
 
 /* Assumes 8bit bytes! */
 #define secureheapBITS_PER_BYTE         ( ( size_t ) 8 )
+
+/* Max value that fits in a size_t type. */
+#define secureheapSIZE_MAX              ( ~( ( size_t ) 0 ) )
+
+/* Check if adding a and b will result in overflow. */
+#define secureheapADD_WILL_OVERFLOW( a, b )         ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) )
+
+/* MSB of the xBlockSize member of an BlockLink_t structure is used to track
+ * the allocation status of a block.  When MSB of the xBlockSize member of
+ * an BlockLink_t structure is set then the block belongs to the application.
+ * When the bit is free the block is still part of the free heap space. */
+#define secureheapBLOCK_ALLOCATED_BITMASK    ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ) )
+#define secureheapBLOCK_SIZE_IS_VALID( xBlockSize )    ( ( ( xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) == 0 )
+#define secureheapBLOCK_IS_ALLOCATED( pxBlock )        ( ( ( pxBlock->xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) != 0 )
+#define secureheapALLOCATE_BLOCK( pxBlock )            ( ( pxBlock->xBlockSize ) |= secureheapBLOCK_ALLOCATED_BITMASK )
+#define secureheapFREE_BLOCK( pxBlock )                ( ( pxBlock->xBlockSize ) &= ~secureheapBLOCK_ALLOCATED_BITMASK )
 /*-----------------------------------------------------------*/
 
 /* Allocate the memory for the heap. */
@@ -123,14 +139,6 @@ static BlockLink_t * pxEnd = NULL;
 static size_t xFreeBytesRemaining = 0U;
 static size_t xMinimumEverFreeBytesRemaining = 0U;
 
-/**
- * @brief Gets set to the top bit of an size_t type.
- *
- * When this bit in the xBlockSize member of an BlockLink_t structure is set
- * then the block belongs to the application. When the bit is free the block is
- * still part of the free heap space.
- */
-static size_t xBlockAllocatedBit = 0;
 /*-----------------------------------------------------------*/
 
 static void prvHeapInit( void )
@@ -175,9 +183,6 @@ static void prvHeapInit( void )
     /* Only one block exists - and it covers the entire usable heap space. */
     xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
     xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
-
-    /* Work out the position of the top bit in a size_t variable. */
-    xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );
 }
 /*-----------------------------------------------------------*/
 
@@ -250,6 +255,7 @@ void * pvPortMalloc( size_t xWantedSize )
     BlockLink_t * pxPreviousBlock;
     BlockLink_t * pxNewBlockLink;
     void * pvReturn = NULL;
+    size_t xAdditionalRequiredSize;
 
     /* If this is the first call to malloc then the heap will require
      * initialisation to setup the list of free blocks. */
@@ -262,25 +268,29 @@ void * pvPortMalloc( size_t xWantedSize )
         mtCOVERAGE_TEST_MARKER();
     }
 
-    /* Check the requested block size is not so large that the top bit is set.
-     * The top bit of the block size member of the BlockLink_t structure is used
-     * to determine who owns the block - the application or the kernel, so it
-     * must be free. */
-    if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+    if( xWantedSize > 0 )
     {
-        /* The wanted size is increased so it can contain a BlockLink_t
+        /* The wanted size must be increased so it can contain a BlockLink_t
          * structure in addition to the requested amount of bytes. */
-        if( xWantedSize > 0 )
+        if( secureheapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 )
         {
             xWantedSize += xHeapStructSize;
 
-            /* Ensure that blocks are always aligned to the required number of
-             * bytes. */
+            /* Ensure that blocks are always aligned to the required number
+             * of bytes. */
             if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )
             {
                 /* Byte alignment required. */
-                xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );
-                secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+                xAdditionalRequiredSize = secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK );
+
+                if( secureheapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 )
+                {
+                    xWantedSize += xAdditionalRequiredSize;
+                }
+                else
+                {
+                    xWantedSize = 0;
+                }
             }
             else
             {
@@ -289,9 +299,20 @@ void * pvPortMalloc( size_t xWantedSize )
         }
         else
         {
-            mtCOVERAGE_TEST_MARKER();
+            xWantedSize = 0;
         }
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
 
+    /* Check the requested block size is not so large that the top bit is set.
+     * The top bit of the block size member of the BlockLink_t structure is used
+     * to determine who owns the block - the application or the kernel, so it
+     * must be free. */
+    if( secureheapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 )
+    {
         if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
         {
             /* Traverse the list from the start (lowest address) block until
@@ -355,7 +376,7 @@ void * pvPortMalloc( size_t xWantedSize )
 
                 /* The block is being returned - it is allocated and owned by
                  * the application and has no "next" block. */
-                pxBlock->xBlockSize |= xBlockAllocatedBit;
+                secureheapALLOCATE_BLOCK( pxBlock );
                 pxBlock->pxNextFreeBlock = NULL;
             }
             else
@@ -409,16 +430,16 @@ void vPortFree( void * pv )
         pxLink = ( void * ) puc;
 
         /* Check the block is actually allocated. */
-        secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+        secureportASSERT( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 );
         secureportASSERT( pxLink->pxNextFreeBlock == NULL );
 
-        if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+        if( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 )
         {
             if( pxLink->pxNextFreeBlock == NULL )
             {
                 /* The block is being returned to the heap - it is no longer
                  * allocated. */
-                pxLink->xBlockSize &= ~xBlockAllocatedBit;
+                secureheapFREE_BLOCK( pxLink );
 
                 secureportDISABLE_NON_SECURE_INTERRUPTS();
                 {
diff --git a/portable/GCC/ARM_CM33/secure/secure_heap.c b/portable/GCC/ARM_CM33/secure/secure_heap.c
index 990125a2a..f3b80df54 100644
--- a/portable/GCC/ARM_CM33/secure/secure_heap.c
+++ b/portable/GCC/ARM_CM33/secure/secure_heap.c
@@ -62,6 +62,22 @@
 
 /* Assumes 8bit bytes! */
 #define secureheapBITS_PER_BYTE         ( ( size_t ) 8 )
+
+/* Max value that fits in a size_t type. */
+#define secureheapSIZE_MAX              ( ~( ( size_t ) 0 ) )
+
+/* Check if adding a and b will result in overflow. */
+#define secureheapADD_WILL_OVERFLOW( a, b )         ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) )
+
+/* MSB of the xBlockSize member of an BlockLink_t structure is used to track
+ * the allocation status of a block.  When MSB of the xBlockSize member of
+ * an BlockLink_t structure is set then the block belongs to the application.
+ * When the bit is free the block is still part of the free heap space. */
+#define secureheapBLOCK_ALLOCATED_BITMASK    ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ) )
+#define secureheapBLOCK_SIZE_IS_VALID( xBlockSize )    ( ( ( xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) == 0 )
+#define secureheapBLOCK_IS_ALLOCATED( pxBlock )        ( ( ( pxBlock->xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) != 0 )
+#define secureheapALLOCATE_BLOCK( pxBlock )            ( ( pxBlock->xBlockSize ) |= secureheapBLOCK_ALLOCATED_BITMASK )
+#define secureheapFREE_BLOCK( pxBlock )                ( ( pxBlock->xBlockSize ) &= ~secureheapBLOCK_ALLOCATED_BITMASK )
 /*-----------------------------------------------------------*/
 
 /* Allocate the memory for the heap. */
@@ -123,14 +139,6 @@ static BlockLink_t * pxEnd = NULL;
 static size_t xFreeBytesRemaining = 0U;
 static size_t xMinimumEverFreeBytesRemaining = 0U;
 
-/**
- * @brief Gets set to the top bit of an size_t type.
- *
- * When this bit in the xBlockSize member of an BlockLink_t structure is set
- * then the block belongs to the application. When the bit is free the block is
- * still part of the free heap space.
- */
-static size_t xBlockAllocatedBit = 0;
 /*-----------------------------------------------------------*/
 
 static void prvHeapInit( void )
@@ -175,9 +183,6 @@ static void prvHeapInit( void )
     /* Only one block exists - and it covers the entire usable heap space. */
     xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
     xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
-
-    /* Work out the position of the top bit in a size_t variable. */
-    xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );
 }
 /*-----------------------------------------------------------*/
 
@@ -250,6 +255,7 @@ void * pvPortMalloc( size_t xWantedSize )
     BlockLink_t * pxPreviousBlock;
     BlockLink_t * pxNewBlockLink;
     void * pvReturn = NULL;
+    size_t xAdditionalRequiredSize;
 
     /* If this is the first call to malloc then the heap will require
      * initialisation to setup the list of free blocks. */
@@ -262,25 +268,29 @@ void * pvPortMalloc( size_t xWantedSize )
         mtCOVERAGE_TEST_MARKER();
     }
 
-    /* Check the requested block size is not so large that the top bit is set.
-     * The top bit of the block size member of the BlockLink_t structure is used
-     * to determine who owns the block - the application or the kernel, so it
-     * must be free. */
-    if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+    if( xWantedSize > 0 )
     {
-        /* The wanted size is increased so it can contain a BlockLink_t
+        /* The wanted size must be increased so it can contain a BlockLink_t
          * structure in addition to the requested amount of bytes. */
-        if( xWantedSize > 0 )
+        if( secureheapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 )
         {
             xWantedSize += xHeapStructSize;
 
-            /* Ensure that blocks are always aligned to the required number of
-             * bytes. */
+            /* Ensure that blocks are always aligned to the required number
+             * of bytes. */
             if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )
             {
                 /* Byte alignment required. */
-                xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );
-                secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+                xAdditionalRequiredSize = secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK );
+
+                if( secureheapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 )
+                {
+                    xWantedSize += xAdditionalRequiredSize;
+                }
+                else
+                {
+                    xWantedSize = 0;
+                }
             }
             else
             {
@@ -289,9 +299,20 @@ void * pvPortMalloc( size_t xWantedSize )
         }
         else
         {
-            mtCOVERAGE_TEST_MARKER();
+            xWantedSize = 0;
         }
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
 
+    /* Check the requested block size is not so large that the top bit is set.
+     * The top bit of the block size member of the BlockLink_t structure is used
+     * to determine who owns the block - the application or the kernel, so it
+     * must be free. */
+    if( secureheapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 )
+    {
         if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
         {
             /* Traverse the list from the start (lowest address) block until
@@ -355,7 +376,7 @@ void * pvPortMalloc( size_t xWantedSize )
 
                 /* The block is being returned - it is allocated and owned by
                  * the application and has no "next" block. */
-                pxBlock->xBlockSize |= xBlockAllocatedBit;
+                secureheapALLOCATE_BLOCK( pxBlock );
                 pxBlock->pxNextFreeBlock = NULL;
             }
             else
@@ -409,16 +430,16 @@ void vPortFree( void * pv )
         pxLink = ( void * ) puc;
 
         /* Check the block is actually allocated. */
-        secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+        secureportASSERT( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 );
         secureportASSERT( pxLink->pxNextFreeBlock == NULL );
 
-        if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+        if( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 )
         {
             if( pxLink->pxNextFreeBlock == NULL )
             {
                 /* The block is being returned to the heap - it is no longer
                  * allocated. */
-                pxLink->xBlockSize &= ~xBlockAllocatedBit;
+                secureheapFREE_BLOCK( pxLink );
 
                 secureportDISABLE_NON_SECURE_INTERRUPTS();
                 {
diff --git a/portable/GCC/ARM_CM35P/secure/secure_heap.c b/portable/GCC/ARM_CM35P/secure/secure_heap.c
index 990125a2a..f3b80df54 100644
--- a/portable/GCC/ARM_CM35P/secure/secure_heap.c
+++ b/portable/GCC/ARM_CM35P/secure/secure_heap.c
@@ -62,6 +62,22 @@
 
 /* Assumes 8bit bytes! */
 #define secureheapBITS_PER_BYTE         ( ( size_t ) 8 )
+
+/* Max value that fits in a size_t type. */
+#define secureheapSIZE_MAX              ( ~( ( size_t ) 0 ) )
+
+/* Check if adding a and b will result in overflow. */
+#define secureheapADD_WILL_OVERFLOW( a, b )         ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) )
+
+/* MSB of the xBlockSize member of an BlockLink_t structure is used to track
+ * the allocation status of a block.  When MSB of the xBlockSize member of
+ * an BlockLink_t structure is set then the block belongs to the application.
+ * When the bit is free the block is still part of the free heap space. */
+#define secureheapBLOCK_ALLOCATED_BITMASK    ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ) )
+#define secureheapBLOCK_SIZE_IS_VALID( xBlockSize )    ( ( ( xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) == 0 )
+#define secureheapBLOCK_IS_ALLOCATED( pxBlock )        ( ( ( pxBlock->xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) != 0 )
+#define secureheapALLOCATE_BLOCK( pxBlock )            ( ( pxBlock->xBlockSize ) |= secureheapBLOCK_ALLOCATED_BITMASK )
+#define secureheapFREE_BLOCK( pxBlock )                ( ( pxBlock->xBlockSize ) &= ~secureheapBLOCK_ALLOCATED_BITMASK )
 /*-----------------------------------------------------------*/
 
 /* Allocate the memory for the heap. */
@@ -123,14 +139,6 @@ static BlockLink_t * pxEnd = NULL;
 static size_t xFreeBytesRemaining = 0U;
 static size_t xMinimumEverFreeBytesRemaining = 0U;
 
-/**
- * @brief Gets set to the top bit of an size_t type.
- *
- * When this bit in the xBlockSize member of an BlockLink_t structure is set
- * then the block belongs to the application. When the bit is free the block is
- * still part of the free heap space.
- */
-static size_t xBlockAllocatedBit = 0;
 /*-----------------------------------------------------------*/
 
 static void prvHeapInit( void )
@@ -175,9 +183,6 @@ static void prvHeapInit( void )
     /* Only one block exists - and it covers the entire usable heap space. */
     xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
     xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
-
-    /* Work out the position of the top bit in a size_t variable. */
-    xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );
 }
 /*-----------------------------------------------------------*/
 
@@ -250,6 +255,7 @@ void * pvPortMalloc( size_t xWantedSize )
     BlockLink_t * pxPreviousBlock;
     BlockLink_t * pxNewBlockLink;
     void * pvReturn = NULL;
+    size_t xAdditionalRequiredSize;
 
     /* If this is the first call to malloc then the heap will require
      * initialisation to setup the list of free blocks. */
@@ -262,25 +268,29 @@ void * pvPortMalloc( size_t xWantedSize )
         mtCOVERAGE_TEST_MARKER();
     }
 
-    /* Check the requested block size is not so large that the top bit is set.
-     * The top bit of the block size member of the BlockLink_t structure is used
-     * to determine who owns the block - the application or the kernel, so it
-     * must be free. */
-    if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+    if( xWantedSize > 0 )
     {
-        /* The wanted size is increased so it can contain a BlockLink_t
+        /* The wanted size must be increased so it can contain a BlockLink_t
          * structure in addition to the requested amount of bytes. */
-        if( xWantedSize > 0 )
+        if( secureheapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 )
         {
             xWantedSize += xHeapStructSize;
 
-            /* Ensure that blocks are always aligned to the required number of
-             * bytes. */
+            /* Ensure that blocks are always aligned to the required number
+             * of bytes. */
             if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )
             {
                 /* Byte alignment required. */
-                xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );
-                secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+                xAdditionalRequiredSize = secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK );
+
+                if( secureheapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 )
+                {
+                    xWantedSize += xAdditionalRequiredSize;
+                }
+                else
+                {
+                    xWantedSize = 0;
+                }
             }
             else
             {
@@ -289,9 +299,20 @@ void * pvPortMalloc( size_t xWantedSize )
         }
         else
         {
-            mtCOVERAGE_TEST_MARKER();
+            xWantedSize = 0;
         }
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
 
+    /* Check the requested block size is not so large that the top bit is set.
+     * The top bit of the block size member of the BlockLink_t structure is used
+     * to determine who owns the block - the application or the kernel, so it
+     * must be free. */
+    if( secureheapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 )
+    {
         if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
         {
             /* Traverse the list from the start (lowest address) block until
@@ -355,7 +376,7 @@ void * pvPortMalloc( size_t xWantedSize )
 
                 /* The block is being returned - it is allocated and owned by
                  * the application and has no "next" block. */
-                pxBlock->xBlockSize |= xBlockAllocatedBit;
+                secureheapALLOCATE_BLOCK( pxBlock );
                 pxBlock->pxNextFreeBlock = NULL;
             }
             else
@@ -409,16 +430,16 @@ void vPortFree( void * pv )
         pxLink = ( void * ) puc;
 
         /* Check the block is actually allocated. */
-        secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+        secureportASSERT( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 );
         secureportASSERT( pxLink->pxNextFreeBlock == NULL );
 
-        if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+        if( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 )
         {
             if( pxLink->pxNextFreeBlock == NULL )
             {
                 /* The block is being returned to the heap - it is no longer
                  * allocated. */
-                pxLink->xBlockSize &= ~xBlockAllocatedBit;
+                secureheapFREE_BLOCK( pxLink );
 
                 secureportDISABLE_NON_SECURE_INTERRUPTS();
                 {
diff --git a/portable/GCC/ARM_CM55/secure/secure_heap.c b/portable/GCC/ARM_CM55/secure/secure_heap.c
index 990125a2a..f3b80df54 100644
--- a/portable/GCC/ARM_CM55/secure/secure_heap.c
+++ b/portable/GCC/ARM_CM55/secure/secure_heap.c
@@ -62,6 +62,22 @@
 
 /* Assumes 8bit bytes! */
 #define secureheapBITS_PER_BYTE         ( ( size_t ) 8 )
+
+/* Max value that fits in a size_t type. */
+#define secureheapSIZE_MAX              ( ~( ( size_t ) 0 ) )
+
+/* Check if adding a and b will result in overflow. */
+#define secureheapADD_WILL_OVERFLOW( a, b )         ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) )
+
+/* MSB of the xBlockSize member of an BlockLink_t structure is used to track
+ * the allocation status of a block.  When MSB of the xBlockSize member of
+ * an BlockLink_t structure is set then the block belongs to the application.
+ * When the bit is free the block is still part of the free heap space. */
+#define secureheapBLOCK_ALLOCATED_BITMASK    ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ) )
+#define secureheapBLOCK_SIZE_IS_VALID( xBlockSize )    ( ( ( xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) == 0 )
+#define secureheapBLOCK_IS_ALLOCATED( pxBlock )        ( ( ( pxBlock->xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) != 0 )
+#define secureheapALLOCATE_BLOCK( pxBlock )            ( ( pxBlock->xBlockSize ) |= secureheapBLOCK_ALLOCATED_BITMASK )
+#define secureheapFREE_BLOCK( pxBlock )                ( ( pxBlock->xBlockSize ) &= ~secureheapBLOCK_ALLOCATED_BITMASK )
 /*-----------------------------------------------------------*/
 
 /* Allocate the memory for the heap. */
@@ -123,14 +139,6 @@ static BlockLink_t * pxEnd = NULL;
 static size_t xFreeBytesRemaining = 0U;
 static size_t xMinimumEverFreeBytesRemaining = 0U;
 
-/**
- * @brief Gets set to the top bit of an size_t type.
- *
- * When this bit in the xBlockSize member of an BlockLink_t structure is set
- * then the block belongs to the application. When the bit is free the block is
- * still part of the free heap space.
- */
-static size_t xBlockAllocatedBit = 0;
 /*-----------------------------------------------------------*/
 
 static void prvHeapInit( void )
@@ -175,9 +183,6 @@ static void prvHeapInit( void )
     /* Only one block exists - and it covers the entire usable heap space. */
     xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
     xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
-
-    /* Work out the position of the top bit in a size_t variable. */
-    xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );
 }
 /*-----------------------------------------------------------*/
 
@@ -250,6 +255,7 @@ void * pvPortMalloc( size_t xWantedSize )
     BlockLink_t * pxPreviousBlock;
     BlockLink_t * pxNewBlockLink;
     void * pvReturn = NULL;
+    size_t xAdditionalRequiredSize;
 
     /* If this is the first call to malloc then the heap will require
      * initialisation to setup the list of free blocks. */
@@ -262,25 +268,29 @@ void * pvPortMalloc( size_t xWantedSize )
         mtCOVERAGE_TEST_MARKER();
     }
 
-    /* Check the requested block size is not so large that the top bit is set.
-     * The top bit of the block size member of the BlockLink_t structure is used
-     * to determine who owns the block - the application or the kernel, so it
-     * must be free. */
-    if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+    if( xWantedSize > 0 )
     {
-        /* The wanted size is increased so it can contain a BlockLink_t
+        /* The wanted size must be increased so it can contain a BlockLink_t
          * structure in addition to the requested amount of bytes. */
-        if( xWantedSize > 0 )
+        if( secureheapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 )
         {
             xWantedSize += xHeapStructSize;
 
-            /* Ensure that blocks are always aligned to the required number of
-             * bytes. */
+            /* Ensure that blocks are always aligned to the required number
+             * of bytes. */
             if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )
             {
                 /* Byte alignment required. */
-                xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );
-                secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+                xAdditionalRequiredSize = secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK );
+
+                if( secureheapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 )
+                {
+                    xWantedSize += xAdditionalRequiredSize;
+                }
+                else
+                {
+                    xWantedSize = 0;
+                }
             }
             else
             {
@@ -289,9 +299,20 @@ void * pvPortMalloc( size_t xWantedSize )
         }
         else
         {
-            mtCOVERAGE_TEST_MARKER();
+            xWantedSize = 0;
         }
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
 
+    /* Check the requested block size is not so large that the top bit is set.
+     * The top bit of the block size member of the BlockLink_t structure is used
+     * to determine who owns the block - the application or the kernel, so it
+     * must be free. */
+    if( secureheapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 )
+    {
         if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
         {
             /* Traverse the list from the start (lowest address) block until
@@ -355,7 +376,7 @@ void * pvPortMalloc( size_t xWantedSize )
 
                 /* The block is being returned - it is allocated and owned by
                  * the application and has no "next" block. */
-                pxBlock->xBlockSize |= xBlockAllocatedBit;
+                secureheapALLOCATE_BLOCK( pxBlock );
                 pxBlock->pxNextFreeBlock = NULL;
             }
             else
@@ -409,16 +430,16 @@ void vPortFree( void * pv )
         pxLink = ( void * ) puc;
 
         /* Check the block is actually allocated. */
-        secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+        secureportASSERT( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 );
         secureportASSERT( pxLink->pxNextFreeBlock == NULL );
 
-        if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+        if( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 )
         {
             if( pxLink->pxNextFreeBlock == NULL )
             {
                 /* The block is being returned to the heap - it is no longer
                  * allocated. */
-                pxLink->xBlockSize &= ~xBlockAllocatedBit;
+                secureheapFREE_BLOCK( pxLink );
 
                 secureportDISABLE_NON_SECURE_INTERRUPTS();
                 {
diff --git a/portable/GCC/ARM_CM85/secure/secure_heap.c b/portable/GCC/ARM_CM85/secure/secure_heap.c
index 990125a2a..f3b80df54 100644
--- a/portable/GCC/ARM_CM85/secure/secure_heap.c
+++ b/portable/GCC/ARM_CM85/secure/secure_heap.c
@@ -62,6 +62,22 @@
 
 /* Assumes 8bit bytes! */
 #define secureheapBITS_PER_BYTE         ( ( size_t ) 8 )
+
+/* Max value that fits in a size_t type. */
+#define secureheapSIZE_MAX              ( ~( ( size_t ) 0 ) )
+
+/* Check if adding a and b will result in overflow. */
+#define secureheapADD_WILL_OVERFLOW( a, b )         ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) )
+
+/* MSB of the xBlockSize member of an BlockLink_t structure is used to track
+ * the allocation status of a block.  When MSB of the xBlockSize member of
+ * an BlockLink_t structure is set then the block belongs to the application.
+ * When the bit is free the block is still part of the free heap space. */
+#define secureheapBLOCK_ALLOCATED_BITMASK    ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ) )
+#define secureheapBLOCK_SIZE_IS_VALID( xBlockSize )    ( ( ( xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) == 0 )
+#define secureheapBLOCK_IS_ALLOCATED( pxBlock )        ( ( ( pxBlock->xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) != 0 )
+#define secureheapALLOCATE_BLOCK( pxBlock )            ( ( pxBlock->xBlockSize ) |= secureheapBLOCK_ALLOCATED_BITMASK )
+#define secureheapFREE_BLOCK( pxBlock )                ( ( pxBlock->xBlockSize ) &= ~secureheapBLOCK_ALLOCATED_BITMASK )
 /*-----------------------------------------------------------*/
 
 /* Allocate the memory for the heap. */
@@ -123,14 +139,6 @@ static BlockLink_t * pxEnd = NULL;
 static size_t xFreeBytesRemaining = 0U;
 static size_t xMinimumEverFreeBytesRemaining = 0U;
 
-/**
- * @brief Gets set to the top bit of an size_t type.
- *
- * When this bit in the xBlockSize member of an BlockLink_t structure is set
- * then the block belongs to the application. When the bit is free the block is
- * still part of the free heap space.
- */
-static size_t xBlockAllocatedBit = 0;
 /*-----------------------------------------------------------*/
 
 static void prvHeapInit( void )
@@ -175,9 +183,6 @@ static void prvHeapInit( void )
     /* Only one block exists - and it covers the entire usable heap space. */
     xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
     xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
-
-    /* Work out the position of the top bit in a size_t variable. */
-    xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );
 }
 /*-----------------------------------------------------------*/
 
@@ -250,6 +255,7 @@ void * pvPortMalloc( size_t xWantedSize )
     BlockLink_t * pxPreviousBlock;
     BlockLink_t * pxNewBlockLink;
     void * pvReturn = NULL;
+    size_t xAdditionalRequiredSize;
 
     /* If this is the first call to malloc then the heap will require
      * initialisation to setup the list of free blocks. */
@@ -262,25 +268,29 @@ void * pvPortMalloc( size_t xWantedSize )
         mtCOVERAGE_TEST_MARKER();
     }
 
-    /* Check the requested block size is not so large that the top bit is set.
-     * The top bit of the block size member of the BlockLink_t structure is used
-     * to determine who owns the block - the application or the kernel, so it
-     * must be free. */
-    if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+    if( xWantedSize > 0 )
     {
-        /* The wanted size is increased so it can contain a BlockLink_t
+        /* The wanted size must be increased so it can contain a BlockLink_t
          * structure in addition to the requested amount of bytes. */
-        if( xWantedSize > 0 )
+        if( secureheapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 )
         {
             xWantedSize += xHeapStructSize;
 
-            /* Ensure that blocks are always aligned to the required number of
-             * bytes. */
+            /* Ensure that blocks are always aligned to the required number
+             * of bytes. */
             if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )
             {
                 /* Byte alignment required. */
-                xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );
-                secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+                xAdditionalRequiredSize = secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK );
+
+                if( secureheapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 )
+                {
+                    xWantedSize += xAdditionalRequiredSize;
+                }
+                else
+                {
+                    xWantedSize = 0;
+                }
             }
             else
             {
@@ -289,9 +299,20 @@ void * pvPortMalloc( size_t xWantedSize )
         }
         else
         {
-            mtCOVERAGE_TEST_MARKER();
+            xWantedSize = 0;
         }
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
 
+    /* Check the requested block size is not so large that the top bit is set.
+     * The top bit of the block size member of the BlockLink_t structure is used
+     * to determine who owns the block - the application or the kernel, so it
+     * must be free. */
+    if( secureheapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 )
+    {
         if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
         {
             /* Traverse the list from the start (lowest address) block until
@@ -355,7 +376,7 @@ void * pvPortMalloc( size_t xWantedSize )
 
                 /* The block is being returned - it is allocated and owned by
                  * the application and has no "next" block. */
-                pxBlock->xBlockSize |= xBlockAllocatedBit;
+                secureheapALLOCATE_BLOCK( pxBlock );
                 pxBlock->pxNextFreeBlock = NULL;
             }
             else
@@ -409,16 +430,16 @@ void vPortFree( void * pv )
         pxLink = ( void * ) puc;
 
         /* Check the block is actually allocated. */
-        secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+        secureportASSERT( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 );
         secureportASSERT( pxLink->pxNextFreeBlock == NULL );
 
-        if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+        if( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 )
         {
             if( pxLink->pxNextFreeBlock == NULL )
             {
                 /* The block is being returned to the heap - it is no longer
                  * allocated. */
-                pxLink->xBlockSize &= ~xBlockAllocatedBit;
+                secureheapFREE_BLOCK( pxLink );
 
                 secureportDISABLE_NON_SECURE_INTERRUPTS();
                 {
diff --git a/portable/IAR/ARM_CM23/secure/secure_heap.c b/portable/IAR/ARM_CM23/secure/secure_heap.c
index 990125a2a..f3b80df54 100644
--- a/portable/IAR/ARM_CM23/secure/secure_heap.c
+++ b/portable/IAR/ARM_CM23/secure/secure_heap.c
@@ -62,6 +62,22 @@
 
 /* Assumes 8bit bytes! */
 #define secureheapBITS_PER_BYTE         ( ( size_t ) 8 )
+
+/* Max value that fits in a size_t type. */
+#define secureheapSIZE_MAX              ( ~( ( size_t ) 0 ) )
+
+/* Check if adding a and b will result in overflow. */
+#define secureheapADD_WILL_OVERFLOW( a, b )         ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) )
+
+/* MSB of the xBlockSize member of an BlockLink_t structure is used to track
+ * the allocation status of a block.  When MSB of the xBlockSize member of
+ * an BlockLink_t structure is set then the block belongs to the application.
+ * When the bit is free the block is still part of the free heap space. */
+#define secureheapBLOCK_ALLOCATED_BITMASK    ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ) )
+#define secureheapBLOCK_SIZE_IS_VALID( xBlockSize )    ( ( ( xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) == 0 )
+#define secureheapBLOCK_IS_ALLOCATED( pxBlock )        ( ( ( pxBlock->xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) != 0 )
+#define secureheapALLOCATE_BLOCK( pxBlock )            ( ( pxBlock->xBlockSize ) |= secureheapBLOCK_ALLOCATED_BITMASK )
+#define secureheapFREE_BLOCK( pxBlock )                ( ( pxBlock->xBlockSize ) &= ~secureheapBLOCK_ALLOCATED_BITMASK )
 /*-----------------------------------------------------------*/
 
 /* Allocate the memory for the heap. */
@@ -123,14 +139,6 @@ static BlockLink_t * pxEnd = NULL;
 static size_t xFreeBytesRemaining = 0U;
 static size_t xMinimumEverFreeBytesRemaining = 0U;
 
-/**
- * @brief Gets set to the top bit of an size_t type.
- *
- * When this bit in the xBlockSize member of an BlockLink_t structure is set
- * then the block belongs to the application. When the bit is free the block is
- * still part of the free heap space.
- */
-static size_t xBlockAllocatedBit = 0;
 /*-----------------------------------------------------------*/
 
 static void prvHeapInit( void )
@@ -175,9 +183,6 @@ static void prvHeapInit( void )
     /* Only one block exists - and it covers the entire usable heap space. */
     xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
     xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
-
-    /* Work out the position of the top bit in a size_t variable. */
-    xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );
 }
 /*-----------------------------------------------------------*/
 
@@ -250,6 +255,7 @@ void * pvPortMalloc( size_t xWantedSize )
     BlockLink_t * pxPreviousBlock;
     BlockLink_t * pxNewBlockLink;
     void * pvReturn = NULL;
+    size_t xAdditionalRequiredSize;
 
     /* If this is the first call to malloc then the heap will require
      * initialisation to setup the list of free blocks. */
@@ -262,25 +268,29 @@ void * pvPortMalloc( size_t xWantedSize )
         mtCOVERAGE_TEST_MARKER();
     }
 
-    /* Check the requested block size is not so large that the top bit is set.
-     * The top bit of the block size member of the BlockLink_t structure is used
-     * to determine who owns the block - the application or the kernel, so it
-     * must be free. */
-    if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+    if( xWantedSize > 0 )
     {
-        /* The wanted size is increased so it can contain a BlockLink_t
+        /* The wanted size must be increased so it can contain a BlockLink_t
          * structure in addition to the requested amount of bytes. */
-        if( xWantedSize > 0 )
+        if( secureheapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 )
         {
             xWantedSize += xHeapStructSize;
 
-            /* Ensure that blocks are always aligned to the required number of
-             * bytes. */
+            /* Ensure that blocks are always aligned to the required number
+             * of bytes. */
             if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )
             {
                 /* Byte alignment required. */
-                xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );
-                secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+                xAdditionalRequiredSize = secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK );
+
+                if( secureheapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 )
+                {
+                    xWantedSize += xAdditionalRequiredSize;
+                }
+                else
+                {
+                    xWantedSize = 0;
+                }
             }
             else
             {
@@ -289,9 +299,20 @@ void * pvPortMalloc( size_t xWantedSize )
         }
         else
         {
-            mtCOVERAGE_TEST_MARKER();
+            xWantedSize = 0;
         }
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
 
+    /* Check the requested block size is not so large that the top bit is set.
+     * The top bit of the block size member of the BlockLink_t structure is used
+     * to determine who owns the block - the application or the kernel, so it
+     * must be free. */
+    if( secureheapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 )
+    {
         if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
         {
             /* Traverse the list from the start (lowest address) block until
@@ -355,7 +376,7 @@ void * pvPortMalloc( size_t xWantedSize )
 
                 /* The block is being returned - it is allocated and owned by
                  * the application and has no "next" block. */
-                pxBlock->xBlockSize |= xBlockAllocatedBit;
+                secureheapALLOCATE_BLOCK( pxBlock );
                 pxBlock->pxNextFreeBlock = NULL;
             }
             else
@@ -409,16 +430,16 @@ void vPortFree( void * pv )
         pxLink = ( void * ) puc;
 
         /* Check the block is actually allocated. */
-        secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+        secureportASSERT( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 );
         secureportASSERT( pxLink->pxNextFreeBlock == NULL );
 
-        if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+        if( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 )
         {
             if( pxLink->pxNextFreeBlock == NULL )
             {
                 /* The block is being returned to the heap - it is no longer
                  * allocated. */
-                pxLink->xBlockSize &= ~xBlockAllocatedBit;
+                secureheapFREE_BLOCK( pxLink );
 
                 secureportDISABLE_NON_SECURE_INTERRUPTS();
                 {
diff --git a/portable/IAR/ARM_CM33/secure/secure_heap.c b/portable/IAR/ARM_CM33/secure/secure_heap.c
index 990125a2a..f3b80df54 100644
--- a/portable/IAR/ARM_CM33/secure/secure_heap.c
+++ b/portable/IAR/ARM_CM33/secure/secure_heap.c
@@ -62,6 +62,22 @@
 
 /* Assumes 8bit bytes! */
 #define secureheapBITS_PER_BYTE         ( ( size_t ) 8 )
+
+/* Max value that fits in a size_t type. */
+#define secureheapSIZE_MAX              ( ~( ( size_t ) 0 ) )
+
+/* Check if adding a and b will result in overflow. */
+#define secureheapADD_WILL_OVERFLOW( a, b )         ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) )
+
+/* MSB of the xBlockSize member of an BlockLink_t structure is used to track
+ * the allocation status of a block.  When MSB of the xBlockSize member of
+ * an BlockLink_t structure is set then the block belongs to the application.
+ * When the bit is free the block is still part of the free heap space. */
+#define secureheapBLOCK_ALLOCATED_BITMASK    ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ) )
+#define secureheapBLOCK_SIZE_IS_VALID( xBlockSize )    ( ( ( xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) == 0 )
+#define secureheapBLOCK_IS_ALLOCATED( pxBlock )        ( ( ( pxBlock->xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) != 0 )
+#define secureheapALLOCATE_BLOCK( pxBlock )            ( ( pxBlock->xBlockSize ) |= secureheapBLOCK_ALLOCATED_BITMASK )
+#define secureheapFREE_BLOCK( pxBlock )                ( ( pxBlock->xBlockSize ) &= ~secureheapBLOCK_ALLOCATED_BITMASK )
 /*-----------------------------------------------------------*/
 
 /* Allocate the memory for the heap. */
@@ -123,14 +139,6 @@ static BlockLink_t * pxEnd = NULL;
 static size_t xFreeBytesRemaining = 0U;
 static size_t xMinimumEverFreeBytesRemaining = 0U;
 
-/**
- * @brief Gets set to the top bit of an size_t type.
- *
- * When this bit in the xBlockSize member of an BlockLink_t structure is set
- * then the block belongs to the application. When the bit is free the block is
- * still part of the free heap space.
- */
-static size_t xBlockAllocatedBit = 0;
 /*-----------------------------------------------------------*/
 
 static void prvHeapInit( void )
@@ -175,9 +183,6 @@ static void prvHeapInit( void )
     /* Only one block exists - and it covers the entire usable heap space. */
     xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
     xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
-
-    /* Work out the position of the top bit in a size_t variable. */
-    xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );
 }
 /*-----------------------------------------------------------*/
 
@@ -250,6 +255,7 @@ void * pvPortMalloc( size_t xWantedSize )
     BlockLink_t * pxPreviousBlock;
     BlockLink_t * pxNewBlockLink;
     void * pvReturn = NULL;
+    size_t xAdditionalRequiredSize;
 
     /* If this is the first call to malloc then the heap will require
      * initialisation to setup the list of free blocks. */
@@ -262,25 +268,29 @@ void * pvPortMalloc( size_t xWantedSize )
         mtCOVERAGE_TEST_MARKER();
     }
 
-    /* Check the requested block size is not so large that the top bit is set.
-     * The top bit of the block size member of the BlockLink_t structure is used
-     * to determine who owns the block - the application or the kernel, so it
-     * must be free. */
-    if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+    if( xWantedSize > 0 )
     {
-        /* The wanted size is increased so it can contain a BlockLink_t
+        /* The wanted size must be increased so it can contain a BlockLink_t
          * structure in addition to the requested amount of bytes. */
-        if( xWantedSize > 0 )
+        if( secureheapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 )
         {
             xWantedSize += xHeapStructSize;
 
-            /* Ensure that blocks are always aligned to the required number of
-             * bytes. */
+            /* Ensure that blocks are always aligned to the required number
+             * of bytes. */
             if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )
             {
                 /* Byte alignment required. */
-                xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );
-                secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+                xAdditionalRequiredSize = secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK );
+
+                if( secureheapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 )
+                {
+                    xWantedSize += xAdditionalRequiredSize;
+                }
+                else
+                {
+                    xWantedSize = 0;
+                }
             }
             else
             {
@@ -289,9 +299,20 @@ void * pvPortMalloc( size_t xWantedSize )
         }
         else
         {
-            mtCOVERAGE_TEST_MARKER();
+            xWantedSize = 0;
         }
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
 
+    /* Check the requested block size is not so large that the top bit is set.
+     * The top bit of the block size member of the BlockLink_t structure is used
+     * to determine who owns the block - the application or the kernel, so it
+     * must be free. */
+    if( secureheapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 )
+    {
         if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
         {
             /* Traverse the list from the start (lowest address) block until
@@ -355,7 +376,7 @@ void * pvPortMalloc( size_t xWantedSize )
 
                 /* The block is being returned - it is allocated and owned by
                  * the application and has no "next" block. */
-                pxBlock->xBlockSize |= xBlockAllocatedBit;
+                secureheapALLOCATE_BLOCK( pxBlock );
                 pxBlock->pxNextFreeBlock = NULL;
             }
             else
@@ -409,16 +430,16 @@ void vPortFree( void * pv )
         pxLink = ( void * ) puc;
 
         /* Check the block is actually allocated. */
-        secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+        secureportASSERT( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 );
         secureportASSERT( pxLink->pxNextFreeBlock == NULL );
 
-        if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+        if( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 )
         {
             if( pxLink->pxNextFreeBlock == NULL )
             {
                 /* The block is being returned to the heap - it is no longer
                  * allocated. */
-                pxLink->xBlockSize &= ~xBlockAllocatedBit;
+                secureheapFREE_BLOCK( pxLink );
 
                 secureportDISABLE_NON_SECURE_INTERRUPTS();
                 {
diff --git a/portable/IAR/ARM_CM35P/secure/secure_heap.c b/portable/IAR/ARM_CM35P/secure/secure_heap.c
index 990125a2a..f3b80df54 100644
--- a/portable/IAR/ARM_CM35P/secure/secure_heap.c
+++ b/portable/IAR/ARM_CM35P/secure/secure_heap.c
@@ -62,6 +62,22 @@
 
 /* Assumes 8bit bytes! */
 #define secureheapBITS_PER_BYTE         ( ( size_t ) 8 )
+
+/* Max value that fits in a size_t type. */
+#define secureheapSIZE_MAX              ( ~( ( size_t ) 0 ) )
+
+/* Check if adding a and b will result in overflow. */
+#define secureheapADD_WILL_OVERFLOW( a, b )         ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) )
+
+/* MSB of the xBlockSize member of an BlockLink_t structure is used to track
+ * the allocation status of a block.  When MSB of the xBlockSize member of
+ * an BlockLink_t structure is set then the block belongs to the application.
+ * When the bit is free the block is still part of the free heap space. */
+#define secureheapBLOCK_ALLOCATED_BITMASK    ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ) )
+#define secureheapBLOCK_SIZE_IS_VALID( xBlockSize )    ( ( ( xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) == 0 )
+#define secureheapBLOCK_IS_ALLOCATED( pxBlock )        ( ( ( pxBlock->xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) != 0 )
+#define secureheapALLOCATE_BLOCK( pxBlock )            ( ( pxBlock->xBlockSize ) |= secureheapBLOCK_ALLOCATED_BITMASK )
+#define secureheapFREE_BLOCK( pxBlock )                ( ( pxBlock->xBlockSize ) &= ~secureheapBLOCK_ALLOCATED_BITMASK )
 /*-----------------------------------------------------------*/
 
 /* Allocate the memory for the heap. */
@@ -123,14 +139,6 @@ static BlockLink_t * pxEnd = NULL;
 static size_t xFreeBytesRemaining = 0U;
 static size_t xMinimumEverFreeBytesRemaining = 0U;
 
-/**
- * @brief Gets set to the top bit of an size_t type.
- *
- * When this bit in the xBlockSize member of an BlockLink_t structure is set
- * then the block belongs to the application. When the bit is free the block is
- * still part of the free heap space.
- */
-static size_t xBlockAllocatedBit = 0;
 /*-----------------------------------------------------------*/
 
 static void prvHeapInit( void )
@@ -175,9 +183,6 @@ static void prvHeapInit( void )
     /* Only one block exists - and it covers the entire usable heap space. */
     xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
     xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
-
-    /* Work out the position of the top bit in a size_t variable. */
-    xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );
 }
 /*-----------------------------------------------------------*/
 
@@ -250,6 +255,7 @@ void * pvPortMalloc( size_t xWantedSize )
     BlockLink_t * pxPreviousBlock;
     BlockLink_t * pxNewBlockLink;
     void * pvReturn = NULL;
+    size_t xAdditionalRequiredSize;
 
     /* If this is the first call to malloc then the heap will require
      * initialisation to setup the list of free blocks. */
@@ -262,25 +268,29 @@ void * pvPortMalloc( size_t xWantedSize )
         mtCOVERAGE_TEST_MARKER();
     }
 
-    /* Check the requested block size is not so large that the top bit is set.
-     * The top bit of the block size member of the BlockLink_t structure is used
-     * to determine who owns the block - the application or the kernel, so it
-     * must be free. */
-    if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+    if( xWantedSize > 0 )
     {
-        /* The wanted size is increased so it can contain a BlockLink_t
+        /* The wanted size must be increased so it can contain a BlockLink_t
          * structure in addition to the requested amount of bytes. */
-        if( xWantedSize > 0 )
+        if( secureheapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 )
         {
             xWantedSize += xHeapStructSize;
 
-            /* Ensure that blocks are always aligned to the required number of
-             * bytes. */
+            /* Ensure that blocks are always aligned to the required number
+             * of bytes. */
             if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )
             {
                 /* Byte alignment required. */
-                xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );
-                secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+                xAdditionalRequiredSize = secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK );
+
+                if( secureheapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 )
+                {
+                    xWantedSize += xAdditionalRequiredSize;
+                }
+                else
+                {
+                    xWantedSize = 0;
+                }
             }
             else
             {
@@ -289,9 +299,20 @@ void * pvPortMalloc( size_t xWantedSize )
         }
         else
         {
-            mtCOVERAGE_TEST_MARKER();
+            xWantedSize = 0;
         }
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
 
+    /* Check the requested block size is not so large that the top bit is set.
+     * The top bit of the block size member of the BlockLink_t structure is used
+     * to determine who owns the block - the application or the kernel, so it
+     * must be free. */
+    if( secureheapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 )
+    {
         if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
         {
             /* Traverse the list from the start (lowest address) block until
@@ -355,7 +376,7 @@ void * pvPortMalloc( size_t xWantedSize )
 
                 /* The block is being returned - it is allocated and owned by
                  * the application and has no "next" block. */
-                pxBlock->xBlockSize |= xBlockAllocatedBit;
+                secureheapALLOCATE_BLOCK( pxBlock );
                 pxBlock->pxNextFreeBlock = NULL;
             }
             else
@@ -409,16 +430,16 @@ void vPortFree( void * pv )
         pxLink = ( void * ) puc;
 
         /* Check the block is actually allocated. */
-        secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+        secureportASSERT( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 );
         secureportASSERT( pxLink->pxNextFreeBlock == NULL );
 
-        if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+        if( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 )
         {
             if( pxLink->pxNextFreeBlock == NULL )
             {
                 /* The block is being returned to the heap - it is no longer
                  * allocated. */
-                pxLink->xBlockSize &= ~xBlockAllocatedBit;
+                secureheapFREE_BLOCK( pxLink );
 
                 secureportDISABLE_NON_SECURE_INTERRUPTS();
                 {
diff --git a/portable/IAR/ARM_CM55/secure/secure_heap.c b/portable/IAR/ARM_CM55/secure/secure_heap.c
index 990125a2a..f3b80df54 100644
--- a/portable/IAR/ARM_CM55/secure/secure_heap.c
+++ b/portable/IAR/ARM_CM55/secure/secure_heap.c
@@ -62,6 +62,22 @@
 
 /* Assumes 8bit bytes! */
 #define secureheapBITS_PER_BYTE         ( ( size_t ) 8 )
+
+/* Max value that fits in a size_t type. */
+#define secureheapSIZE_MAX              ( ~( ( size_t ) 0 ) )
+
+/* Check if adding a and b will result in overflow. */
+#define secureheapADD_WILL_OVERFLOW( a, b )         ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) )
+
+/* MSB of the xBlockSize member of an BlockLink_t structure is used to track
+ * the allocation status of a block.  When MSB of the xBlockSize member of
+ * an BlockLink_t structure is set then the block belongs to the application.
+ * When the bit is free the block is still part of the free heap space. */
+#define secureheapBLOCK_ALLOCATED_BITMASK    ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ) )
+#define secureheapBLOCK_SIZE_IS_VALID( xBlockSize )    ( ( ( xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) == 0 )
+#define secureheapBLOCK_IS_ALLOCATED( pxBlock )        ( ( ( pxBlock->xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) != 0 )
+#define secureheapALLOCATE_BLOCK( pxBlock )            ( ( pxBlock->xBlockSize ) |= secureheapBLOCK_ALLOCATED_BITMASK )
+#define secureheapFREE_BLOCK( pxBlock )                ( ( pxBlock->xBlockSize ) &= ~secureheapBLOCK_ALLOCATED_BITMASK )
 /*-----------------------------------------------------------*/
 
 /* Allocate the memory for the heap. */
@@ -123,14 +139,6 @@ static BlockLink_t * pxEnd = NULL;
 static size_t xFreeBytesRemaining = 0U;
 static size_t xMinimumEverFreeBytesRemaining = 0U;
 
-/**
- * @brief Gets set to the top bit of an size_t type.
- *
- * When this bit in the xBlockSize member of an BlockLink_t structure is set
- * then the block belongs to the application. When the bit is free the block is
- * still part of the free heap space.
- */
-static size_t xBlockAllocatedBit = 0;
 /*-----------------------------------------------------------*/
 
 static void prvHeapInit( void )
@@ -175,9 +183,6 @@ static void prvHeapInit( void )
     /* Only one block exists - and it covers the entire usable heap space. */
     xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
     xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
-
-    /* Work out the position of the top bit in a size_t variable. */
-    xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );
 }
 /*-----------------------------------------------------------*/
 
@@ -250,6 +255,7 @@ void * pvPortMalloc( size_t xWantedSize )
     BlockLink_t * pxPreviousBlock;
     BlockLink_t * pxNewBlockLink;
     void * pvReturn = NULL;
+    size_t xAdditionalRequiredSize;
 
     /* If this is the first call to malloc then the heap will require
      * initialisation to setup the list of free blocks. */
@@ -262,25 +268,29 @@ void * pvPortMalloc( size_t xWantedSize )
         mtCOVERAGE_TEST_MARKER();
     }
 
-    /* Check the requested block size is not so large that the top bit is set.
-     * The top bit of the block size member of the BlockLink_t structure is used
-     * to determine who owns the block - the application or the kernel, so it
-     * must be free. */
-    if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+    if( xWantedSize > 0 )
     {
-        /* The wanted size is increased so it can contain a BlockLink_t
+        /* The wanted size must be increased so it can contain a BlockLink_t
          * structure in addition to the requested amount of bytes. */
-        if( xWantedSize > 0 )
+        if( secureheapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 )
         {
             xWantedSize += xHeapStructSize;
 
-            /* Ensure that blocks are always aligned to the required number of
-             * bytes. */
+            /* Ensure that blocks are always aligned to the required number
+             * of bytes. */
             if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )
             {
                 /* Byte alignment required. */
-                xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );
-                secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+                xAdditionalRequiredSize = secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK );
+
+                if( secureheapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 )
+                {
+                    xWantedSize += xAdditionalRequiredSize;
+                }
+                else
+                {
+                    xWantedSize = 0;
+                }
             }
             else
             {
@@ -289,9 +299,20 @@ void * pvPortMalloc( size_t xWantedSize )
         }
         else
         {
-            mtCOVERAGE_TEST_MARKER();
+            xWantedSize = 0;
         }
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
 
+    /* Check the requested block size is not so large that the top bit is set.
+     * The top bit of the block size member of the BlockLink_t structure is used
+     * to determine who owns the block - the application or the kernel, so it
+     * must be free. */
+    if( secureheapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 )
+    {
         if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
         {
             /* Traverse the list from the start (lowest address) block until
@@ -355,7 +376,7 @@ void * pvPortMalloc( size_t xWantedSize )
 
                 /* The block is being returned - it is allocated and owned by
                  * the application and has no "next" block. */
-                pxBlock->xBlockSize |= xBlockAllocatedBit;
+                secureheapALLOCATE_BLOCK( pxBlock );
                 pxBlock->pxNextFreeBlock = NULL;
             }
             else
@@ -409,16 +430,16 @@ void vPortFree( void * pv )
         pxLink = ( void * ) puc;
 
         /* Check the block is actually allocated. */
-        secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+        secureportASSERT( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 );
         secureportASSERT( pxLink->pxNextFreeBlock == NULL );
 
-        if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+        if( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 )
         {
             if( pxLink->pxNextFreeBlock == NULL )
             {
                 /* The block is being returned to the heap - it is no longer
                  * allocated. */
-                pxLink->xBlockSize &= ~xBlockAllocatedBit;
+                secureheapFREE_BLOCK( pxLink );
 
                 secureportDISABLE_NON_SECURE_INTERRUPTS();
                 {
diff --git a/portable/IAR/ARM_CM85/secure/secure_heap.c b/portable/IAR/ARM_CM85/secure/secure_heap.c
index 990125a2a..f3b80df54 100644
--- a/portable/IAR/ARM_CM85/secure/secure_heap.c
+++ b/portable/IAR/ARM_CM85/secure/secure_heap.c
@@ -62,6 +62,22 @@
 
 /* Assumes 8bit bytes! */
 #define secureheapBITS_PER_BYTE         ( ( size_t ) 8 )
+
+/* Max value that fits in a size_t type. */
+#define secureheapSIZE_MAX              ( ~( ( size_t ) 0 ) )
+
+/* Check if adding a and b will result in overflow. */
+#define secureheapADD_WILL_OVERFLOW( a, b )         ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) )
+
+/* MSB of the xBlockSize member of an BlockLink_t structure is used to track
+ * the allocation status of a block.  When MSB of the xBlockSize member of
+ * an BlockLink_t structure is set then the block belongs to the application.
+ * When the bit is free the block is still part of the free heap space. */
+#define secureheapBLOCK_ALLOCATED_BITMASK    ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ) )
+#define secureheapBLOCK_SIZE_IS_VALID( xBlockSize )    ( ( ( xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) == 0 )
+#define secureheapBLOCK_IS_ALLOCATED( pxBlock )        ( ( ( pxBlock->xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) != 0 )
+#define secureheapALLOCATE_BLOCK( pxBlock )            ( ( pxBlock->xBlockSize ) |= secureheapBLOCK_ALLOCATED_BITMASK )
+#define secureheapFREE_BLOCK( pxBlock )                ( ( pxBlock->xBlockSize ) &= ~secureheapBLOCK_ALLOCATED_BITMASK )
 /*-----------------------------------------------------------*/
 
 /* Allocate the memory for the heap. */
@@ -123,14 +139,6 @@ static BlockLink_t * pxEnd = NULL;
 static size_t xFreeBytesRemaining = 0U;
 static size_t xMinimumEverFreeBytesRemaining = 0U;
 
-/**
- * @brief Gets set to the top bit of an size_t type.
- *
- * When this bit in the xBlockSize member of an BlockLink_t structure is set
- * then the block belongs to the application. When the bit is free the block is
- * still part of the free heap space.
- */
-static size_t xBlockAllocatedBit = 0;
 /*-----------------------------------------------------------*/
 
 static void prvHeapInit( void )
@@ -175,9 +183,6 @@ static void prvHeapInit( void )
     /* Only one block exists - and it covers the entire usable heap space. */
     xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
     xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
-
-    /* Work out the position of the top bit in a size_t variable. */
-    xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );
 }
 /*-----------------------------------------------------------*/
 
@@ -250,6 +255,7 @@ void * pvPortMalloc( size_t xWantedSize )
     BlockLink_t * pxPreviousBlock;
     BlockLink_t * pxNewBlockLink;
     void * pvReturn = NULL;
+    size_t xAdditionalRequiredSize;
 
     /* If this is the first call to malloc then the heap will require
      * initialisation to setup the list of free blocks. */
@@ -262,25 +268,29 @@ void * pvPortMalloc( size_t xWantedSize )
         mtCOVERAGE_TEST_MARKER();
     }
 
-    /* Check the requested block size is not so large that the top bit is set.
-     * The top bit of the block size member of the BlockLink_t structure is used
-     * to determine who owns the block - the application or the kernel, so it
-     * must be free. */
-    if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+    if( xWantedSize > 0 )
     {
-        /* The wanted size is increased so it can contain a BlockLink_t
+        /* The wanted size must be increased so it can contain a BlockLink_t
          * structure in addition to the requested amount of bytes. */
-        if( xWantedSize > 0 )
+        if( secureheapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 )
         {
             xWantedSize += xHeapStructSize;
 
-            /* Ensure that blocks are always aligned to the required number of
-             * bytes. */
+            /* Ensure that blocks are always aligned to the required number
+             * of bytes. */
             if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )
             {
                 /* Byte alignment required. */
-                xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );
-                secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+                xAdditionalRequiredSize = secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK );
+
+                if( secureheapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 )
+                {
+                    xWantedSize += xAdditionalRequiredSize;
+                }
+                else
+                {
+                    xWantedSize = 0;
+                }
             }
             else
             {
@@ -289,9 +299,20 @@ void * pvPortMalloc( size_t xWantedSize )
         }
         else
         {
-            mtCOVERAGE_TEST_MARKER();
+            xWantedSize = 0;
         }
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
 
+    /* Check the requested block size is not so large that the top bit is set.
+     * The top bit of the block size member of the BlockLink_t structure is used
+     * to determine who owns the block - the application or the kernel, so it
+     * must be free. */
+    if( secureheapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 )
+    {
         if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
         {
             /* Traverse the list from the start (lowest address) block until
@@ -355,7 +376,7 @@ void * pvPortMalloc( size_t xWantedSize )
 
                 /* The block is being returned - it is allocated and owned by
                  * the application and has no "next" block. */
-                pxBlock->xBlockSize |= xBlockAllocatedBit;
+                secureheapALLOCATE_BLOCK( pxBlock );
                 pxBlock->pxNextFreeBlock = NULL;
             }
             else
@@ -409,16 +430,16 @@ void vPortFree( void * pv )
         pxLink = ( void * ) puc;
 
         /* Check the block is actually allocated. */
-        secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+        secureportASSERT( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 );
         secureportASSERT( pxLink->pxNextFreeBlock == NULL );
 
-        if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+        if( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 )
         {
             if( pxLink->pxNextFreeBlock == NULL )
             {
                 /* The block is being returned to the heap - it is no longer
                  * allocated. */
-                pxLink->xBlockSize &= ~xBlockAllocatedBit;
+                secureheapFREE_BLOCK( pxLink );
 
                 secureportDISABLE_NON_SECURE_INTERRUPTS();
                 {

From b1a85116bdbc22063f9ca0df9eadc95e17f221af Mon Sep 17 00:00:00 2001
From: Chien Wong <13152803+ivq@users.noreply.github.com>
Date: Thu, 17 Aug 2023 12:53:10 +0800
Subject: [PATCH 037/424] Add missing stack alignment adjustment if stack grows
 upwards (#751)

Signed-off-by: Chien Wong <m@xv97.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
---
 tasks.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/tasks.c b/tasks.c
index f9bb48930..3a278424e 100644
--- a/tasks.c
+++ b/tasks.c
@@ -1532,9 +1532,10 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
     #else /* portSTACK_GROWTH */
     {
         pxTopOfStack = pxNewTCB->pxStack;
+        pxTopOfStack = ( StackType_t * ) ( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) + portBYTE_ALIGNMENT_MASK ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception.  Avoiding casts between pointers and integers is not practical.  Size differences accounted for using portPOINTER_SIZE_TYPE type.  Checked by assert(). */
 
-        /* Check the alignment of the stack buffer is correct. */
-        configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxNewTCB->pxStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
+        /* Check the alignment of the calculated top of stack is correct. */
+        configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
 
         /* The other extreme of the stack space is required if stack checking is
          * performed. */

From cd87a397366cb009581c9a1ddc92c2d2ae013929 Mon Sep 17 00:00:00 2001
From: kar-rahul-aws <118818625+kar-rahul-aws@users.noreply.github.com>
Date: Thu, 17 Aug 2023 13:37:58 +0530
Subject: [PATCH 038/424] Update version number in manifest.yml (#755)

* Add automation to update version number in manifest.yml

* Make updater file executable
---
 .github/scripts/manifest_updater.py | 32 +++++++++++++++++++++++++++++
 .github/workflows/auto-release.yml  | 17 +++++++++++++--
 2 files changed, 47 insertions(+), 2 deletions(-)
 create mode 100755 .github/scripts/manifest_updater.py

diff --git a/.github/scripts/manifest_updater.py b/.github/scripts/manifest_updater.py
new file mode 100755
index 000000000..684c7cb5a
--- /dev/null
+++ b/.github/scripts/manifest_updater.py
@@ -0,0 +1,32 @@
+#!/usr/bin/env python3
+import os
+import argparse
+
+THIS_FILE_PATH = os.path.dirname(os.path.abspath(__file__))
+MANIFEST_FILE = os.path.join(THIS_FILE_PATH, '..', '..', 'manifest.yml')
+
+def update_manifest_file(new_version_number):
+    updated_lines = []
+    with open(MANIFEST_FILE, 'r') as f:
+        for line in f:
+            line = line.strip()
+            if line.startswith('version'):
+                updated_lines.append(f'version: "v{new_version_number}"\n')
+            else:
+                updated_lines.append(f'{line}\n')
+
+    with open(MANIFEST_FILE, 'w') as f:
+        f.writelines(updated_lines)
+
+def parse_args():
+    parser = argparse.ArgumentParser()
+    parser.add_argument('-v', '--version', required=True, help='New version number.')
+    args = parser.parse_args()
+    return args
+
+def main():
+    args = parse_args()
+    update_manifest_file(args.version)
+
+if __name__ == '__main__':
+    main()
diff --git a/.github/workflows/auto-release.yml b/.github/workflows/auto-release.yml
index 426d8f0c0..21788c8a6 100644
--- a/.github/workflows/auto-release.yml
+++ b/.github/workflows/auto-release.yml
@@ -63,6 +63,19 @@ jobs:
         env:
             GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
 
+      - name : Update version number in manifest.yml
+        working-directory: ./local_kernel
+        run: |
+          ./.github/scripts/manifest_updater.py -v ${{ github.event.inputs.version_number }}
+          exit $?
+
+      - name : Commit version number change in manifest.yml
+        working-directory: ./local_kernel
+        run: |
+          git add .
+          git commit -m '[AUTO][RELEASE]: Update version number in manifest.yml'
+          git push -u origin ${{ github.event.inputs.version_number }}
+
       - name: Generate SBOM
         uses: FreeRTOS/CI-CD-Github-Actions/sbom-generator@main
         with:
@@ -73,7 +86,7 @@ jobs:
         working-directory: ./local_kernel
         run: |
           git add .
-          git commit -m 'Update SBOM'
+          git commit -m '[AUTO][RELEASE]: Update SBOM'
           git push -u origin ${{ github.event.inputs.version_number }}
           echo "COMMIT_SHA_2=$(git rev-parse HEAD)" >> $GITHUB_ENV
 
@@ -81,7 +94,7 @@ jobs:
         run: |
           # Install deps and run
           pip install -r ./tools/.github/scripts/release-requirements.txt
-          ./tools/.github/scripts/release.py FreeRTOS --kernel-repo-path=local_kernel --kernel-commit=${{ env.COMMIT_SHA_2 }} --new-kernel-version=${{ github.event.inputs.version_number }} --new-kernel-main-br-version=${{ github.event.inputs.main_br_version }}
+          ./tools/.github/scripts/release.py ${{ github.repository_owner }} --kernel-repo-path=local_kernel --kernel-commit=${{ env.COMMIT_SHA_2 }} --new-kernel-version=${{ github.event.inputs.version_number }} --new-kernel-main-br-version=${{ github.event.inputs.main_br_version }}
           exit $?
         env:
             GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}

From cdd3678c29b5064db24d34042acc974c57a0babb Mon Sep 17 00:00:00 2001
From: kar-rahul-aws <118818625+kar-rahul-aws@users.noreply.github.com>
Date: Fri, 18 Aug 2023 14:24:44 +0530
Subject: [PATCH 039/424] Add runtime parameter checks (#761)

* Add runtime parameter checks

This commit adds runtime checks for function parameters to mpu_wrappers_v2 file. The same checks are performed
in the API implementation using asserts.

Signed-off-by: kar-rahul-aws <karahulx@amazon.com>
---
 .github/lexicon.txt               |   1 +
 event_groups.c                    |  20 --
 include/event_groups.h            |  20 ++
 include/queue.h                   |   1 +
 portable/Common/mpu_wrappers_v2.c | 433 ++++++++++++++++++------------
 queue.c                           |   6 +
 tasks.c                           |   2 +
 7 files changed, 290 insertions(+), 193 deletions(-)

diff --git a/.github/lexicon.txt b/.github/lexicon.txt
index 76443884e..2d430498f 100644
--- a/.github/lexicon.txt
+++ b/.github/lexicon.txt
@@ -2462,6 +2462,7 @@ uxpriority
 uxprioritytouse
 uxqueue
 uxqueuegetqueueitemsize
+uxqueuegetqueuelength
 uxqueuelength
 uxqueuemessageswaiting
 uxqueuespacesavailable
diff --git a/event_groups.c b/event_groups.c
index ea4c79f4b..24d818711 100644
--- a/event_groups.c
+++ b/event_groups.c
@@ -46,26 +46,6 @@
  * correct privileged Vs unprivileged linkage and placement. */
 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021 See comment above. */
 
-/* The following bit fields convey control information in a task's event list
- * item value.  It is important they don't clash with the
- * taskEVENT_LIST_ITEM_VALUE_IN_USE definition. */
-#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    #define eventCLEAR_EVENTS_ON_EXIT_BIT    0x0100U
-    #define eventUNBLOCKED_DUE_TO_BIT_SET    0x0200U
-    #define eventWAIT_FOR_ALL_BITS           0x0400U
-    #define eventEVENT_BITS_CONTROL_BYTES    0xff00U
-#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    #define eventCLEAR_EVENTS_ON_EXIT_BIT    0x01000000UL
-    #define eventUNBLOCKED_DUE_TO_BIT_SET    0x02000000UL
-    #define eventWAIT_FOR_ALL_BITS           0x04000000UL
-    #define eventEVENT_BITS_CONTROL_BYTES    0xff000000UL
-#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_64_BITS )
-    #define eventCLEAR_EVENTS_ON_EXIT_BIT    0x0100000000000000ULL
-    #define eventUNBLOCKED_DUE_TO_BIT_SET    0x0200000000000000ULL
-    #define eventWAIT_FOR_ALL_BITS           0x0400000000000000ULL
-    #define eventEVENT_BITS_CONTROL_BYTES    0xff00000000000000ULL
-#endif /* if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) */
-
 typedef struct EventGroupDef_t
 {
     EventBits_t uxEventBits;
diff --git a/include/event_groups.h b/include/event_groups.h
index 47572ce94..1322eae39 100644
--- a/include/event_groups.h
+++ b/include/event_groups.h
@@ -36,6 +36,26 @@
 /* FreeRTOS includes. */
 #include "timers.h"
 
+/* The following bit fields convey control information in a task's event list
+ * item value.  It is important they don't clash with the
+ * taskEVENT_LIST_ITEM_VALUE_IN_USE definition. */
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    #define eventCLEAR_EVENTS_ON_EXIT_BIT    0x0100U
+    #define eventUNBLOCKED_DUE_TO_BIT_SET    0x0200U
+    #define eventWAIT_FOR_ALL_BITS           0x0400U
+    #define eventEVENT_BITS_CONTROL_BYTES    0xff00U
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+    #define eventCLEAR_EVENTS_ON_EXIT_BIT    0x01000000UL
+    #define eventUNBLOCKED_DUE_TO_BIT_SET    0x02000000UL
+    #define eventWAIT_FOR_ALL_BITS           0x04000000UL
+    #define eventEVENT_BITS_CONTROL_BYTES    0xff000000UL
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_64_BITS )
+    #define eventCLEAR_EVENTS_ON_EXIT_BIT    0x0100000000000000ULL
+    #define eventUNBLOCKED_DUE_TO_BIT_SET    0x0200000000000000ULL
+    #define eventWAIT_FOR_ALL_BITS           0x0400000000000000ULL
+    #define eventEVENT_BITS_CONTROL_BYTES    0xff00000000000000ULL
+#endif /* if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) */
+
 /* *INDENT-OFF* */
 #ifdef __cplusplus
     extern "C" {
diff --git a/include/queue.h b/include/queue.h
index 1c1b9822a..db176e552 100644
--- a/include/queue.h
+++ b/include/queue.h
@@ -1753,6 +1753,7 @@ void vQueueSetQueueNumber( QueueHandle_t xQueue,
 UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
 uint8_t ucQueueGetQueueType( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
 UBaseType_t uxQueueGetQueueItemSize( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+UBaseType_t uxQueueGetQueueLength( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/Common/mpu_wrappers_v2.c b/portable/Common/mpu_wrappers_v2.c
index a9c317055..3f71af8a6 100644
--- a/portable/Common/mpu_wrappers_v2.c
+++ b/portable/Common/mpu_wrappers_v2.c
@@ -366,13 +366,16 @@
             BaseType_t xReturn = pdFAIL;
             BaseType_t xIsPreviousWakeTimeAccessible = pdFALSE;
 
-            xIsPreviousWakeTimeAccessible = xPortIsAuthorizedToAccessBuffer( pxPreviousWakeTime,
-                                                                             sizeof( TickType_t ),
-                                                                             ( tskMPU_WRITE_PERMISSION | tskMPU_READ_PERMISSION ) );
-
-            if( xIsPreviousWakeTimeAccessible == pdTRUE )
+            if( ( pxPreviousWakeTime != NULL ) && ( xTimeIncrement > 0U ) )
             {
-                xReturn = xTaskDelayUntil( pxPreviousWakeTime, xTimeIncrement );
+                xIsPreviousWakeTimeAccessible = xPortIsAuthorizedToAccessBuffer( pxPreviousWakeTime,
+                                                                                 sizeof( TickType_t ),
+                                                                                 ( tskMPU_WRITE_PERMISSION | tskMPU_READ_PERMISSION ) );
+
+                if( xIsPreviousWakeTimeAccessible == pdTRUE )
+                {
+                    xReturn = xTaskDelayUntil( pxPreviousWakeTime, xTimeIncrement );
+                }
             }
 
             return xReturn;
@@ -391,22 +394,15 @@
             TaskHandle_t xInternalTaskHandle = NULL;
             int32_t lIndex;
 
-            if( xTask == NULL )
-            {
-                xReturn = xTaskAbortDelay( xTask );
-            }
-            else
-            {
-                lIndex = ( int32_t ) xTask;
+            lIndex = ( int32_t ) xTask;
 
-                if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+            if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+            {
+                xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                if( xInternalTaskHandle != NULL )
                 {
-                    xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
-
-                    if( xInternalTaskHandle != NULL )
-                    {
-                        xReturn = xTaskAbortDelay( xInternalTaskHandle );
-                    }
+                    xReturn = xTaskAbortDelay( xInternalTaskHandle );
                 }
             }
 
@@ -473,22 +469,15 @@
             TaskHandle_t xInternalTaskHandle = NULL;
             int32_t lIndex;
 
-            if( pxTask == NULL )
-            {
-                eReturn = eTaskGetState( pxTask );
-            }
-            else
-            {
-                lIndex = ( int32_t ) pxTask;
+            lIndex = ( int32_t ) pxTask;
 
-                if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+            if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+            {
+                xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                if( xInternalTaskHandle != NULL )
                 {
-                    xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
-
-                    if( xInternalTaskHandle != NULL )
-                    {
-                        eReturn = eTaskGetState( xInternalTaskHandle );
-                    }
+                    eReturn = eTaskGetState( xInternalTaskHandle );
                 }
             }
 
@@ -577,7 +566,11 @@
             {
                 /* After the scheduler starts, only privileged tasks are allowed
                  * to suspend other tasks. */
-                if( ( xTaskGetSchedulerState() == taskSCHEDULER_NOT_STARTED ) || ( portIS_TASK_PRIVILEGED() == pdTRUE ) )
+                #if ( INCLUDE_xTaskGetSchedulerState == 1 )
+                    if( ( xTaskGetSchedulerState() == taskSCHEDULER_NOT_STARTED ) || ( portIS_TASK_PRIVILEGED() == pdTRUE ) )
+                #else
+                    if( portIS_TASK_PRIVILEGED() == pdTRUE )
+                #endif
                 {
                     lIndex = ( int32_t ) pxTaskToSuspend;
 
@@ -1047,13 +1040,16 @@
     {
         BaseType_t xIsTimeOutWriteable = pdFALSE;
 
-        xIsTimeOutWriteable = xPortIsAuthorizedToAccessBuffer( pxTimeOut,
-                                                               sizeof( TimeOut_t ),
-                                                               tskMPU_WRITE_PERMISSION );
-
-        if( xIsTimeOutWriteable == pdTRUE )
+        if( pxTimeOut != NULL )
         {
-            vTaskSetTimeOutState( pxTimeOut );
+            xIsTimeOutWriteable = xPortIsAuthorizedToAccessBuffer( pxTimeOut,
+                                                                   sizeof( TimeOut_t ),
+                                                                   tskMPU_WRITE_PERMISSION );
+
+            if( xIsTimeOutWriteable == pdTRUE )
+            {
+                vTaskSetTimeOutState( pxTimeOut );
+            }
         }
     }
 /*-----------------------------------------------------------*/
@@ -1068,16 +1064,19 @@
         BaseType_t xIsTimeOutWriteable = pdFALSE;
         BaseType_t xIsTicksToWaitWriteable = pdFALSE;
 
-        xIsTimeOutWriteable = xPortIsAuthorizedToAccessBuffer( pxTimeOut,
-                                                               sizeof( TimeOut_t ),
-                                                               tskMPU_WRITE_PERMISSION );
-        xIsTicksToWaitWriteable = xPortIsAuthorizedToAccessBuffer( pxTicksToWait,
-                                                                   sizeof( TickType_t ),
-                                                                   tskMPU_WRITE_PERMISSION );
-
-        if( ( xIsTimeOutWriteable == pdTRUE ) && ( xIsTicksToWaitWriteable == pdTRUE ) )
+        if( ( pxTimeOut != NULL ) && ( pxTicksToWait != NULL ) )
         {
-            xReturn = xTaskCheckForTimeOut( pxTimeOut, pxTicksToWait );
+            xIsTimeOutWriteable = xPortIsAuthorizedToAccessBuffer( pxTimeOut,
+                                                                   sizeof( TimeOut_t ),
+                                                                   tskMPU_WRITE_PERMISSION );
+            xIsTicksToWaitWriteable = xPortIsAuthorizedToAccessBuffer( pxTicksToWait,
+                                                                       sizeof( TickType_t ),
+                                                                       tskMPU_WRITE_PERMISSION );
+
+            if( ( xIsTimeOutWriteable == pdTRUE ) && ( xIsTicksToWaitWriteable == pdTRUE ) )
+            {
+                xReturn = xTaskCheckForTimeOut( pxTimeOut, pxTicksToWait );
+            }
         }
 
         return xReturn;
@@ -1103,24 +1102,27 @@
             TaskHandle_t xInternalTaskHandle = NULL;
             BaseType_t xIsPreviousNotificationValueWriteable = pdFALSE;
 
-            if( pulPreviousNotificationValue != NULL )
+            if( uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES )
             {
-                xIsPreviousNotificationValueWriteable = xPortIsAuthorizedToAccessBuffer( pulPreviousNotificationValue,
-                                                                                         sizeof( uint32_t ),
-                                                                                         tskMPU_WRITE_PERMISSION );
-            }
-
-            if( ( pulPreviousNotificationValue == NULL ) || ( xIsPreviousNotificationValueWriteable == pdTRUE ) )
-            {
-                lIndex = ( int32_t ) xTaskToNotify;
-
-                if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+                if( pulPreviousNotificationValue != NULL )
                 {
-                    xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                    xIsPreviousNotificationValueWriteable = xPortIsAuthorizedToAccessBuffer( pulPreviousNotificationValue,
+                                                                                             sizeof( uint32_t ),
+                                                                                             tskMPU_WRITE_PERMISSION );
+                }
 
-                    if( xInternalTaskHandle != NULL )
+                if( ( pulPreviousNotificationValue == NULL ) || ( xIsPreviousNotificationValueWriteable == pdTRUE ) )
+                {
+                    lIndex = ( int32_t ) xTaskToNotify;
+
+                    if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
                     {
-                        xReturn = xTaskGenericNotify( xInternalTaskHandle, uxIndexToNotify, ulValue, eAction, pulPreviousNotificationValue );
+                        xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                        if( xInternalTaskHandle != NULL )
+                        {
+                            xReturn = xTaskGenericNotify( xInternalTaskHandle, uxIndexToNotify, ulValue, eAction, pulPreviousNotificationValue );
+                        }
                     }
                 }
             }
@@ -1148,16 +1150,19 @@
             BaseType_t xReturn = pdFAIL;
             BaseType_t xIsNotificationValueWritable = pdFALSE;
 
-            if( pulNotificationValue != NULL )
+            if( uxIndexToWaitOn < configTASK_NOTIFICATION_ARRAY_ENTRIES )
             {
-                xIsNotificationValueWritable = xPortIsAuthorizedToAccessBuffer( pulNotificationValue,
-                                                                                sizeof( uint32_t ),
-                                                                                tskMPU_WRITE_PERMISSION );
-            }
+                if( pulNotificationValue != NULL )
+                {
+                    xIsNotificationValueWritable = xPortIsAuthorizedToAccessBuffer( pulNotificationValue,
+                                                                                    sizeof( uint32_t ),
+                                                                                    tskMPU_WRITE_PERMISSION );
+                }
 
-            if( ( pulNotificationValue == NULL ) || ( xIsNotificationValueWritable == pdTRUE ) )
-            {
-                xReturn = xTaskGenericNotifyWait( uxIndexToWaitOn, ulBitsToClearOnEntry, ulBitsToClearOnExit, pulNotificationValue, xTicksToWait );
+                if( ( pulNotificationValue == NULL ) || ( xIsNotificationValueWritable == pdTRUE ) )
+                {
+                    xReturn = xTaskGenericNotifyWait( uxIndexToWaitOn, ulBitsToClearOnEntry, ulBitsToClearOnExit, pulNotificationValue, xTicksToWait );
+                }
             }
 
             return xReturn;
@@ -1176,9 +1181,12 @@
                                                   BaseType_t xClearCountOnExit,
                                                   TickType_t xTicksToWait ) /* PRIVILEGED_FUNCTION */
         {
-            uint32_t ulReturn;
+            uint32_t ulReturn = 0;
 
-            ulReturn = ulTaskGenericNotifyTake( uxIndexToWaitOn, xClearCountOnExit, xTicksToWait );
+            if( uxIndexToWaitOn < configTASK_NOTIFICATION_ARRAY_ENTRIES )
+            {
+                ulReturn = ulTaskGenericNotifyTake( uxIndexToWaitOn, xClearCountOnExit, xTicksToWait );
+            }
 
             return ulReturn;
         }
@@ -1198,21 +1206,24 @@
             int32_t lIndex;
             TaskHandle_t xInternalTaskHandle = NULL;
 
-            if( xTask == NULL )
+            if( uxIndexToClear < configTASK_NOTIFICATION_ARRAY_ENTRIES )
             {
-                xReturn = xTaskGenericNotifyStateClear( xTask, uxIndexToClear );
-            }
-            else
-            {
-                lIndex = ( int32_t ) xTask;
-
-                if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+                if( xTask == NULL )
                 {
-                    xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                    xReturn = xTaskGenericNotifyStateClear( xTask, uxIndexToClear );
+                }
+                else
+                {
+                    lIndex = ( int32_t ) xTask;
 
-                    if( xInternalTaskHandle != NULL )
+                    if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
                     {
-                        xReturn = xTaskGenericNotifyStateClear( xInternalTaskHandle, uxIndexToClear );
+                        xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                        if( xInternalTaskHandle != NULL )
+                        {
+                            xReturn = xTaskGenericNotifyStateClear( xInternalTaskHandle, uxIndexToClear );
+                        }
                     }
                 }
             }
@@ -1237,21 +1248,24 @@
             int32_t lIndex;
             TaskHandle_t xInternalTaskHandle = NULL;
 
-            if( xTask == NULL )
+            if( uxIndexToClear < configTASK_NOTIFICATION_ARRAY_ENTRIES )
             {
-                ulReturn = ulTaskGenericNotifyValueClear( xTask, uxIndexToClear, ulBitsToClear );
-            }
-            else
-            {
-                lIndex = ( int32_t ) xTask;
-
-                if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+                if( xTask == NULL )
                 {
-                    xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                    ulReturn = ulTaskGenericNotifyValueClear( xTask, uxIndexToClear, ulBitsToClear );
+                }
+                else
+                {
+                    lIndex = ( int32_t ) xTask;
 
-                    if( xInternalTaskHandle != NULL )
+                    if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
                     {
-                        ulReturn = ulTaskGenericNotifyValueClear( xInternalTaskHandle, uxIndexToClear, ulBitsToClear );
+                        xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                        if( xInternalTaskHandle != NULL )
+                        {
+                            ulReturn = ulTaskGenericNotifyValueClear( xInternalTaskHandle, uxIndexToClear, ulBitsToClear );
+                        }
                     }
                 }
             }
@@ -1809,6 +1823,7 @@
         QueueHandle_t xInternalQueueHandle = NULL;
         BaseType_t xReturn = pdFAIL;
         BaseType_t xIsItemToQueueReadable = pdFALSE;
+        UBaseType_t uxQueueItemSize, uxQueueLength;
 
         lIndex = ( int32_t ) xQueue;
 
@@ -1818,16 +1833,27 @@
 
             if( xInternalQueueHandle != NULL )
             {
-                if( pvItemToQueue != NULL )
-                {
-                    xIsItemToQueueReadable = xPortIsAuthorizedToAccessBuffer( pvItemToQueue,
-                                                                              uxQueueGetQueueItemSize( xInternalQueueHandle ),
-                                                                              tskMPU_READ_PERMISSION );
-                }
+                uxQueueItemSize = uxQueueGetQueueItemSize( xInternalQueueHandle );
+                uxQueueLength = uxQueueGetQueueLength( xInternalQueueHandle );
 
-                if( ( pvItemToQueue == NULL ) || ( xIsItemToQueueReadable == pdTRUE ) )
+                if( ( !( ( pvItemToQueue == NULL ) && ( uxQueueItemSize != ( UBaseType_t ) 0U ) ) ) &&
+                    ( !( ( xCopyPosition == queueOVERWRITE ) && ( uxQueueLength != ( UBaseType_t ) 1U ) ) )
+                    #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+                        && ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) )
+                    #endif
+                    )
                 {
-                    xReturn = xQueueGenericSend( xInternalQueueHandle, pvItemToQueue, xTicksToWait, xCopyPosition );
+                    if( pvItemToQueue != NULL )
+                    {
+                        xIsItemToQueueReadable = xPortIsAuthorizedToAccessBuffer( pvItemToQueue,
+                                                                                  uxQueueGetQueueItemSize( xInternalQueueHandle ),
+                                                                                  tskMPU_READ_PERMISSION );
+                    }
+
+                    if( ( pvItemToQueue == NULL ) || ( xIsItemToQueueReadable == pdTRUE ) )
+                    {
+                        xReturn = xQueueGenericSend( xInternalQueueHandle, pvItemToQueue, xTicksToWait, xCopyPosition );
+                    }
                 }
             }
         }
@@ -1896,6 +1922,7 @@
         QueueHandle_t xInternalQueueHandle = NULL;
         BaseType_t xReturn = pdFAIL;
         BaseType_t xIsReceiveBufferWritable = pdFALSE;
+        UBaseType_t uxQueueItemSize;
 
         lIndex = ( int32_t ) pxQueue;
 
@@ -1905,13 +1932,22 @@
 
             if( xInternalQueueHandle != NULL )
             {
-                xIsReceiveBufferWritable = xPortIsAuthorizedToAccessBuffer( pvBuffer,
-                                                                            uxQueueGetQueueItemSize( xInternalQueueHandle ),
-                                                                            tskMPU_WRITE_PERMISSION );
+                uxQueueItemSize = uxQueueGetQueueItemSize( xInternalQueueHandle );
 
-                if( xIsReceiveBufferWritable == pdTRUE )
+                if( ( !( ( ( pvBuffer ) == NULL ) && ( uxQueueItemSize != ( UBaseType_t ) 0U ) ) )
+                    #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+                        && ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) )
+                    #endif
+                    )
                 {
-                    xReturn = xQueueReceive( xInternalQueueHandle, pvBuffer, xTicksToWait );
+                    xIsReceiveBufferWritable = xPortIsAuthorizedToAccessBuffer( pvBuffer,
+                                                                                uxQueueGetQueueItemSize( xInternalQueueHandle ),
+                                                                                tskMPU_WRITE_PERMISSION );
+
+                    if( xIsReceiveBufferWritable == pdTRUE )
+                    {
+                        xReturn = xQueueReceive( xInternalQueueHandle, pvBuffer, xTicksToWait );
+                    }
                 }
             }
         }
@@ -1932,6 +1968,7 @@
         QueueHandle_t xInternalQueueHandle = NULL;
         BaseType_t xReturn = pdFAIL;
         BaseType_t xIsReceiveBufferWritable = pdFALSE;
+        UBaseType_t uxQueueItemSize;
 
         lIndex = ( int32_t ) xQueue;
 
@@ -1941,13 +1978,22 @@
 
             if( xInternalQueueHandle != NULL )
             {
-                xIsReceiveBufferWritable = xPortIsAuthorizedToAccessBuffer( pvBuffer,
-                                                                            uxQueueGetQueueItemSize( xInternalQueueHandle ),
-                                                                            tskMPU_WRITE_PERMISSION );
+                uxQueueItemSize = uxQueueGetQueueItemSize( xInternalQueueHandle );
 
-                if( xIsReceiveBufferWritable == pdTRUE )
+                if( ( !( ( ( pvBuffer ) == NULL ) && ( uxQueueItemSize != ( UBaseType_t ) 0U ) ) )
+                    #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+                        && ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) )
+                    #endif
+                    )
                 {
-                    xReturn = xQueuePeek( xInternalQueueHandle, pvBuffer, xTicksToWait );
+                    xIsReceiveBufferWritable = xPortIsAuthorizedToAccessBuffer( pvBuffer,
+                                                                                uxQueueGetQueueItemSize( xInternalQueueHandle ),
+                                                                                tskMPU_WRITE_PERMISSION );
+
+                    if( xIsReceiveBufferWritable == pdTRUE )
+                    {
+                        xReturn = xQueuePeek( xInternalQueueHandle, pvBuffer, xTicksToWait );
+                    }
                 }
             }
         }
@@ -1965,6 +2011,7 @@
         int32_t lIndex;
         QueueHandle_t xInternalQueueHandle = NULL;
         BaseType_t xReturn = pdFAIL;
+        UBaseType_t uxQueueItemSize;
 
         lIndex = ( int32_t ) xQueue;
 
@@ -1974,7 +2021,16 @@
 
             if( xInternalQueueHandle != NULL )
             {
-                xReturn = xQueueSemaphoreTake( xInternalQueueHandle, xTicksToWait );
+                uxQueueItemSize = uxQueueGetQueueItemSize( xInternalQueueHandle );
+
+                if( ( uxQueueItemSize == 0 )
+                    #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+                        && ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) )
+                    #endif
+                    )
+                {
+                    xReturn = xQueueSemaphoreTake( xInternalQueueHandle, xTicksToWait );
+                }
             }
         }
 
@@ -2932,24 +2988,27 @@
             int32_t lIndex;
             BaseType_t xIsHigherPriorityTaskWokenWriteable = pdFALSE;
 
-            if( pxHigherPriorityTaskWoken != NULL )
+            if( xCommandID < tmrFIRST_FROM_ISR_COMMAND )
             {
-                xIsHigherPriorityTaskWokenWriteable = xPortIsAuthorizedToAccessBuffer( pxHigherPriorityTaskWoken,
-                                                                                       sizeof( BaseType_t ),
-                                                                                       tskMPU_WRITE_PERMISSION );
-            }
-
-            if( ( pxHigherPriorityTaskWoken == NULL ) || ( xIsHigherPriorityTaskWokenWriteable == pdTRUE ) )
-            {
-                lIndex = ( int32_t ) xTimer;
-
-                if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+                if( pxHigherPriorityTaskWoken != NULL )
                 {
-                    xInternalTimerHandle = MPU_GetTimerHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                    xIsHigherPriorityTaskWokenWriteable = xPortIsAuthorizedToAccessBuffer( pxHigherPriorityTaskWoken,
+                                                                                           sizeof( BaseType_t ),
+                                                                                           tskMPU_WRITE_PERMISSION );
+                }
 
-                    if( xInternalTimerHandle != NULL )
+                if( ( pxHigherPriorityTaskWoken == NULL ) || ( xIsHigherPriorityTaskWokenWriteable == pdTRUE ) )
+                {
+                    lIndex = ( int32_t ) xTimer;
+
+                    if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
                     {
-                        xReturn = xTimerGenericCommandFromTask( xInternalTimerHandle, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait );
+                        xInternalTimerHandle = MPU_GetTimerHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                        if( xInternalTimerHandle != NULL )
+                        {
+                            xReturn = xTimerGenericCommandFromTask( xInternalTimerHandle, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait );
+                        }
                     }
                 }
             }
@@ -3291,15 +3350,23 @@
         EventGroupHandle_t xInternalEventGroupHandle = NULL;
         int32_t lIndex;
 
-        lIndex = ( int32_t ) xEventGroup;
-
-        if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+        if( ( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 ) &&
+            ( uxBitsToWaitFor != 0 )
+            #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+                && ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) )
+            #endif
+            )
         {
-            xInternalEventGroupHandle = MPU_GetEventGroupHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+            lIndex = ( int32_t ) xEventGroup;
 
-            if( xInternalEventGroupHandle != NULL )
+            if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
             {
-                xReturn = xEventGroupWaitBits( xInternalEventGroupHandle, uxBitsToWaitFor, xClearOnExit, xWaitForAllBits, xTicksToWait );
+                xInternalEventGroupHandle = MPU_GetEventGroupHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                if( xInternalEventGroupHandle != NULL )
+                {
+                    xReturn = xEventGroupWaitBits( xInternalEventGroupHandle, uxBitsToWaitFor, xClearOnExit, xWaitForAllBits, xTicksToWait );
+                }
             }
         }
 
@@ -3317,15 +3384,18 @@
         EventGroupHandle_t xInternalEventGroupHandle = NULL;
         int32_t lIndex;
 
-        lIndex = ( int32_t ) xEventGroup;
-
-        if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+        if( ( uxBitsToClear & eventEVENT_BITS_CONTROL_BYTES ) == 0 )
         {
-            xInternalEventGroupHandle = MPU_GetEventGroupHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+            lIndex = ( int32_t ) xEventGroup;
 
-            if( xInternalEventGroupHandle != NULL )
+            if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
             {
-                xReturn = xEventGroupClearBits( xInternalEventGroupHandle, uxBitsToClear );
+                xInternalEventGroupHandle = MPU_GetEventGroupHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                if( xInternalEventGroupHandle != NULL )
+                {
+                    xReturn = xEventGroupClearBits( xInternalEventGroupHandle, uxBitsToClear );
+                }
             }
         }
 
@@ -3343,15 +3413,18 @@
         EventGroupHandle_t xInternalEventGroupHandle = NULL;
         int32_t lIndex;
 
-        lIndex = ( int32_t ) xEventGroup;
-
-        if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+        if( ( uxBitsToSet & eventEVENT_BITS_CONTROL_BYTES ) == 0 )
         {
-            xInternalEventGroupHandle = MPU_GetEventGroupHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+            lIndex = ( int32_t ) xEventGroup;
 
-            if( xInternalEventGroupHandle != NULL )
+            if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
             {
-                xReturn = xEventGroupSetBits( xInternalEventGroupHandle, uxBitsToSet );
+                xInternalEventGroupHandle = MPU_GetEventGroupHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                if( xInternalEventGroupHandle != NULL )
+                {
+                    xReturn = xEventGroupSetBits( xInternalEventGroupHandle, uxBitsToSet );
+                }
             }
         }
 
@@ -3373,15 +3446,23 @@
         EventGroupHandle_t xInternalEventGroupHandle = NULL;
         int32_t lIndex;
 
-        lIndex = ( int32_t ) xEventGroup;
-
-        if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+        if( ( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 ) &&
+            ( uxBitsToWaitFor != 0 )
+            #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+                && ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) )
+            #endif
+            )
         {
-            xInternalEventGroupHandle = MPU_GetEventGroupHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+            lIndex = ( int32_t ) xEventGroup;
 
-            if( xInternalEventGroupHandle != NULL )
+            if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
             {
-                xReturn = xEventGroupSync( xInternalEventGroupHandle, uxBitsToSet, uxBitsToWaitFor, xTicksToWait );
+                xInternalEventGroupHandle = MPU_GetEventGroupHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                if( xInternalEventGroupHandle != NULL )
+                {
+                    xReturn = xEventGroupSync( xInternalEventGroupHandle, uxBitsToSet, uxBitsToWaitFor, xTicksToWait );
+                }
             }
         }
 
@@ -3654,21 +3735,24 @@
         int32_t lIndex;
         BaseType_t xIsTxDataBufferReadable = pdFALSE;
 
-        xIsTxDataBufferReadable = xPortIsAuthorizedToAccessBuffer( pvTxData,
-                                                                   xDataLengthBytes,
-                                                                   tskMPU_READ_PERMISSION );
-
-        if( xIsTxDataBufferReadable == pdTRUE )
+        if( pvTxData != NULL )
         {
-            lIndex = ( int32_t ) xStreamBuffer;
+            xIsTxDataBufferReadable = xPortIsAuthorizedToAccessBuffer( pvTxData,
+                                                                       xDataLengthBytes,
+                                                                       tskMPU_READ_PERMISSION );
 
-            if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+            if( xIsTxDataBufferReadable == pdTRUE )
             {
-                xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                lIndex = ( int32_t ) xStreamBuffer;
 
-                if( xInternalStreamBufferHandle != NULL )
+                if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
                 {
-                    xReturn = xStreamBufferSend( xInternalStreamBufferHandle, pvTxData, xDataLengthBytes, xTicksToWait );
+                    xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                    if( xInternalStreamBufferHandle != NULL )
+                    {
+                        xReturn = xStreamBufferSend( xInternalStreamBufferHandle, pvTxData, xDataLengthBytes, xTicksToWait );
+                    }
                 }
             }
         }
@@ -3692,21 +3776,24 @@
         int32_t lIndex;
         BaseType_t xIsRxDataBufferWriteable = pdFALSE;
 
-        xIsRxDataBufferWriteable = xPortIsAuthorizedToAccessBuffer( pvRxData,
-                                                                    xBufferLengthBytes,
-                                                                    tskMPU_WRITE_PERMISSION );
-
-        if( xIsRxDataBufferWriteable == pdTRUE )
+        if( pvRxData != NULL )
         {
-            lIndex = ( int32_t ) xStreamBuffer;
+            xIsRxDataBufferWriteable = xPortIsAuthorizedToAccessBuffer( pvRxData,
+                                                                        xBufferLengthBytes,
+                                                                        tskMPU_WRITE_PERMISSION );
 
-            if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+            if( xIsRxDataBufferWriteable == pdTRUE )
             {
-                xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                lIndex = ( int32_t ) xStreamBuffer;
 
-                if( xInternalStreamBufferHandle != NULL )
+                if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
                 {
-                    xReturn = xStreamBufferReceive( xInternalStreamBufferHandle, pvRxData, xBufferLengthBytes, xTicksToWait );
+                    xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                    if( xInternalStreamBufferHandle != NULL )
+                    {
+                        xReturn = xStreamBufferReceive( xInternalStreamBufferHandle, pvRxData, xBufferLengthBytes, xTicksToWait );
+                    }
                 }
             }
         }
diff --git a/queue.c b/queue.c
index 76006d05d..9d300f861 100755
--- a/queue.c
+++ b/queue.c
@@ -2236,6 +2236,12 @@ UBaseType_t uxQueueGetQueueItemSize( QueueHandle_t xQueue ) /* PRIVILEGED_FUNCTI
 }
 /*-----------------------------------------------------------*/
 
+UBaseType_t uxQueueGetQueueLength( QueueHandle_t xQueue ) /* PRIVILEGED_FUNCTION */
+{
+    return ( ( Queue_t * ) xQueue )->uxLength;
+}
+/*-----------------------------------------------------------*/
+
 #if ( configUSE_MUTEXES == 1 )
 
     static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue )
diff --git a/tasks.c b/tasks.c
index 3a278424e..0f865ef4a 100644
--- a/tasks.c
+++ b/tasks.c
@@ -7408,6 +7408,8 @@ TickType_t uxTaskResetEventItemValue( void )
         TCB_t * pxTCB;
         uint32_t ulReturn;
 
+        configASSERT( uxIndexToClear < configTASK_NOTIFICATION_ARRAY_ENTRIES );
+
         /* If null is passed in here then it is the calling task that is having
          * its notification state cleared. */
         pxTCB = prvGetTCBFromHandle( xTask );

From 7372519cba39922ce5aeb92b8931cf8694b78bd2 Mon Sep 17 00:00:00 2001
From: Moral-Hao <sihunzhilei@126.com>
Date: Sat, 19 Aug 2023 00:05:10 +0800
Subject: [PATCH 040/424] Use the bigger priority whenever possible. (#760)

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
---
 tasks.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/tasks.c b/tasks.c
index 0f865ef4a..2786c5ab0 100644
--- a/tasks.c
+++ b/tasks.c
@@ -2462,8 +2462,9 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
                 #if ( configUSE_MUTEXES == 1 )
                 {
                     /* Only change the priority being used if the task is not
-                     * currently using an inherited priority. */
-                    if( pxTCB->uxBasePriority == pxTCB->uxPriority )
+                     * currently using an inherited priority or the new priority
+                     * is bigger than the inherited priority. */
+                    if( ( pxTCB->uxBasePriority == pxTCB->uxPriority ) || ( uxNewPriority > pxTCB->uxPriority ) )
                     {
                         pxTCB->uxPriority = uxNewPriority;
                     }

From b9f488a7133c6dadf236a44ec318eb2d2ab0573b Mon Sep 17 00:00:00 2001
From: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Date: Mon, 21 Aug 2023 14:48:22 +0530
Subject: [PATCH 041/424] Fix remarks emitted by IAR compiler (#763)

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 portable/ARMv8M/non_secure/port.c            |  2 +-
 portable/GCC/ARM_CM23/non_secure/port.c      |  2 +-
 portable/GCC/ARM_CM23_NTZ/non_secure/port.c  |  2 +-
 portable/GCC/ARM_CM33/non_secure/port.c      |  2 +-
 portable/GCC/ARM_CM33_NTZ/non_secure/port.c  |  2 +-
 portable/GCC/ARM_CM35P/non_secure/port.c     |  2 +-
 portable/GCC/ARM_CM35P_NTZ/non_secure/port.c |  2 +-
 portable/GCC/ARM_CM4_MPU/portmacro.h         |  5 +++++
 portable/GCC/ARM_CM55/non_secure/port.c      |  2 +-
 portable/GCC/ARM_CM55_NTZ/non_secure/port.c  |  2 +-
 portable/GCC/ARM_CM85/non_secure/port.c      |  2 +-
 portable/GCC/ARM_CM85_NTZ/non_secure/port.c  |  2 +-
 portable/IAR/ARM_CM23/non_secure/port.c      |  2 +-
 portable/IAR/ARM_CM23_NTZ/non_secure/port.c  |  2 +-
 portable/IAR/ARM_CM3/port.c                  |  2 +-
 portable/IAR/ARM_CM33/non_secure/port.c      |  2 +-
 portable/IAR/ARM_CM33_NTZ/non_secure/port.c  |  2 +-
 portable/IAR/ARM_CM35P/non_secure/port.c     |  2 +-
 portable/IAR/ARM_CM35P_NTZ/non_secure/port.c |  2 +-
 portable/IAR/ARM_CM4F/port.c                 |  2 +-
 portable/IAR/ARM_CM4F_MPU/port.c             |  2 +-
 portable/IAR/ARM_CM4F_MPU/portasm.s          |  6 ++++++
 portable/IAR/ARM_CM4F_MPU/portmacro.h        |  5 +++++
 portable/IAR/ARM_CM55/non_secure/port.c      |  2 +-
 portable/IAR/ARM_CM55_NTZ/non_secure/port.c  |  2 +-
 portable/IAR/ARM_CM7/r0p1/port.c             |  2 +-
 portable/IAR/ARM_CM85/non_secure/port.c      |  2 +-
 portable/IAR/ARM_CM85_NTZ/non_secure/port.c  |  2 +-
 portable/RVDS/ARM_CM4_MPU/portmacro.h        |  5 +++++
 timers.c                                     | 16 ++++++++--------
 30 files changed, 54 insertions(+), 33 deletions(-)

diff --git a/portable/ARMv8M/non_secure/port.c b/portable/ARMv8M/non_secure/port.c
index e027b21e1..80410e82e 100644
--- a/portable/ARMv8M/non_secure/port.c
+++ b/portable/ARMv8M/non_secure/port.c
@@ -1655,7 +1655,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         /* Check that the bits not implemented in hardware are zero in
          * configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
+        configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U );
 
         /* Calculate the maximum acceptable priority group value for the number
          * of bits read back. */
diff --git a/portable/GCC/ARM_CM23/non_secure/port.c b/portable/GCC/ARM_CM23/non_secure/port.c
index e027b21e1..80410e82e 100644
--- a/portable/GCC/ARM_CM23/non_secure/port.c
+++ b/portable/GCC/ARM_CM23/non_secure/port.c
@@ -1655,7 +1655,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         /* Check that the bits not implemented in hardware are zero in
          * configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
+        configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U );
 
         /* Calculate the maximum acceptable priority group value for the number
          * of bits read back. */
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
index e027b21e1..80410e82e 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
@@ -1655,7 +1655,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         /* Check that the bits not implemented in hardware are zero in
          * configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
+        configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U );
 
         /* Calculate the maximum acceptable priority group value for the number
          * of bits read back. */
diff --git a/portable/GCC/ARM_CM33/non_secure/port.c b/portable/GCC/ARM_CM33/non_secure/port.c
index e027b21e1..80410e82e 100644
--- a/portable/GCC/ARM_CM33/non_secure/port.c
+++ b/portable/GCC/ARM_CM33/non_secure/port.c
@@ -1655,7 +1655,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         /* Check that the bits not implemented in hardware are zero in
          * configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
+        configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U );
 
         /* Calculate the maximum acceptable priority group value for the number
          * of bits read back. */
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
index e027b21e1..80410e82e 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
@@ -1655,7 +1655,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         /* Check that the bits not implemented in hardware are zero in
          * configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
+        configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U );
 
         /* Calculate the maximum acceptable priority group value for the number
          * of bits read back. */
diff --git a/portable/GCC/ARM_CM35P/non_secure/port.c b/portable/GCC/ARM_CM35P/non_secure/port.c
index e027b21e1..80410e82e 100644
--- a/portable/GCC/ARM_CM35P/non_secure/port.c
+++ b/portable/GCC/ARM_CM35P/non_secure/port.c
@@ -1655,7 +1655,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         /* Check that the bits not implemented in hardware are zero in
          * configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
+        configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U );
 
         /* Calculate the maximum acceptable priority group value for the number
          * of bits read back. */
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c b/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
index e027b21e1..80410e82e 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
@@ -1655,7 +1655,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         /* Check that the bits not implemented in hardware are zero in
          * configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
+        configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U );
 
         /* Calculate the maximum acceptable priority group value for the number
          * of bits read back. */
diff --git a/portable/GCC/ARM_CM4_MPU/portmacro.h b/portable/GCC/ARM_CM4_MPU/portmacro.h
index 45eaaa7b8..9a8891b30 100644
--- a/portable/GCC/ARM_CM4_MPU/portmacro.h
+++ b/portable/GCC/ARM_CM4_MPU/portmacro.h
@@ -74,6 +74,11 @@ typedef unsigned long    UBaseType_t;
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
 
+/* Errata 837070 workaround must be enabled on Cortex-M7 r0p0
+ * and r0p1 cores. */
+#ifndef configENABLE_ERRATA_837070_WORKAROUND
+    #define configENABLE_ERRATA_837070_WORKAROUND 0
+#endif
 /*-----------------------------------------------------------*/
 
 /* MPU specific constants. */
diff --git a/portable/GCC/ARM_CM55/non_secure/port.c b/portable/GCC/ARM_CM55/non_secure/port.c
index e027b21e1..80410e82e 100644
--- a/portable/GCC/ARM_CM55/non_secure/port.c
+++ b/portable/GCC/ARM_CM55/non_secure/port.c
@@ -1655,7 +1655,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         /* Check that the bits not implemented in hardware are zero in
          * configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
+        configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U );
 
         /* Calculate the maximum acceptable priority group value for the number
          * of bits read back. */
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/port.c b/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
index e027b21e1..80410e82e 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
@@ -1655,7 +1655,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         /* Check that the bits not implemented in hardware are zero in
          * configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
+        configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U );
 
         /* Calculate the maximum acceptable priority group value for the number
          * of bits read back. */
diff --git a/portable/GCC/ARM_CM85/non_secure/port.c b/portable/GCC/ARM_CM85/non_secure/port.c
index e027b21e1..80410e82e 100644
--- a/portable/GCC/ARM_CM85/non_secure/port.c
+++ b/portable/GCC/ARM_CM85/non_secure/port.c
@@ -1655,7 +1655,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         /* Check that the bits not implemented in hardware are zero in
          * configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
+        configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U );
 
         /* Calculate the maximum acceptable priority group value for the number
          * of bits read back. */
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/port.c b/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
index e027b21e1..80410e82e 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
@@ -1655,7 +1655,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         /* Check that the bits not implemented in hardware are zero in
          * configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
+        configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U );
 
         /* Calculate the maximum acceptable priority group value for the number
          * of bits read back. */
diff --git a/portable/IAR/ARM_CM23/non_secure/port.c b/portable/IAR/ARM_CM23/non_secure/port.c
index e027b21e1..80410e82e 100644
--- a/portable/IAR/ARM_CM23/non_secure/port.c
+++ b/portable/IAR/ARM_CM23/non_secure/port.c
@@ -1655,7 +1655,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         /* Check that the bits not implemented in hardware are zero in
          * configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
+        configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U );
 
         /* Calculate the maximum acceptable priority group value for the number
          * of bits read back. */
diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
index e027b21e1..80410e82e 100644
--- a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
@@ -1655,7 +1655,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         /* Check that the bits not implemented in hardware are zero in
          * configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
+        configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U );
 
         /* Calculate the maximum acceptable priority group value for the number
          * of bits read back. */
diff --git a/portable/IAR/ARM_CM3/port.c b/portable/IAR/ARM_CM3/port.c
index 1e3a3ded0..d2298f4c1 100755
--- a/portable/IAR/ARM_CM3/port.c
+++ b/portable/IAR/ARM_CM3/port.c
@@ -243,7 +243,7 @@ BaseType_t xPortStartScheduler( void )
 
         /* Check that the bits not implemented in hardware are zero in
          * configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
+        configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U );
 
         /* Calculate the maximum acceptable priority group value for the number
          * of bits read back. */
diff --git a/portable/IAR/ARM_CM33/non_secure/port.c b/portable/IAR/ARM_CM33/non_secure/port.c
index e027b21e1..80410e82e 100644
--- a/portable/IAR/ARM_CM33/non_secure/port.c
+++ b/portable/IAR/ARM_CM33/non_secure/port.c
@@ -1655,7 +1655,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         /* Check that the bits not implemented in hardware are zero in
          * configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
+        configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U );
 
         /* Calculate the maximum acceptable priority group value for the number
          * of bits read back. */
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
index e027b21e1..80410e82e 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
@@ -1655,7 +1655,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         /* Check that the bits not implemented in hardware are zero in
          * configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
+        configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U );
 
         /* Calculate the maximum acceptable priority group value for the number
          * of bits read back. */
diff --git a/portable/IAR/ARM_CM35P/non_secure/port.c b/portable/IAR/ARM_CM35P/non_secure/port.c
index e027b21e1..80410e82e 100644
--- a/portable/IAR/ARM_CM35P/non_secure/port.c
+++ b/portable/IAR/ARM_CM35P/non_secure/port.c
@@ -1655,7 +1655,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         /* Check that the bits not implemented in hardware are zero in
          * configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
+        configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U );
 
         /* Calculate the maximum acceptable priority group value for the number
          * of bits read back. */
diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c b/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
index e027b21e1..80410e82e 100644
--- a/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
@@ -1655,7 +1655,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         /* Check that the bits not implemented in hardware are zero in
          * configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
+        configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U );
 
         /* Calculate the maximum acceptable priority group value for the number
          * of bits read back. */
diff --git a/portable/IAR/ARM_CM4F/port.c b/portable/IAR/ARM_CM4F/port.c
index 52f5ac287..8234c7dd8 100755
--- a/portable/IAR/ARM_CM4F/port.c
+++ b/portable/IAR/ARM_CM4F/port.c
@@ -281,7 +281,7 @@ BaseType_t xPortStartScheduler( void )
 
         /* Check that the bits not implemented in hardware are zero in
          * configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
+        configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U );
 
         /* Calculate the maximum acceptable priority group value for the number
          * of bits read back. */
diff --git a/portable/IAR/ARM_CM4F_MPU/port.c b/portable/IAR/ARM_CM4F_MPU/port.c
index 27f6f0d6c..d24297e28 100755
--- a/portable/IAR/ARM_CM4F_MPU/port.c
+++ b/portable/IAR/ARM_CM4F_MPU/port.c
@@ -779,7 +779,7 @@ BaseType_t xPortStartScheduler( void )
 
         /* Check that the bits not implemented in hardware are zero in
          * configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
+        configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U );
 
         /* Calculate the maximum acceptable priority group value for the number
          * of bits read back. */
diff --git a/portable/IAR/ARM_CM4F_MPU/portasm.s b/portable/IAR/ARM_CM4F_MPU/portasm.s
index a0cf8baa2..5d7b41061 100644
--- a/portable/IAR/ARM_CM4F_MPU/portasm.s
+++ b/portable/IAR/ARM_CM4F_MPU/portasm.s
@@ -57,6 +57,12 @@ files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler.
     #define configUSE_MPU_WRAPPERS_V1 0
 #endif
 
+/* Errata 837070 workaround must be enabled on Cortex-M7 r0p0
+ * and r0p1 cores. */
+#ifndef configENABLE_ERRATA_837070_WORKAROUND
+    #define configENABLE_ERRATA_837070_WORKAROUND 0
+#endif
+
 /* These must be in sync with portmacro.h. */
 #define portSVC_SYSTEM_CALL_ENTER   3
 #define portSVC_SYSTEM_CALL_ENTER_1 4
diff --git a/portable/IAR/ARM_CM4F_MPU/portmacro.h b/portable/IAR/ARM_CM4F_MPU/portmacro.h
index bf8cad0bb..4be102d6f 100644
--- a/portable/IAR/ARM_CM4F_MPU/portmacro.h
+++ b/portable/IAR/ARM_CM4F_MPU/portmacro.h
@@ -76,6 +76,11 @@ typedef unsigned long    UBaseType_t;
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
 
+/* Errata 837070 workaround must be enabled on Cortex-M7 r0p0
+ * and r0p1 cores. */
+#ifndef configENABLE_ERRATA_837070_WORKAROUND
+    #define configENABLE_ERRATA_837070_WORKAROUND 0
+#endif
 /*-----------------------------------------------------------*/
 
 /* MPU specific constants. */
diff --git a/portable/IAR/ARM_CM55/non_secure/port.c b/portable/IAR/ARM_CM55/non_secure/port.c
index e027b21e1..80410e82e 100644
--- a/portable/IAR/ARM_CM55/non_secure/port.c
+++ b/portable/IAR/ARM_CM55/non_secure/port.c
@@ -1655,7 +1655,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         /* Check that the bits not implemented in hardware are zero in
          * configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
+        configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U );
 
         /* Calculate the maximum acceptable priority group value for the number
          * of bits read back. */
diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/port.c b/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
index e027b21e1..80410e82e 100644
--- a/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
@@ -1655,7 +1655,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         /* Check that the bits not implemented in hardware are zero in
          * configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
+        configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U );
 
         /* Calculate the maximum acceptable priority group value for the number
          * of bits read back. */
diff --git a/portable/IAR/ARM_CM7/r0p1/port.c b/portable/IAR/ARM_CM7/r0p1/port.c
index c1a1cc5aa..fa26a9404 100755
--- a/portable/IAR/ARM_CM7/r0p1/port.c
+++ b/portable/IAR/ARM_CM7/r0p1/port.c
@@ -269,7 +269,7 @@ BaseType_t xPortStartScheduler( void )
 
         /* Check that the bits not implemented in hardware are zero in
          * configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
+        configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U );
 
         /* Calculate the maximum acceptable priority group value for the number
          * of bits read back. */
diff --git a/portable/IAR/ARM_CM85/non_secure/port.c b/portable/IAR/ARM_CM85/non_secure/port.c
index e027b21e1..80410e82e 100644
--- a/portable/IAR/ARM_CM85/non_secure/port.c
+++ b/portable/IAR/ARM_CM85/non_secure/port.c
@@ -1655,7 +1655,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         /* Check that the bits not implemented in hardware are zero in
          * configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
+        configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U );
 
         /* Calculate the maximum acceptable priority group value for the number
          * of bits read back. */
diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/port.c b/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
index e027b21e1..80410e82e 100644
--- a/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
@@ -1655,7 +1655,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         /* Check that the bits not implemented in hardware are zero in
          * configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
+        configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U );
 
         /* Calculate the maximum acceptable priority group value for the number
          * of bits read back. */
diff --git a/portable/RVDS/ARM_CM4_MPU/portmacro.h b/portable/RVDS/ARM_CM4_MPU/portmacro.h
index 0afe11b82..20941571a 100644
--- a/portable/RVDS/ARM_CM4_MPU/portmacro.h
+++ b/portable/RVDS/ARM_CM4_MPU/portmacro.h
@@ -73,6 +73,11 @@ typedef unsigned long    UBaseType_t;
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
 
+/* Errata 837070 workaround must be enabled on Cortex-M7 r0p0
+ * and r0p1 cores. */
+#ifndef configENABLE_ERRATA_837070_WORKAROUND
+    #define configENABLE_ERRATA_837070_WORKAROUND 0
+#endif
 /*-----------------------------------------------------------*/
 
 /* MPU specific constants. */
diff --git a/timers.c b/timers.c
index 0028c3348..f2a210c51 100644
--- a/timers.c
+++ b/timers.c
@@ -67,9 +67,9 @@
     #endif
 
 /* Bit definitions used in the ucStatus member of a timer structure. */
-    #define tmrSTATUS_IS_ACTIVE                  ( ( uint8_t ) 0x01 )
-    #define tmrSTATUS_IS_STATICALLY_ALLOCATED    ( ( uint8_t ) 0x02 )
-    #define tmrSTATUS_IS_AUTORELOAD              ( ( uint8_t ) 0x04 )
+    #define tmrSTATUS_IS_ACTIVE                  ( 0x01U )
+    #define tmrSTATUS_IS_STATICALLY_ALLOCATED    ( 0x02U )
+    #define tmrSTATUS_IS_AUTORELOAD              ( 0x04U )
 
 /* The definition of the timers themselves. */
     typedef struct tmrTimerControl                                               /* The old naming convention is used to prevent breaking kernel aware debuggers. */
@@ -342,7 +342,7 @@
                 /* Timers can be created statically or dynamically so note this
                  * timer was created statically in case it is later deleted.  The
                  * auto-reload bit may get set in prvInitialiseNewTimer(). */
-                pxNewTimer->ucStatus = tmrSTATUS_IS_STATICALLY_ALLOCATED;
+                pxNewTimer->ucStatus = ( uint8_t ) tmrSTATUS_IS_STATICALLY_ALLOCATED;
 
                 prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, xAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer );
             }
@@ -377,7 +377,7 @@
 
         if( xAutoReload != pdFALSE )
         {
-            pxNewTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD;
+            pxNewTimer->ucStatus |= ( uint8_t ) tmrSTATUS_IS_AUTORELOAD;
         }
 
         traceTIMER_CREATE( pxNewTimer );
@@ -499,7 +499,7 @@
         {
             if( xAutoReload != pdFALSE )
             {
-                pxTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD;
+                pxTimer->ucStatus |= ( uint8_t ) tmrSTATUS_IS_AUTORELOAD;
             }
             else
             {
@@ -894,7 +894,7 @@
                     case tmrCOMMAND_RESET:
                     case tmrCOMMAND_RESET_FROM_ISR:
                         /* Start or restart a timer. */
-                        pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
+                        pxTimer->ucStatus |= ( uint8_t ) tmrSTATUS_IS_ACTIVE;
 
                         if( prvInsertTimerInActiveList( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE )
                         {
@@ -928,7 +928,7 @@
 
                     case tmrCOMMAND_CHANGE_PERIOD:
                     case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR:
-                        pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
+                        pxTimer->ucStatus |= ( uint8_t ) tmrSTATUS_IS_ACTIVE;
                         pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue;
                         configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) );
 

From 0d9649ca4514c32b8aaac31a3c56c7865fefcc94 Mon Sep 17 00:00:00 2001
From: oliverlavery <oliver.lavery@gmail.com>
Date: Wed, 23 Aug 2023 05:57:54 +0100
Subject: [PATCH 042/424] Heap protect (#747)

Setting configENABLE_HEAP_PROTECTOR to 1 obfuscates heap
block pointers by XORing them with an application supplied
canary value. This obfuscation helps to catch heap corruption
should a heap buffer overflow occur.

This PR also adds heap bounds checking to heap_4 and heap_5.

This PR also adds some additional integer underflow checks.
---
 include/FreeRTOS.h        |   4 +
 portable/MemMang/heap_4.c |  97 +++++++++++++++++++-----
 portable/MemMang/heap_5.c | 153 ++++++++++++++++++++++++++++++--------
 3 files changed, 201 insertions(+), 53 deletions(-)

diff --git a/include/FreeRTOS.h b/include/FreeRTOS.h
index 34a14ca63..ca5818eae 100644
--- a/include/FreeRTOS.h
+++ b/include/FreeRTOS.h
@@ -1071,6 +1071,10 @@
     #define configAPPLICATION_ALLOCATED_HEAP    0
 #endif
 
+#ifndef configENABLE_HEAP_PROTECTOR
+    #define configENABLE_HEAP_PROTECTOR    0
+#endif
+
 #ifndef configUSE_TASK_NOTIFICATIONS
     #define configUSE_TASK_NOTIFICATIONS    1
 #endif
diff --git a/portable/MemMang/heap_4.c b/portable/MemMang/heap_4.c
index b1053ba40..59a1ce0be 100644
--- a/portable/MemMang/heap_4.c
+++ b/portable/MemMang/heap_4.c
@@ -65,10 +65,13 @@
 #define heapSIZE_MAX              ( ~( ( size_t ) 0 ) )
 
 /* Check if multiplying a and b will result in overflow. */
-#define heapMULTIPLY_WILL_OVERFLOW( a, b )    ( ( ( a ) > 0 ) && ( ( b ) > ( heapSIZE_MAX / ( a ) ) ) )
+#define heapMULTIPLY_WILL_OVERFLOW( a, b )     ( ( ( a ) > 0 ) && ( ( b ) > ( heapSIZE_MAX / ( a ) ) ) )
 
 /* Check if adding a and b will result in overflow. */
-#define heapADD_WILL_OVERFLOW( a, b )         ( ( a ) > ( heapSIZE_MAX - ( b ) ) )
+#define heapADD_WILL_OVERFLOW( a, b )          ( ( a ) > ( heapSIZE_MAX - ( b ) ) )
+
+/* Check if the subtraction operation ( a - b ) will result in underflow. */
+#define heapSUBTRACT_WILL_UNDERFLOW( a, b )    ( ( a ) < ( b ) )
 
 /* MSB of the xBlockSize member of an BlockLink_t structure is used to track
  * the allocation status of a block.  When MSB of the xBlockSize member of
@@ -100,6 +103,38 @@ typedef struct A_BLOCK_LINK
     size_t xBlockSize;                     /**< The size of the free block. */
 } BlockLink_t;
 
+/* Setting configENABLE_HEAP_PROTECTOR to 1 enables heap block pointers
+ * protection using an application supplied canary value to catch heap
+ * corruption should a heap buffer overflow occur.
+ */
+#if ( configENABLE_HEAP_PROTECTOR == 1 )
+
+/**
+ * @brief Application provided function to get a random value to be used as canary.
+ *
+ * @param pxHeapCanary [out] Output parameter to return the canary value.
+ */
+    extern void vApplicationGetRandomHeapCanary( portPOINTER_SIZE_TYPE * pxHeapCanary );
+
+/* Canary value for protecting internal heap pointers. */
+    PRIVILEGED_DATA static portPOINTER_SIZE_TYPE xHeapCanary;
+
+/* Macro to load/store BlockLink_t pointers to memory. By XORing the
+ * pointers with a random canary value, heap overflows will result
+ * in randomly unpredictable pointer values which will be caught by
+ * heapVALIDATE_BLOCK_POINTER assert. */
+    #define heapPROTECT_BLOCK_POINTER( pxBlock )    ( ( BlockLink_t * ) ( ( ( portPOINTER_SIZE_TYPE ) ( pxBlock ) ) ^ xHeapCanary ) )
+#else
+
+    #define heapPROTECT_BLOCK_POINTER( pxBlock )    ( pxBlock )
+
+#endif /* configENABLE_HEAP_PROTECTOR */
+
+/* Assert that a heap block pointer is within the heap bounds. */
+#define heapVALIDATE_BLOCK_POINTER( pxBlock )                          \
+    configASSERT( ( ( uint8_t * ) ( pxBlock ) >= &( ucHeap[ 0 ] ) ) && \
+                  ( ( uint8_t * ) ( pxBlock ) <= &( ucHeap[ configTOTAL_HEAP_SIZE - 1 ] ) ) )
+
 /*-----------------------------------------------------------*/
 
 /*
@@ -206,12 +241,14 @@ void * pvPortMalloc( size_t xWantedSize )
                 /* Traverse the list from the start (lowest address) block until
                  * one of adequate size is found. */
                 pxPreviousBlock = &xStart;
-                pxBlock = xStart.pxNextFreeBlock;
+                pxBlock = heapPROTECT_BLOCK_POINTER( xStart.pxNextFreeBlock );
+                heapVALIDATE_BLOCK_POINTER( pxBlock );
 
-                while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
+                while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != heapPROTECT_BLOCK_POINTER( NULL ) ) )
                 {
                     pxPreviousBlock = pxBlock;
-                    pxBlock = pxBlock->pxNextFreeBlock;
+                    pxBlock = heapPROTECT_BLOCK_POINTER( pxBlock->pxNextFreeBlock );
+                    heapVALIDATE_BLOCK_POINTER( pxBlock );
                 }
 
                 /* If the end marker was reached then a block of adequate size
@@ -220,7 +257,8 @@ void * pvPortMalloc( size_t xWantedSize )
                 {
                     /* Return the memory space pointed to - jumping over the
                      * BlockLink_t structure at its start. */
-                    pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
+                    pvReturn = ( void * ) ( ( ( uint8_t * ) heapPROTECT_BLOCK_POINTER( pxPreviousBlock->pxNextFreeBlock ) ) + xHeapStructSize );
+                    heapVALIDATE_BLOCK_POINTER( pvReturn );
 
                     /* This block is being returned for use so must be taken out
                      * of the list of free blocks. */
@@ -228,6 +266,8 @@ void * pvPortMalloc( size_t xWantedSize )
 
                     /* If the block is larger than required it can be split into
                      * two. */
+                    configASSERT( heapSUBTRACT_WILL_UNDERFLOW( pxBlock->xBlockSize, xWantedSize ) == 0 );
+
                     if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
                     {
                         /* This block is to be split into two.  Create a new
@@ -244,7 +284,7 @@ void * pvPortMalloc( size_t xWantedSize )
 
                         /* Insert the new block into the list of free blocks. */
                         pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock;
-                        pxPreviousBlock->pxNextFreeBlock = pxNewBlockLink;
+                        pxPreviousBlock->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( pxNewBlockLink );
                     }
                     else
                     {
@@ -319,6 +359,7 @@ void vPortFree( void * pv )
         /* This casting is to keep the compiler from issuing warnings. */
         pxLink = ( void * ) puc;
 
+        heapVALIDATE_BLOCK_POINTER( pxLink );
         configASSERT( heapBLOCK_IS_ALLOCATED( pxLink ) != 0 );
         configASSERT( pxLink->pxNextFreeBlock == NULL );
 
@@ -331,7 +372,12 @@ void vPortFree( void * pv )
                 heapFREE_BLOCK( pxLink );
                 #if ( configHEAP_CLEAR_MEMORY_ON_FREE == 1 )
                 {
-                    ( void ) memset( puc + xHeapStructSize, 0, pxLink->xBlockSize - xHeapStructSize );
+                    /* Check for underflow as this can occur if xBlockSize is
+                     * overwritten in a heap block. */
+                    if( heapSUBTRACT_WILL_UNDERFLOW( pxLink->xBlockSize, xHeapStructSize ) == 0 )
+                    {
+                        ( void ) memset( puc + xHeapStructSize, 0, pxLink->xBlockSize - xHeapStructSize );
+                    }
                 }
                 #endif
 
@@ -414,9 +460,15 @@ static void prvHeapInit( void ) /* PRIVILEGED_FUNCTION */
 
     pucAlignedHeap = ( uint8_t * ) uxAddress;
 
+    #if ( configENABLE_HEAP_PROTECTOR == 1 )
+    {
+        vApplicationGetRandomHeapCanary( &( xHeapCanary ) );
+    }
+    #endif
+
     /* xStart is used to hold a pointer to the first item in the list of free
      * blocks.  The void cast is used to prevent compiler warnings. */
-    xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
+    xStart.pxNextFreeBlock = ( void * ) heapPROTECT_BLOCK_POINTER( pucAlignedHeap );
     xStart.xBlockSize = ( size_t ) 0;
 
     /* pxEnd is used to mark the end of the list of free blocks and is inserted
@@ -426,13 +478,13 @@ static void prvHeapInit( void ) /* PRIVILEGED_FUNCTION */
     uxAddress &= ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK );
     pxEnd = ( BlockLink_t * ) uxAddress;
     pxEnd->xBlockSize = 0;
-    pxEnd->pxNextFreeBlock = NULL;
+    pxEnd->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( NULL );
 
     /* To start with there is a single free block that is sized to take up the
      * entire heap space, minus the space taken by pxEnd. */
     pxFirstFreeBlock = ( BlockLink_t * ) pucAlignedHeap;
     pxFirstFreeBlock->xBlockSize = ( size_t ) ( uxAddress - ( portPOINTER_SIZE_TYPE ) pxFirstFreeBlock );
-    pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
+    pxFirstFreeBlock->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( pxEnd );
 
     /* Only one block exists - and it covers the entire usable heap space. */
     xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
@@ -447,11 +499,16 @@ static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) /* PRIVI
 
     /* Iterate through the list until a block is found that has a higher address
      * than the block being inserted. */
-    for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
+    for( pxIterator = &xStart; heapPROTECT_BLOCK_POINTER( pxIterator->pxNextFreeBlock ) < pxBlockToInsert; pxIterator = heapPROTECT_BLOCK_POINTER( pxIterator->pxNextFreeBlock ) )
     {
         /* Nothing to do here, just iterate to the right position. */
     }
 
+    if( pxIterator != &xStart )
+    {
+        heapVALIDATE_BLOCK_POINTER( pxIterator );
+    }
+
     /* Do the block being inserted, and the block it is being inserted after
      * make a contiguous block of memory? */
     puc = ( uint8_t * ) pxIterator;
@@ -470,17 +527,17 @@ static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) /* PRIVI
      * make a contiguous block of memory? */
     puc = ( uint8_t * ) pxBlockToInsert;
 
-    if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
+    if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) heapPROTECT_BLOCK_POINTER( pxIterator->pxNextFreeBlock ) )
     {
-        if( pxIterator->pxNextFreeBlock != pxEnd )
+        if( heapPROTECT_BLOCK_POINTER( pxIterator->pxNextFreeBlock ) != pxEnd )
         {
             /* Form one big block from the two blocks. */
-            pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
-            pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
+            pxBlockToInsert->xBlockSize += heapPROTECT_BLOCK_POINTER( pxIterator->pxNextFreeBlock )->xBlockSize;
+            pxBlockToInsert->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( pxIterator->pxNextFreeBlock )->pxNextFreeBlock;
         }
         else
         {
-            pxBlockToInsert->pxNextFreeBlock = pxEnd;
+            pxBlockToInsert->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( pxEnd );
         }
     }
     else
@@ -494,7 +551,7 @@ static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) /* PRIVI
      * to itself. */
     if( pxIterator != pxBlockToInsert )
     {
-        pxIterator->pxNextFreeBlock = pxBlockToInsert;
+        pxIterator->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( pxBlockToInsert );
     }
     else
     {
@@ -510,7 +567,7 @@ void vPortGetHeapStats( HeapStats_t * pxHeapStats )
 
     vTaskSuspendAll();
     {
-        pxBlock = xStart.pxNextFreeBlock;
+        pxBlock = heapPROTECT_BLOCK_POINTER( xStart.pxNextFreeBlock );
 
         /* pxBlock will be NULL if the heap has not been initialised.  The heap
          * is initialised automatically when the first allocation is made. */
@@ -534,7 +591,7 @@ void vPortGetHeapStats( HeapStats_t * pxHeapStats )
 
                 /* Move to the next block in the chain until the last block is
                  * reached. */
-                pxBlock = pxBlock->pxNextFreeBlock;
+                pxBlock = heapPROTECT_BLOCK_POINTER( pxBlock->pxNextFreeBlock );
             }
         }
     }
diff --git a/portable/MemMang/heap_5.c b/portable/MemMang/heap_5.c
index 618dcf827..17b0d07d9 100644
--- a/portable/MemMang/heap_5.c
+++ b/portable/MemMang/heap_5.c
@@ -99,10 +99,13 @@
 #define heapSIZE_MAX              ( ~( ( size_t ) 0 ) )
 
 /* Check if multiplying a and b will result in overflow. */
-#define heapMULTIPLY_WILL_OVERFLOW( a, b )    ( ( ( a ) > 0 ) && ( ( b ) > ( heapSIZE_MAX / ( a ) ) ) )
+#define heapMULTIPLY_WILL_OVERFLOW( a, b )     ( ( ( a ) > 0 ) && ( ( b ) > ( heapSIZE_MAX / ( a ) ) ) )
 
 /* Check if adding a and b will result in overflow. */
-#define heapADD_WILL_OVERFLOW( a, b )         ( ( a ) > ( heapSIZE_MAX - ( b ) ) )
+#define heapADD_WILL_OVERFLOW( a, b )          ( ( a ) > ( heapSIZE_MAX - ( b ) ) )
+
+/* Check if the subtraction operation ( a - b ) will result in underflow. */
+#define heapSUBTRACT_WILL_UNDERFLOW( a, b )    ( ( a ) < ( b ) )
 
 /* MSB of the xBlockSize member of an BlockLink_t structure is used to track
  * the allocation status of a block.  When MSB of the xBlockSize member of
@@ -124,6 +127,46 @@ typedef struct A_BLOCK_LINK
     size_t xBlockSize;                     /**< The size of the free block. */
 } BlockLink_t;
 
+/* Setting configENABLE_HEAP_PROTECTOR to 1 enables heap block pointers
+ * protection using an application supplied canary value to catch heap
+ * corruption should a heap buffer overflow occur.
+ */
+#if ( configENABLE_HEAP_PROTECTOR == 1 )
+
+/**
+ * @brief Application provided function to get a random value to be used as canary.
+ *
+ * @param pxHeapCanary [out] Output parameter to return the canary value.
+ */
+    extern void vApplicationGetRandomHeapCanary( portPOINTER_SIZE_TYPE * pxHeapCanary );
+
+/* Canary value for protecting internal heap pointers. */
+    PRIVILEGED_DATA static portPOINTER_SIZE_TYPE xHeapCanary;
+
+
+/* Macro to load/store BlockLink_t pointers to memory. By XORing the
+ * pointers with a random canary value, heap overflows will result
+ * in randomly unpredictable pointer values which will be caught by
+ * heapVALIDATE_BLOCK_POINTER assert. */
+    #define heapPROTECT_BLOCK_POINTER( pxBlock )    ( ( BlockLink_t * ) ( ( ( portPOINTER_SIZE_TYPE ) ( pxBlock ) ) ^ xHeapCanary ) )
+
+#else /* if ( configENABLE_HEAP_PROTECTOR == 1 ) */
+
+    #define heapPROTECT_BLOCK_POINTER( pxBlock )    ( pxBlock )
+
+#endif /* configENABLE_HEAP_PROTECTOR */
+
+/* Highest and lowest heap addresses used for heap block bounds checking. */
+PRIVILEGED_DATA static uint8_t * pucHeapHighAddress = NULL;
+PRIVILEGED_DATA static uint8_t * pucHeapLowAddress = NULL;
+
+/* Assert that a heap block pointer is within the heap bounds. */
+#define heapVALIDATE_BLOCK_POINTER( pxBlock )                           \
+    configASSERT( ( pucHeapHighAddress != NULL ) &&                     \
+                  ( pucHeapLowAddress != NULL ) &&                      \
+                  ( ( uint8_t * ) ( pxBlock ) >= pucHeapLowAddress ) && \
+                  ( ( uint8_t * ) ( pxBlock ) < pucHeapHighAddress ) )
+
 /*-----------------------------------------------------------*/
 
 /*
@@ -132,8 +175,8 @@ typedef struct A_BLOCK_LINK
  * the block in front it and/or the block behind it if the memory blocks are
  * adjacent to each other.
  */
-static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert );
-
+static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) PRIVILEGED_FUNCTION;
+void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions ) PRIVILEGED_FUNCTION;
 /*-----------------------------------------------------------*/
 
 /* The size of the structure placed at the beginning of each allocated memory
@@ -141,15 +184,15 @@ static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert );
 static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( portBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
 
 /* Create a couple of list links to mark the start and end of the list. */
-static BlockLink_t xStart;
-static BlockLink_t * pxEnd = NULL;
+PRIVILEGED_DATA static BlockLink_t xStart;
+PRIVILEGED_DATA static BlockLink_t * pxEnd = NULL;
 
 /* Keeps track of the number of calls to allocate and free memory as well as the
  * number of free bytes remaining, but says nothing about fragmentation. */
-static size_t xFreeBytesRemaining = 0U;
-static size_t xMinimumEverFreeBytesRemaining = 0U;
-static size_t xNumberOfSuccessfulAllocations = 0;
-static size_t xNumberOfSuccessfulFrees = 0;
+PRIVILEGED_DATA static size_t xFreeBytesRemaining = 0U;
+PRIVILEGED_DATA static size_t xMinimumEverFreeBytesRemaining = 0U;
+PRIVILEGED_DATA static size_t xNumberOfSuccessfulAllocations = 0;
+PRIVILEGED_DATA static size_t xNumberOfSuccessfulFrees = 0;
 
 /*-----------------------------------------------------------*/
 
@@ -217,12 +260,14 @@ void * pvPortMalloc( size_t xWantedSize )
                 /* Traverse the list from the start (lowest address) block until
                  * one of adequate size is found. */
                 pxPreviousBlock = &xStart;
-                pxBlock = xStart.pxNextFreeBlock;
+                pxBlock = heapPROTECT_BLOCK_POINTER( xStart.pxNextFreeBlock );
+                heapVALIDATE_BLOCK_POINTER( pxBlock );
 
-                while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
+                while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != heapPROTECT_BLOCK_POINTER( NULL ) ) )
                 {
                     pxPreviousBlock = pxBlock;
-                    pxBlock = pxBlock->pxNextFreeBlock;
+                    pxBlock = heapPROTECT_BLOCK_POINTER( pxBlock->pxNextFreeBlock );
+                    heapVALIDATE_BLOCK_POINTER( pxBlock );
                 }
 
                 /* If the end marker was reached then a block of adequate size
@@ -231,7 +276,8 @@ void * pvPortMalloc( size_t xWantedSize )
                 {
                     /* Return the memory space pointed to - jumping over the
                      * BlockLink_t structure at its start. */
-                    pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
+                    pvReturn = ( void * ) ( ( ( uint8_t * ) heapPROTECT_BLOCK_POINTER( pxPreviousBlock->pxNextFreeBlock ) ) + xHeapStructSize );
+                    heapVALIDATE_BLOCK_POINTER( pvReturn );
 
                     /* This block is being returned for use so must be taken out
                      * of the list of free blocks. */
@@ -239,6 +285,8 @@ void * pvPortMalloc( size_t xWantedSize )
 
                     /* If the block is larger than required it can be split into
                      * two. */
+                    configASSERT( heapSUBTRACT_WILL_UNDERFLOW( pxBlock->xBlockSize, xWantedSize ) == 0 );
+
                     if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
                     {
                         /* This block is to be split into two.  Create a new
@@ -246,6 +294,7 @@ void * pvPortMalloc( size_t xWantedSize )
                          * cast is used to prevent byte alignment warnings from the
                          * compiler. */
                         pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
+                        configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 );
 
                         /* Calculate the sizes of two blocks split from the
                          * single block. */
@@ -254,7 +303,7 @@ void * pvPortMalloc( size_t xWantedSize )
 
                         /* Insert the new block into the list of free blocks. */
                         pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock;
-                        pxPreviousBlock->pxNextFreeBlock = pxNewBlockLink;
+                        pxPreviousBlock->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( pxNewBlockLink );
                     }
                     else
                     {
@@ -310,6 +359,7 @@ void * pvPortMalloc( size_t xWantedSize )
     }
     #endif /* if ( configUSE_MALLOC_FAILED_HOOK == 1 ) */
 
+    configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 );
     return pvReturn;
 }
 /*-----------------------------------------------------------*/
@@ -328,6 +378,7 @@ void vPortFree( void * pv )
         /* This casting is to keep the compiler from issuing warnings. */
         pxLink = ( void * ) puc;
 
+        heapVALIDATE_BLOCK_POINTER( pxLink );
         configASSERT( heapBLOCK_IS_ALLOCATED( pxLink ) != 0 );
         configASSERT( pxLink->pxNextFreeBlock == NULL );
 
@@ -340,7 +391,12 @@ void vPortFree( void * pv )
                 heapFREE_BLOCK( pxLink );
                 #if ( configHEAP_CLEAR_MEMORY_ON_FREE == 1 )
                 {
-                    ( void ) memset( puc + xHeapStructSize, 0, pxLink->xBlockSize - xHeapStructSize );
+                    /* Check for underflow as this can occur if xBlockSize is
+                     * overwritten in a heap block. */
+                    if( heapSUBTRACT_WILL_UNDERFLOW( pxLink->xBlockSize, xHeapStructSize ) == 0 )
+                    {
+                        ( void ) memset( puc + xHeapStructSize, 0, pxLink->xBlockSize - xHeapStructSize );
+                    }
                 }
                 #endif
 
@@ -398,18 +454,23 @@ void * pvPortCalloc( size_t xNum,
 }
 /*-----------------------------------------------------------*/
 
-static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert )
+static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) /* PRIVILEGED_FUNCTION */
 {
     BlockLink_t * pxIterator;
     uint8_t * puc;
 
     /* Iterate through the list until a block is found that has a higher address
      * than the block being inserted. */
-    for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
+    for( pxIterator = &xStart; heapPROTECT_BLOCK_POINTER( pxIterator->pxNextFreeBlock ) < pxBlockToInsert; pxIterator = heapPROTECT_BLOCK_POINTER( pxIterator->pxNextFreeBlock ) )
     {
         /* Nothing to do here, just iterate to the right position. */
     }
 
+    if( pxIterator != &xStart )
+    {
+        heapVALIDATE_BLOCK_POINTER( pxIterator );
+    }
+
     /* Do the block being inserted, and the block it is being inserted after
      * make a contiguous block of memory? */
     puc = ( uint8_t * ) pxIterator;
@@ -428,17 +489,17 @@ static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert )
      * make a contiguous block of memory? */
     puc = ( uint8_t * ) pxBlockToInsert;
 
-    if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
+    if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) heapPROTECT_BLOCK_POINTER( pxIterator->pxNextFreeBlock ) )
     {
-        if( pxIterator->pxNextFreeBlock != pxEnd )
+        if( heapPROTECT_BLOCK_POINTER( pxIterator->pxNextFreeBlock ) != pxEnd )
         {
             /* Form one big block from the two blocks. */
-            pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
-            pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
+            pxBlockToInsert->xBlockSize += heapPROTECT_BLOCK_POINTER( pxIterator->pxNextFreeBlock )->xBlockSize;
+            pxBlockToInsert->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( pxIterator->pxNextFreeBlock )->pxNextFreeBlock;
         }
         else
         {
-            pxBlockToInsert->pxNextFreeBlock = pxEnd;
+            pxBlockToInsert->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( pxEnd );
         }
     }
     else
@@ -446,13 +507,13 @@ static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert )
         pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
     }
 
-    /* If the block being inserted plugged a gab, so was merged with the block
+    /* If the block being inserted plugged a gap, so was merged with the block
      * before and the block after, then it's pxNextFreeBlock pointer will have
      * already been set, and should not be set here as that would make it point
      * to itself. */
     if( pxIterator != pxBlockToInsert )
     {
-        pxIterator->pxNextFreeBlock = pxBlockToInsert;
+        pxIterator->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( pxBlockToInsert );
     }
     else
     {
@@ -461,7 +522,7 @@ static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert )
 }
 /*-----------------------------------------------------------*/
 
-void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions )
+void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions ) /* PRIVILEGED_FUNCTION */
 {
     BlockLink_t * pxFirstFreeBlockInRegion = NULL;
     BlockLink_t * pxPreviousFreeBlock;
@@ -474,6 +535,12 @@ void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions )
     /* Can only call once! */
     configASSERT( pxEnd == NULL );
 
+    #if ( configENABLE_HEAP_PROTECTOR == 1 )
+    {
+        vApplicationGetRandomHeapCanary( &( xHeapCanary ) );
+    }
+    #endif
+
     pxHeapRegion = &( pxHeapRegions[ xDefinedRegions ] );
 
     while( pxHeapRegion->xSizeInBytes > 0 )
@@ -499,19 +566,29 @@ void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions )
         {
             /* xStart is used to hold a pointer to the first item in the list of
              *  free blocks.  The void cast is used to prevent compiler warnings. */
-            xStart.pxNextFreeBlock = ( BlockLink_t * ) xAlignedHeap;
+            xStart.pxNextFreeBlock = ( BlockLink_t * ) heapPROTECT_BLOCK_POINTER( xAlignedHeap );
             xStart.xBlockSize = ( size_t ) 0;
         }
         else
         {
             /* Should only get here if one region has already been added to the
              * heap. */
-            configASSERT( pxEnd != NULL );
+            configASSERT( pxEnd != heapPROTECT_BLOCK_POINTER( NULL ) );
 
             /* Check blocks are passed in with increasing start addresses. */
             configASSERT( ( size_t ) xAddress > ( size_t ) pxEnd );
         }
 
+        #if ( configENABLE_HEAP_PROTECTOR == 1 )
+        {
+            if( ( pucHeapLowAddress == NULL ) ||
+                ( ( uint8_t * ) xAlignedHeap < pucHeapLowAddress ) )
+            {
+                pucHeapLowAddress = ( uint8_t * ) xAlignedHeap;
+            }
+        }
+        #endif /* configENABLE_HEAP_PROTECTOR */
+
         /* Remember the location of the end marker in the previous region, if
          * any. */
         pxPreviousFreeBlock = pxEnd;
@@ -523,24 +600,34 @@ void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions )
         xAddress &= ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK );
         pxEnd = ( BlockLink_t * ) xAddress;
         pxEnd->xBlockSize = 0;
-        pxEnd->pxNextFreeBlock = NULL;
+        pxEnd->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( NULL );
 
         /* To start with there is a single free block in this region that is
          * sized to take up the entire heap region minus the space taken by the
          * free block structure. */
         pxFirstFreeBlockInRegion = ( BlockLink_t * ) xAlignedHeap;
         pxFirstFreeBlockInRegion->xBlockSize = ( size_t ) ( xAddress - ( portPOINTER_SIZE_TYPE ) pxFirstFreeBlockInRegion );
-        pxFirstFreeBlockInRegion->pxNextFreeBlock = pxEnd;
+        pxFirstFreeBlockInRegion->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( pxEnd );
 
         /* If this is not the first region that makes up the entire heap space
          * then link the previous region to this region. */
         if( pxPreviousFreeBlock != NULL )
         {
-            pxPreviousFreeBlock->pxNextFreeBlock = pxFirstFreeBlockInRegion;
+            pxPreviousFreeBlock->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( pxFirstFreeBlockInRegion );
         }
 
         xTotalHeapSize += pxFirstFreeBlockInRegion->xBlockSize;
 
+        #if ( configENABLE_HEAP_PROTECTOR == 1 )
+        {
+            if( ( pucHeapHighAddress == NULL ) ||
+                ( ( ( ( uint8_t * ) pxFirstFreeBlockInRegion ) + pxFirstFreeBlockInRegion->xBlockSize ) > pucHeapHighAddress ) )
+            {
+                pucHeapHighAddress = ( ( uint8_t * ) pxFirstFreeBlockInRegion ) + pxFirstFreeBlockInRegion->xBlockSize;
+            }
+        }
+        #endif
+
         /* Move onto the next HeapRegion_t structure. */
         xDefinedRegions++;
         pxHeapRegion = &( pxHeapRegions[ xDefinedRegions ] );
@@ -561,7 +648,7 @@ void vPortGetHeapStats( HeapStats_t * pxHeapStats )
 
     vTaskSuspendAll();
     {
-        pxBlock = xStart.pxNextFreeBlock;
+        pxBlock = heapPROTECT_BLOCK_POINTER( xStart.pxNextFreeBlock );
 
         /* pxBlock will be NULL if the heap has not been initialised.  The heap
          * is initialised automatically when the first allocation is made. */
@@ -591,7 +678,7 @@ void vPortGetHeapStats( HeapStats_t * pxHeapStats )
 
                 /* Move to the next block in the chain until the last block is
                  * reached. */
-                pxBlock = pxBlock->pxNextFreeBlock;
+                pxBlock = heapPROTECT_BLOCK_POINTER( pxBlock->pxNextFreeBlock );
             }
         }
     }

From af2904b01c243b5d59ea477fc8564679b451fcd8 Mon Sep 17 00:00:00 2001
From: Jordan Williams <jordan@jwillikers.com>
Date: Fri, 25 Aug 2023 00:46:36 -0500
Subject: [PATCH 043/424] Fix typo in the include directory for the the
 GCC_ARM_CM55_TFM port (#764)

Should be CM55 not CM85.
---
 portable/CMakeLists.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/portable/CMakeLists.txt b/portable/CMakeLists.txt
index 988be1524..a13e08820 100644
--- a/portable/CMakeLists.txt
+++ b/portable/CMakeLists.txt
@@ -774,7 +774,7 @@ target_include_directories(freertos_kernel_port PUBLIC
     $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM55_NONSECURE>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM55/non_secure>
     $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM55_SECURE>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM55/secure>
     $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM55_NTZ_NONSECURE>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM55_NTZ/non_secure>
-    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM55_TFM>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM85_NTZ/non_secure>
+    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM55_TFM>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM55_NTZ/non_secure>
 
     $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM85_NONSECURE>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM85/non_secure>
     $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM85_SECURE>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM85/secure>

From 80a390cbbbc034fcf173c852f2f4ff03638d2641 Mon Sep 17 00:00:00 2001
From: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Date: Sun, 3 Sep 2023 09:19:26 +0800
Subject: [PATCH 044/424] Update block validate macro in heap_5 (#774)

* Update block validate macro in heap_5, and update for readability
* Don't validate block pointer when configENABLE_HEAP_PROTECTOR is not set to 1
---
 portable/MemMang/heap_5.c | 89 +++++++++++++++++++++------------------
 1 file changed, 49 insertions(+), 40 deletions(-)

diff --git a/portable/MemMang/heap_5.c b/portable/MemMang/heap_5.c
index 17b0d07d9..a801298c1 100644
--- a/portable/MemMang/heap_5.c
+++ b/portable/MemMang/heap_5.c
@@ -117,6 +117,33 @@
 #define heapALLOCATE_BLOCK( pxBlock )            ( ( pxBlock->xBlockSize ) |= heapBLOCK_ALLOCATED_BITMASK )
 #define heapFREE_BLOCK( pxBlock )                ( ( pxBlock->xBlockSize ) &= ~heapBLOCK_ALLOCATED_BITMASK )
 
+/* Setting configENABLE_HEAP_PROTECTOR to 1 enables heap block pointers
+ * protection using an application supplied canary value to catch heap
+ * corruption should a heap buffer overflow occur.
+ */
+#if ( configENABLE_HEAP_PROTECTOR == 1 )
+
+/* Macro to load/store BlockLink_t pointers to memory. By XORing the
+ * pointers with a random canary value, heap overflows will result
+ * in randomly unpredictable pointer values which will be caught by
+ * heapVALIDATE_BLOCK_POINTER assert. */
+    #define heapPROTECT_BLOCK_POINTER( pxBlock )    ( ( BlockLink_t * ) ( ( ( portPOINTER_SIZE_TYPE ) ( pxBlock ) ) ^ xHeapCanary ) )
+
+/* Assert that a heap block pointer is within the heap bounds. */
+    #define heapVALIDATE_BLOCK_POINTER( pxBlock )                       \
+    configASSERT( ( pucHeapHighAddress != NULL ) &&                     \
+                  ( pucHeapLowAddress != NULL ) &&                      \
+                  ( ( uint8_t * ) ( pxBlock ) >= pucHeapLowAddress ) && \
+                  ( ( uint8_t * ) ( pxBlock ) < pucHeapHighAddress ) )
+
+#else /* if ( configENABLE_HEAP_PROTECTOR == 1 ) */
+
+    #define heapPROTECT_BLOCK_POINTER( pxBlock )     ( pxBlock )
+
+    #define heapVALIDATE_BLOCK_POINTER( pxBlock )    ( pxBlock )
+
+#endif /* configENABLE_HEAP_PROTECTOR */
+
 /*-----------------------------------------------------------*/
 
 /* Define the linked list structure.  This is used to link free blocks in order
@@ -127,46 +154,6 @@ typedef struct A_BLOCK_LINK
     size_t xBlockSize;                     /**< The size of the free block. */
 } BlockLink_t;
 
-/* Setting configENABLE_HEAP_PROTECTOR to 1 enables heap block pointers
- * protection using an application supplied canary value to catch heap
- * corruption should a heap buffer overflow occur.
- */
-#if ( configENABLE_HEAP_PROTECTOR == 1 )
-
-/**
- * @brief Application provided function to get a random value to be used as canary.
- *
- * @param pxHeapCanary [out] Output parameter to return the canary value.
- */
-    extern void vApplicationGetRandomHeapCanary( portPOINTER_SIZE_TYPE * pxHeapCanary );
-
-/* Canary value for protecting internal heap pointers. */
-    PRIVILEGED_DATA static portPOINTER_SIZE_TYPE xHeapCanary;
-
-
-/* Macro to load/store BlockLink_t pointers to memory. By XORing the
- * pointers with a random canary value, heap overflows will result
- * in randomly unpredictable pointer values which will be caught by
- * heapVALIDATE_BLOCK_POINTER assert. */
-    #define heapPROTECT_BLOCK_POINTER( pxBlock )    ( ( BlockLink_t * ) ( ( ( portPOINTER_SIZE_TYPE ) ( pxBlock ) ) ^ xHeapCanary ) )
-
-#else /* if ( configENABLE_HEAP_PROTECTOR == 1 ) */
-
-    #define heapPROTECT_BLOCK_POINTER( pxBlock )    ( pxBlock )
-
-#endif /* configENABLE_HEAP_PROTECTOR */
-
-/* Highest and lowest heap addresses used for heap block bounds checking. */
-PRIVILEGED_DATA static uint8_t * pucHeapHighAddress = NULL;
-PRIVILEGED_DATA static uint8_t * pucHeapLowAddress = NULL;
-
-/* Assert that a heap block pointer is within the heap bounds. */
-#define heapVALIDATE_BLOCK_POINTER( pxBlock )                           \
-    configASSERT( ( pucHeapHighAddress != NULL ) &&                     \
-                  ( pucHeapLowAddress != NULL ) &&                      \
-                  ( ( uint8_t * ) ( pxBlock ) >= pucHeapLowAddress ) && \
-                  ( ( uint8_t * ) ( pxBlock ) < pucHeapHighAddress ) )
-
 /*-----------------------------------------------------------*/
 
 /*
@@ -177,6 +164,17 @@ PRIVILEGED_DATA static uint8_t * pucHeapLowAddress = NULL;
  */
 static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) PRIVILEGED_FUNCTION;
 void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions ) PRIVILEGED_FUNCTION;
+
+#if ( configENABLE_HEAP_PROTECTOR == 1 )
+
+/**
+ * @brief Application provided function to get a random value to be used as canary.
+ *
+ * @param pxHeapCanary [out] Output parameter to return the canary value.
+ */
+    extern void vApplicationGetRandomHeapCanary( portPOINTER_SIZE_TYPE * pxHeapCanary );
+#endif /* configENABLE_HEAP_PROTECTOR */
+
 /*-----------------------------------------------------------*/
 
 /* The size of the structure placed at the beginning of each allocated memory
@@ -194,6 +192,17 @@ PRIVILEGED_DATA static size_t xMinimumEverFreeBytesRemaining = 0U;
 PRIVILEGED_DATA static size_t xNumberOfSuccessfulAllocations = 0;
 PRIVILEGED_DATA static size_t xNumberOfSuccessfulFrees = 0;
 
+#if ( configENABLE_HEAP_PROTECTOR == 1 )
+
+/* Canary value for protecting internal heap pointers. */
+    PRIVILEGED_DATA static portPOINTER_SIZE_TYPE xHeapCanary;
+
+/* Highest and lowest heap addresses used for heap block bounds checking. */
+    PRIVILEGED_DATA static uint8_t * pucHeapHighAddress = NULL;
+    PRIVILEGED_DATA static uint8_t * pucHeapLowAddress = NULL;
+
+#endif /* configENABLE_HEAP_PROTECTOR */
+
 /*-----------------------------------------------------------*/
 
 void * pvPortMalloc( size_t xWantedSize )

From 1aaa318f1cdf2d35b47c7f64e7c453cacc184d2a Mon Sep 17 00:00:00 2001
From: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Date: Mon, 4 Sep 2023 18:10:36 +0800
Subject: [PATCH 045/424] Update INFINITE_LOOP control (#775)

* Use for loop instead of while loop for INFINITE_LOOP control
---
 tasks.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/tasks.c b/tasks.c
index 2786c5ab0..6cb233e7a 100644
--- a/tasks.c
+++ b/tasks.c
@@ -5118,7 +5118,7 @@ void vTaskMissedYield( void )
 
         taskYIELD();
 
-        while( INFINITE_LOOP() )
+        for( ; INFINITE_LOOP(); )
         {
             #if ( configUSE_PREEMPTION == 0 )
             {
@@ -5203,7 +5203,7 @@ static portTASK_FUNCTION( prvIdleTask, pvParameters )
     }
     #endif /* #if ( configNUMBER_OF_CORES > 1 ) */
 
-    while( INFINITE_LOOP() )
+    for( ; INFINITE_LOOP(); )
     {
         /* See if any tasks have deleted themselves - if so then the idle task
          * is responsible for freeing the deleted task's TCB and stack. */

From 231278ededca31af3658e2d23bc35bf86c5aff7a Mon Sep 17 00:00:00 2001
From: kar-rahul-aws <118818625+kar-rahul-aws@users.noreply.github.com>
Date: Mon, 4 Sep 2023 22:51:58 +0530
Subject: [PATCH 046/424] Fix cast alignment warning in heap_4.c and heap_5.c
 (#771)

* Fix cast alignment warning
---------

Co-authored-by: Soren Ptak <ptaksoren@gmail.com>
Co-authored-by: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
---
 portable/MemMang/heap_4.c | 9 +++------
 portable/MemMang/heap_5.c | 6 +++---
 2 files changed, 6 insertions(+), 9 deletions(-)

diff --git a/portable/MemMang/heap_4.c b/portable/MemMang/heap_4.c
index 59a1ce0be..6d1c6a8ee 100644
--- a/portable/MemMang/heap_4.c
+++ b/portable/MemMang/heap_4.c
@@ -444,7 +444,6 @@ void * pvPortCalloc( size_t xNum,
 static void prvHeapInit( void ) /* PRIVILEGED_FUNCTION */
 {
     BlockLink_t * pxFirstFreeBlock;
-    uint8_t * pucAlignedHeap;
     portPOINTER_SIZE_TYPE uxAddress;
     size_t xTotalHeapSize = configTOTAL_HEAP_SIZE;
 
@@ -458,8 +457,6 @@ static void prvHeapInit( void ) /* PRIVILEGED_FUNCTION */
         xTotalHeapSize -= ( size_t ) ( uxAddress - ( portPOINTER_SIZE_TYPE ) ucHeap );
     }
 
-    pucAlignedHeap = ( uint8_t * ) uxAddress;
-
     #if ( configENABLE_HEAP_PROTECTOR == 1 )
     {
         vApplicationGetRandomHeapCanary( &( xHeapCanary ) );
@@ -468,12 +465,12 @@ static void prvHeapInit( void ) /* PRIVILEGED_FUNCTION */
 
     /* xStart is used to hold a pointer to the first item in the list of free
      * blocks.  The void cast is used to prevent compiler warnings. */
-    xStart.pxNextFreeBlock = ( void * ) heapPROTECT_BLOCK_POINTER( pucAlignedHeap );
+    xStart.pxNextFreeBlock = ( void * ) heapPROTECT_BLOCK_POINTER( uxAddress );
     xStart.xBlockSize = ( size_t ) 0;
 
     /* pxEnd is used to mark the end of the list of free blocks and is inserted
      * at the end of the heap space. */
-    uxAddress = ( portPOINTER_SIZE_TYPE ) ( pucAlignedHeap + xTotalHeapSize );
+    uxAddress = ( portPOINTER_SIZE_TYPE ) ( uxAddress + xTotalHeapSize );
     uxAddress -= ( portPOINTER_SIZE_TYPE ) xHeapStructSize;
     uxAddress &= ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK );
     pxEnd = ( BlockLink_t * ) uxAddress;
@@ -482,7 +479,7 @@ static void prvHeapInit( void ) /* PRIVILEGED_FUNCTION */
 
     /* To start with there is a single free block that is sized to take up the
      * entire heap space, minus the space taken by pxEnd. */
-    pxFirstFreeBlock = ( BlockLink_t * ) pucAlignedHeap;
+    pxFirstFreeBlock = ( BlockLink_t * ) uxAddress;
     pxFirstFreeBlock->xBlockSize = ( size_t ) ( uxAddress - ( portPOINTER_SIZE_TYPE ) pxFirstFreeBlock );
     pxFirstFreeBlock->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( pxEnd );
 
diff --git a/portable/MemMang/heap_5.c b/portable/MemMang/heap_5.c
index a801298c1..5ced44e65 100644
--- a/portable/MemMang/heap_5.c
+++ b/portable/MemMang/heap_5.c
@@ -138,9 +138,9 @@
 
 #else /* if ( configENABLE_HEAP_PROTECTOR == 1 ) */
 
-    #define heapPROTECT_BLOCK_POINTER( pxBlock )     ( pxBlock )
+    #define heapPROTECT_BLOCK_POINTER( pxBlock )    ( pxBlock )
 
-    #define heapVALIDATE_BLOCK_POINTER( pxBlock )    ( pxBlock )
+    #define heapVALIDATE_BLOCK_POINTER( pxBlock )
 
 #endif /* configENABLE_HEAP_PROTECTOR */
 
@@ -562,7 +562,7 @@ void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions ) /* PRIVI
         if( ( xAddress & portBYTE_ALIGNMENT_MASK ) != 0 )
         {
             xAddress += ( portBYTE_ALIGNMENT - 1 );
-            xAddress &= ~portBYTE_ALIGNMENT_MASK;
+            xAddress &= ~( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK;
 
             /* Adjust the size for the bytes lost to alignment. */
             xTotalRegionSize -= ( size_t ) ( xAddress - ( portPOINTER_SIZE_TYPE ) pxHeapRegion->pucStartAddress );

From d6bccb1f4ca18e4e339696e780d18334e3462710 Mon Sep 17 00:00:00 2001
From: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Date: Tue, 5 Sep 2023 23:16:31 +0530
Subject: [PATCH 047/424] Fix heap address calculation issue (#781)

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 portable/MemMang/heap_4.c | 26 +++++++++++++-------------
 1 file changed, 13 insertions(+), 13 deletions(-)

diff --git a/portable/MemMang/heap_4.c b/portable/MemMang/heap_4.c
index 6d1c6a8ee..507bf48b9 100644
--- a/portable/MemMang/heap_4.c
+++ b/portable/MemMang/heap_4.c
@@ -444,17 +444,17 @@ void * pvPortCalloc( size_t xNum,
 static void prvHeapInit( void ) /* PRIVILEGED_FUNCTION */
 {
     BlockLink_t * pxFirstFreeBlock;
-    portPOINTER_SIZE_TYPE uxAddress;
+    portPOINTER_SIZE_TYPE uxStartAddress, uxEndAddress;
     size_t xTotalHeapSize = configTOTAL_HEAP_SIZE;
 
     /* Ensure the heap starts on a correctly aligned boundary. */
-    uxAddress = ( portPOINTER_SIZE_TYPE ) ucHeap;
+    uxStartAddress = ( portPOINTER_SIZE_TYPE ) ucHeap;
 
-    if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 )
+    if( ( uxStartAddress & portBYTE_ALIGNMENT_MASK ) != 0 )
     {
-        uxAddress += ( portBYTE_ALIGNMENT - 1 );
-        uxAddress &= ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK );
-        xTotalHeapSize -= ( size_t ) ( uxAddress - ( portPOINTER_SIZE_TYPE ) ucHeap );
+        uxStartAddress += ( portBYTE_ALIGNMENT - 1 );
+        uxStartAddress &= ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK );
+        xTotalHeapSize -= ( size_t ) ( uxStartAddress - ( portPOINTER_SIZE_TYPE ) ucHeap );
     }
 
     #if ( configENABLE_HEAP_PROTECTOR == 1 )
@@ -465,22 +465,22 @@ static void prvHeapInit( void ) /* PRIVILEGED_FUNCTION */
 
     /* xStart is used to hold a pointer to the first item in the list of free
      * blocks.  The void cast is used to prevent compiler warnings. */
-    xStart.pxNextFreeBlock = ( void * ) heapPROTECT_BLOCK_POINTER( uxAddress );
+    xStart.pxNextFreeBlock = ( void * ) heapPROTECT_BLOCK_POINTER( uxStartAddress );
     xStart.xBlockSize = ( size_t ) 0;
 
     /* pxEnd is used to mark the end of the list of free blocks and is inserted
      * at the end of the heap space. */
-    uxAddress = ( portPOINTER_SIZE_TYPE ) ( uxAddress + xTotalHeapSize );
-    uxAddress -= ( portPOINTER_SIZE_TYPE ) xHeapStructSize;
-    uxAddress &= ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK );
-    pxEnd = ( BlockLink_t * ) uxAddress;
+    uxEndAddress = uxStartAddress + ( portPOINTER_SIZE_TYPE ) xTotalHeapSize;
+    uxEndAddress -= ( portPOINTER_SIZE_TYPE ) xHeapStructSize;
+    uxEndAddress &= ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK );
+    pxEnd = ( BlockLink_t * ) uxEndAddress;
     pxEnd->xBlockSize = 0;
     pxEnd->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( NULL );
 
     /* To start with there is a single free block that is sized to take up the
      * entire heap space, minus the space taken by pxEnd. */
-    pxFirstFreeBlock = ( BlockLink_t * ) uxAddress;
-    pxFirstFreeBlock->xBlockSize = ( size_t ) ( uxAddress - ( portPOINTER_SIZE_TYPE ) pxFirstFreeBlock );
+    pxFirstFreeBlock = ( BlockLink_t * ) uxStartAddress;
+    pxFirstFreeBlock->xBlockSize = ( size_t ) ( uxEndAddress - ( portPOINTER_SIZE_TYPE ) pxFirstFreeBlock );
     pxFirstFreeBlock->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( pxEnd );
 
     /* Only one block exists - and it covers the entire usable heap space. */

From 5fb9b50da8f1e02fa0c81ee43d7961c479ef5f12 Mon Sep 17 00:00:00 2001
From: Soren Ptak <ptaksoren@gmail.com>
Date: Tue, 5 Sep 2023 17:24:04 -0400
Subject: [PATCH 048/424] CI-CD Updates (#768)

* Use new version of CI-CD Actions
* Use cSpell spell check, and use ubuntu-20.04 for formatting check
* Format and spell check all files in the portable directory
* Remove the https:// from #errors and #warnings as uncrustify attempts to change it to /*
* Use checkout@v3 instead of checkout@v2 on all jobs
---------
---
 .github/.cSpellWords.txt                      |   918 ++
 .github/lexicon.txt                           |  3165 -----
 .github/pull_request_process.md               |     2 +-
 .github/scripts/kernel_checker.py             |     8 +-
 .github/workflows/auto-release.yml            |     4 +-
 .github/workflows/ci.yml                      |   102 +-
 .github/workflows/git-secrets.yml             |     4 +-
 .github/workflows/kernel-checks.yml           |     4 +-
 .github/workflows/kernel-demos.yml            |    20 +-
 .github/workflows/unit-tests.yml              |     4 +-
 CMakeLists.txt                                |     2 +-
 README.md                                     |    63 +-
 cspell.config.yaml                            |    31 +
 portable/ARMv8M/ReadMe.txt                    |     2 +-
 portable/ARMv8M/non_secure/port.c             |  1076 +-
 .../GCC/ARM_CM23/mpu_wrappers_v2_asm.c        |  4246 +++---
 .../portable/GCC/ARM_CM23/portasm.c           |   934 +-
 .../portable/GCC/ARM_CM23/portmacro.h         |     6 +-
 .../GCC/ARM_CM23_NTZ/mpu_wrappers_v2_asm.c    |  4246 +++---
 .../portable/GCC/ARM_CM23_NTZ/portasm.c       |   756 +-
 .../portable/GCC/ARM_CM23_NTZ/portmacro.h     |     6 +-
 .../GCC/ARM_CM33/mpu_wrappers_v2_asm.c        |  4106 +++---
 .../portable/GCC/ARM_CM33/portasm.c           |   882 +-
 .../portable/GCC/ARM_CM33/portmacro.h         |    10 +-
 .../GCC/ARM_CM33_NTZ/mpu_wrappers_v2_asm.c    |  4106 +++---
 .../portable/GCC/ARM_CM33_NTZ/portasm.c       |   710 +-
 .../portable/GCC/ARM_CM33_NTZ/portmacro.h     |    10 +-
 .../portable/GCC/ARM_CM35P/portmacro.h        |    10 +-
 .../portable/GCC/ARM_CM55/portmacro.h         |    10 +-
 .../portable/GCC/ARM_CM85/portmacro.h         |    10 +-
 .../portable/IAR/ARM_CM23/portmacro.h         |     6 +-
 .../portable/IAR/ARM_CM23_NTZ/portmacro.h     |     6 +-
 .../portable/IAR/ARM_CM33/portmacro.h         |    12 +-
 .../portable/IAR/ARM_CM33_NTZ/portmacro.h     |    12 +-
 .../portable/IAR/ARM_CM35P/portmacro.h        |    12 +-
 .../portable/IAR/ARM_CM55/portmacro.h         |    12 +-
 .../portable/IAR/ARM_CM85/portmacro.h         |    12 +-
 portable/ARMv8M/non_secure/portmacrocommon.h  |   222 +-
 .../ARMv8M/secure/context/secure_context.c    |    87 +-
 .../ARMv8M/secure/context/secure_context.h    |    13 +-
 portable/ARMv8M/secure/heap/secure_heap.c     |    20 +-
 portable/ARMv8M/secure/init/secure_init.c     |     2 +-
 portable/BCC/16BitDOS/Flsh186/port.c          |   103 +-
 portable/BCC/16BitDOS/Flsh186/prtmacro.h      |    67 +-
 portable/BCC/16BitDOS/PC/port.c               |   121 +-
 portable/BCC/16BitDOS/PC/prtmacro.h           |    67 +-
 portable/BCC/16BitDOS/common/portasm.h        |    66 +-
 portable/BCC/16BitDOS/common/portcomn.c       |    42 +-
 portable/CCS/ARM_CM3/port.c                   |    32 +-
 portable/CCS/ARM_CM3/portmacro.h              |   128 +-
 portable/CCS/ARM_CM4F/port.c                  |    32 +-
 portable/CCS/ARM_CM4F/portmacro.h             |   126 +-
 portable/CCS/ARM_Cortex-R4/port.c             |   108 +-
 portable/CCS/ARM_Cortex-R4/portmacro.h        |    80 +-
 portable/CCS/MSP430X/data_model.h             |    96 +-
 portable/CCS/MSP430X/port.c                   |    68 +-
 portable/CCS/MSP430X/portmacro.h              |   110 +-
 portable/CodeWarrior/ColdFire_V1/port.c       |    41 +-
 portable/CodeWarrior/ColdFire_V1/portmacro.h  |    54 +-
 portable/CodeWarrior/ColdFire_V2/port.c       |    50 +-
 portable/CodeWarrior/ColdFire_V2/portmacro.h  |    54 +-
 portable/CodeWarrior/HCS12/port.c             |    90 +-
 portable/CodeWarrior/HCS12/portmacro.h        |   201 +-
 portable/GCC/ARM7_AT91FR40008/port.c          |   110 +-
 portable/GCC/ARM7_AT91FR40008/portISR.c       |   114 +-
 portable/GCC/ARM7_AT91FR40008/portmacro.h     |   284 +-
 portable/GCC/ARM7_AT91SAM7S/AT91SAM7X256.h    |  5354 ++++----
 portable/GCC/ARM7_AT91SAM7S/ioat91sam7x256.h  | 10993 +++++++++-------
 .../GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.c     |    90 +-
 .../GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.h     |  2851 ++--
 portable/GCC/ARM7_AT91SAM7S/port.c            |   110 +-
 portable/GCC/ARM7_AT91SAM7S/portISR.c         |   114 +-
 portable/GCC/ARM7_AT91SAM7S/portmacro.h       |   284 +-
 portable/GCC/ARM7_LPC2000/port.c              |   101 +-
 portable/GCC/ARM7_LPC2000/portISR.c           |   120 +-
 portable/GCC/ARM7_LPC2000/portmacro.h         |   242 +-
 portable/GCC/ARM7_LPC23xx/port.c              |   110 +-
 portable/GCC/ARM7_LPC23xx/portISR.c           |   104 +-
 portable/GCC/ARM7_LPC23xx/portmacro.h         |   284 +-
 portable/GCC/ARM_CA53_64_BIT/port.c           |   314 +-
 portable/GCC/ARM_CA53_64_BIT/portmacro.h      |   175 +-
 portable/GCC/ARM_CA53_64_BIT_SRE/port.c       |   267 +-
 portable/GCC/ARM_CA53_64_BIT_SRE/portmacro.h  |   151 +-
 portable/GCC/ARM_CA9/port.c                   |   339 +-
 portable/GCC/ARM_CA9/portmacro.h              |   175 +-
 portable/GCC/ARM_CM0/port.c                   |    46 +-
 portable/GCC/ARM_CM0/portmacro.h              |     6 +-
 .../ARM_CM23/non_secure/mpu_wrappers_v2_asm.c |  4246 +++---
 portable/GCC/ARM_CM23/non_secure/port.c       |  1076 +-
 portable/GCC/ARM_CM23/non_secure/portasm.c    |   934 +-
 portable/GCC/ARM_CM23/non_secure/portmacro.h  |     6 +-
 .../GCC/ARM_CM23/non_secure/portmacrocommon.h |   222 +-
 portable/GCC/ARM_CM23/secure/secure_context.c |    87 +-
 portable/GCC/ARM_CM23/secure/secure_context.h |    13 +-
 portable/GCC/ARM_CM23/secure/secure_heap.c    |    20 +-
 portable/GCC/ARM_CM23/secure/secure_init.c    |     2 +-
 .../non_secure/mpu_wrappers_v2_asm.c          |  4246 +++---
 portable/GCC/ARM_CM23_NTZ/non_secure/port.c   |  1076 +-
 .../GCC/ARM_CM23_NTZ/non_secure/portasm.c     |   756 +-
 .../GCC/ARM_CM23_NTZ/non_secure/portmacro.h   |     6 +-
 .../ARM_CM23_NTZ/non_secure/portmacrocommon.h |   222 +-
 portable/GCC/ARM_CM3/port.c                   |    64 +-
 portable/GCC/ARM_CM3/portmacro.h              |   252 +-
 .../ARM_CM33/non_secure/mpu_wrappers_v2_asm.c |  4106 +++---
 portable/GCC/ARM_CM33/non_secure/port.c       |  1076 +-
 portable/GCC/ARM_CM33/non_secure/portasm.c    |   882 +-
 portable/GCC/ARM_CM33/non_secure/portmacro.h  |    10 +-
 .../GCC/ARM_CM33/non_secure/portmacrocommon.h |   222 +-
 portable/GCC/ARM_CM33/secure/secure_context.c |    87 +-
 portable/GCC/ARM_CM33/secure/secure_context.h |    13 +-
 portable/GCC/ARM_CM33/secure/secure_heap.c    |    20 +-
 portable/GCC/ARM_CM33/secure/secure_init.c    |     2 +-
 .../non_secure/mpu_wrappers_v2_asm.c          |  4106 +++---
 portable/GCC/ARM_CM33_NTZ/non_secure/port.c   |  1076 +-
 .../GCC/ARM_CM33_NTZ/non_secure/portasm.c     |   710 +-
 .../GCC/ARM_CM33_NTZ/non_secure/portmacro.h   |    10 +-
 .../ARM_CM33_NTZ/non_secure/portmacrocommon.h |   222 +-
 .../non_secure/mpu_wrappers_v2_asm.c          |  4106 +++---
 portable/GCC/ARM_CM35P/non_secure/port.c      |  1076 +-
 portable/GCC/ARM_CM35P/non_secure/portasm.c   |   882 +-
 portable/GCC/ARM_CM35P/non_secure/portmacro.h |    10 +-
 .../ARM_CM35P/non_secure/portmacrocommon.h    |   222 +-
 .../GCC/ARM_CM35P/secure/secure_context.c     |    87 +-
 .../GCC/ARM_CM35P/secure/secure_context.h     |    13 +-
 portable/GCC/ARM_CM35P/secure/secure_heap.c   |    20 +-
 portable/GCC/ARM_CM35P/secure/secure_init.c   |     2 +-
 .../non_secure/mpu_wrappers_v2_asm.c          |  4106 +++---
 portable/GCC/ARM_CM35P_NTZ/non_secure/port.c  |  1076 +-
 .../GCC/ARM_CM35P_NTZ/non_secure/portasm.c    |   710 +-
 .../GCC/ARM_CM35P_NTZ/non_secure/portmacro.h  |    10 +-
 .../non_secure/portmacrocommon.h              |   222 +-
 .../GCC/ARM_CM3_MPU/mpu_wrappers_v2_asm.c     |  4106 +++---
 portable/GCC/ARM_CM3_MPU/port.c               |   898 +-
 portable/GCC/ARM_CM3_MPU/portmacro.h          |   402 +-
 portable/GCC/ARM_CM4F/port.c                  |    32 +-
 portable/GCC/ARM_CM4F/portmacro.h             |   252 +-
 .../GCC/ARM_CM4_MPU/mpu_wrappers_v2_asm.c     |  4106 +++---
 portable/GCC/ARM_CM4_MPU/port.c               |  1075 +-
 portable/GCC/ARM_CM4_MPU/portmacro.h          |    50 +-
 .../ARM_CM55/non_secure/mpu_wrappers_v2_asm.c |  4106 +++---
 portable/GCC/ARM_CM55/non_secure/port.c       |  1076 +-
 portable/GCC/ARM_CM55/non_secure/portasm.c    |   882 +-
 portable/GCC/ARM_CM55/non_secure/portmacro.h  |    10 +-
 .../GCC/ARM_CM55/non_secure/portmacrocommon.h |   222 +-
 portable/GCC/ARM_CM55/secure/secure_context.c |    87 +-
 portable/GCC/ARM_CM55/secure/secure_context.h |    13 +-
 portable/GCC/ARM_CM55/secure/secure_heap.c    |    20 +-
 portable/GCC/ARM_CM55/secure/secure_init.c    |     2 +-
 .../non_secure/mpu_wrappers_v2_asm.c          |  4106 +++---
 portable/GCC/ARM_CM55_NTZ/non_secure/port.c   |  1076 +-
 .../GCC/ARM_CM55_NTZ/non_secure/portasm.c     |   710 +-
 .../GCC/ARM_CM55_NTZ/non_secure/portmacro.h   |    10 +-
 .../ARM_CM55_NTZ/non_secure/portmacrocommon.h |   222 +-
 portable/GCC/ARM_CM7/r0p1/port.c              |    32 +-
 portable/GCC/ARM_CM7/r0p1/portmacro.h         |   254 +-
 .../ARM_CM85/non_secure/mpu_wrappers_v2_asm.c |  4106 +++---
 portable/GCC/ARM_CM85/non_secure/port.c       |  1076 +-
 portable/GCC/ARM_CM85/non_secure/portasm.c    |   882 +-
 portable/GCC/ARM_CM85/non_secure/portmacro.h  |    10 +-
 .../GCC/ARM_CM85/non_secure/portmacrocommon.h |   222 +-
 portable/GCC/ARM_CM85/secure/secure_context.c |    87 +-
 portable/GCC/ARM_CM85/secure/secure_context.h |    13 +-
 portable/GCC/ARM_CM85/secure/secure_heap.c    |    20 +-
 portable/GCC/ARM_CM85/secure/secure_init.c    |     2 +-
 .../non_secure/mpu_wrappers_v2_asm.c          |  4106 +++---
 portable/GCC/ARM_CM85_NTZ/non_secure/port.c   |  1076 +-
 .../GCC/ARM_CM85_NTZ/non_secure/portasm.c     |   710 +-
 .../GCC/ARM_CM85_NTZ/non_secure/portmacro.h   |    10 +-
 .../ARM_CM85_NTZ/non_secure/portmacrocommon.h |   222 +-
 portable/GCC/ARM_CR5/port.c                   |     8 +-
 portable/GCC/ARM_CRx_No_GIC/port.c            |   158 +-
 portable/GCC/ARM_CRx_No_GIC/portmacro.h       |   125 +-
 portable/GCC/ATMega323/port.c                 |   319 +-
 portable/GCC/ATMega323/portmacro.h            |    72 +-
 portable/GCC/AVR32_UC3/port.c                 |   261 +-
 portable/GCC/AVR32_UC3/portmacro.h            |   930 +-
 portable/GCC/CORTUS_APS3/port.c               |    14 +-
 portable/GCC/CORTUS_APS3/portmacro.h          |   122 +-
 portable/GCC/ColdFire_V2/port.c               |    30 +-
 portable/GCC/ColdFire_V2/portmacro.h          |    54 +-
 portable/GCC/H8S2329/port.c                   |    91 +-
 portable/GCC/H8S2329/portmacro.h              |   107 +-
 portable/GCC/HCS12/port.c                     |    82 +-
 portable/GCC/HCS12/portmacro.h                |   163 +-
 portable/GCC/IA32_flat/ISR_Support.h          |   145 +-
 portable/GCC/IA32_flat/port.c                 |   243 +-
 portable/GCC/IA32_flat/portmacro.h            |   259 +-
 portable/GCC/MSP430F449/port.c                |   207 +-
 portable/GCC/MSP430F449/portmacro.h           |   106 +-
 portable/GCC/MicroBlaze/port.c                |   172 +-
 portable/GCC/MicroBlaze/portmacro.h           |    90 +-
 portable/GCC/MicroBlazeV8/port.c              |   229 +-
 portable/GCC/MicroBlazeV8/port_exceptions.c   |   354 +-
 portable/GCC/MicroBlazeV8/portmacro.h         |   150 +-
 portable/GCC/MicroBlazeV9/port.c              |   206 +-
 portable/GCC/MicroBlazeV9/port_exceptions.c   |   354 +-
 portable/GCC/MicroBlazeV9/portmacro.h         |   154 +-
 portable/GCC/NiosII/port.c                    |    62 +-
 portable/GCC/NiosII/portmacro.h               |    54 +-
 portable/GCC/PPC405_Xilinx/FPU_Macros.h       |    14 +-
 portable/GCC/PPC405_Xilinx/port.c             |    82 +-
 portable/GCC/PPC405_Xilinx/portmacro.h        |    66 +-
 portable/GCC/PPC440_Xilinx/FPU_Macros.h       |    14 +-
 portable/GCC/PPC440_Xilinx/port.c             |    82 +-
 portable/GCC/PPC440_Xilinx/portmacro.h        |    66 +-
 ...freertos_risc_v_chip_specific_extensions.h |    74 +-
 ...freertos_risc_v_chip_specific_extensions.h |    16 +-
 ...freertos_risc_v_chip_specific_extensions.h |    16 +-
 ...freertos_risc_v_chip_specific_extensions.h |    16 +-
 portable/GCC/RISC-V/port.c                    |    73 +-
 portable/GCC/RISC-V/portContext.h             |   198 +-
 portable/GCC/RISC-V/portmacro.h               |   152 +-
 portable/GCC/RL78/isr_support.h               |   157 +-
 portable/GCC/RL78/port.c                      |    58 +-
 portable/GCC/RL78/portmacro.h                 |   112 +-
 portable/GCC/RX100/port.c                     |   236 +-
 portable/GCC/RX100/portmacro.h                |   109 +-
 portable/GCC/RX200/port.c                     |    77 +-
 portable/GCC/RX200/portmacro.h                |   110 +-
 portable/GCC/RX600/port.c                     |    78 +-
 portable/GCC/RX600/portmacro.h                |   110 +-
 portable/GCC/RX600v2/port.c                   |    83 +-
 portable/GCC/RX600v2/portmacro.h              |   110 +-
 portable/GCC/RX700v3_DPFPU/port.c             |   421 +-
 portable/GCC/RX700v3_DPFPU/portmacro.h        |   141 +-
 portable/GCC/STR75x/port.c                    |    82 +-
 portable/GCC/STR75x/portISR.c                 |   124 +-
 portable/GCC/STR75x/portmacro.h               |    99 +-
 portable/GCC/TriCore_1782/port.c              |   283 +-
 portable/GCC/TriCore_1782/portmacro.h         |   144 +-
 portable/GCC/TriCore_1782/porttrap.c          |   116 +-
 portable/IAR/78K0R/ISR_Support.h              |   179 +-
 portable/IAR/78K0R/port.c                     |    62 +-
 portable/IAR/78K0R/portmacro.h                |   128 +-
 portable/IAR/ARM_CA5_No_GIC/port.c            |   140 +-
 portable/IAR/ARM_CA5_No_GIC/portASM.h         |   221 +-
 portable/IAR/ARM_CA5_No_GIC/portmacro.h       |   148 +-
 portable/IAR/ARM_CA9/port.c                   |   256 +-
 portable/IAR/ARM_CA9/portASM.h                |   227 +-
 portable/IAR/ARM_CA9/portmacro.h              |   208 +-
 portable/IAR/ARM_CM23/non_secure/port.c       |  1076 +-
 portable/IAR/ARM_CM23/non_secure/portmacro.h  |     6 +-
 .../IAR/ARM_CM23/non_secure/portmacrocommon.h |   222 +-
 portable/IAR/ARM_CM23/secure/secure_context.c |    87 +-
 portable/IAR/ARM_CM23/secure/secure_context.h |    13 +-
 portable/IAR/ARM_CM23/secure/secure_heap.c    |    20 +-
 portable/IAR/ARM_CM23/secure/secure_init.c    |     2 +-
 portable/IAR/ARM_CM23_NTZ/non_secure/port.c   |  1076 +-
 .../IAR/ARM_CM23_NTZ/non_secure/portmacro.h   |     6 +-
 .../ARM_CM23_NTZ/non_secure/portmacrocommon.h |   222 +-
 portable/IAR/ARM_CM3/port.c                   |    32 +-
 portable/IAR/ARM_CM3/portmacro.h              |   168 +-
 portable/IAR/ARM_CM33/non_secure/port.c       |  1076 +-
 portable/IAR/ARM_CM33/non_secure/portmacro.h  |    12 +-
 .../IAR/ARM_CM33/non_secure/portmacrocommon.h |   222 +-
 portable/IAR/ARM_CM33/secure/secure_context.c |    87 +-
 portable/IAR/ARM_CM33/secure/secure_context.h |    13 +-
 portable/IAR/ARM_CM33/secure/secure_heap.c    |    20 +-
 portable/IAR/ARM_CM33/secure/secure_init.c    |     2 +-
 portable/IAR/ARM_CM33_NTZ/non_secure/port.c   |  1076 +-
 .../IAR/ARM_CM33_NTZ/non_secure/portmacro.h   |    12 +-
 .../ARM_CM33_NTZ/non_secure/portmacrocommon.h |   222 +-
 portable/IAR/ARM_CM35P/non_secure/port.c      |  1076 +-
 portable/IAR/ARM_CM35P/non_secure/portmacro.h |    12 +-
 .../ARM_CM35P/non_secure/portmacrocommon.h    |   222 +-
 .../IAR/ARM_CM35P/secure/secure_context.c     |    87 +-
 .../IAR/ARM_CM35P/secure/secure_context.h     |    13 +-
 portable/IAR/ARM_CM35P/secure/secure_heap.c   |    20 +-
 portable/IAR/ARM_CM35P/secure/secure_init.c   |     2 +-
 portable/IAR/ARM_CM35P_NTZ/non_secure/port.c  |  1076 +-
 .../IAR/ARM_CM35P_NTZ/non_secure/portmacro.h  |    12 +-
 .../non_secure/portmacrocommon.h              |   222 +-
 portable/IAR/ARM_CM4F/port.c                  |    32 +-
 portable/IAR/ARM_CM4F/portmacro.h             |   168 +-
 portable/IAR/ARM_CM4F_MPU/port.c              |   652 +-
 portable/IAR/ARM_CM4F_MPU/portmacro.h         |    68 +-
 portable/IAR/ARM_CM55/non_secure/port.c       |  1076 +-
 portable/IAR/ARM_CM55/non_secure/portmacro.h  |    12 +-
 .../IAR/ARM_CM55/non_secure/portmacrocommon.h |   222 +-
 portable/IAR/ARM_CM55/secure/secure_context.c |    87 +-
 portable/IAR/ARM_CM55/secure/secure_context.h |    13 +-
 portable/IAR/ARM_CM55/secure/secure_heap.c    |    20 +-
 portable/IAR/ARM_CM55/secure/secure_init.c    |     2 +-
 portable/IAR/ARM_CM55_NTZ/non_secure/port.c   |  1076 +-
 .../IAR/ARM_CM55_NTZ/non_secure/portmacro.h   |    12 +-
 .../ARM_CM55_NTZ/non_secure/portmacrocommon.h |   222 +-
 portable/IAR/ARM_CM7/r0p1/port.c              |    32 +-
 portable/IAR/ARM_CM7/r0p1/portmacro.h         |   168 +-
 portable/IAR/ARM_CM85/non_secure/port.c       |  1076 +-
 portable/IAR/ARM_CM85/non_secure/portmacro.h  |    12 +-
 .../IAR/ARM_CM85/non_secure/portmacrocommon.h |   222 +-
 portable/IAR/ARM_CM85/secure/secure_context.c |    87 +-
 portable/IAR/ARM_CM85/secure/secure_context.h |    13 +-
 portable/IAR/ARM_CM85/secure/secure_heap.c    |    20 +-
 portable/IAR/ARM_CM85/secure/secure_init.c    |     2 +-
 portable/IAR/ARM_CM85_NTZ/non_secure/port.c   |  1076 +-
 .../IAR/ARM_CM85_NTZ/non_secure/portmacro.h   |    12 +-
 .../ARM_CM85_NTZ/non_secure/portmacrocommon.h |   222 +-
 portable/IAR/ARM_CRx_No_GIC/port.c            |   154 +-
 portable/IAR/ARM_CRx_No_GIC/portmacro.h       |   125 +-
 portable/IAR/ATMega323/port.c                 |   168 +-
 portable/IAR/ATMega323/portmacro.h            |    66 +-
 portable/IAR/AVR32_UC3/port.c                 |   251 +-
 portable/IAR/AVR32_UC3/portmacro.h            |   898 +-
 portable/IAR/AVR32_UC3/read.c                 |    68 +-
 portable/IAR/AVR32_UC3/write.c                |    77 +-
 portable/IAR/AVR_AVRDx/portmacro.h            |     4 +-
 portable/IAR/AVR_Mega0/portmacro.h            |     4 +-
 portable/IAR/AtmelSAM7S64/AT91SAM7S64.h       |  3742 +++---
 portable/IAR/AtmelSAM7S64/AT91SAM7S64_inc.h   |  3564 ++---
 portable/IAR/AtmelSAM7S64/AT91SAM7X128.h      |  5326 ++++----
 portable/IAR/AtmelSAM7S64/AT91SAM7X128_inc.h  |  4820 +++----
 portable/IAR/AtmelSAM7S64/AT91SAM7X256.h      |  5326 ++++----
 portable/IAR/AtmelSAM7S64/AT91SAM7X256_inc.h  |  4820 +++----
 portable/IAR/AtmelSAM7S64/ISR_Support.h       |   208 +-
 portable/IAR/AtmelSAM7S64/lib_AT91SAM7S64.h   |  4372 +++---
 portable/IAR/AtmelSAM7S64/lib_AT91SAM7X128.h  |  2851 ++--
 portable/IAR/AtmelSAM7S64/lib_AT91SAM7X256.h  |  2851 ++--
 portable/IAR/AtmelSAM7S64/port.c              |   118 +-
 portable/IAR/AtmelSAM7S64/portmacro.h         |    62 +-
 portable/IAR/AtmelSAM9XE/ISR_Support.h        |   208 +-
 portable/IAR/AtmelSAM9XE/port.c               |    94 +-
 portable/IAR/AtmelSAM9XE/portmacro.h          |    62 +-
 portable/IAR/LPC2000/ISR_Support.h            |   208 +-
 portable/IAR/LPC2000/port.c                   |   150 +-
 portable/IAR/LPC2000/portmacro.h              |    62 +-
 portable/IAR/MSP430/port.c                    |    65 +-
 portable/IAR/MSP430/portasm.h                 |    86 +-
 portable/IAR/MSP430/portmacro.h               |   106 +-
 portable/IAR/MSP430X/data_model.h             |    36 +-
 portable/IAR/MSP430X/port.c                   |    71 +-
 portable/IAR/MSP430X/portmacro.h              |   112 +-
 ...freertos_risc_v_chip_specific_extensions.h |    12 +-
 portable/IAR/RISC-V/port.c                    |    14 +-
 portable/IAR/RISC-V/portContext.h             |   192 +-
 portable/IAR/RISC-V/portmacro.h               |   136 +-
 portable/IAR/RL78/port.c                      |    77 +-
 portable/IAR/RL78/portmacro.h                 |   278 +-
 portable/IAR/RX100/port.c                     |   183 +-
 portable/IAR/RX100/portmacro.h                |    92 +-
 portable/IAR/RX600/port.c                     |    32 +-
 portable/IAR/RX600/portmacro.h                |   108 +-
 portable/IAR/RX700v3_DPFPU/port.c             |   403 +-
 portable/IAR/RX700v3_DPFPU/portmacro.h        |   145 +-
 portable/IAR/RXv2/port.c                      |    32 +-
 portable/IAR/RXv2/portmacro.h                 |   112 +-
 portable/IAR/STR71x/ISR_Support.h             |   208 +-
 portable/IAR/STR71x/port.c                    |    94 +-
 portable/IAR/STR71x/portmacro.h               |    68 +-
 portable/IAR/STR75x/ISR_Support.h             |   208 +-
 portable/IAR/STR75x/port.c                    |    92 +-
 portable/IAR/STR75x/portmacro.h               |    62 +-
 portable/IAR/STR91x/ISR_Support.h             |   154 +-
 portable/IAR/STR91x/port.c                    |   206 +-
 portable/IAR/STR91x/portmacro.h               |    62 +-
 portable/IAR/V850ES/ISR_Support.h             |   241 +-
 portable/IAR/V850ES/port.c                    |   110 +-
 portable/IAR/V850ES/portmacro.h               |    98 +-
 portable/MPLAB/PIC18F/port.c                  |   514 +-
 portable/MPLAB/PIC18F/portmacro.h             |    77 +-
 portable/MPLAB/PIC24_dsPIC/port.c             |   261 +-
 portable/MPLAB/PIC24_dsPIC/portmacro.h        |    64 +-
 portable/MPLAB/PIC32MEC14xx/ISR_Support.h     |   278 +-
 portable/MPLAB/PIC32MEC14xx/port.c            |   198 +-
 portable/MPLAB/PIC32MEC14xx/portmacro.h       |   203 +-
 portable/MPLAB/PIC32MX/ISR_Support.h          |   271 +-
 portable/MPLAB/PIC32MX/port.c                 |   178 +-
 portable/MPLAB/PIC32MX/portmacro.h            |   172 +-
 portable/MPLAB/PIC32MZ/ISR_Support.h          |   737 +-
 portable/MPLAB/PIC32MZ/port.c                 |   210 +-
 portable/MPLAB/PIC32MZ/portmacro.h            |   177 +-
 portable/MSVC-MingW/port.c                    |   347 +-
 portable/MSVC-MingW/portmacro.h               |   129 +-
 portable/MemMang/heap_5.c                     |     2 +-
 portable/MikroC/ARM_CM4F/port.c               |    32 +-
 portable/MikroC/ARM_CM4F/portmacro.h          |   182 +-
 .../Paradigm/Tern_EE/large_untested/port.c    |    84 +-
 .../Paradigm/Tern_EE/large_untested/portasm.h |    56 +-
 .../Tern_EE/large_untested/portmacro.h        |    67 +-
 portable/Paradigm/Tern_EE/small/port.c        |    78 +-
 portable/Paradigm/Tern_EE/small/portasm.h     |    40 +-
 portable/Paradigm/Tern_EE/small/portmacro.h   |    69 +-
 portable/RVDS/ARM7_LPC21xx/port.c             |   152 +-
 portable/RVDS/ARM7_LPC21xx/portmacro.h        |    88 +-
 portable/RVDS/ARM_CA9/port.c                  |   309 +-
 portable/RVDS/ARM_CA9/portmacro.h             |   116 +-
 portable/RVDS/ARM_CM0/portmacro.h             |     6 +-
 portable/RVDS/ARM_CM3/port.c                  |    32 +-
 portable/RVDS/ARM_CM3/portmacro.h             |   226 +-
 portable/RVDS/ARM_CM4F/port.c                 |    32 +-
 portable/RVDS/ARM_CM4F/portmacro.h            |   226 +-
 .../RVDS/ARM_CM4_MPU/mpu_wrappers_v2_asm.c    |  3590 ++---
 portable/RVDS/ARM_CM4_MPU/port.c              |   623 +-
 portable/RVDS/ARM_CM4_MPU/portmacro.h         |    40 +-
 portable/RVDS/ARM_CM7/r0p1/port.c             |    32 +-
 portable/RVDS/ARM_CM7/r0p1/portmacro.h        |   226 +-
 portable/Renesas/RX100/port.c                 |   294 +-
 portable/Renesas/RX100/portmacro.h            |   100 +-
 portable/Renesas/RX200/port.c                 |   147 +-
 portable/Renesas/RX200/portmacro.h            |    98 +-
 portable/Renesas/RX600/port.c                 |   153 +-
 portable/Renesas/RX600/portmacro.h            |    98 +-
 portable/Renesas/RX600v2/port.c               |   205 +-
 portable/Renesas/RX600v2/portmacro.h          |    98 +-
 portable/Renesas/RX700v3_DPFPU/port.c         |   570 +-
 portable/Renesas/RX700v3_DPFPU/portmacro.h    |   132 +-
 portable/Renesas/SH2A_FPU/port.c              |    70 +-
 portable/Renesas/SH2A_FPU/portmacro.h         |    72 +-
 portable/Rowley/MSP430F449/port.c             |    65 +-
 portable/Rowley/MSP430F449/portasm.h          |    82 +-
 portable/Rowley/MSP430F449/portmacro.h        |   104 +-
 portable/SDCC/Cygnal/port.c                   |   541 +-
 portable/SDCC/Cygnal/portmacro.h              |    77 +-
 portable/Softune/MB91460/__STD_LIB_sbrk.c     |    33 +-
 portable/Softune/MB91460/port.c               |    98 +-
 portable/Softune/MB91460/portmacro.h          |    62 +-
 portable/Softune/MB96340/__STD_LIB_sbrk.c     |    33 +-
 portable/Softune/MB96340/port.c               |   370 +-
 portable/Softune/MB96340/portmacro.h          |    76 +-
 portable/Tasking/ARM_CM4F/port.c              |    30 +-
 portable/Tasking/ARM_CM4F/portmacro.h         |    90 +-
 portable/ThirdParty/CDK/T-HEAD_CK802/port.c   |   107 +-
 .../ThirdParty/CDK/T-HEAD_CK802/portmacro.h   |   115 +-
 portable/ThirdParty/GCC/ARC_EM_HS/portmacro.h |    14 +-
 portable/ThirdParty/GCC/ARC_v1/port.c         |    14 +-
 portable/ThirdParty/GCC/ARC_v1/portmacro.h    |   122 +-
 portable/ThirdParty/GCC/ARM_TFM/README.md     |     2 +-
 .../GCC/ARM_TFM/os_wrapper_freertos.c         |    44 +-
 portable/ThirdParty/GCC/ATmega/port.c         |   997 +-
 portable/ThirdParty/GCC/ATmega/portmacro.h    |   102 +-
 portable/ThirdParty/GCC/Posix/port.c          |    15 +-
 portable/ThirdParty/GCC/Posix/portmacro.h     |    79 +-
 .../GCC/Posix/utils/wait_for_event.c          |     4 +-
 portable/ThirdParty/GCC/RP2040/README.md      |    14 +-
 .../GCC/RP2040/idle_task_static_memory.c      |    16 +-
 .../GCC/RP2040/include/freertos_sdk_config.h  |    40 +-
 .../ThirdParty/GCC/RP2040/include/portmacro.h |   315 +-
 .../GCC/RP2040/include/rp2040_config.h        |    21 +-
 portable/ThirdParty/GCC/RP2040/port.c         |   653 +-
 .../include/FreeRTOSConfig_arch.h             |    87 +-
 .../GCC/Xtensa_ESP32/include/port_systick.h   |     2 +-
 .../GCC/Xtensa_ESP32/include/portbenchmark.h  |     1 +
 .../GCC/Xtensa_ESP32/include/portmacro.h      |   151 +-
 .../GCC/Xtensa_ESP32/include/xt_asm_utils.h   |    12 +-
 .../GCC/Xtensa_ESP32/include/xtensa_api.h     |     1 +
 .../GCC/Xtensa_ESP32/include/xtensa_config.h  |    53 +-
 .../GCC/Xtensa_ESP32/include/xtensa_context.h |     1 +
 .../GCC/Xtensa_ESP32/include/xtensa_rtos.h    |     6 +-
 .../GCC/Xtensa_ESP32/include/xtensa_timer.h   |     1 +
 portable/ThirdParty/GCC/Xtensa_ESP32/port.c   |   162 +-
 .../ThirdParty/GCC/Xtensa_ESP32/port_common.c |   180 +-
 .../GCC/Xtensa_ESP32/port_systick.c           |   206 +-
 .../GCC/Xtensa_ESP32/portmux_impl.h           |     6 +-
 .../GCC/Xtensa_ESP32/portmux_impl.inc.h       |    20 +-
 .../ThirdParty/GCC/Xtensa_ESP32/xtensa_init.c |    39 +-
 .../GCC/Xtensa_ESP32/xtensa_overlay_os_hook.c |     1 +
 portable/ThirdParty/XCC/Xtensa/port.c         |    67 +-
 .../ThirdParty/XCC/Xtensa/portbenchmark.h     |     2 +-
 portable/ThirdParty/XCC/Xtensa/portclib.c     |   326 +-
 portable/ThirdParty/XCC/Xtensa/portmacro.h    |   236 +-
 portable/ThirdParty/XCC/Xtensa/porttrace.h    |     6 +-
 portable/ThirdParty/XCC/Xtensa/xtensa_api.h   |   121 +-
 .../ThirdParty/XCC/Xtensa/xtensa_config.h     |   212 +-
 .../ThirdParty/XCC/Xtensa/xtensa_context.h    |   478 +-
 portable/ThirdParty/XCC/Xtensa/xtensa_init.c  |    42 +-
 portable/ThirdParty/XCC/Xtensa/xtensa_intr.c  |   141 +-
 .../XCC/Xtensa/xtensa_overlay_os_hook.c       |    36 +-
 portable/ThirdParty/XCC/Xtensa/xtensa_rtos.h  |   232 +-
 portable/ThirdParty/XCC/Xtensa/xtensa_timer.h |   160 +-
 portable/ThirdParty/xClang/XCOREAI/port.c     |   310 +-
 .../ThirdParty/xClang/XCOREAI/portmacro.h     |   229 +-
 .../xClang/XCOREAI/rtos_support_rtos_config.h |    74 +-
 portable/WizC/PIC18/Drivers/Tick/Tick.c       |    84 +-
 portable/WizC/PIC18/Drivers/Tick/isrTick.c    |    24 +-
 portable/WizC/PIC18/addFreeRTOS.h             |    16 +-
 portable/WizC/PIC18/port.c                    |   134 +-
 portable/WizC/PIC18/portmacro.h               |   543 +-
 portable/oWatcom/16BitDOS/Flsh186/port.c      |   101 +-
 portable/oWatcom/16BitDOS/Flsh186/portmacro.h |    58 +-
 portable/oWatcom/16BitDOS/PC/port.c           |   140 +-
 portable/oWatcom/16BitDOS/PC/portmacro.h      |    60 +-
 portable/oWatcom/16BitDOS/common/portasm.h    |   106 +-
 portable/oWatcom/16BitDOS/common/portcomn.c   |    79 +-
 queue.c                                       |     0
 timers.c                                      |     2 +-
 485 files changed, 108790 insertions(+), 107581 deletions(-)
 create mode 100644 .github/.cSpellWords.txt
 delete mode 100644 .github/lexicon.txt
 create mode 100644 cspell.config.yaml
 mode change 100755 => 100644 portable/CCS/ARM_CM3/port.c
 mode change 100755 => 100644 portable/CCS/ARM_CM4F/port.c
 mode change 100755 => 100644 portable/GCC/ARM_CM7/r0p1/port.c
 mode change 100755 => 100644 portable/IAR/ARM_CM3/port.c
 mode change 100755 => 100644 portable/IAR/ARM_CM4F/port.c
 mode change 100755 => 100644 portable/IAR/ARM_CM4F_MPU/port.c
 mode change 100755 => 100644 portable/IAR/ARM_CM7/r0p1/port.c
 mode change 100755 => 100644 portable/MikroC/ARM_CM4F/port.c
 mode change 100755 => 100644 portable/RVDS/ARM_CM3/port.c
 mode change 100755 => 100644 portable/RVDS/ARM_CM4F/port.c
 mode change 100755 => 100644 portable/RVDS/ARM_CM4_MPU/port.c
 mode change 100755 => 100644 portable/RVDS/ARM_CM7/r0p1/port.c
 mode change 100755 => 100644 portable/Tasking/ARM_CM4F/port.c
 mode change 100755 => 100644 queue.c

diff --git a/.github/.cSpellWords.txt b/.github/.cSpellWords.txt
new file mode 100644
index 000000000..f9e1c9bbf
--- /dev/null
+++ b/.github/.cSpellWords.txt
@@ -0,0 +1,918 @@
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diff --git a/.github/lexicon.txt b/.github/lexicon.txt
deleted file mode 100644
index 2d430498f..000000000
--- a/.github/lexicon.txt
+++ /dev/null
@@ -1,3165 +0,0 @@
-  GNU nano 5.9                     .github/lexicon.txt                     Modified
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-aaaa
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-uladdress
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-ulbitstoclearonentry
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-ulmair
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-ulmatchvalueforonetick
-ulnumberofheapallocations
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-ulong
-ulparameter
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-ulportyieldpending
-ulr
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-ulrlar
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-ulsecurestacksize
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-ultablebase
-ultaskgetidleruntimecounter
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-ultaskgetruntimecounter
-ultaskgetruntimepercent
-ultaskhasfpucontext
-ultasknotifystateclear
-ultasknotifytake
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-ultasknotifyvalueclear
-ultasknotifyvalueclearindexed
-ultaskswitchedintime
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-ultotalmemoryallocations
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-ulusingfpu
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-un
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-uni
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-upto
-urad
-urat
-uri
-ursten
-urstien
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-usa
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-usb
-usbdiv
-usclockhz
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-uselib
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-uxtcbnumber
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-vapplicationcleartimerinterrupt
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-var
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-vportdefineheapregions
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-vportgetheapstats
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-vprocessinterface
-vqueueaddtoregistry
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-vr
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-vrpm
-vsemaphorecreatebinary
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-vsendingcoroutine
-vsetbacklightstate
-vsoftwareinterruptentry
-vstartfirsttask
-vstmdb
-vstmdbeq
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-vtaskdelay
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-vtaskentercritical
-vtaskexitcritical
-vtaskexitcriticalfromisr
-vtaskfunction
-vtaskgetinfo
-vtaskgetruntimestats
-vtasklist
-vtasknotify
-vtasknotifygivefromisr
-vtasknotifygiveindexedfromisr
-vtaskplaceoneventlist
-vtaskpreemptiondisable
-vtaskpreemptionenable
-vtaskpriorityset
-vtaskremovefromunorderedeventlist
-vtaskresume
-vtaskresumefromisr
-vtasksetapplicationtasktag
-vtasksettasknumber
-vtasksettimeout
-vtasksettimeoutstate
-vtaskstartscheduler
-vtasksteptick
-vtasksuspend
-vtasksuspendall
-vtaskswitchcontext
-vtaskswitchcontextforcore
-vtaskusesdpfpu
-vtickisr
-vtimercallback
-vtimerisr
-vtimersetreloadmode
-vtimersettimerid
-vtoggleled
-vtor
-vuart
-walter
-wasn
-watchpoint
-wavesel
-wavsel
-wdcr
-wdd
-wddbghlt
-wddis
-wde
-wderr
-wdfien
-wdg
-wdidlehlt
-wdie
-wdif
-wdmr
-wdp
-wdrproc
-wdrsten
-wdrstt
-wdsr
-wdt
-wdtc
-wdtgetperiod
-wdto
-wdtrestart
-wdtsetmode
-wdtsgettatus
-wdunf
-wdv
-westat
-wfi
-winavr
-wizc
-wl
-wo
-wol
-wperiodmin
-wreg
-writebit
-writting
-wu
-www
-wwwfreertos
-wxr
-xa
-xaa
-xaaaa
-xaaaaaaaa
-xabab
-xabac
-xactivetimerlist
-xaltregions
-xautoreload
-xavailableheapspaceinbytes
-xb
-xbacklighttimer
-xbankedstartscheduler
-xbb
-xbbbb
-xblocks
-xblocksize
-xblocktime
-xblocktimeticks
-xbufferlengthbytes
-xbuffersizebytes
-xbytesavailable
-xbytessent
-xbytestostoremessagelength
-xc
-xcallbackparameters
-xcallbackparameterstype
-xcalls
-xcc
-xcccc
-xcdcd
-xcdce
-xchal
-xchecktaskparameters
-xclearbitonexit
-xclearcountonexit
-xclearonexit
-xclib
-xcommandtime
-xcommsrxqueue
-xconsttickcount
-xcopyposition
-xcore
-xcoreid
-xcoroutinecreate
-xcoroutinepreviouslywoken
-xcoroutinequeue
-xcount
-xcreatedeventgroup
-xcrwokenbypost
-xd
-xdatalengthbytes
-xdd
-xdddd
-xdeadbeef
-xdelay
-xdelayedcoroutinelist
-xdelayedtasklist
-xdelaytime
-xe
-xea
-xeb
-xed
-xee
-xeeee
-xeeeeeeee
-xelapsedtime
-xend
-xer
-xeventbits
-xeventgropucreate
-xeventgropucreatestatic
-xeventgroup
-xeventgroupbuffer
-xeventgroupclearbits
-xeventgroupclearbitsfromisr
-xeventgroupcreate
-xeventgroupcreatestatic
-xeventgroupdelete
-xeventgroupgetbits
-xeventgroupgetbitsfromisr
-xeventgroupgetstaticbuffer
-xeventgroupsetbits
-xeventgroupsetbitsfromisr
-xeventgroupsync
-xeventgroupwaitbits
-xeventlistitem
-xexpectedidletime
-xexpectedticks
-xexpiredtimer
-xf
-xfc
-xff
-xfff
-xfffa
-xfffb
-xfffc
-xfffcc
-xfffd
-xfffdc
-xfffe
-xffff
-xfffff
-xfffffc
-xfffffd
-xffffff
-xffffffe
-xfffffffd
-xfffffffel
-xffffffff
-xfffffffful
-xfirstlength
-xfrequency
-xfunctiontopend
-xgenericlistitem
-xgetfreestackspace
-xhandle
-xhead
-xheapbytescurrentlyallocated
-xheapbytescurrentlyheld
-xheapbyteshighwatermark
-xheapregions
-xhigherpriorittaskwoken
-xhigherprioritytaskwoken
-xhigherprioritytaskwokenbypost
-xidletaskhandle
-xidletaskhandles
-xidletcbbuffers
-xilinx
-xindex
-xinheritanceoccurred
-xinsideinterrupt
-xintc
-xinterfacetoservice
-xinterruptcontroller
-xinterruptdescriptortable
-xisfeasable
-xisfeasible
-xisinsideisr
-xismessagebuffer
-xisprivileged
-xitemvalue
-xlasttime
-xlastwaketime
-xlength
-xlist
-xlistend
-xlowestpriority
-xlowestprioritycore
-xlowestprioritytopreempt
-xmair
-xmaxcount
-xmaxexpirycountbeforestopping
-xmaxheapbyteseverheld
-xmaxsize
-xmc
-xmessage
-xmessagebuffer
-xmessagebuffercreate
-xmessagebuffercreatestatic
-xmessagebuffergetstaticbuffers
-xmessagebufferisempty
-xmessagebufferisfull
-xmessagebuffernextlengthbytes
-xmessagebufferread
-xmessagebufferreceive
-xmessagebufferreceivecompletedfromisr
-xmessagebufferreceivefromisr
-xmessagebufferreset
-xmessagebuffersend
-xmessagebuffersendcompletedfromisr
-xmessagebuffersendfromisr
-xmessagebuffersizebytes
-xmessagebufferspaceavailable
-xmessagebufferspacesavailable
-xmessagebufferstruct
-xmessageid
-xmessagevalue
-xminimumeverfreebytesremaining
-xminsize
-xmpu
-xmpuctrlconst
-xmpusettings
-xmutex
-xmutexbuffer
-xmutexholder
-xn
-xnearstartscheduler
-xnetworkingtaskhandle
-xnewperiod
-xnewqueue
-xnextexpiretime
-xnextfreebyte
-xnexthead
-xnextmessagelength
-xnexttail
-xnexttaskunblocktime
-xnumberoffreeblocks
-xnumberofsuccessfulallocations
-xnumberofsuccessfulfrees
-xnumbertopost
-xnumofoverflows
-xoff
-xon
-xor
-xored
-xoverflowcount
-xpar
-xparameters
-xpendedcounts
-xpendedticks
-xpendingreadycoroutinelist
-xpendingreadylist
-xperiod
-xportgetcoreid
-xportgetfreeheapsize
-xportinstallinterrupthandler
-xportregistercinterrupthandler
-xportregisterdump
-xportstartfirsttask
-xportstartscheduler
-xpreemptiondisable
-xpsr
-xqueue
-xqueueaddtoset
-xqueuebuffer
-xqueuecreate
-xqueuecreatemutex
-xqueuecreateset
-xqueuecreatestatic
-xqueuegenericsend
-xqueuegenericsendfromisr
-xqueuegetmutexholder
-xqueuegetstaticbuffers
-xqueuegivefromisr
-xqueuegivemutexrecursive
-xqueueorsemaphore
-xqueueoverwrite
-xqueueoverwritefromisr
-xqueuepeek
-xqueuepeekfromisr
-xqueuereceive
-xqueuereceivefromisr
-xqueueregistryitem
-xqueueselectfromset
-xqueuesend
-xqueuesendfromisr
-xqueuesendtoback
-xqueuesendtobackfromisr
-xqueuesendtofromfromisr
-xqueuesendtofront
-xqueuesendtofrontfromisr
-xqueuesendtotofront
-xqueueset
-xqueuesizeinbytes
-xram
-xrbarconst
-xreceivedbytes
-xreceivedlength
-xregion
-xregions
-xregionssettings
-xregtest
-xrequiredspace
-xresult
-xreturn
-xreturned
-xrnrconst
-xrunningprivileged
-xrunprivileged
-xrxqueue
-xschedulerrunning
-xsecurecontext
-xsecurecontextconst
-xsecurecontexthandle
-xsemaphore
-xsemaphorebuffer
-xsemaphorecreatebinary
-xsemaphorecreatebinarystatic
-xsemaphorecreatecounting
-xsemaphorecreatecountingstatic
-xsemaphorecreateeventgroupstatic
-xsemaphorecreatemutex
-xsemaphorecreatemutexstatic
-xsemaphorecreaterecursivemutex
-xsemaphorecreaterecursivemutexstatic
-xsemaphoregetmutexholder
-xsemaphoregetmutexholderfromisr
-xsemaphoregetstaticbuffer
-xsemaphoregive
-xsemaphoregivefromisr
-xsemaphoregivemutexrecursive
-xsemaphoregiverecursive
-xsemaphoretake
-xsemaphoretakefromisr
-xsemaphoretakemutexrecursive
-xsemaphoretakerecursive
-xshal
-xsize
-xsizeinbytes
-xsizeoflargestfreeblockinbytes
-xsizeofsmallestfreeblockinbytes
-xspace
-xstack
-xstacksize
-xstart
-xstatelistitem
-xstatic
-xstatictimerqueue
-xstreambuffer
-xstreambufferbytesavailable
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-xstreambuffercreatestatic
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-xstreambufferisempty
-xstreambufferisfull
-xstreambuffernextmessagelengthbytes
-xstreambufferreceive
-xstreambufferreceivecompletedfromisr
-xstreambufferreceivefromisr
-xstreambufferreset
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-xstreambuffersendfromisr
-xstreambuffersettriggerlevel
-xstreambuffersizebytes
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-xstreambufferstruct
-xsuspendedtasklist
-xswithcrequired
-xt
-xtail
-xtal
-xtask
-xtaskabortdelay
-xtaskattribute
-xtaskbuffer
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-xtaskcatchupticks
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-xtaskcreate
-xtaskcreaterestricted
-xtaskcreaterestrictedstatic
-xtaskcreatestatic
-xtaskdelayuntil
-xtaskdetails
-xtaskendscheduler
-xtaskgetapplicationtasktag
-xtaskgetapplicationtasktagfromisr
-xtaskgetcurrenttaskhandle
-xtaskgethandle
-xtaskgetidletaskhandle
-xtaskgetschedulerstate
-xtaskgetstaticbuffers
-xtaskgettickcount
-xtaskgettickcountfromisr
-xtaskhandle
-xtaskincrementtick
-xtasknofify
-xtasknofifyindexed
-xtasknotify
-xtasknotifyandquery
-xtasknotifyandqueryfromisr
-xtasknotifyandqueryindexed
-xtasknotifyandqueryindexedfromisr
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-xtasknotifyindex
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-xtasknotifyindexedfromisr
-xtasknotifystateclear
-xtasknotifystateclearindexed
-xtasknotifytake
-xtasknotifywait
-xtasknotifywaitindexed
-xtasknumber
-xtaskremovefromeventlist
-xtaskresumeall
-xtaskresumefromisr
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-xtaskswaitingtoreceive
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-xtasktodelete
-xtasktomodify
-xtasktonotify
-xtasktoquery
-xtasktoresume
-xtasktosuspend
-xtaskwaitingtoreceive
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-xtaskwokenbyreceive
-xtbsp
-xtensa
-xtexcframe
-xthal
-xthreadstate
-xtickcount
-xtickstocatchup
-xtickstodelay
-xtickstowait
-xticktodelay
-xticktype
-xtimecaps
-xtimeincrement
-xtimenow
-xtimeonentering
-xtimeout
-xtimer
-xtimerbuffer
-xtimerchangeperiod
-xtimerchangeperiodfromisr
-xtimercreate
-xtimercreated
-xtimercreatestatic
-xtimerdelete
-xtimergenericcommand
-xtimergetexpirytime
-xtimergetperiod
-xtimergetreloadmode
-xtimergetstaticbuffer
-xtimergettimerdaemontaskhandle
-xtimeristimeractive
-xtimerlistitem
-xtimerlistswereswitched
-xtimerparameters
-xtimerparameterstype
-xtimerpendfunctioncall
-xtimerpendfunctioncallfromisr
-xtimerperiod
-xtimerperiodinticks
-xtimerqueue
-xtimerreset
-xtimerresetfromisr
-xtimers
-xtimerstart
-xtimerstartfromisr
-xtimerstop
-xtimerstopfromisr
-xtimertaskhandle
-xtlsblock
-xtos
-xtriggerlevel
-xtriggerlevelbytes
-xuart
-xvalueofinsertion
-xvtorconst
-xwaitforallbits
-xwantedsize
-xwasdelayed
-xwritevalue
-xxr
-xyieldfortask
-xyieldpending
-xyieldpendings
-xzr
-yeilding
diff --git a/.github/pull_request_process.md b/.github/pull_request_process.md
index 5e7fedafd..5b8556df9 100644
--- a/.github/pull_request_process.md
+++ b/.github/pull_request_process.md
@@ -1,6 +1,6 @@
 # Pull Request Process
 
-This document explains the stages that a Pull Request (PR) goes through when a pull request is submitted to a git repository in the FreeRTOS organization in Github. Before you start a PR, please read and familiarize yourself with [CONTRIBUTING.md](.github/CONTRIBUTING.md)
+This document explains the stages that a Pull Request (PR) goes through when a pull request is submitted to a git repository in the FreeRTOS organization in Github. Before you start a PR, please read and familiarize yourself with [CONTRIBUTING.md](CONTRIBUTING.md)
 
 ## ****Terminologies****
 
diff --git a/.github/scripts/kernel_checker.py b/.github/scripts/kernel_checker.py
index a0706932f..4b4fbe40d 100755
--- a/.github/scripts/kernel_checker.py
+++ b/.github/scripts/kernel_checker.py
@@ -36,7 +36,8 @@ from common.header_checker import HeaderChecker
 KERNEL_IGNORED_FILES = [
     'FreeRTOS-openocd.c',
     'Makefile',
-    '.DS_Store'
+    '.DS_Store',
+    'cspell.config.yaml'
 ]
 
 KERNEL_IGNORED_EXTENSIONS = [
@@ -88,7 +89,10 @@ KERNEL_IGNORED_PATTERNS = [
     r'.*portable/IAR/AtmelSAM7S64/.*AT91SAM7.*',
     r'.*portable/GCC/ARM7_AT91SAM7S/.*',
     r'.*portable/MPLAB/PIC18F/stdio.h',
-    r'.*portable/ThirdParty/xClang/XCOREAI/*'
+    r'.*portable/ThirdParty/xClang/XCOREAI/*',
+    r'.*IAR/ARM_C*',
+    r'.*IAR/78K0R/*',
+    r'.*CCS/MSP430X/*'
 ]
 
 KERNEL_THIRD_PARTY_PATTERNS = [
diff --git a/.github/workflows/auto-release.yml b/.github/workflows/auto-release.yml
index 21788c8a6..73ec92cf0 100644
--- a/.github/workflows/auto-release.yml
+++ b/.github/workflows/auto-release.yml
@@ -31,14 +31,14 @@ jobs:
 
       # Currently FreeRTOS/.github/scripts houses the release script. Download it for upcoming usage
       - name: Checkout FreeRTOS Release Tools
-        uses: actions/checkout@v2
+        uses: actions/checkout@v3
         with:
           repository: FreeRTOS/FreeRTOS
           path: tools
 
       # Simpler git auth if we use checkout action and forward the repo to release script
       - name: Checkout FreeRTOS Kernel
-        uses: actions/checkout@v2
+        uses: actions/checkout@v3
         with:
           path: local_kernel
           fetch-depth: 0
diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
index b106b5fec..46c6f7ee0 100644
--- a/.github/workflows/ci.yml
+++ b/.github/workflows/ci.yml
@@ -6,75 +6,53 @@ on:
     branches: [main]
   workflow_dispatch:
 jobs:
-  spell-check:
-    runs-on: ubuntu-latest
-    steps:
-      - name: Checkout Parent Repo
-        uses: actions/checkout@v2
-        with:
-          ref: main
-          repository: aws/aws-iot-device-sdk-embedded-C
-          path: main
-      - name: Clone This Repo
-        uses: actions/checkout@v2
-        with:
-            path: ./kernel
-      - name: Install spell
-        run: |
-          sudo apt-get install spell
-          sudo apt-get install util-linux
-      - name: Check spelling
-        run: |
-          PATH=$PATH:main/tools/spell
-          # Make sure that the portable directory is not included in the spellcheck.
-          sed -i 's/find $DIRNAME/find $DIRNAME -not -path '*portable*'/g' main/tools/spell/find-unknown-comment-words
-          find-unknown-comment-words --directory kernel/ --lexicon ./kernel/.github/lexicon.txt
-          if [ "$?" = "0" ]; then
-            exit 0
-          else
-            exit 1
-          fi
   formatting:
     runs-on: ubuntu-20.04
     steps:
-      - uses: actions/checkout@v2
-      - name: Install Uncrustify
-        run: sudo apt-get install uncrustify=0.69.0+dfsg1-1build1
-      - name: Run Uncrustify
-        run: |
-          uncrustify --version
-          find . portable/MemMang/* portable/Common/* \( -name portable \) -prune -false -o -iname "*.[hc]" -exec uncrustify --check -c .github/uncrustify.cfg {} +
-      - name: Check For Trailing Whitespace
-        run: |
-          set +e
-          grep --exclude="*.md" --exclude-dir=".git"  -rnI -e "[[:blank:]]$" .
-          if [ "$?" = "0" ]; then
-            echo "Files have trailing whitespace."
-            exit 1
-          else
-            exit 0
-          fi
-        shell: bash
-      - name: Check for CRLF
-        working-directory: ${{ inputs.path }}
-        run: |
-          set +e
-          find . -path ./.git -prune -o -exec file {} + |  grep "CRLF"
-          if [ "$?" = "0" ]; then
-            echo "Files have CRLF line endings."
-            exit 1
-          else
-            exit 0
-          fi
-        shell: bash
+      - uses: actions/checkout@v3
+      - name: Check Formatting of FreeRTOS-Kernel Files
+        uses: FreeRTOS/CI-CD-Github-Actions/formatting@main
+
+  spell-check:
+      runs-on: ubuntu-latest
+      steps:
+        - name: Clone This Repo
+          uses: actions/checkout@v3
+        - name: Run spellings check
+          uses: FreeRTOS/CI-CD-Github-Actions/spellings@main
+          with:
+            path: ./
+            exclude-files: History.txt
+
+  link-verifier:
+    runs-on: ubuntu-latest
+    steps:
+      - name: Clone This Repo
+        uses: actions/checkout@v3
+      - name: Link Verification
+        uses: FreeRTOS/CI-CD-Github-Actions/link-verifier@v2
 
   url-check:
     runs-on: ubuntu-latest
     steps:
-      - name: Clone This Repo
-        uses: actions/checkout@v2
+      - uses: actions/checkout@v3
         with:
-            path: ./kernel
+          path: ./kernel
+
       - name: URL Checker
         run: |
-            bash kernel/.github/actions/url_verifier.sh kernel
+          bash kernel/.github/actions/url_verifier.sh kernel
+
+  verify-manifest:
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/checkout@v3
+        with:
+          submodules: true
+          fetch-depth: 0
+
+      - name: Run manifest verifier
+        uses: FreeRTOS/CI-CD-GitHub-Actions/manifest-verifier@main
+        with:
+          path: ./
+          fail-on-incorrect-version: true
diff --git a/.github/workflows/git-secrets.yml b/.github/workflows/git-secrets.yml
index b78a79c45..2b88ce0a7 100644
--- a/.github/workflows/git-secrets.yml
+++ b/.github/workflows/git-secrets.yml
@@ -7,11 +7,11 @@ jobs:
   git-secrets:
     runs-on: ubuntu-latest
     steps:
-      - uses: actions/checkout@v2
+      - uses: actions/checkout@v3
         with:
           submodules: recursive
       - name: Checkout awslabs/git-secrets
-        uses: actions/checkout@v2
+        uses: actions/checkout@v3
         with:
           repository: awslabs/git-secrets
           ref: master
diff --git a/.github/workflows/kernel-checks.yml b/.github/workflows/kernel-checks.yml
index a4627f0e0..679ede23e 100644
--- a/.github/workflows/kernel-checks.yml
+++ b/.github/workflows/kernel-checks.yml
@@ -18,7 +18,7 @@ jobs:
 
       # There is shared code, hosted by FreeRTOS/FreeRTOS, with deps needed by header checker
       - name: Checkout FreeRTOS Tools
-        uses: actions/checkout@v2
+        uses: actions/checkout@v3
         with:
           repository: FreeRTOS/FreeRTOS
           ref:  main
@@ -26,7 +26,7 @@ jobs:
 
       # Checkout user pull request changes
       - name: Checkout Pull Request
-        uses: actions/checkout@v2
+        uses: actions/checkout@v3
         with:
           path: inspect
 
diff --git a/.github/workflows/kernel-demos.yml b/.github/workflows/kernel-demos.yml
index 79ed8ca02..21cbd5c8d 100644
--- a/.github/workflows/kernel-demos.yml
+++ b/.github/workflows/kernel-demos.yml
@@ -7,7 +7,7 @@ jobs:
     runs-on: windows-latest
     steps:
       - name: Checkout the FreeRTOS/FreeRTOS Repository
-        uses: actions/checkout@v2
+        uses: actions/checkout@v3
         with:
           ref: main
           repository: FreeRTOS/FreeRTOS
@@ -16,7 +16,7 @@ jobs:
 
       # Checkout user pull request changes
       - name: Checkout Pull Request
-        uses: actions/checkout@v2
+        uses: actions/checkout@v3
         with:
           path: ./FreeRTOS/Source
 
@@ -36,7 +36,7 @@ jobs:
     runs-on: windows-latest
     steps:
       - name: Checkout the FreeRTOS/FreeRTOS Repository
-        uses: actions/checkout@v2
+        uses: actions/checkout@v3
         with:
           ref: main
           repository: FreeRTOS/FreeRTOS
@@ -45,7 +45,7 @@ jobs:
 
       # Checkout user pull request changes
       - name: Checkout Pull Request
-        uses: actions/checkout@v2
+        uses: actions/checkout@v3
         with:
           path: ./FreeRTOS/Source
 
@@ -61,7 +61,7 @@ jobs:
     runs-on: ubuntu-latest
     steps:
       - name: Checkout the FreeRTOS/FreeRTOS Repository
-        uses: actions/checkout@v2
+        uses: actions/checkout@v3
         with:
           ref: main
           repository: FreeRTOS/FreeRTOS
@@ -70,7 +70,7 @@ jobs:
 
       # Checkout user pull request changes
       - name: Checkout Pull Request
-        uses: actions/checkout@v2
+        uses: actions/checkout@v3
         with:
           path: ./FreeRTOS/Source
 
@@ -95,7 +95,7 @@ jobs:
     runs-on: ubuntu-latest
     steps:
       - name: Checkout the FreeRTOS/FreeRTOS Repository
-        uses: actions/checkout@v2
+        uses: actions/checkout@v3
         with:
           ref: main
           repository: FreeRTOS/FreeRTOS
@@ -104,7 +104,7 @@ jobs:
 
       # Checkout user pull request changes
       - name: Checkout Pull Request
-        uses: actions/checkout@v2
+        uses: actions/checkout@v3
         with:
           path: ./FreeRTOS/Source
 
@@ -124,7 +124,7 @@ jobs:
     runs-on: ubuntu-latest
     steps:
       - name: Checkout the FreeRTOS/FreeRTOS Repository
-        uses: actions/checkout@v2
+        uses: actions/checkout@v3
         with:
           ref: main
           repository: FreeRTOS/FreeRTOS
@@ -146,7 +146,7 @@ jobs:
 
       # Checkout user pull request changes
       - name: Checkout Pull Request
-        uses: actions/checkout@v2
+        uses: actions/checkout@v3
         with:
           path: ./FreeRTOS/Source
 
diff --git a/.github/workflows/unit-tests.yml b/.github/workflows/unit-tests.yml
index 73e1808fa..c154750b4 100644
--- a/.github/workflows/unit-tests.yml
+++ b/.github/workflows/unit-tests.yml
@@ -6,7 +6,7 @@ jobs:
     runs-on: ubuntu-20.04
     steps:
     - name: Checkout Parent Repository
-      uses: actions/checkout@v2
+      uses: actions/checkout@v3
       with:
         ref: main
         repository: FreeRTOS/FreeRTOS
@@ -15,7 +15,7 @@ jobs:
 
     # Checkout user pull request changes
     - name: Checkout Pull Request
-      uses: actions/checkout@v2
+      uses: actions/checkout@v3
       with:
         path: ./FreeRTOS/Source
 
diff --git a/CMakeLists.txt b/CMakeLists.txt
index 678b6a6f5..15bbe0bf6 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -4,7 +4,7 @@ cmake_minimum_required(VERSION 3.15)
 #   FREERTOS_PORT, if not specified and native port detected, uses the native compile.
 #
 # User is responsible for one library target:
-#   freertos_config ,typcially an INTERFACE library
+#   freertos_config ,typically an INTERFACE library
 #
 # DEPRECATED: FREERTOS_CONFIG_FILE_DIRECTORY - but still supported if no freertos_config defined for now.
 #             May be removed at some point in the future.
diff --git a/README.md b/README.md
index 540902118..75c7c66dc 100644
--- a/README.md
+++ b/README.md
@@ -1,14 +1,28 @@
 [![CMock Unit Tests](https://github.com/FreeRTOS/FreeRTOS-Kernel/actions/workflows/unit-tests.yml/badge.svg?branch=main&event=push)](https://github.com/FreeRTOS/FreeRTOS-Kernel/actions/workflows/unit-tests.yml?query=branch%3Amain+event%3Apush+workflow%3A%22CMock+Unit+Tests%22++)
 [![codecov](https://codecov.io/gh/FreeRTOS/FreeRTOS-Kernel/badge.svg?branch=main)](https://codecov.io/gh/FreeRTOS/FreeRTOS-Kernel)
 ## Getting started
-This repository contains FreeRTOS kernel source/header files and kernel ports only. This repository is referenced as a submodule in [FreeRTOS/FreeRTOS](https://github.com/FreeRTOS/FreeRTOS) repository, which contains pre-configured demo application projects under ```FreeRTOS/Demo``` directory.
+This repository contains FreeRTOS kernel source/header files and kernel
+ports only. This repository is referenced as a submodule in
+[FreeRTOS/FreeRTOS](https://github.com/FreeRTOS/FreeRTOS)
+repository, which contains pre-configured demo application projects under
+```FreeRTOS/Demo``` directory.
 
-The easiest way to use FreeRTOS is to start with one of the pre-configured demo application projects.  That way you will have the correct FreeRTOS source files included, and the correct include paths configured.  Once a demo application is building and executing you can remove the demo application files, and start to add in your own application source files.  See the [FreeRTOS Kernel Quick Start Guide](https://www.FreeRTOS.org/FreeRTOS-quick-start-guide.html) for detailed instructions and other useful links.
+The easiest way to use FreeRTOS is to start with one of the pre-configured demo
+application projects.  That way you will have the correct FreeRTOS source files
+included, and the correct include paths configured. Once a demo application is
+building and executing you can remove the demo application files, and start to
+add in your own application source files.  See the
+[FreeRTOS Kernel Quick Start Guide](https://www.FreeRTOS.org/FreeRTOS-quick-start-guide.html)
+for detailed instructions and other useful links.
 
-Additionally, for FreeRTOS kernel feature information refer to the [Developer Documentation](https://www.FreeRTOS.org/features.html), and [API Reference](https://www.FreeRTOS.org/a00106.html).
+Additionally, for FreeRTOS kernel feature information refer to the
+[Developer Documentation](https://www.FreeRTOS.org/features.html),
+and [API Reference](https://www.FreeRTOS.org/a00106.html).
 
 ### Getting help
-If you have any questions or need assistance troubleshooting your FreeRTOS project, we have an active community that can help on the [FreeRTOS Community Support Forum](https://forums.freertos.org).
+If you have any questions or need assistance troubleshooting your FreeRTOS project,
+we have an active community that can help on the
+[FreeRTOS Community Support Forum](https://forums.freertos.org).
 
 ## To consume FreeRTOS-Kernel
 
@@ -99,22 +113,49 @@ See the readme file in the ```./portable``` directory for more information.
 - The ```./include``` directory contains the real time kernel header files.
 
 ### Code Formatting
-FreeRTOS files are formatted using the "uncrustify" tool. The configuration file used by uncrustify can be found in the [.github/uncrustify.cfg](.github/uncrustify.cfg) file.
+FreeRTOS files are formatted using the
+"[uncrustify](https://github.com/uncrustify/uncrustify)" tool.
+The configuration file used by uncrustify can be found in the
+[FreeRTOS/CI-CD-GitHub-Actions's](https://github.com/FreeRTOS/CI-CD-Github-Actions)
+[uncrustify.cfg](https://github.com/FreeRTOS/CI-CD-Github-Actions/tree/main/formatting)
+file.
 
 ### Line Endings
-File checked into the FreeRTOS-Kernel repository use unix-style LF line endings for the best compatibility with git.
+File checked into the FreeRTOS-Kernel repository use unix-style LF line endings
+for the best compatibility with git.
 
-For optimal compatibility with Microsoft Windows tools, it is best to enable the git autocrlf feature. You can enable this setting for the current repository using the following command:
+For optimal compatibility with Microsoft Windows tools, it is best to enable
+the git autocrlf feature. You can enable this setting for the current
+repository using the following command:
 ```
 git config core.autocrlf true
 ```
 
 ### Git History Optimizations
-Some commits in this repository perform large refactors which touch many lines and lead to unwanted behavior when using the `git blame` command. You can configure git to ignore the list of large refactor commits in this repository with the following command:
+Some commits in this repository perform large refactors which touch many lines
+and lead to unwanted behavior when using the `git blame` command. You can
+configure git to ignore the list of large refactor commits in this repository
+with the following command:
 ```
 git config blame.ignoreRevsFile .git-blame-ignore-revs
 ```
 
-### Spelling
-*lexicon.txt* contains words that are not traditionally found in an English dictionary. It is used by the spellchecker to verify the various jargon, variable names, and other odd words used in the FreeRTOS code base. If your pull request fails to pass the spelling and you believe this is a mistake, then add the word to *lexicon.txt*.
-Note that only the FreeRTOS Kernel source files are checked for proper spelling, the portable section is ignored.
+### Spelling and Formatting
+We recommend using [Visual Studio Code](https://code.visualstudio.com),
+commonly referred to as VSCode, when working on the FreeRTOS-Kernel.
+The FreeRTOS-Kernel also uses [cSpell](https://cspell.org/) as part of its
+spelling check. The config file for which can be found at [cspell.config.yaml](cspell.config.yaml)
+There is additionally a
+[cSpell plugin for VSCode](https://marketplace.visualstudio.com/items?itemName=streetsidesoftware.code-spell-checker)
+that can be used as well.
+*[.cSpellWords.txt](.github/.cSpellWords.txt)* contains words that are not
+traditionally found in an English dictionary. It is used by the spellchecker
+to verify the various jargon, variable names, and other odd words used in the
+FreeRTOS code base are correct. If your pull request fails to pass the spelling
+and you believe this is a mistake, then add the word to
+*[.cSpellWords.txt](.github/.cSpellWords.txt)*. When adding a word please
+then sort the list, which can be done by running the bash command:
+`sort -u .cSpellWords.txt -o .cSpellWords.txt`
+Note that only the FreeRTOS-Kernel Source Files, [include](include),
+[portable/MemMang](portable/MemMang), and [portable/Common](portable/Common)
+files are checked for proper spelling, and formatting at this time.
diff --git a/cspell.config.yaml b/cspell.config.yaml
new file mode 100644
index 000000000..911ce1d8f
--- /dev/null
+++ b/cspell.config.yaml
@@ -0,0 +1,31 @@
+---
+$schema: https://raw.githubusercontent.com/streetsidesoftware/cspell/main/cspell.schema.json
+version: '0.2'
+# Allows things like stringLength
+allowCompoundWords: true
+
+# Read files not to spell check from the git ignore
+useGitignore: true
+
+#  Language settings for C
+languageSettings:
+  - caseSensitive: false
+    enabled: true
+    languageId: c
+    locale: "*"
+
+# Add a dictionary, and the path to the word list
+dictionaryDefinitions:
+  - name: freertos-words
+    path: '.github/.cSpellWords.txt'
+    addWords: true
+
+dictionaries:
+  - freertos-words
+
+# Paths and files to ignore
+ignorePaths:
+  - 'dependency'
+  - 'docs'
+  - 'ThirdParty'
+  - 'History.txt'
diff --git a/portable/ARMv8M/ReadMe.txt b/portable/ARMv8M/ReadMe.txt
index 3f864bb03..c6dbe7709 100644
--- a/portable/ARMv8M/ReadMe.txt
+++ b/portable/ARMv8M/ReadMe.txt
@@ -1,4 +1,4 @@
-This directory tree contains the master copy of the FreeeRTOS Armv8-M and
+This directory tree contains the master copy of the FreeRTOS Armv8-M and
 Armv8.1-M ports.
 Do not use the files located here!  These file are copied into separate
 FreeRTOS/Source/portable/[compiler]/ARM_CM[23|33|55|85]_NNN directories prior to each
diff --git a/portable/ARMv8M/non_secure/port.c b/portable/ARMv8M/non_secure/port.c
index 80410e82e..c940c304b 100644
--- a/portable/ARMv8M/non_secure/port.c
+++ b/portable/ARMv8M/non_secure/port.c
@@ -110,8 +110,8 @@
 /**
  * @brief Constants used during system call enter and exit.
  */
-#define portPSR_STACK_PADDING_MASK                ( 1UL << 9UL )
-#define portEXC_RETURN_STACK_FRAME_TYPE_MASK      ( 1UL << 4UL )
+#define portPSR_STACK_PADDING_MASK              ( 1UL << 9UL )
+#define portEXC_RETURN_STACK_FRAME_TYPE_MASK    ( 1UL << 4UL )
 /*-----------------------------------------------------------*/
 
 /**
@@ -133,81 +133,81 @@
 /**
  * @brief Offsets in the stack to the parameters when inside the SVC handler.
  */
-#define portOFFSET_TO_LR                    ( 5 )
-#define portOFFSET_TO_PC                    ( 6 )
-#define portOFFSET_TO_PSR                   ( 7 )
+#define portOFFSET_TO_LR     ( 5 )
+#define portOFFSET_TO_PC     ( 6 )
+#define portOFFSET_TO_PSR    ( 7 )
 /*-----------------------------------------------------------*/
 
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                      ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                      ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                       ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                      ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                      ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                     ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                     ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK  ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK               ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK               ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK               ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK               ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK               ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK               ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK               ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK               ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0              ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1              ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2              ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3              ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4              ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5              ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6              ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7              ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE            ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT      ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                      ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE             ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -216,11 +216,11 @@
 
 /* Extract last address of the MPU region as encoded in the
  * RLAR (Region Limit Address Register) value. */
-#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar )  \
+#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar ) \
     ( ( ( rlar ) & portMPU_RLAR_ADDRESS_MASK ) | ~portMPU_RLAR_ADDRESS_MASK )
 
 /* Does addr lies within [start, end] address range? */
-#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end )    \
+#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \
     ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) )
 
 /* Is the access request satisfied by the available permissions? */
@@ -422,54 +422,57 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the system call stack so that upon returning from
-     * SVC, the system call stack is used.
-     *
-     * It is used for the system calls with up to 4 parameters.
-     *
-     * @param pulTaskStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the system call stack so that upon returning from
+ * SVC, the system call stack is used.
+ *
+ * It is used for the system calls with up to 4 parameters.
+ *
+ * @param pulTaskStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallEnter( uint32_t * pulTaskStack,
+                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the system call stack so that upon returning from
-     * SVC, the system call stack is used.
-     *
-     * It is used for the system calls with 5 parameters.
-     *
-     * @param pulTaskStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the system call stack so that upon returning from
+ * SVC, the system call stack is used.
+ *
+ * It is used for the system calls with 5 parameters.
+ *
+ * @param pulTaskStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallEnter_1( uint32_t * pulTaskStack,
+                             uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the task stack so that upon returning from
-     * SVC, the task stack is used again.
-     *
-     * @param pulSystemCallStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the task stack so that upon returning from
+ * SVC, the task stack is used again.
+ *
+ * @param pulSystemCallStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallExit( uint32_t * pulSystemCallStack,
+                          uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Checks whether or not the calling task is privileged.
-     *
-     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
-     */
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
     BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
 
 #endif /* configENABLE_MPU == 1 */
@@ -1086,18 +1089,18 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             vRestoreContextOfFirstTask();
             break;
 
-        #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
-            case portSVC_RAISE_PRIVILEGE:
+            #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+                case portSVC_RAISE_PRIVILEGE:
 
-                /* Only raise the privilege, if the svc was raised from any of
-                 * the system calls. */
-                if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
-                    ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
-                {
-                    vRaisePrivilege();
-                }
-                break;
-        #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+                    /* Only raise the privilege, if the svc was raised from any of
+                     * the system calls. */
+                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+                    {
+                        vRaisePrivilege();
+                    }
+                    break;
+            #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
         default:
             /* Incorrect SVC call. */
@@ -1108,513 +1111,526 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulSystemCallStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallEnter( uint32_t * pulTaskStack,
+                           uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulSystemCallStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        /* This is not NULL only for the duration of the system call. */
-        configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+        #if defined( __ARMCC_VERSION )
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+
+            /* This is not NULL only for the duration of the system call. */
+            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the system call stack for the stack frame. */
+            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulSystemCallStack[ i ] = pulTaskStack[ i ];
+            }
+
+            /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
+             * restore it when we exit from the system call. */
+            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* Use the pulSystemCallStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+
+            /* Remember the location where we should copy the stack frame when we exit from
+             * the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+
+            /* Record if the hardware used padding to force the stack pointer
+             * to be double word aligned. */
+            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
+            {
+                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
             }
+
+            /* We ensure in pxPortInitialiseStack that the system call stack is
+             * double word aligned and therefore, there is no need of padding.
+             * Clear the bit[9] of stacked xPSR. */
+            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
+
+            /* Raise the privilege for the duration of the system call. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " bics r0, r1         \n" /* Clear nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the system call stack for the stack frame. */
-        pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulSystemCallStack[ i ] = pulTaskStack[ i ];
-        }
-
-        /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
-         * restore it when we exit from the system call. */
-        pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-        __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* Use the pulSystemCallStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-
-        /* Remember the location where we should copy the stack frame when we exit from
-         * the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-        /* Record if the hardware used padding to force the stack pointer
-         * to be double word aligned. */
-        if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-        {
-            pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-        }
-        else
-        {
-            pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-        }
-
-        /* We ensure in pxPortInitialiseStack that the system call stack is
-         * double word aligned and therefore, there is no need of padding.
-         * Clear the bit[9] of stacked xPSR. */
-        pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-        /* Raise the privilege for the duration of the system call. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " bics r0, r1         \n" /* Clear nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulSystemCallStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallEnter_1( uint32_t * pulTaskStack,
+                             uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulSystemCallStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        /* This is not NULL only for the duration of the system call. */
-        configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+        #if defined( __ARMCC_VERSION )
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+
+            /* This is not NULL only for the duration of the system call. */
+            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the system call stack for the stack frame and
+             * the parameter passed on the stack. We only need to copy one
+             * parameter but we still reserve 2 spaces to keep the stack
+             * double word aligned. */
+            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulSystemCallStack[ i ] = pulTaskStack[ i ];
+            }
+
+            /* Copy the parameter which is passed the stack. */
+            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
+            {
+                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
+
+                /* Record if the hardware used padding to force the stack pointer
+                 * to be double word aligned. */
+                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
+
+                /* Record if the hardware used padding to force the stack pointer
+                 * to be double word aligned. */
+                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
             }
+
+            /* Store the value of the LR and PSPLIM registers before the SVC was raised.
+             * We need to restore it when we exit from the system call. */
+            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* Use the pulSystemCallStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+
+            /* Remember the location where we should copy the stack frame when we exit from
+             * the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+
+            /* We ensure in pxPortInitialiseStack that the system call stack is
+             * double word aligned and therefore, there is no need of padding.
+             * Clear the bit[9] of stacked xPSR. */
+            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
+
+            /* Raise the privilege for the duration of the system call. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " bics r0, r1         \n" /* Clear nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the system call stack for the stack frame and
-         * the parameter passed on the stack. We only need to copy one
-         * parameter but we still reserve 2 spaces to keep the stack
-         * double word aligned. */
-        pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulSystemCallStack[ i ] = pulTaskStack[ i ];
-        }
-
-        /* Copy the parameter which is passed the stack. */
-        if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-        {
-            pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
-            /* Record if the hardware used padding to force the stack pointer
-             * to be double word aligned. */
-            pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-        }
-        else
-        {
-            pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
-            /* Record if the hardware used padding to force the stack pointer
-             * to be double word aligned. */
-            pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-        }
-
-        /* Store the value of the LR and PSPLIM registers before the SVC was raised.
-         * We need to restore it when we exit from the system call. */
-        pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-        __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* Use the pulSystemCallStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-
-        /* Remember the location where we should copy the stack frame when we exit from
-         * the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-        /* We ensure in pxPortInitialiseStack that the system call stack is
-         * double word aligned and therefore, there is no need of padding.
-         * Clear the bit[9] of stacked xPSR. */
-        pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-        /* Raise the privilege for the duration of the system call. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " bics r0, r1         \n" /* Clear nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulTaskStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallExit( uint32_t * pulSystemCallStack,
+                          uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulTaskStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+        #if defined( __ARMCC_VERSION )
+
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the task stack for the stack frame. */
+            pulTaskStack = pulTaskStack - ulStackFrameSize;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulTaskStack[ i ] = pulSystemCallStack[ i ];
+            }
+
+            /* Use the pulTaskStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
+
+            /* Restore the LR and PSPLIM to what they were at the time of
+             * system call entry. */
+            pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* If the hardware used padding to force the stack pointer
+             * to be double word aligned, set the stacked xPSR bit[9],
+             * otherwise clear it. */
+            if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG )
+            {
+                pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
             }
+
+            /* This is not NULL only for the duration of the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
+
+            /* Drop the privilege before returning to the thread mode. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " orrs r0, r1         \n" /* Set nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the task stack for the stack frame. */
-        pulTaskStack = pulTaskStack - ulStackFrameSize;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulTaskStack[ i ] = pulSystemCallStack[ i ];
-        }
-
-        /* Use the pulTaskStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
-
-        /* Restore the LR and PSPLIM to what they were at the time of
-         * system call entry. */
-        pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* If the hardware used padding to force the stack pointer
-         * to be double word aligned, set the stacked xPSR bit[9],
-         * otherwise clear it. */
-        if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG )
-        {
-            pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK;
-        }
-        else
-        {
-            pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-        }
-
-        /* This is not NULL only for the duration of the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
-
-        /* Drop the privilege before returning to the thread mode. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " orrs r0, r1         \n" /* Set nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */
-{
-    BaseType_t xTaskIsPrivileged = pdFALSE;
-    const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
-
-    if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+    BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */
     {
-        xTaskIsPrivileged = pdTRUE;
-    }
+        BaseType_t xTaskIsPrivileged = pdFALSE;
+        const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
 
-    return xTaskIsPrivileged;
-}
+        if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+        {
+            xTaskIsPrivileged = pdTRUE;
+        }
+
+        return xTaskIsPrivileged;
+    }
 
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
-#if( configENABLE_MPU == 1 )
+#if ( configENABLE_MPU == 1 )
 
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     StackType_t * pxEndOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters,
-                                     BaseType_t xRunPrivileged,
-                                     xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
-{
-    uint32_t ulIndex = 0;
-
-    xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
-    ulIndex++;
-
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
-    ulIndex++;
-
-    #if ( configENABLE_TRUSTZONE == 1 )
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters,
+                                         BaseType_t xRunPrivileged,
+                                         xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
     {
-        xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT;  /* xSecureContext. */
+        uint32_t ulIndex = 0;
+
+        xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
         ulIndex++;
-    }
-    #endif /* configENABLE_TRUSTZONE */
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
-    ulIndex++;
-    if( xRunPrivileged == pdTRUE )
-    {
-        xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */
         ulIndex++;
-    }
-    else
-    {
-        xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */
         ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
+        ulIndex++;
+
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters;            /* r0. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x01010101;                           /* r1. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x02020202;                           /* r2. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x03030303;                           /* r3. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x12121212;                           /* r12. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode;                  /* PC. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR;                     /* xPSR. */
+        ulIndex++;
+
+        #if ( configENABLE_TRUSTZONE == 1 )
+        {
+            xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT; /* xSecureContext. */
+            ulIndex++;
+        }
+        #endif /* configENABLE_TRUSTZONE */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
+        ulIndex++;
+
+        if( xRunPrivileged == pdTRUE )
+        {
+            xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
+            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+            ulIndex++;
+        }
+        else
+        {
+            xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
+            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+            ulIndex++;
+        }
+
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
+        ulIndex++;
+
+        #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+        {
+            /* Ensure that the system call stack is double word aligned. */
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] );
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) &
+                                                                                     ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
+
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] );
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) +
+                                                                                            ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) &
+                                                                                          ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
+
+            /* This is not NULL only for the duration of a system call. */
+            xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL;
+        }
+        #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
+
+        return &( xMPUSettings->ulContext[ ulIndex ] );
     }
-    xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
-    ulIndex++;
-
-    #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
-    {
-        /* Ensure that the system call stack is double word aligned. */
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] );
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) &
-                                                                                 ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
-
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] );
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) +
-                                                                                        ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) &
-                                                                                      ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
-
-        /* This is not NULL only for the duration of a system call. */
-        xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL;
-    }
-    #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
-
-    return &( xMPUSettings->ulContext[ ulIndex ] );
-}
 
 #else /* configENABLE_MPU */
 
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     StackType_t * pxEndOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters ) /* PRIVILEGED_FUNCTION */
-{
-    /* Simulate the stack frame as it would be created by a context switch
-     * interrupt. */
-    #if ( portPRELOAD_REGISTERS == 0 )
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters ) /* PRIVILEGED_FUNCTION */
     {
-        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-        pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
-        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-        pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
-        *pxTopOfStack = portINITIAL_EXC_RETURN;
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
-
-        #if ( configENABLE_TRUSTZONE == 1 )
+        /* Simulate the stack frame as it would be created by a context switch
+         * interrupt. */
+        #if ( portPRELOAD_REGISTERS == 0 )
         {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
-        }
-        #endif /* configENABLE_TRUSTZONE */
-    }
-    #else /* portPRELOAD_REGISTERS */
-    {
-        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
-        pxTopOfStack--;
-        *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
+            pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
+            *pxTopOfStack = portINITIAL_EXC_RETURN;
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+            #if ( configENABLE_TRUSTZONE == 1 )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+            }
+            #endif /* configENABLE_TRUSTZONE */
+        }
+        #else /* portPRELOAD_REGISTERS */
         {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
-        }
-        #endif /* configENABLE_TRUSTZONE */
-    }
-    #endif /* portPRELOAD_REGISTERS */
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
+            pxTopOfStack--;
+            *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack;            /* Slot used to hold this task's PSPLIM value. */
 
-    return pxTopOfStack;
-}
+            #if ( configENABLE_TRUSTZONE == 1 )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+            }
+            #endif /* configENABLE_TRUSTZONE */
+        }
+        #endif /* portPRELOAD_REGISTERS */
+
+        return pxTopOfStack;
+    }
 
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/mpu_wrappers_v2_asm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/mpu_wrappers_v2_asm.c
index f6fb0e778..00c8bcfa8 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/mpu_wrappers_v2_asm.c
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/mpu_wrappers_v2_asm.c
@@ -44,2344 +44,2344 @@
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-#if ( INCLUDE_xTaskDelayUntil == 1 )
+    #if ( INCLUDE_xTaskDelayUntil == 1 )
 
-BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
-                                const TickType_t xTimeIncrement ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
+                                        const TickType_t xTimeIncrement ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
-                                const TickType_t xTimeIncrement ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskDelayUntilImpl                       \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTaskDelayUntil_Unpriv                        \n"
-        " MPU_xTaskDelayUntil_Priv:                             \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTaskDelayUntilImpl                         \n"
-        " MPU_xTaskDelayUntil_Unpriv:                           \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskDelayUntilImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
+                                        const TickType_t xTimeIncrement ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskDelayUntilImpl                       \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xTaskDelayUntil_Unpriv                        \n"
+                " MPU_xTaskDelayUntil_Priv:                             \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xTaskDelayUntilImpl                         \n"
+                " MPU_xTaskDelayUntil_Unpriv:                           \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskDelayUntilImpl                        \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */
+    #endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_xTaskAbortDelay == 1 )
+    #if ( INCLUDE_xTaskAbortDelay == 1 )
 
-BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskAbortDelayImpl                       \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTaskAbortDelay_Unpriv                        \n"
-        " MPU_xTaskAbortDelay_Priv:                             \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTaskAbortDelayImpl                         \n"
-        " MPU_xTaskAbortDelay_Unpriv:                           \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskAbortDelayImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskAbortDelayImpl                       \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xTaskAbortDelay_Unpriv                        \n"
+                " MPU_xTaskAbortDelay_Priv:                             \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xTaskAbortDelayImpl                         \n"
+                " MPU_xTaskAbortDelay_Unpriv:                           \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskAbortDelayImpl                        \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */
+    #endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_vTaskDelay == 1 )
+    #if ( INCLUDE_vTaskDelay == 1 )
 
-void MPU_vTaskDelay( const TickType_t xTicksToDelay ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskDelay( const TickType_t xTicksToDelay ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskDelayImpl                            \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_vTaskDelay_Unpriv                             \n"
-        " MPU_vTaskDelay_Priv:                                  \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_vTaskDelayImpl                              \n"
-        " MPU_vTaskDelay_Unpriv:                                \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskDelayImpl                             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskDelayImpl                            \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_vTaskDelay_Unpriv                             \n"
+                " MPU_vTaskDelay_Priv:                                  \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_vTaskDelayImpl                              \n"
+                " MPU_vTaskDelay_Unpriv:                                \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskDelayImpl                             \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_vTaskDelay == 1 ) */
+    #endif /* if ( INCLUDE_vTaskDelay == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_uxTaskPriorityGet == 1 )
+    #if ( INCLUDE_uxTaskPriorityGet == 1 )
 
-UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskPriorityGetImpl                     \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_uxTaskPriorityGet_Unpriv                      \n"
-        " MPU_uxTaskPriorityGet_Priv:                           \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_uxTaskPriorityGetImpl                       \n"
-        " MPU_uxTaskPriorityGet_Unpriv:                         \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskPriorityGetImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskPriorityGetImpl                     \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_uxTaskPriorityGet_Unpriv                      \n"
+                " MPU_uxTaskPriorityGet_Priv:                           \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_uxTaskPriorityGetImpl                       \n"
+                " MPU_uxTaskPriorityGet_Unpriv:                         \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskPriorityGetImpl                      \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */
+    #endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_eTaskGetState == 1 )
+    #if ( INCLUDE_eTaskGetState == 1 )
 
-eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_eTaskGetStateImpl                         \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_eTaskGetState_Unpriv                          \n"
-        " MPU_eTaskGetState_Priv:                               \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_eTaskGetStateImpl                           \n"
-        " MPU_eTaskGetState_Unpriv:                             \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_eTaskGetStateImpl                          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_eTaskGetStateImpl                         \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_eTaskGetState_Unpriv                          \n"
+                " MPU_eTaskGetState_Priv:                               \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_eTaskGetStateImpl                           \n"
+                " MPU_eTaskGetState_Unpriv:                             \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_eTaskGetStateImpl                          \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_eTaskGetState == 1 ) */
+    #endif /* if ( INCLUDE_eTaskGetState == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-void MPU_vTaskGetInfo( TaskHandle_t xTask,
-                       TaskStatus_t * pxTaskStatus,
-                       BaseType_t xGetFreeStackSpace,
-                       eTaskState eState ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskGetInfo( TaskHandle_t xTask,
+                               TaskStatus_t * pxTaskStatus,
+                               BaseType_t xGetFreeStackSpace,
+                               eTaskState eState ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskGetInfo( TaskHandle_t xTask,
-                       TaskStatus_t * pxTaskStatus,
-                       BaseType_t xGetFreeStackSpace,
-                       eTaskState eState ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskGetInfoImpl                          \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_vTaskGetInfo_Unpriv                           \n"
-        " MPU_vTaskGetInfo_Priv:                                \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_vTaskGetInfoImpl                            \n"
-        " MPU_vTaskGetInfo_Unpriv:                              \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskGetInfoImpl                           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskGetInfo( TaskHandle_t xTask,
+                               TaskStatus_t * pxTaskStatus,
+                               BaseType_t xGetFreeStackSpace,
+                               eTaskState eState ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskGetInfoImpl                          \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_vTaskGetInfo_Unpriv                           \n"
+                " MPU_vTaskGetInfo_Priv:                                \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_vTaskGetInfoImpl                            \n"
+                " MPU_vTaskGetInfo_Unpriv:                              \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskGetInfoImpl                           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
+    #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
+    #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
 
-TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetIdleTaskHandleImpl                \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTaskGetIdleTaskHandle_Unpriv                 \n"
-        " MPU_xTaskGetIdleTaskHandle_Priv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTaskGetIdleTaskHandleImpl                  \n"
-        " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetIdleTaskHandleImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetIdleTaskHandleImpl                \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xTaskGetIdleTaskHandle_Unpriv                 \n"
+                " MPU_xTaskGetIdleTaskHandle_Priv:                      \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xTaskGetIdleTaskHandleImpl                  \n"
+                " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetIdleTaskHandleImpl                 \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */
+    #endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_vTaskSuspend == 1 )
+    #if ( INCLUDE_vTaskSuspend == 1 )
 
-void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSuspendImpl                          \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_vTaskSuspend_Unpriv                           \n"
-        " MPU_vTaskSuspend_Priv:                                \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_vTaskSuspendImpl                            \n"
-        " MPU_vTaskSuspend_Unpriv:                              \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSuspendImpl                           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskSuspendImpl                          \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_vTaskSuspend_Unpriv                           \n"
+                " MPU_vTaskSuspend_Priv:                                \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_vTaskSuspendImpl                            \n"
+                " MPU_vTaskSuspend_Unpriv:                              \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskSuspendImpl                           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
+    #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_vTaskSuspend == 1 )
+    #if ( INCLUDE_vTaskSuspend == 1 )
 
-void MPU_vTaskResume( TaskHandle_t xTaskToResume ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskResume( TaskHandle_t xTaskToResume ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskResumeImpl                           \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_vTaskResume_Unpriv                            \n"
-        " MPU_vTaskResume_Priv:                                 \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_vTaskResumeImpl                             \n"
-        " MPU_vTaskResume_Unpriv:                               \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskResumeImpl                            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskResumeImpl                           \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_vTaskResume_Unpriv                            \n"
+                " MPU_vTaskResume_Priv:                                 \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_vTaskResumeImpl                             \n"
+                " MPU_vTaskResume_Unpriv:                               \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskResumeImpl                            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
+    #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
 /*-----------------------------------------------------------*/
 
-TickType_t MPU_xTaskGetTickCount( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    TickType_t MPU_xTaskGetTickCount( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TickType_t MPU_xTaskGetTickCount( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetTickCountImpl                     \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTaskGetTickCount_Unpriv                      \n"
-        " MPU_xTaskGetTickCount_Priv:                           \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTaskGetTickCountImpl                       \n"
-        " MPU_xTaskGetTickCount_Unpriv:                         \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetTickCountImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    TickType_t MPU_xTaskGetTickCount( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xTaskGetTickCountImpl                     \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xTaskGetTickCount_Unpriv                      \n"
+            " MPU_xTaskGetTickCount_Priv:                           \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xTaskGetTickCountImpl                       \n"
+            " MPU_xTaskGetTickCount_Unpriv:                         \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xTaskGetTickCountImpl                      \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetNumberOfTasksImpl                \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_uxTaskGetNumberOfTasks_Unpriv                 \n"
-        " MPU_uxTaskGetNumberOfTasks_Priv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_uxTaskGetNumberOfTasksImpl                  \n"
-        " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetNumberOfTasksImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_uxTaskGetNumberOfTasksImpl                \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_uxTaskGetNumberOfTasks_Unpriv                 \n"
+            " MPU_uxTaskGetNumberOfTasks_Priv:                      \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_uxTaskGetNumberOfTasksImpl                  \n"
+            " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_uxTaskGetNumberOfTasksImpl                 \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configGENERATE_RUN_TIME_STATS == 1 )
+    #if ( configGENERATE_RUN_TIME_STATS == 1 )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetRunTimeCounterImpl               \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_ulTaskGetRunTimeCounter_Unpriv                \n"
-        " MPU_ulTaskGetRunTimeCounter_Priv:                     \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_ulTaskGetRunTimeCounterImpl                 \n"
-        " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetRunTimeCounterImpl                \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetRunTimeCounterImpl               \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_ulTaskGetRunTimeCounter_Unpriv                \n"
+                " MPU_ulTaskGetRunTimeCounter_Priv:                     \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_ulTaskGetRunTimeCounterImpl                 \n"
+                " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetRunTimeCounterImpl                \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configGENERATE_RUN_TIME_STATS == 1 )
+    #if ( configGENERATE_RUN_TIME_STATS == 1 )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetRunTimePercentImpl               \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_ulTaskGetRunTimePercent_Unpriv                \n"
-        " MPU_ulTaskGetRunTimePercent_Priv:                     \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_ulTaskGetRunTimePercentImpl                 \n"
-        " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetRunTimePercentImpl                \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetRunTimePercentImpl               \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_ulTaskGetRunTimePercent_Unpriv                \n"
+                " MPU_ulTaskGetRunTimePercent_Priv:                     \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_ulTaskGetRunTimePercentImpl                 \n"
+                " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetRunTimePercentImpl                \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+    #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetIdleRunTimePercentImpl           \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv            \n"
-        " MPU_ulTaskGetIdleRunTimePercent_Priv:                 \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_ulTaskGetIdleRunTimePercentImpl             \n"
-        " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetIdleRunTimePercentImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetIdleRunTimePercentImpl           \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv            \n"
+                " MPU_ulTaskGetIdleRunTimePercent_Priv:                 \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_ulTaskGetIdleRunTimePercentImpl             \n"
+                " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetIdleRunTimePercentImpl            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+    #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetIdleRunTimeCounterImpl           \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv            \n"
-        " MPU_ulTaskGetIdleRunTimeCounter_Priv:                 \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_ulTaskGetIdleRunTimeCounterImpl             \n"
-        " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetIdleRunTimeCounterImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetIdleRunTimeCounterImpl           \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv            \n"
+                " MPU_ulTaskGetIdleRunTimeCounter_Priv:                 \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_ulTaskGetIdleRunTimeCounterImpl             \n"
+                " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetIdleRunTimeCounterImpl            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+    #if ( configUSE_APPLICATION_TASK_TAG == 1 )
 
-void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
-                                     TaskHookFunction_t pxHookFunction ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
+                                             TaskHookFunction_t pxHookFunction ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
-                                     TaskHookFunction_t pxHookFunction ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSetApplicationTaskTagImpl            \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_vTaskSetApplicationTaskTag_Unpriv             \n"
-        " MPU_vTaskSetApplicationTaskTag_Priv:                  \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_vTaskSetApplicationTaskTagImpl              \n"
-        " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSetApplicationTaskTagImpl             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
+                                             TaskHookFunction_t pxHookFunction ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskSetApplicationTaskTagImpl            \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_vTaskSetApplicationTaskTag_Unpriv             \n"
+                " MPU_vTaskSetApplicationTaskTag_Priv:                  \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_vTaskSetApplicationTaskTagImpl              \n"
+                " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskSetApplicationTaskTagImpl             \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
+    #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+    #if ( configUSE_APPLICATION_TASK_TAG == 1 )
 
-TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetApplicationTaskTagImpl            \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTaskGetApplicationTaskTag_Unpriv             \n"
-        " MPU_xTaskGetApplicationTaskTag_Priv:                  \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTaskGetApplicationTaskTagImpl              \n"
-        " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetApplicationTaskTagImpl             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetApplicationTaskTagImpl            \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xTaskGetApplicationTaskTag_Unpriv             \n"
+                " MPU_xTaskGetApplicationTaskTag_Priv:                  \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xTaskGetApplicationTaskTagImpl              \n"
+                " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetApplicationTaskTagImpl             \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
+    #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+    #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
 
-void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
-                                            BaseType_t xIndex,
-                                            void * pvValue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
+                                                    BaseType_t xIndex,
+                                                    void * pvValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
-                                            BaseType_t xIndex,
-                                            void * pvValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSetThreadLocalStoragePointerImpl     \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv      \n"
-        " MPU_vTaskSetThreadLocalStoragePointer_Priv:           \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_vTaskSetThreadLocalStoragePointerImpl       \n"
-        " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSetThreadLocalStoragePointerImpl      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
+                                                    BaseType_t xIndex,
+                                                    void * pvValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskSetThreadLocalStoragePointerImpl     \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv      \n"
+                " MPU_vTaskSetThreadLocalStoragePointer_Priv:           \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_vTaskSetThreadLocalStoragePointerImpl       \n"
+                " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskSetThreadLocalStoragePointerImpl      \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
+    #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+    #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
 
-void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
-                                               BaseType_t xIndex ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
+                                                       BaseType_t xIndex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
-                                               BaseType_t xIndex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pvTaskGetThreadLocalStoragePointerImpl    \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv     \n"
-        " MPU_pvTaskGetThreadLocalStoragePointer_Priv:          \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_pvTaskGetThreadLocalStoragePointerImpl      \n"
-        " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pvTaskGetThreadLocalStoragePointerImpl     \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
+                                                       BaseType_t xIndex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pvTaskGetThreadLocalStoragePointerImpl    \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv     \n"
+                " MPU_pvTaskGetThreadLocalStoragePointer_Priv:          \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_pvTaskGetThreadLocalStoragePointerImpl      \n"
+                " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pvTaskGetThreadLocalStoragePointerImpl     \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
+    #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
-                                      const UBaseType_t uxArraySize,
-                                      configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
+                                              const UBaseType_t uxArraySize,
+                                              configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
-                                      const UBaseType_t uxArraySize,
-                                      configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetSystemStateImpl                  \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_uxTaskGetSystemState_Unpriv                   \n"
-        " MPU_uxTaskGetSystemState_Priv:                        \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_uxTaskGetSystemStateImpl                    \n"
-        " MPU_uxTaskGetSystemState_Unpriv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetSystemStateImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
+                                              const UBaseType_t uxArraySize,
+                                              configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskGetSystemStateImpl                  \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_uxTaskGetSystemState_Unpriv                   \n"
+                " MPU_uxTaskGetSystemState_Priv:                        \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_uxTaskGetSystemStateImpl                    \n"
+                " MPU_uxTaskGetSystemState_Unpriv:                      \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskGetSystemStateImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
+    #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
+    #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
 
-UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetStackHighWaterMarkImpl           \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_uxTaskGetStackHighWaterMark_Unpriv            \n"
-        " MPU_uxTaskGetStackHighWaterMark_Priv:                 \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_uxTaskGetStackHighWaterMarkImpl             \n"
-        " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetStackHighWaterMarkImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskGetStackHighWaterMarkImpl           \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_uxTaskGetStackHighWaterMark_Unpriv            \n"
+                " MPU_uxTaskGetStackHighWaterMark_Priv:                 \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_uxTaskGetStackHighWaterMarkImpl             \n"
+                " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskGetStackHighWaterMarkImpl            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */
+    #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
+    #if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
 
-configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetStackHighWaterMark2Impl          \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv           \n"
-        " MPU_uxTaskGetStackHighWaterMark2_Priv:                \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_uxTaskGetStackHighWaterMark2Impl            \n"
-        " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetStackHighWaterMark2Impl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskGetStackHighWaterMark2Impl          \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv           \n"
+                " MPU_uxTaskGetStackHighWaterMark2_Priv:                \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_uxTaskGetStackHighWaterMark2Impl            \n"
+                " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskGetStackHighWaterMark2Impl           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */
+    #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
+    #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
 
-TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetCurrentTaskHandleImpl             \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTaskGetCurrentTaskHandle_Unpriv              \n"
-        " MPU_xTaskGetCurrentTaskHandle_Priv:                   \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTaskGetCurrentTaskHandleImpl               \n"
-        " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetCurrentTaskHandleImpl              \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetCurrentTaskHandleImpl             \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xTaskGetCurrentTaskHandle_Unpriv              \n"
+                " MPU_xTaskGetCurrentTaskHandle_Priv:                   \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xTaskGetCurrentTaskHandleImpl               \n"
+                " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetCurrentTaskHandleImpl              \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
+    #endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_xTaskGetSchedulerState == 1 )
+    #if ( INCLUDE_xTaskGetSchedulerState == 1 )
 
-BaseType_t MPU_xTaskGetSchedulerState( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGetSchedulerState( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGetSchedulerState( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetSchedulerStateImpl                \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTaskGetSchedulerState_Unpriv                 \n"
-        " MPU_xTaskGetSchedulerState_Priv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTaskGetSchedulerStateImpl                  \n"
-        " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetSchedulerStateImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGetSchedulerState( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetSchedulerStateImpl                \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xTaskGetSchedulerState_Unpriv                 \n"
+                " MPU_xTaskGetSchedulerState_Priv:                      \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xTaskGetSchedulerStateImpl                  \n"
+                " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetSchedulerStateImpl                 \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */
+    #endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */
 /*-----------------------------------------------------------*/
 
-void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSetTimeOutStateImpl                  \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_vTaskSetTimeOutState_Unpriv                   \n"
-        " MPU_vTaskSetTimeOutState_Priv:                        \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_vTaskSetTimeOutStateImpl                    \n"
-        " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSetTimeOutStateImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_vTaskSetTimeOutStateImpl                  \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_vTaskSetTimeOutState_Unpriv                   \n"
+            " MPU_vTaskSetTimeOutState_Priv:                        \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_vTaskSetTimeOutStateImpl                    \n"
+            " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_vTaskSetTimeOutStateImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
-                                     TickType_t * const pxTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
+                                         TickType_t * const pxTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
-                                     TickType_t * const pxTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskCheckForTimeOutImpl                  \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTaskCheckForTimeOut_Unpriv                   \n"
-        " MPU_xTaskCheckForTimeOut_Priv:                        \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTaskCheckForTimeOutImpl                    \n"
-        " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskCheckForTimeOutImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
+                                         TickType_t * const pxTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xTaskCheckForTimeOutImpl                  \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xTaskCheckForTimeOut_Unpriv                   \n"
+            " MPU_xTaskCheckForTimeOut_Priv:                        \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xTaskCheckForTimeOutImpl                    \n"
+            " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xTaskCheckForTimeOutImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                   UBaseType_t uxIndexToNotify,
-                                   uint32_t ulValue,
-                                   eNotifyAction eAction,
-                                   uint32_t * pulPreviousNotificationValue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
+                                           UBaseType_t uxIndexToNotify,
+                                           uint32_t ulValue,
+                                           eNotifyAction eAction,
+                                           uint32_t * pulPreviousNotificationValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                   UBaseType_t uxIndexToNotify,
-                                   uint32_t ulValue,
-                                   eNotifyAction eAction,
-                                   uint32_t * pulPreviousNotificationValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGenericNotifyImpl                    \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTaskGenericNotify_Unpriv                     \n"
-        " MPU_xTaskGenericNotify_Priv:                          \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTaskGenericNotifyImpl                      \n"
-        " MPU_xTaskGenericNotify_Unpriv:                        \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGenericNotifyImpl                     \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
+                                           UBaseType_t uxIndexToNotify,
+                                           uint32_t ulValue,
+                                           eNotifyAction eAction,
+                                           uint32_t * pulPreviousNotificationValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGenericNotifyImpl                    \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xTaskGenericNotify_Unpriv                     \n"
+                " MPU_xTaskGenericNotify_Priv:                          \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xTaskGenericNotifyImpl                      \n"
+                " MPU_xTaskGenericNotify_Unpriv:                        \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGenericNotifyImpl                     \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                       uint32_t ulBitsToClearOnEntry,
-                                       uint32_t ulBitsToClearOnExit,
-                                       uint32_t * pulNotificationValue,
-                                       TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
+                                               uint32_t ulBitsToClearOnEntry,
+                                               uint32_t ulBitsToClearOnExit,
+                                               uint32_t * pulNotificationValue,
+                                               TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                       uint32_t ulBitsToClearOnEntry,
-                                       uint32_t ulBitsToClearOnExit,
-                                       uint32_t * pulNotificationValue,
-                                       TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGenericNotifyWaitImpl                \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTaskGenericNotifyWait_Unpriv                 \n"
-        " MPU_xTaskGenericNotifyWait_Priv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTaskGenericNotifyWaitImpl                  \n"
-        " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGenericNotifyWaitImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
+                                               uint32_t ulBitsToClearOnEntry,
+                                               uint32_t ulBitsToClearOnExit,
+                                               uint32_t * pulNotificationValue,
+                                               TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGenericNotifyWaitImpl                \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xTaskGenericNotifyWait_Unpriv                 \n"
+                " MPU_xTaskGenericNotifyWait_Priv:                      \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xTaskGenericNotifyWaitImpl                  \n"
+                " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGenericNotifyWaitImpl                 \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
-                                      BaseType_t xClearCountOnExit,
-                                      TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
+                                              BaseType_t xClearCountOnExit,
+                                              TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
-                                      BaseType_t xClearCountOnExit,
-                                      TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGenericNotifyTakeImpl               \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_ulTaskGenericNotifyTake_Unpriv                \n"
-        " MPU_ulTaskGenericNotifyTake_Priv:                     \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_ulTaskGenericNotifyTakeImpl                 \n"
-        " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGenericNotifyTakeImpl                \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
+                                              BaseType_t xClearCountOnExit,
+                                              TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGenericNotifyTakeImpl               \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_ulTaskGenericNotifyTake_Unpriv                \n"
+                " MPU_ulTaskGenericNotifyTake_Priv:                     \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_ulTaskGenericNotifyTakeImpl                 \n"
+                " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGenericNotifyTakeImpl                \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
-                                             UBaseType_t uxIndexToClear ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
+                                                     UBaseType_t uxIndexToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
-                                             UBaseType_t uxIndexToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGenericNotifyStateClearImpl          \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTaskGenericNotifyStateClear_Unpriv           \n"
-        " MPU_xTaskGenericNotifyStateClear_Priv:                \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTaskGenericNotifyStateClearImpl            \n"
-        " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGenericNotifyStateClearImpl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
+                                                     UBaseType_t uxIndexToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGenericNotifyStateClearImpl          \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xTaskGenericNotifyStateClear_Unpriv           \n"
+                " MPU_xTaskGenericNotifyStateClear_Priv:                \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xTaskGenericNotifyStateClearImpl            \n"
+                " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGenericNotifyStateClearImpl           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
-                                            UBaseType_t uxIndexToClear,
-                                            uint32_t ulBitsToClear ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
+                                                    UBaseType_t uxIndexToClear,
+                                                    uint32_t ulBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
-                                            UBaseType_t uxIndexToClear,
-                                            uint32_t ulBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGenericNotifyValueClearImpl         \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_ulTaskGenericNotifyValueClear_Unpriv          \n"
-        " MPU_ulTaskGenericNotifyValueClear_Priv:               \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_ulTaskGenericNotifyValueClearImpl           \n"
-        " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGenericNotifyValueClearImpl          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
+                                                    UBaseType_t uxIndexToClear,
+                                                    uint32_t ulBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGenericNotifyValueClearImpl         \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_ulTaskGenericNotifyValueClear_Unpriv          \n"
+                " MPU_ulTaskGenericNotifyValueClear_Priv:               \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_ulTaskGenericNotifyValueClearImpl           \n"
+                " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGenericNotifyValueClearImpl          \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
-                                  const void * const pvItemToQueue,
-                                  TickType_t xTicksToWait,
-                                  const BaseType_t xCopyPosition ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
+                                      const void * const pvItemToQueue,
+                                      TickType_t xTicksToWait,
+                                      const BaseType_t xCopyPosition ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
-                                  const void * const pvItemToQueue,
-                                  TickType_t xTicksToWait,
-                                  const BaseType_t xCopyPosition ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueGenericSendImpl                     \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xQueueGenericSend_Unpriv                      \n"
-        " MPU_xQueueGenericSend_Priv:                           \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xQueueGenericSendImpl                       \n"
-        " MPU_xQueueGenericSend_Unpriv:                         \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueGenericSendImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
+                                      const void * const pvItemToQueue,
+                                      TickType_t xTicksToWait,
+                                      const BaseType_t xCopyPosition ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueueGenericSendImpl                     \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xQueueGenericSend_Unpriv                      \n"
+            " MPU_xQueueGenericSend_Priv:                           \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xQueueGenericSendImpl                       \n"
+            " MPU_xQueueGenericSend_Unpriv:                         \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueueGenericSendImpl                      \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxQueueMessagesWaitingImpl                \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_uxQueueMessagesWaiting_Unpriv                 \n"
-        " MPU_uxQueueMessagesWaiting_Priv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_uxQueueMessagesWaitingImpl                  \n"
-        " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxQueueMessagesWaitingImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_uxQueueMessagesWaitingImpl                \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_uxQueueMessagesWaiting_Unpriv                 \n"
+            " MPU_uxQueueMessagesWaiting_Priv:                      \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_uxQueueMessagesWaitingImpl                  \n"
+            " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_uxQueueMessagesWaitingImpl                 \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxQueueSpacesAvailableImpl                \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_uxQueueSpacesAvailable_Unpriv                 \n"
-        " MPU_uxQueueSpacesAvailable_Priv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_uxQueueSpacesAvailableImpl                  \n"
-        " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxQueueSpacesAvailableImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_uxQueueSpacesAvailableImpl                \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_uxQueueSpacesAvailable_Unpriv                 \n"
+            " MPU_uxQueueSpacesAvailable_Priv:                      \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_uxQueueSpacesAvailableImpl                  \n"
+            " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_uxQueueSpacesAvailableImpl                 \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
-                              void * const pvBuffer,
-                              TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
+                                  void * const pvBuffer,
+                                  TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
-                              void * const pvBuffer,
-                              TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueReceiveImpl                         \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xQueueReceive_Unpriv                          \n"
-        " MPU_xQueueReceive_Priv:                               \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xQueueReceiveImpl                           \n"
-        " MPU_xQueueReceive_Unpriv:                             \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueReceiveImpl                          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
+                                  void * const pvBuffer,
+                                  TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueueReceiveImpl                         \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xQueueReceive_Unpriv                          \n"
+            " MPU_xQueueReceive_Priv:                               \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xQueueReceiveImpl                           \n"
+            " MPU_xQueueReceive_Unpriv:                             \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueueReceiveImpl                          \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
-                           void * const pvBuffer,
-                           TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
+                               void * const pvBuffer,
+                               TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
-                           void * const pvBuffer,
-                           TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueuePeekImpl                            \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xQueuePeek_Unpriv                             \n"
-        " MPU_xQueuePeek_Priv:                                  \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xQueuePeekImpl                              \n"
-        " MPU_xQueuePeek_Unpriv:                                \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueuePeekImpl                             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
+                               void * const pvBuffer,
+                               TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueuePeekImpl                            \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xQueuePeek_Unpriv                             \n"
+            " MPU_xQueuePeek_Priv:                                  \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xQueuePeekImpl                              \n"
+            " MPU_xQueuePeek_Unpriv:                                \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueuePeekImpl                             \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
-                                    TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
+                                        TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
-                                    TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueSemaphoreTakeImpl                   \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xQueueSemaphoreTake_Unpriv                    \n"
-        " MPU_xQueueSemaphoreTake_Priv:                         \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xQueueSemaphoreTakeImpl                     \n"
-        " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueSemaphoreTakeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
+                                        TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueueSemaphoreTakeImpl                   \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xQueueSemaphoreTake_Unpriv                    \n"
+            " MPU_xQueueSemaphoreTake_Priv:                         \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xQueueSemaphoreTakeImpl                     \n"
+            " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueueSemaphoreTakeImpl                    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+    #if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
 
-TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueGetMutexHolderImpl                  \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xQueueGetMutexHolder_Unpriv                   \n"
-        " MPU_xQueueGetMutexHolder_Priv:                        \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xQueueGetMutexHolderImpl                    \n"
-        " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueGetMutexHolderImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueGetMutexHolderImpl                  \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xQueueGetMutexHolder_Unpriv                   \n"
+                " MPU_xQueueGetMutexHolder_Priv:                        \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xQueueGetMutexHolderImpl                    \n"
+                " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueGetMutexHolderImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */
+    #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+    #if ( configUSE_RECURSIVE_MUTEXES == 1 )
 
-BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
-                                         TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+                                                 TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+        BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+                                                 TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueTakeMutexRecursiveImpl              \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xQueueTakeMutexRecursive_Unpriv               \n"
+                " MPU_xQueueTakeMutexRecursive_Priv:                    \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xQueueTakeMutexRecursiveImpl                \n"
+                " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueTakeMutexRecursiveImpl               \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_RECURSIVE_MUTEXES == 1 )
+
+        BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueGiveMutexRecursiveImpl              \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xQueueGiveMutexRecursive_Unpriv               \n"
+                " MPU_xQueueGiveMutexRecursive_Priv:                    \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xQueueGiveMutexRecursiveImpl                \n"
+                " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueGiveMutexRecursiveImpl               \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_QUEUE_SETS == 1 )
+
+        QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
+                                                        const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
+                                                        const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueSelectFromSetImpl                   \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xQueueSelectFromSet_Unpriv                    \n"
+                " MPU_xQueueSelectFromSet_Priv:                         \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xQueueSelectFromSetImpl                     \n"
+                " MPU_xQueueSelectFromSet_Unpriv:                       \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueSelectFromSetImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_QUEUE_SETS == 1 )
+
+        BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                                       QueueSetHandle_t xQueueSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                                       QueueSetHandle_t xQueueSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueAddToSetImpl                        \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xQueueAddToSet_Unpriv                         \n"
+                " MPU_xQueueAddToSet_Priv:                              \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xQueueAddToSetImpl                          \n"
+                " MPU_xQueueAddToSet_Unpriv:                            \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueAddToSetImpl                         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+        void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
+                                      const char * pcName ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
+                                      const char * pcName ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vQueueAddToRegistryImpl                   \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_vQueueAddToRegistry_Unpriv                    \n"
+                " MPU_vQueueAddToRegistry_Priv:                         \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_vQueueAddToRegistryImpl                     \n"
+                " MPU_vQueueAddToRegistry_Unpriv:                       \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vQueueAddToRegistryImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+        void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vQueueUnregisterQueueImpl                 \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_vQueueUnregisterQueue_Unpriv                  \n"
+                " MPU_vQueueUnregisterQueue_Priv:                       \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_vQueueUnregisterQueueImpl                   \n"
+                " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vQueueUnregisterQueueImpl                  \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+        const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pcQueueGetNameImpl                        \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_pcQueueGetName_Unpriv                         \n"
+                " MPU_pcQueueGetName_Priv:                              \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_pcQueueGetNameImpl                          \n"
+                " MPU_pcQueueGetName_Unpriv:                            \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pcQueueGetNameImpl                         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pvTimerGetTimerIDImpl                     \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_pvTimerGetTimerID_Unpriv                      \n"
+                " MPU_pvTimerGetTimerID_Priv:                           \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_pvTimerGetTimerIDImpl                       \n"
+                " MPU_pvTimerGetTimerID_Unpriv:                         \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pvTimerGetTimerIDImpl                      \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
+                                   void * pvNewID ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
+                                   void * pvNewID ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTimerSetTimerIDImpl                      \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_vTimerSetTimerID_Unpriv                       \n"
+                " MPU_vTimerSetTimerID_Priv:                            \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_vTimerSetTimerIDImpl                        \n"
+                " MPU_vTimerSetTimerID_Unpriv:                          \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTimerSetTimerIDImpl                       \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerIsTimerActiveImpl                   \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xTimerIsTimerActive_Unpriv                    \n"
+                " MPU_xTimerIsTimerActive_Priv:                         \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xTimerIsTimerActiveImpl                     \n"
+                " MPU_xTimerIsTimerActive_Unpriv:                       \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerIsTimerActiveImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetTimerDaemonTaskHandleImpl        \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv         \n"
+                " MPU_xTimerGetTimerDaemonTaskHandle_Priv:              \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xTimerGetTimerDaemonTaskHandleImpl          \n"
+                " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetTimerDaemonTaskHandleImpl         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                                     const BaseType_t xCommandID,
+                                                     const TickType_t xOptionalValue,
+                                                     BaseType_t * const pxHigherPriorityTaskWoken,
+                                                     const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                                     const BaseType_t xCommandID,
+                                                     const TickType_t xOptionalValue,
+                                                     BaseType_t * const pxHigherPriorityTaskWoken,
+                                                     const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                               \n"
+                " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
+                "                                                               \n"
+                " push {r0, r1}                                                 \n"
+                " mrs r0, control                                               \n"
+                " movs r1, #1                                                   \n"
+                " tst r0, r1                                                    \n"
+                " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
+                " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
+                "     pop {r0, r1}                                              \n"
+                "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
+                " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
+                "     pop {r0, r1}                                              \n"
+                "     svc %0                                                    \n"
+                "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
+                "     svc %1                                                    \n"
+                "     bx lr                                                     \n"
+                "                                                               \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pcTimerGetNameImpl                        \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_pcTimerGetName_Unpriv                         \n"
+                " MPU_pcTimerGetName_Priv:                              \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_pcTimerGetNameImpl                          \n"
+                " MPU_pcTimerGetName_Unpriv:                            \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pcTimerGetNameImpl                         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
+                                      const BaseType_t uxAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
+                                      const BaseType_t uxAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTimerSetReloadModeImpl                   \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_vTimerSetReloadMode_Unpriv                    \n"
+                " MPU_vTimerSetReloadMode_Priv:                         \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_vTimerSetReloadModeImpl                     \n"
+                " MPU_vTimerSetReloadMode_Unpriv:                       \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTimerSetReloadModeImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetReloadModeImpl                   \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xTimerGetReloadMode_Unpriv                    \n"
+                " MPU_xTimerGetReloadMode_Priv:                         \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xTimerGetReloadModeImpl                     \n"
+                " MPU_xTimerGetReloadMode_Unpriv:                       \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetReloadModeImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTimerGetReloadModeImpl                  \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_uxTimerGetReloadMode_Unpriv                   \n"
+                " MPU_uxTimerGetReloadMode_Priv:                        \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_uxTimerGetReloadModeImpl                    \n"
+                " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTimerGetReloadModeImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetPeriodImpl                       \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xTimerGetPeriod_Unpriv                        \n"
+                " MPU_xTimerGetPeriod_Priv:                             \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xTimerGetPeriodImpl                         \n"
+                " MPU_xTimerGetPeriod_Unpriv:                           \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetPeriodImpl                        \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetExpiryTimeImpl                   \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xTimerGetExpiryTime_Unpriv                    \n"
+                " MPU_xTimerGetExpiryTime_Priv:                         \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xTimerGetExpiryTimeImpl                     \n"
+                " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetExpiryTimeImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         const BaseType_t xClearOnExit,
+                                         const BaseType_t xWaitForAllBits,
+                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         const BaseType_t xClearOnExit,
+                                         const BaseType_t xWaitForAllBits,
                                          TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueTakeMutexRecursiveImpl              \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xQueueTakeMutexRecursive_Unpriv               \n"
-        " MPU_xQueueTakeMutexRecursive_Priv:                    \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xQueueTakeMutexRecursiveImpl                \n"
-        " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueTakeMutexRecursiveImpl               \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupWaitBitsImpl                   \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
+            " MPU_xEventGroupWaitBits_Priv:                         \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xEventGroupWaitBitsImpl                     \n"
+            " MPU_xEventGroupWaitBits_Unpriv:                       \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupWaitBitsImpl                    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                          const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueGiveMutexRecursiveImpl              \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xQueueGiveMutexRecursive_Unpriv               \n"
-        " MPU_xQueueGiveMutexRecursive_Priv:                    \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xQueueGiveMutexRecursiveImpl                \n"
-        " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueGiveMutexRecursiveImpl               \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                          const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupClearBitsImpl                  \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xEventGroupClearBits_Unpriv                   \n"
+            " MPU_xEventGroupClearBits_Priv:                        \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xEventGroupClearBitsImpl                    \n"
+            " MPU_xEventGroupClearBits_Unpriv:                      \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupClearBitsImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_QUEUE_SETS == 1 )
+    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                        const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
-                                                const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
-                                                const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueSelectFromSetImpl                   \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xQueueSelectFromSet_Unpriv                    \n"
-        " MPU_xQueueSelectFromSet_Priv:                         \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xQueueSelectFromSetImpl                     \n"
-        " MPU_xQueueSelectFromSet_Unpriv:                       \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueSelectFromSetImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                        const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupSetBitsImpl                    \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xEventGroupSetBits_Unpriv                     \n"
+            " MPU_xEventGroupSetBits_Priv:                          \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xEventGroupSetBitsImpl                      \n"
+            " MPU_xEventGroupSetBits_Unpriv:                        \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupSetBitsImpl                     \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_QUEUE_SETS == 1 )
-
-BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
-                               QueueSetHandle_t xQueueSet ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
-                               QueueSetHandle_t xQueueSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueAddToSetImpl                        \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xQueueAddToSet_Unpriv                         \n"
-        " MPU_xQueueAddToSet_Priv:                              \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xQueueAddToSetImpl                          \n"
-        " MPU_xQueueAddToSet_Unpriv:                            \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueAddToSetImpl                         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_QUEUE_SETS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
-                              const char * pcName ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
-                              const char * pcName ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vQueueAddToRegistryImpl                   \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_vQueueAddToRegistry_Unpriv                    \n"
-        " MPU_vQueueAddToRegistry_Priv:                         \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_vQueueAddToRegistryImpl                     \n"
-        " MPU_vQueueAddToRegistry_Unpriv:                       \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vQueueAddToRegistryImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vQueueUnregisterQueueImpl                 \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_vQueueUnregisterQueue_Unpriv                  \n"
-        " MPU_vQueueUnregisterQueue_Priv:                       \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_vQueueUnregisterQueueImpl                   \n"
-        " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vQueueUnregisterQueueImpl                  \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pcQueueGetNameImpl                        \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_pcQueueGetName_Unpriv                         \n"
-        " MPU_pcQueueGetName_Priv:                              \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_pcQueueGetNameImpl                          \n"
-        " MPU_pcQueueGetName_Unpriv:                            \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pcQueueGetNameImpl                         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pvTimerGetTimerIDImpl                     \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_pvTimerGetTimerID_Unpriv                      \n"
-        " MPU_pvTimerGetTimerID_Priv:                           \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_pvTimerGetTimerIDImpl                       \n"
-        " MPU_pvTimerGetTimerID_Unpriv:                         \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pvTimerGetTimerIDImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
-                           void * pvNewID ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
-                           void * pvNewID ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTimerSetTimerIDImpl                      \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_vTimerSetTimerID_Unpriv                       \n"
-        " MPU_vTimerSetTimerID_Priv:                            \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_vTimerSetTimerIDImpl                        \n"
-        " MPU_vTimerSetTimerID_Unpriv:                          \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTimerSetTimerIDImpl                       \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerIsTimerActiveImpl                   \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTimerIsTimerActive_Unpriv                    \n"
-        " MPU_xTimerIsTimerActive_Priv:                         \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTimerIsTimerActiveImpl                     \n"
-        " MPU_xTimerIsTimerActive_Unpriv:                       \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerIsTimerActiveImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetTimerDaemonTaskHandleImpl        \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv         \n"
-        " MPU_xTimerGetTimerDaemonTaskHandle_Priv:              \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTimerGetTimerDaemonTaskHandleImpl          \n"
-        " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetTimerDaemonTaskHandleImpl         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                             const BaseType_t xCommandID,
-                                             const TickType_t xOptionalValue,
-                                             BaseType_t * const pxHigherPriorityTaskWoken,
-                                             const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                             const BaseType_t xCommandID,
-                                             const TickType_t xOptionalValue,
-                                             BaseType_t * const pxHigherPriorityTaskWoken,
-                                             const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                               \n"
-        " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
-        "                                                               \n"
-        " push {r0, r1}                                                 \n"
-        " mrs r0, control                                               \n"
-        " movs r1, #1                                                   \n"
-        " tst r0, r1                                                    \n"
-        " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
-        " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
-        "     pop {r0, r1}                                              \n"
-        "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
-        " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
-        "     pop {r0, r1}                                              \n"
-        "     svc %0                                                    \n"
-        "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
-        "     svc %1                                                    \n"
-        "     bx lr                                                     \n"
-        "                                                               \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pcTimerGetNameImpl                        \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_pcTimerGetName_Unpriv                         \n"
-        " MPU_pcTimerGetName_Priv:                              \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_pcTimerGetNameImpl                          \n"
-        " MPU_pcTimerGetName_Unpriv:                            \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pcTimerGetNameImpl                         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                              const BaseType_t uxAutoReload ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                              const BaseType_t uxAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTimerSetReloadModeImpl                   \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_vTimerSetReloadMode_Unpriv                    \n"
-        " MPU_vTimerSetReloadMode_Priv:                         \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_vTimerSetReloadModeImpl                     \n"
-        " MPU_vTimerSetReloadMode_Unpriv:                       \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTimerSetReloadModeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetReloadModeImpl                   \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTimerGetReloadMode_Unpriv                    \n"
-        " MPU_xTimerGetReloadMode_Priv:                         \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTimerGetReloadModeImpl                     \n"
-        " MPU_xTimerGetReloadMode_Unpriv:                       \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetReloadModeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTimerGetReloadModeImpl                  \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_uxTimerGetReloadMode_Unpriv                   \n"
-        " MPU_uxTimerGetReloadMode_Priv:                        \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_uxTimerGetReloadModeImpl                    \n"
-        " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTimerGetReloadModeImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetPeriodImpl                       \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTimerGetPeriod_Unpriv                        \n"
-        " MPU_xTimerGetPeriod_Priv:                             \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTimerGetPeriodImpl                         \n"
-        " MPU_xTimerGetPeriod_Unpriv:                           \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetPeriodImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetExpiryTimeImpl                   \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTimerGetExpiryTime_Unpriv                    \n"
-        " MPU_xTimerGetExpiryTime_Priv:                         \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTimerGetExpiryTimeImpl                     \n"
-        " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetExpiryTimeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                     const EventBits_t uxBitsToSet,
                                      const EventBits_t uxBitsToWaitFor,
-                                     const BaseType_t xClearOnExit,
-                                     const BaseType_t xWaitForAllBits,
-                                     TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                     const EventBits_t uxBitsToSet,
                                      const EventBits_t uxBitsToWaitFor,
-                                     const BaseType_t xClearOnExit,
-                                     const BaseType_t xWaitForAllBits,
                                      TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupWaitBitsImpl                   \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
-        " MPU_xEventGroupWaitBits_Priv:                         \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xEventGroupWaitBitsImpl                     \n"
-        " MPU_xEventGroupWaitBits_Unpriv:                       \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupWaitBitsImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupSyncImpl                       \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xEventGroupSync_Unpriv                        \n"
+            " MPU_xEventGroupSync_Priv:                             \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xEventGroupSyncImpl                         \n"
+            " MPU_xEventGroupSync_Unpriv:                           \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupSyncImpl                        \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                      const EventBits_t uxBitsToClear ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                      const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupClearBitsImpl                  \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xEventGroupClearBits_Unpriv                   \n"
-        " MPU_xEventGroupClearBits_Priv:                        \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xEventGroupClearBitsImpl                    \n"
-        " MPU_xEventGroupClearBits_Unpriv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupClearBitsImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxEventGroupGetNumberImpl                 \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_uxEventGroupGetNumber_Unpriv                  \n"
+                " MPU_uxEventGroupGetNumber_Priv:                       \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_uxEventGroupGetNumberImpl                   \n"
+                " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxEventGroupGetNumberImpl                  \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
 /*-----------------------------------------------------------*/
 
-EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                    const EventBits_t uxBitsToSet ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                    const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupSetBitsImpl                    \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xEventGroupSetBits_Unpriv                     \n"
-        " MPU_xEventGroupSetBits_Priv:                          \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xEventGroupSetBitsImpl                      \n"
-        " MPU_xEventGroupSetBits_Unpriv:                        \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupSetBitsImpl                     \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vEventGroupSetNumber( void * xEventGroup,
+                                       UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vEventGroupSetNumber( void * xEventGroup,
+                                       UBaseType_t uxEventGroupNumber ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vEventGroupSetNumberImpl                  \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_vEventGroupSetNumber_Unpriv                   \n"
+                " MPU_vEventGroupSetNumber_Priv:                        \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_vEventGroupSetNumberImpl                    \n"
+                " MPU_vEventGroupSetNumber_Unpriv:                      \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vEventGroupSetNumberImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
 /*-----------------------------------------------------------*/
 
-EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                 const EventBits_t uxBitsToSet,
-                                 const EventBits_t uxBitsToWaitFor,
-                                 TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                  const void * pvTxData,
+                                  size_t xDataLengthBytes,
+                                  TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                 const EventBits_t uxBitsToSet,
-                                 const EventBits_t uxBitsToWaitFor,
-                                 TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupSyncImpl                       \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xEventGroupSync_Unpriv                        \n"
-        " MPU_xEventGroupSync_Priv:                             \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xEventGroupSyncImpl                         \n"
-        " MPU_xEventGroupSync_Unpriv:                           \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupSyncImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                  const void * pvTxData,
+                                  size_t xDataLengthBytes,
+                                  TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferSendImpl                     \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xStreamBufferSend_Unpriv                      \n"
+            " MPU_xStreamBufferSend_Priv:                           \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xStreamBufferSendImpl                       \n"
+            " MPU_xStreamBufferSend_Unpriv:                         \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferSendImpl                      \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                     void * pvRxData,
+                                     size_t xBufferLengthBytes,
+                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxEventGroupGetNumberImpl                 \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_uxEventGroupGetNumber_Unpriv                  \n"
-        " MPU_uxEventGroupGetNumber_Priv:                       \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_uxEventGroupGetNumberImpl                   \n"
-        " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxEventGroupGetNumberImpl                  \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                     void * pvRxData,
+                                     size_t xBufferLengthBytes,
+                                     TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferReceiveImpl                  \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xStreamBufferReceive_Unpriv                   \n"
+            " MPU_xStreamBufferReceive_Priv:                        \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xStreamBufferReceiveImpl                    \n"
+            " MPU_xStreamBufferReceive_Unpriv:                      \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferReceiveImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vEventGroupSetNumber( void * xEventGroup,
-                               UBaseType_t uxEventGroupNumber ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vEventGroupSetNumber( void * xEventGroup,
-                               UBaseType_t uxEventGroupNumber ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vEventGroupSetNumberImpl                  \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_vEventGroupSetNumber_Unpriv                   \n"
-        " MPU_vEventGroupSetNumber_Priv:                        \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_vEventGroupSetNumberImpl                    \n"
-        " MPU_vEventGroupSetNumber_Unpriv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vEventGroupSetNumberImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferIsFullImpl                   \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
+            " MPU_xStreamBufferIsFull_Priv:                         \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xStreamBufferIsFullImpl                     \n"
+            " MPU_xStreamBufferIsFull_Unpriv:                       \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferIsFullImpl                    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                              const void * pvTxData,
-                              size_t xDataLengthBytes,
-                              TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                              const void * pvTxData,
-                              size_t xDataLengthBytes,
-                              TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferSendImpl                     \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xStreamBufferSend_Unpriv                      \n"
-        " MPU_xStreamBufferSend_Priv:                           \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xStreamBufferSendImpl                       \n"
-        " MPU_xStreamBufferSend_Unpriv:                         \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferSendImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
+            " MPU_xStreamBufferIsEmpty_Priv:                        \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xStreamBufferIsEmptyImpl                    \n"
+            " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferIsEmptyImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                 void * pvRxData,
-                                 size_t xBufferLengthBytes,
-                                 TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                 void * pvRxData,
-                                 size_t xBufferLengthBytes,
-                                 TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferReceiveImpl                  \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xStreamBufferReceive_Unpriv                   \n"
-        " MPU_xStreamBufferReceive_Priv:                        \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xStreamBufferReceiveImpl                    \n"
-        " MPU_xStreamBufferReceive_Unpriv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferReceiveImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
+            " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
+            " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferSpacesAvailableImpl           \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferIsFullImpl                   \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
-        " MPU_xStreamBufferIsFull_Priv:                         \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xStreamBufferIsFullImpl                     \n"
-        " MPU_xStreamBufferIsFull_Unpriv:                       \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferIsFullImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
+            " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xStreamBufferBytesAvailableImpl             \n"
+            " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferBytesAvailableImpl            \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                 size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
-        " MPU_xStreamBufferIsEmpty_Priv:                        \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xStreamBufferIsEmptyImpl                    \n"
-        " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferIsEmptyImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                 size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
+            " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
+            " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferSetTriggerLevelImpl           \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
-        " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
-        " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferSpacesAvailableImpl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
-size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
-        " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xStreamBufferBytesAvailableImpl             \n"
-        " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferBytesAvailableImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                             size_t xTriggerLevel ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                             size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
-        " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
-        " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferSetTriggerLevelImpl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
-size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
-        " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
-        " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferNextMessageLengthBytesImpl    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
+            " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
+            " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferNextMessageLengthBytesImpl    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portasm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portasm.c
index 64a24f527..d452c33b0 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portasm.c
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portasm.c
@@ -46,133 +46,133 @@
 
 #if ( configENABLE_MPU == 1 )
 
-void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        " .syntax unified                                 \n"
-        "                                                 \n"
-        " program_mpu_first_task:                         \n"
-        "    ldr r3, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB.*/
-        "                                                 \n"
-        "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-        "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
-        "    movs r3, #1                                  \n" /* r3 = 1. */
-        "    bics r2, r3                                  \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
-        "    str r2, [r1]                                 \n" /* Disable MPU. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
-        "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-        "    ldr r2, xMAIR0Const2                         \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-        "    str r1, [r2]                                 \n" /* Program MAIR0. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-        "    ldr r1, xRNRConst2                           \n" /* r1 = 0xe000ed98 [Location of RNR]. */
-        "                                                 \n"
-        "    movs r3, #4                                  \n" /* r3 = 4. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 4. */
-        "    ldmia r0!, {r4-r5}                           \n" /* Read first set of RBAR/RLAR registers from TCB. */
-        "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "    stmia r2!, {r4-r5}                           \n" /* Write first set of RBAR/RLAR registers. */
-        "    movs r3, #5                                  \n" /* r3 = 5. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 5. */
-        "    ldmia r0!, {r4-r5}                           \n" /* Read second set of RBAR/RLAR registers from TCB. */
-        "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "    stmia r2!, {r4-r5}                           \n" /* Write second set of RBAR/RLAR registers. */
-        "    movs r3, #6                                  \n" /* r3 = 6. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 6. */
-        "    ldmia r0!, {r4-r5}                           \n" /* Read third set of RBAR/RLAR registers from TCB. */
-        "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "    stmia r2!, {r4-r5}                           \n" /* Write third set of RBAR/RLAR registers. */
-        "    movs r3, #7                                  \n" /* r3 = 6. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 7. */
-        "    ldmia r0!, {r4-r5}                           \n" /* Read fourth set of RBAR/RLAR registers from TCB. */
-        "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "    stmia r2!, {r4-r5}                           \n" /* Write fourth set of RBAR/RLAR registers. */
-        "                                                 \n"
-        "   ldr r1, xMPUCTRLConst2                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
-        "   movs r3, #1                                   \n" /* r3 = 1. */
-        "   orrs r2, r3                                   \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
-        "   str r2, [r1]                                  \n" /* Enable MPU. */
-        "   dsb                                           \n" /* Force memory writes before continuing. */
-        "                                                 \n"
-        " restore_context_first_task:                     \n"
-        "    ldr r3, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r1, [r3]                                 \n" /* r1 = pxCurrentTCB.*/
-        "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
-        "                                                 \n"
-        " restore_special_regs_first_task:                \n"
-        "    subs r2, #20                                 \n"
-        "    ldmia r2!, {r0, r3-r6}                       \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, r6 = LR. */
-        "    subs r2, #20                                 \n"
-        "    msr psp, r3                                  \n"
-        "    msr psplim, r4                               \n"
-        "    msr control, r5                              \n"
-        "    mov lr, r6                                   \n"
-        "    ldr r4, xSecureContextConst2                 \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-        "    str r0, [r4]                                 \n" /* Restore xSecureContext. */
-        "                                                 \n"
-        " restore_general_regs_first_task:                \n"
-        "    subs r2, #32                                 \n"
-        "    ldmia r2!, {r4-r7}                           \n" /* r4-r7 contain half of the hardware saved context. */
-        "    stmia r3!, {r4-r7}                           \n" /* Copy half of the the hardware saved context on the task stack. */
-        "    ldmia r2!, {r4-r7}                           \n" /* r4-r7 contain rest half of the hardware saved context. */
-        "    stmia r3!, {r4-r7}                           \n" /* Copy rest half of the the hardware saved context on the task stack. */
-        "    subs r2, #48                                 \n"
-        "    ldmia r2!, {r4-r7}                           \n" /* Restore r8-r11. */
-        "    mov r8, r4                                   \n" /* r8 = r4. */
-        "    mov r9, r5                                   \n" /* r9 = r5. */
-        "    mov r10, r6                                  \n" /* r10 = r6. */
-        "    mov r11, r7                                  \n" /* r11 = r7. */
-        "    subs r2, #32                                 \n"
-        "    ldmia r2!, {r4-r7}                           \n" /* Restore r4-r7. */
-        "    subs r2, #16                                 \n"
-        "                                                 \n"
-        " restore_context_done_first_task:                \n"
-        "    str r2, [r1]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
-        "    bx lr                                        \n"
-        "                                                 \n"
-        " .align 4                                        \n"
-        " pxCurrentTCBConst2: .word pxCurrentTCB          \n"
-        " xSecureContextConst2: .word xSecureContext      \n"
-        " xMPUCTRLConst2: .word 0xe000ed94                \n"
-        " xMAIR0Const2: .word 0xe000edc0                  \n"
-        " xRNRConst2: .word 0xe000ed98                    \n"
-        " xRBARConst2: .word 0xe000ed9c                   \n"
-    );
-}
+    void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                 \n"
+            "                                                 \n"
+            " program_mpu_first_task:                         \n"
+            "    ldr r3, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB.*/
+            "                                                 \n"
+            "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
+            "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
+            "    movs r3, #1                                  \n" /* r3 = 1. */
+            "    bics r2, r3                                  \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
+            "    str r2, [r1]                                 \n" /* Disable MPU. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
+            "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
+            "    ldr r2, xMAIR0Const2                         \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    str r1, [r2]                                 \n" /* Program MAIR0. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
+            "    ldr r1, xRNRConst2                           \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "                                                 \n"
+            "    movs r3, #4                                  \n" /* r3 = 4. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 4. */
+            "    ldmia r0!, {r4-r5}                           \n" /* Read first set of RBAR/RLAR registers from TCB. */
+            "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    stmia r2!, {r4-r5}                           \n" /* Write first set of RBAR/RLAR registers. */
+            "    movs r3, #5                                  \n" /* r3 = 5. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 5. */
+            "    ldmia r0!, {r4-r5}                           \n" /* Read second set of RBAR/RLAR registers from TCB. */
+            "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    stmia r2!, {r4-r5}                           \n" /* Write second set of RBAR/RLAR registers. */
+            "    movs r3, #6                                  \n" /* r3 = 6. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 6. */
+            "    ldmia r0!, {r4-r5}                           \n" /* Read third set of RBAR/RLAR registers from TCB. */
+            "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    stmia r2!, {r4-r5}                           \n" /* Write third set of RBAR/RLAR registers. */
+            "    movs r3, #7                                  \n" /* r3 = 6. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 7. */
+            "    ldmia r0!, {r4-r5}                           \n" /* Read fourth set of RBAR/RLAR registers from TCB. */
+            "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    stmia r2!, {r4-r5}                           \n" /* Write fourth set of RBAR/RLAR registers. */
+            "                                                 \n"
+            "   ldr r1, xMPUCTRLConst2                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
+            "   movs r3, #1                                   \n" /* r3 = 1. */
+            "   orrs r2, r3                                   \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
+            "   str r2, [r1]                                  \n" /* Enable MPU. */
+            "   dsb                                           \n" /* Force memory writes before continuing. */
+            "                                                 \n"
+            " restore_context_first_task:                     \n"
+            "    ldr r3, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r1, [r3]                                 \n" /* r1 = pxCurrentTCB.*/
+            "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
+            "                                                 \n"
+            " restore_special_regs_first_task:                \n"
+            "    subs r2, #20                                 \n"
+            "    ldmia r2!, {r0, r3-r6}                       \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, r6 = LR. */
+            "    subs r2, #20                                 \n"
+            "    msr psp, r3                                  \n"
+            "    msr psplim, r4                               \n"
+            "    msr control, r5                              \n"
+            "    mov lr, r6                                   \n"
+            "    ldr r4, xSecureContextConst2                 \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "    str r0, [r4]                                 \n" /* Restore xSecureContext. */
+            "                                                 \n"
+            " restore_general_regs_first_task:                \n"
+            "    subs r2, #32                                 \n"
+            "    ldmia r2!, {r4-r7}                           \n" /* r4-r7 contain half of the hardware saved context. */
+            "    stmia r3!, {r4-r7}                           \n" /* Copy half of the the hardware saved context on the task stack. */
+            "    ldmia r2!, {r4-r7}                           \n" /* r4-r7 contain rest half of the hardware saved context. */
+            "    stmia r3!, {r4-r7}                           \n" /* Copy rest half of the the hardware saved context on the task stack. */
+            "    subs r2, #48                                 \n"
+            "    ldmia r2!, {r4-r7}                           \n" /* Restore r8-r11. */
+            "    mov r8, r4                                   \n" /* r8 = r4. */
+            "    mov r9, r5                                   \n" /* r9 = r5. */
+            "    mov r10, r6                                  \n" /* r10 = r6. */
+            "    mov r11, r7                                  \n" /* r11 = r7. */
+            "    subs r2, #32                                 \n"
+            "    ldmia r2!, {r4-r7}                           \n" /* Restore r4-r7. */
+            "    subs r2, #16                                 \n"
+            "                                                 \n"
+            " restore_context_done_first_task:                \n"
+            "    str r2, [r1]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
+            "    bx lr                                        \n"
+            "                                                 \n"
+            " .align 4                                        \n"
+            " pxCurrentTCBConst2: .word pxCurrentTCB          \n"
+            " xSecureContextConst2: .word xSecureContext      \n"
+            " xMPUCTRLConst2: .word 0xe000ed94                \n"
+            " xMAIR0Const2: .word 0xe000edc0                  \n"
+            " xRNRConst2: .word 0xe000ed98                    \n"
+            " xRBARConst2: .word 0xe000ed9c                   \n"
+        );
+    }
 
 #else /* configENABLE_MPU */
 
-void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "   .syntax unified                                 \n"
-        "                                                   \n"
-        "   ldr  r2, pxCurrentTCBConst2                     \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr  r3, [r2]                                   \n"/* Read pxCurrentTCB. */
-        "   ldr  r0, [r3]                                   \n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
-        "                                                   \n"
-        "   ldm  r0!, {r1-r3}                               \n"/* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
-        "   ldr  r4, xSecureContextConst2                   \n"
-        "   str  r1, [r4]                                   \n"/* Set xSecureContext to this task's value for the same. */
-        "   msr  psplim, r2                                 \n"/* Set this task's PSPLIM value. */
-        "   movs r1, #2                                     \n"/* r1 = 2. */
-        "   msr  CONTROL, r1                                \n"/* Switch to use PSP in the thread mode. */
-        "   adds r0, #32                                    \n"/* Discard everything up to r0. */
-        "   msr  psp, r0                                    \n"/* This is now the new top of stack to use in the task. */
-        "   isb                                             \n"
-        "   bx   r3                                         \n"/* Finally, branch to EXC_RETURN. */
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "pxCurrentTCBConst2: .word pxCurrentTCB             \n"
-        "xSecureContextConst2: .word xSecureContext         \n"
-    );
-}
+    void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            "   .syntax unified                                 \n"
+            "                                                   \n"
+            "   ldr  r2, pxCurrentTCBConst2                     \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr  r3, [r2]                                   \n" /* Read pxCurrentTCB. */
+            "   ldr  r0, [r3]                                   \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+            "                                                   \n"
+            "   ldm  r0!, {r1-r3}                               \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
+            "   ldr  r4, xSecureContextConst2                   \n"
+            "   str  r1, [r4]                                   \n" /* Set xSecureContext to this task's value for the same. */
+            "   msr  psplim, r2                                 \n" /* Set this task's PSPLIM value. */
+            "   movs r1, #2                                     \n" /* r1 = 2. */
+            "   msr  CONTROL, r1                                \n" /* Switch to use PSP in the thread mode. */
+            "   adds r0, #32                                    \n" /* Discard everything up to r0. */
+            "   msr  psp, r0                                    \n" /* This is now the new top of stack to use in the task. */
+            "   isb                                             \n"
+            "   bx   r3                                         \n" /* Finally, branch to EXC_RETURN. */
+            "                                                   \n"
+            "   .align 4                                        \n"
+            "pxCurrentTCBConst2: .word pxCurrentTCB             \n"
+            "xSecureContextConst2: .word xSecureContext         \n"
+        );
+    }
 
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
@@ -183,15 +183,15 @@ BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs r0, control                                 \n"/* r0 = CONTROL. */
-        "   movs r1, #1                                     \n"/* r1 = 1. */
-        "   tst r0, r1                                      \n"/* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
-        "   beq running_privileged                          \n"/* If the result of previous AND operation was 0, branch. */
-        "   movs r0, #0                                     \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
-        "   bx lr                                           \n"/* Return. */
+        "   mrs r0, control                                 \n" /* r0 = CONTROL. */
+        "   movs r1, #1                                     \n" /* r1 = 1. */
+        "   tst r0, r1                                      \n" /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
+        "   beq running_privileged                          \n" /* If the result of previous AND operation was 0, branch. */
+        "   movs r0, #0                                     \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+        "   bx lr                                           \n" /* Return. */
         " running_privileged:                               \n"
-        "   movs r0, #1                                     \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
-        "   bx lr                                           \n"/* Return. */
+        "   movs r0, #1                                     \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+        "   bx lr                                           \n" /* Return. */
         "                                                   \n"
         "   .align 4                                        \n"
         ::: "r0", "r1", "memory"
@@ -205,11 +205,11 @@ void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs r0, control                                 \n"/* Read the CONTROL register. */
-        "   movs r1, #1                                     \n"/* r1 = 1. */
-        "   bics r0, r1                                     \n"/* Clear the bit 0. */
-        "   msr control, r0                                 \n"/* Write back the new CONTROL value. */
-        "   bx lr                                           \n"/* Return to the caller. */
+        "   mrs r0, control                                 \n" /* Read the CONTROL register. */
+        "   movs r1, #1                                     \n" /* r1 = 1. */
+        "   bics r0, r1                                     \n" /* Clear the bit 0. */
+        "   msr control, r0                                 \n" /* Write back the new CONTROL value. */
+        "   bx lr                                           \n" /* Return to the caller. */
         ::: "r0", "r1", "memory"
     );
 }
@@ -221,11 +221,11 @@ void vResetPrivilege( void ) /* __attribute__ (( naked )) */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs r0, control                                 \n"/* r0 = CONTROL. */
-        "   movs r1, #1                                     \n"/* r1 = 1. */
-        "   orrs r0, r1                                     \n"/* r0 = r0 | r1. */
-        "   msr control, r0                                 \n"/* CONTROL = r0. */
-        "   bx lr                                           \n"/* Return to the caller. */
+        "   mrs r0, control                                 \n" /* r0 = CONTROL. */
+        "   movs r1, #1                                     \n" /* r1 = 1. */
+        "   orrs r0, r1                                     \n" /* r0 = r0 | r1. */
+        "   msr control, r0                                 \n" /* CONTROL = r0. */
+        "   bx lr                                           \n" /* Return to the caller. */
         ::: "r0", "r1", "memory"
     );
 }
@@ -237,14 +237,14 @@ void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   ldr r0, xVTORConst                              \n"/* Use the NVIC offset register to locate the stack. */
-        "   ldr r0, [r0]                                    \n"/* Read the VTOR register which gives the address of vector table. */
-        "   ldr r0, [r0]                                    \n"/* The first entry in vector table is stack pointer. */
-        "   msr msp, r0                                     \n"/* Set the MSP back to the start of the stack. */
-        "   cpsie i                                         \n"/* Globally enable interrupts. */
+        "   ldr r0, xVTORConst                              \n" /* Use the NVIC offset register to locate the stack. */
+        "   ldr r0, [r0]                                    \n" /* Read the VTOR register which gives the address of vector table. */
+        "   ldr r0, [r0]                                    \n" /* The first entry in vector table is stack pointer. */
+        "   msr msp, r0                                     \n" /* Set the MSP back to the start of the stack. */
+        "   cpsie i                                         \n" /* Globally enable interrupts. */
         "   dsb                                             \n"
         "   isb                                             \n"
-        "   svc %0                                          \n"/* System call to start the first task. */
+        "   svc %0                                          \n" /* System call to start the first task. */
         "   nop                                             \n"
         "                                                   \n"
         "   .align 4                                        \n"
@@ -283,328 +283,328 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
 
 #if ( configENABLE_MPU == 1 )
 
-void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        " .syntax unified                                 \n"
-        " .extern SecureContext_SaveContext               \n"
-        " .extern SecureContext_LoadContext               \n"
-        "                                                 \n"
-        " ldr r3, xSecureContextConst                     \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-        " ldr r0, [r3]                                    \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
-        " ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        " ldr r1, [r3]                                    \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later.*/
-        " ldr r2, [r1]                                    \n" /* r2 = Location in TCB where the context should be saved. */
-        "                                                 \n"
-        " cbz r0, save_ns_context                         \n" /* No secure context to save. */
-        " save_s_context:                                 \n"
-        "    push {r0-r2, lr}                             \n"
-        "    bl SecureContext_SaveContext                 \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-        "    pop {r0-r3}                                  \n" /* LR is now in r3. */
-        "    mov lr, r3                                   \n" /* Restore LR. */
-        "                                                 \n"
-        " save_ns_context:                                \n"
-        "    mov r3, lr                                   \n" /* r3 = LR (EXC_RETURN). */
-        "    lsls r3, r3, #25                             \n" /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-        "    bmi save_special_regs                        \n" /* r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
-        "                                                 \n"
-        " save_general_regs:                              \n"
-        "    mrs r3, psp                                  \n"
-        "    stmia r2!, {r4-r7}                           \n" /* Store r4-r7. */
-        "    mov r4, r8                                   \n" /* r4 = r8. */
-        "    mov r5, r9                                   \n" /* r5 = r9. */
-        "    mov r6, r10                                  \n" /* r6 = r10. */
-        "    mov r7, r11                                  \n" /* r7 = r11. */
-        "    stmia r2!, {r4-r7}                           \n" /* Store r8-r11. */
-        "    ldmia r3!, {r4-r7}                           \n" /* Copy half of the  hardware saved context into r4-r7. */
-        "    stmia r2!, {r4-r7}                           \n" /* Store the hardware saved context. */
-        "    ldmia r3!, {r4-r7}                           \n" /* Copy rest half of the  hardware saved context into r4-r7. */
-        "    stmia r2!, {r4-r7}                           \n" /* Store the hardware saved context. */
-        "                                                 \n"
-        " save_special_regs:                              \n"
-        "    mrs r3, psp                                  \n" /* r3 = PSP. */
-        "    mrs r4, psplim                               \n" /* r4 = PSPLIM. */
-        "    mrs r5, control                              \n" /* r5 = CONTROL. */
-        "    mov r6, lr                                   \n" /* r6 = LR. */
-        "    stmia r2!, {r0, r3-r6}                       \n" /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
-        "    str r2, [r1]                                 \n" /* Save the location from where the context should be restored as the first member of TCB. */
-        "                                                 \n"
-        " select_next_task:                               \n"
-        "    cpsid i                                      \n"
-        "    bl vTaskSwitchContext                        \n"
-        "    cpsie i                                      \n"
-        "                                                 \n"
-        " program_mpu:                                    \n"
-        "    ldr r3, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB.*/
-        "                                                 \n"
-        "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-        "    ldr r1, xMPUCTRLConst                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
-        "    movs r3, #1                                  \n" /* r3 = 1. */
-        "    bics r2, r3                                  \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
-        "    str r2, [r1]                                 \n" /* Disable MPU. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
-        "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-        "    ldr r2, xMAIR0Const                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-        "    str r1, [r2]                                 \n" /* Program MAIR0. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-        "    ldr r1, xRNRConst                            \n" /* r1 = 0xe000ed98 [Location of RNR]. */
-        "                                                 \n"
-        "    movs r3, #4                                  \n" /* r3 = 4. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 4. */
-        "    ldmia r0!, {r4-r5}                           \n" /* Read first set of RBAR/RLAR registers from TCB. */
-        "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "    stmia r2!, {r4-r5}                           \n" /* Write first set of RBAR/RLAR registers. */
-        "    movs r3, #5                                  \n" /* r3 = 5. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 5. */
-        "    ldmia r0!, {r4-r5}                           \n" /* Read second set of RBAR/RLAR registers from TCB. */
-        "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "    stmia r2!, {r4-r5}                           \n" /* Write second set of RBAR/RLAR registers. */
-        "    movs r3, #6                                  \n" /* r3 = 6. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 6. */
-        "    ldmia r0!, {r4-r5}                           \n" /* Read third set of RBAR/RLAR registers from TCB. */
-        "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "    stmia r2!, {r4-r5}                           \n" /* Write third set of RBAR/RLAR registers. */
-        "    movs r3, #7                                  \n" /* r3 = 6. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 7. */
-        "    ldmia r0!, {r4-r5}                           \n" /* Read fourth set of RBAR/RLAR registers from TCB. */
-        "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "    stmia r2!, {r4-r5}                           \n" /* Write fourth set of RBAR/RLAR registers. */
-        "                                                 \n"
-        "    ldr r1, xMPUCTRLConst                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
-        "    movs r3, #1                                  \n" /* r3 = 1. */
-        "    orrs r2, r3                                  \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
-        "    str r2, [r1]                                 \n" /* Enable MPU. */
-        "    dsb                                          \n" /* Force memory writes before continuing. */
-        "                                                 \n"
-        " restore_context:                                \n"
-        "    ldr r3, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r1, [r3]                                 \n" /* r1 = pxCurrentTCB.*/
-        "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
-        "                                                 \n"
-        " restore_special_regs:                           \n"
-        "    subs r2, #20                                 \n"
-        "    ldmia r2!, {r0, r3-r6}                       \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, r6 = LR. */
-        "    subs r2, #20                                 \n"
-        "    msr psp, r3                                  \n"
-        "    msr psplim, r4                               \n"
-        "    msr control, r5                              \n"
-        "    mov lr, r6                                   \n"
-        "    ldr r4, xSecureContextConst                  \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-        "    str r0, [r4]                                 \n" /* Restore xSecureContext. */
-        "    cbz r0, restore_ns_context                   \n" /* No secure context to restore. */
-        "                                                 \n"
-        " restore_s_context:                              \n"
-        "    push {r1-r3, lr}                             \n"
-        "    bl SecureContext_LoadContext                 \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-        "    pop {r1-r4}                                  \n" /* LR is now in r4. */
-        "    mov lr, r4                                   \n"
-        "                                                 \n"
-        " restore_ns_context:                             \n"
-        "    mov r0, lr                                   \n" /* r0 = LR (EXC_RETURN). */
-        "    lsls r0, r0, #25                             \n" /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-        "    bmi restore_context_done                     \n" /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
-        "                                                 \n"
-        " restore_general_regs:                           \n"
-        "    subs r2, #32                                 \n"
-        "    ldmia r2!, {r4-r7}                           \n" /* r4-r7 contain half of the hardware saved context. */
-        "    stmia r3!, {r4-r7}                           \n" /* Copy half of the the hardware saved context on the task stack. */
-        "    ldmia r2!, {r4-r7}                           \n" /* r4-r7 contain rest half of the hardware saved context. */
-        "    stmia r3!, {r4-r7}                           \n" /* Copy rest half of the the hardware saved context on the task stack. */
-        "    subs r2, #48                                 \n"
-        "    ldmia r2!, {r4-r7}                           \n" /* Restore r8-r11. */
-        "    mov r8, r4                                   \n" /* r8 = r4. */
-        "    mov r9, r5                                   \n" /* r9 = r5. */
-        "    mov r10, r6                                  \n" /* r10 = r6. */
-        "    mov r11, r7                                  \n" /* r11 = r7. */
-        "    subs r2, #32                                 \n"
-        "    ldmia r2!, {r4-r7}                           \n" /* Restore r4-r7. */
-        "    subs r2, #16                                 \n"
-        "                                                 \n"
-        " restore_context_done:                           \n"
-        "    str r2, [r1]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
-        "    bx lr                                        \n"
-        "                                                 \n"
-        " .align 4                                        \n"
-        " pxCurrentTCBConst: .word pxCurrentTCB           \n"
-        " xSecureContextConst: .word xSecureContext       \n"
-        " xMPUCTRLConst: .word 0xe000ed94                 \n"
-        " xMAIR0Const: .word 0xe000edc0                   \n"
-        " xRNRConst: .word 0xe000ed98                     \n"
-        " xRBARConst: .word 0xe000ed9c                    \n"
-    );
-}
+    void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                 \n"
+            " .extern SecureContext_SaveContext               \n"
+            " .extern SecureContext_LoadContext               \n"
+            "                                                 \n"
+            " ldr r3, xSecureContextConst                     \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            " ldr r0, [r3]                                    \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+            " ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            " ldr r1, [r3]                                    \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later.*/
+            " ldr r2, [r1]                                    \n" /* r2 = Location in TCB where the context should be saved. */
+            "                                                 \n"
+            " cbz r0, save_ns_context                         \n" /* No secure context to save. */
+            " save_s_context:                                 \n"
+            "    push {r0-r2, lr}                             \n"
+            "    bl SecureContext_SaveContext                 \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+            "    pop {r0-r3}                                  \n" /* LR is now in r3. */
+            "    mov lr, r3                                   \n" /* Restore LR. */
+            "                                                 \n"
+            " save_ns_context:                                \n"
+            "    mov r3, lr                                   \n" /* r3 = LR (EXC_RETURN). */
+            "    lsls r3, r3, #25                             \n" /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+            "    bmi save_special_regs                        \n" /* r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
+            "                                                 \n"
+            " save_general_regs:                              \n"
+            "    mrs r3, psp                                  \n"
+            "    stmia r2!, {r4-r7}                           \n" /* Store r4-r7. */
+            "    mov r4, r8                                   \n" /* r4 = r8. */
+            "    mov r5, r9                                   \n" /* r5 = r9. */
+            "    mov r6, r10                                  \n" /* r6 = r10. */
+            "    mov r7, r11                                  \n" /* r7 = r11. */
+            "    stmia r2!, {r4-r7}                           \n" /* Store r8-r11. */
+            "    ldmia r3!, {r4-r7}                           \n" /* Copy half of the  hardware saved context into r4-r7. */
+            "    stmia r2!, {r4-r7}                           \n" /* Store the hardware saved context. */
+            "    ldmia r3!, {r4-r7}                           \n" /* Copy rest half of the  hardware saved context into r4-r7. */
+            "    stmia r2!, {r4-r7}                           \n" /* Store the hardware saved context. */
+            "                                                 \n"
+            " save_special_regs:                              \n"
+            "    mrs r3, psp                                  \n" /* r3 = PSP. */
+            "    mrs r4, psplim                               \n" /* r4 = PSPLIM. */
+            "    mrs r5, control                              \n" /* r5 = CONTROL. */
+            "    mov r6, lr                                   \n" /* r6 = LR. */
+            "    stmia r2!, {r0, r3-r6}                       \n" /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
+            "    str r2, [r1]                                 \n" /* Save the location from where the context should be restored as the first member of TCB. */
+            "                                                 \n"
+            " select_next_task:                               \n"
+            "    cpsid i                                      \n"
+            "    bl vTaskSwitchContext                        \n"
+            "    cpsie i                                      \n"
+            "                                                 \n"
+            " program_mpu:                                    \n"
+            "    ldr r3, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB.*/
+            "                                                 \n"
+            "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
+            "    ldr r1, xMPUCTRLConst                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
+            "    movs r3, #1                                  \n" /* r3 = 1. */
+            "    bics r2, r3                                  \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
+            "    str r2, [r1]                                 \n" /* Disable MPU. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
+            "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
+            "    ldr r2, xMAIR0Const                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    str r1, [r2]                                 \n" /* Program MAIR0. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
+            "    ldr r1, xRNRConst                            \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "                                                 \n"
+            "    movs r3, #4                                  \n" /* r3 = 4. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 4. */
+            "    ldmia r0!, {r4-r5}                           \n" /* Read first set of RBAR/RLAR registers from TCB. */
+            "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    stmia r2!, {r4-r5}                           \n" /* Write first set of RBAR/RLAR registers. */
+            "    movs r3, #5                                  \n" /* r3 = 5. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 5. */
+            "    ldmia r0!, {r4-r5}                           \n" /* Read second set of RBAR/RLAR registers from TCB. */
+            "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    stmia r2!, {r4-r5}                           \n" /* Write second set of RBAR/RLAR registers. */
+            "    movs r3, #6                                  \n" /* r3 = 6. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 6. */
+            "    ldmia r0!, {r4-r5}                           \n" /* Read third set of RBAR/RLAR registers from TCB. */
+            "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    stmia r2!, {r4-r5}                           \n" /* Write third set of RBAR/RLAR registers. */
+            "    movs r3, #7                                  \n" /* r3 = 6. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 7. */
+            "    ldmia r0!, {r4-r5}                           \n" /* Read fourth set of RBAR/RLAR registers from TCB. */
+            "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    stmia r2!, {r4-r5}                           \n" /* Write fourth set of RBAR/RLAR registers. */
+            "                                                 \n"
+            "    ldr r1, xMPUCTRLConst                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
+            "    movs r3, #1                                  \n" /* r3 = 1. */
+            "    orrs r2, r3                                  \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
+            "    str r2, [r1]                                 \n" /* Enable MPU. */
+            "    dsb                                          \n" /* Force memory writes before continuing. */
+            "                                                 \n"
+            " restore_context:                                \n"
+            "    ldr r3, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r1, [r3]                                 \n" /* r1 = pxCurrentTCB.*/
+            "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
+            "                                                 \n"
+            " restore_special_regs:                           \n"
+            "    subs r2, #20                                 \n"
+            "    ldmia r2!, {r0, r3-r6}                       \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, r6 = LR. */
+            "    subs r2, #20                                 \n"
+            "    msr psp, r3                                  \n"
+            "    msr psplim, r4                               \n"
+            "    msr control, r5                              \n"
+            "    mov lr, r6                                   \n"
+            "    ldr r4, xSecureContextConst                  \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "    str r0, [r4]                                 \n" /* Restore xSecureContext. */
+            "    cbz r0, restore_ns_context                   \n" /* No secure context to restore. */
+            "                                                 \n"
+            " restore_s_context:                              \n"
+            "    push {r1-r3, lr}                             \n"
+            "    bl SecureContext_LoadContext                 \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+            "    pop {r1-r4}                                  \n" /* LR is now in r4. */
+            "    mov lr, r4                                   \n"
+            "                                                 \n"
+            " restore_ns_context:                             \n"
+            "    mov r0, lr                                   \n" /* r0 = LR (EXC_RETURN). */
+            "    lsls r0, r0, #25                             \n" /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+            "    bmi restore_context_done                     \n" /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
+            "                                                 \n"
+            " restore_general_regs:                           \n"
+            "    subs r2, #32                                 \n"
+            "    ldmia r2!, {r4-r7}                           \n" /* r4-r7 contain half of the hardware saved context. */
+            "    stmia r3!, {r4-r7}                           \n" /* Copy half of the the hardware saved context on the task stack. */
+            "    ldmia r2!, {r4-r7}                           \n" /* r4-r7 contain rest half of the hardware saved context. */
+            "    stmia r3!, {r4-r7}                           \n" /* Copy rest half of the the hardware saved context on the task stack. */
+            "    subs r2, #48                                 \n"
+            "    ldmia r2!, {r4-r7}                           \n" /* Restore r8-r11. */
+            "    mov r8, r4                                   \n" /* r8 = r4. */
+            "    mov r9, r5                                   \n" /* r9 = r5. */
+            "    mov r10, r6                                  \n" /* r10 = r6. */
+            "    mov r11, r7                                  \n" /* r11 = r7. */
+            "    subs r2, #32                                 \n"
+            "    ldmia r2!, {r4-r7}                           \n" /* Restore r4-r7. */
+            "    subs r2, #16                                 \n"
+            "                                                 \n"
+            " restore_context_done:                           \n"
+            "    str r2, [r1]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
+            "    bx lr                                        \n"
+            "                                                 \n"
+            " .align 4                                        \n"
+            " pxCurrentTCBConst: .word pxCurrentTCB           \n"
+            " xSecureContextConst: .word xSecureContext       \n"
+            " xMPUCTRLConst: .word 0xe000ed94                 \n"
+            " xMAIR0Const: .word 0xe000edc0                   \n"
+            " xRNRConst: .word 0xe000ed98                     \n"
+            " xRBARConst: .word 0xe000ed9c                    \n"
+        );
+    }
 
 #else /* configENABLE_MPU */
 
-void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "   .syntax unified                                 \n"
-        "   .extern SecureContext_SaveContext               \n"
-        "   .extern SecureContext_LoadContext               \n"
-        "                                                   \n"
-        "   ldr r3, xSecureContextConst                     \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
-        "   ldr r0, [r3]                                    \n"/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
-        "   ldr r3, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r3]                                    \n"/* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later.*/
-        "   mrs r2, psp                                     \n"/* Read PSP in r2. */
-        "                                                   \n"
-        "   cbz r0, save_ns_context                         \n"/* No secure context to save. */
-        "   push {r0-r2, r14}                               \n"
-        "   bl SecureContext_SaveContext                    \n"/* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-        "   pop {r0-r3}                                     \n"/* LR is now in r3. */
-        "   mov lr, r3                                      \n"/* LR = r3. */
-        "   lsls r1, r3, #25                                \n"/* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-        "   bpl save_ns_context                             \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-        "   ldr r3, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r3]                                    \n"/* Read pxCurrentTCB. */
-        "   subs r2, r2, #12                                \n"/* Make space for xSecureContext, PSPLIM and LR on the stack. */
-        "   str r2, [r1]                                    \n"/* Save the new top of stack in TCB. */
-        "   mrs r1, psplim                                  \n"/* r1 = PSPLIM. */
-        "   mov r3, lr                                      \n"/* r3 = LR/EXC_RETURN. */
-        "   stmia r2!, {r0, r1, r3}                         \n"/* Store xSecureContext, PSPLIM and LR on the stack. */
-        "   b select_next_task                              \n"
-        "                                                   \n"
-        " save_ns_context:                                  \n"
-        "   ldr r3, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r3]                                    \n"/* Read pxCurrentTCB. */
-        "   subs r2, r2, #44                                \n"/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
-        "   str r2, [r1]                                    \n"/* Save the new top of stack in TCB. */
-        "   mrs r1, psplim                                  \n"/* r1 = PSPLIM. */
-        "   mov r3, lr                                      \n"/* r3 = LR/EXC_RETURN. */
-        "   stmia r2!, {r0, r1, r3-r7}                      \n"/* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */
-        "   mov r4, r8                                      \n"/* r4 = r8. */
-        "   mov r5, r9                                      \n"/* r5 = r9. */
-        "   mov r6, r10                                     \n"/* r6 = r10. */
-        "   mov r7, r11                                     \n"/* r7 = r11. */
-        "   stmia r2!, {r4-r7}                              \n"/* Store the high registers that are not saved automatically. */
-        "                                                   \n"
-        " select_next_task:                                 \n"
-        "   cpsid i                                         \n"
-        "   bl vTaskSwitchContext                           \n"
-        "   cpsie i                                         \n"
-        "                                                   \n"
-        "   ldr r3, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r3]                                    \n"/* Read pxCurrentTCB. */
-        "   ldr r2, [r1]                                    \n"/* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
-        "                                                   \n"
-        "   ldmia r2!, {r0, r1, r4}                         \n"/* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
-        "   msr psplim, r1                                  \n"/* Restore the PSPLIM register value for the task. */
-        "   mov lr, r4                                      \n"/* LR = r4. */
-        "   ldr r3, xSecureContextConst                     \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
-        "   str r0, [r3]                                    \n"/* Restore the task's xSecureContext. */
-        "   cbz r0, restore_ns_context                      \n"/* If there is no secure context for the task, restore the non-secure context. */
-        "   ldr r3, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r3]                                    \n"/* Read pxCurrentTCB. */
-        "   push {r2, r4}                                   \n"
-        "   bl SecureContext_LoadContext                    \n"/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-        "   pop {r2, r4}                                    \n"
-        "   mov lr, r4                                      \n"/* LR = r4. */
-        "   lsls r1, r4, #25                                \n"/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-        "   bpl restore_ns_context                          \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-        "   msr psp, r2                                     \n"/* Remember the new top of stack for the task. */
-        "   bx lr                                           \n"
-        "                                                   \n"
-        " restore_ns_context:                               \n"
-        "   adds r2, r2, #16                                \n"/* Move to the high registers. */
-        "   ldmia r2!, {r4-r7}                              \n"/* Restore the high registers that are not automatically restored. */
-        "   mov r8, r4                                      \n"/* r8 = r4. */
-        "   mov r9, r5                                      \n"/* r9 = r5. */
-        "   mov r10, r6                                     \n"/* r10 = r6. */
-        "   mov r11, r7                                     \n"/* r11 = r7. */
-        "   msr psp, r2                                     \n"/* Remember the new top of stack for the task. */
-        "   subs r2, r2, #32                                \n"/* Go back to the low registers. */
-        "   ldmia r2!, {r4-r7}                              \n"/* Restore the low registers that are not automatically restored. */
-        "   bx lr                                           \n"
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "pxCurrentTCBConst: .word pxCurrentTCB              \n"
-        "xSecureContextConst: .word xSecureContext          \n"
-    );
-}
+    void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            "   .syntax unified                                 \n"
+            "   .extern SecureContext_SaveContext               \n"
+            "   .extern SecureContext_LoadContext               \n"
+            "                                                   \n"
+            "   ldr r3, xSecureContextConst                     \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "   ldr r0, [r3]                                    \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later.*/
+            "   mrs r2, psp                                     \n" /* Read PSP in r2. */
+            "                                                   \n"
+            "   cbz r0, save_ns_context                         \n" /* No secure context to save. */
+            "   push {r0-r2, r14}                               \n"
+            "   bl SecureContext_SaveContext                    \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+            "   pop {r0-r3}                                     \n" /* LR is now in r3. */
+            "   mov lr, r3                                      \n" /* LR = r3. */
+            "   lsls r1, r3, #25                                \n" /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+            "   bpl save_ns_context                             \n" /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
+            "   subs r2, r2, #12                                \n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */
+            "   str r2, [r1]                                    \n" /* Save the new top of stack in TCB. */
+            "   mrs r1, psplim                                  \n" /* r1 = PSPLIM. */
+            "   mov r3, lr                                      \n" /* r3 = LR/EXC_RETURN. */
+            "   stmia r2!, {r0, r1, r3}                         \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
+            "   b select_next_task                              \n"
+            "                                                   \n"
+            " save_ns_context:                                  \n"
+            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
+            "   subs r2, r2, #44                                \n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
+            "   str r2, [r1]                                    \n" /* Save the new top of stack in TCB. */
+            "   mrs r1, psplim                                  \n" /* r1 = PSPLIM. */
+            "   mov r3, lr                                      \n" /* r3 = LR/EXC_RETURN. */
+            "   stmia r2!, {r0, r1, r3-r7}                      \n" /* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */
+            "   mov r4, r8                                      \n" /* r4 = r8. */
+            "   mov r5, r9                                      \n" /* r5 = r9. */
+            "   mov r6, r10                                     \n" /* r6 = r10. */
+            "   mov r7, r11                                     \n" /* r7 = r11. */
+            "   stmia r2!, {r4-r7}                              \n" /* Store the high registers that are not saved automatically. */
+            "                                                   \n"
+            " select_next_task:                                 \n"
+            "   cpsid i                                         \n"
+            "   bl vTaskSwitchContext                           \n"
+            "   cpsie i                                         \n"
+            "                                                   \n"
+            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
+            "   ldr r2, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
+            "                                                   \n"
+            "   ldmia r2!, {r0, r1, r4}                         \n" /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
+            "   msr psplim, r1                                  \n" /* Restore the PSPLIM register value for the task. */
+            "   mov lr, r4                                      \n" /* LR = r4. */
+            "   ldr r3, xSecureContextConst                     \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "   str r0, [r3]                                    \n" /* Restore the task's xSecureContext. */
+            "   cbz r0, restore_ns_context                      \n" /* If there is no secure context for the task, restore the non-secure context. */
+            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
+            "   push {r2, r4}                                   \n"
+            "   bl SecureContext_LoadContext                    \n" /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+            "   pop {r2, r4}                                    \n"
+            "   mov lr, r4                                      \n" /* LR = r4. */
+            "   lsls r1, r4, #25                                \n" /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+            "   bpl restore_ns_context                          \n" /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+            "   msr psp, r2                                     \n" /* Remember the new top of stack for the task. */
+            "   bx lr                                           \n"
+            "                                                   \n"
+            " restore_ns_context:                               \n"
+            "   adds r2, r2, #16                                \n" /* Move to the high registers. */
+            "   ldmia r2!, {r4-r7}                              \n" /* Restore the high registers that are not automatically restored. */
+            "   mov r8, r4                                      \n" /* r8 = r4. */
+            "   mov r9, r5                                      \n" /* r9 = r5. */
+            "   mov r10, r6                                     \n" /* r10 = r6. */
+            "   mov r11, r7                                     \n" /* r11 = r7. */
+            "   msr psp, r2                                     \n" /* Remember the new top of stack for the task. */
+            "   subs r2, r2, #32                                \n" /* Go back to the low registers. */
+            "   ldmia r2!, {r4-r7}                              \n" /* Restore the low registers that are not automatically restored. */
+            "   bx lr                                           \n"
+            "                                                   \n"
+            "   .align 4                                        \n"
+            "pxCurrentTCBConst: .word pxCurrentTCB              \n"
+            "xSecureContextConst: .word xSecureContext          \n"
+        );
+    }
 
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-   __asm volatile
-    (
-        ".syntax unified                \n"
-        ".extern vPortSVCHandler_C      \n"
-        ".extern vSystemCallEnter       \n"
-        ".extern vSystemCallEnter_1     \n"
-        ".extern vSystemCallExit        \n"
-        "                               \n"
-        "movs r0, #4                    \n"
-        "mov r1, lr                     \n"
-        "tst r0, r1                     \n"
-        "beq stack_on_msp               \n"
-        "stack_on_psp:                  \n"
-        "    mrs r0, psp                \n"
-        "    b route_svc                \n"
-        "stack_on_msp:                  \n"
-        "    mrs r0, msp                \n"
-        "    b route_svc                \n"
-        "                               \n"
-        "route_svc:                     \n"
-        "    ldr r2, [r0, #24]          \n"
-        "    subs r2, #2                \n"
-        "    ldrb r3, [r2, #0]          \n"
-        "    cmp r3, %0                 \n"
-        "    beq system_call_enter      \n"
-        "    cmp r3, %1                 \n"
-        "    beq system_call_enter_1    \n"
-        "    cmp r3, %2                 \n"
-        "    beq system_call_exit       \n"
-        "    b vPortSVCHandler_C        \n"
-        "                               \n"
-        "system_call_enter:             \n"
-        "    b vSystemCallEnter         \n"
-        "system_call_enter_1:           \n"
-        "    b vSystemCallEnter_1       \n"
-        "system_call_exit:              \n"
-        "    b vSystemCallExit          \n"
-        "                               \n"
-        : /* No outputs. */
-        :"i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT )
-        : "r0", "r1", "r2", "r3", "memory"
-    );
-}
+    void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            ".syntax unified                \n"
+            ".extern vPortSVCHandler_C      \n"
+            ".extern vSystemCallEnter       \n"
+            ".extern vSystemCallEnter_1     \n"
+            ".extern vSystemCallExit        \n"
+            "                               \n"
+            "movs r0, #4                    \n"
+            "mov r1, lr                     \n"
+            "tst r0, r1                     \n"
+            "beq stack_on_msp               \n"
+            "stack_on_psp:                  \n"
+            "    mrs r0, psp                \n"
+            "    b route_svc                \n"
+            "stack_on_msp:                  \n"
+            "    mrs r0, msp                \n"
+            "    b route_svc                \n"
+            "                               \n"
+            "route_svc:                     \n"
+            "    ldr r2, [r0, #24]          \n"
+            "    subs r2, #2                \n"
+            "    ldrb r3, [r2, #0]          \n"
+            "    cmp r3, %0                 \n"
+            "    beq system_call_enter      \n"
+            "    cmp r3, %1                 \n"
+            "    beq system_call_enter_1    \n"
+            "    cmp r3, %2                 \n"
+            "    beq system_call_exit       \n"
+            "    b vPortSVCHandler_C        \n"
+            "                               \n"
+            "system_call_enter:             \n"
+            "    b vSystemCallEnter         \n"
+            "system_call_enter_1:           \n"
+            "    b vSystemCallEnter_1       \n"
+            "system_call_exit:              \n"
+            "    b vSystemCallExit          \n"
+            "                               \n"
+            : /* No outputs. */
+            : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT )
+            : "r0", "r1", "r2", "r3", "memory"
+        );
+    }
 
 #else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
-void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "   .syntax unified                                 \n"
-        "                                                   \n"
-        "   movs r0, #4                                     \n"
-        "   mov r1, lr                                      \n"
-        "   tst r0, r1                                      \n"
-        "   beq stacking_used_msp                           \n"
-        "   mrs r0, psp                                     \n"
-        "   ldr r2, svchandler_address_const                \n"
-        "   bx r2                                           \n"
-        " stacking_used_msp:                                \n"
-        "   mrs r0, msp                                     \n"
-        "   ldr r2, svchandler_address_const                \n"
-        "   bx r2                                           \n"
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "svchandler_address_const: .word vPortSVCHandler_C  \n"
-    );
-}
+    void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            "   .syntax unified                                 \n"
+            "                                                   \n"
+            "   movs r0, #4                                     \n"
+            "   mov r1, lr                                      \n"
+            "   tst r0, r1                                      \n"
+            "   beq stacking_used_msp                           \n"
+            "   mrs r0, psp                                     \n"
+            "   ldr r2, svchandler_address_const                \n"
+            "   bx r2                                           \n"
+            " stacking_used_msp:                                \n"
+            "   mrs r0, msp                                     \n"
+            "   ldr r2, svchandler_address_const                \n"
+            "   bx r2                                           \n"
+            "                                                   \n"
+            "   .align 4                                        \n"
+            "svchandler_address_const: .word vPortSVCHandler_C  \n"
+        );
+    }
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
@@ -615,8 +615,8 @@ void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   svc %0                                          \n"/* Secure context is allocated in the supervisor call. */
-        "   bx lr                                           \n"/* Return. */
+        "   svc %0                                          \n" /* Secure context is allocated in the supervisor call. */
+        "   bx lr                                           \n" /* Return. */
         ::"i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"
     );
 }
@@ -628,14 +628,14 @@ void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PR
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   ldr r2, [r0]                                    \n"/* The first item in the TCB is the top of the stack. */
-        "   ldr r1, [r2]                                    \n"/* The first item on the stack is the task's xSecureContext. */
-        "   cmp r1, #0                                      \n"/* Raise svc if task's xSecureContext is not NULL. */
-        "   bne free_secure_context                         \n"/* Branch if r1 != 0. */
-        "   bx lr                                           \n"/* There is no secure context (xSecureContext is NULL). */
+        "   ldr r2, [r0]                                    \n" /* The first item in the TCB is the top of the stack. */
+        "   ldr r1, [r2]                                    \n" /* The first item on the stack is the task's xSecureContext. */
+        "   cmp r1, #0                                      \n" /* Raise svc if task's xSecureContext is not NULL. */
+        "   bne free_secure_context                         \n" /* Branch if r1 != 0. */
+        "   bx lr                                           \n" /* There is no secure context (xSecureContext is NULL). */
         " free_secure_context:                              \n"
-        "   svc %0                                          \n"/* Secure context is freed in the supervisor call. */
-        "   bx lr                                           \n"/* Return. */
+        "   svc %0                                          \n" /* Secure context is freed in the supervisor call. */
+        "   bx lr                                           \n" /* Return. */
         ::"i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"
     );
 }
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h
index 233ea5a57..33d522488 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h
@@ -48,9 +48,9 @@
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME                       "Cortex-M23"
-#define portHAS_ARMV8M_MAIN_EXTENSION       0
-#define portDONT_DISCARD                    __attribute__( ( used ) )
+#define portARCH_NAME                    "Cortex-M23"
+#define portHAS_ARMV8M_MAIN_EXTENSION    0
+#define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
 /* ARMv8-M common port configurations. */
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/mpu_wrappers_v2_asm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/mpu_wrappers_v2_asm.c
index f6fb0e778..00c8bcfa8 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/mpu_wrappers_v2_asm.c
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/mpu_wrappers_v2_asm.c
@@ -44,2344 +44,2344 @@
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-#if ( INCLUDE_xTaskDelayUntil == 1 )
+    #if ( INCLUDE_xTaskDelayUntil == 1 )
 
-BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
-                                const TickType_t xTimeIncrement ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
+                                        const TickType_t xTimeIncrement ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
-                                const TickType_t xTimeIncrement ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskDelayUntilImpl                       \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTaskDelayUntil_Unpriv                        \n"
-        " MPU_xTaskDelayUntil_Priv:                             \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTaskDelayUntilImpl                         \n"
-        " MPU_xTaskDelayUntil_Unpriv:                           \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskDelayUntilImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
+                                        const TickType_t xTimeIncrement ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskDelayUntilImpl                       \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xTaskDelayUntil_Unpriv                        \n"
+                " MPU_xTaskDelayUntil_Priv:                             \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xTaskDelayUntilImpl                         \n"
+                " MPU_xTaskDelayUntil_Unpriv:                           \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskDelayUntilImpl                        \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */
+    #endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_xTaskAbortDelay == 1 )
+    #if ( INCLUDE_xTaskAbortDelay == 1 )
 
-BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskAbortDelayImpl                       \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTaskAbortDelay_Unpriv                        \n"
-        " MPU_xTaskAbortDelay_Priv:                             \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTaskAbortDelayImpl                         \n"
-        " MPU_xTaskAbortDelay_Unpriv:                           \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskAbortDelayImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskAbortDelayImpl                       \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xTaskAbortDelay_Unpriv                        \n"
+                " MPU_xTaskAbortDelay_Priv:                             \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xTaskAbortDelayImpl                         \n"
+                " MPU_xTaskAbortDelay_Unpriv:                           \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskAbortDelayImpl                        \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */
+    #endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_vTaskDelay == 1 )
+    #if ( INCLUDE_vTaskDelay == 1 )
 
-void MPU_vTaskDelay( const TickType_t xTicksToDelay ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskDelay( const TickType_t xTicksToDelay ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskDelayImpl                            \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_vTaskDelay_Unpriv                             \n"
-        " MPU_vTaskDelay_Priv:                                  \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_vTaskDelayImpl                              \n"
-        " MPU_vTaskDelay_Unpriv:                                \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskDelayImpl                             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskDelayImpl                            \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_vTaskDelay_Unpriv                             \n"
+                " MPU_vTaskDelay_Priv:                                  \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_vTaskDelayImpl                              \n"
+                " MPU_vTaskDelay_Unpriv:                                \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskDelayImpl                             \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_vTaskDelay == 1 ) */
+    #endif /* if ( INCLUDE_vTaskDelay == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_uxTaskPriorityGet == 1 )
+    #if ( INCLUDE_uxTaskPriorityGet == 1 )
 
-UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskPriorityGetImpl                     \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_uxTaskPriorityGet_Unpriv                      \n"
-        " MPU_uxTaskPriorityGet_Priv:                           \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_uxTaskPriorityGetImpl                       \n"
-        " MPU_uxTaskPriorityGet_Unpriv:                         \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskPriorityGetImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskPriorityGetImpl                     \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_uxTaskPriorityGet_Unpriv                      \n"
+                " MPU_uxTaskPriorityGet_Priv:                           \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_uxTaskPriorityGetImpl                       \n"
+                " MPU_uxTaskPriorityGet_Unpriv:                         \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskPriorityGetImpl                      \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */
+    #endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_eTaskGetState == 1 )
+    #if ( INCLUDE_eTaskGetState == 1 )
 
-eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_eTaskGetStateImpl                         \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_eTaskGetState_Unpriv                          \n"
-        " MPU_eTaskGetState_Priv:                               \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_eTaskGetStateImpl                           \n"
-        " MPU_eTaskGetState_Unpriv:                             \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_eTaskGetStateImpl                          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_eTaskGetStateImpl                         \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_eTaskGetState_Unpriv                          \n"
+                " MPU_eTaskGetState_Priv:                               \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_eTaskGetStateImpl                           \n"
+                " MPU_eTaskGetState_Unpriv:                             \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_eTaskGetStateImpl                          \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_eTaskGetState == 1 ) */
+    #endif /* if ( INCLUDE_eTaskGetState == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-void MPU_vTaskGetInfo( TaskHandle_t xTask,
-                       TaskStatus_t * pxTaskStatus,
-                       BaseType_t xGetFreeStackSpace,
-                       eTaskState eState ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskGetInfo( TaskHandle_t xTask,
+                               TaskStatus_t * pxTaskStatus,
+                               BaseType_t xGetFreeStackSpace,
+                               eTaskState eState ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskGetInfo( TaskHandle_t xTask,
-                       TaskStatus_t * pxTaskStatus,
-                       BaseType_t xGetFreeStackSpace,
-                       eTaskState eState ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskGetInfoImpl                          \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_vTaskGetInfo_Unpriv                           \n"
-        " MPU_vTaskGetInfo_Priv:                                \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_vTaskGetInfoImpl                            \n"
-        " MPU_vTaskGetInfo_Unpriv:                              \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskGetInfoImpl                           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskGetInfo( TaskHandle_t xTask,
+                               TaskStatus_t * pxTaskStatus,
+                               BaseType_t xGetFreeStackSpace,
+                               eTaskState eState ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskGetInfoImpl                          \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_vTaskGetInfo_Unpriv                           \n"
+                " MPU_vTaskGetInfo_Priv:                                \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_vTaskGetInfoImpl                            \n"
+                " MPU_vTaskGetInfo_Unpriv:                              \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskGetInfoImpl                           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
+    #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
+    #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
 
-TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetIdleTaskHandleImpl                \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTaskGetIdleTaskHandle_Unpriv                 \n"
-        " MPU_xTaskGetIdleTaskHandle_Priv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTaskGetIdleTaskHandleImpl                  \n"
-        " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetIdleTaskHandleImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetIdleTaskHandleImpl                \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xTaskGetIdleTaskHandle_Unpriv                 \n"
+                " MPU_xTaskGetIdleTaskHandle_Priv:                      \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xTaskGetIdleTaskHandleImpl                  \n"
+                " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetIdleTaskHandleImpl                 \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */
+    #endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_vTaskSuspend == 1 )
+    #if ( INCLUDE_vTaskSuspend == 1 )
 
-void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSuspendImpl                          \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_vTaskSuspend_Unpriv                           \n"
-        " MPU_vTaskSuspend_Priv:                                \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_vTaskSuspendImpl                            \n"
-        " MPU_vTaskSuspend_Unpriv:                              \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSuspendImpl                           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskSuspendImpl                          \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_vTaskSuspend_Unpriv                           \n"
+                " MPU_vTaskSuspend_Priv:                                \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_vTaskSuspendImpl                            \n"
+                " MPU_vTaskSuspend_Unpriv:                              \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskSuspendImpl                           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
+    #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_vTaskSuspend == 1 )
+    #if ( INCLUDE_vTaskSuspend == 1 )
 
-void MPU_vTaskResume( TaskHandle_t xTaskToResume ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskResume( TaskHandle_t xTaskToResume ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskResumeImpl                           \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_vTaskResume_Unpriv                            \n"
-        " MPU_vTaskResume_Priv:                                 \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_vTaskResumeImpl                             \n"
-        " MPU_vTaskResume_Unpriv:                               \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskResumeImpl                            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskResumeImpl                           \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_vTaskResume_Unpriv                            \n"
+                " MPU_vTaskResume_Priv:                                 \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_vTaskResumeImpl                             \n"
+                " MPU_vTaskResume_Unpriv:                               \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskResumeImpl                            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
+    #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
 /*-----------------------------------------------------------*/
 
-TickType_t MPU_xTaskGetTickCount( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    TickType_t MPU_xTaskGetTickCount( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TickType_t MPU_xTaskGetTickCount( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetTickCountImpl                     \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTaskGetTickCount_Unpriv                      \n"
-        " MPU_xTaskGetTickCount_Priv:                           \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTaskGetTickCountImpl                       \n"
-        " MPU_xTaskGetTickCount_Unpriv:                         \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetTickCountImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    TickType_t MPU_xTaskGetTickCount( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xTaskGetTickCountImpl                     \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xTaskGetTickCount_Unpriv                      \n"
+            " MPU_xTaskGetTickCount_Priv:                           \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xTaskGetTickCountImpl                       \n"
+            " MPU_xTaskGetTickCount_Unpriv:                         \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xTaskGetTickCountImpl                      \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetNumberOfTasksImpl                \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_uxTaskGetNumberOfTasks_Unpriv                 \n"
-        " MPU_uxTaskGetNumberOfTasks_Priv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_uxTaskGetNumberOfTasksImpl                  \n"
-        " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetNumberOfTasksImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_uxTaskGetNumberOfTasksImpl                \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_uxTaskGetNumberOfTasks_Unpriv                 \n"
+            " MPU_uxTaskGetNumberOfTasks_Priv:                      \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_uxTaskGetNumberOfTasksImpl                  \n"
+            " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_uxTaskGetNumberOfTasksImpl                 \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configGENERATE_RUN_TIME_STATS == 1 )
+    #if ( configGENERATE_RUN_TIME_STATS == 1 )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetRunTimeCounterImpl               \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_ulTaskGetRunTimeCounter_Unpriv                \n"
-        " MPU_ulTaskGetRunTimeCounter_Priv:                     \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_ulTaskGetRunTimeCounterImpl                 \n"
-        " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetRunTimeCounterImpl                \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetRunTimeCounterImpl               \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_ulTaskGetRunTimeCounter_Unpriv                \n"
+                " MPU_ulTaskGetRunTimeCounter_Priv:                     \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_ulTaskGetRunTimeCounterImpl                 \n"
+                " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetRunTimeCounterImpl                \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configGENERATE_RUN_TIME_STATS == 1 )
+    #if ( configGENERATE_RUN_TIME_STATS == 1 )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetRunTimePercentImpl               \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_ulTaskGetRunTimePercent_Unpriv                \n"
-        " MPU_ulTaskGetRunTimePercent_Priv:                     \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_ulTaskGetRunTimePercentImpl                 \n"
-        " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetRunTimePercentImpl                \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetRunTimePercentImpl               \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_ulTaskGetRunTimePercent_Unpriv                \n"
+                " MPU_ulTaskGetRunTimePercent_Priv:                     \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_ulTaskGetRunTimePercentImpl                 \n"
+                " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetRunTimePercentImpl                \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+    #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetIdleRunTimePercentImpl           \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv            \n"
-        " MPU_ulTaskGetIdleRunTimePercent_Priv:                 \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_ulTaskGetIdleRunTimePercentImpl             \n"
-        " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetIdleRunTimePercentImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetIdleRunTimePercentImpl           \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv            \n"
+                " MPU_ulTaskGetIdleRunTimePercent_Priv:                 \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_ulTaskGetIdleRunTimePercentImpl             \n"
+                " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetIdleRunTimePercentImpl            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+    #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetIdleRunTimeCounterImpl           \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv            \n"
-        " MPU_ulTaskGetIdleRunTimeCounter_Priv:                 \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_ulTaskGetIdleRunTimeCounterImpl             \n"
-        " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetIdleRunTimeCounterImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetIdleRunTimeCounterImpl           \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv            \n"
+                " MPU_ulTaskGetIdleRunTimeCounter_Priv:                 \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_ulTaskGetIdleRunTimeCounterImpl             \n"
+                " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetIdleRunTimeCounterImpl            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+    #if ( configUSE_APPLICATION_TASK_TAG == 1 )
 
-void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
-                                     TaskHookFunction_t pxHookFunction ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
+                                             TaskHookFunction_t pxHookFunction ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
-                                     TaskHookFunction_t pxHookFunction ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSetApplicationTaskTagImpl            \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_vTaskSetApplicationTaskTag_Unpriv             \n"
-        " MPU_vTaskSetApplicationTaskTag_Priv:                  \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_vTaskSetApplicationTaskTagImpl              \n"
-        " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSetApplicationTaskTagImpl             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
+                                             TaskHookFunction_t pxHookFunction ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskSetApplicationTaskTagImpl            \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_vTaskSetApplicationTaskTag_Unpriv             \n"
+                " MPU_vTaskSetApplicationTaskTag_Priv:                  \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_vTaskSetApplicationTaskTagImpl              \n"
+                " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskSetApplicationTaskTagImpl             \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
+    #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+    #if ( configUSE_APPLICATION_TASK_TAG == 1 )
 
-TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetApplicationTaskTagImpl            \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTaskGetApplicationTaskTag_Unpriv             \n"
-        " MPU_xTaskGetApplicationTaskTag_Priv:                  \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTaskGetApplicationTaskTagImpl              \n"
-        " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetApplicationTaskTagImpl             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetApplicationTaskTagImpl            \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xTaskGetApplicationTaskTag_Unpriv             \n"
+                " MPU_xTaskGetApplicationTaskTag_Priv:                  \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xTaskGetApplicationTaskTagImpl              \n"
+                " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetApplicationTaskTagImpl             \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
+    #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+    #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
 
-void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
-                                            BaseType_t xIndex,
-                                            void * pvValue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
+                                                    BaseType_t xIndex,
+                                                    void * pvValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
-                                            BaseType_t xIndex,
-                                            void * pvValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSetThreadLocalStoragePointerImpl     \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv      \n"
-        " MPU_vTaskSetThreadLocalStoragePointer_Priv:           \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_vTaskSetThreadLocalStoragePointerImpl       \n"
-        " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSetThreadLocalStoragePointerImpl      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
+                                                    BaseType_t xIndex,
+                                                    void * pvValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskSetThreadLocalStoragePointerImpl     \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv      \n"
+                " MPU_vTaskSetThreadLocalStoragePointer_Priv:           \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_vTaskSetThreadLocalStoragePointerImpl       \n"
+                " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskSetThreadLocalStoragePointerImpl      \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
+    #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+    #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
 
-void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
-                                               BaseType_t xIndex ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
+                                                       BaseType_t xIndex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
-                                               BaseType_t xIndex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pvTaskGetThreadLocalStoragePointerImpl    \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv     \n"
-        " MPU_pvTaskGetThreadLocalStoragePointer_Priv:          \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_pvTaskGetThreadLocalStoragePointerImpl      \n"
-        " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pvTaskGetThreadLocalStoragePointerImpl     \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
+                                                       BaseType_t xIndex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pvTaskGetThreadLocalStoragePointerImpl    \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv     \n"
+                " MPU_pvTaskGetThreadLocalStoragePointer_Priv:          \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_pvTaskGetThreadLocalStoragePointerImpl      \n"
+                " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pvTaskGetThreadLocalStoragePointerImpl     \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
+    #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
-                                      const UBaseType_t uxArraySize,
-                                      configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
+                                              const UBaseType_t uxArraySize,
+                                              configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
-                                      const UBaseType_t uxArraySize,
-                                      configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetSystemStateImpl                  \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_uxTaskGetSystemState_Unpriv                   \n"
-        " MPU_uxTaskGetSystemState_Priv:                        \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_uxTaskGetSystemStateImpl                    \n"
-        " MPU_uxTaskGetSystemState_Unpriv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetSystemStateImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
+                                              const UBaseType_t uxArraySize,
+                                              configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskGetSystemStateImpl                  \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_uxTaskGetSystemState_Unpriv                   \n"
+                " MPU_uxTaskGetSystemState_Priv:                        \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_uxTaskGetSystemStateImpl                    \n"
+                " MPU_uxTaskGetSystemState_Unpriv:                      \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskGetSystemStateImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
+    #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
+    #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
 
-UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetStackHighWaterMarkImpl           \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_uxTaskGetStackHighWaterMark_Unpriv            \n"
-        " MPU_uxTaskGetStackHighWaterMark_Priv:                 \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_uxTaskGetStackHighWaterMarkImpl             \n"
-        " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetStackHighWaterMarkImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskGetStackHighWaterMarkImpl           \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_uxTaskGetStackHighWaterMark_Unpriv            \n"
+                " MPU_uxTaskGetStackHighWaterMark_Priv:                 \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_uxTaskGetStackHighWaterMarkImpl             \n"
+                " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskGetStackHighWaterMarkImpl            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */
+    #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
+    #if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
 
-configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetStackHighWaterMark2Impl          \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv           \n"
-        " MPU_uxTaskGetStackHighWaterMark2_Priv:                \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_uxTaskGetStackHighWaterMark2Impl            \n"
-        " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetStackHighWaterMark2Impl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskGetStackHighWaterMark2Impl          \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv           \n"
+                " MPU_uxTaskGetStackHighWaterMark2_Priv:                \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_uxTaskGetStackHighWaterMark2Impl            \n"
+                " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskGetStackHighWaterMark2Impl           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */
+    #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
+    #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
 
-TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetCurrentTaskHandleImpl             \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTaskGetCurrentTaskHandle_Unpriv              \n"
-        " MPU_xTaskGetCurrentTaskHandle_Priv:                   \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTaskGetCurrentTaskHandleImpl               \n"
-        " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetCurrentTaskHandleImpl              \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetCurrentTaskHandleImpl             \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xTaskGetCurrentTaskHandle_Unpriv              \n"
+                " MPU_xTaskGetCurrentTaskHandle_Priv:                   \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xTaskGetCurrentTaskHandleImpl               \n"
+                " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetCurrentTaskHandleImpl              \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
+    #endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_xTaskGetSchedulerState == 1 )
+    #if ( INCLUDE_xTaskGetSchedulerState == 1 )
 
-BaseType_t MPU_xTaskGetSchedulerState( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGetSchedulerState( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGetSchedulerState( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetSchedulerStateImpl                \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTaskGetSchedulerState_Unpriv                 \n"
-        " MPU_xTaskGetSchedulerState_Priv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTaskGetSchedulerStateImpl                  \n"
-        " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetSchedulerStateImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGetSchedulerState( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetSchedulerStateImpl                \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xTaskGetSchedulerState_Unpriv                 \n"
+                " MPU_xTaskGetSchedulerState_Priv:                      \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xTaskGetSchedulerStateImpl                  \n"
+                " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetSchedulerStateImpl                 \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */
+    #endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */
 /*-----------------------------------------------------------*/
 
-void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSetTimeOutStateImpl                  \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_vTaskSetTimeOutState_Unpriv                   \n"
-        " MPU_vTaskSetTimeOutState_Priv:                        \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_vTaskSetTimeOutStateImpl                    \n"
-        " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSetTimeOutStateImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_vTaskSetTimeOutStateImpl                  \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_vTaskSetTimeOutState_Unpriv                   \n"
+            " MPU_vTaskSetTimeOutState_Priv:                        \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_vTaskSetTimeOutStateImpl                    \n"
+            " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_vTaskSetTimeOutStateImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
-                                     TickType_t * const pxTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
+                                         TickType_t * const pxTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
-                                     TickType_t * const pxTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskCheckForTimeOutImpl                  \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTaskCheckForTimeOut_Unpriv                   \n"
-        " MPU_xTaskCheckForTimeOut_Priv:                        \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTaskCheckForTimeOutImpl                    \n"
-        " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskCheckForTimeOutImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
+                                         TickType_t * const pxTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xTaskCheckForTimeOutImpl                  \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xTaskCheckForTimeOut_Unpriv                   \n"
+            " MPU_xTaskCheckForTimeOut_Priv:                        \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xTaskCheckForTimeOutImpl                    \n"
+            " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xTaskCheckForTimeOutImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                   UBaseType_t uxIndexToNotify,
-                                   uint32_t ulValue,
-                                   eNotifyAction eAction,
-                                   uint32_t * pulPreviousNotificationValue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
+                                           UBaseType_t uxIndexToNotify,
+                                           uint32_t ulValue,
+                                           eNotifyAction eAction,
+                                           uint32_t * pulPreviousNotificationValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                   UBaseType_t uxIndexToNotify,
-                                   uint32_t ulValue,
-                                   eNotifyAction eAction,
-                                   uint32_t * pulPreviousNotificationValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGenericNotifyImpl                    \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTaskGenericNotify_Unpriv                     \n"
-        " MPU_xTaskGenericNotify_Priv:                          \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTaskGenericNotifyImpl                      \n"
-        " MPU_xTaskGenericNotify_Unpriv:                        \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGenericNotifyImpl                     \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
+                                           UBaseType_t uxIndexToNotify,
+                                           uint32_t ulValue,
+                                           eNotifyAction eAction,
+                                           uint32_t * pulPreviousNotificationValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGenericNotifyImpl                    \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xTaskGenericNotify_Unpriv                     \n"
+                " MPU_xTaskGenericNotify_Priv:                          \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xTaskGenericNotifyImpl                      \n"
+                " MPU_xTaskGenericNotify_Unpriv:                        \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGenericNotifyImpl                     \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                       uint32_t ulBitsToClearOnEntry,
-                                       uint32_t ulBitsToClearOnExit,
-                                       uint32_t * pulNotificationValue,
-                                       TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
+                                               uint32_t ulBitsToClearOnEntry,
+                                               uint32_t ulBitsToClearOnExit,
+                                               uint32_t * pulNotificationValue,
+                                               TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                       uint32_t ulBitsToClearOnEntry,
-                                       uint32_t ulBitsToClearOnExit,
-                                       uint32_t * pulNotificationValue,
-                                       TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGenericNotifyWaitImpl                \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTaskGenericNotifyWait_Unpriv                 \n"
-        " MPU_xTaskGenericNotifyWait_Priv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTaskGenericNotifyWaitImpl                  \n"
-        " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGenericNotifyWaitImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
+                                               uint32_t ulBitsToClearOnEntry,
+                                               uint32_t ulBitsToClearOnExit,
+                                               uint32_t * pulNotificationValue,
+                                               TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGenericNotifyWaitImpl                \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xTaskGenericNotifyWait_Unpriv                 \n"
+                " MPU_xTaskGenericNotifyWait_Priv:                      \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xTaskGenericNotifyWaitImpl                  \n"
+                " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGenericNotifyWaitImpl                 \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
-                                      BaseType_t xClearCountOnExit,
-                                      TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
+                                              BaseType_t xClearCountOnExit,
+                                              TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
-                                      BaseType_t xClearCountOnExit,
-                                      TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGenericNotifyTakeImpl               \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_ulTaskGenericNotifyTake_Unpriv                \n"
-        " MPU_ulTaskGenericNotifyTake_Priv:                     \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_ulTaskGenericNotifyTakeImpl                 \n"
-        " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGenericNotifyTakeImpl                \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
+                                              BaseType_t xClearCountOnExit,
+                                              TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGenericNotifyTakeImpl               \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_ulTaskGenericNotifyTake_Unpriv                \n"
+                " MPU_ulTaskGenericNotifyTake_Priv:                     \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_ulTaskGenericNotifyTakeImpl                 \n"
+                " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGenericNotifyTakeImpl                \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
-                                             UBaseType_t uxIndexToClear ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
+                                                     UBaseType_t uxIndexToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
-                                             UBaseType_t uxIndexToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGenericNotifyStateClearImpl          \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTaskGenericNotifyStateClear_Unpriv           \n"
-        " MPU_xTaskGenericNotifyStateClear_Priv:                \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTaskGenericNotifyStateClearImpl            \n"
-        " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGenericNotifyStateClearImpl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
+                                                     UBaseType_t uxIndexToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGenericNotifyStateClearImpl          \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xTaskGenericNotifyStateClear_Unpriv           \n"
+                " MPU_xTaskGenericNotifyStateClear_Priv:                \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xTaskGenericNotifyStateClearImpl            \n"
+                " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGenericNotifyStateClearImpl           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
-                                            UBaseType_t uxIndexToClear,
-                                            uint32_t ulBitsToClear ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
+                                                    UBaseType_t uxIndexToClear,
+                                                    uint32_t ulBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
-                                            UBaseType_t uxIndexToClear,
-                                            uint32_t ulBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGenericNotifyValueClearImpl         \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_ulTaskGenericNotifyValueClear_Unpriv          \n"
-        " MPU_ulTaskGenericNotifyValueClear_Priv:               \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_ulTaskGenericNotifyValueClearImpl           \n"
-        " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGenericNotifyValueClearImpl          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
+                                                    UBaseType_t uxIndexToClear,
+                                                    uint32_t ulBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGenericNotifyValueClearImpl         \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_ulTaskGenericNotifyValueClear_Unpriv          \n"
+                " MPU_ulTaskGenericNotifyValueClear_Priv:               \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_ulTaskGenericNotifyValueClearImpl           \n"
+                " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGenericNotifyValueClearImpl          \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
-                                  const void * const pvItemToQueue,
-                                  TickType_t xTicksToWait,
-                                  const BaseType_t xCopyPosition ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
+                                      const void * const pvItemToQueue,
+                                      TickType_t xTicksToWait,
+                                      const BaseType_t xCopyPosition ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
-                                  const void * const pvItemToQueue,
-                                  TickType_t xTicksToWait,
-                                  const BaseType_t xCopyPosition ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueGenericSendImpl                     \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xQueueGenericSend_Unpriv                      \n"
-        " MPU_xQueueGenericSend_Priv:                           \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xQueueGenericSendImpl                       \n"
-        " MPU_xQueueGenericSend_Unpriv:                         \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueGenericSendImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
+                                      const void * const pvItemToQueue,
+                                      TickType_t xTicksToWait,
+                                      const BaseType_t xCopyPosition ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueueGenericSendImpl                     \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xQueueGenericSend_Unpriv                      \n"
+            " MPU_xQueueGenericSend_Priv:                           \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xQueueGenericSendImpl                       \n"
+            " MPU_xQueueGenericSend_Unpriv:                         \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueueGenericSendImpl                      \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxQueueMessagesWaitingImpl                \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_uxQueueMessagesWaiting_Unpriv                 \n"
-        " MPU_uxQueueMessagesWaiting_Priv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_uxQueueMessagesWaitingImpl                  \n"
-        " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxQueueMessagesWaitingImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_uxQueueMessagesWaitingImpl                \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_uxQueueMessagesWaiting_Unpriv                 \n"
+            " MPU_uxQueueMessagesWaiting_Priv:                      \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_uxQueueMessagesWaitingImpl                  \n"
+            " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_uxQueueMessagesWaitingImpl                 \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxQueueSpacesAvailableImpl                \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_uxQueueSpacesAvailable_Unpriv                 \n"
-        " MPU_uxQueueSpacesAvailable_Priv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_uxQueueSpacesAvailableImpl                  \n"
-        " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxQueueSpacesAvailableImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_uxQueueSpacesAvailableImpl                \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_uxQueueSpacesAvailable_Unpriv                 \n"
+            " MPU_uxQueueSpacesAvailable_Priv:                      \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_uxQueueSpacesAvailableImpl                  \n"
+            " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_uxQueueSpacesAvailableImpl                 \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
-                              void * const pvBuffer,
-                              TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
+                                  void * const pvBuffer,
+                                  TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
-                              void * const pvBuffer,
-                              TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueReceiveImpl                         \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xQueueReceive_Unpriv                          \n"
-        " MPU_xQueueReceive_Priv:                               \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xQueueReceiveImpl                           \n"
-        " MPU_xQueueReceive_Unpriv:                             \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueReceiveImpl                          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
+                                  void * const pvBuffer,
+                                  TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueueReceiveImpl                         \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xQueueReceive_Unpriv                          \n"
+            " MPU_xQueueReceive_Priv:                               \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xQueueReceiveImpl                           \n"
+            " MPU_xQueueReceive_Unpriv:                             \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueueReceiveImpl                          \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
-                           void * const pvBuffer,
-                           TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
+                               void * const pvBuffer,
+                               TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
-                           void * const pvBuffer,
-                           TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueuePeekImpl                            \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xQueuePeek_Unpriv                             \n"
-        " MPU_xQueuePeek_Priv:                                  \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xQueuePeekImpl                              \n"
-        " MPU_xQueuePeek_Unpriv:                                \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueuePeekImpl                             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
+                               void * const pvBuffer,
+                               TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueuePeekImpl                            \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xQueuePeek_Unpriv                             \n"
+            " MPU_xQueuePeek_Priv:                                  \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xQueuePeekImpl                              \n"
+            " MPU_xQueuePeek_Unpriv:                                \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueuePeekImpl                             \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
-                                    TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
+                                        TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
-                                    TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueSemaphoreTakeImpl                   \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xQueueSemaphoreTake_Unpriv                    \n"
-        " MPU_xQueueSemaphoreTake_Priv:                         \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xQueueSemaphoreTakeImpl                     \n"
-        " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueSemaphoreTakeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
+                                        TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueueSemaphoreTakeImpl                   \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xQueueSemaphoreTake_Unpriv                    \n"
+            " MPU_xQueueSemaphoreTake_Priv:                         \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xQueueSemaphoreTakeImpl                     \n"
+            " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueueSemaphoreTakeImpl                    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+    #if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
 
-TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueGetMutexHolderImpl                  \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xQueueGetMutexHolder_Unpriv                   \n"
-        " MPU_xQueueGetMutexHolder_Priv:                        \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xQueueGetMutexHolderImpl                    \n"
-        " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueGetMutexHolderImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueGetMutexHolderImpl                  \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xQueueGetMutexHolder_Unpriv                   \n"
+                " MPU_xQueueGetMutexHolder_Priv:                        \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xQueueGetMutexHolderImpl                    \n"
+                " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueGetMutexHolderImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */
+    #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+    #if ( configUSE_RECURSIVE_MUTEXES == 1 )
 
-BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
-                                         TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+                                                 TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+        BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+                                                 TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueTakeMutexRecursiveImpl              \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xQueueTakeMutexRecursive_Unpriv               \n"
+                " MPU_xQueueTakeMutexRecursive_Priv:                    \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xQueueTakeMutexRecursiveImpl                \n"
+                " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueTakeMutexRecursiveImpl               \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_RECURSIVE_MUTEXES == 1 )
+
+        BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueGiveMutexRecursiveImpl              \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xQueueGiveMutexRecursive_Unpriv               \n"
+                " MPU_xQueueGiveMutexRecursive_Priv:                    \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xQueueGiveMutexRecursiveImpl                \n"
+                " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueGiveMutexRecursiveImpl               \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_QUEUE_SETS == 1 )
+
+        QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
+                                                        const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
+                                                        const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueSelectFromSetImpl                   \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xQueueSelectFromSet_Unpriv                    \n"
+                " MPU_xQueueSelectFromSet_Priv:                         \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xQueueSelectFromSetImpl                     \n"
+                " MPU_xQueueSelectFromSet_Unpriv:                       \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueSelectFromSetImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_QUEUE_SETS == 1 )
+
+        BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                                       QueueSetHandle_t xQueueSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                                       QueueSetHandle_t xQueueSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueAddToSetImpl                        \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xQueueAddToSet_Unpriv                         \n"
+                " MPU_xQueueAddToSet_Priv:                              \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xQueueAddToSetImpl                          \n"
+                " MPU_xQueueAddToSet_Unpriv:                            \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueAddToSetImpl                         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+        void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
+                                      const char * pcName ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
+                                      const char * pcName ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vQueueAddToRegistryImpl                   \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_vQueueAddToRegistry_Unpriv                    \n"
+                " MPU_vQueueAddToRegistry_Priv:                         \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_vQueueAddToRegistryImpl                     \n"
+                " MPU_vQueueAddToRegistry_Unpriv:                       \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vQueueAddToRegistryImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+        void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vQueueUnregisterQueueImpl                 \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_vQueueUnregisterQueue_Unpriv                  \n"
+                " MPU_vQueueUnregisterQueue_Priv:                       \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_vQueueUnregisterQueueImpl                   \n"
+                " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vQueueUnregisterQueueImpl                  \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+        const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pcQueueGetNameImpl                        \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_pcQueueGetName_Unpriv                         \n"
+                " MPU_pcQueueGetName_Priv:                              \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_pcQueueGetNameImpl                          \n"
+                " MPU_pcQueueGetName_Unpriv:                            \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pcQueueGetNameImpl                         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pvTimerGetTimerIDImpl                     \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_pvTimerGetTimerID_Unpriv                      \n"
+                " MPU_pvTimerGetTimerID_Priv:                           \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_pvTimerGetTimerIDImpl                       \n"
+                " MPU_pvTimerGetTimerID_Unpriv:                         \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pvTimerGetTimerIDImpl                      \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
+                                   void * pvNewID ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
+                                   void * pvNewID ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTimerSetTimerIDImpl                      \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_vTimerSetTimerID_Unpriv                       \n"
+                " MPU_vTimerSetTimerID_Priv:                            \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_vTimerSetTimerIDImpl                        \n"
+                " MPU_vTimerSetTimerID_Unpriv:                          \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTimerSetTimerIDImpl                       \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerIsTimerActiveImpl                   \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xTimerIsTimerActive_Unpriv                    \n"
+                " MPU_xTimerIsTimerActive_Priv:                         \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xTimerIsTimerActiveImpl                     \n"
+                " MPU_xTimerIsTimerActive_Unpriv:                       \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerIsTimerActiveImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetTimerDaemonTaskHandleImpl        \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv         \n"
+                " MPU_xTimerGetTimerDaemonTaskHandle_Priv:              \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xTimerGetTimerDaemonTaskHandleImpl          \n"
+                " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetTimerDaemonTaskHandleImpl         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                                     const BaseType_t xCommandID,
+                                                     const TickType_t xOptionalValue,
+                                                     BaseType_t * const pxHigherPriorityTaskWoken,
+                                                     const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                                     const BaseType_t xCommandID,
+                                                     const TickType_t xOptionalValue,
+                                                     BaseType_t * const pxHigherPriorityTaskWoken,
+                                                     const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                               \n"
+                " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
+                "                                                               \n"
+                " push {r0, r1}                                                 \n"
+                " mrs r0, control                                               \n"
+                " movs r1, #1                                                   \n"
+                " tst r0, r1                                                    \n"
+                " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
+                " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
+                "     pop {r0, r1}                                              \n"
+                "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
+                " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
+                "     pop {r0, r1}                                              \n"
+                "     svc %0                                                    \n"
+                "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
+                "     svc %1                                                    \n"
+                "     bx lr                                                     \n"
+                "                                                               \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pcTimerGetNameImpl                        \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_pcTimerGetName_Unpriv                         \n"
+                " MPU_pcTimerGetName_Priv:                              \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_pcTimerGetNameImpl                          \n"
+                " MPU_pcTimerGetName_Unpriv:                            \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pcTimerGetNameImpl                         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
+                                      const BaseType_t uxAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
+                                      const BaseType_t uxAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTimerSetReloadModeImpl                   \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_vTimerSetReloadMode_Unpriv                    \n"
+                " MPU_vTimerSetReloadMode_Priv:                         \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_vTimerSetReloadModeImpl                     \n"
+                " MPU_vTimerSetReloadMode_Unpriv:                       \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTimerSetReloadModeImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetReloadModeImpl                   \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xTimerGetReloadMode_Unpriv                    \n"
+                " MPU_xTimerGetReloadMode_Priv:                         \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xTimerGetReloadModeImpl                     \n"
+                " MPU_xTimerGetReloadMode_Unpriv:                       \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetReloadModeImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTimerGetReloadModeImpl                  \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_uxTimerGetReloadMode_Unpriv                   \n"
+                " MPU_uxTimerGetReloadMode_Priv:                        \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_uxTimerGetReloadModeImpl                    \n"
+                " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTimerGetReloadModeImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetPeriodImpl                       \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xTimerGetPeriod_Unpriv                        \n"
+                " MPU_xTimerGetPeriod_Priv:                             \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xTimerGetPeriodImpl                         \n"
+                " MPU_xTimerGetPeriod_Unpriv:                           \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetPeriodImpl                        \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetExpiryTimeImpl                   \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xTimerGetExpiryTime_Unpriv                    \n"
+                " MPU_xTimerGetExpiryTime_Priv:                         \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xTimerGetExpiryTimeImpl                     \n"
+                " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetExpiryTimeImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         const BaseType_t xClearOnExit,
+                                         const BaseType_t xWaitForAllBits,
+                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         const BaseType_t xClearOnExit,
+                                         const BaseType_t xWaitForAllBits,
                                          TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueTakeMutexRecursiveImpl              \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xQueueTakeMutexRecursive_Unpriv               \n"
-        " MPU_xQueueTakeMutexRecursive_Priv:                    \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xQueueTakeMutexRecursiveImpl                \n"
-        " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueTakeMutexRecursiveImpl               \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupWaitBitsImpl                   \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
+            " MPU_xEventGroupWaitBits_Priv:                         \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xEventGroupWaitBitsImpl                     \n"
+            " MPU_xEventGroupWaitBits_Unpriv:                       \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupWaitBitsImpl                    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                          const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueGiveMutexRecursiveImpl              \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xQueueGiveMutexRecursive_Unpriv               \n"
-        " MPU_xQueueGiveMutexRecursive_Priv:                    \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xQueueGiveMutexRecursiveImpl                \n"
-        " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueGiveMutexRecursiveImpl               \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                          const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupClearBitsImpl                  \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xEventGroupClearBits_Unpriv                   \n"
+            " MPU_xEventGroupClearBits_Priv:                        \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xEventGroupClearBitsImpl                    \n"
+            " MPU_xEventGroupClearBits_Unpriv:                      \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupClearBitsImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_QUEUE_SETS == 1 )
+    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                        const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
-                                                const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
-                                                const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueSelectFromSetImpl                   \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xQueueSelectFromSet_Unpriv                    \n"
-        " MPU_xQueueSelectFromSet_Priv:                         \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xQueueSelectFromSetImpl                     \n"
-        " MPU_xQueueSelectFromSet_Unpriv:                       \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueSelectFromSetImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                        const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupSetBitsImpl                    \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xEventGroupSetBits_Unpriv                     \n"
+            " MPU_xEventGroupSetBits_Priv:                          \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xEventGroupSetBitsImpl                      \n"
+            " MPU_xEventGroupSetBits_Unpriv:                        \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupSetBitsImpl                     \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_QUEUE_SETS == 1 )
-
-BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
-                               QueueSetHandle_t xQueueSet ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
-                               QueueSetHandle_t xQueueSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueAddToSetImpl                        \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xQueueAddToSet_Unpriv                         \n"
-        " MPU_xQueueAddToSet_Priv:                              \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xQueueAddToSetImpl                          \n"
-        " MPU_xQueueAddToSet_Unpriv:                            \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueAddToSetImpl                         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_QUEUE_SETS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
-                              const char * pcName ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
-                              const char * pcName ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vQueueAddToRegistryImpl                   \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_vQueueAddToRegistry_Unpriv                    \n"
-        " MPU_vQueueAddToRegistry_Priv:                         \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_vQueueAddToRegistryImpl                     \n"
-        " MPU_vQueueAddToRegistry_Unpriv:                       \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vQueueAddToRegistryImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vQueueUnregisterQueueImpl                 \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_vQueueUnregisterQueue_Unpriv                  \n"
-        " MPU_vQueueUnregisterQueue_Priv:                       \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_vQueueUnregisterQueueImpl                   \n"
-        " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vQueueUnregisterQueueImpl                  \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pcQueueGetNameImpl                        \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_pcQueueGetName_Unpriv                         \n"
-        " MPU_pcQueueGetName_Priv:                              \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_pcQueueGetNameImpl                          \n"
-        " MPU_pcQueueGetName_Unpriv:                            \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pcQueueGetNameImpl                         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pvTimerGetTimerIDImpl                     \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_pvTimerGetTimerID_Unpriv                      \n"
-        " MPU_pvTimerGetTimerID_Priv:                           \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_pvTimerGetTimerIDImpl                       \n"
-        " MPU_pvTimerGetTimerID_Unpriv:                         \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pvTimerGetTimerIDImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
-                           void * pvNewID ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
-                           void * pvNewID ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTimerSetTimerIDImpl                      \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_vTimerSetTimerID_Unpriv                       \n"
-        " MPU_vTimerSetTimerID_Priv:                            \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_vTimerSetTimerIDImpl                        \n"
-        " MPU_vTimerSetTimerID_Unpriv:                          \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTimerSetTimerIDImpl                       \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerIsTimerActiveImpl                   \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTimerIsTimerActive_Unpriv                    \n"
-        " MPU_xTimerIsTimerActive_Priv:                         \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTimerIsTimerActiveImpl                     \n"
-        " MPU_xTimerIsTimerActive_Unpriv:                       \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerIsTimerActiveImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetTimerDaemonTaskHandleImpl        \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv         \n"
-        " MPU_xTimerGetTimerDaemonTaskHandle_Priv:              \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTimerGetTimerDaemonTaskHandleImpl          \n"
-        " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetTimerDaemonTaskHandleImpl         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                             const BaseType_t xCommandID,
-                                             const TickType_t xOptionalValue,
-                                             BaseType_t * const pxHigherPriorityTaskWoken,
-                                             const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                             const BaseType_t xCommandID,
-                                             const TickType_t xOptionalValue,
-                                             BaseType_t * const pxHigherPriorityTaskWoken,
-                                             const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                               \n"
-        " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
-        "                                                               \n"
-        " push {r0, r1}                                                 \n"
-        " mrs r0, control                                               \n"
-        " movs r1, #1                                                   \n"
-        " tst r0, r1                                                    \n"
-        " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
-        " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
-        "     pop {r0, r1}                                              \n"
-        "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
-        " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
-        "     pop {r0, r1}                                              \n"
-        "     svc %0                                                    \n"
-        "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
-        "     svc %1                                                    \n"
-        "     bx lr                                                     \n"
-        "                                                               \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pcTimerGetNameImpl                        \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_pcTimerGetName_Unpriv                         \n"
-        " MPU_pcTimerGetName_Priv:                              \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_pcTimerGetNameImpl                          \n"
-        " MPU_pcTimerGetName_Unpriv:                            \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pcTimerGetNameImpl                         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                              const BaseType_t uxAutoReload ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                              const BaseType_t uxAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTimerSetReloadModeImpl                   \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_vTimerSetReloadMode_Unpriv                    \n"
-        " MPU_vTimerSetReloadMode_Priv:                         \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_vTimerSetReloadModeImpl                     \n"
-        " MPU_vTimerSetReloadMode_Unpriv:                       \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTimerSetReloadModeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetReloadModeImpl                   \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTimerGetReloadMode_Unpriv                    \n"
-        " MPU_xTimerGetReloadMode_Priv:                         \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTimerGetReloadModeImpl                     \n"
-        " MPU_xTimerGetReloadMode_Unpriv:                       \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetReloadModeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTimerGetReloadModeImpl                  \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_uxTimerGetReloadMode_Unpriv                   \n"
-        " MPU_uxTimerGetReloadMode_Priv:                        \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_uxTimerGetReloadModeImpl                    \n"
-        " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTimerGetReloadModeImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetPeriodImpl                       \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTimerGetPeriod_Unpriv                        \n"
-        " MPU_xTimerGetPeriod_Priv:                             \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTimerGetPeriodImpl                         \n"
-        " MPU_xTimerGetPeriod_Unpriv:                           \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetPeriodImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetExpiryTimeImpl                   \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTimerGetExpiryTime_Unpriv                    \n"
-        " MPU_xTimerGetExpiryTime_Priv:                         \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTimerGetExpiryTimeImpl                     \n"
-        " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetExpiryTimeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                     const EventBits_t uxBitsToSet,
                                      const EventBits_t uxBitsToWaitFor,
-                                     const BaseType_t xClearOnExit,
-                                     const BaseType_t xWaitForAllBits,
-                                     TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                     const EventBits_t uxBitsToSet,
                                      const EventBits_t uxBitsToWaitFor,
-                                     const BaseType_t xClearOnExit,
-                                     const BaseType_t xWaitForAllBits,
                                      TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupWaitBitsImpl                   \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
-        " MPU_xEventGroupWaitBits_Priv:                         \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xEventGroupWaitBitsImpl                     \n"
-        " MPU_xEventGroupWaitBits_Unpriv:                       \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupWaitBitsImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupSyncImpl                       \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xEventGroupSync_Unpriv                        \n"
+            " MPU_xEventGroupSync_Priv:                             \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xEventGroupSyncImpl                         \n"
+            " MPU_xEventGroupSync_Unpriv:                           \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupSyncImpl                        \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                      const EventBits_t uxBitsToClear ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                      const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupClearBitsImpl                  \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xEventGroupClearBits_Unpriv                   \n"
-        " MPU_xEventGroupClearBits_Priv:                        \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xEventGroupClearBitsImpl                    \n"
-        " MPU_xEventGroupClearBits_Unpriv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupClearBitsImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxEventGroupGetNumberImpl                 \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_uxEventGroupGetNumber_Unpriv                  \n"
+                " MPU_uxEventGroupGetNumber_Priv:                       \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_uxEventGroupGetNumberImpl                   \n"
+                " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxEventGroupGetNumberImpl                  \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
 /*-----------------------------------------------------------*/
 
-EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                    const EventBits_t uxBitsToSet ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                    const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupSetBitsImpl                    \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xEventGroupSetBits_Unpriv                     \n"
-        " MPU_xEventGroupSetBits_Priv:                          \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xEventGroupSetBitsImpl                      \n"
-        " MPU_xEventGroupSetBits_Unpriv:                        \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupSetBitsImpl                     \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vEventGroupSetNumber( void * xEventGroup,
+                                       UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vEventGroupSetNumber( void * xEventGroup,
+                                       UBaseType_t uxEventGroupNumber ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vEventGroupSetNumberImpl                  \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_vEventGroupSetNumber_Unpriv                   \n"
+                " MPU_vEventGroupSetNumber_Priv:                        \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_vEventGroupSetNumberImpl                    \n"
+                " MPU_vEventGroupSetNumber_Unpriv:                      \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vEventGroupSetNumberImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
 /*-----------------------------------------------------------*/
 
-EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                 const EventBits_t uxBitsToSet,
-                                 const EventBits_t uxBitsToWaitFor,
-                                 TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                  const void * pvTxData,
+                                  size_t xDataLengthBytes,
+                                  TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                 const EventBits_t uxBitsToSet,
-                                 const EventBits_t uxBitsToWaitFor,
-                                 TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupSyncImpl                       \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xEventGroupSync_Unpriv                        \n"
-        " MPU_xEventGroupSync_Priv:                             \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xEventGroupSyncImpl                         \n"
-        " MPU_xEventGroupSync_Unpriv:                           \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupSyncImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                  const void * pvTxData,
+                                  size_t xDataLengthBytes,
+                                  TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferSendImpl                     \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xStreamBufferSend_Unpriv                      \n"
+            " MPU_xStreamBufferSend_Priv:                           \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xStreamBufferSendImpl                       \n"
+            " MPU_xStreamBufferSend_Unpriv:                         \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferSendImpl                      \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                     void * pvRxData,
+                                     size_t xBufferLengthBytes,
+                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxEventGroupGetNumberImpl                 \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_uxEventGroupGetNumber_Unpriv                  \n"
-        " MPU_uxEventGroupGetNumber_Priv:                       \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_uxEventGroupGetNumberImpl                   \n"
-        " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxEventGroupGetNumberImpl                  \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                     void * pvRxData,
+                                     size_t xBufferLengthBytes,
+                                     TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferReceiveImpl                  \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xStreamBufferReceive_Unpriv                   \n"
+            " MPU_xStreamBufferReceive_Priv:                        \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xStreamBufferReceiveImpl                    \n"
+            " MPU_xStreamBufferReceive_Unpriv:                      \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferReceiveImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vEventGroupSetNumber( void * xEventGroup,
-                               UBaseType_t uxEventGroupNumber ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vEventGroupSetNumber( void * xEventGroup,
-                               UBaseType_t uxEventGroupNumber ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vEventGroupSetNumberImpl                  \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_vEventGroupSetNumber_Unpriv                   \n"
-        " MPU_vEventGroupSetNumber_Priv:                        \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_vEventGroupSetNumberImpl                    \n"
-        " MPU_vEventGroupSetNumber_Unpriv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vEventGroupSetNumberImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferIsFullImpl                   \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
+            " MPU_xStreamBufferIsFull_Priv:                         \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xStreamBufferIsFullImpl                     \n"
+            " MPU_xStreamBufferIsFull_Unpriv:                       \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferIsFullImpl                    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                              const void * pvTxData,
-                              size_t xDataLengthBytes,
-                              TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                              const void * pvTxData,
-                              size_t xDataLengthBytes,
-                              TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferSendImpl                     \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xStreamBufferSend_Unpriv                      \n"
-        " MPU_xStreamBufferSend_Priv:                           \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xStreamBufferSendImpl                       \n"
-        " MPU_xStreamBufferSend_Unpriv:                         \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferSendImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
+            " MPU_xStreamBufferIsEmpty_Priv:                        \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xStreamBufferIsEmptyImpl                    \n"
+            " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferIsEmptyImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                 void * pvRxData,
-                                 size_t xBufferLengthBytes,
-                                 TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                 void * pvRxData,
-                                 size_t xBufferLengthBytes,
-                                 TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferReceiveImpl                  \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xStreamBufferReceive_Unpriv                   \n"
-        " MPU_xStreamBufferReceive_Priv:                        \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xStreamBufferReceiveImpl                    \n"
-        " MPU_xStreamBufferReceive_Unpriv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferReceiveImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
+            " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
+            " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferSpacesAvailableImpl           \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferIsFullImpl                   \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
-        " MPU_xStreamBufferIsFull_Priv:                         \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xStreamBufferIsFullImpl                     \n"
-        " MPU_xStreamBufferIsFull_Unpriv:                       \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferIsFullImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
+            " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xStreamBufferBytesAvailableImpl             \n"
+            " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferBytesAvailableImpl            \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                 size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
-        " MPU_xStreamBufferIsEmpty_Priv:                        \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xStreamBufferIsEmptyImpl                    \n"
-        " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferIsEmptyImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                 size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
+            " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
+            " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferSetTriggerLevelImpl           \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
-        " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
-        " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferSpacesAvailableImpl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
-size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
-        " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xStreamBufferBytesAvailableImpl             \n"
-        " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferBytesAvailableImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                             size_t xTriggerLevel ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                             size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
-        " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
-        " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferSetTriggerLevelImpl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
-size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
-        " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
-        " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferNextMessageLengthBytesImpl    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
+            " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
+            " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferNextMessageLengthBytesImpl    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portasm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portasm.c
index b11b6e97c..c1d3b4618 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portasm.c
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portasm.c
@@ -46,127 +46,127 @@
 
 #if ( configENABLE_MPU == 1 )
 
-void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        " .syntax unified                                 \n"
-        "                                                 \n"
-        " program_mpu_first_task:                         \n"
-        "    ldr r3, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB.*/
-        "                                                 \n"
-        "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-        "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
-        "    movs r3, #1                                  \n" /* r3 = 1. */
-        "    bics r2, r3                                  \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
-        "    str r2, [r1]                                 \n" /* Disable MPU. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
-        "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-        "    ldr r2, xMAIR0Const2                         \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-        "    str r1, [r2]                                 \n" /* Program MAIR0. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-        "    ldr r1, xRNRConst2                           \n" /* r1 = 0xe000ed98 [Location of RNR]. */
-        "                                                 \n"
-        "    movs r3, #4                                  \n" /* r3 = 4. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 4. */
-        "    ldmia r0!, {r4-r5}                           \n" /* Read first set of RBAR/RLAR registers from TCB. */
-        "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "    stmia r2!, {r4-r5}                           \n" /* Write first set of RBAR/RLAR registers. */
-        "    movs r3, #5                                  \n" /* r3 = 5. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 5. */
-        "    ldmia r0!, {r4-r5}                           \n" /* Read second set of RBAR/RLAR registers from TCB. */
-        "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "    stmia r2!, {r4-r5}                           \n" /* Write second set of RBAR/RLAR registers. */
-        "    movs r3, #6                                  \n" /* r3 = 6. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 6. */
-        "    ldmia r0!, {r4-r5}                           \n" /* Read third set of RBAR/RLAR registers from TCB. */
-        "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "    stmia r2!, {r4-r5}                           \n" /* Write third set of RBAR/RLAR registers. */
-        "    movs r3, #7                                  \n" /* r3 = 6. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 7. */
-        "    ldmia r0!, {r4-r5}                           \n" /* Read fourth set of RBAR/RLAR registers from TCB. */
-        "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "    stmia r2!, {r4-r5}                           \n" /* Write fourth set of RBAR/RLAR registers. */
-        "                                                 \n"
-        "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
-        "    movs r3, #1                                  \n" /* r3 = 1. */
-        "    orrs r2, r3                                  \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
-        "    str r2, [r1]                                 \n" /* Enable MPU. */
-        "    dsb                                          \n" /* Force memory writes before continuing. */
-        "                                                 \n"
-        " restore_context_first_task:                     \n"
-        "    ldr r2, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB.*/
-        "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
-        "                                                 \n"
-        " restore_special_regs_first_task:                \n"
-        "    subs r1, #16                                 \n"
-        "    ldmia r1!, {r2-r5}                           \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, r5 = LR. */
-        "    subs r1, #16                                 \n"
-        "    msr psp, r2                                  \n"
-        "    msr psplim, r3                               \n"
-        "    msr control, r4                              \n"
-        "    mov lr, r5                                   \n"
-        "                                                 \n"
-        " restore_general_regs_first_task:                \n"
-        "    subs r1, #32                                 \n"
-        "    ldmia r1!, {r4-r7}                           \n" /* r4-r7 contain half of the hardware saved context. */
-        "    stmia r2!, {r4-r7}                           \n" /* Copy half of the the hardware saved context on the task stack. */
-        "    ldmia r1!, {r4-r7}                           \n" /* r4-r7 contain rest half of the hardware saved context. */
-        "    stmia r2!, {r4-r7}                           \n" /* Copy rest half of the the hardware saved context on the task stack. */
-        "    subs r1, #48                                 \n"
-        "    ldmia r1!, {r4-r7}                           \n" /* Restore r8-r11. */
-        "    mov r8, r4                                   \n" /* r8 = r4. */
-        "    mov r9, r5                                   \n" /* r9 = r5. */
-        "    mov r10, r6                                  \n" /* r10 = r6. */
-        "    mov r11, r7                                  \n" /* r11 = r7. */
-        "    subs r1, #32                                 \n"
-        "    ldmia r1!, {r4-r7}                           \n" /* Restore r4-r7. */
-        "    subs r1, #16                                 \n"
-        "                                                 \n"
-        " restore_context_done_first_task:                \n"
-        "    str r1, [r0]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
-        "    bx lr                                        \n"
-        "                                                 \n"
-        " .align 4                                        \n"
-        " pxCurrentTCBConst2: .word pxCurrentTCB          \n"
-        " xMPUCTRLConst2: .word 0xe000ed94                \n"
-        " xMAIR0Const2: .word 0xe000edc0                  \n"
-        " xRNRConst2: .word 0xe000ed98                    \n"
-        " xRBARConst2: .word 0xe000ed9c                   \n"
-    );
-}
+    void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                 \n"
+            "                                                 \n"
+            " program_mpu_first_task:                         \n"
+            "    ldr r3, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB.*/
+            "                                                 \n"
+            "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
+            "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
+            "    movs r3, #1                                  \n" /* r3 = 1. */
+            "    bics r2, r3                                  \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
+            "    str r2, [r1]                                 \n" /* Disable MPU. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
+            "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
+            "    ldr r2, xMAIR0Const2                         \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    str r1, [r2]                                 \n" /* Program MAIR0. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
+            "    ldr r1, xRNRConst2                           \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "                                                 \n"
+            "    movs r3, #4                                  \n" /* r3 = 4. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 4. */
+            "    ldmia r0!, {r4-r5}                           \n" /* Read first set of RBAR/RLAR registers from TCB. */
+            "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    stmia r2!, {r4-r5}                           \n" /* Write first set of RBAR/RLAR registers. */
+            "    movs r3, #5                                  \n" /* r3 = 5. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 5. */
+            "    ldmia r0!, {r4-r5}                           \n" /* Read second set of RBAR/RLAR registers from TCB. */
+            "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    stmia r2!, {r4-r5}                           \n" /* Write second set of RBAR/RLAR registers. */
+            "    movs r3, #6                                  \n" /* r3 = 6. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 6. */
+            "    ldmia r0!, {r4-r5}                           \n" /* Read third set of RBAR/RLAR registers from TCB. */
+            "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    stmia r2!, {r4-r5}                           \n" /* Write third set of RBAR/RLAR registers. */
+            "    movs r3, #7                                  \n" /* r3 = 6. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 7. */
+            "    ldmia r0!, {r4-r5}                           \n" /* Read fourth set of RBAR/RLAR registers from TCB. */
+            "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    stmia r2!, {r4-r5}                           \n" /* Write fourth set of RBAR/RLAR registers. */
+            "                                                 \n"
+            "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
+            "    movs r3, #1                                  \n" /* r3 = 1. */
+            "    orrs r2, r3                                  \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
+            "    str r2, [r1]                                 \n" /* Enable MPU. */
+            "    dsb                                          \n" /* Force memory writes before continuing. */
+            "                                                 \n"
+            " restore_context_first_task:                     \n"
+            "    ldr r2, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB.*/
+            "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
+            "                                                 \n"
+            " restore_special_regs_first_task:                \n"
+            "    subs r1, #16                                 \n"
+            "    ldmia r1!, {r2-r5}                           \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, r5 = LR. */
+            "    subs r1, #16                                 \n"
+            "    msr psp, r2                                  \n"
+            "    msr psplim, r3                               \n"
+            "    msr control, r4                              \n"
+            "    mov lr, r5                                   \n"
+            "                                                 \n"
+            " restore_general_regs_first_task:                \n"
+            "    subs r1, #32                                 \n"
+            "    ldmia r1!, {r4-r7}                           \n" /* r4-r7 contain half of the hardware saved context. */
+            "    stmia r2!, {r4-r7}                           \n" /* Copy half of the the hardware saved context on the task stack. */
+            "    ldmia r1!, {r4-r7}                           \n" /* r4-r7 contain rest half of the hardware saved context. */
+            "    stmia r2!, {r4-r7}                           \n" /* Copy rest half of the the hardware saved context on the task stack. */
+            "    subs r1, #48                                 \n"
+            "    ldmia r1!, {r4-r7}                           \n" /* Restore r8-r11. */
+            "    mov r8, r4                                   \n" /* r8 = r4. */
+            "    mov r9, r5                                   \n" /* r9 = r5. */
+            "    mov r10, r6                                  \n" /* r10 = r6. */
+            "    mov r11, r7                                  \n" /* r11 = r7. */
+            "    subs r1, #32                                 \n"
+            "    ldmia r1!, {r4-r7}                           \n" /* Restore r4-r7. */
+            "    subs r1, #16                                 \n"
+            "                                                 \n"
+            " restore_context_done_first_task:                \n"
+            "    str r1, [r0]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
+            "    bx lr                                        \n"
+            "                                                 \n"
+            " .align 4                                        \n"
+            " pxCurrentTCBConst2: .word pxCurrentTCB          \n"
+            " xMPUCTRLConst2: .word 0xe000ed94                \n"
+            " xMAIR0Const2: .word 0xe000edc0                  \n"
+            " xRNRConst2: .word 0xe000ed98                    \n"
+            " xRBARConst2: .word 0xe000ed9c                   \n"
+        );
+    }
 
 #else /* configENABLE_MPU */
 
-void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "   .syntax unified                                 \n"
-        "                                                   \n"
-        "   ldr  r2, pxCurrentTCBConst2                     \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr  r1, [r2]                                   \n"/* Read pxCurrentTCB. */
-        "   ldr  r0, [r1]                                   \n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
-        "                                                   \n"
-        "   ldm  r0!, {r1-r2}                               \n"/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
-        "   msr  psplim, r1                                 \n"/* Set this task's PSPLIM value. */
-        "   movs r1, #2                                     \n"/* r1 = 2. */
-        "   msr  CONTROL, r1                                \n"/* Switch to use PSP in the thread mode. */
-        "   adds r0, #32                                    \n"/* Discard everything up to r0. */
-        "   msr  psp, r0                                    \n"/* This is now the new top of stack to use in the task. */
-        "   isb                                             \n"
-        "   bx   r2                                         \n"/* Finally, branch to EXC_RETURN. */
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "pxCurrentTCBConst2: .word pxCurrentTCB             \n"
-    );
-}
+    void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            "   .syntax unified                                 \n"
+            "                                                   \n"
+            "   ldr  r2, pxCurrentTCBConst2                     \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr  r1, [r2]                                   \n" /* Read pxCurrentTCB. */
+            "   ldr  r0, [r1]                                   \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+            "                                                   \n"
+            "   ldm  r0!, {r1-r2}                               \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
+            "   msr  psplim, r1                                 \n" /* Set this task's PSPLIM value. */
+            "   movs r1, #2                                     \n" /* r1 = 2. */
+            "   msr  CONTROL, r1                                \n" /* Switch to use PSP in the thread mode. */
+            "   adds r0, #32                                    \n" /* Discard everything up to r0. */
+            "   msr  psp, r0                                    \n" /* This is now the new top of stack to use in the task. */
+            "   isb                                             \n"
+            "   bx   r2                                         \n" /* Finally, branch to EXC_RETURN. */
+            "                                                   \n"
+            "   .align 4                                        \n"
+            "pxCurrentTCBConst2: .word pxCurrentTCB             \n"
+        );
+    }
 
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
@@ -177,15 +177,15 @@ BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs r0, control                                 \n"/* r0 = CONTROL. */
-        "   movs r1, #1                                     \n"/* r1 = 1. */
-        "   tst r0, r1                                      \n"/* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
-        "   beq running_privileged                          \n"/* If the result of previous AND operation was 0, branch. */
-        "   movs r0, #0                                     \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
-        "   bx lr                                           \n"/* Return. */
+        "   mrs r0, control                                 \n" /* r0 = CONTROL. */
+        "   movs r1, #1                                     \n" /* r1 = 1. */
+        "   tst r0, r1                                      \n" /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
+        "   beq running_privileged                          \n" /* If the result of previous AND operation was 0, branch. */
+        "   movs r0, #0                                     \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+        "   bx lr                                           \n" /* Return. */
         " running_privileged:                               \n"
-        "   movs r0, #1                                     \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
-        "   bx lr                                           \n"/* Return. */
+        "   movs r0, #1                                     \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+        "   bx lr                                           \n" /* Return. */
         "                                                   \n"
         "   .align 4                                        \n"
         ::: "r0", "r1", "memory"
@@ -199,11 +199,11 @@ void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs  r0, control                                \n"/* Read the CONTROL register. */
-        "   movs r1, #1                                     \n"/* r1 = 1. */
-        "   bics r0, r1                                     \n"/* Clear the bit 0. */
-        "   msr  control, r0                                \n"/* Write back the new CONTROL value. */
-        "   bx lr                                           \n"/* Return to the caller. */
+        "   mrs  r0, control                                \n" /* Read the CONTROL register. */
+        "   movs r1, #1                                     \n" /* r1 = 1. */
+        "   bics r0, r1                                     \n" /* Clear the bit 0. */
+        "   msr  control, r0                                \n" /* Write back the new CONTROL value. */
+        "   bx lr                                           \n" /* Return to the caller. */
         ::: "r0", "r1", "memory"
     );
 }
@@ -215,11 +215,11 @@ void vResetPrivilege( void ) /* __attribute__ (( naked )) */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs r0, control                                 \n"/* r0 = CONTROL. */
-        "   movs r1, #1                                     \n"/* r1 = 1. */
-        "   orrs r0, r1                                     \n"/* r0 = r0 | r1. */
-        "   msr control, r0                                 \n"/* CONTROL = r0. */
-        "   bx lr                                           \n"/* Return to the caller. */
+        "   mrs r0, control                                 \n" /* r0 = CONTROL. */
+        "   movs r1, #1                                     \n" /* r1 = 1. */
+        "   orrs r0, r1                                     \n" /* r0 = r0 | r1. */
+        "   msr control, r0                                 \n" /* CONTROL = r0. */
+        "   bx lr                                           \n" /* Return to the caller. */
         ::: "r0", "r1", "memory"
     );
 }
@@ -231,14 +231,14 @@ void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   ldr r0, xVTORConst                              \n"/* Use the NVIC offset register to locate the stack. */
-        "   ldr r0, [r0]                                    \n"/* Read the VTOR register which gives the address of vector table. */
-        "   ldr r0, [r0]                                    \n"/* The first entry in vector table is stack pointer. */
-        "   msr msp, r0                                     \n"/* Set the MSP back to the start of the stack. */
-        "   cpsie i                                         \n"/* Globally enable interrupts. */
+        "   ldr r0, xVTORConst                              \n" /* Use the NVIC offset register to locate the stack. */
+        "   ldr r0, [r0]                                    \n" /* Read the VTOR register which gives the address of vector table. */
+        "   ldr r0, [r0]                                    \n" /* The first entry in vector table is stack pointer. */
+        "   msr msp, r0                                     \n" /* Set the MSP back to the start of the stack. */
+        "   cpsie i                                         \n" /* Globally enable interrupts. */
         "   dsb                                             \n"
         "   isb                                             \n"
-        "   svc %0                                          \n"/* System call to start the first task. */
+        "   svc %0                                          \n" /* System call to start the first task. */
         "   nop                                             \n"
         "                                                   \n"
         "   .align 4                                        \n"
@@ -277,254 +277,254 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
 
 #if ( configENABLE_MPU == 1 )
 
-void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        " .syntax unified                                 \n"
-        "                                                 \n"
-        " ldr r2, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        " ldr r0, [r2]                                    \n" /* r0 = pxCurrentTCB. */
-        " ldr r1, [r0]                                    \n" /* r1 = Location in TCB where the context should be saved. */
-        " mrs r2, psp                                     \n" /* r2 = PSP. */
-        "                                                 \n"
-        " save_general_regs:                              \n"
-        "    stmia r1!, {r4-r7}                           \n" /* Store r4-r7. */
-        "    mov r4, r8                                   \n" /* r4 = r8. */
-        "    mov r5, r9                                   \n" /* r5 = r9. */
-        "    mov r6, r10                                  \n" /* r6 = r10. */
-        "    mov r7, r11                                  \n" /* r7 = r11. */
-        "    stmia r1!, {r4-r7}                           \n" /* Store r8-r11. */
-        "    ldmia r2!, {r4-r7}                           \n" /* Copy half of the  hardware saved context into r4-r7. */
-        "    stmia r1!, {r4-r7}                           \n" /* Store the hardware saved context. */
-        "    ldmia r2!, {r4-r7}                           \n" /* Copy rest half of the  hardware saved context into r4-r7. */
-        "    stmia r1!, {r4-r7}                           \n" /* Store the hardware saved context. */
-        "                                                 \n"
-        " save_special_regs:                              \n"
-        "    mrs r2, psp                                  \n" /* r2 = PSP. */
-        "    mrs r3, psplim                               \n" /* r3 = PSPLIM. */
-        "    mrs r4, control                              \n" /* r4 = CONTROL. */
-        "    mov r5, lr                                   \n" /* r5 = LR. */
-        "    stmia r1!, {r2-r5}                           \n" /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
-        "    str r1, [r0]                                 \n" /* Save the location from where the context should be restored as the first member of TCB. */
-        "                                                 \n"
-        " select_next_task:                               \n"
-        "    cpsid i                                      \n"
-        "    bl vTaskSwitchContext                        \n"
-        "    cpsie i                                      \n"
-        "                                                 \n"
-        " program_mpu:                                    \n"
-        "    ldr r3, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB.*/
-        "                                                 \n"
-        "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-        "    ldr r1, xMPUCTRLConst                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
-        "    movs r3, #1                                  \n" /* r3 = 1. */
-        "    bics r2, r3                                  \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
-        "    str r2, [r1]                                 \n" /* Disable MPU. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
-        "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-        "    ldr r2, xMAIR0Const                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-        "    str r1, [r2]                                 \n" /* Program MAIR0. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-        "    ldr r1, xRNRConst                            \n" /* r1 = 0xe000ed98 [Location of RNR]. */
-        "                                                 \n"
-        "    movs r3, #4                                  \n" /* r3 = 4. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 4. */
-        "    ldmia r0!, {r4-r5}                           \n" /* Read first set of RBAR/RLAR registers from TCB. */
-        "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "    stmia r2!, {r4-r5}                           \n" /* Write first set of RBAR/RLAR registers. */
-        "    movs r3, #5                                  \n" /* r3 = 5. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 5. */
-        "    ldmia r0!, {r4-r5}                           \n" /* Read second set of RBAR/RLAR registers from TCB. */
-        "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "    stmia r2!, {r4-r5}                           \n" /* Write second set of RBAR/RLAR registers. */
-        "    movs r3, #6                                  \n" /* r3 = 6. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 6. */
-        "    ldmia r0!, {r4-r5}                           \n" /* Read third set of RBAR/RLAR registers from TCB. */
-        "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "    stmia r2!, {r4-r5}                           \n" /* Write third set of RBAR/RLAR registers. */
-        "    movs r3, #7                                  \n" /* r3 = 6. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 7. */
-        "    ldmia r0!, {r4-r5}                           \n" /* Read fourth set of RBAR/RLAR registers from TCB. */
-        "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "    stmia r2!, {r4-r5}                           \n" /* Write fourth set of RBAR/RLAR registers. */
-        "                                                 \n"
-        "    ldr r1, xMPUCTRLConst                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
-        "    movs r3, #1                                  \n" /* r3 = 1. */
-        "    orrs r2, r3                                  \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
-        "    str r2, [r1]                                 \n" /* Enable MPU. */
-        "    dsb                                          \n" /* Force memory writes before continuing. */
-        "                                                 \n"
-        " restore_context:                                \n"
-        "    ldr r2, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB.*/
-        "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
-        "                                                 \n"
-        " restore_special_regs:                           \n"
-        "    subs r1, #16                                 \n"
-        "    ldmia r1!, {r2-r5}                           \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, r5 = LR. */
-        "    subs r1, #16                                 \n"
-        "    msr psp, r2                                  \n"
-        "    msr psplim, r3                               \n"
-        "    msr control, r4                              \n"
-        "    mov lr, r5                                   \n"
-        "                                                 \n"
-        " restore_general_regs:                           \n"
-        "    subs r1, #32                                 \n"
-        "    ldmia r1!, {r4-r7}                           \n" /* r4-r7 contain half of the hardware saved context. */
-        "    stmia r2!, {r4-r7}                           \n" /* Copy half of the the hardware saved context on the task stack. */
-        "    ldmia r1!, {r4-r7}                           \n" /* r4-r7 contain rest half of the hardware saved context. */
-        "    stmia r2!, {r4-r7}                           \n" /* Copy rest half of the the hardware saved context on the task stack. */
-        "    subs r1, #48                                 \n"
-        "    ldmia r1!, {r4-r7}                           \n" /* Restore r8-r11. */
-        "    mov r8, r4                                   \n" /* r8 = r4. */
-        "    mov r9, r5                                   \n" /* r9 = r5. */
-        "    mov r10, r6                                  \n" /* r10 = r6. */
-        "    mov r11, r7                                  \n" /* r11 = r7. */
-        "    subs r1, #32                                 \n"
-        "    ldmia r1!, {r4-r7}                           \n" /* Restore r4-r7. */
-        "    subs r1, #16                                 \n"
-        "                                                 \n"
-        " restore_context_done:                           \n"
-        "    str r1, [r0]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
-        "    bx lr                                        \n"
-        "                                                 \n"
-        " .align 4                                        \n"
-        " pxCurrentTCBConst: .word pxCurrentTCB           \n"
-        " xMPUCTRLConst: .word 0xe000ed94                 \n"
-        " xMAIR0Const: .word 0xe000edc0                   \n"
-        " xRNRConst: .word 0xe000ed98                     \n"
-        " xRBARConst: .word 0xe000ed9c                    \n"
-    );
-}
+    void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                 \n"
+            "                                                 \n"
+            " ldr r2, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            " ldr r0, [r2]                                    \n" /* r0 = pxCurrentTCB. */
+            " ldr r1, [r0]                                    \n" /* r1 = Location in TCB where the context should be saved. */
+            " mrs r2, psp                                     \n" /* r2 = PSP. */
+            "                                                 \n"
+            " save_general_regs:                              \n"
+            "    stmia r1!, {r4-r7}                           \n" /* Store r4-r7. */
+            "    mov r4, r8                                   \n" /* r4 = r8. */
+            "    mov r5, r9                                   \n" /* r5 = r9. */
+            "    mov r6, r10                                  \n" /* r6 = r10. */
+            "    mov r7, r11                                  \n" /* r7 = r11. */
+            "    stmia r1!, {r4-r7}                           \n" /* Store r8-r11. */
+            "    ldmia r2!, {r4-r7}                           \n" /* Copy half of the  hardware saved context into r4-r7. */
+            "    stmia r1!, {r4-r7}                           \n" /* Store the hardware saved context. */
+            "    ldmia r2!, {r4-r7}                           \n" /* Copy rest half of the  hardware saved context into r4-r7. */
+            "    stmia r1!, {r4-r7}                           \n" /* Store the hardware saved context. */
+            "                                                 \n"
+            " save_special_regs:                              \n"
+            "    mrs r2, psp                                  \n" /* r2 = PSP. */
+            "    mrs r3, psplim                               \n" /* r3 = PSPLIM. */
+            "    mrs r4, control                              \n" /* r4 = CONTROL. */
+            "    mov r5, lr                                   \n" /* r5 = LR. */
+            "    stmia r1!, {r2-r5}                           \n" /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
+            "    str r1, [r0]                                 \n" /* Save the location from where the context should be restored as the first member of TCB. */
+            "                                                 \n"
+            " select_next_task:                               \n"
+            "    cpsid i                                      \n"
+            "    bl vTaskSwitchContext                        \n"
+            "    cpsie i                                      \n"
+            "                                                 \n"
+            " program_mpu:                                    \n"
+            "    ldr r3, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB.*/
+            "                                                 \n"
+            "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
+            "    ldr r1, xMPUCTRLConst                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
+            "    movs r3, #1                                  \n" /* r3 = 1. */
+            "    bics r2, r3                                  \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
+            "    str r2, [r1]                                 \n" /* Disable MPU. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
+            "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
+            "    ldr r2, xMAIR0Const                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    str r1, [r2]                                 \n" /* Program MAIR0. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
+            "    ldr r1, xRNRConst                            \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "                                                 \n"
+            "    movs r3, #4                                  \n" /* r3 = 4. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 4. */
+            "    ldmia r0!, {r4-r5}                           \n" /* Read first set of RBAR/RLAR registers from TCB. */
+            "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    stmia r2!, {r4-r5}                           \n" /* Write first set of RBAR/RLAR registers. */
+            "    movs r3, #5                                  \n" /* r3 = 5. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 5. */
+            "    ldmia r0!, {r4-r5}                           \n" /* Read second set of RBAR/RLAR registers from TCB. */
+            "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    stmia r2!, {r4-r5}                           \n" /* Write second set of RBAR/RLAR registers. */
+            "    movs r3, #6                                  \n" /* r3 = 6. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 6. */
+            "    ldmia r0!, {r4-r5}                           \n" /* Read third set of RBAR/RLAR registers from TCB. */
+            "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    stmia r2!, {r4-r5}                           \n" /* Write third set of RBAR/RLAR registers. */
+            "    movs r3, #7                                  \n" /* r3 = 6. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 7. */
+            "    ldmia r0!, {r4-r5}                           \n" /* Read fourth set of RBAR/RLAR registers from TCB. */
+            "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    stmia r2!, {r4-r5}                           \n" /* Write fourth set of RBAR/RLAR registers. */
+            "                                                 \n"
+            "    ldr r1, xMPUCTRLConst                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
+            "    movs r3, #1                                  \n" /* r3 = 1. */
+            "    orrs r2, r3                                  \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
+            "    str r2, [r1]                                 \n" /* Enable MPU. */
+            "    dsb                                          \n" /* Force memory writes before continuing. */
+            "                                                 \n"
+            " restore_context:                                \n"
+            "    ldr r2, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB.*/
+            "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
+            "                                                 \n"
+            " restore_special_regs:                           \n"
+            "    subs r1, #16                                 \n"
+            "    ldmia r1!, {r2-r5}                           \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, r5 = LR. */
+            "    subs r1, #16                                 \n"
+            "    msr psp, r2                                  \n"
+            "    msr psplim, r3                               \n"
+            "    msr control, r4                              \n"
+            "    mov lr, r5                                   \n"
+            "                                                 \n"
+            " restore_general_regs:                           \n"
+            "    subs r1, #32                                 \n"
+            "    ldmia r1!, {r4-r7}                           \n" /* r4-r7 contain half of the hardware saved context. */
+            "    stmia r2!, {r4-r7}                           \n" /* Copy half of the the hardware saved context on the task stack. */
+            "    ldmia r1!, {r4-r7}                           \n" /* r4-r7 contain rest half of the hardware saved context. */
+            "    stmia r2!, {r4-r7}                           \n" /* Copy rest half of the the hardware saved context on the task stack. */
+            "    subs r1, #48                                 \n"
+            "    ldmia r1!, {r4-r7}                           \n" /* Restore r8-r11. */
+            "    mov r8, r4                                   \n" /* r8 = r4. */
+            "    mov r9, r5                                   \n" /* r9 = r5. */
+            "    mov r10, r6                                  \n" /* r10 = r6. */
+            "    mov r11, r7                                  \n" /* r11 = r7. */
+            "    subs r1, #32                                 \n"
+            "    ldmia r1!, {r4-r7}                           \n" /* Restore r4-r7. */
+            "    subs r1, #16                                 \n"
+            "                                                 \n"
+            " restore_context_done:                           \n"
+            "    str r1, [r0]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
+            "    bx lr                                        \n"
+            "                                                 \n"
+            " .align 4                                        \n"
+            " pxCurrentTCBConst: .word pxCurrentTCB           \n"
+            " xMPUCTRLConst: .word 0xe000ed94                 \n"
+            " xMAIR0Const: .word 0xe000edc0                   \n"
+            " xRNRConst: .word 0xe000ed98                     \n"
+            " xRBARConst: .word 0xe000ed9c                    \n"
+        );
+    }
 
 #else /* configENABLE_MPU */
 
-void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "   .syntax unified                                 \n"
-        "                                                   \n"
-        "   mrs r0, psp                                     \n"/* Read PSP in r0. */
-        "   ldr r2, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r2]                                    \n"/* Read pxCurrentTCB. */
-        "   subs r0, r0, #40                                \n"/* Make space for PSPLIM, LR and the remaining registers on the stack. */
-        "   str r0, [r1]                                    \n"/* Save the new top of stack in TCB. */
-        "   mrs r2, psplim                                  \n"/* r2 = PSPLIM. */
-        "   mov r3, lr                                      \n"/* r3 = LR/EXC_RETURN. */
-        "   stmia r0!, {r2-r7}                              \n"/* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */
-        "   mov r4, r8                                      \n"/* r4 = r8. */
-        "   mov r5, r9                                      \n"/* r5 = r9. */
-        "   mov r6, r10                                     \n"/* r6 = r10. */
-        "   mov r7, r11                                     \n"/* r7 = r11. */
-        "   stmia r0!, {r4-r7}                              \n"/* Store the high registers that are not saved automatically. */
-        "                                                   \n"
-        "   cpsid i                                         \n"
-        "   bl vTaskSwitchContext                           \n"
-        "   cpsie i                                         \n"
-        "                                                   \n"
-        "   ldr r2, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r2]                                    \n"/* Read pxCurrentTCB. */
-        "   ldr r0, [r1]                                    \n"/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
-        "                                                   \n"
-        "   adds r0, r0, #24                                \n"/* Move to the high registers. */
-        "   ldmia r0!, {r4-r7}                              \n"/* Restore the high registers that are not automatically restored. */
-        "   mov r8, r4                                      \n"/* r8 = r4. */
-        "   mov r9, r5                                      \n"/* r9 = r5. */
-        "   mov r10, r6                                     \n"/* r10 = r6. */
-        "   mov r11, r7                                     \n"/* r11 = r7. */
-        "   msr psp, r0                                     \n"/* Remember the new top of stack for the task. */
-        "   subs r0, r0, #40                                \n"/* Move to the starting of the saved context. */
-        "   ldmia r0!, {r2-r7}                              \n"/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */
-        "   msr psplim, r2                                  \n"/* Restore the PSPLIM register value for the task. */
-        "   bx r3                                           \n"
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "pxCurrentTCBConst: .word pxCurrentTCB              \n"
-    );
-}
+    void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            "   .syntax unified                                 \n"
+            "                                                   \n"
+            "   mrs r0, psp                                     \n" /* Read PSP in r0. */
+            "   ldr r2, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r1, [r2]                                    \n" /* Read pxCurrentTCB. */
+            "   subs r0, r0, #40                                \n" /* Make space for PSPLIM, LR and the remaining registers on the stack. */
+            "   str r0, [r1]                                    \n" /* Save the new top of stack in TCB. */
+            "   mrs r2, psplim                                  \n" /* r2 = PSPLIM. */
+            "   mov r3, lr                                      \n" /* r3 = LR/EXC_RETURN. */
+            "   stmia r0!, {r2-r7}                              \n" /* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */
+            "   mov r4, r8                                      \n" /* r4 = r8. */
+            "   mov r5, r9                                      \n" /* r5 = r9. */
+            "   mov r6, r10                                     \n" /* r6 = r10. */
+            "   mov r7, r11                                     \n" /* r7 = r11. */
+            "   stmia r0!, {r4-r7}                              \n" /* Store the high registers that are not saved automatically. */
+            "                                                   \n"
+            "   cpsid i                                         \n"
+            "   bl vTaskSwitchContext                           \n"
+            "   cpsie i                                         \n"
+            "                                                   \n"
+            "   ldr r2, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r1, [r2]                                    \n" /* Read pxCurrentTCB. */
+            "   ldr r0, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
+            "                                                   \n"
+            "   adds r0, r0, #24                                \n" /* Move to the high registers. */
+            "   ldmia r0!, {r4-r7}                              \n" /* Restore the high registers that are not automatically restored. */
+            "   mov r8, r4                                      \n" /* r8 = r4. */
+            "   mov r9, r5                                      \n" /* r9 = r5. */
+            "   mov r10, r6                                     \n" /* r10 = r6. */
+            "   mov r11, r7                                     \n" /* r11 = r7. */
+            "   msr psp, r0                                     \n" /* Remember the new top of stack for the task. */
+            "   subs r0, r0, #40                                \n" /* Move to the starting of the saved context. */
+            "   ldmia r0!, {r2-r7}                              \n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */
+            "   msr psplim, r2                                  \n" /* Restore the PSPLIM register value for the task. */
+            "   bx r3                                           \n"
+            "                                                   \n"
+            "   .align 4                                        \n"
+            "pxCurrentTCBConst: .word pxCurrentTCB              \n"
+        );
+    }
 
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-   __asm volatile
-    (
-        ".syntax unified                \n"
-        ".extern vPortSVCHandler_C      \n"
-        ".extern vSystemCallEnter       \n"
-        ".extern vSystemCallEnter_1     \n"
-        ".extern vSystemCallExit        \n"
-        "                               \n"
-        "movs r0, #4                    \n"
-        "mov r1, lr                     \n"
-        "tst r0, r1                     \n"
-        "beq stack_on_msp               \n"
-        "stack_on_psp:                  \n"
-        "    mrs r0, psp                \n"
-        "    b route_svc                \n"
-        "stack_on_msp:                  \n"
-        "    mrs r0, msp                \n"
-        "    b route_svc                \n"
-        "                               \n"
-        "route_svc:                     \n"
-        "    ldr r2, [r0, #24]          \n"
-        "    subs r2, #2                \n"
-        "    ldrb r3, [r2, #0]          \n"
-        "    cmp r3, %0                 \n"
-        "    beq system_call_enter      \n"
-        "    cmp r3, %1                 \n"
-        "    beq system_call_enter_1    \n"
-        "    cmp r3, %2                 \n"
-        "    beq system_call_exit       \n"
-        "    b vPortSVCHandler_C        \n"
-        "                               \n"
-        "system_call_enter:             \n"
-        "    b vSystemCallEnter         \n"
-        "system_call_enter_1:           \n"
-        "    b vSystemCallEnter_1       \n"
-        "system_call_exit:              \n"
-        "    b vSystemCallExit          \n"
-        "                               \n"
-        : /* No outputs. */
-        :"i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT )
-        : "r0", "r1", "r2", "r3", "memory"
-    );
-}
+    void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            ".syntax unified                \n"
+            ".extern vPortSVCHandler_C      \n"
+            ".extern vSystemCallEnter       \n"
+            ".extern vSystemCallEnter_1     \n"
+            ".extern vSystemCallExit        \n"
+            "                               \n"
+            "movs r0, #4                    \n"
+            "mov r1, lr                     \n"
+            "tst r0, r1                     \n"
+            "beq stack_on_msp               \n"
+            "stack_on_psp:                  \n"
+            "    mrs r0, psp                \n"
+            "    b route_svc                \n"
+            "stack_on_msp:                  \n"
+            "    mrs r0, msp                \n"
+            "    b route_svc                \n"
+            "                               \n"
+            "route_svc:                     \n"
+            "    ldr r2, [r0, #24]          \n"
+            "    subs r2, #2                \n"
+            "    ldrb r3, [r2, #0]          \n"
+            "    cmp r3, %0                 \n"
+            "    beq system_call_enter      \n"
+            "    cmp r3, %1                 \n"
+            "    beq system_call_enter_1    \n"
+            "    cmp r3, %2                 \n"
+            "    beq system_call_exit       \n"
+            "    b vPortSVCHandler_C        \n"
+            "                               \n"
+            "system_call_enter:             \n"
+            "    b vSystemCallEnter         \n"
+            "system_call_enter_1:           \n"
+            "    b vSystemCallEnter_1       \n"
+            "system_call_exit:              \n"
+            "    b vSystemCallExit          \n"
+            "                               \n"
+            : /* No outputs. */
+            : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT )
+            : "r0", "r1", "r2", "r3", "memory"
+        );
+    }
 
 #else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
-void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "   .syntax unified                                 \n"
-        "                                                   \n"
-        "   movs r0, #4                                     \n"
-        "   mov r1, lr                                      \n"
-        "   tst r0, r1                                      \n"
-        "   beq stacking_used_msp                           \n"
-        "   mrs r0, psp                                     \n"
-        "   ldr r2, svchandler_address_const                \n"
-        "   bx r2                                           \n"
-        " stacking_used_msp:                                \n"
-        "   mrs r0, msp                                     \n"
-        "   ldr r2, svchandler_address_const                \n"
-        "   bx r2                                           \n"
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "svchandler_address_const: .word vPortSVCHandler_C  \n"
-    );
-}
+    void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            "   .syntax unified                                 \n"
+            "                                                   \n"
+            "   movs r0, #4                                     \n"
+            "   mov r1, lr                                      \n"
+            "   tst r0, r1                                      \n"
+            "   beq stacking_used_msp                           \n"
+            "   mrs r0, psp                                     \n"
+            "   ldr r2, svchandler_address_const                \n"
+            "   bx r2                                           \n"
+            " stacking_used_msp:                                \n"
+            "   mrs r0, msp                                     \n"
+            "   ldr r2, svchandler_address_const                \n"
+            "   bx r2                                           \n"
+            "                                                   \n"
+            "   .align 4                                        \n"
+            "svchandler_address_const: .word vPortSVCHandler_C  \n"
+        );
+    }
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h
index 233ea5a57..33d522488 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h
@@ -48,9 +48,9 @@
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME                       "Cortex-M23"
-#define portHAS_ARMV8M_MAIN_EXTENSION       0
-#define portDONT_DISCARD                    __attribute__( ( used ) )
+#define portARCH_NAME                    "Cortex-M23"
+#define portHAS_ARMV8M_MAIN_EXTENSION    0
+#define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
 /* ARMv8-M common port configurations. */
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/mpu_wrappers_v2_asm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/mpu_wrappers_v2_asm.c
index 2d1218a95..d1fbdc0e5 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/mpu_wrappers_v2_asm.c
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/mpu_wrappers_v2_asm.c
@@ -44,2274 +44,2274 @@
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-#if ( INCLUDE_xTaskDelayUntil == 1 )
+    #if ( INCLUDE_xTaskDelayUntil == 1 )
 
-BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
-                                const TickType_t xTimeIncrement ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
+                                        const TickType_t xTimeIncrement ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
-                                const TickType_t xTimeIncrement ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskDelayUntilImpl                       \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskDelayUntil_Unpriv                        \n"
-        " MPU_xTaskDelayUntil_Priv:                             \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskDelayUntilImpl                         \n"
-        " MPU_xTaskDelayUntil_Unpriv:                           \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskDelayUntilImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
+                                        const TickType_t xTimeIncrement ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskDelayUntilImpl                       \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskDelayUntil_Unpriv                        \n"
+                " MPU_xTaskDelayUntil_Priv:                             \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskDelayUntilImpl                         \n"
+                " MPU_xTaskDelayUntil_Unpriv:                           \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskDelayUntilImpl                        \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */
+    #endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_xTaskAbortDelay == 1 )
+    #if ( INCLUDE_xTaskAbortDelay == 1 )
 
-BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskAbortDelayImpl                       \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskAbortDelay_Unpriv                        \n"
-        " MPU_xTaskAbortDelay_Priv:                             \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskAbortDelayImpl                         \n"
-        " MPU_xTaskAbortDelay_Unpriv:                           \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskAbortDelayImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskAbortDelayImpl                       \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskAbortDelay_Unpriv                        \n"
+                " MPU_xTaskAbortDelay_Priv:                             \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskAbortDelayImpl                         \n"
+                " MPU_xTaskAbortDelay_Unpriv:                           \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskAbortDelayImpl                        \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */
+    #endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_vTaskDelay == 1 )
+    #if ( INCLUDE_vTaskDelay == 1 )
 
-void MPU_vTaskDelay( const TickType_t xTicksToDelay ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskDelay( const TickType_t xTicksToDelay ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskDelayImpl                            \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskDelay_Unpriv                             \n"
-        " MPU_vTaskDelay_Priv:                                  \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskDelayImpl                              \n"
-        " MPU_vTaskDelay_Unpriv:                                \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskDelayImpl                             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskDelayImpl                            \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskDelay_Unpriv                             \n"
+                " MPU_vTaskDelay_Priv:                                  \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskDelayImpl                              \n"
+                " MPU_vTaskDelay_Unpriv:                                \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskDelayImpl                             \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_vTaskDelay == 1 ) */
+    #endif /* if ( INCLUDE_vTaskDelay == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_uxTaskPriorityGet == 1 )
+    #if ( INCLUDE_uxTaskPriorityGet == 1 )
 
-UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskPriorityGetImpl                     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTaskPriorityGet_Unpriv                      \n"
-        " MPU_uxTaskPriorityGet_Priv:                           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTaskPriorityGetImpl                       \n"
-        " MPU_uxTaskPriorityGet_Unpriv:                         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskPriorityGetImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskPriorityGetImpl                     \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTaskPriorityGet_Unpriv                      \n"
+                " MPU_uxTaskPriorityGet_Priv:                           \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTaskPriorityGetImpl                       \n"
+                " MPU_uxTaskPriorityGet_Unpriv:                         \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskPriorityGetImpl                      \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */
+    #endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_eTaskGetState == 1 )
+    #if ( INCLUDE_eTaskGetState == 1 )
 
-eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_eTaskGetStateImpl                         \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_eTaskGetState_Unpriv                          \n"
-        " MPU_eTaskGetState_Priv:                               \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_eTaskGetStateImpl                           \n"
-        " MPU_eTaskGetState_Unpriv:                             \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_eTaskGetStateImpl                          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_eTaskGetStateImpl                         \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_eTaskGetState_Unpriv                          \n"
+                " MPU_eTaskGetState_Priv:                               \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_eTaskGetStateImpl                           \n"
+                " MPU_eTaskGetState_Unpriv:                             \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_eTaskGetStateImpl                          \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_eTaskGetState == 1 ) */
+    #endif /* if ( INCLUDE_eTaskGetState == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-void MPU_vTaskGetInfo( TaskHandle_t xTask,
-                       TaskStatus_t * pxTaskStatus,
-                       BaseType_t xGetFreeStackSpace,
-                       eTaskState eState ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskGetInfo( TaskHandle_t xTask,
+                               TaskStatus_t * pxTaskStatus,
+                               BaseType_t xGetFreeStackSpace,
+                               eTaskState eState ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskGetInfo( TaskHandle_t xTask,
-                       TaskStatus_t * pxTaskStatus,
-                       BaseType_t xGetFreeStackSpace,
-                       eTaskState eState ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskGetInfoImpl                          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskGetInfo_Unpriv                           \n"
-        " MPU_vTaskGetInfo_Priv:                                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskGetInfoImpl                            \n"
-        " MPU_vTaskGetInfo_Unpriv:                              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskGetInfoImpl                           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskGetInfo( TaskHandle_t xTask,
+                               TaskStatus_t * pxTaskStatus,
+                               BaseType_t xGetFreeStackSpace,
+                               eTaskState eState ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskGetInfoImpl                          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskGetInfo_Unpriv                           \n"
+                " MPU_vTaskGetInfo_Priv:                                \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskGetInfoImpl                            \n"
+                " MPU_vTaskGetInfo_Unpriv:                              \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskGetInfoImpl                           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
+    #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
+    #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
 
-TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetIdleTaskHandleImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGetIdleTaskHandle_Unpriv                 \n"
-        " MPU_xTaskGetIdleTaskHandle_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGetIdleTaskHandleImpl                  \n"
-        " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetIdleTaskHandleImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetIdleTaskHandleImpl                \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGetIdleTaskHandle_Unpriv                 \n"
+                " MPU_xTaskGetIdleTaskHandle_Priv:                      \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGetIdleTaskHandleImpl                  \n"
+                " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetIdleTaskHandleImpl                 \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */
+    #endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_vTaskSuspend == 1 )
+    #if ( INCLUDE_vTaskSuspend == 1 )
 
-void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSuspendImpl                          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskSuspend_Unpriv                           \n"
-        " MPU_vTaskSuspend_Priv:                                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskSuspendImpl                            \n"
-        " MPU_vTaskSuspend_Unpriv:                              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSuspendImpl                           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskSuspendImpl                          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskSuspend_Unpriv                           \n"
+                " MPU_vTaskSuspend_Priv:                                \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskSuspendImpl                            \n"
+                " MPU_vTaskSuspend_Unpriv:                              \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskSuspendImpl                           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
+    #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_vTaskSuspend == 1 )
+    #if ( INCLUDE_vTaskSuspend == 1 )
 
-void MPU_vTaskResume( TaskHandle_t xTaskToResume ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskResume( TaskHandle_t xTaskToResume ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskResumeImpl                           \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskResume_Unpriv                            \n"
-        " MPU_vTaskResume_Priv:                                 \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskResumeImpl                             \n"
-        " MPU_vTaskResume_Unpriv:                               \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskResumeImpl                            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskResumeImpl                           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskResume_Unpriv                            \n"
+                " MPU_vTaskResume_Priv:                                 \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskResumeImpl                             \n"
+                " MPU_vTaskResume_Unpriv:                               \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskResumeImpl                            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
+    #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
 /*-----------------------------------------------------------*/
 
-TickType_t MPU_xTaskGetTickCount( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    TickType_t MPU_xTaskGetTickCount( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TickType_t MPU_xTaskGetTickCount( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetTickCountImpl                     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGetTickCount_Unpriv                      \n"
-        " MPU_xTaskGetTickCount_Priv:                           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGetTickCountImpl                       \n"
-        " MPU_xTaskGetTickCount_Unpriv:                         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetTickCountImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    TickType_t MPU_xTaskGetTickCount( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xTaskGetTickCountImpl                     \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xTaskGetTickCount_Unpriv                      \n"
+            " MPU_xTaskGetTickCount_Priv:                           \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xTaskGetTickCountImpl                       \n"
+            " MPU_xTaskGetTickCount_Unpriv:                         \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xTaskGetTickCountImpl                      \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetNumberOfTasksImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTaskGetNumberOfTasks_Unpriv                 \n"
-        " MPU_uxTaskGetNumberOfTasks_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTaskGetNumberOfTasksImpl                  \n"
-        " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetNumberOfTasksImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_uxTaskGetNumberOfTasksImpl                \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_uxTaskGetNumberOfTasks_Unpriv                 \n"
+            " MPU_uxTaskGetNumberOfTasks_Priv:                      \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_uxTaskGetNumberOfTasksImpl                  \n"
+            " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_uxTaskGetNumberOfTasksImpl                 \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configGENERATE_RUN_TIME_STATS == 1 )
+    #if ( configGENERATE_RUN_TIME_STATS == 1 )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetRunTimeCounterImpl               \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGetRunTimeCounter_Unpriv                \n"
-        " MPU_ulTaskGetRunTimeCounter_Priv:                     \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGetRunTimeCounterImpl                 \n"
-        " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetRunTimeCounterImpl                \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetRunTimeCounterImpl               \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGetRunTimeCounter_Unpriv                \n"
+                " MPU_ulTaskGetRunTimeCounter_Priv:                     \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGetRunTimeCounterImpl                 \n"
+                " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetRunTimeCounterImpl                \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configGENERATE_RUN_TIME_STATS == 1 )
+    #if ( configGENERATE_RUN_TIME_STATS == 1 )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetRunTimePercentImpl               \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGetRunTimePercent_Unpriv                \n"
-        " MPU_ulTaskGetRunTimePercent_Priv:                     \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGetRunTimePercentImpl                 \n"
-        " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetRunTimePercentImpl                \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetRunTimePercentImpl               \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGetRunTimePercent_Unpriv                \n"
+                " MPU_ulTaskGetRunTimePercent_Priv:                     \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGetRunTimePercentImpl                 \n"
+                " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetRunTimePercentImpl                \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+    #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetIdleRunTimePercentImpl           \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv            \n"
-        " MPU_ulTaskGetIdleRunTimePercent_Priv:                 \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGetIdleRunTimePercentImpl             \n"
-        " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetIdleRunTimePercentImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetIdleRunTimePercentImpl           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv            \n"
+                " MPU_ulTaskGetIdleRunTimePercent_Priv:                 \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGetIdleRunTimePercentImpl             \n"
+                " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetIdleRunTimePercentImpl            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+    #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetIdleRunTimeCounterImpl           \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv            \n"
-        " MPU_ulTaskGetIdleRunTimeCounter_Priv:                 \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGetIdleRunTimeCounterImpl             \n"
-        " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetIdleRunTimeCounterImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetIdleRunTimeCounterImpl           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv            \n"
+                " MPU_ulTaskGetIdleRunTimeCounter_Priv:                 \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGetIdleRunTimeCounterImpl             \n"
+                " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetIdleRunTimeCounterImpl            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+    #if ( configUSE_APPLICATION_TASK_TAG == 1 )
 
-void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
-                                     TaskHookFunction_t pxHookFunction ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
+                                             TaskHookFunction_t pxHookFunction ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
-                                     TaskHookFunction_t pxHookFunction ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSetApplicationTaskTagImpl            \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskSetApplicationTaskTag_Unpriv             \n"
-        " MPU_vTaskSetApplicationTaskTag_Priv:                  \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskSetApplicationTaskTagImpl              \n"
-        " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSetApplicationTaskTagImpl             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
+                                             TaskHookFunction_t pxHookFunction ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskSetApplicationTaskTagImpl            \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskSetApplicationTaskTag_Unpriv             \n"
+                " MPU_vTaskSetApplicationTaskTag_Priv:                  \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskSetApplicationTaskTagImpl              \n"
+                " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskSetApplicationTaskTagImpl             \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
+    #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+    #if ( configUSE_APPLICATION_TASK_TAG == 1 )
 
-TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetApplicationTaskTagImpl            \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGetApplicationTaskTag_Unpriv             \n"
-        " MPU_xTaskGetApplicationTaskTag_Priv:                  \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGetApplicationTaskTagImpl              \n"
-        " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetApplicationTaskTagImpl             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetApplicationTaskTagImpl            \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGetApplicationTaskTag_Unpriv             \n"
+                " MPU_xTaskGetApplicationTaskTag_Priv:                  \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGetApplicationTaskTagImpl              \n"
+                " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetApplicationTaskTagImpl             \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
+    #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+    #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
 
-void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
-                                            BaseType_t xIndex,
-                                            void * pvValue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
+                                                    BaseType_t xIndex,
+                                                    void * pvValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
-                                            BaseType_t xIndex,
-                                            void * pvValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSetThreadLocalStoragePointerImpl     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv      \n"
-        " MPU_vTaskSetThreadLocalStoragePointer_Priv:           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskSetThreadLocalStoragePointerImpl       \n"
-        " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSetThreadLocalStoragePointerImpl      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
+                                                    BaseType_t xIndex,
+                                                    void * pvValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskSetThreadLocalStoragePointerImpl     \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv      \n"
+                " MPU_vTaskSetThreadLocalStoragePointer_Priv:           \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskSetThreadLocalStoragePointerImpl       \n"
+                " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskSetThreadLocalStoragePointerImpl      \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
+    #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+    #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
 
-void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
-                                               BaseType_t xIndex ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
+                                                       BaseType_t xIndex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
-                                               BaseType_t xIndex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pvTaskGetThreadLocalStoragePointerImpl    \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv     \n"
-        " MPU_pvTaskGetThreadLocalStoragePointer_Priv:          \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_pvTaskGetThreadLocalStoragePointerImpl      \n"
-        " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pvTaskGetThreadLocalStoragePointerImpl     \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
+                                                       BaseType_t xIndex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pvTaskGetThreadLocalStoragePointerImpl    \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv     \n"
+                " MPU_pvTaskGetThreadLocalStoragePointer_Priv:          \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_pvTaskGetThreadLocalStoragePointerImpl      \n"
+                " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pvTaskGetThreadLocalStoragePointerImpl     \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
+    #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
-                                      const UBaseType_t uxArraySize,
-                                      configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
+                                              const UBaseType_t uxArraySize,
+                                              configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
-                                      const UBaseType_t uxArraySize,
-                                      configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetSystemStateImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTaskGetSystemState_Unpriv                   \n"
-        " MPU_uxTaskGetSystemState_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTaskGetSystemStateImpl                    \n"
-        " MPU_uxTaskGetSystemState_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetSystemStateImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
+                                              const UBaseType_t uxArraySize,
+                                              configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskGetSystemStateImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTaskGetSystemState_Unpriv                   \n"
+                " MPU_uxTaskGetSystemState_Priv:                        \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTaskGetSystemStateImpl                    \n"
+                " MPU_uxTaskGetSystemState_Unpriv:                      \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskGetSystemStateImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
+    #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
+    #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
 
-UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetStackHighWaterMarkImpl           \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTaskGetStackHighWaterMark_Unpriv            \n"
-        " MPU_uxTaskGetStackHighWaterMark_Priv:                 \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTaskGetStackHighWaterMarkImpl             \n"
-        " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetStackHighWaterMarkImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskGetStackHighWaterMarkImpl           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTaskGetStackHighWaterMark_Unpriv            \n"
+                " MPU_uxTaskGetStackHighWaterMark_Priv:                 \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTaskGetStackHighWaterMarkImpl             \n"
+                " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskGetStackHighWaterMarkImpl            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */
+    #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
+    #if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
 
-configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetStackHighWaterMark2Impl          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv           \n"
-        " MPU_uxTaskGetStackHighWaterMark2_Priv:                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTaskGetStackHighWaterMark2Impl            \n"
-        " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetStackHighWaterMark2Impl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskGetStackHighWaterMark2Impl          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv           \n"
+                " MPU_uxTaskGetStackHighWaterMark2_Priv:                \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTaskGetStackHighWaterMark2Impl            \n"
+                " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskGetStackHighWaterMark2Impl           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */
+    #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
+    #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
 
-TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetCurrentTaskHandleImpl             \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGetCurrentTaskHandle_Unpriv              \n"
-        " MPU_xTaskGetCurrentTaskHandle_Priv:                   \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGetCurrentTaskHandleImpl               \n"
-        " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetCurrentTaskHandleImpl              \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetCurrentTaskHandleImpl             \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGetCurrentTaskHandle_Unpriv              \n"
+                " MPU_xTaskGetCurrentTaskHandle_Priv:                   \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGetCurrentTaskHandleImpl               \n"
+                " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetCurrentTaskHandleImpl              \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
+    #endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_xTaskGetSchedulerState == 1 )
+    #if ( INCLUDE_xTaskGetSchedulerState == 1 )
 
-BaseType_t MPU_xTaskGetSchedulerState( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGetSchedulerState( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGetSchedulerState( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetSchedulerStateImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGetSchedulerState_Unpriv                 \n"
-        " MPU_xTaskGetSchedulerState_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGetSchedulerStateImpl                  \n"
-        " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetSchedulerStateImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGetSchedulerState( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetSchedulerStateImpl                \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGetSchedulerState_Unpriv                 \n"
+                " MPU_xTaskGetSchedulerState_Priv:                      \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGetSchedulerStateImpl                  \n"
+                " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetSchedulerStateImpl                 \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */
+    #endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */
 /*-----------------------------------------------------------*/
 
-void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSetTimeOutStateImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskSetTimeOutState_Unpriv                   \n"
-        " MPU_vTaskSetTimeOutState_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskSetTimeOutStateImpl                    \n"
-        " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSetTimeOutStateImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_vTaskSetTimeOutStateImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_vTaskSetTimeOutState_Unpriv                   \n"
+            " MPU_vTaskSetTimeOutState_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_vTaskSetTimeOutStateImpl                    \n"
+            " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_vTaskSetTimeOutStateImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
-                                     TickType_t * const pxTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
+                                         TickType_t * const pxTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
-                                     TickType_t * const pxTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskCheckForTimeOutImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskCheckForTimeOut_Unpriv                   \n"
-        " MPU_xTaskCheckForTimeOut_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskCheckForTimeOutImpl                    \n"
-        " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskCheckForTimeOutImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
+                                         TickType_t * const pxTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xTaskCheckForTimeOutImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xTaskCheckForTimeOut_Unpriv                   \n"
+            " MPU_xTaskCheckForTimeOut_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xTaskCheckForTimeOutImpl                    \n"
+            " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xTaskCheckForTimeOutImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                   UBaseType_t uxIndexToNotify,
-                                   uint32_t ulValue,
-                                   eNotifyAction eAction,
-                                   uint32_t * pulPreviousNotificationValue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
+                                           UBaseType_t uxIndexToNotify,
+                                           uint32_t ulValue,
+                                           eNotifyAction eAction,
+                                           uint32_t * pulPreviousNotificationValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                   UBaseType_t uxIndexToNotify,
-                                   uint32_t ulValue,
-                                   eNotifyAction eAction,
-                                   uint32_t * pulPreviousNotificationValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGenericNotifyImpl                    \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGenericNotify_Unpriv                     \n"
-        " MPU_xTaskGenericNotify_Priv:                          \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGenericNotifyImpl                      \n"
-        " MPU_xTaskGenericNotify_Unpriv:                        \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGenericNotifyImpl                     \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
+                                           UBaseType_t uxIndexToNotify,
+                                           uint32_t ulValue,
+                                           eNotifyAction eAction,
+                                           uint32_t * pulPreviousNotificationValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGenericNotifyImpl                    \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGenericNotify_Unpriv                     \n"
+                " MPU_xTaskGenericNotify_Priv:                          \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGenericNotifyImpl                      \n"
+                " MPU_xTaskGenericNotify_Unpriv:                        \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGenericNotifyImpl                     \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                       uint32_t ulBitsToClearOnEntry,
-                                       uint32_t ulBitsToClearOnExit,
-                                       uint32_t * pulNotificationValue,
-                                       TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
+                                               uint32_t ulBitsToClearOnEntry,
+                                               uint32_t ulBitsToClearOnExit,
+                                               uint32_t * pulNotificationValue,
+                                               TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                       uint32_t ulBitsToClearOnEntry,
-                                       uint32_t ulBitsToClearOnExit,
-                                       uint32_t * pulNotificationValue,
-                                       TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGenericNotifyWaitImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGenericNotifyWait_Unpriv                 \n"
-        " MPU_xTaskGenericNotifyWait_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGenericNotifyWaitImpl                  \n"
-        " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGenericNotifyWaitImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
+                                               uint32_t ulBitsToClearOnEntry,
+                                               uint32_t ulBitsToClearOnExit,
+                                               uint32_t * pulNotificationValue,
+                                               TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGenericNotifyWaitImpl                \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGenericNotifyWait_Unpriv                 \n"
+                " MPU_xTaskGenericNotifyWait_Priv:                      \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGenericNotifyWaitImpl                  \n"
+                " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGenericNotifyWaitImpl                 \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
-                                      BaseType_t xClearCountOnExit,
-                                      TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
+                                              BaseType_t xClearCountOnExit,
+                                              TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
-                                      BaseType_t xClearCountOnExit,
-                                      TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGenericNotifyTakeImpl               \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGenericNotifyTake_Unpriv                \n"
-        " MPU_ulTaskGenericNotifyTake_Priv:                     \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGenericNotifyTakeImpl                 \n"
-        " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGenericNotifyTakeImpl                \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
+                                              BaseType_t xClearCountOnExit,
+                                              TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGenericNotifyTakeImpl               \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGenericNotifyTake_Unpriv                \n"
+                " MPU_ulTaskGenericNotifyTake_Priv:                     \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGenericNotifyTakeImpl                 \n"
+                " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGenericNotifyTakeImpl                \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
-                                             UBaseType_t uxIndexToClear ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
+                                                     UBaseType_t uxIndexToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
-                                             UBaseType_t uxIndexToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGenericNotifyStateClearImpl          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGenericNotifyStateClear_Unpriv           \n"
-        " MPU_xTaskGenericNotifyStateClear_Priv:                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGenericNotifyStateClearImpl            \n"
-        " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGenericNotifyStateClearImpl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
+                                                     UBaseType_t uxIndexToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGenericNotifyStateClearImpl          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGenericNotifyStateClear_Unpriv           \n"
+                " MPU_xTaskGenericNotifyStateClear_Priv:                \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGenericNotifyStateClearImpl            \n"
+                " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGenericNotifyStateClearImpl           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
-                                            UBaseType_t uxIndexToClear,
-                                            uint32_t ulBitsToClear ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
+                                                    UBaseType_t uxIndexToClear,
+                                                    uint32_t ulBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
-                                            UBaseType_t uxIndexToClear,
-                                            uint32_t ulBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGenericNotifyValueClearImpl         \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGenericNotifyValueClear_Unpriv          \n"
-        " MPU_ulTaskGenericNotifyValueClear_Priv:               \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGenericNotifyValueClearImpl           \n"
-        " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGenericNotifyValueClearImpl          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
+                                                    UBaseType_t uxIndexToClear,
+                                                    uint32_t ulBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGenericNotifyValueClearImpl         \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGenericNotifyValueClear_Unpriv          \n"
+                " MPU_ulTaskGenericNotifyValueClear_Priv:               \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGenericNotifyValueClearImpl           \n"
+                " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGenericNotifyValueClearImpl          \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
-                                  const void * const pvItemToQueue,
-                                  TickType_t xTicksToWait,
-                                  const BaseType_t xCopyPosition ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
+                                      const void * const pvItemToQueue,
+                                      TickType_t xTicksToWait,
+                                      const BaseType_t xCopyPosition ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
-                                  const void * const pvItemToQueue,
-                                  TickType_t xTicksToWait,
-                                  const BaseType_t xCopyPosition ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueGenericSendImpl                     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueGenericSend_Unpriv                      \n"
-        " MPU_xQueueGenericSend_Priv:                           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueGenericSendImpl                       \n"
-        " MPU_xQueueGenericSend_Unpriv:                         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueGenericSendImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
+                                      const void * const pvItemToQueue,
+                                      TickType_t xTicksToWait,
+                                      const BaseType_t xCopyPosition ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueueGenericSendImpl                     \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xQueueGenericSend_Unpriv                      \n"
+            " MPU_xQueueGenericSend_Priv:                           \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xQueueGenericSendImpl                       \n"
+            " MPU_xQueueGenericSend_Unpriv:                         \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueueGenericSendImpl                      \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxQueueMessagesWaitingImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxQueueMessagesWaiting_Unpriv                 \n"
-        " MPU_uxQueueMessagesWaiting_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxQueueMessagesWaitingImpl                  \n"
-        " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxQueueMessagesWaitingImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_uxQueueMessagesWaitingImpl                \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_uxQueueMessagesWaiting_Unpriv                 \n"
+            " MPU_uxQueueMessagesWaiting_Priv:                      \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_uxQueueMessagesWaitingImpl                  \n"
+            " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_uxQueueMessagesWaitingImpl                 \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxQueueSpacesAvailableImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxQueueSpacesAvailable_Unpriv                 \n"
-        " MPU_uxQueueSpacesAvailable_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxQueueSpacesAvailableImpl                  \n"
-        " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxQueueSpacesAvailableImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_uxQueueSpacesAvailableImpl                \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_uxQueueSpacesAvailable_Unpriv                 \n"
+            " MPU_uxQueueSpacesAvailable_Priv:                      \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_uxQueueSpacesAvailableImpl                  \n"
+            " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_uxQueueSpacesAvailableImpl                 \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
-                              void * const pvBuffer,
-                              TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
+                                  void * const pvBuffer,
+                                  TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
-                              void * const pvBuffer,
-                              TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueReceiveImpl                         \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueReceive_Unpriv                          \n"
-        " MPU_xQueueReceive_Priv:                               \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueReceiveImpl                           \n"
-        " MPU_xQueueReceive_Unpriv:                             \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueReceiveImpl                          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
+                                  void * const pvBuffer,
+                                  TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueueReceiveImpl                         \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xQueueReceive_Unpriv                          \n"
+            " MPU_xQueueReceive_Priv:                               \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xQueueReceiveImpl                           \n"
+            " MPU_xQueueReceive_Unpriv:                             \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueueReceiveImpl                          \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
-                           void * const pvBuffer,
-                           TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
+                               void * const pvBuffer,
+                               TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
-                           void * const pvBuffer,
-                           TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueuePeekImpl                            \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueuePeek_Unpriv                             \n"
-        " MPU_xQueuePeek_Priv:                                  \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueuePeekImpl                              \n"
-        " MPU_xQueuePeek_Unpriv:                                \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueuePeekImpl                             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
+                               void * const pvBuffer,
+                               TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueuePeekImpl                            \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xQueuePeek_Unpriv                             \n"
+            " MPU_xQueuePeek_Priv:                                  \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xQueuePeekImpl                              \n"
+            " MPU_xQueuePeek_Unpriv:                                \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueuePeekImpl                             \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
-                                    TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
+                                        TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
-                                    TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueSemaphoreTakeImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueSemaphoreTake_Unpriv                    \n"
-        " MPU_xQueueSemaphoreTake_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueSemaphoreTakeImpl                     \n"
-        " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueSemaphoreTakeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
+                                        TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueueSemaphoreTakeImpl                   \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xQueueSemaphoreTake_Unpriv                    \n"
+            " MPU_xQueueSemaphoreTake_Priv:                         \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xQueueSemaphoreTakeImpl                     \n"
+            " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueueSemaphoreTakeImpl                    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+    #if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
 
-TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueGetMutexHolderImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueGetMutexHolder_Unpriv                   \n"
-        " MPU_xQueueGetMutexHolder_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueGetMutexHolderImpl                    \n"
-        " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueGetMutexHolderImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueGetMutexHolderImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueGetMutexHolder_Unpriv                   \n"
+                " MPU_xQueueGetMutexHolder_Priv:                        \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueGetMutexHolderImpl                    \n"
+                " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueGetMutexHolderImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */
+    #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+    #if ( configUSE_RECURSIVE_MUTEXES == 1 )
 
-BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
-                                         TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+                                                 TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+        BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+                                                 TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueTakeMutexRecursiveImpl              \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueTakeMutexRecursive_Unpriv               \n"
+                " MPU_xQueueTakeMutexRecursive_Priv:                    \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueTakeMutexRecursiveImpl                \n"
+                " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueTakeMutexRecursiveImpl               \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_RECURSIVE_MUTEXES == 1 )
+
+        BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueGiveMutexRecursiveImpl              \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueGiveMutexRecursive_Unpriv               \n"
+                " MPU_xQueueGiveMutexRecursive_Priv:                    \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueGiveMutexRecursiveImpl                \n"
+                " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueGiveMutexRecursiveImpl               \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_QUEUE_SETS == 1 )
+
+        QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
+                                                        const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
+                                                        const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueSelectFromSetImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueSelectFromSet_Unpriv                    \n"
+                " MPU_xQueueSelectFromSet_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueSelectFromSetImpl                     \n"
+                " MPU_xQueueSelectFromSet_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueSelectFromSetImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_QUEUE_SETS == 1 )
+
+        BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                                       QueueSetHandle_t xQueueSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                                       QueueSetHandle_t xQueueSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueAddToSetImpl                        \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueAddToSet_Unpriv                         \n"
+                " MPU_xQueueAddToSet_Priv:                              \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueAddToSetImpl                          \n"
+                " MPU_xQueueAddToSet_Unpriv:                            \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueAddToSetImpl                         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+        void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
+                                      const char * pcName ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
+                                      const char * pcName ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vQueueAddToRegistryImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vQueueAddToRegistry_Unpriv                    \n"
+                " MPU_vQueueAddToRegistry_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vQueueAddToRegistryImpl                     \n"
+                " MPU_vQueueAddToRegistry_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vQueueAddToRegistryImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+        void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vQueueUnregisterQueueImpl                 \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vQueueUnregisterQueue_Unpriv                  \n"
+                " MPU_vQueueUnregisterQueue_Priv:                       \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vQueueUnregisterQueueImpl                   \n"
+                " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vQueueUnregisterQueueImpl                  \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+        const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pcQueueGetNameImpl                        \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_pcQueueGetName_Unpriv                         \n"
+                " MPU_pcQueueGetName_Priv:                              \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_pcQueueGetNameImpl                          \n"
+                " MPU_pcQueueGetName_Unpriv:                            \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pcQueueGetNameImpl                         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pvTimerGetTimerIDImpl                     \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_pvTimerGetTimerID_Unpriv                      \n"
+                " MPU_pvTimerGetTimerID_Priv:                           \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_pvTimerGetTimerIDImpl                       \n"
+                " MPU_pvTimerGetTimerID_Unpriv:                         \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pvTimerGetTimerIDImpl                      \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
+                                   void * pvNewID ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
+                                   void * pvNewID ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTimerSetTimerIDImpl                      \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTimerSetTimerID_Unpriv                       \n"
+                " MPU_vTimerSetTimerID_Priv:                            \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTimerSetTimerIDImpl                        \n"
+                " MPU_vTimerSetTimerID_Unpriv:                          \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTimerSetTimerIDImpl                       \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerIsTimerActiveImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerIsTimerActive_Unpriv                    \n"
+                " MPU_xTimerIsTimerActive_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerIsTimerActiveImpl                     \n"
+                " MPU_xTimerIsTimerActive_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerIsTimerActiveImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetTimerDaemonTaskHandleImpl        \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv         \n"
+                " MPU_xTimerGetTimerDaemonTaskHandle_Priv:              \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerGetTimerDaemonTaskHandleImpl          \n"
+                " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetTimerDaemonTaskHandleImpl         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                                     const BaseType_t xCommandID,
+                                                     const TickType_t xOptionalValue,
+                                                     BaseType_t * const pxHigherPriorityTaskWoken,
+                                                     const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                                     const BaseType_t xCommandID,
+                                                     const TickType_t xOptionalValue,
+                                                     BaseType_t * const pxHigherPriorityTaskWoken,
+                                                     const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                               \n"
+                " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
+                "                                                               \n"
+                " push {r0}                                                     \n"
+                " mrs r0, control                                               \n"
+                " tst r0, #1                                                    \n"
+                " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
+                " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
+                "     pop {r0}                                                  \n"
+                "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
+                " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
+                "     pop {r0}                                                  \n"
+                "     svc %0                                                    \n"
+                "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
+                "     svc %1                                                    \n"
+                "     bx lr                                                     \n"
+                "                                                               \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pcTimerGetNameImpl                        \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_pcTimerGetName_Unpriv                         \n"
+                " MPU_pcTimerGetName_Priv:                              \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_pcTimerGetNameImpl                          \n"
+                " MPU_pcTimerGetName_Unpriv:                            \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pcTimerGetNameImpl                         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
+                                      const BaseType_t uxAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
+                                      const BaseType_t uxAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTimerSetReloadModeImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTimerSetReloadMode_Unpriv                    \n"
+                " MPU_vTimerSetReloadMode_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTimerSetReloadModeImpl                     \n"
+                " MPU_vTimerSetReloadMode_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTimerSetReloadModeImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetReloadModeImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerGetReloadMode_Unpriv                    \n"
+                " MPU_xTimerGetReloadMode_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerGetReloadModeImpl                     \n"
+                " MPU_xTimerGetReloadMode_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetReloadModeImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTimerGetReloadModeImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTimerGetReloadMode_Unpriv                   \n"
+                " MPU_uxTimerGetReloadMode_Priv:                        \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTimerGetReloadModeImpl                    \n"
+                " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTimerGetReloadModeImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetPeriodImpl                       \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerGetPeriod_Unpriv                        \n"
+                " MPU_xTimerGetPeriod_Priv:                             \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerGetPeriodImpl                         \n"
+                " MPU_xTimerGetPeriod_Unpriv:                           \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetPeriodImpl                        \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetExpiryTimeImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerGetExpiryTime_Unpriv                    \n"
+                " MPU_xTimerGetExpiryTime_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerGetExpiryTimeImpl                     \n"
+                " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetExpiryTimeImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         const BaseType_t xClearOnExit,
+                                         const BaseType_t xWaitForAllBits,
+                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         const BaseType_t xClearOnExit,
+                                         const BaseType_t xWaitForAllBits,
                                          TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueTakeMutexRecursiveImpl              \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueTakeMutexRecursive_Unpriv               \n"
-        " MPU_xQueueTakeMutexRecursive_Priv:                    \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueTakeMutexRecursiveImpl                \n"
-        " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueTakeMutexRecursiveImpl               \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupWaitBitsImpl                   \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
+            " MPU_xEventGroupWaitBits_Priv:                         \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xEventGroupWaitBitsImpl                     \n"
+            " MPU_xEventGroupWaitBits_Unpriv:                       \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupWaitBitsImpl                    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                          const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueGiveMutexRecursiveImpl              \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueGiveMutexRecursive_Unpriv               \n"
-        " MPU_xQueueGiveMutexRecursive_Priv:                    \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueGiveMutexRecursiveImpl                \n"
-        " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueGiveMutexRecursiveImpl               \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                          const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupClearBitsImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xEventGroupClearBits_Unpriv                   \n"
+            " MPU_xEventGroupClearBits_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xEventGroupClearBitsImpl                    \n"
+            " MPU_xEventGroupClearBits_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupClearBitsImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_QUEUE_SETS == 1 )
+    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                        const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
-                                                const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
-                                                const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueSelectFromSetImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueSelectFromSet_Unpriv                    \n"
-        " MPU_xQueueSelectFromSet_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueSelectFromSetImpl                     \n"
-        " MPU_xQueueSelectFromSet_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueSelectFromSetImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                        const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupSetBitsImpl                    \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xEventGroupSetBits_Unpriv                     \n"
+            " MPU_xEventGroupSetBits_Priv:                          \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xEventGroupSetBitsImpl                      \n"
+            " MPU_xEventGroupSetBits_Unpriv:                        \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupSetBitsImpl                     \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_QUEUE_SETS == 1 )
-
-BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
-                               QueueSetHandle_t xQueueSet ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
-                               QueueSetHandle_t xQueueSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueAddToSetImpl                        \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueAddToSet_Unpriv                         \n"
-        " MPU_xQueueAddToSet_Priv:                              \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueAddToSetImpl                          \n"
-        " MPU_xQueueAddToSet_Unpriv:                            \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueAddToSetImpl                         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_QUEUE_SETS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
-                              const char * pcName ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
-                              const char * pcName ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vQueueAddToRegistryImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vQueueAddToRegistry_Unpriv                    \n"
-        " MPU_vQueueAddToRegistry_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vQueueAddToRegistryImpl                     \n"
-        " MPU_vQueueAddToRegistry_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vQueueAddToRegistryImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vQueueUnregisterQueueImpl                 \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vQueueUnregisterQueue_Unpriv                  \n"
-        " MPU_vQueueUnregisterQueue_Priv:                       \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vQueueUnregisterQueueImpl                   \n"
-        " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vQueueUnregisterQueueImpl                  \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pcQueueGetNameImpl                        \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_pcQueueGetName_Unpriv                         \n"
-        " MPU_pcQueueGetName_Priv:                              \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_pcQueueGetNameImpl                          \n"
-        " MPU_pcQueueGetName_Unpriv:                            \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pcQueueGetNameImpl                         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pvTimerGetTimerIDImpl                     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_pvTimerGetTimerID_Unpriv                      \n"
-        " MPU_pvTimerGetTimerID_Priv:                           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_pvTimerGetTimerIDImpl                       \n"
-        " MPU_pvTimerGetTimerID_Unpriv:                         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pvTimerGetTimerIDImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
-                           void * pvNewID ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
-                           void * pvNewID ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTimerSetTimerIDImpl                      \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTimerSetTimerID_Unpriv                       \n"
-        " MPU_vTimerSetTimerID_Priv:                            \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTimerSetTimerIDImpl                        \n"
-        " MPU_vTimerSetTimerID_Unpriv:                          \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTimerSetTimerIDImpl                       \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerIsTimerActiveImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTimerIsTimerActive_Unpriv                    \n"
-        " MPU_xTimerIsTimerActive_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerIsTimerActiveImpl                     \n"
-        " MPU_xTimerIsTimerActive_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerIsTimerActiveImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetTimerDaemonTaskHandleImpl        \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv         \n"
-        " MPU_xTimerGetTimerDaemonTaskHandle_Priv:              \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerGetTimerDaemonTaskHandleImpl          \n"
-        " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetTimerDaemonTaskHandleImpl         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                             const BaseType_t xCommandID,
-                                             const TickType_t xOptionalValue,
-                                             BaseType_t * const pxHigherPriorityTaskWoken,
-                                             const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                             const BaseType_t xCommandID,
-                                             const TickType_t xOptionalValue,
-                                             BaseType_t * const pxHigherPriorityTaskWoken,
-                                             const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                               \n"
-        " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
-        "                                                               \n"
-        " push {r0}                                                     \n"
-        " mrs r0, control                                               \n"
-        " tst r0, #1                                                    \n"
-        " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
-        " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
-        "     pop {r0}                                                  \n"
-        "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
-        " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
-        "     pop {r0}                                                  \n"
-        "     svc %0                                                    \n"
-        "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
-        "     svc %1                                                    \n"
-        "     bx lr                                                     \n"
-        "                                                               \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pcTimerGetNameImpl                        \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_pcTimerGetName_Unpriv                         \n"
-        " MPU_pcTimerGetName_Priv:                              \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_pcTimerGetNameImpl                          \n"
-        " MPU_pcTimerGetName_Unpriv:                            \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pcTimerGetNameImpl                         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                              const BaseType_t uxAutoReload ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                              const BaseType_t uxAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTimerSetReloadModeImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTimerSetReloadMode_Unpriv                    \n"
-        " MPU_vTimerSetReloadMode_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTimerSetReloadModeImpl                     \n"
-        " MPU_vTimerSetReloadMode_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTimerSetReloadModeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetReloadModeImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTimerGetReloadMode_Unpriv                    \n"
-        " MPU_xTimerGetReloadMode_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerGetReloadModeImpl                     \n"
-        " MPU_xTimerGetReloadMode_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetReloadModeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTimerGetReloadModeImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTimerGetReloadMode_Unpriv                   \n"
-        " MPU_uxTimerGetReloadMode_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTimerGetReloadModeImpl                    \n"
-        " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTimerGetReloadModeImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetPeriodImpl                       \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTimerGetPeriod_Unpriv                        \n"
-        " MPU_xTimerGetPeriod_Priv:                             \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerGetPeriodImpl                         \n"
-        " MPU_xTimerGetPeriod_Unpriv:                           \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetPeriodImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetExpiryTimeImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTimerGetExpiryTime_Unpriv                    \n"
-        " MPU_xTimerGetExpiryTime_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerGetExpiryTimeImpl                     \n"
-        " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetExpiryTimeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                     const EventBits_t uxBitsToSet,
                                      const EventBits_t uxBitsToWaitFor,
-                                     const BaseType_t xClearOnExit,
-                                     const BaseType_t xWaitForAllBits,
-                                     TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                     const EventBits_t uxBitsToSet,
                                      const EventBits_t uxBitsToWaitFor,
-                                     const BaseType_t xClearOnExit,
-                                     const BaseType_t xWaitForAllBits,
                                      TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupWaitBitsImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
-        " MPU_xEventGroupWaitBits_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xEventGroupWaitBitsImpl                     \n"
-        " MPU_xEventGroupWaitBits_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupWaitBitsImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupSyncImpl                       \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xEventGroupSync_Unpriv                        \n"
+            " MPU_xEventGroupSync_Priv:                             \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xEventGroupSyncImpl                         \n"
+            " MPU_xEventGroupSync_Unpriv:                           \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupSyncImpl                        \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                      const EventBits_t uxBitsToClear ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                      const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupClearBitsImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xEventGroupClearBits_Unpriv                   \n"
-        " MPU_xEventGroupClearBits_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xEventGroupClearBitsImpl                    \n"
-        " MPU_xEventGroupClearBits_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupClearBitsImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxEventGroupGetNumberImpl                 \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxEventGroupGetNumber_Unpriv                  \n"
+                " MPU_uxEventGroupGetNumber_Priv:                       \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxEventGroupGetNumberImpl                   \n"
+                " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxEventGroupGetNumberImpl                  \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
 /*-----------------------------------------------------------*/
 
-EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                    const EventBits_t uxBitsToSet ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                    const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupSetBitsImpl                    \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xEventGroupSetBits_Unpriv                     \n"
-        " MPU_xEventGroupSetBits_Priv:                          \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xEventGroupSetBitsImpl                      \n"
-        " MPU_xEventGroupSetBits_Unpriv:                        \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupSetBitsImpl                     \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vEventGroupSetNumber( void * xEventGroup,
+                                       UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vEventGroupSetNumber( void * xEventGroup,
+                                       UBaseType_t uxEventGroupNumber ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vEventGroupSetNumberImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vEventGroupSetNumber_Unpriv                   \n"
+                " MPU_vEventGroupSetNumber_Priv:                        \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vEventGroupSetNumberImpl                    \n"
+                " MPU_vEventGroupSetNumber_Unpriv:                      \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vEventGroupSetNumberImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
 /*-----------------------------------------------------------*/
 
-EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                 const EventBits_t uxBitsToSet,
-                                 const EventBits_t uxBitsToWaitFor,
-                                 TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                  const void * pvTxData,
+                                  size_t xDataLengthBytes,
+                                  TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                 const EventBits_t uxBitsToSet,
-                                 const EventBits_t uxBitsToWaitFor,
-                                 TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupSyncImpl                       \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xEventGroupSync_Unpriv                        \n"
-        " MPU_xEventGroupSync_Priv:                             \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xEventGroupSyncImpl                         \n"
-        " MPU_xEventGroupSync_Unpriv:                           \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupSyncImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                  const void * pvTxData,
+                                  size_t xDataLengthBytes,
+                                  TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferSendImpl                     \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferSend_Unpriv                      \n"
+            " MPU_xStreamBufferSend_Priv:                           \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferSendImpl                       \n"
+            " MPU_xStreamBufferSend_Unpriv:                         \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferSendImpl                      \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                     void * pvRxData,
+                                     size_t xBufferLengthBytes,
+                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxEventGroupGetNumberImpl                 \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxEventGroupGetNumber_Unpriv                  \n"
-        " MPU_uxEventGroupGetNumber_Priv:                       \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxEventGroupGetNumberImpl                   \n"
-        " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxEventGroupGetNumberImpl                  \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                     void * pvRxData,
+                                     size_t xBufferLengthBytes,
+                                     TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferReceiveImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferReceive_Unpriv                   \n"
+            " MPU_xStreamBufferReceive_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferReceiveImpl                    \n"
+            " MPU_xStreamBufferReceive_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferReceiveImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vEventGroupSetNumber( void * xEventGroup,
-                               UBaseType_t uxEventGroupNumber ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vEventGroupSetNumber( void * xEventGroup,
-                               UBaseType_t uxEventGroupNumber ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vEventGroupSetNumberImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vEventGroupSetNumber_Unpriv                   \n"
-        " MPU_vEventGroupSetNumber_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vEventGroupSetNumberImpl                    \n"
-        " MPU_vEventGroupSetNumber_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vEventGroupSetNumberImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferIsFullImpl                   \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
+            " MPU_xStreamBufferIsFull_Priv:                         \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferIsFullImpl                     \n"
+            " MPU_xStreamBufferIsFull_Unpriv:                       \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferIsFullImpl                    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                              const void * pvTxData,
-                              size_t xDataLengthBytes,
-                              TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                              const void * pvTxData,
-                              size_t xDataLengthBytes,
-                              TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferSendImpl                     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferSend_Unpriv                      \n"
-        " MPU_xStreamBufferSend_Priv:                           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferSendImpl                       \n"
-        " MPU_xStreamBufferSend_Unpriv:                         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferSendImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
+            " MPU_xStreamBufferIsEmpty_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferIsEmptyImpl                    \n"
+            " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferIsEmptyImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                 void * pvRxData,
-                                 size_t xBufferLengthBytes,
-                                 TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                 void * pvRxData,
-                                 size_t xBufferLengthBytes,
-                                 TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferReceiveImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferReceive_Unpriv                   \n"
-        " MPU_xStreamBufferReceive_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferReceiveImpl                    \n"
-        " MPU_xStreamBufferReceive_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferReceiveImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
+            " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
+            " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferSpacesAvailableImpl           \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferIsFullImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
-        " MPU_xStreamBufferIsFull_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferIsFullImpl                     \n"
-        " MPU_xStreamBufferIsFull_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferIsFullImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
+            " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferBytesAvailableImpl             \n"
+            " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferBytesAvailableImpl            \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                 size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
-        " MPU_xStreamBufferIsEmpty_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferIsEmptyImpl                    \n"
-        " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferIsEmptyImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                 size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
+            " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
+            " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferSetTriggerLevelImpl           \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
-        " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
-        " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferSpacesAvailableImpl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
-size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
-        " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferBytesAvailableImpl             \n"
-        " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferBytesAvailableImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                             size_t xTriggerLevel ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                             size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
-        " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
-        " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferSetTriggerLevelImpl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
-size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
-        " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
-        " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferNextMessageLengthBytesImpl    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
+            " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
+            " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferNextMessageLengthBytesImpl    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c
index f7ec7d9c0..ba8f6c62d 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c
@@ -42,116 +42,116 @@
 
 #if ( configENABLE_MPU == 1 )
 
-void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        " .syntax unified                                 \n"
-        "                                                 \n"
-        " program_mpu_first_task:                         \n"
-        "    ldr r3, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB. */
-        "                                                 \n"
-        "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-        "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
-        "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
-        "    str r2, [r1]                                 \n" /* Disable MPU. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
-        "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-        "    ldr r2, xMAIR0Const2                         \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-        "    str r1, [r2]                                 \n" /* Program MAIR0. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-        "    ldr r1, xRNRConst2                           \n" /* r1 = 0xe000ed98 [Location of RNR]. */
-        "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "                                                 \n"
-        "    movs r3, #4                                  \n" /* r3 = 4. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 4. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-        "                                                 \n"
-        #if ( configTOTAL_MPU_REGIONS == 16 )
-        "    movs r3, #8                                  \n" /* r3 = 8. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 8. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-        "    movs r3, #12                                 \n" /* r3 = 12. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 12. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-        #endif /* configTOTAL_MPU_REGIONS == 16 */
-        "                                                 \n"
-        "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
-        "    orr r2, #1                                   \n" /* r2 = r1 | 1 i.e. Set the bit 0 in r2. */
-        "    str r2, [r1]                                 \n" /* Enable MPU. */
-        "    dsb                                          \n" /* Force memory writes before continuing. */
-        "                                                 \n"
-        " restore_context_first_task:                     \n"
-        "    ldr r3, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r1, [r3]                                 \n" /* r1 = pxCurrentTCB.*/
-        "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
-        "                                                 \n"
-        " restore_special_regs_first_task:                \n"
-        "    ldmdb r2!, {r0, r3-r5, lr}                   \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
-        "    msr psp, r3                                  \n"
-        "    msr psplim, r4                               \n"
-        "    msr control, r5                              \n"
-        "    ldr r4, xSecureContextConst2                 \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-        "    str r0, [r4]                                 \n" /* Restore xSecureContext. */
-        "                                                 \n"
-        " restore_general_regs_first_task:                \n"
-        "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
-        "    stmia r3!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
-        "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 restored. */
-        "                                                 \n"
-        " restore_context_done_first_task:                \n"
-        "    str r2, [r1]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
-        "    mov r0, #0                                   \n"
-        "    msr basepri, r0                              \n" /* Ensure that interrupts are enabled when the first task starts. */
-        "    bx lr                                        \n"
-        "                                                 \n"
-        " .align 4                                        \n"
-        " pxCurrentTCBConst2: .word pxCurrentTCB          \n"
-        " xSecureContextConst2: .word xSecureContext      \n"
-        " xMPUCTRLConst2: .word 0xe000ed94                \n"
-        " xMAIR0Const2: .word 0xe000edc0                  \n"
-        " xRNRConst2: .word 0xe000ed98                    \n"
-        " xRBARConst2: .word 0xe000ed9c                   \n"
-    );
-}
+    void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                 \n"
+            "                                                 \n"
+            " program_mpu_first_task:                         \n"
+            "    ldr r3, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB. */
+            "                                                 \n"
+            "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
+            "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
+            "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
+            "    str r2, [r1]                                 \n" /* Disable MPU. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
+            "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
+            "    ldr r2, xMAIR0Const2                         \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    str r1, [r2]                                 \n" /* Program MAIR0. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
+            "    ldr r1, xRNRConst2                           \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "                                                 \n"
+            "    movs r3, #4                                  \n" /* r3 = 4. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 4. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "                                                 \n"
+            #if ( configTOTAL_MPU_REGIONS == 16 )
+                "    movs r3, #8                                  \n" /* r3 = 8. */
+                "    str r3, [r1]                                 \n" /* Program RNR = 8. */
+                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
+                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+                "    movs r3, #12                                 \n" /* r3 = 12. */
+                "    str r3, [r1]                                 \n" /* Program RNR = 12. */
+                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
+                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            #endif /* configTOTAL_MPU_REGIONS == 16 */
+            "                                                 \n"
+            "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
+            "    orr r2, #1                                   \n" /* r2 = r1 | 1 i.e. Set the bit 0 in r2. */
+            "    str r2, [r1]                                 \n" /* Enable MPU. */
+            "    dsb                                          \n" /* Force memory writes before continuing. */
+            "                                                 \n"
+            " restore_context_first_task:                     \n"
+            "    ldr r3, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r1, [r3]                                 \n" /* r1 = pxCurrentTCB.*/
+            "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
+            "                                                 \n"
+            " restore_special_regs_first_task:                \n"
+            "    ldmdb r2!, {r0, r3-r5, lr}                   \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
+            "    msr psp, r3                                  \n"
+            "    msr psplim, r4                               \n"
+            "    msr control, r5                              \n"
+            "    ldr r4, xSecureContextConst2                 \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "    str r0, [r4]                                 \n" /* Restore xSecureContext. */
+            "                                                 \n"
+            " restore_general_regs_first_task:                \n"
+            "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
+            "    stmia r3!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
+            "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 restored. */
+            "                                                 \n"
+            " restore_context_done_first_task:                \n"
+            "    str r2, [r1]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
+            "    mov r0, #0                                   \n"
+            "    msr basepri, r0                              \n" /* Ensure that interrupts are enabled when the first task starts. */
+            "    bx lr                                        \n"
+            "                                                 \n"
+            " .align 4                                        \n"
+            " pxCurrentTCBConst2: .word pxCurrentTCB          \n"
+            " xSecureContextConst2: .word xSecureContext      \n"
+            " xMPUCTRLConst2: .word 0xe000ed94                \n"
+            " xMAIR0Const2: .word 0xe000edc0                  \n"
+            " xRNRConst2: .word 0xe000ed98                    \n"
+            " xRBARConst2: .word 0xe000ed9c                   \n"
+        );
+    }
 
 #else /* configENABLE_MPU */
 
-void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "   .syntax unified                                 \n"
-        "                                                   \n"
-        "   ldr  r2, pxCurrentTCBConst2                     \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr  r3, [r2]                                   \n" /* Read pxCurrentTCB. */
-        "   ldr  r0, [r3]                                   \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
-        "                                                   \n"
-        "   ldm  r0!, {r1-r3}                               \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
-        "   ldr  r4, xSecureContextConst2                   \n"
-        "   str  r1, [r4]                                   \n" /* Set xSecureContext to this task's value for the same. */
-        "   msr  psplim, r2                                 \n" /* Set this task's PSPLIM value. */
-        "   movs r1, #2                                     \n" /* r1 = 2. */
-        "   msr  CONTROL, r1                                \n" /* Switch to use PSP in the thread mode. */
-        "   adds r0, #32                                    \n" /* Discard everything up to r0. */
-        "   msr  psp, r0                                    \n" /* This is now the new top of stack to use in the task. */
-        "   isb                                             \n"
-        "   mov  r0, #0                                     \n"
-        "   msr  basepri, r0                                \n" /* Ensure that interrupts are enabled when the first task starts. */
-        "   bx   r3                                         \n" /* Finally, branch to EXC_RETURN. */
-        "   .align 4                                        \n"
-        "pxCurrentTCBConst2: .word pxCurrentTCB             \n"
-        "xSecureContextConst2: .word xSecureContext         \n"
-    );
-}
+    void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            "   .syntax unified                                 \n"
+            "                                                   \n"
+            "   ldr  r2, pxCurrentTCBConst2                     \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr  r3, [r2]                                   \n" /* Read pxCurrentTCB. */
+            "   ldr  r0, [r3]                                   \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+            "                                                   \n"
+            "   ldm  r0!, {r1-r3}                               \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
+            "   ldr  r4, xSecureContextConst2                   \n"
+            "   str  r1, [r4]                                   \n" /* Set xSecureContext to this task's value for the same. */
+            "   msr  psplim, r2                                 \n" /* Set this task's PSPLIM value. */
+            "   movs r1, #2                                     \n" /* r1 = 2. */
+            "   msr  CONTROL, r1                                \n" /* Switch to use PSP in the thread mode. */
+            "   adds r0, #32                                    \n" /* Discard everything up to r0. */
+            "   msr  psp, r0                                    \n" /* This is now the new top of stack to use in the task. */
+            "   isb                                             \n"
+            "   mov  r0, #0                                     \n"
+            "   msr  basepri, r0                                \n" /* Ensure that interrupts are enabled when the first task starts. */
+            "   bx   r3                                         \n" /* Finally, branch to EXC_RETURN. */
+            "   .align 4                                        \n"
+            "pxCurrentTCBConst2: .word pxCurrentTCB             \n"
+            "xSecureContextConst2: .word xSecureContext         \n"
+        );
+    }
 
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
@@ -162,12 +162,12 @@ BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs r0, control                                 \n"/* r0 = CONTROL. */
-        "   tst r0, #1                                      \n"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+        "   mrs r0, control                                 \n" /* r0 = CONTROL. */
+        "   tst r0, #1                                      \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
         "   ite ne                                          \n"
-        "   movne r0, #0                                    \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
-        "   moveq r0, #1                                    \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
-        "   bx lr                                           \n"/* Return. */
+        "   movne r0, #0                                    \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+        "   moveq r0, #1                                    \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+        "   bx lr                                           \n" /* Return. */
         "                                                   \n"
         "   .align 4                                        \n"
         ::: "r0", "memory"
@@ -181,10 +181,10 @@ void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs r0, control                                 \n"/* Read the CONTROL register. */
-        "   bic r0, #1                                      \n"/* Clear the bit 0. */
-        "   msr control, r0                                 \n"/* Write back the new CONTROL value. */
-        "   bx lr                                           \n"/* Return to the caller. */
+        "   mrs r0, control                                 \n" /* Read the CONTROL register. */
+        "   bic r0, #1                                      \n" /* Clear the bit 0. */
+        "   msr control, r0                                 \n" /* Write back the new CONTROL value. */
+        "   bx lr                                           \n" /* Return to the caller. */
         ::: "r0", "memory"
     );
 }
@@ -196,10 +196,10 @@ void vResetPrivilege( void ) /* __attribute__ (( naked )) */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs r0, control                                 \n"/* r0 = CONTROL. */
-        "   orr r0, #1                                      \n"/* r0 = r0 | 1. */
-        "   msr control, r0                                 \n"/* CONTROL = r0. */
-        "   bx lr                                           \n"/* Return to the caller. */
+        "   mrs r0, control                                 \n" /* r0 = CONTROL. */
+        "   orr r0, #1                                      \n" /* r0 = r0 | 1. */
+        "   msr control, r0                                 \n" /* CONTROL = r0. */
+        "   bx lr                                           \n" /* Return to the caller. */
         ::: "r0", "memory"
     );
 }
@@ -211,15 +211,15 @@ void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   ldr r0, xVTORConst                              \n"/* Use the NVIC offset register to locate the stack. */
-        "   ldr r0, [r0]                                    \n"/* Read the VTOR register which gives the address of vector table. */
-        "   ldr r0, [r0]                                    \n"/* The first entry in vector table is stack pointer. */
-        "   msr msp, r0                                     \n"/* Set the MSP back to the start of the stack. */
-        "   cpsie i                                         \n"/* Globally enable interrupts. */
+        "   ldr r0, xVTORConst                              \n" /* Use the NVIC offset register to locate the stack. */
+        "   ldr r0, [r0]                                    \n" /* Read the VTOR register which gives the address of vector table. */
+        "   ldr r0, [r0]                                    \n" /* The first entry in vector table is stack pointer. */
+        "   msr msp, r0                                     \n" /* Set the MSP back to the start of the stack. */
+        "   cpsie i                                         \n" /* Globally enable interrupts. */
         "   cpsie f                                         \n"
         "   dsb                                             \n"
         "   isb                                             \n"
-        "   svc %0                                          \n"/* System call to start the first task. */
+        "   svc %0                                          \n" /* System call to start the first task. */
         "   nop                                             \n"
         "                                                   \n"
         "   .align 4                                        \n"
@@ -235,12 +235,12 @@ uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCT
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs r0, basepri                                 \n"/* r0 = basepri. Return original basepri value. */
-        "   mov r1, %0                                      \n"/* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        "   msr basepri, r1                                 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        "   mrs r0, basepri                                 \n" /* r0 = basepri. Return original basepri value. */
+        "   mov r1, %0                                      \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        "   msr basepri, r1                                 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
         "   dsb                                             \n"
         "   isb                                             \n"
-        "   bx lr                                           \n"/* Return. */
+        "   bx lr                                           \n" /* Return. */
         ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
     );
 }
@@ -252,10 +252,10 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   msr basepri, r0                                 \n"/* basepri = ulMask. */
+        "   msr basepri, r0                                 \n" /* basepri = ulMask. */
         "   dsb                                             \n"
         "   isb                                             \n"
-        "   bx lr                                           \n"/* Return. */
+        "   bx lr                                           \n" /* Return. */
         ::: "memory"
     );
 }
@@ -263,320 +263,320 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
 
 #if ( configENABLE_MPU == 1 )
 
-void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        " .syntax unified                                 \n"
-        " .extern SecureContext_SaveContext               \n"
-        " .extern SecureContext_LoadContext               \n"
-        "                                                 \n"
-        " ldr r3, xSecureContextConst                     \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-        " ldr r0, [r3]                                    \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
-        " ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        " ldr r1, [r3]                                    \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
-        " ldr r2, [r1]                                    \n" /* r2 = Location in TCB where the context should be saved. */
-        "                                                 \n"
-        " cbz r0, save_ns_context                         \n" /* No secure context to save. */
-        " save_s_context:                                 \n"
-        "    push {r0-r2, lr}                             \n"
-        "    bl SecureContext_SaveContext                 \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-        "    pop {r0-r2, lr}                              \n"
-        "                                                 \n"
-        " save_ns_context:                                \n"
-        "    mov r3, lr                                   \n" /* r3 = LR (EXC_RETURN). */
-        "    lsls r3, r3, #25                             \n" /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-        "    bmi save_special_regs                        \n" /* r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
-        "                                                 \n"
-        " save_general_regs:                              \n"
-        "    mrs r3, psp                                  \n"
-        "                                                 \n"
-    #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-        "    add r3, r3, #0x20                            \n" /* Move r3 to location where s0 is saved. */
-        "    tst lr, #0x10                                \n"
-        "    ittt eq                                      \n"
-        "    vstmiaeq r2!, {s16-s31}                      \n" /* Store s16-s31. */
-        "    vldmiaeq r3, {s0-s16}                        \n" /* Copy hardware saved FP context into s0-s16. */
-        "    vstmiaeq r2!, {s0-s16}                       \n" /* Store hardware saved FP context. */
-        "    sub r3, r3, #0x20                            \n" /* Set r3 back to the location of hardware saved context. */
-    #endif /* configENABLE_FPU || configENABLE_MVE */
-        "                                                 \n"
-        "    stmia r2!, {r4-r11}                          \n" /* Store r4-r11. */
-        "    ldmia r3, {r4-r11}                           \n" /* Copy the hardware saved context into r4-r11. */
-        "    stmia r2!, {r4-r11}                          \n" /* Store the hardware saved context. */
-        "                                                 \n"
-        " save_special_regs:                              \n"
-        "    mrs r3, psp                                  \n" /* r3 = PSP. */
-        "    mrs r4, psplim                               \n" /* r4 = PSPLIM. */
-        "    mrs r5, control                              \n" /* r5 = CONTROL. */
-        "    stmia r2!, {r0, r3-r5, lr}                   \n" /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
-        "    str r2, [r1]                                 \n" /* Save the location from where the context should be restored as the first member of TCB. */
-        "                                                 \n"
-        " select_next_task:                               \n"
-        "    mov r0, %0                                   \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
-        "    msr basepri, r0                              \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        "    dsb                                          \n"
-        "    isb                                          \n"
-        "    bl vTaskSwitchContext                        \n"
-        "    mov r0, #0                                   \n" /* r0 = 0. */
-        "    msr basepri, r0                              \n" /* Enable interrupts. */
-        "                                                 \n"
-        " program_mpu:                                    \n"
-        "    ldr r3, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB.*/
-        "                                                 \n"
-        "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-        "    ldr r1, xMPUCTRLConst                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
-        "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
-        "    str r2, [r1]                                 \n" /* Disable MPU. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
-        "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-        "    ldr r2, xMAIR0Const                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-        "    str r1, [r2]                                 \n" /* Program MAIR0. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-        "    ldr r1, xRNRConst                            \n" /* r1 = 0xe000ed98 [Location of RNR]. */
-        "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "                                                 \n"
-        "    movs r3, #4                                  \n" /* r3 = 4. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 4. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-        "                                                 \n"
-        #if ( configTOTAL_MPU_REGIONS == 16 )
-        "    movs r3, #8                                  \n" /* r3 = 8. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 8. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-        "    movs r3, #12                                 \n" /* r3 = 12. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 12. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-        #endif /* configTOTAL_MPU_REGIONS == 16 */
-        "                                                 \n"
-        "   ldr r1, xMPUCTRLConst                         \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
-        "   orr r2, #1                                    \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
-        "   str r2, [r1]                                  \n" /* Enable MPU. */
-        "   dsb                                           \n" /* Force memory writes before continuing. */
-        "                                                 \n"
-        " restore_context:                                \n"
-        "    ldr r3, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r1, [r3]                                 \n" /* r1 = pxCurrentTCB.*/
-        "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
-        "                                                 \n"
-        " restore_special_regs:                           \n"
-        "    ldmdb r2!, {r0, r3-r5, lr}                   \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
-        "    msr psp, r3                                  \n"
-        "    msr psplim, r4                               \n"
-        "    msr control, r5                              \n"
-        "    ldr r4, xSecureContextConst                  \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-        "    str r0, [r4]                                 \n" /* Restore xSecureContext. */
-        "    cbz r0, restore_ns_context                   \n" /* No secure context to restore. */
-        "                                                 \n"
-        " restore_s_context:                              \n"
-        "    push {r1-r3, lr}                             \n"
-        "    bl SecureContext_LoadContext                 \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-        "    pop {r1-r3, lr}                              \n"
-        "                                                 \n"
-        " restore_ns_context:                             \n"
-        "    mov r0, lr                                   \n" /* r0 = LR (EXC_RETURN). */
-        "    lsls r0, r0, #25                             \n" /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-        "    bmi restore_context_done                     \n" /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
-        "                                                 \n"
-        " restore_general_regs:                           \n"
-        "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
-        "    stmia r3!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
-        "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 restored. */
-    #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-        "    tst lr, #0x10                                \n"
-        "    ittt eq                                      \n"
-        "    vldmdbeq r2!, {s0-s16}                       \n" /* s0-s16 contain hardware saved FP context. */
-        "    vstmiaeq r3!, {s0-s16}                       \n" /* Copy hardware saved FP context on the task stack. */
-        "    vldmdbeq r2!, {s16-s31}                      \n" /* Restore s16-s31. */
-    #endif /* configENABLE_FPU || configENABLE_MVE */
-        "                                                 \n"
-        " restore_context_done:                           \n"
-        "    str r2, [r1]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
-        "    bx lr                                        \n"
-        "                                                 \n"
-        " .align 4                                        \n"
-        " pxCurrentTCBConst: .word pxCurrentTCB           \n"
-        " xSecureContextConst: .word xSecureContext       \n"
-        " xMPUCTRLConst: .word 0xe000ed94                 \n"
-        " xMAIR0Const: .word 0xe000edc0                   \n"
-        " xRNRConst: .word 0xe000ed98                     \n"
-        " xRBARConst: .word 0xe000ed9c                    \n"
-        ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
-    );
-}
+    void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                 \n"
+            " .extern SecureContext_SaveContext               \n"
+            " .extern SecureContext_LoadContext               \n"
+            "                                                 \n"
+            " ldr r3, xSecureContextConst                     \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            " ldr r0, [r3]                                    \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+            " ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            " ldr r1, [r3]                                    \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
+            " ldr r2, [r1]                                    \n" /* r2 = Location in TCB where the context should be saved. */
+            "                                                 \n"
+            " cbz r0, save_ns_context                         \n" /* No secure context to save. */
+            " save_s_context:                                 \n"
+            "    push {r0-r2, lr}                             \n"
+            "    bl SecureContext_SaveContext                 \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+            "    pop {r0-r2, lr}                              \n"
+            "                                                 \n"
+            " save_ns_context:                                \n"
+            "    mov r3, lr                                   \n" /* r3 = LR (EXC_RETURN). */
+            "    lsls r3, r3, #25                             \n" /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+            "    bmi save_special_regs                        \n" /* r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
+            "                                                 \n"
+            " save_general_regs:                              \n"
+            "    mrs r3, psp                                  \n"
+            "                                                 \n"
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+                "    add r3, r3, #0x20                            \n" /* Move r3 to location where s0 is saved. */
+                "    tst lr, #0x10                                \n"
+                "    ittt eq                                      \n"
+                "    vstmiaeq r2!, {s16-s31}                      \n" /* Store s16-s31. */
+                "    vldmiaeq r3, {s0-s16}                        \n" /* Copy hardware saved FP context into s0-s16. */
+                "    vstmiaeq r2!, {s0-s16}                       \n" /* Store hardware saved FP context. */
+                "    sub r3, r3, #0x20                            \n" /* Set r3 back to the location of hardware saved context. */
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+            "                                                 \n"
+            "    stmia r2!, {r4-r11}                          \n" /* Store r4-r11. */
+            "    ldmia r3, {r4-r11}                           \n" /* Copy the hardware saved context into r4-r11. */
+            "    stmia r2!, {r4-r11}                          \n" /* Store the hardware saved context. */
+            "                                                 \n"
+            " save_special_regs:                              \n"
+            "    mrs r3, psp                                  \n" /* r3 = PSP. */
+            "    mrs r4, psplim                               \n" /* r4 = PSPLIM. */
+            "    mrs r5, control                              \n" /* r5 = CONTROL. */
+            "    stmia r2!, {r0, r3-r5, lr}                   \n" /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
+            "    str r2, [r1]                                 \n" /* Save the location from where the context should be restored as the first member of TCB. */
+            "                                                 \n"
+            " select_next_task:                               \n"
+            "    mov r0, %0                                   \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
+            "    msr basepri, r0                              \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+            "    dsb                                          \n"
+            "    isb                                          \n"
+            "    bl vTaskSwitchContext                        \n"
+            "    mov r0, #0                                   \n" /* r0 = 0. */
+            "    msr basepri, r0                              \n" /* Enable interrupts. */
+            "                                                 \n"
+            " program_mpu:                                    \n"
+            "    ldr r3, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB.*/
+            "                                                 \n"
+            "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
+            "    ldr r1, xMPUCTRLConst                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
+            "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
+            "    str r2, [r1]                                 \n" /* Disable MPU. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
+            "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
+            "    ldr r2, xMAIR0Const                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    str r1, [r2]                                 \n" /* Program MAIR0. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
+            "    ldr r1, xRNRConst                            \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "                                                 \n"
+            "    movs r3, #4                                  \n" /* r3 = 4. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 4. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "                                                 \n"
+            #if ( configTOTAL_MPU_REGIONS == 16 )
+                "    movs r3, #8                                  \n" /* r3 = 8. */
+                "    str r3, [r1]                                 \n" /* Program RNR = 8. */
+                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+                "    movs r3, #12                                 \n" /* r3 = 12. */
+                "    str r3, [r1]                                 \n" /* Program RNR = 12. */
+                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            #endif /* configTOTAL_MPU_REGIONS == 16 */
+            "                                                 \n"
+            "   ldr r1, xMPUCTRLConst                         \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
+            "   orr r2, #1                                    \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
+            "   str r2, [r1]                                  \n" /* Enable MPU. */
+            "   dsb                                           \n" /* Force memory writes before continuing. */
+            "                                                 \n"
+            " restore_context:                                \n"
+            "    ldr r3, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r1, [r3]                                 \n" /* r1 = pxCurrentTCB.*/
+            "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
+            "                                                 \n"
+            " restore_special_regs:                           \n"
+            "    ldmdb r2!, {r0, r3-r5, lr}                   \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
+            "    msr psp, r3                                  \n"
+            "    msr psplim, r4                               \n"
+            "    msr control, r5                              \n"
+            "    ldr r4, xSecureContextConst                  \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "    str r0, [r4]                                 \n" /* Restore xSecureContext. */
+            "    cbz r0, restore_ns_context                   \n" /* No secure context to restore. */
+            "                                                 \n"
+            " restore_s_context:                              \n"
+            "    push {r1-r3, lr}                             \n"
+            "    bl SecureContext_LoadContext                 \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+            "    pop {r1-r3, lr}                              \n"
+            "                                                 \n"
+            " restore_ns_context:                             \n"
+            "    mov r0, lr                                   \n" /* r0 = LR (EXC_RETURN). */
+            "    lsls r0, r0, #25                             \n" /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+            "    bmi restore_context_done                     \n" /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
+            "                                                 \n"
+            " restore_general_regs:                           \n"
+            "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
+            "    stmia r3!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
+            "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 restored. */
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+                "    tst lr, #0x10                                \n"
+                "    ittt eq                                      \n"
+                "    vldmdbeq r2!, {s0-s16}                       \n" /* s0-s16 contain hardware saved FP context. */
+                "    vstmiaeq r3!, {s0-s16}                       \n" /* Copy hardware saved FP context on the task stack. */
+                "    vldmdbeq r2!, {s16-s31}                      \n" /* Restore s16-s31. */
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+            "                                                 \n"
+            " restore_context_done:                           \n"
+            "    str r2, [r1]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
+            "    bx lr                                        \n"
+            "                                                 \n"
+            " .align 4                                        \n"
+            " pxCurrentTCBConst: .word pxCurrentTCB           \n"
+            " xSecureContextConst: .word xSecureContext       \n"
+            " xMPUCTRLConst: .word 0xe000ed94                 \n"
+            " xMAIR0Const: .word 0xe000edc0                   \n"
+            " xRNRConst: .word 0xe000ed98                     \n"
+            " xRBARConst: .word 0xe000ed9c                    \n"
+            ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+        );
+    }
 
 #else /* configENABLE_MPU */
 
-void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "   .syntax unified                                 \n"
-        "   .extern SecureContext_SaveContext               \n"
-        "   .extern SecureContext_LoadContext               \n"
-        "                                                   \n"
-        "   ldr r3, xSecureContextConst                     \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
-        "   ldr r0, [r3]                                    \n"/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
-        "   ldr r3, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r3]                                    \n"/* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
-        "   mrs r2, psp                                     \n"/* Read PSP in r2. */
-        "                                                   \n"
-        "   cbz r0, save_ns_context                         \n"/* No secure context to save. */
-        "   push {r0-r2, r14}                               \n"
-        "   bl SecureContext_SaveContext                    \n"/* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-        "   pop {r0-r3}                                     \n"/* LR is now in r3. */
-        "   mov lr, r3                                      \n"/* LR = r3. */
-        "   lsls r1, r3, #25                                \n"/* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-        "   bpl save_ns_context                             \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-        "                                                   \n"
-        "   ldr r3, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r3]                                    \n"/* Read pxCurrentTCB.*/
-        "   subs r2, r2, #12                                \n"/* Make space for xSecureContext, PSPLIM and LR on the stack. */
-        "   str r2, [r1]                                    \n"/* Save the new top of stack in TCB. */
-        "   mrs r1, psplim                                  \n"/* r1 = PSPLIM. */
-        "   mov r3, lr                                      \n"/* r3 = LR/EXC_RETURN. */
-        "   stmia r2!, {r0, r1, r3}                         \n"/* Store xSecureContext, PSPLIM and LR on the stack. */
-        "   b select_next_task                              \n"
-        "                                                   \n"
-        " save_ns_context:                                  \n"
-        "   ldr r3, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r3]                                    \n"/* Read pxCurrentTCB. */
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-            "   tst lr, #0x10                               \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
-            "   it eq                                       \n"
-            "   vstmdbeq r2!, {s16-s31}                     \n"/* Store the additional FP context registers which are not saved automatically. */
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-        "   subs r2, r2, #44                                \n"/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
-        "   str r2, [r1]                                    \n"/* Save the new top of stack in TCB. */
-        "   adds r2, r2, #12                                \n"/* r2 = r2 + 12. */
-        "   stm r2, {r4-r11}                                \n"/* Store the registers that are not saved automatically. */
-        "   mrs r1, psplim                                  \n"/* r1 = PSPLIM. */
-        "   mov r3, lr                                      \n"/* r3 = LR/EXC_RETURN. */
-        "   subs r2, r2, #12                                \n"/* r2 = r2 - 12. */
-        "   stmia r2!, {r0, r1, r3}                         \n"/* Store xSecureContext, PSPLIM and LR on the stack. */
-        "                                                   \n"
-        " select_next_task:                                 \n"
-        "   mov r0, %0                                      \n"/* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
-        "   msr basepri, r0                                 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        "   dsb                                             \n"
-        "   isb                                             \n"
-        "   bl vTaskSwitchContext                           \n"
-        "   mov r0, #0                                      \n"/* r0 = 0. */
-        "   msr basepri, r0                                 \n"/* Enable interrupts. */
-        "                                                   \n"
-        "   ldr r3, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r3]                                    \n"/* Read pxCurrentTCB. */
-        "   ldr r2, [r1]                                    \n"/* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
-        "                                                   \n"
-        "   ldmia r2!, {r0, r1, r4}                         \n"/* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
-        "   msr psplim, r1                                  \n"/* Restore the PSPLIM register value for the task. */
-        "   mov lr, r4                                      \n"/* LR = r4. */
-        "   ldr r3, xSecureContextConst                     \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
-        "   str r0, [r3]                                    \n"/* Restore the task's xSecureContext. */
-        "   cbz r0, restore_ns_context                      \n"/* If there is no secure context for the task, restore the non-secure context. */
-        "   ldr r3, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r3]                                    \n"/* Read pxCurrentTCB. */
-        "   push {r2, r4}                                   \n"
-        "   bl SecureContext_LoadContext                    \n"/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-        "   pop {r2, r4}                                    \n"
-        "   mov lr, r4                                      \n"/* LR = r4. */
-        "   lsls r1, r4, #25                                \n"/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-        "   bpl restore_ns_context                          \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-        "   msr psp, r2                                     \n"/* Remember the new top of stack for the task. */
-        "   bx lr                                           \n"
-        "                                                   \n"
-        " restore_ns_context:                               \n"
-        "   ldmia r2!, {r4-r11}                             \n"/* Restore the registers that are not automatically restored. */
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-            "   tst lr, #0x10                               \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
-            "   it eq                                       \n"
-            "   vldmiaeq r2!, {s16-s31}                     \n"/* Restore the additional FP context registers which are not restored automatically. */
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-        "   msr psp, r2                                     \n"/* Remember the new top of stack for the task. */
-        "   bx lr                                           \n"
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "pxCurrentTCBConst: .word pxCurrentTCB              \n"
-        "xSecureContextConst: .word xSecureContext          \n"
-        ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
-    );
-}
+    void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            "   .syntax unified                                 \n"
+            "   .extern SecureContext_SaveContext               \n"
+            "   .extern SecureContext_LoadContext               \n"
+            "                                                   \n"
+            "   ldr r3, xSecureContextConst                     \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "   ldr r0, [r3]                                    \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
+            "   mrs r2, psp                                     \n" /* Read PSP in r2. */
+            "                                                   \n"
+            "   cbz r0, save_ns_context                         \n" /* No secure context to save. */
+            "   push {r0-r2, r14}                               \n"
+            "   bl SecureContext_SaveContext                    \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+            "   pop {r0-r3}                                     \n" /* LR is now in r3. */
+            "   mov lr, r3                                      \n" /* LR = r3. */
+            "   lsls r1, r3, #25                                \n" /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+            "   bpl save_ns_context                             \n" /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+            "                                                   \n"
+            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB.*/
+            "   subs r2, r2, #12                                \n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */
+            "   str r2, [r1]                                    \n" /* Save the new top of stack in TCB. */
+            "   mrs r1, psplim                                  \n" /* r1 = PSPLIM. */
+            "   mov r3, lr                                      \n" /* r3 = LR/EXC_RETURN. */
+            "   stmia r2!, {r0, r1, r3}                         \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
+            "   b select_next_task                              \n"
+            "                                                   \n"
+            " save_ns_context:                                  \n"
+            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+                "   tst lr, #0x10                               \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+                "   it eq                                       \n"
+                "   vstmdbeq r2!, {s16-s31}                     \n" /* Store the additional FP context registers which are not saved automatically. */
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+            "   subs r2, r2, #44                                \n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
+            "   str r2, [r1]                                    \n" /* Save the new top of stack in TCB. */
+            "   adds r2, r2, #12                                \n" /* r2 = r2 + 12. */
+            "   stm r2, {r4-r11}                                \n" /* Store the registers that are not saved automatically. */
+            "   mrs r1, psplim                                  \n" /* r1 = PSPLIM. */
+            "   mov r3, lr                                      \n" /* r3 = LR/EXC_RETURN. */
+            "   subs r2, r2, #12                                \n" /* r2 = r2 - 12. */
+            "   stmia r2!, {r0, r1, r3}                         \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
+            "                                                   \n"
+            " select_next_task:                                 \n"
+            "   mov r0, %0                                      \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
+            "   msr basepri, r0                                 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+            "   dsb                                             \n"
+            "   isb                                             \n"
+            "   bl vTaskSwitchContext                           \n"
+            "   mov r0, #0                                      \n" /* r0 = 0. */
+            "   msr basepri, r0                                 \n" /* Enable interrupts. */
+            "                                                   \n"
+            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
+            "   ldr r2, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
+            "                                                   \n"
+            "   ldmia r2!, {r0, r1, r4}                         \n" /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
+            "   msr psplim, r1                                  \n" /* Restore the PSPLIM register value for the task. */
+            "   mov lr, r4                                      \n" /* LR = r4. */
+            "   ldr r3, xSecureContextConst                     \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "   str r0, [r3]                                    \n" /* Restore the task's xSecureContext. */
+            "   cbz r0, restore_ns_context                      \n" /* If there is no secure context for the task, restore the non-secure context. */
+            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
+            "   push {r2, r4}                                   \n"
+            "   bl SecureContext_LoadContext                    \n" /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+            "   pop {r2, r4}                                    \n"
+            "   mov lr, r4                                      \n" /* LR = r4. */
+            "   lsls r1, r4, #25                                \n" /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+            "   bpl restore_ns_context                          \n" /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+            "   msr psp, r2                                     \n" /* Remember the new top of stack for the task. */
+            "   bx lr                                           \n"
+            "                                                   \n"
+            " restore_ns_context:                               \n"
+            "   ldmia r2!, {r4-r11}                             \n" /* Restore the registers that are not automatically restored. */
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+                "   tst lr, #0x10                               \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+                "   it eq                                       \n"
+                "   vldmiaeq r2!, {s16-s31}                     \n" /* Restore the additional FP context registers which are not restored automatically. */
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+            "   msr psp, r2                                     \n" /* Remember the new top of stack for the task. */
+            "   bx lr                                           \n"
+            "                                                   \n"
+            "   .align 4                                        \n"
+            "pxCurrentTCBConst: .word pxCurrentTCB              \n"
+            "xSecureContextConst: .word xSecureContext          \n"
+            ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+        );
+    }
 
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-   __asm volatile
-    (
-        ".syntax unified                \n"
-        ".extern vPortSVCHandler_C      \n"
-        ".extern vSystemCallEnter       \n"
-        ".extern vSystemCallEnter_1     \n"
-        ".extern vSystemCallExit        \n"
-        "                               \n"
-        "tst lr, #4                     \n"
-        "ite eq                         \n"
-        "mrseq r0, msp                  \n"
-        "mrsne r0, psp                  \n"
-        "                               \n"
-        "ldr r1, [r0, #24]              \n"
-        "ldrb r2, [r1, #-2]             \n"
-        "cmp r2, %0                     \n"
-        "beq syscall_enter              \n"
-        "cmp r2, %1                     \n"
-        "beq syscall_enter_1            \n"
-        "cmp r2, %2                     \n"
-        "beq syscall_exit               \n"
-        "b vPortSVCHandler_C            \n"
-        "                               \n"
-        "syscall_enter:                 \n"
-        "    mov r1, lr                 \n"
-        "    b vSystemCallEnter         \n"
-        "                               \n"
-        "syscall_enter_1:               \n"
-        "    mov r1, lr                 \n"
-        "    b vSystemCallEnter_1       \n"
-        "                               \n"
-        "syscall_exit:                  \n"
-        "    mov r1, lr                 \n"
-        "    b vSystemCallExit          \n"
-        "                               \n"
-        : /* No outputs. */
-        :"i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT )
-        : "r0", "r1", "r2", "memory"
-    );
-}
+    void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            ".syntax unified                \n"
+            ".extern vPortSVCHandler_C      \n"
+            ".extern vSystemCallEnter       \n"
+            ".extern vSystemCallEnter_1     \n"
+            ".extern vSystemCallExit        \n"
+            "                               \n"
+            "tst lr, #4                     \n"
+            "ite eq                         \n"
+            "mrseq r0, msp                  \n"
+            "mrsne r0, psp                  \n"
+            "                               \n"
+            "ldr r1, [r0, #24]              \n"
+            "ldrb r2, [r1, #-2]             \n"
+            "cmp r2, %0                     \n"
+            "beq syscall_enter              \n"
+            "cmp r2, %1                     \n"
+            "beq syscall_enter_1            \n"
+            "cmp r2, %2                     \n"
+            "beq syscall_exit               \n"
+            "b vPortSVCHandler_C            \n"
+            "                               \n"
+            "syscall_enter:                 \n"
+            "    mov r1, lr                 \n"
+            "    b vSystemCallEnter         \n"
+            "                               \n"
+            "syscall_enter_1:               \n"
+            "    mov r1, lr                 \n"
+            "    b vSystemCallEnter_1       \n"
+            "                               \n"
+            "syscall_exit:                  \n"
+            "    mov r1, lr                 \n"
+            "    b vSystemCallExit          \n"
+            "                               \n"
+            : /* No outputs. */
+            : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT )
+            : "r0", "r1", "r2", "memory"
+        );
+    }
 
 #else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
-void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "   .syntax unified                                 \n"
-        "                                                   \n"
-        "   tst lr, #4                                      \n"
-        "   ite eq                                          \n"
-        "   mrseq r0, msp                                   \n"
-        "   mrsne r0, psp                                   \n"
-        "   ldr r1, svchandler_address_const                \n"
-        "   bx r1                                           \n"
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "svchandler_address_const: .word vPortSVCHandler_C  \n"
-    );
-}
+    void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            "   .syntax unified                                 \n"
+            "                                                   \n"
+            "   tst lr, #4                                      \n"
+            "   ite eq                                          \n"
+            "   mrseq r0, msp                                   \n"
+            "   mrsne r0, psp                                   \n"
+            "   ldr r1, svchandler_address_const                \n"
+            "   bx r1                                           \n"
+            "                                                   \n"
+            "   .align 4                                        \n"
+            "svchandler_address_const: .word vPortSVCHandler_C  \n"
+        );
+    }
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
@@ -587,8 +587,8 @@ void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   svc %0                                          \n"/* Secure context is allocated in the supervisor call. */
-        "   bx lr                                           \n"/* Return. */
+        "   svc %0                                          \n" /* Secure context is allocated in the supervisor call. */
+        "   bx lr                                           \n" /* Return. */
         ::"i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"
     );
 }
@@ -600,12 +600,12 @@ void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PR
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   ldr r2, [r0]                                    \n"/* The first item in the TCB is the top of the stack. */
-        "   ldr r1, [r2]                                    \n"/* The first item on the stack is the task's xSecureContext. */
-        "   cmp r1, #0                                      \n"/* Raise svc if task's xSecureContext is not NULL. */
+        "   ldr r2, [r0]                                    \n" /* The first item in the TCB is the top of the stack. */
+        "   ldr r1, [r2]                                    \n" /* The first item on the stack is the task's xSecureContext. */
+        "   cmp r1, #0                                      \n" /* Raise svc if task's xSecureContext is not NULL. */
         "   it ne                                           \n"
-        "   svcne %0                                        \n"/* Secure context is freed in the supervisor call. */
-        "   bx lr                                           \n"/* Return. */
+        "   svcne %0                                        \n" /* Secure context is freed in the supervisor call. */
+        "   bx lr                                           \n" /* Return. */
         ::"i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"
     );
 }
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h
index 428d38f0a..227327ac8 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h
@@ -48,9 +48,9 @@
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME                       "Cortex-M33"
-#define portHAS_ARMV8M_MAIN_EXTENSION       1
-#define portDONT_DISCARD                    __attribute__( ( used ) )
+#define portARCH_NAME                    "Cortex-M33"
+#define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
 /* ARMv8-M common port configurations. */
@@ -60,8 +60,8 @@
 /**
  * @brief Critical section management.
  */
-#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()
-#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )
+#define portDISABLE_INTERRUPTS()    ulSetInterruptMask()
+#define portENABLE_INTERRUPTS()     vClearInterruptMask( 0 )
 /*-----------------------------------------------------------*/
 
 /* *INDENT-OFF* */
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/mpu_wrappers_v2_asm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/mpu_wrappers_v2_asm.c
index 2d1218a95..d1fbdc0e5 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/mpu_wrappers_v2_asm.c
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/mpu_wrappers_v2_asm.c
@@ -44,2274 +44,2274 @@
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-#if ( INCLUDE_xTaskDelayUntil == 1 )
+    #if ( INCLUDE_xTaskDelayUntil == 1 )
 
-BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
-                                const TickType_t xTimeIncrement ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
+                                        const TickType_t xTimeIncrement ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
-                                const TickType_t xTimeIncrement ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskDelayUntilImpl                       \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskDelayUntil_Unpriv                        \n"
-        " MPU_xTaskDelayUntil_Priv:                             \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskDelayUntilImpl                         \n"
-        " MPU_xTaskDelayUntil_Unpriv:                           \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskDelayUntilImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
+                                        const TickType_t xTimeIncrement ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskDelayUntilImpl                       \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskDelayUntil_Unpriv                        \n"
+                " MPU_xTaskDelayUntil_Priv:                             \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskDelayUntilImpl                         \n"
+                " MPU_xTaskDelayUntil_Unpriv:                           \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskDelayUntilImpl                        \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */
+    #endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_xTaskAbortDelay == 1 )
+    #if ( INCLUDE_xTaskAbortDelay == 1 )
 
-BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskAbortDelayImpl                       \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskAbortDelay_Unpriv                        \n"
-        " MPU_xTaskAbortDelay_Priv:                             \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskAbortDelayImpl                         \n"
-        " MPU_xTaskAbortDelay_Unpriv:                           \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskAbortDelayImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskAbortDelayImpl                       \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskAbortDelay_Unpriv                        \n"
+                " MPU_xTaskAbortDelay_Priv:                             \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskAbortDelayImpl                         \n"
+                " MPU_xTaskAbortDelay_Unpriv:                           \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskAbortDelayImpl                        \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */
+    #endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_vTaskDelay == 1 )
+    #if ( INCLUDE_vTaskDelay == 1 )
 
-void MPU_vTaskDelay( const TickType_t xTicksToDelay ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskDelay( const TickType_t xTicksToDelay ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskDelayImpl                            \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskDelay_Unpriv                             \n"
-        " MPU_vTaskDelay_Priv:                                  \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskDelayImpl                              \n"
-        " MPU_vTaskDelay_Unpriv:                                \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskDelayImpl                             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskDelayImpl                            \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskDelay_Unpriv                             \n"
+                " MPU_vTaskDelay_Priv:                                  \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskDelayImpl                              \n"
+                " MPU_vTaskDelay_Unpriv:                                \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskDelayImpl                             \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_vTaskDelay == 1 ) */
+    #endif /* if ( INCLUDE_vTaskDelay == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_uxTaskPriorityGet == 1 )
+    #if ( INCLUDE_uxTaskPriorityGet == 1 )
 
-UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskPriorityGetImpl                     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTaskPriorityGet_Unpriv                      \n"
-        " MPU_uxTaskPriorityGet_Priv:                           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTaskPriorityGetImpl                       \n"
-        " MPU_uxTaskPriorityGet_Unpriv:                         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskPriorityGetImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskPriorityGetImpl                     \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTaskPriorityGet_Unpriv                      \n"
+                " MPU_uxTaskPriorityGet_Priv:                           \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTaskPriorityGetImpl                       \n"
+                " MPU_uxTaskPriorityGet_Unpriv:                         \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskPriorityGetImpl                      \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */
+    #endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_eTaskGetState == 1 )
+    #if ( INCLUDE_eTaskGetState == 1 )
 
-eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_eTaskGetStateImpl                         \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_eTaskGetState_Unpriv                          \n"
-        " MPU_eTaskGetState_Priv:                               \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_eTaskGetStateImpl                           \n"
-        " MPU_eTaskGetState_Unpriv:                             \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_eTaskGetStateImpl                          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_eTaskGetStateImpl                         \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_eTaskGetState_Unpriv                          \n"
+                " MPU_eTaskGetState_Priv:                               \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_eTaskGetStateImpl                           \n"
+                " MPU_eTaskGetState_Unpriv:                             \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_eTaskGetStateImpl                          \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_eTaskGetState == 1 ) */
+    #endif /* if ( INCLUDE_eTaskGetState == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-void MPU_vTaskGetInfo( TaskHandle_t xTask,
-                       TaskStatus_t * pxTaskStatus,
-                       BaseType_t xGetFreeStackSpace,
-                       eTaskState eState ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskGetInfo( TaskHandle_t xTask,
+                               TaskStatus_t * pxTaskStatus,
+                               BaseType_t xGetFreeStackSpace,
+                               eTaskState eState ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskGetInfo( TaskHandle_t xTask,
-                       TaskStatus_t * pxTaskStatus,
-                       BaseType_t xGetFreeStackSpace,
-                       eTaskState eState ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskGetInfoImpl                          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskGetInfo_Unpriv                           \n"
-        " MPU_vTaskGetInfo_Priv:                                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskGetInfoImpl                            \n"
-        " MPU_vTaskGetInfo_Unpriv:                              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskGetInfoImpl                           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskGetInfo( TaskHandle_t xTask,
+                               TaskStatus_t * pxTaskStatus,
+                               BaseType_t xGetFreeStackSpace,
+                               eTaskState eState ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskGetInfoImpl                          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskGetInfo_Unpriv                           \n"
+                " MPU_vTaskGetInfo_Priv:                                \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskGetInfoImpl                            \n"
+                " MPU_vTaskGetInfo_Unpriv:                              \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskGetInfoImpl                           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
+    #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
+    #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
 
-TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetIdleTaskHandleImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGetIdleTaskHandle_Unpriv                 \n"
-        " MPU_xTaskGetIdleTaskHandle_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGetIdleTaskHandleImpl                  \n"
-        " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetIdleTaskHandleImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetIdleTaskHandleImpl                \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGetIdleTaskHandle_Unpriv                 \n"
+                " MPU_xTaskGetIdleTaskHandle_Priv:                      \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGetIdleTaskHandleImpl                  \n"
+                " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetIdleTaskHandleImpl                 \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */
+    #endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_vTaskSuspend == 1 )
+    #if ( INCLUDE_vTaskSuspend == 1 )
 
-void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSuspendImpl                          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskSuspend_Unpriv                           \n"
-        " MPU_vTaskSuspend_Priv:                                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskSuspendImpl                            \n"
-        " MPU_vTaskSuspend_Unpriv:                              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSuspendImpl                           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskSuspendImpl                          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskSuspend_Unpriv                           \n"
+                " MPU_vTaskSuspend_Priv:                                \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskSuspendImpl                            \n"
+                " MPU_vTaskSuspend_Unpriv:                              \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskSuspendImpl                           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
+    #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_vTaskSuspend == 1 )
+    #if ( INCLUDE_vTaskSuspend == 1 )
 
-void MPU_vTaskResume( TaskHandle_t xTaskToResume ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskResume( TaskHandle_t xTaskToResume ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskResumeImpl                           \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskResume_Unpriv                            \n"
-        " MPU_vTaskResume_Priv:                                 \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskResumeImpl                             \n"
-        " MPU_vTaskResume_Unpriv:                               \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskResumeImpl                            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskResumeImpl                           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskResume_Unpriv                            \n"
+                " MPU_vTaskResume_Priv:                                 \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskResumeImpl                             \n"
+                " MPU_vTaskResume_Unpriv:                               \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskResumeImpl                            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
+    #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
 /*-----------------------------------------------------------*/
 
-TickType_t MPU_xTaskGetTickCount( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    TickType_t MPU_xTaskGetTickCount( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TickType_t MPU_xTaskGetTickCount( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetTickCountImpl                     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGetTickCount_Unpriv                      \n"
-        " MPU_xTaskGetTickCount_Priv:                           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGetTickCountImpl                       \n"
-        " MPU_xTaskGetTickCount_Unpriv:                         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetTickCountImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    TickType_t MPU_xTaskGetTickCount( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xTaskGetTickCountImpl                     \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xTaskGetTickCount_Unpriv                      \n"
+            " MPU_xTaskGetTickCount_Priv:                           \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xTaskGetTickCountImpl                       \n"
+            " MPU_xTaskGetTickCount_Unpriv:                         \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xTaskGetTickCountImpl                      \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetNumberOfTasksImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTaskGetNumberOfTasks_Unpriv                 \n"
-        " MPU_uxTaskGetNumberOfTasks_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTaskGetNumberOfTasksImpl                  \n"
-        " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetNumberOfTasksImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_uxTaskGetNumberOfTasksImpl                \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_uxTaskGetNumberOfTasks_Unpriv                 \n"
+            " MPU_uxTaskGetNumberOfTasks_Priv:                      \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_uxTaskGetNumberOfTasksImpl                  \n"
+            " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_uxTaskGetNumberOfTasksImpl                 \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configGENERATE_RUN_TIME_STATS == 1 )
+    #if ( configGENERATE_RUN_TIME_STATS == 1 )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetRunTimeCounterImpl               \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGetRunTimeCounter_Unpriv                \n"
-        " MPU_ulTaskGetRunTimeCounter_Priv:                     \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGetRunTimeCounterImpl                 \n"
-        " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetRunTimeCounterImpl                \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetRunTimeCounterImpl               \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGetRunTimeCounter_Unpriv                \n"
+                " MPU_ulTaskGetRunTimeCounter_Priv:                     \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGetRunTimeCounterImpl                 \n"
+                " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetRunTimeCounterImpl                \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configGENERATE_RUN_TIME_STATS == 1 )
+    #if ( configGENERATE_RUN_TIME_STATS == 1 )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetRunTimePercentImpl               \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGetRunTimePercent_Unpriv                \n"
-        " MPU_ulTaskGetRunTimePercent_Priv:                     \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGetRunTimePercentImpl                 \n"
-        " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetRunTimePercentImpl                \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetRunTimePercentImpl               \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGetRunTimePercent_Unpriv                \n"
+                " MPU_ulTaskGetRunTimePercent_Priv:                     \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGetRunTimePercentImpl                 \n"
+                " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetRunTimePercentImpl                \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+    #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetIdleRunTimePercentImpl           \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv            \n"
-        " MPU_ulTaskGetIdleRunTimePercent_Priv:                 \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGetIdleRunTimePercentImpl             \n"
-        " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetIdleRunTimePercentImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetIdleRunTimePercentImpl           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv            \n"
+                " MPU_ulTaskGetIdleRunTimePercent_Priv:                 \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGetIdleRunTimePercentImpl             \n"
+                " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetIdleRunTimePercentImpl            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+    #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetIdleRunTimeCounterImpl           \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv            \n"
-        " MPU_ulTaskGetIdleRunTimeCounter_Priv:                 \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGetIdleRunTimeCounterImpl             \n"
-        " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetIdleRunTimeCounterImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetIdleRunTimeCounterImpl           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv            \n"
+                " MPU_ulTaskGetIdleRunTimeCounter_Priv:                 \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGetIdleRunTimeCounterImpl             \n"
+                " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetIdleRunTimeCounterImpl            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+    #if ( configUSE_APPLICATION_TASK_TAG == 1 )
 
-void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
-                                     TaskHookFunction_t pxHookFunction ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
+                                             TaskHookFunction_t pxHookFunction ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
-                                     TaskHookFunction_t pxHookFunction ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSetApplicationTaskTagImpl            \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskSetApplicationTaskTag_Unpriv             \n"
-        " MPU_vTaskSetApplicationTaskTag_Priv:                  \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskSetApplicationTaskTagImpl              \n"
-        " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSetApplicationTaskTagImpl             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
+                                             TaskHookFunction_t pxHookFunction ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskSetApplicationTaskTagImpl            \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskSetApplicationTaskTag_Unpriv             \n"
+                " MPU_vTaskSetApplicationTaskTag_Priv:                  \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskSetApplicationTaskTagImpl              \n"
+                " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskSetApplicationTaskTagImpl             \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
+    #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+    #if ( configUSE_APPLICATION_TASK_TAG == 1 )
 
-TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetApplicationTaskTagImpl            \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGetApplicationTaskTag_Unpriv             \n"
-        " MPU_xTaskGetApplicationTaskTag_Priv:                  \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGetApplicationTaskTagImpl              \n"
-        " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetApplicationTaskTagImpl             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetApplicationTaskTagImpl            \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGetApplicationTaskTag_Unpriv             \n"
+                " MPU_xTaskGetApplicationTaskTag_Priv:                  \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGetApplicationTaskTagImpl              \n"
+                " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetApplicationTaskTagImpl             \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
+    #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+    #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
 
-void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
-                                            BaseType_t xIndex,
-                                            void * pvValue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
+                                                    BaseType_t xIndex,
+                                                    void * pvValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
-                                            BaseType_t xIndex,
-                                            void * pvValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSetThreadLocalStoragePointerImpl     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv      \n"
-        " MPU_vTaskSetThreadLocalStoragePointer_Priv:           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskSetThreadLocalStoragePointerImpl       \n"
-        " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSetThreadLocalStoragePointerImpl      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
+                                                    BaseType_t xIndex,
+                                                    void * pvValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskSetThreadLocalStoragePointerImpl     \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv      \n"
+                " MPU_vTaskSetThreadLocalStoragePointer_Priv:           \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskSetThreadLocalStoragePointerImpl       \n"
+                " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskSetThreadLocalStoragePointerImpl      \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
+    #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+    #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
 
-void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
-                                               BaseType_t xIndex ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
+                                                       BaseType_t xIndex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
-                                               BaseType_t xIndex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pvTaskGetThreadLocalStoragePointerImpl    \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv     \n"
-        " MPU_pvTaskGetThreadLocalStoragePointer_Priv:          \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_pvTaskGetThreadLocalStoragePointerImpl      \n"
-        " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pvTaskGetThreadLocalStoragePointerImpl     \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
+                                                       BaseType_t xIndex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pvTaskGetThreadLocalStoragePointerImpl    \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv     \n"
+                " MPU_pvTaskGetThreadLocalStoragePointer_Priv:          \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_pvTaskGetThreadLocalStoragePointerImpl      \n"
+                " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pvTaskGetThreadLocalStoragePointerImpl     \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
+    #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
-                                      const UBaseType_t uxArraySize,
-                                      configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
+                                              const UBaseType_t uxArraySize,
+                                              configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
-                                      const UBaseType_t uxArraySize,
-                                      configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetSystemStateImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTaskGetSystemState_Unpriv                   \n"
-        " MPU_uxTaskGetSystemState_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTaskGetSystemStateImpl                    \n"
-        " MPU_uxTaskGetSystemState_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetSystemStateImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
+                                              const UBaseType_t uxArraySize,
+                                              configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskGetSystemStateImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTaskGetSystemState_Unpriv                   \n"
+                " MPU_uxTaskGetSystemState_Priv:                        \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTaskGetSystemStateImpl                    \n"
+                " MPU_uxTaskGetSystemState_Unpriv:                      \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskGetSystemStateImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
+    #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
+    #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
 
-UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetStackHighWaterMarkImpl           \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTaskGetStackHighWaterMark_Unpriv            \n"
-        " MPU_uxTaskGetStackHighWaterMark_Priv:                 \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTaskGetStackHighWaterMarkImpl             \n"
-        " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetStackHighWaterMarkImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskGetStackHighWaterMarkImpl           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTaskGetStackHighWaterMark_Unpriv            \n"
+                " MPU_uxTaskGetStackHighWaterMark_Priv:                 \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTaskGetStackHighWaterMarkImpl             \n"
+                " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskGetStackHighWaterMarkImpl            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */
+    #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
+    #if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
 
-configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetStackHighWaterMark2Impl          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv           \n"
-        " MPU_uxTaskGetStackHighWaterMark2_Priv:                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTaskGetStackHighWaterMark2Impl            \n"
-        " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetStackHighWaterMark2Impl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskGetStackHighWaterMark2Impl          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv           \n"
+                " MPU_uxTaskGetStackHighWaterMark2_Priv:                \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTaskGetStackHighWaterMark2Impl            \n"
+                " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskGetStackHighWaterMark2Impl           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */
+    #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
+    #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
 
-TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetCurrentTaskHandleImpl             \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGetCurrentTaskHandle_Unpriv              \n"
-        " MPU_xTaskGetCurrentTaskHandle_Priv:                   \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGetCurrentTaskHandleImpl               \n"
-        " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetCurrentTaskHandleImpl              \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetCurrentTaskHandleImpl             \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGetCurrentTaskHandle_Unpriv              \n"
+                " MPU_xTaskGetCurrentTaskHandle_Priv:                   \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGetCurrentTaskHandleImpl               \n"
+                " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetCurrentTaskHandleImpl              \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
+    #endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_xTaskGetSchedulerState == 1 )
+    #if ( INCLUDE_xTaskGetSchedulerState == 1 )
 
-BaseType_t MPU_xTaskGetSchedulerState( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGetSchedulerState( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGetSchedulerState( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetSchedulerStateImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGetSchedulerState_Unpriv                 \n"
-        " MPU_xTaskGetSchedulerState_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGetSchedulerStateImpl                  \n"
-        " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetSchedulerStateImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGetSchedulerState( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetSchedulerStateImpl                \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGetSchedulerState_Unpriv                 \n"
+                " MPU_xTaskGetSchedulerState_Priv:                      \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGetSchedulerStateImpl                  \n"
+                " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetSchedulerStateImpl                 \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */
+    #endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */
 /*-----------------------------------------------------------*/
 
-void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSetTimeOutStateImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskSetTimeOutState_Unpriv                   \n"
-        " MPU_vTaskSetTimeOutState_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskSetTimeOutStateImpl                    \n"
-        " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSetTimeOutStateImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_vTaskSetTimeOutStateImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_vTaskSetTimeOutState_Unpriv                   \n"
+            " MPU_vTaskSetTimeOutState_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_vTaskSetTimeOutStateImpl                    \n"
+            " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_vTaskSetTimeOutStateImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
-                                     TickType_t * const pxTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
+                                         TickType_t * const pxTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
-                                     TickType_t * const pxTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskCheckForTimeOutImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskCheckForTimeOut_Unpriv                   \n"
-        " MPU_xTaskCheckForTimeOut_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskCheckForTimeOutImpl                    \n"
-        " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskCheckForTimeOutImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
+                                         TickType_t * const pxTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xTaskCheckForTimeOutImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xTaskCheckForTimeOut_Unpriv                   \n"
+            " MPU_xTaskCheckForTimeOut_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xTaskCheckForTimeOutImpl                    \n"
+            " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xTaskCheckForTimeOutImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                   UBaseType_t uxIndexToNotify,
-                                   uint32_t ulValue,
-                                   eNotifyAction eAction,
-                                   uint32_t * pulPreviousNotificationValue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
+                                           UBaseType_t uxIndexToNotify,
+                                           uint32_t ulValue,
+                                           eNotifyAction eAction,
+                                           uint32_t * pulPreviousNotificationValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                   UBaseType_t uxIndexToNotify,
-                                   uint32_t ulValue,
-                                   eNotifyAction eAction,
-                                   uint32_t * pulPreviousNotificationValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGenericNotifyImpl                    \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGenericNotify_Unpriv                     \n"
-        " MPU_xTaskGenericNotify_Priv:                          \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGenericNotifyImpl                      \n"
-        " MPU_xTaskGenericNotify_Unpriv:                        \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGenericNotifyImpl                     \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
+                                           UBaseType_t uxIndexToNotify,
+                                           uint32_t ulValue,
+                                           eNotifyAction eAction,
+                                           uint32_t * pulPreviousNotificationValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGenericNotifyImpl                    \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGenericNotify_Unpriv                     \n"
+                " MPU_xTaskGenericNotify_Priv:                          \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGenericNotifyImpl                      \n"
+                " MPU_xTaskGenericNotify_Unpriv:                        \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGenericNotifyImpl                     \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                       uint32_t ulBitsToClearOnEntry,
-                                       uint32_t ulBitsToClearOnExit,
-                                       uint32_t * pulNotificationValue,
-                                       TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
+                                               uint32_t ulBitsToClearOnEntry,
+                                               uint32_t ulBitsToClearOnExit,
+                                               uint32_t * pulNotificationValue,
+                                               TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                       uint32_t ulBitsToClearOnEntry,
-                                       uint32_t ulBitsToClearOnExit,
-                                       uint32_t * pulNotificationValue,
-                                       TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGenericNotifyWaitImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGenericNotifyWait_Unpriv                 \n"
-        " MPU_xTaskGenericNotifyWait_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGenericNotifyWaitImpl                  \n"
-        " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGenericNotifyWaitImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
+                                               uint32_t ulBitsToClearOnEntry,
+                                               uint32_t ulBitsToClearOnExit,
+                                               uint32_t * pulNotificationValue,
+                                               TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGenericNotifyWaitImpl                \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGenericNotifyWait_Unpriv                 \n"
+                " MPU_xTaskGenericNotifyWait_Priv:                      \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGenericNotifyWaitImpl                  \n"
+                " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGenericNotifyWaitImpl                 \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
-                                      BaseType_t xClearCountOnExit,
-                                      TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
+                                              BaseType_t xClearCountOnExit,
+                                              TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
-                                      BaseType_t xClearCountOnExit,
-                                      TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGenericNotifyTakeImpl               \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGenericNotifyTake_Unpriv                \n"
-        " MPU_ulTaskGenericNotifyTake_Priv:                     \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGenericNotifyTakeImpl                 \n"
-        " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGenericNotifyTakeImpl                \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
+                                              BaseType_t xClearCountOnExit,
+                                              TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGenericNotifyTakeImpl               \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGenericNotifyTake_Unpriv                \n"
+                " MPU_ulTaskGenericNotifyTake_Priv:                     \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGenericNotifyTakeImpl                 \n"
+                " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGenericNotifyTakeImpl                \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
-                                             UBaseType_t uxIndexToClear ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
+                                                     UBaseType_t uxIndexToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
-                                             UBaseType_t uxIndexToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGenericNotifyStateClearImpl          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGenericNotifyStateClear_Unpriv           \n"
-        " MPU_xTaskGenericNotifyStateClear_Priv:                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGenericNotifyStateClearImpl            \n"
-        " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGenericNotifyStateClearImpl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
+                                                     UBaseType_t uxIndexToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGenericNotifyStateClearImpl          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGenericNotifyStateClear_Unpriv           \n"
+                " MPU_xTaskGenericNotifyStateClear_Priv:                \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGenericNotifyStateClearImpl            \n"
+                " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGenericNotifyStateClearImpl           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
-                                            UBaseType_t uxIndexToClear,
-                                            uint32_t ulBitsToClear ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
+                                                    UBaseType_t uxIndexToClear,
+                                                    uint32_t ulBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
-                                            UBaseType_t uxIndexToClear,
-                                            uint32_t ulBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGenericNotifyValueClearImpl         \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGenericNotifyValueClear_Unpriv          \n"
-        " MPU_ulTaskGenericNotifyValueClear_Priv:               \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGenericNotifyValueClearImpl           \n"
-        " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGenericNotifyValueClearImpl          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
+                                                    UBaseType_t uxIndexToClear,
+                                                    uint32_t ulBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGenericNotifyValueClearImpl         \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGenericNotifyValueClear_Unpriv          \n"
+                " MPU_ulTaskGenericNotifyValueClear_Priv:               \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGenericNotifyValueClearImpl           \n"
+                " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGenericNotifyValueClearImpl          \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
-                                  const void * const pvItemToQueue,
-                                  TickType_t xTicksToWait,
-                                  const BaseType_t xCopyPosition ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
+                                      const void * const pvItemToQueue,
+                                      TickType_t xTicksToWait,
+                                      const BaseType_t xCopyPosition ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
-                                  const void * const pvItemToQueue,
-                                  TickType_t xTicksToWait,
-                                  const BaseType_t xCopyPosition ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueGenericSendImpl                     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueGenericSend_Unpriv                      \n"
-        " MPU_xQueueGenericSend_Priv:                           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueGenericSendImpl                       \n"
-        " MPU_xQueueGenericSend_Unpriv:                         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueGenericSendImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
+                                      const void * const pvItemToQueue,
+                                      TickType_t xTicksToWait,
+                                      const BaseType_t xCopyPosition ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueueGenericSendImpl                     \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xQueueGenericSend_Unpriv                      \n"
+            " MPU_xQueueGenericSend_Priv:                           \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xQueueGenericSendImpl                       \n"
+            " MPU_xQueueGenericSend_Unpriv:                         \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueueGenericSendImpl                      \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxQueueMessagesWaitingImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxQueueMessagesWaiting_Unpriv                 \n"
-        " MPU_uxQueueMessagesWaiting_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxQueueMessagesWaitingImpl                  \n"
-        " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxQueueMessagesWaitingImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_uxQueueMessagesWaitingImpl                \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_uxQueueMessagesWaiting_Unpriv                 \n"
+            " MPU_uxQueueMessagesWaiting_Priv:                      \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_uxQueueMessagesWaitingImpl                  \n"
+            " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_uxQueueMessagesWaitingImpl                 \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxQueueSpacesAvailableImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxQueueSpacesAvailable_Unpriv                 \n"
-        " MPU_uxQueueSpacesAvailable_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxQueueSpacesAvailableImpl                  \n"
-        " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxQueueSpacesAvailableImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_uxQueueSpacesAvailableImpl                \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_uxQueueSpacesAvailable_Unpriv                 \n"
+            " MPU_uxQueueSpacesAvailable_Priv:                      \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_uxQueueSpacesAvailableImpl                  \n"
+            " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_uxQueueSpacesAvailableImpl                 \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
-                              void * const pvBuffer,
-                              TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
+                                  void * const pvBuffer,
+                                  TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
-                              void * const pvBuffer,
-                              TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueReceiveImpl                         \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueReceive_Unpriv                          \n"
-        " MPU_xQueueReceive_Priv:                               \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueReceiveImpl                           \n"
-        " MPU_xQueueReceive_Unpriv:                             \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueReceiveImpl                          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
+                                  void * const pvBuffer,
+                                  TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueueReceiveImpl                         \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xQueueReceive_Unpriv                          \n"
+            " MPU_xQueueReceive_Priv:                               \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xQueueReceiveImpl                           \n"
+            " MPU_xQueueReceive_Unpriv:                             \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueueReceiveImpl                          \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
-                           void * const pvBuffer,
-                           TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
+                               void * const pvBuffer,
+                               TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
-                           void * const pvBuffer,
-                           TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueuePeekImpl                            \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueuePeek_Unpriv                             \n"
-        " MPU_xQueuePeek_Priv:                                  \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueuePeekImpl                              \n"
-        " MPU_xQueuePeek_Unpriv:                                \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueuePeekImpl                             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
+                               void * const pvBuffer,
+                               TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueuePeekImpl                            \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xQueuePeek_Unpriv                             \n"
+            " MPU_xQueuePeek_Priv:                                  \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xQueuePeekImpl                              \n"
+            " MPU_xQueuePeek_Unpriv:                                \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueuePeekImpl                             \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
-                                    TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
+                                        TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
-                                    TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueSemaphoreTakeImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueSemaphoreTake_Unpriv                    \n"
-        " MPU_xQueueSemaphoreTake_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueSemaphoreTakeImpl                     \n"
-        " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueSemaphoreTakeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
+                                        TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueueSemaphoreTakeImpl                   \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xQueueSemaphoreTake_Unpriv                    \n"
+            " MPU_xQueueSemaphoreTake_Priv:                         \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xQueueSemaphoreTakeImpl                     \n"
+            " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueueSemaphoreTakeImpl                    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+    #if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
 
-TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueGetMutexHolderImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueGetMutexHolder_Unpriv                   \n"
-        " MPU_xQueueGetMutexHolder_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueGetMutexHolderImpl                    \n"
-        " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueGetMutexHolderImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueGetMutexHolderImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueGetMutexHolder_Unpriv                   \n"
+                " MPU_xQueueGetMutexHolder_Priv:                        \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueGetMutexHolderImpl                    \n"
+                " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueGetMutexHolderImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */
+    #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+    #if ( configUSE_RECURSIVE_MUTEXES == 1 )
 
-BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
-                                         TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+                                                 TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+        BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+                                                 TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueTakeMutexRecursiveImpl              \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueTakeMutexRecursive_Unpriv               \n"
+                " MPU_xQueueTakeMutexRecursive_Priv:                    \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueTakeMutexRecursiveImpl                \n"
+                " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueTakeMutexRecursiveImpl               \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_RECURSIVE_MUTEXES == 1 )
+
+        BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueGiveMutexRecursiveImpl              \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueGiveMutexRecursive_Unpriv               \n"
+                " MPU_xQueueGiveMutexRecursive_Priv:                    \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueGiveMutexRecursiveImpl                \n"
+                " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueGiveMutexRecursiveImpl               \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_QUEUE_SETS == 1 )
+
+        QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
+                                                        const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
+                                                        const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueSelectFromSetImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueSelectFromSet_Unpriv                    \n"
+                " MPU_xQueueSelectFromSet_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueSelectFromSetImpl                     \n"
+                " MPU_xQueueSelectFromSet_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueSelectFromSetImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_QUEUE_SETS == 1 )
+
+        BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                                       QueueSetHandle_t xQueueSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                                       QueueSetHandle_t xQueueSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueAddToSetImpl                        \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueAddToSet_Unpriv                         \n"
+                " MPU_xQueueAddToSet_Priv:                              \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueAddToSetImpl                          \n"
+                " MPU_xQueueAddToSet_Unpriv:                            \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueAddToSetImpl                         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+        void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
+                                      const char * pcName ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
+                                      const char * pcName ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vQueueAddToRegistryImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vQueueAddToRegistry_Unpriv                    \n"
+                " MPU_vQueueAddToRegistry_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vQueueAddToRegistryImpl                     \n"
+                " MPU_vQueueAddToRegistry_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vQueueAddToRegistryImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+        void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vQueueUnregisterQueueImpl                 \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vQueueUnregisterQueue_Unpriv                  \n"
+                " MPU_vQueueUnregisterQueue_Priv:                       \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vQueueUnregisterQueueImpl                   \n"
+                " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vQueueUnregisterQueueImpl                  \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+        const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pcQueueGetNameImpl                        \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_pcQueueGetName_Unpriv                         \n"
+                " MPU_pcQueueGetName_Priv:                              \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_pcQueueGetNameImpl                          \n"
+                " MPU_pcQueueGetName_Unpriv:                            \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pcQueueGetNameImpl                         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pvTimerGetTimerIDImpl                     \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_pvTimerGetTimerID_Unpriv                      \n"
+                " MPU_pvTimerGetTimerID_Priv:                           \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_pvTimerGetTimerIDImpl                       \n"
+                " MPU_pvTimerGetTimerID_Unpriv:                         \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pvTimerGetTimerIDImpl                      \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
+                                   void * pvNewID ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
+                                   void * pvNewID ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTimerSetTimerIDImpl                      \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTimerSetTimerID_Unpriv                       \n"
+                " MPU_vTimerSetTimerID_Priv:                            \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTimerSetTimerIDImpl                        \n"
+                " MPU_vTimerSetTimerID_Unpriv:                          \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTimerSetTimerIDImpl                       \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerIsTimerActiveImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerIsTimerActive_Unpriv                    \n"
+                " MPU_xTimerIsTimerActive_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerIsTimerActiveImpl                     \n"
+                " MPU_xTimerIsTimerActive_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerIsTimerActiveImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetTimerDaemonTaskHandleImpl        \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv         \n"
+                " MPU_xTimerGetTimerDaemonTaskHandle_Priv:              \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerGetTimerDaemonTaskHandleImpl          \n"
+                " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetTimerDaemonTaskHandleImpl         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                                     const BaseType_t xCommandID,
+                                                     const TickType_t xOptionalValue,
+                                                     BaseType_t * const pxHigherPriorityTaskWoken,
+                                                     const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                                     const BaseType_t xCommandID,
+                                                     const TickType_t xOptionalValue,
+                                                     BaseType_t * const pxHigherPriorityTaskWoken,
+                                                     const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                               \n"
+                " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
+                "                                                               \n"
+                " push {r0}                                                     \n"
+                " mrs r0, control                                               \n"
+                " tst r0, #1                                                    \n"
+                " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
+                " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
+                "     pop {r0}                                                  \n"
+                "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
+                " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
+                "     pop {r0}                                                  \n"
+                "     svc %0                                                    \n"
+                "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
+                "     svc %1                                                    \n"
+                "     bx lr                                                     \n"
+                "                                                               \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pcTimerGetNameImpl                        \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_pcTimerGetName_Unpriv                         \n"
+                " MPU_pcTimerGetName_Priv:                              \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_pcTimerGetNameImpl                          \n"
+                " MPU_pcTimerGetName_Unpriv:                            \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pcTimerGetNameImpl                         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
+                                      const BaseType_t uxAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
+                                      const BaseType_t uxAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTimerSetReloadModeImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTimerSetReloadMode_Unpriv                    \n"
+                " MPU_vTimerSetReloadMode_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTimerSetReloadModeImpl                     \n"
+                " MPU_vTimerSetReloadMode_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTimerSetReloadModeImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetReloadModeImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerGetReloadMode_Unpriv                    \n"
+                " MPU_xTimerGetReloadMode_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerGetReloadModeImpl                     \n"
+                " MPU_xTimerGetReloadMode_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetReloadModeImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTimerGetReloadModeImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTimerGetReloadMode_Unpriv                   \n"
+                " MPU_uxTimerGetReloadMode_Priv:                        \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTimerGetReloadModeImpl                    \n"
+                " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTimerGetReloadModeImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetPeriodImpl                       \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerGetPeriod_Unpriv                        \n"
+                " MPU_xTimerGetPeriod_Priv:                             \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerGetPeriodImpl                         \n"
+                " MPU_xTimerGetPeriod_Unpriv:                           \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetPeriodImpl                        \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetExpiryTimeImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerGetExpiryTime_Unpriv                    \n"
+                " MPU_xTimerGetExpiryTime_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerGetExpiryTimeImpl                     \n"
+                " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetExpiryTimeImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         const BaseType_t xClearOnExit,
+                                         const BaseType_t xWaitForAllBits,
+                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         const BaseType_t xClearOnExit,
+                                         const BaseType_t xWaitForAllBits,
                                          TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueTakeMutexRecursiveImpl              \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueTakeMutexRecursive_Unpriv               \n"
-        " MPU_xQueueTakeMutexRecursive_Priv:                    \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueTakeMutexRecursiveImpl                \n"
-        " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueTakeMutexRecursiveImpl               \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupWaitBitsImpl                   \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
+            " MPU_xEventGroupWaitBits_Priv:                         \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xEventGroupWaitBitsImpl                     \n"
+            " MPU_xEventGroupWaitBits_Unpriv:                       \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupWaitBitsImpl                    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                          const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueGiveMutexRecursiveImpl              \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueGiveMutexRecursive_Unpriv               \n"
-        " MPU_xQueueGiveMutexRecursive_Priv:                    \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueGiveMutexRecursiveImpl                \n"
-        " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueGiveMutexRecursiveImpl               \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                          const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupClearBitsImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xEventGroupClearBits_Unpriv                   \n"
+            " MPU_xEventGroupClearBits_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xEventGroupClearBitsImpl                    \n"
+            " MPU_xEventGroupClearBits_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupClearBitsImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_QUEUE_SETS == 1 )
+    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                        const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
-                                                const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
-                                                const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueSelectFromSetImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueSelectFromSet_Unpriv                    \n"
-        " MPU_xQueueSelectFromSet_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueSelectFromSetImpl                     \n"
-        " MPU_xQueueSelectFromSet_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueSelectFromSetImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                        const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupSetBitsImpl                    \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xEventGroupSetBits_Unpriv                     \n"
+            " MPU_xEventGroupSetBits_Priv:                          \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xEventGroupSetBitsImpl                      \n"
+            " MPU_xEventGroupSetBits_Unpriv:                        \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupSetBitsImpl                     \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_QUEUE_SETS == 1 )
-
-BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
-                               QueueSetHandle_t xQueueSet ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
-                               QueueSetHandle_t xQueueSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueAddToSetImpl                        \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueAddToSet_Unpriv                         \n"
-        " MPU_xQueueAddToSet_Priv:                              \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueAddToSetImpl                          \n"
-        " MPU_xQueueAddToSet_Unpriv:                            \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueAddToSetImpl                         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_QUEUE_SETS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
-                              const char * pcName ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
-                              const char * pcName ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vQueueAddToRegistryImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vQueueAddToRegistry_Unpriv                    \n"
-        " MPU_vQueueAddToRegistry_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vQueueAddToRegistryImpl                     \n"
-        " MPU_vQueueAddToRegistry_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vQueueAddToRegistryImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vQueueUnregisterQueueImpl                 \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vQueueUnregisterQueue_Unpriv                  \n"
-        " MPU_vQueueUnregisterQueue_Priv:                       \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vQueueUnregisterQueueImpl                   \n"
-        " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vQueueUnregisterQueueImpl                  \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pcQueueGetNameImpl                        \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_pcQueueGetName_Unpriv                         \n"
-        " MPU_pcQueueGetName_Priv:                              \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_pcQueueGetNameImpl                          \n"
-        " MPU_pcQueueGetName_Unpriv:                            \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pcQueueGetNameImpl                         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pvTimerGetTimerIDImpl                     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_pvTimerGetTimerID_Unpriv                      \n"
-        " MPU_pvTimerGetTimerID_Priv:                           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_pvTimerGetTimerIDImpl                       \n"
-        " MPU_pvTimerGetTimerID_Unpriv:                         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pvTimerGetTimerIDImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
-                           void * pvNewID ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
-                           void * pvNewID ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTimerSetTimerIDImpl                      \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTimerSetTimerID_Unpriv                       \n"
-        " MPU_vTimerSetTimerID_Priv:                            \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTimerSetTimerIDImpl                        \n"
-        " MPU_vTimerSetTimerID_Unpriv:                          \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTimerSetTimerIDImpl                       \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerIsTimerActiveImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTimerIsTimerActive_Unpriv                    \n"
-        " MPU_xTimerIsTimerActive_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerIsTimerActiveImpl                     \n"
-        " MPU_xTimerIsTimerActive_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerIsTimerActiveImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetTimerDaemonTaskHandleImpl        \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv         \n"
-        " MPU_xTimerGetTimerDaemonTaskHandle_Priv:              \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerGetTimerDaemonTaskHandleImpl          \n"
-        " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetTimerDaemonTaskHandleImpl         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                             const BaseType_t xCommandID,
-                                             const TickType_t xOptionalValue,
-                                             BaseType_t * const pxHigherPriorityTaskWoken,
-                                             const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                             const BaseType_t xCommandID,
-                                             const TickType_t xOptionalValue,
-                                             BaseType_t * const pxHigherPriorityTaskWoken,
-                                             const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                               \n"
-        " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
-        "                                                               \n"
-        " push {r0}                                                     \n"
-        " mrs r0, control                                               \n"
-        " tst r0, #1                                                    \n"
-        " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
-        " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
-        "     pop {r0}                                                  \n"
-        "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
-        " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
-        "     pop {r0}                                                  \n"
-        "     svc %0                                                    \n"
-        "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
-        "     svc %1                                                    \n"
-        "     bx lr                                                     \n"
-        "                                                               \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pcTimerGetNameImpl                        \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_pcTimerGetName_Unpriv                         \n"
-        " MPU_pcTimerGetName_Priv:                              \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_pcTimerGetNameImpl                          \n"
-        " MPU_pcTimerGetName_Unpriv:                            \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pcTimerGetNameImpl                         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                              const BaseType_t uxAutoReload ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                              const BaseType_t uxAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTimerSetReloadModeImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTimerSetReloadMode_Unpriv                    \n"
-        " MPU_vTimerSetReloadMode_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTimerSetReloadModeImpl                     \n"
-        " MPU_vTimerSetReloadMode_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTimerSetReloadModeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetReloadModeImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTimerGetReloadMode_Unpriv                    \n"
-        " MPU_xTimerGetReloadMode_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerGetReloadModeImpl                     \n"
-        " MPU_xTimerGetReloadMode_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetReloadModeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTimerGetReloadModeImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTimerGetReloadMode_Unpriv                   \n"
-        " MPU_uxTimerGetReloadMode_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTimerGetReloadModeImpl                    \n"
-        " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTimerGetReloadModeImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetPeriodImpl                       \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTimerGetPeriod_Unpriv                        \n"
-        " MPU_xTimerGetPeriod_Priv:                             \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerGetPeriodImpl                         \n"
-        " MPU_xTimerGetPeriod_Unpriv:                           \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetPeriodImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetExpiryTimeImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTimerGetExpiryTime_Unpriv                    \n"
-        " MPU_xTimerGetExpiryTime_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerGetExpiryTimeImpl                     \n"
-        " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetExpiryTimeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                     const EventBits_t uxBitsToSet,
                                      const EventBits_t uxBitsToWaitFor,
-                                     const BaseType_t xClearOnExit,
-                                     const BaseType_t xWaitForAllBits,
-                                     TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                     const EventBits_t uxBitsToSet,
                                      const EventBits_t uxBitsToWaitFor,
-                                     const BaseType_t xClearOnExit,
-                                     const BaseType_t xWaitForAllBits,
                                      TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupWaitBitsImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
-        " MPU_xEventGroupWaitBits_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xEventGroupWaitBitsImpl                     \n"
-        " MPU_xEventGroupWaitBits_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupWaitBitsImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupSyncImpl                       \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xEventGroupSync_Unpriv                        \n"
+            " MPU_xEventGroupSync_Priv:                             \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xEventGroupSyncImpl                         \n"
+            " MPU_xEventGroupSync_Unpriv:                           \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupSyncImpl                        \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                      const EventBits_t uxBitsToClear ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                      const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupClearBitsImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xEventGroupClearBits_Unpriv                   \n"
-        " MPU_xEventGroupClearBits_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xEventGroupClearBitsImpl                    \n"
-        " MPU_xEventGroupClearBits_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupClearBitsImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxEventGroupGetNumberImpl                 \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxEventGroupGetNumber_Unpriv                  \n"
+                " MPU_uxEventGroupGetNumber_Priv:                       \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxEventGroupGetNumberImpl                   \n"
+                " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxEventGroupGetNumberImpl                  \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
 /*-----------------------------------------------------------*/
 
-EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                    const EventBits_t uxBitsToSet ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                    const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupSetBitsImpl                    \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xEventGroupSetBits_Unpriv                     \n"
-        " MPU_xEventGroupSetBits_Priv:                          \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xEventGroupSetBitsImpl                      \n"
-        " MPU_xEventGroupSetBits_Unpriv:                        \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupSetBitsImpl                     \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vEventGroupSetNumber( void * xEventGroup,
+                                       UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vEventGroupSetNumber( void * xEventGroup,
+                                       UBaseType_t uxEventGroupNumber ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vEventGroupSetNumberImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vEventGroupSetNumber_Unpriv                   \n"
+                " MPU_vEventGroupSetNumber_Priv:                        \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vEventGroupSetNumberImpl                    \n"
+                " MPU_vEventGroupSetNumber_Unpriv:                      \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vEventGroupSetNumberImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
 /*-----------------------------------------------------------*/
 
-EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                 const EventBits_t uxBitsToSet,
-                                 const EventBits_t uxBitsToWaitFor,
-                                 TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                  const void * pvTxData,
+                                  size_t xDataLengthBytes,
+                                  TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                 const EventBits_t uxBitsToSet,
-                                 const EventBits_t uxBitsToWaitFor,
-                                 TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupSyncImpl                       \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xEventGroupSync_Unpriv                        \n"
-        " MPU_xEventGroupSync_Priv:                             \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xEventGroupSyncImpl                         \n"
-        " MPU_xEventGroupSync_Unpriv:                           \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupSyncImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                  const void * pvTxData,
+                                  size_t xDataLengthBytes,
+                                  TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferSendImpl                     \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferSend_Unpriv                      \n"
+            " MPU_xStreamBufferSend_Priv:                           \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferSendImpl                       \n"
+            " MPU_xStreamBufferSend_Unpriv:                         \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferSendImpl                      \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                     void * pvRxData,
+                                     size_t xBufferLengthBytes,
+                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxEventGroupGetNumberImpl                 \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxEventGroupGetNumber_Unpriv                  \n"
-        " MPU_uxEventGroupGetNumber_Priv:                       \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxEventGroupGetNumberImpl                   \n"
-        " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxEventGroupGetNumberImpl                  \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                     void * pvRxData,
+                                     size_t xBufferLengthBytes,
+                                     TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferReceiveImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferReceive_Unpriv                   \n"
+            " MPU_xStreamBufferReceive_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferReceiveImpl                    \n"
+            " MPU_xStreamBufferReceive_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferReceiveImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vEventGroupSetNumber( void * xEventGroup,
-                               UBaseType_t uxEventGroupNumber ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vEventGroupSetNumber( void * xEventGroup,
-                               UBaseType_t uxEventGroupNumber ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vEventGroupSetNumberImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vEventGroupSetNumber_Unpriv                   \n"
-        " MPU_vEventGroupSetNumber_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vEventGroupSetNumberImpl                    \n"
-        " MPU_vEventGroupSetNumber_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vEventGroupSetNumberImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferIsFullImpl                   \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
+            " MPU_xStreamBufferIsFull_Priv:                         \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferIsFullImpl                     \n"
+            " MPU_xStreamBufferIsFull_Unpriv:                       \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferIsFullImpl                    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                              const void * pvTxData,
-                              size_t xDataLengthBytes,
-                              TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                              const void * pvTxData,
-                              size_t xDataLengthBytes,
-                              TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferSendImpl                     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferSend_Unpriv                      \n"
-        " MPU_xStreamBufferSend_Priv:                           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferSendImpl                       \n"
-        " MPU_xStreamBufferSend_Unpriv:                         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferSendImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
+            " MPU_xStreamBufferIsEmpty_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferIsEmptyImpl                    \n"
+            " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferIsEmptyImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                 void * pvRxData,
-                                 size_t xBufferLengthBytes,
-                                 TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                 void * pvRxData,
-                                 size_t xBufferLengthBytes,
-                                 TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferReceiveImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferReceive_Unpriv                   \n"
-        " MPU_xStreamBufferReceive_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferReceiveImpl                    \n"
-        " MPU_xStreamBufferReceive_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferReceiveImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
+            " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
+            " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferSpacesAvailableImpl           \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferIsFullImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
-        " MPU_xStreamBufferIsFull_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferIsFullImpl                     \n"
-        " MPU_xStreamBufferIsFull_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferIsFullImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
+            " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferBytesAvailableImpl             \n"
+            " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferBytesAvailableImpl            \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                 size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
-        " MPU_xStreamBufferIsEmpty_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferIsEmptyImpl                    \n"
-        " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferIsEmptyImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                 size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
+            " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
+            " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferSetTriggerLevelImpl           \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
-        " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
-        " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferSpacesAvailableImpl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
-size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
-        " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferBytesAvailableImpl             \n"
-        " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferBytesAvailableImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                             size_t xTriggerLevel ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                             size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
-        " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
-        " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferSetTriggerLevelImpl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
-size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
-        " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
-        " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferNextMessageLengthBytesImpl    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
+            " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
+            " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferNextMessageLengthBytesImpl    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c
index 504b6bf3b..e533dd7e9 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c
@@ -42,111 +42,111 @@
 
 #if ( configENABLE_MPU == 1 )
 
-void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        " .syntax unified                                 \n"
-        "                                                 \n"
-        " program_mpu_first_task:                         \n"
-        "    ldr r2, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB. */
-        "                                                 \n"
-        "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-        "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
-        "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
-        "    str r2, [r1]                                 \n" /* Disable MPU. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
-        "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-        "    ldr r2, xMAIR0Const2                         \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-        "    str r1, [r2]                                 \n" /* Program MAIR0. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-        "    ldr r1, xRNRConst2                           \n" /* r1 = 0xe000ed98 [Location of RNR]. */
-        "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "                                                 \n"
-        "    movs r3, #4                                  \n" /* r3 = 4. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 4. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-        "                                                 \n"
-    #if ( configTOTAL_MPU_REGIONS == 16 )
-        "    movs r3, #8                                  \n" /* r3 = 8. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 8. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-        "    movs r3, #12                                 \n" /* r3 = 12. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 12. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-    #endif /* configTOTAL_MPU_REGIONS == 16 */
-        "                                                 \n"
-        "   ldr r1, xMPUCTRLConst2                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
-        "   orr r2, #1                                    \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
-        "   str r2, [r1]                                  \n" /* Enable MPU. */
-        "   dsb                                           \n" /* Force memory writes before continuing. */
-        "                                                 \n"
-        " restore_context_first_task:                     \n"
-        "    ldr r2, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB.*/
-        "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
-        "                                                 \n"
-        " restore_special_regs_first_task:                \n"
-        "    ldmdb r1!, {r2-r4, lr}                       \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
-        "    msr psp, r2                                  \n"
-        "    msr psplim, r3                               \n"
-        "    msr control, r4                              \n"
-        "                                                 \n"
-        " restore_general_regs_first_task:                \n"
-        "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
-        "    stmia r2!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
-        "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 restored. */
-        "                                                 \n"
-        " restore_context_done_first_task:                \n"
-        "    str r1, [r0]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
-        "    mov r0, #0                                   \n"
-        "    msr basepri, r0                              \n" /* Ensure that interrupts are enabled when the first task starts. */
-        "    bx lr                                        \n"
-        "                                                 \n"
-        " .align 4                                        \n"
-        " pxCurrentTCBConst2: .word pxCurrentTCB          \n"
-        " xMPUCTRLConst2: .word 0xe000ed94                \n"
-        " xMAIR0Const2: .word 0xe000edc0                  \n"
-        " xRNRConst2: .word 0xe000ed98                    \n"
-        " xRBARConst2: .word 0xe000ed9c                   \n"
-    );
-}
+    void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                 \n"
+            "                                                 \n"
+            " program_mpu_first_task:                         \n"
+            "    ldr r2, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB. */
+            "                                                 \n"
+            "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
+            "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
+            "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
+            "    str r2, [r1]                                 \n" /* Disable MPU. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
+            "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
+            "    ldr r2, xMAIR0Const2                         \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    str r1, [r2]                                 \n" /* Program MAIR0. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
+            "    ldr r1, xRNRConst2                           \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "                                                 \n"
+            "    movs r3, #4                                  \n" /* r3 = 4. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 4. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "                                                 \n"
+            #if ( configTOTAL_MPU_REGIONS == 16 )
+                "    movs r3, #8                                  \n" /* r3 = 8. */
+                "    str r3, [r1]                                 \n" /* Program RNR = 8. */
+                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+                "    movs r3, #12                                 \n" /* r3 = 12. */
+                "    str r3, [r1]                                 \n" /* Program RNR = 12. */
+                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            #endif /* configTOTAL_MPU_REGIONS == 16 */
+            "                                                 \n"
+            "   ldr r1, xMPUCTRLConst2                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
+            "   orr r2, #1                                    \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
+            "   str r2, [r1]                                  \n" /* Enable MPU. */
+            "   dsb                                           \n" /* Force memory writes before continuing. */
+            "                                                 \n"
+            " restore_context_first_task:                     \n"
+            "    ldr r2, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB.*/
+            "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
+            "                                                 \n"
+            " restore_special_regs_first_task:                \n"
+            "    ldmdb r1!, {r2-r4, lr}                       \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
+            "    msr psp, r2                                  \n"
+            "    msr psplim, r3                               \n"
+            "    msr control, r4                              \n"
+            "                                                 \n"
+            " restore_general_regs_first_task:                \n"
+            "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
+            "    stmia r2!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
+            "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 restored. */
+            "                                                 \n"
+            " restore_context_done_first_task:                \n"
+            "    str r1, [r0]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
+            "    mov r0, #0                                   \n"
+            "    msr basepri, r0                              \n" /* Ensure that interrupts are enabled when the first task starts. */
+            "    bx lr                                        \n"
+            "                                                 \n"
+            " .align 4                                        \n"
+            " pxCurrentTCBConst2: .word pxCurrentTCB          \n"
+            " xMPUCTRLConst2: .word 0xe000ed94                \n"
+            " xMAIR0Const2: .word 0xe000edc0                  \n"
+            " xRNRConst2: .word 0xe000ed98                    \n"
+            " xRBARConst2: .word 0xe000ed9c                   \n"
+        );
+    }
 
 #else /* configENABLE_MPU */
 
-void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "   .syntax unified                                 \n"
-        "                                                   \n"
-        "   ldr  r2, pxCurrentTCBConst2                     \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr  r1, [r2]                                   \n"/* Read pxCurrentTCB. */
-        "   ldr  r0, [r1]                                   \n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
-        "                                                   \n"
-        "   ldm  r0!, {r1-r2}                               \n"/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
-        "   msr  psplim, r1                                 \n"/* Set this task's PSPLIM value. */
-        "   movs r1, #2                                     \n"/* r1 = 2. */
-        "   msr  CONTROL, r1                                \n"/* Switch to use PSP in the thread mode. */
-        "   adds r0, #32                                    \n"/* Discard everything up to r0. */
-        "   msr  psp, r0                                    \n"/* This is now the new top of stack to use in the task. */
-        "   isb                                             \n"
-        "   mov  r0, #0                                     \n"
-        "   msr  basepri, r0                                \n"/* Ensure that interrupts are enabled when the first task starts. */
-        "   bx   r2                                         \n"/* Finally, branch to EXC_RETURN. */
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "pxCurrentTCBConst2: .word pxCurrentTCB             \n"
-    );
-}
+    void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            "   .syntax unified                                 \n"
+            "                                                   \n"
+            "   ldr  r2, pxCurrentTCBConst2                     \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr  r1, [r2]                                   \n" /* Read pxCurrentTCB. */
+            "   ldr  r0, [r1]                                   \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+            "                                                   \n"
+            "   ldm  r0!, {r1-r2}                               \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
+            "   msr  psplim, r1                                 \n" /* Set this task's PSPLIM value. */
+            "   movs r1, #2                                     \n" /* r1 = 2. */
+            "   msr  CONTROL, r1                                \n" /* Switch to use PSP in the thread mode. */
+            "   adds r0, #32                                    \n" /* Discard everything up to r0. */
+            "   msr  psp, r0                                    \n" /* This is now the new top of stack to use in the task. */
+            "   isb                                             \n"
+            "   mov  r0, #0                                     \n"
+            "   msr  basepri, r0                                \n" /* Ensure that interrupts are enabled when the first task starts. */
+            "   bx   r2                                         \n" /* Finally, branch to EXC_RETURN. */
+            "                                                   \n"
+            "   .align 4                                        \n"
+            "pxCurrentTCBConst2: .word pxCurrentTCB             \n"
+        );
+    }
 
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
@@ -157,12 +157,12 @@ BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs r0, control                                 \n"/* r0 = CONTROL. */
-        "   tst r0, #1                                      \n"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+        "   mrs r0, control                                 \n" /* r0 = CONTROL. */
+        "   tst r0, #1                                      \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
         "   ite ne                                          \n"
-        "   movne r0, #0                                    \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
-        "   moveq r0, #1                                    \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
-        "   bx lr                                           \n"/* Return. */
+        "   movne r0, #0                                    \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+        "   moveq r0, #1                                    \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+        "   bx lr                                           \n" /* Return. */
         "                                                   \n"
         "   .align 4                                        \n"
         ::: "r0", "memory"
@@ -176,10 +176,10 @@ void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs  r0, control                                \n"/* Read the CONTROL register. */
-        "   bic r0, #1                                      \n"/* Clear the bit 0. */
-        "   msr  control, r0                                \n"/* Write back the new CONTROL value. */
-        "   bx lr                                           \n"/* Return to the caller. */
+        "   mrs  r0, control                                \n" /* Read the CONTROL register. */
+        "   bic r0, #1                                      \n" /* Clear the bit 0. */
+        "   msr  control, r0                                \n" /* Write back the new CONTROL value. */
+        "   bx lr                                           \n" /* Return to the caller. */
         ::: "r0", "memory"
     );
 }
@@ -191,10 +191,10 @@ void vResetPrivilege( void ) /* __attribute__ (( naked )) */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs r0, control                                 \n"/* r0 = CONTROL. */
-        "   orr r0, #1                                      \n"/* r0 = r0 | 1. */
-        "   msr control, r0                                 \n"/* CONTROL = r0. */
-        "   bx lr                                           \n"/* Return to the caller. */
+        "   mrs r0, control                                 \n" /* r0 = CONTROL. */
+        "   orr r0, #1                                      \n" /* r0 = r0 | 1. */
+        "   msr control, r0                                 \n" /* CONTROL = r0. */
+        "   bx lr                                           \n" /* Return to the caller. */
         ::: "r0", "memory"
     );
 }
@@ -206,15 +206,15 @@ void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   ldr r0, xVTORConst                              \n"/* Use the NVIC offset register to locate the stack. */
-        "   ldr r0, [r0]                                    \n"/* Read the VTOR register which gives the address of vector table. */
-        "   ldr r0, [r0]                                    \n"/* The first entry in vector table is stack pointer. */
-        "   msr msp, r0                                     \n"/* Set the MSP back to the start of the stack. */
-        "   cpsie i                                         \n"/* Globally enable interrupts. */
+        "   ldr r0, xVTORConst                              \n" /* Use the NVIC offset register to locate the stack. */
+        "   ldr r0, [r0]                                    \n" /* Read the VTOR register which gives the address of vector table. */
+        "   ldr r0, [r0]                                    \n" /* The first entry in vector table is stack pointer. */
+        "   msr msp, r0                                     \n" /* Set the MSP back to the start of the stack. */
+        "   cpsie i                                         \n" /* Globally enable interrupts. */
         "   cpsie f                                         \n"
         "   dsb                                             \n"
         "   isb                                             \n"
-        "   svc %0                                          \n"/* System call to start the first task. */
+        "   svc %0                                          \n" /* System call to start the first task. */
         "   nop                                             \n"
         "                                                   \n"
         "   .align 4                                        \n"
@@ -230,12 +230,12 @@ uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCT
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs r0, basepri                                 \n"/* r0 = basepri. Return original basepri value. */
-        "   mov r1, %0                                      \n"/* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        "   msr basepri, r1                                 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        "   mrs r0, basepri                                 \n" /* r0 = basepri. Return original basepri value. */
+        "   mov r1, %0                                      \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        "   msr basepri, r1                                 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
         "   dsb                                             \n"
         "   isb                                             \n"
-        "   bx lr                                           \n"/* Return. */
+        "   bx lr                                           \n" /* Return. */
         ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
     );
 }
@@ -247,10 +247,10 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   msr basepri, r0                                 \n"/* basepri = ulMask. */
+        "   msr basepri, r0                                 \n" /* basepri = ulMask. */
         "   dsb                                             \n"
         "   isb                                             \n"
-        "   bx lr                                           \n"/* Return. */
+        "   bx lr                                           \n" /* Return. */
         ::: "memory"
     );
 }
@@ -258,246 +258,246 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
 
 #if ( configENABLE_MPU == 1 )
 
-void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        " .syntax unified                                 \n"
-        "                                                 \n"
-        " ldr r2, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        " ldr r0, [r2]                                    \n" /* r0 = pxCurrentTCB. */
-        " ldr r1, [r0]                                    \n" /* r1 = Location in TCB where the context should be saved. */
-        " mrs r2, psp                                     \n" /* r2 = PSP. */
-        "                                                 \n"
-        " save_general_regs:                              \n"
-    #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-        "    add r2, r2, #0x20                            \n" /* Move r2 to location where s0 is saved. */
-        "    tst lr, #0x10                                \n"
-        "    ittt eq                                      \n"
-        "    vstmiaeq r1!, {s16-s31}                      \n" /* Store s16-s31. */
-        "    vldmiaeq r2, {s0-s16}                        \n" /* Copy hardware saved FP context into s0-s16. */
-        "    vstmiaeq r1!, {s0-s16}                       \n" /* Store hardware saved FP context. */
-        "    sub r2, r2, #0x20                            \n" /* Set r2 back to the location of hardware saved context. */
-    #endif /* configENABLE_FPU || configENABLE_MVE */
-        "                                                 \n"
-        "    stmia r1!, {r4-r11}                          \n" /* Store r4-r11. */
-        "    ldmia r2, {r4-r11}                           \n" /* Copy the hardware saved context into r4-r11. */
-        "    stmia r1!, {r4-r11}                          \n" /* Store the hardware saved context. */
-        "                                                 \n"
-        " save_special_regs:                              \n"
-        "    mrs r3, psplim                               \n" /* r3 = PSPLIM. */
-        "    mrs r4, control                              \n" /* r4 = CONTROL. */
-        "    stmia r1!, {r2-r4, lr}                       \n" /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
-        "    str r1, [r0]                                 \n" /* Save the location from where the context should be restored as the first member of TCB. */
-        "                                                 \n"
-        " select_next_task:                               \n"
-        "    mov r0, %0                                   \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
-        "    msr basepri, r0                              \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        "    dsb                                          \n"
-        "    isb                                          \n"
-        "    bl vTaskSwitchContext                        \n"
-        "    mov r0, #0                                   \n" /* r0 = 0. */
-        "    msr basepri, r0                              \n" /* Enable interrupts. */
-        "                                                 \n"
-        " program_mpu:                                    \n"
-        "    ldr r2, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB. */
-        "                                                 \n"
-        "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-        "    ldr r1, xMPUCTRLConst                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
-        "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
-        "    str r2, [r1]                                 \n" /* Disable MPU. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
-        "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-        "    ldr r2, xMAIR0Const                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-        "    str r1, [r2]                                 \n" /* Program MAIR0. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-        "    ldr r1, xRNRConst                            \n" /* r1 = 0xe000ed98 [Location of RNR]. */
-        "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "                                                 \n"
-        "    movs r3, #4                                  \n" /* r3 = 4. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 4. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-        "                                                 \n"
-    #if ( configTOTAL_MPU_REGIONS == 16 )
-        "    movs r3, #8                                  \n" /* r3 = 8. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 8. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-        "    movs r3, #12                                 \n" /* r3 = 12. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 12. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-    #endif /* configTOTAL_MPU_REGIONS == 16 */
-        "                                                 \n"
-        "   ldr r1, xMPUCTRLConst                         \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
-        "   orr r2, #1                                    \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
-        "   str r2, [r1]                                  \n" /* Enable MPU. */
-        "   dsb                                           \n" /* Force memory writes before continuing. */
-        "                                                 \n"
-        " restore_context:                                \n"
-        "    ldr r2, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB.*/
-        "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
-        "                                                 \n"
-        " restore_special_regs:                           \n"
-        "    ldmdb r1!, {r2-r4, lr}                       \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
-        "    msr psp, r2                                  \n"
-        "    msr psplim, r3                               \n"
-        "    msr control, r4                              \n"
-        "                                                 \n"
-        " restore_general_regs:                           \n"
-        "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
-        "    stmia r2!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
-        "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 restored. */
-    #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-        "    tst lr, #0x10                                \n"
-        "    ittt eq                                      \n"
-        "    vldmdbeq r1!, {s0-s16}                       \n" /* s0-s16 contain hardware saved FP context. */
-        "    vstmiaeq r2!, {s0-s16}                       \n" /* Copy hardware saved FP context on the task stack. */
-        "    vldmdbeq r1!, {s16-s31}                      \n" /* Restore s16-s31. */
-    #endif /* configENABLE_FPU || configENABLE_MVE */
-        "                                                 \n"
-        " restore_context_done:                           \n"
-        "    str r1, [r0]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
-        "    bx lr                                        \n"
-        "                                                 \n"
-        " .align 4                                        \n"
-        " pxCurrentTCBConst: .word pxCurrentTCB           \n"
-        " xMPUCTRLConst: .word 0xe000ed94                 \n"
-        " xMAIR0Const: .word 0xe000edc0                   \n"
-        " xRNRConst: .word 0xe000ed98                     \n"
-        " xRBARConst: .word 0xe000ed9c                    \n"
-        ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
-    );
-}
+    void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                 \n"
+            "                                                 \n"
+            " ldr r2, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            " ldr r0, [r2]                                    \n" /* r0 = pxCurrentTCB. */
+            " ldr r1, [r0]                                    \n" /* r1 = Location in TCB where the context should be saved. */
+            " mrs r2, psp                                     \n" /* r2 = PSP. */
+            "                                                 \n"
+            " save_general_regs:                              \n"
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+                "    add r2, r2, #0x20                            \n" /* Move r2 to location where s0 is saved. */
+                "    tst lr, #0x10                                \n"
+                "    ittt eq                                      \n"
+                "    vstmiaeq r1!, {s16-s31}                      \n" /* Store s16-s31. */
+                "    vldmiaeq r2, {s0-s16}                        \n" /* Copy hardware saved FP context into s0-s16. */
+                "    vstmiaeq r1!, {s0-s16}                       \n" /* Store hardware saved FP context. */
+                "    sub r2, r2, #0x20                            \n" /* Set r2 back to the location of hardware saved context. */
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+            "                                                 \n"
+            "    stmia r1!, {r4-r11}                          \n" /* Store r4-r11. */
+            "    ldmia r2, {r4-r11}                           \n" /* Copy the hardware saved context into r4-r11. */
+            "    stmia r1!, {r4-r11}                          \n" /* Store the hardware saved context. */
+            "                                                 \n"
+            " save_special_regs:                              \n"
+            "    mrs r3, psplim                               \n" /* r3 = PSPLIM. */
+            "    mrs r4, control                              \n" /* r4 = CONTROL. */
+            "    stmia r1!, {r2-r4, lr}                       \n" /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
+            "    str r1, [r0]                                 \n" /* Save the location from where the context should be restored as the first member of TCB. */
+            "                                                 \n"
+            " select_next_task:                               \n"
+            "    mov r0, %0                                   \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
+            "    msr basepri, r0                              \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+            "    dsb                                          \n"
+            "    isb                                          \n"
+            "    bl vTaskSwitchContext                        \n"
+            "    mov r0, #0                                   \n" /* r0 = 0. */
+            "    msr basepri, r0                              \n" /* Enable interrupts. */
+            "                                                 \n"
+            " program_mpu:                                    \n"
+            "    ldr r2, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB. */
+            "                                                 \n"
+            "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
+            "    ldr r1, xMPUCTRLConst                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
+            "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
+            "    str r2, [r1]                                 \n" /* Disable MPU. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
+            "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
+            "    ldr r2, xMAIR0Const                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    str r1, [r2]                                 \n" /* Program MAIR0. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
+            "    ldr r1, xRNRConst                            \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "                                                 \n"
+            "    movs r3, #4                                  \n" /* r3 = 4. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 4. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "                                                 \n"
+            #if ( configTOTAL_MPU_REGIONS == 16 )
+                "    movs r3, #8                                  \n" /* r3 = 8. */
+                "    str r3, [r1]                                 \n" /* Program RNR = 8. */
+                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+                "    movs r3, #12                                 \n" /* r3 = 12. */
+                "    str r3, [r1]                                 \n" /* Program RNR = 12. */
+                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            #endif /* configTOTAL_MPU_REGIONS == 16 */
+            "                                                 \n"
+            "   ldr r1, xMPUCTRLConst                         \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
+            "   orr r2, #1                                    \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
+            "   str r2, [r1]                                  \n" /* Enable MPU. */
+            "   dsb                                           \n" /* Force memory writes before continuing. */
+            "                                                 \n"
+            " restore_context:                                \n"
+            "    ldr r2, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB.*/
+            "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
+            "                                                 \n"
+            " restore_special_regs:                           \n"
+            "    ldmdb r1!, {r2-r4, lr}                       \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
+            "    msr psp, r2                                  \n"
+            "    msr psplim, r3                               \n"
+            "    msr control, r4                              \n"
+            "                                                 \n"
+            " restore_general_regs:                           \n"
+            "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
+            "    stmia r2!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
+            "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 restored. */
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+                "    tst lr, #0x10                                \n"
+                "    ittt eq                                      \n"
+                "    vldmdbeq r1!, {s0-s16}                       \n" /* s0-s16 contain hardware saved FP context. */
+                "    vstmiaeq r2!, {s0-s16}                       \n" /* Copy hardware saved FP context on the task stack. */
+                "    vldmdbeq r1!, {s16-s31}                      \n" /* Restore s16-s31. */
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+            "                                                 \n"
+            " restore_context_done:                           \n"
+            "    str r1, [r0]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
+            "    bx lr                                        \n"
+            "                                                 \n"
+            " .align 4                                        \n"
+            " pxCurrentTCBConst: .word pxCurrentTCB           \n"
+            " xMPUCTRLConst: .word 0xe000ed94                 \n"
+            " xMAIR0Const: .word 0xe000edc0                   \n"
+            " xRNRConst: .word 0xe000ed98                     \n"
+            " xRBARConst: .word 0xe000ed9c                    \n"
+            ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+        );
+    }
 
 #else /* configENABLE_MPU */
 
-void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "   .syntax unified                                 \n"
-        "                                                   \n"
-        "   mrs r0, psp                                     \n"/* Read PSP in r0. */
-        "                                                   \n"
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-            "   tst lr, #0x10                                   \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
-            "   it eq                                           \n"
-            "   vstmdbeq r0!, {s16-s31}                         \n"/* Store the additional FP context registers which are not saved automatically. */
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-        "                                                   \n"
-        "   mrs r2, psplim                                  \n"/* r2 = PSPLIM. */
-        "   mov r3, lr                                      \n"/* r3 = LR/EXC_RETURN. */
-        "   stmdb r0!, {r2-r11}                             \n"/* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */
-        "                                                   \n"
-        "   ldr r2, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r2]                                    \n"/* Read pxCurrentTCB. */
-        "   str r0, [r1]                                    \n"/* Save the new top of stack in TCB. */
-        "                                                   \n"
-        "   mov r0, %0                                      \n"/* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
-        "   msr basepri, r0                                 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        "   dsb                                             \n"
-        "   isb                                             \n"
-        "   bl vTaskSwitchContext                           \n"
-        "   mov r0, #0                                      \n"/* r0 = 0. */
-        "   msr basepri, r0                                 \n"/* Enable interrupts. */
-        "                                                   \n"
-        "   ldr r2, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r2]                                    \n"/* Read pxCurrentTCB. */
-        "   ldr r0, [r1]                                    \n"/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
-        "                                                   \n"
-        "   ldmia r0!, {r2-r11}                             \n"/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
-        "                                                   \n"
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-            "   tst r3, #0x10                                   \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
-            "   it eq                                           \n"
-            "   vldmiaeq r0!, {s16-s31}                         \n"/* Restore the additional FP context registers which are not restored automatically. */
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-        "                                                   \n"
-        "   msr psplim, r2                                  \n"/* Restore the PSPLIM register value for the task. */
-        "   msr psp, r0                                     \n"/* Remember the new top of stack for the task. */
-        "   bx r3                                           \n"
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "pxCurrentTCBConst: .word pxCurrentTCB              \n"
-        ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
-    );
-}
+    void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            "   .syntax unified                                 \n"
+            "                                                   \n"
+            "   mrs r0, psp                                     \n" /* Read PSP in r0. */
+            "                                                   \n"
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+                "   tst lr, #0x10                                   \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+                "   it eq                                           \n"
+                "   vstmdbeq r0!, {s16-s31}                         \n" /* Store the additional FP context registers which are not saved automatically. */
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+            "                                                   \n"
+            "   mrs r2, psplim                                  \n" /* r2 = PSPLIM. */
+            "   mov r3, lr                                      \n" /* r3 = LR/EXC_RETURN. */
+            "   stmdb r0!, {r2-r11}                             \n" /* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */
+            "                                                   \n"
+            "   ldr r2, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r1, [r2]                                    \n" /* Read pxCurrentTCB. */
+            "   str r0, [r1]                                    \n" /* Save the new top of stack in TCB. */
+            "                                                   \n"
+            "   mov r0, %0                                      \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
+            "   msr basepri, r0                                 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+            "   dsb                                             \n"
+            "   isb                                             \n"
+            "   bl vTaskSwitchContext                           \n"
+            "   mov r0, #0                                      \n" /* r0 = 0. */
+            "   msr basepri, r0                                 \n" /* Enable interrupts. */
+            "                                                   \n"
+            "   ldr r2, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r1, [r2]                                    \n" /* Read pxCurrentTCB. */
+            "   ldr r0, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
+            "                                                   \n"
+            "   ldmia r0!, {r2-r11}                             \n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
+            "                                                   \n"
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+                "   tst r3, #0x10                                   \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+                "   it eq                                           \n"
+                "   vldmiaeq r0!, {s16-s31}                         \n" /* Restore the additional FP context registers which are not restored automatically. */
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+            "                                                   \n"
+            "   msr psplim, r2                                  \n" /* Restore the PSPLIM register value for the task. */
+            "   msr psp, r0                                     \n" /* Remember the new top of stack for the task. */
+            "   bx r3                                           \n"
+            "                                                   \n"
+            "   .align 4                                        \n"
+            "pxCurrentTCBConst: .word pxCurrentTCB              \n"
+            ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+        );
+    }
 
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-   __asm volatile
-    (
-        ".syntax unified                \n"
-        ".extern vPortSVCHandler_C      \n"
-        ".extern vSystemCallEnter       \n"
-        ".extern vSystemCallEnter_1     \n"
-        ".extern vSystemCallExit        \n"
-        "                               \n"
-        "tst lr, #4                     \n"
-        "ite eq                         \n"
-        "mrseq r0, msp                  \n"
-        "mrsne r0, psp                  \n"
-        "                               \n"
-        "ldr r1, [r0, #24]              \n"
-        "ldrb r2, [r1, #-2]             \n"
-        "cmp r2, %0                     \n"
-        "beq syscall_enter              \n"
-        "cmp r2, %1                     \n"
-        "beq syscall_enter_1            \n"
-        "cmp r2, %2                     \n"
-        "beq syscall_exit               \n"
-        "b vPortSVCHandler_C            \n"
-        "                               \n"
-        "syscall_enter:                 \n"
-        "    mov r1, lr                 \n"
-        "    b vSystemCallEnter         \n"
-        "                               \n"
-        "syscall_enter_1:               \n"
-        "    mov r1, lr                 \n"
-        "    b vSystemCallEnter_1       \n"
-        "                               \n"
-        "syscall_exit:                  \n"
-        "    mov r1, lr                 \n"
-        "    b vSystemCallExit          \n"
-        "                               \n"
-        : /* No outputs. */
-        :"i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT )
-        : "r0", "r1", "r2", "memory"
-    );
-}
+    void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            ".syntax unified                \n"
+            ".extern vPortSVCHandler_C      \n"
+            ".extern vSystemCallEnter       \n"
+            ".extern vSystemCallEnter_1     \n"
+            ".extern vSystemCallExit        \n"
+            "                               \n"
+            "tst lr, #4                     \n"
+            "ite eq                         \n"
+            "mrseq r0, msp                  \n"
+            "mrsne r0, psp                  \n"
+            "                               \n"
+            "ldr r1, [r0, #24]              \n"
+            "ldrb r2, [r1, #-2]             \n"
+            "cmp r2, %0                     \n"
+            "beq syscall_enter              \n"
+            "cmp r2, %1                     \n"
+            "beq syscall_enter_1            \n"
+            "cmp r2, %2                     \n"
+            "beq syscall_exit               \n"
+            "b vPortSVCHandler_C            \n"
+            "                               \n"
+            "syscall_enter:                 \n"
+            "    mov r1, lr                 \n"
+            "    b vSystemCallEnter         \n"
+            "                               \n"
+            "syscall_enter_1:               \n"
+            "    mov r1, lr                 \n"
+            "    b vSystemCallEnter_1       \n"
+            "                               \n"
+            "syscall_exit:                  \n"
+            "    mov r1, lr                 \n"
+            "    b vSystemCallExit          \n"
+            "                               \n"
+            : /* No outputs. */
+            : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT )
+            : "r0", "r1", "r2", "memory"
+        );
+    }
 
 #else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
-void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "   .syntax unified                                 \n"
-        "                                                   \n"
-        "   tst lr, #4                                      \n"
-        "   ite eq                                          \n"
-        "   mrseq r0, msp                                   \n"
-        "   mrsne r0, psp                                   \n"
-        "   ldr r1, svchandler_address_const                \n"
-        "   bx r1                                           \n"
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "svchandler_address_const: .word vPortSVCHandler_C  \n"
-    );
-}
+    void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            "   .syntax unified                                 \n"
+            "                                                   \n"
+            "   tst lr, #4                                      \n"
+            "   ite eq                                          \n"
+            "   mrseq r0, msp                                   \n"
+            "   mrsne r0, psp                                   \n"
+            "   ldr r1, svchandler_address_const                \n"
+            "   bx r1                                           \n"
+            "                                                   \n"
+            "   .align 4                                        \n"
+            "svchandler_address_const: .word vPortSVCHandler_C  \n"
+        );
+    }
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h
index 428d38f0a..227327ac8 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h
@@ -48,9 +48,9 @@
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME                       "Cortex-M33"
-#define portHAS_ARMV8M_MAIN_EXTENSION       1
-#define portDONT_DISCARD                    __attribute__( ( used ) )
+#define portARCH_NAME                    "Cortex-M33"
+#define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
 /* ARMv8-M common port configurations. */
@@ -60,8 +60,8 @@
 /**
  * @brief Critical section management.
  */
-#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()
-#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )
+#define portDISABLE_INTERRUPTS()    ulSetInterruptMask()
+#define portENABLE_INTERRUPTS()     vClearInterruptMask( 0 )
 /*-----------------------------------------------------------*/
 
 /* *INDENT-OFF* */
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM35P/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM35P/portmacro.h
index 6e4fe5a3d..66fa2056d 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM35P/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM35P/portmacro.h
@@ -48,9 +48,9 @@
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME                       "Cortex-M35P"
-#define portHAS_ARMV8M_MAIN_EXTENSION       1
-#define portDONT_DISCARD                    __attribute__( ( used ) )
+#define portARCH_NAME                    "Cortex-M35P"
+#define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
 /* ARMv8-M common port configurations. */
@@ -60,8 +60,8 @@
 /**
  * @brief Critical section management.
  */
-#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()
-#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )
+#define portDISABLE_INTERRUPTS()    ulSetInterruptMask()
+#define portENABLE_INTERRUPTS()     vClearInterruptMask( 0 )
 /*-----------------------------------------------------------*/
 
 /* *INDENT-OFF* */
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM55/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM55/portmacro.h
index cce022882..7b011b5b5 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM55/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM55/portmacro.h
@@ -53,9 +53,9 @@
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME                       "Cortex-M55"
-#define portHAS_ARMV8M_MAIN_EXTENSION       1
-#define portDONT_DISCARD                    __attribute__( ( used ) )
+#define portARCH_NAME                    "Cortex-M55"
+#define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
 /* ARMv8-M common port configurations. */
@@ -65,8 +65,8 @@
 /**
  * @brief Critical section management.
  */
-#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()
-#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )
+#define portDISABLE_INTERRUPTS()    ulSetInterruptMask()
+#define portENABLE_INTERRUPTS()     vClearInterruptMask( 0 )
 /*-----------------------------------------------------------*/
 
 /* *INDENT-OFF* */
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM85/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM85/portmacro.h
index d14448927..a6fda8a88 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM85/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM85/portmacro.h
@@ -53,9 +53,9 @@
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME                       "Cortex-M85"
-#define portHAS_ARMV8M_MAIN_EXTENSION       1
-#define portDONT_DISCARD                    __attribute__( ( used ) )
+#define portARCH_NAME                    "Cortex-M85"
+#define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
 /* ARMv8-M common port configurations. */
@@ -65,8 +65,8 @@
 /**
  * @brief Critical section management.
  */
-#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()
-#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )
+#define portDISABLE_INTERRUPTS()    ulSetInterruptMask()
+#define portENABLE_INTERRUPTS()     vClearInterruptMask( 0 )
 /*-----------------------------------------------------------*/
 
 /* *INDENT-OFF* */
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h
index 76ba7172e..e426f5b9a 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h
@@ -48,9 +48,9 @@
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME                       "Cortex-M23"
-#define portHAS_ARMV8M_MAIN_EXTENSION       0
-#define portDONT_DISCARD                    __root
+#define portARCH_NAME                    "Cortex-M23"
+#define portHAS_ARMV8M_MAIN_EXTENSION    0
+#define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
 /* ARMv8-M common port configurations. */
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h
index 76ba7172e..e426f5b9a 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h
@@ -48,9 +48,9 @@
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME                       "Cortex-M23"
-#define portHAS_ARMV8M_MAIN_EXTENSION       0
-#define portDONT_DISCARD                    __root
+#define portARCH_NAME                    "Cortex-M23"
+#define portHAS_ARMV8M_MAIN_EXTENSION    0
+#define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
 /* ARMv8-M common port configurations. */
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h
index 145f5246e..a707fc658 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h
@@ -48,12 +48,12 @@
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME                       "Cortex-M33"
-#define portHAS_ARMV8M_MAIN_EXTENSION       1
-#define portDONT_DISCARD                    __root
+#define portARCH_NAME                    "Cortex-M33"
+#define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
-#if( configTOTAL_MPU_REGIONS == 16 )
+#if ( configTOTAL_MPU_REGIONS == 16 )
     #error 16 MPU regions are not yet supported for this port.
 #endif
 /*-----------------------------------------------------------*/
@@ -65,8 +65,8 @@
 /**
  * @brief Critical section management.
  */
-#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()
-#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )
+#define portDISABLE_INTERRUPTS()    ulSetInterruptMask()
+#define portENABLE_INTERRUPTS()     vClearInterruptMask( 0 )
 /*-----------------------------------------------------------*/
 
 /* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h
index 445f0765a..64d39e3b9 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h
@@ -48,16 +48,16 @@
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME                       "Cortex-M33"
-#define portHAS_ARMV8M_MAIN_EXTENSION       1
-#define portDONT_DISCARD                    __root
+#define portARCH_NAME                    "Cortex-M33"
+#define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
 /* ARMv8-M common port configurations. */
 #include "portmacrocommon.h"
 /*-----------------------------------------------------------*/
 
-#if( configTOTAL_MPU_REGIONS == 16 )
+#if ( configTOTAL_MPU_REGIONS == 16 )
     #error 16 MPU regions are not yet supported for this port.
 #endif
 /*-----------------------------------------------------------*/
@@ -65,8 +65,8 @@
 /**
  * @brief Critical section management.
  */
-#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()
-#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )
+#define portDISABLE_INTERRUPTS()    ulSetInterruptMask()
+#define portENABLE_INTERRUPTS()     vClearInterruptMask( 0 )
 /*-----------------------------------------------------------*/
 
 /* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM35P/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM35P/portmacro.h
index 5669c1f60..82bfaeb79 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM35P/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM35P/portmacro.h
@@ -48,16 +48,16 @@
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME                       "Cortex-M35P"
-#define portHAS_ARMV8M_MAIN_EXTENSION       1
-#define portDONT_DISCARD                    __root
+#define portARCH_NAME                    "Cortex-M35P"
+#define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
 /* ARMv8-M common port configurations. */
 #include "portmacrocommon.h"
 /*-----------------------------------------------------------*/
 
-#if( configTOTAL_MPU_REGIONS == 16 )
+#if ( configTOTAL_MPU_REGIONS == 16 )
     #error 16 MPU regions are not yet supported for this port.
 #endif
 /*-----------------------------------------------------------*/
@@ -65,8 +65,8 @@
 /**
  * @brief Critical section management.
  */
-#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()
-#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )
+#define portDISABLE_INTERRUPTS()    ulSetInterruptMask()
+#define portENABLE_INTERRUPTS()     vClearInterruptMask( 0 )
 /*-----------------------------------------------------------*/
 
 /* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM55/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM55/portmacro.h
index 10596e8e5..1338d25be 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM55/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM55/portmacro.h
@@ -53,16 +53,16 @@
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME                       "Cortex-M55"
-#define portHAS_ARMV8M_MAIN_EXTENSION       1
-#define portDONT_DISCARD                    __root
+#define portARCH_NAME                    "Cortex-M55"
+#define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
 /* ARMv8-M common port configurations. */
 #include "portmacrocommon.h"
 /*-----------------------------------------------------------*/
 
-#if( configTOTAL_MPU_REGIONS == 16 )
+#if ( configTOTAL_MPU_REGIONS == 16 )
     #error 16 MPU regions are not yet supported for this port.
 #endif
 /*-----------------------------------------------------------*/
@@ -70,8 +70,8 @@
 /**
  * @brief Critical section management.
  */
-#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()
-#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )
+#define portDISABLE_INTERRUPTS()    ulSetInterruptMask()
+#define portENABLE_INTERRUPTS()     vClearInterruptMask( 0 )
 /*-----------------------------------------------------------*/
 
 /* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM85/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM85/portmacro.h
index 374150262..cffcb20d9 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM85/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM85/portmacro.h
@@ -53,16 +53,16 @@
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME                       "Cortex-M85"
-#define portHAS_ARMV8M_MAIN_EXTENSION       1
-#define portDONT_DISCARD                    __root
+#define portARCH_NAME                    "Cortex-M85"
+#define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
 /* ARMv8-M common port configurations. */
 #include "portmacrocommon.h"
 /*-----------------------------------------------------------*/
 
-#if( configTOTAL_MPU_REGIONS == 16 )
+#if ( configTOTAL_MPU_REGIONS == 16 )
     #error 16 MPU regions are not yet supported for this port.
 #endif
 /*-----------------------------------------------------------*/
@@ -70,8 +70,8 @@
 /**
  * @brief Critical section management.
  */
-#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()
-#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )
+#define portDISABLE_INTERRUPTS()    ulSetInterruptMask()
+#define portENABLE_INTERRUPTS()     vClearInterruptMask( 0 )
 /*-----------------------------------------------------------*/
 
 /* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
diff --git a/portable/ARMv8M/non_secure/portmacrocommon.h b/portable/ARMv8M/non_secure/portmacrocommon.h
index e5ffdb48b..62e462a27 100644
--- a/portable/ARMv8M/non_secure/portmacrocommon.h
+++ b/portable/ARMv8M/non_secure/portmacrocommon.h
@@ -81,8 +81,8 @@ typedef unsigned long    UBaseType_t;
     typedef uint32_t     TickType_t;
     #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-     * not need to be guarded with a critical section. */
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
     #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -117,7 +117,7 @@ extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGE
 extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
 
 #if ( configENABLE_TRUSTZONE == 1 )
-    extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize );     /* __attribute__ (( naked )) */
+    extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
     extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
 #endif /* configENABLE_TRUSTZONE */
 
@@ -188,13 +188,13 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Settings to define an MPU region.
-     */
+/**
+ * @brief Settings to define an MPU region.
+ */
     typedef struct MPURegionSettings
     {
-        uint32_t ulRBAR;     /**< RBAR for the region. */
-        uint32_t ulRLAR;     /**< RLAR for the region. */
+        uint32_t ulRBAR; /**< RBAR for the region. */
+        uint32_t ulRLAR; /**< RLAR for the region. */
     } MPURegionSettings_t;
 
     #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
@@ -203,9 +203,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-        /**
-         * @brief System call stack.
-         */
+/**
+ * @brief System call stack.
+ */
         typedef struct SYSTEM_CALL_STACK_INFO
         {
             uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ];
@@ -218,74 +218,74 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
-    /**
-     * @brief MPU settings as stored in the TCB.
-     */
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
     #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
 
-        #if( configENABLE_TRUSTZONE == 1 )
+        #if ( configENABLE_TRUSTZONE == 1 )
 
-            /*
-             * +-----------+---------------+----------+-----------------+------------------------------+-----+
-             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
-             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
-             * +-----------+---------------+----------+-----------------+------------------------------+-----+
-             *
-             * <-----------><--------------><---------><----------------><-----------------------------><---->
-             *      16             16            8               8                     5                   1
-             */
-            #define MAX_CONTEXT_SIZE 54
+/*
+ * +-----------+---------------+----------+-----------------+------------------------------+-----+
+ * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+ * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+ * +-----------+---------------+----------+-----------------+------------------------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><-----------------------------><---->
+ *      16             16            8               8                     5                   1
+ */
+            #define MAX_CONTEXT_SIZE    54
 
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-            /*
-             * +-----------+---------------+----------+-----------------+----------------------+-----+
-             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
-             * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
-             * +-----------+---------------+----------+-----------------+----------------------+-----+
-             *
-             * <-----------><--------------><---------><----------------><---------------------><---->
-             *      16             16            8               8                  4              1
-             */
-            #define MAX_CONTEXT_SIZE 53
+/*
+ * +-----------+---------------+----------+-----------------+----------------------+-----+
+ * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+ * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
+ * +-----------+---------------+----------+-----------------+----------------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><---------------------><---->
+ *      16             16            8               8                  4              1
+ */
+            #define MAX_CONTEXT_SIZE    53
 
         #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
 
     #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-        #if( configENABLE_TRUSTZONE == 1 )
+        #if ( configENABLE_TRUSTZONE == 1 )
 
-            /*
-             * +----------+-----------------+------------------------------+-----+
-             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
-             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
-             * +----------+-----------------+------------------------------+-----+
-             *
-             * <---------><----------------><------------------------------><---->
-             *     8               8                      5                   1
-             */
-            #define MAX_CONTEXT_SIZE 22
+/*
+ * +----------+-----------------+------------------------------+-----+
+ * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+ * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+ * +----------+-----------------+------------------------------+-----+
+ *
+ * <---------><----------------><------------------------------><---->
+ *     8               8                      5                   1
+ */
+            #define MAX_CONTEXT_SIZE    22
 
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-            /*
-             * +----------+-----------------+----------------------+-----+
-             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
-             * |          | PC, xPSR        | EXC_RETURN           |     |
-             * +----------+-----------------+----------------------+-----+
-             *
-             * <---------><----------------><----------------------><---->
-             *     8               8                  4              1
-             */
-            #define MAX_CONTEXT_SIZE 21
+/*
+ * +----------+-----------------+----------------------+-----+
+ * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+ * |          | PC, xPSR        | EXC_RETURN           |     |
+ * +----------+-----------------+----------------------+-----+
+ *
+ * <---------><----------------><----------------------><---->
+ *     8               8                  4              1
+ */
+            #define MAX_CONTEXT_SIZE    21
 
         #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
 
     #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-    /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
-    #define portSTACK_FRAME_HAS_PADDING_FLAG     ( 1UL << 0UL )
-    #define portTASK_IS_PRIVILEGED_FLAG          ( 1UL << 1UL )
+/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
+    #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
+    #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
     typedef struct MPU_SETTINGS
     {
@@ -364,49 +364,49 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-    /**
-     * @brief Allocate a secure context for the task.
-     *
-     * Tasks are not created with a secure context. Any task that is going to call
-     * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
-     * secure context before it calls any secure function.
-     *
-     * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
-     */
+/**
+ * @brief Allocate a secure context for the task.
+ *
+ * Tasks are not created with a secure context. Any task that is going to call
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+ * secure context before it calls any secure function.
+ *
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+ */
     #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
 
-    /**
-     * @brief Called when a task is deleted to delete the task's secure context,
-     * if it has one.
-     *
-     * @param[in] pxTCB The TCB of the task being deleted.
-     */
+/**
+ * @brief Called when a task is deleted to delete the task's secure context,
+ * if it has one.
+ *
+ * @param[in] pxTCB The TCB of the task being deleted.
+ */
     #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
 #endif /* configENABLE_TRUSTZONE */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Checks whether or not the processor is privileged.
-     *
-     * @return 1 if the processor is already privileged, 0 otherwise.
-     */
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
     #define portIS_PRIVILEGED()      xIsPrivileged()
 
-    /**
-     * @brief Raise an SVC request to raise privilege.
-     *
-     * The SVC handler checks that the SVC was raised from a system call and only
-     * then it raises the privilege. If this is called from any other place,
-     * the privilege is not raised.
-     */
+/**
+ * @brief Raise an SVC request to raise privilege.
+ *
+ * The SVC handler checks that the SVC was raised from a system call and only
+ * then it raises the privilege. If this is called from any other place,
+ * the privilege is not raised.
+ */
     #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
 
-    /**
-     * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
-     * register.
-     */
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
     #define portRESET_PRIVILEGE()    vResetPrivilege()
 #else
     #define portIS_PRIVILEGED()
@@ -419,12 +419,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     extern BaseType_t xPortIsTaskPrivileged( void );
 
-    /**
-     * @brief Checks whether or not the calling task is privileged.
-     *
-     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
-     */
-    #define portIS_TASK_PRIVILEGED()      xPortIsTaskPrivileged()
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
+    #define portIS_TASK_PRIVILEGED()    xPortIsTaskPrivileged()
 
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
@@ -439,9 +439,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * based on whether or not Mainline extension is implemented. */
 #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
     #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
-        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
     #else
-        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    0
     #endif
 #endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
 
@@ -450,9 +450,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  */
 #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
 
-    /**
-     * @brief Count the number of leading zeros in a 32-bit value.
-     */
+/**
+ * @brief Count the number of leading zeros in a 32-bit value.
+ */
     static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
     {
         uint32_t ulReturn;
@@ -462,7 +462,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         return ulReturn;
     }
 
-    /* Check the configuration. */
+/* Check the configuration. */
     #if ( configMAX_PRIORITIES > 32 )
         #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
     #endif
@@ -471,16 +471,16 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection.  Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
     #endif
 
-    /**
-     * @brief Store/clear the ready priorities in a bit map.
-     */
-    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+/**
+ * @brief Store/clear the ready priorities in a bit map.
+ */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )      ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )       ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 
-    /**
-     * @brief Get the priority of the highest-priority task that is ready to execute.
-     */
-    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )   uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+/**
+ * @brief Get the priority of the highest-priority task that is ready to execute.
+ */
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
 
 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 /*-----------------------------------------------------------*/
diff --git a/portable/ARMv8M/secure/context/secure_context.c b/portable/ARMv8M/secure/context/secure_context.c
index 0730d574d..7d2171996 100644
--- a/portable/ARMv8M/secure/context/secure_context.c
+++ b/portable/ARMv8M/secure/context/secure_context.c
@@ -65,7 +65,7 @@
  * @brief Maximum number of secure contexts.
  */
 #ifndef secureconfigMAX_SECURE_CONTEXTS
-    #define secureconfigMAX_SECURE_CONTEXTS        8UL
+    #define secureconfigMAX_SECURE_CONTEXTS    8UL
 #endif
 /*-----------------------------------------------------------*/
 
@@ -164,15 +164,15 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
         }
 
         #if ( configENABLE_MPU == 1 )
-            {
-                /* Configure thread mode to use PSP and to be unprivileged. */
-                secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
-            }
+        {
+            /* Configure thread mode to use PSP and to be unprivileged. */
+            secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
+        }
         #else /* configENABLE_MPU */
-            {
-                /* Configure thread mode to use PSP and to be privileged. */
-                secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
-            }
+        {
+            /* Configure thread mode to use PSP and to be privileged. */
+            secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
+        }
         #endif /* configENABLE_MPU */
     }
 }
@@ -219,16 +219,16 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
             if( pucStackMemory != NULL )
             {
                 /* Since stack grows down, the starting point will be the last
-                 * location. Note that this location is next to the last
-                 * allocated byte for stack (excluding the space for seal values)
-                 * because the hardware decrements the stack pointer before
-                 * writing i.e. if stack pointer is 0x2, a push operation will
-                 * decrement the stack pointer to 0x1 and then write at 0x1. */
+                * location. Note that this location is next to the last
+                * allocated byte for stack (excluding the space for seal values)
+                * because the hardware decrements the stack pointer before
+                * writing i.e. if stack pointer is 0x2, a push operation will
+                * decrement the stack pointer to 0x1 and then write at 0x1. */
                 xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize;
 
                 /* Seal the created secure process stack. */
-                *( uint32_t * )( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE;
-                *( uint32_t * )( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE;
+                *( uint32_t * ) ( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE;
+                *( uint32_t * ) ( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE;
 
                 /* The stack cannot go beyond this location. This value is
                  * programmed in the PSPLIM register on context switch.*/
@@ -237,32 +237,32 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
                 xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle;
 
                 #if ( configENABLE_MPU == 1 )
+                {
+                    /* Store the correct CONTROL value for the task on the stack.
+                     * This value is programmed in the CONTROL register on
+                     * context switch. */
+                    pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart;
+                    pulCurrentStackPointer--;
+
+                    if( ulIsTaskPrivileged )
                     {
-                        /* Store the correct CONTROL value for the task on the stack.
-                         * This value is programmed in the CONTROL register on
-                         * context switch. */
-                        pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart;
-                        pulCurrentStackPointer--;
-
-                        if( ulIsTaskPrivileged )
-                        {
-                            *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
-                        }
-                        else
-                        {
-                            *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
-                        }
-
-                        /* Store the current stack pointer. This value is programmed in
-                         * the PSP register on context switch. */
-                        xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+                        *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
                     }
+                    else
+                    {
+                        *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
+                    }
+
+                    /* Store the current stack pointer. This value is programmed in
+                     * the PSP register on context switch. */
+                    xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+                }
                 #else /* configENABLE_MPU */
-                    {
-                        /* Current SP is set to the starting of the stack. This
-                         * value programmed in the PSP register on context switch. */
-                        xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart;
-                    }
+                {
+                    /* Current SP is set to the starting of the stack. This
+                     * value programmed in the PSP register on context switch. */
+                    xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart;
+                }
                 #endif /* configENABLE_MPU */
 
                 /* Ensure to never return 0 as a valid context handle. */
@@ -275,7 +275,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
 }
 /*-----------------------------------------------------------*/
 
-secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle,
+                                                              void * pvTaskHandle )
 {
     uint32_t ulIPSR, ulSecureContextIndex;
 
@@ -306,7 +307,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandl
 }
 /*-----------------------------------------------------------*/
 
-secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle,
+                                                              void * pvTaskHandle )
 {
     uint8_t * pucStackLimit;
     uint32_t ulSecureContextIndex;
@@ -328,7 +330,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandl
 }
 /*-----------------------------------------------------------*/
 
-secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle,
+                                                              void * pvTaskHandle )
 {
     uint8_t * pucStackLimit;
     uint32_t ulSecureContextIndex;
diff --git a/portable/ARMv8M/secure/context/secure_context.h b/portable/ARMv8M/secure/context/secure_context.h
index d0adbaf01..0bf776198 100644
--- a/portable/ARMv8M/secure/context/secure_context.h
+++ b/portable/ARMv8M/secure/context/secure_context.h
@@ -38,12 +38,12 @@
 /**
  * @brief PSP value when no secure context is loaded.
  */
-#define securecontextNO_STACK               0x0
+#define securecontextNO_STACK              0x0
 
 /**
  * @brief Invalid context ID.
  */
-#define securecontextINVALID_CONTEXT_ID     0UL
+#define securecontextINVALID_CONTEXT_ID    0UL
 /*-----------------------------------------------------------*/
 
 /**
@@ -108,7 +108,8 @@ void SecureContext_Init( void );
  * @param[in] xSecureContextHandle Context handle corresponding to the
  * context to be freed.
  */
-void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle,
+                                void * pvTaskHandle );
 
 /**
  * @brief Loads the given context.
@@ -119,7 +120,8 @@ void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void
  * @param[in] xSecureContextHandle Context handle corresponding to the context
  * to be loaded.
  */
-void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle,
+                                void * pvTaskHandle );
 
 /**
  * @brief Saves the given context.
@@ -130,6 +132,7 @@ void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void
  * @param[in] xSecureContextHandle Context handle corresponding to the context
  * to be saved.
  */
-void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle,
+                                void * pvTaskHandle );
 
 #endif /* __SECURE_CONTEXT_H__ */
diff --git a/portable/ARMv8M/secure/heap/secure_heap.c b/portable/ARMv8M/secure/heap/secure_heap.c
index f3b80df54..1ec3bdbdb 100644
--- a/portable/ARMv8M/secure/heap/secure_heap.c
+++ b/portable/ARMv8M/secure/heap/secure_heap.c
@@ -67,7 +67,7 @@
 #define secureheapSIZE_MAX              ( ~( ( size_t ) 0 ) )
 
 /* Check if adding a and b will result in overflow. */
-#define secureheapADD_WILL_OVERFLOW( a, b )         ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) )
+#define secureheapADD_WILL_OVERFLOW( a, b )    ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) )
 
 /* MSB of the xBlockSize member of an BlockLink_t structure is used to track
  * the allocation status of a block.  When MSB of the xBlockSize member of
@@ -397,17 +397,17 @@ void * pvPortMalloc( size_t xWantedSize )
     traceMALLOC( pvReturn, xWantedSize );
 
     #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
+    {
+        if( pvReturn == NULL )
         {
-            if( pvReturn == NULL )
-            {
-                extern void vApplicationMallocFailedHook( void );
-                vApplicationMallocFailedHook();
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
+            extern void vApplicationMallocFailedHook( void );
+            vApplicationMallocFailedHook();
         }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
     #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */
 
     secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );
diff --git a/portable/ARMv8M/secure/init/secure_init.c b/portable/ARMv8M/secure/init/secure_init.c
index dc19ebc7d..b89c5f644 100644
--- a/portable/ARMv8M/secure/init/secure_init.c
+++ b/portable/ARMv8M/secure/init/secure_init.c
@@ -93,7 +93,7 @@ secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )
          * permitted. CP11 should be programmed to the same value as CP10. */
         *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
 
-        /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
+        /* LSPENS = 0 ==> LSPEN is writable from non-secure state. This ensures
          * that we can enable/disable lazy stacking in port.c file. */
         *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK );
 
diff --git a/portable/BCC/16BitDOS/Flsh186/port.c b/portable/BCC/16BitDOS/Flsh186/port.c
index 66b8b7b7b..6697de2f9 100644
--- a/portable/BCC/16BitDOS/Flsh186/port.c
+++ b/portable/BCC/16BitDOS/Flsh186/port.c
@@ -27,22 +27,22 @@
  */
 
 /*
-Changes from V1.00:
-
-    + Call to taskYIELD() from within tick ISR has been replaced by the more
-      efficient portSWITCH_CONTEXT().
-    + ISR function definitions renamed to include the prv prefix.
-
-Changes from V2.6.1
-
-    + Replaced the sUsingPreemption variable with the configUSE_PREEMPTION
-      macro to be consistent with the later ports.
-*/
+ * Changes from V1.00:
+ *
+ + Call to taskYIELD() from within tick ISR has been replaced by the more
+ +    efficient portSWITCH_CONTEXT().
+ + ISR function definitions renamed to include the prv prefix.
+ +
+ + Changes from V2.6.1
+ +
+ + Replaced the sUsingPreemption variable with the configUSE_PREEMPTION
+ +    macro to be consistent with the later ports.
+ */
 
 /*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the Flashlite 186
- * port.
- *----------------------------------------------------------*/
+* Implementation of functions defined in portable.h for the Flashlite 186
+* port.
+*----------------------------------------------------------*/
 
 #include <dos.h>
 #include <stdlib.h>
@@ -54,9 +54,9 @@ Changes from V2.6.1
 
 /*lint -e950 Non ANSI reserved words okay in this file only. */
 
-#define portTIMER_EOI_TYPE      ( 8 )
-#define portRESET_PIC()         portOUTPUT_WORD( ( uint16_t ) 0xff22, portTIMER_EOI_TYPE )
-#define portTIMER_INT_NUMBER    0x12
+#define portTIMER_EOI_TYPE              ( 8 )
+#define portRESET_PIC()    portOUTPUT_WORD( ( uint16_t ) 0xff22, portTIMER_EOI_TYPE )
+#define portTIMER_INT_NUMBER            0x12
 
 #define portTIMER_1_CONTROL_REGISTER    ( ( uint16_t ) 0xff5e )
 #define portTIMER_0_CONTROL_REGISTER    ( ( uint16_t ) 0xff56 )
@@ -69,14 +69,16 @@ static void prvSetTickFrequency( uint32_t ulTickRateHz );
 static void prvExitFunction( void );
 
 /* The ISR used depends on whether the preemptive or cooperative scheduler
-is being used. */
-#if( configUSE_PREEMPTION == 1 )
-    /* Tick service routine used by the scheduler when preemptive scheduling is
-    being used. */
+ * is being used. */
+#if ( configUSE_PREEMPTION == 1 )
+
+/* Tick service routine used by the scheduler when preemptive scheduling is
+ * being used. */
     static void __interrupt __far prvPreemptiveTick( void );
 #else
-    /* Tick service routine used by the scheduler when cooperative scheduling is
-    being used. */
+
+/* Tick service routine used by the scheduler when cooperative scheduling is
+ * being used. */
     static void __interrupt __far prvNonPreemptiveTick( void );
 #endif
 
@@ -89,9 +91,9 @@ static void __interrupt __far prvYieldProcessor( void );
 static BaseType_t xSchedulerRunning = pdFALSE;
 
 /* Points to the original routine installed on the vector we use for manual
-context switches.  This is then used to restore the original routine during
-prvExitFunction(). */
-static void ( __interrupt __far *pxOldSwitchISR )();
+ * context switches.  This is then used to restore the original routine during
+ * prvExitFunction(). */
+static void( __interrupt __far * pxOldSwitchISR )();
 
 /* Used to restore the original DOS context when the scheduler is ended. */
 static jmp_buf xJumpBuf;
@@ -104,14 +106,14 @@ BaseType_t xPortStartScheduler( void )
     /* This is called with interrupts already disabled. */
 
     /* Remember what was on the interrupts we are going to use
-    so we can put them back later if required. */
+     * so we can put them back later if required. */
     pxOldSwitchISR = _dos_getvect( portSWITCH_INT_NUMBER );
 
     /* Put our manual switch (yield) function on a known
-    vector. */
+     * vector. */
     _dos_setvect( portSWITCH_INT_NUMBER, prvYieldProcessor );
 
-    #if( configUSE_PREEMPTION == 1 )
+    #if ( configUSE_PREEMPTION == 1 )
     {
         /* Put our tick switch function on the timer interrupt. */
         _dos_setvect( portTIMER_INT_NUMBER, prvPreemptiveTick );
@@ -144,8 +146,8 @@ BaseType_t xPortStartScheduler( void )
 /*-----------------------------------------------------------*/
 
 /* The ISR used depends on whether the preemptive or cooperative scheduler
-is being used. */
-#if( configUSE_PREEMPTION == 1 )
+ * is being used. */
+#if ( configUSE_PREEMPTION == 1 )
     static void __interrupt __far prvPreemptiveTick( void )
     {
         /* Get the scheduler to update the task states following the tick. */
@@ -158,15 +160,15 @@ is being used. */
         /* Reset the PIC ready for the next time. */
         portRESET_PIC();
     }
-#else
+#else /* if ( configUSE_PREEMPTION == 1 ) */
     static void __interrupt __far prvNonPreemptiveTick( void )
     {
         /* Same as preemptive tick, but the cooperative scheduler is being used
-        so we don't have to switch in the context of the next task. */
+         * so we don't have to switch in the context of the next task. */
         xTaskIncrementTick();
         portRESET_PIC();
     }
-#endif
+#endif /* if ( configUSE_PREEMPTION == 1 ) */
 /*-----------------------------------------------------------*/
 
 static void __interrupt __far prvYieldProcessor( void )
@@ -179,30 +181,31 @@ static void __interrupt __far prvYieldProcessor( void )
 void vPortEndScheduler( void )
 {
     /* Jump back to the processor state prior to starting the
-    scheduler.  This means we are not going to be using a
-    task stack frame so the task can be deleted. */
+     * scheduler.  This means we are not going to be using a
+     * task stack frame so the task can be deleted. */
     longjmp( xJumpBuf, 1 );
 }
 /*-----------------------------------------------------------*/
 
 static void prvExitFunction( void )
 {
-const uint16_t usTimerDisable = 0x0000;
-uint16_t usTimer0Control;
+    const uint16_t usTimerDisable = 0x0000;
+    uint16_t usTimer0Control;
 
     /* Interrupts should be disabled here anyway - but no
-    harm in making sure. */
+     * harm in making sure. */
     portDISABLE_INTERRUPTS();
+
     if( xSchedulerRunning == pdTRUE )
     {
         /* Put back the switch interrupt routines that was in place
-        before the scheduler started. */
+         * before the scheduler started. */
         _dos_setvect( portSWITCH_INT_NUMBER, pxOldSwitchISR );
     }
 
     /* Disable the timer used for the tick to ensure the scheduler is
-    not called before restoring interrupts.  There was previously nothing
-    on this timer so there is no old ISR to restore. */
+     * not called before restoring interrupts.  There was previously nothing
+     * on this timer so there is no old ISR to restore. */
     portOUTPUT_WORD( portTIMER_1_CONTROL_REGISTER, usTimerDisable );
 
     /* Restart the DOS tick. */
@@ -217,18 +220,18 @@ uint16_t usTimer0Control;
 
 static void prvSetTickFrequency( uint32_t ulTickRateHz )
 {
-const uint16_t usMaxCountRegister = 0xff5a;
-const uint16_t usTimerPriorityRegister = 0xff32;
-const uint16_t usTimerEnable = 0xC000;
-const uint16_t usRetrigger = 0x0001;
-const uint16_t usTimerHighPriority = 0x0000;
-uint16_t usTimer0Control;
+    const uint16_t usMaxCountRegister = 0xff5a;
+    const uint16_t usTimerPriorityRegister = 0xff32;
+    const uint16_t usTimerEnable = 0xC000;
+    const uint16_t usRetrigger = 0x0001;
+    const uint16_t usTimerHighPriority = 0x0000;
+    uint16_t usTimer0Control;
 
 /* ( CPU frequency / 4 ) / clock 2 max count [inpw( 0xff62 ) = 7] */
 
-const uint32_t ulClockFrequency = ( uint32_t ) 0x7f31a0UL;
+    const uint32_t ulClockFrequency = ( uint32_t ) 0x7f31a0UL;
 
-uint32_t ulTimerCount = ulClockFrequency / ulTickRateHz;
+    uint32_t ulTimerCount = ulClockFrequency / ulTickRateHz;
 
     portOUTPUT_WORD( portTIMER_1_CONTROL_REGISTER, usTimerEnable | portTIMER_INTERRUPT_ENABLE | usRetrigger );
     portOUTPUT_WORD( usMaxCountRegister, ( uint16_t ) ulTimerCount );
diff --git a/portable/BCC/16BitDOS/Flsh186/prtmacro.h b/portable/BCC/16BitDOS/Flsh186/prtmacro.h
index 295c0bc73..2fd9f91b2 100644
--- a/portable/BCC/16BitDOS/Flsh186/prtmacro.h
+++ b/portable/BCC/16BitDOS/Flsh186/prtmacro.h
@@ -40,60 +40,61 @@
  */
 
 /* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      long
-#define portLONG        long
-#define portSHORT       int
-#define portSTACK_TYPE  uint16_t
-#define portBASE_TYPE   portSHORT
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        long
+#define portLONG          long
+#define portSHORT         int
+#define portSTACK_TYPE    uint16_t
+#define portBASE_TYPE     portSHORT
 
-typedef portSTACK_TYPE StackType_t;
-typedef short BaseType_t;
-typedef unsigned short UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef short            BaseType_t;
+typedef unsigned short   UBaseType_t;
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffffffffUL
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
 /*-----------------------------------------------------------*/
 
 /* Critical section handling. */
-#define portENTER_CRITICAL()            __asm{ pushf }  \
-                                        __asm{ cli   }  \
+#define portENTER_CRITICAL() \
+    __asm { pushf }          \
+    __asm { cli }            \
 
-#define portEXIT_CRITICAL()             __asm{ popf }
+#define portEXIT_CRITICAL()         __asm { popf }
 
-#define portDISABLE_INTERRUPTS()        __asm{ cli }
+#define portDISABLE_INTERRUPTS()    __asm { cli }
 
-#define portENABLE_INTERRUPTS()         __asm{ sti }
+#define portENABLE_INTERRUPTS()     __asm { sti }
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portNOP()                       __asm{ nop }
-#define portSTACK_GROWTH                ( -1 )
-#define portSWITCH_INT_NUMBER           0x80
-#define portYIELD()                     __asm{ int portSWITCH_INT_NUMBER }
-#define portTICK_PERIOD_MS      ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT      2
-#define portINITIAL_SW      ( ( portSTACK_TYPE ) 0x0202 )   /* Start the tasks with interrupts enabled. */
+#define portNOP()      __asm { nop }
+#define portSTACK_GROWTH         ( -1 )
+#define portSWITCH_INT_NUMBER    0x80
+#define portYIELD()    __asm { int portSWITCH_INT_NUMBER }
+#define portTICK_PERIOD_MS       ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT       2
+#define portINITIAL_SW           ( ( portSTACK_TYPE ) 0x0202 ) /* Start the tasks with interrupts enabled. */
 /*-----------------------------------------------------------*/
 
 /* Compiler specifics. */
-#define portINPUT_BYTE( xAddr )             inp( xAddr )
-#define portOUTPUT_BYTE( xAddr, ucValue )   outp( xAddr, ucValue )
-#define portINPUT_WORD( xAddr )             inpw( xAddr )
-#define portOUTPUT_WORD( xAddr, usValue )   outpw( xAddr, usValue )
+#define portINPUT_BYTE( xAddr )              inp( xAddr )
+#define portOUTPUT_BYTE( xAddr, ucValue )    outp( xAddr, ucValue )
+#define portINPUT_WORD( xAddr )              inpw( xAddr )
+#define portOUTPUT_WORD( xAddr, usValue )    outpw( xAddr, usValue )
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters )
-#define portTASK_FUNCTION( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters )
+#define portTASK_FUNCTION_PROTO( vTaskFunction, vParameters )    void vTaskFunction( void * pvParameters )
+#define portTASK_FUNCTION( vTaskFunction, vParameters )          void vTaskFunction( void * pvParameters )
 
 #endif /* PORTMACRO_H */
diff --git a/portable/BCC/16BitDOS/PC/port.c b/portable/BCC/16BitDOS/PC/port.c
index 6940b1a67..e8a14a881 100644
--- a/portable/BCC/16BitDOS/PC/port.c
+++ b/portable/BCC/16BitDOS/PC/port.c
@@ -27,16 +27,16 @@
  */
 
 /*
-Changes from V2.6.1
-
-    + Replaced the sUsingPreemption variable with the configUSE_PREEMPTION
-      macro to be consistent with the later ports.
-
-Changes from V4.0.1
-
-    + Add function prvSetTickFrequencyDefault() to set the DOS tick back to
-      its proper value when the scheduler exits.
-*/
+ * Changes from V2.6.1
+ *
+ + Replaced the sUsingPreemption variable with the configUSE_PREEMPTION
+ +    macro to be consistent with the later ports.
+ +
+ + Changes from V4.0.1
+ +
+ + Add function prvSetTickFrequencyDefault() to set the DOS tick back to
+ +    its proper value when the scheduler exits.
+ */
 
 #include <stdlib.h>
 #include <dos.h>
@@ -47,9 +47,9 @@ Changes from V4.0.1
 #include "portasm.h"
 
 /*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the industrial
- * PC port.
- *----------------------------------------------------------*/
+* Implementation of functions defined in portable.h for the industrial
+* PC port.
+*----------------------------------------------------------*/
 
 /*lint -e950 Non ANSI reserved words okay in this file only. */
 
@@ -62,19 +62,21 @@ static void prvSetTickFrequency( uint32_t ulTickRateHz );
 static void prvExitFunction( void );
 
 /* Either chain to the DOS tick (which itself clears the PIC) or clear the PIC
-directly.  We chain to the DOS tick as close as possible to the standard DOS
-tick rate. */
+ * directly.  We chain to the DOS tick as close as possible to the standard DOS
+ * tick rate. */
 static void prvPortResetPIC( void );
 
 /* The ISR used depends on whether the preemptive or cooperative
-scheduler is being used. */
-#if( configUSE_PREEMPTION == 1 )
-    /* Tick service routine used by the scheduler when preemptive scheduling is
-    being used. */
+ * scheduler is being used. */
+#if ( configUSE_PREEMPTION == 1 )
+
+/* Tick service routine used by the scheduler when preemptive scheduling is
+ * being used. */
     static void __interrupt __far prvPreemptiveTick( void );
 #else
-    /* Tick service routine used by the scheduler when cooperative scheduling is
-    being used. */
+
+/* Tick service routine used by the scheduler when cooperative scheduling is
+ * being used. */
     static void __interrupt __far prvNonPreemptiveTick( void );
 #endif
 
@@ -82,7 +84,7 @@ scheduler is being used. */
 static void __interrupt __far prvYieldProcessor( void );
 
 /* Set the tick frequency back so the floppy drive works correctly when the
-scheduler exits. */
+ * scheduler exits. */
 static void prvSetTickFrequencyDefault( void );
 
 /*lint -e956 File scopes necessary here. */
@@ -94,10 +96,10 @@ static int16_t sDOSTickCounter;
 static BaseType_t xSchedulerRunning = pdFALSE;
 
 /* Points to the original routine installed on the vector we use for manual context switches.  This is then used to restore the original routine during prvExitFunction(). */
-static void ( __interrupt __far *pxOldSwitchISR )();
+static void( __interrupt __far * pxOldSwitchISR )();
 
 /* Points to the original routine installed on the vector we use to chain to the DOS tick.  This is then used to restore the original routine during prvExitFunction(). */
-static void ( __interrupt __far *pxOldSwitchISRPlus1 )();
+static void( __interrupt __far * pxOldSwitchISRPlus1 )();
 
 /* Used to restore the original DOS context when the scheduler is ended. */
 static jmp_buf xJumpBuf;
@@ -107,12 +109,12 @@ static jmp_buf xJumpBuf;
 /*-----------------------------------------------------------*/
 BaseType_t xPortStartScheduler( void )
 {
-pxISR pxOriginalTickISR;
+    pxISR pxOriginalTickISR;
 
     /* This is called with interrupts already disabled. */
 
     /* Remember what was on the interrupts we are going to use
-    so we can put them back later if required. */
+     * so we can put them back later if required. */
     pxOldSwitchISR = _dos_getvect( portSWITCH_INT_NUMBER );
     pxOriginalTickISR = _dos_getvect( portTIMER_INT_NUMBER );
     pxOldSwitchISRPlus1 = _dos_getvect( portSWITCH_INT_NUMBER + 1 );
@@ -120,16 +122,16 @@ pxISR pxOriginalTickISR;
     prvSetTickFrequency( configTICK_RATE_HZ );
 
     /* Put our manual switch (yield) function on a known
-    vector. */
+     * vector. */
     _dos_setvect( portSWITCH_INT_NUMBER, prvYieldProcessor );
 
     /* Put the old tick on a different interrupt number so we can
-    call it when we want. */
+     * call it when we want. */
     _dos_setvect( portSWITCH_INT_NUMBER + 1, pxOriginalTickISR );
 
     /* The ISR used depends on whether the preemptive or cooperative
-    scheduler is being used. */
-    #if( configUSE_PREEMPTION == 1 )
+     * scheduler is being used. */
+    #if ( configUSE_PREEMPTION == 1 )
     {
         /* Put our tick switch function on the timer interrupt. */
         _dos_setvect( portTIMER_INT_NUMBER, prvPreemptiveTick );
@@ -142,8 +144,8 @@ pxISR pxOriginalTickISR;
     #endif
 
     /* Setup a counter that is used to call the DOS interrupt as close
-    to it's original frequency as can be achieved given our chosen tick
-    frequency. */
+     * to it's original frequency as can be achieved given our chosen tick
+     * frequency. */
     sDOSTickCounter = portTICKS_PER_DOS_TICK;
 
     /* Clean up function if we want to return to DOS. */
@@ -165,8 +167,8 @@ pxISR pxOriginalTickISR;
 /*-----------------------------------------------------------*/
 
 /* The ISR used depends on whether the preemptive or cooperative
-scheduler is being used. */
-#if( configUSE_PREEMPTION == 1 )
+ * scheduler is being used. */
+#if ( configUSE_PREEMPTION == 1 )
     static void __interrupt __far prvPreemptiveTick( void )
     {
         /* Get the scheduler to update the task states following the tick. */
@@ -179,15 +181,15 @@ scheduler is being used. */
         /* Reset the PIC ready for the next time. */
         prvPortResetPIC();
     }
-#else
+#else /* if ( configUSE_PREEMPTION == 1 ) */
     static void __interrupt __far prvNonPreemptiveTick( void )
     {
         /* Same as preemptive tick, but the cooperative scheduler is being used
-        so we don't have to switch in the context of the next task. */
+         * so we don't have to switch in the context of the next task. */
         xTaskIncrementTick();
         prvPortResetPIC();
     }
-#endif
+#endif /* if ( configUSE_PREEMPTION == 1 ) */
 /*-----------------------------------------------------------*/
 
 static void __interrupt __far prvYieldProcessor( void )
@@ -200,19 +202,22 @@ static void __interrupt __far prvYieldProcessor( void )
 static void prvPortResetPIC( void )
 {
     /* We are going to call the DOS tick interrupt at as close a
-    frequency to the normal DOS tick as possible. */
+     * frequency to the normal DOS tick as possible. */
 
     /* WE SHOULD NOT DO THIS IF YIELD WAS CALLED. */
     --sDOSTickCounter;
+
     if( sDOSTickCounter <= 0 )
     {
         sDOSTickCounter = ( int16_t ) portTICKS_PER_DOS_TICK;
-        __asm{ int  portSWITCH_INT_NUMBER + 1 };
+        __asm {
+            int portSWITCH_INT_NUMBER + 1
+        };
     }
     else
     {
         /* Reset the PIC as the DOS tick is not being called to
-        do it. */
+         * do it. */
         __asm
         {
             mov al, 20H
@@ -225,19 +230,20 @@ static void prvPortResetPIC( void )
 void vPortEndScheduler( void )
 {
     /* Jump back to the processor state prior to starting the
-    scheduler.  This means we are not going to be using a
-    task stack frame so the task can be deleted. */
+     * scheduler.  This means we are not going to be using a
+     * task stack frame so the task can be deleted. */
     longjmp( xJumpBuf, 1 );
 }
 /*-----------------------------------------------------------*/
 
 static void prvExitFunction( void )
 {
-void ( __interrupt __far *pxOriginalTickISR )();
+    void( __interrupt __far * pxOriginalTickISR )();
 
     /* Interrupts should be disabled here anyway - but no
-    harm in making sure. */
+     * harm in making sure. */
     portDISABLE_INTERRUPTS();
+
     if( xSchedulerRunning == pdTRUE )
     {
         /* Set the DOS tick back onto the timer ticker. */
@@ -246,28 +252,29 @@ void ( __interrupt __far *pxOriginalTickISR )();
         prvSetTickFrequencyDefault();
 
         /* Put back the switch interrupt routines that was in place
-        before the scheduler started. */
+         * before the scheduler started. */
         _dos_setvect( portSWITCH_INT_NUMBER, pxOldSwitchISR );
         _dos_setvect( portSWITCH_INT_NUMBER + 1, pxOldSwitchISRPlus1 );
     }
+
     /* The tick timer is back how DOS wants it.  We can re-enable
-    interrupts without the scheduler being called. */
+     * interrupts without the scheduler being called. */
     portENABLE_INTERRUPTS();
 }
 /*-----------------------------------------------------------*/
 
 static void prvSetTickFrequency( uint32_t ulTickRateHz )
 {
-const uint16_t usPIT_MODE = ( uint16_t ) 0x43;
-const uint16_t usPIT0 = ( uint16_t ) 0x40;
-const uint32_t ulPIT_CONST = ( uint32_t ) 1193180UL;
-const uint16_t us8254_CTR0_MODE3 = ( uint16_t ) 0x36;
-uint32_t ulOutput;
+    const uint16_t usPIT_MODE = ( uint16_t ) 0x43;
+    const uint16_t usPIT0 = ( uint16_t ) 0x40;
+    const uint32_t ulPIT_CONST = ( uint32_t ) 1193180UL;
+    const uint16_t us8254_CTR0_MODE3 = ( uint16_t ) 0x36;
+    uint32_t ulOutput;
 
     /* Setup the 8245 to tick at the wanted frequency. */
     portOUTPUT_BYTE( usPIT_MODE, us8254_CTR0_MODE3 );
     ulOutput = ulPIT_CONST / ulTickRateHz;
-    portOUTPUT_BYTE( usPIT0, ( uint16_t )( ulOutput & ( uint32_t ) 0xff ) );
+    portOUTPUT_BYTE( usPIT0, ( uint16_t ) ( ulOutput & ( uint32_t ) 0xff ) );
     ulOutput >>= 8;
     portOUTPUT_BYTE( usPIT0, ( uint16_t ) ( ulOutput & ( uint32_t ) 0xff ) );
 }
@@ -275,13 +282,13 @@ uint32_t ulOutput;
 
 static void prvSetTickFrequencyDefault( void )
 {
-const uint16_t usPIT_MODE = ( uint16_t ) 0x43;
-const uint16_t usPIT0 = ( uint16_t ) 0x40;
-const uint16_t us8254_CTR0_MODE3 = ( uint16_t ) 0x36;
+    const uint16_t usPIT_MODE = ( uint16_t ) 0x43;
+    const uint16_t usPIT0 = ( uint16_t ) 0x40;
+    const uint16_t us8254_CTR0_MODE3 = ( uint16_t ) 0x36;
 
     portOUTPUT_BYTE( usPIT_MODE, us8254_CTR0_MODE3 );
-    portOUTPUT_BYTE( usPIT0,0 );
-    portOUTPUT_BYTE( usPIT0,0 );
+    portOUTPUT_BYTE( usPIT0, 0 );
+    portOUTPUT_BYTE( usPIT0, 0 );
 }
 
 
diff --git a/portable/BCC/16BitDOS/PC/prtmacro.h b/portable/BCC/16BitDOS/PC/prtmacro.h
index 5fb4ed6a4..e9e7b4ad0 100644
--- a/portable/BCC/16BitDOS/PC/prtmacro.h
+++ b/portable/BCC/16BitDOS/PC/prtmacro.h
@@ -40,60 +40,61 @@
  */
 
 /* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       long
-#define portDOUBLE      long
-#define portLONG        long
-#define portSHORT       int
-#define portSTACK_TYPE  uint16_t
-#define portBASE_TYPE   portSHORT
+#define portCHAR          char
+#define portFLOAT         long
+#define portDOUBLE        long
+#define portLONG          long
+#define portSHORT         int
+#define portSTACK_TYPE    uint16_t
+#define portBASE_TYPE     portSHORT
 
-typedef portSTACK_TYPE StackType_t;
-typedef short BaseType_t;
-typedef unsigned short UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef short            BaseType_t;
+typedef unsigned short   UBaseType_t;
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffffffffUL
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
 /*-----------------------------------------------------------*/
 
 /* Critical section management. */
-#define portENTER_CRITICAL()            __asm{ pushf }  \
-                                        __asm{ cli   }  \
+#define portENTER_CRITICAL() \
+    __asm { pushf }          \
+    __asm { cli }            \
 
-#define portEXIT_CRITICAL()             __asm{ popf }
+#define portEXIT_CRITICAL()         __asm { popf }
 
-#define portDISABLE_INTERRUPTS()        __asm{ cli }
+#define portDISABLE_INTERRUPTS()    __asm { cli }
 
-#define portENABLE_INTERRUPTS()         __asm{ sti }
+#define portENABLE_INTERRUPTS()     __asm { sti }
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portNOP()               __asm{ nop }
-#define portSTACK_GROWTH        ( -1 )
-#define portSWITCH_INT_NUMBER   0x80
-#define portYIELD()             __asm{ int portSWITCH_INT_NUMBER }
-#define portDOS_TICK_RATE       ( 18.20648 )
-#define portTICK_PERIOD_MS      ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portTICKS_PER_DOS_TICK  ( ( uint16_t ) ( ( ( portDOUBLE ) configTICK_RATE_HZ / portDOS_TICK_RATE ) + 0.5 ) )
-#define portINITIAL_SW          ( ( portSTACK_TYPE ) 0x0202 )   /* Start the tasks with interrupts enabled. */
-#define portBYTE_ALIGNMENT      ( 2 )
+#define portNOP()      __asm { nop }
+#define portSTACK_GROWTH          ( -1 )
+#define portSWITCH_INT_NUMBER     0x80
+#define portYIELD()    __asm { int portSWITCH_INT_NUMBER }
+#define portDOS_TICK_RATE         ( 18.20648 )
+#define portTICK_PERIOD_MS        ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portTICKS_PER_DOS_TICK    ( ( uint16_t ) ( ( ( portDOUBLE ) configTICK_RATE_HZ / portDOS_TICK_RATE ) + 0.5 ) )
+#define portINITIAL_SW            ( ( portSTACK_TYPE ) 0x0202 ) /* Start the tasks with interrupts enabled. */
+#define portBYTE_ALIGNMENT        ( 2 )
 /*-----------------------------------------------------------*/
 
 /* Compiler specifics. */
-#define portINPUT_BYTE( xAddr )             inp( xAddr )
-#define portOUTPUT_BYTE( xAddr, ucValue )   outp( xAddr, ucValue )
+#define portINPUT_BYTE( xAddr )              inp( xAddr )
+#define portOUTPUT_BYTE( xAddr, ucValue )    outp( xAddr, ucValue )
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vTaskFunction, pvParameters ) void vTaskFunction( void *pvParameters )
-#define portTASK_FUNCTION( vTaskFunction, pvParameters ) void vTaskFunction( void *pvParameters )
+#define portTASK_FUNCTION_PROTO( vTaskFunction, pvParameters )    void vTaskFunction( void * pvParameters )
+#define portTASK_FUNCTION( vTaskFunction, pvParameters )          void vTaskFunction( void * pvParameters )
 
 #endif /* PORTMACRO_H */
diff --git a/portable/BCC/16BitDOS/common/portasm.h b/portable/BCC/16BitDOS/common/portasm.h
index e53d257c8..f78147d20 100644
--- a/portable/BCC/16BitDOS/common/portasm.h
+++ b/portable/BCC/16BitDOS/common/portasm.h
@@ -48,40 +48,40 @@ void portSWITCH_CONTEXT( void );
 void portFIRST_CONTEXT( void );
 
 /* There are slightly different versions depending on whether you are building
-to include debugger information.  If debugger information is used then there
-are a couple of extra bytes left of the ISR stack (presumably for use by the
-debugger).  The true stack pointer is then stored in the bp register.  We add
-2 to the stack pointer to remove the extra bytes before we restore our context. */
+ * to include debugger information.  If debugger information is used then there
+ * are a couple of extra bytes left of the ISR stack (presumably for use by the
+ * debugger).  The true stack pointer is then stored in the bp register.  We add
+ * 2 to the stack pointer to remove the extra bytes before we restore our context. */
 
-#define portSWITCH_CONTEXT()                                            \
-                            asm { mov   ax, seg pxCurrentTCB        }   \
-                            asm { mov   ds, ax                      }   \
-                            asm { les   bx, pxCurrentTCB            }   /* Save the stack pointer into the TCB. */      \
-                            asm { mov   es:0x2[ bx ], ss            }   \
-                            asm { mov   es:[ bx ], sp               }   \
-                            asm { call  far ptr vTaskSwitchContext  }   /* Perform the switch. */                       \
-                            asm { mov   ax, seg pxCurrentTCB        }   /* Restore the stack pointer from the TCB. */   \
-                            asm { mov   ds, ax                      }   \
-                            asm { les   bx, dword ptr pxCurrentTCB  }   \
-                            asm { mov   ss, es:[ bx + 2 ]           }   \
-                            asm { mov   sp, es:[ bx ]               }
+#define portSWITCH_CONTEXT()                                                              \
+    asm { mov ax, seg pxCurrentTCB }                                                      \
+    asm { mov ds, ax }                                                                    \
+    asm { les bx, pxCurrentTCB } /* Save the stack pointer into the TCB. */               \
+    asm { mov es : 0x2[ bx ], ss }                                                        \
+    asm { mov es:[ bx ], sp }                                                                      \
+    asm { call far ptr vTaskSwitchContext } /* Perform the switch. */                     \
+    asm { mov ax, seg pxCurrentTCB }        /* Restore the stack pointer from the TCB. */ \
+    asm { mov ds, ax }                                                                    \
+    asm { les bx, dword ptr pxCurrentTCB }                                                \
+    asm { mov ss, es:[ bx + 2 ] }                                                                      \
+    asm { mov sp, es:[ bx ] }
 
-#define portFIRST_CONTEXT()                                             \
-                            __asm { mov ax, seg pxCurrentTCB        }   \
-                            __asm { mov ds, ax                      }   \
-                            __asm { les bx, dword ptr pxCurrentTCB  }   \
-                            __asm { mov ss, es:[ bx + 2 ]           }   \
-                            __asm { mov sp, es:[ bx ]               }   \
-                            __asm { pop bp                          }   \
-                            __asm { pop di                          }   \
-                            __asm { pop si                          }   \
-                            __asm { pop ds                          }   \
-                            __asm { pop es                          }   \
-                            __asm { pop dx                          }   \
-                            __asm { pop cx                          }   \
-                            __asm { pop bx                          }   \
-                            __asm { pop ax                          }   \
-                            __asm { iret                            }
+#define portFIRST_CONTEXT()                  \
+    __asm { mov ax, seg pxCurrentTCB }       \
+    __asm { mov ds, ax }                     \
+    __asm { les bx, dword ptr pxCurrentTCB } \
+    __asm { mov ss, es:[ bx + 2 ] }                         \
+    __asm { mov sp, es:[ bx ] }                             \
+    __asm { pop bp }                         \
+    __asm { pop di }                         \
+    __asm { pop si }                         \
+    __asm { pop ds }                         \
+    __asm { pop es }                         \
+    __asm { pop dx }                         \
+    __asm { pop cx }                         \
+    __asm { pop bx }                         \
+    __asm { pop ax }                         \
+    __asm { iret }
 
 
-#endif
+#endif /* ifndef PORT_ASM_H */
diff --git a/portable/BCC/16BitDOS/common/portcomn.c b/portable/BCC/16BitDOS/common/portcomn.c
index 69ab45ba7..d9a1a43c8 100644
--- a/portable/BCC/16BitDOS/common/portcomn.c
+++ b/portable/BCC/16BitDOS/common/portcomn.c
@@ -27,16 +27,16 @@
  */
 
 /*
-Changes from V1.00:
-
-    + pxPortInitialiseStack() now initialises the stack of new tasks to the
-      same format used by the compiler.  This allows the compiler generated
-      interrupt mechanism to be used for context switches.
-
-Changes from V2.6.1
-
-    + Move usPortCheckFreeStackSpace() to tasks.c.
-*/
+ * Changes from V1.00:
+ *
+ + pxPortInitialiseStack() now initialises the stack of new tasks to the
+ +    same format used by the compiler.  This allows the compiler generated
+ +    interrupt mechanism to be used for context switches.
+ +
+ + Changes from V2.6.1
+ +
+ + Move usPortCheckFreeStackSpace() to tasks.c.
+ */
 
 
 #include <dos.h>
@@ -46,12 +46,14 @@ Changes from V2.6.1
 /*-----------------------------------------------------------*/
 
 /* See header file for description. */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
-StackType_t DS_Reg = 0;
+    StackType_t DS_Reg = 0;
 
     /* Place a few bytes of known values on the bottom of the stack.
-    This is just useful for debugging. */
+     * This is just useful for debugging. */
 
     *pxTopOfStack = 0x1111;
     pxTopOfStack--;
@@ -68,8 +70,8 @@ StackType_t DS_Reg = 0;
     /*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */
 
     /* We are going to start the scheduler using a return from interrupt
-    instruction to load the program counter, so first there would be the
-    function call with parameters preamble. */
+     * instruction to load the program counter, so first there would be the
+     * function call with parameters preamble. */
 
     *pxTopOfStack = FP_SEG( pvParameters );
     pxTopOfStack--;
@@ -89,8 +91,8 @@ StackType_t DS_Reg = 0;
     pxTopOfStack--;
 
     /* The remaining registers would be pushed on the stack by our context
-    switch function.  These are loaded with values simply to make debugging
-    easier. */
+     * switch function.  These are loaded with values simply to make debugging
+     * easier. */
     *pxTopOfStack = ( StackType_t ) 0xAAAA; /* AX */
     pxTopOfStack--;
     *pxTopOfStack = ( StackType_t ) 0xBBBB; /* BX */
@@ -103,9 +105,11 @@ StackType_t DS_Reg = 0;
     pxTopOfStack--;
 
     /* We need the true data segment. */
-    __asm{  MOV DS_Reg, DS };
+    __asm {
+        MOV DS_Reg, DS
+    };
 
-    *pxTopOfStack = DS_Reg;                     /* DS */
+    *pxTopOfStack = DS_Reg;                 /* DS */
     pxTopOfStack--;
     *pxTopOfStack = ( StackType_t ) 0x0123; /* SI */
     pxTopOfStack--;
diff --git a/portable/CCS/ARM_CM3/port.c b/portable/CCS/ARM_CM3/port.c
old mode 100755
new mode 100644
index 530e38ad3..a1353c8bc
--- a/portable/CCS/ARM_CM3/port.c
+++ b/portable/CCS/ARM_CM3/port.c
@@ -265,22 +265,22 @@ BaseType_t xPortStartScheduler( void )
         if( ulImplementedPrioBits == 8 )
         {
             /* When the hardware implements 8 priority bits, there is no way for
-            * the software to configure PRIGROUP to not have sub-priorities. As
-            * a result, the least significant bit is always used for sub-priority
-            * and there are 128 preemption priorities and 2 sub-priorities.
-            *
-            * This may cause some confusion in some cases - for example, if
-            * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
-            * priority interrupts will be masked in Critical Sections as those
-            * are at the same preemption priority. This may appear confusing as
-            * 4 is higher (numerically lower) priority than
-            * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
-            * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
-            * to 4, this confusion does not happen and the behaviour remains the same.
-            *
-            * The following assert ensures that the sub-priority bit in the
-            * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
-            * confusion. */
+             * the software to configure PRIGROUP to not have sub-priorities. As
+             * a result, the least significant bit is always used for sub-priority
+             * and there are 128 preemption priorities and 2 sub-priorities.
+             *
+             * This may cause some confusion in some cases - for example, if
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
+             * priority interrupts will be masked in Critical Sections as those
+             * are at the same preemption priority. This may appear confusing as
+             * 4 is higher (numerically lower) priority than
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
+             * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
+             * to 4, this confusion does not happen and the behaviour remains the same.
+             *
+             * The following assert ensures that the sub-priority bit in the
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
+             * confusion. */
             configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
             ulMaxPRIGROUPValue = 0;
         }
diff --git a/portable/CCS/ARM_CM3/portmacro.h b/portable/CCS/ARM_CM3/portmacro.h
index 9c405d4c8..6c9edc39e 100644
--- a/portable/CCS/ARM_CM3/portmacro.h
+++ b/portable/CCS/ARM_CM3/portmacro.h
@@ -28,7 +28,7 @@
 
 
 #ifndef PORTMACRO_H
-    #define PORTMACRO_H
+#define PORTMACRO_H
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
@@ -47,124 +47,124 @@
  */
 
 /* Type definitions. */
-    #define portCHAR          char
-    #define portFLOAT         float
-    #define portDOUBLE        double
-    #define portLONG          long
-    #define portSHORT         short
-    #define portSTACK_TYPE    uint32_t
-    #define portBASE_TYPE     long
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-    typedef portSTACK_TYPE   StackType_t;
-    typedef long             BaseType_t;
-    typedef unsigned long    UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
-    #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-        typedef uint16_t     TickType_t;
-        #define portMAX_DELAY              ( TickType_t ) 0xffff
-    #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-        typedef uint32_t     TickType_t;
-        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
  * not need to be guarded with a critical section. */
-        #define portTICK_TYPE_IS_ATOMIC    1
-    #else
-        #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
-    #endif
+    #define portTICK_TYPE_IS_ATOMIC    1
+#else
+    #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+#endif
 /*-----------------------------------------------------------*/
 
 /* Architecture specifics. */
-    #define portSTACK_GROWTH      ( -1 )
-    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-    #define portBYTE_ALIGNMENT    8
+#define portSTACK_GROWTH      ( -1 )
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT    8
 
 /*-----------------------------------------------------------*/
 
 /* Compiler directives. */
-    #define portWEAK_SYMBOL    __attribute__( ( weak ) )
+#define portWEAK_SYMBOL    __attribute__( ( weak ) )
 
 /*-----------------------------------------------------------*/
 
 /* Scheduler utilities. */
-    #define portYIELD()                                 \
+#define portYIELD()                                     \
     {                                                   \
         /* Set a PendSV to request a context switch. */ \
         portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
-        __asm( "    dsb");                                \
-        __asm( "    isb");                                \
+        __asm( "    dsb" );                             \
+        __asm( "    isb" );                             \
     }
 
-    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
-    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-    #define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 )
-    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+#define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired != pdFALSE ) portYIELD( ); } while( 0 )
+#define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
 
 /*-----------------------------------------------------------*/
 
 /* Architecture specific optimisations. */
-    #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
-    #endif
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+    #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
+#endif
 
-    #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
 
 /* Check the configuration. */
-        #if ( configMAX_PRIORITIES > 32 )
-            #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
-        #endif
+    #if ( configMAX_PRIORITIES > 32 )
+        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+    #endif
 
 /* Store/clear the ready priorities in a bit map. */
-        #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-        #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 
 /*-----------------------------------------------------------*/
 
-        #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31 - __clz( ( uxReadyPriorities ) ) )
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31 - __clz( ( uxReadyPriorities ) ) )
 
-    #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 /*-----------------------------------------------------------*/
 
 /* Critical section management. */
-    extern void vPortEnterCritical( void );
-    extern void vPortExitCritical( void );
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
 
-    #define portDISABLE_INTERRUPTS()                                     \
+#define portDISABLE_INTERRUPTS()                                         \
     {                                                                    \
         _set_interrupt_priority( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \
-        __asm( "    dsb");                                                 \
-        __asm( "    isb");                                                 \
+        __asm( "    dsb" );                                              \
+        __asm( "    isb" );                                              \
     }
 
-    #define portENABLE_INTERRUPTS()                   _set_interrupt_priority( 0 )
-    #define portENTER_CRITICAL()                      vPortEnterCritical()
-    #define portEXIT_CRITICAL()                       vPortExitCritical()
-    #define portSET_INTERRUPT_MASK_FROM_ISR()         _set_interrupt_priority( configMAX_SYSCALL_INTERRUPT_PRIORITY ); __asm( " dsb" ); __asm( "    isb")
-    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    _set_interrupt_priority( x )
+#define portENABLE_INTERRUPTS()                   _set_interrupt_priority( 0 )
+#define portENTER_CRITICAL()                      vPortEnterCritical()
+#define portEXIT_CRITICAL()                       vPortExitCritical()
+#define portSET_INTERRUPT_MASK_FROM_ISR()         _set_interrupt_priority( configMAX_SYSCALL_INTERRUPT_PRIORITY ); __asm( " dsb" ); __asm( "    isb" )
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    _set_interrupt_priority( x )
 /*-----------------------------------------------------------*/
 
 /* Tickless idle/low power functionality. */
-    #ifndef portSUPPRESS_TICKS_AND_SLEEP
-        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
-        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
-    #endif
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+    extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+    #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site.  These are
  * not necessary for to use this port.  They are defined so the common demo files
  * (which build with all the ports) will build. */
-    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
-    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 /*-----------------------------------------------------------*/
 
-    #ifdef configASSERT
-        void vPortValidateInterruptPriority( void );
-        #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
-    #endif
+#ifdef configASSERT
+    void vPortValidateInterruptPriority( void );
+    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
+#endif
 
 /* portNOP() is not required by this port. */
-    #define portNOP()
+#define portNOP()
 
 /*-----------------------------------------------------------*/
 
diff --git a/portable/CCS/ARM_CM4F/port.c b/portable/CCS/ARM_CM4F/port.c
old mode 100755
new mode 100644
index a1fc5210e..fa444d593
--- a/portable/CCS/ARM_CM4F/port.c
+++ b/portable/CCS/ARM_CM4F/port.c
@@ -284,22 +284,22 @@ BaseType_t xPortStartScheduler( void )
         if( ulImplementedPrioBits == 8 )
         {
             /* When the hardware implements 8 priority bits, there is no way for
-            * the software to configure PRIGROUP to not have sub-priorities. As
-            * a result, the least significant bit is always used for sub-priority
-            * and there are 128 preemption priorities and 2 sub-priorities.
-            *
-            * This may cause some confusion in some cases - for example, if
-            * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
-            * priority interrupts will be masked in Critical Sections as those
-            * are at the same preemption priority. This may appear confusing as
-            * 4 is higher (numerically lower) priority than
-            * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
-            * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
-            * to 4, this confusion does not happen and the behaviour remains the same.
-            *
-            * The following assert ensures that the sub-priority bit in the
-            * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
-            * confusion. */
+             * the software to configure PRIGROUP to not have sub-priorities. As
+             * a result, the least significant bit is always used for sub-priority
+             * and there are 128 preemption priorities and 2 sub-priorities.
+             *
+             * This may cause some confusion in some cases - for example, if
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
+             * priority interrupts will be masked in Critical Sections as those
+             * are at the same preemption priority. This may appear confusing as
+             * 4 is higher (numerically lower) priority than
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
+             * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
+             * to 4, this confusion does not happen and the behaviour remains the same.
+             *
+             * The following assert ensures that the sub-priority bit in the
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
+             * confusion. */
             configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
             ulMaxPRIGROUPValue = 0;
         }
diff --git a/portable/CCS/ARM_CM4F/portmacro.h b/portable/CCS/ARM_CM4F/portmacro.h
index 64c702c94..ba4f7490d 100644
--- a/portable/CCS/ARM_CM4F/portmacro.h
+++ b/portable/CCS/ARM_CM4F/portmacro.h
@@ -28,7 +28,7 @@
 
 
 #ifndef PORTMACRO_H
-    #define PORTMACRO_H
+#define PORTMACRO_H
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
@@ -47,118 +47,118 @@
  */
 
 /* Type definitions. */
-    #define portCHAR          char
-    #define portFLOAT         float
-    #define portDOUBLE        double
-    #define portLONG          long
-    #define portSHORT         short
-    #define portSTACK_TYPE    uint32_t
-    #define portBASE_TYPE     long
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-    typedef portSTACK_TYPE   StackType_t;
-    typedef long             BaseType_t;
-    typedef unsigned long    UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
-    #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-        typedef uint16_t     TickType_t;
-        #define portMAX_DELAY              ( TickType_t ) 0xffff
-    #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-        typedef uint32_t     TickType_t;
-        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
  * not need to be guarded with a critical section. */
-        #define portTICK_TYPE_IS_ATOMIC    1
-    #else
-        #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
-    #endif
+    #define portTICK_TYPE_IS_ATOMIC    1
+#else
+    #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+#endif
 /*-----------------------------------------------------------*/
 
 /* Architecture specifics. */
-    #define portSTACK_GROWTH      ( -1 )
-    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-    #define portBYTE_ALIGNMENT    8
+#define portSTACK_GROWTH      ( -1 )
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT    8
 /*-----------------------------------------------------------*/
 
 /* Scheduler utilities. */
-    #define portYIELD()                                 \
+#define portYIELD()                                     \
     {                                                   \
         /* Set a PendSV to request a context switch. */ \
         portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
-        __asm( "    dsb");                                \
-        __asm( "    isb");                                \
+        __asm( "    dsb" );                             \
+        __asm( "    isb" );                             \
     }
 
-    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
-    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-    #define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 )
-    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+#define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired != pdFALSE ) portYIELD( ); } while( 0 )
+#define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
 
 /*-----------------------------------------------------------*/
 
 /* Architecture specific optimisations. */
-    #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
-    #endif
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+    #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
+#endif
 
-    #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
 
 /* Check the configuration. */
-        #if ( configMAX_PRIORITIES > 32 )
-            #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
-        #endif
+    #if ( configMAX_PRIORITIES > 32 )
+        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+    #endif
 
 /* Store/clear the ready priorities in a bit map. */
-        #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-        #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 
 /*-----------------------------------------------------------*/
 
-        #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31 - __clz( ( uxReadyPriorities ) ) )
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31 - __clz( ( uxReadyPriorities ) ) )
 
-    #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 /*-----------------------------------------------------------*/
 
 /* Critical section management. */
-    extern void vPortEnterCritical( void );
-    extern void vPortExitCritical( void );
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
 
-    #define portDISABLE_INTERRUPTS()                                     \
+#define portDISABLE_INTERRUPTS()                                         \
     {                                                                    \
         _set_interrupt_priority( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \
-        __asm( "    dsb");                                                 \
-        __asm( "    isb");                                                 \
+        __asm( "    dsb" );                                              \
+        __asm( "    isb" );                                              \
     }
 
-    #define portENABLE_INTERRUPTS()                   _set_interrupt_priority( 0 )
-    #define portENTER_CRITICAL()                      vPortEnterCritical()
-    #define portEXIT_CRITICAL()                       vPortExitCritical()
-    #define portSET_INTERRUPT_MASK_FROM_ISR()         _set_interrupt_priority( configMAX_SYSCALL_INTERRUPT_PRIORITY ); __asm( " dsb" ); __asm( "    isb")
-    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    _set_interrupt_priority( x )
+#define portENABLE_INTERRUPTS()                   _set_interrupt_priority( 0 )
+#define portENTER_CRITICAL()                      vPortEnterCritical()
+#define portEXIT_CRITICAL()                       vPortExitCritical()
+#define portSET_INTERRUPT_MASK_FROM_ISR()         _set_interrupt_priority( configMAX_SYSCALL_INTERRUPT_PRIORITY ); __asm( " dsb" ); __asm( "    isb" )
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    _set_interrupt_priority( x )
 /*-----------------------------------------------------------*/
 
 /* Tickless idle/low power functionality. */
-    #ifndef portSUPPRESS_TICKS_AND_SLEEP
-        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
-        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
-    #endif
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+    extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+    #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site.  These are
  * not necessary for to use this port.  They are defined so the common demo files
  * (which build with all the ports) will build. */
-    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
-    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 /*-----------------------------------------------------------*/
 
-    #ifdef configASSERT
-        void vPortValidateInterruptPriority( void );
-        #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
-    #endif
+#ifdef configASSERT
+    void vPortValidateInterruptPriority( void );
+    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
+#endif
 
 /* portNOP() is not required by this port. */
-    #define portNOP()
+#define portNOP()
 
 /*-----------------------------------------------------------*/
 
diff --git a/portable/CCS/ARM_Cortex-R4/port.c b/portable/CCS/ARM_Cortex-R4/port.c
index 6c63a5a71..9eff9cf29 100644
--- a/portable/CCS/ARM_Cortex-R4/port.c
+++ b/portable/CCS/ARM_Cortex-R4/port.c
@@ -38,27 +38,27 @@ uint32_t ulCriticalNesting = 9999;
 /*-----------------------------------------------------------*/
 
 /* Registers required to configure the RTI. */
-#define portRTI_GCTRL_REG       ( * ( ( volatile uint32_t * ) 0xFFFFFC00 ) )
-#define portRTI_TBCTRL_REG      ( * ( ( volatile uint32_t * ) 0xFFFFFC04 ) )
-#define portRTI_COMPCTRL_REG    ( * ( ( volatile uint32_t * ) 0xFFFFFC0C ) )
-#define portRTI_CNT0_FRC0_REG   ( * ( ( volatile uint32_t * ) 0xFFFFFC10 ) )
-#define portRTI_CNT0_UC0_REG    ( * ( ( volatile uint32_t * ) 0xFFFFFC14 ) )
-#define portRTI_CNT0_CPUC0_REG  ( * ( ( volatile uint32_t * ) 0xFFFFFC18 ) )
-#define portRTI_CNT0_COMP0_REG  ( * ( ( volatile uint32_t * ) 0xFFFFFC50 ) )
-#define portRTI_CNT0_UDCP0_REG  ( * ( ( volatile uint32_t * ) 0xFFFFFC54 ) )
-#define portRTI_SETINTENA_REG   ( * ( ( volatile uint32_t * ) 0xFFFFFC80 ) )
-#define portRTI_CLEARINTENA_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC84 ) )
-#define portRTI_INTFLAG_REG     ( * ( ( volatile uint32_t * ) 0xFFFFFC88 ) )
+#define portRTI_GCTRL_REG          ( *( ( volatile uint32_t * ) 0xFFFFFC00 ) )
+#define portRTI_TBCTRL_REG         ( *( ( volatile uint32_t * ) 0xFFFFFC04 ) )
+#define portRTI_COMPCTRL_REG       ( *( ( volatile uint32_t * ) 0xFFFFFC0C ) )
+#define portRTI_CNT0_FRC0_REG      ( *( ( volatile uint32_t * ) 0xFFFFFC10 ) )
+#define portRTI_CNT0_UC0_REG       ( *( ( volatile uint32_t * ) 0xFFFFFC14 ) )
+#define portRTI_CNT0_CPUC0_REG     ( *( ( volatile uint32_t * ) 0xFFFFFC18 ) )
+#define portRTI_CNT0_COMP0_REG     ( *( ( volatile uint32_t * ) 0xFFFFFC50 ) )
+#define portRTI_CNT0_UDCP0_REG     ( *( ( volatile uint32_t * ) 0xFFFFFC54 ) )
+#define portRTI_SETINTENA_REG      ( *( ( volatile uint32_t * ) 0xFFFFFC80 ) )
+#define portRTI_CLEARINTENA_REG    ( *( ( volatile uint32_t * ) 0xFFFFFC84 ) )
+#define portRTI_INTFLAG_REG        ( *( ( volatile uint32_t * ) 0xFFFFFC88 ) )
 
 
 /* Constants required to set up the initial stack of each task. */
-#define portINITIAL_SPSR        ( ( StackType_t ) 0x1F )
-#define portINITIAL_FPSCR       ( ( StackType_t ) 0x00 )
-#define portINSTRUCTION_SIZE    ( ( StackType_t ) 0x04 )
-#define portTHUMB_MODE_BIT      ( ( StackType_t ) 0x20 )
+#define portINITIAL_SPSR                        ( ( StackType_t ) 0x1F )
+#define portINITIAL_FPSCR                       ( ( StackType_t ) 0x00 )
+#define portINSTRUCTION_SIZE                    ( ( StackType_t ) 0x04 )
+#define portTHUMB_MODE_BIT                      ( ( StackType_t ) 0x20 )
 
 /* The number of words on the stack frame between the saved Top Of Stack and
-R0 (in which the parameters are passed. */
+ * R0 (in which the parameters are passed. */
 #define portSPACE_BETWEEN_TOS_AND_PARAMETERS    ( 12 )
 
 /*-----------------------------------------------------------*/
@@ -69,7 +69,7 @@ extern void vPortStartFirstTask( void );
 /*-----------------------------------------------------------*/
 
 /* Saved as part of the task context.  Set to pdFALSE if the task does not
-require an FPU context. */
+ * require an FPU context. */
 uint32_t ulTaskHasFPUContext = 0;
 
 /*-----------------------------------------------------------*/
@@ -78,9 +78,11 @@ uint32_t ulTaskHasFPUContext = 0;
 /*
  * See header file for description.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
-StackType_t *pxOriginalTOS;
+    StackType_t * pxOriginalTOS;
 
     pxOriginalTOS = pxTopOfStack;
 
@@ -92,15 +94,15 @@ StackType_t *pxOriginalTOS;
     #endif
 
     /* Setup the initial stack of the task.  The stack is set exactly as
-    expected by the portRESTORE_CONTEXT() macro. */
+     * expected by the portRESTORE_CONTEXT() macro. */
 
     /* First on the stack is the return address - which is the start of the as
-    the task has not executed yet.  The offset is added to make the return
-    address appear as it would within an IRQ ISR. */
+     * the task has not executed yet.  The offset is added to make the return
+     * address appear as it would within an IRQ ISR. */
     *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
     pxTopOfStack--;
 
-    *pxTopOfStack = ( StackType_t ) 0x00000000; /* R14 */
+    *pxTopOfStack = ( StackType_t ) 0x00000000;    /* R14 */
     pxTopOfStack--;
     *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
     pxTopOfStack--;
@@ -132,11 +134,11 @@ StackType_t *pxOriginalTOS;
         *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
         pxTopOfStack--;
     }
-    #else
+    #else /* ifdef portPRELOAD_TASK_REGISTERS */
     {
         pxTopOfStack -= portSPACE_BETWEEN_TOS_AND_PARAMETERS;
     }
-    #endif
+    #endif /* ifdef portPRELOAD_TASK_REGISTERS */
 
     /* Function parameters are passed in R0. */
     *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
@@ -156,8 +158,8 @@ StackType_t *pxOriginalTOS;
         pxTopOfStack--;
 
         /* The last thing on the stack is the tasks ulUsingFPU value, which by
-        default is set to indicate that the stack frame does not include FPU
-        registers. */
+         * default is set to indicate that the stack frame does not include FPU
+         * registers. */
         *pxTopOfStack = pdFALSE;
     }
     #endif
@@ -166,7 +168,7 @@ StackType_t *pxOriginalTOS;
 }
 /*-----------------------------------------------------------*/
 
-static void prvSetupTimerInterrupt(void)
+static void prvSetupTimerInterrupt( void )
 {
     /* Disable timer 0. */
     portRTI_GCTRL_REG &= 0xFFFFFFFEUL;
@@ -178,8 +180,8 @@ static void prvSetupTimerInterrupt(void)
     portRTI_COMPCTRL_REG = 0x00000000U;
 
     /* Initialise the counter and the prescale counter registers. */
-    portRTI_CNT0_UC0_REG =  0x00000000U;
-    portRTI_CNT0_FRC0_REG =  0x00000000U;
+    portRTI_CNT0_UC0_REG = 0x00000000U;
+    portRTI_CNT0_FRC0_REG = 0x00000000U;
 
     /* Set Prescalar for RTI clock. */
     portRTI_CNT0_CPUC0_REG = 0x00000001U;
@@ -187,7 +189,7 @@ static void prvSetupTimerInterrupt(void)
     portRTI_CNT0_UDCP0_REG = ( configCPU_CLOCK_HZ / 2 ) / configTICK_RATE_HZ;
 
     /* Clear interrupts. */
-    portRTI_INTFLAG_REG =  0x0007000FU;
+    portRTI_INTFLAG_REG = 0x0007000FU;
     portRTI_CLEARINTENA_REG = 0x00070F0FU;
 
     /* Enable the compare 0 interrupt. */
@@ -199,7 +201,7 @@ static void prvSetupTimerInterrupt(void)
 /*
  * See header file for description.
  */
-BaseType_t xPortStartScheduler(void)
+BaseType_t xPortStartScheduler( void )
 {
     /* Start the timer that generates the tick ISR. */
     prvSetupTimerInterrupt();
@@ -208,7 +210,7 @@ BaseType_t xPortStartScheduler(void)
     ulCriticalNesting = 0;
 
     /* Start the first task.  This is done from portASM.asm as ARM mode must be
-    used. */
+     * used. */
     vPortStartFirstTask();
 
     /* Should not get here! */
@@ -219,40 +221,40 @@ BaseType_t xPortStartScheduler(void)
 /*
  * See header file for description.
  */
-void vPortEndScheduler(void)
+void vPortEndScheduler( void )
 {
     /* Not implemented in ports where there is nothing to return to.
-    Artificially force an assert. */
+     * Artificially force an assert. */
     configASSERT( ulCriticalNesting == 1000UL );
 }
 /*-----------------------------------------------------------*/
 
 #if configUSE_PREEMPTION == 0
 
-    /* The cooperative scheduler requires a normal IRQ service routine to
-     * simply increment the system tick. */
+/* The cooperative scheduler requires a normal IRQ service routine to
+ * simply increment the system tick. */
     __interrupt void vPortNonPreemptiveTick( void )
     {
         /* clear clock interrupt flag */
         portRTI_INTFLAG_REG = 0x00000001;
 
         /* Increment the tick count - this may make a delaying task ready
-        to run - but a context switch is not performed. */
+         * to run - but a context switch is not performed. */
         xTaskIncrementTick();
     }
 
- #else
+#else /* if configUSE_PREEMPTION == 0 */
 
-    /*
-     **************************************************************************
-     * The preemptive scheduler ISR is written in assembler and can be found
-     * in the portASM.asm file. This will only get used if portUSE_PREEMPTION
-     * is set to 1 in portmacro.h
-     **************************************************************************
-     */
+/*
+ **************************************************************************
+ * The preemptive scheduler ISR is written in assembler and can be found
+ * in the portASM.asm file. This will only get used if portUSE_PREEMPTION
+ * is set to 1 in portmacro.h
+ **************************************************************************
+ */
     void vPortPreemptiveTick( void );
 
-#endif
+#endif /* if configUSE_PREEMPTION == 0 */
 /*-----------------------------------------------------------*/
 
 
@@ -264,9 +266,9 @@ void vPortEnterCritical( void )
     /* Disable interrupts as per portDISABLE_INTERRUPTS(); */
     portDISABLE_INTERRUPTS();
 
-    /* Now interrupts are disabled ulCriticalNesting can be accessed
-    directly.  Increment ulCriticalNesting to keep a count of how many times
-    portENTER_CRITICAL() has been called. */
+    /* Now that interrupts are disabled, ulCriticalNesting can be accessed
+     * directly.  Increment ulCriticalNesting to keep a count of how many times
+     * portENTER_CRITICAL() has been called. */
     ulCriticalNesting++;
 }
 /*-----------------------------------------------------------*/
@@ -283,7 +285,7 @@ void vPortExitCritical( void )
         ulCriticalNesting--;
 
         /* If the nesting level has reached zero then interrupts should be
-        re-enabled. */
+         * re-enabled. */
         if( ulCriticalNesting == 0 )
         {
             /* Enable interrupts as per portENABLE_INTERRUPTS(). */
@@ -297,10 +299,10 @@ void vPortExitCritical( void )
 
     void vPortTaskUsesFPU( void )
     {
-    extern void vPortInitialiseFPSCR( void );
+        extern void vPortInitialiseFPSCR( void );
 
         /* A task is registering the fact that it needs an FPU context.  Set the
-        FPU flag (saved as part of the task context. */
+         * FPU flag (saved as part of the task context. */
         ulTaskHasFPUContext = pdTRUE;
 
         /* Initialise the floating point status register. */
diff --git a/portable/CCS/ARM_Cortex-R4/portmacro.h b/portable/CCS/ARM_Cortex-R4/portmacro.h
index 07c1827cb..06c758aec 100644
--- a/portable/CCS/ARM_Cortex-R4/portmacro.h
+++ b/portable/CCS/ARM_Cortex-R4/portmacro.h
@@ -40,80 +40,80 @@
  */
 
 /* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint32_t
-#define portBASE_TYPE   long
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
-#if (configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS)
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY (TickType_t) 0xFFFF
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xFFFF
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY (TickType_t) 0xFFFFFFFFF
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xFFFFFFFFF
 
-    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-    not need to be guarded with a critical section. */
-    #define portTICK_TYPE_IS_ATOMIC 1
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+    #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
 
 
 /* Architecture specifics. */
-#define portSTACK_GROWTH    (-1)
-#define portTICK_PERIOD_MS    ((TickType_t) 1000 / configTICK_RATE_HZ)
-#define portBYTE_ALIGNMENT  8
+#define portSTACK_GROWTH      ( -1 )
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT    8
 
 /* Critical section handling. */
-extern void vPortEnterCritical(void);
-extern void vPortExitCritical(void);
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
 #define portENTER_CRITICAL()        vPortEnterCritical()
 #define portEXIT_CRITICAL()         vPortExitCritical()
-#define portDISABLE_INTERRUPTS()    asm( " CPSID I" )
-#define portENABLE_INTERRUPTS()     asm( " CPSIE I" )
+#define portDISABLE_INTERRUPTS()    asm ( " CPSID I" )
+#define portENABLE_INTERRUPTS()     asm ( " CPSIE I" )
 
 /* Scheduler utilities. */
 #pragma SWI_ALIAS( vPortYield, 0 )
 extern void vPortYield( void );
-#define portYIELD()                 vPortYield()
-#define portSYS_SSIR1_REG           ( * ( ( volatile uint32_t * ) 0xFFFFFFB0 ) )
-#define portSYS_SSIR1_SSKEY         ( 0x7500UL )
-#define portYIELD_WITHIN_API()      { portSYS_SSIR1_REG = portSYS_SSIR1_SSKEY;  asm( " DSB " ); asm( " ISB " ); }
-#define portYIELD_FROM_ISR( x )     do { if( x != pdFALSE ) { portSYS_SSIR1_REG = portSYS_SSIR1_SSKEY;  ( void ) portSYS_SSIR1_REG; } } while( 0 )
+#define portYIELD()                vPortYield()
+#define portSYS_SSIR1_REG      ( *( ( volatile uint32_t * ) 0xFFFFFFB0 ) )
+#define portSYS_SSIR1_SSKEY    ( 0x7500UL )
+#define portYIELD_WITHIN_API()     { portSYS_SSIR1_REG = portSYS_SSIR1_SSKEY;  asm ( " DSB " ); asm ( " ISB " ); }
+#define portYIELD_FROM_ISR( x )    do { if( x != pdFALSE ) { portSYS_SSIR1_REG = portSYS_SSIR1_SSKEY;  ( void ) portSYS_SSIR1_REG; } } while( 0 )
 
 #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-    #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+    #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
 #endif
 
 /* Architecture specific optimisations. */
 #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
 
-    /* Check the configuration. */
-    #if( configMAX_PRIORITIES > 32 )
+/* Check the configuration. */
+    #if ( configMAX_PRIORITIES > 32 )
         #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
     #endif
 
-    /* Store/clear the ready priorities in a bit map. */
-    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+/* Store/clear the ready priorities in a bit map. */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 
-    /*-----------------------------------------------------------*/
+/*-----------------------------------------------------------*/
 
-    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __clz( ( uxReadyPriorities ) ) )
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31 - __clz( ( uxReadyPriorities ) ) )
 
 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION(vFunction, pvParameters)       void vFunction(void *pvParameters)
-#define portTASK_FUNCTION_PROTO(vFunction, pvParameters) void vFunction(void *pvParameters)
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
 
 #endif /* __PORTMACRO_H__ */
diff --git a/portable/CCS/MSP430X/data_model.h b/portable/CCS/MSP430X/data_model.h
index 186caa65d..15a88ca78 100644
--- a/portable/CCS/MSP430X/data_model.h
+++ b/portable/CCS/MSP430X/data_model.h
@@ -1,49 +1,53 @@
-;/*
-; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
-; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
-; *
-; * SPDX-License-Identifier: MIT
-; *
-; * Permission is hereby granted, free of charge, to any person obtaining a copy of
-; * this software and associated documentation files (the "Software"), to deal in
-; * the Software without restriction, including without limitation the rights to
-; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
-; * the Software, and to permit persons to whom the Software is furnished to do so,
-; * subject to the following conditions:
-; *
-; * The above copyright notice and this permission notice shall be included in all
-; * copies or substantial portions of the Software.
-; *
-; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-; *
-; * https://www.FreeRTOS.org
-; * https://github.com/FreeRTOS
-; *
-; */
+; /*
+   * ; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+   * ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+   * ; *
+   * ; * SPDX-License-Identifier: MIT
+   * ; *
+   * ; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+   * ; * this software and associated documentation files (the "Software"), to deal in
+   * ; * the Software without restriction, including without limitation the rights to
+   * ; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+   * ; * the Software, and to permit persons to whom the Software is furnished to do so,
+   * ; * subject to the following conditions:
+   * ; *
+   * ; * The above copyright notice and this permission notice shall be included in all
+   * ; * copies or substantial portions of the Software.
+   * ; *
+   * ; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+   * ; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+   * ; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+   * ; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+   * ; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+   * ; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+   * ; *
+   * ; * https://www.FreeRTOS.org
+   * ; * https://github.com/FreeRTOS
+   * ; *
+   * ; */
 
-    .if $DEFINED( __LARGE_DATA_MODEL__ )
-        .define "pushm.a", pushm_x
-        .define "popm.a", popm_x
-        .define "push.a", push_x
-        .define "pop.a", pop_x
-        .define "mov.a", mov_x
-    .else
-        .define "pushm.w", pushm_x
-        .define "popm.w", popm_x
-        .define "push.w", push_x
-        .define "pop.w", pop_x
-        .define "mov.w", mov_x
-    .endif
+.
 
-    .if $DEFINED( __LARGE_CODE_MODEL__ )
-        .define "calla", call_x
-        .define "reta", ret_x
-    .else
+   if $DEFINED( __LARGE_DATA_MODEL__ )
+   .define "pushm.a", pushm_x
+   .define "popm.a", popm_x
+   .define "push.a", push_x
+   .define "pop.a", pop_x
+   .define "mov.a", mov_x
+   .else
+    .define "pushm.w", pushm_x
+       .define "popm.w", popm_x
+       .define "push.w", push_x
+       .define "pop.w", pop_x
+       .define "mov.w", mov_x
+       .endif
+
+       .
+
+       if $DEFINED( __LARGE_CODE_MODEL__ )
+       .define "calla", call_x
+       .define "reta", ret_x
+       .else
         .define "call", call_x
-        .define "ret", ret_x
-    .endif
+           .define "ret", ret_x
+           .endif
diff --git a/portable/CCS/MSP430X/port.c b/portable/CCS/MSP430X/port.c
index c691b5d9f..d8ddfe432 100644
--- a/portable/CCS/MSP430X/port.c
+++ b/portable/CCS/MSP430X/port.c
@@ -31,28 +31,28 @@
 #include "task.h"
 
 /*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the MSP430X port.
- *----------------------------------------------------------*/
+* Implementation of functions defined in portable.h for the MSP430X port.
+*----------------------------------------------------------*/
 
 /* Constants required for hardware setup.  The tick ISR runs off the ACLK,
-not the MCLK. */
+ * not the MCLK. */
 #define portACLK_FREQUENCY_HZ           ( ( TickType_t ) 32768 )
 #define portINITIAL_CRITICAL_NESTING    ( ( uint16_t ) 10 )
 #define portFLAGS_INT_ENABLED           ( ( StackType_t ) 0x08 )
 
 /* We require the address of the pxCurrentTCB variable, but don't want to know
-any details of its type. */
+ * any details of its type. */
 typedef void TCB_t;
 extern volatile TCB_t * volatile pxCurrentTCB;
 
 /* Each task maintains a count of the critical section nesting depth.  Each
-time a critical section is entered the count is incremented.  Each time a
-critical section is exited the count is decremented - with interrupts only
-being re-enabled if the count is zero.
-
-usCriticalNesting will get set to zero when the scheduler starts, but must
-not be initialised to zero as this will cause problems during the startup
-sequence. */
+ * time a critical section is entered the count is incremented.  Each time a
+ * critical section is exited the count is decremented - with interrupts only
+ * being re-enabled if the count is zero.
+ *
+ * usCriticalNesting will get set to zero when the scheduler starts, but must
+ * not be initialised to zero as this will cause problems during the startup
+ * sequence. */
 volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;
 /*-----------------------------------------------------------*/
 
@@ -70,25 +70,27 @@ void vPortSetupTimerInterrupt( void );
  *
  * See the header file portable.h.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
-uint16_t *pusTopOfStack;
-uint32_t *pulTopOfStack, ulTemp;
+    uint16_t * pusTopOfStack;
+    uint32_t * pulTopOfStack, ulTemp;
 
     /*
-        Place a few bytes of known values on the bottom of the stack.
-        This is just useful for debugging and can be included if required.
-
-        *pxTopOfStack = ( StackType_t ) 0x1111;
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x2222;
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x3333;
-        pxTopOfStack--;
-    */
+     *  Place a few bytes of known values on the bottom of the stack.
+     *  This is just useful for debugging and can be included if required.
+     *
+     * pxTopOfStack = ( StackType_t ) 0x1111;
+     *  pxTopOfStack--;
+     * pxTopOfStack = ( StackType_t ) 0x2222;
+     *  pxTopOfStack--;
+     * pxTopOfStack = ( StackType_t ) 0x3333;
+     *  pxTopOfStack--;
+     */
 
     /* Data types are need either 16 bits or 32 bits depending on the data
-    and code model used. */
+     * and code model used. */
     if( sizeof( pxCode ) == sizeof( uint16_t ) )
     {
         pusTopOfStack = ( uint16_t * ) pxTopOfStack;
@@ -137,19 +139,19 @@ uint32_t *pulTopOfStack, ulTemp;
         pxTopOfStack--;
         *pxTopOfStack = ( StackType_t ) 0x4444;
         pxTopOfStack--;
-    #else
+    #else /* ifdef PRELOAD_REGISTER_VALUES */
         pxTopOfStack -= 3;
         *pxTopOfStack = ( StackType_t ) pvParameters;
         pxTopOfStack -= 9;
-    #endif
+    #endif /* ifdef PRELOAD_REGISTER_VALUES */
 
     /* A variable is used to keep track of the critical section nesting.
-    This variable has to be stored as part of the task context and is
-    initially set to zero. */
+     * This variable has to be stored as part of the task context and is
+     * initially set to zero. */
     *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;
 
     /* Return a pointer to the top of the stack we have generated so this can
-    be stored in the task control block for the task. */
+     * be stored in the task control block for the task. */
     return pxTopOfStack;
 }
 /*-----------------------------------------------------------*/
@@ -157,7 +159,7 @@ uint32_t *pulTopOfStack, ulTemp;
 void vPortEndScheduler( void )
 {
     /* It is unlikely that the MSP430 port will get stopped.  If required simply
-    disable the tick interrupt here. */
+     * disable the tick interrupt here. */
 }
 /*-----------------------------------------------------------*/
 
@@ -173,7 +175,7 @@ void vPortSetupTimerInterrupt( void )
 #pragma vector=configTICK_VECTOR
 interrupt void vTickISREntry( void )
 {
-extern void vPortTickISR( void );
+    extern void vPortTickISR( void );
 
     __bic_SR_register_on_exit( SCG1 + SCG0 + OSCOFF + CPUOFF );
     #if configUSE_PREEMPTION == 1
@@ -184,5 +186,3 @@ extern void vPortTickISR( void );
         vPortCooperativeTickISR();
     #endif
 }
-
-
diff --git a/portable/CCS/MSP430X/portmacro.h b/portable/CCS/MSP430X/portmacro.h
index 064b0503a..5b5a87184 100644
--- a/portable/CCS/MSP430X/portmacro.h
+++ b/portable/CCS/MSP430X/portmacro.h
@@ -43,31 +43,31 @@
 #include "msp430.h"
 
 /* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       int
-#define portBASE_TYPE   portSHORT
+#define portCHAR         char
+#define portFLOAT        float
+#define portDOUBLE       double
+#define portLONG         long
+#define portSHORT        int
+#define portBASE_TYPE    portSHORT
 
 /* The stack type changes depending on the data model. */
 #ifdef __LARGE_DATA_MODEL__
-    #define portSTACK_TYPE uint32_t
+    #define portSTACK_TYPE           uint32_t
 #else
-    #define portSTACK_TYPE uint16_t
-    #define portPOINTER_SIZE_TYPE uint16_t
+    #define portSTACK_TYPE           uint16_t
+    #define portPOINTER_SIZE_TYPE    uint16_t
 #endif
 
-typedef portSTACK_TYPE StackType_t;
-typedef short BaseType_t;
-typedef unsigned short UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef short            BaseType_t;
+typedef unsigned short   UBaseType_t;
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY ( TickType_t )    ( 0xFFFFFFFFUL )
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) ( 0xFFFFFFFFUL )
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
@@ -80,37 +80,37 @@ typedef unsigned short UBaseType_t;
 /*-----------------------------------------------------------*/
 
 /* Critical section control macros. */
-#define portNO_CRITICAL_SECTION_NESTING     ( ( uint16_t ) 0 )
+#define portNO_CRITICAL_SECTION_NESTING    ( ( uint16_t ) 0 )
 
-#define portENTER_CRITICAL()                                                    \
-{                                                                               \
-extern volatile uint16_t usCriticalNesting;                                     \
-                                                                                \
-    portDISABLE_INTERRUPTS();                                                   \
-                                                                                \
-    /* Now interrupts are disabled usCriticalNesting can be accessed */         \
-    /* directly.  Increment ulCriticalNesting to keep a count of how many */    \
-    /* times portENTER_CRITICAL() has been called. */                           \
-    usCriticalNesting++;                                                        \
-}
+#define portENTER_CRITICAL()                                                     \
+    {                                                                            \
+        extern volatile uint16_t usCriticalNesting;                              \
+                                                                                 \
+        portDISABLE_INTERRUPTS();                                                \
+                                                                                 \
+        /* Now interrupts are disabled usCriticalNesting can be accessed */      \
+        /* directly.  Increment ulCriticalNesting to keep a count of how many */ \
+        /* times portENTER_CRITICAL() has been called. */                        \
+        usCriticalNesting++;                                                     \
+    }
 
-#define portEXIT_CRITICAL()                                                     \
-{                                                                               \
-extern volatile uint16_t usCriticalNesting;                                     \
-                                                                                \
-    if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING )                   \
-    {                                                                           \
-        /* Decrement the nesting count as we are leaving a critical section. */ \
-        usCriticalNesting--;                                                    \
-                                                                                \
-        /* If the nesting level has reached zero then interrupts should be */   \
-        /* re-enabled. */                                                       \
-        if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING )              \
-        {                                                                       \
-            portENABLE_INTERRUPTS();                                            \
-        }                                                                       \
-    }                                                                           \
-}
+#define portEXIT_CRITICAL()                                                         \
+    {                                                                               \
+        extern volatile uint16_t usCriticalNesting;                                 \
+                                                                                    \
+        if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING )                   \
+        {                                                                           \
+            /* Decrement the nesting count as we are leaving a critical section. */ \
+            usCriticalNesting--;                                                    \
+                                                                                    \
+            /* If the nesting level has reached zero then interrupts should be */   \
+            /* re-enabled. */                                                       \
+            if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING )              \
+            {                                                                       \
+                portENABLE_INTERRUPTS();                                            \
+            }                                                                       \
+        }                                                                           \
+    }
 /*-----------------------------------------------------------*/
 
 /* Task utilities. */
@@ -119,27 +119,27 @@ extern volatile uint16_t usCriticalNesting;
  * Manual context switch called by portYIELD or taskYIELD.
  */
 extern void vPortYield( void );
-#define portYIELD() vPortYield()
+#define portYIELD()    vPortYield()
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portBYTE_ALIGNMENT          2
-#define portSTACK_GROWTH            ( -1 )
-#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portNOP()                   __no_operation()
+#define portBYTE_ALIGNMENT    2
+#define portSTACK_GROWTH      ( -1 )
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()    __no_operation()
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
 extern void vTaskSwitchContext( void );
-#define portYIELD_FROM_ISR( x ) do { if( x ) vPortYield(); } while( 0 )
+#define portYIELD_FROM_ISR( x )                               do { if( x ) vPortYield( ); } while( 0 )
 
 void vApplicationSetupTimerInterrupt( void );
 
 /* sizeof( int ) != sizeof( long ) so a full printf() library is required if
-run time stats information is to be displayed. */
+ * run time stats information is to be displayed. */
 #define portLU_PRINTF_SPECIFIER_REQUIRED
 
 #endif /* PORTMACRO_H */
diff --git a/portable/CodeWarrior/ColdFire_V1/port.c b/portable/CodeWarrior/ColdFire_V1/port.c
index 513ce1632..dd6d794e9 100644
--- a/portable/CodeWarrior/ColdFire_V1/port.c
+++ b/portable/CodeWarrior/ColdFire_V1/port.c
@@ -31,35 +31,38 @@
 #include "task.h"
 
 
-#define portINITIAL_FORMAT_VECTOR       ( ( StackType_t ) 0x4000 )
+#define portINITIAL_FORMAT_VECTOR      ( ( StackType_t ) 0x4000 )
 
 /* Supervisor mode set. */
-#define portINITIAL_STATUS_REGISTER     ( ( StackType_t ) 0x2000)
+#define portINITIAL_STATUS_REGISTER    ( ( StackType_t ) 0x2000 )
 
 /* The clock prescale into the timer peripheral. */
-#define portPRESCALE_VALUE              ( ( uint8_t ) 10 )
+#define portPRESCALE_VALUE             ( ( uint8_t ) 10 )
 
 /* The clock frequency into the RTC. */
-#define portRTC_CLOCK_HZ                ( ( uint32_t ) 1000 )
+#define portRTC_CLOCK_HZ               ( ( uint32_t ) 1000 )
 
 asm void interrupt VectorNumber_VL1swi vPortYieldISR( void );
 static void prvSetupTimerInterrupt( void );
 
 /* Used to keep track of the number of nested calls to taskENTER_CRITICAL().  This
-will be set to 0 prior to the first task being started. */
+ * will be set to 0 prior to the first task being started. */
 static uint32_t ulCriticalNesting = 0x9999UL;
 
 /*-----------------------------------------------------------*/
 
-StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
+    uint32_t ulOriginalA5;
 
-uint32_t ulOriginalA5;
-
-    __asm{ MOVE.L A5, ulOriginalA5 };
+    __asm {
+        MOVE.L A5, ulOriginalA5
+    };
 
 
-    *pxTopOfStack = (StackType_t) 0xDEADBEEF;
+    *pxTopOfStack = ( StackType_t ) 0xDEADBEEF;
     pxTopOfStack--;
 
     /* Exception stack frame starts with the return address. */
@@ -70,12 +73,12 @@ uint32_t ulOriginalA5;
     pxTopOfStack--;
 
     *pxTopOfStack = ( StackType_t ) 0x0; /*FP*/
-    pxTopOfStack -= 14; /* A5 to D0. */
+    pxTopOfStack -= 14;                  /* A5 to D0. */
 
     /* Parameter in A0. */
     *( pxTopOfStack + 8 ) = ( StackType_t ) pvParameters;
 
-    /* A5 must be maintained as it is resurved by the compiler. */
+    /* A5 must be maintained as it is reserved by the compiler. */
     *( pxTopOfStack + 13 ) = ulOriginalA5;
 
     return pxTopOfStack;
@@ -84,7 +87,7 @@ uint32_t ulOriginalA5;
 
 BaseType_t xPortStartScheduler( void )
 {
-extern void vPortStartFirstTask( void );
+    extern void vPortStartFirstTask( void );
 
     ulCriticalNesting = 0UL;
 
@@ -107,7 +110,7 @@ static void prvSetupTimerInterrupt( void )
     RTCMOD = portRTC_CLOCK_HZ / configTICK_RATE_HZ;
 
     /* Enable the RTC to generate interrupts - interrupts are already disabled
-    when this code executes. */
+     * when this code executes. */
     RTCSC_RTIE = 1;
 }
 /*-----------------------------------------------------------*/
@@ -123,19 +126,20 @@ void vPortEnterCritical( void )
     if( ulCriticalNesting == 0UL )
     {
         /* Guard against context switches being pended simultaneously with a
-        critical section being entered. */
+         * critical section being entered. */
         do
         {
             portDISABLE_INTERRUPTS();
+
             if( INTC_FRC == 0UL )
             {
                 break;
             }
 
             portENABLE_INTERRUPTS();
-
         } while( 1 );
     }
+
     ulCriticalNesting++;
 }
 /*-----------------------------------------------------------*/
@@ -143,6 +147,7 @@ void vPortEnterCritical( void )
 void vPortExitCritical( void )
 {
     ulCriticalNesting--;
+
     if( ulCriticalNesting == 0 )
     {
         portENABLE_INTERRUPTS();
@@ -152,7 +157,7 @@ void vPortExitCritical( void )
 
 void vPortYieldHandler( void )
 {
-uint32_t ulSavedInterruptMask;
+    uint32_t ulSavedInterruptMask;
 
     ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR();
     {
@@ -166,7 +171,7 @@ uint32_t ulSavedInterruptMask;
 
 void interrupt VectorNumber_Vrtc vPortTickISR( void )
 {
-uint32_t ulSavedInterruptMask;
+    uint32_t ulSavedInterruptMask;
 
     /* Clear the interrupt. */
     RTCSC |= RTCSC_RTIF_MASK;
diff --git a/portable/CodeWarrior/ColdFire_V1/portmacro.h b/portable/CodeWarrior/ColdFire_V1/portmacro.h
index 8acfcd04f..0f62912d4 100644
--- a/portable/CodeWarrior/ColdFire_V1/portmacro.h
+++ b/portable/CodeWarrior/ColdFire_V1/portmacro.h
@@ -46,34 +46,34 @@
  */
 
 /* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint32_t
-#define portBASE_TYPE   long
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY ( TickType_t )    ( 0xFFFFFFFFUL )
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) ( 0xFFFFFFFFUL )
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portBYTE_ALIGNMENT          4
-#define portSTACK_GROWTH            -1
-#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT    4
+#define portSTACK_GROWTH      -1
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
 /*-----------------------------------------------------------*/
 
 uint32_t ulPortSetIPL( uint32_t );
@@ -83,30 +83,30 @@ uint32_t ulPortSetIPL( uint32_t );
 
 extern void vPortEnterCritical( void );
 extern void vPortExitCritical( void );
-#define portENTER_CRITICAL()        vPortEnterCritical()
-#define portEXIT_CRITICAL()         vPortExitCritical()
+#define portENTER_CRITICAL()    vPortEnterCritical()
+#define portEXIT_CRITICAL()     vPortExitCritical()
 
 extern UBaseType_t uxPortSetInterruptMaskFromISR( void );
 extern void vPortClearInterruptMaskFromISR( UBaseType_t );
-#define portSET_INTERRUPT_MASK_FROM_ISR()   ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY )
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) ulPortSetIPL( uxSavedStatusRegister )
+#define portSET_INTERRUPT_MASK_FROM_ISR()                             ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister )    ulPortSetIPL( uxSavedStatusRegister )
 
 /*-----------------------------------------------------------*/
 
 /* Task utilities. */
-#define portNOP()   asm volatile ( "nop" )
+#define portNOP()      asm volatile ( "nop" )
 
 /* Context switches are requested using the force register. */
-#define portYIELD() INTC_SFRC = 0x3E; portNOP(); portNOP(); portNOP(); portNOP(); portNOP()
+#define portYIELD()    INTC_SFRC = 0x3E; portNOP(); portNOP(); portNOP(); portNOP(); portNOP()
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn))
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters ) __attribute__( ( noreturn ) )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 /*-----------------------------------------------------------*/
 
-#define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired != pdFALSE ) { portYIELD(); } } while( 0 )
+#define portEND_SWITCHING_ISR( xSwitchRequired )              do { if( xSwitchRequired != pdFALSE ) { portYIELD(); } } while( 0 )
 
 
 /* *INDENT-OFF* */
diff --git a/portable/CodeWarrior/ColdFire_V2/port.c b/portable/CodeWarrior/ColdFire_V2/port.c
index 5bca650fe..a7a78a7e9 100644
--- a/portable/CodeWarrior/ColdFire_V2/port.c
+++ b/portable/CodeWarrior/ColdFire_V2/port.c
@@ -31,39 +31,41 @@
 #include "task.h"
 
 
-#define portINITIAL_FORMAT_VECTOR       ( ( StackType_t ) 0x4000 )
+#define portINITIAL_FORMAT_VECTOR      ( ( StackType_t ) 0x4000 )
 
 /* Supervisor mode set. */
-#define portINITIAL_STATUS_REGISTER     ( ( StackType_t ) 0x2000)
+#define portINITIAL_STATUS_REGISTER    ( ( StackType_t ) 0x2000 )
 
 /* Used to keep track of the number of nested calls to taskENTER_CRITICAL().  This
-will be set to 0 prior to the first task being started. */
+ * will be set to 0 prior to the first task being started. */
 static uint32_t ulCriticalNesting = 0x9999UL;
 
 
-#define portSAVE_CONTEXT()              \
-    lea.l       (-60, %sp), %sp;        \
-    movem.l     %d0-%fp, (%sp);         \
-    move.l      pxCurrentTCB, %a0;      \
-    move.l      %sp, (%a0);
+#define portSAVE_CONTEXT()         \
+    lea.l( -60, % sp ), % sp;      \
+    movem.l % d0 - % fp, ( % sp ); \
+    move.l pxCurrentTCB, % a0;     \
+    move.l % sp, ( % a0 );
 
-#define portRESTORE_CONTEXT()           \
-    move.l      pxCurrentTCB, %a0;      \
-    move.l      (%a0), %sp;             \
-    movem.l     (%sp), %d0-%fp;         \
-    lea.l       %sp@(60), %sp;          \
+#define portRESTORE_CONTEXT()     \
+    move.l pxCurrentTCB, % a0;    \
+    move.l( % a0 ), % sp;         \
+    movem.l( % sp ), % d0 - % fp; \
+    lea.l % sp@( 60 ), % sp;      \
     rte
 
 
 
 /*-----------------------------------------------------------*/
 
-StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
     *pxTopOfStack = ( StackType_t ) pvParameters;
     pxTopOfStack--;
 
-    *pxTopOfStack = (StackType_t) 0xDEADBEEF;
+    *pxTopOfStack = ( StackType_t ) 0xDEADBEEF;
     pxTopOfStack--;
 
     /* Exception stack frame starts with the return address. */
@@ -74,7 +76,7 @@ StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t p
     pxTopOfStack--;
 
     *pxTopOfStack = ( StackType_t ) 0x0; /*FP*/
-    pxTopOfStack -= 14; /* A5 to D0. */
+    pxTopOfStack -= 14;                  /* A5 to D0. */
 
     return pxTopOfStack;
 }
@@ -82,7 +84,7 @@ StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t p
 
 BaseType_t xPortStartScheduler( void )
 {
-extern void vPortStartFirstTask( void );
+    extern void vPortStartFirstTask( void );
 
     ulCriticalNesting = 0UL;
 
@@ -107,19 +109,20 @@ void vPortEnterCritical( void )
     if( ulCriticalNesting == 0UL )
     {
         /* Guard against context switches being pended simultaneously with a
-        critical section being entered. */
+         * critical section being entered. */
         do
         {
             portDISABLE_INTERRUPTS();
+
             if( MCF_INTC0_INTFRCH == 0UL )
             {
                 break;
             }
 
             portENABLE_INTERRUPTS();
-
         } while( 1 );
     }
+
     ulCriticalNesting++;
 }
 /*-----------------------------------------------------------*/
@@ -127,6 +130,7 @@ void vPortEnterCritical( void )
 void vPortExitCritical( void )
 {
     ulCriticalNesting--;
+
     if( ulCriticalNesting == 0 )
     {
         portENABLE_INTERRUPTS();
@@ -136,12 +140,12 @@ void vPortExitCritical( void )
 
 void vPortYieldHandler( void )
 {
-uint32_t ulSavedInterruptMask;
+    uint32_t ulSavedInterruptMask;
 
     ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR();
-        /* Note this will clear all forced interrupts - this is done for speed. */
-        MCF_INTC0_INTFRCL = 0;
-        vTaskSwitchContext();
+    /* Note this will clear all forced interrupts - this is done for speed. */
+    MCF_INTC0_INTFRCL = 0;
+    vTaskSwitchContext();
     portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask );
 }
 /*-----------------------------------------------------------*/
diff --git a/portable/CodeWarrior/ColdFire_V2/portmacro.h b/portable/CodeWarrior/ColdFire_V2/portmacro.h
index 053b0adec..a815e6469 100644
--- a/portable/CodeWarrior/ColdFire_V2/portmacro.h
+++ b/portable/CodeWarrior/ColdFire_V2/portmacro.h
@@ -46,33 +46,33 @@
  */
 
 /* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint32_t
-#define portBASE_TYPE   long
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY ( TickType_t )    ( 0xFFFFFFFFUL )
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) ( 0xFFFFFFFFUL )
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portBYTE_ALIGNMENT          4
-#define portSTACK_GROWTH            -1
-#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT    4
+#define portSTACK_GROWTH      -1
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
 /*-----------------------------------------------------------*/
 uint32_t ulPortSetIPL( uint32_t );
 #define portDISABLE_INTERRUPTS()    ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY )
@@ -81,31 +81,31 @@ uint32_t ulPortSetIPL( uint32_t );
 
 extern void vPortEnterCritical( void );
 extern void vPortExitCritical( void );
-#define portENTER_CRITICAL()        vPortEnterCritical()
-#define portEXIT_CRITICAL()         vPortExitCritical()
+#define portENTER_CRITICAL()    vPortEnterCritical()
+#define portEXIT_CRITICAL()     vPortExitCritical()
 
 extern UBaseType_t uxPortSetInterruptMaskFromISR( void );
 extern void vPortClearInterruptMaskFromISR( UBaseType_t );
-#define portSET_INTERRUPT_MASK_FROM_ISR()   ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY )
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) ulPortSetIPL( uxSavedStatusRegister )
+#define portSET_INTERRUPT_MASK_FROM_ISR()                             ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister )    ulPortSetIPL( uxSavedStatusRegister )
 
 /*-----------------------------------------------------------*/
 
 /* Task utilities. */
 
-#define portNOP()   asm volatile (  "nop" )
+#define portNOP()      asm volatile ( "nop" )
 
 /* Note this will overwrite all other bits in the force register, it is done this way for speed. */
-#define portYIELD()         MCF_INTC0_INTFRCL = ( 1UL << configYIELD_INTERRUPT_VECTOR ); portNOP(); portNOP() /* -32 as we are using the high word of the 64bit mask. */
+#define portYIELD()    MCF_INTC0_INTFRCL = ( 1UL << configYIELD_INTERRUPT_VECTOR ); portNOP(); portNOP()      /* -32 as we are using the high word of the 64bit mask. */
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn))
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters ) __attribute__( ( noreturn ) )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 /*-----------------------------------------------------------*/
 
-#define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired != pdFALSE ) { portYIELD(); } } while( 0 )
+#define portEND_SWITCHING_ISR( xSwitchRequired )              do { if( xSwitchRequired != pdFALSE ) { portYIELD(); } } while( 0 )
 
 
 /* *INDENT-OFF* */
diff --git a/portable/CodeWarrior/HCS12/port.c b/portable/CodeWarrior/HCS12/port.c
index e4876125a..1b6f5c37d 100644
--- a/portable/CodeWarrior/HCS12/port.c
+++ b/portable/CodeWarrior/HCS12/port.c
@@ -32,8 +32,8 @@
 
 
 /*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the HCS12 port.
- *----------------------------------------------------------*/
+* Implementation of functions defined in portable.h for the HCS12 port.
+*----------------------------------------------------------*/
 
 
 /*
@@ -43,29 +43,29 @@
 static void prvSetupTimerInterrupt( void );
 
 /* Interrupt service routines have to be in non-banked memory - as does the
-scheduler startup function. */
+ * scheduler startup function. */
 #pragma CODE_SEG __NEAR_SEG NON_BANKED
 
-    /* Manual context switch function.  This is the SWI ISR. */
-    void interrupt vPortYield( void );
+/* Manual context switch function.  This is the SWI ISR. */
+void interrupt vPortYield( void );
 
-    /* Tick context switch function.  This is the timer ISR. */
-    void interrupt vPortTickInterrupt( void );
+/* Tick context switch function.  This is the timer ISR. */
+void interrupt vPortTickInterrupt( void );
 
-    /* Simply called by xPortStartScheduler().  xPortStartScheduler() does not
-    start the scheduler directly because the header file containing the
-    xPortStartScheduler() prototype is part of the common kernel code, and
-    therefore cannot use the CODE_SEG pragma. */
-    static BaseType_t xBankedStartScheduler( void );
+/* Simply called by xPortStartScheduler().  xPortStartScheduler() does not
+ * start the scheduler directly because the header file containing the
+ * xPortStartScheduler() prototype is part of the common kernel code, and
+ * therefore cannot use the CODE_SEG pragma. */
+static BaseType_t xBankedStartScheduler( void );
 
 #pragma CODE_SEG DEFAULT
 
 /* Calls to portENTER_CRITICAL() can be nested.  When they are nested the
-critical section should not be left (i.e. interrupts should not be re-enabled)
-until the nesting depth reaches 0.  This variable simply tracks the nesting
-depth.  Each task maintains it's own critical nesting depth variable so
-uxCriticalNesting is saved and restored from the task stack during a context
-switch. */
+ * critical section should not be left (i.e. interrupts should not be re-enabled)
+ * until the nesting depth reaches 0.  This variable simply tracks the nesting
+ * depth.  Each task maintains it's own critical nesting depth variable so
+ * uxCriticalNesting is saved and restored from the task stack during a context
+ * switch. */
 volatile UBaseType_t uxCriticalNesting = 0xff;
 
 /*-----------------------------------------------------------*/
@@ -73,31 +73,33 @@ volatile UBaseType_t uxCriticalNesting = 0xff;
 /*
  * See header file for description.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
     /*
-        Place a few bytes of known values on the bottom of the stack.
-        This can be uncommented to provide useful stack markers when debugging.
-
-        *pxTopOfStack = ( StackType_t ) 0x11;
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x22;
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x33;
-        pxTopOfStack--;
-    */
+     *  Place a few bytes of known values on the bottom of the stack.
+     *  This can be uncommented to provide useful stack markers when debugging.
+     *
+     * pxTopOfStack = ( StackType_t ) 0x11;
+     *  pxTopOfStack--;
+     * pxTopOfStack = ( StackType_t ) 0x22;
+     *  pxTopOfStack--;
+     * pxTopOfStack = ( StackType_t ) 0x33;
+     *  pxTopOfStack--;
+     */
 
 
 
     /* Setup the initial stack of the task.  The stack is set exactly as
-    expected by the portRESTORE_CONTEXT() macro.  In this case the stack as
-    expected by the HCS12 RTI instruction. */
+     * expected by the portRESTORE_CONTEXT() macro.  In this case the stack as
+     * expected by the HCS12 RTI instruction. */
 
 
     /* The address of the task function is placed in the stack byte at a time. */
-    *pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pxCode) ) + 1 );
+    *pxTopOfStack = ( StackType_t ) *( ( ( StackType_t * ) ( &pxCode ) ) + 1 );
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pxCode) ) + 0 );
+    *pxTopOfStack = ( StackType_t ) *( ( ( StackType_t * ) ( &pxCode ) ) + 0 );
     pxTopOfStack--;
 
     /* Next are all the registers that form part of the task context. */
@@ -115,15 +117,15 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
     pxTopOfStack--;
 
     /* A register contains parameter high byte. */
-    *pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pvParameters) ) + 0 );
+    *pxTopOfStack = ( StackType_t ) *( ( ( StackType_t * ) ( &pvParameters ) ) + 0 );
     pxTopOfStack--;
 
     /* B register contains parameter low byte. */
-    *pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pvParameters) ) + 1 );
+    *pxTopOfStack = ( StackType_t ) *( ( ( StackType_t * ) ( &pvParameters ) ) + 1 );
     pxTopOfStack--;
 
     /* CCR: Note that when the task starts interrupts will be enabled since
-    "I" bit of CCR is cleared */
+     * "I" bit of CCR is cleared */
     *pxTopOfStack = ( StackType_t ) 0x00;
     pxTopOfStack--;
 
@@ -134,7 +136,7 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
     #endif
 
     /* Finally the critical nesting depth is initialised with 0 (not within
-    a critical section). */
+     * a critical section). */
     *pxTopOfStack = ( StackType_t ) 0x00;
 
     return pxTopOfStack;
@@ -157,10 +159,10 @@ static void prvSetupTimerInterrupt( void )
 BaseType_t xPortStartScheduler( void )
 {
     /* xPortStartScheduler() does not start the scheduler directly because
-    the header file containing the xPortStartScheduler() prototype is part
-    of the common kernel code, and therefore cannot use the CODE_SEG pragma.
-    Instead it simply calls the locally defined xBankedStartScheduler() -
-    which does use the CODE_SEG pragma. */
+     * the header file containing the xPortStartScheduler() prototype is part
+     * of the common kernel code, and therefore cannot use the CODE_SEG pragma.
+     * Instead it simply calls the locally defined xBankedStartScheduler() -
+     * which does use the CODE_SEG pragma. */
 
     return xBankedStartScheduler();
 }
@@ -171,7 +173,7 @@ BaseType_t xPortStartScheduler( void )
 static BaseType_t xBankedStartScheduler( void )
 {
     /* Configure the timer that will generate the RTOS tick.  Interrupts are
-    disabled when this function is called. */
+     * disabled when this function is called. */
     prvSetupTimerInterrupt();
 
     /* Restore the context of the first task. */
@@ -222,15 +224,15 @@ void interrupt vPortTickInterrupt( void )
         TFLG1 = 1;
 
         /* Restore the context of a task - which may be a different task
-        to that interrupted. */
+         * to that interrupted. */
         portRESTORE_CONTEXT();
     }
-    #else
+    #else /* if configUSE_PREEMPTION == 1 */
     {
         xTaskIncrementTick();
         TFLG1 = 1;
     }
-    #endif
+    #endif /* if configUSE_PREEMPTION == 1 */
 }
 
 #pragma CODE_SEG DEFAULT
diff --git a/portable/CodeWarrior/HCS12/portmacro.h b/portable/CodeWarrior/HCS12/portmacro.h
index d0d0a140e..f2f899346 100644
--- a/portable/CodeWarrior/HCS12/portmacro.h
+++ b/portable/CodeWarrior/HCS12/portmacro.h
@@ -41,40 +41,40 @@
  */
 
 /* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint8_t
-#define portBASE_TYPE   char
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint8_t
+#define portBASE_TYPE     char
 
-typedef portSTACK_TYPE StackType_t;
-typedef signed char BaseType_t;
-typedef unsigned char UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef signed char      BaseType_t;
+typedef unsigned char    UBaseType_t;
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY ( TickType_t )    ( 0xFFFFFFFFUL )
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) ( 0xFFFFFFFFUL )
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portBYTE_ALIGNMENT          1
-#define portSTACK_GROWTH            ( -1 )
-#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portYIELD()                 __asm( "swi" );
-#define portNOP()                   __asm( "nop" );
+#define portBYTE_ALIGNMENT    1
+#define portSTACK_GROWTH      ( -1 )
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portYIELD()    __asm( "swi" );
+#define portNOP()      __asm( "nop" );
 /*-----------------------------------------------------------*/
 
 /* Critical section handling. */
-#define portENABLE_INTERRUPTS()             __asm( "cli" )
-#define portDISABLE_INTERRUPTS()            __asm( "sei" )
+#define portENABLE_INTERRUPTS()     __asm( "cli" )
+#define portDISABLE_INTERRUPTS()    __asm( "sei" )
 
 /*
  * Disable interrupts before incrementing the count of critical section nesting.
@@ -82,29 +82,29 @@ typedef unsigned char UBaseType_t;
  * re-enabled.  Once interrupts are disabled the nesting count can be accessed
  * directly.  Each task maintains its own nesting count.
  */
-#define portENTER_CRITICAL()                                    \
-{                                                               \
-    extern volatile UBaseType_t uxCriticalNesting;  \
-                                                                \
-    portDISABLE_INTERRUPTS();                                   \
-    uxCriticalNesting++;                                        \
-}
+#define portENTER_CRITICAL()                           \
+    {                                                  \
+        extern volatile UBaseType_t uxCriticalNesting; \
+                                                       \
+        portDISABLE_INTERRUPTS();                      \
+        uxCriticalNesting++;                           \
+    }
 
 /*
  * Interrupts are disabled so we can access the nesting count directly.  If the
  * nesting is found to be 0 (no nesting) then we are leaving the critical
  * section and interrupts can be re-enabled.
  */
-#define  portEXIT_CRITICAL()                                    \
-{                                                               \
-    extern volatile UBaseType_t uxCriticalNesting;  \
-                                                                \
-    uxCriticalNesting--;                                        \
-    if( uxCriticalNesting == 0 )                                \
-    {                                                           \
-        portENABLE_INTERRUPTS();                                \
-    }                                                           \
-}
+#define  portEXIT_CRITICAL()                           \
+    {                                                  \
+        extern volatile UBaseType_t uxCriticalNesting; \
+                                                       \
+        uxCriticalNesting--;                           \
+        if( uxCriticalNesting == 0 )                   \
+        {                                              \
+            portENABLE_INTERRUPTS();                   \
+        }                                              \
+    }
 /*-----------------------------------------------------------*/
 
 /* Task utilities. */
@@ -120,70 +120,71 @@ typedef unsigned char UBaseType_t;
  */
 
 #ifdef BANKED_MODEL
-    /*
-     * Load the stack pointer for the task, then pull the critical nesting
-     * count and PPAGE register from the stack.  The remains of the
-     * context are restored by the RTI instruction.
-     */
-    #define portRESTORE_CONTEXT()                                   \
-    {                                                               \
-        extern volatile void * pxCurrentTCB;                        \
-        extern volatile UBaseType_t uxCriticalNesting;  \
-                                                                    \
-        __asm( "ldx pxCurrentTCB" );                                \
-        __asm( "lds 0, x" );                                        \
-        __asm( "pula" );                                            \
-        __asm( "staa uxCriticalNesting" );                          \
-        __asm( "pula" );                                            \
-        __asm( "staa 0x30" ); /* 0x30 = PPAGE */                    \
+
+/*
+ * Load the stack pointer for the task, then pull the critical nesting
+ * count and PPAGE register from the stack.  The remains of the
+ * context are restored by the RTI instruction.
+ */
+    #define portRESTORE_CONTEXT()                      \
+    {                                                  \
+        extern volatile void * pxCurrentTCB;           \
+        extern volatile UBaseType_t uxCriticalNesting; \
+                                                       \
+        __asm( "ldx pxCurrentTCB" );                   \
+        __asm( "lds 0, x" );                           \
+        __asm( "pula" );                               \
+        __asm( "staa uxCriticalNesting" );             \
+        __asm( "pula" );                               \
+        __asm( "staa 0x30" ); /* 0x30 = PPAGE */       \
     }
 
-    /*
-     * By the time this macro is called the processor has already stacked the
-     * registers.  Simply stack the nesting count and PPAGE value, then save
-     * the task stack pointer.
-     */
-    #define portSAVE_CONTEXT()                                      \
-    {                                                               \
-        extern volatile void * pxCurrentTCB;                        \
-        extern volatile UBaseType_t uxCriticalNesting;  \
-                                                                    \
-        __asm( "ldaa 0x30" );  /* 0x30 = PPAGE */                   \
-        __asm( "psha" );                                            \
-        __asm( "ldaa uxCriticalNesting" );                          \
-        __asm( "psha" );                                            \
-        __asm( "ldx pxCurrentTCB" );                                \
-        __asm( "sts 0, x" );                                        \
+/*
+ * By the time this macro is called the processor has already stacked the
+ * registers.  Simply stack the nesting count and PPAGE value, then save
+ * the task stack pointer.
+ */
+    #define portSAVE_CONTEXT()                         \
+    {                                                  \
+        extern volatile void * pxCurrentTCB;           \
+        extern volatile UBaseType_t uxCriticalNesting; \
+                                                       \
+        __asm( "ldaa 0x30" ); /* 0x30 = PPAGE */       \
+        __asm( "psha" );                               \
+        __asm( "ldaa uxCriticalNesting" );             \
+        __asm( "psha" );                               \
+        __asm( "ldx pxCurrentTCB" );                   \
+        __asm( "sts 0, x" );                           \
     }
-#else
+#else /* ifdef BANKED_MODEL */
 
-    /*
-     * These macros are as per the BANKED versions above, but without saving
-     * and restoring the PPAGE register.
-     */
+/*
+ * These macros are as per the BANKED versions above, but without saving
+ * and restoring the PPAGE register.
+ */
 
-    #define portRESTORE_CONTEXT()                                   \
-    {                                                               \
-        extern volatile void * pxCurrentTCB;                        \
-        extern volatile UBaseType_t uxCriticalNesting;  \
-                                                                    \
-        __asm( "ldx pxCurrentTCB" );                                \
-        __asm( "lds 0, x" );                                        \
-        __asm( "pula" );                                            \
-        __asm( "staa uxCriticalNesting" );                          \
+    #define portRESTORE_CONTEXT()                      \
+    {                                                  \
+        extern volatile void * pxCurrentTCB;           \
+        extern volatile UBaseType_t uxCriticalNesting; \
+                                                       \
+        __asm( "ldx pxCurrentTCB" );                   \
+        __asm( "lds 0, x" );                           \
+        __asm( "pula" );                               \
+        __asm( "staa uxCriticalNesting" );             \
     }
 
-    #define portSAVE_CONTEXT()                                      \
-    {                                                               \
-        extern volatile void * pxCurrentTCB;                        \
-        extern volatile UBaseType_t uxCriticalNesting;  \
-                                                                    \
-        __asm( "ldaa uxCriticalNesting" );                          \
-        __asm( "psha" );                                            \
-        __asm( "ldx pxCurrentTCB" );                                \
-        __asm( "sts 0, x" );                                        \
+    #define portSAVE_CONTEXT()                         \
+    {                                                  \
+        extern volatile void * pxCurrentTCB;           \
+        extern volatile UBaseType_t uxCriticalNesting; \
+                                                       \
+        __asm( "ldaa uxCriticalNesting" );             \
+        __asm( "psha" );                               \
+        __asm( "ldx pxCurrentTCB" );                   \
+        __asm( "sts 0, x" );                           \
     }
-#endif
+#endif /* ifdef BANKED_MODEL */
 
 /*
  * Utility macro to call macros above in correct order in order to perform a
@@ -191,14 +192,14 @@ typedef unsigned char UBaseType_t;
  * the ISR does not use any local (stack) variables.  If the ISR uses stack
  * variables portYIELD() should be used in it's place.
  */
-#define portTASK_SWITCH_FROM_ISR()                              \
-    portSAVE_CONTEXT();                                         \
-    vTaskSwitchContext();                                       \
+#define portTASK_SWITCH_FROM_ISR() \
+    portSAVE_CONTEXT();            \
+    vTaskSwitchContext();          \
     portRESTORE_CONTEXT();
 
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
 #endif /* PORTMACRO_H */
diff --git a/portable/GCC/ARM7_AT91FR40008/port.c b/portable/GCC/ARM7_AT91FR40008/port.c
index d85e476df..86cc6e0f3 100644
--- a/portable/GCC/ARM7_AT91FR40008/port.c
+++ b/portable/GCC/ARM7_AT91FR40008/port.c
@@ -28,13 +28,13 @@
 
 
 /*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the Atmel AT91R40008
- * port.
- *
- * Components that can be compiled to either ARM or THUMB mode are
- * contained in this file.  The ISR routines, which can only be compiled
- * to ARM mode are contained in portISR.c.
- *----------------------------------------------------------*/
+* Implementation of functions defined in portable.h for the Atmel AT91R40008
+* port.
+*
+* Components that can be compiled to either ARM or THUMB mode are
+* contained in this file.  The ISR routines, which can only be compiled
+* to ARM mode are contained in portISR.c.
+*----------------------------------------------------------*/
 
 /* Standard includes. */
 #include <stdlib.h>
@@ -50,11 +50,11 @@
 #include "tc.h"
 
 /* Constants required to setup the task context. */
-#define portINITIAL_SPSR                ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
-#define portTHUMB_MODE_BIT              ( ( StackType_t ) 0x20 )
-#define portINSTRUCTION_SIZE            ( ( StackType_t ) 4 )
-#define portNO_CRITICAL_SECTION_NESTING ( ( StackType_t ) 0 )
-#define portTICK_PRIORITY_6             ( 6 )
+#define portINITIAL_SPSR                   ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT                 ( ( StackType_t ) 0x20 )
+#define portINSTRUCTION_SIZE               ( ( StackType_t ) 4 )
+#define portNO_CRITICAL_SECTION_NESTING    ( ( StackType_t ) 0 )
+#define portTICK_PRIORITY_6                ( 6 )
 /*-----------------------------------------------------------*/
 
 /* Setup the timer to generate the tick interrupts. */
@@ -74,61 +74,63 @@ extern void vPortISRStartFirstTask( void );
  *
  * See header file for description.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
-StackType_t *pxOriginalTOS;
+    StackType_t * pxOriginalTOS;
 
     pxOriginalTOS = pxTopOfStack;
 
     /* To ensure asserts in tasks.c don't fail, although in this case the assert
-    is not really required. */
+     * is not really required. */
     pxTopOfStack--;
 
     /* Setup the initial stack of the task.  The stack is set exactly as
-    expected by the portRESTORE_CONTEXT() macro. */
+     * expected by the portRESTORE_CONTEXT() macro. */
 
     /* First on the stack is the return address - which in this case is the
-    start of the task.  The offset is added to make the return address appear
-    as it would within an IRQ ISR. */
+     * start of the task.  The offset is added to make the return address appear
+     * as it would within an IRQ ISR. */
     *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
     pxTopOfStack--;
 
-    *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */
+    *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa;    /* R14 */
     pxTopOfStack--;
     *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
+    *pxTopOfStack = ( StackType_t ) 0x12121212;    /* R12 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
+    *pxTopOfStack = ( StackType_t ) 0x11111111;    /* R11 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
+    *pxTopOfStack = ( StackType_t ) 0x10101010;    /* R10 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
+    *pxTopOfStack = ( StackType_t ) 0x09090909;    /* R9 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
+    *pxTopOfStack = ( StackType_t ) 0x08080808;    /* R8 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
+    *pxTopOfStack = ( StackType_t ) 0x07070707;    /* R7 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
+    *pxTopOfStack = ( StackType_t ) 0x06060606;    /* R6 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
+    *pxTopOfStack = ( StackType_t ) 0x05050505;    /* R5 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
+    *pxTopOfStack = ( StackType_t ) 0x04040404;    /* R4 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
+    *pxTopOfStack = ( StackType_t ) 0x03030303;    /* R3 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
+    *pxTopOfStack = ( StackType_t ) 0x02020202;    /* R2 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
+    *pxTopOfStack = ( StackType_t ) 0x01010101;    /* R1 */
     pxTopOfStack--;
 
     /* When the task starts is will expect to find the function parameter in
-    R0. */
+     * R0. */
     *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
     pxTopOfStack--;
 
     /* The last thing onto the stack is the status register, which is set for
-    system mode, with interrupts enabled. */
+     * system mode, with interrupts enabled. */
     *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
 
     #ifdef THUMB_INTERWORK
@@ -141,9 +143,9 @@ StackType_t *pxOriginalTOS;
     pxTopOfStack--;
 
     /* Some optimisation levels use the stack differently to others.  This
-    means the interrupt flags cannot always be stored on the stack and will
-    instead be stored in a variable, which is then saved as part of the
-    tasks context. */
+     * means the interrupt flags cannot always be stored on the stack and will
+     * instead be stored in a variable, which is then saved as part of the
+     * tasks context. */
     *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
 
     return pxTopOfStack;
@@ -153,7 +155,7 @@ StackType_t *pxOriginalTOS;
 BaseType_t xPortStartScheduler( void )
 {
     /* Start the timer that generates the tick ISR.  Interrupts are disabled
-    here already. */
+     * here already. */
     prvSetupTimerInterrupt();
 
     /* Start the first task. */
@@ -167,7 +169,7 @@ BaseType_t xPortStartScheduler( void )
 void vPortEndScheduler( void )
 {
     /* It is unlikely that the ARM port will require this function as there
-    is nothing to return to.  */
+     * is nothing to return to.  */
 }
 /*-----------------------------------------------------------*/
 
@@ -176,7 +178,7 @@ void vPortEndScheduler( void )
  */
 static void prvSetupTimerInterrupt( void )
 {
-volatile uint32_t ulDummy;
+    volatile uint32_t ulDummy;
 
     /* Enable clock to the tick timer... */
     AT91C_BASE_PS->PS_PCER = portTIMER_CLK_ENABLE_BIT;
@@ -191,17 +193,17 @@ volatile uint32_t ulDummy;
     ulDummy = portTIMER_REG_BASE_PTR->TC_SR;
 
     /* Store interrupt handler function address in tick timer vector register...
-    The ISR installed depends on whether the preemptive or cooperative
-    scheduler is being used. */
+     * The ISR installed depends on whether the preemptive or cooperative
+     * scheduler is being used. */
     #if configUSE_PREEMPTION == 1
     {
-        extern void ( vPreemptiveTick )( void );
-        AT91C_BASE_AIC->AIC_SVR[portTIMER_AIC_CHANNEL] = ( uint32_t ) vPreemptiveTick;
+        extern void( vPreemptiveTick )( void );
+        AT91C_BASE_AIC->AIC_SVR[ portTIMER_AIC_CHANNEL ] = ( uint32_t ) vPreemptiveTick;
     }
-    #else  // else use cooperative scheduler
+    #else // else use cooperative scheduler
     {
-        extern void ( vNonPreemptiveTick )( void );
-        AT91C_BASE_AIC->AIC_SVR[portTIMER_AIC_CHANNEL] = ( uint32_t ) vNonPreemptiveTick;
+        extern void( vNonPreemptiveTick )( void );
+        AT91C_BASE_AIC->AIC_SVR[ portTIMER_AIC_CHANNEL ] = ( uint32_t ) vNonPreemptiveTick;
     }
     #endif
 
@@ -209,27 +211,27 @@ volatile uint32_t ulDummy;
     AT91C_BASE_AIC->AIC_SMR[ portTIMER_AIC_CHANNEL ] = AIC_SRCTYPE_INT_LEVEL_SENSITIVE | portTICK_PRIORITY_6;
 
     /* Enable the tick timer interrupt...
-
-    First at timer level */
+     *
+     * First at timer level */
     portTIMER_REG_BASE_PTR->TC_IER = TC_CPCS;
 
     /* Then at the AIC level. */
-    AT91C_BASE_AIC->AIC_IECR = (1 << portTIMER_AIC_CHANNEL);
+    AT91C_BASE_AIC->AIC_IECR = ( 1 << portTIMER_AIC_CHANNEL );
 
     /* Calculate timer compare value to achieve the desired tick rate... */
-    if( (configCPU_CLOCK_HZ / (configTICK_RATE_HZ * 2) ) <= 0xFFFF )
+    if( ( configCPU_CLOCK_HZ / ( configTICK_RATE_HZ * 2 ) ) <= 0xFFFF )
     {
         /* The tick rate is fast enough for us to use the faster timer input
-        clock (main clock / 2). */
+         * clock (main clock / 2). */
         portTIMER_REG_BASE_PTR->TC_CMR = TC_WAVE | TC_CLKS_MCK2 | TC_BURST_NONE | TC_CPCTRG;
-        portTIMER_REG_BASE_PTR->TC_RC  = configCPU_CLOCK_HZ / (configTICK_RATE_HZ * 2);
+        portTIMER_REG_BASE_PTR->TC_RC = configCPU_CLOCK_HZ / ( configTICK_RATE_HZ * 2 );
     }
     else
     {
         /* We must use a slower timer input clock (main clock / 8) because the
-        tick rate is too slow for the faster input clock. */
+         * tick rate is too slow for the faster input clock. */
         portTIMER_REG_BASE_PTR->TC_CMR = TC_WAVE | TC_CLKS_MCK8 | TC_BURST_NONE | TC_CPCTRG;
-        portTIMER_REG_BASE_PTR->TC_RC  = configCPU_CLOCK_HZ / (configTICK_RATE_HZ * 8);
+        portTIMER_REG_BASE_PTR->TC_RC = configCPU_CLOCK_HZ / ( configTICK_RATE_HZ * 8 );
     }
 
     /* Start tick timer... */
diff --git a/portable/GCC/ARM7_AT91FR40008/portISR.c b/portable/GCC/ARM7_AT91FR40008/portISR.c
index 15eba673d..9df08b0c9 100644
--- a/portable/GCC/ARM7_AT91FR40008/portISR.c
+++ b/portable/GCC/ARM7_AT91FR40008/portISR.c
@@ -28,17 +28,17 @@
 
 
 /*-----------------------------------------------------------
- * Components that can be compiled to either ARM or THUMB mode are
- * contained in port.c  The ISR routines, which can only be compiled
- * to ARM mode, are contained in this file.
- *----------------------------------------------------------*/
+* Components that can be compiled to either ARM or THUMB mode are
+* contained in port.c  The ISR routines, which can only be compiled
+* to ARM mode, are contained in this file.
+*----------------------------------------------------------*/
 
 /*
-    Changes from V3.2.4
-
-    + The assembler statements are now included in a single asm block rather
-      than each line having its own asm block.
-*/
+ *  Changes from V3.2.4
+ *
+ + The assembler statements are now included in a single asm block rather
+ +    than each line having its own asm block.
+ */
 
 
 /* Scheduler includes. */
@@ -46,16 +46,16 @@
 #include "task.h"
 
 /* Constants required to handle interrupts. */
-#define portCLEAR_AIC_INTERRUPT     ( ( uint32_t ) 0 )
+#define portCLEAR_AIC_INTERRUPT    ( ( uint32_t ) 0 )
 
 /* Constants required to handle critical sections. */
-#define portNO_CRITICAL_NESTING     ( ( uint32_t ) 0 )
+#define portNO_CRITICAL_NESTING    ( ( uint32_t ) 0 )
 volatile uint32_t ulCriticalNesting = 9999UL;
 
 /*-----------------------------------------------------------*/
 
 /* ISR to handle manual context switches (from a call to taskYIELD()). */
-void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked));
+void vPortYieldProcessor( void ) __attribute__( ( interrupt( "SWI" ), naked ) );
 
 /*
  * The scheduler can only be started from ARM mode, hence the inclusion of this
@@ -67,7 +67,7 @@ void vPortISRStartFirstTask( void );
 void vPortISRStartFirstTask( void )
 {
     /* Simply start the scheduler.  This is included here as it can only be
-    called from ARM mode. */
+     * called from ARM mode. */
     portRESTORE_CONTEXT();
 }
 /*-----------------------------------------------------------*/
@@ -83,8 +83,8 @@ void vPortISRStartFirstTask( void )
 void vPortYieldProcessor( void )
 {
     /* Within an IRQ ISR the link register has an offset from the true return
-    address, but an SWI ISR does not.  Add the offset manually so the same
-    ISR return code can be used in both cases. */
+     * address, but an SWI ISR does not.  Add the offset manually so the same
+     * ISR return code can be used in both cases. */
     asm volatile ( "ADD     LR, LR, #4" );
 
     /* Perform the context switch.  First save the context of the current task. */
@@ -105,12 +105,12 @@ void vPortYieldProcessor( void )
 
 #if configUSE_PREEMPTION == 0
 
-    /* The cooperative scheduler requires a normal IRQ service routine to
-    simply increment the system tick. */
-    void vNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ")));
+/* The cooperative scheduler requires a normal IRQ service routine to
+ * simply increment the system tick. */
+    void vNonPreemptiveTick( void ) __attribute__( ( interrupt( "IRQ" ) ) );
     void vNonPreemptiveTick( void )
     {
-    static volatile uint32_t ulDummy;
+        static volatile uint32_t ulDummy;
 
         /* Clear tick timer interrupt indication. */
         ulDummy = portTIMER_REG_BASE_PTR->TC_SR;
@@ -121,25 +121,25 @@ void vPortYieldProcessor( void )
         AT91C_BASE_AIC->AIC_EOICR = portCLEAR_AIC_INTERRUPT;
     }
 
-#else  /* else preemption is turned on */
+#else /* else preemption is turned on */
 
-    /* The preemptive scheduler is defined as "naked" as the full context is
-    saved on entry as part of the context switch. */
-    void vPreemptiveTick( void ) __attribute__((naked));
+/* The preemptive scheduler is defined as "naked" as the full context is
+ * saved on entry as part of the context switch. */
+    void vPreemptiveTick( void ) __attribute__( ( naked ) );
     void vPreemptiveTick( void )
     {
         /* Save the context of the interrupted task. */
         portSAVE_CONTEXT();
 
         /* WARNING - Do not use local (stack) variables here.  Use globals
-                     if you must! */
+         *           if you must! */
         static volatile uint32_t ulDummy;
 
         /* Clear tick timer interrupt indication. */
         ulDummy = portTIMER_REG_BASE_PTR->TC_SR;
 
         /* Increment the RTOS tick count, then look for the highest priority
-        task that is ready to run. */
+         * task that is ready to run. */
         if( xTaskIncrementTick() != pdFALSE )
         {
             vTaskSwitchContext();
@@ -152,7 +152,7 @@ void vPortYieldProcessor( void )
         portRESTORE_CONTEXT();
     }
 
-#endif
+#endif /* if configUSE_PREEMPTION == 0 */
 /*-----------------------------------------------------------*/
 
 /*
@@ -163,50 +163,50 @@ void vPortYieldProcessor( void )
  */
 #ifdef THUMB_INTERWORK
 
-    void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
-    void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
+    void vPortDisableInterruptsFromThumb( void ) __attribute__( ( naked ) );
+    void vPortEnableInterruptsFromThumb( void ) __attribute__( ( naked ) );
 
     void vPortDisableInterruptsFromThumb( void )
     {
         asm volatile (
-            "STMDB  SP!, {R0}       \n\t"   /* Push R0.                                 */
-            "MRS    R0, CPSR        \n\t"   /* Get CPSR.                                */
-            "ORR    R0, R0, #0xC0   \n\t"   /* Disable IRQ, FIQ.                        */
-            "MSR    CPSR, R0        \n\t"   /* Write back modified value.               */
-            "LDMIA  SP!, {R0}       \n\t"   /* Pop R0.                                  */
-            "BX     R14" );                 /* Return back to thumb.                    */
+            "STMDB  SP!, {R0}       \n\t" /* Push R0.                                 */
+            "MRS    R0, CPSR        \n\t" /* Get CPSR.                                */
+            "ORR    R0, R0, #0xC0   \n\t" /* Disable IRQ, FIQ.                        */
+            "MSR    CPSR, R0        \n\t" /* Write back modified value.               */
+            "LDMIA  SP!, {R0}       \n\t" /* Pop R0.                                  */
+            "BX     R14" );               /* Return back to thumb.                    */
     }
 
     void vPortEnableInterruptsFromThumb( void )
     {
         asm volatile (
-            "STMDB  SP!, {R0}       \n\t"   /* Push R0.                                 */
-            "MRS    R0, CPSR        \n\t"   /* Get CPSR.                                */
-            "BIC    R0, R0, #0xC0   \n\t"   /* Enable IRQ, FIQ.                         */
-            "MSR    CPSR, R0        \n\t"   /* Write back modified value.               */
-            "LDMIA  SP!, {R0}       \n\t"   /* Pop R0.                                  */
-            "BX     R14" );                 /* Return back to thumb.                    */
+            "STMDB  SP!, {R0}       \n\t" /* Push R0.                                 */
+            "MRS    R0, CPSR        \n\t" /* Get CPSR.                                */
+            "BIC    R0, R0, #0xC0   \n\t" /* Enable IRQ, FIQ.                         */
+            "MSR    CPSR, R0        \n\t" /* Write back modified value.               */
+            "LDMIA  SP!, {R0}       \n\t" /* Pop R0.                                  */
+            "BX     R14" );               /* Return back to thumb.                    */
     }
 
 #endif /* THUMB_INTERWORK */
 
 /* The code generated by the GCC compiler uses the stack in different ways at
-different optimisation levels.  The interrupt flags can therefore not always
-be saved to the stack.  Instead the critical section nesting level is stored
-in a variable, which is then saved as part of the stack context. */
+ * different optimisation levels.  The interrupt flags can therefore not always
+ * be saved to the stack.  Instead the critical section nesting level is stored
+ * in a variable, which is then saved as part of the stack context. */
 void vPortEnterCritical( void )
 {
     /* Disable interrupts as per portDISABLE_INTERRUPTS();                          */
     asm volatile (
-        "STMDB  SP!, {R0}           \n\t"   /* Push R0.                             */
-        "MRS    R0, CPSR            \n\t"   /* Get CPSR.                            */
-        "ORR    R0, R0, #0xC0       \n\t"   /* Disable IRQ, FIQ.                    */
-        "MSR    CPSR, R0            \n\t"   /* Write back modified value.           */
-        "LDMIA  SP!, {R0}" );               /* Pop R0.                              */
+        "STMDB  SP!, {R0}           \n\t" /* Push R0.                             */
+        "MRS    R0, CPSR            \n\t" /* Get CPSR.                            */
+        "ORR    R0, R0, #0xC0       \n\t" /* Disable IRQ, FIQ.                    */
+        "MSR    CPSR, R0            \n\t" /* Write back modified value.           */
+        "LDMIA  SP!, {R0}" );             /* Pop R0.                              */
 
-    /* Now interrupts are disabled ulCriticalNesting can be accessed
-    directly.  Increment ulCriticalNesting to keep a count of how many times
-    portENTER_CRITICAL() has been called. */
+    /* Now that interrupts are disabled, ulCriticalNesting can be accessed
+     * directly.  Increment ulCriticalNesting to keep a count of how many times
+     * portENTER_CRITICAL() has been called. */
     ulCriticalNesting++;
 }
 
@@ -218,16 +218,16 @@ void vPortExitCritical( void )
         ulCriticalNesting--;
 
         /* If the nesting level has reached zero then interrupts should be
-        re-enabled. */
+         * re-enabled. */
         if( ulCriticalNesting == portNO_CRITICAL_NESTING )
         {
             /* Enable interrupts as per portEXIT_CRITICAL().                */
             asm volatile (
-                "STMDB  SP!, {R0}       \n\t"   /* Push R0.                     */
-                "MRS    R0, CPSR        \n\t"   /* Get CPSR.                    */
-                "BIC    R0, R0, #0xC0   \n\t"   /* Enable IRQ, FIQ.             */
-                "MSR    CPSR, R0        \n\t"   /* Write back modified value.   */
-                "LDMIA  SP!, {R0}" );           /* Pop R0.                      */
+                "STMDB  SP!, {R0}       \n\t" /* Push R0.                     */
+                "MRS    R0, CPSR        \n\t" /* Get CPSR.                    */
+                "BIC    R0, R0, #0xC0   \n\t" /* Enable IRQ, FIQ.             */
+                "MSR    CPSR, R0        \n\t" /* Write back modified value.   */
+                "LDMIA  SP!, {R0}" );         /* Pop R0.                      */
         }
     }
 }
diff --git a/portable/GCC/ARM7_AT91FR40008/portmacro.h b/portable/GCC/ARM7_AT91FR40008/portmacro.h
index 201f3c7a7..f0975cc3e 100644
--- a/portable/GCC/ARM7_AT91FR40008/portmacro.h
+++ b/portable/GCC/ARM7_AT91FR40008/portmacro.h
@@ -27,27 +27,27 @@
  */
 
 /*
-    Changes from V3.2.3
-
-    + Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1.
-
-    Changes from V3.2.4
-
-    + Removed the use of the %0 parameter within the assembler macros and
-      replaced them with hard coded registers.  This will ensure the
-      assembler does not select the link register as the temp register as
-      was occasionally happening previously.
-
-    + The assembler statements are now included in a single asm block rather
-      than each line having its own asm block.
-
-    Changes from V4.5.0
-
-    + Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros
-      and replaced them with portYIELD_FROM_ISR() macro.  Application code
-      should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT()
-      macros as per the V4.5.1 demo code.
-*/
+ *  Changes from V3.2.3
+ *
+ + Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1.
+ +
+ +  Changes from V3.2.4
+ +
+ + Removed the use of the %0 parameter within the assembler macros and
+ +    replaced them with hard coded registers.  This will ensure the
+ +    assembler does not select the link register as the temp register as
+ +    was occasionally happening previously.
+ +
+ + The assembler statements are now included in a single asm block rather
+ +    than each line having its own asm block.
+ +
+ +  Changes from V4.5.0
+ +
+ + Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros
+ +    and replaced them with portYIELD_FROM_ISR() macro.  Application code
+ +    should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT()
+ +    macros as per the V4.5.1 demo code.
+ */
 
 #ifndef PORTMACRO_H
 #define PORTMACRO_H
@@ -69,35 +69,35 @@
  */
 
 /* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint32_t
-#define portBASE_TYPE   long
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY ( TickType_t )    ( 0xFFFFFFFFUL )
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) ( 0xFFFFFFFFUL )
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portSTACK_GROWTH            ( -1 )
-#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT          8
-#define portYIELD()                 asm volatile ( "SWI 0" )
-#define portNOP()                   asm volatile ( "NOP" )
+#define portSTACK_GROWTH      ( -1 )
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT    8
+#define portYIELD()    asm volatile ( "SWI 0" )
+#define portNOP()      asm volatile ( "NOP" )
 
 /*
  * These define the timer to use for generating the tick interrupt.
@@ -118,90 +118,90 @@ typedef unsigned long UBaseType_t;
  * THUMB mode code will result in a compile time error.
  */
 
-#define portRESTORE_CONTEXT()                                           \
-{                                                                       \
-extern volatile void * volatile pxCurrentTCB;                           \
-extern volatile uint32_t ulCriticalNesting;                 \
-                                                                        \
-    /* Set the LR to the task stack. */                                 \
-    asm volatile (                                                      \
-    "LDR        R0, =pxCurrentTCB                               \n\t"   \
-    "LDR        R0, [R0]                                        \n\t"   \
-    "LDR        LR, [R0]                                        \n\t"   \
-                                                                        \
-    /* The critical nesting depth is the first item on the stack. */    \
-    /* Load it into the ulCriticalNesting variable. */                  \
-    "LDR        R0, =ulCriticalNesting                          \n\t"   \
-    "LDMFD  LR!, {R1}                                           \n\t"   \
-    "STR        R1, [R0]                                        \n\t"   \
-                                                                        \
-    /* Get the SPSR from the stack. */                                  \
-    "LDMFD  LR!, {R0}                                           \n\t"   \
-    "MSR        SPSR, R0                                        \n\t"   \
-                                                                        \
-    /* Restore all system mode registers for the task. */               \
-    "LDMFD  LR, {R0-R14}^                                       \n\t"   \
-    "NOP                                                        \n\t"   \
-                                                                        \
-    /* Restore the return address. */                                   \
-    "LDR        LR, [LR, #+60]                                  \n\t"   \
-                                                                        \
-    /* And return - correcting the offset in the LR to obtain the */    \
-    /* correct address. */                                              \
-    "SUBS   PC, LR, #4                                          \n\t"   \
-    );                                                                  \
-    ( void ) ulCriticalNesting;                                         \
-    ( void ) pxCurrentTCB;                                              \
-}
+#define portRESTORE_CONTEXT()                                                 \
+    {                                                                         \
+        extern volatile void * volatile pxCurrentTCB;                         \
+        extern volatile uint32_t ulCriticalNesting;                           \
+                                                                              \
+        /* Set the LR to the task stack. */                                   \
+        asm volatile (                                                        \
+            "LDR        R0, =pxCurrentTCB                               \n\t" \
+            "LDR        R0, [R0]                                        \n\t" \
+            "LDR        LR, [R0]                                        \n\t" \
+                                                                              \
+            /* The critical nesting depth is the first item on the stack. */  \
+            /* Load it into the ulCriticalNesting variable. */                \
+            "LDR        R0, =ulCriticalNesting                          \n\t" \
+            "LDMFD  LR!, {R1}                                           \n\t" \
+            "STR        R1, [R0]                                        \n\t" \
+                                                                              \
+            /* Get the SPSR from the stack. */                                \
+            "LDMFD  LR!, {R0}                                           \n\t" \
+            "MSR        SPSR, R0                                        \n\t" \
+                                                                              \
+            /* Restore all system mode registers for the task. */             \
+            "LDMFD  LR, {R0-R14}^                                       \n\t" \
+            "NOP                                                        \n\t" \
+                                                                              \
+            /* Restore the return address. */                                 \
+            "LDR        LR, [LR, #+60]                                  \n\t" \
+                                                                              \
+            /* And return - correcting the offset in the LR to obtain the */  \
+            /* correct address. */                                            \
+            "SUBS   PC, LR, #4                                          \n\t" \
+            );                                                                \
+        ( void ) ulCriticalNesting;                                           \
+        ( void ) pxCurrentTCB;                                                \
+    }
 /*-----------------------------------------------------------*/
 
-#define portSAVE_CONTEXT()                                              \
-{                                                                       \
-extern volatile void * volatile pxCurrentTCB;                           \
-extern volatile uint32_t ulCriticalNesting;                 \
-                                                                        \
-    /* Push R0 as we are going to use the register. */                  \
-    asm volatile (                                                      \
-    "STMDB  SP!, {R0}                                           \n\t"   \
-                                                                        \
-    /* Set R0 to point to the task stack pointer. */                    \
-    "STMDB  SP,{SP}^                                            \n\t"   \
-    "NOP                                                        \n\t"   \
-    "SUB    SP, SP, #4                                          \n\t"   \
-    "LDMIA  SP!,{R0}                                            \n\t"   \
-                                                                        \
-    /* Push the return address onto the stack. */                       \
-    "STMDB  R0!, {LR}                                           \n\t"   \
-                                                                        \
-    /* Now we have saved LR we can use it instead of R0. */             \
-    "MOV    LR, R0                                              \n\t"   \
-                                                                        \
-    /* Pop R0 so we can save it onto the system mode stack. */          \
-    "LDMIA  SP!, {R0}                                           \n\t"   \
-                                                                        \
-    /* Push all the system mode registers onto the task stack. */       \
-    "STMDB  LR,{R0-LR}^                                         \n\t"   \
-    "NOP                                                        \n\t"   \
-    "SUB    LR, LR, #60                                         \n\t"   \
-                                                                        \
-    /* Push the SPSR onto the task stack. */                            \
-    "MRS    R0, SPSR                                            \n\t"   \
-    "STMDB  LR!, {R0}                                           \n\t"   \
-                                                                        \
-    "LDR    R0, =ulCriticalNesting                              \n\t"   \
-    "LDR    R0, [R0]                                            \n\t"   \
-    "STMDB  LR!, {R0}                                           \n\t"   \
-                                                                        \
-    /* Store the new top of stack for the task. */                      \
-    "LDR    R0, =pxCurrentTCB                                   \n\t"   \
-    "LDR    R0, [R0]                                            \n\t"   \
-    "STR    LR, [R0]                                            \n\t"   \
-    );                                                                  \
-    ( void ) ulCriticalNesting;                                         \
-    ( void ) pxCurrentTCB;                                              \
-}
+#define portSAVE_CONTEXT()                                                    \
+    {                                                                         \
+        extern volatile void * volatile pxCurrentTCB;                         \
+        extern volatile uint32_t ulCriticalNesting;                           \
+                                                                              \
+        /* Push R0 as we are going to use the register. */                    \
+        asm volatile (                                                        \
+            "STMDB  SP!, {R0}                                           \n\t" \
+                                                                              \
+            /* Set R0 to point to the task stack pointer. */                  \
+            "STMDB  SP,{SP}^                                            \n\t" \
+            "NOP                                                        \n\t" \
+            "SUB    SP, SP, #4                                          \n\t" \
+            "LDMIA  SP!,{R0}                                            \n\t" \
+                                                                              \
+            /* Push the return address onto the stack. */                     \
+            "STMDB  R0!, {LR}                                           \n\t" \
+                                                                              \
+            /* Now we have saved LR we can use it instead of R0. */           \
+            "MOV    LR, R0                                              \n\t" \
+                                                                              \
+            /* Pop R0 so we can save it onto the system mode stack. */        \
+            "LDMIA  SP!, {R0}                                           \n\t" \
+                                                                              \
+            /* Push all the system mode registers onto the task stack. */     \
+            "STMDB  LR,{R0-LR}^                                         \n\t" \
+            "NOP                                                        \n\t" \
+            "SUB    LR, LR, #60                                         \n\t" \
+                                                                              \
+            /* Push the SPSR onto the task stack. */                          \
+            "MRS    R0, SPSR                                            \n\t" \
+            "STMDB  LR!, {R0}                                           \n\t" \
+                                                                              \
+            "LDR    R0, =ulCriticalNesting                              \n\t" \
+            "LDR    R0, [R0]                                            \n\t" \
+            "STMDB  LR!, {R0}                                           \n\t" \
+                                                                              \
+            /* Store the new top of stack for the task. */                    \
+            "LDR    R0, =pxCurrentTCB                                   \n\t" \
+            "LDR    R0, [R0]                                            \n\t" \
+            "STR    LR, [R0]                                            \n\t" \
+            );                                                                \
+        ( void ) ulCriticalNesting;                                           \
+        ( void ) pxCurrentTCB;                                                \
+    }
 
-#define portYIELD_FROM_ISR() vTaskSwitchContext()
+#define portYIELD_FROM_ISR()    vTaskSwitchContext()
 
 /* Critical section handling. */
 
@@ -214,43 +214,43 @@ extern volatile uint32_t ulCriticalNesting;                 \
 
 #ifdef THUMB_INTERWORK
 
-    extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
-    extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
+    extern void vPortDisableInterruptsFromThumb( void ) __attribute__( ( naked ) );
+    extern void vPortEnableInterruptsFromThumb( void ) __attribute__( ( naked ) );
 
     #define portDISABLE_INTERRUPTS()    vPortDisableInterruptsFromThumb()
     #define portENABLE_INTERRUPTS()     vPortEnableInterruptsFromThumb()
 
 #else
 
-    #define portDISABLE_INTERRUPTS()                                            \
-        asm volatile (                                                          \
-            "STMDB  SP!, {R0}       \n\t"   /* Push R0.                     */  \
-            "MRS    R0, CPSR        \n\t"   /* Get CPSR.                    */  \
-            "ORR    R0, R0, #0xC0   \n\t"   /* Disable IRQ, FIQ.            */  \
-            "MSR    CPSR, R0        \n\t"   /* Write back modified value.   */  \
-            "LDMIA  SP!, {R0}           " ) /* Pop R0.                      */
+    #define portDISABLE_INTERRUPTS()                                       \
+    asm volatile (                                                         \
+        "STMDB  SP!, {R0}       \n\t"   /* Push R0.                     */ \
+        "MRS    R0, CPSR        \n\t"   /* Get CPSR.                    */ \
+        "ORR    R0, R0, #0xC0   \n\t"   /* Disable IRQ, FIQ.            */ \
+        "MSR    CPSR, R0        \n\t"   /* Write back modified value.   */ \
+        "LDMIA  SP!, {R0}           " ) /* Pop R0.                      */
 
-    #define portENABLE_INTERRUPTS()                                             \
-        asm volatile (                                                          \
-            "STMDB  SP!, {R0}       \n\t"   /* Push R0.                     */  \
-            "MRS    R0, CPSR        \n\t"   /* Get CPSR.                    */  \
-            "BIC    R0, R0, #0xC0   \n\t"   /* Enable IRQ, FIQ.             */  \
-            "MSR    CPSR, R0        \n\t"   /* Write back modified value.   */  \
-            "LDMIA  SP!, {R0}           " ) /* Pop R0.                      */
+    #define portENABLE_INTERRUPTS()                                        \
+    asm volatile (                                                         \
+        "STMDB  SP!, {R0}       \n\t"   /* Push R0.                     */ \
+        "MRS    R0, CPSR        \n\t"   /* Get CPSR.                    */ \
+        "BIC    R0, R0, #0xC0   \n\t"   /* Enable IRQ, FIQ.             */ \
+        "MSR    CPSR, R0        \n\t"   /* Write back modified value.   */ \
+        "LDMIA  SP!, {R0}           " ) /* Pop R0.                      */
 
 #endif /* THUMB_INTERWORK */
 
 extern void vPortEnterCritical( void );
 extern void vPortExitCritical( void );
 
-#define portENTER_CRITICAL()        vPortEnterCritical();
-#define portEXIT_CRITICAL()         vPortExitCritical();
+#define portENTER_CRITICAL()    vPortEnterCritical();
+#define portEXIT_CRITICAL()     vPortExitCritical();
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/GCC/ARM7_AT91SAM7S/AT91SAM7X256.h b/portable/GCC/ARM7_AT91SAM7S/AT91SAM7X256.h
index d44cb286e..a335e4ad2 100644
--- a/portable/GCC/ARM7_AT91SAM7S/AT91SAM7X256.h
+++ b/portable/GCC/ARM7_AT91SAM7S/AT91SAM7X256.h
@@ -1,2731 +1,2759 @@
-//  ----------------------------------------------------------------------------
-//          ATMEL Microcontroller Software Support  -  ROUSSET  -
-//  ----------------------------------------------------------------------------
-//  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
-//  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
-//  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
-//  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
-//  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-//  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-//  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-//  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//  ----------------------------------------------------------------------------
-// File Name           : AT91SAM7X256.h
-// Object              : AT91SAM7X256 definitions
-// Generated           : AT91 SW Application Group  05/20/2005 (16:22:29)
-//
-// CVS Reference       : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005//
-// CVS Reference       : /SYS_SAM7X.pl/1.3/Tue Feb  1 17:01:43 2005//
-// CVS Reference       : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005//
-// CVS Reference       : /PMC_SAM7X.pl/1.4/Tue Feb  8 13:58:10 2005//
-// CVS Reference       : /RSTC_SAM7X.pl/1.1/Tue Feb  1 16:16:26 2005//
-// CVS Reference       : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005//
-// CVS Reference       : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005//
-// CVS Reference       : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//
-// CVS Reference       : /PIO_6057A.pl/1.2/Thu Feb  3 10:18:28 2005//
-// CVS Reference       : /RTTC_6081A.pl/1.2/Tue Nov  9 14:43:58 2004//
-// CVS Reference       : /PITC_6079A.pl/1.2/Tue Nov  9 14:43:56 2004//
-// CVS Reference       : /WDTC_6080A.pl/1.3/Tue Nov  9 14:44:00 2004//
-// CVS Reference       : /VREG_6085B.pl/1.1/Tue Feb  1 16:05:48 2005//
-// CVS Reference       : /PDC_6074C.pl/1.2/Thu Feb  3 08:48:54 2005//
-// CVS Reference       : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//
-// CVS Reference       : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//
-// CVS Reference       : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//
-// CVS Reference       : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//
-// CVS Reference       : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//
-// CVS Reference       : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//
-// CVS Reference       : /CAN_6019B.pl/1.1/Tue Mar  8 12:42:22 2005//
-// CVS Reference       : /EMACB_6119A.pl/1.5/Thu Feb  3 15:52:04 2005//
-// CVS Reference       : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//
-// CVS Reference       : /AES_6149A.pl/1.10/Mon Feb  7 09:44:25 2005//
-// CVS Reference       : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005//
-//  ----------------------------------------------------------------------------
+/*  ---------------------------------------------------------------------------- */
+/*          ATMEL Microcontroller Software Support  -  ROUSSET  - */
+/*  ---------------------------------------------------------------------------- */
+/*  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
+/*  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
+/*  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
+/*  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
+/*  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
+/*  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
+/*  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/*  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
+/*  ---------------------------------------------------------------------------- */
+/* File Name           : AT91SAM7X256.h */
+/* Object              : AT91SAM7X256 definitions */
+/* Generated           : AT91 SW Application Group  05/20/2005 (16:22:29) */
+/* */
+/* CVS Reference       : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005// */
+/* CVS Reference       : /SYS_SAM7X.pl/1.3/Tue Feb  1 17:01:43 2005// */
+/* CVS Reference       : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// */
+/* CVS Reference       : /PMC_SAM7X.pl/1.4/Tue Feb  8 13:58:10 2005// */
+/* CVS Reference       : /RSTC_SAM7X.pl/1.1/Tue Feb  1 16:16:26 2005// */
+/* CVS Reference       : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// */
+/* CVS Reference       : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// */
+/* CVS Reference       : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// */
+/* CVS Reference       : /PIO_6057A.pl/1.2/Thu Feb  3 10:18:28 2005// */
+/* CVS Reference       : /RTTC_6081A.pl/1.2/Tue Nov  9 14:43:58 2004// */
+/* CVS Reference       : /PITC_6079A.pl/1.2/Tue Nov  9 14:43:56 2004// */
+/* CVS Reference       : /WDTC_6080A.pl/1.3/Tue Nov  9 14:44:00 2004// */
+/* CVS Reference       : /VREG_6085B.pl/1.1/Tue Feb  1 16:05:48 2005// */
+/* CVS Reference       : /PDC_6074C.pl/1.2/Thu Feb  3 08:48:54 2005// */
+/* CVS Reference       : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// */
+/* CVS Reference       : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// */
+/* CVS Reference       : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// */
+/* CVS Reference       : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// */
+/* CVS Reference       : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// */
+/* CVS Reference       : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// */
+/* CVS Reference       : /CAN_6019B.pl/1.1/Tue Mar  8 12:42:22 2005// */
+/* CVS Reference       : /EMACB_6119A.pl/1.5/Thu Feb  3 15:52:04 2005// */
+/* CVS Reference       : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// */
+/* CVS Reference       : /AES_6149A.pl/1.10/Mon Feb  7 09:44:25 2005// */
+/* CVS Reference       : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// */
+/*  ---------------------------------------------------------------------------- */
 
 #ifndef AT91SAM7X256_H
 #define AT91SAM7X256_H
 
-typedef volatile unsigned int AT91_REG;// Hardware register definition
+typedef volatile unsigned int AT91_REG; /* Hardware register definition */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR System Peripherals
-// *****************************************************************************
-typedef struct _AT91S_SYS {
-    AT91_REG     AIC_SMR[32];   // Source Mode Register
-    AT91_REG     AIC_SVR[32];   // Source Vector Register
-    AT91_REG     AIC_IVR;   // IRQ Vector Register
-    AT91_REG     AIC_FVR;   // FIQ Vector Register
-    AT91_REG     AIC_ISR;   // Interrupt Status Register
-    AT91_REG     AIC_IPR;   // Interrupt Pending Register
-    AT91_REG     AIC_IMR;   // Interrupt Mask Register
-    AT91_REG     AIC_CISR;  // Core Interrupt Status Register
-    AT91_REG     Reserved0[2];  //
-    AT91_REG     AIC_IECR;  // Interrupt Enable Command Register
-    AT91_REG     AIC_IDCR;  // Interrupt Disable Command Register
-    AT91_REG     AIC_ICCR;  // Interrupt Clear Command Register
-    AT91_REG     AIC_ISCR;  // Interrupt Set Command Register
-    AT91_REG     AIC_EOICR;     // End of Interrupt Command Register
-    AT91_REG     AIC_SPU;   // Spurious Vector Register
-    AT91_REG     AIC_DCR;   // Debug Control Register (Protect)
-    AT91_REG     Reserved1[1];  //
-    AT91_REG     AIC_FFER;  // Fast Forcing Enable Register
-    AT91_REG     AIC_FFDR;  // Fast Forcing Disable Register
-    AT91_REG     AIC_FFSR;  // Fast Forcing Status Register
-    AT91_REG     Reserved2[45];     //
-    AT91_REG     DBGU_CR;   // Control Register
-    AT91_REG     DBGU_MR;   // Mode Register
-    AT91_REG     DBGU_IER;  // Interrupt Enable Register
-    AT91_REG     DBGU_IDR;  // Interrupt Disable Register
-    AT91_REG     DBGU_IMR;  // Interrupt Mask Register
-    AT91_REG     DBGU_CSR;  // Channel Status Register
-    AT91_REG     DBGU_RHR;  // Receiver Holding Register
-    AT91_REG     DBGU_THR;  // Transmitter Holding Register
-    AT91_REG     DBGU_BRGR;     // Baud Rate Generator Register
-    AT91_REG     Reserved3[7];  //
-    AT91_REG     DBGU_CIDR;     // Chip ID Register
-    AT91_REG     DBGU_EXID;     // Chip ID Extension Register
-    AT91_REG     DBGU_FNTR;     // Force NTRST Register
-    AT91_REG     Reserved4[45];     //
-    AT91_REG     DBGU_RPR;  // Receive Pointer Register
-    AT91_REG     DBGU_RCR;  // Receive Counter Register
-    AT91_REG     DBGU_TPR;  // Transmit Pointer Register
-    AT91_REG     DBGU_TCR;  // Transmit Counter Register
-    AT91_REG     DBGU_RNPR;     // Receive Next Pointer Register
-    AT91_REG     DBGU_RNCR;     // Receive Next Counter Register
-    AT91_REG     DBGU_TNPR;     // Transmit Next Pointer Register
-    AT91_REG     DBGU_TNCR;     // Transmit Next Counter Register
-    AT91_REG     DBGU_PTCR;     // PDC Transfer Control Register
-    AT91_REG     DBGU_PTSR;     // PDC Transfer Status Register
-    AT91_REG     Reserved5[54];     //
-    AT91_REG     PIOA_PER;  // PIO Enable Register
-    AT91_REG     PIOA_PDR;  // PIO Disable Register
-    AT91_REG     PIOA_PSR;  // PIO Status Register
-    AT91_REG     Reserved6[1];  //
-    AT91_REG     PIOA_OER;  // Output Enable Register
-    AT91_REG     PIOA_ODR;  // Output Disable Registerr
-    AT91_REG     PIOA_OSR;  // Output Status Register
-    AT91_REG     Reserved7[1];  //
-    AT91_REG     PIOA_IFER;     // Input Filter Enable Register
-    AT91_REG     PIOA_IFDR;     // Input Filter Disable Register
-    AT91_REG     PIOA_IFSR;     // Input Filter Status Register
-    AT91_REG     Reserved8[1];  //
-    AT91_REG     PIOA_SODR;     // Set Output Data Register
-    AT91_REG     PIOA_CODR;     // Clear Output Data Register
-    AT91_REG     PIOA_ODSR;     // Output Data Status Register
-    AT91_REG     PIOA_PDSR;     // Pin Data Status Register
-    AT91_REG     PIOA_IER;  // Interrupt Enable Register
-    AT91_REG     PIOA_IDR;  // Interrupt Disable Register
-    AT91_REG     PIOA_IMR;  // Interrupt Mask Register
-    AT91_REG     PIOA_ISR;  // Interrupt Status Register
-    AT91_REG     PIOA_MDER;     // Multi-driver Enable Register
-    AT91_REG     PIOA_MDDR;     // Multi-driver Disable Register
-    AT91_REG     PIOA_MDSR;     // Multi-driver Status Register
-    AT91_REG     Reserved9[1];  //
-    AT91_REG     PIOA_PPUDR;    // Pull-up Disable Register
-    AT91_REG     PIOA_PPUER;    // Pull-up Enable Register
-    AT91_REG     PIOA_PPUSR;    // Pull-up Status Register
-    AT91_REG     Reserved10[1];     //
-    AT91_REG     PIOA_ASR;  // Select A Register
-    AT91_REG     PIOA_BSR;  // Select B Register
-    AT91_REG     PIOA_ABSR;     // AB Select Status Register
-    AT91_REG     Reserved11[9];     //
-    AT91_REG     PIOA_OWER;     // Output Write Enable Register
-    AT91_REG     PIOA_OWDR;     // Output Write Disable Register
-    AT91_REG     PIOA_OWSR;     // Output Write Status Register
-    AT91_REG     Reserved12[85];    //
-    AT91_REG     PIOB_PER;  // PIO Enable Register
-    AT91_REG     PIOB_PDR;  // PIO Disable Register
-    AT91_REG     PIOB_PSR;  // PIO Status Register
-    AT91_REG     Reserved13[1];     //
-    AT91_REG     PIOB_OER;  // Output Enable Register
-    AT91_REG     PIOB_ODR;  // Output Disable Registerr
-    AT91_REG     PIOB_OSR;  // Output Status Register
-    AT91_REG     Reserved14[1];     //
-    AT91_REG     PIOB_IFER;     // Input Filter Enable Register
-    AT91_REG     PIOB_IFDR;     // Input Filter Disable Register
-    AT91_REG     PIOB_IFSR;     // Input Filter Status Register
-    AT91_REG     Reserved15[1];     //
-    AT91_REG     PIOB_SODR;     // Set Output Data Register
-    AT91_REG     PIOB_CODR;     // Clear Output Data Register
-    AT91_REG     PIOB_ODSR;     // Output Data Status Register
-    AT91_REG     PIOB_PDSR;     // Pin Data Status Register
-    AT91_REG     PIOB_IER;  // Interrupt Enable Register
-    AT91_REG     PIOB_IDR;  // Interrupt Disable Register
-    AT91_REG     PIOB_IMR;  // Interrupt Mask Register
-    AT91_REG     PIOB_ISR;  // Interrupt Status Register
-    AT91_REG     PIOB_MDER;     // Multi-driver Enable Register
-    AT91_REG     PIOB_MDDR;     // Multi-driver Disable Register
-    AT91_REG     PIOB_MDSR;     // Multi-driver Status Register
-    AT91_REG     Reserved16[1];     //
-    AT91_REG     PIOB_PPUDR;    // Pull-up Disable Register
-    AT91_REG     PIOB_PPUER;    // Pull-up Enable Register
-    AT91_REG     PIOB_PPUSR;    // Pull-up Status Register
-    AT91_REG     Reserved17[1];     //
-    AT91_REG     PIOB_ASR;  // Select A Register
-    AT91_REG     PIOB_BSR;  // Select B Register
-    AT91_REG     PIOB_ABSR;     // AB Select Status Register
-    AT91_REG     Reserved18[9];     //
-    AT91_REG     PIOB_OWER;     // Output Write Enable Register
-    AT91_REG     PIOB_OWDR;     // Output Write Disable Register
-    AT91_REG     PIOB_OWSR;     // Output Write Status Register
-    AT91_REG     Reserved19[341];   //
-    AT91_REG     PMC_SCER;  // System Clock Enable Register
-    AT91_REG     PMC_SCDR;  // System Clock Disable Register
-    AT91_REG     PMC_SCSR;  // System Clock Status Register
-    AT91_REG     Reserved20[1];     //
-    AT91_REG     PMC_PCER;  // Peripheral Clock Enable Register
-    AT91_REG     PMC_PCDR;  // Peripheral Clock Disable Register
-    AT91_REG     PMC_PCSR;  // Peripheral Clock Status Register
-    AT91_REG     Reserved21[1];     //
-    AT91_REG     PMC_MOR;   // Main Oscillator Register
-    AT91_REG     PMC_MCFR;  // Main Clock  Frequency Register
-    AT91_REG     Reserved22[1];     //
-    AT91_REG     PMC_PLLR;  // PLL Register
-    AT91_REG     PMC_MCKR;  // Master Clock Register
-    AT91_REG     Reserved23[3];     //
-    AT91_REG     PMC_PCKR[4];   // Programmable Clock Register
-    AT91_REG     Reserved24[4];     //
-    AT91_REG     PMC_IER;   // Interrupt Enable Register
-    AT91_REG     PMC_IDR;   // Interrupt Disable Register
-    AT91_REG     PMC_SR;    // Status Register
-    AT91_REG     PMC_IMR;   // Interrupt Mask Register
-    AT91_REG     Reserved25[36];    //
-    AT91_REG     RSTC_RCR;  // Reset Control Register
-    AT91_REG     RSTC_RSR;  // Reset Status Register
-    AT91_REG     RSTC_RMR;  // Reset Mode Register
-    AT91_REG     Reserved26[5];     //
-    AT91_REG     RTTC_RTMR;     // Real-time Mode Register
-    AT91_REG     RTTC_RTAR;     // Real-time Alarm Register
-    AT91_REG     RTTC_RTVR;     // Real-time Value Register
-    AT91_REG     RTTC_RTSR;     // Real-time Status Register
-    AT91_REG     PITC_PIMR;     // Period Interval Mode Register
-    AT91_REG     PITC_PISR;     // Period Interval Status Register
-    AT91_REG     PITC_PIVR;     // Period Interval Value Register
-    AT91_REG     PITC_PIIR;     // Period Interval Image Register
-    AT91_REG     WDTC_WDCR;     // Watchdog Control Register
-    AT91_REG     WDTC_WDMR;     // Watchdog Mode Register
-    AT91_REG     WDTC_WDSR;     // Watchdog Status Register
-    AT91_REG     Reserved27[5];     //
-    AT91_REG     VREG_MR;   // Voltage Regulator Mode Register
-} AT91S_SYS, *AT91PS_SYS;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR System Peripherals */
+/* ***************************************************************************** */
+typedef struct _AT91S_SYS
+{
+    AT91_REG AIC_SMR[ 32 ];     /* Source Mode Register */
+    AT91_REG AIC_SVR[ 32 ];     /* Source Vector Register */
+    AT91_REG AIC_IVR;           /* IRQ Vector Register */
+    AT91_REG AIC_FVR;           /* FIQ Vector Register */
+    AT91_REG AIC_ISR;           /* Interrupt Status Register */
+    AT91_REG AIC_IPR;           /* Interrupt Pending Register */
+    AT91_REG AIC_IMR;           /* Interrupt Mask Register */
+    AT91_REG AIC_CISR;          /* Core Interrupt Status Register */
+    AT91_REG Reserved0[ 2 ];    /* */
+    AT91_REG AIC_IECR;          /* Interrupt Enable Command Register */
+    AT91_REG AIC_IDCR;          /* Interrupt Disable Command Register */
+    AT91_REG AIC_ICCR;          /* Interrupt Clear Command Register */
+    AT91_REG AIC_ISCR;          /* Interrupt Set Command Register */
+    AT91_REG AIC_EOICR;         /* End of Interrupt Command Register */
+    AT91_REG AIC_SPU;           /* Spurious Vector Register */
+    AT91_REG AIC_DCR;           /* Debug Control Register (Protect) */
+    AT91_REG Reserved1[ 1 ];    /* */
+    AT91_REG AIC_FFER;          /* Fast Forcing Enable Register */
+    AT91_REG AIC_FFDR;          /* Fast Forcing Disable Register */
+    AT91_REG AIC_FFSR;          /* Fast Forcing Status Register */
+    AT91_REG Reserved2[ 45 ];   /* */
+    AT91_REG DBGU_CR;           /* Control Register */
+    AT91_REG DBGU_MR;           /* Mode Register */
+    AT91_REG DBGU_IER;          /* Interrupt Enable Register */
+    AT91_REG DBGU_IDR;          /* Interrupt Disable Register */
+    AT91_REG DBGU_IMR;          /* Interrupt Mask Register */
+    AT91_REG DBGU_CSR;          /* Channel Status Register */
+    AT91_REG DBGU_RHR;          /* Receiver Holding Register */
+    AT91_REG DBGU_THR;          /* Transmitter Holding Register */
+    AT91_REG DBGU_BRGR;         /* Baud Rate Generator Register */
+    AT91_REG Reserved3[ 7 ];    /* */
+    AT91_REG DBGU_CIDR;         /* Chip ID Register */
+    AT91_REG DBGU_EXID;         /* Chip ID Extension Register */
+    AT91_REG DBGU_FNTR;         /* Force NTRST Register */
+    AT91_REG Reserved4[ 45 ];   /* */
+    AT91_REG DBGU_RPR;          /* Receive Pointer Register */
+    AT91_REG DBGU_RCR;          /* Receive Counter Register */
+    AT91_REG DBGU_TPR;          /* Transmit Pointer Register */
+    AT91_REG DBGU_TCR;          /* Transmit Counter Register */
+    AT91_REG DBGU_RNPR;         /* Receive Next Pointer Register */
+    AT91_REG DBGU_RNCR;         /* Receive Next Counter Register */
+    AT91_REG DBGU_TNPR;         /* Transmit Next Pointer Register */
+    AT91_REG DBGU_TNCR;         /* Transmit Next Counter Register */
+    AT91_REG DBGU_PTCR;         /* PDC Transfer Control Register */
+    AT91_REG DBGU_PTSR;         /* PDC Transfer Status Register */
+    AT91_REG Reserved5[ 54 ];   /* */
+    AT91_REG PIOA_PER;          /* PIO Enable Register */
+    AT91_REG PIOA_PDR;          /* PIO Disable Register */
+    AT91_REG PIOA_PSR;          /* PIO Status Register */
+    AT91_REG Reserved6[ 1 ];    /* */
+    AT91_REG PIOA_OER;          /* Output Enable Register */
+    AT91_REG PIOA_ODR;          /* Output Disable Registerr */
+    AT91_REG PIOA_OSR;          /* Output Status Register */
+    AT91_REG Reserved7[ 1 ];    /* */
+    AT91_REG PIOA_IFER;         /* Input Filter Enable Register */
+    AT91_REG PIOA_IFDR;         /* Input Filter Disable Register */
+    AT91_REG PIOA_IFSR;         /* Input Filter Status Register */
+    AT91_REG Reserved8[ 1 ];    /* */
+    AT91_REG PIOA_SODR;         /* Set Output Data Register */
+    AT91_REG PIOA_CODR;         /* Clear Output Data Register */
+    AT91_REG PIOA_ODSR;         /* Output Data Status Register */
+    AT91_REG PIOA_PDSR;         /* Pin Data Status Register */
+    AT91_REG PIOA_IER;          /* Interrupt Enable Register */
+    AT91_REG PIOA_IDR;          /* Interrupt Disable Register */
+    AT91_REG PIOA_IMR;          /* Interrupt Mask Register */
+    AT91_REG PIOA_ISR;          /* Interrupt Status Register */
+    AT91_REG PIOA_MDER;         /* Multi-driver Enable Register */
+    AT91_REG PIOA_MDDR;         /* Multi-driver Disable Register */
+    AT91_REG PIOA_MDSR;         /* Multi-driver Status Register */
+    AT91_REG Reserved9[ 1 ];    /* */
+    AT91_REG PIOA_PPUDR;        /* Pull-up Disable Register */
+    AT91_REG PIOA_PPUER;        /* Pull-up Enable Register */
+    AT91_REG PIOA_PPUSR;        /* Pull-up Status Register */
+    AT91_REG Reserved10[ 1 ];   /* */
+    AT91_REG PIOA_ASR;          /* Select A Register */
+    AT91_REG PIOA_BSR;          /* Select B Register */
+    AT91_REG PIOA_ABSR;         /* AB Select Status Register */
+    AT91_REG Reserved11[ 9 ];   /* */
+    AT91_REG PIOA_OWER;         /* Output Write Enable Register */
+    AT91_REG PIOA_OWDR;         /* Output Write Disable Register */
+    AT91_REG PIOA_OWSR;         /* Output Write Status Register */
+    AT91_REG Reserved12[ 85 ];  /* */
+    AT91_REG PIOB_PER;          /* PIO Enable Register */
+    AT91_REG PIOB_PDR;          /* PIO Disable Register */
+    AT91_REG PIOB_PSR;          /* PIO Status Register */
+    AT91_REG Reserved13[ 1 ];   /* */
+    AT91_REG PIOB_OER;          /* Output Enable Register */
+    AT91_REG PIOB_ODR;          /* Output Disable Registerr */
+    AT91_REG PIOB_OSR;          /* Output Status Register */
+    AT91_REG Reserved14[ 1 ];   /* */
+    AT91_REG PIOB_IFER;         /* Input Filter Enable Register */
+    AT91_REG PIOB_IFDR;         /* Input Filter Disable Register */
+    AT91_REG PIOB_IFSR;         /* Input Filter Status Register */
+    AT91_REG Reserved15[ 1 ];   /* */
+    AT91_REG PIOB_SODR;         /* Set Output Data Register */
+    AT91_REG PIOB_CODR;         /* Clear Output Data Register */
+    AT91_REG PIOB_ODSR;         /* Output Data Status Register */
+    AT91_REG PIOB_PDSR;         /* Pin Data Status Register */
+    AT91_REG PIOB_IER;          /* Interrupt Enable Register */
+    AT91_REG PIOB_IDR;          /* Interrupt Disable Register */
+    AT91_REG PIOB_IMR;          /* Interrupt Mask Register */
+    AT91_REG PIOB_ISR;          /* Interrupt Status Register */
+    AT91_REG PIOB_MDER;         /* Multi-driver Enable Register */
+    AT91_REG PIOB_MDDR;         /* Multi-driver Disable Register */
+    AT91_REG PIOB_MDSR;         /* Multi-driver Status Register */
+    AT91_REG Reserved16[ 1 ];   /* */
+    AT91_REG PIOB_PPUDR;        /* Pull-up Disable Register */
+    AT91_REG PIOB_PPUER;        /* Pull-up Enable Register */
+    AT91_REG PIOB_PPUSR;        /* Pull-up Status Register */
+    AT91_REG Reserved17[ 1 ];   /* */
+    AT91_REG PIOB_ASR;          /* Select A Register */
+    AT91_REG PIOB_BSR;          /* Select B Register */
+    AT91_REG PIOB_ABSR;         /* AB Select Status Register */
+    AT91_REG Reserved18[ 9 ];   /* */
+    AT91_REG PIOB_OWER;         /* Output Write Enable Register */
+    AT91_REG PIOB_OWDR;         /* Output Write Disable Register */
+    AT91_REG PIOB_OWSR;         /* Output Write Status Register */
+    AT91_REG Reserved19[ 341 ]; /* */
+    AT91_REG PMC_SCER;          /* System Clock Enable Register */
+    AT91_REG PMC_SCDR;          /* System Clock Disable Register */
+    AT91_REG PMC_SCSR;          /* System Clock Status Register */
+    AT91_REG Reserved20[ 1 ];   /* */
+    AT91_REG PMC_PCER;          /* Peripheral Clock Enable Register */
+    AT91_REG PMC_PCDR;          /* Peripheral Clock Disable Register */
+    AT91_REG PMC_PCSR;          /* Peripheral Clock Status Register */
+    AT91_REG Reserved21[ 1 ];   /* */
+    AT91_REG PMC_MOR;           /* Main Oscillator Register */
+    AT91_REG PMC_MCFR;          /* Main Clock  Frequency Register */
+    AT91_REG Reserved22[ 1 ];   /* */
+    AT91_REG PMC_PLLR;          /* PLL Register */
+    AT91_REG PMC_MCKR;          /* Master Clock Register */
+    AT91_REG Reserved23[ 3 ];   /* */
+    AT91_REG PMC_PCKR[ 4 ];     /* Programmable Clock Register */
+    AT91_REG Reserved24[ 4 ];   /* */
+    AT91_REG PMC_IER;           /* Interrupt Enable Register */
+    AT91_REG PMC_IDR;           /* Interrupt Disable Register */
+    AT91_REG PMC_SR;            /* Status Register */
+    AT91_REG PMC_IMR;           /* Interrupt Mask Register */
+    AT91_REG Reserved25[ 36 ];  /* */
+    AT91_REG RSTC_RCR;          /* Reset Control Register */
+    AT91_REG RSTC_RSR;          /* Reset Status Register */
+    AT91_REG RSTC_RMR;          /* Reset Mode Register */
+    AT91_REG Reserved26[ 5 ];   /* */
+    AT91_REG RTTC_RTMR;         /* Real-time Mode Register */
+    AT91_REG RTTC_RTAR;         /* Real-time Alarm Register */
+    AT91_REG RTTC_RTVR;         /* Real-time Value Register */
+    AT91_REG RTTC_RTSR;         /* Real-time Status Register */
+    AT91_REG PITC_PIMR;         /* Period Interval Mode Register */
+    AT91_REG PITC_PISR;         /* Period Interval Status Register */
+    AT91_REG PITC_PIVR;         /* Period Interval Value Register */
+    AT91_REG PITC_PIIR;         /* Period Interval Image Register */
+    AT91_REG WDTC_WDCR;         /* Watchdog Control Register */
+    AT91_REG WDTC_WDMR;         /* Watchdog Mode Register */
+    AT91_REG WDTC_WDSR;         /* Watchdog Status Register */
+    AT91_REG Reserved27[ 5 ];   /* */
+    AT91_REG VREG_MR;           /* Voltage Regulator Mode Register */
+} AT91S_SYS, * AT91PS_SYS;
 
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
-// *****************************************************************************
-typedef struct _AT91S_AIC {
-    AT91_REG     AIC_SMR[32];   // Source Mode Register
-    AT91_REG     AIC_SVR[32];   // Source Vector Register
-    AT91_REG     AIC_IVR;   // IRQ Vector Register
-    AT91_REG     AIC_FVR;   // FIQ Vector Register
-    AT91_REG     AIC_ISR;   // Interrupt Status Register
-    AT91_REG     AIC_IPR;   // Interrupt Pending Register
-    AT91_REG     AIC_IMR;   // Interrupt Mask Register
-    AT91_REG     AIC_CISR;  // Core Interrupt Status Register
-    AT91_REG     Reserved0[2];  //
-    AT91_REG     AIC_IECR;  // Interrupt Enable Command Register
-    AT91_REG     AIC_IDCR;  // Interrupt Disable Command Register
-    AT91_REG     AIC_ICCR;  // Interrupt Clear Command Register
-    AT91_REG     AIC_ISCR;  // Interrupt Set Command Register
-    AT91_REG     AIC_EOICR;     // End of Interrupt Command Register
-    AT91_REG     AIC_SPU;   // Spurious Vector Register
-    AT91_REG     AIC_DCR;   // Debug Control Register (Protect)
-    AT91_REG     Reserved1[1];  //
-    AT91_REG     AIC_FFER;  // Fast Forcing Enable Register
-    AT91_REG     AIC_FFDR;  // Fast Forcing Disable Register
-    AT91_REG     AIC_FFSR;  // Fast Forcing Status Register
-} AT91S_AIC, *AT91PS_AIC;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller */
+/* ***************************************************************************** */
+typedef struct _AT91S_AIC
+{
+    AT91_REG AIC_SMR[ 32 ];  /* Source Mode Register */
+    AT91_REG AIC_SVR[ 32 ];  /* Source Vector Register */
+    AT91_REG AIC_IVR;        /* IRQ Vector Register */
+    AT91_REG AIC_FVR;        /* FIQ Vector Register */
+    AT91_REG AIC_ISR;        /* Interrupt Status Register */
+    AT91_REG AIC_IPR;        /* Interrupt Pending Register */
+    AT91_REG AIC_IMR;        /* Interrupt Mask Register */
+    AT91_REG AIC_CISR;       /* Core Interrupt Status Register */
+    AT91_REG Reserved0[ 2 ]; /* */
+    AT91_REG AIC_IECR;       /* Interrupt Enable Command Register */
+    AT91_REG AIC_IDCR;       /* Interrupt Disable Command Register */
+    AT91_REG AIC_ICCR;       /* Interrupt Clear Command Register */
+    AT91_REG AIC_ISCR;       /* Interrupt Set Command Register */
+    AT91_REG AIC_EOICR;      /* End of Interrupt Command Register */
+    AT91_REG AIC_SPU;        /* Spurious Vector Register */
+    AT91_REG AIC_DCR;        /* Debug Control Register (Protect) */
+    AT91_REG Reserved1[ 1 ]; /* */
+    AT91_REG AIC_FFER;       /* Fast Forcing Enable Register */
+    AT91_REG AIC_FFDR;       /* Fast Forcing Disable Register */
+    AT91_REG AIC_FFSR;       /* Fast Forcing Status Register */
+} AT91S_AIC, * AT91PS_AIC;
 
-// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
-#define AT91C_AIC_PRIOR       ((unsigned int) 0x7 <<  0) // (AIC) Priority Level
-#define     AT91C_AIC_PRIOR_LOWEST               ((unsigned int) 0x0) // (AIC) Lowest priority level
-#define     AT91C_AIC_PRIOR_HIGHEST              ((unsigned int) 0x7) // (AIC) Highest priority level
-#define AT91C_AIC_SRCTYPE     ((unsigned int) 0x3 <<  5) // (AIC) Interrupt Source Type
-#define     AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL       ((unsigned int) 0x0 <<  5) // (AIC) Internal Sources Code Label High-level Sensitive
-#define     AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL        ((unsigned int) 0x0 <<  5) // (AIC) External Sources Code Label Low-level Sensitive
-#define     AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE    ((unsigned int) 0x1 <<  5) // (AIC) Internal Sources Code Label Positive Edge triggered
-#define     AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE    ((unsigned int) 0x1 <<  5) // (AIC) External Sources Code Label Negative Edge triggered
-#define     AT91C_AIC_SRCTYPE_HIGH_LEVEL           ((unsigned int) 0x2 <<  5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
-#define     AT91C_AIC_SRCTYPE_POSITIVE_EDGE        ((unsigned int) 0x3 <<  5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
-// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
-#define AT91C_AIC_NFIQ        ((unsigned int) 0x1 <<  0) // (AIC) NFIQ Status
-#define AT91C_AIC_NIRQ        ((unsigned int) 0x1 <<  1) // (AIC) NIRQ Status
-// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
-#define AT91C_AIC_DCR_PROT    ((unsigned int) 0x1 <<  0) // (AIC) Protection Mode
-#define AT91C_AIC_DCR_GMSK    ((unsigned int) 0x1 <<  1) // (AIC) General Mask
+/* -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- */
+#define AT91C_AIC_PRIOR                            ( ( unsigned int ) 0x7 << 0 ) /* (AIC) Priority Level */
+#define     AT91C_AIC_PRIOR_LOWEST                 ( ( unsigned int ) 0x0 )      /* (AIC) Lowest priority level */
+#define     AT91C_AIC_PRIOR_HIGHEST                ( ( unsigned int ) 0x7 )      /* (AIC) Highest priority level */
+#define AT91C_AIC_SRCTYPE                          ( ( unsigned int ) 0x3 << 5 ) /* (AIC) Interrupt Source Type */
+#define     AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL       ( ( unsigned int ) 0x0 << 5 ) /* (AIC) Internal Sources Code Label High-level Sensitive */
+#define     AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL        ( ( unsigned int ) 0x0 << 5 ) /* (AIC) External Sources Code Label Low-level Sensitive */
+#define     AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE    ( ( unsigned int ) 0x1 << 5 ) /* (AIC) Internal Sources Code Label Positive Edge triggered */
+#define     AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE    ( ( unsigned int ) 0x1 << 5 ) /* (AIC) External Sources Code Label Negative Edge triggered */
+#define     AT91C_AIC_SRCTYPE_HIGH_LEVEL           ( ( unsigned int ) 0x2 << 5 ) /* (AIC) Internal Or External Sources Code Label High-level Sensitive */
+#define     AT91C_AIC_SRCTYPE_POSITIVE_EDGE        ( ( unsigned int ) 0x3 << 5 ) /* (AIC) Internal Or External Sources Code Label Positive Edge triggered */
+/* -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- */
+#define AT91C_AIC_NFIQ                             ( ( unsigned int ) 0x1 << 0 ) /* (AIC) NFIQ Status */
+#define AT91C_AIC_NIRQ                             ( ( unsigned int ) 0x1 << 1 ) /* (AIC) NIRQ Status */
+/* -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- */
+#define AT91C_AIC_DCR_PROT                         ( ( unsigned int ) 0x1 << 0 ) /* (AIC) Protection Mode */
+#define AT91C_AIC_DCR_GMSK                         ( ( unsigned int ) 0x1 << 1 ) /* (AIC) General Mask */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller
-// *****************************************************************************
-typedef struct _AT91S_PDC {
-    AT91_REG     PDC_RPR;   // Receive Pointer Register
-    AT91_REG     PDC_RCR;   // Receive Counter Register
-    AT91_REG     PDC_TPR;   // Transmit Pointer Register
-    AT91_REG     PDC_TCR;   // Transmit Counter Register
-    AT91_REG     PDC_RNPR;  // Receive Next Pointer Register
-    AT91_REG     PDC_RNCR;  // Receive Next Counter Register
-    AT91_REG     PDC_TNPR;  // Transmit Next Pointer Register
-    AT91_REG     PDC_TNCR;  // Transmit Next Counter Register
-    AT91_REG     PDC_PTCR;  // PDC Transfer Control Register
-    AT91_REG     PDC_PTSR;  // PDC Transfer Status Register
-} AT91S_PDC, *AT91PS_PDC;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller */
+/* ***************************************************************************** */
+typedef struct _AT91S_PDC
+{
+    AT91_REG PDC_RPR;  /* Receive Pointer Register */
+    AT91_REG PDC_RCR;  /* Receive Counter Register */
+    AT91_REG PDC_TPR;  /* Transmit Pointer Register */
+    AT91_REG PDC_TCR;  /* Transmit Counter Register */
+    AT91_REG PDC_RNPR; /* Receive Next Pointer Register */
+    AT91_REG PDC_RNCR; /* Receive Next Counter Register */
+    AT91_REG PDC_TNPR; /* Transmit Next Pointer Register */
+    AT91_REG PDC_TNCR; /* Transmit Next Counter Register */
+    AT91_REG PDC_PTCR; /* PDC Transfer Control Register */
+    AT91_REG PDC_PTSR; /* PDC Transfer Status Register */
+} AT91S_PDC, * AT91PS_PDC;
 
-// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
-#define AT91C_PDC_RXTEN       ((unsigned int) 0x1 <<  0) // (PDC) Receiver Transfer Enable
-#define AT91C_PDC_RXTDIS      ((unsigned int) 0x1 <<  1) // (PDC) Receiver Transfer Disable
-#define AT91C_PDC_TXTEN       ((unsigned int) 0x1 <<  8) // (PDC) Transmitter Transfer Enable
-#define AT91C_PDC_TXTDIS      ((unsigned int) 0x1 <<  9) // (PDC) Transmitter Transfer Disable
-// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
+/* -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */
+#define AT91C_PDC_RXTEN     ( ( unsigned int ) 0x1 << 0 ) /* (PDC) Receiver Transfer Enable */
+#define AT91C_PDC_RXTDIS    ( ( unsigned int ) 0x1 << 1 ) /* (PDC) Receiver Transfer Disable */
+#define AT91C_PDC_TXTEN     ( ( unsigned int ) 0x1 << 8 ) /* (PDC) Transmitter Transfer Enable */
+#define AT91C_PDC_TXTDIS    ( ( unsigned int ) 0x1 << 9 ) /* (PDC) Transmitter Transfer Disable */
+/* -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Debug Unit
-// *****************************************************************************
-typedef struct _AT91S_DBGU {
-    AT91_REG     DBGU_CR;   // Control Register
-    AT91_REG     DBGU_MR;   // Mode Register
-    AT91_REG     DBGU_IER;  // Interrupt Enable Register
-    AT91_REG     DBGU_IDR;  // Interrupt Disable Register
-    AT91_REG     DBGU_IMR;  // Interrupt Mask Register
-    AT91_REG     DBGU_CSR;  // Channel Status Register
-    AT91_REG     DBGU_RHR;  // Receiver Holding Register
-    AT91_REG     DBGU_THR;  // Transmitter Holding Register
-    AT91_REG     DBGU_BRGR;     // Baud Rate Generator Register
-    AT91_REG     Reserved0[7];  //
-    AT91_REG     DBGU_CIDR;     // Chip ID Register
-    AT91_REG     DBGU_EXID;     // Chip ID Extension Register
-    AT91_REG     DBGU_FNTR;     // Force NTRST Register
-    AT91_REG     Reserved1[45];     //
-    AT91_REG     DBGU_RPR;  // Receive Pointer Register
-    AT91_REG     DBGU_RCR;  // Receive Counter Register
-    AT91_REG     DBGU_TPR;  // Transmit Pointer Register
-    AT91_REG     DBGU_TCR;  // Transmit Counter Register
-    AT91_REG     DBGU_RNPR;     // Receive Next Pointer Register
-    AT91_REG     DBGU_RNCR;     // Receive Next Counter Register
-    AT91_REG     DBGU_TNPR;     // Transmit Next Pointer Register
-    AT91_REG     DBGU_TNCR;     // Transmit Next Counter Register
-    AT91_REG     DBGU_PTCR;     // PDC Transfer Control Register
-    AT91_REG     DBGU_PTSR;     // PDC Transfer Status Register
-} AT91S_DBGU, *AT91PS_DBGU;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Debug Unit */
+/* ***************************************************************************** */
+typedef struct _AT91S_DBGU
+{
+    AT91_REG DBGU_CR;         /* Control Register */
+    AT91_REG DBGU_MR;         /* Mode Register */
+    AT91_REG DBGU_IER;        /* Interrupt Enable Register */
+    AT91_REG DBGU_IDR;        /* Interrupt Disable Register */
+    AT91_REG DBGU_IMR;        /* Interrupt Mask Register */
+    AT91_REG DBGU_CSR;        /* Channel Status Register */
+    AT91_REG DBGU_RHR;        /* Receiver Holding Register */
+    AT91_REG DBGU_THR;        /* Transmitter Holding Register */
+    AT91_REG DBGU_BRGR;       /* Baud Rate Generator Register */
+    AT91_REG Reserved0[ 7 ];  /* */
+    AT91_REG DBGU_CIDR;       /* Chip ID Register */
+    AT91_REG DBGU_EXID;       /* Chip ID Extension Register */
+    AT91_REG DBGU_FNTR;       /* Force NTRST Register */
+    AT91_REG Reserved1[ 45 ]; /* */
+    AT91_REG DBGU_RPR;        /* Receive Pointer Register */
+    AT91_REG DBGU_RCR;        /* Receive Counter Register */
+    AT91_REG DBGU_TPR;        /* Transmit Pointer Register */
+    AT91_REG DBGU_TCR;        /* Transmit Counter Register */
+    AT91_REG DBGU_RNPR;       /* Receive Next Pointer Register */
+    AT91_REG DBGU_RNCR;       /* Receive Next Counter Register */
+    AT91_REG DBGU_TNPR;       /* Transmit Next Pointer Register */
+    AT91_REG DBGU_TNCR;       /* Transmit Next Counter Register */
+    AT91_REG DBGU_PTCR;       /* PDC Transfer Control Register */
+    AT91_REG DBGU_PTSR;       /* PDC Transfer Status Register */
+} AT91S_DBGU, * AT91PS_DBGU;
 
-// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
-#define AT91C_US_RSTRX        ((unsigned int) 0x1 <<  2) // (DBGU) Reset Receiver
-#define AT91C_US_RSTTX        ((unsigned int) 0x1 <<  3) // (DBGU) Reset Transmitter
-#define AT91C_US_RXEN         ((unsigned int) 0x1 <<  4) // (DBGU) Receiver Enable
-#define AT91C_US_RXDIS        ((unsigned int) 0x1 <<  5) // (DBGU) Receiver Disable
-#define AT91C_US_TXEN         ((unsigned int) 0x1 <<  6) // (DBGU) Transmitter Enable
-#define AT91C_US_TXDIS        ((unsigned int) 0x1 <<  7) // (DBGU) Transmitter Disable
-#define AT91C_US_RSTSTA       ((unsigned int) 0x1 <<  8) // (DBGU) Reset Status Bits
-// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
-#define AT91C_US_PAR          ((unsigned int) 0x7 <<  9) // (DBGU) Parity type
-#define     AT91C_US_PAR_EVEN                 ((unsigned int) 0x0 <<  9) // (DBGU) Even Parity
-#define     AT91C_US_PAR_ODD                  ((unsigned int) 0x1 <<  9) // (DBGU) Odd Parity
-#define     AT91C_US_PAR_SPACE                ((unsigned int) 0x2 <<  9) // (DBGU) Parity forced to 0 (Space)
-#define     AT91C_US_PAR_MARK                 ((unsigned int) 0x3 <<  9) // (DBGU) Parity forced to 1 (Mark)
-#define     AT91C_US_PAR_NONE                 ((unsigned int) 0x4 <<  9) // (DBGU) No Parity
-#define     AT91C_US_PAR_MULTI_DROP           ((unsigned int) 0x6 <<  9) // (DBGU) Multi-drop mode
-#define AT91C_US_CHMODE       ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode
-#define     AT91C_US_CHMODE_NORMAL               ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
-#define     AT91C_US_CHMODE_AUTO                 ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
-#define     AT91C_US_CHMODE_LOCAL                ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
-#define     AT91C_US_CHMODE_REMOTE               ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
-// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
-#define AT91C_US_RXRDY        ((unsigned int) 0x1 <<  0) // (DBGU) RXRDY Interrupt
-#define AT91C_US_TXRDY        ((unsigned int) 0x1 <<  1) // (DBGU) TXRDY Interrupt
-#define AT91C_US_ENDRX        ((unsigned int) 0x1 <<  3) // (DBGU) End of Receive Transfer Interrupt
-#define AT91C_US_ENDTX        ((unsigned int) 0x1 <<  4) // (DBGU) End of Transmit Interrupt
-#define AT91C_US_OVRE         ((unsigned int) 0x1 <<  5) // (DBGU) Overrun Interrupt
-#define AT91C_US_FRAME        ((unsigned int) 0x1 <<  6) // (DBGU) Framing Error Interrupt
-#define AT91C_US_PARE         ((unsigned int) 0x1 <<  7) // (DBGU) Parity Error Interrupt
-#define AT91C_US_TXEMPTY      ((unsigned int) 0x1 <<  9) // (DBGU) TXEMPTY Interrupt
-#define AT91C_US_TXBUFE       ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt
-#define AT91C_US_RXBUFF       ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt
-#define AT91C_US_COMM_TX      ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt
-#define AT91C_US_COMM_RX      ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt
-// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
-// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
-// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
-// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
-#define AT91C_US_FORCE_NTRST  ((unsigned int) 0x1 <<  0) // (DBGU) Force NTRST in JTAG
+/* -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- */
+#define AT91C_US_RSTRX                 ( ( unsigned int ) 0x1 << 2 )  /* (DBGU) Reset Receiver */
+#define AT91C_US_RSTTX                 ( ( unsigned int ) 0x1 << 3 )  /* (DBGU) Reset Transmitter */
+#define AT91C_US_RXEN                  ( ( unsigned int ) 0x1 << 4 )  /* (DBGU) Receiver Enable */
+#define AT91C_US_RXDIS                 ( ( unsigned int ) 0x1 << 5 )  /* (DBGU) Receiver Disable */
+#define AT91C_US_TXEN                  ( ( unsigned int ) 0x1 << 6 )  /* (DBGU) Transmitter Enable */
+#define AT91C_US_TXDIS                 ( ( unsigned int ) 0x1 << 7 )  /* (DBGU) Transmitter Disable */
+#define AT91C_US_RSTSTA                ( ( unsigned int ) 0x1 << 8 )  /* (DBGU) Reset Status Bits */
+/* -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- */
+#define AT91C_US_PAR                   ( ( unsigned int ) 0x7 << 9 )  /* (DBGU) Parity type */
+#define     AT91C_US_PAR_EVEN          ( ( unsigned int ) 0x0 << 9 )  /* (DBGU) Even Parity */
+#define     AT91C_US_PAR_ODD           ( ( unsigned int ) 0x1 << 9 )  /* (DBGU) Odd Parity */
+#define     AT91C_US_PAR_SPACE         ( ( unsigned int ) 0x2 << 9 )  /* (DBGU) Parity forced to 0 (Space) */
+#define     AT91C_US_PAR_MARK          ( ( unsigned int ) 0x3 << 9 )  /* (DBGU) Parity forced to 1 (Mark) */
+#define     AT91C_US_PAR_NONE          ( ( unsigned int ) 0x4 << 9 )  /* (DBGU) No Parity */
+#define     AT91C_US_PAR_MULTI_DROP    ( ( unsigned int ) 0x6 << 9 )  /* (DBGU) Multi-drop mode */
+#define AT91C_US_CHMODE                ( ( unsigned int ) 0x3 << 14 ) /* (DBGU) Channel Mode */
+#define     AT91C_US_CHMODE_NORMAL     ( ( unsigned int ) 0x0 << 14 ) /* (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. */
+#define     AT91C_US_CHMODE_AUTO       ( ( unsigned int ) 0x1 << 14 ) /* (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. */
+#define     AT91C_US_CHMODE_LOCAL      ( ( unsigned int ) 0x2 << 14 ) /* (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. */
+#define     AT91C_US_CHMODE_REMOTE     ( ( unsigned int ) 0x3 << 14 ) /* (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. */
+/* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */
+#define AT91C_US_RXRDY                 ( ( unsigned int ) 0x1 << 0 )  /* (DBGU) RXRDY Interrupt */
+#define AT91C_US_TXRDY                 ( ( unsigned int ) 0x1 << 1 )  /* (DBGU) TXRDY Interrupt */
+#define AT91C_US_ENDRX                 ( ( unsigned int ) 0x1 << 3 )  /* (DBGU) End of Receive Transfer Interrupt */
+#define AT91C_US_ENDTX                 ( ( unsigned int ) 0x1 << 4 )  /* (DBGU) End of Transmit Interrupt */
+#define AT91C_US_OVRE                  ( ( unsigned int ) 0x1 << 5 )  /* (DBGU) Overrun Interrupt */
+#define AT91C_US_FRAME                 ( ( unsigned int ) 0x1 << 6 )  /* (DBGU) Framing Error Interrupt */
+#define AT91C_US_PARE                  ( ( unsigned int ) 0x1 << 7 )  /* (DBGU) Parity Error Interrupt */
+#define AT91C_US_TXEMPTY               ( ( unsigned int ) 0x1 << 9 )  /* (DBGU) TXEMPTY Interrupt */
+#define AT91C_US_TXBUFE                ( ( unsigned int ) 0x1 << 11 ) /* (DBGU) TXBUFE Interrupt */
+#define AT91C_US_RXBUFF                ( ( unsigned int ) 0x1 << 12 ) /* (DBGU) RXBUFF Interrupt */
+#define AT91C_US_COMM_TX               ( ( unsigned int ) 0x1 << 30 ) /* (DBGU) COMM_TX Interrupt */
+#define AT91C_US_COMM_RX               ( ( unsigned int ) 0x1 << 31 ) /* (DBGU) COMM_RX Interrupt */
+/* -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- */
+/* -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- */
+/* -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- */
+/* -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- */
+#define AT91C_US_FORCE_NTRST    ( ( unsigned int ) 0x1 << 0 ) /* (DBGU) Force NTRST in JTAG */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
-// *****************************************************************************
-typedef struct _AT91S_PIO {
-    AT91_REG     PIO_PER;   // PIO Enable Register
-    AT91_REG     PIO_PDR;   // PIO Disable Register
-    AT91_REG     PIO_PSR;   // PIO Status Register
-    AT91_REG     Reserved0[1];  //
-    AT91_REG     PIO_OER;   // Output Enable Register
-    AT91_REG     PIO_ODR;   // Output Disable Registerr
-    AT91_REG     PIO_OSR;   // Output Status Register
-    AT91_REG     Reserved1[1];  //
-    AT91_REG     PIO_IFER;  // Input Filter Enable Register
-    AT91_REG     PIO_IFDR;  // Input Filter Disable Register
-    AT91_REG     PIO_IFSR;  // Input Filter Status Register
-    AT91_REG     Reserved2[1];  //
-    AT91_REG     PIO_SODR;  // Set Output Data Register
-    AT91_REG     PIO_CODR;  // Clear Output Data Register
-    AT91_REG     PIO_ODSR;  // Output Data Status Register
-    AT91_REG     PIO_PDSR;  // Pin Data Status Register
-    AT91_REG     PIO_IER;   // Interrupt Enable Register
-    AT91_REG     PIO_IDR;   // Interrupt Disable Register
-    AT91_REG     PIO_IMR;   // Interrupt Mask Register
-    AT91_REG     PIO_ISR;   // Interrupt Status Register
-    AT91_REG     PIO_MDER;  // Multi-driver Enable Register
-    AT91_REG     PIO_MDDR;  // Multi-driver Disable Register
-    AT91_REG     PIO_MDSR;  // Multi-driver Status Register
-    AT91_REG     Reserved3[1];  //
-    AT91_REG     PIO_PPUDR;     // Pull-up Disable Register
-    AT91_REG     PIO_PPUER;     // Pull-up Enable Register
-    AT91_REG     PIO_PPUSR;     // Pull-up Status Register
-    AT91_REG     Reserved4[1];  //
-    AT91_REG     PIO_ASR;   // Select A Register
-    AT91_REG     PIO_BSR;   // Select B Register
-    AT91_REG     PIO_ABSR;  // AB Select Status Register
-    AT91_REG     Reserved5[9];  //
-    AT91_REG     PIO_OWER;  // Output Write Enable Register
-    AT91_REG     PIO_OWDR;  // Output Write Disable Register
-    AT91_REG     PIO_OWSR;  // Output Write Status Register
-} AT91S_PIO, *AT91PS_PIO;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Parallel Input Output Controller */
+/* ***************************************************************************** */
+typedef struct _AT91S_PIO
+{
+    AT91_REG PIO_PER;        /* PIO Enable Register */
+    AT91_REG PIO_PDR;        /* PIO Disable Register */
+    AT91_REG PIO_PSR;        /* PIO Status Register */
+    AT91_REG Reserved0[ 1 ]; /* */
+    AT91_REG PIO_OER;        /* Output Enable Register */
+    AT91_REG PIO_ODR;        /* Output Disable Registerr */
+    AT91_REG PIO_OSR;        /* Output Status Register */
+    AT91_REG Reserved1[ 1 ]; /* */
+    AT91_REG PIO_IFER;       /* Input Filter Enable Register */
+    AT91_REG PIO_IFDR;       /* Input Filter Disable Register */
+    AT91_REG PIO_IFSR;       /* Input Filter Status Register */
+    AT91_REG Reserved2[ 1 ]; /* */
+    AT91_REG PIO_SODR;       /* Set Output Data Register */
+    AT91_REG PIO_CODR;       /* Clear Output Data Register */
+    AT91_REG PIO_ODSR;       /* Output Data Status Register */
+    AT91_REG PIO_PDSR;       /* Pin Data Status Register */
+    AT91_REG PIO_IER;        /* Interrupt Enable Register */
+    AT91_REG PIO_IDR;        /* Interrupt Disable Register */
+    AT91_REG PIO_IMR;        /* Interrupt Mask Register */
+    AT91_REG PIO_ISR;        /* Interrupt Status Register */
+    AT91_REG PIO_MDER;       /* Multi-driver Enable Register */
+    AT91_REG PIO_MDDR;       /* Multi-driver Disable Register */
+    AT91_REG PIO_MDSR;       /* Multi-driver Status Register */
+    AT91_REG Reserved3[ 1 ]; /* */
+    AT91_REG PIO_PPUDR;      /* Pull-up Disable Register */
+    AT91_REG PIO_PPUER;      /* Pull-up Enable Register */
+    AT91_REG PIO_PPUSR;      /* Pull-up Status Register */
+    AT91_REG Reserved4[ 1 ]; /* */
+    AT91_REG PIO_ASR;        /* Select A Register */
+    AT91_REG PIO_BSR;        /* Select B Register */
+    AT91_REG PIO_ABSR;       /* AB Select Status Register */
+    AT91_REG Reserved5[ 9 ]; /* */
+    AT91_REG PIO_OWER;       /* Output Write Enable Register */
+    AT91_REG PIO_OWDR;       /* Output Write Disable Register */
+    AT91_REG PIO_OWSR;       /* Output Write Status Register */
+} AT91S_PIO, * AT91PS_PIO;
 
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Clock Generator Controler
-// *****************************************************************************
-typedef struct _AT91S_CKGR {
-    AT91_REG     CKGR_MOR;  // Main Oscillator Register
-    AT91_REG     CKGR_MCFR;     // Main Clock  Frequency Register
-    AT91_REG     Reserved0[1];  //
-    AT91_REG     CKGR_PLLR;     // PLL Register
-} AT91S_CKGR, *AT91PS_CKGR;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Clock Generator Controller */
+/* ***************************************************************************** */
+typedef struct _AT91S_CKGR
+{
+    AT91_REG CKGR_MOR;       /* Main Oscillator Register */
+    AT91_REG CKGR_MCFR;      /* Main Clock  Frequency Register */
+    AT91_REG Reserved0[ 1 ]; /* */
+    AT91_REG CKGR_PLLR;      /* PLL Register */
+} AT91S_CKGR, * AT91PS_CKGR;
 
-// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
-#define AT91C_CKGR_MOSCEN     ((unsigned int) 0x1 <<  0) // (CKGR) Main Oscillator Enable
-#define AT91C_CKGR_OSCBYPASS  ((unsigned int) 0x1 <<  1) // (CKGR) Main Oscillator Bypass
-#define AT91C_CKGR_OSCOUNT    ((unsigned int) 0xFF <<  8) // (CKGR) Main Oscillator Start-up Time
-// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
-#define AT91C_CKGR_MAINF      ((unsigned int) 0xFFFF <<  0) // (CKGR) Main Clock Frequency
-#define AT91C_CKGR_MAINRDY    ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready
-// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
-#define AT91C_CKGR_DIV        ((unsigned int) 0xFF <<  0) // (CKGR) Divider Selected
-#define     AT91C_CKGR_DIV_0                    ((unsigned int) 0x0) // (CKGR) Divider output is 0
-#define     AT91C_CKGR_DIV_BYPASS               ((unsigned int) 0x1) // (CKGR) Divider is bypassed
-#define AT91C_CKGR_PLLCOUNT   ((unsigned int) 0x3F <<  8) // (CKGR) PLL Counter
-#define AT91C_CKGR_OUT        ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range
-#define     AT91C_CKGR_OUT_0                    ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet
-#define     AT91C_CKGR_OUT_1                    ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet
-#define     AT91C_CKGR_OUT_2                    ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet
-#define     AT91C_CKGR_OUT_3                    ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_MUL        ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier
-#define AT91C_CKGR_USBDIV     ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks
-#define     AT91C_CKGR_USBDIV_0                    ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output
-#define     AT91C_CKGR_USBDIV_1                    ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
-#define     AT91C_CKGR_USBDIV_2                    ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
+/* -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */
+#define AT91C_CKGR_MOSCEN            ( ( unsigned int ) 0x1 << 0 )    /* (CKGR) Main Oscillator Enable */
+#define AT91C_CKGR_OSCBYPASS         ( ( unsigned int ) 0x1 << 1 )    /* (CKGR) Main Oscillator Bypass */
+#define AT91C_CKGR_OSCOUNT           ( ( unsigned int ) 0xFF << 8 )   /* (CKGR) Main Oscillator Start-up Time */
+/* -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- */
+#define AT91C_CKGR_MAINF             ( ( unsigned int ) 0xFFFF << 0 ) /* (CKGR) Main Clock Frequency */
+#define AT91C_CKGR_MAINRDY           ( ( unsigned int ) 0x1 << 16 )   /* (CKGR) Main Clock Ready */
+/* -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- */
+#define AT91C_CKGR_DIV               ( ( unsigned int ) 0xFF << 0 )   /* (CKGR) Divider Selected */
+#define     AT91C_CKGR_DIV_0         ( ( unsigned int ) 0x0 )         /* (CKGR) Divider output is 0 */
+#define     AT91C_CKGR_DIV_BYPASS    ( ( unsigned int ) 0x1 )         /* (CKGR) Divider is bypassed */
+#define AT91C_CKGR_PLLCOUNT          ( ( unsigned int ) 0x3F << 8 )   /* (CKGR) PLL Counter */
+#define AT91C_CKGR_OUT               ( ( unsigned int ) 0x3 << 14 )   /* (CKGR) PLL Output Frequency Range */
+#define     AT91C_CKGR_OUT_0         ( ( unsigned int ) 0x0 << 14 )   /* (CKGR) Please refer to the PLL datasheet */
+#define     AT91C_CKGR_OUT_1         ( ( unsigned int ) 0x1 << 14 )   /* (CKGR) Please refer to the PLL datasheet */
+#define     AT91C_CKGR_OUT_2         ( ( unsigned int ) 0x2 << 14 )   /* (CKGR) Please refer to the PLL datasheet */
+#define     AT91C_CKGR_OUT_3         ( ( unsigned int ) 0x3 << 14 )   /* (CKGR) Please refer to the PLL datasheet */
+#define AT91C_CKGR_MUL               ( ( unsigned int ) 0x7FF << 16 ) /* (CKGR) PLL Multiplier */
+#define AT91C_CKGR_USBDIV            ( ( unsigned int ) 0x3 << 28 )   /* (CKGR) Divider for USB Clocks */
+#define     AT91C_CKGR_USBDIV_0      ( ( unsigned int ) 0x0 << 28 )   /* (CKGR) Divider output is PLL clock output */
+#define     AT91C_CKGR_USBDIV_1      ( ( unsigned int ) 0x1 << 28 )   /* (CKGR) Divider output is PLL clock output divided by 2 */
+#define     AT91C_CKGR_USBDIV_2      ( ( unsigned int ) 0x2 << 28 )   /* (CKGR) Divider output is PLL clock output divided by 4 */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Power Management Controler
-// *****************************************************************************
-typedef struct _AT91S_PMC {
-    AT91_REG     PMC_SCER;  // System Clock Enable Register
-    AT91_REG     PMC_SCDR;  // System Clock Disable Register
-    AT91_REG     PMC_SCSR;  // System Clock Status Register
-    AT91_REG     Reserved0[1];  //
-    AT91_REG     PMC_PCER;  // Peripheral Clock Enable Register
-    AT91_REG     PMC_PCDR;  // Peripheral Clock Disable Register
-    AT91_REG     PMC_PCSR;  // Peripheral Clock Status Register
-    AT91_REG     Reserved1[1];  //
-    AT91_REG     PMC_MOR;   // Main Oscillator Register
-    AT91_REG     PMC_MCFR;  // Main Clock  Frequency Register
-    AT91_REG     Reserved2[1];  //
-    AT91_REG     PMC_PLLR;  // PLL Register
-    AT91_REG     PMC_MCKR;  // Master Clock Register
-    AT91_REG     Reserved3[3];  //
-    AT91_REG     PMC_PCKR[4];   // Programmable Clock Register
-    AT91_REG     Reserved4[4];  //
-    AT91_REG     PMC_IER;   // Interrupt Enable Register
-    AT91_REG     PMC_IDR;   // Interrupt Disable Register
-    AT91_REG     PMC_SR;    // Status Register
-    AT91_REG     PMC_IMR;   // Interrupt Mask Register
-} AT91S_PMC, *AT91PS_PMC;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Power Management Controller */
+/* ***************************************************************************** */
+typedef struct _AT91S_PMC
+{
+    AT91_REG PMC_SCER;       /* System Clock Enable Register */
+    AT91_REG PMC_SCDR;       /* System Clock Disable Register */
+    AT91_REG PMC_SCSR;       /* System Clock Status Register */
+    AT91_REG Reserved0[ 1 ]; /* */
+    AT91_REG PMC_PCER;       /* Peripheral Clock Enable Register */
+    AT91_REG PMC_PCDR;       /* Peripheral Clock Disable Register */
+    AT91_REG PMC_PCSR;       /* Peripheral Clock Status Register */
+    AT91_REG Reserved1[ 1 ]; /* */
+    AT91_REG PMC_MOR;        /* Main Oscillator Register */
+    AT91_REG PMC_MCFR;       /* Main Clock  Frequency Register */
+    AT91_REG Reserved2[ 1 ]; /* */
+    AT91_REG PMC_PLLR;       /* PLL Register */
+    AT91_REG PMC_MCKR;       /* Master Clock Register */
+    AT91_REG Reserved3[ 3 ]; /* */
+    AT91_REG PMC_PCKR[ 4 ];  /* Programmable Clock Register */
+    AT91_REG Reserved4[ 4 ]; /* */
+    AT91_REG PMC_IER;        /* Interrupt Enable Register */
+    AT91_REG PMC_IDR;        /* Interrupt Disable Register */
+    AT91_REG PMC_SR;         /* Status Register */
+    AT91_REG PMC_IMR;        /* Interrupt Mask Register */
+} AT91S_PMC, * AT91PS_PMC;
 
-// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
-#define AT91C_PMC_PCK         ((unsigned int) 0x1 <<  0) // (PMC) Processor Clock
-#define AT91C_PMC_UDP         ((unsigned int) 0x1 <<  7) // (PMC) USB Device Port Clock
-#define AT91C_PMC_PCK0        ((unsigned int) 0x1 <<  8) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK1        ((unsigned int) 0x1 <<  9) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK2        ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK3        ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output
-// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
-// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
-// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
-// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
-// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
-// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
-#define AT91C_PMC_CSS         ((unsigned int) 0x3 <<  0) // (PMC) Programmable Clock Selection
-#define     AT91C_PMC_CSS_SLOW_CLK             ((unsigned int) 0x0) // (PMC) Slow Clock is selected
-#define     AT91C_PMC_CSS_MAIN_CLK             ((unsigned int) 0x1) // (PMC) Main Clock is selected
-#define     AT91C_PMC_CSS_PLL_CLK              ((unsigned int) 0x3) // (PMC) Clock from PLL is selected
-#define AT91C_PMC_PRES        ((unsigned int) 0x7 <<  2) // (PMC) Programmable Clock Prescaler
-#define     AT91C_PMC_PRES_CLK                  ((unsigned int) 0x0 <<  2) // (PMC) Selected clock
-#define     AT91C_PMC_PRES_CLK_2                ((unsigned int) 0x1 <<  2) // (PMC) Selected clock divided by 2
-#define     AT91C_PMC_PRES_CLK_4                ((unsigned int) 0x2 <<  2) // (PMC) Selected clock divided by 4
-#define     AT91C_PMC_PRES_CLK_8                ((unsigned int) 0x3 <<  2) // (PMC) Selected clock divided by 8
-#define     AT91C_PMC_PRES_CLK_16               ((unsigned int) 0x4 <<  2) // (PMC) Selected clock divided by 16
-#define     AT91C_PMC_PRES_CLK_32               ((unsigned int) 0x5 <<  2) // (PMC) Selected clock divided by 32
-#define     AT91C_PMC_PRES_CLK_64               ((unsigned int) 0x6 <<  2) // (PMC) Selected clock divided by 64
-// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
-// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
-#define AT91C_PMC_MOSCS       ((unsigned int) 0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask
-#define AT91C_PMC_LOCK        ((unsigned int) 0x1 <<  2) // (PMC) PLL Status/Enable/Disable/Mask
-#define AT91C_PMC_MCKRDY      ((unsigned int) 0x1 <<  3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK0RDY     ((unsigned int) 0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK1RDY     ((unsigned int) 0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK2RDY     ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK3RDY     ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
-// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
-// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
-// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
+/* -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- */
+#define AT91C_PMC_PCK     ( ( unsigned int ) 0x1 << 0 )  /* (PMC) Processor Clock */
+#define AT91C_PMC_UDP     ( ( unsigned int ) 0x1 << 7 )  /* (PMC) USB Device Port Clock */
+#define AT91C_PMC_PCK0    ( ( unsigned int ) 0x1 << 8 )  /* (PMC) Programmable Clock Output */
+#define AT91C_PMC_PCK1    ( ( unsigned int ) 0x1 << 9 )  /* (PMC) Programmable Clock Output */
+#define AT91C_PMC_PCK2    ( ( unsigned int ) 0x1 << 10 ) /* (PMC) Programmable Clock Output */
+#define AT91C_PMC_PCK3    ( ( unsigned int ) 0x1 << 11 ) /* (PMC) Programmable Clock Output */
+/* -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- */
+/* -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- */
+/* -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- */
+/* -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- */
+/* -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- */
+/* -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- */
+#define AT91C_PMC_CSS                 ( ( unsigned int ) 0x3 << 0 ) /* (PMC) Programmable Clock Selection */
+#define     AT91C_PMC_CSS_SLOW_CLK    ( ( unsigned int ) 0x0 )      /* (PMC) Slow Clock is selected */
+#define     AT91C_PMC_CSS_MAIN_CLK    ( ( unsigned int ) 0x1 )      /* (PMC) Main Clock is selected */
+#define     AT91C_PMC_CSS_PLL_CLK     ( ( unsigned int ) 0x3 )      /* (PMC) Clock from PLL is selected */
+#define AT91C_PMC_PRES                ( ( unsigned int ) 0x7 << 2 ) /* (PMC) Programmable Clock Prescaler */
+#define     AT91C_PMC_PRES_CLK        ( ( unsigned int ) 0x0 << 2 ) /* (PMC) Selected clock */
+#define     AT91C_PMC_PRES_CLK_2      ( ( unsigned int ) 0x1 << 2 ) /* (PMC) Selected clock divided by 2 */
+#define     AT91C_PMC_PRES_CLK_4      ( ( unsigned int ) 0x2 << 2 ) /* (PMC) Selected clock divided by 4 */
+#define     AT91C_PMC_PRES_CLK_8      ( ( unsigned int ) 0x3 << 2 ) /* (PMC) Selected clock divided by 8 */
+#define     AT91C_PMC_PRES_CLK_16     ( ( unsigned int ) 0x4 << 2 ) /* (PMC) Selected clock divided by 16 */
+#define     AT91C_PMC_PRES_CLK_32     ( ( unsigned int ) 0x5 << 2 ) /* (PMC) Selected clock divided by 32 */
+#define     AT91C_PMC_PRES_CLK_64     ( ( unsigned int ) 0x6 << 2 ) /* (PMC) Selected clock divided by 64 */
+/* -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- */
+/* -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- */
+#define AT91C_PMC_MOSCS               ( ( unsigned int ) 0x1 << 0 )  /* (PMC) MOSC Status/Enable/Disable/Mask */
+#define AT91C_PMC_LOCK                ( ( unsigned int ) 0x1 << 2 )  /* (PMC) PLL Status/Enable/Disable/Mask */
+#define AT91C_PMC_MCKRDY              ( ( unsigned int ) 0x1 << 3 )  /* (PMC) MCK_RDY Status/Enable/Disable/Mask */
+#define AT91C_PMC_PCK0RDY             ( ( unsigned int ) 0x1 << 8 )  /* (PMC) PCK0_RDY Status/Enable/Disable/Mask */
+#define AT91C_PMC_PCK1RDY             ( ( unsigned int ) 0x1 << 9 )  /* (PMC) PCK1_RDY Status/Enable/Disable/Mask */
+#define AT91C_PMC_PCK2RDY             ( ( unsigned int ) 0x1 << 10 ) /* (PMC) PCK2_RDY Status/Enable/Disable/Mask */
+#define AT91C_PMC_PCK3RDY             ( ( unsigned int ) 0x1 << 11 ) /* (PMC) PCK3_RDY Status/Enable/Disable/Mask */
+/* -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- */
+/* -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- */
+/* -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Reset Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_RSTC {
-    AT91_REG     RSTC_RCR;  // Reset Control Register
-    AT91_REG     RSTC_RSR;  // Reset Status Register
-    AT91_REG     RSTC_RMR;  // Reset Mode Register
-} AT91S_RSTC, *AT91PS_RSTC;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Reset Controller Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_RSTC
+{
+    AT91_REG RSTC_RCR; /* Reset Control Register */
+    AT91_REG RSTC_RSR; /* Reset Status Register */
+    AT91_REG RSTC_RMR; /* Reset Mode Register */
+} AT91S_RSTC, * AT91PS_RSTC;
 
-// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
-#define AT91C_RSTC_PROCRST    ((unsigned int) 0x1 <<  0) // (RSTC) Processor Reset
-#define AT91C_RSTC_PERRST     ((unsigned int) 0x1 <<  2) // (RSTC) Peripheral Reset
-#define AT91C_RSTC_EXTRST     ((unsigned int) 0x1 <<  3) // (RSTC) External Reset
-#define AT91C_RSTC_KEY        ((unsigned int) 0xFF << 24) // (RSTC) Password
-// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
-#define AT91C_RSTC_URSTS      ((unsigned int) 0x1 <<  0) // (RSTC) User Reset Status
-#define AT91C_RSTC_BODSTS     ((unsigned int) 0x1 <<  1) // (RSTC) Brownout Detection Status
-#define AT91C_RSTC_RSTTYP     ((unsigned int) 0x7 <<  8) // (RSTC) Reset Type
-#define     AT91C_RSTC_RSTTYP_POWERUP              ((unsigned int) 0x0 <<  8) // (RSTC) Power-up Reset. VDDCORE rising.
-#define     AT91C_RSTC_RSTTYP_WAKEUP               ((unsigned int) 0x1 <<  8) // (RSTC) WakeUp Reset. VDDCORE rising.
-#define     AT91C_RSTC_RSTTYP_WATCHDOG             ((unsigned int) 0x2 <<  8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
-#define     AT91C_RSTC_RSTTYP_SOFTWARE             ((unsigned int) 0x3 <<  8) // (RSTC) Software Reset. Processor reset required by the software.
-#define     AT91C_RSTC_RSTTYP_USER                 ((unsigned int) 0x4 <<  8) // (RSTC) User Reset. NRST pin detected low.
-#define     AT91C_RSTC_RSTTYP_BROWNOUT             ((unsigned int) 0x5 <<  8) // (RSTC) Brownout Reset occured.
-#define AT91C_RSTC_NRSTL      ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level
-#define AT91C_RSTC_SRCMP      ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress.
-// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
-#define AT91C_RSTC_URSTEN     ((unsigned int) 0x1 <<  0) // (RSTC) User Reset Enable
-#define AT91C_RSTC_URSTIEN    ((unsigned int) 0x1 <<  4) // (RSTC) User Reset Interrupt Enable
-#define AT91C_RSTC_ERSTL      ((unsigned int) 0xF <<  8) // (RSTC) User Reset Enable
-#define AT91C_RSTC_BODIEN     ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
+/* -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- */
+#define AT91C_RSTC_PROCRST                ( ( unsigned int ) 0x1 << 0 )   /* (RSTC) Processor Reset */
+#define AT91C_RSTC_PERRST                 ( ( unsigned int ) 0x1 << 2 )   /* (RSTC) Peripheral Reset */
+#define AT91C_RSTC_EXTRST                 ( ( unsigned int ) 0x1 << 3 )   /* (RSTC) External Reset */
+#define AT91C_RSTC_KEY                    ( ( unsigned int ) 0xFF << 24 ) /* (RSTC) Password */
+/* -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- */
+#define AT91C_RSTC_URSTS                  ( ( unsigned int ) 0x1 << 0 )   /* (RSTC) User Reset Status */
+#define AT91C_RSTC_BODSTS                 ( ( unsigned int ) 0x1 << 1 )   /* (RSTC) Brownout Detection Status */
+#define AT91C_RSTC_RSTTYP                 ( ( unsigned int ) 0x7 << 8 )   /* (RSTC) Reset Type */
+#define     AT91C_RSTC_RSTTYP_POWERUP     ( ( unsigned int ) 0x0 << 8 )   /* (RSTC) Power-up Reset. VDDCORE rising. */
+#define     AT91C_RSTC_RSTTYP_WAKEUP      ( ( unsigned int ) 0x1 << 8 )   /* (RSTC) WakeUp Reset. VDDCORE rising. */
+#define     AT91C_RSTC_RSTTYP_WATCHDOG    ( ( unsigned int ) 0x2 << 8 )   /* (RSTC) Watchdog Reset. Watchdog overflow occurred. */
+#define     AT91C_RSTC_RSTTYP_SOFTWARE    ( ( unsigned int ) 0x3 << 8 )   /* (RSTC) Software Reset. Processor reset required by the software. */
+#define     AT91C_RSTC_RSTTYP_USER        ( ( unsigned int ) 0x4 << 8 )   /* (RSTC) User Reset. NRST pin detected low. */
+#define     AT91C_RSTC_RSTTYP_BROWNOUT    ( ( unsigned int ) 0x5 << 8 )   /* (RSTC) Brownout Reset occurred. */
+#define AT91C_RSTC_NRSTL                  ( ( unsigned int ) 0x1 << 16 )  /* (RSTC) NRST pin level */
+#define AT91C_RSTC_SRCMP                  ( ( unsigned int ) 0x1 << 17 )  /* (RSTC) Software Reset Command in Progress. */
+/* -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- */
+#define AT91C_RSTC_URSTEN                 ( ( unsigned int ) 0x1 << 0 )   /* (RSTC) User Reset Enable */
+#define AT91C_RSTC_URSTIEN                ( ( unsigned int ) 0x1 << 4 )   /* (RSTC) User Reset Interrupt Enable */
+#define AT91C_RSTC_ERSTL                  ( ( unsigned int ) 0xF << 8 )   /* (RSTC) User Reset Enable */
+#define AT91C_RSTC_BODIEN                 ( ( unsigned int ) 0x1 << 16 )  /* (RSTC) Brownout Detection Interrupt Enable */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_RTTC {
-    AT91_REG     RTTC_RTMR;     // Real-time Mode Register
-    AT91_REG     RTTC_RTAR;     // Real-time Alarm Register
-    AT91_REG     RTTC_RTVR;     // Real-time Value Register
-    AT91_REG     RTTC_RTSR;     // Real-time Status Register
-} AT91S_RTTC, *AT91PS_RTTC;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_RTTC
+{
+    AT91_REG RTTC_RTMR; /* Real-time Mode Register */
+    AT91_REG RTTC_RTAR; /* Real-time Alarm Register */
+    AT91_REG RTTC_RTVR; /* Real-time Value Register */
+    AT91_REG RTTC_RTSR; /* Real-time Status Register */
+} AT91S_RTTC, * AT91PS_RTTC;
 
-// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
-#define AT91C_RTTC_RTPRES     ((unsigned int) 0xFFFF <<  0) // (RTTC) Real-time Timer Prescaler Value
-#define AT91C_RTTC_ALMIEN     ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable
-#define AT91C_RTTC_RTTINCIEN  ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
-#define AT91C_RTTC_RTTRST     ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart
-// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
-#define AT91C_RTTC_ALMV       ((unsigned int) 0x0 <<  0) // (RTTC) Alarm Value
-// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
-#define AT91C_RTTC_CRTV       ((unsigned int) 0x0 <<  0) // (RTTC) Current Real-time Value
-// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
-#define AT91C_RTTC_ALMS       ((unsigned int) 0x1 <<  0) // (RTTC) Real-time Alarm Status
-#define AT91C_RTTC_RTTINC     ((unsigned int) 0x1 <<  1) // (RTTC) Real-time Timer Increment
+/* -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- */
+#define AT91C_RTTC_RTPRES       ( ( unsigned int ) 0xFFFF << 0 ) /* (RTTC) Real-time Timer Prescaler Value */
+#define AT91C_RTTC_ALMIEN       ( ( unsigned int ) 0x1 << 16 )   /* (RTTC) Alarm Interrupt Enable */
+#define AT91C_RTTC_RTTINCIEN    ( ( unsigned int ) 0x1 << 17 )   /* (RTTC) Real Time Timer Increment Interrupt Enable */
+#define AT91C_RTTC_RTTRST       ( ( unsigned int ) 0x1 << 18 )   /* (RTTC) Real Time Timer Restart */
+/* -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- */
+#define AT91C_RTTC_ALMV         ( ( unsigned int ) 0x0 << 0 )    /* (RTTC) Alarm Value */
+/* -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- */
+#define AT91C_RTTC_CRTV         ( ( unsigned int ) 0x0 << 0 )    /* (RTTC) Current Real-time Value */
+/* -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- */
+#define AT91C_RTTC_ALMS         ( ( unsigned int ) 0x1 << 0 )    /* (RTTC) Real-time Alarm Status */
+#define AT91C_RTTC_RTTINC       ( ( unsigned int ) 0x1 << 1 )    /* (RTTC) Real-time Timer Increment */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_PITC {
-    AT91_REG     PITC_PIMR;     // Period Interval Mode Register
-    AT91_REG     PITC_PISR;     // Period Interval Status Register
-    AT91_REG     PITC_PIVR;     // Period Interval Value Register
-    AT91_REG     PITC_PIIR;     // Period Interval Image Register
-} AT91S_PITC, *AT91PS_PITC;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_PITC
+{
+    AT91_REG PITC_PIMR; /* Period Interval Mode Register */
+    AT91_REG PITC_PISR; /* Period Interval Status Register */
+    AT91_REG PITC_PIVR; /* Period Interval Value Register */
+    AT91_REG PITC_PIIR; /* Period Interval Image Register */
+} AT91S_PITC, * AT91PS_PITC;
 
-// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
-#define AT91C_PITC_PIV        ((unsigned int) 0xFFFFF <<  0) // (PITC) Periodic Interval Value
-#define AT91C_PITC_PITEN      ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled
-#define AT91C_PITC_PITIEN     ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
-// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
-#define AT91C_PITC_PITS       ((unsigned int) 0x1 <<  0) // (PITC) Periodic Interval Timer Status
-// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
-#define AT91C_PITC_CPIV       ((unsigned int) 0xFFFFF <<  0) // (PITC) Current Periodic Interval Value
-#define AT91C_PITC_PICNT      ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter
-// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
+/* -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- */
+#define AT91C_PITC_PIV       ( ( unsigned int ) 0xFFFFF << 0 ) /* (PITC) Periodic Interval Value */
+#define AT91C_PITC_PITEN     ( ( unsigned int ) 0x1 << 24 )    /* (PITC) Periodic Interval Timer Enabled */
+#define AT91C_PITC_PITIEN    ( ( unsigned int ) 0x1 << 25 )    /* (PITC) Periodic Interval Timer Interrupt Enable */
+/* -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- */
+#define AT91C_PITC_PITS      ( ( unsigned int ) 0x1 << 0 )     /* (PITC) Periodic Interval Timer Status */
+/* -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- */
+#define AT91C_PITC_CPIV      ( ( unsigned int ) 0xFFFFF << 0 ) /* (PITC) Current Periodic Interval Value */
+#define AT91C_PITC_PICNT     ( ( unsigned int ) 0xFFF << 20 )  /* (PITC) Periodic Interval Counter */
+/* -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_WDTC {
-    AT91_REG     WDTC_WDCR;     // Watchdog Control Register
-    AT91_REG     WDTC_WDMR;     // Watchdog Mode Register
-    AT91_REG     WDTC_WDSR;     // Watchdog Status Register
-} AT91S_WDTC, *AT91PS_WDTC;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_WDTC
+{
+    AT91_REG WDTC_WDCR; /* Watchdog Control Register */
+    AT91_REG WDTC_WDMR; /* Watchdog Mode Register */
+    AT91_REG WDTC_WDSR; /* Watchdog Status Register */
+} AT91S_WDTC, * AT91PS_WDTC;
 
-// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
-#define AT91C_WDTC_WDRSTT     ((unsigned int) 0x1 <<  0) // (WDTC) Watchdog Restart
-#define AT91C_WDTC_KEY        ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password
-// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
-#define AT91C_WDTC_WDV        ((unsigned int) 0xFFF <<  0) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDFIEN     ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
-#define AT91C_WDTC_WDRSTEN    ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable
-#define AT91C_WDTC_WDRPROC    ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDDIS      ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable
-#define AT91C_WDTC_WDD        ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value
-#define AT91C_WDTC_WDDBGHLT   ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt
-#define AT91C_WDTC_WDIDLEHLT  ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt
-// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
-#define AT91C_WDTC_WDUNF      ((unsigned int) 0x1 <<  0) // (WDTC) Watchdog Underflow
-#define AT91C_WDTC_WDERR      ((unsigned int) 0x1 <<  1) // (WDTC) Watchdog Error
+/* -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- */
+#define AT91C_WDTC_WDRSTT       ( ( unsigned int ) 0x1 << 0 )    /* (WDTC) Watchdog Restart */
+#define AT91C_WDTC_KEY          ( ( unsigned int ) 0xFF << 24 )  /* (WDTC) Watchdog KEY Password */
+/* -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- */
+#define AT91C_WDTC_WDV          ( ( unsigned int ) 0xFFF << 0 )  /* (WDTC) Watchdog Timer Restart */
+#define AT91C_WDTC_WDFIEN       ( ( unsigned int ) 0x1 << 12 )   /* (WDTC) Watchdog Fault Interrupt Enable */
+#define AT91C_WDTC_WDRSTEN      ( ( unsigned int ) 0x1 << 13 )   /* (WDTC) Watchdog Reset Enable */
+#define AT91C_WDTC_WDRPROC      ( ( unsigned int ) 0x1 << 14 )   /* (WDTC) Watchdog Timer Restart */
+#define AT91C_WDTC_WDDIS        ( ( unsigned int ) 0x1 << 15 )   /* (WDTC) Watchdog Disable */
+#define AT91C_WDTC_WDD          ( ( unsigned int ) 0xFFF << 16 ) /* (WDTC) Watchdog Delta Value */
+#define AT91C_WDTC_WDDBGHLT     ( ( unsigned int ) 0x1 << 28 )   /* (WDTC) Watchdog Debug Halt */
+#define AT91C_WDTC_WDIDLEHLT    ( ( unsigned int ) 0x1 << 29 )   /* (WDTC) Watchdog Idle Halt */
+/* -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- */
+#define AT91C_WDTC_WDUNF        ( ( unsigned int ) 0x1 << 0 )    /* (WDTC) Watchdog Underflow */
+#define AT91C_WDTC_WDERR        ( ( unsigned int ) 0x1 << 1 )    /* (WDTC) Watchdog Error */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Voltage Regulator Mode Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_VREG {
-    AT91_REG     VREG_MR;   // Voltage Regulator Mode Register
-} AT91S_VREG, *AT91PS_VREG;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Voltage Regulator Mode Controller Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_VREG
+{
+    AT91_REG VREG_MR; /* Voltage Regulator Mode Register */
+} AT91S_VREG, * AT91PS_VREG;
 
-// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register --------
-#define AT91C_VREG_PSTDBY     ((unsigned int) 0x1 <<  0) // (VREG) Voltage Regulator Power Standby Mode
+/* -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- */
+#define AT91C_VREG_PSTDBY    ( ( unsigned int ) 0x1 << 0 ) /* (VREG) Voltage Regulator Power Standby Mode */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Memory Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_MC {
-    AT91_REG     MC_RCR;    // MC Remap Control Register
-    AT91_REG     MC_ASR;    // MC Abort Status Register
-    AT91_REG     MC_AASR;   // MC Abort Address Status Register
-    AT91_REG     Reserved0[21];     //
-    AT91_REG     MC_FMR;    // MC Flash Mode Register
-    AT91_REG     MC_FCR;    // MC Flash Command Register
-    AT91_REG     MC_FSR;    // MC Flash Status Register
-} AT91S_MC, *AT91PS_MC;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Memory Controller Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_MC
+{
+    AT91_REG MC_RCR;          /* MC Remap Control Register */
+    AT91_REG MC_ASR;          /* MC Abort Status Register */
+    AT91_REG MC_AASR;         /* MC Abort Address Status Register */
+    AT91_REG Reserved0[ 21 ]; /* */
+    AT91_REG MC_FMR;          /* MC Flash Mode Register */
+    AT91_REG MC_FCR;          /* MC Flash Command Register */
+    AT91_REG MC_FSR;          /* MC Flash Status Register */
+} AT91S_MC, * AT91PS_MC;
 
-// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
-#define AT91C_MC_RCB          ((unsigned int) 0x1 <<  0) // (MC) Remap Command Bit
-// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
-#define AT91C_MC_UNDADD       ((unsigned int) 0x1 <<  0) // (MC) Undefined Addess Abort Status
-#define AT91C_MC_MISADD       ((unsigned int) 0x1 <<  1) // (MC) Misaligned Addess Abort Status
-#define AT91C_MC_ABTSZ        ((unsigned int) 0x3 <<  8) // (MC) Abort Size Status
-#define     AT91C_MC_ABTSZ_BYTE                 ((unsigned int) 0x0 <<  8) // (MC) Byte
-#define     AT91C_MC_ABTSZ_HWORD                ((unsigned int) 0x1 <<  8) // (MC) Half-word
-#define     AT91C_MC_ABTSZ_WORD                 ((unsigned int) 0x2 <<  8) // (MC) Word
-#define AT91C_MC_ABTTYP       ((unsigned int) 0x3 << 10) // (MC) Abort Type Status
-#define     AT91C_MC_ABTTYP_DATAR                ((unsigned int) 0x0 << 10) // (MC) Data Read
-#define     AT91C_MC_ABTTYP_DATAW                ((unsigned int) 0x1 << 10) // (MC) Data Write
-#define     AT91C_MC_ABTTYP_FETCH                ((unsigned int) 0x2 << 10) // (MC) Code Fetch
-#define AT91C_MC_MST0         ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source
-#define AT91C_MC_MST1         ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source
-#define AT91C_MC_SVMST0       ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source
-#define AT91C_MC_SVMST1       ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source
-// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
-#define AT91C_MC_FRDY         ((unsigned int) 0x1 <<  0) // (MC) Flash Ready
-#define AT91C_MC_LOCKE        ((unsigned int) 0x1 <<  2) // (MC) Lock Error
-#define AT91C_MC_PROGE        ((unsigned int) 0x1 <<  3) // (MC) Programming Error
-#define AT91C_MC_NEBP         ((unsigned int) 0x1 <<  7) // (MC) No Erase Before Programming
-#define AT91C_MC_FWS          ((unsigned int) 0x3 <<  8) // (MC) Flash Wait State
-#define     AT91C_MC_FWS_0FWS                 ((unsigned int) 0x0 <<  8) // (MC) 1 cycle for Read, 2 for Write operations
-#define     AT91C_MC_FWS_1FWS                 ((unsigned int) 0x1 <<  8) // (MC) 2 cycles for Read, 3 for Write operations
-#define     AT91C_MC_FWS_2FWS                 ((unsigned int) 0x2 <<  8) // (MC) 3 cycles for Read, 4 for Write operations
-#define     AT91C_MC_FWS_3FWS                 ((unsigned int) 0x3 <<  8) // (MC) 4 cycles for Read, 4 for Write operations
-#define AT91C_MC_FMCN         ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number
-// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
-#define AT91C_MC_FCMD         ((unsigned int) 0xF <<  0) // (MC) Flash Command
-#define     AT91C_MC_FCMD_START_PROG           ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN.
-#define     AT91C_MC_FCMD_LOCK                 ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define     AT91C_MC_FCMD_PROG_AND_LOCK        ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
-#define     AT91C_MC_FCMD_UNLOCK               ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define     AT91C_MC_FCMD_ERASE_ALL            ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
-#define     AT91C_MC_FCMD_SET_GP_NVM           ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits.
-#define     AT91C_MC_FCMD_CLR_GP_NVM           ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits.
-#define     AT91C_MC_FCMD_SET_SECURITY         ((unsigned int) 0xF) // (MC) Set Security Bit.
-#define AT91C_MC_PAGEN        ((unsigned int) 0x3FF <<  8) // (MC) Page Number
-#define AT91C_MC_KEY          ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key
-// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register --------
-#define AT91C_MC_SECURITY     ((unsigned int) 0x1 <<  4) // (MC) Security Bit Status
-#define AT91C_MC_GPNVM0       ((unsigned int) 0x1 <<  8) // (MC) Sector 0 Lock Status
-#define AT91C_MC_GPNVM1       ((unsigned int) 0x1 <<  9) // (MC) Sector 1 Lock Status
-#define AT91C_MC_GPNVM2       ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status
-#define AT91C_MC_GPNVM3       ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status
-#define AT91C_MC_GPNVM4       ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status
-#define AT91C_MC_GPNVM5       ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status
-#define AT91C_MC_GPNVM6       ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status
-#define AT91C_MC_GPNVM7       ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS0       ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status
-#define AT91C_MC_LOCKS1       ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status
-#define AT91C_MC_LOCKS2       ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status
-#define AT91C_MC_LOCKS3       ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status
-#define AT91C_MC_LOCKS4       ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status
-#define AT91C_MC_LOCKS5       ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status
-#define AT91C_MC_LOCKS6       ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status
-#define AT91C_MC_LOCKS7       ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS8       ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status
-#define AT91C_MC_LOCKS9       ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status
-#define AT91C_MC_LOCKS10      ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status
-#define AT91C_MC_LOCKS11      ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status
-#define AT91C_MC_LOCKS12      ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status
-#define AT91C_MC_LOCKS13      ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status
-#define AT91C_MC_LOCKS14      ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status
-#define AT91C_MC_LOCKS15      ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status
+/* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */
+#define AT91C_MC_RCB                       ( ( unsigned int ) 0x1 << 0 )   /* (MC) Remap Command Bit */
+/* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */
+#define AT91C_MC_UNDADD                    ( ( unsigned int ) 0x1 << 0 )   /* (MC) Undefined Addess Abort Status */
+#define AT91C_MC_MISADD                    ( ( unsigned int ) 0x1 << 1 )   /* (MC) Misaligned Addess Abort Status */
+#define AT91C_MC_ABTSZ                     ( ( unsigned int ) 0x3 << 8 )   /* (MC) Abort Size Status */
+#define     AT91C_MC_ABTSZ_BYTE            ( ( unsigned int ) 0x0 << 8 )   /* (MC) Byte */
+#define     AT91C_MC_ABTSZ_HWORD           ( ( unsigned int ) 0x1 << 8 )   /* (MC) Half-word */
+#define     AT91C_MC_ABTSZ_WORD            ( ( unsigned int ) 0x2 << 8 )   /* (MC) Word */
+#define AT91C_MC_ABTTYP                    ( ( unsigned int ) 0x3 << 10 )  /* (MC) Abort Type Status */
+#define     AT91C_MC_ABTTYP_DATAR          ( ( unsigned int ) 0x0 << 10 )  /* (MC) Data Read */
+#define     AT91C_MC_ABTTYP_DATAW          ( ( unsigned int ) 0x1 << 10 )  /* (MC) Data Write */
+#define     AT91C_MC_ABTTYP_FETCH          ( ( unsigned int ) 0x2 << 10 )  /* (MC) Code Fetch */
+#define AT91C_MC_MST0                      ( ( unsigned int ) 0x1 << 16 )  /* (MC) Master 0 Abort Source */
+#define AT91C_MC_MST1                      ( ( unsigned int ) 0x1 << 17 )  /* (MC) Master 1 Abort Source */
+#define AT91C_MC_SVMST0                    ( ( unsigned int ) 0x1 << 24 )  /* (MC) Saved Master 0 Abort Source */
+#define AT91C_MC_SVMST1                    ( ( unsigned int ) 0x1 << 25 )  /* (MC) Saved Master 1 Abort Source */
+/* -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- */
+#define AT91C_MC_FRDY                      ( ( unsigned int ) 0x1 << 0 )   /* (MC) Flash Ready */
+#define AT91C_MC_LOCKE                     ( ( unsigned int ) 0x1 << 2 )   /* (MC) Lock Error */
+#define AT91C_MC_PROGE                     ( ( unsigned int ) 0x1 << 3 )   /* (MC) Programming Error */
+#define AT91C_MC_NEBP                      ( ( unsigned int ) 0x1 << 7 )   /* (MC) No Erase Before Programming */
+#define AT91C_MC_FWS                       ( ( unsigned int ) 0x3 << 8 )   /* (MC) Flash Wait State */
+#define     AT91C_MC_FWS_0FWS              ( ( unsigned int ) 0x0 << 8 )   /* (MC) 1 cycle for Read, 2 for Write operations */
+#define     AT91C_MC_FWS_1FWS              ( ( unsigned int ) 0x1 << 8 )   /* (MC) 2 cycles for Read, 3 for Write operations */
+#define     AT91C_MC_FWS_2FWS              ( ( unsigned int ) 0x2 << 8 )   /* (MC) 3 cycles for Read, 4 for Write operations */
+#define     AT91C_MC_FWS_3FWS              ( ( unsigned int ) 0x3 << 8 )   /* (MC) 4 cycles for Read, 4 for Write operations */
+#define AT91C_MC_FMCN                      ( ( unsigned int ) 0xFF << 16 ) /* (MC) Flash Microsecond Cycle Number */
+/* -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- */
+#define AT91C_MC_FCMD                      ( ( unsigned int ) 0xF << 0 )   /* (MC) Flash Command */
+#define     AT91C_MC_FCMD_START_PROG       ( ( unsigned int ) 0x1 )        /* (MC) Starts the programming of th epage specified by PAGEN. */
+#define     AT91C_MC_FCMD_LOCK             ( ( unsigned int ) 0x2 )        /* (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */
+#define     AT91C_MC_FCMD_PROG_AND_LOCK    ( ( unsigned int ) 0x3 )        /* (MC) The lock sequence automatically happens after the programming sequence is completed. */
+#define     AT91C_MC_FCMD_UNLOCK           ( ( unsigned int ) 0x4 )        /* (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */
+#define     AT91C_MC_FCMD_ERASE_ALL        ( ( unsigned int ) 0x8 )        /* (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. */
+#define     AT91C_MC_FCMD_SET_GP_NVM       ( ( unsigned int ) 0xB )        /* (MC) Set General Purpose NVM bits. */
+#define     AT91C_MC_FCMD_CLR_GP_NVM       ( ( unsigned int ) 0xD )        /* (MC) Clear General Purpose NVM bits. */
+#define     AT91C_MC_FCMD_SET_SECURITY     ( ( unsigned int ) 0xF )        /* (MC) Set Security Bit. */
+#define AT91C_MC_PAGEN                     ( ( unsigned int ) 0x3FF << 8 ) /* (MC) Page Number */
+#define AT91C_MC_KEY                       ( ( unsigned int ) 0xFF << 24 ) /* (MC) Writing Protect Key */
+/* -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- */
+#define AT91C_MC_SECURITY                  ( ( unsigned int ) 0x1 << 4 )   /* (MC) Security Bit Status */
+#define AT91C_MC_GPNVM0                    ( ( unsigned int ) 0x1 << 8 )   /* (MC) Sector 0 Lock Status */
+#define AT91C_MC_GPNVM1                    ( ( unsigned int ) 0x1 << 9 )   /* (MC) Sector 1 Lock Status */
+#define AT91C_MC_GPNVM2                    ( ( unsigned int ) 0x1 << 10 )  /* (MC) Sector 2 Lock Status */
+#define AT91C_MC_GPNVM3                    ( ( unsigned int ) 0x1 << 11 )  /* (MC) Sector 3 Lock Status */
+#define AT91C_MC_GPNVM4                    ( ( unsigned int ) 0x1 << 12 )  /* (MC) Sector 4 Lock Status */
+#define AT91C_MC_GPNVM5                    ( ( unsigned int ) 0x1 << 13 )  /* (MC) Sector 5 Lock Status */
+#define AT91C_MC_GPNVM6                    ( ( unsigned int ) 0x1 << 14 )  /* (MC) Sector 6 Lock Status */
+#define AT91C_MC_GPNVM7                    ( ( unsigned int ) 0x1 << 15 )  /* (MC) Sector 7 Lock Status */
+#define AT91C_MC_LOCKS0                    ( ( unsigned int ) 0x1 << 16 )  /* (MC) Sector 0 Lock Status */
+#define AT91C_MC_LOCKS1                    ( ( unsigned int ) 0x1 << 17 )  /* (MC) Sector 1 Lock Status */
+#define AT91C_MC_LOCKS2                    ( ( unsigned int ) 0x1 << 18 )  /* (MC) Sector 2 Lock Status */
+#define AT91C_MC_LOCKS3                    ( ( unsigned int ) 0x1 << 19 )  /* (MC) Sector 3 Lock Status */
+#define AT91C_MC_LOCKS4                    ( ( unsigned int ) 0x1 << 20 )  /* (MC) Sector 4 Lock Status */
+#define AT91C_MC_LOCKS5                    ( ( unsigned int ) 0x1 << 21 )  /* (MC) Sector 5 Lock Status */
+#define AT91C_MC_LOCKS6                    ( ( unsigned int ) 0x1 << 22 )  /* (MC) Sector 6 Lock Status */
+#define AT91C_MC_LOCKS7                    ( ( unsigned int ) 0x1 << 23 )  /* (MC) Sector 7 Lock Status */
+#define AT91C_MC_LOCKS8                    ( ( unsigned int ) 0x1 << 24 )  /* (MC) Sector 8 Lock Status */
+#define AT91C_MC_LOCKS9                    ( ( unsigned int ) 0x1 << 25 )  /* (MC) Sector 9 Lock Status */
+#define AT91C_MC_LOCKS10                   ( ( unsigned int ) 0x1 << 26 )  /* (MC) Sector 10 Lock Status */
+#define AT91C_MC_LOCKS11                   ( ( unsigned int ) 0x1 << 27 )  /* (MC) Sector 11 Lock Status */
+#define AT91C_MC_LOCKS12                   ( ( unsigned int ) 0x1 << 28 )  /* (MC) Sector 12 Lock Status */
+#define AT91C_MC_LOCKS13                   ( ( unsigned int ) 0x1 << 29 )  /* (MC) Sector 13 Lock Status */
+#define AT91C_MC_LOCKS14                   ( ( unsigned int ) 0x1 << 30 )  /* (MC) Sector 14 Lock Status */
+#define AT91C_MC_LOCKS15                   ( ( unsigned int ) 0x1 << 31 )  /* (MC) Sector 15 Lock Status */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
-// *****************************************************************************
-typedef struct _AT91S_SPI {
-    AT91_REG     SPI_CR;    // Control Register
-    AT91_REG     SPI_MR;    // Mode Register
-    AT91_REG     SPI_RDR;   // Receive Data Register
-    AT91_REG     SPI_TDR;   // Transmit Data Register
-    AT91_REG     SPI_SR;    // Status Register
-    AT91_REG     SPI_IER;   // Interrupt Enable Register
-    AT91_REG     SPI_IDR;   // Interrupt Disable Register
-    AT91_REG     SPI_IMR;   // Interrupt Mask Register
-    AT91_REG     Reserved0[4];  //
-    AT91_REG     SPI_CSR[4];    // Chip Select Register
-    AT91_REG     Reserved1[48];     //
-    AT91_REG     SPI_RPR;   // Receive Pointer Register
-    AT91_REG     SPI_RCR;   // Receive Counter Register
-    AT91_REG     SPI_TPR;   // Transmit Pointer Register
-    AT91_REG     SPI_TCR;   // Transmit Counter Register
-    AT91_REG     SPI_RNPR;  // Receive Next Pointer Register
-    AT91_REG     SPI_RNCR;  // Receive Next Counter Register
-    AT91_REG     SPI_TNPR;  // Transmit Next Pointer Register
-    AT91_REG     SPI_TNCR;  // Transmit Next Counter Register
-    AT91_REG     SPI_PTCR;  // PDC Transfer Control Register
-    AT91_REG     SPI_PTSR;  // PDC Transfer Status Register
-} AT91S_SPI, *AT91PS_SPI;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Serial Parallel Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_SPI
+{
+    AT91_REG SPI_CR;          /* Control Register */
+    AT91_REG SPI_MR;          /* Mode Register */
+    AT91_REG SPI_RDR;         /* Receive Data Register */
+    AT91_REG SPI_TDR;         /* Transmit Data Register */
+    AT91_REG SPI_SR;          /* Status Register */
+    AT91_REG SPI_IER;         /* Interrupt Enable Register */
+    AT91_REG SPI_IDR;         /* Interrupt Disable Register */
+    AT91_REG SPI_IMR;         /* Interrupt Mask Register */
+    AT91_REG Reserved0[ 4 ];  /* */
+    AT91_REG SPI_CSR[ 4 ];    /* Chip Select Register */
+    AT91_REG Reserved1[ 48 ]; /* */
+    AT91_REG SPI_RPR;         /* Receive Pointer Register */
+    AT91_REG SPI_RCR;         /* Receive Counter Register */
+    AT91_REG SPI_TPR;         /* Transmit Pointer Register */
+    AT91_REG SPI_TCR;         /* Transmit Counter Register */
+    AT91_REG SPI_RNPR;        /* Receive Next Pointer Register */
+    AT91_REG SPI_RNCR;        /* Receive Next Counter Register */
+    AT91_REG SPI_TNPR;        /* Transmit Next Pointer Register */
+    AT91_REG SPI_TNCR;        /* Transmit Next Counter Register */
+    AT91_REG SPI_PTCR;        /* PDC Transfer Control Register */
+    AT91_REG SPI_PTSR;        /* PDC Transfer Status Register */
+} AT91S_SPI, * AT91PS_SPI;
 
-// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
-#define AT91C_SPI_SPIEN       ((unsigned int) 0x1 <<  0) // (SPI) SPI Enable
-#define AT91C_SPI_SPIDIS      ((unsigned int) 0x1 <<  1) // (SPI) SPI Disable
-#define AT91C_SPI_SWRST       ((unsigned int) 0x1 <<  7) // (SPI) SPI Software reset
-#define AT91C_SPI_LASTXFER    ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer
-// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
-#define AT91C_SPI_MSTR        ((unsigned int) 0x1 <<  0) // (SPI) Master/Slave Mode
-#define AT91C_SPI_PS          ((unsigned int) 0x1 <<  1) // (SPI) Peripheral Select
-#define     AT91C_SPI_PS_FIXED                ((unsigned int) 0x0 <<  1) // (SPI) Fixed Peripheral Select
-#define     AT91C_SPI_PS_VARIABLE             ((unsigned int) 0x1 <<  1) // (SPI) Variable Peripheral Select
-#define AT91C_SPI_PCSDEC      ((unsigned int) 0x1 <<  2) // (SPI) Chip Select Decode
-#define AT91C_SPI_FDIV        ((unsigned int) 0x1 <<  3) // (SPI) Clock Selection
-#define AT91C_SPI_MODFDIS     ((unsigned int) 0x1 <<  4) // (SPI) Mode Fault Detection
-#define AT91C_SPI_LLB         ((unsigned int) 0x1 <<  7) // (SPI) Clock Selection
-#define AT91C_SPI_PCS         ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select
-#define AT91C_SPI_DLYBCS      ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects
-// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
-#define AT91C_SPI_RD          ((unsigned int) 0xFFFF <<  0) // (SPI) Receive Data
-#define AT91C_SPI_RPCS        ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
-#define AT91C_SPI_TD          ((unsigned int) 0xFFFF <<  0) // (SPI) Transmit Data
-#define AT91C_SPI_TPCS        ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
-#define AT91C_SPI_RDRF        ((unsigned int) 0x1 <<  0) // (SPI) Receive Data Register Full
-#define AT91C_SPI_TDRE        ((unsigned int) 0x1 <<  1) // (SPI) Transmit Data Register Empty
-#define AT91C_SPI_MODF        ((unsigned int) 0x1 <<  2) // (SPI) Mode Fault Error
-#define AT91C_SPI_OVRES       ((unsigned int) 0x1 <<  3) // (SPI) Overrun Error Status
-#define AT91C_SPI_ENDRX       ((unsigned int) 0x1 <<  4) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_ENDTX       ((unsigned int) 0x1 <<  5) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_RXBUFF      ((unsigned int) 0x1 <<  6) // (SPI) RXBUFF Interrupt
-#define AT91C_SPI_TXBUFE      ((unsigned int) 0x1 <<  7) // (SPI) TXBUFE Interrupt
-#define AT91C_SPI_NSSR        ((unsigned int) 0x1 <<  8) // (SPI) NSSR Interrupt
-#define AT91C_SPI_TXEMPTY     ((unsigned int) 0x1 <<  9) // (SPI) TXEMPTY Interrupt
-#define AT91C_SPI_SPIENS      ((unsigned int) 0x1 << 16) // (SPI) Enable Status
-// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
-// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
-// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
-// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
-#define AT91C_SPI_CPOL        ((unsigned int) 0x1 <<  0) // (SPI) Clock Polarity
-#define AT91C_SPI_NCPHA       ((unsigned int) 0x1 <<  1) // (SPI) Clock Phase
-#define AT91C_SPI_CSAAT       ((unsigned int) 0x1 <<  3) // (SPI) Chip Select Active After Transfer
-#define AT91C_SPI_BITS        ((unsigned int) 0xF <<  4) // (SPI) Bits Per Transfer
-#define     AT91C_SPI_BITS_8                    ((unsigned int) 0x0 <<  4) // (SPI) 8 Bits Per transfer
-#define     AT91C_SPI_BITS_9                    ((unsigned int) 0x1 <<  4) // (SPI) 9 Bits Per transfer
-#define     AT91C_SPI_BITS_10                   ((unsigned int) 0x2 <<  4) // (SPI) 10 Bits Per transfer
-#define     AT91C_SPI_BITS_11                   ((unsigned int) 0x3 <<  4) // (SPI) 11 Bits Per transfer
-#define     AT91C_SPI_BITS_12                   ((unsigned int) 0x4 <<  4) // (SPI) 12 Bits Per transfer
-#define     AT91C_SPI_BITS_13                   ((unsigned int) 0x5 <<  4) // (SPI) 13 Bits Per transfer
-#define     AT91C_SPI_BITS_14                   ((unsigned int) 0x6 <<  4) // (SPI) 14 Bits Per transfer
-#define     AT91C_SPI_BITS_15                   ((unsigned int) 0x7 <<  4) // (SPI) 15 Bits Per transfer
-#define     AT91C_SPI_BITS_16                   ((unsigned int) 0x8 <<  4) // (SPI) 16 Bits Per transfer
-#define AT91C_SPI_SCBR        ((unsigned int) 0xFF <<  8) // (SPI) Serial Clock Baud Rate
-#define AT91C_SPI_DLYBS       ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK
-#define AT91C_SPI_DLYBCT      ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers
+/* -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */
+#define AT91C_SPI_SPIEN              ( ( unsigned int ) 0x1 << 0 )    /* (SPI) SPI Enable */
+#define AT91C_SPI_SPIDIS             ( ( unsigned int ) 0x1 << 1 )    /* (SPI) SPI Disable */
+#define AT91C_SPI_SWRST              ( ( unsigned int ) 0x1 << 7 )    /* (SPI) SPI Software reset */
+#define AT91C_SPI_LASTXFER           ( ( unsigned int ) 0x1 << 24 )   /* (SPI) SPI Last Transfer */
+/* -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- */
+#define AT91C_SPI_MSTR               ( ( unsigned int ) 0x1 << 0 )    /* (SPI) Master/Slave Mode */
+#define AT91C_SPI_PS                 ( ( unsigned int ) 0x1 << 1 )    /* (SPI) Peripheral Select */
+#define     AT91C_SPI_PS_FIXED       ( ( unsigned int ) 0x0 << 1 )    /* (SPI) Fixed Peripheral Select */
+#define     AT91C_SPI_PS_VARIABLE    ( ( unsigned int ) 0x1 << 1 )    /* (SPI) Variable Peripheral Select */
+#define AT91C_SPI_PCSDEC             ( ( unsigned int ) 0x1 << 2 )    /* (SPI) Chip Select Decode */
+#define AT91C_SPI_FDIV               ( ( unsigned int ) 0x1 << 3 )    /* (SPI) Clock Selection */
+#define AT91C_SPI_MODFDIS            ( ( unsigned int ) 0x1 << 4 )    /* (SPI) Mode Fault Detection */
+#define AT91C_SPI_LLB                ( ( unsigned int ) 0x1 << 7 )    /* (SPI) Clock Selection */
+#define AT91C_SPI_PCS                ( ( unsigned int ) 0xF << 16 )   /* (SPI) Peripheral Chip Select */
+#define AT91C_SPI_DLYBCS             ( ( unsigned int ) 0xFF << 24 )  /* (SPI) Delay Between Chip Selects */
+/* -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- */
+#define AT91C_SPI_RD                 ( ( unsigned int ) 0xFFFF << 0 ) /* (SPI) Receive Data */
+#define AT91C_SPI_RPCS               ( ( unsigned int ) 0xF << 16 )   /* (SPI) Peripheral Chip Select Status */
+/* -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- */
+#define AT91C_SPI_TD                 ( ( unsigned int ) 0xFFFF << 0 ) /* (SPI) Transmit Data */
+#define AT91C_SPI_TPCS               ( ( unsigned int ) 0xF << 16 )   /* (SPI) Peripheral Chip Select Status */
+/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
+#define AT91C_SPI_RDRF               ( ( unsigned int ) 0x1 << 0 )    /* (SPI) Receive Data Register Full */
+#define AT91C_SPI_TDRE               ( ( unsigned int ) 0x1 << 1 )    /* (SPI) Transmit Data Register Empty */
+#define AT91C_SPI_MODF               ( ( unsigned int ) 0x1 << 2 )    /* (SPI) Mode Fault Error */
+#define AT91C_SPI_OVRES              ( ( unsigned int ) 0x1 << 3 )    /* (SPI) Overrun Error Status */
+#define AT91C_SPI_ENDRX              ( ( unsigned int ) 0x1 << 4 )    /* (SPI) End of Receiver Transfer */
+#define AT91C_SPI_ENDTX              ( ( unsigned int ) 0x1 << 5 )    /* (SPI) End of Receiver Transfer */
+#define AT91C_SPI_RXBUFF             ( ( unsigned int ) 0x1 << 6 )    /* (SPI) RXBUFF Interrupt */
+#define AT91C_SPI_TXBUFE             ( ( unsigned int ) 0x1 << 7 )    /* (SPI) TXBUFE Interrupt */
+#define AT91C_SPI_NSSR               ( ( unsigned int ) 0x1 << 8 )    /* (SPI) NSSR Interrupt */
+#define AT91C_SPI_TXEMPTY            ( ( unsigned int ) 0x1 << 9 )    /* (SPI) TXEMPTY Interrupt */
+#define AT91C_SPI_SPIENS             ( ( unsigned int ) 0x1 << 16 )   /* (SPI) Enable Status */
+/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
+/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
+/* -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */
+/* -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */
+#define AT91C_SPI_CPOL           ( ( unsigned int ) 0x1 << 0 )   /* (SPI) Clock Polarity */
+#define AT91C_SPI_NCPHA          ( ( unsigned int ) 0x1 << 1 )   /* (SPI) Clock Phase */
+#define AT91C_SPI_CSAAT          ( ( unsigned int ) 0x1 << 3 )   /* (SPI) Chip Select Active After Transfer */
+#define AT91C_SPI_BITS           ( ( unsigned int ) 0xF << 4 )   /* (SPI) Bits Per Transfer */
+#define     AT91C_SPI_BITS_8     ( ( unsigned int ) 0x0 << 4 )   /* (SPI) 8 Bits Per transfer */
+#define     AT91C_SPI_BITS_9     ( ( unsigned int ) 0x1 << 4 )   /* (SPI) 9 Bits Per transfer */
+#define     AT91C_SPI_BITS_10    ( ( unsigned int ) 0x2 << 4 )   /* (SPI) 10 Bits Per transfer */
+#define     AT91C_SPI_BITS_11    ( ( unsigned int ) 0x3 << 4 )   /* (SPI) 11 Bits Per transfer */
+#define     AT91C_SPI_BITS_12    ( ( unsigned int ) 0x4 << 4 )   /* (SPI) 12 Bits Per transfer */
+#define     AT91C_SPI_BITS_13    ( ( unsigned int ) 0x5 << 4 )   /* (SPI) 13 Bits Per transfer */
+#define     AT91C_SPI_BITS_14    ( ( unsigned int ) 0x6 << 4 )   /* (SPI) 14 Bits Per transfer */
+#define     AT91C_SPI_BITS_15    ( ( unsigned int ) 0x7 << 4 )   /* (SPI) 15 Bits Per transfer */
+#define     AT91C_SPI_BITS_16    ( ( unsigned int ) 0x8 << 4 )   /* (SPI) 16 Bits Per transfer */
+#define AT91C_SPI_SCBR           ( ( unsigned int ) 0xFF << 8 )  /* (SPI) Serial Clock Baud Rate */
+#define AT91C_SPI_DLYBS          ( ( unsigned int ) 0xFF << 16 ) /* (SPI) Delay Before SPCK */
+#define AT91C_SPI_DLYBCT         ( ( unsigned int ) 0xFF << 24 ) /* (SPI) Delay Between Consecutive Transfers */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Usart
-// *****************************************************************************
-typedef struct _AT91S_USART {
-    AT91_REG     US_CR;     // Control Register
-    AT91_REG     US_MR;     // Mode Register
-    AT91_REG     US_IER;    // Interrupt Enable Register
-    AT91_REG     US_IDR;    // Interrupt Disable Register
-    AT91_REG     US_IMR;    // Interrupt Mask Register
-    AT91_REG     US_CSR;    // Channel Status Register
-    AT91_REG     US_RHR;    // Receiver Holding Register
-    AT91_REG     US_THR;    // Transmitter Holding Register
-    AT91_REG     US_BRGR;   // Baud Rate Generator Register
-    AT91_REG     US_RTOR;   // Receiver Time-out Register
-    AT91_REG     US_TTGR;   // Transmitter Time-guard Register
-    AT91_REG     Reserved0[5];  //
-    AT91_REG     US_FIDI;   // FI_DI_Ratio Register
-    AT91_REG     US_NER;    // Nb Errors Register
-    AT91_REG     Reserved1[1];  //
-    AT91_REG     US_IF;     // IRDA_FILTER Register
-    AT91_REG     Reserved2[44];     //
-    AT91_REG     US_RPR;    // Receive Pointer Register
-    AT91_REG     US_RCR;    // Receive Counter Register
-    AT91_REG     US_TPR;    // Transmit Pointer Register
-    AT91_REG     US_TCR;    // Transmit Counter Register
-    AT91_REG     US_RNPR;   // Receive Next Pointer Register
-    AT91_REG     US_RNCR;   // Receive Next Counter Register
-    AT91_REG     US_TNPR;   // Transmit Next Pointer Register
-    AT91_REG     US_TNCR;   // Transmit Next Counter Register
-    AT91_REG     US_PTCR;   // PDC Transfer Control Register
-    AT91_REG     US_PTSR;   // PDC Transfer Status Register
-} AT91S_USART, *AT91PS_USART;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Usart */
+/* ***************************************************************************** */
+typedef struct _AT91S_USART
+{
+    AT91_REG US_CR;           /* Control Register */
+    AT91_REG US_MR;           /* Mode Register */
+    AT91_REG US_IER;          /* Interrupt Enable Register */
+    AT91_REG US_IDR;          /* Interrupt Disable Register */
+    AT91_REG US_IMR;          /* Interrupt Mask Register */
+    AT91_REG US_CSR;          /* Channel Status Register */
+    AT91_REG US_RHR;          /* Receiver Holding Register */
+    AT91_REG US_THR;          /* Transmitter Holding Register */
+    AT91_REG US_BRGR;         /* Baud Rate Generator Register */
+    AT91_REG US_RTOR;         /* Receiver Time-out Register */
+    AT91_REG US_TTGR;         /* Transmitter Time-guard Register */
+    AT91_REG Reserved0[ 5 ];  /* */
+    AT91_REG US_FIDI;         /* FI_DI_Ratio Register */
+    AT91_REG US_NER;          /* Nb Errors Register */
+    AT91_REG Reserved1[ 1 ];  /* */
+    AT91_REG US_IF;           /* IRDA_FILTER Register */
+    AT91_REG Reserved2[ 44 ]; /* */
+    AT91_REG US_RPR;          /* Receive Pointer Register */
+    AT91_REG US_RCR;          /* Receive Counter Register */
+    AT91_REG US_TPR;          /* Transmit Pointer Register */
+    AT91_REG US_TCR;          /* Transmit Counter Register */
+    AT91_REG US_RNPR;         /* Receive Next Pointer Register */
+    AT91_REG US_RNCR;         /* Receive Next Counter Register */
+    AT91_REG US_TNPR;         /* Transmit Next Pointer Register */
+    AT91_REG US_TNCR;         /* Transmit Next Counter Register */
+    AT91_REG US_PTCR;         /* PDC Transfer Control Register */
+    AT91_REG US_PTSR;         /* PDC Transfer Status Register */
+} AT91S_USART, * AT91PS_USART;
 
-// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
-#define AT91C_US_STTBRK       ((unsigned int) 0x1 <<  9) // (USART) Start Break
-#define AT91C_US_STPBRK       ((unsigned int) 0x1 << 10) // (USART) Stop Break
-#define AT91C_US_STTTO        ((unsigned int) 0x1 << 11) // (USART) Start Time-out
-#define AT91C_US_SENDA        ((unsigned int) 0x1 << 12) // (USART) Send Address
-#define AT91C_US_RSTIT        ((unsigned int) 0x1 << 13) // (USART) Reset Iterations
-#define AT91C_US_RSTNACK      ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge
-#define AT91C_US_RETTO        ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out
-#define AT91C_US_DTREN        ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable
-#define AT91C_US_DTRDIS       ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable
-#define AT91C_US_RTSEN        ((unsigned int) 0x1 << 18) // (USART) Request to Send enable
-#define AT91C_US_RTSDIS       ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable
-// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
-#define AT91C_US_USMODE       ((unsigned int) 0xF <<  0) // (USART) Usart mode
-#define     AT91C_US_USMODE_NORMAL               ((unsigned int) 0x0) // (USART) Normal
-#define     AT91C_US_USMODE_RS485                ((unsigned int) 0x1) // (USART) RS485
-#define     AT91C_US_USMODE_HWHSH                ((unsigned int) 0x2) // (USART) Hardware Handshaking
-#define     AT91C_US_USMODE_MODEM                ((unsigned int) 0x3) // (USART) Modem
-#define     AT91C_US_USMODE_ISO7816_0            ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0
-#define     AT91C_US_USMODE_ISO7816_1            ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1
-#define     AT91C_US_USMODE_IRDA                 ((unsigned int) 0x8) // (USART) IrDA
-#define     AT91C_US_USMODE_SWHSH                ((unsigned int) 0xC) // (USART) Software Handshaking
-#define AT91C_US_CLKS         ((unsigned int) 0x3 <<  4) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define     AT91C_US_CLKS_CLOCK                ((unsigned int) 0x0 <<  4) // (USART) Clock
-#define     AT91C_US_CLKS_FDIV1                ((unsigned int) 0x1 <<  4) // (USART) fdiv1
-#define     AT91C_US_CLKS_SLOW                 ((unsigned int) 0x2 <<  4) // (USART) slow_clock (ARM)
-#define     AT91C_US_CLKS_EXT                  ((unsigned int) 0x3 <<  4) // (USART) External (SCK)
-#define AT91C_US_CHRL         ((unsigned int) 0x3 <<  6) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define     AT91C_US_CHRL_5_BITS               ((unsigned int) 0x0 <<  6) // (USART) Character Length: 5 bits
-#define     AT91C_US_CHRL_6_BITS               ((unsigned int) 0x1 <<  6) // (USART) Character Length: 6 bits
-#define     AT91C_US_CHRL_7_BITS               ((unsigned int) 0x2 <<  6) // (USART) Character Length: 7 bits
-#define     AT91C_US_CHRL_8_BITS               ((unsigned int) 0x3 <<  6) // (USART) Character Length: 8 bits
-#define AT91C_US_SYNC         ((unsigned int) 0x1 <<  8) // (USART) Synchronous Mode Select
-#define AT91C_US_NBSTOP       ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits
-#define     AT91C_US_NBSTOP_1_BIT                ((unsigned int) 0x0 << 12) // (USART) 1 stop bit
-#define     AT91C_US_NBSTOP_15_BIT               ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
-#define     AT91C_US_NBSTOP_2_BIT                ((unsigned int) 0x2 << 12) // (USART) 2 stop bits
-#define AT91C_US_MSBF         ((unsigned int) 0x1 << 16) // (USART) Bit Order
-#define AT91C_US_MODE9        ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length
-#define AT91C_US_CKLO         ((unsigned int) 0x1 << 18) // (USART) Clock Output Select
-#define AT91C_US_OVER         ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode
-#define AT91C_US_INACK        ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge
-#define AT91C_US_DSNACK       ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK
-#define AT91C_US_MAX_ITER     ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions
-#define AT91C_US_FILTER       ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter
-// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
-#define AT91C_US_RXBRK        ((unsigned int) 0x1 <<  2) // (USART) Break Received/End of Break
-#define AT91C_US_TIMEOUT      ((unsigned int) 0x1 <<  8) // (USART) Receiver Time-out
-#define AT91C_US_ITERATION    ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached
-#define AT91C_US_NACK         ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge
-#define AT91C_US_RIIC         ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag
-#define AT91C_US_DSRIC        ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag
-#define AT91C_US_DCDIC        ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag
-#define AT91C_US_CTSIC        ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag
-// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
-// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
-// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
-#define AT91C_US_RI           ((unsigned int) 0x1 << 20) // (USART) Image of RI Input
-#define AT91C_US_DSR          ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input
-#define AT91C_US_DCD          ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input
-#define AT91C_US_CTS          ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input
+/* -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- */
+#define AT91C_US_STTBRK                  ( ( unsigned int ) 0x1 << 9 )  /* (USART) Start Break */
+#define AT91C_US_STPBRK                  ( ( unsigned int ) 0x1 << 10 ) /* (USART) Stop Break */
+#define AT91C_US_STTTO                   ( ( unsigned int ) 0x1 << 11 ) /* (USART) Start Time-out */
+#define AT91C_US_SENDA                   ( ( unsigned int ) 0x1 << 12 ) /* (USART) Send Address */
+#define AT91C_US_RSTIT                   ( ( unsigned int ) 0x1 << 13 ) /* (USART) Reset Iterations */
+#define AT91C_US_RSTNACK                 ( ( unsigned int ) 0x1 << 14 ) /* (USART) Reset Non Acknowledge */
+#define AT91C_US_RETTO                   ( ( unsigned int ) 0x1 << 15 ) /* (USART) Rearm Time-out */
+#define AT91C_US_DTREN                   ( ( unsigned int ) 0x1 << 16 ) /* (USART) Data Terminal ready Enable */
+#define AT91C_US_DTRDIS                  ( ( unsigned int ) 0x1 << 17 ) /* (USART) Data Terminal ready Disable */
+#define AT91C_US_RTSEN                   ( ( unsigned int ) 0x1 << 18 ) /* (USART) Request to Send enable */
+#define AT91C_US_RTSDIS                  ( ( unsigned int ) 0x1 << 19 ) /* (USART) Request to Send Disable */
+/* -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- */
+#define AT91C_US_USMODE                  ( ( unsigned int ) 0xF << 0 )  /* (USART) Usart mode */
+#define     AT91C_US_USMODE_NORMAL       ( ( unsigned int ) 0x0 )       /* (USART) Normal */
+#define     AT91C_US_USMODE_RS485        ( ( unsigned int ) 0x1 )       /* (USART) RS485 */
+#define     AT91C_US_USMODE_HWHSH        ( ( unsigned int ) 0x2 )       /* (USART) Hardware Handshaking */
+#define     AT91C_US_USMODE_MODEM        ( ( unsigned int ) 0x3 )       /* (USART) Modem */
+#define     AT91C_US_USMODE_ISO7816_0    ( ( unsigned int ) 0x4 )       /* (USART) ISO7816 protocol: T = 0 */
+#define     AT91C_US_USMODE_ISO7816_1    ( ( unsigned int ) 0x6 )       /* (USART) ISO7816 protocol: T = 1 */
+#define     AT91C_US_USMODE_IRDA         ( ( unsigned int ) 0x8 )       /* (USART) IrDA */
+#define     AT91C_US_USMODE_SWHSH        ( ( unsigned int ) 0xC )       /* (USART) Software Handshaking */
+#define AT91C_US_CLKS                    ( ( unsigned int ) 0x3 << 4 )  /* (USART) Clock Selection (Baud Rate generator Input Clock */
+#define     AT91C_US_CLKS_CLOCK          ( ( unsigned int ) 0x0 << 4 )  /* (USART) Clock */
+#define     AT91C_US_CLKS_FDIV1          ( ( unsigned int ) 0x1 << 4 )  /* (USART) fdiv1 */
+#define     AT91C_US_CLKS_SLOW           ( ( unsigned int ) 0x2 << 4 )  /* (USART) slow_clock (ARM) */
+#define     AT91C_US_CLKS_EXT            ( ( unsigned int ) 0x3 << 4 )  /* (USART) External (SCK) */
+#define AT91C_US_CHRL                    ( ( unsigned int ) 0x3 << 6 )  /* (USART) Clock Selection (Baud Rate generator Input Clock */
+#define     AT91C_US_CHRL_5_BITS         ( ( unsigned int ) 0x0 << 6 )  /* (USART) Character Length: 5 bits */
+#define     AT91C_US_CHRL_6_BITS         ( ( unsigned int ) 0x1 << 6 )  /* (USART) Character Length: 6 bits */
+#define     AT91C_US_CHRL_7_BITS         ( ( unsigned int ) 0x2 << 6 )  /* (USART) Character Length: 7 bits */
+#define     AT91C_US_CHRL_8_BITS         ( ( unsigned int ) 0x3 << 6 )  /* (USART) Character Length: 8 bits */
+#define AT91C_US_SYNC                    ( ( unsigned int ) 0x1 << 8 )  /* (USART) Synchronous Mode Select */
+#define AT91C_US_NBSTOP                  ( ( unsigned int ) 0x3 << 12 ) /* (USART) Number of Stop bits */
+#define     AT91C_US_NBSTOP_1_BIT        ( ( unsigned int ) 0x0 << 12 ) /* (USART) 1 stop bit */
+#define     AT91C_US_NBSTOP_15_BIT       ( ( unsigned int ) 0x1 << 12 ) /* (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits */
+#define     AT91C_US_NBSTOP_2_BIT        ( ( unsigned int ) 0x2 << 12 ) /* (USART) 2 stop bits */
+#define AT91C_US_MSBF                    ( ( unsigned int ) 0x1 << 16 ) /* (USART) Bit Order */
+#define AT91C_US_MODE9                   ( ( unsigned int ) 0x1 << 17 ) /* (USART) 9-bit Character length */
+#define AT91C_US_CKLO                    ( ( unsigned int ) 0x1 << 18 ) /* (USART) Clock Output Select */
+#define AT91C_US_OVER                    ( ( unsigned int ) 0x1 << 19 ) /* (USART) Over Sampling Mode */
+#define AT91C_US_INACK                   ( ( unsigned int ) 0x1 << 20 ) /* (USART) Inhibit Non Acknowledge */
+#define AT91C_US_DSNACK                  ( ( unsigned int ) 0x1 << 21 ) /* (USART) Disable Successive NACK */
+#define AT91C_US_MAX_ITER                ( ( unsigned int ) 0x1 << 24 ) /* (USART) Number of Repetitions */
+#define AT91C_US_FILTER                  ( ( unsigned int ) 0x1 << 28 ) /* (USART) Receive Line Filter */
+/* -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- */
+#define AT91C_US_RXBRK                   ( ( unsigned int ) 0x1 << 2 )  /* (USART) Break Received/End of Break */
+#define AT91C_US_TIMEOUT                 ( ( unsigned int ) 0x1 << 8 )  /* (USART) Receiver Time-out */
+#define AT91C_US_ITERATION               ( ( unsigned int ) 0x1 << 10 ) /* (USART) Max number of Repetitions Reached */
+#define AT91C_US_NACK                    ( ( unsigned int ) 0x1 << 13 ) /* (USART) Non Acknowledge */
+#define AT91C_US_RIIC                    ( ( unsigned int ) 0x1 << 16 ) /* (USART) Ring INdicator Input Change Flag */
+#define AT91C_US_DSRIC                   ( ( unsigned int ) 0x1 << 17 ) /* (USART) Data Set Ready Input Change Flag */
+#define AT91C_US_DCDIC                   ( ( unsigned int ) 0x1 << 18 ) /* (USART) Data Carrier Flag */
+#define AT91C_US_CTSIC                   ( ( unsigned int ) 0x1 << 19 ) /* (USART) Clear To Send Input Change Flag */
+/* -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- */
+/* -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- */
+/* -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- */
+#define AT91C_US_RI     ( ( unsigned int ) 0x1 << 20 )   /* (USART) Image of RI Input */
+#define AT91C_US_DSR    ( ( unsigned int ) 0x1 << 21 )   /* (USART) Image of DSR Input */
+#define AT91C_US_DCD    ( ( unsigned int ) 0x1 << 22 )   /* (USART) Image of DCD Input */
+#define AT91C_US_CTS    ( ( unsigned int ) 0x1 << 23 )   /* (USART) Image of CTS Input */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_SSC {
-    AT91_REG     SSC_CR;    // Control Register
-    AT91_REG     SSC_CMR;   // Clock Mode Register
-    AT91_REG     Reserved0[2];  //
-    AT91_REG     SSC_RCMR;  // Receive Clock ModeRegister
-    AT91_REG     SSC_RFMR;  // Receive Frame Mode Register
-    AT91_REG     SSC_TCMR;  // Transmit Clock Mode Register
-    AT91_REG     SSC_TFMR;  // Transmit Frame Mode Register
-    AT91_REG     SSC_RHR;   // Receive Holding Register
-    AT91_REG     SSC_THR;   // Transmit Holding Register
-    AT91_REG     Reserved1[2];  //
-    AT91_REG     SSC_RSHR;  // Receive Sync Holding Register
-    AT91_REG     SSC_TSHR;  // Transmit Sync Holding Register
-    AT91_REG     Reserved2[2];  //
-    AT91_REG     SSC_SR;    // Status Register
-    AT91_REG     SSC_IER;   // Interrupt Enable Register
-    AT91_REG     SSC_IDR;   // Interrupt Disable Register
-    AT91_REG     SSC_IMR;   // Interrupt Mask Register
-    AT91_REG     Reserved3[44];     //
-    AT91_REG     SSC_RPR;   // Receive Pointer Register
-    AT91_REG     SSC_RCR;   // Receive Counter Register
-    AT91_REG     SSC_TPR;   // Transmit Pointer Register
-    AT91_REG     SSC_TCR;   // Transmit Counter Register
-    AT91_REG     SSC_RNPR;  // Receive Next Pointer Register
-    AT91_REG     SSC_RNCR;  // Receive Next Counter Register
-    AT91_REG     SSC_TNPR;  // Transmit Next Pointer Register
-    AT91_REG     SSC_TNCR;  // Transmit Next Counter Register
-    AT91_REG     SSC_PTCR;  // PDC Transfer Control Register
-    AT91_REG     SSC_PTSR;  // PDC Transfer Status Register
-} AT91S_SSC, *AT91PS_SSC;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_SSC
+{
+    AT91_REG SSC_CR;          /* Control Register */
+    AT91_REG SSC_CMR;         /* Clock Mode Register */
+    AT91_REG Reserved0[ 2 ];  /* */
+    AT91_REG SSC_RCMR;        /* Receive Clock ModeRegister */
+    AT91_REG SSC_RFMR;        /* Receive Frame Mode Register */
+    AT91_REG SSC_TCMR;        /* Transmit Clock Mode Register */
+    AT91_REG SSC_TFMR;        /* Transmit Frame Mode Register */
+    AT91_REG SSC_RHR;         /* Receive Holding Register */
+    AT91_REG SSC_THR;         /* Transmit Holding Register */
+    AT91_REG Reserved1[ 2 ];  /* */
+    AT91_REG SSC_RSHR;        /* Receive Sync Holding Register */
+    AT91_REG SSC_TSHR;        /* Transmit Sync Holding Register */
+    AT91_REG Reserved2[ 2 ];  /* */
+    AT91_REG SSC_SR;          /* Status Register */
+    AT91_REG SSC_IER;         /* Interrupt Enable Register */
+    AT91_REG SSC_IDR;         /* Interrupt Disable Register */
+    AT91_REG SSC_IMR;         /* Interrupt Mask Register */
+    AT91_REG Reserved3[ 44 ]; /* */
+    AT91_REG SSC_RPR;         /* Receive Pointer Register */
+    AT91_REG SSC_RCR;         /* Receive Counter Register */
+    AT91_REG SSC_TPR;         /* Transmit Pointer Register */
+    AT91_REG SSC_TCR;         /* Transmit Counter Register */
+    AT91_REG SSC_RNPR;        /* Receive Next Pointer Register */
+    AT91_REG SSC_RNCR;        /* Receive Next Counter Register */
+    AT91_REG SSC_TNPR;        /* Transmit Next Pointer Register */
+    AT91_REG SSC_TNCR;        /* Transmit Next Counter Register */
+    AT91_REG SSC_PTCR;        /* PDC Transfer Control Register */
+    AT91_REG SSC_PTSR;        /* PDC Transfer Status Register */
+} AT91S_SSC, * AT91PS_SSC;
 
-// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
-#define AT91C_SSC_RXEN        ((unsigned int) 0x1 <<  0) // (SSC) Receive Enable
-#define AT91C_SSC_RXDIS       ((unsigned int) 0x1 <<  1) // (SSC) Receive Disable
-#define AT91C_SSC_TXEN        ((unsigned int) 0x1 <<  8) // (SSC) Transmit Enable
-#define AT91C_SSC_TXDIS       ((unsigned int) 0x1 <<  9) // (SSC) Transmit Disable
-#define AT91C_SSC_SWRST       ((unsigned int) 0x1 << 15) // (SSC) Software Reset
-// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
-#define AT91C_SSC_CKS         ((unsigned int) 0x3 <<  0) // (SSC) Receive/Transmit Clock Selection
-#define     AT91C_SSC_CKS_DIV                  ((unsigned int) 0x0) // (SSC) Divided Clock
-#define     AT91C_SSC_CKS_TK                   ((unsigned int) 0x1) // (SSC) TK Clock signal
-#define     AT91C_SSC_CKS_RK                   ((unsigned int) 0x2) // (SSC) RK pin
-#define AT91C_SSC_CKO         ((unsigned int) 0x7 <<  2) // (SSC) Receive/Transmit Clock Output Mode Selection
-#define     AT91C_SSC_CKO_NONE                 ((unsigned int) 0x0 <<  2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
-#define     AT91C_SSC_CKO_CONTINOUS            ((unsigned int) 0x1 <<  2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
-#define     AT91C_SSC_CKO_DATA_TX              ((unsigned int) 0x2 <<  2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
-#define AT91C_SSC_CKI         ((unsigned int) 0x1 <<  5) // (SSC) Receive/Transmit Clock Inversion
-#define AT91C_SSC_START       ((unsigned int) 0xF <<  8) // (SSC) Receive/Transmit Start Selection
-#define     AT91C_SSC_START_CONTINOUS            ((unsigned int) 0x0 <<  8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
-#define     AT91C_SSC_START_TX                   ((unsigned int) 0x1 <<  8) // (SSC) Transmit/Receive start
-#define     AT91C_SSC_START_LOW_RF               ((unsigned int) 0x2 <<  8) // (SSC) Detection of a low level on RF input
-#define     AT91C_SSC_START_HIGH_RF              ((unsigned int) 0x3 <<  8) // (SSC) Detection of a high level on RF input
-#define     AT91C_SSC_START_FALL_RF              ((unsigned int) 0x4 <<  8) // (SSC) Detection of a falling edge on RF input
-#define     AT91C_SSC_START_RISE_RF              ((unsigned int) 0x5 <<  8) // (SSC) Detection of a rising edge on RF input
-#define     AT91C_SSC_START_LEVEL_RF             ((unsigned int) 0x6 <<  8) // (SSC) Detection of any level change on RF input
-#define     AT91C_SSC_START_EDGE_RF              ((unsigned int) 0x7 <<  8) // (SSC) Detection of any edge on RF input
-#define     AT91C_SSC_START_0                    ((unsigned int) 0x8 <<  8) // (SSC) Compare 0
-#define AT91C_SSC_STTDLY      ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay
-#define AT91C_SSC_PERIOD      ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
-// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
-#define AT91C_SSC_DATLEN      ((unsigned int) 0x1F <<  0) // (SSC) Data Length
-#define AT91C_SSC_LOOP        ((unsigned int) 0x1 <<  5) // (SSC) Loop Mode
-#define AT91C_SSC_MSBF        ((unsigned int) 0x1 <<  7) // (SSC) Most Significant Bit First
-#define AT91C_SSC_DATNB       ((unsigned int) 0xF <<  8) // (SSC) Data Number per Frame
-#define AT91C_SSC_FSLEN       ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length
-#define AT91C_SSC_FSOS        ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
-#define     AT91C_SSC_FSOS_NONE                 ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
-#define     AT91C_SSC_FSOS_NEGATIVE             ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
-#define     AT91C_SSC_FSOS_POSITIVE             ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
-#define     AT91C_SSC_FSOS_LOW                  ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
-#define     AT91C_SSC_FSOS_HIGH                 ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
-#define     AT91C_SSC_FSOS_TOGGLE               ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
-#define AT91C_SSC_FSEDGE      ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection
-// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
-// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
-#define AT91C_SSC_DATDEF      ((unsigned int) 0x1 <<  5) // (SSC) Data Default Value
-#define AT91C_SSC_FSDEN       ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable
-// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
-#define AT91C_SSC_TXRDY       ((unsigned int) 0x1 <<  0) // (SSC) Transmit Ready
-#define AT91C_SSC_TXEMPTY     ((unsigned int) 0x1 <<  1) // (SSC) Transmit Empty
-#define AT91C_SSC_ENDTX       ((unsigned int) 0x1 <<  2) // (SSC) End Of Transmission
-#define AT91C_SSC_TXBUFE      ((unsigned int) 0x1 <<  3) // (SSC) Transmit Buffer Empty
-#define AT91C_SSC_RXRDY       ((unsigned int) 0x1 <<  4) // (SSC) Receive Ready
-#define AT91C_SSC_OVRUN       ((unsigned int) 0x1 <<  5) // (SSC) Receive Overrun
-#define AT91C_SSC_ENDRX       ((unsigned int) 0x1 <<  6) // (SSC) End of Reception
-#define AT91C_SSC_RXBUFF      ((unsigned int) 0x1 <<  7) // (SSC) Receive Buffer Full
-#define AT91C_SSC_TXSYN       ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync
-#define AT91C_SSC_RXSYN       ((unsigned int) 0x1 << 11) // (SSC) Receive Sync
-#define AT91C_SSC_TXENA       ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable
-#define AT91C_SSC_RXENA       ((unsigned int) 0x1 << 17) // (SSC) Receive Enable
-// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
-// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
-// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
+/* -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- */
+#define AT91C_SSC_RXEN                    ( ( unsigned int ) 0x1 << 0 )   /* (SSC) Receive Enable */
+#define AT91C_SSC_RXDIS                   ( ( unsigned int ) 0x1 << 1 )   /* (SSC) Receive Disable */
+#define AT91C_SSC_TXEN                    ( ( unsigned int ) 0x1 << 8 )   /* (SSC) Transmit Enable */
+#define AT91C_SSC_TXDIS                   ( ( unsigned int ) 0x1 << 9 )   /* (SSC) Transmit Disable */
+#define AT91C_SSC_SWRST                   ( ( unsigned int ) 0x1 << 15 )  /* (SSC) Software Reset */
+/* -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- */
+#define AT91C_SSC_CKS                     ( ( unsigned int ) 0x3 << 0 )   /* (SSC) Receive/Transmit Clock Selection */
+#define     AT91C_SSC_CKS_DIV             ( ( unsigned int ) 0x0 )        /* (SSC) Divided Clock */
+#define     AT91C_SSC_CKS_TK              ( ( unsigned int ) 0x1 )        /* (SSC) TK Clock signal */
+#define     AT91C_SSC_CKS_RK              ( ( unsigned int ) 0x2 )        /* (SSC) RK pin */
+#define AT91C_SSC_CKO                     ( ( unsigned int ) 0x7 << 2 )   /* (SSC) Receive/Transmit Clock Output Mode Selection */
+#define     AT91C_SSC_CKO_NONE            ( ( unsigned int ) 0x0 << 2 )   /* (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only */
+#define     AT91C_SSC_CKO_CONTINUOUS      ( ( unsigned int ) 0x1 << 2 )   /* (SSC) Continuous Receive/Transmit Clock RK pin: Output */
+#define     AT91C_SSC_CKO_DATA_TX         ( ( unsigned int ) 0x2 << 2 )   /* (SSC) Receive/Transmit Clock only during data transfers RK pin: Output */
+#define AT91C_SSC_CKI                     ( ( unsigned int ) 0x1 << 5 )   /* (SSC) Receive/Transmit Clock Inversion */
+#define AT91C_SSC_START                   ( ( unsigned int ) 0xF << 8 )   /* (SSC) Receive/Transmit Start Selection */
+#define     AT91C_SSC_START_CONTINUOUS    ( ( unsigned int ) 0x0 << 8 )   /* (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */
+#define     AT91C_SSC_START_TX            ( ( unsigned int ) 0x1 << 8 )   /* (SSC) Transmit/Receive start */
+#define     AT91C_SSC_START_LOW_RF        ( ( unsigned int ) 0x2 << 8 )   /* (SSC) Detection of a low level on RF input */
+#define     AT91C_SSC_START_HIGH_RF       ( ( unsigned int ) 0x3 << 8 )   /* (SSC) Detection of a high level on RF input */
+#define     AT91C_SSC_START_FALL_RF       ( ( unsigned int ) 0x4 << 8 )   /* (SSC) Detection of a falling edge on RF input */
+#define     AT91C_SSC_START_RISE_RF       ( ( unsigned int ) 0x5 << 8 )   /* (SSC) Detection of a rising edge on RF input */
+#define     AT91C_SSC_START_LEVEL_RF      ( ( unsigned int ) 0x6 << 8 )   /* (SSC) Detection of any level change on RF input */
+#define     AT91C_SSC_START_EDGE_RF       ( ( unsigned int ) 0x7 << 8 )   /* (SSC) Detection of any edge on RF input */
+#define     AT91C_SSC_START_0             ( ( unsigned int ) 0x8 << 8 )   /* (SSC) Compare 0 */
+#define AT91C_SSC_STTDLY                  ( ( unsigned int ) 0xFF << 16 ) /* (SSC) Receive/Transmit Start Delay */
+#define AT91C_SSC_PERIOD                  ( ( unsigned int ) 0xFF << 24 ) /* (SSC) Receive/Transmit Period Divider Selection */
+/* -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- */
+#define AT91C_SSC_DATLEN                  ( ( unsigned int ) 0x1F << 0 )  /* (SSC) Data Length */
+#define AT91C_SSC_LOOP                    ( ( unsigned int ) 0x1 << 5 )   /* (SSC) Loop Mode */
+#define AT91C_SSC_MSBF                    ( ( unsigned int ) 0x1 << 7 )   /* (SSC) Most Significant Bit First */
+#define AT91C_SSC_DATNB                   ( ( unsigned int ) 0xF << 8 )   /* (SSC) Data Number per Frame */
+#define AT91C_SSC_FSLEN                   ( ( unsigned int ) 0xF << 16 )  /* (SSC) Receive/Transmit Frame Sync length */
+#define AT91C_SSC_FSOS                    ( ( unsigned int ) 0x7 << 20 )  /* (SSC) Receive/Transmit Frame Sync Output Selection */
+#define     AT91C_SSC_FSOS_NONE           ( ( unsigned int ) 0x0 << 20 )  /* (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only */
+#define     AT91C_SSC_FSOS_NEGATIVE       ( ( unsigned int ) 0x1 << 20 )  /* (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse */
+#define     AT91C_SSC_FSOS_POSITIVE       ( ( unsigned int ) 0x2 << 20 )  /* (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse */
+#define     AT91C_SSC_FSOS_LOW            ( ( unsigned int ) 0x3 << 20 )  /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer */
+#define     AT91C_SSC_FSOS_HIGH           ( ( unsigned int ) 0x4 << 20 )  /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer */
+#define     AT91C_SSC_FSOS_TOGGLE         ( ( unsigned int ) 0x5 << 20 )  /* (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer */
+#define AT91C_SSC_FSEDGE                  ( ( unsigned int ) 0x1 << 24 )  /* (SSC) Frame Sync Edge Detection */
+/* -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- */
+/* -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- */
+#define AT91C_SSC_DATDEF                  ( ( unsigned int ) 0x1 << 5 )  /* (SSC) Data Default Value */
+#define AT91C_SSC_FSDEN                   ( ( unsigned int ) 0x1 << 23 ) /* (SSC) Frame Sync Data Enable */
+/* -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- */
+#define AT91C_SSC_TXRDY                   ( ( unsigned int ) 0x1 << 0 )  /* (SSC) Transmit Ready */
+#define AT91C_SSC_TXEMPTY                 ( ( unsigned int ) 0x1 << 1 )  /* (SSC) Transmit Empty */
+#define AT91C_SSC_ENDTX                   ( ( unsigned int ) 0x1 << 2 )  /* (SSC) End Of Transmission */
+#define AT91C_SSC_TXBUFE                  ( ( unsigned int ) 0x1 << 3 )  /* (SSC) Transmit Buffer Empty */
+#define AT91C_SSC_RXRDY                   ( ( unsigned int ) 0x1 << 4 )  /* (SSC) Receive Ready */
+#define AT91C_SSC_OVRUN                   ( ( unsigned int ) 0x1 << 5 )  /* (SSC) Receive Overrun */
+#define AT91C_SSC_ENDRX                   ( ( unsigned int ) 0x1 << 6 )  /* (SSC) End of Reception */
+#define AT91C_SSC_RXBUFF                  ( ( unsigned int ) 0x1 << 7 )  /* (SSC) Receive Buffer Full */
+#define AT91C_SSC_TXSYN                   ( ( unsigned int ) 0x1 << 10 ) /* (SSC) Transmit Sync */
+#define AT91C_SSC_RXSYN                   ( ( unsigned int ) 0x1 << 11 ) /* (SSC) Receive Sync */
+#define AT91C_SSC_TXENA                   ( ( unsigned int ) 0x1 << 16 ) /* (SSC) Transmit Enable */
+#define AT91C_SSC_RXENA                   ( ( unsigned int ) 0x1 << 17 ) /* (SSC) Receive Enable */
+/* -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- */
+/* -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- */
+/* -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Two-wire Interface
-// *****************************************************************************
-typedef struct _AT91S_TWI {
-    AT91_REG     TWI_CR;    // Control Register
-    AT91_REG     TWI_MMR;   // Master Mode Register
-    AT91_REG     Reserved0[1];  //
-    AT91_REG     TWI_IADR;  // Internal Address Register
-    AT91_REG     TWI_CWGR;  // Clock Waveform Generator Register
-    AT91_REG     Reserved1[3];  //
-    AT91_REG     TWI_SR;    // Status Register
-    AT91_REG     TWI_IER;   // Interrupt Enable Register
-    AT91_REG     TWI_IDR;   // Interrupt Disable Register
-    AT91_REG     TWI_IMR;   // Interrupt Mask Register
-    AT91_REG     TWI_RHR;   // Receive Holding Register
-    AT91_REG     TWI_THR;   // Transmit Holding Register
-} AT91S_TWI, *AT91PS_TWI;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Two-wire Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_TWI
+{
+    AT91_REG TWI_CR;         /* Control Register */
+    AT91_REG TWI_MMR;        /* Master Mode Register */
+    AT91_REG Reserved0[ 1 ]; /* */
+    AT91_REG TWI_IADR;       /* Internal Address Register */
+    AT91_REG TWI_CWGR;       /* Clock Waveform Generator Register */
+    AT91_REG Reserved1[ 3 ]; /* */
+    AT91_REG TWI_SR;         /* Status Register */
+    AT91_REG TWI_IER;        /* Interrupt Enable Register */
+    AT91_REG TWI_IDR;        /* Interrupt Disable Register */
+    AT91_REG TWI_IMR;        /* Interrupt Mask Register */
+    AT91_REG TWI_RHR;        /* Receive Holding Register */
+    AT91_REG TWI_THR;        /* Transmit Holding Register */
+} AT91S_TWI, * AT91PS_TWI;
 
-// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
-#define AT91C_TWI_START       ((unsigned int) 0x1 <<  0) // (TWI) Send a START Condition
-#define AT91C_TWI_STOP        ((unsigned int) 0x1 <<  1) // (TWI) Send a STOP Condition
-#define AT91C_TWI_MSEN        ((unsigned int) 0x1 <<  2) // (TWI) TWI Master Transfer Enabled
-#define AT91C_TWI_MSDIS       ((unsigned int) 0x1 <<  3) // (TWI) TWI Master Transfer Disabled
-#define AT91C_TWI_SWRST       ((unsigned int) 0x1 <<  7) // (TWI) Software Reset
-// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
-#define AT91C_TWI_IADRSZ      ((unsigned int) 0x3 <<  8) // (TWI) Internal Device Address Size
-#define     AT91C_TWI_IADRSZ_NO                   ((unsigned int) 0x0 <<  8) // (TWI) No internal device address
-#define     AT91C_TWI_IADRSZ_1_BYTE               ((unsigned int) 0x1 <<  8) // (TWI) One-byte internal device address
-#define     AT91C_TWI_IADRSZ_2_BYTE               ((unsigned int) 0x2 <<  8) // (TWI) Two-byte internal device address
-#define     AT91C_TWI_IADRSZ_3_BYTE               ((unsigned int) 0x3 <<  8) // (TWI) Three-byte internal device address
-#define AT91C_TWI_MREAD       ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction
-#define AT91C_TWI_DADR        ((unsigned int) 0x7F << 16) // (TWI) Device Address
-// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
-#define AT91C_TWI_CLDIV       ((unsigned int) 0xFF <<  0) // (TWI) Clock Low Divider
-#define AT91C_TWI_CHDIV       ((unsigned int) 0xFF <<  8) // (TWI) Clock High Divider
-#define AT91C_TWI_CKDIV       ((unsigned int) 0x7 << 16) // (TWI) Clock Divider
-// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
-#define AT91C_TWI_TXCOMP      ((unsigned int) 0x1 <<  0) // (TWI) Transmission Completed
-#define AT91C_TWI_RXRDY       ((unsigned int) 0x1 <<  1) // (TWI) Receive holding register ReaDY
-#define AT91C_TWI_TXRDY       ((unsigned int) 0x1 <<  2) // (TWI) Transmit holding register ReaDY
-#define AT91C_TWI_OVRE        ((unsigned int) 0x1 <<  6) // (TWI) Overrun Error
-#define AT91C_TWI_UNRE        ((unsigned int) 0x1 <<  7) // (TWI) Underrun Error
-#define AT91C_TWI_NACK        ((unsigned int) 0x1 <<  8) // (TWI) Not Acknowledged
-// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
-// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
-// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
+/* -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- */
+#define AT91C_TWI_START                ( ( unsigned int ) 0x1 << 0 )   /* (TWI) Send a START Condition */
+#define AT91C_TWI_STOP                 ( ( unsigned int ) 0x1 << 1 )   /* (TWI) Send a STOP Condition */
+#define AT91C_TWI_MSEN                 ( ( unsigned int ) 0x1 << 2 )   /* (TWI) TWI Master Transfer Enabled */
+#define AT91C_TWI_MSDIS                ( ( unsigned int ) 0x1 << 3 )   /* (TWI) TWI Master Transfer Disabled */
+#define AT91C_TWI_SWRST                ( ( unsigned int ) 0x1 << 7 )   /* (TWI) Software Reset */
+/* -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- */
+#define AT91C_TWI_IADRSZ               ( ( unsigned int ) 0x3 << 8 )   /* (TWI) Internal Device Address Size */
+#define     AT91C_TWI_IADRSZ_NO        ( ( unsigned int ) 0x0 << 8 )   /* (TWI) No internal device address */
+#define     AT91C_TWI_IADRSZ_1_BYTE    ( ( unsigned int ) 0x1 << 8 )   /* (TWI) One-byte internal device address */
+#define     AT91C_TWI_IADRSZ_2_BYTE    ( ( unsigned int ) 0x2 << 8 )   /* (TWI) Two-byte internal device address */
+#define     AT91C_TWI_IADRSZ_3_BYTE    ( ( unsigned int ) 0x3 << 8 )   /* (TWI) Three-byte internal device address */
+#define AT91C_TWI_MREAD                ( ( unsigned int ) 0x1 << 12 )  /* (TWI) Master Read Direction */
+#define AT91C_TWI_DADR                 ( ( unsigned int ) 0x7F << 16 ) /* (TWI) Device Address */
+/* -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- */
+#define AT91C_TWI_CLDIV                ( ( unsigned int ) 0xFF << 0 )  /* (TWI) Clock Low Divider */
+#define AT91C_TWI_CHDIV                ( ( unsigned int ) 0xFF << 8 )  /* (TWI) Clock High Divider */
+#define AT91C_TWI_CKDIV                ( ( unsigned int ) 0x7 << 16 )  /* (TWI) Clock Divider */
+/* -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- */
+#define AT91C_TWI_TXCOMP               ( ( unsigned int ) 0x1 << 0 )   /* (TWI) Transmission Completed */
+#define AT91C_TWI_RXRDY                ( ( unsigned int ) 0x1 << 1 )   /* (TWI) Receive holding register ReaDY */
+#define AT91C_TWI_TXRDY                ( ( unsigned int ) 0x1 << 2 )   /* (TWI) Transmit holding register ReaDY */
+#define AT91C_TWI_OVRE                 ( ( unsigned int ) 0x1 << 6 )   /* (TWI) Overrun Error */
+#define AT91C_TWI_UNRE                 ( ( unsigned int ) 0x1 << 7 )   /* (TWI) Underrun Error */
+#define AT91C_TWI_NACK                 ( ( unsigned int ) 0x1 << 8 )   /* (TWI) Not Acknowledged */
+/* -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- */
+/* -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- */
+/* -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR PWMC Channel Interface
-// *****************************************************************************
-typedef struct _AT91S_PWMC_CH {
-    AT91_REG     PWMC_CMR;  // Channel Mode Register
-    AT91_REG     PWMC_CDTYR;    // Channel Duty Cycle Register
-    AT91_REG     PWMC_CPRDR;    // Channel Period Register
-    AT91_REG     PWMC_CCNTR;    // Channel Counter Register
-    AT91_REG     PWMC_CUPDR;    // Channel Update Register
-    AT91_REG     PWMC_Reserved[3];  // Reserved
-} AT91S_PWMC_CH, *AT91PS_PWMC_CH;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR PWMC Channel Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_PWMC_CH
+{
+    AT91_REG PWMC_CMR;           /* Channel Mode Register */
+    AT91_REG PWMC_CDTYR;         /* Channel Duty Cycle Register */
+    AT91_REG PWMC_CPRDR;         /* Channel Period Register */
+    AT91_REG PWMC_CCNTR;         /* Channel Counter Register */
+    AT91_REG PWMC_CUPDR;         /* Channel Update Register */
+    AT91_REG PWMC_Reserved[ 3 ]; /* Reserved */
+} AT91S_PWMC_CH, * AT91PS_PWMC_CH;
 
-// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
-#define AT91C_PWMC_CPRE       ((unsigned int) 0xF <<  0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
-#define     AT91C_PWMC_CPRE_MCK                  ((unsigned int) 0x0) // (PWMC_CH)
-#define     AT91C_PWMC_CPRE_MCKA                 ((unsigned int) 0xB) // (PWMC_CH)
-#define     AT91C_PWMC_CPRE_MCKB                 ((unsigned int) 0xC) // (PWMC_CH)
-#define AT91C_PWMC_CALG       ((unsigned int) 0x1 <<  8) // (PWMC_CH) Channel Alignment
-#define AT91C_PWMC_CPOL       ((unsigned int) 0x1 <<  9) // (PWMC_CH) Channel Polarity
-#define AT91C_PWMC_CPD        ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period
-// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
-#define AT91C_PWMC_CDTY       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Duty Cycle
-// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
-#define AT91C_PWMC_CPRD       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Period
-// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
-#define AT91C_PWMC_CCNT       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Counter
-// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
-#define AT91C_PWMC_CUPD       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Update
+/* -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- */
+#define AT91C_PWMC_CPRE             ( ( unsigned int ) 0xF << 0 )  /* (PWMC_CH) Channel Pre-scaler : PWMC_CLKx */
+#define     AT91C_PWMC_CPRE_MCK     ( ( unsigned int ) 0x0 )       /* (PWMC_CH) */
+#define     AT91C_PWMC_CPRE_MCKA    ( ( unsigned int ) 0xB )       /* (PWMC_CH) */
+#define     AT91C_PWMC_CPRE_MCKB    ( ( unsigned int ) 0xC )       /* (PWMC_CH) */
+#define AT91C_PWMC_CALG             ( ( unsigned int ) 0x1 << 8 )  /* (PWMC_CH) Channel Alignment */
+#define AT91C_PWMC_CPOL             ( ( unsigned int ) 0x1 << 9 )  /* (PWMC_CH) Channel Polarity */
+#define AT91C_PWMC_CPD              ( ( unsigned int ) 0x1 << 10 ) /* (PWMC_CH) Channel Update Period */
+/* -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- */
+#define AT91C_PWMC_CDTY             ( ( unsigned int ) 0x0 << 0 )  /* (PWMC_CH) Channel Duty Cycle */
+/* -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- */
+#define AT91C_PWMC_CPRD             ( ( unsigned int ) 0x0 << 0 )  /* (PWMC_CH) Channel Period */
+/* -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- */
+#define AT91C_PWMC_CCNT             ( ( unsigned int ) 0x0 << 0 )  /* (PWMC_CH) Channel Counter */
+/* -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- */
+#define AT91C_PWMC_CUPD             ( ( unsigned int ) 0x0 << 0 )  /* (PWMC_CH) Channel Update */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_PWMC {
-    AT91_REG     PWMC_MR;   // PWMC Mode Register
-    AT91_REG     PWMC_ENA;  // PWMC Enable Register
-    AT91_REG     PWMC_DIS;  // PWMC Disable Register
-    AT91_REG     PWMC_SR;   // PWMC Status Register
-    AT91_REG     PWMC_IER;  // PWMC Interrupt Enable Register
-    AT91_REG     PWMC_IDR;  // PWMC Interrupt Disable Register
-    AT91_REG     PWMC_IMR;  // PWMC Interrupt Mask Register
-    AT91_REG     PWMC_ISR;  // PWMC Interrupt Status Register
-    AT91_REG     Reserved0[55];     //
-    AT91_REG     PWMC_VR;   // PWMC Version Register
-    AT91_REG     Reserved1[64];     //
-    AT91S_PWMC_CH    PWMC_CH[4];    // PWMC Channel
-} AT91S_PWMC, *AT91PS_PWMC;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_PWMC
+{
+    AT91_REG PWMC_MR;           /* PWMC Mode Register */
+    AT91_REG PWMC_ENA;          /* PWMC Enable Register */
+    AT91_REG PWMC_DIS;          /* PWMC Disable Register */
+    AT91_REG PWMC_SR;           /* PWMC Status Register */
+    AT91_REG PWMC_IER;          /* PWMC Interrupt Enable Register */
+    AT91_REG PWMC_IDR;          /* PWMC Interrupt Disable Register */
+    AT91_REG PWMC_IMR;          /* PWMC Interrupt Mask Register */
+    AT91_REG PWMC_ISR;          /* PWMC Interrupt Status Register */
+    AT91_REG Reserved0[ 55 ];   /* */
+    AT91_REG PWMC_VR;           /* PWMC Version Register */
+    AT91_REG Reserved1[ 64 ];   /* */
+    AT91S_PWMC_CH PWMC_CH[ 4 ]; /* PWMC Channel */
+} AT91S_PWMC, * AT91PS_PWMC;
 
-// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
-#define AT91C_PWMC_DIVA       ((unsigned int) 0xFF <<  0) // (PWMC) CLKA divide factor.
-#define AT91C_PWMC_PREA       ((unsigned int) 0xF <<  8) // (PWMC) Divider Input Clock Prescaler A
-#define     AT91C_PWMC_PREA_MCK                  ((unsigned int) 0x0 <<  8) // (PWMC)
-#define AT91C_PWMC_DIVB       ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor.
-#define AT91C_PWMC_PREB       ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B
-#define     AT91C_PWMC_PREB_MCK                  ((unsigned int) 0x0 << 24) // (PWMC)
-// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
-#define AT91C_PWMC_CHID0      ((unsigned int) 0x1 <<  0) // (PWMC) Channel ID 0
-#define AT91C_PWMC_CHID1      ((unsigned int) 0x1 <<  1) // (PWMC) Channel ID 1
-#define AT91C_PWMC_CHID2      ((unsigned int) 0x1 <<  2) // (PWMC) Channel ID 2
-#define AT91C_PWMC_CHID3      ((unsigned int) 0x1 <<  3) // (PWMC) Channel ID 3
-// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
-// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
-// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
-// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
-// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
-// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
+/* -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- */
+#define AT91C_PWMC_DIVA            ( ( unsigned int ) 0xFF << 0 )  /* (PWMC) CLKA divide factor. */
+#define AT91C_PWMC_PREA            ( ( unsigned int ) 0xF << 8 )   /* (PWMC) Divider Input Clock Prescaler A */
+#define     AT91C_PWMC_PREA_MCK    ( ( unsigned int ) 0x0 << 8 )   /* (PWMC) */
+#define AT91C_PWMC_DIVB            ( ( unsigned int ) 0xFF << 16 ) /* (PWMC) CLKB divide factor. */
+#define AT91C_PWMC_PREB            ( ( unsigned int ) 0xF << 24 )  /* (PWMC) Divider Input Clock Prescaler B */
+#define     AT91C_PWMC_PREB_MCK    ( ( unsigned int ) 0x0 << 24 )  /* (PWMC) */
+/* -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- */
+#define AT91C_PWMC_CHID0           ( ( unsigned int ) 0x1 << 0 )   /* (PWMC) Channel ID 0 */
+#define AT91C_PWMC_CHID1           ( ( unsigned int ) 0x1 << 1 )   /* (PWMC) Channel ID 1 */
+#define AT91C_PWMC_CHID2           ( ( unsigned int ) 0x1 << 2 )   /* (PWMC) Channel ID 2 */
+#define AT91C_PWMC_CHID3           ( ( unsigned int ) 0x1 << 3 )   /* (PWMC) Channel ID 3 */
+/* -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- */
+/* -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- */
+/* -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- */
+/* -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- */
+/* -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- */
+/* -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR USB Device Interface
-// *****************************************************************************
-typedef struct _AT91S_UDP {
-    AT91_REG     UDP_NUM;   // Frame Number Register
-    AT91_REG     UDP_GLBSTATE;  // Global State Register
-    AT91_REG     UDP_FADDR;     // Function Address Register
-    AT91_REG     Reserved0[1];  //
-    AT91_REG     UDP_IER;   // Interrupt Enable Register
-    AT91_REG     UDP_IDR;   // Interrupt Disable Register
-    AT91_REG     UDP_IMR;   // Interrupt Mask Register
-    AT91_REG     UDP_ISR;   // Interrupt Status Register
-    AT91_REG     UDP_ICR;   // Interrupt Clear Register
-    AT91_REG     Reserved1[1];  //
-    AT91_REG     UDP_RSTEP;     // Reset Endpoint Register
-    AT91_REG     Reserved2[1];  //
-    AT91_REG     UDP_CSR[6];    // Endpoint Control and Status Register
-    AT91_REG     Reserved3[2];  //
-    AT91_REG     UDP_FDR[6];    // Endpoint FIFO Data Register
-    AT91_REG     Reserved4[3];  //
-    AT91_REG     UDP_TXVC;  // Transceiver Control Register
-} AT91S_UDP, *AT91PS_UDP;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR USB Device Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_UDP
+{
+    AT91_REG UDP_NUM;        /* Frame Number Register */
+    AT91_REG UDP_GLBSTATE;   /* Global State Register */
+    AT91_REG UDP_FADDR;      /* Function Address Register */
+    AT91_REG Reserved0[ 1 ]; /* */
+    AT91_REG UDP_IER;        /* Interrupt Enable Register */
+    AT91_REG UDP_IDR;        /* Interrupt Disable Register */
+    AT91_REG UDP_IMR;        /* Interrupt Mask Register */
+    AT91_REG UDP_ISR;        /* Interrupt Status Register */
+    AT91_REG UDP_ICR;        /* Interrupt Clear Register */
+    AT91_REG Reserved1[ 1 ]; /* */
+    AT91_REG UDP_RSTEP;      /* Reset Endpoint Register */
+    AT91_REG Reserved2[ 1 ]; /* */
+    AT91_REG UDP_CSR[ 6 ];   /* Endpoint Control and Status Register */
+    AT91_REG Reserved3[ 2 ]; /* */
+    AT91_REG UDP_FDR[ 6 ];   /* Endpoint FIFO Data Register */
+    AT91_REG Reserved4[ 3 ]; /* */
+    AT91_REG UDP_TXVC;       /* Transceiver Control Register */
+} AT91S_UDP, * AT91PS_UDP;
 
-// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
-#define AT91C_UDP_FRM_NUM     ((unsigned int) 0x7FF <<  0) // (UDP) Frame Number as Defined in the Packet Field Formats
-#define AT91C_UDP_FRM_ERR     ((unsigned int) 0x1 << 16) // (UDP) Frame Error
-#define AT91C_UDP_FRM_OK      ((unsigned int) 0x1 << 17) // (UDP) Frame OK
-// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
-#define AT91C_UDP_FADDEN      ((unsigned int) 0x1 <<  0) // (UDP) Function Address Enable
-#define AT91C_UDP_CONFG       ((unsigned int) 0x1 <<  1) // (UDP) Configured
-#define AT91C_UDP_ESR         ((unsigned int) 0x1 <<  2) // (UDP) Enable Send Resume
-#define AT91C_UDP_RSMINPR     ((unsigned int) 0x1 <<  3) // (UDP) A Resume Has Been Sent to the Host
-#define AT91C_UDP_RMWUPE      ((unsigned int) 0x1 <<  4) // (UDP) Remote Wake Up Enable
-// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
-#define AT91C_UDP_FADD        ((unsigned int) 0xFF <<  0) // (UDP) Function Address Value
-#define AT91C_UDP_FEN         ((unsigned int) 0x1 <<  8) // (UDP) Function Enable
-// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
-#define AT91C_UDP_EPINT0      ((unsigned int) 0x1 <<  0) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT1      ((unsigned int) 0x1 <<  1) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT2      ((unsigned int) 0x1 <<  2) // (UDP) Endpoint 2 Interrupt
-#define AT91C_UDP_EPINT3      ((unsigned int) 0x1 <<  3) // (UDP) Endpoint 3 Interrupt
-#define AT91C_UDP_EPINT4      ((unsigned int) 0x1 <<  4) // (UDP) Endpoint 4 Interrupt
-#define AT91C_UDP_EPINT5      ((unsigned int) 0x1 <<  5) // (UDP) Endpoint 5 Interrupt
-#define AT91C_UDP_RXSUSP      ((unsigned int) 0x1 <<  8) // (UDP) USB Suspend Interrupt
-#define AT91C_UDP_RXRSM       ((unsigned int) 0x1 <<  9) // (UDP) USB Resume Interrupt
-#define AT91C_UDP_EXTRSM      ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt
-#define AT91C_UDP_SOFINT      ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt
-#define AT91C_UDP_WAKEUP      ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt
-// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
-// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
-// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
-#define AT91C_UDP_ENDBUSRES   ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
-// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
-// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
-#define AT91C_UDP_EP0         ((unsigned int) 0x1 <<  0) // (UDP) Reset Endpoint 0
-#define AT91C_UDP_EP1         ((unsigned int) 0x1 <<  1) // (UDP) Reset Endpoint 1
-#define AT91C_UDP_EP2         ((unsigned int) 0x1 <<  2) // (UDP) Reset Endpoint 2
-#define AT91C_UDP_EP3         ((unsigned int) 0x1 <<  3) // (UDP) Reset Endpoint 3
-#define AT91C_UDP_EP4         ((unsigned int) 0x1 <<  4) // (UDP) Reset Endpoint 4
-#define AT91C_UDP_EP5         ((unsigned int) 0x1 <<  5) // (UDP) Reset Endpoint 5
-// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
-#define AT91C_UDP_TXCOMP      ((unsigned int) 0x1 <<  0) // (UDP) Generates an IN packet with data previously written in the DPR
-#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 <<  1) // (UDP) Receive Data Bank 0
-#define AT91C_UDP_RXSETUP     ((unsigned int) 0x1 <<  2) // (UDP) Sends STALL to the Host (Control endpoints)
-#define AT91C_UDP_ISOERROR    ((unsigned int) 0x1 <<  3) // (UDP) Isochronous error (Isochronous endpoints)
-#define AT91C_UDP_TXPKTRDY    ((unsigned int) 0x1 <<  4) // (UDP) Transmit Packet Ready
-#define AT91C_UDP_FORCESTALL  ((unsigned int) 0x1 <<  5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
-#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 <<  6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
-#define AT91C_UDP_DIR         ((unsigned int) 0x1 <<  7) // (UDP) Transfer Direction
-#define AT91C_UDP_EPTYPE      ((unsigned int) 0x7 <<  8) // (UDP) Endpoint type
-#define     AT91C_UDP_EPTYPE_CTRL                 ((unsigned int) 0x0 <<  8) // (UDP) Control
-#define     AT91C_UDP_EPTYPE_ISO_OUT              ((unsigned int) 0x1 <<  8) // (UDP) Isochronous OUT
-#define     AT91C_UDP_EPTYPE_BULK_OUT             ((unsigned int) 0x2 <<  8) // (UDP) Bulk OUT
-#define     AT91C_UDP_EPTYPE_INT_OUT              ((unsigned int) 0x3 <<  8) // (UDP) Interrupt OUT
-#define     AT91C_UDP_EPTYPE_ISO_IN               ((unsigned int) 0x5 <<  8) // (UDP) Isochronous IN
-#define     AT91C_UDP_EPTYPE_BULK_IN              ((unsigned int) 0x6 <<  8) // (UDP) Bulk IN
-#define     AT91C_UDP_EPTYPE_INT_IN               ((unsigned int) 0x7 <<  8) // (UDP) Interrupt IN
-#define AT91C_UDP_DTGLE       ((unsigned int) 0x1 << 11) // (UDP) Data Toggle
-#define AT91C_UDP_EPEDS       ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable
-#define AT91C_UDP_RXBYTECNT   ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
-// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------
-#define AT91C_UDP_TXVDIS      ((unsigned int) 0x1 <<  8) // (UDP)
-#define AT91C_UDP_PUON        ((unsigned int) 0x1 <<  9) // (UDP) Pull-up ON
+/* -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- */
+#define AT91C_UDP_FRM_NUM    ( ( unsigned int ) 0x7FF << 0 ) /* (UDP) Frame Number as Defined in the Packet Field Formats */
+#define AT91C_UDP_FRM_ERR    ( ( unsigned int ) 0x1 << 16 )  /* (UDP) Frame Error */
+#define AT91C_UDP_FRM_OK     ( ( unsigned int ) 0x1 << 17 )  /* (UDP) Frame OK */
+/* -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- */
+#define AT91C_UDP_FADDEN     ( ( unsigned int ) 0x1 << 0 )   /* (UDP) Function Address Enable */
+#define AT91C_UDP_CONFG      ( ( unsigned int ) 0x1 << 1 )   /* (UDP) Configured */
+#define AT91C_UDP_ESR        ( ( unsigned int ) 0x1 << 2 )   /* (UDP) Enable Send Resume */
+#define AT91C_UDP_RSMINPR    ( ( unsigned int ) 0x1 << 3 )   /* (UDP) A Resume Has Been Sent to the Host */
+#define AT91C_UDP_RMWUPE     ( ( unsigned int ) 0x1 << 4 )   /* (UDP) Remote Wake Up Enable */
+/* -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- */
+#define AT91C_UDP_FADD       ( ( unsigned int ) 0xFF << 0 )  /* (UDP) Function Address Value */
+#define AT91C_UDP_FEN        ( ( unsigned int ) 0x1 << 8 )   /* (UDP) Function Enable */
+/* -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- */
+#define AT91C_UDP_EPINT0     ( ( unsigned int ) 0x1 << 0 )   /* (UDP) Endpoint 0 Interrupt */
+#define AT91C_UDP_EPINT1     ( ( unsigned int ) 0x1 << 1 )   /* (UDP) Endpoint 0 Interrupt */
+#define AT91C_UDP_EPINT2     ( ( unsigned int ) 0x1 << 2 )   /* (UDP) Endpoint 2 Interrupt */
+#define AT91C_UDP_EPINT3     ( ( unsigned int ) 0x1 << 3 )   /* (UDP) Endpoint 3 Interrupt */
+#define AT91C_UDP_EPINT4     ( ( unsigned int ) 0x1 << 4 )   /* (UDP) Endpoint 4 Interrupt */
+#define AT91C_UDP_EPINT5     ( ( unsigned int ) 0x1 << 5 )   /* (UDP) Endpoint 5 Interrupt */
+#define AT91C_UDP_RXSUSP     ( ( unsigned int ) 0x1 << 8 )   /* (UDP) USB Suspend Interrupt */
+#define AT91C_UDP_RXRSM      ( ( unsigned int ) 0x1 << 9 )   /* (UDP) USB Resume Interrupt */
+#define AT91C_UDP_EXTRSM     ( ( unsigned int ) 0x1 << 10 )  /* (UDP) USB External Resume Interrupt */
+#define AT91C_UDP_SOFINT     ( ( unsigned int ) 0x1 << 11 )  /* (UDP) USB Start Of frame Interrupt */
+#define AT91C_UDP_WAKEUP     ( ( unsigned int ) 0x1 << 13 )  /* (UDP) USB Resume Interrupt */
+/* -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- */
+/* -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- */
+/* -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- */
+#define AT91C_UDP_ENDBUSRES              ( ( unsigned int ) 0x1 << 12 ) /* (UDP) USB End Of Bus Reset Interrupt */
+/* -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- */
+/* -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- */
+#define AT91C_UDP_EP0                    ( ( unsigned int ) 0x1 << 0 )    /* (UDP) Reset Endpoint 0 */
+#define AT91C_UDP_EP1                    ( ( unsigned int ) 0x1 << 1 )    /* (UDP) Reset Endpoint 1 */
+#define AT91C_UDP_EP2                    ( ( unsigned int ) 0x1 << 2 )    /* (UDP) Reset Endpoint 2 */
+#define AT91C_UDP_EP3                    ( ( unsigned int ) 0x1 << 3 )    /* (UDP) Reset Endpoint 3 */
+#define AT91C_UDP_EP4                    ( ( unsigned int ) 0x1 << 4 )    /* (UDP) Reset Endpoint 4 */
+#define AT91C_UDP_EP5                    ( ( unsigned int ) 0x1 << 5 )    /* (UDP) Reset Endpoint 5 */
+/* -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- */
+#define AT91C_UDP_TXCOMP                 ( ( unsigned int ) 0x1 << 0 )    /* (UDP) Generates an IN packet with data previously written in the DPR */
+#define AT91C_UDP_RX_DATA_BK0            ( ( unsigned int ) 0x1 << 1 )    /* (UDP) Receive Data Bank 0 */
+#define AT91C_UDP_RXSETUP                ( ( unsigned int ) 0x1 << 2 )    /* (UDP) Sends STALL to the Host (Control endpoints) */
+#define AT91C_UDP_ISOERROR               ( ( unsigned int ) 0x1 << 3 )    /* (UDP) Isochronous error (Isochronous endpoints) */
+#define AT91C_UDP_TXPKTRDY               ( ( unsigned int ) 0x1 << 4 )    /* (UDP) Transmit Packet Ready */
+#define AT91C_UDP_FORCESTALL             ( ( unsigned int ) 0x1 << 5 )    /* (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). */
+#define AT91C_UDP_RX_DATA_BK1            ( ( unsigned int ) 0x1 << 6 )    /* (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). */
+#define AT91C_UDP_DIR                    ( ( unsigned int ) 0x1 << 7 )    /* (UDP) Transfer Direction */
+#define AT91C_UDP_EPTYPE                 ( ( unsigned int ) 0x7 << 8 )    /* (UDP) Endpoint type */
+#define     AT91C_UDP_EPTYPE_CTRL        ( ( unsigned int ) 0x0 << 8 )    /* (UDP) Control */
+#define     AT91C_UDP_EPTYPE_ISO_OUT     ( ( unsigned int ) 0x1 << 8 )    /* (UDP) Isochronous OUT */
+#define     AT91C_UDP_EPTYPE_BULK_OUT    ( ( unsigned int ) 0x2 << 8 )    /* (UDP) Bulk OUT */
+#define     AT91C_UDP_EPTYPE_INT_OUT     ( ( unsigned int ) 0x3 << 8 )    /* (UDP) Interrupt OUT */
+#define     AT91C_UDP_EPTYPE_ISO_IN      ( ( unsigned int ) 0x5 << 8 )    /* (UDP) Isochronous IN */
+#define     AT91C_UDP_EPTYPE_BULK_IN     ( ( unsigned int ) 0x6 << 8 )    /* (UDP) Bulk IN */
+#define     AT91C_UDP_EPTYPE_INT_IN      ( ( unsigned int ) 0x7 << 8 )    /* (UDP) Interrupt IN */
+#define AT91C_UDP_DTGLE                  ( ( unsigned int ) 0x1 << 11 )   /* (UDP) Data Toggle */
+#define AT91C_UDP_EPEDS                  ( ( unsigned int ) 0x1 << 15 )   /* (UDP) Endpoint Enable Disable */
+#define AT91C_UDP_RXBYTECNT              ( ( unsigned int ) 0x7FF << 16 ) /* (UDP) Number Of Bytes Available in the FIFO */
+/* -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- */
+#define AT91C_UDP_TXVDIS                 ( ( unsigned int ) 0x1 << 8 )    /* (UDP) */
+#define AT91C_UDP_PUON                   ( ( unsigned int ) 0x1 << 9 )    /* (UDP) Pull-up ON */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
-// *****************************************************************************
-typedef struct _AT91S_TC {
-    AT91_REG     TC_CCR;    // Channel Control Register
-    AT91_REG     TC_CMR;    // Channel Mode Register (Capture Mode / Waveform Mode)
-    AT91_REG     Reserved0[2];  //
-    AT91_REG     TC_CV;     // Counter Value
-    AT91_REG     TC_RA;     // Register A
-    AT91_REG     TC_RB;     // Register B
-    AT91_REG     TC_RC;     // Register C
-    AT91_REG     TC_SR;     // Status Register
-    AT91_REG     TC_IER;    // Interrupt Enable Register
-    AT91_REG     TC_IDR;    // Interrupt Disable Register
-    AT91_REG     TC_IMR;    // Interrupt Mask Register
-} AT91S_TC, *AT91PS_TC;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_TC
+{
+    AT91_REG TC_CCR;         /* Channel Control Register */
+    AT91_REG TC_CMR;         /* Channel Mode Register (Capture Mode / Waveform Mode) */
+    AT91_REG Reserved0[ 2 ]; /* */
+    AT91_REG TC_CV;          /* Counter Value */
+    AT91_REG TC_RA;          /* Register A */
+    AT91_REG TC_RB;          /* Register B */
+    AT91_REG TC_RC;          /* Register C */
+    AT91_REG TC_SR;          /* Status Register */
+    AT91_REG TC_IER;         /* Interrupt Enable Register */
+    AT91_REG TC_IDR;         /* Interrupt Disable Register */
+    AT91_REG TC_IMR;         /* Interrupt Mask Register */
+} AT91S_TC, * AT91PS_TC;
 
-// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
-#define AT91C_TC_CLKEN        ((unsigned int) 0x1 <<  0) // (TC) Counter Clock Enable Command
-#define AT91C_TC_CLKDIS       ((unsigned int) 0x1 <<  1) // (TC) Counter Clock Disable Command
-#define AT91C_TC_SWTRG        ((unsigned int) 0x1 <<  2) // (TC) Software Trigger Command
-// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
-#define AT91C_TC_CLKS         ((unsigned int) 0x7 <<  0) // (TC) Clock Selection
-#define     AT91C_TC_CLKS_TIMER_DIV1_CLOCK     ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
-#define     AT91C_TC_CLKS_TIMER_DIV2_CLOCK     ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
-#define     AT91C_TC_CLKS_TIMER_DIV3_CLOCK     ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
-#define     AT91C_TC_CLKS_TIMER_DIV4_CLOCK     ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
-#define     AT91C_TC_CLKS_TIMER_DIV5_CLOCK     ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
-#define     AT91C_TC_CLKS_XC0                  ((unsigned int) 0x5) // (TC) Clock selected: XC0
-#define     AT91C_TC_CLKS_XC1                  ((unsigned int) 0x6) // (TC) Clock selected: XC1
-#define     AT91C_TC_CLKS_XC2                  ((unsigned int) 0x7) // (TC) Clock selected: XC2
-#define AT91C_TC_CLKI         ((unsigned int) 0x1 <<  3) // (TC) Clock Invert
-#define AT91C_TC_BURST        ((unsigned int) 0x3 <<  4) // (TC) Burst Signal Selection
-#define     AT91C_TC_BURST_NONE                 ((unsigned int) 0x0 <<  4) // (TC) The clock is not gated by an external signal
-#define     AT91C_TC_BURST_XC0                  ((unsigned int) 0x1 <<  4) // (TC) XC0 is ANDed with the selected clock
-#define     AT91C_TC_BURST_XC1                  ((unsigned int) 0x2 <<  4) // (TC) XC1 is ANDed with the selected clock
-#define     AT91C_TC_BURST_XC2                  ((unsigned int) 0x3 <<  4) // (TC) XC2 is ANDed with the selected clock
-#define AT91C_TC_CPCSTOP      ((unsigned int) 0x1 <<  6) // (TC) Counter Clock Stopped with RC Compare
-#define AT91C_TC_LDBSTOP      ((unsigned int) 0x1 <<  6) // (TC) Counter Clock Stopped with RB Loading
-#define AT91C_TC_CPCDIS       ((unsigned int) 0x1 <<  7) // (TC) Counter Clock Disable with RC Compare
-#define AT91C_TC_LDBDIS       ((unsigned int) 0x1 <<  7) // (TC) Counter Clock Disabled with RB Loading
-#define AT91C_TC_ETRGEDG      ((unsigned int) 0x3 <<  8) // (TC) External Trigger Edge Selection
-#define     AT91C_TC_ETRGEDG_NONE                 ((unsigned int) 0x0 <<  8) // (TC) Edge: None
-#define     AT91C_TC_ETRGEDG_RISING               ((unsigned int) 0x1 <<  8) // (TC) Edge: rising edge
-#define     AT91C_TC_ETRGEDG_FALLING              ((unsigned int) 0x2 <<  8) // (TC) Edge: falling edge
-#define     AT91C_TC_ETRGEDG_BOTH                 ((unsigned int) 0x3 <<  8) // (TC) Edge: each edge
-#define AT91C_TC_EEVTEDG      ((unsigned int) 0x3 <<  8) // (TC) External Event Edge Selection
-#define     AT91C_TC_EEVTEDG_NONE                 ((unsigned int) 0x0 <<  8) // (TC) Edge: None
-#define     AT91C_TC_EEVTEDG_RISING               ((unsigned int) 0x1 <<  8) // (TC) Edge: rising edge
-#define     AT91C_TC_EEVTEDG_FALLING              ((unsigned int) 0x2 <<  8) // (TC) Edge: falling edge
-#define     AT91C_TC_EEVTEDG_BOTH                 ((unsigned int) 0x3 <<  8) // (TC) Edge: each edge
-#define AT91C_TC_EEVT         ((unsigned int) 0x3 << 10) // (TC) External Event  Selection
-#define     AT91C_TC_EEVT_TIOB                 ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
-#define     AT91C_TC_EEVT_XC0                  ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
-#define     AT91C_TC_EEVT_XC1                  ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
-#define     AT91C_TC_EEVT_XC2                  ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
-#define AT91C_TC_ABETRG       ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
-#define AT91C_TC_ENETRG       ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable
-#define AT91C_TC_WAVESEL      ((unsigned int) 0x3 << 13) // (TC) Waveform  Selection
-#define     AT91C_TC_WAVESEL_UP                   ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
-#define     AT91C_TC_WAVESEL_UPDOWN               ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
-#define     AT91C_TC_WAVESEL_UP_AUTO              ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
-#define     AT91C_TC_WAVESEL_UPDOWN_AUTO          ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
-#define AT91C_TC_CPCTRG       ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable
-#define AT91C_TC_WAVE         ((unsigned int) 0x1 << 15) // (TC)
-#define AT91C_TC_ACPA         ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA
-#define     AT91C_TC_ACPA_NONE                 ((unsigned int) 0x0 << 16) // (TC) Effect: none
-#define     AT91C_TC_ACPA_SET                  ((unsigned int) 0x1 << 16) // (TC) Effect: set
-#define     AT91C_TC_ACPA_CLEAR                ((unsigned int) 0x2 << 16) // (TC) Effect: clear
-#define     AT91C_TC_ACPA_TOGGLE               ((unsigned int) 0x3 << 16) // (TC) Effect: toggle
-#define AT91C_TC_LDRA         ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection
-#define     AT91C_TC_LDRA_NONE                 ((unsigned int) 0x0 << 16) // (TC) Edge: None
-#define     AT91C_TC_LDRA_RISING               ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA
-#define     AT91C_TC_LDRA_FALLING              ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA
-#define     AT91C_TC_LDRA_BOTH                 ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_ACPC         ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA
-#define     AT91C_TC_ACPC_NONE                 ((unsigned int) 0x0 << 18) // (TC) Effect: none
-#define     AT91C_TC_ACPC_SET                  ((unsigned int) 0x1 << 18) // (TC) Effect: set
-#define     AT91C_TC_ACPC_CLEAR                ((unsigned int) 0x2 << 18) // (TC) Effect: clear
-#define     AT91C_TC_ACPC_TOGGLE               ((unsigned int) 0x3 << 18) // (TC) Effect: toggle
-#define AT91C_TC_LDRB         ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection
-#define     AT91C_TC_LDRB_NONE                 ((unsigned int) 0x0 << 18) // (TC) Edge: None
-#define     AT91C_TC_LDRB_RISING               ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA
-#define     AT91C_TC_LDRB_FALLING              ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA
-#define     AT91C_TC_LDRB_BOTH                 ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_AEEVT        ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA
-#define     AT91C_TC_AEEVT_NONE                 ((unsigned int) 0x0 << 20) // (TC) Effect: none
-#define     AT91C_TC_AEEVT_SET                  ((unsigned int) 0x1 << 20) // (TC) Effect: set
-#define     AT91C_TC_AEEVT_CLEAR                ((unsigned int) 0x2 << 20) // (TC) Effect: clear
-#define     AT91C_TC_AEEVT_TOGGLE               ((unsigned int) 0x3 << 20) // (TC) Effect: toggle
-#define AT91C_TC_ASWTRG       ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA
-#define     AT91C_TC_ASWTRG_NONE                 ((unsigned int) 0x0 << 22) // (TC) Effect: none
-#define     AT91C_TC_ASWTRG_SET                  ((unsigned int) 0x1 << 22) // (TC) Effect: set
-#define     AT91C_TC_ASWTRG_CLEAR                ((unsigned int) 0x2 << 22) // (TC) Effect: clear
-#define     AT91C_TC_ASWTRG_TOGGLE               ((unsigned int) 0x3 << 22) // (TC) Effect: toggle
-#define AT91C_TC_BCPB         ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB
-#define     AT91C_TC_BCPB_NONE                 ((unsigned int) 0x0 << 24) // (TC) Effect: none
-#define     AT91C_TC_BCPB_SET                  ((unsigned int) 0x1 << 24) // (TC) Effect: set
-#define     AT91C_TC_BCPB_CLEAR                ((unsigned int) 0x2 << 24) // (TC) Effect: clear
-#define     AT91C_TC_BCPB_TOGGLE               ((unsigned int) 0x3 << 24) // (TC) Effect: toggle
-#define AT91C_TC_BCPC         ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB
-#define     AT91C_TC_BCPC_NONE                 ((unsigned int) 0x0 << 26) // (TC) Effect: none
-#define     AT91C_TC_BCPC_SET                  ((unsigned int) 0x1 << 26) // (TC) Effect: set
-#define     AT91C_TC_BCPC_CLEAR                ((unsigned int) 0x2 << 26) // (TC) Effect: clear
-#define     AT91C_TC_BCPC_TOGGLE               ((unsigned int) 0x3 << 26) // (TC) Effect: toggle
-#define AT91C_TC_BEEVT        ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB
-#define     AT91C_TC_BEEVT_NONE                 ((unsigned int) 0x0 << 28) // (TC) Effect: none
-#define     AT91C_TC_BEEVT_SET                  ((unsigned int) 0x1 << 28) // (TC) Effect: set
-#define     AT91C_TC_BEEVT_CLEAR                ((unsigned int) 0x2 << 28) // (TC) Effect: clear
-#define     AT91C_TC_BEEVT_TOGGLE               ((unsigned int) 0x3 << 28) // (TC) Effect: toggle
-#define AT91C_TC_BSWTRG       ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB
-#define     AT91C_TC_BSWTRG_NONE                 ((unsigned int) 0x0 << 30) // (TC) Effect: none
-#define     AT91C_TC_BSWTRG_SET                  ((unsigned int) 0x1 << 30) // (TC) Effect: set
-#define     AT91C_TC_BSWTRG_CLEAR                ((unsigned int) 0x2 << 30) // (TC) Effect: clear
-#define     AT91C_TC_BSWTRG_TOGGLE               ((unsigned int) 0x3 << 30) // (TC) Effect: toggle
-// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
-#define AT91C_TC_COVFS        ((unsigned int) 0x1 <<  0) // (TC) Counter Overflow
-#define AT91C_TC_LOVRS        ((unsigned int) 0x1 <<  1) // (TC) Load Overrun
-#define AT91C_TC_CPAS         ((unsigned int) 0x1 <<  2) // (TC) RA Compare
-#define AT91C_TC_CPBS         ((unsigned int) 0x1 <<  3) // (TC) RB Compare
-#define AT91C_TC_CPCS         ((unsigned int) 0x1 <<  4) // (TC) RC Compare
-#define AT91C_TC_LDRAS        ((unsigned int) 0x1 <<  5) // (TC) RA Loading
-#define AT91C_TC_LDRBS        ((unsigned int) 0x1 <<  6) // (TC) RB Loading
-#define AT91C_TC_ETRGS        ((unsigned int) 0x1 <<  7) // (TC) External Trigger
-#define AT91C_TC_CLKSTA       ((unsigned int) 0x1 << 16) // (TC) Clock Enabling
-#define AT91C_TC_MTIOA        ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror
-#define AT91C_TC_MTIOB        ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror
-// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
-// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
-// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
+/* -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- */
+#define AT91C_TC_CLKEN                        ( ( unsigned int ) 0x1 << 0 )  /* (TC) Counter Clock Enable Command */
+#define AT91C_TC_CLKDIS                       ( ( unsigned int ) 0x1 << 1 )  /* (TC) Counter Clock Disable Command */
+#define AT91C_TC_SWTRG                        ( ( unsigned int ) 0x1 << 2 )  /* (TC) Software Trigger Command */
+/* -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- */
+#define AT91C_TC_CLKS                         ( ( unsigned int ) 0x7 << 0 )  /* (TC) Clock Selection */
+#define     AT91C_TC_CLKS_TIMER_DIV1_CLOCK    ( ( unsigned int ) 0x0 )       /* (TC) Clock selected: TIMER_DIV1_CLOCK */
+#define     AT91C_TC_CLKS_TIMER_DIV2_CLOCK    ( ( unsigned int ) 0x1 )       /* (TC) Clock selected: TIMER_DIV2_CLOCK */
+#define     AT91C_TC_CLKS_TIMER_DIV3_CLOCK    ( ( unsigned int ) 0x2 )       /* (TC) Clock selected: TIMER_DIV3_CLOCK */
+#define     AT91C_TC_CLKS_TIMER_DIV4_CLOCK    ( ( unsigned int ) 0x3 )       /* (TC) Clock selected: TIMER_DIV4_CLOCK */
+#define     AT91C_TC_CLKS_TIMER_DIV5_CLOCK    ( ( unsigned int ) 0x4 )       /* (TC) Clock selected: TIMER_DIV5_CLOCK */
+#define     AT91C_TC_CLKS_XC0                 ( ( unsigned int ) 0x5 )       /* (TC) Clock selected: XC0 */
+#define     AT91C_TC_CLKS_XC1                 ( ( unsigned int ) 0x6 )       /* (TC) Clock selected: XC1 */
+#define     AT91C_TC_CLKS_XC2                 ( ( unsigned int ) 0x7 )       /* (TC) Clock selected: XC2 */
+#define AT91C_TC_CLKI                         ( ( unsigned int ) 0x1 << 3 )  /* (TC) Clock Invert */
+#define AT91C_TC_BURST                        ( ( unsigned int ) 0x3 << 4 )  /* (TC) Burst Signal Selection */
+#define     AT91C_TC_BURST_NONE               ( ( unsigned int ) 0x0 << 4 )  /* (TC) The clock is not gated by an external signal */
+#define     AT91C_TC_BURST_XC0                ( ( unsigned int ) 0x1 << 4 )  /* (TC) XC0 is ANDed with the selected clock */
+#define     AT91C_TC_BURST_XC1                ( ( unsigned int ) 0x2 << 4 )  /* (TC) XC1 is ANDed with the selected clock */
+#define     AT91C_TC_BURST_XC2                ( ( unsigned int ) 0x3 << 4 )  /* (TC) XC2 is ANDed with the selected clock */
+#define AT91C_TC_CPCSTOP                      ( ( unsigned int ) 0x1 << 6 )  /* (TC) Counter Clock Stopped with RC Compare */
+#define AT91C_TC_LDBSTOP                      ( ( unsigned int ) 0x1 << 6 )  /* (TC) Counter Clock Stopped with RB Loading */
+#define AT91C_TC_CPCDIS                       ( ( unsigned int ) 0x1 << 7 )  /* (TC) Counter Clock Disable with RC Compare */
+#define AT91C_TC_LDBDIS                       ( ( unsigned int ) 0x1 << 7 )  /* (TC) Counter Clock Disabled with RB Loading */
+#define AT91C_TC_ETRGEDG                      ( ( unsigned int ) 0x3 << 8 )  /* (TC) External Trigger Edge Selection */
+#define     AT91C_TC_ETRGEDG_NONE             ( ( unsigned int ) 0x0 << 8 )  /* (TC) Edge: None */
+#define     AT91C_TC_ETRGEDG_RISING           ( ( unsigned int ) 0x1 << 8 )  /* (TC) Edge: rising edge */
+#define     AT91C_TC_ETRGEDG_FALLING          ( ( unsigned int ) 0x2 << 8 )  /* (TC) Edge: falling edge */
+#define     AT91C_TC_ETRGEDG_BOTH             ( ( unsigned int ) 0x3 << 8 )  /* (TC) Edge: each edge */
+#define AT91C_TC_EEVTEDG                      ( ( unsigned int ) 0x3 << 8 )  /* (TC) External Event Edge Selection */
+#define     AT91C_TC_EEVTEDG_NONE             ( ( unsigned int ) 0x0 << 8 )  /* (TC) Edge: None */
+#define     AT91C_TC_EEVTEDG_RISING           ( ( unsigned int ) 0x1 << 8 )  /* (TC) Edge: rising edge */
+#define     AT91C_TC_EEVTEDG_FALLING          ( ( unsigned int ) 0x2 << 8 )  /* (TC) Edge: falling edge */
+#define     AT91C_TC_EEVTEDG_BOTH             ( ( unsigned int ) 0x3 << 8 )  /* (TC) Edge: each edge */
+#define AT91C_TC_EEVT                         ( ( unsigned int ) 0x3 << 10 ) /* (TC) External Event  Selection */
+#define     AT91C_TC_EEVT_TIOB                ( ( unsigned int ) 0x0 << 10 ) /* (TC) Signal selected as external event: TIOB TIOB direction: input */
+#define     AT91C_TC_EEVT_XC0                 ( ( unsigned int ) 0x1 << 10 ) /* (TC) Signal selected as external event: XC0 TIOB direction: output */
+#define     AT91C_TC_EEVT_XC1                 ( ( unsigned int ) 0x2 << 10 ) /* (TC) Signal selected as external event: XC1 TIOB direction: output */
+#define     AT91C_TC_EEVT_XC2                 ( ( unsigned int ) 0x3 << 10 ) /* (TC) Signal selected as external event: XC2 TIOB direction: output */
+#define AT91C_TC_ABETRG                       ( ( unsigned int ) 0x1 << 10 ) /* (TC) TIOA or TIOB External Trigger Selection */
+#define AT91C_TC_ENETRG                       ( ( unsigned int ) 0x1 << 12 ) /* (TC) External Event Trigger enable */
+#define AT91C_TC_WAVESEL                      ( ( unsigned int ) 0x3 << 13 ) /* (TC) Waveform  Selection */
+#define     AT91C_TC_WAVESEL_UP               ( ( unsigned int ) 0x0 << 13 ) /* (TC) UP mode without atomatic trigger on RC Compare */
+#define     AT91C_TC_WAVESEL_UPDOWN           ( ( unsigned int ) 0x1 << 13 ) /* (TC) UPDOWN mode without automatic trigger on RC Compare */
+#define     AT91C_TC_WAVESEL_UP_AUTO          ( ( unsigned int ) 0x2 << 13 ) /* (TC) UP mode with automatic trigger on RC Compare */
+#define     AT91C_TC_WAVESEL_UPDOWN_AUTO      ( ( unsigned int ) 0x3 << 13 ) /* (TC) UPDOWN mode with automatic trigger on RC Compare */
+#define AT91C_TC_CPCTRG                       ( ( unsigned int ) 0x1 << 14 ) /* (TC) RC Compare Trigger Enable */
+#define AT91C_TC_WAVE                         ( ( unsigned int ) 0x1 << 15 ) /* (TC) */
+#define AT91C_TC_ACPA                         ( ( unsigned int ) 0x3 << 16 ) /* (TC) RA Compare Effect on TIOA */
+#define     AT91C_TC_ACPA_NONE                ( ( unsigned int ) 0x0 << 16 ) /* (TC) Effect: none */
+#define     AT91C_TC_ACPA_SET                 ( ( unsigned int ) 0x1 << 16 ) /* (TC) Effect: set */
+#define     AT91C_TC_ACPA_CLEAR               ( ( unsigned int ) 0x2 << 16 ) /* (TC) Effect: clear */
+#define     AT91C_TC_ACPA_TOGGLE              ( ( unsigned int ) 0x3 << 16 ) /* (TC) Effect: toggle */
+#define AT91C_TC_LDRA                         ( ( unsigned int ) 0x3 << 16 ) /* (TC) RA Loading Selection */
+#define     AT91C_TC_LDRA_NONE                ( ( unsigned int ) 0x0 << 16 ) /* (TC) Edge: None */
+#define     AT91C_TC_LDRA_RISING              ( ( unsigned int ) 0x1 << 16 ) /* (TC) Edge: rising edge of TIOA */
+#define     AT91C_TC_LDRA_FALLING             ( ( unsigned int ) 0x2 << 16 ) /* (TC) Edge: falling edge of TIOA */
+#define     AT91C_TC_LDRA_BOTH                ( ( unsigned int ) 0x3 << 16 ) /* (TC) Edge: each edge of TIOA */
+#define AT91C_TC_ACPC                         ( ( unsigned int ) 0x3 << 18 ) /* (TC) RC Compare Effect on TIOA */
+#define     AT91C_TC_ACPC_NONE                ( ( unsigned int ) 0x0 << 18 ) /* (TC) Effect: none */
+#define     AT91C_TC_ACPC_SET                 ( ( unsigned int ) 0x1 << 18 ) /* (TC) Effect: set */
+#define     AT91C_TC_ACPC_CLEAR               ( ( unsigned int ) 0x2 << 18 ) /* (TC) Effect: clear */
+#define     AT91C_TC_ACPC_TOGGLE              ( ( unsigned int ) 0x3 << 18 ) /* (TC) Effect: toggle */
+#define AT91C_TC_LDRB                         ( ( unsigned int ) 0x3 << 18 ) /* (TC) RB Loading Selection */
+#define     AT91C_TC_LDRB_NONE                ( ( unsigned int ) 0x0 << 18 ) /* (TC) Edge: None */
+#define     AT91C_TC_LDRB_RISING              ( ( unsigned int ) 0x1 << 18 ) /* (TC) Edge: rising edge of TIOA */
+#define     AT91C_TC_LDRB_FALLING             ( ( unsigned int ) 0x2 << 18 ) /* (TC) Edge: falling edge of TIOA */
+#define     AT91C_TC_LDRB_BOTH                ( ( unsigned int ) 0x3 << 18 ) /* (TC) Edge: each edge of TIOA */
+#define AT91C_TC_AEEVT                        ( ( unsigned int ) 0x3 << 20 ) /* (TC) External Event Effect on TIOA */
+#define     AT91C_TC_AEEVT_NONE               ( ( unsigned int ) 0x0 << 20 ) /* (TC) Effect: none */
+#define     AT91C_TC_AEEVT_SET                ( ( unsigned int ) 0x1 << 20 ) /* (TC) Effect: set */
+#define     AT91C_TC_AEEVT_CLEAR              ( ( unsigned int ) 0x2 << 20 ) /* (TC) Effect: clear */
+#define     AT91C_TC_AEEVT_TOGGLE             ( ( unsigned int ) 0x3 << 20 ) /* (TC) Effect: toggle */
+#define AT91C_TC_ASWTRG                       ( ( unsigned int ) 0x3 << 22 ) /* (TC) Software Trigger Effect on TIOA */
+#define     AT91C_TC_ASWTRG_NONE              ( ( unsigned int ) 0x0 << 22 ) /* (TC) Effect: none */
+#define     AT91C_TC_ASWTRG_SET               ( ( unsigned int ) 0x1 << 22 ) /* (TC) Effect: set */
+#define     AT91C_TC_ASWTRG_CLEAR             ( ( unsigned int ) 0x2 << 22 ) /* (TC) Effect: clear */
+#define     AT91C_TC_ASWTRG_TOGGLE            ( ( unsigned int ) 0x3 << 22 ) /* (TC) Effect: toggle */
+#define AT91C_TC_BCPB                         ( ( unsigned int ) 0x3 << 24 ) /* (TC) RB Compare Effect on TIOB */
+#define     AT91C_TC_BCPB_NONE                ( ( unsigned int ) 0x0 << 24 ) /* (TC) Effect: none */
+#define     AT91C_TC_BCPB_SET                 ( ( unsigned int ) 0x1 << 24 ) /* (TC) Effect: set */
+#define     AT91C_TC_BCPB_CLEAR               ( ( unsigned int ) 0x2 << 24 ) /* (TC) Effect: clear */
+#define     AT91C_TC_BCPB_TOGGLE              ( ( unsigned int ) 0x3 << 24 ) /* (TC) Effect: toggle */
+#define AT91C_TC_BCPC                         ( ( unsigned int ) 0x3 << 26 ) /* (TC) RC Compare Effect on TIOB */
+#define     AT91C_TC_BCPC_NONE                ( ( unsigned int ) 0x0 << 26 ) /* (TC) Effect: none */
+#define     AT91C_TC_BCPC_SET                 ( ( unsigned int ) 0x1 << 26 ) /* (TC) Effect: set */
+#define     AT91C_TC_BCPC_CLEAR               ( ( unsigned int ) 0x2 << 26 ) /* (TC) Effect: clear */
+#define     AT91C_TC_BCPC_TOGGLE              ( ( unsigned int ) 0x3 << 26 ) /* (TC) Effect: toggle */
+#define AT91C_TC_BEEVT                        ( ( unsigned int ) 0x3 << 28 ) /* (TC) External Event Effect on TIOB */
+#define     AT91C_TC_BEEVT_NONE               ( ( unsigned int ) 0x0 << 28 ) /* (TC) Effect: none */
+#define     AT91C_TC_BEEVT_SET                ( ( unsigned int ) 0x1 << 28 ) /* (TC) Effect: set */
+#define     AT91C_TC_BEEVT_CLEAR              ( ( unsigned int ) 0x2 << 28 ) /* (TC) Effect: clear */
+#define     AT91C_TC_BEEVT_TOGGLE             ( ( unsigned int ) 0x3 << 28 ) /* (TC) Effect: toggle */
+#define AT91C_TC_BSWTRG                       ( ( unsigned int ) 0x3 << 30 ) /* (TC) Software Trigger Effect on TIOB */
+#define     AT91C_TC_BSWTRG_NONE              ( ( unsigned int ) 0x0 << 30 ) /* (TC) Effect: none */
+#define     AT91C_TC_BSWTRG_SET               ( ( unsigned int ) 0x1 << 30 ) /* (TC) Effect: set */
+#define     AT91C_TC_BSWTRG_CLEAR             ( ( unsigned int ) 0x2 << 30 ) /* (TC) Effect: clear */
+#define     AT91C_TC_BSWTRG_TOGGLE            ( ( unsigned int ) 0x3 << 30 ) /* (TC) Effect: toggle */
+/* -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- */
+#define AT91C_TC_COVFS                        ( ( unsigned int ) 0x1 << 0 )  /* (TC) Counter Overflow */
+#define AT91C_TC_LOVRS                        ( ( unsigned int ) 0x1 << 1 )  /* (TC) Load Overrun */
+#define AT91C_TC_CPAS                         ( ( unsigned int ) 0x1 << 2 )  /* (TC) RA Compare */
+#define AT91C_TC_CPBS                         ( ( unsigned int ) 0x1 << 3 )  /* (TC) RB Compare */
+#define AT91C_TC_CPCS                         ( ( unsigned int ) 0x1 << 4 )  /* (TC) RC Compare */
+#define AT91C_TC_LDRAS                        ( ( unsigned int ) 0x1 << 5 )  /* (TC) RA Loading */
+#define AT91C_TC_LDRBS                        ( ( unsigned int ) 0x1 << 6 )  /* (TC) RB Loading */
+#define AT91C_TC_ETRGS                        ( ( unsigned int ) 0x1 << 7 )  /* (TC) External Trigger */
+#define AT91C_TC_CLKSTA                       ( ( unsigned int ) 0x1 << 16 ) /* (TC) Clock Enabling */
+#define AT91C_TC_MTIOA                        ( ( unsigned int ) 0x1 << 17 ) /* (TC) TIOA Mirror */
+#define AT91C_TC_MTIOB                        ( ( unsigned int ) 0x1 << 18 ) /* (TC) TIOA Mirror */
+/* -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- */
+/* -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- */
+/* -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Timer Counter Interface
-// *****************************************************************************
-typedef struct _AT91S_TCB {
-    AT91S_TC     TCB_TC0;   // TC Channel 0
-    AT91_REG     Reserved0[4];  //
-    AT91S_TC     TCB_TC1;   // TC Channel 1
-    AT91_REG     Reserved1[4];  //
-    AT91S_TC     TCB_TC2;   // TC Channel 2
-    AT91_REG     Reserved2[4];  //
-    AT91_REG     TCB_BCR;   // TC Block Control Register
-    AT91_REG     TCB_BMR;   // TC Block Mode Register
-} AT91S_TCB, *AT91PS_TCB;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Timer Counter Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_TCB
+{
+    AT91S_TC TCB_TC0;        /* TC Channel 0 */
+    AT91_REG Reserved0[ 4 ]; /* */
+    AT91S_TC TCB_TC1;        /* TC Channel 1 */
+    AT91_REG Reserved1[ 4 ]; /* */
+    AT91S_TC TCB_TC2;        /* TC Channel 2 */
+    AT91_REG Reserved2[ 4 ]; /* */
+    AT91_REG TCB_BCR;        /* TC Block Control Register */
+    AT91_REG TCB_BMR;        /* TC Block Mode Register */
+} AT91S_TCB, * AT91PS_TCB;
 
-// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
-#define AT91C_TCB_SYNC        ((unsigned int) 0x1 <<  0) // (TCB) Synchro Command
-// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
-#define AT91C_TCB_TC0XC0S     ((unsigned int) 0x3 <<  0) // (TCB) External Clock Signal 0 Selection
-#define     AT91C_TCB_TC0XC0S_TCLK0                ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0
-#define     AT91C_TCB_TC0XC0S_NONE                 ((unsigned int) 0x1) // (TCB) None signal connected to XC0
-#define     AT91C_TCB_TC0XC0S_TIOA1                ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0
-#define     AT91C_TCB_TC0XC0S_TIOA2                ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0
-#define AT91C_TCB_TC1XC1S     ((unsigned int) 0x3 <<  2) // (TCB) External Clock Signal 1 Selection
-#define     AT91C_TCB_TC1XC1S_TCLK1                ((unsigned int) 0x0 <<  2) // (TCB) TCLK1 connected to XC1
-#define     AT91C_TCB_TC1XC1S_NONE                 ((unsigned int) 0x1 <<  2) // (TCB) None signal connected to XC1
-#define     AT91C_TCB_TC1XC1S_TIOA0                ((unsigned int) 0x2 <<  2) // (TCB) TIOA0 connected to XC1
-#define     AT91C_TCB_TC1XC1S_TIOA2                ((unsigned int) 0x3 <<  2) // (TCB) TIOA2 connected to XC1
-#define AT91C_TCB_TC2XC2S     ((unsigned int) 0x3 <<  4) // (TCB) External Clock Signal 2 Selection
-#define     AT91C_TCB_TC2XC2S_TCLK2                ((unsigned int) 0x0 <<  4) // (TCB) TCLK2 connected to XC2
-#define     AT91C_TCB_TC2XC2S_NONE                 ((unsigned int) 0x1 <<  4) // (TCB) None signal connected to XC2
-#define     AT91C_TCB_TC2XC2S_TIOA0                ((unsigned int) 0x2 <<  4) // (TCB) TIOA0 connected to XC2
-#define     AT91C_TCB_TC2XC2S_TIOA1                ((unsigned int) 0x3 <<  4) // (TCB) TIOA2 connected to XC2
+/* -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- */
+#define AT91C_TCB_SYNC                 ( ( unsigned int ) 0x1 << 0 ) /* (TCB) Synchro Command */
+/* -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- */
+#define AT91C_TCB_TC0XC0S              ( ( unsigned int ) 0x3 << 0 ) /* (TCB) External Clock Signal 0 Selection */
+#define     AT91C_TCB_TC0XC0S_TCLK0    ( ( unsigned int ) 0x0 )      /* (TCB) TCLK0 connected to XC0 */
+#define     AT91C_TCB_TC0XC0S_NONE     ( ( unsigned int ) 0x1 )      /* (TCB) None signal connected to XC0 */
+#define     AT91C_TCB_TC0XC0S_TIOA1    ( ( unsigned int ) 0x2 )      /* (TCB) TIOA1 connected to XC0 */
+#define     AT91C_TCB_TC0XC0S_TIOA2    ( ( unsigned int ) 0x3 )      /* (TCB) TIOA2 connected to XC0 */
+#define AT91C_TCB_TC1XC1S              ( ( unsigned int ) 0x3 << 2 ) /* (TCB) External Clock Signal 1 Selection */
+#define     AT91C_TCB_TC1XC1S_TCLK1    ( ( unsigned int ) 0x0 << 2 ) /* (TCB) TCLK1 connected to XC1 */
+#define     AT91C_TCB_TC1XC1S_NONE     ( ( unsigned int ) 0x1 << 2 ) /* (TCB) None signal connected to XC1 */
+#define     AT91C_TCB_TC1XC1S_TIOA0    ( ( unsigned int ) 0x2 << 2 ) /* (TCB) TIOA0 connected to XC1 */
+#define     AT91C_TCB_TC1XC1S_TIOA2    ( ( unsigned int ) 0x3 << 2 ) /* (TCB) TIOA2 connected to XC1 */
+#define AT91C_TCB_TC2XC2S              ( ( unsigned int ) 0x3 << 4 ) /* (TCB) External Clock Signal 2 Selection */
+#define     AT91C_TCB_TC2XC2S_TCLK2    ( ( unsigned int ) 0x0 << 4 ) /* (TCB) TCLK2 connected to XC2 */
+#define     AT91C_TCB_TC2XC2S_NONE     ( ( unsigned int ) 0x1 << 4 ) /* (TCB) None signal connected to XC2 */
+#define     AT91C_TCB_TC2XC2S_TIOA0    ( ( unsigned int ) 0x2 << 4 ) /* (TCB) TIOA0 connected to XC2 */
+#define     AT91C_TCB_TC2XC2S_TIOA1    ( ( unsigned int ) 0x3 << 4 ) /* (TCB) TIOA2 connected to XC2 */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Control Area Network MailBox Interface
-// *****************************************************************************
-typedef struct _AT91S_CAN_MB {
-    AT91_REG     CAN_MB_MMR;    // MailBox Mode Register
-    AT91_REG     CAN_MB_MAM;    // MailBox Acceptance Mask Register
-    AT91_REG     CAN_MB_MID;    // MailBox ID Register
-    AT91_REG     CAN_MB_MFID;   // MailBox Family ID Register
-    AT91_REG     CAN_MB_MSR;    // MailBox Status Register
-    AT91_REG     CAN_MB_MDL;    // MailBox Data Low Register
-    AT91_REG     CAN_MB_MDH;    // MailBox Data High Register
-    AT91_REG     CAN_MB_MCR;    // MailBox Control Register
-} AT91S_CAN_MB, *AT91PS_CAN_MB;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Control Area Network MailBox Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_CAN_MB
+{
+    AT91_REG CAN_MB_MMR;  /* MailBox Mode Register */
+    AT91_REG CAN_MB_MAM;  /* MailBox Acceptance Mask Register */
+    AT91_REG CAN_MB_MID;  /* MailBox ID Register */
+    AT91_REG CAN_MB_MFID; /* MailBox Family ID Register */
+    AT91_REG CAN_MB_MSR;  /* MailBox Status Register */
+    AT91_REG CAN_MB_MDL;  /* MailBox Data Low Register */
+    AT91_REG CAN_MB_MDH;  /* MailBox Data High Register */
+    AT91_REG CAN_MB_MCR;  /* MailBox Control Register */
+} AT91S_CAN_MB, * AT91PS_CAN_MB;
 
-// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register --------
-#define AT91C_CAN_MTIMEMARK   ((unsigned int) 0xFFFF <<  0) // (CAN_MB) Mailbox Timemark
-#define AT91C_CAN_PRIOR       ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority
-#define AT91C_CAN_MOT         ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type
-#define     AT91C_CAN_MOT_DIS                  ((unsigned int) 0x0 << 24) // (CAN_MB)
-#define     AT91C_CAN_MOT_RX                   ((unsigned int) 0x1 << 24) // (CAN_MB)
-#define     AT91C_CAN_MOT_RXOVERWRITE          ((unsigned int) 0x2 << 24) // (CAN_MB)
-#define     AT91C_CAN_MOT_TX                   ((unsigned int) 0x3 << 24) // (CAN_MB)
-#define     AT91C_CAN_MOT_CONSUMER             ((unsigned int) 0x4 << 24) // (CAN_MB)
-#define     AT91C_CAN_MOT_PRODUCER             ((unsigned int) 0x5 << 24) // (CAN_MB)
-// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register --------
-#define AT91C_CAN_MIDvB       ((unsigned int) 0x3FFFF <<  0) // (CAN_MB) Complementary bits for identifier in extended mode
-#define AT91C_CAN_MIDvA       ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode
-#define AT91C_CAN_MIDE        ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version
-// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register --------
-// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register --------
-// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register --------
-#define AT91C_CAN_MTIMESTAMP  ((unsigned int) 0xFFFF <<  0) // (CAN_MB) Timer Value
-#define AT91C_CAN_MDLC        ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code
-#define AT91C_CAN_MRTR        ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request
-#define AT91C_CAN_MABT        ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort
-#define AT91C_CAN_MRDY        ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready
-#define AT91C_CAN_MMI         ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored
-// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register --------
-// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register --------
-// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register --------
-#define AT91C_CAN_MACR        ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox
-#define AT91C_CAN_MTCR        ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command
+/* -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- */
+#define AT91C_CAN_MTIMEMARK              ( ( unsigned int ) 0xFFFF << 0 )  /* (CAN_MB) Mailbox Timemark */
+#define AT91C_CAN_PRIOR                  ( ( unsigned int ) 0xF << 16 )    /* (CAN_MB) Mailbox Priority */
+#define AT91C_CAN_MOT                    ( ( unsigned int ) 0x7 << 24 )    /* (CAN_MB) Mailbox Object Type */
+#define     AT91C_CAN_MOT_DIS            ( ( unsigned int ) 0x0 << 24 )    /* (CAN_MB) */
+#define     AT91C_CAN_MOT_RX             ( ( unsigned int ) 0x1 << 24 )    /* (CAN_MB) */
+#define     AT91C_CAN_MOT_RXOVERWRITE    ( ( unsigned int ) 0x2 << 24 )    /* (CAN_MB) */
+#define     AT91C_CAN_MOT_TX             ( ( unsigned int ) 0x3 << 24 )    /* (CAN_MB) */
+#define     AT91C_CAN_MOT_CONSUMER       ( ( unsigned int ) 0x4 << 24 )    /* (CAN_MB) */
+#define     AT91C_CAN_MOT_PRODUCER       ( ( unsigned int ) 0x5 << 24 )    /* (CAN_MB) */
+/* -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- */
+#define AT91C_CAN_MIDvB                  ( ( unsigned int ) 0x3FFFF << 0 ) /* (CAN_MB) Complementary bits for identifier in extended mode */
+#define AT91C_CAN_MIDvA                  ( ( unsigned int ) 0x7FF << 18 )  /* (CAN_MB) Identifier for standard frame mode */
+#define AT91C_CAN_MIDE                   ( ( unsigned int ) 0x1 << 29 )    /* (CAN_MB) Identifier Version */
+/* -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- */
+/* -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- */
+/* -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- */
+#define AT91C_CAN_MTIMESTAMP    ( ( unsigned int ) 0xFFFF << 0 ) /* (CAN_MB) Timer Value */
+#define AT91C_CAN_MDLC          ( ( unsigned int ) 0xF << 16 )   /* (CAN_MB) Mailbox Data Length Code */
+#define AT91C_CAN_MRTR          ( ( unsigned int ) 0x1 << 20 )   /* (CAN_MB) Mailbox Remote Transmission Request */
+#define AT91C_CAN_MABT          ( ( unsigned int ) 0x1 << 22 )   /* (CAN_MB) Mailbox Message Abort */
+#define AT91C_CAN_MRDY          ( ( unsigned int ) 0x1 << 23 )   /* (CAN_MB) Mailbox Ready */
+#define AT91C_CAN_MMI           ( ( unsigned int ) 0x1 << 24 )   /* (CAN_MB) Mailbox Message Ignored */
+/* -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- */
+/* -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- */
+/* -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- */
+#define AT91C_CAN_MACR    ( ( unsigned int ) 0x1 << 22 ) /* (CAN_MB) Abort Request for Mailbox */
+#define AT91C_CAN_MTCR    ( ( unsigned int ) 0x1 << 23 ) /* (CAN_MB) Mailbox Transfer Command */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Control Area Network Interface
-// *****************************************************************************
-typedef struct _AT91S_CAN {
-    AT91_REG     CAN_MR;    // Mode Register
-    AT91_REG     CAN_IER;   // Interrupt Enable Register
-    AT91_REG     CAN_IDR;   // Interrupt Disable Register
-    AT91_REG     CAN_IMR;   // Interrupt Mask Register
-    AT91_REG     CAN_SR;    // Status Register
-    AT91_REG     CAN_BR;    // Baudrate Register
-    AT91_REG     CAN_TIM;   // Timer Register
-    AT91_REG     CAN_TIMESTP;   // Time Stamp Register
-    AT91_REG     CAN_ECR;   // Error Counter Register
-    AT91_REG     CAN_TCR;   // Transfer Command Register
-    AT91_REG     CAN_ACR;   // Abort Command Register
-    AT91_REG     Reserved0[52];     //
-    AT91_REG     CAN_VR;    // Version Register
-    AT91_REG     Reserved1[64];     //
-    AT91S_CAN_MB     CAN_MB0;   // CAN Mailbox 0
-    AT91S_CAN_MB     CAN_MB1;   // CAN Mailbox 1
-    AT91S_CAN_MB     CAN_MB2;   // CAN Mailbox 2
-    AT91S_CAN_MB     CAN_MB3;   // CAN Mailbox 3
-    AT91S_CAN_MB     CAN_MB4;   // CAN Mailbox 4
-    AT91S_CAN_MB     CAN_MB5;   // CAN Mailbox 5
-    AT91S_CAN_MB     CAN_MB6;   // CAN Mailbox 6
-    AT91S_CAN_MB     CAN_MB7;   // CAN Mailbox 7
-    AT91S_CAN_MB     CAN_MB8;   // CAN Mailbox 8
-    AT91S_CAN_MB     CAN_MB9;   // CAN Mailbox 9
-    AT91S_CAN_MB     CAN_MB10;  // CAN Mailbox 10
-    AT91S_CAN_MB     CAN_MB11;  // CAN Mailbox 11
-    AT91S_CAN_MB     CAN_MB12;  // CAN Mailbox 12
-    AT91S_CAN_MB     CAN_MB13;  // CAN Mailbox 13
-    AT91S_CAN_MB     CAN_MB14;  // CAN Mailbox 14
-    AT91S_CAN_MB     CAN_MB15;  // CAN Mailbox 15
-} AT91S_CAN, *AT91PS_CAN;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Control Area Network Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_CAN
+{
+    AT91_REG CAN_MR;          /* Mode Register */
+    AT91_REG CAN_IER;         /* Interrupt Enable Register */
+    AT91_REG CAN_IDR;         /* Interrupt Disable Register */
+    AT91_REG CAN_IMR;         /* Interrupt Mask Register */
+    AT91_REG CAN_SR;          /* Status Register */
+    AT91_REG CAN_BR;          /* Baudrate Register */
+    AT91_REG CAN_TIM;         /* Timer Register */
+    AT91_REG CAN_TIMESTP;     /* Time Stamp Register */
+    AT91_REG CAN_ECR;         /* Error Counter Register */
+    AT91_REG CAN_TCR;         /* Transfer Command Register */
+    AT91_REG CAN_ACR;         /* Abort Command Register */
+    AT91_REG Reserved0[ 52 ]; /* */
+    AT91_REG CAN_VR;          /* Version Register */
+    AT91_REG Reserved1[ 64 ]; /* */
+    AT91S_CAN_MB CAN_MB0;     /* CAN Mailbox 0 */
+    AT91S_CAN_MB CAN_MB1;     /* CAN Mailbox 1 */
+    AT91S_CAN_MB CAN_MB2;     /* CAN Mailbox 2 */
+    AT91S_CAN_MB CAN_MB3;     /* CAN Mailbox 3 */
+    AT91S_CAN_MB CAN_MB4;     /* CAN Mailbox 4 */
+    AT91S_CAN_MB CAN_MB5;     /* CAN Mailbox 5 */
+    AT91S_CAN_MB CAN_MB6;     /* CAN Mailbox 6 */
+    AT91S_CAN_MB CAN_MB7;     /* CAN Mailbox 7 */
+    AT91S_CAN_MB CAN_MB8;     /* CAN Mailbox 8 */
+    AT91S_CAN_MB CAN_MB9;     /* CAN Mailbox 9 */
+    AT91S_CAN_MB CAN_MB10;    /* CAN Mailbox 10 */
+    AT91S_CAN_MB CAN_MB11;    /* CAN Mailbox 11 */
+    AT91S_CAN_MB CAN_MB12;    /* CAN Mailbox 12 */
+    AT91S_CAN_MB CAN_MB13;    /* CAN Mailbox 13 */
+    AT91S_CAN_MB CAN_MB14;    /* CAN Mailbox 14 */
+    AT91S_CAN_MB CAN_MB15;    /* CAN Mailbox 15 */
+} AT91S_CAN, * AT91PS_CAN;
 
-// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register --------
-#define AT91C_CAN_CANEN       ((unsigned int) 0x1 <<  0) // (CAN) CAN Controller Enable
-#define AT91C_CAN_LPM         ((unsigned int) 0x1 <<  1) // (CAN) Disable/Enable Low Power Mode
-#define AT91C_CAN_ABM         ((unsigned int) 0x1 <<  2) // (CAN) Disable/Enable Autobaud/Listen Mode
-#define AT91C_CAN_OVL         ((unsigned int) 0x1 <<  3) // (CAN) Disable/Enable Overload Frame
-#define AT91C_CAN_TEOF        ((unsigned int) 0x1 <<  4) // (CAN) Time Stamp messages at each end of Frame
-#define AT91C_CAN_TTM         ((unsigned int) 0x1 <<  5) // (CAN) Disable/Enable Time Trigger Mode
-#define AT91C_CAN_TIMFRZ      ((unsigned int) 0x1 <<  6) // (CAN) Enable Timer Freeze
-#define AT91C_CAN_DRPT        ((unsigned int) 0x1 <<  7) // (CAN) Disable Repeat
-// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register --------
-#define AT91C_CAN_MB0         ((unsigned int) 0x1 <<  0) // (CAN) Mailbox 0 Flag
-#define AT91C_CAN_MB1         ((unsigned int) 0x1 <<  1) // (CAN) Mailbox 1 Flag
-#define AT91C_CAN_MB2         ((unsigned int) 0x1 <<  2) // (CAN) Mailbox 2 Flag
-#define AT91C_CAN_MB3         ((unsigned int) 0x1 <<  3) // (CAN) Mailbox 3 Flag
-#define AT91C_CAN_MB4         ((unsigned int) 0x1 <<  4) // (CAN) Mailbox 4 Flag
-#define AT91C_CAN_MB5         ((unsigned int) 0x1 <<  5) // (CAN) Mailbox 5 Flag
-#define AT91C_CAN_MB6         ((unsigned int) 0x1 <<  6) // (CAN) Mailbox 6 Flag
-#define AT91C_CAN_MB7         ((unsigned int) 0x1 <<  7) // (CAN) Mailbox 7 Flag
-#define AT91C_CAN_MB8         ((unsigned int) 0x1 <<  8) // (CAN) Mailbox 8 Flag
-#define AT91C_CAN_MB9         ((unsigned int) 0x1 <<  9) // (CAN) Mailbox 9 Flag
-#define AT91C_CAN_MB10        ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag
-#define AT91C_CAN_MB11        ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag
-#define AT91C_CAN_MB12        ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag
-#define AT91C_CAN_MB13        ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag
-#define AT91C_CAN_MB14        ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag
-#define AT91C_CAN_MB15        ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag
-#define AT91C_CAN_ERRA        ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag
-#define AT91C_CAN_WARN        ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag
-#define AT91C_CAN_ERRP        ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag
-#define AT91C_CAN_BOFF        ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag
-#define AT91C_CAN_SLEEP       ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag
-#define AT91C_CAN_WAKEUP      ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag
-#define AT91C_CAN_TOVF        ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag
-#define AT91C_CAN_TSTP        ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag
-#define AT91C_CAN_CERR        ((unsigned int) 0x1 << 24) // (CAN) CRC Error
-#define AT91C_CAN_SERR        ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error
-#define AT91C_CAN_AERR        ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error
-#define AT91C_CAN_FERR        ((unsigned int) 0x1 << 27) // (CAN) Form Error
-#define AT91C_CAN_BERR        ((unsigned int) 0x1 << 28) // (CAN) Bit Error
-// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register --------
-// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register --------
-// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register --------
-#define AT91C_CAN_RBSY        ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy
-#define AT91C_CAN_TBSY        ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy
-#define AT91C_CAN_OVLY        ((unsigned int) 0x1 << 31) // (CAN) Overload Busy
-// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register --------
-#define AT91C_CAN_PHASE2      ((unsigned int) 0x7 <<  0) // (CAN) Phase 2 segment
-#define AT91C_CAN_PHASE1      ((unsigned int) 0x7 <<  4) // (CAN) Phase 1 segment
-#define AT91C_CAN_PROPAG      ((unsigned int) 0x7 <<  8) // (CAN) Programmation time segment
-#define AT91C_CAN_SYNC        ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment
-#define AT91C_CAN_BRP         ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler
-#define AT91C_CAN_SMP         ((unsigned int) 0x1 << 24) // (CAN) Sampling mode
-// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register --------
-#define AT91C_CAN_TIMER       ((unsigned int) 0xFFFF <<  0) // (CAN) Timer field
-// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register --------
-// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register --------
-#define AT91C_CAN_REC         ((unsigned int) 0xFF <<  0) // (CAN) Receive Error Counter
-#define AT91C_CAN_TEC         ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter
-// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register --------
-#define AT91C_CAN_TIMRST      ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field
-// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register --------
+/* -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- */
+#define AT91C_CAN_CANEN     ( ( unsigned int ) 0x1 << 0 )  /* (CAN) CAN Controller Enable */
+#define AT91C_CAN_LPM       ( ( unsigned int ) 0x1 << 1 )  /* (CAN) Disable/Enable Low Power Mode */
+#define AT91C_CAN_ABM       ( ( unsigned int ) 0x1 << 2 )  /* (CAN) Disable/Enable Autobaud/Listen Mode */
+#define AT91C_CAN_OVL       ( ( unsigned int ) 0x1 << 3 )  /* (CAN) Disable/Enable Overload Frame */
+#define AT91C_CAN_TEOF      ( ( unsigned int ) 0x1 << 4 )  /* (CAN) Time Stamp messages at each end of Frame */
+#define AT91C_CAN_TTM       ( ( unsigned int ) 0x1 << 5 )  /* (CAN) Disable/Enable Time Trigger Mode */
+#define AT91C_CAN_TIMFRZ    ( ( unsigned int ) 0x1 << 6 )  /* (CAN) Enable Timer Freeze */
+#define AT91C_CAN_DRPT      ( ( unsigned int ) 0x1 << 7 )  /* (CAN) Disable Repeat */
+/* -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- */
+#define AT91C_CAN_MB0       ( ( unsigned int ) 0x1 << 0 )  /* (CAN) Mailbox 0 Flag */
+#define AT91C_CAN_MB1       ( ( unsigned int ) 0x1 << 1 )  /* (CAN) Mailbox 1 Flag */
+#define AT91C_CAN_MB2       ( ( unsigned int ) 0x1 << 2 )  /* (CAN) Mailbox 2 Flag */
+#define AT91C_CAN_MB3       ( ( unsigned int ) 0x1 << 3 )  /* (CAN) Mailbox 3 Flag */
+#define AT91C_CAN_MB4       ( ( unsigned int ) 0x1 << 4 )  /* (CAN) Mailbox 4 Flag */
+#define AT91C_CAN_MB5       ( ( unsigned int ) 0x1 << 5 )  /* (CAN) Mailbox 5 Flag */
+#define AT91C_CAN_MB6       ( ( unsigned int ) 0x1 << 6 )  /* (CAN) Mailbox 6 Flag */
+#define AT91C_CAN_MB7       ( ( unsigned int ) 0x1 << 7 )  /* (CAN) Mailbox 7 Flag */
+#define AT91C_CAN_MB8       ( ( unsigned int ) 0x1 << 8 )  /* (CAN) Mailbox 8 Flag */
+#define AT91C_CAN_MB9       ( ( unsigned int ) 0x1 << 9 )  /* (CAN) Mailbox 9 Flag */
+#define AT91C_CAN_MB10      ( ( unsigned int ) 0x1 << 10 ) /* (CAN) Mailbox 10 Flag */
+#define AT91C_CAN_MB11      ( ( unsigned int ) 0x1 << 11 ) /* (CAN) Mailbox 11 Flag */
+#define AT91C_CAN_MB12      ( ( unsigned int ) 0x1 << 12 ) /* (CAN) Mailbox 12 Flag */
+#define AT91C_CAN_MB13      ( ( unsigned int ) 0x1 << 13 ) /* (CAN) Mailbox 13 Flag */
+#define AT91C_CAN_MB14      ( ( unsigned int ) 0x1 << 14 ) /* (CAN) Mailbox 14 Flag */
+#define AT91C_CAN_MB15      ( ( unsigned int ) 0x1 << 15 ) /* (CAN) Mailbox 15 Flag */
+#define AT91C_CAN_ERRA      ( ( unsigned int ) 0x1 << 16 ) /* (CAN) Error Active Mode Flag */
+#define AT91C_CAN_WARN      ( ( unsigned int ) 0x1 << 17 ) /* (CAN) Warning Limit Flag */
+#define AT91C_CAN_ERRP      ( ( unsigned int ) 0x1 << 18 ) /* (CAN) Error Passive Mode Flag */
+#define AT91C_CAN_BOFF      ( ( unsigned int ) 0x1 << 19 ) /* (CAN) Bus Off Mode Flag */
+#define AT91C_CAN_SLEEP     ( ( unsigned int ) 0x1 << 20 ) /* (CAN) Sleep Flag */
+#define AT91C_CAN_WAKEUP    ( ( unsigned int ) 0x1 << 21 ) /* (CAN) Wakeup Flag */
+#define AT91C_CAN_TOVF      ( ( unsigned int ) 0x1 << 22 ) /* (CAN) Timer Overflow Flag */
+#define AT91C_CAN_TSTP      ( ( unsigned int ) 0x1 << 23 ) /* (CAN) Timestamp Flag */
+#define AT91C_CAN_CERR      ( ( unsigned int ) 0x1 << 24 ) /* (CAN) CRC Error */
+#define AT91C_CAN_SERR      ( ( unsigned int ) 0x1 << 25 ) /* (CAN) Stuffing Error */
+#define AT91C_CAN_AERR      ( ( unsigned int ) 0x1 << 26 ) /* (CAN) Acknowledgment Error */
+#define AT91C_CAN_FERR      ( ( unsigned int ) 0x1 << 27 ) /* (CAN) Form Error */
+#define AT91C_CAN_BERR      ( ( unsigned int ) 0x1 << 28 ) /* (CAN) Bit Error */
+/* -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- */
+/* -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- */
+/* -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- */
+#define AT91C_CAN_RBSY      ( ( unsigned int ) 0x1 << 29 )   /* (CAN) Receiver Busy */
+#define AT91C_CAN_TBSY      ( ( unsigned int ) 0x1 << 30 )   /* (CAN) Transmitter Busy */
+#define AT91C_CAN_OVLY      ( ( unsigned int ) 0x1 << 31 )   /* (CAN) Overload Busy */
+/* -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- */
+#define AT91C_CAN_PHASE2    ( ( unsigned int ) 0x7 << 0 )    /* (CAN) Phase 2 segment */
+#define AT91C_CAN_PHASE1    ( ( unsigned int ) 0x7 << 4 )    /* (CAN) Phase 1 segment */
+#define AT91C_CAN_PROPAG    ( ( unsigned int ) 0x7 << 8 )    /* (CAN) Programmation time segment */
+#define AT91C_CAN_SYNC      ( ( unsigned int ) 0x3 << 12 )   /* (CAN) Re-synchronization jump width segment */
+#define AT91C_CAN_BRP       ( ( unsigned int ) 0x7F << 16 )  /* (CAN) Baudrate Prescaler */
+#define AT91C_CAN_SMP       ( ( unsigned int ) 0x1 << 24 )   /* (CAN) Sampling mode */
+/* -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- */
+#define AT91C_CAN_TIMER     ( ( unsigned int ) 0xFFFF << 0 ) /* (CAN) Timer field */
+/* -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- */
+/* -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- */
+#define AT91C_CAN_REC       ( ( unsigned int ) 0xFF << 0 )  /* (CAN) Receive Error Counter */
+#define AT91C_CAN_TEC       ( ( unsigned int ) 0xFF << 16 ) /* (CAN) Transmit Error Counter */
+/* -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- */
+#define AT91C_CAN_TIMRST    ( ( unsigned int ) 0x1 << 31 )  /* (CAN) Timer Reset Field */
+/* -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Ethernet MAC 10/100
-// *****************************************************************************
-typedef struct _AT91S_EMAC {
-    AT91_REG     EMAC_NCR;  // Network Control Register
-    AT91_REG     EMAC_NCFGR;    // Network Configuration Register
-    AT91_REG     EMAC_NSR;  // Network Status Register
-    AT91_REG     Reserved0[2];  //
-    AT91_REG     EMAC_TSR;  // Transmit Status Register
-    AT91_REG     EMAC_RBQP;     // Receive Buffer Queue Pointer
-    AT91_REG     EMAC_TBQP;     // Transmit Buffer Queue Pointer
-    AT91_REG     EMAC_RSR;  // Receive Status Register
-    AT91_REG     EMAC_ISR;  // Interrupt Status Register
-    AT91_REG     EMAC_IER;  // Interrupt Enable Register
-    AT91_REG     EMAC_IDR;  // Interrupt Disable Register
-    AT91_REG     EMAC_IMR;  // Interrupt Mask Register
-    AT91_REG     EMAC_MAN;  // PHY Maintenance Register
-    AT91_REG     EMAC_PTR;  // Pause Time Register
-    AT91_REG     EMAC_PFR;  // Pause Frames received Register
-    AT91_REG     EMAC_FTO;  // Frames Transmitted OK Register
-    AT91_REG     EMAC_SCF;  // Single Collision Frame Register
-    AT91_REG     EMAC_MCF;  // Multiple Collision Frame Register
-    AT91_REG     EMAC_FRO;  // Frames Received OK Register
-    AT91_REG     EMAC_FCSE;     // Frame Check Sequence Error Register
-    AT91_REG     EMAC_ALE;  // Alignment Error Register
-    AT91_REG     EMAC_DTF;  // Deferred Transmission Frame Register
-    AT91_REG     EMAC_LCOL;     // Late Collision Register
-    AT91_REG     EMAC_ECOL;     // Excessive Collision Register
-    AT91_REG     EMAC_TUND;     // Transmit Underrun Error Register
-    AT91_REG     EMAC_CSE;  // Carrier Sense Error Register
-    AT91_REG     EMAC_RRE;  // Receive Ressource Error Register
-    AT91_REG     EMAC_ROV;  // Receive Overrun Errors Register
-    AT91_REG     EMAC_RSE;  // Receive Symbol Errors Register
-    AT91_REG     EMAC_ELE;  // Excessive Length Errors Register
-    AT91_REG     EMAC_RJA;  // Receive Jabbers Register
-    AT91_REG     EMAC_USF;  // Undersize Frames Register
-    AT91_REG     EMAC_STE;  // SQE Test Error Register
-    AT91_REG     EMAC_RLE;  // Receive Length Field Mismatch Register
-    AT91_REG     EMAC_TPF;  // Transmitted Pause Frames Register
-    AT91_REG     EMAC_HRB;  // Hash Address Bottom[31:0]
-    AT91_REG     EMAC_HRT;  // Hash Address Top[63:32]
-    AT91_REG     EMAC_SA1L;     // Specific Address 1 Bottom, First 4 bytes
-    AT91_REG     EMAC_SA1H;     // Specific Address 1 Top, Last 2 bytes
-    AT91_REG     EMAC_SA2L;     // Specific Address 2 Bottom, First 4 bytes
-    AT91_REG     EMAC_SA2H;     // Specific Address 2 Top, Last 2 bytes
-    AT91_REG     EMAC_SA3L;     // Specific Address 3 Bottom, First 4 bytes
-    AT91_REG     EMAC_SA3H;     // Specific Address 3 Top, Last 2 bytes
-    AT91_REG     EMAC_SA4L;     // Specific Address 4 Bottom, First 4 bytes
-    AT91_REG     EMAC_SA4H;     // Specific Address 4 Top, Last 2 bytes
-    AT91_REG     EMAC_TID;  // Type ID Checking Register
-    AT91_REG     EMAC_TPQ;  // Transmit Pause Quantum Register
-    AT91_REG     EMAC_USRIO;    // USER Input/Output Register
-    AT91_REG     EMAC_WOL;  // Wake On LAN Register
-    AT91_REG     Reserved1[13];     //
-    AT91_REG     EMAC_REV;  // Revision Register
-} AT91S_EMAC, *AT91PS_EMAC;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Ethernet MAC 10/100 */
+/* ***************************************************************************** */
+typedef struct _AT91S_EMAC
+{
+    AT91_REG EMAC_NCR;        /* Network Control Register */
+    AT91_REG EMAC_NCFGR;      /* Network Configuration Register */
+    AT91_REG EMAC_NSR;        /* Network Status Register */
+    AT91_REG Reserved0[ 2 ];  /* */
+    AT91_REG EMAC_TSR;        /* Transmit Status Register */
+    AT91_REG EMAC_RBQP;       /* Receive Buffer Queue Pointer */
+    AT91_REG EMAC_TBQP;       /* Transmit Buffer Queue Pointer */
+    AT91_REG EMAC_RSR;        /* Receive Status Register */
+    AT91_REG EMAC_ISR;        /* Interrupt Status Register */
+    AT91_REG EMAC_IER;        /* Interrupt Enable Register */
+    AT91_REG EMAC_IDR;        /* Interrupt Disable Register */
+    AT91_REG EMAC_IMR;        /* Interrupt Mask Register */
+    AT91_REG EMAC_MAN;        /* PHY Maintenance Register */
+    AT91_REG EMAC_PTR;        /* Pause Time Register */
+    AT91_REG EMAC_PFR;        /* Pause Frames received Register */
+    AT91_REG EMAC_FTO;        /* Frames Transmitted OK Register */
+    AT91_REG EMAC_SCF;        /* Single Collision Frame Register */
+    AT91_REG EMAC_MCF;        /* Multiple Collision Frame Register */
+    AT91_REG EMAC_FRO;        /* Frames Received OK Register */
+    AT91_REG EMAC_FCSE;       /* Frame Check Sequence Error Register */
+    AT91_REG EMAC_ALE;        /* Alignment Error Register */
+    AT91_REG EMAC_DTF;        /* Deferred Transmission Frame Register */
+    AT91_REG EMAC_LCOL;       /* Late Collision Register */
+    AT91_REG EMAC_ECOL;       /* Excessive Collision Register */
+    AT91_REG EMAC_TUND;       /* Transmit Underrun Error Register */
+    AT91_REG EMAC_CSE;        /* Carrier Sense Error Register */
+    AT91_REG EMAC_RRE;        /* Receive Ressource Error Register */
+    AT91_REG EMAC_ROV;        /* Receive Overrun Errors Register */
+    AT91_REG EMAC_RSE;        /* Receive Symbol Errors Register */
+    AT91_REG EMAC_ELE;        /* Excessive Length Errors Register */
+    AT91_REG EMAC_RJA;        /* Receive Jabbers Register */
+    AT91_REG EMAC_USF;        /* Undersize Frames Register */
+    AT91_REG EMAC_STE;        /* SQE Test Error Register */
+    AT91_REG EMAC_RLE;        /* Receive Length Field Mismatch Register */
+    AT91_REG EMAC_TPF;        /* Transmitted Pause Frames Register */
+    AT91_REG EMAC_HRB;        /* Hash Address Bottom[31:0] */
+    AT91_REG EMAC_HRT;        /* Hash Address Top[63:32] */
+    AT91_REG EMAC_SA1L;       /* Specific Address 1 Bottom, First 4 bytes */
+    AT91_REG EMAC_SA1H;       /* Specific Address 1 Top, Last 2 bytes */
+    AT91_REG EMAC_SA2L;       /* Specific Address 2 Bottom, First 4 bytes */
+    AT91_REG EMAC_SA2H;       /* Specific Address 2 Top, Last 2 bytes */
+    AT91_REG EMAC_SA3L;       /* Specific Address 3 Bottom, First 4 bytes */
+    AT91_REG EMAC_SA3H;       /* Specific Address 3 Top, Last 2 bytes */
+    AT91_REG EMAC_SA4L;       /* Specific Address 4 Bottom, First 4 bytes */
+    AT91_REG EMAC_SA4H;       /* Specific Address 4 Top, Last 2 bytes */
+    AT91_REG EMAC_TID;        /* Type ID Checking Register */
+    AT91_REG EMAC_TPQ;        /* Transmit Pause Quantum Register */
+    AT91_REG EMAC_USRIO;      /* USER Input/Output Register */
+    AT91_REG EMAC_WOL;        /* Wake On LAN Register */
+    AT91_REG Reserved1[ 13 ]; /* */
+    AT91_REG EMAC_REV;        /* Revision Register */
+} AT91S_EMAC, * AT91PS_EMAC;
 
-// -------- EMAC_NCR : (EMAC Offset: 0x0)  --------
-#define AT91C_EMAC_LB         ((unsigned int) 0x1 <<  0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
-#define AT91C_EMAC_LLB        ((unsigned int) 0x1 <<  1) // (EMAC) Loopback local.
-#define AT91C_EMAC_RE         ((unsigned int) 0x1 <<  2) // (EMAC) Receive enable.
-#define AT91C_EMAC_TE         ((unsigned int) 0x1 <<  3) // (EMAC) Transmit enable.
-#define AT91C_EMAC_MPE        ((unsigned int) 0x1 <<  4) // (EMAC) Management port enable.
-#define AT91C_EMAC_CLRSTAT    ((unsigned int) 0x1 <<  5) // (EMAC) Clear statistics registers.
-#define AT91C_EMAC_INCSTAT    ((unsigned int) 0x1 <<  6) // (EMAC) Increment statistics registers.
-#define AT91C_EMAC_WESTAT     ((unsigned int) 0x1 <<  7) // (EMAC) Write enable for statistics registers.
-#define AT91C_EMAC_BP         ((unsigned int) 0x1 <<  8) // (EMAC) Back pressure.
-#define AT91C_EMAC_TSTART     ((unsigned int) 0x1 <<  9) // (EMAC) Start Transmission.
-#define AT91C_EMAC_THALT      ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt.
-#define AT91C_EMAC_TPFR       ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame
-#define AT91C_EMAC_TZQ        ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame
-// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register --------
-#define AT91C_EMAC_SPD        ((unsigned int) 0x1 <<  0) // (EMAC) Speed.
-#define AT91C_EMAC_FD         ((unsigned int) 0x1 <<  1) // (EMAC) Full duplex.
-#define AT91C_EMAC_JFRAME     ((unsigned int) 0x1 <<  3) // (EMAC) Jumbo Frames.
-#define AT91C_EMAC_CAF        ((unsigned int) 0x1 <<  4) // (EMAC) Copy all frames.
-#define AT91C_EMAC_NBC        ((unsigned int) 0x1 <<  5) // (EMAC) No broadcast.
-#define AT91C_EMAC_MTI        ((unsigned int) 0x1 <<  6) // (EMAC) Multicast hash event enable
-#define AT91C_EMAC_UNI        ((unsigned int) 0x1 <<  7) // (EMAC) Unicast hash enable.
-#define AT91C_EMAC_BIG        ((unsigned int) 0x1 <<  8) // (EMAC) Receive 1522 bytes.
-#define AT91C_EMAC_EAE        ((unsigned int) 0x1 <<  9) // (EMAC) External address match enable.
-#define AT91C_EMAC_CLK        ((unsigned int) 0x3 << 10) // (EMAC)
-#define     AT91C_EMAC_CLK_HCLK_8               ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8
-#define     AT91C_EMAC_CLK_HCLK_16              ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16
-#define     AT91C_EMAC_CLK_HCLK_32              ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32
-#define     AT91C_EMAC_CLK_HCLK_64              ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64
-#define AT91C_EMAC_RTY        ((unsigned int) 0x1 << 12) // (EMAC)
-#define AT91C_EMAC_PAE        ((unsigned int) 0x1 << 13) // (EMAC)
-#define AT91C_EMAC_RBOF       ((unsigned int) 0x3 << 14) // (EMAC)
-#define     AT91C_EMAC_RBOF_OFFSET_0             ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer
-#define     AT91C_EMAC_RBOF_OFFSET_1             ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer
-#define     AT91C_EMAC_RBOF_OFFSET_2             ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
-#define     AT91C_EMAC_RBOF_OFFSET_3             ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
-#define AT91C_EMAC_RLCE       ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable
-#define AT91C_EMAC_DRFCS      ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS
-#define AT91C_EMAC_EFRHD      ((unsigned int) 0x1 << 18) // (EMAC)
-#define AT91C_EMAC_IRXFCS     ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS
-// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register --------
-#define AT91C_EMAC_LINKR      ((unsigned int) 0x1 <<  0) // (EMAC)
-#define AT91C_EMAC_MDIO       ((unsigned int) 0x1 <<  1) // (EMAC)
-#define AT91C_EMAC_IDLE       ((unsigned int) 0x1 <<  2) // (EMAC)
-// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register --------
-#define AT91C_EMAC_UBR        ((unsigned int) 0x1 <<  0) // (EMAC)
-#define AT91C_EMAC_COL        ((unsigned int) 0x1 <<  1) // (EMAC)
-#define AT91C_EMAC_RLES       ((unsigned int) 0x1 <<  2) // (EMAC)
-#define AT91C_EMAC_TGO        ((unsigned int) 0x1 <<  3) // (EMAC) Transmit Go
-#define AT91C_EMAC_BEX        ((unsigned int) 0x1 <<  4) // (EMAC) Buffers exhausted mid frame
-#define AT91C_EMAC_COMP       ((unsigned int) 0x1 <<  5) // (EMAC)
-#define AT91C_EMAC_UND        ((unsigned int) 0x1 <<  6) // (EMAC)
-// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register --------
-#define AT91C_EMAC_BNA        ((unsigned int) 0x1 <<  0) // (EMAC)
-#define AT91C_EMAC_REC        ((unsigned int) 0x1 <<  1) // (EMAC)
-#define AT91C_EMAC_OVR        ((unsigned int) 0x1 <<  2) // (EMAC)
-// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register --------
-#define AT91C_EMAC_MFD        ((unsigned int) 0x1 <<  0) // (EMAC)
-#define AT91C_EMAC_RCOMP      ((unsigned int) 0x1 <<  1) // (EMAC)
-#define AT91C_EMAC_RXUBR      ((unsigned int) 0x1 <<  2) // (EMAC)
-#define AT91C_EMAC_TXUBR      ((unsigned int) 0x1 <<  3) // (EMAC)
-#define AT91C_EMAC_TUNDR      ((unsigned int) 0x1 <<  4) // (EMAC)
-#define AT91C_EMAC_RLEX       ((unsigned int) 0x1 <<  5) // (EMAC)
-#define AT91C_EMAC_TXERR      ((unsigned int) 0x1 <<  6) // (EMAC)
-#define AT91C_EMAC_TCOMP      ((unsigned int) 0x1 <<  7) // (EMAC)
-#define AT91C_EMAC_LINK       ((unsigned int) 0x1 <<  9) // (EMAC)
-#define AT91C_EMAC_ROVR       ((unsigned int) 0x1 << 10) // (EMAC)
-#define AT91C_EMAC_HRESP      ((unsigned int) 0x1 << 11) // (EMAC)
-#define AT91C_EMAC_PFRE       ((unsigned int) 0x1 << 12) // (EMAC)
-#define AT91C_EMAC_PTZ        ((unsigned int) 0x1 << 13) // (EMAC)
-// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register --------
-// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register --------
-// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register --------
-// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register --------
-#define AT91C_EMAC_DATA       ((unsigned int) 0xFFFF <<  0) // (EMAC)
-#define AT91C_EMAC_CODE       ((unsigned int) 0x3 << 16) // (EMAC)
-#define AT91C_EMAC_REGA       ((unsigned int) 0x1F << 18) // (EMAC)
-#define AT91C_EMAC_PHYA       ((unsigned int) 0x1F << 23) // (EMAC)
-#define AT91C_EMAC_RW         ((unsigned int) 0x3 << 28) // (EMAC)
-#define AT91C_EMAC_SOF        ((unsigned int) 0x3 << 30) // (EMAC)
-// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register --------
-#define AT91C_EMAC_RMII       ((unsigned int) 0x1 <<  0) // (EMAC) Reduce MII
-// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register --------
-#define AT91C_EMAC_IP         ((unsigned int) 0xFFFF <<  0) // (EMAC) ARP request IP address
-#define AT91C_EMAC_MAG        ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable
-#define AT91C_EMAC_ARP        ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable
-#define AT91C_EMAC_SA1        ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable
-// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register --------
-#define AT91C_EMAC_REVREF     ((unsigned int) 0xFFFF <<  0) // (EMAC)
-#define AT91C_EMAC_PARTREF    ((unsigned int) 0xFFFF << 16) // (EMAC)
+/* -------- EMAC_NCR : (EMAC Offset: 0x0)  -------- */
+#define AT91C_EMAC_LB                   ( ( unsigned int ) 0x1 << 0 )  /* (EMAC) Loopback. Optional. When set, loopback signal is at high level. */
+#define AT91C_EMAC_LLB                  ( ( unsigned int ) 0x1 << 1 )  /* (EMAC) Loopback local. */
+#define AT91C_EMAC_RE                   ( ( unsigned int ) 0x1 << 2 )  /* (EMAC) Receive enable. */
+#define AT91C_EMAC_TE                   ( ( unsigned int ) 0x1 << 3 )  /* (EMAC) Transmit enable. */
+#define AT91C_EMAC_MPE                  ( ( unsigned int ) 0x1 << 4 )  /* (EMAC) Management port enable. */
+#define AT91C_EMAC_CLRSTAT              ( ( unsigned int ) 0x1 << 5 )  /* (EMAC) Clear statistics registers. */
+#define AT91C_EMAC_INCSTAT              ( ( unsigned int ) 0x1 << 6 )  /* (EMAC) Increment statistics registers. */
+#define AT91C_EMAC_WESTAT               ( ( unsigned int ) 0x1 << 7 )  /* (EMAC) Write enable for statistics registers. */
+#define AT91C_EMAC_BP                   ( ( unsigned int ) 0x1 << 8 )  /* (EMAC) Back pressure. */
+#define AT91C_EMAC_TSTART               ( ( unsigned int ) 0x1 << 9 )  /* (EMAC) Start Transmission. */
+#define AT91C_EMAC_THALT                ( ( unsigned int ) 0x1 << 10 ) /* (EMAC) Transmission Halt. */
+#define AT91C_EMAC_TPFR                 ( ( unsigned int ) 0x1 << 11 ) /* (EMAC) Transmit pause frame */
+#define AT91C_EMAC_TZQ                  ( ( unsigned int ) 0x1 << 12 ) /* (EMAC) Transmit zero quantum pause frame */
+/* -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- */
+#define AT91C_EMAC_SPD                  ( ( unsigned int ) 0x1 << 0 )  /* (EMAC) Speed. */
+#define AT91C_EMAC_FD                   ( ( unsigned int ) 0x1 << 1 )  /* (EMAC) Full duplex. */
+#define AT91C_EMAC_JFRAME               ( ( unsigned int ) 0x1 << 3 )  /* (EMAC) Jumbo Frames. */
+#define AT91C_EMAC_CAF                  ( ( unsigned int ) 0x1 << 4 )  /* (EMAC) Copy all frames. */
+#define AT91C_EMAC_NBC                  ( ( unsigned int ) 0x1 << 5 )  /* (EMAC) No broadcast. */
+#define AT91C_EMAC_MTI                  ( ( unsigned int ) 0x1 << 6 )  /* (EMAC) Multicast hash event enable */
+#define AT91C_EMAC_UNI                  ( ( unsigned int ) 0x1 << 7 )  /* (EMAC) Unicast hash enable. */
+#define AT91C_EMAC_BIG                  ( ( unsigned int ) 0x1 << 8 )  /* (EMAC) Receive 1522 bytes. */
+#define AT91C_EMAC_EAE                  ( ( unsigned int ) 0x1 << 9 )  /* (EMAC) External address match enable. */
+#define AT91C_EMAC_CLK                  ( ( unsigned int ) 0x3 << 10 ) /* (EMAC) */
+#define     AT91C_EMAC_CLK_HCLK_8       ( ( unsigned int ) 0x0 << 10 ) /* (EMAC) HCLK divided by 8 */
+#define     AT91C_EMAC_CLK_HCLK_16      ( ( unsigned int ) 0x1 << 10 ) /* (EMAC) HCLK divided by 16 */
+#define     AT91C_EMAC_CLK_HCLK_32      ( ( unsigned int ) 0x2 << 10 ) /* (EMAC) HCLK divided by 32 */
+#define     AT91C_EMAC_CLK_HCLK_64      ( ( unsigned int ) 0x3 << 10 ) /* (EMAC) HCLK divided by 64 */
+#define AT91C_EMAC_RTY                  ( ( unsigned int ) 0x1 << 12 ) /* (EMAC) */
+#define AT91C_EMAC_PAE                  ( ( unsigned int ) 0x1 << 13 ) /* (EMAC) */
+#define AT91C_EMAC_RBOF                 ( ( unsigned int ) 0x3 << 14 ) /* (EMAC) */
+#define     AT91C_EMAC_RBOF_OFFSET_0    ( ( unsigned int ) 0x0 << 14 ) /* (EMAC) no offset from start of receive buffer */
+#define     AT91C_EMAC_RBOF_OFFSET_1    ( ( unsigned int ) 0x1 << 14 ) /* (EMAC) one byte offset from start of receive buffer */
+#define     AT91C_EMAC_RBOF_OFFSET_2    ( ( unsigned int ) 0x2 << 14 ) /* (EMAC) two bytes offset from start of receive buffer */
+#define     AT91C_EMAC_RBOF_OFFSET_3    ( ( unsigned int ) 0x3 << 14 ) /* (EMAC) three bytes offset from start of receive buffer */
+#define AT91C_EMAC_RLCE                 ( ( unsigned int ) 0x1 << 16 ) /* (EMAC) Receive Length field Checking Enable */
+#define AT91C_EMAC_DRFCS                ( ( unsigned int ) 0x1 << 17 ) /* (EMAC) Discard Receive FCS */
+#define AT91C_EMAC_EFRHD                ( ( unsigned int ) 0x1 << 18 ) /* (EMAC) */
+#define AT91C_EMAC_IRXFCS               ( ( unsigned int ) 0x1 << 19 ) /* (EMAC) Ignore RX FCS */
+/* -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- */
+#define AT91C_EMAC_LINKR                ( ( unsigned int ) 0x1 << 0 )  /* (EMAC) */
+#define AT91C_EMAC_MDIO                 ( ( unsigned int ) 0x1 << 1 )  /* (EMAC) */
+#define AT91C_EMAC_IDLE                 ( ( unsigned int ) 0x1 << 2 )  /* (EMAC) */
+/* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- */
+#define AT91C_EMAC_UBR                  ( ( unsigned int ) 0x1 << 0 )  /* (EMAC) */
+#define AT91C_EMAC_COL                  ( ( unsigned int ) 0x1 << 1 )  /* (EMAC) */
+#define AT91C_EMAC_RLES                 ( ( unsigned int ) 0x1 << 2 )  /* (EMAC) */
+#define AT91C_EMAC_TGO                  ( ( unsigned int ) 0x1 << 3 )  /* (EMAC) Transmit Go */
+#define AT91C_EMAC_BEX                  ( ( unsigned int ) 0x1 << 4 )  /* (EMAC) Buffers exhausted mid frame */
+#define AT91C_EMAC_COMP                 ( ( unsigned int ) 0x1 << 5 )  /* (EMAC) */
+#define AT91C_EMAC_UND                  ( ( unsigned int ) 0x1 << 6 )  /* (EMAC) */
+/* -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- */
+#define AT91C_EMAC_BNA                  ( ( unsigned int ) 0x1 << 0 )  /* (EMAC) */
+#define AT91C_EMAC_REC                  ( ( unsigned int ) 0x1 << 1 )  /* (EMAC) */
+#define AT91C_EMAC_OVR                  ( ( unsigned int ) 0x1 << 2 )  /* (EMAC) */
+/* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- */
+#define AT91C_EMAC_MFD                  ( ( unsigned int ) 0x1 << 0 )  /* (EMAC) */
+#define AT91C_EMAC_RCOMP                ( ( unsigned int ) 0x1 << 1 )  /* (EMAC) */
+#define AT91C_EMAC_RXUBR                ( ( unsigned int ) 0x1 << 2 )  /* (EMAC) */
+#define AT91C_EMAC_TXUBR                ( ( unsigned int ) 0x1 << 3 )  /* (EMAC) */
+#define AT91C_EMAC_TUNDR                ( ( unsigned int ) 0x1 << 4 )  /* (EMAC) */
+#define AT91C_EMAC_RLEX                 ( ( unsigned int ) 0x1 << 5 )  /* (EMAC) */
+#define AT91C_EMAC_TXERR                ( ( unsigned int ) 0x1 << 6 )  /* (EMAC) */
+#define AT91C_EMAC_TCOMP                ( ( unsigned int ) 0x1 << 7 )  /* (EMAC) */
+#define AT91C_EMAC_LINK                 ( ( unsigned int ) 0x1 << 9 )  /* (EMAC) */
+#define AT91C_EMAC_ROVR                 ( ( unsigned int ) 0x1 << 10 ) /* (EMAC) */
+#define AT91C_EMAC_HRESP                ( ( unsigned int ) 0x1 << 11 ) /* (EMAC) */
+#define AT91C_EMAC_PFRE                 ( ( unsigned int ) 0x1 << 12 ) /* (EMAC) */
+#define AT91C_EMAC_PTZ                  ( ( unsigned int ) 0x1 << 13 ) /* (EMAC) */
+/* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- */
+/* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- */
+/* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */
+/* -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- */
+#define AT91C_EMAC_DATA       ( ( unsigned int ) 0xFFFF << 0 )  /* (EMAC) */
+#define AT91C_EMAC_CODE       ( ( unsigned int ) 0x3 << 16 )    /* (EMAC) */
+#define AT91C_EMAC_REGA       ( ( unsigned int ) 0x1F << 18 )   /* (EMAC) */
+#define AT91C_EMAC_PHYA       ( ( unsigned int ) 0x1F << 23 )   /* (EMAC) */
+#define AT91C_EMAC_RW         ( ( unsigned int ) 0x3 << 28 )    /* (EMAC) */
+#define AT91C_EMAC_SOF        ( ( unsigned int ) 0x3 << 30 )    /* (EMAC) */
+/* -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- */
+#define AT91C_EMAC_RMII       ( ( unsigned int ) 0x1 << 0 )     /* (EMAC) Reduce MII */
+/* -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- */
+#define AT91C_EMAC_IP         ( ( unsigned int ) 0xFFFF << 0 )  /* (EMAC) ARP request IP address */
+#define AT91C_EMAC_MAG        ( ( unsigned int ) 0x1 << 16 )    /* (EMAC) Magic packet event enable */
+#define AT91C_EMAC_ARP        ( ( unsigned int ) 0x1 << 17 )    /* (EMAC) ARP request event enable */
+#define AT91C_EMAC_SA1        ( ( unsigned int ) 0x1 << 18 )    /* (EMAC) Specific address register 1 event enable */
+/* -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- */
+#define AT91C_EMAC_REVREF     ( ( unsigned int ) 0xFFFF << 0 )  /* (EMAC) */
+#define AT91C_EMAC_PARTREF    ( ( unsigned int ) 0xFFFF << 16 ) /* (EMAC) */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
-// *****************************************************************************
-typedef struct _AT91S_ADC {
-    AT91_REG     ADC_CR;    // ADC Control Register
-    AT91_REG     ADC_MR;    // ADC Mode Register
-    AT91_REG     Reserved0[2];  //
-    AT91_REG     ADC_CHER;  // ADC Channel Enable Register
-    AT91_REG     ADC_CHDR;  // ADC Channel Disable Register
-    AT91_REG     ADC_CHSR;  // ADC Channel Status Register
-    AT91_REG     ADC_SR;    // ADC Status Register
-    AT91_REG     ADC_LCDR;  // ADC Last Converted Data Register
-    AT91_REG     ADC_IER;   // ADC Interrupt Enable Register
-    AT91_REG     ADC_IDR;   // ADC Interrupt Disable Register
-    AT91_REG     ADC_IMR;   // ADC Interrupt Mask Register
-    AT91_REG     ADC_CDR0;  // ADC Channel Data Register 0
-    AT91_REG     ADC_CDR1;  // ADC Channel Data Register 1
-    AT91_REG     ADC_CDR2;  // ADC Channel Data Register 2
-    AT91_REG     ADC_CDR3;  // ADC Channel Data Register 3
-    AT91_REG     ADC_CDR4;  // ADC Channel Data Register 4
-    AT91_REG     ADC_CDR5;  // ADC Channel Data Register 5
-    AT91_REG     ADC_CDR6;  // ADC Channel Data Register 6
-    AT91_REG     ADC_CDR7;  // ADC Channel Data Register 7
-    AT91_REG     Reserved1[44];     //
-    AT91_REG     ADC_RPR;   // Receive Pointer Register
-    AT91_REG     ADC_RCR;   // Receive Counter Register
-    AT91_REG     ADC_TPR;   // Transmit Pointer Register
-    AT91_REG     ADC_TCR;   // Transmit Counter Register
-    AT91_REG     ADC_RNPR;  // Receive Next Pointer Register
-    AT91_REG     ADC_RNCR;  // Receive Next Counter Register
-    AT91_REG     ADC_TNPR;  // Transmit Next Pointer Register
-    AT91_REG     ADC_TNCR;  // Transmit Next Counter Register
-    AT91_REG     ADC_PTCR;  // PDC Transfer Control Register
-    AT91_REG     ADC_PTSR;  // PDC Transfer Status Register
-} AT91S_ADC, *AT91PS_ADC;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor */
+/* ***************************************************************************** */
+typedef struct _AT91S_ADC
+{
+    AT91_REG ADC_CR;          /* ADC Control Register */
+    AT91_REG ADC_MR;          /* ADC Mode Register */
+    AT91_REG Reserved0[ 2 ];  /* */
+    AT91_REG ADC_CHER;        /* ADC Channel Enable Register */
+    AT91_REG ADC_CHDR;        /* ADC Channel Disable Register */
+    AT91_REG ADC_CHSR;        /* ADC Channel Status Register */
+    AT91_REG ADC_SR;          /* ADC Status Register */
+    AT91_REG ADC_LCDR;        /* ADC Last Converted Data Register */
+    AT91_REG ADC_IER;         /* ADC Interrupt Enable Register */
+    AT91_REG ADC_IDR;         /* ADC Interrupt Disable Register */
+    AT91_REG ADC_IMR;         /* ADC Interrupt Mask Register */
+    AT91_REG ADC_CDR0;        /* ADC Channel Data Register 0 */
+    AT91_REG ADC_CDR1;        /* ADC Channel Data Register 1 */
+    AT91_REG ADC_CDR2;        /* ADC Channel Data Register 2 */
+    AT91_REG ADC_CDR3;        /* ADC Channel Data Register 3 */
+    AT91_REG ADC_CDR4;        /* ADC Channel Data Register 4 */
+    AT91_REG ADC_CDR5;        /* ADC Channel Data Register 5 */
+    AT91_REG ADC_CDR6;        /* ADC Channel Data Register 6 */
+    AT91_REG ADC_CDR7;        /* ADC Channel Data Register 7 */
+    AT91_REG Reserved1[ 44 ]; /* */
+    AT91_REG ADC_RPR;         /* Receive Pointer Register */
+    AT91_REG ADC_RCR;         /* Receive Counter Register */
+    AT91_REG ADC_TPR;         /* Transmit Pointer Register */
+    AT91_REG ADC_TCR;         /* Transmit Counter Register */
+    AT91_REG ADC_RNPR;        /* Receive Next Pointer Register */
+    AT91_REG ADC_RNCR;        /* Receive Next Counter Register */
+    AT91_REG ADC_TNPR;        /* Transmit Next Pointer Register */
+    AT91_REG ADC_TNCR;        /* Transmit Next Counter Register */
+    AT91_REG ADC_PTCR;        /* PDC Transfer Control Register */
+    AT91_REG ADC_PTSR;        /* PDC Transfer Status Register */
+} AT91S_ADC, * AT91PS_ADC;
 
-// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
-#define AT91C_ADC_SWRST       ((unsigned int) 0x1 <<  0) // (ADC) Software Reset
-#define AT91C_ADC_START       ((unsigned int) 0x1 <<  1) // (ADC) Start Conversion
-// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
-#define AT91C_ADC_TRGEN       ((unsigned int) 0x1 <<  0) // (ADC) Trigger Enable
-#define     AT91C_ADC_TRGEN_DIS                  ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
-#define     AT91C_ADC_TRGEN_EN                   ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
-#define AT91C_ADC_TRGSEL      ((unsigned int) 0x7 <<  1) // (ADC) Trigger Selection
-#define     AT91C_ADC_TRGSEL_TIOA0                ((unsigned int) 0x0 <<  1) // (ADC) Selected TRGSEL = TIAO0
-#define     AT91C_ADC_TRGSEL_TIOA1                ((unsigned int) 0x1 <<  1) // (ADC) Selected TRGSEL = TIAO1
-#define     AT91C_ADC_TRGSEL_TIOA2                ((unsigned int) 0x2 <<  1) // (ADC) Selected TRGSEL = TIAO2
-#define     AT91C_ADC_TRGSEL_TIOA3                ((unsigned int) 0x3 <<  1) // (ADC) Selected TRGSEL = TIAO3
-#define     AT91C_ADC_TRGSEL_TIOA4                ((unsigned int) 0x4 <<  1) // (ADC) Selected TRGSEL = TIAO4
-#define     AT91C_ADC_TRGSEL_TIOA5                ((unsigned int) 0x5 <<  1) // (ADC) Selected TRGSEL = TIAO5
-#define     AT91C_ADC_TRGSEL_EXT                  ((unsigned int) 0x6 <<  1) // (ADC) Selected TRGSEL = External Trigger
-#define AT91C_ADC_LOWRES      ((unsigned int) 0x1 <<  4) // (ADC) Resolution.
-#define     AT91C_ADC_LOWRES_10_BIT               ((unsigned int) 0x0 <<  4) // (ADC) 10-bit resolution
-#define     AT91C_ADC_LOWRES_8_BIT                ((unsigned int) 0x1 <<  4) // (ADC) 8-bit resolution
-#define AT91C_ADC_SLEEP       ((unsigned int) 0x1 <<  5) // (ADC) Sleep Mode
-#define     AT91C_ADC_SLEEP_NORMAL_MODE          ((unsigned int) 0x0 <<  5) // (ADC) Normal Mode
-#define     AT91C_ADC_SLEEP_MODE                 ((unsigned int) 0x1 <<  5) // (ADC) Sleep Mode
-#define AT91C_ADC_PRESCAL     ((unsigned int) 0x3F <<  8) // (ADC) Prescaler rate selection
-#define AT91C_ADC_STARTUP     ((unsigned int) 0x1F << 16) // (ADC) Startup Time
-#define AT91C_ADC_SHTIM       ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time
-// --------     ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
-#define AT91C_ADC_CH0         ((unsigned int) 0x1 <<  0) // (ADC) Channel 0
-#define AT91C_ADC_CH1         ((unsigned int) 0x1 <<  1) // (ADC) Channel 1
-#define AT91C_ADC_CH2         ((unsigned int) 0x1 <<  2) // (ADC) Channel 2
-#define AT91C_ADC_CH3         ((unsigned int) 0x1 <<  3) // (ADC) Channel 3
-#define AT91C_ADC_CH4         ((unsigned int) 0x1 <<  4) // (ADC) Channel 4
-#define AT91C_ADC_CH5         ((unsigned int) 0x1 <<  5) // (ADC) Channel 5
-#define AT91C_ADC_CH6         ((unsigned int) 0x1 <<  6) // (ADC) Channel 6
-#define AT91C_ADC_CH7         ((unsigned int) 0x1 <<  7) // (ADC) Channel 7
-// --------     ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
-// --------     ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
-// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
-#define AT91C_ADC_EOC0        ((unsigned int) 0x1 <<  0) // (ADC) End of Conversion
-#define AT91C_ADC_EOC1        ((unsigned int) 0x1 <<  1) // (ADC) End of Conversion
-#define AT91C_ADC_EOC2        ((unsigned int) 0x1 <<  2) // (ADC) End of Conversion
-#define AT91C_ADC_EOC3        ((unsigned int) 0x1 <<  3) // (ADC) End of Conversion
-#define AT91C_ADC_EOC4        ((unsigned int) 0x1 <<  4) // (ADC) End of Conversion
-#define AT91C_ADC_EOC5        ((unsigned int) 0x1 <<  5) // (ADC) End of Conversion
-#define AT91C_ADC_EOC6        ((unsigned int) 0x1 <<  6) // (ADC) End of Conversion
-#define AT91C_ADC_EOC7        ((unsigned int) 0x1 <<  7) // (ADC) End of Conversion
-#define AT91C_ADC_OVRE0       ((unsigned int) 0x1 <<  8) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE1       ((unsigned int) 0x1 <<  9) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE2       ((unsigned int) 0x1 << 10) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE3       ((unsigned int) 0x1 << 11) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE4       ((unsigned int) 0x1 << 12) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE5       ((unsigned int) 0x1 << 13) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE6       ((unsigned int) 0x1 << 14) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE7       ((unsigned int) 0x1 << 15) // (ADC) Overrun Error
-#define AT91C_ADC_DRDY        ((unsigned int) 0x1 << 16) // (ADC) Data Ready
-#define AT91C_ADC_GOVRE       ((unsigned int) 0x1 << 17) // (ADC) General Overrun
-#define AT91C_ADC_ENDRX       ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer
-#define AT91C_ADC_RXBUFF      ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt
-// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
-#define AT91C_ADC_LDATA       ((unsigned int) 0x3FF <<  0) // (ADC) Last Data Converted
-// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
-// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
-// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
-// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
-#define AT91C_ADC_DATA        ((unsigned int) 0x3FF <<  0) // (ADC) Converted Data
-// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
-// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
-// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
-// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
-// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
-// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
-// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
+/* -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- */
+#define AT91C_ADC_SWRST                    ( ( unsigned int ) 0x1 << 0 )   /* (ADC) Software Reset */
+#define AT91C_ADC_START                    ( ( unsigned int ) 0x1 << 1 )   /* (ADC) Start Conversion */
+/* -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- */
+#define AT91C_ADC_TRGEN                    ( ( unsigned int ) 0x1 << 0 )   /* (ADC) Trigger Enable */
+#define     AT91C_ADC_TRGEN_DIS            ( ( unsigned int ) 0x0 )        /* (ADC) Hardware triggers are disabled. Starting a conversion is only possible by software */
+#define     AT91C_ADC_TRGEN_EN             ( ( unsigned int ) 0x1 )        /* (ADC) Hardware trigger selected by TRGSEL field is enabled. */
+#define AT91C_ADC_TRGSEL                   ( ( unsigned int ) 0x7 << 1 )   /* (ADC) Trigger Selection */
+#define     AT91C_ADC_TRGSEL_TIOA0         ( ( unsigned int ) 0x0 << 1 )   /* (ADC) Selected TRGSEL = TIAO0 */
+#define     AT91C_ADC_TRGSEL_TIOA1         ( ( unsigned int ) 0x1 << 1 )   /* (ADC) Selected TRGSEL = TIAO1 */
+#define     AT91C_ADC_TRGSEL_TIOA2         ( ( unsigned int ) 0x2 << 1 )   /* (ADC) Selected TRGSEL = TIAO2 */
+#define     AT91C_ADC_TRGSEL_TIOA3         ( ( unsigned int ) 0x3 << 1 )   /* (ADC) Selected TRGSEL = TIAO3 */
+#define     AT91C_ADC_TRGSEL_TIOA4         ( ( unsigned int ) 0x4 << 1 )   /* (ADC) Selected TRGSEL = TIAO4 */
+#define     AT91C_ADC_TRGSEL_TIOA5         ( ( unsigned int ) 0x5 << 1 )   /* (ADC) Selected TRGSEL = TIAO5 */
+#define     AT91C_ADC_TRGSEL_EXT           ( ( unsigned int ) 0x6 << 1 )   /* (ADC) Selected TRGSEL = External Trigger */
+#define AT91C_ADC_LOWRES                   ( ( unsigned int ) 0x1 << 4 )   /* (ADC) Resolution. */
+#define     AT91C_ADC_LOWRES_10_BIT        ( ( unsigned int ) 0x0 << 4 )   /* (ADC) 10-bit resolution */
+#define     AT91C_ADC_LOWRES_8_BIT         ( ( unsigned int ) 0x1 << 4 )   /* (ADC) 8-bit resolution */
+#define AT91C_ADC_SLEEP                    ( ( unsigned int ) 0x1 << 5 )   /* (ADC) Sleep Mode */
+#define     AT91C_ADC_SLEEP_NORMAL_MODE    ( ( unsigned int ) 0x0 << 5 )   /* (ADC) Normal Mode */
+#define     AT91C_ADC_SLEEP_MODE           ( ( unsigned int ) 0x1 << 5 )   /* (ADC) Sleep Mode */
+#define AT91C_ADC_PRESCAL                  ( ( unsigned int ) 0x3F << 8 )  /* (ADC) Prescaler rate selection */
+#define AT91C_ADC_STARTUP                  ( ( unsigned int ) 0x1F << 16 ) /* (ADC) Startup Time */
+#define AT91C_ADC_SHTIM                    ( ( unsigned int ) 0xF << 24 )  /* (ADC) Sample & Hold Time */
+/* --------     ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- */
+#define AT91C_ADC_CH0                      ( ( unsigned int ) 0x1 << 0 )   /* (ADC) Channel 0 */
+#define AT91C_ADC_CH1                      ( ( unsigned int ) 0x1 << 1 )   /* (ADC) Channel 1 */
+#define AT91C_ADC_CH2                      ( ( unsigned int ) 0x1 << 2 )   /* (ADC) Channel 2 */
+#define AT91C_ADC_CH3                      ( ( unsigned int ) 0x1 << 3 )   /* (ADC) Channel 3 */
+#define AT91C_ADC_CH4                      ( ( unsigned int ) 0x1 << 4 )   /* (ADC) Channel 4 */
+#define AT91C_ADC_CH5                      ( ( unsigned int ) 0x1 << 5 )   /* (ADC) Channel 5 */
+#define AT91C_ADC_CH6                      ( ( unsigned int ) 0x1 << 6 )   /* (ADC) Channel 6 */
+#define AT91C_ADC_CH7                      ( ( unsigned int ) 0x1 << 7 )   /* (ADC) Channel 7 */
+/* --------     ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- */
+/* --------     ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- */
+/* -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- */
+#define AT91C_ADC_EOC0      ( ( unsigned int ) 0x1 << 0 )   /* (ADC) End of Conversion */
+#define AT91C_ADC_EOC1      ( ( unsigned int ) 0x1 << 1 )   /* (ADC) End of Conversion */
+#define AT91C_ADC_EOC2      ( ( unsigned int ) 0x1 << 2 )   /* (ADC) End of Conversion */
+#define AT91C_ADC_EOC3      ( ( unsigned int ) 0x1 << 3 )   /* (ADC) End of Conversion */
+#define AT91C_ADC_EOC4      ( ( unsigned int ) 0x1 << 4 )   /* (ADC) End of Conversion */
+#define AT91C_ADC_EOC5      ( ( unsigned int ) 0x1 << 5 )   /* (ADC) End of Conversion */
+#define AT91C_ADC_EOC6      ( ( unsigned int ) 0x1 << 6 )   /* (ADC) End of Conversion */
+#define AT91C_ADC_EOC7      ( ( unsigned int ) 0x1 << 7 )   /* (ADC) End of Conversion */
+#define AT91C_ADC_OVRE0     ( ( unsigned int ) 0x1 << 8 )   /* (ADC) Overrun Error */
+#define AT91C_ADC_OVRE1     ( ( unsigned int ) 0x1 << 9 )   /* (ADC) Overrun Error */
+#define AT91C_ADC_OVRE2     ( ( unsigned int ) 0x1 << 10 )  /* (ADC) Overrun Error */
+#define AT91C_ADC_OVRE3     ( ( unsigned int ) 0x1 << 11 )  /* (ADC) Overrun Error */
+#define AT91C_ADC_OVRE4     ( ( unsigned int ) 0x1 << 12 )  /* (ADC) Overrun Error */
+#define AT91C_ADC_OVRE5     ( ( unsigned int ) 0x1 << 13 )  /* (ADC) Overrun Error */
+#define AT91C_ADC_OVRE6     ( ( unsigned int ) 0x1 << 14 )  /* (ADC) Overrun Error */
+#define AT91C_ADC_OVRE7     ( ( unsigned int ) 0x1 << 15 )  /* (ADC) Overrun Error */
+#define AT91C_ADC_DRDY      ( ( unsigned int ) 0x1 << 16 )  /* (ADC) Data Ready */
+#define AT91C_ADC_GOVRE     ( ( unsigned int ) 0x1 << 17 )  /* (ADC) General Overrun */
+#define AT91C_ADC_ENDRX     ( ( unsigned int ) 0x1 << 18 )  /* (ADC) End of Receiver Transfer */
+#define AT91C_ADC_RXBUFF    ( ( unsigned int ) 0x1 << 19 )  /* (ADC) RXBUFF Interrupt */
+/* -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- */
+#define AT91C_ADC_LDATA     ( ( unsigned int ) 0x3FF << 0 ) /* (ADC) Last Data Converted */
+/* -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- */
+/* -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- */
+/* -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- */
+/* -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- */
+#define AT91C_ADC_DATA    ( ( unsigned int ) 0x3FF << 0 )  /* (ADC) Converted Data */
+/* -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- */
+/* -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- */
+/* -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- */
+/* -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- */
+/* -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- */
+/* -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- */
+/* -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Advanced  Encryption Standard
-// *****************************************************************************
-typedef struct _AT91S_AES {
-    AT91_REG     AES_CR;    // Control Register
-    AT91_REG     AES_MR;    // Mode Register
-    AT91_REG     Reserved0[2];  //
-    AT91_REG     AES_IER;   // Interrupt Enable Register
-    AT91_REG     AES_IDR;   // Interrupt Disable Register
-    AT91_REG     AES_IMR;   // Interrupt Mask Register
-    AT91_REG     AES_ISR;   // Interrupt Status Register
-    AT91_REG     AES_KEYWxR[4];     // Key Word x Register
-    AT91_REG     Reserved1[4];  //
-    AT91_REG     AES_IDATAxR[4];    // Input Data x Register
-    AT91_REG     AES_ODATAxR[4];    // Output Data x Register
-    AT91_REG     AES_IVxR[4];   // Initialization Vector x Register
-    AT91_REG     Reserved2[35];     //
-    AT91_REG     AES_VR;    // AES Version Register
-    AT91_REG     AES_RPR;   // Receive Pointer Register
-    AT91_REG     AES_RCR;   // Receive Counter Register
-    AT91_REG     AES_TPR;   // Transmit Pointer Register
-    AT91_REG     AES_TCR;   // Transmit Counter Register
-    AT91_REG     AES_RNPR;  // Receive Next Pointer Register
-    AT91_REG     AES_RNCR;  // Receive Next Counter Register
-    AT91_REG     AES_TNPR;  // Transmit Next Pointer Register
-    AT91_REG     AES_TNCR;  // Transmit Next Counter Register
-    AT91_REG     AES_PTCR;  // PDC Transfer Control Register
-    AT91_REG     AES_PTSR;  // PDC Transfer Status Register
-} AT91S_AES, *AT91PS_AES;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Advanced  Encryption Standard */
+/* ***************************************************************************** */
+typedef struct _AT91S_AES
+{
+    AT91_REG AES_CR;           /* Control Register */
+    AT91_REG AES_MR;           /* Mode Register */
+    AT91_REG Reserved0[ 2 ];   /* */
+    AT91_REG AES_IER;          /* Interrupt Enable Register */
+    AT91_REG AES_IDR;          /* Interrupt Disable Register */
+    AT91_REG AES_IMR;          /* Interrupt Mask Register */
+    AT91_REG AES_ISR;          /* Interrupt Status Register */
+    AT91_REG AES_KEYWxR[ 4 ];  /* Key Word x Register */
+    AT91_REG Reserved1[ 4 ];   /* */
+    AT91_REG AES_IDATAxR[ 4 ]; /* Input Data x Register */
+    AT91_REG AES_ODATAxR[ 4 ]; /* Output Data x Register */
+    AT91_REG AES_IVxR[ 4 ];    /* Initialization Vector x Register */
+    AT91_REG Reserved2[ 35 ];  /* */
+    AT91_REG AES_VR;           /* AES Version Register */
+    AT91_REG AES_RPR;          /* Receive Pointer Register */
+    AT91_REG AES_RCR;          /* Receive Counter Register */
+    AT91_REG AES_TPR;          /* Transmit Pointer Register */
+    AT91_REG AES_TCR;          /* Transmit Counter Register */
+    AT91_REG AES_RNPR;         /* Receive Next Pointer Register */
+    AT91_REG AES_RNCR;         /* Receive Next Counter Register */
+    AT91_REG AES_TNPR;         /* Transmit Next Pointer Register */
+    AT91_REG AES_TNCR;         /* Transmit Next Counter Register */
+    AT91_REG AES_PTCR;         /* PDC Transfer Control Register */
+    AT91_REG AES_PTSR;         /* PDC Transfer Status Register */
+} AT91S_AES, * AT91PS_AES;
 
-// -------- AES_CR : (AES Offset: 0x0) Control Register --------
-#define AT91C_AES_START       ((unsigned int) 0x1 <<  0) // (AES) Starts Processing
-#define AT91C_AES_SWRST       ((unsigned int) 0x1 <<  8) // (AES) Software Reset
-#define AT91C_AES_LOADSEED    ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading
-// -------- AES_MR : (AES Offset: 0x4) Mode Register --------
-#define AT91C_AES_CIPHER      ((unsigned int) 0x1 <<  0) // (AES) Processing Mode
-#define AT91C_AES_PROCDLY     ((unsigned int) 0xF <<  4) // (AES) Processing Delay
-#define AT91C_AES_SMOD        ((unsigned int) 0x3 <<  8) // (AES) Start Mode
-#define     AT91C_AES_SMOD_MANUAL               ((unsigned int) 0x0 <<  8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.
-#define     AT91C_AES_SMOD_AUTO                 ((unsigned int) 0x1 <<  8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).
-#define     AT91C_AES_SMOD_PDC                  ((unsigned int) 0x2 <<  8) // (AES) PDC Mode (cf datasheet).
-#define AT91C_AES_OPMOD       ((unsigned int) 0x7 << 12) // (AES) Operation Mode
-#define     AT91C_AES_OPMOD_ECB                  ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode.
-#define     AT91C_AES_OPMOD_CBC                  ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode.
-#define     AT91C_AES_OPMOD_OFB                  ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode.
-#define     AT91C_AES_OPMOD_CFB                  ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode.
-#define     AT91C_AES_OPMOD_CTR                  ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode.
-#define AT91C_AES_LOD         ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode
-#define AT91C_AES_CFBS        ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size
-#define     AT91C_AES_CFBS_128_BIT              ((unsigned int) 0x0 << 16) // (AES) 128-bit.
-#define     AT91C_AES_CFBS_64_BIT               ((unsigned int) 0x1 << 16) // (AES) 64-bit.
-#define     AT91C_AES_CFBS_32_BIT               ((unsigned int) 0x2 << 16) // (AES) 32-bit.
-#define     AT91C_AES_CFBS_16_BIT               ((unsigned int) 0x3 << 16) // (AES) 16-bit.
-#define     AT91C_AES_CFBS_8_BIT                ((unsigned int) 0x4 << 16) // (AES) 8-bit.
-#define AT91C_AES_CKEY        ((unsigned int) 0xF << 20) // (AES) Countermeasure Key
-#define AT91C_AES_CTYPE       ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type
-#define     AT91C_AES_CTYPE_TYPE1_EN             ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled.
-#define     AT91C_AES_CTYPE_TYPE2_EN             ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled.
-#define     AT91C_AES_CTYPE_TYPE3_EN             ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled.
-#define     AT91C_AES_CTYPE_TYPE4_EN             ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled.
-#define     AT91C_AES_CTYPE_TYPE5_EN             ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled.
-// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register --------
-#define AT91C_AES_DATRDY      ((unsigned int) 0x1 <<  0) // (AES) DATRDY
-#define AT91C_AES_ENDRX       ((unsigned int) 0x1 <<  1) // (AES) PDC Read Buffer End
-#define AT91C_AES_ENDTX       ((unsigned int) 0x1 <<  2) // (AES) PDC Write Buffer End
-#define AT91C_AES_RXBUFF      ((unsigned int) 0x1 <<  3) // (AES) PDC Read Buffer Full
-#define AT91C_AES_TXBUFE      ((unsigned int) 0x1 <<  4) // (AES) PDC Write Buffer Empty
-#define AT91C_AES_URAD        ((unsigned int) 0x1 <<  8) // (AES) Unspecified Register Access Detection
-// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register --------
-// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register --------
-// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register --------
-#define AT91C_AES_URAT        ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status
-#define     AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode.
-#define     AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing.
-#define     AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing.
-#define     AT91C_AES_URAT_OUT_DAT_READ_SUBKEY  ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation.
-#define     AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation.
-#define     AT91C_AES_URAT_WO_REG_READ          ((unsigned int) 0x5 << 12) // (AES) Write-only register read access.
+/* -------- AES_CR : (AES Offset: 0x0) Control Register -------- */
+#define AT91C_AES_START                 ( ( unsigned int ) 0x1 << 0 )   /* (AES) Starts Processing */
+#define AT91C_AES_SWRST                 ( ( unsigned int ) 0x1 << 8 )   /* (AES) Software Reset */
+#define AT91C_AES_LOADSEED              ( ( unsigned int ) 0x1 << 16 )  /* (AES) Random Number Generator Seed Loading */
+/* -------- AES_MR : (AES Offset: 0x4) Mode Register -------- */
+#define AT91C_AES_CIPHER                ( ( unsigned int ) 0x1 << 0 )   /* (AES) Processing Mode */
+#define AT91C_AES_PROCDLY               ( ( unsigned int ) 0xF << 4 )   /* (AES) Processing Delay */
+#define AT91C_AES_SMOD                  ( ( unsigned int ) 0x3 << 8 )   /* (AES) Start Mode */
+#define     AT91C_AES_SMOD_MANUAL       ( ( unsigned int ) 0x0 << 8 )   /* (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. */
+#define     AT91C_AES_SMOD_AUTO         ( ( unsigned int ) 0x1 << 8 )   /* (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). */
+#define     AT91C_AES_SMOD_PDC          ( ( unsigned int ) 0x2 << 8 )   /* (AES) PDC Mode (cf datasheet). */
+#define AT91C_AES_OPMOD                 ( ( unsigned int ) 0x7 << 12 )  /* (AES) Operation Mode */
+#define     AT91C_AES_OPMOD_ECB         ( ( unsigned int ) 0x0 << 12 )  /* (AES) ECB Electronic CodeBook mode. */
+#define     AT91C_AES_OPMOD_CBC         ( ( unsigned int ) 0x1 << 12 )  /* (AES) CBC Cipher Block Chaining mode. */
+#define     AT91C_AES_OPMOD_OFB         ( ( unsigned int ) 0x2 << 12 )  /* (AES) OFB Output Feedback mode. */
+#define     AT91C_AES_OPMOD_CFB         ( ( unsigned int ) 0x3 << 12 )  /* (AES) CFB Cipher Feedback mode. */
+#define     AT91C_AES_OPMOD_CTR         ( ( unsigned int ) 0x4 << 12 )  /* (AES) CTR Counter mode. */
+#define AT91C_AES_LOD                   ( ( unsigned int ) 0x1 << 15 )  /* (AES) Last Output Data Mode */
+#define AT91C_AES_CFBS                  ( ( unsigned int ) 0x7 << 16 )  /* (AES) Cipher Feedback Data Size */
+#define     AT91C_AES_CFBS_128_BIT      ( ( unsigned int ) 0x0 << 16 )  /* (AES) 128-bit. */
+#define     AT91C_AES_CFBS_64_BIT       ( ( unsigned int ) 0x1 << 16 )  /* (AES) 64-bit. */
+#define     AT91C_AES_CFBS_32_BIT       ( ( unsigned int ) 0x2 << 16 )  /* (AES) 32-bit. */
+#define     AT91C_AES_CFBS_16_BIT       ( ( unsigned int ) 0x3 << 16 )  /* (AES) 16-bit. */
+#define     AT91C_AES_CFBS_8_BIT        ( ( unsigned int ) 0x4 << 16 )  /* (AES) 8-bit. */
+#define AT91C_AES_CKEY                  ( ( unsigned int ) 0xF << 20 )  /* (AES) Countermeasure Key */
+#define AT91C_AES_CTYPE                 ( ( unsigned int ) 0x1F << 24 ) /* (AES) Countermeasure Type */
+#define     AT91C_AES_CTYPE_TYPE1_EN    ( ( unsigned int ) 0x1 << 24 )  /* (AES) Countermeasure type 1 is enabled. */
+#define     AT91C_AES_CTYPE_TYPE2_EN    ( ( unsigned int ) 0x2 << 24 )  /* (AES) Countermeasure type 2 is enabled. */
+#define     AT91C_AES_CTYPE_TYPE3_EN    ( ( unsigned int ) 0x4 << 24 )  /* (AES) Countermeasure type 3 is enabled. */
+#define     AT91C_AES_CTYPE_TYPE4_EN    ( ( unsigned int ) 0x8 << 24 )  /* (AES) Countermeasure type 4 is enabled. */
+#define     AT91C_AES_CTYPE_TYPE5_EN    ( ( unsigned int ) 0x10 << 24 ) /* (AES) Countermeasure type 5 is enabled. */
+/* -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- */
+#define AT91C_AES_DATRDY                ( ( unsigned int ) 0x1 << 0 )   /* (AES) DATRDY */
+#define AT91C_AES_ENDRX                 ( ( unsigned int ) 0x1 << 1 )   /* (AES) PDC Read Buffer End */
+#define AT91C_AES_ENDTX                 ( ( unsigned int ) 0x1 << 2 )   /* (AES) PDC Write Buffer End */
+#define AT91C_AES_RXBUFF                ( ( unsigned int ) 0x1 << 3 )   /* (AES) PDC Read Buffer Full */
+#define AT91C_AES_TXBUFE                ( ( unsigned int ) 0x1 << 4 )   /* (AES) PDC Write Buffer Empty */
+#define AT91C_AES_URAD                  ( ( unsigned int ) 0x1 << 8 )   /* (AES) Unspecified Register Access Detection */
+/* -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- */
+/* -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- */
+/* -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- */
+#define AT91C_AES_URAT                              ( ( unsigned int ) 0x7 << 12 ) /* (AES) Unspecified Register Access Type Status */
+#define     AT91C_AES_URAT_IN_DAT_WRITE_DATPROC     ( ( unsigned int ) 0x0 << 12 ) /* (AES) Input data register written during the data processing in PDC mode. */
+#define     AT91C_AES_URAT_OUT_DAT_READ_DATPROC     ( ( unsigned int ) 0x1 << 12 ) /* (AES) Output data register read during the data processing. */
+#define     AT91C_AES_URAT_MODEREG_WRITE_DATPROC    ( ( unsigned int ) 0x2 << 12 ) /* (AES) Mode register written during the data processing. */
+#define     AT91C_AES_URAT_OUT_DAT_READ_SUBKEY      ( ( unsigned int ) 0x3 << 12 ) /* (AES) Output data register read during the sub-keys generation. */
+#define     AT91C_AES_URAT_MODEREG_WRITE_SUBKEY     ( ( unsigned int ) 0x4 << 12 ) /* (AES) Mode register written during the sub-keys generation. */
+#define     AT91C_AES_URAT_WO_REG_READ              ( ( unsigned int ) 0x5 << 12 ) /* (AES) Write-only register read access. */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Triple Data Encryption Standard
-// *****************************************************************************
-typedef struct _AT91S_TDES {
-    AT91_REG     TDES_CR;   // Control Register
-    AT91_REG     TDES_MR;   // Mode Register
-    AT91_REG     Reserved0[2];  //
-    AT91_REG     TDES_IER;  // Interrupt Enable Register
-    AT91_REG     TDES_IDR;  // Interrupt Disable Register
-    AT91_REG     TDES_IMR;  // Interrupt Mask Register
-    AT91_REG     TDES_ISR;  // Interrupt Status Register
-    AT91_REG     TDES_KEY1WxR[2];   // Key 1 Word x Register
-    AT91_REG     TDES_KEY2WxR[2];   // Key 2 Word x Register
-    AT91_REG     TDES_KEY3WxR[2];   // Key 3 Word x Register
-    AT91_REG     Reserved1[2];  //
-    AT91_REG     TDES_IDATAxR[2];   // Input Data x Register
-    AT91_REG     Reserved2[2];  //
-    AT91_REG     TDES_ODATAxR[2];   // Output Data x Register
-    AT91_REG     Reserved3[2];  //
-    AT91_REG     TDES_IVxR[2];  // Initialization Vector x Register
-    AT91_REG     Reserved4[37];     //
-    AT91_REG     TDES_VR;   // TDES Version Register
-    AT91_REG     TDES_RPR;  // Receive Pointer Register
-    AT91_REG     TDES_RCR;  // Receive Counter Register
-    AT91_REG     TDES_TPR;  // Transmit Pointer Register
-    AT91_REG     TDES_TCR;  // Transmit Counter Register
-    AT91_REG     TDES_RNPR;     // Receive Next Pointer Register
-    AT91_REG     TDES_RNCR;     // Receive Next Counter Register
-    AT91_REG     TDES_TNPR;     // Transmit Next Pointer Register
-    AT91_REG     TDES_TNCR;     // Transmit Next Counter Register
-    AT91_REG     TDES_PTCR;     // PDC Transfer Control Register
-    AT91_REG     TDES_PTSR;     // PDC Transfer Status Register
-} AT91S_TDES, *AT91PS_TDES;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Triple Data Encryption Standard */
+/* ***************************************************************************** */
+typedef struct _AT91S_TDES
+{
+    AT91_REG TDES_CR;           /* Control Register */
+    AT91_REG TDES_MR;           /* Mode Register */
+    AT91_REG Reserved0[ 2 ];    /* */
+    AT91_REG TDES_IER;          /* Interrupt Enable Register */
+    AT91_REG TDES_IDR;          /* Interrupt Disable Register */
+    AT91_REG TDES_IMR;          /* Interrupt Mask Register */
+    AT91_REG TDES_ISR;          /* Interrupt Status Register */
+    AT91_REG TDES_KEY1WxR[ 2 ]; /* Key 1 Word x Register */
+    AT91_REG TDES_KEY2WxR[ 2 ]; /* Key 2 Word x Register */
+    AT91_REG TDES_KEY3WxR[ 2 ]; /* Key 3 Word x Register */
+    AT91_REG Reserved1[ 2 ];    /* */
+    AT91_REG TDES_IDATAxR[ 2 ]; /* Input Data x Register */
+    AT91_REG Reserved2[ 2 ];    /* */
+    AT91_REG TDES_ODATAxR[ 2 ]; /* Output Data x Register */
+    AT91_REG Reserved3[ 2 ];    /* */
+    AT91_REG TDES_IVxR[ 2 ];    /* Initialization Vector x Register */
+    AT91_REG Reserved4[ 37 ];   /* */
+    AT91_REG TDES_VR;           /* TDES Version Register */
+    AT91_REG TDES_RPR;          /* Receive Pointer Register */
+    AT91_REG TDES_RCR;          /* Receive Counter Register */
+    AT91_REG TDES_TPR;          /* Transmit Pointer Register */
+    AT91_REG TDES_TCR;          /* Transmit Counter Register */
+    AT91_REG TDES_RNPR;         /* Receive Next Pointer Register */
+    AT91_REG TDES_RNCR;         /* Receive Next Counter Register */
+    AT91_REG TDES_TNPR;         /* Transmit Next Pointer Register */
+    AT91_REG TDES_TNCR;         /* Transmit Next Counter Register */
+    AT91_REG TDES_PTCR;         /* PDC Transfer Control Register */
+    AT91_REG TDES_PTSR;         /* PDC Transfer Status Register */
+} AT91S_TDES, * AT91PS_TDES;
 
-// -------- TDES_CR : (TDES Offset: 0x0) Control Register --------
-#define AT91C_TDES_START      ((unsigned int) 0x1 <<  0) // (TDES) Starts Processing
-#define AT91C_TDES_SWRST      ((unsigned int) 0x1 <<  8) // (TDES) Software Reset
-// -------- TDES_MR : (TDES Offset: 0x4) Mode Register --------
-#define AT91C_TDES_CIPHER     ((unsigned int) 0x1 <<  0) // (TDES) Processing Mode
-#define AT91C_TDES_TDESMOD    ((unsigned int) 0x1 <<  1) // (TDES) Single or Triple DES Mode
-#define AT91C_TDES_KEYMOD     ((unsigned int) 0x1 <<  4) // (TDES) Key Mode
-#define AT91C_TDES_SMOD       ((unsigned int) 0x3 <<  8) // (TDES) Start Mode
-#define     AT91C_TDES_SMOD_MANUAL               ((unsigned int) 0x0 <<  8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.
-#define     AT91C_TDES_SMOD_AUTO                 ((unsigned int) 0x1 <<  8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).
-#define     AT91C_TDES_SMOD_PDC                  ((unsigned int) 0x2 <<  8) // (TDES) PDC Mode (cf datasheet).
-#define AT91C_TDES_OPMOD      ((unsigned int) 0x3 << 12) // (TDES) Operation Mode
-#define     AT91C_TDES_OPMOD_ECB                  ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode.
-#define     AT91C_TDES_OPMOD_CBC                  ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode.
-#define     AT91C_TDES_OPMOD_OFB                  ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode.
-#define     AT91C_TDES_OPMOD_CFB                  ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode.
-#define AT91C_TDES_LOD        ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode
-#define AT91C_TDES_CFBS       ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size
-#define     AT91C_TDES_CFBS_64_BIT               ((unsigned int) 0x0 << 16) // (TDES) 64-bit.
-#define     AT91C_TDES_CFBS_32_BIT               ((unsigned int) 0x1 << 16) // (TDES) 32-bit.
-#define     AT91C_TDES_CFBS_16_BIT               ((unsigned int) 0x2 << 16) // (TDES) 16-bit.
-#define     AT91C_TDES_CFBS_8_BIT                ((unsigned int) 0x3 << 16) // (TDES) 8-bit.
-// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register --------
-#define AT91C_TDES_DATRDY     ((unsigned int) 0x1 <<  0) // (TDES) DATRDY
-#define AT91C_TDES_ENDRX      ((unsigned int) 0x1 <<  1) // (TDES) PDC Read Buffer End
-#define AT91C_TDES_ENDTX      ((unsigned int) 0x1 <<  2) // (TDES) PDC Write Buffer End
-#define AT91C_TDES_RXBUFF     ((unsigned int) 0x1 <<  3) // (TDES) PDC Read Buffer Full
-#define AT91C_TDES_TXBUFE     ((unsigned int) 0x1 <<  4) // (TDES) PDC Write Buffer Empty
-#define AT91C_TDES_URAD       ((unsigned int) 0x1 <<  8) // (TDES) Unspecified Register Access Detection
-// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register --------
-// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register --------
-// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register --------
-#define AT91C_TDES_URAT       ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status
-#define     AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode.
-#define     AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing.
-#define     AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing.
-#define     AT91C_TDES_URAT_WO_REG_READ          ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access.
+/* -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- */
+#define AT91C_TDES_START              ( ( unsigned int ) 0x1 << 0 )  /* (TDES) Starts Processing */
+#define AT91C_TDES_SWRST              ( ( unsigned int ) 0x1 << 8 )  /* (TDES) Software Reset */
+/* -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- */
+#define AT91C_TDES_CIPHER             ( ( unsigned int ) 0x1 << 0 )  /* (TDES) Processing Mode */
+#define AT91C_TDES_TDESMOD            ( ( unsigned int ) 0x1 << 1 )  /* (TDES) Single or Triple DES Mode */
+#define AT91C_TDES_KEYMOD             ( ( unsigned int ) 0x1 << 4 )  /* (TDES) Key Mode */
+#define AT91C_TDES_SMOD               ( ( unsigned int ) 0x3 << 8 )  /* (TDES) Start Mode */
+#define     AT91C_TDES_SMOD_MANUAL    ( ( unsigned int ) 0x0 << 8 )  /* (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. */
+#define     AT91C_TDES_SMOD_AUTO      ( ( unsigned int ) 0x1 << 8 )  /* (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). */
+#define     AT91C_TDES_SMOD_PDC       ( ( unsigned int ) 0x2 << 8 )  /* (TDES) PDC Mode (cf datasheet). */
+#define AT91C_TDES_OPMOD              ( ( unsigned int ) 0x3 << 12 ) /* (TDES) Operation Mode */
+#define     AT91C_TDES_OPMOD_ECB      ( ( unsigned int ) 0x0 << 12 ) /* (TDES) ECB Electronic CodeBook mode. */
+#define     AT91C_TDES_OPMOD_CBC      ( ( unsigned int ) 0x1 << 12 ) /* (TDES) CBC Cipher Block Chaining mode. */
+#define     AT91C_TDES_OPMOD_OFB      ( ( unsigned int ) 0x2 << 12 ) /* (TDES) OFB Output Feedback mode. */
+#define     AT91C_TDES_OPMOD_CFB      ( ( unsigned int ) 0x3 << 12 ) /* (TDES) CFB Cipher Feedback mode. */
+#define AT91C_TDES_LOD                ( ( unsigned int ) 0x1 << 15 ) /* (TDES) Last Output Data Mode */
+#define AT91C_TDES_CFBS               ( ( unsigned int ) 0x3 << 16 ) /* (TDES) Cipher Feedback Data Size */
+#define     AT91C_TDES_CFBS_64_BIT    ( ( unsigned int ) 0x0 << 16 ) /* (TDES) 64-bit. */
+#define     AT91C_TDES_CFBS_32_BIT    ( ( unsigned int ) 0x1 << 16 ) /* (TDES) 32-bit. */
+#define     AT91C_TDES_CFBS_16_BIT    ( ( unsigned int ) 0x2 << 16 ) /* (TDES) 16-bit. */
+#define     AT91C_TDES_CFBS_8_BIT     ( ( unsigned int ) 0x3 << 16 ) /* (TDES) 8-bit. */
+/* -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- */
+#define AT91C_TDES_DATRDY             ( ( unsigned int ) 0x1 << 0 )  /* (TDES) DATRDY */
+#define AT91C_TDES_ENDRX              ( ( unsigned int ) 0x1 << 1 )  /* (TDES) PDC Read Buffer End */
+#define AT91C_TDES_ENDTX              ( ( unsigned int ) 0x1 << 2 )  /* (TDES) PDC Write Buffer End */
+#define AT91C_TDES_RXBUFF             ( ( unsigned int ) 0x1 << 3 )  /* (TDES) PDC Read Buffer Full */
+#define AT91C_TDES_TXBUFE             ( ( unsigned int ) 0x1 << 4 )  /* (TDES) PDC Write Buffer Empty */
+#define AT91C_TDES_URAD               ( ( unsigned int ) 0x1 << 8 )  /* (TDES) Unspecified Register Access Detection */
+/* -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- */
+/* -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- */
+/* -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- */
+#define AT91C_TDES_URAT                              ( ( unsigned int ) 0x3 << 12 ) /* (TDES) Unspecified Register Access Type Status */
+#define     AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC     ( ( unsigned int ) 0x0 << 12 ) /* (TDES) Input data register written during the data processing in PDC mode. */
+#define     AT91C_TDES_URAT_OUT_DAT_READ_DATPROC     ( ( unsigned int ) 0x1 << 12 ) /* (TDES) Output data register read during the data processing. */
+#define     AT91C_TDES_URAT_MODEREG_WRITE_DATPROC    ( ( unsigned int ) 0x2 << 12 ) /* (TDES) Mode register written during the data processing. */
+#define     AT91C_TDES_URAT_WO_REG_READ              ( ( unsigned int ) 0x3 << 12 ) /* (TDES) Write-only register read access. */
 
-// *****************************************************************************
-//               REGISTER ADDRESS DEFINITION FOR AT91SAM7X256
-// *****************************************************************************
-// ========== Register definition for SYS peripheral ==========
-// ========== Register definition for AIC peripheral ==========
-#define AT91C_AIC_IVR   ((AT91_REG *)   0xFFFFF100) // (AIC) IRQ Vector Register
-#define AT91C_AIC_SMR   ((AT91_REG *)   0xFFFFF000) // (AIC) Source Mode Register
-#define AT91C_AIC_FVR   ((AT91_REG *)   0xFFFFF104) // (AIC) FIQ Vector Register
-#define AT91C_AIC_DCR   ((AT91_REG *)   0xFFFFF138) // (AIC) Debug Control Register (Protect)
-#define AT91C_AIC_EOICR ((AT91_REG *)   0xFFFFF130) // (AIC) End of Interrupt Command Register
-#define AT91C_AIC_SVR   ((AT91_REG *)   0xFFFFF080) // (AIC) Source Vector Register
-#define AT91C_AIC_FFSR  ((AT91_REG *)   0xFFFFF148) // (AIC) Fast Forcing Status Register
-#define AT91C_AIC_ICCR  ((AT91_REG *)   0xFFFFF128) // (AIC) Interrupt Clear Command Register
-#define AT91C_AIC_ISR   ((AT91_REG *)   0xFFFFF108) // (AIC) Interrupt Status Register
-#define AT91C_AIC_IMR   ((AT91_REG *)   0xFFFFF110) // (AIC) Interrupt Mask Register
-#define AT91C_AIC_IPR   ((AT91_REG *)   0xFFFFF10C) // (AIC) Interrupt Pending Register
-#define AT91C_AIC_FFER  ((AT91_REG *)   0xFFFFF140) // (AIC) Fast Forcing Enable Register
-#define AT91C_AIC_IECR  ((AT91_REG *)   0xFFFFF120) // (AIC) Interrupt Enable Command Register
-#define AT91C_AIC_ISCR  ((AT91_REG *)   0xFFFFF12C) // (AIC) Interrupt Set Command Register
-#define AT91C_AIC_FFDR  ((AT91_REG *)   0xFFFFF144) // (AIC) Fast Forcing Disable Register
-#define AT91C_AIC_CISR  ((AT91_REG *)   0xFFFFF114) // (AIC) Core Interrupt Status Register
-#define AT91C_AIC_IDCR  ((AT91_REG *)   0xFFFFF124) // (AIC) Interrupt Disable Command Register
-#define AT91C_AIC_SPU   ((AT91_REG *)   0xFFFFF134) // (AIC) Spurious Vector Register
-// ========== Register definition for PDC_DBGU peripheral ==========
-#define AT91C_DBGU_TCR  ((AT91_REG *)   0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
-#define AT91C_DBGU_RNPR ((AT91_REG *)   0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
-#define AT91C_DBGU_TNPR ((AT91_REG *)   0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
-#define AT91C_DBGU_TPR  ((AT91_REG *)   0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
-#define AT91C_DBGU_RPR  ((AT91_REG *)   0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
-#define AT91C_DBGU_RCR  ((AT91_REG *)   0xFFFFF304) // (PDC_DBGU) Receive Counter Register
-#define AT91C_DBGU_RNCR ((AT91_REG *)   0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
-#define AT91C_DBGU_PTCR ((AT91_REG *)   0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
-#define AT91C_DBGU_PTSR ((AT91_REG *)   0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
-#define AT91C_DBGU_TNCR ((AT91_REG *)   0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
-// ========== Register definition for DBGU peripheral ==========
-#define AT91C_DBGU_EXID ((AT91_REG *)   0xFFFFF244) // (DBGU) Chip ID Extension Register
-#define AT91C_DBGU_BRGR ((AT91_REG *)   0xFFFFF220) // (DBGU) Baud Rate Generator Register
-#define AT91C_DBGU_IDR  ((AT91_REG *)   0xFFFFF20C) // (DBGU) Interrupt Disable Register
-#define AT91C_DBGU_CSR  ((AT91_REG *)   0xFFFFF214) // (DBGU) Channel Status Register
-#define AT91C_DBGU_CIDR ((AT91_REG *)   0xFFFFF240) // (DBGU) Chip ID Register
-#define AT91C_DBGU_MR   ((AT91_REG *)   0xFFFFF204) // (DBGU) Mode Register
-#define AT91C_DBGU_IMR  ((AT91_REG *)   0xFFFFF210) // (DBGU) Interrupt Mask Register
-#define AT91C_DBGU_CR   ((AT91_REG *)   0xFFFFF200) // (DBGU) Control Register
-#define AT91C_DBGU_FNTR ((AT91_REG *)   0xFFFFF248) // (DBGU) Force NTRST Register
-#define AT91C_DBGU_THR  ((AT91_REG *)   0xFFFFF21C) // (DBGU) Transmitter Holding Register
-#define AT91C_DBGU_RHR  ((AT91_REG *)   0xFFFFF218) // (DBGU) Receiver Holding Register
-#define AT91C_DBGU_IER  ((AT91_REG *)   0xFFFFF208) // (DBGU) Interrupt Enable Register
-// ========== Register definition for PIOA peripheral ==========
-#define AT91C_PIOA_ODR  ((AT91_REG *)   0xFFFFF414) // (PIOA) Output Disable Registerr
-#define AT91C_PIOA_SODR ((AT91_REG *)   0xFFFFF430) // (PIOA) Set Output Data Register
-#define AT91C_PIOA_ISR  ((AT91_REG *)   0xFFFFF44C) // (PIOA) Interrupt Status Register
-#define AT91C_PIOA_ABSR ((AT91_REG *)   0xFFFFF478) // (PIOA) AB Select Status Register
-#define AT91C_PIOA_IER  ((AT91_REG *)   0xFFFFF440) // (PIOA) Interrupt Enable Register
-#define AT91C_PIOA_PPUDR ((AT91_REG *)  0xFFFFF460) // (PIOA) Pull-up Disable Register
-#define AT91C_PIOA_IMR  ((AT91_REG *)   0xFFFFF448) // (PIOA) Interrupt Mask Register
-#define AT91C_PIOA_PER  ((AT91_REG *)   0xFFFFF400) // (PIOA) PIO Enable Register
-#define AT91C_PIOA_IFDR ((AT91_REG *)   0xFFFFF424) // (PIOA) Input Filter Disable Register
-#define AT91C_PIOA_OWDR ((AT91_REG *)   0xFFFFF4A4) // (PIOA) Output Write Disable Register
-#define AT91C_PIOA_MDSR ((AT91_REG *)   0xFFFFF458) // (PIOA) Multi-driver Status Register
-#define AT91C_PIOA_IDR  ((AT91_REG *)   0xFFFFF444) // (PIOA) Interrupt Disable Register
-#define AT91C_PIOA_ODSR ((AT91_REG *)   0xFFFFF438) // (PIOA) Output Data Status Register
-#define AT91C_PIOA_PPUSR ((AT91_REG *)  0xFFFFF468) // (PIOA) Pull-up Status Register
-#define AT91C_PIOA_OWSR ((AT91_REG *)   0xFFFFF4A8) // (PIOA) Output Write Status Register
-#define AT91C_PIOA_BSR  ((AT91_REG *)   0xFFFFF474) // (PIOA) Select B Register
-#define AT91C_PIOA_OWER ((AT91_REG *)   0xFFFFF4A0) // (PIOA) Output Write Enable Register
-#define AT91C_PIOA_IFER ((AT91_REG *)   0xFFFFF420) // (PIOA) Input Filter Enable Register
-#define AT91C_PIOA_PDSR ((AT91_REG *)   0xFFFFF43C) // (PIOA) Pin Data Status Register
-#define AT91C_PIOA_PPUER ((AT91_REG *)  0xFFFFF464) // (PIOA) Pull-up Enable Register
-#define AT91C_PIOA_OSR  ((AT91_REG *)   0xFFFFF418) // (PIOA) Output Status Register
-#define AT91C_PIOA_ASR  ((AT91_REG *)   0xFFFFF470) // (PIOA) Select A Register
-#define AT91C_PIOA_MDDR ((AT91_REG *)   0xFFFFF454) // (PIOA) Multi-driver Disable Register
-#define AT91C_PIOA_CODR ((AT91_REG *)   0xFFFFF434) // (PIOA) Clear Output Data Register
-#define AT91C_PIOA_MDER ((AT91_REG *)   0xFFFFF450) // (PIOA) Multi-driver Enable Register
-#define AT91C_PIOA_PDR  ((AT91_REG *)   0xFFFFF404) // (PIOA) PIO Disable Register
-#define AT91C_PIOA_IFSR ((AT91_REG *)   0xFFFFF428) // (PIOA) Input Filter Status Register
-#define AT91C_PIOA_OER  ((AT91_REG *)   0xFFFFF410) // (PIOA) Output Enable Register
-#define AT91C_PIOA_PSR  ((AT91_REG *)   0xFFFFF408) // (PIOA) PIO Status Register
-// ========== Register definition for PIOB peripheral ==========
-#define AT91C_PIOB_OWDR ((AT91_REG *)   0xFFFFF6A4) // (PIOB) Output Write Disable Register
-#define AT91C_PIOB_MDER ((AT91_REG *)   0xFFFFF650) // (PIOB) Multi-driver Enable Register
-#define AT91C_PIOB_PPUSR ((AT91_REG *)  0xFFFFF668) // (PIOB) Pull-up Status Register
-#define AT91C_PIOB_IMR  ((AT91_REG *)   0xFFFFF648) // (PIOB) Interrupt Mask Register
-#define AT91C_PIOB_ASR  ((AT91_REG *)   0xFFFFF670) // (PIOB) Select A Register
-#define AT91C_PIOB_PPUDR ((AT91_REG *)  0xFFFFF660) // (PIOB) Pull-up Disable Register
-#define AT91C_PIOB_PSR  ((AT91_REG *)   0xFFFFF608) // (PIOB) PIO Status Register
-#define AT91C_PIOB_IER  ((AT91_REG *)   0xFFFFF640) // (PIOB) Interrupt Enable Register
-#define AT91C_PIOB_CODR ((AT91_REG *)   0xFFFFF634) // (PIOB) Clear Output Data Register
-#define AT91C_PIOB_OWER ((AT91_REG *)   0xFFFFF6A0) // (PIOB) Output Write Enable Register
-#define AT91C_PIOB_ABSR ((AT91_REG *)   0xFFFFF678) // (PIOB) AB Select Status Register
-#define AT91C_PIOB_IFDR ((AT91_REG *)   0xFFFFF624) // (PIOB) Input Filter Disable Register
-#define AT91C_PIOB_PDSR ((AT91_REG *)   0xFFFFF63C) // (PIOB) Pin Data Status Register
-#define AT91C_PIOB_IDR  ((AT91_REG *)   0xFFFFF644) // (PIOB) Interrupt Disable Register
-#define AT91C_PIOB_OWSR ((AT91_REG *)   0xFFFFF6A8) // (PIOB) Output Write Status Register
-#define AT91C_PIOB_PDR  ((AT91_REG *)   0xFFFFF604) // (PIOB) PIO Disable Register
-#define AT91C_PIOB_ODR  ((AT91_REG *)   0xFFFFF614) // (PIOB) Output Disable Registerr
-#define AT91C_PIOB_IFSR ((AT91_REG *)   0xFFFFF628) // (PIOB) Input Filter Status Register
-#define AT91C_PIOB_PPUER ((AT91_REG *)  0xFFFFF664) // (PIOB) Pull-up Enable Register
-#define AT91C_PIOB_SODR ((AT91_REG *)   0xFFFFF630) // (PIOB) Set Output Data Register
-#define AT91C_PIOB_ISR  ((AT91_REG *)   0xFFFFF64C) // (PIOB) Interrupt Status Register
-#define AT91C_PIOB_ODSR ((AT91_REG *)   0xFFFFF638) // (PIOB) Output Data Status Register
-#define AT91C_PIOB_OSR  ((AT91_REG *)   0xFFFFF618) // (PIOB) Output Status Register
-#define AT91C_PIOB_MDSR ((AT91_REG *)   0xFFFFF658) // (PIOB) Multi-driver Status Register
-#define AT91C_PIOB_IFER ((AT91_REG *)   0xFFFFF620) // (PIOB) Input Filter Enable Register
-#define AT91C_PIOB_BSR  ((AT91_REG *)   0xFFFFF674) // (PIOB) Select B Register
-#define AT91C_PIOB_MDDR ((AT91_REG *)   0xFFFFF654) // (PIOB) Multi-driver Disable Register
-#define AT91C_PIOB_OER  ((AT91_REG *)   0xFFFFF610) // (PIOB) Output Enable Register
-#define AT91C_PIOB_PER  ((AT91_REG *)   0xFFFFF600) // (PIOB) PIO Enable Register
-// ========== Register definition for CKGR peripheral ==========
-#define AT91C_CKGR_MOR  ((AT91_REG *)   0xFFFFFC20) // (CKGR) Main Oscillator Register
-#define AT91C_CKGR_PLLR ((AT91_REG *)   0xFFFFFC2C) // (CKGR) PLL Register
-#define AT91C_CKGR_MCFR ((AT91_REG *)   0xFFFFFC24) // (CKGR) Main Clock  Frequency Register
-// ========== Register definition for PMC peripheral ==========
-#define AT91C_PMC_IDR   ((AT91_REG *)   0xFFFFFC64) // (PMC) Interrupt Disable Register
-#define AT91C_PMC_MOR   ((AT91_REG *)   0xFFFFFC20) // (PMC) Main Oscillator Register
-#define AT91C_PMC_PLLR  ((AT91_REG *)   0xFFFFFC2C) // (PMC) PLL Register
-#define AT91C_PMC_PCER  ((AT91_REG *)   0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
-#define AT91C_PMC_PCKR  ((AT91_REG *)   0xFFFFFC40) // (PMC) Programmable Clock Register
-#define AT91C_PMC_MCKR  ((AT91_REG *)   0xFFFFFC30) // (PMC) Master Clock Register
-#define AT91C_PMC_SCDR  ((AT91_REG *)   0xFFFFFC04) // (PMC) System Clock Disable Register
-#define AT91C_PMC_PCDR  ((AT91_REG *)   0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
-#define AT91C_PMC_SCSR  ((AT91_REG *)   0xFFFFFC08) // (PMC) System Clock Status Register
-#define AT91C_PMC_PCSR  ((AT91_REG *)   0xFFFFFC18) // (PMC) Peripheral Clock Status Register
-#define AT91C_PMC_MCFR  ((AT91_REG *)   0xFFFFFC24) // (PMC) Main Clock  Frequency Register
-#define AT91C_PMC_SCER  ((AT91_REG *)   0xFFFFFC00) // (PMC) System Clock Enable Register
-#define AT91C_PMC_IMR   ((AT91_REG *)   0xFFFFFC6C) // (PMC) Interrupt Mask Register
-#define AT91C_PMC_IER   ((AT91_REG *)   0xFFFFFC60) // (PMC) Interrupt Enable Register
-#define AT91C_PMC_SR    ((AT91_REG *)   0xFFFFFC68) // (PMC) Status Register
-// ========== Register definition for RSTC peripheral ==========
-#define AT91C_RSTC_RCR  ((AT91_REG *)   0xFFFFFD00) // (RSTC) Reset Control Register
-#define AT91C_RSTC_RMR  ((AT91_REG *)   0xFFFFFD08) // (RSTC) Reset Mode Register
-#define AT91C_RSTC_RSR  ((AT91_REG *)   0xFFFFFD04) // (RSTC) Reset Status Register
-// ========== Register definition for RTTC peripheral ==========
-#define AT91C_RTTC_RTSR ((AT91_REG *)   0xFFFFFD2C) // (RTTC) Real-time Status Register
-#define AT91C_RTTC_RTMR ((AT91_REG *)   0xFFFFFD20) // (RTTC) Real-time Mode Register
-#define AT91C_RTTC_RTVR ((AT91_REG *)   0xFFFFFD28) // (RTTC) Real-time Value Register
-#define AT91C_RTTC_RTAR ((AT91_REG *)   0xFFFFFD24) // (RTTC) Real-time Alarm Register
-// ========== Register definition for PITC peripheral ==========
-#define AT91C_PITC_PIVR ((AT91_REG *)   0xFFFFFD38) // (PITC) Period Interval Value Register
-#define AT91C_PITC_PISR ((AT91_REG *)   0xFFFFFD34) // (PITC) Period Interval Status Register
-#define AT91C_PITC_PIIR ((AT91_REG *)   0xFFFFFD3C) // (PITC) Period Interval Image Register
-#define AT91C_PITC_PIMR ((AT91_REG *)   0xFFFFFD30) // (PITC) Period Interval Mode Register
-// ========== Register definition for WDTC peripheral ==========
-#define AT91C_WDTC_WDCR ((AT91_REG *)   0xFFFFFD40) // (WDTC) Watchdog Control Register
-#define AT91C_WDTC_WDSR ((AT91_REG *)   0xFFFFFD48) // (WDTC) Watchdog Status Register
-#define AT91C_WDTC_WDMR ((AT91_REG *)   0xFFFFFD44) // (WDTC) Watchdog Mode Register
-// ========== Register definition for VREG peripheral ==========
-#define AT91C_VREG_MR   ((AT91_REG *)   0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
-// ========== Register definition for MC peripheral ==========
-#define AT91C_MC_ASR    ((AT91_REG *)   0xFFFFFF04) // (MC) MC Abort Status Register
-#define AT91C_MC_RCR    ((AT91_REG *)   0xFFFFFF00) // (MC) MC Remap Control Register
-#define AT91C_MC_FCR    ((AT91_REG *)   0xFFFFFF64) // (MC) MC Flash Command Register
-#define AT91C_MC_AASR   ((AT91_REG *)   0xFFFFFF08) // (MC) MC Abort Address Status Register
-#define AT91C_MC_FSR    ((AT91_REG *)   0xFFFFFF68) // (MC) MC Flash Status Register
-#define AT91C_MC_FMR    ((AT91_REG *)   0xFFFFFF60) // (MC) MC Flash Mode Register
-// ========== Register definition for PDC_SPI1 peripheral ==========
-#define AT91C_SPI1_PTCR ((AT91_REG *)   0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register
-#define AT91C_SPI1_RPR  ((AT91_REG *)   0xFFFE4100) // (PDC_SPI1) Receive Pointer Register
-#define AT91C_SPI1_TNCR ((AT91_REG *)   0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register
-#define AT91C_SPI1_TPR  ((AT91_REG *)   0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register
-#define AT91C_SPI1_TNPR ((AT91_REG *)   0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register
-#define AT91C_SPI1_TCR  ((AT91_REG *)   0xFFFE410C) // (PDC_SPI1) Transmit Counter Register
-#define AT91C_SPI1_RCR  ((AT91_REG *)   0xFFFE4104) // (PDC_SPI1) Receive Counter Register
-#define AT91C_SPI1_RNPR ((AT91_REG *)   0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register
-#define AT91C_SPI1_RNCR ((AT91_REG *)   0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register
-#define AT91C_SPI1_PTSR ((AT91_REG *)   0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register
-// ========== Register definition for SPI1 peripheral ==========
-#define AT91C_SPI1_IMR  ((AT91_REG *)   0xFFFE401C) // (SPI1) Interrupt Mask Register
-#define AT91C_SPI1_IER  ((AT91_REG *)   0xFFFE4014) // (SPI1) Interrupt Enable Register
-#define AT91C_SPI1_MR   ((AT91_REG *)   0xFFFE4004) // (SPI1) Mode Register
-#define AT91C_SPI1_RDR  ((AT91_REG *)   0xFFFE4008) // (SPI1) Receive Data Register
-#define AT91C_SPI1_IDR  ((AT91_REG *)   0xFFFE4018) // (SPI1) Interrupt Disable Register
-#define AT91C_SPI1_SR   ((AT91_REG *)   0xFFFE4010) // (SPI1) Status Register
-#define AT91C_SPI1_TDR  ((AT91_REG *)   0xFFFE400C) // (SPI1) Transmit Data Register
-#define AT91C_SPI1_CR   ((AT91_REG *)   0xFFFE4000) // (SPI1) Control Register
-#define AT91C_SPI1_CSR  ((AT91_REG *)   0xFFFE4030) // (SPI1) Chip Select Register
-// ========== Register definition for PDC_SPI0 peripheral ==========
-#define AT91C_SPI0_PTCR ((AT91_REG *)   0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register
-#define AT91C_SPI0_TPR  ((AT91_REG *)   0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register
-#define AT91C_SPI0_TCR  ((AT91_REG *)   0xFFFE010C) // (PDC_SPI0) Transmit Counter Register
-#define AT91C_SPI0_RCR  ((AT91_REG *)   0xFFFE0104) // (PDC_SPI0) Receive Counter Register
-#define AT91C_SPI0_PTSR ((AT91_REG *)   0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register
-#define AT91C_SPI0_RNPR ((AT91_REG *)   0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register
-#define AT91C_SPI0_RPR  ((AT91_REG *)   0xFFFE0100) // (PDC_SPI0) Receive Pointer Register
-#define AT91C_SPI0_TNCR ((AT91_REG *)   0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register
-#define AT91C_SPI0_RNCR ((AT91_REG *)   0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register
-#define AT91C_SPI0_TNPR ((AT91_REG *)   0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register
-// ========== Register definition for SPI0 peripheral ==========
-#define AT91C_SPI0_IER  ((AT91_REG *)   0xFFFE0014) // (SPI0) Interrupt Enable Register
-#define AT91C_SPI0_SR   ((AT91_REG *)   0xFFFE0010) // (SPI0) Status Register
-#define AT91C_SPI0_IDR  ((AT91_REG *)   0xFFFE0018) // (SPI0) Interrupt Disable Register
-#define AT91C_SPI0_CR   ((AT91_REG *)   0xFFFE0000) // (SPI0) Control Register
-#define AT91C_SPI0_MR   ((AT91_REG *)   0xFFFE0004) // (SPI0) Mode Register
-#define AT91C_SPI0_IMR  ((AT91_REG *)   0xFFFE001C) // (SPI0) Interrupt Mask Register
-#define AT91C_SPI0_TDR  ((AT91_REG *)   0xFFFE000C) // (SPI0) Transmit Data Register
-#define AT91C_SPI0_RDR  ((AT91_REG *)   0xFFFE0008) // (SPI0) Receive Data Register
-#define AT91C_SPI0_CSR  ((AT91_REG *)   0xFFFE0030) // (SPI0) Chip Select Register
-// ========== Register definition for PDC_US1 peripheral ==========
-#define AT91C_US1_RNCR  ((AT91_REG *)   0xFFFC4114) // (PDC_US1) Receive Next Counter Register
-#define AT91C_US1_PTCR  ((AT91_REG *)   0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
-#define AT91C_US1_TCR   ((AT91_REG *)   0xFFFC410C) // (PDC_US1) Transmit Counter Register
-#define AT91C_US1_PTSR  ((AT91_REG *)   0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
-#define AT91C_US1_TNPR  ((AT91_REG *)   0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
-#define AT91C_US1_RCR   ((AT91_REG *)   0xFFFC4104) // (PDC_US1) Receive Counter Register
-#define AT91C_US1_RNPR  ((AT91_REG *)   0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
-#define AT91C_US1_RPR   ((AT91_REG *)   0xFFFC4100) // (PDC_US1) Receive Pointer Register
-#define AT91C_US1_TNCR  ((AT91_REG *)   0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
-#define AT91C_US1_TPR   ((AT91_REG *)   0xFFFC4108) // (PDC_US1) Transmit Pointer Register
-// ========== Register definition for US1 peripheral ==========
-#define AT91C_US1_IF    ((AT91_REG *)   0xFFFC404C) // (US1) IRDA_FILTER Register
-#define AT91C_US1_NER   ((AT91_REG *)   0xFFFC4044) // (US1) Nb Errors Register
-#define AT91C_US1_RTOR  ((AT91_REG *)   0xFFFC4024) // (US1) Receiver Time-out Register
-#define AT91C_US1_CSR   ((AT91_REG *)   0xFFFC4014) // (US1) Channel Status Register
-#define AT91C_US1_IDR   ((AT91_REG *)   0xFFFC400C) // (US1) Interrupt Disable Register
-#define AT91C_US1_IER   ((AT91_REG *)   0xFFFC4008) // (US1) Interrupt Enable Register
-#define AT91C_US1_THR   ((AT91_REG *)   0xFFFC401C) // (US1) Transmitter Holding Register
-#define AT91C_US1_TTGR  ((AT91_REG *)   0xFFFC4028) // (US1) Transmitter Time-guard Register
-#define AT91C_US1_RHR   ((AT91_REG *)   0xFFFC4018) // (US1) Receiver Holding Register
-#define AT91C_US1_BRGR  ((AT91_REG *)   0xFFFC4020) // (US1) Baud Rate Generator Register
-#define AT91C_US1_IMR   ((AT91_REG *)   0xFFFC4010) // (US1) Interrupt Mask Register
-#define AT91C_US1_FIDI  ((AT91_REG *)   0xFFFC4040) // (US1) FI_DI_Ratio Register
-#define AT91C_US1_CR    ((AT91_REG *)   0xFFFC4000) // (US1) Control Register
-#define AT91C_US1_MR    ((AT91_REG *)   0xFFFC4004) // (US1) Mode Register
-// ========== Register definition for PDC_US0 peripheral ==========
-#define AT91C_US0_TNPR  ((AT91_REG *)   0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
-#define AT91C_US0_RNPR  ((AT91_REG *)   0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
-#define AT91C_US0_TCR   ((AT91_REG *)   0xFFFC010C) // (PDC_US0) Transmit Counter Register
-#define AT91C_US0_PTCR  ((AT91_REG *)   0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
-#define AT91C_US0_PTSR  ((AT91_REG *)   0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
-#define AT91C_US0_TNCR  ((AT91_REG *)   0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
-#define AT91C_US0_TPR   ((AT91_REG *)   0xFFFC0108) // (PDC_US0) Transmit Pointer Register
-#define AT91C_US0_RCR   ((AT91_REG *)   0xFFFC0104) // (PDC_US0) Receive Counter Register
-#define AT91C_US0_RPR   ((AT91_REG *)   0xFFFC0100) // (PDC_US0) Receive Pointer Register
-#define AT91C_US0_RNCR  ((AT91_REG *)   0xFFFC0114) // (PDC_US0) Receive Next Counter Register
-// ========== Register definition for US0 peripheral ==========
-#define AT91C_US0_BRGR  ((AT91_REG *)   0xFFFC0020) // (US0) Baud Rate Generator Register
-#define AT91C_US0_NER   ((AT91_REG *)   0xFFFC0044) // (US0) Nb Errors Register
-#define AT91C_US0_CR    ((AT91_REG *)   0xFFFC0000) // (US0) Control Register
-#define AT91C_US0_IMR   ((AT91_REG *)   0xFFFC0010) // (US0) Interrupt Mask Register
-#define AT91C_US0_FIDI  ((AT91_REG *)   0xFFFC0040) // (US0) FI_DI_Ratio Register
-#define AT91C_US0_TTGR  ((AT91_REG *)   0xFFFC0028) // (US0) Transmitter Time-guard Register
-#define AT91C_US0_MR    ((AT91_REG *)   0xFFFC0004) // (US0) Mode Register
-#define AT91C_US0_RTOR  ((AT91_REG *)   0xFFFC0024) // (US0) Receiver Time-out Register
-#define AT91C_US0_CSR   ((AT91_REG *)   0xFFFC0014) // (US0) Channel Status Register
-#define AT91C_US0_RHR   ((AT91_REG *)   0xFFFC0018) // (US0) Receiver Holding Register
-#define AT91C_US0_IDR   ((AT91_REG *)   0xFFFC000C) // (US0) Interrupt Disable Register
-#define AT91C_US0_THR   ((AT91_REG *)   0xFFFC001C) // (US0) Transmitter Holding Register
-#define AT91C_US0_IF    ((AT91_REG *)   0xFFFC004C) // (US0) IRDA_FILTER Register
-#define AT91C_US0_IER   ((AT91_REG *)   0xFFFC0008) // (US0) Interrupt Enable Register
-// ========== Register definition for PDC_SSC peripheral ==========
-#define AT91C_SSC_TNCR  ((AT91_REG *)   0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
-#define AT91C_SSC_RPR   ((AT91_REG *)   0xFFFD4100) // (PDC_SSC) Receive Pointer Register
-#define AT91C_SSC_RNCR  ((AT91_REG *)   0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
-#define AT91C_SSC_TPR   ((AT91_REG *)   0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
-#define AT91C_SSC_PTCR  ((AT91_REG *)   0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
-#define AT91C_SSC_TCR   ((AT91_REG *)   0xFFFD410C) // (PDC_SSC) Transmit Counter Register
-#define AT91C_SSC_RCR   ((AT91_REG *)   0xFFFD4104) // (PDC_SSC) Receive Counter Register
-#define AT91C_SSC_RNPR  ((AT91_REG *)   0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
-#define AT91C_SSC_TNPR  ((AT91_REG *)   0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
-#define AT91C_SSC_PTSR  ((AT91_REG *)   0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
-// ========== Register definition for SSC peripheral ==========
-#define AT91C_SSC_RHR   ((AT91_REG *)   0xFFFD4020) // (SSC) Receive Holding Register
-#define AT91C_SSC_RSHR  ((AT91_REG *)   0xFFFD4030) // (SSC) Receive Sync Holding Register
-#define AT91C_SSC_TFMR  ((AT91_REG *)   0xFFFD401C) // (SSC) Transmit Frame Mode Register
-#define AT91C_SSC_IDR   ((AT91_REG *)   0xFFFD4048) // (SSC) Interrupt Disable Register
-#define AT91C_SSC_THR   ((AT91_REG *)   0xFFFD4024) // (SSC) Transmit Holding Register
-#define AT91C_SSC_RCMR  ((AT91_REG *)   0xFFFD4010) // (SSC) Receive Clock ModeRegister
-#define AT91C_SSC_IER   ((AT91_REG *)   0xFFFD4044) // (SSC) Interrupt Enable Register
-#define AT91C_SSC_TSHR  ((AT91_REG *)   0xFFFD4034) // (SSC) Transmit Sync Holding Register
-#define AT91C_SSC_SR    ((AT91_REG *)   0xFFFD4040) // (SSC) Status Register
-#define AT91C_SSC_CMR   ((AT91_REG *)   0xFFFD4004) // (SSC) Clock Mode Register
-#define AT91C_SSC_TCMR  ((AT91_REG *)   0xFFFD4018) // (SSC) Transmit Clock Mode Register
-#define AT91C_SSC_CR    ((AT91_REG *)   0xFFFD4000) // (SSC) Control Register
-#define AT91C_SSC_IMR   ((AT91_REG *)   0xFFFD404C) // (SSC) Interrupt Mask Register
-#define AT91C_SSC_RFMR  ((AT91_REG *)   0xFFFD4014) // (SSC) Receive Frame Mode Register
-// ========== Register definition for TWI peripheral ==========
-#define AT91C_TWI_IER   ((AT91_REG *)   0xFFFB8024) // (TWI) Interrupt Enable Register
-#define AT91C_TWI_CR    ((AT91_REG *)   0xFFFB8000) // (TWI) Control Register
-#define AT91C_TWI_SR    ((AT91_REG *)   0xFFFB8020) // (TWI) Status Register
-#define AT91C_TWI_IMR   ((AT91_REG *)   0xFFFB802C) // (TWI) Interrupt Mask Register
-#define AT91C_TWI_THR   ((AT91_REG *)   0xFFFB8034) // (TWI) Transmit Holding Register
-#define AT91C_TWI_IDR   ((AT91_REG *)   0xFFFB8028) // (TWI) Interrupt Disable Register
-#define AT91C_TWI_IADR  ((AT91_REG *)   0xFFFB800C) // (TWI) Internal Address Register
-#define AT91C_TWI_MMR   ((AT91_REG *)   0xFFFB8004) // (TWI) Master Mode Register
-#define AT91C_TWI_CWGR  ((AT91_REG *)   0xFFFB8010) // (TWI) Clock Waveform Generator Register
-#define AT91C_TWI_RHR   ((AT91_REG *)   0xFFFB8030) // (TWI) Receive Holding Register
-// ========== Register definition for PWMC_CH3 peripheral ==========
-#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *)  0xFFFCC270) // (PWMC_CH3) Channel Update Register
-#define AT91C_PWMC_CH3_Reserved ((AT91_REG *)   0xFFFCC274) // (PWMC_CH3) Reserved
-#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *)  0xFFFCC268) // (PWMC_CH3) Channel Period Register
-#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *)  0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
-#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *)  0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
-#define AT91C_PWMC_CH3_CMR ((AT91_REG *)    0xFFFCC260) // (PWMC_CH3) Channel Mode Register
-// ========== Register definition for PWMC_CH2 peripheral ==========
-#define AT91C_PWMC_CH2_Reserved ((AT91_REG *)   0xFFFCC254) // (PWMC_CH2) Reserved
-#define AT91C_PWMC_CH2_CMR ((AT91_REG *)    0xFFFCC240) // (PWMC_CH2) Channel Mode Register
-#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *)  0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
-#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *)  0xFFFCC248) // (PWMC_CH2) Channel Period Register
-#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *)  0xFFFCC250) // (PWMC_CH2) Channel Update Register
-#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *)  0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
-// ========== Register definition for PWMC_CH1 peripheral ==========
-#define AT91C_PWMC_CH1_Reserved ((AT91_REG *)   0xFFFCC234) // (PWMC_CH1) Reserved
-#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *)  0xFFFCC230) // (PWMC_CH1) Channel Update Register
-#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *)  0xFFFCC228) // (PWMC_CH1) Channel Period Register
-#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *)  0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
-#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *)  0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
-#define AT91C_PWMC_CH1_CMR ((AT91_REG *)    0xFFFCC220) // (PWMC_CH1) Channel Mode Register
-// ========== Register definition for PWMC_CH0 peripheral ==========
-#define AT91C_PWMC_CH0_Reserved ((AT91_REG *)   0xFFFCC214) // (PWMC_CH0) Reserved
-#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *)  0xFFFCC208) // (PWMC_CH0) Channel Period Register
-#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *)  0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
-#define AT91C_PWMC_CH0_CMR ((AT91_REG *)    0xFFFCC200) // (PWMC_CH0) Channel Mode Register
-#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *)  0xFFFCC210) // (PWMC_CH0) Channel Update Register
-#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *)  0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
-// ========== Register definition for PWMC peripheral ==========
-#define AT91C_PWMC_IDR  ((AT91_REG *)   0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
-#define AT91C_PWMC_DIS  ((AT91_REG *)   0xFFFCC008) // (PWMC) PWMC Disable Register
-#define AT91C_PWMC_IER  ((AT91_REG *)   0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
-#define AT91C_PWMC_VR   ((AT91_REG *)   0xFFFCC0FC) // (PWMC) PWMC Version Register
-#define AT91C_PWMC_ISR  ((AT91_REG *)   0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
-#define AT91C_PWMC_SR   ((AT91_REG *)   0xFFFCC00C) // (PWMC) PWMC Status Register
-#define AT91C_PWMC_IMR  ((AT91_REG *)   0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
-#define AT91C_PWMC_MR   ((AT91_REG *)   0xFFFCC000) // (PWMC) PWMC Mode Register
-#define AT91C_PWMC_ENA  ((AT91_REG *)   0xFFFCC004) // (PWMC) PWMC Enable Register
-// ========== Register definition for UDP peripheral ==========
-#define AT91C_UDP_IMR   ((AT91_REG *)   0xFFFB0018) // (UDP) Interrupt Mask Register
-#define AT91C_UDP_FADDR ((AT91_REG *)   0xFFFB0008) // (UDP) Function Address Register
-#define AT91C_UDP_NUM   ((AT91_REG *)   0xFFFB0000) // (UDP) Frame Number Register
-#define AT91C_UDP_FDR   ((AT91_REG *)   0xFFFB0050) // (UDP) Endpoint FIFO Data Register
-#define AT91C_UDP_ISR   ((AT91_REG *)   0xFFFB001C) // (UDP) Interrupt Status Register
-#define AT91C_UDP_CSR   ((AT91_REG *)   0xFFFB0030) // (UDP) Endpoint Control and Status Register
-#define AT91C_UDP_IDR   ((AT91_REG *)   0xFFFB0014) // (UDP) Interrupt Disable Register
-#define AT91C_UDP_ICR   ((AT91_REG *)   0xFFFB0020) // (UDP) Interrupt Clear Register
-#define AT91C_UDP_RSTEP ((AT91_REG *)   0xFFFB0028) // (UDP) Reset Endpoint Register
-#define AT91C_UDP_TXVC  ((AT91_REG *)   0xFFFB0074) // (UDP) Transceiver Control Register
-#define AT91C_UDP_GLBSTATE ((AT91_REG *)    0xFFFB0004) // (UDP) Global State Register
-#define AT91C_UDP_IER   ((AT91_REG *)   0xFFFB0010) // (UDP) Interrupt Enable Register
-// ========== Register definition for TC0 peripheral ==========
-#define AT91C_TC0_SR    ((AT91_REG *)   0xFFFA0020) // (TC0) Status Register
-#define AT91C_TC0_RC    ((AT91_REG *)   0xFFFA001C) // (TC0) Register C
-#define AT91C_TC0_RB    ((AT91_REG *)   0xFFFA0018) // (TC0) Register B
-#define AT91C_TC0_CCR   ((AT91_REG *)   0xFFFA0000) // (TC0) Channel Control Register
-#define AT91C_TC0_CMR   ((AT91_REG *)   0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC0_IER   ((AT91_REG *)   0xFFFA0024) // (TC0) Interrupt Enable Register
-#define AT91C_TC0_RA    ((AT91_REG *)   0xFFFA0014) // (TC0) Register A
-#define AT91C_TC0_IDR   ((AT91_REG *)   0xFFFA0028) // (TC0) Interrupt Disable Register
-#define AT91C_TC0_CV    ((AT91_REG *)   0xFFFA0010) // (TC0) Counter Value
-#define AT91C_TC0_IMR   ((AT91_REG *)   0xFFFA002C) // (TC0) Interrupt Mask Register
-// ========== Register definition for TC1 peripheral ==========
-#define AT91C_TC1_RB    ((AT91_REG *)   0xFFFA0058) // (TC1) Register B
-#define AT91C_TC1_CCR   ((AT91_REG *)   0xFFFA0040) // (TC1) Channel Control Register
-#define AT91C_TC1_IER   ((AT91_REG *)   0xFFFA0064) // (TC1) Interrupt Enable Register
-#define AT91C_TC1_IDR   ((AT91_REG *)   0xFFFA0068) // (TC1) Interrupt Disable Register
-#define AT91C_TC1_SR    ((AT91_REG *)   0xFFFA0060) // (TC1) Status Register
-#define AT91C_TC1_CMR   ((AT91_REG *)   0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC1_RA    ((AT91_REG *)   0xFFFA0054) // (TC1) Register A
-#define AT91C_TC1_RC    ((AT91_REG *)   0xFFFA005C) // (TC1) Register C
-#define AT91C_TC1_IMR   ((AT91_REG *)   0xFFFA006C) // (TC1) Interrupt Mask Register
-#define AT91C_TC1_CV    ((AT91_REG *)   0xFFFA0050) // (TC1) Counter Value
-// ========== Register definition for TC2 peripheral ==========
-#define AT91C_TC2_CMR   ((AT91_REG *)   0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC2_CCR   ((AT91_REG *)   0xFFFA0080) // (TC2) Channel Control Register
-#define AT91C_TC2_CV    ((AT91_REG *)   0xFFFA0090) // (TC2) Counter Value
-#define AT91C_TC2_RA    ((AT91_REG *)   0xFFFA0094) // (TC2) Register A
-#define AT91C_TC2_RB    ((AT91_REG *)   0xFFFA0098) // (TC2) Register B
-#define AT91C_TC2_IDR   ((AT91_REG *)   0xFFFA00A8) // (TC2) Interrupt Disable Register
-#define AT91C_TC2_IMR   ((AT91_REG *)   0xFFFA00AC) // (TC2) Interrupt Mask Register
-#define AT91C_TC2_RC    ((AT91_REG *)   0xFFFA009C) // (TC2) Register C
-#define AT91C_TC2_IER   ((AT91_REG *)   0xFFFA00A4) // (TC2) Interrupt Enable Register
-#define AT91C_TC2_SR    ((AT91_REG *)   0xFFFA00A0) // (TC2) Status Register
-// ========== Register definition for TCB peripheral ==========
-#define AT91C_TCB_BMR   ((AT91_REG *)   0xFFFA00C4) // (TCB) TC Block Mode Register
-#define AT91C_TCB_BCR   ((AT91_REG *)   0xFFFA00C0) // (TCB) TC Block Control Register
-// ========== Register definition for CAN_MB0 peripheral ==========
-#define AT91C_CAN_MB0_MDL ((AT91_REG *)     0xFFFD0214) // (CAN_MB0) MailBox Data Low Register
-#define AT91C_CAN_MB0_MAM ((AT91_REG *)     0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB0_MCR ((AT91_REG *)     0xFFFD021C) // (CAN_MB0) MailBox Control Register
-#define AT91C_CAN_MB0_MID ((AT91_REG *)     0xFFFD0208) // (CAN_MB0) MailBox ID Register
-#define AT91C_CAN_MB0_MSR ((AT91_REG *)     0xFFFD0210) // (CAN_MB0) MailBox Status Register
-#define AT91C_CAN_MB0_MFID ((AT91_REG *)    0xFFFD020C) // (CAN_MB0) MailBox Family ID Register
-#define AT91C_CAN_MB0_MDH ((AT91_REG *)     0xFFFD0218) // (CAN_MB0) MailBox Data High Register
-#define AT91C_CAN_MB0_MMR ((AT91_REG *)     0xFFFD0200) // (CAN_MB0) MailBox Mode Register
-// ========== Register definition for CAN_MB1 peripheral ==========
-#define AT91C_CAN_MB1_MDL ((AT91_REG *)     0xFFFD0234) // (CAN_MB1) MailBox Data Low Register
-#define AT91C_CAN_MB1_MID ((AT91_REG *)     0xFFFD0228) // (CAN_MB1) MailBox ID Register
-#define AT91C_CAN_MB1_MMR ((AT91_REG *)     0xFFFD0220) // (CAN_MB1) MailBox Mode Register
-#define AT91C_CAN_MB1_MSR ((AT91_REG *)     0xFFFD0230) // (CAN_MB1) MailBox Status Register
-#define AT91C_CAN_MB1_MAM ((AT91_REG *)     0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB1_MDH ((AT91_REG *)     0xFFFD0238) // (CAN_MB1) MailBox Data High Register
-#define AT91C_CAN_MB1_MCR ((AT91_REG *)     0xFFFD023C) // (CAN_MB1) MailBox Control Register
-#define AT91C_CAN_MB1_MFID ((AT91_REG *)    0xFFFD022C) // (CAN_MB1) MailBox Family ID Register
-// ========== Register definition for CAN_MB2 peripheral ==========
-#define AT91C_CAN_MB2_MCR ((AT91_REG *)     0xFFFD025C) // (CAN_MB2) MailBox Control Register
-#define AT91C_CAN_MB2_MDH ((AT91_REG *)     0xFFFD0258) // (CAN_MB2) MailBox Data High Register
-#define AT91C_CAN_MB2_MID ((AT91_REG *)     0xFFFD0248) // (CAN_MB2) MailBox ID Register
-#define AT91C_CAN_MB2_MDL ((AT91_REG *)     0xFFFD0254) // (CAN_MB2) MailBox Data Low Register
-#define AT91C_CAN_MB2_MMR ((AT91_REG *)     0xFFFD0240) // (CAN_MB2) MailBox Mode Register
-#define AT91C_CAN_MB2_MAM ((AT91_REG *)     0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB2_MFID ((AT91_REG *)    0xFFFD024C) // (CAN_MB2) MailBox Family ID Register
-#define AT91C_CAN_MB2_MSR ((AT91_REG *)     0xFFFD0250) // (CAN_MB2) MailBox Status Register
-// ========== Register definition for CAN_MB3 peripheral ==========
-#define AT91C_CAN_MB3_MFID ((AT91_REG *)    0xFFFD026C) // (CAN_MB3) MailBox Family ID Register
-#define AT91C_CAN_MB3_MAM ((AT91_REG *)     0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB3_MID ((AT91_REG *)     0xFFFD0268) // (CAN_MB3) MailBox ID Register
-#define AT91C_CAN_MB3_MCR ((AT91_REG *)     0xFFFD027C) // (CAN_MB3) MailBox Control Register
-#define AT91C_CAN_MB3_MMR ((AT91_REG *)     0xFFFD0260) // (CAN_MB3) MailBox Mode Register
-#define AT91C_CAN_MB3_MSR ((AT91_REG *)     0xFFFD0270) // (CAN_MB3) MailBox Status Register
-#define AT91C_CAN_MB3_MDL ((AT91_REG *)     0xFFFD0274) // (CAN_MB3) MailBox Data Low Register
-#define AT91C_CAN_MB3_MDH ((AT91_REG *)     0xFFFD0278) // (CAN_MB3) MailBox Data High Register
-// ========== Register definition for CAN_MB4 peripheral ==========
-#define AT91C_CAN_MB4_MID ((AT91_REG *)     0xFFFD0288) // (CAN_MB4) MailBox ID Register
-#define AT91C_CAN_MB4_MMR ((AT91_REG *)     0xFFFD0280) // (CAN_MB4) MailBox Mode Register
-#define AT91C_CAN_MB4_MDH ((AT91_REG *)     0xFFFD0298) // (CAN_MB4) MailBox Data High Register
-#define AT91C_CAN_MB4_MFID ((AT91_REG *)    0xFFFD028C) // (CAN_MB4) MailBox Family ID Register
-#define AT91C_CAN_MB4_MSR ((AT91_REG *)     0xFFFD0290) // (CAN_MB4) MailBox Status Register
-#define AT91C_CAN_MB4_MCR ((AT91_REG *)     0xFFFD029C) // (CAN_MB4) MailBox Control Register
-#define AT91C_CAN_MB4_MDL ((AT91_REG *)     0xFFFD0294) // (CAN_MB4) MailBox Data Low Register
-#define AT91C_CAN_MB4_MAM ((AT91_REG *)     0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register
-// ========== Register definition for CAN_MB5 peripheral ==========
-#define AT91C_CAN_MB5_MSR ((AT91_REG *)     0xFFFD02B0) // (CAN_MB5) MailBox Status Register
-#define AT91C_CAN_MB5_MCR ((AT91_REG *)     0xFFFD02BC) // (CAN_MB5) MailBox Control Register
-#define AT91C_CAN_MB5_MFID ((AT91_REG *)    0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register
-#define AT91C_CAN_MB5_MDH ((AT91_REG *)     0xFFFD02B8) // (CAN_MB5) MailBox Data High Register
-#define AT91C_CAN_MB5_MID ((AT91_REG *)     0xFFFD02A8) // (CAN_MB5) MailBox ID Register
-#define AT91C_CAN_MB5_MMR ((AT91_REG *)     0xFFFD02A0) // (CAN_MB5) MailBox Mode Register
-#define AT91C_CAN_MB5_MDL ((AT91_REG *)     0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register
-#define AT91C_CAN_MB5_MAM ((AT91_REG *)     0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register
-// ========== Register definition for CAN_MB6 peripheral ==========
-#define AT91C_CAN_MB6_MFID ((AT91_REG *)    0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register
-#define AT91C_CAN_MB6_MID ((AT91_REG *)     0xFFFD02C8) // (CAN_MB6) MailBox ID Register
-#define AT91C_CAN_MB6_MAM ((AT91_REG *)     0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB6_MSR ((AT91_REG *)     0xFFFD02D0) // (CAN_MB6) MailBox Status Register
-#define AT91C_CAN_MB6_MDL ((AT91_REG *)     0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register
-#define AT91C_CAN_MB6_MCR ((AT91_REG *)     0xFFFD02DC) // (CAN_MB6) MailBox Control Register
-#define AT91C_CAN_MB6_MDH ((AT91_REG *)     0xFFFD02D8) // (CAN_MB6) MailBox Data High Register
-#define AT91C_CAN_MB6_MMR ((AT91_REG *)     0xFFFD02C0) // (CAN_MB6) MailBox Mode Register
-// ========== Register definition for CAN_MB7 peripheral ==========
-#define AT91C_CAN_MB7_MCR ((AT91_REG *)     0xFFFD02FC) // (CAN_MB7) MailBox Control Register
-#define AT91C_CAN_MB7_MDH ((AT91_REG *)     0xFFFD02F8) // (CAN_MB7) MailBox Data High Register
-#define AT91C_CAN_MB7_MFID ((AT91_REG *)    0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register
-#define AT91C_CAN_MB7_MDL ((AT91_REG *)     0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register
-#define AT91C_CAN_MB7_MID ((AT91_REG *)     0xFFFD02E8) // (CAN_MB7) MailBox ID Register
-#define AT91C_CAN_MB7_MMR ((AT91_REG *)     0xFFFD02E0) // (CAN_MB7) MailBox Mode Register
-#define AT91C_CAN_MB7_MAM ((AT91_REG *)     0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB7_MSR ((AT91_REG *)     0xFFFD02F0) // (CAN_MB7) MailBox Status Register
-// ========== Register definition for CAN peripheral ==========
-#define AT91C_CAN_TCR   ((AT91_REG *)   0xFFFD0024) // (CAN) Transfer Command Register
-#define AT91C_CAN_IMR   ((AT91_REG *)   0xFFFD000C) // (CAN) Interrupt Mask Register
-#define AT91C_CAN_IER   ((AT91_REG *)   0xFFFD0004) // (CAN) Interrupt Enable Register
-#define AT91C_CAN_ECR   ((AT91_REG *)   0xFFFD0020) // (CAN) Error Counter Register
-#define AT91C_CAN_TIMESTP ((AT91_REG *)     0xFFFD001C) // (CAN) Time Stamp Register
-#define AT91C_CAN_MR    ((AT91_REG *)   0xFFFD0000) // (CAN) Mode Register
-#define AT91C_CAN_IDR   ((AT91_REG *)   0xFFFD0008) // (CAN) Interrupt Disable Register
-#define AT91C_CAN_ACR   ((AT91_REG *)   0xFFFD0028) // (CAN) Abort Command Register
-#define AT91C_CAN_TIM   ((AT91_REG *)   0xFFFD0018) // (CAN) Timer Register
-#define AT91C_CAN_SR    ((AT91_REG *)   0xFFFD0010) // (CAN) Status Register
-#define AT91C_CAN_BR    ((AT91_REG *)   0xFFFD0014) // (CAN) Baudrate Register
-#define AT91C_CAN_VR    ((AT91_REG *)   0xFFFD00FC) // (CAN) Version Register
-// ========== Register definition for EMAC peripheral ==========
-#define AT91C_EMAC_ISR  ((AT91_REG *)   0xFFFDC024) // (EMAC) Interrupt Status Register
-#define AT91C_EMAC_SA4H ((AT91_REG *)   0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes
-#define AT91C_EMAC_SA1L ((AT91_REG *)   0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes
-#define AT91C_EMAC_ELE  ((AT91_REG *)   0xFFFDC078) // (EMAC) Excessive Length Errors Register
-#define AT91C_EMAC_LCOL ((AT91_REG *)   0xFFFDC05C) // (EMAC) Late Collision Register
-#define AT91C_EMAC_RLE  ((AT91_REG *)   0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register
-#define AT91C_EMAC_WOL  ((AT91_REG *)   0xFFFDC0C4) // (EMAC) Wake On LAN Register
-#define AT91C_EMAC_DTF  ((AT91_REG *)   0xFFFDC058) // (EMAC) Deferred Transmission Frame Register
-#define AT91C_EMAC_TUND ((AT91_REG *)   0xFFFDC064) // (EMAC) Transmit Underrun Error Register
-#define AT91C_EMAC_NCR  ((AT91_REG *)   0xFFFDC000) // (EMAC) Network Control Register
-#define AT91C_EMAC_SA4L ((AT91_REG *)   0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes
-#define AT91C_EMAC_RSR  ((AT91_REG *)   0xFFFDC020) // (EMAC) Receive Status Register
-#define AT91C_EMAC_SA3L ((AT91_REG *)   0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes
-#define AT91C_EMAC_TSR  ((AT91_REG *)   0xFFFDC014) // (EMAC) Transmit Status Register
-#define AT91C_EMAC_IDR  ((AT91_REG *)   0xFFFDC02C) // (EMAC) Interrupt Disable Register
-#define AT91C_EMAC_RSE  ((AT91_REG *)   0xFFFDC074) // (EMAC) Receive Symbol Errors Register
-#define AT91C_EMAC_ECOL ((AT91_REG *)   0xFFFDC060) // (EMAC) Excessive Collision Register
-#define AT91C_EMAC_TID  ((AT91_REG *)   0xFFFDC0B8) // (EMAC) Type ID Checking Register
-#define AT91C_EMAC_HRB  ((AT91_REG *)   0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]
-#define AT91C_EMAC_TBQP ((AT91_REG *)   0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer
-#define AT91C_EMAC_USRIO ((AT91_REG *)  0xFFFDC0C0) // (EMAC) USER Input/Output Register
-#define AT91C_EMAC_PTR  ((AT91_REG *)   0xFFFDC038) // (EMAC) Pause Time Register
-#define AT91C_EMAC_SA2H ((AT91_REG *)   0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes
-#define AT91C_EMAC_ROV  ((AT91_REG *)   0xFFFDC070) // (EMAC) Receive Overrun Errors Register
-#define AT91C_EMAC_ALE  ((AT91_REG *)   0xFFFDC054) // (EMAC) Alignment Error Register
-#define AT91C_EMAC_RJA  ((AT91_REG *)   0xFFFDC07C) // (EMAC) Receive Jabbers Register
-#define AT91C_EMAC_RBQP ((AT91_REG *)   0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer
-#define AT91C_EMAC_TPF  ((AT91_REG *)   0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register
-#define AT91C_EMAC_NCFGR ((AT91_REG *)  0xFFFDC004) // (EMAC) Network Configuration Register
-#define AT91C_EMAC_HRT  ((AT91_REG *)   0xFFFDC094) // (EMAC) Hash Address Top[63:32]
-#define AT91C_EMAC_USF  ((AT91_REG *)   0xFFFDC080) // (EMAC) Undersize Frames Register
-#define AT91C_EMAC_FCSE ((AT91_REG *)   0xFFFDC050) // (EMAC) Frame Check Sequence Error Register
-#define AT91C_EMAC_TPQ  ((AT91_REG *)   0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register
-#define AT91C_EMAC_MAN  ((AT91_REG *)   0xFFFDC034) // (EMAC) PHY Maintenance Register
-#define AT91C_EMAC_FTO  ((AT91_REG *)   0xFFFDC040) // (EMAC) Frames Transmitted OK Register
-#define AT91C_EMAC_REV  ((AT91_REG *)   0xFFFDC0FC) // (EMAC) Revision Register
-#define AT91C_EMAC_IMR  ((AT91_REG *)   0xFFFDC030) // (EMAC) Interrupt Mask Register
-#define AT91C_EMAC_SCF  ((AT91_REG *)   0xFFFDC044) // (EMAC) Single Collision Frame Register
-#define AT91C_EMAC_PFR  ((AT91_REG *)   0xFFFDC03C) // (EMAC) Pause Frames received Register
-#define AT91C_EMAC_MCF  ((AT91_REG *)   0xFFFDC048) // (EMAC) Multiple Collision Frame Register
-#define AT91C_EMAC_NSR  ((AT91_REG *)   0xFFFDC008) // (EMAC) Network Status Register
-#define AT91C_EMAC_SA2L ((AT91_REG *)   0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes
-#define AT91C_EMAC_FRO  ((AT91_REG *)   0xFFFDC04C) // (EMAC) Frames Received OK Register
-#define AT91C_EMAC_IER  ((AT91_REG *)   0xFFFDC028) // (EMAC) Interrupt Enable Register
-#define AT91C_EMAC_SA1H ((AT91_REG *)   0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes
-#define AT91C_EMAC_CSE  ((AT91_REG *)   0xFFFDC068) // (EMAC) Carrier Sense Error Register
-#define AT91C_EMAC_SA3H ((AT91_REG *)   0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes
-#define AT91C_EMAC_RRE  ((AT91_REG *)   0xFFFDC06C) // (EMAC) Receive Ressource Error Register
-#define AT91C_EMAC_STE  ((AT91_REG *)   0xFFFDC084) // (EMAC) SQE Test Error Register
-// ========== Register definition for PDC_ADC peripheral ==========
-#define AT91C_ADC_PTSR  ((AT91_REG *)   0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
-#define AT91C_ADC_PTCR  ((AT91_REG *)   0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
-#define AT91C_ADC_TNPR  ((AT91_REG *)   0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
-#define AT91C_ADC_TNCR  ((AT91_REG *)   0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
-#define AT91C_ADC_RNPR  ((AT91_REG *)   0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
-#define AT91C_ADC_RNCR  ((AT91_REG *)   0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
-#define AT91C_ADC_RPR   ((AT91_REG *)   0xFFFD8100) // (PDC_ADC) Receive Pointer Register
-#define AT91C_ADC_TCR   ((AT91_REG *)   0xFFFD810C) // (PDC_ADC) Transmit Counter Register
-#define AT91C_ADC_TPR   ((AT91_REG *)   0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
-#define AT91C_ADC_RCR   ((AT91_REG *)   0xFFFD8104) // (PDC_ADC) Receive Counter Register
-// ========== Register definition for ADC peripheral ==========
-#define AT91C_ADC_CDR2  ((AT91_REG *)   0xFFFD8038) // (ADC) ADC Channel Data Register 2
-#define AT91C_ADC_CDR3  ((AT91_REG *)   0xFFFD803C) // (ADC) ADC Channel Data Register 3
-#define AT91C_ADC_CDR0  ((AT91_REG *)   0xFFFD8030) // (ADC) ADC Channel Data Register 0
-#define AT91C_ADC_CDR5  ((AT91_REG *)   0xFFFD8044) // (ADC) ADC Channel Data Register 5
-#define AT91C_ADC_CHDR  ((AT91_REG *)   0xFFFD8014) // (ADC) ADC Channel Disable Register
-#define AT91C_ADC_SR    ((AT91_REG *)   0xFFFD801C) // (ADC) ADC Status Register
-#define AT91C_ADC_CDR4  ((AT91_REG *)   0xFFFD8040) // (ADC) ADC Channel Data Register 4
-#define AT91C_ADC_CDR1  ((AT91_REG *)   0xFFFD8034) // (ADC) ADC Channel Data Register 1
-#define AT91C_ADC_LCDR  ((AT91_REG *)   0xFFFD8020) // (ADC) ADC Last Converted Data Register
-#define AT91C_ADC_IDR   ((AT91_REG *)   0xFFFD8028) // (ADC) ADC Interrupt Disable Register
-#define AT91C_ADC_CR    ((AT91_REG *)   0xFFFD8000) // (ADC) ADC Control Register
-#define AT91C_ADC_CDR7  ((AT91_REG *)   0xFFFD804C) // (ADC) ADC Channel Data Register 7
-#define AT91C_ADC_CDR6  ((AT91_REG *)   0xFFFD8048) // (ADC) ADC Channel Data Register 6
-#define AT91C_ADC_IER   ((AT91_REG *)   0xFFFD8024) // (ADC) ADC Interrupt Enable Register
-#define AT91C_ADC_CHER  ((AT91_REG *)   0xFFFD8010) // (ADC) ADC Channel Enable Register
-#define AT91C_ADC_CHSR  ((AT91_REG *)   0xFFFD8018) // (ADC) ADC Channel Status Register
-#define AT91C_ADC_MR    ((AT91_REG *)   0xFFFD8004) // (ADC) ADC Mode Register
-#define AT91C_ADC_IMR   ((AT91_REG *)   0xFFFD802C) // (ADC) ADC Interrupt Mask Register
-// ========== Register definition for PDC_AES peripheral ==========
-#define AT91C_AES_TPR   ((AT91_REG *)   0xFFFA4108) // (PDC_AES) Transmit Pointer Register
-#define AT91C_AES_PTCR  ((AT91_REG *)   0xFFFA4120) // (PDC_AES) PDC Transfer Control Register
-#define AT91C_AES_RNPR  ((AT91_REG *)   0xFFFA4110) // (PDC_AES) Receive Next Pointer Register
-#define AT91C_AES_TNCR  ((AT91_REG *)   0xFFFA411C) // (PDC_AES) Transmit Next Counter Register
-#define AT91C_AES_TCR   ((AT91_REG *)   0xFFFA410C) // (PDC_AES) Transmit Counter Register
-#define AT91C_AES_RCR   ((AT91_REG *)   0xFFFA4104) // (PDC_AES) Receive Counter Register
-#define AT91C_AES_RNCR  ((AT91_REG *)   0xFFFA4114) // (PDC_AES) Receive Next Counter Register
-#define AT91C_AES_TNPR  ((AT91_REG *)   0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register
-#define AT91C_AES_RPR   ((AT91_REG *)   0xFFFA4100) // (PDC_AES) Receive Pointer Register
-#define AT91C_AES_PTSR  ((AT91_REG *)   0xFFFA4124) // (PDC_AES) PDC Transfer Status Register
-// ========== Register definition for AES peripheral ==========
-#define AT91C_AES_IVxR  ((AT91_REG *)   0xFFFA4060) // (AES) Initialization Vector x Register
-#define AT91C_AES_MR    ((AT91_REG *)   0xFFFA4004) // (AES) Mode Register
-#define AT91C_AES_VR    ((AT91_REG *)   0xFFFA40FC) // (AES) AES Version Register
-#define AT91C_AES_ODATAxR ((AT91_REG *)     0xFFFA4050) // (AES) Output Data x Register
-#define AT91C_AES_IDATAxR ((AT91_REG *)     0xFFFA4040) // (AES) Input Data x Register
-#define AT91C_AES_CR    ((AT91_REG *)   0xFFFA4000) // (AES) Control Register
-#define AT91C_AES_IDR   ((AT91_REG *)   0xFFFA4014) // (AES) Interrupt Disable Register
-#define AT91C_AES_IMR   ((AT91_REG *)   0xFFFA4018) // (AES) Interrupt Mask Register
-#define AT91C_AES_IER   ((AT91_REG *)   0xFFFA4010) // (AES) Interrupt Enable Register
-#define AT91C_AES_KEYWxR ((AT91_REG *)  0xFFFA4020) // (AES) Key Word x Register
-#define AT91C_AES_ISR   ((AT91_REG *)   0xFFFA401C) // (AES) Interrupt Status Register
-// ========== Register definition for PDC_TDES peripheral ==========
-#define AT91C_TDES_RNCR ((AT91_REG *)   0xFFFA8114) // (PDC_TDES) Receive Next Counter Register
-#define AT91C_TDES_TCR  ((AT91_REG *)   0xFFFA810C) // (PDC_TDES) Transmit Counter Register
-#define AT91C_TDES_RCR  ((AT91_REG *)   0xFFFA8104) // (PDC_TDES) Receive Counter Register
-#define AT91C_TDES_TNPR ((AT91_REG *)   0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register
-#define AT91C_TDES_RNPR ((AT91_REG *)   0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register
-#define AT91C_TDES_RPR  ((AT91_REG *)   0xFFFA8100) // (PDC_TDES) Receive Pointer Register
-#define AT91C_TDES_TNCR ((AT91_REG *)   0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register
-#define AT91C_TDES_TPR  ((AT91_REG *)   0xFFFA8108) // (PDC_TDES) Transmit Pointer Register
-#define AT91C_TDES_PTSR ((AT91_REG *)   0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register
-#define AT91C_TDES_PTCR ((AT91_REG *)   0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register
-// ========== Register definition for TDES peripheral ==========
-#define AT91C_TDES_KEY2WxR ((AT91_REG *)    0xFFFA8028) // (TDES) Key 2 Word x Register
-#define AT91C_TDES_KEY3WxR ((AT91_REG *)    0xFFFA8030) // (TDES) Key 3 Word x Register
-#define AT91C_TDES_IDR  ((AT91_REG *)   0xFFFA8014) // (TDES) Interrupt Disable Register
-#define AT91C_TDES_VR   ((AT91_REG *)   0xFFFA80FC) // (TDES) TDES Version Register
-#define AT91C_TDES_IVxR ((AT91_REG *)   0xFFFA8060) // (TDES) Initialization Vector x Register
-#define AT91C_TDES_ODATAxR ((AT91_REG *)    0xFFFA8050) // (TDES) Output Data x Register
-#define AT91C_TDES_IMR  ((AT91_REG *)   0xFFFA8018) // (TDES) Interrupt Mask Register
-#define AT91C_TDES_MR   ((AT91_REG *)   0xFFFA8004) // (TDES) Mode Register
-#define AT91C_TDES_CR   ((AT91_REG *)   0xFFFA8000) // (TDES) Control Register
-#define AT91C_TDES_IER  ((AT91_REG *)   0xFFFA8010) // (TDES) Interrupt Enable Register
-#define AT91C_TDES_ISR  ((AT91_REG *)   0xFFFA801C) // (TDES) Interrupt Status Register
-#define AT91C_TDES_IDATAxR ((AT91_REG *)    0xFFFA8040) // (TDES) Input Data x Register
-#define AT91C_TDES_KEY1WxR ((AT91_REG *)    0xFFFA8020) // (TDES) Key 1 Word x Register
+/* ***************************************************************************** */
+/*               REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 */
+/* ***************************************************************************** */
+/* ========== Register definition for SYS peripheral ========== */
+/* ========== Register definition for AIC peripheral ========== */
+#define AT91C_AIC_IVR              ( ( AT91_REG * ) 0xFFFFF100 ) /* (AIC) IRQ Vector Register */
+#define AT91C_AIC_SMR              ( ( AT91_REG * ) 0xFFFFF000 ) /* (AIC) Source Mode Register */
+#define AT91C_AIC_FVR              ( ( AT91_REG * ) 0xFFFFF104 ) /* (AIC) FIQ Vector Register */
+#define AT91C_AIC_DCR              ( ( AT91_REG * ) 0xFFFFF138 ) /* (AIC) Debug Control Register (Protect) */
+#define AT91C_AIC_EOICR            ( ( AT91_REG * ) 0xFFFFF130 ) /* (AIC) End of Interrupt Command Register */
+#define AT91C_AIC_SVR              ( ( AT91_REG * ) 0xFFFFF080 ) /* (AIC) Source Vector Register */
+#define AT91C_AIC_FFSR             ( ( AT91_REG * ) 0xFFFFF148 ) /* (AIC) Fast Forcing Status Register */
+#define AT91C_AIC_ICCR             ( ( AT91_REG * ) 0xFFFFF128 ) /* (AIC) Interrupt Clear Command Register */
+#define AT91C_AIC_ISR              ( ( AT91_REG * ) 0xFFFFF108 ) /* (AIC) Interrupt Status Register */
+#define AT91C_AIC_IMR              ( ( AT91_REG * ) 0xFFFFF110 ) /* (AIC) Interrupt Mask Register */
+#define AT91C_AIC_IPR              ( ( AT91_REG * ) 0xFFFFF10C ) /* (AIC) Interrupt Pending Register */
+#define AT91C_AIC_FFER             ( ( AT91_REG * ) 0xFFFFF140 ) /* (AIC) Fast Forcing Enable Register */
+#define AT91C_AIC_IECR             ( ( AT91_REG * ) 0xFFFFF120 ) /* (AIC) Interrupt Enable Command Register */
+#define AT91C_AIC_ISCR             ( ( AT91_REG * ) 0xFFFFF12C ) /* (AIC) Interrupt Set Command Register */
+#define AT91C_AIC_FFDR             ( ( AT91_REG * ) 0xFFFFF144 ) /* (AIC) Fast Forcing Disable Register */
+#define AT91C_AIC_CISR             ( ( AT91_REG * ) 0xFFFFF114 ) /* (AIC) Core Interrupt Status Register */
+#define AT91C_AIC_IDCR             ( ( AT91_REG * ) 0xFFFFF124 ) /* (AIC) Interrupt Disable Command Register */
+#define AT91C_AIC_SPU              ( ( AT91_REG * ) 0xFFFFF134 ) /* (AIC) Spurious Vector Register */
+/* ========== Register definition for PDC_DBGU peripheral ========== */
+#define AT91C_DBGU_TCR             ( ( AT91_REG * ) 0xFFFFF30C ) /* (PDC_DBGU) Transmit Counter Register */
+#define AT91C_DBGU_RNPR            ( ( AT91_REG * ) 0xFFFFF310 ) /* (PDC_DBGU) Receive Next Pointer Register */
+#define AT91C_DBGU_TNPR            ( ( AT91_REG * ) 0xFFFFF318 ) /* (PDC_DBGU) Transmit Next Pointer Register */
+#define AT91C_DBGU_TPR             ( ( AT91_REG * ) 0xFFFFF308 ) /* (PDC_DBGU) Transmit Pointer Register */
+#define AT91C_DBGU_RPR             ( ( AT91_REG * ) 0xFFFFF300 ) /* (PDC_DBGU) Receive Pointer Register */
+#define AT91C_DBGU_RCR             ( ( AT91_REG * ) 0xFFFFF304 ) /* (PDC_DBGU) Receive Counter Register */
+#define AT91C_DBGU_RNCR            ( ( AT91_REG * ) 0xFFFFF314 ) /* (PDC_DBGU) Receive Next Counter Register */
+#define AT91C_DBGU_PTCR            ( ( AT91_REG * ) 0xFFFFF320 ) /* (PDC_DBGU) PDC Transfer Control Register */
+#define AT91C_DBGU_PTSR            ( ( AT91_REG * ) 0xFFFFF324 ) /* (PDC_DBGU) PDC Transfer Status Register */
+#define AT91C_DBGU_TNCR            ( ( AT91_REG * ) 0xFFFFF31C ) /* (PDC_DBGU) Transmit Next Counter Register */
+/* ========== Register definition for DBGU peripheral ========== */
+#define AT91C_DBGU_EXID            ( ( AT91_REG * ) 0xFFFFF244 ) /* (DBGU) Chip ID Extension Register */
+#define AT91C_DBGU_BRGR            ( ( AT91_REG * ) 0xFFFFF220 ) /* (DBGU) Baud Rate Generator Register */
+#define AT91C_DBGU_IDR             ( ( AT91_REG * ) 0xFFFFF20C ) /* (DBGU) Interrupt Disable Register */
+#define AT91C_DBGU_CSR             ( ( AT91_REG * ) 0xFFFFF214 ) /* (DBGU) Channel Status Register */
+#define AT91C_DBGU_CIDR            ( ( AT91_REG * ) 0xFFFFF240 ) /* (DBGU) Chip ID Register */
+#define AT91C_DBGU_MR              ( ( AT91_REG * ) 0xFFFFF204 ) /* (DBGU) Mode Register */
+#define AT91C_DBGU_IMR             ( ( AT91_REG * ) 0xFFFFF210 ) /* (DBGU) Interrupt Mask Register */
+#define AT91C_DBGU_CR              ( ( AT91_REG * ) 0xFFFFF200 ) /* (DBGU) Control Register */
+#define AT91C_DBGU_FNTR            ( ( AT91_REG * ) 0xFFFFF248 ) /* (DBGU) Force NTRST Register */
+#define AT91C_DBGU_THR             ( ( AT91_REG * ) 0xFFFFF21C ) /* (DBGU) Transmitter Holding Register */
+#define AT91C_DBGU_RHR             ( ( AT91_REG * ) 0xFFFFF218 ) /* (DBGU) Receiver Holding Register */
+#define AT91C_DBGU_IER             ( ( AT91_REG * ) 0xFFFFF208 ) /* (DBGU) Interrupt Enable Register */
+/* ========== Register definition for PIOA peripheral ========== */
+#define AT91C_PIOA_ODR             ( ( AT91_REG * ) 0xFFFFF414 ) /* (PIOA) Output Disable Registerr */
+#define AT91C_PIOA_SODR            ( ( AT91_REG * ) 0xFFFFF430 ) /* (PIOA) Set Output Data Register */
+#define AT91C_PIOA_ISR             ( ( AT91_REG * ) 0xFFFFF44C ) /* (PIOA) Interrupt Status Register */
+#define AT91C_PIOA_ABSR            ( ( AT91_REG * ) 0xFFFFF478 ) /* (PIOA) AB Select Status Register */
+#define AT91C_PIOA_IER             ( ( AT91_REG * ) 0xFFFFF440 ) /* (PIOA) Interrupt Enable Register */
+#define AT91C_PIOA_PPUDR           ( ( AT91_REG * ) 0xFFFFF460 ) /* (PIOA) Pull-up Disable Register */
+#define AT91C_PIOA_IMR             ( ( AT91_REG * ) 0xFFFFF448 ) /* (PIOA) Interrupt Mask Register */
+#define AT91C_PIOA_PER             ( ( AT91_REG * ) 0xFFFFF400 ) /* (PIOA) PIO Enable Register */
+#define AT91C_PIOA_IFDR            ( ( AT91_REG * ) 0xFFFFF424 ) /* (PIOA) Input Filter Disable Register */
+#define AT91C_PIOA_OWDR            ( ( AT91_REG * ) 0xFFFFF4A4 ) /* (PIOA) Output Write Disable Register */
+#define AT91C_PIOA_MDSR            ( ( AT91_REG * ) 0xFFFFF458 ) /* (PIOA) Multi-driver Status Register */
+#define AT91C_PIOA_IDR             ( ( AT91_REG * ) 0xFFFFF444 ) /* (PIOA) Interrupt Disable Register */
+#define AT91C_PIOA_ODSR            ( ( AT91_REG * ) 0xFFFFF438 ) /* (PIOA) Output Data Status Register */
+#define AT91C_PIOA_PPUSR           ( ( AT91_REG * ) 0xFFFFF468 ) /* (PIOA) Pull-up Status Register */
+#define AT91C_PIOA_OWSR            ( ( AT91_REG * ) 0xFFFFF4A8 ) /* (PIOA) Output Write Status Register */
+#define AT91C_PIOA_BSR             ( ( AT91_REG * ) 0xFFFFF474 ) /* (PIOA) Select B Register */
+#define AT91C_PIOA_OWER            ( ( AT91_REG * ) 0xFFFFF4A0 ) /* (PIOA) Output Write Enable Register */
+#define AT91C_PIOA_IFER            ( ( AT91_REG * ) 0xFFFFF420 ) /* (PIOA) Input Filter Enable Register */
+#define AT91C_PIOA_PDSR            ( ( AT91_REG * ) 0xFFFFF43C ) /* (PIOA) Pin Data Status Register */
+#define AT91C_PIOA_PPUER           ( ( AT91_REG * ) 0xFFFFF464 ) /* (PIOA) Pull-up Enable Register */
+#define AT91C_PIOA_OSR             ( ( AT91_REG * ) 0xFFFFF418 ) /* (PIOA) Output Status Register */
+#define AT91C_PIOA_ASR             ( ( AT91_REG * ) 0xFFFFF470 ) /* (PIOA) Select A Register */
+#define AT91C_PIOA_MDDR            ( ( AT91_REG * ) 0xFFFFF454 ) /* (PIOA) Multi-driver Disable Register */
+#define AT91C_PIOA_CODR            ( ( AT91_REG * ) 0xFFFFF434 ) /* (PIOA) Clear Output Data Register */
+#define AT91C_PIOA_MDER            ( ( AT91_REG * ) 0xFFFFF450 ) /* (PIOA) Multi-driver Enable Register */
+#define AT91C_PIOA_PDR             ( ( AT91_REG * ) 0xFFFFF404 ) /* (PIOA) PIO Disable Register */
+#define AT91C_PIOA_IFSR            ( ( AT91_REG * ) 0xFFFFF428 ) /* (PIOA) Input Filter Status Register */
+#define AT91C_PIOA_OER             ( ( AT91_REG * ) 0xFFFFF410 ) /* (PIOA) Output Enable Register */
+#define AT91C_PIOA_PSR             ( ( AT91_REG * ) 0xFFFFF408 ) /* (PIOA) PIO Status Register */
+/* ========== Register definition for PIOB peripheral ========== */
+#define AT91C_PIOB_OWDR            ( ( AT91_REG * ) 0xFFFFF6A4 ) /* (PIOB) Output Write Disable Register */
+#define AT91C_PIOB_MDER            ( ( AT91_REG * ) 0xFFFFF650 ) /* (PIOB) Multi-driver Enable Register */
+#define AT91C_PIOB_PPUSR           ( ( AT91_REG * ) 0xFFFFF668 ) /* (PIOB) Pull-up Status Register */
+#define AT91C_PIOB_IMR             ( ( AT91_REG * ) 0xFFFFF648 ) /* (PIOB) Interrupt Mask Register */
+#define AT91C_PIOB_ASR             ( ( AT91_REG * ) 0xFFFFF670 ) /* (PIOB) Select A Register */
+#define AT91C_PIOB_PPUDR           ( ( AT91_REG * ) 0xFFFFF660 ) /* (PIOB) Pull-up Disable Register */
+#define AT91C_PIOB_PSR             ( ( AT91_REG * ) 0xFFFFF608 ) /* (PIOB) PIO Status Register */
+#define AT91C_PIOB_IER             ( ( AT91_REG * ) 0xFFFFF640 ) /* (PIOB) Interrupt Enable Register */
+#define AT91C_PIOB_CODR            ( ( AT91_REG * ) 0xFFFFF634 ) /* (PIOB) Clear Output Data Register */
+#define AT91C_PIOB_OWER            ( ( AT91_REG * ) 0xFFFFF6A0 ) /* (PIOB) Output Write Enable Register */
+#define AT91C_PIOB_ABSR            ( ( AT91_REG * ) 0xFFFFF678 ) /* (PIOB) AB Select Status Register */
+#define AT91C_PIOB_IFDR            ( ( AT91_REG * ) 0xFFFFF624 ) /* (PIOB) Input Filter Disable Register */
+#define AT91C_PIOB_PDSR            ( ( AT91_REG * ) 0xFFFFF63C ) /* (PIOB) Pin Data Status Register */
+#define AT91C_PIOB_IDR             ( ( AT91_REG * ) 0xFFFFF644 ) /* (PIOB) Interrupt Disable Register */
+#define AT91C_PIOB_OWSR            ( ( AT91_REG * ) 0xFFFFF6A8 ) /* (PIOB) Output Write Status Register */
+#define AT91C_PIOB_PDR             ( ( AT91_REG * ) 0xFFFFF604 ) /* (PIOB) PIO Disable Register */
+#define AT91C_PIOB_ODR             ( ( AT91_REG * ) 0xFFFFF614 ) /* (PIOB) Output Disable Registerr */
+#define AT91C_PIOB_IFSR            ( ( AT91_REG * ) 0xFFFFF628 ) /* (PIOB) Input Filter Status Register */
+#define AT91C_PIOB_PPUER           ( ( AT91_REG * ) 0xFFFFF664 ) /* (PIOB) Pull-up Enable Register */
+#define AT91C_PIOB_SODR            ( ( AT91_REG * ) 0xFFFFF630 ) /* (PIOB) Set Output Data Register */
+#define AT91C_PIOB_ISR             ( ( AT91_REG * ) 0xFFFFF64C ) /* (PIOB) Interrupt Status Register */
+#define AT91C_PIOB_ODSR            ( ( AT91_REG * ) 0xFFFFF638 ) /* (PIOB) Output Data Status Register */
+#define AT91C_PIOB_OSR             ( ( AT91_REG * ) 0xFFFFF618 ) /* (PIOB) Output Status Register */
+#define AT91C_PIOB_MDSR            ( ( AT91_REG * ) 0xFFFFF658 ) /* (PIOB) Multi-driver Status Register */
+#define AT91C_PIOB_IFER            ( ( AT91_REG * ) 0xFFFFF620 ) /* (PIOB) Input Filter Enable Register */
+#define AT91C_PIOB_BSR             ( ( AT91_REG * ) 0xFFFFF674 ) /* (PIOB) Select B Register */
+#define AT91C_PIOB_MDDR            ( ( AT91_REG * ) 0xFFFFF654 ) /* (PIOB) Multi-driver Disable Register */
+#define AT91C_PIOB_OER             ( ( AT91_REG * ) 0xFFFFF610 ) /* (PIOB) Output Enable Register */
+#define AT91C_PIOB_PER             ( ( AT91_REG * ) 0xFFFFF600 ) /* (PIOB) PIO Enable Register */
+/* ========== Register definition for CKGR peripheral ========== */
+#define AT91C_CKGR_MOR             ( ( AT91_REG * ) 0xFFFFFC20 ) /* (CKGR) Main Oscillator Register */
+#define AT91C_CKGR_PLLR            ( ( AT91_REG * ) 0xFFFFFC2C ) /* (CKGR) PLL Register */
+#define AT91C_CKGR_MCFR            ( ( AT91_REG * ) 0xFFFFFC24 ) /* (CKGR) Main Clock  Frequency Register */
+/* ========== Register definition for PMC peripheral ========== */
+#define AT91C_PMC_IDR              ( ( AT91_REG * ) 0xFFFFFC64 ) /* (PMC) Interrupt Disable Register */
+#define AT91C_PMC_MOR              ( ( AT91_REG * ) 0xFFFFFC20 ) /* (PMC) Main Oscillator Register */
+#define AT91C_PMC_PLLR             ( ( AT91_REG * ) 0xFFFFFC2C ) /* (PMC) PLL Register */
+#define AT91C_PMC_PCER             ( ( AT91_REG * ) 0xFFFFFC10 ) /* (PMC) Peripheral Clock Enable Register */
+#define AT91C_PMC_PCKR             ( ( AT91_REG * ) 0xFFFFFC40 ) /* (PMC) Programmable Clock Register */
+#define AT91C_PMC_MCKR             ( ( AT91_REG * ) 0xFFFFFC30 ) /* (PMC) Master Clock Register */
+#define AT91C_PMC_SCDR             ( ( AT91_REG * ) 0xFFFFFC04 ) /* (PMC) System Clock Disable Register */
+#define AT91C_PMC_PCDR             ( ( AT91_REG * ) 0xFFFFFC14 ) /* (PMC) Peripheral Clock Disable Register */
+#define AT91C_PMC_SCSR             ( ( AT91_REG * ) 0xFFFFFC08 ) /* (PMC) System Clock Status Register */
+#define AT91C_PMC_PCSR             ( ( AT91_REG * ) 0xFFFFFC18 ) /* (PMC) Peripheral Clock Status Register */
+#define AT91C_PMC_MCFR             ( ( AT91_REG * ) 0xFFFFFC24 ) /* (PMC) Main Clock  Frequency Register */
+#define AT91C_PMC_SCER             ( ( AT91_REG * ) 0xFFFFFC00 ) /* (PMC) System Clock Enable Register */
+#define AT91C_PMC_IMR              ( ( AT91_REG * ) 0xFFFFFC6C ) /* (PMC) Interrupt Mask Register */
+#define AT91C_PMC_IER              ( ( AT91_REG * ) 0xFFFFFC60 ) /* (PMC) Interrupt Enable Register */
+#define AT91C_PMC_SR               ( ( AT91_REG * ) 0xFFFFFC68 ) /* (PMC) Status Register */
+/* ========== Register definition for RSTC peripheral ========== */
+#define AT91C_RSTC_RCR             ( ( AT91_REG * ) 0xFFFFFD00 ) /* (RSTC) Reset Control Register */
+#define AT91C_RSTC_RMR             ( ( AT91_REG * ) 0xFFFFFD08 ) /* (RSTC) Reset Mode Register */
+#define AT91C_RSTC_RSR             ( ( AT91_REG * ) 0xFFFFFD04 ) /* (RSTC) Reset Status Register */
+/* ========== Register definition for RTTC peripheral ========== */
+#define AT91C_RTTC_RTSR            ( ( AT91_REG * ) 0xFFFFFD2C ) /* (RTTC) Real-time Status Register */
+#define AT91C_RTTC_RTMR            ( ( AT91_REG * ) 0xFFFFFD20 ) /* (RTTC) Real-time Mode Register */
+#define AT91C_RTTC_RTVR            ( ( AT91_REG * ) 0xFFFFFD28 ) /* (RTTC) Real-time Value Register */
+#define AT91C_RTTC_RTAR            ( ( AT91_REG * ) 0xFFFFFD24 ) /* (RTTC) Real-time Alarm Register */
+/* ========== Register definition for PITC peripheral ========== */
+#define AT91C_PITC_PIVR            ( ( AT91_REG * ) 0xFFFFFD38 ) /* (PITC) Period Interval Value Register */
+#define AT91C_PITC_PISR            ( ( AT91_REG * ) 0xFFFFFD34 ) /* (PITC) Period Interval Status Register */
+#define AT91C_PITC_PIIR            ( ( AT91_REG * ) 0xFFFFFD3C ) /* (PITC) Period Interval Image Register */
+#define AT91C_PITC_PIMR            ( ( AT91_REG * ) 0xFFFFFD30 ) /* (PITC) Period Interval Mode Register */
+/* ========== Register definition for WDTC peripheral ========== */
+#define AT91C_WDTC_WDCR            ( ( AT91_REG * ) 0xFFFFFD40 ) /* (WDTC) Watchdog Control Register */
+#define AT91C_WDTC_WDSR            ( ( AT91_REG * ) 0xFFFFFD48 ) /* (WDTC) Watchdog Status Register */
+#define AT91C_WDTC_WDMR            ( ( AT91_REG * ) 0xFFFFFD44 ) /* (WDTC) Watchdog Mode Register */
+/* ========== Register definition for VREG peripheral ========== */
+#define AT91C_VREG_MR              ( ( AT91_REG * ) 0xFFFFFD60 ) /* (VREG) Voltage Regulator Mode Register */
+/* ========== Register definition for MC peripheral ========== */
+#define AT91C_MC_ASR               ( ( AT91_REG * ) 0xFFFFFF04 ) /* (MC) MC Abort Status Register */
+#define AT91C_MC_RCR               ( ( AT91_REG * ) 0xFFFFFF00 ) /* (MC) MC Remap Control Register */
+#define AT91C_MC_FCR               ( ( AT91_REG * ) 0xFFFFFF64 ) /* (MC) MC Flash Command Register */
+#define AT91C_MC_AASR              ( ( AT91_REG * ) 0xFFFFFF08 ) /* (MC) MC Abort Address Status Register */
+#define AT91C_MC_FSR               ( ( AT91_REG * ) 0xFFFFFF68 ) /* (MC) MC Flash Status Register */
+#define AT91C_MC_FMR               ( ( AT91_REG * ) 0xFFFFFF60 ) /* (MC) MC Flash Mode Register */
+/* ========== Register definition for PDC_SPI1 peripheral ========== */
+#define AT91C_SPI1_PTCR            ( ( AT91_REG * ) 0xFFFE4120 ) /* (PDC_SPI1) PDC Transfer Control Register */
+#define AT91C_SPI1_RPR             ( ( AT91_REG * ) 0xFFFE4100 ) /* (PDC_SPI1) Receive Pointer Register */
+#define AT91C_SPI1_TNCR            ( ( AT91_REG * ) 0xFFFE411C ) /* (PDC_SPI1) Transmit Next Counter Register */
+#define AT91C_SPI1_TPR             ( ( AT91_REG * ) 0xFFFE4108 ) /* (PDC_SPI1) Transmit Pointer Register */
+#define AT91C_SPI1_TNPR            ( ( AT91_REG * ) 0xFFFE4118 ) /* (PDC_SPI1) Transmit Next Pointer Register */
+#define AT91C_SPI1_TCR             ( ( AT91_REG * ) 0xFFFE410C ) /* (PDC_SPI1) Transmit Counter Register */
+#define AT91C_SPI1_RCR             ( ( AT91_REG * ) 0xFFFE4104 ) /* (PDC_SPI1) Receive Counter Register */
+#define AT91C_SPI1_RNPR            ( ( AT91_REG * ) 0xFFFE4110 ) /* (PDC_SPI1) Receive Next Pointer Register */
+#define AT91C_SPI1_RNCR            ( ( AT91_REG * ) 0xFFFE4114 ) /* (PDC_SPI1) Receive Next Counter Register */
+#define AT91C_SPI1_PTSR            ( ( AT91_REG * ) 0xFFFE4124 ) /* (PDC_SPI1) PDC Transfer Status Register */
+/* ========== Register definition for SPI1 peripheral ========== */
+#define AT91C_SPI1_IMR             ( ( AT91_REG * ) 0xFFFE401C ) /* (SPI1) Interrupt Mask Register */
+#define AT91C_SPI1_IER             ( ( AT91_REG * ) 0xFFFE4014 ) /* (SPI1) Interrupt Enable Register */
+#define AT91C_SPI1_MR              ( ( AT91_REG * ) 0xFFFE4004 ) /* (SPI1) Mode Register */
+#define AT91C_SPI1_RDR             ( ( AT91_REG * ) 0xFFFE4008 ) /* (SPI1) Receive Data Register */
+#define AT91C_SPI1_IDR             ( ( AT91_REG * ) 0xFFFE4018 ) /* (SPI1) Interrupt Disable Register */
+#define AT91C_SPI1_SR              ( ( AT91_REG * ) 0xFFFE4010 ) /* (SPI1) Status Register */
+#define AT91C_SPI1_TDR             ( ( AT91_REG * ) 0xFFFE400C ) /* (SPI1) Transmit Data Register */
+#define AT91C_SPI1_CR              ( ( AT91_REG * ) 0xFFFE4000 ) /* (SPI1) Control Register */
+#define AT91C_SPI1_CSR             ( ( AT91_REG * ) 0xFFFE4030 ) /* (SPI1) Chip Select Register */
+/* ========== Register definition for PDC_SPI0 peripheral ========== */
+#define AT91C_SPI0_PTCR            ( ( AT91_REG * ) 0xFFFE0120 ) /* (PDC_SPI0) PDC Transfer Control Register */
+#define AT91C_SPI0_TPR             ( ( AT91_REG * ) 0xFFFE0108 ) /* (PDC_SPI0) Transmit Pointer Register */
+#define AT91C_SPI0_TCR             ( ( AT91_REG * ) 0xFFFE010C ) /* (PDC_SPI0) Transmit Counter Register */
+#define AT91C_SPI0_RCR             ( ( AT91_REG * ) 0xFFFE0104 ) /* (PDC_SPI0) Receive Counter Register */
+#define AT91C_SPI0_PTSR            ( ( AT91_REG * ) 0xFFFE0124 ) /* (PDC_SPI0) PDC Transfer Status Register */
+#define AT91C_SPI0_RNPR            ( ( AT91_REG * ) 0xFFFE0110 ) /* (PDC_SPI0) Receive Next Pointer Register */
+#define AT91C_SPI0_RPR             ( ( AT91_REG * ) 0xFFFE0100 ) /* (PDC_SPI0) Receive Pointer Register */
+#define AT91C_SPI0_TNCR            ( ( AT91_REG * ) 0xFFFE011C ) /* (PDC_SPI0) Transmit Next Counter Register */
+#define AT91C_SPI0_RNCR            ( ( AT91_REG * ) 0xFFFE0114 ) /* (PDC_SPI0) Receive Next Counter Register */
+#define AT91C_SPI0_TNPR            ( ( AT91_REG * ) 0xFFFE0118 ) /* (PDC_SPI0) Transmit Next Pointer Register */
+/* ========== Register definition for SPI0 peripheral ========== */
+#define AT91C_SPI0_IER             ( ( AT91_REG * ) 0xFFFE0014 ) /* (SPI0) Interrupt Enable Register */
+#define AT91C_SPI0_SR              ( ( AT91_REG * ) 0xFFFE0010 ) /* (SPI0) Status Register */
+#define AT91C_SPI0_IDR             ( ( AT91_REG * ) 0xFFFE0018 ) /* (SPI0) Interrupt Disable Register */
+#define AT91C_SPI0_CR              ( ( AT91_REG * ) 0xFFFE0000 ) /* (SPI0) Control Register */
+#define AT91C_SPI0_MR              ( ( AT91_REG * ) 0xFFFE0004 ) /* (SPI0) Mode Register */
+#define AT91C_SPI0_IMR             ( ( AT91_REG * ) 0xFFFE001C ) /* (SPI0) Interrupt Mask Register */
+#define AT91C_SPI0_TDR             ( ( AT91_REG * ) 0xFFFE000C ) /* (SPI0) Transmit Data Register */
+#define AT91C_SPI0_RDR             ( ( AT91_REG * ) 0xFFFE0008 ) /* (SPI0) Receive Data Register */
+#define AT91C_SPI0_CSR             ( ( AT91_REG * ) 0xFFFE0030 ) /* (SPI0) Chip Select Register */
+/* ========== Register definition for PDC_US1 peripheral ========== */
+#define AT91C_US1_RNCR             ( ( AT91_REG * ) 0xFFFC4114 ) /* (PDC_US1) Receive Next Counter Register */
+#define AT91C_US1_PTCR             ( ( AT91_REG * ) 0xFFFC4120 ) /* (PDC_US1) PDC Transfer Control Register */
+#define AT91C_US1_TCR              ( ( AT91_REG * ) 0xFFFC410C ) /* (PDC_US1) Transmit Counter Register */
+#define AT91C_US1_PTSR             ( ( AT91_REG * ) 0xFFFC4124 ) /* (PDC_US1) PDC Transfer Status Register */
+#define AT91C_US1_TNPR             ( ( AT91_REG * ) 0xFFFC4118 ) /* (PDC_US1) Transmit Next Pointer Register */
+#define AT91C_US1_RCR              ( ( AT91_REG * ) 0xFFFC4104 ) /* (PDC_US1) Receive Counter Register */
+#define AT91C_US1_RNPR             ( ( AT91_REG * ) 0xFFFC4110 ) /* (PDC_US1) Receive Next Pointer Register */
+#define AT91C_US1_RPR              ( ( AT91_REG * ) 0xFFFC4100 ) /* (PDC_US1) Receive Pointer Register */
+#define AT91C_US1_TNCR             ( ( AT91_REG * ) 0xFFFC411C ) /* (PDC_US1) Transmit Next Counter Register */
+#define AT91C_US1_TPR              ( ( AT91_REG * ) 0xFFFC4108 ) /* (PDC_US1) Transmit Pointer Register */
+/* ========== Register definition for US1 peripheral ========== */
+#define AT91C_US1_IF               ( ( AT91_REG * ) 0xFFFC404C ) /* (US1) IRDA_FILTER Register */
+#define AT91C_US1_NER              ( ( AT91_REG * ) 0xFFFC4044 ) /* (US1) Nb Errors Register */
+#define AT91C_US1_RTOR             ( ( AT91_REG * ) 0xFFFC4024 ) /* (US1) Receiver Time-out Register */
+#define AT91C_US1_CSR              ( ( AT91_REG * ) 0xFFFC4014 ) /* (US1) Channel Status Register */
+#define AT91C_US1_IDR              ( ( AT91_REG * ) 0xFFFC400C ) /* (US1) Interrupt Disable Register */
+#define AT91C_US1_IER              ( ( AT91_REG * ) 0xFFFC4008 ) /* (US1) Interrupt Enable Register */
+#define AT91C_US1_THR              ( ( AT91_REG * ) 0xFFFC401C ) /* (US1) Transmitter Holding Register */
+#define AT91C_US1_TTGR             ( ( AT91_REG * ) 0xFFFC4028 ) /* (US1) Transmitter Time-guard Register */
+#define AT91C_US1_RHR              ( ( AT91_REG * ) 0xFFFC4018 ) /* (US1) Receiver Holding Register */
+#define AT91C_US1_BRGR             ( ( AT91_REG * ) 0xFFFC4020 ) /* (US1) Baud Rate Generator Register */
+#define AT91C_US1_IMR              ( ( AT91_REG * ) 0xFFFC4010 ) /* (US1) Interrupt Mask Register */
+#define AT91C_US1_FIDI             ( ( AT91_REG * ) 0xFFFC4040 ) /* (US1) FI_DI_Ratio Register */
+#define AT91C_US1_CR               ( ( AT91_REG * ) 0xFFFC4000 ) /* (US1) Control Register */
+#define AT91C_US1_MR               ( ( AT91_REG * ) 0xFFFC4004 ) /* (US1) Mode Register */
+/* ========== Register definition for PDC_US0 peripheral ========== */
+#define AT91C_US0_TNPR             ( ( AT91_REG * ) 0xFFFC0118 ) /* (PDC_US0) Transmit Next Pointer Register */
+#define AT91C_US0_RNPR             ( ( AT91_REG * ) 0xFFFC0110 ) /* (PDC_US0) Receive Next Pointer Register */
+#define AT91C_US0_TCR              ( ( AT91_REG * ) 0xFFFC010C ) /* (PDC_US0) Transmit Counter Register */
+#define AT91C_US0_PTCR             ( ( AT91_REG * ) 0xFFFC0120 ) /* (PDC_US0) PDC Transfer Control Register */
+#define AT91C_US0_PTSR             ( ( AT91_REG * ) 0xFFFC0124 ) /* (PDC_US0) PDC Transfer Status Register */
+#define AT91C_US0_TNCR             ( ( AT91_REG * ) 0xFFFC011C ) /* (PDC_US0) Transmit Next Counter Register */
+#define AT91C_US0_TPR              ( ( AT91_REG * ) 0xFFFC0108 ) /* (PDC_US0) Transmit Pointer Register */
+#define AT91C_US0_RCR              ( ( AT91_REG * ) 0xFFFC0104 ) /* (PDC_US0) Receive Counter Register */
+#define AT91C_US0_RPR              ( ( AT91_REG * ) 0xFFFC0100 ) /* (PDC_US0) Receive Pointer Register */
+#define AT91C_US0_RNCR             ( ( AT91_REG * ) 0xFFFC0114 ) /* (PDC_US0) Receive Next Counter Register */
+/* ========== Register definition for US0 peripheral ========== */
+#define AT91C_US0_BRGR             ( ( AT91_REG * ) 0xFFFC0020 ) /* (US0) Baud Rate Generator Register */
+#define AT91C_US0_NER              ( ( AT91_REG * ) 0xFFFC0044 ) /* (US0) Nb Errors Register */
+#define AT91C_US0_CR               ( ( AT91_REG * ) 0xFFFC0000 ) /* (US0) Control Register */
+#define AT91C_US0_IMR              ( ( AT91_REG * ) 0xFFFC0010 ) /* (US0) Interrupt Mask Register */
+#define AT91C_US0_FIDI             ( ( AT91_REG * ) 0xFFFC0040 ) /* (US0) FI_DI_Ratio Register */
+#define AT91C_US0_TTGR             ( ( AT91_REG * ) 0xFFFC0028 ) /* (US0) Transmitter Time-guard Register */
+#define AT91C_US0_MR               ( ( AT91_REG * ) 0xFFFC0004 ) /* (US0) Mode Register */
+#define AT91C_US0_RTOR             ( ( AT91_REG * ) 0xFFFC0024 ) /* (US0) Receiver Time-out Register */
+#define AT91C_US0_CSR              ( ( AT91_REG * ) 0xFFFC0014 ) /* (US0) Channel Status Register */
+#define AT91C_US0_RHR              ( ( AT91_REG * ) 0xFFFC0018 ) /* (US0) Receiver Holding Register */
+#define AT91C_US0_IDR              ( ( AT91_REG * ) 0xFFFC000C ) /* (US0) Interrupt Disable Register */
+#define AT91C_US0_THR              ( ( AT91_REG * ) 0xFFFC001C ) /* (US0) Transmitter Holding Register */
+#define AT91C_US0_IF               ( ( AT91_REG * ) 0xFFFC004C ) /* (US0) IRDA_FILTER Register */
+#define AT91C_US0_IER              ( ( AT91_REG * ) 0xFFFC0008 ) /* (US0) Interrupt Enable Register */
+/* ========== Register definition for PDC_SSC peripheral ========== */
+#define AT91C_SSC_TNCR             ( ( AT91_REG * ) 0xFFFD411C ) /* (PDC_SSC) Transmit Next Counter Register */
+#define AT91C_SSC_RPR              ( ( AT91_REG * ) 0xFFFD4100 ) /* (PDC_SSC) Receive Pointer Register */
+#define AT91C_SSC_RNCR             ( ( AT91_REG * ) 0xFFFD4114 ) /* (PDC_SSC) Receive Next Counter Register */
+#define AT91C_SSC_TPR              ( ( AT91_REG * ) 0xFFFD4108 ) /* (PDC_SSC) Transmit Pointer Register */
+#define AT91C_SSC_PTCR             ( ( AT91_REG * ) 0xFFFD4120 ) /* (PDC_SSC) PDC Transfer Control Register */
+#define AT91C_SSC_TCR              ( ( AT91_REG * ) 0xFFFD410C ) /* (PDC_SSC) Transmit Counter Register */
+#define AT91C_SSC_RCR              ( ( AT91_REG * ) 0xFFFD4104 ) /* (PDC_SSC) Receive Counter Register */
+#define AT91C_SSC_RNPR             ( ( AT91_REG * ) 0xFFFD4110 ) /* (PDC_SSC) Receive Next Pointer Register */
+#define AT91C_SSC_TNPR             ( ( AT91_REG * ) 0xFFFD4118 ) /* (PDC_SSC) Transmit Next Pointer Register */
+#define AT91C_SSC_PTSR             ( ( AT91_REG * ) 0xFFFD4124 ) /* (PDC_SSC) PDC Transfer Status Register */
+/* ========== Register definition for SSC peripheral ========== */
+#define AT91C_SSC_RHR              ( ( AT91_REG * ) 0xFFFD4020 ) /* (SSC) Receive Holding Register */
+#define AT91C_SSC_RSHR             ( ( AT91_REG * ) 0xFFFD4030 ) /* (SSC) Receive Sync Holding Register */
+#define AT91C_SSC_TFMR             ( ( AT91_REG * ) 0xFFFD401C ) /* (SSC) Transmit Frame Mode Register */
+#define AT91C_SSC_IDR              ( ( AT91_REG * ) 0xFFFD4048 ) /* (SSC) Interrupt Disable Register */
+#define AT91C_SSC_THR              ( ( AT91_REG * ) 0xFFFD4024 ) /* (SSC) Transmit Holding Register */
+#define AT91C_SSC_RCMR             ( ( AT91_REG * ) 0xFFFD4010 ) /* (SSC) Receive Clock ModeRegister */
+#define AT91C_SSC_IER              ( ( AT91_REG * ) 0xFFFD4044 ) /* (SSC) Interrupt Enable Register */
+#define AT91C_SSC_TSHR             ( ( AT91_REG * ) 0xFFFD4034 ) /* (SSC) Transmit Sync Holding Register */
+#define AT91C_SSC_SR               ( ( AT91_REG * ) 0xFFFD4040 ) /* (SSC) Status Register */
+#define AT91C_SSC_CMR              ( ( AT91_REG * ) 0xFFFD4004 ) /* (SSC) Clock Mode Register */
+#define AT91C_SSC_TCMR             ( ( AT91_REG * ) 0xFFFD4018 ) /* (SSC) Transmit Clock Mode Register */
+#define AT91C_SSC_CR               ( ( AT91_REG * ) 0xFFFD4000 ) /* (SSC) Control Register */
+#define AT91C_SSC_IMR              ( ( AT91_REG * ) 0xFFFD404C ) /* (SSC) Interrupt Mask Register */
+#define AT91C_SSC_RFMR             ( ( AT91_REG * ) 0xFFFD4014 ) /* (SSC) Receive Frame Mode Register */
+/* ========== Register definition for TWI peripheral ========== */
+#define AT91C_TWI_IER              ( ( AT91_REG * ) 0xFFFB8024 ) /* (TWI) Interrupt Enable Register */
+#define AT91C_TWI_CR               ( ( AT91_REG * ) 0xFFFB8000 ) /* (TWI) Control Register */
+#define AT91C_TWI_SR               ( ( AT91_REG * ) 0xFFFB8020 ) /* (TWI) Status Register */
+#define AT91C_TWI_IMR              ( ( AT91_REG * ) 0xFFFB802C ) /* (TWI) Interrupt Mask Register */
+#define AT91C_TWI_THR              ( ( AT91_REG * ) 0xFFFB8034 ) /* (TWI) Transmit Holding Register */
+#define AT91C_TWI_IDR              ( ( AT91_REG * ) 0xFFFB8028 ) /* (TWI) Interrupt Disable Register */
+#define AT91C_TWI_IADR             ( ( AT91_REG * ) 0xFFFB800C ) /* (TWI) Internal Address Register */
+#define AT91C_TWI_MMR              ( ( AT91_REG * ) 0xFFFB8004 ) /* (TWI) Master Mode Register */
+#define AT91C_TWI_CWGR             ( ( AT91_REG * ) 0xFFFB8010 ) /* (TWI) Clock Waveform Generator Register */
+#define AT91C_TWI_RHR              ( ( AT91_REG * ) 0xFFFB8030 ) /* (TWI) Receive Holding Register */
+/* ========== Register definition for PWMC_CH3 peripheral ========== */
+#define AT91C_PWMC_CH3_CUPDR       ( ( AT91_REG * ) 0xFFFCC270 ) /* (PWMC_CH3) Channel Update Register */
+#define AT91C_PWMC_CH3_Reserved    ( ( AT91_REG * ) 0xFFFCC274 ) /* (PWMC_CH3) Reserved */
+#define AT91C_PWMC_CH3_CPRDR       ( ( AT91_REG * ) 0xFFFCC268 ) /* (PWMC_CH3) Channel Period Register */
+#define AT91C_PWMC_CH3_CDTYR       ( ( AT91_REG * ) 0xFFFCC264 ) /* (PWMC_CH3) Channel Duty Cycle Register */
+#define AT91C_PWMC_CH3_CCNTR       ( ( AT91_REG * ) 0xFFFCC26C ) /* (PWMC_CH3) Channel Counter Register */
+#define AT91C_PWMC_CH3_CMR         ( ( AT91_REG * ) 0xFFFCC260 ) /* (PWMC_CH3) Channel Mode Register */
+/* ========== Register definition for PWMC_CH2 peripheral ========== */
+#define AT91C_PWMC_CH2_Reserved    ( ( AT91_REG * ) 0xFFFCC254 ) /* (PWMC_CH2) Reserved */
+#define AT91C_PWMC_CH2_CMR         ( ( AT91_REG * ) 0xFFFCC240 ) /* (PWMC_CH2) Channel Mode Register */
+#define AT91C_PWMC_CH2_CCNTR       ( ( AT91_REG * ) 0xFFFCC24C ) /* (PWMC_CH2) Channel Counter Register */
+#define AT91C_PWMC_CH2_CPRDR       ( ( AT91_REG * ) 0xFFFCC248 ) /* (PWMC_CH2) Channel Period Register */
+#define AT91C_PWMC_CH2_CUPDR       ( ( AT91_REG * ) 0xFFFCC250 ) /* (PWMC_CH2) Channel Update Register */
+#define AT91C_PWMC_CH2_CDTYR       ( ( AT91_REG * ) 0xFFFCC244 ) /* (PWMC_CH2) Channel Duty Cycle Register */
+/* ========== Register definition for PWMC_CH1 peripheral ========== */
+#define AT91C_PWMC_CH1_Reserved    ( ( AT91_REG * ) 0xFFFCC234 ) /* (PWMC_CH1) Reserved */
+#define AT91C_PWMC_CH1_CUPDR       ( ( AT91_REG * ) 0xFFFCC230 ) /* (PWMC_CH1) Channel Update Register */
+#define AT91C_PWMC_CH1_CPRDR       ( ( AT91_REG * ) 0xFFFCC228 ) /* (PWMC_CH1) Channel Period Register */
+#define AT91C_PWMC_CH1_CCNTR       ( ( AT91_REG * ) 0xFFFCC22C ) /* (PWMC_CH1) Channel Counter Register */
+#define AT91C_PWMC_CH1_CDTYR       ( ( AT91_REG * ) 0xFFFCC224 ) /* (PWMC_CH1) Channel Duty Cycle Register */
+#define AT91C_PWMC_CH1_CMR         ( ( AT91_REG * ) 0xFFFCC220 ) /* (PWMC_CH1) Channel Mode Register */
+/* ========== Register definition for PWMC_CH0 peripheral ========== */
+#define AT91C_PWMC_CH0_Reserved    ( ( AT91_REG * ) 0xFFFCC214 ) /* (PWMC_CH0) Reserved */
+#define AT91C_PWMC_CH0_CPRDR       ( ( AT91_REG * ) 0xFFFCC208 ) /* (PWMC_CH0) Channel Period Register */
+#define AT91C_PWMC_CH0_CDTYR       ( ( AT91_REG * ) 0xFFFCC204 ) /* (PWMC_CH0) Channel Duty Cycle Register */
+#define AT91C_PWMC_CH0_CMR         ( ( AT91_REG * ) 0xFFFCC200 ) /* (PWMC_CH0) Channel Mode Register */
+#define AT91C_PWMC_CH0_CUPDR       ( ( AT91_REG * ) 0xFFFCC210 ) /* (PWMC_CH0) Channel Update Register */
+#define AT91C_PWMC_CH0_CCNTR       ( ( AT91_REG * ) 0xFFFCC20C ) /* (PWMC_CH0) Channel Counter Register */
+/* ========== Register definition for PWMC peripheral ========== */
+#define AT91C_PWMC_IDR             ( ( AT91_REG * ) 0xFFFCC014 ) /* (PWMC) PWMC Interrupt Disable Register */
+#define AT91C_PWMC_DIS             ( ( AT91_REG * ) 0xFFFCC008 ) /* (PWMC) PWMC Disable Register */
+#define AT91C_PWMC_IER             ( ( AT91_REG * ) 0xFFFCC010 ) /* (PWMC) PWMC Interrupt Enable Register */
+#define AT91C_PWMC_VR              ( ( AT91_REG * ) 0xFFFCC0FC ) /* (PWMC) PWMC Version Register */
+#define AT91C_PWMC_ISR             ( ( AT91_REG * ) 0xFFFCC01C ) /* (PWMC) PWMC Interrupt Status Register */
+#define AT91C_PWMC_SR              ( ( AT91_REG * ) 0xFFFCC00C ) /* (PWMC) PWMC Status Register */
+#define AT91C_PWMC_IMR             ( ( AT91_REG * ) 0xFFFCC018 ) /* (PWMC) PWMC Interrupt Mask Register */
+#define AT91C_PWMC_MR              ( ( AT91_REG * ) 0xFFFCC000 ) /* (PWMC) PWMC Mode Register */
+#define AT91C_PWMC_ENA             ( ( AT91_REG * ) 0xFFFCC004 ) /* (PWMC) PWMC Enable Register */
+/* ========== Register definition for UDP peripheral ========== */
+#define AT91C_UDP_IMR              ( ( AT91_REG * ) 0xFFFB0018 ) /* (UDP) Interrupt Mask Register */
+#define AT91C_UDP_FADDR            ( ( AT91_REG * ) 0xFFFB0008 ) /* (UDP) Function Address Register */
+#define AT91C_UDP_NUM              ( ( AT91_REG * ) 0xFFFB0000 ) /* (UDP) Frame Number Register */
+#define AT91C_UDP_FDR              ( ( AT91_REG * ) 0xFFFB0050 ) /* (UDP) Endpoint FIFO Data Register */
+#define AT91C_UDP_ISR              ( ( AT91_REG * ) 0xFFFB001C ) /* (UDP) Interrupt Status Register */
+#define AT91C_UDP_CSR              ( ( AT91_REG * ) 0xFFFB0030 ) /* (UDP) Endpoint Control and Status Register */
+#define AT91C_UDP_IDR              ( ( AT91_REG * ) 0xFFFB0014 ) /* (UDP) Interrupt Disable Register */
+#define AT91C_UDP_ICR              ( ( AT91_REG * ) 0xFFFB0020 ) /* (UDP) Interrupt Clear Register */
+#define AT91C_UDP_RSTEP            ( ( AT91_REG * ) 0xFFFB0028 ) /* (UDP) Reset Endpoint Register */
+#define AT91C_UDP_TXVC             ( ( AT91_REG * ) 0xFFFB0074 ) /* (UDP) Transceiver Control Register */
+#define AT91C_UDP_GLBSTATE         ( ( AT91_REG * ) 0xFFFB0004 ) /* (UDP) Global State Register */
+#define AT91C_UDP_IER              ( ( AT91_REG * ) 0xFFFB0010 ) /* (UDP) Interrupt Enable Register */
+/* ========== Register definition for TC0 peripheral ========== */
+#define AT91C_TC0_SR               ( ( AT91_REG * ) 0xFFFA0020 ) /* (TC0) Status Register */
+#define AT91C_TC0_RC               ( ( AT91_REG * ) 0xFFFA001C ) /* (TC0) Register C */
+#define AT91C_TC0_RB               ( ( AT91_REG * ) 0xFFFA0018 ) /* (TC0) Register B */
+#define AT91C_TC0_CCR              ( ( AT91_REG * ) 0xFFFA0000 ) /* (TC0) Channel Control Register */
+#define AT91C_TC0_CMR              ( ( AT91_REG * ) 0xFFFA0004 ) /* (TC0) Channel Mode Register (Capture Mode / Waveform Mode) */
+#define AT91C_TC0_IER              ( ( AT91_REG * ) 0xFFFA0024 ) /* (TC0) Interrupt Enable Register */
+#define AT91C_TC0_RA               ( ( AT91_REG * ) 0xFFFA0014 ) /* (TC0) Register A */
+#define AT91C_TC0_IDR              ( ( AT91_REG * ) 0xFFFA0028 ) /* (TC0) Interrupt Disable Register */
+#define AT91C_TC0_CV               ( ( AT91_REG * ) 0xFFFA0010 ) /* (TC0) Counter Value */
+#define AT91C_TC0_IMR              ( ( AT91_REG * ) 0xFFFA002C ) /* (TC0) Interrupt Mask Register */
+/* ========== Register definition for TC1 peripheral ========== */
+#define AT91C_TC1_RB               ( ( AT91_REG * ) 0xFFFA0058 ) /* (TC1) Register B */
+#define AT91C_TC1_CCR              ( ( AT91_REG * ) 0xFFFA0040 ) /* (TC1) Channel Control Register */
+#define AT91C_TC1_IER              ( ( AT91_REG * ) 0xFFFA0064 ) /* (TC1) Interrupt Enable Register */
+#define AT91C_TC1_IDR              ( ( AT91_REG * ) 0xFFFA0068 ) /* (TC1) Interrupt Disable Register */
+#define AT91C_TC1_SR               ( ( AT91_REG * ) 0xFFFA0060 ) /* (TC1) Status Register */
+#define AT91C_TC1_CMR              ( ( AT91_REG * ) 0xFFFA0044 ) /* (TC1) Channel Mode Register (Capture Mode / Waveform Mode) */
+#define AT91C_TC1_RA               ( ( AT91_REG * ) 0xFFFA0054 ) /* (TC1) Register A */
+#define AT91C_TC1_RC               ( ( AT91_REG * ) 0xFFFA005C ) /* (TC1) Register C */
+#define AT91C_TC1_IMR              ( ( AT91_REG * ) 0xFFFA006C ) /* (TC1) Interrupt Mask Register */
+#define AT91C_TC1_CV               ( ( AT91_REG * ) 0xFFFA0050 ) /* (TC1) Counter Value */
+/* ========== Register definition for TC2 peripheral ========== */
+#define AT91C_TC2_CMR              ( ( AT91_REG * ) 0xFFFA0084 ) /* (TC2) Channel Mode Register (Capture Mode / Waveform Mode) */
+#define AT91C_TC2_CCR              ( ( AT91_REG * ) 0xFFFA0080 ) /* (TC2) Channel Control Register */
+#define AT91C_TC2_CV               ( ( AT91_REG * ) 0xFFFA0090 ) /* (TC2) Counter Value */
+#define AT91C_TC2_RA               ( ( AT91_REG * ) 0xFFFA0094 ) /* (TC2) Register A */
+#define AT91C_TC2_RB               ( ( AT91_REG * ) 0xFFFA0098 ) /* (TC2) Register B */
+#define AT91C_TC2_IDR              ( ( AT91_REG * ) 0xFFFA00A8 ) /* (TC2) Interrupt Disable Register */
+#define AT91C_TC2_IMR              ( ( AT91_REG * ) 0xFFFA00AC ) /* (TC2) Interrupt Mask Register */
+#define AT91C_TC2_RC               ( ( AT91_REG * ) 0xFFFA009C ) /* (TC2) Register C */
+#define AT91C_TC2_IER              ( ( AT91_REG * ) 0xFFFA00A4 ) /* (TC2) Interrupt Enable Register */
+#define AT91C_TC2_SR               ( ( AT91_REG * ) 0xFFFA00A0 ) /* (TC2) Status Register */
+/* ========== Register definition for TCB peripheral ========== */
+#define AT91C_TCB_BMR              ( ( AT91_REG * ) 0xFFFA00C4 ) /* (TCB) TC Block Mode Register */
+#define AT91C_TCB_BCR              ( ( AT91_REG * ) 0xFFFA00C0 ) /* (TCB) TC Block Control Register */
+/* ========== Register definition for CAN_MB0 peripheral ========== */
+#define AT91C_CAN_MB0_MDL          ( ( AT91_REG * ) 0xFFFD0214 ) /* (CAN_MB0) MailBox Data Low Register */
+#define AT91C_CAN_MB0_MAM          ( ( AT91_REG * ) 0xFFFD0204 ) /* (CAN_MB0) MailBox Acceptance Mask Register */
+#define AT91C_CAN_MB0_MCR          ( ( AT91_REG * ) 0xFFFD021C ) /* (CAN_MB0) MailBox Control Register */
+#define AT91C_CAN_MB0_MID          ( ( AT91_REG * ) 0xFFFD0208 ) /* (CAN_MB0) MailBox ID Register */
+#define AT91C_CAN_MB0_MSR          ( ( AT91_REG * ) 0xFFFD0210 ) /* (CAN_MB0) MailBox Status Register */
+#define AT91C_CAN_MB0_MFID         ( ( AT91_REG * ) 0xFFFD020C ) /* (CAN_MB0) MailBox Family ID Register */
+#define AT91C_CAN_MB0_MDH          ( ( AT91_REG * ) 0xFFFD0218 ) /* (CAN_MB0) MailBox Data High Register */
+#define AT91C_CAN_MB0_MMR          ( ( AT91_REG * ) 0xFFFD0200 ) /* (CAN_MB0) MailBox Mode Register */
+/* ========== Register definition for CAN_MB1 peripheral ========== */
+#define AT91C_CAN_MB1_MDL          ( ( AT91_REG * ) 0xFFFD0234 ) /* (CAN_MB1) MailBox Data Low Register */
+#define AT91C_CAN_MB1_MID          ( ( AT91_REG * ) 0xFFFD0228 ) /* (CAN_MB1) MailBox ID Register */
+#define AT91C_CAN_MB1_MMR          ( ( AT91_REG * ) 0xFFFD0220 ) /* (CAN_MB1) MailBox Mode Register */
+#define AT91C_CAN_MB1_MSR          ( ( AT91_REG * ) 0xFFFD0230 ) /* (CAN_MB1) MailBox Status Register */
+#define AT91C_CAN_MB1_MAM          ( ( AT91_REG * ) 0xFFFD0224 ) /* (CAN_MB1) MailBox Acceptance Mask Register */
+#define AT91C_CAN_MB1_MDH          ( ( AT91_REG * ) 0xFFFD0238 ) /* (CAN_MB1) MailBox Data High Register */
+#define AT91C_CAN_MB1_MCR          ( ( AT91_REG * ) 0xFFFD023C ) /* (CAN_MB1) MailBox Control Register */
+#define AT91C_CAN_MB1_MFID         ( ( AT91_REG * ) 0xFFFD022C ) /* (CAN_MB1) MailBox Family ID Register */
+/* ========== Register definition for CAN_MB2 peripheral ========== */
+#define AT91C_CAN_MB2_MCR          ( ( AT91_REG * ) 0xFFFD025C ) /* (CAN_MB2) MailBox Control Register */
+#define AT91C_CAN_MB2_MDH          ( ( AT91_REG * ) 0xFFFD0258 ) /* (CAN_MB2) MailBox Data High Register */
+#define AT91C_CAN_MB2_MID          ( ( AT91_REG * ) 0xFFFD0248 ) /* (CAN_MB2) MailBox ID Register */
+#define AT91C_CAN_MB2_MDL          ( ( AT91_REG * ) 0xFFFD0254 ) /* (CAN_MB2) MailBox Data Low Register */
+#define AT91C_CAN_MB2_MMR          ( ( AT91_REG * ) 0xFFFD0240 ) /* (CAN_MB2) MailBox Mode Register */
+#define AT91C_CAN_MB2_MAM          ( ( AT91_REG * ) 0xFFFD0244 ) /* (CAN_MB2) MailBox Acceptance Mask Register */
+#define AT91C_CAN_MB2_MFID         ( ( AT91_REG * ) 0xFFFD024C ) /* (CAN_MB2) MailBox Family ID Register */
+#define AT91C_CAN_MB2_MSR          ( ( AT91_REG * ) 0xFFFD0250 ) /* (CAN_MB2) MailBox Status Register */
+/* ========== Register definition for CAN_MB3 peripheral ========== */
+#define AT91C_CAN_MB3_MFID         ( ( AT91_REG * ) 0xFFFD026C ) /* (CAN_MB3) MailBox Family ID Register */
+#define AT91C_CAN_MB3_MAM          ( ( AT91_REG * ) 0xFFFD0264 ) /* (CAN_MB3) MailBox Acceptance Mask Register */
+#define AT91C_CAN_MB3_MID          ( ( AT91_REG * ) 0xFFFD0268 ) /* (CAN_MB3) MailBox ID Register */
+#define AT91C_CAN_MB3_MCR          ( ( AT91_REG * ) 0xFFFD027C ) /* (CAN_MB3) MailBox Control Register */
+#define AT91C_CAN_MB3_MMR          ( ( AT91_REG * ) 0xFFFD0260 ) /* (CAN_MB3) MailBox Mode Register */
+#define AT91C_CAN_MB3_MSR          ( ( AT91_REG * ) 0xFFFD0270 ) /* (CAN_MB3) MailBox Status Register */
+#define AT91C_CAN_MB3_MDL          ( ( AT91_REG * ) 0xFFFD0274 ) /* (CAN_MB3) MailBox Data Low Register */
+#define AT91C_CAN_MB3_MDH          ( ( AT91_REG * ) 0xFFFD0278 ) /* (CAN_MB3) MailBox Data High Register */
+/* ========== Register definition for CAN_MB4 peripheral ========== */
+#define AT91C_CAN_MB4_MID          ( ( AT91_REG * ) 0xFFFD0288 ) /* (CAN_MB4) MailBox ID Register */
+#define AT91C_CAN_MB4_MMR          ( ( AT91_REG * ) 0xFFFD0280 ) /* (CAN_MB4) MailBox Mode Register */
+#define AT91C_CAN_MB4_MDH          ( ( AT91_REG * ) 0xFFFD0298 ) /* (CAN_MB4) MailBox Data High Register */
+#define AT91C_CAN_MB4_MFID         ( ( AT91_REG * ) 0xFFFD028C ) /* (CAN_MB4) MailBox Family ID Register */
+#define AT91C_CAN_MB4_MSR          ( ( AT91_REG * ) 0xFFFD0290 ) /* (CAN_MB4) MailBox Status Register */
+#define AT91C_CAN_MB4_MCR          ( ( AT91_REG * ) 0xFFFD029C ) /* (CAN_MB4) MailBox Control Register */
+#define AT91C_CAN_MB4_MDL          ( ( AT91_REG * ) 0xFFFD0294 ) /* (CAN_MB4) MailBox Data Low Register */
+#define AT91C_CAN_MB4_MAM          ( ( AT91_REG * ) 0xFFFD0284 ) /* (CAN_MB4) MailBox Acceptance Mask Register */
+/* ========== Register definition for CAN_MB5 peripheral ========== */
+#define AT91C_CAN_MB5_MSR          ( ( AT91_REG * ) 0xFFFD02B0 ) /* (CAN_MB5) MailBox Status Register */
+#define AT91C_CAN_MB5_MCR          ( ( AT91_REG * ) 0xFFFD02BC ) /* (CAN_MB5) MailBox Control Register */
+#define AT91C_CAN_MB5_MFID         ( ( AT91_REG * ) 0xFFFD02AC ) /* (CAN_MB5) MailBox Family ID Register */
+#define AT91C_CAN_MB5_MDH          ( ( AT91_REG * ) 0xFFFD02B8 ) /* (CAN_MB5) MailBox Data High Register */
+#define AT91C_CAN_MB5_MID          ( ( AT91_REG * ) 0xFFFD02A8 ) /* (CAN_MB5) MailBox ID Register */
+#define AT91C_CAN_MB5_MMR          ( ( AT91_REG * ) 0xFFFD02A0 ) /* (CAN_MB5) MailBox Mode Register */
+#define AT91C_CAN_MB5_MDL          ( ( AT91_REG * ) 0xFFFD02B4 ) /* (CAN_MB5) MailBox Data Low Register */
+#define AT91C_CAN_MB5_MAM          ( ( AT91_REG * ) 0xFFFD02A4 ) /* (CAN_MB5) MailBox Acceptance Mask Register */
+/* ========== Register definition for CAN_MB6 peripheral ========== */
+#define AT91C_CAN_MB6_MFID         ( ( AT91_REG * ) 0xFFFD02CC ) /* (CAN_MB6) MailBox Family ID Register */
+#define AT91C_CAN_MB6_MID          ( ( AT91_REG * ) 0xFFFD02C8 ) /* (CAN_MB6) MailBox ID Register */
+#define AT91C_CAN_MB6_MAM          ( ( AT91_REG * ) 0xFFFD02C4 ) /* (CAN_MB6) MailBox Acceptance Mask Register */
+#define AT91C_CAN_MB6_MSR          ( ( AT91_REG * ) 0xFFFD02D0 ) /* (CAN_MB6) MailBox Status Register */
+#define AT91C_CAN_MB6_MDL          ( ( AT91_REG * ) 0xFFFD02D4 ) /* (CAN_MB6) MailBox Data Low Register */
+#define AT91C_CAN_MB6_MCR          ( ( AT91_REG * ) 0xFFFD02DC ) /* (CAN_MB6) MailBox Control Register */
+#define AT91C_CAN_MB6_MDH          ( ( AT91_REG * ) 0xFFFD02D8 ) /* (CAN_MB6) MailBox Data High Register */
+#define AT91C_CAN_MB6_MMR          ( ( AT91_REG * ) 0xFFFD02C0 ) /* (CAN_MB6) MailBox Mode Register */
+/* ========== Register definition for CAN_MB7 peripheral ========== */
+#define AT91C_CAN_MB7_MCR          ( ( AT91_REG * ) 0xFFFD02FC ) /* (CAN_MB7) MailBox Control Register */
+#define AT91C_CAN_MB7_MDH          ( ( AT91_REG * ) 0xFFFD02F8 ) /* (CAN_MB7) MailBox Data High Register */
+#define AT91C_CAN_MB7_MFID         ( ( AT91_REG * ) 0xFFFD02EC ) /* (CAN_MB7) MailBox Family ID Register */
+#define AT91C_CAN_MB7_MDL          ( ( AT91_REG * ) 0xFFFD02F4 ) /* (CAN_MB7) MailBox Data Low Register */
+#define AT91C_CAN_MB7_MID          ( ( AT91_REG * ) 0xFFFD02E8 ) /* (CAN_MB7) MailBox ID Register */
+#define AT91C_CAN_MB7_MMR          ( ( AT91_REG * ) 0xFFFD02E0 ) /* (CAN_MB7) MailBox Mode Register */
+#define AT91C_CAN_MB7_MAM          ( ( AT91_REG * ) 0xFFFD02E4 ) /* (CAN_MB7) MailBox Acceptance Mask Register */
+#define AT91C_CAN_MB7_MSR          ( ( AT91_REG * ) 0xFFFD02F0 ) /* (CAN_MB7) MailBox Status Register */
+/* ========== Register definition for CAN peripheral ========== */
+#define AT91C_CAN_TCR              ( ( AT91_REG * ) 0xFFFD0024 ) /* (CAN) Transfer Command Register */
+#define AT91C_CAN_IMR              ( ( AT91_REG * ) 0xFFFD000C ) /* (CAN) Interrupt Mask Register */
+#define AT91C_CAN_IER              ( ( AT91_REG * ) 0xFFFD0004 ) /* (CAN) Interrupt Enable Register */
+#define AT91C_CAN_ECR              ( ( AT91_REG * ) 0xFFFD0020 ) /* (CAN) Error Counter Register */
+#define AT91C_CAN_TIMESTP          ( ( AT91_REG * ) 0xFFFD001C ) /* (CAN) Time Stamp Register */
+#define AT91C_CAN_MR               ( ( AT91_REG * ) 0xFFFD0000 ) /* (CAN) Mode Register */
+#define AT91C_CAN_IDR              ( ( AT91_REG * ) 0xFFFD0008 ) /* (CAN) Interrupt Disable Register */
+#define AT91C_CAN_ACR              ( ( AT91_REG * ) 0xFFFD0028 ) /* (CAN) Abort Command Register */
+#define AT91C_CAN_TIM              ( ( AT91_REG * ) 0xFFFD0018 ) /* (CAN) Timer Register */
+#define AT91C_CAN_SR               ( ( AT91_REG * ) 0xFFFD0010 ) /* (CAN) Status Register */
+#define AT91C_CAN_BR               ( ( AT91_REG * ) 0xFFFD0014 ) /* (CAN) Baudrate Register */
+#define AT91C_CAN_VR               ( ( AT91_REG * ) 0xFFFD00FC ) /* (CAN) Version Register */
+/* ========== Register definition for EMAC peripheral ========== */
+#define AT91C_EMAC_ISR             ( ( AT91_REG * ) 0xFFFDC024 ) /* (EMAC) Interrupt Status Register */
+#define AT91C_EMAC_SA4H            ( ( AT91_REG * ) 0xFFFDC0B4 ) /* (EMAC) Specific Address 4 Top, Last 2 bytes */
+#define AT91C_EMAC_SA1L            ( ( AT91_REG * ) 0xFFFDC098 ) /* (EMAC) Specific Address 1 Bottom, First 4 bytes */
+#define AT91C_EMAC_ELE             ( ( AT91_REG * ) 0xFFFDC078 ) /* (EMAC) Excessive Length Errors Register */
+#define AT91C_EMAC_LCOL            ( ( AT91_REG * ) 0xFFFDC05C ) /* (EMAC) Late Collision Register */
+#define AT91C_EMAC_RLE             ( ( AT91_REG * ) 0xFFFDC088 ) /* (EMAC) Receive Length Field Mismatch Register */
+#define AT91C_EMAC_WOL             ( ( AT91_REG * ) 0xFFFDC0C4 ) /* (EMAC) Wake On LAN Register */
+#define AT91C_EMAC_DTF             ( ( AT91_REG * ) 0xFFFDC058 ) /* (EMAC) Deferred Transmission Frame Register */
+#define AT91C_EMAC_TUND            ( ( AT91_REG * ) 0xFFFDC064 ) /* (EMAC) Transmit Underrun Error Register */
+#define AT91C_EMAC_NCR             ( ( AT91_REG * ) 0xFFFDC000 ) /* (EMAC) Network Control Register */
+#define AT91C_EMAC_SA4L            ( ( AT91_REG * ) 0xFFFDC0B0 ) /* (EMAC) Specific Address 4 Bottom, First 4 bytes */
+#define AT91C_EMAC_RSR             ( ( AT91_REG * ) 0xFFFDC020 ) /* (EMAC) Receive Status Register */
+#define AT91C_EMAC_SA3L            ( ( AT91_REG * ) 0xFFFDC0A8 ) /* (EMAC) Specific Address 3 Bottom, First 4 bytes */
+#define AT91C_EMAC_TSR             ( ( AT91_REG * ) 0xFFFDC014 ) /* (EMAC) Transmit Status Register */
+#define AT91C_EMAC_IDR             ( ( AT91_REG * ) 0xFFFDC02C ) /* (EMAC) Interrupt Disable Register */
+#define AT91C_EMAC_RSE             ( ( AT91_REG * ) 0xFFFDC074 ) /* (EMAC) Receive Symbol Errors Register */
+#define AT91C_EMAC_ECOL            ( ( AT91_REG * ) 0xFFFDC060 ) /* (EMAC) Excessive Collision Register */
+#define AT91C_EMAC_TID             ( ( AT91_REG * ) 0xFFFDC0B8 ) /* (EMAC) Type ID Checking Register */
+#define AT91C_EMAC_HRB             ( ( AT91_REG * ) 0xFFFDC090 ) /* (EMAC) Hash Address Bottom[31:0] */
+#define AT91C_EMAC_TBQP            ( ( AT91_REG * ) 0xFFFDC01C ) /* (EMAC) Transmit Buffer Queue Pointer */
+#define AT91C_EMAC_USRIO           ( ( AT91_REG * ) 0xFFFDC0C0 ) /* (EMAC) USER Input/Output Register */
+#define AT91C_EMAC_PTR             ( ( AT91_REG * ) 0xFFFDC038 ) /* (EMAC) Pause Time Register */
+#define AT91C_EMAC_SA2H            ( ( AT91_REG * ) 0xFFFDC0A4 ) /* (EMAC) Specific Address 2 Top, Last 2 bytes */
+#define AT91C_EMAC_ROV             ( ( AT91_REG * ) 0xFFFDC070 ) /* (EMAC) Receive Overrun Errors Register */
+#define AT91C_EMAC_ALE             ( ( AT91_REG * ) 0xFFFDC054 ) /* (EMAC) Alignment Error Register */
+#define AT91C_EMAC_RJA             ( ( AT91_REG * ) 0xFFFDC07C ) /* (EMAC) Receive Jabbers Register */
+#define AT91C_EMAC_RBQP            ( ( AT91_REG * ) 0xFFFDC018 ) /* (EMAC) Receive Buffer Queue Pointer */
+#define AT91C_EMAC_TPF             ( ( AT91_REG * ) 0xFFFDC08C ) /* (EMAC) Transmitted Pause Frames Register */
+#define AT91C_EMAC_NCFGR           ( ( AT91_REG * ) 0xFFFDC004 ) /* (EMAC) Network Configuration Register */
+#define AT91C_EMAC_HRT             ( ( AT91_REG * ) 0xFFFDC094 ) /* (EMAC) Hash Address Top[63:32] */
+#define AT91C_EMAC_USF             ( ( AT91_REG * ) 0xFFFDC080 ) /* (EMAC) Undersize Frames Register */
+#define AT91C_EMAC_FCSE            ( ( AT91_REG * ) 0xFFFDC050 ) /* (EMAC) Frame Check Sequence Error Register */
+#define AT91C_EMAC_TPQ             ( ( AT91_REG * ) 0xFFFDC0BC ) /* (EMAC) Transmit Pause Quantum Register */
+#define AT91C_EMAC_MAN             ( ( AT91_REG * ) 0xFFFDC034 ) /* (EMAC) PHY Maintenance Register */
+#define AT91C_EMAC_FTO             ( ( AT91_REG * ) 0xFFFDC040 ) /* (EMAC) Frames Transmitted OK Register */
+#define AT91C_EMAC_REV             ( ( AT91_REG * ) 0xFFFDC0FC ) /* (EMAC) Revision Register */
+#define AT91C_EMAC_IMR             ( ( AT91_REG * ) 0xFFFDC030 ) /* (EMAC) Interrupt Mask Register */
+#define AT91C_EMAC_SCF             ( ( AT91_REG * ) 0xFFFDC044 ) /* (EMAC) Single Collision Frame Register */
+#define AT91C_EMAC_PFR             ( ( AT91_REG * ) 0xFFFDC03C ) /* (EMAC) Pause Frames received Register */
+#define AT91C_EMAC_MCF             ( ( AT91_REG * ) 0xFFFDC048 ) /* (EMAC) Multiple Collision Frame Register */
+#define AT91C_EMAC_NSR             ( ( AT91_REG * ) 0xFFFDC008 ) /* (EMAC) Network Status Register */
+#define AT91C_EMAC_SA2L            ( ( AT91_REG * ) 0xFFFDC0A0 ) /* (EMAC) Specific Address 2 Bottom, First 4 bytes */
+#define AT91C_EMAC_FRO             ( ( AT91_REG * ) 0xFFFDC04C ) /* (EMAC) Frames Received OK Register */
+#define AT91C_EMAC_IER             ( ( AT91_REG * ) 0xFFFDC028 ) /* (EMAC) Interrupt Enable Register */
+#define AT91C_EMAC_SA1H            ( ( AT91_REG * ) 0xFFFDC09C ) /* (EMAC) Specific Address 1 Top, Last 2 bytes */
+#define AT91C_EMAC_CSE             ( ( AT91_REG * ) 0xFFFDC068 ) /* (EMAC) Carrier Sense Error Register */
+#define AT91C_EMAC_SA3H            ( ( AT91_REG * ) 0xFFFDC0AC ) /* (EMAC) Specific Address 3 Top, Last 2 bytes */
+#define AT91C_EMAC_RRE             ( ( AT91_REG * ) 0xFFFDC06C ) /* (EMAC) Receive Ressource Error Register */
+#define AT91C_EMAC_STE             ( ( AT91_REG * ) 0xFFFDC084 ) /* (EMAC) SQE Test Error Register */
+/* ========== Register definition for PDC_ADC peripheral ========== */
+#define AT91C_ADC_PTSR             ( ( AT91_REG * ) 0xFFFD8124 ) /* (PDC_ADC) PDC Transfer Status Register */
+#define AT91C_ADC_PTCR             ( ( AT91_REG * ) 0xFFFD8120 ) /* (PDC_ADC) PDC Transfer Control Register */
+#define AT91C_ADC_TNPR             ( ( AT91_REG * ) 0xFFFD8118 ) /* (PDC_ADC) Transmit Next Pointer Register */
+#define AT91C_ADC_TNCR             ( ( AT91_REG * ) 0xFFFD811C ) /* (PDC_ADC) Transmit Next Counter Register */
+#define AT91C_ADC_RNPR             ( ( AT91_REG * ) 0xFFFD8110 ) /* (PDC_ADC) Receive Next Pointer Register */
+#define AT91C_ADC_RNCR             ( ( AT91_REG * ) 0xFFFD8114 ) /* (PDC_ADC) Receive Next Counter Register */
+#define AT91C_ADC_RPR              ( ( AT91_REG * ) 0xFFFD8100 ) /* (PDC_ADC) Receive Pointer Register */
+#define AT91C_ADC_TCR              ( ( AT91_REG * ) 0xFFFD810C ) /* (PDC_ADC) Transmit Counter Register */
+#define AT91C_ADC_TPR              ( ( AT91_REG * ) 0xFFFD8108 ) /* (PDC_ADC) Transmit Pointer Register */
+#define AT91C_ADC_RCR              ( ( AT91_REG * ) 0xFFFD8104 ) /* (PDC_ADC) Receive Counter Register */
+/* ========== Register definition for ADC peripheral ========== */
+#define AT91C_ADC_CDR2             ( ( AT91_REG * ) 0xFFFD8038 ) /* (ADC) ADC Channel Data Register 2 */
+#define AT91C_ADC_CDR3             ( ( AT91_REG * ) 0xFFFD803C ) /* (ADC) ADC Channel Data Register 3 */
+#define AT91C_ADC_CDR0             ( ( AT91_REG * ) 0xFFFD8030 ) /* (ADC) ADC Channel Data Register 0 */
+#define AT91C_ADC_CDR5             ( ( AT91_REG * ) 0xFFFD8044 ) /* (ADC) ADC Channel Data Register 5 */
+#define AT91C_ADC_CHDR             ( ( AT91_REG * ) 0xFFFD8014 ) /* (ADC) ADC Channel Disable Register */
+#define AT91C_ADC_SR               ( ( AT91_REG * ) 0xFFFD801C ) /* (ADC) ADC Status Register */
+#define AT91C_ADC_CDR4             ( ( AT91_REG * ) 0xFFFD8040 ) /* (ADC) ADC Channel Data Register 4 */
+#define AT91C_ADC_CDR1             ( ( AT91_REG * ) 0xFFFD8034 ) /* (ADC) ADC Channel Data Register 1 */
+#define AT91C_ADC_LCDR             ( ( AT91_REG * ) 0xFFFD8020 ) /* (ADC) ADC Last Converted Data Register */
+#define AT91C_ADC_IDR              ( ( AT91_REG * ) 0xFFFD8028 ) /* (ADC) ADC Interrupt Disable Register */
+#define AT91C_ADC_CR               ( ( AT91_REG * ) 0xFFFD8000 ) /* (ADC) ADC Control Register */
+#define AT91C_ADC_CDR7             ( ( AT91_REG * ) 0xFFFD804C ) /* (ADC) ADC Channel Data Register 7 */
+#define AT91C_ADC_CDR6             ( ( AT91_REG * ) 0xFFFD8048 ) /* (ADC) ADC Channel Data Register 6 */
+#define AT91C_ADC_IER              ( ( AT91_REG * ) 0xFFFD8024 ) /* (ADC) ADC Interrupt Enable Register */
+#define AT91C_ADC_CHER             ( ( AT91_REG * ) 0xFFFD8010 ) /* (ADC) ADC Channel Enable Register */
+#define AT91C_ADC_CHSR             ( ( AT91_REG * ) 0xFFFD8018 ) /* (ADC) ADC Channel Status Register */
+#define AT91C_ADC_MR               ( ( AT91_REG * ) 0xFFFD8004 ) /* (ADC) ADC Mode Register */
+#define AT91C_ADC_IMR              ( ( AT91_REG * ) 0xFFFD802C ) /* (ADC) ADC Interrupt Mask Register */
+/* ========== Register definition for PDC_AES peripheral ========== */
+#define AT91C_AES_TPR              ( ( AT91_REG * ) 0xFFFA4108 ) /* (PDC_AES) Transmit Pointer Register */
+#define AT91C_AES_PTCR             ( ( AT91_REG * ) 0xFFFA4120 ) /* (PDC_AES) PDC Transfer Control Register */
+#define AT91C_AES_RNPR             ( ( AT91_REG * ) 0xFFFA4110 ) /* (PDC_AES) Receive Next Pointer Register */
+#define AT91C_AES_TNCR             ( ( AT91_REG * ) 0xFFFA411C ) /* (PDC_AES) Transmit Next Counter Register */
+#define AT91C_AES_TCR              ( ( AT91_REG * ) 0xFFFA410C ) /* (PDC_AES) Transmit Counter Register */
+#define AT91C_AES_RCR              ( ( AT91_REG * ) 0xFFFA4104 ) /* (PDC_AES) Receive Counter Register */
+#define AT91C_AES_RNCR             ( ( AT91_REG * ) 0xFFFA4114 ) /* (PDC_AES) Receive Next Counter Register */
+#define AT91C_AES_TNPR             ( ( AT91_REG * ) 0xFFFA4118 ) /* (PDC_AES) Transmit Next Pointer Register */
+#define AT91C_AES_RPR              ( ( AT91_REG * ) 0xFFFA4100 ) /* (PDC_AES) Receive Pointer Register */
+#define AT91C_AES_PTSR             ( ( AT91_REG * ) 0xFFFA4124 ) /* (PDC_AES) PDC Transfer Status Register */
+/* ========== Register definition for AES peripheral ========== */
+#define AT91C_AES_IVxR             ( ( AT91_REG * ) 0xFFFA4060 ) /* (AES) Initialization Vector x Register */
+#define AT91C_AES_MR               ( ( AT91_REG * ) 0xFFFA4004 ) /* (AES) Mode Register */
+#define AT91C_AES_VR               ( ( AT91_REG * ) 0xFFFA40FC ) /* (AES) AES Version Register */
+#define AT91C_AES_ODATAxR          ( ( AT91_REG * ) 0xFFFA4050 ) /* (AES) Output Data x Register */
+#define AT91C_AES_IDATAxR          ( ( AT91_REG * ) 0xFFFA4040 ) /* (AES) Input Data x Register */
+#define AT91C_AES_CR               ( ( AT91_REG * ) 0xFFFA4000 ) /* (AES) Control Register */
+#define AT91C_AES_IDR              ( ( AT91_REG * ) 0xFFFA4014 ) /* (AES) Interrupt Disable Register */
+#define AT91C_AES_IMR              ( ( AT91_REG * ) 0xFFFA4018 ) /* (AES) Interrupt Mask Register */
+#define AT91C_AES_IER              ( ( AT91_REG * ) 0xFFFA4010 ) /* (AES) Interrupt Enable Register */
+#define AT91C_AES_KEYWxR           ( ( AT91_REG * ) 0xFFFA4020 ) /* (AES) Key Word x Register */
+#define AT91C_AES_ISR              ( ( AT91_REG * ) 0xFFFA401C ) /* (AES) Interrupt Status Register */
+/* ========== Register definition for PDC_TDES peripheral ========== */
+#define AT91C_TDES_RNCR            ( ( AT91_REG * ) 0xFFFA8114 ) /* (PDC_TDES) Receive Next Counter Register */
+#define AT91C_TDES_TCR             ( ( AT91_REG * ) 0xFFFA810C ) /* (PDC_TDES) Transmit Counter Register */
+#define AT91C_TDES_RCR             ( ( AT91_REG * ) 0xFFFA8104 ) /* (PDC_TDES) Receive Counter Register */
+#define AT91C_TDES_TNPR            ( ( AT91_REG * ) 0xFFFA8118 ) /* (PDC_TDES) Transmit Next Pointer Register */
+#define AT91C_TDES_RNPR            ( ( AT91_REG * ) 0xFFFA8110 ) /* (PDC_TDES) Receive Next Pointer Register */
+#define AT91C_TDES_RPR             ( ( AT91_REG * ) 0xFFFA8100 ) /* (PDC_TDES) Receive Pointer Register */
+#define AT91C_TDES_TNCR            ( ( AT91_REG * ) 0xFFFA811C ) /* (PDC_TDES) Transmit Next Counter Register */
+#define AT91C_TDES_TPR             ( ( AT91_REG * ) 0xFFFA8108 ) /* (PDC_TDES) Transmit Pointer Register */
+#define AT91C_TDES_PTSR            ( ( AT91_REG * ) 0xFFFA8124 ) /* (PDC_TDES) PDC Transfer Status Register */
+#define AT91C_TDES_PTCR            ( ( AT91_REG * ) 0xFFFA8120 ) /* (PDC_TDES) PDC Transfer Control Register */
+/* ========== Register definition for TDES peripheral ========== */
+#define AT91C_TDES_KEY2WxR         ( ( AT91_REG * ) 0xFFFA8028 ) /* (TDES) Key 2 Word x Register */
+#define AT91C_TDES_KEY3WxR         ( ( AT91_REG * ) 0xFFFA8030 ) /* (TDES) Key 3 Word x Register */
+#define AT91C_TDES_IDR             ( ( AT91_REG * ) 0xFFFA8014 ) /* (TDES) Interrupt Disable Register */
+#define AT91C_TDES_VR              ( ( AT91_REG * ) 0xFFFA80FC ) /* (TDES) TDES Version Register */
+#define AT91C_TDES_IVxR            ( ( AT91_REG * ) 0xFFFA8060 ) /* (TDES) Initialization Vector x Register */
+#define AT91C_TDES_ODATAxR         ( ( AT91_REG * ) 0xFFFA8050 ) /* (TDES) Output Data x Register */
+#define AT91C_TDES_IMR             ( ( AT91_REG * ) 0xFFFA8018 ) /* (TDES) Interrupt Mask Register */
+#define AT91C_TDES_MR              ( ( AT91_REG * ) 0xFFFA8004 ) /* (TDES) Mode Register */
+#define AT91C_TDES_CR              ( ( AT91_REG * ) 0xFFFA8000 ) /* (TDES) Control Register */
+#define AT91C_TDES_IER             ( ( AT91_REG * ) 0xFFFA8010 ) /* (TDES) Interrupt Enable Register */
+#define AT91C_TDES_ISR             ( ( AT91_REG * ) 0xFFFA801C ) /* (TDES) Interrupt Status Register */
+#define AT91C_TDES_IDATAxR         ( ( AT91_REG * ) 0xFFFA8040 ) /* (TDES) Input Data x Register */
+#define AT91C_TDES_KEY1WxR         ( ( AT91_REG * ) 0xFFFA8020 ) /* (TDES) Key 1 Word x Register */
 
-// *****************************************************************************
-//               PIO DEFINITIONS FOR AT91SAM7X256
-// *****************************************************************************
-#define AT91C_PIO_PA0        ((unsigned int) 1 <<  0) // Pin Controlled by PA0
-#define AT91C_PA0_RXD0     ((unsigned int) AT91C_PIO_PA0) //  USART 0 Receive Data
-#define AT91C_PIO_PA1        ((unsigned int) 1 <<  1) // Pin Controlled by PA1
-#define AT91C_PA1_TXD0     ((unsigned int) AT91C_PIO_PA1) //  USART 0 Transmit Data
-#define AT91C_PIO_PA10       ((unsigned int) 1 << 10) // Pin Controlled by PA10
-#define AT91C_PA10_TWD      ((unsigned int) AT91C_PIO_PA10) //  TWI Two-wire Serial Data
-#define AT91C_PIO_PA11       ((unsigned int) 1 << 11) // Pin Controlled by PA11
-#define AT91C_PA11_TWCK     ((unsigned int) AT91C_PIO_PA11) //  TWI Two-wire Serial Clock
-#define AT91C_PIO_PA12       ((unsigned int) 1 << 12) // Pin Controlled by PA12
-#define AT91C_PA12_NPCS00   ((unsigned int) AT91C_PIO_PA12) //  SPI 0 Peripheral Chip Select 0
-#define AT91C_PIO_PA13       ((unsigned int) 1 << 13) // Pin Controlled by PA13
-#define AT91C_PA13_NPCS01   ((unsigned int) AT91C_PIO_PA13) //  SPI 0 Peripheral Chip Select 1
-#define AT91C_PA13_PCK1     ((unsigned int) AT91C_PIO_PA13) //  PMC Programmable Clock Output 1
-#define AT91C_PIO_PA14       ((unsigned int) 1 << 14) // Pin Controlled by PA14
-#define AT91C_PA14_NPCS02   ((unsigned int) AT91C_PIO_PA14) //  SPI 0 Peripheral Chip Select 2
-#define AT91C_PA14_IRQ1     ((unsigned int) AT91C_PIO_PA14) //  External Interrupt 1
-#define AT91C_PIO_PA15       ((unsigned int) 1 << 15) // Pin Controlled by PA15
-#define AT91C_PA15_NPCS03   ((unsigned int) AT91C_PIO_PA15) //  SPI 0 Peripheral Chip Select 3
-#define AT91C_PA15_TCLK2    ((unsigned int) AT91C_PIO_PA15) //  Timer Counter 2 external clock input
-#define AT91C_PIO_PA16       ((unsigned int) 1 << 16) // Pin Controlled by PA16
-#define AT91C_PA16_MISO0    ((unsigned int) AT91C_PIO_PA16) //  SPI 0 Master In Slave
-#define AT91C_PIO_PA17       ((unsigned int) 1 << 17) // Pin Controlled by PA17
-#define AT91C_PA17_MOSI0    ((unsigned int) AT91C_PIO_PA17) //  SPI 0 Master Out Slave
-#define AT91C_PIO_PA18       ((unsigned int) 1 << 18) // Pin Controlled by PA18
-#define AT91C_PA18_SPCK0    ((unsigned int) AT91C_PIO_PA18) //  SPI 0 Serial Clock
-#define AT91C_PIO_PA19       ((unsigned int) 1 << 19) // Pin Controlled by PA19
-#define AT91C_PA19_CANRX    ((unsigned int) AT91C_PIO_PA19) //  CAN Receive
-#define AT91C_PIO_PA2        ((unsigned int) 1 <<  2) // Pin Controlled by PA2
-#define AT91C_PA2_SCK0     ((unsigned int) AT91C_PIO_PA2) //  USART 0 Serial Clock
-#define AT91C_PA2_NPCS11   ((unsigned int) AT91C_PIO_PA2) //  SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PA20       ((unsigned int) 1 << 20) // Pin Controlled by PA20
-#define AT91C_PA20_CANTX    ((unsigned int) AT91C_PIO_PA20) //  CAN Transmit
-#define AT91C_PIO_PA21       ((unsigned int) 1 << 21) // Pin Controlled by PA21
-#define AT91C_PA21_TF       ((unsigned int) AT91C_PIO_PA21) //  SSC Transmit Frame Sync
-#define AT91C_PA21_NPCS10   ((unsigned int) AT91C_PIO_PA21) //  SPI 1 Peripheral Chip Select 0
-#define AT91C_PIO_PA22       ((unsigned int) 1 << 22) // Pin Controlled by PA22
-#define AT91C_PA22_TK       ((unsigned int) AT91C_PIO_PA22) //  SSC Transmit Clock
-#define AT91C_PA22_SPCK1    ((unsigned int) AT91C_PIO_PA22) //  SPI 1 Serial Clock
-#define AT91C_PIO_PA23       ((unsigned int) 1 << 23) // Pin Controlled by PA23
-#define AT91C_PA23_TD       ((unsigned int) AT91C_PIO_PA23) //  SSC Transmit data
-#define AT91C_PA23_MOSI1    ((unsigned int) AT91C_PIO_PA23) //  SPI 1 Master Out Slave
-#define AT91C_PIO_PA24       ((unsigned int) 1 << 24) // Pin Controlled by PA24
-#define AT91C_PA24_RD       ((unsigned int) AT91C_PIO_PA24) //  SSC Receive Data
-#define AT91C_PA24_MISO1    ((unsigned int) AT91C_PIO_PA24) //  SPI 1 Master In Slave
-#define AT91C_PIO_PA25       ((unsigned int) 1 << 25) // Pin Controlled by PA25
-#define AT91C_PA25_RK       ((unsigned int) AT91C_PIO_PA25) //  SSC Receive Clock
-#define AT91C_PA25_NPCS11   ((unsigned int) AT91C_PIO_PA25) //  SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PA26       ((unsigned int) 1 << 26) // Pin Controlled by PA26
-#define AT91C_PA26_RF       ((unsigned int) AT91C_PIO_PA26) //  SSC Receive Frame Sync
-#define AT91C_PA26_NPCS12   ((unsigned int) AT91C_PIO_PA26) //  SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PA27       ((unsigned int) 1 << 27) // Pin Controlled by PA27
-#define AT91C_PA27_DRXD     ((unsigned int) AT91C_PIO_PA27) //  DBGU Debug Receive Data
-#define AT91C_PA27_PCK3     ((unsigned int) AT91C_PIO_PA27) //  PMC Programmable Clock Output 3
-#define AT91C_PIO_PA28       ((unsigned int) 1 << 28) // Pin Controlled by PA28
-#define AT91C_PA28_DTXD     ((unsigned int) AT91C_PIO_PA28) //  DBGU Debug Transmit Data
-#define AT91C_PIO_PA29       ((unsigned int) 1 << 29) // Pin Controlled by PA29
-#define AT91C_PA29_FIQ      ((unsigned int) AT91C_PIO_PA29) //  AIC Fast Interrupt Input
-#define AT91C_PA29_NPCS13   ((unsigned int) AT91C_PIO_PA29) //  SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PA3        ((unsigned int) 1 <<  3) // Pin Controlled by PA3
-#define AT91C_PA3_RTS0     ((unsigned int) AT91C_PIO_PA3) //  USART 0 Ready To Send
-#define AT91C_PA3_NPCS12   ((unsigned int) AT91C_PIO_PA3) //  SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PA30       ((unsigned int) 1 << 30) // Pin Controlled by PA30
-#define AT91C_PA30_IRQ0     ((unsigned int) AT91C_PIO_PA30) //  External Interrupt 0
-#define AT91C_PA30_PCK2     ((unsigned int) AT91C_PIO_PA30) //  PMC Programmable Clock Output 2
-#define AT91C_PIO_PA4        ((unsigned int) 1 <<  4) // Pin Controlled by PA4
-#define AT91C_PA4_CTS0     ((unsigned int) AT91C_PIO_PA4) //  USART 0 Clear To Send
-#define AT91C_PA4_NPCS13   ((unsigned int) AT91C_PIO_PA4) //  SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PA5        ((unsigned int) 1 <<  5) // Pin Controlled by PA5
-#define AT91C_PA5_RXD1     ((unsigned int) AT91C_PIO_PA5) //  USART 1 Receive Data
-#define AT91C_PIO_PA6        ((unsigned int) 1 <<  6) // Pin Controlled by PA6
-#define AT91C_PA6_TXD1     ((unsigned int) AT91C_PIO_PA6) //  USART 1 Transmit Data
-#define AT91C_PIO_PA7        ((unsigned int) 1 <<  7) // Pin Controlled by PA7
-#define AT91C_PA7_SCK1     ((unsigned int) AT91C_PIO_PA7) //  USART 1 Serial Clock
-#define AT91C_PA7_NPCS01   ((unsigned int) AT91C_PIO_PA7) //  SPI 0 Peripheral Chip Select 1
-#define AT91C_PIO_PA8        ((unsigned int) 1 <<  8) // Pin Controlled by PA8
-#define AT91C_PA8_RTS1     ((unsigned int) AT91C_PIO_PA8) //  USART 1 Ready To Send
-#define AT91C_PA8_NPCS02   ((unsigned int) AT91C_PIO_PA8) //  SPI 0 Peripheral Chip Select 2
-#define AT91C_PIO_PA9        ((unsigned int) 1 <<  9) // Pin Controlled by PA9
-#define AT91C_PA9_CTS1     ((unsigned int) AT91C_PIO_PA9) //  USART 1 Clear To Send
-#define AT91C_PA9_NPCS03   ((unsigned int) AT91C_PIO_PA9) //  SPI 0 Peripheral Chip Select 3
-#define AT91C_PIO_PB0        ((unsigned int) 1 <<  0) // Pin Controlled by PB0
-#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) //  Ethernet MAC Transmit Clock/Reference Clock
-#define AT91C_PB0_PCK0     ((unsigned int) AT91C_PIO_PB0) //  PMC Programmable Clock Output 0
-#define AT91C_PIO_PB1        ((unsigned int) 1 <<  1) // Pin Controlled by PB1
-#define AT91C_PB1_ETXEN    ((unsigned int) AT91C_PIO_PB1) //  Ethernet MAC Transmit Enable
-#define AT91C_PIO_PB10       ((unsigned int) 1 << 10) // Pin Controlled by PB10
-#define AT91C_PB10_ETX2     ((unsigned int) AT91C_PIO_PB10) //  Ethernet MAC Transmit Data 2
-#define AT91C_PB10_NPCS11   ((unsigned int) AT91C_PIO_PB10) //  SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PB11       ((unsigned int) 1 << 11) // Pin Controlled by PB11
-#define AT91C_PB11_ETX3     ((unsigned int) AT91C_PIO_PB11) //  Ethernet MAC Transmit Data 3
-#define AT91C_PB11_NPCS12   ((unsigned int) AT91C_PIO_PB11) //  SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PB12       ((unsigned int) 1 << 12) // Pin Controlled by PB12
-#define AT91C_PB12_ETXER    ((unsigned int) AT91C_PIO_PB12) //  Ethernet MAC Transmikt Coding Error
-#define AT91C_PB12_TCLK0    ((unsigned int) AT91C_PIO_PB12) //  Timer Counter 0 external clock input
-#define AT91C_PIO_PB13       ((unsigned int) 1 << 13) // Pin Controlled by PB13
-#define AT91C_PB13_ERX2     ((unsigned int) AT91C_PIO_PB13) //  Ethernet MAC Receive Data 2
-#define AT91C_PB13_NPCS01   ((unsigned int) AT91C_PIO_PB13) //  SPI 0 Peripheral Chip Select 1
-#define AT91C_PIO_PB14       ((unsigned int) 1 << 14) // Pin Controlled by PB14
-#define AT91C_PB14_ERX3     ((unsigned int) AT91C_PIO_PB14) //  Ethernet MAC Receive Data 3
-#define AT91C_PB14_NPCS02   ((unsigned int) AT91C_PIO_PB14) //  SPI 0 Peripheral Chip Select 2
-#define AT91C_PIO_PB15       ((unsigned int) 1 << 15) // Pin Controlled by PB15
-#define AT91C_PB15_ERXDV    ((unsigned int) AT91C_PIO_PB15) //  Ethernet MAC Receive Data Valid
-#define AT91C_PIO_PB16       ((unsigned int) 1 << 16) // Pin Controlled by PB16
-#define AT91C_PB16_ECOL     ((unsigned int) AT91C_PIO_PB16) //  Ethernet MAC Collision Detected
-#define AT91C_PB16_NPCS13   ((unsigned int) AT91C_PIO_PB16) //  SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PB17       ((unsigned int) 1 << 17) // Pin Controlled by PB17
-#define AT91C_PB17_ERXCK    ((unsigned int) AT91C_PIO_PB17) //  Ethernet MAC Receive Clock
-#define AT91C_PB17_NPCS03   ((unsigned int) AT91C_PIO_PB17) //  SPI 0 Peripheral Chip Select 3
-#define AT91C_PIO_PB18       ((unsigned int) 1 << 18) // Pin Controlled by PB18
-#define AT91C_PB18_EF100    ((unsigned int) AT91C_PIO_PB18) //  Ethernet MAC Force 100 Mbits/sec
-#define AT91C_PB18_ADTRG    ((unsigned int) AT91C_PIO_PB18) //  ADC External Trigger
-#define AT91C_PIO_PB19       ((unsigned int) 1 << 19) // Pin Controlled by PB19
-#define AT91C_PB19_PWM0     ((unsigned int) AT91C_PIO_PB19) //  PWM Channel 0
-#define AT91C_PB19_TCLK1    ((unsigned int) AT91C_PIO_PB19) //  Timer Counter 1 external clock input
-#define AT91C_PIO_PB2        ((unsigned int) 1 <<  2) // Pin Controlled by PB2
-#define AT91C_PB2_ETX0     ((unsigned int) AT91C_PIO_PB2) //  Ethernet MAC Transmit Data 0
-#define AT91C_PIO_PB20       ((unsigned int) 1 << 20) // Pin Controlled by PB20
-#define AT91C_PB20_PWM1     ((unsigned int) AT91C_PIO_PB20) //  PWM Channel 1
-#define AT91C_PB20_PCK0     ((unsigned int) AT91C_PIO_PB20) //  PMC Programmable Clock Output 0
-#define AT91C_PIO_PB21       ((unsigned int) 1 << 21) // Pin Controlled by PB21
-#define AT91C_PB21_PWM2     ((unsigned int) AT91C_PIO_PB21) //  PWM Channel 2
-#define AT91C_PB21_PCK1     ((unsigned int) AT91C_PIO_PB21) //  PMC Programmable Clock Output 1
-#define AT91C_PIO_PB22       ((unsigned int) 1 << 22) // Pin Controlled by PB22
-#define AT91C_PB22_PWM3     ((unsigned int) AT91C_PIO_PB22) //  PWM Channel 3
-#define AT91C_PB22_PCK2     ((unsigned int) AT91C_PIO_PB22) //  PMC Programmable Clock Output 2
-#define AT91C_PIO_PB23       ((unsigned int) 1 << 23) // Pin Controlled by PB23
-#define AT91C_PB23_TIOA0    ((unsigned int) AT91C_PIO_PB23) //  Timer Counter 0 Multipurpose Timer I/O Pin A
-#define AT91C_PB23_DCD1     ((unsigned int) AT91C_PIO_PB23) //  USART 1 Data Carrier Detect
-#define AT91C_PIO_PB24       ((unsigned int) 1 << 24) // Pin Controlled by PB24
-#define AT91C_PB24_TIOB0    ((unsigned int) AT91C_PIO_PB24) //  Timer Counter 0 Multipurpose Timer I/O Pin B
-#define AT91C_PB24_DSR1     ((unsigned int) AT91C_PIO_PB24) //  USART 1 Data Set ready
-#define AT91C_PIO_PB25       ((unsigned int) 1 << 25) // Pin Controlled by PB25
-#define AT91C_PB25_TIOA1    ((unsigned int) AT91C_PIO_PB25) //  Timer Counter 1 Multipurpose Timer I/O Pin A
-#define AT91C_PB25_DTR1     ((unsigned int) AT91C_PIO_PB25) //  USART 1 Data Terminal ready
-#define AT91C_PIO_PB26       ((unsigned int) 1 << 26) // Pin Controlled by PB26
-#define AT91C_PB26_TIOB1    ((unsigned int) AT91C_PIO_PB26) //  Timer Counter 1 Multipurpose Timer I/O Pin B
-#define AT91C_PB26_RI1      ((unsigned int) AT91C_PIO_PB26) //  USART 1 Ring Indicator
-#define AT91C_PIO_PB27       ((unsigned int) 1 << 27) // Pin Controlled by PB27
-#define AT91C_PB27_TIOA2    ((unsigned int) AT91C_PIO_PB27) //  Timer Counter 2 Multipurpose Timer I/O Pin A
-#define AT91C_PB27_PWM0     ((unsigned int) AT91C_PIO_PB27) //  PWM Channel 0
-#define AT91C_PIO_PB28       ((unsigned int) 1 << 28) // Pin Controlled by PB28
-#define AT91C_PB28_TIOB2    ((unsigned int) AT91C_PIO_PB28) //  Timer Counter 2 Multipurpose Timer I/O Pin B
-#define AT91C_PB28_PWM1     ((unsigned int) AT91C_PIO_PB28) //  PWM Channel 1
-#define AT91C_PIO_PB29       ((unsigned int) 1 << 29) // Pin Controlled by PB29
-#define AT91C_PB29_PCK1     ((unsigned int) AT91C_PIO_PB29) //  PMC Programmable Clock Output 1
-#define AT91C_PB29_PWM2     ((unsigned int) AT91C_PIO_PB29) //  PWM Channel 2
-#define AT91C_PIO_PB3        ((unsigned int) 1 <<  3) // Pin Controlled by PB3
-#define AT91C_PB3_ETX1     ((unsigned int) AT91C_PIO_PB3) //  Ethernet MAC Transmit Data 1
-#define AT91C_PIO_PB30       ((unsigned int) 1 << 30) // Pin Controlled by PB30
-#define AT91C_PB30_PCK2     ((unsigned int) AT91C_PIO_PB30) //  PMC Programmable Clock Output 2
-#define AT91C_PB30_PWM3     ((unsigned int) AT91C_PIO_PB30) //  PWM Channel 3
-#define AT91C_PIO_PB4        ((unsigned int) 1 <<  4) // Pin Controlled by PB4
-#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) //  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
-#define AT91C_PIO_PB5        ((unsigned int) 1 <<  5) // Pin Controlled by PB5
-#define AT91C_PB5_ERX0     ((unsigned int) AT91C_PIO_PB5) //  Ethernet MAC Receive Data 0
-#define AT91C_PIO_PB6        ((unsigned int) 1 <<  6) // Pin Controlled by PB6
-#define AT91C_PB6_ERX1     ((unsigned int) AT91C_PIO_PB6) //  Ethernet MAC Receive Data 1
-#define AT91C_PIO_PB7        ((unsigned int) 1 <<  7) // Pin Controlled by PB7
-#define AT91C_PB7_ERXER    ((unsigned int) AT91C_PIO_PB7) //  Ethernet MAC Receive Error
-#define AT91C_PIO_PB8        ((unsigned int) 1 <<  8) // Pin Controlled by PB8
-#define AT91C_PB8_EMDC     ((unsigned int) AT91C_PIO_PB8) //  Ethernet MAC Management Data Clock
-#define AT91C_PIO_PB9        ((unsigned int) 1 <<  9) // Pin Controlled by PB9
-#define AT91C_PB9_EMDIO    ((unsigned int) AT91C_PIO_PB9) //  Ethernet MAC Management Data Input/Output
+/* ***************************************************************************** */
+/*               PIO DEFINITIONS FOR AT91SAM7X256 */
+/* ***************************************************************************** */
+#define AT91C_PIO_PA0             ( ( unsigned int ) 1 << 0 )         /* Pin Controlled by PA0 */
+#define AT91C_PA0_RXD0            ( ( unsigned int ) AT91C_PIO_PA0 )  /*  USART 0 Receive Data */
+#define AT91C_PIO_PA1             ( ( unsigned int ) 1 << 1 )         /* Pin Controlled by PA1 */
+#define AT91C_PA1_TXD0            ( ( unsigned int ) AT91C_PIO_PA1 )  /*  USART 0 Transmit Data */
+#define AT91C_PIO_PA10            ( ( unsigned int ) 1 << 10 )        /* Pin Controlled by PA10 */
+#define AT91C_PA10_TWD            ( ( unsigned int ) AT91C_PIO_PA10 ) /*  TWI Two-wire Serial Data */
+#define AT91C_PIO_PA11            ( ( unsigned int ) 1 << 11 )        /* Pin Controlled by PA11 */
+#define AT91C_PA11_TWCK           ( ( unsigned int ) AT91C_PIO_PA11 ) /*  TWI Two-wire Serial Clock */
+#define AT91C_PIO_PA12            ( ( unsigned int ) 1 << 12 )        /* Pin Controlled by PA12 */
+#define AT91C_PA12_NPCS00         ( ( unsigned int ) AT91C_PIO_PA12 ) /*  SPI 0 Peripheral Chip Select 0 */
+#define AT91C_PIO_PA13            ( ( unsigned int ) 1 << 13 )        /* Pin Controlled by PA13 */
+#define AT91C_PA13_NPCS01         ( ( unsigned int ) AT91C_PIO_PA13 ) /*  SPI 0 Peripheral Chip Select 1 */
+#define AT91C_PA13_PCK1           ( ( unsigned int ) AT91C_PIO_PA13 ) /*  PMC Programmable Clock Output 1 */
+#define AT91C_PIO_PA14            ( ( unsigned int ) 1 << 14 )        /* Pin Controlled by PA14 */
+#define AT91C_PA14_NPCS02         ( ( unsigned int ) AT91C_PIO_PA14 ) /*  SPI 0 Peripheral Chip Select 2 */
+#define AT91C_PA14_IRQ1           ( ( unsigned int ) AT91C_PIO_PA14 ) /*  External Interrupt 1 */
+#define AT91C_PIO_PA15            ( ( unsigned int ) 1 << 15 )        /* Pin Controlled by PA15 */
+#define AT91C_PA15_NPCS03         ( ( unsigned int ) AT91C_PIO_PA15 ) /*  SPI 0 Peripheral Chip Select 3 */
+#define AT91C_PA15_TCLK2          ( ( unsigned int ) AT91C_PIO_PA15 ) /*  Timer Counter 2 external clock input */
+#define AT91C_PIO_PA16            ( ( unsigned int ) 1 << 16 )        /* Pin Controlled by PA16 */
+#define AT91C_PA16_MISO0          ( ( unsigned int ) AT91C_PIO_PA16 ) /*  SPI 0 Master In Slave */
+#define AT91C_PIO_PA17            ( ( unsigned int ) 1 << 17 )        /* Pin Controlled by PA17 */
+#define AT91C_PA17_MOSI0          ( ( unsigned int ) AT91C_PIO_PA17 ) /*  SPI 0 Master Out Slave */
+#define AT91C_PIO_PA18            ( ( unsigned int ) 1 << 18 )        /* Pin Controlled by PA18 */
+#define AT91C_PA18_SPCK0          ( ( unsigned int ) AT91C_PIO_PA18 ) /*  SPI 0 Serial Clock */
+#define AT91C_PIO_PA19            ( ( unsigned int ) 1 << 19 )        /* Pin Controlled by PA19 */
+#define AT91C_PA19_CANRX          ( ( unsigned int ) AT91C_PIO_PA19 ) /*  CAN Receive */
+#define AT91C_PIO_PA2             ( ( unsigned int ) 1 << 2 )         /* Pin Controlled by PA2 */
+#define AT91C_PA2_SCK0            ( ( unsigned int ) AT91C_PIO_PA2 )  /*  USART 0 Serial Clock */
+#define AT91C_PA2_NPCS11          ( ( unsigned int ) AT91C_PIO_PA2 )  /*  SPI 1 Peripheral Chip Select 1 */
+#define AT91C_PIO_PA20            ( ( unsigned int ) 1 << 20 )        /* Pin Controlled by PA20 */
+#define AT91C_PA20_CANTX          ( ( unsigned int ) AT91C_PIO_PA20 ) /*  CAN Transmit */
+#define AT91C_PIO_PA21            ( ( unsigned int ) 1 << 21 )        /* Pin Controlled by PA21 */
+#define AT91C_PA21_TF             ( ( unsigned int ) AT91C_PIO_PA21 ) /*  SSC Transmit Frame Sync */
+#define AT91C_PA21_NPCS10         ( ( unsigned int ) AT91C_PIO_PA21 ) /*  SPI 1 Peripheral Chip Select 0 */
+#define AT91C_PIO_PA22            ( ( unsigned int ) 1 << 22 )        /* Pin Controlled by PA22 */
+#define AT91C_PA22_TK             ( ( unsigned int ) AT91C_PIO_PA22 ) /*  SSC Transmit Clock */
+#define AT91C_PA22_SPCK1          ( ( unsigned int ) AT91C_PIO_PA22 ) /*  SPI 1 Serial Clock */
+#define AT91C_PIO_PA23            ( ( unsigned int ) 1 << 23 )        /* Pin Controlled by PA23 */
+#define AT91C_PA23_TD             ( ( unsigned int ) AT91C_PIO_PA23 ) /*  SSC Transmit data */
+#define AT91C_PA23_MOSI1          ( ( unsigned int ) AT91C_PIO_PA23 ) /*  SPI 1 Master Out Slave */
+#define AT91C_PIO_PA24            ( ( unsigned int ) 1 << 24 )        /* Pin Controlled by PA24 */
+#define AT91C_PA24_RD             ( ( unsigned int ) AT91C_PIO_PA24 ) /*  SSC Receive Data */
+#define AT91C_PA24_MISO1          ( ( unsigned int ) AT91C_PIO_PA24 ) /*  SPI 1 Master In Slave */
+#define AT91C_PIO_PA25            ( ( unsigned int ) 1 << 25 )        /* Pin Controlled by PA25 */
+#define AT91C_PA25_RK             ( ( unsigned int ) AT91C_PIO_PA25 ) /*  SSC Receive Clock */
+#define AT91C_PA25_NPCS11         ( ( unsigned int ) AT91C_PIO_PA25 ) /*  SPI 1 Peripheral Chip Select 1 */
+#define AT91C_PIO_PA26            ( ( unsigned int ) 1 << 26 )        /* Pin Controlled by PA26 */
+#define AT91C_PA26_RF             ( ( unsigned int ) AT91C_PIO_PA26 ) /*  SSC Receive Frame Sync */
+#define AT91C_PA26_NPCS12         ( ( unsigned int ) AT91C_PIO_PA26 ) /*  SPI 1 Peripheral Chip Select 2 */
+#define AT91C_PIO_PA27            ( ( unsigned int ) 1 << 27 )        /* Pin Controlled by PA27 */
+#define AT91C_PA27_DRXD           ( ( unsigned int ) AT91C_PIO_PA27 ) /*  DBGU Debug Receive Data */
+#define AT91C_PA27_PCK3           ( ( unsigned int ) AT91C_PIO_PA27 ) /*  PMC Programmable Clock Output 3 */
+#define AT91C_PIO_PA28            ( ( unsigned int ) 1 << 28 )        /* Pin Controlled by PA28 */
+#define AT91C_PA28_DTXD           ( ( unsigned int ) AT91C_PIO_PA28 ) /*  DBGU Debug Transmit Data */
+#define AT91C_PIO_PA29            ( ( unsigned int ) 1 << 29 )        /* Pin Controlled by PA29 */
+#define AT91C_PA29_FIQ            ( ( unsigned int ) AT91C_PIO_PA29 ) /*  AIC Fast Interrupt Input */
+#define AT91C_PA29_NPCS13         ( ( unsigned int ) AT91C_PIO_PA29 ) /*  SPI 1 Peripheral Chip Select 3 */
+#define AT91C_PIO_PA3             ( ( unsigned int ) 1 << 3 )         /* Pin Controlled by PA3 */
+#define AT91C_PA3_RTS0            ( ( unsigned int ) AT91C_PIO_PA3 )  /*  USART 0 Ready To Send */
+#define AT91C_PA3_NPCS12          ( ( unsigned int ) AT91C_PIO_PA3 )  /*  SPI 1 Peripheral Chip Select 2 */
+#define AT91C_PIO_PA30            ( ( unsigned int ) 1 << 30 )        /* Pin Controlled by PA30 */
+#define AT91C_PA30_IRQ0           ( ( unsigned int ) AT91C_PIO_PA30 ) /*  External Interrupt 0 */
+#define AT91C_PA30_PCK2           ( ( unsigned int ) AT91C_PIO_PA30 ) /*  PMC Programmable Clock Output 2 */
+#define AT91C_PIO_PA4             ( ( unsigned int ) 1 << 4 )         /* Pin Controlled by PA4 */
+#define AT91C_PA4_CTS0            ( ( unsigned int ) AT91C_PIO_PA4 )  /*  USART 0 Clear To Send */
+#define AT91C_PA4_NPCS13          ( ( unsigned int ) AT91C_PIO_PA4 )  /*  SPI 1 Peripheral Chip Select 3 */
+#define AT91C_PIO_PA5             ( ( unsigned int ) 1 << 5 )         /* Pin Controlled by PA5 */
+#define AT91C_PA5_RXD1            ( ( unsigned int ) AT91C_PIO_PA5 )  /*  USART 1 Receive Data */
+#define AT91C_PIO_PA6             ( ( unsigned int ) 1 << 6 )         /* Pin Controlled by PA6 */
+#define AT91C_PA6_TXD1            ( ( unsigned int ) AT91C_PIO_PA6 )  /*  USART 1 Transmit Data */
+#define AT91C_PIO_PA7             ( ( unsigned int ) 1 << 7 )         /* Pin Controlled by PA7 */
+#define AT91C_PA7_SCK1            ( ( unsigned int ) AT91C_PIO_PA7 )  /*  USART 1 Serial Clock */
+#define AT91C_PA7_NPCS01          ( ( unsigned int ) AT91C_PIO_PA7 )  /*  SPI 0 Peripheral Chip Select 1 */
+#define AT91C_PIO_PA8             ( ( unsigned int ) 1 << 8 )         /* Pin Controlled by PA8 */
+#define AT91C_PA8_RTS1            ( ( unsigned int ) AT91C_PIO_PA8 )  /*  USART 1 Ready To Send */
+#define AT91C_PA8_NPCS02          ( ( unsigned int ) AT91C_PIO_PA8 )  /*  SPI 0 Peripheral Chip Select 2 */
+#define AT91C_PIO_PA9             ( ( unsigned int ) 1 << 9 )         /* Pin Controlled by PA9 */
+#define AT91C_PA9_CTS1            ( ( unsigned int ) AT91C_PIO_PA9 )  /*  USART 1 Clear To Send */
+#define AT91C_PA9_NPCS03          ( ( unsigned int ) AT91C_PIO_PA9 )  /*  SPI 0 Peripheral Chip Select 3 */
+#define AT91C_PIO_PB0             ( ( unsigned int ) 1 << 0 )         /* Pin Controlled by PB0 */
+#define AT91C_PB0_ETXCK_EREFCK    ( ( unsigned int ) AT91C_PIO_PB0 )  /*  Ethernet MAC Transmit Clock/Reference Clock */
+#define AT91C_PB0_PCK0            ( ( unsigned int ) AT91C_PIO_PB0 )  /*  PMC Programmable Clock Output 0 */
+#define AT91C_PIO_PB1             ( ( unsigned int ) 1 << 1 )         /* Pin Controlled by PB1 */
+#define AT91C_PB1_ETXEN           ( ( unsigned int ) AT91C_PIO_PB1 )  /*  Ethernet MAC Transmit Enable */
+#define AT91C_PIO_PB10            ( ( unsigned int ) 1 << 10 )        /* Pin Controlled by PB10 */
+#define AT91C_PB10_ETX2           ( ( unsigned int ) AT91C_PIO_PB10 ) /*  Ethernet MAC Transmit Data 2 */
+#define AT91C_PB10_NPCS11         ( ( unsigned int ) AT91C_PIO_PB10 ) /*  SPI 1 Peripheral Chip Select 1 */
+#define AT91C_PIO_PB11            ( ( unsigned int ) 1 << 11 )        /* Pin Controlled by PB11 */
+#define AT91C_PB11_ETX3           ( ( unsigned int ) AT91C_PIO_PB11 ) /*  Ethernet MAC Transmit Data 3 */
+#define AT91C_PB11_NPCS12         ( ( unsigned int ) AT91C_PIO_PB11 ) /*  SPI 1 Peripheral Chip Select 2 */
+#define AT91C_PIO_PB12            ( ( unsigned int ) 1 << 12 )        /* Pin Controlled by PB12 */
+#define AT91C_PB12_ETXER          ( ( unsigned int ) AT91C_PIO_PB12 ) /*  Ethernet MAC Transmit Coding Error */
+#define AT91C_PB12_TCLK0          ( ( unsigned int ) AT91C_PIO_PB12 ) /*  Timer Counter 0 external clock input */
+#define AT91C_PIO_PB13            ( ( unsigned int ) 1 << 13 )        /* Pin Controlled by PB13 */
+#define AT91C_PB13_ERX2           ( ( unsigned int ) AT91C_PIO_PB13 ) /*  Ethernet MAC Receive Data 2 */
+#define AT91C_PB13_NPCS01         ( ( unsigned int ) AT91C_PIO_PB13 ) /*  SPI 0 Peripheral Chip Select 1 */
+#define AT91C_PIO_PB14            ( ( unsigned int ) 1 << 14 )        /* Pin Controlled by PB14 */
+#define AT91C_PB14_ERX3           ( ( unsigned int ) AT91C_PIO_PB14 ) /*  Ethernet MAC Receive Data 3 */
+#define AT91C_PB14_NPCS02         ( ( unsigned int ) AT91C_PIO_PB14 ) /*  SPI 0 Peripheral Chip Select 2 */
+#define AT91C_PIO_PB15            ( ( unsigned int ) 1 << 15 )        /* Pin Controlled by PB15 */
+#define AT91C_PB15_ERXDV          ( ( unsigned int ) AT91C_PIO_PB15 ) /*  Ethernet MAC Receive Data Valid */
+#define AT91C_PIO_PB16            ( ( unsigned int ) 1 << 16 )        /* Pin Controlled by PB16 */
+#define AT91C_PB16_ECOL           ( ( unsigned int ) AT91C_PIO_PB16 ) /*  Ethernet MAC Collision Detected */
+#define AT91C_PB16_NPCS13         ( ( unsigned int ) AT91C_PIO_PB16 ) /*  SPI 1 Peripheral Chip Select 3 */
+#define AT91C_PIO_PB17            ( ( unsigned int ) 1 << 17 )        /* Pin Controlled by PB17 */
+#define AT91C_PB17_ERXCK          ( ( unsigned int ) AT91C_PIO_PB17 ) /*  Ethernet MAC Receive Clock */
+#define AT91C_PB17_NPCS03         ( ( unsigned int ) AT91C_PIO_PB17 ) /*  SPI 0 Peripheral Chip Select 3 */
+#define AT91C_PIO_PB18            ( ( unsigned int ) 1 << 18 )        /* Pin Controlled by PB18 */
+#define AT91C_PB18_EF100          ( ( unsigned int ) AT91C_PIO_PB18 ) /*  Ethernet MAC Force 100 Mbits/sec */
+#define AT91C_PB18_ADTRG          ( ( unsigned int ) AT91C_PIO_PB18 ) /*  ADC External Trigger */
+#define AT91C_PIO_PB19            ( ( unsigned int ) 1 << 19 )        /* Pin Controlled by PB19 */
+#define AT91C_PB19_PWM0           ( ( unsigned int ) AT91C_PIO_PB19 ) /*  PWM Channel 0 */
+#define AT91C_PB19_TCLK1          ( ( unsigned int ) AT91C_PIO_PB19 ) /*  Timer Counter 1 external clock input */
+#define AT91C_PIO_PB2             ( ( unsigned int ) 1 << 2 )         /* Pin Controlled by PB2 */
+#define AT91C_PB2_ETX0            ( ( unsigned int ) AT91C_PIO_PB2 )  /*  Ethernet MAC Transmit Data 0 */
+#define AT91C_PIO_PB20            ( ( unsigned int ) 1 << 20 )        /* Pin Controlled by PB20 */
+#define AT91C_PB20_PWM1           ( ( unsigned int ) AT91C_PIO_PB20 ) /*  PWM Channel 1 */
+#define AT91C_PB20_PCK0           ( ( unsigned int ) AT91C_PIO_PB20 ) /*  PMC Programmable Clock Output 0 */
+#define AT91C_PIO_PB21            ( ( unsigned int ) 1 << 21 )        /* Pin Controlled by PB21 */
+#define AT91C_PB21_PWM2           ( ( unsigned int ) AT91C_PIO_PB21 ) /*  PWM Channel 2 */
+#define AT91C_PB21_PCK1           ( ( unsigned int ) AT91C_PIO_PB21 ) /*  PMC Programmable Clock Output 1 */
+#define AT91C_PIO_PB22            ( ( unsigned int ) 1 << 22 )        /* Pin Controlled by PB22 */
+#define AT91C_PB22_PWM3           ( ( unsigned int ) AT91C_PIO_PB22 ) /*  PWM Channel 3 */
+#define AT91C_PB22_PCK2           ( ( unsigned int ) AT91C_PIO_PB22 ) /*  PMC Programmable Clock Output 2 */
+#define AT91C_PIO_PB23            ( ( unsigned int ) 1 << 23 )        /* Pin Controlled by PB23 */
+#define AT91C_PB23_TIOA0          ( ( unsigned int ) AT91C_PIO_PB23 ) /*  Timer Counter 0 Multipurpose Timer I/O Pin A */
+#define AT91C_PB23_DCD1           ( ( unsigned int ) AT91C_PIO_PB23 ) /*  USART 1 Data Carrier Detect */
+#define AT91C_PIO_PB24            ( ( unsigned int ) 1 << 24 )        /* Pin Controlled by PB24 */
+#define AT91C_PB24_TIOB0          ( ( unsigned int ) AT91C_PIO_PB24 ) /*  Timer Counter 0 Multipurpose Timer I/O Pin B */
+#define AT91C_PB24_DSR1           ( ( unsigned int ) AT91C_PIO_PB24 ) /*  USART 1 Data Set ready */
+#define AT91C_PIO_PB25            ( ( unsigned int ) 1 << 25 )        /* Pin Controlled by PB25 */
+#define AT91C_PB25_TIOA1          ( ( unsigned int ) AT91C_PIO_PB25 ) /*  Timer Counter 1 Multipurpose Timer I/O Pin A */
+#define AT91C_PB25_DTR1           ( ( unsigned int ) AT91C_PIO_PB25 ) /*  USART 1 Data Terminal ready */
+#define AT91C_PIO_PB26            ( ( unsigned int ) 1 << 26 )        /* Pin Controlled by PB26 */
+#define AT91C_PB26_TIOB1          ( ( unsigned int ) AT91C_PIO_PB26 ) /*  Timer Counter 1 Multipurpose Timer I/O Pin B */
+#define AT91C_PB26_RI1            ( ( unsigned int ) AT91C_PIO_PB26 ) /*  USART 1 Ring Indicator */
+#define AT91C_PIO_PB27            ( ( unsigned int ) 1 << 27 )        /* Pin Controlled by PB27 */
+#define AT91C_PB27_TIOA2          ( ( unsigned int ) AT91C_PIO_PB27 ) /*  Timer Counter 2 Multipurpose Timer I/O Pin A */
+#define AT91C_PB27_PWM0           ( ( unsigned int ) AT91C_PIO_PB27 ) /*  PWM Channel 0 */
+#define AT91C_PIO_PB28            ( ( unsigned int ) 1 << 28 )        /* Pin Controlled by PB28 */
+#define AT91C_PB28_TIOB2          ( ( unsigned int ) AT91C_PIO_PB28 ) /*  Timer Counter 2 Multipurpose Timer I/O Pin B */
+#define AT91C_PB28_PWM1           ( ( unsigned int ) AT91C_PIO_PB28 ) /*  PWM Channel 1 */
+#define AT91C_PIO_PB29            ( ( unsigned int ) 1 << 29 )        /* Pin Controlled by PB29 */
+#define AT91C_PB29_PCK1           ( ( unsigned int ) AT91C_PIO_PB29 ) /*  PMC Programmable Clock Output 1 */
+#define AT91C_PB29_PWM2           ( ( unsigned int ) AT91C_PIO_PB29 ) /*  PWM Channel 2 */
+#define AT91C_PIO_PB3             ( ( unsigned int ) 1 << 3 )         /* Pin Controlled by PB3 */
+#define AT91C_PB3_ETX1            ( ( unsigned int ) AT91C_PIO_PB3 )  /*  Ethernet MAC Transmit Data 1 */
+#define AT91C_PIO_PB30            ( ( unsigned int ) 1 << 30 )        /* Pin Controlled by PB30 */
+#define AT91C_PB30_PCK2           ( ( unsigned int ) AT91C_PIO_PB30 ) /*  PMC Programmable Clock Output 2 */
+#define AT91C_PB30_PWM3           ( ( unsigned int ) AT91C_PIO_PB30 ) /*  PWM Channel 3 */
+#define AT91C_PIO_PB4             ( ( unsigned int ) 1 << 4 )         /* Pin Controlled by PB4 */
+#define AT91C_PB4_ECRS_ECRSDV     ( ( unsigned int ) AT91C_PIO_PB4 )  /*  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid */
+#define AT91C_PIO_PB5             ( ( unsigned int ) 1 << 5 )         /* Pin Controlled by PB5 */
+#define AT91C_PB5_ERX0            ( ( unsigned int ) AT91C_PIO_PB5 )  /*  Ethernet MAC Receive Data 0 */
+#define AT91C_PIO_PB6             ( ( unsigned int ) 1 << 6 )         /* Pin Controlled by PB6 */
+#define AT91C_PB6_ERX1            ( ( unsigned int ) AT91C_PIO_PB6 )  /*  Ethernet MAC Receive Data 1 */
+#define AT91C_PIO_PB7             ( ( unsigned int ) 1 << 7 )         /* Pin Controlled by PB7 */
+#define AT91C_PB7_ERXER           ( ( unsigned int ) AT91C_PIO_PB7 )  /*  Ethernet MAC Receive Error */
+#define AT91C_PIO_PB8             ( ( unsigned int ) 1 << 8 )         /* Pin Controlled by PB8 */
+#define AT91C_PB8_EMDC            ( ( unsigned int ) AT91C_PIO_PB8 )  /*  Ethernet MAC Management Data Clock */
+#define AT91C_PIO_PB9             ( ( unsigned int ) 1 << 9 )         /* Pin Controlled by PB9 */
+#define AT91C_PB9_EMDIO           ( ( unsigned int ) AT91C_PIO_PB9 )  /*  Ethernet MAC Management Data Input/Output */
 
-// *****************************************************************************
-//               PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256
-// *****************************************************************************
-#define AT91C_ID_FIQ    ((unsigned int)  0) // Advanced Interrupt Controller (FIQ)
-#define AT91C_ID_SYS    ((unsigned int)  1) // System Peripheral
-#define AT91C_ID_PIOA   ((unsigned int)  2) // Parallel IO Controller A
-#define AT91C_ID_PIOB   ((unsigned int)  3) // Parallel IO Controller B
-#define AT91C_ID_SPI0   ((unsigned int)  4) // Serial Peripheral Interface 0
-#define AT91C_ID_SPI1   ((unsigned int)  5) // Serial Peripheral Interface 1
-#define AT91C_ID_US0    ((unsigned int)  6) // USART 0
-#define AT91C_ID_US1    ((unsigned int)  7) // USART 1
-#define AT91C_ID_SSC    ((unsigned int)  8) // Serial Synchronous Controller
-#define AT91C_ID_TWI    ((unsigned int)  9) // Two-Wire Interface
-#define AT91C_ID_PWMC   ((unsigned int) 10) // PWM Controller
-#define AT91C_ID_UDP    ((unsigned int) 11) // USB Device Port
-#define AT91C_ID_TC0    ((unsigned int) 12) // Timer Counter 0
-#define AT91C_ID_TC1    ((unsigned int) 13) // Timer Counter 1
-#define AT91C_ID_TC2    ((unsigned int) 14) // Timer Counter 2
-#define AT91C_ID_CAN    ((unsigned int) 15) // Control Area Network Controller
-#define AT91C_ID_EMAC   ((unsigned int) 16) // Ethernet MAC
-#define AT91C_ID_ADC    ((unsigned int) 17) // Analog-to-Digital Converter
-#define AT91C_ID_AES    ((unsigned int) 18) // Advanced Encryption Standard 128-bit
-#define AT91C_ID_TDES   ((unsigned int) 19) // Triple Data Encryption Standard
-#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved
-#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved
-#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved
-#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved
-#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved
-#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved
-#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved
-#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved
-#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved
-#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved
-#define AT91C_ID_IRQ0   ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0)
-#define AT91C_ID_IRQ1   ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1)
+/* ***************************************************************************** */
+/*               PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 */
+/* ***************************************************************************** */
+#define AT91C_ID_FIQ            ( ( unsigned int ) 0 )  /* Advanced Interrupt Controller (FIQ) */
+#define AT91C_ID_SYS            ( ( unsigned int ) 1 )  /* System Peripheral */
+#define AT91C_ID_PIOA           ( ( unsigned int ) 2 )  /* Parallel IO Controller A */
+#define AT91C_ID_PIOB           ( ( unsigned int ) 3 )  /* Parallel IO Controller B */
+#define AT91C_ID_SPI0           ( ( unsigned int ) 4 )  /* Serial Peripheral Interface 0 */
+#define AT91C_ID_SPI1           ( ( unsigned int ) 5 )  /* Serial Peripheral Interface 1 */
+#define AT91C_ID_US0            ( ( unsigned int ) 6 )  /* USART 0 */
+#define AT91C_ID_US1            ( ( unsigned int ) 7 )  /* USART 1 */
+#define AT91C_ID_SSC            ( ( unsigned int ) 8 )  /* Serial Synchronous Controller */
+#define AT91C_ID_TWI            ( ( unsigned int ) 9 )  /* Two-Wire Interface */
+#define AT91C_ID_PWMC           ( ( unsigned int ) 10 ) /* PWM Controller */
+#define AT91C_ID_UDP            ( ( unsigned int ) 11 ) /* USB Device Port */
+#define AT91C_ID_TC0            ( ( unsigned int ) 12 ) /* Timer Counter 0 */
+#define AT91C_ID_TC1            ( ( unsigned int ) 13 ) /* Timer Counter 1 */
+#define AT91C_ID_TC2            ( ( unsigned int ) 14 ) /* Timer Counter 2 */
+#define AT91C_ID_CAN            ( ( unsigned int ) 15 ) /* Control Area Network Controller */
+#define AT91C_ID_EMAC           ( ( unsigned int ) 16 ) /* Ethernet MAC */
+#define AT91C_ID_ADC            ( ( unsigned int ) 17 ) /* Analog-to-Digital Converter */
+#define AT91C_ID_AES            ( ( unsigned int ) 18 ) /* Advanced Encryption Standard 128-bit */
+#define AT91C_ID_TDES           ( ( unsigned int ) 19 ) /* Triple Data Encryption Standard */
+#define AT91C_ID_20_Reserved    ( ( unsigned int ) 20 ) /* Reserved */
+#define AT91C_ID_21_Reserved    ( ( unsigned int ) 21 ) /* Reserved */
+#define AT91C_ID_22_Reserved    ( ( unsigned int ) 22 ) /* Reserved */
+#define AT91C_ID_23_Reserved    ( ( unsigned int ) 23 ) /* Reserved */
+#define AT91C_ID_24_Reserved    ( ( unsigned int ) 24 ) /* Reserved */
+#define AT91C_ID_25_Reserved    ( ( unsigned int ) 25 ) /* Reserved */
+#define AT91C_ID_26_Reserved    ( ( unsigned int ) 26 ) /* Reserved */
+#define AT91C_ID_27_Reserved    ( ( unsigned int ) 27 ) /* Reserved */
+#define AT91C_ID_28_Reserved    ( ( unsigned int ) 28 ) /* Reserved */
+#define AT91C_ID_29_Reserved    ( ( unsigned int ) 29 ) /* Reserved */
+#define AT91C_ID_IRQ0           ( ( unsigned int ) 30 ) /* Advanced Interrupt Controller (IRQ0) */
+#define AT91C_ID_IRQ1           ( ( unsigned int ) 31 ) /* Advanced Interrupt Controller (IRQ1) */
 
-// *****************************************************************************
-//               BASE ADDRESS DEFINITIONS FOR AT91SAM7X256
-// *****************************************************************************
-#define AT91C_BASE_SYS       ((AT91PS_SYS)  0xFFFFF000) // (SYS) Base Address
-#define AT91C_BASE_AIC       ((AT91PS_AIC)  0xFFFFF000) // (AIC) Base Address
-#define AT91C_BASE_PDC_DBGU  ((AT91PS_PDC)  0xFFFFF300) // (PDC_DBGU) Base Address
-#define AT91C_BASE_DBGU      ((AT91PS_DBGU)     0xFFFFF200) // (DBGU) Base Address
-#define AT91C_BASE_PIOA      ((AT91PS_PIO)  0xFFFFF400) // (PIOA) Base Address
-#define AT91C_BASE_PIOB      ((AT91PS_PIO)  0xFFFFF600) // (PIOB) Base Address
-#define AT91C_BASE_CKGR      ((AT91PS_CKGR)     0xFFFFFC20) // (CKGR) Base Address
-#define AT91C_BASE_PMC       ((AT91PS_PMC)  0xFFFFFC00) // (PMC) Base Address
-#define AT91C_BASE_RSTC      ((AT91PS_RSTC)     0xFFFFFD00) // (RSTC) Base Address
-#define AT91C_BASE_RTTC      ((AT91PS_RTTC)     0xFFFFFD20) // (RTTC) Base Address
-#define AT91C_BASE_PITC      ((AT91PS_PITC)     0xFFFFFD30) // (PITC) Base Address
-#define AT91C_BASE_WDTC      ((AT91PS_WDTC)     0xFFFFFD40) // (WDTC) Base Address
-#define AT91C_BASE_VREG      ((AT91PS_VREG)     0xFFFFFD60) // (VREG) Base Address
-#define AT91C_BASE_MC        ((AT91PS_MC)   0xFFFFFF00) // (MC) Base Address
-#define AT91C_BASE_PDC_SPI1  ((AT91PS_PDC)  0xFFFE4100) // (PDC_SPI1) Base Address
-#define AT91C_BASE_SPI1      ((AT91PS_SPI)  0xFFFE4000) // (SPI1) Base Address
-#define AT91C_BASE_PDC_SPI0  ((AT91PS_PDC)  0xFFFE0100) // (PDC_SPI0) Base Address
-#define AT91C_BASE_SPI0      ((AT91PS_SPI)  0xFFFE0000) // (SPI0) Base Address
-#define AT91C_BASE_PDC_US1   ((AT91PS_PDC)  0xFFFC4100) // (PDC_US1) Base Address
-#define AT91C_BASE_US1       ((AT91PS_USART)    0xFFFC4000) // (US1) Base Address
-#define AT91C_BASE_PDC_US0   ((AT91PS_PDC)  0xFFFC0100) // (PDC_US0) Base Address
-#define AT91C_BASE_US0       ((AT91PS_USART)    0xFFFC0000) // (US0) Base Address
-#define AT91C_BASE_PDC_SSC   ((AT91PS_PDC)  0xFFFD4100) // (PDC_SSC) Base Address
-#define AT91C_BASE_SSC       ((AT91PS_SSC)  0xFFFD4000) // (SSC) Base Address
-#define AT91C_BASE_TWI       ((AT91PS_TWI)  0xFFFB8000) // (TWI) Base Address
-#define AT91C_BASE_PWMC_CH3  ((AT91PS_PWMC_CH)  0xFFFCC260) // (PWMC_CH3) Base Address
-#define AT91C_BASE_PWMC_CH2  ((AT91PS_PWMC_CH)  0xFFFCC240) // (PWMC_CH2) Base Address
-#define AT91C_BASE_PWMC_CH1  ((AT91PS_PWMC_CH)  0xFFFCC220) // (PWMC_CH1) Base Address
-#define AT91C_BASE_PWMC_CH0  ((AT91PS_PWMC_CH)  0xFFFCC200) // (PWMC_CH0) Base Address
-#define AT91C_BASE_PWMC      ((AT91PS_PWMC)     0xFFFCC000) // (PWMC) Base Address
-#define AT91C_BASE_UDP       ((AT91PS_UDP)  0xFFFB0000) // (UDP) Base Address
-#define AT91C_BASE_TC0       ((AT91PS_TC)   0xFFFA0000) // (TC0) Base Address
-#define AT91C_BASE_TC1       ((AT91PS_TC)   0xFFFA0040) // (TC1) Base Address
-#define AT91C_BASE_TC2       ((AT91PS_TC)   0xFFFA0080) // (TC2) Base Address
-#define AT91C_BASE_TCB       ((AT91PS_TCB)  0xFFFA0000) // (TCB) Base Address
-#define AT91C_BASE_CAN_MB0   ((AT91PS_CAN_MB)   0xFFFD0200) // (CAN_MB0) Base Address
-#define AT91C_BASE_CAN_MB1   ((AT91PS_CAN_MB)   0xFFFD0220) // (CAN_MB1) Base Address
-#define AT91C_BASE_CAN_MB2   ((AT91PS_CAN_MB)   0xFFFD0240) // (CAN_MB2) Base Address
-#define AT91C_BASE_CAN_MB3   ((AT91PS_CAN_MB)   0xFFFD0260) // (CAN_MB3) Base Address
-#define AT91C_BASE_CAN_MB4   ((AT91PS_CAN_MB)   0xFFFD0280) // (CAN_MB4) Base Address
-#define AT91C_BASE_CAN_MB5   ((AT91PS_CAN_MB)   0xFFFD02A0) // (CAN_MB5) Base Address
-#define AT91C_BASE_CAN_MB6   ((AT91PS_CAN_MB)   0xFFFD02C0) // (CAN_MB6) Base Address
-#define AT91C_BASE_CAN_MB7   ((AT91PS_CAN_MB)   0xFFFD02E0) // (CAN_MB7) Base Address
-#define AT91C_BASE_CAN       ((AT91PS_CAN)  0xFFFD0000) // (CAN) Base Address
-#define AT91C_BASE_EMAC      ((AT91PS_EMAC)     0xFFFDC000) // (EMAC) Base Address
-#define AT91C_BASE_PDC_ADC   ((AT91PS_PDC)  0xFFFD8100) // (PDC_ADC) Base Address
-#define AT91C_BASE_ADC       ((AT91PS_ADC)  0xFFFD8000) // (ADC) Base Address
-#define AT91C_BASE_PDC_AES   ((AT91PS_PDC)  0xFFFA4100) // (PDC_AES) Base Address
-#define AT91C_BASE_AES       ((AT91PS_AES)  0xFFFA4000) // (AES) Base Address
-#define AT91C_BASE_PDC_TDES  ((AT91PS_PDC)  0xFFFA8100) // (PDC_TDES) Base Address
-#define AT91C_BASE_TDES      ((AT91PS_TDES)     0xFFFA8000) // (TDES) Base Address
+/* ***************************************************************************** */
+/*               BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 */
+/* ***************************************************************************** */
+#define AT91C_BASE_SYS         ( ( AT91PS_SYS ) 0xFFFFF000 )     /* (SYS) Base Address */
+#define AT91C_BASE_AIC         ( ( AT91PS_AIC ) 0xFFFFF000 )     /* (AIC) Base Address */
+#define AT91C_BASE_PDC_DBGU    ( ( AT91PS_PDC ) 0xFFFFF300 )     /* (PDC_DBGU) Base Address */
+#define AT91C_BASE_DBGU        ( ( AT91PS_DBGU ) 0xFFFFF200 )    /* (DBGU) Base Address */
+#define AT91C_BASE_PIOA        ( ( AT91PS_PIO ) 0xFFFFF400 )     /* (PIOA) Base Address */
+#define AT91C_BASE_PIOB        ( ( AT91PS_PIO ) 0xFFFFF600 )     /* (PIOB) Base Address */
+#define AT91C_BASE_CKGR        ( ( AT91PS_CKGR ) 0xFFFFFC20 )    /* (CKGR) Base Address */
+#define AT91C_BASE_PMC         ( ( AT91PS_PMC ) 0xFFFFFC00 )     /* (PMC) Base Address */
+#define AT91C_BASE_RSTC        ( ( AT91PS_RSTC ) 0xFFFFFD00 )    /* (RSTC) Base Address */
+#define AT91C_BASE_RTTC        ( ( AT91PS_RTTC ) 0xFFFFFD20 )    /* (RTTC) Base Address */
+#define AT91C_BASE_PITC        ( ( AT91PS_PITC ) 0xFFFFFD30 )    /* (PITC) Base Address */
+#define AT91C_BASE_WDTC        ( ( AT91PS_WDTC ) 0xFFFFFD40 )    /* (WDTC) Base Address */
+#define AT91C_BASE_VREG        ( ( AT91PS_VREG ) 0xFFFFFD60 )    /* (VREG) Base Address */
+#define AT91C_BASE_MC          ( ( AT91PS_MC ) 0xFFFFFF00 )      /* (MC) Base Address */
+#define AT91C_BASE_PDC_SPI1    ( ( AT91PS_PDC ) 0xFFFE4100 )     /* (PDC_SPI1) Base Address */
+#define AT91C_BASE_SPI1        ( ( AT91PS_SPI ) 0xFFFE4000 )     /* (SPI1) Base Address */
+#define AT91C_BASE_PDC_SPI0    ( ( AT91PS_PDC ) 0xFFFE0100 )     /* (PDC_SPI0) Base Address */
+#define AT91C_BASE_SPI0        ( ( AT91PS_SPI ) 0xFFFE0000 )     /* (SPI0) Base Address */
+#define AT91C_BASE_PDC_US1     ( ( AT91PS_PDC ) 0xFFFC4100 )     /* (PDC_US1) Base Address */
+#define AT91C_BASE_US1         ( ( AT91PS_USART ) 0xFFFC4000 )   /* (US1) Base Address */
+#define AT91C_BASE_PDC_US0     ( ( AT91PS_PDC ) 0xFFFC0100 )     /* (PDC_US0) Base Address */
+#define AT91C_BASE_US0         ( ( AT91PS_USART ) 0xFFFC0000 )   /* (US0) Base Address */
+#define AT91C_BASE_PDC_SSC     ( ( AT91PS_PDC ) 0xFFFD4100 )     /* (PDC_SSC) Base Address */
+#define AT91C_BASE_SSC         ( ( AT91PS_SSC ) 0xFFFD4000 )     /* (SSC) Base Address */
+#define AT91C_BASE_TWI         ( ( AT91PS_TWI ) 0xFFFB8000 )     /* (TWI) Base Address */
+#define AT91C_BASE_PWMC_CH3    ( ( AT91PS_PWMC_CH ) 0xFFFCC260 ) /* (PWMC_CH3) Base Address */
+#define AT91C_BASE_PWMC_CH2    ( ( AT91PS_PWMC_CH ) 0xFFFCC240 ) /* (PWMC_CH2) Base Address */
+#define AT91C_BASE_PWMC_CH1    ( ( AT91PS_PWMC_CH ) 0xFFFCC220 ) /* (PWMC_CH1) Base Address */
+#define AT91C_BASE_PWMC_CH0    ( ( AT91PS_PWMC_CH ) 0xFFFCC200 ) /* (PWMC_CH0) Base Address */
+#define AT91C_BASE_PWMC        ( ( AT91PS_PWMC ) 0xFFFCC000 )    /* (PWMC) Base Address */
+#define AT91C_BASE_UDP         ( ( AT91PS_UDP ) 0xFFFB0000 )     /* (UDP) Base Address */
+#define AT91C_BASE_TC0         ( ( AT91PS_TC ) 0xFFFA0000 )      /* (TC0) Base Address */
+#define AT91C_BASE_TC1         ( ( AT91PS_TC ) 0xFFFA0040 )      /* (TC1) Base Address */
+#define AT91C_BASE_TC2         ( ( AT91PS_TC ) 0xFFFA0080 )      /* (TC2) Base Address */
+#define AT91C_BASE_TCB         ( ( AT91PS_TCB ) 0xFFFA0000 )     /* (TCB) Base Address */
+#define AT91C_BASE_CAN_MB0     ( ( AT91PS_CAN_MB ) 0xFFFD0200 )  /* (CAN_MB0) Base Address */
+#define AT91C_BASE_CAN_MB1     ( ( AT91PS_CAN_MB ) 0xFFFD0220 )  /* (CAN_MB1) Base Address */
+#define AT91C_BASE_CAN_MB2     ( ( AT91PS_CAN_MB ) 0xFFFD0240 )  /* (CAN_MB2) Base Address */
+#define AT91C_BASE_CAN_MB3     ( ( AT91PS_CAN_MB ) 0xFFFD0260 )  /* (CAN_MB3) Base Address */
+#define AT91C_BASE_CAN_MB4     ( ( AT91PS_CAN_MB ) 0xFFFD0280 )  /* (CAN_MB4) Base Address */
+#define AT91C_BASE_CAN_MB5     ( ( AT91PS_CAN_MB ) 0xFFFD02A0 )  /* (CAN_MB5) Base Address */
+#define AT91C_BASE_CAN_MB6     ( ( AT91PS_CAN_MB ) 0xFFFD02C0 )  /* (CAN_MB6) Base Address */
+#define AT91C_BASE_CAN_MB7     ( ( AT91PS_CAN_MB ) 0xFFFD02E0 )  /* (CAN_MB7) Base Address */
+#define AT91C_BASE_CAN         ( ( AT91PS_CAN ) 0xFFFD0000 )     /* (CAN) Base Address */
+#define AT91C_BASE_EMAC        ( ( AT91PS_EMAC ) 0xFFFDC000 )    /* (EMAC) Base Address */
+#define AT91C_BASE_PDC_ADC     ( ( AT91PS_PDC ) 0xFFFD8100 )     /* (PDC_ADC) Base Address */
+#define AT91C_BASE_ADC         ( ( AT91PS_ADC ) 0xFFFD8000 )     /* (ADC) Base Address */
+#define AT91C_BASE_PDC_AES     ( ( AT91PS_PDC ) 0xFFFA4100 )     /* (PDC_AES) Base Address */
+#define AT91C_BASE_AES         ( ( AT91PS_AES ) 0xFFFA4000 )     /* (AES) Base Address */
+#define AT91C_BASE_PDC_TDES    ( ( AT91PS_PDC ) 0xFFFA8100 )     /* (PDC_TDES) Base Address */
+#define AT91C_BASE_TDES        ( ( AT91PS_TDES ) 0xFFFA8000 )    /* (TDES) Base Address */
 
-// *****************************************************************************
-//               MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256
-// *****************************************************************************
-#define AT91C_ISRAM  ((char *)  0x00200000) // Internal SRAM base address
-#define AT91C_ISRAM_SIZE     ((unsigned int) 0x00010000) // Internal SRAM size in byte (64 Kbyte)
-#define AT91C_IFLASH     ((char *)  0x00100000) // Internal ROM base address
-#define AT91C_IFLASH_SIZE    ((unsigned int) 0x00040000) // Internal ROM size in byte (256 Kbyte)
+/* ***************************************************************************** */
+/*               MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 */
+/* ***************************************************************************** */
+#define AT91C_ISRAM          ( ( char * ) 0x00200000 )       /* Internal SRAM base address */
+#define AT91C_ISRAM_SIZE     ( ( unsigned int ) 0x00010000 ) /* Internal SRAM size in byte (64 Kbyte) */
+#define AT91C_IFLASH         ( ( char * ) 0x00100000 )       /* Internal ROM base address */
+#define AT91C_IFLASH_SIZE    ( ( unsigned int ) 0x00040000 ) /* Internal ROM size in byte (256 Kbyte) */
 
-#define AT91F_AIC_ConfigureIt( irq_id, priority, src_type, newHandler )     \
-{                                                                           \
-    unsigned int mask ;                                                     \
-                                                                            \
-    mask = 0x1 << irq_id;                                                   \
-    /* Disable the interrupt on the interrupt controller */                 \
-    AT91C_BASE_AIC->AIC_IDCR = mask ;                                       \
-    /* Save the interrupt handler routine pointer and the interrupt priority */ \
-    AT91C_BASE_AIC->AIC_SVR[irq_id] = (unsigned int) newHandler ;           \
-    /* Store the Source Mode Register */                                    \
-    AT91C_BASE_AIC->AIC_SMR[irq_id] = src_type | priority  ;                \
-    /* Clear the interrupt on the interrupt controller */                   \
-    AT91C_BASE_AIC->AIC_ICCR = mask ;                                       \
-}
+#define AT91F_AIC_ConfigureIt( irq_id, priority, src_type, newHandler )             \
+    {                                                                               \
+        unsigned int mask;                                                          \
+                                                                                    \
+        mask = 0x1 << irq_id;                                                       \
+        /* Disable the interrupt on the interrupt controller */                     \
+        AT91C_BASE_AIC->AIC_IDCR = mask;                                            \
+        /* Save the interrupt handler routine pointer and the interrupt priority */ \
+        AT91C_BASE_AIC->AIC_SVR[ irq_id ] = ( unsigned int ) newHandler;            \
+        /* Store the Source Mode Register */                                        \
+        AT91C_BASE_AIC->AIC_SMR[ irq_id ] = src_type | priority;                    \
+        /* Clear the interrupt on the interrupt controller */                       \
+        AT91C_BASE_AIC->AIC_ICCR = mask;                                            \
+    }
 
 
-#endif
+#endif /* ifndef AT91SAM7X256_H */
diff --git a/portable/GCC/ARM7_AT91SAM7S/ioat91sam7x256.h b/portable/GCC/ARM7_AT91SAM7S/ioat91sam7x256.h
index d4c43e8f3..a680c4861 100644
--- a/portable/GCC/ARM7_AT91SAM7S/ioat91sam7x256.h
+++ b/portable/GCC/ARM7_AT91SAM7S/ioat91sam7x256.h
@@ -1,4697 +1,6372 @@
-// - ----------------------------------------------------------------------------
-// -          ATMEL Microcontroller Software Support  -  ROUSSET  -
-// - ----------------------------------------------------------------------------
-// -  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
-// -  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-// -  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
-// -  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
-// -  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// -  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
-// -  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-// -  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-// -  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-// -  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// - ----------------------------------------------------------------------------
-// - File Name           : AT91SAM7X256.h
-// - Object              : AT91SAM7X256 definitions
-// - Generated           : AT91 SW Application Group  05/20/2005 (16:22:29)
-// -
-// - CVS Reference       : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005//
-// - CVS Reference       : /SYS_SAM7X.pl/1.3/Tue Feb  1 17:01:43 2005//
-// - CVS Reference       : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005//
-// - CVS Reference       : /PMC_SAM7X.pl/1.4/Tue Feb  8 13:58:10 2005//
-// - CVS Reference       : /RSTC_SAM7X.pl/1.1/Tue Feb  1 16:16:26 2005//
-// - CVS Reference       : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005//
-// - CVS Reference       : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005//
-// - CVS Reference       : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//
-// - CVS Reference       : /PIO_6057A.pl/1.2/Thu Feb  3 10:18:28 2005//
-// - CVS Reference       : /RTTC_6081A.pl/1.2/Tue Nov  9 14:43:58 2004//
-// - CVS Reference       : /PITC_6079A.pl/1.2/Tue Nov  9 14:43:56 2004//
-// - CVS Reference       : /WDTC_6080A.pl/1.3/Tue Nov  9 14:44:00 2004//
-// - CVS Reference       : /VREG_6085B.pl/1.1/Tue Feb  1 16:05:48 2005//
-// - CVS Reference       : /PDC_6074C.pl/1.2/Thu Feb  3 08:48:54 2005//
-// - CVS Reference       : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//
-// - CVS Reference       : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//
-// - CVS Reference       : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//
-// - CVS Reference       : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//
-// - CVS Reference       : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//
-// - CVS Reference       : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//
-// - CVS Reference       : /CAN_6019B.pl/1.1/Tue Mar  8 12:42:22 2005//
-// - CVS Reference       : /EMACB_6119A.pl/1.5/Thu Feb  3 15:52:04 2005//
-// - CVS Reference       : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//
-// - CVS Reference       : /AES_6149A.pl/1.10/Mon Feb  7 09:44:25 2005//
-// - CVS Reference       : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005//
-// - ----------------------------------------------------------------------------
+/* - ---------------------------------------------------------------------------- */
+/* -          ATMEL Microcontroller Software Support  -  ROUSSET  - */
+/* - ---------------------------------------------------------------------------- */
+/* -  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
+/* -  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* -  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
+/* -  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
+/* -  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* -  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
+/* -  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
+/* -  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
+/* -  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* -  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
+/* - ---------------------------------------------------------------------------- */
+/* - File Name           : AT91SAM7X256.h */
+/* - Object              : AT91SAM7X256 definitions */
+/* - Generated           : AT91 SW Application Group  05/20/2005 (16:22:29) */
+/* - */
+/* - CVS Reference       : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005// */
+/* - CVS Reference       : /SYS_SAM7X.pl/1.3/Tue Feb  1 17:01:43 2005// */
+/* - CVS Reference       : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// */
+/* - CVS Reference       : /PMC_SAM7X.pl/1.4/Tue Feb  8 13:58:10 2005// */
+/* - CVS Reference       : /RSTC_SAM7X.pl/1.1/Tue Feb  1 16:16:26 2005// */
+/* - CVS Reference       : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// */
+/* - CVS Reference       : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// */
+/* - CVS Reference       : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// */
+/* - CVS Reference       : /PIO_6057A.pl/1.2/Thu Feb  3 10:18:28 2005// */
+/* - CVS Reference       : /RTTC_6081A.pl/1.2/Tue Nov  9 14:43:58 2004// */
+/* - CVS Reference       : /PITC_6079A.pl/1.2/Tue Nov  9 14:43:56 2004// */
+/* - CVS Reference       : /WDTC_6080A.pl/1.3/Tue Nov  9 14:44:00 2004// */
+/* - CVS Reference       : /VREG_6085B.pl/1.1/Tue Feb  1 16:05:48 2005// */
+/* - CVS Reference       : /PDC_6074C.pl/1.2/Thu Feb  3 08:48:54 2005// */
+/* - CVS Reference       : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// */
+/* - CVS Reference       : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// */
+/* - CVS Reference       : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// */
+/* - CVS Reference       : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// */
+/* - CVS Reference       : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// */
+/* - CVS Reference       : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// */
+/* - CVS Reference       : /CAN_6019B.pl/1.1/Tue Mar  8 12:42:22 2005// */
+/* - CVS Reference       : /EMACB_6119A.pl/1.5/Thu Feb  3 15:52:04 2005// */
+/* - CVS Reference       : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// */
+/* - CVS Reference       : /AES_6149A.pl/1.10/Mon Feb  7 09:44:25 2005// */
+/* - CVS Reference       : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// */
+/* - ---------------------------------------------------------------------------- */
 
 #ifndef AT91SAM7X256_H
 #define AT91SAM7X256_H
 
-typedef volatile unsigned int AT91_REG;// Hardware register definition
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR System Peripherals
-// *****************************************************************************
-typedef struct _AT91S_SYS {
-    AT91_REG     AIC_SMR[32];   // Source Mode Register
-    AT91_REG     AIC_SVR[32];   // Source Vector Register
-    AT91_REG     AIC_IVR;   // IRQ Vector Register
-    AT91_REG     AIC_FVR;   // FIQ Vector Register
-    AT91_REG     AIC_ISR;   // Interrupt Status Register
-    AT91_REG     AIC_IPR;   // Interrupt Pending Register
-    AT91_REG     AIC_IMR;   // Interrupt Mask Register
-    AT91_REG     AIC_CISR;  // Core Interrupt Status Register
-    AT91_REG     Reserved0[2];  //
-    AT91_REG     AIC_IECR;  // Interrupt Enable Command Register
-    AT91_REG     AIC_IDCR;  // Interrupt Disable Command Register
-    AT91_REG     AIC_ICCR;  // Interrupt Clear Command Register
-    AT91_REG     AIC_ISCR;  // Interrupt Set Command Register
-    AT91_REG     AIC_EOICR;     // End of Interrupt Command Register
-    AT91_REG     AIC_SPU;   // Spurious Vector Register
-    AT91_REG     AIC_DCR;   // Debug Control Register (Protect)
-    AT91_REG     Reserved1[1];  //
-    AT91_REG     AIC_FFER;  // Fast Forcing Enable Register
-    AT91_REG     AIC_FFDR;  // Fast Forcing Disable Register
-    AT91_REG     AIC_FFSR;  // Fast Forcing Status Register
-    AT91_REG     Reserved2[45];     //
-    AT91_REG     DBGU_CR;   // Control Register
-    AT91_REG     DBGU_MR;   // Mode Register
-    AT91_REG     DBGU_IER;  // Interrupt Enable Register
-    AT91_REG     DBGU_IDR;  // Interrupt Disable Register
-    AT91_REG     DBGU_IMR;  // Interrupt Mask Register
-    AT91_REG     DBGU_CSR;  // Channel Status Register
-    AT91_REG     DBGU_RHR;  // Receiver Holding Register
-    AT91_REG     DBGU_THR;  // Transmitter Holding Register
-    AT91_REG     DBGU_BRGR;     // Baud Rate Generator Register
-    AT91_REG     Reserved3[7];  //
-    AT91_REG     DBGU_CIDR;     // Chip ID Register
-    AT91_REG     DBGU_EXID;     // Chip ID Extension Register
-    AT91_REG     DBGU_FNTR;     // Force NTRST Register
-    AT91_REG     Reserved4[45];     //
-    AT91_REG     DBGU_RPR;  // Receive Pointer Register
-    AT91_REG     DBGU_RCR;  // Receive Counter Register
-    AT91_REG     DBGU_TPR;  // Transmit Pointer Register
-    AT91_REG     DBGU_TCR;  // Transmit Counter Register
-    AT91_REG     DBGU_RNPR;     // Receive Next Pointer Register
-    AT91_REG     DBGU_RNCR;     // Receive Next Counter Register
-    AT91_REG     DBGU_TNPR;     // Transmit Next Pointer Register
-    AT91_REG     DBGU_TNCR;     // Transmit Next Counter Register
-    AT91_REG     DBGU_PTCR;     // PDC Transfer Control Register
-    AT91_REG     DBGU_PTSR;     // PDC Transfer Status Register
-    AT91_REG     Reserved5[54];     //
-    AT91_REG     PIOA_PER;  // PIO Enable Register
-    AT91_REG     PIOA_PDR;  // PIO Disable Register
-    AT91_REG     PIOA_PSR;  // PIO Status Register
-    AT91_REG     Reserved6[1];  //
-    AT91_REG     PIOA_OER;  // Output Enable Register
-    AT91_REG     PIOA_ODR;  // Output Disable Registerr
-    AT91_REG     PIOA_OSR;  // Output Status Register
-    AT91_REG     Reserved7[1];  //
-    AT91_REG     PIOA_IFER;     // Input Filter Enable Register
-    AT91_REG     PIOA_IFDR;     // Input Filter Disable Register
-    AT91_REG     PIOA_IFSR;     // Input Filter Status Register
-    AT91_REG     Reserved8[1];  //
-    AT91_REG     PIOA_SODR;     // Set Output Data Register
-    AT91_REG     PIOA_CODR;     // Clear Output Data Register
-    AT91_REG     PIOA_ODSR;     // Output Data Status Register
-    AT91_REG     PIOA_PDSR;     // Pin Data Status Register
-    AT91_REG     PIOA_IER;  // Interrupt Enable Register
-    AT91_REG     PIOA_IDR;  // Interrupt Disable Register
-    AT91_REG     PIOA_IMR;  // Interrupt Mask Register
-    AT91_REG     PIOA_ISR;  // Interrupt Status Register
-    AT91_REG     PIOA_MDER;     // Multi-driver Enable Register
-    AT91_REG     PIOA_MDDR;     // Multi-driver Disable Register
-    AT91_REG     PIOA_MDSR;     // Multi-driver Status Register
-    AT91_REG     Reserved9[1];  //
-    AT91_REG     PIOA_PPUDR;    // Pull-up Disable Register
-    AT91_REG     PIOA_PPUER;    // Pull-up Enable Register
-    AT91_REG     PIOA_PPUSR;    // Pull-up Status Register
-    AT91_REG     Reserved10[1];     //
-    AT91_REG     PIOA_ASR;  // Select A Register
-    AT91_REG     PIOA_BSR;  // Select B Register
-    AT91_REG     PIOA_ABSR;     // AB Select Status Register
-    AT91_REG     Reserved11[9];     //
-    AT91_REG     PIOA_OWER;     // Output Write Enable Register
-    AT91_REG     PIOA_OWDR;     // Output Write Disable Register
-    AT91_REG     PIOA_OWSR;     // Output Write Status Register
-    AT91_REG     Reserved12[85];    //
-    AT91_REG     PIOB_PER;  // PIO Enable Register
-    AT91_REG     PIOB_PDR;  // PIO Disable Register
-    AT91_REG     PIOB_PSR;  // PIO Status Register
-    AT91_REG     Reserved13[1];     //
-    AT91_REG     PIOB_OER;  // Output Enable Register
-    AT91_REG     PIOB_ODR;  // Output Disable Registerr
-    AT91_REG     PIOB_OSR;  // Output Status Register
-    AT91_REG     Reserved14[1];     //
-    AT91_REG     PIOB_IFER;     // Input Filter Enable Register
-    AT91_REG     PIOB_IFDR;     // Input Filter Disable Register
-    AT91_REG     PIOB_IFSR;     // Input Filter Status Register
-    AT91_REG     Reserved15[1];     //
-    AT91_REG     PIOB_SODR;     // Set Output Data Register
-    AT91_REG     PIOB_CODR;     // Clear Output Data Register
-    AT91_REG     PIOB_ODSR;     // Output Data Status Register
-    AT91_REG     PIOB_PDSR;     // Pin Data Status Register
-    AT91_REG     PIOB_IER;  // Interrupt Enable Register
-    AT91_REG     PIOB_IDR;  // Interrupt Disable Register
-    AT91_REG     PIOB_IMR;  // Interrupt Mask Register
-    AT91_REG     PIOB_ISR;  // Interrupt Status Register
-    AT91_REG     PIOB_MDER;     // Multi-driver Enable Register
-    AT91_REG     PIOB_MDDR;     // Multi-driver Disable Register
-    AT91_REG     PIOB_MDSR;     // Multi-driver Status Register
-    AT91_REG     Reserved16[1];     //
-    AT91_REG     PIOB_PPUDR;    // Pull-up Disable Register
-    AT91_REG     PIOB_PPUER;    // Pull-up Enable Register
-    AT91_REG     PIOB_PPUSR;    // Pull-up Status Register
-    AT91_REG     Reserved17[1];     //
-    AT91_REG     PIOB_ASR;  // Select A Register
-    AT91_REG     PIOB_BSR;  // Select B Register
-    AT91_REG     PIOB_ABSR;     // AB Select Status Register
-    AT91_REG     Reserved18[9];     //
-    AT91_REG     PIOB_OWER;     // Output Write Enable Register
-    AT91_REG     PIOB_OWDR;     // Output Write Disable Register
-    AT91_REG     PIOB_OWSR;     // Output Write Status Register
-    AT91_REG     Reserved19[341];   //
-    AT91_REG     PMC_SCER;  // System Clock Enable Register
-    AT91_REG     PMC_SCDR;  // System Clock Disable Register
-    AT91_REG     PMC_SCSR;  // System Clock Status Register
-    AT91_REG     Reserved20[1];     //
-    AT91_REG     PMC_PCER;  // Peripheral Clock Enable Register
-    AT91_REG     PMC_PCDR;  // Peripheral Clock Disable Register
-    AT91_REG     PMC_PCSR;  // Peripheral Clock Status Register
-    AT91_REG     Reserved21[1];     //
-    AT91_REG     PMC_MOR;   // Main Oscillator Register
-    AT91_REG     PMC_MCFR;  // Main Clock  Frequency Register
-    AT91_REG     Reserved22[1];     //
-    AT91_REG     PMC_PLLR;  // PLL Register
-    AT91_REG     PMC_MCKR;  // Master Clock Register
-    AT91_REG     Reserved23[3];     //
-    AT91_REG     PMC_PCKR[4];   // Programmable Clock Register
-    AT91_REG     Reserved24[4];     //
-    AT91_REG     PMC_IER;   // Interrupt Enable Register
-    AT91_REG     PMC_IDR;   // Interrupt Disable Register
-    AT91_REG     PMC_SR;    // Status Register
-    AT91_REG     PMC_IMR;   // Interrupt Mask Register
-    AT91_REG     Reserved25[36];    //
-    AT91_REG     RSTC_RCR;  // Reset Control Register
-    AT91_REG     RSTC_RSR;  // Reset Status Register
-    AT91_REG     RSTC_RMR;  // Reset Mode Register
-    AT91_REG     Reserved26[5];     //
-    AT91_REG     RTTC_RTMR;     // Real-time Mode Register
-    AT91_REG     RTTC_RTAR;     // Real-time Alarm Register
-    AT91_REG     RTTC_RTVR;     // Real-time Value Register
-    AT91_REG     RTTC_RTSR;     // Real-time Status Register
-    AT91_REG     PITC_PIMR;     // Period Interval Mode Register
-    AT91_REG     PITC_PISR;     // Period Interval Status Register
-    AT91_REG     PITC_PIVR;     // Period Interval Value Register
-    AT91_REG     PITC_PIIR;     // Period Interval Image Register
-    AT91_REG     WDTC_WDCR;     // Watchdog Control Register
-    AT91_REG     WDTC_WDMR;     // Watchdog Mode Register
-    AT91_REG     WDTC_WDSR;     // Watchdog Status Register
-    AT91_REG     Reserved27[5];     //
-    AT91_REG     VREG_MR;   // Voltage Regulator Mode Register
-} AT91S_SYS, *AT91PS_SYS;
-
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
-// *****************************************************************************
-typedef struct _AT91S_AIC {
-    AT91_REG     AIC_SMR[32];   // Source Mode Register
-    AT91_REG     AIC_SVR[32];   // Source Vector Register
-    AT91_REG     AIC_IVR;   // IRQ Vector Register
-    AT91_REG     AIC_FVR;   // FIQ Vector Register
-    AT91_REG     AIC_ISR;   // Interrupt Status Register
-    AT91_REG     AIC_IPR;   // Interrupt Pending Register
-    AT91_REG     AIC_IMR;   // Interrupt Mask Register
-    AT91_REG     AIC_CISR;  // Core Interrupt Status Register
-    AT91_REG     Reserved0[2];  //
-    AT91_REG     AIC_IECR;  // Interrupt Enable Command Register
-    AT91_REG     AIC_IDCR;  // Interrupt Disable Command Register
-    AT91_REG     AIC_ICCR;  // Interrupt Clear Command Register
-    AT91_REG     AIC_ISCR;  // Interrupt Set Command Register
-    AT91_REG     AIC_EOICR;     // End of Interrupt Command Register
-    AT91_REG     AIC_SPU;   // Spurious Vector Register
-    AT91_REG     AIC_DCR;   // Debug Control Register (Protect)
-    AT91_REG     Reserved1[1];  //
-    AT91_REG     AIC_FFER;  // Fast Forcing Enable Register
-    AT91_REG     AIC_FFDR;  // Fast Forcing Disable Register
-    AT91_REG     AIC_FFSR;  // Fast Forcing Status Register
-} AT91S_AIC, *AT91PS_AIC;
-
-// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
-#define AT91C_AIC_PRIOR       ((unsigned int) 0x7 <<  0) // (AIC) Priority Level
-#define     AT91C_AIC_PRIOR_LOWEST               ((unsigned int) 0x0) // (AIC) Lowest priority level
-#define     AT91C_AIC_PRIOR_HIGHEST              ((unsigned int) 0x7) // (AIC) Highest priority level
-#define AT91C_AIC_SRCTYPE     ((unsigned int) 0x3 <<  5) // (AIC) Interrupt Source Type
-#define     AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL       ((unsigned int) 0x0 <<  5) // (AIC) Internal Sources Code Label High-level Sensitive
-#define     AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL        ((unsigned int) 0x0 <<  5) // (AIC) External Sources Code Label Low-level Sensitive
-#define     AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE    ((unsigned int) 0x1 <<  5) // (AIC) Internal Sources Code Label Positive Edge triggered
-#define     AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE    ((unsigned int) 0x1 <<  5) // (AIC) External Sources Code Label Negative Edge triggered
-#define     AT91C_AIC_SRCTYPE_HIGH_LEVEL           ((unsigned int) 0x2 <<  5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
-#define     AT91C_AIC_SRCTYPE_POSITIVE_EDGE        ((unsigned int) 0x3 <<  5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
-// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
-#define AT91C_AIC_NFIQ        ((unsigned int) 0x1 <<  0) // (AIC) NFIQ Status
-#define AT91C_AIC_NIRQ        ((unsigned int) 0x1 <<  1) // (AIC) NIRQ Status
-// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
-#define AT91C_AIC_DCR_PROT    ((unsigned int) 0x1 <<  0) // (AIC) Protection Mode
-#define AT91C_AIC_DCR_GMSK    ((unsigned int) 0x1 <<  1) // (AIC) General Mask
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller
-// *****************************************************************************
-typedef struct _AT91S_PDC {
-    AT91_REG     PDC_RPR;   // Receive Pointer Register
-    AT91_REG     PDC_RCR;   // Receive Counter Register
-    AT91_REG     PDC_TPR;   // Transmit Pointer Register
-    AT91_REG     PDC_TCR;   // Transmit Counter Register
-    AT91_REG     PDC_RNPR;  // Receive Next Pointer Register
-    AT91_REG     PDC_RNCR;  // Receive Next Counter Register
-    AT91_REG     PDC_TNPR;  // Transmit Next Pointer Register
-    AT91_REG     PDC_TNCR;  // Transmit Next Counter Register
-    AT91_REG     PDC_PTCR;  // PDC Transfer Control Register
-    AT91_REG     PDC_PTSR;  // PDC Transfer Status Register
-} AT91S_PDC, *AT91PS_PDC;
-
-// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
-#define AT91C_PDC_RXTEN       ((unsigned int) 0x1 <<  0) // (PDC) Receiver Transfer Enable
-#define AT91C_PDC_RXTDIS      ((unsigned int) 0x1 <<  1) // (PDC) Receiver Transfer Disable
-#define AT91C_PDC_TXTEN       ((unsigned int) 0x1 <<  8) // (PDC) Transmitter Transfer Enable
-#define AT91C_PDC_TXTDIS      ((unsigned int) 0x1 <<  9) // (PDC) Transmitter Transfer Disable
-// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Debug Unit
-// *****************************************************************************
-typedef struct _AT91S_DBGU {
-    AT91_REG     DBGU_CR;   // Control Register
-    AT91_REG     DBGU_MR;   // Mode Register
-    AT91_REG     DBGU_IER;  // Interrupt Enable Register
-    AT91_REG     DBGU_IDR;  // Interrupt Disable Register
-    AT91_REG     DBGU_IMR;  // Interrupt Mask Register
-    AT91_REG     DBGU_CSR;  // Channel Status Register
-    AT91_REG     DBGU_RHR;  // Receiver Holding Register
-    AT91_REG     DBGU_THR;  // Transmitter Holding Register
-    AT91_REG     DBGU_BRGR;     // Baud Rate Generator Register
-    AT91_REG     Reserved0[7];  //
-    AT91_REG     DBGU_CIDR;     // Chip ID Register
-    AT91_REG     DBGU_EXID;     // Chip ID Extension Register
-    AT91_REG     DBGU_FNTR;     // Force NTRST Register
-    AT91_REG     Reserved1[45];     //
-    AT91_REG     DBGU_RPR;  // Receive Pointer Register
-    AT91_REG     DBGU_RCR;  // Receive Counter Register
-    AT91_REG     DBGU_TPR;  // Transmit Pointer Register
-    AT91_REG     DBGU_TCR;  // Transmit Counter Register
-    AT91_REG     DBGU_RNPR;     // Receive Next Pointer Register
-    AT91_REG     DBGU_RNCR;     // Receive Next Counter Register
-    AT91_REG     DBGU_TNPR;     // Transmit Next Pointer Register
-    AT91_REG     DBGU_TNCR;     // Transmit Next Counter Register
-    AT91_REG     DBGU_PTCR;     // PDC Transfer Control Register
-    AT91_REG     DBGU_PTSR;     // PDC Transfer Status Register
-} AT91S_DBGU, *AT91PS_DBGU;
-
-// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
-#define AT91C_US_RSTRX        ((unsigned int) 0x1 <<  2) // (DBGU) Reset Receiver
-#define AT91C_US_RSTTX        ((unsigned int) 0x1 <<  3) // (DBGU) Reset Transmitter
-#define AT91C_US_RXEN         ((unsigned int) 0x1 <<  4) // (DBGU) Receiver Enable
-#define AT91C_US_RXDIS        ((unsigned int) 0x1 <<  5) // (DBGU) Receiver Disable
-#define AT91C_US_TXEN         ((unsigned int) 0x1 <<  6) // (DBGU) Transmitter Enable
-#define AT91C_US_TXDIS        ((unsigned int) 0x1 <<  7) // (DBGU) Transmitter Disable
-#define AT91C_US_RSTSTA       ((unsigned int) 0x1 <<  8) // (DBGU) Reset Status Bits
-// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
-#define AT91C_US_PAR          ((unsigned int) 0x7 <<  9) // (DBGU) Parity type
-#define     AT91C_US_PAR_EVEN                 ((unsigned int) 0x0 <<  9) // (DBGU) Even Parity
-#define     AT91C_US_PAR_ODD                  ((unsigned int) 0x1 <<  9) // (DBGU) Odd Parity
-#define     AT91C_US_PAR_SPACE                ((unsigned int) 0x2 <<  9) // (DBGU) Parity forced to 0 (Space)
-#define     AT91C_US_PAR_MARK                 ((unsigned int) 0x3 <<  9) // (DBGU) Parity forced to 1 (Mark)
-#define     AT91C_US_PAR_NONE                 ((unsigned int) 0x4 <<  9) // (DBGU) No Parity
-#define     AT91C_US_PAR_MULTI_DROP           ((unsigned int) 0x6 <<  9) // (DBGU) Multi-drop mode
-#define AT91C_US_CHMODE       ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode
-#define     AT91C_US_CHMODE_NORMAL               ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
-#define     AT91C_US_CHMODE_AUTO                 ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
-#define     AT91C_US_CHMODE_LOCAL                ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
-#define     AT91C_US_CHMODE_REMOTE               ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
-// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
-#define AT91C_US_RXRDY        ((unsigned int) 0x1 <<  0) // (DBGU) RXRDY Interrupt
-#define AT91C_US_TXRDY        ((unsigned int) 0x1 <<  1) // (DBGU) TXRDY Interrupt
-#define AT91C_US_ENDRX        ((unsigned int) 0x1 <<  3) // (DBGU) End of Receive Transfer Interrupt
-#define AT91C_US_ENDTX        ((unsigned int) 0x1 <<  4) // (DBGU) End of Transmit Interrupt
-#define AT91C_US_OVRE         ((unsigned int) 0x1 <<  5) // (DBGU) Overrun Interrupt
-#define AT91C_US_FRAME        ((unsigned int) 0x1 <<  6) // (DBGU) Framing Error Interrupt
-#define AT91C_US_PARE         ((unsigned int) 0x1 <<  7) // (DBGU) Parity Error Interrupt
-#define AT91C_US_TXEMPTY      ((unsigned int) 0x1 <<  9) // (DBGU) TXEMPTY Interrupt
-#define AT91C_US_TXBUFE       ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt
-#define AT91C_US_RXBUFF       ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt
-#define AT91C_US_COMM_TX      ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt
-#define AT91C_US_COMM_RX      ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt
-// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
-// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
-// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
-// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
-#define AT91C_US_FORCE_NTRST  ((unsigned int) 0x1 <<  0) // (DBGU) Force NTRST in JTAG
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
-// *****************************************************************************
-typedef struct _AT91S_PIO {
-    AT91_REG     PIO_PER;   // PIO Enable Register
-    AT91_REG     PIO_PDR;   // PIO Disable Register
-    AT91_REG     PIO_PSR;   // PIO Status Register
-    AT91_REG     Reserved0[1];  //
-    AT91_REG     PIO_OER;   // Output Enable Register
-    AT91_REG     PIO_ODR;   // Output Disable Registerr
-    AT91_REG     PIO_OSR;   // Output Status Register
-    AT91_REG     Reserved1[1];  //
-    AT91_REG     PIO_IFER;  // Input Filter Enable Register
-    AT91_REG     PIO_IFDR;  // Input Filter Disable Register
-    AT91_REG     PIO_IFSR;  // Input Filter Status Register
-    AT91_REG     Reserved2[1];  //
-    AT91_REG     PIO_SODR;  // Set Output Data Register
-    AT91_REG     PIO_CODR;  // Clear Output Data Register
-    AT91_REG     PIO_ODSR;  // Output Data Status Register
-    AT91_REG     PIO_PDSR;  // Pin Data Status Register
-    AT91_REG     PIO_IER;   // Interrupt Enable Register
-    AT91_REG     PIO_IDR;   // Interrupt Disable Register
-    AT91_REG     PIO_IMR;   // Interrupt Mask Register
-    AT91_REG     PIO_ISR;   // Interrupt Status Register
-    AT91_REG     PIO_MDER;  // Multi-driver Enable Register
-    AT91_REG     PIO_MDDR;  // Multi-driver Disable Register
-    AT91_REG     PIO_MDSR;  // Multi-driver Status Register
-    AT91_REG     Reserved3[1];  //
-    AT91_REG     PIO_PPUDR;     // Pull-up Disable Register
-    AT91_REG     PIO_PPUER;     // Pull-up Enable Register
-    AT91_REG     PIO_PPUSR;     // Pull-up Status Register
-    AT91_REG     Reserved4[1];  //
-    AT91_REG     PIO_ASR;   // Select A Register
-    AT91_REG     PIO_BSR;   // Select B Register
-    AT91_REG     PIO_ABSR;  // AB Select Status Register
-    AT91_REG     Reserved5[9];  //
-    AT91_REG     PIO_OWER;  // Output Write Enable Register
-    AT91_REG     PIO_OWDR;  // Output Write Disable Register
-    AT91_REG     PIO_OWSR;  // Output Write Status Register
-} AT91S_PIO, *AT91PS_PIO;
-
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Clock Generator Controler
-// *****************************************************************************
-typedef struct _AT91S_CKGR {
-    AT91_REG     CKGR_MOR;  // Main Oscillator Register
-    AT91_REG     CKGR_MCFR;     // Main Clock  Frequency Register
-    AT91_REG     Reserved0[1];  //
-    AT91_REG     CKGR_PLLR;     // PLL Register
-} AT91S_CKGR, *AT91PS_CKGR;
-
-// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
-#define AT91C_CKGR_MOSCEN     ((unsigned int) 0x1 <<  0) // (CKGR) Main Oscillator Enable
-#define AT91C_CKGR_OSCBYPASS  ((unsigned int) 0x1 <<  1) // (CKGR) Main Oscillator Bypass
-#define AT91C_CKGR_OSCOUNT    ((unsigned int) 0xFF <<  8) // (CKGR) Main Oscillator Start-up Time
-// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
-#define AT91C_CKGR_MAINF      ((unsigned int) 0xFFFF <<  0) // (CKGR) Main Clock Frequency
-#define AT91C_CKGR_MAINRDY    ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready
-// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
-#define AT91C_CKGR_DIV        ((unsigned int) 0xFF <<  0) // (CKGR) Divider Selected
-#define     AT91C_CKGR_DIV_0                    ((unsigned int) 0x0) // (CKGR) Divider output is 0
-#define     AT91C_CKGR_DIV_BYPASS               ((unsigned int) 0x1) // (CKGR) Divider is bypassed
-#define AT91C_CKGR_PLLCOUNT   ((unsigned int) 0x3F <<  8) // (CKGR) PLL Counter
-#define AT91C_CKGR_OUT        ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range
-#define     AT91C_CKGR_OUT_0                    ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet
-#define     AT91C_CKGR_OUT_1                    ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet
-#define     AT91C_CKGR_OUT_2                    ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet
-#define     AT91C_CKGR_OUT_3                    ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_MUL        ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier
-#define AT91C_CKGR_USBDIV     ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks
-#define     AT91C_CKGR_USBDIV_0                    ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output
-#define     AT91C_CKGR_USBDIV_1                    ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
-#define     AT91C_CKGR_USBDIV_2                    ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Power Management Controler
-// *****************************************************************************
-typedef struct _AT91S_PMC {
-    AT91_REG     PMC_SCER;  // System Clock Enable Register
-    AT91_REG     PMC_SCDR;  // System Clock Disable Register
-    AT91_REG     PMC_SCSR;  // System Clock Status Register
-    AT91_REG     Reserved0[1];  //
-    AT91_REG     PMC_PCER;  // Peripheral Clock Enable Register
-    AT91_REG     PMC_PCDR;  // Peripheral Clock Disable Register
-    AT91_REG     PMC_PCSR;  // Peripheral Clock Status Register
-    AT91_REG     Reserved1[1];  //
-    AT91_REG     PMC_MOR;   // Main Oscillator Register
-    AT91_REG     PMC_MCFR;  // Main Clock  Frequency Register
-    AT91_REG     Reserved2[1];  //
-    AT91_REG     PMC_PLLR;  // PLL Register
-    AT91_REG     PMC_MCKR;  // Master Clock Register
-    AT91_REG     Reserved3[3];  //
-    AT91_REG     PMC_PCKR[4];   // Programmable Clock Register
-    AT91_REG     Reserved4[4];  //
-    AT91_REG     PMC_IER;   // Interrupt Enable Register
-    AT91_REG     PMC_IDR;   // Interrupt Disable Register
-    AT91_REG     PMC_SR;    // Status Register
-    AT91_REG     PMC_IMR;   // Interrupt Mask Register
-} AT91S_PMC, *AT91PS_PMC;
-
-// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
-#define AT91C_PMC_PCK         ((unsigned int) 0x1 <<  0) // (PMC) Processor Clock
-#define AT91C_PMC_UDP         ((unsigned int) 0x1 <<  7) // (PMC) USB Device Port Clock
-#define AT91C_PMC_PCK0        ((unsigned int) 0x1 <<  8) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK1        ((unsigned int) 0x1 <<  9) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK2        ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK3        ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output
-// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
-// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
-// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
-// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
-// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
-// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
-#define AT91C_PMC_CSS         ((unsigned int) 0x3 <<  0) // (PMC) Programmable Clock Selection
-#define     AT91C_PMC_CSS_SLOW_CLK             ((unsigned int) 0x0) // (PMC) Slow Clock is selected
-#define     AT91C_PMC_CSS_MAIN_CLK             ((unsigned int) 0x1) // (PMC) Main Clock is selected
-#define     AT91C_PMC_CSS_PLL_CLK              ((unsigned int) 0x3) // (PMC) Clock from PLL is selected
-#define AT91C_PMC_PRES        ((unsigned int) 0x7 <<  2) // (PMC) Programmable Clock Prescaler
-#define     AT91C_PMC_PRES_CLK                  ((unsigned int) 0x0 <<  2) // (PMC) Selected clock
-#define     AT91C_PMC_PRES_CLK_2                ((unsigned int) 0x1 <<  2) // (PMC) Selected clock divided by 2
-#define     AT91C_PMC_PRES_CLK_4                ((unsigned int) 0x2 <<  2) // (PMC) Selected clock divided by 4
-#define     AT91C_PMC_PRES_CLK_8                ((unsigned int) 0x3 <<  2) // (PMC) Selected clock divided by 8
-#define     AT91C_PMC_PRES_CLK_16               ((unsigned int) 0x4 <<  2) // (PMC) Selected clock divided by 16
-#define     AT91C_PMC_PRES_CLK_32               ((unsigned int) 0x5 <<  2) // (PMC) Selected clock divided by 32
-#define     AT91C_PMC_PRES_CLK_64               ((unsigned int) 0x6 <<  2) // (PMC) Selected clock divided by 64
-// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
-// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
-#define AT91C_PMC_MOSCS       ((unsigned int) 0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask
-#define AT91C_PMC_LOCK        ((unsigned int) 0x1 <<  2) // (PMC) PLL Status/Enable/Disable/Mask
-#define AT91C_PMC_MCKRDY      ((unsigned int) 0x1 <<  3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK0RDY     ((unsigned int) 0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK1RDY     ((unsigned int) 0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK2RDY     ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK3RDY     ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
-// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
-// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
-// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Reset Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_RSTC {
-    AT91_REG     RSTC_RCR;  // Reset Control Register
-    AT91_REG     RSTC_RSR;  // Reset Status Register
-    AT91_REG     RSTC_RMR;  // Reset Mode Register
-} AT91S_RSTC, *AT91PS_RSTC;
-
-// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
-#define AT91C_RSTC_PROCRST    ((unsigned int) 0x1 <<  0) // (RSTC) Processor Reset
-#define AT91C_RSTC_PERRST     ((unsigned int) 0x1 <<  2) // (RSTC) Peripheral Reset
-#define AT91C_RSTC_EXTRST     ((unsigned int) 0x1 <<  3) // (RSTC) External Reset
-#define AT91C_RSTC_KEY        ((unsigned int) 0xFF << 24) // (RSTC) Password
-// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
-#define AT91C_RSTC_URSTS      ((unsigned int) 0x1 <<  0) // (RSTC) User Reset Status
-#define AT91C_RSTC_BODSTS     ((unsigned int) 0x1 <<  1) // (RSTC) Brownout Detection Status
-#define AT91C_RSTC_RSTTYP     ((unsigned int) 0x7 <<  8) // (RSTC) Reset Type
-#define     AT91C_RSTC_RSTTYP_POWERUP              ((unsigned int) 0x0 <<  8) // (RSTC) Power-up Reset. VDDCORE rising.
-#define     AT91C_RSTC_RSTTYP_WAKEUP               ((unsigned int) 0x1 <<  8) // (RSTC) WakeUp Reset. VDDCORE rising.
-#define     AT91C_RSTC_RSTTYP_WATCHDOG             ((unsigned int) 0x2 <<  8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
-#define     AT91C_RSTC_RSTTYP_SOFTWARE             ((unsigned int) 0x3 <<  8) // (RSTC) Software Reset. Processor reset required by the software.
-#define     AT91C_RSTC_RSTTYP_USER                 ((unsigned int) 0x4 <<  8) // (RSTC) User Reset. NRST pin detected low.
-#define     AT91C_RSTC_RSTTYP_BROWNOUT             ((unsigned int) 0x5 <<  8) // (RSTC) Brownout Reset occured.
-#define AT91C_RSTC_NRSTL      ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level
-#define AT91C_RSTC_SRCMP      ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress.
-// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
-#define AT91C_RSTC_URSTEN     ((unsigned int) 0x1 <<  0) // (RSTC) User Reset Enable
-#define AT91C_RSTC_URSTIEN    ((unsigned int) 0x1 <<  4) // (RSTC) User Reset Interrupt Enable
-#define AT91C_RSTC_ERSTL      ((unsigned int) 0xF <<  8) // (RSTC) User Reset Enable
-#define AT91C_RSTC_BODIEN     ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_RTTC {
-    AT91_REG     RTTC_RTMR;     // Real-time Mode Register
-    AT91_REG     RTTC_RTAR;     // Real-time Alarm Register
-    AT91_REG     RTTC_RTVR;     // Real-time Value Register
-    AT91_REG     RTTC_RTSR;     // Real-time Status Register
-} AT91S_RTTC, *AT91PS_RTTC;
-
-// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
-#define AT91C_RTTC_RTPRES     ((unsigned int) 0xFFFF <<  0) // (RTTC) Real-time Timer Prescaler Value
-#define AT91C_RTTC_ALMIEN     ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable
-#define AT91C_RTTC_RTTINCIEN  ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
-#define AT91C_RTTC_RTTRST     ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart
-// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
-#define AT91C_RTTC_ALMV       ((unsigned int) 0x0 <<  0) // (RTTC) Alarm Value
-// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
-#define AT91C_RTTC_CRTV       ((unsigned int) 0x0 <<  0) // (RTTC) Current Real-time Value
-// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
-#define AT91C_RTTC_ALMS       ((unsigned int) 0x1 <<  0) // (RTTC) Real-time Alarm Status
-#define AT91C_RTTC_RTTINC     ((unsigned int) 0x1 <<  1) // (RTTC) Real-time Timer Increment
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_PITC {
-    AT91_REG     PITC_PIMR;     // Period Interval Mode Register
-    AT91_REG     PITC_PISR;     // Period Interval Status Register
-    AT91_REG     PITC_PIVR;     // Period Interval Value Register
-    AT91_REG     PITC_PIIR;     // Period Interval Image Register
-} AT91S_PITC, *AT91PS_PITC;
-
-// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
-#define AT91C_PITC_PIV        ((unsigned int) 0xFFFFF <<  0) // (PITC) Periodic Interval Value
-#define AT91C_PITC_PITEN      ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled
-#define AT91C_PITC_PITIEN     ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
-// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
-#define AT91C_PITC_PITS       ((unsigned int) 0x1 <<  0) // (PITC) Periodic Interval Timer Status
-// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
-#define AT91C_PITC_CPIV       ((unsigned int) 0xFFFFF <<  0) // (PITC) Current Periodic Interval Value
-#define AT91C_PITC_PICNT      ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter
-// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_WDTC {
-    AT91_REG     WDTC_WDCR;     // Watchdog Control Register
-    AT91_REG     WDTC_WDMR;     // Watchdog Mode Register
-    AT91_REG     WDTC_WDSR;     // Watchdog Status Register
-} AT91S_WDTC, *AT91PS_WDTC;
-
-// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
-#define AT91C_WDTC_WDRSTT     ((unsigned int) 0x1 <<  0) // (WDTC) Watchdog Restart
-#define AT91C_WDTC_KEY        ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password
-// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
-#define AT91C_WDTC_WDV        ((unsigned int) 0xFFF <<  0) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDFIEN     ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
-#define AT91C_WDTC_WDRSTEN    ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable
-#define AT91C_WDTC_WDRPROC    ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDDIS      ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable
-#define AT91C_WDTC_WDD        ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value
-#define AT91C_WDTC_WDDBGHLT   ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt
-#define AT91C_WDTC_WDIDLEHLT  ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt
-// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
-#define AT91C_WDTC_WDUNF      ((unsigned int) 0x1 <<  0) // (WDTC) Watchdog Underflow
-#define AT91C_WDTC_WDERR      ((unsigned int) 0x1 <<  1) // (WDTC) Watchdog Error
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Voltage Regulator Mode Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_VREG {
-    AT91_REG     VREG_MR;   // Voltage Regulator Mode Register
-} AT91S_VREG, *AT91PS_VREG;
-
-// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register --------
-#define AT91C_VREG_PSTDBY     ((unsigned int) 0x1 <<  0) // (VREG) Voltage Regulator Power Standby Mode
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Memory Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_MC {
-    AT91_REG     MC_RCR;    // MC Remap Control Register
-    AT91_REG     MC_ASR;    // MC Abort Status Register
-    AT91_REG     MC_AASR;   // MC Abort Address Status Register
-    AT91_REG     Reserved0[21];     //
-    AT91_REG     MC_FMR;    // MC Flash Mode Register
-    AT91_REG     MC_FCR;    // MC Flash Command Register
-    AT91_REG     MC_FSR;    // MC Flash Status Register
-} AT91S_MC, *AT91PS_MC;
-
-// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
-#define AT91C_MC_RCB          ((unsigned int) 0x1 <<  0) // (MC) Remap Command Bit
-// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
-#define AT91C_MC_UNDADD       ((unsigned int) 0x1 <<  0) // (MC) Undefined Addess Abort Status
-#define AT91C_MC_MISADD       ((unsigned int) 0x1 <<  1) // (MC) Misaligned Addess Abort Status
-#define AT91C_MC_ABTSZ        ((unsigned int) 0x3 <<  8) // (MC) Abort Size Status
-#define     AT91C_MC_ABTSZ_BYTE                 ((unsigned int) 0x0 <<  8) // (MC) Byte
-#define     AT91C_MC_ABTSZ_HWORD                ((unsigned int) 0x1 <<  8) // (MC) Half-word
-#define     AT91C_MC_ABTSZ_WORD                 ((unsigned int) 0x2 <<  8) // (MC) Word
-#define AT91C_MC_ABTTYP       ((unsigned int) 0x3 << 10) // (MC) Abort Type Status
-#define     AT91C_MC_ABTTYP_DATAR                ((unsigned int) 0x0 << 10) // (MC) Data Read
-#define     AT91C_MC_ABTTYP_DATAW                ((unsigned int) 0x1 << 10) // (MC) Data Write
-#define     AT91C_MC_ABTTYP_FETCH                ((unsigned int) 0x2 << 10) // (MC) Code Fetch
-#define AT91C_MC_MST0         ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source
-#define AT91C_MC_MST1         ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source
-#define AT91C_MC_SVMST0       ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source
-#define AT91C_MC_SVMST1       ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source
-// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
-#define AT91C_MC_FRDY         ((unsigned int) 0x1 <<  0) // (MC) Flash Ready
-#define AT91C_MC_LOCKE        ((unsigned int) 0x1 <<  2) // (MC) Lock Error
-#define AT91C_MC_PROGE        ((unsigned int) 0x1 <<  3) // (MC) Programming Error
-#define AT91C_MC_NEBP         ((unsigned int) 0x1 <<  7) // (MC) No Erase Before Programming
-#define AT91C_MC_FWS          ((unsigned int) 0x3 <<  8) // (MC) Flash Wait State
-#define     AT91C_MC_FWS_0FWS                 ((unsigned int) 0x0 <<  8) // (MC) 1 cycle for Read, 2 for Write operations
-#define     AT91C_MC_FWS_1FWS                 ((unsigned int) 0x1 <<  8) // (MC) 2 cycles for Read, 3 for Write operations
-#define     AT91C_MC_FWS_2FWS                 ((unsigned int) 0x2 <<  8) // (MC) 3 cycles for Read, 4 for Write operations
-#define     AT91C_MC_FWS_3FWS                 ((unsigned int) 0x3 <<  8) // (MC) 4 cycles for Read, 4 for Write operations
-#define AT91C_MC_FMCN         ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number
-// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
-#define AT91C_MC_FCMD         ((unsigned int) 0xF <<  0) // (MC) Flash Command
-#define     AT91C_MC_FCMD_START_PROG           ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN.
-#define     AT91C_MC_FCMD_LOCK                 ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define     AT91C_MC_FCMD_PROG_AND_LOCK        ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
-#define     AT91C_MC_FCMD_UNLOCK               ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define     AT91C_MC_FCMD_ERASE_ALL            ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
-#define     AT91C_MC_FCMD_SET_GP_NVM           ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits.
-#define     AT91C_MC_FCMD_CLR_GP_NVM           ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits.
-#define     AT91C_MC_FCMD_SET_SECURITY         ((unsigned int) 0xF) // (MC) Set Security Bit.
-#define AT91C_MC_PAGEN        ((unsigned int) 0x3FF <<  8) // (MC) Page Number
-#define AT91C_MC_KEY          ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key
-// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register --------
-#define AT91C_MC_SECURITY     ((unsigned int) 0x1 <<  4) // (MC) Security Bit Status
-#define AT91C_MC_GPNVM0       ((unsigned int) 0x1 <<  8) // (MC) Sector 0 Lock Status
-#define AT91C_MC_GPNVM1       ((unsigned int) 0x1 <<  9) // (MC) Sector 1 Lock Status
-#define AT91C_MC_GPNVM2       ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status
-#define AT91C_MC_GPNVM3       ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status
-#define AT91C_MC_GPNVM4       ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status
-#define AT91C_MC_GPNVM5       ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status
-#define AT91C_MC_GPNVM6       ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status
-#define AT91C_MC_GPNVM7       ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS0       ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status
-#define AT91C_MC_LOCKS1       ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status
-#define AT91C_MC_LOCKS2       ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status
-#define AT91C_MC_LOCKS3       ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status
-#define AT91C_MC_LOCKS4       ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status
-#define AT91C_MC_LOCKS5       ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status
-#define AT91C_MC_LOCKS6       ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status
-#define AT91C_MC_LOCKS7       ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS8       ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status
-#define AT91C_MC_LOCKS9       ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status
-#define AT91C_MC_LOCKS10      ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status
-#define AT91C_MC_LOCKS11      ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status
-#define AT91C_MC_LOCKS12      ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status
-#define AT91C_MC_LOCKS13      ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status
-#define AT91C_MC_LOCKS14      ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status
-#define AT91C_MC_LOCKS15      ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
-// *****************************************************************************
-typedef struct _AT91S_SPI {
-    AT91_REG     SPI_CR;    // Control Register
-    AT91_REG     SPI_MR;    // Mode Register
-    AT91_REG     SPI_RDR;   // Receive Data Register
-    AT91_REG     SPI_TDR;   // Transmit Data Register
-    AT91_REG     SPI_SR;    // Status Register
-    AT91_REG     SPI_IER;   // Interrupt Enable Register
-    AT91_REG     SPI_IDR;   // Interrupt Disable Register
-    AT91_REG     SPI_IMR;   // Interrupt Mask Register
-    AT91_REG     Reserved0[4];  //
-    AT91_REG     SPI_CSR[4];    // Chip Select Register
-    AT91_REG     Reserved1[48];     //
-    AT91_REG     SPI_RPR;   // Receive Pointer Register
-    AT91_REG     SPI_RCR;   // Receive Counter Register
-    AT91_REG     SPI_TPR;   // Transmit Pointer Register
-    AT91_REG     SPI_TCR;   // Transmit Counter Register
-    AT91_REG     SPI_RNPR;  // Receive Next Pointer Register
-    AT91_REG     SPI_RNCR;  // Receive Next Counter Register
-    AT91_REG     SPI_TNPR;  // Transmit Next Pointer Register
-    AT91_REG     SPI_TNCR;  // Transmit Next Counter Register
-    AT91_REG     SPI_PTCR;  // PDC Transfer Control Register
-    AT91_REG     SPI_PTSR;  // PDC Transfer Status Register
-} AT91S_SPI, *AT91PS_SPI;
-
-// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
-#define AT91C_SPI_SPIEN       ((unsigned int) 0x1 <<  0) // (SPI) SPI Enable
-#define AT91C_SPI_SPIDIS      ((unsigned int) 0x1 <<  1) // (SPI) SPI Disable
-#define AT91C_SPI_SWRST       ((unsigned int) 0x1 <<  7) // (SPI) SPI Software reset
-#define AT91C_SPI_LASTXFER    ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer
-// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
-#define AT91C_SPI_MSTR        ((unsigned int) 0x1 <<  0) // (SPI) Master/Slave Mode
-#define AT91C_SPI_PS          ((unsigned int) 0x1 <<  1) // (SPI) Peripheral Select
-#define     AT91C_SPI_PS_FIXED                ((unsigned int) 0x0 <<  1) // (SPI) Fixed Peripheral Select
-#define     AT91C_SPI_PS_VARIABLE             ((unsigned int) 0x1 <<  1) // (SPI) Variable Peripheral Select
-#define AT91C_SPI_PCSDEC      ((unsigned int) 0x1 <<  2) // (SPI) Chip Select Decode
-#define AT91C_SPI_FDIV        ((unsigned int) 0x1 <<  3) // (SPI) Clock Selection
-#define AT91C_SPI_MODFDIS     ((unsigned int) 0x1 <<  4) // (SPI) Mode Fault Detection
-#define AT91C_SPI_LLB         ((unsigned int) 0x1 <<  7) // (SPI) Clock Selection
-#define AT91C_SPI_PCS         ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select
-#define AT91C_SPI_DLYBCS      ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects
-// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
-#define AT91C_SPI_RD          ((unsigned int) 0xFFFF <<  0) // (SPI) Receive Data
-#define AT91C_SPI_RPCS        ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
-#define AT91C_SPI_TD          ((unsigned int) 0xFFFF <<  0) // (SPI) Transmit Data
-#define AT91C_SPI_TPCS        ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
-#define AT91C_SPI_RDRF        ((unsigned int) 0x1 <<  0) // (SPI) Receive Data Register Full
-#define AT91C_SPI_TDRE        ((unsigned int) 0x1 <<  1) // (SPI) Transmit Data Register Empty
-#define AT91C_SPI_MODF        ((unsigned int) 0x1 <<  2) // (SPI) Mode Fault Error
-#define AT91C_SPI_OVRES       ((unsigned int) 0x1 <<  3) // (SPI) Overrun Error Status
-#define AT91C_SPI_ENDRX       ((unsigned int) 0x1 <<  4) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_ENDTX       ((unsigned int) 0x1 <<  5) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_RXBUFF      ((unsigned int) 0x1 <<  6) // (SPI) RXBUFF Interrupt
-#define AT91C_SPI_TXBUFE      ((unsigned int) 0x1 <<  7) // (SPI) TXBUFE Interrupt
-#define AT91C_SPI_NSSR        ((unsigned int) 0x1 <<  8) // (SPI) NSSR Interrupt
-#define AT91C_SPI_TXEMPTY     ((unsigned int) 0x1 <<  9) // (SPI) TXEMPTY Interrupt
-#define AT91C_SPI_SPIENS      ((unsigned int) 0x1 << 16) // (SPI) Enable Status
-// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
-// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
-// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
-// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
-#define AT91C_SPI_CPOL        ((unsigned int) 0x1 <<  0) // (SPI) Clock Polarity
-#define AT91C_SPI_NCPHA       ((unsigned int) 0x1 <<  1) // (SPI) Clock Phase
-#define AT91C_SPI_CSAAT       ((unsigned int) 0x1 <<  3) // (SPI) Chip Select Active After Transfer
-#define AT91C_SPI_BITS        ((unsigned int) 0xF <<  4) // (SPI) Bits Per Transfer
-#define     AT91C_SPI_BITS_8                    ((unsigned int) 0x0 <<  4) // (SPI) 8 Bits Per transfer
-#define     AT91C_SPI_BITS_9                    ((unsigned int) 0x1 <<  4) // (SPI) 9 Bits Per transfer
-#define     AT91C_SPI_BITS_10                   ((unsigned int) 0x2 <<  4) // (SPI) 10 Bits Per transfer
-#define     AT91C_SPI_BITS_11                   ((unsigned int) 0x3 <<  4) // (SPI) 11 Bits Per transfer
-#define     AT91C_SPI_BITS_12                   ((unsigned int) 0x4 <<  4) // (SPI) 12 Bits Per transfer
-#define     AT91C_SPI_BITS_13                   ((unsigned int) 0x5 <<  4) // (SPI) 13 Bits Per transfer
-#define     AT91C_SPI_BITS_14                   ((unsigned int) 0x6 <<  4) // (SPI) 14 Bits Per transfer
-#define     AT91C_SPI_BITS_15                   ((unsigned int) 0x7 <<  4) // (SPI) 15 Bits Per transfer
-#define     AT91C_SPI_BITS_16                   ((unsigned int) 0x8 <<  4) // (SPI) 16 Bits Per transfer
-#define AT91C_SPI_SCBR        ((unsigned int) 0xFF <<  8) // (SPI) Serial Clock Baud Rate
-#define AT91C_SPI_DLYBS       ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK
-#define AT91C_SPI_DLYBCT      ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Usart
-// *****************************************************************************
-typedef struct _AT91S_USART {
-    AT91_REG     US_CR;     // Control Register
-    AT91_REG     US_MR;     // Mode Register
-    AT91_REG     US_IER;    // Interrupt Enable Register
-    AT91_REG     US_IDR;    // Interrupt Disable Register
-    AT91_REG     US_IMR;    // Interrupt Mask Register
-    AT91_REG     US_CSR;    // Channel Status Register
-    AT91_REG     US_RHR;    // Receiver Holding Register
-    AT91_REG     US_THR;    // Transmitter Holding Register
-    AT91_REG     US_BRGR;   // Baud Rate Generator Register
-    AT91_REG     US_RTOR;   // Receiver Time-out Register
-    AT91_REG     US_TTGR;   // Transmitter Time-guard Register
-    AT91_REG     Reserved0[5];  //
-    AT91_REG     US_FIDI;   // FI_DI_Ratio Register
-    AT91_REG     US_NER;    // Nb Errors Register
-    AT91_REG     Reserved1[1];  //
-    AT91_REG     US_IF;     // IRDA_FILTER Register
-    AT91_REG     Reserved2[44];     //
-    AT91_REG     US_RPR;    // Receive Pointer Register
-    AT91_REG     US_RCR;    // Receive Counter Register
-    AT91_REG     US_TPR;    // Transmit Pointer Register
-    AT91_REG     US_TCR;    // Transmit Counter Register
-    AT91_REG     US_RNPR;   // Receive Next Pointer Register
-    AT91_REG     US_RNCR;   // Receive Next Counter Register
-    AT91_REG     US_TNPR;   // Transmit Next Pointer Register
-    AT91_REG     US_TNCR;   // Transmit Next Counter Register
-    AT91_REG     US_PTCR;   // PDC Transfer Control Register
-    AT91_REG     US_PTSR;   // PDC Transfer Status Register
-} AT91S_USART, *AT91PS_USART;
-
-// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
-#define AT91C_US_STTBRK       ((unsigned int) 0x1 <<  9) // (USART) Start Break
-#define AT91C_US_STPBRK       ((unsigned int) 0x1 << 10) // (USART) Stop Break
-#define AT91C_US_STTTO        ((unsigned int) 0x1 << 11) // (USART) Start Time-out
-#define AT91C_US_SENDA        ((unsigned int) 0x1 << 12) // (USART) Send Address
-#define AT91C_US_RSTIT        ((unsigned int) 0x1 << 13) // (USART) Reset Iterations
-#define AT91C_US_RSTNACK      ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge
-#define AT91C_US_RETTO        ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out
-#define AT91C_US_DTREN        ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable
-#define AT91C_US_DTRDIS       ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable
-#define AT91C_US_RTSEN        ((unsigned int) 0x1 << 18) // (USART) Request to Send enable
-#define AT91C_US_RTSDIS       ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable
-// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
-#define AT91C_US_USMODE       ((unsigned int) 0xF <<  0) // (USART) Usart mode
-#define     AT91C_US_USMODE_NORMAL               ((unsigned int) 0x0) // (USART) Normal
-#define     AT91C_US_USMODE_RS485                ((unsigned int) 0x1) // (USART) RS485
-#define     AT91C_US_USMODE_HWHSH                ((unsigned int) 0x2) // (USART) Hardware Handshaking
-#define     AT91C_US_USMODE_MODEM                ((unsigned int) 0x3) // (USART) Modem
-#define     AT91C_US_USMODE_ISO7816_0            ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0
-#define     AT91C_US_USMODE_ISO7816_1            ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1
-#define     AT91C_US_USMODE_IRDA                 ((unsigned int) 0x8) // (USART) IrDA
-#define     AT91C_US_USMODE_SWHSH                ((unsigned int) 0xC) // (USART) Software Handshaking
-#define AT91C_US_CLKS         ((unsigned int) 0x3 <<  4) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define     AT91C_US_CLKS_CLOCK                ((unsigned int) 0x0 <<  4) // (USART) Clock
-#define     AT91C_US_CLKS_FDIV1                ((unsigned int) 0x1 <<  4) // (USART) fdiv1
-#define     AT91C_US_CLKS_SLOW                 ((unsigned int) 0x2 <<  4) // (USART) slow_clock (ARM)
-#define     AT91C_US_CLKS_EXT                  ((unsigned int) 0x3 <<  4) // (USART) External (SCK)
-#define AT91C_US_CHRL         ((unsigned int) 0x3 <<  6) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define     AT91C_US_CHRL_5_BITS               ((unsigned int) 0x0 <<  6) // (USART) Character Length: 5 bits
-#define     AT91C_US_CHRL_6_BITS               ((unsigned int) 0x1 <<  6) // (USART) Character Length: 6 bits
-#define     AT91C_US_CHRL_7_BITS               ((unsigned int) 0x2 <<  6) // (USART) Character Length: 7 bits
-#define     AT91C_US_CHRL_8_BITS               ((unsigned int) 0x3 <<  6) // (USART) Character Length: 8 bits
-#define AT91C_US_SYNC         ((unsigned int) 0x1 <<  8) // (USART) Synchronous Mode Select
-#define AT91C_US_NBSTOP       ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits
-#define     AT91C_US_NBSTOP_1_BIT                ((unsigned int) 0x0 << 12) // (USART) 1 stop bit
-#define     AT91C_US_NBSTOP_15_BIT               ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
-#define     AT91C_US_NBSTOP_2_BIT                ((unsigned int) 0x2 << 12) // (USART) 2 stop bits
-#define AT91C_US_MSBF         ((unsigned int) 0x1 << 16) // (USART) Bit Order
-#define AT91C_US_MODE9        ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length
-#define AT91C_US_CKLO         ((unsigned int) 0x1 << 18) // (USART) Clock Output Select
-#define AT91C_US_OVER         ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode
-#define AT91C_US_INACK        ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge
-#define AT91C_US_DSNACK       ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK
-#define AT91C_US_MAX_ITER     ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions
-#define AT91C_US_FILTER       ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter
-// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
-#define AT91C_US_RXBRK        ((unsigned int) 0x1 <<  2) // (USART) Break Received/End of Break
-#define AT91C_US_TIMEOUT      ((unsigned int) 0x1 <<  8) // (USART) Receiver Time-out
-#define AT91C_US_ITERATION    ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached
-#define AT91C_US_NACK         ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge
-#define AT91C_US_RIIC         ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag
-#define AT91C_US_DSRIC        ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag
-#define AT91C_US_DCDIC        ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag
-#define AT91C_US_CTSIC        ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag
-// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
-// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
-// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
-#define AT91C_US_RI           ((unsigned int) 0x1 << 20) // (USART) Image of RI Input
-#define AT91C_US_DSR          ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input
-#define AT91C_US_DCD          ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input
-#define AT91C_US_CTS          ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_SSC {
-    AT91_REG     SSC_CR;    // Control Register
-    AT91_REG     SSC_CMR;   // Clock Mode Register
-    AT91_REG     Reserved0[2];  //
-    AT91_REG     SSC_RCMR;  // Receive Clock ModeRegister
-    AT91_REG     SSC_RFMR;  // Receive Frame Mode Register
-    AT91_REG     SSC_TCMR;  // Transmit Clock Mode Register
-    AT91_REG     SSC_TFMR;  // Transmit Frame Mode Register
-    AT91_REG     SSC_RHR;   // Receive Holding Register
-    AT91_REG     SSC_THR;   // Transmit Holding Register
-    AT91_REG     Reserved1[2];  //
-    AT91_REG     SSC_RSHR;  // Receive Sync Holding Register
-    AT91_REG     SSC_TSHR;  // Transmit Sync Holding Register
-    AT91_REG     Reserved2[2];  //
-    AT91_REG     SSC_SR;    // Status Register
-    AT91_REG     SSC_IER;   // Interrupt Enable Register
-    AT91_REG     SSC_IDR;   // Interrupt Disable Register
-    AT91_REG     SSC_IMR;   // Interrupt Mask Register
-    AT91_REG     Reserved3[44];     //
-    AT91_REG     SSC_RPR;   // Receive Pointer Register
-    AT91_REG     SSC_RCR;   // Receive Counter Register
-    AT91_REG     SSC_TPR;   // Transmit Pointer Register
-    AT91_REG     SSC_TCR;   // Transmit Counter Register
-    AT91_REG     SSC_RNPR;  // Receive Next Pointer Register
-    AT91_REG     SSC_RNCR;  // Receive Next Counter Register
-    AT91_REG     SSC_TNPR;  // Transmit Next Pointer Register
-    AT91_REG     SSC_TNCR;  // Transmit Next Counter Register
-    AT91_REG     SSC_PTCR;  // PDC Transfer Control Register
-    AT91_REG     SSC_PTSR;  // PDC Transfer Status Register
-} AT91S_SSC, *AT91PS_SSC;
-
-// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
-#define AT91C_SSC_RXEN        ((unsigned int) 0x1 <<  0) // (SSC) Receive Enable
-#define AT91C_SSC_RXDIS       ((unsigned int) 0x1 <<  1) // (SSC) Receive Disable
-#define AT91C_SSC_TXEN        ((unsigned int) 0x1 <<  8) // (SSC) Transmit Enable
-#define AT91C_SSC_TXDIS       ((unsigned int) 0x1 <<  9) // (SSC) Transmit Disable
-#define AT91C_SSC_SWRST       ((unsigned int) 0x1 << 15) // (SSC) Software Reset
-// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
-#define AT91C_SSC_CKS         ((unsigned int) 0x3 <<  0) // (SSC) Receive/Transmit Clock Selection
-#define     AT91C_SSC_CKS_DIV                  ((unsigned int) 0x0) // (SSC) Divided Clock
-#define     AT91C_SSC_CKS_TK                   ((unsigned int) 0x1) // (SSC) TK Clock signal
-#define     AT91C_SSC_CKS_RK                   ((unsigned int) 0x2) // (SSC) RK pin
-#define AT91C_SSC_CKO         ((unsigned int) 0x7 <<  2) // (SSC) Receive/Transmit Clock Output Mode Selection
-#define     AT91C_SSC_CKO_NONE                 ((unsigned int) 0x0 <<  2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
-#define     AT91C_SSC_CKO_CONTINOUS            ((unsigned int) 0x1 <<  2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
-#define     AT91C_SSC_CKO_DATA_TX              ((unsigned int) 0x2 <<  2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
-#define AT91C_SSC_CKI         ((unsigned int) 0x1 <<  5) // (SSC) Receive/Transmit Clock Inversion
-#define AT91C_SSC_START       ((unsigned int) 0xF <<  8) // (SSC) Receive/Transmit Start Selection
-#define     AT91C_SSC_START_CONTINOUS            ((unsigned int) 0x0 <<  8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
-#define     AT91C_SSC_START_TX                   ((unsigned int) 0x1 <<  8) // (SSC) Transmit/Receive start
-#define     AT91C_SSC_START_LOW_RF               ((unsigned int) 0x2 <<  8) // (SSC) Detection of a low level on RF input
-#define     AT91C_SSC_START_HIGH_RF              ((unsigned int) 0x3 <<  8) // (SSC) Detection of a high level on RF input
-#define     AT91C_SSC_START_FALL_RF              ((unsigned int) 0x4 <<  8) // (SSC) Detection of a falling edge on RF input
-#define     AT91C_SSC_START_RISE_RF              ((unsigned int) 0x5 <<  8) // (SSC) Detection of a rising edge on RF input
-#define     AT91C_SSC_START_LEVEL_RF             ((unsigned int) 0x6 <<  8) // (SSC) Detection of any level change on RF input
-#define     AT91C_SSC_START_EDGE_RF              ((unsigned int) 0x7 <<  8) // (SSC) Detection of any edge on RF input
-#define     AT91C_SSC_START_0                    ((unsigned int) 0x8 <<  8) // (SSC) Compare 0
-#define AT91C_SSC_STTDLY      ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay
-#define AT91C_SSC_PERIOD      ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
-// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
-#define AT91C_SSC_DATLEN      ((unsigned int) 0x1F <<  0) // (SSC) Data Length
-#define AT91C_SSC_LOOP        ((unsigned int) 0x1 <<  5) // (SSC) Loop Mode
-#define AT91C_SSC_MSBF        ((unsigned int) 0x1 <<  7) // (SSC) Most Significant Bit First
-#define AT91C_SSC_DATNB       ((unsigned int) 0xF <<  8) // (SSC) Data Number per Frame
-#define AT91C_SSC_FSLEN       ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length
-#define AT91C_SSC_FSOS        ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
-#define     AT91C_SSC_FSOS_NONE                 ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
-#define     AT91C_SSC_FSOS_NEGATIVE             ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
-#define     AT91C_SSC_FSOS_POSITIVE             ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
-#define     AT91C_SSC_FSOS_LOW                  ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
-#define     AT91C_SSC_FSOS_HIGH                 ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
-#define     AT91C_SSC_FSOS_TOGGLE               ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
-#define AT91C_SSC_FSEDGE      ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection
-// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
-// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
-#define AT91C_SSC_DATDEF      ((unsigned int) 0x1 <<  5) // (SSC) Data Default Value
-#define AT91C_SSC_FSDEN       ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable
-// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
-#define AT91C_SSC_TXRDY       ((unsigned int) 0x1 <<  0) // (SSC) Transmit Ready
-#define AT91C_SSC_TXEMPTY     ((unsigned int) 0x1 <<  1) // (SSC) Transmit Empty
-#define AT91C_SSC_ENDTX       ((unsigned int) 0x1 <<  2) // (SSC) End Of Transmission
-#define AT91C_SSC_TXBUFE      ((unsigned int) 0x1 <<  3) // (SSC) Transmit Buffer Empty
-#define AT91C_SSC_RXRDY       ((unsigned int) 0x1 <<  4) // (SSC) Receive Ready
-#define AT91C_SSC_OVRUN       ((unsigned int) 0x1 <<  5) // (SSC) Receive Overrun
-#define AT91C_SSC_ENDRX       ((unsigned int) 0x1 <<  6) // (SSC) End of Reception
-#define AT91C_SSC_RXBUFF      ((unsigned int) 0x1 <<  7) // (SSC) Receive Buffer Full
-#define AT91C_SSC_TXSYN       ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync
-#define AT91C_SSC_RXSYN       ((unsigned int) 0x1 << 11) // (SSC) Receive Sync
-#define AT91C_SSC_TXENA       ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable
-#define AT91C_SSC_RXENA       ((unsigned int) 0x1 << 17) // (SSC) Receive Enable
-// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
-// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
-// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Two-wire Interface
-// *****************************************************************************
-typedef struct _AT91S_TWI {
-    AT91_REG     TWI_CR;    // Control Register
-    AT91_REG     TWI_MMR;   // Master Mode Register
-    AT91_REG     Reserved0[1];  //
-    AT91_REG     TWI_IADR;  // Internal Address Register
-    AT91_REG     TWI_CWGR;  // Clock Waveform Generator Register
-    AT91_REG     Reserved1[3];  //
-    AT91_REG     TWI_SR;    // Status Register
-    AT91_REG     TWI_IER;   // Interrupt Enable Register
-    AT91_REG     TWI_IDR;   // Interrupt Disable Register
-    AT91_REG     TWI_IMR;   // Interrupt Mask Register
-    AT91_REG     TWI_RHR;   // Receive Holding Register
-    AT91_REG     TWI_THR;   // Transmit Holding Register
-} AT91S_TWI, *AT91PS_TWI;
-
-// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
-#define AT91C_TWI_START       ((unsigned int) 0x1 <<  0) // (TWI) Send a START Condition
-#define AT91C_TWI_STOP        ((unsigned int) 0x1 <<  1) // (TWI) Send a STOP Condition
-#define AT91C_TWI_MSEN        ((unsigned int) 0x1 <<  2) // (TWI) TWI Master Transfer Enabled
-#define AT91C_TWI_MSDIS       ((unsigned int) 0x1 <<  3) // (TWI) TWI Master Transfer Disabled
-#define AT91C_TWI_SWRST       ((unsigned int) 0x1 <<  7) // (TWI) Software Reset
-// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
-#define AT91C_TWI_IADRSZ      ((unsigned int) 0x3 <<  8) // (TWI) Internal Device Address Size
-#define     AT91C_TWI_IADRSZ_NO                   ((unsigned int) 0x0 <<  8) // (TWI) No internal device address
-#define     AT91C_TWI_IADRSZ_1_BYTE               ((unsigned int) 0x1 <<  8) // (TWI) One-byte internal device address
-#define     AT91C_TWI_IADRSZ_2_BYTE               ((unsigned int) 0x2 <<  8) // (TWI) Two-byte internal device address
-#define     AT91C_TWI_IADRSZ_3_BYTE               ((unsigned int) 0x3 <<  8) // (TWI) Three-byte internal device address
-#define AT91C_TWI_MREAD       ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction
-#define AT91C_TWI_DADR        ((unsigned int) 0x7F << 16) // (TWI) Device Address
-// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
-#define AT91C_TWI_CLDIV       ((unsigned int) 0xFF <<  0) // (TWI) Clock Low Divider
-#define AT91C_TWI_CHDIV       ((unsigned int) 0xFF <<  8) // (TWI) Clock High Divider
-#define AT91C_TWI_CKDIV       ((unsigned int) 0x7 << 16) // (TWI) Clock Divider
-// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
-#define AT91C_TWI_TXCOMP      ((unsigned int) 0x1 <<  0) // (TWI) Transmission Completed
-#define AT91C_TWI_RXRDY       ((unsigned int) 0x1 <<  1) // (TWI) Receive holding register ReaDY
-#define AT91C_TWI_TXRDY       ((unsigned int) 0x1 <<  2) // (TWI) Transmit holding register ReaDY
-#define AT91C_TWI_OVRE        ((unsigned int) 0x1 <<  6) // (TWI) Overrun Error
-#define AT91C_TWI_UNRE        ((unsigned int) 0x1 <<  7) // (TWI) Underrun Error
-#define AT91C_TWI_NACK        ((unsigned int) 0x1 <<  8) // (TWI) Not Acknowledged
-// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
-// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
-// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR PWMC Channel Interface
-// *****************************************************************************
-typedef struct _AT91S_PWMC_CH {
-    AT91_REG     PWMC_CMR;  // Channel Mode Register
-    AT91_REG     PWMC_CDTYR;    // Channel Duty Cycle Register
-    AT91_REG     PWMC_CPRDR;    // Channel Period Register
-    AT91_REG     PWMC_CCNTR;    // Channel Counter Register
-    AT91_REG     PWMC_CUPDR;    // Channel Update Register
-    AT91_REG     PWMC_Reserved[3];  // Reserved
-} AT91S_PWMC_CH, *AT91PS_PWMC_CH;
-
-// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
-#define AT91C_PWMC_CPRE       ((unsigned int) 0xF <<  0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
-#define     AT91C_PWMC_CPRE_MCK                  ((unsigned int) 0x0) // (PWMC_CH)
-#define     AT91C_PWMC_CPRE_MCKA                 ((unsigned int) 0xB) // (PWMC_CH)
-#define     AT91C_PWMC_CPRE_MCKB                 ((unsigned int) 0xC) // (PWMC_CH)
-#define AT91C_PWMC_CALG       ((unsigned int) 0x1 <<  8) // (PWMC_CH) Channel Alignment
-#define AT91C_PWMC_CPOL       ((unsigned int) 0x1 <<  9) // (PWMC_CH) Channel Polarity
-#define AT91C_PWMC_CPD        ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period
-// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
-#define AT91C_PWMC_CDTY       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Duty Cycle
-// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
-#define AT91C_PWMC_CPRD       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Period
-// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
-#define AT91C_PWMC_CCNT       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Counter
-// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
-#define AT91C_PWMC_CUPD       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Update
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_PWMC {
-    AT91_REG     PWMC_MR;   // PWMC Mode Register
-    AT91_REG     PWMC_ENA;  // PWMC Enable Register
-    AT91_REG     PWMC_DIS;  // PWMC Disable Register
-    AT91_REG     PWMC_SR;   // PWMC Status Register
-    AT91_REG     PWMC_IER;  // PWMC Interrupt Enable Register
-    AT91_REG     PWMC_IDR;  // PWMC Interrupt Disable Register
-    AT91_REG     PWMC_IMR;  // PWMC Interrupt Mask Register
-    AT91_REG     PWMC_ISR;  // PWMC Interrupt Status Register
-    AT91_REG     Reserved0[55];     //
-    AT91_REG     PWMC_VR;   // PWMC Version Register
-    AT91_REG     Reserved1[64];     //
-    AT91S_PWMC_CH    PWMC_CH[4];    // PWMC Channel
-} AT91S_PWMC, *AT91PS_PWMC;
-
-// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
-#define AT91C_PWMC_DIVA       ((unsigned int) 0xFF <<  0) // (PWMC) CLKA divide factor.
-#define AT91C_PWMC_PREA       ((unsigned int) 0xF <<  8) // (PWMC) Divider Input Clock Prescaler A
-#define     AT91C_PWMC_PREA_MCK                  ((unsigned int) 0x0 <<  8) // (PWMC)
-#define AT91C_PWMC_DIVB       ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor.
-#define AT91C_PWMC_PREB       ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B
-#define     AT91C_PWMC_PREB_MCK                  ((unsigned int) 0x0 << 24) // (PWMC)
-// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
-#define AT91C_PWMC_CHID0      ((unsigned int) 0x1 <<  0) // (PWMC) Channel ID 0
-#define AT91C_PWMC_CHID1      ((unsigned int) 0x1 <<  1) // (PWMC) Channel ID 1
-#define AT91C_PWMC_CHID2      ((unsigned int) 0x1 <<  2) // (PWMC) Channel ID 2
-#define AT91C_PWMC_CHID3      ((unsigned int) 0x1 <<  3) // (PWMC) Channel ID 3
-// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
-// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
-// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
-// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
-// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
-// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR USB Device Interface
-// *****************************************************************************
-typedef struct _AT91S_UDP {
-    AT91_REG     UDP_NUM;   // Frame Number Register
-    AT91_REG     UDP_GLBSTATE;  // Global State Register
-    AT91_REG     UDP_FADDR;     // Function Address Register
-    AT91_REG     Reserved0[1];  //
-    AT91_REG     UDP_IER;   // Interrupt Enable Register
-    AT91_REG     UDP_IDR;   // Interrupt Disable Register
-    AT91_REG     UDP_IMR;   // Interrupt Mask Register
-    AT91_REG     UDP_ISR;   // Interrupt Status Register
-    AT91_REG     UDP_ICR;   // Interrupt Clear Register
-    AT91_REG     Reserved1[1];  //
-    AT91_REG     UDP_RSTEP;     // Reset Endpoint Register
-    AT91_REG     Reserved2[1];  //
-    AT91_REG     UDP_CSR[6];    // Endpoint Control and Status Register
-    AT91_REG     Reserved3[2];  //
-    AT91_REG     UDP_FDR[6];    // Endpoint FIFO Data Register
-    AT91_REG     Reserved4[3];  //
-    AT91_REG     UDP_TXVC;  // Transceiver Control Register
-} AT91S_UDP, *AT91PS_UDP;
-
-// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
-#define AT91C_UDP_FRM_NUM     ((unsigned int) 0x7FF <<  0) // (UDP) Frame Number as Defined in the Packet Field Formats
-#define AT91C_UDP_FRM_ERR     ((unsigned int) 0x1 << 16) // (UDP) Frame Error
-#define AT91C_UDP_FRM_OK      ((unsigned int) 0x1 << 17) // (UDP) Frame OK
-// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
-#define AT91C_UDP_FADDEN      ((unsigned int) 0x1 <<  0) // (UDP) Function Address Enable
-#define AT91C_UDP_CONFG       ((unsigned int) 0x1 <<  1) // (UDP) Configured
-#define AT91C_UDP_ESR         ((unsigned int) 0x1 <<  2) // (UDP) Enable Send Resume
-#define AT91C_UDP_RSMINPR     ((unsigned int) 0x1 <<  3) // (UDP) A Resume Has Been Sent to the Host
-#define AT91C_UDP_RMWUPE      ((unsigned int) 0x1 <<  4) // (UDP) Remote Wake Up Enable
-// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
-#define AT91C_UDP_FADD        ((unsigned int) 0xFF <<  0) // (UDP) Function Address Value
-#define AT91C_UDP_FEN         ((unsigned int) 0x1 <<  8) // (UDP) Function Enable
-// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
-#define AT91C_UDP_EPINT0      ((unsigned int) 0x1 <<  0) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT1      ((unsigned int) 0x1 <<  1) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT2      ((unsigned int) 0x1 <<  2) // (UDP) Endpoint 2 Interrupt
-#define AT91C_UDP_EPINT3      ((unsigned int) 0x1 <<  3) // (UDP) Endpoint 3 Interrupt
-#define AT91C_UDP_EPINT4      ((unsigned int) 0x1 <<  4) // (UDP) Endpoint 4 Interrupt
-#define AT91C_UDP_EPINT5      ((unsigned int) 0x1 <<  5) // (UDP) Endpoint 5 Interrupt
-#define AT91C_UDP_RXSUSP      ((unsigned int) 0x1 <<  8) // (UDP) USB Suspend Interrupt
-#define AT91C_UDP_RXRSM       ((unsigned int) 0x1 <<  9) // (UDP) USB Resume Interrupt
-#define AT91C_UDP_EXTRSM      ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt
-#define AT91C_UDP_SOFINT      ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt
-#define AT91C_UDP_WAKEUP      ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt
-// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
-// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
-// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
-#define AT91C_UDP_ENDBUSRES   ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
-// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
-// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
-#define AT91C_UDP_EP0         ((unsigned int) 0x1 <<  0) // (UDP) Reset Endpoint 0
-#define AT91C_UDP_EP1         ((unsigned int) 0x1 <<  1) // (UDP) Reset Endpoint 1
-#define AT91C_UDP_EP2         ((unsigned int) 0x1 <<  2) // (UDP) Reset Endpoint 2
-#define AT91C_UDP_EP3         ((unsigned int) 0x1 <<  3) // (UDP) Reset Endpoint 3
-#define AT91C_UDP_EP4         ((unsigned int) 0x1 <<  4) // (UDP) Reset Endpoint 4
-#define AT91C_UDP_EP5         ((unsigned int) 0x1 <<  5) // (UDP) Reset Endpoint 5
-// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
-#define AT91C_UDP_TXCOMP      ((unsigned int) 0x1 <<  0) // (UDP) Generates an IN packet with data previously written in the DPR
-#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 <<  1) // (UDP) Receive Data Bank 0
-#define AT91C_UDP_RXSETUP     ((unsigned int) 0x1 <<  2) // (UDP) Sends STALL to the Host (Control endpoints)
-#define AT91C_UDP_ISOERROR    ((unsigned int) 0x1 <<  3) // (UDP) Isochronous error (Isochronous endpoints)
-#define AT91C_UDP_TXPKTRDY    ((unsigned int) 0x1 <<  4) // (UDP) Transmit Packet Ready
-#define AT91C_UDP_FORCESTALL  ((unsigned int) 0x1 <<  5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
-#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 <<  6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
-#define AT91C_UDP_DIR         ((unsigned int) 0x1 <<  7) // (UDP) Transfer Direction
-#define AT91C_UDP_EPTYPE      ((unsigned int) 0x7 <<  8) // (UDP) Endpoint type
-#define     AT91C_UDP_EPTYPE_CTRL                 ((unsigned int) 0x0 <<  8) // (UDP) Control
-#define     AT91C_UDP_EPTYPE_ISO_OUT              ((unsigned int) 0x1 <<  8) // (UDP) Isochronous OUT
-#define     AT91C_UDP_EPTYPE_BULK_OUT             ((unsigned int) 0x2 <<  8) // (UDP) Bulk OUT
-#define     AT91C_UDP_EPTYPE_INT_OUT              ((unsigned int) 0x3 <<  8) // (UDP) Interrupt OUT
-#define     AT91C_UDP_EPTYPE_ISO_IN               ((unsigned int) 0x5 <<  8) // (UDP) Isochronous IN
-#define     AT91C_UDP_EPTYPE_BULK_IN              ((unsigned int) 0x6 <<  8) // (UDP) Bulk IN
-#define     AT91C_UDP_EPTYPE_INT_IN               ((unsigned int) 0x7 <<  8) // (UDP) Interrupt IN
-#define AT91C_UDP_DTGLE       ((unsigned int) 0x1 << 11) // (UDP) Data Toggle
-#define AT91C_UDP_EPEDS       ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable
-#define AT91C_UDP_RXBYTECNT   ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
-// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------
-#define AT91C_UDP_TXVDIS      ((unsigned int) 0x1 <<  8) // (UDP)
-#define AT91C_UDP_PUON        ((unsigned int) 0x1 <<  9) // (UDP) Pull-up ON
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
-// *****************************************************************************
-typedef struct _AT91S_TC {
-    AT91_REG     TC_CCR;    // Channel Control Register
-    AT91_REG     TC_CMR;    // Channel Mode Register (Capture Mode / Waveform Mode)
-    AT91_REG     Reserved0[2];  //
-    AT91_REG     TC_CV;     // Counter Value
-    AT91_REG     TC_RA;     // Register A
-    AT91_REG     TC_RB;     // Register B
-    AT91_REG     TC_RC;     // Register C
-    AT91_REG     TC_SR;     // Status Register
-    AT91_REG     TC_IER;    // Interrupt Enable Register
-    AT91_REG     TC_IDR;    // Interrupt Disable Register
-    AT91_REG     TC_IMR;    // Interrupt Mask Register
-} AT91S_TC, *AT91PS_TC;
-
-// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
-#define AT91C_TC_CLKEN        ((unsigned int) 0x1 <<  0) // (TC) Counter Clock Enable Command
-#define AT91C_TC_CLKDIS       ((unsigned int) 0x1 <<  1) // (TC) Counter Clock Disable Command
-#define AT91C_TC_SWTRG        ((unsigned int) 0x1 <<  2) // (TC) Software Trigger Command
-// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
-#define AT91C_TC_CLKS         ((unsigned int) 0x7 <<  0) // (TC) Clock Selection
-#define     AT91C_TC_CLKS_TIMER_DIV1_CLOCK     ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
-#define     AT91C_TC_CLKS_TIMER_DIV2_CLOCK     ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
-#define     AT91C_TC_CLKS_TIMER_DIV3_CLOCK     ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
-#define     AT91C_TC_CLKS_TIMER_DIV4_CLOCK     ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
-#define     AT91C_TC_CLKS_TIMER_DIV5_CLOCK     ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
-#define     AT91C_TC_CLKS_XC0                  ((unsigned int) 0x5) // (TC) Clock selected: XC0
-#define     AT91C_TC_CLKS_XC1                  ((unsigned int) 0x6) // (TC) Clock selected: XC1
-#define     AT91C_TC_CLKS_XC2                  ((unsigned int) 0x7) // (TC) Clock selected: XC2
-#define AT91C_TC_CLKI         ((unsigned int) 0x1 <<  3) // (TC) Clock Invert
-#define AT91C_TC_BURST        ((unsigned int) 0x3 <<  4) // (TC) Burst Signal Selection
-#define     AT91C_TC_BURST_NONE                 ((unsigned int) 0x0 <<  4) // (TC) The clock is not gated by an external signal
-#define     AT91C_TC_BURST_XC0                  ((unsigned int) 0x1 <<  4) // (TC) XC0 is ANDed with the selected clock
-#define     AT91C_TC_BURST_XC1                  ((unsigned int) 0x2 <<  4) // (TC) XC1 is ANDed with the selected clock
-#define     AT91C_TC_BURST_XC2                  ((unsigned int) 0x3 <<  4) // (TC) XC2 is ANDed with the selected clock
-#define AT91C_TC_CPCSTOP      ((unsigned int) 0x1 <<  6) // (TC) Counter Clock Stopped with RC Compare
-#define AT91C_TC_LDBSTOP      ((unsigned int) 0x1 <<  6) // (TC) Counter Clock Stopped with RB Loading
-#define AT91C_TC_CPCDIS       ((unsigned int) 0x1 <<  7) // (TC) Counter Clock Disable with RC Compare
-#define AT91C_TC_LDBDIS       ((unsigned int) 0x1 <<  7) // (TC) Counter Clock Disabled with RB Loading
-#define AT91C_TC_ETRGEDG      ((unsigned int) 0x3 <<  8) // (TC) External Trigger Edge Selection
-#define     AT91C_TC_ETRGEDG_NONE                 ((unsigned int) 0x0 <<  8) // (TC) Edge: None
-#define     AT91C_TC_ETRGEDG_RISING               ((unsigned int) 0x1 <<  8) // (TC) Edge: rising edge
-#define     AT91C_TC_ETRGEDG_FALLING              ((unsigned int) 0x2 <<  8) // (TC) Edge: falling edge
-#define     AT91C_TC_ETRGEDG_BOTH                 ((unsigned int) 0x3 <<  8) // (TC) Edge: each edge
-#define AT91C_TC_EEVTEDG      ((unsigned int) 0x3 <<  8) // (TC) External Event Edge Selection
-#define     AT91C_TC_EEVTEDG_NONE                 ((unsigned int) 0x0 <<  8) // (TC) Edge: None
-#define     AT91C_TC_EEVTEDG_RISING               ((unsigned int) 0x1 <<  8) // (TC) Edge: rising edge
-#define     AT91C_TC_EEVTEDG_FALLING              ((unsigned int) 0x2 <<  8) // (TC) Edge: falling edge
-#define     AT91C_TC_EEVTEDG_BOTH                 ((unsigned int) 0x3 <<  8) // (TC) Edge: each edge
-#define AT91C_TC_EEVT         ((unsigned int) 0x3 << 10) // (TC) External Event  Selection
-#define     AT91C_TC_EEVT_TIOB                 ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
-#define     AT91C_TC_EEVT_XC0                  ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
-#define     AT91C_TC_EEVT_XC1                  ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
-#define     AT91C_TC_EEVT_XC2                  ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
-#define AT91C_TC_ABETRG       ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
-#define AT91C_TC_ENETRG       ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable
-#define AT91C_TC_WAVESEL      ((unsigned int) 0x3 << 13) // (TC) Waveform  Selection
-#define     AT91C_TC_WAVESEL_UP                   ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
-#define     AT91C_TC_WAVESEL_UPDOWN               ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
-#define     AT91C_TC_WAVESEL_UP_AUTO              ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
-#define     AT91C_TC_WAVESEL_UPDOWN_AUTO          ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
-#define AT91C_TC_CPCTRG       ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable
-#define AT91C_TC_WAVE         ((unsigned int) 0x1 << 15) // (TC)
-#define AT91C_TC_ACPA         ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA
-#define     AT91C_TC_ACPA_NONE                 ((unsigned int) 0x0 << 16) // (TC) Effect: none
-#define     AT91C_TC_ACPA_SET                  ((unsigned int) 0x1 << 16) // (TC) Effect: set
-#define     AT91C_TC_ACPA_CLEAR                ((unsigned int) 0x2 << 16) // (TC) Effect: clear
-#define     AT91C_TC_ACPA_TOGGLE               ((unsigned int) 0x3 << 16) // (TC) Effect: toggle
-#define AT91C_TC_LDRA         ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection
-#define     AT91C_TC_LDRA_NONE                 ((unsigned int) 0x0 << 16) // (TC) Edge: None
-#define     AT91C_TC_LDRA_RISING               ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA
-#define     AT91C_TC_LDRA_FALLING              ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA
-#define     AT91C_TC_LDRA_BOTH                 ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_ACPC         ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA
-#define     AT91C_TC_ACPC_NONE                 ((unsigned int) 0x0 << 18) // (TC) Effect: none
-#define     AT91C_TC_ACPC_SET                  ((unsigned int) 0x1 << 18) // (TC) Effect: set
-#define     AT91C_TC_ACPC_CLEAR                ((unsigned int) 0x2 << 18) // (TC) Effect: clear
-#define     AT91C_TC_ACPC_TOGGLE               ((unsigned int) 0x3 << 18) // (TC) Effect: toggle
-#define AT91C_TC_LDRB         ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection
-#define     AT91C_TC_LDRB_NONE                 ((unsigned int) 0x0 << 18) // (TC) Edge: None
-#define     AT91C_TC_LDRB_RISING               ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA
-#define     AT91C_TC_LDRB_FALLING              ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA
-#define     AT91C_TC_LDRB_BOTH                 ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_AEEVT        ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA
-#define     AT91C_TC_AEEVT_NONE                 ((unsigned int) 0x0 << 20) // (TC) Effect: none
-#define     AT91C_TC_AEEVT_SET                  ((unsigned int) 0x1 << 20) // (TC) Effect: set
-#define     AT91C_TC_AEEVT_CLEAR                ((unsigned int) 0x2 << 20) // (TC) Effect: clear
-#define     AT91C_TC_AEEVT_TOGGLE               ((unsigned int) 0x3 << 20) // (TC) Effect: toggle
-#define AT91C_TC_ASWTRG       ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA
-#define     AT91C_TC_ASWTRG_NONE                 ((unsigned int) 0x0 << 22) // (TC) Effect: none
-#define     AT91C_TC_ASWTRG_SET                  ((unsigned int) 0x1 << 22) // (TC) Effect: set
-#define     AT91C_TC_ASWTRG_CLEAR                ((unsigned int) 0x2 << 22) // (TC) Effect: clear
-#define     AT91C_TC_ASWTRG_TOGGLE               ((unsigned int) 0x3 << 22) // (TC) Effect: toggle
-#define AT91C_TC_BCPB         ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB
-#define     AT91C_TC_BCPB_NONE                 ((unsigned int) 0x0 << 24) // (TC) Effect: none
-#define     AT91C_TC_BCPB_SET                  ((unsigned int) 0x1 << 24) // (TC) Effect: set
-#define     AT91C_TC_BCPB_CLEAR                ((unsigned int) 0x2 << 24) // (TC) Effect: clear
-#define     AT91C_TC_BCPB_TOGGLE               ((unsigned int) 0x3 << 24) // (TC) Effect: toggle
-#define AT91C_TC_BCPC         ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB
-#define     AT91C_TC_BCPC_NONE                 ((unsigned int) 0x0 << 26) // (TC) Effect: none
-#define     AT91C_TC_BCPC_SET                  ((unsigned int) 0x1 << 26) // (TC) Effect: set
-#define     AT91C_TC_BCPC_CLEAR                ((unsigned int) 0x2 << 26) // (TC) Effect: clear
-#define     AT91C_TC_BCPC_TOGGLE               ((unsigned int) 0x3 << 26) // (TC) Effect: toggle
-#define AT91C_TC_BEEVT        ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB
-#define     AT91C_TC_BEEVT_NONE                 ((unsigned int) 0x0 << 28) // (TC) Effect: none
-#define     AT91C_TC_BEEVT_SET                  ((unsigned int) 0x1 << 28) // (TC) Effect: set
-#define     AT91C_TC_BEEVT_CLEAR                ((unsigned int) 0x2 << 28) // (TC) Effect: clear
-#define     AT91C_TC_BEEVT_TOGGLE               ((unsigned int) 0x3 << 28) // (TC) Effect: toggle
-#define AT91C_TC_BSWTRG       ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB
-#define     AT91C_TC_BSWTRG_NONE                 ((unsigned int) 0x0 << 30) // (TC) Effect: none
-#define     AT91C_TC_BSWTRG_SET                  ((unsigned int) 0x1 << 30) // (TC) Effect: set
-#define     AT91C_TC_BSWTRG_CLEAR                ((unsigned int) 0x2 << 30) // (TC) Effect: clear
-#define     AT91C_TC_BSWTRG_TOGGLE               ((unsigned int) 0x3 << 30) // (TC) Effect: toggle
-// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
-#define AT91C_TC_COVFS        ((unsigned int) 0x1 <<  0) // (TC) Counter Overflow
-#define AT91C_TC_LOVRS        ((unsigned int) 0x1 <<  1) // (TC) Load Overrun
-#define AT91C_TC_CPAS         ((unsigned int) 0x1 <<  2) // (TC) RA Compare
-#define AT91C_TC_CPBS         ((unsigned int) 0x1 <<  3) // (TC) RB Compare
-#define AT91C_TC_CPCS         ((unsigned int) 0x1 <<  4) // (TC) RC Compare
-#define AT91C_TC_LDRAS        ((unsigned int) 0x1 <<  5) // (TC) RA Loading
-#define AT91C_TC_LDRBS        ((unsigned int) 0x1 <<  6) // (TC) RB Loading
-#define AT91C_TC_ETRGS        ((unsigned int) 0x1 <<  7) // (TC) External Trigger
-#define AT91C_TC_CLKSTA       ((unsigned int) 0x1 << 16) // (TC) Clock Enabling
-#define AT91C_TC_MTIOA        ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror
-#define AT91C_TC_MTIOB        ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror
-// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
-// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
-// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Timer Counter Interface
-// *****************************************************************************
-typedef struct _AT91S_TCB {
-    AT91S_TC     TCB_TC0;   // TC Channel 0
-    AT91_REG     Reserved0[4];  //
-    AT91S_TC     TCB_TC1;   // TC Channel 1
-    AT91_REG     Reserved1[4];  //
-    AT91S_TC     TCB_TC2;   // TC Channel 2
-    AT91_REG     Reserved2[4];  //
-    AT91_REG     TCB_BCR;   // TC Block Control Register
-    AT91_REG     TCB_BMR;   // TC Block Mode Register
-} AT91S_TCB, *AT91PS_TCB;
-
-// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
-#define AT91C_TCB_SYNC        ((unsigned int) 0x1 <<  0) // (TCB) Synchro Command
-// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
-#define AT91C_TCB_TC0XC0S     ((unsigned int) 0x3 <<  0) // (TCB) External Clock Signal 0 Selection
-#define     AT91C_TCB_TC0XC0S_TCLK0                ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0
-#define     AT91C_TCB_TC0XC0S_NONE                 ((unsigned int) 0x1) // (TCB) None signal connected to XC0
-#define     AT91C_TCB_TC0XC0S_TIOA1                ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0
-#define     AT91C_TCB_TC0XC0S_TIOA2                ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0
-#define AT91C_TCB_TC1XC1S     ((unsigned int) 0x3 <<  2) // (TCB) External Clock Signal 1 Selection
-#define     AT91C_TCB_TC1XC1S_TCLK1                ((unsigned int) 0x0 <<  2) // (TCB) TCLK1 connected to XC1
-#define     AT91C_TCB_TC1XC1S_NONE                 ((unsigned int) 0x1 <<  2) // (TCB) None signal connected to XC1
-#define     AT91C_TCB_TC1XC1S_TIOA0                ((unsigned int) 0x2 <<  2) // (TCB) TIOA0 connected to XC1
-#define     AT91C_TCB_TC1XC1S_TIOA2                ((unsigned int) 0x3 <<  2) // (TCB) TIOA2 connected to XC1
-#define AT91C_TCB_TC2XC2S     ((unsigned int) 0x3 <<  4) // (TCB) External Clock Signal 2 Selection
-#define     AT91C_TCB_TC2XC2S_TCLK2                ((unsigned int) 0x0 <<  4) // (TCB) TCLK2 connected to XC2
-#define     AT91C_TCB_TC2XC2S_NONE                 ((unsigned int) 0x1 <<  4) // (TCB) None signal connected to XC2
-#define     AT91C_TCB_TC2XC2S_TIOA0                ((unsigned int) 0x2 <<  4) // (TCB) TIOA0 connected to XC2
-#define     AT91C_TCB_TC2XC2S_TIOA1                ((unsigned int) 0x3 <<  4) // (TCB) TIOA2 connected to XC2
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Control Area Network MailBox Interface
-// *****************************************************************************
-typedef struct _AT91S_CAN_MB {
-    AT91_REG     CAN_MB_MMR;    // MailBox Mode Register
-    AT91_REG     CAN_MB_MAM;    // MailBox Acceptance Mask Register
-    AT91_REG     CAN_MB_MID;    // MailBox ID Register
-    AT91_REG     CAN_MB_MFID;   // MailBox Family ID Register
-    AT91_REG     CAN_MB_MSR;    // MailBox Status Register
-    AT91_REG     CAN_MB_MDL;    // MailBox Data Low Register
-    AT91_REG     CAN_MB_MDH;    // MailBox Data High Register
-    AT91_REG     CAN_MB_MCR;    // MailBox Control Register
-} AT91S_CAN_MB, *AT91PS_CAN_MB;
-
-// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register --------
-#define AT91C_CAN_MTIMEMARK   ((unsigned int) 0xFFFF <<  0) // (CAN_MB) Mailbox Timemark
-#define AT91C_CAN_PRIOR       ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority
-#define AT91C_CAN_MOT         ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type
-#define     AT91C_CAN_MOT_DIS                  ((unsigned int) 0x0 << 24) // (CAN_MB)
-#define     AT91C_CAN_MOT_RX                   ((unsigned int) 0x1 << 24) // (CAN_MB)
-#define     AT91C_CAN_MOT_RXOVERWRITE          ((unsigned int) 0x2 << 24) // (CAN_MB)
-#define     AT91C_CAN_MOT_TX                   ((unsigned int) 0x3 << 24) // (CAN_MB)
-#define     AT91C_CAN_MOT_CONSUMER             ((unsigned int) 0x4 << 24) // (CAN_MB)
-#define     AT91C_CAN_MOT_PRODUCER             ((unsigned int) 0x5 << 24) // (CAN_MB)
-// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register --------
-#define AT91C_CAN_MIDvB       ((unsigned int) 0x3FFFF <<  0) // (CAN_MB) Complementary bits for identifier in extended mode
-#define AT91C_CAN_MIDvA       ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode
-#define AT91C_CAN_MIDE        ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version
-// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register --------
-// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register --------
-// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register --------
-#define AT91C_CAN_MTIMESTAMP  ((unsigned int) 0xFFFF <<  0) // (CAN_MB) Timer Value
-#define AT91C_CAN_MDLC        ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code
-#define AT91C_CAN_MRTR        ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request
-#define AT91C_CAN_MABT        ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort
-#define AT91C_CAN_MRDY        ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready
-#define AT91C_CAN_MMI         ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored
-// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register --------
-// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register --------
-// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register --------
-#define AT91C_CAN_MACR        ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox
-#define AT91C_CAN_MTCR        ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Control Area Network Interface
-// *****************************************************************************
-typedef struct _AT91S_CAN {
-    AT91_REG     CAN_MR;    // Mode Register
-    AT91_REG     CAN_IER;   // Interrupt Enable Register
-    AT91_REG     CAN_IDR;   // Interrupt Disable Register
-    AT91_REG     CAN_IMR;   // Interrupt Mask Register
-    AT91_REG     CAN_SR;    // Status Register
-    AT91_REG     CAN_BR;    // Baudrate Register
-    AT91_REG     CAN_TIM;   // Timer Register
-    AT91_REG     CAN_TIMESTP;   // Time Stamp Register
-    AT91_REG     CAN_ECR;   // Error Counter Register
-    AT91_REG     CAN_TCR;   // Transfer Command Register
-    AT91_REG     CAN_ACR;   // Abort Command Register
-    AT91_REG     Reserved0[52];     //
-    AT91_REG     CAN_VR;    // Version Register
-    AT91_REG     Reserved1[64];     //
-    AT91S_CAN_MB     CAN_MB0;   // CAN Mailbox 0
-    AT91S_CAN_MB     CAN_MB1;   // CAN Mailbox 1
-    AT91S_CAN_MB     CAN_MB2;   // CAN Mailbox 2
-    AT91S_CAN_MB     CAN_MB3;   // CAN Mailbox 3
-    AT91S_CAN_MB     CAN_MB4;   // CAN Mailbox 4
-    AT91S_CAN_MB     CAN_MB5;   // CAN Mailbox 5
-    AT91S_CAN_MB     CAN_MB6;   // CAN Mailbox 6
-    AT91S_CAN_MB     CAN_MB7;   // CAN Mailbox 7
-    AT91S_CAN_MB     CAN_MB8;   // CAN Mailbox 8
-    AT91S_CAN_MB     CAN_MB9;   // CAN Mailbox 9
-    AT91S_CAN_MB     CAN_MB10;  // CAN Mailbox 10
-    AT91S_CAN_MB     CAN_MB11;  // CAN Mailbox 11
-    AT91S_CAN_MB     CAN_MB12;  // CAN Mailbox 12
-    AT91S_CAN_MB     CAN_MB13;  // CAN Mailbox 13
-    AT91S_CAN_MB     CAN_MB14;  // CAN Mailbox 14
-    AT91S_CAN_MB     CAN_MB15;  // CAN Mailbox 15
-} AT91S_CAN, *AT91PS_CAN;
-
-// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register --------
-#define AT91C_CAN_CANEN       ((unsigned int) 0x1 <<  0) // (CAN) CAN Controller Enable
-#define AT91C_CAN_LPM         ((unsigned int) 0x1 <<  1) // (CAN) Disable/Enable Low Power Mode
-#define AT91C_CAN_ABM         ((unsigned int) 0x1 <<  2) // (CAN) Disable/Enable Autobaud/Listen Mode
-#define AT91C_CAN_OVL         ((unsigned int) 0x1 <<  3) // (CAN) Disable/Enable Overload Frame
-#define AT91C_CAN_TEOF        ((unsigned int) 0x1 <<  4) // (CAN) Time Stamp messages at each end of Frame
-#define AT91C_CAN_TTM         ((unsigned int) 0x1 <<  5) // (CAN) Disable/Enable Time Trigger Mode
-#define AT91C_CAN_TIMFRZ      ((unsigned int) 0x1 <<  6) // (CAN) Enable Timer Freeze
-#define AT91C_CAN_DRPT        ((unsigned int) 0x1 <<  7) // (CAN) Disable Repeat
-// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register --------
-#define AT91C_CAN_MB0         ((unsigned int) 0x1 <<  0) // (CAN) Mailbox 0 Flag
-#define AT91C_CAN_MB1         ((unsigned int) 0x1 <<  1) // (CAN) Mailbox 1 Flag
-#define AT91C_CAN_MB2         ((unsigned int) 0x1 <<  2) // (CAN) Mailbox 2 Flag
-#define AT91C_CAN_MB3         ((unsigned int) 0x1 <<  3) // (CAN) Mailbox 3 Flag
-#define AT91C_CAN_MB4         ((unsigned int) 0x1 <<  4) // (CAN) Mailbox 4 Flag
-#define AT91C_CAN_MB5         ((unsigned int) 0x1 <<  5) // (CAN) Mailbox 5 Flag
-#define AT91C_CAN_MB6         ((unsigned int) 0x1 <<  6) // (CAN) Mailbox 6 Flag
-#define AT91C_CAN_MB7         ((unsigned int) 0x1 <<  7) // (CAN) Mailbox 7 Flag
-#define AT91C_CAN_MB8         ((unsigned int) 0x1 <<  8) // (CAN) Mailbox 8 Flag
-#define AT91C_CAN_MB9         ((unsigned int) 0x1 <<  9) // (CAN) Mailbox 9 Flag
-#define AT91C_CAN_MB10        ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag
-#define AT91C_CAN_MB11        ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag
-#define AT91C_CAN_MB12        ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag
-#define AT91C_CAN_MB13        ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag
-#define AT91C_CAN_MB14        ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag
-#define AT91C_CAN_MB15        ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag
-#define AT91C_CAN_ERRA        ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag
-#define AT91C_CAN_WARN        ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag
-#define AT91C_CAN_ERRP        ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag
-#define AT91C_CAN_BOFF        ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag
-#define AT91C_CAN_SLEEP       ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag
-#define AT91C_CAN_WAKEUP      ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag
-#define AT91C_CAN_TOVF        ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag
-#define AT91C_CAN_TSTP        ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag
-#define AT91C_CAN_CERR        ((unsigned int) 0x1 << 24) // (CAN) CRC Error
-#define AT91C_CAN_SERR        ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error
-#define AT91C_CAN_AERR        ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error
-#define AT91C_CAN_FERR        ((unsigned int) 0x1 << 27) // (CAN) Form Error
-#define AT91C_CAN_BERR        ((unsigned int) 0x1 << 28) // (CAN) Bit Error
-// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register --------
-// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register --------
-// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register --------
-#define AT91C_CAN_RBSY        ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy
-#define AT91C_CAN_TBSY        ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy
-#define AT91C_CAN_OVLY        ((unsigned int) 0x1 << 31) // (CAN) Overload Busy
-// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register --------
-#define AT91C_CAN_PHASE2      ((unsigned int) 0x7 <<  0) // (CAN) Phase 2 segment
-#define AT91C_CAN_PHASE1      ((unsigned int) 0x7 <<  4) // (CAN) Phase 1 segment
-#define AT91C_CAN_PROPAG      ((unsigned int) 0x7 <<  8) // (CAN) Programmation time segment
-#define AT91C_CAN_SYNC        ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment
-#define AT91C_CAN_BRP         ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler
-#define AT91C_CAN_SMP         ((unsigned int) 0x1 << 24) // (CAN) Sampling mode
-// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register --------
-#define AT91C_CAN_TIMER       ((unsigned int) 0xFFFF <<  0) // (CAN) Timer field
-// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register --------
-// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register --------
-#define AT91C_CAN_REC         ((unsigned int) 0xFF <<  0) // (CAN) Receive Error Counter
-#define AT91C_CAN_TEC         ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter
-// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register --------
-#define AT91C_CAN_TIMRST      ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field
-// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Ethernet MAC 10/100
-// *****************************************************************************
-typedef struct _AT91S_EMAC {
-    AT91_REG     EMAC_NCR;  // Network Control Register
-    AT91_REG     EMAC_NCFGR;    // Network Configuration Register
-    AT91_REG     EMAC_NSR;  // Network Status Register
-    AT91_REG     Reserved0[2];  //
-    AT91_REG     EMAC_TSR;  // Transmit Status Register
-    AT91_REG     EMAC_RBQP;     // Receive Buffer Queue Pointer
-    AT91_REG     EMAC_TBQP;     // Transmit Buffer Queue Pointer
-    AT91_REG     EMAC_RSR;  // Receive Status Register
-    AT91_REG     EMAC_ISR;  // Interrupt Status Register
-    AT91_REG     EMAC_IER;  // Interrupt Enable Register
-    AT91_REG     EMAC_IDR;  // Interrupt Disable Register
-    AT91_REG     EMAC_IMR;  // Interrupt Mask Register
-    AT91_REG     EMAC_MAN;  // PHY Maintenance Register
-    AT91_REG     EMAC_PTR;  // Pause Time Register
-    AT91_REG     EMAC_PFR;  // Pause Frames received Register
-    AT91_REG     EMAC_FTO;  // Frames Transmitted OK Register
-    AT91_REG     EMAC_SCF;  // Single Collision Frame Register
-    AT91_REG     EMAC_MCF;  // Multiple Collision Frame Register
-    AT91_REG     EMAC_FRO;  // Frames Received OK Register
-    AT91_REG     EMAC_FCSE;     // Frame Check Sequence Error Register
-    AT91_REG     EMAC_ALE;  // Alignment Error Register
-    AT91_REG     EMAC_DTF;  // Deferred Transmission Frame Register
-    AT91_REG     EMAC_LCOL;     // Late Collision Register
-    AT91_REG     EMAC_ECOL;     // Excessive Collision Register
-    AT91_REG     EMAC_TUND;     // Transmit Underrun Error Register
-    AT91_REG     EMAC_CSE;  // Carrier Sense Error Register
-    AT91_REG     EMAC_RRE;  // Receive Ressource Error Register
-    AT91_REG     EMAC_ROV;  // Receive Overrun Errors Register
-    AT91_REG     EMAC_RSE;  // Receive Symbol Errors Register
-    AT91_REG     EMAC_ELE;  // Excessive Length Errors Register
-    AT91_REG     EMAC_RJA;  // Receive Jabbers Register
-    AT91_REG     EMAC_USF;  // Undersize Frames Register
-    AT91_REG     EMAC_STE;  // SQE Test Error Register
-    AT91_REG     EMAC_RLE;  // Receive Length Field Mismatch Register
-    AT91_REG     EMAC_TPF;  // Transmitted Pause Frames Register
-    AT91_REG     EMAC_HRB;  // Hash Address Bottom[31:0]
-    AT91_REG     EMAC_HRT;  // Hash Address Top[63:32]
-    AT91_REG     EMAC_SA1L;     // Specific Address 1 Bottom, First 4 bytes
-    AT91_REG     EMAC_SA1H;     // Specific Address 1 Top, Last 2 bytes
-    AT91_REG     EMAC_SA2L;     // Specific Address 2 Bottom, First 4 bytes
-    AT91_REG     EMAC_SA2H;     // Specific Address 2 Top, Last 2 bytes
-    AT91_REG     EMAC_SA3L;     // Specific Address 3 Bottom, First 4 bytes
-    AT91_REG     EMAC_SA3H;     // Specific Address 3 Top, Last 2 bytes
-    AT91_REG     EMAC_SA4L;     // Specific Address 4 Bottom, First 4 bytes
-    AT91_REG     EMAC_SA4H;     // Specific Address 4 Top, Last 2 bytes
-    AT91_REG     EMAC_TID;  // Type ID Checking Register
-    AT91_REG     EMAC_TPQ;  // Transmit Pause Quantum Register
-    AT91_REG     EMAC_USRIO;    // USER Input/Output Register
-    AT91_REG     EMAC_WOL;  // Wake On LAN Register
-    AT91_REG     Reserved1[13];     //
-    AT91_REG     EMAC_REV;  // Revision Register
-} AT91S_EMAC, *AT91PS_EMAC;
-
-// -------- EMAC_NCR : (EMAC Offset: 0x0)  --------
-#define AT91C_EMAC_LB         ((unsigned int) 0x1 <<  0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
-#define AT91C_EMAC_LLB        ((unsigned int) 0x1 <<  1) // (EMAC) Loopback local.
-#define AT91C_EMAC_RE         ((unsigned int) 0x1 <<  2) // (EMAC) Receive enable.
-#define AT91C_EMAC_TE         ((unsigned int) 0x1 <<  3) // (EMAC) Transmit enable.
-#define AT91C_EMAC_MPE        ((unsigned int) 0x1 <<  4) // (EMAC) Management port enable.
-#define AT91C_EMAC_CLRSTAT    ((unsigned int) 0x1 <<  5) // (EMAC) Clear statistics registers.
-#define AT91C_EMAC_INCSTAT    ((unsigned int) 0x1 <<  6) // (EMAC) Increment statistics registers.
-#define AT91C_EMAC_WESTAT     ((unsigned int) 0x1 <<  7) // (EMAC) Write enable for statistics registers.
-#define AT91C_EMAC_BP         ((unsigned int) 0x1 <<  8) // (EMAC) Back pressure.
-#define AT91C_EMAC_TSTART     ((unsigned int) 0x1 <<  9) // (EMAC) Start Transmission.
-#define AT91C_EMAC_THALT      ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt.
-#define AT91C_EMAC_TPFR       ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame
-#define AT91C_EMAC_TZQ        ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame
-// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register --------
-#define AT91C_EMAC_SPD        ((unsigned int) 0x1 <<  0) // (EMAC) Speed.
-#define AT91C_EMAC_FD         ((unsigned int) 0x1 <<  1) // (EMAC) Full duplex.
-#define AT91C_EMAC_JFRAME     ((unsigned int) 0x1 <<  3) // (EMAC) Jumbo Frames.
-#define AT91C_EMAC_CAF        ((unsigned int) 0x1 <<  4) // (EMAC) Copy all frames.
-#define AT91C_EMAC_NBC        ((unsigned int) 0x1 <<  5) // (EMAC) No broadcast.
-#define AT91C_EMAC_MTI        ((unsigned int) 0x1 <<  6) // (EMAC) Multicast hash event enable
-#define AT91C_EMAC_UNI        ((unsigned int) 0x1 <<  7) // (EMAC) Unicast hash enable.
-#define AT91C_EMAC_BIG        ((unsigned int) 0x1 <<  8) // (EMAC) Receive 1522 bytes.
-#define AT91C_EMAC_EAE        ((unsigned int) 0x1 <<  9) // (EMAC) External address match enable.
-#define AT91C_EMAC_CLK        ((unsigned int) 0x3 << 10) // (EMAC)
-#define     AT91C_EMAC_CLK_HCLK_8               ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8
-#define     AT91C_EMAC_CLK_HCLK_16              ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16
-#define     AT91C_EMAC_CLK_HCLK_32              ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32
-#define     AT91C_EMAC_CLK_HCLK_64              ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64
-#define AT91C_EMAC_RTY        ((unsigned int) 0x1 << 12) // (EMAC)
-#define AT91C_EMAC_PAE        ((unsigned int) 0x1 << 13) // (EMAC)
-#define AT91C_EMAC_RBOF       ((unsigned int) 0x3 << 14) // (EMAC)
-#define     AT91C_EMAC_RBOF_OFFSET_0             ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer
-#define     AT91C_EMAC_RBOF_OFFSET_1             ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer
-#define     AT91C_EMAC_RBOF_OFFSET_2             ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
-#define     AT91C_EMAC_RBOF_OFFSET_3             ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
-#define AT91C_EMAC_RLCE       ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable
-#define AT91C_EMAC_DRFCS      ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS
-#define AT91C_EMAC_EFRHD      ((unsigned int) 0x1 << 18) // (EMAC)
-#define AT91C_EMAC_IRXFCS     ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS
-// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register --------
-#define AT91C_EMAC_LINKR      ((unsigned int) 0x1 <<  0) // (EMAC)
-#define AT91C_EMAC_MDIO       ((unsigned int) 0x1 <<  1) // (EMAC)
-#define AT91C_EMAC_IDLE       ((unsigned int) 0x1 <<  2) // (EMAC)
-// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register --------
-#define AT91C_EMAC_UBR        ((unsigned int) 0x1 <<  0) // (EMAC)
-#define AT91C_EMAC_COL        ((unsigned int) 0x1 <<  1) // (EMAC)
-#define AT91C_EMAC_RLES       ((unsigned int) 0x1 <<  2) // (EMAC)
-#define AT91C_EMAC_TGO        ((unsigned int) 0x1 <<  3) // (EMAC) Transmit Go
-#define AT91C_EMAC_BEX        ((unsigned int) 0x1 <<  4) // (EMAC) Buffers exhausted mid frame
-#define AT91C_EMAC_COMP       ((unsigned int) 0x1 <<  5) // (EMAC)
-#define AT91C_EMAC_UND        ((unsigned int) 0x1 <<  6) // (EMAC)
-// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register --------
-#define AT91C_EMAC_BNA        ((unsigned int) 0x1 <<  0) // (EMAC)
-#define AT91C_EMAC_REC        ((unsigned int) 0x1 <<  1) // (EMAC)
-#define AT91C_EMAC_OVR        ((unsigned int) 0x1 <<  2) // (EMAC)
-// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register --------
-#define AT91C_EMAC_MFD        ((unsigned int) 0x1 <<  0) // (EMAC)
-#define AT91C_EMAC_RCOMP      ((unsigned int) 0x1 <<  1) // (EMAC)
-#define AT91C_EMAC_RXUBR      ((unsigned int) 0x1 <<  2) // (EMAC)
-#define AT91C_EMAC_TXUBR      ((unsigned int) 0x1 <<  3) // (EMAC)
-#define AT91C_EMAC_TUNDR      ((unsigned int) 0x1 <<  4) // (EMAC)
-#define AT91C_EMAC_RLEX       ((unsigned int) 0x1 <<  5) // (EMAC)
-#define AT91C_EMAC_TXERR      ((unsigned int) 0x1 <<  6) // (EMAC)
-#define AT91C_EMAC_TCOMP      ((unsigned int) 0x1 <<  7) // (EMAC)
-#define AT91C_EMAC_LINK       ((unsigned int) 0x1 <<  9) // (EMAC)
-#define AT91C_EMAC_ROVR       ((unsigned int) 0x1 << 10) // (EMAC)
-#define AT91C_EMAC_HRESP      ((unsigned int) 0x1 << 11) // (EMAC)
-#define AT91C_EMAC_PFRE       ((unsigned int) 0x1 << 12) // (EMAC)
-#define AT91C_EMAC_PTZ        ((unsigned int) 0x1 << 13) // (EMAC)
-// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register --------
-// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register --------
-// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register --------
-// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register --------
-#define AT91C_EMAC_DATA       ((unsigned int) 0xFFFF <<  0) // (EMAC)
-#define AT91C_EMAC_CODE       ((unsigned int) 0x3 << 16) // (EMAC)
-#define AT91C_EMAC_REGA       ((unsigned int) 0x1F << 18) // (EMAC)
-#define AT91C_EMAC_PHYA       ((unsigned int) 0x1F << 23) // (EMAC)
-#define AT91C_EMAC_RW         ((unsigned int) 0x3 << 28) // (EMAC)
-#define AT91C_EMAC_SOF        ((unsigned int) 0x3 << 30) // (EMAC)
-// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register --------
-#define AT91C_EMAC_RMII       ((unsigned int) 0x1 <<  0) // (EMAC) Reduce MII
-// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register --------
-#define AT91C_EMAC_IP         ((unsigned int) 0xFFFF <<  0) // (EMAC) ARP request IP address
-#define AT91C_EMAC_MAG        ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable
-#define AT91C_EMAC_ARP        ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable
-#define AT91C_EMAC_SA1        ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable
-// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register --------
-#define AT91C_EMAC_REVREF     ((unsigned int) 0xFFFF <<  0) // (EMAC)
-#define AT91C_EMAC_PARTREF    ((unsigned int) 0xFFFF << 16) // (EMAC)
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
-// *****************************************************************************
-typedef struct _AT91S_ADC {
-    AT91_REG     ADC_CR;    // ADC Control Register
-    AT91_REG     ADC_MR;    // ADC Mode Register
-    AT91_REG     Reserved0[2];  //
-    AT91_REG     ADC_CHER;  // ADC Channel Enable Register
-    AT91_REG     ADC_CHDR;  // ADC Channel Disable Register
-    AT91_REG     ADC_CHSR;  // ADC Channel Status Register
-    AT91_REG     ADC_SR;    // ADC Status Register
-    AT91_REG     ADC_LCDR;  // ADC Last Converted Data Register
-    AT91_REG     ADC_IER;   // ADC Interrupt Enable Register
-    AT91_REG     ADC_IDR;   // ADC Interrupt Disable Register
-    AT91_REG     ADC_IMR;   // ADC Interrupt Mask Register
-    AT91_REG     ADC_CDR0;  // ADC Channel Data Register 0
-    AT91_REG     ADC_CDR1;  // ADC Channel Data Register 1
-    AT91_REG     ADC_CDR2;  // ADC Channel Data Register 2
-    AT91_REG     ADC_CDR3;  // ADC Channel Data Register 3
-    AT91_REG     ADC_CDR4;  // ADC Channel Data Register 4
-    AT91_REG     ADC_CDR5;  // ADC Channel Data Register 5
-    AT91_REG     ADC_CDR6;  // ADC Channel Data Register 6
-    AT91_REG     ADC_CDR7;  // ADC Channel Data Register 7
-    AT91_REG     Reserved1[44];     //
-    AT91_REG     ADC_RPR;   // Receive Pointer Register
-    AT91_REG     ADC_RCR;   // Receive Counter Register
-    AT91_REG     ADC_TPR;   // Transmit Pointer Register
-    AT91_REG     ADC_TCR;   // Transmit Counter Register
-    AT91_REG     ADC_RNPR;  // Receive Next Pointer Register
-    AT91_REG     ADC_RNCR;  // Receive Next Counter Register
-    AT91_REG     ADC_TNPR;  // Transmit Next Pointer Register
-    AT91_REG     ADC_TNCR;  // Transmit Next Counter Register
-    AT91_REG     ADC_PTCR;  // PDC Transfer Control Register
-    AT91_REG     ADC_PTSR;  // PDC Transfer Status Register
-} AT91S_ADC, *AT91PS_ADC;
-
-// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
-#define AT91C_ADC_SWRST       ((unsigned int) 0x1 <<  0) // (ADC) Software Reset
-#define AT91C_ADC_START       ((unsigned int) 0x1 <<  1) // (ADC) Start Conversion
-// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
-#define AT91C_ADC_TRGEN       ((unsigned int) 0x1 <<  0) // (ADC) Trigger Enable
-#define     AT91C_ADC_TRGEN_DIS                  ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
-#define     AT91C_ADC_TRGEN_EN                   ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
-#define AT91C_ADC_TRGSEL      ((unsigned int) 0x7 <<  1) // (ADC) Trigger Selection
-#define     AT91C_ADC_TRGSEL_TIOA0                ((unsigned int) 0x0 <<  1) // (ADC) Selected TRGSEL = TIAO0
-#define     AT91C_ADC_TRGSEL_TIOA1                ((unsigned int) 0x1 <<  1) // (ADC) Selected TRGSEL = TIAO1
-#define     AT91C_ADC_TRGSEL_TIOA2                ((unsigned int) 0x2 <<  1) // (ADC) Selected TRGSEL = TIAO2
-#define     AT91C_ADC_TRGSEL_TIOA3                ((unsigned int) 0x3 <<  1) // (ADC) Selected TRGSEL = TIAO3
-#define     AT91C_ADC_TRGSEL_TIOA4                ((unsigned int) 0x4 <<  1) // (ADC) Selected TRGSEL = TIAO4
-#define     AT91C_ADC_TRGSEL_TIOA5                ((unsigned int) 0x5 <<  1) // (ADC) Selected TRGSEL = TIAO5
-#define     AT91C_ADC_TRGSEL_EXT                  ((unsigned int) 0x6 <<  1) // (ADC) Selected TRGSEL = External Trigger
-#define AT91C_ADC_LOWRES      ((unsigned int) 0x1 <<  4) // (ADC) Resolution.
-#define     AT91C_ADC_LOWRES_10_BIT               ((unsigned int) 0x0 <<  4) // (ADC) 10-bit resolution
-#define     AT91C_ADC_LOWRES_8_BIT                ((unsigned int) 0x1 <<  4) // (ADC) 8-bit resolution
-#define AT91C_ADC_SLEEP       ((unsigned int) 0x1 <<  5) // (ADC) Sleep Mode
-#define     AT91C_ADC_SLEEP_NORMAL_MODE          ((unsigned int) 0x0 <<  5) // (ADC) Normal Mode
-#define     AT91C_ADC_SLEEP_MODE                 ((unsigned int) 0x1 <<  5) // (ADC) Sleep Mode
-#define AT91C_ADC_PRESCAL     ((unsigned int) 0x3F <<  8) // (ADC) Prescaler rate selection
-#define AT91C_ADC_STARTUP     ((unsigned int) 0x1F << 16) // (ADC) Startup Time
-#define AT91C_ADC_SHTIM       ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time
-// --------     ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
-#define AT91C_ADC_CH0         ((unsigned int) 0x1 <<  0) // (ADC) Channel 0
-#define AT91C_ADC_CH1         ((unsigned int) 0x1 <<  1) // (ADC) Channel 1
-#define AT91C_ADC_CH2         ((unsigned int) 0x1 <<  2) // (ADC) Channel 2
-#define AT91C_ADC_CH3         ((unsigned int) 0x1 <<  3) // (ADC) Channel 3
-#define AT91C_ADC_CH4         ((unsigned int) 0x1 <<  4) // (ADC) Channel 4
-#define AT91C_ADC_CH5         ((unsigned int) 0x1 <<  5) // (ADC) Channel 5
-#define AT91C_ADC_CH6         ((unsigned int) 0x1 <<  6) // (ADC) Channel 6
-#define AT91C_ADC_CH7         ((unsigned int) 0x1 <<  7) // (ADC) Channel 7
-// --------     ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
-// --------     ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
-// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
-#define AT91C_ADC_EOC0        ((unsigned int) 0x1 <<  0) // (ADC) End of Conversion
-#define AT91C_ADC_EOC1        ((unsigned int) 0x1 <<  1) // (ADC) End of Conversion
-#define AT91C_ADC_EOC2        ((unsigned int) 0x1 <<  2) // (ADC) End of Conversion
-#define AT91C_ADC_EOC3        ((unsigned int) 0x1 <<  3) // (ADC) End of Conversion
-#define AT91C_ADC_EOC4        ((unsigned int) 0x1 <<  4) // (ADC) End of Conversion
-#define AT91C_ADC_EOC5        ((unsigned int) 0x1 <<  5) // (ADC) End of Conversion
-#define AT91C_ADC_EOC6        ((unsigned int) 0x1 <<  6) // (ADC) End of Conversion
-#define AT91C_ADC_EOC7        ((unsigned int) 0x1 <<  7) // (ADC) End of Conversion
-#define AT91C_ADC_OVRE0       ((unsigned int) 0x1 <<  8) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE1       ((unsigned int) 0x1 <<  9) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE2       ((unsigned int) 0x1 << 10) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE3       ((unsigned int) 0x1 << 11) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE4       ((unsigned int) 0x1 << 12) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE5       ((unsigned int) 0x1 << 13) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE6       ((unsigned int) 0x1 << 14) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE7       ((unsigned int) 0x1 << 15) // (ADC) Overrun Error
-#define AT91C_ADC_DRDY        ((unsigned int) 0x1 << 16) // (ADC) Data Ready
-#define AT91C_ADC_GOVRE       ((unsigned int) 0x1 << 17) // (ADC) General Overrun
-#define AT91C_ADC_ENDRX       ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer
-#define AT91C_ADC_RXBUFF      ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt
-// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
-#define AT91C_ADC_LDATA       ((unsigned int) 0x3FF <<  0) // (ADC) Last Data Converted
-// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
-// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
-// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
-// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
-#define AT91C_ADC_DATA        ((unsigned int) 0x3FF <<  0) // (ADC) Converted Data
-// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
-// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
-// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
-// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
-// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
-// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
-// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Advanced  Encryption Standard
-// *****************************************************************************
-typedef struct _AT91S_AES {
-    AT91_REG     AES_CR;    // Control Register
-    AT91_REG     AES_MR;    // Mode Register
-    AT91_REG     Reserved0[2];  //
-    AT91_REG     AES_IER;   // Interrupt Enable Register
-    AT91_REG     AES_IDR;   // Interrupt Disable Register
-    AT91_REG     AES_IMR;   // Interrupt Mask Register
-    AT91_REG     AES_ISR;   // Interrupt Status Register
-    AT91_REG     AES_KEYWxR[4];     // Key Word x Register
-    AT91_REG     Reserved1[4];  //
-    AT91_REG     AES_IDATAxR[4];    // Input Data x Register
-    AT91_REG     AES_ODATAxR[4];    // Output Data x Register
-    AT91_REG     AES_IVxR[4];   // Initialization Vector x Register
-    AT91_REG     Reserved2[35];     //
-    AT91_REG     AES_VR;    // AES Version Register
-    AT91_REG     AES_RPR;   // Receive Pointer Register
-    AT91_REG     AES_RCR;   // Receive Counter Register
-    AT91_REG     AES_TPR;   // Transmit Pointer Register
-    AT91_REG     AES_TCR;   // Transmit Counter Register
-    AT91_REG     AES_RNPR;  // Receive Next Pointer Register
-    AT91_REG     AES_RNCR;  // Receive Next Counter Register
-    AT91_REG     AES_TNPR;  // Transmit Next Pointer Register
-    AT91_REG     AES_TNCR;  // Transmit Next Counter Register
-    AT91_REG     AES_PTCR;  // PDC Transfer Control Register
-    AT91_REG     AES_PTSR;  // PDC Transfer Status Register
-} AT91S_AES, *AT91PS_AES;
-
-// -------- AES_CR : (AES Offset: 0x0) Control Register --------
-#define AT91C_AES_START       ((unsigned int) 0x1 <<  0) // (AES) Starts Processing
-#define AT91C_AES_SWRST       ((unsigned int) 0x1 <<  8) // (AES) Software Reset
-#define AT91C_AES_LOADSEED    ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading
-// -------- AES_MR : (AES Offset: 0x4) Mode Register --------
-#define AT91C_AES_CIPHER      ((unsigned int) 0x1 <<  0) // (AES) Processing Mode
-#define AT91C_AES_PROCDLY     ((unsigned int) 0xF <<  4) // (AES) Processing Delay
-#define AT91C_AES_SMOD        ((unsigned int) 0x3 <<  8) // (AES) Start Mode
-#define     AT91C_AES_SMOD_MANUAL               ((unsigned int) 0x0 <<  8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.
-#define     AT91C_AES_SMOD_AUTO                 ((unsigned int) 0x1 <<  8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).
-#define     AT91C_AES_SMOD_PDC                  ((unsigned int) 0x2 <<  8) // (AES) PDC Mode (cf datasheet).
-#define AT91C_AES_OPMOD       ((unsigned int) 0x7 << 12) // (AES) Operation Mode
-#define     AT91C_AES_OPMOD_ECB                  ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode.
-#define     AT91C_AES_OPMOD_CBC                  ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode.
-#define     AT91C_AES_OPMOD_OFB                  ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode.
-#define     AT91C_AES_OPMOD_CFB                  ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode.
-#define     AT91C_AES_OPMOD_CTR                  ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode.
-#define AT91C_AES_LOD         ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode
-#define AT91C_AES_CFBS        ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size
-#define     AT91C_AES_CFBS_128_BIT              ((unsigned int) 0x0 << 16) // (AES) 128-bit.
-#define     AT91C_AES_CFBS_64_BIT               ((unsigned int) 0x1 << 16) // (AES) 64-bit.
-#define     AT91C_AES_CFBS_32_BIT               ((unsigned int) 0x2 << 16) // (AES) 32-bit.
-#define     AT91C_AES_CFBS_16_BIT               ((unsigned int) 0x3 << 16) // (AES) 16-bit.
-#define     AT91C_AES_CFBS_8_BIT                ((unsigned int) 0x4 << 16) // (AES) 8-bit.
-#define AT91C_AES_CKEY        ((unsigned int) 0xF << 20) // (AES) Countermeasure Key
-#define AT91C_AES_CTYPE       ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type
-#define     AT91C_AES_CTYPE_TYPE1_EN             ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled.
-#define     AT91C_AES_CTYPE_TYPE2_EN             ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled.
-#define     AT91C_AES_CTYPE_TYPE3_EN             ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled.
-#define     AT91C_AES_CTYPE_TYPE4_EN             ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled.
-#define     AT91C_AES_CTYPE_TYPE5_EN             ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled.
-// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register --------
-#define AT91C_AES_DATRDY      ((unsigned int) 0x1 <<  0) // (AES) DATRDY
-#define AT91C_AES_ENDRX       ((unsigned int) 0x1 <<  1) // (AES) PDC Read Buffer End
-#define AT91C_AES_ENDTX       ((unsigned int) 0x1 <<  2) // (AES) PDC Write Buffer End
-#define AT91C_AES_RXBUFF      ((unsigned int) 0x1 <<  3) // (AES) PDC Read Buffer Full
-#define AT91C_AES_TXBUFE      ((unsigned int) 0x1 <<  4) // (AES) PDC Write Buffer Empty
-#define AT91C_AES_URAD        ((unsigned int) 0x1 <<  8) // (AES) Unspecified Register Access Detection
-// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register --------
-// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register --------
-// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register --------
-#define AT91C_AES_URAT        ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status
-#define     AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode.
-#define     AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing.
-#define     AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing.
-#define     AT91C_AES_URAT_OUT_DAT_READ_SUBKEY  ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation.
-#define     AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation.
-#define     AT91C_AES_URAT_WO_REG_READ          ((unsigned int) 0x5 << 12) // (AES) Write-only register read access.
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Triple Data Encryption Standard
-// *****************************************************************************
-typedef struct _AT91S_TDES {
-    AT91_REG     TDES_CR;   // Control Register
-    AT91_REG     TDES_MR;   // Mode Register
-    AT91_REG     Reserved0[2];  //
-    AT91_REG     TDES_IER;  // Interrupt Enable Register
-    AT91_REG     TDES_IDR;  // Interrupt Disable Register
-    AT91_REG     TDES_IMR;  // Interrupt Mask Register
-    AT91_REG     TDES_ISR;  // Interrupt Status Register
-    AT91_REG     TDES_KEY1WxR[2];   // Key 1 Word x Register
-    AT91_REG     TDES_KEY2WxR[2];   // Key 2 Word x Register
-    AT91_REG     TDES_KEY3WxR[2];   // Key 3 Word x Register
-    AT91_REG     Reserved1[2];  //
-    AT91_REG     TDES_IDATAxR[2];   // Input Data x Register
-    AT91_REG     Reserved2[2];  //
-    AT91_REG     TDES_ODATAxR[2];   // Output Data x Register
-    AT91_REG     Reserved3[2];  //
-    AT91_REG     TDES_IVxR[2];  // Initialization Vector x Register
-    AT91_REG     Reserved4[37];     //
-    AT91_REG     TDES_VR;   // TDES Version Register
-    AT91_REG     TDES_RPR;  // Receive Pointer Register
-    AT91_REG     TDES_RCR;  // Receive Counter Register
-    AT91_REG     TDES_TPR;  // Transmit Pointer Register
-    AT91_REG     TDES_TCR;  // Transmit Counter Register
-    AT91_REG     TDES_RNPR;     // Receive Next Pointer Register
-    AT91_REG     TDES_RNCR;     // Receive Next Counter Register
-    AT91_REG     TDES_TNPR;     // Transmit Next Pointer Register
-    AT91_REG     TDES_TNCR;     // Transmit Next Counter Register
-    AT91_REG     TDES_PTCR;     // PDC Transfer Control Register
-    AT91_REG     TDES_PTSR;     // PDC Transfer Status Register
-} AT91S_TDES, *AT91PS_TDES;
-
-// -------- TDES_CR : (TDES Offset: 0x0) Control Register --------
-#define AT91C_TDES_START      ((unsigned int) 0x1 <<  0) // (TDES) Starts Processing
-#define AT91C_TDES_SWRST      ((unsigned int) 0x1 <<  8) // (TDES) Software Reset
-// -------- TDES_MR : (TDES Offset: 0x4) Mode Register --------
-#define AT91C_TDES_CIPHER     ((unsigned int) 0x1 <<  0) // (TDES) Processing Mode
-#define AT91C_TDES_TDESMOD    ((unsigned int) 0x1 <<  1) // (TDES) Single or Triple DES Mode
-#define AT91C_TDES_KEYMOD     ((unsigned int) 0x1 <<  4) // (TDES) Key Mode
-#define AT91C_TDES_SMOD       ((unsigned int) 0x3 <<  8) // (TDES) Start Mode
-#define     AT91C_TDES_SMOD_MANUAL               ((unsigned int) 0x0 <<  8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.
-#define     AT91C_TDES_SMOD_AUTO                 ((unsigned int) 0x1 <<  8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).
-#define     AT91C_TDES_SMOD_PDC                  ((unsigned int) 0x2 <<  8) // (TDES) PDC Mode (cf datasheet).
-#define AT91C_TDES_OPMOD      ((unsigned int) 0x3 << 12) // (TDES) Operation Mode
-#define     AT91C_TDES_OPMOD_ECB                  ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode.
-#define     AT91C_TDES_OPMOD_CBC                  ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode.
-#define     AT91C_TDES_OPMOD_OFB                  ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode.
-#define     AT91C_TDES_OPMOD_CFB                  ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode.
-#define AT91C_TDES_LOD        ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode
-#define AT91C_TDES_CFBS       ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size
-#define     AT91C_TDES_CFBS_64_BIT               ((unsigned int) 0x0 << 16) // (TDES) 64-bit.
-#define     AT91C_TDES_CFBS_32_BIT               ((unsigned int) 0x1 << 16) // (TDES) 32-bit.
-#define     AT91C_TDES_CFBS_16_BIT               ((unsigned int) 0x2 << 16) // (TDES) 16-bit.
-#define     AT91C_TDES_CFBS_8_BIT                ((unsigned int) 0x3 << 16) // (TDES) 8-bit.
-// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register --------
-#define AT91C_TDES_DATRDY     ((unsigned int) 0x1 <<  0) // (TDES) DATRDY
-#define AT91C_TDES_ENDRX      ((unsigned int) 0x1 <<  1) // (TDES) PDC Read Buffer End
-#define AT91C_TDES_ENDTX      ((unsigned int) 0x1 <<  2) // (TDES) PDC Write Buffer End
-#define AT91C_TDES_RXBUFF     ((unsigned int) 0x1 <<  3) // (TDES) PDC Read Buffer Full
-#define AT91C_TDES_TXBUFE     ((unsigned int) 0x1 <<  4) // (TDES) PDC Write Buffer Empty
-#define AT91C_TDES_URAD       ((unsigned int) 0x1 <<  8) // (TDES) Unspecified Register Access Detection
-// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register --------
-// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register --------
-// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register --------
-#define AT91C_TDES_URAT       ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status
-#define     AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode.
-#define     AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing.
-#define     AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing.
-#define     AT91C_TDES_URAT_WO_REG_READ          ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access.
-
-// *****************************************************************************
-//               REGISTER ADDRESS DEFINITION FOR AT91SAM7X256
-// *****************************************************************************
-// ========== Register definition for SYS peripheral ==========
-// ========== Register definition for AIC peripheral ==========
-#define AT91C_AIC_IVR   ((AT91_REG *)   0xFFFFF100) // (AIC) IRQ Vector Register
-#define AT91C_AIC_SMR   ((AT91_REG *)   0xFFFFF000) // (AIC) Source Mode Register
-#define AT91C_AIC_FVR   ((AT91_REG *)   0xFFFFF104) // (AIC) FIQ Vector Register
-#define AT91C_AIC_DCR   ((AT91_REG *)   0xFFFFF138) // (AIC) Debug Control Register (Protect)
-#define AT91C_AIC_EOICR ((AT91_REG *)   0xFFFFF130) // (AIC) End of Interrupt Command Register
-#define AT91C_AIC_SVR   ((AT91_REG *)   0xFFFFF080) // (AIC) Source Vector Register
-#define AT91C_AIC_FFSR  ((AT91_REG *)   0xFFFFF148) // (AIC) Fast Forcing Status Register
-#define AT91C_AIC_ICCR  ((AT91_REG *)   0xFFFFF128) // (AIC) Interrupt Clear Command Register
-#define AT91C_AIC_ISR   ((AT91_REG *)   0xFFFFF108) // (AIC) Interrupt Status Register
-#define AT91C_AIC_IMR   ((AT91_REG *)   0xFFFFF110) // (AIC) Interrupt Mask Register
-#define AT91C_AIC_IPR   ((AT91_REG *)   0xFFFFF10C) // (AIC) Interrupt Pending Register
-#define AT91C_AIC_FFER  ((AT91_REG *)   0xFFFFF140) // (AIC) Fast Forcing Enable Register
-#define AT91C_AIC_IECR  ((AT91_REG *)   0xFFFFF120) // (AIC) Interrupt Enable Command Register
-#define AT91C_AIC_ISCR  ((AT91_REG *)   0xFFFFF12C) // (AIC) Interrupt Set Command Register
-#define AT91C_AIC_FFDR  ((AT91_REG *)   0xFFFFF144) // (AIC) Fast Forcing Disable Register
-#define AT91C_AIC_CISR  ((AT91_REG *)   0xFFFFF114) // (AIC) Core Interrupt Status Register
-#define AT91C_AIC_IDCR  ((AT91_REG *)   0xFFFFF124) // (AIC) Interrupt Disable Command Register
-#define AT91C_AIC_SPU   ((AT91_REG *)   0xFFFFF134) // (AIC) Spurious Vector Register
-// ========== Register definition for PDC_DBGU peripheral ==========
-#define AT91C_DBGU_TCR  ((AT91_REG *)   0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
-#define AT91C_DBGU_RNPR ((AT91_REG *)   0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
-#define AT91C_DBGU_TNPR ((AT91_REG *)   0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
-#define AT91C_DBGU_TPR  ((AT91_REG *)   0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
-#define AT91C_DBGU_RPR  ((AT91_REG *)   0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
-#define AT91C_DBGU_RCR  ((AT91_REG *)   0xFFFFF304) // (PDC_DBGU) Receive Counter Register
-#define AT91C_DBGU_RNCR ((AT91_REG *)   0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
-#define AT91C_DBGU_PTCR ((AT91_REG *)   0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
-#define AT91C_DBGU_PTSR ((AT91_REG *)   0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
-#define AT91C_DBGU_TNCR ((AT91_REG *)   0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
-// ========== Register definition for DBGU peripheral ==========
-#define AT91C_DBGU_EXID ((AT91_REG *)   0xFFFFF244) // (DBGU) Chip ID Extension Register
-#define AT91C_DBGU_BRGR ((AT91_REG *)   0xFFFFF220) // (DBGU) Baud Rate Generator Register
-#define AT91C_DBGU_IDR  ((AT91_REG *)   0xFFFFF20C) // (DBGU) Interrupt Disable Register
-#define AT91C_DBGU_CSR  ((AT91_REG *)   0xFFFFF214) // (DBGU) Channel Status Register
-#define AT91C_DBGU_CIDR ((AT91_REG *)   0xFFFFF240) // (DBGU) Chip ID Register
-#define AT91C_DBGU_MR   ((AT91_REG *)   0xFFFFF204) // (DBGU) Mode Register
-#define AT91C_DBGU_IMR  ((AT91_REG *)   0xFFFFF210) // (DBGU) Interrupt Mask Register
-#define AT91C_DBGU_CR   ((AT91_REG *)   0xFFFFF200) // (DBGU) Control Register
-#define AT91C_DBGU_FNTR ((AT91_REG *)   0xFFFFF248) // (DBGU) Force NTRST Register
-#define AT91C_DBGU_THR  ((AT91_REG *)   0xFFFFF21C) // (DBGU) Transmitter Holding Register
-#define AT91C_DBGU_RHR  ((AT91_REG *)   0xFFFFF218) // (DBGU) Receiver Holding Register
-#define AT91C_DBGU_IER  ((AT91_REG *)   0xFFFFF208) // (DBGU) Interrupt Enable Register
-// ========== Register definition for PIOA peripheral ==========
-#define AT91C_PIOA_ODR  ((AT91_REG *)   0xFFFFF414) // (PIOA) Output Disable Registerr
-#define AT91C_PIOA_SODR ((AT91_REG *)   0xFFFFF430) // (PIOA) Set Output Data Register
-#define AT91C_PIOA_ISR  ((AT91_REG *)   0xFFFFF44C) // (PIOA) Interrupt Status Register
-#define AT91C_PIOA_ABSR ((AT91_REG *)   0xFFFFF478) // (PIOA) AB Select Status Register
-#define AT91C_PIOA_IER  ((AT91_REG *)   0xFFFFF440) // (PIOA) Interrupt Enable Register
-#define AT91C_PIOA_PPUDR ((AT91_REG *)  0xFFFFF460) // (PIOA) Pull-up Disable Register
-#define AT91C_PIOA_IMR  ((AT91_REG *)   0xFFFFF448) // (PIOA) Interrupt Mask Register
-#define AT91C_PIOA_PER  ((AT91_REG *)   0xFFFFF400) // (PIOA) PIO Enable Register
-#define AT91C_PIOA_IFDR ((AT91_REG *)   0xFFFFF424) // (PIOA) Input Filter Disable Register
-#define AT91C_PIOA_OWDR ((AT91_REG *)   0xFFFFF4A4) // (PIOA) Output Write Disable Register
-#define AT91C_PIOA_MDSR ((AT91_REG *)   0xFFFFF458) // (PIOA) Multi-driver Status Register
-#define AT91C_PIOA_IDR  ((AT91_REG *)   0xFFFFF444) // (PIOA) Interrupt Disable Register
-#define AT91C_PIOA_ODSR ((AT91_REG *)   0xFFFFF438) // (PIOA) Output Data Status Register
-#define AT91C_PIOA_PPUSR ((AT91_REG *)  0xFFFFF468) // (PIOA) Pull-up Status Register
-#define AT91C_PIOA_OWSR ((AT91_REG *)   0xFFFFF4A8) // (PIOA) Output Write Status Register
-#define AT91C_PIOA_BSR  ((AT91_REG *)   0xFFFFF474) // (PIOA) Select B Register
-#define AT91C_PIOA_OWER ((AT91_REG *)   0xFFFFF4A0) // (PIOA) Output Write Enable Register
-#define AT91C_PIOA_IFER ((AT91_REG *)   0xFFFFF420) // (PIOA) Input Filter Enable Register
-#define AT91C_PIOA_PDSR ((AT91_REG *)   0xFFFFF43C) // (PIOA) Pin Data Status Register
-#define AT91C_PIOA_PPUER ((AT91_REG *)  0xFFFFF464) // (PIOA) Pull-up Enable Register
-#define AT91C_PIOA_OSR  ((AT91_REG *)   0xFFFFF418) // (PIOA) Output Status Register
-#define AT91C_PIOA_ASR  ((AT91_REG *)   0xFFFFF470) // (PIOA) Select A Register
-#define AT91C_PIOA_MDDR ((AT91_REG *)   0xFFFFF454) // (PIOA) Multi-driver Disable Register
-#define AT91C_PIOA_CODR ((AT91_REG *)   0xFFFFF434) // (PIOA) Clear Output Data Register
-#define AT91C_PIOA_MDER ((AT91_REG *)   0xFFFFF450) // (PIOA) Multi-driver Enable Register
-#define AT91C_PIOA_PDR  ((AT91_REG *)   0xFFFFF404) // (PIOA) PIO Disable Register
-#define AT91C_PIOA_IFSR ((AT91_REG *)   0xFFFFF428) // (PIOA) Input Filter Status Register
-#define AT91C_PIOA_OER  ((AT91_REG *)   0xFFFFF410) // (PIOA) Output Enable Register
-#define AT91C_PIOA_PSR  ((AT91_REG *)   0xFFFFF408) // (PIOA) PIO Status Register
-// ========== Register definition for PIOB peripheral ==========
-#define AT91C_PIOB_OWDR ((AT91_REG *)   0xFFFFF6A4) // (PIOB) Output Write Disable Register
-#define AT91C_PIOB_MDER ((AT91_REG *)   0xFFFFF650) // (PIOB) Multi-driver Enable Register
-#define AT91C_PIOB_PPUSR ((AT91_REG *)  0xFFFFF668) // (PIOB) Pull-up Status Register
-#define AT91C_PIOB_IMR  ((AT91_REG *)   0xFFFFF648) // (PIOB) Interrupt Mask Register
-#define AT91C_PIOB_ASR  ((AT91_REG *)   0xFFFFF670) // (PIOB) Select A Register
-#define AT91C_PIOB_PPUDR ((AT91_REG *)  0xFFFFF660) // (PIOB) Pull-up Disable Register
-#define AT91C_PIOB_PSR  ((AT91_REG *)   0xFFFFF608) // (PIOB) PIO Status Register
-#define AT91C_PIOB_IER  ((AT91_REG *)   0xFFFFF640) // (PIOB) Interrupt Enable Register
-#define AT91C_PIOB_CODR ((AT91_REG *)   0xFFFFF634) // (PIOB) Clear Output Data Register
-#define AT91C_PIOB_OWER ((AT91_REG *)   0xFFFFF6A0) // (PIOB) Output Write Enable Register
-#define AT91C_PIOB_ABSR ((AT91_REG *)   0xFFFFF678) // (PIOB) AB Select Status Register
-#define AT91C_PIOB_IFDR ((AT91_REG *)   0xFFFFF624) // (PIOB) Input Filter Disable Register
-#define AT91C_PIOB_PDSR ((AT91_REG *)   0xFFFFF63C) // (PIOB) Pin Data Status Register
-#define AT91C_PIOB_IDR  ((AT91_REG *)   0xFFFFF644) // (PIOB) Interrupt Disable Register
-#define AT91C_PIOB_OWSR ((AT91_REG *)   0xFFFFF6A8) // (PIOB) Output Write Status Register
-#define AT91C_PIOB_PDR  ((AT91_REG *)   0xFFFFF604) // (PIOB) PIO Disable Register
-#define AT91C_PIOB_ODR  ((AT91_REG *)   0xFFFFF614) // (PIOB) Output Disable Registerr
-#define AT91C_PIOB_IFSR ((AT91_REG *)   0xFFFFF628) // (PIOB) Input Filter Status Register
-#define AT91C_PIOB_PPUER ((AT91_REG *)  0xFFFFF664) // (PIOB) Pull-up Enable Register
-#define AT91C_PIOB_SODR ((AT91_REG *)   0xFFFFF630) // (PIOB) Set Output Data Register
-#define AT91C_PIOB_ISR  ((AT91_REG *)   0xFFFFF64C) // (PIOB) Interrupt Status Register
-#define AT91C_PIOB_ODSR ((AT91_REG *)   0xFFFFF638) // (PIOB) Output Data Status Register
-#define AT91C_PIOB_OSR  ((AT91_REG *)   0xFFFFF618) // (PIOB) Output Status Register
-#define AT91C_PIOB_MDSR ((AT91_REG *)   0xFFFFF658) // (PIOB) Multi-driver Status Register
-#define AT91C_PIOB_IFER ((AT91_REG *)   0xFFFFF620) // (PIOB) Input Filter Enable Register
-#define AT91C_PIOB_BSR  ((AT91_REG *)   0xFFFFF674) // (PIOB) Select B Register
-#define AT91C_PIOB_MDDR ((AT91_REG *)   0xFFFFF654) // (PIOB) Multi-driver Disable Register
-#define AT91C_PIOB_OER  ((AT91_REG *)   0xFFFFF610) // (PIOB) Output Enable Register
-#define AT91C_PIOB_PER  ((AT91_REG *)   0xFFFFF600) // (PIOB) PIO Enable Register
-// ========== Register definition for CKGR peripheral ==========
-#define AT91C_CKGR_MOR  ((AT91_REG *)   0xFFFFFC20) // (CKGR) Main Oscillator Register
-#define AT91C_CKGR_PLLR ((AT91_REG *)   0xFFFFFC2C) // (CKGR) PLL Register
-#define AT91C_CKGR_MCFR ((AT91_REG *)   0xFFFFFC24) // (CKGR) Main Clock  Frequency Register
-// ========== Register definition for PMC peripheral ==========
-#define AT91C_PMC_IDR   ((AT91_REG *)   0xFFFFFC64) // (PMC) Interrupt Disable Register
-#define AT91C_PMC_MOR   ((AT91_REG *)   0xFFFFFC20) // (PMC) Main Oscillator Register
-#define AT91C_PMC_PLLR  ((AT91_REG *)   0xFFFFFC2C) // (PMC) PLL Register
-#define AT91C_PMC_PCER  ((AT91_REG *)   0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
-#define AT91C_PMC_PCKR  ((AT91_REG *)   0xFFFFFC40) // (PMC) Programmable Clock Register
-#define AT91C_PMC_MCKR  ((AT91_REG *)   0xFFFFFC30) // (PMC) Master Clock Register
-#define AT91C_PMC_SCDR  ((AT91_REG *)   0xFFFFFC04) // (PMC) System Clock Disable Register
-#define AT91C_PMC_PCDR  ((AT91_REG *)   0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
-#define AT91C_PMC_SCSR  ((AT91_REG *)   0xFFFFFC08) // (PMC) System Clock Status Register
-#define AT91C_PMC_PCSR  ((AT91_REG *)   0xFFFFFC18) // (PMC) Peripheral Clock Status Register
-#define AT91C_PMC_MCFR  ((AT91_REG *)   0xFFFFFC24) // (PMC) Main Clock  Frequency Register
-#define AT91C_PMC_SCER  ((AT91_REG *)   0xFFFFFC00) // (PMC) System Clock Enable Register
-#define AT91C_PMC_IMR   ((AT91_REG *)   0xFFFFFC6C) // (PMC) Interrupt Mask Register
-#define AT91C_PMC_IER   ((AT91_REG *)   0xFFFFFC60) // (PMC) Interrupt Enable Register
-#define AT91C_PMC_SR    ((AT91_REG *)   0xFFFFFC68) // (PMC) Status Register
-// ========== Register definition for RSTC peripheral ==========
-#define AT91C_RSTC_RCR  ((AT91_REG *)   0xFFFFFD00) // (RSTC) Reset Control Register
-#define AT91C_RSTC_RMR  ((AT91_REG *)   0xFFFFFD08) // (RSTC) Reset Mode Register
-#define AT91C_RSTC_RSR  ((AT91_REG *)   0xFFFFFD04) // (RSTC) Reset Status Register
-// ========== Register definition for RTTC peripheral ==========
-#define AT91C_RTTC_RTSR ((AT91_REG *)   0xFFFFFD2C) // (RTTC) Real-time Status Register
-#define AT91C_RTTC_RTMR ((AT91_REG *)   0xFFFFFD20) // (RTTC) Real-time Mode Register
-#define AT91C_RTTC_RTVR ((AT91_REG *)   0xFFFFFD28) // (RTTC) Real-time Value Register
-#define AT91C_RTTC_RTAR ((AT91_REG *)   0xFFFFFD24) // (RTTC) Real-time Alarm Register
-// ========== Register definition for PITC peripheral ==========
-#define AT91C_PITC_PIVR ((AT91_REG *)   0xFFFFFD38) // (PITC) Period Interval Value Register
-#define AT91C_PITC_PISR ((AT91_REG *)   0xFFFFFD34) // (PITC) Period Interval Status Register
-#define AT91C_PITC_PIIR ((AT91_REG *)   0xFFFFFD3C) // (PITC) Period Interval Image Register
-#define AT91C_PITC_PIMR ((AT91_REG *)   0xFFFFFD30) // (PITC) Period Interval Mode Register
-// ========== Register definition for WDTC peripheral ==========
-#define AT91C_WDTC_WDCR ((AT91_REG *)   0xFFFFFD40) // (WDTC) Watchdog Control Register
-#define AT91C_WDTC_WDSR ((AT91_REG *)   0xFFFFFD48) // (WDTC) Watchdog Status Register
-#define AT91C_WDTC_WDMR ((AT91_REG *)   0xFFFFFD44) // (WDTC) Watchdog Mode Register
-// ========== Register definition for VREG peripheral ==========
-#define AT91C_VREG_MR   ((AT91_REG *)   0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
-// ========== Register definition for MC peripheral ==========
-#define AT91C_MC_ASR    ((AT91_REG *)   0xFFFFFF04) // (MC) MC Abort Status Register
-#define AT91C_MC_RCR    ((AT91_REG *)   0xFFFFFF00) // (MC) MC Remap Control Register
-#define AT91C_MC_FCR    ((AT91_REG *)   0xFFFFFF64) // (MC) MC Flash Command Register
-#define AT91C_MC_AASR   ((AT91_REG *)   0xFFFFFF08) // (MC) MC Abort Address Status Register
-#define AT91C_MC_FSR    ((AT91_REG *)   0xFFFFFF68) // (MC) MC Flash Status Register
-#define AT91C_MC_FMR    ((AT91_REG *)   0xFFFFFF60) // (MC) MC Flash Mode Register
-// ========== Register definition for PDC_SPI1 peripheral ==========
-#define AT91C_SPI1_PTCR ((AT91_REG *)   0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register
-#define AT91C_SPI1_RPR  ((AT91_REG *)   0xFFFE4100) // (PDC_SPI1) Receive Pointer Register
-#define AT91C_SPI1_TNCR ((AT91_REG *)   0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register
-#define AT91C_SPI1_TPR  ((AT91_REG *)   0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register
-#define AT91C_SPI1_TNPR ((AT91_REG *)   0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register
-#define AT91C_SPI1_TCR  ((AT91_REG *)   0xFFFE410C) // (PDC_SPI1) Transmit Counter Register
-#define AT91C_SPI1_RCR  ((AT91_REG *)   0xFFFE4104) // (PDC_SPI1) Receive Counter Register
-#define AT91C_SPI1_RNPR ((AT91_REG *)   0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register
-#define AT91C_SPI1_RNCR ((AT91_REG *)   0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register
-#define AT91C_SPI1_PTSR ((AT91_REG *)   0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register
-// ========== Register definition for SPI1 peripheral ==========
-#define AT91C_SPI1_IMR  ((AT91_REG *)   0xFFFE401C) // (SPI1) Interrupt Mask Register
-#define AT91C_SPI1_IER  ((AT91_REG *)   0xFFFE4014) // (SPI1) Interrupt Enable Register
-#define AT91C_SPI1_MR   ((AT91_REG *)   0xFFFE4004) // (SPI1) Mode Register
-#define AT91C_SPI1_RDR  ((AT91_REG *)   0xFFFE4008) // (SPI1) Receive Data Register
-#define AT91C_SPI1_IDR  ((AT91_REG *)   0xFFFE4018) // (SPI1) Interrupt Disable Register
-#define AT91C_SPI1_SR   ((AT91_REG *)   0xFFFE4010) // (SPI1) Status Register
-#define AT91C_SPI1_TDR  ((AT91_REG *)   0xFFFE400C) // (SPI1) Transmit Data Register
-#define AT91C_SPI1_CR   ((AT91_REG *)   0xFFFE4000) // (SPI1) Control Register
-#define AT91C_SPI1_CSR  ((AT91_REG *)   0xFFFE4030) // (SPI1) Chip Select Register
-// ========== Register definition for PDC_SPI0 peripheral ==========
-#define AT91C_SPI0_PTCR ((AT91_REG *)   0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register
-#define AT91C_SPI0_TPR  ((AT91_REG *)   0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register
-#define AT91C_SPI0_TCR  ((AT91_REG *)   0xFFFE010C) // (PDC_SPI0) Transmit Counter Register
-#define AT91C_SPI0_RCR  ((AT91_REG *)   0xFFFE0104) // (PDC_SPI0) Receive Counter Register
-#define AT91C_SPI0_PTSR ((AT91_REG *)   0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register
-#define AT91C_SPI0_RNPR ((AT91_REG *)   0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register
-#define AT91C_SPI0_RPR  ((AT91_REG *)   0xFFFE0100) // (PDC_SPI0) Receive Pointer Register
-#define AT91C_SPI0_TNCR ((AT91_REG *)   0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register
-#define AT91C_SPI0_RNCR ((AT91_REG *)   0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register
-#define AT91C_SPI0_TNPR ((AT91_REG *)   0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register
-// ========== Register definition for SPI0 peripheral ==========
-#define AT91C_SPI0_IER  ((AT91_REG *)   0xFFFE0014) // (SPI0) Interrupt Enable Register
-#define AT91C_SPI0_SR   ((AT91_REG *)   0xFFFE0010) // (SPI0) Status Register
-#define AT91C_SPI0_IDR  ((AT91_REG *)   0xFFFE0018) // (SPI0) Interrupt Disable Register
-#define AT91C_SPI0_CR   ((AT91_REG *)   0xFFFE0000) // (SPI0) Control Register
-#define AT91C_SPI0_MR   ((AT91_REG *)   0xFFFE0004) // (SPI0) Mode Register
-#define AT91C_SPI0_IMR  ((AT91_REG *)   0xFFFE001C) // (SPI0) Interrupt Mask Register
-#define AT91C_SPI0_TDR  ((AT91_REG *)   0xFFFE000C) // (SPI0) Transmit Data Register
-#define AT91C_SPI0_RDR  ((AT91_REG *)   0xFFFE0008) // (SPI0) Receive Data Register
-#define AT91C_SPI0_CSR  ((AT91_REG *)   0xFFFE0030) // (SPI0) Chip Select Register
-// ========== Register definition for PDC_US1 peripheral ==========
-#define AT91C_US1_RNCR  ((AT91_REG *)   0xFFFC4114) // (PDC_US1) Receive Next Counter Register
-#define AT91C_US1_PTCR  ((AT91_REG *)   0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
-#define AT91C_US1_TCR   ((AT91_REG *)   0xFFFC410C) // (PDC_US1) Transmit Counter Register
-#define AT91C_US1_PTSR  ((AT91_REG *)   0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
-#define AT91C_US1_TNPR  ((AT91_REG *)   0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
-#define AT91C_US1_RCR   ((AT91_REG *)   0xFFFC4104) // (PDC_US1) Receive Counter Register
-#define AT91C_US1_RNPR  ((AT91_REG *)   0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
-#define AT91C_US1_RPR   ((AT91_REG *)   0xFFFC4100) // (PDC_US1) Receive Pointer Register
-#define AT91C_US1_TNCR  ((AT91_REG *)   0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
-#define AT91C_US1_TPR   ((AT91_REG *)   0xFFFC4108) // (PDC_US1) Transmit Pointer Register
-// ========== Register definition for US1 peripheral ==========
-#define AT91C_US1_IF    ((AT91_REG *)   0xFFFC404C) // (US1) IRDA_FILTER Register
-#define AT91C_US1_NER   ((AT91_REG *)   0xFFFC4044) // (US1) Nb Errors Register
-#define AT91C_US1_RTOR  ((AT91_REG *)   0xFFFC4024) // (US1) Receiver Time-out Register
-#define AT91C_US1_CSR   ((AT91_REG *)   0xFFFC4014) // (US1) Channel Status Register
-#define AT91C_US1_IDR   ((AT91_REG *)   0xFFFC400C) // (US1) Interrupt Disable Register
-#define AT91C_US1_IER   ((AT91_REG *)   0xFFFC4008) // (US1) Interrupt Enable Register
-#define AT91C_US1_THR   ((AT91_REG *)   0xFFFC401C) // (US1) Transmitter Holding Register
-#define AT91C_US1_TTGR  ((AT91_REG *)   0xFFFC4028) // (US1) Transmitter Time-guard Register
-#define AT91C_US1_RHR   ((AT91_REG *)   0xFFFC4018) // (US1) Receiver Holding Register
-#define AT91C_US1_BRGR  ((AT91_REG *)   0xFFFC4020) // (US1) Baud Rate Generator Register
-#define AT91C_US1_IMR   ((AT91_REG *)   0xFFFC4010) // (US1) Interrupt Mask Register
-#define AT91C_US1_FIDI  ((AT91_REG *)   0xFFFC4040) // (US1) FI_DI_Ratio Register
-#define AT91C_US1_CR    ((AT91_REG *)   0xFFFC4000) // (US1) Control Register
-#define AT91C_US1_MR    ((AT91_REG *)   0xFFFC4004) // (US1) Mode Register
-// ========== Register definition for PDC_US0 peripheral ==========
-#define AT91C_US0_TNPR  ((AT91_REG *)   0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
-#define AT91C_US0_RNPR  ((AT91_REG *)   0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
-#define AT91C_US0_TCR   ((AT91_REG *)   0xFFFC010C) // (PDC_US0) Transmit Counter Register
-#define AT91C_US0_PTCR  ((AT91_REG *)   0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
-#define AT91C_US0_PTSR  ((AT91_REG *)   0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
-#define AT91C_US0_TNCR  ((AT91_REG *)   0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
-#define AT91C_US0_TPR   ((AT91_REG *)   0xFFFC0108) // (PDC_US0) Transmit Pointer Register
-#define AT91C_US0_RCR   ((AT91_REG *)   0xFFFC0104) // (PDC_US0) Receive Counter Register
-#define AT91C_US0_RPR   ((AT91_REG *)   0xFFFC0100) // (PDC_US0) Receive Pointer Register
-#define AT91C_US0_RNCR  ((AT91_REG *)   0xFFFC0114) // (PDC_US0) Receive Next Counter Register
-// ========== Register definition for US0 peripheral ==========
-#define AT91C_US0_BRGR  ((AT91_REG *)   0xFFFC0020) // (US0) Baud Rate Generator Register
-#define AT91C_US0_NER   ((AT91_REG *)   0xFFFC0044) // (US0) Nb Errors Register
-#define AT91C_US0_CR    ((AT91_REG *)   0xFFFC0000) // (US0) Control Register
-#define AT91C_US0_IMR   ((AT91_REG *)   0xFFFC0010) // (US0) Interrupt Mask Register
-#define AT91C_US0_FIDI  ((AT91_REG *)   0xFFFC0040) // (US0) FI_DI_Ratio Register
-#define AT91C_US0_TTGR  ((AT91_REG *)   0xFFFC0028) // (US0) Transmitter Time-guard Register
-#define AT91C_US0_MR    ((AT91_REG *)   0xFFFC0004) // (US0) Mode Register
-#define AT91C_US0_RTOR  ((AT91_REG *)   0xFFFC0024) // (US0) Receiver Time-out Register
-#define AT91C_US0_CSR   ((AT91_REG *)   0xFFFC0014) // (US0) Channel Status Register
-#define AT91C_US0_RHR   ((AT91_REG *)   0xFFFC0018) // (US0) Receiver Holding Register
-#define AT91C_US0_IDR   ((AT91_REG *)   0xFFFC000C) // (US0) Interrupt Disable Register
-#define AT91C_US0_THR   ((AT91_REG *)   0xFFFC001C) // (US0) Transmitter Holding Register
-#define AT91C_US0_IF    ((AT91_REG *)   0xFFFC004C) // (US0) IRDA_FILTER Register
-#define AT91C_US0_IER   ((AT91_REG *)   0xFFFC0008) // (US0) Interrupt Enable Register
-// ========== Register definition for PDC_SSC peripheral ==========
-#define AT91C_SSC_TNCR  ((AT91_REG *)   0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
-#define AT91C_SSC_RPR   ((AT91_REG *)   0xFFFD4100) // (PDC_SSC) Receive Pointer Register
-#define AT91C_SSC_RNCR  ((AT91_REG *)   0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
-#define AT91C_SSC_TPR   ((AT91_REG *)   0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
-#define AT91C_SSC_PTCR  ((AT91_REG *)   0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
-#define AT91C_SSC_TCR   ((AT91_REG *)   0xFFFD410C) // (PDC_SSC) Transmit Counter Register
-#define AT91C_SSC_RCR   ((AT91_REG *)   0xFFFD4104) // (PDC_SSC) Receive Counter Register
-#define AT91C_SSC_RNPR  ((AT91_REG *)   0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
-#define AT91C_SSC_TNPR  ((AT91_REG *)   0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
-#define AT91C_SSC_PTSR  ((AT91_REG *)   0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
-// ========== Register definition for SSC peripheral ==========
-#define AT91C_SSC_RHR   ((AT91_REG *)   0xFFFD4020) // (SSC) Receive Holding Register
-#define AT91C_SSC_RSHR  ((AT91_REG *)   0xFFFD4030) // (SSC) Receive Sync Holding Register
-#define AT91C_SSC_TFMR  ((AT91_REG *)   0xFFFD401C) // (SSC) Transmit Frame Mode Register
-#define AT91C_SSC_IDR   ((AT91_REG *)   0xFFFD4048) // (SSC) Interrupt Disable Register
-#define AT91C_SSC_THR   ((AT91_REG *)   0xFFFD4024) // (SSC) Transmit Holding Register
-#define AT91C_SSC_RCMR  ((AT91_REG *)   0xFFFD4010) // (SSC) Receive Clock ModeRegister
-#define AT91C_SSC_IER   ((AT91_REG *)   0xFFFD4044) // (SSC) Interrupt Enable Register
-#define AT91C_SSC_TSHR  ((AT91_REG *)   0xFFFD4034) // (SSC) Transmit Sync Holding Register
-#define AT91C_SSC_SR    ((AT91_REG *)   0xFFFD4040) // (SSC) Status Register
-#define AT91C_SSC_CMR   ((AT91_REG *)   0xFFFD4004) // (SSC) Clock Mode Register
-#define AT91C_SSC_TCMR  ((AT91_REG *)   0xFFFD4018) // (SSC) Transmit Clock Mode Register
-#define AT91C_SSC_CR    ((AT91_REG *)   0xFFFD4000) // (SSC) Control Register
-#define AT91C_SSC_IMR   ((AT91_REG *)   0xFFFD404C) // (SSC) Interrupt Mask Register
-#define AT91C_SSC_RFMR  ((AT91_REG *)   0xFFFD4014) // (SSC) Receive Frame Mode Register
-// ========== Register definition for TWI peripheral ==========
-#define AT91C_TWI_IER   ((AT91_REG *)   0xFFFB8024) // (TWI) Interrupt Enable Register
-#define AT91C_TWI_CR    ((AT91_REG *)   0xFFFB8000) // (TWI) Control Register
-#define AT91C_TWI_SR    ((AT91_REG *)   0xFFFB8020) // (TWI) Status Register
-#define AT91C_TWI_IMR   ((AT91_REG *)   0xFFFB802C) // (TWI) Interrupt Mask Register
-#define AT91C_TWI_THR   ((AT91_REG *)   0xFFFB8034) // (TWI) Transmit Holding Register
-#define AT91C_TWI_IDR   ((AT91_REG *)   0xFFFB8028) // (TWI) Interrupt Disable Register
-#define AT91C_TWI_IADR  ((AT91_REG *)   0xFFFB800C) // (TWI) Internal Address Register
-#define AT91C_TWI_MMR   ((AT91_REG *)   0xFFFB8004) // (TWI) Master Mode Register
-#define AT91C_TWI_CWGR  ((AT91_REG *)   0xFFFB8010) // (TWI) Clock Waveform Generator Register
-#define AT91C_TWI_RHR   ((AT91_REG *)   0xFFFB8030) // (TWI) Receive Holding Register
-// ========== Register definition for PWMC_CH3 peripheral ==========
-#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *)  0xFFFCC270) // (PWMC_CH3) Channel Update Register
-#define AT91C_PWMC_CH3_Reserved ((AT91_REG *)   0xFFFCC274) // (PWMC_CH3) Reserved
-#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *)  0xFFFCC268) // (PWMC_CH3) Channel Period Register
-#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *)  0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
-#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *)  0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
-#define AT91C_PWMC_CH3_CMR ((AT91_REG *)    0xFFFCC260) // (PWMC_CH3) Channel Mode Register
-// ========== Register definition for PWMC_CH2 peripheral ==========
-#define AT91C_PWMC_CH2_Reserved ((AT91_REG *)   0xFFFCC254) // (PWMC_CH2) Reserved
-#define AT91C_PWMC_CH2_CMR ((AT91_REG *)    0xFFFCC240) // (PWMC_CH2) Channel Mode Register
-#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *)  0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
-#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *)  0xFFFCC248) // (PWMC_CH2) Channel Period Register
-#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *)  0xFFFCC250) // (PWMC_CH2) Channel Update Register
-#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *)  0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
-// ========== Register definition for PWMC_CH1 peripheral ==========
-#define AT91C_PWMC_CH1_Reserved ((AT91_REG *)   0xFFFCC234) // (PWMC_CH1) Reserved
-#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *)  0xFFFCC230) // (PWMC_CH1) Channel Update Register
-#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *)  0xFFFCC228) // (PWMC_CH1) Channel Period Register
-#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *)  0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
-#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *)  0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
-#define AT91C_PWMC_CH1_CMR ((AT91_REG *)    0xFFFCC220) // (PWMC_CH1) Channel Mode Register
-// ========== Register definition for PWMC_CH0 peripheral ==========
-#define AT91C_PWMC_CH0_Reserved ((AT91_REG *)   0xFFFCC214) // (PWMC_CH0) Reserved
-#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *)  0xFFFCC208) // (PWMC_CH0) Channel Period Register
-#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *)  0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
-#define AT91C_PWMC_CH0_CMR ((AT91_REG *)    0xFFFCC200) // (PWMC_CH0) Channel Mode Register
-#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *)  0xFFFCC210) // (PWMC_CH0) Channel Update Register
-#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *)  0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
-// ========== Register definition for PWMC peripheral ==========
-#define AT91C_PWMC_IDR  ((AT91_REG *)   0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
-#define AT91C_PWMC_DIS  ((AT91_REG *)   0xFFFCC008) // (PWMC) PWMC Disable Register
-#define AT91C_PWMC_IER  ((AT91_REG *)   0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
-#define AT91C_PWMC_VR   ((AT91_REG *)   0xFFFCC0FC) // (PWMC) PWMC Version Register
-#define AT91C_PWMC_ISR  ((AT91_REG *)   0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
-#define AT91C_PWMC_SR   ((AT91_REG *)   0xFFFCC00C) // (PWMC) PWMC Status Register
-#define AT91C_PWMC_IMR  ((AT91_REG *)   0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
-#define AT91C_PWMC_MR   ((AT91_REG *)   0xFFFCC000) // (PWMC) PWMC Mode Register
-#define AT91C_PWMC_ENA  ((AT91_REG *)   0xFFFCC004) // (PWMC) PWMC Enable Register
-// ========== Register definition for UDP peripheral ==========
-#define AT91C_UDP_IMR   ((AT91_REG *)   0xFFFB0018) // (UDP) Interrupt Mask Register
-#define AT91C_UDP_FADDR ((AT91_REG *)   0xFFFB0008) // (UDP) Function Address Register
-#define AT91C_UDP_NUM   ((AT91_REG *)   0xFFFB0000) // (UDP) Frame Number Register
-#define AT91C_UDP_FDR   ((AT91_REG *)   0xFFFB0050) // (UDP) Endpoint FIFO Data Register
-#define AT91C_UDP_ISR   ((AT91_REG *)   0xFFFB001C) // (UDP) Interrupt Status Register
-#define AT91C_UDP_CSR   ((AT91_REG *)   0xFFFB0030) // (UDP) Endpoint Control and Status Register
-#define AT91C_UDP_IDR   ((AT91_REG *)   0xFFFB0014) // (UDP) Interrupt Disable Register
-#define AT91C_UDP_ICR   ((AT91_REG *)   0xFFFB0020) // (UDP) Interrupt Clear Register
-#define AT91C_UDP_RSTEP ((AT91_REG *)   0xFFFB0028) // (UDP) Reset Endpoint Register
-#define AT91C_UDP_TXVC  ((AT91_REG *)   0xFFFB0074) // (UDP) Transceiver Control Register
-#define AT91C_UDP_GLBSTATE ((AT91_REG *)    0xFFFB0004) // (UDP) Global State Register
-#define AT91C_UDP_IER   ((AT91_REG *)   0xFFFB0010) // (UDP) Interrupt Enable Register
-// ========== Register definition for TC0 peripheral ==========
-#define AT91C_TC0_SR    ((AT91_REG *)   0xFFFA0020) // (TC0) Status Register
-#define AT91C_TC0_RC    ((AT91_REG *)   0xFFFA001C) // (TC0) Register C
-#define AT91C_TC0_RB    ((AT91_REG *)   0xFFFA0018) // (TC0) Register B
-#define AT91C_TC0_CCR   ((AT91_REG *)   0xFFFA0000) // (TC0) Channel Control Register
-#define AT91C_TC0_CMR   ((AT91_REG *)   0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC0_IER   ((AT91_REG *)   0xFFFA0024) // (TC0) Interrupt Enable Register
-#define AT91C_TC0_RA    ((AT91_REG *)   0xFFFA0014) // (TC0) Register A
-#define AT91C_TC0_IDR   ((AT91_REG *)   0xFFFA0028) // (TC0) Interrupt Disable Register
-#define AT91C_TC0_CV    ((AT91_REG *)   0xFFFA0010) // (TC0) Counter Value
-#define AT91C_TC0_IMR   ((AT91_REG *)   0xFFFA002C) // (TC0) Interrupt Mask Register
-// ========== Register definition for TC1 peripheral ==========
-#define AT91C_TC1_RB    ((AT91_REG *)   0xFFFA0058) // (TC1) Register B
-#define AT91C_TC1_CCR   ((AT91_REG *)   0xFFFA0040) // (TC1) Channel Control Register
-#define AT91C_TC1_IER   ((AT91_REG *)   0xFFFA0064) // (TC1) Interrupt Enable Register
-#define AT91C_TC1_IDR   ((AT91_REG *)   0xFFFA0068) // (TC1) Interrupt Disable Register
-#define AT91C_TC1_SR    ((AT91_REG *)   0xFFFA0060) // (TC1) Status Register
-#define AT91C_TC1_CMR   ((AT91_REG *)   0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC1_RA    ((AT91_REG *)   0xFFFA0054) // (TC1) Register A
-#define AT91C_TC1_RC    ((AT91_REG *)   0xFFFA005C) // (TC1) Register C
-#define AT91C_TC1_IMR   ((AT91_REG *)   0xFFFA006C) // (TC1) Interrupt Mask Register
-#define AT91C_TC1_CV    ((AT91_REG *)   0xFFFA0050) // (TC1) Counter Value
-// ========== Register definition for TC2 peripheral ==========
-#define AT91C_TC2_CMR   ((AT91_REG *)   0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC2_CCR   ((AT91_REG *)   0xFFFA0080) // (TC2) Channel Control Register
-#define AT91C_TC2_CV    ((AT91_REG *)   0xFFFA0090) // (TC2) Counter Value
-#define AT91C_TC2_RA    ((AT91_REG *)   0xFFFA0094) // (TC2) Register A
-#define AT91C_TC2_RB    ((AT91_REG *)   0xFFFA0098) // (TC2) Register B
-#define AT91C_TC2_IDR   ((AT91_REG *)   0xFFFA00A8) // (TC2) Interrupt Disable Register
-#define AT91C_TC2_IMR   ((AT91_REG *)   0xFFFA00AC) // (TC2) Interrupt Mask Register
-#define AT91C_TC2_RC    ((AT91_REG *)   0xFFFA009C) // (TC2) Register C
-#define AT91C_TC2_IER   ((AT91_REG *)   0xFFFA00A4) // (TC2) Interrupt Enable Register
-#define AT91C_TC2_SR    ((AT91_REG *)   0xFFFA00A0) // (TC2) Status Register
-// ========== Register definition for TCB peripheral ==========
-#define AT91C_TCB_BMR   ((AT91_REG *)   0xFFFA00C4) // (TCB) TC Block Mode Register
-#define AT91C_TCB_BCR   ((AT91_REG *)   0xFFFA00C0) // (TCB) TC Block Control Register
-// ========== Register definition for CAN_MB0 peripheral ==========
-#define AT91C_CAN_MB0_MDL ((AT91_REG *)     0xFFFD0214) // (CAN_MB0) MailBox Data Low Register
-#define AT91C_CAN_MB0_MAM ((AT91_REG *)     0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB0_MCR ((AT91_REG *)     0xFFFD021C) // (CAN_MB0) MailBox Control Register
-#define AT91C_CAN_MB0_MID ((AT91_REG *)     0xFFFD0208) // (CAN_MB0) MailBox ID Register
-#define AT91C_CAN_MB0_MSR ((AT91_REG *)     0xFFFD0210) // (CAN_MB0) MailBox Status Register
-#define AT91C_CAN_MB0_MFID ((AT91_REG *)    0xFFFD020C) // (CAN_MB0) MailBox Family ID Register
-#define AT91C_CAN_MB0_MDH ((AT91_REG *)     0xFFFD0218) // (CAN_MB0) MailBox Data High Register
-#define AT91C_CAN_MB0_MMR ((AT91_REG *)     0xFFFD0200) // (CAN_MB0) MailBox Mode Register
-// ========== Register definition for CAN_MB1 peripheral ==========
-#define AT91C_CAN_MB1_MDL ((AT91_REG *)     0xFFFD0234) // (CAN_MB1) MailBox Data Low Register
-#define AT91C_CAN_MB1_MID ((AT91_REG *)     0xFFFD0228) // (CAN_MB1) MailBox ID Register
-#define AT91C_CAN_MB1_MMR ((AT91_REG *)     0xFFFD0220) // (CAN_MB1) MailBox Mode Register
-#define AT91C_CAN_MB1_MSR ((AT91_REG *)     0xFFFD0230) // (CAN_MB1) MailBox Status Register
-#define AT91C_CAN_MB1_MAM ((AT91_REG *)     0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB1_MDH ((AT91_REG *)     0xFFFD0238) // (CAN_MB1) MailBox Data High Register
-#define AT91C_CAN_MB1_MCR ((AT91_REG *)     0xFFFD023C) // (CAN_MB1) MailBox Control Register
-#define AT91C_CAN_MB1_MFID ((AT91_REG *)    0xFFFD022C) // (CAN_MB1) MailBox Family ID Register
-// ========== Register definition for CAN_MB2 peripheral ==========
-#define AT91C_CAN_MB2_MCR ((AT91_REG *)     0xFFFD025C) // (CAN_MB2) MailBox Control Register
-#define AT91C_CAN_MB2_MDH ((AT91_REG *)     0xFFFD0258) // (CAN_MB2) MailBox Data High Register
-#define AT91C_CAN_MB2_MID ((AT91_REG *)     0xFFFD0248) // (CAN_MB2) MailBox ID Register
-#define AT91C_CAN_MB2_MDL ((AT91_REG *)     0xFFFD0254) // (CAN_MB2) MailBox Data Low Register
-#define AT91C_CAN_MB2_MMR ((AT91_REG *)     0xFFFD0240) // (CAN_MB2) MailBox Mode Register
-#define AT91C_CAN_MB2_MAM ((AT91_REG *)     0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB2_MFID ((AT91_REG *)    0xFFFD024C) // (CAN_MB2) MailBox Family ID Register
-#define AT91C_CAN_MB2_MSR ((AT91_REG *)     0xFFFD0250) // (CAN_MB2) MailBox Status Register
-// ========== Register definition for CAN_MB3 peripheral ==========
-#define AT91C_CAN_MB3_MFID ((AT91_REG *)    0xFFFD026C) // (CAN_MB3) MailBox Family ID Register
-#define AT91C_CAN_MB3_MAM ((AT91_REG *)     0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB3_MID ((AT91_REG *)     0xFFFD0268) // (CAN_MB3) MailBox ID Register
-#define AT91C_CAN_MB3_MCR ((AT91_REG *)     0xFFFD027C) // (CAN_MB3) MailBox Control Register
-#define AT91C_CAN_MB3_MMR ((AT91_REG *)     0xFFFD0260) // (CAN_MB3) MailBox Mode Register
-#define AT91C_CAN_MB3_MSR ((AT91_REG *)     0xFFFD0270) // (CAN_MB3) MailBox Status Register
-#define AT91C_CAN_MB3_MDL ((AT91_REG *)     0xFFFD0274) // (CAN_MB3) MailBox Data Low Register
-#define AT91C_CAN_MB3_MDH ((AT91_REG *)     0xFFFD0278) // (CAN_MB3) MailBox Data High Register
-// ========== Register definition for CAN_MB4 peripheral ==========
-#define AT91C_CAN_MB4_MID ((AT91_REG *)     0xFFFD0288) // (CAN_MB4) MailBox ID Register
-#define AT91C_CAN_MB4_MMR ((AT91_REG *)     0xFFFD0280) // (CAN_MB4) MailBox Mode Register
-#define AT91C_CAN_MB4_MDH ((AT91_REG *)     0xFFFD0298) // (CAN_MB4) MailBox Data High Register
-#define AT91C_CAN_MB4_MFID ((AT91_REG *)    0xFFFD028C) // (CAN_MB4) MailBox Family ID Register
-#define AT91C_CAN_MB4_MSR ((AT91_REG *)     0xFFFD0290) // (CAN_MB4) MailBox Status Register
-#define AT91C_CAN_MB4_MCR ((AT91_REG *)     0xFFFD029C) // (CAN_MB4) MailBox Control Register
-#define AT91C_CAN_MB4_MDL ((AT91_REG *)     0xFFFD0294) // (CAN_MB4) MailBox Data Low Register
-#define AT91C_CAN_MB4_MAM ((AT91_REG *)     0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register
-// ========== Register definition for CAN_MB5 peripheral ==========
-#define AT91C_CAN_MB5_MSR ((AT91_REG *)     0xFFFD02B0) // (CAN_MB5) MailBox Status Register
-#define AT91C_CAN_MB5_MCR ((AT91_REG *)     0xFFFD02BC) // (CAN_MB5) MailBox Control Register
-#define AT91C_CAN_MB5_MFID ((AT91_REG *)    0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register
-#define AT91C_CAN_MB5_MDH ((AT91_REG *)     0xFFFD02B8) // (CAN_MB5) MailBox Data High Register
-#define AT91C_CAN_MB5_MID ((AT91_REG *)     0xFFFD02A8) // (CAN_MB5) MailBox ID Register
-#define AT91C_CAN_MB5_MMR ((AT91_REG *)     0xFFFD02A0) // (CAN_MB5) MailBox Mode Register
-#define AT91C_CAN_MB5_MDL ((AT91_REG *)     0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register
-#define AT91C_CAN_MB5_MAM ((AT91_REG *)     0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register
-// ========== Register definition for CAN_MB6 peripheral ==========
-#define AT91C_CAN_MB6_MFID ((AT91_REG *)    0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register
-#define AT91C_CAN_MB6_MID ((AT91_REG *)     0xFFFD02C8) // (CAN_MB6) MailBox ID Register
-#define AT91C_CAN_MB6_MAM ((AT91_REG *)     0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB6_MSR ((AT91_REG *)     0xFFFD02D0) // (CAN_MB6) MailBox Status Register
-#define AT91C_CAN_MB6_MDL ((AT91_REG *)     0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register
-#define AT91C_CAN_MB6_MCR ((AT91_REG *)     0xFFFD02DC) // (CAN_MB6) MailBox Control Register
-#define AT91C_CAN_MB6_MDH ((AT91_REG *)     0xFFFD02D8) // (CAN_MB6) MailBox Data High Register
-#define AT91C_CAN_MB6_MMR ((AT91_REG *)     0xFFFD02C0) // (CAN_MB6) MailBox Mode Register
-// ========== Register definition for CAN_MB7 peripheral ==========
-#define AT91C_CAN_MB7_MCR ((AT91_REG *)     0xFFFD02FC) // (CAN_MB7) MailBox Control Register
-#define AT91C_CAN_MB7_MDH ((AT91_REG *)     0xFFFD02F8) // (CAN_MB7) MailBox Data High Register
-#define AT91C_CAN_MB7_MFID ((AT91_REG *)    0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register
-#define AT91C_CAN_MB7_MDL ((AT91_REG *)     0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register
-#define AT91C_CAN_MB7_MID ((AT91_REG *)     0xFFFD02E8) // (CAN_MB7) MailBox ID Register
-#define AT91C_CAN_MB7_MMR ((AT91_REG *)     0xFFFD02E0) // (CAN_MB7) MailBox Mode Register
-#define AT91C_CAN_MB7_MAM ((AT91_REG *)     0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB7_MSR ((AT91_REG *)     0xFFFD02F0) // (CAN_MB7) MailBox Status Register
-// ========== Register definition for CAN peripheral ==========
-#define AT91C_CAN_TCR   ((AT91_REG *)   0xFFFD0024) // (CAN) Transfer Command Register
-#define AT91C_CAN_IMR   ((AT91_REG *)   0xFFFD000C) // (CAN) Interrupt Mask Register
-#define AT91C_CAN_IER   ((AT91_REG *)   0xFFFD0004) // (CAN) Interrupt Enable Register
-#define AT91C_CAN_ECR   ((AT91_REG *)   0xFFFD0020) // (CAN) Error Counter Register
-#define AT91C_CAN_TIMESTP ((AT91_REG *)     0xFFFD001C) // (CAN) Time Stamp Register
-#define AT91C_CAN_MR    ((AT91_REG *)   0xFFFD0000) // (CAN) Mode Register
-#define AT91C_CAN_IDR   ((AT91_REG *)   0xFFFD0008) // (CAN) Interrupt Disable Register
-#define AT91C_CAN_ACR   ((AT91_REG *)   0xFFFD0028) // (CAN) Abort Command Register
-#define AT91C_CAN_TIM   ((AT91_REG *)   0xFFFD0018) // (CAN) Timer Register
-#define AT91C_CAN_SR    ((AT91_REG *)   0xFFFD0010) // (CAN) Status Register
-#define AT91C_CAN_BR    ((AT91_REG *)   0xFFFD0014) // (CAN) Baudrate Register
-#define AT91C_CAN_VR    ((AT91_REG *)   0xFFFD00FC) // (CAN) Version Register
-// ========== Register definition for EMAC peripheral ==========
-#define AT91C_EMAC_ISR  ((AT91_REG *)   0xFFFDC024) // (EMAC) Interrupt Status Register
-#define AT91C_EMAC_SA4H ((AT91_REG *)   0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes
-#define AT91C_EMAC_SA1L ((AT91_REG *)   0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes
-#define AT91C_EMAC_ELE  ((AT91_REG *)   0xFFFDC078) // (EMAC) Excessive Length Errors Register
-#define AT91C_EMAC_LCOL ((AT91_REG *)   0xFFFDC05C) // (EMAC) Late Collision Register
-#define AT91C_EMAC_RLE  ((AT91_REG *)   0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register
-#define AT91C_EMAC_WOL  ((AT91_REG *)   0xFFFDC0C4) // (EMAC) Wake On LAN Register
-#define AT91C_EMAC_DTF  ((AT91_REG *)   0xFFFDC058) // (EMAC) Deferred Transmission Frame Register
-#define AT91C_EMAC_TUND ((AT91_REG *)   0xFFFDC064) // (EMAC) Transmit Underrun Error Register
-#define AT91C_EMAC_NCR  ((AT91_REG *)   0xFFFDC000) // (EMAC) Network Control Register
-#define AT91C_EMAC_SA4L ((AT91_REG *)   0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes
-#define AT91C_EMAC_RSR  ((AT91_REG *)   0xFFFDC020) // (EMAC) Receive Status Register
-#define AT91C_EMAC_SA3L ((AT91_REG *)   0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes
-#define AT91C_EMAC_TSR  ((AT91_REG *)   0xFFFDC014) // (EMAC) Transmit Status Register
-#define AT91C_EMAC_IDR  ((AT91_REG *)   0xFFFDC02C) // (EMAC) Interrupt Disable Register
-#define AT91C_EMAC_RSE  ((AT91_REG *)   0xFFFDC074) // (EMAC) Receive Symbol Errors Register
-#define AT91C_EMAC_ECOL ((AT91_REG *)   0xFFFDC060) // (EMAC) Excessive Collision Register
-#define AT91C_EMAC_TID  ((AT91_REG *)   0xFFFDC0B8) // (EMAC) Type ID Checking Register
-#define AT91C_EMAC_HRB  ((AT91_REG *)   0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]
-#define AT91C_EMAC_TBQP ((AT91_REG *)   0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer
-#define AT91C_EMAC_USRIO ((AT91_REG *)  0xFFFDC0C0) // (EMAC) USER Input/Output Register
-#define AT91C_EMAC_PTR  ((AT91_REG *)   0xFFFDC038) // (EMAC) Pause Time Register
-#define AT91C_EMAC_SA2H ((AT91_REG *)   0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes
-#define AT91C_EMAC_ROV  ((AT91_REG *)   0xFFFDC070) // (EMAC) Receive Overrun Errors Register
-#define AT91C_EMAC_ALE  ((AT91_REG *)   0xFFFDC054) // (EMAC) Alignment Error Register
-#define AT91C_EMAC_RJA  ((AT91_REG *)   0xFFFDC07C) // (EMAC) Receive Jabbers Register
-#define AT91C_EMAC_RBQP ((AT91_REG *)   0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer
-#define AT91C_EMAC_TPF  ((AT91_REG *)   0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register
-#define AT91C_EMAC_NCFGR ((AT91_REG *)  0xFFFDC004) // (EMAC) Network Configuration Register
-#define AT91C_EMAC_HRT  ((AT91_REG *)   0xFFFDC094) // (EMAC) Hash Address Top[63:32]
-#define AT91C_EMAC_USF  ((AT91_REG *)   0xFFFDC080) // (EMAC) Undersize Frames Register
-#define AT91C_EMAC_FCSE ((AT91_REG *)   0xFFFDC050) // (EMAC) Frame Check Sequence Error Register
-#define AT91C_EMAC_TPQ  ((AT91_REG *)   0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register
-#define AT91C_EMAC_MAN  ((AT91_REG *)   0xFFFDC034) // (EMAC) PHY Maintenance Register
-#define AT91C_EMAC_FTO  ((AT91_REG *)   0xFFFDC040) // (EMAC) Frames Transmitted OK Register
-#define AT91C_EMAC_REV  ((AT91_REG *)   0xFFFDC0FC) // (EMAC) Revision Register
-#define AT91C_EMAC_IMR  ((AT91_REG *)   0xFFFDC030) // (EMAC) Interrupt Mask Register
-#define AT91C_EMAC_SCF  ((AT91_REG *)   0xFFFDC044) // (EMAC) Single Collision Frame Register
-#define AT91C_EMAC_PFR  ((AT91_REG *)   0xFFFDC03C) // (EMAC) Pause Frames received Register
-#define AT91C_EMAC_MCF  ((AT91_REG *)   0xFFFDC048) // (EMAC) Multiple Collision Frame Register
-#define AT91C_EMAC_NSR  ((AT91_REG *)   0xFFFDC008) // (EMAC) Network Status Register
-#define AT91C_EMAC_SA2L ((AT91_REG *)   0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes
-#define AT91C_EMAC_FRO  ((AT91_REG *)   0xFFFDC04C) // (EMAC) Frames Received OK Register
-#define AT91C_EMAC_IER  ((AT91_REG *)   0xFFFDC028) // (EMAC) Interrupt Enable Register
-#define AT91C_EMAC_SA1H ((AT91_REG *)   0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes
-#define AT91C_EMAC_CSE  ((AT91_REG *)   0xFFFDC068) // (EMAC) Carrier Sense Error Register
-#define AT91C_EMAC_SA3H ((AT91_REG *)   0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes
-#define AT91C_EMAC_RRE  ((AT91_REG *)   0xFFFDC06C) // (EMAC) Receive Ressource Error Register
-#define AT91C_EMAC_STE  ((AT91_REG *)   0xFFFDC084) // (EMAC) SQE Test Error Register
-// ========== Register definition for PDC_ADC peripheral ==========
-#define AT91C_ADC_PTSR  ((AT91_REG *)   0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
-#define AT91C_ADC_PTCR  ((AT91_REG *)   0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
-#define AT91C_ADC_TNPR  ((AT91_REG *)   0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
-#define AT91C_ADC_TNCR  ((AT91_REG *)   0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
-#define AT91C_ADC_RNPR  ((AT91_REG *)   0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
-#define AT91C_ADC_RNCR  ((AT91_REG *)   0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
-#define AT91C_ADC_RPR   ((AT91_REG *)   0xFFFD8100) // (PDC_ADC) Receive Pointer Register
-#define AT91C_ADC_TCR   ((AT91_REG *)   0xFFFD810C) // (PDC_ADC) Transmit Counter Register
-#define AT91C_ADC_TPR   ((AT91_REG *)   0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
-#define AT91C_ADC_RCR   ((AT91_REG *)   0xFFFD8104) // (PDC_ADC) Receive Counter Register
-// ========== Register definition for ADC peripheral ==========
-#define AT91C_ADC_CDR2  ((AT91_REG *)   0xFFFD8038) // (ADC) ADC Channel Data Register 2
-#define AT91C_ADC_CDR3  ((AT91_REG *)   0xFFFD803C) // (ADC) ADC Channel Data Register 3
-#define AT91C_ADC_CDR0  ((AT91_REG *)   0xFFFD8030) // (ADC) ADC Channel Data Register 0
-#define AT91C_ADC_CDR5  ((AT91_REG *)   0xFFFD8044) // (ADC) ADC Channel Data Register 5
-#define AT91C_ADC_CHDR  ((AT91_REG *)   0xFFFD8014) // (ADC) ADC Channel Disable Register
-#define AT91C_ADC_SR    ((AT91_REG *)   0xFFFD801C) // (ADC) ADC Status Register
-#define AT91C_ADC_CDR4  ((AT91_REG *)   0xFFFD8040) // (ADC) ADC Channel Data Register 4
-#define AT91C_ADC_CDR1  ((AT91_REG *)   0xFFFD8034) // (ADC) ADC Channel Data Register 1
-#define AT91C_ADC_LCDR  ((AT91_REG *)   0xFFFD8020) // (ADC) ADC Last Converted Data Register
-#define AT91C_ADC_IDR   ((AT91_REG *)   0xFFFD8028) // (ADC) ADC Interrupt Disable Register
-#define AT91C_ADC_CR    ((AT91_REG *)   0xFFFD8000) // (ADC) ADC Control Register
-#define AT91C_ADC_CDR7  ((AT91_REG *)   0xFFFD804C) // (ADC) ADC Channel Data Register 7
-#define AT91C_ADC_CDR6  ((AT91_REG *)   0xFFFD8048) // (ADC) ADC Channel Data Register 6
-#define AT91C_ADC_IER   ((AT91_REG *)   0xFFFD8024) // (ADC) ADC Interrupt Enable Register
-#define AT91C_ADC_CHER  ((AT91_REG *)   0xFFFD8010) // (ADC) ADC Channel Enable Register
-#define AT91C_ADC_CHSR  ((AT91_REG *)   0xFFFD8018) // (ADC) ADC Channel Status Register
-#define AT91C_ADC_MR    ((AT91_REG *)   0xFFFD8004) // (ADC) ADC Mode Register
-#define AT91C_ADC_IMR   ((AT91_REG *)   0xFFFD802C) // (ADC) ADC Interrupt Mask Register
-// ========== Register definition for PDC_AES peripheral ==========
-#define AT91C_AES_TPR   ((AT91_REG *)   0xFFFA4108) // (PDC_AES) Transmit Pointer Register
-#define AT91C_AES_PTCR  ((AT91_REG *)   0xFFFA4120) // (PDC_AES) PDC Transfer Control Register
-#define AT91C_AES_RNPR  ((AT91_REG *)   0xFFFA4110) // (PDC_AES) Receive Next Pointer Register
-#define AT91C_AES_TNCR  ((AT91_REG *)   0xFFFA411C) // (PDC_AES) Transmit Next Counter Register
-#define AT91C_AES_TCR   ((AT91_REG *)   0xFFFA410C) // (PDC_AES) Transmit Counter Register
-#define AT91C_AES_RCR   ((AT91_REG *)   0xFFFA4104) // (PDC_AES) Receive Counter Register
-#define AT91C_AES_RNCR  ((AT91_REG *)   0xFFFA4114) // (PDC_AES) Receive Next Counter Register
-#define AT91C_AES_TNPR  ((AT91_REG *)   0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register
-#define AT91C_AES_RPR   ((AT91_REG *)   0xFFFA4100) // (PDC_AES) Receive Pointer Register
-#define AT91C_AES_PTSR  ((AT91_REG *)   0xFFFA4124) // (PDC_AES) PDC Transfer Status Register
-// ========== Register definition for AES peripheral ==========
-#define AT91C_AES_IVxR  ((AT91_REG *)   0xFFFA4060) // (AES) Initialization Vector x Register
-#define AT91C_AES_MR    ((AT91_REG *)   0xFFFA4004) // (AES) Mode Register
-#define AT91C_AES_VR    ((AT91_REG *)   0xFFFA40FC) // (AES) AES Version Register
-#define AT91C_AES_ODATAxR ((AT91_REG *)     0xFFFA4050) // (AES) Output Data x Register
-#define AT91C_AES_IDATAxR ((AT91_REG *)     0xFFFA4040) // (AES) Input Data x Register
-#define AT91C_AES_CR    ((AT91_REG *)   0xFFFA4000) // (AES) Control Register
-#define AT91C_AES_IDR   ((AT91_REG *)   0xFFFA4014) // (AES) Interrupt Disable Register
-#define AT91C_AES_IMR   ((AT91_REG *)   0xFFFA4018) // (AES) Interrupt Mask Register
-#define AT91C_AES_IER   ((AT91_REG *)   0xFFFA4010) // (AES) Interrupt Enable Register
-#define AT91C_AES_KEYWxR ((AT91_REG *)  0xFFFA4020) // (AES) Key Word x Register
-#define AT91C_AES_ISR   ((AT91_REG *)   0xFFFA401C) // (AES) Interrupt Status Register
-// ========== Register definition for PDC_TDES peripheral ==========
-#define AT91C_TDES_RNCR ((AT91_REG *)   0xFFFA8114) // (PDC_TDES) Receive Next Counter Register
-#define AT91C_TDES_TCR  ((AT91_REG *)   0xFFFA810C) // (PDC_TDES) Transmit Counter Register
-#define AT91C_TDES_RCR  ((AT91_REG *)   0xFFFA8104) // (PDC_TDES) Receive Counter Register
-#define AT91C_TDES_TNPR ((AT91_REG *)   0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register
-#define AT91C_TDES_RNPR ((AT91_REG *)   0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register
-#define AT91C_TDES_RPR  ((AT91_REG *)   0xFFFA8100) // (PDC_TDES) Receive Pointer Register
-#define AT91C_TDES_TNCR ((AT91_REG *)   0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register
-#define AT91C_TDES_TPR  ((AT91_REG *)   0xFFFA8108) // (PDC_TDES) Transmit Pointer Register
-#define AT91C_TDES_PTSR ((AT91_REG *)   0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register
-#define AT91C_TDES_PTCR ((AT91_REG *)   0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register
-// ========== Register definition for TDES peripheral ==========
-#define AT91C_TDES_KEY2WxR ((AT91_REG *)    0xFFFA8028) // (TDES) Key 2 Word x Register
-#define AT91C_TDES_KEY3WxR ((AT91_REG *)    0xFFFA8030) // (TDES) Key 3 Word x Register
-#define AT91C_TDES_IDR  ((AT91_REG *)   0xFFFA8014) // (TDES) Interrupt Disable Register
-#define AT91C_TDES_VR   ((AT91_REG *)   0xFFFA80FC) // (TDES) TDES Version Register
-#define AT91C_TDES_IVxR ((AT91_REG *)   0xFFFA8060) // (TDES) Initialization Vector x Register
-#define AT91C_TDES_ODATAxR ((AT91_REG *)    0xFFFA8050) // (TDES) Output Data x Register
-#define AT91C_TDES_IMR  ((AT91_REG *)   0xFFFA8018) // (TDES) Interrupt Mask Register
-#define AT91C_TDES_MR   ((AT91_REG *)   0xFFFA8004) // (TDES) Mode Register
-#define AT91C_TDES_CR   ((AT91_REG *)   0xFFFA8000) // (TDES) Control Register
-#define AT91C_TDES_IER  ((AT91_REG *)   0xFFFA8010) // (TDES) Interrupt Enable Register
-#define AT91C_TDES_ISR  ((AT91_REG *)   0xFFFA801C) // (TDES) Interrupt Status Register
-#define AT91C_TDES_IDATAxR ((AT91_REG *)    0xFFFA8040) // (TDES) Input Data x Register
-#define AT91C_TDES_KEY1WxR ((AT91_REG *)    0xFFFA8020) // (TDES) Key 1 Word x Register
-
-// *****************************************************************************
-//               PIO DEFINITIONS FOR AT91SAM7X256
-// *****************************************************************************
-#define AT91C_PIO_PA0        ((unsigned int) 1 <<  0) // Pin Controlled by PA0
-#define AT91C_PA0_RXD0     ((unsigned int) AT91C_PIO_PA0) //  USART 0 Receive Data
-#define AT91C_PIO_PA1        ((unsigned int) 1 <<  1) // Pin Controlled by PA1
-#define AT91C_PA1_TXD0     ((unsigned int) AT91C_PIO_PA1) //  USART 0 Transmit Data
-#define AT91C_PIO_PA10       ((unsigned int) 1 << 10) // Pin Controlled by PA10
-#define AT91C_PA10_TWD      ((unsigned int) AT91C_PIO_PA10) //  TWI Two-wire Serial Data
-#define AT91C_PIO_PA11       ((unsigned int) 1 << 11) // Pin Controlled by PA11
-#define AT91C_PA11_TWCK     ((unsigned int) AT91C_PIO_PA11) //  TWI Two-wire Serial Clock
-#define AT91C_PIO_PA12       ((unsigned int) 1 << 12) // Pin Controlled by PA12
-#define AT91C_PA12_NPCS00   ((unsigned int) AT91C_PIO_PA12) //  SPI 0 Peripheral Chip Select 0
-#define AT91C_PIO_PA13       ((unsigned int) 1 << 13) // Pin Controlled by PA13
-#define AT91C_PA13_NPCS01   ((unsigned int) AT91C_PIO_PA13) //  SPI 0 Peripheral Chip Select 1
-#define AT91C_PA13_PCK1     ((unsigned int) AT91C_PIO_PA13) //  PMC Programmable Clock Output 1
-#define AT91C_PIO_PA14       ((unsigned int) 1 << 14) // Pin Controlled by PA14
-#define AT91C_PA14_NPCS02   ((unsigned int) AT91C_PIO_PA14) //  SPI 0 Peripheral Chip Select 2
-#define AT91C_PA14_IRQ1     ((unsigned int) AT91C_PIO_PA14) //  External Interrupt 1
-#define AT91C_PIO_PA15       ((unsigned int) 1 << 15) // Pin Controlled by PA15
-#define AT91C_PA15_NPCS03   ((unsigned int) AT91C_PIO_PA15) //  SPI 0 Peripheral Chip Select 3
-#define AT91C_PA15_TCLK2    ((unsigned int) AT91C_PIO_PA15) //  Timer Counter 2 external clock input
-#define AT91C_PIO_PA16       ((unsigned int) 1 << 16) // Pin Controlled by PA16
-#define AT91C_PA16_MISO0    ((unsigned int) AT91C_PIO_PA16) //  SPI 0 Master In Slave
-#define AT91C_PIO_PA17       ((unsigned int) 1 << 17) // Pin Controlled by PA17
-#define AT91C_PA17_MOSI0    ((unsigned int) AT91C_PIO_PA17) //  SPI 0 Master Out Slave
-#define AT91C_PIO_PA18       ((unsigned int) 1 << 18) // Pin Controlled by PA18
-#define AT91C_PA18_SPCK0    ((unsigned int) AT91C_PIO_PA18) //  SPI 0 Serial Clock
-#define AT91C_PIO_PA19       ((unsigned int) 1 << 19) // Pin Controlled by PA19
-#define AT91C_PA19_CANRX    ((unsigned int) AT91C_PIO_PA19) //  CAN Receive
-#define AT91C_PIO_PA2        ((unsigned int) 1 <<  2) // Pin Controlled by PA2
-#define AT91C_PA2_SCK0     ((unsigned int) AT91C_PIO_PA2) //  USART 0 Serial Clock
-#define AT91C_PA2_NPCS11   ((unsigned int) AT91C_PIO_PA2) //  SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PA20       ((unsigned int) 1 << 20) // Pin Controlled by PA20
-#define AT91C_PA20_CANTX    ((unsigned int) AT91C_PIO_PA20) //  CAN Transmit
-#define AT91C_PIO_PA21       ((unsigned int) 1 << 21) // Pin Controlled by PA21
-#define AT91C_PA21_TF       ((unsigned int) AT91C_PIO_PA21) //  SSC Transmit Frame Sync
-#define AT91C_PA21_NPCS10   ((unsigned int) AT91C_PIO_PA21) //  SPI 1 Peripheral Chip Select 0
-#define AT91C_PIO_PA22       ((unsigned int) 1 << 22) // Pin Controlled by PA22
-#define AT91C_PA22_TK       ((unsigned int) AT91C_PIO_PA22) //  SSC Transmit Clock
-#define AT91C_PA22_SPCK1    ((unsigned int) AT91C_PIO_PA22) //  SPI 1 Serial Clock
-#define AT91C_PIO_PA23       ((unsigned int) 1 << 23) // Pin Controlled by PA23
-#define AT91C_PA23_TD       ((unsigned int) AT91C_PIO_PA23) //  SSC Transmit data
-#define AT91C_PA23_MOSI1    ((unsigned int) AT91C_PIO_PA23) //  SPI 1 Master Out Slave
-#define AT91C_PIO_PA24       ((unsigned int) 1 << 24) // Pin Controlled by PA24
-#define AT91C_PA24_RD       ((unsigned int) AT91C_PIO_PA24) //  SSC Receive Data
-#define AT91C_PA24_MISO1    ((unsigned int) AT91C_PIO_PA24) //  SPI 1 Master In Slave
-#define AT91C_PIO_PA25       ((unsigned int) 1 << 25) // Pin Controlled by PA25
-#define AT91C_PA25_RK       ((unsigned int) AT91C_PIO_PA25) //  SSC Receive Clock
-#define AT91C_PA25_NPCS11   ((unsigned int) AT91C_PIO_PA25) //  SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PA26       ((unsigned int) 1 << 26) // Pin Controlled by PA26
-#define AT91C_PA26_RF       ((unsigned int) AT91C_PIO_PA26) //  SSC Receive Frame Sync
-#define AT91C_PA26_NPCS12   ((unsigned int) AT91C_PIO_PA26) //  SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PA27       ((unsigned int) 1 << 27) // Pin Controlled by PA27
-#define AT91C_PA27_DRXD     ((unsigned int) AT91C_PIO_PA27) //  DBGU Debug Receive Data
-#define AT91C_PA27_PCK3     ((unsigned int) AT91C_PIO_PA27) //  PMC Programmable Clock Output 3
-#define AT91C_PIO_PA28       ((unsigned int) 1 << 28) // Pin Controlled by PA28
-#define AT91C_PA28_DTXD     ((unsigned int) AT91C_PIO_PA28) //  DBGU Debug Transmit Data
-#define AT91C_PIO_PA29       ((unsigned int) 1 << 29) // Pin Controlled by PA29
-#define AT91C_PA29_FIQ      ((unsigned int) AT91C_PIO_PA29) //  AIC Fast Interrupt Input
-#define AT91C_PA29_NPCS13   ((unsigned int) AT91C_PIO_PA29) //  SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PA3        ((unsigned int) 1 <<  3) // Pin Controlled by PA3
-#define AT91C_PA3_RTS0     ((unsigned int) AT91C_PIO_PA3) //  USART 0 Ready To Send
-#define AT91C_PA3_NPCS12   ((unsigned int) AT91C_PIO_PA3) //  SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PA30       ((unsigned int) 1 << 30) // Pin Controlled by PA30
-#define AT91C_PA30_IRQ0     ((unsigned int) AT91C_PIO_PA30) //  External Interrupt 0
-#define AT91C_PA30_PCK2     ((unsigned int) AT91C_PIO_PA30) //  PMC Programmable Clock Output 2
-#define AT91C_PIO_PA4        ((unsigned int) 1 <<  4) // Pin Controlled by PA4
-#define AT91C_PA4_CTS0     ((unsigned int) AT91C_PIO_PA4) //  USART 0 Clear To Send
-#define AT91C_PA4_NPCS13   ((unsigned int) AT91C_PIO_PA4) //  SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PA5        ((unsigned int) 1 <<  5) // Pin Controlled by PA5
-#define AT91C_PA5_RXD1     ((unsigned int) AT91C_PIO_PA5) //  USART 1 Receive Data
-#define AT91C_PIO_PA6        ((unsigned int) 1 <<  6) // Pin Controlled by PA6
-#define AT91C_PA6_TXD1     ((unsigned int) AT91C_PIO_PA6) //  USART 1 Transmit Data
-#define AT91C_PIO_PA7        ((unsigned int) 1 <<  7) // Pin Controlled by PA7
-#define AT91C_PA7_SCK1     ((unsigned int) AT91C_PIO_PA7) //  USART 1 Serial Clock
-#define AT91C_PA7_NPCS01   ((unsigned int) AT91C_PIO_PA7) //  SPI 0 Peripheral Chip Select 1
-#define AT91C_PIO_PA8        ((unsigned int) 1 <<  8) // Pin Controlled by PA8
-#define AT91C_PA8_RTS1     ((unsigned int) AT91C_PIO_PA8) //  USART 1 Ready To Send
-#define AT91C_PA8_NPCS02   ((unsigned int) AT91C_PIO_PA8) //  SPI 0 Peripheral Chip Select 2
-#define AT91C_PIO_PA9        ((unsigned int) 1 <<  9) // Pin Controlled by PA9
-#define AT91C_PA9_CTS1     ((unsigned int) AT91C_PIO_PA9) //  USART 1 Clear To Send
-#define AT91C_PA9_NPCS03   ((unsigned int) AT91C_PIO_PA9) //  SPI 0 Peripheral Chip Select 3
-#define AT91C_PIO_PB0        ((unsigned int) 1 <<  0) // Pin Controlled by PB0
-#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) //  Ethernet MAC Transmit Clock/Reference Clock
-#define AT91C_PB0_PCK0     ((unsigned int) AT91C_PIO_PB0) //  PMC Programmable Clock Output 0
-#define AT91C_PIO_PB1        ((unsigned int) 1 <<  1) // Pin Controlled by PB1
-#define AT91C_PB1_ETXEN    ((unsigned int) AT91C_PIO_PB1) //  Ethernet MAC Transmit Enable
-#define AT91C_PIO_PB10       ((unsigned int) 1 << 10) // Pin Controlled by PB10
-#define AT91C_PB10_ETX2     ((unsigned int) AT91C_PIO_PB10) //  Ethernet MAC Transmit Data 2
-#define AT91C_PB10_NPCS11   ((unsigned int) AT91C_PIO_PB10) //  SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PB11       ((unsigned int) 1 << 11) // Pin Controlled by PB11
-#define AT91C_PB11_ETX3     ((unsigned int) AT91C_PIO_PB11) //  Ethernet MAC Transmit Data 3
-#define AT91C_PB11_NPCS12   ((unsigned int) AT91C_PIO_PB11) //  SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PB12       ((unsigned int) 1 << 12) // Pin Controlled by PB12
-#define AT91C_PB12_ETXER    ((unsigned int) AT91C_PIO_PB12) //  Ethernet MAC Transmikt Coding Error
-#define AT91C_PB12_TCLK0    ((unsigned int) AT91C_PIO_PB12) //  Timer Counter 0 external clock input
-#define AT91C_PIO_PB13       ((unsigned int) 1 << 13) // Pin Controlled by PB13
-#define AT91C_PB13_ERX2     ((unsigned int) AT91C_PIO_PB13) //  Ethernet MAC Receive Data 2
-#define AT91C_PB13_NPCS01   ((unsigned int) AT91C_PIO_PB13) //  SPI 0 Peripheral Chip Select 1
-#define AT91C_PIO_PB14       ((unsigned int) 1 << 14) // Pin Controlled by PB14
-#define AT91C_PB14_ERX3     ((unsigned int) AT91C_PIO_PB14) //  Ethernet MAC Receive Data 3
-#define AT91C_PB14_NPCS02   ((unsigned int) AT91C_PIO_PB14) //  SPI 0 Peripheral Chip Select 2
-#define AT91C_PIO_PB15       ((unsigned int) 1 << 15) // Pin Controlled by PB15
-#define AT91C_PB15_ERXDV    ((unsigned int) AT91C_PIO_PB15) //  Ethernet MAC Receive Data Valid
-#define AT91C_PIO_PB16       ((unsigned int) 1 << 16) // Pin Controlled by PB16
-#define AT91C_PB16_ECOL     ((unsigned int) AT91C_PIO_PB16) //  Ethernet MAC Collision Detected
-#define AT91C_PB16_NPCS13   ((unsigned int) AT91C_PIO_PB16) //  SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PB17       ((unsigned int) 1 << 17) // Pin Controlled by PB17
-#define AT91C_PB17_ERXCK    ((unsigned int) AT91C_PIO_PB17) //  Ethernet MAC Receive Clock
-#define AT91C_PB17_NPCS03   ((unsigned int) AT91C_PIO_PB17) //  SPI 0 Peripheral Chip Select 3
-#define AT91C_PIO_PB18       ((unsigned int) 1 << 18) // Pin Controlled by PB18
-#define AT91C_PB18_EF100    ((unsigned int) AT91C_PIO_PB18) //  Ethernet MAC Force 100 Mbits/sec
-#define AT91C_PB18_ADTRG    ((unsigned int) AT91C_PIO_PB18) //  ADC External Trigger
-#define AT91C_PIO_PB19       ((unsigned int) 1 << 19) // Pin Controlled by PB19
-#define AT91C_PB19_PWM0     ((unsigned int) AT91C_PIO_PB19) //  PWM Channel 0
-#define AT91C_PB19_TCLK1    ((unsigned int) AT91C_PIO_PB19) //  Timer Counter 1 external clock input
-#define AT91C_PIO_PB2        ((unsigned int) 1 <<  2) // Pin Controlled by PB2
-#define AT91C_PB2_ETX0     ((unsigned int) AT91C_PIO_PB2) //  Ethernet MAC Transmit Data 0
-#define AT91C_PIO_PB20       ((unsigned int) 1 << 20) // Pin Controlled by PB20
-#define AT91C_PB20_PWM1     ((unsigned int) AT91C_PIO_PB20) //  PWM Channel 1
-#define AT91C_PB20_PCK0     ((unsigned int) AT91C_PIO_PB20) //  PMC Programmable Clock Output 0
-#define AT91C_PIO_PB21       ((unsigned int) 1 << 21) // Pin Controlled by PB21
-#define AT91C_PB21_PWM2     ((unsigned int) AT91C_PIO_PB21) //  PWM Channel 2
-#define AT91C_PB21_PCK1     ((unsigned int) AT91C_PIO_PB21) //  PMC Programmable Clock Output 1
-#define AT91C_PIO_PB22       ((unsigned int) 1 << 22) // Pin Controlled by PB22
-#define AT91C_PB22_PWM3     ((unsigned int) AT91C_PIO_PB22) //  PWM Channel 3
-#define AT91C_PB22_PCK2     ((unsigned int) AT91C_PIO_PB22) //  PMC Programmable Clock Output 2
-#define AT91C_PIO_PB23       ((unsigned int) 1 << 23) // Pin Controlled by PB23
-#define AT91C_PB23_TIOA0    ((unsigned int) AT91C_PIO_PB23) //  Timer Counter 0 Multipurpose Timer I/O Pin A
-#define AT91C_PB23_DCD1     ((unsigned int) AT91C_PIO_PB23) //  USART 1 Data Carrier Detect
-#define AT91C_PIO_PB24       ((unsigned int) 1 << 24) // Pin Controlled by PB24
-#define AT91C_PB24_TIOB0    ((unsigned int) AT91C_PIO_PB24) //  Timer Counter 0 Multipurpose Timer I/O Pin B
-#define AT91C_PB24_DSR1     ((unsigned int) AT91C_PIO_PB24) //  USART 1 Data Set ready
-#define AT91C_PIO_PB25       ((unsigned int) 1 << 25) // Pin Controlled by PB25
-#define AT91C_PB25_TIOA1    ((unsigned int) AT91C_PIO_PB25) //  Timer Counter 1 Multipurpose Timer I/O Pin A
-#define AT91C_PB25_DTR1     ((unsigned int) AT91C_PIO_PB25) //  USART 1 Data Terminal ready
-#define AT91C_PIO_PB26       ((unsigned int) 1 << 26) // Pin Controlled by PB26
-#define AT91C_PB26_TIOB1    ((unsigned int) AT91C_PIO_PB26) //  Timer Counter 1 Multipurpose Timer I/O Pin B
-#define AT91C_PB26_RI1      ((unsigned int) AT91C_PIO_PB26) //  USART 1 Ring Indicator
-#define AT91C_PIO_PB27       ((unsigned int) 1 << 27) // Pin Controlled by PB27
-#define AT91C_PB27_TIOA2    ((unsigned int) AT91C_PIO_PB27) //  Timer Counter 2 Multipurpose Timer I/O Pin A
-#define AT91C_PB27_PWM0     ((unsigned int) AT91C_PIO_PB27) //  PWM Channel 0
-#define AT91C_PIO_PB28       ((unsigned int) 1 << 28) // Pin Controlled by PB28
-#define AT91C_PB28_TIOB2    ((unsigned int) AT91C_PIO_PB28) //  Timer Counter 2 Multipurpose Timer I/O Pin B
-#define AT91C_PB28_PWM1     ((unsigned int) AT91C_PIO_PB28) //  PWM Channel 1
-#define AT91C_PIO_PB29       ((unsigned int) 1 << 29) // Pin Controlled by PB29
-#define AT91C_PB29_PCK1     ((unsigned int) AT91C_PIO_PB29) //  PMC Programmable Clock Output 1
-#define AT91C_PB29_PWM2     ((unsigned int) AT91C_PIO_PB29) //  PWM Channel 2
-#define AT91C_PIO_PB3        ((unsigned int) 1 <<  3) // Pin Controlled by PB3
-#define AT91C_PB3_ETX1     ((unsigned int) AT91C_PIO_PB3) //  Ethernet MAC Transmit Data 1
-#define AT91C_PIO_PB30       ((unsigned int) 1 << 30) // Pin Controlled by PB30
-#define AT91C_PB30_PCK2     ((unsigned int) AT91C_PIO_PB30) //  PMC Programmable Clock Output 2
-#define AT91C_PB30_PWM3     ((unsigned int) AT91C_PIO_PB30) //  PWM Channel 3
-#define AT91C_PIO_PB4        ((unsigned int) 1 <<  4) // Pin Controlled by PB4
-#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) //  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
-#define AT91C_PIO_PB5        ((unsigned int) 1 <<  5) // Pin Controlled by PB5
-#define AT91C_PB5_ERX0     ((unsigned int) AT91C_PIO_PB5) //  Ethernet MAC Receive Data 0
-#define AT91C_PIO_PB6        ((unsigned int) 1 <<  6) // Pin Controlled by PB6
-#define AT91C_PB6_ERX1     ((unsigned int) AT91C_PIO_PB6) //  Ethernet MAC Receive Data 1
-#define AT91C_PIO_PB7        ((unsigned int) 1 <<  7) // Pin Controlled by PB7
-#define AT91C_PB7_ERXER    ((unsigned int) AT91C_PIO_PB7) //  Ethernet MAC Receive Error
-#define AT91C_PIO_PB8        ((unsigned int) 1 <<  8) // Pin Controlled by PB8
-#define AT91C_PB8_EMDC     ((unsigned int) AT91C_PIO_PB8) //  Ethernet MAC Management Data Clock
-#define AT91C_PIO_PB9        ((unsigned int) 1 <<  9) // Pin Controlled by PB9
-#define AT91C_PB9_EMDIO    ((unsigned int) AT91C_PIO_PB9) //  Ethernet MAC Management Data Input/Output
-
-// *****************************************************************************
-//               PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256
-// *****************************************************************************
-#define AT91C_ID_FIQ    ((unsigned int)  0) // Advanced Interrupt Controller (FIQ)
-#define AT91C_ID_SYS    ((unsigned int)  1) // System Peripheral
-#define AT91C_ID_PIOA   ((unsigned int)  2) // Parallel IO Controller A
-#define AT91C_ID_PIOB   ((unsigned int)  3) // Parallel IO Controller B
-#define AT91C_ID_SPI0   ((unsigned int)  4) // Serial Peripheral Interface 0
-#define AT91C_ID_SPI1   ((unsigned int)  5) // Serial Peripheral Interface 1
-#define AT91C_ID_US0    ((unsigned int)  6) // USART 0
-#define AT91C_ID_US1    ((unsigned int)  7) // USART 1
-#define AT91C_ID_SSC    ((unsigned int)  8) // Serial Synchronous Controller
-#define AT91C_ID_TWI    ((unsigned int)  9) // Two-Wire Interface
-#define AT91C_ID_PWMC   ((unsigned int) 10) // PWM Controller
-#define AT91C_ID_UDP    ((unsigned int) 11) // USB Device Port
-#define AT91C_ID_TC0    ((unsigned int) 12) // Timer Counter 0
-#define AT91C_ID_TC1    ((unsigned int) 13) // Timer Counter 1
-#define AT91C_ID_TC2    ((unsigned int) 14) // Timer Counter 2
-#define AT91C_ID_CAN    ((unsigned int) 15) // Control Area Network Controller
-#define AT91C_ID_EMAC   ((unsigned int) 16) // Ethernet MAC
-#define AT91C_ID_ADC    ((unsigned int) 17) // Analog-to-Digital Converter
-#define AT91C_ID_AES    ((unsigned int) 18) // Advanced Encryption Standard 128-bit
-#define AT91C_ID_TDES   ((unsigned int) 19) // Triple Data Encryption Standard
-#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved
-#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved
-#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved
-#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved
-#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved
-#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved
-#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved
-#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved
-#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved
-#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved
-#define AT91C_ID_IRQ0   ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0)
-#define AT91C_ID_IRQ1   ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1)
-
-// *****************************************************************************
-//               BASE ADDRESS DEFINITIONS FOR AT91SAM7X256
-// *****************************************************************************
-#define AT91C_BASE_SYS       ((AT91PS_SYS)  0xFFFFF000) // (SYS) Base Address
-#define AT91C_BASE_AIC       ((AT91PS_AIC)  0xFFFFF000) // (AIC) Base Address
-#define AT91C_BASE_PDC_DBGU  ((AT91PS_PDC)  0xFFFFF300) // (PDC_DBGU) Base Address
-#define AT91C_BASE_DBGU      ((AT91PS_DBGU)     0xFFFFF200) // (DBGU) Base Address
-#define AT91C_BASE_PIOA      ((AT91PS_PIO)  0xFFFFF400) // (PIOA) Base Address
-#define AT91C_BASE_PIOB      ((AT91PS_PIO)  0xFFFFF600) // (PIOB) Base Address
-#define AT91C_BASE_CKGR      ((AT91PS_CKGR)     0xFFFFFC20) // (CKGR) Base Address
-#define AT91C_BASE_PMC       ((AT91PS_PMC)  0xFFFFFC00) // (PMC) Base Address
-#define AT91C_BASE_RSTC      ((AT91PS_RSTC)     0xFFFFFD00) // (RSTC) Base Address
-#define AT91C_BASE_RTTC      ((AT91PS_RTTC)     0xFFFFFD20) // (RTTC) Base Address
-#define AT91C_BASE_PITC      ((AT91PS_PITC)     0xFFFFFD30) // (PITC) Base Address
-#define AT91C_BASE_WDTC      ((AT91PS_WDTC)     0xFFFFFD40) // (WDTC) Base Address
-#define AT91C_BASE_VREG      ((AT91PS_VREG)     0xFFFFFD60) // (VREG) Base Address
-#define AT91C_BASE_MC        ((AT91PS_MC)   0xFFFFFF00) // (MC) Base Address
-#define AT91C_BASE_PDC_SPI1  ((AT91PS_PDC)  0xFFFE4100) // (PDC_SPI1) Base Address
-#define AT91C_BASE_SPI1      ((AT91PS_SPI)  0xFFFE4000) // (SPI1) Base Address
-#define AT91C_BASE_PDC_SPI0  ((AT91PS_PDC)  0xFFFE0100) // (PDC_SPI0) Base Address
-#define AT91C_BASE_SPI0      ((AT91PS_SPI)  0xFFFE0000) // (SPI0) Base Address
-#define AT91C_BASE_PDC_US1   ((AT91PS_PDC)  0xFFFC4100) // (PDC_US1) Base Address
-#define AT91C_BASE_US1       ((AT91PS_USART)    0xFFFC4000) // (US1) Base Address
-#define AT91C_BASE_PDC_US0   ((AT91PS_PDC)  0xFFFC0100) // (PDC_US0) Base Address
-#define AT91C_BASE_US0       ((AT91PS_USART)    0xFFFC0000) // (US0) Base Address
-#define AT91C_BASE_PDC_SSC   ((AT91PS_PDC)  0xFFFD4100) // (PDC_SSC) Base Address
-#define AT91C_BASE_SSC       ((AT91PS_SSC)  0xFFFD4000) // (SSC) Base Address
-#define AT91C_BASE_TWI       ((AT91PS_TWI)  0xFFFB8000) // (TWI) Base Address
-#define AT91C_BASE_PWMC_CH3  ((AT91PS_PWMC_CH)  0xFFFCC260) // (PWMC_CH3) Base Address
-#define AT91C_BASE_PWMC_CH2  ((AT91PS_PWMC_CH)  0xFFFCC240) // (PWMC_CH2) Base Address
-#define AT91C_BASE_PWMC_CH1  ((AT91PS_PWMC_CH)  0xFFFCC220) // (PWMC_CH1) Base Address
-#define AT91C_BASE_PWMC_CH0  ((AT91PS_PWMC_CH)  0xFFFCC200) // (PWMC_CH0) Base Address
-#define AT91C_BASE_PWMC      ((AT91PS_PWMC)     0xFFFCC000) // (PWMC) Base Address
-#define AT91C_BASE_UDP       ((AT91PS_UDP)  0xFFFB0000) // (UDP) Base Address
-#define AT91C_BASE_TC0       ((AT91PS_TC)   0xFFFA0000) // (TC0) Base Address
-#define AT91C_BASE_TC1       ((AT91PS_TC)   0xFFFA0040) // (TC1) Base Address
-#define AT91C_BASE_TC2       ((AT91PS_TC)   0xFFFA0080) // (TC2) Base Address
-#define AT91C_BASE_TCB       ((AT91PS_TCB)  0xFFFA0000) // (TCB) Base Address
-#define AT91C_BASE_CAN_MB0   ((AT91PS_CAN_MB)   0xFFFD0200) // (CAN_MB0) Base Address
-#define AT91C_BASE_CAN_MB1   ((AT91PS_CAN_MB)   0xFFFD0220) // (CAN_MB1) Base Address
-#define AT91C_BASE_CAN_MB2   ((AT91PS_CAN_MB)   0xFFFD0240) // (CAN_MB2) Base Address
-#define AT91C_BASE_CAN_MB3   ((AT91PS_CAN_MB)   0xFFFD0260) // (CAN_MB3) Base Address
-#define AT91C_BASE_CAN_MB4   ((AT91PS_CAN_MB)   0xFFFD0280) // (CAN_MB4) Base Address
-#define AT91C_BASE_CAN_MB5   ((AT91PS_CAN_MB)   0xFFFD02A0) // (CAN_MB5) Base Address
-#define AT91C_BASE_CAN_MB6   ((AT91PS_CAN_MB)   0xFFFD02C0) // (CAN_MB6) Base Address
-#define AT91C_BASE_CAN_MB7   ((AT91PS_CAN_MB)   0xFFFD02E0) // (CAN_MB7) Base Address
-#define AT91C_BASE_CAN       ((AT91PS_CAN)  0xFFFD0000) // (CAN) Base Address
-#define AT91C_BASE_EMAC      ((AT91PS_EMAC)     0xFFFDC000) // (EMAC) Base Address
-#define AT91C_BASE_PDC_ADC   ((AT91PS_PDC)  0xFFFD8100) // (PDC_ADC) Base Address
-#define AT91C_BASE_ADC       ((AT91PS_ADC)  0xFFFD8000) // (ADC) Base Address
-#define AT91C_BASE_PDC_AES   ((AT91PS_PDC)  0xFFFA4100) // (PDC_AES) Base Address
-#define AT91C_BASE_AES       ((AT91PS_AES)  0xFFFA4000) // (AES) Base Address
-#define AT91C_BASE_PDC_TDES  ((AT91PS_PDC)  0xFFFA8100) // (PDC_TDES) Base Address
-#define AT91C_BASE_TDES      ((AT91PS_TDES)     0xFFFA8000) // (TDES) Base Address
-
-// *****************************************************************************
-//               MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256
-// *****************************************************************************
-#define AT91C_ISRAM  ((char *)  0x00200000) // Internal SRAM base address
-#define AT91C_ISRAM_SIZE     ((unsigned int) 0x00010000) // Internal SRAM size in byte (64 Kbyte)
-#define AT91C_IFLASH     ((char *)  0x00100000) // Internal ROM base address
-#define AT91C_IFLASH_SIZE    ((unsigned int) 0x00040000) // Internal ROM size in byte (256 Kbyte)
-
-
-
-// - Hardware register definition
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR System Peripherals
-// - *****************************************************************************
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
-// - *****************************************************************************
-// - -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
+typedef volatile unsigned int AT91_REG; /* Hardware register definition */
+
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR System Peripherals */
+/* ***************************************************************************** */
+typedef struct _AT91S_SYS
+{
+    AT91_REG AIC_SMR[ 32 ];     /* Source Mode Register */
+    AT91_REG AIC_SVR[ 32 ];     /* Source Vector Register */
+    AT91_REG AIC_IVR;           /* IRQ Vector Register */
+    AT91_REG AIC_FVR;           /* FIQ Vector Register */
+    AT91_REG AIC_ISR;           /* Interrupt Status Register */
+    AT91_REG AIC_IPR;           /* Interrupt Pending Register */
+    AT91_REG AIC_IMR;           /* Interrupt Mask Register */
+    AT91_REG AIC_CISR;          /* Core Interrupt Status Register */
+    AT91_REG Reserved0[ 2 ];    /* */
+    AT91_REG AIC_IECR;          /* Interrupt Enable Command Register */
+    AT91_REG AIC_IDCR;          /* Interrupt Disable Command Register */
+    AT91_REG AIC_ICCR;          /* Interrupt Clear Command Register */
+    AT91_REG AIC_ISCR;          /* Interrupt Set Command Register */
+    AT91_REG AIC_EOICR;         /* End of Interrupt Command Register */
+    AT91_REG AIC_SPU;           /* Spurious Vector Register */
+    AT91_REG AIC_DCR;           /* Debug Control Register (Protect) */
+    AT91_REG Reserved1[ 1 ];    /* */
+    AT91_REG AIC_FFER;          /* Fast Forcing Enable Register */
+    AT91_REG AIC_FFDR;          /* Fast Forcing Disable Register */
+    AT91_REG AIC_FFSR;          /* Fast Forcing Status Register */
+    AT91_REG Reserved2[ 45 ];   /* */
+    AT91_REG DBGU_CR;           /* Control Register */
+    AT91_REG DBGU_MR;           /* Mode Register */
+    AT91_REG DBGU_IER;          /* Interrupt Enable Register */
+    AT91_REG DBGU_IDR;          /* Interrupt Disable Register */
+    AT91_REG DBGU_IMR;          /* Interrupt Mask Register */
+    AT91_REG DBGU_CSR;          /* Channel Status Register */
+    AT91_REG DBGU_RHR;          /* Receiver Holding Register */
+    AT91_REG DBGU_THR;          /* Transmitter Holding Register */
+    AT91_REG DBGU_BRGR;         /* Baud Rate Generator Register */
+    AT91_REG Reserved3[ 7 ];    /* */
+    AT91_REG DBGU_CIDR;         /* Chip ID Register */
+    AT91_REG DBGU_EXID;         /* Chip ID Extension Register */
+    AT91_REG DBGU_FNTR;         /* Force NTRST Register */
+    AT91_REG Reserved4[ 45 ];   /* */
+    AT91_REG DBGU_RPR;          /* Receive Pointer Register */
+    AT91_REG DBGU_RCR;          /* Receive Counter Register */
+    AT91_REG DBGU_TPR;          /* Transmit Pointer Register */
+    AT91_REG DBGU_TCR;          /* Transmit Counter Register */
+    AT91_REG DBGU_RNPR;         /* Receive Next Pointer Register */
+    AT91_REG DBGU_RNCR;         /* Receive Next Counter Register */
+    AT91_REG DBGU_TNPR;         /* Transmit Next Pointer Register */
+    AT91_REG DBGU_TNCR;         /* Transmit Next Counter Register */
+    AT91_REG DBGU_PTCR;         /* PDC Transfer Control Register */
+    AT91_REG DBGU_PTSR;         /* PDC Transfer Status Register */
+    AT91_REG Reserved5[ 54 ];   /* */
+    AT91_REG PIOA_PER;          /* PIO Enable Register */
+    AT91_REG PIOA_PDR;          /* PIO Disable Register */
+    AT91_REG PIOA_PSR;          /* PIO Status Register */
+    AT91_REG Reserved6[ 1 ];    /* */
+    AT91_REG PIOA_OER;          /* Output Enable Register */
+    AT91_REG PIOA_ODR;          /* Output Disable Registerr */
+    AT91_REG PIOA_OSR;          /* Output Status Register */
+    AT91_REG Reserved7[ 1 ];    /* */
+    AT91_REG PIOA_IFER;         /* Input Filter Enable Register */
+    AT91_REG PIOA_IFDR;         /* Input Filter Disable Register */
+    AT91_REG PIOA_IFSR;         /* Input Filter Status Register */
+    AT91_REG Reserved8[ 1 ];    /* */
+    AT91_REG PIOA_SODR;         /* Set Output Data Register */
+    AT91_REG PIOA_CODR;         /* Clear Output Data Register */
+    AT91_REG PIOA_ODSR;         /* Output Data Status Register */
+    AT91_REG PIOA_PDSR;         /* Pin Data Status Register */
+    AT91_REG PIOA_IER;          /* Interrupt Enable Register */
+    AT91_REG PIOA_IDR;          /* Interrupt Disable Register */
+    AT91_REG PIOA_IMR;          /* Interrupt Mask Register */
+    AT91_REG PIOA_ISR;          /* Interrupt Status Register */
+    AT91_REG PIOA_MDER;         /* Multi-driver Enable Register */
+    AT91_REG PIOA_MDDR;         /* Multi-driver Disable Register */
+    AT91_REG PIOA_MDSR;         /* Multi-driver Status Register */
+    AT91_REG Reserved9[ 1 ];    /* */
+    AT91_REG PIOA_PPUDR;        /* Pull-up Disable Register */
+    AT91_REG PIOA_PPUER;        /* Pull-up Enable Register */
+    AT91_REG PIOA_PPUSR;        /* Pull-up Status Register */
+    AT91_REG Reserved10[ 1 ];   /* */
+    AT91_REG PIOA_ASR;          /* Select A Register */
+    AT91_REG PIOA_BSR;          /* Select B Register */
+    AT91_REG PIOA_ABSR;         /* AB Select Status Register */
+    AT91_REG Reserved11[ 9 ];   /* */
+    AT91_REG PIOA_OWER;         /* Output Write Enable Register */
+    AT91_REG PIOA_OWDR;         /* Output Write Disable Register */
+    AT91_REG PIOA_OWSR;         /* Output Write Status Register */
+    AT91_REG Reserved12[ 85 ];  /* */
+    AT91_REG PIOB_PER;          /* PIO Enable Register */
+    AT91_REG PIOB_PDR;          /* PIO Disable Register */
+    AT91_REG PIOB_PSR;          /* PIO Status Register */
+    AT91_REG Reserved13[ 1 ];   /* */
+    AT91_REG PIOB_OER;          /* Output Enable Register */
+    AT91_REG PIOB_ODR;          /* Output Disable Registerr */
+    AT91_REG PIOB_OSR;          /* Output Status Register */
+    AT91_REG Reserved14[ 1 ];   /* */
+    AT91_REG PIOB_IFER;         /* Input Filter Enable Register */
+    AT91_REG PIOB_IFDR;         /* Input Filter Disable Register */
+    AT91_REG PIOB_IFSR;         /* Input Filter Status Register */
+    AT91_REG Reserved15[ 1 ];   /* */
+    AT91_REG PIOB_SODR;         /* Set Output Data Register */
+    AT91_REG PIOB_CODR;         /* Clear Output Data Register */
+    AT91_REG PIOB_ODSR;         /* Output Data Status Register */
+    AT91_REG PIOB_PDSR;         /* Pin Data Status Register */
+    AT91_REG PIOB_IER;          /* Interrupt Enable Register */
+    AT91_REG PIOB_IDR;          /* Interrupt Disable Register */
+    AT91_REG PIOB_IMR;          /* Interrupt Mask Register */
+    AT91_REG PIOB_ISR;          /* Interrupt Status Register */
+    AT91_REG PIOB_MDER;         /* Multi-driver Enable Register */
+    AT91_REG PIOB_MDDR;         /* Multi-driver Disable Register */
+    AT91_REG PIOB_MDSR;         /* Multi-driver Status Register */
+    AT91_REG Reserved16[ 1 ];   /* */
+    AT91_REG PIOB_PPUDR;        /* Pull-up Disable Register */
+    AT91_REG PIOB_PPUER;        /* Pull-up Enable Register */
+    AT91_REG PIOB_PPUSR;        /* Pull-up Status Register */
+    AT91_REG Reserved17[ 1 ];   /* */
+    AT91_REG PIOB_ASR;          /* Select A Register */
+    AT91_REG PIOB_BSR;          /* Select B Register */
+    AT91_REG PIOB_ABSR;         /* AB Select Status Register */
+    AT91_REG Reserved18[ 9 ];   /* */
+    AT91_REG PIOB_OWER;         /* Output Write Enable Register */
+    AT91_REG PIOB_OWDR;         /* Output Write Disable Register */
+    AT91_REG PIOB_OWSR;         /* Output Write Status Register */
+    AT91_REG Reserved19[ 341 ]; /* */
+    AT91_REG PMC_SCER;          /* System Clock Enable Register */
+    AT91_REG PMC_SCDR;          /* System Clock Disable Register */
+    AT91_REG PMC_SCSR;          /* System Clock Status Register */
+    AT91_REG Reserved20[ 1 ];   /* */
+    AT91_REG PMC_PCER;          /* Peripheral Clock Enable Register */
+    AT91_REG PMC_PCDR;          /* Peripheral Clock Disable Register */
+    AT91_REG PMC_PCSR;          /* Peripheral Clock Status Register */
+    AT91_REG Reserved21[ 1 ];   /* */
+    AT91_REG PMC_MOR;           /* Main Oscillator Register */
+    AT91_REG PMC_MCFR;          /* Main Clock  Frequency Register */
+    AT91_REG Reserved22[ 1 ];   /* */
+    AT91_REG PMC_PLLR;          /* PLL Register */
+    AT91_REG PMC_MCKR;          /* Master Clock Register */
+    AT91_REG Reserved23[ 3 ];   /* */
+    AT91_REG PMC_PCKR[ 4 ];     /* Programmable Clock Register */
+    AT91_REG Reserved24[ 4 ];   /* */
+    AT91_REG PMC_IER;           /* Interrupt Enable Register */
+    AT91_REG PMC_IDR;           /* Interrupt Disable Register */
+    AT91_REG PMC_SR;            /* Status Register */
+    AT91_REG PMC_IMR;           /* Interrupt Mask Register */
+    AT91_REG Reserved25[ 36 ];  /* */
+    AT91_REG RSTC_RCR;          /* Reset Control Register */
+    AT91_REG RSTC_RSR;          /* Reset Status Register */
+    AT91_REG RSTC_RMR;          /* Reset Mode Register */
+    AT91_REG Reserved26[ 5 ];   /* */
+    AT91_REG RTTC_RTMR;         /* Real-time Mode Register */
+    AT91_REG RTTC_RTAR;         /* Real-time Alarm Register */
+    AT91_REG RTTC_RTVR;         /* Real-time Value Register */
+    AT91_REG RTTC_RTSR;         /* Real-time Status Register */
+    AT91_REG PITC_PIMR;         /* Period Interval Mode Register */
+    AT91_REG PITC_PISR;         /* Period Interval Status Register */
+    AT91_REG PITC_PIVR;         /* Period Interval Value Register */
+    AT91_REG PITC_PIIR;         /* Period Interval Image Register */
+    AT91_REG WDTC_WDCR;         /* Watchdog Control Register */
+    AT91_REG WDTC_WDMR;         /* Watchdog Mode Register */
+    AT91_REG WDTC_WDSR;         /* Watchdog Status Register */
+    AT91_REG Reserved27[ 5 ];   /* */
+    AT91_REG VREG_MR;           /* Voltage Regulator Mode Register */
+} AT91S_SYS, * AT91PS_SYS;
+
+
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller */
+/* ***************************************************************************** */
+typedef struct _AT91S_AIC
+{
+    AT91_REG AIC_SMR[ 32 ];  /* Source Mode Register */
+    AT91_REG AIC_SVR[ 32 ];  /* Source Vector Register */
+    AT91_REG AIC_IVR;        /* IRQ Vector Register */
+    AT91_REG AIC_FVR;        /* FIQ Vector Register */
+    AT91_REG AIC_ISR;        /* Interrupt Status Register */
+    AT91_REG AIC_IPR;        /* Interrupt Pending Register */
+    AT91_REG AIC_IMR;        /* Interrupt Mask Register */
+    AT91_REG AIC_CISR;       /* Core Interrupt Status Register */
+    AT91_REG Reserved0[ 2 ]; /* */
+    AT91_REG AIC_IECR;       /* Interrupt Enable Command Register */
+    AT91_REG AIC_IDCR;       /* Interrupt Disable Command Register */
+    AT91_REG AIC_ICCR;       /* Interrupt Clear Command Register */
+    AT91_REG AIC_ISCR;       /* Interrupt Set Command Register */
+    AT91_REG AIC_EOICR;      /* End of Interrupt Command Register */
+    AT91_REG AIC_SPU;        /* Spurious Vector Register */
+    AT91_REG AIC_DCR;        /* Debug Control Register (Protect) */
+    AT91_REG Reserved1[ 1 ]; /* */
+    AT91_REG AIC_FFER;       /* Fast Forcing Enable Register */
+    AT91_REG AIC_FFDR;       /* Fast Forcing Disable Register */
+    AT91_REG AIC_FFSR;       /* Fast Forcing Status Register */
+} AT91S_AIC, * AT91PS_AIC;
+
+/* -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- */
+#define AT91C_AIC_PRIOR                            ( ( unsigned int ) 0x7 << 0 ) /* (AIC) Priority Level */
+#define     AT91C_AIC_PRIOR_LOWEST                 ( ( unsigned int ) 0x0 )      /* (AIC) Lowest priority level */
+#define     AT91C_AIC_PRIOR_HIGHEST                ( ( unsigned int ) 0x7 )      /* (AIC) Highest priority level */
+#define AT91C_AIC_SRCTYPE                          ( ( unsigned int ) 0x3 << 5 ) /* (AIC) Interrupt Source Type */
+#define     AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL       ( ( unsigned int ) 0x0 << 5 ) /* (AIC) Internal Sources Code Label High-level Sensitive */
+#define     AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL        ( ( unsigned int ) 0x0 << 5 ) /* (AIC) External Sources Code Label Low-level Sensitive */
+#define     AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE    ( ( unsigned int ) 0x1 << 5 ) /* (AIC) Internal Sources Code Label Positive Edge triggered */
+#define     AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE    ( ( unsigned int ) 0x1 << 5 ) /* (AIC) External Sources Code Label Negative Edge triggered */
+#define     AT91C_AIC_SRCTYPE_HIGH_LEVEL           ( ( unsigned int ) 0x2 << 5 ) /* (AIC) Internal Or External Sources Code Label High-level Sensitive */
+#define     AT91C_AIC_SRCTYPE_POSITIVE_EDGE        ( ( unsigned int ) 0x3 << 5 ) /* (AIC) Internal Or External Sources Code Label Positive Edge triggered */
+/* -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- */
+#define AT91C_AIC_NFIQ                             ( ( unsigned int ) 0x1 << 0 ) /* (AIC) NFIQ Status */
+#define AT91C_AIC_NIRQ                             ( ( unsigned int ) 0x1 << 1 ) /* (AIC) NIRQ Status */
+/* -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- */
+#define AT91C_AIC_DCR_PROT                         ( ( unsigned int ) 0x1 << 0 ) /* (AIC) Protection Mode */
+#define AT91C_AIC_DCR_GMSK                         ( ( unsigned int ) 0x1 << 1 ) /* (AIC) General Mask */
+
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller */
+/* ***************************************************************************** */
+typedef struct _AT91S_PDC
+{
+    AT91_REG PDC_RPR;  /* Receive Pointer Register */
+    AT91_REG PDC_RCR;  /* Receive Counter Register */
+    AT91_REG PDC_TPR;  /* Transmit Pointer Register */
+    AT91_REG PDC_TCR;  /* Transmit Counter Register */
+    AT91_REG PDC_RNPR; /* Receive Next Pointer Register */
+    AT91_REG PDC_RNCR; /* Receive Next Counter Register */
+    AT91_REG PDC_TNPR; /* Transmit Next Pointer Register */
+    AT91_REG PDC_TNCR; /* Transmit Next Counter Register */
+    AT91_REG PDC_PTCR; /* PDC Transfer Control Register */
+    AT91_REG PDC_PTSR; /* PDC Transfer Status Register */
+} AT91S_PDC, * AT91PS_PDC;
+
+/* -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */
+#define AT91C_PDC_RXTEN     ( ( unsigned int ) 0x1 << 0 ) /* (PDC) Receiver Transfer Enable */
+#define AT91C_PDC_RXTDIS    ( ( unsigned int ) 0x1 << 1 ) /* (PDC) Receiver Transfer Disable */
+#define AT91C_PDC_TXTEN     ( ( unsigned int ) 0x1 << 8 ) /* (PDC) Transmitter Transfer Enable */
+#define AT91C_PDC_TXTDIS    ( ( unsigned int ) 0x1 << 9 ) /* (PDC) Transmitter Transfer Disable */
+/* -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- */
+
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Debug Unit */
+/* ***************************************************************************** */
+typedef struct _AT91S_DBGU
+{
+    AT91_REG DBGU_CR;         /* Control Register */
+    AT91_REG DBGU_MR;         /* Mode Register */
+    AT91_REG DBGU_IER;        /* Interrupt Enable Register */
+    AT91_REG DBGU_IDR;        /* Interrupt Disable Register */
+    AT91_REG DBGU_IMR;        /* Interrupt Mask Register */
+    AT91_REG DBGU_CSR;        /* Channel Status Register */
+    AT91_REG DBGU_RHR;        /* Receiver Holding Register */
+    AT91_REG DBGU_THR;        /* Transmitter Holding Register */
+    AT91_REG DBGU_BRGR;       /* Baud Rate Generator Register */
+    AT91_REG Reserved0[ 7 ];  /* */
+    AT91_REG DBGU_CIDR;       /* Chip ID Register */
+    AT91_REG DBGU_EXID;       /* Chip ID Extension Register */
+    AT91_REG DBGU_FNTR;       /* Force NTRST Register */
+    AT91_REG Reserved1[ 45 ]; /* */
+    AT91_REG DBGU_RPR;        /* Receive Pointer Register */
+    AT91_REG DBGU_RCR;        /* Receive Counter Register */
+    AT91_REG DBGU_TPR;        /* Transmit Pointer Register */
+    AT91_REG DBGU_TCR;        /* Transmit Counter Register */
+    AT91_REG DBGU_RNPR;       /* Receive Next Pointer Register */
+    AT91_REG DBGU_RNCR;       /* Receive Next Counter Register */
+    AT91_REG DBGU_TNPR;       /* Transmit Next Pointer Register */
+    AT91_REG DBGU_TNCR;       /* Transmit Next Counter Register */
+    AT91_REG DBGU_PTCR;       /* PDC Transfer Control Register */
+    AT91_REG DBGU_PTSR;       /* PDC Transfer Status Register */
+} AT91S_DBGU, * AT91PS_DBGU;
+
+/* -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- */
+#define AT91C_US_RSTRX                 ( ( unsigned int ) 0x1 << 2 )  /* (DBGU) Reset Receiver */
+#define AT91C_US_RSTTX                 ( ( unsigned int ) 0x1 << 3 )  /* (DBGU) Reset Transmitter */
+#define AT91C_US_RXEN                  ( ( unsigned int ) 0x1 << 4 )  /* (DBGU) Receiver Enable */
+#define AT91C_US_RXDIS                 ( ( unsigned int ) 0x1 << 5 )  /* (DBGU) Receiver Disable */
+#define AT91C_US_TXEN                  ( ( unsigned int ) 0x1 << 6 )  /* (DBGU) Transmitter Enable */
+#define AT91C_US_TXDIS                 ( ( unsigned int ) 0x1 << 7 )  /* (DBGU) Transmitter Disable */
+#define AT91C_US_RSTSTA                ( ( unsigned int ) 0x1 << 8 )  /* (DBGU) Reset Status Bits */
+/* -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- */
+#define AT91C_US_PAR                   ( ( unsigned int ) 0x7 << 9 )  /* (DBGU) Parity type */
+#define     AT91C_US_PAR_EVEN          ( ( unsigned int ) 0x0 << 9 )  /* (DBGU) Even Parity */
+#define     AT91C_US_PAR_ODD           ( ( unsigned int ) 0x1 << 9 )  /* (DBGU) Odd Parity */
+#define     AT91C_US_PAR_SPACE         ( ( unsigned int ) 0x2 << 9 )  /* (DBGU) Parity forced to 0 (Space) */
+#define     AT91C_US_PAR_MARK          ( ( unsigned int ) 0x3 << 9 )  /* (DBGU) Parity forced to 1 (Mark) */
+#define     AT91C_US_PAR_NONE          ( ( unsigned int ) 0x4 << 9 )  /* (DBGU) No Parity */
+#define     AT91C_US_PAR_MULTI_DROP    ( ( unsigned int ) 0x6 << 9 )  /* (DBGU) Multi-drop mode */
+#define AT91C_US_CHMODE                ( ( unsigned int ) 0x3 << 14 ) /* (DBGU) Channel Mode */
+#define     AT91C_US_CHMODE_NORMAL     ( ( unsigned int ) 0x0 << 14 ) /* (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. */
+#define     AT91C_US_CHMODE_AUTO       ( ( unsigned int ) 0x1 << 14 ) /* (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. */
+#define     AT91C_US_CHMODE_LOCAL      ( ( unsigned int ) 0x2 << 14 ) /* (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. */
+#define     AT91C_US_CHMODE_REMOTE     ( ( unsigned int ) 0x3 << 14 ) /* (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. */
+/* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */
+#define AT91C_US_RXRDY                 ( ( unsigned int ) 0x1 << 0 )  /* (DBGU) RXRDY Interrupt */
+#define AT91C_US_TXRDY                 ( ( unsigned int ) 0x1 << 1 )  /* (DBGU) TXRDY Interrupt */
+#define AT91C_US_ENDRX                 ( ( unsigned int ) 0x1 << 3 )  /* (DBGU) End of Receive Transfer Interrupt */
+#define AT91C_US_ENDTX                 ( ( unsigned int ) 0x1 << 4 )  /* (DBGU) End of Transmit Interrupt */
+#define AT91C_US_OVRE                  ( ( unsigned int ) 0x1 << 5 )  /* (DBGU) Overrun Interrupt */
+#define AT91C_US_FRAME                 ( ( unsigned int ) 0x1 << 6 )  /* (DBGU) Framing Error Interrupt */
+#define AT91C_US_PARE                  ( ( unsigned int ) 0x1 << 7 )  /* (DBGU) Parity Error Interrupt */
+#define AT91C_US_TXEMPTY               ( ( unsigned int ) 0x1 << 9 )  /* (DBGU) TXEMPTY Interrupt */
+#define AT91C_US_TXBUFE                ( ( unsigned int ) 0x1 << 11 ) /* (DBGU) TXBUFE Interrupt */
+#define AT91C_US_RXBUFF                ( ( unsigned int ) 0x1 << 12 ) /* (DBGU) RXBUFF Interrupt */
+#define AT91C_US_COMM_TX               ( ( unsigned int ) 0x1 << 30 ) /* (DBGU) COMM_TX Interrupt */
+#define AT91C_US_COMM_RX               ( ( unsigned int ) 0x1 << 31 ) /* (DBGU) COMM_RX Interrupt */
+/* -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- */
+/* -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- */
+/* -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- */
+/* -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- */
+#define AT91C_US_FORCE_NTRST    ( ( unsigned int ) 0x1 << 0 ) /* (DBGU) Force NTRST in JTAG */
+
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Parallel Input Output Controller */
+/* ***************************************************************************** */
+typedef struct _AT91S_PIO
+{
+    AT91_REG PIO_PER;        /* PIO Enable Register */
+    AT91_REG PIO_PDR;        /* PIO Disable Register */
+    AT91_REG PIO_PSR;        /* PIO Status Register */
+    AT91_REG Reserved0[ 1 ]; /* */
+    AT91_REG PIO_OER;        /* Output Enable Register */
+    AT91_REG PIO_ODR;        /* Output Disable Registerr */
+    AT91_REG PIO_OSR;        /* Output Status Register */
+    AT91_REG Reserved1[ 1 ]; /* */
+    AT91_REG PIO_IFER;       /* Input Filter Enable Register */
+    AT91_REG PIO_IFDR;       /* Input Filter Disable Register */
+    AT91_REG PIO_IFSR;       /* Input Filter Status Register */
+    AT91_REG Reserved2[ 1 ]; /* */
+    AT91_REG PIO_SODR;       /* Set Output Data Register */
+    AT91_REG PIO_CODR;       /* Clear Output Data Register */
+    AT91_REG PIO_ODSR;       /* Output Data Status Register */
+    AT91_REG PIO_PDSR;       /* Pin Data Status Register */
+    AT91_REG PIO_IER;        /* Interrupt Enable Register */
+    AT91_REG PIO_IDR;        /* Interrupt Disable Register */
+    AT91_REG PIO_IMR;        /* Interrupt Mask Register */
+    AT91_REG PIO_ISR;        /* Interrupt Status Register */
+    AT91_REG PIO_MDER;       /* Multi-driver Enable Register */
+    AT91_REG PIO_MDDR;       /* Multi-driver Disable Register */
+    AT91_REG PIO_MDSR;       /* Multi-driver Status Register */
+    AT91_REG Reserved3[ 1 ]; /* */
+    AT91_REG PIO_PPUDR;      /* Pull-up Disable Register */
+    AT91_REG PIO_PPUER;      /* Pull-up Enable Register */
+    AT91_REG PIO_PPUSR;      /* Pull-up Status Register */
+    AT91_REG Reserved4[ 1 ]; /* */
+    AT91_REG PIO_ASR;        /* Select A Register */
+    AT91_REG PIO_BSR;        /* Select B Register */
+    AT91_REG PIO_ABSR;       /* AB Select Status Register */
+    AT91_REG Reserved5[ 9 ]; /* */
+    AT91_REG PIO_OWER;       /* Output Write Enable Register */
+    AT91_REG PIO_OWDR;       /* Output Write Disable Register */
+    AT91_REG PIO_OWSR;       /* Output Write Status Register */
+} AT91S_PIO, * AT91PS_PIO;
+
+
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Clock Generator Controller */
+/* ***************************************************************************** */
+typedef struct _AT91S_CKGR
+{
+    AT91_REG CKGR_MOR;       /* Main Oscillator Register */
+    AT91_REG CKGR_MCFR;      /* Main Clock  Frequency Register */
+    AT91_REG Reserved0[ 1 ]; /* */
+    AT91_REG CKGR_PLLR;      /* PLL Register */
+} AT91S_CKGR, * AT91PS_CKGR;
+
+/* -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */
+#define AT91C_CKGR_MOSCEN            ( ( unsigned int ) 0x1 << 0 )    /* (CKGR) Main Oscillator Enable */
+#define AT91C_CKGR_OSCBYPASS         ( ( unsigned int ) 0x1 << 1 )    /* (CKGR) Main Oscillator Bypass */
+#define AT91C_CKGR_OSCOUNT           ( ( unsigned int ) 0xFF << 8 )   /* (CKGR) Main Oscillator Start-up Time */
+/* -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- */
+#define AT91C_CKGR_MAINF             ( ( unsigned int ) 0xFFFF << 0 ) /* (CKGR) Main Clock Frequency */
+#define AT91C_CKGR_MAINRDY           ( ( unsigned int ) 0x1 << 16 )   /* (CKGR) Main Clock Ready */
+/* -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- */
+#define AT91C_CKGR_DIV               ( ( unsigned int ) 0xFF << 0 )   /* (CKGR) Divider Selected */
+#define     AT91C_CKGR_DIV_0         ( ( unsigned int ) 0x0 )         /* (CKGR) Divider output is 0 */
+#define     AT91C_CKGR_DIV_BYPASS    ( ( unsigned int ) 0x1 )         /* (CKGR) Divider is bypassed */
+#define AT91C_CKGR_PLLCOUNT          ( ( unsigned int ) 0x3F << 8 )   /* (CKGR) PLL Counter */
+#define AT91C_CKGR_OUT               ( ( unsigned int ) 0x3 << 14 )   /* (CKGR) PLL Output Frequency Range */
+#define     AT91C_CKGR_OUT_0         ( ( unsigned int ) 0x0 << 14 )   /* (CKGR) Please refer to the PLL datasheet */
+#define     AT91C_CKGR_OUT_1         ( ( unsigned int ) 0x1 << 14 )   /* (CKGR) Please refer to the PLL datasheet */
+#define     AT91C_CKGR_OUT_2         ( ( unsigned int ) 0x2 << 14 )   /* (CKGR) Please refer to the PLL datasheet */
+#define     AT91C_CKGR_OUT_3         ( ( unsigned int ) 0x3 << 14 )   /* (CKGR) Please refer to the PLL datasheet */
+#define AT91C_CKGR_MUL               ( ( unsigned int ) 0x7FF << 16 ) /* (CKGR) PLL Multiplier */
+#define AT91C_CKGR_USBDIV            ( ( unsigned int ) 0x3 << 28 )   /* (CKGR) Divider for USB Clocks */
+#define     AT91C_CKGR_USBDIV_0      ( ( unsigned int ) 0x0 << 28 )   /* (CKGR) Divider output is PLL clock output */
+#define     AT91C_CKGR_USBDIV_1      ( ( unsigned int ) 0x1 << 28 )   /* (CKGR) Divider output is PLL clock output divided by 2 */
+#define     AT91C_CKGR_USBDIV_2      ( ( unsigned int ) 0x2 << 28 )   /* (CKGR) Divider output is PLL clock output divided by 4 */
+
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Power Management Controller */
+/* ***************************************************************************** */
+typedef struct _AT91S_PMC
+{
+    AT91_REG PMC_SCER;       /* System Clock Enable Register */
+    AT91_REG PMC_SCDR;       /* System Clock Disable Register */
+    AT91_REG PMC_SCSR;       /* System Clock Status Register */
+    AT91_REG Reserved0[ 1 ]; /* */
+    AT91_REG PMC_PCER;       /* Peripheral Clock Enable Register */
+    AT91_REG PMC_PCDR;       /* Peripheral Clock Disable Register */
+    AT91_REG PMC_PCSR;       /* Peripheral Clock Status Register */
+    AT91_REG Reserved1[ 1 ]; /* */
+    AT91_REG PMC_MOR;        /* Main Oscillator Register */
+    AT91_REG PMC_MCFR;       /* Main Clock  Frequency Register */
+    AT91_REG Reserved2[ 1 ]; /* */
+    AT91_REG PMC_PLLR;       /* PLL Register */
+    AT91_REG PMC_MCKR;       /* Master Clock Register */
+    AT91_REG Reserved3[ 3 ]; /* */
+    AT91_REG PMC_PCKR[ 4 ];  /* Programmable Clock Register */
+    AT91_REG Reserved4[ 4 ]; /* */
+    AT91_REG PMC_IER;        /* Interrupt Enable Register */
+    AT91_REG PMC_IDR;        /* Interrupt Disable Register */
+    AT91_REG PMC_SR;         /* Status Register */
+    AT91_REG PMC_IMR;        /* Interrupt Mask Register */
+} AT91S_PMC, * AT91PS_PMC;
+
+/* -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- */
+#define AT91C_PMC_PCK     ( ( unsigned int ) 0x1 << 0 )  /* (PMC) Processor Clock */
+#define AT91C_PMC_UDP     ( ( unsigned int ) 0x1 << 7 )  /* (PMC) USB Device Port Clock */
+#define AT91C_PMC_PCK0    ( ( unsigned int ) 0x1 << 8 )  /* (PMC) Programmable Clock Output */
+#define AT91C_PMC_PCK1    ( ( unsigned int ) 0x1 << 9 )  /* (PMC) Programmable Clock Output */
+#define AT91C_PMC_PCK2    ( ( unsigned int ) 0x1 << 10 ) /* (PMC) Programmable Clock Output */
+#define AT91C_PMC_PCK3    ( ( unsigned int ) 0x1 << 11 ) /* (PMC) Programmable Clock Output */
+/* -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- */
+/* -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- */
+/* -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- */
+/* -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- */
+/* -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- */
+/* -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- */
+#define AT91C_PMC_CSS                 ( ( unsigned int ) 0x3 << 0 ) /* (PMC) Programmable Clock Selection */
+#define     AT91C_PMC_CSS_SLOW_CLK    ( ( unsigned int ) 0x0 )      /* (PMC) Slow Clock is selected */
+#define     AT91C_PMC_CSS_MAIN_CLK    ( ( unsigned int ) 0x1 )      /* (PMC) Main Clock is selected */
+#define     AT91C_PMC_CSS_PLL_CLK     ( ( unsigned int ) 0x3 )      /* (PMC) Clock from PLL is selected */
+#define AT91C_PMC_PRES                ( ( unsigned int ) 0x7 << 2 ) /* (PMC) Programmable Clock Prescaler */
+#define     AT91C_PMC_PRES_CLK        ( ( unsigned int ) 0x0 << 2 ) /* (PMC) Selected clock */
+#define     AT91C_PMC_PRES_CLK_2      ( ( unsigned int ) 0x1 << 2 ) /* (PMC) Selected clock divided by 2 */
+#define     AT91C_PMC_PRES_CLK_4      ( ( unsigned int ) 0x2 << 2 ) /* (PMC) Selected clock divided by 4 */
+#define     AT91C_PMC_PRES_CLK_8      ( ( unsigned int ) 0x3 << 2 ) /* (PMC) Selected clock divided by 8 */
+#define     AT91C_PMC_PRES_CLK_16     ( ( unsigned int ) 0x4 << 2 ) /* (PMC) Selected clock divided by 16 */
+#define     AT91C_PMC_PRES_CLK_32     ( ( unsigned int ) 0x5 << 2 ) /* (PMC) Selected clock divided by 32 */
+#define     AT91C_PMC_PRES_CLK_64     ( ( unsigned int ) 0x6 << 2 ) /* (PMC) Selected clock divided by 64 */
+/* -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- */
+/* -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- */
+#define AT91C_PMC_MOSCS               ( ( unsigned int ) 0x1 << 0 )  /* (PMC) MOSC Status/Enable/Disable/Mask */
+#define AT91C_PMC_LOCK                ( ( unsigned int ) 0x1 << 2 )  /* (PMC) PLL Status/Enable/Disable/Mask */
+#define AT91C_PMC_MCKRDY              ( ( unsigned int ) 0x1 << 3 )  /* (PMC) MCK_RDY Status/Enable/Disable/Mask */
+#define AT91C_PMC_PCK0RDY             ( ( unsigned int ) 0x1 << 8 )  /* (PMC) PCK0_RDY Status/Enable/Disable/Mask */
+#define AT91C_PMC_PCK1RDY             ( ( unsigned int ) 0x1 << 9 )  /* (PMC) PCK1_RDY Status/Enable/Disable/Mask */
+#define AT91C_PMC_PCK2RDY             ( ( unsigned int ) 0x1 << 10 ) /* (PMC) PCK2_RDY Status/Enable/Disable/Mask */
+#define AT91C_PMC_PCK3RDY             ( ( unsigned int ) 0x1 << 11 ) /* (PMC) PCK3_RDY Status/Enable/Disable/Mask */
+/* -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- */
+/* -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- */
+/* -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- */
+
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Reset Controller Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_RSTC
+{
+    AT91_REG RSTC_RCR; /* Reset Control Register */
+    AT91_REG RSTC_RSR; /* Reset Status Register */
+    AT91_REG RSTC_RMR; /* Reset Mode Register */
+} AT91S_RSTC, * AT91PS_RSTC;
+
+/* -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- */
+#define AT91C_RSTC_PROCRST                ( ( unsigned int ) 0x1 << 0 )   /* (RSTC) Processor Reset */
+#define AT91C_RSTC_PERRST                 ( ( unsigned int ) 0x1 << 2 )   /* (RSTC) Peripheral Reset */
+#define AT91C_RSTC_EXTRST                 ( ( unsigned int ) 0x1 << 3 )   /* (RSTC) External Reset */
+#define AT91C_RSTC_KEY                    ( ( unsigned int ) 0xFF << 24 ) /* (RSTC) Password */
+/* -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- */
+#define AT91C_RSTC_URSTS                  ( ( unsigned int ) 0x1 << 0 )   /* (RSTC) User Reset Status */
+#define AT91C_RSTC_BODSTS                 ( ( unsigned int ) 0x1 << 1 )   /* (RSTC) Brownout Detection Status */
+#define AT91C_RSTC_RSTTYP                 ( ( unsigned int ) 0x7 << 8 )   /* (RSTC) Reset Type */
+#define     AT91C_RSTC_RSTTYP_POWERUP     ( ( unsigned int ) 0x0 << 8 )   /* (RSTC) Power-up Reset. VDDCORE rising. */
+#define     AT91C_RSTC_RSTTYP_WAKEUP      ( ( unsigned int ) 0x1 << 8 )   /* (RSTC) WakeUp Reset. VDDCORE rising. */
+#define     AT91C_RSTC_RSTTYP_WATCHDOG    ( ( unsigned int ) 0x2 << 8 )   /* (RSTC) Watchdog Reset. Watchdog overflow occurred. */
+#define     AT91C_RSTC_RSTTYP_SOFTWARE    ( ( unsigned int ) 0x3 << 8 )   /* (RSTC) Software Reset. Processor reset required by the software. */
+#define     AT91C_RSTC_RSTTYP_USER        ( ( unsigned int ) 0x4 << 8 )   /* (RSTC) User Reset. NRST pin detected low. */
+#define     AT91C_RSTC_RSTTYP_BROWNOUT    ( ( unsigned int ) 0x5 << 8 )   /* (RSTC) Brownout Reset occurred. */
+#define AT91C_RSTC_NRSTL                  ( ( unsigned int ) 0x1 << 16 )  /* (RSTC) NRST pin level */
+#define AT91C_RSTC_SRCMP                  ( ( unsigned int ) 0x1 << 17 )  /* (RSTC) Software Reset Command in Progress. */
+/* -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- */
+#define AT91C_RSTC_URSTEN                 ( ( unsigned int ) 0x1 << 0 )   /* (RSTC) User Reset Enable */
+#define AT91C_RSTC_URSTIEN                ( ( unsigned int ) 0x1 << 4 )   /* (RSTC) User Reset Interrupt Enable */
+#define AT91C_RSTC_ERSTL                  ( ( unsigned int ) 0xF << 8 )   /* (RSTC) User Reset Enable */
+#define AT91C_RSTC_BODIEN                 ( ( unsigned int ) 0x1 << 16 )  /* (RSTC) Brownout Detection Interrupt Enable */
+
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_RTTC
+{
+    AT91_REG RTTC_RTMR; /* Real-time Mode Register */
+    AT91_REG RTTC_RTAR; /* Real-time Alarm Register */
+    AT91_REG RTTC_RTVR; /* Real-time Value Register */
+    AT91_REG RTTC_RTSR; /* Real-time Status Register */
+} AT91S_RTTC, * AT91PS_RTTC;
+
+/* -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- */
+#define AT91C_RTTC_RTPRES       ( ( unsigned int ) 0xFFFF << 0 ) /* (RTTC) Real-time Timer Prescaler Value */
+#define AT91C_RTTC_ALMIEN       ( ( unsigned int ) 0x1 << 16 )   /* (RTTC) Alarm Interrupt Enable */
+#define AT91C_RTTC_RTTINCIEN    ( ( unsigned int ) 0x1 << 17 )   /* (RTTC) Real Time Timer Increment Interrupt Enable */
+#define AT91C_RTTC_RTTRST       ( ( unsigned int ) 0x1 << 18 )   /* (RTTC) Real Time Timer Restart */
+/* -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- */
+#define AT91C_RTTC_ALMV         ( ( unsigned int ) 0x0 << 0 )    /* (RTTC) Alarm Value */
+/* -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- */
+#define AT91C_RTTC_CRTV         ( ( unsigned int ) 0x0 << 0 )    /* (RTTC) Current Real-time Value */
+/* -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- */
+#define AT91C_RTTC_ALMS         ( ( unsigned int ) 0x1 << 0 )    /* (RTTC) Real-time Alarm Status */
+#define AT91C_RTTC_RTTINC       ( ( unsigned int ) 0x1 << 1 )    /* (RTTC) Real-time Timer Increment */
+
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_PITC
+{
+    AT91_REG PITC_PIMR; /* Period Interval Mode Register */
+    AT91_REG PITC_PISR; /* Period Interval Status Register */
+    AT91_REG PITC_PIVR; /* Period Interval Value Register */
+    AT91_REG PITC_PIIR; /* Period Interval Image Register */
+} AT91S_PITC, * AT91PS_PITC;
+
+/* -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- */
+#define AT91C_PITC_PIV       ( ( unsigned int ) 0xFFFFF << 0 ) /* (PITC) Periodic Interval Value */
+#define AT91C_PITC_PITEN     ( ( unsigned int ) 0x1 << 24 )    /* (PITC) Periodic Interval Timer Enabled */
+#define AT91C_PITC_PITIEN    ( ( unsigned int ) 0x1 << 25 )    /* (PITC) Periodic Interval Timer Interrupt Enable */
+/* -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- */
+#define AT91C_PITC_PITS      ( ( unsigned int ) 0x1 << 0 )     /* (PITC) Periodic Interval Timer Status */
+/* -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- */
+#define AT91C_PITC_CPIV      ( ( unsigned int ) 0xFFFFF << 0 ) /* (PITC) Current Periodic Interval Value */
+#define AT91C_PITC_PICNT     ( ( unsigned int ) 0xFFF << 20 )  /* (PITC) Periodic Interval Counter */
+/* -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- */
+
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_WDTC
+{
+    AT91_REG WDTC_WDCR; /* Watchdog Control Register */
+    AT91_REG WDTC_WDMR; /* Watchdog Mode Register */
+    AT91_REG WDTC_WDSR; /* Watchdog Status Register */
+} AT91S_WDTC, * AT91PS_WDTC;
+
+/* -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- */
+#define AT91C_WDTC_WDRSTT       ( ( unsigned int ) 0x1 << 0 )    /* (WDTC) Watchdog Restart */
+#define AT91C_WDTC_KEY          ( ( unsigned int ) 0xFF << 24 )  /* (WDTC) Watchdog KEY Password */
+/* -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- */
+#define AT91C_WDTC_WDV          ( ( unsigned int ) 0xFFF << 0 )  /* (WDTC) Watchdog Timer Restart */
+#define AT91C_WDTC_WDFIEN       ( ( unsigned int ) 0x1 << 12 )   /* (WDTC) Watchdog Fault Interrupt Enable */
+#define AT91C_WDTC_WDRSTEN      ( ( unsigned int ) 0x1 << 13 )   /* (WDTC) Watchdog Reset Enable */
+#define AT91C_WDTC_WDRPROC      ( ( unsigned int ) 0x1 << 14 )   /* (WDTC) Watchdog Timer Restart */
+#define AT91C_WDTC_WDDIS        ( ( unsigned int ) 0x1 << 15 )   /* (WDTC) Watchdog Disable */
+#define AT91C_WDTC_WDD          ( ( unsigned int ) 0xFFF << 16 ) /* (WDTC) Watchdog Delta Value */
+#define AT91C_WDTC_WDDBGHLT     ( ( unsigned int ) 0x1 << 28 )   /* (WDTC) Watchdog Debug Halt */
+#define AT91C_WDTC_WDIDLEHLT    ( ( unsigned int ) 0x1 << 29 )   /* (WDTC) Watchdog Idle Halt */
+/* -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- */
+#define AT91C_WDTC_WDUNF        ( ( unsigned int ) 0x1 << 0 )    /* (WDTC) Watchdog Underflow */
+#define AT91C_WDTC_WDERR        ( ( unsigned int ) 0x1 << 1 )    /* (WDTC) Watchdog Error */
+
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Voltage Regulator Mode Controller Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_VREG
+{
+    AT91_REG VREG_MR; /* Voltage Regulator Mode Register */
+} AT91S_VREG, * AT91PS_VREG;
+
+/* -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- */
+#define AT91C_VREG_PSTDBY    ( ( unsigned int ) 0x1 << 0 ) /* (VREG) Voltage Regulator Power Standby Mode */
+
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Memory Controller Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_MC
+{
+    AT91_REG MC_RCR;          /* MC Remap Control Register */
+    AT91_REG MC_ASR;          /* MC Abort Status Register */
+    AT91_REG MC_AASR;         /* MC Abort Address Status Register */
+    AT91_REG Reserved0[ 21 ]; /* */
+    AT91_REG MC_FMR;          /* MC Flash Mode Register */
+    AT91_REG MC_FCR;          /* MC Flash Command Register */
+    AT91_REG MC_FSR;          /* MC Flash Status Register */
+} AT91S_MC, * AT91PS_MC;
+
+/* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */
+#define AT91C_MC_RCB                       ( ( unsigned int ) 0x1 << 0 )   /* (MC) Remap Command Bit */
+/* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */
+#define AT91C_MC_UNDADD                    ( ( unsigned int ) 0x1 << 0 )   /* (MC) Undefined Addess Abort Status */
+#define AT91C_MC_MISADD                    ( ( unsigned int ) 0x1 << 1 )   /* (MC) Misaligned Addess Abort Status */
+#define AT91C_MC_ABTSZ                     ( ( unsigned int ) 0x3 << 8 )   /* (MC) Abort Size Status */
+#define     AT91C_MC_ABTSZ_BYTE            ( ( unsigned int ) 0x0 << 8 )   /* (MC) Byte */
+#define     AT91C_MC_ABTSZ_HWORD           ( ( unsigned int ) 0x1 << 8 )   /* (MC) Half-word */
+#define     AT91C_MC_ABTSZ_WORD            ( ( unsigned int ) 0x2 << 8 )   /* (MC) Word */
+#define AT91C_MC_ABTTYP                    ( ( unsigned int ) 0x3 << 10 )  /* (MC) Abort Type Status */
+#define     AT91C_MC_ABTTYP_DATAR          ( ( unsigned int ) 0x0 << 10 )  /* (MC) Data Read */
+#define     AT91C_MC_ABTTYP_DATAW          ( ( unsigned int ) 0x1 << 10 )  /* (MC) Data Write */
+#define     AT91C_MC_ABTTYP_FETCH          ( ( unsigned int ) 0x2 << 10 )  /* (MC) Code Fetch */
+#define AT91C_MC_MST0                      ( ( unsigned int ) 0x1 << 16 )  /* (MC) Master 0 Abort Source */
+#define AT91C_MC_MST1                      ( ( unsigned int ) 0x1 << 17 )  /* (MC) Master 1 Abort Source */
+#define AT91C_MC_SVMST0                    ( ( unsigned int ) 0x1 << 24 )  /* (MC) Saved Master 0 Abort Source */
+#define AT91C_MC_SVMST1                    ( ( unsigned int ) 0x1 << 25 )  /* (MC) Saved Master 1 Abort Source */
+/* -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- */
+#define AT91C_MC_FRDY                      ( ( unsigned int ) 0x1 << 0 )   /* (MC) Flash Ready */
+#define AT91C_MC_LOCKE                     ( ( unsigned int ) 0x1 << 2 )   /* (MC) Lock Error */
+#define AT91C_MC_PROGE                     ( ( unsigned int ) 0x1 << 3 )   /* (MC) Programming Error */
+#define AT91C_MC_NEBP                      ( ( unsigned int ) 0x1 << 7 )   /* (MC) No Erase Before Programming */
+#define AT91C_MC_FWS                       ( ( unsigned int ) 0x3 << 8 )   /* (MC) Flash Wait State */
+#define     AT91C_MC_FWS_0FWS              ( ( unsigned int ) 0x0 << 8 )   /* (MC) 1 cycle for Read, 2 for Write operations */
+#define     AT91C_MC_FWS_1FWS              ( ( unsigned int ) 0x1 << 8 )   /* (MC) 2 cycles for Read, 3 for Write operations */
+#define     AT91C_MC_FWS_2FWS              ( ( unsigned int ) 0x2 << 8 )   /* (MC) 3 cycles for Read, 4 for Write operations */
+#define     AT91C_MC_FWS_3FWS              ( ( unsigned int ) 0x3 << 8 )   /* (MC) 4 cycles for Read, 4 for Write operations */
+#define AT91C_MC_FMCN                      ( ( unsigned int ) 0xFF << 16 ) /* (MC) Flash Microsecond Cycle Number */
+/* -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- */
+#define AT91C_MC_FCMD                      ( ( unsigned int ) 0xF << 0 )   /* (MC) Flash Command */
+#define     AT91C_MC_FCMD_START_PROG       ( ( unsigned int ) 0x1 )        /* (MC) Starts the programming of th epage specified by PAGEN. */
+#define     AT91C_MC_FCMD_LOCK             ( ( unsigned int ) 0x2 )        /* (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */
+#define     AT91C_MC_FCMD_PROG_AND_LOCK    ( ( unsigned int ) 0x3 )        /* (MC) The lock sequence automatically happens after the programming sequence is completed. */
+#define     AT91C_MC_FCMD_UNLOCK           ( ( unsigned int ) 0x4 )        /* (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */
+#define     AT91C_MC_FCMD_ERASE_ALL        ( ( unsigned int ) 0x8 )        /* (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. */
+#define     AT91C_MC_FCMD_SET_GP_NVM       ( ( unsigned int ) 0xB )        /* (MC) Set General Purpose NVM bits. */
+#define     AT91C_MC_FCMD_CLR_GP_NVM       ( ( unsigned int ) 0xD )        /* (MC) Clear General Purpose NVM bits. */
+#define     AT91C_MC_FCMD_SET_SECURITY     ( ( unsigned int ) 0xF )        /* (MC) Set Security Bit. */
+#define AT91C_MC_PAGEN                     ( ( unsigned int ) 0x3FF << 8 ) /* (MC) Page Number */
+#define AT91C_MC_KEY                       ( ( unsigned int ) 0xFF << 24 ) /* (MC) Writing Protect Key */
+/* -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- */
+#define AT91C_MC_SECURITY                  ( ( unsigned int ) 0x1 << 4 )   /* (MC) Security Bit Status */
+#define AT91C_MC_GPNVM0                    ( ( unsigned int ) 0x1 << 8 )   /* (MC) Sector 0 Lock Status */
+#define AT91C_MC_GPNVM1                    ( ( unsigned int ) 0x1 << 9 )   /* (MC) Sector 1 Lock Status */
+#define AT91C_MC_GPNVM2                    ( ( unsigned int ) 0x1 << 10 )  /* (MC) Sector 2 Lock Status */
+#define AT91C_MC_GPNVM3                    ( ( unsigned int ) 0x1 << 11 )  /* (MC) Sector 3 Lock Status */
+#define AT91C_MC_GPNVM4                    ( ( unsigned int ) 0x1 << 12 )  /* (MC) Sector 4 Lock Status */
+#define AT91C_MC_GPNVM5                    ( ( unsigned int ) 0x1 << 13 )  /* (MC) Sector 5 Lock Status */
+#define AT91C_MC_GPNVM6                    ( ( unsigned int ) 0x1 << 14 )  /* (MC) Sector 6 Lock Status */
+#define AT91C_MC_GPNVM7                    ( ( unsigned int ) 0x1 << 15 )  /* (MC) Sector 7 Lock Status */
+#define AT91C_MC_LOCKS0                    ( ( unsigned int ) 0x1 << 16 )  /* (MC) Sector 0 Lock Status */
+#define AT91C_MC_LOCKS1                    ( ( unsigned int ) 0x1 << 17 )  /* (MC) Sector 1 Lock Status */
+#define AT91C_MC_LOCKS2                    ( ( unsigned int ) 0x1 << 18 )  /* (MC) Sector 2 Lock Status */
+#define AT91C_MC_LOCKS3                    ( ( unsigned int ) 0x1 << 19 )  /* (MC) Sector 3 Lock Status */
+#define AT91C_MC_LOCKS4                    ( ( unsigned int ) 0x1 << 20 )  /* (MC) Sector 4 Lock Status */
+#define AT91C_MC_LOCKS5                    ( ( unsigned int ) 0x1 << 21 )  /* (MC) Sector 5 Lock Status */
+#define AT91C_MC_LOCKS6                    ( ( unsigned int ) 0x1 << 22 )  /* (MC) Sector 6 Lock Status */
+#define AT91C_MC_LOCKS7                    ( ( unsigned int ) 0x1 << 23 )  /* (MC) Sector 7 Lock Status */
+#define AT91C_MC_LOCKS8                    ( ( unsigned int ) 0x1 << 24 )  /* (MC) Sector 8 Lock Status */
+#define AT91C_MC_LOCKS9                    ( ( unsigned int ) 0x1 << 25 )  /* (MC) Sector 9 Lock Status */
+#define AT91C_MC_LOCKS10                   ( ( unsigned int ) 0x1 << 26 )  /* (MC) Sector 10 Lock Status */
+#define AT91C_MC_LOCKS11                   ( ( unsigned int ) 0x1 << 27 )  /* (MC) Sector 11 Lock Status */
+#define AT91C_MC_LOCKS12                   ( ( unsigned int ) 0x1 << 28 )  /* (MC) Sector 12 Lock Status */
+#define AT91C_MC_LOCKS13                   ( ( unsigned int ) 0x1 << 29 )  /* (MC) Sector 13 Lock Status */
+#define AT91C_MC_LOCKS14                   ( ( unsigned int ) 0x1 << 30 )  /* (MC) Sector 14 Lock Status */
+#define AT91C_MC_LOCKS15                   ( ( unsigned int ) 0x1 << 31 )  /* (MC) Sector 15 Lock Status */
+
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Serial Parallel Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_SPI
+{
+    AT91_REG SPI_CR;          /* Control Register */
+    AT91_REG SPI_MR;          /* Mode Register */
+    AT91_REG SPI_RDR;         /* Receive Data Register */
+    AT91_REG SPI_TDR;         /* Transmit Data Register */
+    AT91_REG SPI_SR;          /* Status Register */
+    AT91_REG SPI_IER;         /* Interrupt Enable Register */
+    AT91_REG SPI_IDR;         /* Interrupt Disable Register */
+    AT91_REG SPI_IMR;         /* Interrupt Mask Register */
+    AT91_REG Reserved0[ 4 ];  /* */
+    AT91_REG SPI_CSR[ 4 ];    /* Chip Select Register */
+    AT91_REG Reserved1[ 48 ]; /* */
+    AT91_REG SPI_RPR;         /* Receive Pointer Register */
+    AT91_REG SPI_RCR;         /* Receive Counter Register */
+    AT91_REG SPI_TPR;         /* Transmit Pointer Register */
+    AT91_REG SPI_TCR;         /* Transmit Counter Register */
+    AT91_REG SPI_RNPR;        /* Receive Next Pointer Register */
+    AT91_REG SPI_RNCR;        /* Receive Next Counter Register */
+    AT91_REG SPI_TNPR;        /* Transmit Next Pointer Register */
+    AT91_REG SPI_TNCR;        /* Transmit Next Counter Register */
+    AT91_REG SPI_PTCR;        /* PDC Transfer Control Register */
+    AT91_REG SPI_PTSR;        /* PDC Transfer Status Register */
+} AT91S_SPI, * AT91PS_SPI;
+
+/* -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */
+#define AT91C_SPI_SPIEN              ( ( unsigned int ) 0x1 << 0 )    /* (SPI) SPI Enable */
+#define AT91C_SPI_SPIDIS             ( ( unsigned int ) 0x1 << 1 )    /* (SPI) SPI Disable */
+#define AT91C_SPI_SWRST              ( ( unsigned int ) 0x1 << 7 )    /* (SPI) SPI Software reset */
+#define AT91C_SPI_LASTXFER           ( ( unsigned int ) 0x1 << 24 )   /* (SPI) SPI Last Transfer */
+/* -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- */
+#define AT91C_SPI_MSTR               ( ( unsigned int ) 0x1 << 0 )    /* (SPI) Master/Slave Mode */
+#define AT91C_SPI_PS                 ( ( unsigned int ) 0x1 << 1 )    /* (SPI) Peripheral Select */
+#define     AT91C_SPI_PS_FIXED       ( ( unsigned int ) 0x0 << 1 )    /* (SPI) Fixed Peripheral Select */
+#define     AT91C_SPI_PS_VARIABLE    ( ( unsigned int ) 0x1 << 1 )    /* (SPI) Variable Peripheral Select */
+#define AT91C_SPI_PCSDEC             ( ( unsigned int ) 0x1 << 2 )    /* (SPI) Chip Select Decode */
+#define AT91C_SPI_FDIV               ( ( unsigned int ) 0x1 << 3 )    /* (SPI) Clock Selection */
+#define AT91C_SPI_MODFDIS            ( ( unsigned int ) 0x1 << 4 )    /* (SPI) Mode Fault Detection */
+#define AT91C_SPI_LLB                ( ( unsigned int ) 0x1 << 7 )    /* (SPI) Clock Selection */
+#define AT91C_SPI_PCS                ( ( unsigned int ) 0xF << 16 )   /* (SPI) Peripheral Chip Select */
+#define AT91C_SPI_DLYBCS             ( ( unsigned int ) 0xFF << 24 )  /* (SPI) Delay Between Chip Selects */
+/* -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- */
+#define AT91C_SPI_RD                 ( ( unsigned int ) 0xFFFF << 0 ) /* (SPI) Receive Data */
+#define AT91C_SPI_RPCS               ( ( unsigned int ) 0xF << 16 )   /* (SPI) Peripheral Chip Select Status */
+/* -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- */
+#define AT91C_SPI_TD                 ( ( unsigned int ) 0xFFFF << 0 ) /* (SPI) Transmit Data */
+#define AT91C_SPI_TPCS               ( ( unsigned int ) 0xF << 16 )   /* (SPI) Peripheral Chip Select Status */
+/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
+#define AT91C_SPI_RDRF               ( ( unsigned int ) 0x1 << 0 )    /* (SPI) Receive Data Register Full */
+#define AT91C_SPI_TDRE               ( ( unsigned int ) 0x1 << 1 )    /* (SPI) Transmit Data Register Empty */
+#define AT91C_SPI_MODF               ( ( unsigned int ) 0x1 << 2 )    /* (SPI) Mode Fault Error */
+#define AT91C_SPI_OVRES              ( ( unsigned int ) 0x1 << 3 )    /* (SPI) Overrun Error Status */
+#define AT91C_SPI_ENDRX              ( ( unsigned int ) 0x1 << 4 )    /* (SPI) End of Receiver Transfer */
+#define AT91C_SPI_ENDTX              ( ( unsigned int ) 0x1 << 5 )    /* (SPI) End of Receiver Transfer */
+#define AT91C_SPI_RXBUFF             ( ( unsigned int ) 0x1 << 6 )    /* (SPI) RXBUFF Interrupt */
+#define AT91C_SPI_TXBUFE             ( ( unsigned int ) 0x1 << 7 )    /* (SPI) TXBUFE Interrupt */
+#define AT91C_SPI_NSSR               ( ( unsigned int ) 0x1 << 8 )    /* (SPI) NSSR Interrupt */
+#define AT91C_SPI_TXEMPTY            ( ( unsigned int ) 0x1 << 9 )    /* (SPI) TXEMPTY Interrupt */
+#define AT91C_SPI_SPIENS             ( ( unsigned int ) 0x1 << 16 )   /* (SPI) Enable Status */
+/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
+/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
+/* -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */
+/* -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */
+#define AT91C_SPI_CPOL           ( ( unsigned int ) 0x1 << 0 )   /* (SPI) Clock Polarity */
+#define AT91C_SPI_NCPHA          ( ( unsigned int ) 0x1 << 1 )   /* (SPI) Clock Phase */
+#define AT91C_SPI_CSAAT          ( ( unsigned int ) 0x1 << 3 )   /* (SPI) Chip Select Active After Transfer */
+#define AT91C_SPI_BITS           ( ( unsigned int ) 0xF << 4 )   /* (SPI) Bits Per Transfer */
+#define     AT91C_SPI_BITS_8     ( ( unsigned int ) 0x0 << 4 )   /* (SPI) 8 Bits Per transfer */
+#define     AT91C_SPI_BITS_9     ( ( unsigned int ) 0x1 << 4 )   /* (SPI) 9 Bits Per transfer */
+#define     AT91C_SPI_BITS_10    ( ( unsigned int ) 0x2 << 4 )   /* (SPI) 10 Bits Per transfer */
+#define     AT91C_SPI_BITS_11    ( ( unsigned int ) 0x3 << 4 )   /* (SPI) 11 Bits Per transfer */
+#define     AT91C_SPI_BITS_12    ( ( unsigned int ) 0x4 << 4 )   /* (SPI) 12 Bits Per transfer */
+#define     AT91C_SPI_BITS_13    ( ( unsigned int ) 0x5 << 4 )   /* (SPI) 13 Bits Per transfer */
+#define     AT91C_SPI_BITS_14    ( ( unsigned int ) 0x6 << 4 )   /* (SPI) 14 Bits Per transfer */
+#define     AT91C_SPI_BITS_15    ( ( unsigned int ) 0x7 << 4 )   /* (SPI) 15 Bits Per transfer */
+#define     AT91C_SPI_BITS_16    ( ( unsigned int ) 0x8 << 4 )   /* (SPI) 16 Bits Per transfer */
+#define AT91C_SPI_SCBR           ( ( unsigned int ) 0xFF << 8 )  /* (SPI) Serial Clock Baud Rate */
+#define AT91C_SPI_DLYBS          ( ( unsigned int ) 0xFF << 16 ) /* (SPI) Delay Before SPCK */
+#define AT91C_SPI_DLYBCT         ( ( unsigned int ) 0xFF << 24 ) /* (SPI) Delay Between Consecutive Transfers */
+
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Usart */
+/* ***************************************************************************** */
+typedef struct _AT91S_USART
+{
+    AT91_REG US_CR;           /* Control Register */
+    AT91_REG US_MR;           /* Mode Register */
+    AT91_REG US_IER;          /* Interrupt Enable Register */
+    AT91_REG US_IDR;          /* Interrupt Disable Register */
+    AT91_REG US_IMR;          /* Interrupt Mask Register */
+    AT91_REG US_CSR;          /* Channel Status Register */
+    AT91_REG US_RHR;          /* Receiver Holding Register */
+    AT91_REG US_THR;          /* Transmitter Holding Register */
+    AT91_REG US_BRGR;         /* Baud Rate Generator Register */
+    AT91_REG US_RTOR;         /* Receiver Time-out Register */
+    AT91_REG US_TTGR;         /* Transmitter Time-guard Register */
+    AT91_REG Reserved0[ 5 ];  /* */
+    AT91_REG US_FIDI;         /* FI_DI_Ratio Register */
+    AT91_REG US_NER;          /* Nb Errors Register */
+    AT91_REG Reserved1[ 1 ];  /* */
+    AT91_REG US_IF;           /* IRDA_FILTER Register */
+    AT91_REG Reserved2[ 44 ]; /* */
+    AT91_REG US_RPR;          /* Receive Pointer Register */
+    AT91_REG US_RCR;          /* Receive Counter Register */
+    AT91_REG US_TPR;          /* Transmit Pointer Register */
+    AT91_REG US_TCR;          /* Transmit Counter Register */
+    AT91_REG US_RNPR;         /* Receive Next Pointer Register */
+    AT91_REG US_RNCR;         /* Receive Next Counter Register */
+    AT91_REG US_TNPR;         /* Transmit Next Pointer Register */
+    AT91_REG US_TNCR;         /* Transmit Next Counter Register */
+    AT91_REG US_PTCR;         /* PDC Transfer Control Register */
+    AT91_REG US_PTSR;         /* PDC Transfer Status Register */
+} AT91S_USART, * AT91PS_USART;
+
+/* -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- */
+#define AT91C_US_STTBRK                  ( ( unsigned int ) 0x1 << 9 )  /* (USART) Start Break */
+#define AT91C_US_STPBRK                  ( ( unsigned int ) 0x1 << 10 ) /* (USART) Stop Break */
+#define AT91C_US_STTTO                   ( ( unsigned int ) 0x1 << 11 ) /* (USART) Start Time-out */
+#define AT91C_US_SENDA                   ( ( unsigned int ) 0x1 << 12 ) /* (USART) Send Address */
+#define AT91C_US_RSTIT                   ( ( unsigned int ) 0x1 << 13 ) /* (USART) Reset Iterations */
+#define AT91C_US_RSTNACK                 ( ( unsigned int ) 0x1 << 14 ) /* (USART) Reset Non Acknowledge */
+#define AT91C_US_RETTO                   ( ( unsigned int ) 0x1 << 15 ) /* (USART) Rearm Time-out */
+#define AT91C_US_DTREN                   ( ( unsigned int ) 0x1 << 16 ) /* (USART) Data Terminal ready Enable */
+#define AT91C_US_DTRDIS                  ( ( unsigned int ) 0x1 << 17 ) /* (USART) Data Terminal ready Disable */
+#define AT91C_US_RTSEN                   ( ( unsigned int ) 0x1 << 18 ) /* (USART) Request to Send enable */
+#define AT91C_US_RTSDIS                  ( ( unsigned int ) 0x1 << 19 ) /* (USART) Request to Send Disable */
+/* -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- */
+#define AT91C_US_USMODE                  ( ( unsigned int ) 0xF << 0 )  /* (USART) Usart mode */
+#define     AT91C_US_USMODE_NORMAL       ( ( unsigned int ) 0x0 )       /* (USART) Normal */
+#define     AT91C_US_USMODE_RS485        ( ( unsigned int ) 0x1 )       /* (USART) RS485 */
+#define     AT91C_US_USMODE_HWHSH        ( ( unsigned int ) 0x2 )       /* (USART) Hardware Handshaking */
+#define     AT91C_US_USMODE_MODEM        ( ( unsigned int ) 0x3 )       /* (USART) Modem */
+#define     AT91C_US_USMODE_ISO7816_0    ( ( unsigned int ) 0x4 )       /* (USART) ISO7816 protocol: T = 0 */
+#define     AT91C_US_USMODE_ISO7816_1    ( ( unsigned int ) 0x6 )       /* (USART) ISO7816 protocol: T = 1 */
+#define     AT91C_US_USMODE_IRDA         ( ( unsigned int ) 0x8 )       /* (USART) IrDA */
+#define     AT91C_US_USMODE_SWHSH        ( ( unsigned int ) 0xC )       /* (USART) Software Handshaking */
+#define AT91C_US_CLKS                    ( ( unsigned int ) 0x3 << 4 )  /* (USART) Clock Selection (Baud Rate generator Input Clock */
+#define     AT91C_US_CLKS_CLOCK          ( ( unsigned int ) 0x0 << 4 )  /* (USART) Clock */
+#define     AT91C_US_CLKS_FDIV1          ( ( unsigned int ) 0x1 << 4 )  /* (USART) fdiv1 */
+#define     AT91C_US_CLKS_SLOW           ( ( unsigned int ) 0x2 << 4 )  /* (USART) slow_clock (ARM) */
+#define     AT91C_US_CLKS_EXT            ( ( unsigned int ) 0x3 << 4 )  /* (USART) External (SCK) */
+#define AT91C_US_CHRL                    ( ( unsigned int ) 0x3 << 6 )  /* (USART) Clock Selection (Baud Rate generator Input Clock */
+#define     AT91C_US_CHRL_5_BITS         ( ( unsigned int ) 0x0 << 6 )  /* (USART) Character Length: 5 bits */
+#define     AT91C_US_CHRL_6_BITS         ( ( unsigned int ) 0x1 << 6 )  /* (USART) Character Length: 6 bits */
+#define     AT91C_US_CHRL_7_BITS         ( ( unsigned int ) 0x2 << 6 )  /* (USART) Character Length: 7 bits */
+#define     AT91C_US_CHRL_8_BITS         ( ( unsigned int ) 0x3 << 6 )  /* (USART) Character Length: 8 bits */
+#define AT91C_US_SYNC                    ( ( unsigned int ) 0x1 << 8 )  /* (USART) Synchronous Mode Select */
+#define AT91C_US_NBSTOP                  ( ( unsigned int ) 0x3 << 12 ) /* (USART) Number of Stop bits */
+#define     AT91C_US_NBSTOP_1_BIT        ( ( unsigned int ) 0x0 << 12 ) /* (USART) 1 stop bit */
+#define     AT91C_US_NBSTOP_15_BIT       ( ( unsigned int ) 0x1 << 12 ) /* (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits */
+#define     AT91C_US_NBSTOP_2_BIT        ( ( unsigned int ) 0x2 << 12 ) /* (USART) 2 stop bits */
+#define AT91C_US_MSBF                    ( ( unsigned int ) 0x1 << 16 ) /* (USART) Bit Order */
+#define AT91C_US_MODE9                   ( ( unsigned int ) 0x1 << 17 ) /* (USART) 9-bit Character length */
+#define AT91C_US_CKLO                    ( ( unsigned int ) 0x1 << 18 ) /* (USART) Clock Output Select */
+#define AT91C_US_OVER                    ( ( unsigned int ) 0x1 << 19 ) /* (USART) Over Sampling Mode */
+#define AT91C_US_INACK                   ( ( unsigned int ) 0x1 << 20 ) /* (USART) Inhibit Non Acknowledge */
+#define AT91C_US_DSNACK                  ( ( unsigned int ) 0x1 << 21 ) /* (USART) Disable Successive NACK */
+#define AT91C_US_MAX_ITER                ( ( unsigned int ) 0x1 << 24 ) /* (USART) Number of Repetitions */
+#define AT91C_US_FILTER                  ( ( unsigned int ) 0x1 << 28 ) /* (USART) Receive Line Filter */
+/* -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- */
+#define AT91C_US_RXBRK                   ( ( unsigned int ) 0x1 << 2 )  /* (USART) Break Received/End of Break */
+#define AT91C_US_TIMEOUT                 ( ( unsigned int ) 0x1 << 8 )  /* (USART) Receiver Time-out */
+#define AT91C_US_ITERATION               ( ( unsigned int ) 0x1 << 10 ) /* (USART) Max number of Repetitions Reached */
+#define AT91C_US_NACK                    ( ( unsigned int ) 0x1 << 13 ) /* (USART) Non Acknowledge */
+#define AT91C_US_RIIC                    ( ( unsigned int ) 0x1 << 16 ) /* (USART) Ring INdicator Input Change Flag */
+#define AT91C_US_DSRIC                   ( ( unsigned int ) 0x1 << 17 ) /* (USART) Data Set Ready Input Change Flag */
+#define AT91C_US_DCDIC                   ( ( unsigned int ) 0x1 << 18 ) /* (USART) Data Carrier Flag */
+#define AT91C_US_CTSIC                   ( ( unsigned int ) 0x1 << 19 ) /* (USART) Clear To Send Input Change Flag */
+/* -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- */
+/* -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- */
+/* -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- */
+#define AT91C_US_RI     ( ( unsigned int ) 0x1 << 20 )   /* (USART) Image of RI Input */
+#define AT91C_US_DSR    ( ( unsigned int ) 0x1 << 21 )   /* (USART) Image of DSR Input */
+#define AT91C_US_DCD    ( ( unsigned int ) 0x1 << 22 )   /* (USART) Image of DCD Input */
+#define AT91C_US_CTS    ( ( unsigned int ) 0x1 << 23 )   /* (USART) Image of CTS Input */
+
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_SSC
+{
+    AT91_REG SSC_CR;          /* Control Register */
+    AT91_REG SSC_CMR;         /* Clock Mode Register */
+    AT91_REG Reserved0[ 2 ];  /* */
+    AT91_REG SSC_RCMR;        /* Receive Clock ModeRegister */
+    AT91_REG SSC_RFMR;        /* Receive Frame Mode Register */
+    AT91_REG SSC_TCMR;        /* Transmit Clock Mode Register */
+    AT91_REG SSC_TFMR;        /* Transmit Frame Mode Register */
+    AT91_REG SSC_RHR;         /* Receive Holding Register */
+    AT91_REG SSC_THR;         /* Transmit Holding Register */
+    AT91_REG Reserved1[ 2 ];  /* */
+    AT91_REG SSC_RSHR;        /* Receive Sync Holding Register */
+    AT91_REG SSC_TSHR;        /* Transmit Sync Holding Register */
+    AT91_REG Reserved2[ 2 ];  /* */
+    AT91_REG SSC_SR;          /* Status Register */
+    AT91_REG SSC_IER;         /* Interrupt Enable Register */
+    AT91_REG SSC_IDR;         /* Interrupt Disable Register */
+    AT91_REG SSC_IMR;         /* Interrupt Mask Register */
+    AT91_REG Reserved3[ 44 ]; /* */
+    AT91_REG SSC_RPR;         /* Receive Pointer Register */
+    AT91_REG SSC_RCR;         /* Receive Counter Register */
+    AT91_REG SSC_TPR;         /* Transmit Pointer Register */
+    AT91_REG SSC_TCR;         /* Transmit Counter Register */
+    AT91_REG SSC_RNPR;        /* Receive Next Pointer Register */
+    AT91_REG SSC_RNCR;        /* Receive Next Counter Register */
+    AT91_REG SSC_TNPR;        /* Transmit Next Pointer Register */
+    AT91_REG SSC_TNCR;        /* Transmit Next Counter Register */
+    AT91_REG SSC_PTCR;        /* PDC Transfer Control Register */
+    AT91_REG SSC_PTSR;        /* PDC Transfer Status Register */
+} AT91S_SSC, * AT91PS_SSC;
+
+/* -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- */
+#define AT91C_SSC_RXEN                    ( ( unsigned int ) 0x1 << 0 )   /* (SSC) Receive Enable */
+#define AT91C_SSC_RXDIS                   ( ( unsigned int ) 0x1 << 1 )   /* (SSC) Receive Disable */
+#define AT91C_SSC_TXEN                    ( ( unsigned int ) 0x1 << 8 )   /* (SSC) Transmit Enable */
+#define AT91C_SSC_TXDIS                   ( ( unsigned int ) 0x1 << 9 )   /* (SSC) Transmit Disable */
+#define AT91C_SSC_SWRST                   ( ( unsigned int ) 0x1 << 15 )  /* (SSC) Software Reset */
+/* -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- */
+#define AT91C_SSC_CKS                     ( ( unsigned int ) 0x3 << 0 )   /* (SSC) Receive/Transmit Clock Selection */
+#define     AT91C_SSC_CKS_DIV             ( ( unsigned int ) 0x0 )        /* (SSC) Divided Clock */
+#define     AT91C_SSC_CKS_TK              ( ( unsigned int ) 0x1 )        /* (SSC) TK Clock signal */
+#define     AT91C_SSC_CKS_RK              ( ( unsigned int ) 0x2 )        /* (SSC) RK pin */
+#define AT91C_SSC_CKO                     ( ( unsigned int ) 0x7 << 2 )   /* (SSC) Receive/Transmit Clock Output Mode Selection */
+#define     AT91C_SSC_CKO_NONE            ( ( unsigned int ) 0x0 << 2 )   /* (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only */
+#define     AT91C_SSC_CKO_CONTINUOUS      ( ( unsigned int ) 0x1 << 2 )   /* (SSC) Continuous Receive/Transmit Clock RK pin: Output */
+#define     AT91C_SSC_CKO_DATA_TX         ( ( unsigned int ) 0x2 << 2 )   /* (SSC) Receive/Transmit Clock only during data transfers RK pin: Output */
+#define AT91C_SSC_CKI                     ( ( unsigned int ) 0x1 << 5 )   /* (SSC) Receive/Transmit Clock Inversion */
+#define AT91C_SSC_START                   ( ( unsigned int ) 0xF << 8 )   /* (SSC) Receive/Transmit Start Selection */
+#define     AT91C_SSC_START_CONTINUOUS    ( ( unsigned int ) 0x0 << 8 )   /* (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */
+#define     AT91C_SSC_START_TX            ( ( unsigned int ) 0x1 << 8 )   /* (SSC) Transmit/Receive start */
+#define     AT91C_SSC_START_LOW_RF        ( ( unsigned int ) 0x2 << 8 )   /* (SSC) Detection of a low level on RF input */
+#define     AT91C_SSC_START_HIGH_RF       ( ( unsigned int ) 0x3 << 8 )   /* (SSC) Detection of a high level on RF input */
+#define     AT91C_SSC_START_FALL_RF       ( ( unsigned int ) 0x4 << 8 )   /* (SSC) Detection of a falling edge on RF input */
+#define     AT91C_SSC_START_RISE_RF       ( ( unsigned int ) 0x5 << 8 )   /* (SSC) Detection of a rising edge on RF input */
+#define     AT91C_SSC_START_LEVEL_RF      ( ( unsigned int ) 0x6 << 8 )   /* (SSC) Detection of any level change on RF input */
+#define     AT91C_SSC_START_EDGE_RF       ( ( unsigned int ) 0x7 << 8 )   /* (SSC) Detection of any edge on RF input */
+#define     AT91C_SSC_START_0             ( ( unsigned int ) 0x8 << 8 )   /* (SSC) Compare 0 */
+#define AT91C_SSC_STTDLY                  ( ( unsigned int ) 0xFF << 16 ) /* (SSC) Receive/Transmit Start Delay */
+#define AT91C_SSC_PERIOD                  ( ( unsigned int ) 0xFF << 24 ) /* (SSC) Receive/Transmit Period Divider Selection */
+/* -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- */
+#define AT91C_SSC_DATLEN                  ( ( unsigned int ) 0x1F << 0 )  /* (SSC) Data Length */
+#define AT91C_SSC_LOOP                    ( ( unsigned int ) 0x1 << 5 )   /* (SSC) Loop Mode */
+#define AT91C_SSC_MSBF                    ( ( unsigned int ) 0x1 << 7 )   /* (SSC) Most Significant Bit First */
+#define AT91C_SSC_DATNB                   ( ( unsigned int ) 0xF << 8 )   /* (SSC) Data Number per Frame */
+#define AT91C_SSC_FSLEN                   ( ( unsigned int ) 0xF << 16 )  /* (SSC) Receive/Transmit Frame Sync length */
+#define AT91C_SSC_FSOS                    ( ( unsigned int ) 0x7 << 20 )  /* (SSC) Receive/Transmit Frame Sync Output Selection */
+#define     AT91C_SSC_FSOS_NONE           ( ( unsigned int ) 0x0 << 20 )  /* (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only */
+#define     AT91C_SSC_FSOS_NEGATIVE       ( ( unsigned int ) 0x1 << 20 )  /* (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse */
+#define     AT91C_SSC_FSOS_POSITIVE       ( ( unsigned int ) 0x2 << 20 )  /* (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse */
+#define     AT91C_SSC_FSOS_LOW            ( ( unsigned int ) 0x3 << 20 )  /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer */
+#define     AT91C_SSC_FSOS_HIGH           ( ( unsigned int ) 0x4 << 20 )  /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer */
+#define     AT91C_SSC_FSOS_TOGGLE         ( ( unsigned int ) 0x5 << 20 )  /* (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer */
+#define AT91C_SSC_FSEDGE                  ( ( unsigned int ) 0x1 << 24 )  /* (SSC) Frame Sync Edge Detection */
+/* -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- */
+/* -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- */
+#define AT91C_SSC_DATDEF                  ( ( unsigned int ) 0x1 << 5 )  /* (SSC) Data Default Value */
+#define AT91C_SSC_FSDEN                   ( ( unsigned int ) 0x1 << 23 ) /* (SSC) Frame Sync Data Enable */
+/* -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- */
+#define AT91C_SSC_TXRDY                   ( ( unsigned int ) 0x1 << 0 )  /* (SSC) Transmit Ready */
+#define AT91C_SSC_TXEMPTY                 ( ( unsigned int ) 0x1 << 1 )  /* (SSC) Transmit Empty */
+#define AT91C_SSC_ENDTX                   ( ( unsigned int ) 0x1 << 2 )  /* (SSC) End Of Transmission */
+#define AT91C_SSC_TXBUFE                  ( ( unsigned int ) 0x1 << 3 )  /* (SSC) Transmit Buffer Empty */
+#define AT91C_SSC_RXRDY                   ( ( unsigned int ) 0x1 << 4 )  /* (SSC) Receive Ready */
+#define AT91C_SSC_OVRUN                   ( ( unsigned int ) 0x1 << 5 )  /* (SSC) Receive Overrun */
+#define AT91C_SSC_ENDRX                   ( ( unsigned int ) 0x1 << 6 )  /* (SSC) End of Reception */
+#define AT91C_SSC_RXBUFF                  ( ( unsigned int ) 0x1 << 7 )  /* (SSC) Receive Buffer Full */
+#define AT91C_SSC_TXSYN                   ( ( unsigned int ) 0x1 << 10 ) /* (SSC) Transmit Sync */
+#define AT91C_SSC_RXSYN                   ( ( unsigned int ) 0x1 << 11 ) /* (SSC) Receive Sync */
+#define AT91C_SSC_TXENA                   ( ( unsigned int ) 0x1 << 16 ) /* (SSC) Transmit Enable */
+#define AT91C_SSC_RXENA                   ( ( unsigned int ) 0x1 << 17 ) /* (SSC) Receive Enable */
+/* -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- */
+/* -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- */
+/* -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- */
+
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Two-wire Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_TWI
+{
+    AT91_REG TWI_CR;         /* Control Register */
+    AT91_REG TWI_MMR;        /* Master Mode Register */
+    AT91_REG Reserved0[ 1 ]; /* */
+    AT91_REG TWI_IADR;       /* Internal Address Register */
+    AT91_REG TWI_CWGR;       /* Clock Waveform Generator Register */
+    AT91_REG Reserved1[ 3 ]; /* */
+    AT91_REG TWI_SR;         /* Status Register */
+    AT91_REG TWI_IER;        /* Interrupt Enable Register */
+    AT91_REG TWI_IDR;        /* Interrupt Disable Register */
+    AT91_REG TWI_IMR;        /* Interrupt Mask Register */
+    AT91_REG TWI_RHR;        /* Receive Holding Register */
+    AT91_REG TWI_THR;        /* Transmit Holding Register */
+} AT91S_TWI, * AT91PS_TWI;
+
+/* -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- */
+#define AT91C_TWI_START                ( ( unsigned int ) 0x1 << 0 )   /* (TWI) Send a START Condition */
+#define AT91C_TWI_STOP                 ( ( unsigned int ) 0x1 << 1 )   /* (TWI) Send a STOP Condition */
+#define AT91C_TWI_MSEN                 ( ( unsigned int ) 0x1 << 2 )   /* (TWI) TWI Master Transfer Enabled */
+#define AT91C_TWI_MSDIS                ( ( unsigned int ) 0x1 << 3 )   /* (TWI) TWI Master Transfer Disabled */
+#define AT91C_TWI_SWRST                ( ( unsigned int ) 0x1 << 7 )   /* (TWI) Software Reset */
+/* -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- */
+#define AT91C_TWI_IADRSZ               ( ( unsigned int ) 0x3 << 8 )   /* (TWI) Internal Device Address Size */
+#define     AT91C_TWI_IADRSZ_NO        ( ( unsigned int ) 0x0 << 8 )   /* (TWI) No internal device address */
+#define     AT91C_TWI_IADRSZ_1_BYTE    ( ( unsigned int ) 0x1 << 8 )   /* (TWI) One-byte internal device address */
+#define     AT91C_TWI_IADRSZ_2_BYTE    ( ( unsigned int ) 0x2 << 8 )   /* (TWI) Two-byte internal device address */
+#define     AT91C_TWI_IADRSZ_3_BYTE    ( ( unsigned int ) 0x3 << 8 )   /* (TWI) Three-byte internal device address */
+#define AT91C_TWI_MREAD                ( ( unsigned int ) 0x1 << 12 )  /* (TWI) Master Read Direction */
+#define AT91C_TWI_DADR                 ( ( unsigned int ) 0x7F << 16 ) /* (TWI) Device Address */
+/* -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- */
+#define AT91C_TWI_CLDIV                ( ( unsigned int ) 0xFF << 0 )  /* (TWI) Clock Low Divider */
+#define AT91C_TWI_CHDIV                ( ( unsigned int ) 0xFF << 8 )  /* (TWI) Clock High Divider */
+#define AT91C_TWI_CKDIV                ( ( unsigned int ) 0x7 << 16 )  /* (TWI) Clock Divider */
+/* -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- */
+#define AT91C_TWI_TXCOMP               ( ( unsigned int ) 0x1 << 0 )   /* (TWI) Transmission Completed */
+#define AT91C_TWI_RXRDY                ( ( unsigned int ) 0x1 << 1 )   /* (TWI) Receive holding register ReaDY */
+#define AT91C_TWI_TXRDY                ( ( unsigned int ) 0x1 << 2 )   /* (TWI) Transmit holding register ReaDY */
+#define AT91C_TWI_OVRE                 ( ( unsigned int ) 0x1 << 6 )   /* (TWI) Overrun Error */
+#define AT91C_TWI_UNRE                 ( ( unsigned int ) 0x1 << 7 )   /* (TWI) Underrun Error */
+#define AT91C_TWI_NACK                 ( ( unsigned int ) 0x1 << 8 )   /* (TWI) Not Acknowledged */
+/* -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- */
+/* -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- */
+/* -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- */
+
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR PWMC Channel Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_PWMC_CH
+{
+    AT91_REG PWMC_CMR;           /* Channel Mode Register */
+    AT91_REG PWMC_CDTYR;         /* Channel Duty Cycle Register */
+    AT91_REG PWMC_CPRDR;         /* Channel Period Register */
+    AT91_REG PWMC_CCNTR;         /* Channel Counter Register */
+    AT91_REG PWMC_CUPDR;         /* Channel Update Register */
+    AT91_REG PWMC_Reserved[ 3 ]; /* Reserved */
+} AT91S_PWMC_CH, * AT91PS_PWMC_CH;
+
+/* -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- */
+#define AT91C_PWMC_CPRE             ( ( unsigned int ) 0xF << 0 )  /* (PWMC_CH) Channel Pre-scaler : PWMC_CLKx */
+#define     AT91C_PWMC_CPRE_MCK     ( ( unsigned int ) 0x0 )       /* (PWMC_CH) */
+#define     AT91C_PWMC_CPRE_MCKA    ( ( unsigned int ) 0xB )       /* (PWMC_CH) */
+#define     AT91C_PWMC_CPRE_MCKB    ( ( unsigned int ) 0xC )       /* (PWMC_CH) */
+#define AT91C_PWMC_CALG             ( ( unsigned int ) 0x1 << 8 )  /* (PWMC_CH) Channel Alignment */
+#define AT91C_PWMC_CPOL             ( ( unsigned int ) 0x1 << 9 )  /* (PWMC_CH) Channel Polarity */
+#define AT91C_PWMC_CPD              ( ( unsigned int ) 0x1 << 10 ) /* (PWMC_CH) Channel Update Period */
+/* -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- */
+#define AT91C_PWMC_CDTY             ( ( unsigned int ) 0x0 << 0 )  /* (PWMC_CH) Channel Duty Cycle */
+/* -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- */
+#define AT91C_PWMC_CPRD             ( ( unsigned int ) 0x0 << 0 )  /* (PWMC_CH) Channel Period */
+/* -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- */
+#define AT91C_PWMC_CCNT             ( ( unsigned int ) 0x0 << 0 )  /* (PWMC_CH) Channel Counter */
+/* -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- */
+#define AT91C_PWMC_CUPD             ( ( unsigned int ) 0x0 << 0 )  /* (PWMC_CH) Channel Update */
+
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_PWMC
+{
+    AT91_REG PWMC_MR;           /* PWMC Mode Register */
+    AT91_REG PWMC_ENA;          /* PWMC Enable Register */
+    AT91_REG PWMC_DIS;          /* PWMC Disable Register */
+    AT91_REG PWMC_SR;           /* PWMC Status Register */
+    AT91_REG PWMC_IER;          /* PWMC Interrupt Enable Register */
+    AT91_REG PWMC_IDR;          /* PWMC Interrupt Disable Register */
+    AT91_REG PWMC_IMR;          /* PWMC Interrupt Mask Register */
+    AT91_REG PWMC_ISR;          /* PWMC Interrupt Status Register */
+    AT91_REG Reserved0[ 55 ];   /* */
+    AT91_REG PWMC_VR;           /* PWMC Version Register */
+    AT91_REG Reserved1[ 64 ];   /* */
+    AT91S_PWMC_CH PWMC_CH[ 4 ]; /* PWMC Channel */
+} AT91S_PWMC, * AT91PS_PWMC;
+
+/* -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- */
+#define AT91C_PWMC_DIVA            ( ( unsigned int ) 0xFF << 0 )  /* (PWMC) CLKA divide factor. */
+#define AT91C_PWMC_PREA            ( ( unsigned int ) 0xF << 8 )   /* (PWMC) Divider Input Clock Prescaler A */
+#define     AT91C_PWMC_PREA_MCK    ( ( unsigned int ) 0x0 << 8 )   /* (PWMC) */
+#define AT91C_PWMC_DIVB            ( ( unsigned int ) 0xFF << 16 ) /* (PWMC) CLKB divide factor. */
+#define AT91C_PWMC_PREB            ( ( unsigned int ) 0xF << 24 )  /* (PWMC) Divider Input Clock Prescaler B */
+#define     AT91C_PWMC_PREB_MCK    ( ( unsigned int ) 0x0 << 24 )  /* (PWMC) */
+/* -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- */
+#define AT91C_PWMC_CHID0           ( ( unsigned int ) 0x1 << 0 )   /* (PWMC) Channel ID 0 */
+#define AT91C_PWMC_CHID1           ( ( unsigned int ) 0x1 << 1 )   /* (PWMC) Channel ID 1 */
+#define AT91C_PWMC_CHID2           ( ( unsigned int ) 0x1 << 2 )   /* (PWMC) Channel ID 2 */
+#define AT91C_PWMC_CHID3           ( ( unsigned int ) 0x1 << 3 )   /* (PWMC) Channel ID 3 */
+/* -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- */
+/* -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- */
+/* -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- */
+/* -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- */
+/* -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- */
+/* -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- */
+
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR USB Device Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_UDP
+{
+    AT91_REG UDP_NUM;        /* Frame Number Register */
+    AT91_REG UDP_GLBSTATE;   /* Global State Register */
+    AT91_REG UDP_FADDR;      /* Function Address Register */
+    AT91_REG Reserved0[ 1 ]; /* */
+    AT91_REG UDP_IER;        /* Interrupt Enable Register */
+    AT91_REG UDP_IDR;        /* Interrupt Disable Register */
+    AT91_REG UDP_IMR;        /* Interrupt Mask Register */
+    AT91_REG UDP_ISR;        /* Interrupt Status Register */
+    AT91_REG UDP_ICR;        /* Interrupt Clear Register */
+    AT91_REG Reserved1[ 1 ]; /* */
+    AT91_REG UDP_RSTEP;      /* Reset Endpoint Register */
+    AT91_REG Reserved2[ 1 ]; /* */
+    AT91_REG UDP_CSR[ 6 ];   /* Endpoint Control and Status Register */
+    AT91_REG Reserved3[ 2 ]; /* */
+    AT91_REG UDP_FDR[ 6 ];   /* Endpoint FIFO Data Register */
+    AT91_REG Reserved4[ 3 ]; /* */
+    AT91_REG UDP_TXVC;       /* Transceiver Control Register */
+} AT91S_UDP, * AT91PS_UDP;
+
+/* -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- */
+#define AT91C_UDP_FRM_NUM    ( ( unsigned int ) 0x7FF << 0 ) /* (UDP) Frame Number as Defined in the Packet Field Formats */
+#define AT91C_UDP_FRM_ERR    ( ( unsigned int ) 0x1 << 16 )  /* (UDP) Frame Error */
+#define AT91C_UDP_FRM_OK     ( ( unsigned int ) 0x1 << 17 )  /* (UDP) Frame OK */
+/* -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- */
+#define AT91C_UDP_FADDEN     ( ( unsigned int ) 0x1 << 0 )   /* (UDP) Function Address Enable */
+#define AT91C_UDP_CONFG      ( ( unsigned int ) 0x1 << 1 )   /* (UDP) Configured */
+#define AT91C_UDP_ESR        ( ( unsigned int ) 0x1 << 2 )   /* (UDP) Enable Send Resume */
+#define AT91C_UDP_RSMINPR    ( ( unsigned int ) 0x1 << 3 )   /* (UDP) A Resume Has Been Sent to the Host */
+#define AT91C_UDP_RMWUPE     ( ( unsigned int ) 0x1 << 4 )   /* (UDP) Remote Wake Up Enable */
+/* -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- */
+#define AT91C_UDP_FADD       ( ( unsigned int ) 0xFF << 0 )  /* (UDP) Function Address Value */
+#define AT91C_UDP_FEN        ( ( unsigned int ) 0x1 << 8 )   /* (UDP) Function Enable */
+/* -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- */
+#define AT91C_UDP_EPINT0     ( ( unsigned int ) 0x1 << 0 )   /* (UDP) Endpoint 0 Interrupt */
+#define AT91C_UDP_EPINT1     ( ( unsigned int ) 0x1 << 1 )   /* (UDP) Endpoint 0 Interrupt */
+#define AT91C_UDP_EPINT2     ( ( unsigned int ) 0x1 << 2 )   /* (UDP) Endpoint 2 Interrupt */
+#define AT91C_UDP_EPINT3     ( ( unsigned int ) 0x1 << 3 )   /* (UDP) Endpoint 3 Interrupt */
+#define AT91C_UDP_EPINT4     ( ( unsigned int ) 0x1 << 4 )   /* (UDP) Endpoint 4 Interrupt */
+#define AT91C_UDP_EPINT5     ( ( unsigned int ) 0x1 << 5 )   /* (UDP) Endpoint 5 Interrupt */
+#define AT91C_UDP_RXSUSP     ( ( unsigned int ) 0x1 << 8 )   /* (UDP) USB Suspend Interrupt */
+#define AT91C_UDP_RXRSM      ( ( unsigned int ) 0x1 << 9 )   /* (UDP) USB Resume Interrupt */
+#define AT91C_UDP_EXTRSM     ( ( unsigned int ) 0x1 << 10 )  /* (UDP) USB External Resume Interrupt */
+#define AT91C_UDP_SOFINT     ( ( unsigned int ) 0x1 << 11 )  /* (UDP) USB Start Of frame Interrupt */
+#define AT91C_UDP_WAKEUP     ( ( unsigned int ) 0x1 << 13 )  /* (UDP) USB Resume Interrupt */
+/* -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- */
+/* -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- */
+/* -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- */
+#define AT91C_UDP_ENDBUSRES              ( ( unsigned int ) 0x1 << 12 ) /* (UDP) USB End Of Bus Reset Interrupt */
+/* -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- */
+/* -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- */
+#define AT91C_UDP_EP0                    ( ( unsigned int ) 0x1 << 0 )    /* (UDP) Reset Endpoint 0 */
+#define AT91C_UDP_EP1                    ( ( unsigned int ) 0x1 << 1 )    /* (UDP) Reset Endpoint 1 */
+#define AT91C_UDP_EP2                    ( ( unsigned int ) 0x1 << 2 )    /* (UDP) Reset Endpoint 2 */
+#define AT91C_UDP_EP3                    ( ( unsigned int ) 0x1 << 3 )    /* (UDP) Reset Endpoint 3 */
+#define AT91C_UDP_EP4                    ( ( unsigned int ) 0x1 << 4 )    /* (UDP) Reset Endpoint 4 */
+#define AT91C_UDP_EP5                    ( ( unsigned int ) 0x1 << 5 )    /* (UDP) Reset Endpoint 5 */
+/* -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- */
+#define AT91C_UDP_TXCOMP                 ( ( unsigned int ) 0x1 << 0 )    /* (UDP) Generates an IN packet with data previously written in the DPR */
+#define AT91C_UDP_RX_DATA_BK0            ( ( unsigned int ) 0x1 << 1 )    /* (UDP) Receive Data Bank 0 */
+#define AT91C_UDP_RXSETUP                ( ( unsigned int ) 0x1 << 2 )    /* (UDP) Sends STALL to the Host (Control endpoints) */
+#define AT91C_UDP_ISOERROR               ( ( unsigned int ) 0x1 << 3 )    /* (UDP) Isochronous error (Isochronous endpoints) */
+#define AT91C_UDP_TXPKTRDY               ( ( unsigned int ) 0x1 << 4 )    /* (UDP) Transmit Packet Ready */
+#define AT91C_UDP_FORCESTALL             ( ( unsigned int ) 0x1 << 5 )    /* (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). */
+#define AT91C_UDP_RX_DATA_BK1            ( ( unsigned int ) 0x1 << 6 )    /* (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). */
+#define AT91C_UDP_DIR                    ( ( unsigned int ) 0x1 << 7 )    /* (UDP) Transfer Direction */
+#define AT91C_UDP_EPTYPE                 ( ( unsigned int ) 0x7 << 8 )    /* (UDP) Endpoint type */
+#define     AT91C_UDP_EPTYPE_CTRL        ( ( unsigned int ) 0x0 << 8 )    /* (UDP) Control */
+#define     AT91C_UDP_EPTYPE_ISO_OUT     ( ( unsigned int ) 0x1 << 8 )    /* (UDP) Isochronous OUT */
+#define     AT91C_UDP_EPTYPE_BULK_OUT    ( ( unsigned int ) 0x2 << 8 )    /* (UDP) Bulk OUT */
+#define     AT91C_UDP_EPTYPE_INT_OUT     ( ( unsigned int ) 0x3 << 8 )    /* (UDP) Interrupt OUT */
+#define     AT91C_UDP_EPTYPE_ISO_IN      ( ( unsigned int ) 0x5 << 8 )    /* (UDP) Isochronous IN */
+#define     AT91C_UDP_EPTYPE_BULK_IN     ( ( unsigned int ) 0x6 << 8 )    /* (UDP) Bulk IN */
+#define     AT91C_UDP_EPTYPE_INT_IN      ( ( unsigned int ) 0x7 << 8 )    /* (UDP) Interrupt IN */
+#define AT91C_UDP_DTGLE                  ( ( unsigned int ) 0x1 << 11 )   /* (UDP) Data Toggle */
+#define AT91C_UDP_EPEDS                  ( ( unsigned int ) 0x1 << 15 )   /* (UDP) Endpoint Enable Disable */
+#define AT91C_UDP_RXBYTECNT              ( ( unsigned int ) 0x7FF << 16 ) /* (UDP) Number Of Bytes Available in the FIFO */
+/* -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- */
+#define AT91C_UDP_TXVDIS                 ( ( unsigned int ) 0x1 << 8 )    /* (UDP) */
+#define AT91C_UDP_PUON                   ( ( unsigned int ) 0x1 << 9 )    /* (UDP) Pull-up ON */
+
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_TC
+{
+    AT91_REG TC_CCR;         /* Channel Control Register */
+    AT91_REG TC_CMR;         /* Channel Mode Register (Capture Mode / Waveform Mode) */
+    AT91_REG Reserved0[ 2 ]; /* */
+    AT91_REG TC_CV;          /* Counter Value */
+    AT91_REG TC_RA;          /* Register A */
+    AT91_REG TC_RB;          /* Register B */
+    AT91_REG TC_RC;          /* Register C */
+    AT91_REG TC_SR;          /* Status Register */
+    AT91_REG TC_IER;         /* Interrupt Enable Register */
+    AT91_REG TC_IDR;         /* Interrupt Disable Register */
+    AT91_REG TC_IMR;         /* Interrupt Mask Register */
+} AT91S_TC, * AT91PS_TC;
+
+/* -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- */
+#define AT91C_TC_CLKEN                        ( ( unsigned int ) 0x1 << 0 )  /* (TC) Counter Clock Enable Command */
+#define AT91C_TC_CLKDIS                       ( ( unsigned int ) 0x1 << 1 )  /* (TC) Counter Clock Disable Command */
+#define AT91C_TC_SWTRG                        ( ( unsigned int ) 0x1 << 2 )  /* (TC) Software Trigger Command */
+/* -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- */
+#define AT91C_TC_CLKS                         ( ( unsigned int ) 0x7 << 0 )  /* (TC) Clock Selection */
+#define     AT91C_TC_CLKS_TIMER_DIV1_CLOCK    ( ( unsigned int ) 0x0 )       /* (TC) Clock selected: TIMER_DIV1_CLOCK */
+#define     AT91C_TC_CLKS_TIMER_DIV2_CLOCK    ( ( unsigned int ) 0x1 )       /* (TC) Clock selected: TIMER_DIV2_CLOCK */
+#define     AT91C_TC_CLKS_TIMER_DIV3_CLOCK    ( ( unsigned int ) 0x2 )       /* (TC) Clock selected: TIMER_DIV3_CLOCK */
+#define     AT91C_TC_CLKS_TIMER_DIV4_CLOCK    ( ( unsigned int ) 0x3 )       /* (TC) Clock selected: TIMER_DIV4_CLOCK */
+#define     AT91C_TC_CLKS_TIMER_DIV5_CLOCK    ( ( unsigned int ) 0x4 )       /* (TC) Clock selected: TIMER_DIV5_CLOCK */
+#define     AT91C_TC_CLKS_XC0                 ( ( unsigned int ) 0x5 )       /* (TC) Clock selected: XC0 */
+#define     AT91C_TC_CLKS_XC1                 ( ( unsigned int ) 0x6 )       /* (TC) Clock selected: XC1 */
+#define     AT91C_TC_CLKS_XC2                 ( ( unsigned int ) 0x7 )       /* (TC) Clock selected: XC2 */
+#define AT91C_TC_CLKI                         ( ( unsigned int ) 0x1 << 3 )  /* (TC) Clock Invert */
+#define AT91C_TC_BURST                        ( ( unsigned int ) 0x3 << 4 )  /* (TC) Burst Signal Selection */
+#define     AT91C_TC_BURST_NONE               ( ( unsigned int ) 0x0 << 4 )  /* (TC) The clock is not gated by an external signal */
+#define     AT91C_TC_BURST_XC0                ( ( unsigned int ) 0x1 << 4 )  /* (TC) XC0 is ANDed with the selected clock */
+#define     AT91C_TC_BURST_XC1                ( ( unsigned int ) 0x2 << 4 )  /* (TC) XC1 is ANDed with the selected clock */
+#define     AT91C_TC_BURST_XC2                ( ( unsigned int ) 0x3 << 4 )  /* (TC) XC2 is ANDed with the selected clock */
+#define AT91C_TC_CPCSTOP                      ( ( unsigned int ) 0x1 << 6 )  /* (TC) Counter Clock Stopped with RC Compare */
+#define AT91C_TC_LDBSTOP                      ( ( unsigned int ) 0x1 << 6 )  /* (TC) Counter Clock Stopped with RB Loading */
+#define AT91C_TC_CPCDIS                       ( ( unsigned int ) 0x1 << 7 )  /* (TC) Counter Clock Disable with RC Compare */
+#define AT91C_TC_LDBDIS                       ( ( unsigned int ) 0x1 << 7 )  /* (TC) Counter Clock Disabled with RB Loading */
+#define AT91C_TC_ETRGEDG                      ( ( unsigned int ) 0x3 << 8 )  /* (TC) External Trigger Edge Selection */
+#define     AT91C_TC_ETRGEDG_NONE             ( ( unsigned int ) 0x0 << 8 )  /* (TC) Edge: None */
+#define     AT91C_TC_ETRGEDG_RISING           ( ( unsigned int ) 0x1 << 8 )  /* (TC) Edge: rising edge */
+#define     AT91C_TC_ETRGEDG_FALLING          ( ( unsigned int ) 0x2 << 8 )  /* (TC) Edge: falling edge */
+#define     AT91C_TC_ETRGEDG_BOTH             ( ( unsigned int ) 0x3 << 8 )  /* (TC) Edge: each edge */
+#define AT91C_TC_EEVTEDG                      ( ( unsigned int ) 0x3 << 8 )  /* (TC) External Event Edge Selection */
+#define     AT91C_TC_EEVTEDG_NONE             ( ( unsigned int ) 0x0 << 8 )  /* (TC) Edge: None */
+#define     AT91C_TC_EEVTEDG_RISING           ( ( unsigned int ) 0x1 << 8 )  /* (TC) Edge: rising edge */
+#define     AT91C_TC_EEVTEDG_FALLING          ( ( unsigned int ) 0x2 << 8 )  /* (TC) Edge: falling edge */
+#define     AT91C_TC_EEVTEDG_BOTH             ( ( unsigned int ) 0x3 << 8 )  /* (TC) Edge: each edge */
+#define AT91C_TC_EEVT                         ( ( unsigned int ) 0x3 << 10 ) /* (TC) External Event  Selection */
+#define     AT91C_TC_EEVT_TIOB                ( ( unsigned int ) 0x0 << 10 ) /* (TC) Signal selected as external event: TIOB TIOB direction: input */
+#define     AT91C_TC_EEVT_XC0                 ( ( unsigned int ) 0x1 << 10 ) /* (TC) Signal selected as external event: XC0 TIOB direction: output */
+#define     AT91C_TC_EEVT_XC1                 ( ( unsigned int ) 0x2 << 10 ) /* (TC) Signal selected as external event: XC1 TIOB direction: output */
+#define     AT91C_TC_EEVT_XC2                 ( ( unsigned int ) 0x3 << 10 ) /* (TC) Signal selected as external event: XC2 TIOB direction: output */
+#define AT91C_TC_ABETRG                       ( ( unsigned int ) 0x1 << 10 ) /* (TC) TIOA or TIOB External Trigger Selection */
+#define AT91C_TC_ENETRG                       ( ( unsigned int ) 0x1 << 12 ) /* (TC) External Event Trigger enable */
+#define AT91C_TC_WAVESEL                      ( ( unsigned int ) 0x3 << 13 ) /* (TC) Waveform  Selection */
+#define     AT91C_TC_WAVESEL_UP               ( ( unsigned int ) 0x0 << 13 ) /* (TC) UP mode without atomatic trigger on RC Compare */
+#define     AT91C_TC_WAVESEL_UPDOWN           ( ( unsigned int ) 0x1 << 13 ) /* (TC) UPDOWN mode without automatic trigger on RC Compare */
+#define     AT91C_TC_WAVESEL_UP_AUTO          ( ( unsigned int ) 0x2 << 13 ) /* (TC) UP mode with automatic trigger on RC Compare */
+#define     AT91C_TC_WAVESEL_UPDOWN_AUTO      ( ( unsigned int ) 0x3 << 13 ) /* (TC) UPDOWN mode with automatic trigger on RC Compare */
+#define AT91C_TC_CPCTRG                       ( ( unsigned int ) 0x1 << 14 ) /* (TC) RC Compare Trigger Enable */
+#define AT91C_TC_WAVE                         ( ( unsigned int ) 0x1 << 15 ) /* (TC) */
+#define AT91C_TC_ACPA                         ( ( unsigned int ) 0x3 << 16 ) /* (TC) RA Compare Effect on TIOA */
+#define     AT91C_TC_ACPA_NONE                ( ( unsigned int ) 0x0 << 16 ) /* (TC) Effect: none */
+#define     AT91C_TC_ACPA_SET                 ( ( unsigned int ) 0x1 << 16 ) /* (TC) Effect: set */
+#define     AT91C_TC_ACPA_CLEAR               ( ( unsigned int ) 0x2 << 16 ) /* (TC) Effect: clear */
+#define     AT91C_TC_ACPA_TOGGLE              ( ( unsigned int ) 0x3 << 16 ) /* (TC) Effect: toggle */
+#define AT91C_TC_LDRA                         ( ( unsigned int ) 0x3 << 16 ) /* (TC) RA Loading Selection */
+#define     AT91C_TC_LDRA_NONE                ( ( unsigned int ) 0x0 << 16 ) /* (TC) Edge: None */
+#define     AT91C_TC_LDRA_RISING              ( ( unsigned int ) 0x1 << 16 ) /* (TC) Edge: rising edge of TIOA */
+#define     AT91C_TC_LDRA_FALLING             ( ( unsigned int ) 0x2 << 16 ) /* (TC) Edge: falling edge of TIOA */
+#define     AT91C_TC_LDRA_BOTH                ( ( unsigned int ) 0x3 << 16 ) /* (TC) Edge: each edge of TIOA */
+#define AT91C_TC_ACPC                         ( ( unsigned int ) 0x3 << 18 ) /* (TC) RC Compare Effect on TIOA */
+#define     AT91C_TC_ACPC_NONE                ( ( unsigned int ) 0x0 << 18 ) /* (TC) Effect: none */
+#define     AT91C_TC_ACPC_SET                 ( ( unsigned int ) 0x1 << 18 ) /* (TC) Effect: set */
+#define     AT91C_TC_ACPC_CLEAR               ( ( unsigned int ) 0x2 << 18 ) /* (TC) Effect: clear */
+#define     AT91C_TC_ACPC_TOGGLE              ( ( unsigned int ) 0x3 << 18 ) /* (TC) Effect: toggle */
+#define AT91C_TC_LDRB                         ( ( unsigned int ) 0x3 << 18 ) /* (TC) RB Loading Selection */
+#define     AT91C_TC_LDRB_NONE                ( ( unsigned int ) 0x0 << 18 ) /* (TC) Edge: None */
+#define     AT91C_TC_LDRB_RISING              ( ( unsigned int ) 0x1 << 18 ) /* (TC) Edge: rising edge of TIOA */
+#define     AT91C_TC_LDRB_FALLING             ( ( unsigned int ) 0x2 << 18 ) /* (TC) Edge: falling edge of TIOA */
+#define     AT91C_TC_LDRB_BOTH                ( ( unsigned int ) 0x3 << 18 ) /* (TC) Edge: each edge of TIOA */
+#define AT91C_TC_AEEVT                        ( ( unsigned int ) 0x3 << 20 ) /* (TC) External Event Effect on TIOA */
+#define     AT91C_TC_AEEVT_NONE               ( ( unsigned int ) 0x0 << 20 ) /* (TC) Effect: none */
+#define     AT91C_TC_AEEVT_SET                ( ( unsigned int ) 0x1 << 20 ) /* (TC) Effect: set */
+#define     AT91C_TC_AEEVT_CLEAR              ( ( unsigned int ) 0x2 << 20 ) /* (TC) Effect: clear */
+#define     AT91C_TC_AEEVT_TOGGLE             ( ( unsigned int ) 0x3 << 20 ) /* (TC) Effect: toggle */
+#define AT91C_TC_ASWTRG                       ( ( unsigned int ) 0x3 << 22 ) /* (TC) Software Trigger Effect on TIOA */
+#define     AT91C_TC_ASWTRG_NONE              ( ( unsigned int ) 0x0 << 22 ) /* (TC) Effect: none */
+#define     AT91C_TC_ASWTRG_SET               ( ( unsigned int ) 0x1 << 22 ) /* (TC) Effect: set */
+#define     AT91C_TC_ASWTRG_CLEAR             ( ( unsigned int ) 0x2 << 22 ) /* (TC) Effect: clear */
+#define     AT91C_TC_ASWTRG_TOGGLE            ( ( unsigned int ) 0x3 << 22 ) /* (TC) Effect: toggle */
+#define AT91C_TC_BCPB                         ( ( unsigned int ) 0x3 << 24 ) /* (TC) RB Compare Effect on TIOB */
+#define     AT91C_TC_BCPB_NONE                ( ( unsigned int ) 0x0 << 24 ) /* (TC) Effect: none */
+#define     AT91C_TC_BCPB_SET                 ( ( unsigned int ) 0x1 << 24 ) /* (TC) Effect: set */
+#define     AT91C_TC_BCPB_CLEAR               ( ( unsigned int ) 0x2 << 24 ) /* (TC) Effect: clear */
+#define     AT91C_TC_BCPB_TOGGLE              ( ( unsigned int ) 0x3 << 24 ) /* (TC) Effect: toggle */
+#define AT91C_TC_BCPC                         ( ( unsigned int ) 0x3 << 26 ) /* (TC) RC Compare Effect on TIOB */
+#define     AT91C_TC_BCPC_NONE                ( ( unsigned int ) 0x0 << 26 ) /* (TC) Effect: none */
+#define     AT91C_TC_BCPC_SET                 ( ( unsigned int ) 0x1 << 26 ) /* (TC) Effect: set */
+#define     AT91C_TC_BCPC_CLEAR               ( ( unsigned int ) 0x2 << 26 ) /* (TC) Effect: clear */
+#define     AT91C_TC_BCPC_TOGGLE              ( ( unsigned int ) 0x3 << 26 ) /* (TC) Effect: toggle */
+#define AT91C_TC_BEEVT                        ( ( unsigned int ) 0x3 << 28 ) /* (TC) External Event Effect on TIOB */
+#define     AT91C_TC_BEEVT_NONE               ( ( unsigned int ) 0x0 << 28 ) /* (TC) Effect: none */
+#define     AT91C_TC_BEEVT_SET                ( ( unsigned int ) 0x1 << 28 ) /* (TC) Effect: set */
+#define     AT91C_TC_BEEVT_CLEAR              ( ( unsigned int ) 0x2 << 28 ) /* (TC) Effect: clear */
+#define     AT91C_TC_BEEVT_TOGGLE             ( ( unsigned int ) 0x3 << 28 ) /* (TC) Effect: toggle */
+#define AT91C_TC_BSWTRG                       ( ( unsigned int ) 0x3 << 30 ) /* (TC) Software Trigger Effect on TIOB */
+#define     AT91C_TC_BSWTRG_NONE              ( ( unsigned int ) 0x0 << 30 ) /* (TC) Effect: none */
+#define     AT91C_TC_BSWTRG_SET               ( ( unsigned int ) 0x1 << 30 ) /* (TC) Effect: set */
+#define     AT91C_TC_BSWTRG_CLEAR             ( ( unsigned int ) 0x2 << 30 ) /* (TC) Effect: clear */
+#define     AT91C_TC_BSWTRG_TOGGLE            ( ( unsigned int ) 0x3 << 30 ) /* (TC) Effect: toggle */
+/* -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- */
+#define AT91C_TC_COVFS                        ( ( unsigned int ) 0x1 << 0 )  /* (TC) Counter Overflow */
+#define AT91C_TC_LOVRS                        ( ( unsigned int ) 0x1 << 1 )  /* (TC) Load Overrun */
+#define AT91C_TC_CPAS                         ( ( unsigned int ) 0x1 << 2 )  /* (TC) RA Compare */
+#define AT91C_TC_CPBS                         ( ( unsigned int ) 0x1 << 3 )  /* (TC) RB Compare */
+#define AT91C_TC_CPCS                         ( ( unsigned int ) 0x1 << 4 )  /* (TC) RC Compare */
+#define AT91C_TC_LDRAS                        ( ( unsigned int ) 0x1 << 5 )  /* (TC) RA Loading */
+#define AT91C_TC_LDRBS                        ( ( unsigned int ) 0x1 << 6 )  /* (TC) RB Loading */
+#define AT91C_TC_ETRGS                        ( ( unsigned int ) 0x1 << 7 )  /* (TC) External Trigger */
+#define AT91C_TC_CLKSTA                       ( ( unsigned int ) 0x1 << 16 ) /* (TC) Clock Enabling */
+#define AT91C_TC_MTIOA                        ( ( unsigned int ) 0x1 << 17 ) /* (TC) TIOA Mirror */
+#define AT91C_TC_MTIOB                        ( ( unsigned int ) 0x1 << 18 ) /* (TC) TIOA Mirror */
+/* -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- */
+/* -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- */
+/* -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- */
+
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Timer Counter Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_TCB
+{
+    AT91S_TC TCB_TC0;        /* TC Channel 0 */
+    AT91_REG Reserved0[ 4 ]; /* */
+    AT91S_TC TCB_TC1;        /* TC Channel 1 */
+    AT91_REG Reserved1[ 4 ]; /* */
+    AT91S_TC TCB_TC2;        /* TC Channel 2 */
+    AT91_REG Reserved2[ 4 ]; /* */
+    AT91_REG TCB_BCR;        /* TC Block Control Register */
+    AT91_REG TCB_BMR;        /* TC Block Mode Register */
+} AT91S_TCB, * AT91PS_TCB;
+
+/* -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- */
+#define AT91C_TCB_SYNC                 ( ( unsigned int ) 0x1 << 0 ) /* (TCB) Synchro Command */
+/* -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- */
+#define AT91C_TCB_TC0XC0S              ( ( unsigned int ) 0x3 << 0 ) /* (TCB) External Clock Signal 0 Selection */
+#define     AT91C_TCB_TC0XC0S_TCLK0    ( ( unsigned int ) 0x0 )      /* (TCB) TCLK0 connected to XC0 */
+#define     AT91C_TCB_TC0XC0S_NONE     ( ( unsigned int ) 0x1 )      /* (TCB) None signal connected to XC0 */
+#define     AT91C_TCB_TC0XC0S_TIOA1    ( ( unsigned int ) 0x2 )      /* (TCB) TIOA1 connected to XC0 */
+#define     AT91C_TCB_TC0XC0S_TIOA2    ( ( unsigned int ) 0x3 )      /* (TCB) TIOA2 connected to XC0 */
+#define AT91C_TCB_TC1XC1S              ( ( unsigned int ) 0x3 << 2 ) /* (TCB) External Clock Signal 1 Selection */
+#define     AT91C_TCB_TC1XC1S_TCLK1    ( ( unsigned int ) 0x0 << 2 ) /* (TCB) TCLK1 connected to XC1 */
+#define     AT91C_TCB_TC1XC1S_NONE     ( ( unsigned int ) 0x1 << 2 ) /* (TCB) None signal connected to XC1 */
+#define     AT91C_TCB_TC1XC1S_TIOA0    ( ( unsigned int ) 0x2 << 2 ) /* (TCB) TIOA0 connected to XC1 */
+#define     AT91C_TCB_TC1XC1S_TIOA2    ( ( unsigned int ) 0x3 << 2 ) /* (TCB) TIOA2 connected to XC1 */
+#define AT91C_TCB_TC2XC2S              ( ( unsigned int ) 0x3 << 4 ) /* (TCB) External Clock Signal 2 Selection */
+#define     AT91C_TCB_TC2XC2S_TCLK2    ( ( unsigned int ) 0x0 << 4 ) /* (TCB) TCLK2 connected to XC2 */
+#define     AT91C_TCB_TC2XC2S_NONE     ( ( unsigned int ) 0x1 << 4 ) /* (TCB) None signal connected to XC2 */
+#define     AT91C_TCB_TC2XC2S_TIOA0    ( ( unsigned int ) 0x2 << 4 ) /* (TCB) TIOA0 connected to XC2 */
+#define     AT91C_TCB_TC2XC2S_TIOA1    ( ( unsigned int ) 0x3 << 4 ) /* (TCB) TIOA2 connected to XC2 */
+
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Control Area Network MailBox Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_CAN_MB
+{
+    AT91_REG CAN_MB_MMR;  /* MailBox Mode Register */
+    AT91_REG CAN_MB_MAM;  /* MailBox Acceptance Mask Register */
+    AT91_REG CAN_MB_MID;  /* MailBox ID Register */
+    AT91_REG CAN_MB_MFID; /* MailBox Family ID Register */
+    AT91_REG CAN_MB_MSR;  /* MailBox Status Register */
+    AT91_REG CAN_MB_MDL;  /* MailBox Data Low Register */
+    AT91_REG CAN_MB_MDH;  /* MailBox Data High Register */
+    AT91_REG CAN_MB_MCR;  /* MailBox Control Register */
+} AT91S_CAN_MB, * AT91PS_CAN_MB;
+
+/* -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- */
+#define AT91C_CAN_MTIMEMARK              ( ( unsigned int ) 0xFFFF << 0 )  /* (CAN_MB) Mailbox Timemark */
+#define AT91C_CAN_PRIOR                  ( ( unsigned int ) 0xF << 16 )    /* (CAN_MB) Mailbox Priority */
+#define AT91C_CAN_MOT                    ( ( unsigned int ) 0x7 << 24 )    /* (CAN_MB) Mailbox Object Type */
+#define     AT91C_CAN_MOT_DIS            ( ( unsigned int ) 0x0 << 24 )    /* (CAN_MB) */
+#define     AT91C_CAN_MOT_RX             ( ( unsigned int ) 0x1 << 24 )    /* (CAN_MB) */
+#define     AT91C_CAN_MOT_RXOVERWRITE    ( ( unsigned int ) 0x2 << 24 )    /* (CAN_MB) */
+#define     AT91C_CAN_MOT_TX             ( ( unsigned int ) 0x3 << 24 )    /* (CAN_MB) */
+#define     AT91C_CAN_MOT_CONSUMER       ( ( unsigned int ) 0x4 << 24 )    /* (CAN_MB) */
+#define     AT91C_CAN_MOT_PRODUCER       ( ( unsigned int ) 0x5 << 24 )    /* (CAN_MB) */
+/* -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- */
+#define AT91C_CAN_MIDvB                  ( ( unsigned int ) 0x3FFFF << 0 ) /* (CAN_MB) Complementary bits for identifier in extended mode */
+#define AT91C_CAN_MIDvA                  ( ( unsigned int ) 0x7FF << 18 )  /* (CAN_MB) Identifier for standard frame mode */
+#define AT91C_CAN_MIDE                   ( ( unsigned int ) 0x1 << 29 )    /* (CAN_MB) Identifier Version */
+/* -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- */
+/* -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- */
+/* -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- */
+#define AT91C_CAN_MTIMESTAMP    ( ( unsigned int ) 0xFFFF << 0 ) /* (CAN_MB) Timer Value */
+#define AT91C_CAN_MDLC          ( ( unsigned int ) 0xF << 16 )   /* (CAN_MB) Mailbox Data Length Code */
+#define AT91C_CAN_MRTR          ( ( unsigned int ) 0x1 << 20 )   /* (CAN_MB) Mailbox Remote Transmission Request */
+#define AT91C_CAN_MABT          ( ( unsigned int ) 0x1 << 22 )   /* (CAN_MB) Mailbox Message Abort */
+#define AT91C_CAN_MRDY          ( ( unsigned int ) 0x1 << 23 )   /* (CAN_MB) Mailbox Ready */
+#define AT91C_CAN_MMI           ( ( unsigned int ) 0x1 << 24 )   /* (CAN_MB) Mailbox Message Ignored */
+/* -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- */
+/* -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- */
+/* -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- */
+#define AT91C_CAN_MACR    ( ( unsigned int ) 0x1 << 22 ) /* (CAN_MB) Abort Request for Mailbox */
+#define AT91C_CAN_MTCR    ( ( unsigned int ) 0x1 << 23 ) /* (CAN_MB) Mailbox Transfer Command */
+
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Control Area Network Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_CAN
+{
+    AT91_REG CAN_MR;          /* Mode Register */
+    AT91_REG CAN_IER;         /* Interrupt Enable Register */
+    AT91_REG CAN_IDR;         /* Interrupt Disable Register */
+    AT91_REG CAN_IMR;         /* Interrupt Mask Register */
+    AT91_REG CAN_SR;          /* Status Register */
+    AT91_REG CAN_BR;          /* Baudrate Register */
+    AT91_REG CAN_TIM;         /* Timer Register */
+    AT91_REG CAN_TIMESTP;     /* Time Stamp Register */
+    AT91_REG CAN_ECR;         /* Error Counter Register */
+    AT91_REG CAN_TCR;         /* Transfer Command Register */
+    AT91_REG CAN_ACR;         /* Abort Command Register */
+    AT91_REG Reserved0[ 52 ]; /* */
+    AT91_REG CAN_VR;          /* Version Register */
+    AT91_REG Reserved1[ 64 ]; /* */
+    AT91S_CAN_MB CAN_MB0;     /* CAN Mailbox 0 */
+    AT91S_CAN_MB CAN_MB1;     /* CAN Mailbox 1 */
+    AT91S_CAN_MB CAN_MB2;     /* CAN Mailbox 2 */
+    AT91S_CAN_MB CAN_MB3;     /* CAN Mailbox 3 */
+    AT91S_CAN_MB CAN_MB4;     /* CAN Mailbox 4 */
+    AT91S_CAN_MB CAN_MB5;     /* CAN Mailbox 5 */
+    AT91S_CAN_MB CAN_MB6;     /* CAN Mailbox 6 */
+    AT91S_CAN_MB CAN_MB7;     /* CAN Mailbox 7 */
+    AT91S_CAN_MB CAN_MB8;     /* CAN Mailbox 8 */
+    AT91S_CAN_MB CAN_MB9;     /* CAN Mailbox 9 */
+    AT91S_CAN_MB CAN_MB10;    /* CAN Mailbox 10 */
+    AT91S_CAN_MB CAN_MB11;    /* CAN Mailbox 11 */
+    AT91S_CAN_MB CAN_MB12;    /* CAN Mailbox 12 */
+    AT91S_CAN_MB CAN_MB13;    /* CAN Mailbox 13 */
+    AT91S_CAN_MB CAN_MB14;    /* CAN Mailbox 14 */
+    AT91S_CAN_MB CAN_MB15;    /* CAN Mailbox 15 */
+} AT91S_CAN, * AT91PS_CAN;
+
+/* -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- */
+#define AT91C_CAN_CANEN     ( ( unsigned int ) 0x1 << 0 )  /* (CAN) CAN Controller Enable */
+#define AT91C_CAN_LPM       ( ( unsigned int ) 0x1 << 1 )  /* (CAN) Disable/Enable Low Power Mode */
+#define AT91C_CAN_ABM       ( ( unsigned int ) 0x1 << 2 )  /* (CAN) Disable/Enable Autobaud/Listen Mode */
+#define AT91C_CAN_OVL       ( ( unsigned int ) 0x1 << 3 )  /* (CAN) Disable/Enable Overload Frame */
+#define AT91C_CAN_TEOF      ( ( unsigned int ) 0x1 << 4 )  /* (CAN) Time Stamp messages at each end of Frame */
+#define AT91C_CAN_TTM       ( ( unsigned int ) 0x1 << 5 )  /* (CAN) Disable/Enable Time Trigger Mode */
+#define AT91C_CAN_TIMFRZ    ( ( unsigned int ) 0x1 << 6 )  /* (CAN) Enable Timer Freeze */
+#define AT91C_CAN_DRPT      ( ( unsigned int ) 0x1 << 7 )  /* (CAN) Disable Repeat */
+/* -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- */
+#define AT91C_CAN_MB0       ( ( unsigned int ) 0x1 << 0 )  /* (CAN) Mailbox 0 Flag */
+#define AT91C_CAN_MB1       ( ( unsigned int ) 0x1 << 1 )  /* (CAN) Mailbox 1 Flag */
+#define AT91C_CAN_MB2       ( ( unsigned int ) 0x1 << 2 )  /* (CAN) Mailbox 2 Flag */
+#define AT91C_CAN_MB3       ( ( unsigned int ) 0x1 << 3 )  /* (CAN) Mailbox 3 Flag */
+#define AT91C_CAN_MB4       ( ( unsigned int ) 0x1 << 4 )  /* (CAN) Mailbox 4 Flag */
+#define AT91C_CAN_MB5       ( ( unsigned int ) 0x1 << 5 )  /* (CAN) Mailbox 5 Flag */
+#define AT91C_CAN_MB6       ( ( unsigned int ) 0x1 << 6 )  /* (CAN) Mailbox 6 Flag */
+#define AT91C_CAN_MB7       ( ( unsigned int ) 0x1 << 7 )  /* (CAN) Mailbox 7 Flag */
+#define AT91C_CAN_MB8       ( ( unsigned int ) 0x1 << 8 )  /* (CAN) Mailbox 8 Flag */
+#define AT91C_CAN_MB9       ( ( unsigned int ) 0x1 << 9 )  /* (CAN) Mailbox 9 Flag */
+#define AT91C_CAN_MB10      ( ( unsigned int ) 0x1 << 10 ) /* (CAN) Mailbox 10 Flag */
+#define AT91C_CAN_MB11      ( ( unsigned int ) 0x1 << 11 ) /* (CAN) Mailbox 11 Flag */
+#define AT91C_CAN_MB12      ( ( unsigned int ) 0x1 << 12 ) /* (CAN) Mailbox 12 Flag */
+#define AT91C_CAN_MB13      ( ( unsigned int ) 0x1 << 13 ) /* (CAN) Mailbox 13 Flag */
+#define AT91C_CAN_MB14      ( ( unsigned int ) 0x1 << 14 ) /* (CAN) Mailbox 14 Flag */
+#define AT91C_CAN_MB15      ( ( unsigned int ) 0x1 << 15 ) /* (CAN) Mailbox 15 Flag */
+#define AT91C_CAN_ERRA      ( ( unsigned int ) 0x1 << 16 ) /* (CAN) Error Active Mode Flag */
+#define AT91C_CAN_WARN      ( ( unsigned int ) 0x1 << 17 ) /* (CAN) Warning Limit Flag */
+#define AT91C_CAN_ERRP      ( ( unsigned int ) 0x1 << 18 ) /* (CAN) Error Passive Mode Flag */
+#define AT91C_CAN_BOFF      ( ( unsigned int ) 0x1 << 19 ) /* (CAN) Bus Off Mode Flag */
+#define AT91C_CAN_SLEEP     ( ( unsigned int ) 0x1 << 20 ) /* (CAN) Sleep Flag */
+#define AT91C_CAN_WAKEUP    ( ( unsigned int ) 0x1 << 21 ) /* (CAN) Wakeup Flag */
+#define AT91C_CAN_TOVF      ( ( unsigned int ) 0x1 << 22 ) /* (CAN) Timer Overflow Flag */
+#define AT91C_CAN_TSTP      ( ( unsigned int ) 0x1 << 23 ) /* (CAN) Timestamp Flag */
+#define AT91C_CAN_CERR      ( ( unsigned int ) 0x1 << 24 ) /* (CAN) CRC Error */
+#define AT91C_CAN_SERR      ( ( unsigned int ) 0x1 << 25 ) /* (CAN) Stuffing Error */
+#define AT91C_CAN_AERR      ( ( unsigned int ) 0x1 << 26 ) /* (CAN) Acknowledgment Error */
+#define AT91C_CAN_FERR      ( ( unsigned int ) 0x1 << 27 ) /* (CAN) Form Error */
+#define AT91C_CAN_BERR      ( ( unsigned int ) 0x1 << 28 ) /* (CAN) Bit Error */
+/* -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- */
+/* -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- */
+/* -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- */
+#define AT91C_CAN_RBSY      ( ( unsigned int ) 0x1 << 29 )   /* (CAN) Receiver Busy */
+#define AT91C_CAN_TBSY      ( ( unsigned int ) 0x1 << 30 )   /* (CAN) Transmitter Busy */
+#define AT91C_CAN_OVLY      ( ( unsigned int ) 0x1 << 31 )   /* (CAN) Overload Busy */
+/* -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- */
+#define AT91C_CAN_PHASE2    ( ( unsigned int ) 0x7 << 0 )    /* (CAN) Phase 2 segment */
+#define AT91C_CAN_PHASE1    ( ( unsigned int ) 0x7 << 4 )    /* (CAN) Phase 1 segment */
+#define AT91C_CAN_PROPAG    ( ( unsigned int ) 0x7 << 8 )    /* (CAN) Programmation time segment */
+#define AT91C_CAN_SYNC      ( ( unsigned int ) 0x3 << 12 )   /* (CAN) Re-synchronization jump width segment */
+#define AT91C_CAN_BRP       ( ( unsigned int ) 0x7F << 16 )  /* (CAN) Baudrate Prescaler */
+#define AT91C_CAN_SMP       ( ( unsigned int ) 0x1 << 24 )   /* (CAN) Sampling mode */
+/* -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- */
+#define AT91C_CAN_TIMER     ( ( unsigned int ) 0xFFFF << 0 ) /* (CAN) Timer field */
+/* -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- */
+/* -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- */
+#define AT91C_CAN_REC       ( ( unsigned int ) 0xFF << 0 )  /* (CAN) Receive Error Counter */
+#define AT91C_CAN_TEC       ( ( unsigned int ) 0xFF << 16 ) /* (CAN) Transmit Error Counter */
+/* -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- */
+#define AT91C_CAN_TIMRST    ( ( unsigned int ) 0x1 << 31 )  /* (CAN) Timer Reset Field */
+/* -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- */
+
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Ethernet MAC 10/100 */
+/* ***************************************************************************** */
+typedef struct _AT91S_EMAC
+{
+    AT91_REG EMAC_NCR;        /* Network Control Register */
+    AT91_REG EMAC_NCFGR;      /* Network Configuration Register */
+    AT91_REG EMAC_NSR;        /* Network Status Register */
+    AT91_REG Reserved0[ 2 ];  /* */
+    AT91_REG EMAC_TSR;        /* Transmit Status Register */
+    AT91_REG EMAC_RBQP;       /* Receive Buffer Queue Pointer */
+    AT91_REG EMAC_TBQP;       /* Transmit Buffer Queue Pointer */
+    AT91_REG EMAC_RSR;        /* Receive Status Register */
+    AT91_REG EMAC_ISR;        /* Interrupt Status Register */
+    AT91_REG EMAC_IER;        /* Interrupt Enable Register */
+    AT91_REG EMAC_IDR;        /* Interrupt Disable Register */
+    AT91_REG EMAC_IMR;        /* Interrupt Mask Register */
+    AT91_REG EMAC_MAN;        /* PHY Maintenance Register */
+    AT91_REG EMAC_PTR;        /* Pause Time Register */
+    AT91_REG EMAC_PFR;        /* Pause Frames received Register */
+    AT91_REG EMAC_FTO;        /* Frames Transmitted OK Register */
+    AT91_REG EMAC_SCF;        /* Single Collision Frame Register */
+    AT91_REG EMAC_MCF;        /* Multiple Collision Frame Register */
+    AT91_REG EMAC_FRO;        /* Frames Received OK Register */
+    AT91_REG EMAC_FCSE;       /* Frame Check Sequence Error Register */
+    AT91_REG EMAC_ALE;        /* Alignment Error Register */
+    AT91_REG EMAC_DTF;        /* Deferred Transmission Frame Register */
+    AT91_REG EMAC_LCOL;       /* Late Collision Register */
+    AT91_REG EMAC_ECOL;       /* Excessive Collision Register */
+    AT91_REG EMAC_TUND;       /* Transmit Underrun Error Register */
+    AT91_REG EMAC_CSE;        /* Carrier Sense Error Register */
+    AT91_REG EMAC_RRE;        /* Receive Ressource Error Register */
+    AT91_REG EMAC_ROV;        /* Receive Overrun Errors Register */
+    AT91_REG EMAC_RSE;        /* Receive Symbol Errors Register */
+    AT91_REG EMAC_ELE;        /* Excessive Length Errors Register */
+    AT91_REG EMAC_RJA;        /* Receive Jabbers Register */
+    AT91_REG EMAC_USF;        /* Undersize Frames Register */
+    AT91_REG EMAC_STE;        /* SQE Test Error Register */
+    AT91_REG EMAC_RLE;        /* Receive Length Field Mismatch Register */
+    AT91_REG EMAC_TPF;        /* Transmitted Pause Frames Register */
+    AT91_REG EMAC_HRB;        /* Hash Address Bottom[31:0] */
+    AT91_REG EMAC_HRT;        /* Hash Address Top[63:32] */
+    AT91_REG EMAC_SA1L;       /* Specific Address 1 Bottom, First 4 bytes */
+    AT91_REG EMAC_SA1H;       /* Specific Address 1 Top, Last 2 bytes */
+    AT91_REG EMAC_SA2L;       /* Specific Address 2 Bottom, First 4 bytes */
+    AT91_REG EMAC_SA2H;       /* Specific Address 2 Top, Last 2 bytes */
+    AT91_REG EMAC_SA3L;       /* Specific Address 3 Bottom, First 4 bytes */
+    AT91_REG EMAC_SA3H;       /* Specific Address 3 Top, Last 2 bytes */
+    AT91_REG EMAC_SA4L;       /* Specific Address 4 Bottom, First 4 bytes */
+    AT91_REG EMAC_SA4H;       /* Specific Address 4 Top, Last 2 bytes */
+    AT91_REG EMAC_TID;        /* Type ID Checking Register */
+    AT91_REG EMAC_TPQ;        /* Transmit Pause Quantum Register */
+    AT91_REG EMAC_USRIO;      /* USER Input/Output Register */
+    AT91_REG EMAC_WOL;        /* Wake On LAN Register */
+    AT91_REG Reserved1[ 13 ]; /* */
+    AT91_REG EMAC_REV;        /* Revision Register */
+} AT91S_EMAC, * AT91PS_EMAC;
+
+/* -------- EMAC_NCR : (EMAC Offset: 0x0)  -------- */
+#define AT91C_EMAC_LB                   ( ( unsigned int ) 0x1 << 0 )  /* (EMAC) Loopback. Optional. When set, loopback signal is at high level. */
+#define AT91C_EMAC_LLB                  ( ( unsigned int ) 0x1 << 1 )  /* (EMAC) Loopback local. */
+#define AT91C_EMAC_RE                   ( ( unsigned int ) 0x1 << 2 )  /* (EMAC) Receive enable. */
+#define AT91C_EMAC_TE                   ( ( unsigned int ) 0x1 << 3 )  /* (EMAC) Transmit enable. */
+#define AT91C_EMAC_MPE                  ( ( unsigned int ) 0x1 << 4 )  /* (EMAC) Management port enable. */
+#define AT91C_EMAC_CLRSTAT              ( ( unsigned int ) 0x1 << 5 )  /* (EMAC) Clear statistics registers. */
+#define AT91C_EMAC_INCSTAT              ( ( unsigned int ) 0x1 << 6 )  /* (EMAC) Increment statistics registers. */
+#define AT91C_EMAC_WESTAT               ( ( unsigned int ) 0x1 << 7 )  /* (EMAC) Write enable for statistics registers. */
+#define AT91C_EMAC_BP                   ( ( unsigned int ) 0x1 << 8 )  /* (EMAC) Back pressure. */
+#define AT91C_EMAC_TSTART               ( ( unsigned int ) 0x1 << 9 )  /* (EMAC) Start Transmission. */
+#define AT91C_EMAC_THALT                ( ( unsigned int ) 0x1 << 10 ) /* (EMAC) Transmission Halt. */
+#define AT91C_EMAC_TPFR                 ( ( unsigned int ) 0x1 << 11 ) /* (EMAC) Transmit pause frame */
+#define AT91C_EMAC_TZQ                  ( ( unsigned int ) 0x1 << 12 ) /* (EMAC) Transmit zero quantum pause frame */
+/* -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- */
+#define AT91C_EMAC_SPD                  ( ( unsigned int ) 0x1 << 0 )  /* (EMAC) Speed. */
+#define AT91C_EMAC_FD                   ( ( unsigned int ) 0x1 << 1 )  /* (EMAC) Full duplex. */
+#define AT91C_EMAC_JFRAME               ( ( unsigned int ) 0x1 << 3 )  /* (EMAC) Jumbo Frames. */
+#define AT91C_EMAC_CAF                  ( ( unsigned int ) 0x1 << 4 )  /* (EMAC) Copy all frames. */
+#define AT91C_EMAC_NBC                  ( ( unsigned int ) 0x1 << 5 )  /* (EMAC) No broadcast. */
+#define AT91C_EMAC_MTI                  ( ( unsigned int ) 0x1 << 6 )  /* (EMAC) Multicast hash event enable */
+#define AT91C_EMAC_UNI                  ( ( unsigned int ) 0x1 << 7 )  /* (EMAC) Unicast hash enable. */
+#define AT91C_EMAC_BIG                  ( ( unsigned int ) 0x1 << 8 )  /* (EMAC) Receive 1522 bytes. */
+#define AT91C_EMAC_EAE                  ( ( unsigned int ) 0x1 << 9 )  /* (EMAC) External address match enable. */
+#define AT91C_EMAC_CLK                  ( ( unsigned int ) 0x3 << 10 ) /* (EMAC) */
+#define     AT91C_EMAC_CLK_HCLK_8       ( ( unsigned int ) 0x0 << 10 ) /* (EMAC) HCLK divided by 8 */
+#define     AT91C_EMAC_CLK_HCLK_16      ( ( unsigned int ) 0x1 << 10 ) /* (EMAC) HCLK divided by 16 */
+#define     AT91C_EMAC_CLK_HCLK_32      ( ( unsigned int ) 0x2 << 10 ) /* (EMAC) HCLK divided by 32 */
+#define     AT91C_EMAC_CLK_HCLK_64      ( ( unsigned int ) 0x3 << 10 ) /* (EMAC) HCLK divided by 64 */
+#define AT91C_EMAC_RTY                  ( ( unsigned int ) 0x1 << 12 ) /* (EMAC) */
+#define AT91C_EMAC_PAE                  ( ( unsigned int ) 0x1 << 13 ) /* (EMAC) */
+#define AT91C_EMAC_RBOF                 ( ( unsigned int ) 0x3 << 14 ) /* (EMAC) */
+#define     AT91C_EMAC_RBOF_OFFSET_0    ( ( unsigned int ) 0x0 << 14 ) /* (EMAC) no offset from start of receive buffer */
+#define     AT91C_EMAC_RBOF_OFFSET_1    ( ( unsigned int ) 0x1 << 14 ) /* (EMAC) one byte offset from start of receive buffer */
+#define     AT91C_EMAC_RBOF_OFFSET_2    ( ( unsigned int ) 0x2 << 14 ) /* (EMAC) two bytes offset from start of receive buffer */
+#define     AT91C_EMAC_RBOF_OFFSET_3    ( ( unsigned int ) 0x3 << 14 ) /* (EMAC) three bytes offset from start of receive buffer */
+#define AT91C_EMAC_RLCE                 ( ( unsigned int ) 0x1 << 16 ) /* (EMAC) Receive Length field Checking Enable */
+#define AT91C_EMAC_DRFCS                ( ( unsigned int ) 0x1 << 17 ) /* (EMAC) Discard Receive FCS */
+#define AT91C_EMAC_EFRHD                ( ( unsigned int ) 0x1 << 18 ) /* (EMAC) */
+#define AT91C_EMAC_IRXFCS               ( ( unsigned int ) 0x1 << 19 ) /* (EMAC) Ignore RX FCS */
+/* -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- */
+#define AT91C_EMAC_LINKR                ( ( unsigned int ) 0x1 << 0 )  /* (EMAC) */
+#define AT91C_EMAC_MDIO                 ( ( unsigned int ) 0x1 << 1 )  /* (EMAC) */
+#define AT91C_EMAC_IDLE                 ( ( unsigned int ) 0x1 << 2 )  /* (EMAC) */
+/* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- */
+#define AT91C_EMAC_UBR                  ( ( unsigned int ) 0x1 << 0 )  /* (EMAC) */
+#define AT91C_EMAC_COL                  ( ( unsigned int ) 0x1 << 1 )  /* (EMAC) */
+#define AT91C_EMAC_RLES                 ( ( unsigned int ) 0x1 << 2 )  /* (EMAC) */
+#define AT91C_EMAC_TGO                  ( ( unsigned int ) 0x1 << 3 )  /* (EMAC) Transmit Go */
+#define AT91C_EMAC_BEX                  ( ( unsigned int ) 0x1 << 4 )  /* (EMAC) Buffers exhausted mid frame */
+#define AT91C_EMAC_COMP                 ( ( unsigned int ) 0x1 << 5 )  /* (EMAC) */
+#define AT91C_EMAC_UND                  ( ( unsigned int ) 0x1 << 6 )  /* (EMAC) */
+/* -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- */
+#define AT91C_EMAC_BNA                  ( ( unsigned int ) 0x1 << 0 )  /* (EMAC) */
+#define AT91C_EMAC_REC                  ( ( unsigned int ) 0x1 << 1 )  /* (EMAC) */
+#define AT91C_EMAC_OVR                  ( ( unsigned int ) 0x1 << 2 )  /* (EMAC) */
+/* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- */
+#define AT91C_EMAC_MFD                  ( ( unsigned int ) 0x1 << 0 )  /* (EMAC) */
+#define AT91C_EMAC_RCOMP                ( ( unsigned int ) 0x1 << 1 )  /* (EMAC) */
+#define AT91C_EMAC_RXUBR                ( ( unsigned int ) 0x1 << 2 )  /* (EMAC) */
+#define AT91C_EMAC_TXUBR                ( ( unsigned int ) 0x1 << 3 )  /* (EMAC) */
+#define AT91C_EMAC_TUNDR                ( ( unsigned int ) 0x1 << 4 )  /* (EMAC) */
+#define AT91C_EMAC_RLEX                 ( ( unsigned int ) 0x1 << 5 )  /* (EMAC) */
+#define AT91C_EMAC_TXERR                ( ( unsigned int ) 0x1 << 6 )  /* (EMAC) */
+#define AT91C_EMAC_TCOMP                ( ( unsigned int ) 0x1 << 7 )  /* (EMAC) */
+#define AT91C_EMAC_LINK                 ( ( unsigned int ) 0x1 << 9 )  /* (EMAC) */
+#define AT91C_EMAC_ROVR                 ( ( unsigned int ) 0x1 << 10 ) /* (EMAC) */
+#define AT91C_EMAC_HRESP                ( ( unsigned int ) 0x1 << 11 ) /* (EMAC) */
+#define AT91C_EMAC_PFRE                 ( ( unsigned int ) 0x1 << 12 ) /* (EMAC) */
+#define AT91C_EMAC_PTZ                  ( ( unsigned int ) 0x1 << 13 ) /* (EMAC) */
+/* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- */
+/* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- */
+/* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */
+/* -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- */
+#define AT91C_EMAC_DATA       ( ( unsigned int ) 0xFFFF << 0 )  /* (EMAC) */
+#define AT91C_EMAC_CODE       ( ( unsigned int ) 0x3 << 16 )    /* (EMAC) */
+#define AT91C_EMAC_REGA       ( ( unsigned int ) 0x1F << 18 )   /* (EMAC) */
+#define AT91C_EMAC_PHYA       ( ( unsigned int ) 0x1F << 23 )   /* (EMAC) */
+#define AT91C_EMAC_RW         ( ( unsigned int ) 0x3 << 28 )    /* (EMAC) */
+#define AT91C_EMAC_SOF        ( ( unsigned int ) 0x3 << 30 )    /* (EMAC) */
+/* -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- */
+#define AT91C_EMAC_RMII       ( ( unsigned int ) 0x1 << 0 )     /* (EMAC) Reduce MII */
+/* -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- */
+#define AT91C_EMAC_IP         ( ( unsigned int ) 0xFFFF << 0 )  /* (EMAC) ARP request IP address */
+#define AT91C_EMAC_MAG        ( ( unsigned int ) 0x1 << 16 )    /* (EMAC) Magic packet event enable */
+#define AT91C_EMAC_ARP        ( ( unsigned int ) 0x1 << 17 )    /* (EMAC) ARP request event enable */
+#define AT91C_EMAC_SA1        ( ( unsigned int ) 0x1 << 18 )    /* (EMAC) Specific address register 1 event enable */
+/* -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- */
+#define AT91C_EMAC_REVREF     ( ( unsigned int ) 0xFFFF << 0 )  /* (EMAC) */
+#define AT91C_EMAC_PARTREF    ( ( unsigned int ) 0xFFFF << 16 ) /* (EMAC) */
+
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor */
+/* ***************************************************************************** */
+typedef struct _AT91S_ADC
+{
+    AT91_REG ADC_CR;          /* ADC Control Register */
+    AT91_REG ADC_MR;          /* ADC Mode Register */
+    AT91_REG Reserved0[ 2 ];  /* */
+    AT91_REG ADC_CHER;        /* ADC Channel Enable Register */
+    AT91_REG ADC_CHDR;        /* ADC Channel Disable Register */
+    AT91_REG ADC_CHSR;        /* ADC Channel Status Register */
+    AT91_REG ADC_SR;          /* ADC Status Register */
+    AT91_REG ADC_LCDR;        /* ADC Last Converted Data Register */
+    AT91_REG ADC_IER;         /* ADC Interrupt Enable Register */
+    AT91_REG ADC_IDR;         /* ADC Interrupt Disable Register */
+    AT91_REG ADC_IMR;         /* ADC Interrupt Mask Register */
+    AT91_REG ADC_CDR0;        /* ADC Channel Data Register 0 */
+    AT91_REG ADC_CDR1;        /* ADC Channel Data Register 1 */
+    AT91_REG ADC_CDR2;        /* ADC Channel Data Register 2 */
+    AT91_REG ADC_CDR3;        /* ADC Channel Data Register 3 */
+    AT91_REG ADC_CDR4;        /* ADC Channel Data Register 4 */
+    AT91_REG ADC_CDR5;        /* ADC Channel Data Register 5 */
+    AT91_REG ADC_CDR6;        /* ADC Channel Data Register 6 */
+    AT91_REG ADC_CDR7;        /* ADC Channel Data Register 7 */
+    AT91_REG Reserved1[ 44 ]; /* */
+    AT91_REG ADC_RPR;         /* Receive Pointer Register */
+    AT91_REG ADC_RCR;         /* Receive Counter Register */
+    AT91_REG ADC_TPR;         /* Transmit Pointer Register */
+    AT91_REG ADC_TCR;         /* Transmit Counter Register */
+    AT91_REG ADC_RNPR;        /* Receive Next Pointer Register */
+    AT91_REG ADC_RNCR;        /* Receive Next Counter Register */
+    AT91_REG ADC_TNPR;        /* Transmit Next Pointer Register */
+    AT91_REG ADC_TNCR;        /* Transmit Next Counter Register */
+    AT91_REG ADC_PTCR;        /* PDC Transfer Control Register */
+    AT91_REG ADC_PTSR;        /* PDC Transfer Status Register */
+} AT91S_ADC, * AT91PS_ADC;
+
+/* -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- */
+#define AT91C_ADC_SWRST                    ( ( unsigned int ) 0x1 << 0 )   /* (ADC) Software Reset */
+#define AT91C_ADC_START                    ( ( unsigned int ) 0x1 << 1 )   /* (ADC) Start Conversion */
+/* -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- */
+#define AT91C_ADC_TRGEN                    ( ( unsigned int ) 0x1 << 0 )   /* (ADC) Trigger Enable */
+#define     AT91C_ADC_TRGEN_DIS            ( ( unsigned int ) 0x0 )        /* (ADC) Hardware triggers are disabled. Starting a conversion is only possible by software */
+#define     AT91C_ADC_TRGEN_EN             ( ( unsigned int ) 0x1 )        /* (ADC) Hardware trigger selected by TRGSEL field is enabled. */
+#define AT91C_ADC_TRGSEL                   ( ( unsigned int ) 0x7 << 1 )   /* (ADC) Trigger Selection */
+#define     AT91C_ADC_TRGSEL_TIOA0         ( ( unsigned int ) 0x0 << 1 )   /* (ADC) Selected TRGSEL = TIAO0 */
+#define     AT91C_ADC_TRGSEL_TIOA1         ( ( unsigned int ) 0x1 << 1 )   /* (ADC) Selected TRGSEL = TIAO1 */
+#define     AT91C_ADC_TRGSEL_TIOA2         ( ( unsigned int ) 0x2 << 1 )   /* (ADC) Selected TRGSEL = TIAO2 */
+#define     AT91C_ADC_TRGSEL_TIOA3         ( ( unsigned int ) 0x3 << 1 )   /* (ADC) Selected TRGSEL = TIAO3 */
+#define     AT91C_ADC_TRGSEL_TIOA4         ( ( unsigned int ) 0x4 << 1 )   /* (ADC) Selected TRGSEL = TIAO4 */
+#define     AT91C_ADC_TRGSEL_TIOA5         ( ( unsigned int ) 0x5 << 1 )   /* (ADC) Selected TRGSEL = TIAO5 */
+#define     AT91C_ADC_TRGSEL_EXT           ( ( unsigned int ) 0x6 << 1 )   /* (ADC) Selected TRGSEL = External Trigger */
+#define AT91C_ADC_LOWRES                   ( ( unsigned int ) 0x1 << 4 )   /* (ADC) Resolution. */
+#define     AT91C_ADC_LOWRES_10_BIT        ( ( unsigned int ) 0x0 << 4 )   /* (ADC) 10-bit resolution */
+#define     AT91C_ADC_LOWRES_8_BIT         ( ( unsigned int ) 0x1 << 4 )   /* (ADC) 8-bit resolution */
+#define AT91C_ADC_SLEEP                    ( ( unsigned int ) 0x1 << 5 )   /* (ADC) Sleep Mode */
+#define     AT91C_ADC_SLEEP_NORMAL_MODE    ( ( unsigned int ) 0x0 << 5 )   /* (ADC) Normal Mode */
+#define     AT91C_ADC_SLEEP_MODE           ( ( unsigned int ) 0x1 << 5 )   /* (ADC) Sleep Mode */
+#define AT91C_ADC_PRESCAL                  ( ( unsigned int ) 0x3F << 8 )  /* (ADC) Prescaler rate selection */
+#define AT91C_ADC_STARTUP                  ( ( unsigned int ) 0x1F << 16 ) /* (ADC) Startup Time */
+#define AT91C_ADC_SHTIM                    ( ( unsigned int ) 0xF << 24 )  /* (ADC) Sample & Hold Time */
+/* --------     ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- */
+#define AT91C_ADC_CH0                      ( ( unsigned int ) 0x1 << 0 )   /* (ADC) Channel 0 */
+#define AT91C_ADC_CH1                      ( ( unsigned int ) 0x1 << 1 )   /* (ADC) Channel 1 */
+#define AT91C_ADC_CH2                      ( ( unsigned int ) 0x1 << 2 )   /* (ADC) Channel 2 */
+#define AT91C_ADC_CH3                      ( ( unsigned int ) 0x1 << 3 )   /* (ADC) Channel 3 */
+#define AT91C_ADC_CH4                      ( ( unsigned int ) 0x1 << 4 )   /* (ADC) Channel 4 */
+#define AT91C_ADC_CH5                      ( ( unsigned int ) 0x1 << 5 )   /* (ADC) Channel 5 */
+#define AT91C_ADC_CH6                      ( ( unsigned int ) 0x1 << 6 )   /* (ADC) Channel 6 */
+#define AT91C_ADC_CH7                      ( ( unsigned int ) 0x1 << 7 )   /* (ADC) Channel 7 */
+/* --------     ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- */
+/* --------     ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- */
+/* -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- */
+#define AT91C_ADC_EOC0      ( ( unsigned int ) 0x1 << 0 )   /* (ADC) End of Conversion */
+#define AT91C_ADC_EOC1      ( ( unsigned int ) 0x1 << 1 )   /* (ADC) End of Conversion */
+#define AT91C_ADC_EOC2      ( ( unsigned int ) 0x1 << 2 )   /* (ADC) End of Conversion */
+#define AT91C_ADC_EOC3      ( ( unsigned int ) 0x1 << 3 )   /* (ADC) End of Conversion */
+#define AT91C_ADC_EOC4      ( ( unsigned int ) 0x1 << 4 )   /* (ADC) End of Conversion */
+#define AT91C_ADC_EOC5      ( ( unsigned int ) 0x1 << 5 )   /* (ADC) End of Conversion */
+#define AT91C_ADC_EOC6      ( ( unsigned int ) 0x1 << 6 )   /* (ADC) End of Conversion */
+#define AT91C_ADC_EOC7      ( ( unsigned int ) 0x1 << 7 )   /* (ADC) End of Conversion */
+#define AT91C_ADC_OVRE0     ( ( unsigned int ) 0x1 << 8 )   /* (ADC) Overrun Error */
+#define AT91C_ADC_OVRE1     ( ( unsigned int ) 0x1 << 9 )   /* (ADC) Overrun Error */
+#define AT91C_ADC_OVRE2     ( ( unsigned int ) 0x1 << 10 )  /* (ADC) Overrun Error */
+#define AT91C_ADC_OVRE3     ( ( unsigned int ) 0x1 << 11 )  /* (ADC) Overrun Error */
+#define AT91C_ADC_OVRE4     ( ( unsigned int ) 0x1 << 12 )  /* (ADC) Overrun Error */
+#define AT91C_ADC_OVRE5     ( ( unsigned int ) 0x1 << 13 )  /* (ADC) Overrun Error */
+#define AT91C_ADC_OVRE6     ( ( unsigned int ) 0x1 << 14 )  /* (ADC) Overrun Error */
+#define AT91C_ADC_OVRE7     ( ( unsigned int ) 0x1 << 15 )  /* (ADC) Overrun Error */
+#define AT91C_ADC_DRDY      ( ( unsigned int ) 0x1 << 16 )  /* (ADC) Data Ready */
+#define AT91C_ADC_GOVRE     ( ( unsigned int ) 0x1 << 17 )  /* (ADC) General Overrun */
+#define AT91C_ADC_ENDRX     ( ( unsigned int ) 0x1 << 18 )  /* (ADC) End of Receiver Transfer */
+#define AT91C_ADC_RXBUFF    ( ( unsigned int ) 0x1 << 19 )  /* (ADC) RXBUFF Interrupt */
+/* -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- */
+#define AT91C_ADC_LDATA     ( ( unsigned int ) 0x3FF << 0 ) /* (ADC) Last Data Converted */
+/* -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- */
+/* -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- */
+/* -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- */
+/* -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- */
+#define AT91C_ADC_DATA    ( ( unsigned int ) 0x3FF << 0 )  /* (ADC) Converted Data */
+/* -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- */
+/* -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- */
+/* -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- */
+/* -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- */
+/* -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- */
+/* -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- */
+/* -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- */
+
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Advanced  Encryption Standard */
+/* ***************************************************************************** */
+typedef struct _AT91S_AES
+{
+    AT91_REG AES_CR;           /* Control Register */
+    AT91_REG AES_MR;           /* Mode Register */
+    AT91_REG Reserved0[ 2 ];   /* */
+    AT91_REG AES_IER;          /* Interrupt Enable Register */
+    AT91_REG AES_IDR;          /* Interrupt Disable Register */
+    AT91_REG AES_IMR;          /* Interrupt Mask Register */
+    AT91_REG AES_ISR;          /* Interrupt Status Register */
+    AT91_REG AES_KEYWxR[ 4 ];  /* Key Word x Register */
+    AT91_REG Reserved1[ 4 ];   /* */
+    AT91_REG AES_IDATAxR[ 4 ]; /* Input Data x Register */
+    AT91_REG AES_ODATAxR[ 4 ]; /* Output Data x Register */
+    AT91_REG AES_IVxR[ 4 ];    /* Initialization Vector x Register */
+    AT91_REG Reserved2[ 35 ];  /* */
+    AT91_REG AES_VR;           /* AES Version Register */
+    AT91_REG AES_RPR;          /* Receive Pointer Register */
+    AT91_REG AES_RCR;          /* Receive Counter Register */
+    AT91_REG AES_TPR;          /* Transmit Pointer Register */
+    AT91_REG AES_TCR;          /* Transmit Counter Register */
+    AT91_REG AES_RNPR;         /* Receive Next Pointer Register */
+    AT91_REG AES_RNCR;         /* Receive Next Counter Register */
+    AT91_REG AES_TNPR;         /* Transmit Next Pointer Register */
+    AT91_REG AES_TNCR;         /* Transmit Next Counter Register */
+    AT91_REG AES_PTCR;         /* PDC Transfer Control Register */
+    AT91_REG AES_PTSR;         /* PDC Transfer Status Register */
+} AT91S_AES, * AT91PS_AES;
+
+/* -------- AES_CR : (AES Offset: 0x0) Control Register -------- */
+#define AT91C_AES_START                 ( ( unsigned int ) 0x1 << 0 )   /* (AES) Starts Processing */
+#define AT91C_AES_SWRST                 ( ( unsigned int ) 0x1 << 8 )   /* (AES) Software Reset */
+#define AT91C_AES_LOADSEED              ( ( unsigned int ) 0x1 << 16 )  /* (AES) Random Number Generator Seed Loading */
+/* -------- AES_MR : (AES Offset: 0x4) Mode Register -------- */
+#define AT91C_AES_CIPHER                ( ( unsigned int ) 0x1 << 0 )   /* (AES) Processing Mode */
+#define AT91C_AES_PROCDLY               ( ( unsigned int ) 0xF << 4 )   /* (AES) Processing Delay */
+#define AT91C_AES_SMOD                  ( ( unsigned int ) 0x3 << 8 )   /* (AES) Start Mode */
+#define     AT91C_AES_SMOD_MANUAL       ( ( unsigned int ) 0x0 << 8 )   /* (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. */
+#define     AT91C_AES_SMOD_AUTO         ( ( unsigned int ) 0x1 << 8 )   /* (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). */
+#define     AT91C_AES_SMOD_PDC          ( ( unsigned int ) 0x2 << 8 )   /* (AES) PDC Mode (cf datasheet). */
+#define AT91C_AES_OPMOD                 ( ( unsigned int ) 0x7 << 12 )  /* (AES) Operation Mode */
+#define     AT91C_AES_OPMOD_ECB         ( ( unsigned int ) 0x0 << 12 )  /* (AES) ECB Electronic CodeBook mode. */
+#define     AT91C_AES_OPMOD_CBC         ( ( unsigned int ) 0x1 << 12 )  /* (AES) CBC Cipher Block Chaining mode. */
+#define     AT91C_AES_OPMOD_OFB         ( ( unsigned int ) 0x2 << 12 )  /* (AES) OFB Output Feedback mode. */
+#define     AT91C_AES_OPMOD_CFB         ( ( unsigned int ) 0x3 << 12 )  /* (AES) CFB Cipher Feedback mode. */
+#define     AT91C_AES_OPMOD_CTR         ( ( unsigned int ) 0x4 << 12 )  /* (AES) CTR Counter mode. */
+#define AT91C_AES_LOD                   ( ( unsigned int ) 0x1 << 15 )  /* (AES) Last Output Data Mode */
+#define AT91C_AES_CFBS                  ( ( unsigned int ) 0x7 << 16 )  /* (AES) Cipher Feedback Data Size */
+#define     AT91C_AES_CFBS_128_BIT      ( ( unsigned int ) 0x0 << 16 )  /* (AES) 128-bit. */
+#define     AT91C_AES_CFBS_64_BIT       ( ( unsigned int ) 0x1 << 16 )  /* (AES) 64-bit. */
+#define     AT91C_AES_CFBS_32_BIT       ( ( unsigned int ) 0x2 << 16 )  /* (AES) 32-bit. */
+#define     AT91C_AES_CFBS_16_BIT       ( ( unsigned int ) 0x3 << 16 )  /* (AES) 16-bit. */
+#define     AT91C_AES_CFBS_8_BIT        ( ( unsigned int ) 0x4 << 16 )  /* (AES) 8-bit. */
+#define AT91C_AES_CKEY                  ( ( unsigned int ) 0xF << 20 )  /* (AES) Countermeasure Key */
+#define AT91C_AES_CTYPE                 ( ( unsigned int ) 0x1F << 24 ) /* (AES) Countermeasure Type */
+#define     AT91C_AES_CTYPE_TYPE1_EN    ( ( unsigned int ) 0x1 << 24 )  /* (AES) Countermeasure type 1 is enabled. */
+#define     AT91C_AES_CTYPE_TYPE2_EN    ( ( unsigned int ) 0x2 << 24 )  /* (AES) Countermeasure type 2 is enabled. */
+#define     AT91C_AES_CTYPE_TYPE3_EN    ( ( unsigned int ) 0x4 << 24 )  /* (AES) Countermeasure type 3 is enabled. */
+#define     AT91C_AES_CTYPE_TYPE4_EN    ( ( unsigned int ) 0x8 << 24 )  /* (AES) Countermeasure type 4 is enabled. */
+#define     AT91C_AES_CTYPE_TYPE5_EN    ( ( unsigned int ) 0x10 << 24 ) /* (AES) Countermeasure type 5 is enabled. */
+/* -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- */
+#define AT91C_AES_DATRDY                ( ( unsigned int ) 0x1 << 0 )   /* (AES) DATRDY */
+#define AT91C_AES_ENDRX                 ( ( unsigned int ) 0x1 << 1 )   /* (AES) PDC Read Buffer End */
+#define AT91C_AES_ENDTX                 ( ( unsigned int ) 0x1 << 2 )   /* (AES) PDC Write Buffer End */
+#define AT91C_AES_RXBUFF                ( ( unsigned int ) 0x1 << 3 )   /* (AES) PDC Read Buffer Full */
+#define AT91C_AES_TXBUFE                ( ( unsigned int ) 0x1 << 4 )   /* (AES) PDC Write Buffer Empty */
+#define AT91C_AES_URAD                  ( ( unsigned int ) 0x1 << 8 )   /* (AES) Unspecified Register Access Detection */
+/* -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- */
+/* -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- */
+/* -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- */
+#define AT91C_AES_URAT                              ( ( unsigned int ) 0x7 << 12 ) /* (AES) Unspecified Register Access Type Status */
+#define     AT91C_AES_URAT_IN_DAT_WRITE_DATPROC     ( ( unsigned int ) 0x0 << 12 ) /* (AES) Input data register written during the data processing in PDC mode. */
+#define     AT91C_AES_URAT_OUT_DAT_READ_DATPROC     ( ( unsigned int ) 0x1 << 12 ) /* (AES) Output data register read during the data processing. */
+#define     AT91C_AES_URAT_MODEREG_WRITE_DATPROC    ( ( unsigned int ) 0x2 << 12 ) /* (AES) Mode register written during the data processing. */
+#define     AT91C_AES_URAT_OUT_DAT_READ_SUBKEY      ( ( unsigned int ) 0x3 << 12 ) /* (AES) Output data register read during the sub-keys generation. */
+#define     AT91C_AES_URAT_MODEREG_WRITE_SUBKEY     ( ( unsigned int ) 0x4 << 12 ) /* (AES) Mode register written during the sub-keys generation. */
+#define     AT91C_AES_URAT_WO_REG_READ              ( ( unsigned int ) 0x5 << 12 ) /* (AES) Write-only register read access. */
+
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Triple Data Encryption Standard */
+/* ***************************************************************************** */
+typedef struct _AT91S_TDES
+{
+    AT91_REG TDES_CR;           /* Control Register */
+    AT91_REG TDES_MR;           /* Mode Register */
+    AT91_REG Reserved0[ 2 ];    /* */
+    AT91_REG TDES_IER;          /* Interrupt Enable Register */
+    AT91_REG TDES_IDR;          /* Interrupt Disable Register */
+    AT91_REG TDES_IMR;          /* Interrupt Mask Register */
+    AT91_REG TDES_ISR;          /* Interrupt Status Register */
+    AT91_REG TDES_KEY1WxR[ 2 ]; /* Key 1 Word x Register */
+    AT91_REG TDES_KEY2WxR[ 2 ]; /* Key 2 Word x Register */
+    AT91_REG TDES_KEY3WxR[ 2 ]; /* Key 3 Word x Register */
+    AT91_REG Reserved1[ 2 ];    /* */
+    AT91_REG TDES_IDATAxR[ 2 ]; /* Input Data x Register */
+    AT91_REG Reserved2[ 2 ];    /* */
+    AT91_REG TDES_ODATAxR[ 2 ]; /* Output Data x Register */
+    AT91_REG Reserved3[ 2 ];    /* */
+    AT91_REG TDES_IVxR[ 2 ];    /* Initialization Vector x Register */
+    AT91_REG Reserved4[ 37 ];   /* */
+    AT91_REG TDES_VR;           /* TDES Version Register */
+    AT91_REG TDES_RPR;          /* Receive Pointer Register */
+    AT91_REG TDES_RCR;          /* Receive Counter Register */
+    AT91_REG TDES_TPR;          /* Transmit Pointer Register */
+    AT91_REG TDES_TCR;          /* Transmit Counter Register */
+    AT91_REG TDES_RNPR;         /* Receive Next Pointer Register */
+    AT91_REG TDES_RNCR;         /* Receive Next Counter Register */
+    AT91_REG TDES_TNPR;         /* Transmit Next Pointer Register */
+    AT91_REG TDES_TNCR;         /* Transmit Next Counter Register */
+    AT91_REG TDES_PTCR;         /* PDC Transfer Control Register */
+    AT91_REG TDES_PTSR;         /* PDC Transfer Status Register */
+} AT91S_TDES, * AT91PS_TDES;
+
+/* -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- */
+#define AT91C_TDES_START              ( ( unsigned int ) 0x1 << 0 )  /* (TDES) Starts Processing */
+#define AT91C_TDES_SWRST              ( ( unsigned int ) 0x1 << 8 )  /* (TDES) Software Reset */
+/* -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- */
+#define AT91C_TDES_CIPHER             ( ( unsigned int ) 0x1 << 0 )  /* (TDES) Processing Mode */
+#define AT91C_TDES_TDESMOD            ( ( unsigned int ) 0x1 << 1 )  /* (TDES) Single or Triple DES Mode */
+#define AT91C_TDES_KEYMOD             ( ( unsigned int ) 0x1 << 4 )  /* (TDES) Key Mode */
+#define AT91C_TDES_SMOD               ( ( unsigned int ) 0x3 << 8 )  /* (TDES) Start Mode */
+#define     AT91C_TDES_SMOD_MANUAL    ( ( unsigned int ) 0x0 << 8 )  /* (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. */
+#define     AT91C_TDES_SMOD_AUTO      ( ( unsigned int ) 0x1 << 8 )  /* (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). */
+#define     AT91C_TDES_SMOD_PDC       ( ( unsigned int ) 0x2 << 8 )  /* (TDES) PDC Mode (cf datasheet). */
+#define AT91C_TDES_OPMOD              ( ( unsigned int ) 0x3 << 12 ) /* (TDES) Operation Mode */
+#define     AT91C_TDES_OPMOD_ECB      ( ( unsigned int ) 0x0 << 12 ) /* (TDES) ECB Electronic CodeBook mode. */
+#define     AT91C_TDES_OPMOD_CBC      ( ( unsigned int ) 0x1 << 12 ) /* (TDES) CBC Cipher Block Chaining mode. */
+#define     AT91C_TDES_OPMOD_OFB      ( ( unsigned int ) 0x2 << 12 ) /* (TDES) OFB Output Feedback mode. */
+#define     AT91C_TDES_OPMOD_CFB      ( ( unsigned int ) 0x3 << 12 ) /* (TDES) CFB Cipher Feedback mode. */
+#define AT91C_TDES_LOD                ( ( unsigned int ) 0x1 << 15 ) /* (TDES) Last Output Data Mode */
+#define AT91C_TDES_CFBS               ( ( unsigned int ) 0x3 << 16 ) /* (TDES) Cipher Feedback Data Size */
+#define     AT91C_TDES_CFBS_64_BIT    ( ( unsigned int ) 0x0 << 16 ) /* (TDES) 64-bit. */
+#define     AT91C_TDES_CFBS_32_BIT    ( ( unsigned int ) 0x1 << 16 ) /* (TDES) 32-bit. */
+#define     AT91C_TDES_CFBS_16_BIT    ( ( unsigned int ) 0x2 << 16 ) /* (TDES) 16-bit. */
+#define     AT91C_TDES_CFBS_8_BIT     ( ( unsigned int ) 0x3 << 16 ) /* (TDES) 8-bit. */
+/* -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- */
+#define AT91C_TDES_DATRDY             ( ( unsigned int ) 0x1 << 0 )  /* (TDES) DATRDY */
+#define AT91C_TDES_ENDRX              ( ( unsigned int ) 0x1 << 1 )  /* (TDES) PDC Read Buffer End */
+#define AT91C_TDES_ENDTX              ( ( unsigned int ) 0x1 << 2 )  /* (TDES) PDC Write Buffer End */
+#define AT91C_TDES_RXBUFF             ( ( unsigned int ) 0x1 << 3 )  /* (TDES) PDC Read Buffer Full */
+#define AT91C_TDES_TXBUFE             ( ( unsigned int ) 0x1 << 4 )  /* (TDES) PDC Write Buffer Empty */
+#define AT91C_TDES_URAD               ( ( unsigned int ) 0x1 << 8 )  /* (TDES) Unspecified Register Access Detection */
+/* -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- */
+/* -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- */
+/* -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- */
+#define AT91C_TDES_URAT                              ( ( unsigned int ) 0x3 << 12 ) /* (TDES) Unspecified Register Access Type Status */
+#define     AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC     ( ( unsigned int ) 0x0 << 12 ) /* (TDES) Input data register written during the data processing in PDC mode. */
+#define     AT91C_TDES_URAT_OUT_DAT_READ_DATPROC     ( ( unsigned int ) 0x1 << 12 ) /* (TDES) Output data register read during the data processing. */
+#define     AT91C_TDES_URAT_MODEREG_WRITE_DATPROC    ( ( unsigned int ) 0x2 << 12 ) /* (TDES) Mode register written during the data processing. */
+#define     AT91C_TDES_URAT_WO_REG_READ              ( ( unsigned int ) 0x3 << 12 ) /* (TDES) Write-only register read access. */
+
+/* ***************************************************************************** */
+/*               REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 */
+/* ***************************************************************************** */
+/* ========== Register definition for SYS peripheral ========== */
+/* ========== Register definition for AIC peripheral ========== */
+#define AT91C_AIC_IVR              ( ( AT91_REG * ) 0xFFFFF100 ) /* (AIC) IRQ Vector Register */
+#define AT91C_AIC_SMR              ( ( AT91_REG * ) 0xFFFFF000 ) /* (AIC) Source Mode Register */
+#define AT91C_AIC_FVR              ( ( AT91_REG * ) 0xFFFFF104 ) /* (AIC) FIQ Vector Register */
+#define AT91C_AIC_DCR              ( ( AT91_REG * ) 0xFFFFF138 ) /* (AIC) Debug Control Register (Protect) */
+#define AT91C_AIC_EOICR            ( ( AT91_REG * ) 0xFFFFF130 ) /* (AIC) End of Interrupt Command Register */
+#define AT91C_AIC_SVR              ( ( AT91_REG * ) 0xFFFFF080 ) /* (AIC) Source Vector Register */
+#define AT91C_AIC_FFSR             ( ( AT91_REG * ) 0xFFFFF148 ) /* (AIC) Fast Forcing Status Register */
+#define AT91C_AIC_ICCR             ( ( AT91_REG * ) 0xFFFFF128 ) /* (AIC) Interrupt Clear Command Register */
+#define AT91C_AIC_ISR              ( ( AT91_REG * ) 0xFFFFF108 ) /* (AIC) Interrupt Status Register */
+#define AT91C_AIC_IMR              ( ( AT91_REG * ) 0xFFFFF110 ) /* (AIC) Interrupt Mask Register */
+#define AT91C_AIC_IPR              ( ( AT91_REG * ) 0xFFFFF10C ) /* (AIC) Interrupt Pending Register */
+#define AT91C_AIC_FFER             ( ( AT91_REG * ) 0xFFFFF140 ) /* (AIC) Fast Forcing Enable Register */
+#define AT91C_AIC_IECR             ( ( AT91_REG * ) 0xFFFFF120 ) /* (AIC) Interrupt Enable Command Register */
+#define AT91C_AIC_ISCR             ( ( AT91_REG * ) 0xFFFFF12C ) /* (AIC) Interrupt Set Command Register */
+#define AT91C_AIC_FFDR             ( ( AT91_REG * ) 0xFFFFF144 ) /* (AIC) Fast Forcing Disable Register */
+#define AT91C_AIC_CISR             ( ( AT91_REG * ) 0xFFFFF114 ) /* (AIC) Core Interrupt Status Register */
+#define AT91C_AIC_IDCR             ( ( AT91_REG * ) 0xFFFFF124 ) /* (AIC) Interrupt Disable Command Register */
+#define AT91C_AIC_SPU              ( ( AT91_REG * ) 0xFFFFF134 ) /* (AIC) Spurious Vector Register */
+/* ========== Register definition for PDC_DBGU peripheral ========== */
+#define AT91C_DBGU_TCR             ( ( AT91_REG * ) 0xFFFFF30C ) /* (PDC_DBGU) Transmit Counter Register */
+#define AT91C_DBGU_RNPR            ( ( AT91_REG * ) 0xFFFFF310 ) /* (PDC_DBGU) Receive Next Pointer Register */
+#define AT91C_DBGU_TNPR            ( ( AT91_REG * ) 0xFFFFF318 ) /* (PDC_DBGU) Transmit Next Pointer Register */
+#define AT91C_DBGU_TPR             ( ( AT91_REG * ) 0xFFFFF308 ) /* (PDC_DBGU) Transmit Pointer Register */
+#define AT91C_DBGU_RPR             ( ( AT91_REG * ) 0xFFFFF300 ) /* (PDC_DBGU) Receive Pointer Register */
+#define AT91C_DBGU_RCR             ( ( AT91_REG * ) 0xFFFFF304 ) /* (PDC_DBGU) Receive Counter Register */
+#define AT91C_DBGU_RNCR            ( ( AT91_REG * ) 0xFFFFF314 ) /* (PDC_DBGU) Receive Next Counter Register */
+#define AT91C_DBGU_PTCR            ( ( AT91_REG * ) 0xFFFFF320 ) /* (PDC_DBGU) PDC Transfer Control Register */
+#define AT91C_DBGU_PTSR            ( ( AT91_REG * ) 0xFFFFF324 ) /* (PDC_DBGU) PDC Transfer Status Register */
+#define AT91C_DBGU_TNCR            ( ( AT91_REG * ) 0xFFFFF31C ) /* (PDC_DBGU) Transmit Next Counter Register */
+/* ========== Register definition for DBGU peripheral ========== */
+#define AT91C_DBGU_EXID            ( ( AT91_REG * ) 0xFFFFF244 ) /* (DBGU) Chip ID Extension Register */
+#define AT91C_DBGU_BRGR            ( ( AT91_REG * ) 0xFFFFF220 ) /* (DBGU) Baud Rate Generator Register */
+#define AT91C_DBGU_IDR             ( ( AT91_REG * ) 0xFFFFF20C ) /* (DBGU) Interrupt Disable Register */
+#define AT91C_DBGU_CSR             ( ( AT91_REG * ) 0xFFFFF214 ) /* (DBGU) Channel Status Register */
+#define AT91C_DBGU_CIDR            ( ( AT91_REG * ) 0xFFFFF240 ) /* (DBGU) Chip ID Register */
+#define AT91C_DBGU_MR              ( ( AT91_REG * ) 0xFFFFF204 ) /* (DBGU) Mode Register */
+#define AT91C_DBGU_IMR             ( ( AT91_REG * ) 0xFFFFF210 ) /* (DBGU) Interrupt Mask Register */
+#define AT91C_DBGU_CR              ( ( AT91_REG * ) 0xFFFFF200 ) /* (DBGU) Control Register */
+#define AT91C_DBGU_FNTR            ( ( AT91_REG * ) 0xFFFFF248 ) /* (DBGU) Force NTRST Register */
+#define AT91C_DBGU_THR             ( ( AT91_REG * ) 0xFFFFF21C ) /* (DBGU) Transmitter Holding Register */
+#define AT91C_DBGU_RHR             ( ( AT91_REG * ) 0xFFFFF218 ) /* (DBGU) Receiver Holding Register */
+#define AT91C_DBGU_IER             ( ( AT91_REG * ) 0xFFFFF208 ) /* (DBGU) Interrupt Enable Register */
+/* ========== Register definition for PIOA peripheral ========== */
+#define AT91C_PIOA_ODR             ( ( AT91_REG * ) 0xFFFFF414 ) /* (PIOA) Output Disable Registerr */
+#define AT91C_PIOA_SODR            ( ( AT91_REG * ) 0xFFFFF430 ) /* (PIOA) Set Output Data Register */
+#define AT91C_PIOA_ISR             ( ( AT91_REG * ) 0xFFFFF44C ) /* (PIOA) Interrupt Status Register */
+#define AT91C_PIOA_ABSR            ( ( AT91_REG * ) 0xFFFFF478 ) /* (PIOA) AB Select Status Register */
+#define AT91C_PIOA_IER             ( ( AT91_REG * ) 0xFFFFF440 ) /* (PIOA) Interrupt Enable Register */
+#define AT91C_PIOA_PPUDR           ( ( AT91_REG * ) 0xFFFFF460 ) /* (PIOA) Pull-up Disable Register */
+#define AT91C_PIOA_IMR             ( ( AT91_REG * ) 0xFFFFF448 ) /* (PIOA) Interrupt Mask Register */
+#define AT91C_PIOA_PER             ( ( AT91_REG * ) 0xFFFFF400 ) /* (PIOA) PIO Enable Register */
+#define AT91C_PIOA_IFDR            ( ( AT91_REG * ) 0xFFFFF424 ) /* (PIOA) Input Filter Disable Register */
+#define AT91C_PIOA_OWDR            ( ( AT91_REG * ) 0xFFFFF4A4 ) /* (PIOA) Output Write Disable Register */
+#define AT91C_PIOA_MDSR            ( ( AT91_REG * ) 0xFFFFF458 ) /* (PIOA) Multi-driver Status Register */
+#define AT91C_PIOA_IDR             ( ( AT91_REG * ) 0xFFFFF444 ) /* (PIOA) Interrupt Disable Register */
+#define AT91C_PIOA_ODSR            ( ( AT91_REG * ) 0xFFFFF438 ) /* (PIOA) Output Data Status Register */
+#define AT91C_PIOA_PPUSR           ( ( AT91_REG * ) 0xFFFFF468 ) /* (PIOA) Pull-up Status Register */
+#define AT91C_PIOA_OWSR            ( ( AT91_REG * ) 0xFFFFF4A8 ) /* (PIOA) Output Write Status Register */
+#define AT91C_PIOA_BSR             ( ( AT91_REG * ) 0xFFFFF474 ) /* (PIOA) Select B Register */
+#define AT91C_PIOA_OWER            ( ( AT91_REG * ) 0xFFFFF4A0 ) /* (PIOA) Output Write Enable Register */
+#define AT91C_PIOA_IFER            ( ( AT91_REG * ) 0xFFFFF420 ) /* (PIOA) Input Filter Enable Register */
+#define AT91C_PIOA_PDSR            ( ( AT91_REG * ) 0xFFFFF43C ) /* (PIOA) Pin Data Status Register */
+#define AT91C_PIOA_PPUER           ( ( AT91_REG * ) 0xFFFFF464 ) /* (PIOA) Pull-up Enable Register */
+#define AT91C_PIOA_OSR             ( ( AT91_REG * ) 0xFFFFF418 ) /* (PIOA) Output Status Register */
+#define AT91C_PIOA_ASR             ( ( AT91_REG * ) 0xFFFFF470 ) /* (PIOA) Select A Register */
+#define AT91C_PIOA_MDDR            ( ( AT91_REG * ) 0xFFFFF454 ) /* (PIOA) Multi-driver Disable Register */
+#define AT91C_PIOA_CODR            ( ( AT91_REG * ) 0xFFFFF434 ) /* (PIOA) Clear Output Data Register */
+#define AT91C_PIOA_MDER            ( ( AT91_REG * ) 0xFFFFF450 ) /* (PIOA) Multi-driver Enable Register */
+#define AT91C_PIOA_PDR             ( ( AT91_REG * ) 0xFFFFF404 ) /* (PIOA) PIO Disable Register */
+#define AT91C_PIOA_IFSR            ( ( AT91_REG * ) 0xFFFFF428 ) /* (PIOA) Input Filter Status Register */
+#define AT91C_PIOA_OER             ( ( AT91_REG * ) 0xFFFFF410 ) /* (PIOA) Output Enable Register */
+#define AT91C_PIOA_PSR             ( ( AT91_REG * ) 0xFFFFF408 ) /* (PIOA) PIO Status Register */
+/* ========== Register definition for PIOB peripheral ========== */
+#define AT91C_PIOB_OWDR            ( ( AT91_REG * ) 0xFFFFF6A4 ) /* (PIOB) Output Write Disable Register */
+#define AT91C_PIOB_MDER            ( ( AT91_REG * ) 0xFFFFF650 ) /* (PIOB) Multi-driver Enable Register */
+#define AT91C_PIOB_PPUSR           ( ( AT91_REG * ) 0xFFFFF668 ) /* (PIOB) Pull-up Status Register */
+#define AT91C_PIOB_IMR             ( ( AT91_REG * ) 0xFFFFF648 ) /* (PIOB) Interrupt Mask Register */
+#define AT91C_PIOB_ASR             ( ( AT91_REG * ) 0xFFFFF670 ) /* (PIOB) Select A Register */
+#define AT91C_PIOB_PPUDR           ( ( AT91_REG * ) 0xFFFFF660 ) /* (PIOB) Pull-up Disable Register */
+#define AT91C_PIOB_PSR             ( ( AT91_REG * ) 0xFFFFF608 ) /* (PIOB) PIO Status Register */
+#define AT91C_PIOB_IER             ( ( AT91_REG * ) 0xFFFFF640 ) /* (PIOB) Interrupt Enable Register */
+#define AT91C_PIOB_CODR            ( ( AT91_REG * ) 0xFFFFF634 ) /* (PIOB) Clear Output Data Register */
+#define AT91C_PIOB_OWER            ( ( AT91_REG * ) 0xFFFFF6A0 ) /* (PIOB) Output Write Enable Register */
+#define AT91C_PIOB_ABSR            ( ( AT91_REG * ) 0xFFFFF678 ) /* (PIOB) AB Select Status Register */
+#define AT91C_PIOB_IFDR            ( ( AT91_REG * ) 0xFFFFF624 ) /* (PIOB) Input Filter Disable Register */
+#define AT91C_PIOB_PDSR            ( ( AT91_REG * ) 0xFFFFF63C ) /* (PIOB) Pin Data Status Register */
+#define AT91C_PIOB_IDR             ( ( AT91_REG * ) 0xFFFFF644 ) /* (PIOB) Interrupt Disable Register */
+#define AT91C_PIOB_OWSR            ( ( AT91_REG * ) 0xFFFFF6A8 ) /* (PIOB) Output Write Status Register */
+#define AT91C_PIOB_PDR             ( ( AT91_REG * ) 0xFFFFF604 ) /* (PIOB) PIO Disable Register */
+#define AT91C_PIOB_ODR             ( ( AT91_REG * ) 0xFFFFF614 ) /* (PIOB) Output Disable Registerr */
+#define AT91C_PIOB_IFSR            ( ( AT91_REG * ) 0xFFFFF628 ) /* (PIOB) Input Filter Status Register */
+#define AT91C_PIOB_PPUER           ( ( AT91_REG * ) 0xFFFFF664 ) /* (PIOB) Pull-up Enable Register */
+#define AT91C_PIOB_SODR            ( ( AT91_REG * ) 0xFFFFF630 ) /* (PIOB) Set Output Data Register */
+#define AT91C_PIOB_ISR             ( ( AT91_REG * ) 0xFFFFF64C ) /* (PIOB) Interrupt Status Register */
+#define AT91C_PIOB_ODSR            ( ( AT91_REG * ) 0xFFFFF638 ) /* (PIOB) Output Data Status Register */
+#define AT91C_PIOB_OSR             ( ( AT91_REG * ) 0xFFFFF618 ) /* (PIOB) Output Status Register */
+#define AT91C_PIOB_MDSR            ( ( AT91_REG * ) 0xFFFFF658 ) /* (PIOB) Multi-driver Status Register */
+#define AT91C_PIOB_IFER            ( ( AT91_REG * ) 0xFFFFF620 ) /* (PIOB) Input Filter Enable Register */
+#define AT91C_PIOB_BSR             ( ( AT91_REG * ) 0xFFFFF674 ) /* (PIOB) Select B Register */
+#define AT91C_PIOB_MDDR            ( ( AT91_REG * ) 0xFFFFF654 ) /* (PIOB) Multi-driver Disable Register */
+#define AT91C_PIOB_OER             ( ( AT91_REG * ) 0xFFFFF610 ) /* (PIOB) Output Enable Register */
+#define AT91C_PIOB_PER             ( ( AT91_REG * ) 0xFFFFF600 ) /* (PIOB) PIO Enable Register */
+/* ========== Register definition for CKGR peripheral ========== */
+#define AT91C_CKGR_MOR             ( ( AT91_REG * ) 0xFFFFFC20 ) /* (CKGR) Main Oscillator Register */
+#define AT91C_CKGR_PLLR            ( ( AT91_REG * ) 0xFFFFFC2C ) /* (CKGR) PLL Register */
+#define AT91C_CKGR_MCFR            ( ( AT91_REG * ) 0xFFFFFC24 ) /* (CKGR) Main Clock  Frequency Register */
+/* ========== Register definition for PMC peripheral ========== */
+#define AT91C_PMC_IDR              ( ( AT91_REG * ) 0xFFFFFC64 ) /* (PMC) Interrupt Disable Register */
+#define AT91C_PMC_MOR              ( ( AT91_REG * ) 0xFFFFFC20 ) /* (PMC) Main Oscillator Register */
+#define AT91C_PMC_PLLR             ( ( AT91_REG * ) 0xFFFFFC2C ) /* (PMC) PLL Register */
+#define AT91C_PMC_PCER             ( ( AT91_REG * ) 0xFFFFFC10 ) /* (PMC) Peripheral Clock Enable Register */
+#define AT91C_PMC_PCKR             ( ( AT91_REG * ) 0xFFFFFC40 ) /* (PMC) Programmable Clock Register */
+#define AT91C_PMC_MCKR             ( ( AT91_REG * ) 0xFFFFFC30 ) /* (PMC) Master Clock Register */
+#define AT91C_PMC_SCDR             ( ( AT91_REG * ) 0xFFFFFC04 ) /* (PMC) System Clock Disable Register */
+#define AT91C_PMC_PCDR             ( ( AT91_REG * ) 0xFFFFFC14 ) /* (PMC) Peripheral Clock Disable Register */
+#define AT91C_PMC_SCSR             ( ( AT91_REG * ) 0xFFFFFC08 ) /* (PMC) System Clock Status Register */
+#define AT91C_PMC_PCSR             ( ( AT91_REG * ) 0xFFFFFC18 ) /* (PMC) Peripheral Clock Status Register */
+#define AT91C_PMC_MCFR             ( ( AT91_REG * ) 0xFFFFFC24 ) /* (PMC) Main Clock  Frequency Register */
+#define AT91C_PMC_SCER             ( ( AT91_REG * ) 0xFFFFFC00 ) /* (PMC) System Clock Enable Register */
+#define AT91C_PMC_IMR              ( ( AT91_REG * ) 0xFFFFFC6C ) /* (PMC) Interrupt Mask Register */
+#define AT91C_PMC_IER              ( ( AT91_REG * ) 0xFFFFFC60 ) /* (PMC) Interrupt Enable Register */
+#define AT91C_PMC_SR               ( ( AT91_REG * ) 0xFFFFFC68 ) /* (PMC) Status Register */
+/* ========== Register definition for RSTC peripheral ========== */
+#define AT91C_RSTC_RCR             ( ( AT91_REG * ) 0xFFFFFD00 ) /* (RSTC) Reset Control Register */
+#define AT91C_RSTC_RMR             ( ( AT91_REG * ) 0xFFFFFD08 ) /* (RSTC) Reset Mode Register */
+#define AT91C_RSTC_RSR             ( ( AT91_REG * ) 0xFFFFFD04 ) /* (RSTC) Reset Status Register */
+/* ========== Register definition for RTTC peripheral ========== */
+#define AT91C_RTTC_RTSR            ( ( AT91_REG * ) 0xFFFFFD2C ) /* (RTTC) Real-time Status Register */
+#define AT91C_RTTC_RTMR            ( ( AT91_REG * ) 0xFFFFFD20 ) /* (RTTC) Real-time Mode Register */
+#define AT91C_RTTC_RTVR            ( ( AT91_REG * ) 0xFFFFFD28 ) /* (RTTC) Real-time Value Register */
+#define AT91C_RTTC_RTAR            ( ( AT91_REG * ) 0xFFFFFD24 ) /* (RTTC) Real-time Alarm Register */
+/* ========== Register definition for PITC peripheral ========== */
+#define AT91C_PITC_PIVR            ( ( AT91_REG * ) 0xFFFFFD38 ) /* (PITC) Period Interval Value Register */
+#define AT91C_PITC_PISR            ( ( AT91_REG * ) 0xFFFFFD34 ) /* (PITC) Period Interval Status Register */
+#define AT91C_PITC_PIIR            ( ( AT91_REG * ) 0xFFFFFD3C ) /* (PITC) Period Interval Image Register */
+#define AT91C_PITC_PIMR            ( ( AT91_REG * ) 0xFFFFFD30 ) /* (PITC) Period Interval Mode Register */
+/* ========== Register definition for WDTC peripheral ========== */
+#define AT91C_WDTC_WDCR            ( ( AT91_REG * ) 0xFFFFFD40 ) /* (WDTC) Watchdog Control Register */
+#define AT91C_WDTC_WDSR            ( ( AT91_REG * ) 0xFFFFFD48 ) /* (WDTC) Watchdog Status Register */
+#define AT91C_WDTC_WDMR            ( ( AT91_REG * ) 0xFFFFFD44 ) /* (WDTC) Watchdog Mode Register */
+/* ========== Register definition for VREG peripheral ========== */
+#define AT91C_VREG_MR              ( ( AT91_REG * ) 0xFFFFFD60 ) /* (VREG) Voltage Regulator Mode Register */
+/* ========== Register definition for MC peripheral ========== */
+#define AT91C_MC_ASR               ( ( AT91_REG * ) 0xFFFFFF04 ) /* (MC) MC Abort Status Register */
+#define AT91C_MC_RCR               ( ( AT91_REG * ) 0xFFFFFF00 ) /* (MC) MC Remap Control Register */
+#define AT91C_MC_FCR               ( ( AT91_REG * ) 0xFFFFFF64 ) /* (MC) MC Flash Command Register */
+#define AT91C_MC_AASR              ( ( AT91_REG * ) 0xFFFFFF08 ) /* (MC) MC Abort Address Status Register */
+#define AT91C_MC_FSR               ( ( AT91_REG * ) 0xFFFFFF68 ) /* (MC) MC Flash Status Register */
+#define AT91C_MC_FMR               ( ( AT91_REG * ) 0xFFFFFF60 ) /* (MC) MC Flash Mode Register */
+/* ========== Register definition for PDC_SPI1 peripheral ========== */
+#define AT91C_SPI1_PTCR            ( ( AT91_REG * ) 0xFFFE4120 ) /* (PDC_SPI1) PDC Transfer Control Register */
+#define AT91C_SPI1_RPR             ( ( AT91_REG * ) 0xFFFE4100 ) /* (PDC_SPI1) Receive Pointer Register */
+#define AT91C_SPI1_TNCR            ( ( AT91_REG * ) 0xFFFE411C ) /* (PDC_SPI1) Transmit Next Counter Register */
+#define AT91C_SPI1_TPR             ( ( AT91_REG * ) 0xFFFE4108 ) /* (PDC_SPI1) Transmit Pointer Register */
+#define AT91C_SPI1_TNPR            ( ( AT91_REG * ) 0xFFFE4118 ) /* (PDC_SPI1) Transmit Next Pointer Register */
+#define AT91C_SPI1_TCR             ( ( AT91_REG * ) 0xFFFE410C ) /* (PDC_SPI1) Transmit Counter Register */
+#define AT91C_SPI1_RCR             ( ( AT91_REG * ) 0xFFFE4104 ) /* (PDC_SPI1) Receive Counter Register */
+#define AT91C_SPI1_RNPR            ( ( AT91_REG * ) 0xFFFE4110 ) /* (PDC_SPI1) Receive Next Pointer Register */
+#define AT91C_SPI1_RNCR            ( ( AT91_REG * ) 0xFFFE4114 ) /* (PDC_SPI1) Receive Next Counter Register */
+#define AT91C_SPI1_PTSR            ( ( AT91_REG * ) 0xFFFE4124 ) /* (PDC_SPI1) PDC Transfer Status Register */
+/* ========== Register definition for SPI1 peripheral ========== */
+#define AT91C_SPI1_IMR             ( ( AT91_REG * ) 0xFFFE401C ) /* (SPI1) Interrupt Mask Register */
+#define AT91C_SPI1_IER             ( ( AT91_REG * ) 0xFFFE4014 ) /* (SPI1) Interrupt Enable Register */
+#define AT91C_SPI1_MR              ( ( AT91_REG * ) 0xFFFE4004 ) /* (SPI1) Mode Register */
+#define AT91C_SPI1_RDR             ( ( AT91_REG * ) 0xFFFE4008 ) /* (SPI1) Receive Data Register */
+#define AT91C_SPI1_IDR             ( ( AT91_REG * ) 0xFFFE4018 ) /* (SPI1) Interrupt Disable Register */
+#define AT91C_SPI1_SR              ( ( AT91_REG * ) 0xFFFE4010 ) /* (SPI1) Status Register */
+#define AT91C_SPI1_TDR             ( ( AT91_REG * ) 0xFFFE400C ) /* (SPI1) Transmit Data Register */
+#define AT91C_SPI1_CR              ( ( AT91_REG * ) 0xFFFE4000 ) /* (SPI1) Control Register */
+#define AT91C_SPI1_CSR             ( ( AT91_REG * ) 0xFFFE4030 ) /* (SPI1) Chip Select Register */
+/* ========== Register definition for PDC_SPI0 peripheral ========== */
+#define AT91C_SPI0_PTCR            ( ( AT91_REG * ) 0xFFFE0120 ) /* (PDC_SPI0) PDC Transfer Control Register */
+#define AT91C_SPI0_TPR             ( ( AT91_REG * ) 0xFFFE0108 ) /* (PDC_SPI0) Transmit Pointer Register */
+#define AT91C_SPI0_TCR             ( ( AT91_REG * ) 0xFFFE010C ) /* (PDC_SPI0) Transmit Counter Register */
+#define AT91C_SPI0_RCR             ( ( AT91_REG * ) 0xFFFE0104 ) /* (PDC_SPI0) Receive Counter Register */
+#define AT91C_SPI0_PTSR            ( ( AT91_REG * ) 0xFFFE0124 ) /* (PDC_SPI0) PDC Transfer Status Register */
+#define AT91C_SPI0_RNPR            ( ( AT91_REG * ) 0xFFFE0110 ) /* (PDC_SPI0) Receive Next Pointer Register */
+#define AT91C_SPI0_RPR             ( ( AT91_REG * ) 0xFFFE0100 ) /* (PDC_SPI0) Receive Pointer Register */
+#define AT91C_SPI0_TNCR            ( ( AT91_REG * ) 0xFFFE011C ) /* (PDC_SPI0) Transmit Next Counter Register */
+#define AT91C_SPI0_RNCR            ( ( AT91_REG * ) 0xFFFE0114 ) /* (PDC_SPI0) Receive Next Counter Register */
+#define AT91C_SPI0_TNPR            ( ( AT91_REG * ) 0xFFFE0118 ) /* (PDC_SPI0) Transmit Next Pointer Register */
+/* ========== Register definition for SPI0 peripheral ========== */
+#define AT91C_SPI0_IER             ( ( AT91_REG * ) 0xFFFE0014 ) /* (SPI0) Interrupt Enable Register */
+#define AT91C_SPI0_SR              ( ( AT91_REG * ) 0xFFFE0010 ) /* (SPI0) Status Register */
+#define AT91C_SPI0_IDR             ( ( AT91_REG * ) 0xFFFE0018 ) /* (SPI0) Interrupt Disable Register */
+#define AT91C_SPI0_CR              ( ( AT91_REG * ) 0xFFFE0000 ) /* (SPI0) Control Register */
+#define AT91C_SPI0_MR              ( ( AT91_REG * ) 0xFFFE0004 ) /* (SPI0) Mode Register */
+#define AT91C_SPI0_IMR             ( ( AT91_REG * ) 0xFFFE001C ) /* (SPI0) Interrupt Mask Register */
+#define AT91C_SPI0_TDR             ( ( AT91_REG * ) 0xFFFE000C ) /* (SPI0) Transmit Data Register */
+#define AT91C_SPI0_RDR             ( ( AT91_REG * ) 0xFFFE0008 ) /* (SPI0) Receive Data Register */
+#define AT91C_SPI0_CSR             ( ( AT91_REG * ) 0xFFFE0030 ) /* (SPI0) Chip Select Register */
+/* ========== Register definition for PDC_US1 peripheral ========== */
+#define AT91C_US1_RNCR             ( ( AT91_REG * ) 0xFFFC4114 ) /* (PDC_US1) Receive Next Counter Register */
+#define AT91C_US1_PTCR             ( ( AT91_REG * ) 0xFFFC4120 ) /* (PDC_US1) PDC Transfer Control Register */
+#define AT91C_US1_TCR              ( ( AT91_REG * ) 0xFFFC410C ) /* (PDC_US1) Transmit Counter Register */
+#define AT91C_US1_PTSR             ( ( AT91_REG * ) 0xFFFC4124 ) /* (PDC_US1) PDC Transfer Status Register */
+#define AT91C_US1_TNPR             ( ( AT91_REG * ) 0xFFFC4118 ) /* (PDC_US1) Transmit Next Pointer Register */
+#define AT91C_US1_RCR              ( ( AT91_REG * ) 0xFFFC4104 ) /* (PDC_US1) Receive Counter Register */
+#define AT91C_US1_RNPR             ( ( AT91_REG * ) 0xFFFC4110 ) /* (PDC_US1) Receive Next Pointer Register */
+#define AT91C_US1_RPR              ( ( AT91_REG * ) 0xFFFC4100 ) /* (PDC_US1) Receive Pointer Register */
+#define AT91C_US1_TNCR             ( ( AT91_REG * ) 0xFFFC411C ) /* (PDC_US1) Transmit Next Counter Register */
+#define AT91C_US1_TPR              ( ( AT91_REG * ) 0xFFFC4108 ) /* (PDC_US1) Transmit Pointer Register */
+/* ========== Register definition for US1 peripheral ========== */
+#define AT91C_US1_IF               ( ( AT91_REG * ) 0xFFFC404C ) /* (US1) IRDA_FILTER Register */
+#define AT91C_US1_NER              ( ( AT91_REG * ) 0xFFFC4044 ) /* (US1) Nb Errors Register */
+#define AT91C_US1_RTOR             ( ( AT91_REG * ) 0xFFFC4024 ) /* (US1) Receiver Time-out Register */
+#define AT91C_US1_CSR              ( ( AT91_REG * ) 0xFFFC4014 ) /* (US1) Channel Status Register */
+#define AT91C_US1_IDR              ( ( AT91_REG * ) 0xFFFC400C ) /* (US1) Interrupt Disable Register */
+#define AT91C_US1_IER              ( ( AT91_REG * ) 0xFFFC4008 ) /* (US1) Interrupt Enable Register */
+#define AT91C_US1_THR              ( ( AT91_REG * ) 0xFFFC401C ) /* (US1) Transmitter Holding Register */
+#define AT91C_US1_TTGR             ( ( AT91_REG * ) 0xFFFC4028 ) /* (US1) Transmitter Time-guard Register */
+#define AT91C_US1_RHR              ( ( AT91_REG * ) 0xFFFC4018 ) /* (US1) Receiver Holding Register */
+#define AT91C_US1_BRGR             ( ( AT91_REG * ) 0xFFFC4020 ) /* (US1) Baud Rate Generator Register */
+#define AT91C_US1_IMR              ( ( AT91_REG * ) 0xFFFC4010 ) /* (US1) Interrupt Mask Register */
+#define AT91C_US1_FIDI             ( ( AT91_REG * ) 0xFFFC4040 ) /* (US1) FI_DI_Ratio Register */
+#define AT91C_US1_CR               ( ( AT91_REG * ) 0xFFFC4000 ) /* (US1) Control Register */
+#define AT91C_US1_MR               ( ( AT91_REG * ) 0xFFFC4004 ) /* (US1) Mode Register */
+/* ========== Register definition for PDC_US0 peripheral ========== */
+#define AT91C_US0_TNPR             ( ( AT91_REG * ) 0xFFFC0118 ) /* (PDC_US0) Transmit Next Pointer Register */
+#define AT91C_US0_RNPR             ( ( AT91_REG * ) 0xFFFC0110 ) /* (PDC_US0) Receive Next Pointer Register */
+#define AT91C_US0_TCR              ( ( AT91_REG * ) 0xFFFC010C ) /* (PDC_US0) Transmit Counter Register */
+#define AT91C_US0_PTCR             ( ( AT91_REG * ) 0xFFFC0120 ) /* (PDC_US0) PDC Transfer Control Register */
+#define AT91C_US0_PTSR             ( ( AT91_REG * ) 0xFFFC0124 ) /* (PDC_US0) PDC Transfer Status Register */
+#define AT91C_US0_TNCR             ( ( AT91_REG * ) 0xFFFC011C ) /* (PDC_US0) Transmit Next Counter Register */
+#define AT91C_US0_TPR              ( ( AT91_REG * ) 0xFFFC0108 ) /* (PDC_US0) Transmit Pointer Register */
+#define AT91C_US0_RCR              ( ( AT91_REG * ) 0xFFFC0104 ) /* (PDC_US0) Receive Counter Register */
+#define AT91C_US0_RPR              ( ( AT91_REG * ) 0xFFFC0100 ) /* (PDC_US0) Receive Pointer Register */
+#define AT91C_US0_RNCR             ( ( AT91_REG * ) 0xFFFC0114 ) /* (PDC_US0) Receive Next Counter Register */
+/* ========== Register definition for US0 peripheral ========== */
+#define AT91C_US0_BRGR             ( ( AT91_REG * ) 0xFFFC0020 ) /* (US0) Baud Rate Generator Register */
+#define AT91C_US0_NER              ( ( AT91_REG * ) 0xFFFC0044 ) /* (US0) Nb Errors Register */
+#define AT91C_US0_CR               ( ( AT91_REG * ) 0xFFFC0000 ) /* (US0) Control Register */
+#define AT91C_US0_IMR              ( ( AT91_REG * ) 0xFFFC0010 ) /* (US0) Interrupt Mask Register */
+#define AT91C_US0_FIDI             ( ( AT91_REG * ) 0xFFFC0040 ) /* (US0) FI_DI_Ratio Register */
+#define AT91C_US0_TTGR             ( ( AT91_REG * ) 0xFFFC0028 ) /* (US0) Transmitter Time-guard Register */
+#define AT91C_US0_MR               ( ( AT91_REG * ) 0xFFFC0004 ) /* (US0) Mode Register */
+#define AT91C_US0_RTOR             ( ( AT91_REG * ) 0xFFFC0024 ) /* (US0) Receiver Time-out Register */
+#define AT91C_US0_CSR              ( ( AT91_REG * ) 0xFFFC0014 ) /* (US0) Channel Status Register */
+#define AT91C_US0_RHR              ( ( AT91_REG * ) 0xFFFC0018 ) /* (US0) Receiver Holding Register */
+#define AT91C_US0_IDR              ( ( AT91_REG * ) 0xFFFC000C ) /* (US0) Interrupt Disable Register */
+#define AT91C_US0_THR              ( ( AT91_REG * ) 0xFFFC001C ) /* (US0) Transmitter Holding Register */
+#define AT91C_US0_IF               ( ( AT91_REG * ) 0xFFFC004C ) /* (US0) IRDA_FILTER Register */
+#define AT91C_US0_IER              ( ( AT91_REG * ) 0xFFFC0008 ) /* (US0) Interrupt Enable Register */
+/* ========== Register definition for PDC_SSC peripheral ========== */
+#define AT91C_SSC_TNCR             ( ( AT91_REG * ) 0xFFFD411C ) /* (PDC_SSC) Transmit Next Counter Register */
+#define AT91C_SSC_RPR              ( ( AT91_REG * ) 0xFFFD4100 ) /* (PDC_SSC) Receive Pointer Register */
+#define AT91C_SSC_RNCR             ( ( AT91_REG * ) 0xFFFD4114 ) /* (PDC_SSC) Receive Next Counter Register */
+#define AT91C_SSC_TPR              ( ( AT91_REG * ) 0xFFFD4108 ) /* (PDC_SSC) Transmit Pointer Register */
+#define AT91C_SSC_PTCR             ( ( AT91_REG * ) 0xFFFD4120 ) /* (PDC_SSC) PDC Transfer Control Register */
+#define AT91C_SSC_TCR              ( ( AT91_REG * ) 0xFFFD410C ) /* (PDC_SSC) Transmit Counter Register */
+#define AT91C_SSC_RCR              ( ( AT91_REG * ) 0xFFFD4104 ) /* (PDC_SSC) Receive Counter Register */
+#define AT91C_SSC_RNPR             ( ( AT91_REG * ) 0xFFFD4110 ) /* (PDC_SSC) Receive Next Pointer Register */
+#define AT91C_SSC_TNPR             ( ( AT91_REG * ) 0xFFFD4118 ) /* (PDC_SSC) Transmit Next Pointer Register */
+#define AT91C_SSC_PTSR             ( ( AT91_REG * ) 0xFFFD4124 ) /* (PDC_SSC) PDC Transfer Status Register */
+/* ========== Register definition for SSC peripheral ========== */
+#define AT91C_SSC_RHR              ( ( AT91_REG * ) 0xFFFD4020 ) /* (SSC) Receive Holding Register */
+#define AT91C_SSC_RSHR             ( ( AT91_REG * ) 0xFFFD4030 ) /* (SSC) Receive Sync Holding Register */
+#define AT91C_SSC_TFMR             ( ( AT91_REG * ) 0xFFFD401C ) /* (SSC) Transmit Frame Mode Register */
+#define AT91C_SSC_IDR              ( ( AT91_REG * ) 0xFFFD4048 ) /* (SSC) Interrupt Disable Register */
+#define AT91C_SSC_THR              ( ( AT91_REG * ) 0xFFFD4024 ) /* (SSC) Transmit Holding Register */
+#define AT91C_SSC_RCMR             ( ( AT91_REG * ) 0xFFFD4010 ) /* (SSC) Receive Clock ModeRegister */
+#define AT91C_SSC_IER              ( ( AT91_REG * ) 0xFFFD4044 ) /* (SSC) Interrupt Enable Register */
+#define AT91C_SSC_TSHR             ( ( AT91_REG * ) 0xFFFD4034 ) /* (SSC) Transmit Sync Holding Register */
+#define AT91C_SSC_SR               ( ( AT91_REG * ) 0xFFFD4040 ) /* (SSC) Status Register */
+#define AT91C_SSC_CMR              ( ( AT91_REG * ) 0xFFFD4004 ) /* (SSC) Clock Mode Register */
+#define AT91C_SSC_TCMR             ( ( AT91_REG * ) 0xFFFD4018 ) /* (SSC) Transmit Clock Mode Register */
+#define AT91C_SSC_CR               ( ( AT91_REG * ) 0xFFFD4000 ) /* (SSC) Control Register */
+#define AT91C_SSC_IMR              ( ( AT91_REG * ) 0xFFFD404C ) /* (SSC) Interrupt Mask Register */
+#define AT91C_SSC_RFMR             ( ( AT91_REG * ) 0xFFFD4014 ) /* (SSC) Receive Frame Mode Register */
+/* ========== Register definition for TWI peripheral ========== */
+#define AT91C_TWI_IER              ( ( AT91_REG * ) 0xFFFB8024 ) /* (TWI) Interrupt Enable Register */
+#define AT91C_TWI_CR               ( ( AT91_REG * ) 0xFFFB8000 ) /* (TWI) Control Register */
+#define AT91C_TWI_SR               ( ( AT91_REG * ) 0xFFFB8020 ) /* (TWI) Status Register */
+#define AT91C_TWI_IMR              ( ( AT91_REG * ) 0xFFFB802C ) /* (TWI) Interrupt Mask Register */
+#define AT91C_TWI_THR              ( ( AT91_REG * ) 0xFFFB8034 ) /* (TWI) Transmit Holding Register */
+#define AT91C_TWI_IDR              ( ( AT91_REG * ) 0xFFFB8028 ) /* (TWI) Interrupt Disable Register */
+#define AT91C_TWI_IADR             ( ( AT91_REG * ) 0xFFFB800C ) /* (TWI) Internal Address Register */
+#define AT91C_TWI_MMR              ( ( AT91_REG * ) 0xFFFB8004 ) /* (TWI) Master Mode Register */
+#define AT91C_TWI_CWGR             ( ( AT91_REG * ) 0xFFFB8010 ) /* (TWI) Clock Waveform Generator Register */
+#define AT91C_TWI_RHR              ( ( AT91_REG * ) 0xFFFB8030 ) /* (TWI) Receive Holding Register */
+/* ========== Register definition for PWMC_CH3 peripheral ========== */
+#define AT91C_PWMC_CH3_CUPDR       ( ( AT91_REG * ) 0xFFFCC270 ) /* (PWMC_CH3) Channel Update Register */
+#define AT91C_PWMC_CH3_Reserved    ( ( AT91_REG * ) 0xFFFCC274 ) /* (PWMC_CH3) Reserved */
+#define AT91C_PWMC_CH3_CPRDR       ( ( AT91_REG * ) 0xFFFCC268 ) /* (PWMC_CH3) Channel Period Register */
+#define AT91C_PWMC_CH3_CDTYR       ( ( AT91_REG * ) 0xFFFCC264 ) /* (PWMC_CH3) Channel Duty Cycle Register */
+#define AT91C_PWMC_CH3_CCNTR       ( ( AT91_REG * ) 0xFFFCC26C ) /* (PWMC_CH3) Channel Counter Register */
+#define AT91C_PWMC_CH3_CMR         ( ( AT91_REG * ) 0xFFFCC260 ) /* (PWMC_CH3) Channel Mode Register */
+/* ========== Register definition for PWMC_CH2 peripheral ========== */
+#define AT91C_PWMC_CH2_Reserved    ( ( AT91_REG * ) 0xFFFCC254 ) /* (PWMC_CH2) Reserved */
+#define AT91C_PWMC_CH2_CMR         ( ( AT91_REG * ) 0xFFFCC240 ) /* (PWMC_CH2) Channel Mode Register */
+#define AT91C_PWMC_CH2_CCNTR       ( ( AT91_REG * ) 0xFFFCC24C ) /* (PWMC_CH2) Channel Counter Register */
+#define AT91C_PWMC_CH2_CPRDR       ( ( AT91_REG * ) 0xFFFCC248 ) /* (PWMC_CH2) Channel Period Register */
+#define AT91C_PWMC_CH2_CUPDR       ( ( AT91_REG * ) 0xFFFCC250 ) /* (PWMC_CH2) Channel Update Register */
+#define AT91C_PWMC_CH2_CDTYR       ( ( AT91_REG * ) 0xFFFCC244 ) /* (PWMC_CH2) Channel Duty Cycle Register */
+/* ========== Register definition for PWMC_CH1 peripheral ========== */
+#define AT91C_PWMC_CH1_Reserved    ( ( AT91_REG * ) 0xFFFCC234 ) /* (PWMC_CH1) Reserved */
+#define AT91C_PWMC_CH1_CUPDR       ( ( AT91_REG * ) 0xFFFCC230 ) /* (PWMC_CH1) Channel Update Register */
+#define AT91C_PWMC_CH1_CPRDR       ( ( AT91_REG * ) 0xFFFCC228 ) /* (PWMC_CH1) Channel Period Register */
+#define AT91C_PWMC_CH1_CCNTR       ( ( AT91_REG * ) 0xFFFCC22C ) /* (PWMC_CH1) Channel Counter Register */
+#define AT91C_PWMC_CH1_CDTYR       ( ( AT91_REG * ) 0xFFFCC224 ) /* (PWMC_CH1) Channel Duty Cycle Register */
+#define AT91C_PWMC_CH1_CMR         ( ( AT91_REG * ) 0xFFFCC220 ) /* (PWMC_CH1) Channel Mode Register */
+/* ========== Register definition for PWMC_CH0 peripheral ========== */
+#define AT91C_PWMC_CH0_Reserved    ( ( AT91_REG * ) 0xFFFCC214 ) /* (PWMC_CH0) Reserved */
+#define AT91C_PWMC_CH0_CPRDR       ( ( AT91_REG * ) 0xFFFCC208 ) /* (PWMC_CH0) Channel Period Register */
+#define AT91C_PWMC_CH0_CDTYR       ( ( AT91_REG * ) 0xFFFCC204 ) /* (PWMC_CH0) Channel Duty Cycle Register */
+#define AT91C_PWMC_CH0_CMR         ( ( AT91_REG * ) 0xFFFCC200 ) /* (PWMC_CH0) Channel Mode Register */
+#define AT91C_PWMC_CH0_CUPDR       ( ( AT91_REG * ) 0xFFFCC210 ) /* (PWMC_CH0) Channel Update Register */
+#define AT91C_PWMC_CH0_CCNTR       ( ( AT91_REG * ) 0xFFFCC20C ) /* (PWMC_CH0) Channel Counter Register */
+/* ========== Register definition for PWMC peripheral ========== */
+#define AT91C_PWMC_IDR             ( ( AT91_REG * ) 0xFFFCC014 ) /* (PWMC) PWMC Interrupt Disable Register */
+#define AT91C_PWMC_DIS             ( ( AT91_REG * ) 0xFFFCC008 ) /* (PWMC) PWMC Disable Register */
+#define AT91C_PWMC_IER             ( ( AT91_REG * ) 0xFFFCC010 ) /* (PWMC) PWMC Interrupt Enable Register */
+#define AT91C_PWMC_VR              ( ( AT91_REG * ) 0xFFFCC0FC ) /* (PWMC) PWMC Version Register */
+#define AT91C_PWMC_ISR             ( ( AT91_REG * ) 0xFFFCC01C ) /* (PWMC) PWMC Interrupt Status Register */
+#define AT91C_PWMC_SR              ( ( AT91_REG * ) 0xFFFCC00C ) /* (PWMC) PWMC Status Register */
+#define AT91C_PWMC_IMR             ( ( AT91_REG * ) 0xFFFCC018 ) /* (PWMC) PWMC Interrupt Mask Register */
+#define AT91C_PWMC_MR              ( ( AT91_REG * ) 0xFFFCC000 ) /* (PWMC) PWMC Mode Register */
+#define AT91C_PWMC_ENA             ( ( AT91_REG * ) 0xFFFCC004 ) /* (PWMC) PWMC Enable Register */
+/* ========== Register definition for UDP peripheral ========== */
+#define AT91C_UDP_IMR              ( ( AT91_REG * ) 0xFFFB0018 ) /* (UDP) Interrupt Mask Register */
+#define AT91C_UDP_FADDR            ( ( AT91_REG * ) 0xFFFB0008 ) /* (UDP) Function Address Register */
+#define AT91C_UDP_NUM              ( ( AT91_REG * ) 0xFFFB0000 ) /* (UDP) Frame Number Register */
+#define AT91C_UDP_FDR              ( ( AT91_REG * ) 0xFFFB0050 ) /* (UDP) Endpoint FIFO Data Register */
+#define AT91C_UDP_ISR              ( ( AT91_REG * ) 0xFFFB001C ) /* (UDP) Interrupt Status Register */
+#define AT91C_UDP_CSR              ( ( AT91_REG * ) 0xFFFB0030 ) /* (UDP) Endpoint Control and Status Register */
+#define AT91C_UDP_IDR              ( ( AT91_REG * ) 0xFFFB0014 ) /* (UDP) Interrupt Disable Register */
+#define AT91C_UDP_ICR              ( ( AT91_REG * ) 0xFFFB0020 ) /* (UDP) Interrupt Clear Register */
+#define AT91C_UDP_RSTEP            ( ( AT91_REG * ) 0xFFFB0028 ) /* (UDP) Reset Endpoint Register */
+#define AT91C_UDP_TXVC             ( ( AT91_REG * ) 0xFFFB0074 ) /* (UDP) Transceiver Control Register */
+#define AT91C_UDP_GLBSTATE         ( ( AT91_REG * ) 0xFFFB0004 ) /* (UDP) Global State Register */
+#define AT91C_UDP_IER              ( ( AT91_REG * ) 0xFFFB0010 ) /* (UDP) Interrupt Enable Register */
+/* ========== Register definition for TC0 peripheral ========== */
+#define AT91C_TC0_SR               ( ( AT91_REG * ) 0xFFFA0020 ) /* (TC0) Status Register */
+#define AT91C_TC0_RC               ( ( AT91_REG * ) 0xFFFA001C ) /* (TC0) Register C */
+#define AT91C_TC0_RB               ( ( AT91_REG * ) 0xFFFA0018 ) /* (TC0) Register B */
+#define AT91C_TC0_CCR              ( ( AT91_REG * ) 0xFFFA0000 ) /* (TC0) Channel Control Register */
+#define AT91C_TC0_CMR              ( ( AT91_REG * ) 0xFFFA0004 ) /* (TC0) Channel Mode Register (Capture Mode / Waveform Mode) */
+#define AT91C_TC0_IER              ( ( AT91_REG * ) 0xFFFA0024 ) /* (TC0) Interrupt Enable Register */
+#define AT91C_TC0_RA               ( ( AT91_REG * ) 0xFFFA0014 ) /* (TC0) Register A */
+#define AT91C_TC0_IDR              ( ( AT91_REG * ) 0xFFFA0028 ) /* (TC0) Interrupt Disable Register */
+#define AT91C_TC0_CV               ( ( AT91_REG * ) 0xFFFA0010 ) /* (TC0) Counter Value */
+#define AT91C_TC0_IMR              ( ( AT91_REG * ) 0xFFFA002C ) /* (TC0) Interrupt Mask Register */
+/* ========== Register definition for TC1 peripheral ========== */
+#define AT91C_TC1_RB               ( ( AT91_REG * ) 0xFFFA0058 ) /* (TC1) Register B */
+#define AT91C_TC1_CCR              ( ( AT91_REG * ) 0xFFFA0040 ) /* (TC1) Channel Control Register */
+#define AT91C_TC1_IER              ( ( AT91_REG * ) 0xFFFA0064 ) /* (TC1) Interrupt Enable Register */
+#define AT91C_TC1_IDR              ( ( AT91_REG * ) 0xFFFA0068 ) /* (TC1) Interrupt Disable Register */
+#define AT91C_TC1_SR               ( ( AT91_REG * ) 0xFFFA0060 ) /* (TC1) Status Register */
+#define AT91C_TC1_CMR              ( ( AT91_REG * ) 0xFFFA0044 ) /* (TC1) Channel Mode Register (Capture Mode / Waveform Mode) */
+#define AT91C_TC1_RA               ( ( AT91_REG * ) 0xFFFA0054 ) /* (TC1) Register A */
+#define AT91C_TC1_RC               ( ( AT91_REG * ) 0xFFFA005C ) /* (TC1) Register C */
+#define AT91C_TC1_IMR              ( ( AT91_REG * ) 0xFFFA006C ) /* (TC1) Interrupt Mask Register */
+#define AT91C_TC1_CV               ( ( AT91_REG * ) 0xFFFA0050 ) /* (TC1) Counter Value */
+/* ========== Register definition for TC2 peripheral ========== */
+#define AT91C_TC2_CMR              ( ( AT91_REG * ) 0xFFFA0084 ) /* (TC2) Channel Mode Register (Capture Mode / Waveform Mode) */
+#define AT91C_TC2_CCR              ( ( AT91_REG * ) 0xFFFA0080 ) /* (TC2) Channel Control Register */
+#define AT91C_TC2_CV               ( ( AT91_REG * ) 0xFFFA0090 ) /* (TC2) Counter Value */
+#define AT91C_TC2_RA               ( ( AT91_REG * ) 0xFFFA0094 ) /* (TC2) Register A */
+#define AT91C_TC2_RB               ( ( AT91_REG * ) 0xFFFA0098 ) /* (TC2) Register B */
+#define AT91C_TC2_IDR              ( ( AT91_REG * ) 0xFFFA00A8 ) /* (TC2) Interrupt Disable Register */
+#define AT91C_TC2_IMR              ( ( AT91_REG * ) 0xFFFA00AC ) /* (TC2) Interrupt Mask Register */
+#define AT91C_TC2_RC               ( ( AT91_REG * ) 0xFFFA009C ) /* (TC2) Register C */
+#define AT91C_TC2_IER              ( ( AT91_REG * ) 0xFFFA00A4 ) /* (TC2) Interrupt Enable Register */
+#define AT91C_TC2_SR               ( ( AT91_REG * ) 0xFFFA00A0 ) /* (TC2) Status Register */
+/* ========== Register definition for TCB peripheral ========== */
+#define AT91C_TCB_BMR              ( ( AT91_REG * ) 0xFFFA00C4 ) /* (TCB) TC Block Mode Register */
+#define AT91C_TCB_BCR              ( ( AT91_REG * ) 0xFFFA00C0 ) /* (TCB) TC Block Control Register */
+/* ========== Register definition for CAN_MB0 peripheral ========== */
+#define AT91C_CAN_MB0_MDL          ( ( AT91_REG * ) 0xFFFD0214 ) /* (CAN_MB0) MailBox Data Low Register */
+#define AT91C_CAN_MB0_MAM          ( ( AT91_REG * ) 0xFFFD0204 ) /* (CAN_MB0) MailBox Acceptance Mask Register */
+#define AT91C_CAN_MB0_MCR          ( ( AT91_REG * ) 0xFFFD021C ) /* (CAN_MB0) MailBox Control Register */
+#define AT91C_CAN_MB0_MID          ( ( AT91_REG * ) 0xFFFD0208 ) /* (CAN_MB0) MailBox ID Register */
+#define AT91C_CAN_MB0_MSR          ( ( AT91_REG * ) 0xFFFD0210 ) /* (CAN_MB0) MailBox Status Register */
+#define AT91C_CAN_MB0_MFID         ( ( AT91_REG * ) 0xFFFD020C ) /* (CAN_MB0) MailBox Family ID Register */
+#define AT91C_CAN_MB0_MDH          ( ( AT91_REG * ) 0xFFFD0218 ) /* (CAN_MB0) MailBox Data High Register */
+#define AT91C_CAN_MB0_MMR          ( ( AT91_REG * ) 0xFFFD0200 ) /* (CAN_MB0) MailBox Mode Register */
+/* ========== Register definition for CAN_MB1 peripheral ========== */
+#define AT91C_CAN_MB1_MDL          ( ( AT91_REG * ) 0xFFFD0234 ) /* (CAN_MB1) MailBox Data Low Register */
+#define AT91C_CAN_MB1_MID          ( ( AT91_REG * ) 0xFFFD0228 ) /* (CAN_MB1) MailBox ID Register */
+#define AT91C_CAN_MB1_MMR          ( ( AT91_REG * ) 0xFFFD0220 ) /* (CAN_MB1) MailBox Mode Register */
+#define AT91C_CAN_MB1_MSR          ( ( AT91_REG * ) 0xFFFD0230 ) /* (CAN_MB1) MailBox Status Register */
+#define AT91C_CAN_MB1_MAM          ( ( AT91_REG * ) 0xFFFD0224 ) /* (CAN_MB1) MailBox Acceptance Mask Register */
+#define AT91C_CAN_MB1_MDH          ( ( AT91_REG * ) 0xFFFD0238 ) /* (CAN_MB1) MailBox Data High Register */
+#define AT91C_CAN_MB1_MCR          ( ( AT91_REG * ) 0xFFFD023C ) /* (CAN_MB1) MailBox Control Register */
+#define AT91C_CAN_MB1_MFID         ( ( AT91_REG * ) 0xFFFD022C ) /* (CAN_MB1) MailBox Family ID Register */
+/* ========== Register definition for CAN_MB2 peripheral ========== */
+#define AT91C_CAN_MB2_MCR          ( ( AT91_REG * ) 0xFFFD025C ) /* (CAN_MB2) MailBox Control Register */
+#define AT91C_CAN_MB2_MDH          ( ( AT91_REG * ) 0xFFFD0258 ) /* (CAN_MB2) MailBox Data High Register */
+#define AT91C_CAN_MB2_MID          ( ( AT91_REG * ) 0xFFFD0248 ) /* (CAN_MB2) MailBox ID Register */
+#define AT91C_CAN_MB2_MDL          ( ( AT91_REG * ) 0xFFFD0254 ) /* (CAN_MB2) MailBox Data Low Register */
+#define AT91C_CAN_MB2_MMR          ( ( AT91_REG * ) 0xFFFD0240 ) /* (CAN_MB2) MailBox Mode Register */
+#define AT91C_CAN_MB2_MAM          ( ( AT91_REG * ) 0xFFFD0244 ) /* (CAN_MB2) MailBox Acceptance Mask Register */
+#define AT91C_CAN_MB2_MFID         ( ( AT91_REG * ) 0xFFFD024C ) /* (CAN_MB2) MailBox Family ID Register */
+#define AT91C_CAN_MB2_MSR          ( ( AT91_REG * ) 0xFFFD0250 ) /* (CAN_MB2) MailBox Status Register */
+/* ========== Register definition for CAN_MB3 peripheral ========== */
+#define AT91C_CAN_MB3_MFID         ( ( AT91_REG * ) 0xFFFD026C ) /* (CAN_MB3) MailBox Family ID Register */
+#define AT91C_CAN_MB3_MAM          ( ( AT91_REG * ) 0xFFFD0264 ) /* (CAN_MB3) MailBox Acceptance Mask Register */
+#define AT91C_CAN_MB3_MID          ( ( AT91_REG * ) 0xFFFD0268 ) /* (CAN_MB3) MailBox ID Register */
+#define AT91C_CAN_MB3_MCR          ( ( AT91_REG * ) 0xFFFD027C ) /* (CAN_MB3) MailBox Control Register */
+#define AT91C_CAN_MB3_MMR          ( ( AT91_REG * ) 0xFFFD0260 ) /* (CAN_MB3) MailBox Mode Register */
+#define AT91C_CAN_MB3_MSR          ( ( AT91_REG * ) 0xFFFD0270 ) /* (CAN_MB3) MailBox Status Register */
+#define AT91C_CAN_MB3_MDL          ( ( AT91_REG * ) 0xFFFD0274 ) /* (CAN_MB3) MailBox Data Low Register */
+#define AT91C_CAN_MB3_MDH          ( ( AT91_REG * ) 0xFFFD0278 ) /* (CAN_MB3) MailBox Data High Register */
+/* ========== Register definition for CAN_MB4 peripheral ========== */
+#define AT91C_CAN_MB4_MID          ( ( AT91_REG * ) 0xFFFD0288 ) /* (CAN_MB4) MailBox ID Register */
+#define AT91C_CAN_MB4_MMR          ( ( AT91_REG * ) 0xFFFD0280 ) /* (CAN_MB4) MailBox Mode Register */
+#define AT91C_CAN_MB4_MDH          ( ( AT91_REG * ) 0xFFFD0298 ) /* (CAN_MB4) MailBox Data High Register */
+#define AT91C_CAN_MB4_MFID         ( ( AT91_REG * ) 0xFFFD028C ) /* (CAN_MB4) MailBox Family ID Register */
+#define AT91C_CAN_MB4_MSR          ( ( AT91_REG * ) 0xFFFD0290 ) /* (CAN_MB4) MailBox Status Register */
+#define AT91C_CAN_MB4_MCR          ( ( AT91_REG * ) 0xFFFD029C ) /* (CAN_MB4) MailBox Control Register */
+#define AT91C_CAN_MB4_MDL          ( ( AT91_REG * ) 0xFFFD0294 ) /* (CAN_MB4) MailBox Data Low Register */
+#define AT91C_CAN_MB4_MAM          ( ( AT91_REG * ) 0xFFFD0284 ) /* (CAN_MB4) MailBox Acceptance Mask Register */
+/* ========== Register definition for CAN_MB5 peripheral ========== */
+#define AT91C_CAN_MB5_MSR          ( ( AT91_REG * ) 0xFFFD02B0 ) /* (CAN_MB5) MailBox Status Register */
+#define AT91C_CAN_MB5_MCR          ( ( AT91_REG * ) 0xFFFD02BC ) /* (CAN_MB5) MailBox Control Register */
+#define AT91C_CAN_MB5_MFID         ( ( AT91_REG * ) 0xFFFD02AC ) /* (CAN_MB5) MailBox Family ID Register */
+#define AT91C_CAN_MB5_MDH          ( ( AT91_REG * ) 0xFFFD02B8 ) /* (CAN_MB5) MailBox Data High Register */
+#define AT91C_CAN_MB5_MID          ( ( AT91_REG * ) 0xFFFD02A8 ) /* (CAN_MB5) MailBox ID Register */
+#define AT91C_CAN_MB5_MMR          ( ( AT91_REG * ) 0xFFFD02A0 ) /* (CAN_MB5) MailBox Mode Register */
+#define AT91C_CAN_MB5_MDL          ( ( AT91_REG * ) 0xFFFD02B4 ) /* (CAN_MB5) MailBox Data Low Register */
+#define AT91C_CAN_MB5_MAM          ( ( AT91_REG * ) 0xFFFD02A4 ) /* (CAN_MB5) MailBox Acceptance Mask Register */
+/* ========== Register definition for CAN_MB6 peripheral ========== */
+#define AT91C_CAN_MB6_MFID         ( ( AT91_REG * ) 0xFFFD02CC ) /* (CAN_MB6) MailBox Family ID Register */
+#define AT91C_CAN_MB6_MID          ( ( AT91_REG * ) 0xFFFD02C8 ) /* (CAN_MB6) MailBox ID Register */
+#define AT91C_CAN_MB6_MAM          ( ( AT91_REG * ) 0xFFFD02C4 ) /* (CAN_MB6) MailBox Acceptance Mask Register */
+#define AT91C_CAN_MB6_MSR          ( ( AT91_REG * ) 0xFFFD02D0 ) /* (CAN_MB6) MailBox Status Register */
+#define AT91C_CAN_MB6_MDL          ( ( AT91_REG * ) 0xFFFD02D4 ) /* (CAN_MB6) MailBox Data Low Register */
+#define AT91C_CAN_MB6_MCR          ( ( AT91_REG * ) 0xFFFD02DC ) /* (CAN_MB6) MailBox Control Register */
+#define AT91C_CAN_MB6_MDH          ( ( AT91_REG * ) 0xFFFD02D8 ) /* (CAN_MB6) MailBox Data High Register */
+#define AT91C_CAN_MB6_MMR          ( ( AT91_REG * ) 0xFFFD02C0 ) /* (CAN_MB6) MailBox Mode Register */
+/* ========== Register definition for CAN_MB7 peripheral ========== */
+#define AT91C_CAN_MB7_MCR          ( ( AT91_REG * ) 0xFFFD02FC ) /* (CAN_MB7) MailBox Control Register */
+#define AT91C_CAN_MB7_MDH          ( ( AT91_REG * ) 0xFFFD02F8 ) /* (CAN_MB7) MailBox Data High Register */
+#define AT91C_CAN_MB7_MFID         ( ( AT91_REG * ) 0xFFFD02EC ) /* (CAN_MB7) MailBox Family ID Register */
+#define AT91C_CAN_MB7_MDL          ( ( AT91_REG * ) 0xFFFD02F4 ) /* (CAN_MB7) MailBox Data Low Register */
+#define AT91C_CAN_MB7_MID          ( ( AT91_REG * ) 0xFFFD02E8 ) /* (CAN_MB7) MailBox ID Register */
+#define AT91C_CAN_MB7_MMR          ( ( AT91_REG * ) 0xFFFD02E0 ) /* (CAN_MB7) MailBox Mode Register */
+#define AT91C_CAN_MB7_MAM          ( ( AT91_REG * ) 0xFFFD02E4 ) /* (CAN_MB7) MailBox Acceptance Mask Register */
+#define AT91C_CAN_MB7_MSR          ( ( AT91_REG * ) 0xFFFD02F0 ) /* (CAN_MB7) MailBox Status Register */
+/* ========== Register definition for CAN peripheral ========== */
+#define AT91C_CAN_TCR              ( ( AT91_REG * ) 0xFFFD0024 ) /* (CAN) Transfer Command Register */
+#define AT91C_CAN_IMR              ( ( AT91_REG * ) 0xFFFD000C ) /* (CAN) Interrupt Mask Register */
+#define AT91C_CAN_IER              ( ( AT91_REG * ) 0xFFFD0004 ) /* (CAN) Interrupt Enable Register */
+#define AT91C_CAN_ECR              ( ( AT91_REG * ) 0xFFFD0020 ) /* (CAN) Error Counter Register */
+#define AT91C_CAN_TIMESTP          ( ( AT91_REG * ) 0xFFFD001C ) /* (CAN) Time Stamp Register */
+#define AT91C_CAN_MR               ( ( AT91_REG * ) 0xFFFD0000 ) /* (CAN) Mode Register */
+#define AT91C_CAN_IDR              ( ( AT91_REG * ) 0xFFFD0008 ) /* (CAN) Interrupt Disable Register */
+#define AT91C_CAN_ACR              ( ( AT91_REG * ) 0xFFFD0028 ) /* (CAN) Abort Command Register */
+#define AT91C_CAN_TIM              ( ( AT91_REG * ) 0xFFFD0018 ) /* (CAN) Timer Register */
+#define AT91C_CAN_SR               ( ( AT91_REG * ) 0xFFFD0010 ) /* (CAN) Status Register */
+#define AT91C_CAN_BR               ( ( AT91_REG * ) 0xFFFD0014 ) /* (CAN) Baudrate Register */
+#define AT91C_CAN_VR               ( ( AT91_REG * ) 0xFFFD00FC ) /* (CAN) Version Register */
+/* ========== Register definition for EMAC peripheral ========== */
+#define AT91C_EMAC_ISR             ( ( AT91_REG * ) 0xFFFDC024 ) /* (EMAC) Interrupt Status Register */
+#define AT91C_EMAC_SA4H            ( ( AT91_REG * ) 0xFFFDC0B4 ) /* (EMAC) Specific Address 4 Top, Last 2 bytes */
+#define AT91C_EMAC_SA1L            ( ( AT91_REG * ) 0xFFFDC098 ) /* (EMAC) Specific Address 1 Bottom, First 4 bytes */
+#define AT91C_EMAC_ELE             ( ( AT91_REG * ) 0xFFFDC078 ) /* (EMAC) Excessive Length Errors Register */
+#define AT91C_EMAC_LCOL            ( ( AT91_REG * ) 0xFFFDC05C ) /* (EMAC) Late Collision Register */
+#define AT91C_EMAC_RLE             ( ( AT91_REG * ) 0xFFFDC088 ) /* (EMAC) Receive Length Field Mismatch Register */
+#define AT91C_EMAC_WOL             ( ( AT91_REG * ) 0xFFFDC0C4 ) /* (EMAC) Wake On LAN Register */
+#define AT91C_EMAC_DTF             ( ( AT91_REG * ) 0xFFFDC058 ) /* (EMAC) Deferred Transmission Frame Register */
+#define AT91C_EMAC_TUND            ( ( AT91_REG * ) 0xFFFDC064 ) /* (EMAC) Transmit Underrun Error Register */
+#define AT91C_EMAC_NCR             ( ( AT91_REG * ) 0xFFFDC000 ) /* (EMAC) Network Control Register */
+#define AT91C_EMAC_SA4L            ( ( AT91_REG * ) 0xFFFDC0B0 ) /* (EMAC) Specific Address 4 Bottom, First 4 bytes */
+#define AT91C_EMAC_RSR             ( ( AT91_REG * ) 0xFFFDC020 ) /* (EMAC) Receive Status Register */
+#define AT91C_EMAC_SA3L            ( ( AT91_REG * ) 0xFFFDC0A8 ) /* (EMAC) Specific Address 3 Bottom, First 4 bytes */
+#define AT91C_EMAC_TSR             ( ( AT91_REG * ) 0xFFFDC014 ) /* (EMAC) Transmit Status Register */
+#define AT91C_EMAC_IDR             ( ( AT91_REG * ) 0xFFFDC02C ) /* (EMAC) Interrupt Disable Register */
+#define AT91C_EMAC_RSE             ( ( AT91_REG * ) 0xFFFDC074 ) /* (EMAC) Receive Symbol Errors Register */
+#define AT91C_EMAC_ECOL            ( ( AT91_REG * ) 0xFFFDC060 ) /* (EMAC) Excessive Collision Register */
+#define AT91C_EMAC_TID             ( ( AT91_REG * ) 0xFFFDC0B8 ) /* (EMAC) Type ID Checking Register */
+#define AT91C_EMAC_HRB             ( ( AT91_REG * ) 0xFFFDC090 ) /* (EMAC) Hash Address Bottom[31:0] */
+#define AT91C_EMAC_TBQP            ( ( AT91_REG * ) 0xFFFDC01C ) /* (EMAC) Transmit Buffer Queue Pointer */
+#define AT91C_EMAC_USRIO           ( ( AT91_REG * ) 0xFFFDC0C0 ) /* (EMAC) USER Input/Output Register */
+#define AT91C_EMAC_PTR             ( ( AT91_REG * ) 0xFFFDC038 ) /* (EMAC) Pause Time Register */
+#define AT91C_EMAC_SA2H            ( ( AT91_REG * ) 0xFFFDC0A4 ) /* (EMAC) Specific Address 2 Top, Last 2 bytes */
+#define AT91C_EMAC_ROV             ( ( AT91_REG * ) 0xFFFDC070 ) /* (EMAC) Receive Overrun Errors Register */
+#define AT91C_EMAC_ALE             ( ( AT91_REG * ) 0xFFFDC054 ) /* (EMAC) Alignment Error Register */
+#define AT91C_EMAC_RJA             ( ( AT91_REG * ) 0xFFFDC07C ) /* (EMAC) Receive Jabbers Register */
+#define AT91C_EMAC_RBQP            ( ( AT91_REG * ) 0xFFFDC018 ) /* (EMAC) Receive Buffer Queue Pointer */
+#define AT91C_EMAC_TPF             ( ( AT91_REG * ) 0xFFFDC08C ) /* (EMAC) Transmitted Pause Frames Register */
+#define AT91C_EMAC_NCFGR           ( ( AT91_REG * ) 0xFFFDC004 ) /* (EMAC) Network Configuration Register */
+#define AT91C_EMAC_HRT             ( ( AT91_REG * ) 0xFFFDC094 ) /* (EMAC) Hash Address Top[63:32] */
+#define AT91C_EMAC_USF             ( ( AT91_REG * ) 0xFFFDC080 ) /* (EMAC) Undersize Frames Register */
+#define AT91C_EMAC_FCSE            ( ( AT91_REG * ) 0xFFFDC050 ) /* (EMAC) Frame Check Sequence Error Register */
+#define AT91C_EMAC_TPQ             ( ( AT91_REG * ) 0xFFFDC0BC ) /* (EMAC) Transmit Pause Quantum Register */
+#define AT91C_EMAC_MAN             ( ( AT91_REG * ) 0xFFFDC034 ) /* (EMAC) PHY Maintenance Register */
+#define AT91C_EMAC_FTO             ( ( AT91_REG * ) 0xFFFDC040 ) /* (EMAC) Frames Transmitted OK Register */
+#define AT91C_EMAC_REV             ( ( AT91_REG * ) 0xFFFDC0FC ) /* (EMAC) Revision Register */
+#define AT91C_EMAC_IMR             ( ( AT91_REG * ) 0xFFFDC030 ) /* (EMAC) Interrupt Mask Register */
+#define AT91C_EMAC_SCF             ( ( AT91_REG * ) 0xFFFDC044 ) /* (EMAC) Single Collision Frame Register */
+#define AT91C_EMAC_PFR             ( ( AT91_REG * ) 0xFFFDC03C ) /* (EMAC) Pause Frames received Register */
+#define AT91C_EMAC_MCF             ( ( AT91_REG * ) 0xFFFDC048 ) /* (EMAC) Multiple Collision Frame Register */
+#define AT91C_EMAC_NSR             ( ( AT91_REG * ) 0xFFFDC008 ) /* (EMAC) Network Status Register */
+#define AT91C_EMAC_SA2L            ( ( AT91_REG * ) 0xFFFDC0A0 ) /* (EMAC) Specific Address 2 Bottom, First 4 bytes */
+#define AT91C_EMAC_FRO             ( ( AT91_REG * ) 0xFFFDC04C ) /* (EMAC) Frames Received OK Register */
+#define AT91C_EMAC_IER             ( ( AT91_REG * ) 0xFFFDC028 ) /* (EMAC) Interrupt Enable Register */
+#define AT91C_EMAC_SA1H            ( ( AT91_REG * ) 0xFFFDC09C ) /* (EMAC) Specific Address 1 Top, Last 2 bytes */
+#define AT91C_EMAC_CSE             ( ( AT91_REG * ) 0xFFFDC068 ) /* (EMAC) Carrier Sense Error Register */
+#define AT91C_EMAC_SA3H            ( ( AT91_REG * ) 0xFFFDC0AC ) /* (EMAC) Specific Address 3 Top, Last 2 bytes */
+#define AT91C_EMAC_RRE             ( ( AT91_REG * ) 0xFFFDC06C ) /* (EMAC) Receive Ressource Error Register */
+#define AT91C_EMAC_STE             ( ( AT91_REG * ) 0xFFFDC084 ) /* (EMAC) SQE Test Error Register */
+/* ========== Register definition for PDC_ADC peripheral ========== */
+#define AT91C_ADC_PTSR             ( ( AT91_REG * ) 0xFFFD8124 ) /* (PDC_ADC) PDC Transfer Status Register */
+#define AT91C_ADC_PTCR             ( ( AT91_REG * ) 0xFFFD8120 ) /* (PDC_ADC) PDC Transfer Control Register */
+#define AT91C_ADC_TNPR             ( ( AT91_REG * ) 0xFFFD8118 ) /* (PDC_ADC) Transmit Next Pointer Register */
+#define AT91C_ADC_TNCR             ( ( AT91_REG * ) 0xFFFD811C ) /* (PDC_ADC) Transmit Next Counter Register */
+#define AT91C_ADC_RNPR             ( ( AT91_REG * ) 0xFFFD8110 ) /* (PDC_ADC) Receive Next Pointer Register */
+#define AT91C_ADC_RNCR             ( ( AT91_REG * ) 0xFFFD8114 ) /* (PDC_ADC) Receive Next Counter Register */
+#define AT91C_ADC_RPR              ( ( AT91_REG * ) 0xFFFD8100 ) /* (PDC_ADC) Receive Pointer Register */
+#define AT91C_ADC_TCR              ( ( AT91_REG * ) 0xFFFD810C ) /* (PDC_ADC) Transmit Counter Register */
+#define AT91C_ADC_TPR              ( ( AT91_REG * ) 0xFFFD8108 ) /* (PDC_ADC) Transmit Pointer Register */
+#define AT91C_ADC_RCR              ( ( AT91_REG * ) 0xFFFD8104 ) /* (PDC_ADC) Receive Counter Register */
+/* ========== Register definition for ADC peripheral ========== */
+#define AT91C_ADC_CDR2             ( ( AT91_REG * ) 0xFFFD8038 ) /* (ADC) ADC Channel Data Register 2 */
+#define AT91C_ADC_CDR3             ( ( AT91_REG * ) 0xFFFD803C ) /* (ADC) ADC Channel Data Register 3 */
+#define AT91C_ADC_CDR0             ( ( AT91_REG * ) 0xFFFD8030 ) /* (ADC) ADC Channel Data Register 0 */
+#define AT91C_ADC_CDR5             ( ( AT91_REG * ) 0xFFFD8044 ) /* (ADC) ADC Channel Data Register 5 */
+#define AT91C_ADC_CHDR             ( ( AT91_REG * ) 0xFFFD8014 ) /* (ADC) ADC Channel Disable Register */
+#define AT91C_ADC_SR               ( ( AT91_REG * ) 0xFFFD801C ) /* (ADC) ADC Status Register */
+#define AT91C_ADC_CDR4             ( ( AT91_REG * ) 0xFFFD8040 ) /* (ADC) ADC Channel Data Register 4 */
+#define AT91C_ADC_CDR1             ( ( AT91_REG * ) 0xFFFD8034 ) /* (ADC) ADC Channel Data Register 1 */
+#define AT91C_ADC_LCDR             ( ( AT91_REG * ) 0xFFFD8020 ) /* (ADC) ADC Last Converted Data Register */
+#define AT91C_ADC_IDR              ( ( AT91_REG * ) 0xFFFD8028 ) /* (ADC) ADC Interrupt Disable Register */
+#define AT91C_ADC_CR               ( ( AT91_REG * ) 0xFFFD8000 ) /* (ADC) ADC Control Register */
+#define AT91C_ADC_CDR7             ( ( AT91_REG * ) 0xFFFD804C ) /* (ADC) ADC Channel Data Register 7 */
+#define AT91C_ADC_CDR6             ( ( AT91_REG * ) 0xFFFD8048 ) /* (ADC) ADC Channel Data Register 6 */
+#define AT91C_ADC_IER              ( ( AT91_REG * ) 0xFFFD8024 ) /* (ADC) ADC Interrupt Enable Register */
+#define AT91C_ADC_CHER             ( ( AT91_REG * ) 0xFFFD8010 ) /* (ADC) ADC Channel Enable Register */
+#define AT91C_ADC_CHSR             ( ( AT91_REG * ) 0xFFFD8018 ) /* (ADC) ADC Channel Status Register */
+#define AT91C_ADC_MR               ( ( AT91_REG * ) 0xFFFD8004 ) /* (ADC) ADC Mode Register */
+#define AT91C_ADC_IMR              ( ( AT91_REG * ) 0xFFFD802C ) /* (ADC) ADC Interrupt Mask Register */
+/* ========== Register definition for PDC_AES peripheral ========== */
+#define AT91C_AES_TPR              ( ( AT91_REG * ) 0xFFFA4108 ) /* (PDC_AES) Transmit Pointer Register */
+#define AT91C_AES_PTCR             ( ( AT91_REG * ) 0xFFFA4120 ) /* (PDC_AES) PDC Transfer Control Register */
+#define AT91C_AES_RNPR             ( ( AT91_REG * ) 0xFFFA4110 ) /* (PDC_AES) Receive Next Pointer Register */
+#define AT91C_AES_TNCR             ( ( AT91_REG * ) 0xFFFA411C ) /* (PDC_AES) Transmit Next Counter Register */
+#define AT91C_AES_TCR              ( ( AT91_REG * ) 0xFFFA410C ) /* (PDC_AES) Transmit Counter Register */
+#define AT91C_AES_RCR              ( ( AT91_REG * ) 0xFFFA4104 ) /* (PDC_AES) Receive Counter Register */
+#define AT91C_AES_RNCR             ( ( AT91_REG * ) 0xFFFA4114 ) /* (PDC_AES) Receive Next Counter Register */
+#define AT91C_AES_TNPR             ( ( AT91_REG * ) 0xFFFA4118 ) /* (PDC_AES) Transmit Next Pointer Register */
+#define AT91C_AES_RPR              ( ( AT91_REG * ) 0xFFFA4100 ) /* (PDC_AES) Receive Pointer Register */
+#define AT91C_AES_PTSR             ( ( AT91_REG * ) 0xFFFA4124 ) /* (PDC_AES) PDC Transfer Status Register */
+/* ========== Register definition for AES peripheral ========== */
+#define AT91C_AES_IVxR             ( ( AT91_REG * ) 0xFFFA4060 ) /* (AES) Initialization Vector x Register */
+#define AT91C_AES_MR               ( ( AT91_REG * ) 0xFFFA4004 ) /* (AES) Mode Register */
+#define AT91C_AES_VR               ( ( AT91_REG * ) 0xFFFA40FC ) /* (AES) AES Version Register */
+#define AT91C_AES_ODATAxR          ( ( AT91_REG * ) 0xFFFA4050 ) /* (AES) Output Data x Register */
+#define AT91C_AES_IDATAxR          ( ( AT91_REG * ) 0xFFFA4040 ) /* (AES) Input Data x Register */
+#define AT91C_AES_CR               ( ( AT91_REG * ) 0xFFFA4000 ) /* (AES) Control Register */
+#define AT91C_AES_IDR              ( ( AT91_REG * ) 0xFFFA4014 ) /* (AES) Interrupt Disable Register */
+#define AT91C_AES_IMR              ( ( AT91_REG * ) 0xFFFA4018 ) /* (AES) Interrupt Mask Register */
+#define AT91C_AES_IER              ( ( AT91_REG * ) 0xFFFA4010 ) /* (AES) Interrupt Enable Register */
+#define AT91C_AES_KEYWxR           ( ( AT91_REG * ) 0xFFFA4020 ) /* (AES) Key Word x Register */
+#define AT91C_AES_ISR              ( ( AT91_REG * ) 0xFFFA401C ) /* (AES) Interrupt Status Register */
+/* ========== Register definition for PDC_TDES peripheral ========== */
+#define AT91C_TDES_RNCR            ( ( AT91_REG * ) 0xFFFA8114 ) /* (PDC_TDES) Receive Next Counter Register */
+#define AT91C_TDES_TCR             ( ( AT91_REG * ) 0xFFFA810C ) /* (PDC_TDES) Transmit Counter Register */
+#define AT91C_TDES_RCR             ( ( AT91_REG * ) 0xFFFA8104 ) /* (PDC_TDES) Receive Counter Register */
+#define AT91C_TDES_TNPR            ( ( AT91_REG * ) 0xFFFA8118 ) /* (PDC_TDES) Transmit Next Pointer Register */
+#define AT91C_TDES_RNPR            ( ( AT91_REG * ) 0xFFFA8110 ) /* (PDC_TDES) Receive Next Pointer Register */
+#define AT91C_TDES_RPR             ( ( AT91_REG * ) 0xFFFA8100 ) /* (PDC_TDES) Receive Pointer Register */
+#define AT91C_TDES_TNCR            ( ( AT91_REG * ) 0xFFFA811C ) /* (PDC_TDES) Transmit Next Counter Register */
+#define AT91C_TDES_TPR             ( ( AT91_REG * ) 0xFFFA8108 ) /* (PDC_TDES) Transmit Pointer Register */
+#define AT91C_TDES_PTSR            ( ( AT91_REG * ) 0xFFFA8124 ) /* (PDC_TDES) PDC Transfer Status Register */
+#define AT91C_TDES_PTCR            ( ( AT91_REG * ) 0xFFFA8120 ) /* (PDC_TDES) PDC Transfer Control Register */
+/* ========== Register definition for TDES peripheral ========== */
+#define AT91C_TDES_KEY2WxR         ( ( AT91_REG * ) 0xFFFA8028 ) /* (TDES) Key 2 Word x Register */
+#define AT91C_TDES_KEY3WxR         ( ( AT91_REG * ) 0xFFFA8030 ) /* (TDES) Key 3 Word x Register */
+#define AT91C_TDES_IDR             ( ( AT91_REG * ) 0xFFFA8014 ) /* (TDES) Interrupt Disable Register */
+#define AT91C_TDES_VR              ( ( AT91_REG * ) 0xFFFA80FC ) /* (TDES) TDES Version Register */
+#define AT91C_TDES_IVxR            ( ( AT91_REG * ) 0xFFFA8060 ) /* (TDES) Initialization Vector x Register */
+#define AT91C_TDES_ODATAxR         ( ( AT91_REG * ) 0xFFFA8050 ) /* (TDES) Output Data x Register */
+#define AT91C_TDES_IMR             ( ( AT91_REG * ) 0xFFFA8018 ) /* (TDES) Interrupt Mask Register */
+#define AT91C_TDES_MR              ( ( AT91_REG * ) 0xFFFA8004 ) /* (TDES) Mode Register */
+#define AT91C_TDES_CR              ( ( AT91_REG * ) 0xFFFA8000 ) /* (TDES) Control Register */
+#define AT91C_TDES_IER             ( ( AT91_REG * ) 0xFFFA8010 ) /* (TDES) Interrupt Enable Register */
+#define AT91C_TDES_ISR             ( ( AT91_REG * ) 0xFFFA801C ) /* (TDES) Interrupt Status Register */
+#define AT91C_TDES_IDATAxR         ( ( AT91_REG * ) 0xFFFA8040 ) /* (TDES) Input Data x Register */
+#define AT91C_TDES_KEY1WxR         ( ( AT91_REG * ) 0xFFFA8020 ) /* (TDES) Key 1 Word x Register */
+
+/* ***************************************************************************** */
+/*               PIO DEFINITIONS FOR AT91SAM7X256 */
+/* ***************************************************************************** */
+#define AT91C_PIO_PA0             ( ( unsigned int ) 1 << 0 )         /* Pin Controlled by PA0 */
+#define AT91C_PA0_RXD0            ( ( unsigned int ) AT91C_PIO_PA0 )  /*  USART 0 Receive Data */
+#define AT91C_PIO_PA1             ( ( unsigned int ) 1 << 1 )         /* Pin Controlled by PA1 */
+#define AT91C_PA1_TXD0            ( ( unsigned int ) AT91C_PIO_PA1 )  /*  USART 0 Transmit Data */
+#define AT91C_PIO_PA10            ( ( unsigned int ) 1 << 10 )        /* Pin Controlled by PA10 */
+#define AT91C_PA10_TWD            ( ( unsigned int ) AT91C_PIO_PA10 ) /*  TWI Two-wire Serial Data */
+#define AT91C_PIO_PA11            ( ( unsigned int ) 1 << 11 )        /* Pin Controlled by PA11 */
+#define AT91C_PA11_TWCK           ( ( unsigned int ) AT91C_PIO_PA11 ) /*  TWI Two-wire Serial Clock */
+#define AT91C_PIO_PA12            ( ( unsigned int ) 1 << 12 )        /* Pin Controlled by PA12 */
+#define AT91C_PA12_NPCS00         ( ( unsigned int ) AT91C_PIO_PA12 ) /*  SPI 0 Peripheral Chip Select 0 */
+#define AT91C_PIO_PA13            ( ( unsigned int ) 1 << 13 )        /* Pin Controlled by PA13 */
+#define AT91C_PA13_NPCS01         ( ( unsigned int ) AT91C_PIO_PA13 ) /*  SPI 0 Peripheral Chip Select 1 */
+#define AT91C_PA13_PCK1           ( ( unsigned int ) AT91C_PIO_PA13 ) /*  PMC Programmable Clock Output 1 */
+#define AT91C_PIO_PA14            ( ( unsigned int ) 1 << 14 )        /* Pin Controlled by PA14 */
+#define AT91C_PA14_NPCS02         ( ( unsigned int ) AT91C_PIO_PA14 ) /*  SPI 0 Peripheral Chip Select 2 */
+#define AT91C_PA14_IRQ1           ( ( unsigned int ) AT91C_PIO_PA14 ) /*  External Interrupt 1 */
+#define AT91C_PIO_PA15            ( ( unsigned int ) 1 << 15 )        /* Pin Controlled by PA15 */
+#define AT91C_PA15_NPCS03         ( ( unsigned int ) AT91C_PIO_PA15 ) /*  SPI 0 Peripheral Chip Select 3 */
+#define AT91C_PA15_TCLK2          ( ( unsigned int ) AT91C_PIO_PA15 ) /*  Timer Counter 2 external clock input */
+#define AT91C_PIO_PA16            ( ( unsigned int ) 1 << 16 )        /* Pin Controlled by PA16 */
+#define AT91C_PA16_MISO0          ( ( unsigned int ) AT91C_PIO_PA16 ) /*  SPI 0 Master In Slave */
+#define AT91C_PIO_PA17            ( ( unsigned int ) 1 << 17 )        /* Pin Controlled by PA17 */
+#define AT91C_PA17_MOSI0          ( ( unsigned int ) AT91C_PIO_PA17 ) /*  SPI 0 Master Out Slave */
+#define AT91C_PIO_PA18            ( ( unsigned int ) 1 << 18 )        /* Pin Controlled by PA18 */
+#define AT91C_PA18_SPCK0          ( ( unsigned int ) AT91C_PIO_PA18 ) /*  SPI 0 Serial Clock */
+#define AT91C_PIO_PA19            ( ( unsigned int ) 1 << 19 )        /* Pin Controlled by PA19 */
+#define AT91C_PA19_CANRX          ( ( unsigned int ) AT91C_PIO_PA19 ) /*  CAN Receive */
+#define AT91C_PIO_PA2             ( ( unsigned int ) 1 << 2 )         /* Pin Controlled by PA2 */
+#define AT91C_PA2_SCK0            ( ( unsigned int ) AT91C_PIO_PA2 )  /*  USART 0 Serial Clock */
+#define AT91C_PA2_NPCS11          ( ( unsigned int ) AT91C_PIO_PA2 )  /*  SPI 1 Peripheral Chip Select 1 */
+#define AT91C_PIO_PA20            ( ( unsigned int ) 1 << 20 )        /* Pin Controlled by PA20 */
+#define AT91C_PA20_CANTX          ( ( unsigned int ) AT91C_PIO_PA20 ) /*  CAN Transmit */
+#define AT91C_PIO_PA21            ( ( unsigned int ) 1 << 21 )        /* Pin Controlled by PA21 */
+#define AT91C_PA21_TF             ( ( unsigned int ) AT91C_PIO_PA21 ) /*  SSC Transmit Frame Sync */
+#define AT91C_PA21_NPCS10         ( ( unsigned int ) AT91C_PIO_PA21 ) /*  SPI 1 Peripheral Chip Select 0 */
+#define AT91C_PIO_PA22            ( ( unsigned int ) 1 << 22 )        /* Pin Controlled by PA22 */
+#define AT91C_PA22_TK             ( ( unsigned int ) AT91C_PIO_PA22 ) /*  SSC Transmit Clock */
+#define AT91C_PA22_SPCK1          ( ( unsigned int ) AT91C_PIO_PA22 ) /*  SPI 1 Serial Clock */
+#define AT91C_PIO_PA23            ( ( unsigned int ) 1 << 23 )        /* Pin Controlled by PA23 */
+#define AT91C_PA23_TD             ( ( unsigned int ) AT91C_PIO_PA23 ) /*  SSC Transmit data */
+#define AT91C_PA23_MOSI1          ( ( unsigned int ) AT91C_PIO_PA23 ) /*  SPI 1 Master Out Slave */
+#define AT91C_PIO_PA24            ( ( unsigned int ) 1 << 24 )        /* Pin Controlled by PA24 */
+#define AT91C_PA24_RD             ( ( unsigned int ) AT91C_PIO_PA24 ) /*  SSC Receive Data */
+#define AT91C_PA24_MISO1          ( ( unsigned int ) AT91C_PIO_PA24 ) /*  SPI 1 Master In Slave */
+#define AT91C_PIO_PA25            ( ( unsigned int ) 1 << 25 )        /* Pin Controlled by PA25 */
+#define AT91C_PA25_RK             ( ( unsigned int ) AT91C_PIO_PA25 ) /*  SSC Receive Clock */
+#define AT91C_PA25_NPCS11         ( ( unsigned int ) AT91C_PIO_PA25 ) /*  SPI 1 Peripheral Chip Select 1 */
+#define AT91C_PIO_PA26            ( ( unsigned int ) 1 << 26 )        /* Pin Controlled by PA26 */
+#define AT91C_PA26_RF             ( ( unsigned int ) AT91C_PIO_PA26 ) /*  SSC Receive Frame Sync */
+#define AT91C_PA26_NPCS12         ( ( unsigned int ) AT91C_PIO_PA26 ) /*  SPI 1 Peripheral Chip Select 2 */
+#define AT91C_PIO_PA27            ( ( unsigned int ) 1 << 27 )        /* Pin Controlled by PA27 */
+#define AT91C_PA27_DRXD           ( ( unsigned int ) AT91C_PIO_PA27 ) /*  DBGU Debug Receive Data */
+#define AT91C_PA27_PCK3           ( ( unsigned int ) AT91C_PIO_PA27 ) /*  PMC Programmable Clock Output 3 */
+#define AT91C_PIO_PA28            ( ( unsigned int ) 1 << 28 )        /* Pin Controlled by PA28 */
+#define AT91C_PA28_DTXD           ( ( unsigned int ) AT91C_PIO_PA28 ) /*  DBGU Debug Transmit Data */
+#define AT91C_PIO_PA29            ( ( unsigned int ) 1 << 29 )        /* Pin Controlled by PA29 */
+#define AT91C_PA29_FIQ            ( ( unsigned int ) AT91C_PIO_PA29 ) /*  AIC Fast Interrupt Input */
+#define AT91C_PA29_NPCS13         ( ( unsigned int ) AT91C_PIO_PA29 ) /*  SPI 1 Peripheral Chip Select 3 */
+#define AT91C_PIO_PA3             ( ( unsigned int ) 1 << 3 )         /* Pin Controlled by PA3 */
+#define AT91C_PA3_RTS0            ( ( unsigned int ) AT91C_PIO_PA3 )  /*  USART 0 Ready To Send */
+#define AT91C_PA3_NPCS12          ( ( unsigned int ) AT91C_PIO_PA3 )  /*  SPI 1 Peripheral Chip Select 2 */
+#define AT91C_PIO_PA30            ( ( unsigned int ) 1 << 30 )        /* Pin Controlled by PA30 */
+#define AT91C_PA30_IRQ0           ( ( unsigned int ) AT91C_PIO_PA30 ) /*  External Interrupt 0 */
+#define AT91C_PA30_PCK2           ( ( unsigned int ) AT91C_PIO_PA30 ) /*  PMC Programmable Clock Output 2 */
+#define AT91C_PIO_PA4             ( ( unsigned int ) 1 << 4 )         /* Pin Controlled by PA4 */
+#define AT91C_PA4_CTS0            ( ( unsigned int ) AT91C_PIO_PA4 )  /*  USART 0 Clear To Send */
+#define AT91C_PA4_NPCS13          ( ( unsigned int ) AT91C_PIO_PA4 )  /*  SPI 1 Peripheral Chip Select 3 */
+#define AT91C_PIO_PA5             ( ( unsigned int ) 1 << 5 )         /* Pin Controlled by PA5 */
+#define AT91C_PA5_RXD1            ( ( unsigned int ) AT91C_PIO_PA5 )  /*  USART 1 Receive Data */
+#define AT91C_PIO_PA6             ( ( unsigned int ) 1 << 6 )         /* Pin Controlled by PA6 */
+#define AT91C_PA6_TXD1            ( ( unsigned int ) AT91C_PIO_PA6 )  /*  USART 1 Transmit Data */
+#define AT91C_PIO_PA7             ( ( unsigned int ) 1 << 7 )         /* Pin Controlled by PA7 */
+#define AT91C_PA7_SCK1            ( ( unsigned int ) AT91C_PIO_PA7 )  /*  USART 1 Serial Clock */
+#define AT91C_PA7_NPCS01          ( ( unsigned int ) AT91C_PIO_PA7 )  /*  SPI 0 Peripheral Chip Select 1 */
+#define AT91C_PIO_PA8             ( ( unsigned int ) 1 << 8 )         /* Pin Controlled by PA8 */
+#define AT91C_PA8_RTS1            ( ( unsigned int ) AT91C_PIO_PA8 )  /*  USART 1 Ready To Send */
+#define AT91C_PA8_NPCS02          ( ( unsigned int ) AT91C_PIO_PA8 )  /*  SPI 0 Peripheral Chip Select 2 */
+#define AT91C_PIO_PA9             ( ( unsigned int ) 1 << 9 )         /* Pin Controlled by PA9 */
+#define AT91C_PA9_CTS1            ( ( unsigned int ) AT91C_PIO_PA9 )  /*  USART 1 Clear To Send */
+#define AT91C_PA9_NPCS03          ( ( unsigned int ) AT91C_PIO_PA9 )  /*  SPI 0 Peripheral Chip Select 3 */
+#define AT91C_PIO_PB0             ( ( unsigned int ) 1 << 0 )         /* Pin Controlled by PB0 */
+#define AT91C_PB0_ETXCK_EREFCK    ( ( unsigned int ) AT91C_PIO_PB0 )  /*  Ethernet MAC Transmit Clock/Reference Clock */
+#define AT91C_PB0_PCK0            ( ( unsigned int ) AT91C_PIO_PB0 )  /*  PMC Programmable Clock Output 0 */
+#define AT91C_PIO_PB1             ( ( unsigned int ) 1 << 1 )         /* Pin Controlled by PB1 */
+#define AT91C_PB1_ETXEN           ( ( unsigned int ) AT91C_PIO_PB1 )  /*  Ethernet MAC Transmit Enable */
+#define AT91C_PIO_PB10            ( ( unsigned int ) 1 << 10 )        /* Pin Controlled by PB10 */
+#define AT91C_PB10_ETX2           ( ( unsigned int ) AT91C_PIO_PB10 ) /*  Ethernet MAC Transmit Data 2 */
+#define AT91C_PB10_NPCS11         ( ( unsigned int ) AT91C_PIO_PB10 ) /*  SPI 1 Peripheral Chip Select 1 */
+#define AT91C_PIO_PB11            ( ( unsigned int ) 1 << 11 )        /* Pin Controlled by PB11 */
+#define AT91C_PB11_ETX3           ( ( unsigned int ) AT91C_PIO_PB11 ) /*  Ethernet MAC Transmit Data 3 */
+#define AT91C_PB11_NPCS12         ( ( unsigned int ) AT91C_PIO_PB11 ) /*  SPI 1 Peripheral Chip Select 2 */
+#define AT91C_PIO_PB12            ( ( unsigned int ) 1 << 12 )        /* Pin Controlled by PB12 */
+#define AT91C_PB12_ETXER          ( ( unsigned int ) AT91C_PIO_PB12 ) /*  Ethernet MAC Transmit Coding Error */
+#define AT91C_PB12_TCLK0          ( ( unsigned int ) AT91C_PIO_PB12 ) /*  Timer Counter 0 external clock input */
+#define AT91C_PIO_PB13            ( ( unsigned int ) 1 << 13 )        /* Pin Controlled by PB13 */
+#define AT91C_PB13_ERX2           ( ( unsigned int ) AT91C_PIO_PB13 ) /*  Ethernet MAC Receive Data 2 */
+#define AT91C_PB13_NPCS01         ( ( unsigned int ) AT91C_PIO_PB13 ) /*  SPI 0 Peripheral Chip Select 1 */
+#define AT91C_PIO_PB14            ( ( unsigned int ) 1 << 14 )        /* Pin Controlled by PB14 */
+#define AT91C_PB14_ERX3           ( ( unsigned int ) AT91C_PIO_PB14 ) /*  Ethernet MAC Receive Data 3 */
+#define AT91C_PB14_NPCS02         ( ( unsigned int ) AT91C_PIO_PB14 ) /*  SPI 0 Peripheral Chip Select 2 */
+#define AT91C_PIO_PB15            ( ( unsigned int ) 1 << 15 )        /* Pin Controlled by PB15 */
+#define AT91C_PB15_ERXDV          ( ( unsigned int ) AT91C_PIO_PB15 ) /*  Ethernet MAC Receive Data Valid */
+#define AT91C_PIO_PB16            ( ( unsigned int ) 1 << 16 )        /* Pin Controlled by PB16 */
+#define AT91C_PB16_ECOL           ( ( unsigned int ) AT91C_PIO_PB16 ) /*  Ethernet MAC Collision Detected */
+#define AT91C_PB16_NPCS13         ( ( unsigned int ) AT91C_PIO_PB16 ) /*  SPI 1 Peripheral Chip Select 3 */
+#define AT91C_PIO_PB17            ( ( unsigned int ) 1 << 17 )        /* Pin Controlled by PB17 */
+#define AT91C_PB17_ERXCK          ( ( unsigned int ) AT91C_PIO_PB17 ) /*  Ethernet MAC Receive Clock */
+#define AT91C_PB17_NPCS03         ( ( unsigned int ) AT91C_PIO_PB17 ) /*  SPI 0 Peripheral Chip Select 3 */
+#define AT91C_PIO_PB18            ( ( unsigned int ) 1 << 18 )        /* Pin Controlled by PB18 */
+#define AT91C_PB18_EF100          ( ( unsigned int ) AT91C_PIO_PB18 ) /*  Ethernet MAC Force 100 Mbits/sec */
+#define AT91C_PB18_ADTRG          ( ( unsigned int ) AT91C_PIO_PB18 ) /*  ADC External Trigger */
+#define AT91C_PIO_PB19            ( ( unsigned int ) 1 << 19 )        /* Pin Controlled by PB19 */
+#define AT91C_PB19_PWM0           ( ( unsigned int ) AT91C_PIO_PB19 ) /*  PWM Channel 0 */
+#define AT91C_PB19_TCLK1          ( ( unsigned int ) AT91C_PIO_PB19 ) /*  Timer Counter 1 external clock input */
+#define AT91C_PIO_PB2             ( ( unsigned int ) 1 << 2 )         /* Pin Controlled by PB2 */
+#define AT91C_PB2_ETX0            ( ( unsigned int ) AT91C_PIO_PB2 )  /*  Ethernet MAC Transmit Data 0 */
+#define AT91C_PIO_PB20            ( ( unsigned int ) 1 << 20 )        /* Pin Controlled by PB20 */
+#define AT91C_PB20_PWM1           ( ( unsigned int ) AT91C_PIO_PB20 ) /*  PWM Channel 1 */
+#define AT91C_PB20_PCK0           ( ( unsigned int ) AT91C_PIO_PB20 ) /*  PMC Programmable Clock Output 0 */
+#define AT91C_PIO_PB21            ( ( unsigned int ) 1 << 21 )        /* Pin Controlled by PB21 */
+#define AT91C_PB21_PWM2           ( ( unsigned int ) AT91C_PIO_PB21 ) /*  PWM Channel 2 */
+#define AT91C_PB21_PCK1           ( ( unsigned int ) AT91C_PIO_PB21 ) /*  PMC Programmable Clock Output 1 */
+#define AT91C_PIO_PB22            ( ( unsigned int ) 1 << 22 )        /* Pin Controlled by PB22 */
+#define AT91C_PB22_PWM3           ( ( unsigned int ) AT91C_PIO_PB22 ) /*  PWM Channel 3 */
+#define AT91C_PB22_PCK2           ( ( unsigned int ) AT91C_PIO_PB22 ) /*  PMC Programmable Clock Output 2 */
+#define AT91C_PIO_PB23            ( ( unsigned int ) 1 << 23 )        /* Pin Controlled by PB23 */
+#define AT91C_PB23_TIOA0          ( ( unsigned int ) AT91C_PIO_PB23 ) /*  Timer Counter 0 Multipurpose Timer I/O Pin A */
+#define AT91C_PB23_DCD1           ( ( unsigned int ) AT91C_PIO_PB23 ) /*  USART 1 Data Carrier Detect */
+#define AT91C_PIO_PB24            ( ( unsigned int ) 1 << 24 )        /* Pin Controlled by PB24 */
+#define AT91C_PB24_TIOB0          ( ( unsigned int ) AT91C_PIO_PB24 ) /*  Timer Counter 0 Multipurpose Timer I/O Pin B */
+#define AT91C_PB24_DSR1           ( ( unsigned int ) AT91C_PIO_PB24 ) /*  USART 1 Data Set ready */
+#define AT91C_PIO_PB25            ( ( unsigned int ) 1 << 25 )        /* Pin Controlled by PB25 */
+#define AT91C_PB25_TIOA1          ( ( unsigned int ) AT91C_PIO_PB25 ) /*  Timer Counter 1 Multipurpose Timer I/O Pin A */
+#define AT91C_PB25_DTR1           ( ( unsigned int ) AT91C_PIO_PB25 ) /*  USART 1 Data Terminal ready */
+#define AT91C_PIO_PB26            ( ( unsigned int ) 1 << 26 )        /* Pin Controlled by PB26 */
+#define AT91C_PB26_TIOB1          ( ( unsigned int ) AT91C_PIO_PB26 ) /*  Timer Counter 1 Multipurpose Timer I/O Pin B */
+#define AT91C_PB26_RI1            ( ( unsigned int ) AT91C_PIO_PB26 ) /*  USART 1 Ring Indicator */
+#define AT91C_PIO_PB27            ( ( unsigned int ) 1 << 27 )        /* Pin Controlled by PB27 */
+#define AT91C_PB27_TIOA2          ( ( unsigned int ) AT91C_PIO_PB27 ) /*  Timer Counter 2 Multipurpose Timer I/O Pin A */
+#define AT91C_PB27_PWM0           ( ( unsigned int ) AT91C_PIO_PB27 ) /*  PWM Channel 0 */
+#define AT91C_PIO_PB28            ( ( unsigned int ) 1 << 28 )        /* Pin Controlled by PB28 */
+#define AT91C_PB28_TIOB2          ( ( unsigned int ) AT91C_PIO_PB28 ) /*  Timer Counter 2 Multipurpose Timer I/O Pin B */
+#define AT91C_PB28_PWM1           ( ( unsigned int ) AT91C_PIO_PB28 ) /*  PWM Channel 1 */
+#define AT91C_PIO_PB29            ( ( unsigned int ) 1 << 29 )        /* Pin Controlled by PB29 */
+#define AT91C_PB29_PCK1           ( ( unsigned int ) AT91C_PIO_PB29 ) /*  PMC Programmable Clock Output 1 */
+#define AT91C_PB29_PWM2           ( ( unsigned int ) AT91C_PIO_PB29 ) /*  PWM Channel 2 */
+#define AT91C_PIO_PB3             ( ( unsigned int ) 1 << 3 )         /* Pin Controlled by PB3 */
+#define AT91C_PB3_ETX1            ( ( unsigned int ) AT91C_PIO_PB3 )  /*  Ethernet MAC Transmit Data 1 */
+#define AT91C_PIO_PB30            ( ( unsigned int ) 1 << 30 )        /* Pin Controlled by PB30 */
+#define AT91C_PB30_PCK2           ( ( unsigned int ) AT91C_PIO_PB30 ) /*  PMC Programmable Clock Output 2 */
+#define AT91C_PB30_PWM3           ( ( unsigned int ) AT91C_PIO_PB30 ) /*  PWM Channel 3 */
+#define AT91C_PIO_PB4             ( ( unsigned int ) 1 << 4 )         /* Pin Controlled by PB4 */
+#define AT91C_PB4_ECRS_ECRSDV     ( ( unsigned int ) AT91C_PIO_PB4 )  /*  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid */
+#define AT91C_PIO_PB5             ( ( unsigned int ) 1 << 5 )         /* Pin Controlled by PB5 */
+#define AT91C_PB5_ERX0            ( ( unsigned int ) AT91C_PIO_PB5 )  /*  Ethernet MAC Receive Data 0 */
+#define AT91C_PIO_PB6             ( ( unsigned int ) 1 << 6 )         /* Pin Controlled by PB6 */
+#define AT91C_PB6_ERX1            ( ( unsigned int ) AT91C_PIO_PB6 )  /*  Ethernet MAC Receive Data 1 */
+#define AT91C_PIO_PB7             ( ( unsigned int ) 1 << 7 )         /* Pin Controlled by PB7 */
+#define AT91C_PB7_ERXER           ( ( unsigned int ) AT91C_PIO_PB7 )  /*  Ethernet MAC Receive Error */
+#define AT91C_PIO_PB8             ( ( unsigned int ) 1 << 8 )         /* Pin Controlled by PB8 */
+#define AT91C_PB8_EMDC            ( ( unsigned int ) AT91C_PIO_PB8 )  /*  Ethernet MAC Management Data Clock */
+#define AT91C_PIO_PB9             ( ( unsigned int ) 1 << 9 )         /* Pin Controlled by PB9 */
+#define AT91C_PB9_EMDIO           ( ( unsigned int ) AT91C_PIO_PB9 )  /*  Ethernet MAC Management Data Input/Output */
+
+/* ***************************************************************************** */
+/*               PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 */
+/* ***************************************************************************** */
+#define AT91C_ID_FIQ            ( ( unsigned int ) 0 )  /* Advanced Interrupt Controller (FIQ) */
+#define AT91C_ID_SYS            ( ( unsigned int ) 1 )  /* System Peripheral */
+#define AT91C_ID_PIOA           ( ( unsigned int ) 2 )  /* Parallel IO Controller A */
+#define AT91C_ID_PIOB           ( ( unsigned int ) 3 )  /* Parallel IO Controller B */
+#define AT91C_ID_SPI0           ( ( unsigned int ) 4 )  /* Serial Peripheral Interface 0 */
+#define AT91C_ID_SPI1           ( ( unsigned int ) 5 )  /* Serial Peripheral Interface 1 */
+#define AT91C_ID_US0            ( ( unsigned int ) 6 )  /* USART 0 */
+#define AT91C_ID_US1            ( ( unsigned int ) 7 )  /* USART 1 */
+#define AT91C_ID_SSC            ( ( unsigned int ) 8 )  /* Serial Synchronous Controller */
+#define AT91C_ID_TWI            ( ( unsigned int ) 9 )  /* Two-Wire Interface */
+#define AT91C_ID_PWMC           ( ( unsigned int ) 10 ) /* PWM Controller */
+#define AT91C_ID_UDP            ( ( unsigned int ) 11 ) /* USB Device Port */
+#define AT91C_ID_TC0            ( ( unsigned int ) 12 ) /* Timer Counter 0 */
+#define AT91C_ID_TC1            ( ( unsigned int ) 13 ) /* Timer Counter 1 */
+#define AT91C_ID_TC2            ( ( unsigned int ) 14 ) /* Timer Counter 2 */
+#define AT91C_ID_CAN            ( ( unsigned int ) 15 ) /* Control Area Network Controller */
+#define AT91C_ID_EMAC           ( ( unsigned int ) 16 ) /* Ethernet MAC */
+#define AT91C_ID_ADC            ( ( unsigned int ) 17 ) /* Analog-to-Digital Converter */
+#define AT91C_ID_AES            ( ( unsigned int ) 18 ) /* Advanced Encryption Standard 128-bit */
+#define AT91C_ID_TDES           ( ( unsigned int ) 19 ) /* Triple Data Encryption Standard */
+#define AT91C_ID_20_Reserved    ( ( unsigned int ) 20 ) /* Reserved */
+#define AT91C_ID_21_Reserved    ( ( unsigned int ) 21 ) /* Reserved */
+#define AT91C_ID_22_Reserved    ( ( unsigned int ) 22 ) /* Reserved */
+#define AT91C_ID_23_Reserved    ( ( unsigned int ) 23 ) /* Reserved */
+#define AT91C_ID_24_Reserved    ( ( unsigned int ) 24 ) /* Reserved */
+#define AT91C_ID_25_Reserved    ( ( unsigned int ) 25 ) /* Reserved */
+#define AT91C_ID_26_Reserved    ( ( unsigned int ) 26 ) /* Reserved */
+#define AT91C_ID_27_Reserved    ( ( unsigned int ) 27 ) /* Reserved */
+#define AT91C_ID_28_Reserved    ( ( unsigned int ) 28 ) /* Reserved */
+#define AT91C_ID_29_Reserved    ( ( unsigned int ) 29 ) /* Reserved */
+#define AT91C_ID_IRQ0           ( ( unsigned int ) 30 ) /* Advanced Interrupt Controller (IRQ0) */
+#define AT91C_ID_IRQ1           ( ( unsigned int ) 31 ) /* Advanced Interrupt Controller (IRQ1) */
+
+/* ***************************************************************************** */
+/*               BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 */
+/* ***************************************************************************** */
+#define AT91C_BASE_SYS         ( ( AT91PS_SYS ) 0xFFFFF000 )     /* (SYS) Base Address */
+#define AT91C_BASE_AIC         ( ( AT91PS_AIC ) 0xFFFFF000 )     /* (AIC) Base Address */
+#define AT91C_BASE_PDC_DBGU    ( ( AT91PS_PDC ) 0xFFFFF300 )     /* (PDC_DBGU) Base Address */
+#define AT91C_BASE_DBGU        ( ( AT91PS_DBGU ) 0xFFFFF200 )    /* (DBGU) Base Address */
+#define AT91C_BASE_PIOA        ( ( AT91PS_PIO ) 0xFFFFF400 )     /* (PIOA) Base Address */
+#define AT91C_BASE_PIOB        ( ( AT91PS_PIO ) 0xFFFFF600 )     /* (PIOB) Base Address */
+#define AT91C_BASE_CKGR        ( ( AT91PS_CKGR ) 0xFFFFFC20 )    /* (CKGR) Base Address */
+#define AT91C_BASE_PMC         ( ( AT91PS_PMC ) 0xFFFFFC00 )     /* (PMC) Base Address */
+#define AT91C_BASE_RSTC        ( ( AT91PS_RSTC ) 0xFFFFFD00 )    /* (RSTC) Base Address */
+#define AT91C_BASE_RTTC        ( ( AT91PS_RTTC ) 0xFFFFFD20 )    /* (RTTC) Base Address */
+#define AT91C_BASE_PITC        ( ( AT91PS_PITC ) 0xFFFFFD30 )    /* (PITC) Base Address */
+#define AT91C_BASE_WDTC        ( ( AT91PS_WDTC ) 0xFFFFFD40 )    /* (WDTC) Base Address */
+#define AT91C_BASE_VREG        ( ( AT91PS_VREG ) 0xFFFFFD60 )    /* (VREG) Base Address */
+#define AT91C_BASE_MC          ( ( AT91PS_MC ) 0xFFFFFF00 )      /* (MC) Base Address */
+#define AT91C_BASE_PDC_SPI1    ( ( AT91PS_PDC ) 0xFFFE4100 )     /* (PDC_SPI1) Base Address */
+#define AT91C_BASE_SPI1        ( ( AT91PS_SPI ) 0xFFFE4000 )     /* (SPI1) Base Address */
+#define AT91C_BASE_PDC_SPI0    ( ( AT91PS_PDC ) 0xFFFE0100 )     /* (PDC_SPI0) Base Address */
+#define AT91C_BASE_SPI0        ( ( AT91PS_SPI ) 0xFFFE0000 )     /* (SPI0) Base Address */
+#define AT91C_BASE_PDC_US1     ( ( AT91PS_PDC ) 0xFFFC4100 )     /* (PDC_US1) Base Address */
+#define AT91C_BASE_US1         ( ( AT91PS_USART ) 0xFFFC4000 )   /* (US1) Base Address */
+#define AT91C_BASE_PDC_US0     ( ( AT91PS_PDC ) 0xFFFC0100 )     /* (PDC_US0) Base Address */
+#define AT91C_BASE_US0         ( ( AT91PS_USART ) 0xFFFC0000 )   /* (US0) Base Address */
+#define AT91C_BASE_PDC_SSC     ( ( AT91PS_PDC ) 0xFFFD4100 )     /* (PDC_SSC) Base Address */
+#define AT91C_BASE_SSC         ( ( AT91PS_SSC ) 0xFFFD4000 )     /* (SSC) Base Address */
+#define AT91C_BASE_TWI         ( ( AT91PS_TWI ) 0xFFFB8000 )     /* (TWI) Base Address */
+#define AT91C_BASE_PWMC_CH3    ( ( AT91PS_PWMC_CH ) 0xFFFCC260 ) /* (PWMC_CH3) Base Address */
+#define AT91C_BASE_PWMC_CH2    ( ( AT91PS_PWMC_CH ) 0xFFFCC240 ) /* (PWMC_CH2) Base Address */
+#define AT91C_BASE_PWMC_CH1    ( ( AT91PS_PWMC_CH ) 0xFFFCC220 ) /* (PWMC_CH1) Base Address */
+#define AT91C_BASE_PWMC_CH0    ( ( AT91PS_PWMC_CH ) 0xFFFCC200 ) /* (PWMC_CH0) Base Address */
+#define AT91C_BASE_PWMC        ( ( AT91PS_PWMC ) 0xFFFCC000 )    /* (PWMC) Base Address */
+#define AT91C_BASE_UDP         ( ( AT91PS_UDP ) 0xFFFB0000 )     /* (UDP) Base Address */
+#define AT91C_BASE_TC0         ( ( AT91PS_TC ) 0xFFFA0000 )      /* (TC0) Base Address */
+#define AT91C_BASE_TC1         ( ( AT91PS_TC ) 0xFFFA0040 )      /* (TC1) Base Address */
+#define AT91C_BASE_TC2         ( ( AT91PS_TC ) 0xFFFA0080 )      /* (TC2) Base Address */
+#define AT91C_BASE_TCB         ( ( AT91PS_TCB ) 0xFFFA0000 )     /* (TCB) Base Address */
+#define AT91C_BASE_CAN_MB0     ( ( AT91PS_CAN_MB ) 0xFFFD0200 )  /* (CAN_MB0) Base Address */
+#define AT91C_BASE_CAN_MB1     ( ( AT91PS_CAN_MB ) 0xFFFD0220 )  /* (CAN_MB1) Base Address */
+#define AT91C_BASE_CAN_MB2     ( ( AT91PS_CAN_MB ) 0xFFFD0240 )  /* (CAN_MB2) Base Address */
+#define AT91C_BASE_CAN_MB3     ( ( AT91PS_CAN_MB ) 0xFFFD0260 )  /* (CAN_MB3) Base Address */
+#define AT91C_BASE_CAN_MB4     ( ( AT91PS_CAN_MB ) 0xFFFD0280 )  /* (CAN_MB4) Base Address */
+#define AT91C_BASE_CAN_MB5     ( ( AT91PS_CAN_MB ) 0xFFFD02A0 )  /* (CAN_MB5) Base Address */
+#define AT91C_BASE_CAN_MB6     ( ( AT91PS_CAN_MB ) 0xFFFD02C0 )  /* (CAN_MB6) Base Address */
+#define AT91C_BASE_CAN_MB7     ( ( AT91PS_CAN_MB ) 0xFFFD02E0 )  /* (CAN_MB7) Base Address */
+#define AT91C_BASE_CAN         ( ( AT91PS_CAN ) 0xFFFD0000 )     /* (CAN) Base Address */
+#define AT91C_BASE_EMAC        ( ( AT91PS_EMAC ) 0xFFFDC000 )    /* (EMAC) Base Address */
+#define AT91C_BASE_PDC_ADC     ( ( AT91PS_PDC ) 0xFFFD8100 )     /* (PDC_ADC) Base Address */
+#define AT91C_BASE_ADC         ( ( AT91PS_ADC ) 0xFFFD8000 )     /* (ADC) Base Address */
+#define AT91C_BASE_PDC_AES     ( ( AT91PS_PDC ) 0xFFFA4100 )     /* (PDC_AES) Base Address */
+#define AT91C_BASE_AES         ( ( AT91PS_AES ) 0xFFFA4000 )     /* (AES) Base Address */
+#define AT91C_BASE_PDC_TDES    ( ( AT91PS_PDC ) 0xFFFA8100 )     /* (PDC_TDES) Base Address */
+#define AT91C_BASE_TDES        ( ( AT91PS_TDES ) 0xFFFA8000 )    /* (TDES) Base Address */
+
+/* ***************************************************************************** */
+/*               MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 */
+/* ***************************************************************************** */
+#define AT91C_ISRAM          ( ( char * ) 0x00200000 )       /* Internal SRAM base address */
+#define AT91C_ISRAM_SIZE     ( ( unsigned int ) 0x00010000 ) /* Internal SRAM size in byte (64 Kbyte) */
+#define AT91C_IFLASH         ( ( char * ) 0x00100000 )       /* Internal ROM base address */
+#define AT91C_IFLASH_SIZE    ( ( unsigned int ) 0x00040000 ) /* Internal ROM size in byte (256 Kbyte) */
+
+
+
+/* - Hardware register definition */
+
+/* - ***************************************************************************** */
+/* -              SOFTWARE API DEFINITION  FOR System Peripherals */
+/* - ***************************************************************************** */
+
+/* - ***************************************************************************** */
+/* -              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller */
+/* - ***************************************************************************** */
+/* - -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- */
 #if 0 /*_RB_*/
-AT91C_AIC_PRIOR           EQU (0x7 <<  0) ;- (AIC) Priority Level
-AT91C_AIC_PRIOR_LOWEST    EQU (0x0) ;- (AIC) Lowest priority level
-AT91C_AIC_PRIOR_HIGHEST   EQU (0x7) ;- (AIC) Highest priority level
-AT91C_AIC_SRCTYPE         EQU (0x3 <<  5) ;- (AIC) Interrupt Source Type
-AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL EQU (0x0 <<  5) ;- (AIC) Internal Sources Code Label High-level Sensitive
-AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL EQU (0x0 <<  5) ;- (AIC) External Sources Code Label Low-level Sensitive
-AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE EQU (0x1 <<  5) ;- (AIC) Internal Sources Code Label Positive Edge triggered
-AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE EQU (0x1 <<  5) ;- (AIC) External Sources Code Label Negative Edge triggered
-AT91C_AIC_SRCTYPE_HIGH_LEVEL EQU (0x2 <<  5) ;- (AIC) Internal Or External Sources Code Label High-level Sensitive
-AT91C_AIC_SRCTYPE_POSITIVE_EDGE EQU (0x3 <<  5) ;- (AIC) Internal Or External Sources Code Label Positive Edge triggered
-// - -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
-AT91C_AIC_NFIQ            EQU (0x1 <<  0) ;- (AIC) NFIQ Status
-AT91C_AIC_NIRQ            EQU (0x1 <<  1) ;- (AIC) NIRQ Status
-// - -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
-AT91C_AIC_DCR_PROT        EQU (0x1 <<  0) ;- (AIC) Protection Mode
-AT91C_AIC_DCR_GMSK        EQU (0x1 <<  1) ;- (AIC) General Mask
-#endif
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller
-// - *****************************************************************************
-// - -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
-AT91C_PDC_RXTEN           EQU (0x1 <<  0) ;- (PDC) Receiver Transfer Enable
-AT91C_PDC_RXTDIS          EQU (0x1 <<  1) ;- (PDC) Receiver Transfer Disable
-AT91C_PDC_TXTEN           EQU (0x1 <<  8) ;- (PDC) Transmitter Transfer Enable
-AT91C_PDC_TXTDIS          EQU (0x1 <<  9) ;- (PDC) Transmitter Transfer Disable
-// - -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
+    AT91C_AIC_PRIOR EQU( 0x7 << 0 );
+    -( AIC ) Priority Level
+    AT91C_AIC_PRIOR_LOWEST EQU( 0x0 );
+    -( AIC ) Lowest priority level
+    AT91C_AIC_PRIOR_HIGHEST EQU( 0x7 );
+    -( AIC ) Highest priority level
+    AT91C_AIC_SRCTYPE EQU( 0x3 << 5 );
+    -( AIC ) Interrupt Source Type
+    AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL EQU( 0x0 << 5 );
+    -( AIC ) Internal Sources Code Label High - level Sensitive
+    AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL EQU( 0x0 << 5 );
+    -( AIC ) External Sources Code Label Low - level Sensitive
+    AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE EQU( 0x1 << 5 );
+    -( AIC ) Internal Sources Code Label Positive Edge triggered
+    AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE EQU( 0x1 << 5 );
+    -( AIC ) External Sources Code Label Negative Edge triggered
+    AT91C_AIC_SRCTYPE_HIGH_LEVEL EQU( 0x2 << 5 );
+    -( AIC ) Internal Or External Sources Code Label High - level Sensitive
+    AT91C_AIC_SRCTYPE_POSITIVE_EDGE EQU( 0x3 << 5 );
+    -( AIC ) Internal Or External Sources Code Label Positive Edge triggered
+/* - -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- */
+    AT91C_AIC_NFIQ EQU( 0x1 << 0 );
+    -( AIC ) NFIQ Status
+    AT91C_AIC_NIRQ EQU( 0x1 << 1 );
+    -( AIC ) NIRQ Status
+/* - -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- */
+    AT91C_AIC_DCR_PROT EQU( 0x1 << 0 );
+    -( AIC ) Protection Mode
+    AT91C_AIC_DCR_GMSK EQU( 0x1 << 1 );
+    -( AIC ) General Mask
+#endif /* if 0 */
+/* - ***************************************************************************** */
+/* -              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller */
+/* - ***************************************************************************** */
+/* - -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */
+AT91C_PDC_RXTEN EQU( 0x1 << 0 );
+-( PDC ) Receiver Transfer Enable
+AT91C_PDC_RXTDIS EQU( 0x1 << 1 );
+-( PDC ) Receiver Transfer Disable
+AT91C_PDC_TXTEN EQU( 0x1 << 8 );
+-( PDC ) Transmitter Transfer Enable
+AT91C_PDC_TXTDIS EQU( 0x1 << 9 );
+-( PDC ) Transmitter Transfer Disable
+/* - -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- */
 
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Debug Unit
-// - *****************************************************************************
-// - -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
-AT91C_US_RSTRX            EQU (0x1 <<  2) ;- (DBGU) Reset Receiver
-AT91C_US_RSTTX            EQU (0x1 <<  3) ;- (DBGU) Reset Transmitter
-AT91C_US_RXEN             EQU (0x1 <<  4) ;- (DBGU) Receiver Enable
-AT91C_US_RXDIS            EQU (0x1 <<  5) ;- (DBGU) Receiver Disable
-AT91C_US_TXEN             EQU (0x1 <<  6) ;- (DBGU) Transmitter Enable
-AT91C_US_TXDIS            EQU (0x1 <<  7) ;- (DBGU) Transmitter Disable
-AT91C_US_RSTSTA           EQU (0x1 <<  8) ;- (DBGU) Reset Status Bits
-// - -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
-AT91C_US_PAR              EQU (0x7 <<  9) ;- (DBGU) Parity type
-AT91C_US_PAR_EVEN         EQU (0x0 <<  9) ;- (DBGU) Even Parity
-AT91C_US_PAR_ODD          EQU (0x1 <<  9) ;- (DBGU) Odd Parity
-AT91C_US_PAR_SPACE        EQU (0x2 <<  9) ;- (DBGU) Parity forced to 0 (Space)
-AT91C_US_PAR_MARK         EQU (0x3 <<  9) ;- (DBGU) Parity forced to 1 (Mark)
-AT91C_US_PAR_NONE         EQU (0x4 <<  9) ;- (DBGU) No Parity
-AT91C_US_PAR_MULTI_DROP   EQU (0x6 <<  9) ;- (DBGU) Multi-drop mode
-AT91C_US_CHMODE           EQU (0x3 << 14) ;- (DBGU) Channel Mode
-AT91C_US_CHMODE_NORMAL    EQU (0x0 << 14) ;- (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
-AT91C_US_CHMODE_AUTO      EQU (0x1 << 14) ;- (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
-AT91C_US_CHMODE_LOCAL     EQU (0x2 << 14) ;- (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
-AT91C_US_CHMODE_REMOTE    EQU (0x3 << 14) ;- (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
-// - -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
-AT91C_US_RXRDY            EQU (0x1 <<  0) ;- (DBGU) RXRDY Interrupt
-AT91C_US_TXRDY            EQU (0x1 <<  1) ;- (DBGU) TXRDY Interrupt
-AT91C_US_ENDRX            EQU (0x1 <<  3) ;- (DBGU) End of Receive Transfer Interrupt
-AT91C_US_ENDTX            EQU (0x1 <<  4) ;- (DBGU) End of Transmit Interrupt
-AT91C_US_OVRE             EQU (0x1 <<  5) ;- (DBGU) Overrun Interrupt
-AT91C_US_FRAME            EQU (0x1 <<  6) ;- (DBGU) Framing Error Interrupt
-AT91C_US_PARE             EQU (0x1 <<  7) ;- (DBGU) Parity Error Interrupt
-AT91C_US_TXEMPTY          EQU (0x1 <<  9) ;- (DBGU) TXEMPTY Interrupt
-AT91C_US_TXBUFE           EQU (0x1 << 11) ;- (DBGU) TXBUFE Interrupt
-AT91C_US_RXBUFF           EQU (0x1 << 12) ;- (DBGU) RXBUFF Interrupt
-AT91C_US_COMM_TX          EQU (0x1 << 30) ;- (DBGU) COMM_TX Interrupt
-AT91C_US_COMM_RX          EQU (0x1 << 31) ;- (DBGU) COMM_RX Interrupt
-// - -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
-// - -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
-// - -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
-// - -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
-AT91C_US_FORCE_NTRST      EQU (0x1 <<  0) ;- (DBGU) Force NTRST in JTAG
+/* - ***************************************************************************** */
+/* -              SOFTWARE API DEFINITION  FOR Debug Unit */
+/* - ***************************************************************************** */
+/* - -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- */
+AT91C_US_RSTRX EQU( 0x1 << 2 );
+-( DBGU ) Reset Receiver
+AT91C_US_RSTTX EQU( 0x1 << 3 );
+-( DBGU ) Reset Transmitter
+AT91C_US_RXEN EQU( 0x1 << 4 );
+-( DBGU ) Receiver Enable
+AT91C_US_RXDIS EQU( 0x1 << 5 );
+-( DBGU ) Receiver Disable
+AT91C_US_TXEN EQU( 0x1 << 6 );
+-( DBGU ) Transmitter Enable
+AT91C_US_TXDIS EQU( 0x1 << 7 );
+-( DBGU ) Transmitter Disable
+AT91C_US_RSTSTA EQU( 0x1 << 8 );
+-( DBGU ) Reset Status Bits
+/* - -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- */
+AT91C_US_PAR EQU( 0x7 << 9 );
+-( DBGU ) Parity type
+AT91C_US_PAR_EVEN EQU( 0x0 << 9 );
+-( DBGU ) Even Parity
+AT91C_US_PAR_ODD EQU( 0x1 << 9 );
+-( DBGU ) Odd Parity
+AT91C_US_PAR_SPACE EQU( 0x2 << 9 );
+-( DBGU ) Parity forced to 0 ( Space )
+AT91C_US_PAR_MARK EQU( 0x3 << 9 );
+-( DBGU ) Parity forced to 1 ( Mark )
+AT91C_US_PAR_NONE EQU( 0x4 << 9 );
+-( DBGU ) No Parity
+AT91C_US_PAR_MULTI_DROP EQU( 0x6 << 9 );
+-( DBGU ) Multi - drop mode
+AT91C_US_CHMODE EQU( 0x3 << 14 );
+-( DBGU ) Channel Mode
+AT91C_US_CHMODE_NORMAL EQU( 0x0 << 14 );
+-( DBGU ) Normal Mode: The USART channel operates as an RX / TX USART.
+   AT91C_US_CHMODE_AUTO EQU( 0x1 << 14 );
+-( DBGU ) Automatic Echo: Receiver Data Input is connected to the TXD pin.
+   AT91C_US_CHMODE_LOCAL EQU( 0x2 << 14 );
+-( DBGU ) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
+   AT91C_US_CHMODE_REMOTE EQU( 0x3 << 14 );
+-( DBGU ) Remote Loopback: RXD pin is internally connected to TXD pin.
+/* - -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */
+   AT91C_US_RXRDY EQU( 0x1 << 0 );
+-( DBGU ) RXRDY Interrupt
+AT91C_US_TXRDY EQU( 0x1 << 1 );
+-( DBGU ) TXRDY Interrupt
+AT91C_US_ENDRX EQU( 0x1 << 3 );
+-( DBGU ) End of Receive Transfer Interrupt
+AT91C_US_ENDTX EQU( 0x1 << 4 );
+-( DBGU ) End of Transmit Interrupt
+AT91C_US_OVRE EQU( 0x1 << 5 );
+-( DBGU ) Overrun Interrupt
+AT91C_US_FRAME EQU( 0x1 << 6 );
+-( DBGU ) Framing Error Interrupt
+AT91C_US_PARE EQU( 0x1 << 7 );
+-( DBGU ) Parity Error Interrupt
+AT91C_US_TXEMPTY EQU( 0x1 << 9 );
+-( DBGU ) TXEMPTY Interrupt
+AT91C_US_TXBUFE EQU( 0x1 << 11 );
+-( DBGU ) TXBUFE Interrupt
+AT91C_US_RXBUFF EQU( 0x1 << 12 );
+-( DBGU ) RXBUFF Interrupt
+AT91C_US_COMM_TX EQU( 0x1 << 30 );
+-( DBGU ) COMM_TX Interrupt
+AT91C_US_COMM_RX EQU( 0x1 << 31 );
+-( DBGU ) COMM_RX Interrupt
+/* - -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- */
+/* - -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- */
+/* - -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- */
+/* - -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- */
+AT91C_US_FORCE_NTRST EQU( 0x1 << 0 );
+-( DBGU ) Force NTRST in JTAG
 
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
-// - *****************************************************************************
+/* - ***************************************************************************** */
+/* -              SOFTWARE API DEFINITION  FOR Parallel Input Output Controller */
+/* - ***************************************************************************** */
 
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Clock Generator Controler
-// - *****************************************************************************
-// - -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
-AT91C_CKGR_MOSCEN         EQU (0x1 <<  0) ;- (CKGR) Main Oscillator Enable
-AT91C_CKGR_OSCBYPASS      EQU (0x1 <<  1) ;- (CKGR) Main Oscillator Bypass
-AT91C_CKGR_OSCOUNT        EQU (0xFF <<  8) ;- (CKGR) Main Oscillator Start-up Time
-// - -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
-AT91C_CKGR_MAINF          EQU (0xFFFF <<  0) ;- (CKGR) Main Clock Frequency
-AT91C_CKGR_MAINRDY        EQU (0x1 << 16) ;- (CKGR) Main Clock Ready
-// - -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
-AT91C_CKGR_DIV            EQU (0xFF <<  0) ;- (CKGR) Divider Selected
-AT91C_CKGR_DIV_0          EQU (0x0) ;- (CKGR) Divider output is 0
-AT91C_CKGR_DIV_BYPASS     EQU (0x1) ;- (CKGR) Divider is bypassed
-AT91C_CKGR_PLLCOUNT       EQU (0x3F <<  8) ;- (CKGR) PLL Counter
-AT91C_CKGR_OUT            EQU (0x3 << 14) ;- (CKGR) PLL Output Frequency Range
-AT91C_CKGR_OUT_0          EQU (0x0 << 14) ;- (CKGR) Please refer to the PLL datasheet
-AT91C_CKGR_OUT_1          EQU (0x1 << 14) ;- (CKGR) Please refer to the PLL datasheet
-AT91C_CKGR_OUT_2          EQU (0x2 << 14) ;- (CKGR) Please refer to the PLL datasheet
-AT91C_CKGR_OUT_3          EQU (0x3 << 14) ;- (CKGR) Please refer to the PLL datasheet
-AT91C_CKGR_MUL            EQU (0x7FF << 16) ;- (CKGR) PLL Multiplier
-AT91C_CKGR_USBDIV         EQU (0x3 << 28) ;- (CKGR) Divider for USB Clocks
-AT91C_CKGR_USBDIV_0       EQU (0x0 << 28) ;- (CKGR) Divider output is PLL clock output
-AT91C_CKGR_USBDIV_1       EQU (0x1 << 28) ;- (CKGR) Divider output is PLL clock output divided by 2
-AT91C_CKGR_USBDIV_2       EQU (0x2 << 28) ;- (CKGR) Divider output is PLL clock output divided by 4
+/* - ***************************************************************************** */
+/* -              SOFTWARE API DEFINITION  FOR Clock Generator Controller */
+/* - ***************************************************************************** */
+/* - -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */
+AT91C_CKGR_MOSCEN EQU( 0x1 << 0 );
+-( CKGR ) Main Oscillator Enable
+AT91C_CKGR_OSCBYPASS EQU( 0x1 << 1 );
+-( CKGR ) Main Oscillator Bypass
+AT91C_CKGR_OSCOUNT EQU( 0xFF << 8 );
+-( CKGR ) Main Oscillator Start - up Time
+/* - -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- */
+AT91C_CKGR_MAINF EQU( 0xFFFF << 0 );
+-( CKGR ) Main Clock Frequency
+AT91C_CKGR_MAINRDY EQU( 0x1 << 16 );
+-( CKGR ) Main Clock Ready
+/* - -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- */
+AT91C_CKGR_DIV EQU( 0xFF << 0 );
+-( CKGR ) Divider Selected
+AT91C_CKGR_DIV_0 EQU( 0x0 );
+-( CKGR ) Divider output is 0
+AT91C_CKGR_DIV_BYPASS EQU( 0x1 );
+-( CKGR ) Divider is bypassed
+AT91C_CKGR_PLLCOUNT EQU( 0x3F << 8 );
+-( CKGR ) PLL Counter
+AT91C_CKGR_OUT EQU( 0x3 << 14 );
+-( CKGR ) PLL Output Frequency Range
+AT91C_CKGR_OUT_0 EQU( 0x0 << 14 );
+-( CKGR ) Please refer to the PLL datasheet
+AT91C_CKGR_OUT_1 EQU( 0x1 << 14 );
+-( CKGR ) Please refer to the PLL datasheet
+AT91C_CKGR_OUT_2 EQU( 0x2 << 14 );
+-( CKGR ) Please refer to the PLL datasheet
+AT91C_CKGR_OUT_3 EQU( 0x3 << 14 );
+-( CKGR ) Please refer to the PLL datasheet
+AT91C_CKGR_MUL EQU( 0x7FF << 16 );
+-( CKGR ) PLL Multiplier
+AT91C_CKGR_USBDIV EQU( 0x3 << 28 );
+-( CKGR ) Divider
 
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Power Management Controler
-// - *****************************************************************************
-// - -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
-AT91C_PMC_PCK             EQU (0x1 <<  0) ;- (PMC) Processor Clock
-AT91C_PMC_UDP             EQU (0x1 <<  7) ;- (PMC) USB Device Port Clock
-AT91C_PMC_PCK0            EQU (0x1 <<  8) ;- (PMC) Programmable Clock Output
-AT91C_PMC_PCK1            EQU (0x1 <<  9) ;- (PMC) Programmable Clock Output
-AT91C_PMC_PCK2            EQU (0x1 << 10) ;- (PMC) Programmable Clock Output
-AT91C_PMC_PCK3            EQU (0x1 << 11) ;- (PMC) Programmable Clock Output
-// - -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
-// - -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
-// - -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
-// - -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
-// - -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
-// - -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
-AT91C_PMC_CSS             EQU (0x3 <<  0) ;- (PMC) Programmable Clock Selection
-AT91C_PMC_CSS_SLOW_CLK    EQU (0x0) ;- (PMC) Slow Clock is selected
-AT91C_PMC_CSS_MAIN_CLK    EQU (0x1) ;- (PMC) Main Clock is selected
-AT91C_PMC_CSS_PLL_CLK     EQU (0x3) ;- (PMC) Clock from PLL is selected
-AT91C_PMC_PRES            EQU (0x7 <<  2) ;- (PMC) Programmable Clock Prescaler
-AT91C_PMC_PRES_CLK        EQU (0x0 <<  2) ;- (PMC) Selected clock
-AT91C_PMC_PRES_CLK_2      EQU (0x1 <<  2) ;- (PMC) Selected clock divided by 2
-AT91C_PMC_PRES_CLK_4      EQU (0x2 <<  2) ;- (PMC) Selected clock divided by 4
-AT91C_PMC_PRES_CLK_8      EQU (0x3 <<  2) ;- (PMC) Selected clock divided by 8
-AT91C_PMC_PRES_CLK_16     EQU (0x4 <<  2) ;- (PMC) Selected clock divided by 16
-AT91C_PMC_PRES_CLK_32     EQU (0x5 <<  2) ;- (PMC) Selected clock divided by 32
-AT91C_PMC_PRES_CLK_64     EQU (0x6 <<  2) ;- (PMC) Selected clock divided by 64
-// - -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
-// - -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
-AT91C_PMC_MOSCS           EQU (0x1 <<  0) ;- (PMC) MOSC Status/Enable/Disable/Mask
-AT91C_PMC_LOCK            EQU (0x1 <<  2) ;- (PMC) PLL Status/Enable/Disable/Mask
-AT91C_PMC_MCKRDY          EQU (0x1 <<  3) ;- (PMC) MCK_RDY Status/Enable/Disable/Mask
-AT91C_PMC_PCK0RDY         EQU (0x1 <<  8) ;- (PMC) PCK0_RDY Status/Enable/Disable/Mask
-AT91C_PMC_PCK1RDY         EQU (0x1 <<  9) ;- (PMC) PCK1_RDY Status/Enable/Disable/Mask
-AT91C_PMC_PCK2RDY         EQU (0x1 << 10) ;- (PMC) PCK2_RDY Status/Enable/Disable/Mask
-AT91C_PMC_PCK3RDY         EQU (0x1 << 11) ;- (PMC) PCK3_RDY Status/Enable/Disable/Mask
-// - -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
-// - -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
-// - -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
+for USB Clocks
+AT91C_CKGR_USBDIV_0 EQU( 0x0 << 28 );
+-( CKGR ) Divider output is PLL clock output
+AT91C_CKGR_USBDIV_1 EQU( 0x1 << 28 );
+-( CKGR ) Divider output is PLL clock output divided by 2
+AT91C_CKGR_USBDIV_2 EQU( 0x2 << 28 );
+-( CKGR ) Divider output is PLL clock output divided by 4
 
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Reset Controller Interface
-// - *****************************************************************************
-// - -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
-AT91C_RSTC_PROCRST        EQU (0x1 <<  0) ;- (RSTC) Processor Reset
-AT91C_RSTC_PERRST         EQU (0x1 <<  2) ;- (RSTC) Peripheral Reset
-AT91C_RSTC_EXTRST         EQU (0x1 <<  3) ;- (RSTC) External Reset
-AT91C_RSTC_KEY            EQU (0xFF << 24) ;- (RSTC) Password
-// - -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
-AT91C_RSTC_URSTS          EQU (0x1 <<  0) ;- (RSTC) User Reset Status
-AT91C_RSTC_BODSTS         EQU (0x1 <<  1) ;- (RSTC) Brownout Detection Status
-AT91C_RSTC_RSTTYP         EQU (0x7 <<  8) ;- (RSTC) Reset Type
-AT91C_RSTC_RSTTYP_POWERUP EQU (0x0 <<  8) ;- (RSTC) Power-up Reset. VDDCORE rising.
-AT91C_RSTC_RSTTYP_WAKEUP  EQU (0x1 <<  8) ;- (RSTC) WakeUp Reset. VDDCORE rising.
-AT91C_RSTC_RSTTYP_WATCHDOG EQU (0x2 <<  8) ;- (RSTC) Watchdog Reset. Watchdog overflow occured.
-AT91C_RSTC_RSTTYP_SOFTWARE EQU (0x3 <<  8) ;- (RSTC) Software Reset. Processor reset required by the software.
-AT91C_RSTC_RSTTYP_USER    EQU (0x4 <<  8) ;- (RSTC) User Reset. NRST pin detected low.
-AT91C_RSTC_RSTTYP_BROWNOUT EQU (0x5 <<  8) ;- (RSTC) Brownout Reset occured.
-AT91C_RSTC_NRSTL          EQU (0x1 << 16) ;- (RSTC) NRST pin level
-AT91C_RSTC_SRCMP          EQU (0x1 << 17) ;- (RSTC) Software Reset Command in Progress.
-// - -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
-AT91C_RSTC_URSTEN         EQU (0x1 <<  0) ;- (RSTC) User Reset Enable
-AT91C_RSTC_URSTIEN        EQU (0x1 <<  4) ;- (RSTC) User Reset Interrupt Enable
-AT91C_RSTC_ERSTL          EQU (0xF <<  8) ;- (RSTC) User Reset Enable
-AT91C_RSTC_BODIEN         EQU (0x1 << 16) ;- (RSTC) Brownout Detection Interrupt Enable
+/* - ***************************************************************************** */
+/* -              SOFTWARE API DEFINITION  FOR Power Management Controller */
+/* - ***************************************************************************** */
+/* - -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- */
+AT91C_PMC_PCK EQU( 0x1 << 0 );
+-( PMC ) Processor Clock
+AT91C_PMC_UDP EQU( 0x1 << 7 );
+-( PMC ) USB Device Port Clock
+AT91C_PMC_PCK0 EQU( 0x1 << 8 );
+-( PMC ) Programmable Clock Output
+AT91C_PMC_PCK1 EQU( 0x1 << 9 );
+-( PMC ) Programmable Clock Output
+AT91C_PMC_PCK2 EQU( 0x1 << 10 );
+-( PMC ) Programmable Clock Output
+AT91C_PMC_PCK3 EQU( 0x1 << 11 );
+-( PMC ) Programmable Clock Output
+/* - -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- */
+/* - -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- */
+/* - -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- */
+/* - -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- */
+/* - -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- */
+/* - -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- */
+AT91C_PMC_CSS EQU( 0x3 << 0 );
+-( PMC ) Programmable Clock Selection
+AT91C_PMC_CSS_SLOW_CLK EQU( 0x0 );
+-( PMC ) Slow Clock is selected
+AT91C_PMC_CSS_MAIN_CLK EQU( 0x1 );
+-( PMC ) Main Clock is selected
+AT91C_PMC_CSS_PLL_CLK EQU( 0x3 );
+-( PMC ) Clock from PLL is selected
+AT91C_PMC_PRES EQU( 0x7 << 2 );
+-( PMC ) Programmable Clock Prescaler
+AT91C_PMC_PRES_CLK EQU( 0x0 << 2 );
+-( PMC ) Selected clock
+AT91C_PMC_PRES_CLK_2 EQU( 0x1 << 2 );
+-( PMC ) Selected clock divided by 2
+AT91C_PMC_PRES_CLK_4 EQU( 0x2 << 2 );
+-( PMC ) Selected clock divided by 4
+AT91C_PMC_PRES_CLK_8 EQU( 0x3 << 2 );
+-( PMC ) Selected clock divided by 8
+AT91C_PMC_PRES_CLK_16 EQU( 0x4 << 2 );
+-( PMC ) Selected clock divided by 16
+AT91C_PMC_PRES_CLK_32 EQU( 0x5 << 2 );
+-( PMC ) Selected clock divided by 32
+AT91C_PMC_PRES_CLK_64 EQU( 0x6 << 2 );
+-( PMC ) Selected clock divided by 64
+/* - -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- */
+/* - -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- */
+AT91C_PMC_MOSCS EQU( 0x1 << 0 );
+-( PMC ) MOSC Status / Enable / Disable / Mask
+AT91C_PMC_LOCK EQU( 0x1 << 2 );
+-( PMC ) PLL Status / Enable / Disable / Mask
+AT91C_PMC_MCKRDY EQU( 0x1 << 3 );
+-( PMC ) MCK_RDY Status / Enable / Disable / Mask
+AT91C_PMC_PCK0RDY EQU( 0x1 << 8 );
+-( PMC ) PCK0_RDY Status / Enable / Disable / Mask
+AT91C_PMC_PCK1RDY EQU( 0x1 << 9 );
+-( PMC ) PCK1_RDY Status / Enable / Disable / Mask
+AT91C_PMC_PCK2RDY EQU( 0x1 << 10 );
+-( PMC ) PCK2_RDY Status / Enable / Disable / Mask
+AT91C_PMC_PCK3RDY EQU( 0x1 << 11 );
+-( PMC ) PCK3_RDY Status / Enable / Disable / Mask
+/* - -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- */
+/* - -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- */
+/* - -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- */
 
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
-// - *****************************************************************************
-// - -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
-AT91C_RTTC_RTPRES         EQU (0xFFFF <<  0) ;- (RTTC) Real-time Timer Prescaler Value
-AT91C_RTTC_ALMIEN         EQU (0x1 << 16) ;- (RTTC) Alarm Interrupt Enable
-AT91C_RTTC_RTTINCIEN      EQU (0x1 << 17) ;- (RTTC) Real Time Timer Increment Interrupt Enable
-AT91C_RTTC_RTTRST         EQU (0x1 << 18) ;- (RTTC) Real Time Timer Restart
-// - -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
-AT91C_RTTC_ALMV           EQU (0x0 <<  0) ;- (RTTC) Alarm Value
-// - -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
-AT91C_RTTC_CRTV           EQU (0x0 <<  0) ;- (RTTC) Current Real-time Value
-// - -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
-AT91C_RTTC_ALMS           EQU (0x1 <<  0) ;- (RTTC) Real-time Alarm Status
-AT91C_RTTC_RTTINC         EQU (0x1 <<  1) ;- (RTTC) Real-time Timer Increment
+/* - ***************************************************************************** */
+/* -              SOFTWARE API DEFINITION  FOR Reset Controller Interface */
+/* - ***************************************************************************** */
+/* - -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- */
+AT91C_RSTC_PROCRST EQU( 0x1 << 0 );
+-( RSTC ) Processor Reset
+AT91C_RSTC_PERRST EQU( 0x1 << 2 );
+-( RSTC ) Peripheral Reset
+AT91C_RSTC_EXTRST EQU( 0x1 << 3 );
+-( RSTC ) External Reset
+AT91C_RSTC_KEY EQU( 0xFF << 24 );
+-( RSTC ) Password
+/* - -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- */
+AT91C_RSTC_URSTS EQU( 0x1 << 0 );
+-( RSTC ) User Reset Status
+AT91C_RSTC_BODSTS EQU( 0x1 << 1 );
+-( RSTC ) Brownout Detection Status
+AT91C_RSTC_RSTTYP EQU( 0x7 << 8 );
+-( RSTC ) Reset Type
+AT91C_RSTC_RSTTYP_POWERUP EQU( 0x0 << 8 );
+-( RSTC ) Power - up Reset.VDDCORE rising.
+   AT91C_RSTC_RSTTYP_WAKEUP EQU( 0x1 << 8 );
+-( RSTC ) WakeUp Reset.VDDCORE rising.
+   AT91C_RSTC_RSTTYP_WATCHDOG EQU( 0x2 << 8 );
+-( RSTC ) Watchdog Reset.Watchdog overflow occurred.
+   AT91C_RSTC_RSTTYP_SOFTWARE EQU( 0x3 << 8 );
+-( RSTC ) Software Reset.Processor reset required by the software.
+   AT91C_RSTC_RSTTYP_USER EQU( 0x4 << 8 );
+-( RSTC ) User Reset.NRST pin detected low.
+   AT91C_RSTC_RSTTYP_BROWNOUT EQU( 0x5 << 8 );
+-( RSTC ) Brownout Reset occurred.
+   AT91C_RSTC_NRSTL EQU( 0x1 << 16 );
+-( RSTC ) NRST pin level
+AT91C_RSTC_SRCMP EQU( 0x1 << 17 );
+-( RSTC ) Software Reset Command in Progress.
+/* - -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- */
+   AT91C_RSTC_URSTEN EQU( 0x1 << 0 );
+-( RSTC ) User Reset Enable
+AT91C_RSTC_URSTIEN EQU( 0x1 << 4 );
+-( RSTC ) User Reset Interrupt Enable
+AT91C_RSTC_ERSTL EQU( 0xF << 8 );
+-( RSTC ) User Reset Enable
+AT91C_RSTC_BODIEN EQU( 0x1 << 16 );
+-( RSTC ) Brownout Detection Interrupt Enable
 
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
-// - *****************************************************************************
-// - -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
-AT91C_PITC_PIV            EQU (0xFFFFF <<  0) ;- (PITC) Periodic Interval Value
-AT91C_PITC_PITEN          EQU (0x1 << 24) ;- (PITC) Periodic Interval Timer Enabled
-AT91C_PITC_PITIEN         EQU (0x1 << 25) ;- (PITC) Periodic Interval Timer Interrupt Enable
-// - -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
-AT91C_PITC_PITS           EQU (0x1 <<  0) ;- (PITC) Periodic Interval Timer Status
-// - -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
-AT91C_PITC_CPIV           EQU (0xFFFFF <<  0) ;- (PITC) Current Periodic Interval Value
-AT91C_PITC_PICNT          EQU (0xFFF << 20) ;- (PITC) Periodic Interval Counter
-// - -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
+/* - ***************************************************************************** */
+/* -              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface */
+/* - ***************************************************************************** */
+/* - -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- */
+AT91C_RTTC_RTPRES EQU( 0xFFFF << 0 );
+-( RTTC ) Real - time Timer Prescaler Value
+AT91C_RTTC_ALMIEN EQU( 0x1 << 16 );
+-( RTTC ) Alarm Interrupt Enable
+AT91C_RTTC_RTTINCIEN EQU( 0x1 << 17 );
+-( RTTC ) Real Time Timer Increment Interrupt Enable
+AT91C_RTTC_RTTRST EQU( 0x1 << 18 );
+-( RTTC ) Real Time Timer Restart
+/* - -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- */
+AT91C_RTTC_ALMV EQU( 0x0 << 0 );
+-( RTTC ) Alarm Value
+/* - -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- */
+AT91C_RTTC_CRTV EQU( 0x0 << 0 );
+-( RTTC ) Current Real - time Value
+/* - -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- */
+AT91C_RTTC_ALMS EQU( 0x1 << 0 );
+-( RTTC ) Real - time Alarm Status
+AT91C_RTTC_RTTINC EQU( 0x1 << 1 );
+-( RTTC ) Real - time Timer Increment
 
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
-// - *****************************************************************************
-// - -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
-AT91C_WDTC_WDRSTT         EQU (0x1 <<  0) ;- (WDTC) Watchdog Restart
-AT91C_WDTC_KEY            EQU (0xFF << 24) ;- (WDTC) Watchdog KEY Password
-// - -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
-AT91C_WDTC_WDV            EQU (0xFFF <<  0) ;- (WDTC) Watchdog Timer Restart
-AT91C_WDTC_WDFIEN         EQU (0x1 << 12) ;- (WDTC) Watchdog Fault Interrupt Enable
-AT91C_WDTC_WDRSTEN        EQU (0x1 << 13) ;- (WDTC) Watchdog Reset Enable
-AT91C_WDTC_WDRPROC        EQU (0x1 << 14) ;- (WDTC) Watchdog Timer Restart
-AT91C_WDTC_WDDIS          EQU (0x1 << 15) ;- (WDTC) Watchdog Disable
-AT91C_WDTC_WDD            EQU (0xFFF << 16) ;- (WDTC) Watchdog Delta Value
-AT91C_WDTC_WDDBGHLT       EQU (0x1 << 28) ;- (WDTC) Watchdog Debug Halt
-AT91C_WDTC_WDIDLEHLT      EQU (0x1 << 29) ;- (WDTC) Watchdog Idle Halt
-// - -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
-AT91C_WDTC_WDUNF          EQU (0x1 <<  0) ;- (WDTC) Watchdog Underflow
-AT91C_WDTC_WDERR          EQU (0x1 <<  1) ;- (WDTC) Watchdog Error
+/* - ***************************************************************************** */
+/* -              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface */
+/* - ***************************************************************************** */
+/* - -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- */
+AT91C_PITC_PIV EQU( 0xFFFFF << 0 );
+-( PITC ) Periodic Interval Value
+AT91C_PITC_PITEN EQU( 0x1 << 24 );
+-( PITC ) Periodic Interval Timer Enabled
+AT91C_PITC_PITIEN EQU( 0x1 << 25 );
+-( PITC ) Periodic Interval Timer Interrupt Enable
+/* - -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- */
+AT91C_PITC_PITS EQU( 0x1 << 0 );
+-( PITC ) Periodic Interval Timer Status
+/* - -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- */
+AT91C_PITC_CPIV EQU( 0xFFFFF << 0 );
+-( PITC ) Current Periodic Interval Value
+AT91C_PITC_PICNT EQU( 0xFFF << 20 );
+-( PITC ) Periodic Interval Counter
+/* - -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- */
 
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Voltage Regulator Mode Controller Interface
-// - *****************************************************************************
-// - -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register --------
-AT91C_VREG_PSTDBY         EQU (0x1 <<  0) ;- (VREG) Voltage Regulator Power Standby Mode
+/* - ***************************************************************************** */
+/* -              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface */
+/* - ***************************************************************************** */
+/* - -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- */
+AT91C_WDTC_WDRSTT EQU( 0x1 << 0 );
+-( WDTC ) Watchdog Restart
+AT91C_WDTC_KEY EQU( 0xFF << 24 );
+-( WDTC ) Watchdog KEY Password
+/* - -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- */
+AT91C_WDTC_WDV EQU( 0xFFF << 0 );
+-( WDTC ) Watchdog Timer Restart
+AT91C_WDTC_WDFIEN EQU( 0x1 << 12 );
+-( WDTC ) Watchdog Fault Interrupt Enable
+AT91C_WDTC_WDRSTEN EQU( 0x1 << 13 );
+-( WDTC ) Watchdog Reset Enable
+AT91C_WDTC_WDRPROC EQU( 0x1 << 14 );
+-( WDTC ) Watchdog Timer Restart
+AT91C_WDTC_WDDIS EQU( 0x1 << 15 );
+-( WDTC ) Watchdog Disable
+AT91C_WDTC_WDD EQU( 0xFFF << 16 );
+-( WDTC ) Watchdog Delta Value
+AT91C_WDTC_WDDBGHLT EQU( 0x1 << 28 );
+-( WDTC ) Watchdog Debug Halt
+AT91C_WDTC_WDIDLEHLT EQU( 0x1 << 29 );
+-( WDTC ) Watchdog Idle Halt
+/* - -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- */
+AT91C_WDTC_WDUNF EQU( 0x1 << 0 );
+-( WDTC ) Watchdog Underflow
+AT91C_WDTC_WDERR EQU( 0x1 << 1 );
+-( WDTC ) Watchdog Error
 
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Memory Controller Interface
-// - *****************************************************************************
-// - -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
-AT91C_MC_RCB              EQU (0x1 <<  0) ;- (MC) Remap Command Bit
-// - -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
-AT91C_MC_UNDADD           EQU (0x1 <<  0) ;- (MC) Undefined Addess Abort Status
-AT91C_MC_MISADD           EQU (0x1 <<  1) ;- (MC) Misaligned Addess Abort Status
-AT91C_MC_ABTSZ            EQU (0x3 <<  8) ;- (MC) Abort Size Status
-AT91C_MC_ABTSZ_BYTE       EQU (0x0 <<  8) ;- (MC) Byte
-AT91C_MC_ABTSZ_HWORD      EQU (0x1 <<  8) ;- (MC) Half-word
-AT91C_MC_ABTSZ_WORD       EQU (0x2 <<  8) ;- (MC) Word
-AT91C_MC_ABTTYP           EQU (0x3 << 10) ;- (MC) Abort Type Status
-AT91C_MC_ABTTYP_DATAR     EQU (0x0 << 10) ;- (MC) Data Read
-AT91C_MC_ABTTYP_DATAW     EQU (0x1 << 10) ;- (MC) Data Write
-AT91C_MC_ABTTYP_FETCH     EQU (0x2 << 10) ;- (MC) Code Fetch
-AT91C_MC_MST0             EQU (0x1 << 16) ;- (MC) Master 0 Abort Source
-AT91C_MC_MST1             EQU (0x1 << 17) ;- (MC) Master 1 Abort Source
-AT91C_MC_SVMST0           EQU (0x1 << 24) ;- (MC) Saved Master 0 Abort Source
-AT91C_MC_SVMST1           EQU (0x1 << 25) ;- (MC) Saved Master 1 Abort Source
-// - -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
-AT91C_MC_FRDY             EQU (0x1 <<  0) ;- (MC) Flash Ready
-AT91C_MC_LOCKE            EQU (0x1 <<  2) ;- (MC) Lock Error
-AT91C_MC_PROGE            EQU (0x1 <<  3) ;- (MC) Programming Error
-AT91C_MC_NEBP             EQU (0x1 <<  7) ;- (MC) No Erase Before Programming
-AT91C_MC_FWS              EQU (0x3 <<  8) ;- (MC) Flash Wait State
-AT91C_MC_FWS_0FWS         EQU (0x0 <<  8) ;- (MC) 1 cycle for Read, 2 for Write operations
-AT91C_MC_FWS_1FWS         EQU (0x1 <<  8) ;- (MC) 2 cycles for Read, 3 for Write operations
-AT91C_MC_FWS_2FWS         EQU (0x2 <<  8) ;- (MC) 3 cycles for Read, 4 for Write operations
-AT91C_MC_FWS_3FWS         EQU (0x3 <<  8) ;- (MC) 4 cycles for Read, 4 for Write operations
-AT91C_MC_FMCN             EQU (0xFF << 16) ;- (MC) Flash Microsecond Cycle Number
-// - -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
-AT91C_MC_FCMD             EQU (0xF <<  0) ;- (MC) Flash Command
-AT91C_MC_FCMD_START_PROG  EQU (0x1) ;- (MC) Starts the programming of th epage specified by PAGEN.
-AT91C_MC_FCMD_LOCK        EQU (0x2) ;- (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-AT91C_MC_FCMD_PROG_AND_LOCK EQU (0x3) ;- (MC) The lock sequence automatically happens after the programming sequence is completed.
-AT91C_MC_FCMD_UNLOCK      EQU (0x4) ;- (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-AT91C_MC_FCMD_ERASE_ALL   EQU (0x8) ;- (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
-AT91C_MC_FCMD_SET_GP_NVM  EQU (0xB) ;- (MC) Set General Purpose NVM bits.
-AT91C_MC_FCMD_CLR_GP_NVM  EQU (0xD) ;- (MC) Clear General Purpose NVM bits.
-AT91C_MC_FCMD_SET_SECURITY EQU (0xF) ;- (MC) Set Security Bit.
-AT91C_MC_PAGEN            EQU (0x3FF <<  8) ;- (MC) Page Number
-AT91C_MC_KEY              EQU (0xFF << 24) ;- (MC) Writing Protect Key
-// - -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register --------
-AT91C_MC_SECURITY         EQU (0x1 <<  4) ;- (MC) Security Bit Status
-AT91C_MC_GPNVM0           EQU (0x1 <<  8) ;- (MC) Sector 0 Lock Status
-AT91C_MC_GPNVM1           EQU (0x1 <<  9) ;- (MC) Sector 1 Lock Status
-AT91C_MC_GPNVM2           EQU (0x1 << 10) ;- (MC) Sector 2 Lock Status
-AT91C_MC_GPNVM3           EQU (0x1 << 11) ;- (MC) Sector 3 Lock Status
-AT91C_MC_GPNVM4           EQU (0x1 << 12) ;- (MC) Sector 4 Lock Status
-AT91C_MC_GPNVM5           EQU (0x1 << 13) ;- (MC) Sector 5 Lock Status
-AT91C_MC_GPNVM6           EQU (0x1 << 14) ;- (MC) Sector 6 Lock Status
-AT91C_MC_GPNVM7           EQU (0x1 << 15) ;- (MC) Sector 7 Lock Status
-AT91C_MC_LOCKS0           EQU (0x1 << 16) ;- (MC) Sector 0 Lock Status
-AT91C_MC_LOCKS1           EQU (0x1 << 17) ;- (MC) Sector 1 Lock Status
-AT91C_MC_LOCKS2           EQU (0x1 << 18) ;- (MC) Sector 2 Lock Status
-AT91C_MC_LOCKS3           EQU (0x1 << 19) ;- (MC) Sector 3 Lock Status
-AT91C_MC_LOCKS4           EQU (0x1 << 20) ;- (MC) Sector 4 Lock Status
-AT91C_MC_LOCKS5           EQU (0x1 << 21) ;- (MC) Sector 5 Lock Status
-AT91C_MC_LOCKS6           EQU (0x1 << 22) ;- (MC) Sector 6 Lock Status
-AT91C_MC_LOCKS7           EQU (0x1 << 23) ;- (MC) Sector 7 Lock Status
-AT91C_MC_LOCKS8           EQU (0x1 << 24) ;- (MC) Sector 8 Lock Status
-AT91C_MC_LOCKS9           EQU (0x1 << 25) ;- (MC) Sector 9 Lock Status
-AT91C_MC_LOCKS10          EQU (0x1 << 26) ;- (MC) Sector 10 Lock Status
-AT91C_MC_LOCKS11          EQU (0x1 << 27) ;- (MC) Sector 11 Lock Status
-AT91C_MC_LOCKS12          EQU (0x1 << 28) ;- (MC) Sector 12 Lock Status
-AT91C_MC_LOCKS13          EQU (0x1 << 29) ;- (MC) Sector 13 Lock Status
-AT91C_MC_LOCKS14          EQU (0x1 << 30) ;- (MC) Sector 14 Lock Status
-AT91C_MC_LOCKS15          EQU (0x1 << 31) ;- (MC) Sector 15 Lock Status
+/* - ***************************************************************************** */
+/* -              SOFTWARE API DEFINITION  FOR Voltage Regulator Mode Controller Interface */
+/* - ***************************************************************************** */
+/* - -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- */
+AT91C_VREG_PSTDBY EQU( 0x1 << 0 );
+-( VREG ) Voltage Regulator Power Standby Mode
 
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
-// - *****************************************************************************
-// - -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
-AT91C_SPI_SPIEN           EQU (0x1 <<  0) ;- (SPI) SPI Enable
-AT91C_SPI_SPIDIS          EQU (0x1 <<  1) ;- (SPI) SPI Disable
-AT91C_SPI_SWRST           EQU (0x1 <<  7) ;- (SPI) SPI Software reset
-AT91C_SPI_LASTXFER        EQU (0x1 << 24) ;- (SPI) SPI Last Transfer
-// - -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
-AT91C_SPI_MSTR            EQU (0x1 <<  0) ;- (SPI) Master/Slave Mode
-AT91C_SPI_PS              EQU (0x1 <<  1) ;- (SPI) Peripheral Select
-AT91C_SPI_PS_FIXED        EQU (0x0 <<  1) ;- (SPI) Fixed Peripheral Select
-AT91C_SPI_PS_VARIABLE     EQU (0x1 <<  1) ;- (SPI) Variable Peripheral Select
-AT91C_SPI_PCSDEC          EQU (0x1 <<  2) ;- (SPI) Chip Select Decode
-AT91C_SPI_FDIV            EQU (0x1 <<  3) ;- (SPI) Clock Selection
-AT91C_SPI_MODFDIS         EQU (0x1 <<  4) ;- (SPI) Mode Fault Detection
-AT91C_SPI_LLB             EQU (0x1 <<  7) ;- (SPI) Clock Selection
-AT91C_SPI_PCS             EQU (0xF << 16) ;- (SPI) Peripheral Chip Select
-AT91C_SPI_DLYBCS          EQU (0xFF << 24) ;- (SPI) Delay Between Chip Selects
-// - -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
-AT91C_SPI_RD              EQU (0xFFFF <<  0) ;- (SPI) Receive Data
-AT91C_SPI_RPCS            EQU (0xF << 16) ;- (SPI) Peripheral Chip Select Status
-// - -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
-AT91C_SPI_TD              EQU (0xFFFF <<  0) ;- (SPI) Transmit Data
-AT91C_SPI_TPCS            EQU (0xF << 16) ;- (SPI) Peripheral Chip Select Status
-// - -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
-AT91C_SPI_RDRF            EQU (0x1 <<  0) ;- (SPI) Receive Data Register Full
-AT91C_SPI_TDRE            EQU (0x1 <<  1) ;- (SPI) Transmit Data Register Empty
-AT91C_SPI_MODF            EQU (0x1 <<  2) ;- (SPI) Mode Fault Error
-AT91C_SPI_OVRES           EQU (0x1 <<  3) ;- (SPI) Overrun Error Status
-AT91C_SPI_ENDRX           EQU (0x1 <<  4) ;- (SPI) End of Receiver Transfer
-AT91C_SPI_ENDTX           EQU (0x1 <<  5) ;- (SPI) End of Receiver Transfer
-AT91C_SPI_RXBUFF          EQU (0x1 <<  6) ;- (SPI) RXBUFF Interrupt
-AT91C_SPI_TXBUFE          EQU (0x1 <<  7) ;- (SPI) TXBUFE Interrupt
-AT91C_SPI_NSSR            EQU (0x1 <<  8) ;- (SPI) NSSR Interrupt
-AT91C_SPI_TXEMPTY         EQU (0x1 <<  9) ;- (SPI) TXEMPTY Interrupt
-AT91C_SPI_SPIENS          EQU (0x1 << 16) ;- (SPI) Enable Status
-// - -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
-// - -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
-// - -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
-// - -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
-AT91C_SPI_CPOL            EQU (0x1 <<  0) ;- (SPI) Clock Polarity
-AT91C_SPI_NCPHA           EQU (0x1 <<  1) ;- (SPI) Clock Phase
-AT91C_SPI_CSAAT           EQU (0x1 <<  3) ;- (SPI) Chip Select Active After Transfer
-AT91C_SPI_BITS            EQU (0xF <<  4) ;- (SPI) Bits Per Transfer
-AT91C_SPI_BITS_8          EQU (0x0 <<  4) ;- (SPI) 8 Bits Per transfer
-AT91C_SPI_BITS_9          EQU (0x1 <<  4) ;- (SPI) 9 Bits Per transfer
-AT91C_SPI_BITS_10         EQU (0x2 <<  4) ;- (SPI) 10 Bits Per transfer
-AT91C_SPI_BITS_11         EQU (0x3 <<  4) ;- (SPI) 11 Bits Per transfer
-AT91C_SPI_BITS_12         EQU (0x4 <<  4) ;- (SPI) 12 Bits Per transfer
-AT91C_SPI_BITS_13         EQU (0x5 <<  4) ;- (SPI) 13 Bits Per transfer
-AT91C_SPI_BITS_14         EQU (0x6 <<  4) ;- (SPI) 14 Bits Per transfer
-AT91C_SPI_BITS_15         EQU (0x7 <<  4) ;- (SPI) 15 Bits Per transfer
-AT91C_SPI_BITS_16         EQU (0x8 <<  4) ;- (SPI) 16 Bits Per transfer
-AT91C_SPI_SCBR            EQU (0xFF <<  8) ;- (SPI) Serial Clock Baud Rate
-AT91C_SPI_DLYBS           EQU (0xFF << 16) ;- (SPI) Delay Before SPCK
-AT91C_SPI_DLYBCT          EQU (0xFF << 24) ;- (SPI) Delay Between Consecutive Transfers
+/* - ***************************************************************************** */
+/* -              SOFTWARE API DEFINITION  FOR Memory Controller Interface */
+/* - ***************************************************************************** */
+/* - -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */
+AT91C_MC_RCB EQU( 0x1 << 0 );
+-( MC ) Remap Command Bit
+/* - -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */
+AT91C_MC_UNDADD EQU( 0x1 << 0 );
+-( MC ) Undefined Addess Abort Status
+AT91C_MC_MISADD EQU( 0x1 << 1 );
+-( MC ) Misaligned Addess Abort Status
+AT91C_MC_ABTSZ EQU( 0x3 << 8 );
+-( MC ) Abort Size Status
+AT91C_MC_ABTSZ_BYTE EQU( 0x0 << 8 );
+-( MC ) Byte
+AT91C_MC_ABTSZ_HWORD EQU( 0x1 << 8 );
+-( MC ) Half - word
+AT91C_MC_ABTSZ_WORD EQU( 0x2 << 8 );
+-( MC ) Word
+AT91C_MC_ABTTYP EQU( 0x3 << 10 );
+-( MC ) Abort Type Status
+AT91C_MC_ABTTYP_DATAR EQU( 0x0 << 10 );
+-( MC ) Data Read
+AT91C_MC_ABTTYP_DATAW EQU( 0x1 << 10 );
+-( MC ) Data Write
+AT91C_MC_ABTTYP_FETCH EQU( 0x2 << 10 );
+-( MC ) Code Fetch
+AT91C_MC_MST0 EQU( 0x1 << 16 );
+-( MC ) Master 0 Abort Source
+AT91C_MC_MST1 EQU( 0x1 << 17 );
+-( MC ) Master 1 Abort Source
+AT91C_MC_SVMST0 EQU( 0x1 << 24 );
+-( MC ) Saved Master 0 Abort Source
+AT91C_MC_SVMST1 EQU( 0x1 << 25 );
+-( MC ) Saved Master 1 Abort Source
+/* - -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- */
+AT91C_MC_FRDY EQU( 0x1 << 0 );
+-( MC ) Flash Ready
+AT91C_MC_LOCKE EQU( 0x1 << 2 );
+-( MC ) Lock Error
+AT91C_MC_PROGE EQU( 0x1 << 3 );
+-( MC ) Programming Error
+AT91C_MC_NEBP EQU( 0x1 << 7 );
+-( MC ) No Erase Before Programming
+AT91C_MC_FWS EQU( 0x3 << 8 );
+-( MC ) Flash Wait State
+AT91C_MC_FWS_0FWS EQU( 0x0 << 8 );
+-( MC ) 1 cycle
 
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Usart
-// - *****************************************************************************
-// - -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
-AT91C_US_STTBRK           EQU (0x1 <<  9) ;- (USART) Start Break
-AT91C_US_STPBRK           EQU (0x1 << 10) ;- (USART) Stop Break
-AT91C_US_STTTO            EQU (0x1 << 11) ;- (USART) Start Time-out
-AT91C_US_SENDA            EQU (0x1 << 12) ;- (USART) Send Address
-AT91C_US_RSTIT            EQU (0x1 << 13) ;- (USART) Reset Iterations
-AT91C_US_RSTNACK          EQU (0x1 << 14) ;- (USART) Reset Non Acknowledge
-AT91C_US_RETTO            EQU (0x1 << 15) ;- (USART) Rearm Time-out
-AT91C_US_DTREN            EQU (0x1 << 16) ;- (USART) Data Terminal ready Enable
-AT91C_US_DTRDIS           EQU (0x1 << 17) ;- (USART) Data Terminal ready Disable
-AT91C_US_RTSEN            EQU (0x1 << 18) ;- (USART) Request to Send enable
-AT91C_US_RTSDIS           EQU (0x1 << 19) ;- (USART) Request to Send Disable
-// - -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
-AT91C_US_USMODE           EQU (0xF <<  0) ;- (USART) Usart mode
-AT91C_US_USMODE_NORMAL    EQU (0x0) ;- (USART) Normal
-AT91C_US_USMODE_RS485     EQU (0x1) ;- (USART) RS485
-AT91C_US_USMODE_HWHSH     EQU (0x2) ;- (USART) Hardware Handshaking
-AT91C_US_USMODE_MODEM     EQU (0x3) ;- (USART) Modem
-AT91C_US_USMODE_ISO7816_0 EQU (0x4) ;- (USART) ISO7816 protocol: T = 0
-AT91C_US_USMODE_ISO7816_1 EQU (0x6) ;- (USART) ISO7816 protocol: T = 1
-AT91C_US_USMODE_IRDA      EQU (0x8) ;- (USART) IrDA
-AT91C_US_USMODE_SWHSH     EQU (0xC) ;- (USART) Software Handshaking
-AT91C_US_CLKS             EQU (0x3 <<  4) ;- (USART) Clock Selection (Baud Rate generator Input Clock
-AT91C_US_CLKS_CLOCK       EQU (0x0 <<  4) ;- (USART) Clock
-AT91C_US_CLKS_FDIV1       EQU (0x1 <<  4) ;- (USART) fdiv1
-AT91C_US_CLKS_SLOW        EQU (0x2 <<  4) ;- (USART) slow_clock (ARM)
-AT91C_US_CLKS_EXT         EQU (0x3 <<  4) ;- (USART) External (SCK)
-AT91C_US_CHRL             EQU (0x3 <<  6) ;- (USART) Clock Selection (Baud Rate generator Input Clock
-AT91C_US_CHRL_5_BITS      EQU (0x0 <<  6) ;- (USART) Character Length: 5 bits
-AT91C_US_CHRL_6_BITS      EQU (0x1 <<  6) ;- (USART) Character Length: 6 bits
-AT91C_US_CHRL_7_BITS      EQU (0x2 <<  6) ;- (USART) Character Length: 7 bits
-AT91C_US_CHRL_8_BITS      EQU (0x3 <<  6) ;- (USART) Character Length: 8 bits
-AT91C_US_SYNC             EQU (0x1 <<  8) ;- (USART) Synchronous Mode Select
-AT91C_US_NBSTOP           EQU (0x3 << 12) ;- (USART) Number of Stop bits
-AT91C_US_NBSTOP_1_BIT     EQU (0x0 << 12) ;- (USART) 1 stop bit
-AT91C_US_NBSTOP_15_BIT    EQU (0x1 << 12) ;- (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
-AT91C_US_NBSTOP_2_BIT     EQU (0x2 << 12) ;- (USART) 2 stop bits
-AT91C_US_MSBF             EQU (0x1 << 16) ;- (USART) Bit Order
-AT91C_US_MODE9            EQU (0x1 << 17) ;- (USART) 9-bit Character length
-AT91C_US_CKLO             EQU (0x1 << 18) ;- (USART) Clock Output Select
-AT91C_US_OVER             EQU (0x1 << 19) ;- (USART) Over Sampling Mode
-AT91C_US_INACK            EQU (0x1 << 20) ;- (USART) Inhibit Non Acknowledge
-AT91C_US_DSNACK           EQU (0x1 << 21) ;- (USART) Disable Successive NACK
-AT91C_US_MAX_ITER         EQU (0x1 << 24) ;- (USART) Number of Repetitions
-AT91C_US_FILTER           EQU (0x1 << 28) ;- (USART) Receive Line Filter
-// - -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
-AT91C_US_RXBRK            EQU (0x1 <<  2) ;- (USART) Break Received/End of Break
-AT91C_US_TIMEOUT          EQU (0x1 <<  8) ;- (USART) Receiver Time-out
-AT91C_US_ITERATION        EQU (0x1 << 10) ;- (USART) Max number of Repetitions Reached
-AT91C_US_NACK             EQU (0x1 << 13) ;- (USART) Non Acknowledge
-AT91C_US_RIIC             EQU (0x1 << 16) ;- (USART) Ring INdicator Input Change Flag
-AT91C_US_DSRIC            EQU (0x1 << 17) ;- (USART) Data Set Ready Input Change Flag
-AT91C_US_DCDIC            EQU (0x1 << 18) ;- (USART) Data Carrier Flag
-AT91C_US_CTSIC            EQU (0x1 << 19) ;- (USART) Clear To Send Input Change Flag
-// - -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
-// - -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
-// - -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
-AT91C_US_RI               EQU (0x1 << 20) ;- (USART) Image of RI Input
-AT91C_US_DSR              EQU (0x1 << 21) ;- (USART) Image of DSR Input
-AT91C_US_DCD              EQU (0x1 << 22) ;- (USART) Image of DCD Input
-AT91C_US_CTS              EQU (0x1 << 23) ;- (USART) Image of CTS Input
+for Read, 2
 
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
-// - *****************************************************************************
-// - -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
-AT91C_SSC_RXEN            EQU (0x1 <<  0) ;- (SSC) Receive Enable
-AT91C_SSC_RXDIS           EQU (0x1 <<  1) ;- (SSC) Receive Disable
-AT91C_SSC_TXEN            EQU (0x1 <<  8) ;- (SSC) Transmit Enable
-AT91C_SSC_TXDIS           EQU (0x1 <<  9) ;- (SSC) Transmit Disable
-AT91C_SSC_SWRST           EQU (0x1 << 15) ;- (SSC) Software Reset
-// - -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
-AT91C_SSC_CKS             EQU (0x3 <<  0) ;- (SSC) Receive/Transmit Clock Selection
-AT91C_SSC_CKS_DIV         EQU (0x0) ;- (SSC) Divided Clock
-AT91C_SSC_CKS_TK          EQU (0x1) ;- (SSC) TK Clock signal
-AT91C_SSC_CKS_RK          EQU (0x2) ;- (SSC) RK pin
-AT91C_SSC_CKO             EQU (0x7 <<  2) ;- (SSC) Receive/Transmit Clock Output Mode Selection
-AT91C_SSC_CKO_NONE        EQU (0x0 <<  2) ;- (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
-AT91C_SSC_CKO_CONTINOUS   EQU (0x1 <<  2) ;- (SSC) Continuous Receive/Transmit Clock RK pin: Output
-AT91C_SSC_CKO_DATA_TX     EQU (0x2 <<  2) ;- (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
-AT91C_SSC_CKI             EQU (0x1 <<  5) ;- (SSC) Receive/Transmit Clock Inversion
-AT91C_SSC_START           EQU (0xF <<  8) ;- (SSC) Receive/Transmit Start Selection
-AT91C_SSC_START_CONTINOUS EQU (0x0 <<  8) ;- (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
-AT91C_SSC_START_TX        EQU (0x1 <<  8) ;- (SSC) Transmit/Receive start
-AT91C_SSC_START_LOW_RF    EQU (0x2 <<  8) ;- (SSC) Detection of a low level on RF input
-AT91C_SSC_START_HIGH_RF   EQU (0x3 <<  8) ;- (SSC) Detection of a high level on RF input
-AT91C_SSC_START_FALL_RF   EQU (0x4 <<  8) ;- (SSC) Detection of a falling edge on RF input
-AT91C_SSC_START_RISE_RF   EQU (0x5 <<  8) ;- (SSC) Detection of a rising edge on RF input
-AT91C_SSC_START_LEVEL_RF  EQU (0x6 <<  8) ;- (SSC) Detection of any level change on RF input
-AT91C_SSC_START_EDGE_RF   EQU (0x7 <<  8) ;- (SSC) Detection of any edge on RF input
-AT91C_SSC_START_0         EQU (0x8 <<  8) ;- (SSC) Compare 0
-AT91C_SSC_STTDLY          EQU (0xFF << 16) ;- (SSC) Receive/Transmit Start Delay
-AT91C_SSC_PERIOD          EQU (0xFF << 24) ;- (SSC) Receive/Transmit Period Divider Selection
-// - -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
-AT91C_SSC_DATLEN          EQU (0x1F <<  0) ;- (SSC) Data Length
-AT91C_SSC_LOOP            EQU (0x1 <<  5) ;- (SSC) Loop Mode
-AT91C_SSC_MSBF            EQU (0x1 <<  7) ;- (SSC) Most Significant Bit First
-AT91C_SSC_DATNB           EQU (0xF <<  8) ;- (SSC) Data Number per Frame
-AT91C_SSC_FSLEN           EQU (0xF << 16) ;- (SSC) Receive/Transmit Frame Sync length
-AT91C_SSC_FSOS            EQU (0x7 << 20) ;- (SSC) Receive/Transmit Frame Sync Output Selection
-AT91C_SSC_FSOS_NONE       EQU (0x0 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
-AT91C_SSC_FSOS_NEGATIVE   EQU (0x1 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
-AT91C_SSC_FSOS_POSITIVE   EQU (0x2 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
-AT91C_SSC_FSOS_LOW        EQU (0x3 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
-AT91C_SSC_FSOS_HIGH       EQU (0x4 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
-AT91C_SSC_FSOS_TOGGLE     EQU (0x5 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
-AT91C_SSC_FSEDGE          EQU (0x1 << 24) ;- (SSC) Frame Sync Edge Detection
-// - -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
-// - -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
-AT91C_SSC_DATDEF          EQU (0x1 <<  5) ;- (SSC) Data Default Value
-AT91C_SSC_FSDEN           EQU (0x1 << 23) ;- (SSC) Frame Sync Data Enable
-// - -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
-AT91C_SSC_TXRDY           EQU (0x1 <<  0) ;- (SSC) Transmit Ready
-AT91C_SSC_TXEMPTY         EQU (0x1 <<  1) ;- (SSC) Transmit Empty
-AT91C_SSC_ENDTX           EQU (0x1 <<  2) ;- (SSC) End Of Transmission
-AT91C_SSC_TXBUFE          EQU (0x1 <<  3) ;- (SSC) Transmit Buffer Empty
-AT91C_SSC_RXRDY           EQU (0x1 <<  4) ;- (SSC) Receive Ready
-AT91C_SSC_OVRUN           EQU (0x1 <<  5) ;- (SSC) Receive Overrun
-AT91C_SSC_ENDRX           EQU (0x1 <<  6) ;- (SSC) End of Reception
-AT91C_SSC_RXBUFF          EQU (0x1 <<  7) ;- (SSC) Receive Buffer Full
-AT91C_SSC_TXSYN           EQU (0x1 << 10) ;- (SSC) Transmit Sync
-AT91C_SSC_RXSYN           EQU (0x1 << 11) ;- (SSC) Receive Sync
-AT91C_SSC_TXENA           EQU (0x1 << 16) ;- (SSC) Transmit Enable
-AT91C_SSC_RXENA           EQU (0x1 << 17) ;- (SSC) Receive Enable
-// - -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
-// - -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
-// - -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
+for Write operations
+AT91C_MC_FWS_1FWS EQU( 0x1 << 8 );
+-( MC ) 2 cycles
 
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Two-wire Interface
-// - *****************************************************************************
-// - -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
-AT91C_TWI_START           EQU (0x1 <<  0) ;- (TWI) Send a START Condition
-AT91C_TWI_STOP            EQU (0x1 <<  1) ;- (TWI) Send a STOP Condition
-AT91C_TWI_MSEN            EQU (0x1 <<  2) ;- (TWI) TWI Master Transfer Enabled
-AT91C_TWI_MSDIS           EQU (0x1 <<  3) ;- (TWI) TWI Master Transfer Disabled
-AT91C_TWI_SWRST           EQU (0x1 <<  7) ;- (TWI) Software Reset
-// - -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
-AT91C_TWI_IADRSZ          EQU (0x3 <<  8) ;- (TWI) Internal Device Address Size
-AT91C_TWI_IADRSZ_NO       EQU (0x0 <<  8) ;- (TWI) No internal device address
-AT91C_TWI_IADRSZ_1_BYTE   EQU (0x1 <<  8) ;- (TWI) One-byte internal device address
-AT91C_TWI_IADRSZ_2_BYTE   EQU (0x2 <<  8) ;- (TWI) Two-byte internal device address
-AT91C_TWI_IADRSZ_3_BYTE   EQU (0x3 <<  8) ;- (TWI) Three-byte internal device address
-AT91C_TWI_MREAD           EQU (0x1 << 12) ;- (TWI) Master Read Direction
-AT91C_TWI_DADR            EQU (0x7F << 16) ;- (TWI) Device Address
-// - -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
-AT91C_TWI_CLDIV           EQU (0xFF <<  0) ;- (TWI) Clock Low Divider
-AT91C_TWI_CHDIV           EQU (0xFF <<  8) ;- (TWI) Clock High Divider
-AT91C_TWI_CKDIV           EQU (0x7 << 16) ;- (TWI) Clock Divider
-// - -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
-AT91C_TWI_TXCOMP          EQU (0x1 <<  0) ;- (TWI) Transmission Completed
-AT91C_TWI_RXRDY           EQU (0x1 <<  1) ;- (TWI) Receive holding register ReaDY
-AT91C_TWI_TXRDY           EQU (0x1 <<  2) ;- (TWI) Transmit holding register ReaDY
-AT91C_TWI_OVRE            EQU (0x1 <<  6) ;- (TWI) Overrun Error
-AT91C_TWI_UNRE            EQU (0x1 <<  7) ;- (TWI) Underrun Error
-AT91C_TWI_NACK            EQU (0x1 <<  8) ;- (TWI) Not Acknowledged
-// - -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
-// - -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
-// - -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
+for Read, 3
 
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR PWMC Channel Interface
-// - *****************************************************************************
-// - -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
-AT91C_PWMC_CPRE           EQU (0xF <<  0) ;- (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
-AT91C_PWMC_CPRE_MCK       EQU (0x0) ;- (PWMC_CH)
-AT91C_PWMC_CPRE_MCKA      EQU (0xB) ;- (PWMC_CH)
-AT91C_PWMC_CPRE_MCKB      EQU (0xC) ;- (PWMC_CH)
-AT91C_PWMC_CALG           EQU (0x1 <<  8) ;- (PWMC_CH) Channel Alignment
-AT91C_PWMC_CPOL           EQU (0x1 <<  9) ;- (PWMC_CH) Channel Polarity
-AT91C_PWMC_CPD            EQU (0x1 << 10) ;- (PWMC_CH) Channel Update Period
-// - -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
-AT91C_PWMC_CDTY           EQU (0x0 <<  0) ;- (PWMC_CH) Channel Duty Cycle
-// - -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
-AT91C_PWMC_CPRD           EQU (0x0 <<  0) ;- (PWMC_CH) Channel Period
-// - -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
-AT91C_PWMC_CCNT           EQU (0x0 <<  0) ;- (PWMC_CH) Channel Counter
-// - -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
-AT91C_PWMC_CUPD           EQU (0x0 <<  0) ;- (PWMC_CH) Channel Update
+for Write operations
+AT91C_MC_FWS_2FWS EQU( 0x2 << 8 );
+-( MC ) 3 cycles
 
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface
-// - *****************************************************************************
-// - -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
-AT91C_PWMC_DIVA           EQU (0xFF <<  0) ;- (PWMC) CLKA divide factor.
-AT91C_PWMC_PREA           EQU (0xF <<  8) ;- (PWMC) Divider Input Clock Prescaler A
-AT91C_PWMC_PREA_MCK       EQU (0x0 <<  8) ;- (PWMC)
-AT91C_PWMC_DIVB           EQU (0xFF << 16) ;- (PWMC) CLKB divide factor.
-AT91C_PWMC_PREB           EQU (0xF << 24) ;- (PWMC) Divider Input Clock Prescaler B
-AT91C_PWMC_PREB_MCK       EQU (0x0 << 24) ;- (PWMC)
-// - -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
-AT91C_PWMC_CHID0          EQU (0x1 <<  0) ;- (PWMC) Channel ID 0
-AT91C_PWMC_CHID1          EQU (0x1 <<  1) ;- (PWMC) Channel ID 1
-AT91C_PWMC_CHID2          EQU (0x1 <<  2) ;- (PWMC) Channel ID 2
-AT91C_PWMC_CHID3          EQU (0x1 <<  3) ;- (PWMC) Channel ID 3
-// - -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
-// - -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
-// - -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
-// - -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
-// - -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
-// - -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
+for Read, 4
 
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR USB Device Interface
-// - *****************************************************************************
-// - -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
-AT91C_UDP_FRM_NUM         EQU (0x7FF <<  0) ;- (UDP) Frame Number as Defined in the Packet Field Formats
-AT91C_UDP_FRM_ERR         EQU (0x1 << 16) ;- (UDP) Frame Error
-AT91C_UDP_FRM_OK          EQU (0x1 << 17) ;- (UDP) Frame OK
-// - -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
-AT91C_UDP_FADDEN          EQU (0x1 <<  0) ;- (UDP) Function Address Enable
-AT91C_UDP_CONFG           EQU (0x1 <<  1) ;- (UDP) Configured
-AT91C_UDP_ESR             EQU (0x1 <<  2) ;- (UDP) Enable Send Resume
-AT91C_UDP_RSMINPR         EQU (0x1 <<  3) ;- (UDP) A Resume Has Been Sent to the Host
-AT91C_UDP_RMWUPE          EQU (0x1 <<  4) ;- (UDP) Remote Wake Up Enable
-// - -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
-AT91C_UDP_FADD            EQU (0xFF <<  0) ;- (UDP) Function Address Value
-AT91C_UDP_FEN             EQU (0x1 <<  8) ;- (UDP) Function Enable
-// - -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
-AT91C_UDP_EPINT0          EQU (0x1 <<  0) ;- (UDP) Endpoint 0 Interrupt
-AT91C_UDP_EPINT1          EQU (0x1 <<  1) ;- (UDP) Endpoint 0 Interrupt
-AT91C_UDP_EPINT2          EQU (0x1 <<  2) ;- (UDP) Endpoint 2 Interrupt
-AT91C_UDP_EPINT3          EQU (0x1 <<  3) ;- (UDP) Endpoint 3 Interrupt
-AT91C_UDP_EPINT4          EQU (0x1 <<  4) ;- (UDP) Endpoint 4 Interrupt
-AT91C_UDP_EPINT5          EQU (0x1 <<  5) ;- (UDP) Endpoint 5 Interrupt
-AT91C_UDP_RXSUSP          EQU (0x1 <<  8) ;- (UDP) USB Suspend Interrupt
-AT91C_UDP_RXRSM           EQU (0x1 <<  9) ;- (UDP) USB Resume Interrupt
-AT91C_UDP_EXTRSM          EQU (0x1 << 10) ;- (UDP) USB External Resume Interrupt
-AT91C_UDP_SOFINT          EQU (0x1 << 11) ;- (UDP) USB Start Of frame Interrupt
-AT91C_UDP_WAKEUP          EQU (0x1 << 13) ;- (UDP) USB Resume Interrupt
-// - -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
-// - -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
-// - -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
-AT91C_UDP_ENDBUSRES       EQU (0x1 << 12) ;- (UDP) USB End Of Bus Reset Interrupt
-// - -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
-// - -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
-AT91C_UDP_EP0             EQU (0x1 <<  0) ;- (UDP) Reset Endpoint 0
-AT91C_UDP_EP1             EQU (0x1 <<  1) ;- (UDP) Reset Endpoint 1
-AT91C_UDP_EP2             EQU (0x1 <<  2) ;- (UDP) Reset Endpoint 2
-AT91C_UDP_EP3             EQU (0x1 <<  3) ;- (UDP) Reset Endpoint 3
-AT91C_UDP_EP4             EQU (0x1 <<  4) ;- (UDP) Reset Endpoint 4
-AT91C_UDP_EP5             EQU (0x1 <<  5) ;- (UDP) Reset Endpoint 5
-// - -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
-AT91C_UDP_TXCOMP          EQU (0x1 <<  0) ;- (UDP) Generates an IN packet with data previously written in the DPR
-AT91C_UDP_RX_DATA_BK0     EQU (0x1 <<  1) ;- (UDP) Receive Data Bank 0
-AT91C_UDP_RXSETUP         EQU (0x1 <<  2) ;- (UDP) Sends STALL to the Host (Control endpoints)
-AT91C_UDP_ISOERROR        EQU (0x1 <<  3) ;- (UDP) Isochronous error (Isochronous endpoints)
-AT91C_UDP_TXPKTRDY        EQU (0x1 <<  4) ;- (UDP) Transmit Packet Ready
-AT91C_UDP_FORCESTALL      EQU (0x1 <<  5) ;- (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
-AT91C_UDP_RX_DATA_BK1     EQU (0x1 <<  6) ;- (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
-AT91C_UDP_DIR             EQU (0x1 <<  7) ;- (UDP) Transfer Direction
-AT91C_UDP_EPTYPE          EQU (0x7 <<  8) ;- (UDP) Endpoint type
-AT91C_UDP_EPTYPE_CTRL     EQU (0x0 <<  8) ;- (UDP) Control
-AT91C_UDP_EPTYPE_ISO_OUT  EQU (0x1 <<  8) ;- (UDP) Isochronous OUT
-AT91C_UDP_EPTYPE_BULK_OUT EQU (0x2 <<  8) ;- (UDP) Bulk OUT
-AT91C_UDP_EPTYPE_INT_OUT  EQU (0x3 <<  8) ;- (UDP) Interrupt OUT
-AT91C_UDP_EPTYPE_ISO_IN   EQU (0x5 <<  8) ;- (UDP) Isochronous IN
-AT91C_UDP_EPTYPE_BULK_IN  EQU (0x6 <<  8) ;- (UDP) Bulk IN
-AT91C_UDP_EPTYPE_INT_IN   EQU (0x7 <<  8) ;- (UDP) Interrupt IN
-AT91C_UDP_DTGLE           EQU (0x1 << 11) ;- (UDP) Data Toggle
-AT91C_UDP_EPEDS           EQU (0x1 << 15) ;- (UDP) Endpoint Enable Disable
-AT91C_UDP_RXBYTECNT       EQU (0x7FF << 16) ;- (UDP) Number Of Bytes Available in the FIFO
-// - -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------
-AT91C_UDP_TXVDIS          EQU (0x1 <<  8) ;- (UDP)
-AT91C_UDP_PUON            EQU (0x1 <<  9) ;- (UDP) Pull-up ON
+for Write operations
+AT91C_MC_FWS_3FWS EQU( 0x3 << 8 );
+-( MC ) 4 cycles
 
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
-// - *****************************************************************************
-// - -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
-AT91C_TC_CLKEN            EQU (0x1 <<  0) ;- (TC) Counter Clock Enable Command
-AT91C_TC_CLKDIS           EQU (0x1 <<  1) ;- (TC) Counter Clock Disable Command
-AT91C_TC_SWTRG            EQU (0x1 <<  2) ;- (TC) Software Trigger Command
-// - -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
-AT91C_TC_CLKS             EQU (0x7 <<  0) ;- (TC) Clock Selection
-AT91C_TC_CLKS_TIMER_DIV1_CLOCK EQU (0x0) ;- (TC) Clock selected: TIMER_DIV1_CLOCK
-AT91C_TC_CLKS_TIMER_DIV2_CLOCK EQU (0x1) ;- (TC) Clock selected: TIMER_DIV2_CLOCK
-AT91C_TC_CLKS_TIMER_DIV3_CLOCK EQU (0x2) ;- (TC) Clock selected: TIMER_DIV3_CLOCK
-AT91C_TC_CLKS_TIMER_DIV4_CLOCK EQU (0x3) ;- (TC) Clock selected: TIMER_DIV4_CLOCK
-AT91C_TC_CLKS_TIMER_DIV5_CLOCK EQU (0x4) ;- (TC) Clock selected: TIMER_DIV5_CLOCK
-AT91C_TC_CLKS_XC0         EQU (0x5) ;- (TC) Clock selected: XC0
-AT91C_TC_CLKS_XC1         EQU (0x6) ;- (TC) Clock selected: XC1
-AT91C_TC_CLKS_XC2         EQU (0x7) ;- (TC) Clock selected: XC2
-AT91C_TC_CLKI             EQU (0x1 <<  3) ;- (TC) Clock Invert
-AT91C_TC_BURST            EQU (0x3 <<  4) ;- (TC) Burst Signal Selection
-AT91C_TC_BURST_NONE       EQU (0x0 <<  4) ;- (TC) The clock is not gated by an external signal
-AT91C_TC_BURST_XC0        EQU (0x1 <<  4) ;- (TC) XC0 is ANDed with the selected clock
-AT91C_TC_BURST_XC1        EQU (0x2 <<  4) ;- (TC) XC1 is ANDed with the selected clock
-AT91C_TC_BURST_XC2        EQU (0x3 <<  4) ;- (TC) XC2 is ANDed with the selected clock
-AT91C_TC_CPCSTOP          EQU (0x1 <<  6) ;- (TC) Counter Clock Stopped with RC Compare
-AT91C_TC_LDBSTOP          EQU (0x1 <<  6) ;- (TC) Counter Clock Stopped with RB Loading
-AT91C_TC_CPCDIS           EQU (0x1 <<  7) ;- (TC) Counter Clock Disable with RC Compare
-AT91C_TC_LDBDIS           EQU (0x1 <<  7) ;- (TC) Counter Clock Disabled with RB Loading
-AT91C_TC_ETRGEDG          EQU (0x3 <<  8) ;- (TC) External Trigger Edge Selection
-AT91C_TC_ETRGEDG_NONE     EQU (0x0 <<  8) ;- (TC) Edge: None
-AT91C_TC_ETRGEDG_RISING   EQU (0x1 <<  8) ;- (TC) Edge: rising edge
-AT91C_TC_ETRGEDG_FALLING  EQU (0x2 <<  8) ;- (TC) Edge: falling edge
-AT91C_TC_ETRGEDG_BOTH     EQU (0x3 <<  8) ;- (TC) Edge: each edge
-AT91C_TC_EEVTEDG          EQU (0x3 <<  8) ;- (TC) External Event Edge Selection
-AT91C_TC_EEVTEDG_NONE     EQU (0x0 <<  8) ;- (TC) Edge: None
-AT91C_TC_EEVTEDG_RISING   EQU (0x1 <<  8) ;- (TC) Edge: rising edge
-AT91C_TC_EEVTEDG_FALLING  EQU (0x2 <<  8) ;- (TC) Edge: falling edge
-AT91C_TC_EEVTEDG_BOTH     EQU (0x3 <<  8) ;- (TC) Edge: each edge
-AT91C_TC_EEVT             EQU (0x3 << 10) ;- (TC) External Event  Selection
-AT91C_TC_EEVT_TIOB        EQU (0x0 << 10) ;- (TC) Signal selected as external event: TIOB TIOB direction: input
-AT91C_TC_EEVT_XC0         EQU (0x1 << 10) ;- (TC) Signal selected as external event: XC0 TIOB direction: output
-AT91C_TC_EEVT_XC1         EQU (0x2 << 10) ;- (TC) Signal selected as external event: XC1 TIOB direction: output
-AT91C_TC_EEVT_XC2         EQU (0x3 << 10) ;- (TC) Signal selected as external event: XC2 TIOB direction: output
-AT91C_TC_ABETRG           EQU (0x1 << 10) ;- (TC) TIOA or TIOB External Trigger Selection
-AT91C_TC_ENETRG           EQU (0x1 << 12) ;- (TC) External Event Trigger enable
-AT91C_TC_WAVESEL          EQU (0x3 << 13) ;- (TC) Waveform  Selection
-AT91C_TC_WAVESEL_UP       EQU (0x0 << 13) ;- (TC) UP mode without atomatic trigger on RC Compare
-AT91C_TC_WAVESEL_UPDOWN   EQU (0x1 << 13) ;- (TC) UPDOWN mode without automatic trigger on RC Compare
-AT91C_TC_WAVESEL_UP_AUTO  EQU (0x2 << 13) ;- (TC) UP mode with automatic trigger on RC Compare
-AT91C_TC_WAVESEL_UPDOWN_AUTO EQU (0x3 << 13) ;- (TC) UPDOWN mode with automatic trigger on RC Compare
-AT91C_TC_CPCTRG           EQU (0x1 << 14) ;- (TC) RC Compare Trigger Enable
-AT91C_TC_WAVE             EQU (0x1 << 15) ;- (TC)
-AT91C_TC_ACPA             EQU (0x3 << 16) ;- (TC) RA Compare Effect on TIOA
-AT91C_TC_ACPA_NONE        EQU (0x0 << 16) ;- (TC) Effect: none
-AT91C_TC_ACPA_SET         EQU (0x1 << 16) ;- (TC) Effect: set
-AT91C_TC_ACPA_CLEAR       EQU (0x2 << 16) ;- (TC) Effect: clear
-AT91C_TC_ACPA_TOGGLE      EQU (0x3 << 16) ;- (TC) Effect: toggle
-AT91C_TC_LDRA             EQU (0x3 << 16) ;- (TC) RA Loading Selection
-AT91C_TC_LDRA_NONE        EQU (0x0 << 16) ;- (TC) Edge: None
-AT91C_TC_LDRA_RISING      EQU (0x1 << 16) ;- (TC) Edge: rising edge of TIOA
-AT91C_TC_LDRA_FALLING     EQU (0x2 << 16) ;- (TC) Edge: falling edge of TIOA
-AT91C_TC_LDRA_BOTH        EQU (0x3 << 16) ;- (TC) Edge: each edge of TIOA
-AT91C_TC_ACPC             EQU (0x3 << 18) ;- (TC) RC Compare Effect on TIOA
-AT91C_TC_ACPC_NONE        EQU (0x0 << 18) ;- (TC) Effect: none
-AT91C_TC_ACPC_SET         EQU (0x1 << 18) ;- (TC) Effect: set
-AT91C_TC_ACPC_CLEAR       EQU (0x2 << 18) ;- (TC) Effect: clear
-AT91C_TC_ACPC_TOGGLE      EQU (0x3 << 18) ;- (TC) Effect: toggle
-AT91C_TC_LDRB             EQU (0x3 << 18) ;- (TC) RB Loading Selection
-AT91C_TC_LDRB_NONE        EQU (0x0 << 18) ;- (TC) Edge: None
-AT91C_TC_LDRB_RISING      EQU (0x1 << 18) ;- (TC) Edge: rising edge of TIOA
-AT91C_TC_LDRB_FALLING     EQU (0x2 << 18) ;- (TC) Edge: falling edge of TIOA
-AT91C_TC_LDRB_BOTH        EQU (0x3 << 18) ;- (TC) Edge: each edge of TIOA
-AT91C_TC_AEEVT            EQU (0x3 << 20) ;- (TC) External Event Effect on TIOA
-AT91C_TC_AEEVT_NONE       EQU (0x0 << 20) ;- (TC) Effect: none
-AT91C_TC_AEEVT_SET        EQU (0x1 << 20) ;- (TC) Effect: set
-AT91C_TC_AEEVT_CLEAR      EQU (0x2 << 20) ;- (TC) Effect: clear
-AT91C_TC_AEEVT_TOGGLE     EQU (0x3 << 20) ;- (TC) Effect: toggle
-AT91C_TC_ASWTRG           EQU (0x3 << 22) ;- (TC) Software Trigger Effect on TIOA
-AT91C_TC_ASWTRG_NONE      EQU (0x0 << 22) ;- (TC) Effect: none
-AT91C_TC_ASWTRG_SET       EQU (0x1 << 22) ;- (TC) Effect: set
-AT91C_TC_ASWTRG_CLEAR     EQU (0x2 << 22) ;- (TC) Effect: clear
-AT91C_TC_ASWTRG_TOGGLE    EQU (0x3 << 22) ;- (TC) Effect: toggle
-AT91C_TC_BCPB             EQU (0x3 << 24) ;- (TC) RB Compare Effect on TIOB
-AT91C_TC_BCPB_NONE        EQU (0x0 << 24) ;- (TC) Effect: none
-AT91C_TC_BCPB_SET         EQU (0x1 << 24) ;- (TC) Effect: set
-AT91C_TC_BCPB_CLEAR       EQU (0x2 << 24) ;- (TC) Effect: clear
-AT91C_TC_BCPB_TOGGLE      EQU (0x3 << 24) ;- (TC) Effect: toggle
-AT91C_TC_BCPC             EQU (0x3 << 26) ;- (TC) RC Compare Effect on TIOB
-AT91C_TC_BCPC_NONE        EQU (0x0 << 26) ;- (TC) Effect: none
-AT91C_TC_BCPC_SET         EQU (0x1 << 26) ;- (TC) Effect: set
-AT91C_TC_BCPC_CLEAR       EQU (0x2 << 26) ;- (TC) Effect: clear
-AT91C_TC_BCPC_TOGGLE      EQU (0x3 << 26) ;- (TC) Effect: toggle
-AT91C_TC_BEEVT            EQU (0x3 << 28) ;- (TC) External Event Effect on TIOB
-AT91C_TC_BEEVT_NONE       EQU (0x0 << 28) ;- (TC) Effect: none
-AT91C_TC_BEEVT_SET        EQU (0x1 << 28) ;- (TC) Effect: set
-AT91C_TC_BEEVT_CLEAR      EQU (0x2 << 28) ;- (TC) Effect: clear
-AT91C_TC_BEEVT_TOGGLE     EQU (0x3 << 28) ;- (TC) Effect: toggle
-AT91C_TC_BSWTRG           EQU (0x3 << 30) ;- (TC) Software Trigger Effect on TIOB
-AT91C_TC_BSWTRG_NONE      EQU (0x0 << 30) ;- (TC) Effect: none
-AT91C_TC_BSWTRG_SET       EQU (0x1 << 30) ;- (TC) Effect: set
-AT91C_TC_BSWTRG_CLEAR     EQU (0x2 << 30) ;- (TC) Effect: clear
-AT91C_TC_BSWTRG_TOGGLE    EQU (0x3 << 30) ;- (TC) Effect: toggle
-// - -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
-AT91C_TC_COVFS            EQU (0x1 <<  0) ;- (TC) Counter Overflow
-AT91C_TC_LOVRS            EQU (0x1 <<  1) ;- (TC) Load Overrun
-AT91C_TC_CPAS             EQU (0x1 <<  2) ;- (TC) RA Compare
-AT91C_TC_CPBS             EQU (0x1 <<  3) ;- (TC) RB Compare
-AT91C_TC_CPCS             EQU (0x1 <<  4) ;- (TC) RC Compare
-AT91C_TC_LDRAS            EQU (0x1 <<  5) ;- (TC) RA Loading
-AT91C_TC_LDRBS            EQU (0x1 <<  6) ;- (TC) RB Loading
-AT91C_TC_ETRGS            EQU (0x1 <<  7) ;- (TC) External Trigger
-AT91C_TC_CLKSTA           EQU (0x1 << 16) ;- (TC) Clock Enabling
-AT91C_TC_MTIOA            EQU (0x1 << 17) ;- (TC) TIOA Mirror
-AT91C_TC_MTIOB            EQU (0x1 << 18) ;- (TC) TIOA Mirror
-// - -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
-// - -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
-// - -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
+for Read, 4
 
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Timer Counter Interface
-// - *****************************************************************************
-// - -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
-AT91C_TCB_SYNC            EQU (0x1 <<  0) ;- (TCB) Synchro Command
-// - -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
-AT91C_TCB_TC0XC0S         EQU (0x3 <<  0) ;- (TCB) External Clock Signal 0 Selection
-AT91C_TCB_TC0XC0S_TCLK0   EQU (0x0) ;- (TCB) TCLK0 connected to XC0
-AT91C_TCB_TC0XC0S_NONE    EQU (0x1) ;- (TCB) None signal connected to XC0
-AT91C_TCB_TC0XC0S_TIOA1   EQU (0x2) ;- (TCB) TIOA1 connected to XC0
-AT91C_TCB_TC0XC0S_TIOA2   EQU (0x3) ;- (TCB) TIOA2 connected to XC0
-AT91C_TCB_TC1XC1S         EQU (0x3 <<  2) ;- (TCB) External Clock Signal 1 Selection
-AT91C_TCB_TC1XC1S_TCLK1   EQU (0x0 <<  2) ;- (TCB) TCLK1 connected to XC1
-AT91C_TCB_TC1XC1S_NONE    EQU (0x1 <<  2) ;- (TCB) None signal connected to XC1
-AT91C_TCB_TC1XC1S_TIOA0   EQU (0x2 <<  2) ;- (TCB) TIOA0 connected to XC1
-AT91C_TCB_TC1XC1S_TIOA2   EQU (0x3 <<  2) ;- (TCB) TIOA2 connected to XC1
-AT91C_TCB_TC2XC2S         EQU (0x3 <<  4) ;- (TCB) External Clock Signal 2 Selection
-AT91C_TCB_TC2XC2S_TCLK2   EQU (0x0 <<  4) ;- (TCB) TCLK2 connected to XC2
-AT91C_TCB_TC2XC2S_NONE    EQU (0x1 <<  4) ;- (TCB) None signal connected to XC2
-AT91C_TCB_TC2XC2S_TIOA0   EQU (0x2 <<  4) ;- (TCB) TIOA0 connected to XC2
-AT91C_TCB_TC2XC2S_TIOA1   EQU (0x3 <<  4) ;- (TCB) TIOA2 connected to XC2
+for Write operations
+AT91C_MC_FMCN EQU( 0xFF << 16 );
+-( MC ) Flash Microsecond Cycle Number
+/* - -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- */
+AT91C_MC_FCMD EQU( 0xF << 0 );
+-( MC ) Flash Command
+AT91C_MC_FCMD_START_PROG EQU( 0x1 );
+-( MC ) Starts the programming of th epage specified by PAGEN.
+   AT91C_MC_FCMD_LOCK EQU( 0x2 );
+-( MC ) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+   AT91C_MC_FCMD_PROG_AND_LOCK EQU( 0x3 );
+-( MC ) The lock sequence automatically happens after the programming sequence is completed.
+   AT91C_MC_FCMD_UNLOCK EQU( 0x4 );
+-( MC ) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+   AT91C_MC_FCMD_ERASE_ALL EQU( 0x8 );
+-( MC ) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
+   AT91C_MC_FCMD_SET_GP_NVM EQU( 0xB );
+-( MC ) Set General Purpose NVM bits.
+   AT91C_MC_FCMD_CLR_GP_NVM EQU( 0xD );
+-( MC ) Clear General Purpose NVM bits.
+   AT91C_MC_FCMD_SET_SECURITY EQU( 0xF );
+-( MC ) Set Security Bit.
+   AT91C_MC_PAGEN EQU( 0x3FF << 8 );
+-( MC ) Page Number
+AT91C_MC_KEY EQU( 0xFF << 24 );
+-( MC ) Writing Protect Key
+/* - -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- */
+AT91C_MC_SECURITY EQU( 0x1 << 4 );
+-( MC ) Security Bit Status
+AT91C_MC_GPNVM0 EQU( 0x1 << 8 );
+-( MC ) Sector 0 Lock Status
+AT91C_MC_GPNVM1 EQU( 0x1 << 9 );
+-( MC ) Sector 1 Lock Status
+AT91C_MC_GPNVM2 EQU( 0x1 << 10 );
+-( MC ) Sector 2 Lock Status
+AT91C_MC_GPNVM3 EQU( 0x1 << 11 );
+-( MC ) Sector 3 Lock Status
+AT91C_MC_GPNVM4 EQU( 0x1 << 12 );
+-( MC ) Sector 4 Lock Status
+AT91C_MC_GPNVM5 EQU( 0x1 << 13 );
+-( MC ) Sector 5 Lock Status
+AT91C_MC_GPNVM6 EQU( 0x1 << 14 );
+-( MC ) Sector 6 Lock Status
+AT91C_MC_GPNVM7 EQU( 0x1 << 15 );
+-( MC ) Sector 7 Lock Status
+AT91C_MC_LOCKS0 EQU( 0x1 << 16 );
+-( MC ) Sector 0 Lock Status
+AT91C_MC_LOCKS1 EQU( 0x1 << 17 );
+-( MC ) Sector 1 Lock Status
+AT91C_MC_LOCKS2 EQU( 0x1 << 18 );
+-( MC ) Sector 2 Lock Status
+AT91C_MC_LOCKS3 EQU( 0x1 << 19 );
+-( MC ) Sector 3 Lock Status
+AT91C_MC_LOCKS4 EQU( 0x1 << 20 );
+-( MC ) Sector 4 Lock Status
+AT91C_MC_LOCKS5 EQU( 0x1 << 21 );
+-( MC ) Sector 5 Lock Status
+AT91C_MC_LOCKS6 EQU( 0x1 << 22 );
+-( MC ) Sector 6 Lock Status
+AT91C_MC_LOCKS7 EQU( 0x1 << 23 );
+-( MC ) Sector 7 Lock Status
+AT91C_MC_LOCKS8 EQU( 0x1 << 24 );
+-( MC ) Sector 8 Lock Status
+AT91C_MC_LOCKS9 EQU( 0x1 << 25 );
+-( MC ) Sector 9 Lock Status
+AT91C_MC_LOCKS10 EQU( 0x1 << 26 );
+-( MC ) Sector 10 Lock Status
+AT91C_MC_LOCKS11 EQU( 0x1 << 27 );
+-( MC ) Sector 11 Lock Status
+AT91C_MC_LOCKS12 EQU( 0x1 << 28 );
+-( MC ) Sector 12 Lock Status
+AT91C_MC_LOCKS13 EQU( 0x1 << 29 );
+-( MC ) Sector 13 Lock Status
+AT91C_MC_LOCKS14 EQU( 0x1 << 30 );
+-( MC ) Sector 14 Lock Status
+AT91C_MC_LOCKS15 EQU( 0x1 << 31 );
+-( MC ) Sector 15 Lock Status
 
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Control Area Network MailBox Interface
-// - *****************************************************************************
-// - -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register --------
-AT91C_CAN_MTIMEMARK       EQU (0xFFFF <<  0) ;- (CAN_MB) Mailbox Timemark
-AT91C_CAN_PRIOR           EQU (0xF << 16) ;- (CAN_MB) Mailbox Priority
-AT91C_CAN_MOT             EQU (0x7 << 24) ;- (CAN_MB) Mailbox Object Type
-AT91C_CAN_MOT_DIS         EQU (0x0 << 24) ;- (CAN_MB)
-AT91C_CAN_MOT_RX          EQU (0x1 << 24) ;- (CAN_MB)
-AT91C_CAN_MOT_RXOVERWRITE EQU (0x2 << 24) ;- (CAN_MB)
-AT91C_CAN_MOT_TX          EQU (0x3 << 24) ;- (CAN_MB)
-AT91C_CAN_MOT_CONSUMER    EQU (0x4 << 24) ;- (CAN_MB)
-AT91C_CAN_MOT_PRODUCER    EQU (0x5 << 24) ;- (CAN_MB)
-// - -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register --------
-AT91C_CAN_MIDvB           EQU (0x3FFFF <<  0) ;- (CAN_MB) Complementary bits for identifier in extended mode
-AT91C_CAN_MIDvA           EQU (0x7FF << 18) ;- (CAN_MB) Identifier for standard frame mode
-AT91C_CAN_MIDE            EQU (0x1 << 29) ;- (CAN_MB) Identifier Version
-// - -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register --------
-// - -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register --------
-// - -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register --------
-AT91C_CAN_MTIMESTAMP      EQU (0xFFFF <<  0) ;- (CAN_MB) Timer Value
-AT91C_CAN_MDLC            EQU (0xF << 16) ;- (CAN_MB) Mailbox Data Length Code
-AT91C_CAN_MRTR            EQU (0x1 << 20) ;- (CAN_MB) Mailbox Remote Transmission Request
-AT91C_CAN_MABT            EQU (0x1 << 22) ;- (CAN_MB) Mailbox Message Abort
-AT91C_CAN_MRDY            EQU (0x1 << 23) ;- (CAN_MB) Mailbox Ready
-AT91C_CAN_MMI             EQU (0x1 << 24) ;- (CAN_MB) Mailbox Message Ignored
-// - -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register --------
-// - -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register --------
-// - -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register --------
-AT91C_CAN_MACR            EQU (0x1 << 22) ;- (CAN_MB) Abort Request for Mailbox
-AT91C_CAN_MTCR            EQU (0x1 << 23) ;- (CAN_MB) Mailbox Transfer Command
+/* - ***************************************************************************** */
+/* -              SOFTWARE API DEFINITION  FOR Serial Parallel Interface */
+/* - ***************************************************************************** */
+/* - -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */
+AT91C_SPI_SPIEN EQU( 0x1 << 0 );
+-( SPI ) SPI Enable
+AT91C_SPI_SPIDIS EQU( 0x1 << 1 );
+-( SPI ) SPI Disable
+AT91C_SPI_SWRST EQU( 0x1 << 7 );
+-( SPI ) SPI Software reset
+AT91C_SPI_LASTXFER EQU( 0x1 << 24 );
+-( SPI ) SPI Last Transfer
+/* - -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- */
+AT91C_SPI_MSTR EQU( 0x1 << 0 );
+-( SPI ) Master / Slave Mode
+AT91C_SPI_PS EQU( 0x1 << 1 );
+-( SPI ) Peripheral Select
+AT91C_SPI_PS_FIXED EQU( 0x0 << 1 );
+-( SPI ) Fixed Peripheral Select
+AT91C_SPI_PS_VARIABLE EQU( 0x1 << 1 );
+-( SPI ) Variable Peripheral Select
+AT91C_SPI_PCSDEC EQU( 0x1 << 2 );
+-( SPI ) Chip Select Decode
+AT91C_SPI_FDIV EQU( 0x1 << 3 );
+-( SPI ) Clock Selection
+AT91C_SPI_MODFDIS EQU( 0x1 << 4 );
+-( SPI ) Mode Fault Detection
+AT91C_SPI_LLB EQU( 0x1 << 7 );
+-( SPI ) Clock Selection
+AT91C_SPI_PCS EQU( 0xF << 16 );
+-( SPI ) Peripheral Chip Select
+AT91C_SPI_DLYBCS EQU( 0xFF << 24 );
+-( SPI ) Delay Between Chip Selects
+/* - -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- */
+AT91C_SPI_RD EQU( 0xFFFF << 0 );
+-( SPI ) Receive Data
+AT91C_SPI_RPCS EQU( 0xF << 16 );
+-( SPI ) Peripheral Chip Select Status
+/* - -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- */
+AT91C_SPI_TD EQU( 0xFFFF << 0 );
+-( SPI ) Transmit Data
+AT91C_SPI_TPCS EQU( 0xF << 16 );
+-( SPI ) Peripheral Chip Select Status
+/* - -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
+AT91C_SPI_RDRF EQU( 0x1 << 0 );
+-( SPI ) Receive Data Register Full
+AT91C_SPI_TDRE EQU( 0x1 << 1 );
+-( SPI ) Transmit Data Register Empty
+AT91C_SPI_MODF EQU( 0x1 << 2 );
+-( SPI ) Mode Fault Error
+AT91C_SPI_OVRES EQU( 0x1 << 3 );
+-( SPI ) Overrun Error Status
+AT91C_SPI_ENDRX EQU( 0x1 << 4 );
+-( SPI ) End of Receiver Transfer
+AT91C_SPI_ENDTX EQU( 0x1 << 5 );
+-( SPI ) End of Receiver Transfer
+AT91C_SPI_RXBUFF EQU( 0x1 << 6 );
+-( SPI ) RXBUFF Interrupt
+AT91C_SPI_TXBUFE EQU( 0x1 << 7 );
+-( SPI ) TXBUFE Interrupt
+AT91C_SPI_NSSR EQU( 0x1 << 8 );
+-( SPI ) NSSR Interrupt
+AT91C_SPI_TXEMPTY EQU( 0x1 << 9 );
+-( SPI ) TXEMPTY Interrupt
+AT91C_SPI_SPIENS EQU( 0x1 << 16 );
+-( SPI ) Enable Status
+/* - -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
+/* - -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
+/* - -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */
+/* - -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */
+AT91C_SPI_CPOL EQU( 0x1 << 0 );
+-( SPI ) Clock Polarity
+AT91C_SPI_NCPHA EQU( 0x1 << 1 );
+-( SPI ) Clock Phase
+AT91C_SPI_CSAAT EQU( 0x1 << 3 );
+-( SPI ) Chip Select Active After Transfer
+AT91C_SPI_BITS EQU( 0xF << 4 );
+-( SPI ) Bits Per Transfer
+AT91C_SPI_BITS_8 EQU( 0x0 << 4 );
+-( SPI ) 8 Bits Per transfer
+AT91C_SPI_BITS_9 EQU( 0x1 << 4 );
+-( SPI ) 9 Bits Per transfer
+AT91C_SPI_BITS_10 EQU( 0x2 << 4 );
+-( SPI ) 10 Bits Per transfer
+AT91C_SPI_BITS_11 EQU( 0x3 << 4 );
+-( SPI ) 11 Bits Per transfer
+AT91C_SPI_BITS_12 EQU( 0x4 << 4 );
+-( SPI ) 12 Bits Per transfer
+AT91C_SPI_BITS_13 EQU( 0x5 << 4 );
+-( SPI ) 13 Bits Per transfer
+AT91C_SPI_BITS_14 EQU( 0x6 << 4 );
+-( SPI ) 14 Bits Per transfer
+AT91C_SPI_BITS_15 EQU( 0x7 << 4 );
+-( SPI ) 15 Bits Per transfer
+AT91C_SPI_BITS_16 EQU( 0x8 << 4 );
+-( SPI ) 16 Bits Per transfer
+AT91C_SPI_SCBR EQU( 0xFF << 8 );
+-( SPI ) Serial Clock Baud Rate
+AT91C_SPI_DLYBS EQU( 0xFF << 16 );
+-( SPI ) Delay Before SPCK
+AT91C_SPI_DLYBCT EQU( 0xFF << 24 );
+-( SPI ) Delay Between Consecutive Transfers
 
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Control Area Network Interface
-// - *****************************************************************************
-// - -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register --------
-AT91C_CAN_CANEN           EQU (0x1 <<  0) ;- (CAN) CAN Controller Enable
-AT91C_CAN_LPM             EQU (0x1 <<  1) ;- (CAN) Disable/Enable Low Power Mode
-AT91C_CAN_ABM             EQU (0x1 <<  2) ;- (CAN) Disable/Enable Autobaud/Listen Mode
-AT91C_CAN_OVL             EQU (0x1 <<  3) ;- (CAN) Disable/Enable Overload Frame
-AT91C_CAN_TEOF            EQU (0x1 <<  4) ;- (CAN) Time Stamp messages at each end of Frame
-AT91C_CAN_TTM             EQU (0x1 <<  5) ;- (CAN) Disable/Enable Time Trigger Mode
-AT91C_CAN_TIMFRZ          EQU (0x1 <<  6) ;- (CAN) Enable Timer Freeze
-AT91C_CAN_DRPT            EQU (0x1 <<  7) ;- (CAN) Disable Repeat
-// - -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register --------
-AT91C_CAN_MB0             EQU (0x1 <<  0) ;- (CAN) Mailbox 0 Flag
-AT91C_CAN_MB1             EQU (0x1 <<  1) ;- (CAN) Mailbox 1 Flag
-AT91C_CAN_MB2             EQU (0x1 <<  2) ;- (CAN) Mailbox 2 Flag
-AT91C_CAN_MB3             EQU (0x1 <<  3) ;- (CAN) Mailbox 3 Flag
-AT91C_CAN_MB4             EQU (0x1 <<  4) ;- (CAN) Mailbox 4 Flag
-AT91C_CAN_MB5             EQU (0x1 <<  5) ;- (CAN) Mailbox 5 Flag
-AT91C_CAN_MB6             EQU (0x1 <<  6) ;- (CAN) Mailbox 6 Flag
-AT91C_CAN_MB7             EQU (0x1 <<  7) ;- (CAN) Mailbox 7 Flag
-AT91C_CAN_MB8             EQU (0x1 <<  8) ;- (CAN) Mailbox 8 Flag
-AT91C_CAN_MB9             EQU (0x1 <<  9) ;- (CAN) Mailbox 9 Flag
-AT91C_CAN_MB10            EQU (0x1 << 10) ;- (CAN) Mailbox 10 Flag
-AT91C_CAN_MB11            EQU (0x1 << 11) ;- (CAN) Mailbox 11 Flag
-AT91C_CAN_MB12            EQU (0x1 << 12) ;- (CAN) Mailbox 12 Flag
-AT91C_CAN_MB13            EQU (0x1 << 13) ;- (CAN) Mailbox 13 Flag
-AT91C_CAN_MB14            EQU (0x1 << 14) ;- (CAN) Mailbox 14 Flag
-AT91C_CAN_MB15            EQU (0x1 << 15) ;- (CAN) Mailbox 15 Flag
-AT91C_CAN_ERRA            EQU (0x1 << 16) ;- (CAN) Error Active Mode Flag
-AT91C_CAN_WARN            EQU (0x1 << 17) ;- (CAN) Warning Limit Flag
-AT91C_CAN_ERRP            EQU (0x1 << 18) ;- (CAN) Error Passive Mode Flag
-AT91C_CAN_BOFF            EQU (0x1 << 19) ;- (CAN) Bus Off Mode Flag
-AT91C_CAN_SLEEP           EQU (0x1 << 20) ;- (CAN) Sleep Flag
-AT91C_CAN_WAKEUP          EQU (0x1 << 21) ;- (CAN) Wakeup Flag
-AT91C_CAN_TOVF            EQU (0x1 << 22) ;- (CAN) Timer Overflow Flag
-AT91C_CAN_TSTP            EQU (0x1 << 23) ;- (CAN) Timestamp Flag
-AT91C_CAN_CERR            EQU (0x1 << 24) ;- (CAN) CRC Error
-AT91C_CAN_SERR            EQU (0x1 << 25) ;- (CAN) Stuffing Error
-AT91C_CAN_AERR            EQU (0x1 << 26) ;- (CAN) Acknowledgment Error
-AT91C_CAN_FERR            EQU (0x1 << 27) ;- (CAN) Form Error
-AT91C_CAN_BERR            EQU (0x1 << 28) ;- (CAN) Bit Error
-// - -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register --------
-// - -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register --------
-// - -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register --------
-AT91C_CAN_RBSY            EQU (0x1 << 29) ;- (CAN) Receiver Busy
-AT91C_CAN_TBSY            EQU (0x1 << 30) ;- (CAN) Transmitter Busy
-AT91C_CAN_OVLY            EQU (0x1 << 31) ;- (CAN) Overload Busy
-// - -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register --------
-AT91C_CAN_PHASE2          EQU (0x7 <<  0) ;- (CAN) Phase 2 segment
-AT91C_CAN_PHASE1          EQU (0x7 <<  4) ;- (CAN) Phase 1 segment
-AT91C_CAN_PROPAG          EQU (0x7 <<  8) ;- (CAN) Programmation time segment
-AT91C_CAN_SYNC            EQU (0x3 << 12) ;- (CAN) Re-synchronization jump width segment
-AT91C_CAN_BRP             EQU (0x7F << 16) ;- (CAN) Baudrate Prescaler
-AT91C_CAN_SMP             EQU (0x1 << 24) ;- (CAN) Sampling mode
-// - -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register --------
-AT91C_CAN_TIMER           EQU (0xFFFF <<  0) ;- (CAN) Timer field
-// - -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register --------
-// - -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register --------
-AT91C_CAN_REC             EQU (0xFF <<  0) ;- (CAN) Receive Error Counter
-AT91C_CAN_TEC             EQU (0xFF << 16) ;- (CAN) Transmit Error Counter
-// - -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register --------
-AT91C_CAN_TIMRST          EQU (0x1 << 31) ;- (CAN) Timer Reset Field
-// - -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register --------
+/* - ***************************************************************************** */
+/* -              SOFTWARE API DEFINITION  FOR Usart */
+/* - ***************************************************************************** */
+/* - -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- */
+AT91C_US_STTBRK EQU( 0x1 << 9 );
+-( USART ) Start Break
+AT91C_US_STPBRK EQU( 0x1 << 10 );
+-( USART ) Stop Break
+AT91C_US_STTTO EQU( 0x1 << 11 );
+-( USART ) Start Time - out
+AT91C_US_SENDA EQU( 0x1 << 12 );
+-( USART ) Send Address
+AT91C_US_RSTIT EQU( 0x1 << 13 );
+-( USART ) Reset Iterations
+AT91C_US_RSTNACK EQU( 0x1 << 14 );
+-( USART ) Reset Non Acknowledge
+AT91C_US_RETTO EQU( 0x1 << 15 );
+-( USART ) Rearm Time - out
+AT91C_US_DTREN EQU( 0x1 << 16 );
+-( USART ) Data Terminal ready Enable
+AT91C_US_DTRDIS EQU( 0x1 << 17 );
+-( USART ) Data Terminal ready Disable
+AT91C_US_RTSEN EQU( 0x1 << 18 );
+-( USART ) Request to Send enable
+AT91C_US_RTSDIS EQU( 0x1 << 19 );
+-( USART ) Request to Send Disable
+/* - -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- */
+AT91C_US_USMODE EQU( 0xF << 0 );
+-( USART ) Usart mode
+AT91C_US_USMODE_NORMAL EQU( 0x0 );
+-( USART ) Normal
+AT91C_US_USMODE_RS485 EQU( 0x1 );
+-( USART ) RS485
+AT91C_US_USMODE_HWHSH EQU( 0x2 );
+-( USART ) Hardware Handshaking
+AT91C_US_USMODE_MODEM EQU( 0x3 );
+-( USART ) Modem
+AT91C_US_USMODE_ISO7816_0 EQU( 0x4 );
+-( USART ) ISO7816 protocol: T = 0
+                                 AT91C_US_USMODE_ISO7816_1 EQU( 0x6 );
+-( USART ) ISO7816 protocol: T = 1
+                                 AT91C_US_USMODE_IRDA EQU( 0x8 );
+-( USART ) IrDA
+AT91C_US_USMODE_SWHSH EQU( 0xC );
+-( USART ) Software Handshaking
+AT91C_US_CLKS EQU( 0x3 << 4 );
+-( USART ) Clock Selection ( Baud Rate generator Input Clock
+                             AT91C_US_CLKS_CLOCK EQU( 0x0 << 4 );
+                             -( USART ) Clock
+                             AT91C_US_CLKS_FDIV1 EQU( 0x1 << 4 );
+                             -( USART ) fdiv1
+                             AT91C_US_CLKS_SLOW EQU( 0x2 << 4 );
+                             -( USART ) slow_clock( ARM )
+                             AT91C_US_CLKS_EXT EQU( 0x3 << 4 );
+                             -( USART ) External( SCK )
+                             AT91C_US_CHRL EQU( 0x3 << 6 );
+                             -( USART ) Clock Selection ( Baud Rate generator Input Clock
+                                                          AT91C_US_CHRL_5_BITS EQU( 0x0 << 6 );
+                                                          -( USART ) Character Length : 5 bits
+                                                          AT91C_US_CHRL_6_BITS EQU( 0x1 << 6 );
+                                                          -( USART ) Character Length : 6 bits
+                                                          AT91C_US_CHRL_7_BITS EQU( 0x2 << 6 );
+                                                          -( USART ) Character Length : 7 bits
+                                                          AT91C_US_CHRL_8_BITS EQU( 0x3 << 6 );
+                                                          -( USART ) Character Length : 8 bits
+                                                          AT91C_US_SYNC EQU( 0x1 << 8 );
+                                                          -( USART ) Synchronous Mode Select
+                                                          AT91C_US_NBSTOP EQU( 0x3 << 12 );
+                                                          -( USART ) Number of Stop bits
+                                                          AT91C_US_NBSTOP_1_BIT EQU( 0x0 << 12 );
+                                                          -( USART ) 1 stop bit
+                                                          AT91C_US_NBSTOP_15_BIT EQU( 0x1 << 12 );
+                                                          -( USART ) Asynchronous( SYNC = 0 ) 2 stop bits Synchronous( SYNC = 1 ) 2 stop bits
+                                                          AT91C_US_NBSTOP_2_BIT EQU( 0x2 << 12 );
+                                                          -( USART ) 2 stop bits
+                                                          AT91C_US_MSBF EQU( 0x1 << 16 );
+                                                          -( USART ) Bit Order
+                                                          AT91C_US_MODE9 EQU( 0x1 << 17 );
+                                                          -( USART ) 9 - bit Character length
+                                                          AT91C_US_CKLO EQU( 0x1 << 18 );
+                                                          -( USART ) Clock Output Select
+                                                          AT91C_US_OVER EQU( 0x1 << 19 );
+                                                          -( USART ) Over Sampling Mode
+                                                          AT91C_US_INACK EQU( 0x1 << 20 );
+                                                          -( USART ) Inhibit Non Acknowledge
+                                                          AT91C_US_DSNACK EQU( 0x1 << 21 );
+                                                          -( USART ) Disable Successive NACK
+                                                          AT91C_US_MAX_ITER EQU( 0x1 << 24 );
+                                                          -( USART ) Number of Repetitions
+                                                          AT91C_US_FILTER EQU( 0x1 << 28 );
+                                                          -( USART ) Receive Line Filter
+/* - -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- */
+                                                          AT91C_US_RXBRK EQU( 0x1 << 2 );
+                                                          -( USART ) Break Received / End of Break
+                                                          AT91C_US_TIMEOUT EQU( 0x1 << 8 );
+                                                          -( USART ) Receiver Time - out
+                                                          AT91C_US_ITERATION EQU( 0x1 << 10 );
+                                                          -( USART ) Max number of Repetitions Reached
+                                                          AT91C_US_NACK EQU( 0x1 << 13 );
+                                                          -( USART ) Non Acknowledge
+                                                          AT91C_US_RIIC EQU( 0x1 << 16 );
+                                                          -( USART ) Ring INdicator Input Change Flag
+                                                          AT91C_US_DSRIC EQU( 0x1 << 17 );
+                                                          -( USART ) Data Set Ready Input Change Flag
+                                                          AT91C_US_DCDIC EQU( 0x1 << 18 );
+                                                          -( USART ) Data Carrier Flag
+                                                          AT91C_US_CTSIC EQU( 0x1 << 19 );
+                                                          -( USART ) Clear To Send Input Change Flag
+/* - -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- */
+/* - -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- */
+/* - -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- */
+                                                          AT91C_US_RI EQU( 0x1 << 20 );
+                                                          -( USART ) Image of RI Input
+                                                          AT91C_US_DSR EQU( 0x1 << 21 );
+                                                          -( USART ) Image of DSR Input
+                                                          AT91C_US_DCD EQU( 0x1 << 22 );
+                                                          -( USART ) Image of DCD Input
+                                                          AT91C_US_CTS EQU( 0x1 << 23 );
+                                                          -( USART ) Image of CTS Input
 
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Ethernet MAC 10/100
-// - *****************************************************************************
-// - -------- EMAC_NCR : (EMAC Offset: 0x0)  --------
-AT91C_EMAC_LB             EQU (0x1 <<  0) ;- (EMAC) Loopback. Optional. When set, loopback signal is at high level.
-AT91C_EMAC_LLB            EQU (0x1 <<  1) ;- (EMAC) Loopback local.
-AT91C_EMAC_RE             EQU (0x1 <<  2) ;- (EMAC) Receive enable.
-AT91C_EMAC_TE             EQU (0x1 <<  3) ;- (EMAC) Transmit enable.
-AT91C_EMAC_MPE            EQU (0x1 <<  4) ;- (EMAC) Management port enable.
-AT91C_EMAC_CLRSTAT        EQU (0x1 <<  5) ;- (EMAC) Clear statistics registers.
-AT91C_EMAC_INCSTAT        EQU (0x1 <<  6) ;- (EMAC) Increment statistics registers.
-AT91C_EMAC_WESTAT         EQU (0x1 <<  7) ;- (EMAC) Write enable for statistics registers.
-AT91C_EMAC_BP             EQU (0x1 <<  8) ;- (EMAC) Back pressure.
-AT91C_EMAC_TSTART         EQU (0x1 <<  9) ;- (EMAC) Start Transmission.
-AT91C_EMAC_THALT          EQU (0x1 << 10) ;- (EMAC) Transmission Halt.
-AT91C_EMAC_TPFR           EQU (0x1 << 11) ;- (EMAC) Transmit pause frame
-AT91C_EMAC_TZQ            EQU (0x1 << 12) ;- (EMAC) Transmit zero quantum pause frame
-// - -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register --------
-AT91C_EMAC_SPD            EQU (0x1 <<  0) ;- (EMAC) Speed.
-AT91C_EMAC_FD             EQU (0x1 <<  1) ;- (EMAC) Full duplex.
-AT91C_EMAC_JFRAME         EQU (0x1 <<  3) ;- (EMAC) Jumbo Frames.
-AT91C_EMAC_CAF            EQU (0x1 <<  4) ;- (EMAC) Copy all frames.
-AT91C_EMAC_NBC            EQU (0x1 <<  5) ;- (EMAC) No broadcast.
-AT91C_EMAC_MTI            EQU (0x1 <<  6) ;- (EMAC) Multicast hash event enable
-AT91C_EMAC_UNI            EQU (0x1 <<  7) ;- (EMAC) Unicast hash enable.
-AT91C_EMAC_BIG            EQU (0x1 <<  8) ;- (EMAC) Receive 1522 bytes.
-AT91C_EMAC_EAE            EQU (0x1 <<  9) ;- (EMAC) External address match enable.
-AT91C_EMAC_CLK            EQU (0x3 << 10) ;- (EMAC)
-AT91C_EMAC_CLK_HCLK_8     EQU (0x0 << 10) ;- (EMAC) HCLK divided by 8
-AT91C_EMAC_CLK_HCLK_16    EQU (0x1 << 10) ;- (EMAC) HCLK divided by 16
-AT91C_EMAC_CLK_HCLK_32    EQU (0x2 << 10) ;- (EMAC) HCLK divided by 32
-AT91C_EMAC_CLK_HCLK_64    EQU (0x3 << 10) ;- (EMAC) HCLK divided by 64
-AT91C_EMAC_RTY            EQU (0x1 << 12) ;- (EMAC)
-AT91C_EMAC_PAE            EQU (0x1 << 13) ;- (EMAC)
-AT91C_EMAC_RBOF           EQU (0x3 << 14) ;- (EMAC)
-AT91C_EMAC_RBOF_OFFSET_0  EQU (0x0 << 14) ;- (EMAC) no offset from start of receive buffer
-AT91C_EMAC_RBOF_OFFSET_1  EQU (0x1 << 14) ;- (EMAC) one byte offset from start of receive buffer
-AT91C_EMAC_RBOF_OFFSET_2  EQU (0x2 << 14) ;- (EMAC) two bytes offset from start of receive buffer
-AT91C_EMAC_RBOF_OFFSET_3  EQU (0x3 << 14) ;- (EMAC) three bytes offset from start of receive buffer
-AT91C_EMAC_RLCE           EQU (0x1 << 16) ;- (EMAC) Receive Length field Checking Enable
-AT91C_EMAC_DRFCS          EQU (0x1 << 17) ;- (EMAC) Discard Receive FCS
-AT91C_EMAC_EFRHD          EQU (0x1 << 18) ;- (EMAC)
-AT91C_EMAC_IRXFCS         EQU (0x1 << 19) ;- (EMAC) Ignore RX FCS
-// - -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register --------
-AT91C_EMAC_LINKR          EQU (0x1 <<  0) ;- (EMAC)
-AT91C_EMAC_MDIO           EQU (0x1 <<  1) ;- (EMAC)
-AT91C_EMAC_IDLE           EQU (0x1 <<  2) ;- (EMAC)
-// - -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register --------
-AT91C_EMAC_UBR            EQU (0x1 <<  0) ;- (EMAC)
-AT91C_EMAC_COL            EQU (0x1 <<  1) ;- (EMAC)
-AT91C_EMAC_RLES           EQU (0x1 <<  2) ;- (EMAC)
-AT91C_EMAC_TGO            EQU (0x1 <<  3) ;- (EMAC) Transmit Go
-AT91C_EMAC_BEX            EQU (0x1 <<  4) ;- (EMAC) Buffers exhausted mid frame
-AT91C_EMAC_COMP           EQU (0x1 <<  5) ;- (EMAC)
-AT91C_EMAC_UND            EQU (0x1 <<  6) ;- (EMAC)
-// - -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register --------
-AT91C_EMAC_BNA            EQU (0x1 <<  0) ;- (EMAC)
-AT91C_EMAC_REC            EQU (0x1 <<  1) ;- (EMAC)
-AT91C_EMAC_OVR            EQU (0x1 <<  2) ;- (EMAC)
-// - -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register --------
-AT91C_EMAC_MFD            EQU (0x1 <<  0) ;- (EMAC)
-AT91C_EMAC_RCOMP          EQU (0x1 <<  1) ;- (EMAC)
-AT91C_EMAC_RXUBR          EQU (0x1 <<  2) ;- (EMAC)
-AT91C_EMAC_TXUBR          EQU (0x1 <<  3) ;- (EMAC)
-AT91C_EMAC_TUNDR          EQU (0x1 <<  4) ;- (EMAC)
-AT91C_EMAC_RLEX           EQU (0x1 <<  5) ;- (EMAC)
-AT91C_EMAC_TXERR          EQU (0x1 <<  6) ;- (EMAC)
-AT91C_EMAC_TCOMP          EQU (0x1 <<  7) ;- (EMAC)
-AT91C_EMAC_LINK           EQU (0x1 <<  9) ;- (EMAC)
-AT91C_EMAC_ROVR           EQU (0x1 << 10) ;- (EMAC)
-AT91C_EMAC_HRESP          EQU (0x1 << 11) ;- (EMAC)
-AT91C_EMAC_PFRE           EQU (0x1 << 12) ;- (EMAC)
-AT91C_EMAC_PTZ            EQU (0x1 << 13) ;- (EMAC)
-// - -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register --------
-// - -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register --------
-// - -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register --------
-// - -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register --------
-AT91C_EMAC_DATA           EQU (0xFFFF <<  0) ;- (EMAC)
-AT91C_EMAC_CODE           EQU (0x3 << 16) ;- (EMAC)
-AT91C_EMAC_REGA           EQU (0x1F << 18) ;- (EMAC)
-AT91C_EMAC_PHYA           EQU (0x1F << 23) ;- (EMAC)
-AT91C_EMAC_RW             EQU (0x3 << 28) ;- (EMAC)
-AT91C_EMAC_SOF            EQU (0x3 << 30) ;- (EMAC)
-// - -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register --------
-AT91C_EMAC_RMII           EQU (0x1 <<  0) ;- (EMAC) Reduce MII
-// - -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register --------
-AT91C_EMAC_IP             EQU (0xFFFF <<  0) ;- (EMAC) ARP request IP address
-AT91C_EMAC_MAG            EQU (0x1 << 16) ;- (EMAC) Magic packet event enable
-AT91C_EMAC_ARP            EQU (0x1 << 17) ;- (EMAC) ARP request event enable
-AT91C_EMAC_SA1            EQU (0x1 << 18) ;- (EMAC) Specific address register 1 event enable
-// - -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register --------
-AT91C_EMAC_REVREF         EQU (0xFFFF <<  0) ;- (EMAC)
-AT91C_EMAC_PARTREF        EQU (0xFFFF << 16) ;- (EMAC)
+/* - ***************************************************************************** */
+/* -              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface */
+/* - ***************************************************************************** */
+/* - -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- */
+                                                          AT91C_SSC_RXEN EQU( 0x1 << 0 );
+                                                          -( SSC ) Receive Enable
+                                                          AT91C_SSC_RXDIS EQU( 0x1 << 1 );
+                                                          -( SSC ) Receive Disable
+                                                          AT91C_SSC_TXEN EQU( 0x1 << 8 );
+                                                          -( SSC ) Transmit Enable
+                                                          AT91C_SSC_TXDIS EQU( 0x1 << 9 );
+                                                          -( SSC ) Transmit Disable
+                                                          AT91C_SSC_SWRST EQU( 0x1 << 15 );
+                                                          -( SSC ) Software Reset
+/* - -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- */
+                                                          AT91C_SSC_CKS EQU( 0x3 << 0 );
+                                                          -( SSC ) Receive / Transmit Clock Selection
+                                                          AT91C_SSC_CKS_DIV EQU( 0x0 );
+                                                          -( SSC ) Divided Clock
+                                                          AT91C_SSC_CKS_TK EQU( 0x1 );
+                                                          -( SSC ) TK Clock signal
+                                                          AT91C_SSC_CKS_RK EQU( 0x2 );
+                                                          -( SSC ) RK pin
+                                                          AT91C_SSC_CKO EQU( 0x7 << 2 );
+                                                          -( SSC ) Receive / Transmit Clock Output Mode Selection
+                                                          AT91C_SSC_CKO_NONE EQU( 0x0 << 2 );
+                                                          -( SSC ) Receive / Transmit Clock Output Mode:None RK pin: Input - only
+                                                          AT91C_SSC_CKO_CONTINUOUS EQU( 0x1 << 2 );
+                                                          -( SSC ) Continuous Receive / Transmit Clock RK pin:Output
+                                                          AT91C_SSC_CKO_DATA_TX EQU( 0x2 << 2 );
+                                                          -( SSC ) Receive / Transmit Clock only during data transfers RK pin:Output
+                                                          AT91C_SSC_CKI EQU( 0x1 << 5 );
+                                                          -( SSC ) Receive / Transmit Clock Inversion
+                                                          AT91C_SSC_START EQU( 0xF << 8 );
+                                                          -( SSC ) Receive / Transmit Start Selection
+                                                          AT91C_SSC_START_CONTINUOUS EQU( 0x0 << 8 );
+                                                          -( SSC ) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
+                                                             AT91C_SSC_START_TX EQU( 0x1 << 8 );
+                                                          -( SSC ) Transmit / Receive start
+                                                          AT91C_SSC_START_LOW_RF EQU( 0x2 << 8 );
+                                                          -( SSC ) Detection of a low level on RF input
+                                                          AT91C_SSC_START_HIGH_RF EQU( 0x3 << 8 );
+                                                          -( SSC ) Detection of a high level on RF input
+                                                          AT91C_SSC_START_FALL_RF EQU( 0x4 << 8 );
+                                                          -( SSC ) Detection of a falling edge on RF input
+                                                          AT91C_SSC_START_RISE_RF EQU( 0x5 << 8 );
+                                                          -( SSC ) Detection of a rising edge on RF input
+                                                          AT91C_SSC_START_LEVEL_RF EQU( 0x6 << 8 );
+                                                          -( SSC ) Detection of any level change on RF input
+                                                          AT91C_SSC_START_EDGE_RF EQU( 0x7 << 8 );
+                                                          -( SSC ) Detection of any edge on RF input
+                                                          AT91C_SSC_START_0 EQU( 0x8 << 8 );
+                                                          -( SSC ) Compare 0
+                                                          AT91C_SSC_STTDLY EQU( 0xFF << 16 );
+                                                          -( SSC ) Receive / Transmit Start Delay
+                                                          AT91C_SSC_PERIOD EQU( 0xFF << 24 );
+                                                          -( SSC ) Receive / Transmit Period Divider Selection
+/* - -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- */
+                                                          AT91C_SSC_DATLEN EQU( 0x1F << 0 );
+                                                          -( SSC ) Data Length
+                                                          AT91C_SSC_LOOP EQU( 0x1 << 5 );
+                                                          -( SSC ) Loop Mode
+                                                          AT91C_SSC_MSBF EQU( 0x1 << 7 );
+                                                          -( SSC ) Most Significant Bit First
+                                                          AT91C_SSC_DATNB EQU( 0xF << 8 );
+                                                          -( SSC ) Data Number per Frame
+                                                          AT91C_SSC_FSLEN EQU( 0xF << 16 );
+                                                          -( SSC ) Receive / Transmit Frame Sync length
+                                                          AT91C_SSC_FSOS EQU( 0x7 << 20 );
+                                                          -( SSC ) Receive / Transmit Frame Sync Output Selection
+                                                          AT91C_SSC_FSOS_NONE EQU( 0x0 << 20 );
+                                                          -( SSC ) Selected Receive / Transmit Frame Sync Signal:None RK pin Input - only
+                                                          AT91C_SSC_FSOS_NEGATIVE EQU( 0x1 << 20 );
+                                                          -( SSC ) Selected Receive / Transmit Frame Sync Signal:Negative Pulse
+                                                          AT91C_SSC_FSOS_POSITIVE EQU( 0x2 << 20 );
+                                                          -( SSC ) Selected Receive / Transmit Frame Sync Signal:Positive Pulse
+                                                          AT91C_SSC_FSOS_LOW EQU( 0x3 << 20 );
+                                                          -( SSC ) Selected Receive / Transmit Frame Sync Signal:Driver Low during data transfer
+                                                          AT91C_SSC_FSOS_HIGH EQU( 0x4 << 20 );
+                                                          -( SSC ) Selected Receive / Transmit Frame Sync Signal:Driver High during data transfer
+                                                          AT91C_SSC_FSOS_TOGGLE EQU( 0x5 << 20 );
+                                                          -( SSC ) Selected Receive / Transmit Frame Sync Signal:Toggling at each start of data transfer
+                                                          AT91C_SSC_FSEDGE EQU( 0x1 << 24 );
+                                                          -( SSC ) Frame Sync Edge Detection
+/* - -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- */
+/* - -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- */
+                                                          AT91C_SSC_DATDEF EQU( 0x1 << 5 );
+                                                          -( SSC ) Data Default Value
+                                                          AT91C_SSC_FSDEN EQU( 0x1 << 23 );
+                                                          -( SSC ) Frame Sync Data Enable
+/* - -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- */
+                                                          AT91C_SSC_TXRDY EQU( 0x1 << 0 );
+                                                          -( SSC ) Transmit Ready
+                                                          AT91C_SSC_TXEMPTY EQU( 0x1 << 1 );
+                                                          -( SSC ) Transmit Empty
+                                                          AT91C_SSC_ENDTX EQU( 0x1 << 2 );
+                                                          -( SSC ) End Of Transmission
+                                                          AT91C_SSC_TXBUFE EQU( 0x1 << 3 );
+                                                          -( SSC ) Transmit Buffer Empty
+                                                          AT91C_SSC_RXRDY EQU( 0x1 << 4 );
+                                                          -( SSC ) Receive Ready
+                                                          AT91C_SSC_OVRUN EQU( 0x1 << 5 );
+                                                          -( SSC ) Receive Overrun
+                                                          AT91C_SSC_ENDRX EQU( 0x1 << 6 );
+                                                          -( SSC ) End of Reception
+                                                          AT91C_SSC_RXBUFF EQU( 0x1 << 7 );
+                                                          -( SSC ) Receive Buffer Full
+                                                          AT91C_SSC_TXSYN EQU( 0x1 << 10 );
+                                                          -( SSC ) Transmit Sync
+                                                          AT91C_SSC_RXSYN EQU( 0x1 << 11 );
+                                                          -( SSC ) Receive Sync
+                                                          AT91C_SSC_TXENA EQU( 0x1 << 16 );
+                                                          -( SSC ) Transmit Enable
+                                                          AT91C_SSC_RXENA EQU( 0x1 << 17 );
+                                                          -( SSC ) Receive Enable
+/* - -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- */
+/* - -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- */
+/* - -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- */
 
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
-// - *****************************************************************************
-// - -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
-AT91C_ADC_SWRST           EQU (0x1 <<  0) ;- (ADC) Software Reset
-AT91C_ADC_START           EQU (0x1 <<  1) ;- (ADC) Start Conversion
-// - -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
-AT91C_ADC_TRGEN           EQU (0x1 <<  0) ;- (ADC) Trigger Enable
-AT91C_ADC_TRGEN_DIS       EQU (0x0) ;- (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
-AT91C_ADC_TRGEN_EN        EQU (0x1) ;- (ADC) Hardware trigger selected by TRGSEL field is enabled.
-AT91C_ADC_TRGSEL          EQU (0x7 <<  1) ;- (ADC) Trigger Selection
-AT91C_ADC_TRGSEL_TIOA0    EQU (0x0 <<  1) ;- (ADC) Selected TRGSEL = TIAO0
-AT91C_ADC_TRGSEL_TIOA1    EQU (0x1 <<  1) ;- (ADC) Selected TRGSEL = TIAO1
-AT91C_ADC_TRGSEL_TIOA2    EQU (0x2 <<  1) ;- (ADC) Selected TRGSEL = TIAO2
-AT91C_ADC_TRGSEL_TIOA3    EQU (0x3 <<  1) ;- (ADC) Selected TRGSEL = TIAO3
-AT91C_ADC_TRGSEL_TIOA4    EQU (0x4 <<  1) ;- (ADC) Selected TRGSEL = TIAO4
-AT91C_ADC_TRGSEL_TIOA5    EQU (0x5 <<  1) ;- (ADC) Selected TRGSEL = TIAO5
-AT91C_ADC_TRGSEL_EXT      EQU (0x6 <<  1) ;- (ADC) Selected TRGSEL = External Trigger
-AT91C_ADC_LOWRES          EQU (0x1 <<  4) ;- (ADC) Resolution.
-AT91C_ADC_LOWRES_10_BIT   EQU (0x0 <<  4) ;- (ADC) 10-bit resolution
-AT91C_ADC_LOWRES_8_BIT    EQU (0x1 <<  4) ;- (ADC) 8-bit resolution
-AT91C_ADC_SLEEP           EQU (0x1 <<  5) ;- (ADC) Sleep Mode
-AT91C_ADC_SLEEP_NORMAL_MODE EQU (0x0 <<  5) ;- (ADC) Normal Mode
-AT91C_ADC_SLEEP_MODE      EQU (0x1 <<  5) ;- (ADC) Sleep Mode
-AT91C_ADC_PRESCAL         EQU (0x3F <<  8) ;- (ADC) Prescaler rate selection
-AT91C_ADC_STARTUP         EQU (0x1F << 16) ;- (ADC) Startup Time
-AT91C_ADC_SHTIM           EQU (0xF << 24) ;- (ADC) Sample & Hold Time
-// - --------   ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
-AT91C_ADC_CH0             EQU (0x1 <<  0) ;- (ADC) Channel 0
-AT91C_ADC_CH1             EQU (0x1 <<  1) ;- (ADC) Channel 1
-AT91C_ADC_CH2             EQU (0x1 <<  2) ;- (ADC) Channel 2
-AT91C_ADC_CH3             EQU (0x1 <<  3) ;- (ADC) Channel 3
-AT91C_ADC_CH4             EQU (0x1 <<  4) ;- (ADC) Channel 4
-AT91C_ADC_CH5             EQU (0x1 <<  5) ;- (ADC) Channel 5
-AT91C_ADC_CH6             EQU (0x1 <<  6) ;- (ADC) Channel 6
-AT91C_ADC_CH7             EQU (0x1 <<  7) ;- (ADC) Channel 7
-// - --------   ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
-// - --------   ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
-// - -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
-AT91C_ADC_EOC0            EQU (0x1 <<  0) ;- (ADC) End of Conversion
-AT91C_ADC_EOC1            EQU (0x1 <<  1) ;- (ADC) End of Conversion
-AT91C_ADC_EOC2            EQU (0x1 <<  2) ;- (ADC) End of Conversion
-AT91C_ADC_EOC3            EQU (0x1 <<  3) ;- (ADC) End of Conversion
-AT91C_ADC_EOC4            EQU (0x1 <<  4) ;- (ADC) End of Conversion
-AT91C_ADC_EOC5            EQU (0x1 <<  5) ;- (ADC) End of Conversion
-AT91C_ADC_EOC6            EQU (0x1 <<  6) ;- (ADC) End of Conversion
-AT91C_ADC_EOC7            EQU (0x1 <<  7) ;- (ADC) End of Conversion
-AT91C_ADC_OVRE0           EQU (0x1 <<  8) ;- (ADC) Overrun Error
-AT91C_ADC_OVRE1           EQU (0x1 <<  9) ;- (ADC) Overrun Error
-AT91C_ADC_OVRE2           EQU (0x1 << 10) ;- (ADC) Overrun Error
-AT91C_ADC_OVRE3           EQU (0x1 << 11) ;- (ADC) Overrun Error
-AT91C_ADC_OVRE4           EQU (0x1 << 12) ;- (ADC) Overrun Error
-AT91C_ADC_OVRE5           EQU (0x1 << 13) ;- (ADC) Overrun Error
-AT91C_ADC_OVRE6           EQU (0x1 << 14) ;- (ADC) Overrun Error
-AT91C_ADC_OVRE7           EQU (0x1 << 15) ;- (ADC) Overrun Error
-AT91C_ADC_DRDY            EQU (0x1 << 16) ;- (ADC) Data Ready
-AT91C_ADC_GOVRE           EQU (0x1 << 17) ;- (ADC) General Overrun
-AT91C_ADC_ENDRX           EQU (0x1 << 18) ;- (ADC) End of Receiver Transfer
-AT91C_ADC_RXBUFF          EQU (0x1 << 19) ;- (ADC) RXBUFF Interrupt
-// - -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
-AT91C_ADC_LDATA           EQU (0x3FF <<  0) ;- (ADC) Last Data Converted
-// - -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
-// - -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
-// - -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
-// - -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
-AT91C_ADC_DATA            EQU (0x3FF <<  0) ;- (ADC) Converted Data
-// - -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
-// - -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
-// - -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
-// - -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
-// - -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
-// - -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
-// - -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
+/* - ***************************************************************************** */
+/* -              SOFTWARE API DEFINITION  FOR Two-wire Interface */
+/* - ***************************************************************************** */
+/* - -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- */
+                                                          AT91C_TWI_START EQU( 0x1 << 0 );
+                                                          -( TWI ) Send a START Condition
+                                                          AT91C_TWI_STOP EQU( 0x1 << 1 );
+                                                          -( TWI ) Send a STOP Condition
+                                                          AT91C_TWI_MSEN EQU( 0x1 << 2 );
+                                                          -( TWI ) TWI Master Transfer Enabled
+                                                          AT91C_TWI_MSDIS EQU( 0x1 << 3 );
+                                                          -( TWI ) TWI Master Transfer Disabled
+                                                          AT91C_TWI_SWRST EQU( 0x1 << 7 );
+                                                          -( TWI ) Software Reset
+/* - -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- */
+                                                          AT91C_TWI_IADRSZ EQU( 0x3 << 8 );
+                                                          -( TWI ) Internal Device Address Size
+                                                          AT91C_TWI_IADRSZ_NO EQU( 0x0 << 8 );
+                                                          -( TWI ) No internal device address
+                                                          AT91C_TWI_IADRSZ_1_BYTE EQU( 0x1 << 8 );
+                                                          -( TWI ) One - byte internal device address
+                                                          AT91C_TWI_IADRSZ_2_BYTE EQU( 0x2 << 8 );
+                                                          -( TWI ) Two - byte internal device address
+                                                          AT91C_TWI_IADRSZ_3_BYTE EQU( 0x3 << 8 );
+                                                          -( TWI ) Three - byte internal device address
+                                                          AT91C_TWI_MREAD EQU( 0x1 << 12 );
+                                                          -( TWI ) Master Read Direction
+                                                          AT91C_TWI_DADR EQU( 0x7F << 16 );
+                                                          -( TWI ) Device Address
+/* - -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- */
+                                                          AT91C_TWI_CLDIV EQU( 0xFF << 0 );
+                                                          -( TWI ) Clock Low Divider
+                                                          AT91C_TWI_CHDIV EQU( 0xFF << 8 );
+                                                          -( TWI ) Clock High Divider
+                                                          AT91C_TWI_CKDIV EQU( 0x7 << 16 );
+                                                          -( TWI ) Clock Divider
+/* - -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- */
+                                                          AT91C_TWI_TXCOMP EQU( 0x1 << 0 );
+                                                          -( TWI ) Transmission Completed
+                                                          AT91C_TWI_RXRDY EQU( 0x1 << 1 );
+                                                          -( TWI ) Receive holding register ReaDY
+                                                          AT91C_TWI_TXRDY EQU( 0x1 << 2 );
+                                                          -( TWI ) Transmit holding register ReaDY
+                                                          AT91C_TWI_OVRE EQU( 0x1 << 6 );
+                                                          -( TWI ) Overrun Error
+                                                          AT91C_TWI_UNRE EQU( 0x1 << 7 );
+                                                          -( TWI ) Underrun Error
+                                                          AT91C_TWI_NACK EQU( 0x1 << 8 );
+                                                          -( TWI ) Not Acknowledged
+/* - -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- */
+/* - -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- */
+/* - -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- */
 
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Advanced  Encryption Standard
-// - *****************************************************************************
-// - -------- AES_CR : (AES Offset: 0x0) Control Register --------
-AT91C_AES_START           EQU (0x1 <<  0) ;- (AES) Starts Processing
-AT91C_AES_SWRST           EQU (0x1 <<  8) ;- (AES) Software Reset
-AT91C_AES_LOADSEED        EQU (0x1 << 16) ;- (AES) Random Number Generator Seed Loading
-// - -------- AES_MR : (AES Offset: 0x4) Mode Register --------
-AT91C_AES_CIPHER          EQU (0x1 <<  0) ;- (AES) Processing Mode
-AT91C_AES_PROCDLY         EQU (0xF <<  4) ;- (AES) Processing Delay
-AT91C_AES_SMOD            EQU (0x3 <<  8) ;- (AES) Start Mode
-AT91C_AES_SMOD_MANUAL     EQU (0x0 <<  8) ;- (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.
-AT91C_AES_SMOD_AUTO       EQU (0x1 <<  8) ;- (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).
-AT91C_AES_SMOD_PDC        EQU (0x2 <<  8) ;- (AES) PDC Mode (cf datasheet).
-AT91C_AES_OPMOD           EQU (0x7 << 12) ;- (AES) Operation Mode
-AT91C_AES_OPMOD_ECB       EQU (0x0 << 12) ;- (AES) ECB Electronic CodeBook mode.
-AT91C_AES_OPMOD_CBC       EQU (0x1 << 12) ;- (AES) CBC Cipher Block Chaining mode.
-AT91C_AES_OPMOD_OFB       EQU (0x2 << 12) ;- (AES) OFB Output Feedback mode.
-AT91C_AES_OPMOD_CFB       EQU (0x3 << 12) ;- (AES) CFB Cipher Feedback mode.
-AT91C_AES_OPMOD_CTR       EQU (0x4 << 12) ;- (AES) CTR Counter mode.
-AT91C_AES_LOD             EQU (0x1 << 15) ;- (AES) Last Output Data Mode
-AT91C_AES_CFBS            EQU (0x7 << 16) ;- (AES) Cipher Feedback Data Size
-AT91C_AES_CFBS_128_BIT    EQU (0x0 << 16) ;- (AES) 128-bit.
-AT91C_AES_CFBS_64_BIT     EQU (0x1 << 16) ;- (AES) 64-bit.
-AT91C_AES_CFBS_32_BIT     EQU (0x2 << 16) ;- (AES) 32-bit.
-AT91C_AES_CFBS_16_BIT     EQU (0x3 << 16) ;- (AES) 16-bit.
-AT91C_AES_CFBS_8_BIT      EQU (0x4 << 16) ;- (AES) 8-bit.
-AT91C_AES_CKEY            EQU (0xF << 20) ;- (AES) Countermeasure Key
-AT91C_AES_CTYPE           EQU (0x1F << 24) ;- (AES) Countermeasure Type
-AT91C_AES_CTYPE_TYPE1_EN  EQU (0x1 << 24) ;- (AES) Countermeasure type 1 is enabled.
-AT91C_AES_CTYPE_TYPE2_EN  EQU (0x2 << 24) ;- (AES) Countermeasure type 2 is enabled.
-AT91C_AES_CTYPE_TYPE3_EN  EQU (0x4 << 24) ;- (AES) Countermeasure type 3 is enabled.
-AT91C_AES_CTYPE_TYPE4_EN  EQU (0x8 << 24) ;- (AES) Countermeasure type 4 is enabled.
-AT91C_AES_CTYPE_TYPE5_EN  EQU (0x10 << 24) ;- (AES) Countermeasure type 5 is enabled.
-// - -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register --------
-AT91C_AES_DATRDY          EQU (0x1 <<  0) ;- (AES) DATRDY
-AT91C_AES_ENDRX           EQU (0x1 <<  1) ;- (AES) PDC Read Buffer End
-AT91C_AES_ENDTX           EQU (0x1 <<  2) ;- (AES) PDC Write Buffer End
-AT91C_AES_RXBUFF          EQU (0x1 <<  3) ;- (AES) PDC Read Buffer Full
-AT91C_AES_TXBUFE          EQU (0x1 <<  4) ;- (AES) PDC Write Buffer Empty
-AT91C_AES_URAD            EQU (0x1 <<  8) ;- (AES) Unspecified Register Access Detection
-// - -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register --------
-// - -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register --------
-// - -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register --------
-AT91C_AES_URAT            EQU (0x7 << 12) ;- (AES) Unspecified Register Access Type Status
-AT91C_AES_URAT_IN_DAT_WRITE_DATPROC EQU (0x0 << 12) ;- (AES) Input data register written during the data processing in PDC mode.
-AT91C_AES_URAT_OUT_DAT_READ_DATPROC EQU (0x1 << 12) ;- (AES) Output data register read during the data processing.
-AT91C_AES_URAT_MODEREG_WRITE_DATPROC EQU (0x2 << 12) ;- (AES) Mode register written during the data processing.
-AT91C_AES_URAT_OUT_DAT_READ_SUBKEY EQU (0x3 << 12) ;- (AES) Output data register read during the sub-keys generation.
-AT91C_AES_URAT_MODEREG_WRITE_SUBKEY EQU (0x4 << 12) ;- (AES) Mode register written during the sub-keys generation.
-AT91C_AES_URAT_WO_REG_READ EQU (0x5 << 12) ;- (AES) Write-only register read access.
+/* - ***************************************************************************** */
+/* -              SOFTWARE API DEFINITION  FOR PWMC Channel Interface */
+/* - ***************************************************************************** */
+/* - -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- */
+                                                          AT91C_PWMC_CPRE EQU( 0xF << 0 );
+                                                          -( PWMC_CH ) Channel Pre - scaler:PWMC_CLKx
+                                                          AT91C_PWMC_CPRE_MCK EQU( 0x0 );
+                                                          -( PWMC_CH )
+                                                          AT91C_PWMC_CPRE_MCKA EQU( 0xB );
+                                                          -( PWMC_CH )
+                                                          AT91C_PWMC_CPRE_MCKB EQU( 0xC );
+                                                          -( PWMC_CH )
+                                                          AT91C_PWMC_CALG EQU( 0x1 << 8 );
+                                                          -( PWMC_CH ) Channel Alignment
+                                                          AT91C_PWMC_CPOL EQU( 0x1 << 9 );
+                                                          -( PWMC_CH ) Channel Polarity
+                                                          AT91C_PWMC_CPD EQU( 0x1 << 10 );
+                                                          -( PWMC_CH ) Channel Update Period
+/* - -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- */
+                                                          AT91C_PWMC_CDTY EQU( 0x0 << 0 );
+                                                          -( PWMC_CH ) Channel Duty Cycle
+/* - -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- */
+                                                          AT91C_PWMC_CPRD EQU( 0x0 << 0 );
+                                                          -( PWMC_CH ) Channel Period
+/* - -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- */
+                                                          AT91C_PWMC_CCNT EQU( 0x0 << 0 );
+                                                          -( PWMC_CH ) Channel Counter
+/* - -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- */
+                                                          AT91C_PWMC_CUPD EQU( 0x0 << 0 );
+                                                          -( PWMC_CH ) Channel Update
 
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Triple Data Encryption Standard
-// - *****************************************************************************
-// - -------- TDES_CR : (TDES Offset: 0x0) Control Register --------
-AT91C_TDES_START          EQU (0x1 <<  0) ;- (TDES) Starts Processing
-AT91C_TDES_SWRST          EQU (0x1 <<  8) ;- (TDES) Software Reset
-// - -------- TDES_MR : (TDES Offset: 0x4) Mode Register --------
-AT91C_TDES_CIPHER         EQU (0x1 <<  0) ;- (TDES) Processing Mode
-AT91C_TDES_TDESMOD        EQU (0x1 <<  1) ;- (TDES) Single or Triple DES Mode
-AT91C_TDES_KEYMOD         EQU (0x1 <<  4) ;- (TDES) Key Mode
-AT91C_TDES_SMOD           EQU (0x3 <<  8) ;- (TDES) Start Mode
-AT91C_TDES_SMOD_MANUAL    EQU (0x0 <<  8) ;- (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.
-AT91C_TDES_SMOD_AUTO      EQU (0x1 <<  8) ;- (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).
-AT91C_TDES_SMOD_PDC       EQU (0x2 <<  8) ;- (TDES) PDC Mode (cf datasheet).
-AT91C_TDES_OPMOD          EQU (0x3 << 12) ;- (TDES) Operation Mode
-AT91C_TDES_OPMOD_ECB      EQU (0x0 << 12) ;- (TDES) ECB Electronic CodeBook mode.
-AT91C_TDES_OPMOD_CBC      EQU (0x1 << 12) ;- (TDES) CBC Cipher Block Chaining mode.
-AT91C_TDES_OPMOD_OFB      EQU (0x2 << 12) ;- (TDES) OFB Output Feedback mode.
-AT91C_TDES_OPMOD_CFB      EQU (0x3 << 12) ;- (TDES) CFB Cipher Feedback mode.
-AT91C_TDES_LOD            EQU (0x1 << 15) ;- (TDES) Last Output Data Mode
-AT91C_TDES_CFBS           EQU (0x3 << 16) ;- (TDES) Cipher Feedback Data Size
-AT91C_TDES_CFBS_64_BIT    EQU (0x0 << 16) ;- (TDES) 64-bit.
-AT91C_TDES_CFBS_32_BIT    EQU (0x1 << 16) ;- (TDES) 32-bit.
-AT91C_TDES_CFBS_16_BIT    EQU (0x2 << 16) ;- (TDES) 16-bit.
-AT91C_TDES_CFBS_8_BIT     EQU (0x3 << 16) ;- (TDES) 8-bit.
-// - -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register --------
-AT91C_TDES_DATRDY         EQU (0x1 <<  0) ;- (TDES) DATRDY
-AT91C_TDES_ENDRX          EQU (0x1 <<  1) ;- (TDES) PDC Read Buffer End
-AT91C_TDES_ENDTX          EQU (0x1 <<  2) ;- (TDES) PDC Write Buffer End
-AT91C_TDES_RXBUFF         EQU (0x1 <<  3) ;- (TDES) PDC Read Buffer Full
-AT91C_TDES_TXBUFE         EQU (0x1 <<  4) ;- (TDES) PDC Write Buffer Empty
-AT91C_TDES_URAD           EQU (0x1 <<  8) ;- (TDES) Unspecified Register Access Detection
-// - -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register --------
-// - -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register --------
-// - -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register --------
-AT91C_TDES_URAT           EQU (0x3 << 12) ;- (TDES) Unspecified Register Access Type Status
-AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC EQU (0x0 << 12) ;- (TDES) Input data register written during the data processing in PDC mode.
-AT91C_TDES_URAT_OUT_DAT_READ_DATPROC EQU (0x1 << 12) ;- (TDES) Output data register read during the data processing.
-AT91C_TDES_URAT_MODEREG_WRITE_DATPROC EQU (0x2 << 12) ;- (TDES) Mode register written during the data processing.
-AT91C_TDES_URAT_WO_REG_READ EQU (0x3 << 12) ;- (TDES) Write-only register read access.
+/* - ***************************************************************************** */
+/* -              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface */
+/* - ***************************************************************************** */
+/* - -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- */
+                                                          AT91C_PWMC_DIVA EQU( 0xFF << 0 );
+                                                          -( PWMC ) CLKA divide factor.
+                                                             AT91C_PWMC_PREA EQU( 0xF << 8 );
+                                                          -( PWMC ) Divider Input Clock Prescaler A
+                                                          AT91C_PWMC_PREA_MCK EQU( 0x0 << 8 );
+                                                          -( PWMC )
+                                                          AT91C_PWMC_DIVB EQU( 0xFF << 16 );
+                                                          -( PWMC ) CLKB divide factor.
+                                                             AT91C_PWMC_PREB EQU( 0xF << 24 );
+                                                          -( PWMC ) Divider Input Clock Prescaler B
+                                                          AT91C_PWMC_PREB_MCK EQU( 0x0 << 24 );
+                                                          -( PWMC )
+/* - -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- */
+                                                          AT91C_PWMC_CHID0 EQU( 0x1 << 0 );
+                                                          -( PWMC ) Channel ID 0
+                                                          AT91C_PWMC_CHID1 EQU( 0x1 << 1 );
+                                                          -( PWMC ) Channel ID 1
+                                                          AT91C_PWMC_CHID2 EQU( 0x1 << 2 );
+                                                          -( PWMC ) Channel ID 2
+                                                          AT91C_PWMC_CHID3 EQU( 0x1 << 3 );
+                                                          -( PWMC ) Channel ID 3
+/* - -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- */
+/* - -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- */
+/* - -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- */
+/* - -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- */
+/* - -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- */
+/* - -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- */
 
-// - *****************************************************************************
-// -               REGISTER ADDRESS DEFINITION FOR AT91SAM7X256
-// - *****************************************************************************
-// - ========== Register definition for SYS peripheral ==========
-// - ========== Register definition for AIC peripheral ==========
-AT91C_AIC_IVR             EQU (0xFFFFF100) ;- (AIC) IRQ Vector Register
-AT91C_AIC_SMR             EQU (0xFFFFF000) ;- (AIC) Source Mode Register
-AT91C_AIC_FVR             EQU (0xFFFFF104) ;- (AIC) FIQ Vector Register
-AT91C_AIC_DCR             EQU (0xFFFFF138) ;- (AIC) Debug Control Register (Protect)
-AT91C_AIC_EOICR           EQU (0xFFFFF130) ;- (AIC) End of Interrupt Command Register
-AT91C_AIC_SVR             EQU (0xFFFFF080) ;- (AIC) Source Vector Register
-AT91C_AIC_FFSR            EQU (0xFFFFF148) ;- (AIC) Fast Forcing Status Register
-AT91C_AIC_ICCR            EQU (0xFFFFF128) ;- (AIC) Interrupt Clear Command Register
-AT91C_AIC_ISR             EQU (0xFFFFF108) ;- (AIC) Interrupt Status Register
-AT91C_AIC_IMR             EQU (0xFFFFF110) ;- (AIC) Interrupt Mask Register
-AT91C_AIC_IPR             EQU (0xFFFFF10C) ;- (AIC) Interrupt Pending Register
-AT91C_AIC_FFER            EQU (0xFFFFF140) ;- (AIC) Fast Forcing Enable Register
-AT91C_AIC_IECR            EQU (0xFFFFF120) ;- (AIC) Interrupt Enable Command Register
-AT91C_AIC_ISCR            EQU (0xFFFFF12C) ;- (AIC) Interrupt Set Command Register
-AT91C_AIC_FFDR            EQU (0xFFFFF144) ;- (AIC) Fast Forcing Disable Register
-AT91C_AIC_CISR            EQU (0xFFFFF114) ;- (AIC) Core Interrupt Status Register
-AT91C_AIC_IDCR            EQU (0xFFFFF124) ;- (AIC) Interrupt Disable Command Register
-AT91C_AIC_SPU             EQU (0xFFFFF134) ;- (AIC) Spurious Vector Register
-// - ========== Register definition for PDC_DBGU peripheral ==========
-AT91C_DBGU_TCR            EQU (0xFFFFF30C) ;- (PDC_DBGU) Transmit Counter Register
-AT91C_DBGU_RNPR           EQU (0xFFFFF310) ;- (PDC_DBGU) Receive Next Pointer Register
-AT91C_DBGU_TNPR           EQU (0xFFFFF318) ;- (PDC_DBGU) Transmit Next Pointer Register
-AT91C_DBGU_TPR            EQU (0xFFFFF308) ;- (PDC_DBGU) Transmit Pointer Register
-AT91C_DBGU_RPR            EQU (0xFFFFF300) ;- (PDC_DBGU) Receive Pointer Register
-AT91C_DBGU_RCR            EQU (0xFFFFF304) ;- (PDC_DBGU) Receive Counter Register
-AT91C_DBGU_RNCR           EQU (0xFFFFF314) ;- (PDC_DBGU) Receive Next Counter Register
-AT91C_DBGU_PTCR           EQU (0xFFFFF320) ;- (PDC_DBGU) PDC Transfer Control Register
-AT91C_DBGU_PTSR           EQU (0xFFFFF324) ;- (PDC_DBGU) PDC Transfer Status Register
-AT91C_DBGU_TNCR           EQU (0xFFFFF31C) ;- (PDC_DBGU) Transmit Next Counter Register
-// - ========== Register definition for DBGU peripheral ==========
-AT91C_DBGU_EXID           EQU (0xFFFFF244) ;- (DBGU) Chip ID Extension Register
-AT91C_DBGU_BRGR           EQU (0xFFFFF220) ;- (DBGU) Baud Rate Generator Register
-AT91C_DBGU_IDR            EQU (0xFFFFF20C) ;- (DBGU) Interrupt Disable Register
-AT91C_DBGU_CSR            EQU (0xFFFFF214) ;- (DBGU) Channel Status Register
-AT91C_DBGU_CIDR           EQU (0xFFFFF240) ;- (DBGU) Chip ID Register
-AT91C_DBGU_MR             EQU (0xFFFFF204) ;- (DBGU) Mode Register
-AT91C_DBGU_IMR            EQU (0xFFFFF210) ;- (DBGU) Interrupt Mask Register
-AT91C_DBGU_CR             EQU (0xFFFFF200) ;- (DBGU) Control Register
-AT91C_DBGU_FNTR           EQU (0xFFFFF248) ;- (DBGU) Force NTRST Register
-AT91C_DBGU_THR            EQU (0xFFFFF21C) ;- (DBGU) Transmitter Holding Register
-AT91C_DBGU_RHR            EQU (0xFFFFF218) ;- (DBGU) Receiver Holding Register
-AT91C_DBGU_IER            EQU (0xFFFFF208) ;- (DBGU) Interrupt Enable Register
-// - ========== Register definition for PIOA peripheral ==========
-AT91C_PIOA_ODR            EQU (0xFFFFF414) ;- (PIOA) Output Disable Registerr
-AT91C_PIOA_SODR           EQU (0xFFFFF430) ;- (PIOA) Set Output Data Register
-AT91C_PIOA_ISR            EQU (0xFFFFF44C) ;- (PIOA) Interrupt Status Register
-AT91C_PIOA_ABSR           EQU (0xFFFFF478) ;- (PIOA) AB Select Status Register
-AT91C_PIOA_IER            EQU (0xFFFFF440) ;- (PIOA) Interrupt Enable Register
-AT91C_PIOA_PPUDR          EQU (0xFFFFF460) ;- (PIOA) Pull-up Disable Register
-AT91C_PIOA_IMR            EQU (0xFFFFF448) ;- (PIOA) Interrupt Mask Register
-AT91C_PIOA_PER            EQU (0xFFFFF400) ;- (PIOA) PIO Enable Register
-AT91C_PIOA_IFDR           EQU (0xFFFFF424) ;- (PIOA) Input Filter Disable Register
-AT91C_PIOA_OWDR           EQU (0xFFFFF4A4) ;- (PIOA) Output Write Disable Register
-AT91C_PIOA_MDSR           EQU (0xFFFFF458) ;- (PIOA) Multi-driver Status Register
-AT91C_PIOA_IDR            EQU (0xFFFFF444) ;- (PIOA) Interrupt Disable Register
-AT91C_PIOA_ODSR           EQU (0xFFFFF438) ;- (PIOA) Output Data Status Register
-AT91C_PIOA_PPUSR          EQU (0xFFFFF468) ;- (PIOA) Pull-up Status Register
-AT91C_PIOA_OWSR           EQU (0xFFFFF4A8) ;- (PIOA) Output Write Status Register
-AT91C_PIOA_BSR            EQU (0xFFFFF474) ;- (PIOA) Select B Register
-AT91C_PIOA_OWER           EQU (0xFFFFF4A0) ;- (PIOA) Output Write Enable Register
-AT91C_PIOA_IFER           EQU (0xFFFFF420) ;- (PIOA) Input Filter Enable Register
-AT91C_PIOA_PDSR           EQU (0xFFFFF43C) ;- (PIOA) Pin Data Status Register
-AT91C_PIOA_PPUER          EQU (0xFFFFF464) ;- (PIOA) Pull-up Enable Register
-AT91C_PIOA_OSR            EQU (0xFFFFF418) ;- (PIOA) Output Status Register
-AT91C_PIOA_ASR            EQU (0xFFFFF470) ;- (PIOA) Select A Register
-AT91C_PIOA_MDDR           EQU (0xFFFFF454) ;- (PIOA) Multi-driver Disable Register
-AT91C_PIOA_CODR           EQU (0xFFFFF434) ;- (PIOA) Clear Output Data Register
-AT91C_PIOA_MDER           EQU (0xFFFFF450) ;- (PIOA) Multi-driver Enable Register
-AT91C_PIOA_PDR            EQU (0xFFFFF404) ;- (PIOA) PIO Disable Register
-AT91C_PIOA_IFSR           EQU (0xFFFFF428) ;- (PIOA) Input Filter Status Register
-AT91C_PIOA_OER            EQU (0xFFFFF410) ;- (PIOA) Output Enable Register
-AT91C_PIOA_PSR            EQU (0xFFFFF408) ;- (PIOA) PIO Status Register
-// - ========== Register definition for PIOB peripheral ==========
-AT91C_PIOB_OWDR           EQU (0xFFFFF6A4) ;- (PIOB) Output Write Disable Register
-AT91C_PIOB_MDER           EQU (0xFFFFF650) ;- (PIOB) Multi-driver Enable Register
-AT91C_PIOB_PPUSR          EQU (0xFFFFF668) ;- (PIOB) Pull-up Status Register
-AT91C_PIOB_IMR            EQU (0xFFFFF648) ;- (PIOB) Interrupt Mask Register
-AT91C_PIOB_ASR            EQU (0xFFFFF670) ;- (PIOB) Select A Register
-AT91C_PIOB_PPUDR          EQU (0xFFFFF660) ;- (PIOB) Pull-up Disable Register
-AT91C_PIOB_PSR            EQU (0xFFFFF608) ;- (PIOB) PIO Status Register
-AT91C_PIOB_IER            EQU (0xFFFFF640) ;- (PIOB) Interrupt Enable Register
-AT91C_PIOB_CODR           EQU (0xFFFFF634) ;- (PIOB) Clear Output Data Register
-AT91C_PIOB_OWER           EQU (0xFFFFF6A0) ;- (PIOB) Output Write Enable Register
-AT91C_PIOB_ABSR           EQU (0xFFFFF678) ;- (PIOB) AB Select Status Register
-AT91C_PIOB_IFDR           EQU (0xFFFFF624) ;- (PIOB) Input Filter Disable Register
-AT91C_PIOB_PDSR           EQU (0xFFFFF63C) ;- (PIOB) Pin Data Status Register
-AT91C_PIOB_IDR            EQU (0xFFFFF644) ;- (PIOB) Interrupt Disable Register
-AT91C_PIOB_OWSR           EQU (0xFFFFF6A8) ;- (PIOB) Output Write Status Register
-AT91C_PIOB_PDR            EQU (0xFFFFF604) ;- (PIOB) PIO Disable Register
-AT91C_PIOB_ODR            EQU (0xFFFFF614) ;- (PIOB) Output Disable Registerr
-AT91C_PIOB_IFSR           EQU (0xFFFFF628) ;- (PIOB) Input Filter Status Register
-AT91C_PIOB_PPUER          EQU (0xFFFFF664) ;- (PIOB) Pull-up Enable Register
-AT91C_PIOB_SODR           EQU (0xFFFFF630) ;- (PIOB) Set Output Data Register
-AT91C_PIOB_ISR            EQU (0xFFFFF64C) ;- (PIOB) Interrupt Status Register
-AT91C_PIOB_ODSR           EQU (0xFFFFF638) ;- (PIOB) Output Data Status Register
-AT91C_PIOB_OSR            EQU (0xFFFFF618) ;- (PIOB) Output Status Register
-AT91C_PIOB_MDSR           EQU (0xFFFFF658) ;- (PIOB) Multi-driver Status Register
-AT91C_PIOB_IFER           EQU (0xFFFFF620) ;- (PIOB) Input Filter Enable Register
-AT91C_PIOB_BSR            EQU (0xFFFFF674) ;- (PIOB) Select B Register
-AT91C_PIOB_MDDR           EQU (0xFFFFF654) ;- (PIOB) Multi-driver Disable Register
-AT91C_PIOB_OER            EQU (0xFFFFF610) ;- (PIOB) Output Enable Register
-AT91C_PIOB_PER            EQU (0xFFFFF600) ;- (PIOB) PIO Enable Register
-// - ========== Register definition for CKGR peripheral ==========
-AT91C_CKGR_MOR            EQU (0xFFFFFC20) ;- (CKGR) Main Oscillator Register
-AT91C_CKGR_PLLR           EQU (0xFFFFFC2C) ;- (CKGR) PLL Register
-AT91C_CKGR_MCFR           EQU (0xFFFFFC24) ;- (CKGR) Main Clock  Frequency Register
-// - ========== Register definition for PMC peripheral ==========
-AT91C_PMC_IDR             EQU (0xFFFFFC64) ;- (PMC) Interrupt Disable Register
-AT91C_PMC_MOR             EQU (0xFFFFFC20) ;- (PMC) Main Oscillator Register
-AT91C_PMC_PLLR            EQU (0xFFFFFC2C) ;- (PMC) PLL Register
-AT91C_PMC_PCER            EQU (0xFFFFFC10) ;- (PMC) Peripheral Clock Enable Register
-AT91C_PMC_PCKR            EQU (0xFFFFFC40) ;- (PMC) Programmable Clock Register
-AT91C_PMC_MCKR            EQU (0xFFFFFC30) ;- (PMC) Master Clock Register
-AT91C_PMC_SCDR            EQU (0xFFFFFC04) ;- (PMC) System Clock Disable Register
-AT91C_PMC_PCDR            EQU (0xFFFFFC14) ;- (PMC) Peripheral Clock Disable Register
-AT91C_PMC_SCSR            EQU (0xFFFFFC08) ;- (PMC) System Clock Status Register
-AT91C_PMC_PCSR            EQU (0xFFFFFC18) ;- (PMC) Peripheral Clock Status Register
-AT91C_PMC_MCFR            EQU (0xFFFFFC24) ;- (PMC) Main Clock  Frequency Register
-AT91C_PMC_SCER            EQU (0xFFFFFC00) ;- (PMC) System Clock Enable Register
-AT91C_PMC_IMR             EQU (0xFFFFFC6C) ;- (PMC) Interrupt Mask Register
-AT91C_PMC_IER             EQU (0xFFFFFC60) ;- (PMC) Interrupt Enable Register
-AT91C_PMC_SR              EQU (0xFFFFFC68) ;- (PMC) Status Register
-// - ========== Register definition for RSTC peripheral ==========
-AT91C_RSTC_RCR            EQU (0xFFFFFD00) ;- (RSTC) Reset Control Register
-AT91C_RSTC_RMR            EQU (0xFFFFFD08) ;- (RSTC) Reset Mode Register
-AT91C_RSTC_RSR            EQU (0xFFFFFD04) ;- (RSTC) Reset Status Register
-// - ========== Register definition for RTTC peripheral ==========
-AT91C_RTTC_RTSR           EQU (0xFFFFFD2C) ;- (RTTC) Real-time Status Register
-AT91C_RTTC_RTMR           EQU (0xFFFFFD20) ;- (RTTC) Real-time Mode Register
-AT91C_RTTC_RTVR           EQU (0xFFFFFD28) ;- (RTTC) Real-time Value Register
-AT91C_RTTC_RTAR           EQU (0xFFFFFD24) ;- (RTTC) Real-time Alarm Register
-// - ========== Register definition for PITC peripheral ==========
-AT91C_PITC_PIVR           EQU (0xFFFFFD38) ;- (PITC) Period Interval Value Register
-AT91C_PITC_PISR           EQU (0xFFFFFD34) ;- (PITC) Period Interval Status Register
-AT91C_PITC_PIIR           EQU (0xFFFFFD3C) ;- (PITC) Period Interval Image Register
-AT91C_PITC_PIMR           EQU (0xFFFFFD30) ;- (PITC) Period Interval Mode Register
-// - ========== Register definition for WDTC peripheral ==========
-AT91C_WDTC_WDCR           EQU (0xFFFFFD40) ;- (WDTC) Watchdog Control Register
-AT91C_WDTC_WDSR           EQU (0xFFFFFD48) ;- (WDTC) Watchdog Status Register
-AT91C_WDTC_WDMR           EQU (0xFFFFFD44) ;- (WDTC) Watchdog Mode Register
-// - ========== Register definition for VREG peripheral ==========
-AT91C_VREG_MR             EQU (0xFFFFFD60) ;- (VREG) Voltage Regulator Mode Register
-// - ========== Register definition for MC peripheral ==========
-AT91C_MC_ASR              EQU (0xFFFFFF04) ;- (MC) MC Abort Status Register
-AT91C_MC_RCR              EQU (0xFFFFFF00) ;- (MC) MC Remap Control Register
-AT91C_MC_FCR              EQU (0xFFFFFF64) ;- (MC) MC Flash Command Register
-AT91C_MC_AASR             EQU (0xFFFFFF08) ;- (MC) MC Abort Address Status Register
-AT91C_MC_FSR              EQU (0xFFFFFF68) ;- (MC) MC Flash Status Register
-AT91C_MC_FMR              EQU (0xFFFFFF60) ;- (MC) MC Flash Mode Register
-// - ========== Register definition for PDC_SPI1 peripheral ==========
-AT91C_SPI1_PTCR           EQU (0xFFFE4120) ;- (PDC_SPI1) PDC Transfer Control Register
-AT91C_SPI1_RPR            EQU (0xFFFE4100) ;- (PDC_SPI1) Receive Pointer Register
-AT91C_SPI1_TNCR           EQU (0xFFFE411C) ;- (PDC_SPI1) Transmit Next Counter Register
-AT91C_SPI1_TPR            EQU (0xFFFE4108) ;- (PDC_SPI1) Transmit Pointer Register
-AT91C_SPI1_TNPR           EQU (0xFFFE4118) ;- (PDC_SPI1) Transmit Next Pointer Register
-AT91C_SPI1_TCR            EQU (0xFFFE410C) ;- (PDC_SPI1) Transmit Counter Register
-AT91C_SPI1_RCR            EQU (0xFFFE4104) ;- (PDC_SPI1) Receive Counter Register
-AT91C_SPI1_RNPR           EQU (0xFFFE4110) ;- (PDC_SPI1) Receive Next Pointer Register
-AT91C_SPI1_RNCR           EQU (0xFFFE4114) ;- (PDC_SPI1) Receive Next Counter Register
-AT91C_SPI1_PTSR           EQU (0xFFFE4124) ;- (PDC_SPI1) PDC Transfer Status Register
-// - ========== Register definition for SPI1 peripheral ==========
-AT91C_SPI1_IMR            EQU (0xFFFE401C) ;- (SPI1) Interrupt Mask Register
-AT91C_SPI1_IER            EQU (0xFFFE4014) ;- (SPI1) Interrupt Enable Register
-AT91C_SPI1_MR             EQU (0xFFFE4004) ;- (SPI1) Mode Register
-AT91C_SPI1_RDR            EQU (0xFFFE4008) ;- (SPI1) Receive Data Register
-AT91C_SPI1_IDR            EQU (0xFFFE4018) ;- (SPI1) Interrupt Disable Register
-AT91C_SPI1_SR             EQU (0xFFFE4010) ;- (SPI1) Status Register
-AT91C_SPI1_TDR            EQU (0xFFFE400C) ;- (SPI1) Transmit Data Register
-AT91C_SPI1_CR             EQU (0xFFFE4000) ;- (SPI1) Control Register
-AT91C_SPI1_CSR            EQU (0xFFFE4030) ;- (SPI1) Chip Select Register
-// - ========== Register definition for PDC_SPI0 peripheral ==========
-AT91C_SPI0_PTCR           EQU (0xFFFE0120) ;- (PDC_SPI0) PDC Transfer Control Register
-AT91C_SPI0_TPR            EQU (0xFFFE0108) ;- (PDC_SPI0) Transmit Pointer Register
-AT91C_SPI0_TCR            EQU (0xFFFE010C) ;- (PDC_SPI0) Transmit Counter Register
-AT91C_SPI0_RCR            EQU (0xFFFE0104) ;- (PDC_SPI0) Receive Counter Register
-AT91C_SPI0_PTSR           EQU (0xFFFE0124) ;- (PDC_SPI0) PDC Transfer Status Register
-AT91C_SPI0_RNPR           EQU (0xFFFE0110) ;- (PDC_SPI0) Receive Next Pointer Register
-AT91C_SPI0_RPR            EQU (0xFFFE0100) ;- (PDC_SPI0) Receive Pointer Register
-AT91C_SPI0_TNCR           EQU (0xFFFE011C) ;- (PDC_SPI0) Transmit Next Counter Register
-AT91C_SPI0_RNCR           EQU (0xFFFE0114) ;- (PDC_SPI0) Receive Next Counter Register
-AT91C_SPI0_TNPR           EQU (0xFFFE0118) ;- (PDC_SPI0) Transmit Next Pointer Register
-// - ========== Register definition for SPI0 peripheral ==========
-AT91C_SPI0_IER            EQU (0xFFFE0014) ;- (SPI0) Interrupt Enable Register
-AT91C_SPI0_SR             EQU (0xFFFE0010) ;- (SPI0) Status Register
-AT91C_SPI0_IDR            EQU (0xFFFE0018) ;- (SPI0) Interrupt Disable Register
-AT91C_SPI0_CR             EQU (0xFFFE0000) ;- (SPI0) Control Register
-AT91C_SPI0_MR             EQU (0xFFFE0004) ;- (SPI0) Mode Register
-AT91C_SPI0_IMR            EQU (0xFFFE001C) ;- (SPI0) Interrupt Mask Register
-AT91C_SPI0_TDR            EQU (0xFFFE000C) ;- (SPI0) Transmit Data Register
-AT91C_SPI0_RDR            EQU (0xFFFE0008) ;- (SPI0) Receive Data Register
-AT91C_SPI0_CSR            EQU (0xFFFE0030) ;- (SPI0) Chip Select Register
-// - ========== Register definition for PDC_US1 peripheral ==========
-AT91C_US1_RNCR            EQU (0xFFFC4114) ;- (PDC_US1) Receive Next Counter Register
-AT91C_US1_PTCR            EQU (0xFFFC4120) ;- (PDC_US1) PDC Transfer Control Register
-AT91C_US1_TCR             EQU (0xFFFC410C) ;- (PDC_US1) Transmit Counter Register
-AT91C_US1_PTSR            EQU (0xFFFC4124) ;- (PDC_US1) PDC Transfer Status Register
-AT91C_US1_TNPR            EQU (0xFFFC4118) ;- (PDC_US1) Transmit Next Pointer Register
-AT91C_US1_RCR             EQU (0xFFFC4104) ;- (PDC_US1) Receive Counter Register
-AT91C_US1_RNPR            EQU (0xFFFC4110) ;- (PDC_US1) Receive Next Pointer Register
-AT91C_US1_RPR             EQU (0xFFFC4100) ;- (PDC_US1) Receive Pointer Register
-AT91C_US1_TNCR            EQU (0xFFFC411C) ;- (PDC_US1) Transmit Next Counter Register
-AT91C_US1_TPR             EQU (0xFFFC4108) ;- (PDC_US1) Transmit Pointer Register
-// - ========== Register definition for US1 peripheral ==========
-AT91C_US1_IF              EQU (0xFFFC404C) ;- (US1) IRDA_FILTER Register
-AT91C_US1_NER             EQU (0xFFFC4044) ;- (US1) Nb Errors Register
-AT91C_US1_RTOR            EQU (0xFFFC4024) ;- (US1) Receiver Time-out Register
-AT91C_US1_CSR             EQU (0xFFFC4014) ;- (US1) Channel Status Register
-AT91C_US1_IDR             EQU (0xFFFC400C) ;- (US1) Interrupt Disable Register
-AT91C_US1_IER             EQU (0xFFFC4008) ;- (US1) Interrupt Enable Register
-AT91C_US1_THR             EQU (0xFFFC401C) ;- (US1) Transmitter Holding Register
-AT91C_US1_TTGR            EQU (0xFFFC4028) ;- (US1) Transmitter Time-guard Register
-AT91C_US1_RHR             EQU (0xFFFC4018) ;- (US1) Receiver Holding Register
-AT91C_US1_BRGR            EQU (0xFFFC4020) ;- (US1) Baud Rate Generator Register
-AT91C_US1_IMR             EQU (0xFFFC4010) ;- (US1) Interrupt Mask Register
-AT91C_US1_FIDI            EQU (0xFFFC4040) ;- (US1) FI_DI_Ratio Register
-AT91C_US1_CR              EQU (0xFFFC4000) ;- (US1) Control Register
-AT91C_US1_MR              EQU (0xFFFC4004) ;- (US1) Mode Register
-// - ========== Register definition for PDC_US0 peripheral ==========
-AT91C_US0_TNPR            EQU (0xFFFC0118) ;- (PDC_US0) Transmit Next Pointer Register
-AT91C_US0_RNPR            EQU (0xFFFC0110) ;- (PDC_US0) Receive Next Pointer Register
-AT91C_US0_TCR             EQU (0xFFFC010C) ;- (PDC_US0) Transmit Counter Register
-AT91C_US0_PTCR            EQU (0xFFFC0120) ;- (PDC_US0) PDC Transfer Control Register
-AT91C_US0_PTSR            EQU (0xFFFC0124) ;- (PDC_US0) PDC Transfer Status Register
-AT91C_US0_TNCR            EQU (0xFFFC011C) ;- (PDC_US0) Transmit Next Counter Register
-AT91C_US0_TPR             EQU (0xFFFC0108) ;- (PDC_US0) Transmit Pointer Register
-AT91C_US0_RCR             EQU (0xFFFC0104) ;- (PDC_US0) Receive Counter Register
-AT91C_US0_RPR             EQU (0xFFFC0100) ;- (PDC_US0) Receive Pointer Register
-AT91C_US0_RNCR            EQU (0xFFFC0114) ;- (PDC_US0) Receive Next Counter Register
-// - ========== Register definition for US0 peripheral ==========
-AT91C_US0_BRGR            EQU (0xFFFC0020) ;- (US0) Baud Rate Generator Register
-AT91C_US0_NER             EQU (0xFFFC0044) ;- (US0) Nb Errors Register
-AT91C_US0_CR              EQU (0xFFFC0000) ;- (US0) Control Register
-AT91C_US0_IMR             EQU (0xFFFC0010) ;- (US0) Interrupt Mask Register
-AT91C_US0_FIDI            EQU (0xFFFC0040) ;- (US0) FI_DI_Ratio Register
-AT91C_US0_TTGR            EQU (0xFFFC0028) ;- (US0) Transmitter Time-guard Register
-AT91C_US0_MR              EQU (0xFFFC0004) ;- (US0) Mode Register
-AT91C_US0_RTOR            EQU (0xFFFC0024) ;- (US0) Receiver Time-out Register
-AT91C_US0_CSR             EQU (0xFFFC0014) ;- (US0) Channel Status Register
-AT91C_US0_RHR             EQU (0xFFFC0018) ;- (US0) Receiver Holding Register
-AT91C_US0_IDR             EQU (0xFFFC000C) ;- (US0) Interrupt Disable Register
-AT91C_US0_THR             EQU (0xFFFC001C) ;- (US0) Transmitter Holding Register
-AT91C_US0_IF              EQU (0xFFFC004C) ;- (US0) IRDA_FILTER Register
-AT91C_US0_IER             EQU (0xFFFC0008) ;- (US0) Interrupt Enable Register
-// - ========== Register definition for PDC_SSC peripheral ==========
-AT91C_SSC_TNCR            EQU (0xFFFD411C) ;- (PDC_SSC) Transmit Next Counter Register
-AT91C_SSC_RPR             EQU (0xFFFD4100) ;- (PDC_SSC) Receive Pointer Register
-AT91C_SSC_RNCR            EQU (0xFFFD4114) ;- (PDC_SSC) Receive Next Counter Register
-AT91C_SSC_TPR             EQU (0xFFFD4108) ;- (PDC_SSC) Transmit Pointer Register
-AT91C_SSC_PTCR            EQU (0xFFFD4120) ;- (PDC_SSC) PDC Transfer Control Register
-AT91C_SSC_TCR             EQU (0xFFFD410C) ;- (PDC_SSC) Transmit Counter Register
-AT91C_SSC_RCR             EQU (0xFFFD4104) ;- (PDC_SSC) Receive Counter Register
-AT91C_SSC_RNPR            EQU (0xFFFD4110) ;- (PDC_SSC) Receive Next Pointer Register
-AT91C_SSC_TNPR            EQU (0xFFFD4118) ;- (PDC_SSC) Transmit Next Pointer Register
-AT91C_SSC_PTSR            EQU (0xFFFD4124) ;- (PDC_SSC) PDC Transfer Status Register
-// - ========== Register definition for SSC peripheral ==========
-AT91C_SSC_RHR             EQU (0xFFFD4020) ;- (SSC) Receive Holding Register
-AT91C_SSC_RSHR            EQU (0xFFFD4030) ;- (SSC) Receive Sync Holding Register
-AT91C_SSC_TFMR            EQU (0xFFFD401C) ;- (SSC) Transmit Frame Mode Register
-AT91C_SSC_IDR             EQU (0xFFFD4048) ;- (SSC) Interrupt Disable Register
-AT91C_SSC_THR             EQU (0xFFFD4024) ;- (SSC) Transmit Holding Register
-AT91C_SSC_RCMR            EQU (0xFFFD4010) ;- (SSC) Receive Clock ModeRegister
-AT91C_SSC_IER             EQU (0xFFFD4044) ;- (SSC) Interrupt Enable Register
-AT91C_SSC_TSHR            EQU (0xFFFD4034) ;- (SSC) Transmit Sync Holding Register
-AT91C_SSC_SR              EQU (0xFFFD4040) ;- (SSC) Status Register
-AT91C_SSC_CMR             EQU (0xFFFD4004) ;- (SSC) Clock Mode Register
-AT91C_SSC_TCMR            EQU (0xFFFD4018) ;- (SSC) Transmit Clock Mode Register
-AT91C_SSC_CR              EQU (0xFFFD4000) ;- (SSC) Control Register
-AT91C_SSC_IMR             EQU (0xFFFD404C) ;- (SSC) Interrupt Mask Register
-AT91C_SSC_RFMR            EQU (0xFFFD4014) ;- (SSC) Receive Frame Mode Register
-// - ========== Register definition for TWI peripheral ==========
-AT91C_TWI_IER             EQU (0xFFFB8024) ;- (TWI) Interrupt Enable Register
-AT91C_TWI_CR              EQU (0xFFFB8000) ;- (TWI) Control Register
-AT91C_TWI_SR              EQU (0xFFFB8020) ;- (TWI) Status Register
-AT91C_TWI_IMR             EQU (0xFFFB802C) ;- (TWI) Interrupt Mask Register
-AT91C_TWI_THR             EQU (0xFFFB8034) ;- (TWI) Transmit Holding Register
-AT91C_TWI_IDR             EQU (0xFFFB8028) ;- (TWI) Interrupt Disable Register
-AT91C_TWI_IADR            EQU (0xFFFB800C) ;- (TWI) Internal Address Register
-AT91C_TWI_MMR             EQU (0xFFFB8004) ;- (TWI) Master Mode Register
-AT91C_TWI_CWGR            EQU (0xFFFB8010) ;- (TWI) Clock Waveform Generator Register
-AT91C_TWI_RHR             EQU (0xFFFB8030) ;- (TWI) Receive Holding Register
-// - ========== Register definition for PWMC_CH3 peripheral ==========
-AT91C_PWMC_CH3_CUPDR      EQU (0xFFFCC270) ;- (PWMC_CH3) Channel Update Register
-AT91C_PWMC_CH3_Reserved   EQU (0xFFFCC274) ;- (PWMC_CH3) Reserved
-AT91C_PWMC_CH3_CPRDR      EQU (0xFFFCC268) ;- (PWMC_CH3) Channel Period Register
-AT91C_PWMC_CH3_CDTYR      EQU (0xFFFCC264) ;- (PWMC_CH3) Channel Duty Cycle Register
-AT91C_PWMC_CH3_CCNTR      EQU (0xFFFCC26C) ;- (PWMC_CH3) Channel Counter Register
-AT91C_PWMC_CH3_CMR        EQU (0xFFFCC260) ;- (PWMC_CH3) Channel Mode Register
-// - ========== Register definition for PWMC_CH2 peripheral ==========
-AT91C_PWMC_CH2_Reserved   EQU (0xFFFCC254) ;- (PWMC_CH2) Reserved
-AT91C_PWMC_CH2_CMR        EQU (0xFFFCC240) ;- (PWMC_CH2) Channel Mode Register
-AT91C_PWMC_CH2_CCNTR      EQU (0xFFFCC24C) ;- (PWMC_CH2) Channel Counter Register
-AT91C_PWMC_CH2_CPRDR      EQU (0xFFFCC248) ;- (PWMC_CH2) Channel Period Register
-AT91C_PWMC_CH2_CUPDR      EQU (0xFFFCC250) ;- (PWMC_CH2) Channel Update Register
-AT91C_PWMC_CH2_CDTYR      EQU (0xFFFCC244) ;- (PWMC_CH2) Channel Duty Cycle Register
-// - ========== Register definition for PWMC_CH1 peripheral ==========
-AT91C_PWMC_CH1_Reserved   EQU (0xFFFCC234) ;- (PWMC_CH1) Reserved
-AT91C_PWMC_CH1_CUPDR      EQU (0xFFFCC230) ;- (PWMC_CH1) Channel Update Register
-AT91C_PWMC_CH1_CPRDR      EQU (0xFFFCC228) ;- (PWMC_CH1) Channel Period Register
-AT91C_PWMC_CH1_CCNTR      EQU (0xFFFCC22C) ;- (PWMC_CH1) Channel Counter Register
-AT91C_PWMC_CH1_CDTYR      EQU (0xFFFCC224) ;- (PWMC_CH1) Channel Duty Cycle Register
-AT91C_PWMC_CH1_CMR        EQU (0xFFFCC220) ;- (PWMC_CH1) Channel Mode Register
-// - ========== Register definition for PWMC_CH0 peripheral ==========
-AT91C_PWMC_CH0_Reserved   EQU (0xFFFCC214) ;- (PWMC_CH0) Reserved
-AT91C_PWMC_CH0_CPRDR      EQU (0xFFFCC208) ;- (PWMC_CH0) Channel Period Register
-AT91C_PWMC_CH0_CDTYR      EQU (0xFFFCC204) ;- (PWMC_CH0) Channel Duty Cycle Register
-AT91C_PWMC_CH0_CMR        EQU (0xFFFCC200) ;- (PWMC_CH0) Channel Mode Register
-AT91C_PWMC_CH0_CUPDR      EQU (0xFFFCC210) ;- (PWMC_CH0) Channel Update Register
-AT91C_PWMC_CH0_CCNTR      EQU (0xFFFCC20C) ;- (PWMC_CH0) Channel Counter Register
-// - ========== Register definition for PWMC peripheral ==========
-AT91C_PWMC_IDR            EQU (0xFFFCC014) ;- (PWMC) PWMC Interrupt Disable Register
-AT91C_PWMC_DIS            EQU (0xFFFCC008) ;- (PWMC) PWMC Disable Register
-AT91C_PWMC_IER            EQU (0xFFFCC010) ;- (PWMC) PWMC Interrupt Enable Register
-AT91C_PWMC_VR             EQU (0xFFFCC0FC) ;- (PWMC) PWMC Version Register
-AT91C_PWMC_ISR            EQU (0xFFFCC01C) ;- (PWMC) PWMC Interrupt Status Register
-AT91C_PWMC_SR             EQU (0xFFFCC00C) ;- (PWMC) PWMC Status Register
-AT91C_PWMC_IMR            EQU (0xFFFCC018) ;- (PWMC) PWMC Interrupt Mask Register
-AT91C_PWMC_MR             EQU (0xFFFCC000) ;- (PWMC) PWMC Mode Register
-AT91C_PWMC_ENA            EQU (0xFFFCC004) ;- (PWMC) PWMC Enable Register
-// - ========== Register definition for UDP peripheral ==========
-AT91C_UDP_IMR             EQU (0xFFFB0018) ;- (UDP) Interrupt Mask Register
-AT91C_UDP_FADDR           EQU (0xFFFB0008) ;- (UDP) Function Address Register
-AT91C_UDP_NUM             EQU (0xFFFB0000) ;- (UDP) Frame Number Register
-AT91C_UDP_FDR             EQU (0xFFFB0050) ;- (UDP) Endpoint FIFO Data Register
-AT91C_UDP_ISR             EQU (0xFFFB001C) ;- (UDP) Interrupt Status Register
-AT91C_UDP_CSR             EQU (0xFFFB0030) ;- (UDP) Endpoint Control and Status Register
-AT91C_UDP_IDR             EQU (0xFFFB0014) ;- (UDP) Interrupt Disable Register
-AT91C_UDP_ICR             EQU (0xFFFB0020) ;- (UDP) Interrupt Clear Register
-AT91C_UDP_RSTEP           EQU (0xFFFB0028) ;- (UDP) Reset Endpoint Register
-AT91C_UDP_TXVC            EQU (0xFFFB0074) ;- (UDP) Transceiver Control Register
-AT91C_UDP_GLBSTATE        EQU (0xFFFB0004) ;- (UDP) Global State Register
-AT91C_UDP_IER             EQU (0xFFFB0010) ;- (UDP) Interrupt Enable Register
-// - ========== Register definition for TC0 peripheral ==========
-AT91C_TC0_SR              EQU (0xFFFA0020) ;- (TC0) Status Register
-AT91C_TC0_RC              EQU (0xFFFA001C) ;- (TC0) Register C
-AT91C_TC0_RB              EQU (0xFFFA0018) ;- (TC0) Register B
-AT91C_TC0_CCR             EQU (0xFFFA0000) ;- (TC0) Channel Control Register
-AT91C_TC0_CMR             EQU (0xFFFA0004) ;- (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
-AT91C_TC0_IER             EQU (0xFFFA0024) ;- (TC0) Interrupt Enable Register
-AT91C_TC0_RA              EQU (0xFFFA0014) ;- (TC0) Register A
-AT91C_TC0_IDR             EQU (0xFFFA0028) ;- (TC0) Interrupt Disable Register
-AT91C_TC0_CV              EQU (0xFFFA0010) ;- (TC0) Counter Value
-AT91C_TC0_IMR             EQU (0xFFFA002C) ;- (TC0) Interrupt Mask Register
-// - ========== Register definition for TC1 peripheral ==========
-AT91C_TC1_RB              EQU (0xFFFA0058) ;- (TC1) Register B
-AT91C_TC1_CCR             EQU (0xFFFA0040) ;- (TC1) Channel Control Register
-AT91C_TC1_IER             EQU (0xFFFA0064) ;- (TC1) Interrupt Enable Register
-AT91C_TC1_IDR             EQU (0xFFFA0068) ;- (TC1) Interrupt Disable Register
-AT91C_TC1_SR              EQU (0xFFFA0060) ;- (TC1) Status Register
-AT91C_TC1_CMR             EQU (0xFFFA0044) ;- (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
-AT91C_TC1_RA              EQU (0xFFFA0054) ;- (TC1) Register A
-AT91C_TC1_RC              EQU (0xFFFA005C) ;- (TC1) Register C
-AT91C_TC1_IMR             EQU (0xFFFA006C) ;- (TC1) Interrupt Mask Register
-AT91C_TC1_CV              EQU (0xFFFA0050) ;- (TC1) Counter Value
-// - ========== Register definition for TC2 peripheral ==========
-AT91C_TC2_CMR             EQU (0xFFFA0084) ;- (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
-AT91C_TC2_CCR             EQU (0xFFFA0080) ;- (TC2) Channel Control Register
-AT91C_TC2_CV              EQU (0xFFFA0090) ;- (TC2) Counter Value
-AT91C_TC2_RA              EQU (0xFFFA0094) ;- (TC2) Register A
-AT91C_TC2_RB              EQU (0xFFFA0098) ;- (TC2) Register B
-AT91C_TC2_IDR             EQU (0xFFFA00A8) ;- (TC2) Interrupt Disable Register
-AT91C_TC2_IMR             EQU (0xFFFA00AC) ;- (TC2) Interrupt Mask Register
-AT91C_TC2_RC              EQU (0xFFFA009C) ;- (TC2) Register C
-AT91C_TC2_IER             EQU (0xFFFA00A4) ;- (TC2) Interrupt Enable Register
-AT91C_TC2_SR              EQU (0xFFFA00A0) ;- (TC2) Status Register
-// - ========== Register definition for TCB peripheral ==========
-AT91C_TCB_BMR             EQU (0xFFFA00C4) ;- (TCB) TC Block Mode Register
-AT91C_TCB_BCR             EQU (0xFFFA00C0) ;- (TCB) TC Block Control Register
-// - ========== Register definition for CAN_MB0 peripheral ==========
-AT91C_CAN_MB0_MDL         EQU (0xFFFD0214) ;- (CAN_MB0) MailBox Data Low Register
-AT91C_CAN_MB0_MAM         EQU (0xFFFD0204) ;- (CAN_MB0) MailBox Acceptance Mask Register
-AT91C_CAN_MB0_MCR         EQU (0xFFFD021C) ;- (CAN_MB0) MailBox Control Register
-AT91C_CAN_MB0_MID         EQU (0xFFFD0208) ;- (CAN_MB0) MailBox ID Register
-AT91C_CAN_MB0_MSR         EQU (0xFFFD0210) ;- (CAN_MB0) MailBox Status Register
-AT91C_CAN_MB0_MFID        EQU (0xFFFD020C) ;- (CAN_MB0) MailBox Family ID Register
-AT91C_CAN_MB0_MDH         EQU (0xFFFD0218) ;- (CAN_MB0) MailBox Data High Register
-AT91C_CAN_MB0_MMR         EQU (0xFFFD0200) ;- (CAN_MB0) MailBox Mode Register
-// - ========== Register definition for CAN_MB1 peripheral ==========
-AT91C_CAN_MB1_MDL         EQU (0xFFFD0234) ;- (CAN_MB1) MailBox Data Low Register
-AT91C_CAN_MB1_MID         EQU (0xFFFD0228) ;- (CAN_MB1) MailBox ID Register
-AT91C_CAN_MB1_MMR         EQU (0xFFFD0220) ;- (CAN_MB1) MailBox Mode Register
-AT91C_CAN_MB1_MSR         EQU (0xFFFD0230) ;- (CAN_MB1) MailBox Status Register
-AT91C_CAN_MB1_MAM         EQU (0xFFFD0224) ;- (CAN_MB1) MailBox Acceptance Mask Register
-AT91C_CAN_MB1_MDH         EQU (0xFFFD0238) ;- (CAN_MB1) MailBox Data High Register
-AT91C_CAN_MB1_MCR         EQU (0xFFFD023C) ;- (CAN_MB1) MailBox Control Register
-AT91C_CAN_MB1_MFID        EQU (0xFFFD022C) ;- (CAN_MB1) MailBox Family ID Register
-// - ========== Register definition for CAN_MB2 peripheral ==========
-AT91C_CAN_MB2_MCR         EQU (0xFFFD025C) ;- (CAN_MB2) MailBox Control Register
-AT91C_CAN_MB2_MDH         EQU (0xFFFD0258) ;- (CAN_MB2) MailBox Data High Register
-AT91C_CAN_MB2_MID         EQU (0xFFFD0248) ;- (CAN_MB2) MailBox ID Register
-AT91C_CAN_MB2_MDL         EQU (0xFFFD0254) ;- (CAN_MB2) MailBox Data Low Register
-AT91C_CAN_MB2_MMR         EQU (0xFFFD0240) ;- (CAN_MB2) MailBox Mode Register
-AT91C_CAN_MB2_MAM         EQU (0xFFFD0244) ;- (CAN_MB2) MailBox Acceptance Mask Register
-AT91C_CAN_MB2_MFID        EQU (0xFFFD024C) ;- (CAN_MB2) MailBox Family ID Register
-AT91C_CAN_MB2_MSR         EQU (0xFFFD0250) ;- (CAN_MB2) MailBox Status Register
-// - ========== Register definition for CAN_MB3 peripheral ==========
-AT91C_CAN_MB3_MFID        EQU (0xFFFD026C) ;- (CAN_MB3) MailBox Family ID Register
-AT91C_CAN_MB3_MAM         EQU (0xFFFD0264) ;- (CAN_MB3) MailBox Acceptance Mask Register
-AT91C_CAN_MB3_MID         EQU (0xFFFD0268) ;- (CAN_MB3) MailBox ID Register
-AT91C_CAN_MB3_MCR         EQU (0xFFFD027C) ;- (CAN_MB3) MailBox Control Register
-AT91C_CAN_MB3_MMR         EQU (0xFFFD0260) ;- (CAN_MB3) MailBox Mode Register
-AT91C_CAN_MB3_MSR         EQU (0xFFFD0270) ;- (CAN_MB3) MailBox Status Register
-AT91C_CAN_MB3_MDL         EQU (0xFFFD0274) ;- (CAN_MB3) MailBox Data Low Register
-AT91C_CAN_MB3_MDH         EQU (0xFFFD0278) ;- (CAN_MB3) MailBox Data High Register
-// - ========== Register definition for CAN_MB4 peripheral ==========
-AT91C_CAN_MB4_MID         EQU (0xFFFD0288) ;- (CAN_MB4) MailBox ID Register
-AT91C_CAN_MB4_MMR         EQU (0xFFFD0280) ;- (CAN_MB4) MailBox Mode Register
-AT91C_CAN_MB4_MDH         EQU (0xFFFD0298) ;- (CAN_MB4) MailBox Data High Register
-AT91C_CAN_MB4_MFID        EQU (0xFFFD028C) ;- (CAN_MB4) MailBox Family ID Register
-AT91C_CAN_MB4_MSR         EQU (0xFFFD0290) ;- (CAN_MB4) MailBox Status Register
-AT91C_CAN_MB4_MCR         EQU (0xFFFD029C) ;- (CAN_MB4) MailBox Control Register
-AT91C_CAN_MB4_MDL         EQU (0xFFFD0294) ;- (CAN_MB4) MailBox Data Low Register
-AT91C_CAN_MB4_MAM         EQU (0xFFFD0284) ;- (CAN_MB4) MailBox Acceptance Mask Register
-// - ========== Register definition for CAN_MB5 peripheral ==========
-AT91C_CAN_MB5_MSR         EQU (0xFFFD02B0) ;- (CAN_MB5) MailBox Status Register
-AT91C_CAN_MB5_MCR         EQU (0xFFFD02BC) ;- (CAN_MB5) MailBox Control Register
-AT91C_CAN_MB5_MFID        EQU (0xFFFD02AC) ;- (CAN_MB5) MailBox Family ID Register
-AT91C_CAN_MB5_MDH         EQU (0xFFFD02B8) ;- (CAN_MB5) MailBox Data High Register
-AT91C_CAN_MB5_MID         EQU (0xFFFD02A8) ;- (CAN_MB5) MailBox ID Register
-AT91C_CAN_MB5_MMR         EQU (0xFFFD02A0) ;- (CAN_MB5) MailBox Mode Register
-AT91C_CAN_MB5_MDL         EQU (0xFFFD02B4) ;- (CAN_MB5) MailBox Data Low Register
-AT91C_CAN_MB5_MAM         EQU (0xFFFD02A4) ;- (CAN_MB5) MailBox Acceptance Mask Register
-// - ========== Register definition for CAN_MB6 peripheral ==========
-AT91C_CAN_MB6_MFID        EQU (0xFFFD02CC) ;- (CAN_MB6) MailBox Family ID Register
-AT91C_CAN_MB6_MID         EQU (0xFFFD02C8) ;- (CAN_MB6) MailBox ID Register
-AT91C_CAN_MB6_MAM         EQU (0xFFFD02C4) ;- (CAN_MB6) MailBox Acceptance Mask Register
-AT91C_CAN_MB6_MSR         EQU (0xFFFD02D0) ;- (CAN_MB6) MailBox Status Register
-AT91C_CAN_MB6_MDL         EQU (0xFFFD02D4) ;- (CAN_MB6) MailBox Data Low Register
-AT91C_CAN_MB6_MCR         EQU (0xFFFD02DC) ;- (CAN_MB6) MailBox Control Register
-AT91C_CAN_MB6_MDH         EQU (0xFFFD02D8) ;- (CAN_MB6) MailBox Data High Register
-AT91C_CAN_MB6_MMR         EQU (0xFFFD02C0) ;- (CAN_MB6) MailBox Mode Register
-// - ========== Register definition for CAN_MB7 peripheral ==========
-AT91C_CAN_MB7_MCR         EQU (0xFFFD02FC) ;- (CAN_MB7) MailBox Control Register
-AT91C_CAN_MB7_MDH         EQU (0xFFFD02F8) ;- (CAN_MB7) MailBox Data High Register
-AT91C_CAN_MB7_MFID        EQU (0xFFFD02EC) ;- (CAN_MB7) MailBox Family ID Register
-AT91C_CAN_MB7_MDL         EQU (0xFFFD02F4) ;- (CAN_MB7) MailBox Data Low Register
-AT91C_CAN_MB7_MID         EQU (0xFFFD02E8) ;- (CAN_MB7) MailBox ID Register
-AT91C_CAN_MB7_MMR         EQU (0xFFFD02E0) ;- (CAN_MB7) MailBox Mode Register
-AT91C_CAN_MB7_MAM         EQU (0xFFFD02E4) ;- (CAN_MB7) MailBox Acceptance Mask Register
-AT91C_CAN_MB7_MSR         EQU (0xFFFD02F0) ;- (CAN_MB7) MailBox Status Register
-// - ========== Register definition for CAN peripheral ==========
-AT91C_CAN_TCR             EQU (0xFFFD0024) ;- (CAN) Transfer Command Register
-AT91C_CAN_IMR             EQU (0xFFFD000C) ;- (CAN) Interrupt Mask Register
-AT91C_CAN_IER             EQU (0xFFFD0004) ;- (CAN) Interrupt Enable Register
-AT91C_CAN_ECR             EQU (0xFFFD0020) ;- (CAN) Error Counter Register
-AT91C_CAN_TIMESTP         EQU (0xFFFD001C) ;- (CAN) Time Stamp Register
-AT91C_CAN_MR              EQU (0xFFFD0000) ;- (CAN) Mode Register
-AT91C_CAN_IDR             EQU (0xFFFD0008) ;- (CAN) Interrupt Disable Register
-AT91C_CAN_ACR             EQU (0xFFFD0028) ;- (CAN) Abort Command Register
-AT91C_CAN_TIM             EQU (0xFFFD0018) ;- (CAN) Timer Register
-AT91C_CAN_SR              EQU (0xFFFD0010) ;- (CAN) Status Register
-AT91C_CAN_BR              EQU (0xFFFD0014) ;- (CAN) Baudrate Register
-AT91C_CAN_VR              EQU (0xFFFD00FC) ;- (CAN) Version Register
-// - ========== Register definition for EMAC peripheral ==========
-AT91C_EMAC_ISR            EQU (0xFFFDC024) ;- (EMAC) Interrupt Status Register
-AT91C_EMAC_SA4H           EQU (0xFFFDC0B4) ;- (EMAC) Specific Address 4 Top, Last 2 bytes
-AT91C_EMAC_SA1L           EQU (0xFFFDC098) ;- (EMAC) Specific Address 1 Bottom, First 4 bytes
-AT91C_EMAC_ELE            EQU (0xFFFDC078) ;- (EMAC) Excessive Length Errors Register
-AT91C_EMAC_LCOL           EQU (0xFFFDC05C) ;- (EMAC) Late Collision Register
-AT91C_EMAC_RLE            EQU (0xFFFDC088) ;- (EMAC) Receive Length Field Mismatch Register
-AT91C_EMAC_WOL            EQU (0xFFFDC0C4) ;- (EMAC) Wake On LAN Register
-AT91C_EMAC_DTF            EQU (0xFFFDC058) ;- (EMAC) Deferred Transmission Frame Register
-AT91C_EMAC_TUND           EQU (0xFFFDC064) ;- (EMAC) Transmit Underrun Error Register
-AT91C_EMAC_NCR            EQU (0xFFFDC000) ;- (EMAC) Network Control Register
-AT91C_EMAC_SA4L           EQU (0xFFFDC0B0) ;- (EMAC) Specific Address 4 Bottom, First 4 bytes
-AT91C_EMAC_RSR            EQU (0xFFFDC020) ;- (EMAC) Receive Status Register
-AT91C_EMAC_SA3L           EQU (0xFFFDC0A8) ;- (EMAC) Specific Address 3 Bottom, First 4 bytes
-AT91C_EMAC_TSR            EQU (0xFFFDC014) ;- (EMAC) Transmit Status Register
-AT91C_EMAC_IDR            EQU (0xFFFDC02C) ;- (EMAC) Interrupt Disable Register
-AT91C_EMAC_RSE            EQU (0xFFFDC074) ;- (EMAC) Receive Symbol Errors Register
-AT91C_EMAC_ECOL           EQU (0xFFFDC060) ;- (EMAC) Excessive Collision Register
-AT91C_EMAC_TID            EQU (0xFFFDC0B8) ;- (EMAC) Type ID Checking Register
-AT91C_EMAC_HRB            EQU (0xFFFDC090) ;- (EMAC) Hash Address Bottom[31:0]
-AT91C_EMAC_TBQP           EQU (0xFFFDC01C) ;- (EMAC) Transmit Buffer Queue Pointer
-AT91C_EMAC_USRIO          EQU (0xFFFDC0C0) ;- (EMAC) USER Input/Output Register
-AT91C_EMAC_PTR            EQU (0xFFFDC038) ;- (EMAC) Pause Time Register
-AT91C_EMAC_SA2H           EQU (0xFFFDC0A4) ;- (EMAC) Specific Address 2 Top, Last 2 bytes
-AT91C_EMAC_ROV            EQU (0xFFFDC070) ;- (EMAC) Receive Overrun Errors Register
-AT91C_EMAC_ALE            EQU (0xFFFDC054) ;- (EMAC) Alignment Error Register
-AT91C_EMAC_RJA            EQU (0xFFFDC07C) ;- (EMAC) Receive Jabbers Register
-AT91C_EMAC_RBQP           EQU (0xFFFDC018) ;- (EMAC) Receive Buffer Queue Pointer
-AT91C_EMAC_TPF            EQU (0xFFFDC08C) ;- (EMAC) Transmitted Pause Frames Register
-AT91C_EMAC_NCFGR          EQU (0xFFFDC004) ;- (EMAC) Network Configuration Register
-AT91C_EMAC_HRT            EQU (0xFFFDC094) ;- (EMAC) Hash Address Top[63:32]
-AT91C_EMAC_USF            EQU (0xFFFDC080) ;- (EMAC) Undersize Frames Register
-AT91C_EMAC_FCSE           EQU (0xFFFDC050) ;- (EMAC) Frame Check Sequence Error Register
-AT91C_EMAC_TPQ            EQU (0xFFFDC0BC) ;- (EMAC) Transmit Pause Quantum Register
-AT91C_EMAC_MAN            EQU (0xFFFDC034) ;- (EMAC) PHY Maintenance Register
-AT91C_EMAC_FTO            EQU (0xFFFDC040) ;- (EMAC) Frames Transmitted OK Register
-AT91C_EMAC_REV            EQU (0xFFFDC0FC) ;- (EMAC) Revision Register
-AT91C_EMAC_IMR            EQU (0xFFFDC030) ;- (EMAC) Interrupt Mask Register
-AT91C_EMAC_SCF            EQU (0xFFFDC044) ;- (EMAC) Single Collision Frame Register
-AT91C_EMAC_PFR            EQU (0xFFFDC03C) ;- (EMAC) Pause Frames received Register
-AT91C_EMAC_MCF            EQU (0xFFFDC048) ;- (EMAC) Multiple Collision Frame Register
-AT91C_EMAC_NSR            EQU (0xFFFDC008) ;- (EMAC) Network Status Register
-AT91C_EMAC_SA2L           EQU (0xFFFDC0A0) ;- (EMAC) Specific Address 2 Bottom, First 4 bytes
-AT91C_EMAC_FRO            EQU (0xFFFDC04C) ;- (EMAC) Frames Received OK Register
-AT91C_EMAC_IER            EQU (0xFFFDC028) ;- (EMAC) Interrupt Enable Register
-AT91C_EMAC_SA1H           EQU (0xFFFDC09C) ;- (EMAC) Specific Address 1 Top, Last 2 bytes
-AT91C_EMAC_CSE            EQU (0xFFFDC068) ;- (EMAC) Carrier Sense Error Register
-AT91C_EMAC_SA3H           EQU (0xFFFDC0AC) ;- (EMAC) Specific Address 3 Top, Last 2 bytes
-AT91C_EMAC_RRE            EQU (0xFFFDC06C) ;- (EMAC) Receive Ressource Error Register
-AT91C_EMAC_STE            EQU (0xFFFDC084) ;- (EMAC) SQE Test Error Register
-// - ========== Register definition for PDC_ADC peripheral ==========
-AT91C_ADC_PTSR            EQU (0xFFFD8124) ;- (PDC_ADC) PDC Transfer Status Register
-AT91C_ADC_PTCR            EQU (0xFFFD8120) ;- (PDC_ADC) PDC Transfer Control Register
-AT91C_ADC_TNPR            EQU (0xFFFD8118) ;- (PDC_ADC) Transmit Next Pointer Register
-AT91C_ADC_TNCR            EQU (0xFFFD811C) ;- (PDC_ADC) Transmit Next Counter Register
-AT91C_ADC_RNPR            EQU (0xFFFD8110) ;- (PDC_ADC) Receive Next Pointer Register
-AT91C_ADC_RNCR            EQU (0xFFFD8114) ;- (PDC_ADC) Receive Next Counter Register
-AT91C_ADC_RPR             EQU (0xFFFD8100) ;- (PDC_ADC) Receive Pointer Register
-AT91C_ADC_TCR             EQU (0xFFFD810C) ;- (PDC_ADC) Transmit Counter Register
-AT91C_ADC_TPR             EQU (0xFFFD8108) ;- (PDC_ADC) Transmit Pointer Register
-AT91C_ADC_RCR             EQU (0xFFFD8104) ;- (PDC_ADC) Receive Counter Register
-// - ========== Register definition for ADC peripheral ==========
-AT91C_ADC_CDR2            EQU (0xFFFD8038) ;- (ADC) ADC Channel Data Register 2
-AT91C_ADC_CDR3            EQU (0xFFFD803C) ;- (ADC) ADC Channel Data Register 3
-AT91C_ADC_CDR0            EQU (0xFFFD8030) ;- (ADC) ADC Channel Data Register 0
-AT91C_ADC_CDR5            EQU (0xFFFD8044) ;- (ADC) ADC Channel Data Register 5
-AT91C_ADC_CHDR            EQU (0xFFFD8014) ;- (ADC) ADC Channel Disable Register
-AT91C_ADC_SR              EQU (0xFFFD801C) ;- (ADC) ADC Status Register
-AT91C_ADC_CDR4            EQU (0xFFFD8040) ;- (ADC) ADC Channel Data Register 4
-AT91C_ADC_CDR1            EQU (0xFFFD8034) ;- (ADC) ADC Channel Data Register 1
-AT91C_ADC_LCDR            EQU (0xFFFD8020) ;- (ADC) ADC Last Converted Data Register
-AT91C_ADC_IDR             EQU (0xFFFD8028) ;- (ADC) ADC Interrupt Disable Register
-AT91C_ADC_CR              EQU (0xFFFD8000) ;- (ADC) ADC Control Register
-AT91C_ADC_CDR7            EQU (0xFFFD804C) ;- (ADC) ADC Channel Data Register 7
-AT91C_ADC_CDR6            EQU (0xFFFD8048) ;- (ADC) ADC Channel Data Register 6
-AT91C_ADC_IER             EQU (0xFFFD8024) ;- (ADC) ADC Interrupt Enable Register
-AT91C_ADC_CHER            EQU (0xFFFD8010) ;- (ADC) ADC Channel Enable Register
-AT91C_ADC_CHSR            EQU (0xFFFD8018) ;- (ADC) ADC Channel Status Register
-AT91C_ADC_MR              EQU (0xFFFD8004) ;- (ADC) ADC Mode Register
-AT91C_ADC_IMR             EQU (0xFFFD802C) ;- (ADC) ADC Interrupt Mask Register
-// - ========== Register definition for PDC_AES peripheral ==========
-AT91C_AES_TPR             EQU (0xFFFA4108) ;- (PDC_AES) Transmit Pointer Register
-AT91C_AES_PTCR            EQU (0xFFFA4120) ;- (PDC_AES) PDC Transfer Control Register
-AT91C_AES_RNPR            EQU (0xFFFA4110) ;- (PDC_AES) Receive Next Pointer Register
-AT91C_AES_TNCR            EQU (0xFFFA411C) ;- (PDC_AES) Transmit Next Counter Register
-AT91C_AES_TCR             EQU (0xFFFA410C) ;- (PDC_AES) Transmit Counter Register
-AT91C_AES_RCR             EQU (0xFFFA4104) ;- (PDC_AES) Receive Counter Register
-AT91C_AES_RNCR            EQU (0xFFFA4114) ;- (PDC_AES) Receive Next Counter Register
-AT91C_AES_TNPR            EQU (0xFFFA4118) ;- (PDC_AES) Transmit Next Pointer Register
-AT91C_AES_RPR             EQU (0xFFFA4100) ;- (PDC_AES) Receive Pointer Register
-AT91C_AES_PTSR            EQU (0xFFFA4124) ;- (PDC_AES) PDC Transfer Status Register
-// - ========== Register definition for AES peripheral ==========
-AT91C_AES_IVxR            EQU (0xFFFA4060) ;- (AES) Initialization Vector x Register
-AT91C_AES_MR              EQU (0xFFFA4004) ;- (AES) Mode Register
-AT91C_AES_VR              EQU (0xFFFA40FC) ;- (AES) AES Version Register
-AT91C_AES_ODATAxR         EQU (0xFFFA4050) ;- (AES) Output Data x Register
-AT91C_AES_IDATAxR         EQU (0xFFFA4040) ;- (AES) Input Data x Register
-AT91C_AES_CR              EQU (0xFFFA4000) ;- (AES) Control Register
-AT91C_AES_IDR             EQU (0xFFFA4014) ;- (AES) Interrupt Disable Register
-AT91C_AES_IMR             EQU (0xFFFA4018) ;- (AES) Interrupt Mask Register
-AT91C_AES_IER             EQU (0xFFFA4010) ;- (AES) Interrupt Enable Register
-AT91C_AES_KEYWxR          EQU (0xFFFA4020) ;- (AES) Key Word x Register
-AT91C_AES_ISR             EQU (0xFFFA401C) ;- (AES) Interrupt Status Register
-// - ========== Register definition for PDC_TDES peripheral ==========
-AT91C_TDES_RNCR           EQU (0xFFFA8114) ;- (PDC_TDES) Receive Next Counter Register
-AT91C_TDES_TCR            EQU (0xFFFA810C) ;- (PDC_TDES) Transmit Counter Register
-AT91C_TDES_RCR            EQU (0xFFFA8104) ;- (PDC_TDES) Receive Counter Register
-AT91C_TDES_TNPR           EQU (0xFFFA8118) ;- (PDC_TDES) Transmit Next Pointer Register
-AT91C_TDES_RNPR           EQU (0xFFFA8110) ;- (PDC_TDES) Receive Next Pointer Register
-AT91C_TDES_RPR            EQU (0xFFFA8100) ;- (PDC_TDES) Receive Pointer Register
-AT91C_TDES_TNCR           EQU (0xFFFA811C) ;- (PDC_TDES) Transmit Next Counter Register
-AT91C_TDES_TPR            EQU (0xFFFA8108) ;- (PDC_TDES) Transmit Pointer Register
-AT91C_TDES_PTSR           EQU (0xFFFA8124) ;- (PDC_TDES) PDC Transfer Status Register
-AT91C_TDES_PTCR           EQU (0xFFFA8120) ;- (PDC_TDES) PDC Transfer Control Register
-// - ========== Register definition for TDES peripheral ==========
-AT91C_TDES_KEY2WxR        EQU (0xFFFA8028) ;- (TDES) Key 2 Word x Register
-AT91C_TDES_KEY3WxR        EQU (0xFFFA8030) ;- (TDES) Key 3 Word x Register
-AT91C_TDES_IDR            EQU (0xFFFA8014) ;- (TDES) Interrupt Disable Register
-AT91C_TDES_VR             EQU (0xFFFA80FC) ;- (TDES) TDES Version Register
-AT91C_TDES_IVxR           EQU (0xFFFA8060) ;- (TDES) Initialization Vector x Register
-AT91C_TDES_ODATAxR        EQU (0xFFFA8050) ;- (TDES) Output Data x Register
-AT91C_TDES_IMR            EQU (0xFFFA8018) ;- (TDES) Interrupt Mask Register
-AT91C_TDES_MR             EQU (0xFFFA8004) ;- (TDES) Mode Register
-AT91C_TDES_CR             EQU (0xFFFA8000) ;- (TDES) Control Register
-AT91C_TDES_IER            EQU (0xFFFA8010) ;- (TDES) Interrupt Enable Register
-AT91C_TDES_ISR            EQU (0xFFFA801C) ;- (TDES) Interrupt Status Register
-AT91C_TDES_IDATAxR        EQU (0xFFFA8040) ;- (TDES) Input Data x Register
-AT91C_TDES_KEY1WxR        EQU (0xFFFA8020) ;- (TDES) Key 1 Word x Register
+/* - ***************************************************************************** */
+/* -              SOFTWARE API DEFINITION  FOR USB Device Interface */
+/* - ***************************************************************************** */
+/* - -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- */
+                                                          AT91C_UDP_FRM_NUM EQU( 0x7FF << 0 );
+                                                          -( UDP ) Frame Number as Defined in the Packet Field Formats
+                                                          AT91C_UDP_FRM_ERR EQU( 0x1 << 16 );
+                                                          -( UDP ) Frame Error
+                                                          AT91C_UDP_FRM_OK EQU( 0x1 << 17 );
+                                                          -( UDP ) Frame OK
+/* - -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- */
+                                                          AT91C_UDP_FADDEN EQU( 0x1 << 0 );
+                                                          -( UDP ) Function Address Enable
+                                                          AT91C_UDP_CONFG EQU( 0x1 << 1 );
+                                                          -( UDP ) Configured
+                                                          AT91C_UDP_ESR EQU( 0x1 << 2 );
+                                                          -( UDP ) Enable Send Resume
+                                                          AT91C_UDP_RSMINPR EQU( 0x1 << 3 );
+                                                          -( UDP ) A Resume Has Been Sent to the Host
+                                                          AT91C_UDP_RMWUPE EQU( 0x1 << 4 );
+                                                          -( UDP ) Remote Wake Up Enable
+/* - -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- */
+                                                          AT91C_UDP_FADD EQU( 0xFF << 0 );
+                                                          -( UDP ) Function Address Value
+                                                          AT91C_UDP_FEN EQU( 0x1 << 8 );
+                                                          -( UDP ) Function Enable
+/* - -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- */
+                                                          AT91C_UDP_EPINT0 EQU( 0x1 << 0 );
+                                                          -( UDP ) Endpoint 0 Interrupt
+                                                          AT91C_UDP_EPINT1 EQU( 0x1 << 1 );
+                                                          -( UDP ) Endpoint 0 Interrupt
+                                                          AT91C_UDP_EPINT2 EQU( 0x1 << 2 );
+                                                          -( UDP ) Endpoint 2 Interrupt
+                                                          AT91C_UDP_EPINT3 EQU( 0x1 << 3 );
+                                                          -( UDP ) Endpoint 3 Interrupt
+                                                          AT91C_UDP_EPINT4 EQU( 0x1 << 4 );
+                                                          -( UDP ) Endpoint 4 Interrupt
+                                                          AT91C_UDP_EPINT5 EQU( 0x1 << 5 );
+                                                          -( UDP ) Endpoint 5 Interrupt
+                                                          AT91C_UDP_RXSUSP EQU( 0x1 << 8 );
+                                                          -( UDP ) USB Suspend Interrupt
+                                                          AT91C_UDP_RXRSM EQU( 0x1 << 9 );
+                                                          -( UDP ) USB Resume Interrupt
+                                                          AT91C_UDP_EXTRSM EQU( 0x1 << 10 );
+                                                          -( UDP ) USB External Resume Interrupt
+                                                          AT91C_UDP_SOFINT EQU( 0x1 << 11 );
+                                                          -( UDP ) USB Start Of frame Interrupt
+                                                          AT91C_UDP_WAKEUP EQU( 0x1 << 13 );
+                                                          -( UDP ) USB Resume Interrupt
+/* - -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- */
+/* - -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- */
+/* - -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- */
+                                                          AT91C_UDP_ENDBUSRES EQU( 0x1 << 12 );
+                                                          -( UDP ) USB End Of Bus Reset Interrupt
+/* - -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- */
+/* - -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- */
+                                                          AT91C_UDP_EP0 EQU( 0x1 << 0 );
+                                                          -( UDP ) Reset Endpoint 0
+                                                          AT91C_UDP_EP1 EQU( 0x1 << 1 );
+                                                          -( UDP ) Reset Endpoint 1
+                                                          AT91C_UDP_EP2 EQU( 0x1 << 2 );
+                                                          -( UDP ) Reset Endpoint 2
+                                                          AT91C_UDP_EP3 EQU( 0x1 << 3 );
+                                                          -( UDP ) Reset Endpoint 3
+                                                          AT91C_UDP_EP4 EQU( 0x1 << 4 );
+                                                          -( UDP ) Reset Endpoint 4
+                                                          AT91C_UDP_EP5 EQU( 0x1 << 5 );
+                                                          -( UDP ) Reset Endpoint 5
+/* - -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- */
+                                                          AT91C_UDP_TXCOMP EQU( 0x1 << 0 );
+                                                          -( UDP ) Generates an IN packet with data previously written in the DPR
+                                                          AT91C_UDP_RX_DATA_BK0 EQU( 0x1 << 1 );
+                                                          -( UDP ) Receive Data Bank 0
+                                                          AT91C_UDP_RXSETUP EQU( 0x1 << 2 );
+                                                          -( UDP ) Sends STALL to the Host( Control endpoints )
+                                                          AT91C_UDP_ISOERROR EQU( 0x1 << 3 );
+                                                          -( UDP ) Isochronous error( Isochronous endpoints )
+                                                          AT91C_UDP_TXPKTRDY EQU( 0x1 << 4 );
+                                                          -( UDP ) Transmit Packet Ready
+                                                          AT91C_UDP_FORCESTALL EQU( 0x1 << 5 );
+                                                          -( UDP ) Force Stall( used by Control, Bulk and Isochronous endpoints ).
+                                                             AT91C_UDP_RX_DATA_BK1 EQU( 0x1 << 6 );
+                                                          -( UDP ) Receive Data Bank 1 ( only used by endpoints with ping - pong attributes ).
+                                                             AT91C_UDP_DIR EQU( 0x1 << 7 );
+                                                          -( UDP ) Transfer Direction
+                                                          AT91C_UDP_EPTYPE EQU( 0x7 << 8 );
+                                                          -( UDP ) Endpoint type
+                                                          AT91C_UDP_EPTYPE_CTRL EQU( 0x0 << 8 );
+                                                          -( UDP ) Control
+                                                          AT91C_UDP_EPTYPE_ISO_OUT EQU( 0x1 << 8 );
+                                                          -( UDP ) Isochronous OUT
+                                                          AT91C_UDP_EPTYPE_BULK_OUT EQU( 0x2 << 8 );
+                                                          -( UDP ) Bulk OUT
+                                                          AT91C_UDP_EPTYPE_INT_OUT EQU( 0x3 << 8 );
+                                                          -( UDP ) Interrupt OUT
+                                                          AT91C_UDP_EPTYPE_ISO_IN EQU( 0x5 << 8 );
+                                                          -( UDP ) Isochronous IN
+                                                          AT91C_UDP_EPTYPE_BULK_IN EQU( 0x6 << 8 );
+                                                          -( UDP ) Bulk IN
+                                                          AT91C_UDP_EPTYPE_INT_IN EQU( 0x7 << 8 );
+                                                          -( UDP ) Interrupt IN
+                                                          AT91C_UDP_DTGLE EQU( 0x1 << 11 );
+                                                          -( UDP ) Data Toggle
+                                                          AT91C_UDP_EPEDS EQU( 0x1 << 15 );
+                                                          -( UDP ) Endpoint Enable Disable
+                                                          AT91C_UDP_RXBYTECNT EQU( 0x7FF << 16 );
+                                                          -( UDP ) Number Of Bytes Available in the FIFO
+/* - -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- */
+                                                          AT91C_UDP_TXVDIS EQU( 0x1 << 8 );
+                                                          -( UDP )
+                                                          AT91C_UDP_PUON EQU( 0x1 << 9 );
+                                                          -( UDP ) Pull - up ON
 
-// - *****************************************************************************
-// -               PIO DEFINITIONS FOR AT91SAM7X256
-// - *****************************************************************************
-AT91C_PIO_PA0             EQU (1 <<  0) ;- Pin Controlled by PA0
-AT91C_PA0_RXD0            EQU (AT91C_PIO_PA0) ;-  USART 0 Receive Data
-AT91C_PIO_PA1             EQU (1 <<  1) ;- Pin Controlled by PA1
-AT91C_PA1_TXD0            EQU (AT91C_PIO_PA1) ;-  USART 0 Transmit Data
-AT91C_PIO_PA10            EQU (1 << 10) ;- Pin Controlled by PA10
-AT91C_PA10_TWD            EQU (AT91C_PIO_PA10) ;-  TWI Two-wire Serial Data
-AT91C_PIO_PA11            EQU (1 << 11) ;- Pin Controlled by PA11
-AT91C_PA11_TWCK           EQU (AT91C_PIO_PA11) ;-  TWI Two-wire Serial Clock
-AT91C_PIO_PA12            EQU (1 << 12) ;- Pin Controlled by PA12
-AT91C_PA12_NPCS00         EQU (AT91C_PIO_PA12) ;-  SPI 0 Peripheral Chip Select 0
-AT91C_PIO_PA13            EQU (1 << 13) ;- Pin Controlled by PA13
-AT91C_PA13_NPCS01         EQU (AT91C_PIO_PA13) ;-  SPI 0 Peripheral Chip Select 1
-AT91C_PA13_PCK1           EQU (AT91C_PIO_PA13) ;-  PMC Programmable Clock Output 1
-AT91C_PIO_PA14            EQU (1 << 14) ;- Pin Controlled by PA14
-AT91C_PA14_NPCS02         EQU (AT91C_PIO_PA14) ;-  SPI 0 Peripheral Chip Select 2
-AT91C_PA14_IRQ1           EQU (AT91C_PIO_PA14) ;-  External Interrupt 1
-AT91C_PIO_PA15            EQU (1 << 15) ;- Pin Controlled by PA15
-AT91C_PA15_NPCS03         EQU (AT91C_PIO_PA15) ;-  SPI 0 Peripheral Chip Select 3
-AT91C_PA15_TCLK2          EQU (AT91C_PIO_PA15) ;-  Timer Counter 2 external clock input
-AT91C_PIO_PA16            EQU (1 << 16) ;- Pin Controlled by PA16
-AT91C_PA16_MISO0          EQU (AT91C_PIO_PA16) ;-  SPI 0 Master In Slave
-AT91C_PIO_PA17            EQU (1 << 17) ;- Pin Controlled by PA17
-AT91C_PA17_MOSI0          EQU (AT91C_PIO_PA17) ;-  SPI 0 Master Out Slave
-AT91C_PIO_PA18            EQU (1 << 18) ;- Pin Controlled by PA18
-AT91C_PA18_SPCK0          EQU (AT91C_PIO_PA18) ;-  SPI 0 Serial Clock
-AT91C_PIO_PA19            EQU (1 << 19) ;- Pin Controlled by PA19
-AT91C_PA19_CANRX          EQU (AT91C_PIO_PA19) ;-  CAN Receive
-AT91C_PIO_PA2             EQU (1 <<  2) ;- Pin Controlled by PA2
-AT91C_PA2_SCK0            EQU (AT91C_PIO_PA2) ;-  USART 0 Serial Clock
-AT91C_PA2_NPCS11          EQU (AT91C_PIO_PA2) ;-  SPI 1 Peripheral Chip Select 1
-AT91C_PIO_PA20            EQU (1 << 20) ;- Pin Controlled by PA20
-AT91C_PA20_CANTX          EQU (AT91C_PIO_PA20) ;-  CAN Transmit
-AT91C_PIO_PA21            EQU (1 << 21) ;- Pin Controlled by PA21
-AT91C_PA21_TF             EQU (AT91C_PIO_PA21) ;-  SSC Transmit Frame Sync
-AT91C_PA21_NPCS10         EQU (AT91C_PIO_PA21) ;-  SPI 1 Peripheral Chip Select 0
-AT91C_PIO_PA22            EQU (1 << 22) ;- Pin Controlled by PA22
-AT91C_PA22_TK             EQU (AT91C_PIO_PA22) ;-  SSC Transmit Clock
-AT91C_PA22_SPCK1          EQU (AT91C_PIO_PA22) ;-  SPI 1 Serial Clock
-AT91C_PIO_PA23            EQU (1 << 23) ;- Pin Controlled by PA23
-AT91C_PA23_TD             EQU (AT91C_PIO_PA23) ;-  SSC Transmit data
-AT91C_PA23_MOSI1          EQU (AT91C_PIO_PA23) ;-  SPI 1 Master Out Slave
-AT91C_PIO_PA24            EQU (1 << 24) ;- Pin Controlled by PA24
-AT91C_PA24_RD             EQU (AT91C_PIO_PA24) ;-  SSC Receive Data
-AT91C_PA24_MISO1          EQU (AT91C_PIO_PA24) ;-  SPI 1 Master In Slave
-AT91C_PIO_PA25            EQU (1 << 25) ;- Pin Controlled by PA25
-AT91C_PA25_RK             EQU (AT91C_PIO_PA25) ;-  SSC Receive Clock
-AT91C_PA25_NPCS11         EQU (AT91C_PIO_PA25) ;-  SPI 1 Peripheral Chip Select 1
-AT91C_PIO_PA26            EQU (1 << 26) ;- Pin Controlled by PA26
-AT91C_PA26_RF             EQU (AT91C_PIO_PA26) ;-  SSC Receive Frame Sync
-AT91C_PA26_NPCS12         EQU (AT91C_PIO_PA26) ;-  SPI 1 Peripheral Chip Select 2
-AT91C_PIO_PA27            EQU (1 << 27) ;- Pin Controlled by PA27
-AT91C_PA27_DRXD           EQU (AT91C_PIO_PA27) ;-  DBGU Debug Receive Data
-AT91C_PA27_PCK3           EQU (AT91C_PIO_PA27) ;-  PMC Programmable Clock Output 3
-AT91C_PIO_PA28            EQU (1 << 28) ;- Pin Controlled by PA28
-AT91C_PA28_DTXD           EQU (AT91C_PIO_PA28) ;-  DBGU Debug Transmit Data
-AT91C_PIO_PA29            EQU (1 << 29) ;- Pin Controlled by PA29
-AT91C_PA29_FIQ            EQU (AT91C_PIO_PA29) ;-  AIC Fast Interrupt Input
-AT91C_PA29_NPCS13         EQU (AT91C_PIO_PA29) ;-  SPI 1 Peripheral Chip Select 3
-AT91C_PIO_PA3             EQU (1 <<  3) ;- Pin Controlled by PA3
-AT91C_PA3_RTS0            EQU (AT91C_PIO_PA3) ;-  USART 0 Ready To Send
-AT91C_PA3_NPCS12          EQU (AT91C_PIO_PA3) ;-  SPI 1 Peripheral Chip Select 2
-AT91C_PIO_PA30            EQU (1 << 30) ;- Pin Controlled by PA30
-AT91C_PA30_IRQ0           EQU (AT91C_PIO_PA30) ;-  External Interrupt 0
-AT91C_PA30_PCK2           EQU (AT91C_PIO_PA30) ;-  PMC Programmable Clock Output 2
-AT91C_PIO_PA4             EQU (1 <<  4) ;- Pin Controlled by PA4
-AT91C_PA4_CTS0            EQU (AT91C_PIO_PA4) ;-  USART 0 Clear To Send
-AT91C_PA4_NPCS13          EQU (AT91C_PIO_PA4) ;-  SPI 1 Peripheral Chip Select 3
-AT91C_PIO_PA5             EQU (1 <<  5) ;- Pin Controlled by PA5
-AT91C_PA5_RXD1            EQU (AT91C_PIO_PA5) ;-  USART 1 Receive Data
-AT91C_PIO_PA6             EQU (1 <<  6) ;- Pin Controlled by PA6
-AT91C_PA6_TXD1            EQU (AT91C_PIO_PA6) ;-  USART 1 Transmit Data
-AT91C_PIO_PA7             EQU (1 <<  7) ;- Pin Controlled by PA7
-AT91C_PA7_SCK1            EQU (AT91C_PIO_PA7) ;-  USART 1 Serial Clock
-AT91C_PA7_NPCS01          EQU (AT91C_PIO_PA7) ;-  SPI 0 Peripheral Chip Select 1
-AT91C_PIO_PA8             EQU (1 <<  8) ;- Pin Controlled by PA8
-AT91C_PA8_RTS1            EQU (AT91C_PIO_PA8) ;-  USART 1 Ready To Send
-AT91C_PA8_NPCS02          EQU (AT91C_PIO_PA8) ;-  SPI 0 Peripheral Chip Select 2
-AT91C_PIO_PA9             EQU (1 <<  9) ;- Pin Controlled by PA9
-AT91C_PA9_CTS1            EQU (AT91C_PIO_PA9) ;-  USART 1 Clear To Send
-AT91C_PA9_NPCS03          EQU (AT91C_PIO_PA9) ;-  SPI 0 Peripheral Chip Select 3
-AT91C_PIO_PB0             EQU (1 <<  0) ;- Pin Controlled by PB0
-AT91C_PB0_ETXCK_EREFCK    EQU (AT91C_PIO_PB0) ;-  Ethernet MAC Transmit Clock/Reference Clock
-AT91C_PB0_PCK0            EQU (AT91C_PIO_PB0) ;-  PMC Programmable Clock Output 0
-AT91C_PIO_PB1             EQU (1 <<  1) ;- Pin Controlled by PB1
-AT91C_PB1_ETXEN           EQU (AT91C_PIO_PB1) ;-  Ethernet MAC Transmit Enable
-AT91C_PIO_PB10            EQU (1 << 10) ;- Pin Controlled by PB10
-AT91C_PB10_ETX2           EQU (AT91C_PIO_PB10) ;-  Ethernet MAC Transmit Data 2
-AT91C_PB10_NPCS11         EQU (AT91C_PIO_PB10) ;-  SPI 1 Peripheral Chip Select 1
-AT91C_PIO_PB11            EQU (1 << 11) ;- Pin Controlled by PB11
-AT91C_PB11_ETX3           EQU (AT91C_PIO_PB11) ;-  Ethernet MAC Transmit Data 3
-AT91C_PB11_NPCS12         EQU (AT91C_PIO_PB11) ;-  SPI 1 Peripheral Chip Select 2
-AT91C_PIO_PB12            EQU (1 << 12) ;- Pin Controlled by PB12
-AT91C_PB12_ETXER          EQU (AT91C_PIO_PB12) ;-  Ethernet MAC Transmikt Coding Error
-AT91C_PB12_TCLK0          EQU (AT91C_PIO_PB12) ;-  Timer Counter 0 external clock input
-AT91C_PIO_PB13            EQU (1 << 13) ;- Pin Controlled by PB13
-AT91C_PB13_ERX2           EQU (AT91C_PIO_PB13) ;-  Ethernet MAC Receive Data 2
-AT91C_PB13_NPCS01         EQU (AT91C_PIO_PB13) ;-  SPI 0 Peripheral Chip Select 1
-AT91C_PIO_PB14            EQU (1 << 14) ;- Pin Controlled by PB14
-AT91C_PB14_ERX3           EQU (AT91C_PIO_PB14) ;-  Ethernet MAC Receive Data 3
-AT91C_PB14_NPCS02         EQU (AT91C_PIO_PB14) ;-  SPI 0 Peripheral Chip Select 2
-AT91C_PIO_PB15            EQU (1 << 15) ;- Pin Controlled by PB15
-AT91C_PB15_ERXDV          EQU (AT91C_PIO_PB15) ;-  Ethernet MAC Receive Data Valid
-AT91C_PIO_PB16            EQU (1 << 16) ;- Pin Controlled by PB16
-AT91C_PB16_ECOL           EQU (AT91C_PIO_PB16) ;-  Ethernet MAC Collision Detected
-AT91C_PB16_NPCS13         EQU (AT91C_PIO_PB16) ;-  SPI 1 Peripheral Chip Select 3
-AT91C_PIO_PB17            EQU (1 << 17) ;- Pin Controlled by PB17
-AT91C_PB17_ERXCK          EQU (AT91C_PIO_PB17) ;-  Ethernet MAC Receive Clock
-AT91C_PB17_NPCS03         EQU (AT91C_PIO_PB17) ;-  SPI 0 Peripheral Chip Select 3
-AT91C_PIO_PB18            EQU (1 << 18) ;- Pin Controlled by PB18
-AT91C_PB18_EF100          EQU (AT91C_PIO_PB18) ;-  Ethernet MAC Force 100 Mbits/sec
-AT91C_PB18_ADTRG          EQU (AT91C_PIO_PB18) ;-  ADC External Trigger
-AT91C_PIO_PB19            EQU (1 << 19) ;- Pin Controlled by PB19
-AT91C_PB19_PWM0           EQU (AT91C_PIO_PB19) ;-  PWM Channel 0
-AT91C_PB19_TCLK1          EQU (AT91C_PIO_PB19) ;-  Timer Counter 1 external clock input
-AT91C_PIO_PB2             EQU (1 <<  2) ;- Pin Controlled by PB2
-AT91C_PB2_ETX0            EQU (AT91C_PIO_PB2) ;-  Ethernet MAC Transmit Data 0
-AT91C_PIO_PB20            EQU (1 << 20) ;- Pin Controlled by PB20
-AT91C_PB20_PWM1           EQU (AT91C_PIO_PB20) ;-  PWM Channel 1
-AT91C_PB20_PCK0           EQU (AT91C_PIO_PB20) ;-  PMC Programmable Clock Output 0
-AT91C_PIO_PB21            EQU (1 << 21) ;- Pin Controlled by PB21
-AT91C_PB21_PWM2           EQU (AT91C_PIO_PB21) ;-  PWM Channel 2
-AT91C_PB21_PCK1           EQU (AT91C_PIO_PB21) ;-  PMC Programmable Clock Output 1
-AT91C_PIO_PB22            EQU (1 << 22) ;- Pin Controlled by PB22
-AT91C_PB22_PWM3           EQU (AT91C_PIO_PB22) ;-  PWM Channel 3
-AT91C_PB22_PCK2           EQU (AT91C_PIO_PB22) ;-  PMC Programmable Clock Output 2
-AT91C_PIO_PB23            EQU (1 << 23) ;- Pin Controlled by PB23
-AT91C_PB23_TIOA0          EQU (AT91C_PIO_PB23) ;-  Timer Counter 0 Multipurpose Timer I/O Pin A
-AT91C_PB23_DCD1           EQU (AT91C_PIO_PB23) ;-  USART 1 Data Carrier Detect
-AT91C_PIO_PB24            EQU (1 << 24) ;- Pin Controlled by PB24
-AT91C_PB24_TIOB0          EQU (AT91C_PIO_PB24) ;-  Timer Counter 0 Multipurpose Timer I/O Pin B
-AT91C_PB24_DSR1           EQU (AT91C_PIO_PB24) ;-  USART 1 Data Set ready
-AT91C_PIO_PB25            EQU (1 << 25) ;- Pin Controlled by PB25
-AT91C_PB25_TIOA1          EQU (AT91C_PIO_PB25) ;-  Timer Counter 1 Multipurpose Timer I/O Pin A
-AT91C_PB25_DTR1           EQU (AT91C_PIO_PB25) ;-  USART 1 Data Terminal ready
-AT91C_PIO_PB26            EQU (1 << 26) ;- Pin Controlled by PB26
-AT91C_PB26_TIOB1          EQU (AT91C_PIO_PB26) ;-  Timer Counter 1 Multipurpose Timer I/O Pin B
-AT91C_PB26_RI1            EQU (AT91C_PIO_PB26) ;-  USART 1 Ring Indicator
-AT91C_PIO_PB27            EQU (1 << 27) ;- Pin Controlled by PB27
-AT91C_PB27_TIOA2          EQU (AT91C_PIO_PB27) ;-  Timer Counter 2 Multipurpose Timer I/O Pin A
-AT91C_PB27_PWM0           EQU (AT91C_PIO_PB27) ;-  PWM Channel 0
-AT91C_PIO_PB28            EQU (1 << 28) ;- Pin Controlled by PB28
-AT91C_PB28_TIOB2          EQU (AT91C_PIO_PB28) ;-  Timer Counter 2 Multipurpose Timer I/O Pin B
-AT91C_PB28_PWM1           EQU (AT91C_PIO_PB28) ;-  PWM Channel 1
-AT91C_PIO_PB29            EQU (1 << 29) ;- Pin Controlled by PB29
-AT91C_PB29_PCK1           EQU (AT91C_PIO_PB29) ;-  PMC Programmable Clock Output 1
-AT91C_PB29_PWM2           EQU (AT91C_PIO_PB29) ;-  PWM Channel 2
-AT91C_PIO_PB3             EQU (1 <<  3) ;- Pin Controlled by PB3
-AT91C_PB3_ETX1            EQU (AT91C_PIO_PB3) ;-  Ethernet MAC Transmit Data 1
-AT91C_PIO_PB30            EQU (1 << 30) ;- Pin Controlled by PB30
-AT91C_PB30_PCK2           EQU (AT91C_PIO_PB30) ;-  PMC Programmable Clock Output 2
-AT91C_PB30_PWM3           EQU (AT91C_PIO_PB30) ;-  PWM Channel 3
-AT91C_PIO_PB4             EQU (1 <<  4) ;- Pin Controlled by PB4
-AT91C_PB4_ECRS_ECRSDV     EQU (AT91C_PIO_PB4) ;-  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
-AT91C_PIO_PB5             EQU (1 <<  5) ;- Pin Controlled by PB5
-AT91C_PB5_ERX0            EQU (AT91C_PIO_PB5) ;-  Ethernet MAC Receive Data 0
-AT91C_PIO_PB6             EQU (1 <<  6) ;- Pin Controlled by PB6
-AT91C_PB6_ERX1            EQU (AT91C_PIO_PB6) ;-  Ethernet MAC Receive Data 1
-AT91C_PIO_PB7             EQU (1 <<  7) ;- Pin Controlled by PB7
-AT91C_PB7_ERXER           EQU (AT91C_PIO_PB7) ;-  Ethernet MAC Receive Error
-AT91C_PIO_PB8             EQU (1 <<  8) ;- Pin Controlled by PB8
-AT91C_PB8_EMDC            EQU (AT91C_PIO_PB8) ;-  Ethernet MAC Management Data Clock
-AT91C_PIO_PB9             EQU (1 <<  9) ;- Pin Controlled by PB9
-AT91C_PB9_EMDIO           EQU (AT91C_PIO_PB9) ;-  Ethernet MAC Management Data Input/Output
+/* - ***************************************************************************** */
+/* -              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface */
+/* - ***************************************************************************** */
+/* - -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- */
+                                                          AT91C_TC_CLKEN EQU( 0x1 << 0 );
+                                                          -( TC ) Counter Clock Enable Command
+                                                          AT91C_TC_CLKDIS EQU( 0x1 << 1 );
+                                                          -( TC ) Counter Clock Disable Command
+                                                          AT91C_TC_SWTRG EQU( 0x1 << 2 );
+                                                          -( TC ) Software Trigger Command
+/* - -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- */
+                                                          AT91C_TC_CLKS EQU( 0x7 << 0 );
+                                                          -( TC ) Clock Selection
+                                                          AT91C_TC_CLKS_TIMER_DIV1_CLOCK EQU( 0x0 );
+                                                          -( TC ) Clock selected:TIMER_DIV1_CLOCK
+                                                          AT91C_TC_CLKS_TIMER_DIV2_CLOCK EQU( 0x1 );
+                                                          -( TC ) Clock selected:TIMER_DIV2_CLOCK
+                                                          AT91C_TC_CLKS_TIMER_DIV3_CLOCK EQU( 0x2 );
+                                                          -( TC ) Clock selected:TIMER_DIV3_CLOCK
+                                                          AT91C_TC_CLKS_TIMER_DIV4_CLOCK EQU( 0x3 );
+                                                          -( TC ) Clock selected:TIMER_DIV4_CLOCK
+                                                          AT91C_TC_CLKS_TIMER_DIV5_CLOCK EQU( 0x4 );
+                                                          -( TC ) Clock selected:TIMER_DIV5_CLOCK
+                                                          AT91C_TC_CLKS_XC0 EQU( 0x5 );
+                                                          -( TC ) Clock selected:XC0
+                                                          AT91C_TC_CLKS_XC1 EQU( 0x6 );
+                                                          -( TC ) Clock selected:XC1
+                                                          AT91C_TC_CLKS_XC2 EQU( 0x7 );
+                                                          -( TC ) Clock selected:XC2
+                                                          AT91C_TC_CLKI EQU( 0x1 << 3 );
+                                                          -( TC ) Clock Invert
+                                                          AT91C_TC_BURST EQU( 0x3 << 4 );
+                                                          -( TC ) Burst Signal Selection
+                                                          AT91C_TC_BURST_NONE EQU( 0x0 << 4 );
+                                                          -( TC ) The clock is not gated by an external signal
+                                                          AT91C_TC_BURST_XC0 EQU( 0x1 << 4 );
+                                                          -( TC ) XC0 is ANDed with the selected clock
+                                                          AT91C_TC_BURST_XC1 EQU( 0x2 << 4 );
+                                                          -( TC ) XC1 is ANDed with the selected clock
+                                                          AT91C_TC_BURST_XC2 EQU( 0x3 << 4 );
+                                                          -( TC ) XC2 is ANDed with the selected clock
+                                                          AT91C_TC_CPCSTOP EQU( 0x1 << 6 );
+                                                          -( TC ) Counter Clock Stopped with RC Compare
+                                                          AT91C_TC_LDBSTOP EQU( 0x1 << 6 );
+                                                          -( TC ) Counter Clock Stopped with RB Loading
+                                                          AT91C_TC_CPCDIS EQU( 0x1 << 7 );
+                                                          -( TC ) Counter Clock Disable with RC Compare
+                                                          AT91C_TC_LDBDIS EQU( 0x1 << 7 );
+                                                          -( TC ) Counter Clock Disabled with RB Loading
+                                                          AT91C_TC_ETRGEDG EQU( 0x3 << 8 );
+                                                          -( TC ) External Trigger Edge Selection
+                                                          AT91C_TC_ETRGEDG_NONE EQU( 0x0 << 8 );
+                                                          -( TC ) Edge:None
+                                                          AT91C_TC_ETRGEDG_RISING EQU( 0x1 << 8 );
+                                                          -( TC ) Edge:rising edge
+                                                          AT91C_TC_ETRGEDG_FALLING EQU( 0x2 << 8 );
+                                                          -( TC ) Edge:falling edge
+                                                          AT91C_TC_ETRGEDG_BOTH EQU( 0x3 << 8 );
+                                                          -( TC ) Edge:each edge
+                                                          AT91C_TC_EEVTEDG EQU( 0x3 << 8 );
+                                                          -( TC ) External Event Edge Selection
+                                                          AT91C_TC_EEVTEDG_NONE EQU( 0x0 << 8 );
+                                                          -( TC ) Edge:None
+                                                          AT91C_TC_EEVTEDG_RISING EQU( 0x1 << 8 );
+                                                          -( TC ) Edge:rising edge
+                                                          AT91C_TC_EEVTEDG_FALLING EQU( 0x2 << 8 );
+                                                          -( TC ) Edge:falling edge
+                                                          AT91C_TC_EEVTEDG_BOTH EQU( 0x3 << 8 );
+                                                          -( TC ) Edge:each edge
+                                                          AT91C_TC_EEVT EQU( 0x3 << 10 );
+                                                          -( TC ) External Event Selection
+                                                          AT91C_TC_EEVT_TIOB EQU( 0x0 << 10 );
+                                                          -( TC ) Signal selected as external event:TIOB TIOB direction: input
+                                                          AT91C_TC_EEVT_XC0 EQU( 0x1 << 10 );
+                                                          -( TC ) Signal selected as external event:XC0 TIOB direction: output
+                                                          AT91C_TC_EEVT_XC1 EQU( 0x2 << 10 );
+                                                          -( TC ) Signal selected as external event:XC1 TIOB direction: output
+                                                          AT91C_TC_EEVT_XC2 EQU( 0x3 << 10 );
+                                                          -( TC ) Signal selected as external event:XC2 TIOB direction: output
+                                                          AT91C_TC_ABETRG EQU( 0x1 << 10 );
+                                                          -( TC ) TIOA or TIOB External Trigger Selection
+                                                          AT91C_TC_ENETRG EQU( 0x1 << 12 );
+                                                          -( TC ) External Event Trigger enable
+                                                          AT91C_TC_WAVESEL EQU( 0x3 << 13 );
+                                                          -( TC ) Waveform Selection
+                                                          AT91C_TC_WAVESEL_UP EQU( 0x0 << 13 );
+                                                          -( TC ) UP mode without atomatic trigger on RC Compare
+                                                          AT91C_TC_WAVESEL_UPDOWN EQU( 0x1 << 13 );
+                                                          -( TC ) UPDOWN mode without automatic trigger on RC Compare
+                                                          AT91C_TC_WAVESEL_UP_AUTO EQU( 0x2 << 13 );
+                                                          -( TC ) UP mode with automatic trigger on RC Compare
+                                                          AT91C_TC_WAVESEL_UPDOWN_AUTO EQU( 0x3 << 13 );
+                                                          -( TC ) UPDOWN mode with automatic trigger on RC Compare
+                                                          AT91C_TC_CPCTRG EQU( 0x1 << 14 );
+                                                          -( TC ) RC Compare Trigger Enable
+                                                          AT91C_TC_WAVE EQU( 0x1 << 15 );
+                                                          -( TC )
+                                                          AT91C_TC_ACPA EQU( 0x3 << 16 );
+                                                          -( TC ) RA Compare Effect on TIOA
+                                                          AT91C_TC_ACPA_NONE EQU( 0x0 << 16 );
+                                                          -( TC ) Effect:none
+                                                          AT91C_TC_ACPA_SET EQU( 0x1 << 16 );
+                                                          -( TC ) Effect:set
+                                                          AT91C_TC_ACPA_CLEAR EQU( 0x2 << 16 );
+                                                          -( TC ) Effect:clear
+                                                          AT91C_TC_ACPA_TOGGLE EQU( 0x3 << 16 );
+                                                          -( TC ) Effect:toggle
+                                                          AT91C_TC_LDRA EQU( 0x3 << 16 );
+                                                          -( TC ) RA Loading Selection
+                                                          AT91C_TC_LDRA_NONE EQU( 0x0 << 16 );
+                                                          -( TC ) Edge:None
+                                                          AT91C_TC_LDRA_RISING EQU( 0x1 << 16 );
+                                                          -( TC ) Edge:rising edge of TIOA
+                                                          AT91C_TC_LDRA_FALLING EQU( 0x2 << 16 );
+                                                          -( TC ) Edge:falling edge of TIOA
+                                                          AT91C_TC_LDRA_BOTH EQU( 0x3 << 16 );
+                                                          -( TC ) Edge:each edge of TIOA
+                                                          AT91C_TC_ACPC EQU( 0x3 << 18 );
+                                                          -( TC ) RC Compare Effect on TIOA
+                                                          AT91C_TC_ACPC_NONE EQU( 0x0 << 18 );
+                                                          -( TC ) Effect:none
+                                                          AT91C_TC_ACPC_SET EQU( 0x1 << 18 );
+                                                          -( TC ) Effect:set
+                                                          AT91C_TC_ACPC_CLEAR EQU( 0x2 << 18 );
+                                                          -( TC ) Effect:clear
+                                                          AT91C_TC_ACPC_TOGGLE EQU( 0x3 << 18 );
+                                                          -( TC ) Effect:toggle
+                                                          AT91C_TC_LDRB EQU( 0x3 << 18 );
+                                                          -( TC ) RB Loading Selection
+                                                          AT91C_TC_LDRB_NONE EQU( 0x0 << 18 );
+                                                          -( TC ) Edge:None
+                                                          AT91C_TC_LDRB_RISING EQU( 0x1 << 18 );
+                                                          -( TC ) Edge:rising edge of TIOA
+                                                          AT91C_TC_LDRB_FALLING EQU( 0x2 << 18 );
+                                                          -( TC ) Edge:falling edge of TIOA
+                                                          AT91C_TC_LDRB_BOTH EQU( 0x3 << 18 );
+                                                          -( TC ) Edge:each edge of TIOA
+                                                          AT91C_TC_AEEVT EQU( 0x3 << 20 );
+                                                          -( TC ) External Event Effect on TIOA
+                                                          AT91C_TC_AEEVT_NONE EQU( 0x0 << 20 );
+                                                          -( TC ) Effect:none
+                                                          AT91C_TC_AEEVT_SET EQU( 0x1 << 20 );
+                                                          -( TC ) Effect:set
+                                                          AT91C_TC_AEEVT_CLEAR EQU( 0x2 << 20 );
+                                                          -( TC ) Effect:clear
+                                                          AT91C_TC_AEEVT_TOGGLE EQU( 0x3 << 20 );
+                                                          -( TC ) Effect:toggle
+                                                          AT91C_TC_ASWTRG EQU( 0x3 << 22 );
+                                                          -( TC ) Software Trigger Effect on TIOA
+                                                          AT91C_TC_ASWTRG_NONE EQU( 0x0 << 22 );
+                                                          -( TC ) Effect:none
+                                                          AT91C_TC_ASWTRG_SET EQU( 0x1 << 22 );
+                                                          -( TC ) Effect:set
+                                                          AT91C_TC_ASWTRG_CLEAR EQU( 0x2 << 22 );
+                                                          -( TC ) Effect:clear
+                                                          AT91C_TC_ASWTRG_TOGGLE EQU( 0x3 << 22 );
+                                                          -( TC ) Effect:toggle
+                                                          AT91C_TC_BCPB EQU( 0x3 << 24 );
+                                                          -( TC ) RB Compare Effect on TIOB
+                                                          AT91C_TC_BCPB_NONE EQU( 0x0 << 24 );
+                                                          -( TC ) Effect:none
+                                                          AT91C_TC_BCPB_SET EQU( 0x1 << 24 );
+                                                          -( TC ) Effect:set
+                                                          AT91C_TC_BCPB_CLEAR EQU( 0x2 << 24 );
+                                                          -( TC ) Effect:clear
+                                                          AT91C_TC_BCPB_TOGGLE EQU( 0x3 << 24 );
+                                                          -( TC ) Effect:toggle
+                                                          AT91C_TC_BCPC EQU( 0x3 << 26 );
+                                                          -( TC ) RC Compare Effect on TIOB
+                                                          AT91C_TC_BCPC_NONE EQU( 0x0 << 26 );
+                                                          -( TC ) Effect:none
+                                                          AT91C_TC_BCPC_SET EQU( 0x1 << 26 );
+                                                          -( TC ) Effect:set
+                                                          AT91C_TC_BCPC_CLEAR EQU( 0x2 << 26 );
+                                                          -( TC ) Effect:clear
+                                                          AT91C_TC_BCPC_TOGGLE EQU( 0x3 << 26 );
+                                                          -( TC ) Effect:toggle
+                                                          AT91C_TC_BEEVT EQU( 0x3 << 28 );
+                                                          -( TC ) External Event Effect on TIOB
+                                                          AT91C_TC_BEEVT_NONE EQU( 0x0 << 28 );
+                                                          -( TC ) Effect:none
+                                                          AT91C_TC_BEEVT_SET EQU( 0x1 << 28 );
+                                                          -( TC ) Effect:set
+                                                          AT91C_TC_BEEVT_CLEAR EQU( 0x2 << 28 );
+                                                          -( TC ) Effect:clear
+                                                          AT91C_TC_BEEVT_TOGGLE EQU( 0x3 << 28 );
+                                                          -( TC ) Effect:toggle
+                                                          AT91C_TC_BSWTRG EQU( 0x3 << 30 );
+                                                          -( TC ) Software Trigger Effect on TIOB
+                                                          AT91C_TC_BSWTRG_NONE EQU( 0x0 << 30 );
+                                                          -( TC ) Effect:none
+                                                          AT91C_TC_BSWTRG_SET EQU( 0x1 << 30 );
+                                                          -( TC ) Effect:set
+                                                          AT91C_TC_BSWTRG_CLEAR EQU( 0x2 << 30 );
+                                                          -( TC ) Effect:clear
+                                                          AT91C_TC_BSWTRG_TOGGLE EQU( 0x3 << 30 );
+                                                          -( TC ) Effect:toggle
+/* - -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- */
+                                                          AT91C_TC_COVFS EQU( 0x1 << 0 );
+                                                          -( TC ) Counter Overflow
+                                                          AT91C_TC_LOVRS EQU( 0x1 << 1 );
+                                                          -( TC ) Load Overrun
+                                                          AT91C_TC_CPAS EQU( 0x1 << 2 );
+                                                          -( TC ) RA Compare
+                                                          AT91C_TC_CPBS EQU( 0x1 << 3 );
+                                                          -( TC ) RB Compare
+                                                          AT91C_TC_CPCS EQU( 0x1 << 4 );
+                                                          -( TC ) RC Compare
+                                                          AT91C_TC_LDRAS EQU( 0x1 << 5 );
+                                                          -( TC ) RA Loading
+                                                          AT91C_TC_LDRBS EQU( 0x1 << 6 );
+                                                          -( TC ) RB Loading
+                                                          AT91C_TC_ETRGS EQU( 0x1 << 7 );
+                                                          -( TC ) External Trigger
+                                                          AT91C_TC_CLKSTA EQU( 0x1 << 16 );
+                                                          -( TC ) Clock Enabling
+                                                          AT91C_TC_MTIOA EQU( 0x1 << 17 );
+                                                          -( TC ) TIOA Mirror
+                                                          AT91C_TC_MTIOB EQU( 0x1 << 18 );
+                                                          -( TC ) TIOA Mirror
+/* - -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- */
+/* - -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- */
+/* - -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- */
 
-// - *****************************************************************************
-// -               PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256
-// - *****************************************************************************
-AT91C_ID_FIQ              EQU ( 0) ;- Advanced Interrupt Controller (FIQ)
-AT91C_ID_SYS              EQU ( 1) ;- System Peripheral
-AT91C_ID_PIOA             EQU ( 2) ;- Parallel IO Controller A
-AT91C_ID_PIOB             EQU ( 3) ;- Parallel IO Controller B
-AT91C_ID_SPI0             EQU ( 4) ;- Serial Peripheral Interface 0
-AT91C_ID_SPI1             EQU ( 5) ;- Serial Peripheral Interface 1
-AT91C_ID_US0              EQU ( 6) ;- USART 0
-AT91C_ID_US1              EQU ( 7) ;- USART 1
-AT91C_ID_SSC              EQU ( 8) ;- Serial Synchronous Controller
-AT91C_ID_TWI              EQU ( 9) ;- Two-Wire Interface
-AT91C_ID_PWMC             EQU (10) ;- PWM Controller
-AT91C_ID_UDP              EQU (11) ;- USB Device Port
-AT91C_ID_TC0              EQU (12) ;- Timer Counter 0
-AT91C_ID_TC1              EQU (13) ;- Timer Counter 1
-AT91C_ID_TC2              EQU (14) ;- Timer Counter 2
-AT91C_ID_CAN              EQU (15) ;- Control Area Network Controller
-AT91C_ID_EMAC             EQU (16) ;- Ethernet MAC
-AT91C_ID_ADC              EQU (17) ;- Analog-to-Digital Converter
-AT91C_ID_AES              EQU (18) ;- Advanced Encryption Standard 128-bit
-AT91C_ID_TDES             EQU (19) ;- Triple Data Encryption Standard
-AT91C_ID_20_Reserved      EQU (20) ;- Reserved
-AT91C_ID_21_Reserved      EQU (21) ;- Reserved
-AT91C_ID_22_Reserved      EQU (22) ;- Reserved
-AT91C_ID_23_Reserved      EQU (23) ;- Reserved
-AT91C_ID_24_Reserved      EQU (24) ;- Reserved
-AT91C_ID_25_Reserved      EQU (25) ;- Reserved
-AT91C_ID_26_Reserved      EQU (26) ;- Reserved
-AT91C_ID_27_Reserved      EQU (27) ;- Reserved
-AT91C_ID_28_Reserved      EQU (28) ;- Reserved
-AT91C_ID_29_Reserved      EQU (29) ;- Reserved
-AT91C_ID_IRQ0             EQU (30) ;- Advanced Interrupt Controller (IRQ0)
-AT91C_ID_IRQ1             EQU (31) ;- Advanced Interrupt Controller (IRQ1)
+/* - ***************************************************************************** */
+/* -              SOFTWARE API DEFINITION  FOR Timer Counter Interface */
+/* - ***************************************************************************** */
+/* - -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- */
+                                                          AT91C_TCB_SYNC EQU( 0x1 << 0 );
+                                                          -( TCB ) Synchro Command
+/* - -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- */
+                                                          AT91C_TCB_TC0XC0S EQU( 0x3 << 0 );
+                                                          -( TCB ) External Clock Signal 0 Selection
+                                                          AT91C_TCB_TC0XC0S_TCLK0 EQU( 0x0 );
+                                                          -( TCB ) TCLK0 connected to XC0
+                                                          AT91C_TCB_TC0XC0S_NONE EQU( 0x1 );
+                                                          -( TCB ) None signal connected to XC0
+                                                          AT91C_TCB_TC0XC0S_TIOA1 EQU( 0x2 );
+                                                          -( TCB ) TIOA1 connected to XC0
+                                                          AT91C_TCB_TC0XC0S_TIOA2 EQU( 0x3 );
+                                                          -( TCB ) TIOA2 connected to XC0
+                                                          AT91C_TCB_TC1XC1S EQU( 0x3 << 2 );
+                                                          -( TCB ) External Clock Signal 1 Selection
+                                                          AT91C_TCB_TC1XC1S_TCLK1 EQU( 0x0 << 2 );
+                                                          -( TCB ) TCLK1 connected to XC1
+                                                          AT91C_TCB_TC1XC1S_NONE EQU( 0x1 << 2 );
+                                                          -( TCB ) None signal connected to XC1
+                                                          AT91C_TCB_TC1XC1S_TIOA0 EQU( 0x2 << 2 );
+                                                          -( TCB ) TIOA0 connected to XC1
+                                                          AT91C_TCB_TC1XC1S_TIOA2 EQU( 0x3 << 2 );
+                                                          -( TCB ) TIOA2 connected to XC1
+                                                          AT91C_TCB_TC2XC2S EQU( 0x3 << 4 );
+                                                          -( TCB ) External Clock Signal 2 Selection
+                                                          AT91C_TCB_TC2XC2S_TCLK2 EQU( 0x0 << 4 );
+                                                          -( TCB ) TCLK2 connected to XC2
+                                                          AT91C_TCB_TC2XC2S_NONE EQU( 0x1 << 4 );
+                                                          -( TCB ) None signal connected to XC2
+                                                          AT91C_TCB_TC2XC2S_TIOA0 EQU( 0x2 << 4 );
+                                                          -( TCB ) TIOA0 connected to XC2
+                                                          AT91C_TCB_TC2XC2S_TIOA1 EQU( 0x3 << 4 );
+                                                          -( TCB ) TIOA2 connected to XC2
 
-// - *****************************************************************************
-// -               BASE ADDRESS DEFINITIONS FOR AT91SAM7X256
-// - *****************************************************************************
-AT91C_BASE_SYS            EQU (0xFFFFF000) ;- (SYS) Base Address
-AT91C_BASE_AIC            EQU (0xFFFFF000) ;- (AIC) Base Address
-AT91C_BASE_PDC_DBGU       EQU (0xFFFFF300) ;- (PDC_DBGU) Base Address
-AT91C_BASE_DBGU           EQU (0xFFFFF200) ;- (DBGU) Base Address
-AT91C_BASE_PIOA           EQU (0xFFFFF400) ;- (PIOA) Base Address
-AT91C_BASE_PIOB           EQU (0xFFFFF600) ;- (PIOB) Base Address
-AT91C_BASE_CKGR           EQU (0xFFFFFC20) ;- (CKGR) Base Address
-AT91C_BASE_PMC            EQU (0xFFFFFC00) ;- (PMC) Base Address
-AT91C_BASE_RSTC           EQU (0xFFFFFD00) ;- (RSTC) Base Address
-AT91C_BASE_RTTC           EQU (0xFFFFFD20) ;- (RTTC) Base Address
-AT91C_BASE_PITC           EQU (0xFFFFFD30) ;- (PITC) Base Address
-AT91C_BASE_WDTC           EQU (0xFFFFFD40) ;- (WDTC) Base Address
-AT91C_BASE_VREG           EQU (0xFFFFFD60) ;- (VREG) Base Address
-AT91C_BASE_MC             EQU (0xFFFFFF00) ;- (MC) Base Address
-AT91C_BASE_PDC_SPI1       EQU (0xFFFE4100) ;- (PDC_SPI1) Base Address
-AT91C_BASE_SPI1           EQU (0xFFFE4000) ;- (SPI1) Base Address
-AT91C_BASE_PDC_SPI0       EQU (0xFFFE0100) ;- (PDC_SPI0) Base Address
-AT91C_BASE_SPI0           EQU (0xFFFE0000) ;- (SPI0) Base Address
-AT91C_BASE_PDC_US1        EQU (0xFFFC4100) ;- (PDC_US1) Base Address
-AT91C_BASE_US1            EQU (0xFFFC4000) ;- (US1) Base Address
-AT91C_BASE_PDC_US0        EQU (0xFFFC0100) ;- (PDC_US0) Base Address
-AT91C_BASE_US0            EQU (0xFFFC0000) ;- (US0) Base Address
-AT91C_BASE_PDC_SSC        EQU (0xFFFD4100) ;- (PDC_SSC) Base Address
-AT91C_BASE_SSC            EQU (0xFFFD4000) ;- (SSC) Base Address
-AT91C_BASE_TWI            EQU (0xFFFB8000) ;- (TWI) Base Address
-AT91C_BASE_PWMC_CH3       EQU (0xFFFCC260) ;- (PWMC_CH3) Base Address
-AT91C_BASE_PWMC_CH2       EQU (0xFFFCC240) ;- (PWMC_CH2) Base Address
-AT91C_BASE_PWMC_CH1       EQU (0xFFFCC220) ;- (PWMC_CH1) Base Address
-AT91C_BASE_PWMC_CH0       EQU (0xFFFCC200) ;- (PWMC_CH0) Base Address
-AT91C_BASE_PWMC           EQU (0xFFFCC000) ;- (PWMC) Base Address
-AT91C_BASE_UDP            EQU (0xFFFB0000) ;- (UDP) Base Address
-AT91C_BASE_TC0            EQU (0xFFFA0000) ;- (TC0) Base Address
-AT91C_BASE_TC1            EQU (0xFFFA0040) ;- (TC1) Base Address
-AT91C_BASE_TC2            EQU (0xFFFA0080) ;- (TC2) Base Address
-AT91C_BASE_TCB            EQU (0xFFFA0000) ;- (TCB) Base Address
-AT91C_BASE_CAN_MB0        EQU (0xFFFD0200) ;- (CAN_MB0) Base Address
-AT91C_BASE_CAN_MB1        EQU (0xFFFD0220) ;- (CAN_MB1) Base Address
-AT91C_BASE_CAN_MB2        EQU (0xFFFD0240) ;- (CAN_MB2) Base Address
-AT91C_BASE_CAN_MB3        EQU (0xFFFD0260) ;- (CAN_MB3) Base Address
-AT91C_BASE_CAN_MB4        EQU (0xFFFD0280) ;- (CAN_MB4) Base Address
-AT91C_BASE_CAN_MB5        EQU (0xFFFD02A0) ;- (CAN_MB5) Base Address
-AT91C_BASE_CAN_MB6        EQU (0xFFFD02C0) ;- (CAN_MB6) Base Address
-AT91C_BASE_CAN_MB7        EQU (0xFFFD02E0) ;- (CAN_MB7) Base Address
-AT91C_BASE_CAN            EQU (0xFFFD0000) ;- (CAN) Base Address
-AT91C_BASE_EMAC           EQU (0xFFFDC000) ;- (EMAC) Base Address
-AT91C_BASE_PDC_ADC        EQU (0xFFFD8100) ;- (PDC_ADC) Base Address
-AT91C_BASE_ADC            EQU (0xFFFD8000) ;- (ADC) Base Address
-AT91C_BASE_PDC_AES        EQU (0xFFFA4100) ;- (PDC_AES) Base Address
-AT91C_BASE_AES            EQU (0xFFFA4000) ;- (AES) Base Address
-AT91C_BASE_PDC_TDES       EQU (0xFFFA8100) ;- (PDC_TDES) Base Address
-AT91C_BASE_TDES           EQU (0xFFFA8000) ;- (TDES) Base Address
+/* - ***************************************************************************** */
+/* -              SOFTWARE API DEFINITION  FOR Control Area Network MailBox Interface */
+/* - ***************************************************************************** */
+/* - -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- */
+                                                          AT91C_CAN_MTIMEMARK EQU( 0xFFFF << 0 );
+                                                          -( CAN_MB ) Mailbox Timemark
+                                                          AT91C_CAN_PRIOR EQU( 0xF << 16 );
+                                                          -( CAN_MB ) Mailbox Priority
+                                                          AT91C_CAN_MOT EQU( 0x7 << 24 );
+                                                          -( CAN_MB ) Mailbox Object Type
+                                                          AT91C_CAN_MOT_DIS EQU( 0x0 << 24 );
+                                                          -( CAN_MB )
+                                                          AT91C_CAN_MOT_RX EQU( 0x1 << 24 );
+                                                          -( CAN_MB )
+                                                          AT91C_CAN_MOT_RXOVERWRITE EQU( 0x2 << 24 );
+                                                          -( CAN_MB )
+                                                          AT91C_CAN_MOT_TX EQU( 0x3 << 24 );
+                                                          -( CAN_MB )
+                                                          AT91C_CAN_MOT_CONSUMER EQU( 0x4 << 24 );
+                                                          -( CAN_MB )
+                                                          AT91C_CAN_MOT_PRODUCER EQU( 0x5 << 24 );
+                                                          -( CAN_MB )
+/* - -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- */
+                                                          AT91C_CAN_MIDvB EQU( 0x3FFFF << 0 );
+                                                          -( CAN_MB ) Complementary bits
 
-// - *****************************************************************************
-// -               MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256
-// - *****************************************************************************
-AT91C_ISRAM               EQU (0x00200000) ;- Internal SRAM base address
-AT91C_ISRAM_SIZE          EQU (0x00010000) ;- Internal SRAM size in byte (64 Kbyte)
-AT91C_IFLASH              EQU (0x00100000) ;- Internal ROM base address
-AT91C_IFLASH_SIZE         EQU (0x00040000) ;- Internal ROM size in byte (256 Kbyte)
+                                                          for identifier in extended mode
+                                                          AT91C_CAN_MIDvA EQU( 0x7FF << 18 );
+                                                          -( CAN_MB ) Identifier
+
+                                                          for standard frame mode
+                                                          AT91C_CAN_MIDE EQU( 0x1 << 29 );
+                                                          -( CAN_MB ) Identifier Version
+/* - -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- */
+/* - -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- */
+/* - -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- */
+                                                          AT91C_CAN_MTIMESTAMP EQU( 0xFFFF << 0 );
+                                                          -( CAN_MB ) Timer Value
+                                                          AT91C_CAN_MDLC EQU( 0xF << 16 );
+                                                          -( CAN_MB ) Mailbox Data Length Code
+                                                          AT91C_CAN_MRTR EQU( 0x1 << 20 );
+                                                          -( CAN_MB ) Mailbox Remote Transmission Request
+                                                          AT91C_CAN_MABT EQU( 0x1 << 22 );
+                                                          -( CAN_MB ) Mailbox Message Abort
+                                                          AT91C_CAN_MRDY EQU( 0x1 << 23 );
+                                                          -( CAN_MB ) Mailbox Ready
+                                                          AT91C_CAN_MMI EQU( 0x1 << 24 );
+                                                          -( CAN_MB ) Mailbox Message Ignored
+/* - -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- */
+/* - -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- */
+/* - -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- */
+                                                          AT91C_CAN_MACR EQU( 0x1 << 22 );
+                                                          -( CAN_MB ) Abort Request
+
+                                                          for Mailbox
+                                                          AT91C_CAN_MTCR EQU( 0x1 << 23 );
+                                                          -( CAN_MB ) Mailbox Transfer Command
+
+/* - ***************************************************************************** */
+/* -              SOFTWARE API DEFINITION  FOR Control Area Network Interface */
+/* - ***************************************************************************** */
+/* - -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- */
+                                                          AT91C_CAN_CANEN EQU( 0x1 << 0 );
+                                                          -( CAN ) CAN Controller Enable
+                                                          AT91C_CAN_LPM EQU( 0x1 << 1 );
+                                                          -( CAN ) Disable / Enable Low Power Mode
+                                                          AT91C_CAN_ABM EQU( 0x1 << 2 );
+                                                          -( CAN ) Disable / Enable Autobaud / Listen Mode
+                                                          AT91C_CAN_OVL EQU( 0x1 << 3 );
+                                                          -( CAN ) Disable / Enable Overload Frame
+                                                          AT91C_CAN_TEOF EQU( 0x1 << 4 );
+                                                          -( CAN ) Time Stamp messages at each end of Frame
+                                                          AT91C_CAN_TTM EQU( 0x1 << 5 );
+                                                          -( CAN ) Disable / Enable Time Trigger Mode
+                                                          AT91C_CAN_TIMFRZ EQU( 0x1 << 6 );
+                                                          -( CAN ) Enable Timer Freeze
+                                                          AT91C_CAN_DRPT EQU( 0x1 << 7 );
+                                                          -( CAN ) Disable Repeat
+/* - -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- */
+                                                          AT91C_CAN_MB0 EQU( 0x1 << 0 );
+                                                          -( CAN ) Mailbox 0 Flag
+                                                          AT91C_CAN_MB1 EQU( 0x1 << 1 );
+                                                          -( CAN ) Mailbox 1 Flag
+                                                          AT91C_CAN_MB2 EQU( 0x1 << 2 );
+                                                          -( CAN ) Mailbox 2 Flag
+                                                          AT91C_CAN_MB3 EQU( 0x1 << 3 );
+                                                          -( CAN ) Mailbox 3 Flag
+                                                          AT91C_CAN_MB4 EQU( 0x1 << 4 );
+                                                          -( CAN ) Mailbox 4 Flag
+                                                          AT91C_CAN_MB5 EQU( 0x1 << 5 );
+                                                          -( CAN ) Mailbox 5 Flag
+                                                          AT91C_CAN_MB6 EQU( 0x1 << 6 );
+                                                          -( CAN ) Mailbox 6 Flag
+                                                          AT91C_CAN_MB7 EQU( 0x1 << 7 );
+                                                          -( CAN ) Mailbox 7 Flag
+                                                          AT91C_CAN_MB8 EQU( 0x1 << 8 );
+                                                          -( CAN ) Mailbox 8 Flag
+                                                          AT91C_CAN_MB9 EQU( 0x1 << 9 );
+                                                          -( CAN ) Mailbox 9 Flag
+                                                          AT91C_CAN_MB10 EQU( 0x1 << 10 );
+                                                          -( CAN ) Mailbox 10 Flag
+                                                          AT91C_CAN_MB11 EQU( 0x1 << 11 );
+                                                          -( CAN ) Mailbox 11 Flag
+                                                          AT91C_CAN_MB12 EQU( 0x1 << 12 );
+                                                          -( CAN ) Mailbox 12 Flag
+                                                          AT91C_CAN_MB13 EQU( 0x1 << 13 );
+                                                          -( CAN ) Mailbox 13 Flag
+                                                          AT91C_CAN_MB14 EQU( 0x1 << 14 );
+                                                          -( CAN ) Mailbox 14 Flag
+                                                          AT91C_CAN_MB15 EQU( 0x1 << 15 );
+                                                          -( CAN ) Mailbox 15 Flag
+                                                          AT91C_CAN_ERRA EQU( 0x1 << 16 );
+                                                          -( CAN ) Error Active Mode Flag
+                                                          AT91C_CAN_WARN EQU( 0x1 << 17 );
+                                                          -( CAN ) Warning Limit Flag
+                                                          AT91C_CAN_ERRP EQU( 0x1 << 18 );
+                                                          -( CAN ) Error Passive Mode Flag
+                                                          AT91C_CAN_BOFF EQU( 0x1 << 19 );
+                                                          -( CAN ) Bus Off Mode Flag
+                                                          AT91C_CAN_SLEEP EQU( 0x1 << 20 );
+                                                          -( CAN ) Sleep Flag
+                                                          AT91C_CAN_WAKEUP EQU( 0x1 << 21 );
+                                                          -( CAN ) Wakeup Flag
+                                                          AT91C_CAN_TOVF EQU( 0x1 << 22 );
+                                                          -( CAN ) Timer Overflow Flag
+                                                          AT91C_CAN_TSTP EQU( 0x1 << 23 );
+                                                          -( CAN ) Timestamp Flag
+                                                          AT91C_CAN_CERR EQU( 0x1 << 24 );
+                                                          -( CAN ) CRC Error
+                                                          AT91C_CAN_SERR EQU( 0x1 << 25 );
+                                                          -( CAN ) Stuffing Error
+                                                          AT91C_CAN_AERR EQU( 0x1 << 26 );
+                                                          -( CAN ) Acknowledgment Error
+                                                          AT91C_CAN_FERR EQU( 0x1 << 27 );
+                                                          -( CAN ) Form Error
+                                                          AT91C_CAN_BERR EQU( 0x1 << 28 );
+                                                          -( CAN ) Bit Error
+/* - -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- */
+/* - -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- */
+/* - -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- */
+                                                          AT91C_CAN_RBSY EQU( 0x1 << 29 );
+                                                          -( CAN ) Receiver Busy
+                                                          AT91C_CAN_TBSY EQU( 0x1 << 30 );
+                                                          -( CAN ) Transmitter Busy
+                                                          AT91C_CAN_OVLY EQU( 0x1 << 31 );
+                                                          -( CAN ) Overload Busy
+/* - -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- */
+                                                          AT91C_CAN_PHASE2 EQU( 0x7 << 0 );
+                                                          -( CAN ) Phase 2 segment
+                                                          AT91C_CAN_PHASE1 EQU( 0x7 << 4 );
+                                                          -( CAN ) Phase 1 segment
+                                                          AT91C_CAN_PROPAG EQU( 0x7 << 8 );
+                                                          -( CAN ) Programmation time segment
+                                                          AT91C_CAN_SYNC EQU( 0x3 << 12 );
+                                                          -( CAN ) Re - synchronization jump width segment
+                                                          AT91C_CAN_BRP EQU( 0x7F << 16 );
+                                                          -( CAN ) Baudrate Prescaler
+                                                          AT91C_CAN_SMP EQU( 0x1 << 24 );
+                                                          -( CAN ) Sampling mode
+/* - -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- */
+                                                          AT91C_CAN_TIMER EQU( 0xFFFF << 0 );
+                                                          -( CAN ) Timer field
+/* - -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- */
+/* - -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- */
+                                                          AT91C_CAN_REC EQU( 0xFF << 0 );
+                                                          -( CAN ) Receive Error Counter
+                                                          AT91C_CAN_TEC EQU( 0xFF << 16 );
+                                                          -( CAN ) Transmit Error Counter
+/* - -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- */
+                                                          AT91C_CAN_TIMRST EQU( 0x1 << 31 );
+                                                          -( CAN ) Timer Reset Field
+/* - -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- */
+
+/* - ***************************************************************************** */
+/* -              SOFTWARE API DEFINITION  FOR Ethernet MAC 10/100 */
+/* - ***************************************************************************** */
+/* - -------- EMAC_NCR : (EMAC Offset: 0x0)  -------- */
+                                                          AT91C_EMAC_LB EQU( 0x1 << 0 );
+                                                          -( EMAC ) Loopback.Optional.When set, loopback signal is at high level.
+                                                             AT91C_EMAC_LLB EQU( 0x1 << 1 );
+                                                          -( EMAC ) Loopback local.
+                                                             AT91C_EMAC_RE EQU( 0x1 << 2 );
+                                                          -( EMAC ) Receive enable.
+                                                             AT91C_EMAC_TE EQU( 0x1 << 3 );
+                                                          -( EMAC ) Transmit enable.
+                                                             AT91C_EMAC_MPE EQU( 0x1 << 4 );
+                                                          -( EMAC ) Management port enable.
+                                                             AT91C_EMAC_CLRSTAT EQU( 0x1 << 5 );
+                                                          -( EMAC ) Clear statistics registers.
+                                                             AT91C_EMAC_INCSTAT EQU( 0x1 << 6 );
+                                                          -( EMAC ) Increment statistics registers.
+                                                             AT91C_EMAC_WESTAT EQU( 0x1 << 7 );
+                                                          -( EMAC ) Write enable
+
+                                                          for statistics registers.
+                                                             AT91C_EMAC_BP EQU( 0x1 << 8 );
+                                                          -( EMAC ) Back pressure.
+                                                             AT91C_EMAC_TSTART EQU( 0x1 << 9 );
+                                                          -( EMAC ) Start Transmission.
+                                                             AT91C_EMAC_THALT EQU( 0x1 << 10 );
+                                                          -( EMAC ) Transmission Halt.
+                                                             AT91C_EMAC_TPFR EQU( 0x1 << 11 );
+                                                          -( EMAC ) Transmit pause frame
+                                                          AT91C_EMAC_TZQ EQU( 0x1 << 12 );
+                                                          -( EMAC ) Transmit zero quantum pause frame
+/* - -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- */
+                                                          AT91C_EMAC_SPD EQU( 0x1 << 0 );
+                                                          -( EMAC ) Speed.
+                                                             AT91C_EMAC_FD EQU( 0x1 << 1 );
+                                                          -( EMAC ) Full duplex.
+                                                             AT91C_EMAC_JFRAME EQU( 0x1 << 3 );
+                                                          -( EMAC ) Jumbo Frames.
+                                                             AT91C_EMAC_CAF EQU( 0x1 << 4 );
+                                                          -( EMAC ) Copy all frames.
+                                                             AT91C_EMAC_NBC EQU( 0x1 << 5 );
+                                                          -( EMAC ) No broadcast.
+                                                             AT91C_EMAC_MTI EQU( 0x1 << 6 );
+                                                          -( EMAC ) Multicast hash event enable
+                                                          AT91C_EMAC_UNI EQU( 0x1 << 7 );
+                                                          -( EMAC ) Unicast hash enable.
+                                                             AT91C_EMAC_BIG EQU( 0x1 << 8 );
+                                                          -( EMAC ) Receive 1522 bytes.
+                                                             AT91C_EMAC_EAE EQU( 0x1 << 9 );
+                                                          -( EMAC ) External address match enable.
+                                                             AT91C_EMAC_CLK EQU( 0x3 << 10 );
+                                                          -( EMAC )
+                                                          AT91C_EMAC_CLK_HCLK_8 EQU( 0x0 << 10 );
+                                                          -( EMAC ) HCLK divided by 8
+                                                          AT91C_EMAC_CLK_HCLK_16 EQU( 0x1 << 10 );
+                                                          -( EMAC ) HCLK divided by 16
+                                                          AT91C_EMAC_CLK_HCLK_32 EQU( 0x2 << 10 );
+                                                          -( EMAC ) HCLK divided by 32
+                                                          AT91C_EMAC_CLK_HCLK_64 EQU( 0x3 << 10 );
+                                                          -( EMAC ) HCLK divided by 64
+                                                          AT91C_EMAC_RTY EQU( 0x1 << 12 );
+                                                          -( EMAC )
+                                                          AT91C_EMAC_PAE EQU( 0x1 << 13 );
+                                                          -( EMAC )
+                                                          AT91C_EMAC_RBOF EQU( 0x3 << 14 );
+                                                          -( EMAC )
+                                                          AT91C_EMAC_RBOF_OFFSET_0 EQU( 0x0 << 14 );
+                                                          -( EMAC ) no offset from start of receive buffer
+                                                          AT91C_EMAC_RBOF_OFFSET_1 EQU( 0x1 << 14 );
+                                                          -( EMAC ) one byte offset from start of receive buffer
+                                                          AT91C_EMAC_RBOF_OFFSET_2 EQU( 0x2 << 14 );
+                                                          -( EMAC ) two bytes offset from start of receive buffer
+                                                          AT91C_EMAC_RBOF_OFFSET_3 EQU( 0x3 << 14 );
+                                                          -( EMAC ) three bytes offset from start of receive buffer
+                                                          AT91C_EMAC_RLCE EQU( 0x1 << 16 );
+                                                          -( EMAC ) Receive Length field Checking Enable
+                                                          AT91C_EMAC_DRFCS EQU( 0x1 << 17 );
+                                                          -( EMAC ) Discard Receive FCS
+                                                          AT91C_EMAC_EFRHD EQU( 0x1 << 18 );
+                                                          -( EMAC )
+                                                          AT91C_EMAC_IRXFCS EQU( 0x1 << 19 );
+                                                          -( EMAC ) Ignore RX FCS
+/* - -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- */
+                                                          AT91C_EMAC_LINKR EQU( 0x1 << 0 );
+                                                          -( EMAC )
+                                                          AT91C_EMAC_MDIO EQU( 0x1 << 1 );
+                                                          -( EMAC )
+                                                          AT91C_EMAC_IDLE EQU( 0x1 << 2 );
+                                                          -( EMAC )
+/* - -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- */
+                                                          AT91C_EMAC_UBR EQU( 0x1 << 0 );
+                                                          -( EMAC )
+                                                          AT91C_EMAC_COL EQU( 0x1 << 1 );
+                                                          -( EMAC )
+                                                          AT91C_EMAC_RLES EQU( 0x1 << 2 );
+                                                          -( EMAC )
+                                                          AT91C_EMAC_TGO EQU( 0x1 << 3 );
+                                                          -( EMAC ) Transmit Go
+                                                          AT91C_EMAC_BEX EQU( 0x1 << 4 );
+                                                          -( EMAC ) Buffers exhausted mid frame
+                                                          AT91C_EMAC_COMP EQU( 0x1 << 5 );
+                                                          -( EMAC )
+                                                          AT91C_EMAC_UND EQU( 0x1 << 6 );
+                                                          -( EMAC )
+/* - -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- */
+                                                          AT91C_EMAC_BNA EQU( 0x1 << 0 );
+                                                          -( EMAC )
+                                                          AT91C_EMAC_REC EQU( 0x1 << 1 );
+                                                          -( EMAC )
+                                                          AT91C_EMAC_OVR EQU( 0x1 << 2 );
+                                                          -( EMAC )
+/* - -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- */
+                                                          AT91C_EMAC_MFD EQU( 0x1 << 0 );
+                                                          -( EMAC )
+                                                          AT91C_EMAC_RCOMP EQU( 0x1 << 1 );
+                                                          -( EMAC )
+                                                          AT91C_EMAC_RXUBR EQU( 0x1 << 2 );
+                                                          -( EMAC )
+                                                          AT91C_EMAC_TXUBR EQU( 0x1 << 3 );
+                                                          -( EMAC )
+                                                          AT91C_EMAC_TUNDR EQU( 0x1 << 4 );
+                                                          -( EMAC )
+                                                          AT91C_EMAC_RLEX EQU( 0x1 << 5 );
+                                                          -( EMAC )
+                                                          AT91C_EMAC_TXERR EQU( 0x1 << 6 );
+                                                          -( EMAC )
+                                                          AT91C_EMAC_TCOMP EQU( 0x1 << 7 );
+                                                          -( EMAC )
+                                                          AT91C_EMAC_LINK EQU( 0x1 << 9 );
+                                                          -( EMAC )
+                                                          AT91C_EMAC_ROVR EQU( 0x1 << 10 );
+                                                          -( EMAC )
+                                                          AT91C_EMAC_HRESP EQU( 0x1 << 11 );
+                                                          -( EMAC )
+                                                          AT91C_EMAC_PFRE EQU( 0x1 << 12 );
+                                                          -( EMAC )
+                                                          AT91C_EMAC_PTZ EQU( 0x1 << 13 );
+                                                          -( EMAC )
+/* - -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- */
+/* - -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- */
+/* - -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */
+/* - -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- */
+                                                          AT91C_EMAC_DATA EQU( 0xFFFF << 0 );
+                                                          -( EMAC )
+                                                          AT91C_EMAC_CODE EQU( 0x3 << 16 );
+                                                          -( EMAC )
+                                                          AT91C_EMAC_REGA EQU( 0x1F << 18 );
+                                                          -( EMAC )
+                                                          AT91C_EMAC_PHYA EQU( 0x1F << 23 );
+                                                          -( EMAC )
+                                                          AT91C_EMAC_RW EQU( 0x3 << 28 );
+                                                          -( EMAC )
+                                                          AT91C_EMAC_SOF EQU( 0x3 << 30 );
+                                                          -( EMAC )
+/* - -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- */
+                                                          AT91C_EMAC_RMII EQU( 0x1 << 0 );
+                                                          -( EMAC ) Reduce MII
+/* - -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- */
+                                                          AT91C_EMAC_IP EQU( 0xFFFF << 0 );
+                                                          -( EMAC ) ARP request IP address
+                                                          AT91C_EMAC_MAG EQU( 0x1 << 16 );
+                                                          -( EMAC ) Magic packet event enable
+                                                          AT91C_EMAC_ARP EQU( 0x1 << 17 );
+                                                          -( EMAC ) ARP request event enable
+                                                          AT91C_EMAC_SA1 EQU( 0x1 << 18 );
+                                                          -( EMAC ) Specific address register 1 event enable
+/* - -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- */
+                                                          AT91C_EMAC_REVREF EQU( 0xFFFF << 0 );
+                                                          -( EMAC )
+                                                          AT91C_EMAC_PARTREF EQU( 0xFFFF << 16 );
+                                                          -( EMAC )
+
+/* - ***************************************************************************** */
+/* -              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor */
+/* - ***************************************************************************** */
+/* - -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- */
+                                                          AT91C_ADC_SWRST EQU( 0x1 << 0 );
+                                                          -( ADC ) Software Reset
+                                                          AT91C_ADC_START EQU( 0x1 << 1 );
+                                                          -( ADC ) Start Conversion
+/* - -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- */
+                                                          AT91C_ADC_TRGEN EQU( 0x1 << 0 );
+                                                          -( ADC ) Trigger Enable
+                                                          AT91C_ADC_TRGEN_DIS EQU( 0x0 );
+                                                          -( ADC ) Hardware triggers are disabled.Starting a conversion is only possible by software
+                                                          AT91C_ADC_TRGEN_EN EQU( 0x1 );
+                                                          -( ADC ) Hardware trigger selected by TRGSEL field is enabled.
+                                                             AT91C_ADC_TRGSEL EQU( 0x7 << 1 );
+                                                          -( ADC ) Trigger Selection
+                                                          AT91C_ADC_TRGSEL_TIOA0 EQU( 0x0 << 1 );
+                                                          -( ADC ) Selected TRGSEL = TIAO0
+                                                                                     AT91C_ADC_TRGSEL_TIOA1 EQU( 0x1 << 1 );
+                                                          -( ADC ) Selected TRGSEL = TIAO1
+                                                                                     AT91C_ADC_TRGSEL_TIOA2 EQU( 0x2 << 1 );
+                                                          -( ADC ) Selected TRGSEL = TIAO2
+                                                                                     AT91C_ADC_TRGSEL_TIOA3 EQU( 0x3 << 1 );
+                                                          -( ADC ) Selected TRGSEL = TIAO3
+                                                                                     AT91C_ADC_TRGSEL_TIOA4 EQU( 0x4 << 1 );
+                                                          -( ADC ) Selected TRGSEL = TIAO4
+                                                                                     AT91C_ADC_TRGSEL_TIOA5 EQU( 0x5 << 1 );
+                                                          -( ADC ) Selected TRGSEL = TIAO5
+                                                                                     AT91C_ADC_TRGSEL_EXT EQU( 0x6 << 1 );
+                                                          -( ADC ) Selected TRGSEL = External Trigger
+                                                                                     AT91C_ADC_LOWRES EQU( 0x1 << 4 );
+                                                          -( ADC ) Resolution.
+                                                             AT91C_ADC_LOWRES_10_BIT EQU( 0x0 << 4 );
+                                                          -( ADC ) 10 - bit resolution
+                                                          AT91C_ADC_LOWRES_8_BIT EQU( 0x1 << 4 );
+                                                          -( ADC ) 8 - bit resolution
+                                                          AT91C_ADC_SLEEP EQU( 0x1 << 5 );
+                                                          -( ADC ) Sleep Mode
+                                                          AT91C_ADC_SLEEP_NORMAL_MODE EQU( 0x0 << 5 );
+                                                          -( ADC ) Normal Mode
+                                                          AT91C_ADC_SLEEP_MODE EQU( 0x1 << 5 );
+                                                          -( ADC ) Sleep Mode
+                                                          AT91C_ADC_PRESCAL EQU( 0x3F << 8 );
+                                                          -( ADC ) Prescaler rate selection
+                                                          AT91C_ADC_STARTUP EQU( 0x1F << 16 );
+                                                          -( ADC ) Startup Time
+                                                          AT91C_ADC_SHTIM EQU( 0xF << 24 );
+                                                          -( ADC ) Sample & Hold Time
+/* - --------   ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- */
+                                                          AT91C_ADC_CH0 EQU( 0x1 << 0 );
+                                                          -( ADC ) Channel 0
+                                                          AT91C_ADC_CH1 EQU( 0x1 << 1 );
+                                                          -( ADC ) Channel 1
+                                                          AT91C_ADC_CH2 EQU( 0x1 << 2 );
+                                                          -( ADC ) Channel 2
+                                                          AT91C_ADC_CH3 EQU( 0x1 << 3 );
+                                                          -( ADC ) Channel 3
+                                                          AT91C_ADC_CH4 EQU( 0x1 << 4 );
+                                                          -( ADC ) Channel 4
+                                                          AT91C_ADC_CH5 EQU( 0x1 << 5 );
+                                                          -( ADC ) Channel 5
+                                                          AT91C_ADC_CH6 EQU( 0x1 << 6 );
+                                                          -( ADC ) Channel 6
+                                                          AT91C_ADC_CH7 EQU( 0x1 << 7 );
+                                                          -( ADC ) Channel 7
+/* - --------   ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- */
+/* - --------   ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- */
+/* - -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- */
+                                                          AT91C_ADC_EOC0 EQU( 0x1 << 0 );
+                                                          -( ADC ) End of Conversion
+                                                          AT91C_ADC_EOC1 EQU( 0x1 << 1 );
+                                                          -( ADC ) End of Conversion
+                                                          AT91C_ADC_EOC2 EQU( 0x1 << 2 );
+                                                          -( ADC ) End of Conversion
+                                                          AT91C_ADC_EOC3 EQU( 0x1 << 3 );
+                                                          -( ADC ) End of Conversion
+                                                          AT91C_ADC_EOC4 EQU( 0x1 << 4 );
+                                                          -( ADC ) End of Conversion
+                                                          AT91C_ADC_EOC5 EQU( 0x1 << 5 );
+                                                          -( ADC ) End of Conversion
+                                                          AT91C_ADC_EOC6 EQU( 0x1 << 6 );
+                                                          -( ADC ) End of Conversion
+                                                          AT91C_ADC_EOC7 EQU( 0x1 << 7 );
+                                                          -( ADC ) End of Conversion
+                                                          AT91C_ADC_OVRE0 EQU( 0x1 << 8 );
+                                                          -( ADC ) Overrun Error
+                                                          AT91C_ADC_OVRE1 EQU( 0x1 << 9 );
+                                                          -( ADC ) Overrun Error
+                                                          AT91C_ADC_OVRE2 EQU( 0x1 << 10 );
+                                                          -( ADC ) Overrun Error
+                                                          AT91C_ADC_OVRE3 EQU( 0x1 << 11 );
+                                                          -( ADC ) Overrun Error
+                                                          AT91C_ADC_OVRE4 EQU( 0x1 << 12 );
+                                                          -( ADC ) Overrun Error
+                                                          AT91C_ADC_OVRE5 EQU( 0x1 << 13 );
+                                                          -( ADC ) Overrun Error
+                                                          AT91C_ADC_OVRE6 EQU( 0x1 << 14 );
+                                                          -( ADC ) Overrun Error
+                                                          AT91C_ADC_OVRE7 EQU( 0x1 << 15 );
+                                                          -( ADC ) Overrun Error
+                                                          AT91C_ADC_DRDY EQU( 0x1 << 16 );
+                                                          -( ADC ) Data Ready
+                                                          AT91C_ADC_GOVRE EQU( 0x1 << 17 );
+                                                          -( ADC ) General Overrun
+                                                          AT91C_ADC_ENDRX EQU( 0x1 << 18 );
+                                                          -( ADC ) End of Receiver Transfer
+                                                          AT91C_ADC_RXBUFF EQU( 0x1 << 19 );
+                                                          -( ADC ) RXBUFF Interrupt
+/* - -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- */
+                                                          AT91C_ADC_LDATA EQU( 0x3FF << 0 );
+                                                          -( ADC ) Last Data Converted
+/* - -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- */
+/* - -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- */
+/* - -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- */
+/* - -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- */
+                                                          AT91C_ADC_DATA EQU( 0x3FF << 0 );
+                                                          -( ADC ) Converted Data
+/* - -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- */
+/* - -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- */
+/* - -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- */
+/* - -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- */
+/* - -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- */
+/* - -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- */
+/* - -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- */
+
+/* - ***************************************************************************** */
+/* -              SOFTWARE API DEFINITION  FOR Advanced  Encryption Standard */
+/* - ***************************************************************************** */
+/* - -------- AES_CR : (AES Offset: 0x0) Control Register -------- */
+                                                          AT91C_AES_START EQU( 0x1 << 0 );
+                                                          -( AES ) Starts Processing
+                                                          AT91C_AES_SWRST EQU( 0x1 << 8 );
+                                                          -( AES ) Software Reset
+                                                          AT91C_AES_LOADSEED EQU( 0x1 << 16 );
+                                                          -( AES ) Random Number Generator Seed Loading
+/* - -------- AES_MR : (AES Offset: 0x4) Mode Register -------- */
+                                                          AT91C_AES_CIPHER EQU( 0x1 << 0 );
+                                                          -( AES ) Processing Mode
+                                                          AT91C_AES_PROCDLY EQU( 0xF << 4 );
+                                                          -( AES ) Processing Delay
+                                                          AT91C_AES_SMOD EQU( 0x3 << 8 );
+                                                          -( AES ) Start Mode
+                                                          AT91C_AES_SMOD_MANUAL EQU( 0x0 << 8 );
+                                                          -( AES ) Manual Mode:The START bit in register AES_CR must be set to begin encryption or decryption.
+                                                             AT91C_AES_SMOD_AUTO EQU( 0x1 << 8 );
+                                                          -( AES ) Auto Mode:no action in AES_CR is necessary( cf datasheet ).
+                                                             AT91C_AES_SMOD_PDC EQU( 0x2 << 8 );
+                                                          -( AES ) PDC Mode( cf datasheet ).
+                                                             AT91C_AES_OPMOD EQU( 0x7 << 12 );
+                                                          -( AES ) Operation Mode
+                                                          AT91C_AES_OPMOD_ECB EQU( 0x0 << 12 );
+                                                          -( AES ) ECB Electronic CodeBook mode.
+                                                             AT91C_AES_OPMOD_CBC EQU( 0x1 << 12 );
+                                                          -( AES ) CBC Cipher Block Chaining mode.
+                                                             AT91C_AES_OPMOD_OFB EQU( 0x2 << 12 );
+                                                          -( AES ) OFB Output Feedback mode.
+                                                             AT91C_AES_OPMOD_CFB EQU( 0x3 << 12 );
+                                                          -( AES ) CFB Cipher Feedback mode.
+                                                             AT91C_AES_OPMOD_CTR EQU( 0x4 << 12 );
+                                                          -( AES ) CTR Counter mode.
+                                                             AT91C_AES_LOD EQU( 0x1 << 15 );
+                                                          -( AES ) Last Output Data Mode
+                                                          AT91C_AES_CFBS EQU( 0x7 << 16 );
+                                                          -( AES ) Cipher Feedback Data Size
+                                                          AT91C_AES_CFBS_128_BIT EQU( 0x0 << 16 );
+                                                          -( AES ) 128 - bit.
+                                                             AT91C_AES_CFBS_64_BIT EQU( 0x1 << 16 );
+                                                          -( AES ) 64 - bit.
+                                                             AT91C_AES_CFBS_32_BIT EQU( 0x2 << 16 );
+                                                          -( AES ) 32 - bit.
+                                                             AT91C_AES_CFBS_16_BIT EQU( 0x3 << 16 );
+                                                          -( AES ) 16 - bit.
+                                                             AT91C_AES_CFBS_8_BIT EQU( 0x4 << 16 );
+                                                          -( AES ) 8 - bit.
+                                                             AT91C_AES_CKEY EQU( 0xF << 20 );
+                                                          -( AES ) Countermeasure Key
+                                                          AT91C_AES_CTYPE EQU( 0x1F << 24 );
+                                                          -( AES ) Countermeasure Type
+                                                          AT91C_AES_CTYPE_TYPE1_EN EQU( 0x1 << 24 );
+                                                          -( AES ) Countermeasure type 1 is enabled.
+                                                             AT91C_AES_CTYPE_TYPE2_EN EQU( 0x2 << 24 );
+                                                          -( AES ) Countermeasure type 2 is enabled.
+                                                             AT91C_AES_CTYPE_TYPE3_EN EQU( 0x4 << 24 );
+                                                          -( AES ) Countermeasure type 3 is enabled.
+                                                             AT91C_AES_CTYPE_TYPE4_EN EQU( 0x8 << 24 );
+                                                          -( AES ) Countermeasure type 4 is enabled.
+                                                             AT91C_AES_CTYPE_TYPE5_EN EQU( 0x10 << 24 );
+                                                          -( AES ) Countermeasure type 5 is enabled.
+/* - -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- */
+                                                             AT91C_AES_DATRDY EQU( 0x1 << 0 );
+                                                          -( AES ) DATRDY
+                                                          AT91C_AES_ENDRX EQU( 0x1 << 1 );
+                                                          -( AES ) PDC Read Buffer End
+                                                          AT91C_AES_ENDTX EQU( 0x1 << 2 );
+                                                          -( AES ) PDC Write Buffer End
+                                                          AT91C_AES_RXBUFF EQU( 0x1 << 3 );
+                                                          -( AES ) PDC Read Buffer Full
+                                                          AT91C_AES_TXBUFE EQU( 0x1 << 4 );
+                                                          -( AES ) PDC Write Buffer Empty
+                                                          AT91C_AES_URAD EQU( 0x1 << 8 );
+                                                          -( AES ) Unspecified Register Access Detection
+/* - -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- */
+/* - -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- */
+/* - -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- */
+                                                          AT91C_AES_URAT EQU( 0x7 << 12 );
+                                                          -( AES ) Unspecified Register Access Type Status
+                                                          AT91C_AES_URAT_IN_DAT_WRITE_DATPROC EQU( 0x0 << 12 );
+                                                          -( AES ) Input data register written during the data processing in PDC mode.
+                                                             AT91C_AES_URAT_OUT_DAT_READ_DATPROC EQU( 0x1 << 12 );
+                                                          -( AES ) Output data register read during the data processing.
+                                                             AT91C_AES_URAT_MODEREG_WRITE_DATPROC EQU( 0x2 << 12 );
+                                                          -( AES ) Mode register written during the data processing.
+                                                             AT91C_AES_URAT_OUT_DAT_READ_SUBKEY EQU( 0x3 << 12 );
+                                                          -( AES ) Output data register read during the sub - keys generation.
+                                                             AT91C_AES_URAT_MODEREG_WRITE_SUBKEY EQU( 0x4 << 12 );
+                                                          -( AES ) Mode register written during the sub - keys generation.
+                                                             AT91C_AES_URAT_WO_REG_READ EQU( 0x5 << 12 );
+                                                          -( AES ) Write - only register read access.
+
+/* - ***************************************************************************** */
+/* -              SOFTWARE API DEFINITION  FOR Triple Data Encryption Standard */
+/* - ***************************************************************************** */
+/* - -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- */
+                                                             AT91C_TDES_START EQU( 0x1 << 0 );
+                                                          -( TDES ) Starts Processing
+                                                          AT91C_TDES_SWRST EQU( 0x1 << 8 );
+                                                          -( TDES ) Software Reset
+/* - -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- */
+                                                          AT91C_TDES_CIPHER EQU( 0x1 << 0 );
+                                                          -( TDES ) Processing Mode
+                                                          AT91C_TDES_TDESMOD EQU( 0x1 << 1 );
+                                                          -( TDES ) Single or Triple DES Mode
+                                                          AT91C_TDES_KEYMOD EQU( 0x1 << 4 );
+                                                          -( TDES ) Key Mode
+                                                          AT91C_TDES_SMOD EQU( 0x3 << 8 );
+                                                          -( TDES ) Start Mode
+                                                          AT91C_TDES_SMOD_MANUAL EQU( 0x0 << 8 );
+                                                          -( TDES ) Manual Mode:The START bit in register TDES_CR must be set to begin encryption or decryption.
+                                                             AT91C_TDES_SMOD_AUTO EQU( 0x1 << 8 );
+                                                          -( TDES ) Auto Mode:no action in TDES_CR is necessary( cf datasheet ).
+                                                             AT91C_TDES_SMOD_PDC EQU( 0x2 << 8 );
+                                                          -( TDES ) PDC Mode( cf datasheet ).
+                                                             AT91C_TDES_OPMOD EQU( 0x3 << 12 );
+                                                          -( TDES ) Operation Mode
+                                                          AT91C_TDES_OPMOD_ECB EQU( 0x0 << 12 );
+                                                          -( TDES ) ECB Electronic CodeBook mode.
+                                                             AT91C_TDES_OPMOD_CBC EQU( 0x1 << 12 );
+                                                          -( TDES ) CBC Cipher Block Chaining mode.
+                                                             AT91C_TDES_OPMOD_OFB EQU( 0x2 << 12 );
+                                                          -( TDES ) OFB Output Feedback mode.
+                                                             AT91C_TDES_OPMOD_CFB EQU( 0x3 << 12 );
+                                                          -( TDES ) CFB Cipher Feedback mode.
+                                                             AT91C_TDES_LOD EQU( 0x1 << 15 );
+                                                          -( TDES ) Last Output Data Mode
+                                                          AT91C_TDES_CFBS EQU( 0x3 << 16 );
+                                                          -( TDES ) Cipher Feedback Data Size
+                                                          AT91C_TDES_CFBS_64_BIT EQU( 0x0 << 16 );
+                                                          -( TDES ) 64 - bit.
+                                                             AT91C_TDES_CFBS_32_BIT EQU( 0x1 << 16 );
+                                                          -( TDES ) 32 - bit.
+                                                             AT91C_TDES_CFBS_16_BIT EQU( 0x2 << 16 );
+                                                          -( TDES ) 16 - bit.
+                                                             AT91C_TDES_CFBS_8_BIT EQU( 0x3 << 16 );
+                                                          -( TDES ) 8 - bit.
+/* - -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- */
+                                                             AT91C_TDES_DATRDY EQU( 0x1 << 0 );
+                                                          -( TDES ) DATRDY
+                                                          AT91C_TDES_ENDRX EQU( 0x1 << 1 );
+                                                          -( TDES ) PDC Read Buffer End
+                                                          AT91C_TDES_ENDTX EQU( 0x1 << 2 );
+                                                          -( TDES ) PDC Write Buffer End
+                                                          AT91C_TDES_RXBUFF EQU( 0x1 << 3 );
+                                                          -( TDES ) PDC Read Buffer Full
+                                                          AT91C_TDES_TXBUFE EQU( 0x1 << 4 );
+                                                          -( TDES ) PDC Write Buffer Empty
+                                                          AT91C_TDES_URAD EQU( 0x1 << 8 );
+                                                          -( TDES ) Unspecified Register Access Detection
+/* - -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- */
+/* - -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- */
+/* - -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- */
+                                                          AT91C_TDES_URAT EQU( 0x3 << 12 );
+                                                          -( TDES ) Unspecified Register Access Type Status
+                                                          AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC EQU( 0x0 << 12 );
+                                                          -( TDES ) Input data register written during the data processing in PDC mode.
+                                                             AT91C_TDES_URAT_OUT_DAT_READ_DATPROC EQU( 0x1 << 12 );
+                                                          -( TDES ) Output data register read during the data processing.
+                                                             AT91C_TDES_URAT_MODEREG_WRITE_DATPROC EQU( 0x2 << 12 );
+                                                          -( TDES ) Mode register written during the data processing.
+                                                             AT91C_TDES_URAT_WO_REG_READ EQU( 0x3 << 12 );
+                                                          -( TDES ) Write - only register read access.
+
+/* - ***************************************************************************** */
+/* -               REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 */
+/* - ***************************************************************************** */
+/* - ========== Register definition for SYS peripheral ========== */
+/* - ========== Register definition for AIC peripheral ========== */
+                                                             AT91C_AIC_IVR EQU( 0xFFFFF100 );
+                                                          -( AIC ) IRQ Vector Register
+                                                          AT91C_AIC_SMR EQU( 0xFFFFF000 );
+                                                          -( AIC ) Source Mode Register
+                                                          AT91C_AIC_FVR EQU( 0xFFFFF104 );
+                                                          -( AIC ) FIQ Vector Register
+                                                          AT91C_AIC_DCR EQU( 0xFFFFF138 );
+                                                          -( AIC ) Debug Control Register( Protect )
+                                                          AT91C_AIC_EOICR EQU( 0xFFFFF130 );
+                                                          -( AIC ) End of Interrupt Command Register
+                                                          AT91C_AIC_SVR EQU( 0xFFFFF080 );
+                                                          -( AIC ) Source Vector Register
+                                                          AT91C_AIC_FFSR EQU( 0xFFFFF148 );
+                                                          -( AIC ) Fast Forcing Status Register
+                                                          AT91C_AIC_ICCR EQU( 0xFFFFF128 );
+                                                          -( AIC ) Interrupt Clear Command Register
+                                                          AT91C_AIC_ISR EQU( 0xFFFFF108 );
+                                                          -( AIC ) Interrupt Status Register
+                                                          AT91C_AIC_IMR EQU( 0xFFFFF110 );
+                                                          -( AIC ) Interrupt Mask Register
+                                                          AT91C_AIC_IPR EQU( 0xFFFFF10C );
+                                                          -( AIC ) Interrupt Pending Register
+                                                          AT91C_AIC_FFER EQU( 0xFFFFF140 );
+                                                          -( AIC ) Fast Forcing Enable Register
+                                                          AT91C_AIC_IECR EQU( 0xFFFFF120 );
+                                                          -( AIC ) Interrupt Enable Command Register
+                                                          AT91C_AIC_ISCR EQU( 0xFFFFF12C );
+                                                          -( AIC ) Interrupt Set Command Register
+                                                          AT91C_AIC_FFDR EQU( 0xFFFFF144 );
+                                                          -( AIC ) Fast Forcing Disable Register
+                                                          AT91C_AIC_CISR EQU( 0xFFFFF114 );
+                                                          -( AIC ) Core Interrupt Status Register
+                                                          AT91C_AIC_IDCR EQU( 0xFFFFF124 );
+                                                          -( AIC ) Interrupt Disable Command Register
+                                                          AT91C_AIC_SPU EQU( 0xFFFFF134 );
+                                                          -( AIC ) Spurious Vector Register
+/* - ========== Register definition for PDC_DBGU peripheral ========== */
+                                                          AT91C_DBGU_TCR EQU( 0xFFFFF30C );
+                                                          -( PDC_DBGU ) Transmit Counter Register
+                                                          AT91C_DBGU_RNPR EQU( 0xFFFFF310 );
+                                                          -( PDC_DBGU ) Receive Next Pointer Register
+                                                          AT91C_DBGU_TNPR EQU( 0xFFFFF318 );
+                                                          -( PDC_DBGU ) Transmit Next Pointer Register
+                                                          AT91C_DBGU_TPR EQU( 0xFFFFF308 );
+                                                          -( PDC_DBGU ) Transmit Pointer Register
+                                                          AT91C_DBGU_RPR EQU( 0xFFFFF300 );
+                                                          -( PDC_DBGU ) Receive Pointer Register
+                                                          AT91C_DBGU_RCR EQU( 0xFFFFF304 );
+                                                          -( PDC_DBGU ) Receive Counter Register
+                                                          AT91C_DBGU_RNCR EQU( 0xFFFFF314 );
+                                                          -( PDC_DBGU ) Receive Next Counter Register
+                                                          AT91C_DBGU_PTCR EQU( 0xFFFFF320 );
+                                                          -( PDC_DBGU ) PDC Transfer Control Register
+                                                          AT91C_DBGU_PTSR EQU( 0xFFFFF324 );
+                                                          -( PDC_DBGU ) PDC Transfer Status Register
+                                                          AT91C_DBGU_TNCR EQU( 0xFFFFF31C );
+                                                          -( PDC_DBGU ) Transmit Next Counter Register
+/* - ========== Register definition for DBGU peripheral ========== */
+                                                          AT91C_DBGU_EXID EQU( 0xFFFFF244 );
+                                                          -( DBGU ) Chip ID Extension Register
+                                                          AT91C_DBGU_BRGR EQU( 0xFFFFF220 );
+                                                          -( DBGU ) Baud Rate Generator Register
+                                                          AT91C_DBGU_IDR EQU( 0xFFFFF20C );
+                                                          -( DBGU ) Interrupt Disable Register
+                                                          AT91C_DBGU_CSR EQU( 0xFFFFF214 );
+                                                          -( DBGU ) Channel Status Register
+                                                          AT91C_DBGU_CIDR EQU( 0xFFFFF240 );
+                                                          -( DBGU ) Chip ID Register
+                                                          AT91C_DBGU_MR EQU( 0xFFFFF204 );
+                                                          -( DBGU ) Mode Register
+                                                          AT91C_DBGU_IMR EQU( 0xFFFFF210 );
+                                                          -( DBGU ) Interrupt Mask Register
+                                                          AT91C_DBGU_CR EQU( 0xFFFFF200 );
+                                                          -( DBGU ) Control Register
+                                                          AT91C_DBGU_FNTR EQU( 0xFFFFF248 );
+                                                          -( DBGU ) Force NTRST Register
+                                                          AT91C_DBGU_THR EQU( 0xFFFFF21C );
+                                                          -( DBGU ) Transmitter Holding Register
+                                                          AT91C_DBGU_RHR EQU( 0xFFFFF218 );
+                                                          -( DBGU ) Receiver Holding Register
+                                                          AT91C_DBGU_IER EQU( 0xFFFFF208 );
+                                                          -( DBGU ) Interrupt Enable Register
+/* - ========== Register definition for PIOA peripheral ========== */
+                                                          AT91C_PIOA_ODR EQU( 0xFFFFF414 );
+                                                          -( PIOA ) Output Disable Registerr
+                                                          AT91C_PIOA_SODR EQU( 0xFFFFF430 );
+                                                          -( PIOA ) Set Output Data Register
+                                                          AT91C_PIOA_ISR EQU( 0xFFFFF44C );
+                                                          -( PIOA ) Interrupt Status Register
+                                                          AT91C_PIOA_ABSR EQU( 0xFFFFF478 );
+                                                          -( PIOA ) AB Select Status Register
+                                                          AT91C_PIOA_IER EQU( 0xFFFFF440 );
+                                                          -( PIOA ) Interrupt Enable Register
+                                                          AT91C_PIOA_PPUDR EQU( 0xFFFFF460 );
+                                                          -( PIOA ) Pull - up Disable Register
+                                                          AT91C_PIOA_IMR EQU( 0xFFFFF448 );
+                                                          -( PIOA ) Interrupt Mask Register
+                                                          AT91C_PIOA_PER EQU( 0xFFFFF400 );
+                                                          -( PIOA ) PIO Enable Register
+                                                          AT91C_PIOA_IFDR EQU( 0xFFFFF424 );
+                                                          -( PIOA ) Input Filter Disable Register
+                                                          AT91C_PIOA_OWDR EQU( 0xFFFFF4A4 );
+                                                          -( PIOA ) Output Write Disable Register
+                                                          AT91C_PIOA_MDSR EQU( 0xFFFFF458 );
+                                                          -( PIOA ) Multi - driver Status Register
+                                                          AT91C_PIOA_IDR EQU( 0xFFFFF444 );
+                                                          -( PIOA ) Interrupt Disable Register
+                                                          AT91C_PIOA_ODSR EQU( 0xFFFFF438 );
+                                                          -( PIOA ) Output Data Status Register
+                                                          AT91C_PIOA_PPUSR EQU( 0xFFFFF468 );
+                                                          -( PIOA ) Pull - up Status Register
+                                                          AT91C_PIOA_OWSR EQU( 0xFFFFF4A8 );
+                                                          -( PIOA ) Output Write Status Register
+                                                          AT91C_PIOA_BSR EQU( 0xFFFFF474 );
+                                                          -( PIOA ) Select B Register
+                                                          AT91C_PIOA_OWER EQU( 0xFFFFF4A0 );
+                                                          -( PIOA ) Output Write Enable Register
+                                                          AT91C_PIOA_IFER EQU( 0xFFFFF420 );
+                                                          -( PIOA ) Input Filter Enable Register
+                                                          AT91C_PIOA_PDSR EQU( 0xFFFFF43C );
+                                                          -( PIOA ) Pin Data Status Register
+                                                          AT91C_PIOA_PPUER EQU( 0xFFFFF464 );
+                                                          -( PIOA ) Pull - up Enable Register
+                                                          AT91C_PIOA_OSR EQU( 0xFFFFF418 );
+                                                          -( PIOA ) Output Status Register
+                                                          AT91C_PIOA_ASR EQU( 0xFFFFF470 );
+                                                          -( PIOA ) Select A Register
+                                                          AT91C_PIOA_MDDR EQU( 0xFFFFF454 );
+                                                          -( PIOA ) Multi - driver Disable Register
+                                                          AT91C_PIOA_CODR EQU( 0xFFFFF434 );
+                                                          -( PIOA ) Clear Output Data Register
+                                                          AT91C_PIOA_MDER EQU( 0xFFFFF450 );
+                                                          -( PIOA ) Multi - driver Enable Register
+                                                          AT91C_PIOA_PDR EQU( 0xFFFFF404 );
+                                                          -( PIOA ) PIO Disable Register
+                                                          AT91C_PIOA_IFSR EQU( 0xFFFFF428 );
+                                                          -( PIOA ) Input Filter Status Register
+                                                          AT91C_PIOA_OER EQU( 0xFFFFF410 );
+                                                          -( PIOA ) Output Enable Register
+                                                          AT91C_PIOA_PSR EQU( 0xFFFFF408 );
+                                                          -( PIOA ) PIO Status Register
+/* - ========== Register definition for PIOB peripheral ========== */
+                                                          AT91C_PIOB_OWDR EQU( 0xFFFFF6A4 );
+                                                          -( PIOB ) Output Write Disable Register
+                                                          AT91C_PIOB_MDER EQU( 0xFFFFF650 );
+                                                          -( PIOB ) Multi - driver Enable Register
+                                                          AT91C_PIOB_PPUSR EQU( 0xFFFFF668 );
+                                                          -( PIOB ) Pull - up Status Register
+                                                          AT91C_PIOB_IMR EQU( 0xFFFFF648 );
+                                                          -( PIOB ) Interrupt Mask Register
+                                                          AT91C_PIOB_ASR EQU( 0xFFFFF670 );
+                                                          -( PIOB ) Select A Register
+                                                          AT91C_PIOB_PPUDR EQU( 0xFFFFF660 );
+                                                          -( PIOB ) Pull - up Disable Register
+                                                          AT91C_PIOB_PSR EQU( 0xFFFFF608 );
+                                                          -( PIOB ) PIO Status Register
+                                                          AT91C_PIOB_IER EQU( 0xFFFFF640 );
+                                                          -( PIOB ) Interrupt Enable Register
+                                                          AT91C_PIOB_CODR EQU( 0xFFFFF634 );
+                                                          -( PIOB ) Clear Output Data Register
+                                                          AT91C_PIOB_OWER EQU( 0xFFFFF6A0 );
+                                                          -( PIOB ) Output Write Enable Register
+                                                          AT91C_PIOB_ABSR EQU( 0xFFFFF678 );
+                                                          -( PIOB ) AB Select Status Register
+                                                          AT91C_PIOB_IFDR EQU( 0xFFFFF624 );
+                                                          -( PIOB ) Input Filter Disable Register
+                                                          AT91C_PIOB_PDSR EQU( 0xFFFFF63C );
+                                                          -( PIOB ) Pin Data Status Register
+                                                          AT91C_PIOB_IDR EQU( 0xFFFFF644 );
+                                                          -( PIOB ) Interrupt Disable Register
+                                                          AT91C_PIOB_OWSR EQU( 0xFFFFF6A8 );
+                                                          -( PIOB ) Output Write Status Register
+                                                          AT91C_PIOB_PDR EQU( 0xFFFFF604 );
+                                                          -( PIOB ) PIO Disable Register
+                                                          AT91C_PIOB_ODR EQU( 0xFFFFF614 );
+                                                          -( PIOB ) Output Disable Registerr
+                                                          AT91C_PIOB_IFSR EQU( 0xFFFFF628 );
+                                                          -( PIOB ) Input Filter Status Register
+                                                          AT91C_PIOB_PPUER EQU( 0xFFFFF664 );
+                                                          -( PIOB ) Pull - up Enable Register
+                                                          AT91C_PIOB_SODR EQU( 0xFFFFF630 );
+                                                          -( PIOB ) Set Output Data Register
+                                                          AT91C_PIOB_ISR EQU( 0xFFFFF64C );
+                                                          -( PIOB ) Interrupt Status Register
+                                                          AT91C_PIOB_ODSR EQU( 0xFFFFF638 );
+                                                          -( PIOB ) Output Data Status Register
+                                                          AT91C_PIOB_OSR EQU( 0xFFFFF618 );
+                                                          -( PIOB ) Output Status Register
+                                                          AT91C_PIOB_MDSR EQU( 0xFFFFF658 );
+                                                          -( PIOB ) Multi - driver Status Register
+                                                          AT91C_PIOB_IFER EQU( 0xFFFFF620 );
+                                                          -( PIOB ) Input Filter Enable Register
+                                                          AT91C_PIOB_BSR EQU( 0xFFFFF674 );
+                                                          -( PIOB ) Select B Register
+                                                          AT91C_PIOB_MDDR EQU( 0xFFFFF654 );
+                                                          -( PIOB ) Multi - driver Disable Register
+                                                          AT91C_PIOB_OER EQU( 0xFFFFF610 );
+                                                          -( PIOB ) Output Enable Register
+                                                          AT91C_PIOB_PER EQU( 0xFFFFF600 );
+                                                          -( PIOB ) PIO Enable Register
+/* - ========== Register definition for CKGR peripheral ========== */
+                                                          AT91C_CKGR_MOR EQU( 0xFFFFFC20 );
+                                                          -( CKGR ) Main Oscillator Register
+                                                          AT91C_CKGR_PLLR EQU( 0xFFFFFC2C );
+                                                          -( CKGR ) PLL Register
+                                                          AT91C_CKGR_MCFR EQU( 0xFFFFFC24 );
+                                                          -( CKGR ) Main Clock Frequency Register
+/* - ========== Register definition for PMC peripheral ========== */
+                                                          AT91C_PMC_IDR EQU( 0xFFFFFC64 );
+                                                          -( PMC ) Interrupt Disable Register
+                                                          AT91C_PMC_MOR EQU( 0xFFFFFC20 );
+                                                          -( PMC ) Main Oscillator Register
+                                                          AT91C_PMC_PLLR EQU( 0xFFFFFC2C );
+                                                          -( PMC ) PLL Register
+                                                          AT91C_PMC_PCER EQU( 0xFFFFFC10 );
+                                                          -( PMC ) Peripheral Clock Enable Register
+                                                          AT91C_PMC_PCKR EQU( 0xFFFFFC40 );
+                                                          -( PMC ) Programmable Clock Register
+                                                          AT91C_PMC_MCKR EQU( 0xFFFFFC30 );
+                                                          -( PMC ) Master Clock Register
+                                                          AT91C_PMC_SCDR EQU( 0xFFFFFC04 );
+                                                          -( PMC ) System Clock Disable Register
+                                                          AT91C_PMC_PCDR EQU( 0xFFFFFC14 );
+                                                          -( PMC ) Peripheral Clock Disable Register
+                                                          AT91C_PMC_SCSR EQU( 0xFFFFFC08 );
+                                                          -( PMC ) System Clock Status Register
+                                                          AT91C_PMC_PCSR EQU( 0xFFFFFC18 );
+                                                          -( PMC ) Peripheral Clock Status Register
+                                                          AT91C_PMC_MCFR EQU( 0xFFFFFC24 );
+                                                          -( PMC ) Main Clock Frequency Register
+                                                          AT91C_PMC_SCER EQU( 0xFFFFFC00 );
+                                                          -( PMC ) System Clock Enable Register
+                                                          AT91C_PMC_IMR EQU( 0xFFFFFC6C );
+                                                          -( PMC ) Interrupt Mask Register
+                                                          AT91C_PMC_IER EQU( 0xFFFFFC60 );
+                                                          -( PMC ) Interrupt Enable Register
+                                                          AT91C_PMC_SR EQU( 0xFFFFFC68 );
+                                                          -( PMC ) Status Register
+/* - ========== Register definition for RSTC peripheral ========== */
+                                                          AT91C_RSTC_RCR EQU( 0xFFFFFD00 );
+                                                          -( RSTC ) Reset Control Register
+                                                          AT91C_RSTC_RMR EQU( 0xFFFFFD08 );
+                                                          -( RSTC ) Reset Mode Register
+                                                          AT91C_RSTC_RSR EQU( 0xFFFFFD04 );
+                                                          -( RSTC ) Reset Status Register
+/* - ========== Register definition for RTTC peripheral ========== */
+                                                          AT91C_RTTC_RTSR EQU( 0xFFFFFD2C );
+                                                          -( RTTC ) Real - time Status Register
+                                                          AT91C_RTTC_RTMR EQU( 0xFFFFFD20 );
+                                                          -( RTTC ) Real - time Mode Register
+                                                          AT91C_RTTC_RTVR EQU( 0xFFFFFD28 );
+                                                          -( RTTC ) Real - time Value Register
+                                                          AT91C_RTTC_RTAR EQU( 0xFFFFFD24 );
+                                                          -( RTTC ) Real - time Alarm Register
+/* - ========== Register definition for PITC peripheral ========== */
+                                                          AT91C_PITC_PIVR EQU( 0xFFFFFD38 );
+                                                          -( PITC ) Period Interval Value Register
+                                                          AT91C_PITC_PISR EQU( 0xFFFFFD34 );
+                                                          -( PITC ) Period Interval Status Register
+                                                          AT91C_PITC_PIIR EQU( 0xFFFFFD3C );
+                                                          -( PITC ) Period Interval Image Register
+                                                          AT91C_PITC_PIMR EQU( 0xFFFFFD30 );
+                                                          -( PITC ) Period Interval Mode Register
+/* - ========== Register definition for WDTC peripheral ========== */
+                                                          AT91C_WDTC_WDCR EQU( 0xFFFFFD40 );
+                                                          -( WDTC ) Watchdog Control Register
+                                                          AT91C_WDTC_WDSR EQU( 0xFFFFFD48 );
+                                                          -( WDTC ) Watchdog Status Register
+                                                          AT91C_WDTC_WDMR EQU( 0xFFFFFD44 );
+                                                          -( WDTC ) Watchdog Mode Register
+/* - ========== Register definition for VREG peripheral ========== */
+                                                          AT91C_VREG_MR EQU( 0xFFFFFD60 );
+                                                          -( VREG ) Voltage Regulator Mode Register
+/* - ========== Register definition for MC peripheral ========== */
+                                                          AT91C_MC_ASR EQU( 0xFFFFFF04 );
+                                                          -( MC ) MC Abort Status Register
+                                                          AT91C_MC_RCR EQU( 0xFFFFFF00 );
+                                                          -( MC ) MC Remap Control Register
+                                                          AT91C_MC_FCR EQU( 0xFFFFFF64 );
+                                                          -( MC ) MC Flash Command Register
+                                                          AT91C_MC_AASR EQU( 0xFFFFFF08 );
+                                                          -( MC ) MC Abort Address Status Register
+                                                          AT91C_MC_FSR EQU( 0xFFFFFF68 );
+                                                          -( MC ) MC Flash Status Register
+                                                          AT91C_MC_FMR EQU( 0xFFFFFF60 );
+                                                          -( MC ) MC Flash Mode Register
+/* - ========== Register definition for PDC_SPI1 peripheral ========== */
+                                                          AT91C_SPI1_PTCR EQU( 0xFFFE4120 );
+                                                          -( PDC_SPI1 ) PDC Transfer Control Register
+                                                          AT91C_SPI1_RPR EQU( 0xFFFE4100 );
+                                                          -( PDC_SPI1 ) Receive Pointer Register
+                                                          AT91C_SPI1_TNCR EQU( 0xFFFE411C );
+                                                          -( PDC_SPI1 ) Transmit Next Counter Register
+                                                          AT91C_SPI1_TPR EQU( 0xFFFE4108 );
+                                                          -( PDC_SPI1 ) Transmit Pointer Register
+                                                          AT91C_SPI1_TNPR EQU( 0xFFFE4118 );
+                                                          -( PDC_SPI1 ) Transmit Next Pointer Register
+                                                          AT91C_SPI1_TCR EQU( 0xFFFE410C );
+                                                          -( PDC_SPI1 ) Transmit Counter Register
+                                                          AT91C_SPI1_RCR EQU( 0xFFFE4104 );
+                                                          -( PDC_SPI1 ) Receive Counter Register
+                                                          AT91C_SPI1_RNPR EQU( 0xFFFE4110 );
+                                                          -( PDC_SPI1 ) Receive Next Pointer Register
+                                                          AT91C_SPI1_RNCR EQU( 0xFFFE4114 );
+                                                          -( PDC_SPI1 ) Receive Next Counter Register
+                                                          AT91C_SPI1_PTSR EQU( 0xFFFE4124 );
+                                                          -( PDC_SPI1 ) PDC Transfer Status Register
+/* - ========== Register definition for SPI1 peripheral ========== */
+                                                          AT91C_SPI1_IMR EQU( 0xFFFE401C );
+                                                          -( SPI1 ) Interrupt Mask Register
+                                                          AT91C_SPI1_IER EQU( 0xFFFE4014 );
+                                                          -( SPI1 ) Interrupt Enable Register
+                                                          AT91C_SPI1_MR EQU( 0xFFFE4004 );
+                                                          -( SPI1 ) Mode Register
+                                                          AT91C_SPI1_RDR EQU( 0xFFFE4008 );
+                                                          -( SPI1 ) Receive Data Register
+                                                          AT91C_SPI1_IDR EQU( 0xFFFE4018 );
+                                                          -( SPI1 ) Interrupt Disable Register
+                                                          AT91C_SPI1_SR EQU( 0xFFFE4010 );
+                                                          -( SPI1 ) Status Register
+                                                          AT91C_SPI1_TDR EQU( 0xFFFE400C );
+                                                          -( SPI1 ) Transmit Data Register
+                                                          AT91C_SPI1_CR EQU( 0xFFFE4000 );
+                                                          -( SPI1 ) Control Register
+                                                          AT91C_SPI1_CSR EQU( 0xFFFE4030 );
+                                                          -( SPI1 ) Chip Select Register
+/* - ========== Register definition for PDC_SPI0 peripheral ========== */
+                                                          AT91C_SPI0_PTCR EQU( 0xFFFE0120 );
+                                                          -( PDC_SPI0 ) PDC Transfer Control Register
+                                                          AT91C_SPI0_TPR EQU( 0xFFFE0108 );
+                                                          -( PDC_SPI0 ) Transmit Pointer Register
+                                                          AT91C_SPI0_TCR EQU( 0xFFFE010C );
+                                                          -( PDC_SPI0 ) Transmit Counter Register
+                                                          AT91C_SPI0_RCR EQU( 0xFFFE0104 );
+                                                          -( PDC_SPI0 ) Receive Counter Register
+                                                          AT91C_SPI0_PTSR EQU( 0xFFFE0124 );
+                                                          -( PDC_SPI0 ) PDC Transfer Status Register
+                                                          AT91C_SPI0_RNPR EQU( 0xFFFE0110 );
+                                                          -( PDC_SPI0 ) Receive Next Pointer Register
+                                                          AT91C_SPI0_RPR EQU( 0xFFFE0100 );
+                                                          -( PDC_SPI0 ) Receive Pointer Register
+                                                          AT91C_SPI0_TNCR EQU( 0xFFFE011C );
+                                                          -( PDC_SPI0 ) Transmit Next Counter Register
+                                                          AT91C_SPI0_RNCR EQU( 0xFFFE0114 );
+                                                          -( PDC_SPI0 ) Receive Next Counter Register
+                                                          AT91C_SPI0_TNPR EQU( 0xFFFE0118 );
+                                                          -( PDC_SPI0 ) Transmit Next Pointer Register
+/* - ========== Register definition for SPI0 peripheral ========== */
+                                                          AT91C_SPI0_IER EQU( 0xFFFE0014 );
+                                                          -( SPI0 ) Interrupt Enable Register
+                                                          AT91C_SPI0_SR EQU( 0xFFFE0010 );
+                                                          -( SPI0 ) Status Register
+                                                          AT91C_SPI0_IDR EQU( 0xFFFE0018 );
+                                                          -( SPI0 ) Interrupt Disable Register
+                                                          AT91C_SPI0_CR EQU( 0xFFFE0000 );
+                                                          -( SPI0 ) Control Register
+                                                          AT91C_SPI0_MR EQU( 0xFFFE0004 );
+                                                          -( SPI0 ) Mode Register
+                                                          AT91C_SPI0_IMR EQU( 0xFFFE001C );
+                                                          -( SPI0 ) Interrupt Mask Register
+                                                          AT91C_SPI0_TDR EQU( 0xFFFE000C );
+                                                          -( SPI0 ) Transmit Data Register
+                                                          AT91C_SPI0_RDR EQU( 0xFFFE0008 );
+                                                          -( SPI0 ) Receive Data Register
+                                                          AT91C_SPI0_CSR EQU( 0xFFFE0030 );
+                                                          -( SPI0 ) Chip Select Register
+/* - ========== Register definition for PDC_US1 peripheral ========== */
+                                                          AT91C_US1_RNCR EQU( 0xFFFC4114 );
+                                                          -( PDC_US1 ) Receive Next Counter Register
+                                                          AT91C_US1_PTCR EQU( 0xFFFC4120 );
+                                                          -( PDC_US1 ) PDC Transfer Control Register
+                                                          AT91C_US1_TCR EQU( 0xFFFC410C );
+                                                          -( PDC_US1 ) Transmit Counter Register
+                                                          AT91C_US1_PTSR EQU( 0xFFFC4124 );
+                                                          -( PDC_US1 ) PDC Transfer Status Register
+                                                          AT91C_US1_TNPR EQU( 0xFFFC4118 );
+                                                          -( PDC_US1 ) Transmit Next Pointer Register
+                                                          AT91C_US1_RCR EQU( 0xFFFC4104 );
+                                                          -( PDC_US1 ) Receive Counter Register
+                                                          AT91C_US1_RNPR EQU( 0xFFFC4110 );
+                                                          -( PDC_US1 ) Receive Next Pointer Register
+                                                          AT91C_US1_RPR EQU( 0xFFFC4100 );
+                                                          -( PDC_US1 ) Receive Pointer Register
+                                                          AT91C_US1_TNCR EQU( 0xFFFC411C );
+                                                          -( PDC_US1 ) Transmit Next Counter Register
+                                                          AT91C_US1_TPR EQU( 0xFFFC4108 );
+                                                          -( PDC_US1 ) Transmit Pointer Register
+/* - ========== Register definition for US1 peripheral ========== */
+                                                          AT91C_US1_IF EQU( 0xFFFC404C );
+                                                          -( US1 ) IRDA_FILTER Register
+                                                          AT91C_US1_NER EQU( 0xFFFC4044 );
+                                                          -( US1 ) Nb Errors Register
+                                                          AT91C_US1_RTOR EQU( 0xFFFC4024 );
+                                                          -( US1 ) Receiver Time - out Register
+                                                          AT91C_US1_CSR EQU( 0xFFFC4014 );
+                                                          -( US1 ) Channel Status Register
+                                                          AT91C_US1_IDR EQU( 0xFFFC400C );
+                                                          -( US1 ) Interrupt Disable Register
+                                                          AT91C_US1_IER EQU( 0xFFFC4008 );
+                                                          -( US1 ) Interrupt Enable Register
+                                                          AT91C_US1_THR EQU( 0xFFFC401C );
+                                                          -( US1 ) Transmitter Holding Register
+                                                          AT91C_US1_TTGR EQU( 0xFFFC4028 );
+                                                          -( US1 ) Transmitter Time - guard Register
+                                                          AT91C_US1_RHR EQU( 0xFFFC4018 );
+                                                          -( US1 ) Receiver Holding Register
+                                                          AT91C_US1_BRGR EQU( 0xFFFC4020 );
+                                                          -( US1 ) Baud Rate Generator Register
+                                                          AT91C_US1_IMR EQU( 0xFFFC4010 );
+                                                          -( US1 ) Interrupt Mask Register
+                                                          AT91C_US1_FIDI EQU( 0xFFFC4040 );
+                                                          -( US1 ) FI_DI_Ratio Register
+                                                          AT91C_US1_CR EQU( 0xFFFC4000 );
+                                                          -( US1 ) Control Register
+                                                          AT91C_US1_MR EQU( 0xFFFC4004 );
+                                                          -( US1 ) Mode Register
+/* - ========== Register definition for PDC_US0 peripheral ========== */
+                                                          AT91C_US0_TNPR EQU( 0xFFFC0118 );
+                                                          -( PDC_US0 ) Transmit Next Pointer Register
+                                                          AT91C_US0_RNPR EQU( 0xFFFC0110 );
+                                                          -( PDC_US0 ) Receive Next Pointer Register
+                                                          AT91C_US0_TCR EQU( 0xFFFC010C );
+                                                          -( PDC_US0 ) Transmit Counter Register
+                                                          AT91C_US0_PTCR EQU( 0xFFFC0120 );
+                                                          -( PDC_US0 ) PDC Transfer Control Register
+                                                          AT91C_US0_PTSR EQU( 0xFFFC0124 );
+                                                          -( PDC_US0 ) PDC Transfer Status Register
+                                                          AT91C_US0_TNCR EQU( 0xFFFC011C );
+                                                          -( PDC_US0 ) Transmit Next Counter Register
+                                                          AT91C_US0_TPR EQU( 0xFFFC0108 );
+                                                          -( PDC_US0 ) Transmit Pointer Register
+                                                          AT91C_US0_RCR EQU( 0xFFFC0104 );
+                                                          -( PDC_US0 ) Receive Counter Register
+                                                          AT91C_US0_RPR EQU( 0xFFFC0100 );
+                                                          -( PDC_US0 ) Receive Pointer Register
+                                                          AT91C_US0_RNCR EQU( 0xFFFC0114 );
+                                                          -( PDC_US0 ) Receive Next Counter Register
+/* - ========== Register definition for US0 peripheral ========== */
+                                                          AT91C_US0_BRGR EQU( 0xFFFC0020 );
+                                                          -( US0 ) Baud Rate Generator Register
+                                                          AT91C_US0_NER EQU( 0xFFFC0044 );
+                                                          -( US0 ) Nb Errors Register
+                                                          AT91C_US0_CR EQU( 0xFFFC0000 );
+                                                          -( US0 ) Control Register
+                                                          AT91C_US0_IMR EQU( 0xFFFC0010 );
+                                                          -( US0 ) Interrupt Mask Register
+                                                          AT91C_US0_FIDI EQU( 0xFFFC0040 );
+                                                          -( US0 ) FI_DI_Ratio Register
+                                                          AT91C_US0_TTGR EQU( 0xFFFC0028 );
+                                                          -( US0 ) Transmitter Time - guard Register
+                                                          AT91C_US0_MR EQU( 0xFFFC0004 );
+                                                          -( US0 ) Mode Register
+                                                          AT91C_US0_RTOR EQU( 0xFFFC0024 );
+                                                          -( US0 ) Receiver Time - out Register
+                                                          AT91C_US0_CSR EQU( 0xFFFC0014 );
+                                                          -( US0 ) Channel Status Register
+                                                          AT91C_US0_RHR EQU( 0xFFFC0018 );
+                                                          -( US0 ) Receiver Holding Register
+                                                          AT91C_US0_IDR EQU( 0xFFFC000C );
+                                                          -( US0 ) Interrupt Disable Register
+                                                          AT91C_US0_THR EQU( 0xFFFC001C );
+                                                          -( US0 ) Transmitter Holding Register
+                                                          AT91C_US0_IF EQU( 0xFFFC004C );
+                                                          -( US0 ) IRDA_FILTER Register
+                                                          AT91C_US0_IER EQU( 0xFFFC0008 );
+                                                          -( US0 ) Interrupt Enable Register
+/* - ========== Register definition for PDC_SSC peripheral ========== */
+                                                          AT91C_SSC_TNCR EQU( 0xFFFD411C );
+                                                          -( PDC_SSC ) Transmit Next Counter Register
+                                                          AT91C_SSC_RPR EQU( 0xFFFD4100 );
+                                                          -( PDC_SSC ) Receive Pointer Register
+                                                          AT91C_SSC_RNCR EQU( 0xFFFD4114 );
+                                                          -( PDC_SSC ) Receive Next Counter Register
+                                                          AT91C_SSC_TPR EQU( 0xFFFD4108 );
+                                                          -( PDC_SSC ) Transmit Pointer Register
+                                                          AT91C_SSC_PTCR EQU( 0xFFFD4120 );
+                                                          -( PDC_SSC ) PDC Transfer Control Register
+                                                          AT91C_SSC_TCR EQU( 0xFFFD410C );
+                                                          -( PDC_SSC ) Transmit Counter Register
+                                                          AT91C_SSC_RCR EQU( 0xFFFD4104 );
+                                                          -( PDC_SSC ) Receive Counter Register
+                                                          AT91C_SSC_RNPR EQU( 0xFFFD4110 );
+                                                          -( PDC_SSC ) Receive Next Pointer Register
+                                                          AT91C_SSC_TNPR EQU( 0xFFFD4118 );
+                                                          -( PDC_SSC ) Transmit Next Pointer Register
+                                                          AT91C_SSC_PTSR EQU( 0xFFFD4124 );
+                                                          -( PDC_SSC ) PDC Transfer Status Register
+/* - ========== Register definition for SSC peripheral ========== */
+                                                          AT91C_SSC_RHR EQU( 0xFFFD4020 );
+                                                          -( SSC ) Receive Holding Register
+                                                          AT91C_SSC_RSHR EQU( 0xFFFD4030 );
+                                                          -( SSC ) Receive Sync Holding Register
+                                                          AT91C_SSC_TFMR EQU( 0xFFFD401C );
+                                                          -( SSC ) Transmit Frame Mode Register
+                                                          AT91C_SSC_IDR EQU( 0xFFFD4048 );
+                                                          -( SSC ) Interrupt Disable Register
+                                                          AT91C_SSC_THR EQU( 0xFFFD4024 );
+                                                          -( SSC ) Transmit Holding Register
+                                                          AT91C_SSC_RCMR EQU( 0xFFFD4010 );
+                                                          -( SSC ) Receive Clock ModeRegister
+                                                          AT91C_SSC_IER EQU( 0xFFFD4044 );
+                                                          -( SSC ) Interrupt Enable Register
+                                                          AT91C_SSC_TSHR EQU( 0xFFFD4034 );
+                                                          -( SSC ) Transmit Sync Holding Register
+                                                          AT91C_SSC_SR EQU( 0xFFFD4040 );
+                                                          -( SSC ) Status Register
+                                                          AT91C_SSC_CMR EQU( 0xFFFD4004 );
+                                                          -( SSC ) Clock Mode Register
+                                                          AT91C_SSC_TCMR EQU( 0xFFFD4018 );
+                                                          -( SSC ) Transmit Clock Mode Register
+                                                          AT91C_SSC_CR EQU( 0xFFFD4000 );
+                                                          -( SSC ) Control Register
+                                                          AT91C_SSC_IMR EQU( 0xFFFD404C );
+                                                          -( SSC ) Interrupt Mask Register
+                                                          AT91C_SSC_RFMR EQU( 0xFFFD4014 );
+                                                          -( SSC ) Receive Frame Mode Register
+/* - ========== Register definition for TWI peripheral ========== */
+                                                          AT91C_TWI_IER EQU( 0xFFFB8024 );
+                                                          -( TWI ) Interrupt Enable Register
+                                                          AT91C_TWI_CR EQU( 0xFFFB8000 );
+                                                          -( TWI ) Control Register
+                                                          AT91C_TWI_SR EQU( 0xFFFB8020 );
+                                                          -( TWI ) Status Register
+                                                          AT91C_TWI_IMR EQU( 0xFFFB802C );
+                                                          -( TWI ) Interrupt Mask Register
+                                                          AT91C_TWI_THR EQU( 0xFFFB8034 );
+                                                          -( TWI ) Transmit Holding Register
+                                                          AT91C_TWI_IDR EQU( 0xFFFB8028 );
+                                                          -( TWI ) Interrupt Disable Register
+                                                          AT91C_TWI_IADR EQU( 0xFFFB800C );
+                                                          -( TWI ) Internal Address Register
+                                                          AT91C_TWI_MMR EQU( 0xFFFB8004 );
+                                                          -( TWI ) Master Mode Register
+                                                          AT91C_TWI_CWGR EQU( 0xFFFB8010 );
+                                                          -( TWI ) Clock Waveform Generator Register
+                                                          AT91C_TWI_RHR EQU( 0xFFFB8030 );
+                                                          -( TWI ) Receive Holding Register
+/* - ========== Register definition for PWMC_CH3 peripheral ========== */
+                                                          AT91C_PWMC_CH3_CUPDR EQU( 0xFFFCC270 );
+                                                          -( PWMC_CH3 ) Channel Update Register
+                                                          AT91C_PWMC_CH3_Reserved EQU( 0xFFFCC274 );
+                                                          -( PWMC_CH3 ) Reserved
+                                                          AT91C_PWMC_CH3_CPRDR EQU( 0xFFFCC268 );
+                                                          -( PWMC_CH3 ) Channel Period Register
+                                                          AT91C_PWMC_CH3_CDTYR EQU( 0xFFFCC264 );
+                                                          -( PWMC_CH3 ) Channel Duty Cycle Register
+                                                          AT91C_PWMC_CH3_CCNTR EQU( 0xFFFCC26C );
+                                                          -( PWMC_CH3 ) Channel Counter Register
+                                                          AT91C_PWMC_CH3_CMR EQU( 0xFFFCC260 );
+                                                          -( PWMC_CH3 ) Channel Mode Register
+/* - ========== Register definition for PWMC_CH2 peripheral ========== */
+                                                          AT91C_PWMC_CH2_Reserved EQU( 0xFFFCC254 );
+                                                          -( PWMC_CH2 ) Reserved
+                                                          AT91C_PWMC_CH2_CMR EQU( 0xFFFCC240 );
+                                                          -( PWMC_CH2 ) Channel Mode Register
+                                                          AT91C_PWMC_CH2_CCNTR EQU( 0xFFFCC24C );
+                                                          -( PWMC_CH2 ) Channel Counter Register
+                                                          AT91C_PWMC_CH2_CPRDR EQU( 0xFFFCC248 );
+                                                          -( PWMC_CH2 ) Channel Period Register
+                                                          AT91C_PWMC_CH2_CUPDR EQU( 0xFFFCC250 );
+                                                          -( PWMC_CH2 ) Channel Update Register
+                                                          AT91C_PWMC_CH2_CDTYR EQU( 0xFFFCC244 );
+                                                          -( PWMC_CH2 ) Channel Duty Cycle Register
+/* - ========== Register definition for PWMC_CH1 peripheral ========== */
+                                                          AT91C_PWMC_CH1_Reserved EQU( 0xFFFCC234 );
+                                                          -( PWMC_CH1 ) Reserved
+                                                          AT91C_PWMC_CH1_CUPDR EQU( 0xFFFCC230 );
+                                                          -( PWMC_CH1 ) Channel Update Register
+                                                          AT91C_PWMC_CH1_CPRDR EQU( 0xFFFCC228 );
+                                                          -( PWMC_CH1 ) Channel Period Register
+                                                          AT91C_PWMC_CH1_CCNTR EQU( 0xFFFCC22C );
+                                                          -( PWMC_CH1 ) Channel Counter Register
+                                                          AT91C_PWMC_CH1_CDTYR EQU( 0xFFFCC224 );
+                                                          -( PWMC_CH1 ) Channel Duty Cycle Register
+                                                          AT91C_PWMC_CH1_CMR EQU( 0xFFFCC220 );
+                                                          -( PWMC_CH1 ) Channel Mode Register
+/* - ========== Register definition for PWMC_CH0 peripheral ========== */
+                                                          AT91C_PWMC_CH0_Reserved EQU( 0xFFFCC214 );
+                                                          -( PWMC_CH0 ) Reserved
+                                                          AT91C_PWMC_CH0_CPRDR EQU( 0xFFFCC208 );
+                                                          -( PWMC_CH0 ) Channel Period Register
+                                                          AT91C_PWMC_CH0_CDTYR EQU( 0xFFFCC204 );
+                                                          -( PWMC_CH0 ) Channel Duty Cycle Register
+                                                          AT91C_PWMC_CH0_CMR EQU( 0xFFFCC200 );
+                                                          -( PWMC_CH0 ) Channel Mode Register
+                                                          AT91C_PWMC_CH0_CUPDR EQU( 0xFFFCC210 );
+                                                          -( PWMC_CH0 ) Channel Update Register
+                                                          AT91C_PWMC_CH0_CCNTR EQU( 0xFFFCC20C );
+                                                          -( PWMC_CH0 ) Channel Counter Register
+/* - ========== Register definition for PWMC peripheral ========== */
+                                                          AT91C_PWMC_IDR EQU( 0xFFFCC014 );
+                                                          -( PWMC ) PWMC Interrupt Disable Register
+                                                          AT91C_PWMC_DIS EQU( 0xFFFCC008 );
+                                                          -( PWMC ) PWMC Disable Register
+                                                          AT91C_PWMC_IER EQU( 0xFFFCC010 );
+                                                          -( PWMC ) PWMC Interrupt Enable Register
+                                                          AT91C_PWMC_VR EQU( 0xFFFCC0FC );
+                                                          -( PWMC ) PWMC Version Register
+                                                          AT91C_PWMC_ISR EQU( 0xFFFCC01C );
+                                                          -( PWMC ) PWMC Interrupt Status Register
+                                                          AT91C_PWMC_SR EQU( 0xFFFCC00C );
+                                                          -( PWMC ) PWMC Status Register
+                                                          AT91C_PWMC_IMR EQU( 0xFFFCC018 );
+                                                          -( PWMC ) PWMC Interrupt Mask Register
+                                                          AT91C_PWMC_MR EQU( 0xFFFCC000 );
+                                                          -( PWMC ) PWMC Mode Register
+                                                          AT91C_PWMC_ENA EQU( 0xFFFCC004 );
+                                                          -( PWMC ) PWMC Enable Register
+/* - ========== Register definition for UDP peripheral ========== */
+                                                          AT91C_UDP_IMR EQU( 0xFFFB0018 );
+                                                          -( UDP ) Interrupt Mask Register
+                                                          AT91C_UDP_FADDR EQU( 0xFFFB0008 );
+                                                          -( UDP ) Function Address Register
+                                                          AT91C_UDP_NUM EQU( 0xFFFB0000 );
+                                                          -( UDP ) Frame Number Register
+                                                          AT91C_UDP_FDR EQU( 0xFFFB0050 );
+                                                          -( UDP ) Endpoint FIFO Data Register
+                                                          AT91C_UDP_ISR EQU( 0xFFFB001C );
+                                                          -( UDP ) Interrupt Status Register
+                                                          AT91C_UDP_CSR EQU( 0xFFFB0030 );
+                                                          -( UDP ) Endpoint Control and Status Register
+                                                          AT91C_UDP_IDR EQU( 0xFFFB0014 );
+                                                          -( UDP ) Interrupt Disable Register
+                                                          AT91C_UDP_ICR EQU( 0xFFFB0020 );
+                                                          -( UDP ) Interrupt Clear Register
+                                                          AT91C_UDP_RSTEP EQU( 0xFFFB0028 );
+                                                          -( UDP ) Reset Endpoint Register
+                                                          AT91C_UDP_TXVC EQU( 0xFFFB0074 );
+                                                          -( UDP ) Transceiver Control Register
+                                                          AT91C_UDP_GLBSTATE EQU( 0xFFFB0004 );
+                                                          -( UDP ) Global State Register
+                                                          AT91C_UDP_IER EQU( 0xFFFB0010 );
+                                                          -( UDP ) Interrupt Enable Register
+/* - ========== Register definition for TC0 peripheral ========== */
+                                                          AT91C_TC0_SR EQU( 0xFFFA0020 );
+                                                          -( TC0 ) Status Register
+                                                          AT91C_TC0_RC EQU( 0xFFFA001C );
+                                                          -( TC0 ) Register C
+                                                          AT91C_TC0_RB EQU( 0xFFFA0018 );
+                                                          -( TC0 ) Register B
+                                                          AT91C_TC0_CCR EQU( 0xFFFA0000 );
+                                                          -( TC0 ) Channel Control Register
+                                                          AT91C_TC0_CMR EQU( 0xFFFA0004 );
+                                                          -( TC0 ) Channel Mode Register( Capture Mode / Waveform Mode )
+                                                          AT91C_TC0_IER EQU( 0xFFFA0024 );
+                                                          -( TC0 ) Interrupt Enable Register
+                                                          AT91C_TC0_RA EQU( 0xFFFA0014 );
+                                                          -( TC0 ) Register A
+                                                          AT91C_TC0_IDR EQU( 0xFFFA0028 );
+                                                          -( TC0 ) Interrupt Disable Register
+                                                          AT91C_TC0_CV EQU( 0xFFFA0010 );
+                                                          -( TC0 ) Counter Value
+                                                          AT91C_TC0_IMR EQU( 0xFFFA002C );
+                                                          -( TC0 ) Interrupt Mask Register
+/* - ========== Register definition for TC1 peripheral ========== */
+                                                          AT91C_TC1_RB EQU( 0xFFFA0058 );
+                                                          -( TC1 ) Register B
+                                                          AT91C_TC1_CCR EQU( 0xFFFA0040 );
+                                                          -( TC1 ) Channel Control Register
+                                                          AT91C_TC1_IER EQU( 0xFFFA0064 );
+                                                          -( TC1 ) Interrupt Enable Register
+                                                          AT91C_TC1_IDR EQU( 0xFFFA0068 );
+                                                          -( TC1 ) Interrupt Disable Register
+                                                          AT91C_TC1_SR EQU( 0xFFFA0060 );
+                                                          -( TC1 ) Status Register
+                                                          AT91C_TC1_CMR EQU( 0xFFFA0044 );
+                                                          -( TC1 ) Channel Mode Register( Capture Mode / Waveform Mode )
+                                                          AT91C_TC1_RA EQU( 0xFFFA0054 );
+                                                          -( TC1 ) Register A
+                                                          AT91C_TC1_RC EQU( 0xFFFA005C );
+                                                          -( TC1 ) Register C
+                                                          AT91C_TC1_IMR EQU( 0xFFFA006C );
+                                                          -( TC1 ) Interrupt Mask Register
+                                                          AT91C_TC1_CV EQU( 0xFFFA0050 );
+                                                          -( TC1 ) Counter Value
+/* - ========== Register definition for TC2 peripheral ========== */
+                                                          AT91C_TC2_CMR EQU( 0xFFFA0084 );
+                                                          -( TC2 ) Channel Mode Register( Capture Mode / Waveform Mode )
+                                                          AT91C_TC2_CCR EQU( 0xFFFA0080 );
+                                                          -( TC2 ) Channel Control Register
+                                                          AT91C_TC2_CV EQU( 0xFFFA0090 );
+                                                          -( TC2 ) Counter Value
+                                                          AT91C_TC2_RA EQU( 0xFFFA0094 );
+                                                          -( TC2 ) Register A
+                                                          AT91C_TC2_RB EQU( 0xFFFA0098 );
+                                                          -( TC2 ) Register B
+                                                          AT91C_TC2_IDR EQU( 0xFFFA00A8 );
+                                                          -( TC2 ) Interrupt Disable Register
+                                                          AT91C_TC2_IMR EQU( 0xFFFA00AC );
+                                                          -( TC2 ) Interrupt Mask Register
+                                                          AT91C_TC2_RC EQU( 0xFFFA009C );
+                                                          -( TC2 ) Register C
+                                                          AT91C_TC2_IER EQU( 0xFFFA00A4 );
+                                                          -( TC2 ) Interrupt Enable Register
+                                                          AT91C_TC2_SR EQU( 0xFFFA00A0 );
+                                                          -( TC2 ) Status Register
+/* - ========== Register definition for TCB peripheral ========== */
+                                                          AT91C_TCB_BMR EQU( 0xFFFA00C4 );
+                                                          -( TCB ) TC Block Mode Register
+                                                          AT91C_TCB_BCR EQU( 0xFFFA00C0 );
+                                                          -( TCB ) TC Block Control Register
+/* - ========== Register definition for CAN_MB0 peripheral ========== */
+                                                          AT91C_CAN_MB0_MDL EQU( 0xFFFD0214 );
+                                                          -( CAN_MB0 ) MailBox Data Low Register
+                                                          AT91C_CAN_MB0_MAM EQU( 0xFFFD0204 );
+                                                          -( CAN_MB0 ) MailBox Acceptance Mask Register
+                                                          AT91C_CAN_MB0_MCR EQU( 0xFFFD021C );
+                                                          -( CAN_MB0 ) MailBox Control Register
+                                                          AT91C_CAN_MB0_MID EQU( 0xFFFD0208 );
+                                                          -( CAN_MB0 ) MailBox ID Register
+                                                          AT91C_CAN_MB0_MSR EQU( 0xFFFD0210 );
+                                                          -( CAN_MB0 ) MailBox Status Register
+                                                          AT91C_CAN_MB0_MFID EQU( 0xFFFD020C );
+                                                          -( CAN_MB0 ) MailBox Family ID Register
+                                                          AT91C_CAN_MB0_MDH EQU( 0xFFFD0218 );
+                                                          -( CAN_MB0 ) MailBox Data High Register
+                                                          AT91C_CAN_MB0_MMR EQU( 0xFFFD0200 );
+                                                          -( CAN_MB0 ) MailBox Mode Register
+/* - ========== Register definition for CAN_MB1 peripheral ========== */
+                                                          AT91C_CAN_MB1_MDL EQU( 0xFFFD0234 );
+                                                          -( CAN_MB1 ) MailBox Data Low Register
+                                                          AT91C_CAN_MB1_MID EQU( 0xFFFD0228 );
+                                                          -( CAN_MB1 ) MailBox ID Register
+                                                          AT91C_CAN_MB1_MMR EQU( 0xFFFD0220 );
+                                                          -( CAN_MB1 ) MailBox Mode Register
+                                                          AT91C_CAN_MB1_MSR EQU( 0xFFFD0230 );
+                                                          -( CAN_MB1 ) MailBox Status Register
+                                                          AT91C_CAN_MB1_MAM EQU( 0xFFFD0224 );
+                                                          -( CAN_MB1 ) MailBox Acceptance Mask Register
+                                                          AT91C_CAN_MB1_MDH EQU( 0xFFFD0238 );
+                                                          -( CAN_MB1 ) MailBox Data High Register
+                                                          AT91C_CAN_MB1_MCR EQU( 0xFFFD023C );
+                                                          -( CAN_MB1 ) MailBox Control Register
+                                                          AT91C_CAN_MB1_MFID EQU( 0xFFFD022C );
+                                                          -( CAN_MB1 ) MailBox Family ID Register
+/* - ========== Register definition for CAN_MB2 peripheral ========== */
+                                                          AT91C_CAN_MB2_MCR EQU( 0xFFFD025C );
+                                                          -( CAN_MB2 ) MailBox Control Register
+                                                          AT91C_CAN_MB2_MDH EQU( 0xFFFD0258 );
+                                                          -( CAN_MB2 ) MailBox Data High Register
+                                                          AT91C_CAN_MB2_MID EQU( 0xFFFD0248 );
+                                                          -( CAN_MB2 ) MailBox ID Register
+                                                          AT91C_CAN_MB2_MDL EQU( 0xFFFD0254 );
+                                                          -( CAN_MB2 ) MailBox Data Low Register
+                                                          AT91C_CAN_MB2_MMR EQU( 0xFFFD0240 );
+                                                          -( CAN_MB2 ) MailBox Mode Register
+                                                          AT91C_CAN_MB2_MAM EQU( 0xFFFD0244 );
+                                                          -( CAN_MB2 ) MailBox Acceptance Mask Register
+                                                          AT91C_CAN_MB2_MFID EQU( 0xFFFD024C );
+                                                          -( CAN_MB2 ) MailBox Family ID Register
+                                                          AT91C_CAN_MB2_MSR EQU( 0xFFFD0250 );
+                                                          -( CAN_MB2 ) MailBox Status Register
+/* - ========== Register definition for CAN_MB3 peripheral ========== */
+                                                          AT91C_CAN_MB3_MFID EQU( 0xFFFD026C );
+                                                          -( CAN_MB3 ) MailBox Family ID Register
+                                                          AT91C_CAN_MB3_MAM EQU( 0xFFFD0264 );
+                                                          -( CAN_MB3 ) MailBox Acceptance Mask Register
+                                                          AT91C_CAN_MB3_MID EQU( 0xFFFD0268 );
+                                                          -( CAN_MB3 ) MailBox ID Register
+                                                          AT91C_CAN_MB3_MCR EQU( 0xFFFD027C );
+                                                          -( CAN_MB3 ) MailBox Control Register
+                                                          AT91C_CAN_MB3_MMR EQU( 0xFFFD0260 );
+                                                          -( CAN_MB3 ) MailBox Mode Register
+                                                          AT91C_CAN_MB3_MSR EQU( 0xFFFD0270 );
+                                                          -( CAN_MB3 ) MailBox Status Register
+                                                          AT91C_CAN_MB3_MDL EQU( 0xFFFD0274 );
+                                                          -( CAN_MB3 ) MailBox Data Low Register
+                                                          AT91C_CAN_MB3_MDH EQU( 0xFFFD0278 );
+                                                          -( CAN_MB3 ) MailBox Data High Register
+/* - ========== Register definition for CAN_MB4 peripheral ========== */
+                                                          AT91C_CAN_MB4_MID EQU( 0xFFFD0288 );
+                                                          -( CAN_MB4 ) MailBox ID Register
+                                                          AT91C_CAN_MB4_MMR EQU( 0xFFFD0280 );
+                                                          -( CAN_MB4 ) MailBox Mode Register
+                                                          AT91C_CAN_MB4_MDH EQU( 0xFFFD0298 );
+                                                          -( CAN_MB4 ) MailBox Data High Register
+                                                          AT91C_CAN_MB4_MFID EQU( 0xFFFD028C );
+                                                          -( CAN_MB4 ) MailBox Family ID Register
+                                                          AT91C_CAN_MB4_MSR EQU( 0xFFFD0290 );
+                                                          -( CAN_MB4 ) MailBox Status Register
+                                                          AT91C_CAN_MB4_MCR EQU( 0xFFFD029C );
+                                                          -( CAN_MB4 ) MailBox Control Register
+                                                          AT91C_CAN_MB4_MDL EQU( 0xFFFD0294 );
+                                                          -( CAN_MB4 ) MailBox Data Low Register
+                                                          AT91C_CAN_MB4_MAM EQU( 0xFFFD0284 );
+                                                          -( CAN_MB4 ) MailBox Acceptance Mask Register
+/* - ========== Register definition for CAN_MB5 peripheral ========== */
+                                                          AT91C_CAN_MB5_MSR EQU( 0xFFFD02B0 );
+                                                          -( CAN_MB5 ) MailBox Status Register
+                                                          AT91C_CAN_MB5_MCR EQU( 0xFFFD02BC );
+                                                          -( CAN_MB5 ) MailBox Control Register
+                                                          AT91C_CAN_MB5_MFID EQU( 0xFFFD02AC );
+                                                          -( CAN_MB5 ) MailBox Family ID Register
+                                                          AT91C_CAN_MB5_MDH EQU( 0xFFFD02B8 );
+                                                          -( CAN_MB5 ) MailBox Data High Register
+                                                          AT91C_CAN_MB5_MID EQU( 0xFFFD02A8 );
+                                                          -( CAN_MB5 ) MailBox ID Register
+                                                          AT91C_CAN_MB5_MMR EQU( 0xFFFD02A0 );
+                                                          -( CAN_MB5 ) MailBox Mode Register
+                                                          AT91C_CAN_MB5_MDL EQU( 0xFFFD02B4 );
+                                                          -( CAN_MB5 ) MailBox Data Low Register
+                                                          AT91C_CAN_MB5_MAM EQU( 0xFFFD02A4 );
+                                                          -( CAN_MB5 ) MailBox Acceptance Mask Register
+/* - ========== Register definition for CAN_MB6 peripheral ========== */
+                                                          AT91C_CAN_MB6_MFID EQU( 0xFFFD02CC );
+                                                          -( CAN_MB6 ) MailBox Family ID Register
+                                                          AT91C_CAN_MB6_MID EQU( 0xFFFD02C8 );
+                                                          -( CAN_MB6 ) MailBox ID Register
+                                                          AT91C_CAN_MB6_MAM EQU( 0xFFFD02C4 );
+                                                          -( CAN_MB6 ) MailBox Acceptance Mask Register
+                                                          AT91C_CAN_MB6_MSR EQU( 0xFFFD02D0 );
+                                                          -( CAN_MB6 ) MailBox Status Register
+                                                          AT91C_CAN_MB6_MDL EQU( 0xFFFD02D4 );
+                                                          -( CAN_MB6 ) MailBox Data Low Register
+                                                          AT91C_CAN_MB6_MCR EQU( 0xFFFD02DC );
+                                                          -( CAN_MB6 ) MailBox Control Register
+                                                          AT91C_CAN_MB6_MDH EQU( 0xFFFD02D8 );
+                                                          -( CAN_MB6 ) MailBox Data High Register
+                                                          AT91C_CAN_MB6_MMR EQU( 0xFFFD02C0 );
+                                                          -( CAN_MB6 ) MailBox Mode Register
+/* - ========== Register definition for CAN_MB7 peripheral ========== */
+                                                          AT91C_CAN_MB7_MCR EQU( 0xFFFD02FC );
+                                                          -( CAN_MB7 ) MailBox Control Register
+                                                          AT91C_CAN_MB7_MDH EQU( 0xFFFD02F8 );
+                                                          -( CAN_MB7 ) MailBox Data High Register
+                                                          AT91C_CAN_MB7_MFID EQU( 0xFFFD02EC );
+                                                          -( CAN_MB7 ) MailBox Family ID Register
+                                                          AT91C_CAN_MB7_MDL EQU( 0xFFFD02F4 );
+                                                          -( CAN_MB7 ) MailBox Data Low Register
+                                                          AT91C_CAN_MB7_MID EQU( 0xFFFD02E8 );
+                                                          -( CAN_MB7 ) MailBox ID Register
+                                                          AT91C_CAN_MB7_MMR EQU( 0xFFFD02E0 );
+                                                          -( CAN_MB7 ) MailBox Mode Register
+                                                          AT91C_CAN_MB7_MAM EQU( 0xFFFD02E4 );
+                                                          -( CAN_MB7 ) MailBox Acceptance Mask Register
+                                                          AT91C_CAN_MB7_MSR EQU( 0xFFFD02F0 );
+                                                          -( CAN_MB7 ) MailBox Status Register
+/* - ========== Register definition for CAN peripheral ========== */
+                                                          AT91C_CAN_TCR EQU( 0xFFFD0024 );
+                                                          -( CAN ) Transfer Command Register
+                                                          AT91C_CAN_IMR EQU( 0xFFFD000C );
+                                                          -( CAN ) Interrupt Mask Register
+                                                          AT91C_CAN_IER EQU( 0xFFFD0004 );
+                                                          -( CAN ) Interrupt Enable Register
+                                                          AT91C_CAN_ECR EQU( 0xFFFD0020 );
+                                                          -( CAN ) Error Counter Register
+                                                          AT91C_CAN_TIMESTP EQU( 0xFFFD001C );
+                                                          -( CAN ) Time Stamp Register
+                                                          AT91C_CAN_MR EQU( 0xFFFD0000 );
+                                                          -( CAN ) Mode Register
+                                                          AT91C_CAN_IDR EQU( 0xFFFD0008 );
+                                                          -( CAN ) Interrupt Disable Register
+                                                          AT91C_CAN_ACR EQU( 0xFFFD0028 );
+                                                          -( CAN ) Abort Command Register
+                                                          AT91C_CAN_TIM EQU( 0xFFFD0018 );
+                                                          -( CAN ) Timer Register
+                                                          AT91C_CAN_SR EQU( 0xFFFD0010 );
+                                                          -( CAN ) Status Register
+                                                          AT91C_CAN_BR EQU( 0xFFFD0014 );
+                                                          -( CAN ) Baudrate Register
+                                                          AT91C_CAN_VR EQU( 0xFFFD00FC );
+                                                          -( CAN ) Version Register
+/* - ========== Register definition for EMAC peripheral ========== */
+                                                          AT91C_EMAC_ISR EQU( 0xFFFDC024 );
+                                                          -( EMAC ) Interrupt Status Register
+                                                          AT91C_EMAC_SA4H EQU( 0xFFFDC0B4 );
+                                                          -( EMAC ) Specific Address 4 Top, Last 2 bytes
+                                                          AT91C_EMAC_SA1L EQU( 0xFFFDC098 );
+                                                          -( EMAC ) Specific Address 1 Bottom, First 4 bytes
+                                                          AT91C_EMAC_ELE EQU( 0xFFFDC078 );
+                                                          -( EMAC ) Excessive Length Errors Register
+                                                          AT91C_EMAC_LCOL EQU( 0xFFFDC05C );
+                                                          -( EMAC ) Late Collision Register
+                                                          AT91C_EMAC_RLE EQU( 0xFFFDC088 );
+                                                          -( EMAC ) Receive Length Field Mismatch Register
+                                                          AT91C_EMAC_WOL EQU( 0xFFFDC0C4 );
+                                                          -( EMAC ) Wake On LAN Register
+                                                          AT91C_EMAC_DTF EQU( 0xFFFDC058 );
+                                                          -( EMAC ) Deferred Transmission Frame Register
+                                                          AT91C_EMAC_TUND EQU( 0xFFFDC064 );
+                                                          -( EMAC ) Transmit Underrun Error Register
+                                                          AT91C_EMAC_NCR EQU( 0xFFFDC000 );
+                                                          -( EMAC ) Network Control Register
+                                                          AT91C_EMAC_SA4L EQU( 0xFFFDC0B0 );
+                                                          -( EMAC ) Specific Address 4 Bottom, First 4 bytes
+                                                          AT91C_EMAC_RSR EQU( 0xFFFDC020 );
+                                                          -( EMAC ) Receive Status Register
+                                                          AT91C_EMAC_SA3L EQU( 0xFFFDC0A8 );
+                                                          -( EMAC ) Specific Address 3 Bottom, First 4 bytes
+                                                          AT91C_EMAC_TSR EQU( 0xFFFDC014 );
+                                                          -( EMAC ) Transmit Status Register
+                                                          AT91C_EMAC_IDR EQU( 0xFFFDC02C );
+                                                          -( EMAC ) Interrupt Disable Register
+                                                          AT91C_EMAC_RSE EQU( 0xFFFDC074 );
+                                                          -( EMAC ) Receive Symbol Errors Register
+                                                          AT91C_EMAC_ECOL EQU( 0xFFFDC060 );
+                                                          -( EMAC ) Excessive Collision Register
+                                                          AT91C_EMAC_TID EQU( 0xFFFDC0B8 );
+                                                          -( EMAC ) Type ID Checking Register
+                                                          AT91C_EMAC_HRB EQU( 0xFFFDC090 );
+                                                          -( EMAC ) Hash Address Bottom[ 31 : 0 ]
+                                                          AT91C_EMAC_TBQP EQU( 0xFFFDC01C );
+                                                          -( EMAC ) Transmit Buffer Queue Pointer
+                                                          AT91C_EMAC_USRIO EQU( 0xFFFDC0C0 );
+                                                          -( EMAC ) USER Input / Output Register
+                                                          AT91C_EMAC_PTR EQU( 0xFFFDC038 );
+                                                          -( EMAC ) Pause Time Register
+                                                          AT91C_EMAC_SA2H EQU( 0xFFFDC0A4 );
+                                                          -( EMAC ) Specific Address 2 Top, Last 2 bytes
+                                                          AT91C_EMAC_ROV EQU( 0xFFFDC070 );
+                                                          -( EMAC ) Receive Overrun Errors Register
+                                                          AT91C_EMAC_ALE EQU( 0xFFFDC054 );
+                                                          -( EMAC ) Alignment Error Register
+                                                          AT91C_EMAC_RJA EQU( 0xFFFDC07C );
+                                                          -( EMAC ) Receive Jabbers Register
+                                                          AT91C_EMAC_RBQP EQU( 0xFFFDC018 );
+                                                          -( EMAC ) Receive Buffer Queue Pointer
+                                                          AT91C_EMAC_TPF EQU( 0xFFFDC08C );
+                                                          -( EMAC ) Transmitted Pause Frames Register
+                                                          AT91C_EMAC_NCFGR EQU( 0xFFFDC004 );
+                                                          -( EMAC ) Network Configuration Register
+                                                          AT91C_EMAC_HRT EQU( 0xFFFDC094 );
+                                                          -( EMAC ) Hash Address Top[ 63 : 32 ]
+                                                          AT91C_EMAC_USF EQU( 0xFFFDC080 );
+                                                          -( EMAC ) Undersize Frames Register
+                                                          AT91C_EMAC_FCSE EQU( 0xFFFDC050 );
+                                                          -( EMAC ) Frame Check Sequence Error Register
+                                                          AT91C_EMAC_TPQ EQU( 0xFFFDC0BC );
+                                                          -( EMAC ) Transmit Pause Quantum Register
+                                                          AT91C_EMAC_MAN EQU( 0xFFFDC034 );
+                                                          -( EMAC ) PHY Maintenance Register
+                                                          AT91C_EMAC_FTO EQU( 0xFFFDC040 );
+                                                          -( EMAC ) Frames Transmitted OK Register
+                                                          AT91C_EMAC_REV EQU( 0xFFFDC0FC );
+                                                          -( EMAC ) Revision Register
+                                                          AT91C_EMAC_IMR EQU( 0xFFFDC030 );
+                                                          -( EMAC ) Interrupt Mask Register
+                                                          AT91C_EMAC_SCF EQU( 0xFFFDC044 );
+                                                          -( EMAC ) Single Collision Frame Register
+                                                          AT91C_EMAC_PFR EQU( 0xFFFDC03C );
+                                                          -( EMAC ) Pause Frames received Register
+                                                          AT91C_EMAC_MCF EQU( 0xFFFDC048 );
+                                                          -( EMAC ) Multiple Collision Frame Register
+                                                          AT91C_EMAC_NSR EQU( 0xFFFDC008 );
+                                                          -( EMAC ) Network Status Register
+                                                          AT91C_EMAC_SA2L EQU( 0xFFFDC0A0 );
+                                                          -( EMAC ) Specific Address 2 Bottom, First 4 bytes
+                                                          AT91C_EMAC_FRO EQU( 0xFFFDC04C );
+                                                          -( EMAC ) Frames Received OK Register
+                                                          AT91C_EMAC_IER EQU( 0xFFFDC028 );
+                                                          -( EMAC ) Interrupt Enable Register
+                                                          AT91C_EMAC_SA1H EQU( 0xFFFDC09C );
+                                                          -( EMAC ) Specific Address 1 Top, Last 2 bytes
+                                                          AT91C_EMAC_CSE EQU( 0xFFFDC068 );
+                                                          -( EMAC ) Carrier Sense Error Register
+                                                          AT91C_EMAC_SA3H EQU( 0xFFFDC0AC );
+                                                          -( EMAC ) Specific Address 3 Top, Last 2 bytes
+                                                          AT91C_EMAC_RRE EQU( 0xFFFDC06C );
+                                                          -( EMAC ) Receive Ressource Error Register
+                                                          AT91C_EMAC_STE EQU( 0xFFFDC084 );
+                                                          -( EMAC ) SQE Test Error Register
+/* - ========== Register definition for PDC_ADC peripheral ========== */
+                                                          AT91C_ADC_PTSR EQU( 0xFFFD8124 );
+                                                          -( PDC_ADC ) PDC Transfer Status Register
+                                                          AT91C_ADC_PTCR EQU( 0xFFFD8120 );
+                                                          -( PDC_ADC ) PDC Transfer Control Register
+                                                          AT91C_ADC_TNPR EQU( 0xFFFD8118 );
+                                                          -( PDC_ADC ) Transmit Next Pointer Register
+                                                          AT91C_ADC_TNCR EQU( 0xFFFD811C );
+                                                          -( PDC_ADC ) Transmit Next Counter Register
+                                                          AT91C_ADC_RNPR EQU( 0xFFFD8110 );
+                                                          -( PDC_ADC ) Receive Next Pointer Register
+                                                          AT91C_ADC_RNCR EQU( 0xFFFD8114 );
+                                                          -( PDC_ADC ) Receive Next Counter Register
+                                                          AT91C_ADC_RPR EQU( 0xFFFD8100 );
+                                                          -( PDC_ADC ) Receive Pointer Register
+                                                          AT91C_ADC_TCR EQU( 0xFFFD810C );
+                                                          -( PDC_ADC ) Transmit Counter Register
+                                                          AT91C_ADC_TPR EQU( 0xFFFD8108 );
+                                                          -( PDC_ADC ) Transmit Pointer Register
+                                                          AT91C_ADC_RCR EQU( 0xFFFD8104 );
+                                                          -( PDC_ADC ) Receive Counter Register
+/* - ========== Register definition for ADC peripheral ========== */
+                                                          AT91C_ADC_CDR2 EQU( 0xFFFD8038 );
+                                                          -( ADC ) ADC Channel Data Register 2
+                                                          AT91C_ADC_CDR3 EQU( 0xFFFD803C );
+                                                          -( ADC ) ADC Channel Data Register 3
+                                                          AT91C_ADC_CDR0 EQU( 0xFFFD8030 );
+                                                          -( ADC ) ADC Channel Data Register 0
+                                                          AT91C_ADC_CDR5 EQU( 0xFFFD8044 );
+                                                          -( ADC ) ADC Channel Data Register 5
+                                                          AT91C_ADC_CHDR EQU( 0xFFFD8014 );
+                                                          -( ADC ) ADC Channel Disable Register
+                                                          AT91C_ADC_SR EQU( 0xFFFD801C );
+                                                          -( ADC ) ADC Status Register
+                                                          AT91C_ADC_CDR4 EQU( 0xFFFD8040 );
+                                                          -( ADC ) ADC Channel Data Register 4
+                                                          AT91C_ADC_CDR1 EQU( 0xFFFD8034 );
+                                                          -( ADC ) ADC Channel Data Register 1
+                                                          AT91C_ADC_LCDR EQU( 0xFFFD8020 );
+                                                          -( ADC ) ADC Last Converted Data Register
+                                                          AT91C_ADC_IDR EQU( 0xFFFD8028 );
+                                                          -( ADC ) ADC Interrupt Disable Register
+                                                          AT91C_ADC_CR EQU( 0xFFFD8000 );
+                                                          -( ADC ) ADC Control Register
+                                                          AT91C_ADC_CDR7 EQU( 0xFFFD804C );
+                                                          -( ADC ) ADC Channel Data Register 7
+                                                          AT91C_ADC_CDR6 EQU( 0xFFFD8048 );
+                                                          -( ADC ) ADC Channel Data Register 6
+                                                          AT91C_ADC_IER EQU( 0xFFFD8024 );
+                                                          -( ADC ) ADC Interrupt Enable Register
+                                                          AT91C_ADC_CHER EQU( 0xFFFD8010 );
+                                                          -( ADC ) ADC Channel Enable Register
+                                                          AT91C_ADC_CHSR EQU( 0xFFFD8018 );
+                                                          -( ADC ) ADC Channel Status Register
+                                                          AT91C_ADC_MR EQU( 0xFFFD8004 );
+                                                          -( ADC ) ADC Mode Register
+                                                          AT91C_ADC_IMR EQU( 0xFFFD802C );
+                                                          -( ADC ) ADC Interrupt Mask Register
+/* - ========== Register definition for PDC_AES peripheral ========== */
+                                                          AT91C_AES_TPR EQU( 0xFFFA4108 );
+                                                          -( PDC_AES ) Transmit Pointer Register
+                                                          AT91C_AES_PTCR EQU( 0xFFFA4120 );
+                                                          -( PDC_AES ) PDC Transfer Control Register
+                                                          AT91C_AES_RNPR EQU( 0xFFFA4110 );
+                                                          -( PDC_AES ) Receive Next Pointer Register
+                                                          AT91C_AES_TNCR EQU( 0xFFFA411C );
+                                                          -( PDC_AES ) Transmit Next Counter Register
+                                                          AT91C_AES_TCR EQU( 0xFFFA410C );
+                                                          -( PDC_AES ) Transmit Counter Register
+                                                          AT91C_AES_RCR EQU( 0xFFFA4104 );
+                                                          -( PDC_AES ) Receive Counter Register
+                                                          AT91C_AES_RNCR EQU( 0xFFFA4114 );
+                                                          -( PDC_AES ) Receive Next Counter Register
+                                                          AT91C_AES_TNPR EQU( 0xFFFA4118 );
+                                                          -( PDC_AES ) Transmit Next Pointer Register
+                                                          AT91C_AES_RPR EQU( 0xFFFA4100 );
+                                                          -( PDC_AES ) Receive Pointer Register
+                                                          AT91C_AES_PTSR EQU( 0xFFFA4124 );
+                                                          -( PDC_AES ) PDC Transfer Status Register
+/* - ========== Register definition for AES peripheral ========== */
+                                                          AT91C_AES_IVxR EQU( 0xFFFA4060 );
+                                                          -( AES ) Initialization Vector x Register
+                                                          AT91C_AES_MR EQU( 0xFFFA4004 );
+                                                          -( AES ) Mode Register
+                                                          AT91C_AES_VR EQU( 0xFFFA40FC );
+                                                          -( AES ) AES Version Register
+                                                          AT91C_AES_ODATAxR EQU( 0xFFFA4050 );
+                                                          -( AES ) Output Data x Register
+                                                          AT91C_AES_IDATAxR EQU( 0xFFFA4040 );
+                                                          -( AES ) Input Data x Register
+                                                          AT91C_AES_CR EQU( 0xFFFA4000 );
+                                                          -( AES ) Control Register
+                                                          AT91C_AES_IDR EQU( 0xFFFA4014 );
+                                                          -( AES ) Interrupt Disable Register
+                                                          AT91C_AES_IMR EQU( 0xFFFA4018 );
+                                                          -( AES ) Interrupt Mask Register
+                                                          AT91C_AES_IER EQU( 0xFFFA4010 );
+                                                          -( AES ) Interrupt Enable Register
+                                                          AT91C_AES_KEYWxR EQU( 0xFFFA4020 );
+                                                          -( AES ) Key Word x Register
+                                                          AT91C_AES_ISR EQU( 0xFFFA401C );
+                                                          -( AES ) Interrupt Status Register
+/* - ========== Register definition for PDC_TDES peripheral ========== */
+                                                          AT91C_TDES_RNCR EQU( 0xFFFA8114 );
+                                                          -( PDC_TDES ) Receive Next Counter Register
+                                                          AT91C_TDES_TCR EQU( 0xFFFA810C );
+                                                          -( PDC_TDES ) Transmit Counter Register
+                                                          AT91C_TDES_RCR EQU( 0xFFFA8104 );
+                                                          -( PDC_TDES ) Receive Counter Register
+                                                          AT91C_TDES_TNPR EQU( 0xFFFA8118 );
+                                                          -( PDC_TDES ) Transmit Next Pointer Register
+                                                          AT91C_TDES_RNPR EQU( 0xFFFA8110 );
+                                                          -( PDC_TDES ) Receive Next Pointer Register
+                                                          AT91C_TDES_RPR EQU( 0xFFFA8100 );
+                                                          -( PDC_TDES ) Receive Pointer Register
+                                                          AT91C_TDES_TNCR EQU( 0xFFFA811C );
+                                                          -( PDC_TDES ) Transmit Next Counter Register
+                                                          AT91C_TDES_TPR EQU( 0xFFFA8108 );
+                                                          -( PDC_TDES ) Transmit Pointer Register
+                                                          AT91C_TDES_PTSR EQU( 0xFFFA8124 );
+                                                          -( PDC_TDES ) PDC Transfer Status Register
+                                                          AT91C_TDES_PTCR EQU( 0xFFFA8120 );
+                                                          -( PDC_TDES ) PDC Transfer Control Register
+/* - ========== Register definition for TDES peripheral ========== */
+                                                          AT91C_TDES_KEY2WxR EQU( 0xFFFA8028 );
+                                                          -( TDES ) Key 2 Word x Register
+                                                          AT91C_TDES_KEY3WxR EQU( 0xFFFA8030 );
+                                                          -( TDES ) Key 3 Word x Register
+                                                          AT91C_TDES_IDR EQU( 0xFFFA8014 );
+                                                          -( TDES ) Interrupt Disable Register
+                                                          AT91C_TDES_VR EQU( 0xFFFA80FC );
+                                                          -( TDES ) TDES Version Register
+                                                          AT91C_TDES_IVxR EQU( 0xFFFA8060 );
+                                                          -( TDES ) Initialization Vector x Register
+                                                          AT91C_TDES_ODATAxR EQU( 0xFFFA8050 );
+                                                          -( TDES ) Output Data x Register
+                                                          AT91C_TDES_IMR EQU( 0xFFFA8018 );
+                                                          -( TDES ) Interrupt Mask Register
+                                                          AT91C_TDES_MR EQU( 0xFFFA8004 );
+                                                          -( TDES ) Mode Register
+                                                          AT91C_TDES_CR EQU( 0xFFFA8000 );
+                                                          -( TDES ) Control Register
+                                                          AT91C_TDES_IER EQU( 0xFFFA8010 );
+                                                          -( TDES ) Interrupt Enable Register
+                                                          AT91C_TDES_ISR EQU( 0xFFFA801C );
+                                                          -( TDES ) Interrupt Status Register
+                                                          AT91C_TDES_IDATAxR EQU( 0xFFFA8040 );
+                                                          -( TDES ) Input Data x Register
+                                                          AT91C_TDES_KEY1WxR EQU( 0xFFFA8020 );
+                                                          -( TDES ) Key 1 Word x Register
+
+/* - ***************************************************************************** */
+/* -               PIO DEFINITIONS FOR AT91SAM7X256 */
+/* - ***************************************************************************** */
+                                                          AT91C_PIO_PA0 EQU( 1 << 0 );
+                                                          -Pin Controlled by PA0
+                                                          AT91C_PA0_RXD0 EQU( AT91C_PIO_PA0 );
+                                                          -USART 0 Receive Data
+                                                          AT91C_PIO_PA1 EQU( 1 << 1 );
+                                                          -Pin Controlled by PA1
+                                                          AT91C_PA1_TXD0 EQU( AT91C_PIO_PA1 );
+                                                          -USART 0 Transmit Data
+                                                          AT91C_PIO_PA10 EQU( 1 << 10 );
+                                                          -Pin Controlled by PA10
+                                                          AT91C_PA10_TWD EQU( AT91C_PIO_PA10 );
+                                                          -TWI Two - wire Serial Data
+                                                          AT91C_PIO_PA11 EQU( 1 << 11 );
+                                                          -Pin Controlled by PA11
+                                                          AT91C_PA11_TWCK EQU( AT91C_PIO_PA11 );
+                                                          -TWI Two - wire Serial Clock
+                                                          AT91C_PIO_PA12 EQU( 1 << 12 );
+                                                          -Pin Controlled by PA12
+                                                          AT91C_PA12_NPCS00 EQU( AT91C_PIO_PA12 );
+                                                          -SPI 0 Peripheral Chip Select 0
+                                                          AT91C_PIO_PA13 EQU( 1 << 13 );
+                                                          -Pin Controlled by PA13
+                                                          AT91C_PA13_NPCS01 EQU( AT91C_PIO_PA13 );
+                                                          -SPI 0 Peripheral Chip Select 1
+                                                          AT91C_PA13_PCK1 EQU( AT91C_PIO_PA13 );
+                                                          -PMC Programmable Clock Output 1
+                                                          AT91C_PIO_PA14 EQU( 1 << 14 );
+                                                          -Pin Controlled by PA14
+                                                          AT91C_PA14_NPCS02 EQU( AT91C_PIO_PA14 );
+                                                          -SPI 0 Peripheral Chip Select 2
+                                                          AT91C_PA14_IRQ1 EQU( AT91C_PIO_PA14 );
+                                                          -External Interrupt 1
+                                                          AT91C_PIO_PA15 EQU( 1 << 15 );
+                                                          -Pin Controlled by PA15
+                                                          AT91C_PA15_NPCS03 EQU( AT91C_PIO_PA15 );
+                                                          -SPI 0 Peripheral Chip Select 3
+                                                          AT91C_PA15_TCLK2 EQU( AT91C_PIO_PA15 );
+                                                          -Timer Counter 2 external clock input
+                                                          AT91C_PIO_PA16 EQU( 1 << 16 );
+                                                          -Pin Controlled by PA16
+                                                          AT91C_PA16_MISO0 EQU( AT91C_PIO_PA16 );
+                                                          -SPI 0 Master In Slave
+                                                          AT91C_PIO_PA17 EQU( 1 << 17 );
+                                                          -Pin Controlled by PA17
+                                                          AT91C_PA17_MOSI0 EQU( AT91C_PIO_PA17 );
+                                                          -SPI 0 Master Out Slave
+                                                          AT91C_PIO_PA18 EQU( 1 << 18 );
+                                                          -Pin Controlled by PA18
+                                                          AT91C_PA18_SPCK0 EQU( AT91C_PIO_PA18 );
+                                                          -SPI 0 Serial Clock
+                                                          AT91C_PIO_PA19 EQU( 1 << 19 );
+                                                          -Pin Controlled by PA19
+                                                          AT91C_PA19_CANRX EQU( AT91C_PIO_PA19 );
+                                                          -CAN Receive
+                                                          AT91C_PIO_PA2 EQU( 1 << 2 );
+                                                          -Pin Controlled by PA2
+                                                          AT91C_PA2_SCK0 EQU( AT91C_PIO_PA2 );
+                                                          -USART 0 Serial Clock
+                                                          AT91C_PA2_NPCS11 EQU( AT91C_PIO_PA2 );
+                                                          -SPI 1 Peripheral Chip Select 1
+                                                          AT91C_PIO_PA20 EQU( 1 << 20 );
+                                                          -Pin Controlled by PA20
+                                                          AT91C_PA20_CANTX EQU( AT91C_PIO_PA20 );
+                                                          -CAN Transmit
+                                                          AT91C_PIO_PA21 EQU( 1 << 21 );
+                                                          -Pin Controlled by PA21
+                                                          AT91C_PA21_TF EQU( AT91C_PIO_PA21 );
+                                                          -SSC Transmit Frame Sync
+                                                          AT91C_PA21_NPCS10 EQU( AT91C_PIO_PA21 );
+                                                          -SPI 1 Peripheral Chip Select 0
+                                                          AT91C_PIO_PA22 EQU( 1 << 22 );
+                                                          -Pin Controlled by PA22
+                                                          AT91C_PA22_TK EQU( AT91C_PIO_PA22 );
+                                                          -SSC Transmit Clock
+                                                          AT91C_PA22_SPCK1 EQU( AT91C_PIO_PA22 );
+                                                          -SPI 1 Serial Clock
+                                                          AT91C_PIO_PA23 EQU( 1 << 23 );
+                                                          -Pin Controlled by PA23
+                                                          AT91C_PA23_TD EQU( AT91C_PIO_PA23 );
+                                                          -SSC Transmit data
+                                                          AT91C_PA23_MOSI1 EQU( AT91C_PIO_PA23 );
+                                                          -SPI 1 Master Out Slave
+                                                          AT91C_PIO_PA24 EQU( 1 << 24 );
+                                                          -Pin Controlled by PA24
+                                                          AT91C_PA24_RD EQU( AT91C_PIO_PA24 );
+                                                          -SSC Receive Data
+                                                          AT91C_PA24_MISO1 EQU( AT91C_PIO_PA24 );
+                                                          -SPI 1 Master In Slave
+                                                          AT91C_PIO_PA25 EQU( 1 << 25 );
+                                                          -Pin Controlled by PA25
+                                                          AT91C_PA25_RK EQU( AT91C_PIO_PA25 );
+                                                          -SSC Receive Clock
+                                                          AT91C_PA25_NPCS11 EQU( AT91C_PIO_PA25 );
+                                                          -SPI 1 Peripheral Chip Select 1
+                                                          AT91C_PIO_PA26 EQU( 1 << 26 );
+                                                          -Pin Controlled by PA26
+                                                          AT91C_PA26_RF EQU( AT91C_PIO_PA26 );
+                                                          -SSC Receive Frame Sync
+                                                          AT91C_PA26_NPCS12 EQU( AT91C_PIO_PA26 );
+                                                          -SPI 1 Peripheral Chip Select 2
+                                                          AT91C_PIO_PA27 EQU( 1 << 27 );
+                                                          -Pin Controlled by PA27
+                                                          AT91C_PA27_DRXD EQU( AT91C_PIO_PA27 );
+                                                          -DBGU Debug Receive Data
+                                                          AT91C_PA27_PCK3 EQU( AT91C_PIO_PA27 );
+                                                          -PMC Programmable Clock Output 3
+                                                          AT91C_PIO_PA28 EQU( 1 << 28 );
+                                                          -Pin Controlled by PA28
+                                                          AT91C_PA28_DTXD EQU( AT91C_PIO_PA28 );
+                                                          -DBGU Debug Transmit Data
+                                                          AT91C_PIO_PA29 EQU( 1 << 29 );
+                                                          -Pin Controlled by PA29
+                                                          AT91C_PA29_FIQ EQU( AT91C_PIO_PA29 );
+                                                          -AIC Fast Interrupt Input
+                                                          AT91C_PA29_NPCS13 EQU( AT91C_PIO_PA29 );
+                                                          -SPI 1 Peripheral Chip Select 3
+                                                          AT91C_PIO_PA3 EQU( 1 << 3 );
+                                                          -Pin Controlled by PA3
+                                                          AT91C_PA3_RTS0 EQU( AT91C_PIO_PA3 );
+                                                          -USART 0 Ready To Send
+                                                          AT91C_PA3_NPCS12 EQU( AT91C_PIO_PA3 );
+                                                          -SPI 1 Peripheral Chip Select 2
+                                                          AT91C_PIO_PA30 EQU( 1 << 30 );
+                                                          -Pin Controlled by PA30
+                                                          AT91C_PA30_IRQ0 EQU( AT91C_PIO_PA30 );
+                                                          -External Interrupt 0
+                                                          AT91C_PA30_PCK2 EQU( AT91C_PIO_PA30 );
+                                                          -PMC Programmable Clock Output 2
+                                                          AT91C_PIO_PA4 EQU( 1 << 4 );
+                                                          -Pin Controlled by PA4
+                                                          AT91C_PA4_CTS0 EQU( AT91C_PIO_PA4 );
+                                                          -USART 0 Clear To Send
+                                                          AT91C_PA4_NPCS13 EQU( AT91C_PIO_PA4 );
+                                                          -SPI 1 Peripheral Chip Select 3
+                                                          AT91C_PIO_PA5 EQU( 1 << 5 );
+                                                          -Pin Controlled by PA5
+                                                          AT91C_PA5_RXD1 EQU( AT91C_PIO_PA5 );
+                                                          -USART 1 Receive Data
+                                                          AT91C_PIO_PA6 EQU( 1 << 6 );
+                                                          -Pin Controlled by PA6
+                                                          AT91C_PA6_TXD1 EQU( AT91C_PIO_PA6 );
+                                                          -USART 1 Transmit Data
+                                                          AT91C_PIO_PA7 EQU( 1 << 7 );
+                                                          -Pin Controlled by PA7
+                                                          AT91C_PA7_SCK1 EQU( AT91C_PIO_PA7 );
+                                                          -USART 1 Serial Clock
+                                                          AT91C_PA7_NPCS01 EQU( AT91C_PIO_PA7 );
+                                                          -SPI 0 Peripheral Chip Select 1
+                                                          AT91C_PIO_PA8 EQU( 1 << 8 );
+                                                          -Pin Controlled by PA8
+                                                          AT91C_PA8_RTS1 EQU( AT91C_PIO_PA8 );
+                                                          -USART 1 Ready To Send
+                                                          AT91C_PA8_NPCS02 EQU( AT91C_PIO_PA8 );
+                                                          -SPI 0 Peripheral Chip Select 2
+                                                          AT91C_PIO_PA9 EQU( 1 << 9 );
+                                                          -Pin Controlled by PA9
+                                                          AT91C_PA9_CTS1 EQU( AT91C_PIO_PA9 );
+                                                          -USART 1 Clear To Send
+                                                          AT91C_PA9_NPCS03 EQU( AT91C_PIO_PA9 );
+                                                          -SPI 0 Peripheral Chip Select 3
+                                                          AT91C_PIO_PB0 EQU( 1 << 0 );
+                                                          -Pin Controlled by PB0
+                                                          AT91C_PB0_ETXCK_EREFCK EQU( AT91C_PIO_PB0 );
+                                                          -Ethernet MAC Transmit Clock / Reference Clock
+                                                          AT91C_PB0_PCK0 EQU( AT91C_PIO_PB0 );
+                                                          -PMC Programmable Clock Output 0
+                                                          AT91C_PIO_PB1 EQU( 1 << 1 );
+                                                          -Pin Controlled by PB1
+                                                          AT91C_PB1_ETXEN EQU( AT91C_PIO_PB1 );
+                                                          -Ethernet MAC Transmit Enable
+                                                          AT91C_PIO_PB10 EQU( 1 << 10 );
+                                                          -Pin Controlled by PB10
+                                                          AT91C_PB10_ETX2 EQU( AT91C_PIO_PB10 );
+                                                          -Ethernet MAC Transmit Data 2
+                                                          AT91C_PB10_NPCS11 EQU( AT91C_PIO_PB10 );
+                                                          -SPI 1 Peripheral Chip Select 1
+                                                          AT91C_PIO_PB11 EQU( 1 << 11 );
+                                                          -Pin Controlled by PB11
+                                                          AT91C_PB11_ETX3 EQU( AT91C_PIO_PB11 );
+                                                          -Ethernet MAC Transmit Data 3
+                                                          AT91C_PB11_NPCS12 EQU( AT91C_PIO_PB11 );
+                                                          -SPI 1 Peripheral Chip Select 2
+                                                          AT91C_PIO_PB12 EQU( 1 << 12 );
+                                                          -Pin Controlled by PB12
+                                                          AT91C_PB12_ETXER EQU( AT91C_PIO_PB12 );
+                                                          -Ethernet MAC Transmit Coding Error
+                                                          AT91C_PB12_TCLK0 EQU( AT91C_PIO_PB12 );
+                                                          -Timer Counter 0 external clock input
+                                                          AT91C_PIO_PB13 EQU( 1 << 13 );
+                                                          -Pin Controlled by PB13
+                                                          AT91C_PB13_ERX2 EQU( AT91C_PIO_PB13 );
+                                                          -Ethernet MAC Receive Data 2
+                                                          AT91C_PB13_NPCS01 EQU( AT91C_PIO_PB13 );
+                                                          -SPI 0 Peripheral Chip Select 1
+                                                          AT91C_PIO_PB14 EQU( 1 << 14 );
+                                                          -Pin Controlled by PB14
+                                                          AT91C_PB14_ERX3 EQU( AT91C_PIO_PB14 );
+                                                          -Ethernet MAC Receive Data 3
+                                                          AT91C_PB14_NPCS02 EQU( AT91C_PIO_PB14 );
+                                                          -SPI 0 Peripheral Chip Select 2
+                                                          AT91C_PIO_PB15 EQU( 1 << 15 );
+                                                          -Pin Controlled by PB15
+                                                          AT91C_PB15_ERXDV EQU( AT91C_PIO_PB15 );
+                                                          -Ethernet MAC Receive Data Valid
+                                                          AT91C_PIO_PB16 EQU( 1 << 16 );
+                                                          -Pin Controlled by PB16
+                                                          AT91C_PB16_ECOL EQU( AT91C_PIO_PB16 );
+                                                          -Ethernet MAC Collision Detected
+                                                          AT91C_PB16_NPCS13 EQU( AT91C_PIO_PB16 );
+                                                          -SPI 1 Peripheral Chip Select 3
+                                                          AT91C_PIO_PB17 EQU( 1 << 17 );
+                                                          -Pin Controlled by PB17
+                                                          AT91C_PB17_ERXCK EQU( AT91C_PIO_PB17 );
+                                                          -Ethernet MAC Receive Clock
+                                                          AT91C_PB17_NPCS03 EQU( AT91C_PIO_PB17 );
+                                                          -SPI 0 Peripheral Chip Select 3
+                                                          AT91C_PIO_PB18 EQU( 1 << 18 );
+                                                          -Pin Controlled by PB18
+                                                          AT91C_PB18_EF100 EQU( AT91C_PIO_PB18 );
+                                                          -Ethernet MAC Force 100 Mbits / sec
+                                                          AT91C_PB18_ADTRG EQU( AT91C_PIO_PB18 );
+                                                          -ADC External Trigger
+                                                          AT91C_PIO_PB19 EQU( 1 << 19 );
+                                                          -Pin Controlled by PB19
+                                                          AT91C_PB19_PWM0 EQU( AT91C_PIO_PB19 );
+                                                          -PWM Channel 0
+                                                          AT91C_PB19_TCLK1 EQU( AT91C_PIO_PB19 );
+                                                          -Timer Counter 1 external clock input
+                                                          AT91C_PIO_PB2 EQU( 1 << 2 );
+                                                          -Pin Controlled by PB2
+                                                          AT91C_PB2_ETX0 EQU( AT91C_PIO_PB2 );
+                                                          -Ethernet MAC Transmit Data 0
+                                                          AT91C_PIO_PB20 EQU( 1 << 20 );
+                                                          -Pin Controlled by PB20
+                                                          AT91C_PB20_PWM1 EQU( AT91C_PIO_PB20 );
+                                                          -PWM Channel 1
+                                                          AT91C_PB20_PCK0 EQU( AT91C_PIO_PB20 );
+                                                          -PMC Programmable Clock Output 0
+                                                          AT91C_PIO_PB21 EQU( 1 << 21 );
+                                                          -Pin Controlled by PB21
+                                                          AT91C_PB21_PWM2 EQU( AT91C_PIO_PB21 );
+                                                          -PWM Channel 2
+                                                          AT91C_PB21_PCK1 EQU( AT91C_PIO_PB21 );
+                                                          -PMC Programmable Clock Output 1
+                                                          AT91C_PIO_PB22 EQU( 1 << 22 );
+                                                          -Pin Controlled by PB22
+                                                          AT91C_PB22_PWM3 EQU( AT91C_PIO_PB22 );
+                                                          -PWM Channel 3
+                                                          AT91C_PB22_PCK2 EQU( AT91C_PIO_PB22 );
+                                                          -PMC Programmable Clock Output 2
+                                                          AT91C_PIO_PB23 EQU( 1 << 23 );
+                                                          -Pin Controlled by PB23
+                                                          AT91C_PB23_TIOA0 EQU( AT91C_PIO_PB23 );
+                                                          -Timer Counter 0 Multipurpose Timer I / O Pin A
+                                                          AT91C_PB23_DCD1 EQU( AT91C_PIO_PB23 );
+                                                          -USART 1 Data Carrier Detect
+                                                          AT91C_PIO_PB24 EQU( 1 << 24 );
+                                                          -Pin Controlled by PB24
+                                                          AT91C_PB24_TIOB0 EQU( AT91C_PIO_PB24 );
+                                                          -Timer Counter 0 Multipurpose Timer I / O Pin B
+                                                          AT91C_PB24_DSR1 EQU( AT91C_PIO_PB24 );
+                                                          -USART 1 Data Set ready
+                                                          AT91C_PIO_PB25 EQU( 1 << 25 );
+                                                          -Pin Controlled by PB25
+                                                          AT91C_PB25_TIOA1 EQU( AT91C_PIO_PB25 );
+                                                          -Timer Counter 1 Multipurpose Timer I / O Pin A
+                                                          AT91C_PB25_DTR1 EQU( AT91C_PIO_PB25 );
+                                                          -USART 1 Data Terminal ready
+                                                          AT91C_PIO_PB26 EQU( 1 << 26 );
+                                                          -Pin Controlled by PB26
+                                                          AT91C_PB26_TIOB1 EQU( AT91C_PIO_PB26 );
+                                                          -Timer Counter 1 Multipurpose Timer I / O Pin B
+                                                          AT91C_PB26_RI1 EQU( AT91C_PIO_PB26 );
+                                                          -USART 1 Ring Indicator
+                                                          AT91C_PIO_PB27 EQU( 1 << 27 );
+                                                          -Pin Controlled by PB27
+                                                          AT91C_PB27_TIOA2 EQU( AT91C_PIO_PB27 );
+                                                          -Timer Counter 2 Multipurpose Timer I / O Pin A
+                                                          AT91C_PB27_PWM0 EQU( AT91C_PIO_PB27 );
+                                                          -PWM Channel 0
+                                                          AT91C_PIO_PB28 EQU( 1 << 28 );
+                                                          -Pin Controlled by PB28
+                                                          AT91C_PB28_TIOB2 EQU( AT91C_PIO_PB28 );
+                                                          -Timer Counter 2 Multipurpose Timer I / O Pin B
+                                                          AT91C_PB28_PWM1 EQU( AT91C_PIO_PB28 );
+                                                          -PWM Channel 1
+                                                          AT91C_PIO_PB29 EQU( 1 << 29 );
+                                                          -Pin Controlled by PB29
+                                                          AT91C_PB29_PCK1 EQU( AT91C_PIO_PB29 );
+                                                          -PMC Programmable Clock Output 1
+                                                          AT91C_PB29_PWM2 EQU( AT91C_PIO_PB29 );
+                                                          -PWM Channel 2
+                                                          AT91C_PIO_PB3 EQU( 1 << 3 );
+                                                          -Pin Controlled by PB3
+                                                          AT91C_PB3_ETX1 EQU( AT91C_PIO_PB3 );
+                                                          -Ethernet MAC Transmit Data 1
+                                                          AT91C_PIO_PB30 EQU( 1 << 30 );
+                                                          -Pin Controlled by PB30
+                                                          AT91C_PB30_PCK2 EQU( AT91C_PIO_PB30 );
+                                                          -PMC Programmable Clock Output 2
+                                                          AT91C_PB30_PWM3 EQU( AT91C_PIO_PB30 );
+                                                          -PWM Channel 3
+                                                          AT91C_PIO_PB4 EQU( 1 << 4 );
+                                                          -Pin Controlled by PB4
+                                                          AT91C_PB4_ECRS_ECRSDV EQU( AT91C_PIO_PB4 );
+                                                          -Ethernet MAC Carrier Sense / Carrier Sense and Data Valid
+                                                          AT91C_PIO_PB5 EQU( 1 << 5 );
+                                                          -Pin Controlled by PB5
+                                                          AT91C_PB5_ERX0 EQU( AT91C_PIO_PB5 );
+                                                          -Ethernet MAC Receive Data 0
+                                                          AT91C_PIO_PB6 EQU( 1 << 6 );
+                                                          -Pin Controlled by PB6
+                                                          AT91C_PB6_ERX1 EQU( AT91C_PIO_PB6 );
+                                                          -Ethernet MAC Receive Data 1
+                                                          AT91C_PIO_PB7 EQU( 1 << 7 );
+                                                          -Pin Controlled by PB7
+                                                          AT91C_PB7_ERXER EQU( AT91C_PIO_PB7 );
+                                                          -Ethernet MAC Receive Error
+                                                          AT91C_PIO_PB8 EQU( 1 << 8 );
+                                                          -Pin Controlled by PB8
+                                                          AT91C_PB8_EMDC EQU( AT91C_PIO_PB8 );
+                                                          -Ethernet MAC Management Data Clock
+                                                          AT91C_PIO_PB9 EQU( 1 << 9 );
+                                                          -Pin Controlled by PB9
+                                                          AT91C_PB9_EMDIO EQU( AT91C_PIO_PB9 );
+                                                          -Ethernet MAC Management Data Input / Output
+
+/* - ***************************************************************************** */
+/* -               PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 */
+/* - ***************************************************************************** */
+                                                          AT91C_ID_FIQ EQU( 0 );
+                                                          -Advanced Interrupt Controller( FIQ )
+                                                          AT91C_ID_SYS EQU( 1 );
+                                                          -System Peripheral
+                                                          AT91C_ID_PIOA EQU( 2 );
+                                                          -Parallel IO Controller A
+                                                          AT91C_ID_PIOB EQU( 3 );
+                                                          -Parallel IO Controller B
+                                                          AT91C_ID_SPI0 EQU( 4 );
+                                                          -Serial Peripheral Interface 0
+                                                          AT91C_ID_SPI1 EQU( 5 );
+                                                          -Serial Peripheral Interface 1
+                                                          AT91C_ID_US0 EQU( 6 );
+                                                          -USART 0
+                                                          AT91C_ID_US1 EQU( 7 );
+                                                          -USART 1
+                                                          AT91C_ID_SSC EQU( 8 );
+                                                          -Serial Synchronous Controller
+                                                          AT91C_ID_TWI EQU( 9 );
+                                                          -Two - Wire Interface
+                                                          AT91C_ID_PWMC EQU( 10 );
+                                                          -PWM Controller
+                                                          AT91C_ID_UDP EQU( 11 );
+                                                          -USB Device Port
+                                                          AT91C_ID_TC0 EQU( 12 );
+                                                          -Timer Counter 0
+                                                          AT91C_ID_TC1 EQU( 13 );
+                                                          -Timer Counter 1
+                                                          AT91C_ID_TC2 EQU( 14 );
+                                                          -Timer Counter 2
+                                                          AT91C_ID_CAN EQU( 15 );
+                                                          -Control Area Network Controller
+                                                          AT91C_ID_EMAC EQU( 16 );
+                                                          -Ethernet MAC
+                                                          AT91C_ID_ADC EQU( 17 );
+                                                          -Analog - to - Digital Converter
+                                                          AT91C_ID_AES EQU( 18 );
+                                                          -Advanced Encryption Standard 128 - bit
+                                                          AT91C_ID_TDES EQU( 19 );
+                                                          -Triple Data Encryption Standard
+                                                          AT91C_ID_20_Reserved EQU( 20 );
+                                                          -Reserved
+                                                          AT91C_ID_21_Reserved EQU( 21 );
+                                                          -Reserved
+                                                          AT91C_ID_22_Reserved EQU( 22 );
+                                                          -Reserved
+                                                          AT91C_ID_23_Reserved EQU( 23 );
+                                                          -Reserved
+                                                          AT91C_ID_24_Reserved EQU( 24 );
+                                                          -Reserved
+                                                          AT91C_ID_25_Reserved EQU( 25 );
+                                                          -Reserved
+                                                          AT91C_ID_26_Reserved EQU( 26 );
+                                                          -Reserved
+                                                          AT91C_ID_27_Reserved EQU( 27 );
+                                                          -Reserved
+                                                          AT91C_ID_28_Reserved EQU( 28 );
+                                                          -Reserved
+                                                          AT91C_ID_29_Reserved EQU( 29 );
+                                                          -Reserved
+                                                          AT91C_ID_IRQ0 EQU( 30 );
+                                                          -Advanced Interrupt Controller( IRQ0 )
+                                                          AT91C_ID_IRQ1 EQU( 31 );
+                                                          -Advanced Interrupt Controller( IRQ1 )
+
+/* - ***************************************************************************** */
+/* -               BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 */
+/* - ***************************************************************************** */
+                                                          AT91C_BASE_SYS EQU( 0xFFFFF000 );
+                                                          -( SYS ) Base Address
+                                                          AT91C_BASE_AIC EQU( 0xFFFFF000 );
+                                                          -( AIC ) Base Address
+                                                          AT91C_BASE_PDC_DBGU EQU( 0xFFFFF300 );
+                                                          -( PDC_DBGU ) Base Address
+                                                          AT91C_BASE_DBGU EQU( 0xFFFFF200 );
+                                                          -( DBGU ) Base Address
+                                                          AT91C_BASE_PIOA EQU( 0xFFFFF400 );
+                                                          -( PIOA ) Base Address
+                                                          AT91C_BASE_PIOB EQU( 0xFFFFF600 );
+                                                          -( PIOB ) Base Address
+                                                          AT91C_BASE_CKGR EQU( 0xFFFFFC20 );
+                                                          -( CKGR ) Base Address
+                                                          AT91C_BASE_PMC EQU( 0xFFFFFC00 );
+                                                          -( PMC ) Base Address
+                                                          AT91C_BASE_RSTC EQU( 0xFFFFFD00 );
+                                                          -( RSTC ) Base Address
+                                                          AT91C_BASE_RTTC EQU( 0xFFFFFD20 );
+                                                          -( RTTC ) Base Address
+                                                          AT91C_BASE_PITC EQU( 0xFFFFFD30 );
+                                                          -( PITC ) Base Address
+                                                          AT91C_BASE_WDTC EQU( 0xFFFFFD40 );
+                                                          -( WDTC ) Base Address
+                                                          AT91C_BASE_VREG EQU( 0xFFFFFD60 );
+                                                          -( VREG ) Base Address
+                                                          AT91C_BASE_MC EQU( 0xFFFFFF00 );
+                                                          -( MC ) Base Address
+                                                          AT91C_BASE_PDC_SPI1 EQU( 0xFFFE4100 );
+                                                          -( PDC_SPI1 ) Base Address
+                                                          AT91C_BASE_SPI1 EQU( 0xFFFE4000 );
+                                                          -( SPI1 ) Base Address
+                                                          AT91C_BASE_PDC_SPI0 EQU( 0xFFFE0100 );
+                                                          -( PDC_SPI0 ) Base Address
+                                                          AT91C_BASE_SPI0 EQU( 0xFFFE0000 );
+                                                          -( SPI0 ) Base Address
+                                                          AT91C_BASE_PDC_US1 EQU( 0xFFFC4100 );
+                                                          -( PDC_US1 ) Base Address
+                                                          AT91C_BASE_US1 EQU( 0xFFFC4000 );
+                                                          -( US1 ) Base Address
+                                                          AT91C_BASE_PDC_US0 EQU( 0xFFFC0100 );
+                                                          -( PDC_US0 ) Base Address
+                                                          AT91C_BASE_US0 EQU( 0xFFFC0000 );
+                                                          -( US0 ) Base Address
+                                                          AT91C_BASE_PDC_SSC EQU( 0xFFFD4100 );
+                                                          -( PDC_SSC ) Base Address
+                                                          AT91C_BASE_SSC EQU( 0xFFFD4000 );
+                                                          -( SSC ) Base Address
+                                                          AT91C_BASE_TWI EQU( 0xFFFB8000 );
+                                                          -( TWI ) Base Address
+                                                          AT91C_BASE_PWMC_CH3 EQU( 0xFFFCC260 );
+                                                          -( PWMC_CH3 ) Base Address
+                                                          AT91C_BASE_PWMC_CH2 EQU( 0xFFFCC240 );
+                                                          -( PWMC_CH2 ) Base Address
+                                                          AT91C_BASE_PWMC_CH1 EQU( 0xFFFCC220 );
+                                                          -( PWMC_CH1 ) Base Address
+                                                          AT91C_BASE_PWMC_CH0 EQU( 0xFFFCC200 );
+                                                          -( PWMC_CH0 ) Base Address
+                                                          AT91C_BASE_PWMC EQU( 0xFFFCC000 );
+                                                          -( PWMC ) Base Address
+                                                          AT91C_BASE_UDP EQU( 0xFFFB0000 );
+                                                          -( UDP ) Base Address
+                                                          AT91C_BASE_TC0 EQU( 0xFFFA0000 );
+                                                          -( TC0 ) Base Address
+                                                          AT91C_BASE_TC1 EQU( 0xFFFA0040 );
+                                                          -( TC1 ) Base Address
+                                                          AT91C_BASE_TC2 EQU( 0xFFFA0080 );
+                                                          -( TC2 ) Base Address
+                                                          AT91C_BASE_TCB EQU( 0xFFFA0000 );
+                                                          -( TCB ) Base Address
+                                                          AT91C_BASE_CAN_MB0 EQU( 0xFFFD0200 );
+                                                          -( CAN_MB0 ) Base Address
+                                                          AT91C_BASE_CAN_MB1 EQU( 0xFFFD0220 );
+                                                          -( CAN_MB1 ) Base Address
+                                                          AT91C_BASE_CAN_MB2 EQU( 0xFFFD0240 );
+                                                          -( CAN_MB2 ) Base Address
+                                                          AT91C_BASE_CAN_MB3 EQU( 0xFFFD0260 );
+                                                          -( CAN_MB3 ) Base Address
+                                                          AT91C_BASE_CAN_MB4 EQU( 0xFFFD0280 );
+                                                          -( CAN_MB4 ) Base Address
+                                                          AT91C_BASE_CAN_MB5 EQU( 0xFFFD02A0 );
+                                                          -( CAN_MB5 ) Base Address
+                                                          AT91C_BASE_CAN_MB6 EQU( 0xFFFD02C0 );
+                                                          -( CAN_MB6 ) Base Address
+                                                          AT91C_BASE_CAN_MB7 EQU( 0xFFFD02E0 );
+                                                          -( CAN_MB7 ) Base Address
+                                                          AT91C_BASE_CAN EQU( 0xFFFD0000 );
+                                                          -( CAN ) Base Address
+                                                          AT91C_BASE_EMAC EQU( 0xFFFDC000 );
+                                                          -( EMAC ) Base Address
+                                                          AT91C_BASE_PDC_ADC EQU( 0xFFFD8100 );
+                                                          -( PDC_ADC ) Base Address
+                                                          AT91C_BASE_ADC EQU( 0xFFFD8000 );
+                                                          -( ADC ) Base Address
+                                                          AT91C_BASE_PDC_AES EQU( 0xFFFA4100 );
+                                                          -( PDC_AES ) Base Address
+                                                          AT91C_BASE_AES EQU( 0xFFFA4000 );
+                                                          -( AES ) Base Address
+                                                          AT91C_BASE_PDC_TDES EQU( 0xFFFA8100 );
+                                                          -( PDC_TDES ) Base Address
+                                                          AT91C_BASE_TDES EQU( 0xFFFA8000 );
+                                                          -( TDES ) Base Address
+
+/* - ***************************************************************************** */
+/* -               MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 */
+/* - ***************************************************************************** */
+                                                          AT91C_ISRAM EQU( 0x00200000 );
+                                                          -Internal SRAM base address
+                                                          AT91C_ISRAM_SIZE EQU( 0x00010000 );
+                                                          -Internal SRAM size in byte( 64 Kbyte )
+                                                          AT91C_IFLASH EQU( 0x00100000 );
+                                                          -Internal ROM base address
+                                                          AT91C_IFLASH_SIZE EQU( 0x00040000 );
+                                                          -Internal ROM size in byte( 256 Kbyte )
 
 
 
diff --git a/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.c b/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.c
index 240c7334b..269d390cc 100644
--- a/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.c
+++ b/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.c
@@ -1,50 +1,50 @@
-//* ----------------------------------------------------------------------------
-//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
-//* ----------------------------------------------------------------------------
-//* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
-//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
-//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
-//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
-//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//* ----------------------------------------------------------------------------
-//* File Name           : lib_AT91SAM7X256.h
-//* Object              : AT91SAM7X256 inlined functions
-//* Generated           : AT91 SW Application Group  05/20/2005 (16:22:29)
-//*
-//* CVS Reference       : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003//
-//* CVS Reference       : /lib_pmc_SAM7X.h/1.1/Tue Feb  1 08:32:10 2005//
-//* CVS Reference       : /lib_VREG_6085B.h/1.1/Tue Feb  1 16:20:47 2005//
-//* CVS Reference       : /lib_rstc_6098A.h/1.1/Wed Oct  6 10:39:20 2004//
-//* CVS Reference       : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003//
-//* CVS Reference       : /lib_wdtc_6080A.h/1.1/Wed Oct  6 10:38:30 2004//
-//* CVS Reference       : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002//
-//* CVS Reference       : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003//
-//* CVS Reference       : /lib_pitc_6079A.h/1.2/Tue Nov  9 14:43:56 2004//
-//* CVS Reference       : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005//
-//* CVS Reference       : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005//
-//* CVS Reference       : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004//
-//* CVS Reference       : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003//
-//* CVS Reference       : /lib_rttc_6081A.h/1.1/Wed Oct  6 10:39:38 2004//
-//* CVS Reference       : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005//
-//* CVS Reference       : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005//
-//* CVS Reference       : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//
-//* CVS Reference       : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004//
-//* CVS Reference       : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003//
-//* CVS Reference       : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003//
-//* CVS Reference       : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//
-//* CVS Reference       : /lib_pdc.h/1.2/Tue Jul  2 13:29:40 2002//
-//* ----------------------------------------------------------------------------
+/** ---------------------------------------------------------------------------- */
+/**         ATMEL Microcontroller Software Support  -  ROUSSET  - */
+/** ---------------------------------------------------------------------------- */
+/** DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
+/** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/** MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
+/** DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
+/** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/** LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
+/** OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
+/** LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
+/** NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/** EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
+/** ---------------------------------------------------------------------------- */
+/** File Name           : lib_AT91SAM7X256.h */
+/** Object              : AT91SAM7X256 inlined functions */
+/** Generated           : AT91 SW Application Group  05/20/2005 (16:22:29) */
+/** */
+/** CVS Reference       : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003// */
+/** CVS Reference       : /lib_pmc_SAM7X.h/1.1/Tue Feb  1 08:32:10 2005// */
+/** CVS Reference       : /lib_VREG_6085B.h/1.1/Tue Feb  1 16:20:47 2005// */
+/** CVS Reference       : /lib_rstc_6098A.h/1.1/Wed Oct  6 10:39:20 2004// */
+/** CVS Reference       : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// */
+/** CVS Reference       : /lib_wdtc_6080A.h/1.1/Wed Oct  6 10:38:30 2004// */
+/** CVS Reference       : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002// */
+/** CVS Reference       : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003// */
+/** CVS Reference       : /lib_pitc_6079A.h/1.2/Tue Nov  9 14:43:56 2004// */
+/** CVS Reference       : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005// */
+/** CVS Reference       : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005// */
+/** CVS Reference       : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004// */
+/** CVS Reference       : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003// */
+/** CVS Reference       : /lib_rttc_6081A.h/1.1/Wed Oct  6 10:39:38 2004// */
+/** CVS Reference       : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005// */
+/** CVS Reference       : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005// */
+/** CVS Reference       : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// */
+/** CVS Reference       : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004// */
+/** CVS Reference       : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// */
+/** CVS Reference       : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003// */
+/** CVS Reference       : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// */
+/** CVS Reference       : /lib_pdc.h/1.2/Tue Jul  2 13:29:40 2002// */
+/** ---------------------------------------------------------------------------- */
 
 
 #include "AT91SAM7X256.h"
 
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_ConfigureIt
-//* \brief Interrupt Handler Initialization
-//*----------------------------------------------------------------------------
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_AIC_ConfigureIt */
+/** \brief Interrupt Handler Initialization */
+/**---------------------------------------------------------------------------- */
diff --git a/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.h b/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.h
index 556e0ca16..0d9a70884 100644
--- a/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.h
+++ b/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.h
@@ -1,1469 +1,1396 @@
-//* ----------------------------------------------------------------------------
-//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
-//* ----------------------------------------------------------------------------
-//* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
-//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
-//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
-//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
-//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//* ----------------------------------------------------------------------------
-//* File Name           : lib_AT91SAM7X256.h
-//* Object              : AT91SAM7X256 inlined functions
-//* Generated           : AT91 SW Application Group  05/20/2005 (16:22:29)
-//*
-//* CVS Reference       : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003//
-//* CVS Reference       : /lib_pmc_SAM7X.h/1.1/Tue Feb  1 08:32:10 2005//
-//* CVS Reference       : /lib_VREG_6085B.h/1.1/Tue Feb  1 16:20:47 2005//
-//* CVS Reference       : /lib_rstc_6098A.h/1.1/Wed Oct  6 10:39:20 2004//
-//* CVS Reference       : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003//
-//* CVS Reference       : /lib_wdtc_6080A.h/1.1/Wed Oct  6 10:38:30 2004//
-//* CVS Reference       : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002//
-//* CVS Reference       : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003//
-//* CVS Reference       : /lib_pitc_6079A.h/1.2/Tue Nov  9 14:43:56 2004//
-//* CVS Reference       : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005//
-//* CVS Reference       : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005//
-//* CVS Reference       : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004//
-//* CVS Reference       : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003//
-//* CVS Reference       : /lib_rttc_6081A.h/1.1/Wed Oct  6 10:39:38 2004//
-//* CVS Reference       : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005//
-//* CVS Reference       : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005//
-//* CVS Reference       : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//
-//* CVS Reference       : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004//
-//* CVS Reference       : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003//
-//* CVS Reference       : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003//
-//* CVS Reference       : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//
-//* CVS Reference       : /lib_pdc.h/1.2/Tue Jul  2 13:29:40 2002//
-//* ----------------------------------------------------------------------------
+/** ---------------------------------------------------------------------------- */
+/**         ATMEL Microcontroller Software Support  -  ROUSSET  - */
+/** ---------------------------------------------------------------------------- */
+/** DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
+/** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/** MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
+/** DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
+/** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/** LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
+/** OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
+/** LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
+/** NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/** EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
+/** ---------------------------------------------------------------------------- */
+/** File Name           : lib_AT91SAM7X256.h */
+/** Object              : AT91SAM7X256 inlined functions */
+/** Generated           : AT91 SW Application Group  05/20/2005 (16:22:29) */
+/** */
+/** CVS Reference       : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003// */
+/** CVS Reference       : /lib_pmc_SAM7X.h/1.1/Tue Feb  1 08:32:10 2005// */
+/** CVS Reference       : /lib_VREG_6085B.h/1.1/Tue Feb  1 16:20:47 2005// */
+/** CVS Reference       : /lib_rstc_6098A.h/1.1/Wed Oct  6 10:39:20 2004// */
+/** CVS Reference       : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// */
+/** CVS Reference       : /lib_wdtc_6080A.h/1.1/Wed Oct  6 10:38:30 2004// */
+/** CVS Reference       : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002// */
+/** CVS Reference       : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003// */
+/** CVS Reference       : /lib_pitc_6079A.h/1.2/Tue Nov  9 14:43:56 2004// */
+/** CVS Reference       : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005// */
+/** CVS Reference       : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005// */
+/** CVS Reference       : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004// */
+/** CVS Reference       : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003// */
+/** CVS Reference       : /lib_rttc_6081A.h/1.1/Wed Oct  6 10:39:38 2004// */
+/** CVS Reference       : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005// */
+/** CVS Reference       : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005// */
+/** CVS Reference       : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// */
+/** CVS Reference       : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004// */
+/** CVS Reference       : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// */
+/** CVS Reference       : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003// */
+/** CVS Reference       : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// */
+/** CVS Reference       : /lib_pdc.h/1.2/Tue Jul  2 13:29:40 2002// */
+/** ---------------------------------------------------------------------------- */
 
 #ifndef lib_AT91SAM7X256_H
-#define lib_AT91SAM7X256_H
+    #define lib_AT91SAM7X256_H
 
 /* *****************************************************************************
-                SOFTWARE API FOR AIC
-   ***************************************************************************** */
-#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20]
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_ConfigureIt
-//* \brief Interrupt Handler Initialization
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_AIC_ConfigureIt (
-    AT91PS_AIC pAic,  // \arg pointer to the AIC registers
-    unsigned int irq_id,     // \arg interrupt number to initialize
-    unsigned int priority,   // \arg priority to give to the interrupt
-    unsigned int src_type,   // \arg activation and sense of activation
-    void (*newHandler) (void) ) // \arg address of the interrupt handler
-{
-    unsigned int oldHandler;
-    unsigned int mask ;
-
-    oldHandler = pAic->AIC_SVR[irq_id];
-
-    mask = 0x1 << irq_id ;
-    //* Disable the interrupt on the interrupt controller
-    pAic->AIC_IDCR = mask ;
-    //* Save the interrupt handler routine pointer and the interrupt priority
-    pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ;
-    //* Store the Source Mode Register
-    pAic->AIC_SMR[irq_id] = src_type | priority  ;
-    //* Clear the interrupt on the interrupt controller
-    pAic->AIC_ICCR = mask ;
-
-    return oldHandler;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_EnableIt
-//* \brief Enable corresponding IT number
-//*----------------------------------------------------------------------------
-__inline void AT91F_AIC_EnableIt (
-    AT91PS_AIC pAic,      // \arg pointer to the AIC registers
-    unsigned int irq_id ) // \arg interrupt number to initialize
-{
-    //* Enable the interrupt on the interrupt controller
-    pAic->AIC_IECR = 0x1 << irq_id ;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_DisableIt
-//* \brief Disable corresponding IT number
-//*----------------------------------------------------------------------------
-__inline void AT91F_AIC_DisableIt (
-    AT91PS_AIC pAic,      // \arg pointer to the AIC registers
-    unsigned int irq_id ) // \arg interrupt number to initialize
-{
-    unsigned int mask = 0x1 << irq_id;
-    //* Disable the interrupt on the interrupt controller
-    pAic->AIC_IDCR = mask ;
-    //* Clear the interrupt on the Interrupt Controller ( if one is pending )
-    pAic->AIC_ICCR = mask ;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_ClearIt
-//* \brief Clear corresponding IT number
-//*----------------------------------------------------------------------------
-__inline void AT91F_AIC_ClearIt (
-    AT91PS_AIC pAic,     // \arg pointer to the AIC registers
-    unsigned int irq_id) // \arg interrupt number to initialize
-{
-    //* Clear the interrupt on the Interrupt Controller ( if one is pending )
-    pAic->AIC_ICCR = (0x1 << irq_id);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_AcknowledgeIt
-//* \brief Acknowledge corresponding IT number
-//*----------------------------------------------------------------------------
-__inline void AT91F_AIC_AcknowledgeIt (
-    AT91PS_AIC pAic)     // \arg pointer to the AIC registers
-{
-    pAic->AIC_EOICR = pAic->AIC_EOICR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_SetExceptionVector
-//* \brief Configure vector handler
-//*----------------------------------------------------------------------------
-__inline unsigned int  AT91F_AIC_SetExceptionVector (
-    unsigned int *pVector, // \arg pointer to the AIC registers
-    void (*Handler) () )   // \arg Interrupt Handler
-{
-    unsigned int oldVector = *pVector;
-
-    if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE)
-        *pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE;
-    else
-        *pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000;
-
-    return oldVector;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_Trig
-//* \brief Trig an IT
-//*----------------------------------------------------------------------------
-__inline void  AT91F_AIC_Trig (
-    AT91PS_AIC pAic,     // \arg pointer to the AIC registers
-    unsigned int irq_id) // \arg interrupt number
-{
-    pAic->AIC_ISCR = (0x1 << irq_id) ;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_IsActive
-//* \brief Test if an IT is active
-//*----------------------------------------------------------------------------
-__inline unsigned int  AT91F_AIC_IsActive (
-    AT91PS_AIC pAic,     // \arg pointer to the AIC registers
-    unsigned int irq_id) // \arg Interrupt Number
-{
-    return (pAic->AIC_ISR & (0x1 << irq_id));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_IsPending
-//* \brief Test if an IT is pending
-//*----------------------------------------------------------------------------
-__inline unsigned int  AT91F_AIC_IsPending (
-    AT91PS_AIC pAic,     // \arg pointer to the AIC registers
-    unsigned int irq_id) // \arg Interrupt Number
-{
-    return (pAic->AIC_IPR & (0x1 << irq_id));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_Open
-//* \brief Set exception vectors and AIC registers to default values
-//*----------------------------------------------------------------------------
-__inline void AT91F_AIC_Open(
-    AT91PS_AIC pAic,        // \arg pointer to the AIC registers
-    void (*IrqHandler) (),  // \arg Default IRQ vector exception
-    void (*FiqHandler) (),  // \arg Default FIQ vector exception
-    void (*DefaultHandler)  (), // \arg Default Handler set in ISR
-    void (*SpuriousHandler) (), // \arg Default Spurious Handler
-    unsigned int protectMode)   // \arg Debug Control Register
-{
-    int i;
-
-    // Disable all interrupts and set IVR to the default handler
-    for (i = 0; i < 32; ++i) {
-        AT91F_AIC_DisableIt(pAic, i);
-        AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_HIGH_LEVEL, DefaultHandler);
-    }
-
-    // Set the IRQ exception vector
-    AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler);
-    // Set the Fast Interrupt exception vector
-    AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler);
-
-    pAic->AIC_SPU = (unsigned int) SpuriousHandler;
-    pAic->AIC_DCR = protectMode;
-}
-/* *****************************************************************************
-                SOFTWARE API FOR PDC
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_SetNextRx
-//* \brief Set the next receive transfer descriptor
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_SetNextRx (
-    AT91PS_PDC pPDC,     // \arg pointer to a PDC controller
-    char *address,       // \arg address to the next bloc to be received
-    unsigned int bytes)  // \arg number of bytes to be received
-{
-    pPDC->PDC_RNPR = (unsigned int) address;
-    pPDC->PDC_RNCR = bytes;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_SetNextTx
-//* \brief Set the next transmit transfer descriptor
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_SetNextTx (
-    AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
-    char *address,         // \arg address to the next bloc to be transmitted
-    unsigned int bytes)    // \arg number of bytes to be transmitted
-{
-    pPDC->PDC_TNPR = (unsigned int) address;
-    pPDC->PDC_TNCR = bytes;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_SetRx
-//* \brief Set the receive transfer descriptor
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_SetRx (
-    AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
-    char *address,         // \arg address to the next bloc to be received
-    unsigned int bytes)    // \arg number of bytes to be received
-{
-    pPDC->PDC_RPR = (unsigned int) address;
-    pPDC->PDC_RCR = bytes;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_SetTx
-//* \brief Set the transmit transfer descriptor
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_SetTx (
-    AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
-    char *address,         // \arg address to the next bloc to be transmitted
-    unsigned int bytes)    // \arg number of bytes to be transmitted
-{
-    pPDC->PDC_TPR = (unsigned int) address;
-    pPDC->PDC_TCR = bytes;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_EnableTx
-//* \brief Enable transmit
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_EnableTx (
-    AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-    pPDC->PDC_PTCR = AT91C_PDC_TXTEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_EnableRx
-//* \brief Enable receive
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_EnableRx (
-    AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-    pPDC->PDC_PTCR = AT91C_PDC_RXTEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_DisableTx
-//* \brief Disable transmit
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_DisableTx (
-    AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-    pPDC->PDC_PTCR = AT91C_PDC_TXTDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_DisableRx
-//* \brief Disable receive
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_DisableRx (
-    AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-    pPDC->PDC_PTCR = AT91C_PDC_RXTDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_IsTxEmpty
-//* \brief Test if the current transfer descriptor has been sent
-//*----------------------------------------------------------------------------
-__inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete
-    AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-    return !(pPDC->PDC_TCR);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_IsNextTxEmpty
-//* \brief Test if the next transfer descriptor has been moved to the current td
-//*----------------------------------------------------------------------------
-__inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete
-    AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-    return !(pPDC->PDC_TNCR);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_IsRxEmpty
-//* \brief Test if the current transfer descriptor has been filled
-//*----------------------------------------------------------------------------
-__inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete
-    AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-    return !(pPDC->PDC_RCR);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_IsNextRxEmpty
-//* \brief Test if the next transfer descriptor has been moved to the current td
-//*----------------------------------------------------------------------------
-__inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete
-    AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-    return !(pPDC->PDC_RNCR);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_Open
-//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_Open (
-    AT91PS_PDC pPDC)       // \arg pointer to a PDC controller
-{
-    //* Disable the RX and TX PDC transfer requests
-    AT91F_PDC_DisableRx(pPDC);
-    AT91F_PDC_DisableTx(pPDC);
-
-    //* Reset all Counter register Next buffer first
-    AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);
-    AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);
-    AT91F_PDC_SetTx(pPDC, (char *) 0, 0);
-    AT91F_PDC_SetRx(pPDC, (char *) 0, 0);
-
-    //* Enable the RX and TX PDC transfer requests
-    AT91F_PDC_EnableRx(pPDC);
-    AT91F_PDC_EnableTx(pPDC);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_Close
-//* \brief Close PDC: disable TX and RX reset transfer descriptors
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_Close (
-    AT91PS_PDC pPDC)       // \arg pointer to a PDC controller
-{
-    //* Disable the RX and TX PDC transfer requests
-    AT91F_PDC_DisableRx(pPDC);
-    AT91F_PDC_DisableTx(pPDC);
-
-    //* Reset all Counter register Next buffer first
-    AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);
-    AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);
-    AT91F_PDC_SetTx(pPDC, (char *) 0, 0);
-    AT91F_PDC_SetRx(pPDC, (char *) 0, 0);
-
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_SendFrame
-//* \brief Close PDC: disable TX and RX reset transfer descriptors
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PDC_SendFrame(
-    AT91PS_PDC pPDC,
-    char *pBuffer,
-    unsigned int szBuffer,
-    char *pNextBuffer,
-    unsigned int szNextBuffer )
-{
-    if (AT91F_PDC_IsTxEmpty(pPDC)) {
-        //* Buffer and next buffer can be initialized
-        AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer);
-        AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer);
-        return 2;
-    }
-    else if (AT91F_PDC_IsNextTxEmpty(pPDC)) {
-        //* Only one buffer can be initialized
-        AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer);
-        return 1;
-    }
-    else {
-        //* All buffer are in use...
-        return 0;
-    }
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_ReceiveFrame
-//* \brief Close PDC: disable TX and RX reset transfer descriptors
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PDC_ReceiveFrame (
-    AT91PS_PDC pPDC,
-    char *pBuffer,
-    unsigned int szBuffer,
-    char *pNextBuffer,
-    unsigned int szNextBuffer )
-{
-    if (AT91F_PDC_IsRxEmpty(pPDC)) {
-        //* Buffer and next buffer can be initialized
-        AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer);
-        AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer);
-        return 2;
-    }
-    else if (AT91F_PDC_IsNextRxEmpty(pPDC)) {
-        //* Only one buffer can be initialized
-        AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer);
-        return 1;
-    }
-    else {
-        //* All buffer are in use...
-        return 0;
-    }
-}
-/* *****************************************************************************
-                SOFTWARE API FOR DBGU
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_DBGU_InterruptEnable
-//* \brief Enable DBGU Interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_DBGU_InterruptEnable(
-        AT91PS_DBGU pDbgu,   // \arg  pointer to a DBGU controller
-        unsigned int flag) // \arg  dbgu interrupt to be enabled
-{
-        pDbgu->DBGU_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_DBGU_InterruptDisable
-//* \brief Disable DBGU Interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_DBGU_InterruptDisable(
-        AT91PS_DBGU pDbgu,   // \arg  pointer to a DBGU controller
-        unsigned int flag) // \arg  dbgu interrupt to be disabled
-{
-        pDbgu->DBGU_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_DBGU_GetInterruptMaskStatus
-//* \brief Return DBGU Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status
-        AT91PS_DBGU pDbgu) // \arg  pointer to a DBGU controller
-{
-        return pDbgu->DBGU_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_DBGU_IsInterruptMasked
-//* \brief Test if DBGU Interrupt is Masked
-//*----------------------------------------------------------------------------
-__inline int AT91F_DBGU_IsInterruptMasked(
-        AT91PS_DBGU pDbgu,   // \arg  pointer to a DBGU controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag);
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR PIO
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgPeriph
-//* \brief Enable pins to be drived by peripheral
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgPeriph(
-    AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-    unsigned int periphAEnable,  // \arg PERIPH A to enable
-    unsigned int periphBEnable)  // \arg PERIPH B to enable
-
-{
-    pPio->PIO_ASR = periphAEnable;
-    pPio->PIO_BSR = periphBEnable;
-    pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgOutput
-//* \brief Enable PIO in output mode
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgOutput(
-    AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-    unsigned int pioEnable)      // \arg PIO to be enabled
-{
-    pPio->PIO_PER = pioEnable; // Set in PIO mode
-    pPio->PIO_OER = pioEnable; // Configure in Output
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgInput
-//* \brief Enable PIO in input mode
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgInput(
-    AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-    unsigned int inputEnable)      // \arg PIO to be enabled
-{
-    // Disable output
-    pPio->PIO_ODR  = inputEnable;
-    pPio->PIO_PER  = inputEnable;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgOpendrain
-//* \brief Configure PIO in open drain
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgOpendrain(
-    AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-    unsigned int multiDrvEnable) // \arg pio to be configured in open drain
-{
-    // Configure the multi-drive option
-    pPio->PIO_MDDR = ~multiDrvEnable;
-    pPio->PIO_MDER = multiDrvEnable;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgPullup
-//* \brief Enable pullup on PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgPullup(
-    AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-    unsigned int pullupEnable)   // \arg enable pullup on PIO
-{
-        // Connect or not Pullup
-    pPio->PIO_PPUDR = ~pullupEnable;
-    pPio->PIO_PPUER = pullupEnable;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgDirectDrive
-//* \brief Enable direct drive on PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgDirectDrive(
-    AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-    unsigned int directDrive)    // \arg PIO to be configured with direct drive
-
-{
-    // Configure the Direct Drive
-    pPio->PIO_OWDR  = ~directDrive;
-    pPio->PIO_OWER  = directDrive;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgInputFilter
-//* \brief Enable input filter on input PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgInputFilter(
-    AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-    unsigned int inputFilter)    // \arg PIO to be configured with input filter
-
-{
-    // Configure the Direct Drive
-    pPio->PIO_IFDR  = ~inputFilter;
-    pPio->PIO_IFER  = inputFilter;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetInput
-//* \brief Return PIO input value
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetInput( // \return PIO input
-    AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-    return pPio->PIO_PDSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsInputSet
-//* \brief Test if PIO is input flag is active
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsInputSet(
-    AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-    unsigned int flag) // \arg  flag to be tested
-{
-    return (AT91F_PIO_GetInput(pPio) & flag);
-}
-
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_SetOutput
-//* \brief Set to 1 output PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_SetOutput(
-    AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-    unsigned int flag) // \arg  output to be set
-{
-    pPio->PIO_SODR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_ClearOutput
-//* \brief Set to 0 output PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_ClearOutput(
-    AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-    unsigned int flag) // \arg  output to be cleared
-{
-    pPio->PIO_CODR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_ForceOutput
-//* \brief Force output when Direct drive option is enabled
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_ForceOutput(
-    AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-    unsigned int flag) // \arg  output to be forced
-{
-    pPio->PIO_ODSR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_Enable
-//* \brief Enable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_Enable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio to be enabled
-{
-        pPio->PIO_PER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_Disable
-//* \brief Disable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_Disable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio to be disabled
-{
-        pPio->PIO_PDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetStatus
-//* \brief Return PIO Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_PSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsSet
-//* \brief Test if PIO is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_OutputEnable
-//* \brief Output Enable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_OutputEnable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio output to be enabled
-{
-        pPio->PIO_OER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_OutputDisable
-//* \brief Output Enable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_OutputDisable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio output to be disabled
-{
-        pPio->PIO_ODR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetOutputStatus
-//* \brief Return PIO Output Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_OSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsOuputSet
-//* \brief Test if PIO Output is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsOutputSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetOutputStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_InputFilterEnable
-//* \brief Input Filter Enable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_InputFilterEnable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio input filter to be enabled
-{
-        pPio->PIO_IFER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_InputFilterDisable
-//* \brief Input Filter Disable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_InputFilterDisable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio input filter to be disabled
-{
-        pPio->PIO_IFDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetInputFilterStatus
-//* \brief Return PIO Input Filter Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_IFSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsInputFilterSet
-//* \brief Test if PIO Input filter is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsInputFilterSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetInputFilterStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetOutputDataStatus
-//* \brief Return PIO Output Data Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status
-    AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_ODSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_InterruptEnable
-//* \brief Enable PIO Interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_InterruptEnable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio interrupt to be enabled
-{
-        pPio->PIO_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_InterruptDisable
-//* \brief Disable PIO Interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_InterruptDisable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio interrupt to be disabled
-{
-        pPio->PIO_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetInterruptMaskStatus
-//* \brief Return PIO Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetInterruptStatus
-//* \brief Return PIO Interrupt Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_ISR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsInterruptMasked
-//* \brief Test if PIO Interrupt is Masked
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsInterruptMasked(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsInterruptSet
-//* \brief Test if PIO Interrupt is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsInterruptSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetInterruptStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_MultiDriverEnable
-//* \brief Multi Driver Enable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_MultiDriverEnable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio to be enabled
-{
-        pPio->PIO_MDER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_MultiDriverDisable
-//* \brief Multi Driver Disable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_MultiDriverDisable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio to be disabled
-{
-        pPio->PIO_MDDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetMultiDriverStatus
-//* \brief Return PIO Multi Driver Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_MDSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsMultiDriverSet
-//* \brief Test if PIO MultiDriver is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsMultiDriverSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_A_RegisterSelection
-//* \brief PIO A Register Selection
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_A_RegisterSelection(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio A register selection
-{
-        pPio->PIO_ASR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_B_RegisterSelection
-//* \brief PIO B Register Selection
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_B_RegisterSelection(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio B register selection
-{
-        pPio->PIO_BSR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_Get_AB_RegisterStatus
-//* \brief Return PIO Interrupt Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_ABSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsAB_RegisterSet
-//* \brief Test if PIO AB Register is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsAB_RegisterSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_OutputWriteEnable
-//* \brief Output Write Enable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_OutputWriteEnable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio output write to be enabled
-{
-        pPio->PIO_OWER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_OutputWriteDisable
-//* \brief Output Write Disable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_OutputWriteDisable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio output write to be disabled
-{
-        pPio->PIO_OWDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetOutputWriteStatus
-//* \brief Return PIO Output Write Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_OWSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsOutputWriteSet
-//* \brief Test if PIO OutputWrite is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsOutputWriteSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetCfgPullup
-//* \brief Return PIO Configuration Pullup
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_PPUSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsOutputDataStatusSet
-//* \brief Test if PIO Output Data Status is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsOutputDataStatusSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetOutputDataStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsCfgPullupStatusSet
-//* \brief Test if PIO Configuration Pullup Status is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsCfgPullupStatusSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (~AT91F_PIO_GetCfgPullup(pPio) & flag);
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR PMC
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_CfgSysClkEnableReg
-//* \brief Configure the System Clock Enable Register of the PMC controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_CfgSysClkEnableReg (
-    AT91PS_PMC pPMC, // \arg pointer to PMC controller
-    unsigned int mode)
-{
-    //* Write to the SCER register
-    pPMC->PMC_SCER = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_CfgSysClkDisableReg
-//* \brief Configure the System Clock Disable Register of the PMC controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_CfgSysClkDisableReg (
-    AT91PS_PMC pPMC, // \arg pointer to PMC controller
-    unsigned int mode)
-{
-    //* Write to the SCDR register
-    pPMC->PMC_SCDR = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_GetSysClkStatusReg
-//* \brief Return the System Clock Status Register of the PMC controller
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_GetSysClkStatusReg (
-    AT91PS_PMC pPMC // pointer to a CAN controller
-    )
-{
-    return pPMC->PMC_SCSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_EnablePeriphClock
-//* \brief Enable peripheral clock
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_EnablePeriphClock (
-    AT91PS_PMC pPMC, // \arg pointer to PMC controller
-    unsigned int periphIds)  // \arg IDs of peripherals to enable
-{
-    pPMC->PMC_PCER = periphIds;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_DisablePeriphClock
-//* \brief Disable peripheral clock
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_DisablePeriphClock (
-    AT91PS_PMC pPMC, // \arg pointer to PMC controller
-    unsigned int periphIds)  // \arg IDs of peripherals to enable
-{
-    pPMC->PMC_PCDR = periphIds;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_GetPeriphClock
-//* \brief Get peripheral clock status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_GetPeriphClock (
-    AT91PS_PMC pPMC) // \arg pointer to PMC controller
-{
-    return pPMC->PMC_PCSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CKGR_CfgMainOscillatorReg
-//* \brief Cfg the main oscillator
-//*----------------------------------------------------------------------------
-__inline void AT91F_CKGR_CfgMainOscillatorReg (
-    AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
-    unsigned int mode)
-{
-    pCKGR->CKGR_MOR = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CKGR_GetMainOscillatorReg
-//* \brief Cfg the main oscillator
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CKGR_GetMainOscillatorReg (
-    AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
-{
-    return pCKGR->CKGR_MOR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CKGR_EnableMainOscillator
-//* \brief Enable the main oscillator
-//*----------------------------------------------------------------------------
-__inline void AT91F_CKGR_EnableMainOscillator(
-    AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
-{
-    pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CKGR_DisableMainOscillator
-//* \brief Disable the main oscillator
-//*----------------------------------------------------------------------------
-__inline void AT91F_CKGR_DisableMainOscillator (
-    AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
-{
-    pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CKGR_CfgMainOscStartUpTime
-//* \brief Cfg MOR Register according to the main osc startup time
-//*----------------------------------------------------------------------------
-__inline void AT91F_CKGR_CfgMainOscStartUpTime (
-    AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
-    unsigned int startup_time,  // \arg main osc startup time in microsecond (us)
-    unsigned int slowClock)  // \arg slowClock in Hz
-{
-    pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT;
-    pCKGR->CKGR_MOR |= ((slowClock * startup_time)/(8*1000000)) << 8;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CKGR_GetMainClockFreqReg
-//* \brief Cfg the main oscillator
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CKGR_GetMainClockFreqReg (
-    AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
-{
-    return pCKGR->CKGR_MCFR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CKGR_GetMainClock
-//* \brief Return Main clock in Hz
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CKGR_GetMainClock (
-    AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
-    unsigned int slowClock)  // \arg slowClock in Hz
-{
-    return ((pCKGR->CKGR_MCFR  & AT91C_CKGR_MAINF) * slowClock) >> 4;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_CfgMCKReg
-//* \brief Cfg Master Clock Register
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_CfgMCKReg (
-    AT91PS_PMC pPMC, // \arg pointer to PMC controller
-    unsigned int mode)
-{
-    pPMC->PMC_MCKR = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_GetMCKReg
-//* \brief Return Master Clock Register
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_GetMCKReg(
-    AT91PS_PMC pPMC) // \arg pointer to PMC controller
-{
-    return pPMC->PMC_MCKR;
-}
-
-//*------------------------------------------------------------------------------
-//* \fn    AT91F_PMC_GetMasterClock
-//* \brief Return master clock in Hz which correponds to processor clock for ARM7
-//*------------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_GetMasterClock (
-    AT91PS_PMC pPMC, // \arg pointer to PMC controller
-    AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
-    unsigned int slowClock)  // \arg slowClock in Hz
-{
-    unsigned int reg = pPMC->PMC_MCKR;
-    unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2));
-    unsigned int pllDivider, pllMultiplier;
-
-    switch (reg & AT91C_PMC_CSS) {
-        case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected
-            return slowClock / prescaler;
-        case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected
-            return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler;
-        case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected
-            reg = pCKGR->CKGR_PLLR;
-            pllDivider    = (reg  & AT91C_CKGR_DIV);
-            pllMultiplier = ((reg  & AT91C_CKGR_MUL) >> 16) + 1;
-            return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler;
-    }
-    return 0;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_EnablePCK
-//* \brief Enable peripheral clock
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_EnablePCK (
-    AT91PS_PMC pPMC, // \arg pointer to PMC controller
-    unsigned int pck,  // \arg Peripheral clock identifier 0 .. 7
-    unsigned int mode)
-{
-    pPMC->PMC_PCKR[pck] = mode;
-    pPMC->PMC_SCER = (1 << pck) << 8;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_DisablePCK
-//* \brief Enable peripheral clock
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_DisablePCK (
-    AT91PS_PMC pPMC, // \arg pointer to PMC controller
-    unsigned int pck)  // \arg Peripheral clock identifier 0 .. 7
-{
-    pPMC->PMC_SCDR = (1 << pck) << 8;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_EnableIt
-//* \brief Enable PMC interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_EnableIt (
-    AT91PS_PMC pPMC,     // pointer to a PMC controller
-    unsigned int flag)   // IT to be enabled
-{
-    //* Write to the IER register
-    pPMC->PMC_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_DisableIt
-//* \brief Disable PMC interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_DisableIt (
-    AT91PS_PMC pPMC, // pointer to a PMC controller
-    unsigned int flag) // IT to be disabled
-{
-    //* Write to the IDR register
-    pPMC->PMC_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_GetStatus
-//* \brief Return PMC Interrupt Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_GetStatus( // \return PMC Interrupt Status
-    AT91PS_PMC pPMC) // pointer to a PMC controller
-{
-    return pPMC->PMC_SR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_GetInterruptMaskStatus
-//* \brief Return PMC Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status
-    AT91PS_PMC pPMC) // pointer to a PMC controller
-{
-    return pPMC->PMC_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_IsInterruptMasked
-//* \brief Test if PMC Interrupt is Masked
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_IsInterruptMasked(
-        AT91PS_PMC pPMC,   // \arg  pointer to a PMC controller
-        unsigned int flag) // \arg  flag to be tested
-{
-    return (AT91F_PMC_GetInterruptMaskStatus(pPMC) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_IsStatusSet
-//* \brief Test if PMC Status is Set
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_IsStatusSet(
-        AT91PS_PMC pPMC,   // \arg  pointer to a PMC controller
-        unsigned int flag) // \arg  flag to be tested
-{
-    return (AT91F_PMC_GetStatus(pPMC) & flag);
-}/* *****************************************************************************
-                SOFTWARE API FOR RSTC
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_RSTSoftReset
-//* \brief Start Software Reset
-//*----------------------------------------------------------------------------
-__inline void AT91F_RSTSoftReset(
-        AT91PS_RSTC pRSTC,
-        unsigned int reset)
-{
-    pRSTC->RSTC_RCR = (0xA5000000 | reset);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_RSTSetMode
-//* \brief Set Reset Mode
-//*----------------------------------------------------------------------------
-__inline void AT91F_RSTSetMode(
-        AT91PS_RSTC pRSTC,
-        unsigned int mode)
-{
-    pRSTC->RSTC_RMR = (0xA5000000 | mode);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_RSTGetMode
-//* \brief Get Reset Mode
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_RSTGetMode(
-        AT91PS_RSTC pRSTC)
-{
-    return (pRSTC->RSTC_RMR);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_RSTGetStatus
-//* \brief Get Reset Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_RSTGetStatus(
-        AT91PS_RSTC pRSTC)
-{
-    return (pRSTC->RSTC_RSR);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_RSTIsSoftRstActive
-//* \brief Return !=0 if software reset is still not completed
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_RSTIsSoftRstActive(
-        AT91PS_RSTC pRSTC)
-{
-    return ((pRSTC->RSTC_RSR) & AT91C_RSTC_SRCMP);
-}
-/* *****************************************************************************
-                SOFTWARE API FOR RTTC
-   ***************************************************************************** */
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_SetRTT_TimeBase()
-//* \brief  Set the RTT prescaler according to the TimeBase in ms
-//*--------------------------------------------------------------------------------------
-__inline unsigned int AT91F_RTTSetTimeBase(
-        AT91PS_RTTC pRTTC,
-        unsigned int ms)
-{
-    if (ms > 2000)
-        return 1;   // AT91C_TIME_OUT_OF_RANGE
-    pRTTC->RTTC_RTMR &= ~0xFFFF;
-    pRTTC->RTTC_RTMR |= (((ms << 15) /1000) & 0xFFFF);
-    return 0;
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_RTTSetPrescaler()
-//* \brief  Set the new prescaler value
-//*--------------------------------------------------------------------------------------
-__inline unsigned int AT91F_RTTSetPrescaler(
-        AT91PS_RTTC pRTTC,
-        unsigned int rtpres)
-{
-    pRTTC->RTTC_RTMR &= ~0xFFFF;
-    pRTTC->RTTC_RTMR |= (rtpres & 0xFFFF);
-    return (pRTTC->RTTC_RTMR);
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_RTTRestart()
-//* \brief  Restart the RTT prescaler
-//*--------------------------------------------------------------------------------------
-__inline void AT91F_RTTRestart(
-        AT91PS_RTTC pRTTC)
-{
-    pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTRST;
-}
-
-
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_RTT_SetAlarmINT()
-//* \brief  Enable RTT Alarm Interrupt
-//*--------------------------------------------------------------------------------------
-__inline void AT91F_RTTSetAlarmINT(
-        AT91PS_RTTC pRTTC)
-{
-    pRTTC->RTTC_RTMR |= AT91C_RTTC_ALMIEN;
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_RTT_ClearAlarmINT()
-//* \brief  Disable RTT Alarm Interrupt
-//*--------------------------------------------------------------------------------------
-__inline void AT91F_RTTClearAlarmINT(
-        AT91PS_RTTC pRTTC)
-{
-    pRTTC->RTTC_RTMR &= ~AT91C_RTTC_ALMIEN;
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_RTT_SetRttIncINT()
-//* \brief  Enable RTT INC Interrupt
-//*--------------------------------------------------------------------------------------
-__inline void AT91F_RTTSetRttIncINT(
-        AT91PS_RTTC pRTTC)
-{
-    pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTINCIEN;
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_RTT_ClearRttIncINT()
-//* \brief  Disable RTT INC Interrupt
-//*--------------------------------------------------------------------------------------
-__inline void AT91F_RTTClearRttIncINT(
-        AT91PS_RTTC pRTTC)
-{
-    pRTTC->RTTC_RTMR &= ~AT91C_RTTC_RTTINCIEN;
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_RTT_SetAlarmValue()
-//* \brief  Set RTT Alarm Value
-//*--------------------------------------------------------------------------------------
-__inline void AT91F_RTTSetAlarmValue(
-        AT91PS_RTTC pRTTC, unsigned int alarm)
-{
-    pRTTC->RTTC_RTAR = alarm;
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_RTT_GetAlarmValue()
-//* \brief  Get RTT Alarm Value
-//*--------------------------------------------------------------------------------------
-__inline unsigned int AT91F_RTTGetAlarmValue(
-        AT91PS_RTTC pRTTC)
-{
-    return(pRTTC->RTTC_RTAR);
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_RTTGetStatus()
-//* \brief  Read the RTT status
-//*--------------------------------------------------------------------------------------
-__inline unsigned int AT91F_RTTGetStatus(
-        AT91PS_RTTC pRTTC)
-{
-    return(pRTTC->RTTC_RTSR);
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_RTT_ReadValue()
-//* \brief  Read the RTT value
-//*--------------------------------------------------------------------------------------
-__inline unsigned int AT91F_RTTReadValue(
-        AT91PS_RTTC pRTTC)
-{
-        register volatile unsigned int val1,val2;
-    do
+*               SOFTWARE API FOR AIC
+***************************************************************************** */
+    #define AT91C_AIC_BRANCH_OPCODE    ( ( void ( * )() ) 0xE51FFF20 ) /* ldr, pc, [pc, #-&F20] */
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_AIC_ConfigureIt */
+/** \brief Interrupt Handler Initialization */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_AIC_ConfigureIt( AT91PS_AIC pAic,                /* \arg pointer to the AIC registers */
+                                                 unsigned int irq_id,            /* \arg interrupt number to initialize */
+                                                 unsigned int priority,          /* \arg priority to give to the interrupt */
+                                                 unsigned int src_type,          /* \arg activation and sense of activation */
+                                                 void ( * newHandler )( void ) ) /* \arg address of the interrupt handler */
     {
-        val1 = pRTTC->RTTC_RTVR;
-        val2 = pRTTC->RTTC_RTVR;
+        unsigned int oldHandler;
+        unsigned int mask;
+
+        oldHandler = pAic->AIC_SVR[ irq_id ];
+
+        mask = 0x1 << irq_id;
+        /** Disable the interrupt on the interrupt controller */
+        pAic->AIC_IDCR = mask;
+        /** Save the interrupt handler routine pointer and the interrupt priority */
+        pAic->AIC_SVR[ irq_id ] = ( unsigned int ) newHandler;
+        /** Store the Source Mode Register */
+        pAic->AIC_SMR[ irq_id ] = src_type | priority;
+        /** Clear the interrupt on the interrupt controller */
+        pAic->AIC_ICCR = mask;
+
+        return oldHandler;
     }
-    while(val1 != val2);
-    return(val1);
-}
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_AIC_EnableIt */
+/** \brief Enable corresponding IT number */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_AIC_EnableIt( AT91PS_AIC pAic,      /* \arg pointer to the AIC registers */
+                                      unsigned int irq_id ) /* \arg interrupt number to initialize */
+    {
+        /** Enable the interrupt on the interrupt controller */
+        pAic->AIC_IECR = 0x1 << irq_id;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_AIC_DisableIt */
+/** \brief Disable corresponding IT number */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_AIC_DisableIt( AT91PS_AIC pAic,      /* \arg pointer to the AIC registers */
+                                       unsigned int irq_id ) /* \arg interrupt number to initialize */
+    {
+        unsigned int mask = 0x1 << irq_id;
+
+        /** Disable the interrupt on the interrupt controller */
+        pAic->AIC_IDCR = mask;
+        /** Clear the interrupt on the Interrupt Controller ( if one is pending ) */
+        pAic->AIC_ICCR = mask;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_AIC_ClearIt */
+/** \brief Clear corresponding IT number */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_AIC_ClearIt( AT91PS_AIC pAic,      /* \arg pointer to the AIC registers */
+                                     unsigned int irq_id ) /* \arg interrupt number to initialize */
+    {
+        /** Clear the interrupt on the Interrupt Controller ( if one is pending ) */
+        pAic->AIC_ICCR = ( 0x1 << irq_id );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_AIC_AcknowledgeIt */
+/** \brief Acknowledge corresponding IT number */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_AIC_AcknowledgeIt( AT91PS_AIC pAic ) /* \arg pointer to the AIC registers */
+    {
+        pAic->AIC_EOICR = pAic->AIC_EOICR;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_AIC_SetExceptionVector */
+/** \brief Configure vector handler */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_AIC_SetExceptionVector( unsigned int * pVector, /* \arg pointer to the AIC registers */
+                                                        void ( * Handler )() )  /* \arg Interrupt Handler */
+    {
+        unsigned int oldVector = *pVector;
+
+        if( ( unsigned int ) Handler == ( unsigned int ) AT91C_AIC_BRANCH_OPCODE )
+        {
+            *pVector = ( unsigned int ) AT91C_AIC_BRANCH_OPCODE;
+        }
+        else
+        {
+            *pVector = ( ( ( ( ( unsigned int ) Handler ) - ( ( unsigned int ) pVector ) - 0x8 ) >> 2 ) & 0x00FFFFFF ) | 0xEA000000;
+        }
+
+        return oldVector;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_AIC_Trig */
+/** \brief Trig an IT */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_AIC_Trig( AT91PS_AIC pAic,      /* \arg pointer to the AIC registers */
+                                  unsigned int irq_id ) /* \arg interrupt number */
+    {
+        pAic->AIC_ISCR = ( 0x1 << irq_id );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_AIC_IsActive */
+/** \brief Test if an IT is active */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_AIC_IsActive( AT91PS_AIC pAic,      /* \arg pointer to the AIC registers */
+                                              unsigned int irq_id ) /* \arg Interrupt Number */
+    {
+        return( pAic->AIC_ISR & ( 0x1 << irq_id ) );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_AIC_IsPending */
+/** \brief Test if an IT is pending */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_AIC_IsPending( AT91PS_AIC pAic,      /* \arg pointer to the AIC registers */
+                                               unsigned int irq_id ) /* \arg Interrupt Number */
+    {
+        return( pAic->AIC_IPR & ( 0x1 << irq_id ) );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_AIC_Open */
+/** \brief Set exception vectors and AIC registers to default values */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_AIC_Open( AT91PS_AIC pAic,              /* \arg pointer to the AIC registers */
+                                  void ( * IrqHandler )(),      /* \arg Default IRQ vector exception */
+                                  void ( * FiqHandler )(),      /* \arg Default FIQ vector exception */
+                                  void ( * DefaultHandler )(),  /* \arg Default Handler set in ISR */
+                                  void ( * SpuriousHandler )(), /* \arg Default Spurious Handler */
+                                  unsigned int protectMode )    /* \arg Debug Control Register */
+    {
+        int i;
+
+        /* Disable all interrupts and set IVR to the default handler */
+        for( i = 0; i < 32; ++i )
+        {
+            AT91F_AIC_DisableIt( pAic, i );
+            AT91F_AIC_ConfigureIt( pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_HIGH_LEVEL, DefaultHandler );
+        }
+
+        /* Set the IRQ exception vector */
+        AT91F_AIC_SetExceptionVector( ( unsigned int * ) 0x18, IrqHandler );
+        /* Set the Fast Interrupt exception vector */
+        AT91F_AIC_SetExceptionVector( ( unsigned int * ) 0x1C, FiqHandler );
+
+        pAic->AIC_SPU = ( unsigned int ) SpuriousHandler;
+        pAic->AIC_DCR = protectMode;
+    }
+
 /* *****************************************************************************
-                SOFTWARE API FOR PITC
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PITInit
-//* \brief System timer init : period in
\ No newline at end of file
+*               SOFTWARE API FOR PDC
+***************************************************************************** */
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_SetNextRx */
+/** \brief Set the next receive transfer descriptor */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PDC_SetNextRx( AT91PS_PDC pPDC,     /* \arg pointer to a PDC controller */
+                                       char * address,      /* \arg address to the next bloc to be received */
+                                       unsigned int bytes ) /* \arg number of bytes to be received */
+    {
+        pPDC->PDC_RNPR = ( unsigned int ) address;
+        pPDC->PDC_RNCR = bytes;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_SetNextTx */
+/** \brief Set the next transmit transfer descriptor */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PDC_SetNextTx( AT91PS_PDC pPDC,     /* \arg pointer to a PDC controller */
+                                       char * address,      /* \arg address to the next bloc to be transmitted */
+                                       unsigned int bytes ) /* \arg number of bytes to be transmitted */
+    {
+        pPDC->PDC_TNPR = ( unsigned int ) address;
+        pPDC->PDC_TNCR = bytes;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_SetRx */
+/** \brief Set the receive transfer descriptor */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PDC_SetRx( AT91PS_PDC pPDC,     /* \arg pointer to a PDC controller */
+                                   char * address,      /* \arg address to the next bloc to be received */
+                                   unsigned int bytes ) /* \arg number of bytes to be received */
+    {
+        pPDC->PDC_RPR = ( unsigned int ) address;
+        pPDC->PDC_RCR = bytes;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_SetTx */
+/** \brief Set the transmit transfer descriptor */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PDC_SetTx( AT91PS_PDC pPDC,     /* \arg pointer to a PDC controller */
+                                   char * address,      /* \arg address to the next bloc to be transmitted */
+                                   unsigned int bytes ) /* \arg number of bytes to be transmitted */
+    {
+        pPDC->PDC_TPR = ( unsigned int ) address;
+        pPDC->PDC_TCR = bytes;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_EnableTx */
+/** \brief Enable transmit */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PDC_EnableTx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
+    {
+        pPDC->PDC_PTCR = AT91C_PDC_TXTEN;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_EnableRx */
+/** \brief Enable receive */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PDC_EnableRx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
+    {
+        pPDC->PDC_PTCR = AT91C_PDC_RXTEN;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_DisableTx */
+/** \brief Disable transmit */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PDC_DisableTx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
+    {
+        pPDC->PDC_PTCR = AT91C_PDC_TXTDIS;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_DisableRx */
+/** \brief Disable receive */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PDC_DisableRx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
+    {
+        pPDC->PDC_PTCR = AT91C_PDC_RXTDIS;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_IsTxEmpty */
+/** \brief Test if the current transfer descriptor has been sent */
+/**---------------------------------------------------------------------------- */
+    __inline int AT91F_PDC_IsTxEmpty( /* \return return 1 if transfer is complete */
+        AT91PS_PDC pPDC )             /* \arg pointer to a PDC controller */
+    {
+        return !( pPDC->PDC_TCR );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_IsNextTxEmpty */
+/** \brief Test if the next transfer descriptor has been moved to the current td */
+/**---------------------------------------------------------------------------- */
+    __inline int AT91F_PDC_IsNextTxEmpty( /* \return return 1 if transfer is complete */
+        AT91PS_PDC pPDC )                 /* \arg pointer to a PDC controller */
+    {
+        return !( pPDC->PDC_TNCR );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_IsRxEmpty */
+/** \brief Test if the current transfer descriptor has been filled */
+/**---------------------------------------------------------------------------- */
+    __inline int AT91F_PDC_IsRxEmpty( /* \return return 1 if transfer is complete */
+        AT91PS_PDC pPDC )             /* \arg pointer to a PDC controller */
+    {
+        return !( pPDC->PDC_RCR );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_IsNextRxEmpty */
+/** \brief Test if the next transfer descriptor has been moved to the current td */
+/**---------------------------------------------------------------------------- */
+    __inline int AT91F_PDC_IsNextRxEmpty( /* \return return 1 if transfer is complete */
+        AT91PS_PDC pPDC )                 /* \arg pointer to a PDC controller */
+    {
+        return !( pPDC->PDC_RNCR );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_Open */
+/** \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PDC_Open( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
+    {
+        /** Disable the RX and TX PDC transfer requests */
+        AT91F_PDC_DisableRx( pPDC );
+        AT91F_PDC_DisableTx( pPDC );
+
+        /** Reset all Counter register Next buffer first */
+        AT91F_PDC_SetNextTx( pPDC, ( char * ) 0, 0 );
+        AT91F_PDC_SetNextRx( pPDC, ( char * ) 0, 0 );
+        AT91F_PDC_SetTx( pPDC, ( char * ) 0, 0 );
+        AT91F_PDC_SetRx( pPDC, ( char * ) 0, 0 );
+
+        /** Enable the RX and TX PDC transfer requests */
+        AT91F_PDC_EnableRx( pPDC );
+        AT91F_PDC_EnableTx( pPDC );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_Close */
+/** \brief Close PDC: disable TX and RX reset transfer descriptors */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PDC_Close( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
+    {
+        /** Disable the RX and TX PDC transfer requests */
+        AT91F_PDC_DisableRx( pPDC );
+        AT91F_PDC_DisableTx( pPDC );
+
+        /** Reset all Counter register Next buffer first */
+        AT91F_PDC_SetNextTx( pPDC, ( char * ) 0, 0 );
+        AT91F_PDC_SetNextRx( pPDC, ( char * ) 0, 0 );
+        AT91F_PDC_SetTx( pPDC, ( char * ) 0, 0 );
+        AT91F_PDC_SetRx( pPDC, ( char * ) 0, 0 );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_SendFrame */
+/** \brief Close PDC: disable TX and RX reset transfer descriptors */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_PDC_SendFrame( AT91PS_PDC pPDC,
+                                               char * pBuffer,
+                                               unsigned int szBuffer,
+                                               char * pNextBuffer,
+                                               unsigned int szNextBuffer )
+    {
+        if( AT91F_PDC_IsTxEmpty( pPDC ) )
+        {
+            /** Buffer and next buffer can be initialized */
+            AT91F_PDC_SetTx( pPDC, pBuffer, szBuffer );
+            AT91F_PDC_SetNextTx( pPDC, pNextBuffer, szNextBuffer );
+            return 2;
+        }
+        else if( AT91F_PDC_IsNextTxEmpty( pPDC ) )
+        {
+            /** Only one buffer can be initialized */
+            AT91F_PDC_SetNextTx( pPDC, pBuffer, szBuffer );
+            return 1;
+        }
+        else
+        {
+            /** All buffer are in use... */
+            return 0;
+        }
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_ReceiveFrame */
+/** \brief Close PDC: disable TX and RX reset transfer descriptors */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_PDC_ReceiveFrame( AT91PS_PDC pPDC,
+                                                  char * pBuffer,
+                                                  unsigned int szBuffer,
+                                                  char * pNextBuffer,
+                                                  unsigned int szNextBuffer )
+    {
+        if( AT91F_PDC_IsRxEmpty( pPDC ) )
+        {
+            /** Buffer and next buffer can be initialized */
+            AT91F_PDC_SetRx( pPDC, pBuffer, szBuffer );
+            AT91F_PDC_SetNextRx( pPDC, pNextBuffer, szNextBuffer );
+            return 2;
+        }
+        else if( AT91F_PDC_IsNextRxEmpty( pPDC ) )
+        {
+            /** Only one buffer can be initialized */
+            AT91F_PDC_SetNextRx( pPDC, pBuffer, szBuffer );
+            return 1;
+        }
+        else
+        {
+            /** All buffer are in use... */
+            return 0;
+        }
+    }
+
+/* *****************************************************************************
+*               SOFTWARE API FOR DBGU
+***************************************************************************** */
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_DBGU_InterruptEnable */
+/** \brief Enable DBGU Interrupt */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_DBGU_InterruptEnable( AT91PS_DBGU pDbgu,  /* \arg  pointer to a DBGU controller */
+                                              unsigned int flag ) /* \arg  dbgu interrupt to be enabled */
+    {
+        pDbgu->DBGU_IER = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_DBGU_InterruptDisable */
+/** \brief Disable DBGU Interrupt */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_DBGU_InterruptDisable( AT91PS_DBGU pDbgu,  /* \arg  pointer to a DBGU controller */
+                                               unsigned int flag ) /* \arg  dbgu interrupt to be disabled */
+    {
+        pDbgu->DBGU_IDR = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_DBGU_GetInterruptMaskStatus */
+/** \brief Return DBGU Interrupt Mask Status */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( /* \return DBGU Interrupt Mask Status */
+        AT91PS_DBGU pDbgu )                                  /* \arg  pointer to a DBGU controller */
+    {
+        return pDbgu->DBGU_IMR;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_DBGU_IsInterruptMasked */
+/** \brief Test if DBGU Interrupt is Masked */
+/**---------------------------------------------------------------------------- */
+    __inline int AT91F_DBGU_IsInterruptMasked( AT91PS_DBGU pDbgu,  /* \arg  pointer to a DBGU controller */
+                                               unsigned int flag ) /* \arg  flag to be tested */
+    {
+        return( AT91F_DBGU_GetInterruptMaskStatus( pDbgu ) & flag );
+    }
+
+/* *****************************************************************************
+*               SOFTWARE API FOR PIO
+***************************************************************************** */
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_CfgPeriph */
+/** \brief Enable pins to be derived by peripheral */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_CfgPeriph( AT91PS_PIO pPio,             /* \arg pointer to a PIO controller */
+                                       unsigned int periphAEnable,  /* \arg PERIPH A to enable */
+                                       unsigned int periphBEnable ) /* \arg PERIPH B to enable */
+
+    {
+        pPio->PIO_ASR = periphAEnable;
+        pPio->PIO_BSR = periphBEnable;
+        pPio->PIO_PDR = ( periphAEnable | periphBEnable ); /* Set in Periph mode */
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_CfgOutput */
+/** \brief Enable PIO in output mode */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_CfgOutput( AT91PS_PIO pPio,         /* \arg pointer to a PIO controller */
+                                       unsigned int pioEnable ) /* \arg PIO to be enabled */
+    {
+        pPio->PIO_PER = pioEnable;                              /* Set in PIO mode */
+        pPio->PIO_OER = pioEnable;                              /* Configure in Output */
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_CfgInput */
+/** \brief Enable PIO in input mode */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_CfgInput( AT91PS_PIO pPio,           /* \arg pointer to a PIO controller */
+                                      unsigned int inputEnable ) /* \arg PIO to be enabled */
+    {
+        /* Disable output */
+        pPio->PIO_ODR = inputEnable;
+        pPio->PIO_PER = inputEnable;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_CfgOpendrain */
+/** \brief Configure PIO in open drain */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_CfgOpendrain( AT91PS_PIO pPio,              /* \arg pointer to a PIO controller */
+                                          unsigned int multiDrvEnable ) /* \arg pio to be configured in open drain */
+    {
+        /* Configure the multi-drive option */
+        pPio->PIO_MDDR = ~multiDrvEnable;
+        pPio->PIO_MDER = multiDrvEnable;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_CfgPullup */
+/** \brief Enable pullup on PIO */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_CfgPullup( AT91PS_PIO pPio,            /* \arg pointer to a PIO controller */
+                                       unsigned int pullupEnable ) /* \arg enable pullup on PIO */
+    {
+        /* Connect or not Pullup */
+        pPio->PIO_PPUDR = ~pullupEnable;
+        pPio->PIO_PPUER = pullupEnable;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_CfgDirectDrive */
+/** \brief Enable direct drive on PIO */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_CfgDirectDrive( AT91PS_PIO pPio,           /* \arg pointer to a PIO controller */
+                                            unsigned int directDrive ) /* \arg PIO to be configured with direct drive */
+
+    {
+        /* Configure the Direct Drive */
+        pPio->PIO_OWDR = ~directDrive;
+        pPio->PIO_OWER = directDrive;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_CfgInputFilter */
+/** \brief Enable input filter on input PIO */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_CfgInputFilter( AT91PS_PIO pPio,           /* \arg pointer to a PIO controller */
+                                            unsigned int inputFilter ) /* \arg PIO to be configured with input filter */
+
+    {
+        /* Configure the Direct Drive */
+        pPio->PIO_IFDR = ~inputFilter;
+        pPio->PIO_IFER = inputFilter;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_GetInput */
+/** \brief Return PIO input value */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_PIO_GetInput( /* \return PIO input */
+        AT91PS_PIO pPio )                     /* \arg  pointer to a PIO controller */
+    {
+        return pPio->PIO_PDSR;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_IsInputSet */
+/** \brief Test if PIO is input flag is active */
+/**---------------------------------------------------------------------------- */
+    __inline int AT91F_PIO_IsInputSet( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                       unsigned int flag ) /* \arg  flag to be tested */
+    {
+        return( AT91F_PIO_GetInput( pPio ) & flag );
+    }
+
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_SetOutput */
+/** \brief Set to 1 output PIO */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_SetOutput( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                       unsigned int flag ) /* \arg  output to be set */
+    {
+        pPio->PIO_SODR = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_ClearOutput */
+/** \brief Set to 0 output PIO */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_ClearOutput( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                         unsigned int flag ) /* \arg  output to be cleared */
+    {
+        pPio->PIO_CODR = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_ForceOutput */
+/** \brief Force output when Direct drive option is enabled */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_ForceOutput( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                         unsigned int flag ) /* \arg  output to be forced */
+    {
+        pPio->PIO_ODSR = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_Enable */
+/** \brief Enable PIO */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_Enable( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                    unsigned int flag ) /* \arg  pio to be enabled */
+    {
+        pPio->PIO_PER = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_Disable */
+/** \brief Disable PIO */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_Disable( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                     unsigned int flag ) /* \arg  pio to be disabled */
+    {
+        pPio->PIO_PDR = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_GetStatus */
+/** \brief Return PIO Status */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_PIO_GetStatus( /* \return PIO Status */
+        AT91PS_PIO pPio )                      /* \arg  pointer to a PIO controller */
+    {
+        return pPio->PIO_PSR;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_IsSet */
+/** \brief Test if PIO is Set */
+/**---------------------------------------------------------------------------- */
+    __inline int AT91F_PIO_IsSet( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                  unsigned int flag ) /* \arg  flag to be tested */
+    {
+        return( AT91F_PIO_GetStatus( pPio ) & flag );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_OutputEnable */
+/** \brief Output Enable PIO */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_OutputEnable( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                          unsigned int flag ) /* \arg  pio output to be enabled */
+    {
+        pPio->PIO_OER = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_OutputDisable */
+/** \brief Output Enable PIO */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_OutputDisable( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                           unsigned int flag ) /* \arg  pio output to be disabled */
+    {
+        pPio->PIO_ODR = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_GetOutputStatus */
+/** \brief Return PIO Output Status */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_PIO_GetOutputStatus( /* \return PIO Output Status */
+        AT91PS_PIO pPio )                            /* \arg  pointer to a PIO controller */
+    {
+        return pPio->PIO_OSR;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_IsOuputSet */
+/** \brief Test if PIO Output is Set */
+/**---------------------------------------------------------------------------- */
+    __inline int AT91F_PIO_IsOutputSet( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                        unsigned int flag ) /* \arg  flag to be tested */
+    {
+        return( AT91F_PIO_GetOutputStatus( pPio ) & flag );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_InputFilterEnable */
+/** \brief Input Filter Enable PIO */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_InputFilterEnable( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                               unsigned int flag ) /* \arg  pio input filter to be enabled */
+    {
+        pPio->PIO_IFER = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_InputFilterDisable */
+/** \brief Input Filter Disable PIO */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_InputFilterDisable( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                                unsigned int flag ) /* \arg  pio input filter to be disabled */
+    {
+        pPio->PIO_IFDR = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_GetInputFilterStatus */
+/** \brief Return PIO Input Filter Status */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_PIO_GetInputFilterStatus( /* \return PIO Input Filter Status */
+        AT91PS_PIO pPio )                                 /* \arg  pointer to a PIO controller */
+    {
+        return pPio->PIO_IFSR;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_IsInputFilterSet */
+/** \brief Test if PIO Input filter is Set */
+/**---------------------------------------------------------------------------- */
+    __inline int AT91F_PIO_IsInputFilterSet( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                             unsigned int flag ) /* \arg  flag to be tested */
+    {
+        return( AT91F_PIO_GetInputFilterStatus( pPio ) & flag );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_GetOutputDataStatus */
+/** \brief Return PIO Output Data Status */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_PIO_GetOutputDataStatus( /* \return PIO Output Data Status */
+        AT91PS_PIO pPio )                                /* \arg  pointer to a PIO controller */
+    {
+        return pPio->PIO_ODSR;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_InterruptEnable */
+/** \brief Enable PIO Interrupt */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_InterruptEnable( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                             unsigned int flag ) /* \arg  pio interrupt to be enabled */
+    {
+        pPio->PIO_IER = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_InterruptDisable */
+/** \brief Disable PIO Interrupt */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_InterruptDisable( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                              unsigned int flag ) /* \arg  pio interrupt to be disabled */
+    {
+        pPio->PIO_IDR = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_GetInterruptMaskStatus */
+/** \brief Return PIO Interrupt Mask Status */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_PIO_GetInterruptMaskStatus( /* \return PIO Interrupt Mask Status */
+        AT91PS_PIO pPio )                                   /* \arg  pointer to a PIO controller */
+    {
+        return pPio->PIO_IMR;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_GetInterruptStatus */
+/** \brief Return PIO Interrupt Status */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_PIO_GetInterruptStatus( /* \return PIO Interrupt Status */
+        AT91PS_PIO pPio )                               /* \arg  pointer to a PIO controller */
+    {
+        return pPio->PIO_ISR;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_IsInterruptMasked */
+/** \brief Test if PIO Interrupt is Masked */
+/**---------------------------------------------------------------------------- */
+    __inline int AT91F_PIO_IsInterruptMasked( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                              unsigned int flag ) /* \arg  flag to be tested */
+    {
+        return( AT91F_PIO_GetInterruptMaskStatus( pPio ) & flag );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_IsInterruptSet */
+/** \brief Test if PIO Interrupt is Set */
+/**---------------------------------------------------------------------------- */
+    __inline int AT91F_PIO_IsInterruptSet( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                           unsigned int flag ) /* \arg  flag to be tested */
+    {
+        return( AT91F_PIO_GetInterruptStatus( pPio ) & flag );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_MultiDriverEnable */
+/** \brief Multi Driver Enable PIO */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_MultiDriverEnable( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                               unsigned int flag ) /* \arg  pio to be enabled */
+    {
+        pPio->PIO_MDER = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_MultiDriverDisable */
+/** \brief Multi Driver Disable PIO */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_MultiDriverDisable( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                                unsigned int flag ) /* \arg  pio to be disabled */
+    {
+        pPio->PIO_MDDR = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_GetMultiDriverStatus */
+/** \brief Return PIO Multi Driver Status */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_PIO_GetMultiDriverStatus( /* \return PIO Multi Driver Status */
+        AT91PS_PIO pPio )                                 /* \arg  pointer to a PIO controller */
+    {
+        return pPio->PIO_MDSR;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_IsMultiDriverSet */
+/** \brief Test if PIO MultiDriver is Set */
+/**---------------------------------------------------------------------------- */
+    __inline int AT91F_PIO_IsMultiDriverSet( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                             unsigned int flag ) /* \arg  flag to be tested */
+    {
+        return( AT91F_PIO_GetMultiDriverStatus( pPio ) & flag );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_A_RegisterSelection */
+/** \brief PIO A Register Selection */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_A_RegisterSelection( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                                 unsigned int flag ) /* \arg  pio A register selection */
+    {
+        pPio->PIO_ASR = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_B_RegisterSelection */
+/** \brief PIO B Register Selection */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_B_RegisterSelection( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                                 unsigned int flag ) /* \arg  pio B register selection */
+    {
+        pPio->PIO_BSR = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_Get_AB_RegisterStatus */
+/** \brief Return PIO Interrupt Status */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( /* \return PIO AB Register Status */
+        AT91PS_PIO pPio )                                  /* \arg  pointer to a PIO controller */
+    {
+        return pPio->PIO_ABSR;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_IsAB_RegisterSet */
+/** \brief Test if PIO AB Register is Set */
+/**---------------------------------------------------------------------------- */
+    __inline int AT91F_PIO_IsAB_RegisterSet( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                             unsigned int flag ) /* \arg  flag to be tested */
+    {
+        return( AT91F_PIO_Get_AB_RegisterStatus( pPio ) & flag );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_OutputWriteEnable */
+/** \brief Output Write Enable PIO */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_OutputWriteEnable( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                               unsigned int flag ) /* \arg  pio output write to be enabled */
+    {
+        pPio->PIO_OWER = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_OutputWriteDisable */
+/** \brief Output Write Disable PIO */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_OutputWriteDisable( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                                unsigned int flag ) /* \arg  pio output write to be disabled */
+    {
+        pPio->PIO_OWDR = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_GetOutputWriteStatus */
+/** \brief Return PIO Output Write Status */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_PIO_GetOutputWriteStatus( /* \return PIO Output Write Status */
+        AT91PS_PIO pPio )                                 /* \arg  pointer to a PIO controller */
+    {
+        return pPio->PIO_OWSR;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_IsOutputWriteSet */
+/** \brief Test if PIO OutputWrite is Set */
+/**---------------------------------------------------------------------------- */
+    __inline int AT91F_PIO_IsOutputWriteSet( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                             unsigned int flag ) /* \arg  flag to be tested */
+    {
+        return( AT91F_PIO_GetOutputWriteStatus( pPio ) & flag );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_GetCfgPullup */
+/** \brief Return PIO Configuration Pullup */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_PIO_GetCfgPullup( /* \return PIO Configuration Pullup */
+        AT91PS_PIO pPio )                         /* \arg  pointer to a PIO controller */
+    {
+        return pPio->PIO_PPUSR;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_IsOutputDataStatusSet */
+/** \brief Test if PIO Output Data Status is Set */
+/**---------------------------------------------------------------------------- */
+    __inline int AT91F_PIO_IsOutputDataStatusSet( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                                  unsigned int flag ) /* \arg  flag to be tested */
+    {
+        return( AT91F_PIO_GetOutputDataStatus( pPio ) & flag );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_IsCfgPullupStatusSet */
+/** \brief Test if PIO Configuration Pullup Status is Set */
+/**---------------------------------------------------------------------------- */
+    __inline int AT91F_PIO_IsCfgPullupStatusSet( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                                 unsigned int flag ) /* \arg  flag to be tested */
+    {
+        return( ~AT91F_PIO_GetCfgPullup( pPio ) & flag );
+    }
+
+/* *****************************************************************************
+*               SOFTWARE API FOR PMC
+***************************************************************************** */
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_CfgSysClkEnableReg */
+/** \brief Configure the System Clock Enable Register of the PMC controller */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PMC_CfgSysClkEnableReg( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */
+                                                unsigned int mode )
+    {
+        /** Write to the SCER register */
+        pPMC->PMC_SCER = mode;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_CfgSysClkDisableReg */
+/** \brief Configure the System Clock Disable Register of the PMC controller */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PMC_CfgSysClkDisableReg( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */
+                                                 unsigned int mode )
+    {
+        /** Write to the SCDR register */
+        pPMC->PMC_SCDR = mode;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_GetSysClkStatusReg */
+/** \brief Return the System Clock Status Register of the PMC controller */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_PMC_GetSysClkStatusReg( AT91PS_PMC pPMC /* pointer to a CAN controller */
+                                                        )
+    {
+        return pPMC->PMC_SCSR;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_EnablePeriphClock */
+/** \brief Enable peripheral clock */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PMC_EnablePeriphClock( AT91PS_PMC pPMC,         /* \arg pointer to PMC controller */
+                                               unsigned int periphIds ) /* \arg IDs of peripherals to enable */
+    {
+        pPMC->PMC_PCER = periphIds;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_DisablePeriphClock */
+/** \brief Disable peripheral clock */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PMC_DisablePeriphClock( AT91PS_PMC pPMC,         /* \arg pointer to PMC controller */
+                                                unsigned int periphIds ) /* \arg IDs of peripherals to enable */
+    {
+        pPMC->PMC_PCDR = periphIds;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_GetPeriphClock */
+/** \brief Get peripheral clock status */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_PMC_GetPeriphClock( AT91PS_PMC pPMC ) /* \arg pointer to PMC controller */
+    {
+        return pPMC->PMC_PCSR;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_CKGR_CfgMainOscillatorReg */
+/** \brief Cfg the main oscillator */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_CKGR_CfgMainOscillatorReg( AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */
+                                                   unsigned int mode )
+    {
+        pCKGR->CKGR_MOR = mode;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_CKGR_GetMainOscillatorReg */
+/** \brief Cfg the main oscillator */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_CKGR_GetMainOscillatorReg( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */
+    {
+        return pCKGR->CKGR_MOR;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_CKGR_EnableMainOscillator */
+/** \brief Enable the main oscillator */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_CKGR_EnableMainOscillator( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */
+    {
+        pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_CKGR_DisableMainOscillator */
+/** \brief Disable the main oscillator */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_CKGR_DisableMainOscillator( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */
+    {
+        pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_CKGR_CfgMainOscStartUpTime */
+/** \brief Cfg MOR Register according to the main osc startup time */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_CKGR_CfgMainOscStartUpTime( AT91PS_CKGR pCKGR,         /* \arg pointer to CKGR controller */
+                                                    unsigned int startup_time, /* \arg main osc startup time in microsecond (us) */
+                                                    unsigned int slowClock )   /* \arg slowClock in Hz */
+    {
+        pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT;
+        pCKGR->CKGR_MOR |= ( ( slowClock * startup_time ) / ( 8 * 1000000 ) ) << 8;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_CKGR_GetMainClockFreqReg */
+/** \brief Cfg the main oscillator */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_CKGR_GetMainClockFreqReg( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */
+    {
+        return pCKGR->CKGR_MCFR;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_CKGR_GetMainClock */
+/** \brief Return Main clock in Hz */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_CKGR_GetMainClock( AT91PS_CKGR pCKGR,       /* \arg pointer to CKGR controller */
+                                                   unsigned int slowClock ) /* \arg slowClock in Hz */
+    {
+        return ( ( pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF ) * slowClock ) >> 4;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_CfgMCKReg */
+/** \brief Cfg Master Clock Register */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PMC_CfgMCKReg( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */
+                                       unsigned int mode )
+    {
+        pPMC->PMC_MCKR = mode;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_GetMCKReg */
+/** \brief Return Master Clock Register */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_PMC_GetMCKReg( AT91PS_PMC pPMC ) /* \arg pointer to PMC controller */
+    {
+        return pPMC->PMC_MCKR;
+    }
+
+/**------------------------------------------------------------------------------ */
+/** \fn    AT91F_PMC_GetMasterClock */
+/** \brief Return master clock in Hz which corresponds to processor clock for ARM7 */
+/**------------------------------------------------------------------------------ */
+    __inline unsigned int AT91F_PMC_GetMasterClock( AT91PS_PMC pPMC,         /* \arg pointer to PMC controller */
+                                                    AT91PS_CKGR pCKGR,       /* \arg pointer to CKGR controller */
+                                                    unsigned int slowClock ) /* \arg slowClock in Hz */
+    {
+        unsigned int reg = pPMC->PMC_MCKR;
+        unsigned int prescaler = ( 1 << ( ( reg & AT91C_PMC_PRES ) >> 2 ) );
+        unsigned int pllDivider, pllMultiplier;
+
+        switch( reg & AT91C_PMC_CSS )
+        {
+            case AT91C_PMC_CSS_SLOW_CLK: /* Slow clock selected */
+                return slowClock / prescaler;
+
+            case AT91C_PMC_CSS_MAIN_CLK: /* Main clock is selected */
+                return AT91F_CKGR_GetMainClock( pCKGR, slowClock ) / prescaler;
+
+            case AT91C_PMC_CSS_PLL_CLK: /* PLLB clock is selected */
+                reg = pCKGR->CKGR_PLLR;
+                pllDivider = ( reg & AT91C_CKGR_DIV );
+                pllMultiplier = ( ( reg & AT91C_CKGR_MUL ) >> 16 ) + 1;
+                return AT91F_CKGR_GetMainClock( pCKGR, slowClock ) / pllDivider * pllMultiplier / prescaler;
+        }
+
+        return 0;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_EnablePCK */
+/** \brief Enable peripheral clock */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PMC_EnablePCK( AT91PS_PMC pPMC,  /* \arg pointer to PMC controller */
+                                       unsigned int pck, /* \arg Peripheral clock identifier 0 .. 7 */
+                                       unsigned int mode )
+    {
+        pPMC->PMC_PCKR[ pck ] = mode;
+        pPMC->PMC_SCER = ( 1 << pck ) << 8;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_DisablePCK */
+/** \brief Enable peripheral clock */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PMC_DisablePCK( AT91PS_PMC pPMC,   /* \arg pointer to PMC controller */
+                                        unsigned int pck ) /* \arg Peripheral clock identifier 0 .. 7 */
+    {
+        pPMC->PMC_SCDR = ( 1 << pck ) << 8;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_EnableIt */
+/** \brief Enable PMC interrupt */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PMC_EnableIt( AT91PS_PMC pPMC,    /* pointer to a PMC controller */
+                                      unsigned int flag ) /* IT to be enabled */
+    {
+        /** Write to the IER register */
+        pPMC->PMC_IER = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_DisableIt */
+/** \brief Disable PMC interrupt */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PMC_DisableIt( AT91PS_PMC pPMC,    /* pointer to a PMC controller */
+                                       unsigned int flag ) /* IT to be disabled */
+    {
+        /** Write to the IDR register */
+        pPMC->PMC_IDR = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_GetStatus */
+/** \brief Return PMC Interrupt Status */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_PMC_GetStatus( /* \return PMC Interrupt Status */
+        AT91PS_PMC pPMC )                      /* pointer to a PMC controller */
+    {
+        return pPMC->PMC_SR;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_GetInterruptMaskStatus */
+/** \brief Return PMC Interrupt Mask Status */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_PMC_GetInterruptMaskStatus( /* \return PMC Interrupt Mask Status */
+        AT91PS_PMC pPMC )                                   /* pointer to a PMC controller */
+    {
+        return pPMC->PMC_IMR;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_IsInterruptMasked */
+/** \brief Test if PMC Interrupt is Masked */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_PMC_IsInterruptMasked( AT91PS_PMC pPMC,    /* \arg  pointer to a PMC controller */
+                                                       unsigned int flag ) /* \arg  flag to be tested */
+    {
+        return( AT91F_PMC_GetInterruptMaskStatus( pPMC ) & flag );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_IsStatusSet */
+/** \brief Test if PMC Status is Set */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_PMC_IsStatusSet( AT91PS_PMC pPMC,    /* \arg  pointer to a PMC controller */
+                                                 unsigned int flag ) /* \arg  flag to be tested */
+    {
+        return( AT91F_PMC_GetStatus( pPMC ) & flag );
+    } /* *****************************************************************************
+      *              SOFTWARE API FOR RSTC
+      ***************************************************************************** */
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_RSTSoftReset */
+/** \brief Start Software Reset */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_RSTSoftReset( AT91PS_RSTC pRSTC,
+                                      unsigned int reset )
+    {
+        pRSTC->RSTC_RCR = ( 0xA5000000 | reset );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_RSTSetMode */
+/** \brief Set Reset Mode */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_RSTSetMode( AT91PS_RSTC pRSTC,
+                                    unsigned int mode )
+    {
+        pRSTC->RSTC_RMR = ( 0xA5000000 | mode );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_RSTGetMode */
+/** \brief Get Reset Mode */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_RSTGetMode( AT91PS_RSTC pRSTC )
+    {
+        return( pRSTC->RSTC_RMR );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_RSTGetStatus */
+/** \brief Get Reset Status */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_RSTGetStatus( AT91PS_RSTC pRSTC )
+    {
+        return( pRSTC->RSTC_RSR );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_RSTIsSoftRstActive */
+/** \brief Return !=0 if software reset is still not completed */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_RSTIsSoftRstActive( AT91PS_RSTC pRSTC )
+    {
+        return( ( pRSTC->RSTC_RSR ) & AT91C_RSTC_SRCMP );
+    }
+
+/* *****************************************************************************
+*               SOFTWARE API FOR RTTC
+***************************************************************************** */
+/**-------------------------------------------------------------------------------------- */
+/** \fn     AT91F_SetRTT_TimeBase() */
+/** \brief  Set the RTT prescaler according to the TimeBase in ms */
+/**-------------------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_RTTSetTimeBase( AT91PS_RTTC pRTTC,
+                                                unsigned int ms )
+    {
+        if( ms > 2000 )
+        {
+            return 1; /* AT91C_TIME_OUT_OF_RANGE */
+        }
+
+        pRTTC->RTTC_RTMR &= ~0xFFFF;
+        pRTTC->RTTC_RTMR |= ( ( ( ms << 15 ) / 1000 ) & 0xFFFF );
+        return 0;
+    }
+
+/**-------------------------------------------------------------------------------------- */
+/** \fn     AT91F_RTTSetPrescaler() */
+/** \brief  Set the new prescaler value */
+/**-------------------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_RTTSetPrescaler( AT91PS_RTTC pRTTC,
+                                                 unsigned int rtpres )
+    {
+        pRTTC->RTTC_RTMR &= ~0xFFFF;
+        pRTTC->RTTC_RTMR |= ( rtpres & 0xFFFF );
+        return( pRTTC->RTTC_RTMR );
+    }
+
+/**-------------------------------------------------------------------------------------- */
+/** \fn     AT91F_RTTRestart() */
+/** \brief  Restart the RTT prescaler */
+/**-------------------------------------------------------------------------------------- */
+    __inline void AT91F_RTTRestart( AT91PS_RTTC pRTTC )
+    {
+        pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTRST;
+    }
+
+
+/**-------------------------------------------------------------------------------------- */
+/** \fn     AT91F_RTT_SetAlarmINT() */
+/** \brief  Enable RTT Alarm Interrupt */
+/**-------------------------------------------------------------------------------------- */
+    __inline void AT91F_RTTSetAlarmINT( AT91PS_RTTC pRTTC )
+    {
+        pRTTC->RTTC_RTMR |= AT91C_RTTC_ALMIEN;
+    }
+
+/**-------------------------------------------------------------------------------------- */
+/** \fn     AT91F_RTT_ClearAlarmINT() */
+/** \brief  Disable RTT Alarm Interrupt */
+/**-------------------------------------------------------------------------------------- */
+    __inline void AT91F_RTTClearAlarmINT( AT91PS_RTTC pRTTC )
+    {
+        pRTTC->RTTC_RTMR &= ~AT91C_RTTC_ALMIEN;
+    }
+
+/**-------------------------------------------------------------------------------------- */
+/** \fn     AT91F_RTT_SetRttIncINT() */
+/** \brief  Enable RTT INC Interrupt */
+/**-------------------------------------------------------------------------------------- */
+    __inline void AT91F_RTTSetRttIncINT( AT91PS_RTTC pRTTC )
+    {
+        pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTINCIEN;
+    }
+
+/**-------------------------------------------------------------------------------------- */
+/** \fn     AT91F_RTT_ClearRttIncINT() */
+/** \brief  Disable RTT INC Interrupt */
+/**-------------------------------------------------------------------------------------- */
+    __inline void AT91F_RTTClearRttIncINT( AT91PS_RTTC pRTTC )
+    {
+        pRTTC->RTTC_RTMR &= ~AT91C_RTTC_RTTINCIEN;
+    }
+
+/**-------------------------------------------------------------------------------------- */
+/** \fn     AT91F_RTT_SetAlarmValue() */
+/** \brief  Set RTT Alarm Value */
+/**-------------------------------------------------------------------------------------- */
+    __inline void AT91F_RTTSetAlarmValue( AT91PS_RTTC pRTTC,
+                                          unsigned int alarm )
+    {
+        pRTTC->RTTC_RTAR = alarm;
+    }
+
+/**-------------------------------------------------------------------------------------- */
+/** \fn     AT91F_RTT_GetAlarmValue() */
+/** \brief  Get RTT Alarm Value */
+/**-------------------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_RTTGetAlarmValue( AT91PS_RTTC pRTTC )
+    {
+        return( pRTTC->RTTC_RTAR );
+    }
+
+/**-------------------------------------------------------------------------------------- */
+/** \fn     AT91F_RTTGetStatus() */
+/** \brief  Read the RTT status */
+/**-------------------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_RTTGetStatus( AT91PS_RTTC pRTTC )
+    {
+        return( pRTTC->RTTC_RTSR );
+    }
+
+/**-------------------------------------------------------------------------------------- */
+/** \fn     AT91F_RTT_ReadValue() */
+/** \brief  Read the RTT value */
+/**-------------------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_RTTReadValue( AT91PS_RTTC pRTTC )
+    {
+        register volatile unsigned int val1, val2;
+
+        do
+        {
+            val1 = pRTTC->RTTC_RTVR;
+            val2 = pRTTC->RTTC_RTVR;
+        }
+        while( val1 != val2 );
+
+        return( val1 );
+    }
+
+/* *****************************************************************************
+*               SOFTWARE API FOR PITC
+***************************************************************************** */
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PITInit */
+/** \brief System timer init : period in */
diff --git a/portable/GCC/ARM7_AT91SAM7S/port.c b/portable/GCC/ARM7_AT91SAM7S/port.c
index a9d78bb13..f1afce707 100644
--- a/portable/GCC/ARM7_AT91SAM7S/port.c
+++ b/portable/GCC/ARM7_AT91SAM7S/port.c
@@ -28,12 +28,12 @@
 
 
 /*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the ARM7 port.
- *
- * Components that can be compiled to either ARM or THUMB mode are
- * contained in this file.  The ISR routines, which can only be compiled
- * to ARM mode are contained in portISR.c.
- *----------------------------------------------------------*/
+* Implementation of functions defined in portable.h for the ARM7 port.
+*
+* Components that can be compiled to either ARM or THUMB mode are
+* contained in this file.  The ISR routines, which can only be compiled
+* to ARM mode are contained in portISR.c.
+*----------------------------------------------------------*/
 
 /* Standard includes. */
 #include <stdlib.h>
@@ -46,24 +46,24 @@
 #include "AT91SAM7X256.h"
 
 /* Constants required to setup the task context. */
-#define portINITIAL_SPSR                ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
-#define portTHUMB_MODE_BIT              ( ( StackType_t ) 0x20 )
-#define portINSTRUCTION_SIZE            ( ( StackType_t ) 4 )
-#define portNO_CRITICAL_SECTION_NESTING ( ( StackType_t ) 0 )
+#define portINITIAL_SPSR                   ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT                 ( ( StackType_t ) 0x20 )
+#define portINSTRUCTION_SIZE               ( ( StackType_t ) 4 )
+#define portNO_CRITICAL_SECTION_NESTING    ( ( StackType_t ) 0 )
 
 /* Constants required to setup the tick ISR. */
-#define portENABLE_TIMER            ( ( uint8_t ) 0x01 )
-#define portPRESCALE_VALUE          0x00
-#define portINTERRUPT_ON_MATCH      ( ( uint32_t ) 0x01 )
-#define portRESET_COUNT_ON_MATCH    ( ( uint32_t ) 0x02 )
+#define portENABLE_TIMER                   ( ( uint8_t ) 0x01 )
+#define portPRESCALE_VALUE                 0x00
+#define portINTERRUPT_ON_MATCH             ( ( uint32_t ) 0x01 )
+#define portRESET_COUNT_ON_MATCH           ( ( uint32_t ) 0x02 )
 
 /* Constants required to setup the PIT. */
-#define portPIT_CLOCK_DIVISOR           ( ( uint32_t ) 16 )
-#define portPIT_COUNTER_VALUE           ( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) * portTICK_PERIOD_MS )
+#define portPIT_CLOCK_DIVISOR              ( ( uint32_t ) 16 )
+#define portPIT_COUNTER_VALUE              ( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) * portTICK_PERIOD_MS )
 
-#define portINT_LEVEL_SENSITIVE  0
-#define portPIT_ENABLE          ( ( uint16_t ) 0x1 << 24 )
-#define portPIT_INT_ENABLE      ( ( uint16_t ) 0x1 << 25 )
+#define portINT_LEVEL_SENSITIVE            0
+#define portPIT_ENABLE                     ( ( uint16_t ) 0x1 << 24 )
+#define portPIT_INT_ENABLE                 ( ( uint16_t ) 0x1 << 25 )
 /*-----------------------------------------------------------*/
 
 /* Setup the timer to generate the tick interrupts. */
@@ -83,61 +83,63 @@ extern void vPortISRStartFirstTask( void );
  *
  * See header file for description.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
-StackType_t *pxOriginalTOS;
+    StackType_t * pxOriginalTOS;
 
     pxOriginalTOS = pxTopOfStack;
 
     /* To ensure asserts in tasks.c don't fail, although in this case the assert
-    is not really required. */
+     * is not really required. */
     pxTopOfStack--;
 
     /* Setup the initial stack of the task.  The stack is set exactly as
-    expected by the portRESTORE_CONTEXT() macro. */
+     * expected by the portRESTORE_CONTEXT() macro. */
 
     /* First on the stack is the return address - which in this case is the
-    start of the task.  The offset is added to make the return address appear
-    as it would within an IRQ ISR. */
+     * start of the task.  The offset is added to make the return address appear
+     * as it would within an IRQ ISR. */
     *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
     pxTopOfStack--;
 
-    *pxTopOfStack = ( StackType_t ) 0x00000000; /* R14 */
+    *pxTopOfStack = ( StackType_t ) 0x00000000;    /* R14 */
     pxTopOfStack--;
     *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
+    *pxTopOfStack = ( StackType_t ) 0x12121212;    /* R12 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
+    *pxTopOfStack = ( StackType_t ) 0x11111111;    /* R11 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
+    *pxTopOfStack = ( StackType_t ) 0x10101010;    /* R10 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
+    *pxTopOfStack = ( StackType_t ) 0x09090909;    /* R9 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
+    *pxTopOfStack = ( StackType_t ) 0x08080808;    /* R8 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
+    *pxTopOfStack = ( StackType_t ) 0x07070707;    /* R7 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
+    *pxTopOfStack = ( StackType_t ) 0x06060606;    /* R6 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
+    *pxTopOfStack = ( StackType_t ) 0x05050505;    /* R5 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
+    *pxTopOfStack = ( StackType_t ) 0x04040404;    /* R4 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
+    *pxTopOfStack = ( StackType_t ) 0x03030303;    /* R3 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
+    *pxTopOfStack = ( StackType_t ) 0x02020202;    /* R2 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
+    *pxTopOfStack = ( StackType_t ) 0x01010101;    /* R1 */
     pxTopOfStack--;
 
     /* When the task starts is will expect to find the function parameter in
-    R0. */
+     * R0. */
     *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
     pxTopOfStack--;
 
     /* The last thing onto the stack is the status register, which is set for
-    system mode, with interrupts enabled. */
+     * system mode, with interrupts enabled. */
     *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
 
     #ifdef THUMB_INTERWORK
@@ -150,9 +152,9 @@ StackType_t *pxOriginalTOS;
     pxTopOfStack--;
 
     /* Some optimisation levels use the stack differently to others.  This
-    means the interrupt flags cannot always be stored on the stack and will
-    instead be stored in a variable, which is then saved as part of the
-    tasks context. */
+     * means the interrupt flags cannot always be stored on the stack and will
+     * instead be stored in a variable, which is then saved as part of the
+     * tasks context. */
     *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
 
     return pxTopOfStack;
@@ -162,7 +164,7 @@ StackType_t *pxOriginalTOS;
 BaseType_t xPortStartScheduler( void )
 {
     /* Start the timer that generates the tick ISR.  Interrupts are disabled
-    here already. */
+     * here already. */
     prvSetupTimerInterrupt();
 
     /* Start the first task. */
@@ -176,7 +178,7 @@ BaseType_t xPortStartScheduler( void )
 void vPortEndScheduler( void )
 {
     /* It is unlikely that the ARM port will require this function as there
-    is nothing to return to.  */
+     * is nothing to return to.  */
 }
 /*-----------------------------------------------------------*/
 
@@ -185,27 +187,23 @@ void vPortEndScheduler( void )
  */
 static void prvSetupTimerInterrupt( void )
 {
-AT91PS_PITC pxPIT = AT91C_BASE_PITC;
+    AT91PS_PITC pxPIT = AT91C_BASE_PITC;
 
     /* Setup the AIC for PIT interrupts.  The interrupt routine chosen depends
-    on whether the preemptive or cooperative scheduler is being used. */
+     * on whether the preemptive or cooperative scheduler is being used. */
     #if configUSE_PREEMPTION == 0
-
-        extern void ( vNonPreemptiveTick ) ( void );
-        AT91F_AIC_ConfigureIt( AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vNonPreemptiveTick );
-
+        extern void( vNonPreemptiveTick ) ( void );
+        AT91F_AIC_ConfigureIt( AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void ( * )( void ) )vNonPreemptiveTick );
     #else
-
-        extern void ( vPreemptiveTick )( void );
-        AT91F_AIC_ConfigureIt( AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vPreemptiveTick );
-
+        extern void( vPreemptiveTick )( void );
+        AT91F_AIC_ConfigureIt( AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void ( * )( void ) )vPreemptiveTick );
     #endif
 
     /* Configure the PIT period. */
     pxPIT->PITC_PIMR = portPIT_ENABLE | portPIT_INT_ENABLE | portPIT_COUNTER_VALUE;
 
     /* Enable the interrupt.  Global interrupts are disabled at this point so
-    this is safe. */
+     * this is safe. */
     AT91C_BASE_AIC->AIC_IECR = 0x1 << AT91C_ID_SYS;
 }
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM7_AT91SAM7S/portISR.c b/portable/GCC/ARM7_AT91SAM7S/portISR.c
index 61cb80419..917c67ddb 100644
--- a/portable/GCC/ARM7_AT91SAM7S/portISR.c
+++ b/portable/GCC/ARM7_AT91SAM7S/portISR.c
@@ -28,17 +28,17 @@
 
 
 /*-----------------------------------------------------------
- * Components that can be compiled to either ARM or THUMB mode are
- * contained in port.c  The ISR routines, which can only be compiled
- * to ARM mode, are contained in this file.
- *----------------------------------------------------------*/
+* Components that can be compiled to either ARM or THUMB mode are
+* contained in port.c  The ISR routines, which can only be compiled
+* to ARM mode, are contained in this file.
+*----------------------------------------------------------*/
 
 /*
-    Changes from V3.2.4
-
-    + The assembler statements are now included in a single asm block rather
-      than each line having its own asm block.
-*/
+ *  Changes from V3.2.4
+ *
+ + The assembler statements are now included in a single asm block rather
+ +    than each line having its own asm block.
+ */
 
 /* Scheduler includes. */
 #include "FreeRTOS.h"
@@ -47,17 +47,17 @@
 #include "AT91SAM7X256.h"
 
 /* Constants required to handle interrupts. */
-#define portTIMER_MATCH_ISR_BIT     ( ( uint8_t ) 0x01 )
-#define portCLEAR_VIC_INTERRUPT     ( ( uint32_t ) 0 )
+#define portTIMER_MATCH_ISR_BIT    ( ( uint8_t ) 0x01 )
+#define portCLEAR_VIC_INTERRUPT    ( ( uint32_t ) 0 )
 
 /* Constants required to handle critical sections. */
-#define portNO_CRITICAL_NESTING     ( ( uint32_t ) 0 )
+#define portNO_CRITICAL_NESTING    ( ( uint32_t ) 0 )
 volatile uint32_t ulCriticalNesting = 9999UL;
 
 /*-----------------------------------------------------------*/
 
 /* ISR to handle manual context switches (from a call to taskYIELD()). */
-void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked));
+void vPortYieldProcessor( void ) __attribute__( ( interrupt( "SWI" ), naked ) );
 
 /*
  * The scheduler can only be started from ARM mode, hence the inclusion of this
@@ -69,7 +69,7 @@ void vPortISRStartFirstTask( void );
 void vPortISRStartFirstTask( void )
 {
     /* Simply start the scheduler.  This is included here as it can only be
-    called from ARM mode. */
+     * called from ARM mode. */
     portRESTORE_CONTEXT();
 }
 /*-----------------------------------------------------------*/
@@ -85,8 +85,8 @@ void vPortISRStartFirstTask( void )
 void vPortYieldProcessor( void )
 {
     /* Within an IRQ ISR the link register has an offset from the true return
-    address, but an SWI ISR does not.  Add the offset manually so the same
-    ISR return code can be used in both cases. */
+     * address, but an SWI ISR does not.  Add the offset manually so the same
+     * ISR return code can be used in both cases. */
     __asm volatile ( "ADD       LR, LR, #4" );
 
     /* Perform the context switch.  First save the context of the current task. */
@@ -107,16 +107,16 @@ void vPortYieldProcessor( void )
 
 #if configUSE_PREEMPTION == 0
 
-    /* The cooperative scheduler requires a normal IRQ service routine to
-    simply increment the system tick. */
-    void vNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ")));
+/* The cooperative scheduler requires a normal IRQ service routine to
+ * simply increment the system tick. */
+    void vNonPreemptiveTick( void ) __attribute__( ( interrupt( "IRQ" ) ) );
     void vNonPreemptiveTick( void )
     {
         uint32_t ulDummy;
 
         /* Increment the tick count - which may wake some tasks but as the
-        preemptive scheduler is not being used any woken task is not given
-        processor time no matter what its priority. */
+         * preemptive scheduler is not being used any woken task is not given
+         * processor time no matter what its priority. */
         xTaskIncrementTick();
 
         /* Clear the PIT interrupt. */
@@ -126,11 +126,11 @@ void vPortYieldProcessor( void )
         AT91C_BASE_AIC->AIC_EOICR = ulDummy;
     }
 
-#else
+#else /* if configUSE_PREEMPTION == 0 */
 
-    /* The preemptive scheduler is defined as "naked" as the full context is
-    saved on entry as part of the context switch. */
-    void vPreemptiveTick( void ) __attribute__((naked));
+/* The preemptive scheduler is defined as "naked" as the full context is
+ * saved on entry as part of the context switch. */
+    void vPreemptiveTick( void ) __attribute__( ( naked ) );
     void vPreemptiveTick( void )
     {
         /* Save the context of the current task. */
@@ -149,7 +149,7 @@ void vPortYieldProcessor( void )
         portRESTORE_CONTEXT();
     }
 
-#endif
+#endif /* if configUSE_PREEMPTION == 0 */
 /*-----------------------------------------------------------*/
 
 /*
@@ -158,49 +158,49 @@ void vPortYieldProcessor( void )
  * ensure a switch to ARM mode.  When THUMB_INTERWORK is not defined then
  * the utilities are defined as macros in portmacro.h - as per other ports.
  */
-void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
-void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
+void vPortDisableInterruptsFromThumb( void ) __attribute__( ( naked ) );
+void vPortEnableInterruptsFromThumb( void ) __attribute__( ( naked ) );
 
 void vPortDisableInterruptsFromThumb( void )
 {
     __asm volatile (
-        "STMDB  SP!, {R0}       \n\t"   /* Push R0.                                 */
-        "MRS    R0, CPSR        \n\t"   /* Get CPSR.                                */
-        "ORR    R0, R0, #0xC0   \n\t"   /* Disable IRQ, FIQ.                        */
-        "MSR    CPSR, R0        \n\t"   /* Write back modified value.               */
-        "LDMIA  SP!, {R0}       \n\t"   /* Pop R0.                                  */
-        "BX     R14" );                 /* Return back to thumb.                    */
+        "STMDB  SP!, {R0}       \n\t" /* Push R0.                                 */
+        "MRS    R0, CPSR        \n\t" /* Get CPSR.                                */
+        "ORR    R0, R0, #0xC0   \n\t" /* Disable IRQ, FIQ.                        */
+        "MSR    CPSR, R0        \n\t" /* Write back modified value.               */
+        "LDMIA  SP!, {R0}       \n\t" /* Pop R0.                                  */
+        "BX     R14" );               /* Return back to thumb.                    */
 }
 
 void vPortEnableInterruptsFromThumb( void )
 {
     __asm volatile (
-        "STMDB  SP!, {R0}       \n\t"   /* Push R0.                                 */
-        "MRS    R0, CPSR        \n\t"   /* Get CPSR.                                */
-        "BIC    R0, R0, #0xC0   \n\t"   /* Enable IRQ, FIQ.                         */
-        "MSR    CPSR, R0        \n\t"   /* Write back modified value.               */
-        "LDMIA  SP!, {R0}       \n\t"   /* Pop R0.                                  */
-        "BX     R14" );                 /* Return back to thumb.                    */
+        "STMDB  SP!, {R0}       \n\t" /* Push R0.                                 */
+        "MRS    R0, CPSR        \n\t" /* Get CPSR.                                */
+        "BIC    R0, R0, #0xC0   \n\t" /* Enable IRQ, FIQ.                         */
+        "MSR    CPSR, R0        \n\t" /* Write back modified value.               */
+        "LDMIA  SP!, {R0}       \n\t" /* Pop R0.                                  */
+        "BX     R14" );               /* Return back to thumb.                    */
 }
 
 
 /* The code generated by the GCC compiler uses the stack in different ways at
-different optimisation levels.  The interrupt flags can therefore not always
-be saved to the stack.  Instead the critical section nesting level is stored
-in a variable, which is then saved as part of the stack context. */
+ * different optimisation levels.  The interrupt flags can therefore not always
+ * be saved to the stack.  Instead the critical section nesting level is stored
+ * in a variable, which is then saved as part of the stack context. */
 void vPortEnterCritical( void )
 {
     /* Disable interrupts as per portDISABLE_INTERRUPTS();                          */
     __asm volatile (
-        "STMDB  SP!, {R0}           \n\t"   /* Push R0.                             */
-        "MRS    R0, CPSR            \n\t"   /* Get CPSR.                            */
-        "ORR    R0, R0, #0xC0       \n\t"   /* Disable IRQ, FIQ.                    */
-        "MSR    CPSR, R0            \n\t"   /* Write back modified value.           */
-        "LDMIA  SP!, {R0}" );               /* Pop R0.                              */
+        "STMDB  SP!, {R0}           \n\t" /* Push R0.                             */
+        "MRS    R0, CPSR            \n\t" /* Get CPSR.                            */
+        "ORR    R0, R0, #0xC0       \n\t" /* Disable IRQ, FIQ.                    */
+        "MSR    CPSR, R0            \n\t" /* Write back modified value.           */
+        "LDMIA  SP!, {R0}" );             /* Pop R0.                              */
 
-    /* Now interrupts are disabled ulCriticalNesting can be accessed
-    directly.  Increment ulCriticalNesting to keep a count of how many times
-    portENTER_CRITICAL() has been called. */
+    /* Now that interrupts are disabled, ulCriticalNesting can be accessed
+     * directly.  Increment ulCriticalNesting to keep a count of how many times
+     * portENTER_CRITICAL() has been called. */
     ulCriticalNesting++;
 }
 
@@ -212,16 +212,16 @@ void vPortExitCritical( void )
         ulCriticalNesting--;
 
         /* If the nesting level has reached zero then interrupts should be
-        re-enabled. */
+         * re-enabled. */
         if( ulCriticalNesting == portNO_CRITICAL_NESTING )
         {
             /* Enable interrupts as per portEXIT_CRITICAL().                    */
             __asm volatile (
-                "STMDB  SP!, {R0}       \n\t"   /* Push R0.                     */
-                "MRS    R0, CPSR        \n\t"   /* Get CPSR.                    */
-                "BIC    R0, R0, #0xC0   \n\t"   /* Enable IRQ, FIQ.             */
-                "MSR    CPSR, R0        \n\t"   /* Write back modified value.   */
-                "LDMIA  SP!, {R0}" );           /* Pop R0.                      */
+                "STMDB  SP!, {R0}       \n\t" /* Push R0.                     */
+                "MRS    R0, CPSR        \n\t" /* Get CPSR.                    */
+                "BIC    R0, R0, #0xC0   \n\t" /* Enable IRQ, FIQ.             */
+                "MSR    CPSR, R0        \n\t" /* Write back modified value.   */
+                "LDMIA  SP!, {R0}" );         /* Pop R0.                      */
         }
     }
 }
diff --git a/portable/GCC/ARM7_AT91SAM7S/portmacro.h b/portable/GCC/ARM7_AT91SAM7S/portmacro.h
index b52fbe0aa..5b78481e3 100644
--- a/portable/GCC/ARM7_AT91SAM7S/portmacro.h
+++ b/portable/GCC/ARM7_AT91SAM7S/portmacro.h
@@ -27,27 +27,27 @@
  */
 
 /*
-    Changes from V3.2.3
-
-    + Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1.
-
-    Changes from V3.2.4
-
-    + Removed the use of the %0 parameter within the assembler macros and
-      replaced them with hard coded registers.  This will ensure the
-      assembler does not select the link register as the temp register as
-      was occasionally happening previously.
-
-    + The assembler statements are now included in a single asm block rather
-      than each line having its own asm block.
-
-    Changes from V4.5.0
-
-    + Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros
-      and replaced them with portYIELD_FROM_ISR() macro.  Application code
-      should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT()
-      macros as per the V4.5.1 demo code.
-*/
+ *  Changes from V3.2.3
+ *
+ + Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1.
+ +
+ +  Changes from V3.2.4
+ +
+ + Removed the use of the %0 parameter within the assembler macros and
+ +    replaced them with hard coded registers.  This will ensure the
+ +    assembler does not select the link register as the temp register as
+ +    was occasionally happening previously.
+ +
+ + The assembler statements are now included in a single asm block rather
+ +    than each line having its own asm block.
+ +
+ +  Changes from V4.5.0
+ +
+ + Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros
+ +    and replaced them with portYIELD_FROM_ISR() macro.  Application code
+ +    should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT()
+ +    macros as per the V4.5.1 demo code.
+ */
 
 #ifndef PORTMACRO_H
 #define PORTMACRO_H
@@ -69,34 +69,34 @@
  */
 
 /* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint32_t
-#define portBASE_TYPE   portLONG
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     portLONG
 
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY ( TickType_t )    ( 0xFFFFFFFFUL )
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) ( 0xFFFFFFFFUL )
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
 /*-----------------------------------------------------------*/
 
 /* Architecture specifics. */
-#define portSTACK_GROWTH            ( -1 )
-#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT          8
-#define portNOP()                   __asm volatile ( "NOP" );
+#define portSTACK_GROWTH      ( -1 )
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT    8
+#define portNOP()    __asm volatile ( "NOP" );
 /*-----------------------------------------------------------*/
 
 
@@ -109,92 +109,92 @@ typedef unsigned long UBaseType_t;
  * THUMB mode code will result in a compile time error.
  */
 
-#define portRESTORE_CONTEXT()                                           \
-{                                                                       \
-extern volatile void * volatile pxCurrentTCB;                           \
-extern volatile uint32_t ulCriticalNesting;                 \
-                                                                        \
-    /* Set the LR to the task stack. */                                 \
-    __asm volatile (                                                    \
-    "LDR        R0, =pxCurrentTCB                               \n\t"   \
-    "LDR        R0, [R0]                                        \n\t"   \
-    "LDR        LR, [R0]                                        \n\t"   \
-                                                                        \
-    /* The critical nesting depth is the first item on the stack. */    \
-    /* Load it into the ulCriticalNesting variable. */                  \
-    "LDR        R0, =ulCriticalNesting                          \n\t"   \
-    "LDMFD  LR!, {R1}                                           \n\t"   \
-    "STR        R1, [R0]                                        \n\t"   \
-                                                                        \
-    /* Get the SPSR from the stack. */                                  \
-    "LDMFD  LR!, {R0}                                           \n\t"   \
-    "MSR        SPSR, R0                                        \n\t"   \
-                                                                        \
-    /* Restore all system mode registers for the task. */               \
-    "LDMFD  LR, {R0-R14}^                                       \n\t"   \
-    "NOP                                                        \n\t"   \
-                                                                        \
-    /* Restore the return address. */                                   \
-    "LDR        LR, [LR, #+60]                                  \n\t"   \
-                                                                        \
-    /* And return - correcting the offset in the LR to obtain the */    \
-    /* correct address. */                                              \
-    "SUBS   PC, LR, #4                                          \n\t"   \
-    );                                                                  \
-    ( void ) ulCriticalNesting;                                         \
-    ( void ) pxCurrentTCB;                                              \
-}
+#define portRESTORE_CONTEXT()                                                 \
+    {                                                                         \
+        extern volatile void * volatile pxCurrentTCB;                         \
+        extern volatile uint32_t ulCriticalNesting;                           \
+                                                                              \
+        /* Set the LR to the task stack. */                                   \
+        __asm volatile (                                                      \
+            "LDR        R0, =pxCurrentTCB                               \n\t" \
+            "LDR        R0, [R0]                                        \n\t" \
+            "LDR        LR, [R0]                                        \n\t" \
+                                                                              \
+            /* The critical nesting depth is the first item on the stack. */  \
+            /* Load it into the ulCriticalNesting variable. */                \
+            "LDR        R0, =ulCriticalNesting                          \n\t" \
+            "LDMFD  LR!, {R1}                                           \n\t" \
+            "STR        R1, [R0]                                        \n\t" \
+                                                                              \
+            /* Get the SPSR from the stack. */                                \
+            "LDMFD  LR!, {R0}                                           \n\t" \
+            "MSR        SPSR, R0                                        \n\t" \
+                                                                              \
+            /* Restore all system mode registers for the task. */             \
+            "LDMFD  LR, {R0-R14}^                                       \n\t" \
+            "NOP                                                        \n\t" \
+                                                                              \
+            /* Restore the return address. */                                 \
+            "LDR        LR, [LR, #+60]                                  \n\t" \
+                                                                              \
+            /* And return - correcting the offset in the LR to obtain the */  \
+            /* correct address. */                                            \
+            "SUBS   PC, LR, #4                                          \n\t" \
+            );                                                                \
+        ( void ) ulCriticalNesting;                                           \
+        ( void ) pxCurrentTCB;                                                \
+    }
 /*-----------------------------------------------------------*/
 
-#define portSAVE_CONTEXT()                                              \
-{                                                                       \
-extern volatile void * volatile pxCurrentTCB;                           \
-extern volatile uint32_t ulCriticalNesting;                 \
-                                                                        \
-    /* Push R0 as we are going to use the register. */                  \
-    __asm volatile (                                                    \
-    "STMDB  SP!, {R0}                                           \n\t"   \
-                                                                        \
-    /* Set R0 to point to the task stack pointer. */                    \
-    "STMDB  SP,{SP}^                                            \n\t"   \
-    "NOP                                                        \n\t"   \
-    "SUB    SP, SP, #4                                          \n\t"   \
-    "LDMIA  SP!,{R0}                                            \n\t"   \
-                                                                        \
-    /* Push the return address onto the stack. */                       \
-    "STMDB  R0!, {LR}                                           \n\t"   \
-                                                                        \
-    /* Now we have saved LR we can use it instead of R0. */             \
-    "MOV    LR, R0                                              \n\t"   \
-                                                                        \
-    /* Pop R0 so we can save it onto the system mode stack. */          \
-    "LDMIA  SP!, {R0}                                           \n\t"   \
-                                                                        \
-    /* Push all the system mode registers onto the task stack. */       \
-    "STMDB  LR,{R0-LR}^                                         \n\t"   \
-    "NOP                                                        \n\t"   \
-    "SUB    LR, LR, #60                                         \n\t"   \
-                                                                        \
-    /* Push the SPSR onto the task stack. */                            \
-    "MRS    R0, SPSR                                            \n\t"   \
-    "STMDB  LR!, {R0}                                           \n\t"   \
-                                                                        \
-    "LDR    R0, =ulCriticalNesting                              \n\t"   \
-    "LDR    R0, [R0]                                            \n\t"   \
-    "STMDB  LR!, {R0}                                           \n\t"   \
-                                                                        \
-    /* Store the new top of stack for the task. */                      \
-    "LDR    R0, =pxCurrentTCB                                   \n\t"   \
-    "LDR    R0, [R0]                                            \n\t"   \
-    "STR    LR, [R0]                                            \n\t"   \
-    );                                                                  \
-    ( void ) ulCriticalNesting;                                         \
-    ( void ) pxCurrentTCB;                                              \
-}
+#define portSAVE_CONTEXT()                                                    \
+    {                                                                         \
+        extern volatile void * volatile pxCurrentTCB;                         \
+        extern volatile uint32_t ulCriticalNesting;                           \
+                                                                              \
+        /* Push R0 as we are going to use the register. */                    \
+        __asm volatile (                                                      \
+            "STMDB  SP!, {R0}                                           \n\t" \
+                                                                              \
+            /* Set R0 to point to the task stack pointer. */                  \
+            "STMDB  SP,{SP}^                                            \n\t" \
+            "NOP                                                        \n\t" \
+            "SUB    SP, SP, #4                                          \n\t" \
+            "LDMIA  SP!,{R0}                                            \n\t" \
+                                                                              \
+            /* Push the return address onto the stack. */                     \
+            "STMDB  R0!, {LR}                                           \n\t" \
+                                                                              \
+            /* Now we have saved LR we can use it instead of R0. */           \
+            "MOV    LR, R0                                              \n\t" \
+                                                                              \
+            /* Pop R0 so we can save it onto the system mode stack. */        \
+            "LDMIA  SP!, {R0}                                           \n\t" \
+                                                                              \
+            /* Push all the system mode registers onto the task stack. */     \
+            "STMDB  LR,{R0-LR}^                                         \n\t" \
+            "NOP                                                        \n\t" \
+            "SUB    LR, LR, #60                                         \n\t" \
+                                                                              \
+            /* Push the SPSR onto the task stack. */                          \
+            "MRS    R0, SPSR                                            \n\t" \
+            "STMDB  LR!, {R0}                                           \n\t" \
+                                                                              \
+            "LDR    R0, =ulCriticalNesting                              \n\t" \
+            "LDR    R0, [R0]                                            \n\t" \
+            "STMDB  LR!, {R0}                                           \n\t" \
+                                                                              \
+            /* Store the new top of stack for the task. */                    \
+            "LDR    R0, =pxCurrentTCB                                   \n\t" \
+            "LDR    R0, [R0]                                            \n\t" \
+            "STR    LR, [R0]                                            \n\t" \
+            );                                                                \
+        ( void ) ulCriticalNesting;                                           \
+        ( void ) pxCurrentTCB;                                                \
+    }
 
 
-#define portYIELD_FROM_ISR()        vTaskSwitchContext()
-#define portYIELD()                 __asm volatile ( "SWI 0" )
+#define portYIELD_FROM_ISR()    vTaskSwitchContext()
+#define portYIELD()             __asm volatile ( "SWI 0" )
 /*-----------------------------------------------------------*/
 
 
@@ -209,42 +209,42 @@ extern volatile uint32_t ulCriticalNesting;                 \
 
 #ifdef THUMB_INTERWORK
 
-    extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
-    extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
+    extern void vPortDisableInterruptsFromThumb( void ) __attribute__( ( naked ) );
+    extern void vPortEnableInterruptsFromThumb( void ) __attribute__( ( naked ) );
 
     #define portDISABLE_INTERRUPTS()    vPortDisableInterruptsFromThumb()
     #define portENABLE_INTERRUPTS()     vPortEnableInterruptsFromThumb()
 
 #else
 
-    #define portDISABLE_INTERRUPTS()                                            \
-        __asm volatile (                                                        \
-            "STMDB  SP!, {R0}       \n\t"   /* Push R0.                     */  \
-            "MRS    R0, CPSR        \n\t"   /* Get CPSR.                    */  \
-            "ORR    R0, R0, #0xC0   \n\t"   /* Disable IRQ, FIQ.            */  \
-            "MSR    CPSR, R0        \n\t"   /* Write back modified value.   */  \
-            "LDMIA  SP!, {R0}           " ) /* Pop R0.                      */
+    #define portDISABLE_INTERRUPTS()                                       \
+    __asm volatile (                                                       \
+        "STMDB  SP!, {R0}       \n\t"   /* Push R0.                     */ \
+        "MRS    R0, CPSR        \n\t"   /* Get CPSR.                    */ \
+        "ORR    R0, R0, #0xC0   \n\t"   /* Disable IRQ, FIQ.            */ \
+        "MSR    CPSR, R0        \n\t"   /* Write back modified value.   */ \
+        "LDMIA  SP!, {R0}           " ) /* Pop R0.                      */
 
-    #define portENABLE_INTERRUPTS()                                             \
-        __asm volatile (                                                        \
-            "STMDB  SP!, {R0}       \n\t"   /* Push R0.                     */  \
-            "MRS    R0, CPSR        \n\t"   /* Get CPSR.                    */  \
-            "BIC    R0, R0, #0xC0   \n\t"   /* Enable IRQ, FIQ.             */  \
-            "MSR    CPSR, R0        \n\t"   /* Write back modified value.   */  \
-            "LDMIA  SP!, {R0}           " ) /* Pop R0.                      */
+    #define portENABLE_INTERRUPTS()                                        \
+    __asm volatile (                                                       \
+        "STMDB  SP!, {R0}       \n\t"   /* Push R0.                     */ \
+        "MRS    R0, CPSR        \n\t"   /* Get CPSR.                    */ \
+        "BIC    R0, R0, #0xC0   \n\t"   /* Enable IRQ, FIQ.             */ \
+        "MSR    CPSR, R0        \n\t"   /* Write back modified value.   */ \
+        "LDMIA  SP!, {R0}           " ) /* Pop R0.                      */
 
 #endif /* THUMB_INTERWORK */
 
 extern void vPortEnterCritical( void );
 extern void vPortExitCritical( void );
 
-#define portENTER_CRITICAL()        vPortEnterCritical();
-#define portEXIT_CRITICAL()         vPortExitCritical();
+#define portENTER_CRITICAL()    vPortEnterCritical();
+#define portEXIT_CRITICAL()     vPortExitCritical();
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/GCC/ARM7_LPC2000/port.c b/portable/GCC/ARM7_LPC2000/port.c
index 87a8fd34d..53df1a534 100644
--- a/portable/GCC/ARM7_LPC2000/port.c
+++ b/portable/GCC/ARM7_LPC2000/port.c
@@ -28,12 +28,12 @@
 
 
 /*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the ARM7 port.
- *
- * Components that can be compiled to either ARM or THUMB mode are
- * contained in this file.  The ISR routines, which can only be compiled
- * to ARM mode are contained in portISR.c.
- *----------------------------------------------------------*/
+* Implementation of functions defined in portable.h for the ARM7 port.
+*
+* Components that can be compiled to either ARM or THUMB mode are
+* contained in this file.  The ISR routines, which can only be compiled
+* to ARM mode are contained in portISR.c.
+*----------------------------------------------------------*/
 
 
 /* Standard includes. */
@@ -44,21 +44,21 @@
 #include "task.h"
 
 /* Constants required to setup the task context. */
-#define portINITIAL_SPSR                ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
-#define portTHUMB_MODE_BIT              ( ( StackType_t ) 0x20 )
-#define portINSTRUCTION_SIZE            ( ( StackType_t ) 4 )
-#define portNO_CRITICAL_SECTION_NESTING ( ( StackType_t ) 0 )
+#define portINITIAL_SPSR                   ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT                 ( ( StackType_t ) 0x20 )
+#define portINSTRUCTION_SIZE               ( ( StackType_t ) 4 )
+#define portNO_CRITICAL_SECTION_NESTING    ( ( StackType_t ) 0 )
 
 /* Constants required to setup the tick ISR. */
-#define portENABLE_TIMER            ( ( uint8_t ) 0x01 )
-#define portPRESCALE_VALUE          0x00
-#define portINTERRUPT_ON_MATCH      ( ( uint32_t ) 0x01 )
-#define portRESET_COUNT_ON_MATCH    ( ( uint32_t ) 0x02 )
+#define portENABLE_TIMER                   ( ( uint8_t ) 0x01 )
+#define portPRESCALE_VALUE                 0x00
+#define portINTERRUPT_ON_MATCH             ( ( uint32_t ) 0x01 )
+#define portRESET_COUNT_ON_MATCH           ( ( uint32_t ) 0x02 )
 
 /* Constants required to setup the VIC for the tick ISR. */
-#define portTIMER_VIC_CHANNEL       ( ( uint32_t ) 0x0004 )
-#define portTIMER_VIC_CHANNEL_BIT   ( ( uint32_t ) 0x0010 )
-#define portTIMER_VIC_ENABLE        ( ( uint32_t ) 0x0020 )
+#define portTIMER_VIC_CHANNEL              ( ( uint32_t ) 0x0004 )
+#define portTIMER_VIC_CHANNEL_BIT          ( ( uint32_t ) 0x0010 )
+#define portTIMER_VIC_ENABLE               ( ( uint32_t ) 0x0020 )
 
 /*-----------------------------------------------------------*/
 
@@ -79,61 +79,63 @@ extern void vPortISRStartFirstTask( void );
  *
  * See header file for description.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
-StackType_t *pxOriginalTOS;
+    StackType_t * pxOriginalTOS;
 
     pxOriginalTOS = pxTopOfStack;
 
     /* To ensure asserts in tasks.c don't fail, although in this case the assert
-    is not really required. */
+     * is not really required. */
     pxTopOfStack--;
 
     /* Setup the initial stack of the task.  The stack is set exactly as
-    expected by the portRESTORE_CONTEXT() macro. */
+     * expected by the portRESTORE_CONTEXT() macro. */
 
     /* First on the stack is the return address - which in this case is the
-    start of the task.  The offset is added to make the return address appear
-    as it would within an IRQ ISR. */
+     * start of the task.  The offset is added to make the return address appear
+     * as it would within an IRQ ISR. */
     *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
     pxTopOfStack--;
 
-    *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */
+    *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa;    /* R14 */
     pxTopOfStack--;
     *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
+    *pxTopOfStack = ( StackType_t ) 0x12121212;    /* R12 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
+    *pxTopOfStack = ( StackType_t ) 0x11111111;    /* R11 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
+    *pxTopOfStack = ( StackType_t ) 0x10101010;    /* R10 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
+    *pxTopOfStack = ( StackType_t ) 0x09090909;    /* R9 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
+    *pxTopOfStack = ( StackType_t ) 0x08080808;    /* R8 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
+    *pxTopOfStack = ( StackType_t ) 0x07070707;    /* R7 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
+    *pxTopOfStack = ( StackType_t ) 0x06060606;    /* R6 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
+    *pxTopOfStack = ( StackType_t ) 0x05050505;    /* R5 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
+    *pxTopOfStack = ( StackType_t ) 0x04040404;    /* R4 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
+    *pxTopOfStack = ( StackType_t ) 0x03030303;    /* R3 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
+    *pxTopOfStack = ( StackType_t ) 0x02020202;    /* R2 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
+    *pxTopOfStack = ( StackType_t ) 0x01010101;    /* R1 */
     pxTopOfStack--;
 
     /* When the task starts is will expect to find the function parameter in
-    R0. */
+     * R0. */
     *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
     pxTopOfStack--;
 
     /* The last thing onto the stack is the status register, which is set for
-    system mode, with interrupts enabled. */
+     * system mode, with interrupts enabled. */
     *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
 
     if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00 )
@@ -145,9 +147,9 @@ StackType_t *pxOriginalTOS;
     pxTopOfStack--;
 
     /* Some optimisation levels use the stack differently to others.  This
-    means the interrupt flags cannot always be stored on the stack and will
-    instead be stored in a variable, which is then saved as part of the
-    tasks context. */
+     * means the interrupt flags cannot always be stored on the stack and will
+     * instead be stored in a variable, which is then saved as part of the
+     * tasks context. */
     *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
 
     return pxTopOfStack;
@@ -157,7 +159,7 @@ StackType_t *pxOriginalTOS;
 BaseType_t xPortStartScheduler( void )
 {
     /* Start the timer that generates the tick ISR.  Interrupts are disabled
-    here already. */
+     * here already. */
     prvSetupTimerInterrupt();
 
     /* Start the first task. */
@@ -171,7 +173,7 @@ BaseType_t xPortStartScheduler( void )
 void vPortEndScheduler( void )
 {
     /* It is unlikely that the ARM port will require this function as there
-    is nothing to return to.  */
+     * is nothing to return to.  */
 }
 /*-----------------------------------------------------------*/
 
@@ -180,18 +182,19 @@ void vPortEndScheduler( void )
  */
 static void prvSetupTimerInterrupt( void )
 {
-uint32_t ulCompareMatch;
-extern void ( vTickISR )( void );
+    uint32_t ulCompareMatch;
+
+    extern void( vTickISR )( void );
 
     /* A 1ms tick does not require the use of the timer prescale.  This is
-    defaulted to zero but can be used if necessary. */
+     * defaulted to zero but can be used if necessary. */
     T0_PR = portPRESCALE_VALUE;
 
     /* Calculate the match value required for our wanted tick rate. */
     ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
 
     /* Protect against divide by zero.  Using an if() statement still results
-    in a warning - hence the #if. */
+     * in a warning - hence the #if. */
     #if portPRESCALE_VALUE != 0
     {
         ulCompareMatch /= ( portPRESCALE_VALUE + 1 );
@@ -207,13 +210,13 @@ extern void ( vTickISR )( void );
     VICIntEnable |= portTIMER_VIC_CHANNEL_BIT;
 
     /* The ISR installed depends on whether the preemptive or cooperative
-    scheduler is being used. */
+     * scheduler is being used. */
 
     VICVectAddr0 = ( int32_t ) vTickISR;
     VICVectCntl0 = portTIMER_VIC_CHANNEL | portTIMER_VIC_ENABLE;
 
     /* Start the timer - interrupts are disabled when this function is called
-    so it is okay to do this here. */
+     * so it is okay to do this here. */
     T0_TCR = portENABLE_TIMER;
 }
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM7_LPC2000/portISR.c b/portable/GCC/ARM7_LPC2000/portISR.c
index f66b4fab1..704907f9d 100644
--- a/portable/GCC/ARM7_LPC2000/portISR.c
+++ b/portable/GCC/ARM7_LPC2000/portISR.c
@@ -28,45 +28,45 @@
 
 
 /*-----------------------------------------------------------
- * Components that can be compiled to either ARM or THUMB mode are
- * contained in port.c  The ISR routines, which can only be compiled
- * to ARM mode, are contained in this file.
- *----------------------------------------------------------*/
+* Components that can be compiled to either ARM or THUMB mode are
+* contained in port.c  The ISR routines, which can only be compiled
+* to ARM mode, are contained in this file.
+*----------------------------------------------------------*/
 
 /*
-    Changes from V2.5.2
-
-    + The critical section management functions have been changed.  These no
-      longer modify the stack and are safe to use at all optimisation levels.
-      The functions are now also the same for both ARM and THUMB modes.
-
-    Changes from V2.6.0
-
-    + Removed the 'static' from the definition of vNonPreemptiveTick() to
-      allow the demo to link when using the cooperative scheduler.
-
-    Changes from V3.2.4
-
-    + The assembler statements are now included in a single asm block rather
-      than each line having its own asm block.
-*/
+ *  Changes from V2.5.2
+ *
+ + The critical section management functions have been changed.  These no
+ +    longer modify the stack and are safe to use at all optimisation levels.
+ +    The functions are now also the same for both ARM and THUMB modes.
+ +
+ +  Changes from V2.6.0
+ +
+ + Removed the 'static' from the definition of vNonPreemptiveTick() to
+ +    allow the demo to link when using the cooperative scheduler.
+ +
+ +  Changes from V3.2.4
+ +
+ + The assembler statements are now included in a single asm block rather
+ +    than each line having its own asm block.
+ */
 
 
 /* Scheduler includes. */
 #include "FreeRTOS.h"
 
 /* Constants required to handle interrupts. */
-#define portTIMER_MATCH_ISR_BIT     ( ( uint8_t ) 0x01 )
-#define portCLEAR_VIC_INTERRUPT     ( ( uint32_t ) 0 )
+#define portTIMER_MATCH_ISR_BIT    ( ( uint8_t ) 0x01 )
+#define portCLEAR_VIC_INTERRUPT    ( ( uint32_t ) 0 )
 
 /* Constants required to handle critical sections. */
-#define portNO_CRITICAL_NESTING     ( ( uint32_t ) 0 )
+#define portNO_CRITICAL_NESTING    ( ( uint32_t ) 0 )
 volatile uint32_t ulCriticalNesting = 9999UL;
 
 /*-----------------------------------------------------------*/
 
 /* ISR to handle manual context switches (from a call to taskYIELD()). */
-void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked));
+void vPortYieldProcessor( void ) __attribute__( ( interrupt( "SWI" ), naked ) );
 
 /*
  * The scheduler can only be started from ARM mode, hence the inclusion of this
@@ -78,7 +78,7 @@ void vPortISRStartFirstTask( void );
 void vPortISRStartFirstTask( void )
 {
     /* Simply start the scheduler.  This is included here as it can only be
-    called from ARM mode. */
+     * called from ARM mode. */
     portRESTORE_CONTEXT();
 }
 /*-----------------------------------------------------------*/
@@ -94,8 +94,8 @@ void vPortISRStartFirstTask( void )
 void vPortYieldProcessor( void )
 {
     /* Within an IRQ ISR the link register has an offset from the true return
-    address, but an SWI ISR does not.  Add the offset manually so the same
-    ISR return code can be used in both cases. */
+     * address, but an SWI ISR does not.  Add the offset manually so the same
+     * ISR return code can be used in both cases. */
     __asm volatile ( "ADD       LR, LR, #4" );
 
     /* Perform the context switch.  First save the context of the current task. */
@@ -112,14 +112,14 @@ void vPortYieldProcessor( void )
 /*
  * The ISR used for the scheduler tick.
  */
-void vTickISR( void ) __attribute__((naked));
+void vTickISR( void ) __attribute__( ( naked ) );
 void vTickISR( void )
 {
     /* Save the context of the interrupted task. */
     portSAVE_CONTEXT();
 
     /* Increment the RTOS tick count, then look for the highest priority
-    task that is ready to run. */
+     * task that is ready to run. */
     __asm volatile
     (
         "   bl xTaskIncrementTick   \t\n" \
@@ -146,50 +146,50 @@ void vTickISR( void )
  */
 #ifdef THUMB_INTERWORK
 
-    void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
-    void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
+    void vPortDisableInterruptsFromThumb( void ) __attribute__( ( naked ) );
+    void vPortEnableInterruptsFromThumb( void ) __attribute__( ( naked ) );
 
     void vPortDisableInterruptsFromThumb( void )
     {
         __asm volatile (
-            "STMDB  SP!, {R0}       \n\t"   /* Push R0.                                 */
-            "MRS    R0, CPSR        \n\t"   /* Get CPSR.                                */
-            "ORR    R0, R0, #0xC0   \n\t"   /* Disable IRQ, FIQ.                        */
-            "MSR    CPSR, R0        \n\t"   /* Write back modified value.               */
-            "LDMIA  SP!, {R0}       \n\t"   /* Pop R0.                                  */
-            "BX     R14" );                 /* Return back to thumb.                    */
+            "STMDB  SP!, {R0}       \n\t" /* Push R0.                                 */
+            "MRS    R0, CPSR        \n\t" /* Get CPSR.                                */
+            "ORR    R0, R0, #0xC0   \n\t" /* Disable IRQ, FIQ.                        */
+            "MSR    CPSR, R0        \n\t" /* Write back modified value.               */
+            "LDMIA  SP!, {R0}       \n\t" /* Pop R0.                                  */
+            "BX     R14" );               /* Return back to thumb.                    */
     }
 
     void vPortEnableInterruptsFromThumb( void )
     {
         __asm volatile (
-            "STMDB  SP!, {R0}       \n\t"   /* Push R0.                                 */
-            "MRS    R0, CPSR        \n\t"   /* Get CPSR.                                */
-            "BIC    R0, R0, #0xC0   \n\t"   /* Enable IRQ, FIQ.                         */
-            "MSR    CPSR, R0        \n\t"   /* Write back modified value.               */
-            "LDMIA  SP!, {R0}       \n\t"   /* Pop R0.                                  */
-            "BX     R14" );                 /* Return back to thumb.                    */
+            "STMDB  SP!, {R0}       \n\t" /* Push R0.                                 */
+            "MRS    R0, CPSR        \n\t" /* Get CPSR.                                */
+            "BIC    R0, R0, #0xC0   \n\t" /* Enable IRQ, FIQ.                         */
+            "MSR    CPSR, R0        \n\t" /* Write back modified value.               */
+            "LDMIA  SP!, {R0}       \n\t" /* Pop R0.                                  */
+            "BX     R14" );               /* Return back to thumb.                    */
     }
 
 #endif /* THUMB_INTERWORK */
 
 /* The code generated by the GCC compiler uses the stack in different ways at
-different optimisation levels.  The interrupt flags can therefore not always
-be saved to the stack.  Instead the critical section nesting level is stored
-in a variable, which is then saved as part of the stack context. */
+ * different optimisation levels.  The interrupt flags can therefore not always
+ * be saved to the stack.  Instead the critical section nesting level is stored
+ * in a variable, which is then saved as part of the stack context. */
 void vPortEnterCritical( void )
 {
     /* Disable interrupts as per portDISABLE_INTERRUPTS();                          */
     __asm volatile (
-        "STMDB  SP!, {R0}           \n\t"   /* Push R0.                             */
-        "MRS    R0, CPSR            \n\t"   /* Get CPSR.                            */
-        "ORR    R0, R0, #0xC0       \n\t"   /* Disable IRQ, FIQ.                    */
-        "MSR    CPSR, R0            \n\t"   /* Write back modified value.           */
-        "LDMIA  SP!, {R0}" );               /* Pop R0.                              */
+        "STMDB  SP!, {R0}           \n\t" /* Push R0.                             */
+        "MRS    R0, CPSR            \n\t" /* Get CPSR.                            */
+        "ORR    R0, R0, #0xC0       \n\t" /* Disable IRQ, FIQ.                    */
+        "MSR    CPSR, R0            \n\t" /* Write back modified value.           */
+        "LDMIA  SP!, {R0}" );             /* Pop R0.                              */
 
-    /* Now interrupts are disabled ulCriticalNesting can be accessed
-    directly.  Increment ulCriticalNesting to keep a count of how many times
-    portENTER_CRITICAL() has been called. */
+    /* Now that interrupts are disabled, ulCriticalNesting can be accessed
+     * directly.  Increment ulCriticalNesting to keep a count of how many times
+     * portENTER_CRITICAL() has been called. */
     ulCriticalNesting++;
 }
 
@@ -201,16 +201,16 @@ void vPortExitCritical( void )
         ulCriticalNesting--;
 
         /* If the nesting level has reached zero then interrupts should be
-        re-enabled. */
+         * re-enabled. */
         if( ulCriticalNesting == portNO_CRITICAL_NESTING )
         {
             /* Enable interrupts as per portEXIT_CRITICAL().                    */
             __asm volatile (
-                "STMDB  SP!, {R0}       \n\t"   /* Push R0.                     */
-                "MRS    R0, CPSR        \n\t"   /* Get CPSR.                    */
-                "BIC    R0, R0, #0xC0   \n\t"   /* Enable IRQ, FIQ.             */
-                "MSR    CPSR, R0        \n\t"   /* Write back modified value.   */
-                "LDMIA  SP!, {R0}" );           /* Pop R0.                      */
+                "STMDB  SP!, {R0}       \n\t" /* Push R0.                     */
+                "MRS    R0, CPSR        \n\t" /* Get CPSR.                    */
+                "BIC    R0, R0, #0xC0   \n\t" /* Enable IRQ, FIQ.             */
+                "MSR    CPSR, R0        \n\t" /* Write back modified value.   */
+                "LDMIA  SP!, {R0}" );         /* Pop R0.                      */
         }
     }
 }
diff --git a/portable/GCC/ARM7_LPC2000/portmacro.h b/portable/GCC/ARM7_LPC2000/portmacro.h
index 6545e1127..b96c6fa8b 100644
--- a/portable/GCC/ARM7_LPC2000/portmacro.h
+++ b/portable/GCC/ARM7_LPC2000/portmacro.h
@@ -46,34 +46,34 @@
  */
 
 /* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint32_t
-#define portBASE_TYPE   portLONG
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     portLONG
 
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY ( TickType_t )    ( 0xFFFFFFFFUL )
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) ( 0xFFFFFFFFUL )
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
 /*-----------------------------------------------------------*/
 
 /* Architecture specifics. */
-#define portSTACK_GROWTH            ( -1 )
-#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT          8
-#define portNOP()                   __asm volatile ( "NOP" );
+#define portSTACK_GROWTH      ( -1 )
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT    8
+#define portNOP()    __asm volatile ( "NOP" );
 /*-----------------------------------------------------------*/
 
 
@@ -86,92 +86,92 @@ typedef unsigned long UBaseType_t;
  * THUMB mode code will result in a compile time error.
  */
 
-#define portRESTORE_CONTEXT()                                           \
-{                                                                       \
-extern volatile void * volatile pxCurrentTCB;                           \
-extern volatile uint32_t ulCriticalNesting;                 \
-                                                                        \
-    /* Set the LR to the task stack. */                                 \
-    __asm volatile (                                                    \
-    "LDR        R0, =pxCurrentTCB                               \n\t"   \
-    "LDR        R0, [R0]                                        \n\t"   \
-    "LDR        LR, [R0]                                        \n\t"   \
-                                                                        \
-    /* The critical nesting depth is the first item on the stack. */    \
-    /* Load it into the ulCriticalNesting variable. */                  \
-    "LDR        R0, =ulCriticalNesting                          \n\t"   \
-    "LDMFD  LR!, {R1}                                           \n\t"   \
-    "STR        R1, [R0]                                        \n\t"   \
-                                                                        \
-    /* Get the SPSR from the stack. */                                  \
-    "LDMFD  LR!, {R0}                                           \n\t"   \
-    "MSR        SPSR, R0                                        \n\t"   \
-                                                                        \
-    /* Restore all system mode registers for the task. */               \
-    "LDMFD  LR, {R0-R14}^                                       \n\t"   \
-    "NOP                                                        \n\t"   \
-                                                                        \
-    /* Restore the return address. */                                   \
-    "LDR        LR, [LR, #+60]                                  \n\t"   \
-                                                                        \
-    /* And return - correcting the offset in the LR to obtain the */    \
-    /* correct address. */                                              \
-    "SUBS   PC, LR, #4                                          \n\t"   \
-    );                                                                  \
-    ( void ) ulCriticalNesting;                                         \
-    ( void ) pxCurrentTCB;                                              \
-}
+#define portRESTORE_CONTEXT()                                                 \
+    {                                                                         \
+        extern volatile void * volatile pxCurrentTCB;                         \
+        extern volatile uint32_t ulCriticalNesting;                           \
+                                                                              \
+        /* Set the LR to the task stack. */                                   \
+        __asm volatile (                                                      \
+            "LDR        R0, =pxCurrentTCB                               \n\t" \
+            "LDR        R0, [R0]                                        \n\t" \
+            "LDR        LR, [R0]                                        \n\t" \
+                                                                              \
+            /* The critical nesting depth is the first item on the stack. */  \
+            /* Load it into the ulCriticalNesting variable. */                \
+            "LDR        R0, =ulCriticalNesting                          \n\t" \
+            "LDMFD  LR!, {R1}                                           \n\t" \
+            "STR        R1, [R0]                                        \n\t" \
+                                                                              \
+            /* Get the SPSR from the stack. */                                \
+            "LDMFD  LR!, {R0}                                           \n\t" \
+            "MSR        SPSR, R0                                        \n\t" \
+                                                                              \
+            /* Restore all system mode registers for the task. */             \
+            "LDMFD  LR, {R0-R14}^                                       \n\t" \
+            "NOP                                                        \n\t" \
+                                                                              \
+            /* Restore the return address. */                                 \
+            "LDR        LR, [LR, #+60]                                  \n\t" \
+                                                                              \
+            /* And return - correcting the offset in the LR to obtain the */  \
+            /* correct address. */                                            \
+            "SUBS   PC, LR, #4                                          \n\t" \
+            );                                                                \
+        ( void ) ulCriticalNesting;                                           \
+        ( void ) pxCurrentTCB;                                                \
+    }
 /*-----------------------------------------------------------*/
 
-#define portSAVE_CONTEXT()                                              \
-{                                                                       \
-extern volatile void * volatile pxCurrentTCB;                           \
-extern volatile uint32_t ulCriticalNesting;                 \
-                                                                        \
-    /* Push R0 as we are going to use the register. */                  \
-    __asm volatile (                                                    \
-    "STMDB  SP!, {R0}                                           \n\t"   \
-                                                                        \
-    /* Set R0 to point to the task stack pointer. */                    \
-    "STMDB  SP,{SP}^                                            \n\t"   \
-    "NOP                                                        \n\t"   \
-    "SUB    SP, SP, #4                                          \n\t"   \
-    "LDMIA  SP!,{R0}                                            \n\t"   \
-                                                                        \
-    /* Push the return address onto the stack. */                       \
-    "STMDB  R0!, {LR}                                           \n\t"   \
-                                                                        \
-    /* Now we have saved LR we can use it instead of R0. */             \
-    "MOV    LR, R0                                              \n\t"   \
-                                                                        \
-    /* Pop R0 so we can save it onto the system mode stack. */          \
-    "LDMIA  SP!, {R0}                                           \n\t"   \
-                                                                        \
-    /* Push all the system mode registers onto the task stack. */       \
-    "STMDB  LR,{R0-LR}^                                         \n\t"   \
-    "NOP                                                        \n\t"   \
-    "SUB    LR, LR, #60                                         \n\t"   \
-                                                                        \
-    /* Push the SPSR onto the task stack. */                            \
-    "MRS    R0, SPSR                                            \n\t"   \
-    "STMDB  LR!, {R0}                                           \n\t"   \
-                                                                        \
-    "LDR    R0, =ulCriticalNesting                              \n\t"   \
-    "LDR    R0, [R0]                                            \n\t"   \
-    "STMDB  LR!, {R0}                                           \n\t"   \
-                                                                        \
-    /* Store the new top of stack for the task. */                      \
-    "LDR    R0, =pxCurrentTCB                                   \n\t"   \
-    "LDR    R0, [R0]                                            \n\t"   \
-    "STR    LR, [R0]                                            \n\t"   \
-    );                                                                  \
-    ( void ) ulCriticalNesting;                                         \
-    ( void ) pxCurrentTCB;                                              \
-}
+#define portSAVE_CONTEXT()                                                    \
+    {                                                                         \
+        extern volatile void * volatile pxCurrentTCB;                         \
+        extern volatile uint32_t ulCriticalNesting;                           \
+                                                                              \
+        /* Push R0 as we are going to use the register. */                    \
+        __asm volatile (                                                      \
+            "STMDB  SP!, {R0}                                           \n\t" \
+                                                                              \
+            /* Set R0 to point to the task stack pointer. */                  \
+            "STMDB  SP,{SP}^                                            \n\t" \
+            "NOP                                                        \n\t" \
+            "SUB    SP, SP, #4                                          \n\t" \
+            "LDMIA  SP!,{R0}                                            \n\t" \
+                                                                              \
+            /* Push the return address onto the stack. */                     \
+            "STMDB  R0!, {LR}                                           \n\t" \
+                                                                              \
+            /* Now we have saved LR we can use it instead of R0. */           \
+            "MOV    LR, R0                                              \n\t" \
+                                                                              \
+            /* Pop R0 so we can save it onto the system mode stack. */        \
+            "LDMIA  SP!, {R0}                                           \n\t" \
+                                                                              \
+            /* Push all the system mode registers onto the task stack. */     \
+            "STMDB  LR,{R0-LR}^                                         \n\t" \
+            "NOP                                                        \n\t" \
+            "SUB    LR, LR, #60                                         \n\t" \
+                                                                              \
+            /* Push the SPSR onto the task stack. */                          \
+            "MRS    R0, SPSR                                            \n\t" \
+            "STMDB  LR!, {R0}                                           \n\t" \
+                                                                              \
+            "LDR    R0, =ulCriticalNesting                              \n\t" \
+            "LDR    R0, [R0]                                            \n\t" \
+            "STMDB  LR!, {R0}                                           \n\t" \
+                                                                              \
+            /* Store the new top of stack for the task. */                    \
+            "LDR    R0, =pxCurrentTCB                                   \n\t" \
+            "LDR    R0, [R0]                                            \n\t" \
+            "STR    LR, [R0]                                            \n\t" \
+            );                                                                \
+        ( void ) ulCriticalNesting;                                           \
+        ( void ) pxCurrentTCB;                                                \
+    }
 
 extern void vTaskSwitchContext( void );
-#define portYIELD_FROM_ISR()        vTaskSwitchContext()
-#define portYIELD()                 __asm volatile ( "SWI 0" )
+#define portYIELD_FROM_ISR()    vTaskSwitchContext()
+#define portYIELD()             __asm volatile ( "SWI 0" )
 /*-----------------------------------------------------------*/
 
 
@@ -186,42 +186,42 @@ extern void vTaskSwitchContext( void );
 
 #ifdef THUMB_INTERWORK
 
-    extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
-    extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
+    extern void vPortDisableInterruptsFromThumb( void ) __attribute__( ( naked ) );
+    extern void vPortEnableInterruptsFromThumb( void ) __attribute__( ( naked ) );
 
     #define portDISABLE_INTERRUPTS()    vPortDisableInterruptsFromThumb()
     #define portENABLE_INTERRUPTS()     vPortEnableInterruptsFromThumb()
 
 #else
 
-    #define portDISABLE_INTERRUPTS()                                            \
-        __asm volatile (                                                        \
-            "STMDB  SP!, {R0}       \n\t"   /* Push R0.                     */  \
-            "MRS    R0, CPSR        \n\t"   /* Get CPSR.                    */  \
-            "ORR    R0, R0, #0xC0   \n\t"   /* Disable IRQ, FIQ.            */  \
-            "MSR    CPSR, R0        \n\t"   /* Write back modified value.   */  \
-            "LDMIA  SP!, {R0}           " ) /* Pop R0.                      */
+    #define portDISABLE_INTERRUPTS()                                       \
+    __asm volatile (                                                       \
+        "STMDB  SP!, {R0}       \n\t"   /* Push R0.                     */ \
+        "MRS    R0, CPSR        \n\t"   /* Get CPSR.                    */ \
+        "ORR    R0, R0, #0xC0   \n\t"   /* Disable IRQ, FIQ.            */ \
+        "MSR    CPSR, R0        \n\t"   /* Write back modified value.   */ \
+        "LDMIA  SP!, {R0}           " ) /* Pop R0.                      */
 
-    #define portENABLE_INTERRUPTS()                                             \
-        __asm volatile (                                                        \
-            "STMDB  SP!, {R0}       \n\t"   /* Push R0.                     */  \
-            "MRS    R0, CPSR        \n\t"   /* Get CPSR.                    */  \
-            "BIC    R0, R0, #0xC0   \n\t"   /* Enable IRQ, FIQ.             */  \
-            "MSR    CPSR, R0        \n\t"   /* Write back modified value.   */  \
-            "LDMIA  SP!, {R0}           " ) /* Pop R0.                      */
+    #define portENABLE_INTERRUPTS()                                        \
+    __asm volatile (                                                       \
+        "STMDB  SP!, {R0}       \n\t"   /* Push R0.                     */ \
+        "MRS    R0, CPSR        \n\t"   /* Get CPSR.                    */ \
+        "BIC    R0, R0, #0xC0   \n\t"   /* Enable IRQ, FIQ.             */ \
+        "MSR    CPSR, R0        \n\t"   /* Write back modified value.   */ \
+        "LDMIA  SP!, {R0}           " ) /* Pop R0.                      */
 
 #endif /* THUMB_INTERWORK */
 
 extern void vPortEnterCritical( void );
 extern void vPortExitCritical( void );
 
-#define portENTER_CRITICAL()        vPortEnterCritical();
-#define portEXIT_CRITICAL()         vPortExitCritical();
+#define portENTER_CRITICAL()    vPortEnterCritical();
+#define portEXIT_CRITICAL()     vPortExitCritical();
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/GCC/ARM7_LPC23xx/port.c b/portable/GCC/ARM7_LPC23xx/port.c
index 3b9921775..4ec34eb3f 100644
--- a/portable/GCC/ARM7_LPC23xx/port.c
+++ b/portable/GCC/ARM7_LPC23xx/port.c
@@ -28,12 +28,12 @@
 
 
 /*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the ARM7 port.
- *
- * Components that can be compiled to either ARM or THUMB mode are
- * contained in this file.  The ISR routines, which can only be compiled
- * to ARM mode are contained in portISR.c.
- *----------------------------------------------------------*/
+* Implementation of functions defined in portable.h for the ARM7 port.
+*
+* Components that can be compiled to either ARM or THUMB mode are
+* contained in this file.  The ISR routines, which can only be compiled
+* to ARM mode are contained in portISR.c.
+*----------------------------------------------------------*/
 
 
 /* Standard includes. */
@@ -44,21 +44,21 @@
 #include "task.h"
 
 /* Constants required to setup the task context. */
-#define portINITIAL_SPSR                ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
-#define portTHUMB_MODE_BIT              ( ( StackType_t ) 0x20 )
-#define portINSTRUCTION_SIZE            ( ( StackType_t ) 4 )
-#define portNO_CRITICAL_SECTION_NESTING ( ( StackType_t ) 0 )
+#define portINITIAL_SPSR                   ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT                 ( ( StackType_t ) 0x20 )
+#define portINSTRUCTION_SIZE               ( ( StackType_t ) 4 )
+#define portNO_CRITICAL_SECTION_NESTING    ( ( StackType_t ) 0 )
 
 /* Constants required to setup the tick ISR. */
-#define portENABLE_TIMER                ( ( uint8_t ) 0x01 )
-#define portPRESCALE_VALUE              0x00
-#define portINTERRUPT_ON_MATCH          ( ( uint32_t ) 0x01 )
-#define portRESET_COUNT_ON_MATCH        ( ( uint32_t ) 0x02 )
+#define portENABLE_TIMER                   ( ( uint8_t ) 0x01 )
+#define portPRESCALE_VALUE                 0x00
+#define portINTERRUPT_ON_MATCH             ( ( uint32_t ) 0x01 )
+#define portRESET_COUNT_ON_MATCH           ( ( uint32_t ) 0x02 )
 
 /* Constants required to setup the VIC for the tick ISR. */
-#define portTIMER_VIC_CHANNEL           ( ( uint32_t ) 0x0004 )
-#define portTIMER_VIC_CHANNEL_BIT       ( ( uint32_t ) 0x0010 )
-#define portTIMER_VIC_ENABLE            ( ( uint32_t ) 0x0020 )
+#define portTIMER_VIC_CHANNEL              ( ( uint32_t ) 0x0004 )
+#define portTIMER_VIC_CHANNEL_BIT          ( ( uint32_t ) 0x0010 )
+#define portTIMER_VIC_ENABLE               ( ( uint32_t ) 0x0020 )
 
 /*-----------------------------------------------------------*/
 
@@ -79,61 +79,63 @@ extern void vPortISRStartFirstTask( void );
  *
  * See header file for description.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
-StackType_t *pxOriginalTOS;
+    StackType_t * pxOriginalTOS;
 
     pxOriginalTOS = pxTopOfStack;
 
     /* To ensure asserts in tasks.c don't fail, although in this case the assert
-    is not really required. */
+     * is not really required. */
     pxTopOfStack--;
 
     /* Setup the initial stack of the task.  The stack is set exactly as
-    expected by the portRESTORE_CONTEXT() macro. */
+     * expected by the portRESTORE_CONTEXT() macro. */
 
     /* First on the stack is the return address - which in this case is the
-    start of the task.  The offset is added to make the return address appear
-    as it would within an IRQ ISR. */
+     * start of the task.  The offset is added to make the return address appear
+     * as it would within an IRQ ISR. */
     *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
     pxTopOfStack--;
 
-    *pxTopOfStack = ( StackType_t ) 0x00000000; /* R14 */
+    *pxTopOfStack = ( StackType_t ) 0x00000000;    /* R14 */
     pxTopOfStack--;
     *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
+    *pxTopOfStack = ( StackType_t ) 0x12121212;    /* R12 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
+    *pxTopOfStack = ( StackType_t ) 0x11111111;    /* R11 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
+    *pxTopOfStack = ( StackType_t ) 0x10101010;    /* R10 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
+    *pxTopOfStack = ( StackType_t ) 0x09090909;    /* R9 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
+    *pxTopOfStack = ( StackType_t ) 0x08080808;    /* R8 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
+    *pxTopOfStack = ( StackType_t ) 0x07070707;    /* R7 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
+    *pxTopOfStack = ( StackType_t ) 0x06060606;    /* R6 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
+    *pxTopOfStack = ( StackType_t ) 0x05050505;    /* R5 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
+    *pxTopOfStack = ( StackType_t ) 0x04040404;    /* R4 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
+    *pxTopOfStack = ( StackType_t ) 0x03030303;    /* R3 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
+    *pxTopOfStack = ( StackType_t ) 0x02020202;    /* R2 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
+    *pxTopOfStack = ( StackType_t ) 0x01010101;    /* R1 */
     pxTopOfStack--;
 
     /* When the task starts is will expect to find the function parameter in
-    R0. */
+     * R0. */
     *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
     pxTopOfStack--;
 
     /* The last thing onto the stack is the status register, which is set for
-    system mode, with interrupts enabled. */
+     * system mode, with interrupts enabled. */
     *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
 
     if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00 )
@@ -145,9 +147,9 @@ StackType_t *pxOriginalTOS;
     pxTopOfStack--;
 
     /* Some optimisation levels use the stack differently to others.  This
-    means the interrupt flags cannot always be stored on the stack and will
-    instead be stored in a variable, which is then saved as part of the
-    tasks context. */
+     * means the interrupt flags cannot always be stored on the stack and will
+     * instead be stored in a variable, which is then saved as part of the
+     * tasks context. */
     *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
 
     return pxTopOfStack;
@@ -157,7 +159,7 @@ StackType_t *pxOriginalTOS;
 BaseType_t xPortStartScheduler( void )
 {
     /* Start the timer that generates the tick ISR.  Interrupts are disabled
-    here already. */
+     * here already. */
     prvSetupTimerInterrupt();
 
     /* Start the first task. */
@@ -171,7 +173,7 @@ BaseType_t xPortStartScheduler( void )
 void vPortEndScheduler( void )
 {
     /* It is unlikely that the ARM port will require this function as there
-    is nothing to return to.  */
+     * is nothing to return to.  */
 }
 /*-----------------------------------------------------------*/
 
@@ -180,21 +182,21 @@ void vPortEndScheduler( void )
  */
 static void prvSetupTimerInterrupt( void )
 {
-uint32_t ulCompareMatch;
+    uint32_t ulCompareMatch;
 
-    PCLKSEL0 = (PCLKSEL0 & (~(0x3<<2))) | (0x01 << 2);
-    T0TCR  = 2;         /* Stop and reset the timer */
-    T0CTCR = 0;         /* Timer mode               */
+    PCLKSEL0 = ( PCLKSEL0 & ( ~( 0x3 << 2 ) ) ) | ( 0x01 << 2 );
+    T0TCR = 2;  /* Stop and reset the timer */
+    T0CTCR = 0; /* Timer mode               */
 
     /* A 1ms tick does not require the use of the timer prescale.  This is
-    defaulted to zero but can be used if necessary. */
+     * defaulted to zero but can be used if necessary. */
     T0PR = portPRESCALE_VALUE;
 
     /* Calculate the match value required for our wanted tick rate. */
     ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
 
     /* Protect against divide by zero.  Using an if() statement still results
-    in a warning - hence the #if. */
+     * in a warning - hence the #if. */
     #if portPRESCALE_VALUE != 0
     {
         ulCompareMatch /= ( portPRESCALE_VALUE + 1 );
@@ -203,21 +205,21 @@ uint32_t ulCompareMatch;
     T0MR1 = ulCompareMatch;
 
     /* Generate tick with timer 0 compare match. */
-    T0MCR  = (3 << 3);  /* Reset timer on match and generate interrupt */
+    T0MCR = ( 3 << 3 ); /* Reset timer on match and generate interrupt */
 
     /* Setup the VIC for the timer. */
     VICIntEnable = 0x00000010;
 
     /* The ISR installed depends on whether the preemptive or cooperative
-    scheduler is being used. */
+     * scheduler is being used. */
     #if configUSE_PREEMPTION == 1
     {
-        extern void ( vPreemptiveTick )( void );
+        extern void( vPreemptiveTick )( void );
         VICVectAddr4 = ( int32_t ) vPreemptiveTick;
     }
     #else
     {
-        extern void ( vNonPreemptiveTick )( void );
+        extern void( vNonPreemptiveTick )( void );
         VICVectAddr4 = ( int32_t ) vNonPreemptiveTick;
     }
     #endif
@@ -225,7 +227,7 @@ uint32_t ulCompareMatch;
     VICVectCntl4 = 1;
 
     /* Start the timer - interrupts are disabled when this function is called
-    so it is okay to do this here. */
+     * so it is okay to do this here. */
     T0TCR = portENABLE_TIMER;
 }
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM7_LPC23xx/portISR.c b/portable/GCC/ARM7_LPC23xx/portISR.c
index a3279d286..4fc549aca 100644
--- a/portable/GCC/ARM7_LPC23xx/portISR.c
+++ b/portable/GCC/ARM7_LPC23xx/portISR.c
@@ -28,27 +28,27 @@
 
 
 /*-----------------------------------------------------------
- * Components that can be compiled to either ARM or THUMB mode are
- * contained in port.c  The ISR routines, which can only be compiled
- * to ARM mode, are contained in this file.
- *----------------------------------------------------------*/
+* Components that can be compiled to either ARM or THUMB mode are
+* contained in port.c  The ISR routines, which can only be compiled
+* to ARM mode, are contained in this file.
+*----------------------------------------------------------*/
 
 /* Scheduler includes. */
 #include "FreeRTOS.h"
 #include "task.h"
 
 /* Constants required to handle interrupts. */
-#define portTIMER_MATCH_ISR_BIT     ( ( uint8_t ) 0x01 )
-#define portCLEAR_VIC_INTERRUPT     ( ( uint32_t ) 0 )
+#define portTIMER_MATCH_ISR_BIT    ( ( uint8_t ) 0x01 )
+#define portCLEAR_VIC_INTERRUPT    ( ( uint32_t ) 0 )
 
 /* Constants required to handle critical sections. */
-#define portNO_CRITICAL_NESTING     ( ( uint32_t ) 0 )
+#define portNO_CRITICAL_NESTING    ( ( uint32_t ) 0 )
 volatile uint32_t ulCriticalNesting = 9999UL;
 
 /*-----------------------------------------------------------*/
 
 /* ISR to handle manual context switches (from a call to taskYIELD()). */
-void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked));
+void vPortYieldProcessor( void ) __attribute__( ( interrupt( "SWI" ), naked ) );
 
 /*
  * The scheduler can only be started from ARM mode, hence the inclusion of this
@@ -60,7 +60,7 @@ void vPortISRStartFirstTask( void );
 void vPortISRStartFirstTask( void )
 {
     /* Simply start the scheduler.  This is included here as it can only be
-    called from ARM mode. */
+     * called from ARM mode. */
     portRESTORE_CONTEXT();
 }
 /*-----------------------------------------------------------*/
@@ -76,15 +76,15 @@ void vPortISRStartFirstTask( void )
 void vPortYieldProcessor( void )
 {
     /* Within an IRQ ISR the link register has an offset from the true return
-    address, but an SWI ISR does not.  Add the offset manually so the same
-    ISR return code can be used in both cases. */
+     * address, but an SWI ISR does not.  Add the offset manually so the same
+     * ISR return code can be used in both cases. */
     __asm volatile ( "ADD       LR, LR, #4" );
 
     /* Perform the context switch.  First save the context of the current task. */
     portSAVE_CONTEXT();
 
     /* Find the highest priority task that is ready to run. */
-    __asm volatile( "bl         vTaskSwitchContext" );
+    __asm volatile ( "bl         vTaskSwitchContext" );
 
     /* Restore the context of the new task. */
     portRESTORE_CONTEXT();
@@ -99,9 +99,9 @@ void vPortYieldProcessor( void )
 
 #if configUSE_PREEMPTION == 0
 
-    /* The cooperative scheduler requires a normal IRQ service routine to
-    simply increment the system tick. */
-    void vNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ")));
+/* The cooperative scheduler requires a normal IRQ service routine to
+ * simply increment the system tick. */
+    void vNonPreemptiveTick( void ) __attribute__( ( interrupt( "IRQ" ) ) );
     void vNonPreemptiveTick( void )
     {
         xTaskIncrementTick();
@@ -109,18 +109,18 @@ void vPortYieldProcessor( void )
         VICVectAddr = portCLEAR_VIC_INTERRUPT;
     }
 
-#else
+#else /* if configUSE_PREEMPTION == 0 */
 
-    /* The preemptive scheduler is defined as "naked" as the full context is
-    saved on entry as part of the context switch. */
-    void vPreemptiveTick( void ) __attribute__((naked));
+/* The preemptive scheduler is defined as "naked" as the full context is
+ * saved on entry as part of the context switch. */
+    void vPreemptiveTick( void ) __attribute__( ( naked ) );
     void vPreemptiveTick( void )
     {
         /* Save the context of the interrupted task. */
         portSAVE_CONTEXT();
 
         /* Increment the RTOS tick count, then look for the highest priority
-        task that is ready to run. */
+         * task that is ready to run. */
         __asm volatile
         (
             "   bl xTaskIncrementTick   \t\n" \
@@ -138,7 +138,7 @@ void vPortYieldProcessor( void )
         portRESTORE_CONTEXT();
     }
 
-#endif
+#endif /* if configUSE_PREEMPTION == 0 */
 /*-----------------------------------------------------------*/
 
 /*
@@ -149,50 +149,50 @@ void vPortYieldProcessor( void )
  */
 #ifdef THUMB_INTERWORK
 
-    void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
-    void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
+    void vPortDisableInterruptsFromThumb( void ) __attribute__( ( naked ) );
+    void vPortEnableInterruptsFromThumb( void ) __attribute__( ( naked ) );
 
     void vPortDisableInterruptsFromThumb( void )
     {
         __asm volatile (
-            "STMDB  SP!, {R0}       \n\t"   /* Push R0.                                 */
-            "MRS    R0, CPSR        \n\t"   /* Get CPSR.                                */
-            "ORR    R0, R0, #0xC0   \n\t"   /* Disable IRQ, FIQ.                        */
-            "MSR    CPSR, R0        \n\t"   /* Write back modified value.               */
-            "LDMIA  SP!, {R0}       \n\t"   /* Pop R0.                                  */
-            "BX     R14" );                 /* Return back to thumb.                    */
+            "STMDB  SP!, {R0}       \n\t" /* Push R0.                                 */
+            "MRS    R0, CPSR        \n\t" /* Get CPSR.                                */
+            "ORR    R0, R0, #0xC0   \n\t" /* Disable IRQ, FIQ.                        */
+            "MSR    CPSR, R0        \n\t" /* Write back modified value.               */
+            "LDMIA  SP!, {R0}       \n\t" /* Pop R0.                                  */
+            "BX     R14" );               /* Return back to thumb.                    */
     }
 
     void vPortEnableInterruptsFromThumb( void )
     {
         __asm volatile (
-            "STMDB  SP!, {R0}       \n\t"   /* Push R0.                                 */
-            "MRS    R0, CPSR        \n\t"   /* Get CPSR.                                */
-            "BIC    R0, R0, #0xC0   \n\t"   /* Enable IRQ, FIQ.                         */
-            "MSR    CPSR, R0        \n\t"   /* Write back modified value.               */
-            "LDMIA  SP!, {R0}       \n\t"   /* Pop R0.                                  */
-            "BX     R14" );                 /* Return back to thumb.                    */
+            "STMDB  SP!, {R0}       \n\t" /* Push R0.                                 */
+            "MRS    R0, CPSR        \n\t" /* Get CPSR.                                */
+            "BIC    R0, R0, #0xC0   \n\t" /* Enable IRQ, FIQ.                         */
+            "MSR    CPSR, R0        \n\t" /* Write back modified value.               */
+            "LDMIA  SP!, {R0}       \n\t" /* Pop R0.                                  */
+            "BX     R14" );               /* Return back to thumb.                    */
     }
 
 #endif /* THUMB_INTERWORK */
 
 /* The code generated by the GCC compiler uses the stack in different ways at
-different optimisation levels.  The interrupt flags can therefore not always
-be saved to the stack.  Instead the critical section nesting level is stored
-in a variable, which is then saved as part of the stack context. */
+ * different optimisation levels.  The interrupt flags can therefore not always
+ * be saved to the stack.  Instead the critical section nesting level is stored
+ * in a variable, which is then saved as part of the stack context. */
 void vPortEnterCritical( void )
 {
     /* Disable interrupts as per portDISABLE_INTERRUPTS();                          */
     __asm volatile (
-        "STMDB  SP!, {R0}           \n\t"   /* Push R0.                             */
-        "MRS    R0, CPSR            \n\t"   /* Get CPSR.                            */
-        "ORR    R0, R0, #0xC0       \n\t"   /* Disable IRQ, FIQ.                    */
-        "MSR    CPSR, R0            \n\t"   /* Write back modified value.           */
-        "LDMIA  SP!, {R0}" );               /* Pop R0.                              */
+        "STMDB  SP!, {R0}           \n\t" /* Push R0.                             */
+        "MRS    R0, CPSR            \n\t" /* Get CPSR.                            */
+        "ORR    R0, R0, #0xC0       \n\t" /* Disable IRQ, FIQ.                    */
+        "MSR    CPSR, R0            \n\t" /* Write back modified value.           */
+        "LDMIA  SP!, {R0}" );             /* Pop R0.                              */
 
-    /* Now interrupts are disabled ulCriticalNesting can be accessed
-    directly.  Increment ulCriticalNesting to keep a count of how many times
-    portENTER_CRITICAL() has been called. */
+    /* Now that interrupts are disabled, ulCriticalNesting can be accessed
+     * directly.  Increment ulCriticalNesting to keep a count of how many times
+     * portENTER_CRITICAL() has been called. */
     ulCriticalNesting++;
 }
 
@@ -204,16 +204,16 @@ void vPortExitCritical( void )
         ulCriticalNesting--;
 
         /* If the nesting level has reached zero then interrupts should be
-        re-enabled. */
+         * re-enabled. */
         if( ulCriticalNesting == portNO_CRITICAL_NESTING )
         {
             /* Enable interrupts as per portEXIT_CRITICAL().                    */
             __asm volatile (
-                "STMDB  SP!, {R0}       \n\t"   /* Push R0.                     */
-                "MRS    R0, CPSR        \n\t"   /* Get CPSR.                    */
-                "BIC    R0, R0, #0xC0   \n\t"   /* Enable IRQ, FIQ.             */
-                "MSR    CPSR, R0        \n\t"   /* Write back modified value.   */
-                "LDMIA  SP!, {R0}" );           /* Pop R0.                      */
+                "STMDB  SP!, {R0}       \n\t" /* Push R0.                     */
+                "MRS    R0, CPSR        \n\t" /* Get CPSR.                    */
+                "BIC    R0, R0, #0xC0   \n\t" /* Enable IRQ, FIQ.             */
+                "MSR    CPSR, R0        \n\t" /* Write back modified value.   */
+                "LDMIA  SP!, {R0}" );         /* Pop R0.                      */
         }
     }
 }
diff --git a/portable/GCC/ARM7_LPC23xx/portmacro.h b/portable/GCC/ARM7_LPC23xx/portmacro.h
index f60cdde53..5b78481e3 100644
--- a/portable/GCC/ARM7_LPC23xx/portmacro.h
+++ b/portable/GCC/ARM7_LPC23xx/portmacro.h
@@ -27,27 +27,27 @@
  */
 
 /*
-    Changes from V3.2.3
-
-    + Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1.
-
-    Changes from V3.2.4
-
-    + Removed the use of the %0 parameter within the assembler macros and
-      replaced them with hard coded registers.  This will ensure the
-      assembler does not select the link register as the temp register as
-      was occasionally happening previously.
-
-    + The assembler statements are now included in a single asm block rather
-      than each line having its own asm block.
-
-    Changes from V4.5.0
-
-    + Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros
-      and replaced them with portYIELD_FROM_ISR() macro.  Application code
-      should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT()
-      macros as per the V4.5.1 demo code.
-*/
+ *  Changes from V3.2.3
+ *
+ + Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1.
+ +
+ +  Changes from V3.2.4
+ +
+ + Removed the use of the %0 parameter within the assembler macros and
+ +    replaced them with hard coded registers.  This will ensure the
+ +    assembler does not select the link register as the temp register as
+ +    was occasionally happening previously.
+ +
+ + The assembler statements are now included in a single asm block rather
+ +    than each line having its own asm block.
+ +
+ +  Changes from V4.5.0
+ +
+ + Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros
+ +    and replaced them with portYIELD_FROM_ISR() macro.  Application code
+ +    should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT()
+ +    macros as per the V4.5.1 demo code.
+ */
 
 #ifndef PORTMACRO_H
 #define PORTMACRO_H
@@ -69,34 +69,34 @@
  */
 
 /* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint32_t
-#define portBASE_TYPE   portLONG
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     portLONG
 
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY ( TickType_t )    ( 0xFFFFFFFFUL )
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) ( 0xFFFFFFFFUL )
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
 /*-----------------------------------------------------------*/
 
 /* Architecture specifics. */
-#define portSTACK_GROWTH            ( -1 )
-#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT          8
-#define portNOP()                   __asm volatile ( "NOP" );
+#define portSTACK_GROWTH      ( -1 )
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT    8
+#define portNOP()    __asm volatile ( "NOP" );
 /*-----------------------------------------------------------*/
 
 
@@ -109,92 +109,92 @@ typedef unsigned long UBaseType_t;
  * THUMB mode code will result in a compile time error.
  */
 
-#define portRESTORE_CONTEXT()                                           \
-{                                                                       \
-extern volatile void * volatile pxCurrentTCB;                           \
-extern volatile uint32_t ulCriticalNesting;                 \
-                                                                        \
-    /* Set the LR to the task stack. */                                 \
-    __asm volatile (                                                    \
-    "LDR        R0, =pxCurrentTCB                               \n\t"   \
-    "LDR        R0, [R0]                                        \n\t"   \
-    "LDR        LR, [R0]                                        \n\t"   \
-                                                                        \
-    /* The critical nesting depth is the first item on the stack. */    \
-    /* Load it into the ulCriticalNesting variable. */                  \
-    "LDR        R0, =ulCriticalNesting                          \n\t"   \
-    "LDMFD  LR!, {R1}                                           \n\t"   \
-    "STR        R1, [R0]                                        \n\t"   \
-                                                                        \
-    /* Get the SPSR from the stack. */                                  \
-    "LDMFD  LR!, {R0}                                           \n\t"   \
-    "MSR        SPSR, R0                                        \n\t"   \
-                                                                        \
-    /* Restore all system mode registers for the task. */               \
-    "LDMFD  LR, {R0-R14}^                                       \n\t"   \
-    "NOP                                                        \n\t"   \
-                                                                        \
-    /* Restore the return address. */                                   \
-    "LDR        LR, [LR, #+60]                                  \n\t"   \
-                                                                        \
-    /* And return - correcting the offset in the LR to obtain the */    \
-    /* correct address. */                                              \
-    "SUBS   PC, LR, #4                                          \n\t"   \
-    );                                                                  \
-    ( void ) ulCriticalNesting;                                         \
-    ( void ) pxCurrentTCB;                                              \
-}
+#define portRESTORE_CONTEXT()                                                 \
+    {                                                                         \
+        extern volatile void * volatile pxCurrentTCB;                         \
+        extern volatile uint32_t ulCriticalNesting;                           \
+                                                                              \
+        /* Set the LR to the task stack. */                                   \
+        __asm volatile (                                                      \
+            "LDR        R0, =pxCurrentTCB                               \n\t" \
+            "LDR        R0, [R0]                                        \n\t" \
+            "LDR        LR, [R0]                                        \n\t" \
+                                                                              \
+            /* The critical nesting depth is the first item on the stack. */  \
+            /* Load it into the ulCriticalNesting variable. */                \
+            "LDR        R0, =ulCriticalNesting                          \n\t" \
+            "LDMFD  LR!, {R1}                                           \n\t" \
+            "STR        R1, [R0]                                        \n\t" \
+                                                                              \
+            /* Get the SPSR from the stack. */                                \
+            "LDMFD  LR!, {R0}                                           \n\t" \
+            "MSR        SPSR, R0                                        \n\t" \
+                                                                              \
+            /* Restore all system mode registers for the task. */             \
+            "LDMFD  LR, {R0-R14}^                                       \n\t" \
+            "NOP                                                        \n\t" \
+                                                                              \
+            /* Restore the return address. */                                 \
+            "LDR        LR, [LR, #+60]                                  \n\t" \
+                                                                              \
+            /* And return - correcting the offset in the LR to obtain the */  \
+            /* correct address. */                                            \
+            "SUBS   PC, LR, #4                                          \n\t" \
+            );                                                                \
+        ( void ) ulCriticalNesting;                                           \
+        ( void ) pxCurrentTCB;                                                \
+    }
 /*-----------------------------------------------------------*/
 
-#define portSAVE_CONTEXT()                                              \
-{                                                                       \
-extern volatile void * volatile pxCurrentTCB;                           \
-extern volatile uint32_t ulCriticalNesting;                 \
-                                                                        \
-    /* Push R0 as we are going to use the register. */                  \
-    __asm volatile (                                                    \
-    "STMDB  SP!, {R0}                                           \n\t"   \
-                                                                        \
-    /* Set R0 to point to the task stack pointer. */                    \
-    "STMDB  SP,{SP}^                                            \n\t"   \
-    "NOP                                                        \n\t"   \
-    "SUB    SP, SP, #4                                          \n\t"   \
-    "LDMIA  SP!,{R0}                                            \n\t"   \
-                                                                        \
-    /* Push the return address onto the stack. */                       \
-    "STMDB  R0!, {LR}                                           \n\t"   \
-                                                                        \
-    /* Now we have saved LR we can use it instead of R0. */             \
-    "MOV    LR, R0                                              \n\t"   \
-                                                                        \
-    /* Pop R0 so we can save it onto the system mode stack. */          \
-    "LDMIA  SP!, {R0}                                           \n\t"   \
-                                                                        \
-    /* Push all the system mode registers onto the task stack. */       \
-    "STMDB  LR,{R0-LR}^                                         \n\t"   \
-    "NOP                                                        \n\t"   \
-    "SUB    LR, LR, #60                                         \n\t"   \
-                                                                        \
-    /* Push the SPSR onto the task stack. */                            \
-    "MRS    R0, SPSR                                            \n\t"   \
-    "STMDB  LR!, {R0}                                           \n\t"   \
-                                                                        \
-    "LDR    R0, =ulCriticalNesting                              \n\t"   \
-    "LDR    R0, [R0]                                            \n\t"   \
-    "STMDB  LR!, {R0}                                           \n\t"   \
-                                                                        \
-    /* Store the new top of stack for the task. */                      \
-    "LDR    R0, =pxCurrentTCB                                   \n\t"   \
-    "LDR    R0, [R0]                                            \n\t"   \
-    "STR    LR, [R0]                                            \n\t"   \
-    );                                                                  \
-    ( void ) ulCriticalNesting;                                         \
-    ( void ) pxCurrentTCB;                                              \
-}
+#define portSAVE_CONTEXT()                                                    \
+    {                                                                         \
+        extern volatile void * volatile pxCurrentTCB;                         \
+        extern volatile uint32_t ulCriticalNesting;                           \
+                                                                              \
+        /* Push R0 as we are going to use the register. */                    \
+        __asm volatile (                                                      \
+            "STMDB  SP!, {R0}                                           \n\t" \
+                                                                              \
+            /* Set R0 to point to the task stack pointer. */                  \
+            "STMDB  SP,{SP}^                                            \n\t" \
+            "NOP                                                        \n\t" \
+            "SUB    SP, SP, #4                                          \n\t" \
+            "LDMIA  SP!,{R0}                                            \n\t" \
+                                                                              \
+            /* Push the return address onto the stack. */                     \
+            "STMDB  R0!, {LR}                                           \n\t" \
+                                                                              \
+            /* Now we have saved LR we can use it instead of R0. */           \
+            "MOV    LR, R0                                              \n\t" \
+                                                                              \
+            /* Pop R0 so we can save it onto the system mode stack. */        \
+            "LDMIA  SP!, {R0}                                           \n\t" \
+                                                                              \
+            /* Push all the system mode registers onto the task stack. */     \
+            "STMDB  LR,{R0-LR}^                                         \n\t" \
+            "NOP                                                        \n\t" \
+            "SUB    LR, LR, #60                                         \n\t" \
+                                                                              \
+            /* Push the SPSR onto the task stack. */                          \
+            "MRS    R0, SPSR                                            \n\t" \
+            "STMDB  LR!, {R0}                                           \n\t" \
+                                                                              \
+            "LDR    R0, =ulCriticalNesting                              \n\t" \
+            "LDR    R0, [R0]                                            \n\t" \
+            "STMDB  LR!, {R0}                                           \n\t" \
+                                                                              \
+            /* Store the new top of stack for the task. */                    \
+            "LDR    R0, =pxCurrentTCB                                   \n\t" \
+            "LDR    R0, [R0]                                            \n\t" \
+            "STR    LR, [R0]                                            \n\t" \
+            );                                                                \
+        ( void ) ulCriticalNesting;                                           \
+        ( void ) pxCurrentTCB;                                                \
+    }
 
 
-#define portYIELD_FROM_ISR()        vTaskSwitchContext()
-#define portYIELD()                 __asm volatile ( "SWI 0" )
+#define portYIELD_FROM_ISR()    vTaskSwitchContext()
+#define portYIELD()             __asm volatile ( "SWI 0" )
 /*-----------------------------------------------------------*/
 
 
@@ -209,42 +209,42 @@ extern volatile uint32_t ulCriticalNesting;                 \
 
 #ifdef THUMB_INTERWORK
 
-    extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
-    extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
+    extern void vPortDisableInterruptsFromThumb( void ) __attribute__( ( naked ) );
+    extern void vPortEnableInterruptsFromThumb( void ) __attribute__( ( naked ) );
 
     #define portDISABLE_INTERRUPTS()    vPortDisableInterruptsFromThumb()
     #define portENABLE_INTERRUPTS()     vPortEnableInterruptsFromThumb()
 
 #else
 
-    #define portDISABLE_INTERRUPTS()                                            \
-        __asm volatile (                                                            \
-            "STMDB  SP!, {R0}       \n\t"   /* Push R0.                     */  \
-            "MRS    R0, CPSR        \n\t"   /* Get CPSR.                    */  \
-            "ORR    R0, R0, #0xC0   \n\t"   /* Disable IRQ, FIQ.            */  \
-            "MSR    CPSR, R0        \n\t"   /* Write back modified value.   */  \
-            "LDMIA  SP!, {R0}           " ) /* Pop R0.                      */
+    #define portDISABLE_INTERRUPTS()                                       \
+    __asm volatile (                                                       \
+        "STMDB  SP!, {R0}       \n\t"   /* Push R0.                     */ \
+        "MRS    R0, CPSR        \n\t"   /* Get CPSR.                    */ \
+        "ORR    R0, R0, #0xC0   \n\t"   /* Disable IRQ, FIQ.            */ \
+        "MSR    CPSR, R0        \n\t"   /* Write back modified value.   */ \
+        "LDMIA  SP!, {R0}           " ) /* Pop R0.                      */
 
-    #define portENABLE_INTERRUPTS()                                             \
-        __asm volatile (                                                            \
-            "STMDB  SP!, {R0}       \n\t"   /* Push R0.                     */  \
-            "MRS    R0, CPSR        \n\t"   /* Get CPSR.                    */  \
-            "BIC    R0, R0, #0xC0   \n\t"   /* Enable IRQ, FIQ.             */  \
-            "MSR    CPSR, R0        \n\t"   /* Write back modified value.   */  \
-            "LDMIA  SP!, {R0}           " ) /* Pop R0.                      */
+    #define portENABLE_INTERRUPTS()                                        \
+    __asm volatile (                                                       \
+        "STMDB  SP!, {R0}       \n\t"   /* Push R0.                     */ \
+        "MRS    R0, CPSR        \n\t"   /* Get CPSR.                    */ \
+        "BIC    R0, R0, #0xC0   \n\t"   /* Enable IRQ, FIQ.             */ \
+        "MSR    CPSR, R0        \n\t"   /* Write back modified value.   */ \
+        "LDMIA  SP!, {R0}           " ) /* Pop R0.                      */
 
 #endif /* THUMB_INTERWORK */
 
 extern void vPortEnterCritical( void );
 extern void vPortExitCritical( void );
 
-#define portENTER_CRITICAL()        vPortEnterCritical();
-#define portEXIT_CRITICAL()         vPortExitCritical();
+#define portENTER_CRITICAL()    vPortEnterCritical();
+#define portEXIT_CRITICAL()     vPortExitCritical();
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/GCC/ARM_CA53_64_BIT/port.c b/portable/GCC/ARM_CA53_64_BIT/port.c
index 545bac15d..8c2af2dc7 100644
--- a/portable/GCC/ARM_CA53_64_BIT/port.c
+++ b/portable/GCC/ARM_CA53_64_BIT/port.c
@@ -34,104 +34,104 @@
 #include "task.h"
 
 #ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS
-    #error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+    #error "configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
 #endif
 
 #ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET
-    #error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+    #error "configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined.  See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
 #endif
 
 #ifndef configUNIQUE_INTERRUPT_PRIORITIES
-    #error configUNIQUE_INTERRUPT_PRIORITIES must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+    #error "configUNIQUE_INTERRUPT_PRIORITIES must be defined.  See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
 #endif
 
 #ifndef configSETUP_TICK_INTERRUPT
-    #error configSETUP_TICK_INTERRUPT() must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+    #error "configSETUP_TICK_INTERRUPT() must be defined.  See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
 #endif /* configSETUP_TICK_INTERRUPT */
 
 #ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
-    #error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+    #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be defined.  See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
 #endif
 
 #if configMAX_API_CALL_INTERRUPT_PRIORITY == 0
-    #error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0
+    #error "configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0"
 #endif
 
 #if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES
-    #error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority
+    #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority"
 #endif
 
 #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
     /* Check the configuration. */
-    #if( configMAX_PRIORITIES > 32 )
-        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+    #if ( configMAX_PRIORITIES > 32 )
+        #error "configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice."
     #endif
 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 
 /* In case security extensions are implemented. */
 #if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
-    #error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
+    #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )"
 #endif
 
 /* Some vendor specific files default configCLEAR_TICK_INTERRUPT() in
-portmacro.h. */
+ * portmacro.h. */
 #ifndef configCLEAR_TICK_INTERRUPT
     #define configCLEAR_TICK_INTERRUPT()
 #endif
 
 /* A critical section is exited when the critical section nesting count reaches
-this value. */
-#define portNO_CRITICAL_NESTING         ( ( size_t ) 0 )
+ * this value. */
+#define portNO_CRITICAL_NESTING          ( ( size_t ) 0 )
 
 /* In all GICs 255 can be written to the priority mask register to unmask all
-(but the lowest) interrupt priority. */
-#define portUNMASK_VALUE                ( 0xFFUL )
+ * (but the lowest) interrupt priority. */
+#define portUNMASK_VALUE                 ( 0xFFUL )
 
 /* Tasks are not created with a floating point context, but can be given a
-floating point context after they have been created.  A variable is stored as
-part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
-does not have an FPU context, or any other value if the task does have an FPU
-context. */
-#define portNO_FLOATING_POINT_CONTEXT   ( ( StackType_t ) 0 )
+ * floating point context after they have been created.  A variable is stored as
+ * part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
+ * does not have an FPU context, or any other value if the task does have an FPU
+ * context. */
+#define portNO_FLOATING_POINT_CONTEXT    ( ( StackType_t ) 0 )
 
 /* Constants required to setup the initial task context. */
-#define portSP_ELx                      ( ( StackType_t ) 0x01 )
-#define portSP_EL0                      ( ( StackType_t ) 0x00 )
+#define portSP_ELx                       ( ( StackType_t ) 0x01 )
+#define portSP_EL0                       ( ( StackType_t ) 0x00 )
 
 #if defined( GUEST )
-    #define portEL1                     ( ( StackType_t ) 0x04 )
-    #define portINITIAL_PSTATE              ( portEL1 | portSP_EL0 )
+    #define portEL1                      ( ( StackType_t ) 0x04 )
+    #define portINITIAL_PSTATE           ( portEL1 | portSP_EL0 )
 #else
-    #define portEL3                     ( ( StackType_t ) 0x0c )
+    #define portEL3                      ( ( StackType_t ) 0x0c )
     /* At the time of writing, the BSP only supports EL3. */
-    #define portINITIAL_PSTATE          ( portEL3 | portSP_EL0 )
+    #define portINITIAL_PSTATE           ( portEL3 | portSP_EL0 )
 #endif
 
 
 /* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary
-point is zero. */
-#define portBINARY_POINT_BITS           ( ( uint8_t ) 0x03 )
+ * point is zero. */
+#define portBINARY_POINT_BITS      ( ( uint8_t ) 0x03 )
 
 /* Masks all bits in the APSR other than the mode bits. */
-#define portAPSR_MODE_BITS_MASK         ( 0x0C )
+#define portAPSR_MODE_BITS_MASK    ( 0x0C )
 
 /* The I bit in the DAIF bits. */
-#define portDAIF_I                      ( 0x80 )
+#define portDAIF_I                 ( 0x80 )
 
 /* Macro to unmask all interrupt priorities. */
-#define portCLEAR_INTERRUPT_MASK()                                  \
-{                                                                   \
-    portDISABLE_INTERRUPTS();                                       \
-    portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE;           \
-    __asm volatile (    "DSB SY     \n"                             \
-                        "ISB SY     \n" );                          \
-    portENABLE_INTERRUPTS();                                        \
-}
+#define portCLEAR_INTERRUPT_MASK()                            \
+    {                                                         \
+        portDISABLE_INTERRUPTS();                             \
+        portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \
+        __asm volatile ( "DSB SY     \n"                      \
+                         "ISB SY     \n" );                   \
+        portENABLE_INTERRUPTS();                              \
+    }
 
 /* Hardware specifics used when sanity checking the configuration. */
-#define portINTERRUPT_PRIORITY_REGISTER_OFFSET      0x400UL
-#define portMAX_8_BIT_VALUE                         ( ( uint8_t ) 0xff )
-#define portBIT_0_SET                               ( ( uint8_t ) 0x01 )
+#define portINTERRUPT_PRIORITY_REGISTER_OFFSET    0x400UL
+#define portMAX_8_BIT_VALUE                       ( ( uint8_t ) 0xff )
+#define portBIT_0_SET                             ( ( uint8_t ) 0x01 )
 
 /*-----------------------------------------------------------*/
 
@@ -144,104 +144,106 @@ extern void vPortRestoreTaskContext( void );
 /*-----------------------------------------------------------*/
 
 /* A variable is used to keep track of the critical section nesting.  This
-variable has to be stored as part of the task context and must be initialised to
-a non zero value to ensure interrupts don't inadvertently become unmasked before
-the scheduler starts.  As it is stored as part of the task context it will
-automatically be set to 0 when the first task is started. */
+ * variable has to be stored as part of the task context and must be initialised to
+ * a non zero value to ensure interrupts don't inadvertently become unmasked before
+ * the scheduler starts.  As it is stored as part of the task context it will
+ * automatically be set to 0 when the first task is started. */
 volatile uint64_t ullCriticalNesting = 9999ULL;
 
 /* Saved as part of the task context.  If ullPortTaskHasFPUContext is non-zero
-then floating point context must be saved and restored for the task. */
+ * then floating point context must be saved and restored for the task. */
 uint64_t ullPortTaskHasFPUContext = pdFALSE;
 
 /* Set to 1 to pend a context switch from an ISR. */
 uint64_t ullPortYieldRequired = pdFALSE;
 
 /* Counts the interrupt nesting depth.  A context switch is only performed if
-if the nesting depth is 0. */
+ * if the nesting depth is 0. */
 uint64_t ullPortInterruptNesting = 0;
 
 /* Used in the ASM code. */
-__attribute__(( used )) const uint64_t ullICCEOIR = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS;
-__attribute__(( used )) const uint64_t ullICCIAR = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS;
-__attribute__(( used )) const uint64_t ullICCPMR = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS;
-__attribute__(( used )) const uint64_t ullMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
+__attribute__( ( used ) ) const uint64_t ullICCEOIR = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS;
+__attribute__( ( used ) ) const uint64_t ullICCIAR = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS;
+__attribute__( ( used ) ) const uint64_t ullICCPMR = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS;
+__attribute__( ( used ) ) const uint64_t ullMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
 
 /*-----------------------------------------------------------*/
 
 /*
  * See header file for description.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
     /* Setup the initial stack of the task.  The stack is set exactly as
-    expected by the portRESTORE_CONTEXT() macro. */
+     * expected by the portRESTORE_CONTEXT() macro. */
 
     /* First all the general purpose registers. */
     pxTopOfStack--;
-    *pxTopOfStack = 0x0101010101010101ULL;  /* R1 */
+    *pxTopOfStack = 0x0101010101010101ULL;        /* R1 */
     pxTopOfStack--;
     *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
     pxTopOfStack--;
-    *pxTopOfStack = 0x0303030303030303ULL;  /* R3 */
+    *pxTopOfStack = 0x0303030303030303ULL;        /* R3 */
     pxTopOfStack--;
-    *pxTopOfStack = 0x0202020202020202ULL;  /* R2 */
+    *pxTopOfStack = 0x0202020202020202ULL;        /* R2 */
     pxTopOfStack--;
-    *pxTopOfStack = 0x0505050505050505ULL;  /* R5 */
+    *pxTopOfStack = 0x0505050505050505ULL;        /* R5 */
     pxTopOfStack--;
-    *pxTopOfStack = 0x0404040404040404ULL;  /* R4 */
+    *pxTopOfStack = 0x0404040404040404ULL;        /* R4 */
     pxTopOfStack--;
-    *pxTopOfStack = 0x0707070707070707ULL;  /* R7 */
+    *pxTopOfStack = 0x0707070707070707ULL;        /* R7 */
     pxTopOfStack--;
-    *pxTopOfStack = 0x0606060606060606ULL;  /* R6 */
+    *pxTopOfStack = 0x0606060606060606ULL;        /* R6 */
     pxTopOfStack--;
-    *pxTopOfStack = 0x0909090909090909ULL;  /* R9 */
+    *pxTopOfStack = 0x0909090909090909ULL;        /* R9 */
     pxTopOfStack--;
-    *pxTopOfStack = 0x0808080808080808ULL;  /* R8 */
+    *pxTopOfStack = 0x0808080808080808ULL;        /* R8 */
     pxTopOfStack--;
-    *pxTopOfStack = 0x1111111111111111ULL;  /* R11 */
+    *pxTopOfStack = 0x1111111111111111ULL;        /* R11 */
     pxTopOfStack--;
-    *pxTopOfStack = 0x1010101010101010ULL;  /* R10 */
+    *pxTopOfStack = 0x1010101010101010ULL;        /* R10 */
     pxTopOfStack--;
-    *pxTopOfStack = 0x1313131313131313ULL;  /* R13 */
+    *pxTopOfStack = 0x1313131313131313ULL;        /* R13 */
     pxTopOfStack--;
-    *pxTopOfStack = 0x1212121212121212ULL;  /* R12 */
+    *pxTopOfStack = 0x1212121212121212ULL;        /* R12 */
     pxTopOfStack--;
-    *pxTopOfStack = 0x1515151515151515ULL;  /* R15 */
+    *pxTopOfStack = 0x1515151515151515ULL;        /* R15 */
     pxTopOfStack--;
-    *pxTopOfStack = 0x1414141414141414ULL;  /* R14 */
+    *pxTopOfStack = 0x1414141414141414ULL;        /* R14 */
     pxTopOfStack--;
-    *pxTopOfStack = 0x1717171717171717ULL;  /* R17 */
+    *pxTopOfStack = 0x1717171717171717ULL;        /* R17 */
     pxTopOfStack--;
-    *pxTopOfStack = 0x1616161616161616ULL;  /* R16 */
+    *pxTopOfStack = 0x1616161616161616ULL;        /* R16 */
     pxTopOfStack--;
-    *pxTopOfStack = 0x1919191919191919ULL;  /* R19 */
+    *pxTopOfStack = 0x1919191919191919ULL;        /* R19 */
     pxTopOfStack--;
-    *pxTopOfStack = 0x1818181818181818ULL;  /* R18 */
+    *pxTopOfStack = 0x1818181818181818ULL;        /* R18 */
     pxTopOfStack--;
-    *pxTopOfStack = 0x2121212121212121ULL;  /* R21 */
+    *pxTopOfStack = 0x2121212121212121ULL;        /* R21 */
     pxTopOfStack--;
-    *pxTopOfStack = 0x2020202020202020ULL;  /* R20 */
+    *pxTopOfStack = 0x2020202020202020ULL;        /* R20 */
     pxTopOfStack--;
-    *pxTopOfStack = 0x2323232323232323ULL;  /* R23 */
+    *pxTopOfStack = 0x2323232323232323ULL;        /* R23 */
     pxTopOfStack--;
-    *pxTopOfStack = 0x2222222222222222ULL;  /* R22 */
+    *pxTopOfStack = 0x2222222222222222ULL;        /* R22 */
     pxTopOfStack--;
-    *pxTopOfStack = 0x2525252525252525ULL;  /* R25 */
+    *pxTopOfStack = 0x2525252525252525ULL;        /* R25 */
     pxTopOfStack--;
-    *pxTopOfStack = 0x2424242424242424ULL;  /* R24 */
+    *pxTopOfStack = 0x2424242424242424ULL;        /* R24 */
     pxTopOfStack--;
-    *pxTopOfStack = 0x2727272727272727ULL;  /* R27 */
+    *pxTopOfStack = 0x2727272727272727ULL;        /* R27 */
     pxTopOfStack--;
-    *pxTopOfStack = 0x2626262626262626ULL;  /* R26 */
+    *pxTopOfStack = 0x2626262626262626ULL;        /* R26 */
     pxTopOfStack--;
-    *pxTopOfStack = 0x2929292929292929ULL;  /* R29 */
+    *pxTopOfStack = 0x2929292929292929ULL;        /* R29 */
     pxTopOfStack--;
-    *pxTopOfStack = 0x2828282828282828ULL;  /* R28 */
+    *pxTopOfStack = 0x2828282828282828ULL;        /* R28 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x00;   /* XZR - has no effect, used so there are an even number of registers. */
+    *pxTopOfStack = ( StackType_t ) 0x00;         /* XZR - has no effect, used so there are an even number of registers. */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x00;   /* R30 - procedure call link register. */
+    *pxTopOfStack = ( StackType_t ) 0x00;         /* R30 - procedure call link register. */
     pxTopOfStack--;
 
     *pxTopOfStack = portINITIAL_PSTATE;
@@ -251,13 +253,13 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
     pxTopOfStack--;
 
     /* The task will start with a critical nesting count of 0 as interrupts are
-    enabled. */
+     * enabled. */
     *pxTopOfStack = portNO_CRITICAL_NESTING;
     pxTopOfStack--;
 
     /* The task will start without a floating point context.  A task that uses
-    the floating point hardware must call vPortTaskUsesFPU() before executing
-    any floating point instructions. */
+     * the floating point hardware must call vPortTaskUsesFPU() before executing
+     * any floating point instructions. */
     *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
 
     return pxTopOfStack;
@@ -266,21 +268,21 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
 
 BaseType_t xPortStartScheduler( void )
 {
-uint32_t ulAPSR;
+    uint32_t ulAPSR;
 
-    #if( configASSERT_DEFINED == 1 )
+    #if ( configASSERT_DEFINED == 1 )
     {
         volatile uint8_t ucOriginalPriority;
         volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + portINTERRUPT_PRIORITY_REGISTER_OFFSET );
         volatile uint8_t ucMaxPriorityValue;
 
         /* Determine how many priority bits are implemented in the GIC.
-
-        Save the interrupt priority value that is about to be clobbered. */
+         *
+         * Save the interrupt priority value that is about to be clobbered. */
         ucOriginalPriority = *pucFirstUserPriorityRegister;
 
         /* Determine the number of priority bits available.  First write to
-        all possible bits. */
+         * all possible bits. */
         *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
 
         /* Read the value back to see how many bits stuck. */
@@ -293,13 +295,13 @@ uint32_t ulAPSR;
         }
 
         /* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read
-        value. */
+         * value. */
 
         configASSERT( ucMaxPriorityValue >= portLOWEST_INTERRUPT_PRIORITY );
 
 
         /* Restore the clobbered interrupt priority register to its original
-        value. */
+         * value. */
         *pucFirstUserPriorityRegister = ucOriginalPriority;
     }
     #endif /* configASSERT_DEFINED */
@@ -309,26 +311,28 @@ uint32_t ulAPSR;
     __asm volatile ( "MRS %0, CurrentEL" : "=r" ( ulAPSR ) );
     ulAPSR &= portAPSR_MODE_BITS_MASK;
 
-#if defined( GUEST )
-    #warning Building for execution as a guest under XEN. THIS IS NOT A FULLY TESTED PATH.
-    configASSERT( ulAPSR == portEL1 );
-    if( ulAPSR == portEL1 )
-#else
-    configASSERT( ulAPSR == portEL3 );
-    if( ulAPSR == portEL3 )
-#endif
+    #if defined( GUEST )
+    #warning "Building for execution as a guest under XEN. THIS IS NOT A FULLY TESTED PATH."
+        configASSERT( ulAPSR == portEL1 );
+
+        if( ulAPSR == portEL1 )
+    #else
+        configASSERT( ulAPSR == portEL3 );
+
+        if( ulAPSR == portEL3 )
+    #endif
     {
         /* Only continue if the binary point value is set to its lowest possible
-        setting.  See the comments in vPortValidateInterruptPriority() below for
-        more information. */
+         * setting.  See the comments in vPortValidateInterruptPriority() below for
+         * more information. */
         configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
 
         if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )
         {
             /* Interrupts are turned off in the CPU itself to ensure a tick does
-            not execute while the scheduler is being started.  Interrupts are
-            automatically turned back on in the CPU when the first task starts
-            executing. */
+             * not execute while the scheduler is being started.  Interrupts are
+             * automatically turned back on in the CPU when the first task starts
+             * executing. */
             portDISABLE_INTERRUPTS();
 
             /* Start the timer that generates the tick ISR. */
@@ -346,7 +350,7 @@ uint32_t ulAPSR;
 void vPortEndScheduler( void )
 {
     /* Not implemented in ports where there is nothing to return to.
-    Artificially force an assert. */
+     * Artificially force an assert. */
     configASSERT( ullCriticalNesting == 1000ULL );
 }
 /*-----------------------------------------------------------*/
@@ -357,15 +361,15 @@ void vPortEnterCritical( void )
     uxPortSetInterruptMask();
 
     /* Now interrupts are disabled ullCriticalNesting can be accessed
-    directly.  Increment ullCriticalNesting to keep a count of how many times
-    portENTER_CRITICAL() has been called. */
+     * directly.  Increment ullCriticalNesting to keep a count of how many times
+     * portENTER_CRITICAL() has been called. */
     ullCriticalNesting++;
 
     /* This is not the interrupt safe version of the enter critical function so
-    assert() if it is being called from an interrupt context.  Only API
-    functions that end in "FromISR" can be used in an interrupt.  Only assert if
-    the critical nesting count is 1 to protect against recursive calls if the
-    assert function also uses a critical section. */
+     * assert() if it is being called from an interrupt context.  Only API
+     * functions that end in "FromISR" can be used in an interrupt.  Only assert if
+     * the critical nesting count is 1 to protect against recursive calls if the
+     * assert function also uses a critical section. */
     if( ullCriticalNesting == 1ULL )
     {
         configASSERT( ullPortInterruptNesting == 0 );
@@ -378,15 +382,15 @@ void vPortExitCritical( void )
     if( ullCriticalNesting > portNO_CRITICAL_NESTING )
     {
         /* Decrement the nesting count as the critical section is being
-        exited. */
+         * exited. */
         ullCriticalNesting--;
 
         /* If the nesting level has reached zero then all interrupt
-        priorities must be re-enabled. */
+         * priorities must be re-enabled. */
         if( ullCriticalNesting == portNO_CRITICAL_NESTING )
         {
             /* Critical nesting has reached zero so all interrupt priorities
-            should be unmasked. */
+             * should be unmasked. */
             portCLEAR_INTERRUPT_MASK();
         }
     }
@@ -403,23 +407,23 @@ void FreeRTOS_Tick_Handler( void )
     #endif
 
     /* Interrupts should not be enabled before this point. */
-    #if( configASSERT_DEFINED == 1 )
+    #if ( configASSERT_DEFINED == 1 )
     {
         uint32_t ulMaskBits;
 
-        __asm volatile( "mrs %0, daif" : "=r"( ulMaskBits ) :: "memory" );
+        __asm volatile ( "mrs %0, daif" : "=r" ( ulMaskBits )::"memory" );
         configASSERT( ( ulMaskBits & portDAIF_I ) != 0 );
     }
     #endif /* configASSERT_DEFINED */
 
     /* Set interrupt mask before altering scheduler structures.   The tick
-    handler runs at the lowest priority, so interrupts cannot already be masked,
-    so there is no need to save and restore the current mask value.  It is
-    necessary to turn off interrupts in the CPU itself while the ICCPMR is being
-    updated. */
+     * handler runs at the lowest priority, so interrupts cannot already be masked,
+     * so there is no need to save and restore the current mask value.  It is
+     * necessary to turn off interrupts in the CPU itself while the ICCPMR is being
+     * updated. */
     portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
-    __asm volatile (    "dsb sy     \n"
-                        "isb sy     \n" ::: "memory" );
+    __asm volatile ( "dsb sy     \n"
+                     "isb sy     \n" ::: "memory" );
 
     /* Ok to enable interrupts after the interrupt source has been cleared. */
     configCLEAR_TICK_INTERRUPT();
@@ -439,11 +443,11 @@ void FreeRTOS_Tick_Handler( void )
 void vPortTaskUsesFPU( void )
 {
     /* A task is registering the fact that it needs an FPU context.  Set the
-    FPU flag (which is saved as part of the task context). */
+     * FPU flag (which is saved as part of the task context). */
     ullPortTaskHasFPUContext = pdTRUE;
 
     /* Consider initialising the FPSR here - but probably not necessary in
-    AArch64. */
+     * AArch64. */
 }
 /*-----------------------------------------------------------*/
 
@@ -458,11 +462,12 @@ void vPortClearInterruptMask( UBaseType_t uxNewMaskValue )
 
 UBaseType_t uxPortSetInterruptMask( void )
 {
-uint32_t ulReturn;
+    uint32_t ulReturn;
 
     /* Interrupt in the CPU must be turned off while the ICCPMR is being
-    updated. */
+     * updated. */
     portDISABLE_INTERRUPTS();
+
     if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
     {
         /* Interrupts were already masked. */
@@ -472,45 +477,46 @@ uint32_t ulReturn;
     {
         ulReturn = pdFALSE;
         portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
-        __asm volatile (    "dsb sy     \n"
-                            "isb sy     \n" ::: "memory" );
+        __asm volatile ( "dsb sy     \n"
+                         "isb sy     \n" ::: "memory" );
     }
+
     portENABLE_INTERRUPTS();
 
     return ulReturn;
 }
 /*-----------------------------------------------------------*/
 
-#if( configASSERT_DEFINED == 1 )
+#if ( configASSERT_DEFINED == 1 )
 
     void vPortValidateInterruptPriority( void )
     {
         /* The following assertion will fail if a service routine (ISR) for
-        an interrupt that has been assigned a priority above
-        configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
-        function.  ISR safe FreeRTOS API functions must *only* be called
-        from interrupts that have been assigned a priority at or below
-        configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
-        Numerically low interrupt priority numbers represent logically high
-        interrupt priorities, therefore the priority of the interrupt must
-        be set to a value equal to or numerically *higher* than
-        configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
-        FreeRTOS maintains separate thread and ISR API functions to ensure
-        interrupt entry is as fast and simple as possible. */
+         * an interrupt that has been assigned a priority above
+         * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+         * function.  ISR safe FreeRTOS API functions must *only* be called
+         * from interrupts that have been assigned a priority at or below
+         * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+         *
+         * Numerically low interrupt priority numbers represent logically high
+         * interrupt priorities, therefore the priority of the interrupt must
+         * be set to a value equal to or numerically *higher* than
+         * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+         *
+         * FreeRTOS maintains separate thread and ISR API functions to ensure
+         * interrupt entry is as fast and simple as possible. */
         configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
 
         /* Priority grouping:  The interrupt controller (GIC) allows the bits
-        that define each interrupt's priority to be split between bits that
-        define the interrupt's pre-emption priority bits and bits that define
-        the interrupt's sub-priority.  For simplicity all bits must be defined
-        to be pre-emption priority bits.  The following assertion will fail if
-        this is not the case (if some bits represent a sub-priority).
-
-        The priority grouping is configured by the GIC's binary point register
-        (ICCBPR).  Writting 0 to ICCBPR will ensure it is set to its lowest
-        possible value (which may be above 0). */
+         * that define each interrupt's priority to be split between bits that
+         * define the interrupt's pre-emption priority bits and bits that define
+         * the interrupt's sub-priority.  For simplicity all bits must be defined
+         * to be pre-emption priority bits.  The following assertion will fail if
+         * this is not the case (if some bits represent a sub-priority).
+         *
+         * The priority grouping is configured by the GIC's binary point register
+         * (ICCBPR).  Writting 0 to ICCBPR will ensure it is set to its lowest
+         * possible value (which may be above 0). */
         configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
     }
 
diff --git a/portable/GCC/ARM_CA53_64_BIT/portmacro.h b/portable/GCC/ARM_CA53_64_BIT/portmacro.h
index 00fc06164..2c9da1c60 100644
--- a/portable/GCC/ARM_CA53_64_BIT/portmacro.h
+++ b/portable/GCC/ARM_CA53_64_BIT/portmacro.h
@@ -46,57 +46,58 @@
  */
 
 /* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  size_t
-#define portBASE_TYPE   long
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    size_t
+#define portBASE_TYPE     long
 
-typedef portSTACK_TYPE StackType_t;
-typedef portBASE_TYPE BaseType_t;
-typedef uint64_t UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef portBASE_TYPE    BaseType_t;
+typedef uint64_t         UBaseType_t;
 
-typedef uint64_t TickType_t;
-#define portMAX_DELAY ( ( TickType_t ) 0xffffffffffffffff )
+typedef uint64_t         TickType_t;
+#define portMAX_DELAY              ( ( TickType_t ) 0xffffffffffffffff )
 
 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-not need to be guarded with a critical section. */
-#define portTICK_TYPE_IS_ATOMIC 1
+ * not need to be guarded with a critical section. */
+#define portTICK_TYPE_IS_ATOMIC    1
 
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portSTACK_GROWTH            ( -1 )
-#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT          16
-#define portPOINTER_SIZE_TYPE       uint64_t
+#define portSTACK_GROWTH         ( -1 )
+#define portTICK_PERIOD_MS       ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT       16
+#define portPOINTER_SIZE_TYPE    uint64_t
 
 /*-----------------------------------------------------------*/
 
 /* Task utilities. */
 
 /* Called at the end of an ISR that can cause a context switch. */
-#define portEND_SWITCHING_ISR( xSwitchRequired )\
-{                                               \
-extern uint64_t ullPortYieldRequired;           \
-                                                \
-    if( xSwitchRequired != pdFALSE )            \
-    {                                           \
-        ullPortYieldRequired = pdTRUE;          \
-    }                                           \
-}
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+    {                                            \
+        extern uint64_t ullPortYieldRequired;    \
+                                                 \
+        if( xSwitchRequired != pdFALSE )         \
+        {                                        \
+            ullPortYieldRequired = pdTRUE;       \
+        }                                        \
+    }
 
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
 #if defined( GUEST )
-    #define portYIELD() __asm volatile ( "SVC 0" ::: "memory" )
+    #define portYIELD()            __asm volatile ( "SVC 0" ::: "memory" )
 #else
-    #define portYIELD() __asm volatile ( "SMC 0" ::: "memory" )
+    #define portYIELD()            __asm volatile ( "SMC 0" ::: "memory" )
 #endif
+
 /*-----------------------------------------------------------
- * Critical section control
- *----------------------------------------------------------*/
+* Critical section control
+*----------------------------------------------------------*/
 
 extern void vPortEnterCritical( void );
 extern void vPortExitCritical( void );
@@ -104,106 +105,106 @@ extern UBaseType_t uxPortSetInterruptMask( void );
 extern void vPortClearInterruptMask( UBaseType_t uxNewMaskValue );
 extern void vPortInstallFreeRTOSVectorTable( void );
 
-#define portDISABLE_INTERRUPTS()                                    \
-    __asm volatile ( "MSR DAIFSET, #2" ::: "memory" );              \
-    __asm volatile ( "DSB SY" );                                    \
+#define portDISABLE_INTERRUPTS()                       \
+    __asm volatile ( "MSR DAIFSET, #2" ::: "memory" ); \
+    __asm volatile ( "DSB SY" );                       \
     __asm volatile ( "ISB SY" );
 
-#define portENABLE_INTERRUPTS()                                     \
-    __asm volatile ( "MSR DAIFCLR, #2" ::: "memory" );              \
-    __asm volatile ( "DSB SY" );                                    \
+#define portENABLE_INTERRUPTS()                        \
+    __asm volatile ( "MSR DAIFCLR, #2" ::: "memory" ); \
+    __asm volatile ( "DSB SY" );                       \
     __asm volatile ( "ISB SY" );
 
 
 /* These macros do not globally disable/enable interrupts.  They do mask off
-interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
-#define portENTER_CRITICAL()        vPortEnterCritical();
-#define portEXIT_CRITICAL()         vPortExitCritical();
-#define portSET_INTERRUPT_MASK_FROM_ISR()       uxPortSetInterruptMask()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)    vPortClearInterruptMask(x)
+ * interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
+#define portENTER_CRITICAL()                      vPortEnterCritical();
+#define portEXIT_CRITICAL()                       vPortExitCritical();
+#define portSET_INTERRUPT_MASK_FROM_ISR()         uxPortSetInterruptMask()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vPortClearInterruptMask( x )
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site.  These are
-not required for this port but included in case common demo code that uses these
-macros is used. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )  void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )    void vFunction( void *pvParameters )
+ * not required for this port but included in case common demo code that uses these
+ * macros is used. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
 /* Prototype of the FreeRTOS tick handler.  This must be installed as the
-handler for whichever peripheral is used to generate the RTOS tick. */
+ * handler for whichever peripheral is used to generate the RTOS tick. */
 void FreeRTOS_Tick_Handler( void );
 
 /* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
-before any floating point instructions are executed. */
+ * before any floating point instructions are executed. */
 void vPortTaskUsesFPU( void );
-#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
+#define portTASK_USES_FLOATING_POINT()    vPortTaskUsesFPU()
 
-#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
-#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
+#define portLOWEST_INTERRUPT_PRIORITY           ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
+#define portLOWEST_USABLE_INTERRUPT_PRIORITY    ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
 
 /* Architecture specific optimisations. */
 #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-    #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+    #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
 #endif
 
 #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
 
-    /* Store/clear the ready priorities in a bit map. */
-    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+/* Store/clear the ready priorities in a bit map. */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 
-    /*-----------------------------------------------------------*/
+/*-----------------------------------------------------------*/
 
-    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __builtin_clz( uxReadyPriorities ) )
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31 - __builtin_clz( uxReadyPriorities ) )
 
 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 
 #ifdef configASSERT
     void vPortValidateInterruptPriority( void );
-    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()  vPortValidateInterruptPriority()
+    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
 #endif /* configASSERT */
 
-#define portNOP() __asm volatile( "NOP" )
-#define portINLINE __inline
+#define portNOP()                                         __asm volatile ( "NOP" )
+#define portINLINE    __inline
 
 /* The number of bits to shift for an interrupt priority is dependent on the
-number of bits implemented by the interrupt controller. */
+ * number of bits implemented by the interrupt controller. */
 #if configUNIQUE_INTERRUPT_PRIORITIES == 16
-    #define portPRIORITY_SHIFT 4
-    #define portMAX_BINARY_POINT_VALUE  3
+    #define portPRIORITY_SHIFT            4
+    #define portMAX_BINARY_POINT_VALUE    3
 #elif configUNIQUE_INTERRUPT_PRIORITIES == 32
-    #define portPRIORITY_SHIFT 3
-    #define portMAX_BINARY_POINT_VALUE  2
+    #define portPRIORITY_SHIFT            3
+    #define portMAX_BINARY_POINT_VALUE    2
 #elif configUNIQUE_INTERRUPT_PRIORITIES == 64
-    #define portPRIORITY_SHIFT 2
-    #define portMAX_BINARY_POINT_VALUE  1
+    #define portPRIORITY_SHIFT            2
+    #define portMAX_BINARY_POINT_VALUE    1
 #elif configUNIQUE_INTERRUPT_PRIORITIES == 128
-    #define portPRIORITY_SHIFT 1
-    #define portMAX_BINARY_POINT_VALUE  0
+    #define portPRIORITY_SHIFT            1
+    #define portMAX_BINARY_POINT_VALUE    0
 #elif configUNIQUE_INTERRUPT_PRIORITIES == 256
-    #define portPRIORITY_SHIFT 0
-    #define portMAX_BINARY_POINT_VALUE  0
-#else
+    #define portPRIORITY_SHIFT            0
+    #define portMAX_BINARY_POINT_VALUE    0
+#else /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */
     #error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting.  configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware
-#endif
+#endif /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */
 
 /* Interrupt controller access addresses. */
-#define portICCPMR_PRIORITY_MASK_OFFSET                         ( 0x04 )
-#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET                 ( 0x0C )
-#define portICCEOIR_END_OF_INTERRUPT_OFFSET                     ( 0x10 )
-#define portICCBPR_BINARY_POINT_OFFSET                          ( 0x08 )
-#define portICCRPR_RUNNING_PRIORITY_OFFSET                      ( 0x14 )
+#define portICCPMR_PRIORITY_MASK_OFFSET                      ( 0x04 )
+#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET              ( 0x0C )
+#define portICCEOIR_END_OF_INTERRUPT_OFFSET                  ( 0x10 )
+#define portICCBPR_BINARY_POINT_OFFSET                       ( 0x08 )
+#define portICCRPR_RUNNING_PRIORITY_OFFSET                   ( 0x14 )
 
-#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS      ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )
-#define portICCPMR_PRIORITY_MASK_REGISTER                   ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )
-#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS   ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )
-#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS       ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )
-#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS           ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )
-#define portICCBPR_BINARY_POINT_REGISTER                    ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
-#define portICCRPR_RUNNING_PRIORITY_REGISTER                ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )
+#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS       ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )
+#define portICCPMR_PRIORITY_MASK_REGISTER                    ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )
+#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS    ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )
+#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS        ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )
+#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS            ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )
+#define portICCBPR_BINARY_POINT_REGISTER                     ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
+#define portICCRPR_RUNNING_PRIORITY_REGISTER                 ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )
 
-#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+#define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/GCC/ARM_CA53_64_BIT_SRE/port.c b/portable/GCC/ARM_CA53_64_BIT_SRE/port.c
index b1f7789d7..8731054bc 100644
--- a/portable/GCC/ARM_CA53_64_BIT_SRE/port.c
+++ b/portable/GCC/ARM_CA53_64_BIT_SRE/port.c
@@ -34,92 +34,92 @@
 #include "task.h"
 
 #ifndef configUNIQUE_INTERRUPT_PRIORITIES
-    #error configUNIQUE_INTERRUPT_PRIORITIES must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+    #error "configUNIQUE_INTERRUPT_PRIORITIES must be defined.  See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
 #endif
 
 #ifndef configSETUP_TICK_INTERRUPT
-    #error configSETUP_TICK_INTERRUPT() must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+    #error "configSETUP_TICK_INTERRUPT() must be defined.  See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
 #endif /* configSETUP_TICK_INTERRUPT */
 
 #ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
-    #error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+    #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be defined.  See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
 #endif
 
 #if configMAX_API_CALL_INTERRUPT_PRIORITY == 0
-    #error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0
+    #error "configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0"
 #endif
 
 #if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES
-    #error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority
+    #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority"
 #endif
 
 #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
     /* Check the configuration. */
-    #if( configMAX_PRIORITIES > 32 )
-        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+    #if ( configMAX_PRIORITIES > 32 )
+        #error "configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice."
     #endif
 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 
 /* In case security extensions are implemented. */
 #if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
-    #error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
+    #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )"
 #endif
 
 /* Some vendor specific files default configCLEAR_TICK_INTERRUPT() in
-portmacro.h. */
+ * portmacro.h. */
 #ifndef configCLEAR_TICK_INTERRUPT
     #define configCLEAR_TICK_INTERRUPT()
 #endif
 
 /* A critical section is exited when the critical section nesting count reaches
-this value. */
-#define portNO_CRITICAL_NESTING         ( ( size_t ) 0 )
+ * this value. */
+#define portNO_CRITICAL_NESTING          ( ( size_t ) 0 )
 
 /* In all GICs 255 can be written to the priority mask register to unmask all
-(but the lowest) interrupt priority. */
-#define portUNMASK_VALUE                ( 0xFFUL )
+ * (but the lowest) interrupt priority. */
+#define portUNMASK_VALUE                 ( 0xFFUL )
 
 /* Tasks are not created with a floating point context, but can be given a
-floating point context after they have been created.  A variable is stored as
-part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
-does not have an FPU context, or any other value if the task does have an FPU
-context. */
-#define portNO_FLOATING_POINT_CONTEXT   ( ( StackType_t ) 0 )
+ * floating point context after they have been created.  A variable is stored as
+ * part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
+ * does not have an FPU context, or any other value if the task does have an FPU
+ * context. */
+#define portNO_FLOATING_POINT_CONTEXT    ( ( StackType_t ) 0 )
 
 /* Constants required to setup the initial task context. */
-#define portSP_ELx                      ( ( StackType_t ) 0x01 )
-#define portSP_EL0                      ( ( StackType_t ) 0x00 )
+#define portSP_ELx                       ( ( StackType_t ) 0x01 )
+#define portSP_EL0                       ( ( StackType_t ) 0x00 )
 
 #if defined( GUEST )
-    #define portEL1                     ( ( StackType_t ) 0x04 )
-    #define portINITIAL_PSTATE              ( portEL1 | portSP_EL0 )
+    #define portEL1                      ( ( StackType_t ) 0x04 )
+    #define portINITIAL_PSTATE           ( portEL1 | portSP_EL0 )
 #else
-    #define portEL3                     ( ( StackType_t ) 0x0c )
+    #define portEL3                      ( ( StackType_t ) 0x0c )
     /* At the time of writing, the BSP only supports EL3. */
-    #define portINITIAL_PSTATE          ( portEL3 | portSP_EL0 )
+    #define portINITIAL_PSTATE           ( portEL3 | portSP_EL0 )
 #endif
 
 /* Masks all bits in the APSR other than the mode bits. */
-#define portAPSR_MODE_BITS_MASK         ( 0x0C )
+#define portAPSR_MODE_BITS_MASK    ( 0x0C )
 
 /* The I bit in the DAIF bits. */
-#define portDAIF_I                      ( 0x80 )
+#define portDAIF_I                 ( 0x80 )
 
 /* Macro to unmask all interrupt priorities. */
 /* s3_0_c4_c6_0 is ICC_PMR_EL1. */
-#define portCLEAR_INTERRUPT_MASK()                      \
-{                                                       \
-    __asm volatile (    "MSR DAIFSET, #2        \n"     \
-                        "DSB SY                 \n"     \
-                        "ISB SY                 \n"     \
-                        "MSR s3_0_c4_c6_0, %0   \n"     \
-                        "DSB SY                 \n"     \
-                        "ISB SY                 \n"     \
-                        "MSR DAIFCLR, #2        \n"     \
-                        "DSB SY                 \n"     \
-                        "ISB SY                 \n"     \
-                        ::"r"( portUNMASK_VALUE ) );    \
-}
+#define portCLEAR_INTERRUPT_MASK()                     \
+    {                                                  \
+        __asm volatile ( "MSR DAIFSET, #2        \n"   \
+                         "DSB SY                 \n"   \
+                         "ISB SY                 \n"   \
+                         "MSR s3_0_c4_c6_0, %0   \n"   \
+                         "DSB SY                 \n"   \
+                         "ISB SY                 \n"   \
+                         "MSR DAIFCLR, #2        \n"   \
+                         "DSB SY                 \n"   \
+                         "ISB SY                 \n"   \
+                         ::"r" ( portUNMASK_VALUE ) ); \
+    }
 
 /*-----------------------------------------------------------*/
 
@@ -132,101 +132,103 @@ extern void vPortRestoreTaskContext( void );
 /*-----------------------------------------------------------*/
 
 /* A variable is used to keep track of the critical section nesting.  This
-variable has to be stored as part of the task context and must be initialised to
-a non zero value to ensure interrupts don't inadvertently become unmasked before
-the scheduler starts.  As it is stored as part of the task context it will
-automatically be set to 0 when the first task is started. */
+ * variable has to be stored as part of the task context and must be initialised to
+ * a non zero value to ensure interrupts don't inadvertently become unmasked before
+ * the scheduler starts.  As it is stored as part of the task context it will
+ * automatically be set to 0 when the first task is started. */
 volatile uint64_t ullCriticalNesting = 9999ULL;
 
 /* Saved as part of the task context.  If ullPortTaskHasFPUContext is non-zero
-then floating point context must be saved and restored for the task. */
+ * then floating point context must be saved and restored for the task. */
 uint64_t ullPortTaskHasFPUContext = pdFALSE;
 
 /* Set to 1 to pend a context switch from an ISR. */
 uint64_t ullPortYieldRequired = pdFALSE;
 
 /* Counts the interrupt nesting depth.  A context switch is only performed if
-if the nesting depth is 0. */
+ * if the nesting depth is 0. */
 uint64_t ullPortInterruptNesting = 0;
 
 /* Used in the ASM code. */
-__attribute__(( used )) const uint64_t ullMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
+__attribute__( ( used ) ) const uint64_t ullMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
 
 /*-----------------------------------------------------------*/
 
 /*
  * See header file for description.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
     /* Setup the initial stack of the task.  The stack is set exactly as
-    expected by the portRESTORE_CONTEXT() macro. */
+     * expected by the portRESTORE_CONTEXT() macro. */
 
     /* First all the general purpose registers. */
     pxTopOfStack--;
-    *pxTopOfStack = 0x0101010101010101ULL;  /* R1 */
+    *pxTopOfStack = 0x0101010101010101ULL;        /* R1 */
     pxTopOfStack--;
     *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
     pxTopOfStack--;
-    *pxTopOfStack = 0x0303030303030303ULL;  /* R3 */
+    *pxTopOfStack = 0x0303030303030303ULL;        /* R3 */
     pxTopOfStack--;
-    *pxTopOfStack = 0x0202020202020202ULL;  /* R2 */
+    *pxTopOfStack = 0x0202020202020202ULL;        /* R2 */
     pxTopOfStack--;
-    *pxTopOfStack = 0x0505050505050505ULL;  /* R5 */
+    *pxTopOfStack = 0x0505050505050505ULL;        /* R5 */
     pxTopOfStack--;
-    *pxTopOfStack = 0x0404040404040404ULL;  /* R4 */
+    *pxTopOfStack = 0x0404040404040404ULL;        /* R4 */
     pxTopOfStack--;
-    *pxTopOfStack = 0x0707070707070707ULL;  /* R7 */
+    *pxTopOfStack = 0x0707070707070707ULL;        /* R7 */
     pxTopOfStack--;
-    *pxTopOfStack = 0x0606060606060606ULL;  /* R6 */
+    *pxTopOfStack = 0x0606060606060606ULL;        /* R6 */
     pxTopOfStack--;
-    *pxTopOfStack = 0x0909090909090909ULL;  /* R9 */
+    *pxTopOfStack = 0x0909090909090909ULL;        /* R9 */
     pxTopOfStack--;
-    *pxTopOfStack = 0x0808080808080808ULL;  /* R8 */
+    *pxTopOfStack = 0x0808080808080808ULL;        /* R8 */
     pxTopOfStack--;
-    *pxTopOfStack = 0x1111111111111111ULL;  /* R11 */
+    *pxTopOfStack = 0x1111111111111111ULL;        /* R11 */
     pxTopOfStack--;
-    *pxTopOfStack = 0x1010101010101010ULL;  /* R10 */
+    *pxTopOfStack = 0x1010101010101010ULL;        /* R10 */
     pxTopOfStack--;
-    *pxTopOfStack = 0x1313131313131313ULL;  /* R13 */
+    *pxTopOfStack = 0x1313131313131313ULL;        /* R13 */
     pxTopOfStack--;
-    *pxTopOfStack = 0x1212121212121212ULL;  /* R12 */
+    *pxTopOfStack = 0x1212121212121212ULL;        /* R12 */
     pxTopOfStack--;
-    *pxTopOfStack = 0x1515151515151515ULL;  /* R15 */
+    *pxTopOfStack = 0x1515151515151515ULL;        /* R15 */
     pxTopOfStack--;
-    *pxTopOfStack = 0x1414141414141414ULL;  /* R14 */
+    *pxTopOfStack = 0x1414141414141414ULL;        /* R14 */
     pxTopOfStack--;
-    *pxTopOfStack = 0x1717171717171717ULL;  /* R17 */
+    *pxTopOfStack = 0x1717171717171717ULL;        /* R17 */
     pxTopOfStack--;
-    *pxTopOfStack = 0x1616161616161616ULL;  /* R16 */
+    *pxTopOfStack = 0x1616161616161616ULL;        /* R16 */
     pxTopOfStack--;
-    *pxTopOfStack = 0x1919191919191919ULL;  /* R19 */
+    *pxTopOfStack = 0x1919191919191919ULL;        /* R19 */
     pxTopOfStack--;
-    *pxTopOfStack = 0x1818181818181818ULL;  /* R18 */
+    *pxTopOfStack = 0x1818181818181818ULL;        /* R18 */
     pxTopOfStack--;
-    *pxTopOfStack = 0x2121212121212121ULL;  /* R21 */
+    *pxTopOfStack = 0x2121212121212121ULL;        /* R21 */
     pxTopOfStack--;
-    *pxTopOfStack = 0x2020202020202020ULL;  /* R20 */
+    *pxTopOfStack = 0x2020202020202020ULL;        /* R20 */
     pxTopOfStack--;
-    *pxTopOfStack = 0x2323232323232323ULL;  /* R23 */
+    *pxTopOfStack = 0x2323232323232323ULL;        /* R23 */
     pxTopOfStack--;
-    *pxTopOfStack = 0x2222222222222222ULL;  /* R22 */
+    *pxTopOfStack = 0x2222222222222222ULL;        /* R22 */
     pxTopOfStack--;
-    *pxTopOfStack = 0x2525252525252525ULL;  /* R25 */
+    *pxTopOfStack = 0x2525252525252525ULL;        /* R25 */
     pxTopOfStack--;
-    *pxTopOfStack = 0x2424242424242424ULL;  /* R24 */
+    *pxTopOfStack = 0x2424242424242424ULL;        /* R24 */
     pxTopOfStack--;
-    *pxTopOfStack = 0x2727272727272727ULL;  /* R27 */
+    *pxTopOfStack = 0x2727272727272727ULL;        /* R27 */
     pxTopOfStack--;
-    *pxTopOfStack = 0x2626262626262626ULL;  /* R26 */
+    *pxTopOfStack = 0x2626262626262626ULL;        /* R26 */
     pxTopOfStack--;
-    *pxTopOfStack = 0x2929292929292929ULL;  /* R29 */
+    *pxTopOfStack = 0x2929292929292929ULL;        /* R29 */
     pxTopOfStack--;
-    *pxTopOfStack = 0x2828282828282828ULL;  /* R28 */
+    *pxTopOfStack = 0x2828282828282828ULL;        /* R28 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x00;   /* XZR - has no effect, used so there are an even number of registers. */
+    *pxTopOfStack = ( StackType_t ) 0x00;         /* XZR - has no effect, used so there are an even number of registers. */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x00;   /* R30 - procedure call link register. */
+    *pxTopOfStack = ( StackType_t ) 0x00;         /* R30 - procedure call link register. */
     pxTopOfStack--;
 
     *pxTopOfStack = portINITIAL_PSTATE;
@@ -236,13 +238,13 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
     pxTopOfStack--;
 
     /* The task will start with a critical nesting count of 0 as interrupts are
-    enabled. */
+     * enabled. */
     *pxTopOfStack = portNO_CRITICAL_NESTING;
     pxTopOfStack--;
 
     /* The task will start without a floating point context.  A task that uses
-    the floating point hardware must call vPortTaskUsesFPU() before executing
-    any floating point instructions. */
+     * the floating point hardware must call vPortTaskUsesFPU() before executing
+     * any floating point instructions. */
     *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
 
     return pxTopOfStack;
@@ -251,23 +253,26 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
 
 BaseType_t xPortStartScheduler( void )
 {
-uint32_t ulAPSR;
+    uint32_t ulAPSR;
 
     __asm volatile ( "MRS %0, CurrentEL" : "=r" ( ulAPSR ) );
+
     ulAPSR &= portAPSR_MODE_BITS_MASK;
 
-#if defined( GUEST )
-    configASSERT( ulAPSR == portEL1 );
-    if( ulAPSR == portEL1 )
-#else
-    configASSERT( ulAPSR == portEL3 );
-    if( ulAPSR == portEL3 )
-#endif
+    #if defined( GUEST )
+        configASSERT( ulAPSR == portEL1 );
+
+        if( ulAPSR == portEL1 )
+    #else
+        configASSERT( ulAPSR == portEL3 );
+
+        if( ulAPSR == portEL3 )
+    #endif
     {
         /* Interrupts are turned off in the CPU itself to ensure a tick does
-        not execute while the scheduler is being started.  Interrupts are
-        automatically turned back on in the CPU when the first task starts
-        executing. */
+         * not execute while the scheduler is being started.  Interrupts are
+         * automatically turned back on in the CPU when the first task starts
+         * executing. */
         portDISABLE_INTERRUPTS();
 
         /* Start the timer that generates the tick ISR. */
@@ -284,7 +289,7 @@ uint32_t ulAPSR;
 void vPortEndScheduler( void )
 {
     /* Not implemented in ports where there is nothing to return to.
-    Artificially force an assert. */
+     * Artificially force an assert. */
     configASSERT( ullCriticalNesting == 1000ULL );
 }
 /*-----------------------------------------------------------*/
@@ -295,15 +300,15 @@ void vPortEnterCritical( void )
     uxPortSetInterruptMask();
 
     /* Now interrupts are disabled ullCriticalNesting can be accessed
-    directly.  Increment ullCriticalNesting to keep a count of how many times
-    portENTER_CRITICAL() has been called. */
+     * directly.  Increment ullCriticalNesting to keep a count of how many times
+     * portENTER_CRITICAL() has been called. */
     ullCriticalNesting++;
 
     /* This is not the interrupt safe version of the enter critical function so
-    assert() if it is being called from an interrupt context.  Only API
-    functions that end in "FromISR" can be used in an interrupt.  Only assert if
-    the critical nesting count is 1 to protect against recursive calls if the
-    assert function also uses a critical section. */
+     * assert() if it is being called from an interrupt context.  Only API
+     * functions that end in "FromISR" can be used in an interrupt.  Only assert if
+     * the critical nesting count is 1 to protect against recursive calls if the
+     * assert function also uses a critical section. */
     if( ullCriticalNesting == 1ULL )
     {
         configASSERT( ullPortInterruptNesting == 0 );
@@ -316,15 +321,15 @@ void vPortExitCritical( void )
     if( ullCriticalNesting > portNO_CRITICAL_NESTING )
     {
         /* Decrement the nesting count as the critical section is being
-        exited. */
+         * exited. */
         ullCriticalNesting--;
 
         /* If the nesting level has reached zero then all interrupt
-        priorities must be re-enabled. */
+         * priorities must be re-enabled. */
         if( ullCriticalNesting == portNO_CRITICAL_NESTING )
         {
             /* Critical nesting has reached zero so all interrupt priorities
-            should be unmasked. */
+             * should be unmasked. */
             portCLEAR_INTERRUPT_MASK();
         }
     }
@@ -344,25 +349,25 @@ void FreeRTOS_Tick_Handler( void )
     #endif
 
     /* Interrupts should not be enabled before this point. */
-    #if( configASSERT_DEFINED == 1 )
+    #if ( configASSERT_DEFINED == 1 )
     {
         uint32_t ulMaskBits;
 
-        __asm volatile( "MRS %0, DAIF" : "=r"( ulMaskBits ) :: "memory" );
+        __asm volatile ( "MRS %0, DAIF" : "=r" ( ulMaskBits )::"memory" );
         configASSERT( ( ulMaskBits & portDAIF_I ) != 0 );
     }
     #endif /* configASSERT_DEFINED */
 
     /* Set interrupt mask before altering scheduler structures.   The tick
-    handler runs at the lowest priority, so interrupts cannot already be masked,
-    so there is no need to save and restore the current mask value.  It is
-    necessary to turn off interrupts in the CPU itself while the ICCPMR is being
-    updated. */
+     * handler runs at the lowest priority, so interrupts cannot already be masked,
+     * so there is no need to save and restore the current mask value.  It is
+     * necessary to turn off interrupts in the CPU itself while the ICCPMR is being
+     * updated. */
     /* s3_0_c4_c6_0 is ICC_PMR_EL1. */
     __asm volatile ( "MSR s3_0_c4_c6_0, %0      \n"
                      "DSB SY                    \n"
                      "ISB SY                    \n"
-                     :: "r" ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) : "memory" );
+                     ::"r" ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) : "memory" );
 
     /* Ok to enable interrupts after the interrupt source has been cleared. */
     configCLEAR_TICK_INTERRUPT();
@@ -382,11 +387,11 @@ void FreeRTOS_Tick_Handler( void )
 void vPortTaskUsesFPU( void )
 {
     /* A task is registering the fact that it needs an FPU context.  Set the
-    FPU flag (which is saved as part of the task context). */
+     * FPU flag (which is saved as part of the task context). */
     ullPortTaskHasFPUContext = pdTRUE;
 
     /* Consider initialising the FPSR here - but probably not necessary in
-    AArch64. */
+     * AArch64. */
 }
 /*-----------------------------------------------------------*/
 
@@ -401,14 +406,15 @@ void vPortClearInterruptMask( UBaseType_t uxNewMaskValue )
 
 UBaseType_t uxPortSetInterruptMask( void )
 {
-uint32_t ulReturn;
-uint64_t ullPMRValue;
+    uint32_t ulReturn;
+    uint64_t ullPMRValue;
 
     /* Interrupt in the CPU must be turned off while the ICCPMR is being
-    updated. */
+     * updated. */
     portDISABLE_INTERRUPTS();
     /* s3_0_c4_c6_0 is ICC_PMR_EL1. */
     __asm volatile ( "MRS %0, s3_0_c4_c6_0" : "=r" ( ullPMRValue ) );
+
     if( ullPMRValue == ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
     {
         /* Interrupts were already masked. */
@@ -421,7 +427,7 @@ uint64_t ullPMRValue;
         __asm volatile ( "MSR s3_0_c4_c6_0, %0      \n"
                          "DSB SY                    \n"
                          "ISB SY                    \n"
-                         :: "r" ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) : "memory" );
+                         ::"r" ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) : "memory" );
     }
 
     portENABLE_INTERRUPTS();
@@ -430,27 +436,28 @@ uint64_t ullPMRValue;
 }
 /*-----------------------------------------------------------*/
 
-#if( configASSERT_DEFINED == 1 )
+#if ( configASSERT_DEFINED == 1 )
 
     void vPortValidateInterruptPriority( void )
     {
         /* The following assertion will fail if a service routine (ISR) for
-        an interrupt that has been assigned a priority above
-        configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
-        function.  ISR safe FreeRTOS API functions must *only* be called
-        from interrupts that have been assigned a priority at or below
-        configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
-        Numerically low interrupt priority numbers represent logically high
-        interrupt priorities, therefore the priority of the interrupt must
-        be set to a value equal to or numerically *higher* than
-        configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
-        FreeRTOS maintains separate thread and ISR API functions to ensure
-        interrupt entry is as fast and simple as possible. */
+         * an interrupt that has been assigned a priority above
+         * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+         * function.  ISR safe FreeRTOS API functions must *only* be called
+         * from interrupts that have been assigned a priority at or below
+         * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+         *
+         * Numerically low interrupt priority numbers represent logically high
+         * interrupt priorities, therefore the priority of the interrupt must
+         * be set to a value equal to or numerically *higher* than
+         * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+         *
+         * FreeRTOS maintains separate thread and ISR API functions to ensure
+         * interrupt entry is as fast and simple as possible. */
         uint64_t ullRunningInterruptPriority;
         /* s3_0_c12_c11_3 is ICC_RPR_EL1. */
         __asm volatile ( "MRS %0, s3_0_c12_c11_3" : "=r" ( ullRunningInterruptPriority ) );
+
         configASSERT( ullRunningInterruptPriority >= ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
     }
 
diff --git a/portable/GCC/ARM_CA53_64_BIT_SRE/portmacro.h b/portable/GCC/ARM_CA53_64_BIT_SRE/portmacro.h
index 019928882..cbe0b54dd 100644
--- a/portable/GCC/ARM_CA53_64_BIT_SRE/portmacro.h
+++ b/portable/GCC/ARM_CA53_64_BIT_SRE/portmacro.h
@@ -46,57 +46,58 @@
  */
 
 /* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  size_t
-#define portBASE_TYPE   long
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    size_t
+#define portBASE_TYPE     long
 
-typedef portSTACK_TYPE StackType_t;
-typedef portBASE_TYPE BaseType_t;
-typedef uint64_t UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef portBASE_TYPE    BaseType_t;
+typedef uint64_t         UBaseType_t;
 
-typedef uint64_t TickType_t;
-#define portMAX_DELAY ( ( TickType_t ) 0xffffffffffffffff )
+typedef uint64_t         TickType_t;
+#define portMAX_DELAY              ( ( TickType_t ) 0xffffffffffffffff )
 
 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-not need to be guarded with a critical section. */
-#define portTICK_TYPE_IS_ATOMIC 1
+ * not need to be guarded with a critical section. */
+#define portTICK_TYPE_IS_ATOMIC    1
 
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portSTACK_GROWTH            ( -1 )
-#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT          16
-#define portPOINTER_SIZE_TYPE       uint64_t
+#define portSTACK_GROWTH         ( -1 )
+#define portTICK_PERIOD_MS       ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT       16
+#define portPOINTER_SIZE_TYPE    uint64_t
 
 /*-----------------------------------------------------------*/
 
 /* Task utilities. */
 
 /* Called at the end of an ISR that can cause a context switch. */
-#define portEND_SWITCHING_ISR( xSwitchRequired )\
-{                                               \
-extern uint64_t ullPortYieldRequired;           \
-                                                \
-    if( xSwitchRequired != pdFALSE )            \
-    {                                           \
-        ullPortYieldRequired = pdTRUE;          \
-    }                                           \
-}
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+    {                                            \
+        extern uint64_t ullPortYieldRequired;    \
+                                                 \
+        if( xSwitchRequired != pdFALSE )         \
+        {                                        \
+            ullPortYieldRequired = pdTRUE;       \
+        }                                        \
+    }
 
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
 #if defined( GUEST )
-    #define portYIELD() __asm volatile ( "SVC 0" ::: "memory" )
+    #define portYIELD()            __asm volatile ( "SVC 0" ::: "memory" )
 #else
-    #define portYIELD() __asm volatile ( "SMC 0" ::: "memory" )
+    #define portYIELD()            __asm volatile ( "SMC 0" ::: "memory" )
 #endif
+
 /*-----------------------------------------------------------
- * Critical section control
- *----------------------------------------------------------*/
+* Critical section control
+*----------------------------------------------------------*/
 
 extern void vPortEnterCritical( void );
 extern void vPortExitCritical( void );
@@ -104,91 +105,91 @@ extern UBaseType_t uxPortSetInterruptMask( void );
 extern void vPortClearInterruptMask( UBaseType_t uxNewMaskValue );
 extern void vPortInstallFreeRTOSVectorTable( void );
 
-#define portDISABLE_INTERRUPTS()                                    \
-    __asm volatile ( "MSR DAIFSET, #2" ::: "memory" );              \
-    __asm volatile ( "DSB SY" );                                    \
+#define portDISABLE_INTERRUPTS()                       \
+    __asm volatile ( "MSR DAIFSET, #2" ::: "memory" ); \
+    __asm volatile ( "DSB SY" );                       \
     __asm volatile ( "ISB SY" );
 
-#define portENABLE_INTERRUPTS()                                     \
-    __asm volatile ( "MSR DAIFCLR, #2" ::: "memory" );              \
-    __asm volatile ( "DSB SY" );                                    \
+#define portENABLE_INTERRUPTS()                        \
+    __asm volatile ( "MSR DAIFCLR, #2" ::: "memory" ); \
+    __asm volatile ( "DSB SY" );                       \
     __asm volatile ( "ISB SY" );
 
 
 /* These macros do not globally disable/enable interrupts.  They do mask off
-interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
-#define portENTER_CRITICAL()        vPortEnterCritical();
-#define portEXIT_CRITICAL()         vPortExitCritical();
-#define portSET_INTERRUPT_MASK_FROM_ISR()       uxPortSetInterruptMask()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)    vPortClearInterruptMask(x)
+ * interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
+#define portENTER_CRITICAL()                      vPortEnterCritical();
+#define portEXIT_CRITICAL()                       vPortExitCritical();
+#define portSET_INTERRUPT_MASK_FROM_ISR()         uxPortSetInterruptMask()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vPortClearInterruptMask( x )
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site.  These are
-not required for this port but included in case common demo code that uses these
-macros is used. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )  void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )    void vFunction( void *pvParameters )
+ * not required for this port but included in case common demo code that uses these
+ * macros is used. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
 /* Prototype of the FreeRTOS tick handler.  This must be installed as the
-handler for whichever peripheral is used to generate the RTOS tick. */
+ * handler for whichever peripheral is used to generate the RTOS tick. */
 void FreeRTOS_Tick_Handler( void );
 
 /* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
-before any floating point instructions are executed. */
+ * before any floating point instructions are executed. */
 void vPortTaskUsesFPU( void );
-#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
+#define portTASK_USES_FLOATING_POINT()    vPortTaskUsesFPU()
 
-#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
-#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
+#define portLOWEST_INTERRUPT_PRIORITY           ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
+#define portLOWEST_USABLE_INTERRUPT_PRIORITY    ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
 
 /* Architecture specific optimisations. */
 #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-    #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+    #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
 #endif
 
 #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
 
-    /* Store/clear the ready priorities in a bit map. */
-    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+/* Store/clear the ready priorities in a bit map. */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 
-    /*-----------------------------------------------------------*/
+/*-----------------------------------------------------------*/
 
-    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __builtin_clz( uxReadyPriorities ) )
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31 - __builtin_clz( uxReadyPriorities ) )
 
 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 
 #ifdef configASSERT
     void vPortValidateInterruptPriority( void );
-    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()  vPortValidateInterruptPriority()
+    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
 #endif /* configASSERT */
 
-#define portNOP() __asm volatile( "NOP" )
-#define portINLINE __inline
+#define portNOP()                                         __asm volatile ( "NOP" )
+#define portINLINE    __inline
 
 /* The number of bits to shift for an interrupt priority is dependent on the
-number of bits implemented by the interrupt controller. */
+ * number of bits implemented by the interrupt controller. */
 #if configUNIQUE_INTERRUPT_PRIORITIES == 16
-    #define portPRIORITY_SHIFT 4
-    #define portMAX_BINARY_POINT_VALUE  3
+    #define portPRIORITY_SHIFT            4
+    #define portMAX_BINARY_POINT_VALUE    3
 #elif configUNIQUE_INTERRUPT_PRIORITIES == 32
-    #define portPRIORITY_SHIFT 3
-    #define portMAX_BINARY_POINT_VALUE  2
+    #define portPRIORITY_SHIFT            3
+    #define portMAX_BINARY_POINT_VALUE    2
 #elif configUNIQUE_INTERRUPT_PRIORITIES == 64
-    #define portPRIORITY_SHIFT 2
-    #define portMAX_BINARY_POINT_VALUE  1
+    #define portPRIORITY_SHIFT            2
+    #define portMAX_BINARY_POINT_VALUE    1
 #elif configUNIQUE_INTERRUPT_PRIORITIES == 128
-    #define portPRIORITY_SHIFT 1
-    #define portMAX_BINARY_POINT_VALUE  0
+    #define portPRIORITY_SHIFT            1
+    #define portMAX_BINARY_POINT_VALUE    0
 #elif configUNIQUE_INTERRUPT_PRIORITIES == 256
-    #define portPRIORITY_SHIFT 0
-    #define portMAX_BINARY_POINT_VALUE  0
-#else
+    #define portPRIORITY_SHIFT            0
+    #define portMAX_BINARY_POINT_VALUE    0
+#else /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */
     #error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting.  configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware
-#endif
+#endif /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */
 
-#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+#define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/GCC/ARM_CA9/port.c b/portable/GCC/ARM_CA9/port.c
index 8c7421411..4e4189d36 100644
--- a/portable/GCC/ARM_CA9/port.c
+++ b/portable/GCC/ARM_CA9/port.c
@@ -35,123 +35,123 @@
 #include "task.h"
 
 #ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS
-    #error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+    #error "configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined.  See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
 #endif
 
 #ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET
-    #error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+    #error "configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined.  See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
 #endif
 
 #ifndef configUNIQUE_INTERRUPT_PRIORITIES
-    #error configUNIQUE_INTERRUPT_PRIORITIES must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+    #error "configUNIQUE_INTERRUPT_PRIORITIES must be defined.  See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
 #endif
 
 #ifndef configSETUP_TICK_INTERRUPT
-    #error configSETUP_TICK_INTERRUPT() must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+    #error "configSETUP_TICK_INTERRUPT() must be defined.  See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
 #endif /* configSETUP_TICK_INTERRUPT */
 
 #ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
-    #error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+    #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be defined.  See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
 #endif
 
 #if configMAX_API_CALL_INTERRUPT_PRIORITY == 0
-    #error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0
+    #error "configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0"
 #endif
 
 #if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES
-    #error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority
+    #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority"
 #endif
 
 #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
     /* Check the configuration. */
-    #if( configMAX_PRIORITIES > 32 )
-        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+    #if ( configMAX_PRIORITIES > 32 )
+        #error "configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice."
     #endif
 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 
 /* In case security extensions are implemented. */
 #if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
-    #error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
+    #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )"
 #endif
 
 /* Some vendor specific files default configCLEAR_TICK_INTERRUPT() in
-portmacro.h. */
+ * portmacro.h. */
 #ifndef configCLEAR_TICK_INTERRUPT
     #define configCLEAR_TICK_INTERRUPT()
 #endif
 
 /* A critical section is exited when the critical section nesting count reaches
-this value. */
-#define portNO_CRITICAL_NESTING         ( ( uint32_t ) 0 )
+ * this value. */
+#define portNO_CRITICAL_NESTING          ( ( uint32_t ) 0 )
 
 /* In all GICs 255 can be written to the priority mask register to unmask all
-(but the lowest) interrupt priority. */
-#define portUNMASK_VALUE                ( 0xFFUL )
+ * (but the lowest) interrupt priority. */
+#define portUNMASK_VALUE                 ( 0xFFUL )
 
 /* Tasks are not created with a floating point context, but can be given a
-floating point context after they have been created.  A variable is stored as
-part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
-does not have an FPU context, or any other value if the task does have an FPU
-context. */
-#define portNO_FLOATING_POINT_CONTEXT   ( ( StackType_t ) 0 )
+ * floating point context after they have been created.  A variable is stored as
+ * part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
+ * does not have an FPU context, or any other value if the task does have an FPU
+ * context. */
+#define portNO_FLOATING_POINT_CONTEXT    ( ( StackType_t ) 0 )
 
 /* Constants required to setup the initial task context. */
-#define portINITIAL_SPSR                ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */
-#define portTHUMB_MODE_BIT              ( ( StackType_t ) 0x20 )
-#define portINTERRUPT_ENABLE_BIT        ( 0x80UL )
-#define portTHUMB_MODE_ADDRESS          ( 0x01UL )
+#define portINITIAL_SPSR                 ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */
+#define portTHUMB_MODE_BIT               ( ( StackType_t ) 0x20 )
+#define portINTERRUPT_ENABLE_BIT         ( 0x80UL )
+#define portTHUMB_MODE_ADDRESS           ( 0x01UL )
 
 /* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary
-point is zero. */
-#define portBINARY_POINT_BITS           ( ( uint8_t ) 0x03 )
+ * point is zero. */
+#define portBINARY_POINT_BITS            ( ( uint8_t ) 0x03 )
 
 /* Masks all bits in the APSR other than the mode bits. */
-#define portAPSR_MODE_BITS_MASK         ( 0x1F )
+#define portAPSR_MODE_BITS_MASK          ( 0x1F )
 
 /* The value of the mode bits in the APSR when the CPU is executing in user
-mode. */
-#define portAPSR_USER_MODE              ( 0x10 )
+ * mode. */
+#define portAPSR_USER_MODE               ( 0x10 )
 
 /* The critical section macros only mask interrupts up to an application
-determined priority level.  Sometimes it is necessary to turn interrupt off in
-the CPU itself before modifying certain hardware registers. */
-#define portCPU_IRQ_DISABLE()                                       \
-    __asm volatile ( "CPSID i" ::: "memory" );                      \
-    __asm volatile ( "DSB" );                                       \
+ * determined priority level.  Sometimes it is necessary to turn interrupt off in
+ * the CPU itself before modifying certain hardware registers. */
+#define portCPU_IRQ_DISABLE()                  \
+    __asm volatile ( "CPSID i" ::: "memory" ); \
+    __asm volatile ( "DSB" );                  \
     __asm volatile ( "ISB" );
 
-#define portCPU_IRQ_ENABLE()                                        \
-    __asm volatile ( "CPSIE i" ::: "memory" );                      \
-    __asm volatile ( "DSB" );                                       \
+#define portCPU_IRQ_ENABLE()                   \
+    __asm volatile ( "CPSIE i" ::: "memory" ); \
+    __asm volatile ( "DSB" );                  \
     __asm volatile ( "ISB" );
 
 
 /* Macro to unmask all interrupt priorities. */
-#define portCLEAR_INTERRUPT_MASK()                                  \
-{                                                                   \
-    portCPU_IRQ_DISABLE();                                          \
-    portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE;           \
-    __asm volatile (    "DSB        \n"                             \
-                        "ISB        \n" );                          \
-    portCPU_IRQ_ENABLE();                                           \
-}
+#define portCLEAR_INTERRUPT_MASK()                            \
+    {                                                         \
+        portCPU_IRQ_DISABLE();                                \
+        portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \
+        __asm volatile ( "DSB        \n"                      \
+                         "ISB        \n" );                   \
+        portCPU_IRQ_ENABLE();                                 \
+    }
 
-#define portINTERRUPT_PRIORITY_REGISTER_OFFSET      0x400UL
-#define portMAX_8_BIT_VALUE                         ( ( uint8_t ) 0xff )
-#define portBIT_0_SET                               ( ( uint8_t ) 0x01 )
+#define portINTERRUPT_PRIORITY_REGISTER_OFFSET    0x400UL
+#define portMAX_8_BIT_VALUE                       ( ( uint8_t ) 0xff )
+#define portBIT_0_SET                             ( ( uint8_t ) 0x01 )
 
 /* Let the user override the pre-loading of the initial LR with the address of
-prvTaskExitError() in case it messes up unwinding of the stack in the
-debugger. */
+ * prvTaskExitError() in case it messes up unwinding of the stack in the
+ * debugger. */
 #ifdef configTASK_RETURN_ADDRESS
-    #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
+    #define portTASK_RETURN_ADDRESS    configTASK_RETURN_ADDRESS
 #else
-    #define portTASK_RETURN_ADDRESS prvTaskExitError
+    #define portTASK_RETURN_ADDRESS    prvTaskExitError
 #endif
 
 /* The space on the stack required to hold the FPU registers.  This is 32 64-bit
-registers, plus a 32-bit status register. */
-#define portFPU_REGISTER_WORDS  ( ( 32 * 2 ) + 1 )
+ * registers, plus a 32-bit status register. */
+#define portFPU_REGISTER_WORDS    ( ( 32 * 2 ) + 1 )
 
 /*-----------------------------------------------------------*/
 
@@ -185,47 +185,49 @@ static void prvTaskExitError( void );
  * FPU registers to be saved on interrupt entry their IRQ handler must be
  * called vApplicationIRQHandler().
  */
-void vApplicationFPUSafeIRQHandler( uint32_t ulICCIAR ) __attribute__((weak) );
+void vApplicationFPUSafeIRQHandler( uint32_t ulICCIAR ) __attribute__( ( weak ) );
 
 /*-----------------------------------------------------------*/
 
 /* A variable is used to keep track of the critical section nesting.  This
-variable has to be stored as part of the task context and must be initialised to
-a non zero value to ensure interrupts don't inadvertently become unmasked before
-the scheduler starts.  As it is stored as part of the task context it will
-automatically be set to 0 when the first task is started. */
+ * variable has to be stored as part of the task context and must be initialised to
+ * a non zero value to ensure interrupts don't inadvertently become unmasked before
+ * the scheduler starts.  As it is stored as part of the task context it will
+ * automatically be set to 0 when the first task is started. */
 volatile uint32_t ulCriticalNesting = 9999UL;
 
 /* Saved as part of the task context.  If ulPortTaskHasFPUContext is non-zero then
-a floating point context must be saved and restored for the task. */
+ * a floating point context must be saved and restored for the task. */
 volatile uint32_t ulPortTaskHasFPUContext = pdFALSE;
 
 /* Set to 1 to pend a context switch from an ISR. */
 volatile uint32_t ulPortYieldRequired = pdFALSE;
 
 /* Counts the interrupt nesting depth.  A context switch is only performed if
-if the nesting depth is 0. */
+ * if the nesting depth is 0. */
 volatile uint32_t ulPortInterruptNesting = 0UL;
 
 /* Used in the asm file. */
-__attribute__(( used )) const uint32_t ulICCIAR = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS;
-__attribute__(( used )) const uint32_t ulICCEOIR = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS;
-__attribute__(( used )) const uint32_t ulICCPMR = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS;
-__attribute__(( used )) const uint32_t ulMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
+__attribute__( ( used ) ) const uint32_t ulICCIAR = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS;
+__attribute__( ( used ) ) const uint32_t ulICCEOIR = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS;
+__attribute__( ( used ) ) const uint32_t ulICCPMR = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS;
+__attribute__( ( used ) ) const uint32_t ulMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
 
 /*-----------------------------------------------------------*/
 
 /*
  * See header file for description.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
     /* Setup the initial stack of the task.  The stack is set exactly as
-    expected by the portRESTORE_CONTEXT() macro.
-
-    The fist real value on the stack is the status register, which is set for
-    system mode, with interrupts enabled.  A few NULLs are added first to ensure
-    GDB does not try decoding a non-existent return address. */
+     * expected by the portRESTORE_CONTEXT() macro.
+     *
+     * The fist real value on the stack is the status register, which is set for
+     * system mode, with interrupts enabled.  A few NULLs are added first to ensure
+     * GDB does not try decoding a non-existent return address. */
     *pxTopOfStack = ( StackType_t ) NULL;
     pxTopOfStack--;
     *pxTopOfStack = ( StackType_t ) NULL;
@@ -247,51 +249,51 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
     pxTopOfStack--;
 
     /* Next all the registers other than the stack pointer. */
-    *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;    /* R14 */
+    *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* R14 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
+    *pxTopOfStack = ( StackType_t ) 0x12121212;              /* R12 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
+    *pxTopOfStack = ( StackType_t ) 0x11111111;              /* R11 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
+    *pxTopOfStack = ( StackType_t ) 0x10101010;              /* R10 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
+    *pxTopOfStack = ( StackType_t ) 0x09090909;              /* R9 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
+    *pxTopOfStack = ( StackType_t ) 0x08080808;              /* R8 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
+    *pxTopOfStack = ( StackType_t ) 0x07070707;              /* R7 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
+    *pxTopOfStack = ( StackType_t ) 0x06060606;              /* R6 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
+    *pxTopOfStack = ( StackType_t ) 0x05050505;              /* R5 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
+    *pxTopOfStack = ( StackType_t ) 0x04040404;              /* R4 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
+    *pxTopOfStack = ( StackType_t ) 0x03030303;              /* R3 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
+    *pxTopOfStack = ( StackType_t ) 0x02020202;              /* R2 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
+    *pxTopOfStack = ( StackType_t ) 0x01010101;              /* R1 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+    *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */
     pxTopOfStack--;
 
     /* The task will start with a critical nesting count of 0 as interrupts are
-    enabled. */
+     * enabled. */
     *pxTopOfStack = portNO_CRITICAL_NESTING;
 
-    #if( configUSE_TASK_FPU_SUPPORT == 1 )
+    #if ( configUSE_TASK_FPU_SUPPORT == 1 )
     {
         /* The task will start without a floating point context.  A task that
-        uses the floating point hardware must call vPortTaskUsesFPU() before
-        executing any floating point instructions. */
+         * uses the floating point hardware must call vPortTaskUsesFPU() before
+         * executing any floating point instructions. */
         pxTopOfStack--;
         *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
     }
-    #elif( configUSE_TASK_FPU_SUPPORT == 2 )
+    #elif ( configUSE_TASK_FPU_SUPPORT == 2 )
     {
         /* The task will start with a floating point context.  Leave enough
-        space for the registers - and ensure they are initialised to 0. */
+         * space for the registers - and ensure they are initialised to 0. */
         pxTopOfStack -= portFPU_REGISTER_WORDS;
         memset( pxTopOfStack, 0x00, portFPU_REGISTER_WORDS * sizeof( StackType_t ) );
 
@@ -299,11 +301,11 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
         *pxTopOfStack = pdTRUE;
         ulPortTaskHasFPUContext = pdTRUE;
     }
-    #else
+    #else /* if ( configUSE_TASK_FPU_SUPPORT == 1 ) */
     {
-        #error Invalid configUSE_TASK_FPU_SUPPORT setting - configUSE_TASK_FPU_SUPPORT must be set to 1, 2, or left undefined.
+        #error "Invalid configUSE_TASK_FPU_SUPPORT setting - configUSE_TASK_FPU_SUPPORT must be set to 1, 2, or left undefined."
     }
-    #endif
+    #endif /* if ( configUSE_TASK_FPU_SUPPORT == 1 ) */
 
     return pxTopOfStack;
 }
@@ -312,34 +314,37 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
 static void prvTaskExitError( void )
 {
     /* A function that implements a task must not exit or attempt to return to
-    its caller as there is nothing to return to.  If a task wants to exit it
-    should instead call vTaskDelete( NULL ).
-
-    Artificially force an assert() to be triggered if configASSERT() is
-    defined, then stop here so application writers can catch the error. */
+     * its caller as there is nothing to return to.  If a task wants to exit it
+     * should instead call vTaskDelete( NULL ).
+     *
+     * Artificially force an assert() to be triggered if configASSERT() is
+     * defined, then stop here so application writers can catch the error. */
     configASSERT( ulPortInterruptNesting == ~0UL );
     portDISABLE_INTERRUPTS();
-    for( ;; );
+
+    for( ; ; )
+    {
+    }
 }
 /*-----------------------------------------------------------*/
 
 BaseType_t xPortStartScheduler( void )
 {
-uint32_t ulAPSR;
+    uint32_t ulAPSR;
 
-    #if( configASSERT_DEFINED == 1 )
+    #if ( configASSERT_DEFINED == 1 )
     {
         volatile uint8_t ucOriginalPriority;
         volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + portINTERRUPT_PRIORITY_REGISTER_OFFSET );
         volatile uint8_t ucMaxPriorityValue;
 
         /* Determine how many priority bits are implemented in the GIC.
-
-        Save the interrupt priority value that is about to be clobbered. */
+         *
+         * Save the interrupt priority value that is about to be clobbered. */
         ucOriginalPriority = *pucFirstUserPriorityRegister;
 
         /* Determine the number of priority bits available.  First write to
-        all possible bits. */
+         * all possible bits. */
         *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
 
         /* Read the value back to see how many bits stuck. */
@@ -352,35 +357,35 @@ uint32_t ulAPSR;
         }
 
         /* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read
-        value. */
+         * value. */
         configASSERT( ucMaxPriorityValue == portLOWEST_INTERRUPT_PRIORITY );
 
         /* Restore the clobbered interrupt priority register to its original
-        value. */
+         * value. */
         *pucFirstUserPriorityRegister = ucOriginalPriority;
     }
     #endif /* configASSERT_DEFINED */
 
 
     /* Only continue if the CPU is not in User mode.  The CPU must be in a
-    Privileged mode for the scheduler to start. */
-    __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) :: "memory" );
+     * Privileged mode for the scheduler to start. */
+    __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR )::"memory" );
     ulAPSR &= portAPSR_MODE_BITS_MASK;
     configASSERT( ulAPSR != portAPSR_USER_MODE );
 
     if( ulAPSR != portAPSR_USER_MODE )
     {
         /* Only continue if the binary point value is set to its lowest possible
-        setting.  See the comments in vPortValidateInterruptPriority() below for
-        more information. */
+         * setting.  See the comments in vPortValidateInterruptPriority() below for
+         * more information. */
         configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
 
         if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )
         {
             /* Interrupts are turned off in the CPU itself to ensure tick does
-            not execute while the scheduler is being started.  Interrupts are
-            automatically turned back on in the CPU when the first task starts
-            executing. */
+             * not execute while the scheduler is being started.  Interrupts are
+             * automatically turned back on in the CPU when the first task starts
+             * executing. */
             portCPU_IRQ_DISABLE();
 
             /* Start the timer that generates the tick ISR. */
@@ -392,10 +397,10 @@ uint32_t ulAPSR;
     }
 
     /* Will only get here if vTaskStartScheduler() was called with the CPU in
-    a non-privileged mode or the binary point register was not set to its lowest
-    possible value.  prvTaskExitError() is referenced to prevent a compiler
-    warning about it being defined but not referenced in the case that the user
-    defines their own exit address. */
+     * a non-privileged mode or the binary point register was not set to its lowest
+     * possible value.  prvTaskExitError() is referenced to prevent a compiler
+     * warning about it being defined but not referenced in the case that the user
+     * defines their own exit address. */
     ( void ) prvTaskExitError;
     return 0;
 }
@@ -404,7 +409,7 @@ uint32_t ulAPSR;
 void vPortEndScheduler( void )
 {
     /* Not implemented in ports where there is nothing to return to.
-    Artificially force an assert. */
+     * Artificially force an assert. */
     configASSERT( ulCriticalNesting == 1000UL );
 }
 /*-----------------------------------------------------------*/
@@ -414,16 +419,16 @@ void vPortEnterCritical( void )
     /* Mask interrupts up to the max syscall interrupt priority. */
     ulPortSetInterruptMask();
 
-    /* Now interrupts are disabled ulCriticalNesting can be accessed
-    directly.  Increment ulCriticalNesting to keep a count of how many times
-    portENTER_CRITICAL() has been called. */
+    /* Now that interrupts are disabled, ulCriticalNesting can be accessed
+     * directly.  Increment ulCriticalNesting to keep a count of how many times
+     * portENTER_CRITICAL() has been called. */
     ulCriticalNesting++;
 
     /* This is not the interrupt safe version of the enter critical function so
-    assert() if it is being called from an interrupt context.  Only API
-    functions that end in "FromISR" can be used in an interrupt.  Only assert if
-    the critical nesting count is 1 to protect against recursive calls if the
-    assert function also uses a critical section. */
+     * assert() if it is being called from an interrupt context.  Only API
+     * functions that end in "FromISR" can be used in an interrupt.  Only assert if
+     * the critical nesting count is 1 to protect against recursive calls if the
+     * assert function also uses a critical section. */
     if( ulCriticalNesting == 1 )
     {
         configASSERT( ulPortInterruptNesting == 0 );
@@ -436,15 +441,15 @@ void vPortExitCritical( void )
     if( ulCriticalNesting > portNO_CRITICAL_NESTING )
     {
         /* Decrement the nesting count as the critical section is being
-        exited. */
+         * exited. */
         ulCriticalNesting--;
 
         /* If the nesting level has reached zero then all interrupt
-        priorities must be re-enabled. */
+         * priorities must be re-enabled. */
         if( ulCriticalNesting == portNO_CRITICAL_NESTING )
         {
             /* Critical nesting has reached zero so all interrupt priorities
-            should be unmasked. */
+             * should be unmasked. */
             portCLEAR_INTERRUPT_MASK();
         }
     }
@@ -454,14 +459,14 @@ void vPortExitCritical( void )
 void FreeRTOS_Tick_Handler( void )
 {
     /* Set interrupt mask before altering scheduler structures.   The tick
-    handler runs at the lowest priority, so interrupts cannot already be masked,
-    so there is no need to save and restore the current mask value.  It is
-    necessary to turn off interrupts in the CPU itself while the ICCPMR is being
-    updated. */
+     * handler runs at the lowest priority, so interrupts cannot already be masked,
+     * so there is no need to save and restore the current mask value.  It is
+     * necessary to turn off interrupts in the CPU itself while the ICCPMR is being
+     * updated. */
     portCPU_IRQ_DISABLE();
     portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
-    __asm volatile (    "dsb        \n"
-                        "isb        \n" ::: "memory" );
+    __asm volatile ( "dsb        \n"
+                     "isb        \n" ::: "memory" );
     portCPU_IRQ_ENABLE();
 
     /* Increment the RTOS tick. */
@@ -476,18 +481,18 @@ void FreeRTOS_Tick_Handler( void )
 }
 /*-----------------------------------------------------------*/
 
-#if( configUSE_TASK_FPU_SUPPORT != 2 )
+#if ( configUSE_TASK_FPU_SUPPORT != 2 )
 
     void vPortTaskUsesFPU( void )
     {
-    uint32_t ulInitialFPSCR = 0;
+        uint32_t ulInitialFPSCR = 0;
 
         /* A task is registering the fact that it needs an FPU context.  Set the
-        FPU flag (which is saved as part of the task context). */
+         * FPU flag (which is saved as part of the task context). */
         ulPortTaskHasFPUContext = pdTRUE;
 
         /* Initialise the floating point status register. */
-        __asm volatile ( "FMXR  FPSCR, %0" :: "r" (ulInitialFPSCR) : "memory" );
+        __asm volatile ( "FMXR  FPSCR, %0" ::"r" ( ulInitialFPSCR ) : "memory" );
     }
 
 #endif /* configUSE_TASK_FPU_SUPPORT */
@@ -504,11 +509,12 @@ void vPortClearInterruptMask( uint32_t ulNewMaskValue )
 
 uint32_t ulPortSetInterruptMask( void )
 {
-uint32_t ulReturn;
+    uint32_t ulReturn;
 
     /* Interrupt in the CPU must be turned off while the ICCPMR is being
-    updated. */
+     * updated. */
     portCPU_IRQ_DISABLE();
+
     if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
     {
         /* Interrupts were already masked. */
@@ -518,45 +524,46 @@ uint32_t ulReturn;
     {
         ulReturn = pdFALSE;
         portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
-        __asm volatile (    "dsb        \n"
-                            "isb        \n" ::: "memory" );
+        __asm volatile ( "dsb        \n"
+                         "isb        \n" ::: "memory" );
     }
+
     portCPU_IRQ_ENABLE();
 
     return ulReturn;
 }
 /*-----------------------------------------------------------*/
 
-#if( configASSERT_DEFINED == 1 )
+#if ( configASSERT_DEFINED == 1 )
 
     void vPortValidateInterruptPriority( void )
     {
         /* The following assertion will fail if a service routine (ISR) for
-        an interrupt that has been assigned a priority above
-        configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
-        function.  ISR safe FreeRTOS API functions must *only* be called
-        from interrupts that have been assigned a priority at or below
-        configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
-        Numerically low interrupt priority numbers represent logically high
-        interrupt priorities, therefore the priority of the interrupt must
-        be set to a value equal to or numerically *higher* than
-        configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
-        FreeRTOS maintains separate thread and ISR API functions to ensure
-        interrupt entry is as fast and simple as possible. */
+         * an interrupt that has been assigned a priority above
+         * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+         * function.  ISR safe FreeRTOS API functions must *only* be called
+         * from interrupts that have been assigned a priority at or below
+         * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+         *
+         * Numerically low interrupt priority numbers represent logically high
+         * interrupt priorities, therefore the priority of the interrupt must
+         * be set to a value equal to or numerically *higher* than
+         * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+         *
+         * FreeRTOS maintains separate thread and ISR API functions to ensure
+         * interrupt entry is as fast and simple as possible. */
         configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
 
         /* Priority grouping:  The interrupt controller (GIC) allows the bits
-        that define each interrupt's priority to be split between bits that
-        define the interrupt's pre-emption priority bits and bits that define
-        the interrupt's sub-priority.  For simplicity all bits must be defined
-        to be pre-emption priority bits.  The following assertion will fail if
-        this is not the case (if some bits represent a sub-priority).
-
-        The priority grouping is configured by the GIC's binary point register
-        (ICCBPR).  Writting 0 to ICCBPR will ensure it is set to its lowest
-        possible value (which may be above 0). */
+         * that define each interrupt's priority to be split between bits that
+         * define the interrupt's pre-emption priority bits and bits that define
+         * the interrupt's sub-priority.  For simplicity all bits must be defined
+         * to be pre-emption priority bits.  The following assertion will fail if
+         * this is not the case (if some bits represent a sub-priority).
+         *
+         * The priority grouping is configured by the GIC's binary point register
+         * (ICCBPR).  Writting 0 to ICCBPR will ensure it is set to its lowest
+         * possible value (which may be above 0). */
         configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
     }
 
diff --git a/portable/GCC/ARM_CA9/portmacro.h b/portable/GCC/ARM_CA9/portmacro.h
index 6f1f22724..bd9b36dd9 100644
--- a/portable/GCC/ARM_CA9/portmacro.h
+++ b/portable/GCC/ARM_CA9/portmacro.h
@@ -46,54 +46,54 @@
  */
 
 /* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint32_t
-#define portBASE_TYPE   long
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
-typedef uint32_t TickType_t;
-#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+typedef uint32_t         TickType_t;
+#define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-not need to be guarded with a critical section. */
-#define portTICK_TYPE_IS_ATOMIC 1
+ * not need to be guarded with a critical section. */
+#define portTICK_TYPE_IS_ATOMIC    1
 
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portSTACK_GROWTH            ( -1 )
-#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT          8
+#define portSTACK_GROWTH      ( -1 )
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT    8
 
 /*-----------------------------------------------------------*/
 
 /* Task utilities. */
 
 /* Called at the end of an ISR that can cause a context switch. */
-#define portEND_SWITCHING_ISR( xSwitchRequired )\
-{                                               \
-extern uint32_t ulPortYieldRequired;            \
-                                                \
-    if( xSwitchRequired != pdFALSE )            \
-    {                                           \
-        ulPortYieldRequired = pdTRUE;           \
-    }                                           \
-}
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+    {                                            \
+        extern uint32_t ulPortYieldRequired;     \
+                                                 \
+        if( xSwitchRequired != pdFALSE )         \
+        {                                        \
+            ulPortYieldRequired = pdTRUE;        \
+        }                                        \
+    }
 
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
-#define portYIELD() __asm volatile ( "SWI 0" ::: "memory" );
+#define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
+#define portYIELD()                __asm volatile ( "SWI 0" ::: "memory" );
 
 
 /*-----------------------------------------------------------
- * Critical section control
- *----------------------------------------------------------*/
+* Critical section control
+*----------------------------------------------------------*/
 
 extern void vPortEnterCritical( void );
 extern void vPortExitCritical( void );
@@ -102,105 +102,106 @@ extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
 extern void vPortInstallFreeRTOSVectorTable( void );
 
 /* These macros do not globally disable/enable interrupts.  They do mask off
-interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
-#define portENTER_CRITICAL()        vPortEnterCritical();
-#define portEXIT_CRITICAL()         vPortExitCritical();
-#define portDISABLE_INTERRUPTS()    ulPortSetInterruptMask()
-#define portENABLE_INTERRUPTS()     vPortClearInterruptMask( 0 )
-#define portSET_INTERRUPT_MASK_FROM_ISR()       ulPortSetInterruptMask()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)    vPortClearInterruptMask(x)
+ * interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
+#define portENTER_CRITICAL()                      vPortEnterCritical();
+#define portEXIT_CRITICAL()                       vPortExitCritical();
+#define portDISABLE_INTERRUPTS()                  ulPortSetInterruptMask()
+#define portENABLE_INTERRUPTS()                   vPortClearInterruptMask( 0 )
+#define portSET_INTERRUPT_MASK_FROM_ISR()         ulPortSetInterruptMask()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vPortClearInterruptMask( x )
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site.  These are
-not required for this port but included in case common demo code that uses these
-macros is used. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )  void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )    void vFunction( void *pvParameters )
+ * not required for this port but included in case common demo code that uses these
+ * macros is used. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
 /* Prototype of the FreeRTOS tick handler.  This must be installed as the
-handler for whichever peripheral is used to generate the RTOS tick. */
+ * handler for whichever peripheral is used to generate the RTOS tick. */
 void FreeRTOS_Tick_Handler( void );
 
 /* If configUSE_TASK_FPU_SUPPORT is set to 1 (or left undefined) then tasks are
-created without an FPU context and must call vPortTaskUsesFPU() to give
-themselves an FPU context before using any FPU instructions.  If
-configUSE_TASK_FPU_SUPPORT is set to 2 then all tasks will have an FPU context
-by default. */
-#if( configUSE_TASK_FPU_SUPPORT != 2 )
+ * created without an FPU context and must call vPortTaskUsesFPU() to give
+ * themselves an FPU context before using any FPU instructions.  If
+ * configUSE_TASK_FPU_SUPPORT is set to 2 then all tasks will have an FPU context
+ * by default. */
+#if ( configUSE_TASK_FPU_SUPPORT != 2 )
     void vPortTaskUsesFPU( void );
 #else
-    /* Each task has an FPU context already, so define this function away to
-    nothing to prevent it being called accidentally. */
+
+/* Each task has an FPU context already, so define this function away to
+ * nothing to prevent it being called accidentally. */
     #define vPortTaskUsesFPU()
 #endif
-#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
+#define portTASK_USES_FLOATING_POINT()    vPortTaskUsesFPU()
 
-#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
-#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
+#define portLOWEST_INTERRUPT_PRIORITY           ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
+#define portLOWEST_USABLE_INTERRUPT_PRIORITY    ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
 
 /* Architecture specific optimisations. */
 #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-    #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+    #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
 #endif
 
 #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
 
-    /* Store/clear the ready priorities in a bit map. */
-    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+/* Store/clear the ready priorities in a bit map. */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 
-    /*-----------------------------------------------------------*/
+/*-----------------------------------------------------------*/
 
-    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __builtin_clz( uxReadyPriorities ) )
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ( uint32_t ) __builtin_clz( uxReadyPriorities ) )
 
 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 
 #ifdef configASSERT
     void vPortValidateInterruptPriority( void );
-    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()  vPortValidateInterruptPriority()
+    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
 #endif /* configASSERT */
 
-#define portNOP() __asm volatile( "NOP" )
-#define portINLINE __inline
+#define portNOP()                                         __asm volatile ( "NOP" )
+#define portINLINE    __inline
 
 /* The number of bits to shift for an interrupt priority is dependent on the
-number of bits implemented by the interrupt controller. */
+ * number of bits implemented by the interrupt controller. */
 #if configUNIQUE_INTERRUPT_PRIORITIES == 16
-    #define portPRIORITY_SHIFT 4
-    #define portMAX_BINARY_POINT_VALUE  3
+    #define portPRIORITY_SHIFT            4
+    #define portMAX_BINARY_POINT_VALUE    3
 #elif configUNIQUE_INTERRUPT_PRIORITIES == 32
-    #define portPRIORITY_SHIFT 3
-    #define portMAX_BINARY_POINT_VALUE  2
+    #define portPRIORITY_SHIFT            3
+    #define portMAX_BINARY_POINT_VALUE    2
 #elif configUNIQUE_INTERRUPT_PRIORITIES == 64
-    #define portPRIORITY_SHIFT 2
-    #define portMAX_BINARY_POINT_VALUE  1
+    #define portPRIORITY_SHIFT            2
+    #define portMAX_BINARY_POINT_VALUE    1
 #elif configUNIQUE_INTERRUPT_PRIORITIES == 128
-    #define portPRIORITY_SHIFT 1
-    #define portMAX_BINARY_POINT_VALUE  0
+    #define portPRIORITY_SHIFT            1
+    #define portMAX_BINARY_POINT_VALUE    0
 #elif configUNIQUE_INTERRUPT_PRIORITIES == 256
-    #define portPRIORITY_SHIFT 0
-    #define portMAX_BINARY_POINT_VALUE  0
-#else
+    #define portPRIORITY_SHIFT            0
+    #define portMAX_BINARY_POINT_VALUE    0
+#else /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */
     #error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting.  configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware
-#endif
+#endif /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */
 
 /* Interrupt controller access addresses. */
-#define portICCPMR_PRIORITY_MASK_OFFSET                         ( 0x04 )
-#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET                 ( 0x0C )
-#define portICCEOIR_END_OF_INTERRUPT_OFFSET                     ( 0x10 )
-#define portICCBPR_BINARY_POINT_OFFSET                          ( 0x08 )
-#define portICCRPR_RUNNING_PRIORITY_OFFSET                      ( 0x14 )
+#define portICCPMR_PRIORITY_MASK_OFFSET                      ( 0x04 )
+#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET              ( 0x0C )
+#define portICCEOIR_END_OF_INTERRUPT_OFFSET                  ( 0x10 )
+#define portICCBPR_BINARY_POINT_OFFSET                       ( 0x08 )
+#define portICCRPR_RUNNING_PRIORITY_OFFSET                   ( 0x14 )
 
-#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS      ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )
-#define portICCPMR_PRIORITY_MASK_REGISTER                   ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )
-#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS   ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )
-#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS       ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )
-#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS           ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )
-#define portICCBPR_BINARY_POINT_REGISTER                    ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
-#define portICCRPR_RUNNING_PRIORITY_REGISTER                ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )
+#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS       ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )
+#define portICCPMR_PRIORITY_MASK_REGISTER                    ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )
+#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS    ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )
+#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS        ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )
+#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS            ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )
+#define portICCBPR_BINARY_POINT_REGISTER                     ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
+#define portICCRPR_RUNNING_PRIORITY_REGISTER                 ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )
 
-#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+#define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/GCC/ARM_CM0/port.c b/portable/GCC/ARM_CM0/port.c
index 261c12d82..e67a10fb5 100644
--- a/portable/GCC/ARM_CM0/port.c
+++ b/portable/GCC/ARM_CM0/port.c
@@ -205,20 +205,20 @@ void vPortStartFirstTask( void )
      * Not all M0 parts have the application vector table at address 0. */
     __asm volatile (
         "   .syntax unified             \n"
-        "   ldr  r2, pxCurrentTCBConst2 \n"/* Obtain location of pxCurrentTCB. */
+        "   ldr  r2, pxCurrentTCBConst2 \n"     /* Obtain location of pxCurrentTCB. */
         "   ldr  r3, [r2]               \n"
-        "   ldr  r0, [r3]               \n"/* The first item in pxCurrentTCB is the task top of stack. */
-        "   adds r0, #32                    \n"/* Discard everything up to r0. */
-        "   msr  psp, r0                    \n"/* This is now the new top of stack to use in the task. */
-        "   movs r0, #2                 \n"/* Switch to the psp stack. */
+        "   ldr  r0, [r3]               \n"     /* The first item in pxCurrentTCB is the task top of stack. */
+        "   adds r0, #32                    \n" /* Discard everything up to r0. */
+        "   msr  psp, r0                    \n" /* This is now the new top of stack to use in the task. */
+        "   movs r0, #2                 \n"     /* Switch to the psp stack. */
         "   msr  CONTROL, r0                \n"
         "   isb                         \n"
-        "   pop  {r0-r5}                    \n"/* Pop the registers that are saved automatically. */
-        "   mov  lr, r5                 \n"/* lr is now in r5. */
-        "   pop  {r3}                   \n"/* Return address is now in r3. */
-        "   pop  {r2}                   \n"/* Pop and discard XPSR. */
-        "   cpsie i                     \n"/* The first task has its context and interrupts can be enabled. */
-        "   bx   r3                     \n"/* Finally, jump to the user defined task code. */
+        "   pop  {r0-r5}                    \n" /* Pop the registers that are saved automatically. */
+        "   mov  lr, r5                 \n"     /* lr is now in r5. */
+        "   pop  {r3}                   \n"     /* Return address is now in r3. */
+        "   pop  {r2}                   \n"     /* Pop and discard XPSR. */
+        "   cpsie i                     \n"     /* The first task has its context and interrupts can be enabled. */
+        "   bx   r3                     \n"     /* Finally, jump to the user defined task code. */
         "                               \n"
         "   .align 4                    \n"
         "pxCurrentTCBConst2: .word pxCurrentTCB   "
@@ -330,13 +330,13 @@ void xPortPendSVHandler( void )
         "   .syntax unified                     \n"
         "   mrs r0, psp                         \n"
         "                                       \n"
-        "   ldr r3, pxCurrentTCBConst           \n"/* Get the location of the current TCB. */
+        "   ldr r3, pxCurrentTCBConst           \n" /* Get the location of the current TCB. */
         "   ldr r2, [r3]                        \n"
         "                                       \n"
-        "   subs r0, r0, #32                    \n"/* Make space for the remaining low registers. */
-        "   str r0, [r2]                        \n"/* Save the new top of stack. */
-        "   stmia r0!, {r4-r7}                  \n"/* Store the low registers that are not saved automatically. */
-        "   mov r4, r8                          \n"/* Store the high registers. */
+        "   subs r0, r0, #32                    \n" /* Make space for the remaining low registers. */
+        "   str r0, [r2]                        \n" /* Save the new top of stack. */
+        "   stmia r0!, {r4-r7}                  \n" /* Store the low registers that are not saved automatically. */
+        "   mov r4, r8                          \n" /* Store the high registers. */
         "   mov r5, r9                          \n"
         "   mov r6, r10                         \n"
         "   mov r7, r11                         \n"
@@ -346,21 +346,21 @@ void xPortPendSVHandler( void )
         "   cpsid i                             \n"
         "   bl vTaskSwitchContext               \n"
         "   cpsie i                             \n"
-        "   pop {r2, r3}                        \n"/* lr goes in r3. r2 now holds tcb pointer. */
+        "   pop {r2, r3}                        \n" /* lr goes in r3. r2 now holds tcb pointer. */
         "                                       \n"
         "   ldr r1, [r2]                        \n"
-        "   ldr r0, [r1]                        \n"/* The first item in pxCurrentTCB is the task top of stack. */
-        "   adds r0, r0, #16                    \n"/* Move to the high registers. */
-        "   ldmia r0!, {r4-r7}                  \n"/* Pop the high registers. */
+        "   ldr r0, [r1]                        \n" /* The first item in pxCurrentTCB is the task top of stack. */
+        "   adds r0, r0, #16                    \n" /* Move to the high registers. */
+        "   ldmia r0!, {r4-r7}                  \n" /* Pop the high registers. */
         "   mov r8, r4                          \n"
         "   mov r9, r5                          \n"
         "   mov r10, r6                         \n"
         "   mov r11, r7                         \n"
         "                                       \n"
-        "   msr psp, r0                         \n"/* Remember the new top of stack for the task. */
+        "   msr psp, r0                         \n" /* Remember the new top of stack for the task. */
         "                                       \n"
-        "   subs r0, r0, #32                    \n"/* Go back for the low registers that are not automatically restored. */
-        "   ldmia r0!, {r4-r7}                  \n"/* Pop low registers.  */
+        "   subs r0, r0, #32                    \n" /* Go back for the low registers that are not automatically restored. */
+        "   ldmia r0!, {r4-r7}                  \n" /* Pop low registers.  */
         "                                       \n"
         "   bx r3                               \n"
         "                                       \n"
diff --git a/portable/GCC/ARM_CM0/portmacro.h b/portable/GCC/ARM_CM0/portmacro.h
index 14375bf95..df571eb53 100644
--- a/portable/GCC/ARM_CM0/portmacro.h
+++ b/portable/GCC/ARM_CM0/portmacro.h
@@ -87,9 +87,9 @@ extern void vPortYield( void );
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
 #define portYIELD()                vPortYield()
-#define portEND_SWITCHING_ISR( xSwitchRequired )                                     \
-        do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
-        while( 0 )
+#define portEND_SWITCHING_ISR( xSwitchRequired )                                 \
+    do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
+    while( 0 )
 #define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/GCC/ARM_CM23/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM23/non_secure/mpu_wrappers_v2_asm.c
index f6fb0e778..00c8bcfa8 100644
--- a/portable/GCC/ARM_CM23/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM23/non_secure/mpu_wrappers_v2_asm.c
@@ -44,2344 +44,2344 @@
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-#if ( INCLUDE_xTaskDelayUntil == 1 )
+    #if ( INCLUDE_xTaskDelayUntil == 1 )
 
-BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
-                                const TickType_t xTimeIncrement ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
+                                        const TickType_t xTimeIncrement ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
-                                const TickType_t xTimeIncrement ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskDelayUntilImpl                       \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTaskDelayUntil_Unpriv                        \n"
-        " MPU_xTaskDelayUntil_Priv:                             \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTaskDelayUntilImpl                         \n"
-        " MPU_xTaskDelayUntil_Unpriv:                           \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskDelayUntilImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
+                                        const TickType_t xTimeIncrement ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskDelayUntilImpl                       \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xTaskDelayUntil_Unpriv                        \n"
+                " MPU_xTaskDelayUntil_Priv:                             \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xTaskDelayUntilImpl                         \n"
+                " MPU_xTaskDelayUntil_Unpriv:                           \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskDelayUntilImpl                        \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */
+    #endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_xTaskAbortDelay == 1 )
+    #if ( INCLUDE_xTaskAbortDelay == 1 )
 
-BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskAbortDelayImpl                       \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTaskAbortDelay_Unpriv                        \n"
-        " MPU_xTaskAbortDelay_Priv:                             \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTaskAbortDelayImpl                         \n"
-        " MPU_xTaskAbortDelay_Unpriv:                           \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskAbortDelayImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskAbortDelayImpl                       \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xTaskAbortDelay_Unpriv                        \n"
+                " MPU_xTaskAbortDelay_Priv:                             \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xTaskAbortDelayImpl                         \n"
+                " MPU_xTaskAbortDelay_Unpriv:                           \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskAbortDelayImpl                        \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */
+    #endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_vTaskDelay == 1 )
+    #if ( INCLUDE_vTaskDelay == 1 )
 
-void MPU_vTaskDelay( const TickType_t xTicksToDelay ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskDelay( const TickType_t xTicksToDelay ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskDelayImpl                            \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_vTaskDelay_Unpriv                             \n"
-        " MPU_vTaskDelay_Priv:                                  \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_vTaskDelayImpl                              \n"
-        " MPU_vTaskDelay_Unpriv:                                \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskDelayImpl                             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskDelayImpl                            \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_vTaskDelay_Unpriv                             \n"
+                " MPU_vTaskDelay_Priv:                                  \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_vTaskDelayImpl                              \n"
+                " MPU_vTaskDelay_Unpriv:                                \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskDelayImpl                             \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_vTaskDelay == 1 ) */
+    #endif /* if ( INCLUDE_vTaskDelay == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_uxTaskPriorityGet == 1 )
+    #if ( INCLUDE_uxTaskPriorityGet == 1 )
 
-UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskPriorityGetImpl                     \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_uxTaskPriorityGet_Unpriv                      \n"
-        " MPU_uxTaskPriorityGet_Priv:                           \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_uxTaskPriorityGetImpl                       \n"
-        " MPU_uxTaskPriorityGet_Unpriv:                         \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskPriorityGetImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskPriorityGetImpl                     \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_uxTaskPriorityGet_Unpriv                      \n"
+                " MPU_uxTaskPriorityGet_Priv:                           \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_uxTaskPriorityGetImpl                       \n"
+                " MPU_uxTaskPriorityGet_Unpriv:                         \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskPriorityGetImpl                      \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */
+    #endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_eTaskGetState == 1 )
+    #if ( INCLUDE_eTaskGetState == 1 )
 
-eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_eTaskGetStateImpl                         \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_eTaskGetState_Unpriv                          \n"
-        " MPU_eTaskGetState_Priv:                               \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_eTaskGetStateImpl                           \n"
-        " MPU_eTaskGetState_Unpriv:                             \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_eTaskGetStateImpl                          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_eTaskGetStateImpl                         \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_eTaskGetState_Unpriv                          \n"
+                " MPU_eTaskGetState_Priv:                               \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_eTaskGetStateImpl                           \n"
+                " MPU_eTaskGetState_Unpriv:                             \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_eTaskGetStateImpl                          \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_eTaskGetState == 1 ) */
+    #endif /* if ( INCLUDE_eTaskGetState == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-void MPU_vTaskGetInfo( TaskHandle_t xTask,
-                       TaskStatus_t * pxTaskStatus,
-                       BaseType_t xGetFreeStackSpace,
-                       eTaskState eState ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskGetInfo( TaskHandle_t xTask,
+                               TaskStatus_t * pxTaskStatus,
+                               BaseType_t xGetFreeStackSpace,
+                               eTaskState eState ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskGetInfo( TaskHandle_t xTask,
-                       TaskStatus_t * pxTaskStatus,
-                       BaseType_t xGetFreeStackSpace,
-                       eTaskState eState ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskGetInfoImpl                          \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_vTaskGetInfo_Unpriv                           \n"
-        " MPU_vTaskGetInfo_Priv:                                \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_vTaskGetInfoImpl                            \n"
-        " MPU_vTaskGetInfo_Unpriv:                              \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskGetInfoImpl                           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskGetInfo( TaskHandle_t xTask,
+                               TaskStatus_t * pxTaskStatus,
+                               BaseType_t xGetFreeStackSpace,
+                               eTaskState eState ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskGetInfoImpl                          \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_vTaskGetInfo_Unpriv                           \n"
+                " MPU_vTaskGetInfo_Priv:                                \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_vTaskGetInfoImpl                            \n"
+                " MPU_vTaskGetInfo_Unpriv:                              \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskGetInfoImpl                           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
+    #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
+    #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
 
-TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetIdleTaskHandleImpl                \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTaskGetIdleTaskHandle_Unpriv                 \n"
-        " MPU_xTaskGetIdleTaskHandle_Priv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTaskGetIdleTaskHandleImpl                  \n"
-        " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetIdleTaskHandleImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetIdleTaskHandleImpl                \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xTaskGetIdleTaskHandle_Unpriv                 \n"
+                " MPU_xTaskGetIdleTaskHandle_Priv:                      \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xTaskGetIdleTaskHandleImpl                  \n"
+                " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetIdleTaskHandleImpl                 \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */
+    #endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_vTaskSuspend == 1 )
+    #if ( INCLUDE_vTaskSuspend == 1 )
 
-void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSuspendImpl                          \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_vTaskSuspend_Unpriv                           \n"
-        " MPU_vTaskSuspend_Priv:                                \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_vTaskSuspendImpl                            \n"
-        " MPU_vTaskSuspend_Unpriv:                              \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSuspendImpl                           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskSuspendImpl                          \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_vTaskSuspend_Unpriv                           \n"
+                " MPU_vTaskSuspend_Priv:                                \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_vTaskSuspendImpl                            \n"
+                " MPU_vTaskSuspend_Unpriv:                              \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskSuspendImpl                           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
+    #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_vTaskSuspend == 1 )
+    #if ( INCLUDE_vTaskSuspend == 1 )
 
-void MPU_vTaskResume( TaskHandle_t xTaskToResume ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskResume( TaskHandle_t xTaskToResume ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskResumeImpl                           \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_vTaskResume_Unpriv                            \n"
-        " MPU_vTaskResume_Priv:                                 \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_vTaskResumeImpl                             \n"
-        " MPU_vTaskResume_Unpriv:                               \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskResumeImpl                            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskResumeImpl                           \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_vTaskResume_Unpriv                            \n"
+                " MPU_vTaskResume_Priv:                                 \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_vTaskResumeImpl                             \n"
+                " MPU_vTaskResume_Unpriv:                               \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskResumeImpl                            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
+    #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
 /*-----------------------------------------------------------*/
 
-TickType_t MPU_xTaskGetTickCount( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    TickType_t MPU_xTaskGetTickCount( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TickType_t MPU_xTaskGetTickCount( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetTickCountImpl                     \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTaskGetTickCount_Unpriv                      \n"
-        " MPU_xTaskGetTickCount_Priv:                           \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTaskGetTickCountImpl                       \n"
-        " MPU_xTaskGetTickCount_Unpriv:                         \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetTickCountImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    TickType_t MPU_xTaskGetTickCount( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xTaskGetTickCountImpl                     \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xTaskGetTickCount_Unpriv                      \n"
+            " MPU_xTaskGetTickCount_Priv:                           \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xTaskGetTickCountImpl                       \n"
+            " MPU_xTaskGetTickCount_Unpriv:                         \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xTaskGetTickCountImpl                      \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetNumberOfTasksImpl                \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_uxTaskGetNumberOfTasks_Unpriv                 \n"
-        " MPU_uxTaskGetNumberOfTasks_Priv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_uxTaskGetNumberOfTasksImpl                  \n"
-        " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetNumberOfTasksImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_uxTaskGetNumberOfTasksImpl                \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_uxTaskGetNumberOfTasks_Unpriv                 \n"
+            " MPU_uxTaskGetNumberOfTasks_Priv:                      \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_uxTaskGetNumberOfTasksImpl                  \n"
+            " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_uxTaskGetNumberOfTasksImpl                 \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configGENERATE_RUN_TIME_STATS == 1 )
+    #if ( configGENERATE_RUN_TIME_STATS == 1 )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetRunTimeCounterImpl               \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_ulTaskGetRunTimeCounter_Unpriv                \n"
-        " MPU_ulTaskGetRunTimeCounter_Priv:                     \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_ulTaskGetRunTimeCounterImpl                 \n"
-        " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetRunTimeCounterImpl                \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetRunTimeCounterImpl               \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_ulTaskGetRunTimeCounter_Unpriv                \n"
+                " MPU_ulTaskGetRunTimeCounter_Priv:                     \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_ulTaskGetRunTimeCounterImpl                 \n"
+                " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetRunTimeCounterImpl                \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configGENERATE_RUN_TIME_STATS == 1 )
+    #if ( configGENERATE_RUN_TIME_STATS == 1 )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetRunTimePercentImpl               \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_ulTaskGetRunTimePercent_Unpriv                \n"
-        " MPU_ulTaskGetRunTimePercent_Priv:                     \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_ulTaskGetRunTimePercentImpl                 \n"
-        " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetRunTimePercentImpl                \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetRunTimePercentImpl               \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_ulTaskGetRunTimePercent_Unpriv                \n"
+                " MPU_ulTaskGetRunTimePercent_Priv:                     \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_ulTaskGetRunTimePercentImpl                 \n"
+                " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetRunTimePercentImpl                \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+    #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetIdleRunTimePercentImpl           \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv            \n"
-        " MPU_ulTaskGetIdleRunTimePercent_Priv:                 \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_ulTaskGetIdleRunTimePercentImpl             \n"
-        " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetIdleRunTimePercentImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetIdleRunTimePercentImpl           \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv            \n"
+                " MPU_ulTaskGetIdleRunTimePercent_Priv:                 \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_ulTaskGetIdleRunTimePercentImpl             \n"
+                " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetIdleRunTimePercentImpl            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+    #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetIdleRunTimeCounterImpl           \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv            \n"
-        " MPU_ulTaskGetIdleRunTimeCounter_Priv:                 \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_ulTaskGetIdleRunTimeCounterImpl             \n"
-        " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetIdleRunTimeCounterImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetIdleRunTimeCounterImpl           \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv            \n"
+                " MPU_ulTaskGetIdleRunTimeCounter_Priv:                 \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_ulTaskGetIdleRunTimeCounterImpl             \n"
+                " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetIdleRunTimeCounterImpl            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+    #if ( configUSE_APPLICATION_TASK_TAG == 1 )
 
-void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
-                                     TaskHookFunction_t pxHookFunction ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
+                                             TaskHookFunction_t pxHookFunction ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
-                                     TaskHookFunction_t pxHookFunction ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSetApplicationTaskTagImpl            \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_vTaskSetApplicationTaskTag_Unpriv             \n"
-        " MPU_vTaskSetApplicationTaskTag_Priv:                  \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_vTaskSetApplicationTaskTagImpl              \n"
-        " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSetApplicationTaskTagImpl             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
+                                             TaskHookFunction_t pxHookFunction ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskSetApplicationTaskTagImpl            \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_vTaskSetApplicationTaskTag_Unpriv             \n"
+                " MPU_vTaskSetApplicationTaskTag_Priv:                  \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_vTaskSetApplicationTaskTagImpl              \n"
+                " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskSetApplicationTaskTagImpl             \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
+    #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+    #if ( configUSE_APPLICATION_TASK_TAG == 1 )
 
-TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetApplicationTaskTagImpl            \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTaskGetApplicationTaskTag_Unpriv             \n"
-        " MPU_xTaskGetApplicationTaskTag_Priv:                  \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTaskGetApplicationTaskTagImpl              \n"
-        " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetApplicationTaskTagImpl             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetApplicationTaskTagImpl            \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xTaskGetApplicationTaskTag_Unpriv             \n"
+                " MPU_xTaskGetApplicationTaskTag_Priv:                  \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xTaskGetApplicationTaskTagImpl              \n"
+                " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetApplicationTaskTagImpl             \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
+    #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+    #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
 
-void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
-                                            BaseType_t xIndex,
-                                            void * pvValue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
+                                                    BaseType_t xIndex,
+                                                    void * pvValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
-                                            BaseType_t xIndex,
-                                            void * pvValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSetThreadLocalStoragePointerImpl     \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv      \n"
-        " MPU_vTaskSetThreadLocalStoragePointer_Priv:           \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_vTaskSetThreadLocalStoragePointerImpl       \n"
-        " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSetThreadLocalStoragePointerImpl      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
+                                                    BaseType_t xIndex,
+                                                    void * pvValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskSetThreadLocalStoragePointerImpl     \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv      \n"
+                " MPU_vTaskSetThreadLocalStoragePointer_Priv:           \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_vTaskSetThreadLocalStoragePointerImpl       \n"
+                " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskSetThreadLocalStoragePointerImpl      \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
+    #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+    #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
 
-void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
-                                               BaseType_t xIndex ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
+                                                       BaseType_t xIndex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
-                                               BaseType_t xIndex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pvTaskGetThreadLocalStoragePointerImpl    \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv     \n"
-        " MPU_pvTaskGetThreadLocalStoragePointer_Priv:          \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_pvTaskGetThreadLocalStoragePointerImpl      \n"
-        " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pvTaskGetThreadLocalStoragePointerImpl     \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
+                                                       BaseType_t xIndex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pvTaskGetThreadLocalStoragePointerImpl    \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv     \n"
+                " MPU_pvTaskGetThreadLocalStoragePointer_Priv:          \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_pvTaskGetThreadLocalStoragePointerImpl      \n"
+                " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pvTaskGetThreadLocalStoragePointerImpl     \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
+    #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
-                                      const UBaseType_t uxArraySize,
-                                      configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
+                                              const UBaseType_t uxArraySize,
+                                              configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
-                                      const UBaseType_t uxArraySize,
-                                      configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetSystemStateImpl                  \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_uxTaskGetSystemState_Unpriv                   \n"
-        " MPU_uxTaskGetSystemState_Priv:                        \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_uxTaskGetSystemStateImpl                    \n"
-        " MPU_uxTaskGetSystemState_Unpriv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetSystemStateImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
+                                              const UBaseType_t uxArraySize,
+                                              configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskGetSystemStateImpl                  \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_uxTaskGetSystemState_Unpriv                   \n"
+                " MPU_uxTaskGetSystemState_Priv:                        \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_uxTaskGetSystemStateImpl                    \n"
+                " MPU_uxTaskGetSystemState_Unpriv:                      \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskGetSystemStateImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
+    #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
+    #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
 
-UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetStackHighWaterMarkImpl           \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_uxTaskGetStackHighWaterMark_Unpriv            \n"
-        " MPU_uxTaskGetStackHighWaterMark_Priv:                 \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_uxTaskGetStackHighWaterMarkImpl             \n"
-        " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetStackHighWaterMarkImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskGetStackHighWaterMarkImpl           \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_uxTaskGetStackHighWaterMark_Unpriv            \n"
+                " MPU_uxTaskGetStackHighWaterMark_Priv:                 \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_uxTaskGetStackHighWaterMarkImpl             \n"
+                " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskGetStackHighWaterMarkImpl            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */
+    #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
+    #if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
 
-configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetStackHighWaterMark2Impl          \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv           \n"
-        " MPU_uxTaskGetStackHighWaterMark2_Priv:                \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_uxTaskGetStackHighWaterMark2Impl            \n"
-        " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetStackHighWaterMark2Impl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskGetStackHighWaterMark2Impl          \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv           \n"
+                " MPU_uxTaskGetStackHighWaterMark2_Priv:                \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_uxTaskGetStackHighWaterMark2Impl            \n"
+                " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskGetStackHighWaterMark2Impl           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */
+    #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
+    #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
 
-TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetCurrentTaskHandleImpl             \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTaskGetCurrentTaskHandle_Unpriv              \n"
-        " MPU_xTaskGetCurrentTaskHandle_Priv:                   \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTaskGetCurrentTaskHandleImpl               \n"
-        " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetCurrentTaskHandleImpl              \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetCurrentTaskHandleImpl             \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xTaskGetCurrentTaskHandle_Unpriv              \n"
+                " MPU_xTaskGetCurrentTaskHandle_Priv:                   \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xTaskGetCurrentTaskHandleImpl               \n"
+                " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetCurrentTaskHandleImpl              \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
+    #endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_xTaskGetSchedulerState == 1 )
+    #if ( INCLUDE_xTaskGetSchedulerState == 1 )
 
-BaseType_t MPU_xTaskGetSchedulerState( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGetSchedulerState( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGetSchedulerState( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetSchedulerStateImpl                \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTaskGetSchedulerState_Unpriv                 \n"
-        " MPU_xTaskGetSchedulerState_Priv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTaskGetSchedulerStateImpl                  \n"
-        " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetSchedulerStateImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGetSchedulerState( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetSchedulerStateImpl                \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xTaskGetSchedulerState_Unpriv                 \n"
+                " MPU_xTaskGetSchedulerState_Priv:                      \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xTaskGetSchedulerStateImpl                  \n"
+                " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetSchedulerStateImpl                 \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */
+    #endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */
 /*-----------------------------------------------------------*/
 
-void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSetTimeOutStateImpl                  \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_vTaskSetTimeOutState_Unpriv                   \n"
-        " MPU_vTaskSetTimeOutState_Priv:                        \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_vTaskSetTimeOutStateImpl                    \n"
-        " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSetTimeOutStateImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_vTaskSetTimeOutStateImpl                  \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_vTaskSetTimeOutState_Unpriv                   \n"
+            " MPU_vTaskSetTimeOutState_Priv:                        \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_vTaskSetTimeOutStateImpl                    \n"
+            " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_vTaskSetTimeOutStateImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
-                                     TickType_t * const pxTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
+                                         TickType_t * const pxTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
-                                     TickType_t * const pxTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskCheckForTimeOutImpl                  \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTaskCheckForTimeOut_Unpriv                   \n"
-        " MPU_xTaskCheckForTimeOut_Priv:                        \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTaskCheckForTimeOutImpl                    \n"
-        " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskCheckForTimeOutImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
+                                         TickType_t * const pxTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xTaskCheckForTimeOutImpl                  \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xTaskCheckForTimeOut_Unpriv                   \n"
+            " MPU_xTaskCheckForTimeOut_Priv:                        \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xTaskCheckForTimeOutImpl                    \n"
+            " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xTaskCheckForTimeOutImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                   UBaseType_t uxIndexToNotify,
-                                   uint32_t ulValue,
-                                   eNotifyAction eAction,
-                                   uint32_t * pulPreviousNotificationValue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
+                                           UBaseType_t uxIndexToNotify,
+                                           uint32_t ulValue,
+                                           eNotifyAction eAction,
+                                           uint32_t * pulPreviousNotificationValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                   UBaseType_t uxIndexToNotify,
-                                   uint32_t ulValue,
-                                   eNotifyAction eAction,
-                                   uint32_t * pulPreviousNotificationValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGenericNotifyImpl                    \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTaskGenericNotify_Unpriv                     \n"
-        " MPU_xTaskGenericNotify_Priv:                          \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTaskGenericNotifyImpl                      \n"
-        " MPU_xTaskGenericNotify_Unpriv:                        \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGenericNotifyImpl                     \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
+                                           UBaseType_t uxIndexToNotify,
+                                           uint32_t ulValue,
+                                           eNotifyAction eAction,
+                                           uint32_t * pulPreviousNotificationValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGenericNotifyImpl                    \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xTaskGenericNotify_Unpriv                     \n"
+                " MPU_xTaskGenericNotify_Priv:                          \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xTaskGenericNotifyImpl                      \n"
+                " MPU_xTaskGenericNotify_Unpriv:                        \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGenericNotifyImpl                     \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                       uint32_t ulBitsToClearOnEntry,
-                                       uint32_t ulBitsToClearOnExit,
-                                       uint32_t * pulNotificationValue,
-                                       TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
+                                               uint32_t ulBitsToClearOnEntry,
+                                               uint32_t ulBitsToClearOnExit,
+                                               uint32_t * pulNotificationValue,
+                                               TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                       uint32_t ulBitsToClearOnEntry,
-                                       uint32_t ulBitsToClearOnExit,
-                                       uint32_t * pulNotificationValue,
-                                       TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGenericNotifyWaitImpl                \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTaskGenericNotifyWait_Unpriv                 \n"
-        " MPU_xTaskGenericNotifyWait_Priv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTaskGenericNotifyWaitImpl                  \n"
-        " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGenericNotifyWaitImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
+                                               uint32_t ulBitsToClearOnEntry,
+                                               uint32_t ulBitsToClearOnExit,
+                                               uint32_t * pulNotificationValue,
+                                               TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGenericNotifyWaitImpl                \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xTaskGenericNotifyWait_Unpriv                 \n"
+                " MPU_xTaskGenericNotifyWait_Priv:                      \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xTaskGenericNotifyWaitImpl                  \n"
+                " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGenericNotifyWaitImpl                 \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
-                                      BaseType_t xClearCountOnExit,
-                                      TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
+                                              BaseType_t xClearCountOnExit,
+                                              TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
-                                      BaseType_t xClearCountOnExit,
-                                      TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGenericNotifyTakeImpl               \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_ulTaskGenericNotifyTake_Unpriv                \n"
-        " MPU_ulTaskGenericNotifyTake_Priv:                     \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_ulTaskGenericNotifyTakeImpl                 \n"
-        " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGenericNotifyTakeImpl                \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
+                                              BaseType_t xClearCountOnExit,
+                                              TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGenericNotifyTakeImpl               \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_ulTaskGenericNotifyTake_Unpriv                \n"
+                " MPU_ulTaskGenericNotifyTake_Priv:                     \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_ulTaskGenericNotifyTakeImpl                 \n"
+                " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGenericNotifyTakeImpl                \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
-                                             UBaseType_t uxIndexToClear ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
+                                                     UBaseType_t uxIndexToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
-                                             UBaseType_t uxIndexToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGenericNotifyStateClearImpl          \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTaskGenericNotifyStateClear_Unpriv           \n"
-        " MPU_xTaskGenericNotifyStateClear_Priv:                \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTaskGenericNotifyStateClearImpl            \n"
-        " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGenericNotifyStateClearImpl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
+                                                     UBaseType_t uxIndexToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGenericNotifyStateClearImpl          \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xTaskGenericNotifyStateClear_Unpriv           \n"
+                " MPU_xTaskGenericNotifyStateClear_Priv:                \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xTaskGenericNotifyStateClearImpl            \n"
+                " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGenericNotifyStateClearImpl           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
-                                            UBaseType_t uxIndexToClear,
-                                            uint32_t ulBitsToClear ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
+                                                    UBaseType_t uxIndexToClear,
+                                                    uint32_t ulBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
-                                            UBaseType_t uxIndexToClear,
-                                            uint32_t ulBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGenericNotifyValueClearImpl         \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_ulTaskGenericNotifyValueClear_Unpriv          \n"
-        " MPU_ulTaskGenericNotifyValueClear_Priv:               \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_ulTaskGenericNotifyValueClearImpl           \n"
-        " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGenericNotifyValueClearImpl          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
+                                                    UBaseType_t uxIndexToClear,
+                                                    uint32_t ulBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGenericNotifyValueClearImpl         \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_ulTaskGenericNotifyValueClear_Unpriv          \n"
+                " MPU_ulTaskGenericNotifyValueClear_Priv:               \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_ulTaskGenericNotifyValueClearImpl           \n"
+                " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGenericNotifyValueClearImpl          \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
-                                  const void * const pvItemToQueue,
-                                  TickType_t xTicksToWait,
-                                  const BaseType_t xCopyPosition ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
+                                      const void * const pvItemToQueue,
+                                      TickType_t xTicksToWait,
+                                      const BaseType_t xCopyPosition ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
-                                  const void * const pvItemToQueue,
-                                  TickType_t xTicksToWait,
-                                  const BaseType_t xCopyPosition ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueGenericSendImpl                     \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xQueueGenericSend_Unpriv                      \n"
-        " MPU_xQueueGenericSend_Priv:                           \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xQueueGenericSendImpl                       \n"
-        " MPU_xQueueGenericSend_Unpriv:                         \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueGenericSendImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
+                                      const void * const pvItemToQueue,
+                                      TickType_t xTicksToWait,
+                                      const BaseType_t xCopyPosition ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueueGenericSendImpl                     \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xQueueGenericSend_Unpriv                      \n"
+            " MPU_xQueueGenericSend_Priv:                           \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xQueueGenericSendImpl                       \n"
+            " MPU_xQueueGenericSend_Unpriv:                         \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueueGenericSendImpl                      \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxQueueMessagesWaitingImpl                \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_uxQueueMessagesWaiting_Unpriv                 \n"
-        " MPU_uxQueueMessagesWaiting_Priv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_uxQueueMessagesWaitingImpl                  \n"
-        " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxQueueMessagesWaitingImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_uxQueueMessagesWaitingImpl                \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_uxQueueMessagesWaiting_Unpriv                 \n"
+            " MPU_uxQueueMessagesWaiting_Priv:                      \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_uxQueueMessagesWaitingImpl                  \n"
+            " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_uxQueueMessagesWaitingImpl                 \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxQueueSpacesAvailableImpl                \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_uxQueueSpacesAvailable_Unpriv                 \n"
-        " MPU_uxQueueSpacesAvailable_Priv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_uxQueueSpacesAvailableImpl                  \n"
-        " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxQueueSpacesAvailableImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_uxQueueSpacesAvailableImpl                \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_uxQueueSpacesAvailable_Unpriv                 \n"
+            " MPU_uxQueueSpacesAvailable_Priv:                      \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_uxQueueSpacesAvailableImpl                  \n"
+            " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_uxQueueSpacesAvailableImpl                 \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
-                              void * const pvBuffer,
-                              TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
+                                  void * const pvBuffer,
+                                  TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
-                              void * const pvBuffer,
-                              TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueReceiveImpl                         \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xQueueReceive_Unpriv                          \n"
-        " MPU_xQueueReceive_Priv:                               \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xQueueReceiveImpl                           \n"
-        " MPU_xQueueReceive_Unpriv:                             \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueReceiveImpl                          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
+                                  void * const pvBuffer,
+                                  TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueueReceiveImpl                         \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xQueueReceive_Unpriv                          \n"
+            " MPU_xQueueReceive_Priv:                               \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xQueueReceiveImpl                           \n"
+            " MPU_xQueueReceive_Unpriv:                             \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueueReceiveImpl                          \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
-                           void * const pvBuffer,
-                           TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
+                               void * const pvBuffer,
+                               TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
-                           void * const pvBuffer,
-                           TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueuePeekImpl                            \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xQueuePeek_Unpriv                             \n"
-        " MPU_xQueuePeek_Priv:                                  \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xQueuePeekImpl                              \n"
-        " MPU_xQueuePeek_Unpriv:                                \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueuePeekImpl                             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
+                               void * const pvBuffer,
+                               TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueuePeekImpl                            \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xQueuePeek_Unpriv                             \n"
+            " MPU_xQueuePeek_Priv:                                  \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xQueuePeekImpl                              \n"
+            " MPU_xQueuePeek_Unpriv:                                \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueuePeekImpl                             \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
-                                    TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
+                                        TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
-                                    TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueSemaphoreTakeImpl                   \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xQueueSemaphoreTake_Unpriv                    \n"
-        " MPU_xQueueSemaphoreTake_Priv:                         \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xQueueSemaphoreTakeImpl                     \n"
-        " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueSemaphoreTakeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
+                                        TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueueSemaphoreTakeImpl                   \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xQueueSemaphoreTake_Unpriv                    \n"
+            " MPU_xQueueSemaphoreTake_Priv:                         \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xQueueSemaphoreTakeImpl                     \n"
+            " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueueSemaphoreTakeImpl                    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+    #if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
 
-TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueGetMutexHolderImpl                  \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xQueueGetMutexHolder_Unpriv                   \n"
-        " MPU_xQueueGetMutexHolder_Priv:                        \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xQueueGetMutexHolderImpl                    \n"
-        " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueGetMutexHolderImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueGetMutexHolderImpl                  \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xQueueGetMutexHolder_Unpriv                   \n"
+                " MPU_xQueueGetMutexHolder_Priv:                        \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xQueueGetMutexHolderImpl                    \n"
+                " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueGetMutexHolderImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */
+    #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+    #if ( configUSE_RECURSIVE_MUTEXES == 1 )
 
-BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
-                                         TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+                                                 TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+        BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+                                                 TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueTakeMutexRecursiveImpl              \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xQueueTakeMutexRecursive_Unpriv               \n"
+                " MPU_xQueueTakeMutexRecursive_Priv:                    \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xQueueTakeMutexRecursiveImpl                \n"
+                " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueTakeMutexRecursiveImpl               \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_RECURSIVE_MUTEXES == 1 )
+
+        BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueGiveMutexRecursiveImpl              \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xQueueGiveMutexRecursive_Unpriv               \n"
+                " MPU_xQueueGiveMutexRecursive_Priv:                    \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xQueueGiveMutexRecursiveImpl                \n"
+                " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueGiveMutexRecursiveImpl               \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_QUEUE_SETS == 1 )
+
+        QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
+                                                        const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
+                                                        const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueSelectFromSetImpl                   \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xQueueSelectFromSet_Unpriv                    \n"
+                " MPU_xQueueSelectFromSet_Priv:                         \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xQueueSelectFromSetImpl                     \n"
+                " MPU_xQueueSelectFromSet_Unpriv:                       \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueSelectFromSetImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_QUEUE_SETS == 1 )
+
+        BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                                       QueueSetHandle_t xQueueSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                                       QueueSetHandle_t xQueueSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueAddToSetImpl                        \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xQueueAddToSet_Unpriv                         \n"
+                " MPU_xQueueAddToSet_Priv:                              \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xQueueAddToSetImpl                          \n"
+                " MPU_xQueueAddToSet_Unpriv:                            \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueAddToSetImpl                         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+        void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
+                                      const char * pcName ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
+                                      const char * pcName ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vQueueAddToRegistryImpl                   \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_vQueueAddToRegistry_Unpriv                    \n"
+                " MPU_vQueueAddToRegistry_Priv:                         \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_vQueueAddToRegistryImpl                     \n"
+                " MPU_vQueueAddToRegistry_Unpriv:                       \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vQueueAddToRegistryImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+        void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vQueueUnregisterQueueImpl                 \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_vQueueUnregisterQueue_Unpriv                  \n"
+                " MPU_vQueueUnregisterQueue_Priv:                       \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_vQueueUnregisterQueueImpl                   \n"
+                " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vQueueUnregisterQueueImpl                  \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+        const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pcQueueGetNameImpl                        \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_pcQueueGetName_Unpriv                         \n"
+                " MPU_pcQueueGetName_Priv:                              \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_pcQueueGetNameImpl                          \n"
+                " MPU_pcQueueGetName_Unpriv:                            \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pcQueueGetNameImpl                         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pvTimerGetTimerIDImpl                     \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_pvTimerGetTimerID_Unpriv                      \n"
+                " MPU_pvTimerGetTimerID_Priv:                           \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_pvTimerGetTimerIDImpl                       \n"
+                " MPU_pvTimerGetTimerID_Unpriv:                         \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pvTimerGetTimerIDImpl                      \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
+                                   void * pvNewID ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
+                                   void * pvNewID ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTimerSetTimerIDImpl                      \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_vTimerSetTimerID_Unpriv                       \n"
+                " MPU_vTimerSetTimerID_Priv:                            \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_vTimerSetTimerIDImpl                        \n"
+                " MPU_vTimerSetTimerID_Unpriv:                          \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTimerSetTimerIDImpl                       \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerIsTimerActiveImpl                   \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xTimerIsTimerActive_Unpriv                    \n"
+                " MPU_xTimerIsTimerActive_Priv:                         \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xTimerIsTimerActiveImpl                     \n"
+                " MPU_xTimerIsTimerActive_Unpriv:                       \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerIsTimerActiveImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetTimerDaemonTaskHandleImpl        \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv         \n"
+                " MPU_xTimerGetTimerDaemonTaskHandle_Priv:              \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xTimerGetTimerDaemonTaskHandleImpl          \n"
+                " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetTimerDaemonTaskHandleImpl         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                                     const BaseType_t xCommandID,
+                                                     const TickType_t xOptionalValue,
+                                                     BaseType_t * const pxHigherPriorityTaskWoken,
+                                                     const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                                     const BaseType_t xCommandID,
+                                                     const TickType_t xOptionalValue,
+                                                     BaseType_t * const pxHigherPriorityTaskWoken,
+                                                     const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                               \n"
+                " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
+                "                                                               \n"
+                " push {r0, r1}                                                 \n"
+                " mrs r0, control                                               \n"
+                " movs r1, #1                                                   \n"
+                " tst r0, r1                                                    \n"
+                " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
+                " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
+                "     pop {r0, r1}                                              \n"
+                "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
+                " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
+                "     pop {r0, r1}                                              \n"
+                "     svc %0                                                    \n"
+                "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
+                "     svc %1                                                    \n"
+                "     bx lr                                                     \n"
+                "                                                               \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pcTimerGetNameImpl                        \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_pcTimerGetName_Unpriv                         \n"
+                " MPU_pcTimerGetName_Priv:                              \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_pcTimerGetNameImpl                          \n"
+                " MPU_pcTimerGetName_Unpriv:                            \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pcTimerGetNameImpl                         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
+                                      const BaseType_t uxAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
+                                      const BaseType_t uxAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTimerSetReloadModeImpl                   \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_vTimerSetReloadMode_Unpriv                    \n"
+                " MPU_vTimerSetReloadMode_Priv:                         \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_vTimerSetReloadModeImpl                     \n"
+                " MPU_vTimerSetReloadMode_Unpriv:                       \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTimerSetReloadModeImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetReloadModeImpl                   \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xTimerGetReloadMode_Unpriv                    \n"
+                " MPU_xTimerGetReloadMode_Priv:                         \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xTimerGetReloadModeImpl                     \n"
+                " MPU_xTimerGetReloadMode_Unpriv:                       \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetReloadModeImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTimerGetReloadModeImpl                  \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_uxTimerGetReloadMode_Unpriv                   \n"
+                " MPU_uxTimerGetReloadMode_Priv:                        \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_uxTimerGetReloadModeImpl                    \n"
+                " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTimerGetReloadModeImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetPeriodImpl                       \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xTimerGetPeriod_Unpriv                        \n"
+                " MPU_xTimerGetPeriod_Priv:                             \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xTimerGetPeriodImpl                         \n"
+                " MPU_xTimerGetPeriod_Unpriv:                           \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetPeriodImpl                        \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetExpiryTimeImpl                   \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xTimerGetExpiryTime_Unpriv                    \n"
+                " MPU_xTimerGetExpiryTime_Priv:                         \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xTimerGetExpiryTimeImpl                     \n"
+                " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetExpiryTimeImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         const BaseType_t xClearOnExit,
+                                         const BaseType_t xWaitForAllBits,
+                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         const BaseType_t xClearOnExit,
+                                         const BaseType_t xWaitForAllBits,
                                          TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueTakeMutexRecursiveImpl              \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xQueueTakeMutexRecursive_Unpriv               \n"
-        " MPU_xQueueTakeMutexRecursive_Priv:                    \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xQueueTakeMutexRecursiveImpl                \n"
-        " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueTakeMutexRecursiveImpl               \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupWaitBitsImpl                   \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
+            " MPU_xEventGroupWaitBits_Priv:                         \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xEventGroupWaitBitsImpl                     \n"
+            " MPU_xEventGroupWaitBits_Unpriv:                       \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupWaitBitsImpl                    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                          const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueGiveMutexRecursiveImpl              \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xQueueGiveMutexRecursive_Unpriv               \n"
-        " MPU_xQueueGiveMutexRecursive_Priv:                    \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xQueueGiveMutexRecursiveImpl                \n"
-        " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueGiveMutexRecursiveImpl               \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                          const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupClearBitsImpl                  \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xEventGroupClearBits_Unpriv                   \n"
+            " MPU_xEventGroupClearBits_Priv:                        \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xEventGroupClearBitsImpl                    \n"
+            " MPU_xEventGroupClearBits_Unpriv:                      \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupClearBitsImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_QUEUE_SETS == 1 )
+    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                        const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
-                                                const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
-                                                const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueSelectFromSetImpl                   \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xQueueSelectFromSet_Unpriv                    \n"
-        " MPU_xQueueSelectFromSet_Priv:                         \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xQueueSelectFromSetImpl                     \n"
-        " MPU_xQueueSelectFromSet_Unpriv:                       \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueSelectFromSetImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                        const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupSetBitsImpl                    \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xEventGroupSetBits_Unpriv                     \n"
+            " MPU_xEventGroupSetBits_Priv:                          \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xEventGroupSetBitsImpl                      \n"
+            " MPU_xEventGroupSetBits_Unpriv:                        \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupSetBitsImpl                     \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_QUEUE_SETS == 1 )
-
-BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
-                               QueueSetHandle_t xQueueSet ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
-                               QueueSetHandle_t xQueueSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueAddToSetImpl                        \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xQueueAddToSet_Unpriv                         \n"
-        " MPU_xQueueAddToSet_Priv:                              \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xQueueAddToSetImpl                          \n"
-        " MPU_xQueueAddToSet_Unpriv:                            \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueAddToSetImpl                         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_QUEUE_SETS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
-                              const char * pcName ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
-                              const char * pcName ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vQueueAddToRegistryImpl                   \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_vQueueAddToRegistry_Unpriv                    \n"
-        " MPU_vQueueAddToRegistry_Priv:                         \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_vQueueAddToRegistryImpl                     \n"
-        " MPU_vQueueAddToRegistry_Unpriv:                       \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vQueueAddToRegistryImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vQueueUnregisterQueueImpl                 \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_vQueueUnregisterQueue_Unpriv                  \n"
-        " MPU_vQueueUnregisterQueue_Priv:                       \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_vQueueUnregisterQueueImpl                   \n"
-        " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vQueueUnregisterQueueImpl                  \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pcQueueGetNameImpl                        \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_pcQueueGetName_Unpriv                         \n"
-        " MPU_pcQueueGetName_Priv:                              \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_pcQueueGetNameImpl                          \n"
-        " MPU_pcQueueGetName_Unpriv:                            \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pcQueueGetNameImpl                         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pvTimerGetTimerIDImpl                     \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_pvTimerGetTimerID_Unpriv                      \n"
-        " MPU_pvTimerGetTimerID_Priv:                           \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_pvTimerGetTimerIDImpl                       \n"
-        " MPU_pvTimerGetTimerID_Unpriv:                         \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pvTimerGetTimerIDImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
-                           void * pvNewID ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
-                           void * pvNewID ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTimerSetTimerIDImpl                      \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_vTimerSetTimerID_Unpriv                       \n"
-        " MPU_vTimerSetTimerID_Priv:                            \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_vTimerSetTimerIDImpl                        \n"
-        " MPU_vTimerSetTimerID_Unpriv:                          \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTimerSetTimerIDImpl                       \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerIsTimerActiveImpl                   \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTimerIsTimerActive_Unpriv                    \n"
-        " MPU_xTimerIsTimerActive_Priv:                         \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTimerIsTimerActiveImpl                     \n"
-        " MPU_xTimerIsTimerActive_Unpriv:                       \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerIsTimerActiveImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetTimerDaemonTaskHandleImpl        \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv         \n"
-        " MPU_xTimerGetTimerDaemonTaskHandle_Priv:              \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTimerGetTimerDaemonTaskHandleImpl          \n"
-        " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetTimerDaemonTaskHandleImpl         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                             const BaseType_t xCommandID,
-                                             const TickType_t xOptionalValue,
-                                             BaseType_t * const pxHigherPriorityTaskWoken,
-                                             const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                             const BaseType_t xCommandID,
-                                             const TickType_t xOptionalValue,
-                                             BaseType_t * const pxHigherPriorityTaskWoken,
-                                             const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                               \n"
-        " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
-        "                                                               \n"
-        " push {r0, r1}                                                 \n"
-        " mrs r0, control                                               \n"
-        " movs r1, #1                                                   \n"
-        " tst r0, r1                                                    \n"
-        " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
-        " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
-        "     pop {r0, r1}                                              \n"
-        "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
-        " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
-        "     pop {r0, r1}                                              \n"
-        "     svc %0                                                    \n"
-        "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
-        "     svc %1                                                    \n"
-        "     bx lr                                                     \n"
-        "                                                               \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pcTimerGetNameImpl                        \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_pcTimerGetName_Unpriv                         \n"
-        " MPU_pcTimerGetName_Priv:                              \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_pcTimerGetNameImpl                          \n"
-        " MPU_pcTimerGetName_Unpriv:                            \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pcTimerGetNameImpl                         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                              const BaseType_t uxAutoReload ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                              const BaseType_t uxAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTimerSetReloadModeImpl                   \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_vTimerSetReloadMode_Unpriv                    \n"
-        " MPU_vTimerSetReloadMode_Priv:                         \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_vTimerSetReloadModeImpl                     \n"
-        " MPU_vTimerSetReloadMode_Unpriv:                       \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTimerSetReloadModeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetReloadModeImpl                   \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTimerGetReloadMode_Unpriv                    \n"
-        " MPU_xTimerGetReloadMode_Priv:                         \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTimerGetReloadModeImpl                     \n"
-        " MPU_xTimerGetReloadMode_Unpriv:                       \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetReloadModeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTimerGetReloadModeImpl                  \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_uxTimerGetReloadMode_Unpriv                   \n"
-        " MPU_uxTimerGetReloadMode_Priv:                        \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_uxTimerGetReloadModeImpl                    \n"
-        " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTimerGetReloadModeImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetPeriodImpl                       \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTimerGetPeriod_Unpriv                        \n"
-        " MPU_xTimerGetPeriod_Priv:                             \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTimerGetPeriodImpl                         \n"
-        " MPU_xTimerGetPeriod_Unpriv:                           \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetPeriodImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetExpiryTimeImpl                   \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTimerGetExpiryTime_Unpriv                    \n"
-        " MPU_xTimerGetExpiryTime_Priv:                         \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTimerGetExpiryTimeImpl                     \n"
-        " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetExpiryTimeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                     const EventBits_t uxBitsToSet,
                                      const EventBits_t uxBitsToWaitFor,
-                                     const BaseType_t xClearOnExit,
-                                     const BaseType_t xWaitForAllBits,
-                                     TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                     const EventBits_t uxBitsToSet,
                                      const EventBits_t uxBitsToWaitFor,
-                                     const BaseType_t xClearOnExit,
-                                     const BaseType_t xWaitForAllBits,
                                      TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupWaitBitsImpl                   \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
-        " MPU_xEventGroupWaitBits_Priv:                         \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xEventGroupWaitBitsImpl                     \n"
-        " MPU_xEventGroupWaitBits_Unpriv:                       \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupWaitBitsImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupSyncImpl                       \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xEventGroupSync_Unpriv                        \n"
+            " MPU_xEventGroupSync_Priv:                             \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xEventGroupSyncImpl                         \n"
+            " MPU_xEventGroupSync_Unpriv:                           \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupSyncImpl                        \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                      const EventBits_t uxBitsToClear ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                      const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupClearBitsImpl                  \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xEventGroupClearBits_Unpriv                   \n"
-        " MPU_xEventGroupClearBits_Priv:                        \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xEventGroupClearBitsImpl                    \n"
-        " MPU_xEventGroupClearBits_Unpriv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupClearBitsImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxEventGroupGetNumberImpl                 \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_uxEventGroupGetNumber_Unpriv                  \n"
+                " MPU_uxEventGroupGetNumber_Priv:                       \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_uxEventGroupGetNumberImpl                   \n"
+                " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxEventGroupGetNumberImpl                  \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
 /*-----------------------------------------------------------*/
 
-EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                    const EventBits_t uxBitsToSet ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                    const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupSetBitsImpl                    \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xEventGroupSetBits_Unpriv                     \n"
-        " MPU_xEventGroupSetBits_Priv:                          \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xEventGroupSetBitsImpl                      \n"
-        " MPU_xEventGroupSetBits_Unpriv:                        \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupSetBitsImpl                     \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vEventGroupSetNumber( void * xEventGroup,
+                                       UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vEventGroupSetNumber( void * xEventGroup,
+                                       UBaseType_t uxEventGroupNumber ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vEventGroupSetNumberImpl                  \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_vEventGroupSetNumber_Unpriv                   \n"
+                " MPU_vEventGroupSetNumber_Priv:                        \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_vEventGroupSetNumberImpl                    \n"
+                " MPU_vEventGroupSetNumber_Unpriv:                      \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vEventGroupSetNumberImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
 /*-----------------------------------------------------------*/
 
-EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                 const EventBits_t uxBitsToSet,
-                                 const EventBits_t uxBitsToWaitFor,
-                                 TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                  const void * pvTxData,
+                                  size_t xDataLengthBytes,
+                                  TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                 const EventBits_t uxBitsToSet,
-                                 const EventBits_t uxBitsToWaitFor,
-                                 TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupSyncImpl                       \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xEventGroupSync_Unpriv                        \n"
-        " MPU_xEventGroupSync_Priv:                             \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xEventGroupSyncImpl                         \n"
-        " MPU_xEventGroupSync_Unpriv:                           \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupSyncImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                  const void * pvTxData,
+                                  size_t xDataLengthBytes,
+                                  TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferSendImpl                     \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xStreamBufferSend_Unpriv                      \n"
+            " MPU_xStreamBufferSend_Priv:                           \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xStreamBufferSendImpl                       \n"
+            " MPU_xStreamBufferSend_Unpriv:                         \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferSendImpl                      \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                     void * pvRxData,
+                                     size_t xBufferLengthBytes,
+                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxEventGroupGetNumberImpl                 \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_uxEventGroupGetNumber_Unpriv                  \n"
-        " MPU_uxEventGroupGetNumber_Priv:                       \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_uxEventGroupGetNumberImpl                   \n"
-        " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxEventGroupGetNumberImpl                  \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                     void * pvRxData,
+                                     size_t xBufferLengthBytes,
+                                     TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferReceiveImpl                  \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xStreamBufferReceive_Unpriv                   \n"
+            " MPU_xStreamBufferReceive_Priv:                        \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xStreamBufferReceiveImpl                    \n"
+            " MPU_xStreamBufferReceive_Unpriv:                      \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferReceiveImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vEventGroupSetNumber( void * xEventGroup,
-                               UBaseType_t uxEventGroupNumber ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vEventGroupSetNumber( void * xEventGroup,
-                               UBaseType_t uxEventGroupNumber ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vEventGroupSetNumberImpl                  \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_vEventGroupSetNumber_Unpriv                   \n"
-        " MPU_vEventGroupSetNumber_Priv:                        \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_vEventGroupSetNumberImpl                    \n"
-        " MPU_vEventGroupSetNumber_Unpriv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vEventGroupSetNumberImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferIsFullImpl                   \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
+            " MPU_xStreamBufferIsFull_Priv:                         \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xStreamBufferIsFullImpl                     \n"
+            " MPU_xStreamBufferIsFull_Unpriv:                       \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferIsFullImpl                    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                              const void * pvTxData,
-                              size_t xDataLengthBytes,
-                              TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                              const void * pvTxData,
-                              size_t xDataLengthBytes,
-                              TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferSendImpl                     \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xStreamBufferSend_Unpriv                      \n"
-        " MPU_xStreamBufferSend_Priv:                           \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xStreamBufferSendImpl                       \n"
-        " MPU_xStreamBufferSend_Unpriv:                         \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferSendImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
+            " MPU_xStreamBufferIsEmpty_Priv:                        \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xStreamBufferIsEmptyImpl                    \n"
+            " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferIsEmptyImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                 void * pvRxData,
-                                 size_t xBufferLengthBytes,
-                                 TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                 void * pvRxData,
-                                 size_t xBufferLengthBytes,
-                                 TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferReceiveImpl                  \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xStreamBufferReceive_Unpriv                   \n"
-        " MPU_xStreamBufferReceive_Priv:                        \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xStreamBufferReceiveImpl                    \n"
-        " MPU_xStreamBufferReceive_Unpriv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferReceiveImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
+            " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
+            " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferSpacesAvailableImpl           \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferIsFullImpl                   \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
-        " MPU_xStreamBufferIsFull_Priv:                         \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xStreamBufferIsFullImpl                     \n"
-        " MPU_xStreamBufferIsFull_Unpriv:                       \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferIsFullImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
+            " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xStreamBufferBytesAvailableImpl             \n"
+            " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferBytesAvailableImpl            \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                 size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
-        " MPU_xStreamBufferIsEmpty_Priv:                        \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xStreamBufferIsEmptyImpl                    \n"
-        " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferIsEmptyImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                 size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
+            " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
+            " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferSetTriggerLevelImpl           \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
-        " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
-        " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferSpacesAvailableImpl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
-size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
-        " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xStreamBufferBytesAvailableImpl             \n"
-        " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferBytesAvailableImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                             size_t xTriggerLevel ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                             size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
-        " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
-        " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferSetTriggerLevelImpl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
-size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
-        " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
-        " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferNextMessageLengthBytesImpl    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
+            " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
+            " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferNextMessageLengthBytesImpl    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
diff --git a/portable/GCC/ARM_CM23/non_secure/port.c b/portable/GCC/ARM_CM23/non_secure/port.c
index 80410e82e..c940c304b 100644
--- a/portable/GCC/ARM_CM23/non_secure/port.c
+++ b/portable/GCC/ARM_CM23/non_secure/port.c
@@ -110,8 +110,8 @@
 /**
  * @brief Constants used during system call enter and exit.
  */
-#define portPSR_STACK_PADDING_MASK                ( 1UL << 9UL )
-#define portEXC_RETURN_STACK_FRAME_TYPE_MASK      ( 1UL << 4UL )
+#define portPSR_STACK_PADDING_MASK              ( 1UL << 9UL )
+#define portEXC_RETURN_STACK_FRAME_TYPE_MASK    ( 1UL << 4UL )
 /*-----------------------------------------------------------*/
 
 /**
@@ -133,81 +133,81 @@
 /**
  * @brief Offsets in the stack to the parameters when inside the SVC handler.
  */
-#define portOFFSET_TO_LR                    ( 5 )
-#define portOFFSET_TO_PC                    ( 6 )
-#define portOFFSET_TO_PSR                   ( 7 )
+#define portOFFSET_TO_LR     ( 5 )
+#define portOFFSET_TO_PC     ( 6 )
+#define portOFFSET_TO_PSR    ( 7 )
 /*-----------------------------------------------------------*/
 
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                      ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                      ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                       ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                      ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                      ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                     ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                     ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK  ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK               ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK               ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK               ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK               ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK               ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK               ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK               ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK               ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0              ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1              ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2              ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3              ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4              ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5              ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6              ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7              ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE            ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT      ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                      ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE             ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -216,11 +216,11 @@
 
 /* Extract last address of the MPU region as encoded in the
  * RLAR (Region Limit Address Register) value. */
-#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar )  \
+#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar ) \
     ( ( ( rlar ) & portMPU_RLAR_ADDRESS_MASK ) | ~portMPU_RLAR_ADDRESS_MASK )
 
 /* Does addr lies within [start, end] address range? */
-#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end )    \
+#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \
     ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) )
 
 /* Is the access request satisfied by the available permissions? */
@@ -422,54 +422,57 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the system call stack so that upon returning from
-     * SVC, the system call stack is used.
-     *
-     * It is used for the system calls with up to 4 parameters.
-     *
-     * @param pulTaskStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the system call stack so that upon returning from
+ * SVC, the system call stack is used.
+ *
+ * It is used for the system calls with up to 4 parameters.
+ *
+ * @param pulTaskStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallEnter( uint32_t * pulTaskStack,
+                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the system call stack so that upon returning from
-     * SVC, the system call stack is used.
-     *
-     * It is used for the system calls with 5 parameters.
-     *
-     * @param pulTaskStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the system call stack so that upon returning from
+ * SVC, the system call stack is used.
+ *
+ * It is used for the system calls with 5 parameters.
+ *
+ * @param pulTaskStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallEnter_1( uint32_t * pulTaskStack,
+                             uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the task stack so that upon returning from
-     * SVC, the task stack is used again.
-     *
-     * @param pulSystemCallStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the task stack so that upon returning from
+ * SVC, the task stack is used again.
+ *
+ * @param pulSystemCallStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallExit( uint32_t * pulSystemCallStack,
+                          uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Checks whether or not the calling task is privileged.
-     *
-     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
-     */
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
     BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
 
 #endif /* configENABLE_MPU == 1 */
@@ -1086,18 +1089,18 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             vRestoreContextOfFirstTask();
             break;
 
-        #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
-            case portSVC_RAISE_PRIVILEGE:
+            #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+                case portSVC_RAISE_PRIVILEGE:
 
-                /* Only raise the privilege, if the svc was raised from any of
-                 * the system calls. */
-                if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
-                    ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
-                {
-                    vRaisePrivilege();
-                }
-                break;
-        #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+                    /* Only raise the privilege, if the svc was raised from any of
+                     * the system calls. */
+                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+                    {
+                        vRaisePrivilege();
+                    }
+                    break;
+            #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
         default:
             /* Incorrect SVC call. */
@@ -1108,513 +1111,526 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulSystemCallStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallEnter( uint32_t * pulTaskStack,
+                           uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulSystemCallStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        /* This is not NULL only for the duration of the system call. */
-        configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+        #if defined( __ARMCC_VERSION )
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+
+            /* This is not NULL only for the duration of the system call. */
+            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the system call stack for the stack frame. */
+            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulSystemCallStack[ i ] = pulTaskStack[ i ];
+            }
+
+            /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
+             * restore it when we exit from the system call. */
+            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* Use the pulSystemCallStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+
+            /* Remember the location where we should copy the stack frame when we exit from
+             * the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+
+            /* Record if the hardware used padding to force the stack pointer
+             * to be double word aligned. */
+            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
+            {
+                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
             }
+
+            /* We ensure in pxPortInitialiseStack that the system call stack is
+             * double word aligned and therefore, there is no need of padding.
+             * Clear the bit[9] of stacked xPSR. */
+            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
+
+            /* Raise the privilege for the duration of the system call. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " bics r0, r1         \n" /* Clear nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the system call stack for the stack frame. */
-        pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulSystemCallStack[ i ] = pulTaskStack[ i ];
-        }
-
-        /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
-         * restore it when we exit from the system call. */
-        pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-        __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* Use the pulSystemCallStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-
-        /* Remember the location where we should copy the stack frame when we exit from
-         * the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-        /* Record if the hardware used padding to force the stack pointer
-         * to be double word aligned. */
-        if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-        {
-            pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-        }
-        else
-        {
-            pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-        }
-
-        /* We ensure in pxPortInitialiseStack that the system call stack is
-         * double word aligned and therefore, there is no need of padding.
-         * Clear the bit[9] of stacked xPSR. */
-        pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-        /* Raise the privilege for the duration of the system call. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " bics r0, r1         \n" /* Clear nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulSystemCallStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallEnter_1( uint32_t * pulTaskStack,
+                             uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulSystemCallStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        /* This is not NULL only for the duration of the system call. */
-        configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+        #if defined( __ARMCC_VERSION )
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+
+            /* This is not NULL only for the duration of the system call. */
+            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the system call stack for the stack frame and
+             * the parameter passed on the stack. We only need to copy one
+             * parameter but we still reserve 2 spaces to keep the stack
+             * double word aligned. */
+            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulSystemCallStack[ i ] = pulTaskStack[ i ];
+            }
+
+            /* Copy the parameter which is passed the stack. */
+            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
+            {
+                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
+
+                /* Record if the hardware used padding to force the stack pointer
+                 * to be double word aligned. */
+                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
+
+                /* Record if the hardware used padding to force the stack pointer
+                 * to be double word aligned. */
+                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
             }
+
+            /* Store the value of the LR and PSPLIM registers before the SVC was raised.
+             * We need to restore it when we exit from the system call. */
+            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* Use the pulSystemCallStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+
+            /* Remember the location where we should copy the stack frame when we exit from
+             * the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+
+            /* We ensure in pxPortInitialiseStack that the system call stack is
+             * double word aligned and therefore, there is no need of padding.
+             * Clear the bit[9] of stacked xPSR. */
+            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
+
+            /* Raise the privilege for the duration of the system call. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " bics r0, r1         \n" /* Clear nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the system call stack for the stack frame and
-         * the parameter passed on the stack. We only need to copy one
-         * parameter but we still reserve 2 spaces to keep the stack
-         * double word aligned. */
-        pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulSystemCallStack[ i ] = pulTaskStack[ i ];
-        }
-
-        /* Copy the parameter which is passed the stack. */
-        if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-        {
-            pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
-            /* Record if the hardware used padding to force the stack pointer
-             * to be double word aligned. */
-            pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-        }
-        else
-        {
-            pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
-            /* Record if the hardware used padding to force the stack pointer
-             * to be double word aligned. */
-            pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-        }
-
-        /* Store the value of the LR and PSPLIM registers before the SVC was raised.
-         * We need to restore it when we exit from the system call. */
-        pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-        __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* Use the pulSystemCallStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-
-        /* Remember the location where we should copy the stack frame when we exit from
-         * the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-        /* We ensure in pxPortInitialiseStack that the system call stack is
-         * double word aligned and therefore, there is no need of padding.
-         * Clear the bit[9] of stacked xPSR. */
-        pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-        /* Raise the privilege for the duration of the system call. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " bics r0, r1         \n" /* Clear nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulTaskStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallExit( uint32_t * pulSystemCallStack,
+                          uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulTaskStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+        #if defined( __ARMCC_VERSION )
+
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the task stack for the stack frame. */
+            pulTaskStack = pulTaskStack - ulStackFrameSize;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulTaskStack[ i ] = pulSystemCallStack[ i ];
+            }
+
+            /* Use the pulTaskStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
+
+            /* Restore the LR and PSPLIM to what they were at the time of
+             * system call entry. */
+            pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* If the hardware used padding to force the stack pointer
+             * to be double word aligned, set the stacked xPSR bit[9],
+             * otherwise clear it. */
+            if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG )
+            {
+                pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
             }
+
+            /* This is not NULL only for the duration of the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
+
+            /* Drop the privilege before returning to the thread mode. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " orrs r0, r1         \n" /* Set nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the task stack for the stack frame. */
-        pulTaskStack = pulTaskStack - ulStackFrameSize;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulTaskStack[ i ] = pulSystemCallStack[ i ];
-        }
-
-        /* Use the pulTaskStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
-
-        /* Restore the LR and PSPLIM to what they were at the time of
-         * system call entry. */
-        pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* If the hardware used padding to force the stack pointer
-         * to be double word aligned, set the stacked xPSR bit[9],
-         * otherwise clear it. */
-        if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG )
-        {
-            pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK;
-        }
-        else
-        {
-            pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-        }
-
-        /* This is not NULL only for the duration of the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
-
-        /* Drop the privilege before returning to the thread mode. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " orrs r0, r1         \n" /* Set nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */
-{
-    BaseType_t xTaskIsPrivileged = pdFALSE;
-    const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
-
-    if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+    BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */
     {
-        xTaskIsPrivileged = pdTRUE;
-    }
+        BaseType_t xTaskIsPrivileged = pdFALSE;
+        const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
 
-    return xTaskIsPrivileged;
-}
+        if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+        {
+            xTaskIsPrivileged = pdTRUE;
+        }
+
+        return xTaskIsPrivileged;
+    }
 
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
-#if( configENABLE_MPU == 1 )
+#if ( configENABLE_MPU == 1 )
 
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     StackType_t * pxEndOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters,
-                                     BaseType_t xRunPrivileged,
-                                     xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
-{
-    uint32_t ulIndex = 0;
-
-    xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
-    ulIndex++;
-
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
-    ulIndex++;
-
-    #if ( configENABLE_TRUSTZONE == 1 )
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters,
+                                         BaseType_t xRunPrivileged,
+                                         xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
     {
-        xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT;  /* xSecureContext. */
+        uint32_t ulIndex = 0;
+
+        xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
         ulIndex++;
-    }
-    #endif /* configENABLE_TRUSTZONE */
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
-    ulIndex++;
-    if( xRunPrivileged == pdTRUE )
-    {
-        xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */
         ulIndex++;
-    }
-    else
-    {
-        xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */
         ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
+        ulIndex++;
+
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters;            /* r0. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x01010101;                           /* r1. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x02020202;                           /* r2. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x03030303;                           /* r3. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x12121212;                           /* r12. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode;                  /* PC. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR;                     /* xPSR. */
+        ulIndex++;
+
+        #if ( configENABLE_TRUSTZONE == 1 )
+        {
+            xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT; /* xSecureContext. */
+            ulIndex++;
+        }
+        #endif /* configENABLE_TRUSTZONE */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
+        ulIndex++;
+
+        if( xRunPrivileged == pdTRUE )
+        {
+            xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
+            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+            ulIndex++;
+        }
+        else
+        {
+            xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
+            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+            ulIndex++;
+        }
+
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
+        ulIndex++;
+
+        #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+        {
+            /* Ensure that the system call stack is double word aligned. */
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] );
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) &
+                                                                                     ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
+
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] );
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) +
+                                                                                            ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) &
+                                                                                          ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
+
+            /* This is not NULL only for the duration of a system call. */
+            xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL;
+        }
+        #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
+
+        return &( xMPUSettings->ulContext[ ulIndex ] );
     }
-    xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
-    ulIndex++;
-
-    #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
-    {
-        /* Ensure that the system call stack is double word aligned. */
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] );
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) &
-                                                                                 ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
-
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] );
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) +
-                                                                                        ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) &
-                                                                                      ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
-
-        /* This is not NULL only for the duration of a system call. */
-        xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL;
-    }
-    #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
-
-    return &( xMPUSettings->ulContext[ ulIndex ] );
-}
 
 #else /* configENABLE_MPU */
 
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     StackType_t * pxEndOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters ) /* PRIVILEGED_FUNCTION */
-{
-    /* Simulate the stack frame as it would be created by a context switch
-     * interrupt. */
-    #if ( portPRELOAD_REGISTERS == 0 )
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters ) /* PRIVILEGED_FUNCTION */
     {
-        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-        pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
-        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-        pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
-        *pxTopOfStack = portINITIAL_EXC_RETURN;
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
-
-        #if ( configENABLE_TRUSTZONE == 1 )
+        /* Simulate the stack frame as it would be created by a context switch
+         * interrupt. */
+        #if ( portPRELOAD_REGISTERS == 0 )
         {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
-        }
-        #endif /* configENABLE_TRUSTZONE */
-    }
-    #else /* portPRELOAD_REGISTERS */
-    {
-        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
-        pxTopOfStack--;
-        *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
+            pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
+            *pxTopOfStack = portINITIAL_EXC_RETURN;
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+            #if ( configENABLE_TRUSTZONE == 1 )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+            }
+            #endif /* configENABLE_TRUSTZONE */
+        }
+        #else /* portPRELOAD_REGISTERS */
         {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
-        }
-        #endif /* configENABLE_TRUSTZONE */
-    }
-    #endif /* portPRELOAD_REGISTERS */
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
+            pxTopOfStack--;
+            *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack;            /* Slot used to hold this task's PSPLIM value. */
 
-    return pxTopOfStack;
-}
+            #if ( configENABLE_TRUSTZONE == 1 )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+            }
+            #endif /* configENABLE_TRUSTZONE */
+        }
+        #endif /* portPRELOAD_REGISTERS */
+
+        return pxTopOfStack;
+    }
 
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM23/non_secure/portasm.c b/portable/GCC/ARM_CM23/non_secure/portasm.c
index 64a24f527..d452c33b0 100644
--- a/portable/GCC/ARM_CM23/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM23/non_secure/portasm.c
@@ -46,133 +46,133 @@
 
 #if ( configENABLE_MPU == 1 )
 
-void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        " .syntax unified                                 \n"
-        "                                                 \n"
-        " program_mpu_first_task:                         \n"
-        "    ldr r3, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB.*/
-        "                                                 \n"
-        "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-        "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
-        "    movs r3, #1                                  \n" /* r3 = 1. */
-        "    bics r2, r3                                  \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
-        "    str r2, [r1]                                 \n" /* Disable MPU. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
-        "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-        "    ldr r2, xMAIR0Const2                         \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-        "    str r1, [r2]                                 \n" /* Program MAIR0. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-        "    ldr r1, xRNRConst2                           \n" /* r1 = 0xe000ed98 [Location of RNR]. */
-        "                                                 \n"
-        "    movs r3, #4                                  \n" /* r3 = 4. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 4. */
-        "    ldmia r0!, {r4-r5}                           \n" /* Read first set of RBAR/RLAR registers from TCB. */
-        "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "    stmia r2!, {r4-r5}                           \n" /* Write first set of RBAR/RLAR registers. */
-        "    movs r3, #5                                  \n" /* r3 = 5. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 5. */
-        "    ldmia r0!, {r4-r5}                           \n" /* Read second set of RBAR/RLAR registers from TCB. */
-        "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "    stmia r2!, {r4-r5}                           \n" /* Write second set of RBAR/RLAR registers. */
-        "    movs r3, #6                                  \n" /* r3 = 6. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 6. */
-        "    ldmia r0!, {r4-r5}                           \n" /* Read third set of RBAR/RLAR registers from TCB. */
-        "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "    stmia r2!, {r4-r5}                           \n" /* Write third set of RBAR/RLAR registers. */
-        "    movs r3, #7                                  \n" /* r3 = 6. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 7. */
-        "    ldmia r0!, {r4-r5}                           \n" /* Read fourth set of RBAR/RLAR registers from TCB. */
-        "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "    stmia r2!, {r4-r5}                           \n" /* Write fourth set of RBAR/RLAR registers. */
-        "                                                 \n"
-        "   ldr r1, xMPUCTRLConst2                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
-        "   movs r3, #1                                   \n" /* r3 = 1. */
-        "   orrs r2, r3                                   \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
-        "   str r2, [r1]                                  \n" /* Enable MPU. */
-        "   dsb                                           \n" /* Force memory writes before continuing. */
-        "                                                 \n"
-        " restore_context_first_task:                     \n"
-        "    ldr r3, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r1, [r3]                                 \n" /* r1 = pxCurrentTCB.*/
-        "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
-        "                                                 \n"
-        " restore_special_regs_first_task:                \n"
-        "    subs r2, #20                                 \n"
-        "    ldmia r2!, {r0, r3-r6}                       \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, r6 = LR. */
-        "    subs r2, #20                                 \n"
-        "    msr psp, r3                                  \n"
-        "    msr psplim, r4                               \n"
-        "    msr control, r5                              \n"
-        "    mov lr, r6                                   \n"
-        "    ldr r4, xSecureContextConst2                 \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-        "    str r0, [r4]                                 \n" /* Restore xSecureContext. */
-        "                                                 \n"
-        " restore_general_regs_first_task:                \n"
-        "    subs r2, #32                                 \n"
-        "    ldmia r2!, {r4-r7}                           \n" /* r4-r7 contain half of the hardware saved context. */
-        "    stmia r3!, {r4-r7}                           \n" /* Copy half of the the hardware saved context on the task stack. */
-        "    ldmia r2!, {r4-r7}                           \n" /* r4-r7 contain rest half of the hardware saved context. */
-        "    stmia r3!, {r4-r7}                           \n" /* Copy rest half of the the hardware saved context on the task stack. */
-        "    subs r2, #48                                 \n"
-        "    ldmia r2!, {r4-r7}                           \n" /* Restore r8-r11. */
-        "    mov r8, r4                                   \n" /* r8 = r4. */
-        "    mov r9, r5                                   \n" /* r9 = r5. */
-        "    mov r10, r6                                  \n" /* r10 = r6. */
-        "    mov r11, r7                                  \n" /* r11 = r7. */
-        "    subs r2, #32                                 \n"
-        "    ldmia r2!, {r4-r7}                           \n" /* Restore r4-r7. */
-        "    subs r2, #16                                 \n"
-        "                                                 \n"
-        " restore_context_done_first_task:                \n"
-        "    str r2, [r1]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
-        "    bx lr                                        \n"
-        "                                                 \n"
-        " .align 4                                        \n"
-        " pxCurrentTCBConst2: .word pxCurrentTCB          \n"
-        " xSecureContextConst2: .word xSecureContext      \n"
-        " xMPUCTRLConst2: .word 0xe000ed94                \n"
-        " xMAIR0Const2: .word 0xe000edc0                  \n"
-        " xRNRConst2: .word 0xe000ed98                    \n"
-        " xRBARConst2: .word 0xe000ed9c                   \n"
-    );
-}
+    void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                 \n"
+            "                                                 \n"
+            " program_mpu_first_task:                         \n"
+            "    ldr r3, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB.*/
+            "                                                 \n"
+            "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
+            "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
+            "    movs r3, #1                                  \n" /* r3 = 1. */
+            "    bics r2, r3                                  \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
+            "    str r2, [r1]                                 \n" /* Disable MPU. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
+            "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
+            "    ldr r2, xMAIR0Const2                         \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    str r1, [r2]                                 \n" /* Program MAIR0. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
+            "    ldr r1, xRNRConst2                           \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "                                                 \n"
+            "    movs r3, #4                                  \n" /* r3 = 4. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 4. */
+            "    ldmia r0!, {r4-r5}                           \n" /* Read first set of RBAR/RLAR registers from TCB. */
+            "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    stmia r2!, {r4-r5}                           \n" /* Write first set of RBAR/RLAR registers. */
+            "    movs r3, #5                                  \n" /* r3 = 5. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 5. */
+            "    ldmia r0!, {r4-r5}                           \n" /* Read second set of RBAR/RLAR registers from TCB. */
+            "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    stmia r2!, {r4-r5}                           \n" /* Write second set of RBAR/RLAR registers. */
+            "    movs r3, #6                                  \n" /* r3 = 6. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 6. */
+            "    ldmia r0!, {r4-r5}                           \n" /* Read third set of RBAR/RLAR registers from TCB. */
+            "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    stmia r2!, {r4-r5}                           \n" /* Write third set of RBAR/RLAR registers. */
+            "    movs r3, #7                                  \n" /* r3 = 6. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 7. */
+            "    ldmia r0!, {r4-r5}                           \n" /* Read fourth set of RBAR/RLAR registers from TCB. */
+            "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    stmia r2!, {r4-r5}                           \n" /* Write fourth set of RBAR/RLAR registers. */
+            "                                                 \n"
+            "   ldr r1, xMPUCTRLConst2                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
+            "   movs r3, #1                                   \n" /* r3 = 1. */
+            "   orrs r2, r3                                   \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
+            "   str r2, [r1]                                  \n" /* Enable MPU. */
+            "   dsb                                           \n" /* Force memory writes before continuing. */
+            "                                                 \n"
+            " restore_context_first_task:                     \n"
+            "    ldr r3, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r1, [r3]                                 \n" /* r1 = pxCurrentTCB.*/
+            "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
+            "                                                 \n"
+            " restore_special_regs_first_task:                \n"
+            "    subs r2, #20                                 \n"
+            "    ldmia r2!, {r0, r3-r6}                       \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, r6 = LR. */
+            "    subs r2, #20                                 \n"
+            "    msr psp, r3                                  \n"
+            "    msr psplim, r4                               \n"
+            "    msr control, r5                              \n"
+            "    mov lr, r6                                   \n"
+            "    ldr r4, xSecureContextConst2                 \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "    str r0, [r4]                                 \n" /* Restore xSecureContext. */
+            "                                                 \n"
+            " restore_general_regs_first_task:                \n"
+            "    subs r2, #32                                 \n"
+            "    ldmia r2!, {r4-r7}                           \n" /* r4-r7 contain half of the hardware saved context. */
+            "    stmia r3!, {r4-r7}                           \n" /* Copy half of the the hardware saved context on the task stack. */
+            "    ldmia r2!, {r4-r7}                           \n" /* r4-r7 contain rest half of the hardware saved context. */
+            "    stmia r3!, {r4-r7}                           \n" /* Copy rest half of the the hardware saved context on the task stack. */
+            "    subs r2, #48                                 \n"
+            "    ldmia r2!, {r4-r7}                           \n" /* Restore r8-r11. */
+            "    mov r8, r4                                   \n" /* r8 = r4. */
+            "    mov r9, r5                                   \n" /* r9 = r5. */
+            "    mov r10, r6                                  \n" /* r10 = r6. */
+            "    mov r11, r7                                  \n" /* r11 = r7. */
+            "    subs r2, #32                                 \n"
+            "    ldmia r2!, {r4-r7}                           \n" /* Restore r4-r7. */
+            "    subs r2, #16                                 \n"
+            "                                                 \n"
+            " restore_context_done_first_task:                \n"
+            "    str r2, [r1]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
+            "    bx lr                                        \n"
+            "                                                 \n"
+            " .align 4                                        \n"
+            " pxCurrentTCBConst2: .word pxCurrentTCB          \n"
+            " xSecureContextConst2: .word xSecureContext      \n"
+            " xMPUCTRLConst2: .word 0xe000ed94                \n"
+            " xMAIR0Const2: .word 0xe000edc0                  \n"
+            " xRNRConst2: .word 0xe000ed98                    \n"
+            " xRBARConst2: .word 0xe000ed9c                   \n"
+        );
+    }
 
 #else /* configENABLE_MPU */
 
-void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "   .syntax unified                                 \n"
-        "                                                   \n"
-        "   ldr  r2, pxCurrentTCBConst2                     \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr  r3, [r2]                                   \n"/* Read pxCurrentTCB. */
-        "   ldr  r0, [r3]                                   \n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
-        "                                                   \n"
-        "   ldm  r0!, {r1-r3}                               \n"/* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
-        "   ldr  r4, xSecureContextConst2                   \n"
-        "   str  r1, [r4]                                   \n"/* Set xSecureContext to this task's value for the same. */
-        "   msr  psplim, r2                                 \n"/* Set this task's PSPLIM value. */
-        "   movs r1, #2                                     \n"/* r1 = 2. */
-        "   msr  CONTROL, r1                                \n"/* Switch to use PSP in the thread mode. */
-        "   adds r0, #32                                    \n"/* Discard everything up to r0. */
-        "   msr  psp, r0                                    \n"/* This is now the new top of stack to use in the task. */
-        "   isb                                             \n"
-        "   bx   r3                                         \n"/* Finally, branch to EXC_RETURN. */
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "pxCurrentTCBConst2: .word pxCurrentTCB             \n"
-        "xSecureContextConst2: .word xSecureContext         \n"
-    );
-}
+    void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            "   .syntax unified                                 \n"
+            "                                                   \n"
+            "   ldr  r2, pxCurrentTCBConst2                     \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr  r3, [r2]                                   \n" /* Read pxCurrentTCB. */
+            "   ldr  r0, [r3]                                   \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+            "                                                   \n"
+            "   ldm  r0!, {r1-r3}                               \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
+            "   ldr  r4, xSecureContextConst2                   \n"
+            "   str  r1, [r4]                                   \n" /* Set xSecureContext to this task's value for the same. */
+            "   msr  psplim, r2                                 \n" /* Set this task's PSPLIM value. */
+            "   movs r1, #2                                     \n" /* r1 = 2. */
+            "   msr  CONTROL, r1                                \n" /* Switch to use PSP in the thread mode. */
+            "   adds r0, #32                                    \n" /* Discard everything up to r0. */
+            "   msr  psp, r0                                    \n" /* This is now the new top of stack to use in the task. */
+            "   isb                                             \n"
+            "   bx   r3                                         \n" /* Finally, branch to EXC_RETURN. */
+            "                                                   \n"
+            "   .align 4                                        \n"
+            "pxCurrentTCBConst2: .word pxCurrentTCB             \n"
+            "xSecureContextConst2: .word xSecureContext         \n"
+        );
+    }
 
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
@@ -183,15 +183,15 @@ BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs r0, control                                 \n"/* r0 = CONTROL. */
-        "   movs r1, #1                                     \n"/* r1 = 1. */
-        "   tst r0, r1                                      \n"/* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
-        "   beq running_privileged                          \n"/* If the result of previous AND operation was 0, branch. */
-        "   movs r0, #0                                     \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
-        "   bx lr                                           \n"/* Return. */
+        "   mrs r0, control                                 \n" /* r0 = CONTROL. */
+        "   movs r1, #1                                     \n" /* r1 = 1. */
+        "   tst r0, r1                                      \n" /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
+        "   beq running_privileged                          \n" /* If the result of previous AND operation was 0, branch. */
+        "   movs r0, #0                                     \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+        "   bx lr                                           \n" /* Return. */
         " running_privileged:                               \n"
-        "   movs r0, #1                                     \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
-        "   bx lr                                           \n"/* Return. */
+        "   movs r0, #1                                     \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+        "   bx lr                                           \n" /* Return. */
         "                                                   \n"
         "   .align 4                                        \n"
         ::: "r0", "r1", "memory"
@@ -205,11 +205,11 @@ void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs r0, control                                 \n"/* Read the CONTROL register. */
-        "   movs r1, #1                                     \n"/* r1 = 1. */
-        "   bics r0, r1                                     \n"/* Clear the bit 0. */
-        "   msr control, r0                                 \n"/* Write back the new CONTROL value. */
-        "   bx lr                                           \n"/* Return to the caller. */
+        "   mrs r0, control                                 \n" /* Read the CONTROL register. */
+        "   movs r1, #1                                     \n" /* r1 = 1. */
+        "   bics r0, r1                                     \n" /* Clear the bit 0. */
+        "   msr control, r0                                 \n" /* Write back the new CONTROL value. */
+        "   bx lr                                           \n" /* Return to the caller. */
         ::: "r0", "r1", "memory"
     );
 }
@@ -221,11 +221,11 @@ void vResetPrivilege( void ) /* __attribute__ (( naked )) */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs r0, control                                 \n"/* r0 = CONTROL. */
-        "   movs r1, #1                                     \n"/* r1 = 1. */
-        "   orrs r0, r1                                     \n"/* r0 = r0 | r1. */
-        "   msr control, r0                                 \n"/* CONTROL = r0. */
-        "   bx lr                                           \n"/* Return to the caller. */
+        "   mrs r0, control                                 \n" /* r0 = CONTROL. */
+        "   movs r1, #1                                     \n" /* r1 = 1. */
+        "   orrs r0, r1                                     \n" /* r0 = r0 | r1. */
+        "   msr control, r0                                 \n" /* CONTROL = r0. */
+        "   bx lr                                           \n" /* Return to the caller. */
         ::: "r0", "r1", "memory"
     );
 }
@@ -237,14 +237,14 @@ void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   ldr r0, xVTORConst                              \n"/* Use the NVIC offset register to locate the stack. */
-        "   ldr r0, [r0]                                    \n"/* Read the VTOR register which gives the address of vector table. */
-        "   ldr r0, [r0]                                    \n"/* The first entry in vector table is stack pointer. */
-        "   msr msp, r0                                     \n"/* Set the MSP back to the start of the stack. */
-        "   cpsie i                                         \n"/* Globally enable interrupts. */
+        "   ldr r0, xVTORConst                              \n" /* Use the NVIC offset register to locate the stack. */
+        "   ldr r0, [r0]                                    \n" /* Read the VTOR register which gives the address of vector table. */
+        "   ldr r0, [r0]                                    \n" /* The first entry in vector table is stack pointer. */
+        "   msr msp, r0                                     \n" /* Set the MSP back to the start of the stack. */
+        "   cpsie i                                         \n" /* Globally enable interrupts. */
         "   dsb                                             \n"
         "   isb                                             \n"
-        "   svc %0                                          \n"/* System call to start the first task. */
+        "   svc %0                                          \n" /* System call to start the first task. */
         "   nop                                             \n"
         "                                                   \n"
         "   .align 4                                        \n"
@@ -283,328 +283,328 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
 
 #if ( configENABLE_MPU == 1 )
 
-void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        " .syntax unified                                 \n"
-        " .extern SecureContext_SaveContext               \n"
-        " .extern SecureContext_LoadContext               \n"
-        "                                                 \n"
-        " ldr r3, xSecureContextConst                     \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-        " ldr r0, [r3]                                    \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
-        " ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        " ldr r1, [r3]                                    \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later.*/
-        " ldr r2, [r1]                                    \n" /* r2 = Location in TCB where the context should be saved. */
-        "                                                 \n"
-        " cbz r0, save_ns_context                         \n" /* No secure context to save. */
-        " save_s_context:                                 \n"
-        "    push {r0-r2, lr}                             \n"
-        "    bl SecureContext_SaveContext                 \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-        "    pop {r0-r3}                                  \n" /* LR is now in r3. */
-        "    mov lr, r3                                   \n" /* Restore LR. */
-        "                                                 \n"
-        " save_ns_context:                                \n"
-        "    mov r3, lr                                   \n" /* r3 = LR (EXC_RETURN). */
-        "    lsls r3, r3, #25                             \n" /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-        "    bmi save_special_regs                        \n" /* r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
-        "                                                 \n"
-        " save_general_regs:                              \n"
-        "    mrs r3, psp                                  \n"
-        "    stmia r2!, {r4-r7}                           \n" /* Store r4-r7. */
-        "    mov r4, r8                                   \n" /* r4 = r8. */
-        "    mov r5, r9                                   \n" /* r5 = r9. */
-        "    mov r6, r10                                  \n" /* r6 = r10. */
-        "    mov r7, r11                                  \n" /* r7 = r11. */
-        "    stmia r2!, {r4-r7}                           \n" /* Store r8-r11. */
-        "    ldmia r3!, {r4-r7}                           \n" /* Copy half of the  hardware saved context into r4-r7. */
-        "    stmia r2!, {r4-r7}                           \n" /* Store the hardware saved context. */
-        "    ldmia r3!, {r4-r7}                           \n" /* Copy rest half of the  hardware saved context into r4-r7. */
-        "    stmia r2!, {r4-r7}                           \n" /* Store the hardware saved context. */
-        "                                                 \n"
-        " save_special_regs:                              \n"
-        "    mrs r3, psp                                  \n" /* r3 = PSP. */
-        "    mrs r4, psplim                               \n" /* r4 = PSPLIM. */
-        "    mrs r5, control                              \n" /* r5 = CONTROL. */
-        "    mov r6, lr                                   \n" /* r6 = LR. */
-        "    stmia r2!, {r0, r3-r6}                       \n" /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
-        "    str r2, [r1]                                 \n" /* Save the location from where the context should be restored as the first member of TCB. */
-        "                                                 \n"
-        " select_next_task:                               \n"
-        "    cpsid i                                      \n"
-        "    bl vTaskSwitchContext                        \n"
-        "    cpsie i                                      \n"
-        "                                                 \n"
-        " program_mpu:                                    \n"
-        "    ldr r3, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB.*/
-        "                                                 \n"
-        "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-        "    ldr r1, xMPUCTRLConst                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
-        "    movs r3, #1                                  \n" /* r3 = 1. */
-        "    bics r2, r3                                  \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
-        "    str r2, [r1]                                 \n" /* Disable MPU. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
-        "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-        "    ldr r2, xMAIR0Const                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-        "    str r1, [r2]                                 \n" /* Program MAIR0. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-        "    ldr r1, xRNRConst                            \n" /* r1 = 0xe000ed98 [Location of RNR]. */
-        "                                                 \n"
-        "    movs r3, #4                                  \n" /* r3 = 4. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 4. */
-        "    ldmia r0!, {r4-r5}                           \n" /* Read first set of RBAR/RLAR registers from TCB. */
-        "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "    stmia r2!, {r4-r5}                           \n" /* Write first set of RBAR/RLAR registers. */
-        "    movs r3, #5                                  \n" /* r3 = 5. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 5. */
-        "    ldmia r0!, {r4-r5}                           \n" /* Read second set of RBAR/RLAR registers from TCB. */
-        "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "    stmia r2!, {r4-r5}                           \n" /* Write second set of RBAR/RLAR registers. */
-        "    movs r3, #6                                  \n" /* r3 = 6. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 6. */
-        "    ldmia r0!, {r4-r5}                           \n" /* Read third set of RBAR/RLAR registers from TCB. */
-        "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "    stmia r2!, {r4-r5}                           \n" /* Write third set of RBAR/RLAR registers. */
-        "    movs r3, #7                                  \n" /* r3 = 6. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 7. */
-        "    ldmia r0!, {r4-r5}                           \n" /* Read fourth set of RBAR/RLAR registers from TCB. */
-        "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "    stmia r2!, {r4-r5}                           \n" /* Write fourth set of RBAR/RLAR registers. */
-        "                                                 \n"
-        "    ldr r1, xMPUCTRLConst                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
-        "    movs r3, #1                                  \n" /* r3 = 1. */
-        "    orrs r2, r3                                  \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
-        "    str r2, [r1]                                 \n" /* Enable MPU. */
-        "    dsb                                          \n" /* Force memory writes before continuing. */
-        "                                                 \n"
-        " restore_context:                                \n"
-        "    ldr r3, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r1, [r3]                                 \n" /* r1 = pxCurrentTCB.*/
-        "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
-        "                                                 \n"
-        " restore_special_regs:                           \n"
-        "    subs r2, #20                                 \n"
-        "    ldmia r2!, {r0, r3-r6}                       \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, r6 = LR. */
-        "    subs r2, #20                                 \n"
-        "    msr psp, r3                                  \n"
-        "    msr psplim, r4                               \n"
-        "    msr control, r5                              \n"
-        "    mov lr, r6                                   \n"
-        "    ldr r4, xSecureContextConst                  \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-        "    str r0, [r4]                                 \n" /* Restore xSecureContext. */
-        "    cbz r0, restore_ns_context                   \n" /* No secure context to restore. */
-        "                                                 \n"
-        " restore_s_context:                              \n"
-        "    push {r1-r3, lr}                             \n"
-        "    bl SecureContext_LoadContext                 \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-        "    pop {r1-r4}                                  \n" /* LR is now in r4. */
-        "    mov lr, r4                                   \n"
-        "                                                 \n"
-        " restore_ns_context:                             \n"
-        "    mov r0, lr                                   \n" /* r0 = LR (EXC_RETURN). */
-        "    lsls r0, r0, #25                             \n" /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-        "    bmi restore_context_done                     \n" /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
-        "                                                 \n"
-        " restore_general_regs:                           \n"
-        "    subs r2, #32                                 \n"
-        "    ldmia r2!, {r4-r7}                           \n" /* r4-r7 contain half of the hardware saved context. */
-        "    stmia r3!, {r4-r7}                           \n" /* Copy half of the the hardware saved context on the task stack. */
-        "    ldmia r2!, {r4-r7}                           \n" /* r4-r7 contain rest half of the hardware saved context. */
-        "    stmia r3!, {r4-r7}                           \n" /* Copy rest half of the the hardware saved context on the task stack. */
-        "    subs r2, #48                                 \n"
-        "    ldmia r2!, {r4-r7}                           \n" /* Restore r8-r11. */
-        "    mov r8, r4                                   \n" /* r8 = r4. */
-        "    mov r9, r5                                   \n" /* r9 = r5. */
-        "    mov r10, r6                                  \n" /* r10 = r6. */
-        "    mov r11, r7                                  \n" /* r11 = r7. */
-        "    subs r2, #32                                 \n"
-        "    ldmia r2!, {r4-r7}                           \n" /* Restore r4-r7. */
-        "    subs r2, #16                                 \n"
-        "                                                 \n"
-        " restore_context_done:                           \n"
-        "    str r2, [r1]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
-        "    bx lr                                        \n"
-        "                                                 \n"
-        " .align 4                                        \n"
-        " pxCurrentTCBConst: .word pxCurrentTCB           \n"
-        " xSecureContextConst: .word xSecureContext       \n"
-        " xMPUCTRLConst: .word 0xe000ed94                 \n"
-        " xMAIR0Const: .word 0xe000edc0                   \n"
-        " xRNRConst: .word 0xe000ed98                     \n"
-        " xRBARConst: .word 0xe000ed9c                    \n"
-    );
-}
+    void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                 \n"
+            " .extern SecureContext_SaveContext               \n"
+            " .extern SecureContext_LoadContext               \n"
+            "                                                 \n"
+            " ldr r3, xSecureContextConst                     \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            " ldr r0, [r3]                                    \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+            " ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            " ldr r1, [r3]                                    \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later.*/
+            " ldr r2, [r1]                                    \n" /* r2 = Location in TCB where the context should be saved. */
+            "                                                 \n"
+            " cbz r0, save_ns_context                         \n" /* No secure context to save. */
+            " save_s_context:                                 \n"
+            "    push {r0-r2, lr}                             \n"
+            "    bl SecureContext_SaveContext                 \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+            "    pop {r0-r3}                                  \n" /* LR is now in r3. */
+            "    mov lr, r3                                   \n" /* Restore LR. */
+            "                                                 \n"
+            " save_ns_context:                                \n"
+            "    mov r3, lr                                   \n" /* r3 = LR (EXC_RETURN). */
+            "    lsls r3, r3, #25                             \n" /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+            "    bmi save_special_regs                        \n" /* r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
+            "                                                 \n"
+            " save_general_regs:                              \n"
+            "    mrs r3, psp                                  \n"
+            "    stmia r2!, {r4-r7}                           \n" /* Store r4-r7. */
+            "    mov r4, r8                                   \n" /* r4 = r8. */
+            "    mov r5, r9                                   \n" /* r5 = r9. */
+            "    mov r6, r10                                  \n" /* r6 = r10. */
+            "    mov r7, r11                                  \n" /* r7 = r11. */
+            "    stmia r2!, {r4-r7}                           \n" /* Store r8-r11. */
+            "    ldmia r3!, {r4-r7}                           \n" /* Copy half of the  hardware saved context into r4-r7. */
+            "    stmia r2!, {r4-r7}                           \n" /* Store the hardware saved context. */
+            "    ldmia r3!, {r4-r7}                           \n" /* Copy rest half of the  hardware saved context into r4-r7. */
+            "    stmia r2!, {r4-r7}                           \n" /* Store the hardware saved context. */
+            "                                                 \n"
+            " save_special_regs:                              \n"
+            "    mrs r3, psp                                  \n" /* r3 = PSP. */
+            "    mrs r4, psplim                               \n" /* r4 = PSPLIM. */
+            "    mrs r5, control                              \n" /* r5 = CONTROL. */
+            "    mov r6, lr                                   \n" /* r6 = LR. */
+            "    stmia r2!, {r0, r3-r6}                       \n" /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
+            "    str r2, [r1]                                 \n" /* Save the location from where the context should be restored as the first member of TCB. */
+            "                                                 \n"
+            " select_next_task:                               \n"
+            "    cpsid i                                      \n"
+            "    bl vTaskSwitchContext                        \n"
+            "    cpsie i                                      \n"
+            "                                                 \n"
+            " program_mpu:                                    \n"
+            "    ldr r3, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB.*/
+            "                                                 \n"
+            "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
+            "    ldr r1, xMPUCTRLConst                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
+            "    movs r3, #1                                  \n" /* r3 = 1. */
+            "    bics r2, r3                                  \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
+            "    str r2, [r1]                                 \n" /* Disable MPU. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
+            "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
+            "    ldr r2, xMAIR0Const                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    str r1, [r2]                                 \n" /* Program MAIR0. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
+            "    ldr r1, xRNRConst                            \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "                                                 \n"
+            "    movs r3, #4                                  \n" /* r3 = 4. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 4. */
+            "    ldmia r0!, {r4-r5}                           \n" /* Read first set of RBAR/RLAR registers from TCB. */
+            "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    stmia r2!, {r4-r5}                           \n" /* Write first set of RBAR/RLAR registers. */
+            "    movs r3, #5                                  \n" /* r3 = 5. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 5. */
+            "    ldmia r0!, {r4-r5}                           \n" /* Read second set of RBAR/RLAR registers from TCB. */
+            "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    stmia r2!, {r4-r5}                           \n" /* Write second set of RBAR/RLAR registers. */
+            "    movs r3, #6                                  \n" /* r3 = 6. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 6. */
+            "    ldmia r0!, {r4-r5}                           \n" /* Read third set of RBAR/RLAR registers from TCB. */
+            "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    stmia r2!, {r4-r5}                           \n" /* Write third set of RBAR/RLAR registers. */
+            "    movs r3, #7                                  \n" /* r3 = 6. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 7. */
+            "    ldmia r0!, {r4-r5}                           \n" /* Read fourth set of RBAR/RLAR registers from TCB. */
+            "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    stmia r2!, {r4-r5}                           \n" /* Write fourth set of RBAR/RLAR registers. */
+            "                                                 \n"
+            "    ldr r1, xMPUCTRLConst                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
+            "    movs r3, #1                                  \n" /* r3 = 1. */
+            "    orrs r2, r3                                  \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
+            "    str r2, [r1]                                 \n" /* Enable MPU. */
+            "    dsb                                          \n" /* Force memory writes before continuing. */
+            "                                                 \n"
+            " restore_context:                                \n"
+            "    ldr r3, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r1, [r3]                                 \n" /* r1 = pxCurrentTCB.*/
+            "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
+            "                                                 \n"
+            " restore_special_regs:                           \n"
+            "    subs r2, #20                                 \n"
+            "    ldmia r2!, {r0, r3-r6}                       \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, r6 = LR. */
+            "    subs r2, #20                                 \n"
+            "    msr psp, r3                                  \n"
+            "    msr psplim, r4                               \n"
+            "    msr control, r5                              \n"
+            "    mov lr, r6                                   \n"
+            "    ldr r4, xSecureContextConst                  \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "    str r0, [r4]                                 \n" /* Restore xSecureContext. */
+            "    cbz r0, restore_ns_context                   \n" /* No secure context to restore. */
+            "                                                 \n"
+            " restore_s_context:                              \n"
+            "    push {r1-r3, lr}                             \n"
+            "    bl SecureContext_LoadContext                 \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+            "    pop {r1-r4}                                  \n" /* LR is now in r4. */
+            "    mov lr, r4                                   \n"
+            "                                                 \n"
+            " restore_ns_context:                             \n"
+            "    mov r0, lr                                   \n" /* r0 = LR (EXC_RETURN). */
+            "    lsls r0, r0, #25                             \n" /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+            "    bmi restore_context_done                     \n" /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
+            "                                                 \n"
+            " restore_general_regs:                           \n"
+            "    subs r2, #32                                 \n"
+            "    ldmia r2!, {r4-r7}                           \n" /* r4-r7 contain half of the hardware saved context. */
+            "    stmia r3!, {r4-r7}                           \n" /* Copy half of the the hardware saved context on the task stack. */
+            "    ldmia r2!, {r4-r7}                           \n" /* r4-r7 contain rest half of the hardware saved context. */
+            "    stmia r3!, {r4-r7}                           \n" /* Copy rest half of the the hardware saved context on the task stack. */
+            "    subs r2, #48                                 \n"
+            "    ldmia r2!, {r4-r7}                           \n" /* Restore r8-r11. */
+            "    mov r8, r4                                   \n" /* r8 = r4. */
+            "    mov r9, r5                                   \n" /* r9 = r5. */
+            "    mov r10, r6                                  \n" /* r10 = r6. */
+            "    mov r11, r7                                  \n" /* r11 = r7. */
+            "    subs r2, #32                                 \n"
+            "    ldmia r2!, {r4-r7}                           \n" /* Restore r4-r7. */
+            "    subs r2, #16                                 \n"
+            "                                                 \n"
+            " restore_context_done:                           \n"
+            "    str r2, [r1]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
+            "    bx lr                                        \n"
+            "                                                 \n"
+            " .align 4                                        \n"
+            " pxCurrentTCBConst: .word pxCurrentTCB           \n"
+            " xSecureContextConst: .word xSecureContext       \n"
+            " xMPUCTRLConst: .word 0xe000ed94                 \n"
+            " xMAIR0Const: .word 0xe000edc0                   \n"
+            " xRNRConst: .word 0xe000ed98                     \n"
+            " xRBARConst: .word 0xe000ed9c                    \n"
+        );
+    }
 
 #else /* configENABLE_MPU */
 
-void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "   .syntax unified                                 \n"
-        "   .extern SecureContext_SaveContext               \n"
-        "   .extern SecureContext_LoadContext               \n"
-        "                                                   \n"
-        "   ldr r3, xSecureContextConst                     \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
-        "   ldr r0, [r3]                                    \n"/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
-        "   ldr r3, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r3]                                    \n"/* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later.*/
-        "   mrs r2, psp                                     \n"/* Read PSP in r2. */
-        "                                                   \n"
-        "   cbz r0, save_ns_context                         \n"/* No secure context to save. */
-        "   push {r0-r2, r14}                               \n"
-        "   bl SecureContext_SaveContext                    \n"/* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-        "   pop {r0-r3}                                     \n"/* LR is now in r3. */
-        "   mov lr, r3                                      \n"/* LR = r3. */
-        "   lsls r1, r3, #25                                \n"/* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-        "   bpl save_ns_context                             \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-        "   ldr r3, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r3]                                    \n"/* Read pxCurrentTCB. */
-        "   subs r2, r2, #12                                \n"/* Make space for xSecureContext, PSPLIM and LR on the stack. */
-        "   str r2, [r1]                                    \n"/* Save the new top of stack in TCB. */
-        "   mrs r1, psplim                                  \n"/* r1 = PSPLIM. */
-        "   mov r3, lr                                      \n"/* r3 = LR/EXC_RETURN. */
-        "   stmia r2!, {r0, r1, r3}                         \n"/* Store xSecureContext, PSPLIM and LR on the stack. */
-        "   b select_next_task                              \n"
-        "                                                   \n"
-        " save_ns_context:                                  \n"
-        "   ldr r3, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r3]                                    \n"/* Read pxCurrentTCB. */
-        "   subs r2, r2, #44                                \n"/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
-        "   str r2, [r1]                                    \n"/* Save the new top of stack in TCB. */
-        "   mrs r1, psplim                                  \n"/* r1 = PSPLIM. */
-        "   mov r3, lr                                      \n"/* r3 = LR/EXC_RETURN. */
-        "   stmia r2!, {r0, r1, r3-r7}                      \n"/* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */
-        "   mov r4, r8                                      \n"/* r4 = r8. */
-        "   mov r5, r9                                      \n"/* r5 = r9. */
-        "   mov r6, r10                                     \n"/* r6 = r10. */
-        "   mov r7, r11                                     \n"/* r7 = r11. */
-        "   stmia r2!, {r4-r7}                              \n"/* Store the high registers that are not saved automatically. */
-        "                                                   \n"
-        " select_next_task:                                 \n"
-        "   cpsid i                                         \n"
-        "   bl vTaskSwitchContext                           \n"
-        "   cpsie i                                         \n"
-        "                                                   \n"
-        "   ldr r3, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r3]                                    \n"/* Read pxCurrentTCB. */
-        "   ldr r2, [r1]                                    \n"/* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
-        "                                                   \n"
-        "   ldmia r2!, {r0, r1, r4}                         \n"/* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
-        "   msr psplim, r1                                  \n"/* Restore the PSPLIM register value for the task. */
-        "   mov lr, r4                                      \n"/* LR = r4. */
-        "   ldr r3, xSecureContextConst                     \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
-        "   str r0, [r3]                                    \n"/* Restore the task's xSecureContext. */
-        "   cbz r0, restore_ns_context                      \n"/* If there is no secure context for the task, restore the non-secure context. */
-        "   ldr r3, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r3]                                    \n"/* Read pxCurrentTCB. */
-        "   push {r2, r4}                                   \n"
-        "   bl SecureContext_LoadContext                    \n"/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-        "   pop {r2, r4}                                    \n"
-        "   mov lr, r4                                      \n"/* LR = r4. */
-        "   lsls r1, r4, #25                                \n"/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-        "   bpl restore_ns_context                          \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-        "   msr psp, r2                                     \n"/* Remember the new top of stack for the task. */
-        "   bx lr                                           \n"
-        "                                                   \n"
-        " restore_ns_context:                               \n"
-        "   adds r2, r2, #16                                \n"/* Move to the high registers. */
-        "   ldmia r2!, {r4-r7}                              \n"/* Restore the high registers that are not automatically restored. */
-        "   mov r8, r4                                      \n"/* r8 = r4. */
-        "   mov r9, r5                                      \n"/* r9 = r5. */
-        "   mov r10, r6                                     \n"/* r10 = r6. */
-        "   mov r11, r7                                     \n"/* r11 = r7. */
-        "   msr psp, r2                                     \n"/* Remember the new top of stack for the task. */
-        "   subs r2, r2, #32                                \n"/* Go back to the low registers. */
-        "   ldmia r2!, {r4-r7}                              \n"/* Restore the low registers that are not automatically restored. */
-        "   bx lr                                           \n"
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "pxCurrentTCBConst: .word pxCurrentTCB              \n"
-        "xSecureContextConst: .word xSecureContext          \n"
-    );
-}
+    void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            "   .syntax unified                                 \n"
+            "   .extern SecureContext_SaveContext               \n"
+            "   .extern SecureContext_LoadContext               \n"
+            "                                                   \n"
+            "   ldr r3, xSecureContextConst                     \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "   ldr r0, [r3]                                    \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later.*/
+            "   mrs r2, psp                                     \n" /* Read PSP in r2. */
+            "                                                   \n"
+            "   cbz r0, save_ns_context                         \n" /* No secure context to save. */
+            "   push {r0-r2, r14}                               \n"
+            "   bl SecureContext_SaveContext                    \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+            "   pop {r0-r3}                                     \n" /* LR is now in r3. */
+            "   mov lr, r3                                      \n" /* LR = r3. */
+            "   lsls r1, r3, #25                                \n" /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+            "   bpl save_ns_context                             \n" /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
+            "   subs r2, r2, #12                                \n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */
+            "   str r2, [r1]                                    \n" /* Save the new top of stack in TCB. */
+            "   mrs r1, psplim                                  \n" /* r1 = PSPLIM. */
+            "   mov r3, lr                                      \n" /* r3 = LR/EXC_RETURN. */
+            "   stmia r2!, {r0, r1, r3}                         \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
+            "   b select_next_task                              \n"
+            "                                                   \n"
+            " save_ns_context:                                  \n"
+            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
+            "   subs r2, r2, #44                                \n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
+            "   str r2, [r1]                                    \n" /* Save the new top of stack in TCB. */
+            "   mrs r1, psplim                                  \n" /* r1 = PSPLIM. */
+            "   mov r3, lr                                      \n" /* r3 = LR/EXC_RETURN. */
+            "   stmia r2!, {r0, r1, r3-r7}                      \n" /* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */
+            "   mov r4, r8                                      \n" /* r4 = r8. */
+            "   mov r5, r9                                      \n" /* r5 = r9. */
+            "   mov r6, r10                                     \n" /* r6 = r10. */
+            "   mov r7, r11                                     \n" /* r7 = r11. */
+            "   stmia r2!, {r4-r7}                              \n" /* Store the high registers that are not saved automatically. */
+            "                                                   \n"
+            " select_next_task:                                 \n"
+            "   cpsid i                                         \n"
+            "   bl vTaskSwitchContext                           \n"
+            "   cpsie i                                         \n"
+            "                                                   \n"
+            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
+            "   ldr r2, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
+            "                                                   \n"
+            "   ldmia r2!, {r0, r1, r4}                         \n" /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
+            "   msr psplim, r1                                  \n" /* Restore the PSPLIM register value for the task. */
+            "   mov lr, r4                                      \n" /* LR = r4. */
+            "   ldr r3, xSecureContextConst                     \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "   str r0, [r3]                                    \n" /* Restore the task's xSecureContext. */
+            "   cbz r0, restore_ns_context                      \n" /* If there is no secure context for the task, restore the non-secure context. */
+            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
+            "   push {r2, r4}                                   \n"
+            "   bl SecureContext_LoadContext                    \n" /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+            "   pop {r2, r4}                                    \n"
+            "   mov lr, r4                                      \n" /* LR = r4. */
+            "   lsls r1, r4, #25                                \n" /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+            "   bpl restore_ns_context                          \n" /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+            "   msr psp, r2                                     \n" /* Remember the new top of stack for the task. */
+            "   bx lr                                           \n"
+            "                                                   \n"
+            " restore_ns_context:                               \n"
+            "   adds r2, r2, #16                                \n" /* Move to the high registers. */
+            "   ldmia r2!, {r4-r7}                              \n" /* Restore the high registers that are not automatically restored. */
+            "   mov r8, r4                                      \n" /* r8 = r4. */
+            "   mov r9, r5                                      \n" /* r9 = r5. */
+            "   mov r10, r6                                     \n" /* r10 = r6. */
+            "   mov r11, r7                                     \n" /* r11 = r7. */
+            "   msr psp, r2                                     \n" /* Remember the new top of stack for the task. */
+            "   subs r2, r2, #32                                \n" /* Go back to the low registers. */
+            "   ldmia r2!, {r4-r7}                              \n" /* Restore the low registers that are not automatically restored. */
+            "   bx lr                                           \n"
+            "                                                   \n"
+            "   .align 4                                        \n"
+            "pxCurrentTCBConst: .word pxCurrentTCB              \n"
+            "xSecureContextConst: .word xSecureContext          \n"
+        );
+    }
 
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-   __asm volatile
-    (
-        ".syntax unified                \n"
-        ".extern vPortSVCHandler_C      \n"
-        ".extern vSystemCallEnter       \n"
-        ".extern vSystemCallEnter_1     \n"
-        ".extern vSystemCallExit        \n"
-        "                               \n"
-        "movs r0, #4                    \n"
-        "mov r1, lr                     \n"
-        "tst r0, r1                     \n"
-        "beq stack_on_msp               \n"
-        "stack_on_psp:                  \n"
-        "    mrs r0, psp                \n"
-        "    b route_svc                \n"
-        "stack_on_msp:                  \n"
-        "    mrs r0, msp                \n"
-        "    b route_svc                \n"
-        "                               \n"
-        "route_svc:                     \n"
-        "    ldr r2, [r0, #24]          \n"
-        "    subs r2, #2                \n"
-        "    ldrb r3, [r2, #0]          \n"
-        "    cmp r3, %0                 \n"
-        "    beq system_call_enter      \n"
-        "    cmp r3, %1                 \n"
-        "    beq system_call_enter_1    \n"
-        "    cmp r3, %2                 \n"
-        "    beq system_call_exit       \n"
-        "    b vPortSVCHandler_C        \n"
-        "                               \n"
-        "system_call_enter:             \n"
-        "    b vSystemCallEnter         \n"
-        "system_call_enter_1:           \n"
-        "    b vSystemCallEnter_1       \n"
-        "system_call_exit:              \n"
-        "    b vSystemCallExit          \n"
-        "                               \n"
-        : /* No outputs. */
-        :"i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT )
-        : "r0", "r1", "r2", "r3", "memory"
-    );
-}
+    void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            ".syntax unified                \n"
+            ".extern vPortSVCHandler_C      \n"
+            ".extern vSystemCallEnter       \n"
+            ".extern vSystemCallEnter_1     \n"
+            ".extern vSystemCallExit        \n"
+            "                               \n"
+            "movs r0, #4                    \n"
+            "mov r1, lr                     \n"
+            "tst r0, r1                     \n"
+            "beq stack_on_msp               \n"
+            "stack_on_psp:                  \n"
+            "    mrs r0, psp                \n"
+            "    b route_svc                \n"
+            "stack_on_msp:                  \n"
+            "    mrs r0, msp                \n"
+            "    b route_svc                \n"
+            "                               \n"
+            "route_svc:                     \n"
+            "    ldr r2, [r0, #24]          \n"
+            "    subs r2, #2                \n"
+            "    ldrb r3, [r2, #0]          \n"
+            "    cmp r3, %0                 \n"
+            "    beq system_call_enter      \n"
+            "    cmp r3, %1                 \n"
+            "    beq system_call_enter_1    \n"
+            "    cmp r3, %2                 \n"
+            "    beq system_call_exit       \n"
+            "    b vPortSVCHandler_C        \n"
+            "                               \n"
+            "system_call_enter:             \n"
+            "    b vSystemCallEnter         \n"
+            "system_call_enter_1:           \n"
+            "    b vSystemCallEnter_1       \n"
+            "system_call_exit:              \n"
+            "    b vSystemCallExit          \n"
+            "                               \n"
+            : /* No outputs. */
+            : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT )
+            : "r0", "r1", "r2", "r3", "memory"
+        );
+    }
 
 #else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
-void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "   .syntax unified                                 \n"
-        "                                                   \n"
-        "   movs r0, #4                                     \n"
-        "   mov r1, lr                                      \n"
-        "   tst r0, r1                                      \n"
-        "   beq stacking_used_msp                           \n"
-        "   mrs r0, psp                                     \n"
-        "   ldr r2, svchandler_address_const                \n"
-        "   bx r2                                           \n"
-        " stacking_used_msp:                                \n"
-        "   mrs r0, msp                                     \n"
-        "   ldr r2, svchandler_address_const                \n"
-        "   bx r2                                           \n"
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "svchandler_address_const: .word vPortSVCHandler_C  \n"
-    );
-}
+    void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            "   .syntax unified                                 \n"
+            "                                                   \n"
+            "   movs r0, #4                                     \n"
+            "   mov r1, lr                                      \n"
+            "   tst r0, r1                                      \n"
+            "   beq stacking_used_msp                           \n"
+            "   mrs r0, psp                                     \n"
+            "   ldr r2, svchandler_address_const                \n"
+            "   bx r2                                           \n"
+            " stacking_used_msp:                                \n"
+            "   mrs r0, msp                                     \n"
+            "   ldr r2, svchandler_address_const                \n"
+            "   bx r2                                           \n"
+            "                                                   \n"
+            "   .align 4                                        \n"
+            "svchandler_address_const: .word vPortSVCHandler_C  \n"
+        );
+    }
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
@@ -615,8 +615,8 @@ void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   svc %0                                          \n"/* Secure context is allocated in the supervisor call. */
-        "   bx lr                                           \n"/* Return. */
+        "   svc %0                                          \n" /* Secure context is allocated in the supervisor call. */
+        "   bx lr                                           \n" /* Return. */
         ::"i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"
     );
 }
@@ -628,14 +628,14 @@ void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PR
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   ldr r2, [r0]                                    \n"/* The first item in the TCB is the top of the stack. */
-        "   ldr r1, [r2]                                    \n"/* The first item on the stack is the task's xSecureContext. */
-        "   cmp r1, #0                                      \n"/* Raise svc if task's xSecureContext is not NULL. */
-        "   bne free_secure_context                         \n"/* Branch if r1 != 0. */
-        "   bx lr                                           \n"/* There is no secure context (xSecureContext is NULL). */
+        "   ldr r2, [r0]                                    \n" /* The first item in the TCB is the top of the stack. */
+        "   ldr r1, [r2]                                    \n" /* The first item on the stack is the task's xSecureContext. */
+        "   cmp r1, #0                                      \n" /* Raise svc if task's xSecureContext is not NULL. */
+        "   bne free_secure_context                         \n" /* Branch if r1 != 0. */
+        "   bx lr                                           \n" /* There is no secure context (xSecureContext is NULL). */
         " free_secure_context:                              \n"
-        "   svc %0                                          \n"/* Secure context is freed in the supervisor call. */
-        "   bx lr                                           \n"/* Return. */
+        "   svc %0                                          \n" /* Secure context is freed in the supervisor call. */
+        "   bx lr                                           \n" /* Return. */
         ::"i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"
     );
 }
diff --git a/portable/GCC/ARM_CM23/non_secure/portmacro.h b/portable/GCC/ARM_CM23/non_secure/portmacro.h
index 233ea5a57..33d522488 100644
--- a/portable/GCC/ARM_CM23/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM23/non_secure/portmacro.h
@@ -48,9 +48,9 @@
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME                       "Cortex-M23"
-#define portHAS_ARMV8M_MAIN_EXTENSION       0
-#define portDONT_DISCARD                    __attribute__( ( used ) )
+#define portARCH_NAME                    "Cortex-M23"
+#define portHAS_ARMV8M_MAIN_EXTENSION    0
+#define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
 /* ARMv8-M common port configurations. */
diff --git a/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h
index e5ffdb48b..62e462a27 100644
--- a/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h
@@ -81,8 +81,8 @@ typedef unsigned long    UBaseType_t;
     typedef uint32_t     TickType_t;
     #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-     * not need to be guarded with a critical section. */
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
     #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -117,7 +117,7 @@ extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGE
 extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
 
 #if ( configENABLE_TRUSTZONE == 1 )
-    extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize );     /* __attribute__ (( naked )) */
+    extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
     extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
 #endif /* configENABLE_TRUSTZONE */
 
@@ -188,13 +188,13 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Settings to define an MPU region.
-     */
+/**
+ * @brief Settings to define an MPU region.
+ */
     typedef struct MPURegionSettings
     {
-        uint32_t ulRBAR;     /**< RBAR for the region. */
-        uint32_t ulRLAR;     /**< RLAR for the region. */
+        uint32_t ulRBAR; /**< RBAR for the region. */
+        uint32_t ulRLAR; /**< RLAR for the region. */
     } MPURegionSettings_t;
 
     #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
@@ -203,9 +203,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-        /**
-         * @brief System call stack.
-         */
+/**
+ * @brief System call stack.
+ */
         typedef struct SYSTEM_CALL_STACK_INFO
         {
             uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ];
@@ -218,74 +218,74 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
-    /**
-     * @brief MPU settings as stored in the TCB.
-     */
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
     #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
 
-        #if( configENABLE_TRUSTZONE == 1 )
+        #if ( configENABLE_TRUSTZONE == 1 )
 
-            /*
-             * +-----------+---------------+----------+-----------------+------------------------------+-----+
-             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
-             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
-             * +-----------+---------------+----------+-----------------+------------------------------+-----+
-             *
-             * <-----------><--------------><---------><----------------><-----------------------------><---->
-             *      16             16            8               8                     5                   1
-             */
-            #define MAX_CONTEXT_SIZE 54
+/*
+ * +-----------+---------------+----------+-----------------+------------------------------+-----+
+ * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+ * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+ * +-----------+---------------+----------+-----------------+------------------------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><-----------------------------><---->
+ *      16             16            8               8                     5                   1
+ */
+            #define MAX_CONTEXT_SIZE    54
 
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-            /*
-             * +-----------+---------------+----------+-----------------+----------------------+-----+
-             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
-             * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
-             * +-----------+---------------+----------+-----------------+----------------------+-----+
-             *
-             * <-----------><--------------><---------><----------------><---------------------><---->
-             *      16             16            8               8                  4              1
-             */
-            #define MAX_CONTEXT_SIZE 53
+/*
+ * +-----------+---------------+----------+-----------------+----------------------+-----+
+ * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+ * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
+ * +-----------+---------------+----------+-----------------+----------------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><---------------------><---->
+ *      16             16            8               8                  4              1
+ */
+            #define MAX_CONTEXT_SIZE    53
 
         #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
 
     #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-        #if( configENABLE_TRUSTZONE == 1 )
+        #if ( configENABLE_TRUSTZONE == 1 )
 
-            /*
-             * +----------+-----------------+------------------------------+-----+
-             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
-             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
-             * +----------+-----------------+------------------------------+-----+
-             *
-             * <---------><----------------><------------------------------><---->
-             *     8               8                      5                   1
-             */
-            #define MAX_CONTEXT_SIZE 22
+/*
+ * +----------+-----------------+------------------------------+-----+
+ * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+ * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+ * +----------+-----------------+------------------------------+-----+
+ *
+ * <---------><----------------><------------------------------><---->
+ *     8               8                      5                   1
+ */
+            #define MAX_CONTEXT_SIZE    22
 
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-            /*
-             * +----------+-----------------+----------------------+-----+
-             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
-             * |          | PC, xPSR        | EXC_RETURN           |     |
-             * +----------+-----------------+----------------------+-----+
-             *
-             * <---------><----------------><----------------------><---->
-             *     8               8                  4              1
-             */
-            #define MAX_CONTEXT_SIZE 21
+/*
+ * +----------+-----------------+----------------------+-----+
+ * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+ * |          | PC, xPSR        | EXC_RETURN           |     |
+ * +----------+-----------------+----------------------+-----+
+ *
+ * <---------><----------------><----------------------><---->
+ *     8               8                  4              1
+ */
+            #define MAX_CONTEXT_SIZE    21
 
         #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
 
     #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-    /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
-    #define portSTACK_FRAME_HAS_PADDING_FLAG     ( 1UL << 0UL )
-    #define portTASK_IS_PRIVILEGED_FLAG          ( 1UL << 1UL )
+/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
+    #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
+    #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
     typedef struct MPU_SETTINGS
     {
@@ -364,49 +364,49 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-    /**
-     * @brief Allocate a secure context for the task.
-     *
-     * Tasks are not created with a secure context. Any task that is going to call
-     * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
-     * secure context before it calls any secure function.
-     *
-     * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
-     */
+/**
+ * @brief Allocate a secure context for the task.
+ *
+ * Tasks are not created with a secure context. Any task that is going to call
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+ * secure context before it calls any secure function.
+ *
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+ */
     #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
 
-    /**
-     * @brief Called when a task is deleted to delete the task's secure context,
-     * if it has one.
-     *
-     * @param[in] pxTCB The TCB of the task being deleted.
-     */
+/**
+ * @brief Called when a task is deleted to delete the task's secure context,
+ * if it has one.
+ *
+ * @param[in] pxTCB The TCB of the task being deleted.
+ */
     #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
 #endif /* configENABLE_TRUSTZONE */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Checks whether or not the processor is privileged.
-     *
-     * @return 1 if the processor is already privileged, 0 otherwise.
-     */
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
     #define portIS_PRIVILEGED()      xIsPrivileged()
 
-    /**
-     * @brief Raise an SVC request to raise privilege.
-     *
-     * The SVC handler checks that the SVC was raised from a system call and only
-     * then it raises the privilege. If this is called from any other place,
-     * the privilege is not raised.
-     */
+/**
+ * @brief Raise an SVC request to raise privilege.
+ *
+ * The SVC handler checks that the SVC was raised from a system call and only
+ * then it raises the privilege. If this is called from any other place,
+ * the privilege is not raised.
+ */
     #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
 
-    /**
-     * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
-     * register.
-     */
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
     #define portRESET_PRIVILEGE()    vResetPrivilege()
 #else
     #define portIS_PRIVILEGED()
@@ -419,12 +419,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     extern BaseType_t xPortIsTaskPrivileged( void );
 
-    /**
-     * @brief Checks whether or not the calling task is privileged.
-     *
-     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
-     */
-    #define portIS_TASK_PRIVILEGED()      xPortIsTaskPrivileged()
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
+    #define portIS_TASK_PRIVILEGED()    xPortIsTaskPrivileged()
 
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
@@ -439,9 +439,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * based on whether or not Mainline extension is implemented. */
 #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
     #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
-        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
     #else
-        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    0
     #endif
 #endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
 
@@ -450,9 +450,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  */
 #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
 
-    /**
-     * @brief Count the number of leading zeros in a 32-bit value.
-     */
+/**
+ * @brief Count the number of leading zeros in a 32-bit value.
+ */
     static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
     {
         uint32_t ulReturn;
@@ -462,7 +462,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         return ulReturn;
     }
 
-    /* Check the configuration. */
+/* Check the configuration. */
     #if ( configMAX_PRIORITIES > 32 )
         #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
     #endif
@@ -471,16 +471,16 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection.  Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
     #endif
 
-    /**
-     * @brief Store/clear the ready priorities in a bit map.
-     */
-    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+/**
+ * @brief Store/clear the ready priorities in a bit map.
+ */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )      ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )       ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 
-    /**
-     * @brief Get the priority of the highest-priority task that is ready to execute.
-     */
-    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )   uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+/**
+ * @brief Get the priority of the highest-priority task that is ready to execute.
+ */
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
 
 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM23/secure/secure_context.c b/portable/GCC/ARM_CM23/secure/secure_context.c
index 0730d574d..7d2171996 100644
--- a/portable/GCC/ARM_CM23/secure/secure_context.c
+++ b/portable/GCC/ARM_CM23/secure/secure_context.c
@@ -65,7 +65,7 @@
  * @brief Maximum number of secure contexts.
  */
 #ifndef secureconfigMAX_SECURE_CONTEXTS
-    #define secureconfigMAX_SECURE_CONTEXTS        8UL
+    #define secureconfigMAX_SECURE_CONTEXTS    8UL
 #endif
 /*-----------------------------------------------------------*/
 
@@ -164,15 +164,15 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
         }
 
         #if ( configENABLE_MPU == 1 )
-            {
-                /* Configure thread mode to use PSP and to be unprivileged. */
-                secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
-            }
+        {
+            /* Configure thread mode to use PSP and to be unprivileged. */
+            secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
+        }
         #else /* configENABLE_MPU */
-            {
-                /* Configure thread mode to use PSP and to be privileged. */
-                secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
-            }
+        {
+            /* Configure thread mode to use PSP and to be privileged. */
+            secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
+        }
         #endif /* configENABLE_MPU */
     }
 }
@@ -219,16 +219,16 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
             if( pucStackMemory != NULL )
             {
                 /* Since stack grows down, the starting point will be the last
-                 * location. Note that this location is next to the last
-                 * allocated byte for stack (excluding the space for seal values)
-                 * because the hardware decrements the stack pointer before
-                 * writing i.e. if stack pointer is 0x2, a push operation will
-                 * decrement the stack pointer to 0x1 and then write at 0x1. */
+                * location. Note that this location is next to the last
+                * allocated byte for stack (excluding the space for seal values)
+                * because the hardware decrements the stack pointer before
+                * writing i.e. if stack pointer is 0x2, a push operation will
+                * decrement the stack pointer to 0x1 and then write at 0x1. */
                 xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize;
 
                 /* Seal the created secure process stack. */
-                *( uint32_t * )( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE;
-                *( uint32_t * )( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE;
+                *( uint32_t * ) ( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE;
+                *( uint32_t * ) ( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE;
 
                 /* The stack cannot go beyond this location. This value is
                  * programmed in the PSPLIM register on context switch.*/
@@ -237,32 +237,32 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
                 xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle;
 
                 #if ( configENABLE_MPU == 1 )
+                {
+                    /* Store the correct CONTROL value for the task on the stack.
+                     * This value is programmed in the CONTROL register on
+                     * context switch. */
+                    pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart;
+                    pulCurrentStackPointer--;
+
+                    if( ulIsTaskPrivileged )
                     {
-                        /* Store the correct CONTROL value for the task on the stack.
-                         * This value is programmed in the CONTROL register on
-                         * context switch. */
-                        pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart;
-                        pulCurrentStackPointer--;
-
-                        if( ulIsTaskPrivileged )
-                        {
-                            *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
-                        }
-                        else
-                        {
-                            *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
-                        }
-
-                        /* Store the current stack pointer. This value is programmed in
-                         * the PSP register on context switch. */
-                        xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+                        *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
                     }
+                    else
+                    {
+                        *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
+                    }
+
+                    /* Store the current stack pointer. This value is programmed in
+                     * the PSP register on context switch. */
+                    xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+                }
                 #else /* configENABLE_MPU */
-                    {
-                        /* Current SP is set to the starting of the stack. This
-                         * value programmed in the PSP register on context switch. */
-                        xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart;
-                    }
+                {
+                    /* Current SP is set to the starting of the stack. This
+                     * value programmed in the PSP register on context switch. */
+                    xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart;
+                }
                 #endif /* configENABLE_MPU */
 
                 /* Ensure to never return 0 as a valid context handle. */
@@ -275,7 +275,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
 }
 /*-----------------------------------------------------------*/
 
-secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle,
+                                                              void * pvTaskHandle )
 {
     uint32_t ulIPSR, ulSecureContextIndex;
 
@@ -306,7 +307,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandl
 }
 /*-----------------------------------------------------------*/
 
-secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle,
+                                                              void * pvTaskHandle )
 {
     uint8_t * pucStackLimit;
     uint32_t ulSecureContextIndex;
@@ -328,7 +330,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandl
 }
 /*-----------------------------------------------------------*/
 
-secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle,
+                                                              void * pvTaskHandle )
 {
     uint8_t * pucStackLimit;
     uint32_t ulSecureContextIndex;
diff --git a/portable/GCC/ARM_CM23/secure/secure_context.h b/portable/GCC/ARM_CM23/secure/secure_context.h
index d0adbaf01..0bf776198 100644
--- a/portable/GCC/ARM_CM23/secure/secure_context.h
+++ b/portable/GCC/ARM_CM23/secure/secure_context.h
@@ -38,12 +38,12 @@
 /**
  * @brief PSP value when no secure context is loaded.
  */
-#define securecontextNO_STACK               0x0
+#define securecontextNO_STACK              0x0
 
 /**
  * @brief Invalid context ID.
  */
-#define securecontextINVALID_CONTEXT_ID     0UL
+#define securecontextINVALID_CONTEXT_ID    0UL
 /*-----------------------------------------------------------*/
 
 /**
@@ -108,7 +108,8 @@ void SecureContext_Init( void );
  * @param[in] xSecureContextHandle Context handle corresponding to the
  * context to be freed.
  */
-void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle,
+                                void * pvTaskHandle );
 
 /**
  * @brief Loads the given context.
@@ -119,7 +120,8 @@ void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void
  * @param[in] xSecureContextHandle Context handle corresponding to the context
  * to be loaded.
  */
-void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle,
+                                void * pvTaskHandle );
 
 /**
  * @brief Saves the given context.
@@ -130,6 +132,7 @@ void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void
  * @param[in] xSecureContextHandle Context handle corresponding to the context
  * to be saved.
  */
-void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle,
+                                void * pvTaskHandle );
 
 #endif /* __SECURE_CONTEXT_H__ */
diff --git a/portable/GCC/ARM_CM23/secure/secure_heap.c b/portable/GCC/ARM_CM23/secure/secure_heap.c
index f3b80df54..1ec3bdbdb 100644
--- a/portable/GCC/ARM_CM23/secure/secure_heap.c
+++ b/portable/GCC/ARM_CM23/secure/secure_heap.c
@@ -67,7 +67,7 @@
 #define secureheapSIZE_MAX              ( ~( ( size_t ) 0 ) )
 
 /* Check if adding a and b will result in overflow. */
-#define secureheapADD_WILL_OVERFLOW( a, b )         ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) )
+#define secureheapADD_WILL_OVERFLOW( a, b )    ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) )
 
 /* MSB of the xBlockSize member of an BlockLink_t structure is used to track
  * the allocation status of a block.  When MSB of the xBlockSize member of
@@ -397,17 +397,17 @@ void * pvPortMalloc( size_t xWantedSize )
     traceMALLOC( pvReturn, xWantedSize );
 
     #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
+    {
+        if( pvReturn == NULL )
         {
-            if( pvReturn == NULL )
-            {
-                extern void vApplicationMallocFailedHook( void );
-                vApplicationMallocFailedHook();
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
+            extern void vApplicationMallocFailedHook( void );
+            vApplicationMallocFailedHook();
         }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
     #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */
 
     secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );
diff --git a/portable/GCC/ARM_CM23/secure/secure_init.c b/portable/GCC/ARM_CM23/secure/secure_init.c
index dc19ebc7d..b89c5f644 100644
--- a/portable/GCC/ARM_CM23/secure/secure_init.c
+++ b/portable/GCC/ARM_CM23/secure/secure_init.c
@@ -93,7 +93,7 @@ secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )
          * permitted. CP11 should be programmed to the same value as CP10. */
         *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
 
-        /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
+        /* LSPENS = 0 ==> LSPEN is writable from non-secure state. This ensures
          * that we can enable/disable lazy stacking in port.c file. */
         *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK );
 
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.c
index f6fb0e778..00c8bcfa8 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.c
@@ -44,2344 +44,2344 @@
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-#if ( INCLUDE_xTaskDelayUntil == 1 )
+    #if ( INCLUDE_xTaskDelayUntil == 1 )
 
-BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
-                                const TickType_t xTimeIncrement ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
+                                        const TickType_t xTimeIncrement ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
-                                const TickType_t xTimeIncrement ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskDelayUntilImpl                       \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTaskDelayUntil_Unpriv                        \n"
-        " MPU_xTaskDelayUntil_Priv:                             \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTaskDelayUntilImpl                         \n"
-        " MPU_xTaskDelayUntil_Unpriv:                           \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskDelayUntilImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
+                                        const TickType_t xTimeIncrement ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskDelayUntilImpl                       \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xTaskDelayUntil_Unpriv                        \n"
+                " MPU_xTaskDelayUntil_Priv:                             \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xTaskDelayUntilImpl                         \n"
+                " MPU_xTaskDelayUntil_Unpriv:                           \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskDelayUntilImpl                        \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */
+    #endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_xTaskAbortDelay == 1 )
+    #if ( INCLUDE_xTaskAbortDelay == 1 )
 
-BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskAbortDelayImpl                       \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTaskAbortDelay_Unpriv                        \n"
-        " MPU_xTaskAbortDelay_Priv:                             \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTaskAbortDelayImpl                         \n"
-        " MPU_xTaskAbortDelay_Unpriv:                           \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskAbortDelayImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskAbortDelayImpl                       \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xTaskAbortDelay_Unpriv                        \n"
+                " MPU_xTaskAbortDelay_Priv:                             \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xTaskAbortDelayImpl                         \n"
+                " MPU_xTaskAbortDelay_Unpriv:                           \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskAbortDelayImpl                        \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */
+    #endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_vTaskDelay == 1 )
+    #if ( INCLUDE_vTaskDelay == 1 )
 
-void MPU_vTaskDelay( const TickType_t xTicksToDelay ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskDelay( const TickType_t xTicksToDelay ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskDelayImpl                            \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_vTaskDelay_Unpriv                             \n"
-        " MPU_vTaskDelay_Priv:                                  \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_vTaskDelayImpl                              \n"
-        " MPU_vTaskDelay_Unpriv:                                \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskDelayImpl                             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskDelayImpl                            \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_vTaskDelay_Unpriv                             \n"
+                " MPU_vTaskDelay_Priv:                                  \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_vTaskDelayImpl                              \n"
+                " MPU_vTaskDelay_Unpriv:                                \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskDelayImpl                             \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_vTaskDelay == 1 ) */
+    #endif /* if ( INCLUDE_vTaskDelay == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_uxTaskPriorityGet == 1 )
+    #if ( INCLUDE_uxTaskPriorityGet == 1 )
 
-UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskPriorityGetImpl                     \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_uxTaskPriorityGet_Unpriv                      \n"
-        " MPU_uxTaskPriorityGet_Priv:                           \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_uxTaskPriorityGetImpl                       \n"
-        " MPU_uxTaskPriorityGet_Unpriv:                         \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskPriorityGetImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskPriorityGetImpl                     \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_uxTaskPriorityGet_Unpriv                      \n"
+                " MPU_uxTaskPriorityGet_Priv:                           \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_uxTaskPriorityGetImpl                       \n"
+                " MPU_uxTaskPriorityGet_Unpriv:                         \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskPriorityGetImpl                      \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */
+    #endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_eTaskGetState == 1 )
+    #if ( INCLUDE_eTaskGetState == 1 )
 
-eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_eTaskGetStateImpl                         \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_eTaskGetState_Unpriv                          \n"
-        " MPU_eTaskGetState_Priv:                               \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_eTaskGetStateImpl                           \n"
-        " MPU_eTaskGetState_Unpriv:                             \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_eTaskGetStateImpl                          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_eTaskGetStateImpl                         \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_eTaskGetState_Unpriv                          \n"
+                " MPU_eTaskGetState_Priv:                               \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_eTaskGetStateImpl                           \n"
+                " MPU_eTaskGetState_Unpriv:                             \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_eTaskGetStateImpl                          \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_eTaskGetState == 1 ) */
+    #endif /* if ( INCLUDE_eTaskGetState == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-void MPU_vTaskGetInfo( TaskHandle_t xTask,
-                       TaskStatus_t * pxTaskStatus,
-                       BaseType_t xGetFreeStackSpace,
-                       eTaskState eState ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskGetInfo( TaskHandle_t xTask,
+                               TaskStatus_t * pxTaskStatus,
+                               BaseType_t xGetFreeStackSpace,
+                               eTaskState eState ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskGetInfo( TaskHandle_t xTask,
-                       TaskStatus_t * pxTaskStatus,
-                       BaseType_t xGetFreeStackSpace,
-                       eTaskState eState ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskGetInfoImpl                          \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_vTaskGetInfo_Unpriv                           \n"
-        " MPU_vTaskGetInfo_Priv:                                \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_vTaskGetInfoImpl                            \n"
-        " MPU_vTaskGetInfo_Unpriv:                              \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskGetInfoImpl                           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskGetInfo( TaskHandle_t xTask,
+                               TaskStatus_t * pxTaskStatus,
+                               BaseType_t xGetFreeStackSpace,
+                               eTaskState eState ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskGetInfoImpl                          \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_vTaskGetInfo_Unpriv                           \n"
+                " MPU_vTaskGetInfo_Priv:                                \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_vTaskGetInfoImpl                            \n"
+                " MPU_vTaskGetInfo_Unpriv:                              \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskGetInfoImpl                           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
+    #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
+    #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
 
-TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetIdleTaskHandleImpl                \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTaskGetIdleTaskHandle_Unpriv                 \n"
-        " MPU_xTaskGetIdleTaskHandle_Priv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTaskGetIdleTaskHandleImpl                  \n"
-        " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetIdleTaskHandleImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetIdleTaskHandleImpl                \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xTaskGetIdleTaskHandle_Unpriv                 \n"
+                " MPU_xTaskGetIdleTaskHandle_Priv:                      \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xTaskGetIdleTaskHandleImpl                  \n"
+                " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetIdleTaskHandleImpl                 \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */
+    #endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_vTaskSuspend == 1 )
+    #if ( INCLUDE_vTaskSuspend == 1 )
 
-void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSuspendImpl                          \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_vTaskSuspend_Unpriv                           \n"
-        " MPU_vTaskSuspend_Priv:                                \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_vTaskSuspendImpl                            \n"
-        " MPU_vTaskSuspend_Unpriv:                              \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSuspendImpl                           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskSuspendImpl                          \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_vTaskSuspend_Unpriv                           \n"
+                " MPU_vTaskSuspend_Priv:                                \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_vTaskSuspendImpl                            \n"
+                " MPU_vTaskSuspend_Unpriv:                              \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskSuspendImpl                           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
+    #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_vTaskSuspend == 1 )
+    #if ( INCLUDE_vTaskSuspend == 1 )
 
-void MPU_vTaskResume( TaskHandle_t xTaskToResume ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskResume( TaskHandle_t xTaskToResume ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskResumeImpl                           \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_vTaskResume_Unpriv                            \n"
-        " MPU_vTaskResume_Priv:                                 \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_vTaskResumeImpl                             \n"
-        " MPU_vTaskResume_Unpriv:                               \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskResumeImpl                            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskResumeImpl                           \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_vTaskResume_Unpriv                            \n"
+                " MPU_vTaskResume_Priv:                                 \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_vTaskResumeImpl                             \n"
+                " MPU_vTaskResume_Unpriv:                               \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskResumeImpl                            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
+    #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
 /*-----------------------------------------------------------*/
 
-TickType_t MPU_xTaskGetTickCount( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    TickType_t MPU_xTaskGetTickCount( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TickType_t MPU_xTaskGetTickCount( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetTickCountImpl                     \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTaskGetTickCount_Unpriv                      \n"
-        " MPU_xTaskGetTickCount_Priv:                           \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTaskGetTickCountImpl                       \n"
-        " MPU_xTaskGetTickCount_Unpriv:                         \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetTickCountImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    TickType_t MPU_xTaskGetTickCount( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xTaskGetTickCountImpl                     \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xTaskGetTickCount_Unpriv                      \n"
+            " MPU_xTaskGetTickCount_Priv:                           \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xTaskGetTickCountImpl                       \n"
+            " MPU_xTaskGetTickCount_Unpriv:                         \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xTaskGetTickCountImpl                      \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetNumberOfTasksImpl                \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_uxTaskGetNumberOfTasks_Unpriv                 \n"
-        " MPU_uxTaskGetNumberOfTasks_Priv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_uxTaskGetNumberOfTasksImpl                  \n"
-        " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetNumberOfTasksImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_uxTaskGetNumberOfTasksImpl                \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_uxTaskGetNumberOfTasks_Unpriv                 \n"
+            " MPU_uxTaskGetNumberOfTasks_Priv:                      \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_uxTaskGetNumberOfTasksImpl                  \n"
+            " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_uxTaskGetNumberOfTasksImpl                 \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configGENERATE_RUN_TIME_STATS == 1 )
+    #if ( configGENERATE_RUN_TIME_STATS == 1 )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetRunTimeCounterImpl               \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_ulTaskGetRunTimeCounter_Unpriv                \n"
-        " MPU_ulTaskGetRunTimeCounter_Priv:                     \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_ulTaskGetRunTimeCounterImpl                 \n"
-        " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetRunTimeCounterImpl                \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetRunTimeCounterImpl               \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_ulTaskGetRunTimeCounter_Unpriv                \n"
+                " MPU_ulTaskGetRunTimeCounter_Priv:                     \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_ulTaskGetRunTimeCounterImpl                 \n"
+                " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetRunTimeCounterImpl                \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configGENERATE_RUN_TIME_STATS == 1 )
+    #if ( configGENERATE_RUN_TIME_STATS == 1 )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetRunTimePercentImpl               \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_ulTaskGetRunTimePercent_Unpriv                \n"
-        " MPU_ulTaskGetRunTimePercent_Priv:                     \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_ulTaskGetRunTimePercentImpl                 \n"
-        " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetRunTimePercentImpl                \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetRunTimePercentImpl               \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_ulTaskGetRunTimePercent_Unpriv                \n"
+                " MPU_ulTaskGetRunTimePercent_Priv:                     \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_ulTaskGetRunTimePercentImpl                 \n"
+                " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetRunTimePercentImpl                \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+    #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetIdleRunTimePercentImpl           \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv            \n"
-        " MPU_ulTaskGetIdleRunTimePercent_Priv:                 \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_ulTaskGetIdleRunTimePercentImpl             \n"
-        " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetIdleRunTimePercentImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetIdleRunTimePercentImpl           \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv            \n"
+                " MPU_ulTaskGetIdleRunTimePercent_Priv:                 \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_ulTaskGetIdleRunTimePercentImpl             \n"
+                " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetIdleRunTimePercentImpl            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+    #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetIdleRunTimeCounterImpl           \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv            \n"
-        " MPU_ulTaskGetIdleRunTimeCounter_Priv:                 \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_ulTaskGetIdleRunTimeCounterImpl             \n"
-        " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetIdleRunTimeCounterImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetIdleRunTimeCounterImpl           \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv            \n"
+                " MPU_ulTaskGetIdleRunTimeCounter_Priv:                 \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_ulTaskGetIdleRunTimeCounterImpl             \n"
+                " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetIdleRunTimeCounterImpl            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+    #if ( configUSE_APPLICATION_TASK_TAG == 1 )
 
-void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
-                                     TaskHookFunction_t pxHookFunction ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
+                                             TaskHookFunction_t pxHookFunction ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
-                                     TaskHookFunction_t pxHookFunction ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSetApplicationTaskTagImpl            \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_vTaskSetApplicationTaskTag_Unpriv             \n"
-        " MPU_vTaskSetApplicationTaskTag_Priv:                  \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_vTaskSetApplicationTaskTagImpl              \n"
-        " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSetApplicationTaskTagImpl             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
+                                             TaskHookFunction_t pxHookFunction ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskSetApplicationTaskTagImpl            \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_vTaskSetApplicationTaskTag_Unpriv             \n"
+                " MPU_vTaskSetApplicationTaskTag_Priv:                  \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_vTaskSetApplicationTaskTagImpl              \n"
+                " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskSetApplicationTaskTagImpl             \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
+    #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+    #if ( configUSE_APPLICATION_TASK_TAG == 1 )
 
-TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetApplicationTaskTagImpl            \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTaskGetApplicationTaskTag_Unpriv             \n"
-        " MPU_xTaskGetApplicationTaskTag_Priv:                  \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTaskGetApplicationTaskTagImpl              \n"
-        " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetApplicationTaskTagImpl             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetApplicationTaskTagImpl            \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xTaskGetApplicationTaskTag_Unpriv             \n"
+                " MPU_xTaskGetApplicationTaskTag_Priv:                  \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xTaskGetApplicationTaskTagImpl              \n"
+                " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetApplicationTaskTagImpl             \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
+    #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+    #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
 
-void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
-                                            BaseType_t xIndex,
-                                            void * pvValue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
+                                                    BaseType_t xIndex,
+                                                    void * pvValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
-                                            BaseType_t xIndex,
-                                            void * pvValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSetThreadLocalStoragePointerImpl     \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv      \n"
-        " MPU_vTaskSetThreadLocalStoragePointer_Priv:           \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_vTaskSetThreadLocalStoragePointerImpl       \n"
-        " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSetThreadLocalStoragePointerImpl      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
+                                                    BaseType_t xIndex,
+                                                    void * pvValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskSetThreadLocalStoragePointerImpl     \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv      \n"
+                " MPU_vTaskSetThreadLocalStoragePointer_Priv:           \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_vTaskSetThreadLocalStoragePointerImpl       \n"
+                " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskSetThreadLocalStoragePointerImpl      \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
+    #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+    #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
 
-void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
-                                               BaseType_t xIndex ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
+                                                       BaseType_t xIndex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
-                                               BaseType_t xIndex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pvTaskGetThreadLocalStoragePointerImpl    \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv     \n"
-        " MPU_pvTaskGetThreadLocalStoragePointer_Priv:          \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_pvTaskGetThreadLocalStoragePointerImpl      \n"
-        " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pvTaskGetThreadLocalStoragePointerImpl     \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
+                                                       BaseType_t xIndex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pvTaskGetThreadLocalStoragePointerImpl    \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv     \n"
+                " MPU_pvTaskGetThreadLocalStoragePointer_Priv:          \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_pvTaskGetThreadLocalStoragePointerImpl      \n"
+                " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pvTaskGetThreadLocalStoragePointerImpl     \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
+    #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
-                                      const UBaseType_t uxArraySize,
-                                      configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
+                                              const UBaseType_t uxArraySize,
+                                              configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
-                                      const UBaseType_t uxArraySize,
-                                      configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetSystemStateImpl                  \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_uxTaskGetSystemState_Unpriv                   \n"
-        " MPU_uxTaskGetSystemState_Priv:                        \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_uxTaskGetSystemStateImpl                    \n"
-        " MPU_uxTaskGetSystemState_Unpriv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetSystemStateImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
+                                              const UBaseType_t uxArraySize,
+                                              configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskGetSystemStateImpl                  \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_uxTaskGetSystemState_Unpriv                   \n"
+                " MPU_uxTaskGetSystemState_Priv:                        \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_uxTaskGetSystemStateImpl                    \n"
+                " MPU_uxTaskGetSystemState_Unpriv:                      \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskGetSystemStateImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
+    #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
+    #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
 
-UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetStackHighWaterMarkImpl           \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_uxTaskGetStackHighWaterMark_Unpriv            \n"
-        " MPU_uxTaskGetStackHighWaterMark_Priv:                 \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_uxTaskGetStackHighWaterMarkImpl             \n"
-        " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetStackHighWaterMarkImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskGetStackHighWaterMarkImpl           \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_uxTaskGetStackHighWaterMark_Unpriv            \n"
+                " MPU_uxTaskGetStackHighWaterMark_Priv:                 \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_uxTaskGetStackHighWaterMarkImpl             \n"
+                " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskGetStackHighWaterMarkImpl            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */
+    #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
+    #if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
 
-configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetStackHighWaterMark2Impl          \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv           \n"
-        " MPU_uxTaskGetStackHighWaterMark2_Priv:                \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_uxTaskGetStackHighWaterMark2Impl            \n"
-        " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetStackHighWaterMark2Impl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskGetStackHighWaterMark2Impl          \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv           \n"
+                " MPU_uxTaskGetStackHighWaterMark2_Priv:                \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_uxTaskGetStackHighWaterMark2Impl            \n"
+                " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskGetStackHighWaterMark2Impl           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */
+    #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
+    #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
 
-TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetCurrentTaskHandleImpl             \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTaskGetCurrentTaskHandle_Unpriv              \n"
-        " MPU_xTaskGetCurrentTaskHandle_Priv:                   \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTaskGetCurrentTaskHandleImpl               \n"
-        " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetCurrentTaskHandleImpl              \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetCurrentTaskHandleImpl             \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xTaskGetCurrentTaskHandle_Unpriv              \n"
+                " MPU_xTaskGetCurrentTaskHandle_Priv:                   \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xTaskGetCurrentTaskHandleImpl               \n"
+                " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetCurrentTaskHandleImpl              \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
+    #endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_xTaskGetSchedulerState == 1 )
+    #if ( INCLUDE_xTaskGetSchedulerState == 1 )
 
-BaseType_t MPU_xTaskGetSchedulerState( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGetSchedulerState( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGetSchedulerState( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetSchedulerStateImpl                \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTaskGetSchedulerState_Unpriv                 \n"
-        " MPU_xTaskGetSchedulerState_Priv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTaskGetSchedulerStateImpl                  \n"
-        " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetSchedulerStateImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGetSchedulerState( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetSchedulerStateImpl                \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xTaskGetSchedulerState_Unpriv                 \n"
+                " MPU_xTaskGetSchedulerState_Priv:                      \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xTaskGetSchedulerStateImpl                  \n"
+                " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetSchedulerStateImpl                 \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */
+    #endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */
 /*-----------------------------------------------------------*/
 
-void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSetTimeOutStateImpl                  \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_vTaskSetTimeOutState_Unpriv                   \n"
-        " MPU_vTaskSetTimeOutState_Priv:                        \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_vTaskSetTimeOutStateImpl                    \n"
-        " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSetTimeOutStateImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_vTaskSetTimeOutStateImpl                  \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_vTaskSetTimeOutState_Unpriv                   \n"
+            " MPU_vTaskSetTimeOutState_Priv:                        \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_vTaskSetTimeOutStateImpl                    \n"
+            " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_vTaskSetTimeOutStateImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
-                                     TickType_t * const pxTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
+                                         TickType_t * const pxTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
-                                     TickType_t * const pxTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskCheckForTimeOutImpl                  \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTaskCheckForTimeOut_Unpriv                   \n"
-        " MPU_xTaskCheckForTimeOut_Priv:                        \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTaskCheckForTimeOutImpl                    \n"
-        " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskCheckForTimeOutImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
+                                         TickType_t * const pxTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xTaskCheckForTimeOutImpl                  \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xTaskCheckForTimeOut_Unpriv                   \n"
+            " MPU_xTaskCheckForTimeOut_Priv:                        \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xTaskCheckForTimeOutImpl                    \n"
+            " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xTaskCheckForTimeOutImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                   UBaseType_t uxIndexToNotify,
-                                   uint32_t ulValue,
-                                   eNotifyAction eAction,
-                                   uint32_t * pulPreviousNotificationValue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
+                                           UBaseType_t uxIndexToNotify,
+                                           uint32_t ulValue,
+                                           eNotifyAction eAction,
+                                           uint32_t * pulPreviousNotificationValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                   UBaseType_t uxIndexToNotify,
-                                   uint32_t ulValue,
-                                   eNotifyAction eAction,
-                                   uint32_t * pulPreviousNotificationValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGenericNotifyImpl                    \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTaskGenericNotify_Unpriv                     \n"
-        " MPU_xTaskGenericNotify_Priv:                          \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTaskGenericNotifyImpl                      \n"
-        " MPU_xTaskGenericNotify_Unpriv:                        \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGenericNotifyImpl                     \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
+                                           UBaseType_t uxIndexToNotify,
+                                           uint32_t ulValue,
+                                           eNotifyAction eAction,
+                                           uint32_t * pulPreviousNotificationValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGenericNotifyImpl                    \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xTaskGenericNotify_Unpriv                     \n"
+                " MPU_xTaskGenericNotify_Priv:                          \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xTaskGenericNotifyImpl                      \n"
+                " MPU_xTaskGenericNotify_Unpriv:                        \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGenericNotifyImpl                     \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                       uint32_t ulBitsToClearOnEntry,
-                                       uint32_t ulBitsToClearOnExit,
-                                       uint32_t * pulNotificationValue,
-                                       TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
+                                               uint32_t ulBitsToClearOnEntry,
+                                               uint32_t ulBitsToClearOnExit,
+                                               uint32_t * pulNotificationValue,
+                                               TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                       uint32_t ulBitsToClearOnEntry,
-                                       uint32_t ulBitsToClearOnExit,
-                                       uint32_t * pulNotificationValue,
-                                       TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGenericNotifyWaitImpl                \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTaskGenericNotifyWait_Unpriv                 \n"
-        " MPU_xTaskGenericNotifyWait_Priv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTaskGenericNotifyWaitImpl                  \n"
-        " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGenericNotifyWaitImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
+                                               uint32_t ulBitsToClearOnEntry,
+                                               uint32_t ulBitsToClearOnExit,
+                                               uint32_t * pulNotificationValue,
+                                               TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGenericNotifyWaitImpl                \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xTaskGenericNotifyWait_Unpriv                 \n"
+                " MPU_xTaskGenericNotifyWait_Priv:                      \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xTaskGenericNotifyWaitImpl                  \n"
+                " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGenericNotifyWaitImpl                 \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
-                                      BaseType_t xClearCountOnExit,
-                                      TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
+                                              BaseType_t xClearCountOnExit,
+                                              TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
-                                      BaseType_t xClearCountOnExit,
-                                      TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGenericNotifyTakeImpl               \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_ulTaskGenericNotifyTake_Unpriv                \n"
-        " MPU_ulTaskGenericNotifyTake_Priv:                     \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_ulTaskGenericNotifyTakeImpl                 \n"
-        " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGenericNotifyTakeImpl                \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
+                                              BaseType_t xClearCountOnExit,
+                                              TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGenericNotifyTakeImpl               \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_ulTaskGenericNotifyTake_Unpriv                \n"
+                " MPU_ulTaskGenericNotifyTake_Priv:                     \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_ulTaskGenericNotifyTakeImpl                 \n"
+                " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGenericNotifyTakeImpl                \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
-                                             UBaseType_t uxIndexToClear ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
+                                                     UBaseType_t uxIndexToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
-                                             UBaseType_t uxIndexToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGenericNotifyStateClearImpl          \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTaskGenericNotifyStateClear_Unpriv           \n"
-        " MPU_xTaskGenericNotifyStateClear_Priv:                \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTaskGenericNotifyStateClearImpl            \n"
-        " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGenericNotifyStateClearImpl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
+                                                     UBaseType_t uxIndexToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGenericNotifyStateClearImpl          \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xTaskGenericNotifyStateClear_Unpriv           \n"
+                " MPU_xTaskGenericNotifyStateClear_Priv:                \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xTaskGenericNotifyStateClearImpl            \n"
+                " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGenericNotifyStateClearImpl           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
-                                            UBaseType_t uxIndexToClear,
-                                            uint32_t ulBitsToClear ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
+                                                    UBaseType_t uxIndexToClear,
+                                                    uint32_t ulBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
-                                            UBaseType_t uxIndexToClear,
-                                            uint32_t ulBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGenericNotifyValueClearImpl         \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_ulTaskGenericNotifyValueClear_Unpriv          \n"
-        " MPU_ulTaskGenericNotifyValueClear_Priv:               \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_ulTaskGenericNotifyValueClearImpl           \n"
-        " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGenericNotifyValueClearImpl          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
+                                                    UBaseType_t uxIndexToClear,
+                                                    uint32_t ulBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGenericNotifyValueClearImpl         \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_ulTaskGenericNotifyValueClear_Unpriv          \n"
+                " MPU_ulTaskGenericNotifyValueClear_Priv:               \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_ulTaskGenericNotifyValueClearImpl           \n"
+                " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGenericNotifyValueClearImpl          \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
-                                  const void * const pvItemToQueue,
-                                  TickType_t xTicksToWait,
-                                  const BaseType_t xCopyPosition ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
+                                      const void * const pvItemToQueue,
+                                      TickType_t xTicksToWait,
+                                      const BaseType_t xCopyPosition ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
-                                  const void * const pvItemToQueue,
-                                  TickType_t xTicksToWait,
-                                  const BaseType_t xCopyPosition ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueGenericSendImpl                     \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xQueueGenericSend_Unpriv                      \n"
-        " MPU_xQueueGenericSend_Priv:                           \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xQueueGenericSendImpl                       \n"
-        " MPU_xQueueGenericSend_Unpriv:                         \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueGenericSendImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
+                                      const void * const pvItemToQueue,
+                                      TickType_t xTicksToWait,
+                                      const BaseType_t xCopyPosition ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueueGenericSendImpl                     \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xQueueGenericSend_Unpriv                      \n"
+            " MPU_xQueueGenericSend_Priv:                           \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xQueueGenericSendImpl                       \n"
+            " MPU_xQueueGenericSend_Unpriv:                         \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueueGenericSendImpl                      \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxQueueMessagesWaitingImpl                \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_uxQueueMessagesWaiting_Unpriv                 \n"
-        " MPU_uxQueueMessagesWaiting_Priv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_uxQueueMessagesWaitingImpl                  \n"
-        " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxQueueMessagesWaitingImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_uxQueueMessagesWaitingImpl                \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_uxQueueMessagesWaiting_Unpriv                 \n"
+            " MPU_uxQueueMessagesWaiting_Priv:                      \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_uxQueueMessagesWaitingImpl                  \n"
+            " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_uxQueueMessagesWaitingImpl                 \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxQueueSpacesAvailableImpl                \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_uxQueueSpacesAvailable_Unpriv                 \n"
-        " MPU_uxQueueSpacesAvailable_Priv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_uxQueueSpacesAvailableImpl                  \n"
-        " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxQueueSpacesAvailableImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_uxQueueSpacesAvailableImpl                \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_uxQueueSpacesAvailable_Unpriv                 \n"
+            " MPU_uxQueueSpacesAvailable_Priv:                      \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_uxQueueSpacesAvailableImpl                  \n"
+            " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_uxQueueSpacesAvailableImpl                 \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
-                              void * const pvBuffer,
-                              TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
+                                  void * const pvBuffer,
+                                  TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
-                              void * const pvBuffer,
-                              TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueReceiveImpl                         \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xQueueReceive_Unpriv                          \n"
-        " MPU_xQueueReceive_Priv:                               \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xQueueReceiveImpl                           \n"
-        " MPU_xQueueReceive_Unpriv:                             \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueReceiveImpl                          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
+                                  void * const pvBuffer,
+                                  TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueueReceiveImpl                         \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xQueueReceive_Unpriv                          \n"
+            " MPU_xQueueReceive_Priv:                               \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xQueueReceiveImpl                           \n"
+            " MPU_xQueueReceive_Unpriv:                             \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueueReceiveImpl                          \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
-                           void * const pvBuffer,
-                           TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
+                               void * const pvBuffer,
+                               TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
-                           void * const pvBuffer,
-                           TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueuePeekImpl                            \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xQueuePeek_Unpriv                             \n"
-        " MPU_xQueuePeek_Priv:                                  \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xQueuePeekImpl                              \n"
-        " MPU_xQueuePeek_Unpriv:                                \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueuePeekImpl                             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
+                               void * const pvBuffer,
+                               TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueuePeekImpl                            \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xQueuePeek_Unpriv                             \n"
+            " MPU_xQueuePeek_Priv:                                  \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xQueuePeekImpl                              \n"
+            " MPU_xQueuePeek_Unpriv:                                \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueuePeekImpl                             \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
-                                    TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
+                                        TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
-                                    TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueSemaphoreTakeImpl                   \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xQueueSemaphoreTake_Unpriv                    \n"
-        " MPU_xQueueSemaphoreTake_Priv:                         \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xQueueSemaphoreTakeImpl                     \n"
-        " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueSemaphoreTakeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
+                                        TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueueSemaphoreTakeImpl                   \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xQueueSemaphoreTake_Unpriv                    \n"
+            " MPU_xQueueSemaphoreTake_Priv:                         \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xQueueSemaphoreTakeImpl                     \n"
+            " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueueSemaphoreTakeImpl                    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+    #if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
 
-TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueGetMutexHolderImpl                  \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xQueueGetMutexHolder_Unpriv                   \n"
-        " MPU_xQueueGetMutexHolder_Priv:                        \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xQueueGetMutexHolderImpl                    \n"
-        " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueGetMutexHolderImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueGetMutexHolderImpl                  \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xQueueGetMutexHolder_Unpriv                   \n"
+                " MPU_xQueueGetMutexHolder_Priv:                        \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xQueueGetMutexHolderImpl                    \n"
+                " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueGetMutexHolderImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */
+    #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+    #if ( configUSE_RECURSIVE_MUTEXES == 1 )
 
-BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
-                                         TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+                                                 TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+        BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+                                                 TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueTakeMutexRecursiveImpl              \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xQueueTakeMutexRecursive_Unpriv               \n"
+                " MPU_xQueueTakeMutexRecursive_Priv:                    \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xQueueTakeMutexRecursiveImpl                \n"
+                " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueTakeMutexRecursiveImpl               \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_RECURSIVE_MUTEXES == 1 )
+
+        BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueGiveMutexRecursiveImpl              \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xQueueGiveMutexRecursive_Unpriv               \n"
+                " MPU_xQueueGiveMutexRecursive_Priv:                    \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xQueueGiveMutexRecursiveImpl                \n"
+                " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueGiveMutexRecursiveImpl               \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_QUEUE_SETS == 1 )
+
+        QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
+                                                        const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
+                                                        const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueSelectFromSetImpl                   \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xQueueSelectFromSet_Unpriv                    \n"
+                " MPU_xQueueSelectFromSet_Priv:                         \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xQueueSelectFromSetImpl                     \n"
+                " MPU_xQueueSelectFromSet_Unpriv:                       \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueSelectFromSetImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_QUEUE_SETS == 1 )
+
+        BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                                       QueueSetHandle_t xQueueSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                                       QueueSetHandle_t xQueueSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueAddToSetImpl                        \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xQueueAddToSet_Unpriv                         \n"
+                " MPU_xQueueAddToSet_Priv:                              \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xQueueAddToSetImpl                          \n"
+                " MPU_xQueueAddToSet_Unpriv:                            \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueAddToSetImpl                         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+        void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
+                                      const char * pcName ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
+                                      const char * pcName ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vQueueAddToRegistryImpl                   \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_vQueueAddToRegistry_Unpriv                    \n"
+                " MPU_vQueueAddToRegistry_Priv:                         \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_vQueueAddToRegistryImpl                     \n"
+                " MPU_vQueueAddToRegistry_Unpriv:                       \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vQueueAddToRegistryImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+        void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vQueueUnregisterQueueImpl                 \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_vQueueUnregisterQueue_Unpriv                  \n"
+                " MPU_vQueueUnregisterQueue_Priv:                       \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_vQueueUnregisterQueueImpl                   \n"
+                " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vQueueUnregisterQueueImpl                  \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+        const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pcQueueGetNameImpl                        \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_pcQueueGetName_Unpriv                         \n"
+                " MPU_pcQueueGetName_Priv:                              \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_pcQueueGetNameImpl                          \n"
+                " MPU_pcQueueGetName_Unpriv:                            \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pcQueueGetNameImpl                         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pvTimerGetTimerIDImpl                     \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_pvTimerGetTimerID_Unpriv                      \n"
+                " MPU_pvTimerGetTimerID_Priv:                           \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_pvTimerGetTimerIDImpl                       \n"
+                " MPU_pvTimerGetTimerID_Unpriv:                         \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pvTimerGetTimerIDImpl                      \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
+                                   void * pvNewID ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
+                                   void * pvNewID ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTimerSetTimerIDImpl                      \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_vTimerSetTimerID_Unpriv                       \n"
+                " MPU_vTimerSetTimerID_Priv:                            \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_vTimerSetTimerIDImpl                        \n"
+                " MPU_vTimerSetTimerID_Unpriv:                          \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTimerSetTimerIDImpl                       \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerIsTimerActiveImpl                   \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xTimerIsTimerActive_Unpriv                    \n"
+                " MPU_xTimerIsTimerActive_Priv:                         \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xTimerIsTimerActiveImpl                     \n"
+                " MPU_xTimerIsTimerActive_Unpriv:                       \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerIsTimerActiveImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetTimerDaemonTaskHandleImpl        \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv         \n"
+                " MPU_xTimerGetTimerDaemonTaskHandle_Priv:              \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xTimerGetTimerDaemonTaskHandleImpl          \n"
+                " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetTimerDaemonTaskHandleImpl         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                                     const BaseType_t xCommandID,
+                                                     const TickType_t xOptionalValue,
+                                                     BaseType_t * const pxHigherPriorityTaskWoken,
+                                                     const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                                     const BaseType_t xCommandID,
+                                                     const TickType_t xOptionalValue,
+                                                     BaseType_t * const pxHigherPriorityTaskWoken,
+                                                     const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                               \n"
+                " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
+                "                                                               \n"
+                " push {r0, r1}                                                 \n"
+                " mrs r0, control                                               \n"
+                " movs r1, #1                                                   \n"
+                " tst r0, r1                                                    \n"
+                " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
+                " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
+                "     pop {r0, r1}                                              \n"
+                "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
+                " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
+                "     pop {r0, r1}                                              \n"
+                "     svc %0                                                    \n"
+                "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
+                "     svc %1                                                    \n"
+                "     bx lr                                                     \n"
+                "                                                               \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pcTimerGetNameImpl                        \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_pcTimerGetName_Unpriv                         \n"
+                " MPU_pcTimerGetName_Priv:                              \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_pcTimerGetNameImpl                          \n"
+                " MPU_pcTimerGetName_Unpriv:                            \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pcTimerGetNameImpl                         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
+                                      const BaseType_t uxAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
+                                      const BaseType_t uxAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTimerSetReloadModeImpl                   \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_vTimerSetReloadMode_Unpriv                    \n"
+                " MPU_vTimerSetReloadMode_Priv:                         \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_vTimerSetReloadModeImpl                     \n"
+                " MPU_vTimerSetReloadMode_Unpriv:                       \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTimerSetReloadModeImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetReloadModeImpl                   \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xTimerGetReloadMode_Unpriv                    \n"
+                " MPU_xTimerGetReloadMode_Priv:                         \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xTimerGetReloadModeImpl                     \n"
+                " MPU_xTimerGetReloadMode_Unpriv:                       \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetReloadModeImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTimerGetReloadModeImpl                  \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_uxTimerGetReloadMode_Unpriv                   \n"
+                " MPU_uxTimerGetReloadMode_Priv:                        \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_uxTimerGetReloadModeImpl                    \n"
+                " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTimerGetReloadModeImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetPeriodImpl                       \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xTimerGetPeriod_Unpriv                        \n"
+                " MPU_xTimerGetPeriod_Priv:                             \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xTimerGetPeriodImpl                         \n"
+                " MPU_xTimerGetPeriod_Unpriv:                           \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetPeriodImpl                        \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetExpiryTimeImpl                   \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_xTimerGetExpiryTime_Unpriv                    \n"
+                " MPU_xTimerGetExpiryTime_Priv:                         \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_xTimerGetExpiryTimeImpl                     \n"
+                " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetExpiryTimeImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         const BaseType_t xClearOnExit,
+                                         const BaseType_t xWaitForAllBits,
+                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         const BaseType_t xClearOnExit,
+                                         const BaseType_t xWaitForAllBits,
                                          TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueTakeMutexRecursiveImpl              \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xQueueTakeMutexRecursive_Unpriv               \n"
-        " MPU_xQueueTakeMutexRecursive_Priv:                    \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xQueueTakeMutexRecursiveImpl                \n"
-        " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueTakeMutexRecursiveImpl               \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupWaitBitsImpl                   \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
+            " MPU_xEventGroupWaitBits_Priv:                         \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xEventGroupWaitBitsImpl                     \n"
+            " MPU_xEventGroupWaitBits_Unpriv:                       \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupWaitBitsImpl                    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                          const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueGiveMutexRecursiveImpl              \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xQueueGiveMutexRecursive_Unpriv               \n"
-        " MPU_xQueueGiveMutexRecursive_Priv:                    \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xQueueGiveMutexRecursiveImpl                \n"
-        " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueGiveMutexRecursiveImpl               \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                          const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupClearBitsImpl                  \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xEventGroupClearBits_Unpriv                   \n"
+            " MPU_xEventGroupClearBits_Priv:                        \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xEventGroupClearBitsImpl                    \n"
+            " MPU_xEventGroupClearBits_Unpriv:                      \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupClearBitsImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_QUEUE_SETS == 1 )
+    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                        const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
-                                                const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
-                                                const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueSelectFromSetImpl                   \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xQueueSelectFromSet_Unpriv                    \n"
-        " MPU_xQueueSelectFromSet_Priv:                         \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xQueueSelectFromSetImpl                     \n"
-        " MPU_xQueueSelectFromSet_Unpriv:                       \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueSelectFromSetImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                        const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupSetBitsImpl                    \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xEventGroupSetBits_Unpriv                     \n"
+            " MPU_xEventGroupSetBits_Priv:                          \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xEventGroupSetBitsImpl                      \n"
+            " MPU_xEventGroupSetBits_Unpriv:                        \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupSetBitsImpl                     \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_QUEUE_SETS == 1 )
-
-BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
-                               QueueSetHandle_t xQueueSet ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
-                               QueueSetHandle_t xQueueSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueAddToSetImpl                        \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xQueueAddToSet_Unpriv                         \n"
-        " MPU_xQueueAddToSet_Priv:                              \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xQueueAddToSetImpl                          \n"
-        " MPU_xQueueAddToSet_Unpriv:                            \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueAddToSetImpl                         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_QUEUE_SETS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
-                              const char * pcName ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
-                              const char * pcName ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vQueueAddToRegistryImpl                   \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_vQueueAddToRegistry_Unpriv                    \n"
-        " MPU_vQueueAddToRegistry_Priv:                         \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_vQueueAddToRegistryImpl                     \n"
-        " MPU_vQueueAddToRegistry_Unpriv:                       \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vQueueAddToRegistryImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vQueueUnregisterQueueImpl                 \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_vQueueUnregisterQueue_Unpriv                  \n"
-        " MPU_vQueueUnregisterQueue_Priv:                       \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_vQueueUnregisterQueueImpl                   \n"
-        " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vQueueUnregisterQueueImpl                  \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pcQueueGetNameImpl                        \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_pcQueueGetName_Unpriv                         \n"
-        " MPU_pcQueueGetName_Priv:                              \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_pcQueueGetNameImpl                          \n"
-        " MPU_pcQueueGetName_Unpriv:                            \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pcQueueGetNameImpl                         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pvTimerGetTimerIDImpl                     \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_pvTimerGetTimerID_Unpriv                      \n"
-        " MPU_pvTimerGetTimerID_Priv:                           \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_pvTimerGetTimerIDImpl                       \n"
-        " MPU_pvTimerGetTimerID_Unpriv:                         \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pvTimerGetTimerIDImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
-                           void * pvNewID ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
-                           void * pvNewID ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTimerSetTimerIDImpl                      \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_vTimerSetTimerID_Unpriv                       \n"
-        " MPU_vTimerSetTimerID_Priv:                            \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_vTimerSetTimerIDImpl                        \n"
-        " MPU_vTimerSetTimerID_Unpriv:                          \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTimerSetTimerIDImpl                       \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerIsTimerActiveImpl                   \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTimerIsTimerActive_Unpriv                    \n"
-        " MPU_xTimerIsTimerActive_Priv:                         \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTimerIsTimerActiveImpl                     \n"
-        " MPU_xTimerIsTimerActive_Unpriv:                       \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerIsTimerActiveImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetTimerDaemonTaskHandleImpl        \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv         \n"
-        " MPU_xTimerGetTimerDaemonTaskHandle_Priv:              \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTimerGetTimerDaemonTaskHandleImpl          \n"
-        " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetTimerDaemonTaskHandleImpl         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                             const BaseType_t xCommandID,
-                                             const TickType_t xOptionalValue,
-                                             BaseType_t * const pxHigherPriorityTaskWoken,
-                                             const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                             const BaseType_t xCommandID,
-                                             const TickType_t xOptionalValue,
-                                             BaseType_t * const pxHigherPriorityTaskWoken,
-                                             const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                               \n"
-        " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
-        "                                                               \n"
-        " push {r0, r1}                                                 \n"
-        " mrs r0, control                                               \n"
-        " movs r1, #1                                                   \n"
-        " tst r0, r1                                                    \n"
-        " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
-        " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
-        "     pop {r0, r1}                                              \n"
-        "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
-        " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
-        "     pop {r0, r1}                                              \n"
-        "     svc %0                                                    \n"
-        "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
-        "     svc %1                                                    \n"
-        "     bx lr                                                     \n"
-        "                                                               \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pcTimerGetNameImpl                        \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_pcTimerGetName_Unpriv                         \n"
-        " MPU_pcTimerGetName_Priv:                              \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_pcTimerGetNameImpl                          \n"
-        " MPU_pcTimerGetName_Unpriv:                            \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pcTimerGetNameImpl                         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                              const BaseType_t uxAutoReload ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                              const BaseType_t uxAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTimerSetReloadModeImpl                   \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_vTimerSetReloadMode_Unpriv                    \n"
-        " MPU_vTimerSetReloadMode_Priv:                         \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_vTimerSetReloadModeImpl                     \n"
-        " MPU_vTimerSetReloadMode_Unpriv:                       \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTimerSetReloadModeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetReloadModeImpl                   \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTimerGetReloadMode_Unpriv                    \n"
-        " MPU_xTimerGetReloadMode_Priv:                         \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTimerGetReloadModeImpl                     \n"
-        " MPU_xTimerGetReloadMode_Unpriv:                       \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetReloadModeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTimerGetReloadModeImpl                  \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_uxTimerGetReloadMode_Unpriv                   \n"
-        " MPU_uxTimerGetReloadMode_Priv:                        \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_uxTimerGetReloadModeImpl                    \n"
-        " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTimerGetReloadModeImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetPeriodImpl                       \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTimerGetPeriod_Unpriv                        \n"
-        " MPU_xTimerGetPeriod_Priv:                             \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTimerGetPeriodImpl                         \n"
-        " MPU_xTimerGetPeriod_Unpriv:                           \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetPeriodImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetExpiryTimeImpl                   \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xTimerGetExpiryTime_Unpriv                    \n"
-        " MPU_xTimerGetExpiryTime_Priv:                         \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xTimerGetExpiryTimeImpl                     \n"
-        " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetExpiryTimeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                     const EventBits_t uxBitsToSet,
                                      const EventBits_t uxBitsToWaitFor,
-                                     const BaseType_t xClearOnExit,
-                                     const BaseType_t xWaitForAllBits,
-                                     TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                     const EventBits_t uxBitsToSet,
                                      const EventBits_t uxBitsToWaitFor,
-                                     const BaseType_t xClearOnExit,
-                                     const BaseType_t xWaitForAllBits,
                                      TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupWaitBitsImpl                   \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
-        " MPU_xEventGroupWaitBits_Priv:                         \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xEventGroupWaitBitsImpl                     \n"
-        " MPU_xEventGroupWaitBits_Unpriv:                       \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupWaitBitsImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupSyncImpl                       \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xEventGroupSync_Unpriv                        \n"
+            " MPU_xEventGroupSync_Priv:                             \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xEventGroupSyncImpl                         \n"
+            " MPU_xEventGroupSync_Unpriv:                           \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupSyncImpl                        \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                      const EventBits_t uxBitsToClear ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                      const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupClearBitsImpl                  \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xEventGroupClearBits_Unpriv                   \n"
-        " MPU_xEventGroupClearBits_Priv:                        \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xEventGroupClearBitsImpl                    \n"
-        " MPU_xEventGroupClearBits_Unpriv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupClearBitsImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxEventGroupGetNumberImpl                 \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_uxEventGroupGetNumber_Unpriv                  \n"
+                " MPU_uxEventGroupGetNumber_Priv:                       \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_uxEventGroupGetNumberImpl                   \n"
+                " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxEventGroupGetNumberImpl                  \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
 /*-----------------------------------------------------------*/
 
-EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                    const EventBits_t uxBitsToSet ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                    const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupSetBitsImpl                    \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xEventGroupSetBits_Unpriv                     \n"
-        " MPU_xEventGroupSetBits_Priv:                          \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xEventGroupSetBitsImpl                      \n"
-        " MPU_xEventGroupSetBits_Unpriv:                        \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupSetBitsImpl                     \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vEventGroupSetNumber( void * xEventGroup,
+                                       UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vEventGroupSetNumber( void * xEventGroup,
+                                       UBaseType_t uxEventGroupNumber ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vEventGroupSetNumberImpl                  \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " bne MPU_vEventGroupSetNumber_Unpriv                   \n"
+                " MPU_vEventGroupSetNumber_Priv:                        \n"
+                "     pop {r0, r1}                                      \n"
+                "     b MPU_vEventGroupSetNumberImpl                    \n"
+                " MPU_vEventGroupSetNumber_Unpriv:                      \n"
+                "     pop {r0, r1}                                      \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vEventGroupSetNumberImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
 /*-----------------------------------------------------------*/
 
-EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                 const EventBits_t uxBitsToSet,
-                                 const EventBits_t uxBitsToWaitFor,
-                                 TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                  const void * pvTxData,
+                                  size_t xDataLengthBytes,
+                                  TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                 const EventBits_t uxBitsToSet,
-                                 const EventBits_t uxBitsToWaitFor,
-                                 TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupSyncImpl                       \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xEventGroupSync_Unpriv                        \n"
-        " MPU_xEventGroupSync_Priv:                             \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xEventGroupSyncImpl                         \n"
-        " MPU_xEventGroupSync_Unpriv:                           \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupSyncImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                  const void * pvTxData,
+                                  size_t xDataLengthBytes,
+                                  TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferSendImpl                     \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xStreamBufferSend_Unpriv                      \n"
+            " MPU_xStreamBufferSend_Priv:                           \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xStreamBufferSendImpl                       \n"
+            " MPU_xStreamBufferSend_Unpriv:                         \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferSendImpl                      \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                     void * pvRxData,
+                                     size_t xBufferLengthBytes,
+                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxEventGroupGetNumberImpl                 \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_uxEventGroupGetNumber_Unpriv                  \n"
-        " MPU_uxEventGroupGetNumber_Priv:                       \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_uxEventGroupGetNumberImpl                   \n"
-        " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxEventGroupGetNumberImpl                  \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                     void * pvRxData,
+                                     size_t xBufferLengthBytes,
+                                     TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferReceiveImpl                  \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xStreamBufferReceive_Unpriv                   \n"
+            " MPU_xStreamBufferReceive_Priv:                        \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xStreamBufferReceiveImpl                    \n"
+            " MPU_xStreamBufferReceive_Unpriv:                      \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferReceiveImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vEventGroupSetNumber( void * xEventGroup,
-                               UBaseType_t uxEventGroupNumber ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vEventGroupSetNumber( void * xEventGroup,
-                               UBaseType_t uxEventGroupNumber ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vEventGroupSetNumberImpl                  \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_vEventGroupSetNumber_Unpriv                   \n"
-        " MPU_vEventGroupSetNumber_Priv:                        \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_vEventGroupSetNumberImpl                    \n"
-        " MPU_vEventGroupSetNumber_Unpriv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vEventGroupSetNumberImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferIsFullImpl                   \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
+            " MPU_xStreamBufferIsFull_Priv:                         \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xStreamBufferIsFullImpl                     \n"
+            " MPU_xStreamBufferIsFull_Unpriv:                       \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferIsFullImpl                    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                              const void * pvTxData,
-                              size_t xDataLengthBytes,
-                              TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                              const void * pvTxData,
-                              size_t xDataLengthBytes,
-                              TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferSendImpl                     \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xStreamBufferSend_Unpriv                      \n"
-        " MPU_xStreamBufferSend_Priv:                           \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xStreamBufferSendImpl                       \n"
-        " MPU_xStreamBufferSend_Unpriv:                         \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferSendImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
+            " MPU_xStreamBufferIsEmpty_Priv:                        \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xStreamBufferIsEmptyImpl                    \n"
+            " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferIsEmptyImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                 void * pvRxData,
-                                 size_t xBufferLengthBytes,
-                                 TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                 void * pvRxData,
-                                 size_t xBufferLengthBytes,
-                                 TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferReceiveImpl                  \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xStreamBufferReceive_Unpriv                   \n"
-        " MPU_xStreamBufferReceive_Priv:                        \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xStreamBufferReceiveImpl                    \n"
-        " MPU_xStreamBufferReceive_Unpriv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferReceiveImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
+            " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
+            " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferSpacesAvailableImpl           \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferIsFullImpl                   \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
-        " MPU_xStreamBufferIsFull_Priv:                         \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xStreamBufferIsFullImpl                     \n"
-        " MPU_xStreamBufferIsFull_Unpriv:                       \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferIsFullImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
+            " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xStreamBufferBytesAvailableImpl             \n"
+            " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferBytesAvailableImpl            \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                 size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
-        " MPU_xStreamBufferIsEmpty_Priv:                        \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xStreamBufferIsEmptyImpl                    \n"
-        " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferIsEmptyImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                 size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
+            " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
+            " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferSetTriggerLevelImpl           \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
-        " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
-        " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferSpacesAvailableImpl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
-size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
-        " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xStreamBufferBytesAvailableImpl             \n"
-        " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferBytesAvailableImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                             size_t xTriggerLevel ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                             size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
-        " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
-        " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferSetTriggerLevelImpl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
-size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
-        "                                                       \n"
-        " push {r0, r1}                                         \n"
-        " mrs r0, control                                       \n"
-        " movs r1, #1                                           \n"
-        " tst r0, r1                                            \n"
-        " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
-        " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
-        "     pop {r0, r1}                                      \n"
-        "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
-        " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
-        "     pop {r0, r1}                                      \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferNextMessageLengthBytesImpl    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
+            " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
+            "     pop {r0, r1}                                      \n"
+            "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
+            " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
+            "     pop {r0, r1}                                      \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferNextMessageLengthBytesImpl    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
index 80410e82e..c940c304b 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
@@ -110,8 +110,8 @@
 /**
  * @brief Constants used during system call enter and exit.
  */
-#define portPSR_STACK_PADDING_MASK                ( 1UL << 9UL )
-#define portEXC_RETURN_STACK_FRAME_TYPE_MASK      ( 1UL << 4UL )
+#define portPSR_STACK_PADDING_MASK              ( 1UL << 9UL )
+#define portEXC_RETURN_STACK_FRAME_TYPE_MASK    ( 1UL << 4UL )
 /*-----------------------------------------------------------*/
 
 /**
@@ -133,81 +133,81 @@
 /**
  * @brief Offsets in the stack to the parameters when inside the SVC handler.
  */
-#define portOFFSET_TO_LR                    ( 5 )
-#define portOFFSET_TO_PC                    ( 6 )
-#define portOFFSET_TO_PSR                   ( 7 )
+#define portOFFSET_TO_LR     ( 5 )
+#define portOFFSET_TO_PC     ( 6 )
+#define portOFFSET_TO_PSR    ( 7 )
 /*-----------------------------------------------------------*/
 
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                      ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                      ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                       ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                      ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                      ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                     ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                     ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK  ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK               ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK               ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK               ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK               ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK               ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK               ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK               ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK               ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0              ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1              ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2              ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3              ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4              ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5              ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6              ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7              ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE            ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT      ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                      ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE             ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -216,11 +216,11 @@
 
 /* Extract last address of the MPU region as encoded in the
  * RLAR (Region Limit Address Register) value. */
-#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar )  \
+#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar ) \
     ( ( ( rlar ) & portMPU_RLAR_ADDRESS_MASK ) | ~portMPU_RLAR_ADDRESS_MASK )
 
 /* Does addr lies within [start, end] address range? */
-#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end )    \
+#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \
     ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) )
 
 /* Is the access request satisfied by the available permissions? */
@@ -422,54 +422,57 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the system call stack so that upon returning from
-     * SVC, the system call stack is used.
-     *
-     * It is used for the system calls with up to 4 parameters.
-     *
-     * @param pulTaskStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the system call stack so that upon returning from
+ * SVC, the system call stack is used.
+ *
+ * It is used for the system calls with up to 4 parameters.
+ *
+ * @param pulTaskStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallEnter( uint32_t * pulTaskStack,
+                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the system call stack so that upon returning from
-     * SVC, the system call stack is used.
-     *
-     * It is used for the system calls with 5 parameters.
-     *
-     * @param pulTaskStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the system call stack so that upon returning from
+ * SVC, the system call stack is used.
+ *
+ * It is used for the system calls with 5 parameters.
+ *
+ * @param pulTaskStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallEnter_1( uint32_t * pulTaskStack,
+                             uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the task stack so that upon returning from
-     * SVC, the task stack is used again.
-     *
-     * @param pulSystemCallStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the task stack so that upon returning from
+ * SVC, the task stack is used again.
+ *
+ * @param pulSystemCallStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallExit( uint32_t * pulSystemCallStack,
+                          uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Checks whether or not the calling task is privileged.
-     *
-     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
-     */
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
     BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
 
 #endif /* configENABLE_MPU == 1 */
@@ -1086,18 +1089,18 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             vRestoreContextOfFirstTask();
             break;
 
-        #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
-            case portSVC_RAISE_PRIVILEGE:
+            #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+                case portSVC_RAISE_PRIVILEGE:
 
-                /* Only raise the privilege, if the svc was raised from any of
-                 * the system calls. */
-                if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
-                    ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
-                {
-                    vRaisePrivilege();
-                }
-                break;
-        #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+                    /* Only raise the privilege, if the svc was raised from any of
+                     * the system calls. */
+                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+                    {
+                        vRaisePrivilege();
+                    }
+                    break;
+            #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
         default:
             /* Incorrect SVC call. */
@@ -1108,513 +1111,526 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulSystemCallStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallEnter( uint32_t * pulTaskStack,
+                           uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulSystemCallStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        /* This is not NULL only for the duration of the system call. */
-        configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+        #if defined( __ARMCC_VERSION )
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+
+            /* This is not NULL only for the duration of the system call. */
+            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the system call stack for the stack frame. */
+            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulSystemCallStack[ i ] = pulTaskStack[ i ];
+            }
+
+            /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
+             * restore it when we exit from the system call. */
+            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* Use the pulSystemCallStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+
+            /* Remember the location where we should copy the stack frame when we exit from
+             * the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+
+            /* Record if the hardware used padding to force the stack pointer
+             * to be double word aligned. */
+            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
+            {
+                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
             }
+
+            /* We ensure in pxPortInitialiseStack that the system call stack is
+             * double word aligned and therefore, there is no need of padding.
+             * Clear the bit[9] of stacked xPSR. */
+            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
+
+            /* Raise the privilege for the duration of the system call. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " bics r0, r1         \n" /* Clear nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the system call stack for the stack frame. */
-        pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulSystemCallStack[ i ] = pulTaskStack[ i ];
-        }
-
-        /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
-         * restore it when we exit from the system call. */
-        pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-        __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* Use the pulSystemCallStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-
-        /* Remember the location where we should copy the stack frame when we exit from
-         * the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-        /* Record if the hardware used padding to force the stack pointer
-         * to be double word aligned. */
-        if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-        {
-            pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-        }
-        else
-        {
-            pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-        }
-
-        /* We ensure in pxPortInitialiseStack that the system call stack is
-         * double word aligned and therefore, there is no need of padding.
-         * Clear the bit[9] of stacked xPSR. */
-        pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-        /* Raise the privilege for the duration of the system call. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " bics r0, r1         \n" /* Clear nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulSystemCallStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallEnter_1( uint32_t * pulTaskStack,
+                             uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulSystemCallStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        /* This is not NULL only for the duration of the system call. */
-        configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+        #if defined( __ARMCC_VERSION )
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+
+            /* This is not NULL only for the duration of the system call. */
+            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the system call stack for the stack frame and
+             * the parameter passed on the stack. We only need to copy one
+             * parameter but we still reserve 2 spaces to keep the stack
+             * double word aligned. */
+            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulSystemCallStack[ i ] = pulTaskStack[ i ];
+            }
+
+            /* Copy the parameter which is passed the stack. */
+            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
+            {
+                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
+
+                /* Record if the hardware used padding to force the stack pointer
+                 * to be double word aligned. */
+                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
+
+                /* Record if the hardware used padding to force the stack pointer
+                 * to be double word aligned. */
+                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
             }
+
+            /* Store the value of the LR and PSPLIM registers before the SVC was raised.
+             * We need to restore it when we exit from the system call. */
+            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* Use the pulSystemCallStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+
+            /* Remember the location where we should copy the stack frame when we exit from
+             * the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+
+            /* We ensure in pxPortInitialiseStack that the system call stack is
+             * double word aligned and therefore, there is no need of padding.
+             * Clear the bit[9] of stacked xPSR. */
+            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
+
+            /* Raise the privilege for the duration of the system call. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " bics r0, r1         \n" /* Clear nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the system call stack for the stack frame and
-         * the parameter passed on the stack. We only need to copy one
-         * parameter but we still reserve 2 spaces to keep the stack
-         * double word aligned. */
-        pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulSystemCallStack[ i ] = pulTaskStack[ i ];
-        }
-
-        /* Copy the parameter which is passed the stack. */
-        if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-        {
-            pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
-            /* Record if the hardware used padding to force the stack pointer
-             * to be double word aligned. */
-            pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-        }
-        else
-        {
-            pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
-            /* Record if the hardware used padding to force the stack pointer
-             * to be double word aligned. */
-            pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-        }
-
-        /* Store the value of the LR and PSPLIM registers before the SVC was raised.
-         * We need to restore it when we exit from the system call. */
-        pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-        __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* Use the pulSystemCallStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-
-        /* Remember the location where we should copy the stack frame when we exit from
-         * the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-        /* We ensure in pxPortInitialiseStack that the system call stack is
-         * double word aligned and therefore, there is no need of padding.
-         * Clear the bit[9] of stacked xPSR. */
-        pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-        /* Raise the privilege for the duration of the system call. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " bics r0, r1         \n" /* Clear nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulTaskStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallExit( uint32_t * pulSystemCallStack,
+                          uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulTaskStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+        #if defined( __ARMCC_VERSION )
+
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the task stack for the stack frame. */
+            pulTaskStack = pulTaskStack - ulStackFrameSize;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulTaskStack[ i ] = pulSystemCallStack[ i ];
+            }
+
+            /* Use the pulTaskStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
+
+            /* Restore the LR and PSPLIM to what they were at the time of
+             * system call entry. */
+            pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* If the hardware used padding to force the stack pointer
+             * to be double word aligned, set the stacked xPSR bit[9],
+             * otherwise clear it. */
+            if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG )
+            {
+                pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
             }
+
+            /* This is not NULL only for the duration of the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
+
+            /* Drop the privilege before returning to the thread mode. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " orrs r0, r1         \n" /* Set nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the task stack for the stack frame. */
-        pulTaskStack = pulTaskStack - ulStackFrameSize;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulTaskStack[ i ] = pulSystemCallStack[ i ];
-        }
-
-        /* Use the pulTaskStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
-
-        /* Restore the LR and PSPLIM to what they were at the time of
-         * system call entry. */
-        pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* If the hardware used padding to force the stack pointer
-         * to be double word aligned, set the stacked xPSR bit[9],
-         * otherwise clear it. */
-        if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG )
-        {
-            pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK;
-        }
-        else
-        {
-            pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-        }
-
-        /* This is not NULL only for the duration of the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
-
-        /* Drop the privilege before returning to the thread mode. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " orrs r0, r1         \n" /* Set nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */
-{
-    BaseType_t xTaskIsPrivileged = pdFALSE;
-    const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
-
-    if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+    BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */
     {
-        xTaskIsPrivileged = pdTRUE;
-    }
+        BaseType_t xTaskIsPrivileged = pdFALSE;
+        const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
 
-    return xTaskIsPrivileged;
-}
+        if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+        {
+            xTaskIsPrivileged = pdTRUE;
+        }
+
+        return xTaskIsPrivileged;
+    }
 
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
-#if( configENABLE_MPU == 1 )
+#if ( configENABLE_MPU == 1 )
 
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     StackType_t * pxEndOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters,
-                                     BaseType_t xRunPrivileged,
-                                     xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
-{
-    uint32_t ulIndex = 0;
-
-    xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
-    ulIndex++;
-
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
-    ulIndex++;
-
-    #if ( configENABLE_TRUSTZONE == 1 )
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters,
+                                         BaseType_t xRunPrivileged,
+                                         xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
     {
-        xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT;  /* xSecureContext. */
+        uint32_t ulIndex = 0;
+
+        xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
         ulIndex++;
-    }
-    #endif /* configENABLE_TRUSTZONE */
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
-    ulIndex++;
-    if( xRunPrivileged == pdTRUE )
-    {
-        xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */
         ulIndex++;
-    }
-    else
-    {
-        xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */
         ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
+        ulIndex++;
+
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters;            /* r0. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x01010101;                           /* r1. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x02020202;                           /* r2. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x03030303;                           /* r3. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x12121212;                           /* r12. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode;                  /* PC. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR;                     /* xPSR. */
+        ulIndex++;
+
+        #if ( configENABLE_TRUSTZONE == 1 )
+        {
+            xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT; /* xSecureContext. */
+            ulIndex++;
+        }
+        #endif /* configENABLE_TRUSTZONE */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
+        ulIndex++;
+
+        if( xRunPrivileged == pdTRUE )
+        {
+            xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
+            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+            ulIndex++;
+        }
+        else
+        {
+            xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
+            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+            ulIndex++;
+        }
+
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
+        ulIndex++;
+
+        #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+        {
+            /* Ensure that the system call stack is double word aligned. */
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] );
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) &
+                                                                                     ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
+
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] );
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) +
+                                                                                            ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) &
+                                                                                          ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
+
+            /* This is not NULL only for the duration of a system call. */
+            xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL;
+        }
+        #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
+
+        return &( xMPUSettings->ulContext[ ulIndex ] );
     }
-    xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
-    ulIndex++;
-
-    #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
-    {
-        /* Ensure that the system call stack is double word aligned. */
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] );
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) &
-                                                                                 ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
-
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] );
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) +
-                                                                                        ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) &
-                                                                                      ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
-
-        /* This is not NULL only for the duration of a system call. */
-        xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL;
-    }
-    #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
-
-    return &( xMPUSettings->ulContext[ ulIndex ] );
-}
 
 #else /* configENABLE_MPU */
 
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     StackType_t * pxEndOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters ) /* PRIVILEGED_FUNCTION */
-{
-    /* Simulate the stack frame as it would be created by a context switch
-     * interrupt. */
-    #if ( portPRELOAD_REGISTERS == 0 )
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters ) /* PRIVILEGED_FUNCTION */
     {
-        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-        pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
-        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-        pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
-        *pxTopOfStack = portINITIAL_EXC_RETURN;
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
-
-        #if ( configENABLE_TRUSTZONE == 1 )
+        /* Simulate the stack frame as it would be created by a context switch
+         * interrupt. */
+        #if ( portPRELOAD_REGISTERS == 0 )
         {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
-        }
-        #endif /* configENABLE_TRUSTZONE */
-    }
-    #else /* portPRELOAD_REGISTERS */
-    {
-        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
-        pxTopOfStack--;
-        *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
+            pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
+            *pxTopOfStack = portINITIAL_EXC_RETURN;
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+            #if ( configENABLE_TRUSTZONE == 1 )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+            }
+            #endif /* configENABLE_TRUSTZONE */
+        }
+        #else /* portPRELOAD_REGISTERS */
         {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
-        }
-        #endif /* configENABLE_TRUSTZONE */
-    }
-    #endif /* portPRELOAD_REGISTERS */
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
+            pxTopOfStack--;
+            *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack;            /* Slot used to hold this task's PSPLIM value. */
 
-    return pxTopOfStack;
-}
+            #if ( configENABLE_TRUSTZONE == 1 )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+            }
+            #endif /* configENABLE_TRUSTZONE */
+        }
+        #endif /* portPRELOAD_REGISTERS */
+
+        return pxTopOfStack;
+    }
 
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c b/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c
index b11b6e97c..c1d3b4618 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c
@@ -46,127 +46,127 @@
 
 #if ( configENABLE_MPU == 1 )
 
-void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        " .syntax unified                                 \n"
-        "                                                 \n"
-        " program_mpu_first_task:                         \n"
-        "    ldr r3, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB.*/
-        "                                                 \n"
-        "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-        "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
-        "    movs r3, #1                                  \n" /* r3 = 1. */
-        "    bics r2, r3                                  \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
-        "    str r2, [r1]                                 \n" /* Disable MPU. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
-        "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-        "    ldr r2, xMAIR0Const2                         \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-        "    str r1, [r2]                                 \n" /* Program MAIR0. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-        "    ldr r1, xRNRConst2                           \n" /* r1 = 0xe000ed98 [Location of RNR]. */
-        "                                                 \n"
-        "    movs r3, #4                                  \n" /* r3 = 4. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 4. */
-        "    ldmia r0!, {r4-r5}                           \n" /* Read first set of RBAR/RLAR registers from TCB. */
-        "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "    stmia r2!, {r4-r5}                           \n" /* Write first set of RBAR/RLAR registers. */
-        "    movs r3, #5                                  \n" /* r3 = 5. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 5. */
-        "    ldmia r0!, {r4-r5}                           \n" /* Read second set of RBAR/RLAR registers from TCB. */
-        "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "    stmia r2!, {r4-r5}                           \n" /* Write second set of RBAR/RLAR registers. */
-        "    movs r3, #6                                  \n" /* r3 = 6. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 6. */
-        "    ldmia r0!, {r4-r5}                           \n" /* Read third set of RBAR/RLAR registers from TCB. */
-        "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "    stmia r2!, {r4-r5}                           \n" /* Write third set of RBAR/RLAR registers. */
-        "    movs r3, #7                                  \n" /* r3 = 6. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 7. */
-        "    ldmia r0!, {r4-r5}                           \n" /* Read fourth set of RBAR/RLAR registers from TCB. */
-        "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "    stmia r2!, {r4-r5}                           \n" /* Write fourth set of RBAR/RLAR registers. */
-        "                                                 \n"
-        "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
-        "    movs r3, #1                                  \n" /* r3 = 1. */
-        "    orrs r2, r3                                  \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
-        "    str r2, [r1]                                 \n" /* Enable MPU. */
-        "    dsb                                          \n" /* Force memory writes before continuing. */
-        "                                                 \n"
-        " restore_context_first_task:                     \n"
-        "    ldr r2, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB.*/
-        "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
-        "                                                 \n"
-        " restore_special_regs_first_task:                \n"
-        "    subs r1, #16                                 \n"
-        "    ldmia r1!, {r2-r5}                           \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, r5 = LR. */
-        "    subs r1, #16                                 \n"
-        "    msr psp, r2                                  \n"
-        "    msr psplim, r3                               \n"
-        "    msr control, r4                              \n"
-        "    mov lr, r5                                   \n"
-        "                                                 \n"
-        " restore_general_regs_first_task:                \n"
-        "    subs r1, #32                                 \n"
-        "    ldmia r1!, {r4-r7}                           \n" /* r4-r7 contain half of the hardware saved context. */
-        "    stmia r2!, {r4-r7}                           \n" /* Copy half of the the hardware saved context on the task stack. */
-        "    ldmia r1!, {r4-r7}                           \n" /* r4-r7 contain rest half of the hardware saved context. */
-        "    stmia r2!, {r4-r7}                           \n" /* Copy rest half of the the hardware saved context on the task stack. */
-        "    subs r1, #48                                 \n"
-        "    ldmia r1!, {r4-r7}                           \n" /* Restore r8-r11. */
-        "    mov r8, r4                                   \n" /* r8 = r4. */
-        "    mov r9, r5                                   \n" /* r9 = r5. */
-        "    mov r10, r6                                  \n" /* r10 = r6. */
-        "    mov r11, r7                                  \n" /* r11 = r7. */
-        "    subs r1, #32                                 \n"
-        "    ldmia r1!, {r4-r7}                           \n" /* Restore r4-r7. */
-        "    subs r1, #16                                 \n"
-        "                                                 \n"
-        " restore_context_done_first_task:                \n"
-        "    str r1, [r0]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
-        "    bx lr                                        \n"
-        "                                                 \n"
-        " .align 4                                        \n"
-        " pxCurrentTCBConst2: .word pxCurrentTCB          \n"
-        " xMPUCTRLConst2: .word 0xe000ed94                \n"
-        " xMAIR0Const2: .word 0xe000edc0                  \n"
-        " xRNRConst2: .word 0xe000ed98                    \n"
-        " xRBARConst2: .word 0xe000ed9c                   \n"
-    );
-}
+    void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                 \n"
+            "                                                 \n"
+            " program_mpu_first_task:                         \n"
+            "    ldr r3, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB.*/
+            "                                                 \n"
+            "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
+            "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
+            "    movs r3, #1                                  \n" /* r3 = 1. */
+            "    bics r2, r3                                  \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
+            "    str r2, [r1]                                 \n" /* Disable MPU. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
+            "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
+            "    ldr r2, xMAIR0Const2                         \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    str r1, [r2]                                 \n" /* Program MAIR0. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
+            "    ldr r1, xRNRConst2                           \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "                                                 \n"
+            "    movs r3, #4                                  \n" /* r3 = 4. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 4. */
+            "    ldmia r0!, {r4-r5}                           \n" /* Read first set of RBAR/RLAR registers from TCB. */
+            "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    stmia r2!, {r4-r5}                           \n" /* Write first set of RBAR/RLAR registers. */
+            "    movs r3, #5                                  \n" /* r3 = 5. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 5. */
+            "    ldmia r0!, {r4-r5}                           \n" /* Read second set of RBAR/RLAR registers from TCB. */
+            "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    stmia r2!, {r4-r5}                           \n" /* Write second set of RBAR/RLAR registers. */
+            "    movs r3, #6                                  \n" /* r3 = 6. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 6. */
+            "    ldmia r0!, {r4-r5}                           \n" /* Read third set of RBAR/RLAR registers from TCB. */
+            "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    stmia r2!, {r4-r5}                           \n" /* Write third set of RBAR/RLAR registers. */
+            "    movs r3, #7                                  \n" /* r3 = 6. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 7. */
+            "    ldmia r0!, {r4-r5}                           \n" /* Read fourth set of RBAR/RLAR registers from TCB. */
+            "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    stmia r2!, {r4-r5}                           \n" /* Write fourth set of RBAR/RLAR registers. */
+            "                                                 \n"
+            "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
+            "    movs r3, #1                                  \n" /* r3 = 1. */
+            "    orrs r2, r3                                  \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
+            "    str r2, [r1]                                 \n" /* Enable MPU. */
+            "    dsb                                          \n" /* Force memory writes before continuing. */
+            "                                                 \n"
+            " restore_context_first_task:                     \n"
+            "    ldr r2, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB.*/
+            "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
+            "                                                 \n"
+            " restore_special_regs_first_task:                \n"
+            "    subs r1, #16                                 \n"
+            "    ldmia r1!, {r2-r5}                           \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, r5 = LR. */
+            "    subs r1, #16                                 \n"
+            "    msr psp, r2                                  \n"
+            "    msr psplim, r3                               \n"
+            "    msr control, r4                              \n"
+            "    mov lr, r5                                   \n"
+            "                                                 \n"
+            " restore_general_regs_first_task:                \n"
+            "    subs r1, #32                                 \n"
+            "    ldmia r1!, {r4-r7}                           \n" /* r4-r7 contain half of the hardware saved context. */
+            "    stmia r2!, {r4-r7}                           \n" /* Copy half of the the hardware saved context on the task stack. */
+            "    ldmia r1!, {r4-r7}                           \n" /* r4-r7 contain rest half of the hardware saved context. */
+            "    stmia r2!, {r4-r7}                           \n" /* Copy rest half of the the hardware saved context on the task stack. */
+            "    subs r1, #48                                 \n"
+            "    ldmia r1!, {r4-r7}                           \n" /* Restore r8-r11. */
+            "    mov r8, r4                                   \n" /* r8 = r4. */
+            "    mov r9, r5                                   \n" /* r9 = r5. */
+            "    mov r10, r6                                  \n" /* r10 = r6. */
+            "    mov r11, r7                                  \n" /* r11 = r7. */
+            "    subs r1, #32                                 \n"
+            "    ldmia r1!, {r4-r7}                           \n" /* Restore r4-r7. */
+            "    subs r1, #16                                 \n"
+            "                                                 \n"
+            " restore_context_done_first_task:                \n"
+            "    str r1, [r0]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
+            "    bx lr                                        \n"
+            "                                                 \n"
+            " .align 4                                        \n"
+            " pxCurrentTCBConst2: .word pxCurrentTCB          \n"
+            " xMPUCTRLConst2: .word 0xe000ed94                \n"
+            " xMAIR0Const2: .word 0xe000edc0                  \n"
+            " xRNRConst2: .word 0xe000ed98                    \n"
+            " xRBARConst2: .word 0xe000ed9c                   \n"
+        );
+    }
 
 #else /* configENABLE_MPU */
 
-void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "   .syntax unified                                 \n"
-        "                                                   \n"
-        "   ldr  r2, pxCurrentTCBConst2                     \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr  r1, [r2]                                   \n"/* Read pxCurrentTCB. */
-        "   ldr  r0, [r1]                                   \n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
-        "                                                   \n"
-        "   ldm  r0!, {r1-r2}                               \n"/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
-        "   msr  psplim, r1                                 \n"/* Set this task's PSPLIM value. */
-        "   movs r1, #2                                     \n"/* r1 = 2. */
-        "   msr  CONTROL, r1                                \n"/* Switch to use PSP in the thread mode. */
-        "   adds r0, #32                                    \n"/* Discard everything up to r0. */
-        "   msr  psp, r0                                    \n"/* This is now the new top of stack to use in the task. */
-        "   isb                                             \n"
-        "   bx   r2                                         \n"/* Finally, branch to EXC_RETURN. */
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "pxCurrentTCBConst2: .word pxCurrentTCB             \n"
-    );
-}
+    void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            "   .syntax unified                                 \n"
+            "                                                   \n"
+            "   ldr  r2, pxCurrentTCBConst2                     \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr  r1, [r2]                                   \n" /* Read pxCurrentTCB. */
+            "   ldr  r0, [r1]                                   \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+            "                                                   \n"
+            "   ldm  r0!, {r1-r2}                               \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
+            "   msr  psplim, r1                                 \n" /* Set this task's PSPLIM value. */
+            "   movs r1, #2                                     \n" /* r1 = 2. */
+            "   msr  CONTROL, r1                                \n" /* Switch to use PSP in the thread mode. */
+            "   adds r0, #32                                    \n" /* Discard everything up to r0. */
+            "   msr  psp, r0                                    \n" /* This is now the new top of stack to use in the task. */
+            "   isb                                             \n"
+            "   bx   r2                                         \n" /* Finally, branch to EXC_RETURN. */
+            "                                                   \n"
+            "   .align 4                                        \n"
+            "pxCurrentTCBConst2: .word pxCurrentTCB             \n"
+        );
+    }
 
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
@@ -177,15 +177,15 @@ BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs r0, control                                 \n"/* r0 = CONTROL. */
-        "   movs r1, #1                                     \n"/* r1 = 1. */
-        "   tst r0, r1                                      \n"/* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
-        "   beq running_privileged                          \n"/* If the result of previous AND operation was 0, branch. */
-        "   movs r0, #0                                     \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
-        "   bx lr                                           \n"/* Return. */
+        "   mrs r0, control                                 \n" /* r0 = CONTROL. */
+        "   movs r1, #1                                     \n" /* r1 = 1. */
+        "   tst r0, r1                                      \n" /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
+        "   beq running_privileged                          \n" /* If the result of previous AND operation was 0, branch. */
+        "   movs r0, #0                                     \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+        "   bx lr                                           \n" /* Return. */
         " running_privileged:                               \n"
-        "   movs r0, #1                                     \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
-        "   bx lr                                           \n"/* Return. */
+        "   movs r0, #1                                     \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+        "   bx lr                                           \n" /* Return. */
         "                                                   \n"
         "   .align 4                                        \n"
         ::: "r0", "r1", "memory"
@@ -199,11 +199,11 @@ void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs  r0, control                                \n"/* Read the CONTROL register. */
-        "   movs r1, #1                                     \n"/* r1 = 1. */
-        "   bics r0, r1                                     \n"/* Clear the bit 0. */
-        "   msr  control, r0                                \n"/* Write back the new CONTROL value. */
-        "   bx lr                                           \n"/* Return to the caller. */
+        "   mrs  r0, control                                \n" /* Read the CONTROL register. */
+        "   movs r1, #1                                     \n" /* r1 = 1. */
+        "   bics r0, r1                                     \n" /* Clear the bit 0. */
+        "   msr  control, r0                                \n" /* Write back the new CONTROL value. */
+        "   bx lr                                           \n" /* Return to the caller. */
         ::: "r0", "r1", "memory"
     );
 }
@@ -215,11 +215,11 @@ void vResetPrivilege( void ) /* __attribute__ (( naked )) */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs r0, control                                 \n"/* r0 = CONTROL. */
-        "   movs r1, #1                                     \n"/* r1 = 1. */
-        "   orrs r0, r1                                     \n"/* r0 = r0 | r1. */
-        "   msr control, r0                                 \n"/* CONTROL = r0. */
-        "   bx lr                                           \n"/* Return to the caller. */
+        "   mrs r0, control                                 \n" /* r0 = CONTROL. */
+        "   movs r1, #1                                     \n" /* r1 = 1. */
+        "   orrs r0, r1                                     \n" /* r0 = r0 | r1. */
+        "   msr control, r0                                 \n" /* CONTROL = r0. */
+        "   bx lr                                           \n" /* Return to the caller. */
         ::: "r0", "r1", "memory"
     );
 }
@@ -231,14 +231,14 @@ void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   ldr r0, xVTORConst                              \n"/* Use the NVIC offset register to locate the stack. */
-        "   ldr r0, [r0]                                    \n"/* Read the VTOR register which gives the address of vector table. */
-        "   ldr r0, [r0]                                    \n"/* The first entry in vector table is stack pointer. */
-        "   msr msp, r0                                     \n"/* Set the MSP back to the start of the stack. */
-        "   cpsie i                                         \n"/* Globally enable interrupts. */
+        "   ldr r0, xVTORConst                              \n" /* Use the NVIC offset register to locate the stack. */
+        "   ldr r0, [r0]                                    \n" /* Read the VTOR register which gives the address of vector table. */
+        "   ldr r0, [r0]                                    \n" /* The first entry in vector table is stack pointer. */
+        "   msr msp, r0                                     \n" /* Set the MSP back to the start of the stack. */
+        "   cpsie i                                         \n" /* Globally enable interrupts. */
         "   dsb                                             \n"
         "   isb                                             \n"
-        "   svc %0                                          \n"/* System call to start the first task. */
+        "   svc %0                                          \n" /* System call to start the first task. */
         "   nop                                             \n"
         "                                                   \n"
         "   .align 4                                        \n"
@@ -277,254 +277,254 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
 
 #if ( configENABLE_MPU == 1 )
 
-void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        " .syntax unified                                 \n"
-        "                                                 \n"
-        " ldr r2, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        " ldr r0, [r2]                                    \n" /* r0 = pxCurrentTCB. */
-        " ldr r1, [r0]                                    \n" /* r1 = Location in TCB where the context should be saved. */
-        " mrs r2, psp                                     \n" /* r2 = PSP. */
-        "                                                 \n"
-        " save_general_regs:                              \n"
-        "    stmia r1!, {r4-r7}                           \n" /* Store r4-r7. */
-        "    mov r4, r8                                   \n" /* r4 = r8. */
-        "    mov r5, r9                                   \n" /* r5 = r9. */
-        "    mov r6, r10                                  \n" /* r6 = r10. */
-        "    mov r7, r11                                  \n" /* r7 = r11. */
-        "    stmia r1!, {r4-r7}                           \n" /* Store r8-r11. */
-        "    ldmia r2!, {r4-r7}                           \n" /* Copy half of the  hardware saved context into r4-r7. */
-        "    stmia r1!, {r4-r7}                           \n" /* Store the hardware saved context. */
-        "    ldmia r2!, {r4-r7}                           \n" /* Copy rest half of the  hardware saved context into r4-r7. */
-        "    stmia r1!, {r4-r7}                           \n" /* Store the hardware saved context. */
-        "                                                 \n"
-        " save_special_regs:                              \n"
-        "    mrs r2, psp                                  \n" /* r2 = PSP. */
-        "    mrs r3, psplim                               \n" /* r3 = PSPLIM. */
-        "    mrs r4, control                              \n" /* r4 = CONTROL. */
-        "    mov r5, lr                                   \n" /* r5 = LR. */
-        "    stmia r1!, {r2-r5}                           \n" /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
-        "    str r1, [r0]                                 \n" /* Save the location from where the context should be restored as the first member of TCB. */
-        "                                                 \n"
-        " select_next_task:                               \n"
-        "    cpsid i                                      \n"
-        "    bl vTaskSwitchContext                        \n"
-        "    cpsie i                                      \n"
-        "                                                 \n"
-        " program_mpu:                                    \n"
-        "    ldr r3, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB.*/
-        "                                                 \n"
-        "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-        "    ldr r1, xMPUCTRLConst                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
-        "    movs r3, #1                                  \n" /* r3 = 1. */
-        "    bics r2, r3                                  \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
-        "    str r2, [r1]                                 \n" /* Disable MPU. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
-        "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-        "    ldr r2, xMAIR0Const                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-        "    str r1, [r2]                                 \n" /* Program MAIR0. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-        "    ldr r1, xRNRConst                            \n" /* r1 = 0xe000ed98 [Location of RNR]. */
-        "                                                 \n"
-        "    movs r3, #4                                  \n" /* r3 = 4. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 4. */
-        "    ldmia r0!, {r4-r5}                           \n" /* Read first set of RBAR/RLAR registers from TCB. */
-        "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "    stmia r2!, {r4-r5}                           \n" /* Write first set of RBAR/RLAR registers. */
-        "    movs r3, #5                                  \n" /* r3 = 5. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 5. */
-        "    ldmia r0!, {r4-r5}                           \n" /* Read second set of RBAR/RLAR registers from TCB. */
-        "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "    stmia r2!, {r4-r5}                           \n" /* Write second set of RBAR/RLAR registers. */
-        "    movs r3, #6                                  \n" /* r3 = 6. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 6. */
-        "    ldmia r0!, {r4-r5}                           \n" /* Read third set of RBAR/RLAR registers from TCB. */
-        "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "    stmia r2!, {r4-r5}                           \n" /* Write third set of RBAR/RLAR registers. */
-        "    movs r3, #7                                  \n" /* r3 = 6. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 7. */
-        "    ldmia r0!, {r4-r5}                           \n" /* Read fourth set of RBAR/RLAR registers from TCB. */
-        "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "    stmia r2!, {r4-r5}                           \n" /* Write fourth set of RBAR/RLAR registers. */
-        "                                                 \n"
-        "    ldr r1, xMPUCTRLConst                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
-        "    movs r3, #1                                  \n" /* r3 = 1. */
-        "    orrs r2, r3                                  \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
-        "    str r2, [r1]                                 \n" /* Enable MPU. */
-        "    dsb                                          \n" /* Force memory writes before continuing. */
-        "                                                 \n"
-        " restore_context:                                \n"
-        "    ldr r2, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB.*/
-        "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
-        "                                                 \n"
-        " restore_special_regs:                           \n"
-        "    subs r1, #16                                 \n"
-        "    ldmia r1!, {r2-r5}                           \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, r5 = LR. */
-        "    subs r1, #16                                 \n"
-        "    msr psp, r2                                  \n"
-        "    msr psplim, r3                               \n"
-        "    msr control, r4                              \n"
-        "    mov lr, r5                                   \n"
-        "                                                 \n"
-        " restore_general_regs:                           \n"
-        "    subs r1, #32                                 \n"
-        "    ldmia r1!, {r4-r7}                           \n" /* r4-r7 contain half of the hardware saved context. */
-        "    stmia r2!, {r4-r7}                           \n" /* Copy half of the the hardware saved context on the task stack. */
-        "    ldmia r1!, {r4-r7}                           \n" /* r4-r7 contain rest half of the hardware saved context. */
-        "    stmia r2!, {r4-r7}                           \n" /* Copy rest half of the the hardware saved context on the task stack. */
-        "    subs r1, #48                                 \n"
-        "    ldmia r1!, {r4-r7}                           \n" /* Restore r8-r11. */
-        "    mov r8, r4                                   \n" /* r8 = r4. */
-        "    mov r9, r5                                   \n" /* r9 = r5. */
-        "    mov r10, r6                                  \n" /* r10 = r6. */
-        "    mov r11, r7                                  \n" /* r11 = r7. */
-        "    subs r1, #32                                 \n"
-        "    ldmia r1!, {r4-r7}                           \n" /* Restore r4-r7. */
-        "    subs r1, #16                                 \n"
-        "                                                 \n"
-        " restore_context_done:                           \n"
-        "    str r1, [r0]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
-        "    bx lr                                        \n"
-        "                                                 \n"
-        " .align 4                                        \n"
-        " pxCurrentTCBConst: .word pxCurrentTCB           \n"
-        " xMPUCTRLConst: .word 0xe000ed94                 \n"
-        " xMAIR0Const: .word 0xe000edc0                   \n"
-        " xRNRConst: .word 0xe000ed98                     \n"
-        " xRBARConst: .word 0xe000ed9c                    \n"
-    );
-}
+    void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                 \n"
+            "                                                 \n"
+            " ldr r2, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            " ldr r0, [r2]                                    \n" /* r0 = pxCurrentTCB. */
+            " ldr r1, [r0]                                    \n" /* r1 = Location in TCB where the context should be saved. */
+            " mrs r2, psp                                     \n" /* r2 = PSP. */
+            "                                                 \n"
+            " save_general_regs:                              \n"
+            "    stmia r1!, {r4-r7}                           \n" /* Store r4-r7. */
+            "    mov r4, r8                                   \n" /* r4 = r8. */
+            "    mov r5, r9                                   \n" /* r5 = r9. */
+            "    mov r6, r10                                  \n" /* r6 = r10. */
+            "    mov r7, r11                                  \n" /* r7 = r11. */
+            "    stmia r1!, {r4-r7}                           \n" /* Store r8-r11. */
+            "    ldmia r2!, {r4-r7}                           \n" /* Copy half of the  hardware saved context into r4-r7. */
+            "    stmia r1!, {r4-r7}                           \n" /* Store the hardware saved context. */
+            "    ldmia r2!, {r4-r7}                           \n" /* Copy rest half of the  hardware saved context into r4-r7. */
+            "    stmia r1!, {r4-r7}                           \n" /* Store the hardware saved context. */
+            "                                                 \n"
+            " save_special_regs:                              \n"
+            "    mrs r2, psp                                  \n" /* r2 = PSP. */
+            "    mrs r3, psplim                               \n" /* r3 = PSPLIM. */
+            "    mrs r4, control                              \n" /* r4 = CONTROL. */
+            "    mov r5, lr                                   \n" /* r5 = LR. */
+            "    stmia r1!, {r2-r5}                           \n" /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
+            "    str r1, [r0]                                 \n" /* Save the location from where the context should be restored as the first member of TCB. */
+            "                                                 \n"
+            " select_next_task:                               \n"
+            "    cpsid i                                      \n"
+            "    bl vTaskSwitchContext                        \n"
+            "    cpsie i                                      \n"
+            "                                                 \n"
+            " program_mpu:                                    \n"
+            "    ldr r3, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB.*/
+            "                                                 \n"
+            "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
+            "    ldr r1, xMPUCTRLConst                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
+            "    movs r3, #1                                  \n" /* r3 = 1. */
+            "    bics r2, r3                                  \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
+            "    str r2, [r1]                                 \n" /* Disable MPU. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
+            "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
+            "    ldr r2, xMAIR0Const                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    str r1, [r2]                                 \n" /* Program MAIR0. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
+            "    ldr r1, xRNRConst                            \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "                                                 \n"
+            "    movs r3, #4                                  \n" /* r3 = 4. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 4. */
+            "    ldmia r0!, {r4-r5}                           \n" /* Read first set of RBAR/RLAR registers from TCB. */
+            "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    stmia r2!, {r4-r5}                           \n" /* Write first set of RBAR/RLAR registers. */
+            "    movs r3, #5                                  \n" /* r3 = 5. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 5. */
+            "    ldmia r0!, {r4-r5}                           \n" /* Read second set of RBAR/RLAR registers from TCB. */
+            "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    stmia r2!, {r4-r5}                           \n" /* Write second set of RBAR/RLAR registers. */
+            "    movs r3, #6                                  \n" /* r3 = 6. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 6. */
+            "    ldmia r0!, {r4-r5}                           \n" /* Read third set of RBAR/RLAR registers from TCB. */
+            "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    stmia r2!, {r4-r5}                           \n" /* Write third set of RBAR/RLAR registers. */
+            "    movs r3, #7                                  \n" /* r3 = 6. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 7. */
+            "    ldmia r0!, {r4-r5}                           \n" /* Read fourth set of RBAR/RLAR registers from TCB. */
+            "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    stmia r2!, {r4-r5}                           \n" /* Write fourth set of RBAR/RLAR registers. */
+            "                                                 \n"
+            "    ldr r1, xMPUCTRLConst                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
+            "    movs r3, #1                                  \n" /* r3 = 1. */
+            "    orrs r2, r3                                  \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
+            "    str r2, [r1]                                 \n" /* Enable MPU. */
+            "    dsb                                          \n" /* Force memory writes before continuing. */
+            "                                                 \n"
+            " restore_context:                                \n"
+            "    ldr r2, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB.*/
+            "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
+            "                                                 \n"
+            " restore_special_regs:                           \n"
+            "    subs r1, #16                                 \n"
+            "    ldmia r1!, {r2-r5}                           \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, r5 = LR. */
+            "    subs r1, #16                                 \n"
+            "    msr psp, r2                                  \n"
+            "    msr psplim, r3                               \n"
+            "    msr control, r4                              \n"
+            "    mov lr, r5                                   \n"
+            "                                                 \n"
+            " restore_general_regs:                           \n"
+            "    subs r1, #32                                 \n"
+            "    ldmia r1!, {r4-r7}                           \n" /* r4-r7 contain half of the hardware saved context. */
+            "    stmia r2!, {r4-r7}                           \n" /* Copy half of the the hardware saved context on the task stack. */
+            "    ldmia r1!, {r4-r7}                           \n" /* r4-r7 contain rest half of the hardware saved context. */
+            "    stmia r2!, {r4-r7}                           \n" /* Copy rest half of the the hardware saved context on the task stack. */
+            "    subs r1, #48                                 \n"
+            "    ldmia r1!, {r4-r7}                           \n" /* Restore r8-r11. */
+            "    mov r8, r4                                   \n" /* r8 = r4. */
+            "    mov r9, r5                                   \n" /* r9 = r5. */
+            "    mov r10, r6                                  \n" /* r10 = r6. */
+            "    mov r11, r7                                  \n" /* r11 = r7. */
+            "    subs r1, #32                                 \n"
+            "    ldmia r1!, {r4-r7}                           \n" /* Restore r4-r7. */
+            "    subs r1, #16                                 \n"
+            "                                                 \n"
+            " restore_context_done:                           \n"
+            "    str r1, [r0]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
+            "    bx lr                                        \n"
+            "                                                 \n"
+            " .align 4                                        \n"
+            " pxCurrentTCBConst: .word pxCurrentTCB           \n"
+            " xMPUCTRLConst: .word 0xe000ed94                 \n"
+            " xMAIR0Const: .word 0xe000edc0                   \n"
+            " xRNRConst: .word 0xe000ed98                     \n"
+            " xRBARConst: .word 0xe000ed9c                    \n"
+        );
+    }
 
 #else /* configENABLE_MPU */
 
-void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "   .syntax unified                                 \n"
-        "                                                   \n"
-        "   mrs r0, psp                                     \n"/* Read PSP in r0. */
-        "   ldr r2, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r2]                                    \n"/* Read pxCurrentTCB. */
-        "   subs r0, r0, #40                                \n"/* Make space for PSPLIM, LR and the remaining registers on the stack. */
-        "   str r0, [r1]                                    \n"/* Save the new top of stack in TCB. */
-        "   mrs r2, psplim                                  \n"/* r2 = PSPLIM. */
-        "   mov r3, lr                                      \n"/* r3 = LR/EXC_RETURN. */
-        "   stmia r0!, {r2-r7}                              \n"/* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */
-        "   mov r4, r8                                      \n"/* r4 = r8. */
-        "   mov r5, r9                                      \n"/* r5 = r9. */
-        "   mov r6, r10                                     \n"/* r6 = r10. */
-        "   mov r7, r11                                     \n"/* r7 = r11. */
-        "   stmia r0!, {r4-r7}                              \n"/* Store the high registers that are not saved automatically. */
-        "                                                   \n"
-        "   cpsid i                                         \n"
-        "   bl vTaskSwitchContext                           \n"
-        "   cpsie i                                         \n"
-        "                                                   \n"
-        "   ldr r2, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r2]                                    \n"/* Read pxCurrentTCB. */
-        "   ldr r0, [r1]                                    \n"/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
-        "                                                   \n"
-        "   adds r0, r0, #24                                \n"/* Move to the high registers. */
-        "   ldmia r0!, {r4-r7}                              \n"/* Restore the high registers that are not automatically restored. */
-        "   mov r8, r4                                      \n"/* r8 = r4. */
-        "   mov r9, r5                                      \n"/* r9 = r5. */
-        "   mov r10, r6                                     \n"/* r10 = r6. */
-        "   mov r11, r7                                     \n"/* r11 = r7. */
-        "   msr psp, r0                                     \n"/* Remember the new top of stack for the task. */
-        "   subs r0, r0, #40                                \n"/* Move to the starting of the saved context. */
-        "   ldmia r0!, {r2-r7}                              \n"/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */
-        "   msr psplim, r2                                  \n"/* Restore the PSPLIM register value for the task. */
-        "   bx r3                                           \n"
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "pxCurrentTCBConst: .word pxCurrentTCB              \n"
-    );
-}
+    void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            "   .syntax unified                                 \n"
+            "                                                   \n"
+            "   mrs r0, psp                                     \n" /* Read PSP in r0. */
+            "   ldr r2, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r1, [r2]                                    \n" /* Read pxCurrentTCB. */
+            "   subs r0, r0, #40                                \n" /* Make space for PSPLIM, LR and the remaining registers on the stack. */
+            "   str r0, [r1]                                    \n" /* Save the new top of stack in TCB. */
+            "   mrs r2, psplim                                  \n" /* r2 = PSPLIM. */
+            "   mov r3, lr                                      \n" /* r3 = LR/EXC_RETURN. */
+            "   stmia r0!, {r2-r7}                              \n" /* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */
+            "   mov r4, r8                                      \n" /* r4 = r8. */
+            "   mov r5, r9                                      \n" /* r5 = r9. */
+            "   mov r6, r10                                     \n" /* r6 = r10. */
+            "   mov r7, r11                                     \n" /* r7 = r11. */
+            "   stmia r0!, {r4-r7}                              \n" /* Store the high registers that are not saved automatically. */
+            "                                                   \n"
+            "   cpsid i                                         \n"
+            "   bl vTaskSwitchContext                           \n"
+            "   cpsie i                                         \n"
+            "                                                   \n"
+            "   ldr r2, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r1, [r2]                                    \n" /* Read pxCurrentTCB. */
+            "   ldr r0, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
+            "                                                   \n"
+            "   adds r0, r0, #24                                \n" /* Move to the high registers. */
+            "   ldmia r0!, {r4-r7}                              \n" /* Restore the high registers that are not automatically restored. */
+            "   mov r8, r4                                      \n" /* r8 = r4. */
+            "   mov r9, r5                                      \n" /* r9 = r5. */
+            "   mov r10, r6                                     \n" /* r10 = r6. */
+            "   mov r11, r7                                     \n" /* r11 = r7. */
+            "   msr psp, r0                                     \n" /* Remember the new top of stack for the task. */
+            "   subs r0, r0, #40                                \n" /* Move to the starting of the saved context. */
+            "   ldmia r0!, {r2-r7}                              \n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */
+            "   msr psplim, r2                                  \n" /* Restore the PSPLIM register value for the task. */
+            "   bx r3                                           \n"
+            "                                                   \n"
+            "   .align 4                                        \n"
+            "pxCurrentTCBConst: .word pxCurrentTCB              \n"
+        );
+    }
 
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-   __asm volatile
-    (
-        ".syntax unified                \n"
-        ".extern vPortSVCHandler_C      \n"
-        ".extern vSystemCallEnter       \n"
-        ".extern vSystemCallEnter_1     \n"
-        ".extern vSystemCallExit        \n"
-        "                               \n"
-        "movs r0, #4                    \n"
-        "mov r1, lr                     \n"
-        "tst r0, r1                     \n"
-        "beq stack_on_msp               \n"
-        "stack_on_psp:                  \n"
-        "    mrs r0, psp                \n"
-        "    b route_svc                \n"
-        "stack_on_msp:                  \n"
-        "    mrs r0, msp                \n"
-        "    b route_svc                \n"
-        "                               \n"
-        "route_svc:                     \n"
-        "    ldr r2, [r0, #24]          \n"
-        "    subs r2, #2                \n"
-        "    ldrb r3, [r2, #0]          \n"
-        "    cmp r3, %0                 \n"
-        "    beq system_call_enter      \n"
-        "    cmp r3, %1                 \n"
-        "    beq system_call_enter_1    \n"
-        "    cmp r3, %2                 \n"
-        "    beq system_call_exit       \n"
-        "    b vPortSVCHandler_C        \n"
-        "                               \n"
-        "system_call_enter:             \n"
-        "    b vSystemCallEnter         \n"
-        "system_call_enter_1:           \n"
-        "    b vSystemCallEnter_1       \n"
-        "system_call_exit:              \n"
-        "    b vSystemCallExit          \n"
-        "                               \n"
-        : /* No outputs. */
-        :"i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT )
-        : "r0", "r1", "r2", "r3", "memory"
-    );
-}
+    void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            ".syntax unified                \n"
+            ".extern vPortSVCHandler_C      \n"
+            ".extern vSystemCallEnter       \n"
+            ".extern vSystemCallEnter_1     \n"
+            ".extern vSystemCallExit        \n"
+            "                               \n"
+            "movs r0, #4                    \n"
+            "mov r1, lr                     \n"
+            "tst r0, r1                     \n"
+            "beq stack_on_msp               \n"
+            "stack_on_psp:                  \n"
+            "    mrs r0, psp                \n"
+            "    b route_svc                \n"
+            "stack_on_msp:                  \n"
+            "    mrs r0, msp                \n"
+            "    b route_svc                \n"
+            "                               \n"
+            "route_svc:                     \n"
+            "    ldr r2, [r0, #24]          \n"
+            "    subs r2, #2                \n"
+            "    ldrb r3, [r2, #0]          \n"
+            "    cmp r3, %0                 \n"
+            "    beq system_call_enter      \n"
+            "    cmp r3, %1                 \n"
+            "    beq system_call_enter_1    \n"
+            "    cmp r3, %2                 \n"
+            "    beq system_call_exit       \n"
+            "    b vPortSVCHandler_C        \n"
+            "                               \n"
+            "system_call_enter:             \n"
+            "    b vSystemCallEnter         \n"
+            "system_call_enter_1:           \n"
+            "    b vSystemCallEnter_1       \n"
+            "system_call_exit:              \n"
+            "    b vSystemCallExit          \n"
+            "                               \n"
+            : /* No outputs. */
+            : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT )
+            : "r0", "r1", "r2", "r3", "memory"
+        );
+    }
 
 #else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
-void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "   .syntax unified                                 \n"
-        "                                                   \n"
-        "   movs r0, #4                                     \n"
-        "   mov r1, lr                                      \n"
-        "   tst r0, r1                                      \n"
-        "   beq stacking_used_msp                           \n"
-        "   mrs r0, psp                                     \n"
-        "   ldr r2, svchandler_address_const                \n"
-        "   bx r2                                           \n"
-        " stacking_used_msp:                                \n"
-        "   mrs r0, msp                                     \n"
-        "   ldr r2, svchandler_address_const                \n"
-        "   bx r2                                           \n"
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "svchandler_address_const: .word vPortSVCHandler_C  \n"
-    );
-}
+    void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            "   .syntax unified                                 \n"
+            "                                                   \n"
+            "   movs r0, #4                                     \n"
+            "   mov r1, lr                                      \n"
+            "   tst r0, r1                                      \n"
+            "   beq stacking_used_msp                           \n"
+            "   mrs r0, psp                                     \n"
+            "   ldr r2, svchandler_address_const                \n"
+            "   bx r2                                           \n"
+            " stacking_used_msp:                                \n"
+            "   mrs r0, msp                                     \n"
+            "   ldr r2, svchandler_address_const                \n"
+            "   bx r2                                           \n"
+            "                                                   \n"
+            "   .align 4                                        \n"
+            "svchandler_address_const: .word vPortSVCHandler_C  \n"
+        );
+    }
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h b/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h
index 233ea5a57..33d522488 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h
@@ -48,9 +48,9 @@
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME                       "Cortex-M23"
-#define portHAS_ARMV8M_MAIN_EXTENSION       0
-#define portDONT_DISCARD                    __attribute__( ( used ) )
+#define portARCH_NAME                    "Cortex-M23"
+#define portHAS_ARMV8M_MAIN_EXTENSION    0
+#define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
 /* ARMv8-M common port configurations. */
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h
index e5ffdb48b..62e462a27 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h
@@ -81,8 +81,8 @@ typedef unsigned long    UBaseType_t;
     typedef uint32_t     TickType_t;
     #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-     * not need to be guarded with a critical section. */
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
     #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -117,7 +117,7 @@ extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGE
 extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
 
 #if ( configENABLE_TRUSTZONE == 1 )
-    extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize );     /* __attribute__ (( naked )) */
+    extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
     extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
 #endif /* configENABLE_TRUSTZONE */
 
@@ -188,13 +188,13 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Settings to define an MPU region.
-     */
+/**
+ * @brief Settings to define an MPU region.
+ */
     typedef struct MPURegionSettings
     {
-        uint32_t ulRBAR;     /**< RBAR for the region. */
-        uint32_t ulRLAR;     /**< RLAR for the region. */
+        uint32_t ulRBAR; /**< RBAR for the region. */
+        uint32_t ulRLAR; /**< RLAR for the region. */
     } MPURegionSettings_t;
 
     #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
@@ -203,9 +203,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-        /**
-         * @brief System call stack.
-         */
+/**
+ * @brief System call stack.
+ */
         typedef struct SYSTEM_CALL_STACK_INFO
         {
             uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ];
@@ -218,74 +218,74 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
-    /**
-     * @brief MPU settings as stored in the TCB.
-     */
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
     #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
 
-        #if( configENABLE_TRUSTZONE == 1 )
+        #if ( configENABLE_TRUSTZONE == 1 )
 
-            /*
-             * +-----------+---------------+----------+-----------------+------------------------------+-----+
-             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
-             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
-             * +-----------+---------------+----------+-----------------+------------------------------+-----+
-             *
-             * <-----------><--------------><---------><----------------><-----------------------------><---->
-             *      16             16            8               8                     5                   1
-             */
-            #define MAX_CONTEXT_SIZE 54
+/*
+ * +-----------+---------------+----------+-----------------+------------------------------+-----+
+ * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+ * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+ * +-----------+---------------+----------+-----------------+------------------------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><-----------------------------><---->
+ *      16             16            8               8                     5                   1
+ */
+            #define MAX_CONTEXT_SIZE    54
 
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-            /*
-             * +-----------+---------------+----------+-----------------+----------------------+-----+
-             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
-             * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
-             * +-----------+---------------+----------+-----------------+----------------------+-----+
-             *
-             * <-----------><--------------><---------><----------------><---------------------><---->
-             *      16             16            8               8                  4              1
-             */
-            #define MAX_CONTEXT_SIZE 53
+/*
+ * +-----------+---------------+----------+-----------------+----------------------+-----+
+ * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+ * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
+ * +-----------+---------------+----------+-----------------+----------------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><---------------------><---->
+ *      16             16            8               8                  4              1
+ */
+            #define MAX_CONTEXT_SIZE    53
 
         #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
 
     #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-        #if( configENABLE_TRUSTZONE == 1 )
+        #if ( configENABLE_TRUSTZONE == 1 )
 
-            /*
-             * +----------+-----------------+------------------------------+-----+
-             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
-             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
-             * +----------+-----------------+------------------------------+-----+
-             *
-             * <---------><----------------><------------------------------><---->
-             *     8               8                      5                   1
-             */
-            #define MAX_CONTEXT_SIZE 22
+/*
+ * +----------+-----------------+------------------------------+-----+
+ * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+ * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+ * +----------+-----------------+------------------------------+-----+
+ *
+ * <---------><----------------><------------------------------><---->
+ *     8               8                      5                   1
+ */
+            #define MAX_CONTEXT_SIZE    22
 
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-            /*
-             * +----------+-----------------+----------------------+-----+
-             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
-             * |          | PC, xPSR        | EXC_RETURN           |     |
-             * +----------+-----------------+----------------------+-----+
-             *
-             * <---------><----------------><----------------------><---->
-             *     8               8                  4              1
-             */
-            #define MAX_CONTEXT_SIZE 21
+/*
+ * +----------+-----------------+----------------------+-----+
+ * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+ * |          | PC, xPSR        | EXC_RETURN           |     |
+ * +----------+-----------------+----------------------+-----+
+ *
+ * <---------><----------------><----------------------><---->
+ *     8               8                  4              1
+ */
+            #define MAX_CONTEXT_SIZE    21
 
         #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
 
     #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-    /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
-    #define portSTACK_FRAME_HAS_PADDING_FLAG     ( 1UL << 0UL )
-    #define portTASK_IS_PRIVILEGED_FLAG          ( 1UL << 1UL )
+/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
+    #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
+    #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
     typedef struct MPU_SETTINGS
     {
@@ -364,49 +364,49 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-    /**
-     * @brief Allocate a secure context for the task.
-     *
-     * Tasks are not created with a secure context. Any task that is going to call
-     * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
-     * secure context before it calls any secure function.
-     *
-     * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
-     */
+/**
+ * @brief Allocate a secure context for the task.
+ *
+ * Tasks are not created with a secure context. Any task that is going to call
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+ * secure context before it calls any secure function.
+ *
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+ */
     #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
 
-    /**
-     * @brief Called when a task is deleted to delete the task's secure context,
-     * if it has one.
-     *
-     * @param[in] pxTCB The TCB of the task being deleted.
-     */
+/**
+ * @brief Called when a task is deleted to delete the task's secure context,
+ * if it has one.
+ *
+ * @param[in] pxTCB The TCB of the task being deleted.
+ */
     #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
 #endif /* configENABLE_TRUSTZONE */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Checks whether or not the processor is privileged.
-     *
-     * @return 1 if the processor is already privileged, 0 otherwise.
-     */
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
     #define portIS_PRIVILEGED()      xIsPrivileged()
 
-    /**
-     * @brief Raise an SVC request to raise privilege.
-     *
-     * The SVC handler checks that the SVC was raised from a system call and only
-     * then it raises the privilege. If this is called from any other place,
-     * the privilege is not raised.
-     */
+/**
+ * @brief Raise an SVC request to raise privilege.
+ *
+ * The SVC handler checks that the SVC was raised from a system call and only
+ * then it raises the privilege. If this is called from any other place,
+ * the privilege is not raised.
+ */
     #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
 
-    /**
-     * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
-     * register.
-     */
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
     #define portRESET_PRIVILEGE()    vResetPrivilege()
 #else
     #define portIS_PRIVILEGED()
@@ -419,12 +419,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     extern BaseType_t xPortIsTaskPrivileged( void );
 
-    /**
-     * @brief Checks whether or not the calling task is privileged.
-     *
-     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
-     */
-    #define portIS_TASK_PRIVILEGED()      xPortIsTaskPrivileged()
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
+    #define portIS_TASK_PRIVILEGED()    xPortIsTaskPrivileged()
 
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
@@ -439,9 +439,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * based on whether or not Mainline extension is implemented. */
 #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
     #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
-        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
     #else
-        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    0
     #endif
 #endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
 
@@ -450,9 +450,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  */
 #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
 
-    /**
-     * @brief Count the number of leading zeros in a 32-bit value.
-     */
+/**
+ * @brief Count the number of leading zeros in a 32-bit value.
+ */
     static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
     {
         uint32_t ulReturn;
@@ -462,7 +462,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         return ulReturn;
     }
 
-    /* Check the configuration. */
+/* Check the configuration. */
     #if ( configMAX_PRIORITIES > 32 )
         #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
     #endif
@@ -471,16 +471,16 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection.  Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
     #endif
 
-    /**
-     * @brief Store/clear the ready priorities in a bit map.
-     */
-    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+/**
+ * @brief Store/clear the ready priorities in a bit map.
+ */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )      ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )       ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 
-    /**
-     * @brief Get the priority of the highest-priority task that is ready to execute.
-     */
-    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )   uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+/**
+ * @brief Get the priority of the highest-priority task that is ready to execute.
+ */
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
 
 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM3/port.c b/portable/GCC/ARM_CM3/port.c
index ac8185f5f..df633d11e 100644
--- a/portable/GCC/ARM_CM3/port.c
+++ b/portable/GCC/ARM_CM3/port.c
@@ -219,11 +219,11 @@ static void prvTaskExitError( void )
 void vPortSVCHandler( void )
 {
     __asm volatile (
-        "   ldr r3, pxCurrentTCBConst2      \n"/* Restore the context. */
-        "   ldr r1, [r3]                    \n"/* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
-        "   ldr r0, [r1]                    \n"/* The first item in pxCurrentTCB is the task top of stack. */
-        "   ldmia r0!, {r4-r11}             \n"/* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
-        "   msr psp, r0                     \n"/* Restore the task stack pointer. */
+        "   ldr r3, pxCurrentTCBConst2      \n" /* Restore the context. */
+        "   ldr r1, [r3]                    \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
+        "   ldr r0, [r1]                    \n" /* The first item in pxCurrentTCB is the task top of stack. */
+        "   ldmia r0!, {r4-r11}             \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
+        "   msr psp, r0                     \n" /* Restore the task stack pointer. */
         "   isb                             \n"
         "   mov r0, #0                      \n"
         "   msr basepri, r0                 \n"
@@ -239,15 +239,15 @@ void vPortSVCHandler( void )
 static void prvPortStartFirstTask( void )
 {
     __asm volatile (
-        " ldr r0, =0xE000ED08   \n"/* Use the NVIC offset register to locate the stack. */
+        " ldr r0, =0xE000ED08   \n" /* Use the NVIC offset register to locate the stack. */
         " ldr r0, [r0]          \n"
         " ldr r0, [r0]          \n"
-        " msr msp, r0           \n"/* Set the msp back to the start of the stack. */
-        " cpsie i               \n"/* Globally enable interrupts. */
+        " msr msp, r0           \n" /* Set the msp back to the start of the stack. */
+        " cpsie i               \n" /* Globally enable interrupts. */
         " cpsie f               \n"
         " dsb                   \n"
         " isb                   \n"
-        " svc 0                 \n"/* System call to start first task. */
+        " svc 0                 \n" /* System call to start first task. */
         " nop                   \n"
         " .ltorg                \n"
         );
@@ -308,22 +308,22 @@ BaseType_t xPortStartScheduler( void )
         if( ulImplementedPrioBits == 8 )
         {
             /* When the hardware implements 8 priority bits, there is no way for
-            * the software to configure PRIGROUP to not have sub-priorities. As
-            * a result, the least significant bit is always used for sub-priority
-            * and there are 128 preemption priorities and 2 sub-priorities.
-            *
-            * This may cause some confusion in some cases - for example, if
-            * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
-            * priority interrupts will be masked in Critical Sections as those
-            * are at the same preemption priority. This may appear confusing as
-            * 4 is higher (numerically lower) priority than
-            * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
-            * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
-            * to 4, this confusion does not happen and the behaviour remains the same.
-            *
-            * The following assert ensures that the sub-priority bit in the
-            * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
-            * confusion. */
+             * the software to configure PRIGROUP to not have sub-priorities. As
+             * a result, the least significant bit is always used for sub-priority
+             * and there are 128 preemption priorities and 2 sub-priorities.
+             *
+             * This may cause some confusion in some cases - for example, if
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
+             * priority interrupts will be masked in Critical Sections as those
+             * are at the same preemption priority. This may appear confusing as
+             * 4 is higher (numerically lower) priority than
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
+             * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
+             * to 4, this confusion does not happen and the behaviour remains the same.
+             *
+             * The following assert ensures that the sub-priority bit in the
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
+             * confusion. */
             configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
             ulMaxPRIGROUPValue = 0;
         }
@@ -417,11 +417,11 @@ void xPortPendSVHandler( void )
         "   mrs r0, psp                         \n"
         "   isb                                 \n"
         "                                       \n"
-        "   ldr r3, pxCurrentTCBConst           \n"/* Get the location of the current TCB. */
+        "   ldr r3, pxCurrentTCBConst           \n" /* Get the location of the current TCB. */
         "   ldr r2, [r3]                        \n"
         "                                       \n"
-        "   stmdb r0!, {r4-r11}                 \n"/* Save the remaining registers. */
-        "   str r0, [r2]                        \n"/* Save the new top of stack into the first member of the TCB. */
+        "   stmdb r0!, {r4-r11}                 \n" /* Save the remaining registers. */
+        "   str r0, [r2]                        \n" /* Save the new top of stack into the first member of the TCB. */
         "                                       \n"
         "   stmdb sp!, {r3, r14}                \n"
         "   mov r0, %0                          \n"
@@ -430,10 +430,10 @@ void xPortPendSVHandler( void )
         "   mov r0, #0                          \n"
         "   msr basepri, r0                     \n"
         "   ldmia sp!, {r3, r14}                \n"
-        "                                       \n"/* Restore the context, including the critical nesting count. */
+        "                                       \n" /* Restore the context, including the critical nesting count. */
         "   ldr r1, [r3]                        \n"
-        "   ldr r0, [r1]                        \n"/* The first item in pxCurrentTCB is the task top of stack. */
-        "   ldmia r0!, {r4-r11}                 \n"/* Pop the registers. */
+        "   ldr r0, [r1]                        \n" /* The first item in pxCurrentTCB is the task top of stack. */
+        "   ldmia r0!, {r4-r11}                 \n" /* Pop the registers. */
         "   msr psp, r0                         \n"
         "   isb                                 \n"
         "   bx r14                              \n"
@@ -769,4 +769,4 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
         configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
     }
 
-#endif /* configASSERT_DEFINED */
\ No newline at end of file
+#endif /* configASSERT_DEFINED */
diff --git a/portable/GCC/ARM_CM3/portmacro.h b/portable/GCC/ARM_CM3/portmacro.h
index 0ff96b82a..0d6782270 100644
--- a/portable/GCC/ARM_CM3/portmacro.h
+++ b/portable/GCC/ARM_CM3/portmacro.h
@@ -28,7 +28,7 @@
 
 
 #ifndef PORTMACRO_H
-    #define PORTMACRO_H
+#define PORTMACRO_H
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
@@ -47,42 +47,42 @@
  */
 
 /* Type definitions. */
-    #define portCHAR          char
-    #define portFLOAT         float
-    #define portDOUBLE        double
-    #define portLONG          long
-    #define portSHORT         short
-    #define portSTACK_TYPE    uint32_t
-    #define portBASE_TYPE     long
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-    typedef portSTACK_TYPE   StackType_t;
-    typedef long             BaseType_t;
-    typedef unsigned long    UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
-    #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-        typedef uint16_t     TickType_t;
-        #define portMAX_DELAY              ( TickType_t ) 0xffff
-    #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-        typedef uint32_t     TickType_t;
-        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
  * not need to be guarded with a critical section. */
-        #define portTICK_TYPE_IS_ATOMIC    1
-    #else
-        #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
-    #endif
+    #define portTICK_TYPE_IS_ATOMIC    1
+#else
+    #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+#endif
 /*-----------------------------------------------------------*/
 
 /* Architecture specifics. */
-    #define portSTACK_GROWTH      ( -1 )
-    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-    #define portBYTE_ALIGNMENT    8
-    #define portDONT_DISCARD      __attribute__( ( used ) )
+#define portSTACK_GROWTH      ( -1 )
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT    8
+#define portDONT_DISCARD      __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
 /* Scheduler utilities. */
-    #define portYIELD()                                 \
+#define portYIELD()                                     \
     {                                                   \
         /* Set a PendSV to request a context switch. */ \
         portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
@@ -93,156 +93,156 @@
         __asm volatile ( "isb" );                                  \
     }
 
-    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
-    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-    #define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 )
-    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+#define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired != pdFALSE ) portYIELD( ); } while( 0 )
+#define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
 /* Critical section management. */
-    extern void vPortEnterCritical( void );
-    extern void vPortExitCritical( void );
-    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulPortRaiseBASEPRI()
-    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vPortSetBASEPRI( x )
-    #define portDISABLE_INTERRUPTS()                  vPortRaiseBASEPRI()
-    #define portENABLE_INTERRUPTS()                   vPortSetBASEPRI( 0 )
-    #define portENTER_CRITICAL()                      vPortEnterCritical()
-    #define portEXIT_CRITICAL()                       vPortExitCritical()
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+#define portSET_INTERRUPT_MASK_FROM_ISR()         ulPortRaiseBASEPRI()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vPortSetBASEPRI( x )
+#define portDISABLE_INTERRUPTS()                  vPortRaiseBASEPRI()
+#define portENABLE_INTERRUPTS()                   vPortSetBASEPRI( 0 )
+#define portENTER_CRITICAL()                      vPortEnterCritical()
+#define portEXIT_CRITICAL()                       vPortExitCritical()
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site.  These are
  * not necessary for to use this port.  They are defined so the common demo files
  * (which build with all the ports) will build. */
-    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
-    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 /*-----------------------------------------------------------*/
 
 /* Tickless idle/low power functionality. */
-    #ifndef portSUPPRESS_TICKS_AND_SLEEP
-        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
-        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
-    #endif
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+    extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+    #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
 /*-----------------------------------------------------------*/
 
 /* Architecture specific optimisations. */
-    #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
-    #endif
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+    #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
+#endif
 
-    #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
 
 /* Generic helper function. */
-        __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
-        {
-            uint8_t ucReturn;
+    __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
+    {
+        uint8_t ucReturn;
 
-            __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
+        __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
 
-            return ucReturn;
-        }
+        return ucReturn;
+    }
 
 /* Check the configuration. */
-        #if ( configMAX_PRIORITIES > 32 )
-            #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
-        #endif
+    #if ( configMAX_PRIORITIES > 32 )
+        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+    #endif
 
 /* Store/clear the ready priorities in a bit map. */
-        #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-        #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 
 /*-----------------------------------------------------------*/
 
-        #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
 
-    #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 
 /*-----------------------------------------------------------*/
 
-    #ifdef configASSERT
-        void vPortValidateInterruptPriority( void );
-        #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
-    #endif
+#ifdef configASSERT
+    void vPortValidateInterruptPriority( void );
+    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
+#endif
 
 /* portNOP() is not required by this port. */
-    #define portNOP()
+#define portNOP()
 
-    #define portINLINE              __inline
+#define portINLINE              __inline
 
-    #ifndef portFORCE_INLINE
-        #define portFORCE_INLINE    inline __attribute__( ( always_inline ) )
-    #endif
+#ifndef portFORCE_INLINE
+    #define portFORCE_INLINE    inline __attribute__( ( always_inline ) )
+#endif
 
 /*-----------------------------------------------------------*/
 
-    portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
+portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
+{
+    uint32_t ulCurrentInterrupt;
+    BaseType_t xReturn;
+
+    /* Obtain the number of the currently executing interrupt. */
+    __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+    if( ulCurrentInterrupt == 0 )
     {
-        uint32_t ulCurrentInterrupt;
-        BaseType_t xReturn;
-
-        /* Obtain the number of the currently executing interrupt. */
-        __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
-
-        if( ulCurrentInterrupt == 0 )
-        {
-            xReturn = pdFALSE;
-        }
-        else
-        {
-            xReturn = pdTRUE;
-        }
-
-        return xReturn;
+        xReturn = pdFALSE;
+    }
+    else
+    {
+        xReturn = pdTRUE;
     }
 
-/*-----------------------------------------------------------*/
-
-    portFORCE_INLINE static void vPortRaiseBASEPRI( void )
-    {
-        uint32_t ulNewBASEPRI;
-
-        __asm volatile
-        (
-            "   mov %0, %1                                              \n"\
-            "   msr basepri, %0                                         \n"\
-            "   isb                                                     \n"\
-            "   dsb                                                     \n"\
-            : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
-        );
-    }
+    return xReturn;
+}
 
 /*-----------------------------------------------------------*/
 
-    portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
-    {
-        uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
+portFORCE_INLINE static void vPortRaiseBASEPRI( void )
+{
+    uint32_t ulNewBASEPRI;
 
-        __asm volatile
-        (
-            "   mrs %0, basepri                                         \n"\
-            "   mov %1, %2                                              \n"\
-            "   msr basepri, %1                                         \n"\
-            "   isb                                                     \n"\
-            "   dsb                                                     \n"\
-            : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
-        );
+    __asm volatile
+    (
+        "   mov %0, %1                                              \n" \
+        "   msr basepri, %0                                         \n" \
+        "   isb                                                     \n" \
+        "   dsb                                                     \n" \
+        : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+    );
+}
 
-        /* This return will not be reached but is necessary to prevent compiler
-         * warnings. */
-        return ulOriginalBASEPRI;
-    }
 /*-----------------------------------------------------------*/
 
-    portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
-    {
-        __asm volatile
-        (
-            "   msr basepri, %0 "::"r" ( ulNewMaskValue ) : "memory"
-        );
-    }
+portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
+{
+    uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
+
+    __asm volatile
+    (
+        "   mrs %0, basepri                                         \n" \
+        "   mov %1, %2                                              \n" \
+        "   msr basepri, %1                                         \n" \
+        "   isb                                                     \n" \
+        "   dsb                                                     \n" \
+        : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+    );
+
+    /* This return will not be reached but is necessary to prevent compiler
+     * warnings. */
+    return ulOriginalBASEPRI;
+}
 /*-----------------------------------------------------------*/
 
-    #define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
+portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
+{
+    __asm volatile
+    (
+        "   msr basepri, %0 " ::"r" ( ulNewMaskValue ) : "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+#define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/GCC/ARM_CM33/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM33/non_secure/mpu_wrappers_v2_asm.c
index 2d1218a95..d1fbdc0e5 100644
--- a/portable/GCC/ARM_CM33/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM33/non_secure/mpu_wrappers_v2_asm.c
@@ -44,2274 +44,2274 @@
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-#if ( INCLUDE_xTaskDelayUntil == 1 )
+    #if ( INCLUDE_xTaskDelayUntil == 1 )
 
-BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
-                                const TickType_t xTimeIncrement ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
+                                        const TickType_t xTimeIncrement ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
-                                const TickType_t xTimeIncrement ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskDelayUntilImpl                       \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskDelayUntil_Unpriv                        \n"
-        " MPU_xTaskDelayUntil_Priv:                             \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskDelayUntilImpl                         \n"
-        " MPU_xTaskDelayUntil_Unpriv:                           \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskDelayUntilImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
+                                        const TickType_t xTimeIncrement ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskDelayUntilImpl                       \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskDelayUntil_Unpriv                        \n"
+                " MPU_xTaskDelayUntil_Priv:                             \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskDelayUntilImpl                         \n"
+                " MPU_xTaskDelayUntil_Unpriv:                           \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskDelayUntilImpl                        \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */
+    #endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_xTaskAbortDelay == 1 )
+    #if ( INCLUDE_xTaskAbortDelay == 1 )
 
-BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskAbortDelayImpl                       \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskAbortDelay_Unpriv                        \n"
-        " MPU_xTaskAbortDelay_Priv:                             \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskAbortDelayImpl                         \n"
-        " MPU_xTaskAbortDelay_Unpriv:                           \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskAbortDelayImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskAbortDelayImpl                       \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskAbortDelay_Unpriv                        \n"
+                " MPU_xTaskAbortDelay_Priv:                             \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskAbortDelayImpl                         \n"
+                " MPU_xTaskAbortDelay_Unpriv:                           \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskAbortDelayImpl                        \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */
+    #endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_vTaskDelay == 1 )
+    #if ( INCLUDE_vTaskDelay == 1 )
 
-void MPU_vTaskDelay( const TickType_t xTicksToDelay ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskDelay( const TickType_t xTicksToDelay ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskDelayImpl                            \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskDelay_Unpriv                             \n"
-        " MPU_vTaskDelay_Priv:                                  \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskDelayImpl                              \n"
-        " MPU_vTaskDelay_Unpriv:                                \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskDelayImpl                             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskDelayImpl                            \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskDelay_Unpriv                             \n"
+                " MPU_vTaskDelay_Priv:                                  \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskDelayImpl                              \n"
+                " MPU_vTaskDelay_Unpriv:                                \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskDelayImpl                             \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_vTaskDelay == 1 ) */
+    #endif /* if ( INCLUDE_vTaskDelay == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_uxTaskPriorityGet == 1 )
+    #if ( INCLUDE_uxTaskPriorityGet == 1 )
 
-UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskPriorityGetImpl                     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTaskPriorityGet_Unpriv                      \n"
-        " MPU_uxTaskPriorityGet_Priv:                           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTaskPriorityGetImpl                       \n"
-        " MPU_uxTaskPriorityGet_Unpriv:                         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskPriorityGetImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskPriorityGetImpl                     \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTaskPriorityGet_Unpriv                      \n"
+                " MPU_uxTaskPriorityGet_Priv:                           \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTaskPriorityGetImpl                       \n"
+                " MPU_uxTaskPriorityGet_Unpriv:                         \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskPriorityGetImpl                      \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */
+    #endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_eTaskGetState == 1 )
+    #if ( INCLUDE_eTaskGetState == 1 )
 
-eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_eTaskGetStateImpl                         \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_eTaskGetState_Unpriv                          \n"
-        " MPU_eTaskGetState_Priv:                               \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_eTaskGetStateImpl                           \n"
-        " MPU_eTaskGetState_Unpriv:                             \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_eTaskGetStateImpl                          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_eTaskGetStateImpl                         \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_eTaskGetState_Unpriv                          \n"
+                " MPU_eTaskGetState_Priv:                               \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_eTaskGetStateImpl                           \n"
+                " MPU_eTaskGetState_Unpriv:                             \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_eTaskGetStateImpl                          \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_eTaskGetState == 1 ) */
+    #endif /* if ( INCLUDE_eTaskGetState == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-void MPU_vTaskGetInfo( TaskHandle_t xTask,
-                       TaskStatus_t * pxTaskStatus,
-                       BaseType_t xGetFreeStackSpace,
-                       eTaskState eState ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskGetInfo( TaskHandle_t xTask,
+                               TaskStatus_t * pxTaskStatus,
+                               BaseType_t xGetFreeStackSpace,
+                               eTaskState eState ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskGetInfo( TaskHandle_t xTask,
-                       TaskStatus_t * pxTaskStatus,
-                       BaseType_t xGetFreeStackSpace,
-                       eTaskState eState ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskGetInfoImpl                          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskGetInfo_Unpriv                           \n"
-        " MPU_vTaskGetInfo_Priv:                                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskGetInfoImpl                            \n"
-        " MPU_vTaskGetInfo_Unpriv:                              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskGetInfoImpl                           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskGetInfo( TaskHandle_t xTask,
+                               TaskStatus_t * pxTaskStatus,
+                               BaseType_t xGetFreeStackSpace,
+                               eTaskState eState ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskGetInfoImpl                          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskGetInfo_Unpriv                           \n"
+                " MPU_vTaskGetInfo_Priv:                                \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskGetInfoImpl                            \n"
+                " MPU_vTaskGetInfo_Unpriv:                              \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskGetInfoImpl                           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
+    #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
+    #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
 
-TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetIdleTaskHandleImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGetIdleTaskHandle_Unpriv                 \n"
-        " MPU_xTaskGetIdleTaskHandle_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGetIdleTaskHandleImpl                  \n"
-        " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetIdleTaskHandleImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetIdleTaskHandleImpl                \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGetIdleTaskHandle_Unpriv                 \n"
+                " MPU_xTaskGetIdleTaskHandle_Priv:                      \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGetIdleTaskHandleImpl                  \n"
+                " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetIdleTaskHandleImpl                 \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */
+    #endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_vTaskSuspend == 1 )
+    #if ( INCLUDE_vTaskSuspend == 1 )
 
-void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSuspendImpl                          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskSuspend_Unpriv                           \n"
-        " MPU_vTaskSuspend_Priv:                                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskSuspendImpl                            \n"
-        " MPU_vTaskSuspend_Unpriv:                              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSuspendImpl                           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskSuspendImpl                          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskSuspend_Unpriv                           \n"
+                " MPU_vTaskSuspend_Priv:                                \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskSuspendImpl                            \n"
+                " MPU_vTaskSuspend_Unpriv:                              \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskSuspendImpl                           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
+    #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_vTaskSuspend == 1 )
+    #if ( INCLUDE_vTaskSuspend == 1 )
 
-void MPU_vTaskResume( TaskHandle_t xTaskToResume ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskResume( TaskHandle_t xTaskToResume ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskResumeImpl                           \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskResume_Unpriv                            \n"
-        " MPU_vTaskResume_Priv:                                 \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskResumeImpl                             \n"
-        " MPU_vTaskResume_Unpriv:                               \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskResumeImpl                            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskResumeImpl                           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskResume_Unpriv                            \n"
+                " MPU_vTaskResume_Priv:                                 \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskResumeImpl                             \n"
+                " MPU_vTaskResume_Unpriv:                               \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskResumeImpl                            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
+    #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
 /*-----------------------------------------------------------*/
 
-TickType_t MPU_xTaskGetTickCount( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    TickType_t MPU_xTaskGetTickCount( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TickType_t MPU_xTaskGetTickCount( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetTickCountImpl                     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGetTickCount_Unpriv                      \n"
-        " MPU_xTaskGetTickCount_Priv:                           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGetTickCountImpl                       \n"
-        " MPU_xTaskGetTickCount_Unpriv:                         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetTickCountImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    TickType_t MPU_xTaskGetTickCount( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xTaskGetTickCountImpl                     \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xTaskGetTickCount_Unpriv                      \n"
+            " MPU_xTaskGetTickCount_Priv:                           \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xTaskGetTickCountImpl                       \n"
+            " MPU_xTaskGetTickCount_Unpriv:                         \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xTaskGetTickCountImpl                      \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetNumberOfTasksImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTaskGetNumberOfTasks_Unpriv                 \n"
-        " MPU_uxTaskGetNumberOfTasks_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTaskGetNumberOfTasksImpl                  \n"
-        " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetNumberOfTasksImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_uxTaskGetNumberOfTasksImpl                \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_uxTaskGetNumberOfTasks_Unpriv                 \n"
+            " MPU_uxTaskGetNumberOfTasks_Priv:                      \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_uxTaskGetNumberOfTasksImpl                  \n"
+            " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_uxTaskGetNumberOfTasksImpl                 \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configGENERATE_RUN_TIME_STATS == 1 )
+    #if ( configGENERATE_RUN_TIME_STATS == 1 )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetRunTimeCounterImpl               \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGetRunTimeCounter_Unpriv                \n"
-        " MPU_ulTaskGetRunTimeCounter_Priv:                     \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGetRunTimeCounterImpl                 \n"
-        " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetRunTimeCounterImpl                \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetRunTimeCounterImpl               \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGetRunTimeCounter_Unpriv                \n"
+                " MPU_ulTaskGetRunTimeCounter_Priv:                     \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGetRunTimeCounterImpl                 \n"
+                " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetRunTimeCounterImpl                \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configGENERATE_RUN_TIME_STATS == 1 )
+    #if ( configGENERATE_RUN_TIME_STATS == 1 )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetRunTimePercentImpl               \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGetRunTimePercent_Unpriv                \n"
-        " MPU_ulTaskGetRunTimePercent_Priv:                     \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGetRunTimePercentImpl                 \n"
-        " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetRunTimePercentImpl                \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetRunTimePercentImpl               \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGetRunTimePercent_Unpriv                \n"
+                " MPU_ulTaskGetRunTimePercent_Priv:                     \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGetRunTimePercentImpl                 \n"
+                " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetRunTimePercentImpl                \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+    #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetIdleRunTimePercentImpl           \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv            \n"
-        " MPU_ulTaskGetIdleRunTimePercent_Priv:                 \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGetIdleRunTimePercentImpl             \n"
-        " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetIdleRunTimePercentImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetIdleRunTimePercentImpl           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv            \n"
+                " MPU_ulTaskGetIdleRunTimePercent_Priv:                 \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGetIdleRunTimePercentImpl             \n"
+                " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetIdleRunTimePercentImpl            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+    #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetIdleRunTimeCounterImpl           \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv            \n"
-        " MPU_ulTaskGetIdleRunTimeCounter_Priv:                 \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGetIdleRunTimeCounterImpl             \n"
-        " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetIdleRunTimeCounterImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetIdleRunTimeCounterImpl           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv            \n"
+                " MPU_ulTaskGetIdleRunTimeCounter_Priv:                 \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGetIdleRunTimeCounterImpl             \n"
+                " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetIdleRunTimeCounterImpl            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+    #if ( configUSE_APPLICATION_TASK_TAG == 1 )
 
-void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
-                                     TaskHookFunction_t pxHookFunction ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
+                                             TaskHookFunction_t pxHookFunction ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
-                                     TaskHookFunction_t pxHookFunction ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSetApplicationTaskTagImpl            \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskSetApplicationTaskTag_Unpriv             \n"
-        " MPU_vTaskSetApplicationTaskTag_Priv:                  \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskSetApplicationTaskTagImpl              \n"
-        " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSetApplicationTaskTagImpl             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
+                                             TaskHookFunction_t pxHookFunction ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskSetApplicationTaskTagImpl            \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskSetApplicationTaskTag_Unpriv             \n"
+                " MPU_vTaskSetApplicationTaskTag_Priv:                  \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskSetApplicationTaskTagImpl              \n"
+                " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskSetApplicationTaskTagImpl             \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
+    #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+    #if ( configUSE_APPLICATION_TASK_TAG == 1 )
 
-TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetApplicationTaskTagImpl            \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGetApplicationTaskTag_Unpriv             \n"
-        " MPU_xTaskGetApplicationTaskTag_Priv:                  \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGetApplicationTaskTagImpl              \n"
-        " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetApplicationTaskTagImpl             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetApplicationTaskTagImpl            \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGetApplicationTaskTag_Unpriv             \n"
+                " MPU_xTaskGetApplicationTaskTag_Priv:                  \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGetApplicationTaskTagImpl              \n"
+                " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetApplicationTaskTagImpl             \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
+    #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+    #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
 
-void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
-                                            BaseType_t xIndex,
-                                            void * pvValue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
+                                                    BaseType_t xIndex,
+                                                    void * pvValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
-                                            BaseType_t xIndex,
-                                            void * pvValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSetThreadLocalStoragePointerImpl     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv      \n"
-        " MPU_vTaskSetThreadLocalStoragePointer_Priv:           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskSetThreadLocalStoragePointerImpl       \n"
-        " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSetThreadLocalStoragePointerImpl      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
+                                                    BaseType_t xIndex,
+                                                    void * pvValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskSetThreadLocalStoragePointerImpl     \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv      \n"
+                " MPU_vTaskSetThreadLocalStoragePointer_Priv:           \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskSetThreadLocalStoragePointerImpl       \n"
+                " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskSetThreadLocalStoragePointerImpl      \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
+    #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+    #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
 
-void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
-                                               BaseType_t xIndex ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
+                                                       BaseType_t xIndex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
-                                               BaseType_t xIndex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pvTaskGetThreadLocalStoragePointerImpl    \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv     \n"
-        " MPU_pvTaskGetThreadLocalStoragePointer_Priv:          \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_pvTaskGetThreadLocalStoragePointerImpl      \n"
-        " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pvTaskGetThreadLocalStoragePointerImpl     \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
+                                                       BaseType_t xIndex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pvTaskGetThreadLocalStoragePointerImpl    \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv     \n"
+                " MPU_pvTaskGetThreadLocalStoragePointer_Priv:          \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_pvTaskGetThreadLocalStoragePointerImpl      \n"
+                " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pvTaskGetThreadLocalStoragePointerImpl     \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
+    #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
-                                      const UBaseType_t uxArraySize,
-                                      configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
+                                              const UBaseType_t uxArraySize,
+                                              configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
-                                      const UBaseType_t uxArraySize,
-                                      configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetSystemStateImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTaskGetSystemState_Unpriv                   \n"
-        " MPU_uxTaskGetSystemState_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTaskGetSystemStateImpl                    \n"
-        " MPU_uxTaskGetSystemState_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetSystemStateImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
+                                              const UBaseType_t uxArraySize,
+                                              configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskGetSystemStateImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTaskGetSystemState_Unpriv                   \n"
+                " MPU_uxTaskGetSystemState_Priv:                        \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTaskGetSystemStateImpl                    \n"
+                " MPU_uxTaskGetSystemState_Unpriv:                      \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskGetSystemStateImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
+    #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
+    #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
 
-UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetStackHighWaterMarkImpl           \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTaskGetStackHighWaterMark_Unpriv            \n"
-        " MPU_uxTaskGetStackHighWaterMark_Priv:                 \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTaskGetStackHighWaterMarkImpl             \n"
-        " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetStackHighWaterMarkImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskGetStackHighWaterMarkImpl           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTaskGetStackHighWaterMark_Unpriv            \n"
+                " MPU_uxTaskGetStackHighWaterMark_Priv:                 \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTaskGetStackHighWaterMarkImpl             \n"
+                " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskGetStackHighWaterMarkImpl            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */
+    #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
+    #if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
 
-configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetStackHighWaterMark2Impl          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv           \n"
-        " MPU_uxTaskGetStackHighWaterMark2_Priv:                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTaskGetStackHighWaterMark2Impl            \n"
-        " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetStackHighWaterMark2Impl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskGetStackHighWaterMark2Impl          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv           \n"
+                " MPU_uxTaskGetStackHighWaterMark2_Priv:                \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTaskGetStackHighWaterMark2Impl            \n"
+                " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskGetStackHighWaterMark2Impl           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */
+    #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
+    #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
 
-TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetCurrentTaskHandleImpl             \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGetCurrentTaskHandle_Unpriv              \n"
-        " MPU_xTaskGetCurrentTaskHandle_Priv:                   \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGetCurrentTaskHandleImpl               \n"
-        " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetCurrentTaskHandleImpl              \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetCurrentTaskHandleImpl             \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGetCurrentTaskHandle_Unpriv              \n"
+                " MPU_xTaskGetCurrentTaskHandle_Priv:                   \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGetCurrentTaskHandleImpl               \n"
+                " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetCurrentTaskHandleImpl              \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
+    #endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_xTaskGetSchedulerState == 1 )
+    #if ( INCLUDE_xTaskGetSchedulerState == 1 )
 
-BaseType_t MPU_xTaskGetSchedulerState( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGetSchedulerState( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGetSchedulerState( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetSchedulerStateImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGetSchedulerState_Unpriv                 \n"
-        " MPU_xTaskGetSchedulerState_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGetSchedulerStateImpl                  \n"
-        " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetSchedulerStateImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGetSchedulerState( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetSchedulerStateImpl                \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGetSchedulerState_Unpriv                 \n"
+                " MPU_xTaskGetSchedulerState_Priv:                      \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGetSchedulerStateImpl                  \n"
+                " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetSchedulerStateImpl                 \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */
+    #endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */
 /*-----------------------------------------------------------*/
 
-void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSetTimeOutStateImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskSetTimeOutState_Unpriv                   \n"
-        " MPU_vTaskSetTimeOutState_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskSetTimeOutStateImpl                    \n"
-        " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSetTimeOutStateImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_vTaskSetTimeOutStateImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_vTaskSetTimeOutState_Unpriv                   \n"
+            " MPU_vTaskSetTimeOutState_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_vTaskSetTimeOutStateImpl                    \n"
+            " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_vTaskSetTimeOutStateImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
-                                     TickType_t * const pxTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
+                                         TickType_t * const pxTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
-                                     TickType_t * const pxTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskCheckForTimeOutImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskCheckForTimeOut_Unpriv                   \n"
-        " MPU_xTaskCheckForTimeOut_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskCheckForTimeOutImpl                    \n"
-        " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskCheckForTimeOutImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
+                                         TickType_t * const pxTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xTaskCheckForTimeOutImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xTaskCheckForTimeOut_Unpriv                   \n"
+            " MPU_xTaskCheckForTimeOut_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xTaskCheckForTimeOutImpl                    \n"
+            " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xTaskCheckForTimeOutImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                   UBaseType_t uxIndexToNotify,
-                                   uint32_t ulValue,
-                                   eNotifyAction eAction,
-                                   uint32_t * pulPreviousNotificationValue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
+                                           UBaseType_t uxIndexToNotify,
+                                           uint32_t ulValue,
+                                           eNotifyAction eAction,
+                                           uint32_t * pulPreviousNotificationValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                   UBaseType_t uxIndexToNotify,
-                                   uint32_t ulValue,
-                                   eNotifyAction eAction,
-                                   uint32_t * pulPreviousNotificationValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGenericNotifyImpl                    \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGenericNotify_Unpriv                     \n"
-        " MPU_xTaskGenericNotify_Priv:                          \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGenericNotifyImpl                      \n"
-        " MPU_xTaskGenericNotify_Unpriv:                        \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGenericNotifyImpl                     \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
+                                           UBaseType_t uxIndexToNotify,
+                                           uint32_t ulValue,
+                                           eNotifyAction eAction,
+                                           uint32_t * pulPreviousNotificationValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGenericNotifyImpl                    \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGenericNotify_Unpriv                     \n"
+                " MPU_xTaskGenericNotify_Priv:                          \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGenericNotifyImpl                      \n"
+                " MPU_xTaskGenericNotify_Unpriv:                        \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGenericNotifyImpl                     \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                       uint32_t ulBitsToClearOnEntry,
-                                       uint32_t ulBitsToClearOnExit,
-                                       uint32_t * pulNotificationValue,
-                                       TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
+                                               uint32_t ulBitsToClearOnEntry,
+                                               uint32_t ulBitsToClearOnExit,
+                                               uint32_t * pulNotificationValue,
+                                               TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                       uint32_t ulBitsToClearOnEntry,
-                                       uint32_t ulBitsToClearOnExit,
-                                       uint32_t * pulNotificationValue,
-                                       TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGenericNotifyWaitImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGenericNotifyWait_Unpriv                 \n"
-        " MPU_xTaskGenericNotifyWait_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGenericNotifyWaitImpl                  \n"
-        " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGenericNotifyWaitImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
+                                               uint32_t ulBitsToClearOnEntry,
+                                               uint32_t ulBitsToClearOnExit,
+                                               uint32_t * pulNotificationValue,
+                                               TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGenericNotifyWaitImpl                \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGenericNotifyWait_Unpriv                 \n"
+                " MPU_xTaskGenericNotifyWait_Priv:                      \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGenericNotifyWaitImpl                  \n"
+                " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGenericNotifyWaitImpl                 \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
-                                      BaseType_t xClearCountOnExit,
-                                      TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
+                                              BaseType_t xClearCountOnExit,
+                                              TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
-                                      BaseType_t xClearCountOnExit,
-                                      TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGenericNotifyTakeImpl               \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGenericNotifyTake_Unpriv                \n"
-        " MPU_ulTaskGenericNotifyTake_Priv:                     \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGenericNotifyTakeImpl                 \n"
-        " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGenericNotifyTakeImpl                \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
+                                              BaseType_t xClearCountOnExit,
+                                              TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGenericNotifyTakeImpl               \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGenericNotifyTake_Unpriv                \n"
+                " MPU_ulTaskGenericNotifyTake_Priv:                     \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGenericNotifyTakeImpl                 \n"
+                " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGenericNotifyTakeImpl                \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
-                                             UBaseType_t uxIndexToClear ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
+                                                     UBaseType_t uxIndexToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
-                                             UBaseType_t uxIndexToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGenericNotifyStateClearImpl          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGenericNotifyStateClear_Unpriv           \n"
-        " MPU_xTaskGenericNotifyStateClear_Priv:                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGenericNotifyStateClearImpl            \n"
-        " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGenericNotifyStateClearImpl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
+                                                     UBaseType_t uxIndexToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGenericNotifyStateClearImpl          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGenericNotifyStateClear_Unpriv           \n"
+                " MPU_xTaskGenericNotifyStateClear_Priv:                \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGenericNotifyStateClearImpl            \n"
+                " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGenericNotifyStateClearImpl           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
-                                            UBaseType_t uxIndexToClear,
-                                            uint32_t ulBitsToClear ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
+                                                    UBaseType_t uxIndexToClear,
+                                                    uint32_t ulBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
-                                            UBaseType_t uxIndexToClear,
-                                            uint32_t ulBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGenericNotifyValueClearImpl         \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGenericNotifyValueClear_Unpriv          \n"
-        " MPU_ulTaskGenericNotifyValueClear_Priv:               \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGenericNotifyValueClearImpl           \n"
-        " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGenericNotifyValueClearImpl          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
+                                                    UBaseType_t uxIndexToClear,
+                                                    uint32_t ulBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGenericNotifyValueClearImpl         \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGenericNotifyValueClear_Unpriv          \n"
+                " MPU_ulTaskGenericNotifyValueClear_Priv:               \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGenericNotifyValueClearImpl           \n"
+                " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGenericNotifyValueClearImpl          \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
-                                  const void * const pvItemToQueue,
-                                  TickType_t xTicksToWait,
-                                  const BaseType_t xCopyPosition ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
+                                      const void * const pvItemToQueue,
+                                      TickType_t xTicksToWait,
+                                      const BaseType_t xCopyPosition ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
-                                  const void * const pvItemToQueue,
-                                  TickType_t xTicksToWait,
-                                  const BaseType_t xCopyPosition ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueGenericSendImpl                     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueGenericSend_Unpriv                      \n"
-        " MPU_xQueueGenericSend_Priv:                           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueGenericSendImpl                       \n"
-        " MPU_xQueueGenericSend_Unpriv:                         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueGenericSendImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
+                                      const void * const pvItemToQueue,
+                                      TickType_t xTicksToWait,
+                                      const BaseType_t xCopyPosition ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueueGenericSendImpl                     \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xQueueGenericSend_Unpriv                      \n"
+            " MPU_xQueueGenericSend_Priv:                           \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xQueueGenericSendImpl                       \n"
+            " MPU_xQueueGenericSend_Unpriv:                         \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueueGenericSendImpl                      \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxQueueMessagesWaitingImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxQueueMessagesWaiting_Unpriv                 \n"
-        " MPU_uxQueueMessagesWaiting_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxQueueMessagesWaitingImpl                  \n"
-        " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxQueueMessagesWaitingImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_uxQueueMessagesWaitingImpl                \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_uxQueueMessagesWaiting_Unpriv                 \n"
+            " MPU_uxQueueMessagesWaiting_Priv:                      \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_uxQueueMessagesWaitingImpl                  \n"
+            " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_uxQueueMessagesWaitingImpl                 \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxQueueSpacesAvailableImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxQueueSpacesAvailable_Unpriv                 \n"
-        " MPU_uxQueueSpacesAvailable_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxQueueSpacesAvailableImpl                  \n"
-        " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxQueueSpacesAvailableImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_uxQueueSpacesAvailableImpl                \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_uxQueueSpacesAvailable_Unpriv                 \n"
+            " MPU_uxQueueSpacesAvailable_Priv:                      \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_uxQueueSpacesAvailableImpl                  \n"
+            " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_uxQueueSpacesAvailableImpl                 \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
-                              void * const pvBuffer,
-                              TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
+                                  void * const pvBuffer,
+                                  TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
-                              void * const pvBuffer,
-                              TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueReceiveImpl                         \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueReceive_Unpriv                          \n"
-        " MPU_xQueueReceive_Priv:                               \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueReceiveImpl                           \n"
-        " MPU_xQueueReceive_Unpriv:                             \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueReceiveImpl                          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
+                                  void * const pvBuffer,
+                                  TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueueReceiveImpl                         \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xQueueReceive_Unpriv                          \n"
+            " MPU_xQueueReceive_Priv:                               \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xQueueReceiveImpl                           \n"
+            " MPU_xQueueReceive_Unpriv:                             \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueueReceiveImpl                          \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
-                           void * const pvBuffer,
-                           TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
+                               void * const pvBuffer,
+                               TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
-                           void * const pvBuffer,
-                           TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueuePeekImpl                            \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueuePeek_Unpriv                             \n"
-        " MPU_xQueuePeek_Priv:                                  \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueuePeekImpl                              \n"
-        " MPU_xQueuePeek_Unpriv:                                \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueuePeekImpl                             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
+                               void * const pvBuffer,
+                               TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueuePeekImpl                            \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xQueuePeek_Unpriv                             \n"
+            " MPU_xQueuePeek_Priv:                                  \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xQueuePeekImpl                              \n"
+            " MPU_xQueuePeek_Unpriv:                                \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueuePeekImpl                             \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
-                                    TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
+                                        TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
-                                    TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueSemaphoreTakeImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueSemaphoreTake_Unpriv                    \n"
-        " MPU_xQueueSemaphoreTake_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueSemaphoreTakeImpl                     \n"
-        " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueSemaphoreTakeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
+                                        TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueueSemaphoreTakeImpl                   \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xQueueSemaphoreTake_Unpriv                    \n"
+            " MPU_xQueueSemaphoreTake_Priv:                         \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xQueueSemaphoreTakeImpl                     \n"
+            " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueueSemaphoreTakeImpl                    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+    #if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
 
-TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueGetMutexHolderImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueGetMutexHolder_Unpriv                   \n"
-        " MPU_xQueueGetMutexHolder_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueGetMutexHolderImpl                    \n"
-        " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueGetMutexHolderImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueGetMutexHolderImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueGetMutexHolder_Unpriv                   \n"
+                " MPU_xQueueGetMutexHolder_Priv:                        \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueGetMutexHolderImpl                    \n"
+                " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueGetMutexHolderImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */
+    #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+    #if ( configUSE_RECURSIVE_MUTEXES == 1 )
 
-BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
-                                         TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+                                                 TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+        BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+                                                 TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueTakeMutexRecursiveImpl              \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueTakeMutexRecursive_Unpriv               \n"
+                " MPU_xQueueTakeMutexRecursive_Priv:                    \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueTakeMutexRecursiveImpl                \n"
+                " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueTakeMutexRecursiveImpl               \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_RECURSIVE_MUTEXES == 1 )
+
+        BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueGiveMutexRecursiveImpl              \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueGiveMutexRecursive_Unpriv               \n"
+                " MPU_xQueueGiveMutexRecursive_Priv:                    \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueGiveMutexRecursiveImpl                \n"
+                " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueGiveMutexRecursiveImpl               \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_QUEUE_SETS == 1 )
+
+        QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
+                                                        const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
+                                                        const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueSelectFromSetImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueSelectFromSet_Unpriv                    \n"
+                " MPU_xQueueSelectFromSet_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueSelectFromSetImpl                     \n"
+                " MPU_xQueueSelectFromSet_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueSelectFromSetImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_QUEUE_SETS == 1 )
+
+        BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                                       QueueSetHandle_t xQueueSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                                       QueueSetHandle_t xQueueSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueAddToSetImpl                        \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueAddToSet_Unpriv                         \n"
+                " MPU_xQueueAddToSet_Priv:                              \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueAddToSetImpl                          \n"
+                " MPU_xQueueAddToSet_Unpriv:                            \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueAddToSetImpl                         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+        void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
+                                      const char * pcName ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
+                                      const char * pcName ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vQueueAddToRegistryImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vQueueAddToRegistry_Unpriv                    \n"
+                " MPU_vQueueAddToRegistry_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vQueueAddToRegistryImpl                     \n"
+                " MPU_vQueueAddToRegistry_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vQueueAddToRegistryImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+        void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vQueueUnregisterQueueImpl                 \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vQueueUnregisterQueue_Unpriv                  \n"
+                " MPU_vQueueUnregisterQueue_Priv:                       \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vQueueUnregisterQueueImpl                   \n"
+                " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vQueueUnregisterQueueImpl                  \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+        const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pcQueueGetNameImpl                        \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_pcQueueGetName_Unpriv                         \n"
+                " MPU_pcQueueGetName_Priv:                              \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_pcQueueGetNameImpl                          \n"
+                " MPU_pcQueueGetName_Unpriv:                            \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pcQueueGetNameImpl                         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pvTimerGetTimerIDImpl                     \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_pvTimerGetTimerID_Unpriv                      \n"
+                " MPU_pvTimerGetTimerID_Priv:                           \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_pvTimerGetTimerIDImpl                       \n"
+                " MPU_pvTimerGetTimerID_Unpriv:                         \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pvTimerGetTimerIDImpl                      \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
+                                   void * pvNewID ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
+                                   void * pvNewID ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTimerSetTimerIDImpl                      \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTimerSetTimerID_Unpriv                       \n"
+                " MPU_vTimerSetTimerID_Priv:                            \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTimerSetTimerIDImpl                        \n"
+                " MPU_vTimerSetTimerID_Unpriv:                          \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTimerSetTimerIDImpl                       \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerIsTimerActiveImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerIsTimerActive_Unpriv                    \n"
+                " MPU_xTimerIsTimerActive_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerIsTimerActiveImpl                     \n"
+                " MPU_xTimerIsTimerActive_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerIsTimerActiveImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetTimerDaemonTaskHandleImpl        \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv         \n"
+                " MPU_xTimerGetTimerDaemonTaskHandle_Priv:              \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerGetTimerDaemonTaskHandleImpl          \n"
+                " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetTimerDaemonTaskHandleImpl         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                                     const BaseType_t xCommandID,
+                                                     const TickType_t xOptionalValue,
+                                                     BaseType_t * const pxHigherPriorityTaskWoken,
+                                                     const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                                     const BaseType_t xCommandID,
+                                                     const TickType_t xOptionalValue,
+                                                     BaseType_t * const pxHigherPriorityTaskWoken,
+                                                     const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                               \n"
+                " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
+                "                                                               \n"
+                " push {r0}                                                     \n"
+                " mrs r0, control                                               \n"
+                " tst r0, #1                                                    \n"
+                " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
+                " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
+                "     pop {r0}                                                  \n"
+                "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
+                " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
+                "     pop {r0}                                                  \n"
+                "     svc %0                                                    \n"
+                "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
+                "     svc %1                                                    \n"
+                "     bx lr                                                     \n"
+                "                                                               \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pcTimerGetNameImpl                        \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_pcTimerGetName_Unpriv                         \n"
+                " MPU_pcTimerGetName_Priv:                              \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_pcTimerGetNameImpl                          \n"
+                " MPU_pcTimerGetName_Unpriv:                            \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pcTimerGetNameImpl                         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
+                                      const BaseType_t uxAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
+                                      const BaseType_t uxAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTimerSetReloadModeImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTimerSetReloadMode_Unpriv                    \n"
+                " MPU_vTimerSetReloadMode_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTimerSetReloadModeImpl                     \n"
+                " MPU_vTimerSetReloadMode_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTimerSetReloadModeImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetReloadModeImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerGetReloadMode_Unpriv                    \n"
+                " MPU_xTimerGetReloadMode_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerGetReloadModeImpl                     \n"
+                " MPU_xTimerGetReloadMode_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetReloadModeImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTimerGetReloadModeImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTimerGetReloadMode_Unpriv                   \n"
+                " MPU_uxTimerGetReloadMode_Priv:                        \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTimerGetReloadModeImpl                    \n"
+                " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTimerGetReloadModeImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetPeriodImpl                       \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerGetPeriod_Unpriv                        \n"
+                " MPU_xTimerGetPeriod_Priv:                             \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerGetPeriodImpl                         \n"
+                " MPU_xTimerGetPeriod_Unpriv:                           \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetPeriodImpl                        \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetExpiryTimeImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerGetExpiryTime_Unpriv                    \n"
+                " MPU_xTimerGetExpiryTime_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerGetExpiryTimeImpl                     \n"
+                " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetExpiryTimeImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         const BaseType_t xClearOnExit,
+                                         const BaseType_t xWaitForAllBits,
+                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         const BaseType_t xClearOnExit,
+                                         const BaseType_t xWaitForAllBits,
                                          TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueTakeMutexRecursiveImpl              \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueTakeMutexRecursive_Unpriv               \n"
-        " MPU_xQueueTakeMutexRecursive_Priv:                    \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueTakeMutexRecursiveImpl                \n"
-        " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueTakeMutexRecursiveImpl               \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupWaitBitsImpl                   \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
+            " MPU_xEventGroupWaitBits_Priv:                         \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xEventGroupWaitBitsImpl                     \n"
+            " MPU_xEventGroupWaitBits_Unpriv:                       \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupWaitBitsImpl                    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                          const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueGiveMutexRecursiveImpl              \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueGiveMutexRecursive_Unpriv               \n"
-        " MPU_xQueueGiveMutexRecursive_Priv:                    \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueGiveMutexRecursiveImpl                \n"
-        " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueGiveMutexRecursiveImpl               \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                          const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupClearBitsImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xEventGroupClearBits_Unpriv                   \n"
+            " MPU_xEventGroupClearBits_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xEventGroupClearBitsImpl                    \n"
+            " MPU_xEventGroupClearBits_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupClearBitsImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_QUEUE_SETS == 1 )
+    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                        const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
-                                                const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
-                                                const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueSelectFromSetImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueSelectFromSet_Unpriv                    \n"
-        " MPU_xQueueSelectFromSet_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueSelectFromSetImpl                     \n"
-        " MPU_xQueueSelectFromSet_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueSelectFromSetImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                        const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupSetBitsImpl                    \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xEventGroupSetBits_Unpriv                     \n"
+            " MPU_xEventGroupSetBits_Priv:                          \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xEventGroupSetBitsImpl                      \n"
+            " MPU_xEventGroupSetBits_Unpriv:                        \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupSetBitsImpl                     \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_QUEUE_SETS == 1 )
-
-BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
-                               QueueSetHandle_t xQueueSet ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
-                               QueueSetHandle_t xQueueSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueAddToSetImpl                        \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueAddToSet_Unpriv                         \n"
-        " MPU_xQueueAddToSet_Priv:                              \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueAddToSetImpl                          \n"
-        " MPU_xQueueAddToSet_Unpriv:                            \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueAddToSetImpl                         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_QUEUE_SETS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
-                              const char * pcName ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
-                              const char * pcName ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vQueueAddToRegistryImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vQueueAddToRegistry_Unpriv                    \n"
-        " MPU_vQueueAddToRegistry_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vQueueAddToRegistryImpl                     \n"
-        " MPU_vQueueAddToRegistry_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vQueueAddToRegistryImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vQueueUnregisterQueueImpl                 \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vQueueUnregisterQueue_Unpriv                  \n"
-        " MPU_vQueueUnregisterQueue_Priv:                       \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vQueueUnregisterQueueImpl                   \n"
-        " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vQueueUnregisterQueueImpl                  \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pcQueueGetNameImpl                        \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_pcQueueGetName_Unpriv                         \n"
-        " MPU_pcQueueGetName_Priv:                              \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_pcQueueGetNameImpl                          \n"
-        " MPU_pcQueueGetName_Unpriv:                            \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pcQueueGetNameImpl                         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pvTimerGetTimerIDImpl                     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_pvTimerGetTimerID_Unpriv                      \n"
-        " MPU_pvTimerGetTimerID_Priv:                           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_pvTimerGetTimerIDImpl                       \n"
-        " MPU_pvTimerGetTimerID_Unpriv:                         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pvTimerGetTimerIDImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
-                           void * pvNewID ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
-                           void * pvNewID ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTimerSetTimerIDImpl                      \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTimerSetTimerID_Unpriv                       \n"
-        " MPU_vTimerSetTimerID_Priv:                            \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTimerSetTimerIDImpl                        \n"
-        " MPU_vTimerSetTimerID_Unpriv:                          \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTimerSetTimerIDImpl                       \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerIsTimerActiveImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTimerIsTimerActive_Unpriv                    \n"
-        " MPU_xTimerIsTimerActive_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerIsTimerActiveImpl                     \n"
-        " MPU_xTimerIsTimerActive_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerIsTimerActiveImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetTimerDaemonTaskHandleImpl        \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv         \n"
-        " MPU_xTimerGetTimerDaemonTaskHandle_Priv:              \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerGetTimerDaemonTaskHandleImpl          \n"
-        " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetTimerDaemonTaskHandleImpl         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                             const BaseType_t xCommandID,
-                                             const TickType_t xOptionalValue,
-                                             BaseType_t * const pxHigherPriorityTaskWoken,
-                                             const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                             const BaseType_t xCommandID,
-                                             const TickType_t xOptionalValue,
-                                             BaseType_t * const pxHigherPriorityTaskWoken,
-                                             const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                               \n"
-        " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
-        "                                                               \n"
-        " push {r0}                                                     \n"
-        " mrs r0, control                                               \n"
-        " tst r0, #1                                                    \n"
-        " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
-        " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
-        "     pop {r0}                                                  \n"
-        "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
-        " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
-        "     pop {r0}                                                  \n"
-        "     svc %0                                                    \n"
-        "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
-        "     svc %1                                                    \n"
-        "     bx lr                                                     \n"
-        "                                                               \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pcTimerGetNameImpl                        \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_pcTimerGetName_Unpriv                         \n"
-        " MPU_pcTimerGetName_Priv:                              \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_pcTimerGetNameImpl                          \n"
-        " MPU_pcTimerGetName_Unpriv:                            \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pcTimerGetNameImpl                         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                              const BaseType_t uxAutoReload ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                              const BaseType_t uxAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTimerSetReloadModeImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTimerSetReloadMode_Unpriv                    \n"
-        " MPU_vTimerSetReloadMode_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTimerSetReloadModeImpl                     \n"
-        " MPU_vTimerSetReloadMode_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTimerSetReloadModeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetReloadModeImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTimerGetReloadMode_Unpriv                    \n"
-        " MPU_xTimerGetReloadMode_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerGetReloadModeImpl                     \n"
-        " MPU_xTimerGetReloadMode_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetReloadModeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTimerGetReloadModeImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTimerGetReloadMode_Unpriv                   \n"
-        " MPU_uxTimerGetReloadMode_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTimerGetReloadModeImpl                    \n"
-        " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTimerGetReloadModeImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetPeriodImpl                       \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTimerGetPeriod_Unpriv                        \n"
-        " MPU_xTimerGetPeriod_Priv:                             \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerGetPeriodImpl                         \n"
-        " MPU_xTimerGetPeriod_Unpriv:                           \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetPeriodImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetExpiryTimeImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTimerGetExpiryTime_Unpriv                    \n"
-        " MPU_xTimerGetExpiryTime_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerGetExpiryTimeImpl                     \n"
-        " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetExpiryTimeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                     const EventBits_t uxBitsToSet,
                                      const EventBits_t uxBitsToWaitFor,
-                                     const BaseType_t xClearOnExit,
-                                     const BaseType_t xWaitForAllBits,
-                                     TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                     const EventBits_t uxBitsToSet,
                                      const EventBits_t uxBitsToWaitFor,
-                                     const BaseType_t xClearOnExit,
-                                     const BaseType_t xWaitForAllBits,
                                      TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupWaitBitsImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
-        " MPU_xEventGroupWaitBits_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xEventGroupWaitBitsImpl                     \n"
-        " MPU_xEventGroupWaitBits_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupWaitBitsImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupSyncImpl                       \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xEventGroupSync_Unpriv                        \n"
+            " MPU_xEventGroupSync_Priv:                             \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xEventGroupSyncImpl                         \n"
+            " MPU_xEventGroupSync_Unpriv:                           \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupSyncImpl                        \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                      const EventBits_t uxBitsToClear ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                      const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupClearBitsImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xEventGroupClearBits_Unpriv                   \n"
-        " MPU_xEventGroupClearBits_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xEventGroupClearBitsImpl                    \n"
-        " MPU_xEventGroupClearBits_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupClearBitsImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxEventGroupGetNumberImpl                 \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxEventGroupGetNumber_Unpriv                  \n"
+                " MPU_uxEventGroupGetNumber_Priv:                       \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxEventGroupGetNumberImpl                   \n"
+                " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxEventGroupGetNumberImpl                  \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
 /*-----------------------------------------------------------*/
 
-EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                    const EventBits_t uxBitsToSet ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                    const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupSetBitsImpl                    \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xEventGroupSetBits_Unpriv                     \n"
-        " MPU_xEventGroupSetBits_Priv:                          \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xEventGroupSetBitsImpl                      \n"
-        " MPU_xEventGroupSetBits_Unpriv:                        \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupSetBitsImpl                     \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vEventGroupSetNumber( void * xEventGroup,
+                                       UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vEventGroupSetNumber( void * xEventGroup,
+                                       UBaseType_t uxEventGroupNumber ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vEventGroupSetNumberImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vEventGroupSetNumber_Unpriv                   \n"
+                " MPU_vEventGroupSetNumber_Priv:                        \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vEventGroupSetNumberImpl                    \n"
+                " MPU_vEventGroupSetNumber_Unpriv:                      \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vEventGroupSetNumberImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
 /*-----------------------------------------------------------*/
 
-EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                 const EventBits_t uxBitsToSet,
-                                 const EventBits_t uxBitsToWaitFor,
-                                 TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                  const void * pvTxData,
+                                  size_t xDataLengthBytes,
+                                  TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                 const EventBits_t uxBitsToSet,
-                                 const EventBits_t uxBitsToWaitFor,
-                                 TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupSyncImpl                       \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xEventGroupSync_Unpriv                        \n"
-        " MPU_xEventGroupSync_Priv:                             \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xEventGroupSyncImpl                         \n"
-        " MPU_xEventGroupSync_Unpriv:                           \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupSyncImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                  const void * pvTxData,
+                                  size_t xDataLengthBytes,
+                                  TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferSendImpl                     \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferSend_Unpriv                      \n"
+            " MPU_xStreamBufferSend_Priv:                           \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferSendImpl                       \n"
+            " MPU_xStreamBufferSend_Unpriv:                         \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferSendImpl                      \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                     void * pvRxData,
+                                     size_t xBufferLengthBytes,
+                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxEventGroupGetNumberImpl                 \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxEventGroupGetNumber_Unpriv                  \n"
-        " MPU_uxEventGroupGetNumber_Priv:                       \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxEventGroupGetNumberImpl                   \n"
-        " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxEventGroupGetNumberImpl                  \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                     void * pvRxData,
+                                     size_t xBufferLengthBytes,
+                                     TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferReceiveImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferReceive_Unpriv                   \n"
+            " MPU_xStreamBufferReceive_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferReceiveImpl                    \n"
+            " MPU_xStreamBufferReceive_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferReceiveImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vEventGroupSetNumber( void * xEventGroup,
-                               UBaseType_t uxEventGroupNumber ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vEventGroupSetNumber( void * xEventGroup,
-                               UBaseType_t uxEventGroupNumber ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vEventGroupSetNumberImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vEventGroupSetNumber_Unpriv                   \n"
-        " MPU_vEventGroupSetNumber_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vEventGroupSetNumberImpl                    \n"
-        " MPU_vEventGroupSetNumber_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vEventGroupSetNumberImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferIsFullImpl                   \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
+            " MPU_xStreamBufferIsFull_Priv:                         \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferIsFullImpl                     \n"
+            " MPU_xStreamBufferIsFull_Unpriv:                       \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferIsFullImpl                    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                              const void * pvTxData,
-                              size_t xDataLengthBytes,
-                              TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                              const void * pvTxData,
-                              size_t xDataLengthBytes,
-                              TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferSendImpl                     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferSend_Unpriv                      \n"
-        " MPU_xStreamBufferSend_Priv:                           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferSendImpl                       \n"
-        " MPU_xStreamBufferSend_Unpriv:                         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferSendImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
+            " MPU_xStreamBufferIsEmpty_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferIsEmptyImpl                    \n"
+            " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferIsEmptyImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                 void * pvRxData,
-                                 size_t xBufferLengthBytes,
-                                 TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                 void * pvRxData,
-                                 size_t xBufferLengthBytes,
-                                 TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferReceiveImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferReceive_Unpriv                   \n"
-        " MPU_xStreamBufferReceive_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferReceiveImpl                    \n"
-        " MPU_xStreamBufferReceive_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferReceiveImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
+            " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
+            " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferSpacesAvailableImpl           \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferIsFullImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
-        " MPU_xStreamBufferIsFull_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferIsFullImpl                     \n"
-        " MPU_xStreamBufferIsFull_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferIsFullImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
+            " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferBytesAvailableImpl             \n"
+            " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferBytesAvailableImpl            \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                 size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
-        " MPU_xStreamBufferIsEmpty_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferIsEmptyImpl                    \n"
-        " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferIsEmptyImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                 size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
+            " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
+            " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferSetTriggerLevelImpl           \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
-        " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
-        " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferSpacesAvailableImpl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
-size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
-        " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferBytesAvailableImpl             \n"
-        " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferBytesAvailableImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                             size_t xTriggerLevel ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                             size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
-        " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
-        " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferSetTriggerLevelImpl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
-size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
-        " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
-        " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferNextMessageLengthBytesImpl    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
+            " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
+            " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferNextMessageLengthBytesImpl    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
diff --git a/portable/GCC/ARM_CM33/non_secure/port.c b/portable/GCC/ARM_CM33/non_secure/port.c
index 80410e82e..c940c304b 100644
--- a/portable/GCC/ARM_CM33/non_secure/port.c
+++ b/portable/GCC/ARM_CM33/non_secure/port.c
@@ -110,8 +110,8 @@
 /**
  * @brief Constants used during system call enter and exit.
  */
-#define portPSR_STACK_PADDING_MASK                ( 1UL << 9UL )
-#define portEXC_RETURN_STACK_FRAME_TYPE_MASK      ( 1UL << 4UL )
+#define portPSR_STACK_PADDING_MASK              ( 1UL << 9UL )
+#define portEXC_RETURN_STACK_FRAME_TYPE_MASK    ( 1UL << 4UL )
 /*-----------------------------------------------------------*/
 
 /**
@@ -133,81 +133,81 @@
 /**
  * @brief Offsets in the stack to the parameters when inside the SVC handler.
  */
-#define portOFFSET_TO_LR                    ( 5 )
-#define portOFFSET_TO_PC                    ( 6 )
-#define portOFFSET_TO_PSR                   ( 7 )
+#define portOFFSET_TO_LR     ( 5 )
+#define portOFFSET_TO_PC     ( 6 )
+#define portOFFSET_TO_PSR    ( 7 )
 /*-----------------------------------------------------------*/
 
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                      ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                      ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                       ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                      ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                      ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                     ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                     ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK  ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK               ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK               ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK               ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK               ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK               ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK               ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK               ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK               ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0              ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1              ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2              ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3              ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4              ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5              ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6              ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7              ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE            ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT      ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                      ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE             ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -216,11 +216,11 @@
 
 /* Extract last address of the MPU region as encoded in the
  * RLAR (Region Limit Address Register) value. */
-#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar )  \
+#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar ) \
     ( ( ( rlar ) & portMPU_RLAR_ADDRESS_MASK ) | ~portMPU_RLAR_ADDRESS_MASK )
 
 /* Does addr lies within [start, end] address range? */
-#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end )    \
+#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \
     ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) )
 
 /* Is the access request satisfied by the available permissions? */
@@ -422,54 +422,57 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the system call stack so that upon returning from
-     * SVC, the system call stack is used.
-     *
-     * It is used for the system calls with up to 4 parameters.
-     *
-     * @param pulTaskStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the system call stack so that upon returning from
+ * SVC, the system call stack is used.
+ *
+ * It is used for the system calls with up to 4 parameters.
+ *
+ * @param pulTaskStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallEnter( uint32_t * pulTaskStack,
+                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the system call stack so that upon returning from
-     * SVC, the system call stack is used.
-     *
-     * It is used for the system calls with 5 parameters.
-     *
-     * @param pulTaskStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the system call stack so that upon returning from
+ * SVC, the system call stack is used.
+ *
+ * It is used for the system calls with 5 parameters.
+ *
+ * @param pulTaskStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallEnter_1( uint32_t * pulTaskStack,
+                             uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the task stack so that upon returning from
-     * SVC, the task stack is used again.
-     *
-     * @param pulSystemCallStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the task stack so that upon returning from
+ * SVC, the task stack is used again.
+ *
+ * @param pulSystemCallStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallExit( uint32_t * pulSystemCallStack,
+                          uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Checks whether or not the calling task is privileged.
-     *
-     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
-     */
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
     BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
 
 #endif /* configENABLE_MPU == 1 */
@@ -1086,18 +1089,18 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             vRestoreContextOfFirstTask();
             break;
 
-        #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
-            case portSVC_RAISE_PRIVILEGE:
+            #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+                case portSVC_RAISE_PRIVILEGE:
 
-                /* Only raise the privilege, if the svc was raised from any of
-                 * the system calls. */
-                if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
-                    ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
-                {
-                    vRaisePrivilege();
-                }
-                break;
-        #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+                    /* Only raise the privilege, if the svc was raised from any of
+                     * the system calls. */
+                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+                    {
+                        vRaisePrivilege();
+                    }
+                    break;
+            #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
         default:
             /* Incorrect SVC call. */
@@ -1108,513 +1111,526 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulSystemCallStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallEnter( uint32_t * pulTaskStack,
+                           uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulSystemCallStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        /* This is not NULL only for the duration of the system call. */
-        configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+        #if defined( __ARMCC_VERSION )
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+
+            /* This is not NULL only for the duration of the system call. */
+            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the system call stack for the stack frame. */
+            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulSystemCallStack[ i ] = pulTaskStack[ i ];
+            }
+
+            /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
+             * restore it when we exit from the system call. */
+            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* Use the pulSystemCallStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+
+            /* Remember the location where we should copy the stack frame when we exit from
+             * the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+
+            /* Record if the hardware used padding to force the stack pointer
+             * to be double word aligned. */
+            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
+            {
+                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
             }
+
+            /* We ensure in pxPortInitialiseStack that the system call stack is
+             * double word aligned and therefore, there is no need of padding.
+             * Clear the bit[9] of stacked xPSR. */
+            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
+
+            /* Raise the privilege for the duration of the system call. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " bics r0, r1         \n" /* Clear nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the system call stack for the stack frame. */
-        pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulSystemCallStack[ i ] = pulTaskStack[ i ];
-        }
-
-        /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
-         * restore it when we exit from the system call. */
-        pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-        __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* Use the pulSystemCallStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-
-        /* Remember the location where we should copy the stack frame when we exit from
-         * the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-        /* Record if the hardware used padding to force the stack pointer
-         * to be double word aligned. */
-        if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-        {
-            pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-        }
-        else
-        {
-            pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-        }
-
-        /* We ensure in pxPortInitialiseStack that the system call stack is
-         * double word aligned and therefore, there is no need of padding.
-         * Clear the bit[9] of stacked xPSR. */
-        pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-        /* Raise the privilege for the duration of the system call. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " bics r0, r1         \n" /* Clear nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulSystemCallStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallEnter_1( uint32_t * pulTaskStack,
+                             uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulSystemCallStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        /* This is not NULL only for the duration of the system call. */
-        configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+        #if defined( __ARMCC_VERSION )
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+
+            /* This is not NULL only for the duration of the system call. */
+            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the system call stack for the stack frame and
+             * the parameter passed on the stack. We only need to copy one
+             * parameter but we still reserve 2 spaces to keep the stack
+             * double word aligned. */
+            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulSystemCallStack[ i ] = pulTaskStack[ i ];
+            }
+
+            /* Copy the parameter which is passed the stack. */
+            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
+            {
+                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
+
+                /* Record if the hardware used padding to force the stack pointer
+                 * to be double word aligned. */
+                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
+
+                /* Record if the hardware used padding to force the stack pointer
+                 * to be double word aligned. */
+                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
             }
+
+            /* Store the value of the LR and PSPLIM registers before the SVC was raised.
+             * We need to restore it when we exit from the system call. */
+            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* Use the pulSystemCallStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+
+            /* Remember the location where we should copy the stack frame when we exit from
+             * the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+
+            /* We ensure in pxPortInitialiseStack that the system call stack is
+             * double word aligned and therefore, there is no need of padding.
+             * Clear the bit[9] of stacked xPSR. */
+            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
+
+            /* Raise the privilege for the duration of the system call. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " bics r0, r1         \n" /* Clear nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the system call stack for the stack frame and
-         * the parameter passed on the stack. We only need to copy one
-         * parameter but we still reserve 2 spaces to keep the stack
-         * double word aligned. */
-        pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulSystemCallStack[ i ] = pulTaskStack[ i ];
-        }
-
-        /* Copy the parameter which is passed the stack. */
-        if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-        {
-            pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
-            /* Record if the hardware used padding to force the stack pointer
-             * to be double word aligned. */
-            pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-        }
-        else
-        {
-            pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
-            /* Record if the hardware used padding to force the stack pointer
-             * to be double word aligned. */
-            pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-        }
-
-        /* Store the value of the LR and PSPLIM registers before the SVC was raised.
-         * We need to restore it when we exit from the system call. */
-        pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-        __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* Use the pulSystemCallStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-
-        /* Remember the location where we should copy the stack frame when we exit from
-         * the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-        /* We ensure in pxPortInitialiseStack that the system call stack is
-         * double word aligned and therefore, there is no need of padding.
-         * Clear the bit[9] of stacked xPSR. */
-        pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-        /* Raise the privilege for the duration of the system call. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " bics r0, r1         \n" /* Clear nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulTaskStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallExit( uint32_t * pulSystemCallStack,
+                          uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulTaskStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+        #if defined( __ARMCC_VERSION )
+
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the task stack for the stack frame. */
+            pulTaskStack = pulTaskStack - ulStackFrameSize;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulTaskStack[ i ] = pulSystemCallStack[ i ];
+            }
+
+            /* Use the pulTaskStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
+
+            /* Restore the LR and PSPLIM to what they were at the time of
+             * system call entry. */
+            pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* If the hardware used padding to force the stack pointer
+             * to be double word aligned, set the stacked xPSR bit[9],
+             * otherwise clear it. */
+            if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG )
+            {
+                pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
             }
+
+            /* This is not NULL only for the duration of the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
+
+            /* Drop the privilege before returning to the thread mode. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " orrs r0, r1         \n" /* Set nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the task stack for the stack frame. */
-        pulTaskStack = pulTaskStack - ulStackFrameSize;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulTaskStack[ i ] = pulSystemCallStack[ i ];
-        }
-
-        /* Use the pulTaskStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
-
-        /* Restore the LR and PSPLIM to what they were at the time of
-         * system call entry. */
-        pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* If the hardware used padding to force the stack pointer
-         * to be double word aligned, set the stacked xPSR bit[9],
-         * otherwise clear it. */
-        if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG )
-        {
-            pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK;
-        }
-        else
-        {
-            pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-        }
-
-        /* This is not NULL only for the duration of the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
-
-        /* Drop the privilege before returning to the thread mode. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " orrs r0, r1         \n" /* Set nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */
-{
-    BaseType_t xTaskIsPrivileged = pdFALSE;
-    const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
-
-    if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+    BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */
     {
-        xTaskIsPrivileged = pdTRUE;
-    }
+        BaseType_t xTaskIsPrivileged = pdFALSE;
+        const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
 
-    return xTaskIsPrivileged;
-}
+        if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+        {
+            xTaskIsPrivileged = pdTRUE;
+        }
+
+        return xTaskIsPrivileged;
+    }
 
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
-#if( configENABLE_MPU == 1 )
+#if ( configENABLE_MPU == 1 )
 
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     StackType_t * pxEndOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters,
-                                     BaseType_t xRunPrivileged,
-                                     xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
-{
-    uint32_t ulIndex = 0;
-
-    xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
-    ulIndex++;
-
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
-    ulIndex++;
-
-    #if ( configENABLE_TRUSTZONE == 1 )
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters,
+                                         BaseType_t xRunPrivileged,
+                                         xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
     {
-        xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT;  /* xSecureContext. */
+        uint32_t ulIndex = 0;
+
+        xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
         ulIndex++;
-    }
-    #endif /* configENABLE_TRUSTZONE */
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
-    ulIndex++;
-    if( xRunPrivileged == pdTRUE )
-    {
-        xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */
         ulIndex++;
-    }
-    else
-    {
-        xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */
         ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
+        ulIndex++;
+
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters;            /* r0. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x01010101;                           /* r1. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x02020202;                           /* r2. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x03030303;                           /* r3. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x12121212;                           /* r12. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode;                  /* PC. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR;                     /* xPSR. */
+        ulIndex++;
+
+        #if ( configENABLE_TRUSTZONE == 1 )
+        {
+            xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT; /* xSecureContext. */
+            ulIndex++;
+        }
+        #endif /* configENABLE_TRUSTZONE */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
+        ulIndex++;
+
+        if( xRunPrivileged == pdTRUE )
+        {
+            xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
+            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+            ulIndex++;
+        }
+        else
+        {
+            xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
+            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+            ulIndex++;
+        }
+
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
+        ulIndex++;
+
+        #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+        {
+            /* Ensure that the system call stack is double word aligned. */
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] );
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) &
+                                                                                     ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
+
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] );
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) +
+                                                                                            ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) &
+                                                                                          ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
+
+            /* This is not NULL only for the duration of a system call. */
+            xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL;
+        }
+        #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
+
+        return &( xMPUSettings->ulContext[ ulIndex ] );
     }
-    xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
-    ulIndex++;
-
-    #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
-    {
-        /* Ensure that the system call stack is double word aligned. */
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] );
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) &
-                                                                                 ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
-
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] );
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) +
-                                                                                        ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) &
-                                                                                      ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
-
-        /* This is not NULL only for the duration of a system call. */
-        xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL;
-    }
-    #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
-
-    return &( xMPUSettings->ulContext[ ulIndex ] );
-}
 
 #else /* configENABLE_MPU */
 
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     StackType_t * pxEndOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters ) /* PRIVILEGED_FUNCTION */
-{
-    /* Simulate the stack frame as it would be created by a context switch
-     * interrupt. */
-    #if ( portPRELOAD_REGISTERS == 0 )
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters ) /* PRIVILEGED_FUNCTION */
     {
-        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-        pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
-        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-        pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
-        *pxTopOfStack = portINITIAL_EXC_RETURN;
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
-
-        #if ( configENABLE_TRUSTZONE == 1 )
+        /* Simulate the stack frame as it would be created by a context switch
+         * interrupt. */
+        #if ( portPRELOAD_REGISTERS == 0 )
         {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
-        }
-        #endif /* configENABLE_TRUSTZONE */
-    }
-    #else /* portPRELOAD_REGISTERS */
-    {
-        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
-        pxTopOfStack--;
-        *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
+            pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
+            *pxTopOfStack = portINITIAL_EXC_RETURN;
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+            #if ( configENABLE_TRUSTZONE == 1 )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+            }
+            #endif /* configENABLE_TRUSTZONE */
+        }
+        #else /* portPRELOAD_REGISTERS */
         {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
-        }
-        #endif /* configENABLE_TRUSTZONE */
-    }
-    #endif /* portPRELOAD_REGISTERS */
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
+            pxTopOfStack--;
+            *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack;            /* Slot used to hold this task's PSPLIM value. */
 
-    return pxTopOfStack;
-}
+            #if ( configENABLE_TRUSTZONE == 1 )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+            }
+            #endif /* configENABLE_TRUSTZONE */
+        }
+        #endif /* portPRELOAD_REGISTERS */
+
+        return pxTopOfStack;
+    }
 
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM33/non_secure/portasm.c b/portable/GCC/ARM_CM33/non_secure/portasm.c
index f7ec7d9c0..ba8f6c62d 100644
--- a/portable/GCC/ARM_CM33/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM33/non_secure/portasm.c
@@ -42,116 +42,116 @@
 
 #if ( configENABLE_MPU == 1 )
 
-void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        " .syntax unified                                 \n"
-        "                                                 \n"
-        " program_mpu_first_task:                         \n"
-        "    ldr r3, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB. */
-        "                                                 \n"
-        "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-        "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
-        "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
-        "    str r2, [r1]                                 \n" /* Disable MPU. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
-        "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-        "    ldr r2, xMAIR0Const2                         \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-        "    str r1, [r2]                                 \n" /* Program MAIR0. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-        "    ldr r1, xRNRConst2                           \n" /* r1 = 0xe000ed98 [Location of RNR]. */
-        "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "                                                 \n"
-        "    movs r3, #4                                  \n" /* r3 = 4. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 4. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-        "                                                 \n"
-        #if ( configTOTAL_MPU_REGIONS == 16 )
-        "    movs r3, #8                                  \n" /* r3 = 8. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 8. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-        "    movs r3, #12                                 \n" /* r3 = 12. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 12. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-        #endif /* configTOTAL_MPU_REGIONS == 16 */
-        "                                                 \n"
-        "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
-        "    orr r2, #1                                   \n" /* r2 = r1 | 1 i.e. Set the bit 0 in r2. */
-        "    str r2, [r1]                                 \n" /* Enable MPU. */
-        "    dsb                                          \n" /* Force memory writes before continuing. */
-        "                                                 \n"
-        " restore_context_first_task:                     \n"
-        "    ldr r3, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r1, [r3]                                 \n" /* r1 = pxCurrentTCB.*/
-        "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
-        "                                                 \n"
-        " restore_special_regs_first_task:                \n"
-        "    ldmdb r2!, {r0, r3-r5, lr}                   \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
-        "    msr psp, r3                                  \n"
-        "    msr psplim, r4                               \n"
-        "    msr control, r5                              \n"
-        "    ldr r4, xSecureContextConst2                 \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-        "    str r0, [r4]                                 \n" /* Restore xSecureContext. */
-        "                                                 \n"
-        " restore_general_regs_first_task:                \n"
-        "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
-        "    stmia r3!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
-        "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 restored. */
-        "                                                 \n"
-        " restore_context_done_first_task:                \n"
-        "    str r2, [r1]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
-        "    mov r0, #0                                   \n"
-        "    msr basepri, r0                              \n" /* Ensure that interrupts are enabled when the first task starts. */
-        "    bx lr                                        \n"
-        "                                                 \n"
-        " .align 4                                        \n"
-        " pxCurrentTCBConst2: .word pxCurrentTCB          \n"
-        " xSecureContextConst2: .word xSecureContext      \n"
-        " xMPUCTRLConst2: .word 0xe000ed94                \n"
-        " xMAIR0Const2: .word 0xe000edc0                  \n"
-        " xRNRConst2: .word 0xe000ed98                    \n"
-        " xRBARConst2: .word 0xe000ed9c                   \n"
-    );
-}
+    void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                 \n"
+            "                                                 \n"
+            " program_mpu_first_task:                         \n"
+            "    ldr r3, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB. */
+            "                                                 \n"
+            "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
+            "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
+            "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
+            "    str r2, [r1]                                 \n" /* Disable MPU. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
+            "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
+            "    ldr r2, xMAIR0Const2                         \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    str r1, [r2]                                 \n" /* Program MAIR0. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
+            "    ldr r1, xRNRConst2                           \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "                                                 \n"
+            "    movs r3, #4                                  \n" /* r3 = 4. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 4. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "                                                 \n"
+            #if ( configTOTAL_MPU_REGIONS == 16 )
+                "    movs r3, #8                                  \n" /* r3 = 8. */
+                "    str r3, [r1]                                 \n" /* Program RNR = 8. */
+                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
+                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+                "    movs r3, #12                                 \n" /* r3 = 12. */
+                "    str r3, [r1]                                 \n" /* Program RNR = 12. */
+                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
+                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            #endif /* configTOTAL_MPU_REGIONS == 16 */
+            "                                                 \n"
+            "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
+            "    orr r2, #1                                   \n" /* r2 = r1 | 1 i.e. Set the bit 0 in r2. */
+            "    str r2, [r1]                                 \n" /* Enable MPU. */
+            "    dsb                                          \n" /* Force memory writes before continuing. */
+            "                                                 \n"
+            " restore_context_first_task:                     \n"
+            "    ldr r3, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r1, [r3]                                 \n" /* r1 = pxCurrentTCB.*/
+            "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
+            "                                                 \n"
+            " restore_special_regs_first_task:                \n"
+            "    ldmdb r2!, {r0, r3-r5, lr}                   \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
+            "    msr psp, r3                                  \n"
+            "    msr psplim, r4                               \n"
+            "    msr control, r5                              \n"
+            "    ldr r4, xSecureContextConst2                 \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "    str r0, [r4]                                 \n" /* Restore xSecureContext. */
+            "                                                 \n"
+            " restore_general_regs_first_task:                \n"
+            "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
+            "    stmia r3!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
+            "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 restored. */
+            "                                                 \n"
+            " restore_context_done_first_task:                \n"
+            "    str r2, [r1]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
+            "    mov r0, #0                                   \n"
+            "    msr basepri, r0                              \n" /* Ensure that interrupts are enabled when the first task starts. */
+            "    bx lr                                        \n"
+            "                                                 \n"
+            " .align 4                                        \n"
+            " pxCurrentTCBConst2: .word pxCurrentTCB          \n"
+            " xSecureContextConst2: .word xSecureContext      \n"
+            " xMPUCTRLConst2: .word 0xe000ed94                \n"
+            " xMAIR0Const2: .word 0xe000edc0                  \n"
+            " xRNRConst2: .word 0xe000ed98                    \n"
+            " xRBARConst2: .word 0xe000ed9c                   \n"
+        );
+    }
 
 #else /* configENABLE_MPU */
 
-void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "   .syntax unified                                 \n"
-        "                                                   \n"
-        "   ldr  r2, pxCurrentTCBConst2                     \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr  r3, [r2]                                   \n" /* Read pxCurrentTCB. */
-        "   ldr  r0, [r3]                                   \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
-        "                                                   \n"
-        "   ldm  r0!, {r1-r3}                               \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
-        "   ldr  r4, xSecureContextConst2                   \n"
-        "   str  r1, [r4]                                   \n" /* Set xSecureContext to this task's value for the same. */
-        "   msr  psplim, r2                                 \n" /* Set this task's PSPLIM value. */
-        "   movs r1, #2                                     \n" /* r1 = 2. */
-        "   msr  CONTROL, r1                                \n" /* Switch to use PSP in the thread mode. */
-        "   adds r0, #32                                    \n" /* Discard everything up to r0. */
-        "   msr  psp, r0                                    \n" /* This is now the new top of stack to use in the task. */
-        "   isb                                             \n"
-        "   mov  r0, #0                                     \n"
-        "   msr  basepri, r0                                \n" /* Ensure that interrupts are enabled when the first task starts. */
-        "   bx   r3                                         \n" /* Finally, branch to EXC_RETURN. */
-        "   .align 4                                        \n"
-        "pxCurrentTCBConst2: .word pxCurrentTCB             \n"
-        "xSecureContextConst2: .word xSecureContext         \n"
-    );
-}
+    void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            "   .syntax unified                                 \n"
+            "                                                   \n"
+            "   ldr  r2, pxCurrentTCBConst2                     \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr  r3, [r2]                                   \n" /* Read pxCurrentTCB. */
+            "   ldr  r0, [r3]                                   \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+            "                                                   \n"
+            "   ldm  r0!, {r1-r3}                               \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
+            "   ldr  r4, xSecureContextConst2                   \n"
+            "   str  r1, [r4]                                   \n" /* Set xSecureContext to this task's value for the same. */
+            "   msr  psplim, r2                                 \n" /* Set this task's PSPLIM value. */
+            "   movs r1, #2                                     \n" /* r1 = 2. */
+            "   msr  CONTROL, r1                                \n" /* Switch to use PSP in the thread mode. */
+            "   adds r0, #32                                    \n" /* Discard everything up to r0. */
+            "   msr  psp, r0                                    \n" /* This is now the new top of stack to use in the task. */
+            "   isb                                             \n"
+            "   mov  r0, #0                                     \n"
+            "   msr  basepri, r0                                \n" /* Ensure that interrupts are enabled when the first task starts. */
+            "   bx   r3                                         \n" /* Finally, branch to EXC_RETURN. */
+            "   .align 4                                        \n"
+            "pxCurrentTCBConst2: .word pxCurrentTCB             \n"
+            "xSecureContextConst2: .word xSecureContext         \n"
+        );
+    }
 
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
@@ -162,12 +162,12 @@ BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs r0, control                                 \n"/* r0 = CONTROL. */
-        "   tst r0, #1                                      \n"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+        "   mrs r0, control                                 \n" /* r0 = CONTROL. */
+        "   tst r0, #1                                      \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
         "   ite ne                                          \n"
-        "   movne r0, #0                                    \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
-        "   moveq r0, #1                                    \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
-        "   bx lr                                           \n"/* Return. */
+        "   movne r0, #0                                    \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+        "   moveq r0, #1                                    \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+        "   bx lr                                           \n" /* Return. */
         "                                                   \n"
         "   .align 4                                        \n"
         ::: "r0", "memory"
@@ -181,10 +181,10 @@ void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs r0, control                                 \n"/* Read the CONTROL register. */
-        "   bic r0, #1                                      \n"/* Clear the bit 0. */
-        "   msr control, r0                                 \n"/* Write back the new CONTROL value. */
-        "   bx lr                                           \n"/* Return to the caller. */
+        "   mrs r0, control                                 \n" /* Read the CONTROL register. */
+        "   bic r0, #1                                      \n" /* Clear the bit 0. */
+        "   msr control, r0                                 \n" /* Write back the new CONTROL value. */
+        "   bx lr                                           \n" /* Return to the caller. */
         ::: "r0", "memory"
     );
 }
@@ -196,10 +196,10 @@ void vResetPrivilege( void ) /* __attribute__ (( naked )) */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs r0, control                                 \n"/* r0 = CONTROL. */
-        "   orr r0, #1                                      \n"/* r0 = r0 | 1. */
-        "   msr control, r0                                 \n"/* CONTROL = r0. */
-        "   bx lr                                           \n"/* Return to the caller. */
+        "   mrs r0, control                                 \n" /* r0 = CONTROL. */
+        "   orr r0, #1                                      \n" /* r0 = r0 | 1. */
+        "   msr control, r0                                 \n" /* CONTROL = r0. */
+        "   bx lr                                           \n" /* Return to the caller. */
         ::: "r0", "memory"
     );
 }
@@ -211,15 +211,15 @@ void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   ldr r0, xVTORConst                              \n"/* Use the NVIC offset register to locate the stack. */
-        "   ldr r0, [r0]                                    \n"/* Read the VTOR register which gives the address of vector table. */
-        "   ldr r0, [r0]                                    \n"/* The first entry in vector table is stack pointer. */
-        "   msr msp, r0                                     \n"/* Set the MSP back to the start of the stack. */
-        "   cpsie i                                         \n"/* Globally enable interrupts. */
+        "   ldr r0, xVTORConst                              \n" /* Use the NVIC offset register to locate the stack. */
+        "   ldr r0, [r0]                                    \n" /* Read the VTOR register which gives the address of vector table. */
+        "   ldr r0, [r0]                                    \n" /* The first entry in vector table is stack pointer. */
+        "   msr msp, r0                                     \n" /* Set the MSP back to the start of the stack. */
+        "   cpsie i                                         \n" /* Globally enable interrupts. */
         "   cpsie f                                         \n"
         "   dsb                                             \n"
         "   isb                                             \n"
-        "   svc %0                                          \n"/* System call to start the first task. */
+        "   svc %0                                          \n" /* System call to start the first task. */
         "   nop                                             \n"
         "                                                   \n"
         "   .align 4                                        \n"
@@ -235,12 +235,12 @@ uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCT
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs r0, basepri                                 \n"/* r0 = basepri. Return original basepri value. */
-        "   mov r1, %0                                      \n"/* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        "   msr basepri, r1                                 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        "   mrs r0, basepri                                 \n" /* r0 = basepri. Return original basepri value. */
+        "   mov r1, %0                                      \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        "   msr basepri, r1                                 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
         "   dsb                                             \n"
         "   isb                                             \n"
-        "   bx lr                                           \n"/* Return. */
+        "   bx lr                                           \n" /* Return. */
         ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
     );
 }
@@ -252,10 +252,10 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   msr basepri, r0                                 \n"/* basepri = ulMask. */
+        "   msr basepri, r0                                 \n" /* basepri = ulMask. */
         "   dsb                                             \n"
         "   isb                                             \n"
-        "   bx lr                                           \n"/* Return. */
+        "   bx lr                                           \n" /* Return. */
         ::: "memory"
     );
 }
@@ -263,320 +263,320 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
 
 #if ( configENABLE_MPU == 1 )
 
-void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        " .syntax unified                                 \n"
-        " .extern SecureContext_SaveContext               \n"
-        " .extern SecureContext_LoadContext               \n"
-        "                                                 \n"
-        " ldr r3, xSecureContextConst                     \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-        " ldr r0, [r3]                                    \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
-        " ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        " ldr r1, [r3]                                    \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
-        " ldr r2, [r1]                                    \n" /* r2 = Location in TCB where the context should be saved. */
-        "                                                 \n"
-        " cbz r0, save_ns_context                         \n" /* No secure context to save. */
-        " save_s_context:                                 \n"
-        "    push {r0-r2, lr}                             \n"
-        "    bl SecureContext_SaveContext                 \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-        "    pop {r0-r2, lr}                              \n"
-        "                                                 \n"
-        " save_ns_context:                                \n"
-        "    mov r3, lr                                   \n" /* r3 = LR (EXC_RETURN). */
-        "    lsls r3, r3, #25                             \n" /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-        "    bmi save_special_regs                        \n" /* r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
-        "                                                 \n"
-        " save_general_regs:                              \n"
-        "    mrs r3, psp                                  \n"
-        "                                                 \n"
-    #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-        "    add r3, r3, #0x20                            \n" /* Move r3 to location where s0 is saved. */
-        "    tst lr, #0x10                                \n"
-        "    ittt eq                                      \n"
-        "    vstmiaeq r2!, {s16-s31}                      \n" /* Store s16-s31. */
-        "    vldmiaeq r3, {s0-s16}                        \n" /* Copy hardware saved FP context into s0-s16. */
-        "    vstmiaeq r2!, {s0-s16}                       \n" /* Store hardware saved FP context. */
-        "    sub r3, r3, #0x20                            \n" /* Set r3 back to the location of hardware saved context. */
-    #endif /* configENABLE_FPU || configENABLE_MVE */
-        "                                                 \n"
-        "    stmia r2!, {r4-r11}                          \n" /* Store r4-r11. */
-        "    ldmia r3, {r4-r11}                           \n" /* Copy the hardware saved context into r4-r11. */
-        "    stmia r2!, {r4-r11}                          \n" /* Store the hardware saved context. */
-        "                                                 \n"
-        " save_special_regs:                              \n"
-        "    mrs r3, psp                                  \n" /* r3 = PSP. */
-        "    mrs r4, psplim                               \n" /* r4 = PSPLIM. */
-        "    mrs r5, control                              \n" /* r5 = CONTROL. */
-        "    stmia r2!, {r0, r3-r5, lr}                   \n" /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
-        "    str r2, [r1]                                 \n" /* Save the location from where the context should be restored as the first member of TCB. */
-        "                                                 \n"
-        " select_next_task:                               \n"
-        "    mov r0, %0                                   \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
-        "    msr basepri, r0                              \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        "    dsb                                          \n"
-        "    isb                                          \n"
-        "    bl vTaskSwitchContext                        \n"
-        "    mov r0, #0                                   \n" /* r0 = 0. */
-        "    msr basepri, r0                              \n" /* Enable interrupts. */
-        "                                                 \n"
-        " program_mpu:                                    \n"
-        "    ldr r3, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB.*/
-        "                                                 \n"
-        "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-        "    ldr r1, xMPUCTRLConst                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
-        "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
-        "    str r2, [r1]                                 \n" /* Disable MPU. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
-        "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-        "    ldr r2, xMAIR0Const                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-        "    str r1, [r2]                                 \n" /* Program MAIR0. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-        "    ldr r1, xRNRConst                            \n" /* r1 = 0xe000ed98 [Location of RNR]. */
-        "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "                                                 \n"
-        "    movs r3, #4                                  \n" /* r3 = 4. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 4. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-        "                                                 \n"
-        #if ( configTOTAL_MPU_REGIONS == 16 )
-        "    movs r3, #8                                  \n" /* r3 = 8. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 8. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-        "    movs r3, #12                                 \n" /* r3 = 12. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 12. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-        #endif /* configTOTAL_MPU_REGIONS == 16 */
-        "                                                 \n"
-        "   ldr r1, xMPUCTRLConst                         \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
-        "   orr r2, #1                                    \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
-        "   str r2, [r1]                                  \n" /* Enable MPU. */
-        "   dsb                                           \n" /* Force memory writes before continuing. */
-        "                                                 \n"
-        " restore_context:                                \n"
-        "    ldr r3, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r1, [r3]                                 \n" /* r1 = pxCurrentTCB.*/
-        "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
-        "                                                 \n"
-        " restore_special_regs:                           \n"
-        "    ldmdb r2!, {r0, r3-r5, lr}                   \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
-        "    msr psp, r3                                  \n"
-        "    msr psplim, r4                               \n"
-        "    msr control, r5                              \n"
-        "    ldr r4, xSecureContextConst                  \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-        "    str r0, [r4]                                 \n" /* Restore xSecureContext. */
-        "    cbz r0, restore_ns_context                   \n" /* No secure context to restore. */
-        "                                                 \n"
-        " restore_s_context:                              \n"
-        "    push {r1-r3, lr}                             \n"
-        "    bl SecureContext_LoadContext                 \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-        "    pop {r1-r3, lr}                              \n"
-        "                                                 \n"
-        " restore_ns_context:                             \n"
-        "    mov r0, lr                                   \n" /* r0 = LR (EXC_RETURN). */
-        "    lsls r0, r0, #25                             \n" /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-        "    bmi restore_context_done                     \n" /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
-        "                                                 \n"
-        " restore_general_regs:                           \n"
-        "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
-        "    stmia r3!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
-        "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 restored. */
-    #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-        "    tst lr, #0x10                                \n"
-        "    ittt eq                                      \n"
-        "    vldmdbeq r2!, {s0-s16}                       \n" /* s0-s16 contain hardware saved FP context. */
-        "    vstmiaeq r3!, {s0-s16}                       \n" /* Copy hardware saved FP context on the task stack. */
-        "    vldmdbeq r2!, {s16-s31}                      \n" /* Restore s16-s31. */
-    #endif /* configENABLE_FPU || configENABLE_MVE */
-        "                                                 \n"
-        " restore_context_done:                           \n"
-        "    str r2, [r1]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
-        "    bx lr                                        \n"
-        "                                                 \n"
-        " .align 4                                        \n"
-        " pxCurrentTCBConst: .word pxCurrentTCB           \n"
-        " xSecureContextConst: .word xSecureContext       \n"
-        " xMPUCTRLConst: .word 0xe000ed94                 \n"
-        " xMAIR0Const: .word 0xe000edc0                   \n"
-        " xRNRConst: .word 0xe000ed98                     \n"
-        " xRBARConst: .word 0xe000ed9c                    \n"
-        ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
-    );
-}
+    void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                 \n"
+            " .extern SecureContext_SaveContext               \n"
+            " .extern SecureContext_LoadContext               \n"
+            "                                                 \n"
+            " ldr r3, xSecureContextConst                     \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            " ldr r0, [r3]                                    \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+            " ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            " ldr r1, [r3]                                    \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
+            " ldr r2, [r1]                                    \n" /* r2 = Location in TCB where the context should be saved. */
+            "                                                 \n"
+            " cbz r0, save_ns_context                         \n" /* No secure context to save. */
+            " save_s_context:                                 \n"
+            "    push {r0-r2, lr}                             \n"
+            "    bl SecureContext_SaveContext                 \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+            "    pop {r0-r2, lr}                              \n"
+            "                                                 \n"
+            " save_ns_context:                                \n"
+            "    mov r3, lr                                   \n" /* r3 = LR (EXC_RETURN). */
+            "    lsls r3, r3, #25                             \n" /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+            "    bmi save_special_regs                        \n" /* r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
+            "                                                 \n"
+            " save_general_regs:                              \n"
+            "    mrs r3, psp                                  \n"
+            "                                                 \n"
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+                "    add r3, r3, #0x20                            \n" /* Move r3 to location where s0 is saved. */
+                "    tst lr, #0x10                                \n"
+                "    ittt eq                                      \n"
+                "    vstmiaeq r2!, {s16-s31}                      \n" /* Store s16-s31. */
+                "    vldmiaeq r3, {s0-s16}                        \n" /* Copy hardware saved FP context into s0-s16. */
+                "    vstmiaeq r2!, {s0-s16}                       \n" /* Store hardware saved FP context. */
+                "    sub r3, r3, #0x20                            \n" /* Set r3 back to the location of hardware saved context. */
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+            "                                                 \n"
+            "    stmia r2!, {r4-r11}                          \n" /* Store r4-r11. */
+            "    ldmia r3, {r4-r11}                           \n" /* Copy the hardware saved context into r4-r11. */
+            "    stmia r2!, {r4-r11}                          \n" /* Store the hardware saved context. */
+            "                                                 \n"
+            " save_special_regs:                              \n"
+            "    mrs r3, psp                                  \n" /* r3 = PSP. */
+            "    mrs r4, psplim                               \n" /* r4 = PSPLIM. */
+            "    mrs r5, control                              \n" /* r5 = CONTROL. */
+            "    stmia r2!, {r0, r3-r5, lr}                   \n" /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
+            "    str r2, [r1]                                 \n" /* Save the location from where the context should be restored as the first member of TCB. */
+            "                                                 \n"
+            " select_next_task:                               \n"
+            "    mov r0, %0                                   \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
+            "    msr basepri, r0                              \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+            "    dsb                                          \n"
+            "    isb                                          \n"
+            "    bl vTaskSwitchContext                        \n"
+            "    mov r0, #0                                   \n" /* r0 = 0. */
+            "    msr basepri, r0                              \n" /* Enable interrupts. */
+            "                                                 \n"
+            " program_mpu:                                    \n"
+            "    ldr r3, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB.*/
+            "                                                 \n"
+            "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
+            "    ldr r1, xMPUCTRLConst                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
+            "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
+            "    str r2, [r1]                                 \n" /* Disable MPU. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
+            "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
+            "    ldr r2, xMAIR0Const                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    str r1, [r2]                                 \n" /* Program MAIR0. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
+            "    ldr r1, xRNRConst                            \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "                                                 \n"
+            "    movs r3, #4                                  \n" /* r3 = 4. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 4. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "                                                 \n"
+            #if ( configTOTAL_MPU_REGIONS == 16 )
+                "    movs r3, #8                                  \n" /* r3 = 8. */
+                "    str r3, [r1]                                 \n" /* Program RNR = 8. */
+                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+                "    movs r3, #12                                 \n" /* r3 = 12. */
+                "    str r3, [r1]                                 \n" /* Program RNR = 12. */
+                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            #endif /* configTOTAL_MPU_REGIONS == 16 */
+            "                                                 \n"
+            "   ldr r1, xMPUCTRLConst                         \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
+            "   orr r2, #1                                    \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
+            "   str r2, [r1]                                  \n" /* Enable MPU. */
+            "   dsb                                           \n" /* Force memory writes before continuing. */
+            "                                                 \n"
+            " restore_context:                                \n"
+            "    ldr r3, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r1, [r3]                                 \n" /* r1 = pxCurrentTCB.*/
+            "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
+            "                                                 \n"
+            " restore_special_regs:                           \n"
+            "    ldmdb r2!, {r0, r3-r5, lr}                   \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
+            "    msr psp, r3                                  \n"
+            "    msr psplim, r4                               \n"
+            "    msr control, r5                              \n"
+            "    ldr r4, xSecureContextConst                  \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "    str r0, [r4]                                 \n" /* Restore xSecureContext. */
+            "    cbz r0, restore_ns_context                   \n" /* No secure context to restore. */
+            "                                                 \n"
+            " restore_s_context:                              \n"
+            "    push {r1-r3, lr}                             \n"
+            "    bl SecureContext_LoadContext                 \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+            "    pop {r1-r3, lr}                              \n"
+            "                                                 \n"
+            " restore_ns_context:                             \n"
+            "    mov r0, lr                                   \n" /* r0 = LR (EXC_RETURN). */
+            "    lsls r0, r0, #25                             \n" /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+            "    bmi restore_context_done                     \n" /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
+            "                                                 \n"
+            " restore_general_regs:                           \n"
+            "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
+            "    stmia r3!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
+            "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 restored. */
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+                "    tst lr, #0x10                                \n"
+                "    ittt eq                                      \n"
+                "    vldmdbeq r2!, {s0-s16}                       \n" /* s0-s16 contain hardware saved FP context. */
+                "    vstmiaeq r3!, {s0-s16}                       \n" /* Copy hardware saved FP context on the task stack. */
+                "    vldmdbeq r2!, {s16-s31}                      \n" /* Restore s16-s31. */
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+            "                                                 \n"
+            " restore_context_done:                           \n"
+            "    str r2, [r1]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
+            "    bx lr                                        \n"
+            "                                                 \n"
+            " .align 4                                        \n"
+            " pxCurrentTCBConst: .word pxCurrentTCB           \n"
+            " xSecureContextConst: .word xSecureContext       \n"
+            " xMPUCTRLConst: .word 0xe000ed94                 \n"
+            " xMAIR0Const: .word 0xe000edc0                   \n"
+            " xRNRConst: .word 0xe000ed98                     \n"
+            " xRBARConst: .word 0xe000ed9c                    \n"
+            ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+        );
+    }
 
 #else /* configENABLE_MPU */
 
-void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "   .syntax unified                                 \n"
-        "   .extern SecureContext_SaveContext               \n"
-        "   .extern SecureContext_LoadContext               \n"
-        "                                                   \n"
-        "   ldr r3, xSecureContextConst                     \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
-        "   ldr r0, [r3]                                    \n"/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
-        "   ldr r3, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r3]                                    \n"/* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
-        "   mrs r2, psp                                     \n"/* Read PSP in r2. */
-        "                                                   \n"
-        "   cbz r0, save_ns_context                         \n"/* No secure context to save. */
-        "   push {r0-r2, r14}                               \n"
-        "   bl SecureContext_SaveContext                    \n"/* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-        "   pop {r0-r3}                                     \n"/* LR is now in r3. */
-        "   mov lr, r3                                      \n"/* LR = r3. */
-        "   lsls r1, r3, #25                                \n"/* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-        "   bpl save_ns_context                             \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-        "                                                   \n"
-        "   ldr r3, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r3]                                    \n"/* Read pxCurrentTCB.*/
-        "   subs r2, r2, #12                                \n"/* Make space for xSecureContext, PSPLIM and LR on the stack. */
-        "   str r2, [r1]                                    \n"/* Save the new top of stack in TCB. */
-        "   mrs r1, psplim                                  \n"/* r1 = PSPLIM. */
-        "   mov r3, lr                                      \n"/* r3 = LR/EXC_RETURN. */
-        "   stmia r2!, {r0, r1, r3}                         \n"/* Store xSecureContext, PSPLIM and LR on the stack. */
-        "   b select_next_task                              \n"
-        "                                                   \n"
-        " save_ns_context:                                  \n"
-        "   ldr r3, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r3]                                    \n"/* Read pxCurrentTCB. */
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-            "   tst lr, #0x10                               \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
-            "   it eq                                       \n"
-            "   vstmdbeq r2!, {s16-s31}                     \n"/* Store the additional FP context registers which are not saved automatically. */
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-        "   subs r2, r2, #44                                \n"/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
-        "   str r2, [r1]                                    \n"/* Save the new top of stack in TCB. */
-        "   adds r2, r2, #12                                \n"/* r2 = r2 + 12. */
-        "   stm r2, {r4-r11}                                \n"/* Store the registers that are not saved automatically. */
-        "   mrs r1, psplim                                  \n"/* r1 = PSPLIM. */
-        "   mov r3, lr                                      \n"/* r3 = LR/EXC_RETURN. */
-        "   subs r2, r2, #12                                \n"/* r2 = r2 - 12. */
-        "   stmia r2!, {r0, r1, r3}                         \n"/* Store xSecureContext, PSPLIM and LR on the stack. */
-        "                                                   \n"
-        " select_next_task:                                 \n"
-        "   mov r0, %0                                      \n"/* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
-        "   msr basepri, r0                                 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        "   dsb                                             \n"
-        "   isb                                             \n"
-        "   bl vTaskSwitchContext                           \n"
-        "   mov r0, #0                                      \n"/* r0 = 0. */
-        "   msr basepri, r0                                 \n"/* Enable interrupts. */
-        "                                                   \n"
-        "   ldr r3, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r3]                                    \n"/* Read pxCurrentTCB. */
-        "   ldr r2, [r1]                                    \n"/* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
-        "                                                   \n"
-        "   ldmia r2!, {r0, r1, r4}                         \n"/* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
-        "   msr psplim, r1                                  \n"/* Restore the PSPLIM register value for the task. */
-        "   mov lr, r4                                      \n"/* LR = r4. */
-        "   ldr r3, xSecureContextConst                     \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
-        "   str r0, [r3]                                    \n"/* Restore the task's xSecureContext. */
-        "   cbz r0, restore_ns_context                      \n"/* If there is no secure context for the task, restore the non-secure context. */
-        "   ldr r3, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r3]                                    \n"/* Read pxCurrentTCB. */
-        "   push {r2, r4}                                   \n"
-        "   bl SecureContext_LoadContext                    \n"/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-        "   pop {r2, r4}                                    \n"
-        "   mov lr, r4                                      \n"/* LR = r4. */
-        "   lsls r1, r4, #25                                \n"/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-        "   bpl restore_ns_context                          \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-        "   msr psp, r2                                     \n"/* Remember the new top of stack for the task. */
-        "   bx lr                                           \n"
-        "                                                   \n"
-        " restore_ns_context:                               \n"
-        "   ldmia r2!, {r4-r11}                             \n"/* Restore the registers that are not automatically restored. */
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-            "   tst lr, #0x10                               \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
-            "   it eq                                       \n"
-            "   vldmiaeq r2!, {s16-s31}                     \n"/* Restore the additional FP context registers which are not restored automatically. */
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-        "   msr psp, r2                                     \n"/* Remember the new top of stack for the task. */
-        "   bx lr                                           \n"
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "pxCurrentTCBConst: .word pxCurrentTCB              \n"
-        "xSecureContextConst: .word xSecureContext          \n"
-        ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
-    );
-}
+    void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            "   .syntax unified                                 \n"
+            "   .extern SecureContext_SaveContext               \n"
+            "   .extern SecureContext_LoadContext               \n"
+            "                                                   \n"
+            "   ldr r3, xSecureContextConst                     \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "   ldr r0, [r3]                                    \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
+            "   mrs r2, psp                                     \n" /* Read PSP in r2. */
+            "                                                   \n"
+            "   cbz r0, save_ns_context                         \n" /* No secure context to save. */
+            "   push {r0-r2, r14}                               \n"
+            "   bl SecureContext_SaveContext                    \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+            "   pop {r0-r3}                                     \n" /* LR is now in r3. */
+            "   mov lr, r3                                      \n" /* LR = r3. */
+            "   lsls r1, r3, #25                                \n" /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+            "   bpl save_ns_context                             \n" /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+            "                                                   \n"
+            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB.*/
+            "   subs r2, r2, #12                                \n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */
+            "   str r2, [r1]                                    \n" /* Save the new top of stack in TCB. */
+            "   mrs r1, psplim                                  \n" /* r1 = PSPLIM. */
+            "   mov r3, lr                                      \n" /* r3 = LR/EXC_RETURN. */
+            "   stmia r2!, {r0, r1, r3}                         \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
+            "   b select_next_task                              \n"
+            "                                                   \n"
+            " save_ns_context:                                  \n"
+            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+                "   tst lr, #0x10                               \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+                "   it eq                                       \n"
+                "   vstmdbeq r2!, {s16-s31}                     \n" /* Store the additional FP context registers which are not saved automatically. */
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+            "   subs r2, r2, #44                                \n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
+            "   str r2, [r1]                                    \n" /* Save the new top of stack in TCB. */
+            "   adds r2, r2, #12                                \n" /* r2 = r2 + 12. */
+            "   stm r2, {r4-r11}                                \n" /* Store the registers that are not saved automatically. */
+            "   mrs r1, psplim                                  \n" /* r1 = PSPLIM. */
+            "   mov r3, lr                                      \n" /* r3 = LR/EXC_RETURN. */
+            "   subs r2, r2, #12                                \n" /* r2 = r2 - 12. */
+            "   stmia r2!, {r0, r1, r3}                         \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
+            "                                                   \n"
+            " select_next_task:                                 \n"
+            "   mov r0, %0                                      \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
+            "   msr basepri, r0                                 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+            "   dsb                                             \n"
+            "   isb                                             \n"
+            "   bl vTaskSwitchContext                           \n"
+            "   mov r0, #0                                      \n" /* r0 = 0. */
+            "   msr basepri, r0                                 \n" /* Enable interrupts. */
+            "                                                   \n"
+            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
+            "   ldr r2, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
+            "                                                   \n"
+            "   ldmia r2!, {r0, r1, r4}                         \n" /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
+            "   msr psplim, r1                                  \n" /* Restore the PSPLIM register value for the task. */
+            "   mov lr, r4                                      \n" /* LR = r4. */
+            "   ldr r3, xSecureContextConst                     \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "   str r0, [r3]                                    \n" /* Restore the task's xSecureContext. */
+            "   cbz r0, restore_ns_context                      \n" /* If there is no secure context for the task, restore the non-secure context. */
+            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
+            "   push {r2, r4}                                   \n"
+            "   bl SecureContext_LoadContext                    \n" /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+            "   pop {r2, r4}                                    \n"
+            "   mov lr, r4                                      \n" /* LR = r4. */
+            "   lsls r1, r4, #25                                \n" /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+            "   bpl restore_ns_context                          \n" /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+            "   msr psp, r2                                     \n" /* Remember the new top of stack for the task. */
+            "   bx lr                                           \n"
+            "                                                   \n"
+            " restore_ns_context:                               \n"
+            "   ldmia r2!, {r4-r11}                             \n" /* Restore the registers that are not automatically restored. */
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+                "   tst lr, #0x10                               \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+                "   it eq                                       \n"
+                "   vldmiaeq r2!, {s16-s31}                     \n" /* Restore the additional FP context registers which are not restored automatically. */
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+            "   msr psp, r2                                     \n" /* Remember the new top of stack for the task. */
+            "   bx lr                                           \n"
+            "                                                   \n"
+            "   .align 4                                        \n"
+            "pxCurrentTCBConst: .word pxCurrentTCB              \n"
+            "xSecureContextConst: .word xSecureContext          \n"
+            ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+        );
+    }
 
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-   __asm volatile
-    (
-        ".syntax unified                \n"
-        ".extern vPortSVCHandler_C      \n"
-        ".extern vSystemCallEnter       \n"
-        ".extern vSystemCallEnter_1     \n"
-        ".extern vSystemCallExit        \n"
-        "                               \n"
-        "tst lr, #4                     \n"
-        "ite eq                         \n"
-        "mrseq r0, msp                  \n"
-        "mrsne r0, psp                  \n"
-        "                               \n"
-        "ldr r1, [r0, #24]              \n"
-        "ldrb r2, [r1, #-2]             \n"
-        "cmp r2, %0                     \n"
-        "beq syscall_enter              \n"
-        "cmp r2, %1                     \n"
-        "beq syscall_enter_1            \n"
-        "cmp r2, %2                     \n"
-        "beq syscall_exit               \n"
-        "b vPortSVCHandler_C            \n"
-        "                               \n"
-        "syscall_enter:                 \n"
-        "    mov r1, lr                 \n"
-        "    b vSystemCallEnter         \n"
-        "                               \n"
-        "syscall_enter_1:               \n"
-        "    mov r1, lr                 \n"
-        "    b vSystemCallEnter_1       \n"
-        "                               \n"
-        "syscall_exit:                  \n"
-        "    mov r1, lr                 \n"
-        "    b vSystemCallExit          \n"
-        "                               \n"
-        : /* No outputs. */
-        :"i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT )
-        : "r0", "r1", "r2", "memory"
-    );
-}
+    void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            ".syntax unified                \n"
+            ".extern vPortSVCHandler_C      \n"
+            ".extern vSystemCallEnter       \n"
+            ".extern vSystemCallEnter_1     \n"
+            ".extern vSystemCallExit        \n"
+            "                               \n"
+            "tst lr, #4                     \n"
+            "ite eq                         \n"
+            "mrseq r0, msp                  \n"
+            "mrsne r0, psp                  \n"
+            "                               \n"
+            "ldr r1, [r0, #24]              \n"
+            "ldrb r2, [r1, #-2]             \n"
+            "cmp r2, %0                     \n"
+            "beq syscall_enter              \n"
+            "cmp r2, %1                     \n"
+            "beq syscall_enter_1            \n"
+            "cmp r2, %2                     \n"
+            "beq syscall_exit               \n"
+            "b vPortSVCHandler_C            \n"
+            "                               \n"
+            "syscall_enter:                 \n"
+            "    mov r1, lr                 \n"
+            "    b vSystemCallEnter         \n"
+            "                               \n"
+            "syscall_enter_1:               \n"
+            "    mov r1, lr                 \n"
+            "    b vSystemCallEnter_1       \n"
+            "                               \n"
+            "syscall_exit:                  \n"
+            "    mov r1, lr                 \n"
+            "    b vSystemCallExit          \n"
+            "                               \n"
+            : /* No outputs. */
+            : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT )
+            : "r0", "r1", "r2", "memory"
+        );
+    }
 
 #else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
-void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "   .syntax unified                                 \n"
-        "                                                   \n"
-        "   tst lr, #4                                      \n"
-        "   ite eq                                          \n"
-        "   mrseq r0, msp                                   \n"
-        "   mrsne r0, psp                                   \n"
-        "   ldr r1, svchandler_address_const                \n"
-        "   bx r1                                           \n"
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "svchandler_address_const: .word vPortSVCHandler_C  \n"
-    );
-}
+    void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            "   .syntax unified                                 \n"
+            "                                                   \n"
+            "   tst lr, #4                                      \n"
+            "   ite eq                                          \n"
+            "   mrseq r0, msp                                   \n"
+            "   mrsne r0, psp                                   \n"
+            "   ldr r1, svchandler_address_const                \n"
+            "   bx r1                                           \n"
+            "                                                   \n"
+            "   .align 4                                        \n"
+            "svchandler_address_const: .word vPortSVCHandler_C  \n"
+        );
+    }
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
@@ -587,8 +587,8 @@ void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   svc %0                                          \n"/* Secure context is allocated in the supervisor call. */
-        "   bx lr                                           \n"/* Return. */
+        "   svc %0                                          \n" /* Secure context is allocated in the supervisor call. */
+        "   bx lr                                           \n" /* Return. */
         ::"i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"
     );
 }
@@ -600,12 +600,12 @@ void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PR
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   ldr r2, [r0]                                    \n"/* The first item in the TCB is the top of the stack. */
-        "   ldr r1, [r2]                                    \n"/* The first item on the stack is the task's xSecureContext. */
-        "   cmp r1, #0                                      \n"/* Raise svc if task's xSecureContext is not NULL. */
+        "   ldr r2, [r0]                                    \n" /* The first item in the TCB is the top of the stack. */
+        "   ldr r1, [r2]                                    \n" /* The first item on the stack is the task's xSecureContext. */
+        "   cmp r1, #0                                      \n" /* Raise svc if task's xSecureContext is not NULL. */
         "   it ne                                           \n"
-        "   svcne %0                                        \n"/* Secure context is freed in the supervisor call. */
-        "   bx lr                                           \n"/* Return. */
+        "   svcne %0                                        \n" /* Secure context is freed in the supervisor call. */
+        "   bx lr                                           \n" /* Return. */
         ::"i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"
     );
 }
diff --git a/portable/GCC/ARM_CM33/non_secure/portmacro.h b/portable/GCC/ARM_CM33/non_secure/portmacro.h
index 428d38f0a..227327ac8 100644
--- a/portable/GCC/ARM_CM33/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM33/non_secure/portmacro.h
@@ -48,9 +48,9 @@
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME                       "Cortex-M33"
-#define portHAS_ARMV8M_MAIN_EXTENSION       1
-#define portDONT_DISCARD                    __attribute__( ( used ) )
+#define portARCH_NAME                    "Cortex-M33"
+#define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
 /* ARMv8-M common port configurations. */
@@ -60,8 +60,8 @@
 /**
  * @brief Critical section management.
  */
-#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()
-#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )
+#define portDISABLE_INTERRUPTS()    ulSetInterruptMask()
+#define portENABLE_INTERRUPTS()     vClearInterruptMask( 0 )
 /*-----------------------------------------------------------*/
 
 /* *INDENT-OFF* */
diff --git a/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h
index e5ffdb48b..62e462a27 100644
--- a/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h
@@ -81,8 +81,8 @@ typedef unsigned long    UBaseType_t;
     typedef uint32_t     TickType_t;
     #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-     * not need to be guarded with a critical section. */
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
     #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -117,7 +117,7 @@ extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGE
 extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
 
 #if ( configENABLE_TRUSTZONE == 1 )
-    extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize );     /* __attribute__ (( naked )) */
+    extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
     extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
 #endif /* configENABLE_TRUSTZONE */
 
@@ -188,13 +188,13 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Settings to define an MPU region.
-     */
+/**
+ * @brief Settings to define an MPU region.
+ */
     typedef struct MPURegionSettings
     {
-        uint32_t ulRBAR;     /**< RBAR for the region. */
-        uint32_t ulRLAR;     /**< RLAR for the region. */
+        uint32_t ulRBAR; /**< RBAR for the region. */
+        uint32_t ulRLAR; /**< RLAR for the region. */
     } MPURegionSettings_t;
 
     #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
@@ -203,9 +203,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-        /**
-         * @brief System call stack.
-         */
+/**
+ * @brief System call stack.
+ */
         typedef struct SYSTEM_CALL_STACK_INFO
         {
             uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ];
@@ -218,74 +218,74 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
-    /**
-     * @brief MPU settings as stored in the TCB.
-     */
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
     #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
 
-        #if( configENABLE_TRUSTZONE == 1 )
+        #if ( configENABLE_TRUSTZONE == 1 )
 
-            /*
-             * +-----------+---------------+----------+-----------------+------------------------------+-----+
-             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
-             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
-             * +-----------+---------------+----------+-----------------+------------------------------+-----+
-             *
-             * <-----------><--------------><---------><----------------><-----------------------------><---->
-             *      16             16            8               8                     5                   1
-             */
-            #define MAX_CONTEXT_SIZE 54
+/*
+ * +-----------+---------------+----------+-----------------+------------------------------+-----+
+ * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+ * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+ * +-----------+---------------+----------+-----------------+------------------------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><-----------------------------><---->
+ *      16             16            8               8                     5                   1
+ */
+            #define MAX_CONTEXT_SIZE    54
 
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-            /*
-             * +-----------+---------------+----------+-----------------+----------------------+-----+
-             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
-             * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
-             * +-----------+---------------+----------+-----------------+----------------------+-----+
-             *
-             * <-----------><--------------><---------><----------------><---------------------><---->
-             *      16             16            8               8                  4              1
-             */
-            #define MAX_CONTEXT_SIZE 53
+/*
+ * +-----------+---------------+----------+-----------------+----------------------+-----+
+ * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+ * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
+ * +-----------+---------------+----------+-----------------+----------------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><---------------------><---->
+ *      16             16            8               8                  4              1
+ */
+            #define MAX_CONTEXT_SIZE    53
 
         #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
 
     #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-        #if( configENABLE_TRUSTZONE == 1 )
+        #if ( configENABLE_TRUSTZONE == 1 )
 
-            /*
-             * +----------+-----------------+------------------------------+-----+
-             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
-             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
-             * +----------+-----------------+------------------------------+-----+
-             *
-             * <---------><----------------><------------------------------><---->
-             *     8               8                      5                   1
-             */
-            #define MAX_CONTEXT_SIZE 22
+/*
+ * +----------+-----------------+------------------------------+-----+
+ * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+ * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+ * +----------+-----------------+------------------------------+-----+
+ *
+ * <---------><----------------><------------------------------><---->
+ *     8               8                      5                   1
+ */
+            #define MAX_CONTEXT_SIZE    22
 
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-            /*
-             * +----------+-----------------+----------------------+-----+
-             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
-             * |          | PC, xPSR        | EXC_RETURN           |     |
-             * +----------+-----------------+----------------------+-----+
-             *
-             * <---------><----------------><----------------------><---->
-             *     8               8                  4              1
-             */
-            #define MAX_CONTEXT_SIZE 21
+/*
+ * +----------+-----------------+----------------------+-----+
+ * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+ * |          | PC, xPSR        | EXC_RETURN           |     |
+ * +----------+-----------------+----------------------+-----+
+ *
+ * <---------><----------------><----------------------><---->
+ *     8               8                  4              1
+ */
+            #define MAX_CONTEXT_SIZE    21
 
         #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
 
     #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-    /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
-    #define portSTACK_FRAME_HAS_PADDING_FLAG     ( 1UL << 0UL )
-    #define portTASK_IS_PRIVILEGED_FLAG          ( 1UL << 1UL )
+/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
+    #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
+    #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
     typedef struct MPU_SETTINGS
     {
@@ -364,49 +364,49 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-    /**
-     * @brief Allocate a secure context for the task.
-     *
-     * Tasks are not created with a secure context. Any task that is going to call
-     * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
-     * secure context before it calls any secure function.
-     *
-     * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
-     */
+/**
+ * @brief Allocate a secure context for the task.
+ *
+ * Tasks are not created with a secure context. Any task that is going to call
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+ * secure context before it calls any secure function.
+ *
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+ */
     #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
 
-    /**
-     * @brief Called when a task is deleted to delete the task's secure context,
-     * if it has one.
-     *
-     * @param[in] pxTCB The TCB of the task being deleted.
-     */
+/**
+ * @brief Called when a task is deleted to delete the task's secure context,
+ * if it has one.
+ *
+ * @param[in] pxTCB The TCB of the task being deleted.
+ */
     #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
 #endif /* configENABLE_TRUSTZONE */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Checks whether or not the processor is privileged.
-     *
-     * @return 1 if the processor is already privileged, 0 otherwise.
-     */
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
     #define portIS_PRIVILEGED()      xIsPrivileged()
 
-    /**
-     * @brief Raise an SVC request to raise privilege.
-     *
-     * The SVC handler checks that the SVC was raised from a system call and only
-     * then it raises the privilege. If this is called from any other place,
-     * the privilege is not raised.
-     */
+/**
+ * @brief Raise an SVC request to raise privilege.
+ *
+ * The SVC handler checks that the SVC was raised from a system call and only
+ * then it raises the privilege. If this is called from any other place,
+ * the privilege is not raised.
+ */
     #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
 
-    /**
-     * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
-     * register.
-     */
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
     #define portRESET_PRIVILEGE()    vResetPrivilege()
 #else
     #define portIS_PRIVILEGED()
@@ -419,12 +419,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     extern BaseType_t xPortIsTaskPrivileged( void );
 
-    /**
-     * @brief Checks whether or not the calling task is privileged.
-     *
-     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
-     */
-    #define portIS_TASK_PRIVILEGED()      xPortIsTaskPrivileged()
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
+    #define portIS_TASK_PRIVILEGED()    xPortIsTaskPrivileged()
 
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
@@ -439,9 +439,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * based on whether or not Mainline extension is implemented. */
 #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
     #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
-        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
     #else
-        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    0
     #endif
 #endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
 
@@ -450,9 +450,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  */
 #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
 
-    /**
-     * @brief Count the number of leading zeros in a 32-bit value.
-     */
+/**
+ * @brief Count the number of leading zeros in a 32-bit value.
+ */
     static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
     {
         uint32_t ulReturn;
@@ -462,7 +462,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         return ulReturn;
     }
 
-    /* Check the configuration. */
+/* Check the configuration. */
     #if ( configMAX_PRIORITIES > 32 )
         #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
     #endif
@@ -471,16 +471,16 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection.  Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
     #endif
 
-    /**
-     * @brief Store/clear the ready priorities in a bit map.
-     */
-    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+/**
+ * @brief Store/clear the ready priorities in a bit map.
+ */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )      ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )       ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 
-    /**
-     * @brief Get the priority of the highest-priority task that is ready to execute.
-     */
-    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )   uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+/**
+ * @brief Get the priority of the highest-priority task that is ready to execute.
+ */
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
 
 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM33/secure/secure_context.c b/portable/GCC/ARM_CM33/secure/secure_context.c
index 0730d574d..7d2171996 100644
--- a/portable/GCC/ARM_CM33/secure/secure_context.c
+++ b/portable/GCC/ARM_CM33/secure/secure_context.c
@@ -65,7 +65,7 @@
  * @brief Maximum number of secure contexts.
  */
 #ifndef secureconfigMAX_SECURE_CONTEXTS
-    #define secureconfigMAX_SECURE_CONTEXTS        8UL
+    #define secureconfigMAX_SECURE_CONTEXTS    8UL
 #endif
 /*-----------------------------------------------------------*/
 
@@ -164,15 +164,15 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
         }
 
         #if ( configENABLE_MPU == 1 )
-            {
-                /* Configure thread mode to use PSP and to be unprivileged. */
-                secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
-            }
+        {
+            /* Configure thread mode to use PSP and to be unprivileged. */
+            secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
+        }
         #else /* configENABLE_MPU */
-            {
-                /* Configure thread mode to use PSP and to be privileged. */
-                secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
-            }
+        {
+            /* Configure thread mode to use PSP and to be privileged. */
+            secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
+        }
         #endif /* configENABLE_MPU */
     }
 }
@@ -219,16 +219,16 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
             if( pucStackMemory != NULL )
             {
                 /* Since stack grows down, the starting point will be the last
-                 * location. Note that this location is next to the last
-                 * allocated byte for stack (excluding the space for seal values)
-                 * because the hardware decrements the stack pointer before
-                 * writing i.e. if stack pointer is 0x2, a push operation will
-                 * decrement the stack pointer to 0x1 and then write at 0x1. */
+                * location. Note that this location is next to the last
+                * allocated byte for stack (excluding the space for seal values)
+                * because the hardware decrements the stack pointer before
+                * writing i.e. if stack pointer is 0x2, a push operation will
+                * decrement the stack pointer to 0x1 and then write at 0x1. */
                 xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize;
 
                 /* Seal the created secure process stack. */
-                *( uint32_t * )( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE;
-                *( uint32_t * )( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE;
+                *( uint32_t * ) ( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE;
+                *( uint32_t * ) ( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE;
 
                 /* The stack cannot go beyond this location. This value is
                  * programmed in the PSPLIM register on context switch.*/
@@ -237,32 +237,32 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
                 xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle;
 
                 #if ( configENABLE_MPU == 1 )
+                {
+                    /* Store the correct CONTROL value for the task on the stack.
+                     * This value is programmed in the CONTROL register on
+                     * context switch. */
+                    pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart;
+                    pulCurrentStackPointer--;
+
+                    if( ulIsTaskPrivileged )
                     {
-                        /* Store the correct CONTROL value for the task on the stack.
-                         * This value is programmed in the CONTROL register on
-                         * context switch. */
-                        pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart;
-                        pulCurrentStackPointer--;
-
-                        if( ulIsTaskPrivileged )
-                        {
-                            *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
-                        }
-                        else
-                        {
-                            *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
-                        }
-
-                        /* Store the current stack pointer. This value is programmed in
-                         * the PSP register on context switch. */
-                        xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+                        *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
                     }
+                    else
+                    {
+                        *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
+                    }
+
+                    /* Store the current stack pointer. This value is programmed in
+                     * the PSP register on context switch. */
+                    xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+                }
                 #else /* configENABLE_MPU */
-                    {
-                        /* Current SP is set to the starting of the stack. This
-                         * value programmed in the PSP register on context switch. */
-                        xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart;
-                    }
+                {
+                    /* Current SP is set to the starting of the stack. This
+                     * value programmed in the PSP register on context switch. */
+                    xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart;
+                }
                 #endif /* configENABLE_MPU */
 
                 /* Ensure to never return 0 as a valid context handle. */
@@ -275,7 +275,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
 }
 /*-----------------------------------------------------------*/
 
-secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle,
+                                                              void * pvTaskHandle )
 {
     uint32_t ulIPSR, ulSecureContextIndex;
 
@@ -306,7 +307,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandl
 }
 /*-----------------------------------------------------------*/
 
-secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle,
+                                                              void * pvTaskHandle )
 {
     uint8_t * pucStackLimit;
     uint32_t ulSecureContextIndex;
@@ -328,7 +330,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandl
 }
 /*-----------------------------------------------------------*/
 
-secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle,
+                                                              void * pvTaskHandle )
 {
     uint8_t * pucStackLimit;
     uint32_t ulSecureContextIndex;
diff --git a/portable/GCC/ARM_CM33/secure/secure_context.h b/portable/GCC/ARM_CM33/secure/secure_context.h
index d0adbaf01..0bf776198 100644
--- a/portable/GCC/ARM_CM33/secure/secure_context.h
+++ b/portable/GCC/ARM_CM33/secure/secure_context.h
@@ -38,12 +38,12 @@
 /**
  * @brief PSP value when no secure context is loaded.
  */
-#define securecontextNO_STACK               0x0
+#define securecontextNO_STACK              0x0
 
 /**
  * @brief Invalid context ID.
  */
-#define securecontextINVALID_CONTEXT_ID     0UL
+#define securecontextINVALID_CONTEXT_ID    0UL
 /*-----------------------------------------------------------*/
 
 /**
@@ -108,7 +108,8 @@ void SecureContext_Init( void );
  * @param[in] xSecureContextHandle Context handle corresponding to the
  * context to be freed.
  */
-void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle,
+                                void * pvTaskHandle );
 
 /**
  * @brief Loads the given context.
@@ -119,7 +120,8 @@ void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void
  * @param[in] xSecureContextHandle Context handle corresponding to the context
  * to be loaded.
  */
-void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle,
+                                void * pvTaskHandle );
 
 /**
  * @brief Saves the given context.
@@ -130,6 +132,7 @@ void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void
  * @param[in] xSecureContextHandle Context handle corresponding to the context
  * to be saved.
  */
-void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle,
+                                void * pvTaskHandle );
 
 #endif /* __SECURE_CONTEXT_H__ */
diff --git a/portable/GCC/ARM_CM33/secure/secure_heap.c b/portable/GCC/ARM_CM33/secure/secure_heap.c
index f3b80df54..1ec3bdbdb 100644
--- a/portable/GCC/ARM_CM33/secure/secure_heap.c
+++ b/portable/GCC/ARM_CM33/secure/secure_heap.c
@@ -67,7 +67,7 @@
 #define secureheapSIZE_MAX              ( ~( ( size_t ) 0 ) )
 
 /* Check if adding a and b will result in overflow. */
-#define secureheapADD_WILL_OVERFLOW( a, b )         ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) )
+#define secureheapADD_WILL_OVERFLOW( a, b )    ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) )
 
 /* MSB of the xBlockSize member of an BlockLink_t structure is used to track
  * the allocation status of a block.  When MSB of the xBlockSize member of
@@ -397,17 +397,17 @@ void * pvPortMalloc( size_t xWantedSize )
     traceMALLOC( pvReturn, xWantedSize );
 
     #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
+    {
+        if( pvReturn == NULL )
         {
-            if( pvReturn == NULL )
-            {
-                extern void vApplicationMallocFailedHook( void );
-                vApplicationMallocFailedHook();
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
+            extern void vApplicationMallocFailedHook( void );
+            vApplicationMallocFailedHook();
         }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
     #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */
 
     secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );
diff --git a/portable/GCC/ARM_CM33/secure/secure_init.c b/portable/GCC/ARM_CM33/secure/secure_init.c
index dc19ebc7d..b89c5f644 100644
--- a/portable/GCC/ARM_CM33/secure/secure_init.c
+++ b/portable/GCC/ARM_CM33/secure/secure_init.c
@@ -93,7 +93,7 @@ secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )
          * permitted. CP11 should be programmed to the same value as CP10. */
         *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
 
-        /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
+        /* LSPENS = 0 ==> LSPEN is writable from non-secure state. This ensures
          * that we can enable/disable lazy stacking in port.c file. */
         *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK );
 
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.c
index 2d1218a95..d1fbdc0e5 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.c
@@ -44,2274 +44,2274 @@
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-#if ( INCLUDE_xTaskDelayUntil == 1 )
+    #if ( INCLUDE_xTaskDelayUntil == 1 )
 
-BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
-                                const TickType_t xTimeIncrement ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
+                                        const TickType_t xTimeIncrement ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
-                                const TickType_t xTimeIncrement ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskDelayUntilImpl                       \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskDelayUntil_Unpriv                        \n"
-        " MPU_xTaskDelayUntil_Priv:                             \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskDelayUntilImpl                         \n"
-        " MPU_xTaskDelayUntil_Unpriv:                           \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskDelayUntilImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
+                                        const TickType_t xTimeIncrement ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskDelayUntilImpl                       \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskDelayUntil_Unpriv                        \n"
+                " MPU_xTaskDelayUntil_Priv:                             \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskDelayUntilImpl                         \n"
+                " MPU_xTaskDelayUntil_Unpriv:                           \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskDelayUntilImpl                        \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */
+    #endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_xTaskAbortDelay == 1 )
+    #if ( INCLUDE_xTaskAbortDelay == 1 )
 
-BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskAbortDelayImpl                       \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskAbortDelay_Unpriv                        \n"
-        " MPU_xTaskAbortDelay_Priv:                             \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskAbortDelayImpl                         \n"
-        " MPU_xTaskAbortDelay_Unpriv:                           \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskAbortDelayImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskAbortDelayImpl                       \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskAbortDelay_Unpriv                        \n"
+                " MPU_xTaskAbortDelay_Priv:                             \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskAbortDelayImpl                         \n"
+                " MPU_xTaskAbortDelay_Unpriv:                           \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskAbortDelayImpl                        \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */
+    #endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_vTaskDelay == 1 )
+    #if ( INCLUDE_vTaskDelay == 1 )
 
-void MPU_vTaskDelay( const TickType_t xTicksToDelay ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskDelay( const TickType_t xTicksToDelay ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskDelayImpl                            \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskDelay_Unpriv                             \n"
-        " MPU_vTaskDelay_Priv:                                  \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskDelayImpl                              \n"
-        " MPU_vTaskDelay_Unpriv:                                \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskDelayImpl                             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskDelayImpl                            \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskDelay_Unpriv                             \n"
+                " MPU_vTaskDelay_Priv:                                  \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskDelayImpl                              \n"
+                " MPU_vTaskDelay_Unpriv:                                \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskDelayImpl                             \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_vTaskDelay == 1 ) */
+    #endif /* if ( INCLUDE_vTaskDelay == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_uxTaskPriorityGet == 1 )
+    #if ( INCLUDE_uxTaskPriorityGet == 1 )
 
-UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskPriorityGetImpl                     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTaskPriorityGet_Unpriv                      \n"
-        " MPU_uxTaskPriorityGet_Priv:                           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTaskPriorityGetImpl                       \n"
-        " MPU_uxTaskPriorityGet_Unpriv:                         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskPriorityGetImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskPriorityGetImpl                     \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTaskPriorityGet_Unpriv                      \n"
+                " MPU_uxTaskPriorityGet_Priv:                           \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTaskPriorityGetImpl                       \n"
+                " MPU_uxTaskPriorityGet_Unpriv:                         \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskPriorityGetImpl                      \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */
+    #endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_eTaskGetState == 1 )
+    #if ( INCLUDE_eTaskGetState == 1 )
 
-eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_eTaskGetStateImpl                         \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_eTaskGetState_Unpriv                          \n"
-        " MPU_eTaskGetState_Priv:                               \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_eTaskGetStateImpl                           \n"
-        " MPU_eTaskGetState_Unpriv:                             \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_eTaskGetStateImpl                          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_eTaskGetStateImpl                         \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_eTaskGetState_Unpriv                          \n"
+                " MPU_eTaskGetState_Priv:                               \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_eTaskGetStateImpl                           \n"
+                " MPU_eTaskGetState_Unpriv:                             \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_eTaskGetStateImpl                          \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_eTaskGetState == 1 ) */
+    #endif /* if ( INCLUDE_eTaskGetState == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-void MPU_vTaskGetInfo( TaskHandle_t xTask,
-                       TaskStatus_t * pxTaskStatus,
-                       BaseType_t xGetFreeStackSpace,
-                       eTaskState eState ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskGetInfo( TaskHandle_t xTask,
+                               TaskStatus_t * pxTaskStatus,
+                               BaseType_t xGetFreeStackSpace,
+                               eTaskState eState ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskGetInfo( TaskHandle_t xTask,
-                       TaskStatus_t * pxTaskStatus,
-                       BaseType_t xGetFreeStackSpace,
-                       eTaskState eState ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskGetInfoImpl                          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskGetInfo_Unpriv                           \n"
-        " MPU_vTaskGetInfo_Priv:                                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskGetInfoImpl                            \n"
-        " MPU_vTaskGetInfo_Unpriv:                              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskGetInfoImpl                           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskGetInfo( TaskHandle_t xTask,
+                               TaskStatus_t * pxTaskStatus,
+                               BaseType_t xGetFreeStackSpace,
+                               eTaskState eState ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskGetInfoImpl                          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskGetInfo_Unpriv                           \n"
+                " MPU_vTaskGetInfo_Priv:                                \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskGetInfoImpl                            \n"
+                " MPU_vTaskGetInfo_Unpriv:                              \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskGetInfoImpl                           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
+    #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
+    #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
 
-TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetIdleTaskHandleImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGetIdleTaskHandle_Unpriv                 \n"
-        " MPU_xTaskGetIdleTaskHandle_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGetIdleTaskHandleImpl                  \n"
-        " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetIdleTaskHandleImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetIdleTaskHandleImpl                \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGetIdleTaskHandle_Unpriv                 \n"
+                " MPU_xTaskGetIdleTaskHandle_Priv:                      \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGetIdleTaskHandleImpl                  \n"
+                " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetIdleTaskHandleImpl                 \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */
+    #endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_vTaskSuspend == 1 )
+    #if ( INCLUDE_vTaskSuspend == 1 )
 
-void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSuspendImpl                          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskSuspend_Unpriv                           \n"
-        " MPU_vTaskSuspend_Priv:                                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskSuspendImpl                            \n"
-        " MPU_vTaskSuspend_Unpriv:                              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSuspendImpl                           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskSuspendImpl                          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskSuspend_Unpriv                           \n"
+                " MPU_vTaskSuspend_Priv:                                \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskSuspendImpl                            \n"
+                " MPU_vTaskSuspend_Unpriv:                              \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskSuspendImpl                           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
+    #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_vTaskSuspend == 1 )
+    #if ( INCLUDE_vTaskSuspend == 1 )
 
-void MPU_vTaskResume( TaskHandle_t xTaskToResume ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskResume( TaskHandle_t xTaskToResume ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskResumeImpl                           \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskResume_Unpriv                            \n"
-        " MPU_vTaskResume_Priv:                                 \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskResumeImpl                             \n"
-        " MPU_vTaskResume_Unpriv:                               \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskResumeImpl                            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskResumeImpl                           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskResume_Unpriv                            \n"
+                " MPU_vTaskResume_Priv:                                 \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskResumeImpl                             \n"
+                " MPU_vTaskResume_Unpriv:                               \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskResumeImpl                            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
+    #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
 /*-----------------------------------------------------------*/
 
-TickType_t MPU_xTaskGetTickCount( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    TickType_t MPU_xTaskGetTickCount( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TickType_t MPU_xTaskGetTickCount( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetTickCountImpl                     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGetTickCount_Unpriv                      \n"
-        " MPU_xTaskGetTickCount_Priv:                           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGetTickCountImpl                       \n"
-        " MPU_xTaskGetTickCount_Unpriv:                         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetTickCountImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    TickType_t MPU_xTaskGetTickCount( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xTaskGetTickCountImpl                     \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xTaskGetTickCount_Unpriv                      \n"
+            " MPU_xTaskGetTickCount_Priv:                           \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xTaskGetTickCountImpl                       \n"
+            " MPU_xTaskGetTickCount_Unpriv:                         \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xTaskGetTickCountImpl                      \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetNumberOfTasksImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTaskGetNumberOfTasks_Unpriv                 \n"
-        " MPU_uxTaskGetNumberOfTasks_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTaskGetNumberOfTasksImpl                  \n"
-        " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetNumberOfTasksImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_uxTaskGetNumberOfTasksImpl                \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_uxTaskGetNumberOfTasks_Unpriv                 \n"
+            " MPU_uxTaskGetNumberOfTasks_Priv:                      \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_uxTaskGetNumberOfTasksImpl                  \n"
+            " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_uxTaskGetNumberOfTasksImpl                 \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configGENERATE_RUN_TIME_STATS == 1 )
+    #if ( configGENERATE_RUN_TIME_STATS == 1 )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetRunTimeCounterImpl               \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGetRunTimeCounter_Unpriv                \n"
-        " MPU_ulTaskGetRunTimeCounter_Priv:                     \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGetRunTimeCounterImpl                 \n"
-        " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetRunTimeCounterImpl                \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetRunTimeCounterImpl               \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGetRunTimeCounter_Unpriv                \n"
+                " MPU_ulTaskGetRunTimeCounter_Priv:                     \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGetRunTimeCounterImpl                 \n"
+                " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetRunTimeCounterImpl                \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configGENERATE_RUN_TIME_STATS == 1 )
+    #if ( configGENERATE_RUN_TIME_STATS == 1 )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetRunTimePercentImpl               \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGetRunTimePercent_Unpriv                \n"
-        " MPU_ulTaskGetRunTimePercent_Priv:                     \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGetRunTimePercentImpl                 \n"
-        " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetRunTimePercentImpl                \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetRunTimePercentImpl               \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGetRunTimePercent_Unpriv                \n"
+                " MPU_ulTaskGetRunTimePercent_Priv:                     \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGetRunTimePercentImpl                 \n"
+                " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetRunTimePercentImpl                \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+    #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetIdleRunTimePercentImpl           \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv            \n"
-        " MPU_ulTaskGetIdleRunTimePercent_Priv:                 \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGetIdleRunTimePercentImpl             \n"
-        " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetIdleRunTimePercentImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetIdleRunTimePercentImpl           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv            \n"
+                " MPU_ulTaskGetIdleRunTimePercent_Priv:                 \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGetIdleRunTimePercentImpl             \n"
+                " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetIdleRunTimePercentImpl            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+    #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetIdleRunTimeCounterImpl           \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv            \n"
-        " MPU_ulTaskGetIdleRunTimeCounter_Priv:                 \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGetIdleRunTimeCounterImpl             \n"
-        " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetIdleRunTimeCounterImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetIdleRunTimeCounterImpl           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv            \n"
+                " MPU_ulTaskGetIdleRunTimeCounter_Priv:                 \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGetIdleRunTimeCounterImpl             \n"
+                " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetIdleRunTimeCounterImpl            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+    #if ( configUSE_APPLICATION_TASK_TAG == 1 )
 
-void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
-                                     TaskHookFunction_t pxHookFunction ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
+                                             TaskHookFunction_t pxHookFunction ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
-                                     TaskHookFunction_t pxHookFunction ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSetApplicationTaskTagImpl            \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskSetApplicationTaskTag_Unpriv             \n"
-        " MPU_vTaskSetApplicationTaskTag_Priv:                  \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskSetApplicationTaskTagImpl              \n"
-        " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSetApplicationTaskTagImpl             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
+                                             TaskHookFunction_t pxHookFunction ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskSetApplicationTaskTagImpl            \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskSetApplicationTaskTag_Unpriv             \n"
+                " MPU_vTaskSetApplicationTaskTag_Priv:                  \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskSetApplicationTaskTagImpl              \n"
+                " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskSetApplicationTaskTagImpl             \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
+    #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+    #if ( configUSE_APPLICATION_TASK_TAG == 1 )
 
-TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetApplicationTaskTagImpl            \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGetApplicationTaskTag_Unpriv             \n"
-        " MPU_xTaskGetApplicationTaskTag_Priv:                  \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGetApplicationTaskTagImpl              \n"
-        " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetApplicationTaskTagImpl             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetApplicationTaskTagImpl            \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGetApplicationTaskTag_Unpriv             \n"
+                " MPU_xTaskGetApplicationTaskTag_Priv:                  \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGetApplicationTaskTagImpl              \n"
+                " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetApplicationTaskTagImpl             \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
+    #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+    #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
 
-void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
-                                            BaseType_t xIndex,
-                                            void * pvValue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
+                                                    BaseType_t xIndex,
+                                                    void * pvValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
-                                            BaseType_t xIndex,
-                                            void * pvValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSetThreadLocalStoragePointerImpl     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv      \n"
-        " MPU_vTaskSetThreadLocalStoragePointer_Priv:           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskSetThreadLocalStoragePointerImpl       \n"
-        " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSetThreadLocalStoragePointerImpl      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
+                                                    BaseType_t xIndex,
+                                                    void * pvValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskSetThreadLocalStoragePointerImpl     \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv      \n"
+                " MPU_vTaskSetThreadLocalStoragePointer_Priv:           \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskSetThreadLocalStoragePointerImpl       \n"
+                " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskSetThreadLocalStoragePointerImpl      \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
+    #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+    #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
 
-void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
-                                               BaseType_t xIndex ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
+                                                       BaseType_t xIndex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
-                                               BaseType_t xIndex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pvTaskGetThreadLocalStoragePointerImpl    \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv     \n"
-        " MPU_pvTaskGetThreadLocalStoragePointer_Priv:          \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_pvTaskGetThreadLocalStoragePointerImpl      \n"
-        " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pvTaskGetThreadLocalStoragePointerImpl     \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
+                                                       BaseType_t xIndex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pvTaskGetThreadLocalStoragePointerImpl    \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv     \n"
+                " MPU_pvTaskGetThreadLocalStoragePointer_Priv:          \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_pvTaskGetThreadLocalStoragePointerImpl      \n"
+                " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pvTaskGetThreadLocalStoragePointerImpl     \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
+    #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
-                                      const UBaseType_t uxArraySize,
-                                      configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
+                                              const UBaseType_t uxArraySize,
+                                              configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
-                                      const UBaseType_t uxArraySize,
-                                      configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetSystemStateImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTaskGetSystemState_Unpriv                   \n"
-        " MPU_uxTaskGetSystemState_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTaskGetSystemStateImpl                    \n"
-        " MPU_uxTaskGetSystemState_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetSystemStateImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
+                                              const UBaseType_t uxArraySize,
+                                              configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskGetSystemStateImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTaskGetSystemState_Unpriv                   \n"
+                " MPU_uxTaskGetSystemState_Priv:                        \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTaskGetSystemStateImpl                    \n"
+                " MPU_uxTaskGetSystemState_Unpriv:                      \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskGetSystemStateImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
+    #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
+    #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
 
-UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetStackHighWaterMarkImpl           \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTaskGetStackHighWaterMark_Unpriv            \n"
-        " MPU_uxTaskGetStackHighWaterMark_Priv:                 \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTaskGetStackHighWaterMarkImpl             \n"
-        " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetStackHighWaterMarkImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskGetStackHighWaterMarkImpl           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTaskGetStackHighWaterMark_Unpriv            \n"
+                " MPU_uxTaskGetStackHighWaterMark_Priv:                 \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTaskGetStackHighWaterMarkImpl             \n"
+                " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskGetStackHighWaterMarkImpl            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */
+    #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
+    #if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
 
-configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetStackHighWaterMark2Impl          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv           \n"
-        " MPU_uxTaskGetStackHighWaterMark2_Priv:                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTaskGetStackHighWaterMark2Impl            \n"
-        " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetStackHighWaterMark2Impl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskGetStackHighWaterMark2Impl          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv           \n"
+                " MPU_uxTaskGetStackHighWaterMark2_Priv:                \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTaskGetStackHighWaterMark2Impl            \n"
+                " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskGetStackHighWaterMark2Impl           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */
+    #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
+    #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
 
-TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetCurrentTaskHandleImpl             \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGetCurrentTaskHandle_Unpriv              \n"
-        " MPU_xTaskGetCurrentTaskHandle_Priv:                   \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGetCurrentTaskHandleImpl               \n"
-        " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetCurrentTaskHandleImpl              \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetCurrentTaskHandleImpl             \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGetCurrentTaskHandle_Unpriv              \n"
+                " MPU_xTaskGetCurrentTaskHandle_Priv:                   \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGetCurrentTaskHandleImpl               \n"
+                " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetCurrentTaskHandleImpl              \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
+    #endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_xTaskGetSchedulerState == 1 )
+    #if ( INCLUDE_xTaskGetSchedulerState == 1 )
 
-BaseType_t MPU_xTaskGetSchedulerState( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGetSchedulerState( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGetSchedulerState( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetSchedulerStateImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGetSchedulerState_Unpriv                 \n"
-        " MPU_xTaskGetSchedulerState_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGetSchedulerStateImpl                  \n"
-        " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetSchedulerStateImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGetSchedulerState( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetSchedulerStateImpl                \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGetSchedulerState_Unpriv                 \n"
+                " MPU_xTaskGetSchedulerState_Priv:                      \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGetSchedulerStateImpl                  \n"
+                " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetSchedulerStateImpl                 \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */
+    #endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */
 /*-----------------------------------------------------------*/
 
-void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSetTimeOutStateImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskSetTimeOutState_Unpriv                   \n"
-        " MPU_vTaskSetTimeOutState_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskSetTimeOutStateImpl                    \n"
-        " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSetTimeOutStateImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_vTaskSetTimeOutStateImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_vTaskSetTimeOutState_Unpriv                   \n"
+            " MPU_vTaskSetTimeOutState_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_vTaskSetTimeOutStateImpl                    \n"
+            " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_vTaskSetTimeOutStateImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
-                                     TickType_t * const pxTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
+                                         TickType_t * const pxTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
-                                     TickType_t * const pxTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskCheckForTimeOutImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskCheckForTimeOut_Unpriv                   \n"
-        " MPU_xTaskCheckForTimeOut_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskCheckForTimeOutImpl                    \n"
-        " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskCheckForTimeOutImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
+                                         TickType_t * const pxTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xTaskCheckForTimeOutImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xTaskCheckForTimeOut_Unpriv                   \n"
+            " MPU_xTaskCheckForTimeOut_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xTaskCheckForTimeOutImpl                    \n"
+            " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xTaskCheckForTimeOutImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                   UBaseType_t uxIndexToNotify,
-                                   uint32_t ulValue,
-                                   eNotifyAction eAction,
-                                   uint32_t * pulPreviousNotificationValue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
+                                           UBaseType_t uxIndexToNotify,
+                                           uint32_t ulValue,
+                                           eNotifyAction eAction,
+                                           uint32_t * pulPreviousNotificationValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                   UBaseType_t uxIndexToNotify,
-                                   uint32_t ulValue,
-                                   eNotifyAction eAction,
-                                   uint32_t * pulPreviousNotificationValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGenericNotifyImpl                    \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGenericNotify_Unpriv                     \n"
-        " MPU_xTaskGenericNotify_Priv:                          \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGenericNotifyImpl                      \n"
-        " MPU_xTaskGenericNotify_Unpriv:                        \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGenericNotifyImpl                     \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
+                                           UBaseType_t uxIndexToNotify,
+                                           uint32_t ulValue,
+                                           eNotifyAction eAction,
+                                           uint32_t * pulPreviousNotificationValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGenericNotifyImpl                    \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGenericNotify_Unpriv                     \n"
+                " MPU_xTaskGenericNotify_Priv:                          \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGenericNotifyImpl                      \n"
+                " MPU_xTaskGenericNotify_Unpriv:                        \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGenericNotifyImpl                     \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                       uint32_t ulBitsToClearOnEntry,
-                                       uint32_t ulBitsToClearOnExit,
-                                       uint32_t * pulNotificationValue,
-                                       TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
+                                               uint32_t ulBitsToClearOnEntry,
+                                               uint32_t ulBitsToClearOnExit,
+                                               uint32_t * pulNotificationValue,
+                                               TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                       uint32_t ulBitsToClearOnEntry,
-                                       uint32_t ulBitsToClearOnExit,
-                                       uint32_t * pulNotificationValue,
-                                       TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGenericNotifyWaitImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGenericNotifyWait_Unpriv                 \n"
-        " MPU_xTaskGenericNotifyWait_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGenericNotifyWaitImpl                  \n"
-        " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGenericNotifyWaitImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
+                                               uint32_t ulBitsToClearOnEntry,
+                                               uint32_t ulBitsToClearOnExit,
+                                               uint32_t * pulNotificationValue,
+                                               TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGenericNotifyWaitImpl                \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGenericNotifyWait_Unpriv                 \n"
+                " MPU_xTaskGenericNotifyWait_Priv:                      \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGenericNotifyWaitImpl                  \n"
+                " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGenericNotifyWaitImpl                 \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
-                                      BaseType_t xClearCountOnExit,
-                                      TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
+                                              BaseType_t xClearCountOnExit,
+                                              TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
-                                      BaseType_t xClearCountOnExit,
-                                      TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGenericNotifyTakeImpl               \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGenericNotifyTake_Unpriv                \n"
-        " MPU_ulTaskGenericNotifyTake_Priv:                     \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGenericNotifyTakeImpl                 \n"
-        " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGenericNotifyTakeImpl                \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
+                                              BaseType_t xClearCountOnExit,
+                                              TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGenericNotifyTakeImpl               \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGenericNotifyTake_Unpriv                \n"
+                " MPU_ulTaskGenericNotifyTake_Priv:                     \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGenericNotifyTakeImpl                 \n"
+                " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGenericNotifyTakeImpl                \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
-                                             UBaseType_t uxIndexToClear ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
+                                                     UBaseType_t uxIndexToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
-                                             UBaseType_t uxIndexToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGenericNotifyStateClearImpl          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGenericNotifyStateClear_Unpriv           \n"
-        " MPU_xTaskGenericNotifyStateClear_Priv:                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGenericNotifyStateClearImpl            \n"
-        " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGenericNotifyStateClearImpl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
+                                                     UBaseType_t uxIndexToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGenericNotifyStateClearImpl          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGenericNotifyStateClear_Unpriv           \n"
+                " MPU_xTaskGenericNotifyStateClear_Priv:                \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGenericNotifyStateClearImpl            \n"
+                " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGenericNotifyStateClearImpl           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
-                                            UBaseType_t uxIndexToClear,
-                                            uint32_t ulBitsToClear ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
+                                                    UBaseType_t uxIndexToClear,
+                                                    uint32_t ulBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
-                                            UBaseType_t uxIndexToClear,
-                                            uint32_t ulBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGenericNotifyValueClearImpl         \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGenericNotifyValueClear_Unpriv          \n"
-        " MPU_ulTaskGenericNotifyValueClear_Priv:               \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGenericNotifyValueClearImpl           \n"
-        " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGenericNotifyValueClearImpl          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
+                                                    UBaseType_t uxIndexToClear,
+                                                    uint32_t ulBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGenericNotifyValueClearImpl         \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGenericNotifyValueClear_Unpriv          \n"
+                " MPU_ulTaskGenericNotifyValueClear_Priv:               \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGenericNotifyValueClearImpl           \n"
+                " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGenericNotifyValueClearImpl          \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
-                                  const void * const pvItemToQueue,
-                                  TickType_t xTicksToWait,
-                                  const BaseType_t xCopyPosition ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
+                                      const void * const pvItemToQueue,
+                                      TickType_t xTicksToWait,
+                                      const BaseType_t xCopyPosition ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
-                                  const void * const pvItemToQueue,
-                                  TickType_t xTicksToWait,
-                                  const BaseType_t xCopyPosition ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueGenericSendImpl                     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueGenericSend_Unpriv                      \n"
-        " MPU_xQueueGenericSend_Priv:                           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueGenericSendImpl                       \n"
-        " MPU_xQueueGenericSend_Unpriv:                         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueGenericSendImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
+                                      const void * const pvItemToQueue,
+                                      TickType_t xTicksToWait,
+                                      const BaseType_t xCopyPosition ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueueGenericSendImpl                     \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xQueueGenericSend_Unpriv                      \n"
+            " MPU_xQueueGenericSend_Priv:                           \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xQueueGenericSendImpl                       \n"
+            " MPU_xQueueGenericSend_Unpriv:                         \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueueGenericSendImpl                      \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxQueueMessagesWaitingImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxQueueMessagesWaiting_Unpriv                 \n"
-        " MPU_uxQueueMessagesWaiting_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxQueueMessagesWaitingImpl                  \n"
-        " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxQueueMessagesWaitingImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_uxQueueMessagesWaitingImpl                \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_uxQueueMessagesWaiting_Unpriv                 \n"
+            " MPU_uxQueueMessagesWaiting_Priv:                      \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_uxQueueMessagesWaitingImpl                  \n"
+            " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_uxQueueMessagesWaitingImpl                 \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxQueueSpacesAvailableImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxQueueSpacesAvailable_Unpriv                 \n"
-        " MPU_uxQueueSpacesAvailable_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxQueueSpacesAvailableImpl                  \n"
-        " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxQueueSpacesAvailableImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_uxQueueSpacesAvailableImpl                \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_uxQueueSpacesAvailable_Unpriv                 \n"
+            " MPU_uxQueueSpacesAvailable_Priv:                      \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_uxQueueSpacesAvailableImpl                  \n"
+            " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_uxQueueSpacesAvailableImpl                 \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
-                              void * const pvBuffer,
-                              TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
+                                  void * const pvBuffer,
+                                  TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
-                              void * const pvBuffer,
-                              TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueReceiveImpl                         \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueReceive_Unpriv                          \n"
-        " MPU_xQueueReceive_Priv:                               \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueReceiveImpl                           \n"
-        " MPU_xQueueReceive_Unpriv:                             \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueReceiveImpl                          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
+                                  void * const pvBuffer,
+                                  TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueueReceiveImpl                         \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xQueueReceive_Unpriv                          \n"
+            " MPU_xQueueReceive_Priv:                               \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xQueueReceiveImpl                           \n"
+            " MPU_xQueueReceive_Unpriv:                             \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueueReceiveImpl                          \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
-                           void * const pvBuffer,
-                           TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
+                               void * const pvBuffer,
+                               TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
-                           void * const pvBuffer,
-                           TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueuePeekImpl                            \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueuePeek_Unpriv                             \n"
-        " MPU_xQueuePeek_Priv:                                  \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueuePeekImpl                              \n"
-        " MPU_xQueuePeek_Unpriv:                                \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueuePeekImpl                             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
+                               void * const pvBuffer,
+                               TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueuePeekImpl                            \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xQueuePeek_Unpriv                             \n"
+            " MPU_xQueuePeek_Priv:                                  \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xQueuePeekImpl                              \n"
+            " MPU_xQueuePeek_Unpriv:                                \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueuePeekImpl                             \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
-                                    TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
+                                        TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
-                                    TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueSemaphoreTakeImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueSemaphoreTake_Unpriv                    \n"
-        " MPU_xQueueSemaphoreTake_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueSemaphoreTakeImpl                     \n"
-        " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueSemaphoreTakeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
+                                        TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueueSemaphoreTakeImpl                   \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xQueueSemaphoreTake_Unpriv                    \n"
+            " MPU_xQueueSemaphoreTake_Priv:                         \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xQueueSemaphoreTakeImpl                     \n"
+            " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueueSemaphoreTakeImpl                    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+    #if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
 
-TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueGetMutexHolderImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueGetMutexHolder_Unpriv                   \n"
-        " MPU_xQueueGetMutexHolder_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueGetMutexHolderImpl                    \n"
-        " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueGetMutexHolderImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueGetMutexHolderImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueGetMutexHolder_Unpriv                   \n"
+                " MPU_xQueueGetMutexHolder_Priv:                        \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueGetMutexHolderImpl                    \n"
+                " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueGetMutexHolderImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */
+    #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+    #if ( configUSE_RECURSIVE_MUTEXES == 1 )
 
-BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
-                                         TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+                                                 TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+        BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+                                                 TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueTakeMutexRecursiveImpl              \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueTakeMutexRecursive_Unpriv               \n"
+                " MPU_xQueueTakeMutexRecursive_Priv:                    \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueTakeMutexRecursiveImpl                \n"
+                " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueTakeMutexRecursiveImpl               \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_RECURSIVE_MUTEXES == 1 )
+
+        BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueGiveMutexRecursiveImpl              \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueGiveMutexRecursive_Unpriv               \n"
+                " MPU_xQueueGiveMutexRecursive_Priv:                    \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueGiveMutexRecursiveImpl                \n"
+                " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueGiveMutexRecursiveImpl               \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_QUEUE_SETS == 1 )
+
+        QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
+                                                        const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
+                                                        const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueSelectFromSetImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueSelectFromSet_Unpriv                    \n"
+                " MPU_xQueueSelectFromSet_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueSelectFromSetImpl                     \n"
+                " MPU_xQueueSelectFromSet_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueSelectFromSetImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_QUEUE_SETS == 1 )
+
+        BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                                       QueueSetHandle_t xQueueSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                                       QueueSetHandle_t xQueueSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueAddToSetImpl                        \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueAddToSet_Unpriv                         \n"
+                " MPU_xQueueAddToSet_Priv:                              \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueAddToSetImpl                          \n"
+                " MPU_xQueueAddToSet_Unpriv:                            \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueAddToSetImpl                         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+        void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
+                                      const char * pcName ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
+                                      const char * pcName ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vQueueAddToRegistryImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vQueueAddToRegistry_Unpriv                    \n"
+                " MPU_vQueueAddToRegistry_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vQueueAddToRegistryImpl                     \n"
+                " MPU_vQueueAddToRegistry_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vQueueAddToRegistryImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+        void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vQueueUnregisterQueueImpl                 \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vQueueUnregisterQueue_Unpriv                  \n"
+                " MPU_vQueueUnregisterQueue_Priv:                       \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vQueueUnregisterQueueImpl                   \n"
+                " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vQueueUnregisterQueueImpl                  \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+        const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pcQueueGetNameImpl                        \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_pcQueueGetName_Unpriv                         \n"
+                " MPU_pcQueueGetName_Priv:                              \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_pcQueueGetNameImpl                          \n"
+                " MPU_pcQueueGetName_Unpriv:                            \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pcQueueGetNameImpl                         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pvTimerGetTimerIDImpl                     \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_pvTimerGetTimerID_Unpriv                      \n"
+                " MPU_pvTimerGetTimerID_Priv:                           \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_pvTimerGetTimerIDImpl                       \n"
+                " MPU_pvTimerGetTimerID_Unpriv:                         \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pvTimerGetTimerIDImpl                      \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
+                                   void * pvNewID ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
+                                   void * pvNewID ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTimerSetTimerIDImpl                      \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTimerSetTimerID_Unpriv                       \n"
+                " MPU_vTimerSetTimerID_Priv:                            \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTimerSetTimerIDImpl                        \n"
+                " MPU_vTimerSetTimerID_Unpriv:                          \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTimerSetTimerIDImpl                       \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerIsTimerActiveImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerIsTimerActive_Unpriv                    \n"
+                " MPU_xTimerIsTimerActive_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerIsTimerActiveImpl                     \n"
+                " MPU_xTimerIsTimerActive_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerIsTimerActiveImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetTimerDaemonTaskHandleImpl        \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv         \n"
+                " MPU_xTimerGetTimerDaemonTaskHandle_Priv:              \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerGetTimerDaemonTaskHandleImpl          \n"
+                " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetTimerDaemonTaskHandleImpl         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                                     const BaseType_t xCommandID,
+                                                     const TickType_t xOptionalValue,
+                                                     BaseType_t * const pxHigherPriorityTaskWoken,
+                                                     const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                                     const BaseType_t xCommandID,
+                                                     const TickType_t xOptionalValue,
+                                                     BaseType_t * const pxHigherPriorityTaskWoken,
+                                                     const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                               \n"
+                " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
+                "                                                               \n"
+                " push {r0}                                                     \n"
+                " mrs r0, control                                               \n"
+                " tst r0, #1                                                    \n"
+                " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
+                " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
+                "     pop {r0}                                                  \n"
+                "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
+                " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
+                "     pop {r0}                                                  \n"
+                "     svc %0                                                    \n"
+                "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
+                "     svc %1                                                    \n"
+                "     bx lr                                                     \n"
+                "                                                               \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pcTimerGetNameImpl                        \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_pcTimerGetName_Unpriv                         \n"
+                " MPU_pcTimerGetName_Priv:                              \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_pcTimerGetNameImpl                          \n"
+                " MPU_pcTimerGetName_Unpriv:                            \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pcTimerGetNameImpl                         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
+                                      const BaseType_t uxAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
+                                      const BaseType_t uxAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTimerSetReloadModeImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTimerSetReloadMode_Unpriv                    \n"
+                " MPU_vTimerSetReloadMode_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTimerSetReloadModeImpl                     \n"
+                " MPU_vTimerSetReloadMode_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTimerSetReloadModeImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetReloadModeImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerGetReloadMode_Unpriv                    \n"
+                " MPU_xTimerGetReloadMode_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerGetReloadModeImpl                     \n"
+                " MPU_xTimerGetReloadMode_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetReloadModeImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTimerGetReloadModeImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTimerGetReloadMode_Unpriv                   \n"
+                " MPU_uxTimerGetReloadMode_Priv:                        \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTimerGetReloadModeImpl                    \n"
+                " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTimerGetReloadModeImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetPeriodImpl                       \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerGetPeriod_Unpriv                        \n"
+                " MPU_xTimerGetPeriod_Priv:                             \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerGetPeriodImpl                         \n"
+                " MPU_xTimerGetPeriod_Unpriv:                           \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetPeriodImpl                        \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetExpiryTimeImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerGetExpiryTime_Unpriv                    \n"
+                " MPU_xTimerGetExpiryTime_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerGetExpiryTimeImpl                     \n"
+                " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetExpiryTimeImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         const BaseType_t xClearOnExit,
+                                         const BaseType_t xWaitForAllBits,
+                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         const BaseType_t xClearOnExit,
+                                         const BaseType_t xWaitForAllBits,
                                          TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueTakeMutexRecursiveImpl              \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueTakeMutexRecursive_Unpriv               \n"
-        " MPU_xQueueTakeMutexRecursive_Priv:                    \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueTakeMutexRecursiveImpl                \n"
-        " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueTakeMutexRecursiveImpl               \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupWaitBitsImpl                   \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
+            " MPU_xEventGroupWaitBits_Priv:                         \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xEventGroupWaitBitsImpl                     \n"
+            " MPU_xEventGroupWaitBits_Unpriv:                       \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupWaitBitsImpl                    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                          const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueGiveMutexRecursiveImpl              \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueGiveMutexRecursive_Unpriv               \n"
-        " MPU_xQueueGiveMutexRecursive_Priv:                    \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueGiveMutexRecursiveImpl                \n"
-        " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueGiveMutexRecursiveImpl               \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                          const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupClearBitsImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xEventGroupClearBits_Unpriv                   \n"
+            " MPU_xEventGroupClearBits_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xEventGroupClearBitsImpl                    \n"
+            " MPU_xEventGroupClearBits_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupClearBitsImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_QUEUE_SETS == 1 )
+    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                        const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
-                                                const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
-                                                const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueSelectFromSetImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueSelectFromSet_Unpriv                    \n"
-        " MPU_xQueueSelectFromSet_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueSelectFromSetImpl                     \n"
-        " MPU_xQueueSelectFromSet_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueSelectFromSetImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                        const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupSetBitsImpl                    \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xEventGroupSetBits_Unpriv                     \n"
+            " MPU_xEventGroupSetBits_Priv:                          \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xEventGroupSetBitsImpl                      \n"
+            " MPU_xEventGroupSetBits_Unpriv:                        \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupSetBitsImpl                     \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_QUEUE_SETS == 1 )
-
-BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
-                               QueueSetHandle_t xQueueSet ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
-                               QueueSetHandle_t xQueueSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueAddToSetImpl                        \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueAddToSet_Unpriv                         \n"
-        " MPU_xQueueAddToSet_Priv:                              \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueAddToSetImpl                          \n"
-        " MPU_xQueueAddToSet_Unpriv:                            \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueAddToSetImpl                         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_QUEUE_SETS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
-                              const char * pcName ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
-                              const char * pcName ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vQueueAddToRegistryImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vQueueAddToRegistry_Unpriv                    \n"
-        " MPU_vQueueAddToRegistry_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vQueueAddToRegistryImpl                     \n"
-        " MPU_vQueueAddToRegistry_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vQueueAddToRegistryImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vQueueUnregisterQueueImpl                 \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vQueueUnregisterQueue_Unpriv                  \n"
-        " MPU_vQueueUnregisterQueue_Priv:                       \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vQueueUnregisterQueueImpl                   \n"
-        " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vQueueUnregisterQueueImpl                  \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pcQueueGetNameImpl                        \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_pcQueueGetName_Unpriv                         \n"
-        " MPU_pcQueueGetName_Priv:                              \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_pcQueueGetNameImpl                          \n"
-        " MPU_pcQueueGetName_Unpriv:                            \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pcQueueGetNameImpl                         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pvTimerGetTimerIDImpl                     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_pvTimerGetTimerID_Unpriv                      \n"
-        " MPU_pvTimerGetTimerID_Priv:                           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_pvTimerGetTimerIDImpl                       \n"
-        " MPU_pvTimerGetTimerID_Unpriv:                         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pvTimerGetTimerIDImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
-                           void * pvNewID ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
-                           void * pvNewID ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTimerSetTimerIDImpl                      \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTimerSetTimerID_Unpriv                       \n"
-        " MPU_vTimerSetTimerID_Priv:                            \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTimerSetTimerIDImpl                        \n"
-        " MPU_vTimerSetTimerID_Unpriv:                          \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTimerSetTimerIDImpl                       \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerIsTimerActiveImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTimerIsTimerActive_Unpriv                    \n"
-        " MPU_xTimerIsTimerActive_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerIsTimerActiveImpl                     \n"
-        " MPU_xTimerIsTimerActive_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerIsTimerActiveImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetTimerDaemonTaskHandleImpl        \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv         \n"
-        " MPU_xTimerGetTimerDaemonTaskHandle_Priv:              \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerGetTimerDaemonTaskHandleImpl          \n"
-        " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetTimerDaemonTaskHandleImpl         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                             const BaseType_t xCommandID,
-                                             const TickType_t xOptionalValue,
-                                             BaseType_t * const pxHigherPriorityTaskWoken,
-                                             const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                             const BaseType_t xCommandID,
-                                             const TickType_t xOptionalValue,
-                                             BaseType_t * const pxHigherPriorityTaskWoken,
-                                             const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                               \n"
-        " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
-        "                                                               \n"
-        " push {r0}                                                     \n"
-        " mrs r0, control                                               \n"
-        " tst r0, #1                                                    \n"
-        " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
-        " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
-        "     pop {r0}                                                  \n"
-        "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
-        " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
-        "     pop {r0}                                                  \n"
-        "     svc %0                                                    \n"
-        "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
-        "     svc %1                                                    \n"
-        "     bx lr                                                     \n"
-        "                                                               \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pcTimerGetNameImpl                        \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_pcTimerGetName_Unpriv                         \n"
-        " MPU_pcTimerGetName_Priv:                              \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_pcTimerGetNameImpl                          \n"
-        " MPU_pcTimerGetName_Unpriv:                            \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pcTimerGetNameImpl                         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                              const BaseType_t uxAutoReload ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                              const BaseType_t uxAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTimerSetReloadModeImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTimerSetReloadMode_Unpriv                    \n"
-        " MPU_vTimerSetReloadMode_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTimerSetReloadModeImpl                     \n"
-        " MPU_vTimerSetReloadMode_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTimerSetReloadModeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetReloadModeImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTimerGetReloadMode_Unpriv                    \n"
-        " MPU_xTimerGetReloadMode_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerGetReloadModeImpl                     \n"
-        " MPU_xTimerGetReloadMode_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetReloadModeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTimerGetReloadModeImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTimerGetReloadMode_Unpriv                   \n"
-        " MPU_uxTimerGetReloadMode_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTimerGetReloadModeImpl                    \n"
-        " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTimerGetReloadModeImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetPeriodImpl                       \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTimerGetPeriod_Unpriv                        \n"
-        " MPU_xTimerGetPeriod_Priv:                             \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerGetPeriodImpl                         \n"
-        " MPU_xTimerGetPeriod_Unpriv:                           \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetPeriodImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetExpiryTimeImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTimerGetExpiryTime_Unpriv                    \n"
-        " MPU_xTimerGetExpiryTime_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerGetExpiryTimeImpl                     \n"
-        " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetExpiryTimeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                     const EventBits_t uxBitsToSet,
                                      const EventBits_t uxBitsToWaitFor,
-                                     const BaseType_t xClearOnExit,
-                                     const BaseType_t xWaitForAllBits,
-                                     TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                     const EventBits_t uxBitsToSet,
                                      const EventBits_t uxBitsToWaitFor,
-                                     const BaseType_t xClearOnExit,
-                                     const BaseType_t xWaitForAllBits,
                                      TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupWaitBitsImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
-        " MPU_xEventGroupWaitBits_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xEventGroupWaitBitsImpl                     \n"
-        " MPU_xEventGroupWaitBits_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupWaitBitsImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupSyncImpl                       \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xEventGroupSync_Unpriv                        \n"
+            " MPU_xEventGroupSync_Priv:                             \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xEventGroupSyncImpl                         \n"
+            " MPU_xEventGroupSync_Unpriv:                           \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupSyncImpl                        \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                      const EventBits_t uxBitsToClear ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                      const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupClearBitsImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xEventGroupClearBits_Unpriv                   \n"
-        " MPU_xEventGroupClearBits_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xEventGroupClearBitsImpl                    \n"
-        " MPU_xEventGroupClearBits_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupClearBitsImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxEventGroupGetNumberImpl                 \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxEventGroupGetNumber_Unpriv                  \n"
+                " MPU_uxEventGroupGetNumber_Priv:                       \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxEventGroupGetNumberImpl                   \n"
+                " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxEventGroupGetNumberImpl                  \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
 /*-----------------------------------------------------------*/
 
-EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                    const EventBits_t uxBitsToSet ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                    const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupSetBitsImpl                    \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xEventGroupSetBits_Unpriv                     \n"
-        " MPU_xEventGroupSetBits_Priv:                          \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xEventGroupSetBitsImpl                      \n"
-        " MPU_xEventGroupSetBits_Unpriv:                        \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupSetBitsImpl                     \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vEventGroupSetNumber( void * xEventGroup,
+                                       UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vEventGroupSetNumber( void * xEventGroup,
+                                       UBaseType_t uxEventGroupNumber ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vEventGroupSetNumberImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vEventGroupSetNumber_Unpriv                   \n"
+                " MPU_vEventGroupSetNumber_Priv:                        \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vEventGroupSetNumberImpl                    \n"
+                " MPU_vEventGroupSetNumber_Unpriv:                      \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vEventGroupSetNumberImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
 /*-----------------------------------------------------------*/
 
-EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                 const EventBits_t uxBitsToSet,
-                                 const EventBits_t uxBitsToWaitFor,
-                                 TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                  const void * pvTxData,
+                                  size_t xDataLengthBytes,
+                                  TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                 const EventBits_t uxBitsToSet,
-                                 const EventBits_t uxBitsToWaitFor,
-                                 TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupSyncImpl                       \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xEventGroupSync_Unpriv                        \n"
-        " MPU_xEventGroupSync_Priv:                             \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xEventGroupSyncImpl                         \n"
-        " MPU_xEventGroupSync_Unpriv:                           \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupSyncImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                  const void * pvTxData,
+                                  size_t xDataLengthBytes,
+                                  TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferSendImpl                     \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferSend_Unpriv                      \n"
+            " MPU_xStreamBufferSend_Priv:                           \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferSendImpl                       \n"
+            " MPU_xStreamBufferSend_Unpriv:                         \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferSendImpl                      \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                     void * pvRxData,
+                                     size_t xBufferLengthBytes,
+                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxEventGroupGetNumberImpl                 \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxEventGroupGetNumber_Unpriv                  \n"
-        " MPU_uxEventGroupGetNumber_Priv:                       \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxEventGroupGetNumberImpl                   \n"
-        " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxEventGroupGetNumberImpl                  \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                     void * pvRxData,
+                                     size_t xBufferLengthBytes,
+                                     TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferReceiveImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferReceive_Unpriv                   \n"
+            " MPU_xStreamBufferReceive_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferReceiveImpl                    \n"
+            " MPU_xStreamBufferReceive_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferReceiveImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vEventGroupSetNumber( void * xEventGroup,
-                               UBaseType_t uxEventGroupNumber ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vEventGroupSetNumber( void * xEventGroup,
-                               UBaseType_t uxEventGroupNumber ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vEventGroupSetNumberImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vEventGroupSetNumber_Unpriv                   \n"
-        " MPU_vEventGroupSetNumber_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vEventGroupSetNumberImpl                    \n"
-        " MPU_vEventGroupSetNumber_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vEventGroupSetNumberImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferIsFullImpl                   \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
+            " MPU_xStreamBufferIsFull_Priv:                         \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferIsFullImpl                     \n"
+            " MPU_xStreamBufferIsFull_Unpriv:                       \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferIsFullImpl                    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                              const void * pvTxData,
-                              size_t xDataLengthBytes,
-                              TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                              const void * pvTxData,
-                              size_t xDataLengthBytes,
-                              TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferSendImpl                     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferSend_Unpriv                      \n"
-        " MPU_xStreamBufferSend_Priv:                           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferSendImpl                       \n"
-        " MPU_xStreamBufferSend_Unpriv:                         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferSendImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
+            " MPU_xStreamBufferIsEmpty_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferIsEmptyImpl                    \n"
+            " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferIsEmptyImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                 void * pvRxData,
-                                 size_t xBufferLengthBytes,
-                                 TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                 void * pvRxData,
-                                 size_t xBufferLengthBytes,
-                                 TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferReceiveImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferReceive_Unpriv                   \n"
-        " MPU_xStreamBufferReceive_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferReceiveImpl                    \n"
-        " MPU_xStreamBufferReceive_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferReceiveImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
+            " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
+            " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferSpacesAvailableImpl           \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferIsFullImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
-        " MPU_xStreamBufferIsFull_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferIsFullImpl                     \n"
-        " MPU_xStreamBufferIsFull_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferIsFullImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
+            " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferBytesAvailableImpl             \n"
+            " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferBytesAvailableImpl            \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                 size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
-        " MPU_xStreamBufferIsEmpty_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferIsEmptyImpl                    \n"
-        " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferIsEmptyImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                 size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
+            " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
+            " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferSetTriggerLevelImpl           \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
-        " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
-        " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferSpacesAvailableImpl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
-size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
-        " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferBytesAvailableImpl             \n"
-        " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferBytesAvailableImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                             size_t xTriggerLevel ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                             size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
-        " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
-        " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferSetTriggerLevelImpl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
-size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
-        " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
-        " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferNextMessageLengthBytesImpl    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
+            " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
+            " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferNextMessageLengthBytesImpl    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
index 80410e82e..c940c304b 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
@@ -110,8 +110,8 @@
 /**
  * @brief Constants used during system call enter and exit.
  */
-#define portPSR_STACK_PADDING_MASK                ( 1UL << 9UL )
-#define portEXC_RETURN_STACK_FRAME_TYPE_MASK      ( 1UL << 4UL )
+#define portPSR_STACK_PADDING_MASK              ( 1UL << 9UL )
+#define portEXC_RETURN_STACK_FRAME_TYPE_MASK    ( 1UL << 4UL )
 /*-----------------------------------------------------------*/
 
 /**
@@ -133,81 +133,81 @@
 /**
  * @brief Offsets in the stack to the parameters when inside the SVC handler.
  */
-#define portOFFSET_TO_LR                    ( 5 )
-#define portOFFSET_TO_PC                    ( 6 )
-#define portOFFSET_TO_PSR                   ( 7 )
+#define portOFFSET_TO_LR     ( 5 )
+#define portOFFSET_TO_PC     ( 6 )
+#define portOFFSET_TO_PSR    ( 7 )
 /*-----------------------------------------------------------*/
 
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                      ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                      ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                       ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                      ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                      ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                     ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                     ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK  ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK               ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK               ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK               ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK               ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK               ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK               ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK               ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK               ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0              ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1              ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2              ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3              ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4              ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5              ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6              ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7              ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE            ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT      ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                      ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE             ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -216,11 +216,11 @@
 
 /* Extract last address of the MPU region as encoded in the
  * RLAR (Region Limit Address Register) value. */
-#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar )  \
+#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar ) \
     ( ( ( rlar ) & portMPU_RLAR_ADDRESS_MASK ) | ~portMPU_RLAR_ADDRESS_MASK )
 
 /* Does addr lies within [start, end] address range? */
-#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end )    \
+#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \
     ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) )
 
 /* Is the access request satisfied by the available permissions? */
@@ -422,54 +422,57 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the system call stack so that upon returning from
-     * SVC, the system call stack is used.
-     *
-     * It is used for the system calls with up to 4 parameters.
-     *
-     * @param pulTaskStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the system call stack so that upon returning from
+ * SVC, the system call stack is used.
+ *
+ * It is used for the system calls with up to 4 parameters.
+ *
+ * @param pulTaskStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallEnter( uint32_t * pulTaskStack,
+                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the system call stack so that upon returning from
-     * SVC, the system call stack is used.
-     *
-     * It is used for the system calls with 5 parameters.
-     *
-     * @param pulTaskStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the system call stack so that upon returning from
+ * SVC, the system call stack is used.
+ *
+ * It is used for the system calls with 5 parameters.
+ *
+ * @param pulTaskStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallEnter_1( uint32_t * pulTaskStack,
+                             uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the task stack so that upon returning from
-     * SVC, the task stack is used again.
-     *
-     * @param pulSystemCallStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the task stack so that upon returning from
+ * SVC, the task stack is used again.
+ *
+ * @param pulSystemCallStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallExit( uint32_t * pulSystemCallStack,
+                          uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Checks whether or not the calling task is privileged.
-     *
-     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
-     */
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
     BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
 
 #endif /* configENABLE_MPU == 1 */
@@ -1086,18 +1089,18 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             vRestoreContextOfFirstTask();
             break;
 
-        #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
-            case portSVC_RAISE_PRIVILEGE:
+            #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+                case portSVC_RAISE_PRIVILEGE:
 
-                /* Only raise the privilege, if the svc was raised from any of
-                 * the system calls. */
-                if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
-                    ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
-                {
-                    vRaisePrivilege();
-                }
-                break;
-        #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+                    /* Only raise the privilege, if the svc was raised from any of
+                     * the system calls. */
+                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+                    {
+                        vRaisePrivilege();
+                    }
+                    break;
+            #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
         default:
             /* Incorrect SVC call. */
@@ -1108,513 +1111,526 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulSystemCallStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallEnter( uint32_t * pulTaskStack,
+                           uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulSystemCallStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        /* This is not NULL only for the duration of the system call. */
-        configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+        #if defined( __ARMCC_VERSION )
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+
+            /* This is not NULL only for the duration of the system call. */
+            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the system call stack for the stack frame. */
+            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulSystemCallStack[ i ] = pulTaskStack[ i ];
+            }
+
+            /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
+             * restore it when we exit from the system call. */
+            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* Use the pulSystemCallStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+
+            /* Remember the location where we should copy the stack frame when we exit from
+             * the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+
+            /* Record if the hardware used padding to force the stack pointer
+             * to be double word aligned. */
+            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
+            {
+                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
             }
+
+            /* We ensure in pxPortInitialiseStack that the system call stack is
+             * double word aligned and therefore, there is no need of padding.
+             * Clear the bit[9] of stacked xPSR. */
+            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
+
+            /* Raise the privilege for the duration of the system call. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " bics r0, r1         \n" /* Clear nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the system call stack for the stack frame. */
-        pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulSystemCallStack[ i ] = pulTaskStack[ i ];
-        }
-
-        /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
-         * restore it when we exit from the system call. */
-        pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-        __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* Use the pulSystemCallStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-
-        /* Remember the location where we should copy the stack frame when we exit from
-         * the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-        /* Record if the hardware used padding to force the stack pointer
-         * to be double word aligned. */
-        if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-        {
-            pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-        }
-        else
-        {
-            pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-        }
-
-        /* We ensure in pxPortInitialiseStack that the system call stack is
-         * double word aligned and therefore, there is no need of padding.
-         * Clear the bit[9] of stacked xPSR. */
-        pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-        /* Raise the privilege for the duration of the system call. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " bics r0, r1         \n" /* Clear nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulSystemCallStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallEnter_1( uint32_t * pulTaskStack,
+                             uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulSystemCallStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        /* This is not NULL only for the duration of the system call. */
-        configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+        #if defined( __ARMCC_VERSION )
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+
+            /* This is not NULL only for the duration of the system call. */
+            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the system call stack for the stack frame and
+             * the parameter passed on the stack. We only need to copy one
+             * parameter but we still reserve 2 spaces to keep the stack
+             * double word aligned. */
+            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulSystemCallStack[ i ] = pulTaskStack[ i ];
+            }
+
+            /* Copy the parameter which is passed the stack. */
+            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
+            {
+                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
+
+                /* Record if the hardware used padding to force the stack pointer
+                 * to be double word aligned. */
+                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
+
+                /* Record if the hardware used padding to force the stack pointer
+                 * to be double word aligned. */
+                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
             }
+
+            /* Store the value of the LR and PSPLIM registers before the SVC was raised.
+             * We need to restore it when we exit from the system call. */
+            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* Use the pulSystemCallStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+
+            /* Remember the location where we should copy the stack frame when we exit from
+             * the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+
+            /* We ensure in pxPortInitialiseStack that the system call stack is
+             * double word aligned and therefore, there is no need of padding.
+             * Clear the bit[9] of stacked xPSR. */
+            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
+
+            /* Raise the privilege for the duration of the system call. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " bics r0, r1         \n" /* Clear nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the system call stack for the stack frame and
-         * the parameter passed on the stack. We only need to copy one
-         * parameter but we still reserve 2 spaces to keep the stack
-         * double word aligned. */
-        pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulSystemCallStack[ i ] = pulTaskStack[ i ];
-        }
-
-        /* Copy the parameter which is passed the stack. */
-        if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-        {
-            pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
-            /* Record if the hardware used padding to force the stack pointer
-             * to be double word aligned. */
-            pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-        }
-        else
-        {
-            pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
-            /* Record if the hardware used padding to force the stack pointer
-             * to be double word aligned. */
-            pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-        }
-
-        /* Store the value of the LR and PSPLIM registers before the SVC was raised.
-         * We need to restore it when we exit from the system call. */
-        pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-        __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* Use the pulSystemCallStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-
-        /* Remember the location where we should copy the stack frame when we exit from
-         * the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-        /* We ensure in pxPortInitialiseStack that the system call stack is
-         * double word aligned and therefore, there is no need of padding.
-         * Clear the bit[9] of stacked xPSR. */
-        pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-        /* Raise the privilege for the duration of the system call. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " bics r0, r1         \n" /* Clear nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulTaskStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallExit( uint32_t * pulSystemCallStack,
+                          uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulTaskStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+        #if defined( __ARMCC_VERSION )
+
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the task stack for the stack frame. */
+            pulTaskStack = pulTaskStack - ulStackFrameSize;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulTaskStack[ i ] = pulSystemCallStack[ i ];
+            }
+
+            /* Use the pulTaskStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
+
+            /* Restore the LR and PSPLIM to what they were at the time of
+             * system call entry. */
+            pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* If the hardware used padding to force the stack pointer
+             * to be double word aligned, set the stacked xPSR bit[9],
+             * otherwise clear it. */
+            if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG )
+            {
+                pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
             }
+
+            /* This is not NULL only for the duration of the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
+
+            /* Drop the privilege before returning to the thread mode. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " orrs r0, r1         \n" /* Set nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the task stack for the stack frame. */
-        pulTaskStack = pulTaskStack - ulStackFrameSize;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulTaskStack[ i ] = pulSystemCallStack[ i ];
-        }
-
-        /* Use the pulTaskStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
-
-        /* Restore the LR and PSPLIM to what they were at the time of
-         * system call entry. */
-        pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* If the hardware used padding to force the stack pointer
-         * to be double word aligned, set the stacked xPSR bit[9],
-         * otherwise clear it. */
-        if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG )
-        {
-            pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK;
-        }
-        else
-        {
-            pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-        }
-
-        /* This is not NULL only for the duration of the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
-
-        /* Drop the privilege before returning to the thread mode. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " orrs r0, r1         \n" /* Set nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */
-{
-    BaseType_t xTaskIsPrivileged = pdFALSE;
-    const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
-
-    if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+    BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */
     {
-        xTaskIsPrivileged = pdTRUE;
-    }
+        BaseType_t xTaskIsPrivileged = pdFALSE;
+        const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
 
-    return xTaskIsPrivileged;
-}
+        if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+        {
+            xTaskIsPrivileged = pdTRUE;
+        }
+
+        return xTaskIsPrivileged;
+    }
 
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
-#if( configENABLE_MPU == 1 )
+#if ( configENABLE_MPU == 1 )
 
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     StackType_t * pxEndOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters,
-                                     BaseType_t xRunPrivileged,
-                                     xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
-{
-    uint32_t ulIndex = 0;
-
-    xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
-    ulIndex++;
-
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
-    ulIndex++;
-
-    #if ( configENABLE_TRUSTZONE == 1 )
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters,
+                                         BaseType_t xRunPrivileged,
+                                         xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
     {
-        xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT;  /* xSecureContext. */
+        uint32_t ulIndex = 0;
+
+        xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
         ulIndex++;
-    }
-    #endif /* configENABLE_TRUSTZONE */
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
-    ulIndex++;
-    if( xRunPrivileged == pdTRUE )
-    {
-        xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */
         ulIndex++;
-    }
-    else
-    {
-        xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */
         ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
+        ulIndex++;
+
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters;            /* r0. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x01010101;                           /* r1. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x02020202;                           /* r2. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x03030303;                           /* r3. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x12121212;                           /* r12. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode;                  /* PC. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR;                     /* xPSR. */
+        ulIndex++;
+
+        #if ( configENABLE_TRUSTZONE == 1 )
+        {
+            xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT; /* xSecureContext. */
+            ulIndex++;
+        }
+        #endif /* configENABLE_TRUSTZONE */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
+        ulIndex++;
+
+        if( xRunPrivileged == pdTRUE )
+        {
+            xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
+            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+            ulIndex++;
+        }
+        else
+        {
+            xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
+            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+            ulIndex++;
+        }
+
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
+        ulIndex++;
+
+        #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+        {
+            /* Ensure that the system call stack is double word aligned. */
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] );
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) &
+                                                                                     ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
+
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] );
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) +
+                                                                                            ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) &
+                                                                                          ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
+
+            /* This is not NULL only for the duration of a system call. */
+            xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL;
+        }
+        #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
+
+        return &( xMPUSettings->ulContext[ ulIndex ] );
     }
-    xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
-    ulIndex++;
-
-    #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
-    {
-        /* Ensure that the system call stack is double word aligned. */
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] );
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) &
-                                                                                 ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
-
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] );
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) +
-                                                                                        ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) &
-                                                                                      ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
-
-        /* This is not NULL only for the duration of a system call. */
-        xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL;
-    }
-    #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
-
-    return &( xMPUSettings->ulContext[ ulIndex ] );
-}
 
 #else /* configENABLE_MPU */
 
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     StackType_t * pxEndOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters ) /* PRIVILEGED_FUNCTION */
-{
-    /* Simulate the stack frame as it would be created by a context switch
-     * interrupt. */
-    #if ( portPRELOAD_REGISTERS == 0 )
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters ) /* PRIVILEGED_FUNCTION */
     {
-        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-        pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
-        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-        pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
-        *pxTopOfStack = portINITIAL_EXC_RETURN;
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
-
-        #if ( configENABLE_TRUSTZONE == 1 )
+        /* Simulate the stack frame as it would be created by a context switch
+         * interrupt. */
+        #if ( portPRELOAD_REGISTERS == 0 )
         {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
-        }
-        #endif /* configENABLE_TRUSTZONE */
-    }
-    #else /* portPRELOAD_REGISTERS */
-    {
-        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
-        pxTopOfStack--;
-        *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
+            pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
+            *pxTopOfStack = portINITIAL_EXC_RETURN;
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+            #if ( configENABLE_TRUSTZONE == 1 )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+            }
+            #endif /* configENABLE_TRUSTZONE */
+        }
+        #else /* portPRELOAD_REGISTERS */
         {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
-        }
-        #endif /* configENABLE_TRUSTZONE */
-    }
-    #endif /* portPRELOAD_REGISTERS */
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
+            pxTopOfStack--;
+            *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack;            /* Slot used to hold this task's PSPLIM value. */
 
-    return pxTopOfStack;
-}
+            #if ( configENABLE_TRUSTZONE == 1 )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+            }
+            #endif /* configENABLE_TRUSTZONE */
+        }
+        #endif /* portPRELOAD_REGISTERS */
+
+        return pxTopOfStack;
+    }
 
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c b/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c
index 504b6bf3b..e533dd7e9 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c
@@ -42,111 +42,111 @@
 
 #if ( configENABLE_MPU == 1 )
 
-void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        " .syntax unified                                 \n"
-        "                                                 \n"
-        " program_mpu_first_task:                         \n"
-        "    ldr r2, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB. */
-        "                                                 \n"
-        "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-        "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
-        "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
-        "    str r2, [r1]                                 \n" /* Disable MPU. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
-        "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-        "    ldr r2, xMAIR0Const2                         \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-        "    str r1, [r2]                                 \n" /* Program MAIR0. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-        "    ldr r1, xRNRConst2                           \n" /* r1 = 0xe000ed98 [Location of RNR]. */
-        "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "                                                 \n"
-        "    movs r3, #4                                  \n" /* r3 = 4. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 4. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-        "                                                 \n"
-    #if ( configTOTAL_MPU_REGIONS == 16 )
-        "    movs r3, #8                                  \n" /* r3 = 8. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 8. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-        "    movs r3, #12                                 \n" /* r3 = 12. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 12. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-    #endif /* configTOTAL_MPU_REGIONS == 16 */
-        "                                                 \n"
-        "   ldr r1, xMPUCTRLConst2                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
-        "   orr r2, #1                                    \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
-        "   str r2, [r1]                                  \n" /* Enable MPU. */
-        "   dsb                                           \n" /* Force memory writes before continuing. */
-        "                                                 \n"
-        " restore_context_first_task:                     \n"
-        "    ldr r2, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB.*/
-        "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
-        "                                                 \n"
-        " restore_special_regs_first_task:                \n"
-        "    ldmdb r1!, {r2-r4, lr}                       \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
-        "    msr psp, r2                                  \n"
-        "    msr psplim, r3                               \n"
-        "    msr control, r4                              \n"
-        "                                                 \n"
-        " restore_general_regs_first_task:                \n"
-        "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
-        "    stmia r2!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
-        "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 restored. */
-        "                                                 \n"
-        " restore_context_done_first_task:                \n"
-        "    str r1, [r0]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
-        "    mov r0, #0                                   \n"
-        "    msr basepri, r0                              \n" /* Ensure that interrupts are enabled when the first task starts. */
-        "    bx lr                                        \n"
-        "                                                 \n"
-        " .align 4                                        \n"
-        " pxCurrentTCBConst2: .word pxCurrentTCB          \n"
-        " xMPUCTRLConst2: .word 0xe000ed94                \n"
-        " xMAIR0Const2: .word 0xe000edc0                  \n"
-        " xRNRConst2: .word 0xe000ed98                    \n"
-        " xRBARConst2: .word 0xe000ed9c                   \n"
-    );
-}
+    void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                 \n"
+            "                                                 \n"
+            " program_mpu_first_task:                         \n"
+            "    ldr r2, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB. */
+            "                                                 \n"
+            "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
+            "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
+            "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
+            "    str r2, [r1]                                 \n" /* Disable MPU. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
+            "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
+            "    ldr r2, xMAIR0Const2                         \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    str r1, [r2]                                 \n" /* Program MAIR0. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
+            "    ldr r1, xRNRConst2                           \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "                                                 \n"
+            "    movs r3, #4                                  \n" /* r3 = 4. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 4. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "                                                 \n"
+            #if ( configTOTAL_MPU_REGIONS == 16 )
+                "    movs r3, #8                                  \n" /* r3 = 8. */
+                "    str r3, [r1]                                 \n" /* Program RNR = 8. */
+                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+                "    movs r3, #12                                 \n" /* r3 = 12. */
+                "    str r3, [r1]                                 \n" /* Program RNR = 12. */
+                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            #endif /* configTOTAL_MPU_REGIONS == 16 */
+            "                                                 \n"
+            "   ldr r1, xMPUCTRLConst2                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
+            "   orr r2, #1                                    \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
+            "   str r2, [r1]                                  \n" /* Enable MPU. */
+            "   dsb                                           \n" /* Force memory writes before continuing. */
+            "                                                 \n"
+            " restore_context_first_task:                     \n"
+            "    ldr r2, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB.*/
+            "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
+            "                                                 \n"
+            " restore_special_regs_first_task:                \n"
+            "    ldmdb r1!, {r2-r4, lr}                       \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
+            "    msr psp, r2                                  \n"
+            "    msr psplim, r3                               \n"
+            "    msr control, r4                              \n"
+            "                                                 \n"
+            " restore_general_regs_first_task:                \n"
+            "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
+            "    stmia r2!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
+            "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 restored. */
+            "                                                 \n"
+            " restore_context_done_first_task:                \n"
+            "    str r1, [r0]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
+            "    mov r0, #0                                   \n"
+            "    msr basepri, r0                              \n" /* Ensure that interrupts are enabled when the first task starts. */
+            "    bx lr                                        \n"
+            "                                                 \n"
+            " .align 4                                        \n"
+            " pxCurrentTCBConst2: .word pxCurrentTCB          \n"
+            " xMPUCTRLConst2: .word 0xe000ed94                \n"
+            " xMAIR0Const2: .word 0xe000edc0                  \n"
+            " xRNRConst2: .word 0xe000ed98                    \n"
+            " xRBARConst2: .word 0xe000ed9c                   \n"
+        );
+    }
 
 #else /* configENABLE_MPU */
 
-void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "   .syntax unified                                 \n"
-        "                                                   \n"
-        "   ldr  r2, pxCurrentTCBConst2                     \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr  r1, [r2]                                   \n"/* Read pxCurrentTCB. */
-        "   ldr  r0, [r1]                                   \n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
-        "                                                   \n"
-        "   ldm  r0!, {r1-r2}                               \n"/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
-        "   msr  psplim, r1                                 \n"/* Set this task's PSPLIM value. */
-        "   movs r1, #2                                     \n"/* r1 = 2. */
-        "   msr  CONTROL, r1                                \n"/* Switch to use PSP in the thread mode. */
-        "   adds r0, #32                                    \n"/* Discard everything up to r0. */
-        "   msr  psp, r0                                    \n"/* This is now the new top of stack to use in the task. */
-        "   isb                                             \n"
-        "   mov  r0, #0                                     \n"
-        "   msr  basepri, r0                                \n"/* Ensure that interrupts are enabled when the first task starts. */
-        "   bx   r2                                         \n"/* Finally, branch to EXC_RETURN. */
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "pxCurrentTCBConst2: .word pxCurrentTCB             \n"
-    );
-}
+    void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            "   .syntax unified                                 \n"
+            "                                                   \n"
+            "   ldr  r2, pxCurrentTCBConst2                     \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr  r1, [r2]                                   \n" /* Read pxCurrentTCB. */
+            "   ldr  r0, [r1]                                   \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+            "                                                   \n"
+            "   ldm  r0!, {r1-r2}                               \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
+            "   msr  psplim, r1                                 \n" /* Set this task's PSPLIM value. */
+            "   movs r1, #2                                     \n" /* r1 = 2. */
+            "   msr  CONTROL, r1                                \n" /* Switch to use PSP in the thread mode. */
+            "   adds r0, #32                                    \n" /* Discard everything up to r0. */
+            "   msr  psp, r0                                    \n" /* This is now the new top of stack to use in the task. */
+            "   isb                                             \n"
+            "   mov  r0, #0                                     \n"
+            "   msr  basepri, r0                                \n" /* Ensure that interrupts are enabled when the first task starts. */
+            "   bx   r2                                         \n" /* Finally, branch to EXC_RETURN. */
+            "                                                   \n"
+            "   .align 4                                        \n"
+            "pxCurrentTCBConst2: .word pxCurrentTCB             \n"
+        );
+    }
 
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
@@ -157,12 +157,12 @@ BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs r0, control                                 \n"/* r0 = CONTROL. */
-        "   tst r0, #1                                      \n"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+        "   mrs r0, control                                 \n" /* r0 = CONTROL. */
+        "   tst r0, #1                                      \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
         "   ite ne                                          \n"
-        "   movne r0, #0                                    \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
-        "   moveq r0, #1                                    \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
-        "   bx lr                                           \n"/* Return. */
+        "   movne r0, #0                                    \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+        "   moveq r0, #1                                    \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+        "   bx lr                                           \n" /* Return. */
         "                                                   \n"
         "   .align 4                                        \n"
         ::: "r0", "memory"
@@ -176,10 +176,10 @@ void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs  r0, control                                \n"/* Read the CONTROL register. */
-        "   bic r0, #1                                      \n"/* Clear the bit 0. */
-        "   msr  control, r0                                \n"/* Write back the new CONTROL value. */
-        "   bx lr                                           \n"/* Return to the caller. */
+        "   mrs  r0, control                                \n" /* Read the CONTROL register. */
+        "   bic r0, #1                                      \n" /* Clear the bit 0. */
+        "   msr  control, r0                                \n" /* Write back the new CONTROL value. */
+        "   bx lr                                           \n" /* Return to the caller. */
         ::: "r0", "memory"
     );
 }
@@ -191,10 +191,10 @@ void vResetPrivilege( void ) /* __attribute__ (( naked )) */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs r0, control                                 \n"/* r0 = CONTROL. */
-        "   orr r0, #1                                      \n"/* r0 = r0 | 1. */
-        "   msr control, r0                                 \n"/* CONTROL = r0. */
-        "   bx lr                                           \n"/* Return to the caller. */
+        "   mrs r0, control                                 \n" /* r0 = CONTROL. */
+        "   orr r0, #1                                      \n" /* r0 = r0 | 1. */
+        "   msr control, r0                                 \n" /* CONTROL = r0. */
+        "   bx lr                                           \n" /* Return to the caller. */
         ::: "r0", "memory"
     );
 }
@@ -206,15 +206,15 @@ void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   ldr r0, xVTORConst                              \n"/* Use the NVIC offset register to locate the stack. */
-        "   ldr r0, [r0]                                    \n"/* Read the VTOR register which gives the address of vector table. */
-        "   ldr r0, [r0]                                    \n"/* The first entry in vector table is stack pointer. */
-        "   msr msp, r0                                     \n"/* Set the MSP back to the start of the stack. */
-        "   cpsie i                                         \n"/* Globally enable interrupts. */
+        "   ldr r0, xVTORConst                              \n" /* Use the NVIC offset register to locate the stack. */
+        "   ldr r0, [r0]                                    \n" /* Read the VTOR register which gives the address of vector table. */
+        "   ldr r0, [r0]                                    \n" /* The first entry in vector table is stack pointer. */
+        "   msr msp, r0                                     \n" /* Set the MSP back to the start of the stack. */
+        "   cpsie i                                         \n" /* Globally enable interrupts. */
         "   cpsie f                                         \n"
         "   dsb                                             \n"
         "   isb                                             \n"
-        "   svc %0                                          \n"/* System call to start the first task. */
+        "   svc %0                                          \n" /* System call to start the first task. */
         "   nop                                             \n"
         "                                                   \n"
         "   .align 4                                        \n"
@@ -230,12 +230,12 @@ uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCT
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs r0, basepri                                 \n"/* r0 = basepri. Return original basepri value. */
-        "   mov r1, %0                                      \n"/* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        "   msr basepri, r1                                 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        "   mrs r0, basepri                                 \n" /* r0 = basepri. Return original basepri value. */
+        "   mov r1, %0                                      \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        "   msr basepri, r1                                 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
         "   dsb                                             \n"
         "   isb                                             \n"
-        "   bx lr                                           \n"/* Return. */
+        "   bx lr                                           \n" /* Return. */
         ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
     );
 }
@@ -247,10 +247,10 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   msr basepri, r0                                 \n"/* basepri = ulMask. */
+        "   msr basepri, r0                                 \n" /* basepri = ulMask. */
         "   dsb                                             \n"
         "   isb                                             \n"
-        "   bx lr                                           \n"/* Return. */
+        "   bx lr                                           \n" /* Return. */
         ::: "memory"
     );
 }
@@ -258,246 +258,246 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
 
 #if ( configENABLE_MPU == 1 )
 
-void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        " .syntax unified                                 \n"
-        "                                                 \n"
-        " ldr r2, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        " ldr r0, [r2]                                    \n" /* r0 = pxCurrentTCB. */
-        " ldr r1, [r0]                                    \n" /* r1 = Location in TCB where the context should be saved. */
-        " mrs r2, psp                                     \n" /* r2 = PSP. */
-        "                                                 \n"
-        " save_general_regs:                              \n"
-    #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-        "    add r2, r2, #0x20                            \n" /* Move r2 to location where s0 is saved. */
-        "    tst lr, #0x10                                \n"
-        "    ittt eq                                      \n"
-        "    vstmiaeq r1!, {s16-s31}                      \n" /* Store s16-s31. */
-        "    vldmiaeq r2, {s0-s16}                        \n" /* Copy hardware saved FP context into s0-s16. */
-        "    vstmiaeq r1!, {s0-s16}                       \n" /* Store hardware saved FP context. */
-        "    sub r2, r2, #0x20                            \n" /* Set r2 back to the location of hardware saved context. */
-    #endif /* configENABLE_FPU || configENABLE_MVE */
-        "                                                 \n"
-        "    stmia r1!, {r4-r11}                          \n" /* Store r4-r11. */
-        "    ldmia r2, {r4-r11}                           \n" /* Copy the hardware saved context into r4-r11. */
-        "    stmia r1!, {r4-r11}                          \n" /* Store the hardware saved context. */
-        "                                                 \n"
-        " save_special_regs:                              \n"
-        "    mrs r3, psplim                               \n" /* r3 = PSPLIM. */
-        "    mrs r4, control                              \n" /* r4 = CONTROL. */
-        "    stmia r1!, {r2-r4, lr}                       \n" /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
-        "    str r1, [r0]                                 \n" /* Save the location from where the context should be restored as the first member of TCB. */
-        "                                                 \n"
-        " select_next_task:                               \n"
-        "    mov r0, %0                                   \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
-        "    msr basepri, r0                              \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        "    dsb                                          \n"
-        "    isb                                          \n"
-        "    bl vTaskSwitchContext                        \n"
-        "    mov r0, #0                                   \n" /* r0 = 0. */
-        "    msr basepri, r0                              \n" /* Enable interrupts. */
-        "                                                 \n"
-        " program_mpu:                                    \n"
-        "    ldr r2, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB. */
-        "                                                 \n"
-        "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-        "    ldr r1, xMPUCTRLConst                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
-        "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
-        "    str r2, [r1]                                 \n" /* Disable MPU. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
-        "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-        "    ldr r2, xMAIR0Const                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-        "    str r1, [r2]                                 \n" /* Program MAIR0. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-        "    ldr r1, xRNRConst                            \n" /* r1 = 0xe000ed98 [Location of RNR]. */
-        "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "                                                 \n"
-        "    movs r3, #4                                  \n" /* r3 = 4. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 4. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-        "                                                 \n"
-    #if ( configTOTAL_MPU_REGIONS == 16 )
-        "    movs r3, #8                                  \n" /* r3 = 8. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 8. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-        "    movs r3, #12                                 \n" /* r3 = 12. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 12. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-    #endif /* configTOTAL_MPU_REGIONS == 16 */
-        "                                                 \n"
-        "   ldr r1, xMPUCTRLConst                         \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
-        "   orr r2, #1                                    \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
-        "   str r2, [r1]                                  \n" /* Enable MPU. */
-        "   dsb                                           \n" /* Force memory writes before continuing. */
-        "                                                 \n"
-        " restore_context:                                \n"
-        "    ldr r2, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB.*/
-        "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
-        "                                                 \n"
-        " restore_special_regs:                           \n"
-        "    ldmdb r1!, {r2-r4, lr}                       \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
-        "    msr psp, r2                                  \n"
-        "    msr psplim, r3                               \n"
-        "    msr control, r4                              \n"
-        "                                                 \n"
-        " restore_general_regs:                           \n"
-        "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
-        "    stmia r2!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
-        "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 restored. */
-    #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-        "    tst lr, #0x10                                \n"
-        "    ittt eq                                      \n"
-        "    vldmdbeq r1!, {s0-s16}                       \n" /* s0-s16 contain hardware saved FP context. */
-        "    vstmiaeq r2!, {s0-s16}                       \n" /* Copy hardware saved FP context on the task stack. */
-        "    vldmdbeq r1!, {s16-s31}                      \n" /* Restore s16-s31. */
-    #endif /* configENABLE_FPU || configENABLE_MVE */
-        "                                                 \n"
-        " restore_context_done:                           \n"
-        "    str r1, [r0]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
-        "    bx lr                                        \n"
-        "                                                 \n"
-        " .align 4                                        \n"
-        " pxCurrentTCBConst: .word pxCurrentTCB           \n"
-        " xMPUCTRLConst: .word 0xe000ed94                 \n"
-        " xMAIR0Const: .word 0xe000edc0                   \n"
-        " xRNRConst: .word 0xe000ed98                     \n"
-        " xRBARConst: .word 0xe000ed9c                    \n"
-        ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
-    );
-}
+    void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                 \n"
+            "                                                 \n"
+            " ldr r2, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            " ldr r0, [r2]                                    \n" /* r0 = pxCurrentTCB. */
+            " ldr r1, [r0]                                    \n" /* r1 = Location in TCB where the context should be saved. */
+            " mrs r2, psp                                     \n" /* r2 = PSP. */
+            "                                                 \n"
+            " save_general_regs:                              \n"
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+                "    add r2, r2, #0x20                            \n" /* Move r2 to location where s0 is saved. */
+                "    tst lr, #0x10                                \n"
+                "    ittt eq                                      \n"
+                "    vstmiaeq r1!, {s16-s31}                      \n" /* Store s16-s31. */
+                "    vldmiaeq r2, {s0-s16}                        \n" /* Copy hardware saved FP context into s0-s16. */
+                "    vstmiaeq r1!, {s0-s16}                       \n" /* Store hardware saved FP context. */
+                "    sub r2, r2, #0x20                            \n" /* Set r2 back to the location of hardware saved context. */
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+            "                                                 \n"
+            "    stmia r1!, {r4-r11}                          \n" /* Store r4-r11. */
+            "    ldmia r2, {r4-r11}                           \n" /* Copy the hardware saved context into r4-r11. */
+            "    stmia r1!, {r4-r11}                          \n" /* Store the hardware saved context. */
+            "                                                 \n"
+            " save_special_regs:                              \n"
+            "    mrs r3, psplim                               \n" /* r3 = PSPLIM. */
+            "    mrs r4, control                              \n" /* r4 = CONTROL. */
+            "    stmia r1!, {r2-r4, lr}                       \n" /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
+            "    str r1, [r0]                                 \n" /* Save the location from where the context should be restored as the first member of TCB. */
+            "                                                 \n"
+            " select_next_task:                               \n"
+            "    mov r0, %0                                   \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
+            "    msr basepri, r0                              \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+            "    dsb                                          \n"
+            "    isb                                          \n"
+            "    bl vTaskSwitchContext                        \n"
+            "    mov r0, #0                                   \n" /* r0 = 0. */
+            "    msr basepri, r0                              \n" /* Enable interrupts. */
+            "                                                 \n"
+            " program_mpu:                                    \n"
+            "    ldr r2, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB. */
+            "                                                 \n"
+            "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
+            "    ldr r1, xMPUCTRLConst                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
+            "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
+            "    str r2, [r1]                                 \n" /* Disable MPU. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
+            "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
+            "    ldr r2, xMAIR0Const                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    str r1, [r2]                                 \n" /* Program MAIR0. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
+            "    ldr r1, xRNRConst                            \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "                                                 \n"
+            "    movs r3, #4                                  \n" /* r3 = 4. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 4. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "                                                 \n"
+            #if ( configTOTAL_MPU_REGIONS == 16 )
+                "    movs r3, #8                                  \n" /* r3 = 8. */
+                "    str r3, [r1]                                 \n" /* Program RNR = 8. */
+                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+                "    movs r3, #12                                 \n" /* r3 = 12. */
+                "    str r3, [r1]                                 \n" /* Program RNR = 12. */
+                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            #endif /* configTOTAL_MPU_REGIONS == 16 */
+            "                                                 \n"
+            "   ldr r1, xMPUCTRLConst                         \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
+            "   orr r2, #1                                    \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
+            "   str r2, [r1]                                  \n" /* Enable MPU. */
+            "   dsb                                           \n" /* Force memory writes before continuing. */
+            "                                                 \n"
+            " restore_context:                                \n"
+            "    ldr r2, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB.*/
+            "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
+            "                                                 \n"
+            " restore_special_regs:                           \n"
+            "    ldmdb r1!, {r2-r4, lr}                       \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
+            "    msr psp, r2                                  \n"
+            "    msr psplim, r3                               \n"
+            "    msr control, r4                              \n"
+            "                                                 \n"
+            " restore_general_regs:                           \n"
+            "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
+            "    stmia r2!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
+            "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 restored. */
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+                "    tst lr, #0x10                                \n"
+                "    ittt eq                                      \n"
+                "    vldmdbeq r1!, {s0-s16}                       \n" /* s0-s16 contain hardware saved FP context. */
+                "    vstmiaeq r2!, {s0-s16}                       \n" /* Copy hardware saved FP context on the task stack. */
+                "    vldmdbeq r1!, {s16-s31}                      \n" /* Restore s16-s31. */
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+            "                                                 \n"
+            " restore_context_done:                           \n"
+            "    str r1, [r0]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
+            "    bx lr                                        \n"
+            "                                                 \n"
+            " .align 4                                        \n"
+            " pxCurrentTCBConst: .word pxCurrentTCB           \n"
+            " xMPUCTRLConst: .word 0xe000ed94                 \n"
+            " xMAIR0Const: .word 0xe000edc0                   \n"
+            " xRNRConst: .word 0xe000ed98                     \n"
+            " xRBARConst: .word 0xe000ed9c                    \n"
+            ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+        );
+    }
 
 #else /* configENABLE_MPU */
 
-void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "   .syntax unified                                 \n"
-        "                                                   \n"
-        "   mrs r0, psp                                     \n"/* Read PSP in r0. */
-        "                                                   \n"
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-            "   tst lr, #0x10                                   \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
-            "   it eq                                           \n"
-            "   vstmdbeq r0!, {s16-s31}                         \n"/* Store the additional FP context registers which are not saved automatically. */
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-        "                                                   \n"
-        "   mrs r2, psplim                                  \n"/* r2 = PSPLIM. */
-        "   mov r3, lr                                      \n"/* r3 = LR/EXC_RETURN. */
-        "   stmdb r0!, {r2-r11}                             \n"/* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */
-        "                                                   \n"
-        "   ldr r2, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r2]                                    \n"/* Read pxCurrentTCB. */
-        "   str r0, [r1]                                    \n"/* Save the new top of stack in TCB. */
-        "                                                   \n"
-        "   mov r0, %0                                      \n"/* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
-        "   msr basepri, r0                                 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        "   dsb                                             \n"
-        "   isb                                             \n"
-        "   bl vTaskSwitchContext                           \n"
-        "   mov r0, #0                                      \n"/* r0 = 0. */
-        "   msr basepri, r0                                 \n"/* Enable interrupts. */
-        "                                                   \n"
-        "   ldr r2, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r2]                                    \n"/* Read pxCurrentTCB. */
-        "   ldr r0, [r1]                                    \n"/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
-        "                                                   \n"
-        "   ldmia r0!, {r2-r11}                             \n"/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
-        "                                                   \n"
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-            "   tst r3, #0x10                                   \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
-            "   it eq                                           \n"
-            "   vldmiaeq r0!, {s16-s31}                         \n"/* Restore the additional FP context registers which are not restored automatically. */
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-        "                                                   \n"
-        "   msr psplim, r2                                  \n"/* Restore the PSPLIM register value for the task. */
-        "   msr psp, r0                                     \n"/* Remember the new top of stack for the task. */
-        "   bx r3                                           \n"
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "pxCurrentTCBConst: .word pxCurrentTCB              \n"
-        ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
-    );
-}
+    void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            "   .syntax unified                                 \n"
+            "                                                   \n"
+            "   mrs r0, psp                                     \n" /* Read PSP in r0. */
+            "                                                   \n"
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+                "   tst lr, #0x10                                   \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+                "   it eq                                           \n"
+                "   vstmdbeq r0!, {s16-s31}                         \n" /* Store the additional FP context registers which are not saved automatically. */
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+            "                                                   \n"
+            "   mrs r2, psplim                                  \n" /* r2 = PSPLIM. */
+            "   mov r3, lr                                      \n" /* r3 = LR/EXC_RETURN. */
+            "   stmdb r0!, {r2-r11}                             \n" /* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */
+            "                                                   \n"
+            "   ldr r2, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r1, [r2]                                    \n" /* Read pxCurrentTCB. */
+            "   str r0, [r1]                                    \n" /* Save the new top of stack in TCB. */
+            "                                                   \n"
+            "   mov r0, %0                                      \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
+            "   msr basepri, r0                                 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+            "   dsb                                             \n"
+            "   isb                                             \n"
+            "   bl vTaskSwitchContext                           \n"
+            "   mov r0, #0                                      \n" /* r0 = 0. */
+            "   msr basepri, r0                                 \n" /* Enable interrupts. */
+            "                                                   \n"
+            "   ldr r2, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r1, [r2]                                    \n" /* Read pxCurrentTCB. */
+            "   ldr r0, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
+            "                                                   \n"
+            "   ldmia r0!, {r2-r11}                             \n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
+            "                                                   \n"
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+                "   tst r3, #0x10                                   \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+                "   it eq                                           \n"
+                "   vldmiaeq r0!, {s16-s31}                         \n" /* Restore the additional FP context registers which are not restored automatically. */
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+            "                                                   \n"
+            "   msr psplim, r2                                  \n" /* Restore the PSPLIM register value for the task. */
+            "   msr psp, r0                                     \n" /* Remember the new top of stack for the task. */
+            "   bx r3                                           \n"
+            "                                                   \n"
+            "   .align 4                                        \n"
+            "pxCurrentTCBConst: .word pxCurrentTCB              \n"
+            ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+        );
+    }
 
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-   __asm volatile
-    (
-        ".syntax unified                \n"
-        ".extern vPortSVCHandler_C      \n"
-        ".extern vSystemCallEnter       \n"
-        ".extern vSystemCallEnter_1     \n"
-        ".extern vSystemCallExit        \n"
-        "                               \n"
-        "tst lr, #4                     \n"
-        "ite eq                         \n"
-        "mrseq r0, msp                  \n"
-        "mrsne r0, psp                  \n"
-        "                               \n"
-        "ldr r1, [r0, #24]              \n"
-        "ldrb r2, [r1, #-2]             \n"
-        "cmp r2, %0                     \n"
-        "beq syscall_enter              \n"
-        "cmp r2, %1                     \n"
-        "beq syscall_enter_1            \n"
-        "cmp r2, %2                     \n"
-        "beq syscall_exit               \n"
-        "b vPortSVCHandler_C            \n"
-        "                               \n"
-        "syscall_enter:                 \n"
-        "    mov r1, lr                 \n"
-        "    b vSystemCallEnter         \n"
-        "                               \n"
-        "syscall_enter_1:               \n"
-        "    mov r1, lr                 \n"
-        "    b vSystemCallEnter_1       \n"
-        "                               \n"
-        "syscall_exit:                  \n"
-        "    mov r1, lr                 \n"
-        "    b vSystemCallExit          \n"
-        "                               \n"
-        : /* No outputs. */
-        :"i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT )
-        : "r0", "r1", "r2", "memory"
-    );
-}
+    void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            ".syntax unified                \n"
+            ".extern vPortSVCHandler_C      \n"
+            ".extern vSystemCallEnter       \n"
+            ".extern vSystemCallEnter_1     \n"
+            ".extern vSystemCallExit        \n"
+            "                               \n"
+            "tst lr, #4                     \n"
+            "ite eq                         \n"
+            "mrseq r0, msp                  \n"
+            "mrsne r0, psp                  \n"
+            "                               \n"
+            "ldr r1, [r0, #24]              \n"
+            "ldrb r2, [r1, #-2]             \n"
+            "cmp r2, %0                     \n"
+            "beq syscall_enter              \n"
+            "cmp r2, %1                     \n"
+            "beq syscall_enter_1            \n"
+            "cmp r2, %2                     \n"
+            "beq syscall_exit               \n"
+            "b vPortSVCHandler_C            \n"
+            "                               \n"
+            "syscall_enter:                 \n"
+            "    mov r1, lr                 \n"
+            "    b vSystemCallEnter         \n"
+            "                               \n"
+            "syscall_enter_1:               \n"
+            "    mov r1, lr                 \n"
+            "    b vSystemCallEnter_1       \n"
+            "                               \n"
+            "syscall_exit:                  \n"
+            "    mov r1, lr                 \n"
+            "    b vSystemCallExit          \n"
+            "                               \n"
+            : /* No outputs. */
+            : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT )
+            : "r0", "r1", "r2", "memory"
+        );
+    }
 
 #else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
-void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "   .syntax unified                                 \n"
-        "                                                   \n"
-        "   tst lr, #4                                      \n"
-        "   ite eq                                          \n"
-        "   mrseq r0, msp                                   \n"
-        "   mrsne r0, psp                                   \n"
-        "   ldr r1, svchandler_address_const                \n"
-        "   bx r1                                           \n"
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "svchandler_address_const: .word vPortSVCHandler_C  \n"
-    );
-}
+    void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            "   .syntax unified                                 \n"
+            "                                                   \n"
+            "   tst lr, #4                                      \n"
+            "   ite eq                                          \n"
+            "   mrseq r0, msp                                   \n"
+            "   mrsne r0, psp                                   \n"
+            "   ldr r1, svchandler_address_const                \n"
+            "   bx r1                                           \n"
+            "                                                   \n"
+            "   .align 4                                        \n"
+            "svchandler_address_const: .word vPortSVCHandler_C  \n"
+        );
+    }
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h b/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h
index 428d38f0a..227327ac8 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h
@@ -48,9 +48,9 @@
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME                       "Cortex-M33"
-#define portHAS_ARMV8M_MAIN_EXTENSION       1
-#define portDONT_DISCARD                    __attribute__( ( used ) )
+#define portARCH_NAME                    "Cortex-M33"
+#define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
 /* ARMv8-M common port configurations. */
@@ -60,8 +60,8 @@
 /**
  * @brief Critical section management.
  */
-#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()
-#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )
+#define portDISABLE_INTERRUPTS()    ulSetInterruptMask()
+#define portENABLE_INTERRUPTS()     vClearInterruptMask( 0 )
 /*-----------------------------------------------------------*/
 
 /* *INDENT-OFF* */
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h
index e5ffdb48b..62e462a27 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h
@@ -81,8 +81,8 @@ typedef unsigned long    UBaseType_t;
     typedef uint32_t     TickType_t;
     #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-     * not need to be guarded with a critical section. */
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
     #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -117,7 +117,7 @@ extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGE
 extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
 
 #if ( configENABLE_TRUSTZONE == 1 )
-    extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize );     /* __attribute__ (( naked )) */
+    extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
     extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
 #endif /* configENABLE_TRUSTZONE */
 
@@ -188,13 +188,13 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Settings to define an MPU region.
-     */
+/**
+ * @brief Settings to define an MPU region.
+ */
     typedef struct MPURegionSettings
     {
-        uint32_t ulRBAR;     /**< RBAR for the region. */
-        uint32_t ulRLAR;     /**< RLAR for the region. */
+        uint32_t ulRBAR; /**< RBAR for the region. */
+        uint32_t ulRLAR; /**< RLAR for the region. */
     } MPURegionSettings_t;
 
     #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
@@ -203,9 +203,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-        /**
-         * @brief System call stack.
-         */
+/**
+ * @brief System call stack.
+ */
         typedef struct SYSTEM_CALL_STACK_INFO
         {
             uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ];
@@ -218,74 +218,74 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
-    /**
-     * @brief MPU settings as stored in the TCB.
-     */
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
     #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
 
-        #if( configENABLE_TRUSTZONE == 1 )
+        #if ( configENABLE_TRUSTZONE == 1 )
 
-            /*
-             * +-----------+---------------+----------+-----------------+------------------------------+-----+
-             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
-             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
-             * +-----------+---------------+----------+-----------------+------------------------------+-----+
-             *
-             * <-----------><--------------><---------><----------------><-----------------------------><---->
-             *      16             16            8               8                     5                   1
-             */
-            #define MAX_CONTEXT_SIZE 54
+/*
+ * +-----------+---------------+----------+-----------------+------------------------------+-----+
+ * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+ * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+ * +-----------+---------------+----------+-----------------+------------------------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><-----------------------------><---->
+ *      16             16            8               8                     5                   1
+ */
+            #define MAX_CONTEXT_SIZE    54
 
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-            /*
-             * +-----------+---------------+----------+-----------------+----------------------+-----+
-             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
-             * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
-             * +-----------+---------------+----------+-----------------+----------------------+-----+
-             *
-             * <-----------><--------------><---------><----------------><---------------------><---->
-             *      16             16            8               8                  4              1
-             */
-            #define MAX_CONTEXT_SIZE 53
+/*
+ * +-----------+---------------+----------+-----------------+----------------------+-----+
+ * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+ * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
+ * +-----------+---------------+----------+-----------------+----------------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><---------------------><---->
+ *      16             16            8               8                  4              1
+ */
+            #define MAX_CONTEXT_SIZE    53
 
         #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
 
     #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-        #if( configENABLE_TRUSTZONE == 1 )
+        #if ( configENABLE_TRUSTZONE == 1 )
 
-            /*
-             * +----------+-----------------+------------------------------+-----+
-             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
-             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
-             * +----------+-----------------+------------------------------+-----+
-             *
-             * <---------><----------------><------------------------------><---->
-             *     8               8                      5                   1
-             */
-            #define MAX_CONTEXT_SIZE 22
+/*
+ * +----------+-----------------+------------------------------+-----+
+ * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+ * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+ * +----------+-----------------+------------------------------+-----+
+ *
+ * <---------><----------------><------------------------------><---->
+ *     8               8                      5                   1
+ */
+            #define MAX_CONTEXT_SIZE    22
 
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-            /*
-             * +----------+-----------------+----------------------+-----+
-             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
-             * |          | PC, xPSR        | EXC_RETURN           |     |
-             * +----------+-----------------+----------------------+-----+
-             *
-             * <---------><----------------><----------------------><---->
-             *     8               8                  4              1
-             */
-            #define MAX_CONTEXT_SIZE 21
+/*
+ * +----------+-----------------+----------------------+-----+
+ * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+ * |          | PC, xPSR        | EXC_RETURN           |     |
+ * +----------+-----------------+----------------------+-----+
+ *
+ * <---------><----------------><----------------------><---->
+ *     8               8                  4              1
+ */
+            #define MAX_CONTEXT_SIZE    21
 
         #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
 
     #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-    /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
-    #define portSTACK_FRAME_HAS_PADDING_FLAG     ( 1UL << 0UL )
-    #define portTASK_IS_PRIVILEGED_FLAG          ( 1UL << 1UL )
+/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
+    #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
+    #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
     typedef struct MPU_SETTINGS
     {
@@ -364,49 +364,49 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-    /**
-     * @brief Allocate a secure context for the task.
-     *
-     * Tasks are not created with a secure context. Any task that is going to call
-     * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
-     * secure context before it calls any secure function.
-     *
-     * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
-     */
+/**
+ * @brief Allocate a secure context for the task.
+ *
+ * Tasks are not created with a secure context. Any task that is going to call
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+ * secure context before it calls any secure function.
+ *
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+ */
     #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
 
-    /**
-     * @brief Called when a task is deleted to delete the task's secure context,
-     * if it has one.
-     *
-     * @param[in] pxTCB The TCB of the task being deleted.
-     */
+/**
+ * @brief Called when a task is deleted to delete the task's secure context,
+ * if it has one.
+ *
+ * @param[in] pxTCB The TCB of the task being deleted.
+ */
     #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
 #endif /* configENABLE_TRUSTZONE */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Checks whether or not the processor is privileged.
-     *
-     * @return 1 if the processor is already privileged, 0 otherwise.
-     */
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
     #define portIS_PRIVILEGED()      xIsPrivileged()
 
-    /**
-     * @brief Raise an SVC request to raise privilege.
-     *
-     * The SVC handler checks that the SVC was raised from a system call and only
-     * then it raises the privilege. If this is called from any other place,
-     * the privilege is not raised.
-     */
+/**
+ * @brief Raise an SVC request to raise privilege.
+ *
+ * The SVC handler checks that the SVC was raised from a system call and only
+ * then it raises the privilege. If this is called from any other place,
+ * the privilege is not raised.
+ */
     #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
 
-    /**
-     * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
-     * register.
-     */
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
     #define portRESET_PRIVILEGE()    vResetPrivilege()
 #else
     #define portIS_PRIVILEGED()
@@ -419,12 +419,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     extern BaseType_t xPortIsTaskPrivileged( void );
 
-    /**
-     * @brief Checks whether or not the calling task is privileged.
-     *
-     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
-     */
-    #define portIS_TASK_PRIVILEGED()      xPortIsTaskPrivileged()
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
+    #define portIS_TASK_PRIVILEGED()    xPortIsTaskPrivileged()
 
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
@@ -439,9 +439,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * based on whether or not Mainline extension is implemented. */
 #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
     #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
-        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
     #else
-        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    0
     #endif
 #endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
 
@@ -450,9 +450,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  */
 #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
 
-    /**
-     * @brief Count the number of leading zeros in a 32-bit value.
-     */
+/**
+ * @brief Count the number of leading zeros in a 32-bit value.
+ */
     static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
     {
         uint32_t ulReturn;
@@ -462,7 +462,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         return ulReturn;
     }
 
-    /* Check the configuration. */
+/* Check the configuration. */
     #if ( configMAX_PRIORITIES > 32 )
         #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
     #endif
@@ -471,16 +471,16 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection.  Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
     #endif
 
-    /**
-     * @brief Store/clear the ready priorities in a bit map.
-     */
-    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+/**
+ * @brief Store/clear the ready priorities in a bit map.
+ */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )      ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )       ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 
-    /**
-     * @brief Get the priority of the highest-priority task that is ready to execute.
-     */
-    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )   uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+/**
+ * @brief Get the priority of the highest-priority task that is ready to execute.
+ */
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
 
 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.c
index 2d1218a95..d1fbdc0e5 100644
--- a/portable/GCC/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.c
@@ -44,2274 +44,2274 @@
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-#if ( INCLUDE_xTaskDelayUntil == 1 )
+    #if ( INCLUDE_xTaskDelayUntil == 1 )
 
-BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
-                                const TickType_t xTimeIncrement ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
+                                        const TickType_t xTimeIncrement ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
-                                const TickType_t xTimeIncrement ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskDelayUntilImpl                       \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskDelayUntil_Unpriv                        \n"
-        " MPU_xTaskDelayUntil_Priv:                             \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskDelayUntilImpl                         \n"
-        " MPU_xTaskDelayUntil_Unpriv:                           \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskDelayUntilImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
+                                        const TickType_t xTimeIncrement ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskDelayUntilImpl                       \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskDelayUntil_Unpriv                        \n"
+                " MPU_xTaskDelayUntil_Priv:                             \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskDelayUntilImpl                         \n"
+                " MPU_xTaskDelayUntil_Unpriv:                           \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskDelayUntilImpl                        \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */
+    #endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_xTaskAbortDelay == 1 )
+    #if ( INCLUDE_xTaskAbortDelay == 1 )
 
-BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskAbortDelayImpl                       \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskAbortDelay_Unpriv                        \n"
-        " MPU_xTaskAbortDelay_Priv:                             \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskAbortDelayImpl                         \n"
-        " MPU_xTaskAbortDelay_Unpriv:                           \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskAbortDelayImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskAbortDelayImpl                       \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskAbortDelay_Unpriv                        \n"
+                " MPU_xTaskAbortDelay_Priv:                             \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskAbortDelayImpl                         \n"
+                " MPU_xTaskAbortDelay_Unpriv:                           \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskAbortDelayImpl                        \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */
+    #endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_vTaskDelay == 1 )
+    #if ( INCLUDE_vTaskDelay == 1 )
 
-void MPU_vTaskDelay( const TickType_t xTicksToDelay ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskDelay( const TickType_t xTicksToDelay ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskDelayImpl                            \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskDelay_Unpriv                             \n"
-        " MPU_vTaskDelay_Priv:                                  \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskDelayImpl                              \n"
-        " MPU_vTaskDelay_Unpriv:                                \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskDelayImpl                             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskDelayImpl                            \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskDelay_Unpriv                             \n"
+                " MPU_vTaskDelay_Priv:                                  \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskDelayImpl                              \n"
+                " MPU_vTaskDelay_Unpriv:                                \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskDelayImpl                             \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_vTaskDelay == 1 ) */
+    #endif /* if ( INCLUDE_vTaskDelay == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_uxTaskPriorityGet == 1 )
+    #if ( INCLUDE_uxTaskPriorityGet == 1 )
 
-UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskPriorityGetImpl                     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTaskPriorityGet_Unpriv                      \n"
-        " MPU_uxTaskPriorityGet_Priv:                           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTaskPriorityGetImpl                       \n"
-        " MPU_uxTaskPriorityGet_Unpriv:                         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskPriorityGetImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskPriorityGetImpl                     \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTaskPriorityGet_Unpriv                      \n"
+                " MPU_uxTaskPriorityGet_Priv:                           \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTaskPriorityGetImpl                       \n"
+                " MPU_uxTaskPriorityGet_Unpriv:                         \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskPriorityGetImpl                      \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */
+    #endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_eTaskGetState == 1 )
+    #if ( INCLUDE_eTaskGetState == 1 )
 
-eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_eTaskGetStateImpl                         \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_eTaskGetState_Unpriv                          \n"
-        " MPU_eTaskGetState_Priv:                               \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_eTaskGetStateImpl                           \n"
-        " MPU_eTaskGetState_Unpriv:                             \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_eTaskGetStateImpl                          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_eTaskGetStateImpl                         \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_eTaskGetState_Unpriv                          \n"
+                " MPU_eTaskGetState_Priv:                               \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_eTaskGetStateImpl                           \n"
+                " MPU_eTaskGetState_Unpriv:                             \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_eTaskGetStateImpl                          \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_eTaskGetState == 1 ) */
+    #endif /* if ( INCLUDE_eTaskGetState == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-void MPU_vTaskGetInfo( TaskHandle_t xTask,
-                       TaskStatus_t * pxTaskStatus,
-                       BaseType_t xGetFreeStackSpace,
-                       eTaskState eState ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskGetInfo( TaskHandle_t xTask,
+                               TaskStatus_t * pxTaskStatus,
+                               BaseType_t xGetFreeStackSpace,
+                               eTaskState eState ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskGetInfo( TaskHandle_t xTask,
-                       TaskStatus_t * pxTaskStatus,
-                       BaseType_t xGetFreeStackSpace,
-                       eTaskState eState ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskGetInfoImpl                          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskGetInfo_Unpriv                           \n"
-        " MPU_vTaskGetInfo_Priv:                                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskGetInfoImpl                            \n"
-        " MPU_vTaskGetInfo_Unpriv:                              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskGetInfoImpl                           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskGetInfo( TaskHandle_t xTask,
+                               TaskStatus_t * pxTaskStatus,
+                               BaseType_t xGetFreeStackSpace,
+                               eTaskState eState ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskGetInfoImpl                          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskGetInfo_Unpriv                           \n"
+                " MPU_vTaskGetInfo_Priv:                                \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskGetInfoImpl                            \n"
+                " MPU_vTaskGetInfo_Unpriv:                              \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskGetInfoImpl                           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
+    #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
+    #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
 
-TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetIdleTaskHandleImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGetIdleTaskHandle_Unpriv                 \n"
-        " MPU_xTaskGetIdleTaskHandle_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGetIdleTaskHandleImpl                  \n"
-        " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetIdleTaskHandleImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetIdleTaskHandleImpl                \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGetIdleTaskHandle_Unpriv                 \n"
+                " MPU_xTaskGetIdleTaskHandle_Priv:                      \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGetIdleTaskHandleImpl                  \n"
+                " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetIdleTaskHandleImpl                 \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */
+    #endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_vTaskSuspend == 1 )
+    #if ( INCLUDE_vTaskSuspend == 1 )
 
-void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSuspendImpl                          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskSuspend_Unpriv                           \n"
-        " MPU_vTaskSuspend_Priv:                                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskSuspendImpl                            \n"
-        " MPU_vTaskSuspend_Unpriv:                              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSuspendImpl                           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskSuspendImpl                          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskSuspend_Unpriv                           \n"
+                " MPU_vTaskSuspend_Priv:                                \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskSuspendImpl                            \n"
+                " MPU_vTaskSuspend_Unpriv:                              \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskSuspendImpl                           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
+    #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_vTaskSuspend == 1 )
+    #if ( INCLUDE_vTaskSuspend == 1 )
 
-void MPU_vTaskResume( TaskHandle_t xTaskToResume ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskResume( TaskHandle_t xTaskToResume ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskResumeImpl                           \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskResume_Unpriv                            \n"
-        " MPU_vTaskResume_Priv:                                 \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskResumeImpl                             \n"
-        " MPU_vTaskResume_Unpriv:                               \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskResumeImpl                            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskResumeImpl                           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskResume_Unpriv                            \n"
+                " MPU_vTaskResume_Priv:                                 \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskResumeImpl                             \n"
+                " MPU_vTaskResume_Unpriv:                               \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskResumeImpl                            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
+    #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
 /*-----------------------------------------------------------*/
 
-TickType_t MPU_xTaskGetTickCount( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    TickType_t MPU_xTaskGetTickCount( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TickType_t MPU_xTaskGetTickCount( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetTickCountImpl                     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGetTickCount_Unpriv                      \n"
-        " MPU_xTaskGetTickCount_Priv:                           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGetTickCountImpl                       \n"
-        " MPU_xTaskGetTickCount_Unpriv:                         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetTickCountImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    TickType_t MPU_xTaskGetTickCount( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xTaskGetTickCountImpl                     \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xTaskGetTickCount_Unpriv                      \n"
+            " MPU_xTaskGetTickCount_Priv:                           \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xTaskGetTickCountImpl                       \n"
+            " MPU_xTaskGetTickCount_Unpriv:                         \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xTaskGetTickCountImpl                      \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetNumberOfTasksImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTaskGetNumberOfTasks_Unpriv                 \n"
-        " MPU_uxTaskGetNumberOfTasks_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTaskGetNumberOfTasksImpl                  \n"
-        " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetNumberOfTasksImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_uxTaskGetNumberOfTasksImpl                \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_uxTaskGetNumberOfTasks_Unpriv                 \n"
+            " MPU_uxTaskGetNumberOfTasks_Priv:                      \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_uxTaskGetNumberOfTasksImpl                  \n"
+            " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_uxTaskGetNumberOfTasksImpl                 \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configGENERATE_RUN_TIME_STATS == 1 )
+    #if ( configGENERATE_RUN_TIME_STATS == 1 )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetRunTimeCounterImpl               \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGetRunTimeCounter_Unpriv                \n"
-        " MPU_ulTaskGetRunTimeCounter_Priv:                     \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGetRunTimeCounterImpl                 \n"
-        " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetRunTimeCounterImpl                \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetRunTimeCounterImpl               \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGetRunTimeCounter_Unpriv                \n"
+                " MPU_ulTaskGetRunTimeCounter_Priv:                     \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGetRunTimeCounterImpl                 \n"
+                " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetRunTimeCounterImpl                \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configGENERATE_RUN_TIME_STATS == 1 )
+    #if ( configGENERATE_RUN_TIME_STATS == 1 )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetRunTimePercentImpl               \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGetRunTimePercent_Unpriv                \n"
-        " MPU_ulTaskGetRunTimePercent_Priv:                     \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGetRunTimePercentImpl                 \n"
-        " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetRunTimePercentImpl                \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetRunTimePercentImpl               \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGetRunTimePercent_Unpriv                \n"
+                " MPU_ulTaskGetRunTimePercent_Priv:                     \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGetRunTimePercentImpl                 \n"
+                " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetRunTimePercentImpl                \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+    #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetIdleRunTimePercentImpl           \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv            \n"
-        " MPU_ulTaskGetIdleRunTimePercent_Priv:                 \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGetIdleRunTimePercentImpl             \n"
-        " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetIdleRunTimePercentImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetIdleRunTimePercentImpl           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv            \n"
+                " MPU_ulTaskGetIdleRunTimePercent_Priv:                 \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGetIdleRunTimePercentImpl             \n"
+                " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetIdleRunTimePercentImpl            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+    #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetIdleRunTimeCounterImpl           \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv            \n"
-        " MPU_ulTaskGetIdleRunTimeCounter_Priv:                 \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGetIdleRunTimeCounterImpl             \n"
-        " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetIdleRunTimeCounterImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetIdleRunTimeCounterImpl           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv            \n"
+                " MPU_ulTaskGetIdleRunTimeCounter_Priv:                 \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGetIdleRunTimeCounterImpl             \n"
+                " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetIdleRunTimeCounterImpl            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+    #if ( configUSE_APPLICATION_TASK_TAG == 1 )
 
-void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
-                                     TaskHookFunction_t pxHookFunction ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
+                                             TaskHookFunction_t pxHookFunction ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
-                                     TaskHookFunction_t pxHookFunction ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSetApplicationTaskTagImpl            \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskSetApplicationTaskTag_Unpriv             \n"
-        " MPU_vTaskSetApplicationTaskTag_Priv:                  \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskSetApplicationTaskTagImpl              \n"
-        " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSetApplicationTaskTagImpl             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
+                                             TaskHookFunction_t pxHookFunction ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskSetApplicationTaskTagImpl            \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskSetApplicationTaskTag_Unpriv             \n"
+                " MPU_vTaskSetApplicationTaskTag_Priv:                  \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskSetApplicationTaskTagImpl              \n"
+                " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskSetApplicationTaskTagImpl             \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
+    #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+    #if ( configUSE_APPLICATION_TASK_TAG == 1 )
 
-TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetApplicationTaskTagImpl            \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGetApplicationTaskTag_Unpriv             \n"
-        " MPU_xTaskGetApplicationTaskTag_Priv:                  \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGetApplicationTaskTagImpl              \n"
-        " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetApplicationTaskTagImpl             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetApplicationTaskTagImpl            \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGetApplicationTaskTag_Unpriv             \n"
+                " MPU_xTaskGetApplicationTaskTag_Priv:                  \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGetApplicationTaskTagImpl              \n"
+                " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetApplicationTaskTagImpl             \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
+    #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+    #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
 
-void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
-                                            BaseType_t xIndex,
-                                            void * pvValue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
+                                                    BaseType_t xIndex,
+                                                    void * pvValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
-                                            BaseType_t xIndex,
-                                            void * pvValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSetThreadLocalStoragePointerImpl     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv      \n"
-        " MPU_vTaskSetThreadLocalStoragePointer_Priv:           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskSetThreadLocalStoragePointerImpl       \n"
-        " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSetThreadLocalStoragePointerImpl      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
+                                                    BaseType_t xIndex,
+                                                    void * pvValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskSetThreadLocalStoragePointerImpl     \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv      \n"
+                " MPU_vTaskSetThreadLocalStoragePointer_Priv:           \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskSetThreadLocalStoragePointerImpl       \n"
+                " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskSetThreadLocalStoragePointerImpl      \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
+    #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+    #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
 
-void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
-                                               BaseType_t xIndex ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
+                                                       BaseType_t xIndex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
-                                               BaseType_t xIndex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pvTaskGetThreadLocalStoragePointerImpl    \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv     \n"
-        " MPU_pvTaskGetThreadLocalStoragePointer_Priv:          \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_pvTaskGetThreadLocalStoragePointerImpl      \n"
-        " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pvTaskGetThreadLocalStoragePointerImpl     \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
+                                                       BaseType_t xIndex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pvTaskGetThreadLocalStoragePointerImpl    \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv     \n"
+                " MPU_pvTaskGetThreadLocalStoragePointer_Priv:          \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_pvTaskGetThreadLocalStoragePointerImpl      \n"
+                " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pvTaskGetThreadLocalStoragePointerImpl     \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
+    #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
-                                      const UBaseType_t uxArraySize,
-                                      configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
+                                              const UBaseType_t uxArraySize,
+                                              configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
-                                      const UBaseType_t uxArraySize,
-                                      configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetSystemStateImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTaskGetSystemState_Unpriv                   \n"
-        " MPU_uxTaskGetSystemState_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTaskGetSystemStateImpl                    \n"
-        " MPU_uxTaskGetSystemState_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetSystemStateImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
+                                              const UBaseType_t uxArraySize,
+                                              configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskGetSystemStateImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTaskGetSystemState_Unpriv                   \n"
+                " MPU_uxTaskGetSystemState_Priv:                        \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTaskGetSystemStateImpl                    \n"
+                " MPU_uxTaskGetSystemState_Unpriv:                      \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskGetSystemStateImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
+    #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
+    #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
 
-UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetStackHighWaterMarkImpl           \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTaskGetStackHighWaterMark_Unpriv            \n"
-        " MPU_uxTaskGetStackHighWaterMark_Priv:                 \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTaskGetStackHighWaterMarkImpl             \n"
-        " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetStackHighWaterMarkImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskGetStackHighWaterMarkImpl           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTaskGetStackHighWaterMark_Unpriv            \n"
+                " MPU_uxTaskGetStackHighWaterMark_Priv:                 \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTaskGetStackHighWaterMarkImpl             \n"
+                " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskGetStackHighWaterMarkImpl            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */
+    #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
+    #if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
 
-configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetStackHighWaterMark2Impl          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv           \n"
-        " MPU_uxTaskGetStackHighWaterMark2_Priv:                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTaskGetStackHighWaterMark2Impl            \n"
-        " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetStackHighWaterMark2Impl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskGetStackHighWaterMark2Impl          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv           \n"
+                " MPU_uxTaskGetStackHighWaterMark2_Priv:                \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTaskGetStackHighWaterMark2Impl            \n"
+                " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskGetStackHighWaterMark2Impl           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */
+    #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
+    #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
 
-TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetCurrentTaskHandleImpl             \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGetCurrentTaskHandle_Unpriv              \n"
-        " MPU_xTaskGetCurrentTaskHandle_Priv:                   \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGetCurrentTaskHandleImpl               \n"
-        " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetCurrentTaskHandleImpl              \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetCurrentTaskHandleImpl             \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGetCurrentTaskHandle_Unpriv              \n"
+                " MPU_xTaskGetCurrentTaskHandle_Priv:                   \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGetCurrentTaskHandleImpl               \n"
+                " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetCurrentTaskHandleImpl              \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
+    #endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_xTaskGetSchedulerState == 1 )
+    #if ( INCLUDE_xTaskGetSchedulerState == 1 )
 
-BaseType_t MPU_xTaskGetSchedulerState( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGetSchedulerState( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGetSchedulerState( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetSchedulerStateImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGetSchedulerState_Unpriv                 \n"
-        " MPU_xTaskGetSchedulerState_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGetSchedulerStateImpl                  \n"
-        " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetSchedulerStateImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGetSchedulerState( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetSchedulerStateImpl                \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGetSchedulerState_Unpriv                 \n"
+                " MPU_xTaskGetSchedulerState_Priv:                      \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGetSchedulerStateImpl                  \n"
+                " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetSchedulerStateImpl                 \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */
+    #endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */
 /*-----------------------------------------------------------*/
 
-void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSetTimeOutStateImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskSetTimeOutState_Unpriv                   \n"
-        " MPU_vTaskSetTimeOutState_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskSetTimeOutStateImpl                    \n"
-        " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSetTimeOutStateImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_vTaskSetTimeOutStateImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_vTaskSetTimeOutState_Unpriv                   \n"
+            " MPU_vTaskSetTimeOutState_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_vTaskSetTimeOutStateImpl                    \n"
+            " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_vTaskSetTimeOutStateImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
-                                     TickType_t * const pxTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
+                                         TickType_t * const pxTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
-                                     TickType_t * const pxTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskCheckForTimeOutImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskCheckForTimeOut_Unpriv                   \n"
-        " MPU_xTaskCheckForTimeOut_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskCheckForTimeOutImpl                    \n"
-        " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskCheckForTimeOutImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
+                                         TickType_t * const pxTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xTaskCheckForTimeOutImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xTaskCheckForTimeOut_Unpriv                   \n"
+            " MPU_xTaskCheckForTimeOut_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xTaskCheckForTimeOutImpl                    \n"
+            " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xTaskCheckForTimeOutImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                   UBaseType_t uxIndexToNotify,
-                                   uint32_t ulValue,
-                                   eNotifyAction eAction,
-                                   uint32_t * pulPreviousNotificationValue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
+                                           UBaseType_t uxIndexToNotify,
+                                           uint32_t ulValue,
+                                           eNotifyAction eAction,
+                                           uint32_t * pulPreviousNotificationValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                   UBaseType_t uxIndexToNotify,
-                                   uint32_t ulValue,
-                                   eNotifyAction eAction,
-                                   uint32_t * pulPreviousNotificationValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGenericNotifyImpl                    \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGenericNotify_Unpriv                     \n"
-        " MPU_xTaskGenericNotify_Priv:                          \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGenericNotifyImpl                      \n"
-        " MPU_xTaskGenericNotify_Unpriv:                        \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGenericNotifyImpl                     \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
+                                           UBaseType_t uxIndexToNotify,
+                                           uint32_t ulValue,
+                                           eNotifyAction eAction,
+                                           uint32_t * pulPreviousNotificationValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGenericNotifyImpl                    \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGenericNotify_Unpriv                     \n"
+                " MPU_xTaskGenericNotify_Priv:                          \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGenericNotifyImpl                      \n"
+                " MPU_xTaskGenericNotify_Unpriv:                        \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGenericNotifyImpl                     \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                       uint32_t ulBitsToClearOnEntry,
-                                       uint32_t ulBitsToClearOnExit,
-                                       uint32_t * pulNotificationValue,
-                                       TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
+                                               uint32_t ulBitsToClearOnEntry,
+                                               uint32_t ulBitsToClearOnExit,
+                                               uint32_t * pulNotificationValue,
+                                               TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                       uint32_t ulBitsToClearOnEntry,
-                                       uint32_t ulBitsToClearOnExit,
-                                       uint32_t * pulNotificationValue,
-                                       TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGenericNotifyWaitImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGenericNotifyWait_Unpriv                 \n"
-        " MPU_xTaskGenericNotifyWait_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGenericNotifyWaitImpl                  \n"
-        " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGenericNotifyWaitImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
+                                               uint32_t ulBitsToClearOnEntry,
+                                               uint32_t ulBitsToClearOnExit,
+                                               uint32_t * pulNotificationValue,
+                                               TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGenericNotifyWaitImpl                \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGenericNotifyWait_Unpriv                 \n"
+                " MPU_xTaskGenericNotifyWait_Priv:                      \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGenericNotifyWaitImpl                  \n"
+                " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGenericNotifyWaitImpl                 \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
-                                      BaseType_t xClearCountOnExit,
-                                      TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
+                                              BaseType_t xClearCountOnExit,
+                                              TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
-                                      BaseType_t xClearCountOnExit,
-                                      TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGenericNotifyTakeImpl               \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGenericNotifyTake_Unpriv                \n"
-        " MPU_ulTaskGenericNotifyTake_Priv:                     \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGenericNotifyTakeImpl                 \n"
-        " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGenericNotifyTakeImpl                \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
+                                              BaseType_t xClearCountOnExit,
+                                              TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGenericNotifyTakeImpl               \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGenericNotifyTake_Unpriv                \n"
+                " MPU_ulTaskGenericNotifyTake_Priv:                     \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGenericNotifyTakeImpl                 \n"
+                " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGenericNotifyTakeImpl                \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
-                                             UBaseType_t uxIndexToClear ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
+                                                     UBaseType_t uxIndexToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
-                                             UBaseType_t uxIndexToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGenericNotifyStateClearImpl          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGenericNotifyStateClear_Unpriv           \n"
-        " MPU_xTaskGenericNotifyStateClear_Priv:                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGenericNotifyStateClearImpl            \n"
-        " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGenericNotifyStateClearImpl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
+                                                     UBaseType_t uxIndexToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGenericNotifyStateClearImpl          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGenericNotifyStateClear_Unpriv           \n"
+                " MPU_xTaskGenericNotifyStateClear_Priv:                \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGenericNotifyStateClearImpl            \n"
+                " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGenericNotifyStateClearImpl           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
-                                            UBaseType_t uxIndexToClear,
-                                            uint32_t ulBitsToClear ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
+                                                    UBaseType_t uxIndexToClear,
+                                                    uint32_t ulBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
-                                            UBaseType_t uxIndexToClear,
-                                            uint32_t ulBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGenericNotifyValueClearImpl         \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGenericNotifyValueClear_Unpriv          \n"
-        " MPU_ulTaskGenericNotifyValueClear_Priv:               \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGenericNotifyValueClearImpl           \n"
-        " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGenericNotifyValueClearImpl          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
+                                                    UBaseType_t uxIndexToClear,
+                                                    uint32_t ulBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGenericNotifyValueClearImpl         \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGenericNotifyValueClear_Unpriv          \n"
+                " MPU_ulTaskGenericNotifyValueClear_Priv:               \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGenericNotifyValueClearImpl           \n"
+                " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGenericNotifyValueClearImpl          \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
-                                  const void * const pvItemToQueue,
-                                  TickType_t xTicksToWait,
-                                  const BaseType_t xCopyPosition ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
+                                      const void * const pvItemToQueue,
+                                      TickType_t xTicksToWait,
+                                      const BaseType_t xCopyPosition ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
-                                  const void * const pvItemToQueue,
-                                  TickType_t xTicksToWait,
-                                  const BaseType_t xCopyPosition ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueGenericSendImpl                     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueGenericSend_Unpriv                      \n"
-        " MPU_xQueueGenericSend_Priv:                           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueGenericSendImpl                       \n"
-        " MPU_xQueueGenericSend_Unpriv:                         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueGenericSendImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
+                                      const void * const pvItemToQueue,
+                                      TickType_t xTicksToWait,
+                                      const BaseType_t xCopyPosition ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueueGenericSendImpl                     \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xQueueGenericSend_Unpriv                      \n"
+            " MPU_xQueueGenericSend_Priv:                           \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xQueueGenericSendImpl                       \n"
+            " MPU_xQueueGenericSend_Unpriv:                         \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueueGenericSendImpl                      \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxQueueMessagesWaitingImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxQueueMessagesWaiting_Unpriv                 \n"
-        " MPU_uxQueueMessagesWaiting_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxQueueMessagesWaitingImpl                  \n"
-        " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxQueueMessagesWaitingImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_uxQueueMessagesWaitingImpl                \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_uxQueueMessagesWaiting_Unpriv                 \n"
+            " MPU_uxQueueMessagesWaiting_Priv:                      \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_uxQueueMessagesWaitingImpl                  \n"
+            " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_uxQueueMessagesWaitingImpl                 \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxQueueSpacesAvailableImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxQueueSpacesAvailable_Unpriv                 \n"
-        " MPU_uxQueueSpacesAvailable_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxQueueSpacesAvailableImpl                  \n"
-        " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxQueueSpacesAvailableImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_uxQueueSpacesAvailableImpl                \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_uxQueueSpacesAvailable_Unpriv                 \n"
+            " MPU_uxQueueSpacesAvailable_Priv:                      \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_uxQueueSpacesAvailableImpl                  \n"
+            " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_uxQueueSpacesAvailableImpl                 \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
-                              void * const pvBuffer,
-                              TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
+                                  void * const pvBuffer,
+                                  TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
-                              void * const pvBuffer,
-                              TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueReceiveImpl                         \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueReceive_Unpriv                          \n"
-        " MPU_xQueueReceive_Priv:                               \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueReceiveImpl                           \n"
-        " MPU_xQueueReceive_Unpriv:                             \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueReceiveImpl                          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
+                                  void * const pvBuffer,
+                                  TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueueReceiveImpl                         \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xQueueReceive_Unpriv                          \n"
+            " MPU_xQueueReceive_Priv:                               \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xQueueReceiveImpl                           \n"
+            " MPU_xQueueReceive_Unpriv:                             \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueueReceiveImpl                          \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
-                           void * const pvBuffer,
-                           TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
+                               void * const pvBuffer,
+                               TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
-                           void * const pvBuffer,
-                           TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueuePeekImpl                            \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueuePeek_Unpriv                             \n"
-        " MPU_xQueuePeek_Priv:                                  \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueuePeekImpl                              \n"
-        " MPU_xQueuePeek_Unpriv:                                \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueuePeekImpl                             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
+                               void * const pvBuffer,
+                               TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueuePeekImpl                            \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xQueuePeek_Unpriv                             \n"
+            " MPU_xQueuePeek_Priv:                                  \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xQueuePeekImpl                              \n"
+            " MPU_xQueuePeek_Unpriv:                                \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueuePeekImpl                             \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
-                                    TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
+                                        TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
-                                    TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueSemaphoreTakeImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueSemaphoreTake_Unpriv                    \n"
-        " MPU_xQueueSemaphoreTake_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueSemaphoreTakeImpl                     \n"
-        " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueSemaphoreTakeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
+                                        TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueueSemaphoreTakeImpl                   \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xQueueSemaphoreTake_Unpriv                    \n"
+            " MPU_xQueueSemaphoreTake_Priv:                         \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xQueueSemaphoreTakeImpl                     \n"
+            " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueueSemaphoreTakeImpl                    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+    #if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
 
-TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueGetMutexHolderImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueGetMutexHolder_Unpriv                   \n"
-        " MPU_xQueueGetMutexHolder_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueGetMutexHolderImpl                    \n"
-        " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueGetMutexHolderImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueGetMutexHolderImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueGetMutexHolder_Unpriv                   \n"
+                " MPU_xQueueGetMutexHolder_Priv:                        \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueGetMutexHolderImpl                    \n"
+                " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueGetMutexHolderImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */
+    #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+    #if ( configUSE_RECURSIVE_MUTEXES == 1 )
 
-BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
-                                         TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+                                                 TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+        BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+                                                 TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueTakeMutexRecursiveImpl              \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueTakeMutexRecursive_Unpriv               \n"
+                " MPU_xQueueTakeMutexRecursive_Priv:                    \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueTakeMutexRecursiveImpl                \n"
+                " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueTakeMutexRecursiveImpl               \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_RECURSIVE_MUTEXES == 1 )
+
+        BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueGiveMutexRecursiveImpl              \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueGiveMutexRecursive_Unpriv               \n"
+                " MPU_xQueueGiveMutexRecursive_Priv:                    \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueGiveMutexRecursiveImpl                \n"
+                " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueGiveMutexRecursiveImpl               \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_QUEUE_SETS == 1 )
+
+        QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
+                                                        const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
+                                                        const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueSelectFromSetImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueSelectFromSet_Unpriv                    \n"
+                " MPU_xQueueSelectFromSet_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueSelectFromSetImpl                     \n"
+                " MPU_xQueueSelectFromSet_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueSelectFromSetImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_QUEUE_SETS == 1 )
+
+        BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                                       QueueSetHandle_t xQueueSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                                       QueueSetHandle_t xQueueSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueAddToSetImpl                        \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueAddToSet_Unpriv                         \n"
+                " MPU_xQueueAddToSet_Priv:                              \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueAddToSetImpl                          \n"
+                " MPU_xQueueAddToSet_Unpriv:                            \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueAddToSetImpl                         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+        void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
+                                      const char * pcName ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
+                                      const char * pcName ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vQueueAddToRegistryImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vQueueAddToRegistry_Unpriv                    \n"
+                " MPU_vQueueAddToRegistry_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vQueueAddToRegistryImpl                     \n"
+                " MPU_vQueueAddToRegistry_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vQueueAddToRegistryImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+        void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vQueueUnregisterQueueImpl                 \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vQueueUnregisterQueue_Unpriv                  \n"
+                " MPU_vQueueUnregisterQueue_Priv:                       \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vQueueUnregisterQueueImpl                   \n"
+                " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vQueueUnregisterQueueImpl                  \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+        const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pcQueueGetNameImpl                        \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_pcQueueGetName_Unpriv                         \n"
+                " MPU_pcQueueGetName_Priv:                              \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_pcQueueGetNameImpl                          \n"
+                " MPU_pcQueueGetName_Unpriv:                            \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pcQueueGetNameImpl                         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pvTimerGetTimerIDImpl                     \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_pvTimerGetTimerID_Unpriv                      \n"
+                " MPU_pvTimerGetTimerID_Priv:                           \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_pvTimerGetTimerIDImpl                       \n"
+                " MPU_pvTimerGetTimerID_Unpriv:                         \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pvTimerGetTimerIDImpl                      \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
+                                   void * pvNewID ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
+                                   void * pvNewID ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTimerSetTimerIDImpl                      \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTimerSetTimerID_Unpriv                       \n"
+                " MPU_vTimerSetTimerID_Priv:                            \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTimerSetTimerIDImpl                        \n"
+                " MPU_vTimerSetTimerID_Unpriv:                          \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTimerSetTimerIDImpl                       \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerIsTimerActiveImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerIsTimerActive_Unpriv                    \n"
+                " MPU_xTimerIsTimerActive_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerIsTimerActiveImpl                     \n"
+                " MPU_xTimerIsTimerActive_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerIsTimerActiveImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetTimerDaemonTaskHandleImpl        \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv         \n"
+                " MPU_xTimerGetTimerDaemonTaskHandle_Priv:              \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerGetTimerDaemonTaskHandleImpl          \n"
+                " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetTimerDaemonTaskHandleImpl         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                                     const BaseType_t xCommandID,
+                                                     const TickType_t xOptionalValue,
+                                                     BaseType_t * const pxHigherPriorityTaskWoken,
+                                                     const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                                     const BaseType_t xCommandID,
+                                                     const TickType_t xOptionalValue,
+                                                     BaseType_t * const pxHigherPriorityTaskWoken,
+                                                     const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                               \n"
+                " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
+                "                                                               \n"
+                " push {r0}                                                     \n"
+                " mrs r0, control                                               \n"
+                " tst r0, #1                                                    \n"
+                " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
+                " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
+                "     pop {r0}                                                  \n"
+                "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
+                " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
+                "     pop {r0}                                                  \n"
+                "     svc %0                                                    \n"
+                "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
+                "     svc %1                                                    \n"
+                "     bx lr                                                     \n"
+                "                                                               \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pcTimerGetNameImpl                        \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_pcTimerGetName_Unpriv                         \n"
+                " MPU_pcTimerGetName_Priv:                              \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_pcTimerGetNameImpl                          \n"
+                " MPU_pcTimerGetName_Unpriv:                            \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pcTimerGetNameImpl                         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
+                                      const BaseType_t uxAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
+                                      const BaseType_t uxAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTimerSetReloadModeImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTimerSetReloadMode_Unpriv                    \n"
+                " MPU_vTimerSetReloadMode_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTimerSetReloadModeImpl                     \n"
+                " MPU_vTimerSetReloadMode_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTimerSetReloadModeImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetReloadModeImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerGetReloadMode_Unpriv                    \n"
+                " MPU_xTimerGetReloadMode_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerGetReloadModeImpl                     \n"
+                " MPU_xTimerGetReloadMode_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetReloadModeImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTimerGetReloadModeImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTimerGetReloadMode_Unpriv                   \n"
+                " MPU_uxTimerGetReloadMode_Priv:                        \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTimerGetReloadModeImpl                    \n"
+                " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTimerGetReloadModeImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetPeriodImpl                       \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerGetPeriod_Unpriv                        \n"
+                " MPU_xTimerGetPeriod_Priv:                             \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerGetPeriodImpl                         \n"
+                " MPU_xTimerGetPeriod_Unpriv:                           \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetPeriodImpl                        \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetExpiryTimeImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerGetExpiryTime_Unpriv                    \n"
+                " MPU_xTimerGetExpiryTime_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerGetExpiryTimeImpl                     \n"
+                " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetExpiryTimeImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         const BaseType_t xClearOnExit,
+                                         const BaseType_t xWaitForAllBits,
+                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         const BaseType_t xClearOnExit,
+                                         const BaseType_t xWaitForAllBits,
                                          TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueTakeMutexRecursiveImpl              \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueTakeMutexRecursive_Unpriv               \n"
-        " MPU_xQueueTakeMutexRecursive_Priv:                    \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueTakeMutexRecursiveImpl                \n"
-        " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueTakeMutexRecursiveImpl               \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupWaitBitsImpl                   \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
+            " MPU_xEventGroupWaitBits_Priv:                         \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xEventGroupWaitBitsImpl                     \n"
+            " MPU_xEventGroupWaitBits_Unpriv:                       \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupWaitBitsImpl                    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                          const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueGiveMutexRecursiveImpl              \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueGiveMutexRecursive_Unpriv               \n"
-        " MPU_xQueueGiveMutexRecursive_Priv:                    \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueGiveMutexRecursiveImpl                \n"
-        " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueGiveMutexRecursiveImpl               \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                          const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupClearBitsImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xEventGroupClearBits_Unpriv                   \n"
+            " MPU_xEventGroupClearBits_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xEventGroupClearBitsImpl                    \n"
+            " MPU_xEventGroupClearBits_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupClearBitsImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_QUEUE_SETS == 1 )
+    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                        const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
-                                                const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
-                                                const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueSelectFromSetImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueSelectFromSet_Unpriv                    \n"
-        " MPU_xQueueSelectFromSet_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueSelectFromSetImpl                     \n"
-        " MPU_xQueueSelectFromSet_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueSelectFromSetImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                        const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupSetBitsImpl                    \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xEventGroupSetBits_Unpriv                     \n"
+            " MPU_xEventGroupSetBits_Priv:                          \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xEventGroupSetBitsImpl                      \n"
+            " MPU_xEventGroupSetBits_Unpriv:                        \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupSetBitsImpl                     \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_QUEUE_SETS == 1 )
-
-BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
-                               QueueSetHandle_t xQueueSet ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
-                               QueueSetHandle_t xQueueSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueAddToSetImpl                        \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueAddToSet_Unpriv                         \n"
-        " MPU_xQueueAddToSet_Priv:                              \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueAddToSetImpl                          \n"
-        " MPU_xQueueAddToSet_Unpriv:                            \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueAddToSetImpl                         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_QUEUE_SETS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
-                              const char * pcName ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
-                              const char * pcName ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vQueueAddToRegistryImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vQueueAddToRegistry_Unpriv                    \n"
-        " MPU_vQueueAddToRegistry_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vQueueAddToRegistryImpl                     \n"
-        " MPU_vQueueAddToRegistry_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vQueueAddToRegistryImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vQueueUnregisterQueueImpl                 \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vQueueUnregisterQueue_Unpriv                  \n"
-        " MPU_vQueueUnregisterQueue_Priv:                       \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vQueueUnregisterQueueImpl                   \n"
-        " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vQueueUnregisterQueueImpl                  \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pcQueueGetNameImpl                        \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_pcQueueGetName_Unpriv                         \n"
-        " MPU_pcQueueGetName_Priv:                              \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_pcQueueGetNameImpl                          \n"
-        " MPU_pcQueueGetName_Unpriv:                            \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pcQueueGetNameImpl                         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pvTimerGetTimerIDImpl                     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_pvTimerGetTimerID_Unpriv                      \n"
-        " MPU_pvTimerGetTimerID_Priv:                           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_pvTimerGetTimerIDImpl                       \n"
-        " MPU_pvTimerGetTimerID_Unpriv:                         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pvTimerGetTimerIDImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
-                           void * pvNewID ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
-                           void * pvNewID ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTimerSetTimerIDImpl                      \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTimerSetTimerID_Unpriv                       \n"
-        " MPU_vTimerSetTimerID_Priv:                            \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTimerSetTimerIDImpl                        \n"
-        " MPU_vTimerSetTimerID_Unpriv:                          \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTimerSetTimerIDImpl                       \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerIsTimerActiveImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTimerIsTimerActive_Unpriv                    \n"
-        " MPU_xTimerIsTimerActive_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerIsTimerActiveImpl                     \n"
-        " MPU_xTimerIsTimerActive_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerIsTimerActiveImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetTimerDaemonTaskHandleImpl        \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv         \n"
-        " MPU_xTimerGetTimerDaemonTaskHandle_Priv:              \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerGetTimerDaemonTaskHandleImpl          \n"
-        " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetTimerDaemonTaskHandleImpl         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                             const BaseType_t xCommandID,
-                                             const TickType_t xOptionalValue,
-                                             BaseType_t * const pxHigherPriorityTaskWoken,
-                                             const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                             const BaseType_t xCommandID,
-                                             const TickType_t xOptionalValue,
-                                             BaseType_t * const pxHigherPriorityTaskWoken,
-                                             const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                               \n"
-        " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
-        "                                                               \n"
-        " push {r0}                                                     \n"
-        " mrs r0, control                                               \n"
-        " tst r0, #1                                                    \n"
-        " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
-        " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
-        "     pop {r0}                                                  \n"
-        "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
-        " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
-        "     pop {r0}                                                  \n"
-        "     svc %0                                                    \n"
-        "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
-        "     svc %1                                                    \n"
-        "     bx lr                                                     \n"
-        "                                                               \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pcTimerGetNameImpl                        \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_pcTimerGetName_Unpriv                         \n"
-        " MPU_pcTimerGetName_Priv:                              \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_pcTimerGetNameImpl                          \n"
-        " MPU_pcTimerGetName_Unpriv:                            \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pcTimerGetNameImpl                         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                              const BaseType_t uxAutoReload ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                              const BaseType_t uxAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTimerSetReloadModeImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTimerSetReloadMode_Unpriv                    \n"
-        " MPU_vTimerSetReloadMode_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTimerSetReloadModeImpl                     \n"
-        " MPU_vTimerSetReloadMode_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTimerSetReloadModeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetReloadModeImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTimerGetReloadMode_Unpriv                    \n"
-        " MPU_xTimerGetReloadMode_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerGetReloadModeImpl                     \n"
-        " MPU_xTimerGetReloadMode_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetReloadModeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTimerGetReloadModeImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTimerGetReloadMode_Unpriv                   \n"
-        " MPU_uxTimerGetReloadMode_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTimerGetReloadModeImpl                    \n"
-        " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTimerGetReloadModeImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetPeriodImpl                       \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTimerGetPeriod_Unpriv                        \n"
-        " MPU_xTimerGetPeriod_Priv:                             \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerGetPeriodImpl                         \n"
-        " MPU_xTimerGetPeriod_Unpriv:                           \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetPeriodImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetExpiryTimeImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTimerGetExpiryTime_Unpriv                    \n"
-        " MPU_xTimerGetExpiryTime_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerGetExpiryTimeImpl                     \n"
-        " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetExpiryTimeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                     const EventBits_t uxBitsToSet,
                                      const EventBits_t uxBitsToWaitFor,
-                                     const BaseType_t xClearOnExit,
-                                     const BaseType_t xWaitForAllBits,
-                                     TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                     const EventBits_t uxBitsToSet,
                                      const EventBits_t uxBitsToWaitFor,
-                                     const BaseType_t xClearOnExit,
-                                     const BaseType_t xWaitForAllBits,
                                      TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupWaitBitsImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
-        " MPU_xEventGroupWaitBits_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xEventGroupWaitBitsImpl                     \n"
-        " MPU_xEventGroupWaitBits_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupWaitBitsImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupSyncImpl                       \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xEventGroupSync_Unpriv                        \n"
+            " MPU_xEventGroupSync_Priv:                             \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xEventGroupSyncImpl                         \n"
+            " MPU_xEventGroupSync_Unpriv:                           \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupSyncImpl                        \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                      const EventBits_t uxBitsToClear ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                      const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupClearBitsImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xEventGroupClearBits_Unpriv                   \n"
-        " MPU_xEventGroupClearBits_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xEventGroupClearBitsImpl                    \n"
-        " MPU_xEventGroupClearBits_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupClearBitsImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxEventGroupGetNumberImpl                 \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxEventGroupGetNumber_Unpriv                  \n"
+                " MPU_uxEventGroupGetNumber_Priv:                       \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxEventGroupGetNumberImpl                   \n"
+                " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxEventGroupGetNumberImpl                  \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
 /*-----------------------------------------------------------*/
 
-EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                    const EventBits_t uxBitsToSet ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                    const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupSetBitsImpl                    \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xEventGroupSetBits_Unpriv                     \n"
-        " MPU_xEventGroupSetBits_Priv:                          \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xEventGroupSetBitsImpl                      \n"
-        " MPU_xEventGroupSetBits_Unpriv:                        \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupSetBitsImpl                     \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vEventGroupSetNumber( void * xEventGroup,
+                                       UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vEventGroupSetNumber( void * xEventGroup,
+                                       UBaseType_t uxEventGroupNumber ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vEventGroupSetNumberImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vEventGroupSetNumber_Unpriv                   \n"
+                " MPU_vEventGroupSetNumber_Priv:                        \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vEventGroupSetNumberImpl                    \n"
+                " MPU_vEventGroupSetNumber_Unpriv:                      \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vEventGroupSetNumberImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
 /*-----------------------------------------------------------*/
 
-EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                 const EventBits_t uxBitsToSet,
-                                 const EventBits_t uxBitsToWaitFor,
-                                 TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                  const void * pvTxData,
+                                  size_t xDataLengthBytes,
+                                  TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                 const EventBits_t uxBitsToSet,
-                                 const EventBits_t uxBitsToWaitFor,
-                                 TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupSyncImpl                       \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xEventGroupSync_Unpriv                        \n"
-        " MPU_xEventGroupSync_Priv:                             \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xEventGroupSyncImpl                         \n"
-        " MPU_xEventGroupSync_Unpriv:                           \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupSyncImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                  const void * pvTxData,
+                                  size_t xDataLengthBytes,
+                                  TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferSendImpl                     \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferSend_Unpriv                      \n"
+            " MPU_xStreamBufferSend_Priv:                           \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferSendImpl                       \n"
+            " MPU_xStreamBufferSend_Unpriv:                         \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferSendImpl                      \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                     void * pvRxData,
+                                     size_t xBufferLengthBytes,
+                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxEventGroupGetNumberImpl                 \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxEventGroupGetNumber_Unpriv                  \n"
-        " MPU_uxEventGroupGetNumber_Priv:                       \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxEventGroupGetNumberImpl                   \n"
-        " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxEventGroupGetNumberImpl                  \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                     void * pvRxData,
+                                     size_t xBufferLengthBytes,
+                                     TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferReceiveImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferReceive_Unpriv                   \n"
+            " MPU_xStreamBufferReceive_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferReceiveImpl                    \n"
+            " MPU_xStreamBufferReceive_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferReceiveImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vEventGroupSetNumber( void * xEventGroup,
-                               UBaseType_t uxEventGroupNumber ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vEventGroupSetNumber( void * xEventGroup,
-                               UBaseType_t uxEventGroupNumber ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vEventGroupSetNumberImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vEventGroupSetNumber_Unpriv                   \n"
-        " MPU_vEventGroupSetNumber_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vEventGroupSetNumberImpl                    \n"
-        " MPU_vEventGroupSetNumber_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vEventGroupSetNumberImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferIsFullImpl                   \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
+            " MPU_xStreamBufferIsFull_Priv:                         \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferIsFullImpl                     \n"
+            " MPU_xStreamBufferIsFull_Unpriv:                       \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferIsFullImpl                    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                              const void * pvTxData,
-                              size_t xDataLengthBytes,
-                              TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                              const void * pvTxData,
-                              size_t xDataLengthBytes,
-                              TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferSendImpl                     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferSend_Unpriv                      \n"
-        " MPU_xStreamBufferSend_Priv:                           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferSendImpl                       \n"
-        " MPU_xStreamBufferSend_Unpriv:                         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferSendImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
+            " MPU_xStreamBufferIsEmpty_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferIsEmptyImpl                    \n"
+            " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferIsEmptyImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                 void * pvRxData,
-                                 size_t xBufferLengthBytes,
-                                 TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                 void * pvRxData,
-                                 size_t xBufferLengthBytes,
-                                 TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferReceiveImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferReceive_Unpriv                   \n"
-        " MPU_xStreamBufferReceive_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferReceiveImpl                    \n"
-        " MPU_xStreamBufferReceive_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferReceiveImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
+            " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
+            " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferSpacesAvailableImpl           \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferIsFullImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
-        " MPU_xStreamBufferIsFull_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferIsFullImpl                     \n"
-        " MPU_xStreamBufferIsFull_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferIsFullImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
+            " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferBytesAvailableImpl             \n"
+            " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferBytesAvailableImpl            \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                 size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
-        " MPU_xStreamBufferIsEmpty_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferIsEmptyImpl                    \n"
-        " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferIsEmptyImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                 size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
+            " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
+            " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferSetTriggerLevelImpl           \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
-        " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
-        " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferSpacesAvailableImpl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
-size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
-        " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferBytesAvailableImpl             \n"
-        " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferBytesAvailableImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                             size_t xTriggerLevel ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                             size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
-        " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
-        " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferSetTriggerLevelImpl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
-size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
-        " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
-        " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferNextMessageLengthBytesImpl    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
+            " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
+            " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferNextMessageLengthBytesImpl    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
diff --git a/portable/GCC/ARM_CM35P/non_secure/port.c b/portable/GCC/ARM_CM35P/non_secure/port.c
index 80410e82e..c940c304b 100644
--- a/portable/GCC/ARM_CM35P/non_secure/port.c
+++ b/portable/GCC/ARM_CM35P/non_secure/port.c
@@ -110,8 +110,8 @@
 /**
  * @brief Constants used during system call enter and exit.
  */
-#define portPSR_STACK_PADDING_MASK                ( 1UL << 9UL )
-#define portEXC_RETURN_STACK_FRAME_TYPE_MASK      ( 1UL << 4UL )
+#define portPSR_STACK_PADDING_MASK              ( 1UL << 9UL )
+#define portEXC_RETURN_STACK_FRAME_TYPE_MASK    ( 1UL << 4UL )
 /*-----------------------------------------------------------*/
 
 /**
@@ -133,81 +133,81 @@
 /**
  * @brief Offsets in the stack to the parameters when inside the SVC handler.
  */
-#define portOFFSET_TO_LR                    ( 5 )
-#define portOFFSET_TO_PC                    ( 6 )
-#define portOFFSET_TO_PSR                   ( 7 )
+#define portOFFSET_TO_LR     ( 5 )
+#define portOFFSET_TO_PC     ( 6 )
+#define portOFFSET_TO_PSR    ( 7 )
 /*-----------------------------------------------------------*/
 
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                      ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                      ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                       ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                      ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                      ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                     ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                     ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK  ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK               ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK               ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK               ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK               ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK               ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK               ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK               ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK               ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0              ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1              ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2              ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3              ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4              ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5              ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6              ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7              ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE            ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT      ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                      ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE             ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -216,11 +216,11 @@
 
 /* Extract last address of the MPU region as encoded in the
  * RLAR (Region Limit Address Register) value. */
-#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar )  \
+#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar ) \
     ( ( ( rlar ) & portMPU_RLAR_ADDRESS_MASK ) | ~portMPU_RLAR_ADDRESS_MASK )
 
 /* Does addr lies within [start, end] address range? */
-#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end )    \
+#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \
     ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) )
 
 /* Is the access request satisfied by the available permissions? */
@@ -422,54 +422,57 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the system call stack so that upon returning from
-     * SVC, the system call stack is used.
-     *
-     * It is used for the system calls with up to 4 parameters.
-     *
-     * @param pulTaskStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the system call stack so that upon returning from
+ * SVC, the system call stack is used.
+ *
+ * It is used for the system calls with up to 4 parameters.
+ *
+ * @param pulTaskStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallEnter( uint32_t * pulTaskStack,
+                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the system call stack so that upon returning from
-     * SVC, the system call stack is used.
-     *
-     * It is used for the system calls with 5 parameters.
-     *
-     * @param pulTaskStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the system call stack so that upon returning from
+ * SVC, the system call stack is used.
+ *
+ * It is used for the system calls with 5 parameters.
+ *
+ * @param pulTaskStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallEnter_1( uint32_t * pulTaskStack,
+                             uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the task stack so that upon returning from
-     * SVC, the task stack is used again.
-     *
-     * @param pulSystemCallStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the task stack so that upon returning from
+ * SVC, the task stack is used again.
+ *
+ * @param pulSystemCallStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallExit( uint32_t * pulSystemCallStack,
+                          uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Checks whether or not the calling task is privileged.
-     *
-     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
-     */
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
     BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
 
 #endif /* configENABLE_MPU == 1 */
@@ -1086,18 +1089,18 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             vRestoreContextOfFirstTask();
             break;
 
-        #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
-            case portSVC_RAISE_PRIVILEGE:
+            #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+                case portSVC_RAISE_PRIVILEGE:
 
-                /* Only raise the privilege, if the svc was raised from any of
-                 * the system calls. */
-                if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
-                    ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
-                {
-                    vRaisePrivilege();
-                }
-                break;
-        #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+                    /* Only raise the privilege, if the svc was raised from any of
+                     * the system calls. */
+                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+                    {
+                        vRaisePrivilege();
+                    }
+                    break;
+            #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
         default:
             /* Incorrect SVC call. */
@@ -1108,513 +1111,526 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulSystemCallStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallEnter( uint32_t * pulTaskStack,
+                           uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulSystemCallStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        /* This is not NULL only for the duration of the system call. */
-        configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+        #if defined( __ARMCC_VERSION )
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+
+            /* This is not NULL only for the duration of the system call. */
+            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the system call stack for the stack frame. */
+            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulSystemCallStack[ i ] = pulTaskStack[ i ];
+            }
+
+            /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
+             * restore it when we exit from the system call. */
+            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* Use the pulSystemCallStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+
+            /* Remember the location where we should copy the stack frame when we exit from
+             * the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+
+            /* Record if the hardware used padding to force the stack pointer
+             * to be double word aligned. */
+            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
+            {
+                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
             }
+
+            /* We ensure in pxPortInitialiseStack that the system call stack is
+             * double word aligned and therefore, there is no need of padding.
+             * Clear the bit[9] of stacked xPSR. */
+            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
+
+            /* Raise the privilege for the duration of the system call. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " bics r0, r1         \n" /* Clear nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the system call stack for the stack frame. */
-        pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulSystemCallStack[ i ] = pulTaskStack[ i ];
-        }
-
-        /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
-         * restore it when we exit from the system call. */
-        pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-        __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* Use the pulSystemCallStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-
-        /* Remember the location where we should copy the stack frame when we exit from
-         * the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-        /* Record if the hardware used padding to force the stack pointer
-         * to be double word aligned. */
-        if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-        {
-            pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-        }
-        else
-        {
-            pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-        }
-
-        /* We ensure in pxPortInitialiseStack that the system call stack is
-         * double word aligned and therefore, there is no need of padding.
-         * Clear the bit[9] of stacked xPSR. */
-        pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-        /* Raise the privilege for the duration of the system call. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " bics r0, r1         \n" /* Clear nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulSystemCallStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallEnter_1( uint32_t * pulTaskStack,
+                             uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulSystemCallStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        /* This is not NULL only for the duration of the system call. */
-        configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+        #if defined( __ARMCC_VERSION )
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+
+            /* This is not NULL only for the duration of the system call. */
+            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the system call stack for the stack frame and
+             * the parameter passed on the stack. We only need to copy one
+             * parameter but we still reserve 2 spaces to keep the stack
+             * double word aligned. */
+            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulSystemCallStack[ i ] = pulTaskStack[ i ];
+            }
+
+            /* Copy the parameter which is passed the stack. */
+            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
+            {
+                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
+
+                /* Record if the hardware used padding to force the stack pointer
+                 * to be double word aligned. */
+                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
+
+                /* Record if the hardware used padding to force the stack pointer
+                 * to be double word aligned. */
+                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
             }
+
+            /* Store the value of the LR and PSPLIM registers before the SVC was raised.
+             * We need to restore it when we exit from the system call. */
+            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* Use the pulSystemCallStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+
+            /* Remember the location where we should copy the stack frame when we exit from
+             * the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+
+            /* We ensure in pxPortInitialiseStack that the system call stack is
+             * double word aligned and therefore, there is no need of padding.
+             * Clear the bit[9] of stacked xPSR. */
+            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
+
+            /* Raise the privilege for the duration of the system call. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " bics r0, r1         \n" /* Clear nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the system call stack for the stack frame and
-         * the parameter passed on the stack. We only need to copy one
-         * parameter but we still reserve 2 spaces to keep the stack
-         * double word aligned. */
-        pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulSystemCallStack[ i ] = pulTaskStack[ i ];
-        }
-
-        /* Copy the parameter which is passed the stack. */
-        if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-        {
-            pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
-            /* Record if the hardware used padding to force the stack pointer
-             * to be double word aligned. */
-            pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-        }
-        else
-        {
-            pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
-            /* Record if the hardware used padding to force the stack pointer
-             * to be double word aligned. */
-            pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-        }
-
-        /* Store the value of the LR and PSPLIM registers before the SVC was raised.
-         * We need to restore it when we exit from the system call. */
-        pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-        __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* Use the pulSystemCallStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-
-        /* Remember the location where we should copy the stack frame when we exit from
-         * the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-        /* We ensure in pxPortInitialiseStack that the system call stack is
-         * double word aligned and therefore, there is no need of padding.
-         * Clear the bit[9] of stacked xPSR. */
-        pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-        /* Raise the privilege for the duration of the system call. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " bics r0, r1         \n" /* Clear nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulTaskStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallExit( uint32_t * pulSystemCallStack,
+                          uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulTaskStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+        #if defined( __ARMCC_VERSION )
+
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the task stack for the stack frame. */
+            pulTaskStack = pulTaskStack - ulStackFrameSize;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulTaskStack[ i ] = pulSystemCallStack[ i ];
+            }
+
+            /* Use the pulTaskStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
+
+            /* Restore the LR and PSPLIM to what they were at the time of
+             * system call entry. */
+            pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* If the hardware used padding to force the stack pointer
+             * to be double word aligned, set the stacked xPSR bit[9],
+             * otherwise clear it. */
+            if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG )
+            {
+                pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
             }
+
+            /* This is not NULL only for the duration of the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
+
+            /* Drop the privilege before returning to the thread mode. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " orrs r0, r1         \n" /* Set nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the task stack for the stack frame. */
-        pulTaskStack = pulTaskStack - ulStackFrameSize;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulTaskStack[ i ] = pulSystemCallStack[ i ];
-        }
-
-        /* Use the pulTaskStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
-
-        /* Restore the LR and PSPLIM to what they were at the time of
-         * system call entry. */
-        pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* If the hardware used padding to force the stack pointer
-         * to be double word aligned, set the stacked xPSR bit[9],
-         * otherwise clear it. */
-        if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG )
-        {
-            pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK;
-        }
-        else
-        {
-            pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-        }
-
-        /* This is not NULL only for the duration of the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
-
-        /* Drop the privilege before returning to the thread mode. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " orrs r0, r1         \n" /* Set nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */
-{
-    BaseType_t xTaskIsPrivileged = pdFALSE;
-    const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
-
-    if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+    BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */
     {
-        xTaskIsPrivileged = pdTRUE;
-    }
+        BaseType_t xTaskIsPrivileged = pdFALSE;
+        const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
 
-    return xTaskIsPrivileged;
-}
+        if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+        {
+            xTaskIsPrivileged = pdTRUE;
+        }
+
+        return xTaskIsPrivileged;
+    }
 
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
-#if( configENABLE_MPU == 1 )
+#if ( configENABLE_MPU == 1 )
 
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     StackType_t * pxEndOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters,
-                                     BaseType_t xRunPrivileged,
-                                     xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
-{
-    uint32_t ulIndex = 0;
-
-    xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
-    ulIndex++;
-
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
-    ulIndex++;
-
-    #if ( configENABLE_TRUSTZONE == 1 )
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters,
+                                         BaseType_t xRunPrivileged,
+                                         xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
     {
-        xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT;  /* xSecureContext. */
+        uint32_t ulIndex = 0;
+
+        xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
         ulIndex++;
-    }
-    #endif /* configENABLE_TRUSTZONE */
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
-    ulIndex++;
-    if( xRunPrivileged == pdTRUE )
-    {
-        xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */
         ulIndex++;
-    }
-    else
-    {
-        xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */
         ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
+        ulIndex++;
+
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters;            /* r0. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x01010101;                           /* r1. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x02020202;                           /* r2. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x03030303;                           /* r3. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x12121212;                           /* r12. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode;                  /* PC. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR;                     /* xPSR. */
+        ulIndex++;
+
+        #if ( configENABLE_TRUSTZONE == 1 )
+        {
+            xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT; /* xSecureContext. */
+            ulIndex++;
+        }
+        #endif /* configENABLE_TRUSTZONE */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
+        ulIndex++;
+
+        if( xRunPrivileged == pdTRUE )
+        {
+            xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
+            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+            ulIndex++;
+        }
+        else
+        {
+            xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
+            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+            ulIndex++;
+        }
+
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
+        ulIndex++;
+
+        #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+        {
+            /* Ensure that the system call stack is double word aligned. */
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] );
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) &
+                                                                                     ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
+
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] );
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) +
+                                                                                            ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) &
+                                                                                          ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
+
+            /* This is not NULL only for the duration of a system call. */
+            xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL;
+        }
+        #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
+
+        return &( xMPUSettings->ulContext[ ulIndex ] );
     }
-    xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
-    ulIndex++;
-
-    #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
-    {
-        /* Ensure that the system call stack is double word aligned. */
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] );
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) &
-                                                                                 ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
-
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] );
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) +
-                                                                                        ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) &
-                                                                                      ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
-
-        /* This is not NULL only for the duration of a system call. */
-        xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL;
-    }
-    #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
-
-    return &( xMPUSettings->ulContext[ ulIndex ] );
-}
 
 #else /* configENABLE_MPU */
 
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     StackType_t * pxEndOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters ) /* PRIVILEGED_FUNCTION */
-{
-    /* Simulate the stack frame as it would be created by a context switch
-     * interrupt. */
-    #if ( portPRELOAD_REGISTERS == 0 )
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters ) /* PRIVILEGED_FUNCTION */
     {
-        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-        pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
-        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-        pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
-        *pxTopOfStack = portINITIAL_EXC_RETURN;
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
-
-        #if ( configENABLE_TRUSTZONE == 1 )
+        /* Simulate the stack frame as it would be created by a context switch
+         * interrupt. */
+        #if ( portPRELOAD_REGISTERS == 0 )
         {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
-        }
-        #endif /* configENABLE_TRUSTZONE */
-    }
-    #else /* portPRELOAD_REGISTERS */
-    {
-        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
-        pxTopOfStack--;
-        *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
+            pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
+            *pxTopOfStack = portINITIAL_EXC_RETURN;
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+            #if ( configENABLE_TRUSTZONE == 1 )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+            }
+            #endif /* configENABLE_TRUSTZONE */
+        }
+        #else /* portPRELOAD_REGISTERS */
         {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
-        }
-        #endif /* configENABLE_TRUSTZONE */
-    }
-    #endif /* portPRELOAD_REGISTERS */
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
+            pxTopOfStack--;
+            *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack;            /* Slot used to hold this task's PSPLIM value. */
 
-    return pxTopOfStack;
-}
+            #if ( configENABLE_TRUSTZONE == 1 )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+            }
+            #endif /* configENABLE_TRUSTZONE */
+        }
+        #endif /* portPRELOAD_REGISTERS */
+
+        return pxTopOfStack;
+    }
 
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM35P/non_secure/portasm.c b/portable/GCC/ARM_CM35P/non_secure/portasm.c
index f7ec7d9c0..ba8f6c62d 100644
--- a/portable/GCC/ARM_CM35P/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM35P/non_secure/portasm.c
@@ -42,116 +42,116 @@
 
 #if ( configENABLE_MPU == 1 )
 
-void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        " .syntax unified                                 \n"
-        "                                                 \n"
-        " program_mpu_first_task:                         \n"
-        "    ldr r3, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB. */
-        "                                                 \n"
-        "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-        "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
-        "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
-        "    str r2, [r1]                                 \n" /* Disable MPU. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
-        "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-        "    ldr r2, xMAIR0Const2                         \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-        "    str r1, [r2]                                 \n" /* Program MAIR0. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-        "    ldr r1, xRNRConst2                           \n" /* r1 = 0xe000ed98 [Location of RNR]. */
-        "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "                                                 \n"
-        "    movs r3, #4                                  \n" /* r3 = 4. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 4. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-        "                                                 \n"
-        #if ( configTOTAL_MPU_REGIONS == 16 )
-        "    movs r3, #8                                  \n" /* r3 = 8. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 8. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-        "    movs r3, #12                                 \n" /* r3 = 12. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 12. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-        #endif /* configTOTAL_MPU_REGIONS == 16 */
-        "                                                 \n"
-        "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
-        "    orr r2, #1                                   \n" /* r2 = r1 | 1 i.e. Set the bit 0 in r2. */
-        "    str r2, [r1]                                 \n" /* Enable MPU. */
-        "    dsb                                          \n" /* Force memory writes before continuing. */
-        "                                                 \n"
-        " restore_context_first_task:                     \n"
-        "    ldr r3, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r1, [r3]                                 \n" /* r1 = pxCurrentTCB.*/
-        "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
-        "                                                 \n"
-        " restore_special_regs_first_task:                \n"
-        "    ldmdb r2!, {r0, r3-r5, lr}                   \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
-        "    msr psp, r3                                  \n"
-        "    msr psplim, r4                               \n"
-        "    msr control, r5                              \n"
-        "    ldr r4, xSecureContextConst2                 \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-        "    str r0, [r4]                                 \n" /* Restore xSecureContext. */
-        "                                                 \n"
-        " restore_general_regs_first_task:                \n"
-        "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
-        "    stmia r3!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
-        "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 restored. */
-        "                                                 \n"
-        " restore_context_done_first_task:                \n"
-        "    str r2, [r1]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
-        "    mov r0, #0                                   \n"
-        "    msr basepri, r0                              \n" /* Ensure that interrupts are enabled when the first task starts. */
-        "    bx lr                                        \n"
-        "                                                 \n"
-        " .align 4                                        \n"
-        " pxCurrentTCBConst2: .word pxCurrentTCB          \n"
-        " xSecureContextConst2: .word xSecureContext      \n"
-        " xMPUCTRLConst2: .word 0xe000ed94                \n"
-        " xMAIR0Const2: .word 0xe000edc0                  \n"
-        " xRNRConst2: .word 0xe000ed98                    \n"
-        " xRBARConst2: .word 0xe000ed9c                   \n"
-    );
-}
+    void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                 \n"
+            "                                                 \n"
+            " program_mpu_first_task:                         \n"
+            "    ldr r3, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB. */
+            "                                                 \n"
+            "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
+            "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
+            "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
+            "    str r2, [r1]                                 \n" /* Disable MPU. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
+            "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
+            "    ldr r2, xMAIR0Const2                         \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    str r1, [r2]                                 \n" /* Program MAIR0. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
+            "    ldr r1, xRNRConst2                           \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "                                                 \n"
+            "    movs r3, #4                                  \n" /* r3 = 4. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 4. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "                                                 \n"
+            #if ( configTOTAL_MPU_REGIONS == 16 )
+                "    movs r3, #8                                  \n" /* r3 = 8. */
+                "    str r3, [r1]                                 \n" /* Program RNR = 8. */
+                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
+                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+                "    movs r3, #12                                 \n" /* r3 = 12. */
+                "    str r3, [r1]                                 \n" /* Program RNR = 12. */
+                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
+                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            #endif /* configTOTAL_MPU_REGIONS == 16 */
+            "                                                 \n"
+            "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
+            "    orr r2, #1                                   \n" /* r2 = r1 | 1 i.e. Set the bit 0 in r2. */
+            "    str r2, [r1]                                 \n" /* Enable MPU. */
+            "    dsb                                          \n" /* Force memory writes before continuing. */
+            "                                                 \n"
+            " restore_context_first_task:                     \n"
+            "    ldr r3, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r1, [r3]                                 \n" /* r1 = pxCurrentTCB.*/
+            "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
+            "                                                 \n"
+            " restore_special_regs_first_task:                \n"
+            "    ldmdb r2!, {r0, r3-r5, lr}                   \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
+            "    msr psp, r3                                  \n"
+            "    msr psplim, r4                               \n"
+            "    msr control, r5                              \n"
+            "    ldr r4, xSecureContextConst2                 \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "    str r0, [r4]                                 \n" /* Restore xSecureContext. */
+            "                                                 \n"
+            " restore_general_regs_first_task:                \n"
+            "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
+            "    stmia r3!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
+            "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 restored. */
+            "                                                 \n"
+            " restore_context_done_first_task:                \n"
+            "    str r2, [r1]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
+            "    mov r0, #0                                   \n"
+            "    msr basepri, r0                              \n" /* Ensure that interrupts are enabled when the first task starts. */
+            "    bx lr                                        \n"
+            "                                                 \n"
+            " .align 4                                        \n"
+            " pxCurrentTCBConst2: .word pxCurrentTCB          \n"
+            " xSecureContextConst2: .word xSecureContext      \n"
+            " xMPUCTRLConst2: .word 0xe000ed94                \n"
+            " xMAIR0Const2: .word 0xe000edc0                  \n"
+            " xRNRConst2: .word 0xe000ed98                    \n"
+            " xRBARConst2: .word 0xe000ed9c                   \n"
+        );
+    }
 
 #else /* configENABLE_MPU */
 
-void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "   .syntax unified                                 \n"
-        "                                                   \n"
-        "   ldr  r2, pxCurrentTCBConst2                     \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr  r3, [r2]                                   \n" /* Read pxCurrentTCB. */
-        "   ldr  r0, [r3]                                   \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
-        "                                                   \n"
-        "   ldm  r0!, {r1-r3}                               \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
-        "   ldr  r4, xSecureContextConst2                   \n"
-        "   str  r1, [r4]                                   \n" /* Set xSecureContext to this task's value for the same. */
-        "   msr  psplim, r2                                 \n" /* Set this task's PSPLIM value. */
-        "   movs r1, #2                                     \n" /* r1 = 2. */
-        "   msr  CONTROL, r1                                \n" /* Switch to use PSP in the thread mode. */
-        "   adds r0, #32                                    \n" /* Discard everything up to r0. */
-        "   msr  psp, r0                                    \n" /* This is now the new top of stack to use in the task. */
-        "   isb                                             \n"
-        "   mov  r0, #0                                     \n"
-        "   msr  basepri, r0                                \n" /* Ensure that interrupts are enabled when the first task starts. */
-        "   bx   r3                                         \n" /* Finally, branch to EXC_RETURN. */
-        "   .align 4                                        \n"
-        "pxCurrentTCBConst2: .word pxCurrentTCB             \n"
-        "xSecureContextConst2: .word xSecureContext         \n"
-    );
-}
+    void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            "   .syntax unified                                 \n"
+            "                                                   \n"
+            "   ldr  r2, pxCurrentTCBConst2                     \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr  r3, [r2]                                   \n" /* Read pxCurrentTCB. */
+            "   ldr  r0, [r3]                                   \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+            "                                                   \n"
+            "   ldm  r0!, {r1-r3}                               \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
+            "   ldr  r4, xSecureContextConst2                   \n"
+            "   str  r1, [r4]                                   \n" /* Set xSecureContext to this task's value for the same. */
+            "   msr  psplim, r2                                 \n" /* Set this task's PSPLIM value. */
+            "   movs r1, #2                                     \n" /* r1 = 2. */
+            "   msr  CONTROL, r1                                \n" /* Switch to use PSP in the thread mode. */
+            "   adds r0, #32                                    \n" /* Discard everything up to r0. */
+            "   msr  psp, r0                                    \n" /* This is now the new top of stack to use in the task. */
+            "   isb                                             \n"
+            "   mov  r0, #0                                     \n"
+            "   msr  basepri, r0                                \n" /* Ensure that interrupts are enabled when the first task starts. */
+            "   bx   r3                                         \n" /* Finally, branch to EXC_RETURN. */
+            "   .align 4                                        \n"
+            "pxCurrentTCBConst2: .word pxCurrentTCB             \n"
+            "xSecureContextConst2: .word xSecureContext         \n"
+        );
+    }
 
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
@@ -162,12 +162,12 @@ BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs r0, control                                 \n"/* r0 = CONTROL. */
-        "   tst r0, #1                                      \n"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+        "   mrs r0, control                                 \n" /* r0 = CONTROL. */
+        "   tst r0, #1                                      \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
         "   ite ne                                          \n"
-        "   movne r0, #0                                    \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
-        "   moveq r0, #1                                    \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
-        "   bx lr                                           \n"/* Return. */
+        "   movne r0, #0                                    \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+        "   moveq r0, #1                                    \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+        "   bx lr                                           \n" /* Return. */
         "                                                   \n"
         "   .align 4                                        \n"
         ::: "r0", "memory"
@@ -181,10 +181,10 @@ void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs r0, control                                 \n"/* Read the CONTROL register. */
-        "   bic r0, #1                                      \n"/* Clear the bit 0. */
-        "   msr control, r0                                 \n"/* Write back the new CONTROL value. */
-        "   bx lr                                           \n"/* Return to the caller. */
+        "   mrs r0, control                                 \n" /* Read the CONTROL register. */
+        "   bic r0, #1                                      \n" /* Clear the bit 0. */
+        "   msr control, r0                                 \n" /* Write back the new CONTROL value. */
+        "   bx lr                                           \n" /* Return to the caller. */
         ::: "r0", "memory"
     );
 }
@@ -196,10 +196,10 @@ void vResetPrivilege( void ) /* __attribute__ (( naked )) */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs r0, control                                 \n"/* r0 = CONTROL. */
-        "   orr r0, #1                                      \n"/* r0 = r0 | 1. */
-        "   msr control, r0                                 \n"/* CONTROL = r0. */
-        "   bx lr                                           \n"/* Return to the caller. */
+        "   mrs r0, control                                 \n" /* r0 = CONTROL. */
+        "   orr r0, #1                                      \n" /* r0 = r0 | 1. */
+        "   msr control, r0                                 \n" /* CONTROL = r0. */
+        "   bx lr                                           \n" /* Return to the caller. */
         ::: "r0", "memory"
     );
 }
@@ -211,15 +211,15 @@ void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   ldr r0, xVTORConst                              \n"/* Use the NVIC offset register to locate the stack. */
-        "   ldr r0, [r0]                                    \n"/* Read the VTOR register which gives the address of vector table. */
-        "   ldr r0, [r0]                                    \n"/* The first entry in vector table is stack pointer. */
-        "   msr msp, r0                                     \n"/* Set the MSP back to the start of the stack. */
-        "   cpsie i                                         \n"/* Globally enable interrupts. */
+        "   ldr r0, xVTORConst                              \n" /* Use the NVIC offset register to locate the stack. */
+        "   ldr r0, [r0]                                    \n" /* Read the VTOR register which gives the address of vector table. */
+        "   ldr r0, [r0]                                    \n" /* The first entry in vector table is stack pointer. */
+        "   msr msp, r0                                     \n" /* Set the MSP back to the start of the stack. */
+        "   cpsie i                                         \n" /* Globally enable interrupts. */
         "   cpsie f                                         \n"
         "   dsb                                             \n"
         "   isb                                             \n"
-        "   svc %0                                          \n"/* System call to start the first task. */
+        "   svc %0                                          \n" /* System call to start the first task. */
         "   nop                                             \n"
         "                                                   \n"
         "   .align 4                                        \n"
@@ -235,12 +235,12 @@ uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCT
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs r0, basepri                                 \n"/* r0 = basepri. Return original basepri value. */
-        "   mov r1, %0                                      \n"/* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        "   msr basepri, r1                                 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        "   mrs r0, basepri                                 \n" /* r0 = basepri. Return original basepri value. */
+        "   mov r1, %0                                      \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        "   msr basepri, r1                                 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
         "   dsb                                             \n"
         "   isb                                             \n"
-        "   bx lr                                           \n"/* Return. */
+        "   bx lr                                           \n" /* Return. */
         ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
     );
 }
@@ -252,10 +252,10 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   msr basepri, r0                                 \n"/* basepri = ulMask. */
+        "   msr basepri, r0                                 \n" /* basepri = ulMask. */
         "   dsb                                             \n"
         "   isb                                             \n"
-        "   bx lr                                           \n"/* Return. */
+        "   bx lr                                           \n" /* Return. */
         ::: "memory"
     );
 }
@@ -263,320 +263,320 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
 
 #if ( configENABLE_MPU == 1 )
 
-void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        " .syntax unified                                 \n"
-        " .extern SecureContext_SaveContext               \n"
-        " .extern SecureContext_LoadContext               \n"
-        "                                                 \n"
-        " ldr r3, xSecureContextConst                     \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-        " ldr r0, [r3]                                    \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
-        " ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        " ldr r1, [r3]                                    \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
-        " ldr r2, [r1]                                    \n" /* r2 = Location in TCB where the context should be saved. */
-        "                                                 \n"
-        " cbz r0, save_ns_context                         \n" /* No secure context to save. */
-        " save_s_context:                                 \n"
-        "    push {r0-r2, lr}                             \n"
-        "    bl SecureContext_SaveContext                 \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-        "    pop {r0-r2, lr}                              \n"
-        "                                                 \n"
-        " save_ns_context:                                \n"
-        "    mov r3, lr                                   \n" /* r3 = LR (EXC_RETURN). */
-        "    lsls r3, r3, #25                             \n" /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-        "    bmi save_special_regs                        \n" /* r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
-        "                                                 \n"
-        " save_general_regs:                              \n"
-        "    mrs r3, psp                                  \n"
-        "                                                 \n"
-    #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-        "    add r3, r3, #0x20                            \n" /* Move r3 to location where s0 is saved. */
-        "    tst lr, #0x10                                \n"
-        "    ittt eq                                      \n"
-        "    vstmiaeq r2!, {s16-s31}                      \n" /* Store s16-s31. */
-        "    vldmiaeq r3, {s0-s16}                        \n" /* Copy hardware saved FP context into s0-s16. */
-        "    vstmiaeq r2!, {s0-s16}                       \n" /* Store hardware saved FP context. */
-        "    sub r3, r3, #0x20                            \n" /* Set r3 back to the location of hardware saved context. */
-    #endif /* configENABLE_FPU || configENABLE_MVE */
-        "                                                 \n"
-        "    stmia r2!, {r4-r11}                          \n" /* Store r4-r11. */
-        "    ldmia r3, {r4-r11}                           \n" /* Copy the hardware saved context into r4-r11. */
-        "    stmia r2!, {r4-r11}                          \n" /* Store the hardware saved context. */
-        "                                                 \n"
-        " save_special_regs:                              \n"
-        "    mrs r3, psp                                  \n" /* r3 = PSP. */
-        "    mrs r4, psplim                               \n" /* r4 = PSPLIM. */
-        "    mrs r5, control                              \n" /* r5 = CONTROL. */
-        "    stmia r2!, {r0, r3-r5, lr}                   \n" /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
-        "    str r2, [r1]                                 \n" /* Save the location from where the context should be restored as the first member of TCB. */
-        "                                                 \n"
-        " select_next_task:                               \n"
-        "    mov r0, %0                                   \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
-        "    msr basepri, r0                              \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        "    dsb                                          \n"
-        "    isb                                          \n"
-        "    bl vTaskSwitchContext                        \n"
-        "    mov r0, #0                                   \n" /* r0 = 0. */
-        "    msr basepri, r0                              \n" /* Enable interrupts. */
-        "                                                 \n"
-        " program_mpu:                                    \n"
-        "    ldr r3, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB.*/
-        "                                                 \n"
-        "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-        "    ldr r1, xMPUCTRLConst                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
-        "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
-        "    str r2, [r1]                                 \n" /* Disable MPU. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
-        "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-        "    ldr r2, xMAIR0Const                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-        "    str r1, [r2]                                 \n" /* Program MAIR0. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-        "    ldr r1, xRNRConst                            \n" /* r1 = 0xe000ed98 [Location of RNR]. */
-        "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "                                                 \n"
-        "    movs r3, #4                                  \n" /* r3 = 4. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 4. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-        "                                                 \n"
-        #if ( configTOTAL_MPU_REGIONS == 16 )
-        "    movs r3, #8                                  \n" /* r3 = 8. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 8. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-        "    movs r3, #12                                 \n" /* r3 = 12. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 12. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-        #endif /* configTOTAL_MPU_REGIONS == 16 */
-        "                                                 \n"
-        "   ldr r1, xMPUCTRLConst                         \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
-        "   orr r2, #1                                    \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
-        "   str r2, [r1]                                  \n" /* Enable MPU. */
-        "   dsb                                           \n" /* Force memory writes before continuing. */
-        "                                                 \n"
-        " restore_context:                                \n"
-        "    ldr r3, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r1, [r3]                                 \n" /* r1 = pxCurrentTCB.*/
-        "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
-        "                                                 \n"
-        " restore_special_regs:                           \n"
-        "    ldmdb r2!, {r0, r3-r5, lr}                   \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
-        "    msr psp, r3                                  \n"
-        "    msr psplim, r4                               \n"
-        "    msr control, r5                              \n"
-        "    ldr r4, xSecureContextConst                  \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-        "    str r0, [r4]                                 \n" /* Restore xSecureContext. */
-        "    cbz r0, restore_ns_context                   \n" /* No secure context to restore. */
-        "                                                 \n"
-        " restore_s_context:                              \n"
-        "    push {r1-r3, lr}                             \n"
-        "    bl SecureContext_LoadContext                 \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-        "    pop {r1-r3, lr}                              \n"
-        "                                                 \n"
-        " restore_ns_context:                             \n"
-        "    mov r0, lr                                   \n" /* r0 = LR (EXC_RETURN). */
-        "    lsls r0, r0, #25                             \n" /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-        "    bmi restore_context_done                     \n" /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
-        "                                                 \n"
-        " restore_general_regs:                           \n"
-        "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
-        "    stmia r3!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
-        "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 restored. */
-    #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-        "    tst lr, #0x10                                \n"
-        "    ittt eq                                      \n"
-        "    vldmdbeq r2!, {s0-s16}                       \n" /* s0-s16 contain hardware saved FP context. */
-        "    vstmiaeq r3!, {s0-s16}                       \n" /* Copy hardware saved FP context on the task stack. */
-        "    vldmdbeq r2!, {s16-s31}                      \n" /* Restore s16-s31. */
-    #endif /* configENABLE_FPU || configENABLE_MVE */
-        "                                                 \n"
-        " restore_context_done:                           \n"
-        "    str r2, [r1]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
-        "    bx lr                                        \n"
-        "                                                 \n"
-        " .align 4                                        \n"
-        " pxCurrentTCBConst: .word pxCurrentTCB           \n"
-        " xSecureContextConst: .word xSecureContext       \n"
-        " xMPUCTRLConst: .word 0xe000ed94                 \n"
-        " xMAIR0Const: .word 0xe000edc0                   \n"
-        " xRNRConst: .word 0xe000ed98                     \n"
-        " xRBARConst: .word 0xe000ed9c                    \n"
-        ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
-    );
-}
+    void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                 \n"
+            " .extern SecureContext_SaveContext               \n"
+            " .extern SecureContext_LoadContext               \n"
+            "                                                 \n"
+            " ldr r3, xSecureContextConst                     \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            " ldr r0, [r3]                                    \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+            " ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            " ldr r1, [r3]                                    \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
+            " ldr r2, [r1]                                    \n" /* r2 = Location in TCB where the context should be saved. */
+            "                                                 \n"
+            " cbz r0, save_ns_context                         \n" /* No secure context to save. */
+            " save_s_context:                                 \n"
+            "    push {r0-r2, lr}                             \n"
+            "    bl SecureContext_SaveContext                 \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+            "    pop {r0-r2, lr}                              \n"
+            "                                                 \n"
+            " save_ns_context:                                \n"
+            "    mov r3, lr                                   \n" /* r3 = LR (EXC_RETURN). */
+            "    lsls r3, r3, #25                             \n" /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+            "    bmi save_special_regs                        \n" /* r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
+            "                                                 \n"
+            " save_general_regs:                              \n"
+            "    mrs r3, psp                                  \n"
+            "                                                 \n"
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+                "    add r3, r3, #0x20                            \n" /* Move r3 to location where s0 is saved. */
+                "    tst lr, #0x10                                \n"
+                "    ittt eq                                      \n"
+                "    vstmiaeq r2!, {s16-s31}                      \n" /* Store s16-s31. */
+                "    vldmiaeq r3, {s0-s16}                        \n" /* Copy hardware saved FP context into s0-s16. */
+                "    vstmiaeq r2!, {s0-s16}                       \n" /* Store hardware saved FP context. */
+                "    sub r3, r3, #0x20                            \n" /* Set r3 back to the location of hardware saved context. */
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+            "                                                 \n"
+            "    stmia r2!, {r4-r11}                          \n" /* Store r4-r11. */
+            "    ldmia r3, {r4-r11}                           \n" /* Copy the hardware saved context into r4-r11. */
+            "    stmia r2!, {r4-r11}                          \n" /* Store the hardware saved context. */
+            "                                                 \n"
+            " save_special_regs:                              \n"
+            "    mrs r3, psp                                  \n" /* r3 = PSP. */
+            "    mrs r4, psplim                               \n" /* r4 = PSPLIM. */
+            "    mrs r5, control                              \n" /* r5 = CONTROL. */
+            "    stmia r2!, {r0, r3-r5, lr}                   \n" /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
+            "    str r2, [r1]                                 \n" /* Save the location from where the context should be restored as the first member of TCB. */
+            "                                                 \n"
+            " select_next_task:                               \n"
+            "    mov r0, %0                                   \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
+            "    msr basepri, r0                              \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+            "    dsb                                          \n"
+            "    isb                                          \n"
+            "    bl vTaskSwitchContext                        \n"
+            "    mov r0, #0                                   \n" /* r0 = 0. */
+            "    msr basepri, r0                              \n" /* Enable interrupts. */
+            "                                                 \n"
+            " program_mpu:                                    \n"
+            "    ldr r3, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB.*/
+            "                                                 \n"
+            "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
+            "    ldr r1, xMPUCTRLConst                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
+            "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
+            "    str r2, [r1]                                 \n" /* Disable MPU. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
+            "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
+            "    ldr r2, xMAIR0Const                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    str r1, [r2]                                 \n" /* Program MAIR0. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
+            "    ldr r1, xRNRConst                            \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "                                                 \n"
+            "    movs r3, #4                                  \n" /* r3 = 4. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 4. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "                                                 \n"
+            #if ( configTOTAL_MPU_REGIONS == 16 )
+                "    movs r3, #8                                  \n" /* r3 = 8. */
+                "    str r3, [r1]                                 \n" /* Program RNR = 8. */
+                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+                "    movs r3, #12                                 \n" /* r3 = 12. */
+                "    str r3, [r1]                                 \n" /* Program RNR = 12. */
+                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            #endif /* configTOTAL_MPU_REGIONS == 16 */
+            "                                                 \n"
+            "   ldr r1, xMPUCTRLConst                         \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
+            "   orr r2, #1                                    \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
+            "   str r2, [r1]                                  \n" /* Enable MPU. */
+            "   dsb                                           \n" /* Force memory writes before continuing. */
+            "                                                 \n"
+            " restore_context:                                \n"
+            "    ldr r3, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r1, [r3]                                 \n" /* r1 = pxCurrentTCB.*/
+            "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
+            "                                                 \n"
+            " restore_special_regs:                           \n"
+            "    ldmdb r2!, {r0, r3-r5, lr}                   \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
+            "    msr psp, r3                                  \n"
+            "    msr psplim, r4                               \n"
+            "    msr control, r5                              \n"
+            "    ldr r4, xSecureContextConst                  \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "    str r0, [r4]                                 \n" /* Restore xSecureContext. */
+            "    cbz r0, restore_ns_context                   \n" /* No secure context to restore. */
+            "                                                 \n"
+            " restore_s_context:                              \n"
+            "    push {r1-r3, lr}                             \n"
+            "    bl SecureContext_LoadContext                 \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+            "    pop {r1-r3, lr}                              \n"
+            "                                                 \n"
+            " restore_ns_context:                             \n"
+            "    mov r0, lr                                   \n" /* r0 = LR (EXC_RETURN). */
+            "    lsls r0, r0, #25                             \n" /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+            "    bmi restore_context_done                     \n" /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
+            "                                                 \n"
+            " restore_general_regs:                           \n"
+            "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
+            "    stmia r3!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
+            "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 restored. */
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+                "    tst lr, #0x10                                \n"
+                "    ittt eq                                      \n"
+                "    vldmdbeq r2!, {s0-s16}                       \n" /* s0-s16 contain hardware saved FP context. */
+                "    vstmiaeq r3!, {s0-s16}                       \n" /* Copy hardware saved FP context on the task stack. */
+                "    vldmdbeq r2!, {s16-s31}                      \n" /* Restore s16-s31. */
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+            "                                                 \n"
+            " restore_context_done:                           \n"
+            "    str r2, [r1]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
+            "    bx lr                                        \n"
+            "                                                 \n"
+            " .align 4                                        \n"
+            " pxCurrentTCBConst: .word pxCurrentTCB           \n"
+            " xSecureContextConst: .word xSecureContext       \n"
+            " xMPUCTRLConst: .word 0xe000ed94                 \n"
+            " xMAIR0Const: .word 0xe000edc0                   \n"
+            " xRNRConst: .word 0xe000ed98                     \n"
+            " xRBARConst: .word 0xe000ed9c                    \n"
+            ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+        );
+    }
 
 #else /* configENABLE_MPU */
 
-void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "   .syntax unified                                 \n"
-        "   .extern SecureContext_SaveContext               \n"
-        "   .extern SecureContext_LoadContext               \n"
-        "                                                   \n"
-        "   ldr r3, xSecureContextConst                     \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
-        "   ldr r0, [r3]                                    \n"/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
-        "   ldr r3, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r3]                                    \n"/* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
-        "   mrs r2, psp                                     \n"/* Read PSP in r2. */
-        "                                                   \n"
-        "   cbz r0, save_ns_context                         \n"/* No secure context to save. */
-        "   push {r0-r2, r14}                               \n"
-        "   bl SecureContext_SaveContext                    \n"/* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-        "   pop {r0-r3}                                     \n"/* LR is now in r3. */
-        "   mov lr, r3                                      \n"/* LR = r3. */
-        "   lsls r1, r3, #25                                \n"/* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-        "   bpl save_ns_context                             \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-        "                                                   \n"
-        "   ldr r3, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r3]                                    \n"/* Read pxCurrentTCB.*/
-        "   subs r2, r2, #12                                \n"/* Make space for xSecureContext, PSPLIM and LR on the stack. */
-        "   str r2, [r1]                                    \n"/* Save the new top of stack in TCB. */
-        "   mrs r1, psplim                                  \n"/* r1 = PSPLIM. */
-        "   mov r3, lr                                      \n"/* r3 = LR/EXC_RETURN. */
-        "   stmia r2!, {r0, r1, r3}                         \n"/* Store xSecureContext, PSPLIM and LR on the stack. */
-        "   b select_next_task                              \n"
-        "                                                   \n"
-        " save_ns_context:                                  \n"
-        "   ldr r3, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r3]                                    \n"/* Read pxCurrentTCB. */
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-            "   tst lr, #0x10                               \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
-            "   it eq                                       \n"
-            "   vstmdbeq r2!, {s16-s31}                     \n"/* Store the additional FP context registers which are not saved automatically. */
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-        "   subs r2, r2, #44                                \n"/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
-        "   str r2, [r1]                                    \n"/* Save the new top of stack in TCB. */
-        "   adds r2, r2, #12                                \n"/* r2 = r2 + 12. */
-        "   stm r2, {r4-r11}                                \n"/* Store the registers that are not saved automatically. */
-        "   mrs r1, psplim                                  \n"/* r1 = PSPLIM. */
-        "   mov r3, lr                                      \n"/* r3 = LR/EXC_RETURN. */
-        "   subs r2, r2, #12                                \n"/* r2 = r2 - 12. */
-        "   stmia r2!, {r0, r1, r3}                         \n"/* Store xSecureContext, PSPLIM and LR on the stack. */
-        "                                                   \n"
-        " select_next_task:                                 \n"
-        "   mov r0, %0                                      \n"/* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
-        "   msr basepri, r0                                 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        "   dsb                                             \n"
-        "   isb                                             \n"
-        "   bl vTaskSwitchContext                           \n"
-        "   mov r0, #0                                      \n"/* r0 = 0. */
-        "   msr basepri, r0                                 \n"/* Enable interrupts. */
-        "                                                   \n"
-        "   ldr r3, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r3]                                    \n"/* Read pxCurrentTCB. */
-        "   ldr r2, [r1]                                    \n"/* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
-        "                                                   \n"
-        "   ldmia r2!, {r0, r1, r4}                         \n"/* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
-        "   msr psplim, r1                                  \n"/* Restore the PSPLIM register value for the task. */
-        "   mov lr, r4                                      \n"/* LR = r4. */
-        "   ldr r3, xSecureContextConst                     \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
-        "   str r0, [r3]                                    \n"/* Restore the task's xSecureContext. */
-        "   cbz r0, restore_ns_context                      \n"/* If there is no secure context for the task, restore the non-secure context. */
-        "   ldr r3, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r3]                                    \n"/* Read pxCurrentTCB. */
-        "   push {r2, r4}                                   \n"
-        "   bl SecureContext_LoadContext                    \n"/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-        "   pop {r2, r4}                                    \n"
-        "   mov lr, r4                                      \n"/* LR = r4. */
-        "   lsls r1, r4, #25                                \n"/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-        "   bpl restore_ns_context                          \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-        "   msr psp, r2                                     \n"/* Remember the new top of stack for the task. */
-        "   bx lr                                           \n"
-        "                                                   \n"
-        " restore_ns_context:                               \n"
-        "   ldmia r2!, {r4-r11}                             \n"/* Restore the registers that are not automatically restored. */
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-            "   tst lr, #0x10                               \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
-            "   it eq                                       \n"
-            "   vldmiaeq r2!, {s16-s31}                     \n"/* Restore the additional FP context registers which are not restored automatically. */
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-        "   msr psp, r2                                     \n"/* Remember the new top of stack for the task. */
-        "   bx lr                                           \n"
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "pxCurrentTCBConst: .word pxCurrentTCB              \n"
-        "xSecureContextConst: .word xSecureContext          \n"
-        ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
-    );
-}
+    void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            "   .syntax unified                                 \n"
+            "   .extern SecureContext_SaveContext               \n"
+            "   .extern SecureContext_LoadContext               \n"
+            "                                                   \n"
+            "   ldr r3, xSecureContextConst                     \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "   ldr r0, [r3]                                    \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
+            "   mrs r2, psp                                     \n" /* Read PSP in r2. */
+            "                                                   \n"
+            "   cbz r0, save_ns_context                         \n" /* No secure context to save. */
+            "   push {r0-r2, r14}                               \n"
+            "   bl SecureContext_SaveContext                    \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+            "   pop {r0-r3}                                     \n" /* LR is now in r3. */
+            "   mov lr, r3                                      \n" /* LR = r3. */
+            "   lsls r1, r3, #25                                \n" /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+            "   bpl save_ns_context                             \n" /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+            "                                                   \n"
+            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB.*/
+            "   subs r2, r2, #12                                \n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */
+            "   str r2, [r1]                                    \n" /* Save the new top of stack in TCB. */
+            "   mrs r1, psplim                                  \n" /* r1 = PSPLIM. */
+            "   mov r3, lr                                      \n" /* r3 = LR/EXC_RETURN. */
+            "   stmia r2!, {r0, r1, r3}                         \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
+            "   b select_next_task                              \n"
+            "                                                   \n"
+            " save_ns_context:                                  \n"
+            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+                "   tst lr, #0x10                               \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+                "   it eq                                       \n"
+                "   vstmdbeq r2!, {s16-s31}                     \n" /* Store the additional FP context registers which are not saved automatically. */
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+            "   subs r2, r2, #44                                \n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
+            "   str r2, [r1]                                    \n" /* Save the new top of stack in TCB. */
+            "   adds r2, r2, #12                                \n" /* r2 = r2 + 12. */
+            "   stm r2, {r4-r11}                                \n" /* Store the registers that are not saved automatically. */
+            "   mrs r1, psplim                                  \n" /* r1 = PSPLIM. */
+            "   mov r3, lr                                      \n" /* r3 = LR/EXC_RETURN. */
+            "   subs r2, r2, #12                                \n" /* r2 = r2 - 12. */
+            "   stmia r2!, {r0, r1, r3}                         \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
+            "                                                   \n"
+            " select_next_task:                                 \n"
+            "   mov r0, %0                                      \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
+            "   msr basepri, r0                                 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+            "   dsb                                             \n"
+            "   isb                                             \n"
+            "   bl vTaskSwitchContext                           \n"
+            "   mov r0, #0                                      \n" /* r0 = 0. */
+            "   msr basepri, r0                                 \n" /* Enable interrupts. */
+            "                                                   \n"
+            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
+            "   ldr r2, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
+            "                                                   \n"
+            "   ldmia r2!, {r0, r1, r4}                         \n" /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
+            "   msr psplim, r1                                  \n" /* Restore the PSPLIM register value for the task. */
+            "   mov lr, r4                                      \n" /* LR = r4. */
+            "   ldr r3, xSecureContextConst                     \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "   str r0, [r3]                                    \n" /* Restore the task's xSecureContext. */
+            "   cbz r0, restore_ns_context                      \n" /* If there is no secure context for the task, restore the non-secure context. */
+            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
+            "   push {r2, r4}                                   \n"
+            "   bl SecureContext_LoadContext                    \n" /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+            "   pop {r2, r4}                                    \n"
+            "   mov lr, r4                                      \n" /* LR = r4. */
+            "   lsls r1, r4, #25                                \n" /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+            "   bpl restore_ns_context                          \n" /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+            "   msr psp, r2                                     \n" /* Remember the new top of stack for the task. */
+            "   bx lr                                           \n"
+            "                                                   \n"
+            " restore_ns_context:                               \n"
+            "   ldmia r2!, {r4-r11}                             \n" /* Restore the registers that are not automatically restored. */
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+                "   tst lr, #0x10                               \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+                "   it eq                                       \n"
+                "   vldmiaeq r2!, {s16-s31}                     \n" /* Restore the additional FP context registers which are not restored automatically. */
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+            "   msr psp, r2                                     \n" /* Remember the new top of stack for the task. */
+            "   bx lr                                           \n"
+            "                                                   \n"
+            "   .align 4                                        \n"
+            "pxCurrentTCBConst: .word pxCurrentTCB              \n"
+            "xSecureContextConst: .word xSecureContext          \n"
+            ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+        );
+    }
 
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-   __asm volatile
-    (
-        ".syntax unified                \n"
-        ".extern vPortSVCHandler_C      \n"
-        ".extern vSystemCallEnter       \n"
-        ".extern vSystemCallEnter_1     \n"
-        ".extern vSystemCallExit        \n"
-        "                               \n"
-        "tst lr, #4                     \n"
-        "ite eq                         \n"
-        "mrseq r0, msp                  \n"
-        "mrsne r0, psp                  \n"
-        "                               \n"
-        "ldr r1, [r0, #24]              \n"
-        "ldrb r2, [r1, #-2]             \n"
-        "cmp r2, %0                     \n"
-        "beq syscall_enter              \n"
-        "cmp r2, %1                     \n"
-        "beq syscall_enter_1            \n"
-        "cmp r2, %2                     \n"
-        "beq syscall_exit               \n"
-        "b vPortSVCHandler_C            \n"
-        "                               \n"
-        "syscall_enter:                 \n"
-        "    mov r1, lr                 \n"
-        "    b vSystemCallEnter         \n"
-        "                               \n"
-        "syscall_enter_1:               \n"
-        "    mov r1, lr                 \n"
-        "    b vSystemCallEnter_1       \n"
-        "                               \n"
-        "syscall_exit:                  \n"
-        "    mov r1, lr                 \n"
-        "    b vSystemCallExit          \n"
-        "                               \n"
-        : /* No outputs. */
-        :"i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT )
-        : "r0", "r1", "r2", "memory"
-    );
-}
+    void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            ".syntax unified                \n"
+            ".extern vPortSVCHandler_C      \n"
+            ".extern vSystemCallEnter       \n"
+            ".extern vSystemCallEnter_1     \n"
+            ".extern vSystemCallExit        \n"
+            "                               \n"
+            "tst lr, #4                     \n"
+            "ite eq                         \n"
+            "mrseq r0, msp                  \n"
+            "mrsne r0, psp                  \n"
+            "                               \n"
+            "ldr r1, [r0, #24]              \n"
+            "ldrb r2, [r1, #-2]             \n"
+            "cmp r2, %0                     \n"
+            "beq syscall_enter              \n"
+            "cmp r2, %1                     \n"
+            "beq syscall_enter_1            \n"
+            "cmp r2, %2                     \n"
+            "beq syscall_exit               \n"
+            "b vPortSVCHandler_C            \n"
+            "                               \n"
+            "syscall_enter:                 \n"
+            "    mov r1, lr                 \n"
+            "    b vSystemCallEnter         \n"
+            "                               \n"
+            "syscall_enter_1:               \n"
+            "    mov r1, lr                 \n"
+            "    b vSystemCallEnter_1       \n"
+            "                               \n"
+            "syscall_exit:                  \n"
+            "    mov r1, lr                 \n"
+            "    b vSystemCallExit          \n"
+            "                               \n"
+            : /* No outputs. */
+            : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT )
+            : "r0", "r1", "r2", "memory"
+        );
+    }
 
 #else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
-void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "   .syntax unified                                 \n"
-        "                                                   \n"
-        "   tst lr, #4                                      \n"
-        "   ite eq                                          \n"
-        "   mrseq r0, msp                                   \n"
-        "   mrsne r0, psp                                   \n"
-        "   ldr r1, svchandler_address_const                \n"
-        "   bx r1                                           \n"
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "svchandler_address_const: .word vPortSVCHandler_C  \n"
-    );
-}
+    void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            "   .syntax unified                                 \n"
+            "                                                   \n"
+            "   tst lr, #4                                      \n"
+            "   ite eq                                          \n"
+            "   mrseq r0, msp                                   \n"
+            "   mrsne r0, psp                                   \n"
+            "   ldr r1, svchandler_address_const                \n"
+            "   bx r1                                           \n"
+            "                                                   \n"
+            "   .align 4                                        \n"
+            "svchandler_address_const: .word vPortSVCHandler_C  \n"
+        );
+    }
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
@@ -587,8 +587,8 @@ void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   svc %0                                          \n"/* Secure context is allocated in the supervisor call. */
-        "   bx lr                                           \n"/* Return. */
+        "   svc %0                                          \n" /* Secure context is allocated in the supervisor call. */
+        "   bx lr                                           \n" /* Return. */
         ::"i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"
     );
 }
@@ -600,12 +600,12 @@ void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PR
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   ldr r2, [r0]                                    \n"/* The first item in the TCB is the top of the stack. */
-        "   ldr r1, [r2]                                    \n"/* The first item on the stack is the task's xSecureContext. */
-        "   cmp r1, #0                                      \n"/* Raise svc if task's xSecureContext is not NULL. */
+        "   ldr r2, [r0]                                    \n" /* The first item in the TCB is the top of the stack. */
+        "   ldr r1, [r2]                                    \n" /* The first item on the stack is the task's xSecureContext. */
+        "   cmp r1, #0                                      \n" /* Raise svc if task's xSecureContext is not NULL. */
         "   it ne                                           \n"
-        "   svcne %0                                        \n"/* Secure context is freed in the supervisor call. */
-        "   bx lr                                           \n"/* Return. */
+        "   svcne %0                                        \n" /* Secure context is freed in the supervisor call. */
+        "   bx lr                                           \n" /* Return. */
         ::"i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"
     );
 }
diff --git a/portable/GCC/ARM_CM35P/non_secure/portmacro.h b/portable/GCC/ARM_CM35P/non_secure/portmacro.h
index 6e4fe5a3d..66fa2056d 100644
--- a/portable/GCC/ARM_CM35P/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM35P/non_secure/portmacro.h
@@ -48,9 +48,9 @@
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME                       "Cortex-M35P"
-#define portHAS_ARMV8M_MAIN_EXTENSION       1
-#define portDONT_DISCARD                    __attribute__( ( used ) )
+#define portARCH_NAME                    "Cortex-M35P"
+#define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
 /* ARMv8-M common port configurations. */
@@ -60,8 +60,8 @@
 /**
  * @brief Critical section management.
  */
-#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()
-#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )
+#define portDISABLE_INTERRUPTS()    ulSetInterruptMask()
+#define portENABLE_INTERRUPTS()     vClearInterruptMask( 0 )
 /*-----------------------------------------------------------*/
 
 /* *INDENT-OFF* */
diff --git a/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h
index e5ffdb48b..62e462a27 100644
--- a/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h
@@ -81,8 +81,8 @@ typedef unsigned long    UBaseType_t;
     typedef uint32_t     TickType_t;
     #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-     * not need to be guarded with a critical section. */
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
     #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -117,7 +117,7 @@ extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGE
 extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
 
 #if ( configENABLE_TRUSTZONE == 1 )
-    extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize );     /* __attribute__ (( naked )) */
+    extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
     extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
 #endif /* configENABLE_TRUSTZONE */
 
@@ -188,13 +188,13 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Settings to define an MPU region.
-     */
+/**
+ * @brief Settings to define an MPU region.
+ */
     typedef struct MPURegionSettings
     {
-        uint32_t ulRBAR;     /**< RBAR for the region. */
-        uint32_t ulRLAR;     /**< RLAR for the region. */
+        uint32_t ulRBAR; /**< RBAR for the region. */
+        uint32_t ulRLAR; /**< RLAR for the region. */
     } MPURegionSettings_t;
 
     #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
@@ -203,9 +203,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-        /**
-         * @brief System call stack.
-         */
+/**
+ * @brief System call stack.
+ */
         typedef struct SYSTEM_CALL_STACK_INFO
         {
             uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ];
@@ -218,74 +218,74 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
-    /**
-     * @brief MPU settings as stored in the TCB.
-     */
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
     #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
 
-        #if( configENABLE_TRUSTZONE == 1 )
+        #if ( configENABLE_TRUSTZONE == 1 )
 
-            /*
-             * +-----------+---------------+----------+-----------------+------------------------------+-----+
-             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
-             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
-             * +-----------+---------------+----------+-----------------+------------------------------+-----+
-             *
-             * <-----------><--------------><---------><----------------><-----------------------------><---->
-             *      16             16            8               8                     5                   1
-             */
-            #define MAX_CONTEXT_SIZE 54
+/*
+ * +-----------+---------------+----------+-----------------+------------------------------+-----+
+ * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+ * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+ * +-----------+---------------+----------+-----------------+------------------------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><-----------------------------><---->
+ *      16             16            8               8                     5                   1
+ */
+            #define MAX_CONTEXT_SIZE    54
 
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-            /*
-             * +-----------+---------------+----------+-----------------+----------------------+-----+
-             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
-             * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
-             * +-----------+---------------+----------+-----------------+----------------------+-----+
-             *
-             * <-----------><--------------><---------><----------------><---------------------><---->
-             *      16             16            8               8                  4              1
-             */
-            #define MAX_CONTEXT_SIZE 53
+/*
+ * +-----------+---------------+----------+-----------------+----------------------+-----+
+ * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+ * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
+ * +-----------+---------------+----------+-----------------+----------------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><---------------------><---->
+ *      16             16            8               8                  4              1
+ */
+            #define MAX_CONTEXT_SIZE    53
 
         #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
 
     #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-        #if( configENABLE_TRUSTZONE == 1 )
+        #if ( configENABLE_TRUSTZONE == 1 )
 
-            /*
-             * +----------+-----------------+------------------------------+-----+
-             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
-             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
-             * +----------+-----------------+------------------------------+-----+
-             *
-             * <---------><----------------><------------------------------><---->
-             *     8               8                      5                   1
-             */
-            #define MAX_CONTEXT_SIZE 22
+/*
+ * +----------+-----------------+------------------------------+-----+
+ * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+ * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+ * +----------+-----------------+------------------------------+-----+
+ *
+ * <---------><----------------><------------------------------><---->
+ *     8               8                      5                   1
+ */
+            #define MAX_CONTEXT_SIZE    22
 
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-            /*
-             * +----------+-----------------+----------------------+-----+
-             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
-             * |          | PC, xPSR        | EXC_RETURN           |     |
-             * +----------+-----------------+----------------------+-----+
-             *
-             * <---------><----------------><----------------------><---->
-             *     8               8                  4              1
-             */
-            #define MAX_CONTEXT_SIZE 21
+/*
+ * +----------+-----------------+----------------------+-----+
+ * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+ * |          | PC, xPSR        | EXC_RETURN           |     |
+ * +----------+-----------------+----------------------+-----+
+ *
+ * <---------><----------------><----------------------><---->
+ *     8               8                  4              1
+ */
+            #define MAX_CONTEXT_SIZE    21
 
         #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
 
     #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-    /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
-    #define portSTACK_FRAME_HAS_PADDING_FLAG     ( 1UL << 0UL )
-    #define portTASK_IS_PRIVILEGED_FLAG          ( 1UL << 1UL )
+/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
+    #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
+    #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
     typedef struct MPU_SETTINGS
     {
@@ -364,49 +364,49 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-    /**
-     * @brief Allocate a secure context for the task.
-     *
-     * Tasks are not created with a secure context. Any task that is going to call
-     * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
-     * secure context before it calls any secure function.
-     *
-     * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
-     */
+/**
+ * @brief Allocate a secure context for the task.
+ *
+ * Tasks are not created with a secure context. Any task that is going to call
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+ * secure context before it calls any secure function.
+ *
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+ */
     #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
 
-    /**
-     * @brief Called when a task is deleted to delete the task's secure context,
-     * if it has one.
-     *
-     * @param[in] pxTCB The TCB of the task being deleted.
-     */
+/**
+ * @brief Called when a task is deleted to delete the task's secure context,
+ * if it has one.
+ *
+ * @param[in] pxTCB The TCB of the task being deleted.
+ */
     #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
 #endif /* configENABLE_TRUSTZONE */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Checks whether or not the processor is privileged.
-     *
-     * @return 1 if the processor is already privileged, 0 otherwise.
-     */
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
     #define portIS_PRIVILEGED()      xIsPrivileged()
 
-    /**
-     * @brief Raise an SVC request to raise privilege.
-     *
-     * The SVC handler checks that the SVC was raised from a system call and only
-     * then it raises the privilege. If this is called from any other place,
-     * the privilege is not raised.
-     */
+/**
+ * @brief Raise an SVC request to raise privilege.
+ *
+ * The SVC handler checks that the SVC was raised from a system call and only
+ * then it raises the privilege. If this is called from any other place,
+ * the privilege is not raised.
+ */
     #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
 
-    /**
-     * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
-     * register.
-     */
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
     #define portRESET_PRIVILEGE()    vResetPrivilege()
 #else
     #define portIS_PRIVILEGED()
@@ -419,12 +419,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     extern BaseType_t xPortIsTaskPrivileged( void );
 
-    /**
-     * @brief Checks whether or not the calling task is privileged.
-     *
-     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
-     */
-    #define portIS_TASK_PRIVILEGED()      xPortIsTaskPrivileged()
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
+    #define portIS_TASK_PRIVILEGED()    xPortIsTaskPrivileged()
 
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
@@ -439,9 +439,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * based on whether or not Mainline extension is implemented. */
 #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
     #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
-        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
     #else
-        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    0
     #endif
 #endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
 
@@ -450,9 +450,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  */
 #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
 
-    /**
-     * @brief Count the number of leading zeros in a 32-bit value.
-     */
+/**
+ * @brief Count the number of leading zeros in a 32-bit value.
+ */
     static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
     {
         uint32_t ulReturn;
@@ -462,7 +462,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         return ulReturn;
     }
 
-    /* Check the configuration. */
+/* Check the configuration. */
     #if ( configMAX_PRIORITIES > 32 )
         #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
     #endif
@@ -471,16 +471,16 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection.  Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
     #endif
 
-    /**
-     * @brief Store/clear the ready priorities in a bit map.
-     */
-    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+/**
+ * @brief Store/clear the ready priorities in a bit map.
+ */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )      ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )       ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 
-    /**
-     * @brief Get the priority of the highest-priority task that is ready to execute.
-     */
-    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )   uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+/**
+ * @brief Get the priority of the highest-priority task that is ready to execute.
+ */
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
 
 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM35P/secure/secure_context.c b/portable/GCC/ARM_CM35P/secure/secure_context.c
index 0730d574d..7d2171996 100644
--- a/portable/GCC/ARM_CM35P/secure/secure_context.c
+++ b/portable/GCC/ARM_CM35P/secure/secure_context.c
@@ -65,7 +65,7 @@
  * @brief Maximum number of secure contexts.
  */
 #ifndef secureconfigMAX_SECURE_CONTEXTS
-    #define secureconfigMAX_SECURE_CONTEXTS        8UL
+    #define secureconfigMAX_SECURE_CONTEXTS    8UL
 #endif
 /*-----------------------------------------------------------*/
 
@@ -164,15 +164,15 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
         }
 
         #if ( configENABLE_MPU == 1 )
-            {
-                /* Configure thread mode to use PSP and to be unprivileged. */
-                secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
-            }
+        {
+            /* Configure thread mode to use PSP and to be unprivileged. */
+            secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
+        }
         #else /* configENABLE_MPU */
-            {
-                /* Configure thread mode to use PSP and to be privileged. */
-                secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
-            }
+        {
+            /* Configure thread mode to use PSP and to be privileged. */
+            secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
+        }
         #endif /* configENABLE_MPU */
     }
 }
@@ -219,16 +219,16 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
             if( pucStackMemory != NULL )
             {
                 /* Since stack grows down, the starting point will be the last
-                 * location. Note that this location is next to the last
-                 * allocated byte for stack (excluding the space for seal values)
-                 * because the hardware decrements the stack pointer before
-                 * writing i.e. if stack pointer is 0x2, a push operation will
-                 * decrement the stack pointer to 0x1 and then write at 0x1. */
+                * location. Note that this location is next to the last
+                * allocated byte for stack (excluding the space for seal values)
+                * because the hardware decrements the stack pointer before
+                * writing i.e. if stack pointer is 0x2, a push operation will
+                * decrement the stack pointer to 0x1 and then write at 0x1. */
                 xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize;
 
                 /* Seal the created secure process stack. */
-                *( uint32_t * )( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE;
-                *( uint32_t * )( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE;
+                *( uint32_t * ) ( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE;
+                *( uint32_t * ) ( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE;
 
                 /* The stack cannot go beyond this location. This value is
                  * programmed in the PSPLIM register on context switch.*/
@@ -237,32 +237,32 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
                 xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle;
 
                 #if ( configENABLE_MPU == 1 )
+                {
+                    /* Store the correct CONTROL value for the task on the stack.
+                     * This value is programmed in the CONTROL register on
+                     * context switch. */
+                    pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart;
+                    pulCurrentStackPointer--;
+
+                    if( ulIsTaskPrivileged )
                     {
-                        /* Store the correct CONTROL value for the task on the stack.
-                         * This value is programmed in the CONTROL register on
-                         * context switch. */
-                        pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart;
-                        pulCurrentStackPointer--;
-
-                        if( ulIsTaskPrivileged )
-                        {
-                            *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
-                        }
-                        else
-                        {
-                            *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
-                        }
-
-                        /* Store the current stack pointer. This value is programmed in
-                         * the PSP register on context switch. */
-                        xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+                        *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
                     }
+                    else
+                    {
+                        *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
+                    }
+
+                    /* Store the current stack pointer. This value is programmed in
+                     * the PSP register on context switch. */
+                    xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+                }
                 #else /* configENABLE_MPU */
-                    {
-                        /* Current SP is set to the starting of the stack. This
-                         * value programmed in the PSP register on context switch. */
-                        xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart;
-                    }
+                {
+                    /* Current SP is set to the starting of the stack. This
+                     * value programmed in the PSP register on context switch. */
+                    xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart;
+                }
                 #endif /* configENABLE_MPU */
 
                 /* Ensure to never return 0 as a valid context handle. */
@@ -275,7 +275,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
 }
 /*-----------------------------------------------------------*/
 
-secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle,
+                                                              void * pvTaskHandle )
 {
     uint32_t ulIPSR, ulSecureContextIndex;
 
@@ -306,7 +307,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandl
 }
 /*-----------------------------------------------------------*/
 
-secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle,
+                                                              void * pvTaskHandle )
 {
     uint8_t * pucStackLimit;
     uint32_t ulSecureContextIndex;
@@ -328,7 +330,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandl
 }
 /*-----------------------------------------------------------*/
 
-secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle,
+                                                              void * pvTaskHandle )
 {
     uint8_t * pucStackLimit;
     uint32_t ulSecureContextIndex;
diff --git a/portable/GCC/ARM_CM35P/secure/secure_context.h b/portable/GCC/ARM_CM35P/secure/secure_context.h
index d0adbaf01..0bf776198 100644
--- a/portable/GCC/ARM_CM35P/secure/secure_context.h
+++ b/portable/GCC/ARM_CM35P/secure/secure_context.h
@@ -38,12 +38,12 @@
 /**
  * @brief PSP value when no secure context is loaded.
  */
-#define securecontextNO_STACK               0x0
+#define securecontextNO_STACK              0x0
 
 /**
  * @brief Invalid context ID.
  */
-#define securecontextINVALID_CONTEXT_ID     0UL
+#define securecontextINVALID_CONTEXT_ID    0UL
 /*-----------------------------------------------------------*/
 
 /**
@@ -108,7 +108,8 @@ void SecureContext_Init( void );
  * @param[in] xSecureContextHandle Context handle corresponding to the
  * context to be freed.
  */
-void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle,
+                                void * pvTaskHandle );
 
 /**
  * @brief Loads the given context.
@@ -119,7 +120,8 @@ void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void
  * @param[in] xSecureContextHandle Context handle corresponding to the context
  * to be loaded.
  */
-void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle,
+                                void * pvTaskHandle );
 
 /**
  * @brief Saves the given context.
@@ -130,6 +132,7 @@ void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void
  * @param[in] xSecureContextHandle Context handle corresponding to the context
  * to be saved.
  */
-void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle,
+                                void * pvTaskHandle );
 
 #endif /* __SECURE_CONTEXT_H__ */
diff --git a/portable/GCC/ARM_CM35P/secure/secure_heap.c b/portable/GCC/ARM_CM35P/secure/secure_heap.c
index f3b80df54..1ec3bdbdb 100644
--- a/portable/GCC/ARM_CM35P/secure/secure_heap.c
+++ b/portable/GCC/ARM_CM35P/secure/secure_heap.c
@@ -67,7 +67,7 @@
 #define secureheapSIZE_MAX              ( ~( ( size_t ) 0 ) )
 
 /* Check if adding a and b will result in overflow. */
-#define secureheapADD_WILL_OVERFLOW( a, b )         ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) )
+#define secureheapADD_WILL_OVERFLOW( a, b )    ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) )
 
 /* MSB of the xBlockSize member of an BlockLink_t structure is used to track
  * the allocation status of a block.  When MSB of the xBlockSize member of
@@ -397,17 +397,17 @@ void * pvPortMalloc( size_t xWantedSize )
     traceMALLOC( pvReturn, xWantedSize );
 
     #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
+    {
+        if( pvReturn == NULL )
         {
-            if( pvReturn == NULL )
-            {
-                extern void vApplicationMallocFailedHook( void );
-                vApplicationMallocFailedHook();
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
+            extern void vApplicationMallocFailedHook( void );
+            vApplicationMallocFailedHook();
         }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
     #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */
 
     secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );
diff --git a/portable/GCC/ARM_CM35P/secure/secure_init.c b/portable/GCC/ARM_CM35P/secure/secure_init.c
index dc19ebc7d..b89c5f644 100644
--- a/portable/GCC/ARM_CM35P/secure/secure_init.c
+++ b/portable/GCC/ARM_CM35P/secure/secure_init.c
@@ -93,7 +93,7 @@ secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )
          * permitted. CP11 should be programmed to the same value as CP10. */
         *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
 
-        /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
+        /* LSPENS = 0 ==> LSPEN is writable from non-secure state. This ensures
          * that we can enable/disable lazy stacking in port.c file. */
         *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK );
 
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.c
index 2d1218a95..d1fbdc0e5 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.c
@@ -44,2274 +44,2274 @@
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-#if ( INCLUDE_xTaskDelayUntil == 1 )
+    #if ( INCLUDE_xTaskDelayUntil == 1 )
 
-BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
-                                const TickType_t xTimeIncrement ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
+                                        const TickType_t xTimeIncrement ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
-                                const TickType_t xTimeIncrement ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskDelayUntilImpl                       \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskDelayUntil_Unpriv                        \n"
-        " MPU_xTaskDelayUntil_Priv:                             \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskDelayUntilImpl                         \n"
-        " MPU_xTaskDelayUntil_Unpriv:                           \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskDelayUntilImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
+                                        const TickType_t xTimeIncrement ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskDelayUntilImpl                       \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskDelayUntil_Unpriv                        \n"
+                " MPU_xTaskDelayUntil_Priv:                             \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskDelayUntilImpl                         \n"
+                " MPU_xTaskDelayUntil_Unpriv:                           \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskDelayUntilImpl                        \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */
+    #endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_xTaskAbortDelay == 1 )
+    #if ( INCLUDE_xTaskAbortDelay == 1 )
 
-BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskAbortDelayImpl                       \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskAbortDelay_Unpriv                        \n"
-        " MPU_xTaskAbortDelay_Priv:                             \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskAbortDelayImpl                         \n"
-        " MPU_xTaskAbortDelay_Unpriv:                           \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskAbortDelayImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskAbortDelayImpl                       \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskAbortDelay_Unpriv                        \n"
+                " MPU_xTaskAbortDelay_Priv:                             \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskAbortDelayImpl                         \n"
+                " MPU_xTaskAbortDelay_Unpriv:                           \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskAbortDelayImpl                        \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */
+    #endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_vTaskDelay == 1 )
+    #if ( INCLUDE_vTaskDelay == 1 )
 
-void MPU_vTaskDelay( const TickType_t xTicksToDelay ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskDelay( const TickType_t xTicksToDelay ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskDelayImpl                            \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskDelay_Unpriv                             \n"
-        " MPU_vTaskDelay_Priv:                                  \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskDelayImpl                              \n"
-        " MPU_vTaskDelay_Unpriv:                                \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskDelayImpl                             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskDelayImpl                            \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskDelay_Unpriv                             \n"
+                " MPU_vTaskDelay_Priv:                                  \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskDelayImpl                              \n"
+                " MPU_vTaskDelay_Unpriv:                                \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskDelayImpl                             \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_vTaskDelay == 1 ) */
+    #endif /* if ( INCLUDE_vTaskDelay == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_uxTaskPriorityGet == 1 )
+    #if ( INCLUDE_uxTaskPriorityGet == 1 )
 
-UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskPriorityGetImpl                     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTaskPriorityGet_Unpriv                      \n"
-        " MPU_uxTaskPriorityGet_Priv:                           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTaskPriorityGetImpl                       \n"
-        " MPU_uxTaskPriorityGet_Unpriv:                         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskPriorityGetImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskPriorityGetImpl                     \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTaskPriorityGet_Unpriv                      \n"
+                " MPU_uxTaskPriorityGet_Priv:                           \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTaskPriorityGetImpl                       \n"
+                " MPU_uxTaskPriorityGet_Unpriv:                         \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskPriorityGetImpl                      \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */
+    #endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_eTaskGetState == 1 )
+    #if ( INCLUDE_eTaskGetState == 1 )
 
-eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_eTaskGetStateImpl                         \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_eTaskGetState_Unpriv                          \n"
-        " MPU_eTaskGetState_Priv:                               \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_eTaskGetStateImpl                           \n"
-        " MPU_eTaskGetState_Unpriv:                             \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_eTaskGetStateImpl                          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_eTaskGetStateImpl                         \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_eTaskGetState_Unpriv                          \n"
+                " MPU_eTaskGetState_Priv:                               \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_eTaskGetStateImpl                           \n"
+                " MPU_eTaskGetState_Unpriv:                             \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_eTaskGetStateImpl                          \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_eTaskGetState == 1 ) */
+    #endif /* if ( INCLUDE_eTaskGetState == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-void MPU_vTaskGetInfo( TaskHandle_t xTask,
-                       TaskStatus_t * pxTaskStatus,
-                       BaseType_t xGetFreeStackSpace,
-                       eTaskState eState ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskGetInfo( TaskHandle_t xTask,
+                               TaskStatus_t * pxTaskStatus,
+                               BaseType_t xGetFreeStackSpace,
+                               eTaskState eState ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskGetInfo( TaskHandle_t xTask,
-                       TaskStatus_t * pxTaskStatus,
-                       BaseType_t xGetFreeStackSpace,
-                       eTaskState eState ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskGetInfoImpl                          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskGetInfo_Unpriv                           \n"
-        " MPU_vTaskGetInfo_Priv:                                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskGetInfoImpl                            \n"
-        " MPU_vTaskGetInfo_Unpriv:                              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskGetInfoImpl                           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskGetInfo( TaskHandle_t xTask,
+                               TaskStatus_t * pxTaskStatus,
+                               BaseType_t xGetFreeStackSpace,
+                               eTaskState eState ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskGetInfoImpl                          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskGetInfo_Unpriv                           \n"
+                " MPU_vTaskGetInfo_Priv:                                \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskGetInfoImpl                            \n"
+                " MPU_vTaskGetInfo_Unpriv:                              \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskGetInfoImpl                           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
+    #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
+    #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
 
-TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetIdleTaskHandleImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGetIdleTaskHandle_Unpriv                 \n"
-        " MPU_xTaskGetIdleTaskHandle_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGetIdleTaskHandleImpl                  \n"
-        " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetIdleTaskHandleImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetIdleTaskHandleImpl                \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGetIdleTaskHandle_Unpriv                 \n"
+                " MPU_xTaskGetIdleTaskHandle_Priv:                      \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGetIdleTaskHandleImpl                  \n"
+                " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetIdleTaskHandleImpl                 \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */
+    #endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_vTaskSuspend == 1 )
+    #if ( INCLUDE_vTaskSuspend == 1 )
 
-void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSuspendImpl                          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskSuspend_Unpriv                           \n"
-        " MPU_vTaskSuspend_Priv:                                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskSuspendImpl                            \n"
-        " MPU_vTaskSuspend_Unpriv:                              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSuspendImpl                           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskSuspendImpl                          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskSuspend_Unpriv                           \n"
+                " MPU_vTaskSuspend_Priv:                                \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskSuspendImpl                            \n"
+                " MPU_vTaskSuspend_Unpriv:                              \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskSuspendImpl                           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
+    #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_vTaskSuspend == 1 )
+    #if ( INCLUDE_vTaskSuspend == 1 )
 
-void MPU_vTaskResume( TaskHandle_t xTaskToResume ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskResume( TaskHandle_t xTaskToResume ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskResumeImpl                           \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskResume_Unpriv                            \n"
-        " MPU_vTaskResume_Priv:                                 \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskResumeImpl                             \n"
-        " MPU_vTaskResume_Unpriv:                               \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskResumeImpl                            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskResumeImpl                           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskResume_Unpriv                            \n"
+                " MPU_vTaskResume_Priv:                                 \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskResumeImpl                             \n"
+                " MPU_vTaskResume_Unpriv:                               \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskResumeImpl                            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
+    #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
 /*-----------------------------------------------------------*/
 
-TickType_t MPU_xTaskGetTickCount( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    TickType_t MPU_xTaskGetTickCount( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TickType_t MPU_xTaskGetTickCount( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetTickCountImpl                     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGetTickCount_Unpriv                      \n"
-        " MPU_xTaskGetTickCount_Priv:                           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGetTickCountImpl                       \n"
-        " MPU_xTaskGetTickCount_Unpriv:                         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetTickCountImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    TickType_t MPU_xTaskGetTickCount( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xTaskGetTickCountImpl                     \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xTaskGetTickCount_Unpriv                      \n"
+            " MPU_xTaskGetTickCount_Priv:                           \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xTaskGetTickCountImpl                       \n"
+            " MPU_xTaskGetTickCount_Unpriv:                         \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xTaskGetTickCountImpl                      \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetNumberOfTasksImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTaskGetNumberOfTasks_Unpriv                 \n"
-        " MPU_uxTaskGetNumberOfTasks_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTaskGetNumberOfTasksImpl                  \n"
-        " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetNumberOfTasksImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_uxTaskGetNumberOfTasksImpl                \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_uxTaskGetNumberOfTasks_Unpriv                 \n"
+            " MPU_uxTaskGetNumberOfTasks_Priv:                      \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_uxTaskGetNumberOfTasksImpl                  \n"
+            " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_uxTaskGetNumberOfTasksImpl                 \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configGENERATE_RUN_TIME_STATS == 1 )
+    #if ( configGENERATE_RUN_TIME_STATS == 1 )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetRunTimeCounterImpl               \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGetRunTimeCounter_Unpriv                \n"
-        " MPU_ulTaskGetRunTimeCounter_Priv:                     \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGetRunTimeCounterImpl                 \n"
-        " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetRunTimeCounterImpl                \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetRunTimeCounterImpl               \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGetRunTimeCounter_Unpriv                \n"
+                " MPU_ulTaskGetRunTimeCounter_Priv:                     \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGetRunTimeCounterImpl                 \n"
+                " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetRunTimeCounterImpl                \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configGENERATE_RUN_TIME_STATS == 1 )
+    #if ( configGENERATE_RUN_TIME_STATS == 1 )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetRunTimePercentImpl               \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGetRunTimePercent_Unpriv                \n"
-        " MPU_ulTaskGetRunTimePercent_Priv:                     \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGetRunTimePercentImpl                 \n"
-        " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetRunTimePercentImpl                \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetRunTimePercentImpl               \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGetRunTimePercent_Unpriv                \n"
+                " MPU_ulTaskGetRunTimePercent_Priv:                     \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGetRunTimePercentImpl                 \n"
+                " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetRunTimePercentImpl                \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+    #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetIdleRunTimePercentImpl           \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv            \n"
-        " MPU_ulTaskGetIdleRunTimePercent_Priv:                 \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGetIdleRunTimePercentImpl             \n"
-        " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetIdleRunTimePercentImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetIdleRunTimePercentImpl           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv            \n"
+                " MPU_ulTaskGetIdleRunTimePercent_Priv:                 \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGetIdleRunTimePercentImpl             \n"
+                " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetIdleRunTimePercentImpl            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+    #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetIdleRunTimeCounterImpl           \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv            \n"
-        " MPU_ulTaskGetIdleRunTimeCounter_Priv:                 \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGetIdleRunTimeCounterImpl             \n"
-        " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetIdleRunTimeCounterImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetIdleRunTimeCounterImpl           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv            \n"
+                " MPU_ulTaskGetIdleRunTimeCounter_Priv:                 \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGetIdleRunTimeCounterImpl             \n"
+                " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetIdleRunTimeCounterImpl            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+    #if ( configUSE_APPLICATION_TASK_TAG == 1 )
 
-void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
-                                     TaskHookFunction_t pxHookFunction ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
+                                             TaskHookFunction_t pxHookFunction ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
-                                     TaskHookFunction_t pxHookFunction ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSetApplicationTaskTagImpl            \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskSetApplicationTaskTag_Unpriv             \n"
-        " MPU_vTaskSetApplicationTaskTag_Priv:                  \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskSetApplicationTaskTagImpl              \n"
-        " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSetApplicationTaskTagImpl             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
+                                             TaskHookFunction_t pxHookFunction ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskSetApplicationTaskTagImpl            \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskSetApplicationTaskTag_Unpriv             \n"
+                " MPU_vTaskSetApplicationTaskTag_Priv:                  \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskSetApplicationTaskTagImpl              \n"
+                " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskSetApplicationTaskTagImpl             \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
+    #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+    #if ( configUSE_APPLICATION_TASK_TAG == 1 )
 
-TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetApplicationTaskTagImpl            \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGetApplicationTaskTag_Unpriv             \n"
-        " MPU_xTaskGetApplicationTaskTag_Priv:                  \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGetApplicationTaskTagImpl              \n"
-        " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetApplicationTaskTagImpl             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetApplicationTaskTagImpl            \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGetApplicationTaskTag_Unpriv             \n"
+                " MPU_xTaskGetApplicationTaskTag_Priv:                  \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGetApplicationTaskTagImpl              \n"
+                " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetApplicationTaskTagImpl             \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
+    #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+    #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
 
-void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
-                                            BaseType_t xIndex,
-                                            void * pvValue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
+                                                    BaseType_t xIndex,
+                                                    void * pvValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
-                                            BaseType_t xIndex,
-                                            void * pvValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSetThreadLocalStoragePointerImpl     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv      \n"
-        " MPU_vTaskSetThreadLocalStoragePointer_Priv:           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskSetThreadLocalStoragePointerImpl       \n"
-        " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSetThreadLocalStoragePointerImpl      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
+                                                    BaseType_t xIndex,
+                                                    void * pvValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskSetThreadLocalStoragePointerImpl     \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv      \n"
+                " MPU_vTaskSetThreadLocalStoragePointer_Priv:           \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskSetThreadLocalStoragePointerImpl       \n"
+                " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskSetThreadLocalStoragePointerImpl      \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
+    #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+    #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
 
-void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
-                                               BaseType_t xIndex ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
+                                                       BaseType_t xIndex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
-                                               BaseType_t xIndex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pvTaskGetThreadLocalStoragePointerImpl    \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv     \n"
-        " MPU_pvTaskGetThreadLocalStoragePointer_Priv:          \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_pvTaskGetThreadLocalStoragePointerImpl      \n"
-        " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pvTaskGetThreadLocalStoragePointerImpl     \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
+                                                       BaseType_t xIndex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pvTaskGetThreadLocalStoragePointerImpl    \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv     \n"
+                " MPU_pvTaskGetThreadLocalStoragePointer_Priv:          \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_pvTaskGetThreadLocalStoragePointerImpl      \n"
+                " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pvTaskGetThreadLocalStoragePointerImpl     \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
+    #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
-                                      const UBaseType_t uxArraySize,
-                                      configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
+                                              const UBaseType_t uxArraySize,
+                                              configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
-                                      const UBaseType_t uxArraySize,
-                                      configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetSystemStateImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTaskGetSystemState_Unpriv                   \n"
-        " MPU_uxTaskGetSystemState_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTaskGetSystemStateImpl                    \n"
-        " MPU_uxTaskGetSystemState_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetSystemStateImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
+                                              const UBaseType_t uxArraySize,
+                                              configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskGetSystemStateImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTaskGetSystemState_Unpriv                   \n"
+                " MPU_uxTaskGetSystemState_Priv:                        \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTaskGetSystemStateImpl                    \n"
+                " MPU_uxTaskGetSystemState_Unpriv:                      \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskGetSystemStateImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
+    #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
+    #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
 
-UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetStackHighWaterMarkImpl           \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTaskGetStackHighWaterMark_Unpriv            \n"
-        " MPU_uxTaskGetStackHighWaterMark_Priv:                 \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTaskGetStackHighWaterMarkImpl             \n"
-        " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetStackHighWaterMarkImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskGetStackHighWaterMarkImpl           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTaskGetStackHighWaterMark_Unpriv            \n"
+                " MPU_uxTaskGetStackHighWaterMark_Priv:                 \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTaskGetStackHighWaterMarkImpl             \n"
+                " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskGetStackHighWaterMarkImpl            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */
+    #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
+    #if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
 
-configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetStackHighWaterMark2Impl          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv           \n"
-        " MPU_uxTaskGetStackHighWaterMark2_Priv:                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTaskGetStackHighWaterMark2Impl            \n"
-        " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetStackHighWaterMark2Impl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskGetStackHighWaterMark2Impl          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv           \n"
+                " MPU_uxTaskGetStackHighWaterMark2_Priv:                \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTaskGetStackHighWaterMark2Impl            \n"
+                " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskGetStackHighWaterMark2Impl           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */
+    #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
+    #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
 
-TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetCurrentTaskHandleImpl             \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGetCurrentTaskHandle_Unpriv              \n"
-        " MPU_xTaskGetCurrentTaskHandle_Priv:                   \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGetCurrentTaskHandleImpl               \n"
-        " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetCurrentTaskHandleImpl              \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetCurrentTaskHandleImpl             \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGetCurrentTaskHandle_Unpriv              \n"
+                " MPU_xTaskGetCurrentTaskHandle_Priv:                   \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGetCurrentTaskHandleImpl               \n"
+                " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetCurrentTaskHandleImpl              \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
+    #endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_xTaskGetSchedulerState == 1 )
+    #if ( INCLUDE_xTaskGetSchedulerState == 1 )
 
-BaseType_t MPU_xTaskGetSchedulerState( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGetSchedulerState( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGetSchedulerState( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetSchedulerStateImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGetSchedulerState_Unpriv                 \n"
-        " MPU_xTaskGetSchedulerState_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGetSchedulerStateImpl                  \n"
-        " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetSchedulerStateImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGetSchedulerState( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetSchedulerStateImpl                \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGetSchedulerState_Unpriv                 \n"
+                " MPU_xTaskGetSchedulerState_Priv:                      \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGetSchedulerStateImpl                  \n"
+                " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetSchedulerStateImpl                 \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */
+    #endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */
 /*-----------------------------------------------------------*/
 
-void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSetTimeOutStateImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskSetTimeOutState_Unpriv                   \n"
-        " MPU_vTaskSetTimeOutState_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskSetTimeOutStateImpl                    \n"
-        " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSetTimeOutStateImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_vTaskSetTimeOutStateImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_vTaskSetTimeOutState_Unpriv                   \n"
+            " MPU_vTaskSetTimeOutState_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_vTaskSetTimeOutStateImpl                    \n"
+            " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_vTaskSetTimeOutStateImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
-                                     TickType_t * const pxTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
+                                         TickType_t * const pxTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
-                                     TickType_t * const pxTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskCheckForTimeOutImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskCheckForTimeOut_Unpriv                   \n"
-        " MPU_xTaskCheckForTimeOut_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskCheckForTimeOutImpl                    \n"
-        " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskCheckForTimeOutImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
+                                         TickType_t * const pxTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xTaskCheckForTimeOutImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xTaskCheckForTimeOut_Unpriv                   \n"
+            " MPU_xTaskCheckForTimeOut_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xTaskCheckForTimeOutImpl                    \n"
+            " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xTaskCheckForTimeOutImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                   UBaseType_t uxIndexToNotify,
-                                   uint32_t ulValue,
-                                   eNotifyAction eAction,
-                                   uint32_t * pulPreviousNotificationValue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
+                                           UBaseType_t uxIndexToNotify,
+                                           uint32_t ulValue,
+                                           eNotifyAction eAction,
+                                           uint32_t * pulPreviousNotificationValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                   UBaseType_t uxIndexToNotify,
-                                   uint32_t ulValue,
-                                   eNotifyAction eAction,
-                                   uint32_t * pulPreviousNotificationValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGenericNotifyImpl                    \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGenericNotify_Unpriv                     \n"
-        " MPU_xTaskGenericNotify_Priv:                          \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGenericNotifyImpl                      \n"
-        " MPU_xTaskGenericNotify_Unpriv:                        \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGenericNotifyImpl                     \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
+                                           UBaseType_t uxIndexToNotify,
+                                           uint32_t ulValue,
+                                           eNotifyAction eAction,
+                                           uint32_t * pulPreviousNotificationValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGenericNotifyImpl                    \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGenericNotify_Unpriv                     \n"
+                " MPU_xTaskGenericNotify_Priv:                          \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGenericNotifyImpl                      \n"
+                " MPU_xTaskGenericNotify_Unpriv:                        \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGenericNotifyImpl                     \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                       uint32_t ulBitsToClearOnEntry,
-                                       uint32_t ulBitsToClearOnExit,
-                                       uint32_t * pulNotificationValue,
-                                       TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
+                                               uint32_t ulBitsToClearOnEntry,
+                                               uint32_t ulBitsToClearOnExit,
+                                               uint32_t * pulNotificationValue,
+                                               TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                       uint32_t ulBitsToClearOnEntry,
-                                       uint32_t ulBitsToClearOnExit,
-                                       uint32_t * pulNotificationValue,
-                                       TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGenericNotifyWaitImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGenericNotifyWait_Unpriv                 \n"
-        " MPU_xTaskGenericNotifyWait_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGenericNotifyWaitImpl                  \n"
-        " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGenericNotifyWaitImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
+                                               uint32_t ulBitsToClearOnEntry,
+                                               uint32_t ulBitsToClearOnExit,
+                                               uint32_t * pulNotificationValue,
+                                               TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGenericNotifyWaitImpl                \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGenericNotifyWait_Unpriv                 \n"
+                " MPU_xTaskGenericNotifyWait_Priv:                      \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGenericNotifyWaitImpl                  \n"
+                " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGenericNotifyWaitImpl                 \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
-                                      BaseType_t xClearCountOnExit,
-                                      TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
+                                              BaseType_t xClearCountOnExit,
+                                              TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
-                                      BaseType_t xClearCountOnExit,
-                                      TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGenericNotifyTakeImpl               \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGenericNotifyTake_Unpriv                \n"
-        " MPU_ulTaskGenericNotifyTake_Priv:                     \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGenericNotifyTakeImpl                 \n"
-        " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGenericNotifyTakeImpl                \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
+                                              BaseType_t xClearCountOnExit,
+                                              TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGenericNotifyTakeImpl               \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGenericNotifyTake_Unpriv                \n"
+                " MPU_ulTaskGenericNotifyTake_Priv:                     \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGenericNotifyTakeImpl                 \n"
+                " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGenericNotifyTakeImpl                \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
-                                             UBaseType_t uxIndexToClear ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
+                                                     UBaseType_t uxIndexToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
-                                             UBaseType_t uxIndexToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGenericNotifyStateClearImpl          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGenericNotifyStateClear_Unpriv           \n"
-        " MPU_xTaskGenericNotifyStateClear_Priv:                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGenericNotifyStateClearImpl            \n"
-        " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGenericNotifyStateClearImpl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
+                                                     UBaseType_t uxIndexToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGenericNotifyStateClearImpl          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGenericNotifyStateClear_Unpriv           \n"
+                " MPU_xTaskGenericNotifyStateClear_Priv:                \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGenericNotifyStateClearImpl            \n"
+                " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGenericNotifyStateClearImpl           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
-                                            UBaseType_t uxIndexToClear,
-                                            uint32_t ulBitsToClear ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
+                                                    UBaseType_t uxIndexToClear,
+                                                    uint32_t ulBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
-                                            UBaseType_t uxIndexToClear,
-                                            uint32_t ulBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGenericNotifyValueClearImpl         \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGenericNotifyValueClear_Unpriv          \n"
-        " MPU_ulTaskGenericNotifyValueClear_Priv:               \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGenericNotifyValueClearImpl           \n"
-        " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGenericNotifyValueClearImpl          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
+                                                    UBaseType_t uxIndexToClear,
+                                                    uint32_t ulBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGenericNotifyValueClearImpl         \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGenericNotifyValueClear_Unpriv          \n"
+                " MPU_ulTaskGenericNotifyValueClear_Priv:               \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGenericNotifyValueClearImpl           \n"
+                " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGenericNotifyValueClearImpl          \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
-                                  const void * const pvItemToQueue,
-                                  TickType_t xTicksToWait,
-                                  const BaseType_t xCopyPosition ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
+                                      const void * const pvItemToQueue,
+                                      TickType_t xTicksToWait,
+                                      const BaseType_t xCopyPosition ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
-                                  const void * const pvItemToQueue,
-                                  TickType_t xTicksToWait,
-                                  const BaseType_t xCopyPosition ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueGenericSendImpl                     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueGenericSend_Unpriv                      \n"
-        " MPU_xQueueGenericSend_Priv:                           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueGenericSendImpl                       \n"
-        " MPU_xQueueGenericSend_Unpriv:                         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueGenericSendImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
+                                      const void * const pvItemToQueue,
+                                      TickType_t xTicksToWait,
+                                      const BaseType_t xCopyPosition ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueueGenericSendImpl                     \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xQueueGenericSend_Unpriv                      \n"
+            " MPU_xQueueGenericSend_Priv:                           \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xQueueGenericSendImpl                       \n"
+            " MPU_xQueueGenericSend_Unpriv:                         \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueueGenericSendImpl                      \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxQueueMessagesWaitingImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxQueueMessagesWaiting_Unpriv                 \n"
-        " MPU_uxQueueMessagesWaiting_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxQueueMessagesWaitingImpl                  \n"
-        " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxQueueMessagesWaitingImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_uxQueueMessagesWaitingImpl                \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_uxQueueMessagesWaiting_Unpriv                 \n"
+            " MPU_uxQueueMessagesWaiting_Priv:                      \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_uxQueueMessagesWaitingImpl                  \n"
+            " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_uxQueueMessagesWaitingImpl                 \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxQueueSpacesAvailableImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxQueueSpacesAvailable_Unpriv                 \n"
-        " MPU_uxQueueSpacesAvailable_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxQueueSpacesAvailableImpl                  \n"
-        " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxQueueSpacesAvailableImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_uxQueueSpacesAvailableImpl                \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_uxQueueSpacesAvailable_Unpriv                 \n"
+            " MPU_uxQueueSpacesAvailable_Priv:                      \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_uxQueueSpacesAvailableImpl                  \n"
+            " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_uxQueueSpacesAvailableImpl                 \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
-                              void * const pvBuffer,
-                              TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
+                                  void * const pvBuffer,
+                                  TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
-                              void * const pvBuffer,
-                              TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueReceiveImpl                         \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueReceive_Unpriv                          \n"
-        " MPU_xQueueReceive_Priv:                               \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueReceiveImpl                           \n"
-        " MPU_xQueueReceive_Unpriv:                             \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueReceiveImpl                          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
+                                  void * const pvBuffer,
+                                  TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueueReceiveImpl                         \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xQueueReceive_Unpriv                          \n"
+            " MPU_xQueueReceive_Priv:                               \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xQueueReceiveImpl                           \n"
+            " MPU_xQueueReceive_Unpriv:                             \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueueReceiveImpl                          \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
-                           void * const pvBuffer,
-                           TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
+                               void * const pvBuffer,
+                               TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
-                           void * const pvBuffer,
-                           TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueuePeekImpl                            \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueuePeek_Unpriv                             \n"
-        " MPU_xQueuePeek_Priv:                                  \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueuePeekImpl                              \n"
-        " MPU_xQueuePeek_Unpriv:                                \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueuePeekImpl                             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
+                               void * const pvBuffer,
+                               TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueuePeekImpl                            \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xQueuePeek_Unpriv                             \n"
+            " MPU_xQueuePeek_Priv:                                  \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xQueuePeekImpl                              \n"
+            " MPU_xQueuePeek_Unpriv:                                \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueuePeekImpl                             \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
-                                    TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
+                                        TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
-                                    TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueSemaphoreTakeImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueSemaphoreTake_Unpriv                    \n"
-        " MPU_xQueueSemaphoreTake_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueSemaphoreTakeImpl                     \n"
-        " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueSemaphoreTakeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
+                                        TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueueSemaphoreTakeImpl                   \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xQueueSemaphoreTake_Unpriv                    \n"
+            " MPU_xQueueSemaphoreTake_Priv:                         \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xQueueSemaphoreTakeImpl                     \n"
+            " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueueSemaphoreTakeImpl                    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+    #if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
 
-TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueGetMutexHolderImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueGetMutexHolder_Unpriv                   \n"
-        " MPU_xQueueGetMutexHolder_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueGetMutexHolderImpl                    \n"
-        " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueGetMutexHolderImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueGetMutexHolderImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueGetMutexHolder_Unpriv                   \n"
+                " MPU_xQueueGetMutexHolder_Priv:                        \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueGetMutexHolderImpl                    \n"
+                " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueGetMutexHolderImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */
+    #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+    #if ( configUSE_RECURSIVE_MUTEXES == 1 )
 
-BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
-                                         TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+                                                 TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+        BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+                                                 TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueTakeMutexRecursiveImpl              \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueTakeMutexRecursive_Unpriv               \n"
+                " MPU_xQueueTakeMutexRecursive_Priv:                    \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueTakeMutexRecursiveImpl                \n"
+                " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueTakeMutexRecursiveImpl               \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_RECURSIVE_MUTEXES == 1 )
+
+        BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueGiveMutexRecursiveImpl              \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueGiveMutexRecursive_Unpriv               \n"
+                " MPU_xQueueGiveMutexRecursive_Priv:                    \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueGiveMutexRecursiveImpl                \n"
+                " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueGiveMutexRecursiveImpl               \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_QUEUE_SETS == 1 )
+
+        QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
+                                                        const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
+                                                        const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueSelectFromSetImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueSelectFromSet_Unpriv                    \n"
+                " MPU_xQueueSelectFromSet_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueSelectFromSetImpl                     \n"
+                " MPU_xQueueSelectFromSet_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueSelectFromSetImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_QUEUE_SETS == 1 )
+
+        BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                                       QueueSetHandle_t xQueueSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                                       QueueSetHandle_t xQueueSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueAddToSetImpl                        \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueAddToSet_Unpriv                         \n"
+                " MPU_xQueueAddToSet_Priv:                              \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueAddToSetImpl                          \n"
+                " MPU_xQueueAddToSet_Unpriv:                            \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueAddToSetImpl                         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+        void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
+                                      const char * pcName ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
+                                      const char * pcName ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vQueueAddToRegistryImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vQueueAddToRegistry_Unpriv                    \n"
+                " MPU_vQueueAddToRegistry_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vQueueAddToRegistryImpl                     \n"
+                " MPU_vQueueAddToRegistry_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vQueueAddToRegistryImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+        void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vQueueUnregisterQueueImpl                 \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vQueueUnregisterQueue_Unpriv                  \n"
+                " MPU_vQueueUnregisterQueue_Priv:                       \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vQueueUnregisterQueueImpl                   \n"
+                " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vQueueUnregisterQueueImpl                  \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+        const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pcQueueGetNameImpl                        \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_pcQueueGetName_Unpriv                         \n"
+                " MPU_pcQueueGetName_Priv:                              \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_pcQueueGetNameImpl                          \n"
+                " MPU_pcQueueGetName_Unpriv:                            \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pcQueueGetNameImpl                         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pvTimerGetTimerIDImpl                     \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_pvTimerGetTimerID_Unpriv                      \n"
+                " MPU_pvTimerGetTimerID_Priv:                           \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_pvTimerGetTimerIDImpl                       \n"
+                " MPU_pvTimerGetTimerID_Unpriv:                         \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pvTimerGetTimerIDImpl                      \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
+                                   void * pvNewID ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
+                                   void * pvNewID ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTimerSetTimerIDImpl                      \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTimerSetTimerID_Unpriv                       \n"
+                " MPU_vTimerSetTimerID_Priv:                            \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTimerSetTimerIDImpl                        \n"
+                " MPU_vTimerSetTimerID_Unpriv:                          \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTimerSetTimerIDImpl                       \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerIsTimerActiveImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerIsTimerActive_Unpriv                    \n"
+                " MPU_xTimerIsTimerActive_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerIsTimerActiveImpl                     \n"
+                " MPU_xTimerIsTimerActive_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerIsTimerActiveImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetTimerDaemonTaskHandleImpl        \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv         \n"
+                " MPU_xTimerGetTimerDaemonTaskHandle_Priv:              \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerGetTimerDaemonTaskHandleImpl          \n"
+                " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetTimerDaemonTaskHandleImpl         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                                     const BaseType_t xCommandID,
+                                                     const TickType_t xOptionalValue,
+                                                     BaseType_t * const pxHigherPriorityTaskWoken,
+                                                     const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                                     const BaseType_t xCommandID,
+                                                     const TickType_t xOptionalValue,
+                                                     BaseType_t * const pxHigherPriorityTaskWoken,
+                                                     const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                               \n"
+                " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
+                "                                                               \n"
+                " push {r0}                                                     \n"
+                " mrs r0, control                                               \n"
+                " tst r0, #1                                                    \n"
+                " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
+                " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
+                "     pop {r0}                                                  \n"
+                "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
+                " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
+                "     pop {r0}                                                  \n"
+                "     svc %0                                                    \n"
+                "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
+                "     svc %1                                                    \n"
+                "     bx lr                                                     \n"
+                "                                                               \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pcTimerGetNameImpl                        \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_pcTimerGetName_Unpriv                         \n"
+                " MPU_pcTimerGetName_Priv:                              \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_pcTimerGetNameImpl                          \n"
+                " MPU_pcTimerGetName_Unpriv:                            \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pcTimerGetNameImpl                         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
+                                      const BaseType_t uxAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
+                                      const BaseType_t uxAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTimerSetReloadModeImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTimerSetReloadMode_Unpriv                    \n"
+                " MPU_vTimerSetReloadMode_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTimerSetReloadModeImpl                     \n"
+                " MPU_vTimerSetReloadMode_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTimerSetReloadModeImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetReloadModeImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerGetReloadMode_Unpriv                    \n"
+                " MPU_xTimerGetReloadMode_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerGetReloadModeImpl                     \n"
+                " MPU_xTimerGetReloadMode_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetReloadModeImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTimerGetReloadModeImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTimerGetReloadMode_Unpriv                   \n"
+                " MPU_uxTimerGetReloadMode_Priv:                        \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTimerGetReloadModeImpl                    \n"
+                " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTimerGetReloadModeImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetPeriodImpl                       \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerGetPeriod_Unpriv                        \n"
+                " MPU_xTimerGetPeriod_Priv:                             \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerGetPeriodImpl                         \n"
+                " MPU_xTimerGetPeriod_Unpriv:                           \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetPeriodImpl                        \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetExpiryTimeImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerGetExpiryTime_Unpriv                    \n"
+                " MPU_xTimerGetExpiryTime_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerGetExpiryTimeImpl                     \n"
+                " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetExpiryTimeImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         const BaseType_t xClearOnExit,
+                                         const BaseType_t xWaitForAllBits,
+                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         const BaseType_t xClearOnExit,
+                                         const BaseType_t xWaitForAllBits,
                                          TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueTakeMutexRecursiveImpl              \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueTakeMutexRecursive_Unpriv               \n"
-        " MPU_xQueueTakeMutexRecursive_Priv:                    \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueTakeMutexRecursiveImpl                \n"
-        " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueTakeMutexRecursiveImpl               \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupWaitBitsImpl                   \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
+            " MPU_xEventGroupWaitBits_Priv:                         \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xEventGroupWaitBitsImpl                     \n"
+            " MPU_xEventGroupWaitBits_Unpriv:                       \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupWaitBitsImpl                    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                          const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueGiveMutexRecursiveImpl              \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueGiveMutexRecursive_Unpriv               \n"
-        " MPU_xQueueGiveMutexRecursive_Priv:                    \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueGiveMutexRecursiveImpl                \n"
-        " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueGiveMutexRecursiveImpl               \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                          const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupClearBitsImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xEventGroupClearBits_Unpriv                   \n"
+            " MPU_xEventGroupClearBits_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xEventGroupClearBitsImpl                    \n"
+            " MPU_xEventGroupClearBits_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupClearBitsImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_QUEUE_SETS == 1 )
+    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                        const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
-                                                const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
-                                                const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueSelectFromSetImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueSelectFromSet_Unpriv                    \n"
-        " MPU_xQueueSelectFromSet_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueSelectFromSetImpl                     \n"
-        " MPU_xQueueSelectFromSet_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueSelectFromSetImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                        const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupSetBitsImpl                    \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xEventGroupSetBits_Unpriv                     \n"
+            " MPU_xEventGroupSetBits_Priv:                          \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xEventGroupSetBitsImpl                      \n"
+            " MPU_xEventGroupSetBits_Unpriv:                        \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupSetBitsImpl                     \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_QUEUE_SETS == 1 )
-
-BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
-                               QueueSetHandle_t xQueueSet ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
-                               QueueSetHandle_t xQueueSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueAddToSetImpl                        \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueAddToSet_Unpriv                         \n"
-        " MPU_xQueueAddToSet_Priv:                              \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueAddToSetImpl                          \n"
-        " MPU_xQueueAddToSet_Unpriv:                            \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueAddToSetImpl                         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_QUEUE_SETS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
-                              const char * pcName ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
-                              const char * pcName ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vQueueAddToRegistryImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vQueueAddToRegistry_Unpriv                    \n"
-        " MPU_vQueueAddToRegistry_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vQueueAddToRegistryImpl                     \n"
-        " MPU_vQueueAddToRegistry_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vQueueAddToRegistryImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vQueueUnregisterQueueImpl                 \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vQueueUnregisterQueue_Unpriv                  \n"
-        " MPU_vQueueUnregisterQueue_Priv:                       \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vQueueUnregisterQueueImpl                   \n"
-        " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vQueueUnregisterQueueImpl                  \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pcQueueGetNameImpl                        \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_pcQueueGetName_Unpriv                         \n"
-        " MPU_pcQueueGetName_Priv:                              \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_pcQueueGetNameImpl                          \n"
-        " MPU_pcQueueGetName_Unpriv:                            \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pcQueueGetNameImpl                         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pvTimerGetTimerIDImpl                     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_pvTimerGetTimerID_Unpriv                      \n"
-        " MPU_pvTimerGetTimerID_Priv:                           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_pvTimerGetTimerIDImpl                       \n"
-        " MPU_pvTimerGetTimerID_Unpriv:                         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pvTimerGetTimerIDImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
-                           void * pvNewID ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
-                           void * pvNewID ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTimerSetTimerIDImpl                      \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTimerSetTimerID_Unpriv                       \n"
-        " MPU_vTimerSetTimerID_Priv:                            \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTimerSetTimerIDImpl                        \n"
-        " MPU_vTimerSetTimerID_Unpriv:                          \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTimerSetTimerIDImpl                       \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerIsTimerActiveImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTimerIsTimerActive_Unpriv                    \n"
-        " MPU_xTimerIsTimerActive_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerIsTimerActiveImpl                     \n"
-        " MPU_xTimerIsTimerActive_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerIsTimerActiveImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetTimerDaemonTaskHandleImpl        \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv         \n"
-        " MPU_xTimerGetTimerDaemonTaskHandle_Priv:              \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerGetTimerDaemonTaskHandleImpl          \n"
-        " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetTimerDaemonTaskHandleImpl         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                             const BaseType_t xCommandID,
-                                             const TickType_t xOptionalValue,
-                                             BaseType_t * const pxHigherPriorityTaskWoken,
-                                             const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                             const BaseType_t xCommandID,
-                                             const TickType_t xOptionalValue,
-                                             BaseType_t * const pxHigherPriorityTaskWoken,
-                                             const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                               \n"
-        " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
-        "                                                               \n"
-        " push {r0}                                                     \n"
-        " mrs r0, control                                               \n"
-        " tst r0, #1                                                    \n"
-        " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
-        " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
-        "     pop {r0}                                                  \n"
-        "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
-        " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
-        "     pop {r0}                                                  \n"
-        "     svc %0                                                    \n"
-        "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
-        "     svc %1                                                    \n"
-        "     bx lr                                                     \n"
-        "                                                               \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pcTimerGetNameImpl                        \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_pcTimerGetName_Unpriv                         \n"
-        " MPU_pcTimerGetName_Priv:                              \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_pcTimerGetNameImpl                          \n"
-        " MPU_pcTimerGetName_Unpriv:                            \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pcTimerGetNameImpl                         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                              const BaseType_t uxAutoReload ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                              const BaseType_t uxAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTimerSetReloadModeImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTimerSetReloadMode_Unpriv                    \n"
-        " MPU_vTimerSetReloadMode_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTimerSetReloadModeImpl                     \n"
-        " MPU_vTimerSetReloadMode_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTimerSetReloadModeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetReloadModeImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTimerGetReloadMode_Unpriv                    \n"
-        " MPU_xTimerGetReloadMode_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerGetReloadModeImpl                     \n"
-        " MPU_xTimerGetReloadMode_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetReloadModeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTimerGetReloadModeImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTimerGetReloadMode_Unpriv                   \n"
-        " MPU_uxTimerGetReloadMode_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTimerGetReloadModeImpl                    \n"
-        " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTimerGetReloadModeImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetPeriodImpl                       \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTimerGetPeriod_Unpriv                        \n"
-        " MPU_xTimerGetPeriod_Priv:                             \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerGetPeriodImpl                         \n"
-        " MPU_xTimerGetPeriod_Unpriv:                           \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetPeriodImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetExpiryTimeImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTimerGetExpiryTime_Unpriv                    \n"
-        " MPU_xTimerGetExpiryTime_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerGetExpiryTimeImpl                     \n"
-        " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetExpiryTimeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                     const EventBits_t uxBitsToSet,
                                      const EventBits_t uxBitsToWaitFor,
-                                     const BaseType_t xClearOnExit,
-                                     const BaseType_t xWaitForAllBits,
-                                     TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                     const EventBits_t uxBitsToSet,
                                      const EventBits_t uxBitsToWaitFor,
-                                     const BaseType_t xClearOnExit,
-                                     const BaseType_t xWaitForAllBits,
                                      TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupWaitBitsImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
-        " MPU_xEventGroupWaitBits_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xEventGroupWaitBitsImpl                     \n"
-        " MPU_xEventGroupWaitBits_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupWaitBitsImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupSyncImpl                       \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xEventGroupSync_Unpriv                        \n"
+            " MPU_xEventGroupSync_Priv:                             \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xEventGroupSyncImpl                         \n"
+            " MPU_xEventGroupSync_Unpriv:                           \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupSyncImpl                        \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                      const EventBits_t uxBitsToClear ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                      const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupClearBitsImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xEventGroupClearBits_Unpriv                   \n"
-        " MPU_xEventGroupClearBits_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xEventGroupClearBitsImpl                    \n"
-        " MPU_xEventGroupClearBits_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupClearBitsImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxEventGroupGetNumberImpl                 \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxEventGroupGetNumber_Unpriv                  \n"
+                " MPU_uxEventGroupGetNumber_Priv:                       \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxEventGroupGetNumberImpl                   \n"
+                " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxEventGroupGetNumberImpl                  \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
 /*-----------------------------------------------------------*/
 
-EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                    const EventBits_t uxBitsToSet ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                    const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupSetBitsImpl                    \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xEventGroupSetBits_Unpriv                     \n"
-        " MPU_xEventGroupSetBits_Priv:                          \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xEventGroupSetBitsImpl                      \n"
-        " MPU_xEventGroupSetBits_Unpriv:                        \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupSetBitsImpl                     \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vEventGroupSetNumber( void * xEventGroup,
+                                       UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vEventGroupSetNumber( void * xEventGroup,
+                                       UBaseType_t uxEventGroupNumber ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vEventGroupSetNumberImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vEventGroupSetNumber_Unpriv                   \n"
+                " MPU_vEventGroupSetNumber_Priv:                        \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vEventGroupSetNumberImpl                    \n"
+                " MPU_vEventGroupSetNumber_Unpriv:                      \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vEventGroupSetNumberImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
 /*-----------------------------------------------------------*/
 
-EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                 const EventBits_t uxBitsToSet,
-                                 const EventBits_t uxBitsToWaitFor,
-                                 TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                  const void * pvTxData,
+                                  size_t xDataLengthBytes,
+                                  TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                 const EventBits_t uxBitsToSet,
-                                 const EventBits_t uxBitsToWaitFor,
-                                 TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupSyncImpl                       \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xEventGroupSync_Unpriv                        \n"
-        " MPU_xEventGroupSync_Priv:                             \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xEventGroupSyncImpl                         \n"
-        " MPU_xEventGroupSync_Unpriv:                           \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupSyncImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                  const void * pvTxData,
+                                  size_t xDataLengthBytes,
+                                  TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferSendImpl                     \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferSend_Unpriv                      \n"
+            " MPU_xStreamBufferSend_Priv:                           \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferSendImpl                       \n"
+            " MPU_xStreamBufferSend_Unpriv:                         \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferSendImpl                      \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                     void * pvRxData,
+                                     size_t xBufferLengthBytes,
+                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxEventGroupGetNumberImpl                 \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxEventGroupGetNumber_Unpriv                  \n"
-        " MPU_uxEventGroupGetNumber_Priv:                       \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxEventGroupGetNumberImpl                   \n"
-        " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxEventGroupGetNumberImpl                  \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                     void * pvRxData,
+                                     size_t xBufferLengthBytes,
+                                     TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferReceiveImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferReceive_Unpriv                   \n"
+            " MPU_xStreamBufferReceive_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferReceiveImpl                    \n"
+            " MPU_xStreamBufferReceive_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferReceiveImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vEventGroupSetNumber( void * xEventGroup,
-                               UBaseType_t uxEventGroupNumber ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vEventGroupSetNumber( void * xEventGroup,
-                               UBaseType_t uxEventGroupNumber ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vEventGroupSetNumberImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vEventGroupSetNumber_Unpriv                   \n"
-        " MPU_vEventGroupSetNumber_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vEventGroupSetNumberImpl                    \n"
-        " MPU_vEventGroupSetNumber_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vEventGroupSetNumberImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferIsFullImpl                   \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
+            " MPU_xStreamBufferIsFull_Priv:                         \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferIsFullImpl                     \n"
+            " MPU_xStreamBufferIsFull_Unpriv:                       \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferIsFullImpl                    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                              const void * pvTxData,
-                              size_t xDataLengthBytes,
-                              TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                              const void * pvTxData,
-                              size_t xDataLengthBytes,
-                              TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferSendImpl                     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferSend_Unpriv                      \n"
-        " MPU_xStreamBufferSend_Priv:                           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferSendImpl                       \n"
-        " MPU_xStreamBufferSend_Unpriv:                         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferSendImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
+            " MPU_xStreamBufferIsEmpty_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferIsEmptyImpl                    \n"
+            " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferIsEmptyImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                 void * pvRxData,
-                                 size_t xBufferLengthBytes,
-                                 TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                 void * pvRxData,
-                                 size_t xBufferLengthBytes,
-                                 TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferReceiveImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferReceive_Unpriv                   \n"
-        " MPU_xStreamBufferReceive_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferReceiveImpl                    \n"
-        " MPU_xStreamBufferReceive_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferReceiveImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
+            " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
+            " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferSpacesAvailableImpl           \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferIsFullImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
-        " MPU_xStreamBufferIsFull_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferIsFullImpl                     \n"
-        " MPU_xStreamBufferIsFull_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferIsFullImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
+            " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferBytesAvailableImpl             \n"
+            " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferBytesAvailableImpl            \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                 size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
-        " MPU_xStreamBufferIsEmpty_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferIsEmptyImpl                    \n"
-        " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferIsEmptyImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                 size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
+            " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
+            " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferSetTriggerLevelImpl           \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
-        " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
-        " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferSpacesAvailableImpl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
-size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
-        " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferBytesAvailableImpl             \n"
-        " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferBytesAvailableImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                             size_t xTriggerLevel ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                             size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
-        " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
-        " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferSetTriggerLevelImpl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
-size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
-        " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
-        " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferNextMessageLengthBytesImpl    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
+            " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
+            " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferNextMessageLengthBytesImpl    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c b/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
index 80410e82e..c940c304b 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
@@ -110,8 +110,8 @@
 /**
  * @brief Constants used during system call enter and exit.
  */
-#define portPSR_STACK_PADDING_MASK                ( 1UL << 9UL )
-#define portEXC_RETURN_STACK_FRAME_TYPE_MASK      ( 1UL << 4UL )
+#define portPSR_STACK_PADDING_MASK              ( 1UL << 9UL )
+#define portEXC_RETURN_STACK_FRAME_TYPE_MASK    ( 1UL << 4UL )
 /*-----------------------------------------------------------*/
 
 /**
@@ -133,81 +133,81 @@
 /**
  * @brief Offsets in the stack to the parameters when inside the SVC handler.
  */
-#define portOFFSET_TO_LR                    ( 5 )
-#define portOFFSET_TO_PC                    ( 6 )
-#define portOFFSET_TO_PSR                   ( 7 )
+#define portOFFSET_TO_LR     ( 5 )
+#define portOFFSET_TO_PC     ( 6 )
+#define portOFFSET_TO_PSR    ( 7 )
 /*-----------------------------------------------------------*/
 
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                      ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                      ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                       ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                      ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                      ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                     ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                     ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK  ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK               ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK               ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK               ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK               ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK               ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK               ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK               ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK               ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0              ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1              ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2              ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3              ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4              ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5              ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6              ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7              ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE            ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT      ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                      ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE             ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -216,11 +216,11 @@
 
 /* Extract last address of the MPU region as encoded in the
  * RLAR (Region Limit Address Register) value. */
-#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar )  \
+#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar ) \
     ( ( ( rlar ) & portMPU_RLAR_ADDRESS_MASK ) | ~portMPU_RLAR_ADDRESS_MASK )
 
 /* Does addr lies within [start, end] address range? */
-#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end )    \
+#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \
     ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) )
 
 /* Is the access request satisfied by the available permissions? */
@@ -422,54 +422,57 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the system call stack so that upon returning from
-     * SVC, the system call stack is used.
-     *
-     * It is used for the system calls with up to 4 parameters.
-     *
-     * @param pulTaskStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the system call stack so that upon returning from
+ * SVC, the system call stack is used.
+ *
+ * It is used for the system calls with up to 4 parameters.
+ *
+ * @param pulTaskStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallEnter( uint32_t * pulTaskStack,
+                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the system call stack so that upon returning from
-     * SVC, the system call stack is used.
-     *
-     * It is used for the system calls with 5 parameters.
-     *
-     * @param pulTaskStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the system call stack so that upon returning from
+ * SVC, the system call stack is used.
+ *
+ * It is used for the system calls with 5 parameters.
+ *
+ * @param pulTaskStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallEnter_1( uint32_t * pulTaskStack,
+                             uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the task stack so that upon returning from
-     * SVC, the task stack is used again.
-     *
-     * @param pulSystemCallStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the task stack so that upon returning from
+ * SVC, the task stack is used again.
+ *
+ * @param pulSystemCallStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallExit( uint32_t * pulSystemCallStack,
+                          uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Checks whether or not the calling task is privileged.
-     *
-     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
-     */
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
     BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
 
 #endif /* configENABLE_MPU == 1 */
@@ -1086,18 +1089,18 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             vRestoreContextOfFirstTask();
             break;
 
-        #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
-            case portSVC_RAISE_PRIVILEGE:
+            #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+                case portSVC_RAISE_PRIVILEGE:
 
-                /* Only raise the privilege, if the svc was raised from any of
-                 * the system calls. */
-                if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
-                    ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
-                {
-                    vRaisePrivilege();
-                }
-                break;
-        #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+                    /* Only raise the privilege, if the svc was raised from any of
+                     * the system calls. */
+                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+                    {
+                        vRaisePrivilege();
+                    }
+                    break;
+            #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
         default:
             /* Incorrect SVC call. */
@@ -1108,513 +1111,526 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulSystemCallStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallEnter( uint32_t * pulTaskStack,
+                           uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulSystemCallStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        /* This is not NULL only for the duration of the system call. */
-        configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+        #if defined( __ARMCC_VERSION )
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+
+            /* This is not NULL only for the duration of the system call. */
+            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the system call stack for the stack frame. */
+            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulSystemCallStack[ i ] = pulTaskStack[ i ];
+            }
+
+            /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
+             * restore it when we exit from the system call. */
+            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* Use the pulSystemCallStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+
+            /* Remember the location where we should copy the stack frame when we exit from
+             * the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+
+            /* Record if the hardware used padding to force the stack pointer
+             * to be double word aligned. */
+            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
+            {
+                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
             }
+
+            /* We ensure in pxPortInitialiseStack that the system call stack is
+             * double word aligned and therefore, there is no need of padding.
+             * Clear the bit[9] of stacked xPSR. */
+            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
+
+            /* Raise the privilege for the duration of the system call. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " bics r0, r1         \n" /* Clear nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the system call stack for the stack frame. */
-        pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulSystemCallStack[ i ] = pulTaskStack[ i ];
-        }
-
-        /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
-         * restore it when we exit from the system call. */
-        pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-        __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* Use the pulSystemCallStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-
-        /* Remember the location where we should copy the stack frame when we exit from
-         * the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-        /* Record if the hardware used padding to force the stack pointer
-         * to be double word aligned. */
-        if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-        {
-            pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-        }
-        else
-        {
-            pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-        }
-
-        /* We ensure in pxPortInitialiseStack that the system call stack is
-         * double word aligned and therefore, there is no need of padding.
-         * Clear the bit[9] of stacked xPSR. */
-        pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-        /* Raise the privilege for the duration of the system call. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " bics r0, r1         \n" /* Clear nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulSystemCallStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallEnter_1( uint32_t * pulTaskStack,
+                             uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulSystemCallStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        /* This is not NULL only for the duration of the system call. */
-        configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+        #if defined( __ARMCC_VERSION )
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+
+            /* This is not NULL only for the duration of the system call. */
+            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the system call stack for the stack frame and
+             * the parameter passed on the stack. We only need to copy one
+             * parameter but we still reserve 2 spaces to keep the stack
+             * double word aligned. */
+            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulSystemCallStack[ i ] = pulTaskStack[ i ];
+            }
+
+            /* Copy the parameter which is passed the stack. */
+            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
+            {
+                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
+
+                /* Record if the hardware used padding to force the stack pointer
+                 * to be double word aligned. */
+                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
+
+                /* Record if the hardware used padding to force the stack pointer
+                 * to be double word aligned. */
+                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
             }
+
+            /* Store the value of the LR and PSPLIM registers before the SVC was raised.
+             * We need to restore it when we exit from the system call. */
+            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* Use the pulSystemCallStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+
+            /* Remember the location where we should copy the stack frame when we exit from
+             * the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+
+            /* We ensure in pxPortInitialiseStack that the system call stack is
+             * double word aligned and therefore, there is no need of padding.
+             * Clear the bit[9] of stacked xPSR. */
+            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
+
+            /* Raise the privilege for the duration of the system call. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " bics r0, r1         \n" /* Clear nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the system call stack for the stack frame and
-         * the parameter passed on the stack. We only need to copy one
-         * parameter but we still reserve 2 spaces to keep the stack
-         * double word aligned. */
-        pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulSystemCallStack[ i ] = pulTaskStack[ i ];
-        }
-
-        /* Copy the parameter which is passed the stack. */
-        if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-        {
-            pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
-            /* Record if the hardware used padding to force the stack pointer
-             * to be double word aligned. */
-            pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-        }
-        else
-        {
-            pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
-            /* Record if the hardware used padding to force the stack pointer
-             * to be double word aligned. */
-            pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-        }
-
-        /* Store the value of the LR and PSPLIM registers before the SVC was raised.
-         * We need to restore it when we exit from the system call. */
-        pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-        __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* Use the pulSystemCallStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-
-        /* Remember the location where we should copy the stack frame when we exit from
-         * the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-        /* We ensure in pxPortInitialiseStack that the system call stack is
-         * double word aligned and therefore, there is no need of padding.
-         * Clear the bit[9] of stacked xPSR. */
-        pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-        /* Raise the privilege for the duration of the system call. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " bics r0, r1         \n" /* Clear nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulTaskStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallExit( uint32_t * pulSystemCallStack,
+                          uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulTaskStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+        #if defined( __ARMCC_VERSION )
+
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the task stack for the stack frame. */
+            pulTaskStack = pulTaskStack - ulStackFrameSize;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulTaskStack[ i ] = pulSystemCallStack[ i ];
+            }
+
+            /* Use the pulTaskStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
+
+            /* Restore the LR and PSPLIM to what they were at the time of
+             * system call entry. */
+            pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* If the hardware used padding to force the stack pointer
+             * to be double word aligned, set the stacked xPSR bit[9],
+             * otherwise clear it. */
+            if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG )
+            {
+                pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
             }
+
+            /* This is not NULL only for the duration of the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
+
+            /* Drop the privilege before returning to the thread mode. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " orrs r0, r1         \n" /* Set nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the task stack for the stack frame. */
-        pulTaskStack = pulTaskStack - ulStackFrameSize;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulTaskStack[ i ] = pulSystemCallStack[ i ];
-        }
-
-        /* Use the pulTaskStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
-
-        /* Restore the LR and PSPLIM to what they were at the time of
-         * system call entry. */
-        pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* If the hardware used padding to force the stack pointer
-         * to be double word aligned, set the stacked xPSR bit[9],
-         * otherwise clear it. */
-        if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG )
-        {
-            pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK;
-        }
-        else
-        {
-            pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-        }
-
-        /* This is not NULL only for the duration of the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
-
-        /* Drop the privilege before returning to the thread mode. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " orrs r0, r1         \n" /* Set nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */
-{
-    BaseType_t xTaskIsPrivileged = pdFALSE;
-    const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
-
-    if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+    BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */
     {
-        xTaskIsPrivileged = pdTRUE;
-    }
+        BaseType_t xTaskIsPrivileged = pdFALSE;
+        const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
 
-    return xTaskIsPrivileged;
-}
+        if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+        {
+            xTaskIsPrivileged = pdTRUE;
+        }
+
+        return xTaskIsPrivileged;
+    }
 
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
-#if( configENABLE_MPU == 1 )
+#if ( configENABLE_MPU == 1 )
 
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     StackType_t * pxEndOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters,
-                                     BaseType_t xRunPrivileged,
-                                     xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
-{
-    uint32_t ulIndex = 0;
-
-    xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
-    ulIndex++;
-
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
-    ulIndex++;
-
-    #if ( configENABLE_TRUSTZONE == 1 )
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters,
+                                         BaseType_t xRunPrivileged,
+                                         xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
     {
-        xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT;  /* xSecureContext. */
+        uint32_t ulIndex = 0;
+
+        xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
         ulIndex++;
-    }
-    #endif /* configENABLE_TRUSTZONE */
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
-    ulIndex++;
-    if( xRunPrivileged == pdTRUE )
-    {
-        xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */
         ulIndex++;
-    }
-    else
-    {
-        xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */
         ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
+        ulIndex++;
+
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters;            /* r0. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x01010101;                           /* r1. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x02020202;                           /* r2. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x03030303;                           /* r3. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x12121212;                           /* r12. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode;                  /* PC. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR;                     /* xPSR. */
+        ulIndex++;
+
+        #if ( configENABLE_TRUSTZONE == 1 )
+        {
+            xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT; /* xSecureContext. */
+            ulIndex++;
+        }
+        #endif /* configENABLE_TRUSTZONE */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
+        ulIndex++;
+
+        if( xRunPrivileged == pdTRUE )
+        {
+            xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
+            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+            ulIndex++;
+        }
+        else
+        {
+            xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
+            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+            ulIndex++;
+        }
+
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
+        ulIndex++;
+
+        #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+        {
+            /* Ensure that the system call stack is double word aligned. */
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] );
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) &
+                                                                                     ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
+
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] );
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) +
+                                                                                            ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) &
+                                                                                          ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
+
+            /* This is not NULL only for the duration of a system call. */
+            xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL;
+        }
+        #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
+
+        return &( xMPUSettings->ulContext[ ulIndex ] );
     }
-    xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
-    ulIndex++;
-
-    #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
-    {
-        /* Ensure that the system call stack is double word aligned. */
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] );
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) &
-                                                                                 ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
-
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] );
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) +
-                                                                                        ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) &
-                                                                                      ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
-
-        /* This is not NULL only for the duration of a system call. */
-        xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL;
-    }
-    #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
-
-    return &( xMPUSettings->ulContext[ ulIndex ] );
-}
 
 #else /* configENABLE_MPU */
 
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     StackType_t * pxEndOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters ) /* PRIVILEGED_FUNCTION */
-{
-    /* Simulate the stack frame as it would be created by a context switch
-     * interrupt. */
-    #if ( portPRELOAD_REGISTERS == 0 )
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters ) /* PRIVILEGED_FUNCTION */
     {
-        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-        pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
-        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-        pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
-        *pxTopOfStack = portINITIAL_EXC_RETURN;
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
-
-        #if ( configENABLE_TRUSTZONE == 1 )
+        /* Simulate the stack frame as it would be created by a context switch
+         * interrupt. */
+        #if ( portPRELOAD_REGISTERS == 0 )
         {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
-        }
-        #endif /* configENABLE_TRUSTZONE */
-    }
-    #else /* portPRELOAD_REGISTERS */
-    {
-        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
-        pxTopOfStack--;
-        *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
+            pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
+            *pxTopOfStack = portINITIAL_EXC_RETURN;
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+            #if ( configENABLE_TRUSTZONE == 1 )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+            }
+            #endif /* configENABLE_TRUSTZONE */
+        }
+        #else /* portPRELOAD_REGISTERS */
         {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
-        }
-        #endif /* configENABLE_TRUSTZONE */
-    }
-    #endif /* portPRELOAD_REGISTERS */
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
+            pxTopOfStack--;
+            *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack;            /* Slot used to hold this task's PSPLIM value. */
 
-    return pxTopOfStack;
-}
+            #if ( configENABLE_TRUSTZONE == 1 )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+            }
+            #endif /* configENABLE_TRUSTZONE */
+        }
+        #endif /* portPRELOAD_REGISTERS */
+
+        return pxTopOfStack;
+    }
 
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.c b/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.c
index 504b6bf3b..e533dd7e9 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.c
@@ -42,111 +42,111 @@
 
 #if ( configENABLE_MPU == 1 )
 
-void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        " .syntax unified                                 \n"
-        "                                                 \n"
-        " program_mpu_first_task:                         \n"
-        "    ldr r2, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB. */
-        "                                                 \n"
-        "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-        "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
-        "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
-        "    str r2, [r1]                                 \n" /* Disable MPU. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
-        "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-        "    ldr r2, xMAIR0Const2                         \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-        "    str r1, [r2]                                 \n" /* Program MAIR0. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-        "    ldr r1, xRNRConst2                           \n" /* r1 = 0xe000ed98 [Location of RNR]. */
-        "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "                                                 \n"
-        "    movs r3, #4                                  \n" /* r3 = 4. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 4. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-        "                                                 \n"
-    #if ( configTOTAL_MPU_REGIONS == 16 )
-        "    movs r3, #8                                  \n" /* r3 = 8. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 8. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-        "    movs r3, #12                                 \n" /* r3 = 12. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 12. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-    #endif /* configTOTAL_MPU_REGIONS == 16 */
-        "                                                 \n"
-        "   ldr r1, xMPUCTRLConst2                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
-        "   orr r2, #1                                    \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
-        "   str r2, [r1]                                  \n" /* Enable MPU. */
-        "   dsb                                           \n" /* Force memory writes before continuing. */
-        "                                                 \n"
-        " restore_context_first_task:                     \n"
-        "    ldr r2, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB.*/
-        "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
-        "                                                 \n"
-        " restore_special_regs_first_task:                \n"
-        "    ldmdb r1!, {r2-r4, lr}                       \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
-        "    msr psp, r2                                  \n"
-        "    msr psplim, r3                               \n"
-        "    msr control, r4                              \n"
-        "                                                 \n"
-        " restore_general_regs_first_task:                \n"
-        "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
-        "    stmia r2!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
-        "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 restored. */
-        "                                                 \n"
-        " restore_context_done_first_task:                \n"
-        "    str r1, [r0]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
-        "    mov r0, #0                                   \n"
-        "    msr basepri, r0                              \n" /* Ensure that interrupts are enabled when the first task starts. */
-        "    bx lr                                        \n"
-        "                                                 \n"
-        " .align 4                                        \n"
-        " pxCurrentTCBConst2: .word pxCurrentTCB          \n"
-        " xMPUCTRLConst2: .word 0xe000ed94                \n"
-        " xMAIR0Const2: .word 0xe000edc0                  \n"
-        " xRNRConst2: .word 0xe000ed98                    \n"
-        " xRBARConst2: .word 0xe000ed9c                   \n"
-    );
-}
+    void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                 \n"
+            "                                                 \n"
+            " program_mpu_first_task:                         \n"
+            "    ldr r2, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB. */
+            "                                                 \n"
+            "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
+            "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
+            "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
+            "    str r2, [r1]                                 \n" /* Disable MPU. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
+            "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
+            "    ldr r2, xMAIR0Const2                         \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    str r1, [r2]                                 \n" /* Program MAIR0. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
+            "    ldr r1, xRNRConst2                           \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "                                                 \n"
+            "    movs r3, #4                                  \n" /* r3 = 4. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 4. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "                                                 \n"
+            #if ( configTOTAL_MPU_REGIONS == 16 )
+                "    movs r3, #8                                  \n" /* r3 = 8. */
+                "    str r3, [r1]                                 \n" /* Program RNR = 8. */
+                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+                "    movs r3, #12                                 \n" /* r3 = 12. */
+                "    str r3, [r1]                                 \n" /* Program RNR = 12. */
+                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            #endif /* configTOTAL_MPU_REGIONS == 16 */
+            "                                                 \n"
+            "   ldr r1, xMPUCTRLConst2                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
+            "   orr r2, #1                                    \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
+            "   str r2, [r1]                                  \n" /* Enable MPU. */
+            "   dsb                                           \n" /* Force memory writes before continuing. */
+            "                                                 \n"
+            " restore_context_first_task:                     \n"
+            "    ldr r2, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB.*/
+            "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
+            "                                                 \n"
+            " restore_special_regs_first_task:                \n"
+            "    ldmdb r1!, {r2-r4, lr}                       \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
+            "    msr psp, r2                                  \n"
+            "    msr psplim, r3                               \n"
+            "    msr control, r4                              \n"
+            "                                                 \n"
+            " restore_general_regs_first_task:                \n"
+            "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
+            "    stmia r2!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
+            "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 restored. */
+            "                                                 \n"
+            " restore_context_done_first_task:                \n"
+            "    str r1, [r0]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
+            "    mov r0, #0                                   \n"
+            "    msr basepri, r0                              \n" /* Ensure that interrupts are enabled when the first task starts. */
+            "    bx lr                                        \n"
+            "                                                 \n"
+            " .align 4                                        \n"
+            " pxCurrentTCBConst2: .word pxCurrentTCB          \n"
+            " xMPUCTRLConst2: .word 0xe000ed94                \n"
+            " xMAIR0Const2: .word 0xe000edc0                  \n"
+            " xRNRConst2: .word 0xe000ed98                    \n"
+            " xRBARConst2: .word 0xe000ed9c                   \n"
+        );
+    }
 
 #else /* configENABLE_MPU */
 
-void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "   .syntax unified                                 \n"
-        "                                                   \n"
-        "   ldr  r2, pxCurrentTCBConst2                     \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr  r1, [r2]                                   \n"/* Read pxCurrentTCB. */
-        "   ldr  r0, [r1]                                   \n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
-        "                                                   \n"
-        "   ldm  r0!, {r1-r2}                               \n"/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
-        "   msr  psplim, r1                                 \n"/* Set this task's PSPLIM value. */
-        "   movs r1, #2                                     \n"/* r1 = 2. */
-        "   msr  CONTROL, r1                                \n"/* Switch to use PSP in the thread mode. */
-        "   adds r0, #32                                    \n"/* Discard everything up to r0. */
-        "   msr  psp, r0                                    \n"/* This is now the new top of stack to use in the task. */
-        "   isb                                             \n"
-        "   mov  r0, #0                                     \n"
-        "   msr  basepri, r0                                \n"/* Ensure that interrupts are enabled when the first task starts. */
-        "   bx   r2                                         \n"/* Finally, branch to EXC_RETURN. */
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "pxCurrentTCBConst2: .word pxCurrentTCB             \n"
-    );
-}
+    void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            "   .syntax unified                                 \n"
+            "                                                   \n"
+            "   ldr  r2, pxCurrentTCBConst2                     \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr  r1, [r2]                                   \n" /* Read pxCurrentTCB. */
+            "   ldr  r0, [r1]                                   \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+            "                                                   \n"
+            "   ldm  r0!, {r1-r2}                               \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
+            "   msr  psplim, r1                                 \n" /* Set this task's PSPLIM value. */
+            "   movs r1, #2                                     \n" /* r1 = 2. */
+            "   msr  CONTROL, r1                                \n" /* Switch to use PSP in the thread mode. */
+            "   adds r0, #32                                    \n" /* Discard everything up to r0. */
+            "   msr  psp, r0                                    \n" /* This is now the new top of stack to use in the task. */
+            "   isb                                             \n"
+            "   mov  r0, #0                                     \n"
+            "   msr  basepri, r0                                \n" /* Ensure that interrupts are enabled when the first task starts. */
+            "   bx   r2                                         \n" /* Finally, branch to EXC_RETURN. */
+            "                                                   \n"
+            "   .align 4                                        \n"
+            "pxCurrentTCBConst2: .word pxCurrentTCB             \n"
+        );
+    }
 
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
@@ -157,12 +157,12 @@ BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs r0, control                                 \n"/* r0 = CONTROL. */
-        "   tst r0, #1                                      \n"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+        "   mrs r0, control                                 \n" /* r0 = CONTROL. */
+        "   tst r0, #1                                      \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
         "   ite ne                                          \n"
-        "   movne r0, #0                                    \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
-        "   moveq r0, #1                                    \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
-        "   bx lr                                           \n"/* Return. */
+        "   movne r0, #0                                    \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+        "   moveq r0, #1                                    \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+        "   bx lr                                           \n" /* Return. */
         "                                                   \n"
         "   .align 4                                        \n"
         ::: "r0", "memory"
@@ -176,10 +176,10 @@ void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs  r0, control                                \n"/* Read the CONTROL register. */
-        "   bic r0, #1                                      \n"/* Clear the bit 0. */
-        "   msr  control, r0                                \n"/* Write back the new CONTROL value. */
-        "   bx lr                                           \n"/* Return to the caller. */
+        "   mrs  r0, control                                \n" /* Read the CONTROL register. */
+        "   bic r0, #1                                      \n" /* Clear the bit 0. */
+        "   msr  control, r0                                \n" /* Write back the new CONTROL value. */
+        "   bx lr                                           \n" /* Return to the caller. */
         ::: "r0", "memory"
     );
 }
@@ -191,10 +191,10 @@ void vResetPrivilege( void ) /* __attribute__ (( naked )) */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs r0, control                                 \n"/* r0 = CONTROL. */
-        "   orr r0, #1                                      \n"/* r0 = r0 | 1. */
-        "   msr control, r0                                 \n"/* CONTROL = r0. */
-        "   bx lr                                           \n"/* Return to the caller. */
+        "   mrs r0, control                                 \n" /* r0 = CONTROL. */
+        "   orr r0, #1                                      \n" /* r0 = r0 | 1. */
+        "   msr control, r0                                 \n" /* CONTROL = r0. */
+        "   bx lr                                           \n" /* Return to the caller. */
         ::: "r0", "memory"
     );
 }
@@ -206,15 +206,15 @@ void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   ldr r0, xVTORConst                              \n"/* Use the NVIC offset register to locate the stack. */
-        "   ldr r0, [r0]                                    \n"/* Read the VTOR register which gives the address of vector table. */
-        "   ldr r0, [r0]                                    \n"/* The first entry in vector table is stack pointer. */
-        "   msr msp, r0                                     \n"/* Set the MSP back to the start of the stack. */
-        "   cpsie i                                         \n"/* Globally enable interrupts. */
+        "   ldr r0, xVTORConst                              \n" /* Use the NVIC offset register to locate the stack. */
+        "   ldr r0, [r0]                                    \n" /* Read the VTOR register which gives the address of vector table. */
+        "   ldr r0, [r0]                                    \n" /* The first entry in vector table is stack pointer. */
+        "   msr msp, r0                                     \n" /* Set the MSP back to the start of the stack. */
+        "   cpsie i                                         \n" /* Globally enable interrupts. */
         "   cpsie f                                         \n"
         "   dsb                                             \n"
         "   isb                                             \n"
-        "   svc %0                                          \n"/* System call to start the first task. */
+        "   svc %0                                          \n" /* System call to start the first task. */
         "   nop                                             \n"
         "                                                   \n"
         "   .align 4                                        \n"
@@ -230,12 +230,12 @@ uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCT
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs r0, basepri                                 \n"/* r0 = basepri. Return original basepri value. */
-        "   mov r1, %0                                      \n"/* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        "   msr basepri, r1                                 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        "   mrs r0, basepri                                 \n" /* r0 = basepri. Return original basepri value. */
+        "   mov r1, %0                                      \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        "   msr basepri, r1                                 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
         "   dsb                                             \n"
         "   isb                                             \n"
-        "   bx lr                                           \n"/* Return. */
+        "   bx lr                                           \n" /* Return. */
         ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
     );
 }
@@ -247,10 +247,10 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   msr basepri, r0                                 \n"/* basepri = ulMask. */
+        "   msr basepri, r0                                 \n" /* basepri = ulMask. */
         "   dsb                                             \n"
         "   isb                                             \n"
-        "   bx lr                                           \n"/* Return. */
+        "   bx lr                                           \n" /* Return. */
         ::: "memory"
     );
 }
@@ -258,246 +258,246 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
 
 #if ( configENABLE_MPU == 1 )
 
-void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        " .syntax unified                                 \n"
-        "                                                 \n"
-        " ldr r2, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        " ldr r0, [r2]                                    \n" /* r0 = pxCurrentTCB. */
-        " ldr r1, [r0]                                    \n" /* r1 = Location in TCB where the context should be saved. */
-        " mrs r2, psp                                     \n" /* r2 = PSP. */
-        "                                                 \n"
-        " save_general_regs:                              \n"
-    #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-        "    add r2, r2, #0x20                            \n" /* Move r2 to location where s0 is saved. */
-        "    tst lr, #0x10                                \n"
-        "    ittt eq                                      \n"
-        "    vstmiaeq r1!, {s16-s31}                      \n" /* Store s16-s31. */
-        "    vldmiaeq r2, {s0-s16}                        \n" /* Copy hardware saved FP context into s0-s16. */
-        "    vstmiaeq r1!, {s0-s16}                       \n" /* Store hardware saved FP context. */
-        "    sub r2, r2, #0x20                            \n" /* Set r2 back to the location of hardware saved context. */
-    #endif /* configENABLE_FPU || configENABLE_MVE */
-        "                                                 \n"
-        "    stmia r1!, {r4-r11}                          \n" /* Store r4-r11. */
-        "    ldmia r2, {r4-r11}                           \n" /* Copy the hardware saved context into r4-r11. */
-        "    stmia r1!, {r4-r11}                          \n" /* Store the hardware saved context. */
-        "                                                 \n"
-        " save_special_regs:                              \n"
-        "    mrs r3, psplim                               \n" /* r3 = PSPLIM. */
-        "    mrs r4, control                              \n" /* r4 = CONTROL. */
-        "    stmia r1!, {r2-r4, lr}                       \n" /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
-        "    str r1, [r0]                                 \n" /* Save the location from where the context should be restored as the first member of TCB. */
-        "                                                 \n"
-        " select_next_task:                               \n"
-        "    mov r0, %0                                   \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
-        "    msr basepri, r0                              \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        "    dsb                                          \n"
-        "    isb                                          \n"
-        "    bl vTaskSwitchContext                        \n"
-        "    mov r0, #0                                   \n" /* r0 = 0. */
-        "    msr basepri, r0                              \n" /* Enable interrupts. */
-        "                                                 \n"
-        " program_mpu:                                    \n"
-        "    ldr r2, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB. */
-        "                                                 \n"
-        "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-        "    ldr r1, xMPUCTRLConst                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
-        "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
-        "    str r2, [r1]                                 \n" /* Disable MPU. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
-        "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-        "    ldr r2, xMAIR0Const                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-        "    str r1, [r2]                                 \n" /* Program MAIR0. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-        "    ldr r1, xRNRConst                            \n" /* r1 = 0xe000ed98 [Location of RNR]. */
-        "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "                                                 \n"
-        "    movs r3, #4                                  \n" /* r3 = 4. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 4. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-        "                                                 \n"
-    #if ( configTOTAL_MPU_REGIONS == 16 )
-        "    movs r3, #8                                  \n" /* r3 = 8. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 8. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-        "    movs r3, #12                                 \n" /* r3 = 12. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 12. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-    #endif /* configTOTAL_MPU_REGIONS == 16 */
-        "                                                 \n"
-        "   ldr r1, xMPUCTRLConst                         \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
-        "   orr r2, #1                                    \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
-        "   str r2, [r1]                                  \n" /* Enable MPU. */
-        "   dsb                                           \n" /* Force memory writes before continuing. */
-        "                                                 \n"
-        " restore_context:                                \n"
-        "    ldr r2, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB.*/
-        "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
-        "                                                 \n"
-        " restore_special_regs:                           \n"
-        "    ldmdb r1!, {r2-r4, lr}                       \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
-        "    msr psp, r2                                  \n"
-        "    msr psplim, r3                               \n"
-        "    msr control, r4                              \n"
-        "                                                 \n"
-        " restore_general_regs:                           \n"
-        "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
-        "    stmia r2!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
-        "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 restored. */
-    #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-        "    tst lr, #0x10                                \n"
-        "    ittt eq                                      \n"
-        "    vldmdbeq r1!, {s0-s16}                       \n" /* s0-s16 contain hardware saved FP context. */
-        "    vstmiaeq r2!, {s0-s16}                       \n" /* Copy hardware saved FP context on the task stack. */
-        "    vldmdbeq r1!, {s16-s31}                      \n" /* Restore s16-s31. */
-    #endif /* configENABLE_FPU || configENABLE_MVE */
-        "                                                 \n"
-        " restore_context_done:                           \n"
-        "    str r1, [r0]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
-        "    bx lr                                        \n"
-        "                                                 \n"
-        " .align 4                                        \n"
-        " pxCurrentTCBConst: .word pxCurrentTCB           \n"
-        " xMPUCTRLConst: .word 0xe000ed94                 \n"
-        " xMAIR0Const: .word 0xe000edc0                   \n"
-        " xRNRConst: .word 0xe000ed98                     \n"
-        " xRBARConst: .word 0xe000ed9c                    \n"
-        ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
-    );
-}
+    void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                 \n"
+            "                                                 \n"
+            " ldr r2, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            " ldr r0, [r2]                                    \n" /* r0 = pxCurrentTCB. */
+            " ldr r1, [r0]                                    \n" /* r1 = Location in TCB where the context should be saved. */
+            " mrs r2, psp                                     \n" /* r2 = PSP. */
+            "                                                 \n"
+            " save_general_regs:                              \n"
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+                "    add r2, r2, #0x20                            \n" /* Move r2 to location where s0 is saved. */
+                "    tst lr, #0x10                                \n"
+                "    ittt eq                                      \n"
+                "    vstmiaeq r1!, {s16-s31}                      \n" /* Store s16-s31. */
+                "    vldmiaeq r2, {s0-s16}                        \n" /* Copy hardware saved FP context into s0-s16. */
+                "    vstmiaeq r1!, {s0-s16}                       \n" /* Store hardware saved FP context. */
+                "    sub r2, r2, #0x20                            \n" /* Set r2 back to the location of hardware saved context. */
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+            "                                                 \n"
+            "    stmia r1!, {r4-r11}                          \n" /* Store r4-r11. */
+            "    ldmia r2, {r4-r11}                           \n" /* Copy the hardware saved context into r4-r11. */
+            "    stmia r1!, {r4-r11}                          \n" /* Store the hardware saved context. */
+            "                                                 \n"
+            " save_special_regs:                              \n"
+            "    mrs r3, psplim                               \n" /* r3 = PSPLIM. */
+            "    mrs r4, control                              \n" /* r4 = CONTROL. */
+            "    stmia r1!, {r2-r4, lr}                       \n" /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
+            "    str r1, [r0]                                 \n" /* Save the location from where the context should be restored as the first member of TCB. */
+            "                                                 \n"
+            " select_next_task:                               \n"
+            "    mov r0, %0                                   \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
+            "    msr basepri, r0                              \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+            "    dsb                                          \n"
+            "    isb                                          \n"
+            "    bl vTaskSwitchContext                        \n"
+            "    mov r0, #0                                   \n" /* r0 = 0. */
+            "    msr basepri, r0                              \n" /* Enable interrupts. */
+            "                                                 \n"
+            " program_mpu:                                    \n"
+            "    ldr r2, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB. */
+            "                                                 \n"
+            "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
+            "    ldr r1, xMPUCTRLConst                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
+            "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
+            "    str r2, [r1]                                 \n" /* Disable MPU. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
+            "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
+            "    ldr r2, xMAIR0Const                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    str r1, [r2]                                 \n" /* Program MAIR0. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
+            "    ldr r1, xRNRConst                            \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "                                                 \n"
+            "    movs r3, #4                                  \n" /* r3 = 4. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 4. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "                                                 \n"
+            #if ( configTOTAL_MPU_REGIONS == 16 )
+                "    movs r3, #8                                  \n" /* r3 = 8. */
+                "    str r3, [r1]                                 \n" /* Program RNR = 8. */
+                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+                "    movs r3, #12                                 \n" /* r3 = 12. */
+                "    str r3, [r1]                                 \n" /* Program RNR = 12. */
+                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            #endif /* configTOTAL_MPU_REGIONS == 16 */
+            "                                                 \n"
+            "   ldr r1, xMPUCTRLConst                         \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
+            "   orr r2, #1                                    \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
+            "   str r2, [r1]                                  \n" /* Enable MPU. */
+            "   dsb                                           \n" /* Force memory writes before continuing. */
+            "                                                 \n"
+            " restore_context:                                \n"
+            "    ldr r2, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB.*/
+            "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
+            "                                                 \n"
+            " restore_special_regs:                           \n"
+            "    ldmdb r1!, {r2-r4, lr}                       \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
+            "    msr psp, r2                                  \n"
+            "    msr psplim, r3                               \n"
+            "    msr control, r4                              \n"
+            "                                                 \n"
+            " restore_general_regs:                           \n"
+            "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
+            "    stmia r2!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
+            "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 restored. */
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+                "    tst lr, #0x10                                \n"
+                "    ittt eq                                      \n"
+                "    vldmdbeq r1!, {s0-s16}                       \n" /* s0-s16 contain hardware saved FP context. */
+                "    vstmiaeq r2!, {s0-s16}                       \n" /* Copy hardware saved FP context on the task stack. */
+                "    vldmdbeq r1!, {s16-s31}                      \n" /* Restore s16-s31. */
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+            "                                                 \n"
+            " restore_context_done:                           \n"
+            "    str r1, [r0]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
+            "    bx lr                                        \n"
+            "                                                 \n"
+            " .align 4                                        \n"
+            " pxCurrentTCBConst: .word pxCurrentTCB           \n"
+            " xMPUCTRLConst: .word 0xe000ed94                 \n"
+            " xMAIR0Const: .word 0xe000edc0                   \n"
+            " xRNRConst: .word 0xe000ed98                     \n"
+            " xRBARConst: .word 0xe000ed9c                    \n"
+            ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+        );
+    }
 
 #else /* configENABLE_MPU */
 
-void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "   .syntax unified                                 \n"
-        "                                                   \n"
-        "   mrs r0, psp                                     \n"/* Read PSP in r0. */
-        "                                                   \n"
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-            "   tst lr, #0x10                                   \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
-            "   it eq                                           \n"
-            "   vstmdbeq r0!, {s16-s31}                         \n"/* Store the additional FP context registers which are not saved automatically. */
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-        "                                                   \n"
-        "   mrs r2, psplim                                  \n"/* r2 = PSPLIM. */
-        "   mov r3, lr                                      \n"/* r3 = LR/EXC_RETURN. */
-        "   stmdb r0!, {r2-r11}                             \n"/* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */
-        "                                                   \n"
-        "   ldr r2, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r2]                                    \n"/* Read pxCurrentTCB. */
-        "   str r0, [r1]                                    \n"/* Save the new top of stack in TCB. */
-        "                                                   \n"
-        "   mov r0, %0                                      \n"/* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
-        "   msr basepri, r0                                 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        "   dsb                                             \n"
-        "   isb                                             \n"
-        "   bl vTaskSwitchContext                           \n"
-        "   mov r0, #0                                      \n"/* r0 = 0. */
-        "   msr basepri, r0                                 \n"/* Enable interrupts. */
-        "                                                   \n"
-        "   ldr r2, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r2]                                    \n"/* Read pxCurrentTCB. */
-        "   ldr r0, [r1]                                    \n"/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
-        "                                                   \n"
-        "   ldmia r0!, {r2-r11}                             \n"/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
-        "                                                   \n"
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-            "   tst r3, #0x10                                   \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
-            "   it eq                                           \n"
-            "   vldmiaeq r0!, {s16-s31}                         \n"/* Restore the additional FP context registers which are not restored automatically. */
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-        "                                                   \n"
-        "   msr psplim, r2                                  \n"/* Restore the PSPLIM register value for the task. */
-        "   msr psp, r0                                     \n"/* Remember the new top of stack for the task. */
-        "   bx r3                                           \n"
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "pxCurrentTCBConst: .word pxCurrentTCB              \n"
-        ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
-    );
-}
+    void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            "   .syntax unified                                 \n"
+            "                                                   \n"
+            "   mrs r0, psp                                     \n" /* Read PSP in r0. */
+            "                                                   \n"
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+                "   tst lr, #0x10                                   \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+                "   it eq                                           \n"
+                "   vstmdbeq r0!, {s16-s31}                         \n" /* Store the additional FP context registers which are not saved automatically. */
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+            "                                                   \n"
+            "   mrs r2, psplim                                  \n" /* r2 = PSPLIM. */
+            "   mov r3, lr                                      \n" /* r3 = LR/EXC_RETURN. */
+            "   stmdb r0!, {r2-r11}                             \n" /* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */
+            "                                                   \n"
+            "   ldr r2, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r1, [r2]                                    \n" /* Read pxCurrentTCB. */
+            "   str r0, [r1]                                    \n" /* Save the new top of stack in TCB. */
+            "                                                   \n"
+            "   mov r0, %0                                      \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
+            "   msr basepri, r0                                 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+            "   dsb                                             \n"
+            "   isb                                             \n"
+            "   bl vTaskSwitchContext                           \n"
+            "   mov r0, #0                                      \n" /* r0 = 0. */
+            "   msr basepri, r0                                 \n" /* Enable interrupts. */
+            "                                                   \n"
+            "   ldr r2, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r1, [r2]                                    \n" /* Read pxCurrentTCB. */
+            "   ldr r0, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
+            "                                                   \n"
+            "   ldmia r0!, {r2-r11}                             \n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
+            "                                                   \n"
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+                "   tst r3, #0x10                                   \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+                "   it eq                                           \n"
+                "   vldmiaeq r0!, {s16-s31}                         \n" /* Restore the additional FP context registers which are not restored automatically. */
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+            "                                                   \n"
+            "   msr psplim, r2                                  \n" /* Restore the PSPLIM register value for the task. */
+            "   msr psp, r0                                     \n" /* Remember the new top of stack for the task. */
+            "   bx r3                                           \n"
+            "                                                   \n"
+            "   .align 4                                        \n"
+            "pxCurrentTCBConst: .word pxCurrentTCB              \n"
+            ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+        );
+    }
 
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-   __asm volatile
-    (
-        ".syntax unified                \n"
-        ".extern vPortSVCHandler_C      \n"
-        ".extern vSystemCallEnter       \n"
-        ".extern vSystemCallEnter_1     \n"
-        ".extern vSystemCallExit        \n"
-        "                               \n"
-        "tst lr, #4                     \n"
-        "ite eq                         \n"
-        "mrseq r0, msp                  \n"
-        "mrsne r0, psp                  \n"
-        "                               \n"
-        "ldr r1, [r0, #24]              \n"
-        "ldrb r2, [r1, #-2]             \n"
-        "cmp r2, %0                     \n"
-        "beq syscall_enter              \n"
-        "cmp r2, %1                     \n"
-        "beq syscall_enter_1            \n"
-        "cmp r2, %2                     \n"
-        "beq syscall_exit               \n"
-        "b vPortSVCHandler_C            \n"
-        "                               \n"
-        "syscall_enter:                 \n"
-        "    mov r1, lr                 \n"
-        "    b vSystemCallEnter         \n"
-        "                               \n"
-        "syscall_enter_1:               \n"
-        "    mov r1, lr                 \n"
-        "    b vSystemCallEnter_1       \n"
-        "                               \n"
-        "syscall_exit:                  \n"
-        "    mov r1, lr                 \n"
-        "    b vSystemCallExit          \n"
-        "                               \n"
-        : /* No outputs. */
-        :"i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT )
-        : "r0", "r1", "r2", "memory"
-    );
-}
+    void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            ".syntax unified                \n"
+            ".extern vPortSVCHandler_C      \n"
+            ".extern vSystemCallEnter       \n"
+            ".extern vSystemCallEnter_1     \n"
+            ".extern vSystemCallExit        \n"
+            "                               \n"
+            "tst lr, #4                     \n"
+            "ite eq                         \n"
+            "mrseq r0, msp                  \n"
+            "mrsne r0, psp                  \n"
+            "                               \n"
+            "ldr r1, [r0, #24]              \n"
+            "ldrb r2, [r1, #-2]             \n"
+            "cmp r2, %0                     \n"
+            "beq syscall_enter              \n"
+            "cmp r2, %1                     \n"
+            "beq syscall_enter_1            \n"
+            "cmp r2, %2                     \n"
+            "beq syscall_exit               \n"
+            "b vPortSVCHandler_C            \n"
+            "                               \n"
+            "syscall_enter:                 \n"
+            "    mov r1, lr                 \n"
+            "    b vSystemCallEnter         \n"
+            "                               \n"
+            "syscall_enter_1:               \n"
+            "    mov r1, lr                 \n"
+            "    b vSystemCallEnter_1       \n"
+            "                               \n"
+            "syscall_exit:                  \n"
+            "    mov r1, lr                 \n"
+            "    b vSystemCallExit          \n"
+            "                               \n"
+            : /* No outputs. */
+            : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT )
+            : "r0", "r1", "r2", "memory"
+        );
+    }
 
 #else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
-void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "   .syntax unified                                 \n"
-        "                                                   \n"
-        "   tst lr, #4                                      \n"
-        "   ite eq                                          \n"
-        "   mrseq r0, msp                                   \n"
-        "   mrsne r0, psp                                   \n"
-        "   ldr r1, svchandler_address_const                \n"
-        "   bx r1                                           \n"
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "svchandler_address_const: .word vPortSVCHandler_C  \n"
-    );
-}
+    void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            "   .syntax unified                                 \n"
+            "                                                   \n"
+            "   tst lr, #4                                      \n"
+            "   ite eq                                          \n"
+            "   mrseq r0, msp                                   \n"
+            "   mrsne r0, psp                                   \n"
+            "   ldr r1, svchandler_address_const                \n"
+            "   bx r1                                           \n"
+            "                                                   \n"
+            "   .align 4                                        \n"
+            "svchandler_address_const: .word vPortSVCHandler_C  \n"
+        );
+    }
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacro.h b/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacro.h
index 6e4fe5a3d..66fa2056d 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacro.h
@@ -48,9 +48,9 @@
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME                       "Cortex-M35P"
-#define portHAS_ARMV8M_MAIN_EXTENSION       1
-#define portDONT_DISCARD                    __attribute__( ( used ) )
+#define portARCH_NAME                    "Cortex-M35P"
+#define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
 /* ARMv8-M common port configurations. */
@@ -60,8 +60,8 @@
 /**
  * @brief Critical section management.
  */
-#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()
-#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )
+#define portDISABLE_INTERRUPTS()    ulSetInterruptMask()
+#define portENABLE_INTERRUPTS()     vClearInterruptMask( 0 )
 /*-----------------------------------------------------------*/
 
 /* *INDENT-OFF* */
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
index e5ffdb48b..62e462a27 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
@@ -81,8 +81,8 @@ typedef unsigned long    UBaseType_t;
     typedef uint32_t     TickType_t;
     #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-     * not need to be guarded with a critical section. */
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
     #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -117,7 +117,7 @@ extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGE
 extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
 
 #if ( configENABLE_TRUSTZONE == 1 )
-    extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize );     /* __attribute__ (( naked )) */
+    extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
     extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
 #endif /* configENABLE_TRUSTZONE */
 
@@ -188,13 +188,13 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Settings to define an MPU region.
-     */
+/**
+ * @brief Settings to define an MPU region.
+ */
     typedef struct MPURegionSettings
     {
-        uint32_t ulRBAR;     /**< RBAR for the region. */
-        uint32_t ulRLAR;     /**< RLAR for the region. */
+        uint32_t ulRBAR; /**< RBAR for the region. */
+        uint32_t ulRLAR; /**< RLAR for the region. */
     } MPURegionSettings_t;
 
     #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
@@ -203,9 +203,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-        /**
-         * @brief System call stack.
-         */
+/**
+ * @brief System call stack.
+ */
         typedef struct SYSTEM_CALL_STACK_INFO
         {
             uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ];
@@ -218,74 +218,74 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
-    /**
-     * @brief MPU settings as stored in the TCB.
-     */
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
     #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
 
-        #if( configENABLE_TRUSTZONE == 1 )
+        #if ( configENABLE_TRUSTZONE == 1 )
 
-            /*
-             * +-----------+---------------+----------+-----------------+------------------------------+-----+
-             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
-             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
-             * +-----------+---------------+----------+-----------------+------------------------------+-----+
-             *
-             * <-----------><--------------><---------><----------------><-----------------------------><---->
-             *      16             16            8               8                     5                   1
-             */
-            #define MAX_CONTEXT_SIZE 54
+/*
+ * +-----------+---------------+----------+-----------------+------------------------------+-----+
+ * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+ * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+ * +-----------+---------------+----------+-----------------+------------------------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><-----------------------------><---->
+ *      16             16            8               8                     5                   1
+ */
+            #define MAX_CONTEXT_SIZE    54
 
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-            /*
-             * +-----------+---------------+----------+-----------------+----------------------+-----+
-             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
-             * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
-             * +-----------+---------------+----------+-----------------+----------------------+-----+
-             *
-             * <-----------><--------------><---------><----------------><---------------------><---->
-             *      16             16            8               8                  4              1
-             */
-            #define MAX_CONTEXT_SIZE 53
+/*
+ * +-----------+---------------+----------+-----------------+----------------------+-----+
+ * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+ * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
+ * +-----------+---------------+----------+-----------------+----------------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><---------------------><---->
+ *      16             16            8               8                  4              1
+ */
+            #define MAX_CONTEXT_SIZE    53
 
         #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
 
     #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-        #if( configENABLE_TRUSTZONE == 1 )
+        #if ( configENABLE_TRUSTZONE == 1 )
 
-            /*
-             * +----------+-----------------+------------------------------+-----+
-             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
-             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
-             * +----------+-----------------+------------------------------+-----+
-             *
-             * <---------><----------------><------------------------------><---->
-             *     8               8                      5                   1
-             */
-            #define MAX_CONTEXT_SIZE 22
+/*
+ * +----------+-----------------+------------------------------+-----+
+ * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+ * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+ * +----------+-----------------+------------------------------+-----+
+ *
+ * <---------><----------------><------------------------------><---->
+ *     8               8                      5                   1
+ */
+            #define MAX_CONTEXT_SIZE    22
 
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-            /*
-             * +----------+-----------------+----------------------+-----+
-             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
-             * |          | PC, xPSR        | EXC_RETURN           |     |
-             * +----------+-----------------+----------------------+-----+
-             *
-             * <---------><----------------><----------------------><---->
-             *     8               8                  4              1
-             */
-            #define MAX_CONTEXT_SIZE 21
+/*
+ * +----------+-----------------+----------------------+-----+
+ * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+ * |          | PC, xPSR        | EXC_RETURN           |     |
+ * +----------+-----------------+----------------------+-----+
+ *
+ * <---------><----------------><----------------------><---->
+ *     8               8                  4              1
+ */
+            #define MAX_CONTEXT_SIZE    21
 
         #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
 
     #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-    /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
-    #define portSTACK_FRAME_HAS_PADDING_FLAG     ( 1UL << 0UL )
-    #define portTASK_IS_PRIVILEGED_FLAG          ( 1UL << 1UL )
+/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
+    #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
+    #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
     typedef struct MPU_SETTINGS
     {
@@ -364,49 +364,49 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-    /**
-     * @brief Allocate a secure context for the task.
-     *
-     * Tasks are not created with a secure context. Any task that is going to call
-     * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
-     * secure context before it calls any secure function.
-     *
-     * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
-     */
+/**
+ * @brief Allocate a secure context for the task.
+ *
+ * Tasks are not created with a secure context. Any task that is going to call
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+ * secure context before it calls any secure function.
+ *
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+ */
     #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
 
-    /**
-     * @brief Called when a task is deleted to delete the task's secure context,
-     * if it has one.
-     *
-     * @param[in] pxTCB The TCB of the task being deleted.
-     */
+/**
+ * @brief Called when a task is deleted to delete the task's secure context,
+ * if it has one.
+ *
+ * @param[in] pxTCB The TCB of the task being deleted.
+ */
     #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
 #endif /* configENABLE_TRUSTZONE */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Checks whether or not the processor is privileged.
-     *
-     * @return 1 if the processor is already privileged, 0 otherwise.
-     */
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
     #define portIS_PRIVILEGED()      xIsPrivileged()
 
-    /**
-     * @brief Raise an SVC request to raise privilege.
-     *
-     * The SVC handler checks that the SVC was raised from a system call and only
-     * then it raises the privilege. If this is called from any other place,
-     * the privilege is not raised.
-     */
+/**
+ * @brief Raise an SVC request to raise privilege.
+ *
+ * The SVC handler checks that the SVC was raised from a system call and only
+ * then it raises the privilege. If this is called from any other place,
+ * the privilege is not raised.
+ */
     #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
 
-    /**
-     * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
-     * register.
-     */
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
     #define portRESET_PRIVILEGE()    vResetPrivilege()
 #else
     #define portIS_PRIVILEGED()
@@ -419,12 +419,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     extern BaseType_t xPortIsTaskPrivileged( void );
 
-    /**
-     * @brief Checks whether or not the calling task is privileged.
-     *
-     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
-     */
-    #define portIS_TASK_PRIVILEGED()      xPortIsTaskPrivileged()
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
+    #define portIS_TASK_PRIVILEGED()    xPortIsTaskPrivileged()
 
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
@@ -439,9 +439,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * based on whether or not Mainline extension is implemented. */
 #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
     #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
-        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
     #else
-        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    0
     #endif
 #endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
 
@@ -450,9 +450,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  */
 #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
 
-    /**
-     * @brief Count the number of leading zeros in a 32-bit value.
-     */
+/**
+ * @brief Count the number of leading zeros in a 32-bit value.
+ */
     static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
     {
         uint32_t ulReturn;
@@ -462,7 +462,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         return ulReturn;
     }
 
-    /* Check the configuration. */
+/* Check the configuration. */
     #if ( configMAX_PRIORITIES > 32 )
         #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
     #endif
@@ -471,16 +471,16 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection.  Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
     #endif
 
-    /**
-     * @brief Store/clear the ready priorities in a bit map.
-     */
-    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+/**
+ * @brief Store/clear the ready priorities in a bit map.
+ */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )      ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )       ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 
-    /**
-     * @brief Get the priority of the highest-priority task that is ready to execute.
-     */
-    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )   uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+/**
+ * @brief Get the priority of the highest-priority task that is ready to execute.
+ */
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
 
 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM3_MPU/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM3_MPU/mpu_wrappers_v2_asm.c
index 76c6029af..9a8cf55eb 100644
--- a/portable/GCC/ARM_CM3_MPU/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM3_MPU/mpu_wrappers_v2_asm.c
@@ -44,2274 +44,2274 @@
 
 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
 
-#if ( INCLUDE_xTaskDelayUntil == 1 )
+    #if ( INCLUDE_xTaskDelayUntil == 1 )
 
-BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
-                                const TickType_t xTimeIncrement ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
+                                        const TickType_t xTimeIncrement ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
-                                const TickType_t xTimeIncrement ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskDelayUntilImpl                       \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskDelayUntil_Unpriv                        \n"
-        " MPU_xTaskDelayUntil_Priv:                             \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskDelayUntilImpl                         \n"
-        " MPU_xTaskDelayUntil_Unpriv:                           \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskDelayUntilImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
+                                        const TickType_t xTimeIncrement ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskDelayUntilImpl                       \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskDelayUntil_Unpriv                        \n"
+                " MPU_xTaskDelayUntil_Priv:                             \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskDelayUntilImpl                         \n"
+                " MPU_xTaskDelayUntil_Unpriv:                           \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskDelayUntilImpl                        \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */
+    #endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_xTaskAbortDelay == 1 )
+    #if ( INCLUDE_xTaskAbortDelay == 1 )
 
-BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskAbortDelayImpl                       \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskAbortDelay_Unpriv                        \n"
-        " MPU_xTaskAbortDelay_Priv:                             \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskAbortDelayImpl                         \n"
-        " MPU_xTaskAbortDelay_Unpriv:                           \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskAbortDelayImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskAbortDelayImpl                       \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskAbortDelay_Unpriv                        \n"
+                " MPU_xTaskAbortDelay_Priv:                             \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskAbortDelayImpl                         \n"
+                " MPU_xTaskAbortDelay_Unpriv:                           \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskAbortDelayImpl                        \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */
+    #endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_vTaskDelay == 1 )
+    #if ( INCLUDE_vTaskDelay == 1 )
 
-void MPU_vTaskDelay( const TickType_t xTicksToDelay ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskDelay( const TickType_t xTicksToDelay ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskDelayImpl                            \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskDelay_Unpriv                             \n"
-        " MPU_vTaskDelay_Priv:                                  \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskDelayImpl                              \n"
-        " MPU_vTaskDelay_Unpriv:                                \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskDelayImpl                             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskDelayImpl                            \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskDelay_Unpriv                             \n"
+                " MPU_vTaskDelay_Priv:                                  \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskDelayImpl                              \n"
+                " MPU_vTaskDelay_Unpriv:                                \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskDelayImpl                             \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_vTaskDelay == 1 ) */
+    #endif /* if ( INCLUDE_vTaskDelay == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_uxTaskPriorityGet == 1 )
+    #if ( INCLUDE_uxTaskPriorityGet == 1 )
 
-UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskPriorityGetImpl                     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTaskPriorityGet_Unpriv                      \n"
-        " MPU_uxTaskPriorityGet_Priv:                           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTaskPriorityGetImpl                       \n"
-        " MPU_uxTaskPriorityGet_Unpriv:                         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskPriorityGetImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskPriorityGetImpl                     \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTaskPriorityGet_Unpriv                      \n"
+                " MPU_uxTaskPriorityGet_Priv:                           \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTaskPriorityGetImpl                       \n"
+                " MPU_uxTaskPriorityGet_Unpriv:                         \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskPriorityGetImpl                      \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */
+    #endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_eTaskGetState == 1 )
+    #if ( INCLUDE_eTaskGetState == 1 )
 
-eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_eTaskGetStateImpl                         \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_eTaskGetState_Unpriv                          \n"
-        " MPU_eTaskGetState_Priv:                               \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_eTaskGetStateImpl                           \n"
-        " MPU_eTaskGetState_Unpriv:                             \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_eTaskGetStateImpl                          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_eTaskGetStateImpl                         \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_eTaskGetState_Unpriv                          \n"
+                " MPU_eTaskGetState_Priv:                               \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_eTaskGetStateImpl                           \n"
+                " MPU_eTaskGetState_Unpriv:                             \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_eTaskGetStateImpl                          \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_eTaskGetState == 1 ) */
+    #endif /* if ( INCLUDE_eTaskGetState == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-void MPU_vTaskGetInfo( TaskHandle_t xTask,
-                       TaskStatus_t * pxTaskStatus,
-                       BaseType_t xGetFreeStackSpace,
-                       eTaskState eState ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskGetInfo( TaskHandle_t xTask,
+                               TaskStatus_t * pxTaskStatus,
+                               BaseType_t xGetFreeStackSpace,
+                               eTaskState eState ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskGetInfo( TaskHandle_t xTask,
-                       TaskStatus_t * pxTaskStatus,
-                       BaseType_t xGetFreeStackSpace,
-                       eTaskState eState ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskGetInfoImpl                          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskGetInfo_Unpriv                           \n"
-        " MPU_vTaskGetInfo_Priv:                                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskGetInfoImpl                            \n"
-        " MPU_vTaskGetInfo_Unpriv:                              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskGetInfoImpl                           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskGetInfo( TaskHandle_t xTask,
+                               TaskStatus_t * pxTaskStatus,
+                               BaseType_t xGetFreeStackSpace,
+                               eTaskState eState ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskGetInfoImpl                          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskGetInfo_Unpriv                           \n"
+                " MPU_vTaskGetInfo_Priv:                                \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskGetInfoImpl                            \n"
+                " MPU_vTaskGetInfo_Unpriv:                              \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskGetInfoImpl                           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
+    #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
+    #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
 
-TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetIdleTaskHandleImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGetIdleTaskHandle_Unpriv                 \n"
-        " MPU_xTaskGetIdleTaskHandle_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGetIdleTaskHandleImpl                  \n"
-        " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetIdleTaskHandleImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetIdleTaskHandleImpl                \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGetIdleTaskHandle_Unpriv                 \n"
+                " MPU_xTaskGetIdleTaskHandle_Priv:                      \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGetIdleTaskHandleImpl                  \n"
+                " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetIdleTaskHandleImpl                 \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */
+    #endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_vTaskSuspend == 1 )
+    #if ( INCLUDE_vTaskSuspend == 1 )
 
-void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSuspendImpl                          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskSuspend_Unpriv                           \n"
-        " MPU_vTaskSuspend_Priv:                                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskSuspendImpl                            \n"
-        " MPU_vTaskSuspend_Unpriv:                              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSuspendImpl                           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskSuspendImpl                          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskSuspend_Unpriv                           \n"
+                " MPU_vTaskSuspend_Priv:                                \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskSuspendImpl                            \n"
+                " MPU_vTaskSuspend_Unpriv:                              \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskSuspendImpl                           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
+    #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_vTaskSuspend == 1 )
+    #if ( INCLUDE_vTaskSuspend == 1 )
 
-void MPU_vTaskResume( TaskHandle_t xTaskToResume ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskResume( TaskHandle_t xTaskToResume ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskResumeImpl                           \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskResume_Unpriv                            \n"
-        " MPU_vTaskResume_Priv:                                 \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskResumeImpl                             \n"
-        " MPU_vTaskResume_Unpriv:                               \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskResumeImpl                            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskResumeImpl                           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskResume_Unpriv                            \n"
+                " MPU_vTaskResume_Priv:                                 \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskResumeImpl                             \n"
+                " MPU_vTaskResume_Unpriv:                               \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskResumeImpl                            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
+    #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
 /*-----------------------------------------------------------*/
 
-TickType_t MPU_xTaskGetTickCount( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    TickType_t MPU_xTaskGetTickCount( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TickType_t MPU_xTaskGetTickCount( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetTickCountImpl                     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGetTickCount_Unpriv                      \n"
-        " MPU_xTaskGetTickCount_Priv:                           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGetTickCountImpl                       \n"
-        " MPU_xTaskGetTickCount_Unpriv:                         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetTickCountImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    TickType_t MPU_xTaskGetTickCount( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xTaskGetTickCountImpl                     \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xTaskGetTickCount_Unpriv                      \n"
+            " MPU_xTaskGetTickCount_Priv:                           \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xTaskGetTickCountImpl                       \n"
+            " MPU_xTaskGetTickCount_Unpriv:                         \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xTaskGetTickCountImpl                      \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetNumberOfTasksImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTaskGetNumberOfTasks_Unpriv                 \n"
-        " MPU_uxTaskGetNumberOfTasks_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTaskGetNumberOfTasksImpl                  \n"
-        " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetNumberOfTasksImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_uxTaskGetNumberOfTasksImpl                \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_uxTaskGetNumberOfTasks_Unpriv                 \n"
+            " MPU_uxTaskGetNumberOfTasks_Priv:                      \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_uxTaskGetNumberOfTasksImpl                  \n"
+            " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_uxTaskGetNumberOfTasksImpl                 \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configGENERATE_RUN_TIME_STATS == 1 )
+    #if ( configGENERATE_RUN_TIME_STATS == 1 )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetRunTimeCounterImpl               \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGetRunTimeCounter_Unpriv                \n"
-        " MPU_ulTaskGetRunTimeCounter_Priv:                     \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGetRunTimeCounterImpl                 \n"
-        " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetRunTimeCounterImpl                \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetRunTimeCounterImpl               \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGetRunTimeCounter_Unpriv                \n"
+                " MPU_ulTaskGetRunTimeCounter_Priv:                     \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGetRunTimeCounterImpl                 \n"
+                " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetRunTimeCounterImpl                \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configGENERATE_RUN_TIME_STATS == 1 )
+    #if ( configGENERATE_RUN_TIME_STATS == 1 )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetRunTimePercentImpl               \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGetRunTimePercent_Unpriv                \n"
-        " MPU_ulTaskGetRunTimePercent_Priv:                     \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGetRunTimePercentImpl                 \n"
-        " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetRunTimePercentImpl                \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetRunTimePercentImpl               \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGetRunTimePercent_Unpriv                \n"
+                " MPU_ulTaskGetRunTimePercent_Priv:                     \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGetRunTimePercentImpl                 \n"
+                " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetRunTimePercentImpl                \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+    #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetIdleRunTimePercentImpl           \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv            \n"
-        " MPU_ulTaskGetIdleRunTimePercent_Priv:                 \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGetIdleRunTimePercentImpl             \n"
-        " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetIdleRunTimePercentImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetIdleRunTimePercentImpl           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv            \n"
+                " MPU_ulTaskGetIdleRunTimePercent_Priv:                 \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGetIdleRunTimePercentImpl             \n"
+                " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetIdleRunTimePercentImpl            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+    #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetIdleRunTimeCounterImpl           \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv            \n"
-        " MPU_ulTaskGetIdleRunTimeCounter_Priv:                 \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGetIdleRunTimeCounterImpl             \n"
-        " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetIdleRunTimeCounterImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetIdleRunTimeCounterImpl           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv            \n"
+                " MPU_ulTaskGetIdleRunTimeCounter_Priv:                 \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGetIdleRunTimeCounterImpl             \n"
+                " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetIdleRunTimeCounterImpl            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+    #if ( configUSE_APPLICATION_TASK_TAG == 1 )
 
-void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
-                                     TaskHookFunction_t pxHookFunction ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
+                                             TaskHookFunction_t pxHookFunction ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
-                                     TaskHookFunction_t pxHookFunction ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSetApplicationTaskTagImpl            \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskSetApplicationTaskTag_Unpriv             \n"
-        " MPU_vTaskSetApplicationTaskTag_Priv:                  \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskSetApplicationTaskTagImpl              \n"
-        " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSetApplicationTaskTagImpl             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
+                                             TaskHookFunction_t pxHookFunction ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskSetApplicationTaskTagImpl            \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskSetApplicationTaskTag_Unpriv             \n"
+                " MPU_vTaskSetApplicationTaskTag_Priv:                  \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskSetApplicationTaskTagImpl              \n"
+                " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskSetApplicationTaskTagImpl             \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
+    #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+    #if ( configUSE_APPLICATION_TASK_TAG == 1 )
 
-TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetApplicationTaskTagImpl            \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGetApplicationTaskTag_Unpriv             \n"
-        " MPU_xTaskGetApplicationTaskTag_Priv:                  \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGetApplicationTaskTagImpl              \n"
-        " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetApplicationTaskTagImpl             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetApplicationTaskTagImpl            \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGetApplicationTaskTag_Unpriv             \n"
+                " MPU_xTaskGetApplicationTaskTag_Priv:                  \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGetApplicationTaskTagImpl              \n"
+                " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetApplicationTaskTagImpl             \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
+    #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+    #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
 
-void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
-                                            BaseType_t xIndex,
-                                            void * pvValue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
+                                                    BaseType_t xIndex,
+                                                    void * pvValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
-                                            BaseType_t xIndex,
-                                            void * pvValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSetThreadLocalStoragePointerImpl     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv      \n"
-        " MPU_vTaskSetThreadLocalStoragePointer_Priv:           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskSetThreadLocalStoragePointerImpl       \n"
-        " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSetThreadLocalStoragePointerImpl      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
+                                                    BaseType_t xIndex,
+                                                    void * pvValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskSetThreadLocalStoragePointerImpl     \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv      \n"
+                " MPU_vTaskSetThreadLocalStoragePointer_Priv:           \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskSetThreadLocalStoragePointerImpl       \n"
+                " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskSetThreadLocalStoragePointerImpl      \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
+    #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+    #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
 
-void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
-                                               BaseType_t xIndex ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
+                                                       BaseType_t xIndex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
-                                               BaseType_t xIndex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pvTaskGetThreadLocalStoragePointerImpl    \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv     \n"
-        " MPU_pvTaskGetThreadLocalStoragePointer_Priv:          \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_pvTaskGetThreadLocalStoragePointerImpl      \n"
-        " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pvTaskGetThreadLocalStoragePointerImpl     \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
+                                                       BaseType_t xIndex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pvTaskGetThreadLocalStoragePointerImpl    \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv     \n"
+                " MPU_pvTaskGetThreadLocalStoragePointer_Priv:          \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_pvTaskGetThreadLocalStoragePointerImpl      \n"
+                " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pvTaskGetThreadLocalStoragePointerImpl     \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
+    #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
-                                      const UBaseType_t uxArraySize,
-                                      configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
+                                              const UBaseType_t uxArraySize,
+                                              configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
-                                      const UBaseType_t uxArraySize,
-                                      configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetSystemStateImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTaskGetSystemState_Unpriv                   \n"
-        " MPU_uxTaskGetSystemState_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTaskGetSystemStateImpl                    \n"
-        " MPU_uxTaskGetSystemState_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetSystemStateImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
+                                              const UBaseType_t uxArraySize,
+                                              configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskGetSystemStateImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTaskGetSystemState_Unpriv                   \n"
+                " MPU_uxTaskGetSystemState_Priv:                        \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTaskGetSystemStateImpl                    \n"
+                " MPU_uxTaskGetSystemState_Unpriv:                      \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskGetSystemStateImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
+    #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
+    #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
 
-UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetStackHighWaterMarkImpl           \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTaskGetStackHighWaterMark_Unpriv            \n"
-        " MPU_uxTaskGetStackHighWaterMark_Priv:                 \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTaskGetStackHighWaterMarkImpl             \n"
-        " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetStackHighWaterMarkImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskGetStackHighWaterMarkImpl           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTaskGetStackHighWaterMark_Unpriv            \n"
+                " MPU_uxTaskGetStackHighWaterMark_Priv:                 \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTaskGetStackHighWaterMarkImpl             \n"
+                " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskGetStackHighWaterMarkImpl            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */
+    #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
+    #if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
 
-configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetStackHighWaterMark2Impl          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv           \n"
-        " MPU_uxTaskGetStackHighWaterMark2_Priv:                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTaskGetStackHighWaterMark2Impl            \n"
-        " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetStackHighWaterMark2Impl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskGetStackHighWaterMark2Impl          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv           \n"
+                " MPU_uxTaskGetStackHighWaterMark2_Priv:                \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTaskGetStackHighWaterMark2Impl            \n"
+                " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskGetStackHighWaterMark2Impl           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */
+    #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
+    #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
 
-TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetCurrentTaskHandleImpl             \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGetCurrentTaskHandle_Unpriv              \n"
-        " MPU_xTaskGetCurrentTaskHandle_Priv:                   \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGetCurrentTaskHandleImpl               \n"
-        " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetCurrentTaskHandleImpl              \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetCurrentTaskHandleImpl             \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGetCurrentTaskHandle_Unpriv              \n"
+                " MPU_xTaskGetCurrentTaskHandle_Priv:                   \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGetCurrentTaskHandleImpl               \n"
+                " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetCurrentTaskHandleImpl              \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
+    #endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_xTaskGetSchedulerState == 1 )
+    #if ( INCLUDE_xTaskGetSchedulerState == 1 )
 
-BaseType_t MPU_xTaskGetSchedulerState( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGetSchedulerState( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGetSchedulerState( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetSchedulerStateImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGetSchedulerState_Unpriv                 \n"
-        " MPU_xTaskGetSchedulerState_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGetSchedulerStateImpl                  \n"
-        " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetSchedulerStateImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGetSchedulerState( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetSchedulerStateImpl                \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGetSchedulerState_Unpriv                 \n"
+                " MPU_xTaskGetSchedulerState_Priv:                      \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGetSchedulerStateImpl                  \n"
+                " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetSchedulerStateImpl                 \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */
+    #endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */
 /*-----------------------------------------------------------*/
 
-void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSetTimeOutStateImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskSetTimeOutState_Unpriv                   \n"
-        " MPU_vTaskSetTimeOutState_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskSetTimeOutStateImpl                    \n"
-        " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSetTimeOutStateImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_vTaskSetTimeOutStateImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_vTaskSetTimeOutState_Unpriv                   \n"
+            " MPU_vTaskSetTimeOutState_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_vTaskSetTimeOutStateImpl                    \n"
+            " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_vTaskSetTimeOutStateImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
-                                     TickType_t * const pxTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
+                                         TickType_t * const pxTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
-                                     TickType_t * const pxTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskCheckForTimeOutImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskCheckForTimeOut_Unpriv                   \n"
-        " MPU_xTaskCheckForTimeOut_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskCheckForTimeOutImpl                    \n"
-        " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskCheckForTimeOutImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
+                                         TickType_t * const pxTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xTaskCheckForTimeOutImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xTaskCheckForTimeOut_Unpriv                   \n"
+            " MPU_xTaskCheckForTimeOut_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xTaskCheckForTimeOutImpl                    \n"
+            " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xTaskCheckForTimeOutImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                   UBaseType_t uxIndexToNotify,
-                                   uint32_t ulValue,
-                                   eNotifyAction eAction,
-                                   uint32_t * pulPreviousNotificationValue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
+                                           UBaseType_t uxIndexToNotify,
+                                           uint32_t ulValue,
+                                           eNotifyAction eAction,
+                                           uint32_t * pulPreviousNotificationValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                   UBaseType_t uxIndexToNotify,
-                                   uint32_t ulValue,
-                                   eNotifyAction eAction,
-                                   uint32_t * pulPreviousNotificationValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGenericNotifyImpl                    \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGenericNotify_Unpriv                     \n"
-        " MPU_xTaskGenericNotify_Priv:                          \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGenericNotifyImpl                      \n"
-        " MPU_xTaskGenericNotify_Unpriv:                        \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGenericNotifyImpl                     \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
+                                           UBaseType_t uxIndexToNotify,
+                                           uint32_t ulValue,
+                                           eNotifyAction eAction,
+                                           uint32_t * pulPreviousNotificationValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGenericNotifyImpl                    \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGenericNotify_Unpriv                     \n"
+                " MPU_xTaskGenericNotify_Priv:                          \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGenericNotifyImpl                      \n"
+                " MPU_xTaskGenericNotify_Unpriv:                        \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGenericNotifyImpl                     \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                       uint32_t ulBitsToClearOnEntry,
-                                       uint32_t ulBitsToClearOnExit,
-                                       uint32_t * pulNotificationValue,
-                                       TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
+                                               uint32_t ulBitsToClearOnEntry,
+                                               uint32_t ulBitsToClearOnExit,
+                                               uint32_t * pulNotificationValue,
+                                               TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                       uint32_t ulBitsToClearOnEntry,
-                                       uint32_t ulBitsToClearOnExit,
-                                       uint32_t * pulNotificationValue,
-                                       TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGenericNotifyWaitImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGenericNotifyWait_Unpriv                 \n"
-        " MPU_xTaskGenericNotifyWait_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGenericNotifyWaitImpl                  \n"
-        " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGenericNotifyWaitImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
+                                               uint32_t ulBitsToClearOnEntry,
+                                               uint32_t ulBitsToClearOnExit,
+                                               uint32_t * pulNotificationValue,
+                                               TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGenericNotifyWaitImpl                \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGenericNotifyWait_Unpriv                 \n"
+                " MPU_xTaskGenericNotifyWait_Priv:                      \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGenericNotifyWaitImpl                  \n"
+                " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGenericNotifyWaitImpl                 \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
-                                      BaseType_t xClearCountOnExit,
-                                      TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
+                                              BaseType_t xClearCountOnExit,
+                                              TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
-                                      BaseType_t xClearCountOnExit,
-                                      TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGenericNotifyTakeImpl               \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGenericNotifyTake_Unpriv                \n"
-        " MPU_ulTaskGenericNotifyTake_Priv:                     \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGenericNotifyTakeImpl                 \n"
-        " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGenericNotifyTakeImpl                \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
+                                              BaseType_t xClearCountOnExit,
+                                              TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGenericNotifyTakeImpl               \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGenericNotifyTake_Unpriv                \n"
+                " MPU_ulTaskGenericNotifyTake_Priv:                     \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGenericNotifyTakeImpl                 \n"
+                " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGenericNotifyTakeImpl                \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
-                                             UBaseType_t uxIndexToClear ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
+                                                     UBaseType_t uxIndexToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
-                                             UBaseType_t uxIndexToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGenericNotifyStateClearImpl          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGenericNotifyStateClear_Unpriv           \n"
-        " MPU_xTaskGenericNotifyStateClear_Priv:                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGenericNotifyStateClearImpl            \n"
-        " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGenericNotifyStateClearImpl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
+                                                     UBaseType_t uxIndexToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGenericNotifyStateClearImpl          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGenericNotifyStateClear_Unpriv           \n"
+                " MPU_xTaskGenericNotifyStateClear_Priv:                \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGenericNotifyStateClearImpl            \n"
+                " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGenericNotifyStateClearImpl           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
-                                            UBaseType_t uxIndexToClear,
-                                            uint32_t ulBitsToClear ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
+                                                    UBaseType_t uxIndexToClear,
+                                                    uint32_t ulBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
-                                            UBaseType_t uxIndexToClear,
-                                            uint32_t ulBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGenericNotifyValueClearImpl         \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGenericNotifyValueClear_Unpriv          \n"
-        " MPU_ulTaskGenericNotifyValueClear_Priv:               \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGenericNotifyValueClearImpl           \n"
-        " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGenericNotifyValueClearImpl          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
+                                                    UBaseType_t uxIndexToClear,
+                                                    uint32_t ulBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGenericNotifyValueClearImpl         \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGenericNotifyValueClear_Unpriv          \n"
+                " MPU_ulTaskGenericNotifyValueClear_Priv:               \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGenericNotifyValueClearImpl           \n"
+                " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGenericNotifyValueClearImpl          \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
-                                  const void * const pvItemToQueue,
-                                  TickType_t xTicksToWait,
-                                  const BaseType_t xCopyPosition ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
+                                      const void * const pvItemToQueue,
+                                      TickType_t xTicksToWait,
+                                      const BaseType_t xCopyPosition ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
-                                  const void * const pvItemToQueue,
-                                  TickType_t xTicksToWait,
-                                  const BaseType_t xCopyPosition ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueGenericSendImpl                     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueGenericSend_Unpriv                      \n"
-        " MPU_xQueueGenericSend_Priv:                           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueGenericSendImpl                       \n"
-        " MPU_xQueueGenericSend_Unpriv:                         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueGenericSendImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
+                                      const void * const pvItemToQueue,
+                                      TickType_t xTicksToWait,
+                                      const BaseType_t xCopyPosition ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueueGenericSendImpl                     \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xQueueGenericSend_Unpriv                      \n"
+            " MPU_xQueueGenericSend_Priv:                           \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xQueueGenericSendImpl                       \n"
+            " MPU_xQueueGenericSend_Unpriv:                         \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueueGenericSendImpl                      \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxQueueMessagesWaitingImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxQueueMessagesWaiting_Unpriv                 \n"
-        " MPU_uxQueueMessagesWaiting_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxQueueMessagesWaitingImpl                  \n"
-        " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxQueueMessagesWaitingImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_uxQueueMessagesWaitingImpl                \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_uxQueueMessagesWaiting_Unpriv                 \n"
+            " MPU_uxQueueMessagesWaiting_Priv:                      \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_uxQueueMessagesWaitingImpl                  \n"
+            " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_uxQueueMessagesWaitingImpl                 \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxQueueSpacesAvailableImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxQueueSpacesAvailable_Unpriv                 \n"
-        " MPU_uxQueueSpacesAvailable_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxQueueSpacesAvailableImpl                  \n"
-        " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxQueueSpacesAvailableImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_uxQueueSpacesAvailableImpl                \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_uxQueueSpacesAvailable_Unpriv                 \n"
+            " MPU_uxQueueSpacesAvailable_Priv:                      \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_uxQueueSpacesAvailableImpl                  \n"
+            " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_uxQueueSpacesAvailableImpl                 \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
-                              void * const pvBuffer,
-                              TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
+                                  void * const pvBuffer,
+                                  TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
-                              void * const pvBuffer,
-                              TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueReceiveImpl                         \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueReceive_Unpriv                          \n"
-        " MPU_xQueueReceive_Priv:                               \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueReceiveImpl                           \n"
-        " MPU_xQueueReceive_Unpriv:                             \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueReceiveImpl                          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
+                                  void * const pvBuffer,
+                                  TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueueReceiveImpl                         \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xQueueReceive_Unpriv                          \n"
+            " MPU_xQueueReceive_Priv:                               \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xQueueReceiveImpl                           \n"
+            " MPU_xQueueReceive_Unpriv:                             \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueueReceiveImpl                          \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
-                           void * const pvBuffer,
-                           TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
+                               void * const pvBuffer,
+                               TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
-                           void * const pvBuffer,
-                           TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueuePeekImpl                            \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueuePeek_Unpriv                             \n"
-        " MPU_xQueuePeek_Priv:                                  \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueuePeekImpl                              \n"
-        " MPU_xQueuePeek_Unpriv:                                \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueuePeekImpl                             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
+                               void * const pvBuffer,
+                               TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueuePeekImpl                            \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xQueuePeek_Unpriv                             \n"
+            " MPU_xQueuePeek_Priv:                                  \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xQueuePeekImpl                              \n"
+            " MPU_xQueuePeek_Unpriv:                                \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueuePeekImpl                             \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
-                                    TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
+                                        TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
-                                    TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueSemaphoreTakeImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueSemaphoreTake_Unpriv                    \n"
-        " MPU_xQueueSemaphoreTake_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueSemaphoreTakeImpl                     \n"
-        " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueSemaphoreTakeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
+                                        TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueueSemaphoreTakeImpl                   \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xQueueSemaphoreTake_Unpriv                    \n"
+            " MPU_xQueueSemaphoreTake_Priv:                         \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xQueueSemaphoreTakeImpl                     \n"
+            " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueueSemaphoreTakeImpl                    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+    #if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
 
-TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueGetMutexHolderImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueGetMutexHolder_Unpriv                   \n"
-        " MPU_xQueueGetMutexHolder_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueGetMutexHolderImpl                    \n"
-        " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueGetMutexHolderImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueGetMutexHolderImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueGetMutexHolder_Unpriv                   \n"
+                " MPU_xQueueGetMutexHolder_Priv:                        \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueGetMutexHolderImpl                    \n"
+                " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueGetMutexHolderImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */
+    #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+    #if ( configUSE_RECURSIVE_MUTEXES == 1 )
 
-BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
-                                         TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+                                                 TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+        BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+                                                 TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueTakeMutexRecursiveImpl              \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueTakeMutexRecursive_Unpriv               \n"
+                " MPU_xQueueTakeMutexRecursive_Priv:                    \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueTakeMutexRecursiveImpl                \n"
+                " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueTakeMutexRecursiveImpl               \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_RECURSIVE_MUTEXES == 1 )
+
+        BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueGiveMutexRecursiveImpl              \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueGiveMutexRecursive_Unpriv               \n"
+                " MPU_xQueueGiveMutexRecursive_Priv:                    \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueGiveMutexRecursiveImpl                \n"
+                " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueGiveMutexRecursiveImpl               \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_QUEUE_SETS == 1 )
+
+        QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
+                                                        const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
+                                                        const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueSelectFromSetImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueSelectFromSet_Unpriv                    \n"
+                " MPU_xQueueSelectFromSet_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueSelectFromSetImpl                     \n"
+                " MPU_xQueueSelectFromSet_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueSelectFromSetImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_QUEUE_SETS == 1 )
+
+        BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                                       QueueSetHandle_t xQueueSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                                       QueueSetHandle_t xQueueSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueAddToSetImpl                        \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueAddToSet_Unpriv                         \n"
+                " MPU_xQueueAddToSet_Priv:                              \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueAddToSetImpl                          \n"
+                " MPU_xQueueAddToSet_Unpriv:                            \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueAddToSetImpl                         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+        void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
+                                      const char * pcName ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
+                                      const char * pcName ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vQueueAddToRegistryImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vQueueAddToRegistry_Unpriv                    \n"
+                " MPU_vQueueAddToRegistry_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vQueueAddToRegistryImpl                     \n"
+                " MPU_vQueueAddToRegistry_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vQueueAddToRegistryImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+        void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vQueueUnregisterQueueImpl                 \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vQueueUnregisterQueue_Unpriv                  \n"
+                " MPU_vQueueUnregisterQueue_Priv:                       \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vQueueUnregisterQueueImpl                   \n"
+                " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vQueueUnregisterQueueImpl                  \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+        const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pcQueueGetNameImpl                        \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_pcQueueGetName_Unpriv                         \n"
+                " MPU_pcQueueGetName_Priv:                              \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_pcQueueGetNameImpl                          \n"
+                " MPU_pcQueueGetName_Unpriv:                            \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pcQueueGetNameImpl                         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pvTimerGetTimerIDImpl                     \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_pvTimerGetTimerID_Unpriv                      \n"
+                " MPU_pvTimerGetTimerID_Priv:                           \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_pvTimerGetTimerIDImpl                       \n"
+                " MPU_pvTimerGetTimerID_Unpriv:                         \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pvTimerGetTimerIDImpl                      \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
+                                   void * pvNewID ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
+                                   void * pvNewID ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTimerSetTimerIDImpl                      \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTimerSetTimerID_Unpriv                       \n"
+                " MPU_vTimerSetTimerID_Priv:                            \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTimerSetTimerIDImpl                        \n"
+                " MPU_vTimerSetTimerID_Unpriv:                          \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTimerSetTimerIDImpl                       \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerIsTimerActiveImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerIsTimerActive_Unpriv                    \n"
+                " MPU_xTimerIsTimerActive_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerIsTimerActiveImpl                     \n"
+                " MPU_xTimerIsTimerActive_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerIsTimerActiveImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetTimerDaemonTaskHandleImpl        \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv         \n"
+                " MPU_xTimerGetTimerDaemonTaskHandle_Priv:              \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerGetTimerDaemonTaskHandleImpl          \n"
+                " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetTimerDaemonTaskHandleImpl         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                                     const BaseType_t xCommandID,
+                                                     const TickType_t xOptionalValue,
+                                                     BaseType_t * const pxHigherPriorityTaskWoken,
+                                                     const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                                     const BaseType_t xCommandID,
+                                                     const TickType_t xOptionalValue,
+                                                     BaseType_t * const pxHigherPriorityTaskWoken,
+                                                     const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                               \n"
+                " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
+                "                                                               \n"
+                " push {r0}                                                     \n"
+                " mrs r0, control                                               \n"
+                " tst r0, #1                                                    \n"
+                " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
+                " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
+                "     pop {r0}                                                  \n"
+                "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
+                " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
+                "     pop {r0}                                                  \n"
+                "     svc %0                                                    \n"
+                "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
+                "     svc %1                                                    \n"
+                "     bx lr                                                     \n"
+                "                                                               \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pcTimerGetNameImpl                        \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_pcTimerGetName_Unpriv                         \n"
+                " MPU_pcTimerGetName_Priv:                              \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_pcTimerGetNameImpl                          \n"
+                " MPU_pcTimerGetName_Unpriv:                            \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pcTimerGetNameImpl                         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
+                                      const BaseType_t uxAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
+                                      const BaseType_t uxAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTimerSetReloadModeImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTimerSetReloadMode_Unpriv                    \n"
+                " MPU_vTimerSetReloadMode_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTimerSetReloadModeImpl                     \n"
+                " MPU_vTimerSetReloadMode_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTimerSetReloadModeImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetReloadModeImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerGetReloadMode_Unpriv                    \n"
+                " MPU_xTimerGetReloadMode_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerGetReloadModeImpl                     \n"
+                " MPU_xTimerGetReloadMode_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetReloadModeImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTimerGetReloadModeImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTimerGetReloadMode_Unpriv                   \n"
+                " MPU_uxTimerGetReloadMode_Priv:                        \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTimerGetReloadModeImpl                    \n"
+                " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTimerGetReloadModeImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetPeriodImpl                       \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerGetPeriod_Unpriv                        \n"
+                " MPU_xTimerGetPeriod_Priv:                             \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerGetPeriodImpl                         \n"
+                " MPU_xTimerGetPeriod_Unpriv:                           \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetPeriodImpl                        \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetExpiryTimeImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerGetExpiryTime_Unpriv                    \n"
+                " MPU_xTimerGetExpiryTime_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerGetExpiryTimeImpl                     \n"
+                " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetExpiryTimeImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         const BaseType_t xClearOnExit,
+                                         const BaseType_t xWaitForAllBits,
+                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         const BaseType_t xClearOnExit,
+                                         const BaseType_t xWaitForAllBits,
                                          TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueTakeMutexRecursiveImpl              \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueTakeMutexRecursive_Unpriv               \n"
-        " MPU_xQueueTakeMutexRecursive_Priv:                    \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueTakeMutexRecursiveImpl                \n"
-        " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueTakeMutexRecursiveImpl               \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupWaitBitsImpl                   \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
+            " MPU_xEventGroupWaitBits_Priv:                         \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xEventGroupWaitBitsImpl                     \n"
+            " MPU_xEventGroupWaitBits_Unpriv:                       \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupWaitBitsImpl                    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                          const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueGiveMutexRecursiveImpl              \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueGiveMutexRecursive_Unpriv               \n"
-        " MPU_xQueueGiveMutexRecursive_Priv:                    \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueGiveMutexRecursiveImpl                \n"
-        " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueGiveMutexRecursiveImpl               \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                          const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupClearBitsImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xEventGroupClearBits_Unpriv                   \n"
+            " MPU_xEventGroupClearBits_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xEventGroupClearBitsImpl                    \n"
+            " MPU_xEventGroupClearBits_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupClearBitsImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_QUEUE_SETS == 1 )
+    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                        const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
-                                                const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
-                                                const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueSelectFromSetImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueSelectFromSet_Unpriv                    \n"
-        " MPU_xQueueSelectFromSet_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueSelectFromSetImpl                     \n"
-        " MPU_xQueueSelectFromSet_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueSelectFromSetImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                        const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupSetBitsImpl                    \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xEventGroupSetBits_Unpriv                     \n"
+            " MPU_xEventGroupSetBits_Priv:                          \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xEventGroupSetBitsImpl                      \n"
+            " MPU_xEventGroupSetBits_Unpriv:                        \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupSetBitsImpl                     \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_QUEUE_SETS == 1 )
-
-BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
-                               QueueSetHandle_t xQueueSet ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
-                               QueueSetHandle_t xQueueSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueAddToSetImpl                        \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueAddToSet_Unpriv                         \n"
-        " MPU_xQueueAddToSet_Priv:                              \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueAddToSetImpl                          \n"
-        " MPU_xQueueAddToSet_Unpriv:                            \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueAddToSetImpl                         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_QUEUE_SETS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
-                              const char * pcName ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
-                              const char * pcName ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vQueueAddToRegistryImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vQueueAddToRegistry_Unpriv                    \n"
-        " MPU_vQueueAddToRegistry_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vQueueAddToRegistryImpl                     \n"
-        " MPU_vQueueAddToRegistry_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vQueueAddToRegistryImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vQueueUnregisterQueueImpl                 \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vQueueUnregisterQueue_Unpriv                  \n"
-        " MPU_vQueueUnregisterQueue_Priv:                       \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vQueueUnregisterQueueImpl                   \n"
-        " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vQueueUnregisterQueueImpl                  \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pcQueueGetNameImpl                        \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_pcQueueGetName_Unpriv                         \n"
-        " MPU_pcQueueGetName_Priv:                              \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_pcQueueGetNameImpl                          \n"
-        " MPU_pcQueueGetName_Unpriv:                            \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pcQueueGetNameImpl                         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pvTimerGetTimerIDImpl                     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_pvTimerGetTimerID_Unpriv                      \n"
-        " MPU_pvTimerGetTimerID_Priv:                           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_pvTimerGetTimerIDImpl                       \n"
-        " MPU_pvTimerGetTimerID_Unpriv:                         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pvTimerGetTimerIDImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
-                           void * pvNewID ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
-                           void * pvNewID ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTimerSetTimerIDImpl                      \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTimerSetTimerID_Unpriv                       \n"
-        " MPU_vTimerSetTimerID_Priv:                            \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTimerSetTimerIDImpl                        \n"
-        " MPU_vTimerSetTimerID_Unpriv:                          \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTimerSetTimerIDImpl                       \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerIsTimerActiveImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTimerIsTimerActive_Unpriv                    \n"
-        " MPU_xTimerIsTimerActive_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerIsTimerActiveImpl                     \n"
-        " MPU_xTimerIsTimerActive_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerIsTimerActiveImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetTimerDaemonTaskHandleImpl        \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv         \n"
-        " MPU_xTimerGetTimerDaemonTaskHandle_Priv:              \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerGetTimerDaemonTaskHandleImpl          \n"
-        " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetTimerDaemonTaskHandleImpl         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                             const BaseType_t xCommandID,
-                                             const TickType_t xOptionalValue,
-                                             BaseType_t * const pxHigherPriorityTaskWoken,
-                                             const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                             const BaseType_t xCommandID,
-                                             const TickType_t xOptionalValue,
-                                             BaseType_t * const pxHigherPriorityTaskWoken,
-                                             const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                               \n"
-        " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
-        "                                                               \n"
-        " push {r0}                                                     \n"
-        " mrs r0, control                                               \n"
-        " tst r0, #1                                                    \n"
-        " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
-        " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
-        "     pop {r0}                                                  \n"
-        "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
-        " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
-        "     pop {r0}                                                  \n"
-        "     svc %0                                                    \n"
-        "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
-        "     svc %1                                                    \n"
-        "     bx lr                                                     \n"
-        "                                                               \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pcTimerGetNameImpl                        \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_pcTimerGetName_Unpriv                         \n"
-        " MPU_pcTimerGetName_Priv:                              \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_pcTimerGetNameImpl                          \n"
-        " MPU_pcTimerGetName_Unpriv:                            \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pcTimerGetNameImpl                         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                              const BaseType_t uxAutoReload ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                              const BaseType_t uxAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTimerSetReloadModeImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTimerSetReloadMode_Unpriv                    \n"
-        " MPU_vTimerSetReloadMode_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTimerSetReloadModeImpl                     \n"
-        " MPU_vTimerSetReloadMode_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTimerSetReloadModeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetReloadModeImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTimerGetReloadMode_Unpriv                    \n"
-        " MPU_xTimerGetReloadMode_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerGetReloadModeImpl                     \n"
-        " MPU_xTimerGetReloadMode_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetReloadModeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTimerGetReloadModeImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTimerGetReloadMode_Unpriv                   \n"
-        " MPU_uxTimerGetReloadMode_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTimerGetReloadModeImpl                    \n"
-        " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTimerGetReloadModeImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetPeriodImpl                       \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTimerGetPeriod_Unpriv                        \n"
-        " MPU_xTimerGetPeriod_Priv:                             \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerGetPeriodImpl                         \n"
-        " MPU_xTimerGetPeriod_Unpriv:                           \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetPeriodImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetExpiryTimeImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTimerGetExpiryTime_Unpriv                    \n"
-        " MPU_xTimerGetExpiryTime_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerGetExpiryTimeImpl                     \n"
-        " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetExpiryTimeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                     const EventBits_t uxBitsToSet,
                                      const EventBits_t uxBitsToWaitFor,
-                                     const BaseType_t xClearOnExit,
-                                     const BaseType_t xWaitForAllBits,
-                                     TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                     const EventBits_t uxBitsToSet,
                                      const EventBits_t uxBitsToWaitFor,
-                                     const BaseType_t xClearOnExit,
-                                     const BaseType_t xWaitForAllBits,
                                      TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupWaitBitsImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
-        " MPU_xEventGroupWaitBits_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xEventGroupWaitBitsImpl                     \n"
-        " MPU_xEventGroupWaitBits_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupWaitBitsImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupSyncImpl                       \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xEventGroupSync_Unpriv                        \n"
+            " MPU_xEventGroupSync_Priv:                             \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xEventGroupSyncImpl                         \n"
+            " MPU_xEventGroupSync_Unpriv:                           \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupSyncImpl                        \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                      const EventBits_t uxBitsToClear ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                      const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupClearBitsImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xEventGroupClearBits_Unpriv                   \n"
-        " MPU_xEventGroupClearBits_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xEventGroupClearBitsImpl                    \n"
-        " MPU_xEventGroupClearBits_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupClearBitsImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxEventGroupGetNumberImpl                 \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxEventGroupGetNumber_Unpriv                  \n"
+                " MPU_uxEventGroupGetNumber_Priv:                       \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxEventGroupGetNumberImpl                   \n"
+                " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxEventGroupGetNumberImpl                  \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
 /*-----------------------------------------------------------*/
 
-EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                    const EventBits_t uxBitsToSet ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                    const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupSetBitsImpl                    \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xEventGroupSetBits_Unpriv                     \n"
-        " MPU_xEventGroupSetBits_Priv:                          \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xEventGroupSetBitsImpl                      \n"
-        " MPU_xEventGroupSetBits_Unpriv:                        \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupSetBitsImpl                     \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vEventGroupSetNumber( void * xEventGroup,
+                                       UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vEventGroupSetNumber( void * xEventGroup,
+                                       UBaseType_t uxEventGroupNumber ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vEventGroupSetNumberImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vEventGroupSetNumber_Unpriv                   \n"
+                " MPU_vEventGroupSetNumber_Priv:                        \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vEventGroupSetNumberImpl                    \n"
+                " MPU_vEventGroupSetNumber_Unpriv:                      \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vEventGroupSetNumberImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
 /*-----------------------------------------------------------*/
 
-EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                 const EventBits_t uxBitsToSet,
-                                 const EventBits_t uxBitsToWaitFor,
-                                 TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                  const void * pvTxData,
+                                  size_t xDataLengthBytes,
+                                  TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                 const EventBits_t uxBitsToSet,
-                                 const EventBits_t uxBitsToWaitFor,
-                                 TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupSyncImpl                       \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xEventGroupSync_Unpriv                        \n"
-        " MPU_xEventGroupSync_Priv:                             \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xEventGroupSyncImpl                         \n"
-        " MPU_xEventGroupSync_Unpriv:                           \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupSyncImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                  const void * pvTxData,
+                                  size_t xDataLengthBytes,
+                                  TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferSendImpl                     \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferSend_Unpriv                      \n"
+            " MPU_xStreamBufferSend_Priv:                           \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferSendImpl                       \n"
+            " MPU_xStreamBufferSend_Unpriv:                         \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferSendImpl                      \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                     void * pvRxData,
+                                     size_t xBufferLengthBytes,
+                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxEventGroupGetNumberImpl                 \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxEventGroupGetNumber_Unpriv                  \n"
-        " MPU_uxEventGroupGetNumber_Priv:                       \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxEventGroupGetNumberImpl                   \n"
-        " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxEventGroupGetNumberImpl                  \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                     void * pvRxData,
+                                     size_t xBufferLengthBytes,
+                                     TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferReceiveImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferReceive_Unpriv                   \n"
+            " MPU_xStreamBufferReceive_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferReceiveImpl                    \n"
+            " MPU_xStreamBufferReceive_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferReceiveImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vEventGroupSetNumber( void * xEventGroup,
-                               UBaseType_t uxEventGroupNumber ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vEventGroupSetNumber( void * xEventGroup,
-                               UBaseType_t uxEventGroupNumber ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vEventGroupSetNumberImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vEventGroupSetNumber_Unpriv                   \n"
-        " MPU_vEventGroupSetNumber_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vEventGroupSetNumberImpl                    \n"
-        " MPU_vEventGroupSetNumber_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vEventGroupSetNumberImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferIsFullImpl                   \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
+            " MPU_xStreamBufferIsFull_Priv:                         \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferIsFullImpl                     \n"
+            " MPU_xStreamBufferIsFull_Unpriv:                       \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferIsFullImpl                    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                              const void * pvTxData,
-                              size_t xDataLengthBytes,
-                              TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                              const void * pvTxData,
-                              size_t xDataLengthBytes,
-                              TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferSendImpl                     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferSend_Unpriv                      \n"
-        " MPU_xStreamBufferSend_Priv:                           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferSendImpl                       \n"
-        " MPU_xStreamBufferSend_Unpriv:                         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferSendImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
+            " MPU_xStreamBufferIsEmpty_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferIsEmptyImpl                    \n"
+            " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferIsEmptyImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                 void * pvRxData,
-                                 size_t xBufferLengthBytes,
-                                 TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                 void * pvRxData,
-                                 size_t xBufferLengthBytes,
-                                 TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferReceiveImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferReceive_Unpriv                   \n"
-        " MPU_xStreamBufferReceive_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferReceiveImpl                    \n"
-        " MPU_xStreamBufferReceive_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferReceiveImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
+            " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
+            " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferSpacesAvailableImpl           \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferIsFullImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
-        " MPU_xStreamBufferIsFull_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferIsFullImpl                     \n"
-        " MPU_xStreamBufferIsFull_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferIsFullImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
+            " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferBytesAvailableImpl             \n"
+            " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferBytesAvailableImpl            \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                 size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
-        " MPU_xStreamBufferIsEmpty_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferIsEmptyImpl                    \n"
-        " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferIsEmptyImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                 size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
+            " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
+            " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferSetTriggerLevelImpl           \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
-        " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
-        " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferSpacesAvailableImpl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
-size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
-        " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferBytesAvailableImpl             \n"
-        " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferBytesAvailableImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                             size_t xTriggerLevel ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                             size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
-        " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
-        " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferSetTriggerLevelImpl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
-size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
-        " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
-        " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferNextMessageLengthBytesImpl    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
+            " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
+            " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferNextMessageLengthBytesImpl    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
 #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
diff --git a/portable/GCC/ARM_CM3_MPU/port.c b/portable/GCC/ARM_CM3_MPU/port.c
index 844b2ce1f..2fcd22e9b 100644
--- a/portable/GCC/ARM_CM3_MPU/port.c
+++ b/portable/GCC/ARM_CM3_MPU/port.c
@@ -188,7 +188,7 @@ void vResetPrivilege( void ) __attribute__( ( naked ) );
 /**
  * @brief Enter critical section.
  */
-#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
+#if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
     void vPortEnterCritical( void ) FREERTOS_SYSTEM_CALL;
 #else
     void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
@@ -197,7 +197,7 @@ void vResetPrivilege( void ) __attribute__( ( naked ) );
 /**
  * @brief Exit from critical section.
  */
-#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
+#if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
     void vPortExitCritical( void ) FREERTOS_SYSTEM_CALL;
 #else
     void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
@@ -205,40 +205,40 @@ void vResetPrivilege( void ) __attribute__( ( naked ) );
 
 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
 
-    /**
-     * @brief Sets up the system call stack so that upon returning from
-     * SVC, the system call stack is used.
-     *
-     * It is used for the system calls with up to 4 parameters.
-     *
-     * @param pulTaskStack The current SP when the SVC was raised.
-     */
+/**
+ * @brief Sets up the system call stack so that upon returning from
+ * SVC, the system call stack is used.
+ *
+ * It is used for the system calls with up to 4 parameters.
+ *
+ * @param pulTaskStack The current SP when the SVC was raised.
+ */
     void vSystemCallEnter( uint32_t * pulTaskStack ) PRIVILEGED_FUNCTION;
 
 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
 
-    /**
-     * @brief Sets up the system call stack so that upon returning from
-     * SVC, the system call stack is used.
-     *
-     * It is used for the system calls with 5 parameters.
-     *
-     * @param pulTaskStack The current SP when the SVC was raised.
-     */
+/**
+ * @brief Sets up the system call stack so that upon returning from
+ * SVC, the system call stack is used.
+ *
+ * It is used for the system calls with 5 parameters.
+ *
+ * @param pulTaskStack The current SP when the SVC was raised.
+ */
     void vSystemCallEnter_1( uint32_t * pulTaskStack ) PRIVILEGED_FUNCTION;
 
 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
 
-    /**
-     * @brief Sets up the task stack so that upon returning from
-     * SVC, the task stack is used again.
-     *
-     * @param pulSystemCallStack The current SP when the SVC was raised.
-     */
+/**
+ * @brief Sets up the task stack so that upon returning from
+ * SVC, the task stack is used again.
+ *
+ * @param pulSystemCallStack The current SP when the SVC was raised.
+ */
     void vSystemCallExit( uint32_t * pulSystemCallStack ) PRIVILEGED_FUNCTION;
 
 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@@ -287,25 +287,26 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
         xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
         xMPUSettings->ulContext[ 0 ] = portINITIAL_CONTROL_IF_UNPRIVILEGED;
     }
-    xMPUSettings->ulContext[ 1 ] = 0x04040404; /* r4. */
-    xMPUSettings->ulContext[ 2 ] = 0x05050505; /* r5. */
-    xMPUSettings->ulContext[ 3 ] = 0x06060606; /* r6. */
-    xMPUSettings->ulContext[ 4 ] = 0x07070707; /* r7. */
-    xMPUSettings->ulContext[ 5 ] = 0x08080808; /* r8. */
-    xMPUSettings->ulContext[ 6 ] = 0x09090909; /* r9. */
-    xMPUSettings->ulContext[ 7 ] = 0x10101010; /* r10. */
-    xMPUSettings->ulContext[ 8 ] = 0x11111111; /* r11. */
-    xMPUSettings->ulContext[ 9 ] = portINITIAL_EXC_RETURN; /* EXC_RETURN. */
 
-    xMPUSettings->ulContext[ 10 ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
-    xMPUSettings->ulContext[ 11 ] = ( uint32_t ) pvParameters; /* r0. */
-    xMPUSettings->ulContext[ 12 ] = 0x01010101; /* r1. */
-    xMPUSettings->ulContext[ 13 ] = 0x02020202; /* r2. */
-    xMPUSettings->ulContext[ 14 ] = 0x03030303; /* r3. */
-    xMPUSettings->ulContext[ 15 ] = 0x12121212; /* r12. */
-    xMPUSettings->ulContext[ 16 ] = 0; /* LR. */
+    xMPUSettings->ulContext[ 1 ] = 0x04040404;                                        /* r4. */
+    xMPUSettings->ulContext[ 2 ] = 0x05050505;                                        /* r5. */
+    xMPUSettings->ulContext[ 3 ] = 0x06060606;                                        /* r6. */
+    xMPUSettings->ulContext[ 4 ] = 0x07070707;                                        /* r7. */
+    xMPUSettings->ulContext[ 5 ] = 0x08080808;                                        /* r8. */
+    xMPUSettings->ulContext[ 6 ] = 0x09090909;                                        /* r9. */
+    xMPUSettings->ulContext[ 7 ] = 0x10101010;                                        /* r10. */
+    xMPUSettings->ulContext[ 8 ] = 0x11111111;                                        /* r11. */
+    xMPUSettings->ulContext[ 9 ] = portINITIAL_EXC_RETURN;                            /* EXC_RETURN. */
+
+    xMPUSettings->ulContext[ 10 ] = ( uint32_t ) ( pxTopOfStack - 8 );                /* PSP with the hardware saved stack. */
+    xMPUSettings->ulContext[ 11 ] = ( uint32_t ) pvParameters;                        /* r0. */
+    xMPUSettings->ulContext[ 12 ] = 0x01010101;                                       /* r1. */
+    xMPUSettings->ulContext[ 13 ] = 0x02020202;                                       /* r2. */
+    xMPUSettings->ulContext[ 14 ] = 0x03030303;                                       /* r3. */
+    xMPUSettings->ulContext[ 15 ] = 0x12121212;                                       /* r12. */
+    xMPUSettings->ulContext[ 16 ] = 0;                                                /* LR. */
     xMPUSettings->ulContext[ 17 ] = ( ( uint32_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC. */
-    xMPUSettings->ulContext[ 18 ] = portINITIAL_XPSR; /* xPSR. */
+    xMPUSettings->ulContext[ 18 ] = portINITIAL_XPSR;                                 /* xPSR. */
 
     #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
     {
@@ -325,56 +326,56 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
 
 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
 
-void vPortSVCHandler( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        ".syntax unified                \n"
-        ".extern vSVCHandler_C          \n"
-        ".extern vSystemCallEnter       \n"
-        ".extern vSystemCallEnter_1     \n"
-        ".extern vSystemCallExit        \n"
-        "                               \n"
-        "tst lr, #4                     \n"
-        "ite eq                         \n"
-        "mrseq r0, msp                  \n"
-        "mrsne r0, psp                  \n"
-        "                               \n"
-        "ldr r1, [r0, #24]              \n"
-        "ldrb r2, [r1, #-2]             \n"
-        "cmp r2, %0                     \n"
-        "beq vSystemCallEnter           \n"
-        "cmp r2, %1                     \n"
-        "beq vSystemCallEnter_1         \n"
-        "cmp r2, %2                     \n"
-        "beq vSystemCallExit            \n"
-        "b vSVCHandler_C                \n"
-        "                               \n"
-        : /* No outputs. */
-        :"i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT )
-        : "r0", "r1", "r2", "memory"
-    );
-}
+    void vPortSVCHandler( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            ".syntax unified                \n"
+            ".extern vSVCHandler_C          \n"
+            ".extern vSystemCallEnter       \n"
+            ".extern vSystemCallEnter_1     \n"
+            ".extern vSystemCallExit        \n"
+            "                               \n"
+            "tst lr, #4                     \n"
+            "ite eq                         \n"
+            "mrseq r0, msp                  \n"
+            "mrsne r0, psp                  \n"
+            "                               \n"
+            "ldr r1, [r0, #24]              \n"
+            "ldrb r2, [r1, #-2]             \n"
+            "cmp r2, %0                     \n"
+            "beq vSystemCallEnter           \n"
+            "cmp r2, %1                     \n"
+            "beq vSystemCallEnter_1         \n"
+            "cmp r2, %2                     \n"
+            "beq vSystemCallExit            \n"
+            "b vSVCHandler_C                \n"
+            "                               \n"
+            : /* No outputs. */
+            : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT )
+            : "r0", "r1", "r2", "memory"
+        );
+    }
 
 #else /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
-void vPortSVCHandler( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */
-{
-    /* Assumes psp was in use. */
-    __asm volatile
-    (
-        #ifndef USE_PROCESS_STACK   /* Code should not be required if a main() is using the process stack. */
-            "   tst lr, #4                      \n"
-            "   ite eq                          \n"
-            "   mrseq r0, msp                   \n"
-            "   mrsne r0, psp                   \n"
-        #else
-            "   mrs r0, psp                     \n"
-        #endif
-        "   b %0                            \n"
-        ::"i" ( vSVCHandler_C ) : "r0", "memory"
-    );
-}
+    void vPortSVCHandler( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */
+    {
+        /* Assumes psp was in use. */
+        __asm volatile
+        (
+            #ifndef USE_PROCESS_STACK /* Code should not be required if a main() is using the process stack. */
+                "   tst lr, #4                      \n"
+                "   ite eq                          \n"
+                "   mrseq r0, msp                   \n"
+                "   mrsne r0, psp                   \n"
+            #else
+                "   mrs r0, psp                     \n"
+            #endif
+            "   b %0                            \n"
+            ::"i" ( vSVCHandler_C ) : "r0", "memory"
+        );
+    }
 
 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
@@ -388,7 +389,7 @@ void vSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
         #if defined( __ARMCC_VERSION )
 
             /* Declaration when these variable are defined in code instead of being
-            * exported from linker scripts. */
+             * exported from linker scripts. */
             extern uint32_t * __syscalls_flash_start__;
             extern uint32_t * __syscalls_flash_end__;
         #else
@@ -432,9 +433,9 @@ void vSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
                     {
                         __asm volatile
                         (
-                            "   mrs r1, control     \n"/* Obtain current control value. */
-                            "   bic r1, #1          \n"/* Set privilege bit. */
-                            "   msr control, r1     \n"/* Write back new control value. */
+                            "   mrs r1, control     \n" /* Obtain current control value. */
+                            "   bic r1, #1          \n" /* Set privilege bit. */
+                            "   msr control, r1     \n" /* Write back new control value. */
                             ::: "r1", "memory"
                         );
                     }
@@ -444,13 +445,13 @@ void vSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
                 case portSVC_RAISE_PRIVILEGE:
                     __asm volatile
                     (
-                        "   mrs r1, control     \n"/* Obtain current control value. */
-                        "   bic r1, #1          \n"/* Set privilege bit. */
-                        "   msr control, r1     \n"/* Write back new control value. */
+                        "   mrs r1, control     \n" /* Obtain current control value. */
+                        "   bic r1, #1          \n" /* Set privilege bit. */
+                        "   msr control, r1     \n" /* Write back new control value. */
                         ::: "r1", "memory"
                     );
                     break;
-            #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
+                    #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
 
                 default: /* Unknown SVC call. */
                     break;
@@ -460,243 +461,251 @@ void vSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
 
 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
 
-void vSystemCallEnter( uint32_t * pulTaskStack ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulSystemCallStack;
-    uint32_t ulSystemCallLocation, i;
-    const uint32_t ulStackFrameSize = 8;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallEnter( uint32_t * pulTaskStack ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulSystemCallStack;
+        uint32_t ulSystemCallLocation, i;
+        const uint32_t ulStackFrameSize = 8;
 
-        /* This is not NULL only for the duration of the system call. */
-        configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+        #if defined( __ARMCC_VERSION )
 
-        /* Make space on the system call stack for the stack frame. */
-        pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
 
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
+        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            pulSystemCallStack[ i ] = pulTaskStack[ i ];
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+
+            /* This is not NULL only for the duration of the system call. */
+            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+
+            /* Make space on the system call stack for the stack frame. */
+            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulSystemCallStack[ i ] = pulTaskStack[ i ];
+            }
+
+            /* Use the pulSystemCallStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
+
+            /* Raise the privilege for the duration of the system call. */
+            __asm volatile (
+                " mrs r1, control     \n" /* Obtain current control value. */
+                " bic r1, #1          \n" /* Clear nPRIV bit. */
+                " msr control, r1     \n" /* Write back new control value. */
+                ::: "r1", "memory"
+                );
+
+            /* Remember the location where we should copy the stack frame when we exit from
+             * the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+
+            /* Store the value of the Link Register before the SVC was raised. We need to
+             * restore it when we exit from the system call. */
+            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+
+            /* Record if the hardware used padding to force the stack pointer
+             * to be double word aligned. */
+            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
+            {
+                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
+            }
+            else
+            {
+                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
+            }
+
+            /* We ensure in pxPortInitialiseStack that the system call stack is
+             * double word aligned and therefore, there is no need of padding.
+             * Clear the bit[9] of stacked xPSR. */
+            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
         }
-
-        /* Use the pulSystemCallStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-
-        /* Raise the privilege for the duration of the system call. */
-        __asm volatile (
-                            " mrs r1, control     \n" /* Obtain current control value. */
-                            " bic r1, #1          \n" /* Clear nPRIV bit. */
-                            " msr control, r1     \n" /* Write back new control value. */
-                            ::: "r1", "memory"
-                        );
-
-        /* Remember the location where we should copy the stack frame when we exit from
-         * the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-        /* Store the value of the Link Register before the SVC was raised. We need to
-         * restore it when we exit from the system call. */
-        pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-
-        /* Record if the hardware used padding to force the stack pointer
-         * to be double word aligned. */
-        if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-        {
-            pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-        }
-        else
-        {
-            pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-        }
-
-        /* We ensure in pxPortInitialiseStack that the system call stack is
-         * double word aligned and therefore, there is no need of padding.
-         * Clear the bit[9] of stacked xPSR. */
-        pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
     }
-}
 
 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
 
-void vSystemCallEnter_1( uint32_t * pulTaskStack ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulSystemCallStack;
-    uint32_t ulSystemCallLocation, i;
-    const uint32_t ulStackFrameSize = 8;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallEnter_1( uint32_t * pulTaskStack ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulSystemCallStack;
+        uint32_t ulSystemCallLocation, i;
+        const uint32_t ulStackFrameSize = 8;
 
-        /* This is not NULL only for the duration of the system call. */
-        configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+        #if defined( __ARMCC_VERSION )
 
-        /* Make space on the system call stack for the stack frame and
-         * the parameter passed on the stack. We only need to copy one
-         * parameter but we still reserve 2 spaces to keep the stack
-         * double word aligned. */
-        pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
 
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
+        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            pulSystemCallStack[ i ] = pulTaskStack[ i ];
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+
+            /* This is not NULL only for the duration of the system call. */
+            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+
+            /* Make space on the system call stack for the stack frame and
+             * the parameter passed on the stack. We only need to copy one
+             * parameter but we still reserve 2 spaces to keep the stack
+             * double word aligned. */
+            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulSystemCallStack[ i ] = pulTaskStack[ i ];
+            }
+
+            /* Copy the parameter which is passed the stack. */
+            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
+            {
+                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
+
+                /* Record if the hardware used padding to force the stack pointer
+                 * to be double word aligned. */
+                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
+            }
+            else
+            {
+                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
+
+                /* Record if the hardware used padding to force the stack pointer
+                 * to be double word aligned. */
+                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
+            }
+
+            /* Use the pulSystemCallStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
+
+            /* Raise the privilege for the duration of the system call. */
+            __asm volatile (
+                " mrs r1, control     \n" /* Obtain current control value. */
+                " bic r1, #1          \n" /* Clear nPRIV bit. */
+                " msr control, r1     \n" /* Write back new control value. */
+                ::: "r1", "memory"
+                );
+
+            /* Remember the location where we should copy the stack frame when we exit from
+             * the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+
+            /* Store the value of the Link Register before the SVC was raised. We need to
+             * restore it when we exit from the system call. */
+            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+
+            /* We ensure in pxPortInitialiseStack that the system call stack is
+             * double word aligned and therefore, there is no need of padding.
+             * Clear the bit[9] of stacked xPSR. */
+            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
         }
-
-        /* Copy the parameter which is passed the stack. */
-        if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-        {
-            pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
-            /* Record if the hardware used padding to force the stack pointer
-             * to be double word aligned. */
-            pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-        }
-        else
-        {
-            pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
-            /* Record if the hardware used padding to force the stack pointer
-             * to be double word aligned. */
-            pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-        }
-
-        /* Use the pulSystemCallStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-
-        /* Raise the privilege for the duration of the system call. */
-        __asm volatile (
-                            " mrs r1, control     \n" /* Obtain current control value. */
-                            " bic r1, #1          \n" /* Clear nPRIV bit. */
-                            " msr control, r1     \n" /* Write back new control value. */
-                            ::: "r1", "memory"
-                        );
-
-        /* Remember the location where we should copy the stack frame when we exit from
-         * the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-        /* Store the value of the Link Register before the SVC was raised. We need to
-         * restore it when we exit from the system call. */
-        pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-
-        /* We ensure in pxPortInitialiseStack that the system call stack is
-         * double word aligned and therefore, there is no need of padding.
-         * Clear the bit[9] of stacked xPSR. */
-        pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
     }
-}
 
 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
 
-void vSystemCallExit( uint32_t * pulSystemCallStack ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulTaskStack;
-    uint32_t ulSystemCallLocation, i;
-    const uint32_t ulStackFrameSize = 8;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallExit( uint32_t * pulSystemCallStack ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulTaskStack;
+        uint32_t ulSystemCallLocation, i;
+        const uint32_t ulStackFrameSize = 8;
 
-        /* Make space on the task stack for the stack frame. */
-        pulTaskStack = pulTaskStack - ulStackFrameSize;
+        #if defined( __ARMCC_VERSION )
 
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            pulTaskStack[ i ] = pulSystemCallStack[ i ];
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
+
+            /* Make space on the task stack for the stack frame. */
+            pulTaskStack = pulTaskStack - ulStackFrameSize;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulTaskStack[ i ] = pulSystemCallStack[ i ];
+            }
+
+            /* Use the pulTaskStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
+
+            /* Drop the privilege before returning to the thread mode. */
+            __asm volatile (
+                " mrs r1, control     \n" /* Obtain current control value. */
+                " orr r1, #1          \n" /* Set nPRIV bit. */
+                " msr control, r1     \n" /* Write back new control value. */
+                ::: "r1", "memory"
+                );
+
+            /* Restore the stacked link register to what it was at the time of
+             * system call entry. */
+            pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+
+            /* If the hardware used padding to force the stack pointer
+             * to be double word aligned, set the stacked xPSR bit[9],
+             * otherwise clear it. */
+            if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG )
+            {
+                pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK;
+            }
+            else
+            {
+                pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
+            }
+
+            /* This is not NULL only for the duration of the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
         }
-
-        /* Use the pulTaskStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
-
-        /* Drop the privilege before returning to the thread mode. */
-        __asm volatile (
-                            " mrs r1, control     \n" /* Obtain current control value. */
-                            " orr r1, #1          \n" /* Set nPRIV bit. */
-                            " msr control, r1     \n" /* Write back new control value. */
-                            ::: "r1", "memory"
-                        );
-
-        /* Restore the stacked link register to what it was at the time of
-         * system call entry. */
-        pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
-
-        /* If the hardware used padding to force the stack pointer
-         * to be double word aligned, set the stacked xPSR bit[9],
-         * otherwise clear it. */
-        if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG )
-        {
-            pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK;
-        }
-        else
-        {
-            pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-        }
-
-        /* This is not NULL only for the duration of the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
     }
-}
 
 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
@@ -774,87 +783,87 @@ static void prvRestoreContextOfFirstTask( void )
 BaseType_t xPortStartScheduler( void )
 {
     #if ( configASSERT_DEFINED == 1 )
+    {
+        volatile uint8_t ucOriginalPriority;
+        volatile uint32_t ulImplementedPrioBits = 0;
+        volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
+        volatile uint8_t ucMaxPriorityValue;
+
+        /* Determine the maximum priority from which ISR safe FreeRTOS API
+         * functions can be called.  ISR safe functions are those that end in
+         * "FromISR".  FreeRTOS maintains separate thread and ISR API functions
+         * to ensure interrupt entry is as fast and simple as possible.
+         *
+         * Save the interrupt priority value that is about to be clobbered. */
+        ucOriginalPriority = *pucFirstUserPriorityRegister;
+
+        /* Determine the number of priority bits available.  First write to all
+         * possible bits. */
+        *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+        /* Read the value back to see how many bits stuck. */
+        ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+        /* Use the same mask on the maximum system call priority. */
+        ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+        /* Check that the maximum system call priority is nonzero after
+         * accounting for the number of priority bits supported by the
+         * hardware. A priority of 0 is invalid because setting the BASEPRI
+         * register to 0 unmasks all interrupts, and interrupts with priority 0
+         * cannot be masked using BASEPRI.
+         * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+        configASSERT( ucMaxSysCallPriority );
+
+        /* Check that the bits not implemented in hardware are zero in
+         * configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
+
+        /* Calculate the maximum acceptable priority group value for the number
+         * of bits read back. */
+
+        while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
         {
-            volatile uint8_t ucOriginalPriority;
-            volatile uint32_t ulImplementedPrioBits = 0;
-            volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
-            volatile uint8_t ucMaxPriorityValue;
-
-            /* Determine the maximum priority from which ISR safe FreeRTOS API
-             * functions can be called.  ISR safe functions are those that end in
-             * "FromISR".  FreeRTOS maintains separate thread and ISR API functions
-             * to ensure interrupt entry is as fast and simple as possible.
-             *
-             * Save the interrupt priority value that is about to be clobbered. */
-            ucOriginalPriority = *pucFirstUserPriorityRegister;
-
-            /* Determine the number of priority bits available.  First write to all
-             * possible bits. */
-            *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
-
-            /* Read the value back to see how many bits stuck. */
-            ucMaxPriorityValue = *pucFirstUserPriorityRegister;
-
-            /* Use the same mask on the maximum system call priority. */
-            ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
-
-            /* Check that the maximum system call priority is nonzero after
-             * accounting for the number of priority bits supported by the
-             * hardware. A priority of 0 is invalid because setting the BASEPRI
-             * register to 0 unmasks all interrupts, and interrupts with priority 0
-             * cannot be masked using BASEPRI.
-             * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
-            configASSERT( ucMaxSysCallPriority );
-
-            /* Check that the bits not implemented in hardware are zero in
-             * configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-            configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
-
-            /* Calculate the maximum acceptable priority group value for the number
-             * of bits read back. */
-
-            while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
-            {
-                ulImplementedPrioBits++;
-                ucMaxPriorityValue <<= ( uint8_t ) 0x01;
-            }
-
-            if( ulImplementedPrioBits == 8 )
-            {
-                /* When the hardware implements 8 priority bits, there is no way for
-                * the software to configure PRIGROUP to not have sub-priorities. As
-                * a result, the least significant bit is always used for sub-priority
-                * and there are 128 preemption priorities and 2 sub-priorities.
-                *
-                * This may cause some confusion in some cases - for example, if
-                * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
-                * priority interrupts will be masked in Critical Sections as those
-                * are at the same preemption priority. This may appear confusing as
-                * 4 is higher (numerically lower) priority than
-                * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
-                * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
-                * to 4, this confusion does not happen and the behaviour remains the same.
-                *
-                * The following assert ensures that the sub-priority bit in the
-                * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
-                * confusion. */
-                configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
-                ulMaxPRIGROUPValue = 0;
-            }
-            else
-            {
-                ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
-            }
-
-            /* Shift the priority group value back to its position within the AIRCR
-             * register. */
-            ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
-            ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
-            /* Restore the clobbered interrupt priority register to its original
-             * value. */
-            *pucFirstUserPriorityRegister = ucOriginalPriority;
+            ulImplementedPrioBits++;
+            ucMaxPriorityValue <<= ( uint8_t ) 0x01;
         }
+
+        if( ulImplementedPrioBits == 8 )
+        {
+            /* When the hardware implements 8 priority bits, there is no way for
+             * the software to configure PRIGROUP to not have sub-priorities. As
+             * a result, the least significant bit is always used for sub-priority
+             * and there are 128 preemption priorities and 2 sub-priorities.
+             *
+             * This may cause some confusion in some cases - for example, if
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
+             * priority interrupts will be masked in Critical Sections as those
+             * are at the same preemption priority. This may appear confusing as
+             * 4 is higher (numerically lower) priority than
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
+             * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
+             * to 4, this confusion does not happen and the behaviour remains the same.
+             *
+             * The following assert ensures that the sub-priority bit in the
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
+             * confusion. */
+            configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
+            ulMaxPRIGROUPValue = 0;
+        }
+        else
+        {
+            ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
+        }
+
+        /* Shift the priority group value back to its position within the AIRCR
+         * register. */
+        ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+        ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+        /* Restore the clobbered interrupt priority register to its original
+         * value. */
+        *pucFirstUserPriorityRegister = ucOriginalPriority;
+    }
     #endif /* configASSERT_DEFINED */
 
     /* Make PendSV and SysTick the same priority as the kernel, and the SVC
@@ -875,15 +884,15 @@ BaseType_t xPortStartScheduler( void )
 
     /* Start the first task. */
     __asm volatile (
-        " ldr r0, =0xE000ED08   \n"/* Use the NVIC offset register to locate the stack. */
+        " ldr r0, =0xE000ED08   \n" /* Use the NVIC offset register to locate the stack. */
         " ldr r0, [r0]          \n"
         " ldr r0, [r0]          \n"
-        " msr msp, r0           \n"/* Set the msp back to the start of the stack. */
-        " cpsie i               \n"/* Globally enable interrupts. */
+        " msr msp, r0           \n" /* Set the msp back to the start of the stack. */
+        " cpsie i               \n" /* Globally enable interrupts. */
         " cpsie f               \n"
         " dsb                   \n"
         " isb                   \n"
-        " svc %0                \n"/* System call to start first task. */
+        " svc %0                \n" /* System call to start first task. */
         " nop                   \n"
         " .ltorg                \n"
         ::"i" ( portSVC_START_SCHEDULER ) : "memory" );
@@ -903,39 +912,63 @@ void vPortEndScheduler( void )
 
 void vPortEnterCritical( void )
 {
-#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
-    if( portIS_PRIVILEGED() == pdFALSE )
-    {
-        portRAISE_PRIVILEGE();
-        portMEMORY_BARRIER();
+    #if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
+        if( portIS_PRIVILEGED() == pdFALSE )
+        {
+            portRAISE_PRIVILEGE();
+            portMEMORY_BARRIER();
 
+            portDISABLE_INTERRUPTS();
+            uxCriticalNesting++;
+            portMEMORY_BARRIER();
+
+            portRESET_PRIVILEGE();
+            portMEMORY_BARRIER();
+        }
+        else
+        {
+            portDISABLE_INTERRUPTS();
+            uxCriticalNesting++;
+        }
+    #else /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */
         portDISABLE_INTERRUPTS();
         uxCriticalNesting++;
-        portMEMORY_BARRIER();
-
-        portRESET_PRIVILEGE();
-        portMEMORY_BARRIER();
-    }
-    else
-    {
-        portDISABLE_INTERRUPTS();
-        uxCriticalNesting++;
-    }
-#else
-    portDISABLE_INTERRUPTS();
-    uxCriticalNesting++;
-#endif
+    #endif /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */
 }
 /*-----------------------------------------------------------*/
 
 void vPortExitCritical( void )
 {
-#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
-    if( portIS_PRIVILEGED() == pdFALSE )
-    {
-        portRAISE_PRIVILEGE();
-        portMEMORY_BARRIER();
+    #if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
+        if( portIS_PRIVILEGED() == pdFALSE )
+        {
+            portRAISE_PRIVILEGE();
+            portMEMORY_BARRIER();
 
+            configASSERT( uxCriticalNesting );
+            uxCriticalNesting--;
+
+            if( uxCriticalNesting == 0 )
+            {
+                portENABLE_INTERRUPTS();
+            }
+
+            portMEMORY_BARRIER();
+
+            portRESET_PRIVILEGE();
+            portMEMORY_BARRIER();
+        }
+        else
+        {
+            configASSERT( uxCriticalNesting );
+            uxCriticalNesting--;
+
+            if( uxCriticalNesting == 0 )
+            {
+                portENABLE_INTERRUPTS();
+            }
+        }
+    #else /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */
         configASSERT( uxCriticalNesting );
         uxCriticalNesting--;
 
@@ -943,30 +976,7 @@ void vPortExitCritical( void )
         {
             portENABLE_INTERRUPTS();
         }
-        portMEMORY_BARRIER();
-
-        portRESET_PRIVILEGE();
-        portMEMORY_BARRIER();
-    }
-    else
-    {
-        configASSERT( uxCriticalNesting );
-        uxCriticalNesting--;
-
-        if( uxCriticalNesting == 0 )
-        {
-            portENABLE_INTERRUPTS();
-        }
-    }
-#else
-    configASSERT( uxCriticalNesting );
-    uxCriticalNesting--;
-
-    if( uxCriticalNesting == 0 )
-    {
-        portENABLE_INTERRUPTS();
-    }
-#endif
+    #endif /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */
 }
 /*-----------------------------------------------------------*/
 
@@ -1167,12 +1177,12 @@ BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
 {
     __asm volatile
     (
-        "   mrs r0, control                         \n"/* r0 = CONTROL. */
-        "   tst r0, #1                              \n"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+        "   mrs r0, control                         \n" /* r0 = CONTROL. */
+        "   tst r0, #1                              \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
         "   ite ne                                  \n"
-        "   movne r0, #0                            \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
-        "   moveq r0, #1                            \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
-        "   bx lr                                   \n"/* Return. */
+        "   movne r0, #0                            \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+        "   moveq r0, #1                            \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+        "   bx lr                                   \n" /* Return. */
         "                                           \n"
         "   .align 4                                \n"
         ::: "r0", "memory"
@@ -1184,10 +1194,10 @@ void vResetPrivilege( void ) /* __attribute__ (( naked )) */
 {
     __asm volatile
     (
-        "   mrs r0, control                         \n"/* r0 = CONTROL. */
-        "   orr r0, #1                              \n"/* r0 = r0 | 1. */
-        "   msr control, r0                         \n"/* CONTROL = r0. */
-        "   bx lr                                   \n"/* Return to the caller. */
+        "   mrs r0, control                         \n" /* r0 = CONTROL. */
+        "   orr r0, #1                              \n" /* r0 = r0 | 1. */
+        "   msr control, r0                         \n" /* CONTROL = r0. */
+        "   bx lr                                   \n" /* Return to the caller. */
         ::: "r0", "memory"
     );
 }
@@ -1211,7 +1221,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
         xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
             ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */
             ( portMPU_REGION_VALID ) |
-            ( portSTACK_REGION ); /* Region number. */
+            ( portSTACK_REGION );                     /* Region number. */
 
         xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
             ( portMPU_REGION_READ_WRITE ) |
@@ -1284,11 +1294,13 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
                 xMPUSettings->xRegionSettings[ ul ].ulRegionStartAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress;
                 xMPUSettings->xRegionSettings[ ul ].ulRegionEndAddress = ( uint32_t ) ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1UL );
                 xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = 0UL;
+
                 if( ( ( xRegions[ lIndex ].ulParameters & portMPU_REGION_READ_ONLY ) == portMPU_REGION_READ_ONLY ) ||
                     ( ( xRegions[ lIndex ].ulParameters & portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ) == portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ) )
                 {
                     xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = tskMPU_READ_PERMISSION;
                 }
+
                 if( ( xRegions[ lIndex ].ulParameters & portMPU_REGION_READ_WRITE ) == portMPU_REGION_READ_WRITE )
                 {
                     xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = ( tskMPU_READ_PERMISSION | tskMPU_WRITE_PERMISSION );
@@ -1405,7 +1417,7 @@ BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
          * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
          * scheduler.  Note however that some vendor specific peripheral libraries
          * assume a non-zero priority group setting, in which cases using a value
-         * of zero will result in unpredicable behaviour. */
+         * of zero will result in unpredictable behaviour. */
         configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
     }
 
diff --git a/portable/GCC/ARM_CM3_MPU/portmacro.h b/portable/GCC/ARM_CM3_MPU/portmacro.h
index 322e41a6c..31a4812ea 100644
--- a/portable/GCC/ARM_CM3_MPU/portmacro.h
+++ b/portable/GCC/ARM_CM3_MPU/portmacro.h
@@ -47,123 +47,123 @@
  */
 
 /* Type definitions. */
-    #define portCHAR          char
-    #define portFLOAT         float
-    #define portDOUBLE        double
-    #define portLONG          long
-    #define portSHORT         short
-    #define portSTACK_TYPE    uint32_t
-    #define portBASE_TYPE     long
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-    typedef portSTACK_TYPE   StackType_t;
-    typedef long             BaseType_t;
-    typedef unsigned long    UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
-    #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-        typedef uint16_t     TickType_t;
-        #define portMAX_DELAY              ( TickType_t ) 0xffff
-    #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-        typedef uint32_t     TickType_t;
-        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
  * not need to be guarded with a critical section. */
-        #define portTICK_TYPE_IS_ATOMIC    1
-    #else
-        #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
-    #endif
+    #define portTICK_TYPE_IS_ATOMIC    1
+#else
+    #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+#endif
 /*-----------------------------------------------------------*/
 
 /* MPU specific constants. */
-    #define portUSING_MPU_WRAPPERS                                   1
-    #define portPRIVILEGE_BIT                                        ( 0x80000000UL )
+#define portUSING_MPU_WRAPPERS                                   1
+#define portPRIVILEGE_BIT                                        ( 0x80000000UL )
 
-    #define portMPU_REGION_READ_WRITE                                ( 0x03UL << 24UL )
-    #define portMPU_REGION_PRIVILEGED_READ_ONLY                      ( 0x05UL << 24UL )
-    #define portMPU_REGION_READ_ONLY                                 ( 0x06UL << 24UL )
-    #define portMPU_REGION_PRIVILEGED_READ_WRITE                     ( 0x01UL << 24UL )
-    #define portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY    ( 0x02UL << 24UL )
-    #define portMPU_REGION_CACHEABLE_BUFFERABLE                      ( 0x07UL << 16UL )
-    #define portMPU_REGION_EXECUTE_NEVER                             ( 0x01UL << 28UL )
+#define portMPU_REGION_READ_WRITE                                ( 0x03UL << 24UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY                      ( 0x05UL << 24UL )
+#define portMPU_REGION_READ_ONLY                                 ( 0x06UL << 24UL )
+#define portMPU_REGION_PRIVILEGED_READ_WRITE                     ( 0x01UL << 24UL )
+#define portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY    ( 0x02UL << 24UL )
+#define portMPU_REGION_CACHEABLE_BUFFERABLE                      ( 0x07UL << 16UL )
+#define portMPU_REGION_EXECUTE_NEVER                             ( 0x01UL << 28UL )
 
-    #define portSTACK_REGION                                         ( 3UL )
-    #define portGENERAL_PERIPHERALS_REGION                           ( 4UL )
-    #define portUNPRIVILEGED_FLASH_REGION                            ( 5UL )
-    #define portPRIVILEGED_FLASH_REGION                              ( 6UL )
-    #define portPRIVILEGED_RAM_REGION                                ( 7UL )
-    #define portFIRST_CONFIGURABLE_REGION                            ( 0UL )
-    #define portLAST_CONFIGURABLE_REGION                             ( 2UL )
-    #define portNUM_CONFIGURABLE_REGIONS                             ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
-    #define portTOTAL_NUM_REGIONS_IN_TCB                             ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+#define portSTACK_REGION                                         ( 3UL )
+#define portGENERAL_PERIPHERALS_REGION                           ( 4UL )
+#define portUNPRIVILEGED_FLASH_REGION                            ( 5UL )
+#define portPRIVILEGED_FLASH_REGION                              ( 6UL )
+#define portPRIVILEGED_RAM_REGION                                ( 7UL )
+#define portFIRST_CONFIGURABLE_REGION                            ( 0UL )
+#define portLAST_CONFIGURABLE_REGION                             ( 2UL )
+#define portNUM_CONFIGURABLE_REGIONS                             ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS_IN_TCB                             ( portNUM_CONFIGURABLE_REGIONS + 1 )     /* Plus one to make space for the stack region. */
 
-    #define portSWITCH_TO_USER_MODE()    __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0 " ::: "r0", "memory" )
+#define portSWITCH_TO_USER_MODE()    __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0 " ::: "r0", "memory" )
 
-    typedef struct MPU_REGION_REGISTERS
+typedef struct MPU_REGION_REGISTERS
+{
+    uint32_t ulRegionBaseAddress;
+    uint32_t ulRegionAttribute;
+} xMPU_REGION_REGISTERS;
+
+typedef struct MPU_REGION_SETTINGS
+{
+    uint32_t ulRegionStartAddress;
+    uint32_t ulRegionEndAddress;
+    uint32_t ulRegionPermissions;
+} xMPU_REGION_SETTINGS;
+
+#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+
+    #ifndef configSYSTEM_CALL_STACK_SIZE
+        #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
+    #endif
+
+    typedef struct SYSTEM_CALL_STACK_INFO
     {
-        uint32_t ulRegionBaseAddress;
-        uint32_t ulRegionAttribute;
-    } xMPU_REGION_REGISTERS;
+        uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ];
+        uint32_t * pulSystemCallStack;
+        uint32_t * pulTaskStack;
+        uint32_t ulLinkRegisterAtSystemCallEntry;
+    } xSYSTEM_CALL_STACK_INFO;
 
-    typedef struct MPU_REGION_SETTINGS
-    {
-        uint32_t ulRegionStartAddress;
-        uint32_t ulRegionEndAddress;
-        uint32_t ulRegionPermissions;
-    } xMPU_REGION_SETTINGS;
+#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+
+#define MAX_CONTEXT_SIZE                    20
+
+/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
+#define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
+#define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
+
+typedef struct MPU_SETTINGS
+{
+    xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS_IN_TCB ];
+    xMPU_REGION_SETTINGS xRegionSettings[ portTOTAL_NUM_REGIONS_IN_TCB ];
+    uint32_t ulContext[ MAX_CONTEXT_SIZE ];
+    uint32_t ulTaskFlags;
 
     #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
-
-        #ifndef configSYSTEM_CALL_STACK_SIZE
-            #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
-        #endif
-
-        typedef struct SYSTEM_CALL_STACK_INFO
-        {
-            uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ];
-            uint32_t * pulSystemCallStack;
-            uint32_t * pulTaskStack;
-            uint32_t ulLinkRegisterAtSystemCallEntry;
-        } xSYSTEM_CALL_STACK_INFO;
-
-    #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
-
-    #define MAX_CONTEXT_SIZE 20
-
-    /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
-    #define portSTACK_FRAME_HAS_PADDING_FLAG     ( 1UL << 0UL )
-    #define portTASK_IS_PRIVILEGED_FLAG          ( 1UL << 1UL )
-
-    typedef struct MPU_SETTINGS
-    {
-        xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS_IN_TCB ];
-        xMPU_REGION_SETTINGS xRegionSettings[ portTOTAL_NUM_REGIONS_IN_TCB ];
-        uint32_t ulContext[ MAX_CONTEXT_SIZE ];
-        uint32_t ulTaskFlags;
-
-        #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
-            xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
-        #endif
-    } xMPU_SETTINGS;
+        xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
+    #endif
+} xMPU_SETTINGS;
 
 /* Architecture specifics. */
-    #define portSTACK_GROWTH      ( -1 )
-    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-    #define portBYTE_ALIGNMENT    8
-    #define portDONT_DISCARD      __attribute__( ( used ) )
+#define portSTACK_GROWTH      ( -1 )
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT    8
+#define portDONT_DISCARD      __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
 /* SVC numbers for various services. */
-    #define portSVC_START_SCHEDULER     0
-    #define portSVC_YIELD               1
-    #define portSVC_RAISE_PRIVILEGE     2
-    #define portSVC_SYSTEM_CALL_ENTER   3   /* System calls with upto 4 parameters. */
-    #define portSVC_SYSTEM_CALL_ENTER_1 4   /* System calls with 5 parameters. */
-    #define portSVC_SYSTEM_CALL_EXIT    5
+#define portSVC_START_SCHEDULER        0
+#define portSVC_YIELD                  1
+#define portSVC_RAISE_PRIVILEGE        2
+#define portSVC_SYSTEM_CALL_ENTER      3    /* System calls with upto 4 parameters. */
+#define portSVC_SYSTEM_CALL_ENTER_1    4    /* System calls with 5 parameters. */
+#define portSVC_SYSTEM_CALL_EXIT       5
 
 /* Scheduler utilities. */
 
-    #define portYIELD()    __asm volatile ( "   SVC %0  \n"::"i" ( portSVC_YIELD ) : "memory" )
-    #define portYIELD_WITHIN_API()                      \
+#define portYIELD()    __asm volatile ( "   SVC %0  \n" ::"i" ( portSVC_YIELD ) : "memory" )
+#define portYIELD_WITHIN_API()                          \
     {                                                   \
         /* Set a PendSV to request a context switch. */ \
         portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
@@ -174,185 +174,187 @@
         __asm volatile ( "isb" );                                  \
     }
 
-    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
-    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-    #define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )
-    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+#define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired )                                 \
+    do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
+    while( 0 )
+#define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
 /* Critical section management. */
-    extern void vPortEnterCritical( void );
-    extern void vPortExitCritical( void );
-    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulPortRaiseBASEPRI()
-    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vPortSetBASEPRI( x )
-    #define portDISABLE_INTERRUPTS()                  vPortRaiseBASEPRI()
-    #define portENABLE_INTERRUPTS()                   vPortSetBASEPRI( 0 )
-    #define portENTER_CRITICAL()                      vPortEnterCritical()
-    #define portEXIT_CRITICAL()                       vPortExitCritical()
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+#define portSET_INTERRUPT_MASK_FROM_ISR()         ulPortRaiseBASEPRI()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vPortSetBASEPRI( x )
+#define portDISABLE_INTERRUPTS()                  vPortRaiseBASEPRI()
+#define portENABLE_INTERRUPTS()                   vPortSetBASEPRI( 0 )
+#define portENTER_CRITICAL()                      vPortEnterCritical()
+#define portEXIT_CRITICAL()                       vPortExitCritical()
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site.  These are
  * not necessary for to use this port.  They are defined so the common demo files
  * (which build with all the ports) will build. */
-    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
-    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 /*-----------------------------------------------------------*/
 
 /* Architecture specific optimisations. */
-    #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
-    #endif
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+    #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
+#endif
 
-    #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
 
 /* Generic helper function. */
-        __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
-        {
-            uint8_t ucReturn;
+    __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
+    {
+        uint8_t ucReturn;
 
-            __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
+        __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
 
-            return ucReturn;
-        }
+        return ucReturn;
+    }
 
 /* Check the configuration. */
-        #if ( configMAX_PRIORITIES > 32 )
-            #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
-        #endif
+    #if ( configMAX_PRIORITIES > 32 )
+        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+    #endif
 
 /* Store/clear the ready priorities in a bit map. */
-        #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-        #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 
 /*-----------------------------------------------------------*/
 
-        #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
 
-    #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 
 /*-----------------------------------------------------------*/
 
-    #ifdef configASSERT
-        void vPortValidateInterruptPriority( void );
-        #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
-    #endif
+#ifdef configASSERT
+    void vPortValidateInterruptPriority( void );
+    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
+#endif
 
 /* portNOP() is not required by this port. */
-    #define portNOP()
+#define portNOP()
 
-    #define portINLINE              __inline
+#define portINLINE              __inline
 
-    #ifndef portFORCE_INLINE
-        #define portFORCE_INLINE    inline __attribute__( ( always_inline ) )
-    #endif
+#ifndef portFORCE_INLINE
+    #define portFORCE_INLINE    inline __attribute__( ( always_inline ) )
+#endif
 /*-----------------------------------------------------------*/
 
-    extern BaseType_t xIsPrivileged( void );
-    extern void vResetPrivilege( void );
+extern BaseType_t xIsPrivileged( void );
+extern void vResetPrivilege( void );
 
 /**
  * @brief Checks whether or not the processor is privileged.
  *
  * @return 1 if the processor is already privileged, 0 otherwise.
  */
-    #define portIS_PRIVILEGED()      xIsPrivileged()
+#define portIS_PRIVILEGED()      xIsPrivileged()
 
 /**
  * @brief Raise an SVC request to raise privilege.
  */
-    #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+#define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
 
 /**
  * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
  * register.
  */
-    #define portRESET_PRIVILEGE()    vResetPrivilege()
+#define portRESET_PRIVILEGE()    vResetPrivilege()
 /*-----------------------------------------------------------*/
 
-    extern BaseType_t xPortIsTaskPrivileged( void );
+extern BaseType_t xPortIsTaskPrivileged( void );
 
 /**
  * @brief Checks whether or not the calling task is privileged.
  *
  * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
  */
-    #define portIS_TASK_PRIVILEGED()      xPortIsTaskPrivileged()
+#define portIS_TASK_PRIVILEGED()    xPortIsTaskPrivileged()
 /*-----------------------------------------------------------*/
 
-    portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
+portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
+{
+    uint32_t ulCurrentInterrupt;
+    BaseType_t xReturn;
+
+    /* Obtain the number of the currently executing interrupt. */
+    __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+    if( ulCurrentInterrupt == 0 )
     {
-        uint32_t ulCurrentInterrupt;
-        BaseType_t xReturn;
-
-        /* Obtain the number of the currently executing interrupt. */
-        __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
-
-        if( ulCurrentInterrupt == 0 )
-        {
-            xReturn = pdFALSE;
-        }
-        else
-        {
-            xReturn = pdTRUE;
-        }
-
-        return xReturn;
+        xReturn = pdFALSE;
+    }
+    else
+    {
+        xReturn = pdTRUE;
     }
 
-/*-----------------------------------------------------------*/
-
-    portFORCE_INLINE static void vPortRaiseBASEPRI( void )
-    {
-        uint32_t ulNewBASEPRI;
-
-        __asm volatile
-        (
-            "   mov %0, %1                                              \n"\
-            "   msr basepri, %0                                         \n"\
-            "   isb                                                     \n"\
-            "   dsb                                                     \n"\
-            : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
-        );
-    }
+    return xReturn;
+}
 
 /*-----------------------------------------------------------*/
 
-    portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
-    {
-        uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
+portFORCE_INLINE static void vPortRaiseBASEPRI( void )
+{
+    uint32_t ulNewBASEPRI;
 
-        __asm volatile
-        (
-            "   mrs %0, basepri                                         \n"\
-            "   mov %1, %2                                              \n"\
-            "   msr basepri, %1                                         \n"\
-            "   isb                                                     \n"\
-            "   dsb                                                     \n"\
-            : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
-        );
+    __asm volatile
+    (
+        "   mov %0, %1                                              \n" \
+        "   msr basepri, %0                                         \n" \
+        "   isb                                                     \n" \
+        "   dsb                                                     \n" \
+        : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+    );
+}
 
-        /* This return will not be reached but is necessary to prevent compiler
-         * warnings. */
-        return ulOriginalBASEPRI;
-    }
 /*-----------------------------------------------------------*/
 
-    portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
-    {
-        __asm volatile
-        (
-            "   msr basepri, %0 "::"r" ( ulNewMaskValue ) : "memory"
-        );
-    }
+portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
+{
+    uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
+
+    __asm volatile
+    (
+        "   mrs %0, basepri                                         \n" \
+        "   mov %1, %2                                              \n" \
+        "   msr basepri, %1                                         \n" \
+        "   isb                                                     \n" \
+        "   dsb                                                     \n" \
+        : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+    );
+
+    /* This return will not be reached but is necessary to prevent compiler
+     * warnings. */
+    return ulOriginalBASEPRI;
+}
 /*-----------------------------------------------------------*/
 
-    #define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
+portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
+{
+    __asm volatile
+    (
+        "   msr basepri, %0 " ::"r" ( ulNewMaskValue ) : "memory"
+    );
+}
+/*-----------------------------------------------------------*/
 
-    #ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY
-        #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. *www.FreeRTOS.org/FreeRTOS-V10.3.x.html"
-        #define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY    0
-    #endif
+#define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
+
+#ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY
+    #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. *www.FreeRTOS.org/FreeRTOS-V10.3.x.html"
+    #define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY    0
+#endif
 /*-----------------------------------------------------------*/
 
 /* *INDENT-OFF* */
diff --git a/portable/GCC/ARM_CM4F/port.c b/portable/GCC/ARM_CM4F/port.c
index d18854e1b..e5ea4e336 100644
--- a/portable/GCC/ARM_CM4F/port.c
+++ b/portable/GCC/ARM_CM4F/port.c
@@ -351,22 +351,22 @@ BaseType_t xPortStartScheduler( void )
         if( ulImplementedPrioBits == 8 )
         {
             /* When the hardware implements 8 priority bits, there is no way for
-            * the software to configure PRIGROUP to not have sub-priorities. As
-            * a result, the least significant bit is always used for sub-priority
-            * and there are 128 preemption priorities and 2 sub-priorities.
-            *
-            * This may cause some confusion in some cases - for example, if
-            * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
-            * priority interrupts will be masked in Critical Sections as those
-            * are at the same preemption priority. This may appear confusing as
-            * 4 is higher (numerically lower) priority than
-            * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
-            * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
-            * to 4, this confusion does not happen and the behaviour remains the same.
-            *
-            * The following assert ensures that the sub-priority bit in the
-            * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
-            * confusion. */
+             * the software to configure PRIGROUP to not have sub-priorities. As
+             * a result, the least significant bit is always used for sub-priority
+             * and there are 128 preemption priorities and 2 sub-priorities.
+             *
+             * This may cause some confusion in some cases - for example, if
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
+             * priority interrupts will be masked in Critical Sections as those
+             * are at the same preemption priority. This may appear confusing as
+             * 4 is higher (numerically lower) priority than
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
+             * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
+             * to 4, this confusion does not happen and the behaviour remains the same.
+             *
+             * The following assert ensures that the sub-priority bit in the
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
+             * confusion. */
             configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
             ulMaxPRIGROUPValue = 0;
         }
diff --git a/portable/GCC/ARM_CM4F/portmacro.h b/portable/GCC/ARM_CM4F/portmacro.h
index 532eefa74..5d70c0e22 100644
--- a/portable/GCC/ARM_CM4F/portmacro.h
+++ b/portable/GCC/ARM_CM4F/portmacro.h
@@ -28,7 +28,7 @@
 
 
 #ifndef PORTMACRO_H
-    #define PORTMACRO_H
+#define PORTMACRO_H
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
@@ -47,45 +47,45 @@
  */
 
 /* Type definitions. */
-    #define portCHAR          char
-    #define portFLOAT         float
-    #define portDOUBLE        double
-    #define portLONG          long
-    #define portSHORT         short
-    #define portSTACK_TYPE    uint32_t
-    #define portBASE_TYPE     long
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-    typedef portSTACK_TYPE   StackType_t;
-    typedef long             BaseType_t;
-    typedef unsigned long    UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
-    #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-        typedef uint16_t     TickType_t;
-        #define portMAX_DELAY              ( TickType_t ) 0xffff
-    #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-        typedef uint32_t     TickType_t;
-        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
  * not need to be guarded with a critical section. */
-        #define portTICK_TYPE_IS_ATOMIC    1
-    #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_64_BITS )
-        typedef uint64_t     TickType_t;
-        #define portMAX_DELAY              ( TickType_t ) 0xffffffffffffffffULL
-    #else
-        #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
-    #endif
+    #define portTICK_TYPE_IS_ATOMIC    1
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_64_BITS )
+    typedef uint64_t TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffffffffffffffffULL
+#else /* if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) */
+    #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+#endif /* if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) */
 /*-----------------------------------------------------------*/
 
 /* Architecture specifics. */
-    #define portSTACK_GROWTH      ( -1 )
-    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-    #define portBYTE_ALIGNMENT    8
-    #define portDONT_DISCARD      __attribute__( ( used ) )
+#define portSTACK_GROWTH      ( -1 )
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT    8
+#define portDONT_DISCARD      __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
 /* Scheduler utilities. */
-    #define portYIELD()                                 \
+#define portYIELD()                                     \
     {                                                   \
         /* Set a PendSV to request a context switch. */ \
         portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
@@ -96,154 +96,154 @@
         __asm volatile ( "isb" );                                  \
     }
 
-    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
-    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-    #define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 )
-    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+#define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired != pdFALSE ) portYIELD( ); } while( 0 )
+#define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
 /* Critical section management. */
-    extern void vPortEnterCritical( void );
-    extern void vPortExitCritical( void );
-    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulPortRaiseBASEPRI()
-    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vPortSetBASEPRI( x )
-    #define portDISABLE_INTERRUPTS()                  vPortRaiseBASEPRI()
-    #define portENABLE_INTERRUPTS()                   vPortSetBASEPRI( 0 )
-    #define portENTER_CRITICAL()                      vPortEnterCritical()
-    #define portEXIT_CRITICAL()                       vPortExitCritical()
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+#define portSET_INTERRUPT_MASK_FROM_ISR()         ulPortRaiseBASEPRI()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vPortSetBASEPRI( x )
+#define portDISABLE_INTERRUPTS()                  vPortRaiseBASEPRI()
+#define portENABLE_INTERRUPTS()                   vPortSetBASEPRI( 0 )
+#define portENTER_CRITICAL()                      vPortEnterCritical()
+#define portEXIT_CRITICAL()                       vPortExitCritical()
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site.  These are
  * not necessary for to use this port.  They are defined so the common demo files
  * (which build with all the ports) will build. */
-    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
-    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 /*-----------------------------------------------------------*/
 
 /* Tickless idle/low power functionality. */
-    #ifndef portSUPPRESS_TICKS_AND_SLEEP
-        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
-        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
-    #endif
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+    extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+    #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
 /*-----------------------------------------------------------*/
 
 /* Architecture specific optimisations. */
-    #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
-    #endif
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+    #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
+#endif
 
-    #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
 
 /* Generic helper function. */
-        __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
-        {
-            uint8_t ucReturn;
+    __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
+    {
+        uint8_t ucReturn;
 
-            __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
+        __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
 
-            return ucReturn;
-        }
+        return ucReturn;
+    }
 
 /* Check the configuration. */
-        #if ( configMAX_PRIORITIES > 32 )
-            #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
-        #endif
+    #if ( configMAX_PRIORITIES > 32 )
+        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+    #endif
 
 /* Store/clear the ready priorities in a bit map. */
-        #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-        #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 
 /*-----------------------------------------------------------*/
 
-        #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
 
-    #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 
 /*-----------------------------------------------------------*/
 
-    #ifdef configASSERT
-        void vPortValidateInterruptPriority( void );
-        #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
-    #endif
+#ifdef configASSERT
+    void vPortValidateInterruptPriority( void );
+    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
+#endif
 
 /* portNOP() is not required by this port. */
-    #define portNOP()
+#define portNOP()
 
-    #define portINLINE              __inline
+#define portINLINE              __inline
 
-    #ifndef portFORCE_INLINE
-        #define portFORCE_INLINE    inline __attribute__( ( always_inline ) )
-    #endif
+#ifndef portFORCE_INLINE
+    #define portFORCE_INLINE    inline __attribute__( ( always_inline ) )
+#endif
 
-    portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
+portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
+{
+    uint32_t ulCurrentInterrupt;
+    BaseType_t xReturn;
+
+    /* Obtain the number of the currently executing interrupt. */
+    __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+    if( ulCurrentInterrupt == 0 )
     {
-        uint32_t ulCurrentInterrupt;
-        BaseType_t xReturn;
-
-        /* Obtain the number of the currently executing interrupt. */
-        __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
-
-        if( ulCurrentInterrupt == 0 )
-        {
-            xReturn = pdFALSE;
-        }
-        else
-        {
-            xReturn = pdTRUE;
-        }
-
-        return xReturn;
+        xReturn = pdFALSE;
     }
+    else
+    {
+        xReturn = pdTRUE;
+    }
+
+    return xReturn;
+}
 
 /*-----------------------------------------------------------*/
 
-    portFORCE_INLINE static void vPortRaiseBASEPRI( void )
-    {
-        uint32_t ulNewBASEPRI;
+portFORCE_INLINE static void vPortRaiseBASEPRI( void )
+{
+    uint32_t ulNewBASEPRI;
 
-        __asm volatile
-        (
-            "   mov %0, %1                                              \n"\
-            "   msr basepri, %0                                         \n"\
-            "   isb                                                     \n"\
-            "   dsb                                                     \n"\
-            : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
-        );
-    }
+    __asm volatile
+    (
+        "   mov %0, %1                                              \n" \
+        "   msr basepri, %0                                         \n" \
+        "   isb                                                     \n" \
+        "   dsb                                                     \n" \
+        : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+    );
+}
 
 /*-----------------------------------------------------------*/
 
-    portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
-    {
-        uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
+portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
+{
+    uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
 
-        __asm volatile
-        (
-            "   mrs %0, basepri                                         \n"\
-            "   mov %1, %2                                              \n"\
-            "   msr basepri, %1                                         \n"\
-            "   isb                                                     \n"\
-            "   dsb                                                     \n"\
-            : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
-        );
+    __asm volatile
+    (
+        "   mrs %0, basepri                                         \n" \
+        "   mov %1, %2                                              \n" \
+        "   msr basepri, %1                                         \n" \
+        "   isb                                                     \n" \
+        "   dsb                                                     \n" \
+        : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+    );
 
-        /* This return will not be reached but is necessary to prevent compiler
-         * warnings. */
-        return ulOriginalBASEPRI;
-    }
+    /* This return will not be reached but is necessary to prevent compiler
+     * warnings. */
+    return ulOriginalBASEPRI;
+}
 /*-----------------------------------------------------------*/
 
-    portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
-    {
-        __asm volatile
-        (
-            "   msr basepri, %0 "::"r" ( ulNewMaskValue ) : "memory"
-        );
-    }
+portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
+{
+    __asm volatile
+    (
+        "   msr basepri, %0 " ::"r" ( ulNewMaskValue ) : "memory"
+    );
+}
 /*-----------------------------------------------------------*/
 
-    #define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
+#define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/GCC/ARM_CM4_MPU/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM4_MPU/mpu_wrappers_v2_asm.c
index 76c6029af..9a8cf55eb 100644
--- a/portable/GCC/ARM_CM4_MPU/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM4_MPU/mpu_wrappers_v2_asm.c
@@ -44,2274 +44,2274 @@
 
 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
 
-#if ( INCLUDE_xTaskDelayUntil == 1 )
+    #if ( INCLUDE_xTaskDelayUntil == 1 )
 
-BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
-                                const TickType_t xTimeIncrement ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
+                                        const TickType_t xTimeIncrement ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
-                                const TickType_t xTimeIncrement ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskDelayUntilImpl                       \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskDelayUntil_Unpriv                        \n"
-        " MPU_xTaskDelayUntil_Priv:                             \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskDelayUntilImpl                         \n"
-        " MPU_xTaskDelayUntil_Unpriv:                           \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskDelayUntilImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
+                                        const TickType_t xTimeIncrement ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskDelayUntilImpl                       \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskDelayUntil_Unpriv                        \n"
+                " MPU_xTaskDelayUntil_Priv:                             \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskDelayUntilImpl                         \n"
+                " MPU_xTaskDelayUntil_Unpriv:                           \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskDelayUntilImpl                        \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */
+    #endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_xTaskAbortDelay == 1 )
+    #if ( INCLUDE_xTaskAbortDelay == 1 )
 
-BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskAbortDelayImpl                       \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskAbortDelay_Unpriv                        \n"
-        " MPU_xTaskAbortDelay_Priv:                             \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskAbortDelayImpl                         \n"
-        " MPU_xTaskAbortDelay_Unpriv:                           \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskAbortDelayImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskAbortDelayImpl                       \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskAbortDelay_Unpriv                        \n"
+                " MPU_xTaskAbortDelay_Priv:                             \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskAbortDelayImpl                         \n"
+                " MPU_xTaskAbortDelay_Unpriv:                           \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskAbortDelayImpl                        \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */
+    #endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_vTaskDelay == 1 )
+    #if ( INCLUDE_vTaskDelay == 1 )
 
-void MPU_vTaskDelay( const TickType_t xTicksToDelay ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskDelay( const TickType_t xTicksToDelay ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskDelayImpl                            \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskDelay_Unpriv                             \n"
-        " MPU_vTaskDelay_Priv:                                  \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskDelayImpl                              \n"
-        " MPU_vTaskDelay_Unpriv:                                \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskDelayImpl                             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskDelayImpl                            \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskDelay_Unpriv                             \n"
+                " MPU_vTaskDelay_Priv:                                  \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskDelayImpl                              \n"
+                " MPU_vTaskDelay_Unpriv:                                \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskDelayImpl                             \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_vTaskDelay == 1 ) */
+    #endif /* if ( INCLUDE_vTaskDelay == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_uxTaskPriorityGet == 1 )
+    #if ( INCLUDE_uxTaskPriorityGet == 1 )
 
-UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskPriorityGetImpl                     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTaskPriorityGet_Unpriv                      \n"
-        " MPU_uxTaskPriorityGet_Priv:                           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTaskPriorityGetImpl                       \n"
-        " MPU_uxTaskPriorityGet_Unpriv:                         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskPriorityGetImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskPriorityGetImpl                     \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTaskPriorityGet_Unpriv                      \n"
+                " MPU_uxTaskPriorityGet_Priv:                           \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTaskPriorityGetImpl                       \n"
+                " MPU_uxTaskPriorityGet_Unpriv:                         \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskPriorityGetImpl                      \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */
+    #endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_eTaskGetState == 1 )
+    #if ( INCLUDE_eTaskGetState == 1 )
 
-eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_eTaskGetStateImpl                         \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_eTaskGetState_Unpriv                          \n"
-        " MPU_eTaskGetState_Priv:                               \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_eTaskGetStateImpl                           \n"
-        " MPU_eTaskGetState_Unpriv:                             \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_eTaskGetStateImpl                          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_eTaskGetStateImpl                         \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_eTaskGetState_Unpriv                          \n"
+                " MPU_eTaskGetState_Priv:                               \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_eTaskGetStateImpl                           \n"
+                " MPU_eTaskGetState_Unpriv:                             \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_eTaskGetStateImpl                          \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_eTaskGetState == 1 ) */
+    #endif /* if ( INCLUDE_eTaskGetState == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-void MPU_vTaskGetInfo( TaskHandle_t xTask,
-                       TaskStatus_t * pxTaskStatus,
-                       BaseType_t xGetFreeStackSpace,
-                       eTaskState eState ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskGetInfo( TaskHandle_t xTask,
+                               TaskStatus_t * pxTaskStatus,
+                               BaseType_t xGetFreeStackSpace,
+                               eTaskState eState ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskGetInfo( TaskHandle_t xTask,
-                       TaskStatus_t * pxTaskStatus,
-                       BaseType_t xGetFreeStackSpace,
-                       eTaskState eState ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskGetInfoImpl                          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskGetInfo_Unpriv                           \n"
-        " MPU_vTaskGetInfo_Priv:                                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskGetInfoImpl                            \n"
-        " MPU_vTaskGetInfo_Unpriv:                              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskGetInfoImpl                           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskGetInfo( TaskHandle_t xTask,
+                               TaskStatus_t * pxTaskStatus,
+                               BaseType_t xGetFreeStackSpace,
+                               eTaskState eState ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskGetInfoImpl                          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskGetInfo_Unpriv                           \n"
+                " MPU_vTaskGetInfo_Priv:                                \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskGetInfoImpl                            \n"
+                " MPU_vTaskGetInfo_Unpriv:                              \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskGetInfoImpl                           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
+    #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
+    #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
 
-TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetIdleTaskHandleImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGetIdleTaskHandle_Unpriv                 \n"
-        " MPU_xTaskGetIdleTaskHandle_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGetIdleTaskHandleImpl                  \n"
-        " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetIdleTaskHandleImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetIdleTaskHandleImpl                \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGetIdleTaskHandle_Unpriv                 \n"
+                " MPU_xTaskGetIdleTaskHandle_Priv:                      \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGetIdleTaskHandleImpl                  \n"
+                " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetIdleTaskHandleImpl                 \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */
+    #endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_vTaskSuspend == 1 )
+    #if ( INCLUDE_vTaskSuspend == 1 )
 
-void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSuspendImpl                          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskSuspend_Unpriv                           \n"
-        " MPU_vTaskSuspend_Priv:                                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskSuspendImpl                            \n"
-        " MPU_vTaskSuspend_Unpriv:                              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSuspendImpl                           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskSuspendImpl                          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskSuspend_Unpriv                           \n"
+                " MPU_vTaskSuspend_Priv:                                \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskSuspendImpl                            \n"
+                " MPU_vTaskSuspend_Unpriv:                              \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskSuspendImpl                           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
+    #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_vTaskSuspend == 1 )
+    #if ( INCLUDE_vTaskSuspend == 1 )
 
-void MPU_vTaskResume( TaskHandle_t xTaskToResume ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskResume( TaskHandle_t xTaskToResume ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskResumeImpl                           \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskResume_Unpriv                            \n"
-        " MPU_vTaskResume_Priv:                                 \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskResumeImpl                             \n"
-        " MPU_vTaskResume_Unpriv:                               \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskResumeImpl                            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskResumeImpl                           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskResume_Unpriv                            \n"
+                " MPU_vTaskResume_Priv:                                 \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskResumeImpl                             \n"
+                " MPU_vTaskResume_Unpriv:                               \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskResumeImpl                            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
+    #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
 /*-----------------------------------------------------------*/
 
-TickType_t MPU_xTaskGetTickCount( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    TickType_t MPU_xTaskGetTickCount( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TickType_t MPU_xTaskGetTickCount( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetTickCountImpl                     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGetTickCount_Unpriv                      \n"
-        " MPU_xTaskGetTickCount_Priv:                           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGetTickCountImpl                       \n"
-        " MPU_xTaskGetTickCount_Unpriv:                         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetTickCountImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    TickType_t MPU_xTaskGetTickCount( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xTaskGetTickCountImpl                     \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xTaskGetTickCount_Unpriv                      \n"
+            " MPU_xTaskGetTickCount_Priv:                           \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xTaskGetTickCountImpl                       \n"
+            " MPU_xTaskGetTickCount_Unpriv:                         \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xTaskGetTickCountImpl                      \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetNumberOfTasksImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTaskGetNumberOfTasks_Unpriv                 \n"
-        " MPU_uxTaskGetNumberOfTasks_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTaskGetNumberOfTasksImpl                  \n"
-        " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetNumberOfTasksImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_uxTaskGetNumberOfTasksImpl                \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_uxTaskGetNumberOfTasks_Unpriv                 \n"
+            " MPU_uxTaskGetNumberOfTasks_Priv:                      \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_uxTaskGetNumberOfTasksImpl                  \n"
+            " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_uxTaskGetNumberOfTasksImpl                 \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configGENERATE_RUN_TIME_STATS == 1 )
+    #if ( configGENERATE_RUN_TIME_STATS == 1 )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetRunTimeCounterImpl               \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGetRunTimeCounter_Unpriv                \n"
-        " MPU_ulTaskGetRunTimeCounter_Priv:                     \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGetRunTimeCounterImpl                 \n"
-        " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetRunTimeCounterImpl                \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetRunTimeCounterImpl               \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGetRunTimeCounter_Unpriv                \n"
+                " MPU_ulTaskGetRunTimeCounter_Priv:                     \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGetRunTimeCounterImpl                 \n"
+                " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetRunTimeCounterImpl                \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configGENERATE_RUN_TIME_STATS == 1 )
+    #if ( configGENERATE_RUN_TIME_STATS == 1 )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetRunTimePercentImpl               \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGetRunTimePercent_Unpriv                \n"
-        " MPU_ulTaskGetRunTimePercent_Priv:                     \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGetRunTimePercentImpl                 \n"
-        " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetRunTimePercentImpl                \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetRunTimePercentImpl               \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGetRunTimePercent_Unpriv                \n"
+                " MPU_ulTaskGetRunTimePercent_Priv:                     \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGetRunTimePercentImpl                 \n"
+                " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetRunTimePercentImpl                \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+    #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetIdleRunTimePercentImpl           \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv            \n"
-        " MPU_ulTaskGetIdleRunTimePercent_Priv:                 \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGetIdleRunTimePercentImpl             \n"
-        " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetIdleRunTimePercentImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetIdleRunTimePercentImpl           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv            \n"
+                " MPU_ulTaskGetIdleRunTimePercent_Priv:                 \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGetIdleRunTimePercentImpl             \n"
+                " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetIdleRunTimePercentImpl            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+    #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetIdleRunTimeCounterImpl           \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv            \n"
-        " MPU_ulTaskGetIdleRunTimeCounter_Priv:                 \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGetIdleRunTimeCounterImpl             \n"
-        " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetIdleRunTimeCounterImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetIdleRunTimeCounterImpl           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv            \n"
+                " MPU_ulTaskGetIdleRunTimeCounter_Priv:                 \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGetIdleRunTimeCounterImpl             \n"
+                " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetIdleRunTimeCounterImpl            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+    #if ( configUSE_APPLICATION_TASK_TAG == 1 )
 
-void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
-                                     TaskHookFunction_t pxHookFunction ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
+                                             TaskHookFunction_t pxHookFunction ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
-                                     TaskHookFunction_t pxHookFunction ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSetApplicationTaskTagImpl            \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskSetApplicationTaskTag_Unpriv             \n"
-        " MPU_vTaskSetApplicationTaskTag_Priv:                  \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskSetApplicationTaskTagImpl              \n"
-        " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSetApplicationTaskTagImpl             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
+                                             TaskHookFunction_t pxHookFunction ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskSetApplicationTaskTagImpl            \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskSetApplicationTaskTag_Unpriv             \n"
+                " MPU_vTaskSetApplicationTaskTag_Priv:                  \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskSetApplicationTaskTagImpl              \n"
+                " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskSetApplicationTaskTagImpl             \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
+    #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+    #if ( configUSE_APPLICATION_TASK_TAG == 1 )
 
-TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetApplicationTaskTagImpl            \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGetApplicationTaskTag_Unpriv             \n"
-        " MPU_xTaskGetApplicationTaskTag_Priv:                  \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGetApplicationTaskTagImpl              \n"
-        " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetApplicationTaskTagImpl             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetApplicationTaskTagImpl            \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGetApplicationTaskTag_Unpriv             \n"
+                " MPU_xTaskGetApplicationTaskTag_Priv:                  \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGetApplicationTaskTagImpl              \n"
+                " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetApplicationTaskTagImpl             \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
+    #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+    #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
 
-void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
-                                            BaseType_t xIndex,
-                                            void * pvValue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
+                                                    BaseType_t xIndex,
+                                                    void * pvValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
-                                            BaseType_t xIndex,
-                                            void * pvValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSetThreadLocalStoragePointerImpl     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv      \n"
-        " MPU_vTaskSetThreadLocalStoragePointer_Priv:           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskSetThreadLocalStoragePointerImpl       \n"
-        " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSetThreadLocalStoragePointerImpl      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
+                                                    BaseType_t xIndex,
+                                                    void * pvValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskSetThreadLocalStoragePointerImpl     \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv      \n"
+                " MPU_vTaskSetThreadLocalStoragePointer_Priv:           \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskSetThreadLocalStoragePointerImpl       \n"
+                " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskSetThreadLocalStoragePointerImpl      \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
+    #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+    #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
 
-void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
-                                               BaseType_t xIndex ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
+                                                       BaseType_t xIndex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
-                                               BaseType_t xIndex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pvTaskGetThreadLocalStoragePointerImpl    \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv     \n"
-        " MPU_pvTaskGetThreadLocalStoragePointer_Priv:          \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_pvTaskGetThreadLocalStoragePointerImpl      \n"
-        " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pvTaskGetThreadLocalStoragePointerImpl     \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
+                                                       BaseType_t xIndex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pvTaskGetThreadLocalStoragePointerImpl    \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv     \n"
+                " MPU_pvTaskGetThreadLocalStoragePointer_Priv:          \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_pvTaskGetThreadLocalStoragePointerImpl      \n"
+                " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pvTaskGetThreadLocalStoragePointerImpl     \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
+    #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
-                                      const UBaseType_t uxArraySize,
-                                      configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
+                                              const UBaseType_t uxArraySize,
+                                              configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
-                                      const UBaseType_t uxArraySize,
-                                      configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetSystemStateImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTaskGetSystemState_Unpriv                   \n"
-        " MPU_uxTaskGetSystemState_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTaskGetSystemStateImpl                    \n"
-        " MPU_uxTaskGetSystemState_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetSystemStateImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
+                                              const UBaseType_t uxArraySize,
+                                              configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskGetSystemStateImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTaskGetSystemState_Unpriv                   \n"
+                " MPU_uxTaskGetSystemState_Priv:                        \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTaskGetSystemStateImpl                    \n"
+                " MPU_uxTaskGetSystemState_Unpriv:                      \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskGetSystemStateImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
+    #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
+    #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
 
-UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetStackHighWaterMarkImpl           \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTaskGetStackHighWaterMark_Unpriv            \n"
-        " MPU_uxTaskGetStackHighWaterMark_Priv:                 \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTaskGetStackHighWaterMarkImpl             \n"
-        " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetStackHighWaterMarkImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskGetStackHighWaterMarkImpl           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTaskGetStackHighWaterMark_Unpriv            \n"
+                " MPU_uxTaskGetStackHighWaterMark_Priv:                 \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTaskGetStackHighWaterMarkImpl             \n"
+                " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskGetStackHighWaterMarkImpl            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */
+    #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
+    #if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
 
-configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetStackHighWaterMark2Impl          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv           \n"
-        " MPU_uxTaskGetStackHighWaterMark2_Priv:                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTaskGetStackHighWaterMark2Impl            \n"
-        " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetStackHighWaterMark2Impl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskGetStackHighWaterMark2Impl          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv           \n"
+                " MPU_uxTaskGetStackHighWaterMark2_Priv:                \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTaskGetStackHighWaterMark2Impl            \n"
+                " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskGetStackHighWaterMark2Impl           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */
+    #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
+    #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
 
-TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetCurrentTaskHandleImpl             \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGetCurrentTaskHandle_Unpriv              \n"
-        " MPU_xTaskGetCurrentTaskHandle_Priv:                   \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGetCurrentTaskHandleImpl               \n"
-        " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetCurrentTaskHandleImpl              \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetCurrentTaskHandleImpl             \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGetCurrentTaskHandle_Unpriv              \n"
+                " MPU_xTaskGetCurrentTaskHandle_Priv:                   \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGetCurrentTaskHandleImpl               \n"
+                " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetCurrentTaskHandleImpl              \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
+    #endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_xTaskGetSchedulerState == 1 )
+    #if ( INCLUDE_xTaskGetSchedulerState == 1 )
 
-BaseType_t MPU_xTaskGetSchedulerState( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGetSchedulerState( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGetSchedulerState( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetSchedulerStateImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGetSchedulerState_Unpriv                 \n"
-        " MPU_xTaskGetSchedulerState_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGetSchedulerStateImpl                  \n"
-        " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetSchedulerStateImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGetSchedulerState( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetSchedulerStateImpl                \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGetSchedulerState_Unpriv                 \n"
+                " MPU_xTaskGetSchedulerState_Priv:                      \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGetSchedulerStateImpl                  \n"
+                " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetSchedulerStateImpl                 \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */
+    #endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */
 /*-----------------------------------------------------------*/
 
-void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSetTimeOutStateImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskSetTimeOutState_Unpriv                   \n"
-        " MPU_vTaskSetTimeOutState_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskSetTimeOutStateImpl                    \n"
-        " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSetTimeOutStateImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_vTaskSetTimeOutStateImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_vTaskSetTimeOutState_Unpriv                   \n"
+            " MPU_vTaskSetTimeOutState_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_vTaskSetTimeOutStateImpl                    \n"
+            " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_vTaskSetTimeOutStateImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
-                                     TickType_t * const pxTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
+                                         TickType_t * const pxTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
-                                     TickType_t * const pxTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskCheckForTimeOutImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskCheckForTimeOut_Unpriv                   \n"
-        " MPU_xTaskCheckForTimeOut_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskCheckForTimeOutImpl                    \n"
-        " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskCheckForTimeOutImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
+                                         TickType_t * const pxTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xTaskCheckForTimeOutImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xTaskCheckForTimeOut_Unpriv                   \n"
+            " MPU_xTaskCheckForTimeOut_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xTaskCheckForTimeOutImpl                    \n"
+            " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xTaskCheckForTimeOutImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                   UBaseType_t uxIndexToNotify,
-                                   uint32_t ulValue,
-                                   eNotifyAction eAction,
-                                   uint32_t * pulPreviousNotificationValue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
+                                           UBaseType_t uxIndexToNotify,
+                                           uint32_t ulValue,
+                                           eNotifyAction eAction,
+                                           uint32_t * pulPreviousNotificationValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                   UBaseType_t uxIndexToNotify,
-                                   uint32_t ulValue,
-                                   eNotifyAction eAction,
-                                   uint32_t * pulPreviousNotificationValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGenericNotifyImpl                    \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGenericNotify_Unpriv                     \n"
-        " MPU_xTaskGenericNotify_Priv:                          \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGenericNotifyImpl                      \n"
-        " MPU_xTaskGenericNotify_Unpriv:                        \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGenericNotifyImpl                     \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
+                                           UBaseType_t uxIndexToNotify,
+                                           uint32_t ulValue,
+                                           eNotifyAction eAction,
+                                           uint32_t * pulPreviousNotificationValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGenericNotifyImpl                    \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGenericNotify_Unpriv                     \n"
+                " MPU_xTaskGenericNotify_Priv:                          \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGenericNotifyImpl                      \n"
+                " MPU_xTaskGenericNotify_Unpriv:                        \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGenericNotifyImpl                     \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                       uint32_t ulBitsToClearOnEntry,
-                                       uint32_t ulBitsToClearOnExit,
-                                       uint32_t * pulNotificationValue,
-                                       TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
+                                               uint32_t ulBitsToClearOnEntry,
+                                               uint32_t ulBitsToClearOnExit,
+                                               uint32_t * pulNotificationValue,
+                                               TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                       uint32_t ulBitsToClearOnEntry,
-                                       uint32_t ulBitsToClearOnExit,
-                                       uint32_t * pulNotificationValue,
-                                       TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGenericNotifyWaitImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGenericNotifyWait_Unpriv                 \n"
-        " MPU_xTaskGenericNotifyWait_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGenericNotifyWaitImpl                  \n"
-        " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGenericNotifyWaitImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
+                                               uint32_t ulBitsToClearOnEntry,
+                                               uint32_t ulBitsToClearOnExit,
+                                               uint32_t * pulNotificationValue,
+                                               TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGenericNotifyWaitImpl                \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGenericNotifyWait_Unpriv                 \n"
+                " MPU_xTaskGenericNotifyWait_Priv:                      \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGenericNotifyWaitImpl                  \n"
+                " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGenericNotifyWaitImpl                 \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
-                                      BaseType_t xClearCountOnExit,
-                                      TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
+                                              BaseType_t xClearCountOnExit,
+                                              TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
-                                      BaseType_t xClearCountOnExit,
-                                      TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGenericNotifyTakeImpl               \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGenericNotifyTake_Unpriv                \n"
-        " MPU_ulTaskGenericNotifyTake_Priv:                     \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGenericNotifyTakeImpl                 \n"
-        " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGenericNotifyTakeImpl                \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
+                                              BaseType_t xClearCountOnExit,
+                                              TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGenericNotifyTakeImpl               \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGenericNotifyTake_Unpriv                \n"
+                " MPU_ulTaskGenericNotifyTake_Priv:                     \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGenericNotifyTakeImpl                 \n"
+                " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGenericNotifyTakeImpl                \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
-                                             UBaseType_t uxIndexToClear ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
+                                                     UBaseType_t uxIndexToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
-                                             UBaseType_t uxIndexToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGenericNotifyStateClearImpl          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGenericNotifyStateClear_Unpriv           \n"
-        " MPU_xTaskGenericNotifyStateClear_Priv:                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGenericNotifyStateClearImpl            \n"
-        " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGenericNotifyStateClearImpl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
+                                                     UBaseType_t uxIndexToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGenericNotifyStateClearImpl          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGenericNotifyStateClear_Unpriv           \n"
+                " MPU_xTaskGenericNotifyStateClear_Priv:                \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGenericNotifyStateClearImpl            \n"
+                " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGenericNotifyStateClearImpl           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
-                                            UBaseType_t uxIndexToClear,
-                                            uint32_t ulBitsToClear ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
+                                                    UBaseType_t uxIndexToClear,
+                                                    uint32_t ulBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
-                                            UBaseType_t uxIndexToClear,
-                                            uint32_t ulBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGenericNotifyValueClearImpl         \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGenericNotifyValueClear_Unpriv          \n"
-        " MPU_ulTaskGenericNotifyValueClear_Priv:               \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGenericNotifyValueClearImpl           \n"
-        " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGenericNotifyValueClearImpl          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
+                                                    UBaseType_t uxIndexToClear,
+                                                    uint32_t ulBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGenericNotifyValueClearImpl         \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGenericNotifyValueClear_Unpriv          \n"
+                " MPU_ulTaskGenericNotifyValueClear_Priv:               \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGenericNotifyValueClearImpl           \n"
+                " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGenericNotifyValueClearImpl          \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
-                                  const void * const pvItemToQueue,
-                                  TickType_t xTicksToWait,
-                                  const BaseType_t xCopyPosition ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
+                                      const void * const pvItemToQueue,
+                                      TickType_t xTicksToWait,
+                                      const BaseType_t xCopyPosition ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
-                                  const void * const pvItemToQueue,
-                                  TickType_t xTicksToWait,
-                                  const BaseType_t xCopyPosition ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueGenericSendImpl                     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueGenericSend_Unpriv                      \n"
-        " MPU_xQueueGenericSend_Priv:                           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueGenericSendImpl                       \n"
-        " MPU_xQueueGenericSend_Unpriv:                         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueGenericSendImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
+                                      const void * const pvItemToQueue,
+                                      TickType_t xTicksToWait,
+                                      const BaseType_t xCopyPosition ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueueGenericSendImpl                     \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xQueueGenericSend_Unpriv                      \n"
+            " MPU_xQueueGenericSend_Priv:                           \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xQueueGenericSendImpl                       \n"
+            " MPU_xQueueGenericSend_Unpriv:                         \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueueGenericSendImpl                      \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxQueueMessagesWaitingImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxQueueMessagesWaiting_Unpriv                 \n"
-        " MPU_uxQueueMessagesWaiting_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxQueueMessagesWaitingImpl                  \n"
-        " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxQueueMessagesWaitingImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_uxQueueMessagesWaitingImpl                \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_uxQueueMessagesWaiting_Unpriv                 \n"
+            " MPU_uxQueueMessagesWaiting_Priv:                      \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_uxQueueMessagesWaitingImpl                  \n"
+            " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_uxQueueMessagesWaitingImpl                 \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxQueueSpacesAvailableImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxQueueSpacesAvailable_Unpriv                 \n"
-        " MPU_uxQueueSpacesAvailable_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxQueueSpacesAvailableImpl                  \n"
-        " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxQueueSpacesAvailableImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_uxQueueSpacesAvailableImpl                \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_uxQueueSpacesAvailable_Unpriv                 \n"
+            " MPU_uxQueueSpacesAvailable_Priv:                      \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_uxQueueSpacesAvailableImpl                  \n"
+            " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_uxQueueSpacesAvailableImpl                 \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
-                              void * const pvBuffer,
-                              TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
+                                  void * const pvBuffer,
+                                  TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
-                              void * const pvBuffer,
-                              TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueReceiveImpl                         \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueReceive_Unpriv                          \n"
-        " MPU_xQueueReceive_Priv:                               \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueReceiveImpl                           \n"
-        " MPU_xQueueReceive_Unpriv:                             \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueReceiveImpl                          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
+                                  void * const pvBuffer,
+                                  TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueueReceiveImpl                         \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xQueueReceive_Unpriv                          \n"
+            " MPU_xQueueReceive_Priv:                               \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xQueueReceiveImpl                           \n"
+            " MPU_xQueueReceive_Unpriv:                             \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueueReceiveImpl                          \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
-                           void * const pvBuffer,
-                           TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
+                               void * const pvBuffer,
+                               TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
-                           void * const pvBuffer,
-                           TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueuePeekImpl                            \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueuePeek_Unpriv                             \n"
-        " MPU_xQueuePeek_Priv:                                  \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueuePeekImpl                              \n"
-        " MPU_xQueuePeek_Unpriv:                                \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueuePeekImpl                             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
+                               void * const pvBuffer,
+                               TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueuePeekImpl                            \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xQueuePeek_Unpriv                             \n"
+            " MPU_xQueuePeek_Priv:                                  \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xQueuePeekImpl                              \n"
+            " MPU_xQueuePeek_Unpriv:                                \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueuePeekImpl                             \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
-                                    TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
+                                        TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
-                                    TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueSemaphoreTakeImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueSemaphoreTake_Unpriv                    \n"
-        " MPU_xQueueSemaphoreTake_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueSemaphoreTakeImpl                     \n"
-        " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueSemaphoreTakeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
+                                        TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueueSemaphoreTakeImpl                   \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xQueueSemaphoreTake_Unpriv                    \n"
+            " MPU_xQueueSemaphoreTake_Priv:                         \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xQueueSemaphoreTakeImpl                     \n"
+            " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueueSemaphoreTakeImpl                    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+    #if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
 
-TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueGetMutexHolderImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueGetMutexHolder_Unpriv                   \n"
-        " MPU_xQueueGetMutexHolder_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueGetMutexHolderImpl                    \n"
-        " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueGetMutexHolderImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueGetMutexHolderImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueGetMutexHolder_Unpriv                   \n"
+                " MPU_xQueueGetMutexHolder_Priv:                        \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueGetMutexHolderImpl                    \n"
+                " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueGetMutexHolderImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */
+    #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+    #if ( configUSE_RECURSIVE_MUTEXES == 1 )
 
-BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
-                                         TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+                                                 TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+        BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+                                                 TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueTakeMutexRecursiveImpl              \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueTakeMutexRecursive_Unpriv               \n"
+                " MPU_xQueueTakeMutexRecursive_Priv:                    \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueTakeMutexRecursiveImpl                \n"
+                " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueTakeMutexRecursiveImpl               \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_RECURSIVE_MUTEXES == 1 )
+
+        BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueGiveMutexRecursiveImpl              \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueGiveMutexRecursive_Unpriv               \n"
+                " MPU_xQueueGiveMutexRecursive_Priv:                    \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueGiveMutexRecursiveImpl                \n"
+                " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueGiveMutexRecursiveImpl               \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_QUEUE_SETS == 1 )
+
+        QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
+                                                        const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
+                                                        const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueSelectFromSetImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueSelectFromSet_Unpriv                    \n"
+                " MPU_xQueueSelectFromSet_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueSelectFromSetImpl                     \n"
+                " MPU_xQueueSelectFromSet_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueSelectFromSetImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_QUEUE_SETS == 1 )
+
+        BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                                       QueueSetHandle_t xQueueSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                                       QueueSetHandle_t xQueueSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueAddToSetImpl                        \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueAddToSet_Unpriv                         \n"
+                " MPU_xQueueAddToSet_Priv:                              \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueAddToSetImpl                          \n"
+                " MPU_xQueueAddToSet_Unpriv:                            \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueAddToSetImpl                         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+        void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
+                                      const char * pcName ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
+                                      const char * pcName ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vQueueAddToRegistryImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vQueueAddToRegistry_Unpriv                    \n"
+                " MPU_vQueueAddToRegistry_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vQueueAddToRegistryImpl                     \n"
+                " MPU_vQueueAddToRegistry_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vQueueAddToRegistryImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+        void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vQueueUnregisterQueueImpl                 \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vQueueUnregisterQueue_Unpriv                  \n"
+                " MPU_vQueueUnregisterQueue_Priv:                       \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vQueueUnregisterQueueImpl                   \n"
+                " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vQueueUnregisterQueueImpl                  \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+        const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pcQueueGetNameImpl                        \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_pcQueueGetName_Unpriv                         \n"
+                " MPU_pcQueueGetName_Priv:                              \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_pcQueueGetNameImpl                          \n"
+                " MPU_pcQueueGetName_Unpriv:                            \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pcQueueGetNameImpl                         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pvTimerGetTimerIDImpl                     \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_pvTimerGetTimerID_Unpriv                      \n"
+                " MPU_pvTimerGetTimerID_Priv:                           \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_pvTimerGetTimerIDImpl                       \n"
+                " MPU_pvTimerGetTimerID_Unpriv:                         \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pvTimerGetTimerIDImpl                      \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
+                                   void * pvNewID ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
+                                   void * pvNewID ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTimerSetTimerIDImpl                      \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTimerSetTimerID_Unpriv                       \n"
+                " MPU_vTimerSetTimerID_Priv:                            \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTimerSetTimerIDImpl                        \n"
+                " MPU_vTimerSetTimerID_Unpriv:                          \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTimerSetTimerIDImpl                       \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerIsTimerActiveImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerIsTimerActive_Unpriv                    \n"
+                " MPU_xTimerIsTimerActive_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerIsTimerActiveImpl                     \n"
+                " MPU_xTimerIsTimerActive_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerIsTimerActiveImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetTimerDaemonTaskHandleImpl        \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv         \n"
+                " MPU_xTimerGetTimerDaemonTaskHandle_Priv:              \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerGetTimerDaemonTaskHandleImpl          \n"
+                " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetTimerDaemonTaskHandleImpl         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                                     const BaseType_t xCommandID,
+                                                     const TickType_t xOptionalValue,
+                                                     BaseType_t * const pxHigherPriorityTaskWoken,
+                                                     const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                                     const BaseType_t xCommandID,
+                                                     const TickType_t xOptionalValue,
+                                                     BaseType_t * const pxHigherPriorityTaskWoken,
+                                                     const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                               \n"
+                " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
+                "                                                               \n"
+                " push {r0}                                                     \n"
+                " mrs r0, control                                               \n"
+                " tst r0, #1                                                    \n"
+                " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
+                " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
+                "     pop {r0}                                                  \n"
+                "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
+                " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
+                "     pop {r0}                                                  \n"
+                "     svc %0                                                    \n"
+                "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
+                "     svc %1                                                    \n"
+                "     bx lr                                                     \n"
+                "                                                               \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pcTimerGetNameImpl                        \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_pcTimerGetName_Unpriv                         \n"
+                " MPU_pcTimerGetName_Priv:                              \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_pcTimerGetNameImpl                          \n"
+                " MPU_pcTimerGetName_Unpriv:                            \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pcTimerGetNameImpl                         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
+                                      const BaseType_t uxAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
+                                      const BaseType_t uxAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTimerSetReloadModeImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTimerSetReloadMode_Unpriv                    \n"
+                " MPU_vTimerSetReloadMode_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTimerSetReloadModeImpl                     \n"
+                " MPU_vTimerSetReloadMode_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTimerSetReloadModeImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetReloadModeImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerGetReloadMode_Unpriv                    \n"
+                " MPU_xTimerGetReloadMode_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerGetReloadModeImpl                     \n"
+                " MPU_xTimerGetReloadMode_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetReloadModeImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTimerGetReloadModeImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTimerGetReloadMode_Unpriv                   \n"
+                " MPU_uxTimerGetReloadMode_Priv:                        \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTimerGetReloadModeImpl                    \n"
+                " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTimerGetReloadModeImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetPeriodImpl                       \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerGetPeriod_Unpriv                        \n"
+                " MPU_xTimerGetPeriod_Priv:                             \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerGetPeriodImpl                         \n"
+                " MPU_xTimerGetPeriod_Unpriv:                           \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetPeriodImpl                        \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetExpiryTimeImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerGetExpiryTime_Unpriv                    \n"
+                " MPU_xTimerGetExpiryTime_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerGetExpiryTimeImpl                     \n"
+                " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetExpiryTimeImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         const BaseType_t xClearOnExit,
+                                         const BaseType_t xWaitForAllBits,
+                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         const BaseType_t xClearOnExit,
+                                         const BaseType_t xWaitForAllBits,
                                          TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueTakeMutexRecursiveImpl              \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueTakeMutexRecursive_Unpriv               \n"
-        " MPU_xQueueTakeMutexRecursive_Priv:                    \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueTakeMutexRecursiveImpl                \n"
-        " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueTakeMutexRecursiveImpl               \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupWaitBitsImpl                   \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
+            " MPU_xEventGroupWaitBits_Priv:                         \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xEventGroupWaitBitsImpl                     \n"
+            " MPU_xEventGroupWaitBits_Unpriv:                       \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupWaitBitsImpl                    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                          const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueGiveMutexRecursiveImpl              \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueGiveMutexRecursive_Unpriv               \n"
-        " MPU_xQueueGiveMutexRecursive_Priv:                    \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueGiveMutexRecursiveImpl                \n"
-        " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueGiveMutexRecursiveImpl               \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                          const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupClearBitsImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xEventGroupClearBits_Unpriv                   \n"
+            " MPU_xEventGroupClearBits_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xEventGroupClearBitsImpl                    \n"
+            " MPU_xEventGroupClearBits_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupClearBitsImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_QUEUE_SETS == 1 )
+    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                        const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
-                                                const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
-                                                const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueSelectFromSetImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueSelectFromSet_Unpriv                    \n"
-        " MPU_xQueueSelectFromSet_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueSelectFromSetImpl                     \n"
-        " MPU_xQueueSelectFromSet_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueSelectFromSetImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                        const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupSetBitsImpl                    \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xEventGroupSetBits_Unpriv                     \n"
+            " MPU_xEventGroupSetBits_Priv:                          \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xEventGroupSetBitsImpl                      \n"
+            " MPU_xEventGroupSetBits_Unpriv:                        \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupSetBitsImpl                     \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_QUEUE_SETS == 1 )
-
-BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
-                               QueueSetHandle_t xQueueSet ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
-                               QueueSetHandle_t xQueueSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueAddToSetImpl                        \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueAddToSet_Unpriv                         \n"
-        " MPU_xQueueAddToSet_Priv:                              \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueAddToSetImpl                          \n"
-        " MPU_xQueueAddToSet_Unpriv:                            \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueAddToSetImpl                         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_QUEUE_SETS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
-                              const char * pcName ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
-                              const char * pcName ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vQueueAddToRegistryImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vQueueAddToRegistry_Unpriv                    \n"
-        " MPU_vQueueAddToRegistry_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vQueueAddToRegistryImpl                     \n"
-        " MPU_vQueueAddToRegistry_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vQueueAddToRegistryImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vQueueUnregisterQueueImpl                 \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vQueueUnregisterQueue_Unpriv                  \n"
-        " MPU_vQueueUnregisterQueue_Priv:                       \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vQueueUnregisterQueueImpl                   \n"
-        " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vQueueUnregisterQueueImpl                  \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pcQueueGetNameImpl                        \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_pcQueueGetName_Unpriv                         \n"
-        " MPU_pcQueueGetName_Priv:                              \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_pcQueueGetNameImpl                          \n"
-        " MPU_pcQueueGetName_Unpriv:                            \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pcQueueGetNameImpl                         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pvTimerGetTimerIDImpl                     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_pvTimerGetTimerID_Unpriv                      \n"
-        " MPU_pvTimerGetTimerID_Priv:                           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_pvTimerGetTimerIDImpl                       \n"
-        " MPU_pvTimerGetTimerID_Unpriv:                         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pvTimerGetTimerIDImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
-                           void * pvNewID ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
-                           void * pvNewID ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTimerSetTimerIDImpl                      \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTimerSetTimerID_Unpriv                       \n"
-        " MPU_vTimerSetTimerID_Priv:                            \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTimerSetTimerIDImpl                        \n"
-        " MPU_vTimerSetTimerID_Unpriv:                          \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTimerSetTimerIDImpl                       \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerIsTimerActiveImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTimerIsTimerActive_Unpriv                    \n"
-        " MPU_xTimerIsTimerActive_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerIsTimerActiveImpl                     \n"
-        " MPU_xTimerIsTimerActive_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerIsTimerActiveImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetTimerDaemonTaskHandleImpl        \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv         \n"
-        " MPU_xTimerGetTimerDaemonTaskHandle_Priv:              \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerGetTimerDaemonTaskHandleImpl          \n"
-        " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetTimerDaemonTaskHandleImpl         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                             const BaseType_t xCommandID,
-                                             const TickType_t xOptionalValue,
-                                             BaseType_t * const pxHigherPriorityTaskWoken,
-                                             const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                             const BaseType_t xCommandID,
-                                             const TickType_t xOptionalValue,
-                                             BaseType_t * const pxHigherPriorityTaskWoken,
-                                             const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                               \n"
-        " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
-        "                                                               \n"
-        " push {r0}                                                     \n"
-        " mrs r0, control                                               \n"
-        " tst r0, #1                                                    \n"
-        " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
-        " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
-        "     pop {r0}                                                  \n"
-        "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
-        " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
-        "     pop {r0}                                                  \n"
-        "     svc %0                                                    \n"
-        "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
-        "     svc %1                                                    \n"
-        "     bx lr                                                     \n"
-        "                                                               \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pcTimerGetNameImpl                        \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_pcTimerGetName_Unpriv                         \n"
-        " MPU_pcTimerGetName_Priv:                              \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_pcTimerGetNameImpl                          \n"
-        " MPU_pcTimerGetName_Unpriv:                            \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pcTimerGetNameImpl                         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                              const BaseType_t uxAutoReload ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                              const BaseType_t uxAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTimerSetReloadModeImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTimerSetReloadMode_Unpriv                    \n"
-        " MPU_vTimerSetReloadMode_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTimerSetReloadModeImpl                     \n"
-        " MPU_vTimerSetReloadMode_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTimerSetReloadModeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetReloadModeImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTimerGetReloadMode_Unpriv                    \n"
-        " MPU_xTimerGetReloadMode_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerGetReloadModeImpl                     \n"
-        " MPU_xTimerGetReloadMode_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetReloadModeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTimerGetReloadModeImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTimerGetReloadMode_Unpriv                   \n"
-        " MPU_uxTimerGetReloadMode_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTimerGetReloadModeImpl                    \n"
-        " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTimerGetReloadModeImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetPeriodImpl                       \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTimerGetPeriod_Unpriv                        \n"
-        " MPU_xTimerGetPeriod_Priv:                             \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerGetPeriodImpl                         \n"
-        " MPU_xTimerGetPeriod_Unpriv:                           \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetPeriodImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetExpiryTimeImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTimerGetExpiryTime_Unpriv                    \n"
-        " MPU_xTimerGetExpiryTime_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerGetExpiryTimeImpl                     \n"
-        " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetExpiryTimeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                     const EventBits_t uxBitsToSet,
                                      const EventBits_t uxBitsToWaitFor,
-                                     const BaseType_t xClearOnExit,
-                                     const BaseType_t xWaitForAllBits,
-                                     TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                     const EventBits_t uxBitsToSet,
                                      const EventBits_t uxBitsToWaitFor,
-                                     const BaseType_t xClearOnExit,
-                                     const BaseType_t xWaitForAllBits,
                                      TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupWaitBitsImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
-        " MPU_xEventGroupWaitBits_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xEventGroupWaitBitsImpl                     \n"
-        " MPU_xEventGroupWaitBits_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupWaitBitsImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupSyncImpl                       \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xEventGroupSync_Unpriv                        \n"
+            " MPU_xEventGroupSync_Priv:                             \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xEventGroupSyncImpl                         \n"
+            " MPU_xEventGroupSync_Unpriv:                           \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupSyncImpl                        \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                      const EventBits_t uxBitsToClear ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                      const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupClearBitsImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xEventGroupClearBits_Unpriv                   \n"
-        " MPU_xEventGroupClearBits_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xEventGroupClearBitsImpl                    \n"
-        " MPU_xEventGroupClearBits_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupClearBitsImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxEventGroupGetNumberImpl                 \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxEventGroupGetNumber_Unpriv                  \n"
+                " MPU_uxEventGroupGetNumber_Priv:                       \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxEventGroupGetNumberImpl                   \n"
+                " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxEventGroupGetNumberImpl                  \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
 /*-----------------------------------------------------------*/
 
-EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                    const EventBits_t uxBitsToSet ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                    const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupSetBitsImpl                    \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xEventGroupSetBits_Unpriv                     \n"
-        " MPU_xEventGroupSetBits_Priv:                          \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xEventGroupSetBitsImpl                      \n"
-        " MPU_xEventGroupSetBits_Unpriv:                        \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupSetBitsImpl                     \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vEventGroupSetNumber( void * xEventGroup,
+                                       UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vEventGroupSetNumber( void * xEventGroup,
+                                       UBaseType_t uxEventGroupNumber ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vEventGroupSetNumberImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vEventGroupSetNumber_Unpriv                   \n"
+                " MPU_vEventGroupSetNumber_Priv:                        \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vEventGroupSetNumberImpl                    \n"
+                " MPU_vEventGroupSetNumber_Unpriv:                      \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vEventGroupSetNumberImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
 /*-----------------------------------------------------------*/
 
-EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                 const EventBits_t uxBitsToSet,
-                                 const EventBits_t uxBitsToWaitFor,
-                                 TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                  const void * pvTxData,
+                                  size_t xDataLengthBytes,
+                                  TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                 const EventBits_t uxBitsToSet,
-                                 const EventBits_t uxBitsToWaitFor,
-                                 TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupSyncImpl                       \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xEventGroupSync_Unpriv                        \n"
-        " MPU_xEventGroupSync_Priv:                             \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xEventGroupSyncImpl                         \n"
-        " MPU_xEventGroupSync_Unpriv:                           \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupSyncImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                  const void * pvTxData,
+                                  size_t xDataLengthBytes,
+                                  TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferSendImpl                     \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferSend_Unpriv                      \n"
+            " MPU_xStreamBufferSend_Priv:                           \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferSendImpl                       \n"
+            " MPU_xStreamBufferSend_Unpriv:                         \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferSendImpl                      \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                     void * pvRxData,
+                                     size_t xBufferLengthBytes,
+                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxEventGroupGetNumberImpl                 \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxEventGroupGetNumber_Unpriv                  \n"
-        " MPU_uxEventGroupGetNumber_Priv:                       \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxEventGroupGetNumberImpl                   \n"
-        " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxEventGroupGetNumberImpl                  \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                     void * pvRxData,
+                                     size_t xBufferLengthBytes,
+                                     TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferReceiveImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferReceive_Unpriv                   \n"
+            " MPU_xStreamBufferReceive_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferReceiveImpl                    \n"
+            " MPU_xStreamBufferReceive_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferReceiveImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vEventGroupSetNumber( void * xEventGroup,
-                               UBaseType_t uxEventGroupNumber ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vEventGroupSetNumber( void * xEventGroup,
-                               UBaseType_t uxEventGroupNumber ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vEventGroupSetNumberImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vEventGroupSetNumber_Unpriv                   \n"
-        " MPU_vEventGroupSetNumber_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vEventGroupSetNumberImpl                    \n"
-        " MPU_vEventGroupSetNumber_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vEventGroupSetNumberImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferIsFullImpl                   \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
+            " MPU_xStreamBufferIsFull_Priv:                         \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferIsFullImpl                     \n"
+            " MPU_xStreamBufferIsFull_Unpriv:                       \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferIsFullImpl                    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                              const void * pvTxData,
-                              size_t xDataLengthBytes,
-                              TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                              const void * pvTxData,
-                              size_t xDataLengthBytes,
-                              TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferSendImpl                     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferSend_Unpriv                      \n"
-        " MPU_xStreamBufferSend_Priv:                           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferSendImpl                       \n"
-        " MPU_xStreamBufferSend_Unpriv:                         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferSendImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
+            " MPU_xStreamBufferIsEmpty_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferIsEmptyImpl                    \n"
+            " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferIsEmptyImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                 void * pvRxData,
-                                 size_t xBufferLengthBytes,
-                                 TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                 void * pvRxData,
-                                 size_t xBufferLengthBytes,
-                                 TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferReceiveImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferReceive_Unpriv                   \n"
-        " MPU_xStreamBufferReceive_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferReceiveImpl                    \n"
-        " MPU_xStreamBufferReceive_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferReceiveImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
+            " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
+            " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferSpacesAvailableImpl           \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferIsFullImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
-        " MPU_xStreamBufferIsFull_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferIsFullImpl                     \n"
-        " MPU_xStreamBufferIsFull_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferIsFullImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
+            " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferBytesAvailableImpl             \n"
+            " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferBytesAvailableImpl            \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                 size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
-        " MPU_xStreamBufferIsEmpty_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferIsEmptyImpl                    \n"
-        " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferIsEmptyImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                 size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
+            " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
+            " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferSetTriggerLevelImpl           \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
-        " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
-        " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferSpacesAvailableImpl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
-size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
-        " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferBytesAvailableImpl             \n"
-        " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferBytesAvailableImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                             size_t xTriggerLevel ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                             size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
-        " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
-        " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferSetTriggerLevelImpl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
-size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
-        " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
-        " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferNextMessageLengthBytesImpl    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
+            " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
+            " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferNextMessageLengthBytesImpl    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
 #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
diff --git a/portable/GCC/ARM_CM4_MPU/port.c b/portable/GCC/ARM_CM4_MPU/port.c
index 548187db3..886be7018 100644
--- a/portable/GCC/ARM_CM4_MPU/port.c
+++ b/portable/GCC/ARM_CM4_MPU/port.c
@@ -130,7 +130,7 @@
 
 /* For strict compliance with the Cortex-M spec the task start address should
  * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
-#define portSTART_ADDRESS_MASK                    ( ( StackType_t ) 0xfffffffeUL )
+#define portSTART_ADDRESS_MASK    ( ( StackType_t ) 0xfffffffeUL )
 
 /* Does addr lie within [start, end] address range? */
 #define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \
@@ -209,7 +209,7 @@ void vResetPrivilege( void ) __attribute__( ( naked ) );
 /**
  * @brief Enter critical section.
  */
-#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
+#if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
     void vPortEnterCritical( void ) FREERTOS_SYSTEM_CALL;
 #else
     void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
@@ -218,7 +218,7 @@ void vResetPrivilege( void ) __attribute__( ( naked ) );
 /**
  * @brief Exit from critical section.
  */
-#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
+#if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
     void vPortExitCritical( void ) FREERTOS_SYSTEM_CALL;
 #else
     void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
@@ -226,44 +226,47 @@ void vResetPrivilege( void ) __attribute__( ( naked ) );
 
 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
 
-    /**
-     * @brief Sets up the system call stack so that upon returning from
-     * SVC, the system call stack is used.
-     *
-     * It is used for the system calls with up to 4 parameters.
-     *
-     * @param pulTaskStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the system call stack so that upon returning from
+ * SVC, the system call stack is used.
+ *
+ * It is used for the system calls with up to 4 parameters.
+ *
+ * @param pulTaskStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallEnter( uint32_t * pulTaskStack,
+                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
 
-    /**
-     * @brief Sets up the system call stack so that upon returning from
-     * SVC, the system call stack is used.
-     *
-     * It is used for the system calls with 5 parameters.
-     *
-     * @param pulTaskStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the system call stack so that upon returning from
+ * SVC, the system call stack is used.
+ *
+ * It is used for the system calls with 5 parameters.
+ *
+ * @param pulTaskStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallEnter_1( uint32_t * pulTaskStack,
+                             uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
 
-    /**
-     * @brief Sets up the task stack so that upon returning from
-     * SVC, the task stack is used again.
-     *
-     * @param pulSystemCallStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the task stack so that upon returning from
+ * SVC, the task stack is used again.
+ *
+ * @param pulSystemCallStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallExit( uint32_t * pulSystemCallStack,
+                          uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
@@ -312,25 +315,26 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
         xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
         xMPUSettings->ulContext[ 0 ] = portINITIAL_CONTROL_IF_UNPRIVILEGED;
     }
-    xMPUSettings->ulContext[ 1 ] = 0x04040404; /* r4. */
-    xMPUSettings->ulContext[ 2 ] = 0x05050505; /* r5. */
-    xMPUSettings->ulContext[ 3 ] = 0x06060606; /* r6. */
-    xMPUSettings->ulContext[ 4 ] = 0x07070707; /* r7. */
-    xMPUSettings->ulContext[ 5 ] = 0x08080808; /* r8. */
-    xMPUSettings->ulContext[ 6 ] = 0x09090909; /* r9. */
-    xMPUSettings->ulContext[ 7 ] = 0x10101010; /* r10. */
-    xMPUSettings->ulContext[ 8 ] = 0x11111111; /* r11. */
-    xMPUSettings->ulContext[ 9 ] = portINITIAL_EXC_RETURN; /* EXC_RETURN. */
 
-    xMPUSettings->ulContext[ 10 ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
-    xMPUSettings->ulContext[ 11 ] = ( uint32_t ) pvParameters; /* r0. */
-    xMPUSettings->ulContext[ 12 ] = 0x01010101; /* r1. */
-    xMPUSettings->ulContext[ 13 ] = 0x02020202; /* r2. */
-    xMPUSettings->ulContext[ 14 ] = 0x03030303; /* r3. */
-    xMPUSettings->ulContext[ 15 ] = 0x12121212; /* r12. */
-    xMPUSettings->ulContext[ 16 ] = 0; /* LR. */
+    xMPUSettings->ulContext[ 1 ] = 0x04040404;                                        /* r4. */
+    xMPUSettings->ulContext[ 2 ] = 0x05050505;                                        /* r5. */
+    xMPUSettings->ulContext[ 3 ] = 0x06060606;                                        /* r6. */
+    xMPUSettings->ulContext[ 4 ] = 0x07070707;                                        /* r7. */
+    xMPUSettings->ulContext[ 5 ] = 0x08080808;                                        /* r8. */
+    xMPUSettings->ulContext[ 6 ] = 0x09090909;                                        /* r9. */
+    xMPUSettings->ulContext[ 7 ] = 0x10101010;                                        /* r10. */
+    xMPUSettings->ulContext[ 8 ] = 0x11111111;                                        /* r11. */
+    xMPUSettings->ulContext[ 9 ] = portINITIAL_EXC_RETURN;                            /* EXC_RETURN. */
+
+    xMPUSettings->ulContext[ 10 ] = ( uint32_t ) ( pxTopOfStack - 8 );                /* PSP with the hardware saved stack. */
+    xMPUSettings->ulContext[ 11 ] = ( uint32_t ) pvParameters;                        /* r0. */
+    xMPUSettings->ulContext[ 12 ] = 0x01010101;                                       /* r1. */
+    xMPUSettings->ulContext[ 13 ] = 0x02020202;                                       /* r2. */
+    xMPUSettings->ulContext[ 14 ] = 0x03030303;                                       /* r3. */
+    xMPUSettings->ulContext[ 15 ] = 0x12121212;                                       /* r12. */
+    xMPUSettings->ulContext[ 16 ] = 0;                                                /* LR. */
     xMPUSettings->ulContext[ 17 ] = ( ( uint32_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC. */
-    xMPUSettings->ulContext[ 18 ] = portINITIAL_XPSR; /* xPSR. */
+    xMPUSettings->ulContext[ 18 ] = portINITIAL_XPSR;                                 /* xPSR. */
 
     #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
     {
@@ -350,68 +354,68 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
 
 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
 
-void vPortSVCHandler( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        ".syntax unified                \n"
-        ".extern vSVCHandler_C          \n"
-        ".extern vSystemCallEnter       \n"
-        ".extern vSystemCallEnter_1     \n"
-        ".extern vSystemCallExit        \n"
-        "                               \n"
-        "tst lr, #4                     \n"
-        "ite eq                         \n"
-        "mrseq r0, msp                  \n"
-        "mrsne r0, psp                  \n"
-        "                               \n"
-        "ldr r1, [r0, #24]              \n"
-        "ldrb r2, [r1, #-2]             \n"
-        "cmp r2, %0                     \n"
-        "beq syscall_enter              \n"
-        "cmp r2, %1                     \n"
-        "beq syscall_enter_1            \n"
-        "cmp r2, %2                     \n"
-        "beq syscall_exit               \n"
-        "b vSVCHandler_C                \n"
-        "                               \n"
-        "syscall_enter:                 \n"
-        "    mov r1, lr                 \n"
-        "    b vSystemCallEnter         \n"
-        "                               \n"
-        "syscall_enter_1:               \n"
-        "    mov r1, lr                 \n"
-        "    b vSystemCallEnter_1       \n"
-        "                               \n"
-        "syscall_exit:                  \n"
-        "    mov r1, lr                 \n"
-        "    b vSystemCallExit          \n"
-        "                               \n"
-        : /* No outputs. */
-        :"i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT )
-        : "r0", "r1", "r2", "memory"
-    );
-}
+    void vPortSVCHandler( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            ".syntax unified                \n"
+            ".extern vSVCHandler_C          \n"
+            ".extern vSystemCallEnter       \n"
+            ".extern vSystemCallEnter_1     \n"
+            ".extern vSystemCallExit        \n"
+            "                               \n"
+            "tst lr, #4                     \n"
+            "ite eq                         \n"
+            "mrseq r0, msp                  \n"
+            "mrsne r0, psp                  \n"
+            "                               \n"
+            "ldr r1, [r0, #24]              \n"
+            "ldrb r2, [r1, #-2]             \n"
+            "cmp r2, %0                     \n"
+            "beq syscall_enter              \n"
+            "cmp r2, %1                     \n"
+            "beq syscall_enter_1            \n"
+            "cmp r2, %2                     \n"
+            "beq syscall_exit               \n"
+            "b vSVCHandler_C                \n"
+            "                               \n"
+            "syscall_enter:                 \n"
+            "    mov r1, lr                 \n"
+            "    b vSystemCallEnter         \n"
+            "                               \n"
+            "syscall_enter_1:               \n"
+            "    mov r1, lr                 \n"
+            "    b vSystemCallEnter_1       \n"
+            "                               \n"
+            "syscall_exit:                  \n"
+            "    mov r1, lr                 \n"
+            "    b vSystemCallExit          \n"
+            "                               \n"
+            : /* No outputs. */
+            : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT )
+            : "r0", "r1", "r2", "memory"
+        );
+    }
 
 #else /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
-void vPortSVCHandler( void )
-{
-    /* Assumes psp was in use. */
-    __asm volatile
-    (
-        #ifndef USE_PROCESS_STACK   /* Code should not be required if a main() is using the process stack. */
-            "   tst lr, #4                      \n"
-            "   ite eq                          \n"
-            "   mrseq r0, msp                   \n"
-            "   mrsne r0, psp                   \n"
-        #else
-            "   mrs r0, psp                     \n"
-        #endif
-        "   b %0                            \n"
-        ::"i" ( vSVCHandler_C ) : "r0", "memory"
-    );
-}
+    void vPortSVCHandler( void )
+    {
+        /* Assumes psp was in use. */
+        __asm volatile
+        (
+            #ifndef USE_PROCESS_STACK /* Code should not be required if a main() is using the process stack. */
+                "   tst lr, #4                      \n"
+                "   ite eq                          \n"
+                "   mrseq r0, msp                   \n"
+                "   mrsne r0, psp                   \n"
+            #else
+                "   mrs r0, psp                     \n"
+            #endif
+            "   b %0                            \n"
+            ::"i" ( vSVCHandler_C ) : "r0", "memory"
+        );
+    }
 
 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
@@ -425,7 +429,7 @@ void vSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
         #if defined( __ARMCC_VERSION )
 
             /* Declaration when these variable are defined in code instead of being
-            * exported from linker scripts. */
+             * exported from linker scripts. */
             extern uint32_t * __syscalls_flash_start__;
             extern uint32_t * __syscalls_flash_end__;
         #else
@@ -469,9 +473,9 @@ void vSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
                     {
                         __asm volatile
                         (
-                            "   mrs r1, control     \n"/* Obtain current control value. */
-                            "   bic r1, #1          \n"/* Set privilege bit. */
-                            "   msr control, r1     \n"/* Write back new control value. */
+                            "   mrs r1, control     \n" /* Obtain current control value. */
+                            "   bic r1, #1          \n" /* Set privilege bit. */
+                            "   msr control, r1     \n" /* Write back new control value. */
                             ::: "r1", "memory"
                         );
                     }
@@ -481,13 +485,13 @@ void vSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
                 case portSVC_RAISE_PRIVILEGE:
                     __asm volatile
                     (
-                        "   mrs r1, control     \n"/* Obtain current control value. */
-                        "   bic r1, #1          \n"/* Set privilege bit. */
-                        "   msr control, r1     \n"/* Write back new control value. */
+                        "   mrs r1, control     \n" /* Obtain current control value. */
+                        "   bic r1, #1          \n" /* Set privilege bit. */
+                        "   msr control, r1     \n" /* Write back new control value. */
                         ::: "r1", "memory"
                     );
                     break;
-            #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
+                    #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
 
                 default: /* Unknown SVC call. */
                     break;
@@ -497,288 +501,299 @@ void vSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
 
 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
 
-void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulSystemCallStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallEnter( uint32_t * pulTaskStack,
+                           uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulSystemCallStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        /* This is not NULL only for the duration of the system call. */
-        configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+        #if defined( __ARMCC_VERSION )
 
-        if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            /* Extended frame i.e. FPU in use. */
-            ulStackFrameSize = 26;
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+
+            /* This is not NULL only for the duration of the system call. */
+            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+
+            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            {
+                /* Extended frame i.e. FPU in use. */
+                ulStackFrameSize = 26;
+                __asm volatile (
+                    " vpush {s0}         \n" /* Trigger lazy stacking. */
+                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                    ::: "memory"
+                    );
+            }
+            else
+            {
+                /* Standard frame i.e. FPU not in use. */
+                ulStackFrameSize = 8;
+            }
+
+            /* Make space on the system call stack for the stack frame. */
+            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulSystemCallStack[ i ] = pulTaskStack[ i ];
+            }
+
+            /* Use the pulSystemCallStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
+
+            /* Raise the privilege for the duration of the system call. */
             __asm volatile (
-                                " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                ::: "memory"
-                           );
+                " mrs r1, control     \n" /* Obtain current control value. */
+                " bic r1, #1          \n" /* Clear nPRIV bit. */
+                " msr control, r1     \n" /* Write back new control value. */
+                ::: "r1", "memory"
+                );
+
+            /* Remember the location where we should copy the stack frame when we exit from
+             * the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+
+            /* Store the value of the Link Register before the SVC was raised. We need to
+             * restore it when we exit from the system call. */
+            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+
+            /* Record if the hardware used padding to force the stack pointer
+             * to be double word aligned. */
+            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
+            {
+                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
+            }
+            else
+            {
+                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
+            }
+
+            /* We ensure in pxPortInitialiseStack that the system call stack is
+             * double word aligned and therefore, there is no need of padding.
+             * Clear the bit[9] of stacked xPSR. */
+            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
         }
-        else
-        {
-            /* Standard frame i.e. FPU not in use. */
-            ulStackFrameSize = 8;
-        }
-
-        /* Make space on the system call stack for the stack frame. */
-        pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulSystemCallStack[ i ] = pulTaskStack[ i ];
-        }
-
-        /* Use the pulSystemCallStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-
-        /* Raise the privilege for the duration of the system call. */
-        __asm volatile (
-                            " mrs r1, control     \n" /* Obtain current control value. */
-                            " bic r1, #1          \n" /* Clear nPRIV bit. */
-                            " msr control, r1     \n" /* Write back new control value. */
-                            ::: "r1", "memory"
-                        );
-
-        /* Remember the location where we should copy the stack frame when we exit from
-         * the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-        /* Store the value of the Link Register before the SVC was raised. We need to
-         * restore it when we exit from the system call. */
-        pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-
-        /* Record if the hardware used padding to force the stack pointer
-         * to be double word aligned. */
-        if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-        {
-            pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-        }
-        else
-        {
-            pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-        }
-
-        /* We ensure in pxPortInitialiseStack that the system call stack is
-         * double word aligned and therefore, there is no need of padding.
-         * Clear the bit[9] of stacked xPSR. */
-        pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
     }
-}
 
 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
 
-void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulSystemCallStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallEnter_1( uint32_t * pulTaskStack,
+                             uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulSystemCallStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        /* This is not NULL only for the duration of the system call. */
-        configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+        #if defined( __ARMCC_VERSION )
 
-        if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            /* Extended frame i.e. FPU in use. */
-            ulStackFrameSize = 26;
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+
+            /* This is not NULL only for the duration of the system call. */
+            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+
+            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            {
+                /* Extended frame i.e. FPU in use. */
+                ulStackFrameSize = 26;
+                __asm volatile (
+                    " vpush {s0}         \n" /* Trigger lazy stacking. */
+                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                    ::: "memory"
+                    );
+            }
+            else
+            {
+                /* Standard frame i.e. FPU not in use. */
+                ulStackFrameSize = 8;
+            }
+
+            /* Make space on the system call stack for the stack frame and
+             * the parameter passed on the stack. We only need to copy one
+             * parameter but we still reserve 2 spaces to keep the stack
+             * double word aligned. */
+            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulSystemCallStack[ i ] = pulTaskStack[ i ];
+            }
+
+            /* Copy the parameter which is passed the stack. */
+            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
+            {
+                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
+
+                /* Record if the hardware used padding to force the stack pointer
+                 * to be double word aligned. */
+                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
+            }
+            else
+            {
+                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
+
+                /* Record if the hardware used padding to force the stack pointer
+                 * to be double word aligned. */
+                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
+            }
+
+            /* Use the pulSystemCallStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
+
+            /* Raise the privilege for the duration of the system call. */
             __asm volatile (
-                                " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                ::: "memory"
-                           );
+                " mrs r1, control     \n" /* Obtain current control value. */
+                " bic r1, #1          \n" /* Clear nPRIV bit. */
+                " msr control, r1     \n" /* Write back new control value. */
+                ::: "r1", "memory"
+                );
+
+            /* Remember the location where we should copy the stack frame when we exit from
+             * the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+
+            /* Store the value of the Link Register before the SVC was raised. We need to
+             * restore it when we exit from the system call. */
+            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+
+            /* We ensure in pxPortInitialiseStack that the system call stack is
+             * double word aligned and therefore, there is no need of padding.
+             * Clear the bit[9] of stacked xPSR. */
+            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
         }
-        else
-        {
-            /* Standard frame i.e. FPU not in use. */
-            ulStackFrameSize = 8;
-        }
-
-        /* Make space on the system call stack for the stack frame and
-         * the parameter passed on the stack. We only need to copy one
-         * parameter but we still reserve 2 spaces to keep the stack
-         * double word aligned. */
-        pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulSystemCallStack[ i ] = pulTaskStack[ i ];
-        }
-
-        /* Copy the parameter which is passed the stack. */
-        if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-        {
-            pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
-            /* Record if the hardware used padding to force the stack pointer
-             * to be double word aligned. */
-            pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-        }
-        else
-        {
-            pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
-            /* Record if the hardware used padding to force the stack pointer
-             * to be double word aligned. */
-            pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-        }
-
-        /* Use the pulSystemCallStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-
-        /* Raise the privilege for the duration of the system call. */
-        __asm volatile (
-                            " mrs r1, control     \n" /* Obtain current control value. */
-                            " bic r1, #1          \n" /* Clear nPRIV bit. */
-                            " msr control, r1     \n" /* Write back new control value. */
-                            ::: "r1", "memory"
-                        );
-
-        /* Remember the location where we should copy the stack frame when we exit from
-         * the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-        /* Store the value of the Link Register before the SVC was raised. We need to
-         * restore it when we exit from the system call. */
-        pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-
-        /* We ensure in pxPortInitialiseStack that the system call stack is
-         * double word aligned and therefore, there is no need of padding.
-         * Clear the bit[9] of stacked xPSR. */
-        pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
     }
-}
 
 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
 
-void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulTaskStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallExit( uint32_t * pulSystemCallStack,
+                          uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulTaskStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+        #if defined( __ARMCC_VERSION )
+
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            /* Extended frame i.e. FPU in use. */
-            ulStackFrameSize = 26;
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
+
+            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            {
+                /* Extended frame i.e. FPU in use. */
+                ulStackFrameSize = 26;
+                __asm volatile (
+                    " vpush {s0}         \n" /* Trigger lazy stacking. */
+                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                    ::: "memory"
+                    );
+            }
+            else
+            {
+                /* Standard frame i.e. FPU not in use. */
+                ulStackFrameSize = 8;
+            }
+
+            /* Make space on the task stack for the stack frame. */
+            pulTaskStack = pulTaskStack - ulStackFrameSize;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulTaskStack[ i ] = pulSystemCallStack[ i ];
+            }
+
+            /* Use the pulTaskStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
+
+            /* Drop the privilege before returning to the thread mode. */
             __asm volatile (
-                                " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                ::: "memory"
-                        );
+                " mrs r1, control     \n" /* Obtain current control value. */
+                " orr r1, #1          \n" /* Set nPRIV bit. */
+                " msr control, r1     \n" /* Write back new control value. */
+                ::: "r1", "memory"
+                );
+
+            /* Restore the stacked link register to what it was at the time of
+             * system call entry. */
+            pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+
+            /* If the hardware used padding to force the stack pointer
+             * to be double word aligned, set the stacked xPSR bit[9],
+             * otherwise clear it. */
+            if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG )
+            {
+                pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK;
+            }
+            else
+            {
+                pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
+            }
+
+            /* This is not NULL only for the duration of the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
         }
-        else
-        {
-            /* Standard frame i.e. FPU not in use. */
-            ulStackFrameSize = 8;
-        }
-
-        /* Make space on the task stack for the stack frame. */
-        pulTaskStack = pulTaskStack - ulStackFrameSize;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulTaskStack[ i ] = pulSystemCallStack[ i ];
-        }
-
-        /* Use the pulTaskStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
-
-        /* Drop the privilege before returning to the thread mode. */
-        __asm volatile (
-                            " mrs r1, control     \n" /* Obtain current control value. */
-                            " orr r1, #1          \n" /* Set nPRIV bit. */
-                            " msr control, r1     \n" /* Write back new control value. */
-                            ::: "r1", "memory"
-                        );
-
-        /* Restore the stacked link register to what it was at the time of
-         * system call entry. */
-        pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
-
-        /* If the hardware used padding to force the stack pointer
-         * to be double word aligned, set the stacked xPSR bit[9],
-         * otherwise clear it. */
-        if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG )
-        {
-            pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK;
-        }
-        else
-        {
-            pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-        }
-
-        /* This is not NULL only for the duration of the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
     }
-}
 
 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
@@ -821,12 +836,12 @@ static void prvRestoreContextOfFirstTask( void )
         " ldmia r2!, {r4-r11}                   \n" /* Read 4 sets of MPU registers [MPU Region # 0 - 3]. */
         " stmia r0, {r4-r11}                    \n" /* Write 4 sets of MPU registers [MPU Region # 0 - 3]. */
         "                                       \n"
-    #if ( configTOTAL_MPU_REGIONS == 16 )
-        " ldmia r2!, {r4-r11}                   \n" /* Read 4 sets of MPU registers [MPU Region # 4 - 8]. */
-        " stmia r0, {r4-r11}                    \n" /* Write 4 sets of MPU registers. [MPU Region # 4 - 8]. */
-        " ldmia r2!, {r4-r11}                   \n" /* Read 4 sets of MPU registers [MPU Region # 9 - 12]. */
-        " stmia r0, {r4-r11}                    \n" /* Write 4 sets of MPU registers. [MPU Region # 9 - 12]. */
-    #endif /* configTOTAL_MPU_REGIONS == 16. */
+        #if ( configTOTAL_MPU_REGIONS == 16 )
+            " ldmia r2!, {r4-r11}                   \n" /* Read 4 sets of MPU registers [MPU Region # 4 - 8]. */
+            " stmia r0, {r4-r11}                    \n" /* Write 4 sets of MPU registers. [MPU Region # 4 - 8]. */
+            " ldmia r2!, {r4-r11}                   \n" /* Read 4 sets of MPU registers [MPU Region # 9 - 12]. */
+            " stmia r0, {r4-r11}                    \n" /* Write 4 sets of MPU registers. [MPU Region # 9 - 12]. */
+        #endif /* configTOTAL_MPU_REGIONS == 16. */
         "                                       \n"
         " ldr r0, =0xe000ed94                   \n" /* MPU_CTRL register. */
         " ldr r3, [r0]                          \n" /* Read the value of MPU_CTRL. */
@@ -867,6 +882,7 @@ BaseType_t xPortStartScheduler( void )
     #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
         configASSERT( ( portCPUID == portCORTEX_M7_r0p1_ID ) || ( portCPUID == portCORTEX_M7_r0p0_ID ) );
     #else
+
         /* When using this port on a Cortex-M7 r0p0 or r0p1 core, define
          * configENABLE_ERRATA_837070_WORKAROUND to 1 in your
          * FreeRTOSConfig.h. */
@@ -875,87 +891,87 @@ BaseType_t xPortStartScheduler( void )
     #endif
 
     #if ( configASSERT_DEFINED == 1 )
+    {
+        volatile uint8_t ucOriginalPriority;
+        volatile uint32_t ulImplementedPrioBits = 0;
+        volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
+        volatile uint8_t ucMaxPriorityValue;
+
+        /* Determine the maximum priority from which ISR safe FreeRTOS API
+         * functions can be called.  ISR safe functions are those that end in
+         * "FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+         * ensure interrupt entry is as fast and simple as possible.
+         *
+         * Save the interrupt priority value that is about to be clobbered. */
+        ucOriginalPriority = *pucFirstUserPriorityRegister;
+
+        /* Determine the number of priority bits available.  First write to all
+         * possible bits. */
+        *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+        /* Read the value back to see how many bits stuck. */
+        ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+        /* Use the same mask on the maximum system call priority. */
+        ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+        /* Check that the maximum system call priority is nonzero after
+         * accounting for the number of priority bits supported by the
+         * hardware. A priority of 0 is invalid because setting the BASEPRI
+         * register to 0 unmasks all interrupts, and interrupts with priority 0
+         * cannot be masked using BASEPRI.
+         * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+        configASSERT( ucMaxSysCallPriority );
+
+        /* Check that the bits not implemented in hardware are zero in
+         * configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
+
+        /* Calculate the maximum acceptable priority group value for the number
+         * of bits read back. */
+
+        while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
         {
-            volatile uint8_t ucOriginalPriority;
-            volatile uint32_t ulImplementedPrioBits = 0;
-            volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
-            volatile uint8_t ucMaxPriorityValue;
-
-            /* Determine the maximum priority from which ISR safe FreeRTOS API
-             * functions can be called.  ISR safe functions are those that end in
-             * "FromISR".  FreeRTOS maintains separate thread and ISR API functions to
-             * ensure interrupt entry is as fast and simple as possible.
-             *
-             * Save the interrupt priority value that is about to be clobbered. */
-            ucOriginalPriority = *pucFirstUserPriorityRegister;
-
-            /* Determine the number of priority bits available.  First write to all
-             * possible bits. */
-            *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
-
-            /* Read the value back to see how many bits stuck. */
-            ucMaxPriorityValue = *pucFirstUserPriorityRegister;
-
-            /* Use the same mask on the maximum system call priority. */
-            ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
-
-            /* Check that the maximum system call priority is nonzero after
-             * accounting for the number of priority bits supported by the
-             * hardware. A priority of 0 is invalid because setting the BASEPRI
-             * register to 0 unmasks all interrupts, and interrupts with priority 0
-             * cannot be masked using BASEPRI.
-             * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
-            configASSERT( ucMaxSysCallPriority );
-
-            /* Check that the bits not implemented in hardware are zero in
-             * configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-            configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
-
-            /* Calculate the maximum acceptable priority group value for the number
-             * of bits read back. */
-
-            while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
-            {
-                ulImplementedPrioBits++;
-                ucMaxPriorityValue <<= ( uint8_t ) 0x01;
-            }
-
-            if( ulImplementedPrioBits == 8 )
-            {
-                /* When the hardware implements 8 priority bits, there is no way for
-                * the software to configure PRIGROUP to not have sub-priorities. As
-                * a result, the least significant bit is always used for sub-priority
-                * and there are 128 preemption priorities and 2 sub-priorities.
-                *
-                * This may cause some confusion in some cases - for example, if
-                * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
-                * priority interrupts will be masked in Critical Sections as those
-                * are at the same preemption priority. This may appear confusing as
-                * 4 is higher (numerically lower) priority than
-                * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
-                * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
-                * to 4, this confusion does not happen and the behaviour remains the same.
-                *
-                * The following assert ensures that the sub-priority bit in the
-                * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
-                * confusion. */
-                configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
-                ulMaxPRIGROUPValue = 0;
-            }
-            else
-            {
-                ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
-            }
-
-            /* Shift the priority group value back to its position within the AIRCR
-             * register. */
-            ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
-            ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
-            /* Restore the clobbered interrupt priority register to its original
-             * value. */
-            *pucFirstUserPriorityRegister = ucOriginalPriority;
+            ulImplementedPrioBits++;
+            ucMaxPriorityValue <<= ( uint8_t ) 0x01;
         }
+
+        if( ulImplementedPrioBits == 8 )
+        {
+            /* When the hardware implements 8 priority bits, there is no way for
+             * the software to configure PRIGROUP to not have sub-priorities. As
+             * a result, the least significant bit is always used for sub-priority
+             * and there are 128 preemption priorities and 2 sub-priorities.
+             *
+             * This may cause some confusion in some cases - for example, if
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
+             * priority interrupts will be masked in Critical Sections as those
+             * are at the same preemption priority. This may appear confusing as
+             * 4 is higher (numerically lower) priority than
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
+             * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
+             * to 4, this confusion does not happen and the behaviour remains the same.
+             *
+             * The following assert ensures that the sub-priority bit in the
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
+             * confusion. */
+            configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
+            ulMaxPRIGROUPValue = 0;
+        }
+        else
+        {
+            ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
+        }
+
+        /* Shift the priority group value back to its position within the AIRCR
+         * register. */
+        ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+        ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+        /* Restore the clobbered interrupt priority register to its original
+         * value. */
+        *pucFirstUserPriorityRegister = ucOriginalPriority;
+    }
     #endif /* configASSERT_DEFINED */
 
     /* Make PendSV and SysTick the same priority as the kernel, and the SVC
@@ -985,17 +1001,17 @@ BaseType_t xPortStartScheduler( void )
      * would otherwise result in the unnecessary leaving of space in the SVC stack
      * for lazy saving of FPU registers. */
     __asm volatile (
-        " ldr r0, =0xE000ED08   \n"/* Use the NVIC offset register to locate the stack. */
+        " ldr r0, =0xE000ED08   \n" /* Use the NVIC offset register to locate the stack. */
         " ldr r0, [r0]          \n"
         " ldr r0, [r0]          \n"
-        " msr msp, r0           \n"/* Set the msp back to the start of the stack. */
-        " mov r0, #0            \n"/* Clear the bit that indicates the FPU is in use, see comment above. */
+        " msr msp, r0           \n" /* Set the msp back to the start of the stack. */
+        " mov r0, #0            \n" /* Clear the bit that indicates the FPU is in use, see comment above. */
         " msr control, r0       \n"
-        " cpsie i               \n"/* Globally enable interrupts. */
+        " cpsie i               \n" /* Globally enable interrupts. */
         " cpsie f               \n"
         " dsb                   \n"
         " isb                   \n"
-        " svc %0                \n"/* System call to start first task. */
+        " svc %0                \n" /* System call to start first task. */
         " nop                   \n"
         " .ltorg                \n"
         ::"i" ( portSVC_START_SCHEDULER ) : "memory" );
@@ -1015,39 +1031,63 @@ void vPortEndScheduler( void )
 
 void vPortEnterCritical( void )
 {
-#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
-    if( portIS_PRIVILEGED() == pdFALSE )
-    {
-        portRAISE_PRIVILEGE();
-        portMEMORY_BARRIER();
+    #if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
+        if( portIS_PRIVILEGED() == pdFALSE )
+        {
+            portRAISE_PRIVILEGE();
+            portMEMORY_BARRIER();
 
+            portDISABLE_INTERRUPTS();
+            uxCriticalNesting++;
+            portMEMORY_BARRIER();
+
+            portRESET_PRIVILEGE();
+            portMEMORY_BARRIER();
+        }
+        else
+        {
+            portDISABLE_INTERRUPTS();
+            uxCriticalNesting++;
+        }
+    #else /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */
         portDISABLE_INTERRUPTS();
         uxCriticalNesting++;
-        portMEMORY_BARRIER();
-
-        portRESET_PRIVILEGE();
-        portMEMORY_BARRIER();
-    }
-    else
-    {
-        portDISABLE_INTERRUPTS();
-        uxCriticalNesting++;
-    }
-#else
-    portDISABLE_INTERRUPTS();
-    uxCriticalNesting++;
-#endif
+    #endif /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */
 }
 /*-----------------------------------------------------------*/
 
 void vPortExitCritical( void )
 {
-#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
-    if( portIS_PRIVILEGED() == pdFALSE )
-    {
-        portRAISE_PRIVILEGE();
-        portMEMORY_BARRIER();
+    #if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
+        if( portIS_PRIVILEGED() == pdFALSE )
+        {
+            portRAISE_PRIVILEGE();
+            portMEMORY_BARRIER();
 
+            configASSERT( uxCriticalNesting );
+            uxCriticalNesting--;
+
+            if( uxCriticalNesting == 0 )
+            {
+                portENABLE_INTERRUPTS();
+            }
+
+            portMEMORY_BARRIER();
+
+            portRESET_PRIVILEGE();
+            portMEMORY_BARRIER();
+        }
+        else
+        {
+            configASSERT( uxCriticalNesting );
+            uxCriticalNesting--;
+
+            if( uxCriticalNesting == 0 )
+            {
+                portENABLE_INTERRUPTS();
+            }
+        }
+    #else /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */
         configASSERT( uxCriticalNesting );
         uxCriticalNesting--;
 
@@ -1055,30 +1095,7 @@ void vPortExitCritical( void )
         {
             portENABLE_INTERRUPTS();
         }
-        portMEMORY_BARRIER();
-
-        portRESET_PRIVILEGE();
-        portMEMORY_BARRIER();
-    }
-    else
-    {
-        configASSERT( uxCriticalNesting );
-        uxCriticalNesting--;
-
-        if( uxCriticalNesting == 0 )
-        {
-            portENABLE_INTERRUPTS();
-        }
-    }
-#else
-    configASSERT( uxCriticalNesting );
-    uxCriticalNesting--;
-
-    if( uxCriticalNesting == 0 )
-    {
-        portENABLE_INTERRUPTS();
-    }
-#endif
+    #endif /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */
 }
 /*-----------------------------------------------------------*/
 
@@ -1112,15 +1129,15 @@ void xPortPendSVHandler( void )
         "                                       \n"
         /*---------- Select next task. --------- */
         " mov r0, %0                            \n"
-    #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
-        " cpsid i                               \n" /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
-    #endif
+        #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
+            " cpsid i                               \n" /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
+        #endif
         " msr basepri, r0                       \n"
         " dsb                                   \n"
         " isb                                   \n"
-    #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
-        " cpsie i                               \n" /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
-    #endif
+        #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
+            " cpsie i                               \n" /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
+        #endif
         " bl vTaskSwitchContext                 \n"
         " mov r0, #0                            \n"
         " msr basepri, r0                       \n"
@@ -1140,12 +1157,12 @@ void xPortPendSVHandler( void )
         " ldmia r2!, {r4-r11}                   \n" /* Read 4 sets of MPU registers [MPU Region # 0 - 3]. */
         " stmia r0, {r4-r11}                    \n" /* Write 4 sets of MPU registers [MPU Region # 0 - 3]. */
         "                                       \n"
-    #if ( configTOTAL_MPU_REGIONS == 16 )
-        " ldmia r2!, {r4-r11}                   \n" /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
-        " stmia r0, {r4-r11}                    \n" /* Write 4 sets of MPU registers. [MPU Region # 4 - 7]. */
-        " ldmia r2!, {r4-r11}                   \n" /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
-        " stmia r0, {r4-r11}                    \n" /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
-    #endif /* configTOTAL_MPU_REGIONS == 16. */
+        #if ( configTOTAL_MPU_REGIONS == 16 )
+            " ldmia r2!, {r4-r11}                   \n" /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
+            " stmia r0, {r4-r11}                    \n" /* Write 4 sets of MPU registers. [MPU Region # 4 - 7]. */
+            " ldmia r2!, {r4-r11}                   \n" /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
+            " stmia r0, {r4-r11}                    \n" /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
+        #endif /* configTOTAL_MPU_REGIONS == 16. */
         "                                       \n"
         " ldr r0, =0xe000ed94                   \n" /* MPU_CTRL register. */
         " ldr r3, [r0]                          \n" /* Read the value of MPU_CTRL. */
@@ -1219,10 +1236,10 @@ static void vPortEnableVFP( void )
 {
     __asm volatile
     (
-        "   ldr.w r0, =0xE000ED88       \n"/* The FPU enable bits are in the CPACR. */
+        "   ldr.w r0, =0xE000ED88       \n" /* The FPU enable bits are in the CPACR. */
         "   ldr r1, [r0]                \n"
         "                               \n"
-        "   orr r1, r1, #( 0xf << 20 )  \n"/* Enable CP10 and CP11 coprocessors, then save back. */
+        "   orr r1, r1, #( 0xf << 20 )  \n" /* Enable CP10 and CP11 coprocessors, then save back. */
         "   str r1, [r0]                \n"
         "   bx r14                      \n"
         "   .ltorg                      \n"
@@ -1341,12 +1358,12 @@ BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
 {
     __asm volatile
     (
-        "   mrs r0, control                         \n"/* r0 = CONTROL. */
-        "   tst r0, #1                              \n"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+        "   mrs r0, control                         \n" /* r0 = CONTROL. */
+        "   tst r0, #1                              \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
         "   ite ne                                  \n"
-        "   movne r0, #0                            \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
-        "   moveq r0, #1                            \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
-        "   bx lr                                   \n"/* Return. */
+        "   movne r0, #0                            \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+        "   moveq r0, #1                            \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+        "   bx lr                                   \n" /* Return. */
         "                                           \n"
         "   .align 4                                \n"
         ::: "r0", "memory"
@@ -1358,10 +1375,10 @@ void vResetPrivilege( void ) /* __attribute__ (( naked )) */
 {
     __asm volatile
     (
-        "   mrs r0, control                         \n"/* r0 = CONTROL. */
-        "   orr r0, #1                              \n"/* r0 = r0 | 1. */
-        "   msr control, r0                         \n"/* CONTROL = r0. */
-        "   bx lr                                   \n"/* Return to the caller. */
+        "   mrs r0, control                         \n" /* r0 = CONTROL. */
+        "   orr r0, #1                              \n" /* r0 = r0 | 1. */
+        "   msr control, r0                         \n" /* CONTROL = r0. */
+        "   bx lr                                   \n" /* Return to the caller. */
         ::: "r0", "memory"
     );
 }
@@ -1397,7 +1414,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
         xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
             ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */
             ( portMPU_REGION_VALID ) |
-            ( portSTACK_REGION ); /* Region number. */
+            ( portSTACK_REGION );                     /* Region number. */
 
         xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
             ( portMPU_REGION_READ_WRITE ) |
@@ -1471,11 +1488,13 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
                 xMPUSettings->xRegionSettings[ ul ].ulRegionStartAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress;
                 xMPUSettings->xRegionSettings[ ul ].ulRegionEndAddress = ( uint32_t ) ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1UL );
                 xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = 0UL;
+
                 if( ( ( xRegions[ lIndex ].ulParameters & portMPU_REGION_READ_ONLY ) == portMPU_REGION_READ_ONLY ) ||
                     ( ( xRegions[ lIndex ].ulParameters & portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ) == portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ) )
                 {
                     xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = tskMPU_READ_PERMISSION;
                 }
+
                 if( ( xRegions[ lIndex ].ulParameters & portMPU_REGION_READ_WRITE ) == portMPU_REGION_READ_WRITE )
                 {
                     xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = ( tskMPU_READ_PERMISSION | tskMPU_WRITE_PERMISSION );
@@ -1592,7 +1611,7 @@ BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
          * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
          * scheduler.  Note however that some vendor specific peripheral libraries
          * assume a non-zero priority group setting, in which cases using a value
-         * of zero will result in unpredicable behaviour. */
+         * of zero will result in unpredictable behaviour. */
         configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
     }
 
diff --git a/portable/GCC/ARM_CM4_MPU/portmacro.h b/portable/GCC/ARM_CM4_MPU/portmacro.h
index 9a8891b30..c2d2464b4 100644
--- a/portable/GCC/ARM_CM4_MPU/portmacro.h
+++ b/portable/GCC/ARM_CM4_MPU/portmacro.h
@@ -63,7 +63,7 @@ typedef unsigned long    UBaseType_t;
 #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
     typedef uint16_t     TickType_t;
     #define portMAX_DELAY              ( TickType_t ) 0xffff
-#elif ( configTICK_TYPE_WIDTH_IN_BITS  == TICK_TYPE_WIDTH_32_BITS )
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
     typedef uint32_t     TickType_t;
     #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
@@ -71,13 +71,13 @@ typedef unsigned long    UBaseType_t;
  * not need to be guarded with a critical section. */
     #define portTICK_TYPE_IS_ATOMIC    1
 #else
-    #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+    #error "configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width."
 #endif
 
 /* Errata 837070 workaround must be enabled on Cortex-M7 r0p0
  * and r0p1 cores. */
 #ifndef configENABLE_ERRATA_837070_WORKAROUND
-    #define configENABLE_ERRATA_837070_WORKAROUND 0
+    #define configENABLE_ERRATA_837070_WORKAROUND    0
 #endif
 /*-----------------------------------------------------------*/
 
@@ -208,7 +208,7 @@ typedef struct MPU_REGION_SETTINGS
 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
 
     #ifndef configSYSTEM_CALL_STACK_SIZE
-        #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
+        #error "configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2."
     #endif
 
     typedef struct SYSTEM_CALL_STACK_INFO
@@ -221,11 +221,11 @@ typedef struct MPU_REGION_SETTINGS
 
 #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
-#define MAX_CONTEXT_SIZE 52
+#define MAX_CONTEXT_SIZE                    52
 
 /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
-#define portSTACK_FRAME_HAS_PADDING_FLAG     ( 1UL << 0UL )
-#define portTASK_IS_PRIVILEGED_FLAG          ( 1UL << 1UL )
+#define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
+#define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
 typedef struct MPU_SETTINGS
 {
@@ -247,16 +247,16 @@ typedef struct MPU_SETTINGS
 /*-----------------------------------------------------------*/
 
 /* SVC numbers for various services. */
-#define portSVC_START_SCHEDULER     0
-#define portSVC_YIELD               1
-#define portSVC_RAISE_PRIVILEGE     2
-#define portSVC_SYSTEM_CALL_ENTER   3   /* System calls with upto 4 parameters. */
-#define portSVC_SYSTEM_CALL_ENTER_1 4   /* System calls with 5 parameters. */
-#define portSVC_SYSTEM_CALL_EXIT    5
+#define portSVC_START_SCHEDULER        0
+#define portSVC_YIELD                  1
+#define portSVC_RAISE_PRIVILEGE        2
+#define portSVC_SYSTEM_CALL_ENTER      3 /* System calls with upto 4 parameters. */
+#define portSVC_SYSTEM_CALL_ENTER_1    4 /* System calls with 5 parameters. */
+#define portSVC_SYSTEM_CALL_EXIT       5
 
 /* Scheduler utilities. */
 
-#define portYIELD()    __asm volatile ( "   SVC %0  \n"::"i" ( portSVC_YIELD ) : "memory" )
+#define portYIELD()    __asm volatile ( "   SVC %0  \n" ::"i" ( portSVC_YIELD ) : "memory" )
 #define portYIELD_WITHIN_API()                          \
     {                                                   \
         /* Set a PendSV to request a context switch. */ \
@@ -270,8 +270,10 @@ typedef struct MPU_SETTINGS
 
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )
-#define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+#define portEND_SWITCHING_ISR( xSwitchRequired )                                 \
+    do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
+    while( 0 )
+#define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
 /* Critical section management. */
@@ -312,7 +314,7 @@ extern void vPortExitCritical( void );
 
 /* Check the configuration. */
     #if ( configMAX_PRIORITIES > 32 )
-        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+        #error "configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice."
     #endif
 
 /* Store/clear the ready priorities in a bit map. */
@@ -371,7 +373,7 @@ extern BaseType_t xPortIsTaskPrivileged( void );
  *
  * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
  */
-#define portIS_TASK_PRIVILEGED()      xPortIsTaskPrivileged()
+#define portIS_TASK_PRIVILEGED()    xPortIsTaskPrivileged()
 /*-----------------------------------------------------------*/
 
 portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
@@ -404,13 +406,13 @@ portFORCE_INLINE static void vPortRaiseBASEPRI( void )
     (
         "   mov %0, %1                                              \n"
         #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
-            "   cpsid i                                             \n"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
+            "   cpsid i                                             \n" /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
         #endif
         "   msr basepri, %0                                         \n"
         "   isb                                                     \n"
         "   dsb                                                     \n"
         #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
-            "   cpsie i                                             \n"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
+            "   cpsie i                                             \n" /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
         #endif
         : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
     );
@@ -427,13 +429,13 @@ portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
         "   mrs %0, basepri                                         \n"
         "   mov %1, %2                                              \n"
         #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
-            "   cpsid i                                             \n"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
+            "   cpsid i                                             \n" /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
         #endif
         "   msr basepri, %1                                         \n"
         "   isb                                                     \n"
         "   dsb                                                     \n"
         #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
-            "   cpsie i                                             \n"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
+            "   cpsie i                                             \n" /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
         #endif
         : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
     );
@@ -448,7 +450,7 @@ portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
 {
     __asm volatile
     (
-        "   msr basepri, %0 "::"r" ( ulNewMaskValue ) : "memory"
+        "   msr basepri, %0 " ::"r" ( ulNewMaskValue ) : "memory"
     );
 }
 /*-----------------------------------------------------------*/
@@ -456,7 +458,7 @@ portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
 #define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
 
 #ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY
-    #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. https://www.FreeRTOS.org/FreeRTOS-V10.3.x.html"
+    #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. www.FreeRTOS.org/FreeRTOS-V10.3.x.html"
     #define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY    0
 #endif
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM55/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM55/non_secure/mpu_wrappers_v2_asm.c
index 2d1218a95..d1fbdc0e5 100644
--- a/portable/GCC/ARM_CM55/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM55/non_secure/mpu_wrappers_v2_asm.c
@@ -44,2274 +44,2274 @@
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-#if ( INCLUDE_xTaskDelayUntil == 1 )
+    #if ( INCLUDE_xTaskDelayUntil == 1 )
 
-BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
-                                const TickType_t xTimeIncrement ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
+                                        const TickType_t xTimeIncrement ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
-                                const TickType_t xTimeIncrement ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskDelayUntilImpl                       \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskDelayUntil_Unpriv                        \n"
-        " MPU_xTaskDelayUntil_Priv:                             \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskDelayUntilImpl                         \n"
-        " MPU_xTaskDelayUntil_Unpriv:                           \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskDelayUntilImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
+                                        const TickType_t xTimeIncrement ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskDelayUntilImpl                       \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskDelayUntil_Unpriv                        \n"
+                " MPU_xTaskDelayUntil_Priv:                             \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskDelayUntilImpl                         \n"
+                " MPU_xTaskDelayUntil_Unpriv:                           \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskDelayUntilImpl                        \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */
+    #endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_xTaskAbortDelay == 1 )
+    #if ( INCLUDE_xTaskAbortDelay == 1 )
 
-BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskAbortDelayImpl                       \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskAbortDelay_Unpriv                        \n"
-        " MPU_xTaskAbortDelay_Priv:                             \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskAbortDelayImpl                         \n"
-        " MPU_xTaskAbortDelay_Unpriv:                           \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskAbortDelayImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskAbortDelayImpl                       \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskAbortDelay_Unpriv                        \n"
+                " MPU_xTaskAbortDelay_Priv:                             \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskAbortDelayImpl                         \n"
+                " MPU_xTaskAbortDelay_Unpriv:                           \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskAbortDelayImpl                        \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */
+    #endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_vTaskDelay == 1 )
+    #if ( INCLUDE_vTaskDelay == 1 )
 
-void MPU_vTaskDelay( const TickType_t xTicksToDelay ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskDelay( const TickType_t xTicksToDelay ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskDelayImpl                            \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskDelay_Unpriv                             \n"
-        " MPU_vTaskDelay_Priv:                                  \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskDelayImpl                              \n"
-        " MPU_vTaskDelay_Unpriv:                                \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskDelayImpl                             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskDelayImpl                            \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskDelay_Unpriv                             \n"
+                " MPU_vTaskDelay_Priv:                                  \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskDelayImpl                              \n"
+                " MPU_vTaskDelay_Unpriv:                                \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskDelayImpl                             \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_vTaskDelay == 1 ) */
+    #endif /* if ( INCLUDE_vTaskDelay == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_uxTaskPriorityGet == 1 )
+    #if ( INCLUDE_uxTaskPriorityGet == 1 )
 
-UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskPriorityGetImpl                     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTaskPriorityGet_Unpriv                      \n"
-        " MPU_uxTaskPriorityGet_Priv:                           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTaskPriorityGetImpl                       \n"
-        " MPU_uxTaskPriorityGet_Unpriv:                         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskPriorityGetImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskPriorityGetImpl                     \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTaskPriorityGet_Unpriv                      \n"
+                " MPU_uxTaskPriorityGet_Priv:                           \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTaskPriorityGetImpl                       \n"
+                " MPU_uxTaskPriorityGet_Unpriv:                         \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskPriorityGetImpl                      \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */
+    #endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_eTaskGetState == 1 )
+    #if ( INCLUDE_eTaskGetState == 1 )
 
-eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_eTaskGetStateImpl                         \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_eTaskGetState_Unpriv                          \n"
-        " MPU_eTaskGetState_Priv:                               \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_eTaskGetStateImpl                           \n"
-        " MPU_eTaskGetState_Unpriv:                             \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_eTaskGetStateImpl                          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_eTaskGetStateImpl                         \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_eTaskGetState_Unpriv                          \n"
+                " MPU_eTaskGetState_Priv:                               \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_eTaskGetStateImpl                           \n"
+                " MPU_eTaskGetState_Unpriv:                             \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_eTaskGetStateImpl                          \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_eTaskGetState == 1 ) */
+    #endif /* if ( INCLUDE_eTaskGetState == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-void MPU_vTaskGetInfo( TaskHandle_t xTask,
-                       TaskStatus_t * pxTaskStatus,
-                       BaseType_t xGetFreeStackSpace,
-                       eTaskState eState ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskGetInfo( TaskHandle_t xTask,
+                               TaskStatus_t * pxTaskStatus,
+                               BaseType_t xGetFreeStackSpace,
+                               eTaskState eState ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskGetInfo( TaskHandle_t xTask,
-                       TaskStatus_t * pxTaskStatus,
-                       BaseType_t xGetFreeStackSpace,
-                       eTaskState eState ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskGetInfoImpl                          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskGetInfo_Unpriv                           \n"
-        " MPU_vTaskGetInfo_Priv:                                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskGetInfoImpl                            \n"
-        " MPU_vTaskGetInfo_Unpriv:                              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskGetInfoImpl                           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskGetInfo( TaskHandle_t xTask,
+                               TaskStatus_t * pxTaskStatus,
+                               BaseType_t xGetFreeStackSpace,
+                               eTaskState eState ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskGetInfoImpl                          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskGetInfo_Unpriv                           \n"
+                " MPU_vTaskGetInfo_Priv:                                \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskGetInfoImpl                            \n"
+                " MPU_vTaskGetInfo_Unpriv:                              \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskGetInfoImpl                           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
+    #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
+    #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
 
-TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetIdleTaskHandleImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGetIdleTaskHandle_Unpriv                 \n"
-        " MPU_xTaskGetIdleTaskHandle_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGetIdleTaskHandleImpl                  \n"
-        " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetIdleTaskHandleImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetIdleTaskHandleImpl                \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGetIdleTaskHandle_Unpriv                 \n"
+                " MPU_xTaskGetIdleTaskHandle_Priv:                      \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGetIdleTaskHandleImpl                  \n"
+                " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetIdleTaskHandleImpl                 \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */
+    #endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_vTaskSuspend == 1 )
+    #if ( INCLUDE_vTaskSuspend == 1 )
 
-void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSuspendImpl                          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskSuspend_Unpriv                           \n"
-        " MPU_vTaskSuspend_Priv:                                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskSuspendImpl                            \n"
-        " MPU_vTaskSuspend_Unpriv:                              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSuspendImpl                           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskSuspendImpl                          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskSuspend_Unpriv                           \n"
+                " MPU_vTaskSuspend_Priv:                                \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskSuspendImpl                            \n"
+                " MPU_vTaskSuspend_Unpriv:                              \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskSuspendImpl                           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
+    #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_vTaskSuspend == 1 )
+    #if ( INCLUDE_vTaskSuspend == 1 )
 
-void MPU_vTaskResume( TaskHandle_t xTaskToResume ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskResume( TaskHandle_t xTaskToResume ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskResumeImpl                           \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskResume_Unpriv                            \n"
-        " MPU_vTaskResume_Priv:                                 \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskResumeImpl                             \n"
-        " MPU_vTaskResume_Unpriv:                               \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskResumeImpl                            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskResumeImpl                           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskResume_Unpriv                            \n"
+                " MPU_vTaskResume_Priv:                                 \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskResumeImpl                             \n"
+                " MPU_vTaskResume_Unpriv:                               \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskResumeImpl                            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
+    #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
 /*-----------------------------------------------------------*/
 
-TickType_t MPU_xTaskGetTickCount( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    TickType_t MPU_xTaskGetTickCount( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TickType_t MPU_xTaskGetTickCount( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetTickCountImpl                     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGetTickCount_Unpriv                      \n"
-        " MPU_xTaskGetTickCount_Priv:                           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGetTickCountImpl                       \n"
-        " MPU_xTaskGetTickCount_Unpriv:                         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetTickCountImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    TickType_t MPU_xTaskGetTickCount( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xTaskGetTickCountImpl                     \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xTaskGetTickCount_Unpriv                      \n"
+            " MPU_xTaskGetTickCount_Priv:                           \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xTaskGetTickCountImpl                       \n"
+            " MPU_xTaskGetTickCount_Unpriv:                         \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xTaskGetTickCountImpl                      \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetNumberOfTasksImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTaskGetNumberOfTasks_Unpriv                 \n"
-        " MPU_uxTaskGetNumberOfTasks_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTaskGetNumberOfTasksImpl                  \n"
-        " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetNumberOfTasksImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_uxTaskGetNumberOfTasksImpl                \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_uxTaskGetNumberOfTasks_Unpriv                 \n"
+            " MPU_uxTaskGetNumberOfTasks_Priv:                      \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_uxTaskGetNumberOfTasksImpl                  \n"
+            " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_uxTaskGetNumberOfTasksImpl                 \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configGENERATE_RUN_TIME_STATS == 1 )
+    #if ( configGENERATE_RUN_TIME_STATS == 1 )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetRunTimeCounterImpl               \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGetRunTimeCounter_Unpriv                \n"
-        " MPU_ulTaskGetRunTimeCounter_Priv:                     \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGetRunTimeCounterImpl                 \n"
-        " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetRunTimeCounterImpl                \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetRunTimeCounterImpl               \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGetRunTimeCounter_Unpriv                \n"
+                " MPU_ulTaskGetRunTimeCounter_Priv:                     \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGetRunTimeCounterImpl                 \n"
+                " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetRunTimeCounterImpl                \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configGENERATE_RUN_TIME_STATS == 1 )
+    #if ( configGENERATE_RUN_TIME_STATS == 1 )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetRunTimePercentImpl               \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGetRunTimePercent_Unpriv                \n"
-        " MPU_ulTaskGetRunTimePercent_Priv:                     \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGetRunTimePercentImpl                 \n"
-        " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetRunTimePercentImpl                \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetRunTimePercentImpl               \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGetRunTimePercent_Unpriv                \n"
+                " MPU_ulTaskGetRunTimePercent_Priv:                     \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGetRunTimePercentImpl                 \n"
+                " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetRunTimePercentImpl                \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+    #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetIdleRunTimePercentImpl           \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv            \n"
-        " MPU_ulTaskGetIdleRunTimePercent_Priv:                 \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGetIdleRunTimePercentImpl             \n"
-        " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetIdleRunTimePercentImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetIdleRunTimePercentImpl           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv            \n"
+                " MPU_ulTaskGetIdleRunTimePercent_Priv:                 \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGetIdleRunTimePercentImpl             \n"
+                " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetIdleRunTimePercentImpl            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+    #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetIdleRunTimeCounterImpl           \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv            \n"
-        " MPU_ulTaskGetIdleRunTimeCounter_Priv:                 \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGetIdleRunTimeCounterImpl             \n"
-        " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetIdleRunTimeCounterImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetIdleRunTimeCounterImpl           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv            \n"
+                " MPU_ulTaskGetIdleRunTimeCounter_Priv:                 \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGetIdleRunTimeCounterImpl             \n"
+                " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetIdleRunTimeCounterImpl            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+    #if ( configUSE_APPLICATION_TASK_TAG == 1 )
 
-void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
-                                     TaskHookFunction_t pxHookFunction ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
+                                             TaskHookFunction_t pxHookFunction ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
-                                     TaskHookFunction_t pxHookFunction ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSetApplicationTaskTagImpl            \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskSetApplicationTaskTag_Unpriv             \n"
-        " MPU_vTaskSetApplicationTaskTag_Priv:                  \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskSetApplicationTaskTagImpl              \n"
-        " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSetApplicationTaskTagImpl             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
+                                             TaskHookFunction_t pxHookFunction ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskSetApplicationTaskTagImpl            \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskSetApplicationTaskTag_Unpriv             \n"
+                " MPU_vTaskSetApplicationTaskTag_Priv:                  \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskSetApplicationTaskTagImpl              \n"
+                " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskSetApplicationTaskTagImpl             \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
+    #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+    #if ( configUSE_APPLICATION_TASK_TAG == 1 )
 
-TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetApplicationTaskTagImpl            \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGetApplicationTaskTag_Unpriv             \n"
-        " MPU_xTaskGetApplicationTaskTag_Priv:                  \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGetApplicationTaskTagImpl              \n"
-        " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetApplicationTaskTagImpl             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetApplicationTaskTagImpl            \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGetApplicationTaskTag_Unpriv             \n"
+                " MPU_xTaskGetApplicationTaskTag_Priv:                  \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGetApplicationTaskTagImpl              \n"
+                " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetApplicationTaskTagImpl             \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
+    #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+    #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
 
-void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
-                                            BaseType_t xIndex,
-                                            void * pvValue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
+                                                    BaseType_t xIndex,
+                                                    void * pvValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
-                                            BaseType_t xIndex,
-                                            void * pvValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSetThreadLocalStoragePointerImpl     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv      \n"
-        " MPU_vTaskSetThreadLocalStoragePointer_Priv:           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskSetThreadLocalStoragePointerImpl       \n"
-        " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSetThreadLocalStoragePointerImpl      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
+                                                    BaseType_t xIndex,
+                                                    void * pvValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskSetThreadLocalStoragePointerImpl     \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv      \n"
+                " MPU_vTaskSetThreadLocalStoragePointer_Priv:           \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskSetThreadLocalStoragePointerImpl       \n"
+                " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskSetThreadLocalStoragePointerImpl      \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
+    #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+    #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
 
-void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
-                                               BaseType_t xIndex ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
+                                                       BaseType_t xIndex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
-                                               BaseType_t xIndex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pvTaskGetThreadLocalStoragePointerImpl    \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv     \n"
-        " MPU_pvTaskGetThreadLocalStoragePointer_Priv:          \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_pvTaskGetThreadLocalStoragePointerImpl      \n"
-        " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pvTaskGetThreadLocalStoragePointerImpl     \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
+                                                       BaseType_t xIndex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pvTaskGetThreadLocalStoragePointerImpl    \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv     \n"
+                " MPU_pvTaskGetThreadLocalStoragePointer_Priv:          \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_pvTaskGetThreadLocalStoragePointerImpl      \n"
+                " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pvTaskGetThreadLocalStoragePointerImpl     \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
+    #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
-                                      const UBaseType_t uxArraySize,
-                                      configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
+                                              const UBaseType_t uxArraySize,
+                                              configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
-                                      const UBaseType_t uxArraySize,
-                                      configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetSystemStateImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTaskGetSystemState_Unpriv                   \n"
-        " MPU_uxTaskGetSystemState_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTaskGetSystemStateImpl                    \n"
-        " MPU_uxTaskGetSystemState_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetSystemStateImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
+                                              const UBaseType_t uxArraySize,
+                                              configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskGetSystemStateImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTaskGetSystemState_Unpriv                   \n"
+                " MPU_uxTaskGetSystemState_Priv:                        \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTaskGetSystemStateImpl                    \n"
+                " MPU_uxTaskGetSystemState_Unpriv:                      \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskGetSystemStateImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
+    #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
+    #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
 
-UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetStackHighWaterMarkImpl           \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTaskGetStackHighWaterMark_Unpriv            \n"
-        " MPU_uxTaskGetStackHighWaterMark_Priv:                 \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTaskGetStackHighWaterMarkImpl             \n"
-        " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetStackHighWaterMarkImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskGetStackHighWaterMarkImpl           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTaskGetStackHighWaterMark_Unpriv            \n"
+                " MPU_uxTaskGetStackHighWaterMark_Priv:                 \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTaskGetStackHighWaterMarkImpl             \n"
+                " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskGetStackHighWaterMarkImpl            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */
+    #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
+    #if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
 
-configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetStackHighWaterMark2Impl          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv           \n"
-        " MPU_uxTaskGetStackHighWaterMark2_Priv:                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTaskGetStackHighWaterMark2Impl            \n"
-        " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetStackHighWaterMark2Impl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskGetStackHighWaterMark2Impl          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv           \n"
+                " MPU_uxTaskGetStackHighWaterMark2_Priv:                \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTaskGetStackHighWaterMark2Impl            \n"
+                " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskGetStackHighWaterMark2Impl           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */
+    #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
+    #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
 
-TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetCurrentTaskHandleImpl             \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGetCurrentTaskHandle_Unpriv              \n"
-        " MPU_xTaskGetCurrentTaskHandle_Priv:                   \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGetCurrentTaskHandleImpl               \n"
-        " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetCurrentTaskHandleImpl              \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetCurrentTaskHandleImpl             \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGetCurrentTaskHandle_Unpriv              \n"
+                " MPU_xTaskGetCurrentTaskHandle_Priv:                   \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGetCurrentTaskHandleImpl               \n"
+                " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetCurrentTaskHandleImpl              \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
+    #endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_xTaskGetSchedulerState == 1 )
+    #if ( INCLUDE_xTaskGetSchedulerState == 1 )
 
-BaseType_t MPU_xTaskGetSchedulerState( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGetSchedulerState( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGetSchedulerState( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetSchedulerStateImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGetSchedulerState_Unpriv                 \n"
-        " MPU_xTaskGetSchedulerState_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGetSchedulerStateImpl                  \n"
-        " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetSchedulerStateImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGetSchedulerState( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetSchedulerStateImpl                \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGetSchedulerState_Unpriv                 \n"
+                " MPU_xTaskGetSchedulerState_Priv:                      \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGetSchedulerStateImpl                  \n"
+                " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetSchedulerStateImpl                 \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */
+    #endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */
 /*-----------------------------------------------------------*/
 
-void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSetTimeOutStateImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskSetTimeOutState_Unpriv                   \n"
-        " MPU_vTaskSetTimeOutState_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskSetTimeOutStateImpl                    \n"
-        " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSetTimeOutStateImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_vTaskSetTimeOutStateImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_vTaskSetTimeOutState_Unpriv                   \n"
+            " MPU_vTaskSetTimeOutState_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_vTaskSetTimeOutStateImpl                    \n"
+            " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_vTaskSetTimeOutStateImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
-                                     TickType_t * const pxTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
+                                         TickType_t * const pxTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
-                                     TickType_t * const pxTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskCheckForTimeOutImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskCheckForTimeOut_Unpriv                   \n"
-        " MPU_xTaskCheckForTimeOut_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskCheckForTimeOutImpl                    \n"
-        " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskCheckForTimeOutImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
+                                         TickType_t * const pxTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xTaskCheckForTimeOutImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xTaskCheckForTimeOut_Unpriv                   \n"
+            " MPU_xTaskCheckForTimeOut_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xTaskCheckForTimeOutImpl                    \n"
+            " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xTaskCheckForTimeOutImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                   UBaseType_t uxIndexToNotify,
-                                   uint32_t ulValue,
-                                   eNotifyAction eAction,
-                                   uint32_t * pulPreviousNotificationValue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
+                                           UBaseType_t uxIndexToNotify,
+                                           uint32_t ulValue,
+                                           eNotifyAction eAction,
+                                           uint32_t * pulPreviousNotificationValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                   UBaseType_t uxIndexToNotify,
-                                   uint32_t ulValue,
-                                   eNotifyAction eAction,
-                                   uint32_t * pulPreviousNotificationValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGenericNotifyImpl                    \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGenericNotify_Unpriv                     \n"
-        " MPU_xTaskGenericNotify_Priv:                          \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGenericNotifyImpl                      \n"
-        " MPU_xTaskGenericNotify_Unpriv:                        \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGenericNotifyImpl                     \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
+                                           UBaseType_t uxIndexToNotify,
+                                           uint32_t ulValue,
+                                           eNotifyAction eAction,
+                                           uint32_t * pulPreviousNotificationValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGenericNotifyImpl                    \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGenericNotify_Unpriv                     \n"
+                " MPU_xTaskGenericNotify_Priv:                          \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGenericNotifyImpl                      \n"
+                " MPU_xTaskGenericNotify_Unpriv:                        \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGenericNotifyImpl                     \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                       uint32_t ulBitsToClearOnEntry,
-                                       uint32_t ulBitsToClearOnExit,
-                                       uint32_t * pulNotificationValue,
-                                       TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
+                                               uint32_t ulBitsToClearOnEntry,
+                                               uint32_t ulBitsToClearOnExit,
+                                               uint32_t * pulNotificationValue,
+                                               TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                       uint32_t ulBitsToClearOnEntry,
-                                       uint32_t ulBitsToClearOnExit,
-                                       uint32_t * pulNotificationValue,
-                                       TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGenericNotifyWaitImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGenericNotifyWait_Unpriv                 \n"
-        " MPU_xTaskGenericNotifyWait_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGenericNotifyWaitImpl                  \n"
-        " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGenericNotifyWaitImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
+                                               uint32_t ulBitsToClearOnEntry,
+                                               uint32_t ulBitsToClearOnExit,
+                                               uint32_t * pulNotificationValue,
+                                               TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGenericNotifyWaitImpl                \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGenericNotifyWait_Unpriv                 \n"
+                " MPU_xTaskGenericNotifyWait_Priv:                      \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGenericNotifyWaitImpl                  \n"
+                " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGenericNotifyWaitImpl                 \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
-                                      BaseType_t xClearCountOnExit,
-                                      TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
+                                              BaseType_t xClearCountOnExit,
+                                              TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
-                                      BaseType_t xClearCountOnExit,
-                                      TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGenericNotifyTakeImpl               \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGenericNotifyTake_Unpriv                \n"
-        " MPU_ulTaskGenericNotifyTake_Priv:                     \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGenericNotifyTakeImpl                 \n"
-        " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGenericNotifyTakeImpl                \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
+                                              BaseType_t xClearCountOnExit,
+                                              TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGenericNotifyTakeImpl               \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGenericNotifyTake_Unpriv                \n"
+                " MPU_ulTaskGenericNotifyTake_Priv:                     \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGenericNotifyTakeImpl                 \n"
+                " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGenericNotifyTakeImpl                \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
-                                             UBaseType_t uxIndexToClear ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
+                                                     UBaseType_t uxIndexToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
-                                             UBaseType_t uxIndexToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGenericNotifyStateClearImpl          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGenericNotifyStateClear_Unpriv           \n"
-        " MPU_xTaskGenericNotifyStateClear_Priv:                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGenericNotifyStateClearImpl            \n"
-        " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGenericNotifyStateClearImpl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
+                                                     UBaseType_t uxIndexToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGenericNotifyStateClearImpl          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGenericNotifyStateClear_Unpriv           \n"
+                " MPU_xTaskGenericNotifyStateClear_Priv:                \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGenericNotifyStateClearImpl            \n"
+                " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGenericNotifyStateClearImpl           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
-                                            UBaseType_t uxIndexToClear,
-                                            uint32_t ulBitsToClear ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
+                                                    UBaseType_t uxIndexToClear,
+                                                    uint32_t ulBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
-                                            UBaseType_t uxIndexToClear,
-                                            uint32_t ulBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGenericNotifyValueClearImpl         \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGenericNotifyValueClear_Unpriv          \n"
-        " MPU_ulTaskGenericNotifyValueClear_Priv:               \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGenericNotifyValueClearImpl           \n"
-        " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGenericNotifyValueClearImpl          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
+                                                    UBaseType_t uxIndexToClear,
+                                                    uint32_t ulBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGenericNotifyValueClearImpl         \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGenericNotifyValueClear_Unpriv          \n"
+                " MPU_ulTaskGenericNotifyValueClear_Priv:               \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGenericNotifyValueClearImpl           \n"
+                " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGenericNotifyValueClearImpl          \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
-                                  const void * const pvItemToQueue,
-                                  TickType_t xTicksToWait,
-                                  const BaseType_t xCopyPosition ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
+                                      const void * const pvItemToQueue,
+                                      TickType_t xTicksToWait,
+                                      const BaseType_t xCopyPosition ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
-                                  const void * const pvItemToQueue,
-                                  TickType_t xTicksToWait,
-                                  const BaseType_t xCopyPosition ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueGenericSendImpl                     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueGenericSend_Unpriv                      \n"
-        " MPU_xQueueGenericSend_Priv:                           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueGenericSendImpl                       \n"
-        " MPU_xQueueGenericSend_Unpriv:                         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueGenericSendImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
+                                      const void * const pvItemToQueue,
+                                      TickType_t xTicksToWait,
+                                      const BaseType_t xCopyPosition ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueueGenericSendImpl                     \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xQueueGenericSend_Unpriv                      \n"
+            " MPU_xQueueGenericSend_Priv:                           \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xQueueGenericSendImpl                       \n"
+            " MPU_xQueueGenericSend_Unpriv:                         \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueueGenericSendImpl                      \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxQueueMessagesWaitingImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxQueueMessagesWaiting_Unpriv                 \n"
-        " MPU_uxQueueMessagesWaiting_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxQueueMessagesWaitingImpl                  \n"
-        " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxQueueMessagesWaitingImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_uxQueueMessagesWaitingImpl                \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_uxQueueMessagesWaiting_Unpriv                 \n"
+            " MPU_uxQueueMessagesWaiting_Priv:                      \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_uxQueueMessagesWaitingImpl                  \n"
+            " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_uxQueueMessagesWaitingImpl                 \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxQueueSpacesAvailableImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxQueueSpacesAvailable_Unpriv                 \n"
-        " MPU_uxQueueSpacesAvailable_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxQueueSpacesAvailableImpl                  \n"
-        " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxQueueSpacesAvailableImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_uxQueueSpacesAvailableImpl                \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_uxQueueSpacesAvailable_Unpriv                 \n"
+            " MPU_uxQueueSpacesAvailable_Priv:                      \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_uxQueueSpacesAvailableImpl                  \n"
+            " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_uxQueueSpacesAvailableImpl                 \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
-                              void * const pvBuffer,
-                              TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
+                                  void * const pvBuffer,
+                                  TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
-                              void * const pvBuffer,
-                              TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueReceiveImpl                         \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueReceive_Unpriv                          \n"
-        " MPU_xQueueReceive_Priv:                               \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueReceiveImpl                           \n"
-        " MPU_xQueueReceive_Unpriv:                             \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueReceiveImpl                          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
+                                  void * const pvBuffer,
+                                  TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueueReceiveImpl                         \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xQueueReceive_Unpriv                          \n"
+            " MPU_xQueueReceive_Priv:                               \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xQueueReceiveImpl                           \n"
+            " MPU_xQueueReceive_Unpriv:                             \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueueReceiveImpl                          \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
-                           void * const pvBuffer,
-                           TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
+                               void * const pvBuffer,
+                               TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
-                           void * const pvBuffer,
-                           TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueuePeekImpl                            \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueuePeek_Unpriv                             \n"
-        " MPU_xQueuePeek_Priv:                                  \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueuePeekImpl                              \n"
-        " MPU_xQueuePeek_Unpriv:                                \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueuePeekImpl                             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
+                               void * const pvBuffer,
+                               TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueuePeekImpl                            \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xQueuePeek_Unpriv                             \n"
+            " MPU_xQueuePeek_Priv:                                  \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xQueuePeekImpl                              \n"
+            " MPU_xQueuePeek_Unpriv:                                \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueuePeekImpl                             \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
-                                    TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
+                                        TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
-                                    TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueSemaphoreTakeImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueSemaphoreTake_Unpriv                    \n"
-        " MPU_xQueueSemaphoreTake_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueSemaphoreTakeImpl                     \n"
-        " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueSemaphoreTakeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
+                                        TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueueSemaphoreTakeImpl                   \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xQueueSemaphoreTake_Unpriv                    \n"
+            " MPU_xQueueSemaphoreTake_Priv:                         \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xQueueSemaphoreTakeImpl                     \n"
+            " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueueSemaphoreTakeImpl                    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+    #if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
 
-TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueGetMutexHolderImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueGetMutexHolder_Unpriv                   \n"
-        " MPU_xQueueGetMutexHolder_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueGetMutexHolderImpl                    \n"
-        " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueGetMutexHolderImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueGetMutexHolderImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueGetMutexHolder_Unpriv                   \n"
+                " MPU_xQueueGetMutexHolder_Priv:                        \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueGetMutexHolderImpl                    \n"
+                " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueGetMutexHolderImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */
+    #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+    #if ( configUSE_RECURSIVE_MUTEXES == 1 )
 
-BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
-                                         TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+                                                 TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+        BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+                                                 TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueTakeMutexRecursiveImpl              \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueTakeMutexRecursive_Unpriv               \n"
+                " MPU_xQueueTakeMutexRecursive_Priv:                    \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueTakeMutexRecursiveImpl                \n"
+                " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueTakeMutexRecursiveImpl               \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_RECURSIVE_MUTEXES == 1 )
+
+        BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueGiveMutexRecursiveImpl              \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueGiveMutexRecursive_Unpriv               \n"
+                " MPU_xQueueGiveMutexRecursive_Priv:                    \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueGiveMutexRecursiveImpl                \n"
+                " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueGiveMutexRecursiveImpl               \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_QUEUE_SETS == 1 )
+
+        QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
+                                                        const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
+                                                        const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueSelectFromSetImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueSelectFromSet_Unpriv                    \n"
+                " MPU_xQueueSelectFromSet_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueSelectFromSetImpl                     \n"
+                " MPU_xQueueSelectFromSet_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueSelectFromSetImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_QUEUE_SETS == 1 )
+
+        BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                                       QueueSetHandle_t xQueueSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                                       QueueSetHandle_t xQueueSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueAddToSetImpl                        \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueAddToSet_Unpriv                         \n"
+                " MPU_xQueueAddToSet_Priv:                              \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueAddToSetImpl                          \n"
+                " MPU_xQueueAddToSet_Unpriv:                            \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueAddToSetImpl                         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+        void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
+                                      const char * pcName ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
+                                      const char * pcName ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vQueueAddToRegistryImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vQueueAddToRegistry_Unpriv                    \n"
+                " MPU_vQueueAddToRegistry_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vQueueAddToRegistryImpl                     \n"
+                " MPU_vQueueAddToRegistry_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vQueueAddToRegistryImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+        void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vQueueUnregisterQueueImpl                 \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vQueueUnregisterQueue_Unpriv                  \n"
+                " MPU_vQueueUnregisterQueue_Priv:                       \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vQueueUnregisterQueueImpl                   \n"
+                " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vQueueUnregisterQueueImpl                  \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+        const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pcQueueGetNameImpl                        \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_pcQueueGetName_Unpriv                         \n"
+                " MPU_pcQueueGetName_Priv:                              \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_pcQueueGetNameImpl                          \n"
+                " MPU_pcQueueGetName_Unpriv:                            \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pcQueueGetNameImpl                         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pvTimerGetTimerIDImpl                     \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_pvTimerGetTimerID_Unpriv                      \n"
+                " MPU_pvTimerGetTimerID_Priv:                           \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_pvTimerGetTimerIDImpl                       \n"
+                " MPU_pvTimerGetTimerID_Unpriv:                         \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pvTimerGetTimerIDImpl                      \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
+                                   void * pvNewID ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
+                                   void * pvNewID ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTimerSetTimerIDImpl                      \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTimerSetTimerID_Unpriv                       \n"
+                " MPU_vTimerSetTimerID_Priv:                            \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTimerSetTimerIDImpl                        \n"
+                " MPU_vTimerSetTimerID_Unpriv:                          \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTimerSetTimerIDImpl                       \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerIsTimerActiveImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerIsTimerActive_Unpriv                    \n"
+                " MPU_xTimerIsTimerActive_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerIsTimerActiveImpl                     \n"
+                " MPU_xTimerIsTimerActive_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerIsTimerActiveImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetTimerDaemonTaskHandleImpl        \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv         \n"
+                " MPU_xTimerGetTimerDaemonTaskHandle_Priv:              \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerGetTimerDaemonTaskHandleImpl          \n"
+                " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetTimerDaemonTaskHandleImpl         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                                     const BaseType_t xCommandID,
+                                                     const TickType_t xOptionalValue,
+                                                     BaseType_t * const pxHigherPriorityTaskWoken,
+                                                     const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                                     const BaseType_t xCommandID,
+                                                     const TickType_t xOptionalValue,
+                                                     BaseType_t * const pxHigherPriorityTaskWoken,
+                                                     const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                               \n"
+                " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
+                "                                                               \n"
+                " push {r0}                                                     \n"
+                " mrs r0, control                                               \n"
+                " tst r0, #1                                                    \n"
+                " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
+                " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
+                "     pop {r0}                                                  \n"
+                "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
+                " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
+                "     pop {r0}                                                  \n"
+                "     svc %0                                                    \n"
+                "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
+                "     svc %1                                                    \n"
+                "     bx lr                                                     \n"
+                "                                                               \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pcTimerGetNameImpl                        \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_pcTimerGetName_Unpriv                         \n"
+                " MPU_pcTimerGetName_Priv:                              \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_pcTimerGetNameImpl                          \n"
+                " MPU_pcTimerGetName_Unpriv:                            \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pcTimerGetNameImpl                         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
+                                      const BaseType_t uxAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
+                                      const BaseType_t uxAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTimerSetReloadModeImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTimerSetReloadMode_Unpriv                    \n"
+                " MPU_vTimerSetReloadMode_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTimerSetReloadModeImpl                     \n"
+                " MPU_vTimerSetReloadMode_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTimerSetReloadModeImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetReloadModeImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerGetReloadMode_Unpriv                    \n"
+                " MPU_xTimerGetReloadMode_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerGetReloadModeImpl                     \n"
+                " MPU_xTimerGetReloadMode_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetReloadModeImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTimerGetReloadModeImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTimerGetReloadMode_Unpriv                   \n"
+                " MPU_uxTimerGetReloadMode_Priv:                        \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTimerGetReloadModeImpl                    \n"
+                " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTimerGetReloadModeImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetPeriodImpl                       \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerGetPeriod_Unpriv                        \n"
+                " MPU_xTimerGetPeriod_Priv:                             \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerGetPeriodImpl                         \n"
+                " MPU_xTimerGetPeriod_Unpriv:                           \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetPeriodImpl                        \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetExpiryTimeImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerGetExpiryTime_Unpriv                    \n"
+                " MPU_xTimerGetExpiryTime_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerGetExpiryTimeImpl                     \n"
+                " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetExpiryTimeImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         const BaseType_t xClearOnExit,
+                                         const BaseType_t xWaitForAllBits,
+                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         const BaseType_t xClearOnExit,
+                                         const BaseType_t xWaitForAllBits,
                                          TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueTakeMutexRecursiveImpl              \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueTakeMutexRecursive_Unpriv               \n"
-        " MPU_xQueueTakeMutexRecursive_Priv:                    \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueTakeMutexRecursiveImpl                \n"
-        " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueTakeMutexRecursiveImpl               \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupWaitBitsImpl                   \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
+            " MPU_xEventGroupWaitBits_Priv:                         \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xEventGroupWaitBitsImpl                     \n"
+            " MPU_xEventGroupWaitBits_Unpriv:                       \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupWaitBitsImpl                    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                          const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueGiveMutexRecursiveImpl              \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueGiveMutexRecursive_Unpriv               \n"
-        " MPU_xQueueGiveMutexRecursive_Priv:                    \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueGiveMutexRecursiveImpl                \n"
-        " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueGiveMutexRecursiveImpl               \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                          const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupClearBitsImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xEventGroupClearBits_Unpriv                   \n"
+            " MPU_xEventGroupClearBits_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xEventGroupClearBitsImpl                    \n"
+            " MPU_xEventGroupClearBits_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupClearBitsImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_QUEUE_SETS == 1 )
+    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                        const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
-                                                const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
-                                                const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueSelectFromSetImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueSelectFromSet_Unpriv                    \n"
-        " MPU_xQueueSelectFromSet_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueSelectFromSetImpl                     \n"
-        " MPU_xQueueSelectFromSet_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueSelectFromSetImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                        const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupSetBitsImpl                    \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xEventGroupSetBits_Unpriv                     \n"
+            " MPU_xEventGroupSetBits_Priv:                          \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xEventGroupSetBitsImpl                      \n"
+            " MPU_xEventGroupSetBits_Unpriv:                        \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupSetBitsImpl                     \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_QUEUE_SETS == 1 )
-
-BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
-                               QueueSetHandle_t xQueueSet ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
-                               QueueSetHandle_t xQueueSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueAddToSetImpl                        \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueAddToSet_Unpriv                         \n"
-        " MPU_xQueueAddToSet_Priv:                              \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueAddToSetImpl                          \n"
-        " MPU_xQueueAddToSet_Unpriv:                            \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueAddToSetImpl                         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_QUEUE_SETS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
-                              const char * pcName ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
-                              const char * pcName ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vQueueAddToRegistryImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vQueueAddToRegistry_Unpriv                    \n"
-        " MPU_vQueueAddToRegistry_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vQueueAddToRegistryImpl                     \n"
-        " MPU_vQueueAddToRegistry_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vQueueAddToRegistryImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vQueueUnregisterQueueImpl                 \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vQueueUnregisterQueue_Unpriv                  \n"
-        " MPU_vQueueUnregisterQueue_Priv:                       \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vQueueUnregisterQueueImpl                   \n"
-        " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vQueueUnregisterQueueImpl                  \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pcQueueGetNameImpl                        \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_pcQueueGetName_Unpriv                         \n"
-        " MPU_pcQueueGetName_Priv:                              \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_pcQueueGetNameImpl                          \n"
-        " MPU_pcQueueGetName_Unpriv:                            \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pcQueueGetNameImpl                         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pvTimerGetTimerIDImpl                     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_pvTimerGetTimerID_Unpriv                      \n"
-        " MPU_pvTimerGetTimerID_Priv:                           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_pvTimerGetTimerIDImpl                       \n"
-        " MPU_pvTimerGetTimerID_Unpriv:                         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pvTimerGetTimerIDImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
-                           void * pvNewID ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
-                           void * pvNewID ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTimerSetTimerIDImpl                      \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTimerSetTimerID_Unpriv                       \n"
-        " MPU_vTimerSetTimerID_Priv:                            \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTimerSetTimerIDImpl                        \n"
-        " MPU_vTimerSetTimerID_Unpriv:                          \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTimerSetTimerIDImpl                       \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerIsTimerActiveImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTimerIsTimerActive_Unpriv                    \n"
-        " MPU_xTimerIsTimerActive_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerIsTimerActiveImpl                     \n"
-        " MPU_xTimerIsTimerActive_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerIsTimerActiveImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetTimerDaemonTaskHandleImpl        \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv         \n"
-        " MPU_xTimerGetTimerDaemonTaskHandle_Priv:              \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerGetTimerDaemonTaskHandleImpl          \n"
-        " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetTimerDaemonTaskHandleImpl         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                             const BaseType_t xCommandID,
-                                             const TickType_t xOptionalValue,
-                                             BaseType_t * const pxHigherPriorityTaskWoken,
-                                             const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                             const BaseType_t xCommandID,
-                                             const TickType_t xOptionalValue,
-                                             BaseType_t * const pxHigherPriorityTaskWoken,
-                                             const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                               \n"
-        " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
-        "                                                               \n"
-        " push {r0}                                                     \n"
-        " mrs r0, control                                               \n"
-        " tst r0, #1                                                    \n"
-        " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
-        " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
-        "     pop {r0}                                                  \n"
-        "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
-        " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
-        "     pop {r0}                                                  \n"
-        "     svc %0                                                    \n"
-        "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
-        "     svc %1                                                    \n"
-        "     bx lr                                                     \n"
-        "                                                               \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pcTimerGetNameImpl                        \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_pcTimerGetName_Unpriv                         \n"
-        " MPU_pcTimerGetName_Priv:                              \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_pcTimerGetNameImpl                          \n"
-        " MPU_pcTimerGetName_Unpriv:                            \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pcTimerGetNameImpl                         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                              const BaseType_t uxAutoReload ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                              const BaseType_t uxAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTimerSetReloadModeImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTimerSetReloadMode_Unpriv                    \n"
-        " MPU_vTimerSetReloadMode_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTimerSetReloadModeImpl                     \n"
-        " MPU_vTimerSetReloadMode_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTimerSetReloadModeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetReloadModeImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTimerGetReloadMode_Unpriv                    \n"
-        " MPU_xTimerGetReloadMode_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerGetReloadModeImpl                     \n"
-        " MPU_xTimerGetReloadMode_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetReloadModeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTimerGetReloadModeImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTimerGetReloadMode_Unpriv                   \n"
-        " MPU_uxTimerGetReloadMode_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTimerGetReloadModeImpl                    \n"
-        " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTimerGetReloadModeImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetPeriodImpl                       \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTimerGetPeriod_Unpriv                        \n"
-        " MPU_xTimerGetPeriod_Priv:                             \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerGetPeriodImpl                         \n"
-        " MPU_xTimerGetPeriod_Unpriv:                           \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetPeriodImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetExpiryTimeImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTimerGetExpiryTime_Unpriv                    \n"
-        " MPU_xTimerGetExpiryTime_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerGetExpiryTimeImpl                     \n"
-        " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetExpiryTimeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                     const EventBits_t uxBitsToSet,
                                      const EventBits_t uxBitsToWaitFor,
-                                     const BaseType_t xClearOnExit,
-                                     const BaseType_t xWaitForAllBits,
-                                     TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                     const EventBits_t uxBitsToSet,
                                      const EventBits_t uxBitsToWaitFor,
-                                     const BaseType_t xClearOnExit,
-                                     const BaseType_t xWaitForAllBits,
                                      TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupWaitBitsImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
-        " MPU_xEventGroupWaitBits_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xEventGroupWaitBitsImpl                     \n"
-        " MPU_xEventGroupWaitBits_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupWaitBitsImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupSyncImpl                       \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xEventGroupSync_Unpriv                        \n"
+            " MPU_xEventGroupSync_Priv:                             \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xEventGroupSyncImpl                         \n"
+            " MPU_xEventGroupSync_Unpriv:                           \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupSyncImpl                        \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                      const EventBits_t uxBitsToClear ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                      const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupClearBitsImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xEventGroupClearBits_Unpriv                   \n"
-        " MPU_xEventGroupClearBits_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xEventGroupClearBitsImpl                    \n"
-        " MPU_xEventGroupClearBits_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupClearBitsImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxEventGroupGetNumberImpl                 \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxEventGroupGetNumber_Unpriv                  \n"
+                " MPU_uxEventGroupGetNumber_Priv:                       \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxEventGroupGetNumberImpl                   \n"
+                " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxEventGroupGetNumberImpl                  \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
 /*-----------------------------------------------------------*/
 
-EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                    const EventBits_t uxBitsToSet ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                    const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupSetBitsImpl                    \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xEventGroupSetBits_Unpriv                     \n"
-        " MPU_xEventGroupSetBits_Priv:                          \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xEventGroupSetBitsImpl                      \n"
-        " MPU_xEventGroupSetBits_Unpriv:                        \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupSetBitsImpl                     \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vEventGroupSetNumber( void * xEventGroup,
+                                       UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vEventGroupSetNumber( void * xEventGroup,
+                                       UBaseType_t uxEventGroupNumber ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vEventGroupSetNumberImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vEventGroupSetNumber_Unpriv                   \n"
+                " MPU_vEventGroupSetNumber_Priv:                        \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vEventGroupSetNumberImpl                    \n"
+                " MPU_vEventGroupSetNumber_Unpriv:                      \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vEventGroupSetNumberImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
 /*-----------------------------------------------------------*/
 
-EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                 const EventBits_t uxBitsToSet,
-                                 const EventBits_t uxBitsToWaitFor,
-                                 TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                  const void * pvTxData,
+                                  size_t xDataLengthBytes,
+                                  TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                 const EventBits_t uxBitsToSet,
-                                 const EventBits_t uxBitsToWaitFor,
-                                 TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupSyncImpl                       \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xEventGroupSync_Unpriv                        \n"
-        " MPU_xEventGroupSync_Priv:                             \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xEventGroupSyncImpl                         \n"
-        " MPU_xEventGroupSync_Unpriv:                           \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupSyncImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                  const void * pvTxData,
+                                  size_t xDataLengthBytes,
+                                  TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferSendImpl                     \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferSend_Unpriv                      \n"
+            " MPU_xStreamBufferSend_Priv:                           \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferSendImpl                       \n"
+            " MPU_xStreamBufferSend_Unpriv:                         \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferSendImpl                      \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                     void * pvRxData,
+                                     size_t xBufferLengthBytes,
+                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxEventGroupGetNumberImpl                 \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxEventGroupGetNumber_Unpriv                  \n"
-        " MPU_uxEventGroupGetNumber_Priv:                       \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxEventGroupGetNumberImpl                   \n"
-        " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxEventGroupGetNumberImpl                  \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                     void * pvRxData,
+                                     size_t xBufferLengthBytes,
+                                     TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferReceiveImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferReceive_Unpriv                   \n"
+            " MPU_xStreamBufferReceive_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferReceiveImpl                    \n"
+            " MPU_xStreamBufferReceive_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferReceiveImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vEventGroupSetNumber( void * xEventGroup,
-                               UBaseType_t uxEventGroupNumber ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vEventGroupSetNumber( void * xEventGroup,
-                               UBaseType_t uxEventGroupNumber ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vEventGroupSetNumberImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vEventGroupSetNumber_Unpriv                   \n"
-        " MPU_vEventGroupSetNumber_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vEventGroupSetNumberImpl                    \n"
-        " MPU_vEventGroupSetNumber_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vEventGroupSetNumberImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferIsFullImpl                   \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
+            " MPU_xStreamBufferIsFull_Priv:                         \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferIsFullImpl                     \n"
+            " MPU_xStreamBufferIsFull_Unpriv:                       \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferIsFullImpl                    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                              const void * pvTxData,
-                              size_t xDataLengthBytes,
-                              TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                              const void * pvTxData,
-                              size_t xDataLengthBytes,
-                              TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferSendImpl                     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferSend_Unpriv                      \n"
-        " MPU_xStreamBufferSend_Priv:                           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferSendImpl                       \n"
-        " MPU_xStreamBufferSend_Unpriv:                         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferSendImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
+            " MPU_xStreamBufferIsEmpty_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferIsEmptyImpl                    \n"
+            " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferIsEmptyImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                 void * pvRxData,
-                                 size_t xBufferLengthBytes,
-                                 TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                 void * pvRxData,
-                                 size_t xBufferLengthBytes,
-                                 TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferReceiveImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferReceive_Unpriv                   \n"
-        " MPU_xStreamBufferReceive_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferReceiveImpl                    \n"
-        " MPU_xStreamBufferReceive_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferReceiveImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
+            " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
+            " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferSpacesAvailableImpl           \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferIsFullImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
-        " MPU_xStreamBufferIsFull_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferIsFullImpl                     \n"
-        " MPU_xStreamBufferIsFull_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferIsFullImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
+            " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferBytesAvailableImpl             \n"
+            " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferBytesAvailableImpl            \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                 size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
-        " MPU_xStreamBufferIsEmpty_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferIsEmptyImpl                    \n"
-        " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferIsEmptyImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                 size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
+            " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
+            " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferSetTriggerLevelImpl           \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
-        " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
-        " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferSpacesAvailableImpl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
-size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
-        " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferBytesAvailableImpl             \n"
-        " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferBytesAvailableImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                             size_t xTriggerLevel ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                             size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
-        " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
-        " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferSetTriggerLevelImpl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
-size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
-        " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
-        " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferNextMessageLengthBytesImpl    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
+            " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
+            " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferNextMessageLengthBytesImpl    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
diff --git a/portable/GCC/ARM_CM55/non_secure/port.c b/portable/GCC/ARM_CM55/non_secure/port.c
index 80410e82e..c940c304b 100644
--- a/portable/GCC/ARM_CM55/non_secure/port.c
+++ b/portable/GCC/ARM_CM55/non_secure/port.c
@@ -110,8 +110,8 @@
 /**
  * @brief Constants used during system call enter and exit.
  */
-#define portPSR_STACK_PADDING_MASK                ( 1UL << 9UL )
-#define portEXC_RETURN_STACK_FRAME_TYPE_MASK      ( 1UL << 4UL )
+#define portPSR_STACK_PADDING_MASK              ( 1UL << 9UL )
+#define portEXC_RETURN_STACK_FRAME_TYPE_MASK    ( 1UL << 4UL )
 /*-----------------------------------------------------------*/
 
 /**
@@ -133,81 +133,81 @@
 /**
  * @brief Offsets in the stack to the parameters when inside the SVC handler.
  */
-#define portOFFSET_TO_LR                    ( 5 )
-#define portOFFSET_TO_PC                    ( 6 )
-#define portOFFSET_TO_PSR                   ( 7 )
+#define portOFFSET_TO_LR     ( 5 )
+#define portOFFSET_TO_PC     ( 6 )
+#define portOFFSET_TO_PSR    ( 7 )
 /*-----------------------------------------------------------*/
 
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                      ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                      ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                       ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                      ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                      ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                     ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                     ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK  ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK               ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK               ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK               ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK               ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK               ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK               ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK               ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK               ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0              ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1              ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2              ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3              ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4              ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5              ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6              ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7              ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE            ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT      ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                      ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE             ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -216,11 +216,11 @@
 
 /* Extract last address of the MPU region as encoded in the
  * RLAR (Region Limit Address Register) value. */
-#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar )  \
+#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar ) \
     ( ( ( rlar ) & portMPU_RLAR_ADDRESS_MASK ) | ~portMPU_RLAR_ADDRESS_MASK )
 
 /* Does addr lies within [start, end] address range? */
-#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end )    \
+#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \
     ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) )
 
 /* Is the access request satisfied by the available permissions? */
@@ -422,54 +422,57 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the system call stack so that upon returning from
-     * SVC, the system call stack is used.
-     *
-     * It is used for the system calls with up to 4 parameters.
-     *
-     * @param pulTaskStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the system call stack so that upon returning from
+ * SVC, the system call stack is used.
+ *
+ * It is used for the system calls with up to 4 parameters.
+ *
+ * @param pulTaskStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallEnter( uint32_t * pulTaskStack,
+                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the system call stack so that upon returning from
-     * SVC, the system call stack is used.
-     *
-     * It is used for the system calls with 5 parameters.
-     *
-     * @param pulTaskStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the system call stack so that upon returning from
+ * SVC, the system call stack is used.
+ *
+ * It is used for the system calls with 5 parameters.
+ *
+ * @param pulTaskStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallEnter_1( uint32_t * pulTaskStack,
+                             uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the task stack so that upon returning from
-     * SVC, the task stack is used again.
-     *
-     * @param pulSystemCallStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the task stack so that upon returning from
+ * SVC, the task stack is used again.
+ *
+ * @param pulSystemCallStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallExit( uint32_t * pulSystemCallStack,
+                          uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Checks whether or not the calling task is privileged.
-     *
-     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
-     */
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
     BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
 
 #endif /* configENABLE_MPU == 1 */
@@ -1086,18 +1089,18 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             vRestoreContextOfFirstTask();
             break;
 
-        #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
-            case portSVC_RAISE_PRIVILEGE:
+            #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+                case portSVC_RAISE_PRIVILEGE:
 
-                /* Only raise the privilege, if the svc was raised from any of
-                 * the system calls. */
-                if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
-                    ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
-                {
-                    vRaisePrivilege();
-                }
-                break;
-        #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+                    /* Only raise the privilege, if the svc was raised from any of
+                     * the system calls. */
+                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+                    {
+                        vRaisePrivilege();
+                    }
+                    break;
+            #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
         default:
             /* Incorrect SVC call. */
@@ -1108,513 +1111,526 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulSystemCallStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallEnter( uint32_t * pulTaskStack,
+                           uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulSystemCallStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        /* This is not NULL only for the duration of the system call. */
-        configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+        #if defined( __ARMCC_VERSION )
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+
+            /* This is not NULL only for the duration of the system call. */
+            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the system call stack for the stack frame. */
+            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulSystemCallStack[ i ] = pulTaskStack[ i ];
+            }
+
+            /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
+             * restore it when we exit from the system call. */
+            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* Use the pulSystemCallStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+
+            /* Remember the location where we should copy the stack frame when we exit from
+             * the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+
+            /* Record if the hardware used padding to force the stack pointer
+             * to be double word aligned. */
+            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
+            {
+                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
             }
+
+            /* We ensure in pxPortInitialiseStack that the system call stack is
+             * double word aligned and therefore, there is no need of padding.
+             * Clear the bit[9] of stacked xPSR. */
+            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
+
+            /* Raise the privilege for the duration of the system call. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " bics r0, r1         \n" /* Clear nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the system call stack for the stack frame. */
-        pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulSystemCallStack[ i ] = pulTaskStack[ i ];
-        }
-
-        /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
-         * restore it when we exit from the system call. */
-        pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-        __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* Use the pulSystemCallStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-
-        /* Remember the location where we should copy the stack frame when we exit from
-         * the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-        /* Record if the hardware used padding to force the stack pointer
-         * to be double word aligned. */
-        if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-        {
-            pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-        }
-        else
-        {
-            pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-        }
-
-        /* We ensure in pxPortInitialiseStack that the system call stack is
-         * double word aligned and therefore, there is no need of padding.
-         * Clear the bit[9] of stacked xPSR. */
-        pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-        /* Raise the privilege for the duration of the system call. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " bics r0, r1         \n" /* Clear nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulSystemCallStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallEnter_1( uint32_t * pulTaskStack,
+                             uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulSystemCallStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        /* This is not NULL only for the duration of the system call. */
-        configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+        #if defined( __ARMCC_VERSION )
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+
+            /* This is not NULL only for the duration of the system call. */
+            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the system call stack for the stack frame and
+             * the parameter passed on the stack. We only need to copy one
+             * parameter but we still reserve 2 spaces to keep the stack
+             * double word aligned. */
+            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulSystemCallStack[ i ] = pulTaskStack[ i ];
+            }
+
+            /* Copy the parameter which is passed the stack. */
+            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
+            {
+                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
+
+                /* Record if the hardware used padding to force the stack pointer
+                 * to be double word aligned. */
+                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
+
+                /* Record if the hardware used padding to force the stack pointer
+                 * to be double word aligned. */
+                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
             }
+
+            /* Store the value of the LR and PSPLIM registers before the SVC was raised.
+             * We need to restore it when we exit from the system call. */
+            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* Use the pulSystemCallStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+
+            /* Remember the location where we should copy the stack frame when we exit from
+             * the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+
+            /* We ensure in pxPortInitialiseStack that the system call stack is
+             * double word aligned and therefore, there is no need of padding.
+             * Clear the bit[9] of stacked xPSR. */
+            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
+
+            /* Raise the privilege for the duration of the system call. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " bics r0, r1         \n" /* Clear nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the system call stack for the stack frame and
-         * the parameter passed on the stack. We only need to copy one
-         * parameter but we still reserve 2 spaces to keep the stack
-         * double word aligned. */
-        pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulSystemCallStack[ i ] = pulTaskStack[ i ];
-        }
-
-        /* Copy the parameter which is passed the stack. */
-        if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-        {
-            pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
-            /* Record if the hardware used padding to force the stack pointer
-             * to be double word aligned. */
-            pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-        }
-        else
-        {
-            pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
-            /* Record if the hardware used padding to force the stack pointer
-             * to be double word aligned. */
-            pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-        }
-
-        /* Store the value of the LR and PSPLIM registers before the SVC was raised.
-         * We need to restore it when we exit from the system call. */
-        pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-        __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* Use the pulSystemCallStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-
-        /* Remember the location where we should copy the stack frame when we exit from
-         * the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-        /* We ensure in pxPortInitialiseStack that the system call stack is
-         * double word aligned and therefore, there is no need of padding.
-         * Clear the bit[9] of stacked xPSR. */
-        pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-        /* Raise the privilege for the duration of the system call. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " bics r0, r1         \n" /* Clear nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulTaskStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallExit( uint32_t * pulSystemCallStack,
+                          uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulTaskStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+        #if defined( __ARMCC_VERSION )
+
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the task stack for the stack frame. */
+            pulTaskStack = pulTaskStack - ulStackFrameSize;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulTaskStack[ i ] = pulSystemCallStack[ i ];
+            }
+
+            /* Use the pulTaskStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
+
+            /* Restore the LR and PSPLIM to what they were at the time of
+             * system call entry. */
+            pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* If the hardware used padding to force the stack pointer
+             * to be double word aligned, set the stacked xPSR bit[9],
+             * otherwise clear it. */
+            if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG )
+            {
+                pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
             }
+
+            /* This is not NULL only for the duration of the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
+
+            /* Drop the privilege before returning to the thread mode. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " orrs r0, r1         \n" /* Set nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the task stack for the stack frame. */
-        pulTaskStack = pulTaskStack - ulStackFrameSize;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulTaskStack[ i ] = pulSystemCallStack[ i ];
-        }
-
-        /* Use the pulTaskStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
-
-        /* Restore the LR and PSPLIM to what they were at the time of
-         * system call entry. */
-        pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* If the hardware used padding to force the stack pointer
-         * to be double word aligned, set the stacked xPSR bit[9],
-         * otherwise clear it. */
-        if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG )
-        {
-            pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK;
-        }
-        else
-        {
-            pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-        }
-
-        /* This is not NULL only for the duration of the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
-
-        /* Drop the privilege before returning to the thread mode. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " orrs r0, r1         \n" /* Set nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */
-{
-    BaseType_t xTaskIsPrivileged = pdFALSE;
-    const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
-
-    if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+    BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */
     {
-        xTaskIsPrivileged = pdTRUE;
-    }
+        BaseType_t xTaskIsPrivileged = pdFALSE;
+        const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
 
-    return xTaskIsPrivileged;
-}
+        if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+        {
+            xTaskIsPrivileged = pdTRUE;
+        }
+
+        return xTaskIsPrivileged;
+    }
 
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
-#if( configENABLE_MPU == 1 )
+#if ( configENABLE_MPU == 1 )
 
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     StackType_t * pxEndOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters,
-                                     BaseType_t xRunPrivileged,
-                                     xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
-{
-    uint32_t ulIndex = 0;
-
-    xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
-    ulIndex++;
-
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
-    ulIndex++;
-
-    #if ( configENABLE_TRUSTZONE == 1 )
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters,
+                                         BaseType_t xRunPrivileged,
+                                         xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
     {
-        xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT;  /* xSecureContext. */
+        uint32_t ulIndex = 0;
+
+        xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
         ulIndex++;
-    }
-    #endif /* configENABLE_TRUSTZONE */
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
-    ulIndex++;
-    if( xRunPrivileged == pdTRUE )
-    {
-        xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */
         ulIndex++;
-    }
-    else
-    {
-        xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */
         ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
+        ulIndex++;
+
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters;            /* r0. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x01010101;                           /* r1. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x02020202;                           /* r2. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x03030303;                           /* r3. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x12121212;                           /* r12. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode;                  /* PC. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR;                     /* xPSR. */
+        ulIndex++;
+
+        #if ( configENABLE_TRUSTZONE == 1 )
+        {
+            xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT; /* xSecureContext. */
+            ulIndex++;
+        }
+        #endif /* configENABLE_TRUSTZONE */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
+        ulIndex++;
+
+        if( xRunPrivileged == pdTRUE )
+        {
+            xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
+            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+            ulIndex++;
+        }
+        else
+        {
+            xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
+            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+            ulIndex++;
+        }
+
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
+        ulIndex++;
+
+        #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+        {
+            /* Ensure that the system call stack is double word aligned. */
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] );
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) &
+                                                                                     ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
+
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] );
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) +
+                                                                                            ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) &
+                                                                                          ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
+
+            /* This is not NULL only for the duration of a system call. */
+            xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL;
+        }
+        #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
+
+        return &( xMPUSettings->ulContext[ ulIndex ] );
     }
-    xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
-    ulIndex++;
-
-    #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
-    {
-        /* Ensure that the system call stack is double word aligned. */
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] );
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) &
-                                                                                 ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
-
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] );
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) +
-                                                                                        ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) &
-                                                                                      ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
-
-        /* This is not NULL only for the duration of a system call. */
-        xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL;
-    }
-    #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
-
-    return &( xMPUSettings->ulContext[ ulIndex ] );
-}
 
 #else /* configENABLE_MPU */
 
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     StackType_t * pxEndOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters ) /* PRIVILEGED_FUNCTION */
-{
-    /* Simulate the stack frame as it would be created by a context switch
-     * interrupt. */
-    #if ( portPRELOAD_REGISTERS == 0 )
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters ) /* PRIVILEGED_FUNCTION */
     {
-        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-        pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
-        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-        pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
-        *pxTopOfStack = portINITIAL_EXC_RETURN;
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
-
-        #if ( configENABLE_TRUSTZONE == 1 )
+        /* Simulate the stack frame as it would be created by a context switch
+         * interrupt. */
+        #if ( portPRELOAD_REGISTERS == 0 )
         {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
-        }
-        #endif /* configENABLE_TRUSTZONE */
-    }
-    #else /* portPRELOAD_REGISTERS */
-    {
-        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
-        pxTopOfStack--;
-        *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
+            pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
+            *pxTopOfStack = portINITIAL_EXC_RETURN;
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+            #if ( configENABLE_TRUSTZONE == 1 )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+            }
+            #endif /* configENABLE_TRUSTZONE */
+        }
+        #else /* portPRELOAD_REGISTERS */
         {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
-        }
-        #endif /* configENABLE_TRUSTZONE */
-    }
-    #endif /* portPRELOAD_REGISTERS */
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
+            pxTopOfStack--;
+            *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack;            /* Slot used to hold this task's PSPLIM value. */
 
-    return pxTopOfStack;
-}
+            #if ( configENABLE_TRUSTZONE == 1 )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+            }
+            #endif /* configENABLE_TRUSTZONE */
+        }
+        #endif /* portPRELOAD_REGISTERS */
+
+        return pxTopOfStack;
+    }
 
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM55/non_secure/portasm.c b/portable/GCC/ARM_CM55/non_secure/portasm.c
index f7ec7d9c0..ba8f6c62d 100644
--- a/portable/GCC/ARM_CM55/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM55/non_secure/portasm.c
@@ -42,116 +42,116 @@
 
 #if ( configENABLE_MPU == 1 )
 
-void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        " .syntax unified                                 \n"
-        "                                                 \n"
-        " program_mpu_first_task:                         \n"
-        "    ldr r3, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB. */
-        "                                                 \n"
-        "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-        "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
-        "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
-        "    str r2, [r1]                                 \n" /* Disable MPU. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
-        "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-        "    ldr r2, xMAIR0Const2                         \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-        "    str r1, [r2]                                 \n" /* Program MAIR0. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-        "    ldr r1, xRNRConst2                           \n" /* r1 = 0xe000ed98 [Location of RNR]. */
-        "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "                                                 \n"
-        "    movs r3, #4                                  \n" /* r3 = 4. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 4. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-        "                                                 \n"
-        #if ( configTOTAL_MPU_REGIONS == 16 )
-        "    movs r3, #8                                  \n" /* r3 = 8. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 8. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-        "    movs r3, #12                                 \n" /* r3 = 12. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 12. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-        #endif /* configTOTAL_MPU_REGIONS == 16 */
-        "                                                 \n"
-        "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
-        "    orr r2, #1                                   \n" /* r2 = r1 | 1 i.e. Set the bit 0 in r2. */
-        "    str r2, [r1]                                 \n" /* Enable MPU. */
-        "    dsb                                          \n" /* Force memory writes before continuing. */
-        "                                                 \n"
-        " restore_context_first_task:                     \n"
-        "    ldr r3, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r1, [r3]                                 \n" /* r1 = pxCurrentTCB.*/
-        "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
-        "                                                 \n"
-        " restore_special_regs_first_task:                \n"
-        "    ldmdb r2!, {r0, r3-r5, lr}                   \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
-        "    msr psp, r3                                  \n"
-        "    msr psplim, r4                               \n"
-        "    msr control, r5                              \n"
-        "    ldr r4, xSecureContextConst2                 \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-        "    str r0, [r4]                                 \n" /* Restore xSecureContext. */
-        "                                                 \n"
-        " restore_general_regs_first_task:                \n"
-        "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
-        "    stmia r3!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
-        "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 restored. */
-        "                                                 \n"
-        " restore_context_done_first_task:                \n"
-        "    str r2, [r1]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
-        "    mov r0, #0                                   \n"
-        "    msr basepri, r0                              \n" /* Ensure that interrupts are enabled when the first task starts. */
-        "    bx lr                                        \n"
-        "                                                 \n"
-        " .align 4                                        \n"
-        " pxCurrentTCBConst2: .word pxCurrentTCB          \n"
-        " xSecureContextConst2: .word xSecureContext      \n"
-        " xMPUCTRLConst2: .word 0xe000ed94                \n"
-        " xMAIR0Const2: .word 0xe000edc0                  \n"
-        " xRNRConst2: .word 0xe000ed98                    \n"
-        " xRBARConst2: .word 0xe000ed9c                   \n"
-    );
-}
+    void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                 \n"
+            "                                                 \n"
+            " program_mpu_first_task:                         \n"
+            "    ldr r3, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB. */
+            "                                                 \n"
+            "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
+            "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
+            "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
+            "    str r2, [r1]                                 \n" /* Disable MPU. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
+            "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
+            "    ldr r2, xMAIR0Const2                         \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    str r1, [r2]                                 \n" /* Program MAIR0. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
+            "    ldr r1, xRNRConst2                           \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "                                                 \n"
+            "    movs r3, #4                                  \n" /* r3 = 4. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 4. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "                                                 \n"
+            #if ( configTOTAL_MPU_REGIONS == 16 )
+                "    movs r3, #8                                  \n" /* r3 = 8. */
+                "    str r3, [r1]                                 \n" /* Program RNR = 8. */
+                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
+                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+                "    movs r3, #12                                 \n" /* r3 = 12. */
+                "    str r3, [r1]                                 \n" /* Program RNR = 12. */
+                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
+                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            #endif /* configTOTAL_MPU_REGIONS == 16 */
+            "                                                 \n"
+            "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
+            "    orr r2, #1                                   \n" /* r2 = r1 | 1 i.e. Set the bit 0 in r2. */
+            "    str r2, [r1]                                 \n" /* Enable MPU. */
+            "    dsb                                          \n" /* Force memory writes before continuing. */
+            "                                                 \n"
+            " restore_context_first_task:                     \n"
+            "    ldr r3, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r1, [r3]                                 \n" /* r1 = pxCurrentTCB.*/
+            "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
+            "                                                 \n"
+            " restore_special_regs_first_task:                \n"
+            "    ldmdb r2!, {r0, r3-r5, lr}                   \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
+            "    msr psp, r3                                  \n"
+            "    msr psplim, r4                               \n"
+            "    msr control, r5                              \n"
+            "    ldr r4, xSecureContextConst2                 \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "    str r0, [r4]                                 \n" /* Restore xSecureContext. */
+            "                                                 \n"
+            " restore_general_regs_first_task:                \n"
+            "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
+            "    stmia r3!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
+            "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 restored. */
+            "                                                 \n"
+            " restore_context_done_first_task:                \n"
+            "    str r2, [r1]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
+            "    mov r0, #0                                   \n"
+            "    msr basepri, r0                              \n" /* Ensure that interrupts are enabled when the first task starts. */
+            "    bx lr                                        \n"
+            "                                                 \n"
+            " .align 4                                        \n"
+            " pxCurrentTCBConst2: .word pxCurrentTCB          \n"
+            " xSecureContextConst2: .word xSecureContext      \n"
+            " xMPUCTRLConst2: .word 0xe000ed94                \n"
+            " xMAIR0Const2: .word 0xe000edc0                  \n"
+            " xRNRConst2: .word 0xe000ed98                    \n"
+            " xRBARConst2: .word 0xe000ed9c                   \n"
+        );
+    }
 
 #else /* configENABLE_MPU */
 
-void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "   .syntax unified                                 \n"
-        "                                                   \n"
-        "   ldr  r2, pxCurrentTCBConst2                     \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr  r3, [r2]                                   \n" /* Read pxCurrentTCB. */
-        "   ldr  r0, [r3]                                   \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
-        "                                                   \n"
-        "   ldm  r0!, {r1-r3}                               \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
-        "   ldr  r4, xSecureContextConst2                   \n"
-        "   str  r1, [r4]                                   \n" /* Set xSecureContext to this task's value for the same. */
-        "   msr  psplim, r2                                 \n" /* Set this task's PSPLIM value. */
-        "   movs r1, #2                                     \n" /* r1 = 2. */
-        "   msr  CONTROL, r1                                \n" /* Switch to use PSP in the thread mode. */
-        "   adds r0, #32                                    \n" /* Discard everything up to r0. */
-        "   msr  psp, r0                                    \n" /* This is now the new top of stack to use in the task. */
-        "   isb                                             \n"
-        "   mov  r0, #0                                     \n"
-        "   msr  basepri, r0                                \n" /* Ensure that interrupts are enabled when the first task starts. */
-        "   bx   r3                                         \n" /* Finally, branch to EXC_RETURN. */
-        "   .align 4                                        \n"
-        "pxCurrentTCBConst2: .word pxCurrentTCB             \n"
-        "xSecureContextConst2: .word xSecureContext         \n"
-    );
-}
+    void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            "   .syntax unified                                 \n"
+            "                                                   \n"
+            "   ldr  r2, pxCurrentTCBConst2                     \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr  r3, [r2]                                   \n" /* Read pxCurrentTCB. */
+            "   ldr  r0, [r3]                                   \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+            "                                                   \n"
+            "   ldm  r0!, {r1-r3}                               \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
+            "   ldr  r4, xSecureContextConst2                   \n"
+            "   str  r1, [r4]                                   \n" /* Set xSecureContext to this task's value for the same. */
+            "   msr  psplim, r2                                 \n" /* Set this task's PSPLIM value. */
+            "   movs r1, #2                                     \n" /* r1 = 2. */
+            "   msr  CONTROL, r1                                \n" /* Switch to use PSP in the thread mode. */
+            "   adds r0, #32                                    \n" /* Discard everything up to r0. */
+            "   msr  psp, r0                                    \n" /* This is now the new top of stack to use in the task. */
+            "   isb                                             \n"
+            "   mov  r0, #0                                     \n"
+            "   msr  basepri, r0                                \n" /* Ensure that interrupts are enabled when the first task starts. */
+            "   bx   r3                                         \n" /* Finally, branch to EXC_RETURN. */
+            "   .align 4                                        \n"
+            "pxCurrentTCBConst2: .word pxCurrentTCB             \n"
+            "xSecureContextConst2: .word xSecureContext         \n"
+        );
+    }
 
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
@@ -162,12 +162,12 @@ BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs r0, control                                 \n"/* r0 = CONTROL. */
-        "   tst r0, #1                                      \n"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+        "   mrs r0, control                                 \n" /* r0 = CONTROL. */
+        "   tst r0, #1                                      \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
         "   ite ne                                          \n"
-        "   movne r0, #0                                    \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
-        "   moveq r0, #1                                    \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
-        "   bx lr                                           \n"/* Return. */
+        "   movne r0, #0                                    \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+        "   moveq r0, #1                                    \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+        "   bx lr                                           \n" /* Return. */
         "                                                   \n"
         "   .align 4                                        \n"
         ::: "r0", "memory"
@@ -181,10 +181,10 @@ void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs r0, control                                 \n"/* Read the CONTROL register. */
-        "   bic r0, #1                                      \n"/* Clear the bit 0. */
-        "   msr control, r0                                 \n"/* Write back the new CONTROL value. */
-        "   bx lr                                           \n"/* Return to the caller. */
+        "   mrs r0, control                                 \n" /* Read the CONTROL register. */
+        "   bic r0, #1                                      \n" /* Clear the bit 0. */
+        "   msr control, r0                                 \n" /* Write back the new CONTROL value. */
+        "   bx lr                                           \n" /* Return to the caller. */
         ::: "r0", "memory"
     );
 }
@@ -196,10 +196,10 @@ void vResetPrivilege( void ) /* __attribute__ (( naked )) */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs r0, control                                 \n"/* r0 = CONTROL. */
-        "   orr r0, #1                                      \n"/* r0 = r0 | 1. */
-        "   msr control, r0                                 \n"/* CONTROL = r0. */
-        "   bx lr                                           \n"/* Return to the caller. */
+        "   mrs r0, control                                 \n" /* r0 = CONTROL. */
+        "   orr r0, #1                                      \n" /* r0 = r0 | 1. */
+        "   msr control, r0                                 \n" /* CONTROL = r0. */
+        "   bx lr                                           \n" /* Return to the caller. */
         ::: "r0", "memory"
     );
 }
@@ -211,15 +211,15 @@ void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   ldr r0, xVTORConst                              \n"/* Use the NVIC offset register to locate the stack. */
-        "   ldr r0, [r0]                                    \n"/* Read the VTOR register which gives the address of vector table. */
-        "   ldr r0, [r0]                                    \n"/* The first entry in vector table is stack pointer. */
-        "   msr msp, r0                                     \n"/* Set the MSP back to the start of the stack. */
-        "   cpsie i                                         \n"/* Globally enable interrupts. */
+        "   ldr r0, xVTORConst                              \n" /* Use the NVIC offset register to locate the stack. */
+        "   ldr r0, [r0]                                    \n" /* Read the VTOR register which gives the address of vector table. */
+        "   ldr r0, [r0]                                    \n" /* The first entry in vector table is stack pointer. */
+        "   msr msp, r0                                     \n" /* Set the MSP back to the start of the stack. */
+        "   cpsie i                                         \n" /* Globally enable interrupts. */
         "   cpsie f                                         \n"
         "   dsb                                             \n"
         "   isb                                             \n"
-        "   svc %0                                          \n"/* System call to start the first task. */
+        "   svc %0                                          \n" /* System call to start the first task. */
         "   nop                                             \n"
         "                                                   \n"
         "   .align 4                                        \n"
@@ -235,12 +235,12 @@ uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCT
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs r0, basepri                                 \n"/* r0 = basepri. Return original basepri value. */
-        "   mov r1, %0                                      \n"/* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        "   msr basepri, r1                                 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        "   mrs r0, basepri                                 \n" /* r0 = basepri. Return original basepri value. */
+        "   mov r1, %0                                      \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        "   msr basepri, r1                                 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
         "   dsb                                             \n"
         "   isb                                             \n"
-        "   bx lr                                           \n"/* Return. */
+        "   bx lr                                           \n" /* Return. */
         ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
     );
 }
@@ -252,10 +252,10 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   msr basepri, r0                                 \n"/* basepri = ulMask. */
+        "   msr basepri, r0                                 \n" /* basepri = ulMask. */
         "   dsb                                             \n"
         "   isb                                             \n"
-        "   bx lr                                           \n"/* Return. */
+        "   bx lr                                           \n" /* Return. */
         ::: "memory"
     );
 }
@@ -263,320 +263,320 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
 
 #if ( configENABLE_MPU == 1 )
 
-void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        " .syntax unified                                 \n"
-        " .extern SecureContext_SaveContext               \n"
-        " .extern SecureContext_LoadContext               \n"
-        "                                                 \n"
-        " ldr r3, xSecureContextConst                     \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-        " ldr r0, [r3]                                    \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
-        " ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        " ldr r1, [r3]                                    \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
-        " ldr r2, [r1]                                    \n" /* r2 = Location in TCB where the context should be saved. */
-        "                                                 \n"
-        " cbz r0, save_ns_context                         \n" /* No secure context to save. */
-        " save_s_context:                                 \n"
-        "    push {r0-r2, lr}                             \n"
-        "    bl SecureContext_SaveContext                 \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-        "    pop {r0-r2, lr}                              \n"
-        "                                                 \n"
-        " save_ns_context:                                \n"
-        "    mov r3, lr                                   \n" /* r3 = LR (EXC_RETURN). */
-        "    lsls r3, r3, #25                             \n" /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-        "    bmi save_special_regs                        \n" /* r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
-        "                                                 \n"
-        " save_general_regs:                              \n"
-        "    mrs r3, psp                                  \n"
-        "                                                 \n"
-    #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-        "    add r3, r3, #0x20                            \n" /* Move r3 to location where s0 is saved. */
-        "    tst lr, #0x10                                \n"
-        "    ittt eq                                      \n"
-        "    vstmiaeq r2!, {s16-s31}                      \n" /* Store s16-s31. */
-        "    vldmiaeq r3, {s0-s16}                        \n" /* Copy hardware saved FP context into s0-s16. */
-        "    vstmiaeq r2!, {s0-s16}                       \n" /* Store hardware saved FP context. */
-        "    sub r3, r3, #0x20                            \n" /* Set r3 back to the location of hardware saved context. */
-    #endif /* configENABLE_FPU || configENABLE_MVE */
-        "                                                 \n"
-        "    stmia r2!, {r4-r11}                          \n" /* Store r4-r11. */
-        "    ldmia r3, {r4-r11}                           \n" /* Copy the hardware saved context into r4-r11. */
-        "    stmia r2!, {r4-r11}                          \n" /* Store the hardware saved context. */
-        "                                                 \n"
-        " save_special_regs:                              \n"
-        "    mrs r3, psp                                  \n" /* r3 = PSP. */
-        "    mrs r4, psplim                               \n" /* r4 = PSPLIM. */
-        "    mrs r5, control                              \n" /* r5 = CONTROL. */
-        "    stmia r2!, {r0, r3-r5, lr}                   \n" /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
-        "    str r2, [r1]                                 \n" /* Save the location from where the context should be restored as the first member of TCB. */
-        "                                                 \n"
-        " select_next_task:                               \n"
-        "    mov r0, %0                                   \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
-        "    msr basepri, r0                              \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        "    dsb                                          \n"
-        "    isb                                          \n"
-        "    bl vTaskSwitchContext                        \n"
-        "    mov r0, #0                                   \n" /* r0 = 0. */
-        "    msr basepri, r0                              \n" /* Enable interrupts. */
-        "                                                 \n"
-        " program_mpu:                                    \n"
-        "    ldr r3, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB.*/
-        "                                                 \n"
-        "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-        "    ldr r1, xMPUCTRLConst                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
-        "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
-        "    str r2, [r1]                                 \n" /* Disable MPU. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
-        "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-        "    ldr r2, xMAIR0Const                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-        "    str r1, [r2]                                 \n" /* Program MAIR0. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-        "    ldr r1, xRNRConst                            \n" /* r1 = 0xe000ed98 [Location of RNR]. */
-        "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "                                                 \n"
-        "    movs r3, #4                                  \n" /* r3 = 4. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 4. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-        "                                                 \n"
-        #if ( configTOTAL_MPU_REGIONS == 16 )
-        "    movs r3, #8                                  \n" /* r3 = 8. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 8. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-        "    movs r3, #12                                 \n" /* r3 = 12. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 12. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-        #endif /* configTOTAL_MPU_REGIONS == 16 */
-        "                                                 \n"
-        "   ldr r1, xMPUCTRLConst                         \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
-        "   orr r2, #1                                    \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
-        "   str r2, [r1]                                  \n" /* Enable MPU. */
-        "   dsb                                           \n" /* Force memory writes before continuing. */
-        "                                                 \n"
-        " restore_context:                                \n"
-        "    ldr r3, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r1, [r3]                                 \n" /* r1 = pxCurrentTCB.*/
-        "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
-        "                                                 \n"
-        " restore_special_regs:                           \n"
-        "    ldmdb r2!, {r0, r3-r5, lr}                   \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
-        "    msr psp, r3                                  \n"
-        "    msr psplim, r4                               \n"
-        "    msr control, r5                              \n"
-        "    ldr r4, xSecureContextConst                  \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-        "    str r0, [r4]                                 \n" /* Restore xSecureContext. */
-        "    cbz r0, restore_ns_context                   \n" /* No secure context to restore. */
-        "                                                 \n"
-        " restore_s_context:                              \n"
-        "    push {r1-r3, lr}                             \n"
-        "    bl SecureContext_LoadContext                 \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-        "    pop {r1-r3, lr}                              \n"
-        "                                                 \n"
-        " restore_ns_context:                             \n"
-        "    mov r0, lr                                   \n" /* r0 = LR (EXC_RETURN). */
-        "    lsls r0, r0, #25                             \n" /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-        "    bmi restore_context_done                     \n" /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
-        "                                                 \n"
-        " restore_general_regs:                           \n"
-        "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
-        "    stmia r3!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
-        "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 restored. */
-    #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-        "    tst lr, #0x10                                \n"
-        "    ittt eq                                      \n"
-        "    vldmdbeq r2!, {s0-s16}                       \n" /* s0-s16 contain hardware saved FP context. */
-        "    vstmiaeq r3!, {s0-s16}                       \n" /* Copy hardware saved FP context on the task stack. */
-        "    vldmdbeq r2!, {s16-s31}                      \n" /* Restore s16-s31. */
-    #endif /* configENABLE_FPU || configENABLE_MVE */
-        "                                                 \n"
-        " restore_context_done:                           \n"
-        "    str r2, [r1]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
-        "    bx lr                                        \n"
-        "                                                 \n"
-        " .align 4                                        \n"
-        " pxCurrentTCBConst: .word pxCurrentTCB           \n"
-        " xSecureContextConst: .word xSecureContext       \n"
-        " xMPUCTRLConst: .word 0xe000ed94                 \n"
-        " xMAIR0Const: .word 0xe000edc0                   \n"
-        " xRNRConst: .word 0xe000ed98                     \n"
-        " xRBARConst: .word 0xe000ed9c                    \n"
-        ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
-    );
-}
+    void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                 \n"
+            " .extern SecureContext_SaveContext               \n"
+            " .extern SecureContext_LoadContext               \n"
+            "                                                 \n"
+            " ldr r3, xSecureContextConst                     \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            " ldr r0, [r3]                                    \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+            " ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            " ldr r1, [r3]                                    \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
+            " ldr r2, [r1]                                    \n" /* r2 = Location in TCB where the context should be saved. */
+            "                                                 \n"
+            " cbz r0, save_ns_context                         \n" /* No secure context to save. */
+            " save_s_context:                                 \n"
+            "    push {r0-r2, lr}                             \n"
+            "    bl SecureContext_SaveContext                 \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+            "    pop {r0-r2, lr}                              \n"
+            "                                                 \n"
+            " save_ns_context:                                \n"
+            "    mov r3, lr                                   \n" /* r3 = LR (EXC_RETURN). */
+            "    lsls r3, r3, #25                             \n" /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+            "    bmi save_special_regs                        \n" /* r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
+            "                                                 \n"
+            " save_general_regs:                              \n"
+            "    mrs r3, psp                                  \n"
+            "                                                 \n"
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+                "    add r3, r3, #0x20                            \n" /* Move r3 to location where s0 is saved. */
+                "    tst lr, #0x10                                \n"
+                "    ittt eq                                      \n"
+                "    vstmiaeq r2!, {s16-s31}                      \n" /* Store s16-s31. */
+                "    vldmiaeq r3, {s0-s16}                        \n" /* Copy hardware saved FP context into s0-s16. */
+                "    vstmiaeq r2!, {s0-s16}                       \n" /* Store hardware saved FP context. */
+                "    sub r3, r3, #0x20                            \n" /* Set r3 back to the location of hardware saved context. */
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+            "                                                 \n"
+            "    stmia r2!, {r4-r11}                          \n" /* Store r4-r11. */
+            "    ldmia r3, {r4-r11}                           \n" /* Copy the hardware saved context into r4-r11. */
+            "    stmia r2!, {r4-r11}                          \n" /* Store the hardware saved context. */
+            "                                                 \n"
+            " save_special_regs:                              \n"
+            "    mrs r3, psp                                  \n" /* r3 = PSP. */
+            "    mrs r4, psplim                               \n" /* r4 = PSPLIM. */
+            "    mrs r5, control                              \n" /* r5 = CONTROL. */
+            "    stmia r2!, {r0, r3-r5, lr}                   \n" /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
+            "    str r2, [r1]                                 \n" /* Save the location from where the context should be restored as the first member of TCB. */
+            "                                                 \n"
+            " select_next_task:                               \n"
+            "    mov r0, %0                                   \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
+            "    msr basepri, r0                              \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+            "    dsb                                          \n"
+            "    isb                                          \n"
+            "    bl vTaskSwitchContext                        \n"
+            "    mov r0, #0                                   \n" /* r0 = 0. */
+            "    msr basepri, r0                              \n" /* Enable interrupts. */
+            "                                                 \n"
+            " program_mpu:                                    \n"
+            "    ldr r3, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB.*/
+            "                                                 \n"
+            "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
+            "    ldr r1, xMPUCTRLConst                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
+            "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
+            "    str r2, [r1]                                 \n" /* Disable MPU. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
+            "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
+            "    ldr r2, xMAIR0Const                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    str r1, [r2]                                 \n" /* Program MAIR0. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
+            "    ldr r1, xRNRConst                            \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "                                                 \n"
+            "    movs r3, #4                                  \n" /* r3 = 4. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 4. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "                                                 \n"
+            #if ( configTOTAL_MPU_REGIONS == 16 )
+                "    movs r3, #8                                  \n" /* r3 = 8. */
+                "    str r3, [r1]                                 \n" /* Program RNR = 8. */
+                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+                "    movs r3, #12                                 \n" /* r3 = 12. */
+                "    str r3, [r1]                                 \n" /* Program RNR = 12. */
+                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            #endif /* configTOTAL_MPU_REGIONS == 16 */
+            "                                                 \n"
+            "   ldr r1, xMPUCTRLConst                         \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
+            "   orr r2, #1                                    \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
+            "   str r2, [r1]                                  \n" /* Enable MPU. */
+            "   dsb                                           \n" /* Force memory writes before continuing. */
+            "                                                 \n"
+            " restore_context:                                \n"
+            "    ldr r3, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r1, [r3]                                 \n" /* r1 = pxCurrentTCB.*/
+            "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
+            "                                                 \n"
+            " restore_special_regs:                           \n"
+            "    ldmdb r2!, {r0, r3-r5, lr}                   \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
+            "    msr psp, r3                                  \n"
+            "    msr psplim, r4                               \n"
+            "    msr control, r5                              \n"
+            "    ldr r4, xSecureContextConst                  \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "    str r0, [r4]                                 \n" /* Restore xSecureContext. */
+            "    cbz r0, restore_ns_context                   \n" /* No secure context to restore. */
+            "                                                 \n"
+            " restore_s_context:                              \n"
+            "    push {r1-r3, lr}                             \n"
+            "    bl SecureContext_LoadContext                 \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+            "    pop {r1-r3, lr}                              \n"
+            "                                                 \n"
+            " restore_ns_context:                             \n"
+            "    mov r0, lr                                   \n" /* r0 = LR (EXC_RETURN). */
+            "    lsls r0, r0, #25                             \n" /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+            "    bmi restore_context_done                     \n" /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
+            "                                                 \n"
+            " restore_general_regs:                           \n"
+            "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
+            "    stmia r3!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
+            "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 restored. */
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+                "    tst lr, #0x10                                \n"
+                "    ittt eq                                      \n"
+                "    vldmdbeq r2!, {s0-s16}                       \n" /* s0-s16 contain hardware saved FP context. */
+                "    vstmiaeq r3!, {s0-s16}                       \n" /* Copy hardware saved FP context on the task stack. */
+                "    vldmdbeq r2!, {s16-s31}                      \n" /* Restore s16-s31. */
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+            "                                                 \n"
+            " restore_context_done:                           \n"
+            "    str r2, [r1]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
+            "    bx lr                                        \n"
+            "                                                 \n"
+            " .align 4                                        \n"
+            " pxCurrentTCBConst: .word pxCurrentTCB           \n"
+            " xSecureContextConst: .word xSecureContext       \n"
+            " xMPUCTRLConst: .word 0xe000ed94                 \n"
+            " xMAIR0Const: .word 0xe000edc0                   \n"
+            " xRNRConst: .word 0xe000ed98                     \n"
+            " xRBARConst: .word 0xe000ed9c                    \n"
+            ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+        );
+    }
 
 #else /* configENABLE_MPU */
 
-void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "   .syntax unified                                 \n"
-        "   .extern SecureContext_SaveContext               \n"
-        "   .extern SecureContext_LoadContext               \n"
-        "                                                   \n"
-        "   ldr r3, xSecureContextConst                     \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
-        "   ldr r0, [r3]                                    \n"/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
-        "   ldr r3, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r3]                                    \n"/* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
-        "   mrs r2, psp                                     \n"/* Read PSP in r2. */
-        "                                                   \n"
-        "   cbz r0, save_ns_context                         \n"/* No secure context to save. */
-        "   push {r0-r2, r14}                               \n"
-        "   bl SecureContext_SaveContext                    \n"/* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-        "   pop {r0-r3}                                     \n"/* LR is now in r3. */
-        "   mov lr, r3                                      \n"/* LR = r3. */
-        "   lsls r1, r3, #25                                \n"/* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-        "   bpl save_ns_context                             \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-        "                                                   \n"
-        "   ldr r3, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r3]                                    \n"/* Read pxCurrentTCB.*/
-        "   subs r2, r2, #12                                \n"/* Make space for xSecureContext, PSPLIM and LR on the stack. */
-        "   str r2, [r1]                                    \n"/* Save the new top of stack in TCB. */
-        "   mrs r1, psplim                                  \n"/* r1 = PSPLIM. */
-        "   mov r3, lr                                      \n"/* r3 = LR/EXC_RETURN. */
-        "   stmia r2!, {r0, r1, r3}                         \n"/* Store xSecureContext, PSPLIM and LR on the stack. */
-        "   b select_next_task                              \n"
-        "                                                   \n"
-        " save_ns_context:                                  \n"
-        "   ldr r3, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r3]                                    \n"/* Read pxCurrentTCB. */
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-            "   tst lr, #0x10                               \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
-            "   it eq                                       \n"
-            "   vstmdbeq r2!, {s16-s31}                     \n"/* Store the additional FP context registers which are not saved automatically. */
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-        "   subs r2, r2, #44                                \n"/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
-        "   str r2, [r1]                                    \n"/* Save the new top of stack in TCB. */
-        "   adds r2, r2, #12                                \n"/* r2 = r2 + 12. */
-        "   stm r2, {r4-r11}                                \n"/* Store the registers that are not saved automatically. */
-        "   mrs r1, psplim                                  \n"/* r1 = PSPLIM. */
-        "   mov r3, lr                                      \n"/* r3 = LR/EXC_RETURN. */
-        "   subs r2, r2, #12                                \n"/* r2 = r2 - 12. */
-        "   stmia r2!, {r0, r1, r3}                         \n"/* Store xSecureContext, PSPLIM and LR on the stack. */
-        "                                                   \n"
-        " select_next_task:                                 \n"
-        "   mov r0, %0                                      \n"/* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
-        "   msr basepri, r0                                 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        "   dsb                                             \n"
-        "   isb                                             \n"
-        "   bl vTaskSwitchContext                           \n"
-        "   mov r0, #0                                      \n"/* r0 = 0. */
-        "   msr basepri, r0                                 \n"/* Enable interrupts. */
-        "                                                   \n"
-        "   ldr r3, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r3]                                    \n"/* Read pxCurrentTCB. */
-        "   ldr r2, [r1]                                    \n"/* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
-        "                                                   \n"
-        "   ldmia r2!, {r0, r1, r4}                         \n"/* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
-        "   msr psplim, r1                                  \n"/* Restore the PSPLIM register value for the task. */
-        "   mov lr, r4                                      \n"/* LR = r4. */
-        "   ldr r3, xSecureContextConst                     \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
-        "   str r0, [r3]                                    \n"/* Restore the task's xSecureContext. */
-        "   cbz r0, restore_ns_context                      \n"/* If there is no secure context for the task, restore the non-secure context. */
-        "   ldr r3, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r3]                                    \n"/* Read pxCurrentTCB. */
-        "   push {r2, r4}                                   \n"
-        "   bl SecureContext_LoadContext                    \n"/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-        "   pop {r2, r4}                                    \n"
-        "   mov lr, r4                                      \n"/* LR = r4. */
-        "   lsls r1, r4, #25                                \n"/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-        "   bpl restore_ns_context                          \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-        "   msr psp, r2                                     \n"/* Remember the new top of stack for the task. */
-        "   bx lr                                           \n"
-        "                                                   \n"
-        " restore_ns_context:                               \n"
-        "   ldmia r2!, {r4-r11}                             \n"/* Restore the registers that are not automatically restored. */
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-            "   tst lr, #0x10                               \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
-            "   it eq                                       \n"
-            "   vldmiaeq r2!, {s16-s31}                     \n"/* Restore the additional FP context registers which are not restored automatically. */
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-        "   msr psp, r2                                     \n"/* Remember the new top of stack for the task. */
-        "   bx lr                                           \n"
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "pxCurrentTCBConst: .word pxCurrentTCB              \n"
-        "xSecureContextConst: .word xSecureContext          \n"
-        ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
-    );
-}
+    void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            "   .syntax unified                                 \n"
+            "   .extern SecureContext_SaveContext               \n"
+            "   .extern SecureContext_LoadContext               \n"
+            "                                                   \n"
+            "   ldr r3, xSecureContextConst                     \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "   ldr r0, [r3]                                    \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
+            "   mrs r2, psp                                     \n" /* Read PSP in r2. */
+            "                                                   \n"
+            "   cbz r0, save_ns_context                         \n" /* No secure context to save. */
+            "   push {r0-r2, r14}                               \n"
+            "   bl SecureContext_SaveContext                    \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+            "   pop {r0-r3}                                     \n" /* LR is now in r3. */
+            "   mov lr, r3                                      \n" /* LR = r3. */
+            "   lsls r1, r3, #25                                \n" /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+            "   bpl save_ns_context                             \n" /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+            "                                                   \n"
+            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB.*/
+            "   subs r2, r2, #12                                \n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */
+            "   str r2, [r1]                                    \n" /* Save the new top of stack in TCB. */
+            "   mrs r1, psplim                                  \n" /* r1 = PSPLIM. */
+            "   mov r3, lr                                      \n" /* r3 = LR/EXC_RETURN. */
+            "   stmia r2!, {r0, r1, r3}                         \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
+            "   b select_next_task                              \n"
+            "                                                   \n"
+            " save_ns_context:                                  \n"
+            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+                "   tst lr, #0x10                               \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+                "   it eq                                       \n"
+                "   vstmdbeq r2!, {s16-s31}                     \n" /* Store the additional FP context registers which are not saved automatically. */
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+            "   subs r2, r2, #44                                \n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
+            "   str r2, [r1]                                    \n" /* Save the new top of stack in TCB. */
+            "   adds r2, r2, #12                                \n" /* r2 = r2 + 12. */
+            "   stm r2, {r4-r11}                                \n" /* Store the registers that are not saved automatically. */
+            "   mrs r1, psplim                                  \n" /* r1 = PSPLIM. */
+            "   mov r3, lr                                      \n" /* r3 = LR/EXC_RETURN. */
+            "   subs r2, r2, #12                                \n" /* r2 = r2 - 12. */
+            "   stmia r2!, {r0, r1, r3}                         \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
+            "                                                   \n"
+            " select_next_task:                                 \n"
+            "   mov r0, %0                                      \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
+            "   msr basepri, r0                                 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+            "   dsb                                             \n"
+            "   isb                                             \n"
+            "   bl vTaskSwitchContext                           \n"
+            "   mov r0, #0                                      \n" /* r0 = 0. */
+            "   msr basepri, r0                                 \n" /* Enable interrupts. */
+            "                                                   \n"
+            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
+            "   ldr r2, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
+            "                                                   \n"
+            "   ldmia r2!, {r0, r1, r4}                         \n" /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
+            "   msr psplim, r1                                  \n" /* Restore the PSPLIM register value for the task. */
+            "   mov lr, r4                                      \n" /* LR = r4. */
+            "   ldr r3, xSecureContextConst                     \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "   str r0, [r3]                                    \n" /* Restore the task's xSecureContext. */
+            "   cbz r0, restore_ns_context                      \n" /* If there is no secure context for the task, restore the non-secure context. */
+            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
+            "   push {r2, r4}                                   \n"
+            "   bl SecureContext_LoadContext                    \n" /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+            "   pop {r2, r4}                                    \n"
+            "   mov lr, r4                                      \n" /* LR = r4. */
+            "   lsls r1, r4, #25                                \n" /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+            "   bpl restore_ns_context                          \n" /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+            "   msr psp, r2                                     \n" /* Remember the new top of stack for the task. */
+            "   bx lr                                           \n"
+            "                                                   \n"
+            " restore_ns_context:                               \n"
+            "   ldmia r2!, {r4-r11}                             \n" /* Restore the registers that are not automatically restored. */
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+                "   tst lr, #0x10                               \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+                "   it eq                                       \n"
+                "   vldmiaeq r2!, {s16-s31}                     \n" /* Restore the additional FP context registers which are not restored automatically. */
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+            "   msr psp, r2                                     \n" /* Remember the new top of stack for the task. */
+            "   bx lr                                           \n"
+            "                                                   \n"
+            "   .align 4                                        \n"
+            "pxCurrentTCBConst: .word pxCurrentTCB              \n"
+            "xSecureContextConst: .word xSecureContext          \n"
+            ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+        );
+    }
 
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-   __asm volatile
-    (
-        ".syntax unified                \n"
-        ".extern vPortSVCHandler_C      \n"
-        ".extern vSystemCallEnter       \n"
-        ".extern vSystemCallEnter_1     \n"
-        ".extern vSystemCallExit        \n"
-        "                               \n"
-        "tst lr, #4                     \n"
-        "ite eq                         \n"
-        "mrseq r0, msp                  \n"
-        "mrsne r0, psp                  \n"
-        "                               \n"
-        "ldr r1, [r0, #24]              \n"
-        "ldrb r2, [r1, #-2]             \n"
-        "cmp r2, %0                     \n"
-        "beq syscall_enter              \n"
-        "cmp r2, %1                     \n"
-        "beq syscall_enter_1            \n"
-        "cmp r2, %2                     \n"
-        "beq syscall_exit               \n"
-        "b vPortSVCHandler_C            \n"
-        "                               \n"
-        "syscall_enter:                 \n"
-        "    mov r1, lr                 \n"
-        "    b vSystemCallEnter         \n"
-        "                               \n"
-        "syscall_enter_1:               \n"
-        "    mov r1, lr                 \n"
-        "    b vSystemCallEnter_1       \n"
-        "                               \n"
-        "syscall_exit:                  \n"
-        "    mov r1, lr                 \n"
-        "    b vSystemCallExit          \n"
-        "                               \n"
-        : /* No outputs. */
-        :"i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT )
-        : "r0", "r1", "r2", "memory"
-    );
-}
+    void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            ".syntax unified                \n"
+            ".extern vPortSVCHandler_C      \n"
+            ".extern vSystemCallEnter       \n"
+            ".extern vSystemCallEnter_1     \n"
+            ".extern vSystemCallExit        \n"
+            "                               \n"
+            "tst lr, #4                     \n"
+            "ite eq                         \n"
+            "mrseq r0, msp                  \n"
+            "mrsne r0, psp                  \n"
+            "                               \n"
+            "ldr r1, [r0, #24]              \n"
+            "ldrb r2, [r1, #-2]             \n"
+            "cmp r2, %0                     \n"
+            "beq syscall_enter              \n"
+            "cmp r2, %1                     \n"
+            "beq syscall_enter_1            \n"
+            "cmp r2, %2                     \n"
+            "beq syscall_exit               \n"
+            "b vPortSVCHandler_C            \n"
+            "                               \n"
+            "syscall_enter:                 \n"
+            "    mov r1, lr                 \n"
+            "    b vSystemCallEnter         \n"
+            "                               \n"
+            "syscall_enter_1:               \n"
+            "    mov r1, lr                 \n"
+            "    b vSystemCallEnter_1       \n"
+            "                               \n"
+            "syscall_exit:                  \n"
+            "    mov r1, lr                 \n"
+            "    b vSystemCallExit          \n"
+            "                               \n"
+            : /* No outputs. */
+            : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT )
+            : "r0", "r1", "r2", "memory"
+        );
+    }
 
 #else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
-void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "   .syntax unified                                 \n"
-        "                                                   \n"
-        "   tst lr, #4                                      \n"
-        "   ite eq                                          \n"
-        "   mrseq r0, msp                                   \n"
-        "   mrsne r0, psp                                   \n"
-        "   ldr r1, svchandler_address_const                \n"
-        "   bx r1                                           \n"
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "svchandler_address_const: .word vPortSVCHandler_C  \n"
-    );
-}
+    void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            "   .syntax unified                                 \n"
+            "                                                   \n"
+            "   tst lr, #4                                      \n"
+            "   ite eq                                          \n"
+            "   mrseq r0, msp                                   \n"
+            "   mrsne r0, psp                                   \n"
+            "   ldr r1, svchandler_address_const                \n"
+            "   bx r1                                           \n"
+            "                                                   \n"
+            "   .align 4                                        \n"
+            "svchandler_address_const: .word vPortSVCHandler_C  \n"
+        );
+    }
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
@@ -587,8 +587,8 @@ void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   svc %0                                          \n"/* Secure context is allocated in the supervisor call. */
-        "   bx lr                                           \n"/* Return. */
+        "   svc %0                                          \n" /* Secure context is allocated in the supervisor call. */
+        "   bx lr                                           \n" /* Return. */
         ::"i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"
     );
 }
@@ -600,12 +600,12 @@ void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PR
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   ldr r2, [r0]                                    \n"/* The first item in the TCB is the top of the stack. */
-        "   ldr r1, [r2]                                    \n"/* The first item on the stack is the task's xSecureContext. */
-        "   cmp r1, #0                                      \n"/* Raise svc if task's xSecureContext is not NULL. */
+        "   ldr r2, [r0]                                    \n" /* The first item in the TCB is the top of the stack. */
+        "   ldr r1, [r2]                                    \n" /* The first item on the stack is the task's xSecureContext. */
+        "   cmp r1, #0                                      \n" /* Raise svc if task's xSecureContext is not NULL. */
         "   it ne                                           \n"
-        "   svcne %0                                        \n"/* Secure context is freed in the supervisor call. */
-        "   bx lr                                           \n"/* Return. */
+        "   svcne %0                                        \n" /* Secure context is freed in the supervisor call. */
+        "   bx lr                                           \n" /* Return. */
         ::"i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"
     );
 }
diff --git a/portable/GCC/ARM_CM55/non_secure/portmacro.h b/portable/GCC/ARM_CM55/non_secure/portmacro.h
index cce022882..7b011b5b5 100644
--- a/portable/GCC/ARM_CM55/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM55/non_secure/portmacro.h
@@ -53,9 +53,9 @@
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME                       "Cortex-M55"
-#define portHAS_ARMV8M_MAIN_EXTENSION       1
-#define portDONT_DISCARD                    __attribute__( ( used ) )
+#define portARCH_NAME                    "Cortex-M55"
+#define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
 /* ARMv8-M common port configurations. */
@@ -65,8 +65,8 @@
 /**
  * @brief Critical section management.
  */
-#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()
-#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )
+#define portDISABLE_INTERRUPTS()    ulSetInterruptMask()
+#define portENABLE_INTERRUPTS()     vClearInterruptMask( 0 )
 /*-----------------------------------------------------------*/
 
 /* *INDENT-OFF* */
diff --git a/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h
index e5ffdb48b..62e462a27 100644
--- a/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h
@@ -81,8 +81,8 @@ typedef unsigned long    UBaseType_t;
     typedef uint32_t     TickType_t;
     #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-     * not need to be guarded with a critical section. */
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
     #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -117,7 +117,7 @@ extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGE
 extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
 
 #if ( configENABLE_TRUSTZONE == 1 )
-    extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize );     /* __attribute__ (( naked )) */
+    extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
     extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
 #endif /* configENABLE_TRUSTZONE */
 
@@ -188,13 +188,13 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Settings to define an MPU region.
-     */
+/**
+ * @brief Settings to define an MPU region.
+ */
     typedef struct MPURegionSettings
     {
-        uint32_t ulRBAR;     /**< RBAR for the region. */
-        uint32_t ulRLAR;     /**< RLAR for the region. */
+        uint32_t ulRBAR; /**< RBAR for the region. */
+        uint32_t ulRLAR; /**< RLAR for the region. */
     } MPURegionSettings_t;
 
     #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
@@ -203,9 +203,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-        /**
-         * @brief System call stack.
-         */
+/**
+ * @brief System call stack.
+ */
         typedef struct SYSTEM_CALL_STACK_INFO
         {
             uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ];
@@ -218,74 +218,74 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
-    /**
-     * @brief MPU settings as stored in the TCB.
-     */
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
     #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
 
-        #if( configENABLE_TRUSTZONE == 1 )
+        #if ( configENABLE_TRUSTZONE == 1 )
 
-            /*
-             * +-----------+---------------+----------+-----------------+------------------------------+-----+
-             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
-             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
-             * +-----------+---------------+----------+-----------------+------------------------------+-----+
-             *
-             * <-----------><--------------><---------><----------------><-----------------------------><---->
-             *      16             16            8               8                     5                   1
-             */
-            #define MAX_CONTEXT_SIZE 54
+/*
+ * +-----------+---------------+----------+-----------------+------------------------------+-----+
+ * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+ * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+ * +-----------+---------------+----------+-----------------+------------------------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><-----------------------------><---->
+ *      16             16            8               8                     5                   1
+ */
+            #define MAX_CONTEXT_SIZE    54
 
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-            /*
-             * +-----------+---------------+----------+-----------------+----------------------+-----+
-             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
-             * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
-             * +-----------+---------------+----------+-----------------+----------------------+-----+
-             *
-             * <-----------><--------------><---------><----------------><---------------------><---->
-             *      16             16            8               8                  4              1
-             */
-            #define MAX_CONTEXT_SIZE 53
+/*
+ * +-----------+---------------+----------+-----------------+----------------------+-----+
+ * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+ * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
+ * +-----------+---------------+----------+-----------------+----------------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><---------------------><---->
+ *      16             16            8               8                  4              1
+ */
+            #define MAX_CONTEXT_SIZE    53
 
         #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
 
     #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-        #if( configENABLE_TRUSTZONE == 1 )
+        #if ( configENABLE_TRUSTZONE == 1 )
 
-            /*
-             * +----------+-----------------+------------------------------+-----+
-             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
-             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
-             * +----------+-----------------+------------------------------+-----+
-             *
-             * <---------><----------------><------------------------------><---->
-             *     8               8                      5                   1
-             */
-            #define MAX_CONTEXT_SIZE 22
+/*
+ * +----------+-----------------+------------------------------+-----+
+ * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+ * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+ * +----------+-----------------+------------------------------+-----+
+ *
+ * <---------><----------------><------------------------------><---->
+ *     8               8                      5                   1
+ */
+            #define MAX_CONTEXT_SIZE    22
 
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-            /*
-             * +----------+-----------------+----------------------+-----+
-             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
-             * |          | PC, xPSR        | EXC_RETURN           |     |
-             * +----------+-----------------+----------------------+-----+
-             *
-             * <---------><----------------><----------------------><---->
-             *     8               8                  4              1
-             */
-            #define MAX_CONTEXT_SIZE 21
+/*
+ * +----------+-----------------+----------------------+-----+
+ * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+ * |          | PC, xPSR        | EXC_RETURN           |     |
+ * +----------+-----------------+----------------------+-----+
+ *
+ * <---------><----------------><----------------------><---->
+ *     8               8                  4              1
+ */
+            #define MAX_CONTEXT_SIZE    21
 
         #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
 
     #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-    /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
-    #define portSTACK_FRAME_HAS_PADDING_FLAG     ( 1UL << 0UL )
-    #define portTASK_IS_PRIVILEGED_FLAG          ( 1UL << 1UL )
+/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
+    #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
+    #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
     typedef struct MPU_SETTINGS
     {
@@ -364,49 +364,49 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-    /**
-     * @brief Allocate a secure context for the task.
-     *
-     * Tasks are not created with a secure context. Any task that is going to call
-     * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
-     * secure context before it calls any secure function.
-     *
-     * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
-     */
+/**
+ * @brief Allocate a secure context for the task.
+ *
+ * Tasks are not created with a secure context. Any task that is going to call
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+ * secure context before it calls any secure function.
+ *
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+ */
     #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
 
-    /**
-     * @brief Called when a task is deleted to delete the task's secure context,
-     * if it has one.
-     *
-     * @param[in] pxTCB The TCB of the task being deleted.
-     */
+/**
+ * @brief Called when a task is deleted to delete the task's secure context,
+ * if it has one.
+ *
+ * @param[in] pxTCB The TCB of the task being deleted.
+ */
     #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
 #endif /* configENABLE_TRUSTZONE */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Checks whether or not the processor is privileged.
-     *
-     * @return 1 if the processor is already privileged, 0 otherwise.
-     */
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
     #define portIS_PRIVILEGED()      xIsPrivileged()
 
-    /**
-     * @brief Raise an SVC request to raise privilege.
-     *
-     * The SVC handler checks that the SVC was raised from a system call and only
-     * then it raises the privilege. If this is called from any other place,
-     * the privilege is not raised.
-     */
+/**
+ * @brief Raise an SVC request to raise privilege.
+ *
+ * The SVC handler checks that the SVC was raised from a system call and only
+ * then it raises the privilege. If this is called from any other place,
+ * the privilege is not raised.
+ */
     #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
 
-    /**
-     * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
-     * register.
-     */
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
     #define portRESET_PRIVILEGE()    vResetPrivilege()
 #else
     #define portIS_PRIVILEGED()
@@ -419,12 +419,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     extern BaseType_t xPortIsTaskPrivileged( void );
 
-    /**
-     * @brief Checks whether or not the calling task is privileged.
-     *
-     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
-     */
-    #define portIS_TASK_PRIVILEGED()      xPortIsTaskPrivileged()
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
+    #define portIS_TASK_PRIVILEGED()    xPortIsTaskPrivileged()
 
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
@@ -439,9 +439,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * based on whether or not Mainline extension is implemented. */
 #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
     #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
-        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
     #else
-        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    0
     #endif
 #endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
 
@@ -450,9 +450,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  */
 #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
 
-    /**
-     * @brief Count the number of leading zeros in a 32-bit value.
-     */
+/**
+ * @brief Count the number of leading zeros in a 32-bit value.
+ */
     static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
     {
         uint32_t ulReturn;
@@ -462,7 +462,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         return ulReturn;
     }
 
-    /* Check the configuration. */
+/* Check the configuration. */
     #if ( configMAX_PRIORITIES > 32 )
         #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
     #endif
@@ -471,16 +471,16 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection.  Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
     #endif
 
-    /**
-     * @brief Store/clear the ready priorities in a bit map.
-     */
-    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+/**
+ * @brief Store/clear the ready priorities in a bit map.
+ */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )      ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )       ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 
-    /**
-     * @brief Get the priority of the highest-priority task that is ready to execute.
-     */
-    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )   uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+/**
+ * @brief Get the priority of the highest-priority task that is ready to execute.
+ */
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
 
 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM55/secure/secure_context.c b/portable/GCC/ARM_CM55/secure/secure_context.c
index 0730d574d..7d2171996 100644
--- a/portable/GCC/ARM_CM55/secure/secure_context.c
+++ b/portable/GCC/ARM_CM55/secure/secure_context.c
@@ -65,7 +65,7 @@
  * @brief Maximum number of secure contexts.
  */
 #ifndef secureconfigMAX_SECURE_CONTEXTS
-    #define secureconfigMAX_SECURE_CONTEXTS        8UL
+    #define secureconfigMAX_SECURE_CONTEXTS    8UL
 #endif
 /*-----------------------------------------------------------*/
 
@@ -164,15 +164,15 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
         }
 
         #if ( configENABLE_MPU == 1 )
-            {
-                /* Configure thread mode to use PSP and to be unprivileged. */
-                secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
-            }
+        {
+            /* Configure thread mode to use PSP and to be unprivileged. */
+            secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
+        }
         #else /* configENABLE_MPU */
-            {
-                /* Configure thread mode to use PSP and to be privileged. */
-                secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
-            }
+        {
+            /* Configure thread mode to use PSP and to be privileged. */
+            secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
+        }
         #endif /* configENABLE_MPU */
     }
 }
@@ -219,16 +219,16 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
             if( pucStackMemory != NULL )
             {
                 /* Since stack grows down, the starting point will be the last
-                 * location. Note that this location is next to the last
-                 * allocated byte for stack (excluding the space for seal values)
-                 * because the hardware decrements the stack pointer before
-                 * writing i.e. if stack pointer is 0x2, a push operation will
-                 * decrement the stack pointer to 0x1 and then write at 0x1. */
+                * location. Note that this location is next to the last
+                * allocated byte for stack (excluding the space for seal values)
+                * because the hardware decrements the stack pointer before
+                * writing i.e. if stack pointer is 0x2, a push operation will
+                * decrement the stack pointer to 0x1 and then write at 0x1. */
                 xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize;
 
                 /* Seal the created secure process stack. */
-                *( uint32_t * )( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE;
-                *( uint32_t * )( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE;
+                *( uint32_t * ) ( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE;
+                *( uint32_t * ) ( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE;
 
                 /* The stack cannot go beyond this location. This value is
                  * programmed in the PSPLIM register on context switch.*/
@@ -237,32 +237,32 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
                 xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle;
 
                 #if ( configENABLE_MPU == 1 )
+                {
+                    /* Store the correct CONTROL value for the task on the stack.
+                     * This value is programmed in the CONTROL register on
+                     * context switch. */
+                    pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart;
+                    pulCurrentStackPointer--;
+
+                    if( ulIsTaskPrivileged )
                     {
-                        /* Store the correct CONTROL value for the task on the stack.
-                         * This value is programmed in the CONTROL register on
-                         * context switch. */
-                        pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart;
-                        pulCurrentStackPointer--;
-
-                        if( ulIsTaskPrivileged )
-                        {
-                            *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
-                        }
-                        else
-                        {
-                            *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
-                        }
-
-                        /* Store the current stack pointer. This value is programmed in
-                         * the PSP register on context switch. */
-                        xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+                        *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
                     }
+                    else
+                    {
+                        *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
+                    }
+
+                    /* Store the current stack pointer. This value is programmed in
+                     * the PSP register on context switch. */
+                    xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+                }
                 #else /* configENABLE_MPU */
-                    {
-                        /* Current SP is set to the starting of the stack. This
-                         * value programmed in the PSP register on context switch. */
-                        xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart;
-                    }
+                {
+                    /* Current SP is set to the starting of the stack. This
+                     * value programmed in the PSP register on context switch. */
+                    xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart;
+                }
                 #endif /* configENABLE_MPU */
 
                 /* Ensure to never return 0 as a valid context handle. */
@@ -275,7 +275,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
 }
 /*-----------------------------------------------------------*/
 
-secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle,
+                                                              void * pvTaskHandle )
 {
     uint32_t ulIPSR, ulSecureContextIndex;
 
@@ -306,7 +307,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandl
 }
 /*-----------------------------------------------------------*/
 
-secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle,
+                                                              void * pvTaskHandle )
 {
     uint8_t * pucStackLimit;
     uint32_t ulSecureContextIndex;
@@ -328,7 +330,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandl
 }
 /*-----------------------------------------------------------*/
 
-secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle,
+                                                              void * pvTaskHandle )
 {
     uint8_t * pucStackLimit;
     uint32_t ulSecureContextIndex;
diff --git a/portable/GCC/ARM_CM55/secure/secure_context.h b/portable/GCC/ARM_CM55/secure/secure_context.h
index d0adbaf01..0bf776198 100644
--- a/portable/GCC/ARM_CM55/secure/secure_context.h
+++ b/portable/GCC/ARM_CM55/secure/secure_context.h
@@ -38,12 +38,12 @@
 /**
  * @brief PSP value when no secure context is loaded.
  */
-#define securecontextNO_STACK               0x0
+#define securecontextNO_STACK              0x0
 
 /**
  * @brief Invalid context ID.
  */
-#define securecontextINVALID_CONTEXT_ID     0UL
+#define securecontextINVALID_CONTEXT_ID    0UL
 /*-----------------------------------------------------------*/
 
 /**
@@ -108,7 +108,8 @@ void SecureContext_Init( void );
  * @param[in] xSecureContextHandle Context handle corresponding to the
  * context to be freed.
  */
-void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle,
+                                void * pvTaskHandle );
 
 /**
  * @brief Loads the given context.
@@ -119,7 +120,8 @@ void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void
  * @param[in] xSecureContextHandle Context handle corresponding to the context
  * to be loaded.
  */
-void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle,
+                                void * pvTaskHandle );
 
 /**
  * @brief Saves the given context.
@@ -130,6 +132,7 @@ void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void
  * @param[in] xSecureContextHandle Context handle corresponding to the context
  * to be saved.
  */
-void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle,
+                                void * pvTaskHandle );
 
 #endif /* __SECURE_CONTEXT_H__ */
diff --git a/portable/GCC/ARM_CM55/secure/secure_heap.c b/portable/GCC/ARM_CM55/secure/secure_heap.c
index f3b80df54..1ec3bdbdb 100644
--- a/portable/GCC/ARM_CM55/secure/secure_heap.c
+++ b/portable/GCC/ARM_CM55/secure/secure_heap.c
@@ -67,7 +67,7 @@
 #define secureheapSIZE_MAX              ( ~( ( size_t ) 0 ) )
 
 /* Check if adding a and b will result in overflow. */
-#define secureheapADD_WILL_OVERFLOW( a, b )         ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) )
+#define secureheapADD_WILL_OVERFLOW( a, b )    ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) )
 
 /* MSB of the xBlockSize member of an BlockLink_t structure is used to track
  * the allocation status of a block.  When MSB of the xBlockSize member of
@@ -397,17 +397,17 @@ void * pvPortMalloc( size_t xWantedSize )
     traceMALLOC( pvReturn, xWantedSize );
 
     #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
+    {
+        if( pvReturn == NULL )
         {
-            if( pvReturn == NULL )
-            {
-                extern void vApplicationMallocFailedHook( void );
-                vApplicationMallocFailedHook();
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
+            extern void vApplicationMallocFailedHook( void );
+            vApplicationMallocFailedHook();
         }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
     #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */
 
     secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );
diff --git a/portable/GCC/ARM_CM55/secure/secure_init.c b/portable/GCC/ARM_CM55/secure/secure_init.c
index dc19ebc7d..b89c5f644 100644
--- a/portable/GCC/ARM_CM55/secure/secure_init.c
+++ b/portable/GCC/ARM_CM55/secure/secure_init.c
@@ -93,7 +93,7 @@ secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )
          * permitted. CP11 should be programmed to the same value as CP10. */
         *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
 
-        /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
+        /* LSPENS = 0 ==> LSPEN is writable from non-secure state. This ensures
          * that we can enable/disable lazy stacking in port.c file. */
         *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK );
 
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.c
index 2d1218a95..d1fbdc0e5 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.c
@@ -44,2274 +44,2274 @@
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-#if ( INCLUDE_xTaskDelayUntil == 1 )
+    #if ( INCLUDE_xTaskDelayUntil == 1 )
 
-BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
-                                const TickType_t xTimeIncrement ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
+                                        const TickType_t xTimeIncrement ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
-                                const TickType_t xTimeIncrement ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskDelayUntilImpl                       \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskDelayUntil_Unpriv                        \n"
-        " MPU_xTaskDelayUntil_Priv:                             \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskDelayUntilImpl                         \n"
-        " MPU_xTaskDelayUntil_Unpriv:                           \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskDelayUntilImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
+                                        const TickType_t xTimeIncrement ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskDelayUntilImpl                       \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskDelayUntil_Unpriv                        \n"
+                " MPU_xTaskDelayUntil_Priv:                             \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskDelayUntilImpl                         \n"
+                " MPU_xTaskDelayUntil_Unpriv:                           \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskDelayUntilImpl                        \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */
+    #endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_xTaskAbortDelay == 1 )
+    #if ( INCLUDE_xTaskAbortDelay == 1 )
 
-BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskAbortDelayImpl                       \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskAbortDelay_Unpriv                        \n"
-        " MPU_xTaskAbortDelay_Priv:                             \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskAbortDelayImpl                         \n"
-        " MPU_xTaskAbortDelay_Unpriv:                           \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskAbortDelayImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskAbortDelayImpl                       \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskAbortDelay_Unpriv                        \n"
+                " MPU_xTaskAbortDelay_Priv:                             \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskAbortDelayImpl                         \n"
+                " MPU_xTaskAbortDelay_Unpriv:                           \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskAbortDelayImpl                        \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */
+    #endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_vTaskDelay == 1 )
+    #if ( INCLUDE_vTaskDelay == 1 )
 
-void MPU_vTaskDelay( const TickType_t xTicksToDelay ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskDelay( const TickType_t xTicksToDelay ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskDelayImpl                            \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskDelay_Unpriv                             \n"
-        " MPU_vTaskDelay_Priv:                                  \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskDelayImpl                              \n"
-        " MPU_vTaskDelay_Unpriv:                                \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskDelayImpl                             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskDelayImpl                            \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskDelay_Unpriv                             \n"
+                " MPU_vTaskDelay_Priv:                                  \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskDelayImpl                              \n"
+                " MPU_vTaskDelay_Unpriv:                                \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskDelayImpl                             \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_vTaskDelay == 1 ) */
+    #endif /* if ( INCLUDE_vTaskDelay == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_uxTaskPriorityGet == 1 )
+    #if ( INCLUDE_uxTaskPriorityGet == 1 )
 
-UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskPriorityGetImpl                     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTaskPriorityGet_Unpriv                      \n"
-        " MPU_uxTaskPriorityGet_Priv:                           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTaskPriorityGetImpl                       \n"
-        " MPU_uxTaskPriorityGet_Unpriv:                         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskPriorityGetImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskPriorityGetImpl                     \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTaskPriorityGet_Unpriv                      \n"
+                " MPU_uxTaskPriorityGet_Priv:                           \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTaskPriorityGetImpl                       \n"
+                " MPU_uxTaskPriorityGet_Unpriv:                         \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskPriorityGetImpl                      \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */
+    #endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_eTaskGetState == 1 )
+    #if ( INCLUDE_eTaskGetState == 1 )
 
-eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_eTaskGetStateImpl                         \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_eTaskGetState_Unpriv                          \n"
-        " MPU_eTaskGetState_Priv:                               \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_eTaskGetStateImpl                           \n"
-        " MPU_eTaskGetState_Unpriv:                             \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_eTaskGetStateImpl                          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_eTaskGetStateImpl                         \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_eTaskGetState_Unpriv                          \n"
+                " MPU_eTaskGetState_Priv:                               \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_eTaskGetStateImpl                           \n"
+                " MPU_eTaskGetState_Unpriv:                             \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_eTaskGetStateImpl                          \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_eTaskGetState == 1 ) */
+    #endif /* if ( INCLUDE_eTaskGetState == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-void MPU_vTaskGetInfo( TaskHandle_t xTask,
-                       TaskStatus_t * pxTaskStatus,
-                       BaseType_t xGetFreeStackSpace,
-                       eTaskState eState ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskGetInfo( TaskHandle_t xTask,
+                               TaskStatus_t * pxTaskStatus,
+                               BaseType_t xGetFreeStackSpace,
+                               eTaskState eState ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskGetInfo( TaskHandle_t xTask,
-                       TaskStatus_t * pxTaskStatus,
-                       BaseType_t xGetFreeStackSpace,
-                       eTaskState eState ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskGetInfoImpl                          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskGetInfo_Unpriv                           \n"
-        " MPU_vTaskGetInfo_Priv:                                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskGetInfoImpl                            \n"
-        " MPU_vTaskGetInfo_Unpriv:                              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskGetInfoImpl                           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskGetInfo( TaskHandle_t xTask,
+                               TaskStatus_t * pxTaskStatus,
+                               BaseType_t xGetFreeStackSpace,
+                               eTaskState eState ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskGetInfoImpl                          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskGetInfo_Unpriv                           \n"
+                " MPU_vTaskGetInfo_Priv:                                \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskGetInfoImpl                            \n"
+                " MPU_vTaskGetInfo_Unpriv:                              \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskGetInfoImpl                           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
+    #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
+    #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
 
-TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetIdleTaskHandleImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGetIdleTaskHandle_Unpriv                 \n"
-        " MPU_xTaskGetIdleTaskHandle_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGetIdleTaskHandleImpl                  \n"
-        " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetIdleTaskHandleImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetIdleTaskHandleImpl                \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGetIdleTaskHandle_Unpriv                 \n"
+                " MPU_xTaskGetIdleTaskHandle_Priv:                      \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGetIdleTaskHandleImpl                  \n"
+                " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetIdleTaskHandleImpl                 \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */
+    #endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_vTaskSuspend == 1 )
+    #if ( INCLUDE_vTaskSuspend == 1 )
 
-void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSuspendImpl                          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskSuspend_Unpriv                           \n"
-        " MPU_vTaskSuspend_Priv:                                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskSuspendImpl                            \n"
-        " MPU_vTaskSuspend_Unpriv:                              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSuspendImpl                           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskSuspendImpl                          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskSuspend_Unpriv                           \n"
+                " MPU_vTaskSuspend_Priv:                                \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskSuspendImpl                            \n"
+                " MPU_vTaskSuspend_Unpriv:                              \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskSuspendImpl                           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
+    #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_vTaskSuspend == 1 )
+    #if ( INCLUDE_vTaskSuspend == 1 )
 
-void MPU_vTaskResume( TaskHandle_t xTaskToResume ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskResume( TaskHandle_t xTaskToResume ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskResumeImpl                           \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskResume_Unpriv                            \n"
-        " MPU_vTaskResume_Priv:                                 \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskResumeImpl                             \n"
-        " MPU_vTaskResume_Unpriv:                               \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskResumeImpl                            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskResumeImpl                           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskResume_Unpriv                            \n"
+                " MPU_vTaskResume_Priv:                                 \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskResumeImpl                             \n"
+                " MPU_vTaskResume_Unpriv:                               \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskResumeImpl                            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
+    #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
 /*-----------------------------------------------------------*/
 
-TickType_t MPU_xTaskGetTickCount( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    TickType_t MPU_xTaskGetTickCount( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TickType_t MPU_xTaskGetTickCount( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetTickCountImpl                     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGetTickCount_Unpriv                      \n"
-        " MPU_xTaskGetTickCount_Priv:                           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGetTickCountImpl                       \n"
-        " MPU_xTaskGetTickCount_Unpriv:                         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetTickCountImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    TickType_t MPU_xTaskGetTickCount( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xTaskGetTickCountImpl                     \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xTaskGetTickCount_Unpriv                      \n"
+            " MPU_xTaskGetTickCount_Priv:                           \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xTaskGetTickCountImpl                       \n"
+            " MPU_xTaskGetTickCount_Unpriv:                         \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xTaskGetTickCountImpl                      \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetNumberOfTasksImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTaskGetNumberOfTasks_Unpriv                 \n"
-        " MPU_uxTaskGetNumberOfTasks_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTaskGetNumberOfTasksImpl                  \n"
-        " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetNumberOfTasksImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_uxTaskGetNumberOfTasksImpl                \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_uxTaskGetNumberOfTasks_Unpriv                 \n"
+            " MPU_uxTaskGetNumberOfTasks_Priv:                      \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_uxTaskGetNumberOfTasksImpl                  \n"
+            " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_uxTaskGetNumberOfTasksImpl                 \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configGENERATE_RUN_TIME_STATS == 1 )
+    #if ( configGENERATE_RUN_TIME_STATS == 1 )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetRunTimeCounterImpl               \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGetRunTimeCounter_Unpriv                \n"
-        " MPU_ulTaskGetRunTimeCounter_Priv:                     \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGetRunTimeCounterImpl                 \n"
-        " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetRunTimeCounterImpl                \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetRunTimeCounterImpl               \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGetRunTimeCounter_Unpriv                \n"
+                " MPU_ulTaskGetRunTimeCounter_Priv:                     \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGetRunTimeCounterImpl                 \n"
+                " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetRunTimeCounterImpl                \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configGENERATE_RUN_TIME_STATS == 1 )
+    #if ( configGENERATE_RUN_TIME_STATS == 1 )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetRunTimePercentImpl               \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGetRunTimePercent_Unpriv                \n"
-        " MPU_ulTaskGetRunTimePercent_Priv:                     \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGetRunTimePercentImpl                 \n"
-        " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetRunTimePercentImpl                \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetRunTimePercentImpl               \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGetRunTimePercent_Unpriv                \n"
+                " MPU_ulTaskGetRunTimePercent_Priv:                     \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGetRunTimePercentImpl                 \n"
+                " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetRunTimePercentImpl                \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+    #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetIdleRunTimePercentImpl           \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv            \n"
-        " MPU_ulTaskGetIdleRunTimePercent_Priv:                 \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGetIdleRunTimePercentImpl             \n"
-        " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetIdleRunTimePercentImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetIdleRunTimePercentImpl           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv            \n"
+                " MPU_ulTaskGetIdleRunTimePercent_Priv:                 \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGetIdleRunTimePercentImpl             \n"
+                " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetIdleRunTimePercentImpl            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+    #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetIdleRunTimeCounterImpl           \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv            \n"
-        " MPU_ulTaskGetIdleRunTimeCounter_Priv:                 \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGetIdleRunTimeCounterImpl             \n"
-        " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetIdleRunTimeCounterImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetIdleRunTimeCounterImpl           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv            \n"
+                " MPU_ulTaskGetIdleRunTimeCounter_Priv:                 \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGetIdleRunTimeCounterImpl             \n"
+                " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetIdleRunTimeCounterImpl            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+    #if ( configUSE_APPLICATION_TASK_TAG == 1 )
 
-void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
-                                     TaskHookFunction_t pxHookFunction ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
+                                             TaskHookFunction_t pxHookFunction ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
-                                     TaskHookFunction_t pxHookFunction ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSetApplicationTaskTagImpl            \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskSetApplicationTaskTag_Unpriv             \n"
-        " MPU_vTaskSetApplicationTaskTag_Priv:                  \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskSetApplicationTaskTagImpl              \n"
-        " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSetApplicationTaskTagImpl             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
+                                             TaskHookFunction_t pxHookFunction ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskSetApplicationTaskTagImpl            \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskSetApplicationTaskTag_Unpriv             \n"
+                " MPU_vTaskSetApplicationTaskTag_Priv:                  \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskSetApplicationTaskTagImpl              \n"
+                " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskSetApplicationTaskTagImpl             \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
+    #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+    #if ( configUSE_APPLICATION_TASK_TAG == 1 )
 
-TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetApplicationTaskTagImpl            \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGetApplicationTaskTag_Unpriv             \n"
-        " MPU_xTaskGetApplicationTaskTag_Priv:                  \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGetApplicationTaskTagImpl              \n"
-        " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetApplicationTaskTagImpl             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetApplicationTaskTagImpl            \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGetApplicationTaskTag_Unpriv             \n"
+                " MPU_xTaskGetApplicationTaskTag_Priv:                  \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGetApplicationTaskTagImpl              \n"
+                " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetApplicationTaskTagImpl             \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
+    #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+    #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
 
-void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
-                                            BaseType_t xIndex,
-                                            void * pvValue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
+                                                    BaseType_t xIndex,
+                                                    void * pvValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
-                                            BaseType_t xIndex,
-                                            void * pvValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSetThreadLocalStoragePointerImpl     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv      \n"
-        " MPU_vTaskSetThreadLocalStoragePointer_Priv:           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskSetThreadLocalStoragePointerImpl       \n"
-        " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSetThreadLocalStoragePointerImpl      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
+                                                    BaseType_t xIndex,
+                                                    void * pvValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskSetThreadLocalStoragePointerImpl     \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv      \n"
+                " MPU_vTaskSetThreadLocalStoragePointer_Priv:           \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskSetThreadLocalStoragePointerImpl       \n"
+                " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskSetThreadLocalStoragePointerImpl      \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
+    #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+    #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
 
-void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
-                                               BaseType_t xIndex ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
+                                                       BaseType_t xIndex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
-                                               BaseType_t xIndex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pvTaskGetThreadLocalStoragePointerImpl    \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv     \n"
-        " MPU_pvTaskGetThreadLocalStoragePointer_Priv:          \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_pvTaskGetThreadLocalStoragePointerImpl      \n"
-        " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pvTaskGetThreadLocalStoragePointerImpl     \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
+                                                       BaseType_t xIndex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pvTaskGetThreadLocalStoragePointerImpl    \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv     \n"
+                " MPU_pvTaskGetThreadLocalStoragePointer_Priv:          \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_pvTaskGetThreadLocalStoragePointerImpl      \n"
+                " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pvTaskGetThreadLocalStoragePointerImpl     \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
+    #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
-                                      const UBaseType_t uxArraySize,
-                                      configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
+                                              const UBaseType_t uxArraySize,
+                                              configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
-                                      const UBaseType_t uxArraySize,
-                                      configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetSystemStateImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTaskGetSystemState_Unpriv                   \n"
-        " MPU_uxTaskGetSystemState_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTaskGetSystemStateImpl                    \n"
-        " MPU_uxTaskGetSystemState_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetSystemStateImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
+                                              const UBaseType_t uxArraySize,
+                                              configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskGetSystemStateImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTaskGetSystemState_Unpriv                   \n"
+                " MPU_uxTaskGetSystemState_Priv:                        \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTaskGetSystemStateImpl                    \n"
+                " MPU_uxTaskGetSystemState_Unpriv:                      \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskGetSystemStateImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
+    #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
+    #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
 
-UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetStackHighWaterMarkImpl           \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTaskGetStackHighWaterMark_Unpriv            \n"
-        " MPU_uxTaskGetStackHighWaterMark_Priv:                 \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTaskGetStackHighWaterMarkImpl             \n"
-        " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetStackHighWaterMarkImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskGetStackHighWaterMarkImpl           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTaskGetStackHighWaterMark_Unpriv            \n"
+                " MPU_uxTaskGetStackHighWaterMark_Priv:                 \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTaskGetStackHighWaterMarkImpl             \n"
+                " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskGetStackHighWaterMarkImpl            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */
+    #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
+    #if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
 
-configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetStackHighWaterMark2Impl          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv           \n"
-        " MPU_uxTaskGetStackHighWaterMark2_Priv:                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTaskGetStackHighWaterMark2Impl            \n"
-        " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetStackHighWaterMark2Impl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskGetStackHighWaterMark2Impl          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv           \n"
+                " MPU_uxTaskGetStackHighWaterMark2_Priv:                \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTaskGetStackHighWaterMark2Impl            \n"
+                " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskGetStackHighWaterMark2Impl           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */
+    #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
+    #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
 
-TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetCurrentTaskHandleImpl             \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGetCurrentTaskHandle_Unpriv              \n"
-        " MPU_xTaskGetCurrentTaskHandle_Priv:                   \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGetCurrentTaskHandleImpl               \n"
-        " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetCurrentTaskHandleImpl              \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetCurrentTaskHandleImpl             \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGetCurrentTaskHandle_Unpriv              \n"
+                " MPU_xTaskGetCurrentTaskHandle_Priv:                   \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGetCurrentTaskHandleImpl               \n"
+                " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetCurrentTaskHandleImpl              \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
+    #endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_xTaskGetSchedulerState == 1 )
+    #if ( INCLUDE_xTaskGetSchedulerState == 1 )
 
-BaseType_t MPU_xTaskGetSchedulerState( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGetSchedulerState( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGetSchedulerState( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetSchedulerStateImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGetSchedulerState_Unpriv                 \n"
-        " MPU_xTaskGetSchedulerState_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGetSchedulerStateImpl                  \n"
-        " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetSchedulerStateImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGetSchedulerState( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetSchedulerStateImpl                \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGetSchedulerState_Unpriv                 \n"
+                " MPU_xTaskGetSchedulerState_Priv:                      \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGetSchedulerStateImpl                  \n"
+                " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetSchedulerStateImpl                 \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */
+    #endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */
 /*-----------------------------------------------------------*/
 
-void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSetTimeOutStateImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskSetTimeOutState_Unpriv                   \n"
-        " MPU_vTaskSetTimeOutState_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskSetTimeOutStateImpl                    \n"
-        " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSetTimeOutStateImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_vTaskSetTimeOutStateImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_vTaskSetTimeOutState_Unpriv                   \n"
+            " MPU_vTaskSetTimeOutState_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_vTaskSetTimeOutStateImpl                    \n"
+            " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_vTaskSetTimeOutStateImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
-                                     TickType_t * const pxTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
+                                         TickType_t * const pxTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
-                                     TickType_t * const pxTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskCheckForTimeOutImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskCheckForTimeOut_Unpriv                   \n"
-        " MPU_xTaskCheckForTimeOut_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskCheckForTimeOutImpl                    \n"
-        " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskCheckForTimeOutImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
+                                         TickType_t * const pxTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xTaskCheckForTimeOutImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xTaskCheckForTimeOut_Unpriv                   \n"
+            " MPU_xTaskCheckForTimeOut_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xTaskCheckForTimeOutImpl                    \n"
+            " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xTaskCheckForTimeOutImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                   UBaseType_t uxIndexToNotify,
-                                   uint32_t ulValue,
-                                   eNotifyAction eAction,
-                                   uint32_t * pulPreviousNotificationValue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
+                                           UBaseType_t uxIndexToNotify,
+                                           uint32_t ulValue,
+                                           eNotifyAction eAction,
+                                           uint32_t * pulPreviousNotificationValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                   UBaseType_t uxIndexToNotify,
-                                   uint32_t ulValue,
-                                   eNotifyAction eAction,
-                                   uint32_t * pulPreviousNotificationValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGenericNotifyImpl                    \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGenericNotify_Unpriv                     \n"
-        " MPU_xTaskGenericNotify_Priv:                          \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGenericNotifyImpl                      \n"
-        " MPU_xTaskGenericNotify_Unpriv:                        \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGenericNotifyImpl                     \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
+                                           UBaseType_t uxIndexToNotify,
+                                           uint32_t ulValue,
+                                           eNotifyAction eAction,
+                                           uint32_t * pulPreviousNotificationValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGenericNotifyImpl                    \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGenericNotify_Unpriv                     \n"
+                " MPU_xTaskGenericNotify_Priv:                          \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGenericNotifyImpl                      \n"
+                " MPU_xTaskGenericNotify_Unpriv:                        \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGenericNotifyImpl                     \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                       uint32_t ulBitsToClearOnEntry,
-                                       uint32_t ulBitsToClearOnExit,
-                                       uint32_t * pulNotificationValue,
-                                       TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
+                                               uint32_t ulBitsToClearOnEntry,
+                                               uint32_t ulBitsToClearOnExit,
+                                               uint32_t * pulNotificationValue,
+                                               TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                       uint32_t ulBitsToClearOnEntry,
-                                       uint32_t ulBitsToClearOnExit,
-                                       uint32_t * pulNotificationValue,
-                                       TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGenericNotifyWaitImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGenericNotifyWait_Unpriv                 \n"
-        " MPU_xTaskGenericNotifyWait_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGenericNotifyWaitImpl                  \n"
-        " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGenericNotifyWaitImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
+                                               uint32_t ulBitsToClearOnEntry,
+                                               uint32_t ulBitsToClearOnExit,
+                                               uint32_t * pulNotificationValue,
+                                               TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGenericNotifyWaitImpl                \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGenericNotifyWait_Unpriv                 \n"
+                " MPU_xTaskGenericNotifyWait_Priv:                      \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGenericNotifyWaitImpl                  \n"
+                " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGenericNotifyWaitImpl                 \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
-                                      BaseType_t xClearCountOnExit,
-                                      TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
+                                              BaseType_t xClearCountOnExit,
+                                              TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
-                                      BaseType_t xClearCountOnExit,
-                                      TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGenericNotifyTakeImpl               \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGenericNotifyTake_Unpriv                \n"
-        " MPU_ulTaskGenericNotifyTake_Priv:                     \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGenericNotifyTakeImpl                 \n"
-        " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGenericNotifyTakeImpl                \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
+                                              BaseType_t xClearCountOnExit,
+                                              TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGenericNotifyTakeImpl               \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGenericNotifyTake_Unpriv                \n"
+                " MPU_ulTaskGenericNotifyTake_Priv:                     \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGenericNotifyTakeImpl                 \n"
+                " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGenericNotifyTakeImpl                \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
-                                             UBaseType_t uxIndexToClear ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
+                                                     UBaseType_t uxIndexToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
-                                             UBaseType_t uxIndexToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGenericNotifyStateClearImpl          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGenericNotifyStateClear_Unpriv           \n"
-        " MPU_xTaskGenericNotifyStateClear_Priv:                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGenericNotifyStateClearImpl            \n"
-        " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGenericNotifyStateClearImpl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
+                                                     UBaseType_t uxIndexToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGenericNotifyStateClearImpl          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGenericNotifyStateClear_Unpriv           \n"
+                " MPU_xTaskGenericNotifyStateClear_Priv:                \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGenericNotifyStateClearImpl            \n"
+                " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGenericNotifyStateClearImpl           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
-                                            UBaseType_t uxIndexToClear,
-                                            uint32_t ulBitsToClear ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
+                                                    UBaseType_t uxIndexToClear,
+                                                    uint32_t ulBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
-                                            UBaseType_t uxIndexToClear,
-                                            uint32_t ulBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGenericNotifyValueClearImpl         \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGenericNotifyValueClear_Unpriv          \n"
-        " MPU_ulTaskGenericNotifyValueClear_Priv:               \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGenericNotifyValueClearImpl           \n"
-        " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGenericNotifyValueClearImpl          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
+                                                    UBaseType_t uxIndexToClear,
+                                                    uint32_t ulBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGenericNotifyValueClearImpl         \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGenericNotifyValueClear_Unpriv          \n"
+                " MPU_ulTaskGenericNotifyValueClear_Priv:               \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGenericNotifyValueClearImpl           \n"
+                " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGenericNotifyValueClearImpl          \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
-                                  const void * const pvItemToQueue,
-                                  TickType_t xTicksToWait,
-                                  const BaseType_t xCopyPosition ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
+                                      const void * const pvItemToQueue,
+                                      TickType_t xTicksToWait,
+                                      const BaseType_t xCopyPosition ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
-                                  const void * const pvItemToQueue,
-                                  TickType_t xTicksToWait,
-                                  const BaseType_t xCopyPosition ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueGenericSendImpl                     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueGenericSend_Unpriv                      \n"
-        " MPU_xQueueGenericSend_Priv:                           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueGenericSendImpl                       \n"
-        " MPU_xQueueGenericSend_Unpriv:                         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueGenericSendImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
+                                      const void * const pvItemToQueue,
+                                      TickType_t xTicksToWait,
+                                      const BaseType_t xCopyPosition ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueueGenericSendImpl                     \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xQueueGenericSend_Unpriv                      \n"
+            " MPU_xQueueGenericSend_Priv:                           \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xQueueGenericSendImpl                       \n"
+            " MPU_xQueueGenericSend_Unpriv:                         \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueueGenericSendImpl                      \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxQueueMessagesWaitingImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxQueueMessagesWaiting_Unpriv                 \n"
-        " MPU_uxQueueMessagesWaiting_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxQueueMessagesWaitingImpl                  \n"
-        " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxQueueMessagesWaitingImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_uxQueueMessagesWaitingImpl                \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_uxQueueMessagesWaiting_Unpriv                 \n"
+            " MPU_uxQueueMessagesWaiting_Priv:                      \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_uxQueueMessagesWaitingImpl                  \n"
+            " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_uxQueueMessagesWaitingImpl                 \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxQueueSpacesAvailableImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxQueueSpacesAvailable_Unpriv                 \n"
-        " MPU_uxQueueSpacesAvailable_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxQueueSpacesAvailableImpl                  \n"
-        " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxQueueSpacesAvailableImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_uxQueueSpacesAvailableImpl                \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_uxQueueSpacesAvailable_Unpriv                 \n"
+            " MPU_uxQueueSpacesAvailable_Priv:                      \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_uxQueueSpacesAvailableImpl                  \n"
+            " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_uxQueueSpacesAvailableImpl                 \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
-                              void * const pvBuffer,
-                              TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
+                                  void * const pvBuffer,
+                                  TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
-                              void * const pvBuffer,
-                              TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueReceiveImpl                         \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueReceive_Unpriv                          \n"
-        " MPU_xQueueReceive_Priv:                               \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueReceiveImpl                           \n"
-        " MPU_xQueueReceive_Unpriv:                             \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueReceiveImpl                          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
+                                  void * const pvBuffer,
+                                  TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueueReceiveImpl                         \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xQueueReceive_Unpriv                          \n"
+            " MPU_xQueueReceive_Priv:                               \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xQueueReceiveImpl                           \n"
+            " MPU_xQueueReceive_Unpriv:                             \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueueReceiveImpl                          \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
-                           void * const pvBuffer,
-                           TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
+                               void * const pvBuffer,
+                               TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
-                           void * const pvBuffer,
-                           TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueuePeekImpl                            \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueuePeek_Unpriv                             \n"
-        " MPU_xQueuePeek_Priv:                                  \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueuePeekImpl                              \n"
-        " MPU_xQueuePeek_Unpriv:                                \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueuePeekImpl                             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
+                               void * const pvBuffer,
+                               TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueuePeekImpl                            \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xQueuePeek_Unpriv                             \n"
+            " MPU_xQueuePeek_Priv:                                  \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xQueuePeekImpl                              \n"
+            " MPU_xQueuePeek_Unpriv:                                \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueuePeekImpl                             \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
-                                    TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
+                                        TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
-                                    TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueSemaphoreTakeImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueSemaphoreTake_Unpriv                    \n"
-        " MPU_xQueueSemaphoreTake_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueSemaphoreTakeImpl                     \n"
-        " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueSemaphoreTakeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
+                                        TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueueSemaphoreTakeImpl                   \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xQueueSemaphoreTake_Unpriv                    \n"
+            " MPU_xQueueSemaphoreTake_Priv:                         \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xQueueSemaphoreTakeImpl                     \n"
+            " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueueSemaphoreTakeImpl                    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+    #if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
 
-TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueGetMutexHolderImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueGetMutexHolder_Unpriv                   \n"
-        " MPU_xQueueGetMutexHolder_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueGetMutexHolderImpl                    \n"
-        " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueGetMutexHolderImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueGetMutexHolderImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueGetMutexHolder_Unpriv                   \n"
+                " MPU_xQueueGetMutexHolder_Priv:                        \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueGetMutexHolderImpl                    \n"
+                " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueGetMutexHolderImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */
+    #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+    #if ( configUSE_RECURSIVE_MUTEXES == 1 )
 
-BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
-                                         TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+                                                 TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+        BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+                                                 TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueTakeMutexRecursiveImpl              \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueTakeMutexRecursive_Unpriv               \n"
+                " MPU_xQueueTakeMutexRecursive_Priv:                    \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueTakeMutexRecursiveImpl                \n"
+                " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueTakeMutexRecursiveImpl               \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_RECURSIVE_MUTEXES == 1 )
+
+        BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueGiveMutexRecursiveImpl              \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueGiveMutexRecursive_Unpriv               \n"
+                " MPU_xQueueGiveMutexRecursive_Priv:                    \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueGiveMutexRecursiveImpl                \n"
+                " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueGiveMutexRecursiveImpl               \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_QUEUE_SETS == 1 )
+
+        QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
+                                                        const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
+                                                        const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueSelectFromSetImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueSelectFromSet_Unpriv                    \n"
+                " MPU_xQueueSelectFromSet_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueSelectFromSetImpl                     \n"
+                " MPU_xQueueSelectFromSet_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueSelectFromSetImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_QUEUE_SETS == 1 )
+
+        BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                                       QueueSetHandle_t xQueueSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                                       QueueSetHandle_t xQueueSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueAddToSetImpl                        \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueAddToSet_Unpriv                         \n"
+                " MPU_xQueueAddToSet_Priv:                              \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueAddToSetImpl                          \n"
+                " MPU_xQueueAddToSet_Unpriv:                            \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueAddToSetImpl                         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+        void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
+                                      const char * pcName ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
+                                      const char * pcName ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vQueueAddToRegistryImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vQueueAddToRegistry_Unpriv                    \n"
+                " MPU_vQueueAddToRegistry_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vQueueAddToRegistryImpl                     \n"
+                " MPU_vQueueAddToRegistry_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vQueueAddToRegistryImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+        void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vQueueUnregisterQueueImpl                 \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vQueueUnregisterQueue_Unpriv                  \n"
+                " MPU_vQueueUnregisterQueue_Priv:                       \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vQueueUnregisterQueueImpl                   \n"
+                " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vQueueUnregisterQueueImpl                  \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+        const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pcQueueGetNameImpl                        \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_pcQueueGetName_Unpriv                         \n"
+                " MPU_pcQueueGetName_Priv:                              \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_pcQueueGetNameImpl                          \n"
+                " MPU_pcQueueGetName_Unpriv:                            \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pcQueueGetNameImpl                         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pvTimerGetTimerIDImpl                     \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_pvTimerGetTimerID_Unpriv                      \n"
+                " MPU_pvTimerGetTimerID_Priv:                           \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_pvTimerGetTimerIDImpl                       \n"
+                " MPU_pvTimerGetTimerID_Unpriv:                         \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pvTimerGetTimerIDImpl                      \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
+                                   void * pvNewID ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
+                                   void * pvNewID ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTimerSetTimerIDImpl                      \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTimerSetTimerID_Unpriv                       \n"
+                " MPU_vTimerSetTimerID_Priv:                            \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTimerSetTimerIDImpl                        \n"
+                " MPU_vTimerSetTimerID_Unpriv:                          \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTimerSetTimerIDImpl                       \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerIsTimerActiveImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerIsTimerActive_Unpriv                    \n"
+                " MPU_xTimerIsTimerActive_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerIsTimerActiveImpl                     \n"
+                " MPU_xTimerIsTimerActive_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerIsTimerActiveImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetTimerDaemonTaskHandleImpl        \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv         \n"
+                " MPU_xTimerGetTimerDaemonTaskHandle_Priv:              \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerGetTimerDaemonTaskHandleImpl          \n"
+                " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetTimerDaemonTaskHandleImpl         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                                     const BaseType_t xCommandID,
+                                                     const TickType_t xOptionalValue,
+                                                     BaseType_t * const pxHigherPriorityTaskWoken,
+                                                     const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                                     const BaseType_t xCommandID,
+                                                     const TickType_t xOptionalValue,
+                                                     BaseType_t * const pxHigherPriorityTaskWoken,
+                                                     const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                               \n"
+                " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
+                "                                                               \n"
+                " push {r0}                                                     \n"
+                " mrs r0, control                                               \n"
+                " tst r0, #1                                                    \n"
+                " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
+                " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
+                "     pop {r0}                                                  \n"
+                "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
+                " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
+                "     pop {r0}                                                  \n"
+                "     svc %0                                                    \n"
+                "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
+                "     svc %1                                                    \n"
+                "     bx lr                                                     \n"
+                "                                                               \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pcTimerGetNameImpl                        \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_pcTimerGetName_Unpriv                         \n"
+                " MPU_pcTimerGetName_Priv:                              \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_pcTimerGetNameImpl                          \n"
+                " MPU_pcTimerGetName_Unpriv:                            \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pcTimerGetNameImpl                         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
+                                      const BaseType_t uxAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
+                                      const BaseType_t uxAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTimerSetReloadModeImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTimerSetReloadMode_Unpriv                    \n"
+                " MPU_vTimerSetReloadMode_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTimerSetReloadModeImpl                     \n"
+                " MPU_vTimerSetReloadMode_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTimerSetReloadModeImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetReloadModeImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerGetReloadMode_Unpriv                    \n"
+                " MPU_xTimerGetReloadMode_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerGetReloadModeImpl                     \n"
+                " MPU_xTimerGetReloadMode_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetReloadModeImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTimerGetReloadModeImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTimerGetReloadMode_Unpriv                   \n"
+                " MPU_uxTimerGetReloadMode_Priv:                        \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTimerGetReloadModeImpl                    \n"
+                " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTimerGetReloadModeImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetPeriodImpl                       \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerGetPeriod_Unpriv                        \n"
+                " MPU_xTimerGetPeriod_Priv:                             \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerGetPeriodImpl                         \n"
+                " MPU_xTimerGetPeriod_Unpriv:                           \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetPeriodImpl                        \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetExpiryTimeImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerGetExpiryTime_Unpriv                    \n"
+                " MPU_xTimerGetExpiryTime_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerGetExpiryTimeImpl                     \n"
+                " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetExpiryTimeImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         const BaseType_t xClearOnExit,
+                                         const BaseType_t xWaitForAllBits,
+                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         const BaseType_t xClearOnExit,
+                                         const BaseType_t xWaitForAllBits,
                                          TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueTakeMutexRecursiveImpl              \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueTakeMutexRecursive_Unpriv               \n"
-        " MPU_xQueueTakeMutexRecursive_Priv:                    \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueTakeMutexRecursiveImpl                \n"
-        " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueTakeMutexRecursiveImpl               \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupWaitBitsImpl                   \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
+            " MPU_xEventGroupWaitBits_Priv:                         \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xEventGroupWaitBitsImpl                     \n"
+            " MPU_xEventGroupWaitBits_Unpriv:                       \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupWaitBitsImpl                    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                          const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueGiveMutexRecursiveImpl              \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueGiveMutexRecursive_Unpriv               \n"
-        " MPU_xQueueGiveMutexRecursive_Priv:                    \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueGiveMutexRecursiveImpl                \n"
-        " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueGiveMutexRecursiveImpl               \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                          const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupClearBitsImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xEventGroupClearBits_Unpriv                   \n"
+            " MPU_xEventGroupClearBits_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xEventGroupClearBitsImpl                    \n"
+            " MPU_xEventGroupClearBits_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupClearBitsImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_QUEUE_SETS == 1 )
+    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                        const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
-                                                const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
-                                                const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueSelectFromSetImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueSelectFromSet_Unpriv                    \n"
-        " MPU_xQueueSelectFromSet_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueSelectFromSetImpl                     \n"
-        " MPU_xQueueSelectFromSet_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueSelectFromSetImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                        const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupSetBitsImpl                    \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xEventGroupSetBits_Unpriv                     \n"
+            " MPU_xEventGroupSetBits_Priv:                          \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xEventGroupSetBitsImpl                      \n"
+            " MPU_xEventGroupSetBits_Unpriv:                        \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupSetBitsImpl                     \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_QUEUE_SETS == 1 )
-
-BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
-                               QueueSetHandle_t xQueueSet ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
-                               QueueSetHandle_t xQueueSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueAddToSetImpl                        \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueAddToSet_Unpriv                         \n"
-        " MPU_xQueueAddToSet_Priv:                              \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueAddToSetImpl                          \n"
-        " MPU_xQueueAddToSet_Unpriv:                            \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueAddToSetImpl                         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_QUEUE_SETS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
-                              const char * pcName ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
-                              const char * pcName ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vQueueAddToRegistryImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vQueueAddToRegistry_Unpriv                    \n"
-        " MPU_vQueueAddToRegistry_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vQueueAddToRegistryImpl                     \n"
-        " MPU_vQueueAddToRegistry_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vQueueAddToRegistryImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vQueueUnregisterQueueImpl                 \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vQueueUnregisterQueue_Unpriv                  \n"
-        " MPU_vQueueUnregisterQueue_Priv:                       \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vQueueUnregisterQueueImpl                   \n"
-        " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vQueueUnregisterQueueImpl                  \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pcQueueGetNameImpl                        \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_pcQueueGetName_Unpriv                         \n"
-        " MPU_pcQueueGetName_Priv:                              \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_pcQueueGetNameImpl                          \n"
-        " MPU_pcQueueGetName_Unpriv:                            \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pcQueueGetNameImpl                         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pvTimerGetTimerIDImpl                     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_pvTimerGetTimerID_Unpriv                      \n"
-        " MPU_pvTimerGetTimerID_Priv:                           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_pvTimerGetTimerIDImpl                       \n"
-        " MPU_pvTimerGetTimerID_Unpriv:                         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pvTimerGetTimerIDImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
-                           void * pvNewID ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
-                           void * pvNewID ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTimerSetTimerIDImpl                      \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTimerSetTimerID_Unpriv                       \n"
-        " MPU_vTimerSetTimerID_Priv:                            \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTimerSetTimerIDImpl                        \n"
-        " MPU_vTimerSetTimerID_Unpriv:                          \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTimerSetTimerIDImpl                       \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerIsTimerActiveImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTimerIsTimerActive_Unpriv                    \n"
-        " MPU_xTimerIsTimerActive_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerIsTimerActiveImpl                     \n"
-        " MPU_xTimerIsTimerActive_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerIsTimerActiveImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetTimerDaemonTaskHandleImpl        \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv         \n"
-        " MPU_xTimerGetTimerDaemonTaskHandle_Priv:              \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerGetTimerDaemonTaskHandleImpl          \n"
-        " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetTimerDaemonTaskHandleImpl         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                             const BaseType_t xCommandID,
-                                             const TickType_t xOptionalValue,
-                                             BaseType_t * const pxHigherPriorityTaskWoken,
-                                             const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                             const BaseType_t xCommandID,
-                                             const TickType_t xOptionalValue,
-                                             BaseType_t * const pxHigherPriorityTaskWoken,
-                                             const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                               \n"
-        " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
-        "                                                               \n"
-        " push {r0}                                                     \n"
-        " mrs r0, control                                               \n"
-        " tst r0, #1                                                    \n"
-        " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
-        " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
-        "     pop {r0}                                                  \n"
-        "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
-        " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
-        "     pop {r0}                                                  \n"
-        "     svc %0                                                    \n"
-        "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
-        "     svc %1                                                    \n"
-        "     bx lr                                                     \n"
-        "                                                               \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pcTimerGetNameImpl                        \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_pcTimerGetName_Unpriv                         \n"
-        " MPU_pcTimerGetName_Priv:                              \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_pcTimerGetNameImpl                          \n"
-        " MPU_pcTimerGetName_Unpriv:                            \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pcTimerGetNameImpl                         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                              const BaseType_t uxAutoReload ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                              const BaseType_t uxAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTimerSetReloadModeImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTimerSetReloadMode_Unpriv                    \n"
-        " MPU_vTimerSetReloadMode_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTimerSetReloadModeImpl                     \n"
-        " MPU_vTimerSetReloadMode_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTimerSetReloadModeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetReloadModeImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTimerGetReloadMode_Unpriv                    \n"
-        " MPU_xTimerGetReloadMode_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerGetReloadModeImpl                     \n"
-        " MPU_xTimerGetReloadMode_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetReloadModeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTimerGetReloadModeImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTimerGetReloadMode_Unpriv                   \n"
-        " MPU_uxTimerGetReloadMode_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTimerGetReloadModeImpl                    \n"
-        " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTimerGetReloadModeImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetPeriodImpl                       \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTimerGetPeriod_Unpriv                        \n"
-        " MPU_xTimerGetPeriod_Priv:                             \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerGetPeriodImpl                         \n"
-        " MPU_xTimerGetPeriod_Unpriv:                           \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetPeriodImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetExpiryTimeImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTimerGetExpiryTime_Unpriv                    \n"
-        " MPU_xTimerGetExpiryTime_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerGetExpiryTimeImpl                     \n"
-        " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetExpiryTimeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                     const EventBits_t uxBitsToSet,
                                      const EventBits_t uxBitsToWaitFor,
-                                     const BaseType_t xClearOnExit,
-                                     const BaseType_t xWaitForAllBits,
-                                     TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                     const EventBits_t uxBitsToSet,
                                      const EventBits_t uxBitsToWaitFor,
-                                     const BaseType_t xClearOnExit,
-                                     const BaseType_t xWaitForAllBits,
                                      TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupWaitBitsImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
-        " MPU_xEventGroupWaitBits_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xEventGroupWaitBitsImpl                     \n"
-        " MPU_xEventGroupWaitBits_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupWaitBitsImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupSyncImpl                       \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xEventGroupSync_Unpriv                        \n"
+            " MPU_xEventGroupSync_Priv:                             \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xEventGroupSyncImpl                         \n"
+            " MPU_xEventGroupSync_Unpriv:                           \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupSyncImpl                        \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                      const EventBits_t uxBitsToClear ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                      const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupClearBitsImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xEventGroupClearBits_Unpriv                   \n"
-        " MPU_xEventGroupClearBits_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xEventGroupClearBitsImpl                    \n"
-        " MPU_xEventGroupClearBits_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupClearBitsImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxEventGroupGetNumberImpl                 \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxEventGroupGetNumber_Unpriv                  \n"
+                " MPU_uxEventGroupGetNumber_Priv:                       \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxEventGroupGetNumberImpl                   \n"
+                " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxEventGroupGetNumberImpl                  \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
 /*-----------------------------------------------------------*/
 
-EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                    const EventBits_t uxBitsToSet ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                    const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupSetBitsImpl                    \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xEventGroupSetBits_Unpriv                     \n"
-        " MPU_xEventGroupSetBits_Priv:                          \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xEventGroupSetBitsImpl                      \n"
-        " MPU_xEventGroupSetBits_Unpriv:                        \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupSetBitsImpl                     \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vEventGroupSetNumber( void * xEventGroup,
+                                       UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vEventGroupSetNumber( void * xEventGroup,
+                                       UBaseType_t uxEventGroupNumber ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vEventGroupSetNumberImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vEventGroupSetNumber_Unpriv                   \n"
+                " MPU_vEventGroupSetNumber_Priv:                        \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vEventGroupSetNumberImpl                    \n"
+                " MPU_vEventGroupSetNumber_Unpriv:                      \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vEventGroupSetNumberImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
 /*-----------------------------------------------------------*/
 
-EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                 const EventBits_t uxBitsToSet,
-                                 const EventBits_t uxBitsToWaitFor,
-                                 TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                  const void * pvTxData,
+                                  size_t xDataLengthBytes,
+                                  TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                 const EventBits_t uxBitsToSet,
-                                 const EventBits_t uxBitsToWaitFor,
-                                 TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupSyncImpl                       \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xEventGroupSync_Unpriv                        \n"
-        " MPU_xEventGroupSync_Priv:                             \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xEventGroupSyncImpl                         \n"
-        " MPU_xEventGroupSync_Unpriv:                           \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupSyncImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                  const void * pvTxData,
+                                  size_t xDataLengthBytes,
+                                  TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferSendImpl                     \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferSend_Unpriv                      \n"
+            " MPU_xStreamBufferSend_Priv:                           \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferSendImpl                       \n"
+            " MPU_xStreamBufferSend_Unpriv:                         \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferSendImpl                      \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                     void * pvRxData,
+                                     size_t xBufferLengthBytes,
+                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxEventGroupGetNumberImpl                 \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxEventGroupGetNumber_Unpriv                  \n"
-        " MPU_uxEventGroupGetNumber_Priv:                       \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxEventGroupGetNumberImpl                   \n"
-        " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxEventGroupGetNumberImpl                  \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                     void * pvRxData,
+                                     size_t xBufferLengthBytes,
+                                     TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferReceiveImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferReceive_Unpriv                   \n"
+            " MPU_xStreamBufferReceive_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferReceiveImpl                    \n"
+            " MPU_xStreamBufferReceive_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferReceiveImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vEventGroupSetNumber( void * xEventGroup,
-                               UBaseType_t uxEventGroupNumber ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vEventGroupSetNumber( void * xEventGroup,
-                               UBaseType_t uxEventGroupNumber ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vEventGroupSetNumberImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vEventGroupSetNumber_Unpriv                   \n"
-        " MPU_vEventGroupSetNumber_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vEventGroupSetNumberImpl                    \n"
-        " MPU_vEventGroupSetNumber_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vEventGroupSetNumberImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferIsFullImpl                   \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
+            " MPU_xStreamBufferIsFull_Priv:                         \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferIsFullImpl                     \n"
+            " MPU_xStreamBufferIsFull_Unpriv:                       \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferIsFullImpl                    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                              const void * pvTxData,
-                              size_t xDataLengthBytes,
-                              TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                              const void * pvTxData,
-                              size_t xDataLengthBytes,
-                              TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferSendImpl                     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferSend_Unpriv                      \n"
-        " MPU_xStreamBufferSend_Priv:                           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferSendImpl                       \n"
-        " MPU_xStreamBufferSend_Unpriv:                         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferSendImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
+            " MPU_xStreamBufferIsEmpty_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferIsEmptyImpl                    \n"
+            " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferIsEmptyImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                 void * pvRxData,
-                                 size_t xBufferLengthBytes,
-                                 TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                 void * pvRxData,
-                                 size_t xBufferLengthBytes,
-                                 TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferReceiveImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferReceive_Unpriv                   \n"
-        " MPU_xStreamBufferReceive_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferReceiveImpl                    \n"
-        " MPU_xStreamBufferReceive_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferReceiveImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
+            " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
+            " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferSpacesAvailableImpl           \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferIsFullImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
-        " MPU_xStreamBufferIsFull_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferIsFullImpl                     \n"
-        " MPU_xStreamBufferIsFull_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferIsFullImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
+            " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferBytesAvailableImpl             \n"
+            " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferBytesAvailableImpl            \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                 size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
-        " MPU_xStreamBufferIsEmpty_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferIsEmptyImpl                    \n"
-        " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferIsEmptyImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                 size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
+            " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
+            " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferSetTriggerLevelImpl           \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
-        " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
-        " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferSpacesAvailableImpl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
-size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
-        " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferBytesAvailableImpl             \n"
-        " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferBytesAvailableImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                             size_t xTriggerLevel ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                             size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
-        " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
-        " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferSetTriggerLevelImpl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
-size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
-        " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
-        " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferNextMessageLengthBytesImpl    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
+            " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
+            " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferNextMessageLengthBytesImpl    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/port.c b/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
index 80410e82e..c940c304b 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
@@ -110,8 +110,8 @@
 /**
  * @brief Constants used during system call enter and exit.
  */
-#define portPSR_STACK_PADDING_MASK                ( 1UL << 9UL )
-#define portEXC_RETURN_STACK_FRAME_TYPE_MASK      ( 1UL << 4UL )
+#define portPSR_STACK_PADDING_MASK              ( 1UL << 9UL )
+#define portEXC_RETURN_STACK_FRAME_TYPE_MASK    ( 1UL << 4UL )
 /*-----------------------------------------------------------*/
 
 /**
@@ -133,81 +133,81 @@
 /**
  * @brief Offsets in the stack to the parameters when inside the SVC handler.
  */
-#define portOFFSET_TO_LR                    ( 5 )
-#define portOFFSET_TO_PC                    ( 6 )
-#define portOFFSET_TO_PSR                   ( 7 )
+#define portOFFSET_TO_LR     ( 5 )
+#define portOFFSET_TO_PC     ( 6 )
+#define portOFFSET_TO_PSR    ( 7 )
 /*-----------------------------------------------------------*/
 
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                      ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                      ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                       ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                      ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                      ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                     ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                     ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK  ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK               ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK               ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK               ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK               ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK               ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK               ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK               ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK               ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0              ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1              ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2              ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3              ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4              ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5              ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6              ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7              ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE            ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT      ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                      ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE             ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -216,11 +216,11 @@
 
 /* Extract last address of the MPU region as encoded in the
  * RLAR (Region Limit Address Register) value. */
-#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar )  \
+#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar ) \
     ( ( ( rlar ) & portMPU_RLAR_ADDRESS_MASK ) | ~portMPU_RLAR_ADDRESS_MASK )
 
 /* Does addr lies within [start, end] address range? */
-#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end )    \
+#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \
     ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) )
 
 /* Is the access request satisfied by the available permissions? */
@@ -422,54 +422,57 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the system call stack so that upon returning from
-     * SVC, the system call stack is used.
-     *
-     * It is used for the system calls with up to 4 parameters.
-     *
-     * @param pulTaskStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the system call stack so that upon returning from
+ * SVC, the system call stack is used.
+ *
+ * It is used for the system calls with up to 4 parameters.
+ *
+ * @param pulTaskStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallEnter( uint32_t * pulTaskStack,
+                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the system call stack so that upon returning from
-     * SVC, the system call stack is used.
-     *
-     * It is used for the system calls with 5 parameters.
-     *
-     * @param pulTaskStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the system call stack so that upon returning from
+ * SVC, the system call stack is used.
+ *
+ * It is used for the system calls with 5 parameters.
+ *
+ * @param pulTaskStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallEnter_1( uint32_t * pulTaskStack,
+                             uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the task stack so that upon returning from
-     * SVC, the task stack is used again.
-     *
-     * @param pulSystemCallStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the task stack so that upon returning from
+ * SVC, the task stack is used again.
+ *
+ * @param pulSystemCallStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallExit( uint32_t * pulSystemCallStack,
+                          uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Checks whether or not the calling task is privileged.
-     *
-     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
-     */
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
     BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
 
 #endif /* configENABLE_MPU == 1 */
@@ -1086,18 +1089,18 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             vRestoreContextOfFirstTask();
             break;
 
-        #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
-            case portSVC_RAISE_PRIVILEGE:
+            #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+                case portSVC_RAISE_PRIVILEGE:
 
-                /* Only raise the privilege, if the svc was raised from any of
-                 * the system calls. */
-                if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
-                    ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
-                {
-                    vRaisePrivilege();
-                }
-                break;
-        #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+                    /* Only raise the privilege, if the svc was raised from any of
+                     * the system calls. */
+                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+                    {
+                        vRaisePrivilege();
+                    }
+                    break;
+            #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
         default:
             /* Incorrect SVC call. */
@@ -1108,513 +1111,526 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulSystemCallStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallEnter( uint32_t * pulTaskStack,
+                           uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulSystemCallStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        /* This is not NULL only for the duration of the system call. */
-        configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+        #if defined( __ARMCC_VERSION )
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+
+            /* This is not NULL only for the duration of the system call. */
+            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the system call stack for the stack frame. */
+            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulSystemCallStack[ i ] = pulTaskStack[ i ];
+            }
+
+            /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
+             * restore it when we exit from the system call. */
+            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* Use the pulSystemCallStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+
+            /* Remember the location where we should copy the stack frame when we exit from
+             * the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+
+            /* Record if the hardware used padding to force the stack pointer
+             * to be double word aligned. */
+            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
+            {
+                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
             }
+
+            /* We ensure in pxPortInitialiseStack that the system call stack is
+             * double word aligned and therefore, there is no need of padding.
+             * Clear the bit[9] of stacked xPSR. */
+            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
+
+            /* Raise the privilege for the duration of the system call. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " bics r0, r1         \n" /* Clear nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the system call stack for the stack frame. */
-        pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulSystemCallStack[ i ] = pulTaskStack[ i ];
-        }
-
-        /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
-         * restore it when we exit from the system call. */
-        pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-        __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* Use the pulSystemCallStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-
-        /* Remember the location where we should copy the stack frame when we exit from
-         * the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-        /* Record if the hardware used padding to force the stack pointer
-         * to be double word aligned. */
-        if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-        {
-            pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-        }
-        else
-        {
-            pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-        }
-
-        /* We ensure in pxPortInitialiseStack that the system call stack is
-         * double word aligned and therefore, there is no need of padding.
-         * Clear the bit[9] of stacked xPSR. */
-        pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-        /* Raise the privilege for the duration of the system call. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " bics r0, r1         \n" /* Clear nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulSystemCallStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallEnter_1( uint32_t * pulTaskStack,
+                             uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulSystemCallStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        /* This is not NULL only for the duration of the system call. */
-        configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+        #if defined( __ARMCC_VERSION )
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+
+            /* This is not NULL only for the duration of the system call. */
+            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the system call stack for the stack frame and
+             * the parameter passed on the stack. We only need to copy one
+             * parameter but we still reserve 2 spaces to keep the stack
+             * double word aligned. */
+            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulSystemCallStack[ i ] = pulTaskStack[ i ];
+            }
+
+            /* Copy the parameter which is passed the stack. */
+            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
+            {
+                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
+
+                /* Record if the hardware used padding to force the stack pointer
+                 * to be double word aligned. */
+                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
+
+                /* Record if the hardware used padding to force the stack pointer
+                 * to be double word aligned. */
+                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
             }
+
+            /* Store the value of the LR and PSPLIM registers before the SVC was raised.
+             * We need to restore it when we exit from the system call. */
+            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* Use the pulSystemCallStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+
+            /* Remember the location where we should copy the stack frame when we exit from
+             * the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+
+            /* We ensure in pxPortInitialiseStack that the system call stack is
+             * double word aligned and therefore, there is no need of padding.
+             * Clear the bit[9] of stacked xPSR. */
+            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
+
+            /* Raise the privilege for the duration of the system call. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " bics r0, r1         \n" /* Clear nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the system call stack for the stack frame and
-         * the parameter passed on the stack. We only need to copy one
-         * parameter but we still reserve 2 spaces to keep the stack
-         * double word aligned. */
-        pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulSystemCallStack[ i ] = pulTaskStack[ i ];
-        }
-
-        /* Copy the parameter which is passed the stack. */
-        if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-        {
-            pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
-            /* Record if the hardware used padding to force the stack pointer
-             * to be double word aligned. */
-            pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-        }
-        else
-        {
-            pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
-            /* Record if the hardware used padding to force the stack pointer
-             * to be double word aligned. */
-            pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-        }
-
-        /* Store the value of the LR and PSPLIM registers before the SVC was raised.
-         * We need to restore it when we exit from the system call. */
-        pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-        __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* Use the pulSystemCallStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-
-        /* Remember the location where we should copy the stack frame when we exit from
-         * the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-        /* We ensure in pxPortInitialiseStack that the system call stack is
-         * double word aligned and therefore, there is no need of padding.
-         * Clear the bit[9] of stacked xPSR. */
-        pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-        /* Raise the privilege for the duration of the system call. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " bics r0, r1         \n" /* Clear nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulTaskStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallExit( uint32_t * pulSystemCallStack,
+                          uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulTaskStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+        #if defined( __ARMCC_VERSION )
+
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the task stack for the stack frame. */
+            pulTaskStack = pulTaskStack - ulStackFrameSize;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulTaskStack[ i ] = pulSystemCallStack[ i ];
+            }
+
+            /* Use the pulTaskStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
+
+            /* Restore the LR and PSPLIM to what they were at the time of
+             * system call entry. */
+            pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* If the hardware used padding to force the stack pointer
+             * to be double word aligned, set the stacked xPSR bit[9],
+             * otherwise clear it. */
+            if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG )
+            {
+                pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
             }
+
+            /* This is not NULL only for the duration of the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
+
+            /* Drop the privilege before returning to the thread mode. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " orrs r0, r1         \n" /* Set nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the task stack for the stack frame. */
-        pulTaskStack = pulTaskStack - ulStackFrameSize;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulTaskStack[ i ] = pulSystemCallStack[ i ];
-        }
-
-        /* Use the pulTaskStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
-
-        /* Restore the LR and PSPLIM to what they were at the time of
-         * system call entry. */
-        pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* If the hardware used padding to force the stack pointer
-         * to be double word aligned, set the stacked xPSR bit[9],
-         * otherwise clear it. */
-        if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG )
-        {
-            pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK;
-        }
-        else
-        {
-            pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-        }
-
-        /* This is not NULL only for the duration of the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
-
-        /* Drop the privilege before returning to the thread mode. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " orrs r0, r1         \n" /* Set nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */
-{
-    BaseType_t xTaskIsPrivileged = pdFALSE;
-    const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
-
-    if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+    BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */
     {
-        xTaskIsPrivileged = pdTRUE;
-    }
+        BaseType_t xTaskIsPrivileged = pdFALSE;
+        const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
 
-    return xTaskIsPrivileged;
-}
+        if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+        {
+            xTaskIsPrivileged = pdTRUE;
+        }
+
+        return xTaskIsPrivileged;
+    }
 
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
-#if( configENABLE_MPU == 1 )
+#if ( configENABLE_MPU == 1 )
 
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     StackType_t * pxEndOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters,
-                                     BaseType_t xRunPrivileged,
-                                     xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
-{
-    uint32_t ulIndex = 0;
-
-    xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
-    ulIndex++;
-
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
-    ulIndex++;
-
-    #if ( configENABLE_TRUSTZONE == 1 )
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters,
+                                         BaseType_t xRunPrivileged,
+                                         xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
     {
-        xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT;  /* xSecureContext. */
+        uint32_t ulIndex = 0;
+
+        xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
         ulIndex++;
-    }
-    #endif /* configENABLE_TRUSTZONE */
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
-    ulIndex++;
-    if( xRunPrivileged == pdTRUE )
-    {
-        xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */
         ulIndex++;
-    }
-    else
-    {
-        xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */
         ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
+        ulIndex++;
+
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters;            /* r0. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x01010101;                           /* r1. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x02020202;                           /* r2. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x03030303;                           /* r3. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x12121212;                           /* r12. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode;                  /* PC. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR;                     /* xPSR. */
+        ulIndex++;
+
+        #if ( configENABLE_TRUSTZONE == 1 )
+        {
+            xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT; /* xSecureContext. */
+            ulIndex++;
+        }
+        #endif /* configENABLE_TRUSTZONE */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
+        ulIndex++;
+
+        if( xRunPrivileged == pdTRUE )
+        {
+            xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
+            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+            ulIndex++;
+        }
+        else
+        {
+            xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
+            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+            ulIndex++;
+        }
+
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
+        ulIndex++;
+
+        #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+        {
+            /* Ensure that the system call stack is double word aligned. */
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] );
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) &
+                                                                                     ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
+
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] );
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) +
+                                                                                            ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) &
+                                                                                          ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
+
+            /* This is not NULL only for the duration of a system call. */
+            xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL;
+        }
+        #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
+
+        return &( xMPUSettings->ulContext[ ulIndex ] );
     }
-    xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
-    ulIndex++;
-
-    #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
-    {
-        /* Ensure that the system call stack is double word aligned. */
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] );
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) &
-                                                                                 ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
-
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] );
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) +
-                                                                                        ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) &
-                                                                                      ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
-
-        /* This is not NULL only for the duration of a system call. */
-        xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL;
-    }
-    #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
-
-    return &( xMPUSettings->ulContext[ ulIndex ] );
-}
 
 #else /* configENABLE_MPU */
 
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     StackType_t * pxEndOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters ) /* PRIVILEGED_FUNCTION */
-{
-    /* Simulate the stack frame as it would be created by a context switch
-     * interrupt. */
-    #if ( portPRELOAD_REGISTERS == 0 )
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters ) /* PRIVILEGED_FUNCTION */
     {
-        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-        pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
-        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-        pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
-        *pxTopOfStack = portINITIAL_EXC_RETURN;
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
-
-        #if ( configENABLE_TRUSTZONE == 1 )
+        /* Simulate the stack frame as it would be created by a context switch
+         * interrupt. */
+        #if ( portPRELOAD_REGISTERS == 0 )
         {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
-        }
-        #endif /* configENABLE_TRUSTZONE */
-    }
-    #else /* portPRELOAD_REGISTERS */
-    {
-        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
-        pxTopOfStack--;
-        *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
+            pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
+            *pxTopOfStack = portINITIAL_EXC_RETURN;
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+            #if ( configENABLE_TRUSTZONE == 1 )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+            }
+            #endif /* configENABLE_TRUSTZONE */
+        }
+        #else /* portPRELOAD_REGISTERS */
         {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
-        }
-        #endif /* configENABLE_TRUSTZONE */
-    }
-    #endif /* portPRELOAD_REGISTERS */
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
+            pxTopOfStack--;
+            *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack;            /* Slot used to hold this task's PSPLIM value. */
 
-    return pxTopOfStack;
-}
+            #if ( configENABLE_TRUSTZONE == 1 )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+            }
+            #endif /* configENABLE_TRUSTZONE */
+        }
+        #endif /* portPRELOAD_REGISTERS */
+
+        return pxTopOfStack;
+    }
 
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.c b/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.c
index 504b6bf3b..e533dd7e9 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.c
@@ -42,111 +42,111 @@
 
 #if ( configENABLE_MPU == 1 )
 
-void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        " .syntax unified                                 \n"
-        "                                                 \n"
-        " program_mpu_first_task:                         \n"
-        "    ldr r2, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB. */
-        "                                                 \n"
-        "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-        "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
-        "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
-        "    str r2, [r1]                                 \n" /* Disable MPU. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
-        "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-        "    ldr r2, xMAIR0Const2                         \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-        "    str r1, [r2]                                 \n" /* Program MAIR0. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-        "    ldr r1, xRNRConst2                           \n" /* r1 = 0xe000ed98 [Location of RNR]. */
-        "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "                                                 \n"
-        "    movs r3, #4                                  \n" /* r3 = 4. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 4. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-        "                                                 \n"
-    #if ( configTOTAL_MPU_REGIONS == 16 )
-        "    movs r3, #8                                  \n" /* r3 = 8. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 8. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-        "    movs r3, #12                                 \n" /* r3 = 12. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 12. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-    #endif /* configTOTAL_MPU_REGIONS == 16 */
-        "                                                 \n"
-        "   ldr r1, xMPUCTRLConst2                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
-        "   orr r2, #1                                    \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
-        "   str r2, [r1]                                  \n" /* Enable MPU. */
-        "   dsb                                           \n" /* Force memory writes before continuing. */
-        "                                                 \n"
-        " restore_context_first_task:                     \n"
-        "    ldr r2, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB.*/
-        "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
-        "                                                 \n"
-        " restore_special_regs_first_task:                \n"
-        "    ldmdb r1!, {r2-r4, lr}                       \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
-        "    msr psp, r2                                  \n"
-        "    msr psplim, r3                               \n"
-        "    msr control, r4                              \n"
-        "                                                 \n"
-        " restore_general_regs_first_task:                \n"
-        "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
-        "    stmia r2!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
-        "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 restored. */
-        "                                                 \n"
-        " restore_context_done_first_task:                \n"
-        "    str r1, [r0]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
-        "    mov r0, #0                                   \n"
-        "    msr basepri, r0                              \n" /* Ensure that interrupts are enabled when the first task starts. */
-        "    bx lr                                        \n"
-        "                                                 \n"
-        " .align 4                                        \n"
-        " pxCurrentTCBConst2: .word pxCurrentTCB          \n"
-        " xMPUCTRLConst2: .word 0xe000ed94                \n"
-        " xMAIR0Const2: .word 0xe000edc0                  \n"
-        " xRNRConst2: .word 0xe000ed98                    \n"
-        " xRBARConst2: .word 0xe000ed9c                   \n"
-    );
-}
+    void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                 \n"
+            "                                                 \n"
+            " program_mpu_first_task:                         \n"
+            "    ldr r2, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB. */
+            "                                                 \n"
+            "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
+            "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
+            "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
+            "    str r2, [r1]                                 \n" /* Disable MPU. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
+            "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
+            "    ldr r2, xMAIR0Const2                         \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    str r1, [r2]                                 \n" /* Program MAIR0. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
+            "    ldr r1, xRNRConst2                           \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "                                                 \n"
+            "    movs r3, #4                                  \n" /* r3 = 4. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 4. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "                                                 \n"
+            #if ( configTOTAL_MPU_REGIONS == 16 )
+                "    movs r3, #8                                  \n" /* r3 = 8. */
+                "    str r3, [r1]                                 \n" /* Program RNR = 8. */
+                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+                "    movs r3, #12                                 \n" /* r3 = 12. */
+                "    str r3, [r1]                                 \n" /* Program RNR = 12. */
+                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            #endif /* configTOTAL_MPU_REGIONS == 16 */
+            "                                                 \n"
+            "   ldr r1, xMPUCTRLConst2                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
+            "   orr r2, #1                                    \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
+            "   str r2, [r1]                                  \n" /* Enable MPU. */
+            "   dsb                                           \n" /* Force memory writes before continuing. */
+            "                                                 \n"
+            " restore_context_first_task:                     \n"
+            "    ldr r2, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB.*/
+            "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
+            "                                                 \n"
+            " restore_special_regs_first_task:                \n"
+            "    ldmdb r1!, {r2-r4, lr}                       \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
+            "    msr psp, r2                                  \n"
+            "    msr psplim, r3                               \n"
+            "    msr control, r4                              \n"
+            "                                                 \n"
+            " restore_general_regs_first_task:                \n"
+            "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
+            "    stmia r2!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
+            "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 restored. */
+            "                                                 \n"
+            " restore_context_done_first_task:                \n"
+            "    str r1, [r0]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
+            "    mov r0, #0                                   \n"
+            "    msr basepri, r0                              \n" /* Ensure that interrupts are enabled when the first task starts. */
+            "    bx lr                                        \n"
+            "                                                 \n"
+            " .align 4                                        \n"
+            " pxCurrentTCBConst2: .word pxCurrentTCB          \n"
+            " xMPUCTRLConst2: .word 0xe000ed94                \n"
+            " xMAIR0Const2: .word 0xe000edc0                  \n"
+            " xRNRConst2: .word 0xe000ed98                    \n"
+            " xRBARConst2: .word 0xe000ed9c                   \n"
+        );
+    }
 
 #else /* configENABLE_MPU */
 
-void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "   .syntax unified                                 \n"
-        "                                                   \n"
-        "   ldr  r2, pxCurrentTCBConst2                     \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr  r1, [r2]                                   \n"/* Read pxCurrentTCB. */
-        "   ldr  r0, [r1]                                   \n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
-        "                                                   \n"
-        "   ldm  r0!, {r1-r2}                               \n"/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
-        "   msr  psplim, r1                                 \n"/* Set this task's PSPLIM value. */
-        "   movs r1, #2                                     \n"/* r1 = 2. */
-        "   msr  CONTROL, r1                                \n"/* Switch to use PSP in the thread mode. */
-        "   adds r0, #32                                    \n"/* Discard everything up to r0. */
-        "   msr  psp, r0                                    \n"/* This is now the new top of stack to use in the task. */
-        "   isb                                             \n"
-        "   mov  r0, #0                                     \n"
-        "   msr  basepri, r0                                \n"/* Ensure that interrupts are enabled when the first task starts. */
-        "   bx   r2                                         \n"/* Finally, branch to EXC_RETURN. */
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "pxCurrentTCBConst2: .word pxCurrentTCB             \n"
-    );
-}
+    void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            "   .syntax unified                                 \n"
+            "                                                   \n"
+            "   ldr  r2, pxCurrentTCBConst2                     \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr  r1, [r2]                                   \n" /* Read pxCurrentTCB. */
+            "   ldr  r0, [r1]                                   \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+            "                                                   \n"
+            "   ldm  r0!, {r1-r2}                               \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
+            "   msr  psplim, r1                                 \n" /* Set this task's PSPLIM value. */
+            "   movs r1, #2                                     \n" /* r1 = 2. */
+            "   msr  CONTROL, r1                                \n" /* Switch to use PSP in the thread mode. */
+            "   adds r0, #32                                    \n" /* Discard everything up to r0. */
+            "   msr  psp, r0                                    \n" /* This is now the new top of stack to use in the task. */
+            "   isb                                             \n"
+            "   mov  r0, #0                                     \n"
+            "   msr  basepri, r0                                \n" /* Ensure that interrupts are enabled when the first task starts. */
+            "   bx   r2                                         \n" /* Finally, branch to EXC_RETURN. */
+            "                                                   \n"
+            "   .align 4                                        \n"
+            "pxCurrentTCBConst2: .word pxCurrentTCB             \n"
+        );
+    }
 
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
@@ -157,12 +157,12 @@ BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs r0, control                                 \n"/* r0 = CONTROL. */
-        "   tst r0, #1                                      \n"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+        "   mrs r0, control                                 \n" /* r0 = CONTROL. */
+        "   tst r0, #1                                      \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
         "   ite ne                                          \n"
-        "   movne r0, #0                                    \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
-        "   moveq r0, #1                                    \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
-        "   bx lr                                           \n"/* Return. */
+        "   movne r0, #0                                    \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+        "   moveq r0, #1                                    \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+        "   bx lr                                           \n" /* Return. */
         "                                                   \n"
         "   .align 4                                        \n"
         ::: "r0", "memory"
@@ -176,10 +176,10 @@ void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs  r0, control                                \n"/* Read the CONTROL register. */
-        "   bic r0, #1                                      \n"/* Clear the bit 0. */
-        "   msr  control, r0                                \n"/* Write back the new CONTROL value. */
-        "   bx lr                                           \n"/* Return to the caller. */
+        "   mrs  r0, control                                \n" /* Read the CONTROL register. */
+        "   bic r0, #1                                      \n" /* Clear the bit 0. */
+        "   msr  control, r0                                \n" /* Write back the new CONTROL value. */
+        "   bx lr                                           \n" /* Return to the caller. */
         ::: "r0", "memory"
     );
 }
@@ -191,10 +191,10 @@ void vResetPrivilege( void ) /* __attribute__ (( naked )) */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs r0, control                                 \n"/* r0 = CONTROL. */
-        "   orr r0, #1                                      \n"/* r0 = r0 | 1. */
-        "   msr control, r0                                 \n"/* CONTROL = r0. */
-        "   bx lr                                           \n"/* Return to the caller. */
+        "   mrs r0, control                                 \n" /* r0 = CONTROL. */
+        "   orr r0, #1                                      \n" /* r0 = r0 | 1. */
+        "   msr control, r0                                 \n" /* CONTROL = r0. */
+        "   bx lr                                           \n" /* Return to the caller. */
         ::: "r0", "memory"
     );
 }
@@ -206,15 +206,15 @@ void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   ldr r0, xVTORConst                              \n"/* Use the NVIC offset register to locate the stack. */
-        "   ldr r0, [r0]                                    \n"/* Read the VTOR register which gives the address of vector table. */
-        "   ldr r0, [r0]                                    \n"/* The first entry in vector table is stack pointer. */
-        "   msr msp, r0                                     \n"/* Set the MSP back to the start of the stack. */
-        "   cpsie i                                         \n"/* Globally enable interrupts. */
+        "   ldr r0, xVTORConst                              \n" /* Use the NVIC offset register to locate the stack. */
+        "   ldr r0, [r0]                                    \n" /* Read the VTOR register which gives the address of vector table. */
+        "   ldr r0, [r0]                                    \n" /* The first entry in vector table is stack pointer. */
+        "   msr msp, r0                                     \n" /* Set the MSP back to the start of the stack. */
+        "   cpsie i                                         \n" /* Globally enable interrupts. */
         "   cpsie f                                         \n"
         "   dsb                                             \n"
         "   isb                                             \n"
-        "   svc %0                                          \n"/* System call to start the first task. */
+        "   svc %0                                          \n" /* System call to start the first task. */
         "   nop                                             \n"
         "                                                   \n"
         "   .align 4                                        \n"
@@ -230,12 +230,12 @@ uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCT
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs r0, basepri                                 \n"/* r0 = basepri. Return original basepri value. */
-        "   mov r1, %0                                      \n"/* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        "   msr basepri, r1                                 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        "   mrs r0, basepri                                 \n" /* r0 = basepri. Return original basepri value. */
+        "   mov r1, %0                                      \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        "   msr basepri, r1                                 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
         "   dsb                                             \n"
         "   isb                                             \n"
-        "   bx lr                                           \n"/* Return. */
+        "   bx lr                                           \n" /* Return. */
         ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
     );
 }
@@ -247,10 +247,10 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   msr basepri, r0                                 \n"/* basepri = ulMask. */
+        "   msr basepri, r0                                 \n" /* basepri = ulMask. */
         "   dsb                                             \n"
         "   isb                                             \n"
-        "   bx lr                                           \n"/* Return. */
+        "   bx lr                                           \n" /* Return. */
         ::: "memory"
     );
 }
@@ -258,246 +258,246 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
 
 #if ( configENABLE_MPU == 1 )
 
-void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        " .syntax unified                                 \n"
-        "                                                 \n"
-        " ldr r2, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        " ldr r0, [r2]                                    \n" /* r0 = pxCurrentTCB. */
-        " ldr r1, [r0]                                    \n" /* r1 = Location in TCB where the context should be saved. */
-        " mrs r2, psp                                     \n" /* r2 = PSP. */
-        "                                                 \n"
-        " save_general_regs:                              \n"
-    #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-        "    add r2, r2, #0x20                            \n" /* Move r2 to location where s0 is saved. */
-        "    tst lr, #0x10                                \n"
-        "    ittt eq                                      \n"
-        "    vstmiaeq r1!, {s16-s31}                      \n" /* Store s16-s31. */
-        "    vldmiaeq r2, {s0-s16}                        \n" /* Copy hardware saved FP context into s0-s16. */
-        "    vstmiaeq r1!, {s0-s16}                       \n" /* Store hardware saved FP context. */
-        "    sub r2, r2, #0x20                            \n" /* Set r2 back to the location of hardware saved context. */
-    #endif /* configENABLE_FPU || configENABLE_MVE */
-        "                                                 \n"
-        "    stmia r1!, {r4-r11}                          \n" /* Store r4-r11. */
-        "    ldmia r2, {r4-r11}                           \n" /* Copy the hardware saved context into r4-r11. */
-        "    stmia r1!, {r4-r11}                          \n" /* Store the hardware saved context. */
-        "                                                 \n"
-        " save_special_regs:                              \n"
-        "    mrs r3, psplim                               \n" /* r3 = PSPLIM. */
-        "    mrs r4, control                              \n" /* r4 = CONTROL. */
-        "    stmia r1!, {r2-r4, lr}                       \n" /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
-        "    str r1, [r0]                                 \n" /* Save the location from where the context should be restored as the first member of TCB. */
-        "                                                 \n"
-        " select_next_task:                               \n"
-        "    mov r0, %0                                   \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
-        "    msr basepri, r0                              \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        "    dsb                                          \n"
-        "    isb                                          \n"
-        "    bl vTaskSwitchContext                        \n"
-        "    mov r0, #0                                   \n" /* r0 = 0. */
-        "    msr basepri, r0                              \n" /* Enable interrupts. */
-        "                                                 \n"
-        " program_mpu:                                    \n"
-        "    ldr r2, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB. */
-        "                                                 \n"
-        "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-        "    ldr r1, xMPUCTRLConst                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
-        "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
-        "    str r2, [r1]                                 \n" /* Disable MPU. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
-        "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-        "    ldr r2, xMAIR0Const                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-        "    str r1, [r2]                                 \n" /* Program MAIR0. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-        "    ldr r1, xRNRConst                            \n" /* r1 = 0xe000ed98 [Location of RNR]. */
-        "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "                                                 \n"
-        "    movs r3, #4                                  \n" /* r3 = 4. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 4. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-        "                                                 \n"
-    #if ( configTOTAL_MPU_REGIONS == 16 )
-        "    movs r3, #8                                  \n" /* r3 = 8. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 8. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-        "    movs r3, #12                                 \n" /* r3 = 12. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 12. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-    #endif /* configTOTAL_MPU_REGIONS == 16 */
-        "                                                 \n"
-        "   ldr r1, xMPUCTRLConst                         \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
-        "   orr r2, #1                                    \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
-        "   str r2, [r1]                                  \n" /* Enable MPU. */
-        "   dsb                                           \n" /* Force memory writes before continuing. */
-        "                                                 \n"
-        " restore_context:                                \n"
-        "    ldr r2, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB.*/
-        "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
-        "                                                 \n"
-        " restore_special_regs:                           \n"
-        "    ldmdb r1!, {r2-r4, lr}                       \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
-        "    msr psp, r2                                  \n"
-        "    msr psplim, r3                               \n"
-        "    msr control, r4                              \n"
-        "                                                 \n"
-        " restore_general_regs:                           \n"
-        "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
-        "    stmia r2!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
-        "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 restored. */
-    #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-        "    tst lr, #0x10                                \n"
-        "    ittt eq                                      \n"
-        "    vldmdbeq r1!, {s0-s16}                       \n" /* s0-s16 contain hardware saved FP context. */
-        "    vstmiaeq r2!, {s0-s16}                       \n" /* Copy hardware saved FP context on the task stack. */
-        "    vldmdbeq r1!, {s16-s31}                      \n" /* Restore s16-s31. */
-    #endif /* configENABLE_FPU || configENABLE_MVE */
-        "                                                 \n"
-        " restore_context_done:                           \n"
-        "    str r1, [r0]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
-        "    bx lr                                        \n"
-        "                                                 \n"
-        " .align 4                                        \n"
-        " pxCurrentTCBConst: .word pxCurrentTCB           \n"
-        " xMPUCTRLConst: .word 0xe000ed94                 \n"
-        " xMAIR0Const: .word 0xe000edc0                   \n"
-        " xRNRConst: .word 0xe000ed98                     \n"
-        " xRBARConst: .word 0xe000ed9c                    \n"
-        ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
-    );
-}
+    void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                 \n"
+            "                                                 \n"
+            " ldr r2, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            " ldr r0, [r2]                                    \n" /* r0 = pxCurrentTCB. */
+            " ldr r1, [r0]                                    \n" /* r1 = Location in TCB where the context should be saved. */
+            " mrs r2, psp                                     \n" /* r2 = PSP. */
+            "                                                 \n"
+            " save_general_regs:                              \n"
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+                "    add r2, r2, #0x20                            \n" /* Move r2 to location where s0 is saved. */
+                "    tst lr, #0x10                                \n"
+                "    ittt eq                                      \n"
+                "    vstmiaeq r1!, {s16-s31}                      \n" /* Store s16-s31. */
+                "    vldmiaeq r2, {s0-s16}                        \n" /* Copy hardware saved FP context into s0-s16. */
+                "    vstmiaeq r1!, {s0-s16}                       \n" /* Store hardware saved FP context. */
+                "    sub r2, r2, #0x20                            \n" /* Set r2 back to the location of hardware saved context. */
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+            "                                                 \n"
+            "    stmia r1!, {r4-r11}                          \n" /* Store r4-r11. */
+            "    ldmia r2, {r4-r11}                           \n" /* Copy the hardware saved context into r4-r11. */
+            "    stmia r1!, {r4-r11}                          \n" /* Store the hardware saved context. */
+            "                                                 \n"
+            " save_special_regs:                              \n"
+            "    mrs r3, psplim                               \n" /* r3 = PSPLIM. */
+            "    mrs r4, control                              \n" /* r4 = CONTROL. */
+            "    stmia r1!, {r2-r4, lr}                       \n" /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
+            "    str r1, [r0]                                 \n" /* Save the location from where the context should be restored as the first member of TCB. */
+            "                                                 \n"
+            " select_next_task:                               \n"
+            "    mov r0, %0                                   \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
+            "    msr basepri, r0                              \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+            "    dsb                                          \n"
+            "    isb                                          \n"
+            "    bl vTaskSwitchContext                        \n"
+            "    mov r0, #0                                   \n" /* r0 = 0. */
+            "    msr basepri, r0                              \n" /* Enable interrupts. */
+            "                                                 \n"
+            " program_mpu:                                    \n"
+            "    ldr r2, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB. */
+            "                                                 \n"
+            "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
+            "    ldr r1, xMPUCTRLConst                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
+            "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
+            "    str r2, [r1]                                 \n" /* Disable MPU. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
+            "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
+            "    ldr r2, xMAIR0Const                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    str r1, [r2]                                 \n" /* Program MAIR0. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
+            "    ldr r1, xRNRConst                            \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "                                                 \n"
+            "    movs r3, #4                                  \n" /* r3 = 4. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 4. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "                                                 \n"
+            #if ( configTOTAL_MPU_REGIONS == 16 )
+                "    movs r3, #8                                  \n" /* r3 = 8. */
+                "    str r3, [r1]                                 \n" /* Program RNR = 8. */
+                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+                "    movs r3, #12                                 \n" /* r3 = 12. */
+                "    str r3, [r1]                                 \n" /* Program RNR = 12. */
+                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            #endif /* configTOTAL_MPU_REGIONS == 16 */
+            "                                                 \n"
+            "   ldr r1, xMPUCTRLConst                         \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
+            "   orr r2, #1                                    \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
+            "   str r2, [r1]                                  \n" /* Enable MPU. */
+            "   dsb                                           \n" /* Force memory writes before continuing. */
+            "                                                 \n"
+            " restore_context:                                \n"
+            "    ldr r2, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB.*/
+            "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
+            "                                                 \n"
+            " restore_special_regs:                           \n"
+            "    ldmdb r1!, {r2-r4, lr}                       \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
+            "    msr psp, r2                                  \n"
+            "    msr psplim, r3                               \n"
+            "    msr control, r4                              \n"
+            "                                                 \n"
+            " restore_general_regs:                           \n"
+            "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
+            "    stmia r2!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
+            "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 restored. */
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+                "    tst lr, #0x10                                \n"
+                "    ittt eq                                      \n"
+                "    vldmdbeq r1!, {s0-s16}                       \n" /* s0-s16 contain hardware saved FP context. */
+                "    vstmiaeq r2!, {s0-s16}                       \n" /* Copy hardware saved FP context on the task stack. */
+                "    vldmdbeq r1!, {s16-s31}                      \n" /* Restore s16-s31. */
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+            "                                                 \n"
+            " restore_context_done:                           \n"
+            "    str r1, [r0]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
+            "    bx lr                                        \n"
+            "                                                 \n"
+            " .align 4                                        \n"
+            " pxCurrentTCBConst: .word pxCurrentTCB           \n"
+            " xMPUCTRLConst: .word 0xe000ed94                 \n"
+            " xMAIR0Const: .word 0xe000edc0                   \n"
+            " xRNRConst: .word 0xe000ed98                     \n"
+            " xRBARConst: .word 0xe000ed9c                    \n"
+            ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+        );
+    }
 
 #else /* configENABLE_MPU */
 
-void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "   .syntax unified                                 \n"
-        "                                                   \n"
-        "   mrs r0, psp                                     \n"/* Read PSP in r0. */
-        "                                                   \n"
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-            "   tst lr, #0x10                                   \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
-            "   it eq                                           \n"
-            "   vstmdbeq r0!, {s16-s31}                         \n"/* Store the additional FP context registers which are not saved automatically. */
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-        "                                                   \n"
-        "   mrs r2, psplim                                  \n"/* r2 = PSPLIM. */
-        "   mov r3, lr                                      \n"/* r3 = LR/EXC_RETURN. */
-        "   stmdb r0!, {r2-r11}                             \n"/* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */
-        "                                                   \n"
-        "   ldr r2, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r2]                                    \n"/* Read pxCurrentTCB. */
-        "   str r0, [r1]                                    \n"/* Save the new top of stack in TCB. */
-        "                                                   \n"
-        "   mov r0, %0                                      \n"/* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
-        "   msr basepri, r0                                 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        "   dsb                                             \n"
-        "   isb                                             \n"
-        "   bl vTaskSwitchContext                           \n"
-        "   mov r0, #0                                      \n"/* r0 = 0. */
-        "   msr basepri, r0                                 \n"/* Enable interrupts. */
-        "                                                   \n"
-        "   ldr r2, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r2]                                    \n"/* Read pxCurrentTCB. */
-        "   ldr r0, [r1]                                    \n"/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
-        "                                                   \n"
-        "   ldmia r0!, {r2-r11}                             \n"/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
-        "                                                   \n"
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-            "   tst r3, #0x10                                   \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
-            "   it eq                                           \n"
-            "   vldmiaeq r0!, {s16-s31}                         \n"/* Restore the additional FP context registers which are not restored automatically. */
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-        "                                                   \n"
-        "   msr psplim, r2                                  \n"/* Restore the PSPLIM register value for the task. */
-        "   msr psp, r0                                     \n"/* Remember the new top of stack for the task. */
-        "   bx r3                                           \n"
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "pxCurrentTCBConst: .word pxCurrentTCB              \n"
-        ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
-    );
-}
+    void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            "   .syntax unified                                 \n"
+            "                                                   \n"
+            "   mrs r0, psp                                     \n" /* Read PSP in r0. */
+            "                                                   \n"
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+                "   tst lr, #0x10                                   \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+                "   it eq                                           \n"
+                "   vstmdbeq r0!, {s16-s31}                         \n" /* Store the additional FP context registers which are not saved automatically. */
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+            "                                                   \n"
+            "   mrs r2, psplim                                  \n" /* r2 = PSPLIM. */
+            "   mov r3, lr                                      \n" /* r3 = LR/EXC_RETURN. */
+            "   stmdb r0!, {r2-r11}                             \n" /* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */
+            "                                                   \n"
+            "   ldr r2, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r1, [r2]                                    \n" /* Read pxCurrentTCB. */
+            "   str r0, [r1]                                    \n" /* Save the new top of stack in TCB. */
+            "                                                   \n"
+            "   mov r0, %0                                      \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
+            "   msr basepri, r0                                 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+            "   dsb                                             \n"
+            "   isb                                             \n"
+            "   bl vTaskSwitchContext                           \n"
+            "   mov r0, #0                                      \n" /* r0 = 0. */
+            "   msr basepri, r0                                 \n" /* Enable interrupts. */
+            "                                                   \n"
+            "   ldr r2, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r1, [r2]                                    \n" /* Read pxCurrentTCB. */
+            "   ldr r0, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
+            "                                                   \n"
+            "   ldmia r0!, {r2-r11}                             \n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
+            "                                                   \n"
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+                "   tst r3, #0x10                                   \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+                "   it eq                                           \n"
+                "   vldmiaeq r0!, {s16-s31}                         \n" /* Restore the additional FP context registers which are not restored automatically. */
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+            "                                                   \n"
+            "   msr psplim, r2                                  \n" /* Restore the PSPLIM register value for the task. */
+            "   msr psp, r0                                     \n" /* Remember the new top of stack for the task. */
+            "   bx r3                                           \n"
+            "                                                   \n"
+            "   .align 4                                        \n"
+            "pxCurrentTCBConst: .word pxCurrentTCB              \n"
+            ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+        );
+    }
 
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-   __asm volatile
-    (
-        ".syntax unified                \n"
-        ".extern vPortSVCHandler_C      \n"
-        ".extern vSystemCallEnter       \n"
-        ".extern vSystemCallEnter_1     \n"
-        ".extern vSystemCallExit        \n"
-        "                               \n"
-        "tst lr, #4                     \n"
-        "ite eq                         \n"
-        "mrseq r0, msp                  \n"
-        "mrsne r0, psp                  \n"
-        "                               \n"
-        "ldr r1, [r0, #24]              \n"
-        "ldrb r2, [r1, #-2]             \n"
-        "cmp r2, %0                     \n"
-        "beq syscall_enter              \n"
-        "cmp r2, %1                     \n"
-        "beq syscall_enter_1            \n"
-        "cmp r2, %2                     \n"
-        "beq syscall_exit               \n"
-        "b vPortSVCHandler_C            \n"
-        "                               \n"
-        "syscall_enter:                 \n"
-        "    mov r1, lr                 \n"
-        "    b vSystemCallEnter         \n"
-        "                               \n"
-        "syscall_enter_1:               \n"
-        "    mov r1, lr                 \n"
-        "    b vSystemCallEnter_1       \n"
-        "                               \n"
-        "syscall_exit:                  \n"
-        "    mov r1, lr                 \n"
-        "    b vSystemCallExit          \n"
-        "                               \n"
-        : /* No outputs. */
-        :"i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT )
-        : "r0", "r1", "r2", "memory"
-    );
-}
+    void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            ".syntax unified                \n"
+            ".extern vPortSVCHandler_C      \n"
+            ".extern vSystemCallEnter       \n"
+            ".extern vSystemCallEnter_1     \n"
+            ".extern vSystemCallExit        \n"
+            "                               \n"
+            "tst lr, #4                     \n"
+            "ite eq                         \n"
+            "mrseq r0, msp                  \n"
+            "mrsne r0, psp                  \n"
+            "                               \n"
+            "ldr r1, [r0, #24]              \n"
+            "ldrb r2, [r1, #-2]             \n"
+            "cmp r2, %0                     \n"
+            "beq syscall_enter              \n"
+            "cmp r2, %1                     \n"
+            "beq syscall_enter_1            \n"
+            "cmp r2, %2                     \n"
+            "beq syscall_exit               \n"
+            "b vPortSVCHandler_C            \n"
+            "                               \n"
+            "syscall_enter:                 \n"
+            "    mov r1, lr                 \n"
+            "    b vSystemCallEnter         \n"
+            "                               \n"
+            "syscall_enter_1:               \n"
+            "    mov r1, lr                 \n"
+            "    b vSystemCallEnter_1       \n"
+            "                               \n"
+            "syscall_exit:                  \n"
+            "    mov r1, lr                 \n"
+            "    b vSystemCallExit          \n"
+            "                               \n"
+            : /* No outputs. */
+            : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT )
+            : "r0", "r1", "r2", "memory"
+        );
+    }
 
 #else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
-void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "   .syntax unified                                 \n"
-        "                                                   \n"
-        "   tst lr, #4                                      \n"
-        "   ite eq                                          \n"
-        "   mrseq r0, msp                                   \n"
-        "   mrsne r0, psp                                   \n"
-        "   ldr r1, svchandler_address_const                \n"
-        "   bx r1                                           \n"
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "svchandler_address_const: .word vPortSVCHandler_C  \n"
-    );
-}
+    void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            "   .syntax unified                                 \n"
+            "                                                   \n"
+            "   tst lr, #4                                      \n"
+            "   ite eq                                          \n"
+            "   mrseq r0, msp                                   \n"
+            "   mrsne r0, psp                                   \n"
+            "   ldr r1, svchandler_address_const                \n"
+            "   bx r1                                           \n"
+            "                                                   \n"
+            "   .align 4                                        \n"
+            "svchandler_address_const: .word vPortSVCHandler_C  \n"
+        );
+    }
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/portmacro.h b/portable/GCC/ARM_CM55_NTZ/non_secure/portmacro.h
index cce022882..7b011b5b5 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/portmacro.h
@@ -53,9 +53,9 @@
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME                       "Cortex-M55"
-#define portHAS_ARMV8M_MAIN_EXTENSION       1
-#define portDONT_DISCARD                    __attribute__( ( used ) )
+#define portARCH_NAME                    "Cortex-M55"
+#define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
 /* ARMv8-M common port configurations. */
@@ -65,8 +65,8 @@
 /**
  * @brief Critical section management.
  */
-#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()
-#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )
+#define portDISABLE_INTERRUPTS()    ulSetInterruptMask()
+#define portENABLE_INTERRUPTS()     vClearInterruptMask( 0 )
 /*-----------------------------------------------------------*/
 
 /* *INDENT-OFF* */
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h
index e5ffdb48b..62e462a27 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h
@@ -81,8 +81,8 @@ typedef unsigned long    UBaseType_t;
     typedef uint32_t     TickType_t;
     #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-     * not need to be guarded with a critical section. */
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
     #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -117,7 +117,7 @@ extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGE
 extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
 
 #if ( configENABLE_TRUSTZONE == 1 )
-    extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize );     /* __attribute__ (( naked )) */
+    extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
     extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
 #endif /* configENABLE_TRUSTZONE */
 
@@ -188,13 +188,13 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Settings to define an MPU region.
-     */
+/**
+ * @brief Settings to define an MPU region.
+ */
     typedef struct MPURegionSettings
     {
-        uint32_t ulRBAR;     /**< RBAR for the region. */
-        uint32_t ulRLAR;     /**< RLAR for the region. */
+        uint32_t ulRBAR; /**< RBAR for the region. */
+        uint32_t ulRLAR; /**< RLAR for the region. */
     } MPURegionSettings_t;
 
     #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
@@ -203,9 +203,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-        /**
-         * @brief System call stack.
-         */
+/**
+ * @brief System call stack.
+ */
         typedef struct SYSTEM_CALL_STACK_INFO
         {
             uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ];
@@ -218,74 +218,74 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
-    /**
-     * @brief MPU settings as stored in the TCB.
-     */
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
     #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
 
-        #if( configENABLE_TRUSTZONE == 1 )
+        #if ( configENABLE_TRUSTZONE == 1 )
 
-            /*
-             * +-----------+---------------+----------+-----------------+------------------------------+-----+
-             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
-             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
-             * +-----------+---------------+----------+-----------------+------------------------------+-----+
-             *
-             * <-----------><--------------><---------><----------------><-----------------------------><---->
-             *      16             16            8               8                     5                   1
-             */
-            #define MAX_CONTEXT_SIZE 54
+/*
+ * +-----------+---------------+----------+-----------------+------------------------------+-----+
+ * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+ * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+ * +-----------+---------------+----------+-----------------+------------------------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><-----------------------------><---->
+ *      16             16            8               8                     5                   1
+ */
+            #define MAX_CONTEXT_SIZE    54
 
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-            /*
-             * +-----------+---------------+----------+-----------------+----------------------+-----+
-             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
-             * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
-             * +-----------+---------------+----------+-----------------+----------------------+-----+
-             *
-             * <-----------><--------------><---------><----------------><---------------------><---->
-             *      16             16            8               8                  4              1
-             */
-            #define MAX_CONTEXT_SIZE 53
+/*
+ * +-----------+---------------+----------+-----------------+----------------------+-----+
+ * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+ * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
+ * +-----------+---------------+----------+-----------------+----------------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><---------------------><---->
+ *      16             16            8               8                  4              1
+ */
+            #define MAX_CONTEXT_SIZE    53
 
         #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
 
     #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-        #if( configENABLE_TRUSTZONE == 1 )
+        #if ( configENABLE_TRUSTZONE == 1 )
 
-            /*
-             * +----------+-----------------+------------------------------+-----+
-             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
-             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
-             * +----------+-----------------+------------------------------+-----+
-             *
-             * <---------><----------------><------------------------------><---->
-             *     8               8                      5                   1
-             */
-            #define MAX_CONTEXT_SIZE 22
+/*
+ * +----------+-----------------+------------------------------+-----+
+ * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+ * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+ * +----------+-----------------+------------------------------+-----+
+ *
+ * <---------><----------------><------------------------------><---->
+ *     8               8                      5                   1
+ */
+            #define MAX_CONTEXT_SIZE    22
 
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-            /*
-             * +----------+-----------------+----------------------+-----+
-             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
-             * |          | PC, xPSR        | EXC_RETURN           |     |
-             * +----------+-----------------+----------------------+-----+
-             *
-             * <---------><----------------><----------------------><---->
-             *     8               8                  4              1
-             */
-            #define MAX_CONTEXT_SIZE 21
+/*
+ * +----------+-----------------+----------------------+-----+
+ * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+ * |          | PC, xPSR        | EXC_RETURN           |     |
+ * +----------+-----------------+----------------------+-----+
+ *
+ * <---------><----------------><----------------------><---->
+ *     8               8                  4              1
+ */
+            #define MAX_CONTEXT_SIZE    21
 
         #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
 
     #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-    /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
-    #define portSTACK_FRAME_HAS_PADDING_FLAG     ( 1UL << 0UL )
-    #define portTASK_IS_PRIVILEGED_FLAG          ( 1UL << 1UL )
+/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
+    #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
+    #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
     typedef struct MPU_SETTINGS
     {
@@ -364,49 +364,49 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-    /**
-     * @brief Allocate a secure context for the task.
-     *
-     * Tasks are not created with a secure context. Any task that is going to call
-     * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
-     * secure context before it calls any secure function.
-     *
-     * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
-     */
+/**
+ * @brief Allocate a secure context for the task.
+ *
+ * Tasks are not created with a secure context. Any task that is going to call
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+ * secure context before it calls any secure function.
+ *
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+ */
     #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
 
-    /**
-     * @brief Called when a task is deleted to delete the task's secure context,
-     * if it has one.
-     *
-     * @param[in] pxTCB The TCB of the task being deleted.
-     */
+/**
+ * @brief Called when a task is deleted to delete the task's secure context,
+ * if it has one.
+ *
+ * @param[in] pxTCB The TCB of the task being deleted.
+ */
     #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
 #endif /* configENABLE_TRUSTZONE */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Checks whether or not the processor is privileged.
-     *
-     * @return 1 if the processor is already privileged, 0 otherwise.
-     */
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
     #define portIS_PRIVILEGED()      xIsPrivileged()
 
-    /**
-     * @brief Raise an SVC request to raise privilege.
-     *
-     * The SVC handler checks that the SVC was raised from a system call and only
-     * then it raises the privilege. If this is called from any other place,
-     * the privilege is not raised.
-     */
+/**
+ * @brief Raise an SVC request to raise privilege.
+ *
+ * The SVC handler checks that the SVC was raised from a system call and only
+ * then it raises the privilege. If this is called from any other place,
+ * the privilege is not raised.
+ */
     #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
 
-    /**
-     * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
-     * register.
-     */
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
     #define portRESET_PRIVILEGE()    vResetPrivilege()
 #else
     #define portIS_PRIVILEGED()
@@ -419,12 +419,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     extern BaseType_t xPortIsTaskPrivileged( void );
 
-    /**
-     * @brief Checks whether or not the calling task is privileged.
-     *
-     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
-     */
-    #define portIS_TASK_PRIVILEGED()      xPortIsTaskPrivileged()
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
+    #define portIS_TASK_PRIVILEGED()    xPortIsTaskPrivileged()
 
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
@@ -439,9 +439,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * based on whether or not Mainline extension is implemented. */
 #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
     #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
-        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
     #else
-        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    0
     #endif
 #endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
 
@@ -450,9 +450,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  */
 #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
 
-    /**
-     * @brief Count the number of leading zeros in a 32-bit value.
-     */
+/**
+ * @brief Count the number of leading zeros in a 32-bit value.
+ */
     static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
     {
         uint32_t ulReturn;
@@ -462,7 +462,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         return ulReturn;
     }
 
-    /* Check the configuration. */
+/* Check the configuration. */
     #if ( configMAX_PRIORITIES > 32 )
         #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
     #endif
@@ -471,16 +471,16 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection.  Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
     #endif
 
-    /**
-     * @brief Store/clear the ready priorities in a bit map.
-     */
-    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+/**
+ * @brief Store/clear the ready priorities in a bit map.
+ */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )      ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )       ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 
-    /**
-     * @brief Get the priority of the highest-priority task that is ready to execute.
-     */
-    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )   uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+/**
+ * @brief Get the priority of the highest-priority task that is ready to execute.
+ */
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
 
 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM7/r0p1/port.c b/portable/GCC/ARM_CM7/r0p1/port.c
old mode 100755
new mode 100644
index aab077d76..ccaaf884e
--- a/portable/GCC/ARM_CM7/r0p1/port.c
+++ b/portable/GCC/ARM_CM7/r0p1/port.c
@@ -339,22 +339,22 @@ BaseType_t xPortStartScheduler( void )
         if( ulImplementedPrioBits == 8 )
         {
             /* When the hardware implements 8 priority bits, there is no way for
-            * the software to configure PRIGROUP to not have sub-priorities. As
-            * a result, the least significant bit is always used for sub-priority
-            * and there are 128 preemption priorities and 2 sub-priorities.
-            *
-            * This may cause some confusion in some cases - for example, if
-            * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
-            * priority interrupts will be masked in Critical Sections as those
-            * are at the same preemption priority. This may appear confusing as
-            * 4 is higher (numerically lower) priority than
-            * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
-            * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
-            * to 4, this confusion does not happen and the behaviour remains the same.
-            *
-            * The following assert ensures that the sub-priority bit in the
-            * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
-            * confusion. */
+             * the software to configure PRIGROUP to not have sub-priorities. As
+             * a result, the least significant bit is always used for sub-priority
+             * and there are 128 preemption priorities and 2 sub-priorities.
+             *
+             * This may cause some confusion in some cases - for example, if
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
+             * priority interrupts will be masked in Critical Sections as those
+             * are at the same preemption priority. This may appear confusing as
+             * 4 is higher (numerically lower) priority than
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
+             * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
+             * to 4, this confusion does not happen and the behaviour remains the same.
+             *
+             * The following assert ensures that the sub-priority bit in the
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
+             * confusion. */
             configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
             ulMaxPRIGROUPValue = 0;
         }
diff --git a/portable/GCC/ARM_CM7/r0p1/portmacro.h b/portable/GCC/ARM_CM7/r0p1/portmacro.h
index f433beb52..96d5e3579 100644
--- a/portable/GCC/ARM_CM7/r0p1/portmacro.h
+++ b/portable/GCC/ARM_CM7/r0p1/portmacro.h
@@ -28,7 +28,7 @@
 
 
 #ifndef PORTMACRO_H
-    #define PORTMACRO_H
+#define PORTMACRO_H
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
@@ -47,42 +47,42 @@
  */
 
 /* Type definitions. */
-    #define portCHAR          char
-    #define portFLOAT         float
-    #define portDOUBLE        double
-    #define portLONG          long
-    #define portSHORT         short
-    #define portSTACK_TYPE    uint32_t
-    #define portBASE_TYPE     long
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-    typedef portSTACK_TYPE   StackType_t;
-    typedef long             BaseType_t;
-    typedef unsigned long    UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
-    #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-        typedef uint16_t     TickType_t;
-        #define portMAX_DELAY              ( TickType_t ) 0xffff
-    #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-        typedef uint32_t     TickType_t;
-        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
  * not need to be guarded with a critical section. */
-        #define portTICK_TYPE_IS_ATOMIC    1
-    #else
-        #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
-    #endif
+    #define portTICK_TYPE_IS_ATOMIC    1
+#else
+    #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+#endif
 /*-----------------------------------------------------------*/
 
 /* Architecture specifics. */
-    #define portSTACK_GROWTH      ( -1 )
-    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-    #define portBYTE_ALIGNMENT    8
-    #define portDONT_DISCARD      __attribute__( ( used ) )
+#define portSTACK_GROWTH      ( -1 )
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT    8
+#define portDONT_DISCARD      __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
 /* Scheduler utilities. */
-    #define portYIELD()                                 \
+#define portYIELD()                                     \
     {                                                   \
         /* Set a PendSV to request a context switch. */ \
         portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
@@ -93,158 +93,158 @@
         __asm volatile ( "isb" );                                  \
     }
 
-    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
-    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-    #define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 )
-    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+#define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired != pdFALSE ) portYIELD( ); } while( 0 )
+#define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
 /* Critical section management. */
-    extern void vPortEnterCritical( void );
-    extern void vPortExitCritical( void );
-    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulPortRaiseBASEPRI()
-    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vPortSetBASEPRI( x )
-    #define portDISABLE_INTERRUPTS()                  vPortRaiseBASEPRI()
-    #define portENABLE_INTERRUPTS()                   vPortSetBASEPRI( 0 )
-    #define portENTER_CRITICAL()                      vPortEnterCritical()
-    #define portEXIT_CRITICAL()                       vPortExitCritical()
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+#define portSET_INTERRUPT_MASK_FROM_ISR()         ulPortRaiseBASEPRI()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vPortSetBASEPRI( x )
+#define portDISABLE_INTERRUPTS()                  vPortRaiseBASEPRI()
+#define portENABLE_INTERRUPTS()                   vPortSetBASEPRI( 0 )
+#define portENTER_CRITICAL()                      vPortEnterCritical()
+#define portEXIT_CRITICAL()                       vPortExitCritical()
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site.  These are
  * not necessary for to use this port.  They are defined so the common demo files
  * (which build with all the ports) will build. */
-    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
-    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 /*-----------------------------------------------------------*/
 
 /* Tickless idle/low power functionality. */
-    #ifndef portSUPPRESS_TICKS_AND_SLEEP
-        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
-        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
-    #endif
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+    extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+    #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
 /*-----------------------------------------------------------*/
 
 /* Architecture specific optimisations. */
-    #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
-    #endif
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+    #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
+#endif
 
-    #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
 
 /* Generic helper function. */
-        __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
-        {
-            uint8_t ucReturn;
+    __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
+    {
+        uint8_t ucReturn;
 
-            __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
+        __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
 
-            return ucReturn;
-        }
+        return ucReturn;
+    }
 
 /* Check the configuration. */
-        #if ( configMAX_PRIORITIES > 32 )
-            #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
-        #endif
+    #if ( configMAX_PRIORITIES > 32 )
+        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+    #endif
 
 /* Store/clear the ready priorities in a bit map. */
-        #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-        #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 
 /*-----------------------------------------------------------*/
 
-        #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
 
-    #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 
 /*-----------------------------------------------------------*/
 
-    #ifdef configASSERT
-        void vPortValidateInterruptPriority( void );
-        #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
-    #endif
+#ifdef configASSERT
+    void vPortValidateInterruptPriority( void );
+    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
+#endif
 
 /* portNOP() is not required by this port. */
-    #define portNOP()
+#define portNOP()
 
-    #define portINLINE              __inline
+#define portINLINE              __inline
 
-    #ifndef portFORCE_INLINE
-        #define portFORCE_INLINE    inline __attribute__( ( always_inline ) )
-    #endif
+#ifndef portFORCE_INLINE
+    #define portFORCE_INLINE    inline __attribute__( ( always_inline ) )
+#endif
 
-    portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
+portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
+{
+    uint32_t ulCurrentInterrupt;
+    BaseType_t xReturn;
+
+    /* Obtain the number of the currently executing interrupt. */
+    __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+    if( ulCurrentInterrupt == 0 )
     {
-        uint32_t ulCurrentInterrupt;
-        BaseType_t xReturn;
-
-        /* Obtain the number of the currently executing interrupt. */
-        __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
-
-        if( ulCurrentInterrupt == 0 )
-        {
-            xReturn = pdFALSE;
-        }
-        else
-        {
-            xReturn = pdTRUE;
-        }
-
-        return xReturn;
+        xReturn = pdFALSE;
     }
+    else
+    {
+        xReturn = pdTRUE;
+    }
+
+    return xReturn;
+}
 
 /*-----------------------------------------------------------*/
 
-    portFORCE_INLINE static void vPortRaiseBASEPRI( void )
-    {
-        uint32_t ulNewBASEPRI;
+portFORCE_INLINE static void vPortRaiseBASEPRI( void )
+{
+    uint32_t ulNewBASEPRI;
 
-        __asm volatile
-        (
-            "   mov %0, %1                                              \n"\
-            "   cpsid i                                                 \n"\
-            "   msr basepri, %0                                         \n"\
-            "   isb                                                     \n"\
-            "   dsb                                                     \n"\
-            "   cpsie i                                                 \n"\
-            : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
-        );
-    }
+    __asm volatile
+    (
+        "   mov %0, %1                                              \n" \
+        "   cpsid i                                                 \n" \
+        "   msr basepri, %0                                         \n" \
+        "   isb                                                     \n" \
+        "   dsb                                                     \n" \
+        "   cpsie i                                                 \n" \
+        : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+    );
+}
 
 /*-----------------------------------------------------------*/
 
-    portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
-    {
-        uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
+portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
+{
+    uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
 
-        __asm volatile
-        (
-            "   mrs %0, basepri                                         \n"\
-            "   mov %1, %2                                              \n"\
-            "   cpsid i                                                 \n"\
-            "   msr basepri, %1                                         \n"\
-            "   isb                                                     \n"\
-            "   dsb                                                     \n"\
-            "   cpsie i                                                 \n"\
-            : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
-        );
+    __asm volatile
+    (
+        "   mrs %0, basepri                                         \n" \
+        "   mov %1, %2                                              \n" \
+        "   cpsid i                                                 \n" \
+        "   msr basepri, %1                                         \n" \
+        "   isb                                                     \n" \
+        "   dsb                                                     \n" \
+        "   cpsie i                                                 \n" \
+        : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+    );
 
-        /* This return will not be reached but is necessary to prevent compiler
-         * warnings. */
-        return ulOriginalBASEPRI;
-    }
+    /* This return will not be reached but is necessary to prevent compiler
+     * warnings. */
+    return ulOriginalBASEPRI;
+}
 /*-----------------------------------------------------------*/
 
-    portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
-    {
-        __asm volatile
-        (
-            "   msr basepri, %0 "::"r" ( ulNewMaskValue ) : "memory"
-        );
-    }
+portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
+{
+    __asm volatile
+    (
+        "   msr basepri, %0 " ::"r" ( ulNewMaskValue ) : "memory"
+    );
+}
 /*-----------------------------------------------------------*/
 
-    #define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
+#define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/GCC/ARM_CM85/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM85/non_secure/mpu_wrappers_v2_asm.c
index 2d1218a95..d1fbdc0e5 100644
--- a/portable/GCC/ARM_CM85/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM85/non_secure/mpu_wrappers_v2_asm.c
@@ -44,2274 +44,2274 @@
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-#if ( INCLUDE_xTaskDelayUntil == 1 )
+    #if ( INCLUDE_xTaskDelayUntil == 1 )
 
-BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
-                                const TickType_t xTimeIncrement ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
+                                        const TickType_t xTimeIncrement ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
-                                const TickType_t xTimeIncrement ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskDelayUntilImpl                       \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskDelayUntil_Unpriv                        \n"
-        " MPU_xTaskDelayUntil_Priv:                             \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskDelayUntilImpl                         \n"
-        " MPU_xTaskDelayUntil_Unpriv:                           \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskDelayUntilImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
+                                        const TickType_t xTimeIncrement ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskDelayUntilImpl                       \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskDelayUntil_Unpriv                        \n"
+                " MPU_xTaskDelayUntil_Priv:                             \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskDelayUntilImpl                         \n"
+                " MPU_xTaskDelayUntil_Unpriv:                           \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskDelayUntilImpl                        \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */
+    #endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_xTaskAbortDelay == 1 )
+    #if ( INCLUDE_xTaskAbortDelay == 1 )
 
-BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskAbortDelayImpl                       \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskAbortDelay_Unpriv                        \n"
-        " MPU_xTaskAbortDelay_Priv:                             \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskAbortDelayImpl                         \n"
-        " MPU_xTaskAbortDelay_Unpriv:                           \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskAbortDelayImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskAbortDelayImpl                       \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskAbortDelay_Unpriv                        \n"
+                " MPU_xTaskAbortDelay_Priv:                             \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskAbortDelayImpl                         \n"
+                " MPU_xTaskAbortDelay_Unpriv:                           \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskAbortDelayImpl                        \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */
+    #endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_vTaskDelay == 1 )
+    #if ( INCLUDE_vTaskDelay == 1 )
 
-void MPU_vTaskDelay( const TickType_t xTicksToDelay ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskDelay( const TickType_t xTicksToDelay ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskDelayImpl                            \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskDelay_Unpriv                             \n"
-        " MPU_vTaskDelay_Priv:                                  \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskDelayImpl                              \n"
-        " MPU_vTaskDelay_Unpriv:                                \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskDelayImpl                             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskDelayImpl                            \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskDelay_Unpriv                             \n"
+                " MPU_vTaskDelay_Priv:                                  \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskDelayImpl                              \n"
+                " MPU_vTaskDelay_Unpriv:                                \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskDelayImpl                             \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_vTaskDelay == 1 ) */
+    #endif /* if ( INCLUDE_vTaskDelay == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_uxTaskPriorityGet == 1 )
+    #if ( INCLUDE_uxTaskPriorityGet == 1 )
 
-UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskPriorityGetImpl                     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTaskPriorityGet_Unpriv                      \n"
-        " MPU_uxTaskPriorityGet_Priv:                           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTaskPriorityGetImpl                       \n"
-        " MPU_uxTaskPriorityGet_Unpriv:                         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskPriorityGetImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskPriorityGetImpl                     \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTaskPriorityGet_Unpriv                      \n"
+                " MPU_uxTaskPriorityGet_Priv:                           \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTaskPriorityGetImpl                       \n"
+                " MPU_uxTaskPriorityGet_Unpriv:                         \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskPriorityGetImpl                      \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */
+    #endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_eTaskGetState == 1 )
+    #if ( INCLUDE_eTaskGetState == 1 )
 
-eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_eTaskGetStateImpl                         \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_eTaskGetState_Unpriv                          \n"
-        " MPU_eTaskGetState_Priv:                               \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_eTaskGetStateImpl                           \n"
-        " MPU_eTaskGetState_Unpriv:                             \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_eTaskGetStateImpl                          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_eTaskGetStateImpl                         \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_eTaskGetState_Unpriv                          \n"
+                " MPU_eTaskGetState_Priv:                               \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_eTaskGetStateImpl                           \n"
+                " MPU_eTaskGetState_Unpriv:                             \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_eTaskGetStateImpl                          \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_eTaskGetState == 1 ) */
+    #endif /* if ( INCLUDE_eTaskGetState == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-void MPU_vTaskGetInfo( TaskHandle_t xTask,
-                       TaskStatus_t * pxTaskStatus,
-                       BaseType_t xGetFreeStackSpace,
-                       eTaskState eState ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskGetInfo( TaskHandle_t xTask,
+                               TaskStatus_t * pxTaskStatus,
+                               BaseType_t xGetFreeStackSpace,
+                               eTaskState eState ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskGetInfo( TaskHandle_t xTask,
-                       TaskStatus_t * pxTaskStatus,
-                       BaseType_t xGetFreeStackSpace,
-                       eTaskState eState ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskGetInfoImpl                          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskGetInfo_Unpriv                           \n"
-        " MPU_vTaskGetInfo_Priv:                                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskGetInfoImpl                            \n"
-        " MPU_vTaskGetInfo_Unpriv:                              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskGetInfoImpl                           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskGetInfo( TaskHandle_t xTask,
+                               TaskStatus_t * pxTaskStatus,
+                               BaseType_t xGetFreeStackSpace,
+                               eTaskState eState ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskGetInfoImpl                          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskGetInfo_Unpriv                           \n"
+                " MPU_vTaskGetInfo_Priv:                                \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskGetInfoImpl                            \n"
+                " MPU_vTaskGetInfo_Unpriv:                              \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskGetInfoImpl                           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
+    #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
+    #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
 
-TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetIdleTaskHandleImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGetIdleTaskHandle_Unpriv                 \n"
-        " MPU_xTaskGetIdleTaskHandle_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGetIdleTaskHandleImpl                  \n"
-        " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetIdleTaskHandleImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetIdleTaskHandleImpl                \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGetIdleTaskHandle_Unpriv                 \n"
+                " MPU_xTaskGetIdleTaskHandle_Priv:                      \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGetIdleTaskHandleImpl                  \n"
+                " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetIdleTaskHandleImpl                 \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */
+    #endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_vTaskSuspend == 1 )
+    #if ( INCLUDE_vTaskSuspend == 1 )
 
-void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSuspendImpl                          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskSuspend_Unpriv                           \n"
-        " MPU_vTaskSuspend_Priv:                                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskSuspendImpl                            \n"
-        " MPU_vTaskSuspend_Unpriv:                              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSuspendImpl                           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskSuspendImpl                          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskSuspend_Unpriv                           \n"
+                " MPU_vTaskSuspend_Priv:                                \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskSuspendImpl                            \n"
+                " MPU_vTaskSuspend_Unpriv:                              \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskSuspendImpl                           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
+    #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_vTaskSuspend == 1 )
+    #if ( INCLUDE_vTaskSuspend == 1 )
 
-void MPU_vTaskResume( TaskHandle_t xTaskToResume ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskResume( TaskHandle_t xTaskToResume ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskResumeImpl                           \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskResume_Unpriv                            \n"
-        " MPU_vTaskResume_Priv:                                 \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskResumeImpl                             \n"
-        " MPU_vTaskResume_Unpriv:                               \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskResumeImpl                            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskResumeImpl                           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskResume_Unpriv                            \n"
+                " MPU_vTaskResume_Priv:                                 \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskResumeImpl                             \n"
+                " MPU_vTaskResume_Unpriv:                               \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskResumeImpl                            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
+    #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
 /*-----------------------------------------------------------*/
 
-TickType_t MPU_xTaskGetTickCount( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    TickType_t MPU_xTaskGetTickCount( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TickType_t MPU_xTaskGetTickCount( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetTickCountImpl                     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGetTickCount_Unpriv                      \n"
-        " MPU_xTaskGetTickCount_Priv:                           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGetTickCountImpl                       \n"
-        " MPU_xTaskGetTickCount_Unpriv:                         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetTickCountImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    TickType_t MPU_xTaskGetTickCount( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xTaskGetTickCountImpl                     \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xTaskGetTickCount_Unpriv                      \n"
+            " MPU_xTaskGetTickCount_Priv:                           \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xTaskGetTickCountImpl                       \n"
+            " MPU_xTaskGetTickCount_Unpriv:                         \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xTaskGetTickCountImpl                      \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetNumberOfTasksImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTaskGetNumberOfTasks_Unpriv                 \n"
-        " MPU_uxTaskGetNumberOfTasks_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTaskGetNumberOfTasksImpl                  \n"
-        " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetNumberOfTasksImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_uxTaskGetNumberOfTasksImpl                \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_uxTaskGetNumberOfTasks_Unpriv                 \n"
+            " MPU_uxTaskGetNumberOfTasks_Priv:                      \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_uxTaskGetNumberOfTasksImpl                  \n"
+            " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_uxTaskGetNumberOfTasksImpl                 \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configGENERATE_RUN_TIME_STATS == 1 )
+    #if ( configGENERATE_RUN_TIME_STATS == 1 )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetRunTimeCounterImpl               \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGetRunTimeCounter_Unpriv                \n"
-        " MPU_ulTaskGetRunTimeCounter_Priv:                     \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGetRunTimeCounterImpl                 \n"
-        " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetRunTimeCounterImpl                \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetRunTimeCounterImpl               \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGetRunTimeCounter_Unpriv                \n"
+                " MPU_ulTaskGetRunTimeCounter_Priv:                     \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGetRunTimeCounterImpl                 \n"
+                " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetRunTimeCounterImpl                \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configGENERATE_RUN_TIME_STATS == 1 )
+    #if ( configGENERATE_RUN_TIME_STATS == 1 )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetRunTimePercentImpl               \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGetRunTimePercent_Unpriv                \n"
-        " MPU_ulTaskGetRunTimePercent_Priv:                     \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGetRunTimePercentImpl                 \n"
-        " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetRunTimePercentImpl                \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetRunTimePercentImpl               \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGetRunTimePercent_Unpriv                \n"
+                " MPU_ulTaskGetRunTimePercent_Priv:                     \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGetRunTimePercentImpl                 \n"
+                " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetRunTimePercentImpl                \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+    #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetIdleRunTimePercentImpl           \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv            \n"
-        " MPU_ulTaskGetIdleRunTimePercent_Priv:                 \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGetIdleRunTimePercentImpl             \n"
-        " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetIdleRunTimePercentImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetIdleRunTimePercentImpl           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv            \n"
+                " MPU_ulTaskGetIdleRunTimePercent_Priv:                 \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGetIdleRunTimePercentImpl             \n"
+                " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetIdleRunTimePercentImpl            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+    #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetIdleRunTimeCounterImpl           \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv            \n"
-        " MPU_ulTaskGetIdleRunTimeCounter_Priv:                 \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGetIdleRunTimeCounterImpl             \n"
-        " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetIdleRunTimeCounterImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetIdleRunTimeCounterImpl           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv            \n"
+                " MPU_ulTaskGetIdleRunTimeCounter_Priv:                 \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGetIdleRunTimeCounterImpl             \n"
+                " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetIdleRunTimeCounterImpl            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+    #if ( configUSE_APPLICATION_TASK_TAG == 1 )
 
-void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
-                                     TaskHookFunction_t pxHookFunction ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
+                                             TaskHookFunction_t pxHookFunction ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
-                                     TaskHookFunction_t pxHookFunction ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSetApplicationTaskTagImpl            \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskSetApplicationTaskTag_Unpriv             \n"
-        " MPU_vTaskSetApplicationTaskTag_Priv:                  \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskSetApplicationTaskTagImpl              \n"
-        " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSetApplicationTaskTagImpl             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
+                                             TaskHookFunction_t pxHookFunction ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskSetApplicationTaskTagImpl            \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskSetApplicationTaskTag_Unpriv             \n"
+                " MPU_vTaskSetApplicationTaskTag_Priv:                  \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskSetApplicationTaskTagImpl              \n"
+                " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskSetApplicationTaskTagImpl             \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
+    #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+    #if ( configUSE_APPLICATION_TASK_TAG == 1 )
 
-TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetApplicationTaskTagImpl            \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGetApplicationTaskTag_Unpriv             \n"
-        " MPU_xTaskGetApplicationTaskTag_Priv:                  \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGetApplicationTaskTagImpl              \n"
-        " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetApplicationTaskTagImpl             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetApplicationTaskTagImpl            \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGetApplicationTaskTag_Unpriv             \n"
+                " MPU_xTaskGetApplicationTaskTag_Priv:                  \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGetApplicationTaskTagImpl              \n"
+                " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetApplicationTaskTagImpl             \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
+    #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+    #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
 
-void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
-                                            BaseType_t xIndex,
-                                            void * pvValue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
+                                                    BaseType_t xIndex,
+                                                    void * pvValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
-                                            BaseType_t xIndex,
-                                            void * pvValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSetThreadLocalStoragePointerImpl     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv      \n"
-        " MPU_vTaskSetThreadLocalStoragePointer_Priv:           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskSetThreadLocalStoragePointerImpl       \n"
-        " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSetThreadLocalStoragePointerImpl      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
+                                                    BaseType_t xIndex,
+                                                    void * pvValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskSetThreadLocalStoragePointerImpl     \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv      \n"
+                " MPU_vTaskSetThreadLocalStoragePointer_Priv:           \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskSetThreadLocalStoragePointerImpl       \n"
+                " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskSetThreadLocalStoragePointerImpl      \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
+    #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+    #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
 
-void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
-                                               BaseType_t xIndex ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
+                                                       BaseType_t xIndex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
-                                               BaseType_t xIndex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pvTaskGetThreadLocalStoragePointerImpl    \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv     \n"
-        " MPU_pvTaskGetThreadLocalStoragePointer_Priv:          \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_pvTaskGetThreadLocalStoragePointerImpl      \n"
-        " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pvTaskGetThreadLocalStoragePointerImpl     \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
+                                                       BaseType_t xIndex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pvTaskGetThreadLocalStoragePointerImpl    \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv     \n"
+                " MPU_pvTaskGetThreadLocalStoragePointer_Priv:          \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_pvTaskGetThreadLocalStoragePointerImpl      \n"
+                " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pvTaskGetThreadLocalStoragePointerImpl     \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
+    #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
-                                      const UBaseType_t uxArraySize,
-                                      configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
+                                              const UBaseType_t uxArraySize,
+                                              configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
-                                      const UBaseType_t uxArraySize,
-                                      configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetSystemStateImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTaskGetSystemState_Unpriv                   \n"
-        " MPU_uxTaskGetSystemState_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTaskGetSystemStateImpl                    \n"
-        " MPU_uxTaskGetSystemState_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetSystemStateImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
+                                              const UBaseType_t uxArraySize,
+                                              configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskGetSystemStateImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTaskGetSystemState_Unpriv                   \n"
+                " MPU_uxTaskGetSystemState_Priv:                        \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTaskGetSystemStateImpl                    \n"
+                " MPU_uxTaskGetSystemState_Unpriv:                      \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskGetSystemStateImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
+    #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
+    #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
 
-UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetStackHighWaterMarkImpl           \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTaskGetStackHighWaterMark_Unpriv            \n"
-        " MPU_uxTaskGetStackHighWaterMark_Priv:                 \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTaskGetStackHighWaterMarkImpl             \n"
-        " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetStackHighWaterMarkImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskGetStackHighWaterMarkImpl           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTaskGetStackHighWaterMark_Unpriv            \n"
+                " MPU_uxTaskGetStackHighWaterMark_Priv:                 \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTaskGetStackHighWaterMarkImpl             \n"
+                " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskGetStackHighWaterMarkImpl            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */
+    #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
+    #if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
 
-configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetStackHighWaterMark2Impl          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv           \n"
-        " MPU_uxTaskGetStackHighWaterMark2_Priv:                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTaskGetStackHighWaterMark2Impl            \n"
-        " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetStackHighWaterMark2Impl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskGetStackHighWaterMark2Impl          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv           \n"
+                " MPU_uxTaskGetStackHighWaterMark2_Priv:                \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTaskGetStackHighWaterMark2Impl            \n"
+                " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskGetStackHighWaterMark2Impl           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */
+    #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
+    #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
 
-TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetCurrentTaskHandleImpl             \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGetCurrentTaskHandle_Unpriv              \n"
-        " MPU_xTaskGetCurrentTaskHandle_Priv:                   \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGetCurrentTaskHandleImpl               \n"
-        " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetCurrentTaskHandleImpl              \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetCurrentTaskHandleImpl             \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGetCurrentTaskHandle_Unpriv              \n"
+                " MPU_xTaskGetCurrentTaskHandle_Priv:                   \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGetCurrentTaskHandleImpl               \n"
+                " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetCurrentTaskHandleImpl              \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
+    #endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_xTaskGetSchedulerState == 1 )
+    #if ( INCLUDE_xTaskGetSchedulerState == 1 )
 
-BaseType_t MPU_xTaskGetSchedulerState( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGetSchedulerState( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGetSchedulerState( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetSchedulerStateImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGetSchedulerState_Unpriv                 \n"
-        " MPU_xTaskGetSchedulerState_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGetSchedulerStateImpl                  \n"
-        " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetSchedulerStateImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGetSchedulerState( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetSchedulerStateImpl                \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGetSchedulerState_Unpriv                 \n"
+                " MPU_xTaskGetSchedulerState_Priv:                      \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGetSchedulerStateImpl                  \n"
+                " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetSchedulerStateImpl                 \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */
+    #endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */
 /*-----------------------------------------------------------*/
 
-void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSetTimeOutStateImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskSetTimeOutState_Unpriv                   \n"
-        " MPU_vTaskSetTimeOutState_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskSetTimeOutStateImpl                    \n"
-        " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSetTimeOutStateImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_vTaskSetTimeOutStateImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_vTaskSetTimeOutState_Unpriv                   \n"
+            " MPU_vTaskSetTimeOutState_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_vTaskSetTimeOutStateImpl                    \n"
+            " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_vTaskSetTimeOutStateImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
-                                     TickType_t * const pxTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
+                                         TickType_t * const pxTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
-                                     TickType_t * const pxTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskCheckForTimeOutImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskCheckForTimeOut_Unpriv                   \n"
-        " MPU_xTaskCheckForTimeOut_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskCheckForTimeOutImpl                    \n"
-        " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskCheckForTimeOutImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
+                                         TickType_t * const pxTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xTaskCheckForTimeOutImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xTaskCheckForTimeOut_Unpriv                   \n"
+            " MPU_xTaskCheckForTimeOut_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xTaskCheckForTimeOutImpl                    \n"
+            " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xTaskCheckForTimeOutImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                   UBaseType_t uxIndexToNotify,
-                                   uint32_t ulValue,
-                                   eNotifyAction eAction,
-                                   uint32_t * pulPreviousNotificationValue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
+                                           UBaseType_t uxIndexToNotify,
+                                           uint32_t ulValue,
+                                           eNotifyAction eAction,
+                                           uint32_t * pulPreviousNotificationValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                   UBaseType_t uxIndexToNotify,
-                                   uint32_t ulValue,
-                                   eNotifyAction eAction,
-                                   uint32_t * pulPreviousNotificationValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGenericNotifyImpl                    \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGenericNotify_Unpriv                     \n"
-        " MPU_xTaskGenericNotify_Priv:                          \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGenericNotifyImpl                      \n"
-        " MPU_xTaskGenericNotify_Unpriv:                        \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGenericNotifyImpl                     \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
+                                           UBaseType_t uxIndexToNotify,
+                                           uint32_t ulValue,
+                                           eNotifyAction eAction,
+                                           uint32_t * pulPreviousNotificationValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGenericNotifyImpl                    \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGenericNotify_Unpriv                     \n"
+                " MPU_xTaskGenericNotify_Priv:                          \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGenericNotifyImpl                      \n"
+                " MPU_xTaskGenericNotify_Unpriv:                        \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGenericNotifyImpl                     \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                       uint32_t ulBitsToClearOnEntry,
-                                       uint32_t ulBitsToClearOnExit,
-                                       uint32_t * pulNotificationValue,
-                                       TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
+                                               uint32_t ulBitsToClearOnEntry,
+                                               uint32_t ulBitsToClearOnExit,
+                                               uint32_t * pulNotificationValue,
+                                               TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                       uint32_t ulBitsToClearOnEntry,
-                                       uint32_t ulBitsToClearOnExit,
-                                       uint32_t * pulNotificationValue,
-                                       TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGenericNotifyWaitImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGenericNotifyWait_Unpriv                 \n"
-        " MPU_xTaskGenericNotifyWait_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGenericNotifyWaitImpl                  \n"
-        " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGenericNotifyWaitImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
+                                               uint32_t ulBitsToClearOnEntry,
+                                               uint32_t ulBitsToClearOnExit,
+                                               uint32_t * pulNotificationValue,
+                                               TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGenericNotifyWaitImpl                \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGenericNotifyWait_Unpriv                 \n"
+                " MPU_xTaskGenericNotifyWait_Priv:                      \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGenericNotifyWaitImpl                  \n"
+                " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGenericNotifyWaitImpl                 \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
-                                      BaseType_t xClearCountOnExit,
-                                      TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
+                                              BaseType_t xClearCountOnExit,
+                                              TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
-                                      BaseType_t xClearCountOnExit,
-                                      TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGenericNotifyTakeImpl               \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGenericNotifyTake_Unpriv                \n"
-        " MPU_ulTaskGenericNotifyTake_Priv:                     \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGenericNotifyTakeImpl                 \n"
-        " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGenericNotifyTakeImpl                \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
+                                              BaseType_t xClearCountOnExit,
+                                              TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGenericNotifyTakeImpl               \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGenericNotifyTake_Unpriv                \n"
+                " MPU_ulTaskGenericNotifyTake_Priv:                     \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGenericNotifyTakeImpl                 \n"
+                " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGenericNotifyTakeImpl                \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
-                                             UBaseType_t uxIndexToClear ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
+                                                     UBaseType_t uxIndexToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
-                                             UBaseType_t uxIndexToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGenericNotifyStateClearImpl          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGenericNotifyStateClear_Unpriv           \n"
-        " MPU_xTaskGenericNotifyStateClear_Priv:                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGenericNotifyStateClearImpl            \n"
-        " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGenericNotifyStateClearImpl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
+                                                     UBaseType_t uxIndexToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGenericNotifyStateClearImpl          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGenericNotifyStateClear_Unpriv           \n"
+                " MPU_xTaskGenericNotifyStateClear_Priv:                \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGenericNotifyStateClearImpl            \n"
+                " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGenericNotifyStateClearImpl           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
-                                            UBaseType_t uxIndexToClear,
-                                            uint32_t ulBitsToClear ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
+                                                    UBaseType_t uxIndexToClear,
+                                                    uint32_t ulBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
-                                            UBaseType_t uxIndexToClear,
-                                            uint32_t ulBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGenericNotifyValueClearImpl         \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGenericNotifyValueClear_Unpriv          \n"
-        " MPU_ulTaskGenericNotifyValueClear_Priv:               \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGenericNotifyValueClearImpl           \n"
-        " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGenericNotifyValueClearImpl          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
+                                                    UBaseType_t uxIndexToClear,
+                                                    uint32_t ulBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGenericNotifyValueClearImpl         \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGenericNotifyValueClear_Unpriv          \n"
+                " MPU_ulTaskGenericNotifyValueClear_Priv:               \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGenericNotifyValueClearImpl           \n"
+                " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGenericNotifyValueClearImpl          \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
-                                  const void * const pvItemToQueue,
-                                  TickType_t xTicksToWait,
-                                  const BaseType_t xCopyPosition ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
+                                      const void * const pvItemToQueue,
+                                      TickType_t xTicksToWait,
+                                      const BaseType_t xCopyPosition ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
-                                  const void * const pvItemToQueue,
-                                  TickType_t xTicksToWait,
-                                  const BaseType_t xCopyPosition ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueGenericSendImpl                     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueGenericSend_Unpriv                      \n"
-        " MPU_xQueueGenericSend_Priv:                           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueGenericSendImpl                       \n"
-        " MPU_xQueueGenericSend_Unpriv:                         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueGenericSendImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
+                                      const void * const pvItemToQueue,
+                                      TickType_t xTicksToWait,
+                                      const BaseType_t xCopyPosition ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueueGenericSendImpl                     \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xQueueGenericSend_Unpriv                      \n"
+            " MPU_xQueueGenericSend_Priv:                           \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xQueueGenericSendImpl                       \n"
+            " MPU_xQueueGenericSend_Unpriv:                         \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueueGenericSendImpl                      \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxQueueMessagesWaitingImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxQueueMessagesWaiting_Unpriv                 \n"
-        " MPU_uxQueueMessagesWaiting_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxQueueMessagesWaitingImpl                  \n"
-        " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxQueueMessagesWaitingImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_uxQueueMessagesWaitingImpl                \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_uxQueueMessagesWaiting_Unpriv                 \n"
+            " MPU_uxQueueMessagesWaiting_Priv:                      \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_uxQueueMessagesWaitingImpl                  \n"
+            " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_uxQueueMessagesWaitingImpl                 \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxQueueSpacesAvailableImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxQueueSpacesAvailable_Unpriv                 \n"
-        " MPU_uxQueueSpacesAvailable_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxQueueSpacesAvailableImpl                  \n"
-        " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxQueueSpacesAvailableImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_uxQueueSpacesAvailableImpl                \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_uxQueueSpacesAvailable_Unpriv                 \n"
+            " MPU_uxQueueSpacesAvailable_Priv:                      \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_uxQueueSpacesAvailableImpl                  \n"
+            " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_uxQueueSpacesAvailableImpl                 \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
-                              void * const pvBuffer,
-                              TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
+                                  void * const pvBuffer,
+                                  TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
-                              void * const pvBuffer,
-                              TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueReceiveImpl                         \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueReceive_Unpriv                          \n"
-        " MPU_xQueueReceive_Priv:                               \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueReceiveImpl                           \n"
-        " MPU_xQueueReceive_Unpriv:                             \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueReceiveImpl                          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
+                                  void * const pvBuffer,
+                                  TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueueReceiveImpl                         \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xQueueReceive_Unpriv                          \n"
+            " MPU_xQueueReceive_Priv:                               \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xQueueReceiveImpl                           \n"
+            " MPU_xQueueReceive_Unpriv:                             \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueueReceiveImpl                          \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
-                           void * const pvBuffer,
-                           TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
+                               void * const pvBuffer,
+                               TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
-                           void * const pvBuffer,
-                           TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueuePeekImpl                            \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueuePeek_Unpriv                             \n"
-        " MPU_xQueuePeek_Priv:                                  \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueuePeekImpl                              \n"
-        " MPU_xQueuePeek_Unpriv:                                \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueuePeekImpl                             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
+                               void * const pvBuffer,
+                               TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueuePeekImpl                            \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xQueuePeek_Unpriv                             \n"
+            " MPU_xQueuePeek_Priv:                                  \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xQueuePeekImpl                              \n"
+            " MPU_xQueuePeek_Unpriv:                                \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueuePeekImpl                             \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
-                                    TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
+                                        TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
-                                    TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueSemaphoreTakeImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueSemaphoreTake_Unpriv                    \n"
-        " MPU_xQueueSemaphoreTake_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueSemaphoreTakeImpl                     \n"
-        " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueSemaphoreTakeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
+                                        TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueueSemaphoreTakeImpl                   \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xQueueSemaphoreTake_Unpriv                    \n"
+            " MPU_xQueueSemaphoreTake_Priv:                         \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xQueueSemaphoreTakeImpl                     \n"
+            " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueueSemaphoreTakeImpl                    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+    #if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
 
-TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueGetMutexHolderImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueGetMutexHolder_Unpriv                   \n"
-        " MPU_xQueueGetMutexHolder_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueGetMutexHolderImpl                    \n"
-        " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueGetMutexHolderImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueGetMutexHolderImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueGetMutexHolder_Unpriv                   \n"
+                " MPU_xQueueGetMutexHolder_Priv:                        \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueGetMutexHolderImpl                    \n"
+                " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueGetMutexHolderImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */
+    #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+    #if ( configUSE_RECURSIVE_MUTEXES == 1 )
 
-BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
-                                         TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+                                                 TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+        BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+                                                 TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueTakeMutexRecursiveImpl              \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueTakeMutexRecursive_Unpriv               \n"
+                " MPU_xQueueTakeMutexRecursive_Priv:                    \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueTakeMutexRecursiveImpl                \n"
+                " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueTakeMutexRecursiveImpl               \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_RECURSIVE_MUTEXES == 1 )
+
+        BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueGiveMutexRecursiveImpl              \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueGiveMutexRecursive_Unpriv               \n"
+                " MPU_xQueueGiveMutexRecursive_Priv:                    \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueGiveMutexRecursiveImpl                \n"
+                " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueGiveMutexRecursiveImpl               \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_QUEUE_SETS == 1 )
+
+        QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
+                                                        const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
+                                                        const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueSelectFromSetImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueSelectFromSet_Unpriv                    \n"
+                " MPU_xQueueSelectFromSet_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueSelectFromSetImpl                     \n"
+                " MPU_xQueueSelectFromSet_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueSelectFromSetImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_QUEUE_SETS == 1 )
+
+        BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                                       QueueSetHandle_t xQueueSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                                       QueueSetHandle_t xQueueSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueAddToSetImpl                        \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueAddToSet_Unpriv                         \n"
+                " MPU_xQueueAddToSet_Priv:                              \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueAddToSetImpl                          \n"
+                " MPU_xQueueAddToSet_Unpriv:                            \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueAddToSetImpl                         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+        void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
+                                      const char * pcName ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
+                                      const char * pcName ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vQueueAddToRegistryImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vQueueAddToRegistry_Unpriv                    \n"
+                " MPU_vQueueAddToRegistry_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vQueueAddToRegistryImpl                     \n"
+                " MPU_vQueueAddToRegistry_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vQueueAddToRegistryImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+        void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vQueueUnregisterQueueImpl                 \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vQueueUnregisterQueue_Unpriv                  \n"
+                " MPU_vQueueUnregisterQueue_Priv:                       \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vQueueUnregisterQueueImpl                   \n"
+                " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vQueueUnregisterQueueImpl                  \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+        const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pcQueueGetNameImpl                        \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_pcQueueGetName_Unpriv                         \n"
+                " MPU_pcQueueGetName_Priv:                              \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_pcQueueGetNameImpl                          \n"
+                " MPU_pcQueueGetName_Unpriv:                            \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pcQueueGetNameImpl                         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pvTimerGetTimerIDImpl                     \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_pvTimerGetTimerID_Unpriv                      \n"
+                " MPU_pvTimerGetTimerID_Priv:                           \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_pvTimerGetTimerIDImpl                       \n"
+                " MPU_pvTimerGetTimerID_Unpriv:                         \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pvTimerGetTimerIDImpl                      \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
+                                   void * pvNewID ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
+                                   void * pvNewID ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTimerSetTimerIDImpl                      \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTimerSetTimerID_Unpriv                       \n"
+                " MPU_vTimerSetTimerID_Priv:                            \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTimerSetTimerIDImpl                        \n"
+                " MPU_vTimerSetTimerID_Unpriv:                          \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTimerSetTimerIDImpl                       \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerIsTimerActiveImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerIsTimerActive_Unpriv                    \n"
+                " MPU_xTimerIsTimerActive_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerIsTimerActiveImpl                     \n"
+                " MPU_xTimerIsTimerActive_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerIsTimerActiveImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetTimerDaemonTaskHandleImpl        \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv         \n"
+                " MPU_xTimerGetTimerDaemonTaskHandle_Priv:              \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerGetTimerDaemonTaskHandleImpl          \n"
+                " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetTimerDaemonTaskHandleImpl         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                                     const BaseType_t xCommandID,
+                                                     const TickType_t xOptionalValue,
+                                                     BaseType_t * const pxHigherPriorityTaskWoken,
+                                                     const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                                     const BaseType_t xCommandID,
+                                                     const TickType_t xOptionalValue,
+                                                     BaseType_t * const pxHigherPriorityTaskWoken,
+                                                     const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                               \n"
+                " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
+                "                                                               \n"
+                " push {r0}                                                     \n"
+                " mrs r0, control                                               \n"
+                " tst r0, #1                                                    \n"
+                " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
+                " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
+                "     pop {r0}                                                  \n"
+                "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
+                " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
+                "     pop {r0}                                                  \n"
+                "     svc %0                                                    \n"
+                "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
+                "     svc %1                                                    \n"
+                "     bx lr                                                     \n"
+                "                                                               \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pcTimerGetNameImpl                        \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_pcTimerGetName_Unpriv                         \n"
+                " MPU_pcTimerGetName_Priv:                              \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_pcTimerGetNameImpl                          \n"
+                " MPU_pcTimerGetName_Unpriv:                            \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pcTimerGetNameImpl                         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
+                                      const BaseType_t uxAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
+                                      const BaseType_t uxAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTimerSetReloadModeImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTimerSetReloadMode_Unpriv                    \n"
+                " MPU_vTimerSetReloadMode_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTimerSetReloadModeImpl                     \n"
+                " MPU_vTimerSetReloadMode_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTimerSetReloadModeImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetReloadModeImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerGetReloadMode_Unpriv                    \n"
+                " MPU_xTimerGetReloadMode_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerGetReloadModeImpl                     \n"
+                " MPU_xTimerGetReloadMode_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetReloadModeImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTimerGetReloadModeImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTimerGetReloadMode_Unpriv                   \n"
+                " MPU_uxTimerGetReloadMode_Priv:                        \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTimerGetReloadModeImpl                    \n"
+                " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTimerGetReloadModeImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetPeriodImpl                       \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerGetPeriod_Unpriv                        \n"
+                " MPU_xTimerGetPeriod_Priv:                             \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerGetPeriodImpl                         \n"
+                " MPU_xTimerGetPeriod_Unpriv:                           \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetPeriodImpl                        \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetExpiryTimeImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerGetExpiryTime_Unpriv                    \n"
+                " MPU_xTimerGetExpiryTime_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerGetExpiryTimeImpl                     \n"
+                " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetExpiryTimeImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         const BaseType_t xClearOnExit,
+                                         const BaseType_t xWaitForAllBits,
+                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         const BaseType_t xClearOnExit,
+                                         const BaseType_t xWaitForAllBits,
                                          TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueTakeMutexRecursiveImpl              \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueTakeMutexRecursive_Unpriv               \n"
-        " MPU_xQueueTakeMutexRecursive_Priv:                    \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueTakeMutexRecursiveImpl                \n"
-        " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueTakeMutexRecursiveImpl               \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupWaitBitsImpl                   \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
+            " MPU_xEventGroupWaitBits_Priv:                         \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xEventGroupWaitBitsImpl                     \n"
+            " MPU_xEventGroupWaitBits_Unpriv:                       \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupWaitBitsImpl                    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                          const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueGiveMutexRecursiveImpl              \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueGiveMutexRecursive_Unpriv               \n"
-        " MPU_xQueueGiveMutexRecursive_Priv:                    \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueGiveMutexRecursiveImpl                \n"
-        " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueGiveMutexRecursiveImpl               \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                          const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupClearBitsImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xEventGroupClearBits_Unpriv                   \n"
+            " MPU_xEventGroupClearBits_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xEventGroupClearBitsImpl                    \n"
+            " MPU_xEventGroupClearBits_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupClearBitsImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_QUEUE_SETS == 1 )
+    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                        const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
-                                                const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
-                                                const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueSelectFromSetImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueSelectFromSet_Unpriv                    \n"
-        " MPU_xQueueSelectFromSet_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueSelectFromSetImpl                     \n"
-        " MPU_xQueueSelectFromSet_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueSelectFromSetImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                        const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupSetBitsImpl                    \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xEventGroupSetBits_Unpriv                     \n"
+            " MPU_xEventGroupSetBits_Priv:                          \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xEventGroupSetBitsImpl                      \n"
+            " MPU_xEventGroupSetBits_Unpriv:                        \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupSetBitsImpl                     \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_QUEUE_SETS == 1 )
-
-BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
-                               QueueSetHandle_t xQueueSet ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
-                               QueueSetHandle_t xQueueSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueAddToSetImpl                        \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueAddToSet_Unpriv                         \n"
-        " MPU_xQueueAddToSet_Priv:                              \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueAddToSetImpl                          \n"
-        " MPU_xQueueAddToSet_Unpriv:                            \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueAddToSetImpl                         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_QUEUE_SETS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
-                              const char * pcName ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
-                              const char * pcName ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vQueueAddToRegistryImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vQueueAddToRegistry_Unpriv                    \n"
-        " MPU_vQueueAddToRegistry_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vQueueAddToRegistryImpl                     \n"
-        " MPU_vQueueAddToRegistry_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vQueueAddToRegistryImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vQueueUnregisterQueueImpl                 \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vQueueUnregisterQueue_Unpriv                  \n"
-        " MPU_vQueueUnregisterQueue_Priv:                       \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vQueueUnregisterQueueImpl                   \n"
-        " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vQueueUnregisterQueueImpl                  \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pcQueueGetNameImpl                        \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_pcQueueGetName_Unpriv                         \n"
-        " MPU_pcQueueGetName_Priv:                              \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_pcQueueGetNameImpl                          \n"
-        " MPU_pcQueueGetName_Unpriv:                            \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pcQueueGetNameImpl                         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pvTimerGetTimerIDImpl                     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_pvTimerGetTimerID_Unpriv                      \n"
-        " MPU_pvTimerGetTimerID_Priv:                           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_pvTimerGetTimerIDImpl                       \n"
-        " MPU_pvTimerGetTimerID_Unpriv:                         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pvTimerGetTimerIDImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
-                           void * pvNewID ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
-                           void * pvNewID ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTimerSetTimerIDImpl                      \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTimerSetTimerID_Unpriv                       \n"
-        " MPU_vTimerSetTimerID_Priv:                            \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTimerSetTimerIDImpl                        \n"
-        " MPU_vTimerSetTimerID_Unpriv:                          \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTimerSetTimerIDImpl                       \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerIsTimerActiveImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTimerIsTimerActive_Unpriv                    \n"
-        " MPU_xTimerIsTimerActive_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerIsTimerActiveImpl                     \n"
-        " MPU_xTimerIsTimerActive_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerIsTimerActiveImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetTimerDaemonTaskHandleImpl        \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv         \n"
-        " MPU_xTimerGetTimerDaemonTaskHandle_Priv:              \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerGetTimerDaemonTaskHandleImpl          \n"
-        " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetTimerDaemonTaskHandleImpl         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                             const BaseType_t xCommandID,
-                                             const TickType_t xOptionalValue,
-                                             BaseType_t * const pxHigherPriorityTaskWoken,
-                                             const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                             const BaseType_t xCommandID,
-                                             const TickType_t xOptionalValue,
-                                             BaseType_t * const pxHigherPriorityTaskWoken,
-                                             const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                               \n"
-        " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
-        "                                                               \n"
-        " push {r0}                                                     \n"
-        " mrs r0, control                                               \n"
-        " tst r0, #1                                                    \n"
-        " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
-        " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
-        "     pop {r0}                                                  \n"
-        "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
-        " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
-        "     pop {r0}                                                  \n"
-        "     svc %0                                                    \n"
-        "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
-        "     svc %1                                                    \n"
-        "     bx lr                                                     \n"
-        "                                                               \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pcTimerGetNameImpl                        \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_pcTimerGetName_Unpriv                         \n"
-        " MPU_pcTimerGetName_Priv:                              \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_pcTimerGetNameImpl                          \n"
-        " MPU_pcTimerGetName_Unpriv:                            \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pcTimerGetNameImpl                         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                              const BaseType_t uxAutoReload ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                              const BaseType_t uxAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTimerSetReloadModeImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTimerSetReloadMode_Unpriv                    \n"
-        " MPU_vTimerSetReloadMode_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTimerSetReloadModeImpl                     \n"
-        " MPU_vTimerSetReloadMode_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTimerSetReloadModeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetReloadModeImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTimerGetReloadMode_Unpriv                    \n"
-        " MPU_xTimerGetReloadMode_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerGetReloadModeImpl                     \n"
-        " MPU_xTimerGetReloadMode_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetReloadModeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTimerGetReloadModeImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTimerGetReloadMode_Unpriv                   \n"
-        " MPU_uxTimerGetReloadMode_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTimerGetReloadModeImpl                    \n"
-        " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTimerGetReloadModeImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetPeriodImpl                       \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTimerGetPeriod_Unpriv                        \n"
-        " MPU_xTimerGetPeriod_Priv:                             \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerGetPeriodImpl                         \n"
-        " MPU_xTimerGetPeriod_Unpriv:                           \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetPeriodImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetExpiryTimeImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTimerGetExpiryTime_Unpriv                    \n"
-        " MPU_xTimerGetExpiryTime_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerGetExpiryTimeImpl                     \n"
-        " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetExpiryTimeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                     const EventBits_t uxBitsToSet,
                                      const EventBits_t uxBitsToWaitFor,
-                                     const BaseType_t xClearOnExit,
-                                     const BaseType_t xWaitForAllBits,
-                                     TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                     const EventBits_t uxBitsToSet,
                                      const EventBits_t uxBitsToWaitFor,
-                                     const BaseType_t xClearOnExit,
-                                     const BaseType_t xWaitForAllBits,
                                      TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupWaitBitsImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
-        " MPU_xEventGroupWaitBits_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xEventGroupWaitBitsImpl                     \n"
-        " MPU_xEventGroupWaitBits_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupWaitBitsImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupSyncImpl                       \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xEventGroupSync_Unpriv                        \n"
+            " MPU_xEventGroupSync_Priv:                             \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xEventGroupSyncImpl                         \n"
+            " MPU_xEventGroupSync_Unpriv:                           \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupSyncImpl                        \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                      const EventBits_t uxBitsToClear ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                      const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupClearBitsImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xEventGroupClearBits_Unpriv                   \n"
-        " MPU_xEventGroupClearBits_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xEventGroupClearBitsImpl                    \n"
-        " MPU_xEventGroupClearBits_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupClearBitsImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxEventGroupGetNumberImpl                 \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxEventGroupGetNumber_Unpriv                  \n"
+                " MPU_uxEventGroupGetNumber_Priv:                       \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxEventGroupGetNumberImpl                   \n"
+                " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxEventGroupGetNumberImpl                  \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
 /*-----------------------------------------------------------*/
 
-EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                    const EventBits_t uxBitsToSet ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                    const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupSetBitsImpl                    \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xEventGroupSetBits_Unpriv                     \n"
-        " MPU_xEventGroupSetBits_Priv:                          \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xEventGroupSetBitsImpl                      \n"
-        " MPU_xEventGroupSetBits_Unpriv:                        \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupSetBitsImpl                     \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vEventGroupSetNumber( void * xEventGroup,
+                                       UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vEventGroupSetNumber( void * xEventGroup,
+                                       UBaseType_t uxEventGroupNumber ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vEventGroupSetNumberImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vEventGroupSetNumber_Unpriv                   \n"
+                " MPU_vEventGroupSetNumber_Priv:                        \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vEventGroupSetNumberImpl                    \n"
+                " MPU_vEventGroupSetNumber_Unpriv:                      \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vEventGroupSetNumberImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
 /*-----------------------------------------------------------*/
 
-EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                 const EventBits_t uxBitsToSet,
-                                 const EventBits_t uxBitsToWaitFor,
-                                 TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                  const void * pvTxData,
+                                  size_t xDataLengthBytes,
+                                  TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                 const EventBits_t uxBitsToSet,
-                                 const EventBits_t uxBitsToWaitFor,
-                                 TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupSyncImpl                       \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xEventGroupSync_Unpriv                        \n"
-        " MPU_xEventGroupSync_Priv:                             \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xEventGroupSyncImpl                         \n"
-        " MPU_xEventGroupSync_Unpriv:                           \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupSyncImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                  const void * pvTxData,
+                                  size_t xDataLengthBytes,
+                                  TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferSendImpl                     \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferSend_Unpriv                      \n"
+            " MPU_xStreamBufferSend_Priv:                           \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferSendImpl                       \n"
+            " MPU_xStreamBufferSend_Unpriv:                         \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferSendImpl                      \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                     void * pvRxData,
+                                     size_t xBufferLengthBytes,
+                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxEventGroupGetNumberImpl                 \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxEventGroupGetNumber_Unpriv                  \n"
-        " MPU_uxEventGroupGetNumber_Priv:                       \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxEventGroupGetNumberImpl                   \n"
-        " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxEventGroupGetNumberImpl                  \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                     void * pvRxData,
+                                     size_t xBufferLengthBytes,
+                                     TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferReceiveImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferReceive_Unpriv                   \n"
+            " MPU_xStreamBufferReceive_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferReceiveImpl                    \n"
+            " MPU_xStreamBufferReceive_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferReceiveImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vEventGroupSetNumber( void * xEventGroup,
-                               UBaseType_t uxEventGroupNumber ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vEventGroupSetNumber( void * xEventGroup,
-                               UBaseType_t uxEventGroupNumber ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vEventGroupSetNumberImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vEventGroupSetNumber_Unpriv                   \n"
-        " MPU_vEventGroupSetNumber_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vEventGroupSetNumberImpl                    \n"
-        " MPU_vEventGroupSetNumber_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vEventGroupSetNumberImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferIsFullImpl                   \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
+            " MPU_xStreamBufferIsFull_Priv:                         \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferIsFullImpl                     \n"
+            " MPU_xStreamBufferIsFull_Unpriv:                       \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferIsFullImpl                    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                              const void * pvTxData,
-                              size_t xDataLengthBytes,
-                              TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                              const void * pvTxData,
-                              size_t xDataLengthBytes,
-                              TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferSendImpl                     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferSend_Unpriv                      \n"
-        " MPU_xStreamBufferSend_Priv:                           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferSendImpl                       \n"
-        " MPU_xStreamBufferSend_Unpriv:                         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferSendImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
+            " MPU_xStreamBufferIsEmpty_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferIsEmptyImpl                    \n"
+            " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferIsEmptyImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                 void * pvRxData,
-                                 size_t xBufferLengthBytes,
-                                 TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                 void * pvRxData,
-                                 size_t xBufferLengthBytes,
-                                 TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferReceiveImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferReceive_Unpriv                   \n"
-        " MPU_xStreamBufferReceive_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferReceiveImpl                    \n"
-        " MPU_xStreamBufferReceive_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferReceiveImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
+            " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
+            " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferSpacesAvailableImpl           \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferIsFullImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
-        " MPU_xStreamBufferIsFull_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferIsFullImpl                     \n"
-        " MPU_xStreamBufferIsFull_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferIsFullImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
+            " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferBytesAvailableImpl             \n"
+            " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferBytesAvailableImpl            \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                 size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
-        " MPU_xStreamBufferIsEmpty_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferIsEmptyImpl                    \n"
-        " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferIsEmptyImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                 size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
+            " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
+            " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferSetTriggerLevelImpl           \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
-        " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
-        " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferSpacesAvailableImpl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
-size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
-        " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferBytesAvailableImpl             \n"
-        " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferBytesAvailableImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                             size_t xTriggerLevel ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                             size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
-        " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
-        " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferSetTriggerLevelImpl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
-size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
-        " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
-        " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferNextMessageLengthBytesImpl    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
+            " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
+            " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferNextMessageLengthBytesImpl    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
diff --git a/portable/GCC/ARM_CM85/non_secure/port.c b/portable/GCC/ARM_CM85/non_secure/port.c
index 80410e82e..c940c304b 100644
--- a/portable/GCC/ARM_CM85/non_secure/port.c
+++ b/portable/GCC/ARM_CM85/non_secure/port.c
@@ -110,8 +110,8 @@
 /**
  * @brief Constants used during system call enter and exit.
  */
-#define portPSR_STACK_PADDING_MASK                ( 1UL << 9UL )
-#define portEXC_RETURN_STACK_FRAME_TYPE_MASK      ( 1UL << 4UL )
+#define portPSR_STACK_PADDING_MASK              ( 1UL << 9UL )
+#define portEXC_RETURN_STACK_FRAME_TYPE_MASK    ( 1UL << 4UL )
 /*-----------------------------------------------------------*/
 
 /**
@@ -133,81 +133,81 @@
 /**
  * @brief Offsets in the stack to the parameters when inside the SVC handler.
  */
-#define portOFFSET_TO_LR                    ( 5 )
-#define portOFFSET_TO_PC                    ( 6 )
-#define portOFFSET_TO_PSR                   ( 7 )
+#define portOFFSET_TO_LR     ( 5 )
+#define portOFFSET_TO_PC     ( 6 )
+#define portOFFSET_TO_PSR    ( 7 )
 /*-----------------------------------------------------------*/
 
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                      ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                      ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                       ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                      ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                      ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                     ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                     ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK  ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK               ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK               ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK               ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK               ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK               ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK               ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK               ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK               ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0              ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1              ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2              ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3              ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4              ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5              ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6              ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7              ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE            ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT      ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                      ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE             ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -216,11 +216,11 @@
 
 /* Extract last address of the MPU region as encoded in the
  * RLAR (Region Limit Address Register) value. */
-#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar )  \
+#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar ) \
     ( ( ( rlar ) & portMPU_RLAR_ADDRESS_MASK ) | ~portMPU_RLAR_ADDRESS_MASK )
 
 /* Does addr lies within [start, end] address range? */
-#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end )    \
+#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \
     ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) )
 
 /* Is the access request satisfied by the available permissions? */
@@ -422,54 +422,57 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the system call stack so that upon returning from
-     * SVC, the system call stack is used.
-     *
-     * It is used for the system calls with up to 4 parameters.
-     *
-     * @param pulTaskStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the system call stack so that upon returning from
+ * SVC, the system call stack is used.
+ *
+ * It is used for the system calls with up to 4 parameters.
+ *
+ * @param pulTaskStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallEnter( uint32_t * pulTaskStack,
+                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the system call stack so that upon returning from
-     * SVC, the system call stack is used.
-     *
-     * It is used for the system calls with 5 parameters.
-     *
-     * @param pulTaskStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the system call stack so that upon returning from
+ * SVC, the system call stack is used.
+ *
+ * It is used for the system calls with 5 parameters.
+ *
+ * @param pulTaskStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallEnter_1( uint32_t * pulTaskStack,
+                             uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the task stack so that upon returning from
-     * SVC, the task stack is used again.
-     *
-     * @param pulSystemCallStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the task stack so that upon returning from
+ * SVC, the task stack is used again.
+ *
+ * @param pulSystemCallStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallExit( uint32_t * pulSystemCallStack,
+                          uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Checks whether or not the calling task is privileged.
-     *
-     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
-     */
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
     BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
 
 #endif /* configENABLE_MPU == 1 */
@@ -1086,18 +1089,18 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             vRestoreContextOfFirstTask();
             break;
 
-        #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
-            case portSVC_RAISE_PRIVILEGE:
+            #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+                case portSVC_RAISE_PRIVILEGE:
 
-                /* Only raise the privilege, if the svc was raised from any of
-                 * the system calls. */
-                if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
-                    ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
-                {
-                    vRaisePrivilege();
-                }
-                break;
-        #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+                    /* Only raise the privilege, if the svc was raised from any of
+                     * the system calls. */
+                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+                    {
+                        vRaisePrivilege();
+                    }
+                    break;
+            #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
         default:
             /* Incorrect SVC call. */
@@ -1108,513 +1111,526 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulSystemCallStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallEnter( uint32_t * pulTaskStack,
+                           uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulSystemCallStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        /* This is not NULL only for the duration of the system call. */
-        configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+        #if defined( __ARMCC_VERSION )
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+
+            /* This is not NULL only for the duration of the system call. */
+            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the system call stack for the stack frame. */
+            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulSystemCallStack[ i ] = pulTaskStack[ i ];
+            }
+
+            /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
+             * restore it when we exit from the system call. */
+            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* Use the pulSystemCallStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+
+            /* Remember the location where we should copy the stack frame when we exit from
+             * the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+
+            /* Record if the hardware used padding to force the stack pointer
+             * to be double word aligned. */
+            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
+            {
+                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
             }
+
+            /* We ensure in pxPortInitialiseStack that the system call stack is
+             * double word aligned and therefore, there is no need of padding.
+             * Clear the bit[9] of stacked xPSR. */
+            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
+
+            /* Raise the privilege for the duration of the system call. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " bics r0, r1         \n" /* Clear nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the system call stack for the stack frame. */
-        pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulSystemCallStack[ i ] = pulTaskStack[ i ];
-        }
-
-        /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
-         * restore it when we exit from the system call. */
-        pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-        __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* Use the pulSystemCallStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-
-        /* Remember the location where we should copy the stack frame when we exit from
-         * the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-        /* Record if the hardware used padding to force the stack pointer
-         * to be double word aligned. */
-        if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-        {
-            pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-        }
-        else
-        {
-            pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-        }
-
-        /* We ensure in pxPortInitialiseStack that the system call stack is
-         * double word aligned and therefore, there is no need of padding.
-         * Clear the bit[9] of stacked xPSR. */
-        pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-        /* Raise the privilege for the duration of the system call. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " bics r0, r1         \n" /* Clear nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulSystemCallStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallEnter_1( uint32_t * pulTaskStack,
+                             uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulSystemCallStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        /* This is not NULL only for the duration of the system call. */
-        configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+        #if defined( __ARMCC_VERSION )
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+
+            /* This is not NULL only for the duration of the system call. */
+            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the system call stack for the stack frame and
+             * the parameter passed on the stack. We only need to copy one
+             * parameter but we still reserve 2 spaces to keep the stack
+             * double word aligned. */
+            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulSystemCallStack[ i ] = pulTaskStack[ i ];
+            }
+
+            /* Copy the parameter which is passed the stack. */
+            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
+            {
+                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
+
+                /* Record if the hardware used padding to force the stack pointer
+                 * to be double word aligned. */
+                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
+
+                /* Record if the hardware used padding to force the stack pointer
+                 * to be double word aligned. */
+                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
             }
+
+            /* Store the value of the LR and PSPLIM registers before the SVC was raised.
+             * We need to restore it when we exit from the system call. */
+            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* Use the pulSystemCallStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+
+            /* Remember the location where we should copy the stack frame when we exit from
+             * the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+
+            /* We ensure in pxPortInitialiseStack that the system call stack is
+             * double word aligned and therefore, there is no need of padding.
+             * Clear the bit[9] of stacked xPSR. */
+            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
+
+            /* Raise the privilege for the duration of the system call. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " bics r0, r1         \n" /* Clear nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the system call stack for the stack frame and
-         * the parameter passed on the stack. We only need to copy one
-         * parameter but we still reserve 2 spaces to keep the stack
-         * double word aligned. */
-        pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulSystemCallStack[ i ] = pulTaskStack[ i ];
-        }
-
-        /* Copy the parameter which is passed the stack. */
-        if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-        {
-            pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
-            /* Record if the hardware used padding to force the stack pointer
-             * to be double word aligned. */
-            pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-        }
-        else
-        {
-            pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
-            /* Record if the hardware used padding to force the stack pointer
-             * to be double word aligned. */
-            pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-        }
-
-        /* Store the value of the LR and PSPLIM registers before the SVC was raised.
-         * We need to restore it when we exit from the system call. */
-        pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-        __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* Use the pulSystemCallStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-
-        /* Remember the location where we should copy the stack frame when we exit from
-         * the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-        /* We ensure in pxPortInitialiseStack that the system call stack is
-         * double word aligned and therefore, there is no need of padding.
-         * Clear the bit[9] of stacked xPSR. */
-        pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-        /* Raise the privilege for the duration of the system call. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " bics r0, r1         \n" /* Clear nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulTaskStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallExit( uint32_t * pulSystemCallStack,
+                          uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulTaskStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+        #if defined( __ARMCC_VERSION )
+
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the task stack for the stack frame. */
+            pulTaskStack = pulTaskStack - ulStackFrameSize;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulTaskStack[ i ] = pulSystemCallStack[ i ];
+            }
+
+            /* Use the pulTaskStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
+
+            /* Restore the LR and PSPLIM to what they were at the time of
+             * system call entry. */
+            pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* If the hardware used padding to force the stack pointer
+             * to be double word aligned, set the stacked xPSR bit[9],
+             * otherwise clear it. */
+            if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG )
+            {
+                pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
             }
+
+            /* This is not NULL only for the duration of the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
+
+            /* Drop the privilege before returning to the thread mode. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " orrs r0, r1         \n" /* Set nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the task stack for the stack frame. */
-        pulTaskStack = pulTaskStack - ulStackFrameSize;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulTaskStack[ i ] = pulSystemCallStack[ i ];
-        }
-
-        /* Use the pulTaskStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
-
-        /* Restore the LR and PSPLIM to what they were at the time of
-         * system call entry. */
-        pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* If the hardware used padding to force the stack pointer
-         * to be double word aligned, set the stacked xPSR bit[9],
-         * otherwise clear it. */
-        if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG )
-        {
-            pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK;
-        }
-        else
-        {
-            pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-        }
-
-        /* This is not NULL only for the duration of the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
-
-        /* Drop the privilege before returning to the thread mode. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " orrs r0, r1         \n" /* Set nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */
-{
-    BaseType_t xTaskIsPrivileged = pdFALSE;
-    const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
-
-    if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+    BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */
     {
-        xTaskIsPrivileged = pdTRUE;
-    }
+        BaseType_t xTaskIsPrivileged = pdFALSE;
+        const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
 
-    return xTaskIsPrivileged;
-}
+        if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+        {
+            xTaskIsPrivileged = pdTRUE;
+        }
+
+        return xTaskIsPrivileged;
+    }
 
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
-#if( configENABLE_MPU == 1 )
+#if ( configENABLE_MPU == 1 )
 
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     StackType_t * pxEndOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters,
-                                     BaseType_t xRunPrivileged,
-                                     xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
-{
-    uint32_t ulIndex = 0;
-
-    xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
-    ulIndex++;
-
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
-    ulIndex++;
-
-    #if ( configENABLE_TRUSTZONE == 1 )
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters,
+                                         BaseType_t xRunPrivileged,
+                                         xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
     {
-        xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT;  /* xSecureContext. */
+        uint32_t ulIndex = 0;
+
+        xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
         ulIndex++;
-    }
-    #endif /* configENABLE_TRUSTZONE */
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
-    ulIndex++;
-    if( xRunPrivileged == pdTRUE )
-    {
-        xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */
         ulIndex++;
-    }
-    else
-    {
-        xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */
         ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
+        ulIndex++;
+
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters;            /* r0. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x01010101;                           /* r1. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x02020202;                           /* r2. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x03030303;                           /* r3. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x12121212;                           /* r12. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode;                  /* PC. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR;                     /* xPSR. */
+        ulIndex++;
+
+        #if ( configENABLE_TRUSTZONE == 1 )
+        {
+            xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT; /* xSecureContext. */
+            ulIndex++;
+        }
+        #endif /* configENABLE_TRUSTZONE */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
+        ulIndex++;
+
+        if( xRunPrivileged == pdTRUE )
+        {
+            xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
+            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+            ulIndex++;
+        }
+        else
+        {
+            xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
+            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+            ulIndex++;
+        }
+
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
+        ulIndex++;
+
+        #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+        {
+            /* Ensure that the system call stack is double word aligned. */
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] );
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) &
+                                                                                     ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
+
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] );
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) +
+                                                                                            ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) &
+                                                                                          ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
+
+            /* This is not NULL only for the duration of a system call. */
+            xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL;
+        }
+        #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
+
+        return &( xMPUSettings->ulContext[ ulIndex ] );
     }
-    xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
-    ulIndex++;
-
-    #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
-    {
-        /* Ensure that the system call stack is double word aligned. */
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] );
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) &
-                                                                                 ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
-
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] );
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) +
-                                                                                        ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) &
-                                                                                      ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
-
-        /* This is not NULL only for the duration of a system call. */
-        xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL;
-    }
-    #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
-
-    return &( xMPUSettings->ulContext[ ulIndex ] );
-}
 
 #else /* configENABLE_MPU */
 
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     StackType_t * pxEndOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters ) /* PRIVILEGED_FUNCTION */
-{
-    /* Simulate the stack frame as it would be created by a context switch
-     * interrupt. */
-    #if ( portPRELOAD_REGISTERS == 0 )
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters ) /* PRIVILEGED_FUNCTION */
     {
-        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-        pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
-        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-        pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
-        *pxTopOfStack = portINITIAL_EXC_RETURN;
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
-
-        #if ( configENABLE_TRUSTZONE == 1 )
+        /* Simulate the stack frame as it would be created by a context switch
+         * interrupt. */
+        #if ( portPRELOAD_REGISTERS == 0 )
         {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
-        }
-        #endif /* configENABLE_TRUSTZONE */
-    }
-    #else /* portPRELOAD_REGISTERS */
-    {
-        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
-        pxTopOfStack--;
-        *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
+            pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
+            *pxTopOfStack = portINITIAL_EXC_RETURN;
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+            #if ( configENABLE_TRUSTZONE == 1 )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+            }
+            #endif /* configENABLE_TRUSTZONE */
+        }
+        #else /* portPRELOAD_REGISTERS */
         {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
-        }
-        #endif /* configENABLE_TRUSTZONE */
-    }
-    #endif /* portPRELOAD_REGISTERS */
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
+            pxTopOfStack--;
+            *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack;            /* Slot used to hold this task's PSPLIM value. */
 
-    return pxTopOfStack;
-}
+            #if ( configENABLE_TRUSTZONE == 1 )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+            }
+            #endif /* configENABLE_TRUSTZONE */
+        }
+        #endif /* portPRELOAD_REGISTERS */
+
+        return pxTopOfStack;
+    }
 
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM85/non_secure/portasm.c b/portable/GCC/ARM_CM85/non_secure/portasm.c
index f7ec7d9c0..ba8f6c62d 100644
--- a/portable/GCC/ARM_CM85/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM85/non_secure/portasm.c
@@ -42,116 +42,116 @@
 
 #if ( configENABLE_MPU == 1 )
 
-void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        " .syntax unified                                 \n"
-        "                                                 \n"
-        " program_mpu_first_task:                         \n"
-        "    ldr r3, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB. */
-        "                                                 \n"
-        "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-        "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
-        "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
-        "    str r2, [r1]                                 \n" /* Disable MPU. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
-        "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-        "    ldr r2, xMAIR0Const2                         \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-        "    str r1, [r2]                                 \n" /* Program MAIR0. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-        "    ldr r1, xRNRConst2                           \n" /* r1 = 0xe000ed98 [Location of RNR]. */
-        "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "                                                 \n"
-        "    movs r3, #4                                  \n" /* r3 = 4. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 4. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-        "                                                 \n"
-        #if ( configTOTAL_MPU_REGIONS == 16 )
-        "    movs r3, #8                                  \n" /* r3 = 8. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 8. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-        "    movs r3, #12                                 \n" /* r3 = 12. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 12. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-        #endif /* configTOTAL_MPU_REGIONS == 16 */
-        "                                                 \n"
-        "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
-        "    orr r2, #1                                   \n" /* r2 = r1 | 1 i.e. Set the bit 0 in r2. */
-        "    str r2, [r1]                                 \n" /* Enable MPU. */
-        "    dsb                                          \n" /* Force memory writes before continuing. */
-        "                                                 \n"
-        " restore_context_first_task:                     \n"
-        "    ldr r3, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r1, [r3]                                 \n" /* r1 = pxCurrentTCB.*/
-        "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
-        "                                                 \n"
-        " restore_special_regs_first_task:                \n"
-        "    ldmdb r2!, {r0, r3-r5, lr}                   \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
-        "    msr psp, r3                                  \n"
-        "    msr psplim, r4                               \n"
-        "    msr control, r5                              \n"
-        "    ldr r4, xSecureContextConst2                 \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-        "    str r0, [r4]                                 \n" /* Restore xSecureContext. */
-        "                                                 \n"
-        " restore_general_regs_first_task:                \n"
-        "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
-        "    stmia r3!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
-        "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 restored. */
-        "                                                 \n"
-        " restore_context_done_first_task:                \n"
-        "    str r2, [r1]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
-        "    mov r0, #0                                   \n"
-        "    msr basepri, r0                              \n" /* Ensure that interrupts are enabled when the first task starts. */
-        "    bx lr                                        \n"
-        "                                                 \n"
-        " .align 4                                        \n"
-        " pxCurrentTCBConst2: .word pxCurrentTCB          \n"
-        " xSecureContextConst2: .word xSecureContext      \n"
-        " xMPUCTRLConst2: .word 0xe000ed94                \n"
-        " xMAIR0Const2: .word 0xe000edc0                  \n"
-        " xRNRConst2: .word 0xe000ed98                    \n"
-        " xRBARConst2: .word 0xe000ed9c                   \n"
-    );
-}
+    void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                 \n"
+            "                                                 \n"
+            " program_mpu_first_task:                         \n"
+            "    ldr r3, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB. */
+            "                                                 \n"
+            "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
+            "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
+            "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
+            "    str r2, [r1]                                 \n" /* Disable MPU. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
+            "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
+            "    ldr r2, xMAIR0Const2                         \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    str r1, [r2]                                 \n" /* Program MAIR0. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
+            "    ldr r1, xRNRConst2                           \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "                                                 \n"
+            "    movs r3, #4                                  \n" /* r3 = 4. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 4. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "                                                 \n"
+            #if ( configTOTAL_MPU_REGIONS == 16 )
+                "    movs r3, #8                                  \n" /* r3 = 8. */
+                "    str r3, [r1]                                 \n" /* Program RNR = 8. */
+                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
+                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+                "    movs r3, #12                                 \n" /* r3 = 12. */
+                "    str r3, [r1]                                 \n" /* Program RNR = 12. */
+                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
+                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            #endif /* configTOTAL_MPU_REGIONS == 16 */
+            "                                                 \n"
+            "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
+            "    orr r2, #1                                   \n" /* r2 = r1 | 1 i.e. Set the bit 0 in r2. */
+            "    str r2, [r1]                                 \n" /* Enable MPU. */
+            "    dsb                                          \n" /* Force memory writes before continuing. */
+            "                                                 \n"
+            " restore_context_first_task:                     \n"
+            "    ldr r3, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r1, [r3]                                 \n" /* r1 = pxCurrentTCB.*/
+            "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
+            "                                                 \n"
+            " restore_special_regs_first_task:                \n"
+            "    ldmdb r2!, {r0, r3-r5, lr}                   \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
+            "    msr psp, r3                                  \n"
+            "    msr psplim, r4                               \n"
+            "    msr control, r5                              \n"
+            "    ldr r4, xSecureContextConst2                 \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "    str r0, [r4]                                 \n" /* Restore xSecureContext. */
+            "                                                 \n"
+            " restore_general_regs_first_task:                \n"
+            "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
+            "    stmia r3!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
+            "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 restored. */
+            "                                                 \n"
+            " restore_context_done_first_task:                \n"
+            "    str r2, [r1]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
+            "    mov r0, #0                                   \n"
+            "    msr basepri, r0                              \n" /* Ensure that interrupts are enabled when the first task starts. */
+            "    bx lr                                        \n"
+            "                                                 \n"
+            " .align 4                                        \n"
+            " pxCurrentTCBConst2: .word pxCurrentTCB          \n"
+            " xSecureContextConst2: .word xSecureContext      \n"
+            " xMPUCTRLConst2: .word 0xe000ed94                \n"
+            " xMAIR0Const2: .word 0xe000edc0                  \n"
+            " xRNRConst2: .word 0xe000ed98                    \n"
+            " xRBARConst2: .word 0xe000ed9c                   \n"
+        );
+    }
 
 #else /* configENABLE_MPU */
 
-void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "   .syntax unified                                 \n"
-        "                                                   \n"
-        "   ldr  r2, pxCurrentTCBConst2                     \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr  r3, [r2]                                   \n" /* Read pxCurrentTCB. */
-        "   ldr  r0, [r3]                                   \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
-        "                                                   \n"
-        "   ldm  r0!, {r1-r3}                               \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
-        "   ldr  r4, xSecureContextConst2                   \n"
-        "   str  r1, [r4]                                   \n" /* Set xSecureContext to this task's value for the same. */
-        "   msr  psplim, r2                                 \n" /* Set this task's PSPLIM value. */
-        "   movs r1, #2                                     \n" /* r1 = 2. */
-        "   msr  CONTROL, r1                                \n" /* Switch to use PSP in the thread mode. */
-        "   adds r0, #32                                    \n" /* Discard everything up to r0. */
-        "   msr  psp, r0                                    \n" /* This is now the new top of stack to use in the task. */
-        "   isb                                             \n"
-        "   mov  r0, #0                                     \n"
-        "   msr  basepri, r0                                \n" /* Ensure that interrupts are enabled when the first task starts. */
-        "   bx   r3                                         \n" /* Finally, branch to EXC_RETURN. */
-        "   .align 4                                        \n"
-        "pxCurrentTCBConst2: .word pxCurrentTCB             \n"
-        "xSecureContextConst2: .word xSecureContext         \n"
-    );
-}
+    void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            "   .syntax unified                                 \n"
+            "                                                   \n"
+            "   ldr  r2, pxCurrentTCBConst2                     \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr  r3, [r2]                                   \n" /* Read pxCurrentTCB. */
+            "   ldr  r0, [r3]                                   \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+            "                                                   \n"
+            "   ldm  r0!, {r1-r3}                               \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
+            "   ldr  r4, xSecureContextConst2                   \n"
+            "   str  r1, [r4]                                   \n" /* Set xSecureContext to this task's value for the same. */
+            "   msr  psplim, r2                                 \n" /* Set this task's PSPLIM value. */
+            "   movs r1, #2                                     \n" /* r1 = 2. */
+            "   msr  CONTROL, r1                                \n" /* Switch to use PSP in the thread mode. */
+            "   adds r0, #32                                    \n" /* Discard everything up to r0. */
+            "   msr  psp, r0                                    \n" /* This is now the new top of stack to use in the task. */
+            "   isb                                             \n"
+            "   mov  r0, #0                                     \n"
+            "   msr  basepri, r0                                \n" /* Ensure that interrupts are enabled when the first task starts. */
+            "   bx   r3                                         \n" /* Finally, branch to EXC_RETURN. */
+            "   .align 4                                        \n"
+            "pxCurrentTCBConst2: .word pxCurrentTCB             \n"
+            "xSecureContextConst2: .word xSecureContext         \n"
+        );
+    }
 
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
@@ -162,12 +162,12 @@ BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs r0, control                                 \n"/* r0 = CONTROL. */
-        "   tst r0, #1                                      \n"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+        "   mrs r0, control                                 \n" /* r0 = CONTROL. */
+        "   tst r0, #1                                      \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
         "   ite ne                                          \n"
-        "   movne r0, #0                                    \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
-        "   moveq r0, #1                                    \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
-        "   bx lr                                           \n"/* Return. */
+        "   movne r0, #0                                    \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+        "   moveq r0, #1                                    \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+        "   bx lr                                           \n" /* Return. */
         "                                                   \n"
         "   .align 4                                        \n"
         ::: "r0", "memory"
@@ -181,10 +181,10 @@ void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs r0, control                                 \n"/* Read the CONTROL register. */
-        "   bic r0, #1                                      \n"/* Clear the bit 0. */
-        "   msr control, r0                                 \n"/* Write back the new CONTROL value. */
-        "   bx lr                                           \n"/* Return to the caller. */
+        "   mrs r0, control                                 \n" /* Read the CONTROL register. */
+        "   bic r0, #1                                      \n" /* Clear the bit 0. */
+        "   msr control, r0                                 \n" /* Write back the new CONTROL value. */
+        "   bx lr                                           \n" /* Return to the caller. */
         ::: "r0", "memory"
     );
 }
@@ -196,10 +196,10 @@ void vResetPrivilege( void ) /* __attribute__ (( naked )) */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs r0, control                                 \n"/* r0 = CONTROL. */
-        "   orr r0, #1                                      \n"/* r0 = r0 | 1. */
-        "   msr control, r0                                 \n"/* CONTROL = r0. */
-        "   bx lr                                           \n"/* Return to the caller. */
+        "   mrs r0, control                                 \n" /* r0 = CONTROL. */
+        "   orr r0, #1                                      \n" /* r0 = r0 | 1. */
+        "   msr control, r0                                 \n" /* CONTROL = r0. */
+        "   bx lr                                           \n" /* Return to the caller. */
         ::: "r0", "memory"
     );
 }
@@ -211,15 +211,15 @@ void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   ldr r0, xVTORConst                              \n"/* Use the NVIC offset register to locate the stack. */
-        "   ldr r0, [r0]                                    \n"/* Read the VTOR register which gives the address of vector table. */
-        "   ldr r0, [r0]                                    \n"/* The first entry in vector table is stack pointer. */
-        "   msr msp, r0                                     \n"/* Set the MSP back to the start of the stack. */
-        "   cpsie i                                         \n"/* Globally enable interrupts. */
+        "   ldr r0, xVTORConst                              \n" /* Use the NVIC offset register to locate the stack. */
+        "   ldr r0, [r0]                                    \n" /* Read the VTOR register which gives the address of vector table. */
+        "   ldr r0, [r0]                                    \n" /* The first entry in vector table is stack pointer. */
+        "   msr msp, r0                                     \n" /* Set the MSP back to the start of the stack. */
+        "   cpsie i                                         \n" /* Globally enable interrupts. */
         "   cpsie f                                         \n"
         "   dsb                                             \n"
         "   isb                                             \n"
-        "   svc %0                                          \n"/* System call to start the first task. */
+        "   svc %0                                          \n" /* System call to start the first task. */
         "   nop                                             \n"
         "                                                   \n"
         "   .align 4                                        \n"
@@ -235,12 +235,12 @@ uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCT
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs r0, basepri                                 \n"/* r0 = basepri. Return original basepri value. */
-        "   mov r1, %0                                      \n"/* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        "   msr basepri, r1                                 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        "   mrs r0, basepri                                 \n" /* r0 = basepri. Return original basepri value. */
+        "   mov r1, %0                                      \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        "   msr basepri, r1                                 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
         "   dsb                                             \n"
         "   isb                                             \n"
-        "   bx lr                                           \n"/* Return. */
+        "   bx lr                                           \n" /* Return. */
         ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
     );
 }
@@ -252,10 +252,10 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   msr basepri, r0                                 \n"/* basepri = ulMask. */
+        "   msr basepri, r0                                 \n" /* basepri = ulMask. */
         "   dsb                                             \n"
         "   isb                                             \n"
-        "   bx lr                                           \n"/* Return. */
+        "   bx lr                                           \n" /* Return. */
         ::: "memory"
     );
 }
@@ -263,320 +263,320 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
 
 #if ( configENABLE_MPU == 1 )
 
-void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        " .syntax unified                                 \n"
-        " .extern SecureContext_SaveContext               \n"
-        " .extern SecureContext_LoadContext               \n"
-        "                                                 \n"
-        " ldr r3, xSecureContextConst                     \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-        " ldr r0, [r3]                                    \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
-        " ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        " ldr r1, [r3]                                    \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
-        " ldr r2, [r1]                                    \n" /* r2 = Location in TCB where the context should be saved. */
-        "                                                 \n"
-        " cbz r0, save_ns_context                         \n" /* No secure context to save. */
-        " save_s_context:                                 \n"
-        "    push {r0-r2, lr}                             \n"
-        "    bl SecureContext_SaveContext                 \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-        "    pop {r0-r2, lr}                              \n"
-        "                                                 \n"
-        " save_ns_context:                                \n"
-        "    mov r3, lr                                   \n" /* r3 = LR (EXC_RETURN). */
-        "    lsls r3, r3, #25                             \n" /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-        "    bmi save_special_regs                        \n" /* r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
-        "                                                 \n"
-        " save_general_regs:                              \n"
-        "    mrs r3, psp                                  \n"
-        "                                                 \n"
-    #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-        "    add r3, r3, #0x20                            \n" /* Move r3 to location where s0 is saved. */
-        "    tst lr, #0x10                                \n"
-        "    ittt eq                                      \n"
-        "    vstmiaeq r2!, {s16-s31}                      \n" /* Store s16-s31. */
-        "    vldmiaeq r3, {s0-s16}                        \n" /* Copy hardware saved FP context into s0-s16. */
-        "    vstmiaeq r2!, {s0-s16}                       \n" /* Store hardware saved FP context. */
-        "    sub r3, r3, #0x20                            \n" /* Set r3 back to the location of hardware saved context. */
-    #endif /* configENABLE_FPU || configENABLE_MVE */
-        "                                                 \n"
-        "    stmia r2!, {r4-r11}                          \n" /* Store r4-r11. */
-        "    ldmia r3, {r4-r11}                           \n" /* Copy the hardware saved context into r4-r11. */
-        "    stmia r2!, {r4-r11}                          \n" /* Store the hardware saved context. */
-        "                                                 \n"
-        " save_special_regs:                              \n"
-        "    mrs r3, psp                                  \n" /* r3 = PSP. */
-        "    mrs r4, psplim                               \n" /* r4 = PSPLIM. */
-        "    mrs r5, control                              \n" /* r5 = CONTROL. */
-        "    stmia r2!, {r0, r3-r5, lr}                   \n" /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
-        "    str r2, [r1]                                 \n" /* Save the location from where the context should be restored as the first member of TCB. */
-        "                                                 \n"
-        " select_next_task:                               \n"
-        "    mov r0, %0                                   \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
-        "    msr basepri, r0                              \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        "    dsb                                          \n"
-        "    isb                                          \n"
-        "    bl vTaskSwitchContext                        \n"
-        "    mov r0, #0                                   \n" /* r0 = 0. */
-        "    msr basepri, r0                              \n" /* Enable interrupts. */
-        "                                                 \n"
-        " program_mpu:                                    \n"
-        "    ldr r3, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB.*/
-        "                                                 \n"
-        "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-        "    ldr r1, xMPUCTRLConst                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
-        "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
-        "    str r2, [r1]                                 \n" /* Disable MPU. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
-        "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-        "    ldr r2, xMAIR0Const                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-        "    str r1, [r2]                                 \n" /* Program MAIR0. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-        "    ldr r1, xRNRConst                            \n" /* r1 = 0xe000ed98 [Location of RNR]. */
-        "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "                                                 \n"
-        "    movs r3, #4                                  \n" /* r3 = 4. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 4. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-        "                                                 \n"
-        #if ( configTOTAL_MPU_REGIONS == 16 )
-        "    movs r3, #8                                  \n" /* r3 = 8. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 8. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-        "    movs r3, #12                                 \n" /* r3 = 12. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 12. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-        #endif /* configTOTAL_MPU_REGIONS == 16 */
-        "                                                 \n"
-        "   ldr r1, xMPUCTRLConst                         \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
-        "   orr r2, #1                                    \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
-        "   str r2, [r1]                                  \n" /* Enable MPU. */
-        "   dsb                                           \n" /* Force memory writes before continuing. */
-        "                                                 \n"
-        " restore_context:                                \n"
-        "    ldr r3, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r1, [r3]                                 \n" /* r1 = pxCurrentTCB.*/
-        "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
-        "                                                 \n"
-        " restore_special_regs:                           \n"
-        "    ldmdb r2!, {r0, r3-r5, lr}                   \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
-        "    msr psp, r3                                  \n"
-        "    msr psplim, r4                               \n"
-        "    msr control, r5                              \n"
-        "    ldr r4, xSecureContextConst                  \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-        "    str r0, [r4]                                 \n" /* Restore xSecureContext. */
-        "    cbz r0, restore_ns_context                   \n" /* No secure context to restore. */
-        "                                                 \n"
-        " restore_s_context:                              \n"
-        "    push {r1-r3, lr}                             \n"
-        "    bl SecureContext_LoadContext                 \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-        "    pop {r1-r3, lr}                              \n"
-        "                                                 \n"
-        " restore_ns_context:                             \n"
-        "    mov r0, lr                                   \n" /* r0 = LR (EXC_RETURN). */
-        "    lsls r0, r0, #25                             \n" /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-        "    bmi restore_context_done                     \n" /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
-        "                                                 \n"
-        " restore_general_regs:                           \n"
-        "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
-        "    stmia r3!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
-        "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 restored. */
-    #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-        "    tst lr, #0x10                                \n"
-        "    ittt eq                                      \n"
-        "    vldmdbeq r2!, {s0-s16}                       \n" /* s0-s16 contain hardware saved FP context. */
-        "    vstmiaeq r3!, {s0-s16}                       \n" /* Copy hardware saved FP context on the task stack. */
-        "    vldmdbeq r2!, {s16-s31}                      \n" /* Restore s16-s31. */
-    #endif /* configENABLE_FPU || configENABLE_MVE */
-        "                                                 \n"
-        " restore_context_done:                           \n"
-        "    str r2, [r1]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
-        "    bx lr                                        \n"
-        "                                                 \n"
-        " .align 4                                        \n"
-        " pxCurrentTCBConst: .word pxCurrentTCB           \n"
-        " xSecureContextConst: .word xSecureContext       \n"
-        " xMPUCTRLConst: .word 0xe000ed94                 \n"
-        " xMAIR0Const: .word 0xe000edc0                   \n"
-        " xRNRConst: .word 0xe000ed98                     \n"
-        " xRBARConst: .word 0xe000ed9c                    \n"
-        ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
-    );
-}
+    void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                 \n"
+            " .extern SecureContext_SaveContext               \n"
+            " .extern SecureContext_LoadContext               \n"
+            "                                                 \n"
+            " ldr r3, xSecureContextConst                     \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            " ldr r0, [r3]                                    \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+            " ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            " ldr r1, [r3]                                    \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
+            " ldr r2, [r1]                                    \n" /* r2 = Location in TCB where the context should be saved. */
+            "                                                 \n"
+            " cbz r0, save_ns_context                         \n" /* No secure context to save. */
+            " save_s_context:                                 \n"
+            "    push {r0-r2, lr}                             \n"
+            "    bl SecureContext_SaveContext                 \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+            "    pop {r0-r2, lr}                              \n"
+            "                                                 \n"
+            " save_ns_context:                                \n"
+            "    mov r3, lr                                   \n" /* r3 = LR (EXC_RETURN). */
+            "    lsls r3, r3, #25                             \n" /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+            "    bmi save_special_regs                        \n" /* r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
+            "                                                 \n"
+            " save_general_regs:                              \n"
+            "    mrs r3, psp                                  \n"
+            "                                                 \n"
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+                "    add r3, r3, #0x20                            \n" /* Move r3 to location where s0 is saved. */
+                "    tst lr, #0x10                                \n"
+                "    ittt eq                                      \n"
+                "    vstmiaeq r2!, {s16-s31}                      \n" /* Store s16-s31. */
+                "    vldmiaeq r3, {s0-s16}                        \n" /* Copy hardware saved FP context into s0-s16. */
+                "    vstmiaeq r2!, {s0-s16}                       \n" /* Store hardware saved FP context. */
+                "    sub r3, r3, #0x20                            \n" /* Set r3 back to the location of hardware saved context. */
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+            "                                                 \n"
+            "    stmia r2!, {r4-r11}                          \n" /* Store r4-r11. */
+            "    ldmia r3, {r4-r11}                           \n" /* Copy the hardware saved context into r4-r11. */
+            "    stmia r2!, {r4-r11}                          \n" /* Store the hardware saved context. */
+            "                                                 \n"
+            " save_special_regs:                              \n"
+            "    mrs r3, psp                                  \n" /* r3 = PSP. */
+            "    mrs r4, psplim                               \n" /* r4 = PSPLIM. */
+            "    mrs r5, control                              \n" /* r5 = CONTROL. */
+            "    stmia r2!, {r0, r3-r5, lr}                   \n" /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
+            "    str r2, [r1]                                 \n" /* Save the location from where the context should be restored as the first member of TCB. */
+            "                                                 \n"
+            " select_next_task:                               \n"
+            "    mov r0, %0                                   \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
+            "    msr basepri, r0                              \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+            "    dsb                                          \n"
+            "    isb                                          \n"
+            "    bl vTaskSwitchContext                        \n"
+            "    mov r0, #0                                   \n" /* r0 = 0. */
+            "    msr basepri, r0                              \n" /* Enable interrupts. */
+            "                                                 \n"
+            " program_mpu:                                    \n"
+            "    ldr r3, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB.*/
+            "                                                 \n"
+            "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
+            "    ldr r1, xMPUCTRLConst                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
+            "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
+            "    str r2, [r1]                                 \n" /* Disable MPU. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
+            "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
+            "    ldr r2, xMAIR0Const                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    str r1, [r2]                                 \n" /* Program MAIR0. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
+            "    ldr r1, xRNRConst                            \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "                                                 \n"
+            "    movs r3, #4                                  \n" /* r3 = 4. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 4. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "                                                 \n"
+            #if ( configTOTAL_MPU_REGIONS == 16 )
+                "    movs r3, #8                                  \n" /* r3 = 8. */
+                "    str r3, [r1]                                 \n" /* Program RNR = 8. */
+                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+                "    movs r3, #12                                 \n" /* r3 = 12. */
+                "    str r3, [r1]                                 \n" /* Program RNR = 12. */
+                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            #endif /* configTOTAL_MPU_REGIONS == 16 */
+            "                                                 \n"
+            "   ldr r1, xMPUCTRLConst                         \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
+            "   orr r2, #1                                    \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
+            "   str r2, [r1]                                  \n" /* Enable MPU. */
+            "   dsb                                           \n" /* Force memory writes before continuing. */
+            "                                                 \n"
+            " restore_context:                                \n"
+            "    ldr r3, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r1, [r3]                                 \n" /* r1 = pxCurrentTCB.*/
+            "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
+            "                                                 \n"
+            " restore_special_regs:                           \n"
+            "    ldmdb r2!, {r0, r3-r5, lr}                   \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
+            "    msr psp, r3                                  \n"
+            "    msr psplim, r4                               \n"
+            "    msr control, r5                              \n"
+            "    ldr r4, xSecureContextConst                  \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "    str r0, [r4]                                 \n" /* Restore xSecureContext. */
+            "    cbz r0, restore_ns_context                   \n" /* No secure context to restore. */
+            "                                                 \n"
+            " restore_s_context:                              \n"
+            "    push {r1-r3, lr}                             \n"
+            "    bl SecureContext_LoadContext                 \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+            "    pop {r1-r3, lr}                              \n"
+            "                                                 \n"
+            " restore_ns_context:                             \n"
+            "    mov r0, lr                                   \n" /* r0 = LR (EXC_RETURN). */
+            "    lsls r0, r0, #25                             \n" /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+            "    bmi restore_context_done                     \n" /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
+            "                                                 \n"
+            " restore_general_regs:                           \n"
+            "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
+            "    stmia r3!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
+            "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 restored. */
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+                "    tst lr, #0x10                                \n"
+                "    ittt eq                                      \n"
+                "    vldmdbeq r2!, {s0-s16}                       \n" /* s0-s16 contain hardware saved FP context. */
+                "    vstmiaeq r3!, {s0-s16}                       \n" /* Copy hardware saved FP context on the task stack. */
+                "    vldmdbeq r2!, {s16-s31}                      \n" /* Restore s16-s31. */
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+            "                                                 \n"
+            " restore_context_done:                           \n"
+            "    str r2, [r1]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
+            "    bx lr                                        \n"
+            "                                                 \n"
+            " .align 4                                        \n"
+            " pxCurrentTCBConst: .word pxCurrentTCB           \n"
+            " xSecureContextConst: .word xSecureContext       \n"
+            " xMPUCTRLConst: .word 0xe000ed94                 \n"
+            " xMAIR0Const: .word 0xe000edc0                   \n"
+            " xRNRConst: .word 0xe000ed98                     \n"
+            " xRBARConst: .word 0xe000ed9c                    \n"
+            ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+        );
+    }
 
 #else /* configENABLE_MPU */
 
-void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "   .syntax unified                                 \n"
-        "   .extern SecureContext_SaveContext               \n"
-        "   .extern SecureContext_LoadContext               \n"
-        "                                                   \n"
-        "   ldr r3, xSecureContextConst                     \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
-        "   ldr r0, [r3]                                    \n"/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
-        "   ldr r3, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r3]                                    \n"/* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
-        "   mrs r2, psp                                     \n"/* Read PSP in r2. */
-        "                                                   \n"
-        "   cbz r0, save_ns_context                         \n"/* No secure context to save. */
-        "   push {r0-r2, r14}                               \n"
-        "   bl SecureContext_SaveContext                    \n"/* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-        "   pop {r0-r3}                                     \n"/* LR is now in r3. */
-        "   mov lr, r3                                      \n"/* LR = r3. */
-        "   lsls r1, r3, #25                                \n"/* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-        "   bpl save_ns_context                             \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-        "                                                   \n"
-        "   ldr r3, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r3]                                    \n"/* Read pxCurrentTCB.*/
-        "   subs r2, r2, #12                                \n"/* Make space for xSecureContext, PSPLIM and LR on the stack. */
-        "   str r2, [r1]                                    \n"/* Save the new top of stack in TCB. */
-        "   mrs r1, psplim                                  \n"/* r1 = PSPLIM. */
-        "   mov r3, lr                                      \n"/* r3 = LR/EXC_RETURN. */
-        "   stmia r2!, {r0, r1, r3}                         \n"/* Store xSecureContext, PSPLIM and LR on the stack. */
-        "   b select_next_task                              \n"
-        "                                                   \n"
-        " save_ns_context:                                  \n"
-        "   ldr r3, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r3]                                    \n"/* Read pxCurrentTCB. */
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-            "   tst lr, #0x10                               \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
-            "   it eq                                       \n"
-            "   vstmdbeq r2!, {s16-s31}                     \n"/* Store the additional FP context registers which are not saved automatically. */
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-        "   subs r2, r2, #44                                \n"/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
-        "   str r2, [r1]                                    \n"/* Save the new top of stack in TCB. */
-        "   adds r2, r2, #12                                \n"/* r2 = r2 + 12. */
-        "   stm r2, {r4-r11}                                \n"/* Store the registers that are not saved automatically. */
-        "   mrs r1, psplim                                  \n"/* r1 = PSPLIM. */
-        "   mov r3, lr                                      \n"/* r3 = LR/EXC_RETURN. */
-        "   subs r2, r2, #12                                \n"/* r2 = r2 - 12. */
-        "   stmia r2!, {r0, r1, r3}                         \n"/* Store xSecureContext, PSPLIM and LR on the stack. */
-        "                                                   \n"
-        " select_next_task:                                 \n"
-        "   mov r0, %0                                      \n"/* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
-        "   msr basepri, r0                                 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        "   dsb                                             \n"
-        "   isb                                             \n"
-        "   bl vTaskSwitchContext                           \n"
-        "   mov r0, #0                                      \n"/* r0 = 0. */
-        "   msr basepri, r0                                 \n"/* Enable interrupts. */
-        "                                                   \n"
-        "   ldr r3, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r3]                                    \n"/* Read pxCurrentTCB. */
-        "   ldr r2, [r1]                                    \n"/* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
-        "                                                   \n"
-        "   ldmia r2!, {r0, r1, r4}                         \n"/* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
-        "   msr psplim, r1                                  \n"/* Restore the PSPLIM register value for the task. */
-        "   mov lr, r4                                      \n"/* LR = r4. */
-        "   ldr r3, xSecureContextConst                     \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
-        "   str r0, [r3]                                    \n"/* Restore the task's xSecureContext. */
-        "   cbz r0, restore_ns_context                      \n"/* If there is no secure context for the task, restore the non-secure context. */
-        "   ldr r3, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r3]                                    \n"/* Read pxCurrentTCB. */
-        "   push {r2, r4}                                   \n"
-        "   bl SecureContext_LoadContext                    \n"/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-        "   pop {r2, r4}                                    \n"
-        "   mov lr, r4                                      \n"/* LR = r4. */
-        "   lsls r1, r4, #25                                \n"/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-        "   bpl restore_ns_context                          \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-        "   msr psp, r2                                     \n"/* Remember the new top of stack for the task. */
-        "   bx lr                                           \n"
-        "                                                   \n"
-        " restore_ns_context:                               \n"
-        "   ldmia r2!, {r4-r11}                             \n"/* Restore the registers that are not automatically restored. */
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-            "   tst lr, #0x10                               \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
-            "   it eq                                       \n"
-            "   vldmiaeq r2!, {s16-s31}                     \n"/* Restore the additional FP context registers which are not restored automatically. */
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-        "   msr psp, r2                                     \n"/* Remember the new top of stack for the task. */
-        "   bx lr                                           \n"
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "pxCurrentTCBConst: .word pxCurrentTCB              \n"
-        "xSecureContextConst: .word xSecureContext          \n"
-        ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
-    );
-}
+    void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            "   .syntax unified                                 \n"
+            "   .extern SecureContext_SaveContext               \n"
+            "   .extern SecureContext_LoadContext               \n"
+            "                                                   \n"
+            "   ldr r3, xSecureContextConst                     \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "   ldr r0, [r3]                                    \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
+            "   mrs r2, psp                                     \n" /* Read PSP in r2. */
+            "                                                   \n"
+            "   cbz r0, save_ns_context                         \n" /* No secure context to save. */
+            "   push {r0-r2, r14}                               \n"
+            "   bl SecureContext_SaveContext                    \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+            "   pop {r0-r3}                                     \n" /* LR is now in r3. */
+            "   mov lr, r3                                      \n" /* LR = r3. */
+            "   lsls r1, r3, #25                                \n" /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+            "   bpl save_ns_context                             \n" /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+            "                                                   \n"
+            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB.*/
+            "   subs r2, r2, #12                                \n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */
+            "   str r2, [r1]                                    \n" /* Save the new top of stack in TCB. */
+            "   mrs r1, psplim                                  \n" /* r1 = PSPLIM. */
+            "   mov r3, lr                                      \n" /* r3 = LR/EXC_RETURN. */
+            "   stmia r2!, {r0, r1, r3}                         \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
+            "   b select_next_task                              \n"
+            "                                                   \n"
+            " save_ns_context:                                  \n"
+            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+                "   tst lr, #0x10                               \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+                "   it eq                                       \n"
+                "   vstmdbeq r2!, {s16-s31}                     \n" /* Store the additional FP context registers which are not saved automatically. */
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+            "   subs r2, r2, #44                                \n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
+            "   str r2, [r1]                                    \n" /* Save the new top of stack in TCB. */
+            "   adds r2, r2, #12                                \n" /* r2 = r2 + 12. */
+            "   stm r2, {r4-r11}                                \n" /* Store the registers that are not saved automatically. */
+            "   mrs r1, psplim                                  \n" /* r1 = PSPLIM. */
+            "   mov r3, lr                                      \n" /* r3 = LR/EXC_RETURN. */
+            "   subs r2, r2, #12                                \n" /* r2 = r2 - 12. */
+            "   stmia r2!, {r0, r1, r3}                         \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
+            "                                                   \n"
+            " select_next_task:                                 \n"
+            "   mov r0, %0                                      \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
+            "   msr basepri, r0                                 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+            "   dsb                                             \n"
+            "   isb                                             \n"
+            "   bl vTaskSwitchContext                           \n"
+            "   mov r0, #0                                      \n" /* r0 = 0. */
+            "   msr basepri, r0                                 \n" /* Enable interrupts. */
+            "                                                   \n"
+            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
+            "   ldr r2, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
+            "                                                   \n"
+            "   ldmia r2!, {r0, r1, r4}                         \n" /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
+            "   msr psplim, r1                                  \n" /* Restore the PSPLIM register value for the task. */
+            "   mov lr, r4                                      \n" /* LR = r4. */
+            "   ldr r3, xSecureContextConst                     \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "   str r0, [r3]                                    \n" /* Restore the task's xSecureContext. */
+            "   cbz r0, restore_ns_context                      \n" /* If there is no secure context for the task, restore the non-secure context. */
+            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
+            "   push {r2, r4}                                   \n"
+            "   bl SecureContext_LoadContext                    \n" /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+            "   pop {r2, r4}                                    \n"
+            "   mov lr, r4                                      \n" /* LR = r4. */
+            "   lsls r1, r4, #25                                \n" /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+            "   bpl restore_ns_context                          \n" /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+            "   msr psp, r2                                     \n" /* Remember the new top of stack for the task. */
+            "   bx lr                                           \n"
+            "                                                   \n"
+            " restore_ns_context:                               \n"
+            "   ldmia r2!, {r4-r11}                             \n" /* Restore the registers that are not automatically restored. */
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+                "   tst lr, #0x10                               \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+                "   it eq                                       \n"
+                "   vldmiaeq r2!, {s16-s31}                     \n" /* Restore the additional FP context registers which are not restored automatically. */
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+            "   msr psp, r2                                     \n" /* Remember the new top of stack for the task. */
+            "   bx lr                                           \n"
+            "                                                   \n"
+            "   .align 4                                        \n"
+            "pxCurrentTCBConst: .word pxCurrentTCB              \n"
+            "xSecureContextConst: .word xSecureContext          \n"
+            ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+        );
+    }
 
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-   __asm volatile
-    (
-        ".syntax unified                \n"
-        ".extern vPortSVCHandler_C      \n"
-        ".extern vSystemCallEnter       \n"
-        ".extern vSystemCallEnter_1     \n"
-        ".extern vSystemCallExit        \n"
-        "                               \n"
-        "tst lr, #4                     \n"
-        "ite eq                         \n"
-        "mrseq r0, msp                  \n"
-        "mrsne r0, psp                  \n"
-        "                               \n"
-        "ldr r1, [r0, #24]              \n"
-        "ldrb r2, [r1, #-2]             \n"
-        "cmp r2, %0                     \n"
-        "beq syscall_enter              \n"
-        "cmp r2, %1                     \n"
-        "beq syscall_enter_1            \n"
-        "cmp r2, %2                     \n"
-        "beq syscall_exit               \n"
-        "b vPortSVCHandler_C            \n"
-        "                               \n"
-        "syscall_enter:                 \n"
-        "    mov r1, lr                 \n"
-        "    b vSystemCallEnter         \n"
-        "                               \n"
-        "syscall_enter_1:               \n"
-        "    mov r1, lr                 \n"
-        "    b vSystemCallEnter_1       \n"
-        "                               \n"
-        "syscall_exit:                  \n"
-        "    mov r1, lr                 \n"
-        "    b vSystemCallExit          \n"
-        "                               \n"
-        : /* No outputs. */
-        :"i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT )
-        : "r0", "r1", "r2", "memory"
-    );
-}
+    void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            ".syntax unified                \n"
+            ".extern vPortSVCHandler_C      \n"
+            ".extern vSystemCallEnter       \n"
+            ".extern vSystemCallEnter_1     \n"
+            ".extern vSystemCallExit        \n"
+            "                               \n"
+            "tst lr, #4                     \n"
+            "ite eq                         \n"
+            "mrseq r0, msp                  \n"
+            "mrsne r0, psp                  \n"
+            "                               \n"
+            "ldr r1, [r0, #24]              \n"
+            "ldrb r2, [r1, #-2]             \n"
+            "cmp r2, %0                     \n"
+            "beq syscall_enter              \n"
+            "cmp r2, %1                     \n"
+            "beq syscall_enter_1            \n"
+            "cmp r2, %2                     \n"
+            "beq syscall_exit               \n"
+            "b vPortSVCHandler_C            \n"
+            "                               \n"
+            "syscall_enter:                 \n"
+            "    mov r1, lr                 \n"
+            "    b vSystemCallEnter         \n"
+            "                               \n"
+            "syscall_enter_1:               \n"
+            "    mov r1, lr                 \n"
+            "    b vSystemCallEnter_1       \n"
+            "                               \n"
+            "syscall_exit:                  \n"
+            "    mov r1, lr                 \n"
+            "    b vSystemCallExit          \n"
+            "                               \n"
+            : /* No outputs. */
+            : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT )
+            : "r0", "r1", "r2", "memory"
+        );
+    }
 
 #else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
-void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "   .syntax unified                                 \n"
-        "                                                   \n"
-        "   tst lr, #4                                      \n"
-        "   ite eq                                          \n"
-        "   mrseq r0, msp                                   \n"
-        "   mrsne r0, psp                                   \n"
-        "   ldr r1, svchandler_address_const                \n"
-        "   bx r1                                           \n"
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "svchandler_address_const: .word vPortSVCHandler_C  \n"
-    );
-}
+    void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            "   .syntax unified                                 \n"
+            "                                                   \n"
+            "   tst lr, #4                                      \n"
+            "   ite eq                                          \n"
+            "   mrseq r0, msp                                   \n"
+            "   mrsne r0, psp                                   \n"
+            "   ldr r1, svchandler_address_const                \n"
+            "   bx r1                                           \n"
+            "                                                   \n"
+            "   .align 4                                        \n"
+            "svchandler_address_const: .word vPortSVCHandler_C  \n"
+        );
+    }
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
@@ -587,8 +587,8 @@ void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   svc %0                                          \n"/* Secure context is allocated in the supervisor call. */
-        "   bx lr                                           \n"/* Return. */
+        "   svc %0                                          \n" /* Secure context is allocated in the supervisor call. */
+        "   bx lr                                           \n" /* Return. */
         ::"i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"
     );
 }
@@ -600,12 +600,12 @@ void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PR
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   ldr r2, [r0]                                    \n"/* The first item in the TCB is the top of the stack. */
-        "   ldr r1, [r2]                                    \n"/* The first item on the stack is the task's xSecureContext. */
-        "   cmp r1, #0                                      \n"/* Raise svc if task's xSecureContext is not NULL. */
+        "   ldr r2, [r0]                                    \n" /* The first item in the TCB is the top of the stack. */
+        "   ldr r1, [r2]                                    \n" /* The first item on the stack is the task's xSecureContext. */
+        "   cmp r1, #0                                      \n" /* Raise svc if task's xSecureContext is not NULL. */
         "   it ne                                           \n"
-        "   svcne %0                                        \n"/* Secure context is freed in the supervisor call. */
-        "   bx lr                                           \n"/* Return. */
+        "   svcne %0                                        \n" /* Secure context is freed in the supervisor call. */
+        "   bx lr                                           \n" /* Return. */
         ::"i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"
     );
 }
diff --git a/portable/GCC/ARM_CM85/non_secure/portmacro.h b/portable/GCC/ARM_CM85/non_secure/portmacro.h
index d14448927..a6fda8a88 100644
--- a/portable/GCC/ARM_CM85/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM85/non_secure/portmacro.h
@@ -53,9 +53,9 @@
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME                       "Cortex-M85"
-#define portHAS_ARMV8M_MAIN_EXTENSION       1
-#define portDONT_DISCARD                    __attribute__( ( used ) )
+#define portARCH_NAME                    "Cortex-M85"
+#define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
 /* ARMv8-M common port configurations. */
@@ -65,8 +65,8 @@
 /**
  * @brief Critical section management.
  */
-#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()
-#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )
+#define portDISABLE_INTERRUPTS()    ulSetInterruptMask()
+#define portENABLE_INTERRUPTS()     vClearInterruptMask( 0 )
 /*-----------------------------------------------------------*/
 
 /* *INDENT-OFF* */
diff --git a/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h
index e5ffdb48b..62e462a27 100644
--- a/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h
@@ -81,8 +81,8 @@ typedef unsigned long    UBaseType_t;
     typedef uint32_t     TickType_t;
     #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-     * not need to be guarded with a critical section. */
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
     #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -117,7 +117,7 @@ extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGE
 extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
 
 #if ( configENABLE_TRUSTZONE == 1 )
-    extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize );     /* __attribute__ (( naked )) */
+    extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
     extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
 #endif /* configENABLE_TRUSTZONE */
 
@@ -188,13 +188,13 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Settings to define an MPU region.
-     */
+/**
+ * @brief Settings to define an MPU region.
+ */
     typedef struct MPURegionSettings
     {
-        uint32_t ulRBAR;     /**< RBAR for the region. */
-        uint32_t ulRLAR;     /**< RLAR for the region. */
+        uint32_t ulRBAR; /**< RBAR for the region. */
+        uint32_t ulRLAR; /**< RLAR for the region. */
     } MPURegionSettings_t;
 
     #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
@@ -203,9 +203,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-        /**
-         * @brief System call stack.
-         */
+/**
+ * @brief System call stack.
+ */
         typedef struct SYSTEM_CALL_STACK_INFO
         {
             uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ];
@@ -218,74 +218,74 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
-    /**
-     * @brief MPU settings as stored in the TCB.
-     */
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
     #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
 
-        #if( configENABLE_TRUSTZONE == 1 )
+        #if ( configENABLE_TRUSTZONE == 1 )
 
-            /*
-             * +-----------+---------------+----------+-----------------+------------------------------+-----+
-             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
-             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
-             * +-----------+---------------+----------+-----------------+------------------------------+-----+
-             *
-             * <-----------><--------------><---------><----------------><-----------------------------><---->
-             *      16             16            8               8                     5                   1
-             */
-            #define MAX_CONTEXT_SIZE 54
+/*
+ * +-----------+---------------+----------+-----------------+------------------------------+-----+
+ * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+ * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+ * +-----------+---------------+----------+-----------------+------------------------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><-----------------------------><---->
+ *      16             16            8               8                     5                   1
+ */
+            #define MAX_CONTEXT_SIZE    54
 
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-            /*
-             * +-----------+---------------+----------+-----------------+----------------------+-----+
-             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
-             * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
-             * +-----------+---------------+----------+-----------------+----------------------+-----+
-             *
-             * <-----------><--------------><---------><----------------><---------------------><---->
-             *      16             16            8               8                  4              1
-             */
-            #define MAX_CONTEXT_SIZE 53
+/*
+ * +-----------+---------------+----------+-----------------+----------------------+-----+
+ * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+ * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
+ * +-----------+---------------+----------+-----------------+----------------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><---------------------><---->
+ *      16             16            8               8                  4              1
+ */
+            #define MAX_CONTEXT_SIZE    53
 
         #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
 
     #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-        #if( configENABLE_TRUSTZONE == 1 )
+        #if ( configENABLE_TRUSTZONE == 1 )
 
-            /*
-             * +----------+-----------------+------------------------------+-----+
-             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
-             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
-             * +----------+-----------------+------------------------------+-----+
-             *
-             * <---------><----------------><------------------------------><---->
-             *     8               8                      5                   1
-             */
-            #define MAX_CONTEXT_SIZE 22
+/*
+ * +----------+-----------------+------------------------------+-----+
+ * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+ * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+ * +----------+-----------------+------------------------------+-----+
+ *
+ * <---------><----------------><------------------------------><---->
+ *     8               8                      5                   1
+ */
+            #define MAX_CONTEXT_SIZE    22
 
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-            /*
-             * +----------+-----------------+----------------------+-----+
-             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
-             * |          | PC, xPSR        | EXC_RETURN           |     |
-             * +----------+-----------------+----------------------+-----+
-             *
-             * <---------><----------------><----------------------><---->
-             *     8               8                  4              1
-             */
-            #define MAX_CONTEXT_SIZE 21
+/*
+ * +----------+-----------------+----------------------+-----+
+ * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+ * |          | PC, xPSR        | EXC_RETURN           |     |
+ * +----------+-----------------+----------------------+-----+
+ *
+ * <---------><----------------><----------------------><---->
+ *     8               8                  4              1
+ */
+            #define MAX_CONTEXT_SIZE    21
 
         #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
 
     #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-    /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
-    #define portSTACK_FRAME_HAS_PADDING_FLAG     ( 1UL << 0UL )
-    #define portTASK_IS_PRIVILEGED_FLAG          ( 1UL << 1UL )
+/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
+    #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
+    #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
     typedef struct MPU_SETTINGS
     {
@@ -364,49 +364,49 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-    /**
-     * @brief Allocate a secure context for the task.
-     *
-     * Tasks are not created with a secure context. Any task that is going to call
-     * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
-     * secure context before it calls any secure function.
-     *
-     * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
-     */
+/**
+ * @brief Allocate a secure context for the task.
+ *
+ * Tasks are not created with a secure context. Any task that is going to call
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+ * secure context before it calls any secure function.
+ *
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+ */
     #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
 
-    /**
-     * @brief Called when a task is deleted to delete the task's secure context,
-     * if it has one.
-     *
-     * @param[in] pxTCB The TCB of the task being deleted.
-     */
+/**
+ * @brief Called when a task is deleted to delete the task's secure context,
+ * if it has one.
+ *
+ * @param[in] pxTCB The TCB of the task being deleted.
+ */
     #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
 #endif /* configENABLE_TRUSTZONE */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Checks whether or not the processor is privileged.
-     *
-     * @return 1 if the processor is already privileged, 0 otherwise.
-     */
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
     #define portIS_PRIVILEGED()      xIsPrivileged()
 
-    /**
-     * @brief Raise an SVC request to raise privilege.
-     *
-     * The SVC handler checks that the SVC was raised from a system call and only
-     * then it raises the privilege. If this is called from any other place,
-     * the privilege is not raised.
-     */
+/**
+ * @brief Raise an SVC request to raise privilege.
+ *
+ * The SVC handler checks that the SVC was raised from a system call and only
+ * then it raises the privilege. If this is called from any other place,
+ * the privilege is not raised.
+ */
     #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
 
-    /**
-     * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
-     * register.
-     */
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
     #define portRESET_PRIVILEGE()    vResetPrivilege()
 #else
     #define portIS_PRIVILEGED()
@@ -419,12 +419,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     extern BaseType_t xPortIsTaskPrivileged( void );
 
-    /**
-     * @brief Checks whether or not the calling task is privileged.
-     *
-     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
-     */
-    #define portIS_TASK_PRIVILEGED()      xPortIsTaskPrivileged()
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
+    #define portIS_TASK_PRIVILEGED()    xPortIsTaskPrivileged()
 
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
@@ -439,9 +439,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * based on whether or not Mainline extension is implemented. */
 #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
     #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
-        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
     #else
-        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    0
     #endif
 #endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
 
@@ -450,9 +450,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  */
 #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
 
-    /**
-     * @brief Count the number of leading zeros in a 32-bit value.
-     */
+/**
+ * @brief Count the number of leading zeros in a 32-bit value.
+ */
     static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
     {
         uint32_t ulReturn;
@@ -462,7 +462,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         return ulReturn;
     }
 
-    /* Check the configuration. */
+/* Check the configuration. */
     #if ( configMAX_PRIORITIES > 32 )
         #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
     #endif
@@ -471,16 +471,16 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection.  Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
     #endif
 
-    /**
-     * @brief Store/clear the ready priorities in a bit map.
-     */
-    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+/**
+ * @brief Store/clear the ready priorities in a bit map.
+ */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )      ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )       ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 
-    /**
-     * @brief Get the priority of the highest-priority task that is ready to execute.
-     */
-    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )   uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+/**
+ * @brief Get the priority of the highest-priority task that is ready to execute.
+ */
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
 
 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM85/secure/secure_context.c b/portable/GCC/ARM_CM85/secure/secure_context.c
index 0730d574d..7d2171996 100644
--- a/portable/GCC/ARM_CM85/secure/secure_context.c
+++ b/portable/GCC/ARM_CM85/secure/secure_context.c
@@ -65,7 +65,7 @@
  * @brief Maximum number of secure contexts.
  */
 #ifndef secureconfigMAX_SECURE_CONTEXTS
-    #define secureconfigMAX_SECURE_CONTEXTS        8UL
+    #define secureconfigMAX_SECURE_CONTEXTS    8UL
 #endif
 /*-----------------------------------------------------------*/
 
@@ -164,15 +164,15 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
         }
 
         #if ( configENABLE_MPU == 1 )
-            {
-                /* Configure thread mode to use PSP and to be unprivileged. */
-                secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
-            }
+        {
+            /* Configure thread mode to use PSP and to be unprivileged. */
+            secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
+        }
         #else /* configENABLE_MPU */
-            {
-                /* Configure thread mode to use PSP and to be privileged. */
-                secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
-            }
+        {
+            /* Configure thread mode to use PSP and to be privileged. */
+            secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
+        }
         #endif /* configENABLE_MPU */
     }
 }
@@ -219,16 +219,16 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
             if( pucStackMemory != NULL )
             {
                 /* Since stack grows down, the starting point will be the last
-                 * location. Note that this location is next to the last
-                 * allocated byte for stack (excluding the space for seal values)
-                 * because the hardware decrements the stack pointer before
-                 * writing i.e. if stack pointer is 0x2, a push operation will
-                 * decrement the stack pointer to 0x1 and then write at 0x1. */
+                * location. Note that this location is next to the last
+                * allocated byte for stack (excluding the space for seal values)
+                * because the hardware decrements the stack pointer before
+                * writing i.e. if stack pointer is 0x2, a push operation will
+                * decrement the stack pointer to 0x1 and then write at 0x1. */
                 xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize;
 
                 /* Seal the created secure process stack. */
-                *( uint32_t * )( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE;
-                *( uint32_t * )( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE;
+                *( uint32_t * ) ( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE;
+                *( uint32_t * ) ( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE;
 
                 /* The stack cannot go beyond this location. This value is
                  * programmed in the PSPLIM register on context switch.*/
@@ -237,32 +237,32 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
                 xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle;
 
                 #if ( configENABLE_MPU == 1 )
+                {
+                    /* Store the correct CONTROL value for the task on the stack.
+                     * This value is programmed in the CONTROL register on
+                     * context switch. */
+                    pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart;
+                    pulCurrentStackPointer--;
+
+                    if( ulIsTaskPrivileged )
                     {
-                        /* Store the correct CONTROL value for the task on the stack.
-                         * This value is programmed in the CONTROL register on
-                         * context switch. */
-                        pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart;
-                        pulCurrentStackPointer--;
-
-                        if( ulIsTaskPrivileged )
-                        {
-                            *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
-                        }
-                        else
-                        {
-                            *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
-                        }
-
-                        /* Store the current stack pointer. This value is programmed in
-                         * the PSP register on context switch. */
-                        xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+                        *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
                     }
+                    else
+                    {
+                        *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
+                    }
+
+                    /* Store the current stack pointer. This value is programmed in
+                     * the PSP register on context switch. */
+                    xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+                }
                 #else /* configENABLE_MPU */
-                    {
-                        /* Current SP is set to the starting of the stack. This
-                         * value programmed in the PSP register on context switch. */
-                        xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart;
-                    }
+                {
+                    /* Current SP is set to the starting of the stack. This
+                     * value programmed in the PSP register on context switch. */
+                    xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart;
+                }
                 #endif /* configENABLE_MPU */
 
                 /* Ensure to never return 0 as a valid context handle. */
@@ -275,7 +275,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
 }
 /*-----------------------------------------------------------*/
 
-secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle,
+                                                              void * pvTaskHandle )
 {
     uint32_t ulIPSR, ulSecureContextIndex;
 
@@ -306,7 +307,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandl
 }
 /*-----------------------------------------------------------*/
 
-secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle,
+                                                              void * pvTaskHandle )
 {
     uint8_t * pucStackLimit;
     uint32_t ulSecureContextIndex;
@@ -328,7 +330,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandl
 }
 /*-----------------------------------------------------------*/
 
-secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle,
+                                                              void * pvTaskHandle )
 {
     uint8_t * pucStackLimit;
     uint32_t ulSecureContextIndex;
diff --git a/portable/GCC/ARM_CM85/secure/secure_context.h b/portable/GCC/ARM_CM85/secure/secure_context.h
index d0adbaf01..0bf776198 100644
--- a/portable/GCC/ARM_CM85/secure/secure_context.h
+++ b/portable/GCC/ARM_CM85/secure/secure_context.h
@@ -38,12 +38,12 @@
 /**
  * @brief PSP value when no secure context is loaded.
  */
-#define securecontextNO_STACK               0x0
+#define securecontextNO_STACK              0x0
 
 /**
  * @brief Invalid context ID.
  */
-#define securecontextINVALID_CONTEXT_ID     0UL
+#define securecontextINVALID_CONTEXT_ID    0UL
 /*-----------------------------------------------------------*/
 
 /**
@@ -108,7 +108,8 @@ void SecureContext_Init( void );
  * @param[in] xSecureContextHandle Context handle corresponding to the
  * context to be freed.
  */
-void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle,
+                                void * pvTaskHandle );
 
 /**
  * @brief Loads the given context.
@@ -119,7 +120,8 @@ void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void
  * @param[in] xSecureContextHandle Context handle corresponding to the context
  * to be loaded.
  */
-void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle,
+                                void * pvTaskHandle );
 
 /**
  * @brief Saves the given context.
@@ -130,6 +132,7 @@ void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void
  * @param[in] xSecureContextHandle Context handle corresponding to the context
  * to be saved.
  */
-void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle,
+                                void * pvTaskHandle );
 
 #endif /* __SECURE_CONTEXT_H__ */
diff --git a/portable/GCC/ARM_CM85/secure/secure_heap.c b/portable/GCC/ARM_CM85/secure/secure_heap.c
index f3b80df54..1ec3bdbdb 100644
--- a/portable/GCC/ARM_CM85/secure/secure_heap.c
+++ b/portable/GCC/ARM_CM85/secure/secure_heap.c
@@ -67,7 +67,7 @@
 #define secureheapSIZE_MAX              ( ~( ( size_t ) 0 ) )
 
 /* Check if adding a and b will result in overflow. */
-#define secureheapADD_WILL_OVERFLOW( a, b )         ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) )
+#define secureheapADD_WILL_OVERFLOW( a, b )    ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) )
 
 /* MSB of the xBlockSize member of an BlockLink_t structure is used to track
  * the allocation status of a block.  When MSB of the xBlockSize member of
@@ -397,17 +397,17 @@ void * pvPortMalloc( size_t xWantedSize )
     traceMALLOC( pvReturn, xWantedSize );
 
     #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
+    {
+        if( pvReturn == NULL )
         {
-            if( pvReturn == NULL )
-            {
-                extern void vApplicationMallocFailedHook( void );
-                vApplicationMallocFailedHook();
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
+            extern void vApplicationMallocFailedHook( void );
+            vApplicationMallocFailedHook();
         }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
     #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */
 
     secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );
diff --git a/portable/GCC/ARM_CM85/secure/secure_init.c b/portable/GCC/ARM_CM85/secure/secure_init.c
index dc19ebc7d..b89c5f644 100644
--- a/portable/GCC/ARM_CM85/secure/secure_init.c
+++ b/portable/GCC/ARM_CM85/secure/secure_init.c
@@ -93,7 +93,7 @@ secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )
          * permitted. CP11 should be programmed to the same value as CP10. */
         *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
 
-        /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
+        /* LSPENS = 0 ==> LSPEN is writable from non-secure state. This ensures
          * that we can enable/disable lazy stacking in port.c file. */
         *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK );
 
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.c
index 2d1218a95..d1fbdc0e5 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.c
@@ -44,2274 +44,2274 @@
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-#if ( INCLUDE_xTaskDelayUntil == 1 )
+    #if ( INCLUDE_xTaskDelayUntil == 1 )
 
-BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
-                                const TickType_t xTimeIncrement ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
+                                        const TickType_t xTimeIncrement ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
-                                const TickType_t xTimeIncrement ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskDelayUntilImpl                       \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskDelayUntil_Unpriv                        \n"
-        " MPU_xTaskDelayUntil_Priv:                             \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskDelayUntilImpl                         \n"
-        " MPU_xTaskDelayUntil_Unpriv:                           \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskDelayUntilImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
+                                        const TickType_t xTimeIncrement ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskDelayUntilImpl                       \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskDelayUntil_Unpriv                        \n"
+                " MPU_xTaskDelayUntil_Priv:                             \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskDelayUntilImpl                         \n"
+                " MPU_xTaskDelayUntil_Unpriv:                           \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskDelayUntilImpl                        \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */
+    #endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_xTaskAbortDelay == 1 )
+    #if ( INCLUDE_xTaskAbortDelay == 1 )
 
-BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskAbortDelayImpl                       \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskAbortDelay_Unpriv                        \n"
-        " MPU_xTaskAbortDelay_Priv:                             \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskAbortDelayImpl                         \n"
-        " MPU_xTaskAbortDelay_Unpriv:                           \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskAbortDelayImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskAbortDelayImpl                       \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskAbortDelay_Unpriv                        \n"
+                " MPU_xTaskAbortDelay_Priv:                             \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskAbortDelayImpl                         \n"
+                " MPU_xTaskAbortDelay_Unpriv:                           \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskAbortDelayImpl                        \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */
+    #endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_vTaskDelay == 1 )
+    #if ( INCLUDE_vTaskDelay == 1 )
 
-void MPU_vTaskDelay( const TickType_t xTicksToDelay ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskDelay( const TickType_t xTicksToDelay ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskDelayImpl                            \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskDelay_Unpriv                             \n"
-        " MPU_vTaskDelay_Priv:                                  \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskDelayImpl                              \n"
-        " MPU_vTaskDelay_Unpriv:                                \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskDelayImpl                             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskDelayImpl                            \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskDelay_Unpriv                             \n"
+                " MPU_vTaskDelay_Priv:                                  \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskDelayImpl                              \n"
+                " MPU_vTaskDelay_Unpriv:                                \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskDelayImpl                             \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_vTaskDelay == 1 ) */
+    #endif /* if ( INCLUDE_vTaskDelay == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_uxTaskPriorityGet == 1 )
+    #if ( INCLUDE_uxTaskPriorityGet == 1 )
 
-UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskPriorityGetImpl                     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTaskPriorityGet_Unpriv                      \n"
-        " MPU_uxTaskPriorityGet_Priv:                           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTaskPriorityGetImpl                       \n"
-        " MPU_uxTaskPriorityGet_Unpriv:                         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskPriorityGetImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskPriorityGetImpl                     \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTaskPriorityGet_Unpriv                      \n"
+                " MPU_uxTaskPriorityGet_Priv:                           \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTaskPriorityGetImpl                       \n"
+                " MPU_uxTaskPriorityGet_Unpriv:                         \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskPriorityGetImpl                      \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */
+    #endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_eTaskGetState == 1 )
+    #if ( INCLUDE_eTaskGetState == 1 )
 
-eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_eTaskGetStateImpl                         \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_eTaskGetState_Unpriv                          \n"
-        " MPU_eTaskGetState_Priv:                               \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_eTaskGetStateImpl                           \n"
-        " MPU_eTaskGetState_Unpriv:                             \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_eTaskGetStateImpl                          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_eTaskGetStateImpl                         \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_eTaskGetState_Unpriv                          \n"
+                " MPU_eTaskGetState_Priv:                               \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_eTaskGetStateImpl                           \n"
+                " MPU_eTaskGetState_Unpriv:                             \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_eTaskGetStateImpl                          \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_eTaskGetState == 1 ) */
+    #endif /* if ( INCLUDE_eTaskGetState == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-void MPU_vTaskGetInfo( TaskHandle_t xTask,
-                       TaskStatus_t * pxTaskStatus,
-                       BaseType_t xGetFreeStackSpace,
-                       eTaskState eState ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskGetInfo( TaskHandle_t xTask,
+                               TaskStatus_t * pxTaskStatus,
+                               BaseType_t xGetFreeStackSpace,
+                               eTaskState eState ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskGetInfo( TaskHandle_t xTask,
-                       TaskStatus_t * pxTaskStatus,
-                       BaseType_t xGetFreeStackSpace,
-                       eTaskState eState ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskGetInfoImpl                          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskGetInfo_Unpriv                           \n"
-        " MPU_vTaskGetInfo_Priv:                                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskGetInfoImpl                            \n"
-        " MPU_vTaskGetInfo_Unpriv:                              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskGetInfoImpl                           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskGetInfo( TaskHandle_t xTask,
+                               TaskStatus_t * pxTaskStatus,
+                               BaseType_t xGetFreeStackSpace,
+                               eTaskState eState ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskGetInfoImpl                          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskGetInfo_Unpriv                           \n"
+                " MPU_vTaskGetInfo_Priv:                                \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskGetInfoImpl                            \n"
+                " MPU_vTaskGetInfo_Unpriv:                              \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskGetInfoImpl                           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
+    #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
+    #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
 
-TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetIdleTaskHandleImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGetIdleTaskHandle_Unpriv                 \n"
-        " MPU_xTaskGetIdleTaskHandle_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGetIdleTaskHandleImpl                  \n"
-        " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetIdleTaskHandleImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetIdleTaskHandleImpl                \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGetIdleTaskHandle_Unpriv                 \n"
+                " MPU_xTaskGetIdleTaskHandle_Priv:                      \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGetIdleTaskHandleImpl                  \n"
+                " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetIdleTaskHandleImpl                 \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */
+    #endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_vTaskSuspend == 1 )
+    #if ( INCLUDE_vTaskSuspend == 1 )
 
-void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSuspendImpl                          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskSuspend_Unpriv                           \n"
-        " MPU_vTaskSuspend_Priv:                                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskSuspendImpl                            \n"
-        " MPU_vTaskSuspend_Unpriv:                              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSuspendImpl                           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskSuspendImpl                          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskSuspend_Unpriv                           \n"
+                " MPU_vTaskSuspend_Priv:                                \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskSuspendImpl                            \n"
+                " MPU_vTaskSuspend_Unpriv:                              \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskSuspendImpl                           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
+    #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_vTaskSuspend == 1 )
+    #if ( INCLUDE_vTaskSuspend == 1 )
 
-void MPU_vTaskResume( TaskHandle_t xTaskToResume ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskResume( TaskHandle_t xTaskToResume ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskResumeImpl                           \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskResume_Unpriv                            \n"
-        " MPU_vTaskResume_Priv:                                 \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskResumeImpl                             \n"
-        " MPU_vTaskResume_Unpriv:                               \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskResumeImpl                            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskResumeImpl                           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskResume_Unpriv                            \n"
+                " MPU_vTaskResume_Priv:                                 \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskResumeImpl                             \n"
+                " MPU_vTaskResume_Unpriv:                               \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskResumeImpl                            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
+    #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
 /*-----------------------------------------------------------*/
 
-TickType_t MPU_xTaskGetTickCount( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    TickType_t MPU_xTaskGetTickCount( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TickType_t MPU_xTaskGetTickCount( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetTickCountImpl                     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGetTickCount_Unpriv                      \n"
-        " MPU_xTaskGetTickCount_Priv:                           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGetTickCountImpl                       \n"
-        " MPU_xTaskGetTickCount_Unpriv:                         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetTickCountImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    TickType_t MPU_xTaskGetTickCount( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xTaskGetTickCountImpl                     \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xTaskGetTickCount_Unpriv                      \n"
+            " MPU_xTaskGetTickCount_Priv:                           \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xTaskGetTickCountImpl                       \n"
+            " MPU_xTaskGetTickCount_Unpriv:                         \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xTaskGetTickCountImpl                      \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetNumberOfTasksImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTaskGetNumberOfTasks_Unpriv                 \n"
-        " MPU_uxTaskGetNumberOfTasks_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTaskGetNumberOfTasksImpl                  \n"
-        " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetNumberOfTasksImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_uxTaskGetNumberOfTasksImpl                \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_uxTaskGetNumberOfTasks_Unpriv                 \n"
+            " MPU_uxTaskGetNumberOfTasks_Priv:                      \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_uxTaskGetNumberOfTasksImpl                  \n"
+            " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_uxTaskGetNumberOfTasksImpl                 \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configGENERATE_RUN_TIME_STATS == 1 )
+    #if ( configGENERATE_RUN_TIME_STATS == 1 )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetRunTimeCounterImpl               \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGetRunTimeCounter_Unpriv                \n"
-        " MPU_ulTaskGetRunTimeCounter_Priv:                     \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGetRunTimeCounterImpl                 \n"
-        " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetRunTimeCounterImpl                \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetRunTimeCounterImpl               \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGetRunTimeCounter_Unpriv                \n"
+                " MPU_ulTaskGetRunTimeCounter_Priv:                     \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGetRunTimeCounterImpl                 \n"
+                " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetRunTimeCounterImpl                \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configGENERATE_RUN_TIME_STATS == 1 )
+    #if ( configGENERATE_RUN_TIME_STATS == 1 )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetRunTimePercentImpl               \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGetRunTimePercent_Unpriv                \n"
-        " MPU_ulTaskGetRunTimePercent_Priv:                     \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGetRunTimePercentImpl                 \n"
-        " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetRunTimePercentImpl                \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetRunTimePercentImpl               \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGetRunTimePercent_Unpriv                \n"
+                " MPU_ulTaskGetRunTimePercent_Priv:                     \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGetRunTimePercentImpl                 \n"
+                " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetRunTimePercentImpl                \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+    #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetIdleRunTimePercentImpl           \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv            \n"
-        " MPU_ulTaskGetIdleRunTimePercent_Priv:                 \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGetIdleRunTimePercentImpl             \n"
-        " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetIdleRunTimePercentImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetIdleRunTimePercentImpl           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv            \n"
+                " MPU_ulTaskGetIdleRunTimePercent_Priv:                 \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGetIdleRunTimePercentImpl             \n"
+                " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetIdleRunTimePercentImpl            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+    #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGetIdleRunTimeCounterImpl           \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv            \n"
-        " MPU_ulTaskGetIdleRunTimeCounter_Priv:                 \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGetIdleRunTimeCounterImpl             \n"
-        " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGetIdleRunTimeCounterImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetIdleRunTimeCounterImpl           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv            \n"
+                " MPU_ulTaskGetIdleRunTimeCounter_Priv:                 \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGetIdleRunTimeCounterImpl             \n"
+                " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGetIdleRunTimeCounterImpl            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+    #if ( configUSE_APPLICATION_TASK_TAG == 1 )
 
-void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
-                                     TaskHookFunction_t pxHookFunction ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
+                                             TaskHookFunction_t pxHookFunction ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
-                                     TaskHookFunction_t pxHookFunction ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSetApplicationTaskTagImpl            \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskSetApplicationTaskTag_Unpriv             \n"
-        " MPU_vTaskSetApplicationTaskTag_Priv:                  \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskSetApplicationTaskTagImpl              \n"
-        " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSetApplicationTaskTagImpl             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
+                                             TaskHookFunction_t pxHookFunction ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskSetApplicationTaskTagImpl            \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskSetApplicationTaskTag_Unpriv             \n"
+                " MPU_vTaskSetApplicationTaskTag_Priv:                  \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskSetApplicationTaskTagImpl              \n"
+                " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskSetApplicationTaskTagImpl             \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
+    #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+    #if ( configUSE_APPLICATION_TASK_TAG == 1 )
 
-TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetApplicationTaskTagImpl            \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGetApplicationTaskTag_Unpriv             \n"
-        " MPU_xTaskGetApplicationTaskTag_Priv:                  \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGetApplicationTaskTagImpl              \n"
-        " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetApplicationTaskTagImpl             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetApplicationTaskTagImpl            \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGetApplicationTaskTag_Unpriv             \n"
+                " MPU_xTaskGetApplicationTaskTag_Priv:                  \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGetApplicationTaskTagImpl              \n"
+                " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetApplicationTaskTagImpl             \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
+    #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+    #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
 
-void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
-                                            BaseType_t xIndex,
-                                            void * pvValue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
+                                                    BaseType_t xIndex,
+                                                    void * pvValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
-                                            BaseType_t xIndex,
-                                            void * pvValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSetThreadLocalStoragePointerImpl     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv      \n"
-        " MPU_vTaskSetThreadLocalStoragePointer_Priv:           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskSetThreadLocalStoragePointerImpl       \n"
-        " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSetThreadLocalStoragePointerImpl      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
+                                                    BaseType_t xIndex,
+                                                    void * pvValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskSetThreadLocalStoragePointerImpl     \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv      \n"
+                " MPU_vTaskSetThreadLocalStoragePointer_Priv:           \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTaskSetThreadLocalStoragePointerImpl       \n"
+                " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTaskSetThreadLocalStoragePointerImpl      \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
+    #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+    #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
 
-void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
-                                               BaseType_t xIndex ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
+                                                       BaseType_t xIndex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
-                                               BaseType_t xIndex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pvTaskGetThreadLocalStoragePointerImpl    \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv     \n"
-        " MPU_pvTaskGetThreadLocalStoragePointer_Priv:          \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_pvTaskGetThreadLocalStoragePointerImpl      \n"
-        " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pvTaskGetThreadLocalStoragePointerImpl     \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
+                                                       BaseType_t xIndex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pvTaskGetThreadLocalStoragePointerImpl    \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv     \n"
+                " MPU_pvTaskGetThreadLocalStoragePointer_Priv:          \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_pvTaskGetThreadLocalStoragePointerImpl      \n"
+                " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pvTaskGetThreadLocalStoragePointerImpl     \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
+    #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
-                                      const UBaseType_t uxArraySize,
-                                      configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
+                                              const UBaseType_t uxArraySize,
+                                              configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
-                                      const UBaseType_t uxArraySize,
-                                      configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetSystemStateImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTaskGetSystemState_Unpriv                   \n"
-        " MPU_uxTaskGetSystemState_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTaskGetSystemStateImpl                    \n"
-        " MPU_uxTaskGetSystemState_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetSystemStateImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
+                                              const UBaseType_t uxArraySize,
+                                              configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskGetSystemStateImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTaskGetSystemState_Unpriv                   \n"
+                " MPU_uxTaskGetSystemState_Priv:                        \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTaskGetSystemStateImpl                    \n"
+                " MPU_uxTaskGetSystemState_Unpriv:                      \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskGetSystemStateImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
+    #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
+    #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
 
-UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetStackHighWaterMarkImpl           \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTaskGetStackHighWaterMark_Unpriv            \n"
-        " MPU_uxTaskGetStackHighWaterMark_Priv:                 \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTaskGetStackHighWaterMarkImpl             \n"
-        " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetStackHighWaterMarkImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskGetStackHighWaterMarkImpl           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTaskGetStackHighWaterMark_Unpriv            \n"
+                " MPU_uxTaskGetStackHighWaterMark_Priv:                 \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTaskGetStackHighWaterMarkImpl             \n"
+                " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskGetStackHighWaterMarkImpl            \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */
+    #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
+    #if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
 
-configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTaskGetStackHighWaterMark2Impl          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv           \n"
-        " MPU_uxTaskGetStackHighWaterMark2_Priv:                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTaskGetStackHighWaterMark2Impl            \n"
-        " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTaskGetStackHighWaterMark2Impl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskGetStackHighWaterMark2Impl          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv           \n"
+                " MPU_uxTaskGetStackHighWaterMark2_Priv:                \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTaskGetStackHighWaterMark2Impl            \n"
+                " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTaskGetStackHighWaterMark2Impl           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */
+    #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
+    #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
 
-TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetCurrentTaskHandleImpl             \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGetCurrentTaskHandle_Unpriv              \n"
-        " MPU_xTaskGetCurrentTaskHandle_Priv:                   \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGetCurrentTaskHandleImpl               \n"
-        " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetCurrentTaskHandleImpl              \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetCurrentTaskHandleImpl             \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGetCurrentTaskHandle_Unpriv              \n"
+                " MPU_xTaskGetCurrentTaskHandle_Priv:                   \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGetCurrentTaskHandleImpl               \n"
+                " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetCurrentTaskHandleImpl              \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
+    #endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_xTaskGetSchedulerState == 1 )
+    #if ( INCLUDE_xTaskGetSchedulerState == 1 )
 
-BaseType_t MPU_xTaskGetSchedulerState( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGetSchedulerState( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGetSchedulerState( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGetSchedulerStateImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGetSchedulerState_Unpriv                 \n"
-        " MPU_xTaskGetSchedulerState_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGetSchedulerStateImpl                  \n"
-        " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGetSchedulerStateImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGetSchedulerState( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetSchedulerStateImpl                \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGetSchedulerState_Unpriv                 \n"
+                " MPU_xTaskGetSchedulerState_Priv:                      \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGetSchedulerStateImpl                  \n"
+                " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGetSchedulerStateImpl                 \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */
+    #endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */
 /*-----------------------------------------------------------*/
 
-void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTaskSetTimeOutStateImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTaskSetTimeOutState_Unpriv                   \n"
-        " MPU_vTaskSetTimeOutState_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTaskSetTimeOutStateImpl                    \n"
-        " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTaskSetTimeOutStateImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_vTaskSetTimeOutStateImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_vTaskSetTimeOutState_Unpriv                   \n"
+            " MPU_vTaskSetTimeOutState_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_vTaskSetTimeOutStateImpl                    \n"
+            " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_vTaskSetTimeOutStateImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
-                                     TickType_t * const pxTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
+                                         TickType_t * const pxTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
-                                     TickType_t * const pxTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskCheckForTimeOutImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskCheckForTimeOut_Unpriv                   \n"
-        " MPU_xTaskCheckForTimeOut_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskCheckForTimeOutImpl                    \n"
-        " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskCheckForTimeOutImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
+                                         TickType_t * const pxTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xTaskCheckForTimeOutImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xTaskCheckForTimeOut_Unpriv                   \n"
+            " MPU_xTaskCheckForTimeOut_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xTaskCheckForTimeOutImpl                    \n"
+            " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xTaskCheckForTimeOutImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                   UBaseType_t uxIndexToNotify,
-                                   uint32_t ulValue,
-                                   eNotifyAction eAction,
-                                   uint32_t * pulPreviousNotificationValue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
+                                           UBaseType_t uxIndexToNotify,
+                                           uint32_t ulValue,
+                                           eNotifyAction eAction,
+                                           uint32_t * pulPreviousNotificationValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                   UBaseType_t uxIndexToNotify,
-                                   uint32_t ulValue,
-                                   eNotifyAction eAction,
-                                   uint32_t * pulPreviousNotificationValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGenericNotifyImpl                    \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGenericNotify_Unpriv                     \n"
-        " MPU_xTaskGenericNotify_Priv:                          \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGenericNotifyImpl                      \n"
-        " MPU_xTaskGenericNotify_Unpriv:                        \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGenericNotifyImpl                     \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
+                                           UBaseType_t uxIndexToNotify,
+                                           uint32_t ulValue,
+                                           eNotifyAction eAction,
+                                           uint32_t * pulPreviousNotificationValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGenericNotifyImpl                    \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGenericNotify_Unpriv                     \n"
+                " MPU_xTaskGenericNotify_Priv:                          \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGenericNotifyImpl                      \n"
+                " MPU_xTaskGenericNotify_Unpriv:                        \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGenericNotifyImpl                     \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                       uint32_t ulBitsToClearOnEntry,
-                                       uint32_t ulBitsToClearOnExit,
-                                       uint32_t * pulNotificationValue,
-                                       TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
+                                               uint32_t ulBitsToClearOnEntry,
+                                               uint32_t ulBitsToClearOnExit,
+                                               uint32_t * pulNotificationValue,
+                                               TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                       uint32_t ulBitsToClearOnEntry,
-                                       uint32_t ulBitsToClearOnExit,
-                                       uint32_t * pulNotificationValue,
-                                       TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGenericNotifyWaitImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGenericNotifyWait_Unpriv                 \n"
-        " MPU_xTaskGenericNotifyWait_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGenericNotifyWaitImpl                  \n"
-        " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGenericNotifyWaitImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
+                                               uint32_t ulBitsToClearOnEntry,
+                                               uint32_t ulBitsToClearOnExit,
+                                               uint32_t * pulNotificationValue,
+                                               TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGenericNotifyWaitImpl                \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGenericNotifyWait_Unpriv                 \n"
+                " MPU_xTaskGenericNotifyWait_Priv:                      \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGenericNotifyWaitImpl                  \n"
+                " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGenericNotifyWaitImpl                 \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
-                                      BaseType_t xClearCountOnExit,
-                                      TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
+                                              BaseType_t xClearCountOnExit,
+                                              TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
-                                      BaseType_t xClearCountOnExit,
-                                      TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGenericNotifyTakeImpl               \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGenericNotifyTake_Unpriv                \n"
-        " MPU_ulTaskGenericNotifyTake_Priv:                     \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGenericNotifyTakeImpl                 \n"
-        " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGenericNotifyTakeImpl                \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
+                                              BaseType_t xClearCountOnExit,
+                                              TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGenericNotifyTakeImpl               \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGenericNotifyTake_Unpriv                \n"
+                " MPU_ulTaskGenericNotifyTake_Priv:                     \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGenericNotifyTakeImpl                 \n"
+                " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGenericNotifyTakeImpl                \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
-                                             UBaseType_t uxIndexToClear ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
+                                                     UBaseType_t uxIndexToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
-                                             UBaseType_t uxIndexToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTaskGenericNotifyStateClearImpl          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTaskGenericNotifyStateClear_Unpriv           \n"
-        " MPU_xTaskGenericNotifyStateClear_Priv:                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTaskGenericNotifyStateClearImpl            \n"
-        " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTaskGenericNotifyStateClearImpl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
+                                                     UBaseType_t uxIndexToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGenericNotifyStateClearImpl          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTaskGenericNotifyStateClear_Unpriv           \n"
+                " MPU_xTaskGenericNotifyStateClear_Priv:                \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTaskGenericNotifyStateClearImpl            \n"
+                " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTaskGenericNotifyStateClearImpl           \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
-                                            UBaseType_t uxIndexToClear,
-                                            uint32_t ulBitsToClear ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
+                                                    UBaseType_t uxIndexToClear,
+                                                    uint32_t ulBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
-                                            UBaseType_t uxIndexToClear,
-                                            uint32_t ulBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_ulTaskGenericNotifyValueClearImpl         \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_ulTaskGenericNotifyValueClear_Unpriv          \n"
-        " MPU_ulTaskGenericNotifyValueClear_Priv:               \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_ulTaskGenericNotifyValueClearImpl           \n"
-        " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_ulTaskGenericNotifyValueClearImpl          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
+                                                    UBaseType_t uxIndexToClear,
+                                                    uint32_t ulBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGenericNotifyValueClearImpl         \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_ulTaskGenericNotifyValueClear_Unpriv          \n"
+                " MPU_ulTaskGenericNotifyValueClear_Priv:               \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_ulTaskGenericNotifyValueClearImpl           \n"
+                " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_ulTaskGenericNotifyValueClearImpl          \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
-                                  const void * const pvItemToQueue,
-                                  TickType_t xTicksToWait,
-                                  const BaseType_t xCopyPosition ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
+                                      const void * const pvItemToQueue,
+                                      TickType_t xTicksToWait,
+                                      const BaseType_t xCopyPosition ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
-                                  const void * const pvItemToQueue,
-                                  TickType_t xTicksToWait,
-                                  const BaseType_t xCopyPosition ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueGenericSendImpl                     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueGenericSend_Unpriv                      \n"
-        " MPU_xQueueGenericSend_Priv:                           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueGenericSendImpl                       \n"
-        " MPU_xQueueGenericSend_Unpriv:                         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueGenericSendImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
+                                      const void * const pvItemToQueue,
+                                      TickType_t xTicksToWait,
+                                      const BaseType_t xCopyPosition ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueueGenericSendImpl                     \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xQueueGenericSend_Unpriv                      \n"
+            " MPU_xQueueGenericSend_Priv:                           \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xQueueGenericSendImpl                       \n"
+            " MPU_xQueueGenericSend_Unpriv:                         \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueueGenericSendImpl                      \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxQueueMessagesWaitingImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxQueueMessagesWaiting_Unpriv                 \n"
-        " MPU_uxQueueMessagesWaiting_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxQueueMessagesWaitingImpl                  \n"
-        " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxQueueMessagesWaitingImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_uxQueueMessagesWaitingImpl                \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_uxQueueMessagesWaiting_Unpriv                 \n"
+            " MPU_uxQueueMessagesWaiting_Priv:                      \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_uxQueueMessagesWaitingImpl                  \n"
+            " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_uxQueueMessagesWaitingImpl                 \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxQueueSpacesAvailableImpl                \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxQueueSpacesAvailable_Unpriv                 \n"
-        " MPU_uxQueueSpacesAvailable_Priv:                      \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxQueueSpacesAvailableImpl                  \n"
-        " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxQueueSpacesAvailableImpl                 \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_uxQueueSpacesAvailableImpl                \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_uxQueueSpacesAvailable_Unpriv                 \n"
+            " MPU_uxQueueSpacesAvailable_Priv:                      \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_uxQueueSpacesAvailableImpl                  \n"
+            " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_uxQueueSpacesAvailableImpl                 \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
-                              void * const pvBuffer,
-                              TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
+                                  void * const pvBuffer,
+                                  TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
-                              void * const pvBuffer,
-                              TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueReceiveImpl                         \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueReceive_Unpriv                          \n"
-        " MPU_xQueueReceive_Priv:                               \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueReceiveImpl                           \n"
-        " MPU_xQueueReceive_Unpriv:                             \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueReceiveImpl                          \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
+                                  void * const pvBuffer,
+                                  TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueueReceiveImpl                         \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xQueueReceive_Unpriv                          \n"
+            " MPU_xQueueReceive_Priv:                               \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xQueueReceiveImpl                           \n"
+            " MPU_xQueueReceive_Unpriv:                             \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueueReceiveImpl                          \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
-                           void * const pvBuffer,
-                           TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
+                               void * const pvBuffer,
+                               TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
-                           void * const pvBuffer,
-                           TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueuePeekImpl                            \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueuePeek_Unpriv                             \n"
-        " MPU_xQueuePeek_Priv:                                  \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueuePeekImpl                              \n"
-        " MPU_xQueuePeek_Unpriv:                                \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueuePeekImpl                             \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
+                               void * const pvBuffer,
+                               TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueuePeekImpl                            \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xQueuePeek_Unpriv                             \n"
+            " MPU_xQueuePeek_Priv:                                  \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xQueuePeekImpl                              \n"
+            " MPU_xQueuePeek_Unpriv:                                \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueuePeekImpl                             \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
-                                    TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
+                                        TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
-                                    TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueSemaphoreTakeImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueSemaphoreTake_Unpriv                    \n"
-        " MPU_xQueueSemaphoreTake_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueSemaphoreTakeImpl                     \n"
-        " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueSemaphoreTakeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
+                                        TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueueSemaphoreTakeImpl                   \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xQueueSemaphoreTake_Unpriv                    \n"
+            " MPU_xQueueSemaphoreTake_Priv:                         \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xQueueSemaphoreTakeImpl                     \n"
+            " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xQueueSemaphoreTakeImpl                    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+    #if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
 
-TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueGetMutexHolderImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueGetMutexHolder_Unpriv                   \n"
-        " MPU_xQueueGetMutexHolder_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueGetMutexHolderImpl                    \n"
-        " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueGetMutexHolderImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueGetMutexHolderImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueGetMutexHolder_Unpriv                   \n"
+                " MPU_xQueueGetMutexHolder_Priv:                        \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueGetMutexHolderImpl                    \n"
+                " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueGetMutexHolderImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
 
-#endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */
+    #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+    #if ( configUSE_RECURSIVE_MUTEXES == 1 )
 
-BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
-                                         TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+                                                 TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+        BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+                                                 TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueTakeMutexRecursiveImpl              \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueTakeMutexRecursive_Unpriv               \n"
+                " MPU_xQueueTakeMutexRecursive_Priv:                    \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueTakeMutexRecursiveImpl                \n"
+                " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueTakeMutexRecursiveImpl               \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_RECURSIVE_MUTEXES == 1 )
+
+        BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueGiveMutexRecursiveImpl              \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueGiveMutexRecursive_Unpriv               \n"
+                " MPU_xQueueGiveMutexRecursive_Priv:                    \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueGiveMutexRecursiveImpl                \n"
+                " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueGiveMutexRecursiveImpl               \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_QUEUE_SETS == 1 )
+
+        QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
+                                                        const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
+                                                        const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueSelectFromSetImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueSelectFromSet_Unpriv                    \n"
+                " MPU_xQueueSelectFromSet_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueSelectFromSetImpl                     \n"
+                " MPU_xQueueSelectFromSet_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueSelectFromSetImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_QUEUE_SETS == 1 )
+
+        BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                                       QueueSetHandle_t xQueueSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                                       QueueSetHandle_t xQueueSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueAddToSetImpl                        \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xQueueAddToSet_Unpriv                         \n"
+                " MPU_xQueueAddToSet_Priv:                              \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xQueueAddToSetImpl                          \n"
+                " MPU_xQueueAddToSet_Unpriv:                            \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xQueueAddToSetImpl                         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+        void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
+                                      const char * pcName ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
+                                      const char * pcName ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vQueueAddToRegistryImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vQueueAddToRegistry_Unpriv                    \n"
+                " MPU_vQueueAddToRegistry_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vQueueAddToRegistryImpl                     \n"
+                " MPU_vQueueAddToRegistry_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vQueueAddToRegistryImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+        void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vQueueUnregisterQueueImpl                 \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vQueueUnregisterQueue_Unpriv                  \n"
+                " MPU_vQueueUnregisterQueue_Priv:                       \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vQueueUnregisterQueueImpl                   \n"
+                " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vQueueUnregisterQueueImpl                  \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+        const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pcQueueGetNameImpl                        \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_pcQueueGetName_Unpriv                         \n"
+                " MPU_pcQueueGetName_Priv:                              \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_pcQueueGetNameImpl                          \n"
+                " MPU_pcQueueGetName_Unpriv:                            \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pcQueueGetNameImpl                         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pvTimerGetTimerIDImpl                     \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_pvTimerGetTimerID_Unpriv                      \n"
+                " MPU_pvTimerGetTimerID_Priv:                           \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_pvTimerGetTimerIDImpl                       \n"
+                " MPU_pvTimerGetTimerID_Unpriv:                         \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pvTimerGetTimerIDImpl                      \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
+                                   void * pvNewID ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
+                                   void * pvNewID ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTimerSetTimerIDImpl                      \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTimerSetTimerID_Unpriv                       \n"
+                " MPU_vTimerSetTimerID_Priv:                            \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTimerSetTimerIDImpl                        \n"
+                " MPU_vTimerSetTimerID_Unpriv:                          \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTimerSetTimerIDImpl                       \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerIsTimerActiveImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerIsTimerActive_Unpriv                    \n"
+                " MPU_xTimerIsTimerActive_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerIsTimerActiveImpl                     \n"
+                " MPU_xTimerIsTimerActive_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerIsTimerActiveImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetTimerDaemonTaskHandleImpl        \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv         \n"
+                " MPU_xTimerGetTimerDaemonTaskHandle_Priv:              \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerGetTimerDaemonTaskHandleImpl          \n"
+                " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetTimerDaemonTaskHandleImpl         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                                     const BaseType_t xCommandID,
+                                                     const TickType_t xOptionalValue,
+                                                     BaseType_t * const pxHigherPriorityTaskWoken,
+                                                     const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                                     const BaseType_t xCommandID,
+                                                     const TickType_t xOptionalValue,
+                                                     BaseType_t * const pxHigherPriorityTaskWoken,
+                                                     const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                               \n"
+                " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
+                "                                                               \n"
+                " push {r0}                                                     \n"
+                " mrs r0, control                                               \n"
+                " tst r0, #1                                                    \n"
+                " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
+                " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
+                "     pop {r0}                                                  \n"
+                "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
+                " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
+                "     pop {r0}                                                  \n"
+                "     svc %0                                                    \n"
+                "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
+                "     svc %1                                                    \n"
+                "     bx lr                                                     \n"
+                "                                                               \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pcTimerGetNameImpl                        \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_pcTimerGetName_Unpriv                         \n"
+                " MPU_pcTimerGetName_Priv:                              \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_pcTimerGetNameImpl                          \n"
+                " MPU_pcTimerGetName_Unpriv:                            \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_pcTimerGetNameImpl                         \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
+                                      const BaseType_t uxAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
+                                      const BaseType_t uxAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTimerSetReloadModeImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vTimerSetReloadMode_Unpriv                    \n"
+                " MPU_vTimerSetReloadMode_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vTimerSetReloadModeImpl                     \n"
+                " MPU_vTimerSetReloadMode_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vTimerSetReloadModeImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetReloadModeImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerGetReloadMode_Unpriv                    \n"
+                " MPU_xTimerGetReloadMode_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerGetReloadModeImpl                     \n"
+                " MPU_xTimerGetReloadMode_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetReloadModeImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTimerGetReloadModeImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxTimerGetReloadMode_Unpriv                   \n"
+                " MPU_uxTimerGetReloadMode_Priv:                        \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxTimerGetReloadModeImpl                    \n"
+                " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxTimerGetReloadModeImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetPeriodImpl                       \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerGetPeriod_Unpriv                        \n"
+                " MPU_xTimerGetPeriod_Priv:                             \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerGetPeriodImpl                         \n"
+                " MPU_xTimerGetPeriod_Unpriv:                           \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetPeriodImpl                        \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetExpiryTimeImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xTimerGetExpiryTime_Unpriv                    \n"
+                " MPU_xTimerGetExpiryTime_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xTimerGetExpiryTimeImpl                     \n"
+                " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_xTimerGetExpiryTimeImpl                    \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         const BaseType_t xClearOnExit,
+                                         const BaseType_t xWaitForAllBits,
+                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         const BaseType_t xClearOnExit,
+                                         const BaseType_t xWaitForAllBits,
                                          TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueTakeMutexRecursiveImpl              \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueTakeMutexRecursive_Unpriv               \n"
-        " MPU_xQueueTakeMutexRecursive_Priv:                    \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueTakeMutexRecursiveImpl                \n"
-        " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueTakeMutexRecursiveImpl               \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupWaitBitsImpl                   \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
+            " MPU_xEventGroupWaitBits_Priv:                         \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xEventGroupWaitBitsImpl                     \n"
+            " MPU_xEventGroupWaitBits_Unpriv:                       \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupWaitBitsImpl                    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                          const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueGiveMutexRecursiveImpl              \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueGiveMutexRecursive_Unpriv               \n"
-        " MPU_xQueueGiveMutexRecursive_Priv:                    \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueGiveMutexRecursiveImpl                \n"
-        " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueGiveMutexRecursiveImpl               \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                          const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupClearBitsImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xEventGroupClearBits_Unpriv                   \n"
+            " MPU_xEventGroupClearBits_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xEventGroupClearBitsImpl                    \n"
+            " MPU_xEventGroupClearBits_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupClearBitsImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_QUEUE_SETS == 1 )
+    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                        const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
-                                                const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
-                                                const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueSelectFromSetImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueSelectFromSet_Unpriv                    \n"
-        " MPU_xQueueSelectFromSet_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueSelectFromSetImpl                     \n"
-        " MPU_xQueueSelectFromSet_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueSelectFromSetImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                        const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupSetBitsImpl                    \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xEventGroupSetBits_Unpriv                     \n"
+            " MPU_xEventGroupSetBits_Priv:                          \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xEventGroupSetBitsImpl                      \n"
+            " MPU_xEventGroupSetBits_Unpriv:                        \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupSetBitsImpl                     \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_QUEUE_SETS == 1 )
-
-BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
-                               QueueSetHandle_t xQueueSet ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
-                               QueueSetHandle_t xQueueSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xQueueAddToSetImpl                        \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xQueueAddToSet_Unpriv                         \n"
-        " MPU_xQueueAddToSet_Priv:                              \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xQueueAddToSetImpl                          \n"
-        " MPU_xQueueAddToSet_Unpriv:                            \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xQueueAddToSetImpl                         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_QUEUE_SETS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
-                              const char * pcName ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
-                              const char * pcName ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vQueueAddToRegistryImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vQueueAddToRegistry_Unpriv                    \n"
-        " MPU_vQueueAddToRegistry_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vQueueAddToRegistryImpl                     \n"
-        " MPU_vQueueAddToRegistry_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vQueueAddToRegistryImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vQueueUnregisterQueueImpl                 \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vQueueUnregisterQueue_Unpriv                  \n"
-        " MPU_vQueueUnregisterQueue_Priv:                       \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vQueueUnregisterQueueImpl                   \n"
-        " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vQueueUnregisterQueueImpl                  \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pcQueueGetNameImpl                        \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_pcQueueGetName_Unpriv                         \n"
-        " MPU_pcQueueGetName_Priv:                              \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_pcQueueGetNameImpl                          \n"
-        " MPU_pcQueueGetName_Unpriv:                            \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pcQueueGetNameImpl                         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pvTimerGetTimerIDImpl                     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_pvTimerGetTimerID_Unpriv                      \n"
-        " MPU_pvTimerGetTimerID_Priv:                           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_pvTimerGetTimerIDImpl                       \n"
-        " MPU_pvTimerGetTimerID_Unpriv:                         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pvTimerGetTimerIDImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
-                           void * pvNewID ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
-                           void * pvNewID ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTimerSetTimerIDImpl                      \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTimerSetTimerID_Unpriv                       \n"
-        " MPU_vTimerSetTimerID_Priv:                            \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTimerSetTimerIDImpl                        \n"
-        " MPU_vTimerSetTimerID_Unpriv:                          \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTimerSetTimerIDImpl                       \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerIsTimerActiveImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTimerIsTimerActive_Unpriv                    \n"
-        " MPU_xTimerIsTimerActive_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerIsTimerActiveImpl                     \n"
-        " MPU_xTimerIsTimerActive_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerIsTimerActiveImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetTimerDaemonTaskHandleImpl        \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv         \n"
-        " MPU_xTimerGetTimerDaemonTaskHandle_Priv:              \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerGetTimerDaemonTaskHandleImpl          \n"
-        " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetTimerDaemonTaskHandleImpl         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                             const BaseType_t xCommandID,
-                                             const TickType_t xOptionalValue,
-                                             BaseType_t * const pxHigherPriorityTaskWoken,
-                                             const TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                             const BaseType_t xCommandID,
-                                             const TickType_t xOptionalValue,
-                                             BaseType_t * const pxHigherPriorityTaskWoken,
-                                             const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                               \n"
-        " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
-        "                                                               \n"
-        " push {r0}                                                     \n"
-        " mrs r0, control                                               \n"
-        " tst r0, #1                                                    \n"
-        " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
-        " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
-        "     pop {r0}                                                  \n"
-        "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
-        " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
-        "     pop {r0}                                                  \n"
-        "     svc %0                                                    \n"
-        "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
-        "     svc %1                                                    \n"
-        "     bx lr                                                     \n"
-        "                                                               \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_pcTimerGetNameImpl                        \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_pcTimerGetName_Unpriv                         \n"
-        " MPU_pcTimerGetName_Priv:                              \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_pcTimerGetNameImpl                          \n"
-        " MPU_pcTimerGetName_Unpriv:                            \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_pcTimerGetNameImpl                         \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                              const BaseType_t uxAutoReload ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                              const BaseType_t uxAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vTimerSetReloadModeImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vTimerSetReloadMode_Unpriv                    \n"
-        " MPU_vTimerSetReloadMode_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vTimerSetReloadModeImpl                     \n"
-        " MPU_vTimerSetReloadMode_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vTimerSetReloadModeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetReloadModeImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTimerGetReloadMode_Unpriv                    \n"
-        " MPU_xTimerGetReloadMode_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerGetReloadModeImpl                     \n"
-        " MPU_xTimerGetReloadMode_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetReloadModeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxTimerGetReloadModeImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxTimerGetReloadMode_Unpriv                   \n"
-        " MPU_uxTimerGetReloadMode_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxTimerGetReloadModeImpl                    \n"
-        " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxTimerGetReloadModeImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetPeriodImpl                       \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTimerGetPeriod_Unpriv                        \n"
-        " MPU_xTimerGetPeriod_Priv:                             \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerGetPeriodImpl                         \n"
-        " MPU_xTimerGetPeriod_Unpriv:                           \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetPeriodImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xTimerGetExpiryTimeImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xTimerGetExpiryTime_Unpriv                    \n"
-        " MPU_xTimerGetExpiryTime_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xTimerGetExpiryTimeImpl                     \n"
-        " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xTimerGetExpiryTimeImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                     const EventBits_t uxBitsToSet,
                                      const EventBits_t uxBitsToWaitFor,
-                                     const BaseType_t xClearOnExit,
-                                     const BaseType_t xWaitForAllBits,
-                                     TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                     const EventBits_t uxBitsToSet,
                                      const EventBits_t uxBitsToWaitFor,
-                                     const BaseType_t xClearOnExit,
-                                     const BaseType_t xWaitForAllBits,
                                      TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupWaitBitsImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
-        " MPU_xEventGroupWaitBits_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xEventGroupWaitBitsImpl                     \n"
-        " MPU_xEventGroupWaitBits_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupWaitBitsImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupSyncImpl                       \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xEventGroupSync_Unpriv                        \n"
+            " MPU_xEventGroupSync_Priv:                             \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xEventGroupSyncImpl                         \n"
+            " MPU_xEventGroupSync_Unpriv:                           \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xEventGroupSyncImpl                        \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                      const EventBits_t uxBitsToClear ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                      const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupClearBitsImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xEventGroupClearBits_Unpriv                   \n"
-        " MPU_xEventGroupClearBits_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xEventGroupClearBitsImpl                    \n"
-        " MPU_xEventGroupClearBits_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupClearBitsImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxEventGroupGetNumberImpl                 \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_uxEventGroupGetNumber_Unpriv                  \n"
+                " MPU_uxEventGroupGetNumber_Priv:                       \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_uxEventGroupGetNumberImpl                   \n"
+                " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_uxEventGroupGetNumberImpl                  \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
 /*-----------------------------------------------------------*/
 
-EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                    const EventBits_t uxBitsToSet ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                    const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupSetBitsImpl                    \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xEventGroupSetBits_Unpriv                     \n"
-        " MPU_xEventGroupSetBits_Priv:                          \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xEventGroupSetBitsImpl                      \n"
-        " MPU_xEventGroupSetBits_Unpriv:                        \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupSetBitsImpl                     \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+        void MPU_vEventGroupSetNumber( void * xEventGroup,
+                                       UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vEventGroupSetNumber( void * xEventGroup,
+                                       UBaseType_t uxEventGroupNumber ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vEventGroupSetNumberImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_vEventGroupSetNumber_Unpriv                   \n"
+                " MPU_vEventGroupSetNumber_Priv:                        \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_vEventGroupSetNumberImpl                    \n"
+                " MPU_vEventGroupSetNumber_Unpriv:                      \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "     bl MPU_vEventGroupSetNumberImpl                   \n"
+                "     svc %1                                            \n"
+                "     bx lr                                             \n"
+                "                                                       \n"
+                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            );
+        }
+
+    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
 /*-----------------------------------------------------------*/
 
-EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                 const EventBits_t uxBitsToSet,
-                                 const EventBits_t uxBitsToWaitFor,
-                                 TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                  const void * pvTxData,
+                                  size_t xDataLengthBytes,
+                                  TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                 const EventBits_t uxBitsToSet,
-                                 const EventBits_t uxBitsToWaitFor,
-                                 TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xEventGroupSyncImpl                       \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xEventGroupSync_Unpriv                        \n"
-        " MPU_xEventGroupSync_Priv:                             \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xEventGroupSyncImpl                         \n"
-        " MPU_xEventGroupSync_Unpriv:                           \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xEventGroupSyncImpl                        \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                  const void * pvTxData,
+                                  size_t xDataLengthBytes,
+                                  TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferSendImpl                     \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferSend_Unpriv                      \n"
+            " MPU_xStreamBufferSend_Priv:                           \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferSendImpl                       \n"
+            " MPU_xStreamBufferSend_Unpriv:                         \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferSendImpl                      \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                     void * pvRxData,
+                                     size_t xBufferLengthBytes,
+                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_uxEventGroupGetNumberImpl                 \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_uxEventGroupGetNumber_Unpriv                  \n"
-        " MPU_uxEventGroupGetNumber_Priv:                       \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_uxEventGroupGetNumberImpl                   \n"
-        " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_uxEventGroupGetNumberImpl                  \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                     void * pvRxData,
+                                     size_t xBufferLengthBytes,
+                                     TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferReceiveImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferReceive_Unpriv                   \n"
+            " MPU_xStreamBufferReceive_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferReceiveImpl                    \n"
+            " MPU_xStreamBufferReceive_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferReceiveImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-void MPU_vEventGroupSetNumber( void * xEventGroup,
-                               UBaseType_t uxEventGroupNumber ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-void MPU_vEventGroupSetNumber( void * xEventGroup,
-                               UBaseType_t uxEventGroupNumber ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_vEventGroupSetNumberImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_vEventGroupSetNumber_Unpriv                   \n"
-        " MPU_vEventGroupSetNumber_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_vEventGroupSetNumberImpl                    \n"
-        " MPU_vEventGroupSetNumber_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_vEventGroupSetNumberImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-
-#endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferIsFullImpl                   \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
+            " MPU_xStreamBufferIsFull_Priv:                         \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferIsFullImpl                     \n"
+            " MPU_xStreamBufferIsFull_Unpriv:                       \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferIsFullImpl                    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                              const void * pvTxData,
-                              size_t xDataLengthBytes,
-                              TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                              const void * pvTxData,
-                              size_t xDataLengthBytes,
-                              TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferSendImpl                     \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferSend_Unpriv                      \n"
-        " MPU_xStreamBufferSend_Priv:                           \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferSendImpl                       \n"
-        " MPU_xStreamBufferSend_Unpriv:                         \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferSendImpl                      \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
+            " MPU_xStreamBufferIsEmpty_Priv:                        \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferIsEmptyImpl                    \n"
+            " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferIsEmptyImpl                   \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                 void * pvRxData,
-                                 size_t xBufferLengthBytes,
-                                 TickType_t xTicksToWait ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                 void * pvRxData,
-                                 size_t xBufferLengthBytes,
-                                 TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferReceiveImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferReceive_Unpriv                   \n"
-        " MPU_xStreamBufferReceive_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferReceiveImpl                    \n"
-        " MPU_xStreamBufferReceive_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferReceiveImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
+            " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
+            " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferSpacesAvailableImpl           \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferIsFullImpl                   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
-        " MPU_xStreamBufferIsFull_Priv:                         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferIsFullImpl                     \n"
-        " MPU_xStreamBufferIsFull_Unpriv:                       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferIsFullImpl                    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
+            " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferBytesAvailableImpl             \n"
+            " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferBytesAvailableImpl            \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                 size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
-        " MPU_xStreamBufferIsEmpty_Priv:                        \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferIsEmptyImpl                    \n"
-        " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferIsEmptyImpl                   \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                 size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
+            " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
+            " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferSetTriggerLevelImpl           \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
-size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
-        " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
-        " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferSpacesAvailableImpl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
-size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
-        " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferBytesAvailableImpl             \n"
-        " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferBytesAvailableImpl            \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                             size_t xTriggerLevel ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                             size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
-        " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
-        " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferSetTriggerLevelImpl           \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
-/*-----------------------------------------------------------*/
-
-size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__ (( naked )) FREERTOS_SYSTEM_CALL;
-
-size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-{
-    __asm volatile
-    (
-        " .syntax unified                                       \n"
-        " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
-        "                                                       \n"
-        " push {r0}                                             \n"
-        " mrs r0, control                                       \n"
-        " tst r0, #1                                            \n"
-        " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
-        " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
-        "     pop {r0}                                          \n"
-        "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
-        " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
-        "     pop {r0}                                          \n"
-        "     svc %0                                            \n"
-        "     bl MPU_xStreamBufferNextMessageLengthBytesImpl    \n"
-        "     svc %1                                            \n"
-        "     bx lr                                             \n"
-        "                                                       \n"
-        : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
-    );
-}
+    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
+            "                                                       \n"
+            " push {r0}                                             \n"
+            " mrs r0, control                                       \n"
+            " tst r0, #1                                            \n"
+            " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
+            " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
+            "     pop {r0}                                          \n"
+            "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
+            " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
+            "     pop {r0}                                          \n"
+            "     svc %0                                            \n"
+            "     bl MPU_xStreamBufferNextMessageLengthBytesImpl    \n"
+            "     svc %1                                            \n"
+            "     bx lr                                             \n"
+            "                                                       \n"
+            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+        );
+    }
 /*-----------------------------------------------------------*/
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/port.c b/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
index 80410e82e..c940c304b 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
@@ -110,8 +110,8 @@
 /**
  * @brief Constants used during system call enter and exit.
  */
-#define portPSR_STACK_PADDING_MASK                ( 1UL << 9UL )
-#define portEXC_RETURN_STACK_FRAME_TYPE_MASK      ( 1UL << 4UL )
+#define portPSR_STACK_PADDING_MASK              ( 1UL << 9UL )
+#define portEXC_RETURN_STACK_FRAME_TYPE_MASK    ( 1UL << 4UL )
 /*-----------------------------------------------------------*/
 
 /**
@@ -133,81 +133,81 @@
 /**
  * @brief Offsets in the stack to the parameters when inside the SVC handler.
  */
-#define portOFFSET_TO_LR                    ( 5 )
-#define portOFFSET_TO_PC                    ( 6 )
-#define portOFFSET_TO_PSR                   ( 7 )
+#define portOFFSET_TO_LR     ( 5 )
+#define portOFFSET_TO_PC     ( 6 )
+#define portOFFSET_TO_PSR    ( 7 )
 /*-----------------------------------------------------------*/
 
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                      ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                      ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                       ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                      ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                      ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                     ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                     ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK  ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK               ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK               ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK               ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK               ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK               ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK               ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK               ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK               ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0              ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1              ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2              ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3              ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4              ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5              ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6              ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7              ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE            ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT      ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                      ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE             ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -216,11 +216,11 @@
 
 /* Extract last address of the MPU region as encoded in the
  * RLAR (Region Limit Address Register) value. */
-#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar )  \
+#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar ) \
     ( ( ( rlar ) & portMPU_RLAR_ADDRESS_MASK ) | ~portMPU_RLAR_ADDRESS_MASK )
 
 /* Does addr lies within [start, end] address range? */
-#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end )    \
+#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \
     ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) )
 
 /* Is the access request satisfied by the available permissions? */
@@ -422,54 +422,57 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the system call stack so that upon returning from
-     * SVC, the system call stack is used.
-     *
-     * It is used for the system calls with up to 4 parameters.
-     *
-     * @param pulTaskStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the system call stack so that upon returning from
+ * SVC, the system call stack is used.
+ *
+ * It is used for the system calls with up to 4 parameters.
+ *
+ * @param pulTaskStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallEnter( uint32_t * pulTaskStack,
+                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the system call stack so that upon returning from
-     * SVC, the system call stack is used.
-     *
-     * It is used for the system calls with 5 parameters.
-     *
-     * @param pulTaskStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the system call stack so that upon returning from
+ * SVC, the system call stack is used.
+ *
+ * It is used for the system calls with 5 parameters.
+ *
+ * @param pulTaskStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallEnter_1( uint32_t * pulTaskStack,
+                             uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the task stack so that upon returning from
-     * SVC, the task stack is used again.
-     *
-     * @param pulSystemCallStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the task stack so that upon returning from
+ * SVC, the task stack is used again.
+ *
+ * @param pulSystemCallStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallExit( uint32_t * pulSystemCallStack,
+                          uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Checks whether or not the calling task is privileged.
-     *
-     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
-     */
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
     BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
 
 #endif /* configENABLE_MPU == 1 */
@@ -1086,18 +1089,18 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             vRestoreContextOfFirstTask();
             break;
 
-        #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
-            case portSVC_RAISE_PRIVILEGE:
+            #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+                case portSVC_RAISE_PRIVILEGE:
 
-                /* Only raise the privilege, if the svc was raised from any of
-                 * the system calls. */
-                if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
-                    ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
-                {
-                    vRaisePrivilege();
-                }
-                break;
-        #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+                    /* Only raise the privilege, if the svc was raised from any of
+                     * the system calls. */
+                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+                    {
+                        vRaisePrivilege();
+                    }
+                    break;
+            #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
         default:
             /* Incorrect SVC call. */
@@ -1108,513 +1111,526 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulSystemCallStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallEnter( uint32_t * pulTaskStack,
+                           uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulSystemCallStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        /* This is not NULL only for the duration of the system call. */
-        configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+        #if defined( __ARMCC_VERSION )
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+
+            /* This is not NULL only for the duration of the system call. */
+            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the system call stack for the stack frame. */
+            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulSystemCallStack[ i ] = pulTaskStack[ i ];
+            }
+
+            /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
+             * restore it when we exit from the system call. */
+            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* Use the pulSystemCallStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+
+            /* Remember the location where we should copy the stack frame when we exit from
+             * the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+
+            /* Record if the hardware used padding to force the stack pointer
+             * to be double word aligned. */
+            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
+            {
+                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
             }
+
+            /* We ensure in pxPortInitialiseStack that the system call stack is
+             * double word aligned and therefore, there is no need of padding.
+             * Clear the bit[9] of stacked xPSR. */
+            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
+
+            /* Raise the privilege for the duration of the system call. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " bics r0, r1         \n" /* Clear nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the system call stack for the stack frame. */
-        pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulSystemCallStack[ i ] = pulTaskStack[ i ];
-        }
-
-        /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
-         * restore it when we exit from the system call. */
-        pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-        __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* Use the pulSystemCallStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-
-        /* Remember the location where we should copy the stack frame when we exit from
-         * the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-        /* Record if the hardware used padding to force the stack pointer
-         * to be double word aligned. */
-        if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-        {
-            pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-        }
-        else
-        {
-            pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-        }
-
-        /* We ensure in pxPortInitialiseStack that the system call stack is
-         * double word aligned and therefore, there is no need of padding.
-         * Clear the bit[9] of stacked xPSR. */
-        pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-        /* Raise the privilege for the duration of the system call. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " bics r0, r1         \n" /* Clear nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulSystemCallStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallEnter_1( uint32_t * pulTaskStack,
+                             uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulSystemCallStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        /* This is not NULL only for the duration of the system call. */
-        configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+        #if defined( __ARMCC_VERSION )
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+
+            /* This is not NULL only for the duration of the system call. */
+            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the system call stack for the stack frame and
+             * the parameter passed on the stack. We only need to copy one
+             * parameter but we still reserve 2 spaces to keep the stack
+             * double word aligned. */
+            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulSystemCallStack[ i ] = pulTaskStack[ i ];
+            }
+
+            /* Copy the parameter which is passed the stack. */
+            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
+            {
+                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
+
+                /* Record if the hardware used padding to force the stack pointer
+                 * to be double word aligned. */
+                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
+
+                /* Record if the hardware used padding to force the stack pointer
+                 * to be double word aligned. */
+                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
             }
+
+            /* Store the value of the LR and PSPLIM registers before the SVC was raised.
+             * We need to restore it when we exit from the system call. */
+            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* Use the pulSystemCallStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+
+            /* Remember the location where we should copy the stack frame when we exit from
+             * the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+
+            /* We ensure in pxPortInitialiseStack that the system call stack is
+             * double word aligned and therefore, there is no need of padding.
+             * Clear the bit[9] of stacked xPSR. */
+            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
+
+            /* Raise the privilege for the duration of the system call. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " bics r0, r1         \n" /* Clear nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the system call stack for the stack frame and
-         * the parameter passed on the stack. We only need to copy one
-         * parameter but we still reserve 2 spaces to keep the stack
-         * double word aligned. */
-        pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulSystemCallStack[ i ] = pulTaskStack[ i ];
-        }
-
-        /* Copy the parameter which is passed the stack. */
-        if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-        {
-            pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
-            /* Record if the hardware used padding to force the stack pointer
-             * to be double word aligned. */
-            pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-        }
-        else
-        {
-            pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
-            /* Record if the hardware used padding to force the stack pointer
-             * to be double word aligned. */
-            pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-        }
-
-        /* Store the value of the LR and PSPLIM registers before the SVC was raised.
-         * We need to restore it when we exit from the system call. */
-        pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-        __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* Use the pulSystemCallStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-
-        /* Remember the location where we should copy the stack frame when we exit from
-         * the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-        /* We ensure in pxPortInitialiseStack that the system call stack is
-         * double word aligned and therefore, there is no need of padding.
-         * Clear the bit[9] of stacked xPSR. */
-        pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-        /* Raise the privilege for the duration of the system call. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " bics r0, r1         \n" /* Clear nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulTaskStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallExit( uint32_t * pulSystemCallStack,
+                          uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulTaskStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+        #if defined( __ARMCC_VERSION )
+
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the task stack for the stack frame. */
+            pulTaskStack = pulTaskStack - ulStackFrameSize;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulTaskStack[ i ] = pulSystemCallStack[ i ];
+            }
+
+            /* Use the pulTaskStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
+
+            /* Restore the LR and PSPLIM to what they were at the time of
+             * system call entry. */
+            pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* If the hardware used padding to force the stack pointer
+             * to be double word aligned, set the stacked xPSR bit[9],
+             * otherwise clear it. */
+            if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG )
+            {
+                pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
             }
+
+            /* This is not NULL only for the duration of the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
+
+            /* Drop the privilege before returning to the thread mode. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " orrs r0, r1         \n" /* Set nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the task stack for the stack frame. */
-        pulTaskStack = pulTaskStack - ulStackFrameSize;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulTaskStack[ i ] = pulSystemCallStack[ i ];
-        }
-
-        /* Use the pulTaskStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
-
-        /* Restore the LR and PSPLIM to what they were at the time of
-         * system call entry. */
-        pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* If the hardware used padding to force the stack pointer
-         * to be double word aligned, set the stacked xPSR bit[9],
-         * otherwise clear it. */
-        if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG )
-        {
-            pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK;
-        }
-        else
-        {
-            pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-        }
-
-        /* This is not NULL only for the duration of the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
-
-        /* Drop the privilege before returning to the thread mode. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " orrs r0, r1         \n" /* Set nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */
-{
-    BaseType_t xTaskIsPrivileged = pdFALSE;
-    const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
-
-    if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+    BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */
     {
-        xTaskIsPrivileged = pdTRUE;
-    }
+        BaseType_t xTaskIsPrivileged = pdFALSE;
+        const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
 
-    return xTaskIsPrivileged;
-}
+        if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+        {
+            xTaskIsPrivileged = pdTRUE;
+        }
+
+        return xTaskIsPrivileged;
+    }
 
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
-#if( configENABLE_MPU == 1 )
+#if ( configENABLE_MPU == 1 )
 
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     StackType_t * pxEndOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters,
-                                     BaseType_t xRunPrivileged,
-                                     xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
-{
-    uint32_t ulIndex = 0;
-
-    xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
-    ulIndex++;
-
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
-    ulIndex++;
-
-    #if ( configENABLE_TRUSTZONE == 1 )
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters,
+                                         BaseType_t xRunPrivileged,
+                                         xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
     {
-        xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT;  /* xSecureContext. */
+        uint32_t ulIndex = 0;
+
+        xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
         ulIndex++;
-    }
-    #endif /* configENABLE_TRUSTZONE */
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
-    ulIndex++;
-    if( xRunPrivileged == pdTRUE )
-    {
-        xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */
         ulIndex++;
-    }
-    else
-    {
-        xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */
         ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
+        ulIndex++;
+
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters;            /* r0. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x01010101;                           /* r1. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x02020202;                           /* r2. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x03030303;                           /* r3. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x12121212;                           /* r12. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode;                  /* PC. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR;                     /* xPSR. */
+        ulIndex++;
+
+        #if ( configENABLE_TRUSTZONE == 1 )
+        {
+            xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT; /* xSecureContext. */
+            ulIndex++;
+        }
+        #endif /* configENABLE_TRUSTZONE */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
+        ulIndex++;
+
+        if( xRunPrivileged == pdTRUE )
+        {
+            xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
+            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+            ulIndex++;
+        }
+        else
+        {
+            xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
+            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+            ulIndex++;
+        }
+
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
+        ulIndex++;
+
+        #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+        {
+            /* Ensure that the system call stack is double word aligned. */
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] );
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) &
+                                                                                     ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
+
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] );
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) +
+                                                                                            ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) &
+                                                                                          ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
+
+            /* This is not NULL only for the duration of a system call. */
+            xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL;
+        }
+        #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
+
+        return &( xMPUSettings->ulContext[ ulIndex ] );
     }
-    xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
-    ulIndex++;
-
-    #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
-    {
-        /* Ensure that the system call stack is double word aligned. */
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] );
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) &
-                                                                                 ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
-
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] );
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) +
-                                                                                        ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) &
-                                                                                      ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
-
-        /* This is not NULL only for the duration of a system call. */
-        xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL;
-    }
-    #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
-
-    return &( xMPUSettings->ulContext[ ulIndex ] );
-}
 
 #else /* configENABLE_MPU */
 
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     StackType_t * pxEndOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters ) /* PRIVILEGED_FUNCTION */
-{
-    /* Simulate the stack frame as it would be created by a context switch
-     * interrupt. */
-    #if ( portPRELOAD_REGISTERS == 0 )
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters ) /* PRIVILEGED_FUNCTION */
     {
-        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-        pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
-        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-        pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
-        *pxTopOfStack = portINITIAL_EXC_RETURN;
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
-
-        #if ( configENABLE_TRUSTZONE == 1 )
+        /* Simulate the stack frame as it would be created by a context switch
+         * interrupt. */
+        #if ( portPRELOAD_REGISTERS == 0 )
         {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
-        }
-        #endif /* configENABLE_TRUSTZONE */
-    }
-    #else /* portPRELOAD_REGISTERS */
-    {
-        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
-        pxTopOfStack--;
-        *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
+            pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
+            *pxTopOfStack = portINITIAL_EXC_RETURN;
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+            #if ( configENABLE_TRUSTZONE == 1 )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+            }
+            #endif /* configENABLE_TRUSTZONE */
+        }
+        #else /* portPRELOAD_REGISTERS */
         {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
-        }
-        #endif /* configENABLE_TRUSTZONE */
-    }
-    #endif /* portPRELOAD_REGISTERS */
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
+            pxTopOfStack--;
+            *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack;            /* Slot used to hold this task's PSPLIM value. */
 
-    return pxTopOfStack;
-}
+            #if ( configENABLE_TRUSTZONE == 1 )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+            }
+            #endif /* configENABLE_TRUSTZONE */
+        }
+        #endif /* portPRELOAD_REGISTERS */
+
+        return pxTopOfStack;
+    }
 
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.c b/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.c
index 504b6bf3b..e533dd7e9 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.c
@@ -42,111 +42,111 @@
 
 #if ( configENABLE_MPU == 1 )
 
-void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        " .syntax unified                                 \n"
-        "                                                 \n"
-        " program_mpu_first_task:                         \n"
-        "    ldr r2, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB. */
-        "                                                 \n"
-        "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-        "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
-        "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
-        "    str r2, [r1]                                 \n" /* Disable MPU. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
-        "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-        "    ldr r2, xMAIR0Const2                         \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-        "    str r1, [r2]                                 \n" /* Program MAIR0. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-        "    ldr r1, xRNRConst2                           \n" /* r1 = 0xe000ed98 [Location of RNR]. */
-        "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "                                                 \n"
-        "    movs r3, #4                                  \n" /* r3 = 4. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 4. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-        "                                                 \n"
-    #if ( configTOTAL_MPU_REGIONS == 16 )
-        "    movs r3, #8                                  \n" /* r3 = 8. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 8. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-        "    movs r3, #12                                 \n" /* r3 = 12. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 12. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-    #endif /* configTOTAL_MPU_REGIONS == 16 */
-        "                                                 \n"
-        "   ldr r1, xMPUCTRLConst2                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
-        "   orr r2, #1                                    \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
-        "   str r2, [r1]                                  \n" /* Enable MPU. */
-        "   dsb                                           \n" /* Force memory writes before continuing. */
-        "                                                 \n"
-        " restore_context_first_task:                     \n"
-        "    ldr r2, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB.*/
-        "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
-        "                                                 \n"
-        " restore_special_regs_first_task:                \n"
-        "    ldmdb r1!, {r2-r4, lr}                       \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
-        "    msr psp, r2                                  \n"
-        "    msr psplim, r3                               \n"
-        "    msr control, r4                              \n"
-        "                                                 \n"
-        " restore_general_regs_first_task:                \n"
-        "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
-        "    stmia r2!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
-        "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 restored. */
-        "                                                 \n"
-        " restore_context_done_first_task:                \n"
-        "    str r1, [r0]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
-        "    mov r0, #0                                   \n"
-        "    msr basepri, r0                              \n" /* Ensure that interrupts are enabled when the first task starts. */
-        "    bx lr                                        \n"
-        "                                                 \n"
-        " .align 4                                        \n"
-        " pxCurrentTCBConst2: .word pxCurrentTCB          \n"
-        " xMPUCTRLConst2: .word 0xe000ed94                \n"
-        " xMAIR0Const2: .word 0xe000edc0                  \n"
-        " xRNRConst2: .word 0xe000ed98                    \n"
-        " xRBARConst2: .word 0xe000ed9c                   \n"
-    );
-}
+    void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                 \n"
+            "                                                 \n"
+            " program_mpu_first_task:                         \n"
+            "    ldr r2, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB. */
+            "                                                 \n"
+            "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
+            "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
+            "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
+            "    str r2, [r1]                                 \n" /* Disable MPU. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
+            "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
+            "    ldr r2, xMAIR0Const2                         \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    str r1, [r2]                                 \n" /* Program MAIR0. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
+            "    ldr r1, xRNRConst2                           \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "                                                 \n"
+            "    movs r3, #4                                  \n" /* r3 = 4. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 4. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "                                                 \n"
+            #if ( configTOTAL_MPU_REGIONS == 16 )
+                "    movs r3, #8                                  \n" /* r3 = 8. */
+                "    str r3, [r1]                                 \n" /* Program RNR = 8. */
+                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+                "    movs r3, #12                                 \n" /* r3 = 12. */
+                "    str r3, [r1]                                 \n" /* Program RNR = 12. */
+                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            #endif /* configTOTAL_MPU_REGIONS == 16 */
+            "                                                 \n"
+            "   ldr r1, xMPUCTRLConst2                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
+            "   orr r2, #1                                    \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
+            "   str r2, [r1]                                  \n" /* Enable MPU. */
+            "   dsb                                           \n" /* Force memory writes before continuing. */
+            "                                                 \n"
+            " restore_context_first_task:                     \n"
+            "    ldr r2, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB.*/
+            "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
+            "                                                 \n"
+            " restore_special_regs_first_task:                \n"
+            "    ldmdb r1!, {r2-r4, lr}                       \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
+            "    msr psp, r2                                  \n"
+            "    msr psplim, r3                               \n"
+            "    msr control, r4                              \n"
+            "                                                 \n"
+            " restore_general_regs_first_task:                \n"
+            "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
+            "    stmia r2!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
+            "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 restored. */
+            "                                                 \n"
+            " restore_context_done_first_task:                \n"
+            "    str r1, [r0]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
+            "    mov r0, #0                                   \n"
+            "    msr basepri, r0                              \n" /* Ensure that interrupts are enabled when the first task starts. */
+            "    bx lr                                        \n"
+            "                                                 \n"
+            " .align 4                                        \n"
+            " pxCurrentTCBConst2: .word pxCurrentTCB          \n"
+            " xMPUCTRLConst2: .word 0xe000ed94                \n"
+            " xMAIR0Const2: .word 0xe000edc0                  \n"
+            " xRNRConst2: .word 0xe000ed98                    \n"
+            " xRBARConst2: .word 0xe000ed9c                   \n"
+        );
+    }
 
 #else /* configENABLE_MPU */
 
-void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "   .syntax unified                                 \n"
-        "                                                   \n"
-        "   ldr  r2, pxCurrentTCBConst2                     \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr  r1, [r2]                                   \n"/* Read pxCurrentTCB. */
-        "   ldr  r0, [r1]                                   \n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
-        "                                                   \n"
-        "   ldm  r0!, {r1-r2}                               \n"/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
-        "   msr  psplim, r1                                 \n"/* Set this task's PSPLIM value. */
-        "   movs r1, #2                                     \n"/* r1 = 2. */
-        "   msr  CONTROL, r1                                \n"/* Switch to use PSP in the thread mode. */
-        "   adds r0, #32                                    \n"/* Discard everything up to r0. */
-        "   msr  psp, r0                                    \n"/* This is now the new top of stack to use in the task. */
-        "   isb                                             \n"
-        "   mov  r0, #0                                     \n"
-        "   msr  basepri, r0                                \n"/* Ensure that interrupts are enabled when the first task starts. */
-        "   bx   r2                                         \n"/* Finally, branch to EXC_RETURN. */
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "pxCurrentTCBConst2: .word pxCurrentTCB             \n"
-    );
-}
+    void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            "   .syntax unified                                 \n"
+            "                                                   \n"
+            "   ldr  r2, pxCurrentTCBConst2                     \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr  r1, [r2]                                   \n" /* Read pxCurrentTCB. */
+            "   ldr  r0, [r1]                                   \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+            "                                                   \n"
+            "   ldm  r0!, {r1-r2}                               \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
+            "   msr  psplim, r1                                 \n" /* Set this task's PSPLIM value. */
+            "   movs r1, #2                                     \n" /* r1 = 2. */
+            "   msr  CONTROL, r1                                \n" /* Switch to use PSP in the thread mode. */
+            "   adds r0, #32                                    \n" /* Discard everything up to r0. */
+            "   msr  psp, r0                                    \n" /* This is now the new top of stack to use in the task. */
+            "   isb                                             \n"
+            "   mov  r0, #0                                     \n"
+            "   msr  basepri, r0                                \n" /* Ensure that interrupts are enabled when the first task starts. */
+            "   bx   r2                                         \n" /* Finally, branch to EXC_RETURN. */
+            "                                                   \n"
+            "   .align 4                                        \n"
+            "pxCurrentTCBConst2: .word pxCurrentTCB             \n"
+        );
+    }
 
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
@@ -157,12 +157,12 @@ BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs r0, control                                 \n"/* r0 = CONTROL. */
-        "   tst r0, #1                                      \n"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+        "   mrs r0, control                                 \n" /* r0 = CONTROL. */
+        "   tst r0, #1                                      \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
         "   ite ne                                          \n"
-        "   movne r0, #0                                    \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
-        "   moveq r0, #1                                    \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
-        "   bx lr                                           \n"/* Return. */
+        "   movne r0, #0                                    \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+        "   moveq r0, #1                                    \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+        "   bx lr                                           \n" /* Return. */
         "                                                   \n"
         "   .align 4                                        \n"
         ::: "r0", "memory"
@@ -176,10 +176,10 @@ void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs  r0, control                                \n"/* Read the CONTROL register. */
-        "   bic r0, #1                                      \n"/* Clear the bit 0. */
-        "   msr  control, r0                                \n"/* Write back the new CONTROL value. */
-        "   bx lr                                           \n"/* Return to the caller. */
+        "   mrs  r0, control                                \n" /* Read the CONTROL register. */
+        "   bic r0, #1                                      \n" /* Clear the bit 0. */
+        "   msr  control, r0                                \n" /* Write back the new CONTROL value. */
+        "   bx lr                                           \n" /* Return to the caller. */
         ::: "r0", "memory"
     );
 }
@@ -191,10 +191,10 @@ void vResetPrivilege( void ) /* __attribute__ (( naked )) */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs r0, control                                 \n"/* r0 = CONTROL. */
-        "   orr r0, #1                                      \n"/* r0 = r0 | 1. */
-        "   msr control, r0                                 \n"/* CONTROL = r0. */
-        "   bx lr                                           \n"/* Return to the caller. */
+        "   mrs r0, control                                 \n" /* r0 = CONTROL. */
+        "   orr r0, #1                                      \n" /* r0 = r0 | 1. */
+        "   msr control, r0                                 \n" /* CONTROL = r0. */
+        "   bx lr                                           \n" /* Return to the caller. */
         ::: "r0", "memory"
     );
 }
@@ -206,15 +206,15 @@ void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   ldr r0, xVTORConst                              \n"/* Use the NVIC offset register to locate the stack. */
-        "   ldr r0, [r0]                                    \n"/* Read the VTOR register which gives the address of vector table. */
-        "   ldr r0, [r0]                                    \n"/* The first entry in vector table is stack pointer. */
-        "   msr msp, r0                                     \n"/* Set the MSP back to the start of the stack. */
-        "   cpsie i                                         \n"/* Globally enable interrupts. */
+        "   ldr r0, xVTORConst                              \n" /* Use the NVIC offset register to locate the stack. */
+        "   ldr r0, [r0]                                    \n" /* Read the VTOR register which gives the address of vector table. */
+        "   ldr r0, [r0]                                    \n" /* The first entry in vector table is stack pointer. */
+        "   msr msp, r0                                     \n" /* Set the MSP back to the start of the stack. */
+        "   cpsie i                                         \n" /* Globally enable interrupts. */
         "   cpsie f                                         \n"
         "   dsb                                             \n"
         "   isb                                             \n"
-        "   svc %0                                          \n"/* System call to start the first task. */
+        "   svc %0                                          \n" /* System call to start the first task. */
         "   nop                                             \n"
         "                                                   \n"
         "   .align 4                                        \n"
@@ -230,12 +230,12 @@ uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCT
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs r0, basepri                                 \n"/* r0 = basepri. Return original basepri value. */
-        "   mov r1, %0                                      \n"/* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        "   msr basepri, r1                                 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        "   mrs r0, basepri                                 \n" /* r0 = basepri. Return original basepri value. */
+        "   mov r1, %0                                      \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        "   msr basepri, r1                                 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
         "   dsb                                             \n"
         "   isb                                             \n"
-        "   bx lr                                           \n"/* Return. */
+        "   bx lr                                           \n" /* Return. */
         ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
     );
 }
@@ -247,10 +247,10 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   msr basepri, r0                                 \n"/* basepri = ulMask. */
+        "   msr basepri, r0                                 \n" /* basepri = ulMask. */
         "   dsb                                             \n"
         "   isb                                             \n"
-        "   bx lr                                           \n"/* Return. */
+        "   bx lr                                           \n" /* Return. */
         ::: "memory"
     );
 }
@@ -258,246 +258,246 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
 
 #if ( configENABLE_MPU == 1 )
 
-void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        " .syntax unified                                 \n"
-        "                                                 \n"
-        " ldr r2, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        " ldr r0, [r2]                                    \n" /* r0 = pxCurrentTCB. */
-        " ldr r1, [r0]                                    \n" /* r1 = Location in TCB where the context should be saved. */
-        " mrs r2, psp                                     \n" /* r2 = PSP. */
-        "                                                 \n"
-        " save_general_regs:                              \n"
-    #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-        "    add r2, r2, #0x20                            \n" /* Move r2 to location where s0 is saved. */
-        "    tst lr, #0x10                                \n"
-        "    ittt eq                                      \n"
-        "    vstmiaeq r1!, {s16-s31}                      \n" /* Store s16-s31. */
-        "    vldmiaeq r2, {s0-s16}                        \n" /* Copy hardware saved FP context into s0-s16. */
-        "    vstmiaeq r1!, {s0-s16}                       \n" /* Store hardware saved FP context. */
-        "    sub r2, r2, #0x20                            \n" /* Set r2 back to the location of hardware saved context. */
-    #endif /* configENABLE_FPU || configENABLE_MVE */
-        "                                                 \n"
-        "    stmia r1!, {r4-r11}                          \n" /* Store r4-r11. */
-        "    ldmia r2, {r4-r11}                           \n" /* Copy the hardware saved context into r4-r11. */
-        "    stmia r1!, {r4-r11}                          \n" /* Store the hardware saved context. */
-        "                                                 \n"
-        " save_special_regs:                              \n"
-        "    mrs r3, psplim                               \n" /* r3 = PSPLIM. */
-        "    mrs r4, control                              \n" /* r4 = CONTROL. */
-        "    stmia r1!, {r2-r4, lr}                       \n" /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
-        "    str r1, [r0]                                 \n" /* Save the location from where the context should be restored as the first member of TCB. */
-        "                                                 \n"
-        " select_next_task:                               \n"
-        "    mov r0, %0                                   \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
-        "    msr basepri, r0                              \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        "    dsb                                          \n"
-        "    isb                                          \n"
-        "    bl vTaskSwitchContext                        \n"
-        "    mov r0, #0                                   \n" /* r0 = 0. */
-        "    msr basepri, r0                              \n" /* Enable interrupts. */
-        "                                                 \n"
-        " program_mpu:                                    \n"
-        "    ldr r2, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB. */
-        "                                                 \n"
-        "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-        "    ldr r1, xMPUCTRLConst                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
-        "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
-        "    str r2, [r1]                                 \n" /* Disable MPU. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
-        "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-        "    ldr r2, xMAIR0Const                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-        "    str r1, [r2]                                 \n" /* Program MAIR0. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-        "    ldr r1, xRNRConst                            \n" /* r1 = 0xe000ed98 [Location of RNR]. */
-        "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "                                                 \n"
-        "    movs r3, #4                                  \n" /* r3 = 4. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 4. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-        "                                                 \n"
-    #if ( configTOTAL_MPU_REGIONS == 16 )
-        "    movs r3, #8                                  \n" /* r3 = 8. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 8. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-        "    movs r3, #12                                 \n" /* r3 = 12. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 12. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-    #endif /* configTOTAL_MPU_REGIONS == 16 */
-        "                                                 \n"
-        "   ldr r1, xMPUCTRLConst                         \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
-        "   orr r2, #1                                    \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
-        "   str r2, [r1]                                  \n" /* Enable MPU. */
-        "   dsb                                           \n" /* Force memory writes before continuing. */
-        "                                                 \n"
-        " restore_context:                                \n"
-        "    ldr r2, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB.*/
-        "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
-        "                                                 \n"
-        " restore_special_regs:                           \n"
-        "    ldmdb r1!, {r2-r4, lr}                       \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
-        "    msr psp, r2                                  \n"
-        "    msr psplim, r3                               \n"
-        "    msr control, r4                              \n"
-        "                                                 \n"
-        " restore_general_regs:                           \n"
-        "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
-        "    stmia r2!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
-        "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 restored. */
-    #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-        "    tst lr, #0x10                                \n"
-        "    ittt eq                                      \n"
-        "    vldmdbeq r1!, {s0-s16}                       \n" /* s0-s16 contain hardware saved FP context. */
-        "    vstmiaeq r2!, {s0-s16}                       \n" /* Copy hardware saved FP context on the task stack. */
-        "    vldmdbeq r1!, {s16-s31}                      \n" /* Restore s16-s31. */
-    #endif /* configENABLE_FPU || configENABLE_MVE */
-        "                                                 \n"
-        " restore_context_done:                           \n"
-        "    str r1, [r0]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
-        "    bx lr                                        \n"
-        "                                                 \n"
-        " .align 4                                        \n"
-        " pxCurrentTCBConst: .word pxCurrentTCB           \n"
-        " xMPUCTRLConst: .word 0xe000ed94                 \n"
-        " xMAIR0Const: .word 0xe000edc0                   \n"
-        " xRNRConst: .word 0xe000ed98                     \n"
-        " xRBARConst: .word 0xe000ed9c                    \n"
-        ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
-    );
-}
+    void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                 \n"
+            "                                                 \n"
+            " ldr r2, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            " ldr r0, [r2]                                    \n" /* r0 = pxCurrentTCB. */
+            " ldr r1, [r0]                                    \n" /* r1 = Location in TCB where the context should be saved. */
+            " mrs r2, psp                                     \n" /* r2 = PSP. */
+            "                                                 \n"
+            " save_general_regs:                              \n"
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+                "    add r2, r2, #0x20                            \n" /* Move r2 to location where s0 is saved. */
+                "    tst lr, #0x10                                \n"
+                "    ittt eq                                      \n"
+                "    vstmiaeq r1!, {s16-s31}                      \n" /* Store s16-s31. */
+                "    vldmiaeq r2, {s0-s16}                        \n" /* Copy hardware saved FP context into s0-s16. */
+                "    vstmiaeq r1!, {s0-s16}                       \n" /* Store hardware saved FP context. */
+                "    sub r2, r2, #0x20                            \n" /* Set r2 back to the location of hardware saved context. */
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+            "                                                 \n"
+            "    stmia r1!, {r4-r11}                          \n" /* Store r4-r11. */
+            "    ldmia r2, {r4-r11}                           \n" /* Copy the hardware saved context into r4-r11. */
+            "    stmia r1!, {r4-r11}                          \n" /* Store the hardware saved context. */
+            "                                                 \n"
+            " save_special_regs:                              \n"
+            "    mrs r3, psplim                               \n" /* r3 = PSPLIM. */
+            "    mrs r4, control                              \n" /* r4 = CONTROL. */
+            "    stmia r1!, {r2-r4, lr}                       \n" /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
+            "    str r1, [r0]                                 \n" /* Save the location from where the context should be restored as the first member of TCB. */
+            "                                                 \n"
+            " select_next_task:                               \n"
+            "    mov r0, %0                                   \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
+            "    msr basepri, r0                              \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+            "    dsb                                          \n"
+            "    isb                                          \n"
+            "    bl vTaskSwitchContext                        \n"
+            "    mov r0, #0                                   \n" /* r0 = 0. */
+            "    msr basepri, r0                              \n" /* Enable interrupts. */
+            "                                                 \n"
+            " program_mpu:                                    \n"
+            "    ldr r2, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB. */
+            "                                                 \n"
+            "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
+            "    ldr r1, xMPUCTRLConst                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
+            "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
+            "    str r2, [r1]                                 \n" /* Disable MPU. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
+            "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
+            "    ldr r2, xMAIR0Const                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    str r1, [r2]                                 \n" /* Program MAIR0. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
+            "    ldr r1, xRNRConst                            \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "                                                 \n"
+            "    movs r3, #4                                  \n" /* r3 = 4. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 4. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "                                                 \n"
+            #if ( configTOTAL_MPU_REGIONS == 16 )
+                "    movs r3, #8                                  \n" /* r3 = 8. */
+                "    str r3, [r1]                                 \n" /* Program RNR = 8. */
+                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+                "    movs r3, #12                                 \n" /* r3 = 12. */
+                "    str r3, [r1]                                 \n" /* Program RNR = 12. */
+                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            #endif /* configTOTAL_MPU_REGIONS == 16 */
+            "                                                 \n"
+            "   ldr r1, xMPUCTRLConst                         \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
+            "   orr r2, #1                                    \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
+            "   str r2, [r1]                                  \n" /* Enable MPU. */
+            "   dsb                                           \n" /* Force memory writes before continuing. */
+            "                                                 \n"
+            " restore_context:                                \n"
+            "    ldr r2, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB.*/
+            "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
+            "                                                 \n"
+            " restore_special_regs:                           \n"
+            "    ldmdb r1!, {r2-r4, lr}                       \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
+            "    msr psp, r2                                  \n"
+            "    msr psplim, r3                               \n"
+            "    msr control, r4                              \n"
+            "                                                 \n"
+            " restore_general_regs:                           \n"
+            "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
+            "    stmia r2!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
+            "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 restored. */
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+                "    tst lr, #0x10                                \n"
+                "    ittt eq                                      \n"
+                "    vldmdbeq r1!, {s0-s16}                       \n" /* s0-s16 contain hardware saved FP context. */
+                "    vstmiaeq r2!, {s0-s16}                       \n" /* Copy hardware saved FP context on the task stack. */
+                "    vldmdbeq r1!, {s16-s31}                      \n" /* Restore s16-s31. */
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+            "                                                 \n"
+            " restore_context_done:                           \n"
+            "    str r1, [r0]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
+            "    bx lr                                        \n"
+            "                                                 \n"
+            " .align 4                                        \n"
+            " pxCurrentTCBConst: .word pxCurrentTCB           \n"
+            " xMPUCTRLConst: .word 0xe000ed94                 \n"
+            " xMAIR0Const: .word 0xe000edc0                   \n"
+            " xRNRConst: .word 0xe000ed98                     \n"
+            " xRBARConst: .word 0xe000ed9c                    \n"
+            ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+        );
+    }
 
 #else /* configENABLE_MPU */
 
-void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "   .syntax unified                                 \n"
-        "                                                   \n"
-        "   mrs r0, psp                                     \n"/* Read PSP in r0. */
-        "                                                   \n"
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-            "   tst lr, #0x10                                   \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
-            "   it eq                                           \n"
-            "   vstmdbeq r0!, {s16-s31}                         \n"/* Store the additional FP context registers which are not saved automatically. */
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-        "                                                   \n"
-        "   mrs r2, psplim                                  \n"/* r2 = PSPLIM. */
-        "   mov r3, lr                                      \n"/* r3 = LR/EXC_RETURN. */
-        "   stmdb r0!, {r2-r11}                             \n"/* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */
-        "                                                   \n"
-        "   ldr r2, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r2]                                    \n"/* Read pxCurrentTCB. */
-        "   str r0, [r1]                                    \n"/* Save the new top of stack in TCB. */
-        "                                                   \n"
-        "   mov r0, %0                                      \n"/* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
-        "   msr basepri, r0                                 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        "   dsb                                             \n"
-        "   isb                                             \n"
-        "   bl vTaskSwitchContext                           \n"
-        "   mov r0, #0                                      \n"/* r0 = 0. */
-        "   msr basepri, r0                                 \n"/* Enable interrupts. */
-        "                                                   \n"
-        "   ldr r2, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r2]                                    \n"/* Read pxCurrentTCB. */
-        "   ldr r0, [r1]                                    \n"/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
-        "                                                   \n"
-        "   ldmia r0!, {r2-r11}                             \n"/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
-        "                                                   \n"
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-            "   tst r3, #0x10                                   \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
-            "   it eq                                           \n"
-            "   vldmiaeq r0!, {s16-s31}                         \n"/* Restore the additional FP context registers which are not restored automatically. */
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-        "                                                   \n"
-        "   msr psplim, r2                                  \n"/* Restore the PSPLIM register value for the task. */
-        "   msr psp, r0                                     \n"/* Remember the new top of stack for the task. */
-        "   bx r3                                           \n"
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "pxCurrentTCBConst: .word pxCurrentTCB              \n"
-        ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
-    );
-}
+    void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            "   .syntax unified                                 \n"
+            "                                                   \n"
+            "   mrs r0, psp                                     \n" /* Read PSP in r0. */
+            "                                                   \n"
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+                "   tst lr, #0x10                                   \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+                "   it eq                                           \n"
+                "   vstmdbeq r0!, {s16-s31}                         \n" /* Store the additional FP context registers which are not saved automatically. */
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+            "                                                   \n"
+            "   mrs r2, psplim                                  \n" /* r2 = PSPLIM. */
+            "   mov r3, lr                                      \n" /* r3 = LR/EXC_RETURN. */
+            "   stmdb r0!, {r2-r11}                             \n" /* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */
+            "                                                   \n"
+            "   ldr r2, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r1, [r2]                                    \n" /* Read pxCurrentTCB. */
+            "   str r0, [r1]                                    \n" /* Save the new top of stack in TCB. */
+            "                                                   \n"
+            "   mov r0, %0                                      \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
+            "   msr basepri, r0                                 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+            "   dsb                                             \n"
+            "   isb                                             \n"
+            "   bl vTaskSwitchContext                           \n"
+            "   mov r0, #0                                      \n" /* r0 = 0. */
+            "   msr basepri, r0                                 \n" /* Enable interrupts. */
+            "                                                   \n"
+            "   ldr r2, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r1, [r2]                                    \n" /* Read pxCurrentTCB. */
+            "   ldr r0, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
+            "                                                   \n"
+            "   ldmia r0!, {r2-r11}                             \n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
+            "                                                   \n"
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+                "   tst r3, #0x10                                   \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+                "   it eq                                           \n"
+                "   vldmiaeq r0!, {s16-s31}                         \n" /* Restore the additional FP context registers which are not restored automatically. */
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+            "                                                   \n"
+            "   msr psplim, r2                                  \n" /* Restore the PSPLIM register value for the task. */
+            "   msr psp, r0                                     \n" /* Remember the new top of stack for the task. */
+            "   bx r3                                           \n"
+            "                                                   \n"
+            "   .align 4                                        \n"
+            "pxCurrentTCBConst: .word pxCurrentTCB              \n"
+            ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+        );
+    }
 
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-   __asm volatile
-    (
-        ".syntax unified                \n"
-        ".extern vPortSVCHandler_C      \n"
-        ".extern vSystemCallEnter       \n"
-        ".extern vSystemCallEnter_1     \n"
-        ".extern vSystemCallExit        \n"
-        "                               \n"
-        "tst lr, #4                     \n"
-        "ite eq                         \n"
-        "mrseq r0, msp                  \n"
-        "mrsne r0, psp                  \n"
-        "                               \n"
-        "ldr r1, [r0, #24]              \n"
-        "ldrb r2, [r1, #-2]             \n"
-        "cmp r2, %0                     \n"
-        "beq syscall_enter              \n"
-        "cmp r2, %1                     \n"
-        "beq syscall_enter_1            \n"
-        "cmp r2, %2                     \n"
-        "beq syscall_exit               \n"
-        "b vPortSVCHandler_C            \n"
-        "                               \n"
-        "syscall_enter:                 \n"
-        "    mov r1, lr                 \n"
-        "    b vSystemCallEnter         \n"
-        "                               \n"
-        "syscall_enter_1:               \n"
-        "    mov r1, lr                 \n"
-        "    b vSystemCallEnter_1       \n"
-        "                               \n"
-        "syscall_exit:                  \n"
-        "    mov r1, lr                 \n"
-        "    b vSystemCallExit          \n"
-        "                               \n"
-        : /* No outputs. */
-        :"i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT )
-        : "r0", "r1", "r2", "memory"
-    );
-}
+    void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            ".syntax unified                \n"
+            ".extern vPortSVCHandler_C      \n"
+            ".extern vSystemCallEnter       \n"
+            ".extern vSystemCallEnter_1     \n"
+            ".extern vSystemCallExit        \n"
+            "                               \n"
+            "tst lr, #4                     \n"
+            "ite eq                         \n"
+            "mrseq r0, msp                  \n"
+            "mrsne r0, psp                  \n"
+            "                               \n"
+            "ldr r1, [r0, #24]              \n"
+            "ldrb r2, [r1, #-2]             \n"
+            "cmp r2, %0                     \n"
+            "beq syscall_enter              \n"
+            "cmp r2, %1                     \n"
+            "beq syscall_enter_1            \n"
+            "cmp r2, %2                     \n"
+            "beq syscall_exit               \n"
+            "b vPortSVCHandler_C            \n"
+            "                               \n"
+            "syscall_enter:                 \n"
+            "    mov r1, lr                 \n"
+            "    b vSystemCallEnter         \n"
+            "                               \n"
+            "syscall_enter_1:               \n"
+            "    mov r1, lr                 \n"
+            "    b vSystemCallEnter_1       \n"
+            "                               \n"
+            "syscall_exit:                  \n"
+            "    mov r1, lr                 \n"
+            "    b vSystemCallExit          \n"
+            "                               \n"
+            : /* No outputs. */
+            : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT )
+            : "r0", "r1", "r2", "memory"
+        );
+    }
 
 #else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
-void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "   .syntax unified                                 \n"
-        "                                                   \n"
-        "   tst lr, #4                                      \n"
-        "   ite eq                                          \n"
-        "   mrseq r0, msp                                   \n"
-        "   mrsne r0, psp                                   \n"
-        "   ldr r1, svchandler_address_const                \n"
-        "   bx r1                                           \n"
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "svchandler_address_const: .word vPortSVCHandler_C  \n"
-    );
-}
+    void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            "   .syntax unified                                 \n"
+            "                                                   \n"
+            "   tst lr, #4                                      \n"
+            "   ite eq                                          \n"
+            "   mrseq r0, msp                                   \n"
+            "   mrsne r0, psp                                   \n"
+            "   ldr r1, svchandler_address_const                \n"
+            "   bx r1                                           \n"
+            "                                                   \n"
+            "   .align 4                                        \n"
+            "svchandler_address_const: .word vPortSVCHandler_C  \n"
+        );
+    }
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/portmacro.h b/portable/GCC/ARM_CM85_NTZ/non_secure/portmacro.h
index d14448927..a6fda8a88 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/portmacro.h
@@ -53,9 +53,9 @@
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME                       "Cortex-M85"
-#define portHAS_ARMV8M_MAIN_EXTENSION       1
-#define portDONT_DISCARD                    __attribute__( ( used ) )
+#define portARCH_NAME                    "Cortex-M85"
+#define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
 /* ARMv8-M common port configurations. */
@@ -65,8 +65,8 @@
 /**
  * @brief Critical section management.
  */
-#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()
-#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )
+#define portDISABLE_INTERRUPTS()    ulSetInterruptMask()
+#define portENABLE_INTERRUPTS()     vClearInterruptMask( 0 )
 /*-----------------------------------------------------------*/
 
 /* *INDENT-OFF* */
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h
index e5ffdb48b..62e462a27 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h
@@ -81,8 +81,8 @@ typedef unsigned long    UBaseType_t;
     typedef uint32_t     TickType_t;
     #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-     * not need to be guarded with a critical section. */
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
     #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -117,7 +117,7 @@ extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGE
 extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
 
 #if ( configENABLE_TRUSTZONE == 1 )
-    extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize );     /* __attribute__ (( naked )) */
+    extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
     extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
 #endif /* configENABLE_TRUSTZONE */
 
@@ -188,13 +188,13 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Settings to define an MPU region.
-     */
+/**
+ * @brief Settings to define an MPU region.
+ */
     typedef struct MPURegionSettings
     {
-        uint32_t ulRBAR;     /**< RBAR for the region. */
-        uint32_t ulRLAR;     /**< RLAR for the region. */
+        uint32_t ulRBAR; /**< RBAR for the region. */
+        uint32_t ulRLAR; /**< RLAR for the region. */
     } MPURegionSettings_t;
 
     #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
@@ -203,9 +203,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-        /**
-         * @brief System call stack.
-         */
+/**
+ * @brief System call stack.
+ */
         typedef struct SYSTEM_CALL_STACK_INFO
         {
             uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ];
@@ -218,74 +218,74 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
-    /**
-     * @brief MPU settings as stored in the TCB.
-     */
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
     #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
 
-        #if( configENABLE_TRUSTZONE == 1 )
+        #if ( configENABLE_TRUSTZONE == 1 )
 
-            /*
-             * +-----------+---------------+----------+-----------------+------------------------------+-----+
-             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
-             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
-             * +-----------+---------------+----------+-----------------+------------------------------+-----+
-             *
-             * <-----------><--------------><---------><----------------><-----------------------------><---->
-             *      16             16            8               8                     5                   1
-             */
-            #define MAX_CONTEXT_SIZE 54
+/*
+ * +-----------+---------------+----------+-----------------+------------------------------+-----+
+ * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+ * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+ * +-----------+---------------+----------+-----------------+------------------------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><-----------------------------><---->
+ *      16             16            8               8                     5                   1
+ */
+            #define MAX_CONTEXT_SIZE    54
 
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-            /*
-             * +-----------+---------------+----------+-----------------+----------------------+-----+
-             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
-             * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
-             * +-----------+---------------+----------+-----------------+----------------------+-----+
-             *
-             * <-----------><--------------><---------><----------------><---------------------><---->
-             *      16             16            8               8                  4              1
-             */
-            #define MAX_CONTEXT_SIZE 53
+/*
+ * +-----------+---------------+----------+-----------------+----------------------+-----+
+ * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+ * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
+ * +-----------+---------------+----------+-----------------+----------------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><---------------------><---->
+ *      16             16            8               8                  4              1
+ */
+            #define MAX_CONTEXT_SIZE    53
 
         #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
 
     #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-        #if( configENABLE_TRUSTZONE == 1 )
+        #if ( configENABLE_TRUSTZONE == 1 )
 
-            /*
-             * +----------+-----------------+------------------------------+-----+
-             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
-             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
-             * +----------+-----------------+------------------------------+-----+
-             *
-             * <---------><----------------><------------------------------><---->
-             *     8               8                      5                   1
-             */
-            #define MAX_CONTEXT_SIZE 22
+/*
+ * +----------+-----------------+------------------------------+-----+
+ * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+ * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+ * +----------+-----------------+------------------------------+-----+
+ *
+ * <---------><----------------><------------------------------><---->
+ *     8               8                      5                   1
+ */
+            #define MAX_CONTEXT_SIZE    22
 
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-            /*
-             * +----------+-----------------+----------------------+-----+
-             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
-             * |          | PC, xPSR        | EXC_RETURN           |     |
-             * +----------+-----------------+----------------------+-----+
-             *
-             * <---------><----------------><----------------------><---->
-             *     8               8                  4              1
-             */
-            #define MAX_CONTEXT_SIZE 21
+/*
+ * +----------+-----------------+----------------------+-----+
+ * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+ * |          | PC, xPSR        | EXC_RETURN           |     |
+ * +----------+-----------------+----------------------+-----+
+ *
+ * <---------><----------------><----------------------><---->
+ *     8               8                  4              1
+ */
+            #define MAX_CONTEXT_SIZE    21
 
         #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
 
     #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-    /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
-    #define portSTACK_FRAME_HAS_PADDING_FLAG     ( 1UL << 0UL )
-    #define portTASK_IS_PRIVILEGED_FLAG          ( 1UL << 1UL )
+/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
+    #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
+    #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
     typedef struct MPU_SETTINGS
     {
@@ -364,49 +364,49 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-    /**
-     * @brief Allocate a secure context for the task.
-     *
-     * Tasks are not created with a secure context. Any task that is going to call
-     * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
-     * secure context before it calls any secure function.
-     *
-     * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
-     */
+/**
+ * @brief Allocate a secure context for the task.
+ *
+ * Tasks are not created with a secure context. Any task that is going to call
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+ * secure context before it calls any secure function.
+ *
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+ */
     #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
 
-    /**
-     * @brief Called when a task is deleted to delete the task's secure context,
-     * if it has one.
-     *
-     * @param[in] pxTCB The TCB of the task being deleted.
-     */
+/**
+ * @brief Called when a task is deleted to delete the task's secure context,
+ * if it has one.
+ *
+ * @param[in] pxTCB The TCB of the task being deleted.
+ */
     #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
 #endif /* configENABLE_TRUSTZONE */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Checks whether or not the processor is privileged.
-     *
-     * @return 1 if the processor is already privileged, 0 otherwise.
-     */
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
     #define portIS_PRIVILEGED()      xIsPrivileged()
 
-    /**
-     * @brief Raise an SVC request to raise privilege.
-     *
-     * The SVC handler checks that the SVC was raised from a system call and only
-     * then it raises the privilege. If this is called from any other place,
-     * the privilege is not raised.
-     */
+/**
+ * @brief Raise an SVC request to raise privilege.
+ *
+ * The SVC handler checks that the SVC was raised from a system call and only
+ * then it raises the privilege. If this is called from any other place,
+ * the privilege is not raised.
+ */
     #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
 
-    /**
-     * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
-     * register.
-     */
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
     #define portRESET_PRIVILEGE()    vResetPrivilege()
 #else
     #define portIS_PRIVILEGED()
@@ -419,12 +419,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     extern BaseType_t xPortIsTaskPrivileged( void );
 
-    /**
-     * @brief Checks whether or not the calling task is privileged.
-     *
-     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
-     */
-    #define portIS_TASK_PRIVILEGED()      xPortIsTaskPrivileged()
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
+    #define portIS_TASK_PRIVILEGED()    xPortIsTaskPrivileged()
 
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
@@ -439,9 +439,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * based on whether or not Mainline extension is implemented. */
 #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
     #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
-        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
     #else
-        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    0
     #endif
 #endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
 
@@ -450,9 +450,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  */
 #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
 
-    /**
-     * @brief Count the number of leading zeros in a 32-bit value.
-     */
+/**
+ * @brief Count the number of leading zeros in a 32-bit value.
+ */
     static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
     {
         uint32_t ulReturn;
@@ -462,7 +462,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         return ulReturn;
     }
 
-    /* Check the configuration. */
+/* Check the configuration. */
     #if ( configMAX_PRIORITIES > 32 )
         #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
     #endif
@@ -471,16 +471,16 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection.  Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
     #endif
 
-    /**
-     * @brief Store/clear the ready priorities in a bit map.
-     */
-    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+/**
+ * @brief Store/clear the ready priorities in a bit map.
+ */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )      ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )       ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 
-    /**
-     * @brief Get the priority of the highest-priority task that is ready to execute.
-     */
-    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )   uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+/**
+ * @brief Get the priority of the highest-priority task that is ready to execute.
+ */
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
 
 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CR5/port.c b/portable/GCC/ARM_CR5/port.c
index 2cbc24dbf..323ea916d 100644
--- a/portable/GCC/ARM_CR5/port.c
+++ b/portable/GCC/ARM_CR5/port.c
@@ -161,7 +161,7 @@
         portCPU_IRQ_DISABLE();                                \
         portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \
         __asm volatile ( "DSB       \n"                       \
-                         "ISB       \n");                         \
+                         "ISB       \n" );                    \
         portCPU_IRQ_ENABLE();                                 \
     }
 
@@ -525,7 +525,7 @@ void vPortEnterCritical( void )
     ulPortSetInterruptMask();
 
     /*
-     * Now interrupts are disabled ulCriticalNesting can be accessed
+     * Now that interrupts are disabled, ulCriticalNesting can be accessed
      * directly.  Increment ulCriticalNesting to keep a count of how many times
      * portENTER_CRITICAL() has been called.
      */
@@ -580,7 +580,7 @@ void FreeRTOS_Tick_Handler( void )
     portCPU_IRQ_DISABLE();
     portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
     __asm volatile ( "dsb       \n"
-                     "isb       \n"::: "memory" );
+                     "isb       \n" ::: "memory" );
     portCPU_IRQ_ENABLE();
 
     /* Increment the RTOS tick. */
@@ -640,7 +640,7 @@ uint32_t ulPortSetInterruptMask( void )
         ulReturn = pdFALSE;
         portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
         __asm volatile ( "dsb       \n"
-                         "isb       \n"::: "memory" );
+                         "isb       \n" ::: "memory" );
     }
 
     portCPU_IRQ_ENABLE();
diff --git a/portable/GCC/ARM_CRx_No_GIC/port.c b/portable/GCC/ARM_CRx_No_GIC/port.c
index 74d956345..ff2abf4ff 100644
--- a/portable/GCC/ARM_CRx_No_GIC/port.c
+++ b/portable/GCC/ARM_CRx_No_GIC/port.c
@@ -35,7 +35,7 @@
 
 #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
     /* Check the configuration. */
-    #if( configMAX_PRIORITIES > 32 )
+    #if ( configMAX_PRIORITIES > 32 )
         #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
     #endif
 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
@@ -49,35 +49,35 @@
 #endif
 
 /* A critical section is exited when the critical section nesting count reaches
-this value. */
-#define portNO_CRITICAL_NESTING         ( ( uint32_t ) 0 )
+ * this value. */
+#define portNO_CRITICAL_NESTING          ( ( uint32_t ) 0 )
 
 /* Tasks are not created with a floating point context, but can be given a
-floating point context after they have been created.  A variable is stored as
-part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
-does not have an FPU context, or any other value if the task does have an FPU
-context. */
-#define portNO_FLOATING_POINT_CONTEXT   ( ( StackType_t ) 0 )
+ * floating point context after they have been created.  A variable is stored as
+ * part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
+ * does not have an FPU context, or any other value if the task does have an FPU
+ * context. */
+#define portNO_FLOATING_POINT_CONTEXT    ( ( StackType_t ) 0 )
 
 /* Constants required to setup the initial task context. */
-#define portINITIAL_SPSR                ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */
-#define portTHUMB_MODE_BIT              ( ( StackType_t ) 0x20 )
-#define portTHUMB_MODE_ADDRESS          ( 0x01UL )
+#define portINITIAL_SPSR                 ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */
+#define portTHUMB_MODE_BIT               ( ( StackType_t ) 0x20 )
+#define portTHUMB_MODE_ADDRESS           ( 0x01UL )
 
 /* Masks all bits in the APSR other than the mode bits. */
-#define portAPSR_MODE_BITS_MASK         ( 0x1F )
+#define portAPSR_MODE_BITS_MASK          ( 0x1F )
 
 /* The value of the mode bits in the APSR when the CPU is executing in user
-mode. */
-#define portAPSR_USER_MODE              ( 0x10 )
+ * mode. */
+#define portAPSR_USER_MODE               ( 0x10 )
 
 /* Let the user override the pre-loading of the initial LR with the address of
-prvTaskExitError() in case it messes up unwinding of the stack in the
-debugger. */
+ * prvTaskExitError() in case it messes up unwinding of the stack in the
+ * debugger. */
 #ifdef configTASK_RETURN_ADDRESS
-    #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
+    #define portTASK_RETURN_ADDRESS    configTASK_RETURN_ADDRESS
 #else
-    #define portTASK_RETURN_ADDRESS prvTaskExitError
+    #define portTASK_RETURN_ADDRESS    prvTaskExitError
 #endif
 
 /*-----------------------------------------------------------*/
@@ -96,39 +96,41 @@ static void prvTaskExitError( void );
 /*-----------------------------------------------------------*/
 
 /* A variable is used to keep track of the critical section nesting.  This
-variable has to be stored as part of the task context and must be initialised to
-a non zero value to ensure interrupts don't inadvertently become unmasked before
-the scheduler starts.  As it is stored as part of the task context it will
-automatically be set to 0 when the first task is started. */
+ * variable has to be stored as part of the task context and must be initialised to
+ * a non zero value to ensure interrupts don't inadvertently become unmasked before
+ * the scheduler starts.  As it is stored as part of the task context it will
+ * automatically be set to 0 when the first task is started. */
 volatile uint32_t ulCriticalNesting = 9999UL;
 
 /* Saved as part of the task context.  If ulPortTaskHasFPUContext is non-zero then
-a floating point context must be saved and restored for the task. */
+ * a floating point context must be saved and restored for the task. */
 volatile uint32_t ulPortTaskHasFPUContext = pdFALSE;
 
 /* Set to 1 to pend a context switch from an ISR. */
 volatile uint32_t ulPortYieldRequired = pdFALSE;
 
 /* Counts the interrupt nesting depth.  A context switch is only performed if
-if the nesting depth is 0. */
+ * if the nesting depth is 0. */
 volatile uint32_t ulPortInterruptNesting = 0UL;
 
 /* Used in the asm file to clear an interrupt. */
-__attribute__(( used )) const uint32_t ulICCEOIR = configEOI_ADDRESS;
+__attribute__( ( used ) ) const uint32_t ulICCEOIR = configEOI_ADDRESS;
 
 /*-----------------------------------------------------------*/
 
 /*
  * See header file for description.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
     /* Setup the initial stack of the task.  The stack is set exactly as
-    expected by the portRESTORE_CONTEXT() macro.
-
-    The fist real value on the stack is the status register, which is set for
-    system mode, with interrupts enabled.  A few NULLs are added first to ensure
-    GDB does not try decoding a non-existent return address. */
+     * expected by the portRESTORE_CONTEXT() macro.
+     *
+     * The fist real value on the stack is the status register, which is set for
+     * system mode, with interrupts enabled.  A few NULLs are added first to ensure
+     * GDB does not try decoding a non-existent return address. */
     *pxTopOfStack = ( StackType_t ) NULL;
     pxTopOfStack--;
     *pxTopOfStack = ( StackType_t ) NULL;
@@ -150,43 +152,43 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
     pxTopOfStack--;
 
     /* Next all the registers other than the stack pointer. */
-    *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;    /* R14 */
+    *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* R14 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
+    *pxTopOfStack = ( StackType_t ) 0x12121212;              /* R12 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
+    *pxTopOfStack = ( StackType_t ) 0x11111111;              /* R11 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
+    *pxTopOfStack = ( StackType_t ) 0x10101010;              /* R10 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
+    *pxTopOfStack = ( StackType_t ) 0x09090909;              /* R9 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
+    *pxTopOfStack = ( StackType_t ) 0x08080808;              /* R8 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
+    *pxTopOfStack = ( StackType_t ) 0x07070707;              /* R7 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
+    *pxTopOfStack = ( StackType_t ) 0x06060606;              /* R6 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
+    *pxTopOfStack = ( StackType_t ) 0x05050505;              /* R5 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
+    *pxTopOfStack = ( StackType_t ) 0x04040404;              /* R4 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
+    *pxTopOfStack = ( StackType_t ) 0x03030303;              /* R3 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
+    *pxTopOfStack = ( StackType_t ) 0x02020202;              /* R2 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
+    *pxTopOfStack = ( StackType_t ) 0x01010101;              /* R1 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+    *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */
     pxTopOfStack--;
 
     /* The task will start with a critical nesting count of 0 as interrupts are
-    enabled. */
+     * enabled. */
     *pxTopOfStack = portNO_CRITICAL_NESTING;
     pxTopOfStack--;
 
     /* The task will start without a floating point context.  A task that uses
-    the floating point hardware must call vPortTaskUsesFPU() before executing
-    any floating point instructions. */
+     * the floating point hardware must call vPortTaskUsesFPU() before executing
+     * any floating point instructions. */
     *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
 
     return pxTopOfStack;
@@ -196,24 +198,28 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
 static void prvTaskExitError( void )
 {
     /* A function that implements a task must not exit or attempt to return to
-    its caller as there is nothing to return to.  If a task wants to exit it
-    should instead call vTaskDelete( NULL ).
-
-    Artificially force an assert() to be triggered if configASSERT() is
-    defined, then stop here so application writers can catch the error. */
+     * its caller as there is nothing to return to.  If a task wants to exit it
+     * should instead call vTaskDelete( NULL ).
+     *
+     * Artificially force an assert() to be triggered if configASSERT() is
+     * defined, then stop here so application writers can catch the error. */
     configASSERT( ulPortInterruptNesting == ~0UL );
     portDISABLE_INTERRUPTS();
-    for( ;; );
+
+    for( ; ; )
+    {
+    }
 }
 /*-----------------------------------------------------------*/
 
 BaseType_t xPortStartScheduler( void )
 {
-uint32_t ulAPSR;
+    uint32_t ulAPSR;
 
     /* Only continue if the CPU is not in User mode.  The CPU must be in a
-    Privileged mode for the scheduler to start. */
-    __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) :: "memory" );
+     * Privileged mode for the scheduler to start. */
+    __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR )::"memory" );
+
     ulAPSR &= portAPSR_MODE_BITS_MASK;
     configASSERT( ulAPSR != portAPSR_USER_MODE );
 
@@ -228,10 +234,10 @@ uint32_t ulAPSR;
     }
 
     /* Will only get here if vTaskStartScheduler() was called with the CPU in
-    a non-privileged mode or the binary point register was not set to its lowest
-    possible value.  prvTaskExitError() is referenced to prevent a compiler
-    warning about it being defined but not referenced in the case that the user
-    defines their own exit address. */
+     * a non-privileged mode or the binary point register was not set to its lowest
+     * possible value.  prvTaskExitError() is referenced to prevent a compiler
+     * warning about it being defined but not referenced in the case that the user
+     * defines their own exit address. */
     ( void ) prvTaskExitError;
     return 0;
 }
@@ -240,7 +246,7 @@ uint32_t ulAPSR;
 void vPortEndScheduler( void )
 {
     /* Not implemented in ports where there is nothing to return to.
-    Artificially force an assert. */
+     * Artificially force an assert. */
     configASSERT( ulCriticalNesting == 1000UL );
 }
 /*-----------------------------------------------------------*/
@@ -249,16 +255,16 @@ void vPortEnterCritical( void )
 {
     portDISABLE_INTERRUPTS();
 
-    /* Now interrupts are disabled ulCriticalNesting can be accessed
-    directly.  Increment ulCriticalNesting to keep a count of how many times
-    portENTER_CRITICAL() has been called. */
+    /* Now that interrupts are disabled, ulCriticalNesting can be accessed
+     * directly.  Increment ulCriticalNesting to keep a count of how many times
+     * portENTER_CRITICAL() has been called. */
     ulCriticalNesting++;
 
     /* This is not the interrupt safe version of the enter critical function so
-    assert() if it is being called from an interrupt context.  Only API
-    functions that end in "FromISR" can be used in an interrupt.  Only assert if
-    the critical nesting count is 1 to protect against recursive calls if the
-    assert function also uses a critical section. */
+     * assert() if it is being called from an interrupt context.  Only API
+     * functions that end in "FromISR" can be used in an interrupt.  Only assert if
+     * the critical nesting count is 1 to protect against recursive calls if the
+     * assert function also uses a critical section. */
     if( ulCriticalNesting == 1 )
     {
         configASSERT( ulPortInterruptNesting == 0 );
@@ -271,15 +277,15 @@ void vPortExitCritical( void )
     if( ulCriticalNesting > portNO_CRITICAL_NESTING )
     {
         /* Decrement the nesting count as the critical section is being
-        exited. */
+         * exited. */
         ulCriticalNesting--;
 
         /* If the nesting level has reached zero then all interrupt
-        priorities must be re-enabled. */
+         * priorities must be re-enabled. */
         if( ulCriticalNesting == portNO_CRITICAL_NESTING )
         {
             /* Critical nesting has reached zero so all interrupt priorities
-            should be unmasked. */
+             * should be unmasked. */
             portENABLE_INTERRUPTS();
         }
     }
@@ -288,7 +294,7 @@ void vPortExitCritical( void )
 
 void FreeRTOS_Tick_Handler( void )
 {
-uint32_t ulInterruptStatus;
+    uint32_t ulInterruptStatus;
 
     ulInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
 
@@ -306,13 +312,13 @@ uint32_t ulInterruptStatus;
 
 void vPortTaskUsesFPU( void )
 {
-uint32_t ulInitialFPSCR = 0;
+    uint32_t ulInitialFPSCR = 0;
 
     /* A task is registering the fact that it needs an FPU context.  Set the
-    FPU flag (which is saved as part of the task context). */
+     * FPU flag (which is saved as part of the task context). */
     ulPortTaskHasFPUContext = pdTRUE;
 
     /* Initialise the floating point status register. */
-    __asm volatile ( "FMXR  FPSCR, %0" :: "r" (ulInitialFPSCR) : "memory" );
+    __asm volatile ( "FMXR  FPSCR, %0" ::"r" ( ulInitialFPSCR ) : "memory" );
 }
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CRx_No_GIC/portmacro.h b/portable/GCC/ARM_CRx_No_GIC/portmacro.h
index e8e541034..d88a0fd05 100644
--- a/portable/GCC/ARM_CRx_No_GIC/portmacro.h
+++ b/portable/GCC/ARM_CRx_No_GIC/portmacro.h
@@ -46,55 +46,56 @@
  */
 
 /* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint32_t
-#define portBASE_TYPE   long
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
-typedef uint32_t TickType_t;
-#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+typedef uint32_t         TickType_t;
+#define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-not need to be guarded with a critical section. */
-#define portTICK_TYPE_IS_ATOMIC 1
+ * not need to be guarded with a critical section. */
+#define portTICK_TYPE_IS_ATOMIC    1
 
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portSTACK_GROWTH            ( -1 )
-#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT          8
+#define portSTACK_GROWTH      ( -1 )
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT    8
 
 /*-----------------------------------------------------------*/
 
 /* Task utilities. */
 
 /* Called at the end of an ISR that can cause a context switch. */
-#define portEND_SWITCHING_ISR( xSwitchRequired )\
-{                                               \
-extern volatile uint32_t ulPortYieldRequired;   \
-                                                \
-    if( xSwitchRequired != pdFALSE )            \
-    {                                           \
-        ulPortYieldRequired = pdTRUE;           \
-    }                                           \
-}
+#define portEND_SWITCHING_ISR( xSwitchRequired )      \
+    {                                                 \
+        extern volatile uint32_t ulPortYieldRequired; \
+                                                      \
+        if( xSwitchRequired != pdFALSE )              \
+        {                                             \
+            ulPortYieldRequired = pdTRUE;             \
+        }                                             \
+    }
 
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
-#define portYIELD() __asm volatile ( "SWI 0     \n"             \
-                                     "ISB         " ::: "memory" );
+#define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
+#define portYIELD()                 \
+    __asm volatile ( "SWI 0     \n" \
+                     "ISB         " ::: "memory" );
 
 
 /*-----------------------------------------------------------
- * Critical section control
- *----------------------------------------------------------*/
+* Critical section control
+*----------------------------------------------------------*/
 
 extern void vPortEnterCritical( void );
 extern void vPortExitCritical( void );
@@ -106,74 +107,76 @@ extern void vPortInstallFreeRTOSVectorTable( void );
 #define portINTERRUPT_ENABLE_BIT    ( 1 << 7 )
 
 /* In the absence of a priority mask register, these functions and macros
-globally enable and disable interrupts. */
-#define portENTER_CRITICAL()        vPortEnterCritical();
-#define portEXIT_CRITICAL()         vPortExitCritical();
-#define portENABLE_INTERRUPTS()     __asm volatile ( "CPSIE i   \n" ::: "memory" );
-#define portDISABLE_INTERRUPTS()    __asm volatile ( "CPSID i   \n"     \
-                                                     "DSB       \n"     \
-                                                     "ISB         " ::: "memory" );
+ * globally enable and disable interrupts. */
+#define portENTER_CRITICAL()       vPortEnterCritical();
+#define portEXIT_CRITICAL()        vPortExitCritical();
+#define portENABLE_INTERRUPTS()    __asm volatile ( "CPSIE i   \n" ::: "memory" );
+#define portDISABLE_INTERRUPTS()    \
+    __asm volatile ( "CPSID i   \n" \
+                     "DSB       \n" \
+                     "ISB         " ::: "memory" );
 
 __attribute__( ( always_inline ) ) static __inline uint32_t portINLINE_SET_INTERRUPT_MASK_FROM_ISR( void )
 {
-volatile uint32_t ulCPSR;
+    volatile uint32_t ulCPSR;
+
+    __asm volatile ( "MRS %0, CPSR" : "=r" ( ulCPSR )::"memory" );
 
-    __asm volatile ( "MRS %0, CPSR" : "=r" (ulCPSR) :: "memory" );
     ulCPSR &= portINTERRUPT_ENABLE_BIT;
     portDISABLE_INTERRUPTS();
     return ulCPSR;
 }
 
-#define portSET_INTERRUPT_MASK_FROM_ISR() portINLINE_SET_INTERRUPT_MASK_FROM_ISR()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)    do { if( x == 0 ) portENABLE_INTERRUPTS(); } while( 0 )
+#define portSET_INTERRUPT_MASK_FROM_ISR()         portINLINE_SET_INTERRUPT_MASK_FROM_ISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    do { if( x == 0 ) portENABLE_INTERRUPTS( ); } while( 0 )
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site.  These are
-not required for this port but included in case common demo code that uses these
-macros is used. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )  void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )    void vFunction( void *pvParameters )
+ * not required for this port but included in case common demo code that uses these
+ * macros is used. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
 /* Tickless idle/low power functionality. */
 #ifndef portSUPPRESS_TICKS_AND_SLEEP
     extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
-    #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+    #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
 #endif
 
 /* Prototype of the FreeRTOS tick handler.  This must be installed as the
-handler for whichever peripheral is used to generate the RTOS tick. */
+ * handler for whichever peripheral is used to generate the RTOS tick. */
 void FreeRTOS_Tick_Handler( void );
 
 /* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
-before any floating point instructions are executed. */
+ * before any floating point instructions are executed. */
 void vPortTaskUsesFPU( void );
-#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
+#define portTASK_USES_FLOATING_POINT()    vPortTaskUsesFPU()
 
-#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
-#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
+#define portLOWEST_INTERRUPT_PRIORITY           ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
+#define portLOWEST_USABLE_INTERRUPT_PRIORITY    ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
 
 /* Architecture specific optimisations. */
 #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-    #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+    #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
 #endif
 
 #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
 
-    /* Store/clear the ready priorities in a bit map. */
-    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+/* Store/clear the ready priorities in a bit map. */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 
-    /*-----------------------------------------------------------*/
+/*-----------------------------------------------------------*/
 
-    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __builtin_clz( uxReadyPriorities ) )
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ( uint32_t ) __builtin_clz( uxReadyPriorities ) )
 
 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 
-#define portNOP() __asm volatile( "NOP" )
-#define portINLINE __inline
+#define portNOP()               __asm volatile ( "NOP" )
+#define portINLINE    __inline
 
-#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+#define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/GCC/ATMega323/port.c b/portable/GCC/ATMega323/port.c
index c27910c1d..6d71a6da3 100644
--- a/portable/GCC/ATMega323/port.c
+++ b/portable/GCC/ATMega323/port.c
@@ -27,13 +27,13 @@
  */
 
 /*
-
-Changes from V2.6.0
-
-    + AVR port - Replaced the inb() and outb() functions with direct memory
-      access.  This allows the port to be built with the 20050414 build of
-      WinAVR.
-*/
+ *
+ * Changes from V2.6.0
+ *
+ + AVR port - Replaced the inb() and outb() functions with direct memory
+ +    access.  This allows the port to be built with the 20050414 build of
+ +    WinAVR.
+ */
 
 #include <stdlib.h>
 #include <avr/interrupt.h>
@@ -42,8 +42,8 @@ Changes from V2.6.0
 #include "task.h"
 
 /*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the AVR port.
- *----------------------------------------------------------*/
+* Implementation of functions defined in portable.h for the AVR port.
+*----------------------------------------------------------*/
 
 /* Start tasks with interrupts enables. */
 #define portFLAGS_INT_ENABLED                   ( ( StackType_t ) 0x80 )
@@ -57,7 +57,7 @@ Changes from V2.6.0
 /*-----------------------------------------------------------*/
 
 /* We require the address of the pxCurrentTCB variable, but don't want to know
-any details of its type. */
+ * any details of its type. */
 typedef void TCB_t;
 extern volatile TCB_t * volatile pxCurrentTCB;
 
@@ -79,98 +79,98 @@ extern volatile TCB_t * volatile pxCurrentTCB;
  * so we need not worry about reading/writing to the stack pointer.
  */
 
-#define portSAVE_CONTEXT()                                  \
-    asm volatile (  "push   r0                      \n\t"   \
-                    "in     r0, __SREG__            \n\t"   \
-                    "cli                            \n\t"   \
-                    "push   r0                      \n\t"   \
-                    "push   r1                      \n\t"   \
-                    "clr    r1                      \n\t"   \
-                    "push   r2                      \n\t"   \
-                    "push   r3                      \n\t"   \
-                    "push   r4                      \n\t"   \
-                    "push   r5                      \n\t"   \
-                    "push   r6                      \n\t"   \
-                    "push   r7                      \n\t"   \
-                    "push   r8                      \n\t"   \
-                    "push   r9                      \n\t"   \
-                    "push   r10                     \n\t"   \
-                    "push   r11                     \n\t"   \
-                    "push   r12                     \n\t"   \
-                    "push   r13                     \n\t"   \
-                    "push   r14                     \n\t"   \
-                    "push   r15                     \n\t"   \
-                    "push   r16                     \n\t"   \
-                    "push   r17                     \n\t"   \
-                    "push   r18                     \n\t"   \
-                    "push   r19                     \n\t"   \
-                    "push   r20                     \n\t"   \
-                    "push   r21                     \n\t"   \
-                    "push   r22                     \n\t"   \
-                    "push   r23                     \n\t"   \
-                    "push   r24                     \n\t"   \
-                    "push   r25                     \n\t"   \
-                    "push   r26                     \n\t"   \
-                    "push   r27                     \n\t"   \
-                    "push   r28                     \n\t"   \
-                    "push   r29                     \n\t"   \
-                    "push   r30                     \n\t"   \
-                    "push   r31                     \n\t"   \
-                    "lds    r26, pxCurrentTCB       \n\t"   \
-                    "lds    r27, pxCurrentTCB + 1   \n\t"   \
-                    "in     r0, 0x3d                \n\t"   \
-                    "st     x+, r0                  \n\t"   \
-                    "in     r0, 0x3e                \n\t"   \
-                    "st     x+, r0                  \n\t"   \
-                );
+#define portSAVE_CONTEXT()                               \
+    asm volatile ( "push   r0                      \n\t" \
+                   "in     r0, __SREG__            \n\t" \
+                   "cli                            \n\t" \
+                   "push   r0                      \n\t" \
+                   "push   r1                      \n\t" \
+                   "clr    r1                      \n\t" \
+                   "push   r2                      \n\t" \
+                   "push   r3                      \n\t" \
+                   "push   r4                      \n\t" \
+                   "push   r5                      \n\t" \
+                   "push   r6                      \n\t" \
+                   "push   r7                      \n\t" \
+                   "push   r8                      \n\t" \
+                   "push   r9                      \n\t" \
+                   "push   r10                     \n\t" \
+                   "push   r11                     \n\t" \
+                   "push   r12                     \n\t" \
+                   "push   r13                     \n\t" \
+                   "push   r14                     \n\t" \
+                   "push   r15                     \n\t" \
+                   "push   r16                     \n\t" \
+                   "push   r17                     \n\t" \
+                   "push   r18                     \n\t" \
+                   "push   r19                     \n\t" \
+                   "push   r20                     \n\t" \
+                   "push   r21                     \n\t" \
+                   "push   r22                     \n\t" \
+                   "push   r23                     \n\t" \
+                   "push   r24                     \n\t" \
+                   "push   r25                     \n\t" \
+                   "push   r26                     \n\t" \
+                   "push   r27                     \n\t" \
+                   "push   r28                     \n\t" \
+                   "push   r29                     \n\t" \
+                   "push   r30                     \n\t" \
+                   "push   r31                     \n\t" \
+                   "lds    r26, pxCurrentTCB       \n\t" \
+                   "lds    r27, pxCurrentTCB + 1   \n\t" \
+                   "in     r0, 0x3d                \n\t" \
+                   "st     x+, r0                  \n\t" \
+                   "in     r0, 0x3e                \n\t" \
+                   "st     x+, r0                  \n\t" \
+                   );
 
 /*
  * Opposite to portSAVE_CONTEXT().  Interrupts will have been disabled during
  * the context save so we can write to the stack pointer.
  */
 
-#define portRESTORE_CONTEXT()                               \
-    asm volatile (  "lds    r26, pxCurrentTCB       \n\t"   \
-                    "lds    r27, pxCurrentTCB + 1   \n\t"   \
-                    "ld     r28, x+                 \n\t"   \
-                    "out    __SP_L__, r28           \n\t"   \
-                    "ld     r29, x+                 \n\t"   \
-                    "out    __SP_H__, r29           \n\t"   \
-                    "pop    r31                     \n\t"   \
-                    "pop    r30                     \n\t"   \
-                    "pop    r29                     \n\t"   \
-                    "pop    r28                     \n\t"   \
-                    "pop    r27                     \n\t"   \
-                    "pop    r26                     \n\t"   \
-                    "pop    r25                     \n\t"   \
-                    "pop    r24                     \n\t"   \
-                    "pop    r23                     \n\t"   \
-                    "pop    r22                     \n\t"   \
-                    "pop    r21                     \n\t"   \
-                    "pop    r20                     \n\t"   \
-                    "pop    r19                     \n\t"   \
-                    "pop    r18                     \n\t"   \
-                    "pop    r17                     \n\t"   \
-                    "pop    r16                     \n\t"   \
-                    "pop    r15                     \n\t"   \
-                    "pop    r14                     \n\t"   \
-                    "pop    r13                     \n\t"   \
-                    "pop    r12                     \n\t"   \
-                    "pop    r11                     \n\t"   \
-                    "pop    r10                     \n\t"   \
-                    "pop    r9                      \n\t"   \
-                    "pop    r8                      \n\t"   \
-                    "pop    r7                      \n\t"   \
-                    "pop    r6                      \n\t"   \
-                    "pop    r5                      \n\t"   \
-                    "pop    r4                      \n\t"   \
-                    "pop    r3                      \n\t"   \
-                    "pop    r2                      \n\t"   \
-                    "pop    r1                      \n\t"   \
-                    "pop    r0                      \n\t"   \
-                    "out    __SREG__, r0            \n\t"   \
-                    "pop    r0                      \n\t"   \
-                );
+#define portRESTORE_CONTEXT()                            \
+    asm volatile ( "lds    r26, pxCurrentTCB       \n\t" \
+                   "lds    r27, pxCurrentTCB + 1   \n\t" \
+                   "ld     r28, x+                 \n\t" \
+                   "out    __SP_L__, r28           \n\t" \
+                   "ld     r29, x+                 \n\t" \
+                   "out    __SP_H__, r29           \n\t" \
+                   "pop    r31                     \n\t" \
+                   "pop    r30                     \n\t" \
+                   "pop    r29                     \n\t" \
+                   "pop    r28                     \n\t" \
+                   "pop    r27                     \n\t" \
+                   "pop    r26                     \n\t" \
+                   "pop    r25                     \n\t" \
+                   "pop    r24                     \n\t" \
+                   "pop    r23                     \n\t" \
+                   "pop    r22                     \n\t" \
+                   "pop    r21                     \n\t" \
+                   "pop    r20                     \n\t" \
+                   "pop    r19                     \n\t" \
+                   "pop    r18                     \n\t" \
+                   "pop    r17                     \n\t" \
+                   "pop    r16                     \n\t" \
+                   "pop    r15                     \n\t" \
+                   "pop    r14                     \n\t" \
+                   "pop    r13                     \n\t" \
+                   "pop    r12                     \n\t" \
+                   "pop    r11                     \n\t" \
+                   "pop    r10                     \n\t" \
+                   "pop    r9                      \n\t" \
+                   "pop    r8                      \n\t" \
+                   "pop    r7                      \n\t" \
+                   "pop    r6                      \n\t" \
+                   "pop    r5                      \n\t" \
+                   "pop    r4                      \n\t" \
+                   "pop    r3                      \n\t" \
+                   "pop    r2                      \n\t" \
+                   "pop    r1                      \n\t" \
+                   "pop    r0                      \n\t" \
+                   "out    __SREG__, r0            \n\t" \
+                   "pop    r0                      \n\t" \
+                   );
 
 /*-----------------------------------------------------------*/
 
@@ -183,12 +183,14 @@ static void prvSetupTimerInterrupt( void );
 /*
  * See header file for description.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
-uint16_t usAddress;
+    uint16_t usAddress;
 
     /* Place a few bytes of known values on the bottom of the stack.
-    This is just useful for debugging. */
+     * This is just useful for debugging. */
 
     *pxTopOfStack = 0x11;
     pxTopOfStack--;
@@ -198,12 +200,12 @@ uint16_t usAddress;
     pxTopOfStack--;
 
     /* Simulate how the stack would look after a call to vPortYield() generated by
-    the compiler. */
+     * the compiler. */
 
     /*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */
 
     /* The start of the task code will be popped off the stack last, so place
-    it on first. */
+     * it on first. */
     usAddress = ( uint16_t ) pxCode;
     *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
     pxTopOfStack--;
@@ -213,61 +215,61 @@ uint16_t usAddress;
     pxTopOfStack--;
 
     /* Next simulate the stack as if after a call to portSAVE_CONTEXT().
-    portSAVE_CONTEXT places the flags on the stack immediately after r0
-    to ensure the interrupts get disabled as soon as possible, and so ensuring
-    the stack use is minimal should a context switch interrupt occur. */
-    *pxTopOfStack = ( StackType_t ) 0x00;   /* R0 */
+     *  portSAVE_CONTEXT places the flags on the stack immediately after r0
+     *  to ensure the interrupts get disabled as soon as possible, and so ensuring
+     *  the stack use is minimal should a context switch interrupt occur. */
+    *pxTopOfStack = ( StackType_t ) 0x00; /* R0 */
     pxTopOfStack--;
     *pxTopOfStack = portFLAGS_INT_ENABLED;
     pxTopOfStack--;
 
 
     /* Now the remaining registers.   The compiler expects R1 to be 0. */
-    *pxTopOfStack = ( StackType_t ) 0x00;   /* R1 */
+    *pxTopOfStack = ( StackType_t ) 0x00; /* R1 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x02;   /* R2 */
+    *pxTopOfStack = ( StackType_t ) 0x02; /* R2 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x03;   /* R3 */
+    *pxTopOfStack = ( StackType_t ) 0x03; /* R3 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x04;   /* R4 */
+    *pxTopOfStack = ( StackType_t ) 0x04; /* R4 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x05;   /* R5 */
+    *pxTopOfStack = ( StackType_t ) 0x05; /* R5 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x06;   /* R6 */
+    *pxTopOfStack = ( StackType_t ) 0x06; /* R6 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x07;   /* R7 */
+    *pxTopOfStack = ( StackType_t ) 0x07; /* R7 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x08;   /* R8 */
+    *pxTopOfStack = ( StackType_t ) 0x08; /* R8 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x09;   /* R9 */
+    *pxTopOfStack = ( StackType_t ) 0x09; /* R9 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x10;   /* R10 */
+    *pxTopOfStack = ( StackType_t ) 0x10; /* R10 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x11;   /* R11 */
+    *pxTopOfStack = ( StackType_t ) 0x11; /* R11 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x12;   /* R12 */
+    *pxTopOfStack = ( StackType_t ) 0x12; /* R12 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x13;   /* R13 */
+    *pxTopOfStack = ( StackType_t ) 0x13; /* R13 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x14;   /* R14 */
+    *pxTopOfStack = ( StackType_t ) 0x14; /* R14 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x15;   /* R15 */
+    *pxTopOfStack = ( StackType_t ) 0x15; /* R15 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x16;   /* R16 */
+    *pxTopOfStack = ( StackType_t ) 0x16; /* R16 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x17;   /* R17 */
+    *pxTopOfStack = ( StackType_t ) 0x17; /* R17 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x18;   /* R18 */
+    *pxTopOfStack = ( StackType_t ) 0x18; /* R18 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x19;   /* R19 */
+    *pxTopOfStack = ( StackType_t ) 0x19; /* R19 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x20;   /* R20 */
+    *pxTopOfStack = ( StackType_t ) 0x20; /* R20 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x21;   /* R21 */
+    *pxTopOfStack = ( StackType_t ) 0x21; /* R21 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x22;   /* R22 */
+    *pxTopOfStack = ( StackType_t ) 0x22; /* R22 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x23;   /* R23 */
+    *pxTopOfStack = ( StackType_t ) 0x23; /* R23 */
     pxTopOfStack--;
 
     /* Place the parameter on the stack in the expected location. */
@@ -279,17 +281,17 @@ uint16_t usAddress;
     *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
     pxTopOfStack--;
 
-    *pxTopOfStack = ( StackType_t ) 0x26;   /* R26 X */
+    *pxTopOfStack = ( StackType_t ) 0x26;  /* R26 X */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x27;   /* R27 */
+    *pxTopOfStack = ( StackType_t ) 0x27;  /* R27 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x28;   /* R28 Y */
+    *pxTopOfStack = ( StackType_t ) 0x28;  /* R28 Y */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x29;   /* R29 */
+    *pxTopOfStack = ( StackType_t ) 0x29;  /* R29 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x30;   /* R30 Z */
+    *pxTopOfStack = ( StackType_t ) 0x30;  /* R30 Z */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x031;  /* R31 */
+    *pxTopOfStack = ( StackType_t ) 0x031; /* R31 */
     pxTopOfStack--;
 
     /*lint +e950 +e611 +e923 */
@@ -307,7 +309,7 @@ BaseType_t xPortStartScheduler( void )
     portRESTORE_CONTEXT();
 
     /* Simulate a function call end as generated by the compiler.  We will now
-    jump to the start of the task the context of which we have just restored. */
+     * jump to the start of the task the context of which we have just restored. */
     asm volatile ( "ret" );
 
     /* Should not get here. */
@@ -318,7 +320,7 @@ BaseType_t xPortStartScheduler( void )
 void vPortEndScheduler( void )
 {
     /* It is unlikely that the AVR port will get stopped.  If required simply
-    disable the tick interrupt here. */
+     * disable the tick interrupt here. */
 }
 /*-----------------------------------------------------------*/
 
@@ -326,7 +328,7 @@ void vPortEndScheduler( void )
  * Manual context switch.  The first thing we do is save the registers so we
  * can use a naked attribute.
  */
-void vPortYield( void ) __attribute__ ( ( naked ) );
+void vPortYield( void ) __attribute__( ( naked ) );
 void vPortYield( void )
 {
     portSAVE_CONTEXT();
@@ -343,14 +345,16 @@ void vPortYield( void )
  * difference from vPortYield() is the tick count is incremented as the
  * call comes from the tick ISR.
  */
-void vPortYieldFromTick( void ) __attribute__ ( ( naked ) );
+void vPortYieldFromTick( void ) __attribute__( ( naked ) );
 void vPortYieldFromTick( void )
 {
     portSAVE_CONTEXT();
+
     if( xTaskIncrementTick() != pdFALSE )
     {
         vTaskSwitchContext();
     }
+
     portRESTORE_CONTEXT();
 
     asm volatile ( "ret" );
@@ -362,11 +366,11 @@ void vPortYieldFromTick( void )
  */
 static void prvSetupTimerInterrupt( void )
 {
-uint32_t ulCompareMatch;
-uint8_t ucHighByte, ucLowByte;
+    uint32_t ulCompareMatch;
+    uint8_t ucHighByte, ucLowByte;
 
     /* Using 16bit timer 1 to generate the tick.  Correct fuses must be
-    selected for the configCPU_CLOCK_HZ clock. */
+     * selected for the configCPU_CLOCK_HZ clock. */
 
     ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
 
@@ -377,7 +381,7 @@ uint8_t ucHighByte, ucLowByte;
     ulCompareMatch -= ( uint32_t ) 1;
 
     /* Setup compare match value for compare match A.  Interrupts are disabled
-    before this is called so we need not worry here. */
+     * before this is called so we need not worry here. */
     ucLowByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff );
     ulCompareMatch >>= 8;
     ucHighByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff );
@@ -389,7 +393,7 @@ uint8_t ucHighByte, ucLowByte;
     TCCR1B = ucLowByte;
 
     /* Enable the interrupt - this is okay as interrupt are currently globally
-    disabled. */
+     * disabled. */
     ucLowByte = TIMSK;
     ucLowByte |= portCOMPARE_MATCH_A_INTERRUPT_ENABLE;
     TIMSK = ucLowByte;
@@ -398,12 +402,12 @@ uint8_t ucHighByte, ucLowByte;
 
 #if configUSE_PREEMPTION == 1
 
-    /*
-     * Tick ISR for preemptive scheduler.  We can use a naked attribute as
-     * the context is saved at the start of vPortYieldFromTick().  The tick
-     * count is incremented after the context is saved.
-     */
-    void TIMER1_COMPA_vect( void ) __attribute__ ( ( signal, naked ) );
+/*
+ * Tick ISR for preemptive scheduler.  We can use a naked attribute as
+ * the context is saved at the start of vPortYieldFromTick().  The tick
+ * count is incremented after the context is saved.
+ */
+    void TIMER1_COMPA_vect( void ) __attribute__( ( signal, naked ) );
     void TIMER1_COMPA_vect( void )
     {
         vPortYieldFromTick();
@@ -411,17 +415,14 @@ uint8_t ucHighByte, ucLowByte;
     }
 #else
 
-    /*
-     * Tick ISR for the cooperative scheduler.  All this does is increment the
-     * tick count.  We don't need to switch context, this can only be done by
-     * manual calls to taskYIELD();
-     */
-    void TIMER1_COMPA_vect( void ) __attribute__ ( ( signal ) );
+/*
+ * Tick ISR for the cooperative scheduler.  All this does is increment the
+ * tick count.  We don't need to switch context, this can only be done by
+ * manual calls to taskYIELD();
+ */
+    void TIMER1_COMPA_vect( void ) __attribute__( ( signal ) );
     void TIMER1_COMPA_vect( void )
     {
         xTaskIncrementTick();
     }
-#endif
-
-
-
+#endif /* if configUSE_PREEMPTION == 1 */
diff --git a/portable/GCC/ATMega323/portmacro.h b/portable/GCC/ATMega323/portmacro.h
index a9f317e6d..275468b4c 100644
--- a/portable/GCC/ATMega323/portmacro.h
+++ b/portable/GCC/ATMega323/portmacro.h
@@ -27,11 +27,11 @@
  */
 
 /*
-Changes from V1.2.3
-
-    + portCPU_CLOSK_HZ definition changed to 8MHz base 10, previously it
-      base 16.
-*/
+ * Changes from V1.2.3
+ *
+ + portCPU_CLOCK_HZ definition changed to 8MHz base 10, previously it
+ +    base 16.
+ */
 
 #ifndef PORTMACRO_H
 #define PORTMACRO_H
@@ -53,58 +53,60 @@ Changes from V1.2.3
  */
 
 /* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       int
-#define portSTACK_TYPE  uint8_t
-#define portBASE_TYPE   char
+#define portCHAR                 char
+#define portFLOAT                float
+#define portDOUBLE               double
+#define portLONG                 long
+#define portSHORT                int
+#define portSTACK_TYPE           uint8_t
+#define portBASE_TYPE            char
 
 #define portPOINTER_SIZE_TYPE    uint16_t
 
-typedef portSTACK_TYPE StackType_t;
-typedef signed char BaseType_t;
-typedef unsigned char UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef signed char      BaseType_t;
+typedef unsigned char    UBaseType_t;
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY ( TickType_t )    ( 0xFFFFFFFFUL )
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) ( 0xFFFFFFFFUL )
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
 /*-----------------------------------------------------------*/
 
 /* Critical section management. */
-#define portENTER_CRITICAL()        asm volatile ( "in      __tmp_reg__, __SREG__" :: );    \
-                                    asm volatile ( "cli" :: );                              \
-                                    asm volatile ( "push    __tmp_reg__" :: )
+#define portENTER_CRITICAL()                            \
+    asm volatile ( "in      __tmp_reg__, __SREG__" ::); \
+    asm volatile ( "cli" ::);                           \
+    asm volatile ( "push    __tmp_reg__" ::)
 
-#define portEXIT_CRITICAL()         asm volatile ( "pop     __tmp_reg__" :: );              \
-                                    asm volatile ( "out     __SREG__, __tmp_reg__" :: )
+#define portEXIT_CRITICAL()                   \
+    asm volatile ( "pop     __tmp_reg__" ::); \
+    asm volatile ( "out     __SREG__, __tmp_reg__" ::)
 
-#define portDISABLE_INTERRUPTS()    asm volatile ( "cli" :: );
-#define portENABLE_INTERRUPTS()     asm volatile ( "sei" :: );
+#define portDISABLE_INTERRUPTS()    asm volatile ( "cli" ::);
+#define portENABLE_INTERRUPTS()     asm volatile ( "sei" ::);
 /*-----------------------------------------------------------*/
 
 /* Architecture specifics. */
-#define portSTACK_GROWTH            ( -1 )
-#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT          1
-#define portNOP()                   asm volatile ( "nop" );
+#define portSTACK_GROWTH      ( -1 )
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT    1
+#define portNOP()    asm volatile ( "nop" );
 /*-----------------------------------------------------------*/
 
 /* Kernel utilities. */
-extern void vPortYield( void ) __attribute__ ( ( naked ) );
-#define portYIELD()                 vPortYield()
+extern void vPortYield( void ) __attribute__( ( naked ) );
+#define portYIELD()    vPortYield()
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/GCC/AVR32_UC3/port.c b/portable/GCC/AVR32_UC3/port.c
index 8d78fe0d6..6e7257304 100644
--- a/portable/GCC/AVR32_UC3/port.c
+++ b/portable/GCC/AVR32_UC3/port.c
@@ -27,6 +27,7 @@
  */
 
 /*This file has been prepared for Doxygen automatic documentation generation.*/
+
 /*! \file *********************************************************************
  *
  * \brief FreeRTOS port source for AVR32 UC3.
@@ -81,20 +82,20 @@
 /* AVR32 UC3 includes. */
 #include <avr32/io.h>
 #include "gpio.h"
-#if( configTICK_USE_TC==1 )
+#if ( configTICK_USE_TC == 1 )
     #include "tc.h"
 #endif
 
 
 /* Constants required to setup the task context. */
-#define portINITIAL_SR            ( ( StackType_t ) 0x00400000 ) /* AVR32 : [M2:M0]=001 I1M=0 I0M=0, GM=0 */
-#define portINSTRUCTION_SIZE      ( ( StackType_t ) 0 )
+#define portINITIAL_SR             ( ( StackType_t ) 0x00400000 ) /* AVR32 : [M2:M0]=001 I1M=0 I0M=0, GM=0 */
+#define portINSTRUCTION_SIZE       ( ( StackType_t ) 0 )
 
 /* Each task maintains its own critical nesting variable. */
-#define portNO_CRITICAL_NESTING   ( ( uint32_t ) 0 )
+#define portNO_CRITICAL_NESTING    ( ( uint32_t ) 0 )
 volatile uint32_t ulCriticalNesting = 9999UL;
 
-#if( configTICK_USE_TC==0 )
+#if ( configTICK_USE_TC == 0 )
     static void prvScheduleNextTick( void );
 #else
     static void prvClearTcInt( void );
@@ -113,7 +114,7 @@ static void prvSetupTimerInterrupt( void );
  * vectors are not compatible with the SCALL management in the current FreeRTOS
  * port. More low-level initializations are besides added here.
  */
-void _init_startup(void)
+void _init_startup( void )
 {
     /* Import the Exception Vector Base Address. */
     extern void _evba;
@@ -121,7 +122,7 @@ void _init_startup(void)
     #if configHEAP_INIT
         extern void __heap_start__;
         extern void __heap_end__;
-        BaseType_t *pxMem;
+        BaseType_t * pxMem;
     #endif
 
     /* Load the Exception Vector Base Address in the corresponding system register. */
@@ -134,13 +135,11 @@ void _init_startup(void)
     INTC_init_interrupts();
 
     #if configHEAP_INIT
-
         /* Initialize the heap used by malloc. */
-        for( pxMem = &__heap_start__; pxMem < ( BaseType_t * )&__heap_end__; )
+        for( pxMem = &__heap_start__; pxMem < ( BaseType_t * ) &__heap_end__; )
         {
             *pxMem++ = 0xA5A5A5A5;
         }
-
     #endif
 
     /* Give the used CPU clock frequency to Newlib, so it can work properly. */
@@ -158,10 +157,10 @@ void _init_startup(void)
         /* Initialize the USART used for the debug trace with the configured parameters. */
         set_usart_base( ( void * ) configDBG_USART );
         gpio_enable_module( DBG_USART_GPIO_MAP,
-                            sizeof( DBG_USART_GPIO_MAP ) / sizeof( DBG_USART_GPIO_MAP[0] ) );
+                            sizeof( DBG_USART_GPIO_MAP ) / sizeof( DBG_USART_GPIO_MAP[ 0 ] ) );
         usart_init( configDBG_USART_BAUDRATE );
     }
-    #endif
+    #endif /* if configDBG */
 }
 /*-----------------------------------------------------------*/
 
@@ -184,7 +183,7 @@ void _init_startup(void)
  * safe section as memory allocation management uses global data.
  * See the aforementioned details.
  */
-void __malloc_lock(struct _reent *ptr)
+void __malloc_lock( struct _reent * ptr )
 {
     vTaskSuspendAll();
 }
@@ -194,16 +193,17 @@ void __malloc_lock(struct _reent *ptr)
  * a safe section as memory allocation management uses global data.
  * See the aforementioned details.
  */
-void __malloc_unlock(struct _reent *ptr)
+void __malloc_unlock( struct _reent * ptr )
 {
     xTaskResumeAll();
 }
 /*-----------------------------------------------------------*/
 
 /* Added as there is no such function in FreeRTOS. */
-void *pvPortRealloc( void *pv, size_t xWantedSize )
+void * pvPortRealloc( void * pv,
+                      size_t xWantedSize )
 {
-void *pvReturn;
+    void * pvReturn;
 
     vTaskSuspendAll();
     {
@@ -216,27 +216,29 @@ void *pvReturn;
 /*-----------------------------------------------------------*/
 
 /* The cooperative scheduler requires a normal IRQ service routine to
-simply increment the system tick. */
+ * simply increment the system tick. */
+
 /* The preemptive scheduler is defined as "naked" as the full context is saved
-on entry as part of the context switch. */
-__attribute__((__naked__)) static void vTick( void )
+ * on entry as part of the context switch. */
+__attribute__( ( __naked__ ) ) static void vTick( void )
 {
     /* Save the context of the interrupted task. */
     portSAVE_CONTEXT_OS_INT();
 
-    #if( configTICK_USE_TC==1 )
+    #if ( configTICK_USE_TC == 1 )
         /* Clear the interrupt flag. */
         prvClearTcInt();
     #else
+
         /* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)
-        clock cycles from now. */
+         * clock cycles from now. */
         prvScheduleNextTick();
     #endif
 
     /* Because FreeRTOS is not supposed to run with nested interrupts, put all OS
-    calls in a critical section . */
+     * calls in a critical section . */
     portENTER_CRITICAL();
-        xTaskIncrementTick();
+    xTaskIncrementTick();
     portEXIT_CRITICAL();
 
     /* Restore the context of the "elected task". */
@@ -244,7 +246,7 @@ __attribute__((__naked__)) static void vTick( void )
 }
 /*-----------------------------------------------------------*/
 
-__attribute__((__naked__)) void SCALLYield( void )
+__attribute__( ( __naked__ ) ) void SCALLYield( void )
 {
     /* Save the context of the interrupted task. */
     portSAVE_CONTEXT_SCALL();
@@ -254,26 +256,27 @@ __attribute__((__naked__)) void SCALLYield( void )
 /*-----------------------------------------------------------*/
 
 /* The code generated by the GCC compiler uses the stack in different ways at
-different optimisation levels.  The interrupt flags can therefore not always
-be saved to the stack.  Instead the critical section nesting level is stored
-in a variable, which is then saved as part of the stack context. */
-__attribute__((__noinline__)) void vPortEnterCritical( void )
+ * different optimisation levels.  The interrupt flags can therefore not always
+ * be saved to the stack.  Instead the critical section nesting level is stored
+ * in a variable, which is then saved as part of the stack context. */
+__attribute__( ( __noinline__ ) ) void vPortEnterCritical( void )
 {
     /* Disable interrupts */
     portDISABLE_INTERRUPTS();
 
-    /* Now interrupts are disabled ulCriticalNesting can be accessed
-     directly.  Increment ulCriticalNesting to keep a count of how many times
-     portENTER_CRITICAL() has been called. */
+    /* Now that interrupts are disabled, ulCriticalNesting can be accessed
+     * directly.  Increment ulCriticalNesting to keep a count of how many times
+     * portENTER_CRITICAL() has been called. */
     ulCriticalNesting++;
 }
 /*-----------------------------------------------------------*/
 
-__attribute__((__noinline__)) void vPortExitCritical( void )
+__attribute__( ( __noinline__ ) ) void vPortExitCritical( void )
 {
-    if(ulCriticalNesting > portNO_CRITICAL_NESTING)
+    if( ulCriticalNesting > portNO_CRITICAL_NESTING )
     {
         ulCriticalNesting--;
+
         if( ulCriticalNesting == portNO_CRITICAL_NESTING )
         {
             /* Enable all interrupt/exception. */
@@ -289,30 +292,32 @@ __attribute__((__noinline__)) void vPortExitCritical( void )
  *
  * See header file for description.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
     /* Setup the initial stack of the task.  The stack is set exactly as
-    expected by the portRESTORE_CONTEXT() macro. */
+     * expected by the portRESTORE_CONTEXT() macro. */
 
     /* When the task starts, it will expect to find the function parameter in R12. */
     pxTopOfStack--;
-    *pxTopOfStack-- = ( StackType_t ) 0x08080808;                   /* R8 */
-    *pxTopOfStack-- = ( StackType_t ) 0x09090909;                   /* R9 */
-    *pxTopOfStack-- = ( StackType_t ) 0x0A0A0A0A;                   /* R10 */
-    *pxTopOfStack-- = ( StackType_t ) 0x0B0B0B0B;                   /* R11 */
-    *pxTopOfStack-- = ( StackType_t ) pvParameters;                 /* R12 */
-    *pxTopOfStack-- = ( StackType_t ) 0xDEADBEEF;                   /* R14/LR */
+    *pxTopOfStack-- = ( StackType_t ) 0x08080808;                    /* R8 */
+    *pxTopOfStack-- = ( StackType_t ) 0x09090909;                    /* R9 */
+    *pxTopOfStack-- = ( StackType_t ) 0x0A0A0A0A;                    /* R10 */
+    *pxTopOfStack-- = ( StackType_t ) 0x0B0B0B0B;                    /* R11 */
+    *pxTopOfStack-- = ( StackType_t ) pvParameters;                  /* R12 */
+    *pxTopOfStack-- = ( StackType_t ) 0xDEADBEEF;                    /* R14/LR */
     *pxTopOfStack-- = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; /* R15/PC */
-    *pxTopOfStack-- = ( StackType_t ) portINITIAL_SR;               /* SR */
-    *pxTopOfStack-- = ( StackType_t ) 0xFF0000FF;                   /* R0 */
-    *pxTopOfStack-- = ( StackType_t ) 0x01010101;                   /* R1 */
-    *pxTopOfStack-- = ( StackType_t ) 0x02020202;                   /* R2 */
-    *pxTopOfStack-- = ( StackType_t ) 0x03030303;                   /* R3 */
-    *pxTopOfStack-- = ( StackType_t ) 0x04040404;                   /* R4 */
-    *pxTopOfStack-- = ( StackType_t ) 0x05050505;                   /* R5 */
-    *pxTopOfStack-- = ( StackType_t ) 0x06060606;                   /* R6 */
-    *pxTopOfStack-- = ( StackType_t ) 0x07070707;                   /* R7 */
-    *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_NESTING;            /* ulCriticalNesting */
+    *pxTopOfStack-- = ( StackType_t ) portINITIAL_SR;                /* SR */
+    *pxTopOfStack-- = ( StackType_t ) 0xFF0000FF;                    /* R0 */
+    *pxTopOfStack-- = ( StackType_t ) 0x01010101;                    /* R1 */
+    *pxTopOfStack-- = ( StackType_t ) 0x02020202;                    /* R2 */
+    *pxTopOfStack-- = ( StackType_t ) 0x03030303;                    /* R3 */
+    *pxTopOfStack-- = ( StackType_t ) 0x04040404;                    /* R4 */
+    *pxTopOfStack-- = ( StackType_t ) 0x05050505;                    /* R5 */
+    *pxTopOfStack-- = ( StackType_t ) 0x06060606;                    /* R6 */
+    *pxTopOfStack-- = ( StackType_t ) 0x07070707;                    /* R7 */
+    *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_NESTING;         /* ulCriticalNesting */
 
     return pxTopOfStack;
 }
@@ -321,7 +326,7 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
 BaseType_t xPortStartScheduler( void )
 {
     /* Start the timer that generates the tick ISR.  Interrupts are disabled
-    here already. */
+     * here already. */
     prvSetupTimerInterrupt();
 
     /* Start the first task. */
@@ -335,130 +340,134 @@ BaseType_t xPortStartScheduler( void )
 void vPortEndScheduler( void )
 {
     /* It is unlikely that the AVR32 port will require this function as there
-    is nothing to return to.  */
+     * is nothing to return to.  */
 }
 /*-----------------------------------------------------------*/
 
 /* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)
-clock cycles from now. */
-#if( configTICK_USE_TC==0 )
-    static void prvScheduleFirstTick(void)
+ * clock cycles from now. */
+#if ( configTICK_USE_TC == 0 )
+    static void prvScheduleFirstTick( void )
     {
         uint32_t lCycles;
 
-        lCycles = Get_system_register(AVR32_COUNT);
-        lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
-        // If lCycles ends up to be 0, make it 1 so that the COMPARE and exception
-        // generation feature does not get disabled.
-        if(0 == lCycles)
+        lCycles = Get_system_register( AVR32_COUNT );
+        lCycles += ( configCPU_CLOCK_HZ / configTICK_RATE_HZ );
+
+        /* If lCycles ends up to be 0, make it 1 so that the COMPARE and exception */
+        /* generation feature does not get disabled. */
+        if( 0 == lCycles )
         {
             lCycles++;
         }
-        Set_system_register(AVR32_COMPARE, lCycles);
+
+        Set_system_register( AVR32_COMPARE, lCycles );
     }
 
-    __attribute__((__noinline__)) static void prvScheduleNextTick(void)
+    __attribute__( ( __noinline__ ) ) static void prvScheduleNextTick( void )
     {
         uint32_t lCycles, lCount;
 
-        lCycles = Get_system_register(AVR32_COMPARE);
-        lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
-        // If lCycles ends up to be 0, make it 1 so that the COMPARE and exception
-        // generation feature does not get disabled.
-        if(0 == lCycles)
+        lCycles = Get_system_register( AVR32_COMPARE );
+        lCycles += ( configCPU_CLOCK_HZ / configTICK_RATE_HZ );
+
+        /* If lCycles ends up to be 0, make it 1 so that the COMPARE and exception */
+        /* generation feature does not get disabled. */
+        if( 0 == lCycles )
         {
             lCycles++;
         }
-        lCount = Get_system_register(AVR32_COUNT);
+
+        lCount = Get_system_register( AVR32_COUNT );
+
         if( lCycles < lCount )
-        {       // We missed a tick, recover for the next.
-            lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
+        { /* We missed a tick, recover for the next. */
+            lCycles += ( configCPU_CLOCK_HZ / configTICK_RATE_HZ );
         }
-        Set_system_register(AVR32_COMPARE, lCycles);
+
+        Set_system_register( AVR32_COMPARE, lCycles );
     }
-#else
-    __attribute__((__noinline__)) static void prvClearTcInt(void)
+#else /* if ( configTICK_USE_TC == 0 ) */
+    __attribute__( ( __noinline__ ) ) static void prvClearTcInt( void )
     {
-        AVR32_TC.channel[configTICK_TC_CHANNEL].sr;
+        AVR32_TC.channel[ configTICK_TC_CHANNEL ].sr;
     }
-#endif
+#endif /* if ( configTICK_USE_TC == 0 ) */
 /*-----------------------------------------------------------*/
 
 /* Setup the timer to generate the tick interrupts. */
-static void prvSetupTimerInterrupt(void)
+static void prvSetupTimerInterrupt( void )
 {
-#if( configTICK_USE_TC==1 )
+    #if ( configTICK_USE_TC == 1 )
+        volatile avr32_tc_t * tc = &AVR32_TC;
 
-    volatile avr32_tc_t *tc = &AVR32_TC;
+        /* Options for waveform genration. */
+        tc_waveform_opt_t waveform_opt =
+        {
+            .channel = configTICK_TC_CHANNEL,              /* Channel selection. */
 
-    // Options for waveform genration.
-    tc_waveform_opt_t waveform_opt =
-    {
-    .channel  = configTICK_TC_CHANNEL,             /* Channel selection. */
+            .bswtrg  = TC_EVT_EFFECT_NOOP,                 /* Software trigger effect on TIOB. */
+            .beevt   = TC_EVT_EFFECT_NOOP,                 /* External event effect on TIOB. */
+            .bcpc    = TC_EVT_EFFECT_NOOP,                 /* RC compare effect on TIOB. */
+            .bcpb    = TC_EVT_EFFECT_NOOP,                 /* RB compare effect on TIOB. */
 
-    .bswtrg   = TC_EVT_EFFECT_NOOP,                /* Software trigger effect on TIOB. */
-    .beevt    = TC_EVT_EFFECT_NOOP,                /* External event effect on TIOB. */
-    .bcpc     = TC_EVT_EFFECT_NOOP,                /* RC compare effect on TIOB. */
-    .bcpb     = TC_EVT_EFFECT_NOOP,                /* RB compare effect on TIOB. */
+            .aswtrg  = TC_EVT_EFFECT_NOOP,                 /* Software trigger effect on TIOA. */
+            .aeevt   = TC_EVT_EFFECT_NOOP,                 /* External event effect on TIOA. */
+            .acpc    = TC_EVT_EFFECT_NOOP,                 /* RC compare effect on TIOA: toggle. */
+            .acpa    = TC_EVT_EFFECT_NOOP,                 /* RA compare effect on TIOA: toggle (other possibilities are none, set and clear). */
 
-    .aswtrg   = TC_EVT_EFFECT_NOOP,                /* Software trigger effect on TIOA. */
-    .aeevt    = TC_EVT_EFFECT_NOOP,                /* External event effect on TIOA. */
-    .acpc     = TC_EVT_EFFECT_NOOP,                /* RC compare effect on TIOA: toggle. */
-    .acpa     = TC_EVT_EFFECT_NOOP,                /* RA compare effect on TIOA: toggle (other possibilities are none, set and clear). */
+            .wavsel  = TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER, /* Waveform selection: Up mode without automatic trigger on RC compare. */
+            .enetrg  = FALSE,                              /* External event trigger enable. */
+            .eevt    = 0,                                  /* External event selection. */
+            .eevtedg = TC_SEL_NO_EDGE,                     /* External event edge selection. */
+            .cpcdis  = FALSE,                              /* Counter disable when RC compare. */
+            .cpcstop = FALSE,                              /* Counter clock stopped with RC compare. */
 
-    .wavsel   = TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER,/* Waveform selection: Up mode without automatic trigger on RC compare. */
-    .enetrg   = FALSE,                             /* External event trigger enable. */
-    .eevt     = 0,                                 /* External event selection. */
-    .eevtedg  = TC_SEL_NO_EDGE,                    /* External event edge selection. */
-    .cpcdis   = FALSE,                             /* Counter disable when RC compare. */
-    .cpcstop  = FALSE,                             /* Counter clock stopped with RC compare. */
+            .burst   = FALSE,                              /* Burst signal selection. */
+            .clki    = FALSE,                              /* Clock inversion. */
+            .tcclks  = TC_CLOCK_SOURCE_TC2                 /* Internal source clock 2. */
+        };
 
-    .burst    = FALSE,                             /* Burst signal selection. */
-    .clki     = FALSE,                             /* Clock inversion. */
-    .tcclks   = TC_CLOCK_SOURCE_TC2                /* Internal source clock 2. */
-    };
-
-    tc_interrupt_t tc_interrupt =
-    {
-        .etrgs=0,
-        .ldrbs=0,
-        .ldras=0,
-        .cpcs =1,
-        .cpbs =0,
-        .cpas =0,
-        .lovrs=0,
-        .covfs=0,
-    };
-
-#endif
+        tc_interrupt_t tc_interrupt =
+        {
+            .etrgs = 0,
+            .ldrbs = 0,
+            .ldras = 0,
+            .cpcs  = 1,
+            .cpbs  = 0,
+            .cpas  = 0,
+            .lovrs = 0,
+            .covfs = 0,
+        };
+    #endif /* if ( configTICK_USE_TC == 1 ) */
 
     /* Disable all interrupt/exception. */
     portDISABLE_INTERRUPTS();
 
     /* Register the compare interrupt handler to the interrupt controller and
-    enable the compare interrupt. */
+     * enable the compare interrupt. */
 
-    #if( configTICK_USE_TC==1 )
+    #if ( configTICK_USE_TC == 1 )
     {
-        INTC_register_interrupt(&vTick, configTICK_TC_IRQ, INT0);
+        INTC_register_interrupt( &vTick, configTICK_TC_IRQ, INT0 );
 
         /* Initialize the timer/counter. */
-        tc_init_waveform(tc, &waveform_opt);
+        tc_init_waveform( tc, &waveform_opt );
 
         /* Set the compare triggers.
-        Remember TC counter is 16-bits, so counting second is not possible!
-        That's why we configure it to count ms. */
-        tc_write_rc( tc, configTICK_TC_CHANNEL, ( configPBA_CLOCK_HZ / 4) / configTICK_RATE_HZ );
+         * Remember TC counter is 16-bits, so counting second is not possible!
+         * That's why we configure it to count ms. */
+        tc_write_rc( tc, configTICK_TC_CHANNEL, ( configPBA_CLOCK_HZ / 4 ) / configTICK_RATE_HZ );
 
         tc_configure_interrupts( tc, configTICK_TC_CHANNEL, &tc_interrupt );
 
         /* Start the timer/counter. */
-        tc_start(tc, configTICK_TC_CHANNEL);
+        tc_start( tc, configTICK_TC_CHANNEL );
     }
-    #else
+    #else /* if ( configTICK_USE_TC == 1 ) */
     {
-        INTC_register_interrupt(&vTick, AVR32_CORE_COMPARE_IRQ, INT0);
+        INTC_register_interrupt( &vTick, AVR32_CORE_COMPARE_IRQ, INT0 );
         prvScheduleFirstTick();
     }
-    #endif
+    #endif /* if ( configTICK_USE_TC == 1 ) */
 }
diff --git a/portable/GCC/AVR32_UC3/portmacro.h b/portable/GCC/AVR32_UC3/portmacro.h
index ebf501091..521c46397 100644
--- a/portable/GCC/AVR32_UC3/portmacro.h
+++ b/portable/GCC/AVR32_UC3/portmacro.h
@@ -27,6 +27,7 @@
  */
 
 /*This file has been prepared for Doxygen automatic documentation generation.*/
+
 /*! \file *********************************************************************
  *
  * \brief FreeRTOS port source for AVR32 UC3.
@@ -93,30 +94,30 @@
 
 
 /* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint32_t
-#define portBASE_TYPE   long
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
-#define TASK_DELAY_MS(x)   ( (x)        /portTICK_PERIOD_MS )
-#define TASK_DELAY_S(x)    ( (x)*1000   /portTICK_PERIOD_MS )
-#define TASK_DELAY_MIN(x)  ( (x)*60*1000/portTICK_PERIOD_MS )
+#define TASK_DELAY_MS( x )     ( ( x ) / portTICK_PERIOD_MS )
+#define TASK_DELAY_S( x )      ( ( x ) * 1000 / portTICK_PERIOD_MS )
+#define TASK_DELAY_MIN( x )    ( ( x ) * 60 * 1000 / portTICK_PERIOD_MS )
 
-#define configTICK_TC_IRQ             ATPASTE2(AVR32_TC_IRQ, configTICK_TC_CHANNEL)
+#define configTICK_TC_IRQ    ATPASTE2( AVR32_TC_IRQ, configTICK_TC_CHANNEL )
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t   TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY ( TickType_t )    ( 0xFFFFFFFFUL )
+    typedef uint32_t   TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) ( 0xFFFFFFFFUL )
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
@@ -124,23 +125,23 @@ typedef unsigned long UBaseType_t;
 
 /* Architecture specifics. */
 #define portSTACK_GROWTH      ( -1 )
-#define portTICK_PERIOD_MS      ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
 #define portBYTE_ALIGNMENT    4
-#define portNOP()             {__asm__ __volatile__ ("nop");}
+#define portNOP()    { __asm__ __volatile__ ( "nop" ); }
 /*-----------------------------------------------------------*/
 
 
 /*-----------------------------------------------------------*/
 
 /* INTC-specific. */
-#define DISABLE_ALL_EXCEPTIONS()    Disable_global_exception()
-#define ENABLE_ALL_EXCEPTIONS()     Enable_global_exception()
+#define DISABLE_ALL_EXCEPTIONS()        Disable_global_exception()
+#define ENABLE_ALL_EXCEPTIONS()         Enable_global_exception()
 
-#define DISABLE_ALL_INTERRUPTS()    Disable_global_interrupt()
-#define ENABLE_ALL_INTERRUPTS()     Enable_global_interrupt()
+#define DISABLE_ALL_INTERRUPTS()        Disable_global_interrupt()
+#define ENABLE_ALL_INTERRUPTS()         Enable_global_interrupt()
 
-#define DISABLE_INT_LEVEL(int_lev)  Disable_interrupt_level(int_lev)
-#define ENABLE_INT_LEVEL(int_lev)   Enable_interrupt_level(int_lev)
+#define DISABLE_INT_LEVEL( int_lev )    Disable_interrupt_level( int_lev )
+#define ENABLE_INT_LEVEL( int_lev )     Enable_interrupt_level( int_lev )
 
 
 /*
@@ -157,31 +158,32 @@ typedef unsigned long UBaseType_t;
  * which is interrupt-unsafe with the current __malloc_lock and __malloc_unlock.
  */
 #if configDBG
-#define portDBG_TRACE(...) \
-{\
-  fputs(__FILE__ ":" ASTRINGZ(__LINE__) ": ", stdout);\
-  printf(__VA_ARGS__);\
-  fputs("\r\n", stdout);\
-}
+    #define portDBG_TRACE( ... )                                 \
+    {                                                            \
+        fputs( __FILE__ ":" ASTRINGZ( __LINE__ ) ": ", stdout ); \
+        printf( __VA_ARGS__ );                                   \
+        fputs( "\r\n", stdout );                                 \
+    }
 #else
-#define portDBG_TRACE(...)
+    #define portDBG_TRACE( ... )
 #endif
 
 
 /* Critical section management. */
-#define portDISABLE_INTERRUPTS()  DISABLE_ALL_INTERRUPTS()
-#define portENABLE_INTERRUPTS()   ENABLE_ALL_INTERRUPTS()
+#define portDISABLE_INTERRUPTS()    DISABLE_ALL_INTERRUPTS()
+#define portENABLE_INTERRUPTS()     ENABLE_ALL_INTERRUPTS()
 
 
 extern void vPortEnterCritical( void );
 extern void vPortExitCritical( void );
 
-#define portENTER_CRITICAL()      vPortEnterCritical();
-#define portEXIT_CRITICAL()       vPortExitCritical();
+#define portENTER_CRITICAL()    vPortEnterCritical();
+#define portEXIT_CRITICAL()     vPortExitCritical();
 
 
 /* Added as there is no such function in FreeRTOS. */
-extern void *pvPortRealloc( void *pv, size_t xSize );
+extern void * pvPortRealloc( void * pv,
+                             size_t xSize );
 /*-----------------------------------------------------------*/
 
 
@@ -190,44 +192,44 @@ extern void *pvPortRealloc( void *pv, size_t xSize );
 /*
  * Restore Context for cases other than INTi.
  */
-#define portRESTORE_CONTEXT()                                                           \
-{                                                                                       \
-  extern volatile uint32_t ulCriticalNesting;                                   \
-  extern volatile void *volatile pxCurrentTCB;                                          \
-                                                                                        \
-  __asm__ __volatile__ (                                                                \
-    /* Set SP to point to new stack */                                                  \
-    "mov     r8, LO(%[pxCurrentTCB])                                                    \n\t"\
-    "orh     r8, HI(%[pxCurrentTCB])                                                    \n\t"\
-    "ld.w    r0, r8[0]                                                                  \n\t"\
-    "ld.w    sp, r0[0]                                                                  \n\t"\
-                                                                                        \
-    /* Restore ulCriticalNesting variable */                                            \
-    "ld.w    r0, sp++                                                                   \n\t"\
-    "mov     r8, LO(%[ulCriticalNesting])                                               \n\t"\
-    "orh     r8, HI(%[ulCriticalNesting])                                               \n\t"\
-    "st.w    r8[0], r0                                                                  \n\t"\
-                                                                                        \
-    /* Restore R0..R7 */                                                                \
-    "ldm     sp++, r0-r7                                                                \n\t"\
-    /* R0-R7 should not be used below this line */                                      \
-    /* Skip PC and SR (will do it at the end) */                                        \
-    "sub     sp, -2*4                                                                   \n\t"\
-    /* Restore R8..R12 and LR */                                                        \
-    "ldm     sp++, r8-r12, lr                                                           \n\t"\
-    /* Restore SR */                                                                    \
-    "ld.w    r0, sp[-8*4]\n\t" /* R0 is modified, is restored later. */                 \
-    "mtsr    %[SR], r0                                                                  \n\t"\
-    /* Restore r0 */                                                                    \
-    "ld.w    r0, sp[-9*4]                                                               \n\t"\
-    /* Restore PC */                                                                    \
-    "ld.w    pc, sp[-7*4]" /* Get PC from stack - PC is the 7th register saved */       \
-    :                                                                                   \
-    : [ulCriticalNesting] "i" (&ulCriticalNesting),                                     \
-      [pxCurrentTCB] "i" (&pxCurrentTCB),                                               \
-      [SR] "i" (AVR32_SR)                                                               \
-  );                                                                                    \
-}
+#define portRESTORE_CONTEXT()                                                                         \
+    {                                                                                                 \
+        extern volatile uint32_t ulCriticalNesting;                                                   \
+        extern volatile void * volatile pxCurrentTCB;                                                 \
+                                                                                                      \
+        __asm__ __volatile__ (                                                                        \
+            /* Set SP to point to new stack */                                                        \
+            "mov     r8, LO(%[pxCurrentTCB])                                                    \n\t" \
+            "orh     r8, HI(%[pxCurrentTCB])                                                    \n\t" \
+            "ld.w    r0, r8[0]                                                                  \n\t" \
+            "ld.w    sp, r0[0]                                                                  \n\t" \
+                                                                                                      \
+            /* Restore ulCriticalNesting variable */                                                  \
+            "ld.w    r0, sp++                                                                   \n\t" \
+            "mov     r8, LO(%[ulCriticalNesting])                                               \n\t" \
+            "orh     r8, HI(%[ulCriticalNesting])                                               \n\t" \
+            "st.w    r8[0], r0                                                                  \n\t" \
+                                                                                                      \
+            /* Restore R0..R7 */                                                                      \
+            "ldm     sp++, r0-r7                                                                \n\t" \
+            /* R0-R7 should not be used below this line */                                            \
+            /* Skip PC and SR (will do it at the end) */                                              \
+            "sub     sp, -2*4                                                                   \n\t" \
+            /* Restore R8..R12 and LR */                                                              \
+            "ldm     sp++, r8-r12, lr                                                           \n\t" \
+            /* Restore SR */                                                                          \
+            "ld.w    r0, sp[-8*4]\n\t" /* R0 is modified, is restored later. */                       \
+            "mtsr    %[SR], r0                                                                  \n\t" \
+            /* Restore r0 */                                                                          \
+            "ld.w    r0, sp[-9*4]                                                               \n\t" \
+            /* Restore PC */                                                                          \
+            "ld.w    pc, sp[-7*4]" /* Get PC from stack - PC is the 7th register saved */             \
+            :                                                                                         \
+            :[ ulCriticalNesting ] "i" ( &ulCriticalNesting ),                                        \
+            [ pxCurrentTCB ] "i" ( &pxCurrentTCB ),                                                   \
+            [ SR ] "i" ( AVR32_SR )                                                                   \
+            );                                                                                        \
+    }
 
 
 /*
@@ -238,25 +240,25 @@ extern void *pvPortRealloc( void *pv, size_t xSize );
  * are not the same between INT0..3 exceptions and the scall exception.
  */
 
-// Task context stack layout:
-  // R8  (*)
-  // R9  (*)
-  // R10 (*)
-  // R11 (*)
-  // R12 (*)
-  // R14/LR (*)
-  // R15/PC (*)
-  // SR (*)
-  // R0
-  // R1
-  // R2
-  // R3
-  // R4
-  // R5
-  // R6
-  // R7
-  // ulCriticalNesting
-// (*) automatically done for INT0..INT3, but not for SCALL
+/* Task context stack layout: */
+/* R8  (*) */
+/* R9  (*) */
+/* R10 (*) */
+/* R11 (*) */
+/* R12 (*) */
+/* R14/LR (*) */
+/* R15/PC (*) */
+/* SR (*) */
+/* R0 */
+/* R1 */
+/* R2 */
+/* R3 */
+/* R4 */
+/* R5 */
+/* R6 */
+/* R7 */
+/* ulCriticalNesting */
+/* (*) automatically done for INT0..INT3, but not for SCALL */
 
 /*
  * The ISR used for the scheduler tick depends on whether the cooperative or
@@ -267,145 +269,145 @@ extern void *pvPortRealloc( void *pv, size_t xSize );
 /*
  * portSAVE_CONTEXT_OS_INT() for OS Tick exception.
  */
-#define portSAVE_CONTEXT_OS_INT()                                                       \
-{                                                                                       \
-  /* Save R0..R7 */                                                                     \
-  __asm__ __volatile__ ("stm     --sp, r0-r7");                                         \
-                                                                                        \
-  /* With the cooperative scheduler, as there is no context switch by interrupt, */     \
-  /* there is also no context save. */                                                  \
-}
+    #define portSAVE_CONTEXT_OS_INT()                                                     \
+    {                                                                                     \
+        /* Save R0..R7 */                                                                 \
+        __asm__ __volatile__ ( "stm     --sp, r0-r7" );                                   \
+                                                                                          \
+        /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
+        /* there is also no context save. */                                              \
+    }
 
 /*
  * portRESTORE_CONTEXT_OS_INT() for Tick exception.
  */
-#define portRESTORE_CONTEXT_OS_INT()                                                    \
-{                                                                                       \
-  __asm__ __volatile__ (                                                                \
-    /* Restore R0..R7 */                                                                \
-    "ldm     sp++, r0-r7\n\t"                                                           \
-                                                                                        \
-    /* With the cooperative scheduler, as there is no context switch by interrupt, */   \
-    /* there is also no context restore. */                                             \
-    "rete"                                                                              \
-  );                                                                                    \
-}
+    #define portRESTORE_CONTEXT_OS_INT()                                                      \
+    {                                                                                         \
+        __asm__ __volatile__ (                                                                \
+            /* Restore R0..R7 */                                                              \
+            "ldm     sp++, r0-r7\n\t"                                                         \
+                                                                                              \
+            /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
+            /* there is also no context restore. */                                           \
+            "rete"                                                                            \
+            );                                                                                \
+    }
 
-#else
+#else /* if configUSE_PREEMPTION == 0 */
 
 /*
  * portSAVE_CONTEXT_OS_INT() for OS Tick exception.
  */
-#define portSAVE_CONTEXT_OS_INT()                                                                   \
-{                                                                                                   \
-  extern volatile uint32_t ulCriticalNesting;                                               \
-  extern volatile void *volatile pxCurrentTCB;                                                      \
-                                                                                                    \
-  /* When we come here */                                                                           \
-  /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */                    \
-                                                                                                    \
-  __asm__ __volatile__ (                                                                            \
-    /* Save R0..R7 */                                                                               \
-    "stm     --sp, r0-r7                                                                            \n\t"\
-                                                                                                    \
-    /* Save ulCriticalNesting variable  - R0 is overwritten */                                      \
-    "mov     r8, LO(%[ulCriticalNesting])\n\t"                                                      \
-    "orh     r8, HI(%[ulCriticalNesting])\n\t"                                                      \
-    "ld.w    r0, r8[0]                                                                              \n\t"\
-    "st.w    --sp, r0                                                                               \n\t"\
-                                                                                                    \
-    /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */    \
-    /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
-    /* level and allow other lower interrupt level to occur). */                                    \
-    /* In this case we don't want to do a task switch because we don't know what the stack */       \
-    /* currently looks like (we don't know what the interrupted interrupt handler was doing). */    \
-    /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */       \
-    /* will just be restoring the interrupt handler, no way!!! */                                   \
-    /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */                  \
-    "ld.w    r0, sp[9*4]\n\t" /* Read SR in stack */                                                \
-    "bfextu  r0, r0, 22, 3\n\t" /* Extract the mode bits to R0. */                                  \
-    "cp.w    r0, 1\n\t" /* Compare the mode bits with supervisor mode(b'001) */                     \
-    "brhi    LABEL_INT_SKIP_SAVE_CONTEXT_%[LINE]                                                    \n\t"\
-                                                                                                    \
-    /* Store SP in the first member of the structure pointed to by pxCurrentTCB */                  \
-    /* NOTE: we don't enter a critical section here because all interrupt handlers */               \
-    /* MUST perform a SAVE_CONTEXT/RESTORE_CONTEXT in the same way as */                            \
-    /* portSAVE_CONTEXT_OS_INT/port_RESTORE_CONTEXT_OS_INT if they call OS functions. */            \
-    /* => all interrupt handlers must use portENTER_SWITCHING_ISR/portEXIT_SWITCHING_ISR. */        \
-    "mov     r8, LO(%[pxCurrentTCB])\n\t"                                                           \
-    "orh     r8, HI(%[pxCurrentTCB])\n\t"                                                           \
-    "ld.w    r0, r8[0]\n\t"                                                                         \
-    "st.w    r0[0], sp\n"                                                                           \
-                                                                                                    \
-    "LABEL_INT_SKIP_SAVE_CONTEXT_%[LINE]:"                                                          \
-    :                                                                                               \
-    : [ulCriticalNesting] "i" (&ulCriticalNesting),                                                 \
-      [pxCurrentTCB] "i" (&pxCurrentTCB),                                                           \
-      [LINE] "i" (__LINE__)                                                                         \
-  );                                                                                                \
-}
+    #define portSAVE_CONTEXT_OS_INT()                                                                             \
+    {                                                                                                             \
+        extern volatile uint32_t ulCriticalNesting;                                                               \
+        extern volatile void * volatile pxCurrentTCB;                                                             \
+                                                                                                                  \
+        /* When we come here */                                                                                   \
+        /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */                            \
+                                                                                                                  \
+        __asm__ __volatile__ (                                                                                    \
+            /* Save R0..R7 */                                                                                     \
+            "stm     --sp, r0-r7                                                                            \n\t" \
+                                                                                                                  \
+            /* Save ulCriticalNesting variable  - R0 is overwritten */                                            \
+            "mov     r8, LO(%[ulCriticalNesting])\n\t"                                                            \
+            "orh     r8, HI(%[ulCriticalNesting])\n\t"                                                            \
+            "ld.w    r0, r8[0]                                                                              \n\t" \
+            "st.w    --sp, r0                                                                               \n\t" \
+                                                                                                                  \
+            /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */          \
+            /* interrupt handler (which was of a higher priority level but decided to lower its priority */       \
+            /* level and allow other lower interrupt level to occur). */                                          \
+            /* In this case we don't want to do a task switch because we don't know what the stack */             \
+            /* currently looks like (we don't know what the interrupted interrupt handler was doing). */          \
+            /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */             \
+            /* will just be restoring the interrupt handler, no way!!! */                                         \
+            /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */                        \
+            "ld.w    r0, sp[9*4]\n\t"   /* Read SR in stack */                                                    \
+            "bfextu  r0, r0, 22, 3\n\t" /* Extract the mode bits to R0. */                                        \
+            "cp.w    r0, 1\n\t"         /* Compare the mode bits with supervisor mode(b'001) */                   \
+            "brhi    LABEL_INT_SKIP_SAVE_CONTEXT_%[LINE]                                                    \n\t" \
+                                                                                                                  \
+            /* Store SP in the first member of the structure pointed to by pxCurrentTCB */                        \
+            /* NOTE: we don't enter a critical section here because all interrupt handlers */                     \
+            /* MUST perform a SAVE_CONTEXT/RESTORE_CONTEXT in the same way as */                                  \
+            /* portSAVE_CONTEXT_OS_INT/port_RESTORE_CONTEXT_OS_INT if they call OS functions. */                  \
+            /* => all interrupt handlers must use portENTER_SWITCHING_ISR/portEXIT_SWITCHING_ISR. */              \
+            "mov     r8, LO(%[pxCurrentTCB])\n\t"                                                                 \
+            "orh     r8, HI(%[pxCurrentTCB])\n\t"                                                                 \
+            "ld.w    r0, r8[0]\n\t"                                                                               \
+            "st.w    r0[0], sp\n"                                                                                 \
+                                                                                                                  \
+            "LABEL_INT_SKIP_SAVE_CONTEXT_%[LINE]:"                                                                \
+            :                                                                                                     \
+            :[ ulCriticalNesting ] "i" ( &ulCriticalNesting ),                                                    \
+            [ pxCurrentTCB ] "i" ( &pxCurrentTCB ),                                                               \
+            [ LINE ] "i" ( __LINE__ )                                                                             \
+            );                                                                                                    \
+    }
 
 /*
  * portRESTORE_CONTEXT_OS_INT() for Tick exception.
  */
-#define portRESTORE_CONTEXT_OS_INT()                                                                \
-{                                                                                                   \
-  extern volatile uint32_t ulCriticalNesting;                                               \
-  extern volatile void *volatile pxCurrentTCB;                                                      \
-                                                                                                    \
-  /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */      \
-  /* interrupt handler (which was of a higher priority level but decided to lower its priority */   \
-  /* level and allow other lower interrupt level to occur). */                                      \
-  /* In this case we don't want to do a task switch because we don't know what the stack */         \
-  /* currently looks like (we don't know what the interrupted interrupt handler was doing). */      \
-  /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */         \
-  /* will just be restoring the interrupt handler, no way!!! */                                     \
-  __asm__ __volatile__ (                                                                            \
-    "ld.w    r0, sp[9*4]\n\t" /* Read SR in stack */                                                \
-    "bfextu  r0, r0, 22, 3\n\t" /* Extract the mode bits to R0. */                                  \
-    "cp.w    r0, 1\n\t" /* Compare the mode bits with supervisor mode(b'001) */                     \
-    "brhi    LABEL_INT_SKIP_RESTORE_CONTEXT_%[LINE]"                                                \
-    :                                                                                               \
-    : [LINE] "i" (__LINE__)                                                                         \
-  );                                                                                                \
-                                                                                                    \
-  /* Else */                                                                                        \
-  /* because it is here safe, always call vTaskSwitchContext() since an OS tick occurred. */        \
-  /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */\
-  portENTER_CRITICAL();                                                                             \
-  vTaskSwitchContext();                                                                             \
-  portEXIT_CRITICAL();                                                                              \
-                                                                                                    \
-  /* Restore all registers */                                                                       \
-                                                                                                    \
-  __asm__ __volatile__ (                                                                            \
-    /* Set SP to point to new stack */                                                              \
-    "mov     r8, LO(%[pxCurrentTCB])                                                                \n\t"\
-    "orh     r8, HI(%[pxCurrentTCB])                                                                \n\t"\
-    "ld.w    r0, r8[0]                                                                              \n\t"\
-    "ld.w    sp, r0[0]                                                                              \n"\
-                                                                                                    \
-    "LABEL_INT_SKIP_RESTORE_CONTEXT_%[LINE]:                                                        \n\t"\
-                                                                                                    \
-    /* Restore ulCriticalNesting variable */                                                        \
-    "ld.w    r0, sp++                                                                               \n\t"                                                                           \
-    "mov     r8, LO(%[ulCriticalNesting])                                                           \n\t"\
-    "orh     r8, HI(%[ulCriticalNesting])                                                           \n\t"\
-    "st.w    r8[0], r0                                                                              \n\t"\
-                                                                                                    \
-    /* Restore R0..R7 */                                                                            \
-    "ldm     sp++, r0-r7                                                                            \n\t"\
-                                                                                                    \
-    /* Now, the stack should be R8..R12, LR, PC and SR */                                           \
-    "rete"                                                                                          \
-    :                                                                                               \
-    : [ulCriticalNesting] "i" (&ulCriticalNesting),                                                 \
-      [pxCurrentTCB] "i" (&pxCurrentTCB),                                                           \
-      [LINE] "i" (__LINE__)                                                                         \
-  );                                                                                                \
-}
+    #define portRESTORE_CONTEXT_OS_INT()                                                                          \
+    {                                                                                                             \
+        extern volatile uint32_t ulCriticalNesting;                                                               \
+        extern volatile void * volatile pxCurrentTCB;                                                             \
+                                                                                                                  \
+        /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */              \
+        /* interrupt handler (which was of a higher priority level but decided to lower its priority */           \
+        /* level and allow other lower interrupt level to occur). */                                              \
+        /* In this case we don't want to do a task switch because we don't know what the stack */                 \
+        /* currently looks like (we don't know what the interrupted interrupt handler was doing). */              \
+        /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */                 \
+        /* will just be restoring the interrupt handler, no way!!! */                                             \
+        __asm__ __volatile__ (                                                                                    \
+            "ld.w    r0, sp[9*4]\n\t"   /* Read SR in stack */                                                    \
+            "bfextu  r0, r0, 22, 3\n\t" /* Extract the mode bits to R0. */                                        \
+            "cp.w    r0, 1\n\t"         /* Compare the mode bits with supervisor mode(b'001) */                   \
+            "brhi    LABEL_INT_SKIP_RESTORE_CONTEXT_%[LINE]"                                                      \
+            :                                                                                                     \
+            :[ LINE ] "i" ( __LINE__ )                                                                            \
+            );                                                                                                    \
+                                                                                                                  \
+        /* Else */                                                                                                \
+        /* because it is here safe, always call vTaskSwitchContext() since an OS tick occurred. */                \
+        /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */    \
+        portENTER_CRITICAL();                                                                                     \
+        vTaskSwitchContext();                                                                                     \
+        portEXIT_CRITICAL();                                                                                      \
+                                                                                                                  \
+        /* Restore all registers */                                                                               \
+                                                                                                                  \
+        __asm__ __volatile__ (                                                                                    \
+            /* Set SP to point to new stack */                                                                    \
+            "mov     r8, LO(%[pxCurrentTCB])                                                                \n\t" \
+            "orh     r8, HI(%[pxCurrentTCB])                                                                \n\t" \
+            "ld.w    r0, r8[0]                                                                              \n\t" \
+            "ld.w    sp, r0[0]                                                                              \n"   \
+                                                                                                                  \
+            "LABEL_INT_SKIP_RESTORE_CONTEXT_%[LINE]:                                                        \n\t" \
+                                                                                                                  \
+            /* Restore ulCriticalNesting variable */                                                              \
+            "ld.w    r0, sp++                                                                               \n\t" \
+            "mov     r8, LO(%[ulCriticalNesting])                                                           \n\t" \
+            "orh     r8, HI(%[ulCriticalNesting])                                                           \n\t" \
+            "st.w    r8[0], r0                                                                              \n\t" \
+                                                                                                                  \
+            /* Restore R0..R7 */                                                                                  \
+            "ldm     sp++, r0-r7                                                                            \n\t" \
+                                                                                                                  \
+            /* Now, the stack should be R8..R12, LR, PC and SR */                                                 \
+            "rete"                                                                                                \
+            :                                                                                                     \
+            :[ ulCriticalNesting ] "i" ( &ulCriticalNesting ),                                                    \
+            [ pxCurrentTCB ] "i" ( &pxCurrentTCB ),                                                               \
+            [ LINE ] "i" ( __LINE__ )                                                                             \
+            );                                                                                                    \
+    }
 
-#endif
+#endif /* if configUSE_PREEMPTION == 0 */
 
 
 /*
@@ -414,123 +416,123 @@ extern void *pvPortRealloc( void *pv, size_t xSize );
  * NOTE: taskYIELD()(== SCALL) MUST NOT be called in a mode > supervisor mode.
  *
  */
-#define portSAVE_CONTEXT_SCALL()                                                            \
-{                                                                                           \
-  extern volatile uint32_t ulCriticalNesting;                                       \
-  extern volatile void *volatile pxCurrentTCB;                                              \
-                                                                                            \
-  /* Warning: the stack layout after SCALL doesn't match the one after an interrupt. */     \
-  /* If SR[M2:M0] == 001 */                                                                 \
-  /*    PC and SR are on the stack.  */                                                     \
-  /* Else (other modes) */                                                                  \
-  /*    Nothing on the stack. */                                                            \
-                                                                                            \
-  /* WARNING NOTE: the else case cannot happen as it is strictly forbidden to call */       \
-  /* vTaskDelay() and vTaskDelayUntil() OS functions (that result in a taskYield()) */      \
-  /* in an interrupt|exception handler. */                                                  \
-                                                                                            \
-  __asm__ __volatile__ (                                                                    \
-    /* in order to save R0-R7 */                                                            \
-    "sub     sp, 6*4                                                                        \n\t"\
-    /* Save R0..R7 */                                                                       \
-    "stm     --sp, r0-r7                                                                    \n\t"\
-                                                                                            \
-    /* in order to save R8-R12 and LR */                                                    \
-    /* do not use SP if interrupts occurs, SP must be left at bottom of stack */            \
-    "sub     r7, sp,-16*4                                                                   \n\t"\
-    /* Copy PC and SR in other places in the stack. */                                      \
-    "ld.w    r0, r7[-2*4]                                                                   \n\t" /* Read SR */\
-    "st.w    r7[-8*4], r0                                                                   \n\t" /* Copy SR */\
-    "ld.w    r0, r7[-1*4]                                                                   \n\t" /* Read PC */\
-    "st.w    r7[-7*4], r0                                                                   \n\t" /* Copy PC */\
-                                                                                            \
-    /* Save R8..R12 and LR on the stack. */                                                 \
-    "stm     --r7, r8-r12, lr                                                               \n\t"\
-                                                                                            \
-    /* Arriving here we have the following stack organizations: */                          \
-    /* R8..R12, LR, PC, SR, R0..R7. */                                                      \
-                                                                                            \
-    /* Now we can finalize the save. */                                                     \
-                                                                                            \
-    /* Save ulCriticalNesting variable  - R0 is overwritten */                              \
-    "mov     r8, LO(%[ulCriticalNesting])                                                   \n\t"\
-    "orh     r8, HI(%[ulCriticalNesting])                                                   \n\t"\
-    "ld.w    r0, r8[0]                                                                      \n\t"\
-    "st.w    --sp, r0"                                                                      \
-    :                                                                                       \
-    : [ulCriticalNesting] "i" (&ulCriticalNesting)                                          \
-  );                                                                                        \
-                                                                                            \
-  /* Disable the its which may cause a context switch (i.e. cause a change of */            \
-  /* pxCurrentTCB). */                                                                      \
-  /* Basically, all accesses to the pxCurrentTCB structure should be put in a */            \
-  /* critical section because it is a global structure. */                                  \
-  portENTER_CRITICAL();                                                                     \
-                                                                                            \
-  /* Store SP in the first member of the structure pointed to by pxCurrentTCB */            \
-  __asm__ __volatile__ (                                                                    \
-    "mov     r8, LO(%[pxCurrentTCB])                                                        \n\t"\
-    "orh     r8, HI(%[pxCurrentTCB])                                                        \n\t"\
-    "ld.w    r0, r8[0]                                                                      \n\t"\
-    "st.w    r0[0], sp"                                                                     \
-    :                                                                                       \
-    : [pxCurrentTCB] "i" (&pxCurrentTCB)                                                    \
-  );                                                                                        \
-}
+#define portSAVE_CONTEXT_SCALL()                                                                                        \
+    {                                                                                                                   \
+        extern volatile uint32_t ulCriticalNesting;                                                                     \
+        extern volatile void * volatile pxCurrentTCB;                                                                   \
+                                                                                                                        \
+        /* Warning: the stack layout after SCALL doesn't match the one after an interrupt. */                           \
+        /* If SR[M2:M0] == 001 */                                                                                       \
+        /*    PC and SR are on the stack.  */                                                                           \
+        /* Else (other modes) */                                                                                        \
+        /*    Nothing on the stack. */                                                                                  \
+                                                                                                                        \
+        /* WARNING NOTE: the else case cannot happen as it is strictly forbidden to call */                             \
+        /* vTaskDelay() and vTaskDelayUntil() OS functions (that result in a taskYield()) */                            \
+        /* in an interrupt|exception handler. */                                                                        \
+                                                                                                                        \
+        __asm__ __volatile__ (                                                                                          \
+            /* in order to save R0-R7 */                                                                                \
+            "sub     sp, 6*4                                                                        \n\t"               \
+            /* Save R0..R7 */                                                                                           \
+            "stm     --sp, r0-r7                                                                    \n\t"               \
+                                                                                                                        \
+            /* in order to save R8-R12 and LR */                                                                        \
+            /* do not use SP if interrupts occurs, SP must be left at bottom of stack */                                \
+            "sub     r7, sp,-16*4                                                                   \n\t"               \
+            /* Copy PC and SR in other places in the stack. */                                                          \
+            "ld.w    r0, r7[-2*4]                                                                   \n\t" /* Read SR */ \
+            "st.w    r7[-8*4], r0                                                                   \n\t" /* Copy SR */ \
+            "ld.w    r0, r7[-1*4]                                                                   \n\t" /* Read PC */ \
+            "st.w    r7[-7*4], r0                                                                   \n\t" /* Copy PC */ \
+                                                                                                                        \
+            /* Save R8..R12 and LR on the stack. */                                                                     \
+            "stm     --r7, r8-r12, lr                                                               \n\t"               \
+                                                                                                                        \
+            /* Arriving here we have the following stack organizations: */                                              \
+            /* R8..R12, LR, PC, SR, R0..R7. */                                                                          \
+                                                                                                                        \
+            /* Now we can finalize the save. */                                                                         \
+                                                                                                                        \
+            /* Save ulCriticalNesting variable  - R0 is overwritten */                                                  \
+            "mov     r8, LO(%[ulCriticalNesting])                                                   \n\t"               \
+            "orh     r8, HI(%[ulCriticalNesting])                                                   \n\t"               \
+            "ld.w    r0, r8[0]                                                                      \n\t"               \
+            "st.w    --sp, r0"                                                                                          \
+            :                                                                                                           \
+            :[ ulCriticalNesting ] "i" ( &ulCriticalNesting )                                                           \
+            );                                                                                                          \
+                                                                                                                        \
+        /* Disable the its which may cause a context switch (i.e. cause a change of */                                  \
+        /* pxCurrentTCB). */                                                                                            \
+        /* Basically, all accesses to the pxCurrentTCB structure should be put in a */                                  \
+        /* critical section because it is a global structure. */                                                        \
+        portENTER_CRITICAL();                                                                                           \
+                                                                                                                        \
+        /* Store SP in the first member of the structure pointed to by pxCurrentTCB */                                  \
+        __asm__ __volatile__ (                                                                                          \
+            "mov     r8, LO(%[pxCurrentTCB])                                                        \n\t"               \
+            "orh     r8, HI(%[pxCurrentTCB])                                                        \n\t"               \
+            "ld.w    r0, r8[0]                                                                      \n\t"               \
+            "st.w    r0[0], sp"                                                                                         \
+            :                                                                                                           \
+            :[ pxCurrentTCB ] "i" ( &pxCurrentTCB )                                                                     \
+            );                                                                                                          \
+    }
 
 /*
  * portRESTORE_CONTEXT() for SupervisorCALL exception.
  */
-#define portRESTORE_CONTEXT_SCALL()                                                         \
-{                                                                                           \
-  extern volatile uint32_t ulCriticalNesting;                                       \
-  extern volatile void *volatile pxCurrentTCB;                                              \
-                                                                                            \
-  /* Restore all registers */                                                               \
-                                                                                            \
-  /* Set SP to point to new stack */                                                        \
-  __asm__ __volatile__ (                                                                    \
-    "mov     r8, LO(%[pxCurrentTCB])                                                        \n\t"\
-    "orh     r8, HI(%[pxCurrentTCB])                                                        \n\t"\
-    "ld.w    r0, r8[0]                                                                      \n\t"\
-    "ld.w    sp, r0[0]"                                                                     \
-    :                                                                                       \
-    : [pxCurrentTCB] "i" (&pxCurrentTCB)                                                    \
-  );                                                                                        \
-                                                                                            \
-  /* Leave pxCurrentTCB variable access critical section */                                 \
-  portEXIT_CRITICAL();                                                                      \
-                                                                                            \
-  __asm__ __volatile__ (                                                                    \
-    /* Restore ulCriticalNesting variable */                                                \
-    "ld.w    r0, sp++                                                                       \n\t"\
-    "mov     r8, LO(%[ulCriticalNesting])                                                   \n\t"\
-    "orh     r8, HI(%[ulCriticalNesting])                                                   \n\t"\
-    "st.w    r8[0], r0                                                                      \n\t"\
-                                                                                            \
-    /* skip PC and SR */                                                                    \
-    /* do not use SP if interrupts occurs, SP must be left at bottom of stack */            \
-    "sub     r7, sp, -10*4                                                                  \n\t"\
-    /* Restore r8-r12 and LR */                                                             \
-    "ldm     r7++, r8-r12, lr                                                               \n\t"\
-                                                                                            \
-    /* RETS will take care of the extra PC and SR restore. */                               \
-    /* So, we have to prepare the stack for this. */                                        \
-    "ld.w    r0, r7[-8*4]                                                                   \n\t" /* Read SR */\
-    "st.w    r7[-2*4], r0                                                                   \n\t" /* Copy SR */\
-    "ld.w    r0, r7[-7*4]                                                                   \n\t" /* Read PC */\
-    "st.w    r7[-1*4], r0                                                                   \n\t" /* Copy PC */\
-                                                                                            \
-    /* Restore R0..R7 */                                                                    \
-    "ldm     sp++, r0-r7                                                                    \n\t"\
-                                                                                            \
-    "sub     sp, -6*4                                                                       \n\t"\
-                                                                                            \
-    "rets"                                                                                  \
-    :                                                                                       \
-    : [ulCriticalNesting] "i" (&ulCriticalNesting)                                          \
-  );                                                                                        \
-}
+#define portRESTORE_CONTEXT_SCALL()                                                                                     \
+    {                                                                                                                   \
+        extern volatile uint32_t ulCriticalNesting;                                                                     \
+        extern volatile void * volatile pxCurrentTCB;                                                                   \
+                                                                                                                        \
+        /* Restore all registers */                                                                                     \
+                                                                                                                        \
+        /* Set SP to point to new stack */                                                                              \
+        __asm__ __volatile__ (                                                                                          \
+            "mov     r8, LO(%[pxCurrentTCB])                                                        \n\t"               \
+            "orh     r8, HI(%[pxCurrentTCB])                                                        \n\t"               \
+            "ld.w    r0, r8[0]                                                                      \n\t"               \
+            "ld.w    sp, r0[0]"                                                                                         \
+            :                                                                                                           \
+            :[ pxCurrentTCB ] "i" ( &pxCurrentTCB )                                                                     \
+            );                                                                                                          \
+                                                                                                                        \
+        /* Leave pxCurrentTCB variable access critical section */                                                       \
+        portEXIT_CRITICAL();                                                                                            \
+                                                                                                                        \
+        __asm__ __volatile__ (                                                                                          \
+            /* Restore ulCriticalNesting variable */                                                                    \
+            "ld.w    r0, sp++                                                                       \n\t"               \
+            "mov     r8, LO(%[ulCriticalNesting])                                                   \n\t"               \
+            "orh     r8, HI(%[ulCriticalNesting])                                                   \n\t"               \
+            "st.w    r8[0], r0                                                                      \n\t"               \
+                                                                                                                        \
+            /* skip PC and SR */                                                                                        \
+            /* do not use SP if interrupts occurs, SP must be left at bottom of stack */                                \
+            "sub     r7, sp, -10*4                                                                  \n\t"               \
+            /* Restore r8-r12 and LR */                                                                                 \
+            "ldm     r7++, r8-r12, lr                                                               \n\t"               \
+                                                                                                                        \
+            /* RETS will take care of the extra PC and SR restore. */                                                   \
+            /* So, we have to prepare the stack for this. */                                                            \
+            "ld.w    r0, r7[-8*4]                                                                   \n\t" /* Read SR */ \
+            "st.w    r7[-2*4], r0                                                                   \n\t" /* Copy SR */ \
+            "ld.w    r0, r7[-7*4]                                                                   \n\t" /* Read PC */ \
+            "st.w    r7[-1*4], r0                                                                   \n\t" /* Copy PC */ \
+                                                                                                                        \
+            /* Restore R0..R7 */                                                                                        \
+            "ldm     sp++, r0-r7                                                                    \n\t"               \
+                                                                                                                        \
+            "sub     sp, -6*4                                                                       \n\t"               \
+                                                                                                                        \
+            "rets"                                                                                                      \
+            :                                                                                                           \
+            :[ ulCriticalNesting ] "i" ( &ulCriticalNesting )                                                           \
+            );                                                                                                          \
+    }
 
 
 /*
@@ -543,155 +545,155 @@ extern void *pvPortRealloc( void *pv, size_t xSize );
  * ISR entry and exit macros.  These are only required if a task switch
  * is required from the ISR.
  */
-#define portENTER_SWITCHING_ISR()                                                           \
-{                                                                                           \
-  /* Save R0..R7 */                                                                         \
-  __asm__ __volatile__ ("stm     --sp, r0-r7");                                             \
-                                                                                            \
-  /* With the cooperative scheduler, as there is no context switch by interrupt, */         \
-  /* there is also no context save. */                                                      \
-}
+    #define portENTER_SWITCHING_ISR()                                                     \
+    {                                                                                     \
+        /* Save R0..R7 */                                                                 \
+        __asm__ __volatile__ ( "stm     --sp, r0-r7" );                                   \
+                                                                                          \
+        /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
+        /* there is also no context save. */                                              \
+    }
 
 /*
  * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1
  */
-#define portEXIT_SWITCHING_ISR()                                                            \
-{                                                                                           \
-  __asm__ __volatile__ (                                                                    \
-    /* Restore R0..R7 */                                                                    \
-    "ldm     sp++, r0-r7                                                                    \n\t"\
-                                                                                            \
-    /* With the cooperative scheduler, as there is no context switch by interrupt, */       \
-    /* there is also no context restore. */                                                 \
-    "rete"                                                                                  \
-  );                                                                                        \
-}
+    #define portEXIT_SWITCHING_ISR()                                                                      \
+    {                                                                                                     \
+        __asm__ __volatile__ (                                                                            \
+            /* Restore R0..R7 */                                                                          \
+            "ldm     sp++, r0-r7                                                                    \n\t" \
+                                                                                                          \
+            /* With the cooperative scheduler, as there is no context switch by interrupt, */             \
+            /* there is also no context restore. */                                                       \
+            "rete"                                                                                        \
+            );                                                                                            \
+    }
 
-#else
+#else /* if configUSE_PREEMPTION == 0 */
 
 /*
  * ISR entry and exit macros.  These are only required if a task switch
  * is required from the ISR.
  */
-#define portENTER_SWITCHING_ISR()                                                           \
-{                                                                                           \
-  extern volatile uint32_t ulCriticalNesting;                                       \
-  extern volatile void *volatile pxCurrentTCB;                                              \
-                                                                                            \
-  /* When we come here */                                                                   \
-  /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */            \
-                                                                                            \
-  __asm__ __volatile__ (                                                                    \
-    /* Save R0..R7 */                                                                       \
-    "stm     --sp, r0-r7                                                                    \n\t"\
-                                                                                            \
-    /* Save ulCriticalNesting variable  - R0 is overwritten */                              \
-    "mov     r8, LO(%[ulCriticalNesting])                                                   \n\t"\
-    "orh     r8, HI(%[ulCriticalNesting])                                                   \n\t"\
-    "ld.w    r0, r8[0]                                                                      \n\t"\
-    "st.w    --sp, r0                                                                       \n\t"\
-                                                                                                    \
-    /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */    \
-    /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
-    /* level and allow other lower interrupt level to occur). */                                    \
-    /* In this case we don't want to do a task switch because we don't know what the stack */       \
-    /* currently looks like (we don't know what the interrupted interrupt handler was doing). */    \
-    /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */       \
-    /* will just be restoring the interrupt handler, no way!!! */                                   \
-    /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */                  \
-    "ld.w    r0, sp[9*4]                                                                    \n\t" /* Read SR in stack */\
-    "bfextu  r0, r0, 22, 3                                                                  \n\t" /* Extract the mode bits to R0. */\
-    "cp.w    r0, 1                                                                          \n\t" /* Compare the mode bits with supervisor mode(b'001) */\
-    "brhi    LABEL_ISR_SKIP_SAVE_CONTEXT_%[LINE]                                            \n\t"\
-                                                                                            \
-    /* Store SP in the first member of the structure pointed to by pxCurrentTCB */          \
-    "mov     r8, LO(%[pxCurrentTCB])                                                        \n\t"\
-    "orh     r8, HI(%[pxCurrentTCB])                                                        \n\t"\
-    "ld.w    r0, r8[0]                                                                      \n\t"\
-    "st.w    r0[0], sp                                                                      \n"\
-                                                                                            \
-    "LABEL_ISR_SKIP_SAVE_CONTEXT_%[LINE]:"                                                  \
-    :                                                                                       \
-    : [ulCriticalNesting] "i" (&ulCriticalNesting),                                         \
-      [pxCurrentTCB] "i" (&pxCurrentTCB),                                                   \
-      [LINE] "i" (__LINE__)                                                                 \
-  );                                                                                        \
-}
+    #define portENTER_SWITCHING_ISR()                                                                                                                             \
+    {                                                                                                                                                             \
+        extern volatile uint32_t ulCriticalNesting;                                                                                                               \
+        extern volatile void * volatile pxCurrentTCB;                                                                                                             \
+                                                                                                                                                                  \
+        /* When we come here */                                                                                                                                   \
+        /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */                                                                            \
+                                                                                                                                                                  \
+        __asm__ __volatile__ (                                                                                                                                    \
+            /* Save R0..R7 */                                                                                                                                     \
+            "stm     --sp, r0-r7                                                                    \n\t"                                                         \
+                                                                                                                                                                  \
+            /* Save ulCriticalNesting variable  - R0 is overwritten */                                                                                            \
+            "mov     r8, LO(%[ulCriticalNesting])                                                   \n\t"                                                         \
+            "orh     r8, HI(%[ulCriticalNesting])                                                   \n\t"                                                         \
+            "ld.w    r0, r8[0]                                                                      \n\t"                                                         \
+            "st.w    --sp, r0                                                                       \n\t"                                                         \
+                                                                                                                                                                  \
+            /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */                                                          \
+            /* interrupt handler (which was of a higher priority level but decided to lower its priority */                                                       \
+            /* level and allow other lower interrupt level to occur). */                                                                                          \
+            /* In this case we don't want to do a task switch because we don't know what the stack */                                                             \
+            /* currently looks like (we don't know what the interrupted interrupt handler was doing). */                                                          \
+            /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */                                                             \
+            /* will just be restoring the interrupt handler, no way!!! */                                                                                         \
+            /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */                                                                        \
+            "ld.w    r0, sp[9*4]                                                                    \n\t" /* Read SR in stack */                                  \
+            "bfextu  r0, r0, 22, 3                                                                  \n\t" /* Extract the mode bits to R0. */                      \
+            "cp.w    r0, 1                                                                          \n\t" /* Compare the mode bits with supervisor mode(b'001) */ \
+            "brhi    LABEL_ISR_SKIP_SAVE_CONTEXT_%[LINE]                                            \n\t"                                                         \
+                                                                                                                                                                  \
+            /* Store SP in the first member of the structure pointed to by pxCurrentTCB */                                                                        \
+            "mov     r8, LO(%[pxCurrentTCB])                                                        \n\t"                                                         \
+            "orh     r8, HI(%[pxCurrentTCB])                                                        \n\t"                                                         \
+            "ld.w    r0, r8[0]                                                                      \n\t"                                                         \
+            "st.w    r0[0], sp                                                                      \n"                                                           \
+                                                                                                                                                                  \
+            "LABEL_ISR_SKIP_SAVE_CONTEXT_%[LINE]:"                                                                                                                \
+            :                                                                                                                                                     \
+            :[ ulCriticalNesting ] "i" ( &ulCriticalNesting ),                                                                                                    \
+            [ pxCurrentTCB ] "i" ( &pxCurrentTCB ),                                                                                                               \
+            [ LINE ] "i" ( __LINE__ )                                                                                                                             \
+            );                                                                                                                                                    \
+    }
 
 /*
  * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1
  */
-#define portEXIT_SWITCHING_ISR()                                                            \
-{                                                                                           \
-  extern volatile uint32_t ulCriticalNesting;                                       \
-  extern volatile void *volatile pxCurrentTCB;                                              \
-                                                                                            \
-  __asm__ __volatile__ (                                                                    \
-    /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */        \
-    /* interrupt handler (which was of a higher priority level but decided to lower its priority */     \
-    /* level and allow other lower interrupt level to occur). */                                        \
-    /* In this case it's of no use to switch context and restore a new SP because we purposedly */      \
-    /* did not previously save SP in its TCB. */                                                                                \
-    "ld.w    r0, sp[9*4]                                                                    \n\t" /* Read SR in stack */\
-    "bfextu  r0, r0, 22, 3                                                                  \n\t" /* Extract the mode bits to R0. */\
-    "cp.w    r0, 1                                                                          \n\t" /* Compare the mode bits with supervisor mode(b'001) */\
-    "brhi    LABEL_ISR_SKIP_RESTORE_CONTEXT_%[LINE]                                         \n\t"\
-                                                                                            \
-    /* If a switch is required then we just need to call */                                 \
-    /* vTaskSwitchContext() as the context has already been */                              \
-    /* saved. */                                                                            \
-    "cp.w    r12, 1                                                                         \n\t" /* Check if Switch context is required. */\
-    "brne    LABEL_ISR_RESTORE_CONTEXT_%[LINE]"                                             \
-    :                                                                                       \
-    : [LINE] "i" (__LINE__)                                                                 \
-  );                                                                                        \
-                                                                                            \
-  /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */    \
-  portENTER_CRITICAL();                                                                     \
-  vTaskSwitchContext();                                                                     \
-  portEXIT_CRITICAL();                                                                      \
-                                                                                            \
-  __asm__ __volatile__ (                                                                    \
-    "LABEL_ISR_RESTORE_CONTEXT_%[LINE]:                                                     \n\t"\
-    /* Restore the context of which ever task is now the highest */                         \
-    /* priority that is ready to run. */                                                    \
-                                                                                            \
-    /* Restore all registers */                                                             \
-                                                                                            \
-    /* Set SP to point to new stack */                                                      \
-    "mov     r8, LO(%[pxCurrentTCB])                                                        \n\t"\
-    "orh     r8, HI(%[pxCurrentTCB])                                                        \n\t"\
-    "ld.w    r0, r8[0]                                                                      \n\t"\
-    "ld.w    sp, r0[0]                                                                      \n"\
-                                                                                            \
-    "LABEL_ISR_SKIP_RESTORE_CONTEXT_%[LINE]:                                                \n\t"\
-                                                                                            \
-    /* Restore ulCriticalNesting variable */                                                \
-    "ld.w    r0, sp++                                                                       \n\t"\
-    "mov     r8, LO(%[ulCriticalNesting])                                                   \n\t"\
-    "orh     r8, HI(%[ulCriticalNesting])                                                   \n\t"\
-    "st.w    r8[0], r0                                                                      \n\t"\
-                                                                                            \
-    /* Restore R0..R7 */                                                                    \
-    "ldm     sp++, r0-r7                                                                    \n\t"\
-                                                                                            \
-    /* Now, the stack should be R8..R12, LR, PC and SR  */                                  \
-    "rete"                                                                                  \
-    :                                                                                       \
-    : [ulCriticalNesting] "i" (&ulCriticalNesting),                                         \
-      [pxCurrentTCB] "i" (&pxCurrentTCB),                                                   \
-      [LINE] "i" (__LINE__)                                                                 \
-  );                                                                                        \
-}
+    #define portEXIT_SWITCHING_ISR()                                                                                                                              \
+    {                                                                                                                                                             \
+        extern volatile uint32_t ulCriticalNesting;                                                                                                               \
+        extern volatile void * volatile pxCurrentTCB;                                                                                                             \
+                                                                                                                                                                  \
+        __asm__ __volatile__ (                                                                                                                                    \
+            /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */                                                          \
+            /* interrupt handler (which was of a higher priority level but decided to lower its priority */                                                       \
+            /* level and allow other lower interrupt level to occur). */                                                                                          \
+            /* In this case it's of no use to switch context and restore a new SP because we purposely */                                                         \
+            /* did not previously save SP in its TCB. */                                                                                                          \
+            "ld.w    r0, sp[9*4]                                                                    \n\t" /* Read SR in stack */                                  \
+            "bfextu  r0, r0, 22, 3                                                                  \n\t" /* Extract the mode bits to R0. */                      \
+            "cp.w    r0, 1                                                                          \n\t" /* Compare the mode bits with supervisor mode(b'001) */ \
+            "brhi    LABEL_ISR_SKIP_RESTORE_CONTEXT_%[LINE]                                         \n\t"                                                         \
+                                                                                                                                                                  \
+            /* If a switch is required then we just need to call */                                                                                               \
+            /* vTaskSwitchContext() as the context has already been */                                                                                            \
+            /* saved. */                                                                                                                                          \
+            "cp.w    r12, 1                                                                         \n\t" /* Check if Switch context is required. */              \
+            "brne    LABEL_ISR_RESTORE_CONTEXT_%[LINE]"                                                                                                           \
+            :                                                                                                                                                     \
+            :[ LINE ] "i" ( __LINE__ )                                                                                                                            \
+            );                                                                                                                                                    \
+                                                                                                                                                                  \
+        /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */                                                    \
+        portENTER_CRITICAL();                                                                                                                                     \
+        vTaskSwitchContext();                                                                                                                                     \
+        portEXIT_CRITICAL();                                                                                                                                      \
+                                                                                                                                                                  \
+        __asm__ __volatile__ (                                                                                                                                    \
+            "LABEL_ISR_RESTORE_CONTEXT_%[LINE]:                                                     \n\t"                                                         \
+            /* Restore the context of which ever task is now the highest */                                                                                       \
+            /* priority that is ready to run. */                                                                                                                  \
+                                                                                                                                                                  \
+            /* Restore all registers */                                                                                                                           \
+                                                                                                                                                                  \
+            /* Set SP to point to new stack */                                                                                                                    \
+            "mov     r8, LO(%[pxCurrentTCB])                                                        \n\t"                                                         \
+            "orh     r8, HI(%[pxCurrentTCB])                                                        \n\t"                                                         \
+            "ld.w    r0, r8[0]                                                                      \n\t"                                                         \
+            "ld.w    sp, r0[0]                                                                      \n"                                                           \
+                                                                                                                                                                  \
+            "LABEL_ISR_SKIP_RESTORE_CONTEXT_%[LINE]:                                                \n\t"                                                         \
+                                                                                                                                                                  \
+            /* Restore ulCriticalNesting variable */                                                                                                              \
+            "ld.w    r0, sp++                                                                       \n\t"                                                         \
+            "mov     r8, LO(%[ulCriticalNesting])                                                   \n\t"                                                         \
+            "orh     r8, HI(%[ulCriticalNesting])                                                   \n\t"                                                         \
+            "st.w    r8[0], r0                                                                      \n\t"                                                         \
+                                                                                                                                                                  \
+            /* Restore R0..R7 */                                                                                                                                  \
+            "ldm     sp++, r0-r7                                                                    \n\t"                                                         \
+                                                                                                                                                                  \
+            /* Now, the stack should be R8..R12, LR, PC and SR  */                                                                                                \
+            "rete"                                                                                                                                                \
+            :                                                                                                                                                     \
+            :[ ulCriticalNesting ] "i" ( &ulCriticalNesting ),                                                                                                    \
+            [ pxCurrentTCB ] "i" ( &pxCurrentTCB ),                                                                                                               \
+            [ LINE ] "i" ( __LINE__ )                                                                                                                             \
+            );                                                                                                                                                    \
+    }
 
-#endif
+#endif /* if configUSE_PREEMPTION == 0 */
 
 
-#define portYIELD()                 {__asm__ __volatile__ ("scall");}
+#define portYIELD()                                           { __asm__ __volatile__ ( "scall" ); }
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/GCC/CORTUS_APS3/port.c b/portable/GCC/CORTUS_APS3/port.c
index e2ada1a5b..30c3ca654 100644
--- a/portable/GCC/CORTUS_APS3/port.c
+++ b/portable/GCC/CORTUS_APS3/port.c
@@ -39,7 +39,7 @@
 /*-----------------------------------------------------------*/
 
 /* The initial PSR has the Previous Interrupt Enabled (PIEN) flag set. */
-#define portINITIAL_PSR         ( 0x00020000 )
+#define portINITIAL_PSR    ( 0x00020000 )
 
 /*-----------------------------------------------------------*/
 
@@ -49,10 +49,12 @@
 static void prvSetupTimerInterrupt( void );
 /*-----------------------------------------------------------*/
 
-StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
     /* Make space on the stack for the context - this leaves a couple of spaces
-    empty.  */
+     * empty.  */
     pxTopOfStack -= 20;
 
     /* Fill the registers with known values to assist debugging. */
@@ -107,7 +109,7 @@ static void prvSetupTimerInterrupt( void )
 /*-----------------------------------------------------------*/
 
 /* Trap 31 handler. */
-void interrupt31_handler( void ) __attribute__((naked));
+void interrupt31_handler( void ) __attribute__( ( naked ) );
 void interrupt31_handler( void )
 {
     portSAVE_CONTEXT();
@@ -116,7 +118,7 @@ void interrupt31_handler( void )
 }
 /*-----------------------------------------------------------*/
 
-static void prvProcessTick( void ) __attribute__((noinline));
+static void prvProcessTick( void ) __attribute__( ( noinline ) );
 static void prvProcessTick( void )
 {
     if( xTaskIncrementTick() != pdFALSE )
@@ -130,7 +132,7 @@ static void prvProcessTick( void )
 /*-----------------------------------------------------------*/
 
 /* Timer 1 interrupt handler, used for tick interrupt. */
-void interrupt7_handler( void ) __attribute__((naked));
+void interrupt7_handler( void ) __attribute__( ( naked ) );
 void interrupt7_handler( void )
 {
     portSAVE_CONTEXT();
diff --git a/portable/GCC/CORTUS_APS3/portmacro.h b/portable/GCC/CORTUS_APS3/portmacro.h
index 9d2d0e0cd..91a18bc74 100644
--- a/portable/GCC/CORTUS_APS3/portmacro.h
+++ b/portable/GCC/CORTUS_APS3/portmacro.h
@@ -48,36 +48,36 @@
  */
 
 /* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint32_t
-#define portBASE_TYPE   long
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY ( TickType_t )    ( 0xFFFFFFFFUL )
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) ( 0xFFFFFFFFUL )
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
 /*-----------------------------------------------------------*/
 
 /* Architecture specifics. */
-#define portSTACK_GROWTH                            ( -1 )
-#define portTICK_PERIOD_MS                          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT                          4
-#define portNOP()                                   __asm__ volatile ( "mov r0, r0" )
-#define portCRITICAL_NESTING_IN_TCB                 1
-#define portIRQ_TRAP_YIELD                          31
+#define portSTACK_GROWTH               ( -1 )
+#define portTICK_PERIOD_MS             ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT             4
+#define portNOP()    __asm__ volatile ( "mov r0, r0" )
+#define portCRITICAL_NESTING_IN_TCB    1
+#define portIRQ_TRAP_YIELD             31
 /*-----------------------------------------------------------*/
 
 /* Task utilities. */
@@ -86,13 +86,13 @@ extern void vPortYield( void );
 
 /*---------------------------------------------------------------------------*/
 
-#define portYIELD()     asm __volatile__( " trap #%0 "::"i"(portIRQ_TRAP_YIELD):"memory")
+#define portYIELD()    asm __volatile__ ( " trap #%0 " : : "i" ( portIRQ_TRAP_YIELD ) : "memory" )
 /*---------------------------------------------------------------------------*/
 
 extern void vTaskEnterCritical( void );
 extern void vTaskExitCritical( void );
-#define portENTER_CRITICAL()        vTaskEnterCritical()
-#define portEXIT_CRITICAL()         vTaskExitCritical()
+#define portENTER_CRITICAL()    vTaskEnterCritical()
+#define portEXIT_CRITICAL()     vTaskExitCritical()
 /*---------------------------------------------------------------------------*/
 
 /* Critical section management. */
@@ -101,53 +101,53 @@ extern void vTaskExitCritical( void );
 
 /*---------------------------------------------------------------------------*/
 
-#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) do { if( xHigherPriorityTaskWoken != pdFALSE ) vTaskSwitchContext(); } while( 0 )
+#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken )    do { if( xHigherPriorityTaskWoken != pdFALSE ) vTaskSwitchContext( ); } while( 0 )
 
 /*---------------------------------------------------------------------------*/
 
-#define portSAVE_CONTEXT()              \
-    asm __volatile__                                                                                                \
-    (                                                                                                               \
-        "sub    r1, #68                 \n" /* Make space on the stack for the context. */                          \
-        "std    r2, [r1] +  0           \n"                                                                         \
-        "stq    r4, [r1] +  8           \n"                                                                         \
-        "stq    r8, [r1] +  24          \n"                                                                         \
-        "stq    r12, [r1] + 40          \n"                                                                         \
-        "mov    r6, rtt                 \n"                                                                         \
-        "mov    r7, psr                 \n"                                                                         \
-        "std    r6, [r1] +  56          \n"                                                                         \
-        "movhi  r2, #16384              \n" /* Set the pointer to the IC. */                                        \
-        "ldub   r3, [r2] + 2            \n" /* Load the current interrupt mask. */                                  \
-        "st     r3, [r1]+ 64            \n" /* Store the interrupt mask on the stack. */                            \
-        "ld     r2, [r0]+short(pxCurrentTCB)    \n" /* Load the pointer to the TCB. */                              \
-        "st     r1, [r2]                \n" /* Save the stack pointer into the TCB. */                              \
-        "mov    r14, r1                 \n" /* Compiler expects r14 to be set to the function stack. */             \
+#define portSAVE_CONTEXT()                                                                                      \
+    asm __volatile__                                                                                            \
+    (                                                                                                           \
+        "sub    r1, #68                 \n" /* Make space on the stack for the context. */                      \
+        "std    r2, [r1] +  0           \n"                                                                     \
+        "stq    r4, [r1] +  8           \n"                                                                     \
+        "stq    r8, [r1] +  24          \n"                                                                     \
+        "stq    r12, [r1] + 40          \n"                                                                     \
+        "mov    r6, rtt                 \n"                                                                     \
+        "mov    r7, psr                 \n"                                                                     \
+        "std    r6, [r1] +  56          \n"                                                                     \
+        "movhi  r2, #16384              \n"         /* Set the pointer to the IC. */                            \
+        "ldub   r3, [r2] + 2            \n"         /* Load the current interrupt mask. */                      \
+        "st     r3, [r1]+ 64            \n"         /* Store the interrupt mask on the stack. */                \
+        "ld     r2, [r0]+short(pxCurrentTCB)    \n" /* Load the pointer to the TCB. */                          \
+        "st     r1, [r2]                \n"         /* Save the stack pointer into the TCB. */                  \
+        "mov    r14, r1                 \n"         /* Compiler expects r14 to be set to the function stack. */ \
     );
 /*---------------------------------------------------------------------------*/
 
-#define portRESTORE_CONTEXT()                                                                                       \
-    asm __volatile__(                                                                                               \
-        "ld     r2, [r0]+short(pxCurrentTCB)    \n" /* Load the TCB to find the stack pointer and context. */       \
-        "ld     r1, [r2]                \n"                                                                         \
-        "movhi  r2, #16384              \n" /* Set the pointer to the IC. */                                        \
-        "ld     r3, [r1] + 64           \n" /* Load the previous interrupt mask. */                                 \
-        "stb    r3, [r2] + 2            \n" /* Set the current interrupt mask to be the previous. */                \
-        "ldd    r6, [r1] + 56           \n" /* Restore context. */                                                  \
-        "mov    rtt, r6                 \n"                                                                         \
-        "mov    psr, r7                 \n"                                                                         \
-        "ldd    r2, [r1] + 0            \n"                                                                         \
-        "ldq    r4, [r1] +  8           \n"                                                                         \
-        "ldq    r8, [r1] +  24          \n"                                                                         \
-        "ldq    r12, [r1] + 40          \n"                                                                         \
-        "add    r1, #68                 \n"                                                                         \
-        "rti                            \n"                                                                         \
-     );
+#define portRESTORE_CONTEXT()                                                                                 \
+    asm __volatile__ (                                                                                        \
+        "ld     r2, [r0]+short(pxCurrentTCB)    \n" /* Load the TCB to find the stack pointer and context. */ \
+        "ld     r1, [r2]                \n"                                                                   \
+        "movhi  r2, #16384              \n"         /* Set the pointer to the IC. */                          \
+        "ld     r3, [r1] + 64           \n"         /* Load the previous interrupt mask. */                   \
+        "stb    r3, [r2] + 2            \n"         /* Set the current interrupt mask to be the previous. */  \
+        "ldd    r6, [r1] + 56           \n"         /* Restore context. */                                    \
+        "mov    rtt, r6                 \n"                                                                   \
+        "mov    psr, r7                 \n"                                                                   \
+        "ldd    r2, [r1] + 0            \n"                                                                   \
+        "ldq    r4, [r1] +  8           \n"                                                                   \
+        "ldq    r8, [r1] +  24          \n"                                                                   \
+        "ldq    r12, [r1] + 40          \n"                                                                   \
+        "add    r1, #68                 \n"                                                                   \
+        "rti                            \n"                                                                   \
+        );
 
 /*---------------------------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 /*---------------------------------------------------------------------------*/
 
 /* *INDENT-OFF* */
diff --git a/portable/GCC/ColdFire_V2/port.c b/portable/GCC/ColdFire_V2/port.c
index cbf569384..f35126df8 100644
--- a/portable/GCC/ColdFire_V2/port.c
+++ b/portable/GCC/ColdFire_V2/port.c
@@ -30,23 +30,25 @@
 #include "FreeRTOS.h"
 #include "task.h"
 
-#define portINITIAL_FORMAT_VECTOR       ( ( StackType_t ) 0x4000 )
+#define portINITIAL_FORMAT_VECTOR      ( ( StackType_t ) 0x4000 )
 
 /* Supervisor mode set. */
-#define portINITIAL_STATUS_REGISTER     ( ( StackType_t ) 0x2000)
+#define portINITIAL_STATUS_REGISTER    ( ( StackType_t ) 0x2000 )
 
 /* Used to keep track of the number of nested calls to taskENTER_CRITICAL().  This
-will be set to 0 prior to the first task being started. */
+ * will be set to 0 prior to the first task being started. */
 static uint32_t ulCriticalNesting = 0x9999UL;
 
 /*-----------------------------------------------------------*/
 
-StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
     *pxTopOfStack = ( StackType_t ) pvParameters;
     pxTopOfStack--;
 
-    *pxTopOfStack = (StackType_t) 0xDEADBEEF;
+    *pxTopOfStack = ( StackType_t ) 0xDEADBEEF;
     pxTopOfStack--;
 
     /* Exception stack frame starts with the return address. */
@@ -57,7 +59,7 @@ StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t p
     pxTopOfStack--;
 
     *pxTopOfStack = ( StackType_t ) 0x0; /*FP*/
-    pxTopOfStack -= 14; /* A5 to D0. */
+    pxTopOfStack -= 14;                  /* A5 to D0. */
 
     return pxTopOfStack;
 }
@@ -65,7 +67,7 @@ StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t p
 
 BaseType_t xPortStartScheduler( void )
 {
-extern void vPortStartFirstTask( void );
+    extern void vPortStartFirstTask( void );
 
     ulCriticalNesting = 0UL;
 
@@ -90,19 +92,20 @@ void vPortEnterCritical( void )
     if( ulCriticalNesting == 0UL )
     {
         /* Guard against context switches being pended simultaneously with a
-        critical section being entered. */
+         * critical section being entered. */
         do
         {
             portDISABLE_INTERRUPTS();
+
             if( MCF_INTC0_INTFRCL == 0UL )
             {
                 break;
             }
 
             portENABLE_INTERRUPTS();
-
         } while( 1 );
     }
+
     ulCriticalNesting++;
 }
 /*-----------------------------------------------------------*/
@@ -110,6 +113,7 @@ void vPortEnterCritical( void )
 void vPortExitCritical( void )
 {
     ulCriticalNesting--;
+
     if( ulCriticalNesting == 0 )
     {
         portENABLE_INTERRUPTS();
@@ -119,11 +123,11 @@ void vPortExitCritical( void )
 
 void vPortYieldHandler( void )
 {
-uint32_t ulSavedInterruptMask;
+    uint32_t ulSavedInterruptMask;
 
     ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR();
-        /* Note this will clear all forced interrupts - this is done for speed. */
-        MCF_INTC0_INTFRCL = 0;
-        vTaskSwitchContext();
+    /* Note this will clear all forced interrupts - this is done for speed. */
+    MCF_INTC0_INTFRCL = 0;
+    vTaskSwitchContext();
     portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask );
 }
diff --git a/portable/GCC/ColdFire_V2/portmacro.h b/portable/GCC/ColdFire_V2/portmacro.h
index 06ddbd887..c1df5e9c8 100644
--- a/portable/GCC/ColdFire_V2/portmacro.h
+++ b/portable/GCC/ColdFire_V2/portmacro.h
@@ -46,33 +46,33 @@
  */
 
 /* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint32_t
-#define portBASE_TYPE   long
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY ( TickType_t )    ( 0xFFFFFFFFUL )
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) ( 0xFFFFFFFFUL )
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portBYTE_ALIGNMENT          4
-#define portSTACK_GROWTH            -1
-#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT    4
+#define portSTACK_GROWTH      -1
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
 /*-----------------------------------------------------------*/
 uint32_t ulPortSetIPL( uint32_t );
 #define portDISABLE_INTERRUPTS()    ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY )
@@ -81,31 +81,31 @@ uint32_t ulPortSetIPL( uint32_t );
 
 extern void vPortEnterCritical( void );
 extern void vPortExitCritical( void );
-#define portENTER_CRITICAL()        vPortEnterCritical()
-#define portEXIT_CRITICAL()         vPortExitCritical()
+#define portENTER_CRITICAL()    vPortEnterCritical()
+#define portEXIT_CRITICAL()     vPortExitCritical()
 
 extern UBaseType_t uxPortSetInterruptMaskFromISR( void );
 extern void vPortClearInterruptMaskFromISR( UBaseType_t );
-#define portSET_INTERRUPT_MASK_FROM_ISR()   ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY )
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) ulPortSetIPL( uxSavedStatusRegister )
+#define portSET_INTERRUPT_MASK_FROM_ISR()                             ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister )    ulPortSetIPL( uxSavedStatusRegister )
 
 /*-----------------------------------------------------------*/
 
 /* Task utilities. */
 
-#define portNOP()   asm volatile (  "nop" )
+#define portNOP()      asm volatile ( "nop" )
 
 /* Note this will overwrite all other bits in the force register, it is done this way for speed. */
-#define portYIELD()         MCF_INTC0_INTFRCL = ( 1UL << configYIELD_INTERRUPT_VECTOR ); portNOP(); portNOP()
+#define portYIELD()    MCF_INTC0_INTFRCL = ( 1UL << configYIELD_INTERRUPT_VECTOR ); portNOP(); portNOP()
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn))
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters ) __attribute__( ( noreturn ) )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 /*-----------------------------------------------------------*/
 
-#define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired != pdFALSE ) { portYIELD(); } } while( 0 )
+#define portEND_SWITCHING_ISR( xSwitchRequired )              do { if( xSwitchRequired != pdFALSE ) { portYIELD(); } } while( 0 )
 
 
 /* *INDENT-OFF* */
diff --git a/portable/GCC/H8S2329/port.c b/portable/GCC/H8S2329/port.c
index 660cb81e1..7aec16f6c 100644
--- a/portable/GCC/H8S2329/port.c
+++ b/portable/GCC/H8S2329/port.c
@@ -32,22 +32,22 @@
 
 
 /*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the H8S port.
- *----------------------------------------------------------*/
+* Implementation of functions defined in portable.h for the H8S port.
+*----------------------------------------------------------*/
 
 
 /*-----------------------------------------------------------*/
 
 /* When the task starts interrupts should be enabled. */
-#define portINITIAL_CCR         ( ( StackType_t ) 0x00 )
+#define portINITIAL_CCR                    ( ( StackType_t ) 0x00 )
 
 /* Hardware specific constants used to generate the RTOS tick from the TPU. */
-#define portCLEAR_ON_TGRA_COMPARE_MATCH ( ( uint8_t ) 0x20 )
-#define portCLOCK_DIV_64                ( ( uint8_t ) 0x03 )
-#define portCLOCK_DIV                   ( ( uint32_t ) 64 )
-#define portTGRA_INTERRUPT_ENABLE       ( ( uint8_t ) 0x01 )
-#define portTIMER_CHANNEL               ( ( uint8_t ) 0x02 )
-#define portMSTP13                      ( ( uint16_t ) 0x2000 )
+#define portCLEAR_ON_TGRA_COMPARE_MATCH    ( ( uint8_t ) 0x20 )
+#define portCLOCK_DIV_64                   ( ( uint8_t ) 0x03 )
+#define portCLOCK_DIV                      ( ( uint32_t ) 64 )
+#define portTGRA_INTERRUPT_ENABLE          ( ( uint8_t ) 0x01 )
+#define portTIMER_CHANNEL                  ( ( uint8_t ) 0x02 )
+#define portMSTP13                         ( ( uint16_t ) 0x2000 )
 
 /*
  * Setup TPU channel one for the RTOS tick at the requested frequency.
@@ -57,26 +57,29 @@ static void prvSetupTimerInterrupt( void );
 /*
  * The ISR used by portYIELD(). This is installed as a trap handler.
  */
-void vPortYield( void ) __attribute__ ( ( saveall, interrupt_handler ) );
+void vPortYield( void ) __attribute__( ( saveall, interrupt_handler ) );
 
 /*-----------------------------------------------------------*/
 
 /*
  * See header file for description.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
-uint32_t ulValue;
+    uint32_t ulValue;
 
     /* This requires an even address. */
     ulValue = ( uint32_t ) pxTopOfStack;
+
     if( ulValue & 1UL )
     {
         pxTopOfStack = pxTopOfStack - 1;
     }
 
     /* Place a few bytes of known values on the bottom of the stack.
-    This is just useful for debugging. */
+     * This is just useful for debugging. */
     pxTopOfStack--;
     *pxTopOfStack = 0xaa;
     pxTopOfStack--;
@@ -87,7 +90,7 @@ uint32_t ulValue;
     *pxTopOfStack = 0xdd;
 
     /* The initial stack mimics an interrupt stack.  First there is the program
-    counter (24 bits). */
+     * counter (24 bits). */
     ulValue = ( uint32_t ) pxCode;
 
     pxTopOfStack--;
@@ -104,8 +107,8 @@ uint32_t ulValue;
     *pxTopOfStack = portINITIAL_CCR;
 
     /* Next all the general purpose registers - with the parameters being passed
-    in ER0.  The parameter order must match that used by the compiler when the
-    "saveall" function attribute is used. */
+     * in ER0.  The parameter order must match that used by the compiler when the
+     * "saveall" function attribute is used. */
 
     /* ER6 */
     pxTopOfStack--;
@@ -188,22 +191,22 @@ uint32_t ulValue;
 
 BaseType_t xPortStartScheduler( void )
 {
-extern void * pxCurrentTCB;
+    extern void * pxCurrentTCB;
 
     /* Setup the hardware to generate the tick. */
     prvSetupTimerInterrupt();
 
     /* Restore the context of the first task that is going to run.  This
-    mirrors the function epilogue code generated by the compiler when the
-    "saveall" function attribute is used. */
+     * mirrors the function epilogue code generated by the compiler when the
+     * "saveall" function attribute is used. */
     asm volatile (
-                    "MOV.L      @_pxCurrentTCB, ER6         \n\t"
-                    "MOV.L      @ER6, ER7                   \n\t"
-                    "LDM.L      @SP+, (ER4-ER5)             \n\t"
-                    "LDM.L      @SP+, (ER0-ER3)             \n\t"
-                    "MOV.L      @ER7+, ER6                  \n\t"
-                    "RTE                                    \n\t"
-                );
+        "MOV.L      @_pxCurrentTCB, ER6         \n\t"
+        "MOV.L      @ER6, ER7                   \n\t"
+        "LDM.L      @SP+, (ER4-ER5)             \n\t"
+        "LDM.L      @SP+, (ER0-ER3)             \n\t"
+        "MOV.L      @ER7+, ER6                  \n\t"
+        "RTE                                    \n\t"
+        );
 
     ( void ) pxCurrentTCB;
 
@@ -226,7 +229,7 @@ void vPortEndScheduler( void )
 void vPortYield( void )
 {
     portSAVE_STACK_POINTER();
-        vTaskSwitchContext();
+    vTaskSwitchContext();
     portRESTORE_STACK_POINTER();
 }
 /*-----------------------------------------------------------*/
@@ -235,14 +238,14 @@ void vPortYield( void )
  * The interrupt handler installed for the RTOS tick depends on whether the
  * preemptive or cooperative scheduler is being used.
  */
-#if( configUSE_PREEMPTION == 1 )
+#if ( configUSE_PREEMPTION == 1 )
 
-    /*
-     * The preemptive scheduler is used so the ISR calls vTaskSwitchContext().
-     * The function prologue saves the context so all we have to do is save
-     * the stack pointer.
-     */
-    void vTickISR( void ) __attribute__ ( ( saveall, interrupt_handler ) );
+/*
+ * The preemptive scheduler is used so the ISR calls vTaskSwitchContext().
+ * The function prologue saves the context so all we have to do is save
+ * the stack pointer.
+ */
+    void vTickISR( void ) __attribute__( ( saveall, interrupt_handler ) );
     void vTickISR( void )
     {
         portSAVE_STACK_POINTER();
@@ -258,14 +261,14 @@ void vPortYield( void )
         portRESTORE_STACK_POINTER();
     }
 
-#else
+#else /* if ( configUSE_PREEMPTION == 1 ) */
 
-    /*
-     * The cooperative scheduler is being used so all we have to do is
-     * periodically increment the tick.  This can just be a normal ISR and
-     * the "saveall" attribute is not required.
-     */
-    void vTickISR( void ) __attribute__ ( ( interrupt_handler ) );
+/*
+ * The cooperative scheduler is being used so all we have to do is
+ * periodically increment the tick.  This can just be a normal ISR and
+ * the "saveall" attribute is not required.
+ */
+    void vTickISR( void ) __attribute__( ( interrupt_handler ) );
     void vTickISR( void )
     {
         xTaskIncrementTick();
@@ -274,7 +277,7 @@ void vPortYield( void )
         TSR1 &= ~0x01;
     }
 
-#endif
+#endif /* if ( configUSE_PREEMPTION == 1 ) */
 /*-----------------------------------------------------------*/
 
 /*
@@ -282,7 +285,7 @@ void vPortYield( void )
  */
 static void prvSetupTimerInterrupt( void )
 {
-const uint32_t ulCompareMatch = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) / portCLOCK_DIV;
+    const uint32_t ulCompareMatch = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) / portCLOCK_DIV;
 
     /* Turn the module on. */
     MSTPCR &= ~portMSTP13;
@@ -294,7 +297,7 @@ const uint32_t ulCompareMatch = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) / po
     TGR1A = ulCompareMatch;
 
     /* Start the timer and enable the interrupt - we can do this here as
-    interrupts are globally disabled when this function is called. */
+     * interrupts are globally disabled when this function is called. */
     TIER1 |= portTGRA_INTERRUPT_ENABLE;
     TSTR |= portTIMER_CHANNEL;
 }
diff --git a/portable/GCC/H8S2329/portmacro.h b/portable/GCC/H8S2329/portmacro.h
index a5612cadf..4b4e1cdac 100644
--- a/portable/GCC/H8S2329/portmacro.h
+++ b/portable/GCC/H8S2329/portmacro.h
@@ -47,93 +47,94 @@
  */
 
 /* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint8_t
-#define portBASE_TYPE   char
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint8_t
+#define portBASE_TYPE     char
 
-typedef portSTACK_TYPE StackType_t;
-typedef signed char BaseType_t;
-typedef unsigned char UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef signed char      BaseType_t;
+typedef unsigned char    UBaseType_t;
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY ( TickType_t )    ( 0xFFFFFFFFUL )
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) ( 0xFFFFFFFFUL )
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portBYTE_ALIGNMENT          2
-#define portSTACK_GROWTH            ( -1 )
-#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portYIELD()                 asm volatile( "TRAPA #0" )
-#define portNOP()                   asm volatile( "NOP" )
+#define portBYTE_ALIGNMENT    2
+#define portSTACK_GROWTH      ( -1 )
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portYIELD()    asm volatile ( "TRAPA #0" )
+#define portNOP()      asm volatile ( "NOP" )
 /*-----------------------------------------------------------*/
 
 /* Critical section handling. */
-#define portENABLE_INTERRUPTS()     asm volatile( "ANDC #0x7F, CCR" );
-#define portDISABLE_INTERRUPTS()    asm volatile( "ORC  #0x80, CCR" );
+#define portENABLE_INTERRUPTS()     asm volatile ( "ANDC #0x7F, CCR" );
+#define portDISABLE_INTERRUPTS()    asm volatile ( "ORC  #0x80, CCR" );
 
 /* Push the CCR then disable interrupts. */
-#define portENTER_CRITICAL()        asm volatile( "STC  CCR, @-ER7" ); \
-                                    portDISABLE_INTERRUPTS();
+#define portENTER_CRITICAL()            \
+    asm volatile ( "STC  CCR, @-ER7" ); \
+    portDISABLE_INTERRUPTS();
 
 /* Pop the CCR to set the interrupt masking back to its previous state. */
-#define  portEXIT_CRITICAL()        asm volatile( "LDC  @ER7+, CCR" );
+#define  portEXIT_CRITICAL()    asm volatile ( "LDC  @ER7+, CCR" );
 /*-----------------------------------------------------------*/
 
 /* Task utilities. */
 
 /* Context switch macros.  These macros are very simple as the context
-is saved simply by selecting the saveall attribute of the context switch
-interrupt service routines.  These macros save and restore the stack
-pointer to the TCB. */
+ * is saved simply by selecting the saveall attribute of the context switch
+ * interrupt service routines.  These macros save and restore the stack
+ * pointer to the TCB. */
 
-#define portSAVE_STACK_POINTER()                                \
-extern void* pxCurrentTCB;                                      \
-                                                                \
-    asm volatile(                                               \
-                    "MOV.L  @_pxCurrentTCB, ER5         \n\t"   \
-                    "MOV.L  ER7, @ER5                   \n\t"   \
-                );                                              \
+#define portSAVE_STACK_POINTER()                  \
+    extern void * pxCurrentTCB;                   \
+                                                  \
+    asm volatile (                                \
+        "MOV.L  @_pxCurrentTCB, ER5         \n\t" \
+        "MOV.L  ER7, @ER5                   \n\t" \
+        );                                        \
     ( void ) pxCurrentTCB;
 
 
-#define portRESTORE_STACK_POINTER()                             \
-extern void* pxCurrentTCB;                                      \
-                                                                \
-    asm volatile(                                               \
-                    "MOV.L  @_pxCurrentTCB, ER5         \n\t"   \
-                    "MOV.L  @ER5, ER7                   \n\t"   \
-                );                                              \
+#define portRESTORE_STACK_POINTER()               \
+    extern void * pxCurrentTCB;                   \
+                                                  \
+    asm volatile (                                \
+        "MOV.L  @_pxCurrentTCB, ER5         \n\t" \
+        "MOV.L  @ER5, ER7                   \n\t" \
+        );                                        \
     ( void ) pxCurrentTCB;
 
 /*-----------------------------------------------------------*/
 
 /* Macros to allow a context switch from within an application ISR. */
 
-#define portENTER_SWITCHING_ISR() portSAVE_STACK_POINTER(); {
-
-#define portEXIT_SWITCHING_ISR( x )                         \
-    if( x )                                                 \
-    {                                                       \
-        extern void vTaskSwitchContext( void );             \
-        vTaskSwitchContext();                               \
-    }                                                       \
-    } portRESTORE_STACK_POINTER();
+#define portENTER_SWITCHING_ISR()    portSAVE_STACK_POINTER(); {
+#define portEXIT_SWITCHING_ISR( x )             \
+    if( x )                                     \
+    {                                           \
+        extern void vTaskSwitchContext( void ); \
+        vTaskSwitchContext();                   \
+    }                                           \
+}                                               \
+    portRESTORE_STACK_POINTER();
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/GCC/HCS12/port.c b/portable/GCC/HCS12/port.c
index 8ee3e10de..e53a74a38 100644
--- a/portable/GCC/HCS12/port.c
+++ b/portable/GCC/HCS12/port.c
@@ -36,8 +36,8 @@
 #include <sys/ports_def.h>
 
 /*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the HCS12 port.
- *----------------------------------------------------------*/
+* Implementation of functions defined in portable.h for the HCS12 port.
+*----------------------------------------------------------*/
 
 
 /*
@@ -47,45 +47,45 @@
 static void prvSetupTimerInterrupt( void );
 
 /* NOTE: Interrupt service routines must be in non-banked memory - as does the
-scheduler startup function. */
-#define ATTR_NEAR   __attribute__((near))
+ * scheduler startup function. */
+#define ATTR_NEAR    __attribute__( ( near ) )
 
 /* Manual context switch function.  This is the SWI ISR. */
-// __attribute__((interrupt))
+/* __attribute__((interrupt)) */
 void ATTR_NEAR vPortYield( void );
 
 /* Tick context switch function.  This is the timer ISR. */
-// __attribute__((interrupt))
+/* __attribute__((interrupt)) */
 void ATTR_NEAR vPortTickInterrupt( void );
 
 /* Function in non-banked memory which actually switches to first task. */
 BaseType_t ATTR_NEAR xStartSchedulerNear( void );
 
 /* Calls to portENTER_CRITICAL() can be nested.  When they are nested the
-critical section should not be left (i.e. interrupts should not be re-enabled)
-until the nesting depth reaches 0.  This variable simply tracks the nesting
-depth.  Each task maintains it's own critical nesting depth variable so
-uxCriticalNesting is saved and restored from the task stack during a context
-switch. */
-volatile UBaseType_t uxCriticalNesting = 0x80;  // un-initialized
+ * critical section should not be left (i.e. interrupts should not be re-enabled)
+ * until the nesting depth reaches 0.  This variable simply tracks the nesting
+ * depth.  Each task maintains it's own critical nesting depth variable so
+ * uxCriticalNesting is saved and restored from the task stack during a context
+ * switch. */
+volatile UBaseType_t uxCriticalNesting = 0x80; /* un-initialized */
 
 /*-----------------------------------------------------------*/
 
 /*
  * See header file for description.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
-
-
     /* Setup the initial stack of the task.  The stack is set exactly as
-    expected by the portRESTORE_CONTEXT() macro.  In this case the stack as
-    expected by the HCS12 RTI instruction. */
+     * expected by the portRESTORE_CONTEXT() macro.  In this case the stack as
+     * expected by the HCS12 RTI instruction. */
 
 
     /* The address of the task function is placed in the stack byte at a time. */
-    *pxTopOfStack   = ( StackType_t ) *( ((StackType_t *) (&pxCode) ) + 1 );
-    *--pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pxCode) ) + 0 );
+    *pxTopOfStack = ( StackType_t ) *( ( ( StackType_t * ) ( &pxCode ) ) + 1 );
+    *--pxTopOfStack = ( StackType_t ) *( ( ( StackType_t * ) ( &pxCode ) ) + 0 );
 
     /* Next are all the registers that form part of the task context. */
 
@@ -98,32 +98,32 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
     *--pxTopOfStack = ( StackType_t ) 0xcc;
 
     /* A register contains parameter high byte. */
-    *--pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pvParameters) ) + 0 );
+    *--pxTopOfStack = ( StackType_t ) *( ( ( StackType_t * ) ( &pvParameters ) ) + 0 );
 
     /* B register contains parameter low byte. */
-    *--pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pvParameters) ) + 1 );
+    *--pxTopOfStack = ( StackType_t ) *( ( ( StackType_t * ) ( &pvParameters ) ) + 1 );
 
     /* CCR: Note that when the task starts interrupts will be enabled since
-    "I" bit of CCR is cleared */
-    *--pxTopOfStack = ( StackType_t ) 0x80;     // keeps Stop disabled (MCU default)
+     * "I" bit of CCR is cleared */
+    *--pxTopOfStack = ( StackType_t ) 0x80; /* keeps Stop disabled (MCU default) */
 
     /* tmp softregs used by GCC. Values right now don't matter. */
-    __asm("\n\
+    __asm( "\n\
         movw _.frame, 2,-%0                         \n\
         movw _.tmp, 2,-%0                           \n\
         movw _.z, 2,-%0                             \n\
         movw _.xy, 2,-%0                            \n\
         ;movw _.d2, 2,-%0                           \n\
         ;movw _.d1, 2,-%0                           \n\
-    ": "=A"(pxTopOfStack) : "0"(pxTopOfStack) );
+    " : "=A" ( pxTopOfStack ) : "0" ( pxTopOfStack ) );
 
     #ifdef BANKED_MODEL
         /* The page of the task. */
-        *--pxTopOfStack = 0x30;      // can only directly start in PPAGE 0x30
+        *--pxTopOfStack = 0x30; /* can only directly start in PPAGE 0x30 */
     #endif
 
     /* The critical nesting depth is initialised with 0 (meaning not in
-    a critical section). */
+     * a critical section). */
     *--pxTopOfStack = ( StackType_t ) 0x00;
 
 
@@ -141,21 +141,22 @@ static void prvSetupTimerInterrupt( void )
 {
     /* Enable hardware RTI timer */
     /* Ignores configTICK_RATE_HZ */
-    RTICTL = 0x50;          // 16 MHz xtal: 976.56 Hz, 1024mS
-    CRGINT |= 0x80;         // RTIE
+    RTICTL = 0x50;  /* 16 MHz xtal: 976.56 Hz, 1024mS */
+    CRGINT |= 0x80; /* RTIE */
 }
 /*-----------------------------------------------------------*/
 
 BaseType_t xPortStartScheduler( void )
 {
     /* xPortStartScheduler() does not start the scheduler directly because
-    the header file containing the xPortStartScheduler() prototype is part
-    of the common kernel code, and therefore cannot use the CODE_SEG pragma.
-    Instead it simply calls the locally defined xNearStartScheduler() -
-    which does use the CODE_SEG pragma. */
+     * the header file containing the xPortStartScheduler() prototype is part
+     * of the common kernel code, and therefore cannot use the CODE_SEG pragma.
+     * Instead it simply calls the locally defined xNearStartScheduler() -
+     * which does use the CODE_SEG pragma. */
 
     int16_t register d;
-    __asm ("jmp  xStartSchedulerNear        ; will never return": "=d"(d));
+
+    __asm( "jmp  xStartSchedulerNear        ; will never return" : "=d" ( d ) );
     return d;
 }
 /*-----------------------------------------------------------*/
@@ -163,7 +164,7 @@ BaseType_t xPortStartScheduler( void )
 BaseType_t xStartSchedulerNear( void )
 {
     /* Configure the timer that will generate the RTOS tick.  Interrupts are
-    disabled when this function is called. */
+     * disabled when this function is called. */
     prvSetupTimerInterrupt();
 
     /* Restore the context of the first task. */
@@ -187,9 +188,10 @@ BaseType_t xStartSchedulerNear( void )
 void vPortYield( void )
 {
     portISR_HEAD();
+
     /* NOTE: This is the trap routine (swi) although not defined as a trap.
-       It will fill the stack the same way as an ISR in order to mix preemtion
-       and cooperative yield. */
+     * It will fill the stack the same way as an ISR in order to mix preemtion
+     * and cooperative yield. */
 
     portSAVE_CONTEXT();
     vTaskSwitchContext();
@@ -224,14 +226,14 @@ void vPortTickInterrupt( void )
         }
 
         /* Restore the context of a task - which may be a different task
-        to that interrupted. */
+         * to that interrupted. */
         portRESTORE_CONTEXT();
     }
-    #else
+    #else /* if configUSE_PREEMPTION == 1 */
     {
         xTaskIncrementTick();
     }
-    #endif
+    #endif /* if configUSE_PREEMPTION == 1 */
 
     portISR_TAIL();
 }
diff --git a/portable/GCC/HCS12/portmacro.h b/portable/GCC/HCS12/portmacro.h
index a11b96c37..37034a036 100644
--- a/portable/GCC/HCS12/portmacro.h
+++ b/portable/GCC/HCS12/portmacro.h
@@ -47,40 +47,40 @@
  */
 
 /* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint8_t
-#define portBASE_TYPE   char
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint8_t
+#define portBASE_TYPE     char
 
-typedef portSTACK_TYPE StackType_t;
-typedef signed char BaseType_t;
-typedef unsigned char UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef signed char      BaseType_t;
+typedef unsigned char    UBaseType_t;
 
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY ( TickType_t )    ( 0xFFFFFFFFUL )
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) ( 0xFFFFFFFFUL )
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portBYTE_ALIGNMENT          1
-#define portSTACK_GROWTH            ( -1 )
-#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portYIELD()                 __asm( "swi" );
+#define portBYTE_ALIGNMENT    1
+#define portSTACK_GROWTH      ( -1 )
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portYIELD()    __asm( "swi" );
 /*-----------------------------------------------------------*/
 
 /* Critical section handling. */
-#define portENABLE_INTERRUPTS()             __asm( "cli" )
-#define portDISABLE_INTERRUPTS()            __asm( "sei" )
+#define portENABLE_INTERRUPTS()     __asm( "cli" )
+#define portDISABLE_INTERRUPTS()    __asm( "sei" )
 
 /*
  * Disable interrupts before incrementing the count of critical section nesting.
@@ -88,29 +88,29 @@ typedef unsigned char UBaseType_t;
  * re-enabled.  Once interrupts are disabled the nesting count can be accessed
  * directly.  Each task maintains its own nesting count.
  */
-#define portENTER_CRITICAL()                                    \
-{                                                               \
-    extern volatile UBaseType_t uxCriticalNesting;  \
-                                                                \
-    portDISABLE_INTERRUPTS();                                   \
-    uxCriticalNesting++;                                        \
-}
+#define portENTER_CRITICAL()                           \
+    {                                                  \
+        extern volatile UBaseType_t uxCriticalNesting; \
+                                                       \
+        portDISABLE_INTERRUPTS();                      \
+        uxCriticalNesting++;                           \
+    }
 
 /*
  * Interrupts are disabled so we can access the nesting count directly.  If the
  * nesting is found to be 0 (no nesting) then we are leaving the critical
  * section and interrupts can be re-enabled.
  */
-#define  portEXIT_CRITICAL()                                    \
-{                                                               \
-    extern volatile UBaseType_t uxCriticalNesting;  \
-                                                                \
-    uxCriticalNesting--;                                        \
-    if( uxCriticalNesting == 0 )                                \
-    {                                                           \
-        portENABLE_INTERRUPTS();                                \
-    }                                                           \
-}
+#define  portEXIT_CRITICAL()                           \
+    {                                                  \
+        extern volatile UBaseType_t uxCriticalNesting; \
+                                                       \
+        uxCriticalNesting--;                           \
+        if( uxCriticalNesting == 0 )                   \
+        {                                              \
+            portENABLE_INTERRUPTS();                   \
+        }                                              \
+    }
 /*-----------------------------------------------------------*/
 
 /* Task utilities. */
@@ -126,13 +126,14 @@ typedef unsigned char UBaseType_t;
  */
 
 #ifdef BANKED_MODEL
-    /*
-     * Load the stack pointer for the task, then pull the critical nesting
-     * count and PPAGE register from the stack.  The remains of the
-     * context are restored by the RTI instruction.
-     */
-    #define portRESTORE_CONTEXT()                           \
-    {                                       \
+
+/*
+ * Load the stack pointer for the task, then pull the critical nesting
+ * count and PPAGE register from the stack.  The remains of the
+ * context are restored by the RTI instruction.
+ */
+    #define portRESTORE_CONTEXT() \
+    {                             \
         __asm( "                                \n\
         .globl pxCurrentTCB         ; void *            \n\
         .globl uxCriticalNesting        ; char              \n\
@@ -142,16 +143,16 @@ typedef unsigned char UBaseType_t;
                                             \n\
         movb 1,sp+,uxCriticalNesting                        \n\
         movb 1,sp+,0x30             ; PPAGE             \n\
-        " );                                    \
+        " );                      \
     }
 
-    /*
-     * By the time this macro is called the processor has already stacked the
-     * registers.  Simply stack the nesting count and PPAGE value, then save
-     * the task stack pointer.
-     */
-    #define portSAVE_CONTEXT()                          \
-    {                                       \
+/*
+ * By the time this macro is called the processor has already stacked the
+ * registers.  Simply stack the nesting count and PPAGE value, then save
+ * the task stack pointer.
+ */
+    #define portSAVE_CONTEXT() \
+    {                          \
         __asm( "                                \n\
         .globl pxCurrentTCB         ; void *            \n\
         .globl uxCriticalNesting        ; char              \n\
@@ -161,17 +162,17 @@ typedef unsigned char UBaseType_t;
                                             \n\
         ldx  pxCurrentTCB                           \n\
         sts  0,x                ; Stack             \n\
-        " );                                    \
+        " );                   \
     }
-#else
+#else /* ifdef BANKED_MODEL */
 
-    /*
-     * These macros are as per the BANKED versions above, but without saving
-     * and restoring the PPAGE register.
-     */
+/*
+ * These macros are as per the BANKED versions above, but without saving
+ * and restoring the PPAGE register.
+ */
 
-    #define portRESTORE_CONTEXT()                           \
-    {                                       \
+    #define portRESTORE_CONTEXT() \
+    {                             \
         __asm( "                                \n\
         .globl pxCurrentTCB         ; void *            \n\
         .globl uxCriticalNesting        ; char              \n\
@@ -180,11 +181,11 @@ typedef unsigned char UBaseType_t;
         lds  0,x                ; Stack             \n\
                                             \n\
         movb 1,sp+,uxCriticalNesting                        \n\
-        " );                                    \
+        " );                      \
     }
 
-    #define portSAVE_CONTEXT()                          \
-    {                                       \
+    #define portSAVE_CONTEXT() \
+    {                          \
         __asm( "                                \n\
         .globl pxCurrentTCB         ; void *            \n\
         .globl uxCriticalNesting        ; char              \n\
@@ -193,29 +194,29 @@ typedef unsigned char UBaseType_t;
                                             \n\
         ldx  pxCurrentTCB                           \n\
         sts  0,x                ; Stack             \n\
-        " );                                    \
+        " );                   \
     }
-#endif
+#endif /* ifdef BANKED_MODEL */
 
 /*
  * Utility macros to save/restore correct software registers for GCC. This is
  * useful when GCC does not generate appropriate ISR head/tail code.
  */
-#define portISR_HEAD()                                  \
-{                                           \
-        __asm("                                 \n\
+#define portISR_HEAD() \
+    {                  \
+        __asm( "                                 \n\
         movw _.frame, 2,-sp                         \n\
         movw _.tmp, 2,-sp                           \n\
         movw _.z, 2,-sp                             \n\
         movw _.xy, 2,-sp                            \n\
         ;movw _.d2, 2,-sp                           \n\
         ;movw _.d1, 2,-sp                           \n\
-        ");                                 \
-}
+        " );           \
+    }
 
-#define portISR_TAIL()                                  \
-{                                           \
-        __asm("                                 \n\
+#define portISR_TAIL() \
+    {                  \
+        __asm( "                                 \n\
         movw 2,sp+, _.xy                            \n\
         movw 2,sp+, _.z                             \n\
         movw 2,sp+, _.tmp                           \n\
@@ -223,8 +224,8 @@ typedef unsigned char UBaseType_t;
         ;movw 2,sp+, _.d1                           \n\
         ;movw 2,sp+, _.d2                           \n\
         rti                                 \n\
-        ");                                 \
-}
+        " );           \
+    }
 
 /*
  * Utility macro to call macros above in correct order in order to perform a
@@ -233,15 +234,15 @@ typedef unsigned char UBaseType_t;
  * variables portYIELD() should be used in it's place.
  */
 
-#define portTASK_SWITCH_FROM_ISR()                              \
-    portSAVE_CONTEXT();                                         \
-    vTaskSwitchContext();                                       \
+#define portTASK_SWITCH_FROM_ISR() \
+    portSAVE_CONTEXT();            \
+    vTaskSwitchContext();          \
     portRESTORE_CONTEXT();
 
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/GCC/IA32_flat/ISR_Support.h b/portable/GCC/IA32_flat/ISR_Support.h
index 6ee4f2412..cecd6a152 100644
--- a/portable/GCC/IA32_flat/ISR_Support.h
+++ b/portable/GCC/IA32_flat/ISR_Support.h
@@ -26,103 +26,106 @@
  *
  */
 
-    .extern ulTopOfSystemStack
-    .extern ulInterruptNesting
+.extern ulTopOfSystemStack
+   .extern ulInterruptNesting
 
 /*-----------------------------------------------------------*/
 
-.macro portFREERTOS_INTERRUPT_ENTRY
+   .macro portFREERTOS_INTERRUPT_ENTRY
 
-    /* Save general purpose registers. */
-    pusha
+/* Save general purpose registers. */
+pusha
 
-    /* If ulInterruptNesting is zero the rest of the task context will need
-    saving and a stack switch might be required. */
-    movl    ulInterruptNesting, %eax
-    test    %eax, %eax
-    jne     2f
+/* If ulInterruptNesting is zero the rest of the task context will need
+ * saving and a stack switch might be required. */
+movl ulInterruptNesting, % eax
+test % eax, % eax
+jne     2f
 
-    /* Interrupts are not nested, so save the rest of the task context. */
-    .if configSUPPORT_FPU == 1
+/* Interrupts are not nested, so save the rest of the task context. */
+   .
 
-        /* If the task has a buffer allocated to save the FPU context then
-        save the FPU context now. */
-        movl    pucPortTaskFPUContextBuffer, %eax
-        test    %eax, %eax
-        je      1f
-        fnsave  ( %eax ) /* Save FLOP context into ucTempFPUBuffer array. */
-        fwait
+   if configSUPPORT_FPU == 1
 
-        1:
-        /* Save the address of the FPU context, if any. */
-        push    pucPortTaskFPUContextBuffer
+/* If the task has a buffer allocated to save the FPU context then
+ * save the FPU context now. */
+movl pucPortTaskFPUContextBuffer, % eax
+test % eax, % eax
+je      1f
+fnsave( % eax ) /* Save FLOP context into ucTempFPUBuffer array. */
+fwait
 
-    .endif /* configSUPPORT_FPU */
+1 :
+/* Save the address of the FPU context, if any. */
+push pucPortTaskFPUContextBuffer
 
-    /* Find the TCB. */
-    movl    pxCurrentTCB, %eax
+   .endif /* configSUPPORT_FPU */
 
-    /* Stack location is first item in the TCB. */
-    movl    %esp, (%eax)
+/* Find the TCB. */
+movl pxCurrentTCB, % eax
 
-    /* Switch stacks. */
-    movl    ulTopOfSystemStack, %esp
-    movl    %esp, %ebp
+/* Stack location is first item in the TCB. */
+     movl % esp, ( % eax )
 
-    2:
-    /* Increment nesting count. */
-    add     $1, ulInterruptNesting
+/* Switch stacks. */
+movl ulTopOfSystemStack, % esp
+movl % esp, % ebp
 
-.endm
+2 :
+/* Increment nesting count. */
+add $1, ulInterruptNesting
+
+   .endm
 /*-----------------------------------------------------------*/
 
-.macro portINTERRUPT_EPILOGUE
+   .macro portINTERRUPT_EPILOGUE
 
-    cli
-    sub     $1, ulInterruptNesting
+cli
+sub $1, ulInterruptNesting
 
-    /* If the nesting has unwound to zero. */
-    movl    ulInterruptNesting, %eax
-    test    %eax, %eax
-    jne     2f
+/* If the nesting has unwound to zero. */
+movl ulInterruptNesting, % eax
+     test % eax, % eax
+     jne     2f
 
-    /* If a yield was requested then select a new TCB now. */
-    movl    ulPortYieldPending, %eax
-    test    %eax, %eax
-    je      1f
-    movl    $0, ulPortYieldPending
-    call    vTaskSwitchContext
+/* If a yield was requested then select a new TCB now. */
+movl ulPortYieldPending, % eax
+     test % eax, % eax
+     je      1f
+movl $0, ulPortYieldPending
+call vTaskSwitchContext
 
-    1:
-    /* Stack location is first item in the TCB. */
-    movl    pxCurrentTCB, %eax
-    movl    (%eax), %esp
+1 :
+/* Stack location is first item in the TCB. */
+movl pxCurrentTCB, % eax movl( % eax ), % esp
 
-    .if configSUPPORT_FPU == 1
+   .
 
-        /* Restore address of task's FPU context buffer. */
-        pop     pucPortTaskFPUContextBuffer
+   if configSUPPORT_FPU == 1
 
-        /* If the task has a buffer allocated in which its FPU context is saved,
-        then restore it now. */
-        movl    pucPortTaskFPUContextBuffer, %eax
-        test    %eax, %eax
-        je      1f
-        frstor  ( %eax )
-        1:
-    .endif
+/* Restore address of task's FPU context buffer. */
+pop pucPortTaskFPUContextBuffer
 
-    2:
-    popa
+/* If the task has a buffer allocated in which its FPU context is saved,
+ * then restore it now. */
+movl pucPortTaskFPUContextBuffer, % eax
+test % eax, % eax
+je      1f
+frstor( % eax )
+1 :
+.endif
 
-.endm
+2 :
+popa
+
+   .endm
 /*-----------------------------------------------------------*/
 
-.macro portFREERTOS_INTERRUPT_EXIT
+   .macro portFREERTOS_INTERRUPT_EXIT
 
-    portINTERRUPT_EPILOGUE
-    /* EOI. */
-    movl    $0x00, (0xFEE000B0)
-    iret
+portINTERRUPT_EPILOGUE
+/* EOI. */
+movl $0x00, ( 0xFEE000B0 )
+iret
 
-.endm
+   .endm
diff --git a/portable/GCC/IA32_flat/port.c b/portable/GCC/IA32_flat/port.c
index 52cac31d2..da1559416 100644
--- a/portable/GCC/IA32_flat/port.c
+++ b/portable/GCC/IA32_flat/port.c
@@ -35,60 +35,60 @@
 
 #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
     /* Check the configuration. */
-    #if( configMAX_PRIORITIES > 32 )
+    #if ( configMAX_PRIORITIES > 32 )
         #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
     #endif
 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 
-#if( configISR_STACK_SIZE < ( configMINIMAL_STACK_SIZE * 2 ) )
+#if ( configISR_STACK_SIZE < ( configMINIMAL_STACK_SIZE * 2 ) )
     #warning configISR_STACK_SIZE is probably too small!
 #endif /* ( configISR_STACK_SIZE < configMINIMAL_STACK_SIZE * 2 ) */
 
-#if( ( configMAX_API_CALL_INTERRUPT_PRIORITY > portMAX_PRIORITY ) || ( configMAX_API_CALL_INTERRUPT_PRIORITY < 2 ) )
+#if ( ( configMAX_API_CALL_INTERRUPT_PRIORITY > portMAX_PRIORITY ) || ( configMAX_API_CALL_INTERRUPT_PRIORITY < 2 ) )
     #error configMAX_API_CALL_INTERRUPT_PRIORITY must be between 2 and 15
 #endif
 
-#if( ( configSUPPORT_FPU == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) )
+#if ( ( configSUPPORT_FPU == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) )
     #error configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 to use this port with an FPU
 #endif
 
 /* A critical section is exited when the critical section nesting count reaches
-this value. */
-#define portNO_CRITICAL_NESTING         ( ( uint32_t ) 0 )
+ * this value. */
+#define portNO_CRITICAL_NESTING          ( ( uint32_t ) 0 )
 
 /* Tasks are not created with a floating point context, but can be given a
-floating point context after they have been created.  A variable is stored as
-part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
-does not have an FPU context, or any other value if the task does have an FPU
-context. */
-#define portNO_FLOATING_POINT_CONTEXT   ( ( StackType_t ) 0 )
+ * floating point context after they have been created.  A variable is stored as
+ * part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
+ * does not have an FPU context, or any other value if the task does have an FPU
+ * context. */
+#define portNO_FLOATING_POINT_CONTEXT    ( ( StackType_t ) 0 )
 
 /* Only the IF bit is set so tasks start with interrupts enabled. */
-#define portINITIAL_EFLAGS              ( 0x200UL )
+#define portINITIAL_EFLAGS               ( 0x200UL )
 
 /* Error interrupts are at the highest priority vectors. */
-#define portAPIC_LVT_ERROR_VECTOR       ( 0xfe )
-#define portAPIC_SPURIOUS_INT_VECTOR    ( 0xff )
+#define portAPIC_LVT_ERROR_VECTOR        ( 0xfe )
+#define portAPIC_SPURIOUS_INT_VECTOR     ( 0xff )
 
 /* EFLAGS bits. */
-#define portEFLAGS_IF                   ( 0x200UL )
+#define portEFLAGS_IF                    ( 0x200UL )
 
 /* FPU context size if FSAVE is used. */
-#define portFPU_CONTEXT_SIZE_BYTES      108
+#define portFPU_CONTEXT_SIZE_BYTES       108
 
 /* The expected size of each entry in the IDT.  Used to check structure packing
- is set correctly. */
-#define portEXPECTED_IDT_ENTRY_SIZE     8
+ * is set correctly. */
+#define portEXPECTED_IDT_ENTRY_SIZE      8
 
 /* Default flags setting for entries in the IDT. */
-#define portIDT_FLAGS                   ( 0x8E )
+#define portIDT_FLAGS                    ( 0x8E )
 
 /* This is the lowest possible ISR vector available to application code. */
-#define portAPIC_MIN_ALLOWABLE_VECTOR   ( 0x20 )
+#define portAPIC_MIN_ALLOWABLE_VECTOR    ( 0x20 )
 
 /* If configASSERT() is defined then the system stack is filled with this value
-to allow for a crude stack overflow check. */
-#define portSTACK_WORD                  ( 0xecececec )
+ * to allow for a crude stack overflow check. */
+#define portSTACK_WORD                   ( 0xecececec )
 /*-----------------------------------------------------------*/
 
 /*
@@ -104,7 +104,9 @@ static void prvTaskExitError( void );
 /*
  * Complete one descriptor in the IDT.
  */
-static void prvSetInterruptGate( uint8_t ucNumber, ISR_Handler_t pxHandlerFunction, uint8_t ucFlags );
+static void prvSetInterruptGate( uint8_t ucNumber,
+                                 ISR_Handler_t pxHandlerFunction,
+                                 uint8_t ucFlags );
 
 /*
  * The default handler installed in each IDT position.
@@ -135,78 +137,82 @@ static BaseType_t prvCheckValidityOfVectorNumber( uint32_t ulVectorNumber );
 /*-----------------------------------------------------------*/
 
 /* A variable is used to keep track of the critical section nesting.  This
-variable must be initialised to a non zero value to ensure interrupts don't
-inadvertently become unmasked before the scheduler starts. It is set to zero
-before the first task starts executing. */
+ * variable must be initialised to a non zero value to ensure interrupts don't
+ * inadvertently become unmasked before the scheduler starts. It is set to zero
+ * before the first task starts executing. */
 volatile uint32_t ulCriticalNesting = 9999UL;
 
 /* A structure used to map the various fields of an IDT entry into separate
-structure members. */
+ * structure members. */
 struct IDTEntry
 {
-    uint16_t usISRLow;              /* Low 16 bits of handler address. */
-    uint16_t usSegmentSelector;     /* Flat model means this is not changed. */
-    uint8_t ucZero;                 /* Must be set to zero. */
-    uint8_t ucFlags;                /* Flags for this entry. */
-    uint16_t usISRHigh;             /* High 16 bits of handler address. */
-} __attribute__( ( packed ) );
+    uint16_t usISRLow;          /* Low 16 bits of handler address. */
+    uint16_t usSegmentSelector; /* Flat model means this is not changed. */
+    uint8_t ucZero;             /* Must be set to zero. */
+    uint8_t ucFlags;            /* Flags for this entry. */
+    uint16_t usISRHigh;         /* High 16 bits of handler address. */
+}
+__attribute__( ( packed ) );
 typedef struct IDTEntry IDTEntry_t;
 
 
 /* Use to pass the location of the IDT to the CPU. */
 struct IDTPointer
 {
-   uint16_t usTableLimit;
-   uint32_t ulTableBase;                /* The address of the first entry in xInterruptDescriptorTable. */
-} __attribute__( ( __packed__ ) );
+    uint16_t usTableLimit;
+    uint32_t ulTableBase; /* The address of the first entry in xInterruptDescriptorTable. */
+}
+__attribute__( ( __packed__ ) );
 typedef struct IDTPointer IDTPointer_t;
 
 /* The IDT itself. */
-static __attribute__ ( ( aligned( 32 ) ) ) IDTEntry_t xInterruptDescriptorTable[ portNUM_VECTORS ];
+static __attribute__( ( aligned( 32 ) ) ) IDTEntry_t xInterruptDescriptorTable[ portNUM_VECTORS ];
 
 #if ( configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1 )
 
-    /* A table in which application defined interrupt handlers are stored.  These
-    are called by the central interrupt handler if a common interrupt entry
-    point it used. */
-    static ISR_Handler_t xInterruptHandlerTable[ portNUM_VECTORS ] = { NULL };
+/* A table in which application defined interrupt handlers are stored.  These
+ * are called by the central interrupt handler if a common interrupt entry
+ * point it used. */
+static ISR_Handler_t xInterruptHandlerTable[ portNUM_VECTORS ] = { NULL };
 
 #endif /* configUSE_COMMON_INTERRUPT_ENTRY_POINT */
 
 #if ( configSUPPORT_FPU == 1 )
 
-    /* Saved as part of the task context.  If pucPortTaskFPUContextBuffer is NULL
-    then the task does not have an FPU context.  If pucPortTaskFPUContextBuffer is
-    not NULL then it points to a buffer into which the FPU context can be saved. */
-    uint8_t *pucPortTaskFPUContextBuffer __attribute__((used)) = pdFALSE;
+/* Saved as part of the task context.  If pucPortTaskFPUContextBuffer is NULL
+ * then the task does not have an FPU context.  If pucPortTaskFPUContextBuffer is
+ * not NULL then it points to a buffer into which the FPU context can be saved. */
+    uint8_t * pucPortTaskFPUContextBuffer __attribute__( ( used ) ) = pdFALSE;
 
 #endif /* configSUPPORT_FPU */
 
 /* The stack used by interrupt handlers. */
-static uint32_t ulSystemStack[ configISR_STACK_SIZE ] __attribute__((used))  = { 0 };
+static uint32_t ulSystemStack[ configISR_STACK_SIZE ] __attribute__( ( used ) ) = { 0 };
 
 /* Don't use the very top of the system stack so the return address
-appears as 0 if the debugger tries to unwind the stack. */
-volatile uint32_t ulTopOfSystemStack __attribute__((used)) = ( uint32_t ) &( ulSystemStack[ configISR_STACK_SIZE - 5 ] );
+ * appears as 0 if the debugger tries to unwind the stack. */
+volatile uint32_t ulTopOfSystemStack __attribute__( ( used ) ) = ( uint32_t ) &( ulSystemStack[ configISR_STACK_SIZE - 5 ] );
 
 /* If a yield is requested from an interrupt or from a critical section then
-the yield is not performed immediately, and ulPortYieldPending is set to pdTRUE
-instead to indicate the yield should be performed at the end of the interrupt
-when the critical section is exited. */
-volatile uint32_t ulPortYieldPending __attribute__((used)) = pdFALSE;
+ * the yield is not performed immediately, and ulPortYieldPending is set to pdTRUE
+ * instead to indicate the yield should be performed at the end of the interrupt
+ * when the critical section is exited. */
+volatile uint32_t ulPortYieldPending __attribute__( ( used ) ) = pdFALSE;
 
 /* Counts the interrupt nesting depth.  Used to know when to switch to the
-interrupt/system stack and when to save/restore a complete context. */
-volatile uint32_t ulInterruptNesting __attribute__((used)) = 0;
+ * interrupt/system stack and when to save/restore a complete context. */
+volatile uint32_t ulInterruptNesting __attribute__( ( used ) ) = 0;
 
 /*-----------------------------------------------------------*/
 
 /*
  * See header file for description.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
-uint32_t ulCodeSegment;
+    uint32_t ulCodeSegment;
 
     /* Setup the initial stack as expected by the portFREERTOS_INTERRUPT_EXIT macro. */
 
@@ -220,7 +226,7 @@ uint32_t ulCodeSegment;
     pxTopOfStack--;
 
     /* There is nothing to return to so assert if attempting to use the return
-    address. */
+     * address. */
     *pxTopOfStack = ( StackType_t ) prvTaskExitError;
     pxTopOfStack--;
 
@@ -229,7 +235,7 @@ uint32_t ulCodeSegment;
     pxTopOfStack--;
 
     /* CS */
-    __asm volatile( "movl %%cs, %0" : "=r" ( ulCodeSegment ) );
+    __asm volatile ( "movl %%cs, %0" : "=r" ( ulCodeSegment ) );
     *pxTopOfStack = ulCodeSegment;
     pxTopOfStack--;
 
@@ -266,7 +272,7 @@ uint32_t ulCodeSegment;
         pxTopOfStack--;
 
         /* Buffer for FPU context, which is initialised to NULL as tasks are not
-        created with an FPU context. */
+         * created with an FPU context. */
         *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
     }
     #endif /* configSUPPORT_FPU */
@@ -275,16 +281,18 @@ uint32_t ulCodeSegment;
 }
 /*-----------------------------------------------------------*/
 
-static void prvSetInterruptGate( uint8_t ucNumber, ISR_Handler_t pxHandlerFunction, uint8_t ucFlags )
+static void prvSetInterruptGate( uint8_t ucNumber,
+                                 ISR_Handler_t pxHandlerFunction,
+                                 uint8_t ucFlags )
 {
-uint16_t usCodeSegment;
-uint32_t ulBase = ( uint32_t ) pxHandlerFunction;
+    uint16_t usCodeSegment;
+    uint32_t ulBase = ( uint32_t ) pxHandlerFunction;
 
     xInterruptDescriptorTable[ ucNumber ].usISRLow = ( uint16_t ) ( ulBase & USHRT_MAX );
     xInterruptDescriptorTable[ ucNumber ].usISRHigh = ( uint16_t ) ( ( ulBase >> 16UL ) & USHRT_MAX );
 
     /* When the flat model is used the CS will never change. */
-    __asm volatile( "mov %%cs, %0" : "=r" ( usCodeSegment ) );
+    __asm volatile ( "mov %%cs, %0" : "=r" ( usCodeSegment ) );
     xInterruptDescriptorTable[ ucNumber ].usSegmentSelector = usCodeSegment;
     xInterruptDescriptorTable[ ucNumber ].ucZero = 0;
     xInterruptDescriptorTable[ ucNumber ].ucFlags = ucFlags;
@@ -293,8 +301,8 @@ uint32_t ulBase = ( uint32_t ) pxHandlerFunction;
 
 void vPortSetupIDT( void )
 {
-uint32_t ulNum;
-IDTPointer_t xIDT;
+    uint32_t ulNum;
+    IDTPointer_t xIDT;
 
     #if ( configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1 )
     {
@@ -314,28 +322,31 @@ IDTPointer_t xIDT;
     xIDT.usTableLimit = sizeof( xInterruptDescriptorTable ) - 1;
 
     /* Set IDT in CPU. */
-    __asm volatile( "lidt %0" :: "m" (xIDT) );
+    __asm volatile ( "lidt %0" ::"m" ( xIDT ) );
 }
 /*-----------------------------------------------------------*/
 
 static void prvTaskExitError( void )
 {
     /* A function that implements a task must not exit or attempt to return to
-    its caller as there is nothing to return to.  If a task wants to exit it
-    should instead call vTaskDelete( NULL ).
-
-    Artificially force an assert() to be triggered if configASSERT() is
-    defined, then stop here so application writers can catch the error. */
+     * its caller as there is nothing to return to.  If a task wants to exit it
+     * should instead call vTaskDelete( NULL ).
+     *
+     * Artificially force an assert() to be triggered if configASSERT() is
+     * defined, then stop here so application writers can catch the error. */
     configASSERT( ulCriticalNesting == ~0UL );
     portDISABLE_INTERRUPTS();
-    for( ;; );
+
+    for( ; ; )
+    {
+    }
 }
 /*-----------------------------------------------------------*/
 
 static void prvSetupTimerInterrupt( void )
 {
-extern void vPortAPICErrorHandlerWrapper( void );
-extern void vPortAPICSpuriousHandler( void );
+    extern void vPortAPICErrorHandlerWrapper( void );
+    extern void vPortAPICSpuriousHandler( void );
 
     /* Initialise LAPIC to a well known state. */
     portAPIC_LDR = 0xFFFFFFFF;
@@ -372,15 +383,15 @@ extern void vPortAPICSpuriousHandler( void );
 
 BaseType_t xPortStartScheduler( void )
 {
-BaseType_t xWord;
+    BaseType_t xWord;
 
     /* Some versions of GCC require the -mno-ms-bitfields command line option
-    for packing to work. */
+     * for packing to work. */
     configASSERT( sizeof( struct IDTEntry ) == portEXPECTED_IDT_ENTRY_SIZE );
 
     /* Fill part of the system stack with a known value to help detect stack
-    overflow.  A few zeros are left so GDB doesn't get confused unwinding
-    the stack. */
+     * overflow.  A few zeros are left so GDB doesn't get confused unwinding
+     * the stack. */
     for( xWord = 0; xWord < configISR_STACK_SIZE - 20; xWord++ )
     {
         ulSystemStack[ xWord ] = portSTACK_WORD;
@@ -404,7 +415,7 @@ BaseType_t xWord;
     portAPIC_TMRDIV = portAPIC_DIV_16;
 
     /* Should not return from the following function as the scheduler will then
-    be executing the tasks. */
+     * be executing the tasks. */
     vPortStartFirstTask();
 
     return 0;
@@ -414,7 +425,7 @@ BaseType_t xWord;
 void vPortEndScheduler( void )
 {
     /* Not implemented in ports where there is nothing to return to.
-    Artificially force an assert. */
+     * Artificially force an assert. */
     configASSERT( ulCriticalNesting == 1000UL );
 }
 /*-----------------------------------------------------------*/
@@ -423,9 +434,9 @@ void vPortEnterCritical( void )
 {
     if( ulCriticalNesting == 0 )
     {
-        #if( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY )
+        #if ( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY )
         {
-            __asm volatile( "cli" );
+            __asm volatile ( "cli" );
         }
         #else
         {
@@ -435,9 +446,9 @@ void vPortEnterCritical( void )
         #endif
     }
 
-    /* Now interrupts are disabled ulCriticalNesting can be accessed
-    directly.  Increment ulCriticalNesting to keep a count of how many times
-    portENTER_CRITICAL() has been called. */
+    /* Now that interrupts are disabled, ulCriticalNesting can be accessed
+     * directly.  Increment ulCriticalNesting to keep a count of how many times
+     * portENTER_CRITICAL() has been called. */
     ulCriticalNesting++;
 }
 /*-----------------------------------------------------------*/
@@ -447,18 +458,18 @@ void vPortExitCritical( void )
     if( ulCriticalNesting > portNO_CRITICAL_NESTING )
     {
         /* Decrement the nesting count as the critical section is being
-        exited. */
+         * exited. */
         ulCriticalNesting--;
 
         /* If the nesting level has reached zero then all interrupt
-        priorities must be re-enabled. */
+         * priorities must be re-enabled. */
         if( ulCriticalNesting == portNO_CRITICAL_NESTING )
         {
             /* Critical nesting has reached zero so all interrupt priorities
-            should be unmasked. */
-            #if( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY )
+             * should be unmasked. */
+            #if ( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY )
             {
-                __asm volatile( "sti" );
+                __asm volatile ( "sti" );
             }
             #else
             {
@@ -467,11 +478,11 @@ void vPortExitCritical( void )
             #endif
 
             /* If a yield was pended from within the critical section then
-            perform the yield now. */
+             * perform the yield now. */
             if( ulPortYieldPending != pdFALSE )
             {
                 ulPortYieldPending = pdFALSE;
-                __asm volatile( portYIELD_INTERRUPT );
+                __asm volatile ( portYIELD_INTERRUPT );
             }
         }
     }
@@ -480,17 +491,17 @@ void vPortExitCritical( void )
 
 uint32_t ulPortSetInterruptMask( void )
 {
-volatile uint32_t ulOriginalMask;
+    volatile uint32_t ulOriginalMask;
 
     /* Set mask to max syscall priority. */
-    #if( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY )
+    #if ( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY )
     {
         /* Return whether interrupts were already enabled or not.  Pop adjusts
-        the stack first. */
-        __asm volatile( "pushf      \t\n"
-                        "pop %0     \t\n"
-                        "cli            "
-                        : "=rm" (ulOriginalMask) :: "memory" );
+         * the stack first. */
+        __asm volatile ( "pushf      \t\n"
+                         "pop %0     \t\n"
+                         "cli            "
+                         : "=rm" ( ulOriginalMask )::"memory" );
 
         ulOriginalMask &= portEFLAGS_IF;
     }
@@ -501,7 +512,7 @@ volatile uint32_t ulOriginalMask;
         portAPIC_TASK_PRIORITY = portMAX_API_CALL_PRIORITY;
         configASSERT( portAPIC_TASK_PRIORITY == portMAX_API_CALL_PRIORITY );
     }
-    #endif
+    #endif /* if ( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY ) */
 
     return ulOriginalMask;
 }
@@ -509,11 +520,11 @@ volatile uint32_t ulOriginalMask;
 
 void vPortClearInterruptMask( uint32_t ulNewMaskValue )
 {
-    #if( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY )
+    #if ( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY )
     {
         if( ulNewMaskValue != pdFALSE )
         {
-            __asm volatile( "sti" );
+            __asm volatile ( "sti" );
         }
     }
     #else
@@ -521,7 +532,7 @@ void vPortClearInterruptMask( uint32_t ulNewMaskValue )
         portAPIC_TASK_PRIORITY = ulNewMaskValue;
         configASSERT( portAPIC_TASK_PRIORITY == ulNewMaskValue );
     }
-    #endif
+    #endif /* if ( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY ) */
 }
 /*-----------------------------------------------------------*/
 
@@ -530,12 +541,12 @@ void vPortClearInterruptMask( uint32_t ulNewMaskValue )
     void vPortTaskUsesFPU( void )
     {
         /* A task is registering the fact that it needs an FPU context.  Allocate a
-        buffer into which the context can be saved. */
+         * buffer into which the context can be saved. */
         pucPortTaskFPUContextBuffer = ( uint8_t * ) pvPortMalloc( portFPU_CONTEXT_SIZE_BYTES );
         configASSERT( pucPortTaskFPUContextBuffer );
 
         /* Initialise the floating point registers. */
-        __asm volatile( "fninit" );
+        __asm volatile ( "fninit" );
     }
 
 #endif /* configSUPPORT_FPU */
@@ -544,7 +555,7 @@ void vPortClearInterruptMask( uint32_t ulNewMaskValue )
 void vPortAPICErrorHandler( void )
 {
 /* Variable to hold the APIC error status for viewing in the debugger. */
-volatile uint32_t ulErrorStatus = 0;
+    volatile uint32_t ulErrorStatus = 0;
 
     portAPIC_ERROR_STATUS = 0;
     ulErrorStatus = portAPIC_ERROR_STATUS;
@@ -555,7 +566,7 @@ volatile uint32_t ulErrorStatus = 0;
 }
 /*-----------------------------------------------------------*/
 
-#if( configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1 )
+#if ( configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1 )
 
     void vPortCentralInterruptHandler( uint32_t ulVector )
     {
@@ -578,17 +589,18 @@ volatile uint32_t ulErrorStatus = 0;
 
 #if ( configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1 )
 
-    BaseType_t xPortRegisterCInterruptHandler( ISR_Handler_t pxHandler, uint32_t ulVectorNumber )
+    BaseType_t xPortRegisterCInterruptHandler( ISR_Handler_t pxHandler,
+                                               uint32_t ulVectorNumber )
     {
-    BaseType_t xReturn;
+        BaseType_t xReturn;
 
         xReturn = prvCheckValidityOfVectorNumber( ulVectorNumber );
 
         if( xReturn != pdFAIL )
         {
             /* Save the handler passed in by the application in the vector number
-            passed in.  The addresses are then called from the central interrupt
-            handler. */
+             * passed in.  The addresses are then called from the central interrupt
+             * handler. */
             xInterruptHandlerTable[ ulVectorNumber ] = pxHandler;
         }
 
@@ -598,9 +610,10 @@ volatile uint32_t ulErrorStatus = 0;
 #endif /* configUSE_COMMON_INTERRUPT_ENTRY_POINT */
 /*-----------------------------------------------------------*/
 
-BaseType_t xPortInstallInterruptHandler( ISR_Handler_t pxHandler, uint32_t ulVectorNumber )
+BaseType_t xPortInstallInterruptHandler( ISR_Handler_t pxHandler,
+                                         uint32_t ulVectorNumber )
 {
-BaseType_t xReturn;
+    BaseType_t xReturn;
 
     xReturn = prvCheckValidityOfVectorNumber( ulVectorNumber );
 
@@ -620,7 +633,7 @@ BaseType_t xReturn;
 
 static BaseType_t prvCheckValidityOfVectorNumber( uint32_t ulVectorNumber )
 {
-BaseType_t xReturn;
+    BaseType_t xReturn;
 
     /* Check validity of vector number. */
     if( ulVectorNumber >= portNUM_VECTORS )
@@ -669,5 +682,5 @@ BaseType_t xReturn;
 
 void vGenerateYieldInterrupt( void )
 {
-    __asm volatile( portYIELD_INTERRUPT );
+    __asm volatile ( portYIELD_INTERRUPT );
 }
diff --git a/portable/GCC/IA32_flat/portmacro.h b/portable/GCC/IA32_flat/portmacro.h
index 3a0cd287c..fd07ee71d 100644
--- a/portable/GCC/IA32_flat/portmacro.h
+++ b/portable/GCC/IA32_flat/portmacro.h
@@ -46,42 +46,42 @@
  */
 
 /* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint32_t
-#define portBASE_TYPE   long
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
-typedef uint32_t TickType_t;
-#define portMAX_DELAY ( ( TickType_t ) 0xffffffffUL )
+typedef uint32_t         TickType_t;
+#define portMAX_DELAY    ( ( TickType_t ) 0xffffffffUL )
 
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portSTACK_GROWTH            ( -1 )
-#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT          32
+#define portSTACK_GROWTH      ( -1 )
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT    32
 
 /*-----------------------------------------------------------*/
 
 /* Task utilities. */
 
 /* The interrupt priority (for vectors 16 to 255) is determined using vector/16.
-The quotient is rounded to the nearest integer with 1 being the lowest priority
-and 15 is the highest.  Therefore the following two interrupts are at the lowest
-priority.  *NOTE 1* If the yield vector is changed then it must also be changed
-in the portYIELD_INTERRUPT definition immediately below. */
+ * The quotient is rounded to the nearest integer with 1 being the lowest priority
+ * and 15 is the highest.  Therefore the following two interrupts are at the lowest
+ * priority.  *NOTE 1* If the yield vector is changed then it must also be changed
+ * in the portYIELD_INTERRUPT definition immediately below. */
 #define portAPIC_TIMER_INT_VECTOR       ( 0x21 )
 #define portAPIC_YIELD_INT_VECTOR       ( 0x20 )
 
 /* Build yield interrupt instruction. */
-#define portYIELD_INTERRUPT "int $0x20"
+#define portYIELD_INTERRUPT             "int $0x20"
 
 /* APIC register addresses. */
 #define portAPIC_EOI                    ( *( ( volatile uint32_t * ) 0xFEE000B0UL ) )
@@ -90,61 +90,61 @@ in the portYIELD_INTERRUPT definition immediately below. */
 #define portAPIC_ENABLE_BIT             ( 1UL << 8UL )
 #define portAPIC_TIMER_PERIODIC         ( 1UL << 17UL )
 #define portAPIC_DISABLE                ( 1UL << 16UL )
-#define portAPIC_NMI                    ( 4 << 8)
+#define portAPIC_NMI                    ( 4 << 8 )
 #define portAPIC_DIV_16                 ( 0x03 )
 
 /* Define local API register addresses. */
-#define portAPIC_ID_REGISTER            ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x20UL  ) ) )
-#define portAPIC_SPURIOUS_INT           ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0xF0UL  ) ) )
+#define portAPIC_ID_REGISTER            ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x20UL ) ) )
+#define portAPIC_SPURIOUS_INT           ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0xF0UL ) ) )
 #define portAPIC_LVT_TIMER              ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x320UL ) ) )
 #define portAPIC_TIMER_INITIAL_COUNT    ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x380UL ) ) )
 #define portAPIC_TIMER_CURRENT_COUNT    ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x390UL ) ) )
-#define portAPIC_TASK_PRIORITY          ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x80UL  ) ) )
+#define portAPIC_TASK_PRIORITY          ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x80UL ) ) )
 #define portAPIC_LVT_ERROR              ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x370UL ) ) )
 #define portAPIC_ERROR_STATUS           ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x280UL ) ) )
-#define portAPIC_LDR                    ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0xD0UL  ) ) )
+#define portAPIC_LDR                    ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0xD0UL ) ) )
 #define portAPIC_TMRDIV                 ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x3E0UL ) ) )
 #define portAPIC_LVT_PERF               ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x340UL ) ) )
 #define portAPIC_LVT_LINT0              ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x350UL ) ) )
 #define portAPIC_LVT_LINT1              ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x360UL ) ) )
 
 /* Don't yield if inside a critical section - instead hold the yield pending
-so it is performed when the critical section is exited. */
-#define portYIELD()                                 \
-{                                                   \
-extern volatile uint32_t ulCriticalNesting;         \
-extern volatile uint32_t ulPortYieldPending;        \
-    if( ulCriticalNesting != 0 )                    \
-    {                                               \
-        ulPortYieldPending = pdTRUE;                \
-    }                                               \
-    else                                            \
-    {                                               \
-        __asm volatile( portYIELD_INTERRUPT );      \
-    }                                               \
-}
+ * so it is performed when the critical section is exited. */
+#define portYIELD()                                  \
+    {                                                \
+        extern volatile uint32_t ulCriticalNesting;  \
+        extern volatile uint32_t ulPortYieldPending; \
+        if( ulCriticalNesting != 0 )                 \
+        {                                            \
+            ulPortYieldPending = pdTRUE;             \
+        }                                            \
+        else                                         \
+        {                                            \
+            __asm volatile ( portYIELD_INTERRUPT );  \
+        }                                            \
+    }
 
 /* Called at the end of an ISR that can cause a context switch - pend a yield if
-xSwithcRequired is not false. */
-#define portEND_SWITCHING_ISR( xSwitchRequired )    \
-{                                                   \
-extern volatile uint32_t ulPortYieldPending;        \
-    if( xSwitchRequired != pdFALSE )                \
-    {                                               \
-        ulPortYieldPending = 1;                     \
-    }                                               \
-}
+ * xSwitchRequired is not false. */
+#define portEND_SWITCHING_ISR( xSwitchRequired )     \
+    {                                                \
+        extern volatile uint32_t ulPortYieldPending; \
+        if( xSwitchRequired != pdFALSE )             \
+        {                                            \
+            ulPortYieldPending = 1;                  \
+        }                                            \
+    }
 
 /* Same as portEND_SWITCHING_ISR() - take your pick which name to use. */
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
 
 /*-----------------------------------------------------------
- * Critical section control
- *----------------------------------------------------------*/
+* Critical section control
+*----------------------------------------------------------*/
 
 /* Critical sections for use in interrupts. */
-#define portSET_INTERRUPT_MASK_FROM_ISR()       ulPortSetInterruptMask()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)    vPortClearInterruptMask( x )
+#define portSET_INTERRUPT_MASK_FROM_ISR()         ulPortSetInterruptMask()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vPortClearInterruptMask( x )
 
 extern void vPortEnterCritical( void );
 extern void vPortExitCritical( void );
@@ -152,139 +152,146 @@ extern uint32_t ulPortSetInterruptMask( void );
 extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
 
 /* These macros do not globally disable/enable interrupts.  They do mask off
-interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
+ * interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
 #define portENTER_CRITICAL()        vPortEnterCritical()
 #define portEXIT_CRITICAL()         vPortExitCritical()
-#define portDISABLE_INTERRUPTS()    __asm volatile( "cli" )
-#define portENABLE_INTERRUPTS()     __asm volatile( "sti" )
+#define portDISABLE_INTERRUPTS()    __asm volatile ( "cli" )
+#define portENABLE_INTERRUPTS()     __asm volatile ( "sti" )
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site.  These are
-not required for this port but included in case common demo code that uses these
-macros is used. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )  void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )    void vFunction( void *pvParameters )
+ * not required for this port but included in case common demo code that uses these
+ * macros is used. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
 /* Architecture specific optimisations. */
 #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
 
-    /* Store/clear the ready priorities in a bit map. */
-    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    \
-        __asm volatile( "bsr %1, %0\n\t"                                    \
-                        :"=r"(uxTopPriority) : "rm"(uxReadyPriorities) : "cc" )
+/* Store/clear the ready priorities in a bit map. */
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) \
+    __asm volatile ( "bsr %1, %0\n\t"                                    \
+                     : "=r" ( uxTopPriority ) : "rm" ( uxReadyPriorities ) : "cc" )
 
-    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 
 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 
-#define portNOP() __asm volatile( "NOP" )
+#define portNOP()    __asm volatile ( "NOP" )
 
 /*-----------------------------------------------------------
- * Misc
- *----------------------------------------------------------*/
+* Misc
+*----------------------------------------------------------*/
 
 #define portNUM_VECTORS     256
 #define portMAX_PRIORITY    15
-typedef void ( *ISR_Handler_t ) ( void );
+typedef void ( * ISR_Handler_t ) ( void );
 
 /* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
-before any floating point instructions are executed. */
+ * before any floating point instructions are executed. */
 #ifndef configSUPPORT_FPU
-    #define configSUPPORT_FPU 0
+    #define configSUPPORT_FPU    0
 #endif
 
 #if configSUPPORT_FPU == 1
     void vPortTaskUsesFPU( void );
-    #define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
+    #define portTASK_USES_FLOATING_POINT()    vPortTaskUsesFPU()
 #endif
 
 /* See the comments under the configUSE_COMMON_INTERRUPT_ENTRY_POINT definition
-below. */
-BaseType_t xPortRegisterCInterruptHandler( ISR_Handler_t pxHandler, uint32_t ulVectorNumber );
-BaseType_t xPortInstallInterruptHandler( ISR_Handler_t pxHandler, uint32_t ulVectorNumber );
+ * below. */
+BaseType_t xPortRegisterCInterruptHandler( ISR_Handler_t pxHandler,
+                                           uint32_t ulVectorNumber );
+BaseType_t xPortInstallInterruptHandler( ISR_Handler_t pxHandler,
+                                         uint32_t ulVectorNumber );
 
 #ifndef configAPIC_BASE
-    /* configAPIC_BASE_ADDRESS sets the base address of the local APIC.  It can
-    be overridden in FreeRTOSConfig.h should it not be constant. */
-    #define configAPIC_BASE 0xFEE00000UL
+
+/* configAPIC_BASE_ADDRESS sets the base address of the local APIC.  It can
+ * be overridden in FreeRTOSConfig.h should it not be constant. */
+    #define configAPIC_BASE    0xFEE00000UL
 #endif
 
 #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-    /* The FreeRTOS scheduling algorithm selects the task that will enter the
-    Running state.  configUSE_PORT_OPTIMISED_TASK_SELECTION is used to set how
-    that is done.
 
-    If configUSE_PORT_OPTIMISED_TASK_SELECTION is set to 0 then the task to
-    enter the Running state is selected using a portable algorithm written in
-    C.  This is the slowest method, but the algorithm does not restrict the
-    maximum number of unique RTOS task priorities that are available.
-
-    If configUSE_PORT_OPTIMISED_TASK_SELECTION is set to 1 then the task to
-    enter the Running state is selected using a single assembly instruction.
-    This is the fastest method, but restricts the maximum number of unique RTOS
-    task priorities to 32 (the same task priority can be assigned to any number
-    of RTOS tasks). */
+/* The FreeRTOS scheduling algorithm selects the task that will enter the
+ * Running state.  configUSE_PORT_OPTIMISED_TASK_SELECTION is used to set how
+ * that is done.
+ *
+ * If configUSE_PORT_OPTIMISED_TASK_SELECTION is set to 0 then the task to
+ * enter the Running state is selected using a portable algorithm written in
+ * C.  This is the slowest method, but the algorithm does not restrict the
+ * maximum number of unique RTOS task priorities that are available.
+ *
+ * If configUSE_PORT_OPTIMISED_TASK_SELECTION is set to 1 then the task to
+ * enter the Running state is selected using a single assembly instruction.
+ * This is the fastest method, but restricts the maximum number of unique RTOS
+ * task priorities to 32 (the same task priority can be assigned to any number
+ * of RTOS tasks). */
     #warning configUSE_PORT_OPTIMISED_TASK_SELECTION was not defined in FreeRTOSConfig.h and has been defaulted to 1
-    #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+    #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
 #endif
 
 #ifndef configUSE_COMMON_INTERRUPT_ENTRY_POINT
-    /* There are two ways of implementing interrupt handlers:
 
-        1) As standard C functions -
-
-        This method can only be used if configUSE_COMMON_INTERRUPT_ENTRY_POINT
-        is set to 1.  The C function is installed using
-        xPortRegisterCInterruptHandler().
-
-        This is the simplest of the two methods but incurs a slightly longer
-        interrupt entry time.
-
-        2) By using an assembly stub that wraps the handler in the FreeRTOS
-           portFREERTOS_INTERRUPT_ENTRY and portFREERTOS_INTERRUPT_EXIT macros.
-
-        This method can always be used.  It is slightly more complex than
-        method 1 but benefits from a faster interrupt entry time. */
+/* There are two ways of implementing interrupt handlers:
+ *
+ *  1) As standard C functions -
+ *
+ *  This method can only be used if configUSE_COMMON_INTERRUPT_ENTRY_POINT
+ *  is set to 1.  The C function is installed using
+ *  xPortRegisterCInterruptHandler().
+ *
+ *  This is the simplest of the two methods but incurs a slightly longer
+ *  interrupt entry time.
+ *
+ *  2) By using an assembly stub that wraps the handler in the FreeRTOS
+ *     portFREERTOS_INTERRUPT_ENTRY and portFREERTOS_INTERRUPT_EXIT macros.
+ *
+ *  This method can always be used.  It is slightly more complex than
+ *  method 1 but benefits from a faster interrupt entry time. */
     #warning configUSE_COMMON_INTERRUPT_ENTRY_POINT was not defined in FreeRTOSConfig.h and has been defaulted to 1.
-    #define configUSE_COMMON_INTERRUPT_ENTRY_POINT  1
+    #define configUSE_COMMON_INTERRUPT_ENTRY_POINT    1
 #endif
 
 #ifndef configISR_STACK_SIZE
-    /* Interrupt entry code will switch the stack in use to a dedicated system
-    stack.
 
-    configISR_STACK_SIZE defines the number of 32-bit values that can be stored
-    on the system stack, and must be large enough to hold a potentially nested
-    interrupt stack frame. */
+/* Interrupt entry code will switch the stack in use to a dedicated system
+ * stack.
+ *
+ * configISR_STACK_SIZE defines the number of 32-bit values that can be stored
+ * on the system stack, and must be large enough to hold a potentially nested
+ * interrupt stack frame. */
 
     #error configISR_STACK_SIZE was not defined in FreeRTOSConfig.h.
 #endif
 
 #ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
-    /* Interrupt safe FreeRTOS functions (those that end in "FromISR" must not
-    be called from an interrupt that has a priority above that set by
-    configMAX_API_CALL_INTERRUPT_PRIORITY.  */
+
+/* Interrupt safe FreeRTOS functions (those that end in "FromISR" must not
+ * be called from an interrupt that has a priority above that set by
+ * configMAX_API_CALL_INTERRUPT_PRIORITY.  */
     #warning configMAX_API_CALL_INTERRUPT_PRIORITY was not defined in FreeRTOSConfig.h and has been defaulted to 10
-    #define configMAX_API_CALL_INTERRUPT_PRIORITY 10
+    #define configMAX_API_CALL_INTERRUPT_PRIORITY    10
 #endif
 
 #ifndef configSUPPORT_FPU
     #warning configSUPPORT_FPU was not defined in FreeRTOSConfig.h and has been defaulted to 0
-    #define configSUPPORT_FPU 0
+    #define configSUPPORT_FPU    0
 #endif
 
 /* The value written to the task priority register to raise the interrupt mask
-to the maximum from which FreeRTOS API calls can be made. */
-#define portAPIC_PRIORITY_SHIFT     ( 4UL )
-#define portAPIC_MAX_SUB_PRIORITY   ( 0x0fUL )
-#define portMAX_API_CALL_PRIORITY       ( ( configMAX_API_CALL_INTERRUPT_PRIORITY << portAPIC_PRIORITY_SHIFT ) | portAPIC_MAX_SUB_PRIORITY )
+ * to the maximum from which FreeRTOS API calls can be made. */
+#define portAPIC_PRIORITY_SHIFT        ( 4UL )
+#define portAPIC_MAX_SUB_PRIORITY      ( 0x0fUL )
+#define portMAX_API_CALL_PRIORITY      ( ( configMAX_API_CALL_INTERRUPT_PRIORITY << portAPIC_PRIORITY_SHIFT ) | portAPIC_MAX_SUB_PRIORITY )
 
 /* Asserts if interrupt safe FreeRTOS functions are called from a priority
-above the max system call interrupt priority. */
-#define portAPIC_PROCESSOR_PRIORITY ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0xA0UL  ) ) )
-#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( portAPIC_PROCESSOR_PRIORITY ) <= ( portMAX_API_CALL_PRIORITY ) )
+ * above the max system call interrupt priority. */
+#define portAPIC_PROCESSOR_PRIORITY    ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0xA0UL ) ) )
+#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    configASSERT( ( portAPIC_PROCESSOR_PRIORITY ) <= ( portMAX_API_CALL_PRIORITY ) )
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/GCC/MSP430F449/port.c b/portable/GCC/MSP430F449/port.c
index ca5d0c558..0b41665ce 100644
--- a/portable/GCC/MSP430F449/port.c
+++ b/portable/GCC/MSP430F449/port.c
@@ -27,10 +27,10 @@
  */
 
 /*
-    Changes from V2.5.2
-
-    + usCriticalNesting now has a volatile qualifier.
-*/
+ *  Changes from V2.5.2
+ *
+ + usCriticalNesting now has a volatile qualifier.
+ */
 
 /* Standard includes. */
 #include <stdlib.h>
@@ -41,32 +41,32 @@
 #include "task.h"
 
 /*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the MSP430 port.
- *----------------------------------------------------------*/
+* Implementation of functions defined in portable.h for the MSP430 port.
+*----------------------------------------------------------*/
 
 /* Constants required for hardware setup.  The tick ISR runs off the ACLK,
-not the MCLK. */
+ * not the MCLK. */
 #define portACLK_FREQUENCY_HZ           ( ( TickType_t ) 32768 )
 #define portINITIAL_CRITICAL_NESTING    ( ( uint16_t ) 10 )
-#define portFLAGS_INT_ENABLED   ( ( StackType_t ) 0x08 )
+#define portFLAGS_INT_ENABLED           ( ( StackType_t ) 0x08 )
 
 /* We require the address of the pxCurrentTCB variable, but don't want to know
-any details of its type. */
+ * any details of its type. */
 typedef void TCB_t;
 extern volatile TCB_t * volatile pxCurrentTCB;
 
 /* Most ports implement critical sections by placing the interrupt flags on
-the stack before disabling interrupts.  Exiting the critical section is then
-simply a case of popping the flags from the stack.  As mspgcc does not use
-a frame pointer this cannot be done as modifying the stack will clobber all
-the stack variables.  Instead each task maintains a count of the critical
-section nesting depth.  Each time a critical section is entered the count is
-incremented.  Each time a critical section is left the count is decremented -
-with interrupts only being re-enabled if the count is zero.
-
-usCriticalNesting will get set to zero when the scheduler starts, but must
-not be initialised to zero as this will cause problems during the startup
-sequence. */
+ * the stack before disabling interrupts.  Exiting the critical section is then
+ * simply a case of popping the flags from the stack.  As mspgcc does not use
+ * a frame pointer this cannot be done as modifying the stack will clobber all
+ * the stack variables.  Instead each task maintains a count of the critical
+ * section nesting depth.  Each time a critical section is entered the count is
+ * incremented.  Each time a critical section is left the count is decremented -
+ * with interrupts only being re-enabled if the count is zero.
+ *
+ * usCriticalNesting will get set to zero when the scheduler starts, but must
+ * not be initialised to zero as this will cause problems during the startup
+ * sequence. */
 volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;
 /*-----------------------------------------------------------*/
 
@@ -77,24 +77,24 @@ volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;
  * pointer value is saved into the task control block so it can be retrieved
  * the next time the task executes.
  */
-#define portSAVE_CONTEXT()                                  \
-    asm volatile (  "push   r4                      \n\t"   \
-                    "push   r5                      \n\t"   \
-                    "push   r6                      \n\t"   \
-                    "push   r7                      \n\t"   \
-                    "push   r8                      \n\t"   \
-                    "push   r9                      \n\t"   \
-                    "push   r10                     \n\t"   \
-                    "push   r11                     \n\t"   \
-                    "push   r12                     \n\t"   \
-                    "push   r13                     \n\t"   \
-                    "push   r14                     \n\t"   \
-                    "push   r15                     \n\t"   \
-                    "mov.w  usCriticalNesting, r14  \n\t"   \
-                    "push   r14                     \n\t"   \
-                    "mov.w  pxCurrentTCB, r12       \n\t"   \
-                    "mov.w  r1, @r12                \n\t"   \
-                );
+#define portSAVE_CONTEXT()                               \
+    asm volatile ( "push   r4                      \n\t" \
+                   "push   r5                      \n\t" \
+                   "push   r6                      \n\t" \
+                   "push   r7                      \n\t" \
+                   "push   r8                      \n\t" \
+                   "push   r9                      \n\t" \
+                   "push   r10                     \n\t" \
+                   "push   r11                     \n\t" \
+                   "push   r12                     \n\t" \
+                   "push   r13                     \n\t" \
+                   "push   r14                     \n\t" \
+                   "push   r15                     \n\t" \
+                   "mov.w  usCriticalNesting, r14  \n\t" \
+                   "push   r14                     \n\t" \
+                   "mov.w  pxCurrentTCB, r12       \n\t" \
+                   "mov.w  r1, @r12                \n\t" \
+                   );
 
 /*
  * Macro to restore a task context from the task stack.  This is effectively
@@ -106,26 +106,26 @@ volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;
  * The bic instruction ensures there are no low power bits set in the status
  * register that is about to be popped from the stack.
  */
-#define portRESTORE_CONTEXT()                               \
-    asm volatile (  "mov.w  pxCurrentTCB, r12       \n\t"   \
-                    "mov.w  @r12, r1                \n\t"   \
-                    "pop    r15                     \n\t"   \
-                    "mov.w  r15, usCriticalNesting  \n\t"   \
-                    "pop    r15                     \n\t"   \
-                    "pop    r14                     \n\t"   \
-                    "pop    r13                     \n\t"   \
-                    "pop    r12                     \n\t"   \
-                    "pop    r11                     \n\t"   \
-                    "pop    r10                     \n\t"   \
-                    "pop    r9                      \n\t"   \
-                    "pop    r8                      \n\t"   \
-                    "pop    r7                      \n\t"   \
-                    "pop    r6                      \n\t"   \
-                    "pop    r5                      \n\t"   \
-                    "pop    r4                      \n\t"   \
-                    "bic    #(0xf0),0(r1)           \n\t"   \
-                    "reti                           \n\t"   \
-                );
+#define portRESTORE_CONTEXT()                            \
+    asm volatile ( "mov.w  pxCurrentTCB, r12       \n\t" \
+                   "mov.w  @r12, r1                \n\t" \
+                   "pop    r15                     \n\t" \
+                   "mov.w  r15, usCriticalNesting  \n\t" \
+                   "pop    r15                     \n\t" \
+                   "pop    r14                     \n\t" \
+                   "pop    r13                     \n\t" \
+                   "pop    r12                     \n\t" \
+                   "pop    r11                     \n\t" \
+                   "pop    r10                     \n\t" \
+                   "pop    r9                      \n\t" \
+                   "pop    r8                      \n\t" \
+                   "pop    r7                      \n\t" \
+                   "pop    r6                      \n\t" \
+                   "pop    r5                      \n\t" \
+                   "pop    r4                      \n\t" \
+                   "bic    #(0xf0),0(r1)           \n\t" \
+                   "reti                           \n\t" \
+                   );
 /*-----------------------------------------------------------*/
 
 /*
@@ -141,24 +141,26 @@ static void prvSetupTimerInterrupt( void );
  *
  * See the header file portable.h.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
     /*
-        Place a few bytes of known values on the bottom of the stack.
-        This is just useful for debugging and can be included if required.
-
-        *pxTopOfStack = ( StackType_t ) 0x1111;
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x2222;
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x3333;
-        pxTopOfStack--;
-    */
+     *  Place a few bytes of known values on the bottom of the stack.
+     *  This is just useful for debugging and can be included if required.
+     *
+     * pxTopOfStack = ( StackType_t ) 0x1111;
+     *  pxTopOfStack--;
+     * pxTopOfStack = ( StackType_t ) 0x2222;
+     *  pxTopOfStack--;
+     * pxTopOfStack = ( StackType_t ) 0x3333;
+     *  pxTopOfStack--;
+     */
 
     /* The msp430 automatically pushes the PC then SR onto the stack before
-    executing an ISR.  We want the stack to look just as if this has happened
-    so place a pointer to the start of the task on the stack first - followed
-    by the flags we want the task to use when it starts up. */
+     * executing an ISR.  We want the stack to look just as if this has happened
+     * so place a pointer to the start of the task on the stack first - followed
+     * by the flags we want the task to use when it starts up. */
     *pxTopOfStack = ( StackType_t ) pxCode;
     pxTopOfStack--;
     *pxTopOfStack = portFLAGS_INT_ENABLED;
@@ -189,19 +191,19 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
     pxTopOfStack--;
 
     /* When the task starts is will expect to find the function parameter in
-    R15. */
+     * R15. */
     *pxTopOfStack = ( StackType_t ) pvParameters;
     pxTopOfStack--;
 
     /* The code generated by the mspgcc compiler does not maintain separate
-    stack and frame pointers. The portENTER_CRITICAL macro cannot therefore
-    use the stack as per other ports.  Instead a variable is used to keep
-    track of the critical section nesting.  This variable has to be stored
-    as part of the task context and is initially set to zero. */
+     * stack and frame pointers. The portENTER_CRITICAL macro cannot therefore
+     * use the stack as per other ports.  Instead a variable is used to keep
+     * track of the critical section nesting.  This variable has to be stored
+     * as part of the task context and is initially set to zero. */
     *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;
 
     /* Return a pointer to the top of the stack we have generated so this can
-    be stored in the task control block for the task. */
+     * be stored in the task control block for the task. */
     return pxTopOfStack;
 }
 /*-----------------------------------------------------------*/
@@ -209,7 +211,7 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
 BaseType_t xPortStartScheduler( void )
 {
     /* Setup the hardware to generate the tick.  Interrupts are disabled when
-    this function is called. */
+     * this function is called. */
     prvSetupTimerInterrupt();
 
     /* Restore the context of the first task that is going to run. */
@@ -223,7 +225,7 @@ BaseType_t xPortStartScheduler( void )
 void vPortEndScheduler( void )
 {
     /* It is unlikely that the MSP430 port will get stopped.  If required simply
-    disable the tick interrupt here. */
+     * disable the tick interrupt here. */
 }
 /*-----------------------------------------------------------*/
 
@@ -232,13 +234,13 @@ void vPortEndScheduler( void )
  *
  * The first thing we do is save the registers so we can use a naked attribute.
  */
-void vPortYield( void ) __attribute__ ( ( naked ) );
+void vPortYield( void ) __attribute__( ( naked ) );
 void vPortYield( void )
 {
     /* We want the stack of the task being saved to look exactly as if the task
-    was saved during a pre-emptive RTOS tick ISR.  Before calling an ISR the
-    msp430 places the status register onto the stack.  As this is a function
-    call and not an ISR we have to do this manually. */
+     * was saved during a pre-emptive RTOS tick ISR.  Before calling an ISR the
+     * msp430 places the status register onto the stack.  As this is a function
+     * call and not an ISR we have to do this manually. */
     asm volatile ( "push    r2" );
     _DINT();
 
@@ -289,19 +291,19 @@ static void prvSetupTimerInterrupt( void )
 
 #if configUSE_PREEMPTION == 1
 
-    /*
-     * Tick ISR for preemptive scheduler.  We can use a naked attribute as
-     * the context is saved at the start of vPortYieldFromTick().  The tick
-     * count is incremented after the context is saved.
-     */
-    interrupt (TIMERA0_VECTOR) prvTickISR( void ) __attribute__ ( ( naked ) );
-    interrupt (TIMERA0_VECTOR) prvTickISR( void )
+/*
+ * Tick ISR for preemptive scheduler.  We can use a naked attribute as
+ * the context is saved at the start of vPortYieldFromTick().  The tick
+ * count is incremented after the context is saved.
+ */
+    interrupt( TIMERA0_VECTOR ) prvTickISR( void ) __attribute__( ( naked ) );
+    interrupt( TIMERA0_VECTOR ) prvTickISR( void )
     {
         /* Save the context of the interrupted task. */
         portSAVE_CONTEXT();
 
         /* Increment the tick count then switch to the highest priority task
-        that is ready to run. */
+         * that is ready to run. */
         if( xTaskIncrementTick() != pdFALSE )
         {
             vTaskSwitchContext();
@@ -311,19 +313,16 @@ static void prvSetupTimerInterrupt( void )
         portRESTORE_CONTEXT();
     }
 
-#else
+#else /* if configUSE_PREEMPTION == 1 */
 
-    /*
-     * Tick ISR for the cooperative scheduler.  All this does is increment the
-     * tick count.  We don't need to switch context, this can only be done by
-     * manual calls to taskYIELD();
-     */
-    interrupt (TIMERA0_VECTOR) prvTickISR( void );
-    interrupt (TIMERA0_VECTOR) prvTickISR( void )
+/*
+ * Tick ISR for the cooperative scheduler.  All this does is increment the
+ * tick count.  We don't need to switch context, this can only be done by
+ * manual calls to taskYIELD();
+ */
+    interrupt( TIMERA0_VECTOR ) prvTickISR( void );
+    interrupt( TIMERA0_VECTOR ) prvTickISR( void )
     {
         xTaskIncrementTick();
     }
-#endif
-
-
-
+#endif /* if configUSE_PREEMPTION == 1 */
diff --git a/portable/GCC/MSP430F449/portmacro.h b/portable/GCC/MSP430F449/portmacro.h
index 2f70a24d1..445279f5c 100644
--- a/portable/GCC/MSP430F449/portmacro.h
+++ b/portable/GCC/MSP430F449/portmacro.h
@@ -46,24 +46,24 @@
  */
 
 /* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       int
-#define portSTACK_TYPE  uint16_t
-#define portBASE_TYPE   short
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         int
+#define portSTACK_TYPE    uint16_t
+#define portBASE_TYPE     short
 
-typedef portSTACK_TYPE StackType_t;
-typedef short BaseType_t;
-typedef unsigned short UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef short            BaseType_t;
+typedef unsigned short   UBaseType_t;
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY ( TickType_t )    ( 0xFFFFFFFFUL )
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) ( 0xFFFFFFFFUL )
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
@@ -75,54 +75,54 @@ typedef unsigned short UBaseType_t;
 /*-----------------------------------------------------------*/
 
 /* Critical section control macros. */
-#define portNO_CRITICAL_SECTION_NESTING     ( ( uint16_t ) 0 )
+#define portNO_CRITICAL_SECTION_NESTING    ( ( uint16_t ) 0 )
 
-#define portENTER_CRITICAL()                                                    \
-{                                                                               \
-extern volatile uint16_t usCriticalNesting;                         \
-                                                                                \
-    portDISABLE_INTERRUPTS();                                                   \
-                                                                                \
-    /* Now interrupts are disabled ulCriticalNesting can be accessed */         \
-    /* directly.  Increment ulCriticalNesting to keep a count of how many */    \
-    /* times portENTER_CRITICAL() has been called. */                           \
-    usCriticalNesting++;                                                        \
-}
+#define portENTER_CRITICAL()                                                      \
+    {                                                                             \
+        extern volatile uint16_t usCriticalNesting;                               \
+                                                                                  \
+        portDISABLE_INTERRUPTS();                                                 \
+                                                                                  \
+        /* Now that interrupts are disabled, ulCriticalNesting can be accessed */ \
+        /* directly.  Increment ulCriticalNesting to keep a count of how many */  \
+        /* times portENTER_CRITICAL() has been called. */                         \
+        usCriticalNesting++;                                                      \
+    }
 
-#define portEXIT_CRITICAL()                                                     \
-{                                                                               \
-extern volatile uint16_t usCriticalNesting;                         \
-                                                                                \
-    if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING )                   \
-    {                                                                           \
-        /* Decrement the nesting count as we are leaving a critical section. */ \
-        usCriticalNesting--;                                                    \
-                                                                                \
-        /* If the nesting level has reached zero then interrupts should be */   \
-        /* re-enabled. */                                                       \
-        if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING )              \
-        {                                                                       \
-            portENABLE_INTERRUPTS();                                            \
-        }                                                                       \
-    }                                                                           \
-}
+#define portEXIT_CRITICAL()                                                         \
+    {                                                                               \
+        extern volatile uint16_t usCriticalNesting;                                 \
+                                                                                    \
+        if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING )                   \
+        {                                                                           \
+            /* Decrement the nesting count as we are leaving a critical section. */ \
+            usCriticalNesting--;                                                    \
+                                                                                    \
+            /* If the nesting level has reached zero then interrupts should be */   \
+            /* re-enabled. */                                                       \
+            if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING )              \
+            {                                                                       \
+                portENABLE_INTERRUPTS();                                            \
+            }                                                                       \
+        }                                                                           \
+    }
 /*-----------------------------------------------------------*/
 
 /* Task utilities. */
-extern void vPortYield( void ) __attribute__ ( ( naked ) );
-#define portYIELD()         vPortYield()
-#define portNOP()           asm volatile ( "NOP" )
+extern void vPortYield( void ) __attribute__( ( naked ) );
+#define portYIELD()    vPortYield()
+#define portNOP()      asm volatile ( "NOP" )
 /*-----------------------------------------------------------*/
 
-/* Hardwware specifics. */
-#define portBYTE_ALIGNMENT          2
-#define portSTACK_GROWTH            ( -1 )
-#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT    2
+#define portSTACK_GROWTH      ( -1 )
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/GCC/MicroBlaze/port.c b/portable/GCC/MicroBlaze/port.c
index 309b805ad..2051e3e44 100644
--- a/portable/GCC/MicroBlaze/port.c
+++ b/portable/GCC/MicroBlaze/port.c
@@ -27,8 +27,8 @@
  */
 
 /*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the MicroBlaze port.
- *----------------------------------------------------------*/
+* Implementation of functions defined in portable.h for the MicroBlaze port.
+*----------------------------------------------------------*/
 
 
 /* Scheduler includes. */
@@ -43,33 +43,33 @@
 #include <xintc_i.h>
 #include <xtmrctr.h>
 
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
+#if ( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
     #error configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 to use this port.
 #endif
 
 /* Tasks are started with interrupts enabled. */
-#define portINITIAL_MSR_STATE       ( ( StackType_t ) 0x02 )
+#define portINITIAL_MSR_STATE        ( ( StackType_t ) 0x02 )
 
 /* Tasks are started with a critical section nesting of 0 - however prior
-to the scheduler being commenced we don't want the critical nesting level
-to reach zero, so it is initialised to a high value. */
-#define portINITIAL_NESTING_VALUE   ( 0xff )
+ * to the scheduler being commenced we don't want the critical nesting level
+ * to reach zero, so it is initialised to a high value. */
+#define portINITIAL_NESTING_VALUE    ( 0xff )
 
 /* Our hardware setup only uses one counter. */
-#define portCOUNTER_0               0
+#define portCOUNTER_0                0
 
 /* The stack used by the ISR is filled with a known value to assist in
-debugging. */
-#define portISR_STACK_FILL_VALUE    0x55555555
+ * debugging. */
+#define portISR_STACK_FILL_VALUE     0x55555555
 
 /* Counts the nesting depth of calls to portENTER_CRITICAL().  Each task
-maintains it's own count, so this variable is saved as part of the task
-context. */
+ * maintains it's own count, so this variable is saved as part of the task
+ * context. */
 volatile UBaseType_t uxCriticalNesting = portINITIAL_NESTING_VALUE;
 
 /* To limit the amount of stack required by each task, this port uses a
-separate stack for interrupts. */
-uint32_t *pulISRStack;
+ * separate stack for interrupts. */
+uint32_t * pulISRStack;
 
 /*-----------------------------------------------------------*/
 
@@ -86,17 +86,19 @@ static void prvSetupTimerInterrupt( void );
  *
  * See the header file portable.h.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
-extern void * _SDA2_BASE_;
-extern void * _SDA_BASE_;
-const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_;
-const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_;
+    extern void * _SDA2_BASE_;
+    extern void * _SDA_BASE_;
+    const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_;
+    const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_;
 
     /* Place a few bytes of known values on the bottom of the stack.
-    This is essential for the Microblaze port and these lines must
-    not be omitted.  The parameter value will overwrite the
-    0x22222222 value during the function prologue. */
+     * This is essential for the Microblaze port and these lines must
+     * not be omitted.  The parameter value will overwrite the
+     * 0x22222222 value during the function prologue. */
     *pxTopOfStack = ( StackType_t ) 0x11111111;
     pxTopOfStack--;
     *pxTopOfStack = ( StackType_t ) 0x22222222;
@@ -105,98 +107,98 @@ const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_;
     pxTopOfStack--;
 
     /* First stack an initial value for the critical section nesting.  This
-    is initialised to zero as tasks are started with interrupts enabled. */
-    *pxTopOfStack = ( StackType_t ) 0x00;   /* R0. */
+     *  is initialised to zero as tasks are started with interrupts enabled. */
+    *pxTopOfStack = ( StackType_t ) 0x00; /* R0. */
 
     /* Place an initial value for all the general purpose registers. */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) ulR2;   /* R2 - small data area. */
+    *pxTopOfStack = ( StackType_t ) ulR2;         /* R2 - small data area. */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x03;   /* R3. */
+    *pxTopOfStack = ( StackType_t ) 0x03;         /* R3. */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x04;   /* R4. */
+    *pxTopOfStack = ( StackType_t ) 0x04;         /* R4. */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) pvParameters;/* R5 contains the function call parameters. */
+    *pxTopOfStack = ( StackType_t ) pvParameters; /* R5 contains the function call parameters. */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x06;   /* R6. */
+    *pxTopOfStack = ( StackType_t ) 0x06;         /* R6. */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x07;   /* R7. */
+    *pxTopOfStack = ( StackType_t ) 0x07;         /* R7. */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x08;   /* R8. */
+    *pxTopOfStack = ( StackType_t ) 0x08;         /* R8. */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x09;   /* R9. */
+    *pxTopOfStack = ( StackType_t ) 0x09;         /* R9. */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x0a;   /* R10. */
+    *pxTopOfStack = ( StackType_t ) 0x0a;         /* R10. */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x0b;   /* R11. */
+    *pxTopOfStack = ( StackType_t ) 0x0b;         /* R11. */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x0c;   /* R12. */
+    *pxTopOfStack = ( StackType_t ) 0x0c;         /* R12. */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) ulR13;  /* R13 - small data read write area. */
+    *pxTopOfStack = ( StackType_t ) ulR13;        /* R13 - small data read write area. */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) pxCode; /* R14. */
+    *pxTopOfStack = ( StackType_t ) pxCode;       /* R14. */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x0f;   /* R15. */
+    *pxTopOfStack = ( StackType_t ) 0x0f;         /* R15. */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x10;   /* R16. */
+    *pxTopOfStack = ( StackType_t ) 0x10;         /* R16. */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x11;   /* R17. */
+    *pxTopOfStack = ( StackType_t ) 0x11;         /* R17. */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x12;   /* R18. */
+    *pxTopOfStack = ( StackType_t ) 0x12;         /* R18. */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x13;   /* R19. */
+    *pxTopOfStack = ( StackType_t ) 0x13;         /* R19. */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x14;   /* R20. */
+    *pxTopOfStack = ( StackType_t ) 0x14;         /* R20. */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x15;   /* R21. */
+    *pxTopOfStack = ( StackType_t ) 0x15;         /* R21. */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x16;   /* R22. */
+    *pxTopOfStack = ( StackType_t ) 0x16;         /* R22. */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x17;   /* R23. */
+    *pxTopOfStack = ( StackType_t ) 0x17;         /* R23. */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x18;   /* R24. */
+    *pxTopOfStack = ( StackType_t ) 0x18;         /* R24. */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x19;   /* R25. */
+    *pxTopOfStack = ( StackType_t ) 0x19;         /* R25. */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x1a;   /* R26. */
+    *pxTopOfStack = ( StackType_t ) 0x1a;         /* R26. */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x1b;   /* R27. */
+    *pxTopOfStack = ( StackType_t ) 0x1b;         /* R27. */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x1c;   /* R28. */
+    *pxTopOfStack = ( StackType_t ) 0x1c;         /* R28. */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x1d;   /* R29. */
+    *pxTopOfStack = ( StackType_t ) 0x1d;         /* R29. */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x1e;   /* R30. */
+    *pxTopOfStack = ( StackType_t ) 0x1e;         /* R30. */
     pxTopOfStack--;
 
     /* The MSR is stacked between R30 and R31. */
     *pxTopOfStack = portINITIAL_MSR_STATE;
     pxTopOfStack--;
 
-    *pxTopOfStack = ( StackType_t ) 0x1f;   /* R31. */
+    *pxTopOfStack = ( StackType_t ) 0x1f; /* R31. */
     pxTopOfStack--;
 
     /* Return a pointer to the top of the stack we have generated so this can
-    be stored in the task control block for the task. */
+     * be stored in the task control block for the task. */
     return pxTopOfStack;
 }
 /*-----------------------------------------------------------*/
 
 BaseType_t xPortStartScheduler( void )
 {
-extern void ( __FreeRTOS_interrupt_Handler )( void );
-extern void ( vStartFirstTask )( void );
+    extern void( __FreeRTOS_interrupt_Handler )( void );
+    extern void( vStartFirstTask )( void );
 
 
     /* Setup the FreeRTOS interrupt handler.  Code copied from crt0.s. */
-    asm volatile (  "la r6, r0, __FreeRTOS_interrupt_handler        \n\t" \
-                    "sw r6, r1, r0                                  \n\t" \
-                    "lhu r7, r1, r0                                 \n\t" \
-                    "shi r7, r0, 0x12                               \n\t" \
-                    "shi r6, r0, 0x16 " );
+    asm volatile ( "la r6, r0, __FreeRTOS_interrupt_handler        \n\t" \
+                   "sw r6, r1, r0                                  \n\t" \
+                   "lhu r7, r1, r0                                 \n\t" \
+                   "shi r7, r0, 0x12                               \n\t" \
+                   "shi r6, r0, 0x16 " );
 
     /* Setup the hardware to generate the tick.  Interrupts are disabled when
-    this function is called. */
+     * this function is called. */
     prvSetupTimerInterrupt();
 
     /* Allocate the stack to be used by the interrupt handler. */
@@ -229,16 +231,17 @@ void vPortEndScheduler( void )
  */
 void vPortYield( void )
 {
-extern void VPortYieldASM( void );
+    extern void VPortYieldASM( void );
 
     /* Perform the context switch in a critical section to assure it is
-    not interrupted by the tick ISR.  It is not a problem to do this as
-    each task maintains it's own interrupt status. */
+     * not interrupted by the tick ISR.  It is not a problem to do this as
+     * each task maintains it's own interrupt status. */
     portENTER_CRITICAL();
-        /* Jump directly to the yield function to ensure there is no
-        compiler generated prologue code. */
-        asm volatile (  "bralid r14, VPortYieldASM      \n\t" \
-                        "or r0, r0, r0                  \n\t" );
+
+    /* Jump directly to the yield function to ensure there is no
+     * compiler generated prologue code. */
+    asm volatile ( "bralid r14, VPortYieldASM      \n\t" \
+                   "or r0, r0, r0                  \n\t" );
     portEXIT_CRITICAL();
 }
 /*-----------------------------------------------------------*/
@@ -248,25 +251,25 @@ extern void VPortYieldASM( void );
  */
 static void prvSetupTimerInterrupt( void )
 {
-XTmrCtr xTimer;
-const uint32_t ulCounterValue = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
-UBaseType_t uxMask;
+    XTmrCtr xTimer;
+    const uint32_t ulCounterValue = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
+    UBaseType_t uxMask;
 
     /* The OPB timer1 is used to generate the tick.  Use the provided library
-    functions to enable the timer and set the tick frequency. */
+     * functions to enable the timer and set the tick frequency. */
     XTmrCtr_mDisable( XPAR_OPB_TIMER_1_BASEADDR, XPAR_OPB_TIMER_1_DEVICE_ID );
     XTmrCtr_Initialize( &xTimer, XPAR_OPB_TIMER_1_DEVICE_ID );
     XTmrCtr_mSetLoadReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, ulCounterValue );
-    XTmrCtr_mSetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, XTC_CSR_LOAD_MASK | XTC_CSR_INT_OCCURED_MASK );
+    XTmrCtr_mSetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, XTC_CSR_LOAD_MASK | XTC_CSR_INT_occurred_MASK );
 
     /* Set the timer interrupt enable bit while maintaining the other bit
-    states. */
+     * states. */
     uxMask = XIntc_In32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ) );
     uxMask |= XPAR_OPB_TIMER_1_INTERRUPT_MASK;
     XIntc_Out32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ), ( uxMask ) );
 
     XTmrCtr_Start( &xTimer, XPAR_OPB_TIMER_1_DEVICE_ID );
-    XTmrCtr_mSetControlStatusReg(XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, XTC_CSR_ENABLE_TMR_MASK | XTC_CSR_ENABLE_INT_MASK | XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK | XTC_CSR_INT_OCCURED_MASK );
+    XTmrCtr_mSetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, XTC_CSR_ENABLE_TMR_MASK | XTC_CSR_ENABLE_INT_MASK | XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK | XTC_CSR_INT_occurred_MASK );
     XIntc_mAckIntr( XPAR_INTC_SINGLE_BASEADDR, 1 );
 }
 /*-----------------------------------------------------------*/
@@ -279,15 +282,15 @@ UBaseType_t uxMask;
  */
 void vTaskISRHandler( void )
 {
-static uint32_t ulPending;
+    static uint32_t ulPending;
 
     /* Which interrupts are pending? */
     ulPending = XIntc_In32( ( XPAR_INTC_SINGLE_BASEADDR + XIN_IVR_OFFSET ) );
 
     if( ulPending < XPAR_INTC_MAX_NUM_INTR_INPUTS )
     {
-        static XIntc_VectorTableEntry *pxTablePtr;
-        static XIntc_Config *pxConfig;
+        static XIntc_VectorTableEntry * pxTablePtr;
+        static XIntc_Config * pxConfig;
         static uint32_t ulInterruptMask;
 
         ulInterruptMask = ( uint32_t ) 1 << ulPending;
@@ -296,7 +299,8 @@ static uint32_t ulPending;
         pxConfig = &XIntc_ConfigTable[ ( uint32_t ) XPAR_INTC_SINGLE_DEVICE_ID ];
 
         pxTablePtr = &( pxConfig->HandlerTable[ ulPending ] );
-        if( pxConfig->AckBeforeService & ( ulInterruptMask  ) )
+
+        if( pxConfig->AckBeforeService & ( ulInterruptMask ) )
         {
             XIntc_mAckIntr( pxConfig->BaseAddress, ulInterruptMask );
             pxTablePtr->Handler( pxTablePtr->CallBackRef );
@@ -313,9 +317,9 @@ static uint32_t ulPending;
 /*
  * Handler for the timer interrupt.
  */
-void vTickISR( void *pvBaseAddress )
+void vTickISR( void * pvBaseAddress )
 {
-uint32_t ulCSR;
+    uint32_t ulCSR;
 
     /* Increment the RTOS tick - this might cause a task to unblock. */
     if( xTaskIncrementTick() != pdFALSE )
@@ -324,7 +328,7 @@ uint32_t ulCSR;
     }
 
     /* Clear the timer interrupt */
-    ulCSR = XTmrCtr_mGetControlStatusReg(XPAR_OPB_TIMER_1_BASEADDR, 0);
+    ulCSR = XTmrCtr_mGetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, 0 );
     XTmrCtr_mSetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, ulCSR );
 }
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/MicroBlaze/portmacro.h b/portable/GCC/MicroBlaze/portmacro.h
index b04c526a4..8ddeb0ed0 100644
--- a/portable/GCC/MicroBlaze/portmacro.h
+++ b/portable/GCC/MicroBlaze/portmacro.h
@@ -46,28 +46,28 @@
  */
 
 /* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint32_t
-#define portBASE_TYPE   long
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-    not need to be guarded with a critical section. */
-    #define portTICK_TYPE_IS_ATOMIC 1
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+    #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
@@ -83,46 +83,48 @@ void microblaze_enable_interrupts( void );
 /* Critical section macros. */
 void vPortEnterCritical( void );
 void vPortExitCritical( void );
-#define portENTER_CRITICAL()        {                                                       \
-                                        extern UBaseType_t uxCriticalNesting;   \
-                                        microblaze_disable_interrupts();                    \
-                                        uxCriticalNesting++;                                \
-                                    }
+#define portENTER_CRITICAL()                  \
+    {                                         \
+        extern UBaseType_t uxCriticalNesting; \
+        microblaze_disable_interrupts();      \
+        uxCriticalNesting++;                  \
+    }
 
-#define portEXIT_CRITICAL()         {                                                       \
-                                        extern UBaseType_t uxCriticalNesting;   \
-                                        /* Interrupts are disabled, so we can */            \
-                                        /* access the variable directly. */                 \
-                                        uxCriticalNesting--;                                \
-                                        if( uxCriticalNesting == 0 )            \
-                                        {                                                   \
-                                            /* The nesting has unwound and we               \
-                                            can enable interrupts again. */                 \
-                                            portENABLE_INTERRUPTS();                        \
-                                        }                                                   \
-                                    }
+#define portEXIT_CRITICAL()                      \
+    {                                            \
+        extern UBaseType_t uxCriticalNesting;    \
+        /* Interrupts are disabled, so we can */ \
+        /* access the variable directly. */      \
+        uxCriticalNesting--;                     \
+        if( uxCriticalNesting == 0 )             \
+        {                                        \
+            /* The nesting has unwound and we \
+             * can enable interrupts again. */ \
+            portENABLE_INTERRUPTS();           \
+        }                                      \
+    }
 
 /*-----------------------------------------------------------*/
 
 /* Task utilities. */
 void vPortYield( void );
-#define portYIELD() vPortYield()
+#define portYIELD()             vPortYield()
 
 void vTaskSwitchContext();
-#define portYIELD_FROM_ISR() vTaskSwitchContext()
+#define portYIELD_FROM_ISR()    vTaskSwitchContext()
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portBYTE_ALIGNMENT          4
-#define portSTACK_GROWTH            ( -1 )
-#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portNOP()                   asm volatile ( "NOP" )
-#define portMEMORY_BARRIER()        asm volatile ( "" ::: "memory" )
+#define portBYTE_ALIGNMENT    4
+#define portSTACK_GROWTH      ( -1 )
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()               asm volatile ( "NOP" )
+#define portMEMORY_BARRIER()    asm volatile ( "" ::: "memory" )
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/GCC/MicroBlazeV8/port.c b/portable/GCC/MicroBlazeV8/port.c
index 92857417f..5dced2b93 100644
--- a/portable/GCC/MicroBlazeV8/port.c
+++ b/portable/GCC/MicroBlazeV8/port.c
@@ -27,8 +27,8 @@
  */
 
 /*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the MicroBlaze port.
- *----------------------------------------------------------*/
+* Implementation of functions defined in portable.h for the MicroBlaze port.
+*----------------------------------------------------------*/
 
 
 /* Scheduler includes. */
@@ -44,20 +44,20 @@
 #include <microblaze_exceptions_g.h>
 
 /* Tasks are started with a critical section nesting of 0 - however, prior to
-the scheduler being commenced interrupts should not be enabled, so the critical
-nesting variable is initialised to a non-zero value. */
-#define portINITIAL_NESTING_VALUE   ( 0xff )
+ * the scheduler being commenced interrupts should not be enabled, so the critical
+ * nesting variable is initialised to a non-zero value. */
+#define portINITIAL_NESTING_VALUE    ( 0xff )
 
 /* The bit within the MSR register that enabled/disables interrupts and
-exceptions respectively. */
-#define portMSR_IE                  ( 0x02U )
-#define portMSR_EE                  ( 0x100U )
+ * exceptions respectively. */
+#define portMSR_IE                   ( 0x02U )
+#define portMSR_EE                   ( 0x100U )
 
 /* If the floating point unit is included in the MicroBlaze build, then the
-FSR register is saved as part of the task context.  portINITIAL_FSR is the value
-given to the FSR register when the initial context is set up for a task being
-created. */
-#define portINITIAL_FSR             ( 0U )
+ * FSR register is saved as part of the task context.  portINITIAL_FSR is the value
+ * given to the FSR register when the initial context is set up for a task being
+ * created. */
+#define portINITIAL_FSR              ( 0U )
 /*-----------------------------------------------------------*/
 
 /*
@@ -73,27 +73,27 @@ static int32_t prvEnsureInterruptControllerIsInitialised( void );
 /*-----------------------------------------------------------*/
 
 /* Counts the nesting depth of calls to portENTER_CRITICAL().  Each task
-maintains its own count, so this variable is saved as part of the task
-context. */
+ * maintains its own count, so this variable is saved as part of the task
+ * context. */
 volatile UBaseType_t uxCriticalNesting = portINITIAL_NESTING_VALUE;
 
 /* This port uses a separate stack for interrupts.  This prevents the stack of
-every task needing to be large enough to hold an entire interrupt stack on top
-of the task stack. */
-uint32_t *pulISRStack;
+ * every task needing to be large enough to hold an entire interrupt stack on top
+ * of the task stack. */
+uint32_t * pulISRStack;
 
 /* If an interrupt requests a context switch, then ulTaskSwitchRequested will
-get set to 1.  ulTaskSwitchRequested is inspected just before the main interrupt
-handler exits.  If, at that time, ulTaskSwitchRequested is set to 1, the kernel
-will call vTaskSwitchContext() to ensure the task that runs immediately after
-the interrupt exists is the highest priority task that is able to run.  This is
-an unusual mechanism, but is used for this port because a single interrupt can
-cause the servicing of multiple peripherals - and it is inefficient to call
-vTaskSwitchContext() multiple times as each peripheral is serviced. */
+ * get set to 1.  ulTaskSwitchRequested is inspected just before the main interrupt
+ * handler exits.  If, at that time, ulTaskSwitchRequested is set to 1, the kernel
+ * will call vTaskSwitchContext() to ensure the task that runs immediately after
+ * the interrupt exists is the highest priority task that is able to run.  This is
+ * an unusual mechanism, but is used for this port because a single interrupt can
+ * cause the servicing of multiple peripherals - and it is inefficient to call
+ * vTaskSwitchContext() multiple times as each peripheral is serviced. */
 volatile uint32_t ulTaskSwitchRequested = 0UL;
 
 /* The instance of the interrupt controller used by this port.  This is required
-by the Xilinx library API functions. */
+ * by the Xilinx library API functions. */
 static XIntc xInterruptControllerInstance;
 
 /*-----------------------------------------------------------*/
@@ -104,16 +104,18 @@ static XIntc xInterruptControllerInstance;
  *
  * See the portable.h header file.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
-extern void * _SDA2_BASE_;
-extern void * _SDA_BASE_;
-const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_;
-const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_;
+    extern void * _SDA2_BASE_;
+    extern void * _SDA_BASE_;
+    const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_;
+    const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_;
 
     /* Place a few bytes of known values on the bottom of the stack.
-    This is essential for the Microblaze port and these lines must
-    not be omitted. */
+     * This is essential for the Microblaze port and these lines must
+     * not be omitted. */
     *pxTopOfStack = ( StackType_t ) 0x00000000;
     pxTopOfStack--;
     *pxTopOfStack = ( StackType_t ) 0x00000000;
@@ -121,18 +123,18 @@ const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_;
     *pxTopOfStack = ( StackType_t ) 0x00000000;
     pxTopOfStack--;
 
-    #if( XPAR_MICROBLAZE_USE_FPU != 0 )
+    #if ( XPAR_MICROBLAZE_USE_FPU != 0 )
         /* The FSR value placed in the initial task context is just 0. */
         *pxTopOfStack = portINITIAL_FSR;
         pxTopOfStack--;
     #endif
 
     /* The MSR value placed in the initial task context should have interrupts
-    disabled.  Each task will enable interrupts automatically when it enters
-    the running state for the first time. */
+     * disabled.  Each task will enable interrupts automatically when it enters
+     * the running state for the first time. */
     *pxTopOfStack = mfmsr() & ~portMSR_IE;
 
-    #if( MICROBLAZE_EXCEPTIONS_ENABLED == 1 )
+    #if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 )
     {
         /* Ensure exceptions are enabled for the task. */
         *pxTopOfStack |= portMSR_EE;
@@ -142,7 +144,7 @@ const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_;
     pxTopOfStack--;
 
     /* First stack an initial value for the critical section nesting.  This
-    is initialised to zero. */
+     * is initialised to zero. */
     *pxTopOfStack = ( StackType_t ) 0x00;
 
     /* R0 is always zero. */
@@ -150,33 +152,33 @@ const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_;
 
     /* Place an initial value for all the general purpose registers. */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) ulR2;   /* R2 - read only small data area. */
+    *pxTopOfStack = ( StackType_t ) ulR2;         /* R2 - read only small data area. */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x03;   /* R3 - return values and temporaries. */
+    *pxTopOfStack = ( StackType_t ) 0x03;         /* R3 - return values and temporaries. */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x04;   /* R4 - return values and temporaries. */
+    *pxTopOfStack = ( StackType_t ) 0x04;         /* R4 - return values and temporaries. */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) pvParameters;/* R5 contains the function call parameters. */
+    *pxTopOfStack = ( StackType_t ) pvParameters; /* R5 contains the function call parameters. */
 
     #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
         pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x06;   /* R6 - other parameters and temporaries.  Used as the return address from vPortTaskEntryPoint. */
+        *pxTopOfStack = ( StackType_t ) 0x06; /* R6 - other parameters and temporaries.  Used as the return address from vPortTaskEntryPoint. */
         pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x07;   /* R7 - other parameters and temporaries. */
+        *pxTopOfStack = ( StackType_t ) 0x07; /* R7 - other parameters and temporaries. */
         pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x08;   /* R8 - other parameters and temporaries. */
+        *pxTopOfStack = ( StackType_t ) 0x08; /* R8 - other parameters and temporaries. */
         pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x09;   /* R9 - other parameters and temporaries. */
+        *pxTopOfStack = ( StackType_t ) 0x09; /* R9 - other parameters and temporaries. */
         pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x0a;   /* R10 - other parameters and temporaries. */
+        *pxTopOfStack = ( StackType_t ) 0x0a; /* R10 - other parameters and temporaries. */
         pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x0b;   /* R11 - temporaries. */
+        *pxTopOfStack = ( StackType_t ) 0x0b; /* R11 - temporaries. */
         pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x0c;   /* R12 - temporaries. */
+        *pxTopOfStack = ( StackType_t ) 0x0c; /* R12 - temporaries. */
         pxTopOfStack--;
-    #else
-        pxTopOfStack-= 8;
-    #endif
+    #else /* ifdef portPRE_LOAD_STACK_FOR_DEBUGGING */
+        pxTopOfStack -= 8;
+    #endif /* ifdef portPRE_LOAD_STACK_FOR_DEBUGGING */
 
     *pxTopOfStack = ( StackType_t ) ulR13;  /* R13 - read/write small data area. */
     pxTopOfStack--;
@@ -186,79 +188,79 @@ const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_;
 
     #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
         pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x10;   /* R16 - return address for trap (debugger). */
+        *pxTopOfStack = ( StackType_t ) 0x10; /* R16 - return address for trap (debugger). */
         pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x11;   /* R17 - return address for exceptions, if configured. */
+        *pxTopOfStack = ( StackType_t ) 0x11; /* R17 - return address for exceptions, if configured. */
         pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x12;   /* R18 - reserved for assembler and compiler temporaries. */
+        *pxTopOfStack = ( StackType_t ) 0x12; /* R18 - reserved for assembler and compiler temporaries. */
         pxTopOfStack--;
     #else
         pxTopOfStack -= 4;
     #endif
 
-    *pxTopOfStack = ( StackType_t ) 0x00;   /* R19 - must be saved across function calls. Callee-save.  Seems to be interpreted as the frame pointer. */
+    *pxTopOfStack = ( StackType_t ) 0x00; /* R19 - must be saved across function calls. Callee-save.  Seems to be interpreted as the frame pointer. */
 
     #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
         pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x14;   /* R20 - reserved for storing a pointer to the Global Offset Table (GOT) in Position Independent Code (PIC). Non-volatile in non-PIC code. Must be saved across function calls. Callee-save.  Not used by FreeRTOS. */
+        *pxTopOfStack = ( StackType_t ) 0x14; /* R20 - reserved for storing a pointer to the Global Offset Table (GOT) in Position Independent Code (PIC). Non-volatile in non-PIC code. Must be saved across function calls. Callee-save.  Not used by FreeRTOS. */
         pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x15;   /* R21 - must be saved across function calls. Callee-save. */
+        *pxTopOfStack = ( StackType_t ) 0x15; /* R21 - must be saved across function calls. Callee-save. */
         pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x16;   /* R22 - must be saved across function calls. Callee-save. */
+        *pxTopOfStack = ( StackType_t ) 0x16; /* R22 - must be saved across function calls. Callee-save. */
         pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x17;   /* R23 - must be saved across function calls. Callee-save. */
+        *pxTopOfStack = ( StackType_t ) 0x17; /* R23 - must be saved across function calls. Callee-save. */
         pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x18;   /* R24 - must be saved across function calls. Callee-save. */
+        *pxTopOfStack = ( StackType_t ) 0x18; /* R24 - must be saved across function calls. Callee-save. */
         pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x19;   /* R25 - must be saved across function calls. Callee-save. */
+        *pxTopOfStack = ( StackType_t ) 0x19; /* R25 - must be saved across function calls. Callee-save. */
         pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x1a;   /* R26 - must be saved across function calls. Callee-save. */
+        *pxTopOfStack = ( StackType_t ) 0x1a; /* R26 - must be saved across function calls. Callee-save. */
         pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x1b;   /* R27 - must be saved across function calls. Callee-save. */
+        *pxTopOfStack = ( StackType_t ) 0x1b; /* R27 - must be saved across function calls. Callee-save. */
         pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x1c;   /* R28 - must be saved across function calls. Callee-save. */
+        *pxTopOfStack = ( StackType_t ) 0x1c; /* R28 - must be saved across function calls. Callee-save. */
         pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x1d;   /* R29 - must be saved across function calls. Callee-save. */
+        *pxTopOfStack = ( StackType_t ) 0x1d; /* R29 - must be saved across function calls. Callee-save. */
         pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x1e;   /* R30 - must be saved across function calls. Callee-save. */
+        *pxTopOfStack = ( StackType_t ) 0x1e; /* R30 - must be saved across function calls. Callee-save. */
         pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x1f;   /* R31 - must be saved across function calls. Callee-save. */
+        *pxTopOfStack = ( StackType_t ) 0x1f; /* R31 - must be saved across function calls. Callee-save. */
         pxTopOfStack--;
-    #else
+    #else /* ifdef portPRE_LOAD_STACK_FOR_DEBUGGING */
         pxTopOfStack -= 13;
-    #endif
+    #endif /* ifdef portPRE_LOAD_STACK_FOR_DEBUGGING */
 
     /* Return a pointer to the top of the stack that has been generated so this
-    can be stored in the task control block for the task. */
+     * can be stored in the task control block for the task. */
     return pxTopOfStack;
 }
 /*-----------------------------------------------------------*/
 
 BaseType_t xPortStartScheduler( void )
 {
-extern void ( vPortStartFirstTask )( void );
-extern uint32_t _stack[];
+    extern void( vPortStartFirstTask )( void );
+    extern uint32_t _stack[];
 
     /* Setup the hardware to generate the tick.  Interrupts are disabled when
-    this function is called.
-
-    This port uses an application defined callback function to install the tick
-    interrupt handler because the kernel will run on lots of different
-    MicroBlaze and FPGA configurations - not all of which will have the same
-    timer peripherals defined or available.  An example definition of
-    vApplicationSetupTimerInterrupt() is provided in the official demo
-    application that accompanies this port. */
+     * this function is called.
+     *
+     * This port uses an application defined callback function to install the tick
+     * interrupt handler because the kernel will run on lots of different
+     * MicroBlaze and FPGA configurations - not all of which will have the same
+     * timer peripherals defined or available.  An example definition of
+     * vApplicationSetupTimerInterrupt() is provided in the official demo
+     * application that accompanies this port. */
     vApplicationSetupTimerInterrupt();
 
     /* Reuse the stack from main() as the stack for the interrupts/exceptions. */
     pulISRStack = ( uint32_t * ) _stack;
 
     /* Ensure there is enough space for the functions called from the interrupt
-    service routines to write back into the stack frame of the caller. */
+     * service routines to write back into the stack frame of the caller. */
     pulISRStack -= 2;
 
     /* Restore the context of the first task that is going to run.  From here
-    on, the created tasks will be executing. */
+     * on, the created tasks will be executing. */
     vPortStartFirstTask();
 
     /* Should not get here as the tasks are now running! */
@@ -269,7 +271,7 @@ extern uint32_t _stack[];
 void vPortEndScheduler( void )
 {
     /* Not implemented in ports where there is nothing to return to.
-    Artificially force an assert. */
+     * Artificially force an assert. */
     configASSERT( uxCriticalNesting == 1000UL );
 }
 /*-----------------------------------------------------------*/
@@ -279,17 +281,17 @@ void vPortEndScheduler( void )
  */
 void vPortYield( void )
 {
-extern void VPortYieldASM( void );
+    extern void VPortYieldASM( void );
 
     /* Perform the context switch in a critical section to assure it is
-    not interrupted by the tick ISR.  It is not a problem to do this as
-    each task maintains its own interrupt status. */
+     * not interrupted by the tick ISR.  It is not a problem to do this as
+     * each task maintains its own interrupt status. */
     portENTER_CRITICAL();
     {
         /* Jump directly to the yield function to ensure there is no
-        compiler generated prologue code. */
-        asm volatile (  "bralid r14, VPortYieldASM      \n\t" \
-                        "or r0, r0, r0                  \n\t" );
+         * compiler generated prologue code. */
+        asm volatile ( "bralid r14, VPortYieldASM      \n\t" \
+                       "or r0, r0, r0                  \n\t" );
     }
     portEXIT_CRITICAL();
 }
@@ -297,12 +299,13 @@ extern void VPortYieldASM( void );
 
 void vPortEnableInterrupt( uint8_t ucInterruptID )
 {
-int32_t lReturn;
+    int32_t lReturn;
 
     /* An API function is provided to enable an interrupt in the interrupt
-    controller because the interrupt controller instance variable is private
-    to this file. */
+     * controller because the interrupt controller instance variable is private
+     * to this file. */
     lReturn = prvEnsureInterruptControllerIsInitialised();
+
     if( lReturn == pdPASS )
     {
         XIntc_Enable( &xInterruptControllerInstance, ucInterruptID );
@@ -314,11 +317,11 @@ int32_t lReturn;
 
 void vPortDisableInterrupt( uint8_t ucInterruptID )
 {
-int32_t lReturn;
+    int32_t lReturn;
 
     /* An API function is provided to disable an interrupt in the interrupt
-    controller because the interrupt controller instance variable is private
-    to this file. */
+     * controller because the interrupt controller instance variable is private
+     * to this file. */
     lReturn = prvEnsureInterruptControllerIsInitialised();
 
     if( lReturn == pdPASS )
@@ -330,12 +333,14 @@ int32_t lReturn;
 }
 /*-----------------------------------------------------------*/
 
-BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef )
+BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID,
+                                         XInterruptHandler pxHandler,
+                                         void * pvCallBackRef )
 {
-int32_t lReturn;
+    int32_t lReturn;
 
     /* An API function is provided to install an interrupt handler because the
-    interrupt controller instance variable is private to this file. */
+     * interrupt controller instance variable is private to this file. */
 
     lReturn = prvEnsureInterruptControllerIsInitialised();
 
@@ -357,11 +362,11 @@ int32_t lReturn;
 
 static int32_t prvEnsureInterruptControllerIsInitialised( void )
 {
-static int32_t lInterruptControllerInitialised = pdFALSE;
-int32_t lReturn;
+    static int32_t lInterruptControllerInitialised = pdFALSE;
+    int32_t lReturn;
 
     /* Ensure the interrupt controller instance variable is initialised before
-    it is used, and that the initialisation only happens once. */
+     * it is used, and that the initialisation only happens once. */
     if( lInterruptControllerInitialised != pdTRUE )
     {
         lReturn = prvInitialiseInterruptController();
@@ -384,19 +389,19 @@ int32_t lReturn;
  * Handler for the timer interrupt.  This is the handler that the application
  * defined callback function vApplicationSetupTimerInterrupt() should install.
  */
-void vPortTickISR( void *pvUnused )
+void vPortTickISR( void * pvUnused )
 {
-extern void vApplicationClearTimerInterrupt( void );
+    extern void vApplicationClearTimerInterrupt( void );
 
     /* Ensure the unused parameter does not generate a compiler warning. */
     ( void ) pvUnused;
 
     /* This port uses an application defined callback function to clear the tick
-    interrupt because the kernel will run on lots of different MicroBlaze and
-    FPGA configurations - not all of which will have the same timer peripherals
-    defined or available.  An example definition of
-    vApplicationClearTimerInterrupt() is provided in the official demo
-    application that accompanies this port. */
+     * interrupt because the kernel will run on lots of different MicroBlaze and
+     * FPGA configurations - not all of which will have the same timer peripherals
+     * defined or available.  An example definition of
+     * vApplicationClearTimerInterrupt() is provided in the official demo
+     * application that accompanies this port. */
     vApplicationClearTimerInterrupt();
 
     /* Increment the RTOS tick - this might cause a task to unblock. */
@@ -410,7 +415,7 @@ extern void vApplicationClearTimerInterrupt( void );
 
 static int32_t prvInitialiseInterruptController( void )
 {
-int32_t lStatus;
+    int32_t lStatus;
 
     lStatus = XIntc_Initialize( &xInterruptControllerInstance, configINTERRUPT_CONTROLLER_TO_USE );
 
@@ -423,8 +428,8 @@ int32_t lStatus;
         XIntc_SetIntrSvcOption( xInterruptControllerInstance.BaseAddress, XIN_SVC_ALL_ISRS_OPTION );
 
         /* Install exception handlers if the MicroBlaze is configured to handle
-        exceptions, and the application defined constant
-        configINSTALL_EXCEPTION_HANDLERS is set to 1. */
+         * exceptions, and the application defined constant
+         * configINSTALL_EXCEPTION_HANDLERS is set to 1. */
         #if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )
         {
             vPortExceptionsInstallHandlers();
@@ -432,7 +437,7 @@ int32_t lStatus;
         #endif /* MICROBLAZE_EXCEPTIONS_ENABLED */
 
         /* Start the interrupt controller.  Interrupts are enabled when the
-        scheduler starts. */
+         * scheduler starts. */
         lStatus = XIntc_Start( &xInterruptControllerInstance, XIN_REAL_MODE );
 
         if( lStatus == XST_SUCCESS )
diff --git a/portable/GCC/MicroBlazeV8/port_exceptions.c b/portable/GCC/MicroBlazeV8/port_exceptions.c
index 52055fc3c..e2347732d 100644
--- a/portable/GCC/MicroBlazeV8/port_exceptions.c
+++ b/portable/GCC/MicroBlazeV8/port_exceptions.c
@@ -35,246 +35,244 @@
 #include <microblaze_exceptions_g.h>
 
 /* The Xilinx library defined exception entry point stacks a number of
-registers.  These definitions are offsets from the stack pointer to the various
-stacked register values. */
-#define portexR3_STACK_OFFSET   4
-#define portexR4_STACK_OFFSET   5
-#define portexR5_STACK_OFFSET   6
-#define portexR6_STACK_OFFSET   7
-#define portexR7_STACK_OFFSET   8
-#define portexR8_STACK_OFFSET   9
-#define portexR9_STACK_OFFSET   10
-#define portexR10_STACK_OFFSET  11
-#define portexR11_STACK_OFFSET  12
-#define portexR12_STACK_OFFSET  13
-#define portexR15_STACK_OFFSET  16
-#define portexR18_STACK_OFFSET  19
-#define portexMSR_STACK_OFFSET  20
-#define portexR19_STACK_OFFSET  -1
+ * registers.  These definitions are offsets from the stack pointer to the various
+ * stacked register values. */
+#define portexR3_STACK_OFFSET                 4
+#define portexR4_STACK_OFFSET                 5
+#define portexR5_STACK_OFFSET                 6
+#define portexR6_STACK_OFFSET                 7
+#define portexR7_STACK_OFFSET                 8
+#define portexR8_STACK_OFFSET                 9
+#define portexR9_STACK_OFFSET                 10
+#define portexR10_STACK_OFFSET                11
+#define portexR11_STACK_OFFSET                12
+#define portexR12_STACK_OFFSET                13
+#define portexR15_STACK_OFFSET                16
+#define portexR18_STACK_OFFSET                19
+#define portexMSR_STACK_OFFSET                20
+#define portexR19_STACK_OFFSET                -1
 
 /* This is defined to equal the size, in bytes, of the stack frame generated by
-the Xilinx standard library exception entry point.  It is required to determine
-the stack pointer value prior to the exception being entered. */
-#define portexASM_HANDLER_STACK_FRAME_SIZE 84UL
+ * the Xilinx standard library exception entry point.  It is required to determine
+ * the stack pointer value prior to the exception being entered. */
+#define portexASM_HANDLER_STACK_FRAME_SIZE    84UL
 
 /* The number of bytes a MicroBlaze instruction consumes. */
-#define portexINSTRUCTION_SIZE  4
+#define portexINSTRUCTION_SIZE                4
 
 /* Exclude this entire file if the MicroBlaze is not configured to handle
-exceptions, or the application defined configuration constant
-configINSTALL_EXCEPTION_HANDLERS is not set to 1. */
+ * exceptions, or the application defined configuration constant
+ * configINSTALL_EXCEPTION_HANDLERS is not set to 1. */
 #if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )
 
 /* This variable is set in the exception entry code, before
-vPortExceptionHandler is called. */
-uint32_t *pulStackPointerOnFunctionEntry = NULL;
+ * vPortExceptionHandler is called. */
+    uint32_t * pulStackPointerOnFunctionEntry = NULL;
 
 /* This is the structure that is filled with the MicroBlaze context as it
-existed immediately prior to the exception occurrence.  A pointer to this
-structure is passed into the vApplicationExceptionRegisterDump() callback
-function, if one is defined. */
-static xPortRegisterDump xRegisterDump;
+ * existed immediately prior to the exception occurrence.  A pointer to this
+ * structure is passed into the vApplicationExceptionRegisterDump() callback
+ * function, if one is defined. */
+    static xPortRegisterDump xRegisterDump;
 
 /* This is the FreeRTOS exception handler that is installed for all exception
-types.  It is called from vPortExceptionHanlderEntry() - which is itself defined
-in portasm.S. */
-void vPortExceptionHandler( void *pvExceptionID );
-extern void vPortExceptionHandlerEntry( void *pvExceptionID );
+ * types.  It is called from vPortExceptionHandlerEntry() - which is itself defined
+ * in portasm.S. */
+    void vPortExceptionHandler( void * pvExceptionID );
+    extern void vPortExceptionHandlerEntry( void * pvExceptionID );
 
 /*-----------------------------------------------------------*/
 
 /* vApplicationExceptionRegisterDump() is a callback function that the
-application can optionally define to receive a populated xPortRegisterDump
-structure.  If the application chooses not to define a version of
-vApplicationExceptionRegisterDump() then this weekly defined default
-implementation will be called instead. */
-extern void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump ) __attribute__((weak));
-void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump )
-{
-    ( void ) xRegisterDump;
-
-    for( ;; )
+ * application can optionally define to receive a populated xPortRegisterDump
+ * structure.  If the application chooses not to define a version of
+ * vApplicationExceptionRegisterDump() then this weekly defined default
+ * implementation will be called instead. */
+    extern void vApplicationExceptionRegisterDump( xPortRegisterDump * xRegisterDump ) __attribute__( ( weak ) );
+    void vApplicationExceptionRegisterDump( xPortRegisterDump * xRegisterDump )
     {
-        portNOP();
+        ( void ) xRegisterDump;
+
+        for( ; ; )
+        {
+            portNOP();
+        }
     }
-}
 /*-----------------------------------------------------------*/
 
-void vPortExceptionHandler( void *pvExceptionID )
-{
-extern void *pxCurrentTCB;
-
-    /* Fill an xPortRegisterDump structure with the MicroBlaze context as it
-    was immediately before the exception occurrence. */
-
-    /* First fill in the name and handle of the task that was in the Running
-    state when the exception occurred. */
-    xRegisterDump.xCurrentTaskHandle = pxCurrentTCB;
-    xRegisterDump.pcCurrentTaskName = pcTaskGetName( NULL );
-
-    configASSERT( pulStackPointerOnFunctionEntry );
-
-    /* Obtain the values of registers that were stacked prior to this function
-    being called, and may have changed since they were stacked. */
-    xRegisterDump.ulR3 = pulStackPointerOnFunctionEntry[ portexR3_STACK_OFFSET ];
-    xRegisterDump.ulR4 = pulStackPointerOnFunctionEntry[ portexR4_STACK_OFFSET ];
-    xRegisterDump.ulR5 = pulStackPointerOnFunctionEntry[ portexR5_STACK_OFFSET ];
-    xRegisterDump.ulR6 = pulStackPointerOnFunctionEntry[ portexR6_STACK_OFFSET ];
-    xRegisterDump.ulR7 = pulStackPointerOnFunctionEntry[ portexR7_STACK_OFFSET ];
-    xRegisterDump.ulR8 = pulStackPointerOnFunctionEntry[ portexR8_STACK_OFFSET ];
-    xRegisterDump.ulR9 = pulStackPointerOnFunctionEntry[ portexR9_STACK_OFFSET ];
-    xRegisterDump.ulR10 = pulStackPointerOnFunctionEntry[ portexR10_STACK_OFFSET ];
-    xRegisterDump.ulR11 = pulStackPointerOnFunctionEntry[ portexR11_STACK_OFFSET ];
-    xRegisterDump.ulR12 = pulStackPointerOnFunctionEntry[ portexR12_STACK_OFFSET ];
-    xRegisterDump.ulR15_return_address_from_subroutine = pulStackPointerOnFunctionEntry[ portexR15_STACK_OFFSET ];
-    xRegisterDump.ulR18 = pulStackPointerOnFunctionEntry[ portexR18_STACK_OFFSET ];
-    xRegisterDump.ulR19 = pulStackPointerOnFunctionEntry[ portexR19_STACK_OFFSET ];
-    xRegisterDump.ulMSR = pulStackPointerOnFunctionEntry[ portexMSR_STACK_OFFSET ];
-
-    /* Obtain the value of all other registers. */
-    xRegisterDump.ulR2_small_data_area = mfgpr( R2 );
-    xRegisterDump.ulR13_read_write_small_data_area = mfgpr( R13 );
-    xRegisterDump.ulR14_return_address_from_interrupt = mfgpr( R14 );
-    xRegisterDump.ulR16_return_address_from_trap = mfgpr( R16 );
-    xRegisterDump.ulR17_return_address_from_exceptions = mfgpr( R17 );
-    xRegisterDump.ulR20 = mfgpr( R20 );
-    xRegisterDump.ulR21 = mfgpr( R21 );
-    xRegisterDump.ulR22 = mfgpr( R22 );
-    xRegisterDump.ulR23 = mfgpr( R23 );
-    xRegisterDump.ulR24 = mfgpr( R24 );
-    xRegisterDump.ulR25 = mfgpr( R25 );
-    xRegisterDump.ulR26 = mfgpr( R26 );
-    xRegisterDump.ulR27 = mfgpr( R27 );
-    xRegisterDump.ulR28 = mfgpr( R28 );
-    xRegisterDump.ulR29 = mfgpr( R29 );
-    xRegisterDump.ulR30 = mfgpr( R30 );
-    xRegisterDump.ulR31 = mfgpr( R31 );
-    xRegisterDump.ulR1_SP = ( ( uint32_t ) pulStackPointerOnFunctionEntry ) + portexASM_HANDLER_STACK_FRAME_SIZE;
-    xRegisterDump.ulEAR = mfear();
-    xRegisterDump.ulESR = mfesr();
-    xRegisterDump.ulEDR = mfedr();
-
-    /* Move the saved program counter back to the instruction that was executed
-    when the exception occurred.  This is only valid for certain types of
-    exception. */
-    xRegisterDump.ulPC = xRegisterDump.ulR17_return_address_from_exceptions - portexINSTRUCTION_SIZE;
-
-    #if( XPAR_MICROBLAZE_USE_FPU != 0 )
+    void vPortExceptionHandler( void * pvExceptionID )
     {
-        xRegisterDump.ulFSR = mffsr();
-    }
-    #else
-    {
-        xRegisterDump.ulFSR = 0UL;
-    }
-    #endif
+        extern void * pxCurrentTCB;
 
-    /* Also fill in a string that describes what type of exception this is.
-    The string uses the same ID names as defined in the MicroBlaze standard
-    library exception header files. */
-    switch( ( uint32_t ) pvExceptionID )
-    {
-        case XEXC_ID_FSL :
+        /* Fill an xPortRegisterDump structure with the MicroBlaze context as it
+         * was immediately before the exception occurrence. */
+
+        /* First fill in the name and handle of the task that was in the Running
+         * state when the exception occurred. */
+        xRegisterDump.xCurrentTaskHandle = pxCurrentTCB;
+        xRegisterDump.pcCurrentTaskName = pcTaskGetName( NULL );
+
+        configASSERT( pulStackPointerOnFunctionEntry );
+
+        /* Obtain the values of registers that were stacked prior to this function
+         * being called, and may have changed since they were stacked. */
+        xRegisterDump.ulR3 = pulStackPointerOnFunctionEntry[ portexR3_STACK_OFFSET ];
+        xRegisterDump.ulR4 = pulStackPointerOnFunctionEntry[ portexR4_STACK_OFFSET ];
+        xRegisterDump.ulR5 = pulStackPointerOnFunctionEntry[ portexR5_STACK_OFFSET ];
+        xRegisterDump.ulR6 = pulStackPointerOnFunctionEntry[ portexR6_STACK_OFFSET ];
+        xRegisterDump.ulR7 = pulStackPointerOnFunctionEntry[ portexR7_STACK_OFFSET ];
+        xRegisterDump.ulR8 = pulStackPointerOnFunctionEntry[ portexR8_STACK_OFFSET ];
+        xRegisterDump.ulR9 = pulStackPointerOnFunctionEntry[ portexR9_STACK_OFFSET ];
+        xRegisterDump.ulR10 = pulStackPointerOnFunctionEntry[ portexR10_STACK_OFFSET ];
+        xRegisterDump.ulR11 = pulStackPointerOnFunctionEntry[ portexR11_STACK_OFFSET ];
+        xRegisterDump.ulR12 = pulStackPointerOnFunctionEntry[ portexR12_STACK_OFFSET ];
+        xRegisterDump.ulR15_return_address_from_subroutine = pulStackPointerOnFunctionEntry[ portexR15_STACK_OFFSET ];
+        xRegisterDump.ulR18 = pulStackPointerOnFunctionEntry[ portexR18_STACK_OFFSET ];
+        xRegisterDump.ulR19 = pulStackPointerOnFunctionEntry[ portexR19_STACK_OFFSET ];
+        xRegisterDump.ulMSR = pulStackPointerOnFunctionEntry[ portexMSR_STACK_OFFSET ];
+
+        /* Obtain the value of all other registers. */
+        xRegisterDump.ulR2_small_data_area = mfgpr( R2 );
+        xRegisterDump.ulR13_read_write_small_data_area = mfgpr( R13 );
+        xRegisterDump.ulR14_return_address_from_interrupt = mfgpr( R14 );
+        xRegisterDump.ulR16_return_address_from_trap = mfgpr( R16 );
+        xRegisterDump.ulR17_return_address_from_exceptions = mfgpr( R17 );
+        xRegisterDump.ulR20 = mfgpr( R20 );
+        xRegisterDump.ulR21 = mfgpr( R21 );
+        xRegisterDump.ulR22 = mfgpr( R22 );
+        xRegisterDump.ulR23 = mfgpr( R23 );
+        xRegisterDump.ulR24 = mfgpr( R24 );
+        xRegisterDump.ulR25 = mfgpr( R25 );
+        xRegisterDump.ulR26 = mfgpr( R26 );
+        xRegisterDump.ulR27 = mfgpr( R27 );
+        xRegisterDump.ulR28 = mfgpr( R28 );
+        xRegisterDump.ulR29 = mfgpr( R29 );
+        xRegisterDump.ulR30 = mfgpr( R30 );
+        xRegisterDump.ulR31 = mfgpr( R31 );
+        xRegisterDump.ulR1_SP = ( ( uint32_t ) pulStackPointerOnFunctionEntry ) + portexASM_HANDLER_STACK_FRAME_SIZE;
+        xRegisterDump.ulEAR = mfear();
+        xRegisterDump.ulESR = mfesr();
+        xRegisterDump.ulEDR = mfedr();
+
+        /* Move the saved program counter back to the instruction that was executed
+         * when the exception occurred.  This is only valid for certain types of
+         * exception. */
+        xRegisterDump.ulPC = xRegisterDump.ulR17_return_address_from_exceptions - portexINSTRUCTION_SIZE;
+
+        #if ( XPAR_MICROBLAZE_USE_FPU != 0 )
+        {
+            xRegisterDump.ulFSR = mffsr();
+        }
+        #else
+        {
+            xRegisterDump.ulFSR = 0UL;
+        }
+        #endif
+
+        /* Also fill in a string that describes what type of exception this is.
+         * The string uses the same ID names as defined in the MicroBlaze standard
+         * library exception header files. */
+        switch( ( uint32_t ) pvExceptionID )
+        {
+            case XEXC_ID_FSL:
                 xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_FSL";
                 break;
 
-        case XEXC_ID_UNALIGNED_ACCESS :
+            case XEXC_ID_UNALIGNED_ACCESS:
                 xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_UNALIGNED_ACCESS";
                 break;
 
-        case XEXC_ID_ILLEGAL_OPCODE :
+            case XEXC_ID_ILLEGAL_OPCODE:
                 xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_ILLEGAL_OPCODE";
                 break;
 
-        case XEXC_ID_M_AXI_I_EXCEPTION :
+            case XEXC_ID_M_AXI_I_EXCEPTION:
                 xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_M_AXI_I_EXCEPTION or XEXC_ID_IPLB_EXCEPTION";
                 break;
 
-        case XEXC_ID_M_AXI_D_EXCEPTION :
+            case XEXC_ID_M_AXI_D_EXCEPTION:
                 xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_M_AXI_D_EXCEPTION or XEXC_ID_DPLB_EXCEPTION";
                 break;
 
-        case XEXC_ID_DIV_BY_ZERO :
+            case XEXC_ID_DIV_BY_ZERO:
                 xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_DIV_BY_ZERO";
                 break;
 
-        case XEXC_ID_STACK_VIOLATION :
+            case XEXC_ID_STACK_VIOLATION:
                 xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_STACK_VIOLATION or XEXC_ID_MMU";
                 break;
 
-        #if( XPAR_MICROBLAZE_USE_FPU != 0 )
-
-            case XEXC_ID_FPU :
+                #if ( XPAR_MICROBLAZE_USE_FPU != 0 )
+                    case XEXC_ID_FPU:
                         xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_FPU see ulFSR value";
                         break;
+                #endif /* XPAR_MICROBLAZE_USE_FPU */
+        }
 
-        #endif /* XPAR_MICROBLAZE_USE_FPU */
+        /* vApplicationExceptionRegisterDump() is a callback function that the
+         * application can optionally define to receive the populated xPortRegisterDump
+         * structure.  If the application chooses not to define a version of
+         * vApplicationExceptionRegisterDump() then the weekly defined default
+         * implementation within this file will be called instead. */
+        vApplicationExceptionRegisterDump( &xRegisterDump );
+
+        /* Must not attempt to leave this function! */
+        for( ; ; )
+        {
+            portNOP();
+        }
     }
-
-    /* vApplicationExceptionRegisterDump() is a callback function that the
-    application can optionally define to receive the populated xPortRegisterDump
-    structure.  If the application chooses not to define a version of
-    vApplicationExceptionRegisterDump() then the weekly defined default
-    implementation within this file will be called instead. */
-    vApplicationExceptionRegisterDump( &xRegisterDump );
-
-    /* Must not attempt to leave this function! */
-    for( ;; )
-    {
-        portNOP();
-    }
-}
 /*-----------------------------------------------------------*/
 
-void vPortExceptionsInstallHandlers( void )
-{
-static uint32_t ulHandlersAlreadyInstalled = pdFALSE;
-
-    if( ulHandlersAlreadyInstalled == pdFALSE )
+    void vPortExceptionsInstallHandlers( void )
     {
-        ulHandlersAlreadyInstalled = pdTRUE;
+        static uint32_t ulHandlersAlreadyInstalled = pdFALSE;
 
-        #if XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS == 1
-            microblaze_register_exception_handler( XEXC_ID_UNALIGNED_ACCESS, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_UNALIGNED_ACCESS );
-        #endif /* XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS*/
+        if( ulHandlersAlreadyInstalled == pdFALSE )
+        {
+            ulHandlersAlreadyInstalled = pdTRUE;
 
-        #if XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION == 1
-            microblaze_register_exception_handler( XEXC_ID_ILLEGAL_OPCODE, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_ILLEGAL_OPCODE );
-        #endif /* XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION */
+            #if XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS == 1
+                microblaze_register_exception_handler( XEXC_ID_UNALIGNED_ACCESS, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_UNALIGNED_ACCESS );
+            #endif /* XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS*/
 
-        #if XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION == 1
-            microblaze_register_exception_handler( XEXC_ID_M_AXI_I_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_I_EXCEPTION );
-        #endif /* XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION */
+            #if XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION == 1
+                microblaze_register_exception_handler( XEXC_ID_ILLEGAL_OPCODE, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_ILLEGAL_OPCODE );
+            #endif /* XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION */
 
-        #if XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION == 1
-            microblaze_register_exception_handler( XEXC_ID_M_AXI_D_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_D_EXCEPTION );
-        #endif /* XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION */
+            #if XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION == 1
+                microblaze_register_exception_handler( XEXC_ID_M_AXI_I_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_I_EXCEPTION );
+            #endif /* XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION */
 
-        #if XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION == 1
-            microblaze_register_exception_handler( XEXC_ID_IPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_IPLB_EXCEPTION );
-        #endif /* XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION */
+            #if XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION == 1
+                microblaze_register_exception_handler( XEXC_ID_M_AXI_D_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_D_EXCEPTION );
+            #endif /* XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION */
 
-        #if XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION == 1
-            microblaze_register_exception_handler( XEXC_ID_DPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DPLB_EXCEPTION );
-        #endif /* XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION */
+            #if XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION == 1
+                microblaze_register_exception_handler( XEXC_ID_IPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_IPLB_EXCEPTION );
+            #endif /* XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION */
 
-        #if XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION == 1
-            microblaze_register_exception_handler( XEXC_ID_DIV_BY_ZERO, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DIV_BY_ZERO );
-        #endif /* XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION */
+            #if XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION == 1
+                microblaze_register_exception_handler( XEXC_ID_DPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DPLB_EXCEPTION );
+            #endif /* XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION */
 
-        #if XPAR_MICROBLAZE_FPU_EXCEPTION == 1
-            microblaze_register_exception_handler( XEXC_ID_FPU, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FPU );
-        #endif /* XPAR_MICROBLAZE_FPU_EXCEPTION */
+            #if XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION == 1
+                microblaze_register_exception_handler( XEXC_ID_DIV_BY_ZERO, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DIV_BY_ZERO );
+            #endif /* XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION */
 
-        #if XPAR_MICROBLAZE_FSL_EXCEPTION == 1
-            microblaze_register_exception_handler( XEXC_ID_FSL, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FSL );
-        #endif /* XPAR_MICROBLAZE_FSL_EXCEPTION */
+            #if XPAR_MICROBLAZE_FPU_EXCEPTION == 1
+                microblaze_register_exception_handler( XEXC_ID_FPU, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FPU );
+            #endif /* XPAR_MICROBLAZE_FPU_EXCEPTION */
 
-        microblaze_enable_exceptions();
+            #if XPAR_MICROBLAZE_FSL_EXCEPTION == 1
+                microblaze_register_exception_handler( XEXC_ID_FSL, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FSL );
+            #endif /* XPAR_MICROBLAZE_FSL_EXCEPTION */
+
+            microblaze_enable_exceptions();
+        }
     }
-}
 
 /* Exclude the entire file if the MicroBlaze is not configured to handle
-exceptions, or the application defined configuration item
-configINSTALL_EXCEPTION_HANDLERS is not set to 1. */
+ * exceptions, or the application defined configuration item
+ * configINSTALL_EXCEPTION_HANDLERS is not set to 1. */
 #endif /* ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) */
diff --git a/portable/GCC/MicroBlazeV8/portmacro.h b/portable/GCC/MicroBlazeV8/portmacro.h
index 3ade98795..7606850bc 100644
--- a/portable/GCC/MicroBlazeV8/portmacro.h
+++ b/portable/GCC/MicroBlazeV8/portmacro.h
@@ -50,28 +50,28 @@
  */
 
 /* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint32_t
-#define portBASE_TYPE   long
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-    not need to be guarded with a critical section. */
-    #define portTICK_TYPE_IS_ATOMIC 1
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+    #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
@@ -87,88 +87,93 @@ void microblaze_enable_interrupts( void );
 /* Critical section macros. */
 void vPortEnterCritical( void );
 void vPortExitCritical( void );
-#define portENTER_CRITICAL()        {                                                               \
-                                        extern volatile UBaseType_t uxCriticalNesting;              \
-                                        microblaze_disable_interrupts();                            \
-                                        uxCriticalNesting++;                                        \
-                                    }
+#define portENTER_CRITICAL()                           \
+    {                                                  \
+        extern volatile UBaseType_t uxCriticalNesting; \
+        microblaze_disable_interrupts();               \
+        uxCriticalNesting++;                           \
+    }
 
-#define portEXIT_CRITICAL()         {                                                               \
-                                        extern volatile UBaseType_t uxCriticalNesting;              \
-                                        /* Interrupts are disabled, so we can */                    \
-                                        /* access the variable directly. */                         \
-                                        uxCriticalNesting--;                                        \
-                                        if( uxCriticalNesting == 0 )                                \
-                                        {                                                           \
-                                            /* The nesting has unwound and we                       \
-                                            can enable interrupts again. */                         \
-                                            portENABLE_INTERRUPTS();                                \
-                                        }                                                           \
-                                    }
+#define portEXIT_CRITICAL()                            \
+    {                                                  \
+        extern volatile UBaseType_t uxCriticalNesting; \
+        /* Interrupts are disabled, so we can */       \
+        /* access the variable directly. */            \
+        uxCriticalNesting--;                           \
+        if( uxCriticalNesting == 0 )                   \
+        {                                              \
+            /* The nesting has unwound and we \
+             * can enable interrupts again. */ \
+            portENABLE_INTERRUPTS();           \
+        }                                      \
+    }
 
 /*-----------------------------------------------------------*/
 
 /* The yield macro maps directly to the vPortYield() function. */
 void vPortYield( void );
-#define portYIELD() vPortYield()
+#define portYIELD()    vPortYield()
 
 /* portYIELD_FROM_ISR() does not directly call vTaskSwitchContext(), but instead
-sets a flag to say that a yield has been requested.  The interrupt exit code
-then checks this flag, and calls vTaskSwitchContext() before restoring a task
-context, if the flag is not false.  This is done to prevent multiple calls to
-vTaskSwitchContext() being made from a single interrupt, as a single interrupt
-can result in multiple peripherals being serviced. */
+ * sets a flag to say that a yield has been requested.  The interrupt exit code
+ * then checks this flag, and calls vTaskSwitchContext() before restoring a task
+ * context, if the flag is not false.  This is done to prevent multiple calls to
+ * vTaskSwitchContext() being made from a single interrupt, as a single interrupt
+ * can result in multiple peripherals being serviced. */
 extern volatile uint32_t ulTaskSwitchRequested;
-#define portYIELD_FROM_ISR( x ) do { if( ( x ) != pdFALSE ) ulTaskSwitchRequested = 1; } while( 0 )
+#define portYIELD_FROM_ISR( x )                              \
+    do { if( ( x ) != pdFALSE ) ulTaskSwitchRequested = 1; } \
+    while( 0 )
 
-#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
 
-    /* Generic helper function. */
+/* Generic helper function. */
     __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
     {
-    uint8_t ucReturn;
+        uint8_t ucReturn;
 
         __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) );
+
         return ucReturn;
     }
 
-    /* Check the configuration. */
-    #if( configMAX_PRIORITIES > 32 )
+/* Check the configuration. */
+    #if ( configMAX_PRIORITIES > 32 )
         #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
     #endif
 
-    /* Store/clear the ready priorities in a bit map. */
-    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+/* Store/clear the ready priorities in a bit map. */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 
-    /*-----------------------------------------------------------*/
+/*-----------------------------------------------------------*/
 
-    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
 
 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portBYTE_ALIGNMENT          4
-#define portSTACK_GROWTH            ( -1 )
-#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portNOP()                   asm volatile ( "NOP" )
-#define portMEMORY_BARRIER()        asm volatile ( "" ::: "memory" )
+#define portBYTE_ALIGNMENT    4
+#define portSTACK_GROWTH      ( -1 )
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()               asm volatile ( "NOP" )
+#define portMEMORY_BARRIER()    asm volatile ( "" ::: "memory" )
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 /*-----------------------------------------------------------*/
 
 /* The following structure is used by the FreeRTOS exception handler.  It is
-filled with the MicroBlaze context as it was at the time the exception occurred.
-This is done as an aid to debugging exception occurrences. */
+ * filled with the MicroBlaze context as it was at the time the exception occurred.
+ * This is done as an aid to debugging exception occurrences. */
 typedef struct PORT_REGISTER_DUMP
 {
     /* The following structure members hold the values of the MicroBlaze
-    registers at the time the exception was raised. */
+     * registers at the time the exception was raised. */
     uint32_t ulR1_SP;
     uint32_t ulR2_small_data_area;
     uint32_t ulR3;
@@ -208,19 +213,18 @@ typedef struct PORT_REGISTER_DUMP
     uint32_t ulEDR;
 
     /* A human readable description of the exception cause.  The strings used
-    are the same as the #define constant names found in the
-    microblaze_exceptions_i.h header file */
-    int8_t *pcExceptionCause;
+     * are the same as the #define constant names found in the
+     * microblaze_exceptions_i.h header file */
+    int8_t * pcExceptionCause;
 
     /* The human readable name of the task that was running at the time the
-    exception occurred.  This is the name that was given to the task when the
-    task was created using the FreeRTOS xTaskCreate() API function. */
-    char *pcCurrentTaskName;
+     * exception occurred.  This is the name that was given to the task when the
+     * task was created using the FreeRTOS xTaskCreate() API function. */
+    char * pcCurrentTaskName;
 
     /* The handle of the task that was running a the time the exception
-    occurred. */
+     * occurred. */
     void * xCurrentTaskHandle;
-
 } xPortRegisterDump;
 
 
@@ -259,7 +263,9 @@ typedef struct PORT_REGISTER_DUMP
  * pdPASS is returned if the function executes successfully.  Any other value
  * being returned indicates that the function did not execute correctly.
  */
-BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef );
+BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID,
+                                         XInterruptHandler pxHandler,
+                                         void * pvCallBackRef );
 
 
 /*
@@ -364,7 +370,7 @@ void vPortExceptionsInstallHandlers( void );
  * register dump information.  For example, an implementation could be provided
  * that wrote the register dump data to a display, or a UART port.
  */
-void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump );
+void vApplicationExceptionRegisterDump( xPortRegisterDump * xRegisterDump );
 
 
 /* *INDENT-OFF* */
diff --git a/portable/GCC/MicroBlazeV9/port.c b/portable/GCC/MicroBlazeV9/port.c
index 8018da4d6..fd5de1527 100644
--- a/portable/GCC/MicroBlazeV9/port.c
+++ b/portable/GCC/MicroBlazeV9/port.c
@@ -27,8 +27,8 @@
  */
 
 /*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the MicroBlaze port.
- *----------------------------------------------------------*/
+* Implementation of functions defined in portable.h for the MicroBlaze port.
+*----------------------------------------------------------*/
 
 
 /* Scheduler includes. */
@@ -44,20 +44,20 @@
 #include <microblaze_exceptions_g.h>
 
 /* Tasks are started with a critical section nesting of 0 - however, prior to
-the scheduler being commenced interrupts should not be enabled, so the critical
-nesting variable is initialised to a non-zero value. */
-#define portINITIAL_NESTING_VALUE   ( 0xff )
+ * the scheduler being commenced interrupts should not be enabled, so the critical
+ * nesting variable is initialised to a non-zero value. */
+#define portINITIAL_NESTING_VALUE    ( 0xff )
 
 /* The bit within the MSR register that enabled/disables interrupts and
-exceptions respectively. */
-#define portMSR_IE                  ( 0x02U )
-#define portMSR_EE                  ( 0x100U )
+ * exceptions respectively. */
+#define portMSR_IE                   ( 0x02U )
+#define portMSR_EE                   ( 0x100U )
 
 /* If the floating point unit is included in the MicroBlaze build, then the
-FSR register is saved as part of the task context.  portINITIAL_FSR is the value
-given to the FSR register when the initial context is set up for a task being
-created. */
-#define portINITIAL_FSR             ( 0U )
+ * FSR register is saved as part of the task context.  portINITIAL_FSR is the value
+ * given to the FSR register when the initial context is set up for a task being
+ * created. */
+#define portINITIAL_FSR              ( 0U )
 
 /*-----------------------------------------------------------*/
 
@@ -74,27 +74,27 @@ static int32_t prvEnsureInterruptControllerIsInitialised( void );
 /*-----------------------------------------------------------*/
 
 /* Counts the nesting depth of calls to portENTER_CRITICAL().  Each task
-maintains its own count, so this variable is saved as part of the task
-context. */
+ * maintains its own count, so this variable is saved as part of the task
+ * context. */
 volatile UBaseType_t uxCriticalNesting = portINITIAL_NESTING_VALUE;
 
 /* This port uses a separate stack for interrupts.  This prevents the stack of
-every task needing to be large enough to hold an entire interrupt stack on top
-of the task stack. */
-uint32_t *pulISRStack;
+ * every task needing to be large enough to hold an entire interrupt stack on top
+ * of the task stack. */
+uint32_t * pulISRStack;
 
 /* If an interrupt requests a context switch, then ulTaskSwitchRequested will
-get set to 1.  ulTaskSwitchRequested is inspected just before the main interrupt
-handler exits.  If, at that time, ulTaskSwitchRequested is set to 1, the kernel
-will call vTaskSwitchContext() to ensure the task that runs immediately after
-the interrupt exists is the highest priority task that is able to run.  This is
-an unusual mechanism, but is used for this port because a single interrupt can
-cause the servicing of multiple peripherals - and it is inefficient to call
-vTaskSwitchContext() multiple times as each peripheral is serviced. */
+ * get set to 1.  ulTaskSwitchRequested is inspected just before the main interrupt
+ * handler exits.  If, at that time, ulTaskSwitchRequested is set to 1, the kernel
+ * will call vTaskSwitchContext() to ensure the task that runs immediately after
+ * the interrupt exists is the highest priority task that is able to run.  This is
+ * an unusual mechanism, but is used for this port because a single interrupt can
+ * cause the servicing of multiple peripherals - and it is inefficient to call
+ * vTaskSwitchContext() multiple times as each peripheral is serviced. */
 volatile uint32_t ulTaskSwitchRequested = 0UL;
 
 /* The instance of the interrupt controller used by this port.  This is required
-by the Xilinx library API functions. */
+ * by the Xilinx library API functions. */
 static XIntc xInterruptControllerInstance;
 
 /*-----------------------------------------------------------*/
@@ -106,20 +106,25 @@ static XIntc xInterruptControllerInstance;
  * See the portable.h header file.
  */
 #if ( portHAS_STACK_OVERFLOW_CHECKING == 1 )
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters )
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters )
 #else
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters )
 #endif
 {
-extern void * _SDA2_BASE_;
-extern void * _SDA_BASE_;
-const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_;
-const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_;
-extern void _start1( void );
+    extern void * _SDA2_BASE_;
+    extern void * _SDA_BASE_;
+    const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_;
+    const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_;
+    extern void _start1( void );
 
     /* Place a few bytes of known values on the bottom of the stack.
-    This is essential for the Microblaze port and these lines must
-    not be omitted. */
+     * This is essential for the Microblaze port and these lines must
+     * not be omitted. */
     *pxTopOfStack = ( StackType_t ) 0x00000000;
     pxTopOfStack--;
     *pxTopOfStack = ( StackType_t ) 0x00000000;
@@ -129,24 +134,24 @@ extern void _start1( void );
 
     #if ( portHAS_STACK_OVERFLOW_CHECKING == 1 )
         /* Store the stack limits. */
-        *pxTopOfStack = (StackType_t) (pxTopOfStack + 3);
+        *pxTopOfStack = ( StackType_t ) ( pxTopOfStack + 3 );
         pxTopOfStack--;
-        *pxTopOfStack = (StackType_t) pxEndOfStack;
+        *pxTopOfStack = ( StackType_t ) pxEndOfStack;
         pxTopOfStack--;
     #endif
 
-    #if( XPAR_MICROBLAZE_USE_FPU != 0 )
+    #if ( XPAR_MICROBLAZE_USE_FPU != 0 )
         /* The FSR value placed in the initial task context is just 0. */
         *pxTopOfStack = portINITIAL_FSR;
         pxTopOfStack--;
     #endif
 
     /* The MSR value placed in the initial task context should have interrupts
-    disabled.  Each task will enable interrupts automatically when it enters
-    the running state for the first time. */
+     * disabled.  Each task will enable interrupts automatically when it enters
+     * the running state for the first time. */
     *pxTopOfStack = mfmsr() & ~portMSR_IE;
 
-    #if( MICROBLAZE_EXCEPTIONS_ENABLED == 1 )
+    #if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 )
     {
         /* Ensure exceptions are enabled for the task. */
         *pxTopOfStack |= portMSR_EE;
@@ -156,7 +161,7 @@ extern void _start1( void );
     pxTopOfStack--;
 
     /* First stack an initial value for the critical section nesting.  This
-    is initialised to zero. */
+     * is initialised to zero. */
     *pxTopOfStack = ( StackType_t ) 0x00;
 
     /* R0 is always zero. */
@@ -164,13 +169,13 @@ extern void _start1( void );
 
     /* Place an initial value for all the general purpose registers. */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) ulR2;   /* R2 - read only small data area. */
+    *pxTopOfStack = ( StackType_t ) ulR2;         /* R2 - read only small data area. */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x03;   /* R3 - return values and temporaries. */
+    *pxTopOfStack = ( StackType_t ) 0x03;         /* R3 - return values and temporaries. */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x04;   /* R4 - return values and temporaries. */
+    *pxTopOfStack = ( StackType_t ) 0x04;         /* R4 - return values and temporaries. */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) pvParameters;/* R5 contains the function call parameters. */
+    *pxTopOfStack = ( StackType_t ) pvParameters; /* R5 contains the function call parameters. */
 
     #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
         pxTopOfStack--;
@@ -188,15 +193,15 @@ extern void _start1( void );
         pxTopOfStack--;
         *pxTopOfStack = ( StackType_t ) 0x0c;   /* R12 - temporaries. */
         pxTopOfStack--;
-    #else
-        pxTopOfStack-= 8;
-    #endif
+    #else /* ifdef portPRE_LOAD_STACK_FOR_DEBUGGING */
+        pxTopOfStack -= 8;
+    #endif /* ifdef portPRE_LOAD_STACK_FOR_DEBUGGING */
 
-    *pxTopOfStack = ( StackType_t ) ulR13;  /* R13 - read/write small data area. */
+    *pxTopOfStack = ( StackType_t ) ulR13;   /* R13 - read/write small data area. */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) pxCode; /* R14 - return address for interrupt. */
+    *pxTopOfStack = ( StackType_t ) pxCode;  /* R14 - return address for interrupt. */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) _start1;    /* R15 - return address for subroutine. */
+    *pxTopOfStack = ( StackType_t ) _start1; /* R15 - return address for subroutine. */
 
     #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
         pxTopOfStack--;
@@ -238,41 +243,41 @@ extern void _start1( void );
         pxTopOfStack--;
         *pxTopOfStack = ( StackType_t ) 0x1f;   /* R31 - must be saved across function calls. Callee-save. */
         pxTopOfStack--;
-    #else
+    #else /* ifdef portPRE_LOAD_STACK_FOR_DEBUGGING */
         pxTopOfStack -= 13;
-    #endif
+    #endif /* ifdef portPRE_LOAD_STACK_FOR_DEBUGGING */
 
     /* Return a pointer to the top of the stack that has been generated so this
-    can be stored in the task control block for the task. */
+     * can be stored in the task control block for the task. */
     return pxTopOfStack;
 }
 /*-----------------------------------------------------------*/
 
 BaseType_t xPortStartScheduler( void )
 {
-extern void ( vPortStartFirstTask )( void );
-extern uint32_t _stack[];
+    extern void( vPortStartFirstTask )( void );
+    extern uint32_t _stack[];
 
     /* Setup the hardware to generate the tick.  Interrupts are disabled when
-    this function is called.
-
-    This port uses an application defined callback function to install the tick
-    interrupt handler because the kernel will run on lots of different
-    MicroBlaze and FPGA configurations - not all of which will have the same
-    timer peripherals defined or available.  An example definition of
-    vApplicationSetupTimerInterrupt() is provided in the official demo
-    application that accompanies this port. */
+     * this function is called.
+     *
+     * This port uses an application defined callback function to install the tick
+     * interrupt handler because the kernel will run on lots of different
+     * MicroBlaze and FPGA configurations - not all of which will have the same
+     * timer peripherals defined or available.  An example definition of
+     * vApplicationSetupTimerInterrupt() is provided in the official demo
+     * application that accompanies this port. */
     vApplicationSetupTimerInterrupt();
 
     /* Reuse the stack from main() as the stack for the interrupts/exceptions. */
     pulISRStack = ( uint32_t * ) _stack;
 
     /* Ensure there is enough space for the functions called from the interrupt
-    service routines to write back into the stack frame of the caller. */
+     * service routines to write back into the stack frame of the caller. */
     pulISRStack -= 2;
 
     /* Restore the context of the first task that is going to run.  From here
-    on, the created tasks will be executing. */
+     * on, the created tasks will be executing. */
     vPortStartFirstTask();
 
     /* Should not get here as the tasks are now running! */
@@ -283,7 +288,7 @@ extern uint32_t _stack[];
 void vPortEndScheduler( void )
 {
     /* Not implemented in ports where there is nothing to return to.
-    Artificially force an assert. */
+     * Artificially force an assert. */
     configASSERT( uxCriticalNesting == 1000UL );
 }
 /*-----------------------------------------------------------*/
@@ -293,17 +298,17 @@ void vPortEndScheduler( void )
  */
 void vPortYield( void )
 {
-extern void VPortYieldASM( void );
+    extern void VPortYieldASM( void );
 
     /* Perform the context switch in a critical section to assure it is
-    not interrupted by the tick ISR.  It is not a problem to do this as
-    each task maintains its own interrupt status. */
+     * not interrupted by the tick ISR.  It is not a problem to do this as
+     * each task maintains its own interrupt status. */
     portENTER_CRITICAL();
     {
         /* Jump directly to the yield function to ensure there is no
-        compiler generated prologue code. */
-        asm volatile (  "bralid r14, VPortYieldASM      \n\t" \
-                        "or r0, r0, r0                  \n\t" );
+         * compiler generated prologue code. */
+        asm volatile ( "bralid r14, VPortYieldASM      \n\t" \
+                       "or r0, r0, r0                  \n\t" );
     }
     portEXIT_CRITICAL();
 }
@@ -311,16 +316,17 @@ extern void VPortYieldASM( void );
 
 void vPortEnableInterrupt( uint8_t ucInterruptID )
 {
-int32_t lReturn;
+    int32_t lReturn;
 
     /* An API function is provided to enable an interrupt in the interrupt
-    controller because the interrupt controller instance variable is private
-    to this file. */
+     * controller because the interrupt controller instance variable is private
+     * to this file. */
     lReturn = prvEnsureInterruptControllerIsInitialised();
+
     if( lReturn == pdPASS )
     {
         /* Critical section protects read/modify/writer operation inside
-        XIntc_Enable(). */
+         * XIntc_Enable(). */
         portENTER_CRITICAL();
         {
             XIntc_Enable( &xInterruptControllerInstance, ucInterruptID );
@@ -334,11 +340,11 @@ int32_t lReturn;
 
 void vPortDisableInterrupt( uint8_t ucInterruptID )
 {
-int32_t lReturn;
+    int32_t lReturn;
 
     /* An API function is provided to disable an interrupt in the interrupt
-    controller because the interrupt controller instance variable is private
-    to this file. */
+     * controller because the interrupt controller instance variable is private
+     * to this file. */
     lReturn = prvEnsureInterruptControllerIsInitialised();
 
     if( lReturn == pdPASS )
@@ -350,12 +356,14 @@ int32_t lReturn;
 }
 /*-----------------------------------------------------------*/
 
-BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef )
+BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID,
+                                         XInterruptHandler pxHandler,
+                                         void * pvCallBackRef )
 {
-int32_t lReturn;
+    int32_t lReturn;
 
     /* An API function is provided to install an interrupt handler because the
-    interrupt controller instance variable is private to this file. */
+     * interrupt controller instance variable is private to this file. */
 
     lReturn = prvEnsureInterruptControllerIsInitialised();
 
@@ -377,10 +385,10 @@ int32_t lReturn;
 
 void vPortRemoveInterruptHandler( uint8_t ucInterruptID )
 {
-int32_t lReturn;
+    int32_t lReturn;
 
     /* An API function is provided to remove an interrupt handler because the
-    interrupt controller instance variable is private to this file. */
+     * interrupt controller instance variable is private to this file. */
 
     lReturn = prvEnsureInterruptControllerIsInitialised();
 
@@ -395,11 +403,11 @@ int32_t lReturn;
 
 static int32_t prvEnsureInterruptControllerIsInitialised( void )
 {
-static int32_t lInterruptControllerInitialised = pdFALSE;
-int32_t lReturn;
+    static int32_t lInterruptControllerInitialised = pdFALSE;
+    int32_t lReturn;
 
     /* Ensure the interrupt controller instance variable is initialised before
-    it is used, and that the initialisation only happens once. */
+     * it is used, and that the initialisation only happens once. */
     if( lInterruptControllerInitialised != pdTRUE )
     {
         lReturn = prvInitialiseInterruptController();
@@ -422,19 +430,19 @@ int32_t lReturn;
  * Handler for the timer interrupt.  This is the handler that the application
  * defined callback function vApplicationSetupTimerInterrupt() should install.
  */
-void vPortTickISR( void *pvUnused )
+void vPortTickISR( void * pvUnused )
 {
-extern void vApplicationClearTimerInterrupt( void );
+    extern void vApplicationClearTimerInterrupt( void );
 
     /* Ensure the unused parameter does not generate a compiler warning. */
     ( void ) pvUnused;
 
     /* This port uses an application defined callback function to clear the tick
-    interrupt because the kernel will run on lots of different MicroBlaze and
-    FPGA configurations - not all of which will have the same timer peripherals
-    defined or available.  An example definition of
-    vApplicationClearTimerInterrupt() is provided in the official demo
-    application that accompanies this port. */
+     * interrupt because the kernel will run on lots of different MicroBlaze and
+     * FPGA configurations - not all of which will have the same timer peripherals
+     * defined or available.  An example definition of
+     * vApplicationClearTimerInterrupt() is provided in the official demo
+     * application that accompanies this port. */
     vApplicationClearTimerInterrupt();
 
     /* Increment the RTOS tick - this might cause a task to unblock. */
@@ -448,7 +456,7 @@ extern void vApplicationClearTimerInterrupt( void );
 
 static int32_t prvInitialiseInterruptController( void )
 {
-int32_t lStatus;
+    int32_t lStatus;
 
     lStatus = XIntc_Initialize( &xInterruptControllerInstance, configINTERRUPT_CONTROLLER_TO_USE );
 
@@ -461,8 +469,8 @@ int32_t lStatus;
         XIntc_SetIntrSvcOption( xInterruptControllerInstance.BaseAddress, XIN_SVC_ALL_ISRS_OPTION );
 
         /* Install exception handlers if the MicroBlaze is configured to handle
-        exceptions, and the application defined constant
-        configINSTALL_EXCEPTION_HANDLERS is set to 1. */
+         * exceptions, and the application defined constant
+         * configINSTALL_EXCEPTION_HANDLERS is set to 1. */
         #if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )
         {
             vPortExceptionsInstallHandlers();
@@ -470,7 +478,7 @@ int32_t lStatus;
         #endif /* MICROBLAZE_EXCEPTIONS_ENABLED */
 
         /* Start the interrupt controller.  Interrupts are enabled when the
-        scheduler starts. */
+         * scheduler starts. */
         lStatus = XIntc_Start( &xInterruptControllerInstance, XIN_REAL_MODE );
 
         if( lStatus == XST_SUCCESS )
diff --git a/portable/GCC/MicroBlazeV9/port_exceptions.c b/portable/GCC/MicroBlazeV9/port_exceptions.c
index 52055fc3c..e2347732d 100644
--- a/portable/GCC/MicroBlazeV9/port_exceptions.c
+++ b/portable/GCC/MicroBlazeV9/port_exceptions.c
@@ -35,246 +35,244 @@
 #include <microblaze_exceptions_g.h>
 
 /* The Xilinx library defined exception entry point stacks a number of
-registers.  These definitions are offsets from the stack pointer to the various
-stacked register values. */
-#define portexR3_STACK_OFFSET   4
-#define portexR4_STACK_OFFSET   5
-#define portexR5_STACK_OFFSET   6
-#define portexR6_STACK_OFFSET   7
-#define portexR7_STACK_OFFSET   8
-#define portexR8_STACK_OFFSET   9
-#define portexR9_STACK_OFFSET   10
-#define portexR10_STACK_OFFSET  11
-#define portexR11_STACK_OFFSET  12
-#define portexR12_STACK_OFFSET  13
-#define portexR15_STACK_OFFSET  16
-#define portexR18_STACK_OFFSET  19
-#define portexMSR_STACK_OFFSET  20
-#define portexR19_STACK_OFFSET  -1
+ * registers.  These definitions are offsets from the stack pointer to the various
+ * stacked register values. */
+#define portexR3_STACK_OFFSET                 4
+#define portexR4_STACK_OFFSET                 5
+#define portexR5_STACK_OFFSET                 6
+#define portexR6_STACK_OFFSET                 7
+#define portexR7_STACK_OFFSET                 8
+#define portexR8_STACK_OFFSET                 9
+#define portexR9_STACK_OFFSET                 10
+#define portexR10_STACK_OFFSET                11
+#define portexR11_STACK_OFFSET                12
+#define portexR12_STACK_OFFSET                13
+#define portexR15_STACK_OFFSET                16
+#define portexR18_STACK_OFFSET                19
+#define portexMSR_STACK_OFFSET                20
+#define portexR19_STACK_OFFSET                -1
 
 /* This is defined to equal the size, in bytes, of the stack frame generated by
-the Xilinx standard library exception entry point.  It is required to determine
-the stack pointer value prior to the exception being entered. */
-#define portexASM_HANDLER_STACK_FRAME_SIZE 84UL
+ * the Xilinx standard library exception entry point.  It is required to determine
+ * the stack pointer value prior to the exception being entered. */
+#define portexASM_HANDLER_STACK_FRAME_SIZE    84UL
 
 /* The number of bytes a MicroBlaze instruction consumes. */
-#define portexINSTRUCTION_SIZE  4
+#define portexINSTRUCTION_SIZE                4
 
 /* Exclude this entire file if the MicroBlaze is not configured to handle
-exceptions, or the application defined configuration constant
-configINSTALL_EXCEPTION_HANDLERS is not set to 1. */
+ * exceptions, or the application defined configuration constant
+ * configINSTALL_EXCEPTION_HANDLERS is not set to 1. */
 #if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )
 
 /* This variable is set in the exception entry code, before
-vPortExceptionHandler is called. */
-uint32_t *pulStackPointerOnFunctionEntry = NULL;
+ * vPortExceptionHandler is called. */
+    uint32_t * pulStackPointerOnFunctionEntry = NULL;
 
 /* This is the structure that is filled with the MicroBlaze context as it
-existed immediately prior to the exception occurrence.  A pointer to this
-structure is passed into the vApplicationExceptionRegisterDump() callback
-function, if one is defined. */
-static xPortRegisterDump xRegisterDump;
+ * existed immediately prior to the exception occurrence.  A pointer to this
+ * structure is passed into the vApplicationExceptionRegisterDump() callback
+ * function, if one is defined. */
+    static xPortRegisterDump xRegisterDump;
 
 /* This is the FreeRTOS exception handler that is installed for all exception
-types.  It is called from vPortExceptionHanlderEntry() - which is itself defined
-in portasm.S. */
-void vPortExceptionHandler( void *pvExceptionID );
-extern void vPortExceptionHandlerEntry( void *pvExceptionID );
+ * types.  It is called from vPortExceptionHandlerEntry() - which is itself defined
+ * in portasm.S. */
+    void vPortExceptionHandler( void * pvExceptionID );
+    extern void vPortExceptionHandlerEntry( void * pvExceptionID );
 
 /*-----------------------------------------------------------*/
 
 /* vApplicationExceptionRegisterDump() is a callback function that the
-application can optionally define to receive a populated xPortRegisterDump
-structure.  If the application chooses not to define a version of
-vApplicationExceptionRegisterDump() then this weekly defined default
-implementation will be called instead. */
-extern void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump ) __attribute__((weak));
-void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump )
-{
-    ( void ) xRegisterDump;
-
-    for( ;; )
+ * application can optionally define to receive a populated xPortRegisterDump
+ * structure.  If the application chooses not to define a version of
+ * vApplicationExceptionRegisterDump() then this weekly defined default
+ * implementation will be called instead. */
+    extern void vApplicationExceptionRegisterDump( xPortRegisterDump * xRegisterDump ) __attribute__( ( weak ) );
+    void vApplicationExceptionRegisterDump( xPortRegisterDump * xRegisterDump )
     {
-        portNOP();
+        ( void ) xRegisterDump;
+
+        for( ; ; )
+        {
+            portNOP();
+        }
     }
-}
 /*-----------------------------------------------------------*/
 
-void vPortExceptionHandler( void *pvExceptionID )
-{
-extern void *pxCurrentTCB;
-
-    /* Fill an xPortRegisterDump structure with the MicroBlaze context as it
-    was immediately before the exception occurrence. */
-
-    /* First fill in the name and handle of the task that was in the Running
-    state when the exception occurred. */
-    xRegisterDump.xCurrentTaskHandle = pxCurrentTCB;
-    xRegisterDump.pcCurrentTaskName = pcTaskGetName( NULL );
-
-    configASSERT( pulStackPointerOnFunctionEntry );
-
-    /* Obtain the values of registers that were stacked prior to this function
-    being called, and may have changed since they were stacked. */
-    xRegisterDump.ulR3 = pulStackPointerOnFunctionEntry[ portexR3_STACK_OFFSET ];
-    xRegisterDump.ulR4 = pulStackPointerOnFunctionEntry[ portexR4_STACK_OFFSET ];
-    xRegisterDump.ulR5 = pulStackPointerOnFunctionEntry[ portexR5_STACK_OFFSET ];
-    xRegisterDump.ulR6 = pulStackPointerOnFunctionEntry[ portexR6_STACK_OFFSET ];
-    xRegisterDump.ulR7 = pulStackPointerOnFunctionEntry[ portexR7_STACK_OFFSET ];
-    xRegisterDump.ulR8 = pulStackPointerOnFunctionEntry[ portexR8_STACK_OFFSET ];
-    xRegisterDump.ulR9 = pulStackPointerOnFunctionEntry[ portexR9_STACK_OFFSET ];
-    xRegisterDump.ulR10 = pulStackPointerOnFunctionEntry[ portexR10_STACK_OFFSET ];
-    xRegisterDump.ulR11 = pulStackPointerOnFunctionEntry[ portexR11_STACK_OFFSET ];
-    xRegisterDump.ulR12 = pulStackPointerOnFunctionEntry[ portexR12_STACK_OFFSET ];
-    xRegisterDump.ulR15_return_address_from_subroutine = pulStackPointerOnFunctionEntry[ portexR15_STACK_OFFSET ];
-    xRegisterDump.ulR18 = pulStackPointerOnFunctionEntry[ portexR18_STACK_OFFSET ];
-    xRegisterDump.ulR19 = pulStackPointerOnFunctionEntry[ portexR19_STACK_OFFSET ];
-    xRegisterDump.ulMSR = pulStackPointerOnFunctionEntry[ portexMSR_STACK_OFFSET ];
-
-    /* Obtain the value of all other registers. */
-    xRegisterDump.ulR2_small_data_area = mfgpr( R2 );
-    xRegisterDump.ulR13_read_write_small_data_area = mfgpr( R13 );
-    xRegisterDump.ulR14_return_address_from_interrupt = mfgpr( R14 );
-    xRegisterDump.ulR16_return_address_from_trap = mfgpr( R16 );
-    xRegisterDump.ulR17_return_address_from_exceptions = mfgpr( R17 );
-    xRegisterDump.ulR20 = mfgpr( R20 );
-    xRegisterDump.ulR21 = mfgpr( R21 );
-    xRegisterDump.ulR22 = mfgpr( R22 );
-    xRegisterDump.ulR23 = mfgpr( R23 );
-    xRegisterDump.ulR24 = mfgpr( R24 );
-    xRegisterDump.ulR25 = mfgpr( R25 );
-    xRegisterDump.ulR26 = mfgpr( R26 );
-    xRegisterDump.ulR27 = mfgpr( R27 );
-    xRegisterDump.ulR28 = mfgpr( R28 );
-    xRegisterDump.ulR29 = mfgpr( R29 );
-    xRegisterDump.ulR30 = mfgpr( R30 );
-    xRegisterDump.ulR31 = mfgpr( R31 );
-    xRegisterDump.ulR1_SP = ( ( uint32_t ) pulStackPointerOnFunctionEntry ) + portexASM_HANDLER_STACK_FRAME_SIZE;
-    xRegisterDump.ulEAR = mfear();
-    xRegisterDump.ulESR = mfesr();
-    xRegisterDump.ulEDR = mfedr();
-
-    /* Move the saved program counter back to the instruction that was executed
-    when the exception occurred.  This is only valid for certain types of
-    exception. */
-    xRegisterDump.ulPC = xRegisterDump.ulR17_return_address_from_exceptions - portexINSTRUCTION_SIZE;
-
-    #if( XPAR_MICROBLAZE_USE_FPU != 0 )
+    void vPortExceptionHandler( void * pvExceptionID )
     {
-        xRegisterDump.ulFSR = mffsr();
-    }
-    #else
-    {
-        xRegisterDump.ulFSR = 0UL;
-    }
-    #endif
+        extern void * pxCurrentTCB;
 
-    /* Also fill in a string that describes what type of exception this is.
-    The string uses the same ID names as defined in the MicroBlaze standard
-    library exception header files. */
-    switch( ( uint32_t ) pvExceptionID )
-    {
-        case XEXC_ID_FSL :
+        /* Fill an xPortRegisterDump structure with the MicroBlaze context as it
+         * was immediately before the exception occurrence. */
+
+        /* First fill in the name and handle of the task that was in the Running
+         * state when the exception occurred. */
+        xRegisterDump.xCurrentTaskHandle = pxCurrentTCB;
+        xRegisterDump.pcCurrentTaskName = pcTaskGetName( NULL );
+
+        configASSERT( pulStackPointerOnFunctionEntry );
+
+        /* Obtain the values of registers that were stacked prior to this function
+         * being called, and may have changed since they were stacked. */
+        xRegisterDump.ulR3 = pulStackPointerOnFunctionEntry[ portexR3_STACK_OFFSET ];
+        xRegisterDump.ulR4 = pulStackPointerOnFunctionEntry[ portexR4_STACK_OFFSET ];
+        xRegisterDump.ulR5 = pulStackPointerOnFunctionEntry[ portexR5_STACK_OFFSET ];
+        xRegisterDump.ulR6 = pulStackPointerOnFunctionEntry[ portexR6_STACK_OFFSET ];
+        xRegisterDump.ulR7 = pulStackPointerOnFunctionEntry[ portexR7_STACK_OFFSET ];
+        xRegisterDump.ulR8 = pulStackPointerOnFunctionEntry[ portexR8_STACK_OFFSET ];
+        xRegisterDump.ulR9 = pulStackPointerOnFunctionEntry[ portexR9_STACK_OFFSET ];
+        xRegisterDump.ulR10 = pulStackPointerOnFunctionEntry[ portexR10_STACK_OFFSET ];
+        xRegisterDump.ulR11 = pulStackPointerOnFunctionEntry[ portexR11_STACK_OFFSET ];
+        xRegisterDump.ulR12 = pulStackPointerOnFunctionEntry[ portexR12_STACK_OFFSET ];
+        xRegisterDump.ulR15_return_address_from_subroutine = pulStackPointerOnFunctionEntry[ portexR15_STACK_OFFSET ];
+        xRegisterDump.ulR18 = pulStackPointerOnFunctionEntry[ portexR18_STACK_OFFSET ];
+        xRegisterDump.ulR19 = pulStackPointerOnFunctionEntry[ portexR19_STACK_OFFSET ];
+        xRegisterDump.ulMSR = pulStackPointerOnFunctionEntry[ portexMSR_STACK_OFFSET ];
+
+        /* Obtain the value of all other registers. */
+        xRegisterDump.ulR2_small_data_area = mfgpr( R2 );
+        xRegisterDump.ulR13_read_write_small_data_area = mfgpr( R13 );
+        xRegisterDump.ulR14_return_address_from_interrupt = mfgpr( R14 );
+        xRegisterDump.ulR16_return_address_from_trap = mfgpr( R16 );
+        xRegisterDump.ulR17_return_address_from_exceptions = mfgpr( R17 );
+        xRegisterDump.ulR20 = mfgpr( R20 );
+        xRegisterDump.ulR21 = mfgpr( R21 );
+        xRegisterDump.ulR22 = mfgpr( R22 );
+        xRegisterDump.ulR23 = mfgpr( R23 );
+        xRegisterDump.ulR24 = mfgpr( R24 );
+        xRegisterDump.ulR25 = mfgpr( R25 );
+        xRegisterDump.ulR26 = mfgpr( R26 );
+        xRegisterDump.ulR27 = mfgpr( R27 );
+        xRegisterDump.ulR28 = mfgpr( R28 );
+        xRegisterDump.ulR29 = mfgpr( R29 );
+        xRegisterDump.ulR30 = mfgpr( R30 );
+        xRegisterDump.ulR31 = mfgpr( R31 );
+        xRegisterDump.ulR1_SP = ( ( uint32_t ) pulStackPointerOnFunctionEntry ) + portexASM_HANDLER_STACK_FRAME_SIZE;
+        xRegisterDump.ulEAR = mfear();
+        xRegisterDump.ulESR = mfesr();
+        xRegisterDump.ulEDR = mfedr();
+
+        /* Move the saved program counter back to the instruction that was executed
+         * when the exception occurred.  This is only valid for certain types of
+         * exception. */
+        xRegisterDump.ulPC = xRegisterDump.ulR17_return_address_from_exceptions - portexINSTRUCTION_SIZE;
+
+        #if ( XPAR_MICROBLAZE_USE_FPU != 0 )
+        {
+            xRegisterDump.ulFSR = mffsr();
+        }
+        #else
+        {
+            xRegisterDump.ulFSR = 0UL;
+        }
+        #endif
+
+        /* Also fill in a string that describes what type of exception this is.
+         * The string uses the same ID names as defined in the MicroBlaze standard
+         * library exception header files. */
+        switch( ( uint32_t ) pvExceptionID )
+        {
+            case XEXC_ID_FSL:
                 xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_FSL";
                 break;
 
-        case XEXC_ID_UNALIGNED_ACCESS :
+            case XEXC_ID_UNALIGNED_ACCESS:
                 xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_UNALIGNED_ACCESS";
                 break;
 
-        case XEXC_ID_ILLEGAL_OPCODE :
+            case XEXC_ID_ILLEGAL_OPCODE:
                 xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_ILLEGAL_OPCODE";
                 break;
 
-        case XEXC_ID_M_AXI_I_EXCEPTION :
+            case XEXC_ID_M_AXI_I_EXCEPTION:
                 xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_M_AXI_I_EXCEPTION or XEXC_ID_IPLB_EXCEPTION";
                 break;
 
-        case XEXC_ID_M_AXI_D_EXCEPTION :
+            case XEXC_ID_M_AXI_D_EXCEPTION:
                 xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_M_AXI_D_EXCEPTION or XEXC_ID_DPLB_EXCEPTION";
                 break;
 
-        case XEXC_ID_DIV_BY_ZERO :
+            case XEXC_ID_DIV_BY_ZERO:
                 xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_DIV_BY_ZERO";
                 break;
 
-        case XEXC_ID_STACK_VIOLATION :
+            case XEXC_ID_STACK_VIOLATION:
                 xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_STACK_VIOLATION or XEXC_ID_MMU";
                 break;
 
-        #if( XPAR_MICROBLAZE_USE_FPU != 0 )
-
-            case XEXC_ID_FPU :
+                #if ( XPAR_MICROBLAZE_USE_FPU != 0 )
+                    case XEXC_ID_FPU:
                         xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_FPU see ulFSR value";
                         break;
+                #endif /* XPAR_MICROBLAZE_USE_FPU */
+        }
 
-        #endif /* XPAR_MICROBLAZE_USE_FPU */
+        /* vApplicationExceptionRegisterDump() is a callback function that the
+         * application can optionally define to receive the populated xPortRegisterDump
+         * structure.  If the application chooses not to define a version of
+         * vApplicationExceptionRegisterDump() then the weekly defined default
+         * implementation within this file will be called instead. */
+        vApplicationExceptionRegisterDump( &xRegisterDump );
+
+        /* Must not attempt to leave this function! */
+        for( ; ; )
+        {
+            portNOP();
+        }
     }
-
-    /* vApplicationExceptionRegisterDump() is a callback function that the
-    application can optionally define to receive the populated xPortRegisterDump
-    structure.  If the application chooses not to define a version of
-    vApplicationExceptionRegisterDump() then the weekly defined default
-    implementation within this file will be called instead. */
-    vApplicationExceptionRegisterDump( &xRegisterDump );
-
-    /* Must not attempt to leave this function! */
-    for( ;; )
-    {
-        portNOP();
-    }
-}
 /*-----------------------------------------------------------*/
 
-void vPortExceptionsInstallHandlers( void )
-{
-static uint32_t ulHandlersAlreadyInstalled = pdFALSE;
-
-    if( ulHandlersAlreadyInstalled == pdFALSE )
+    void vPortExceptionsInstallHandlers( void )
     {
-        ulHandlersAlreadyInstalled = pdTRUE;
+        static uint32_t ulHandlersAlreadyInstalled = pdFALSE;
 
-        #if XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS == 1
-            microblaze_register_exception_handler( XEXC_ID_UNALIGNED_ACCESS, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_UNALIGNED_ACCESS );
-        #endif /* XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS*/
+        if( ulHandlersAlreadyInstalled == pdFALSE )
+        {
+            ulHandlersAlreadyInstalled = pdTRUE;
 
-        #if XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION == 1
-            microblaze_register_exception_handler( XEXC_ID_ILLEGAL_OPCODE, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_ILLEGAL_OPCODE );
-        #endif /* XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION */
+            #if XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS == 1
+                microblaze_register_exception_handler( XEXC_ID_UNALIGNED_ACCESS, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_UNALIGNED_ACCESS );
+            #endif /* XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS*/
 
-        #if XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION == 1
-            microblaze_register_exception_handler( XEXC_ID_M_AXI_I_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_I_EXCEPTION );
-        #endif /* XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION */
+            #if XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION == 1
+                microblaze_register_exception_handler( XEXC_ID_ILLEGAL_OPCODE, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_ILLEGAL_OPCODE );
+            #endif /* XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION */
 
-        #if XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION == 1
-            microblaze_register_exception_handler( XEXC_ID_M_AXI_D_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_D_EXCEPTION );
-        #endif /* XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION */
+            #if XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION == 1
+                microblaze_register_exception_handler( XEXC_ID_M_AXI_I_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_I_EXCEPTION );
+            #endif /* XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION */
 
-        #if XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION == 1
-            microblaze_register_exception_handler( XEXC_ID_IPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_IPLB_EXCEPTION );
-        #endif /* XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION */
+            #if XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION == 1
+                microblaze_register_exception_handler( XEXC_ID_M_AXI_D_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_D_EXCEPTION );
+            #endif /* XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION */
 
-        #if XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION == 1
-            microblaze_register_exception_handler( XEXC_ID_DPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DPLB_EXCEPTION );
-        #endif /* XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION */
+            #if XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION == 1
+                microblaze_register_exception_handler( XEXC_ID_IPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_IPLB_EXCEPTION );
+            #endif /* XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION */
 
-        #if XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION == 1
-            microblaze_register_exception_handler( XEXC_ID_DIV_BY_ZERO, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DIV_BY_ZERO );
-        #endif /* XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION */
+            #if XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION == 1
+                microblaze_register_exception_handler( XEXC_ID_DPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DPLB_EXCEPTION );
+            #endif /* XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION */
 
-        #if XPAR_MICROBLAZE_FPU_EXCEPTION == 1
-            microblaze_register_exception_handler( XEXC_ID_FPU, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FPU );
-        #endif /* XPAR_MICROBLAZE_FPU_EXCEPTION */
+            #if XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION == 1
+                microblaze_register_exception_handler( XEXC_ID_DIV_BY_ZERO, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DIV_BY_ZERO );
+            #endif /* XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION */
 
-        #if XPAR_MICROBLAZE_FSL_EXCEPTION == 1
-            microblaze_register_exception_handler( XEXC_ID_FSL, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FSL );
-        #endif /* XPAR_MICROBLAZE_FSL_EXCEPTION */
+            #if XPAR_MICROBLAZE_FPU_EXCEPTION == 1
+                microblaze_register_exception_handler( XEXC_ID_FPU, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FPU );
+            #endif /* XPAR_MICROBLAZE_FPU_EXCEPTION */
 
-        microblaze_enable_exceptions();
+            #if XPAR_MICROBLAZE_FSL_EXCEPTION == 1
+                microblaze_register_exception_handler( XEXC_ID_FSL, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FSL );
+            #endif /* XPAR_MICROBLAZE_FSL_EXCEPTION */
+
+            microblaze_enable_exceptions();
+        }
     }
-}
 
 /* Exclude the entire file if the MicroBlaze is not configured to handle
-exceptions, or the application defined configuration item
-configINSTALL_EXCEPTION_HANDLERS is not set to 1. */
+ * exceptions, or the application defined configuration item
+ * configINSTALL_EXCEPTION_HANDLERS is not set to 1. */
 #endif /* ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) */
diff --git a/portable/GCC/MicroBlazeV9/portmacro.h b/portable/GCC/MicroBlazeV9/portmacro.h
index 9d10b5e5b..ccf98ed4c 100644
--- a/portable/GCC/MicroBlazeV9/portmacro.h
+++ b/portable/GCC/MicroBlazeV9/portmacro.h
@@ -50,28 +50,28 @@
  */
 
 /* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint32_t
-#define portBASE_TYPE   long
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-    not need to be guarded with a critical section. */
-    #define portTICK_TYPE_IS_ATOMIC 1
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+    #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
@@ -87,93 +87,98 @@ void microblaze_enable_interrupts( void );
 /* Critical section macros. */
 void vPortEnterCritical( void );
 void vPortExitCritical( void );
-#define portENTER_CRITICAL()        {                                                               \
-                                        extern volatile UBaseType_t uxCriticalNesting;              \
-                                        microblaze_disable_interrupts();                            \
-                                        uxCriticalNesting++;                                        \
-                                    }
+#define portENTER_CRITICAL()                           \
+    {                                                  \
+        extern volatile UBaseType_t uxCriticalNesting; \
+        microblaze_disable_interrupts();               \
+        uxCriticalNesting++;                           \
+    }
 
-#define portEXIT_CRITICAL()         {                                                               \
-                                        extern volatile UBaseType_t uxCriticalNesting;              \
-                                        /* Interrupts are disabled, so we can */                    \
-                                        /* access the variable directly. */                         \
-                                        uxCriticalNesting--;                                        \
-                                        if( uxCriticalNesting == 0 )                                \
-                                        {                                                           \
-                                            /* The nesting has unwound and we                       \
-                                            can enable interrupts again. */                         \
-                                            portENABLE_INTERRUPTS();                                \
-                                        }                                                           \
-                                    }
+#define portEXIT_CRITICAL()                            \
+    {                                                  \
+        extern volatile UBaseType_t uxCriticalNesting; \
+        /* Interrupts are disabled, so we can */       \
+        /* access the variable directly. */            \
+        uxCriticalNesting--;                           \
+        if( uxCriticalNesting == 0 )                   \
+        {                                              \
+            /* The nesting has unwound and we \
+             * can enable interrupts again. */ \
+            portENABLE_INTERRUPTS();           \
+        }                                      \
+    }
 
 /*-----------------------------------------------------------*/
 
 /* The yield macro maps directly to the vPortYield() function. */
 void vPortYield( void );
-#define portYIELD() vPortYield()
+#define portYIELD()    vPortYield()
 
 /* portYIELD_FROM_ISR() does not directly call vTaskSwitchContext(), but instead
-sets a flag to say that a yield has been requested.  The interrupt exit code
-then checks this flag, and calls vTaskSwitchContext() before restoring a task
-context, if the flag is not false.  This is done to prevent multiple calls to
-vTaskSwitchContext() being made from a single interrupt, as a single interrupt
-can result in multiple peripherals being serviced. */
+ * sets a flag to say that a yield has been requested.  The interrupt exit code
+ * then checks this flag, and calls vTaskSwitchContext() before restoring a task
+ * context, if the flag is not false.  This is done to prevent multiple calls to
+ * vTaskSwitchContext() being made from a single interrupt, as a single interrupt
+ * can result in multiple peripherals being serviced. */
 extern volatile uint32_t ulTaskSwitchRequested;
-#define portYIELD_FROM_ISR( x ) do { if( ( x ) != pdFALSE ) ulTaskSwitchRequested = 1; } while( 0 )
+#define portYIELD_FROM_ISR( x )                              \
+    do { if( ( x ) != pdFALSE ) ulTaskSwitchRequested = 1; } \
+    while( 0 )
 
-#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
 
-    /* Generic helper function. */
+/* Generic helper function. */
     __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
     {
-    uint8_t ucReturn;
+        uint8_t ucReturn;
 
         __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) );
+
         return ucReturn;
     }
 
-    /* Check the configuration. */
-    #if( configMAX_PRIORITIES > 32 )
+/* Check the configuration. */
+    #if ( configMAX_PRIORITIES > 32 )
         #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
     #endif
 
-    /* Store/clear the ready priorities in a bit map. */
-    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+/* Store/clear the ready priorities in a bit map. */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 
-    /*-----------------------------------------------------------*/
+/*-----------------------------------------------------------*/
 
-    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
 
 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portBYTE_ALIGNMENT          4
-#define portSTACK_GROWTH            ( -1 )
-#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portNOP()                   asm volatile ( "NOP" )
-#define portMEMORY_BARRIER()        asm volatile ( "" ::: "memory" )
+#define portBYTE_ALIGNMENT    4
+#define portSTACK_GROWTH      ( -1 )
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()               asm volatile ( "NOP" )
+#define portMEMORY_BARRIER()    asm volatile ( "" ::: "memory" )
 /*-----------------------------------------------------------*/
 
-#if( XPAR_MICROBLAZE_USE_STACK_PROTECTION )
-#define portHAS_STACK_OVERFLOW_CHECKING 1
+#if ( XPAR_MICROBLAZE_USE_STACK_PROTECTION )
+    #define portHAS_STACK_OVERFLOW_CHECKING    1
 #endif
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 /*-----------------------------------------------------------*/
 
 /* The following structure is used by the FreeRTOS exception handler.  It is
-filled with the MicroBlaze context as it was at the time the exception occurred.
-This is done as an aid to debugging exception occurrences. */
+ * filled with the MicroBlaze context as it was at the time the exception occurred.
+ * This is done as an aid to debugging exception occurrences. */
 typedef struct PORT_REGISTER_DUMP
 {
     /* The following structure members hold the values of the MicroBlaze
-    registers at the time the exception was raised. */
+     * registers at the time the exception was raised. */
     uint32_t ulR1_SP;
     uint32_t ulR2_small_data_area;
     uint32_t ulR3;
@@ -213,19 +218,18 @@ typedef struct PORT_REGISTER_DUMP
     uint32_t ulEDR;
 
     /* A human readable description of the exception cause.  The strings used
-    are the same as the #define constant names found in the
-    microblaze_exceptions_i.h header file */
-    int8_t *pcExceptionCause;
+     * are the same as the #define constant names found in the
+     * microblaze_exceptions_i.h header file */
+    int8_t * pcExceptionCause;
 
     /* The human readable name of the task that was running at the time the
-    exception occurred.  This is the name that was given to the task when the
-    task was created using the FreeRTOS xTaskCreate() API function. */
-    char *pcCurrentTaskName;
+     * exception occurred.  This is the name that was given to the task when the
+     * task was created using the FreeRTOS xTaskCreate() API function. */
+    char * pcCurrentTaskName;
 
     /* The handle of the task that was running a the time the exception
-    occurred. */
+     * occurred. */
     void * xCurrentTaskHandle;
-
 } xPortRegisterDump;
 
 
@@ -264,7 +268,9 @@ typedef struct PORT_REGISTER_DUMP
  * pdPASS is returned if the function executes successfully.  Any other value
  * being returned indicates that the function did not execute correctly.
  */
-BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef );
+BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID,
+                                         XInterruptHandler pxHandler,
+                                         void * pvCallBackRef );
 
 
 /*
@@ -369,7 +375,7 @@ void vPortExceptionsInstallHandlers( void );
  * register dump information.  For example, an implementation could be provided
  * that wrote the register dump data to a display, or a UART port.
  */
-void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump );
+void vApplicationExceptionRegisterDump( xPortRegisterDump * xRegisterDump );
 
 
 /* *INDENT-OFF* */
diff --git a/portable/GCC/NiosII/port.c b/portable/GCC/NiosII/port.c
index f26e29550..e427b4fcc 100644
--- a/portable/GCC/NiosII/port.c
+++ b/portable/GCC/NiosII/port.c
@@ -27,8 +27,8 @@
  */
 
 /*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the NIOS2 port.
- *----------------------------------------------------------*/
+* Implementation of functions defined in portable.h for the NIOS2 port.
+*----------------------------------------------------------*/
 
 /* Standard Includes. */
 #include <string.h>
@@ -45,10 +45,13 @@
 #include "task.h"
 
 /* Interrupts are enabled. */
-#define portINITIAL_ESTATUS     ( StackType_t ) 0x01
+#define portINITIAL_ESTATUS    ( StackType_t ) 0x01
 
-int _alt_ic_isr_register(alt_u32 ic_id, alt_u32 irq, alt_isr_func isr,
-  void *isr_context, void *flags);
+int _alt_ic_isr_register( alt_u32 ic_id,
+                          alt_u32 irq,
+                          alt_isr_func isr,
+                          void * isr_context,
+                          void * flags );
 /*-----------------------------------------------------------*/
 
 /*
@@ -59,23 +62,25 @@ static void prvSetupTimerInterrupt( void );
 /*
  * Call back for the alarm function.
  */
-void vPortSysTickHandler( void * context);
+void vPortSysTickHandler( void * context );
 
 /*-----------------------------------------------------------*/
 
-static void prvReadGp( uint32_t *ulValue )
+static void prvReadGp( uint32_t * ulValue )
 {
-    asm( "stw gp, (%0)" :: "r"(ulValue) );
+    asm ( "stw gp, (%0)" ::"r" ( ulValue ) );
 }
 /*-----------------------------------------------------------*/
 
 /*
  * See header file for description.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
-StackType_t *pxFramePointer = pxTopOfStack - 1;
-StackType_t xGlobalPointer;
+    StackType_t * pxFramePointer = pxTopOfStack - 1;
+    StackType_t xGlobalPointer;
 
     prvReadGp( &xGlobalPointer );
 
@@ -114,12 +119,12 @@ StackType_t xGlobalPointer;
 BaseType_t xPortStartScheduler( void )
 {
     /* Start the timer that generates the tick ISR.  Interrupts are disabled
-    here already. */
+     * here already. */
     prvSetupTimerInterrupt();
 
     /* Start the first task. */
-    asm volatile (  " movia r2, restore_sp_from_pxCurrentTCB        \n"
-                    " jmp r2                                          " );
+    asm volatile ( " movia r2, restore_sp_from_pxCurrentTCB        \n"
+                   " jmp r2                                          " );
 
     /* Should not get here! */
     return 0;
@@ -129,7 +134,7 @@ BaseType_t xPortStartScheduler( void )
 void vPortEndScheduler( void )
 {
     /* It is unlikely that the NIOS2 port will require this function as there
-    is nothing to return to.  */
+     * is nothing to return to.  */
 }
 /*-----------------------------------------------------------*/
 
@@ -140,10 +145,10 @@ void vPortEndScheduler( void )
 void prvSetupTimerInterrupt( void )
 {
     /* Try to register the interrupt handler. */
-    if ( -EINVAL == _alt_ic_isr_register( SYS_CLK_IRQ_INTERRUPT_CONTROLLER_ID, SYS_CLK_IRQ, vPortSysTickHandler, 0x0, 0x0 ) )
+    if( -EINVAL == _alt_ic_isr_register( SYS_CLK_IRQ_INTERRUPT_CONTROLLER_ID, SYS_CLK_IRQ, vPortSysTickHandler, 0x0, 0x0 ) )
     {
         /* Failed to install the Interrupt Handler. */
-        asm( "break" );
+        asm ( "break" );
     }
     else
     {
@@ -159,7 +164,7 @@ void prvSetupTimerInterrupt( void )
 }
 /*-----------------------------------------------------------*/
 
-void vPortSysTickHandler( void * context)
+void vPortSysTickHandler( void * context )
 {
     /* Increment the kernel tick. */
     if( xTaskIncrementTick() != pdFALSE )
@@ -178,27 +183,30 @@ void vPortSysTickHandler( void * context)
  * kernel has its scheduler started so that contexts are saved and switched
  * correctly.
  */
-int _alt_ic_isr_register(alt_u32 ic_id, alt_u32 irq, alt_isr_func isr,
-  void *isr_context, void *flags)
+int _alt_ic_isr_register( alt_u32 ic_id,
+                          alt_u32 irq,
+                          alt_isr_func isr,
+                          void * isr_context,
+                          void * flags )
 {
     int rc = -EINVAL;
     alt_irq_context status;
-    int id = irq;             /* IRQ interpreted as the interrupt ID. */
+    int id = irq; /* IRQ interpreted as the interrupt ID. */
 
-    if (id < ALT_NIRQ)
+    if( id < ALT_NIRQ )
     {
         /*
          * interrupts are disabled while the handler tables are updated to ensure
-         * that an interrupt doesn't occur while the tables are in an inconsistant
+         * that an interrupt doesn't occur while the tables are in an inconsistent
          * state.
          */
 
-        status = alt_irq_disable_all ();
+        status = alt_irq_disable_all();
 
-        alt_irq[id].handler = isr;
-        alt_irq[id].context = isr_context;
+        alt_irq[ id ].handler = isr;
+        alt_irq[ id ].context = isr_context;
 
-        rc = (isr) ? alt_ic_irq_enable(ic_id, id) : alt_ic_irq_disable(ic_id, id);
+        rc = ( isr ) ? alt_ic_irq_enable( ic_id, id ) : alt_ic_irq_disable( ic_id, id );
 
         /* alt_irq_enable_all(status); This line is removed to prevent the interrupt from being immediately enabled. */
     }
diff --git a/portable/GCC/NiosII/portmacro.h b/portable/GCC/NiosII/portmacro.h
index 3ac552dd8..c6f1b32bc 100644
--- a/portable/GCC/NiosII/portmacro.h
+++ b/portable/GCC/NiosII/portmacro.h
@@ -48,48 +48,48 @@
  */
 
 /* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint32_t
-#define portBASE_TYPE   long
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-    not need to be guarded with a critical section. */
-    #define portTICK_TYPE_IS_ATOMIC 1
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+    #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
 /*-----------------------------------------------------------*/
 
 /* Architecture specifics. */
-#define portSTACK_GROWTH                ( -1 )
-#define portTICK_PERIOD_MS              ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT              4
-#define portNOP()                       asm volatile ( "NOP" )
-#define portCRITICAL_NESTING_IN_TCB     1
+#define portSTACK_GROWTH               ( -1 )
+#define portTICK_PERIOD_MS             ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT             4
+#define portNOP()    asm volatile ( "NOP" )
+#define portCRITICAL_NESTING_IN_TCB    1
 /*-----------------------------------------------------------*/
 
 extern void vTaskSwitchContext( void );
 #define portYIELD()                                 asm volatile ( "trap" );
-#define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired ) vTaskSwitchContext(); } while( 0 )
+#define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired ) vTaskSwitchContext( ); } while( 0 )
 
 
 /* Include the port_asm.S file where the Context saving/restoring is defined. */
-__asm__( "\n\t.globl    save_context" );
+__asm__ ( "\n\t.globl    save_context" );
 
 /*-----------------------------------------------------------*/
 
@@ -103,8 +103,8 @@ extern void vTaskExitCritical( void );
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/GCC/PPC405_Xilinx/FPU_Macros.h b/portable/GCC/PPC405_Xilinx/FPU_Macros.h
index 9c566588a..9d7f96ff9 100644
--- a/portable/GCC/PPC405_Xilinx/FPU_Macros.h
+++ b/portable/GCC/PPC405_Xilinx/FPU_Macros.h
@@ -27,16 +27,16 @@
  */
 
 /* When switching out a task, if the task tag contains a buffer address then
-save the flop context into the buffer. */
-#define traceTASK_SWITCHED_OUT()                                            \
-    if( pxCurrentTCB->pxTaskTag != NULL )                                   \
-    {                                                                       \
-        extern void vPortSaveFPURegisters( void * );                        \
-        vPortSaveFPURegisters( ( void * ) ( pxCurrentTCB->pxTaskTag ) );    \
+ * save the flop context into the buffer. */
+#define traceTASK_SWITCHED_OUT()                                         \
+    if( pxCurrentTCB->pxTaskTag != NULL )                                \
+    {                                                                    \
+        extern void vPortSaveFPURegisters( void * );                     \
+        vPortSaveFPURegisters( ( void * ) ( pxCurrentTCB->pxTaskTag ) ); \
     }
 
 /* When switching in a task, if the task tag contains a buffer address then
-load the flop context from the buffer. */
+ * load the flop context from the buffer. */
 #define traceTASK_SWITCHED_IN()                                             \
     if( pxCurrentTCB->pxTaskTag != NULL )                                   \
     {                                                                       \
diff --git a/portable/GCC/PPC405_Xilinx/port.c b/portable/GCC/PPC405_Xilinx/port.c
index c7ecac070..a988dfc5e 100644
--- a/portable/GCC/PPC405_Xilinx/port.c
+++ b/portable/GCC/PPC405_Xilinx/port.c
@@ -27,8 +27,8 @@
  */
 
 /*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the PPC405 port.
- *----------------------------------------------------------*/
+* Implementation of functions defined in portable.h for the PPC405 port.
+*----------------------------------------------------------*/
 
 
 /* Scheduler includes. */
@@ -43,19 +43,19 @@
 /*-----------------------------------------------------------*/
 
 /* Definitions to set the initial MSR of each task. */
-#define portCRITICAL_INTERRUPT_ENABLE   ( 1UL << 17UL )
-#define portEXTERNAL_INTERRUPT_ENABLE   ( 1UL << 15UL )
-#define portMACHINE_CHECK_ENABLE        ( 1UL << 12UL )
+#define portCRITICAL_INTERRUPT_ENABLE    ( 1UL << 17UL )
+#define portEXTERNAL_INTERRUPT_ENABLE    ( 1UL << 15UL )
+#define portMACHINE_CHECK_ENABLE         ( 1UL << 12UL )
 
 #if configUSE_FPU == 1
-    #define portAPU_PRESENT             ( 1UL << 25UL )
-    #define portFCM_FPU_PRESENT         ( 1UL << 13UL )
+    #define portAPU_PRESENT              ( 1UL << 25UL )
+    #define portFCM_FPU_PRESENT          ( 1UL << 13UL )
 #else
-    #define portAPU_PRESENT             ( 0UL )
-    #define portFCM_FPU_PRESENT         ( 0UL )
+    #define portAPU_PRESENT              ( 0UL )
+    #define portFCM_FPU_PRESENT          ( 0UL )
 #endif
 
-#define portINITIAL_MSR     ( portCRITICAL_INTERRUPT_ENABLE | portEXTERNAL_INTERRUPT_ENABLE | portMACHINE_CHECK_ENABLE | portAPU_PRESENT | portFCM_FPU_PRESENT )
+#define portINITIAL_MSR                  ( portCRITICAL_INTERRUPT_ENABLE | portEXTERNAL_INTERRUPT_ENABLE | portMACHINE_CHECK_ENABLE | portAPU_PRESENT | portFCM_FPU_PRESENT )
 
 
 extern const unsigned _SDA_BASE_;
@@ -97,7 +97,9 @@ static XIntc xInterruptController;
  *
  * See the header file portable.h.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
     /* Place a known value at the bottom of the stack for debugging. */
     *pxTopOfStack = 0xDEADBEEF;
@@ -115,30 +117,30 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
     pxTopOfStack--;
 
     /* Parameters in R2. */
-    *pxTopOfStack = ( StackType_t ) &_SDA2_BASE_;   /* address of the second small data area */
+    *pxTopOfStack = ( StackType_t ) &_SDA2_BASE_; /* address of the second small data area */
     pxTopOfStack--;
 
     /* R1 is the stack pointer so is omitted. */
 
-    *pxTopOfStack = 0x10000001UL;;  /* R0. */
+    *pxTopOfStack = 0x10000001UL;                      /* R0. */
     pxTopOfStack--;
-    *pxTopOfStack = 0x00000000UL;   /* USPRG0. */
+    *pxTopOfStack = 0x00000000UL;                      /* USPRG0. */
     pxTopOfStack--;
-    *pxTopOfStack = 0x00000000UL;   /* CR. */
+    *pxTopOfStack = 0x00000000UL;                      /* CR. */
     pxTopOfStack--;
-    *pxTopOfStack = 0x00000000UL;   /* XER. */
+    *pxTopOfStack = 0x00000000UL;                      /* XER. */
     pxTopOfStack--;
-    *pxTopOfStack = 0x00000000UL;   /* CTR. */
+    *pxTopOfStack = 0x00000000UL;                      /* CTR. */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) vPortEndScheduler;  /* LR. */
+    *pxTopOfStack = ( StackType_t ) vPortEndScheduler; /* LR. */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) pxCode; /* SRR0. */
+    *pxTopOfStack = ( StackType_t ) pxCode;            /* SRR0. */
     pxTopOfStack--;
-    *pxTopOfStack = portINITIAL_MSR;/* SRR1. */
+    *pxTopOfStack = portINITIAL_MSR;                   /* SRR1. */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) vPortEndScheduler;/* Next LR. */
+    *pxTopOfStack = ( StackType_t ) vPortEndScheduler; /* Next LR. */
     pxTopOfStack--;
-    *pxTopOfStack = 0x00000000UL;/* Backchain. */
+    *pxTopOfStack = 0x00000000UL;                      /* Backchain. */
 
     return pxTopOfStack;
 }
@@ -158,7 +160,9 @@ BaseType_t xPortStartScheduler( void )
 void vPortEndScheduler( void )
 {
     /* Not implemented. */
-    for( ;; );
+    for( ; ; )
+    {
+    }
 }
 /*-----------------------------------------------------------*/
 
@@ -167,7 +171,7 @@ void vPortEndScheduler( void )
  */
 static void prvSetupTimerInterrupt( void )
 {
-const uint32_t ulInterval = ( ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL );
+    const uint32_t ulInterval = ( ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL );
 
     XTime_PITClearInterrupt();
     XTime_FITClearInterrupt();
@@ -183,18 +187,18 @@ const uint32_t ulInterval = ( ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL
 }
 /*-----------------------------------------------------------*/
 
-void vPortISRHandler( void *pvNullDoNotUse )
+void vPortISRHandler( void * pvNullDoNotUse )
 {
-uint32_t ulInterruptStatus, ulInterruptMask = 1UL;
-BaseType_t xInterruptNumber;
-XIntc_Config *pxInterruptController;
-XIntc_VectorTableEntry *pxTable;
+    uint32_t ulInterruptStatus, ulInterruptMask = 1UL;
+    BaseType_t xInterruptNumber;
+    XIntc_Config * pxInterruptController;
+    XIntc_VectorTableEntry * pxTable;
 
     /* Just to remove compiler warning. */
     ( void ) pvNullDoNotUse;
 
     /* Get the configuration by using the device ID - in this case it is
-    assumed that only one interrupt controller is being used. */
+     * assumed that only one interrupt controller is being used. */
     pxInterruptController = &XIntc_ConfigTable[ XPAR_XPS_INTC_0_DEVICE_ID ];
 
     /* Which interrupts are pending? */
@@ -227,29 +231,31 @@ XIntc_VectorTableEntry *pxTable;
 
 void vPortSetupInterruptController( void )
 {
-extern void vPortISRWrapper( void );
+    extern void vPortISRWrapper( void );
 
     /* Perform all library calls necessary to initialise the exception table
-    and interrupt controller.  This assumes only one interrupt controller is in
-    use. */
+     * and interrupt controller.  This assumes only one interrupt controller is in
+     * use. */
     XExc_mDisableExceptions( XEXC_NON_CRITICAL );
     XExc_Init();
 
     /* The library functions save the context - we then jump to a wrapper to
-    save the stack into the TCB.  The wrapper then calls the handler defined
-    above. */
+     * save the stack into the TCB.  The wrapper then calls the handler defined
+     * above. */
     XExc_RegisterHandler( XEXC_ID_NON_CRITICAL_INT, ( XExceptionHandler ) vPortISRWrapper, NULL );
     XIntc_Initialize( &xInterruptController, XPAR_XPS_INTC_0_DEVICE_ID );
     XIntc_Start( &xInterruptController, XIN_REAL_MODE );
 }
 /*-----------------------------------------------------------*/
 
-BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef )
+BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID,
+                                         XInterruptHandler pxHandler,
+                                         void * pvCallBackRef )
 {
-BaseType_t xReturn = pdFAIL;
+    BaseType_t xReturn = pdFAIL;
 
     /* This function is defined here so the scope of xInterruptController can
-    remain within this file. */
+     * remain within this file. */
 
     if( XST_SUCCESS == XIntc_Connect( &xInterruptController, ucInterruptID, pxHandler, pvCallBackRef ) )
     {
diff --git a/portable/GCC/PPC405_Xilinx/portmacro.h b/portable/GCC/PPC405_Xilinx/portmacro.h
index 06cca5df9..fe0ca70cd 100644
--- a/portable/GCC/PPC405_Xilinx/portmacro.h
+++ b/portable/GCC/PPC405_Xilinx/portmacro.h
@@ -48,72 +48,74 @@
  */
 
 /* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint32_t
-#define portBASE_TYPE   long
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY ( TickType_t )    ( 0xFFFFFFFFUL )
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) ( 0xFFFFFFFFUL )
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
 /*-----------------------------------------------------------*/
 
 /* This port uses the critical nesting count from the TCB rather than
-maintaining a separate value and then saving this value in the task stack. */
-#define portCRITICAL_NESTING_IN_TCB     1
+ * maintaining a separate value and then saving this value in the task stack. */
+#define portCRITICAL_NESTING_IN_TCB    1
 
 /* Interrupt control macros. */
-#define portDISABLE_INTERRUPTS()        XExc_mDisableExceptions( XEXC_NON_CRITICAL );
-#define portENABLE_INTERRUPTS()         XExc_mEnableExceptions( XEXC_NON_CRITICAL );
+#define portDISABLE_INTERRUPTS()    XExc_mDisableExceptions( XEXC_NON_CRITICAL );
+#define portENABLE_INTERRUPTS()     XExc_mEnableExceptions( XEXC_NON_CRITICAL );
 
 /*-----------------------------------------------------------*/
 
 /* Critical section macros. */
 void vTaskEnterCritical( void );
 void vTaskExitCritical( void );
-#define portENTER_CRITICAL()            vTaskEnterCritical()
-#define portEXIT_CRITICAL()             vTaskExitCritical()
+#define portENTER_CRITICAL()    vTaskEnterCritical()
+#define portEXIT_CRITICAL()     vTaskExitCritical()
 
 /*-----------------------------------------------------------*/
 
 /* Task utilities. */
 void vPortYield( void );
-#define portYIELD() asm volatile ( "SC \n\t NOP" )
-#define portYIELD_FROM_ISR() vTaskSwitchContext()
+#define portYIELD()             asm volatile ( "SC \n\t NOP" )
+#define portYIELD_FROM_ISR()    vTaskSwitchContext()
 
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portBYTE_ALIGNMENT          8
-#define portSTACK_GROWTH            ( -1 )
-#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portNOP()                   asm volatile ( "NOP" )
+#define portBYTE_ALIGNMENT    8
+#define portSTACK_GROWTH      ( -1 )
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()    asm volatile ( "NOP" )
 
-/* There are 32 * 32bit floating point regieters, plus the FPSCR to save. */
-#define portNO_FLOP_REGISTERS_TO_SAVE  ( 32 + 1 )
+/* There are 32 * 32bit floating point registers, plus the FPSCR to save. */
+#define portNO_FLOP_REGISTERS_TO_SAVE    ( 32 + 1 )
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
 /* Port specific interrupt handling functions. */
 void vPortSetupInterruptController( void );
-BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef );
+BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID,
+                                         XInterruptHandler pxHandler,
+                                         void * pvCallBackRef );
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/GCC/PPC440_Xilinx/FPU_Macros.h b/portable/GCC/PPC440_Xilinx/FPU_Macros.h
index 9c566588a..9d7f96ff9 100644
--- a/portable/GCC/PPC440_Xilinx/FPU_Macros.h
+++ b/portable/GCC/PPC440_Xilinx/FPU_Macros.h
@@ -27,16 +27,16 @@
  */
 
 /* When switching out a task, if the task tag contains a buffer address then
-save the flop context into the buffer. */
-#define traceTASK_SWITCHED_OUT()                                            \
-    if( pxCurrentTCB->pxTaskTag != NULL )                                   \
-    {                                                                       \
-        extern void vPortSaveFPURegisters( void * );                        \
-        vPortSaveFPURegisters( ( void * ) ( pxCurrentTCB->pxTaskTag ) );    \
+ * save the flop context into the buffer. */
+#define traceTASK_SWITCHED_OUT()                                         \
+    if( pxCurrentTCB->pxTaskTag != NULL )                                \
+    {                                                                    \
+        extern void vPortSaveFPURegisters( void * );                     \
+        vPortSaveFPURegisters( ( void * ) ( pxCurrentTCB->pxTaskTag ) ); \
     }
 
 /* When switching in a task, if the task tag contains a buffer address then
-load the flop context from the buffer. */
+ * load the flop context from the buffer. */
 #define traceTASK_SWITCHED_IN()                                             \
     if( pxCurrentTCB->pxTaskTag != NULL )                                   \
     {                                                                       \
diff --git a/portable/GCC/PPC440_Xilinx/port.c b/portable/GCC/PPC440_Xilinx/port.c
index 89caeac7c..d36e74300 100644
--- a/portable/GCC/PPC440_Xilinx/port.c
+++ b/portable/GCC/PPC440_Xilinx/port.c
@@ -27,8 +27,8 @@
  */
 
 /*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the PPC440 port.
- *----------------------------------------------------------*/
+* Implementation of functions defined in portable.h for the PPC440 port.
+*----------------------------------------------------------*/
 
 
 /* Scheduler includes. */
@@ -43,19 +43,19 @@
 /*-----------------------------------------------------------*/
 
 /* Definitions to set the initial MSR of each task. */
-#define portCRITICAL_INTERRUPT_ENABLE   ( 1UL << 17UL )
-#define portEXTERNAL_INTERRUPT_ENABLE   ( 1UL << 15UL )
-#define portMACHINE_CHECK_ENABLE        ( 1UL << 12UL )
+#define portCRITICAL_INTERRUPT_ENABLE    ( 1UL << 17UL )
+#define portEXTERNAL_INTERRUPT_ENABLE    ( 1UL << 15UL )
+#define portMACHINE_CHECK_ENABLE         ( 1UL << 12UL )
 
 #if configUSE_FPU == 1
-    #define portAPU_PRESENT             ( 1UL << 25UL )
-    #define portFCM_FPU_PRESENT         ( 1UL << 13UL )
+    #define portAPU_PRESENT              ( 1UL << 25UL )
+    #define portFCM_FPU_PRESENT          ( 1UL << 13UL )
 #else
-    #define portAPU_PRESENT             ( 0UL )
-    #define portFCM_FPU_PRESENT         ( 0UL )
+    #define portAPU_PRESENT              ( 0UL )
+    #define portFCM_FPU_PRESENT          ( 0UL )
 #endif
 
-#define portINITIAL_MSR     ( portCRITICAL_INTERRUPT_ENABLE | portEXTERNAL_INTERRUPT_ENABLE | portMACHINE_CHECK_ENABLE | portAPU_PRESENT | portFCM_FPU_PRESENT )
+#define portINITIAL_MSR                  ( portCRITICAL_INTERRUPT_ENABLE | portEXTERNAL_INTERRUPT_ENABLE | portMACHINE_CHECK_ENABLE | portAPU_PRESENT | portFCM_FPU_PRESENT )
 
 
 extern const unsigned _SDA_BASE_;
@@ -97,7 +97,9 @@ static XIntc xInterruptController;
  *
  * See the header file portable.h.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
     /* Place a known value at the bottom of the stack for debugging. */
     *pxTopOfStack = 0xDEADBEEF;
@@ -115,30 +117,30 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
     pxTopOfStack--;
 
     /* Parameters in R2. */
-    *pxTopOfStack = ( StackType_t ) &_SDA2_BASE_;   /* address of the second small data area */
+    *pxTopOfStack = ( StackType_t ) &_SDA2_BASE_; /* address of the second small data area */
     pxTopOfStack--;
 
     /* R1 is the stack pointer so is omitted. */
 
-    *pxTopOfStack = 0x10000001UL;;  /* R0. */
+    *pxTopOfStack = 0x10000001UL;                      /* R0. */
     pxTopOfStack--;
-    *pxTopOfStack = 0x00000000UL;   /* USPRG0. */
+    *pxTopOfStack = 0x00000000UL;                      /* USPRG0. */
     pxTopOfStack--;
-    *pxTopOfStack = 0x00000000UL;   /* CR. */
+    *pxTopOfStack = 0x00000000UL;                      /* CR. */
     pxTopOfStack--;
-    *pxTopOfStack = 0x00000000UL;   /* XER. */
+    *pxTopOfStack = 0x00000000UL;                      /* XER. */
     pxTopOfStack--;
-    *pxTopOfStack = 0x00000000UL;   /* CTR. */
+    *pxTopOfStack = 0x00000000UL;                      /* CTR. */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) vPortEndScheduler;  /* LR. */
+    *pxTopOfStack = ( StackType_t ) vPortEndScheduler; /* LR. */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) pxCode; /* SRR0. */
+    *pxTopOfStack = ( StackType_t ) pxCode;            /* SRR0. */
     pxTopOfStack--;
-    *pxTopOfStack = portINITIAL_MSR;/* SRR1. */
+    *pxTopOfStack = portINITIAL_MSR;                   /* SRR1. */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) vPortEndScheduler;/* Next LR. */
+    *pxTopOfStack = ( StackType_t ) vPortEndScheduler; /* Next LR. */
     pxTopOfStack--;
-    *pxTopOfStack = 0x00000000UL;/* Backchain. */
+    *pxTopOfStack = 0x00000000UL;                      /* Backchain. */
 
     return pxTopOfStack;
 }
@@ -158,7 +160,9 @@ BaseType_t xPortStartScheduler( void )
 void vPortEndScheduler( void )
 {
     /* Not implemented. */
-    for( ;; );
+    for( ; ; )
+    {
+    }
 }
 /*-----------------------------------------------------------*/
 
@@ -167,7 +171,7 @@ void vPortEndScheduler( void )
  */
 static void prvSetupTimerInterrupt( void )
 {
-const uint32_t ulInterval = ( ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL );
+    const uint32_t ulInterval = ( ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL );
 
     XTime_DECClearInterrupt();
     XTime_FITClearInterrupt();
@@ -183,18 +187,18 @@ const uint32_t ulInterval = ( ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL
 }
 /*-----------------------------------------------------------*/
 
-void vPortISRHandler( void *pvNullDoNotUse )
+void vPortISRHandler( void * pvNullDoNotUse )
 {
-uint32_t ulInterruptStatus, ulInterruptMask = 1UL;
-BaseType_t xInterruptNumber;
-XIntc_Config *pxInterruptController;
-XIntc_VectorTableEntry *pxTable;
+    uint32_t ulInterruptStatus, ulInterruptMask = 1UL;
+    BaseType_t xInterruptNumber;
+    XIntc_Config * pxInterruptController;
+    XIntc_VectorTableEntry * pxTable;
 
     /* Just to remove compiler warning. */
     ( void ) pvNullDoNotUse;
 
     /* Get the configuration by using the device ID - in this case it is
-    assumed that only one interrupt controller is being used. */
+     * assumed that only one interrupt controller is being used. */
     pxInterruptController = &XIntc_ConfigTable[ XPAR_XPS_INTC_0_DEVICE_ID ];
 
     /* Which interrupts are pending? */
@@ -227,29 +231,31 @@ XIntc_VectorTableEntry *pxTable;
 
 void vPortSetupInterruptController( void )
 {
-extern void vPortISRWrapper( void );
+    extern void vPortISRWrapper( void );
 
     /* Perform all library calls necessary to initialise the exception table
-    and interrupt controller.  This assumes only one interrupt controller is in
-    use. */
+     * and interrupt controller.  This assumes only one interrupt controller is in
+     * use. */
     XExc_mDisableExceptions( XEXC_NON_CRITICAL );
     XExc_Init();
 
     /* The library functions save the context - we then jump to a wrapper to
-    save the stack into the TCB.  The wrapper then calls the handler defined
-    above. */
+     * save the stack into the TCB.  The wrapper then calls the handler defined
+     * above. */
     XExc_RegisterHandler( XEXC_ID_NON_CRITICAL_INT, ( XExceptionHandler ) vPortISRWrapper, NULL );
     XIntc_Initialize( &xInterruptController, XPAR_XPS_INTC_0_DEVICE_ID );
     XIntc_Start( &xInterruptController, XIN_REAL_MODE );
 }
 /*-----------------------------------------------------------*/
 
-BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef )
+BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID,
+                                         XInterruptHandler pxHandler,
+                                         void * pvCallBackRef )
 {
-BaseType_t xReturn = pdFAIL;
+    BaseType_t xReturn = pdFAIL;
 
     /* This function is defined here so the scope of xInterruptController can
-    remain within this file. */
+     * remain within this file. */
 
     if( XST_SUCCESS == XIntc_Connect( &xInterruptController, ucInterruptID, pxHandler, pvCallBackRef ) )
     {
diff --git a/portable/GCC/PPC440_Xilinx/portmacro.h b/portable/GCC/PPC440_Xilinx/portmacro.h
index 06cca5df9..fe0ca70cd 100644
--- a/portable/GCC/PPC440_Xilinx/portmacro.h
+++ b/portable/GCC/PPC440_Xilinx/portmacro.h
@@ -48,72 +48,74 @@
  */
 
 /* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint32_t
-#define portBASE_TYPE   long
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY ( TickType_t )    ( 0xFFFFFFFFUL )
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) ( 0xFFFFFFFFUL )
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
 /*-----------------------------------------------------------*/
 
 /* This port uses the critical nesting count from the TCB rather than
-maintaining a separate value and then saving this value in the task stack. */
-#define portCRITICAL_NESTING_IN_TCB     1
+ * maintaining a separate value and then saving this value in the task stack. */
+#define portCRITICAL_NESTING_IN_TCB    1
 
 /* Interrupt control macros. */
-#define portDISABLE_INTERRUPTS()        XExc_mDisableExceptions( XEXC_NON_CRITICAL );
-#define portENABLE_INTERRUPTS()         XExc_mEnableExceptions( XEXC_NON_CRITICAL );
+#define portDISABLE_INTERRUPTS()    XExc_mDisableExceptions( XEXC_NON_CRITICAL );
+#define portENABLE_INTERRUPTS()     XExc_mEnableExceptions( XEXC_NON_CRITICAL );
 
 /*-----------------------------------------------------------*/
 
 /* Critical section macros. */
 void vTaskEnterCritical( void );
 void vTaskExitCritical( void );
-#define portENTER_CRITICAL()            vTaskEnterCritical()
-#define portEXIT_CRITICAL()             vTaskExitCritical()
+#define portENTER_CRITICAL()    vTaskEnterCritical()
+#define portEXIT_CRITICAL()     vTaskExitCritical()
 
 /*-----------------------------------------------------------*/
 
 /* Task utilities. */
 void vPortYield( void );
-#define portYIELD() asm volatile ( "SC \n\t NOP" )
-#define portYIELD_FROM_ISR() vTaskSwitchContext()
+#define portYIELD()             asm volatile ( "SC \n\t NOP" )
+#define portYIELD_FROM_ISR()    vTaskSwitchContext()
 
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portBYTE_ALIGNMENT          8
-#define portSTACK_GROWTH            ( -1 )
-#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portNOP()                   asm volatile ( "NOP" )
+#define portBYTE_ALIGNMENT    8
+#define portSTACK_GROWTH      ( -1 )
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()    asm volatile ( "NOP" )
 
-/* There are 32 * 32bit floating point regieters, plus the FPSCR to save. */
-#define portNO_FLOP_REGISTERS_TO_SAVE  ( 32 + 1 )
+/* There are 32 * 32bit floating point registers, plus the FPSCR to save. */
+#define portNO_FLOP_REGISTERS_TO_SAVE    ( 32 + 1 )
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
 /* Port specific interrupt handling functions. */
 void vPortSetupInterruptController( void );
-BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef );
+BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID,
+                                         XInterruptHandler pxHandler,
+                                         void * pvCallBackRef );
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h b/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h
index 262c337b3..df7be85fc 100644
--- a/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h
+++ b/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h
@@ -58,51 +58,51 @@
 #ifndef __FREERTOS_RISC_V_EXTENSIONS_H__
 #define __FREERTOS_RISC_V_EXTENSIONS_H__
 
-#define portasmHAS_MTIME 0
+#define portasmHAS_MTIME                  0
 
 /* Constants to define the additional registers found on the Pulpino RI5KY. */
-#define lpstart0    0x7b0
-#define lpend0      0x7b1
-#define lpcount0    0x7b2
-#define lpstart1    0x7b4
-#define lpend1      0x7b5
-#define lpcount1    0x7b6
+#define lpstart0                          0x7b0
+#define lpend0                            0x7b1
+#define lpcount0                          0x7b2
+#define lpstart1                          0x7b4
+#define lpend1                            0x7b5
+#define lpcount1                          0x7b6
 
 /* Six additional registers to save and restore, as per the #defines above. */
-#define portasmADDITIONAL_CONTEXT_SIZE 6 /* Must be even number on 32-bit cores. */
+#define portasmADDITIONAL_CONTEXT_SIZE    6 /* Must be even number on 32-bit cores. */
 
 /* Save additional registers found on the Pulpino. */
 .macro portasmSAVE_ADDITIONAL_REGISTERS
-    addi sp, sp, -(portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE) /* Make room for the additional registers. */
-    csrr t0, lpstart0                            /* Load additional registers into accessible temporary registers. */
-    csrr t1, lpend0
-    csrr t2, lpcount0
-    csrr t3, lpstart1
-    csrr t4, lpend1
-    csrr t5, lpcount1
-    sw t0, 1 * portWORD_SIZE( sp )
-    sw t1, 2 * portWORD_SIZE( sp )
-    sw t2, 3 * portWORD_SIZE( sp )
-    sw t3, 4 * portWORD_SIZE( sp )
-    sw t4, 5 * portWORD_SIZE( sp )
-    sw t5, 6 * portWORD_SIZE( sp )
-    .endm
+addi sp, sp, -( portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE ) /* Make room for the additional registers. */
+csrr t0, lpstart0                                                /* Load additional registers into accessible temporary registers. */
+csrr t1, lpend0
+csrr t2, lpcount0
+csrr t3, lpstart1
+csrr t4, lpend1
+csrr t5, lpcount1
+sw t0, 1 * portWORD_SIZE( sp )
+sw t1, 2 * portWORD_SIZE( sp )
+sw t2, 3 * portWORD_SIZE( sp )
+sw t3, 4 * portWORD_SIZE( sp )
+sw t4, 5 * portWORD_SIZE( sp )
+sw t5, 6 * portWORD_SIZE( sp )
+   .endm
 
 /* Restore the additional registers found on the Pulpino. */
-.macro portasmRESTORE_ADDITIONAL_REGISTERS
-    lw t0, 1 * portWORD_SIZE( sp )          /* Load additional registers into accessible temporary registers. */
-    lw t1, 2 * portWORD_SIZE( sp )
-    lw t2, 3 * portWORD_SIZE( sp )
-    lw t3, 4 * portWORD_SIZE( sp )
-    lw t4, 5 * portWORD_SIZE( sp )
-    lw t5, 6 * portWORD_SIZE( sp )
-    csrw lpstart0, t0
-    csrw lpend0, t1
-    csrw lpcount0, t2
-    csrw lpstart1, t3
-    csrw lpend1, t4
-    csrw lpcount1, t5
-    addi sp, sp, (portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE )/* Remove space added for additional registers. */
-    .endm
+   .macro portasmRESTORE_ADDITIONAL_REGISTERS
+lw t0, 1 * portWORD_SIZE( sp ) /* Load additional registers into accessible temporary registers. */
+lw t1, 2 * portWORD_SIZE( sp )
+lw t2, 3 * portWORD_SIZE( sp )
+lw t3, 4 * portWORD_SIZE( sp )
+lw t4, 5 * portWORD_SIZE( sp )
+lw t5, 6 * portWORD_SIZE( sp )
+csrw lpstart0, t0
+csrw lpend0, t1
+csrw lpcount0, t2
+csrw lpstart1, t3
+csrw lpend1, t4
+csrw lpcount1, t5
+addi sp, sp, ( portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE ) /* Remove space added for additional registers. */
+   .endm
 
 #endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */
diff --git a/portable/GCC/RISC-V/chip_specific_extensions/RISCV_MTIME_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h b/portable/GCC/RISC-V/chip_specific_extensions/RISCV_MTIME_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h
index f525e73ad..d4850841f 100644
--- a/portable/GCC/RISC-V/chip_specific_extensions/RISCV_MTIME_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h
+++ b/portable/GCC/RISC-V/chip_specific_extensions/RISCV_MTIME_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h
@@ -54,16 +54,16 @@
 #ifndef __FREERTOS_RISC_V_EXTENSIONS_H__
 #define __FREERTOS_RISC_V_EXTENSIONS_H__
 
-#define portasmHAS_SIFIVE_CLINT         1
-#define portasmHAS_MTIME                1
-#define portasmADDITIONAL_CONTEXT_SIZE  0
+#define portasmHAS_SIFIVE_CLINT           1
+#define portasmHAS_MTIME                  1
+#define portasmADDITIONAL_CONTEXT_SIZE    0
 
 .macro portasmSAVE_ADDITIONAL_REGISTERS
-    /* No additional registers to save, so this macro does nothing. */
-    .endm
+/* No additional registers to save, so this macro does nothing. */
+   .endm
 
-.macro portasmRESTORE_ADDITIONAL_REGISTERS
-    /* No additional registers to restore, so this macro does nothing. */
-    .endm
+   .macro portasmRESTORE_ADDITIONAL_REGISTERS
+/* No additional registers to restore, so this macro does nothing. */
+   .endm
 
 #endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */
diff --git a/portable/GCC/RISC-V/chip_specific_extensions/RISCV_no_extensions/freertos_risc_v_chip_specific_extensions.h b/portable/GCC/RISC-V/chip_specific_extensions/RISCV_no_extensions/freertos_risc_v_chip_specific_extensions.h
index 4a841f4bb..930e50354 100644
--- a/portable/GCC/RISC-V/chip_specific_extensions/RISCV_no_extensions/freertos_risc_v_chip_specific_extensions.h
+++ b/portable/GCC/RISC-V/chip_specific_extensions/RISCV_no_extensions/freertos_risc_v_chip_specific_extensions.h
@@ -54,16 +54,16 @@
 #ifndef __FREERTOS_RISC_V_EXTENSIONS_H__
 #define __FREERTOS_RISC_V_EXTENSIONS_H__
 
-#define portasmHAS_SIFIVE_CLINT         0
-#define portasmHAS_MTIME                0
-#define portasmADDITIONAL_CONTEXT_SIZE  0
+#define portasmHAS_SIFIVE_CLINT           0
+#define portasmHAS_MTIME                  0
+#define portasmADDITIONAL_CONTEXT_SIZE    0
 
 .macro portasmSAVE_ADDITIONAL_REGISTERS
-    /* No additional registers to save, so this macro does nothing. */
-    .endm
+/* No additional registers to save, so this macro does nothing. */
+   .endm
 
-.macro portasmRESTORE_ADDITIONAL_REGISTERS
-    /* No additional registers to restore, so this macro does nothing. */
-    .endm
+   .macro portasmRESTORE_ADDITIONAL_REGISTERS
+/* No additional registers to restore, so this macro does nothing. */
+   .endm
 
 #endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */
diff --git a/portable/GCC/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h b/portable/GCC/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h
index 65204a282..bac15e4d8 100644
--- a/portable/GCC/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h
+++ b/portable/GCC/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h
@@ -54,16 +54,16 @@
 #ifndef __FREERTOS_RISC_V_EXTENSIONS_H__
 #define __FREERTOS_RISC_V_EXTENSIONS_H__
 
-#define portasmHAS_SIFIVE_CLINT 1
-#define portasmHAS_MTIME 1
-#define portasmADDITIONAL_CONTEXT_SIZE 0 /* Must be even number on 32-bit cores. */
+#define portasmHAS_SIFIVE_CLINT           1
+#define portasmHAS_MTIME                  1
+#define portasmADDITIONAL_CONTEXT_SIZE    0 /* Must be even number on 32-bit cores. */
 
 .macro portasmSAVE_ADDITIONAL_REGISTERS
-    /* No additional registers to save, so this macro does nothing. */
-    .endm
+/* No additional registers to save, so this macro does nothing. */
+   .endm
 
-.macro portasmRESTORE_ADDITIONAL_REGISTERS
-    /* No additional registers to restore, so this macro does nothing. */
-    .endm
+   .macro portasmRESTORE_ADDITIONAL_REGISTERS
+/* No additional registers to restore, so this macro does nothing. */
+   .endm
 
 #endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */
diff --git a/portable/GCC/RISC-V/port.c b/portable/GCC/RISC-V/port.c
index 628df8307..e0648aa9c 100644
--- a/portable/GCC/RISC-V/port.c
+++ b/portable/GCC/RISC-V/port.c
@@ -27,8 +27,8 @@
  */
 
 /*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the RISC-V port.
- *----------------------------------------------------------*/
+* Implementation of functions defined in portable.h for the RISC-V port.
+*----------------------------------------------------------*/
 
 /* Scheduler includes. */
 #include "FreeRTOS.h"
@@ -39,15 +39,15 @@
 #include "string.h"
 
 #ifdef configCLINT_BASE_ADDRESS
-    #warning The configCLINT_BASE_ADDRESS constant has been deprecated.  configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS are currently being derived from the (possibly 0) configCLINT_BASE_ADDRESS setting.  Please update to define configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS dirctly in place of configCLINT_BASE_ADDRESS.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
+    #warning "The configCLINT_BASE_ADDRESS constant has been deprecated. configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS are currently being derived from the (possibly 0) configCLINT_BASE_ADDRESS setting.  Please update to define configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS directly in place of configCLINT_BASE_ADDRESS. See www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html"
 #endif
 
 #ifndef configMTIME_BASE_ADDRESS
-    #warning configMTIME_BASE_ADDRESS must be defined in FreeRTOSConfig.h.  If the target chip includes a memory-mapped mtime register then set configMTIME_BASE_ADDRESS to the mapped address.  Otherwise set configMTIME_BASE_ADDRESS to 0.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
+    #warning "configMTIME_BASE_ADDRESS must be defined in FreeRTOSConfig.h. If the target chip includes a memory-mapped mtime register then set configMTIME_BASE_ADDRESS to the mapped address.  Otherwise set configMTIME_BASE_ADDRESS to 0.  See www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html"
 #endif
 
 #ifndef configMTIMECMP_BASE_ADDRESS
-    #warning configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h.  If the target chip includes a memory-mapped mtimecmp register then set configMTIMECMP_BASE_ADDRESS to the mapped address.  Otherwise set configMTIMECMP_BASE_ADDRESS to 0.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
+    #warning "configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h. If the target chip includes a memory-mapped mtimecmp register then set configMTIMECMP_BASE_ADDRESS to the mapped address.  Otherwise set configMTIMECMP_BASE_ADDRESS to 0.  See www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html"
 #endif
 
 /* Let the user override the pre-loading of the initial RA. */
@@ -65,12 +65,12 @@
  * stack that was used by main before the scheduler was started for use as the
  * interrupt stack after the scheduler has started. */
 #ifdef configISR_STACK_SIZE_WORDS
-    static __attribute__ ((aligned(16))) StackType_t xISRStack[ configISR_STACK_SIZE_WORDS ] = { 0 };
-    const StackType_t xISRStackTop = ( StackType_t ) &( xISRStack[ configISR_STACK_SIZE_WORDS & ~portBYTE_ALIGNMENT_MASK ] );
+static __attribute__( ( aligned( 16 ) ) ) StackType_t xISRStack[ configISR_STACK_SIZE_WORDS ] = { 0 };
+const StackType_t xISRStackTop = ( StackType_t ) &( xISRStack[ configISR_STACK_SIZE_WORDS & ~portBYTE_ALIGNMENT_MASK ] );
 
-    /* Don't use 0xa5 as the stack fill bytes as that is used by the kernerl for
-    the task stacks, and so will legitimately appear in many positions within
-    the ISR stack. */
+/* Don't use 0xa5 as the stack fill bytes as that is used by the kernel for
+ * the task stacks, and so will legitimately appear in many positions within
+ * the ISR stack. */
     #define portISR_STACK_FILL_BYTE    0xee
 #else
     extern const uint32_t __freertos_irq_stack_top[];
@@ -82,13 +82,13 @@
  * file is weak to allow application writers to change the timer used to
  * generate the tick interrupt.
  */
-void vPortSetupTimerInterrupt( void ) __attribute__(( weak ));
+void vPortSetupTimerInterrupt( void ) __attribute__( ( weak ) );
 
 /*-----------------------------------------------------------*/
 
 /* Used to program the machine timer compare register. */
 uint64_t ullNextTime = 0ULL;
-const uint64_t *pullNextTime = &ullNextTime;
+const uint64_t * pullNextTime = &ullNextTime;
 const size_t uxTimerIncrementsForOneTick = ( size_t ) ( ( configCPU_CLOCK_HZ ) / ( configTICK_RATE_HZ ) ); /* Assumes increment won't go over 32-bits. */
 uint32_t const ullMachineTimerCompareRegisterBase = configMTIMECMP_BASE_ADDRESS;
 volatile uint64_t * pullMachineTimerCompareRegister = NULL;
@@ -96,7 +96,7 @@ volatile uint64_t * pullMachineTimerCompareRegister = NULL;
 /* Holds the critical nesting value - deliberately non-zero at start up to
  * ensure interrupts are not accidentally enabled before the scheduler starts. */
 size_t xCriticalNesting = ( size_t ) 0xaaaaaaaa;
-size_t *pxCriticalNesting = &xCriticalNesting;
+size_t * pxCriticalNesting = &xCriticalNesting;
 
 /* Used to catch tasks that attempt to return from their implementing function. */
 size_t xTaskReturnAddress = ( size_t ) portTASK_RETURN_ADDRESS;
@@ -106,34 +106,37 @@ size_t xTaskReturnAddress = ( size_t ) portTASK_RETURN_ADDRESS;
  * the stack overflow hook function (because the stack overflow hook is specific
  * to a task stack, not the ISR stack). */
 #if defined( configISR_STACK_SIZE_WORDS ) && ( configCHECK_FOR_STACK_OVERFLOW > 2 )
-    #warning This path not tested, or even compiled yet.
+    #warning "This path not tested, or even compiled yet."
 
-    static const uint8_t ucExpectedStackBytes[] = {
-                                    portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,        \
-                                    portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,        \
-                                    portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,        \
-                                    portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,        \
-                                    portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE };    \
+    static const uint8_t ucExpectedStackBytes[] =
+    {
+        portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
+        portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
+        portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
+        portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
+        portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE
+    }; \
 
-    #define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
-#else
+    #define portCHECK_ISR_STACK()    configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
+#else /* if defined( configISR_STACK_SIZE_WORDS ) && ( configCHECK_FOR_STACK_OVERFLOW > 2 ) */
     /* Define the function away. */
     #define portCHECK_ISR_STACK()
 #endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
 
 /*-----------------------------------------------------------*/
 
-#if( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 )
+#if ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 )
 
     void vPortSetupTimerInterrupt( void )
     {
-    uint32_t ulCurrentTimeHigh, ulCurrentTimeLow;
-    volatile uint32_t * const pulTimeHigh = ( volatile uint32_t * const ) ( ( configMTIME_BASE_ADDRESS ) + 4UL ); /* 8-byte type so high 32-bit word is 4 bytes up. */
-    volatile uint32_t * const pulTimeLow = ( volatile uint32_t * const ) ( configMTIME_BASE_ADDRESS );
-    volatile uint32_t ulHartId;
+        uint32_t ulCurrentTimeHigh, ulCurrentTimeLow;
+        volatile uint32_t * const pulTimeHigh = ( volatile uint32_t * const ) ( ( configMTIME_BASE_ADDRESS ) + 4UL ); /* 8-byte type so high 32-bit word is 4 bytes up. */
+        volatile uint32_t * const pulTimeLow = ( volatile uint32_t * const ) ( configMTIME_BASE_ADDRESS );
+        volatile uint32_t ulHartId;
 
-        __asm volatile( "csrr %0, mhartid" : "=r"( ulHartId ) );
-        pullMachineTimerCompareRegister  = ( volatile uint64_t * ) ( ullMachineTimerCompareRegisterBase + ( ulHartId * sizeof( uint64_t ) ) );
+        __asm volatile ( "csrr %0, mhartid" : "=r" ( ulHartId ) );
+
+        pullMachineTimerCompareRegister = ( volatile uint64_t * ) ( ullMachineTimerCompareRegisterBase + ( ulHartId * sizeof( uint64_t ) ) );
 
         do
         {
@@ -156,9 +159,9 @@ size_t xTaskReturnAddress = ( size_t ) portTASK_RETURN_ADDRESS;
 
 BaseType_t xPortStartScheduler( void )
 {
-extern void xPortStartFirstTask( void );
+    extern void xPortStartFirstTask( void );
 
-    #if( configASSERT_DEFINED == 1 )
+    #if ( configASSERT_DEFINED == 1 )
     {
         /* Check alignment of the interrupt stack - which is the same as the
          * stack that was being used by main() prior to the scheduler being
@@ -178,12 +181,12 @@ extern void xPortStartFirstTask( void );
      * configure whichever clock is to be used to generate the tick interrupt. */
     vPortSetupTimerInterrupt();
 
-    #if( ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 ) )
+    #if ( ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 ) )
     {
         /* Enable mtime and external interrupts.  1<<7 for timer interrupt,
          * 1<<11 for external interrupt.  _RB_ What happens here when mtime is
          * not present as with pulpino? */
-        __asm volatile( "csrs mie, %0" :: "r"(0x880) );
+        __asm volatile ( "csrs mie, %0" ::"r" ( 0x880 ) );
     }
     #endif /* ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 ) */
 
@@ -198,6 +201,8 @@ extern void xPortStartFirstTask( void );
 void vPortEndScheduler( void )
 {
     /* Not implemented. */
-    for( ;; );
+    for( ; ; )
+    {
+    }
 }
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/RISC-V/portContext.h b/portable/GCC/RISC-V/portContext.h
index c7eeeec66..7eb871a14 100644
--- a/portable/GCC/RISC-V/portContext.h
+++ b/portable/GCC/RISC-V/portContext.h
@@ -30,13 +30,13 @@
 #define PORTCONTEXT_H
 
 #if __riscv_xlen == 64
-    #define portWORD_SIZE 8
-    #define store_x sd
-    #define load_x ld
+    #define portWORD_SIZE    8
+    #define store_x          sd
+    #define load_x           ld
 #elif __riscv_xlen == 32
-    #define store_x sw
-    #define load_x lw
-    #define portWORD_SIZE 4
+    #define store_x          sw
+    #define load_x           lw
+    #define portWORD_SIZE    4
 #else
     #error Assembler did not define __riscv_xlen
 #endif
@@ -49,37 +49,37 @@
  * specific version of freertos_risc_v_chip_specific_extensions.h.  See the
  * notes at the top of portASM.S file. */
 #ifdef __riscv_32e
-    #define portCONTEXT_SIZE ( 15 * portWORD_SIZE )
-    #define portCRITICAL_NESTING_OFFSET 13
-    #define portMSTATUS_OFFSET  14
+    #define portCONTEXT_SIZE               ( 15 * portWORD_SIZE )
+    #define portCRITICAL_NESTING_OFFSET    13
+    #define portMSTATUS_OFFSET             14
 #else
-    #define portCONTEXT_SIZE ( 31 * portWORD_SIZE )
-    #define portCRITICAL_NESTING_OFFSET 29
-    #define portMSTATUS_OFFSET  30
+    #define portCONTEXT_SIZE               ( 31 * portWORD_SIZE )
+    #define portCRITICAL_NESTING_OFFSET    29
+    #define portMSTATUS_OFFSET             30
 #endif
 
 /*-----------------------------------------------------------*/
 
 .extern pxCurrentTCB
-.extern xISRStackTop
-.extern xCriticalNesting
-.extern pxCriticalNesting
+   .extern xISRStackTop
+   .extern xCriticalNesting
+   .extern pxCriticalNesting
 /*-----------------------------------------------------------*/
 
-.macro portcontextSAVE_CONTEXT_INTERNAL
-    addi sp, sp, -portCONTEXT_SIZE
-    store_x x1, 1 * portWORD_SIZE( sp )
-    store_x x5, 2 * portWORD_SIZE( sp )
-    store_x x6, 3 * portWORD_SIZE( sp )
-    store_x x7, 4 * portWORD_SIZE( sp )
-    store_x x8, 5 * portWORD_SIZE( sp )
-    store_x x9, 6 * portWORD_SIZE( sp )
-    store_x x10, 7 * portWORD_SIZE( sp )
-    store_x x11, 8 * portWORD_SIZE( sp )
-    store_x x12, 9 * portWORD_SIZE( sp )
-    store_x x13, 10 * portWORD_SIZE( sp )
-    store_x x14, 11 * portWORD_SIZE( sp )
-    store_x x15, 12 * portWORD_SIZE( sp )
+   .macro portcontextSAVE_CONTEXT_INTERNAL
+addi sp, sp, -portCONTEXT_SIZE
+store_x x1, 1 * portWORD_SIZE( sp )
+store_x x5, 2 * portWORD_SIZE( sp )
+store_x x6, 3 * portWORD_SIZE( sp )
+store_x x7, 4 * portWORD_SIZE( sp )
+store_x x8, 5 * portWORD_SIZE( sp )
+store_x x9, 6 * portWORD_SIZE( sp )
+store_x x10, 7 * portWORD_SIZE( sp )
+store_x x11, 8 * portWORD_SIZE( sp )
+store_x x12, 9 * portWORD_SIZE( sp )
+store_x x13, 10 * portWORD_SIZE( sp )
+store_x x14, 11 * portWORD_SIZE( sp )
+store_x x15, 12 * portWORD_SIZE( sp )
 #ifndef __riscv_32e
     store_x x16, 13 * portWORD_SIZE( sp )
     store_x x17, 14 * portWORD_SIZE( sp )
@@ -97,96 +97,96 @@
     store_x x29, 26 * portWORD_SIZE( sp )
     store_x x30, 27 * portWORD_SIZE( sp )
     store_x x31, 28 * portWORD_SIZE( sp )
-#endif
+#endif /* ifndef __riscv_32e */
 
-    load_x  t0, xCriticalNesting         /* Load the value of xCriticalNesting into t0. */
-    store_x t0, portCRITICAL_NESTING_OFFSET * portWORD_SIZE( sp ) /* Store the critical nesting value to the stack. */
+load_x t0, xCriticalNesting                                   /* Load the value of xCriticalNesting into t0. */
+store_x t0, portCRITICAL_NESTING_OFFSET * portWORD_SIZE( sp ) /* Store the critical nesting value to the stack. */
 
 
-    csrr t0, mstatus                     /* Required for MPIE bit. */
-    store_x t0, portMSTATUS_OFFSET * portWORD_SIZE( sp )
+csrr t0, mstatus /* Required for MPIE bit. */
+store_x t0, portMSTATUS_OFFSET * portWORD_SIZE( sp )
 
 
-    portasmSAVE_ADDITIONAL_REGISTERS     /* Defined in freertos_risc_v_chip_specific_extensions.h to save any registers unique to the RISC-V implementation. */
+portasmSAVE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to save any registers unique to the RISC-V implementation. */
 
-    load_x  t0, pxCurrentTCB             /* Load pxCurrentTCB. */
-    store_x  sp, 0( t0 )                 /* Write sp to first TCB member. */
+load_x t0, pxCurrentTCB          /* Load pxCurrentTCB. */
+store_x sp, 0 ( t0 )             /* Write sp to first TCB member. */
 
-    .endm
+   .endm
 /*-----------------------------------------------------------*/
 
-.macro portcontextSAVE_EXCEPTION_CONTEXT
-    portcontextSAVE_CONTEXT_INTERNAL
-    csrr a0, mcause
-    csrr a1, mepc
-    addi a1, a1, 4                      /* Synchronous so update exception return address to the instruction after the instruction that generated the exception. */
-    store_x a1, 0( sp )                 /* Save updated exception return address. */
-    load_x sp, xISRStackTop             /* Switch to ISR stack. */
-    .endm
+   .macro portcontextSAVE_EXCEPTION_CONTEXT
+portcontextSAVE_CONTEXT_INTERNAL
+csrr a0, mcause
+csrr a1, mepc
+addi a1, a1, 4          /* Synchronous so update exception return address to the instruction after the instruction that generated the exception. */
+store_x a1, 0 ( sp )    /* Save updated exception return address. */
+load_x sp, xISRStackTop /* Switch to ISR stack. */
+   .endm
 /*-----------------------------------------------------------*/
 
-.macro portcontextSAVE_INTERRUPT_CONTEXT
-    portcontextSAVE_CONTEXT_INTERNAL
-    csrr a0, mcause
-    csrr a1, mepc
-    store_x a1, 0( sp )                 /* Asynchronous interrupt so save unmodified exception return address. */
-    load_x sp, xISRStackTop             /* Switch to ISR stack. */
-    .endm
+   .macro portcontextSAVE_INTERRUPT_CONTEXT
+portcontextSAVE_CONTEXT_INTERNAL
+csrr a0, mcause
+csrr a1, mepc
+store_x a1, 0 ( sp )    /* Asynchronous interrupt so save unmodified exception return address. */
+load_x sp, xISRStackTop /* Switch to ISR stack. */
+   .endm
 /*-----------------------------------------------------------*/
 
-.macro portcontextRESTORE_CONTEXT
-    load_x  t1, pxCurrentTCB                /* Load pxCurrentTCB. */
-        load_x  sp, 0( t1 )                 /* Read sp from first TCB member. */
+   .macro portcontextRESTORE_CONTEXT
+load_x t1, pxCurrentTCB /* Load pxCurrentTCB. */
+load_x sp, 0 ( t1 )     /* Read sp from first TCB member. */
 
-    /* Load mepc with the address of the instruction in the task to run next. */
-    load_x t0, 0( sp )
-    csrw mepc, t0
+/* Load mepc with the address of the instruction in the task to run next. */
+load_x t0, 0 ( sp )
+csrw mepc, t0
 
-    /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
-    portasmRESTORE_ADDITIONAL_REGISTERS
+/* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
+portasmRESTORE_ADDITIONAL_REGISTERS
 
-    /* Load mstatus with the interrupt enable bits used by the task. */
-    load_x  t0, portMSTATUS_OFFSET * portWORD_SIZE( sp )
-    csrw mstatus, t0                        /* Required for MPIE bit. */
+/* Load mstatus with the interrupt enable bits used by the task. */
+load_x t0, portMSTATUS_OFFSET * portWORD_SIZE( sp )
+csrw mstatus, t0                                             /* Required for MPIE bit. */
 
-    load_x  t0, portCRITICAL_NESTING_OFFSET * portWORD_SIZE( sp )    /* Obtain xCriticalNesting value for this task from task's stack. */
-    load_x  t1, pxCriticalNesting           /* Load the address of xCriticalNesting into t1. */
-    store_x t0, 0( t1 )                     /* Restore the critical nesting value for this task. */
+load_x t0, portCRITICAL_NESTING_OFFSET * portWORD_SIZE( sp ) /* Obtain xCriticalNesting value for this task from task's stack. */
+load_x t1, pxCriticalNesting                                 /* Load the address of xCriticalNesting into t1. */
+store_x t0, 0 ( t1 )                                         /* Restore the critical nesting value for this task. */
 
-    load_x  x1, 1 * portWORD_SIZE( sp )
-    load_x  x5, 2 * portWORD_SIZE( sp )
-    load_x  x6, 3 * portWORD_SIZE( sp )
-    load_x  x7, 4 * portWORD_SIZE( sp )
-    load_x  x8, 5 * portWORD_SIZE( sp )
-    load_x  x9, 6 * portWORD_SIZE( sp )
-    load_x  x10, 7 * portWORD_SIZE( sp )
-    load_x  x11, 8 * portWORD_SIZE( sp )
-    load_x  x12, 9 * portWORD_SIZE( sp )
-    load_x  x13, 10 * portWORD_SIZE( sp )
-    load_x  x14, 11 * portWORD_SIZE( sp )
-    load_x  x15, 12 * portWORD_SIZE( sp )
+load_x x1, 1 * portWORD_SIZE( sp )
+load_x x5, 2 * portWORD_SIZE( sp )
+load_x x6, 3 * portWORD_SIZE( sp )
+load_x x7, 4 * portWORD_SIZE( sp )
+load_x x8, 5 * portWORD_SIZE( sp )
+load_x x9, 6 * portWORD_SIZE( sp )
+load_x x10, 7 * portWORD_SIZE( sp )
+load_x x11, 8 * portWORD_SIZE( sp )
+load_x x12, 9 * portWORD_SIZE( sp )
+load_x x13, 10 * portWORD_SIZE( sp )
+load_x x14, 11 * portWORD_SIZE( sp )
+load_x x15, 12 * portWORD_SIZE( sp )
 #ifndef __riscv_32e
-    load_x  x16, 13 * portWORD_SIZE( sp )
-    load_x  x17, 14 * portWORD_SIZE( sp )
-    load_x  x18, 15 * portWORD_SIZE( sp )
-    load_x  x19, 16 * portWORD_SIZE( sp )
-    load_x  x20, 17 * portWORD_SIZE( sp )
-    load_x  x21, 18 * portWORD_SIZE( sp )
-    load_x  x22, 19 * portWORD_SIZE( sp )
-    load_x  x23, 20 * portWORD_SIZE( sp )
-    load_x  x24, 21 * portWORD_SIZE( sp )
-    load_x  x25, 22 * portWORD_SIZE( sp )
-    load_x  x26, 23 * portWORD_SIZE( sp )
-    load_x  x27, 24 * portWORD_SIZE( sp )
-    load_x  x28, 25 * portWORD_SIZE( sp )
-    load_x  x29, 26 * portWORD_SIZE( sp )
-    load_x  x30, 27 * portWORD_SIZE( sp )
-    load_x  x31, 28 * portWORD_SIZE( sp )
-#endif
-    addi sp, sp, portCONTEXT_SIZE
+    load_x x16, 13 * portWORD_SIZE( sp )
+    load_x x17, 14 * portWORD_SIZE( sp )
+    load_x x18, 15 * portWORD_SIZE( sp )
+    load_x x19, 16 * portWORD_SIZE( sp )
+    load_x x20, 17 * portWORD_SIZE( sp )
+    load_x x21, 18 * portWORD_SIZE( sp )
+    load_x x22, 19 * portWORD_SIZE( sp )
+    load_x x23, 20 * portWORD_SIZE( sp )
+    load_x x24, 21 * portWORD_SIZE( sp )
+    load_x x25, 22 * portWORD_SIZE( sp )
+    load_x x26, 23 * portWORD_SIZE( sp )
+    load_x x27, 24 * portWORD_SIZE( sp )
+    load_x x28, 25 * portWORD_SIZE( sp )
+    load_x x29, 26 * portWORD_SIZE( sp )
+    load_x x30, 27 * portWORD_SIZE( sp )
+    load_x x31, 28 * portWORD_SIZE( sp )
+#endif /* ifndef __riscv_32e */
+addi sp, sp, portCONTEXT_SIZE
 
-    mret
-    .endm
+mret
+   .endm
 /*-----------------------------------------------------------*/
 
 #endif /* PORTCONTEXT_H */
diff --git a/portable/GCC/RISC-V/portmacro.h b/portable/GCC/RISC-V/portmacro.h
index 727273aca..28778c78e 100644
--- a/portable/GCC/RISC-V/portmacro.h
+++ b/portable/GCC/RISC-V/portmacro.h
@@ -48,100 +48,100 @@
 
 /* Type definitions. */
 #if __riscv_xlen == 64
-    #define portSTACK_TYPE          uint64_t
-    #define portBASE_TYPE           int64_t
-    #define portUBASE_TYPE          uint64_t
-    #define portMAX_DELAY           ( TickType_t ) 0xffffffffffffffffUL
-    #define portPOINTER_SIZE_TYPE   uint64_t
+    #define portSTACK_TYPE           uint64_t
+    #define portBASE_TYPE            int64_t
+    #define portUBASE_TYPE           uint64_t
+    #define portMAX_DELAY            ( TickType_t ) 0xffffffffffffffffUL
+    #define portPOINTER_SIZE_TYPE    uint64_t
 #elif __riscv_xlen == 32
-    #define portSTACK_TYPE          uint32_t
-    #define portBASE_TYPE           int32_t
-    #define portUBASE_TYPE          uint32_t
-    #define portMAX_DELAY           ( TickType_t ) 0xffffffffUL
-#else
-    #error Assembler did not define __riscv_xlen
-#endif
+    #define portSTACK_TYPE           uint32_t
+    #define portBASE_TYPE            int32_t
+    #define portUBASE_TYPE           uint32_t
+    #define portMAX_DELAY            ( TickType_t ) 0xffffffffUL
+#else /* if __riscv_xlen == 64 */
+    #error "Assembler did not define __riscv_xlen"
+#endif /* if __riscv_xlen == 64 */
 
-typedef portSTACK_TYPE StackType_t;
-typedef portBASE_TYPE BaseType_t;
-typedef portUBASE_TYPE UBaseType_t;
-typedef portUBASE_TYPE TickType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef portBASE_TYPE    BaseType_t;
+typedef portUBASE_TYPE   UBaseType_t;
+typedef portUBASE_TYPE   TickType_t;
 
 /* Legacy type definitions. */
-#define portCHAR            char
-#define portFLOAT           float
-#define portDOUBLE          double
-#define portLONG            long
-#define portSHORT           short
+#define portCHAR                   char
+#define portFLOAT                  float
+#define portDOUBLE                 double
+#define portLONG                   long
+#define portSHORT                  short
 
 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
  * not need to be guarded with a critical section. */
-#define portTICK_TYPE_IS_ATOMIC 1
+#define portTICK_TYPE_IS_ATOMIC    1
 /*-----------------------------------------------------------*/
 
 /* Architecture specifics. */
-#define portSTACK_GROWTH            ( -1 )
-#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portSTACK_GROWTH          ( -1 )
+#define portTICK_PERIOD_MS        ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
 #ifdef __riscv_32e
-    #define portBYTE_ALIGNMENT      8   /* RV32E uses RISC-V EABI with reduced stack alignment requirements */
+    #define portBYTE_ALIGNMENT    8     /* RV32E uses RISC-V EABI with reduced stack alignment requirements */
 #else
-    #define portBYTE_ALIGNMENT      16
+    #define portBYTE_ALIGNMENT    16
 #endif
 /*-----------------------------------------------------------*/
 
 /* Scheduler utilities. */
 extern void vTaskSwitchContext( void );
-#define portYIELD() __asm volatile( "ecall" );
-#define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) vTaskSwitchContext(); } while( 0 )
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portYIELD()                                 __asm volatile ( "ecall" );
+#define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired ) vTaskSwitchContext( ); } while( 0 )
+#define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
 /* Critical section management. */
-#define portCRITICAL_NESTING_IN_TCB                             0
+#define portCRITICAL_NESTING_IN_TCB    0
 
-#define portSET_INTERRUPT_MASK_FROM_ISR()                       0
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue
+#define portSET_INTERRUPT_MASK_FROM_ISR()                          0
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue )    ( void ) uxSavedStatusValue
 
-#define portDISABLE_INTERRUPTS()    __asm volatile( "csrc mstatus, 8" )
-#define portENABLE_INTERRUPTS()     __asm volatile( "csrs mstatus, 8" )
+#define portDISABLE_INTERRUPTS()                                   __asm volatile ( "csrc mstatus, 8" )
+#define portENABLE_INTERRUPTS()                                    __asm volatile ( "csrs mstatus, 8" )
 
 extern size_t xCriticalNesting;
-#define portENTER_CRITICAL()            \
-{                                       \
-    portDISABLE_INTERRUPTS();           \
-    xCriticalNesting++;                 \
-}
+#define portENTER_CRITICAL()      \
+    {                             \
+        portDISABLE_INTERRUPTS(); \
+        xCriticalNesting++;       \
+    }
 
-#define portEXIT_CRITICAL()             \
-{                                       \
-    xCriticalNesting--;                 \
-    if( xCriticalNesting == 0 )         \
-    {                                   \
-        portENABLE_INTERRUPTS();        \
-    }                                   \
-}
+#define portEXIT_CRITICAL()          \
+    {                                \
+        xCriticalNesting--;          \
+        if( xCriticalNesting == 0 )  \
+        {                            \
+            portENABLE_INTERRUPTS(); \
+        }                            \
+    }
 
 /*-----------------------------------------------------------*/
 
 /* Architecture specific optimisations. */
 #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-    #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+    #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
 #endif
 
-#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
 
-    /* Check the configuration. */
-    #if( configMAX_PRIORITIES > 32 )
-        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+/* Check the configuration. */
+    #if ( configMAX_PRIORITIES > 32 )
+        #error "configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice."
     #endif
 
-    /* Store/clear the ready priorities in a bit map. */
-    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+/* Store/clear the ready priorities in a bit map. */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 
-    /*-----------------------------------------------------------*/
+/*-----------------------------------------------------------*/
 
-    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - __builtin_clz( uxReadyPriorities ) )
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - __builtin_clz( uxReadyPriorities ) )
 
 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 
@@ -151,19 +151,19 @@ extern size_t xCriticalNesting;
 /* Task function macros as described on the FreeRTOS.org WEB site. These are
  * not necessary for to use this port.  They are defined so the common demo
  * files (which build with all the ports) will build. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
 /*-----------------------------------------------------------*/
 
-#define portNOP()    __asm volatile( " nop " )
-#define portINLINE   __inline
+#define portNOP()    __asm volatile ( " nop " )
+#define portINLINE              __inline
 
 #ifndef portFORCE_INLINE
-    #define portFORCE_INLINE inline __attribute__(( always_inline))
+    #define portFORCE_INLINE    inline __attribute__( ( always_inline ) )
 #endif
 
-#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+#define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
 /*-----------------------------------------------------------*/
 
 /* configCLINT_BASE_ADDRESS is a legacy definition that was replaced by the
@@ -171,20 +171,22 @@ extern size_t xCriticalNesting;
  * backward compatibility derive the newer definitions from the old if the old
  * definition is found. */
 #if defined( configCLINT_BASE_ADDRESS ) && !defined( configMTIME_BASE_ADDRESS ) && ( configCLINT_BASE_ADDRESS == 0 )
-    /* Legacy case where configCLINT_BASE_ADDRESS was defined as 0 to indicate
-     * there was no CLINT.  Equivalent now is to set the MTIME and MTIMECMP
-     * addresses to 0. */
-    #define configMTIME_BASE_ADDRESS     ( 0 )
-    #define configMTIMECMP_BASE_ADDRESS ( 0 )
+
+/* Legacy case where configCLINT_BASE_ADDRESS was defined as 0 to indicate
+ * there was no CLINT.  Equivalent now is to set the MTIME and MTIMECMP
+ * addresses to 0. */
+    #define configMTIME_BASE_ADDRESS       ( 0 )
+    #define configMTIMECMP_BASE_ADDRESS    ( 0 )
 #elif defined( configCLINT_BASE_ADDRESS ) && !defined( configMTIME_BASE_ADDRESS )
-    /* Legacy case where configCLINT_BASE_ADDRESS was set to the base address of
-     * the CLINT.  Equivalent now is to derive the MTIME and MTIMECMP addresses
-     * from the CLINT address. */
-    #define configMTIME_BASE_ADDRESS     ( ( configCLINT_BASE_ADDRESS ) + 0xBFF8UL )
-    #define configMTIMECMP_BASE_ADDRESS ( ( configCLINT_BASE_ADDRESS ) + 0x4000UL )
+
+/* Legacy case where configCLINT_BASE_ADDRESS was set to the base address of
+ * the CLINT.  Equivalent now is to derive the MTIME and MTIMECMP addresses
+ * from the CLINT address. */
+    #define configMTIME_BASE_ADDRESS       ( ( configCLINT_BASE_ADDRESS ) + 0xBFF8UL )
+    #define configMTIMECMP_BASE_ADDRESS    ( ( configCLINT_BASE_ADDRESS ) + 0x4000UL )
 #elif !defined( configMTIME_BASE_ADDRESS ) || !defined( configMTIMECMP_BASE_ADDRESS )
-    #error configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h.  Set them to zero if there is no MTIME (machine time) clock.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
-#endif
+    #error "configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h.  Set them to zero if there is no MTIME (machine time) clock.  See www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html"
+#endif /* if defined( configCLINT_BASE_ADDRESS ) && !defined( configMTIME_BASE_ADDRESS ) && ( configCLINT_BASE_ADDRESS == 0 ) */
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/GCC/RL78/isr_support.h b/portable/GCC/RL78/isr_support.h
index 348af1d96..5f8e568bc 100644
--- a/portable/GCC/RL78/isr_support.h
+++ b/portable/GCC/RL78/isr_support.h
@@ -27,8 +27,8 @@
  */
 
 /* Variables used by scheduler */
-    .extern    _pxCurrentTCB
-    .extern    _usCriticalNesting
+.extern _pxCurrentTCB
+   .extern _usCriticalNesting
 
 /*
  * portSAVE_CONTEXT MACRO
@@ -36,47 +36,47 @@
  * memory mode) registers the usCriticalNesting Value and the Stack Pointer
  * of the active Task onto the task stack
  */
-    .macro portSAVE_CONTEXT
+   .macro portSAVE_CONTEXT
 
-    SEL     RB0
+SEL RB0
 
-    /* Save AX Register to stack. */
-    PUSH    AX
-    PUSH    HL
-    /* Save CS register. */
-    MOV     A, CS
-    XCH     A, X
-    /* Save ES register. */
-    MOV     A, ES
-    PUSH    AX
-    /* Save the remaining general purpose registers from bank 0. */
-    PUSH    DE
-    PUSH    BC
-    /* Save the other register banks - only necessary in the GCC port. */
-    SEL     RB1
-    PUSH    AX
-    PUSH    BC
-    PUSH    DE
-    PUSH    HL
-    SEL     RB2
-    PUSH    AX
-    PUSH    BC
-    PUSH    DE
-    PUSH    HL
-    /* Registers in bank 3 are for ISR use only so don't need saving. */
-    SEL     RB0
-    /* Save the usCriticalNesting value. */
-    MOVW    AX, !_usCriticalNesting
-    PUSH    AX
-    /* Save the Stack pointer. */
-    MOVW    AX, !_pxCurrentTCB
-    MOVW    HL, AX
-    MOVW    AX, SP
-    MOVW    [HL], AX
-    /* Switch stack pointers. */
-    movw sp,#_stack /* Set stack pointer */
+/* Save AX Register to stack. */
+PUSH AX
+PUSH HL
+/* Save CS register. */
+MOV A, CS
+XCH A, X
+/* Save ES register. */
+MOV A, ES
+PUSH AX
+/* Save the remaining general purpose registers from bank 0. */
+PUSH DE
+PUSH BC
+/* Save the other register banks - only necessary in the GCC port. */
+SEL RB1
+PUSH AX
+PUSH BC
+PUSH DE
+PUSH HL
+SEL RB2
+PUSH AX
+PUSH BC
+PUSH DE
+PUSH HL
+/* Registers in bank 3 are for ISR use only so don't need saving. */
+SEL RB0
+/* Save the usCriticalNesting value. */
+MOVW AX, !_usCriticalNesting
+PUSH AX
+/* Save the Stack pointer. */
+MOVW AX, !_pxCurrentTCB
+MOVW HL, AX
+MOVW AX, SP
+MOVW[ HL ], AX
+/* Switch stack pointers. */
+movw sp, # _stack /* Set stack pointer */
 
-    .endm
+   .endm
 
 
 /*
@@ -85,42 +85,43 @@
  * general purpose registers and the CS and ES (only in far memory mode)
  * of the selected task from the task stack
  */
-.macro portRESTORE_CONTEXT MACRO
-    SEL     RB0
-    /* Restore the Stack pointer. */
-    MOVW    AX, !_pxCurrentTCB
-    MOVW    HL, AX
-    MOVW    AX, [HL]
-    MOVW    SP, AX
-    /* Restore usCriticalNesting value. */
-    POP     AX
-    MOVW    !_usCriticalNesting, AX
-    /* Restore the alternative register banks - only necessary in the GCC
-    port.  Register bank 3 is dedicated for interrupts use so is not saved or
-    restored. */
-    SEL     RB2
-    POP     HL
-    POP     DE
-    POP     BC
-    POP     AX
-    SEL     RB1
-    POP     HL
-    POP     DE
-    POP     BC
-    POP     AX
-    SEL     RB0
-    /* Restore the necessary general purpose registers. */
-    POP     BC
-    POP     DE
-    /* Restore the ES register. */
-    POP     AX
-    MOV     ES, A
-    /* Restore the CS register. */
-    XCH     A, X
-    MOV     CS, A
-    /* Restore general purpose register HL. */
-    POP     HL
-    /* Restore AX. */
-    POP     AX
+   .macro portRESTORE_CONTEXT MACRO
+SEL RB0
+/* Restore the Stack pointer. */
+MOVW AX, !_pxCurrentTCB
+MOVW HL, AX
+MOVW AX, [ HL ]
+MOVW SP, AX
+/* Restore usCriticalNesting value. */
+POP AX
+MOVW    !_usCriticalNesting, AX
 
-    .endm
+/* Restore the alternative register banks - only necessary in the GCC
+ * port.  Register bank 3 is dedicated for interrupts use so is not saved or
+ * restored. */
+SEL RB2
+POP HL
+POP DE
+POP BC
+POP AX
+SEL RB1
+POP HL
+POP DE
+POP BC
+POP AX
+SEL RB0
+/* Restore the necessary general purpose registers. */
+POP BC
+POP DE
+/* Restore the ES register. */
+POP AX
+MOV ES, A
+/* Restore the CS register. */
+XCH A, X
+MOV CS, A
+/* Restore general purpose register HL. */
+POP HL
+/* Restore AX. */
+POP AX
+
+   .endm
diff --git a/portable/GCC/RL78/port.c b/portable/GCC/RL78/port.c
index 5525b1014..00ff398c8 100644
--- a/portable/GCC/RL78/port.c
+++ b/portable/GCC/RL78/port.c
@@ -31,8 +31,8 @@
 #include "task.h"
 
 /* The critical nesting value is initialised to a non zero value to ensure
-interrupts don't accidentally become enabled before the scheduler is started. */
-#define portINITIAL_CRITICAL_NESTING  ( ( uint16_t ) 10 )
+ * interrupts don't accidentally become enabled before the scheduler is started. */
+#define portINITIAL_CRITICAL_NESTING    ( ( uint16_t ) 10 )
 
 /* Initial PSW value allocated to a newly created task.
  *   11000110
@@ -45,16 +45,16 @@ interrupts don't accidentally become enabled before the scheduler is started. */
  *   |--------------------- Zero Flag set
  *   ---------------------- Global Interrupt Flag set (enabled)
  */
-#define portPSW       ( 0xc6UL )
+#define portPSW                         ( 0xc6UL )
 
 /* Each task maintains a count of the critical section nesting depth.  Each time
-a critical section is entered the count is incremented.  Each time a critical
-section is exited the count is decremented - with interrupts only being
-re-enabled if the count is zero.
-
-usCriticalNesting will get set to zero when the scheduler starts, but must
-not be initialised to zero as that could cause problems during the startup
-sequence. */
+ * a critical section is entered the count is incremented.  Each time a critical
+ * section is exited the count is decremented - with interrupts only being
+ * re-enabled if the count is zero.
+ *
+ * usCriticalNesting will get set to zero when the scheduler starts, but must
+ * not be initialised to zero as that could cause problems during the startup
+ * sequence. */
 volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;
 
 /*-----------------------------------------------------------*/
@@ -62,7 +62,7 @@ volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;
 /*
  * Sets up the periodic ISR used for the RTOS tick.
  */
-__attribute__((weak)) void vApplicationSetupTimerInterrupt( void );
+__attribute__( ( weak ) ) void vApplicationSetupTimerInterrupt( void );
 
 /*
  * Starts the scheduler by loading the context of the first task to run.
@@ -78,30 +78,32 @@ extern void vPortStartFirstTask( void );
  *
  * See the header file portable.h.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
-uint32_t *pulLocal;
+    uint32_t * pulLocal;
 
     /* Stack type and pointers to the stack type are both 2 bytes. */
 
     /* Parameters are passed in on the stack, and written using a 32bit value
-    hence a space is left for the second two bytes. */
+     * hence a space is left for the second two bytes. */
     pxTopOfStack--;
 
     /* Write in the parameter value. */
-    pulLocal =  ( uint32_t * ) pxTopOfStack;
+    pulLocal = ( uint32_t * ) pxTopOfStack;
     *pulLocal = ( StackType_t ) pvParameters;
     pxTopOfStack--;
 
     /* The return address, leaving space for the first two bytes of the
-    32-bit value. */
+     * 32-bit value. */
     pxTopOfStack--;
     pulLocal = ( uint32_t * ) pxTopOfStack;
     *pulLocal = ( uint32_t ) 0;
     pxTopOfStack--;
 
     /* The start address / PSW value is also written in as a 32bit value,
-    so leave a space for the second two bytes. */
+     * so leave a space for the second two bytes. */
     pxTopOfStack--;
 
     /* Task function start address combined with the PSW. */
@@ -122,16 +124,16 @@ uint32_t *pulLocal;
     pxTopOfStack--;
 
     /* The remaining general purpose registers bank 0 (DE and BC) and the other
-    two register banks...register bank 3 is dedicated for use by interrupts so
-    is not saved as part of the task context. */
+     * two register banks...register bank 3 is dedicated for use by interrupts so
+     * is not saved as part of the task context. */
     pxTopOfStack -= 10;
 
     /* Finally the critical section nesting count is set to zero when the task
-    first starts. */
+     * first starts. */
     *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;
 
-    /* Return a pointer to the top of the stack that has beene generated so it
-    can be stored in the task control block for the task. */
+    /* Return a pointer to the top of the stack that has been generated so it
+     * can be stored in the task control block for the task. */
     return pxTopOfStack;
 }
 /*-----------------------------------------------------------*/
@@ -139,7 +141,7 @@ uint32_t *pulLocal;
 BaseType_t xPortStartScheduler( void )
 {
     /* Setup the hardware to generate the tick.  Interrupts are disabled when
-    this function is called. */
+     * this function is called. */
     vApplicationSetupTimerInterrupt();
 
     /* Restore the context of the first task that is going to run. */
@@ -156,10 +158,10 @@ void vPortEndScheduler( void )
 }
 /*-----------------------------------------------------------*/
 
-__attribute__((weak)) void vApplicationSetupTimerInterrupt( void )
+__attribute__( ( weak ) ) void vApplicationSetupTimerInterrupt( void )
 {
-const uint16_t usClockHz = 15000UL; /* Internal clock. */
-const uint16_t usCompareMatch = ( usClockHz / configTICK_RATE_HZ ) + 1UL;
+    const uint16_t usClockHz = 15000UL; /* Internal clock. */
+    const uint16_t usCompareMatch = ( usClockHz / configTICK_RATE_HZ ) + 1UL;
 
     /* Use the internal 15K clock. */
     OSMC = ( unsigned char ) 0x16;
@@ -184,7 +186,7 @@ const uint16_t usCompareMatch = ( usClockHz / configTICK_RATE_HZ ) + 1UL;
         /* Enable INTIT interrupt. */
         ITMK = ( unsigned char ) 0;
     }
-    #endif
+    #endif /* ifdef RTCEN */
 
     #ifdef TMKAEN
     {
@@ -206,6 +208,6 @@ const uint16_t usCompareMatch = ( usClockHz / configTICK_RATE_HZ ) + 1UL;
         /* Enable INTIT interrupt. */
         TMKAMK = ( unsigned char ) 0;
     }
-    #endif
+    #endif /* ifdef TMKAEN */
 }
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/RL78/portmacro.h b/portable/GCC/RL78/portmacro.h
index 349402008..eac8b1086 100644
--- a/portable/GCC/RL78/portmacro.h
+++ b/portable/GCC/RL78/portmacro.h
@@ -41,83 +41,83 @@
 
 /* Type definitions. */
 
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint16_t
-#define portBASE_TYPE   short
-#define portPOINTER_SIZE_TYPE uint16_t
+#define portCHAR                 char
+#define portFLOAT                float
+#define portDOUBLE               double
+#define portLONG                 long
+#define portSHORT                short
+#define portSTACK_TYPE           uint16_t
+#define portBASE_TYPE            short
+#define portPOINTER_SIZE_TYPE    uint16_t
 
-typedef portSTACK_TYPE StackType_t;
-typedef short BaseType_t;
-typedef unsigned short UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef short            BaseType_t;
+typedef unsigned short   UBaseType_t;
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY ( TickType_t )    ( 0xFFFFFFFFUL )
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) ( 0xFFFFFFFFUL )
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
 /*-----------------------------------------------------------*/
 
 /* Interrupt control macros. */
-#define portDISABLE_INTERRUPTS() __asm volatile ( "DI" )
-#define portENABLE_INTERRUPTS()  __asm volatile ( "EI" )
+#define portDISABLE_INTERRUPTS()    __asm volatile ( "DI" )
+#define portENABLE_INTERRUPTS()     __asm volatile ( "EI" )
 /*-----------------------------------------------------------*/
 
 /* Critical section control macros. */
-#define portNO_CRITICAL_SECTION_NESTING     ( ( unsigned short ) 0 )
+#define portNO_CRITICAL_SECTION_NESTING    ( ( unsigned short ) 0 )
 
-#define portENTER_CRITICAL()                                                    \
-{                                                                               \
-extern volatile uint16_t usCriticalNesting;                                     \
-                                                                                \
-    portDISABLE_INTERRUPTS();                                                   \
-                                                                                \
-    /* Now interrupts are disabled ulCriticalNesting can be accessed */         \
-    /* directly.  Increment ulCriticalNesting to keep a count of how many */    \
-    /* times portENTER_CRITICAL() has been called. */                           \
-    usCriticalNesting++;                                                        \
-}
+#define portENTER_CRITICAL()                                                      \
+    {                                                                             \
+        extern volatile uint16_t usCriticalNesting;                               \
+                                                                                  \
+        portDISABLE_INTERRUPTS();                                                 \
+                                                                                  \
+        /* Now that interrupts are disabled, ulCriticalNesting can be accessed */ \
+        /* directly.  Increment ulCriticalNesting to keep a count of how many */  \
+        /* times portENTER_CRITICAL() has been called. */                         \
+        usCriticalNesting++;                                                      \
+    }
 
-#define portEXIT_CRITICAL()                                                     \
-{                                                                               \
-extern volatile uint16_t usCriticalNesting;                                     \
-                                                                                \
-    if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING )                   \
-    {                                                                           \
-        /* Decrement the nesting count as we are leaving a critical section. */ \
-        usCriticalNesting--;                                                    \
-                                                                                \
-        /* If the nesting level has reached zero then interrupts should be */   \
-        /* re-enabled. */                                                       \
-        if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING )              \
-        {                                                                       \
-            portENABLE_INTERRUPTS();                                            \
-        }                                                                       \
-    }                                                                           \
-}
+#define portEXIT_CRITICAL()                                                         \
+    {                                                                               \
+        extern volatile uint16_t usCriticalNesting;                                 \
+                                                                                    \
+        if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING )                   \
+        {                                                                           \
+            /* Decrement the nesting count as we are leaving a critical section. */ \
+            usCriticalNesting--;                                                    \
+                                                                                    \
+            /* If the nesting level has reached zero then interrupts should be */   \
+            /* re-enabled. */                                                       \
+            if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING )              \
+            {                                                                       \
+                portENABLE_INTERRUPTS();                                            \
+            }                                                                       \
+        }                                                                           \
+    }
 /*-----------------------------------------------------------*/
 
 /* Task utilities. */
-#define portYIELD()     __asm volatile ( "BRK" )
-#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) do { if( xHigherPriorityTaskWoken ) vTaskSwitchContext(); } while( 0 )
-#define portNOP()   __asm volatile ( "NOP" )
+#define portYIELD()                                       __asm volatile ( "BRK" )
+#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken )    do { if( xHigherPriorityTaskWoken ) vTaskSwitchContext( ); } while( 0 )
+#define portNOP()                                         __asm volatile ( "NOP" )
 /*-----------------------------------------------------------*/
 
-/* Hardwware specifics. */
-#define portBYTE_ALIGNMENT  2
-#define portSTACK_GROWTH    ( -1 )
-#define portTICK_PERIOD_MS  ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT    2
+#define portSTACK_GROWTH      ( -1 )
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
 #endif /* PORTMACRO_H */
diff --git a/portable/GCC/RX100/port.c b/portable/GCC/RX100/port.c
index fc1958658..e7f72bde6 100644
--- a/portable/GCC/RX100/port.c
+++ b/portable/GCC/RX100/port.c
@@ -27,8 +27,8 @@
  */
 
 /*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the SH2A port.
- *----------------------------------------------------------*/
+* Implementation of functions defined in portable.h for the SH2A port.
+*----------------------------------------------------------*/
 
 /* Standard C includes. */
 #include "limits.h"
@@ -53,36 +53,36 @@
 /*-----------------------------------------------------------*/
 
 /* Tasks should start with interrupts enabled and in Supervisor mode, therefore
-PSW is set with U and I set, and PM and IPL clear. */
-#define portINITIAL_PSW  ( ( StackType_t ) 0x00030000 )
+ * PSW is set with U and I set, and PM and IPL clear. */
+#define portINITIAL_PSW    ( ( StackType_t ) 0x00030000 )
 
 /* The peripheral clock is divided by this value before being supplying the
-CMT. */
+ * CMT. */
 #if ( configUSE_TICKLESS_IDLE == 0 )
     /* If tickless idle is not used then the divisor can be fixed. */
-    #define portCLOCK_DIVISOR   8UL
+    #define portCLOCK_DIVISOR    8UL
 #elif ( configPERIPHERAL_CLOCK_HZ >= 12000000 )
-    #define portCLOCK_DIVISOR   512UL
+    #define portCLOCK_DIVISOR    512UL
 #elif ( configPERIPHERAL_CLOCK_HZ >= 6000000 )
-    #define portCLOCK_DIVISOR   128UL
+    #define portCLOCK_DIVISOR    128UL
 #elif ( configPERIPHERAL_CLOCK_HZ >= 1000000 )
-    #define portCLOCK_DIVISOR   32UL
+    #define portCLOCK_DIVISOR    32UL
 #else
-    #define portCLOCK_DIVISOR   8UL
+    #define portCLOCK_DIVISOR    8UL
 #endif
 
 /* These macros allow a critical section to be added around the call to
-xTaskIncrementTick(), which is only ever called from interrupts at the kernel
-priority - ie a known priority.  Therefore these local macros are a slight
-optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,
-which would require the old IPL to be read first and stored in a local variable. */
-#define portDISABLE_INTERRUPTS_FROM_KERNEL_ISR()    __asm volatile ( "MVTIPL    %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
-#define portENABLE_INTERRUPTS_FROM_KERNEL_ISR()     __asm volatile ( "MVTIPL    %0" ::"i"(configKERNEL_INTERRUPT_PRIORITY) )
+ * xTaskIncrementTick(), which is only ever called from interrupts at the kernel
+ * priority - ie a known priority.  Therefore these local macros are a slight
+ * optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,
+ * which would require the old IPL to be read first and stored in a local variable. */
+#define portDISABLE_INTERRUPTS_FROM_KERNEL_ISR()    __asm volatile ( "MVTIPL    %0" ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+#define portENABLE_INTERRUPTS_FROM_KERNEL_ISR()     __asm volatile ( "MVTIPL    %0" ::"i" ( configKERNEL_INTERRUPT_PRIORITY ) )
 
 /* Keys required to lock and unlock access to certain system registers
-respectively. */
-#define portUNLOCK_KEY      0xA50B
-#define portLOCK_KEY        0xA500
+ * respectively. */
+#define portUNLOCK_KEY    0xA50B
+#define portLOCK_KEY      0xA500
 
 /*-----------------------------------------------------------*/
 
@@ -90,7 +90,7 @@ respectively. */
  * Function to start the first task executing - written in asm code as direct
  * access to registers is required.
  */
-static void prvStartFirstTask( void ) __attribute__((naked));
+static void prvStartFirstTask( void ) __attribute__( ( naked ) );
 
 /*
  * Software interrupt handler.  Performs the actual context switch (saving and
@@ -131,9 +131,10 @@ static void prvStartFirstTask( void ) __attribute__((naked));
  */
 static void prvSetupTimerInterrupt( void );
 #ifndef configSETUP_TICK_INTERRUPT
-    /* The user has not provided their own tick interrupt configuration so use
-    the definition in this file (which uses the interval timer). */
-    #define configSETUP_TICK_INTERRUPT() prvSetupTimerInterrupt()
+
+/* The user has not provided their own tick interrupt configuration so use
+ * the definition in this file (which uses the interval timer). */
+    #define configSETUP_TICK_INTERRUPT()    prvSetupTimerInterrupt()
 #endif /* configSETUP_TICK_INTERRUPT */
 
 /*
@@ -148,40 +149,42 @@ static void prvSetupTimerInterrupt( void );
 /*-----------------------------------------------------------*/
 
 /* Used in the context save and restore code. */
-extern void *pxCurrentTCB;
+extern void * pxCurrentTCB;
 
 /* Calculate how many clock increments make up a single tick period. */
 static const uint32_t ulMatchValueForOneTick = ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
 
 #if configUSE_TICKLESS_IDLE == 1
 
-    /* Holds the maximum number of ticks that can be suppressed - which is
-    basically how far into the future an interrupt can be generated. Set
-    during initialisation.  This is the maximum possible value that the
-    compare match register can hold divided by ulMatchValueForOneTick. */
+/* Holds the maximum number of ticks that can be suppressed - which is
+ * basically how far into the future an interrupt can be generated. Set
+ * during initialisation.  This is the maximum possible value that the
+ * compare match register can hold divided by ulMatchValueForOneTick. */
     static const TickType_t xMaximumPossibleSuppressedTicks = USHRT_MAX / ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
 
-    /* Flag set from the tick interrupt to allow the sleep processing to know if
-    sleep mode was exited because of a tick interrupt, or an interrupt
-    generated by something else. */
+/* Flag set from the tick interrupt to allow the sleep processing to know if
+ * sleep mode was exited because of a tick interrupt, or an interrupt
+ * generated by something else. */
     static volatile uint32_t ulTickFlag = pdFALSE;
 
-    /* The CMT counter is stopped temporarily each time it is re-programmed.
-    The following constant offsets the CMT counter match value by the number of
-    CMT counts that would typically be missed while the counter was stopped to
-    compensate for the lost time.  The large difference between the divided CMT
-    clock and the CPU clock means it is likely ulStoppedTimerCompensation will
-    equal zero - and be optimised away. */
+/* The CMT counter is stopped temporarily each time it is re-programmed.
+ * The following constant offsets the CMT counter match value by the number of
+ * CMT counts that would typically be missed while the counter was stopped to
+ * compensate for the lost time.  The large difference between the divided CMT
+ * clock and the CPU clock means it is likely ulStoppedTimerCompensation will
+ * equal zero - and be optimised away. */
     static const uint32_t ulStoppedTimerCompensation = 100UL / ( configCPU_CLOCK_HZ / ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) );
 
-#endif
+#endif /* if configUSE_TICKLESS_IDLE == 1 */
 
 /*-----------------------------------------------------------*/
 
 /*
  * See header file for description.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
     /* Offset to end up on 8 byte boundary. */
     pxTopOfStack--;
@@ -196,8 +199,8 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
     *pxTopOfStack = ( StackType_t ) pxCode;
 
     /* When debugging it can be useful if every register is set to a known
-    value.  Otherwise code space can be saved by just setting the registers
-    that need to be set. */
+     * value.  Otherwise code space can be saved by just setting the registers
+     * that need to be set. */
     #ifdef USE_FULL_REGISTER_INITIALISATION
     {
         pxTopOfStack--;
@@ -230,19 +233,19 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
         *pxTopOfStack = 0x22222222;
         pxTopOfStack--;
     }
-    #else
+    #else /* ifdef USE_FULL_REGISTER_INITIALISATION */
     {
         /* Leave space for the registers that will get popped from the stack
-        when the task first starts executing. */
+         * when the task first starts executing. */
         pxTopOfStack -= 15;
     }
-    #endif
+    #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */
 
     *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
     pxTopOfStack--;
-    *pxTopOfStack = 0x12345678; /* Accumulator. */
+    *pxTopOfStack = 0x12345678;                   /* Accumulator. */
     pxTopOfStack--;
-    *pxTopOfStack = 0x87654321; /* Accumulator. */
+    *pxTopOfStack = 0x87654321;                   /* Accumulator. */
 
     return pxTopOfStack;
 }
@@ -254,10 +257,10 @@ BaseType_t xPortStartScheduler( void )
     if( pxCurrentTCB != NULL )
     {
         /* Call an application function to set up the timer that will generate
-        the tick interrupt.  This way the application can decide which
-        peripheral to use.  If tickless mode is used then the default
-        implementation defined in this file (which uses CMT0) should not be
-        overridden. */
+         * the tick interrupt.  This way the application can decide which
+         * peripheral to use.  If tickless mode is used then the default
+         * implementation defined in this file (which uses CMT0) should not be
+         * overridden. */
         configSETUP_TICK_INTERRUPT();
 
         /* Enable the software interrupt. */
@@ -274,11 +277,11 @@ BaseType_t xPortStartScheduler( void )
     }
 
     /* Execution should not reach here as the tasks are now running!
-    prvSetupTimerInterrupt() is called here to prevent the compiler outputting
-    a warning about a statically declared function not being referenced in the
-    case that the application writer has provided their own tick interrupt
-    configuration routine (and defined configSETUP_TICK_INTERRUPT() such that
-    their own routine will be called in place of prvSetupTimerInterrupt()). */
+     * prvSetupTimerInterrupt() is called here to prevent the compiler outputting
+     * a warning about a statically declared function not being referenced in the
+     * case that the application writer has provided their own tick interrupt
+     * configuration routine (and defined configSETUP_TICK_INTERRUPT() such that
+     * their own routine will be called in place of prvSetupTimerInterrupt()). */
     prvSetupTimerInterrupt();
 
     /* Should not get here. */
@@ -289,7 +292,7 @@ BaseType_t xPortStartScheduler( void )
 void vPortEndScheduler( void )
 {
     /* Not implemented in ports where there is nothing to return to.
-    Artificially force an assert. */
+     * Artificially force an assert. */
     configASSERT( pxCurrentTCB == NULL );
 }
 /*-----------------------------------------------------------*/
@@ -298,19 +301,22 @@ static void prvStartFirstTask( void )
 {
     __asm volatile
     (
+
         /* When starting the scheduler there is nothing that needs moving to the
-        interrupt stack because the function is not called from an interrupt.
-        Just ensure the current stack is the user stack. */
+         * interrupt stack because the function is not called from an interrupt.
+         * Just ensure the current stack is the user stack. */
         "SETPSW     U                       \n" \
 
+
         /* Obtain the location of the stack associated with which ever task
-        pxCurrentTCB is currently pointing to. */
+         * pxCurrentTCB is currently pointing to. */
         "MOV.L      #_pxCurrentTCB, R15     \n" \
         "MOV.L      [R15], R15              \n" \
         "MOV.L      [R15], R0               \n" \
 
+
         /* Restore the registers from the stack of the task pointed to by
-        pxCurrentTCB. */
+         * pxCurrentTCB. */
         "POP        R15                     \n" \
 
         /* Accumulator low 32 bits. */
@@ -338,10 +344,11 @@ void vPortSoftwareInterruptISR( void )
         /* Re-enable interrupts. */
         "SETPSW     I                           \n" \
 
-        /* Move the data that was automatically pushed onto the interrupt stack when
-        the interrupt occurred from the interrupt stack to the user stack.
 
-        R15 is saved before it is clobbered. */
+        /* Move the data that was automatically pushed onto the interrupt stack when
+         * the interrupt occurred from the interrupt stack to the user stack.
+         *
+         * R15 is saved before it is clobbered. */
         "PUSH.L     R15                         \n" \
 
         /* Read the user stack pointer. */
@@ -381,8 +388,9 @@ void vPortSoftwareInterruptISR( void )
         "MOV.L      [ R15 ], R15                \n" \
         "MOV.L      R0, [ R15 ]                 \n" \
 
+
         /* Ensure the interrupt mask is set to the syscall priority while the kernel
-        structures are being accessed. */
+         * structures are being accessed. */
         "MVTIPL     %0                          \n" \
 
         /* Select the next task to run. */
@@ -391,14 +399,16 @@ void vPortSoftwareInterruptISR( void )
         /* Reset the interrupt mask as no more data structure access is required. */
         "MVTIPL     %1                          \n" \
 
+
         /* Load the stack pointer of the task that is now selected as the Running
-        state task from its TCB. */
+         * state task from its TCB. */
         "MOV.L      #_pxCurrentTCB,R15          \n" \
         "MOV.L      [ R15 ], R15                \n" \
         "MOV.L      [ R15 ], R0                 \n" \
 
+
         /* Restore the context of the new task.  The PSW (Program Status Word) and
-        PC will be popped by the RTE instruction. */
+         * PC will be popped by the RTE instruction. */
         "POP        R15                         \n" \
         "MVTACLO    R15                         \n" \
         "POP        R15                         \n" \
@@ -407,7 +417,7 @@ void vPortSoftwareInterruptISR( void )
         "RTE                                    \n" \
         "NOP                                    \n" \
         "NOP                                      "
-        :: "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY), "i"(configKERNEL_INTERRUPT_PRIORITY)
+        ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ), "i" ( configKERNEL_INTERRUPT_PRIORITY )
     );
 }
 /*-----------------------------------------------------------*/
@@ -415,10 +425,10 @@ void vPortSoftwareInterruptISR( void )
 void vPortTickISR( void )
 {
     /* Re-enabled interrupts. */
-    __asm volatile( "SETPSW I" );
+    __asm volatile ( "SETPSW I" );
 
     /* Increment the tick, and perform any processing the new tick value
-    necessitates.  Ensure IPL is at the max syscall value first. */
+     * necessitates.  Ensure IPL is at the max syscall value first. */
     portDISABLE_INTERRUPTS_FROM_KERNEL_ISR();
     {
         if( xTaskIncrementTick() != pdFALSE )
@@ -434,7 +444,7 @@ void vPortTickISR( void )
         ulTickFlag = pdTRUE;
 
         /* If this is the first tick since exiting tickless mode then the CMT
-        compare match value needs resetting. */
+         * compare match value needs resetting. */
         CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;
     }
     #endif
@@ -467,7 +477,7 @@ void vPortSetIPL( uint32_t ulNewIPL )
         "MVTC   R5, PSW         \n" \
         "POP    R5              \n" \
         "RTS                      "
-     );
+    );
 }
 /*-----------------------------------------------------------*/
 
@@ -505,11 +515,11 @@ static void prvSetupTimerInterrupt( void )
     {
         CMT0.CMCR.BIT.CKS = 0;
     }
-    #else
+    #else /* if portCLOCK_DIVISOR == 512 */
     {
         #error Invalid portCLOCK_DIVISOR setting
     }
-    #endif
+    #endif /* if portCLOCK_DIVISOR == 512 */
 
     /* Enable the interrupt... */
     _IEN( _CMT0_CMI0 ) = 1;
@@ -530,11 +540,11 @@ static void prvSetupTimerInterrupt( void )
         configPRE_SLEEP_PROCESSING( xExpectedIdleTime );
 
         /* xExpectedIdleTime being set to 0 by configPRE_SLEEP_PROCESSING()
-        means the application defined code has already executed the WAIT
-        instruction. */
+         * means the application defined code has already executed the WAIT
+         * instruction. */
         if( xExpectedIdleTime > 0 )
         {
-            __asm volatile( "WAIT" );
+            __asm volatile ( "WAIT" );
         }
 
         /* Allow the application to define some post sleep processing. */
@@ -548,8 +558,8 @@ static void prvSetupTimerInterrupt( void )
 
     void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
     {
-    uint32_t ulMatchValue, ulCompleteTickPeriods, ulCurrentCount;
-    eSleepModeStatus eSleepAction;
+        uint32_t ulMatchValue, ulCompleteTickPeriods, ulCurrentCount;
+        eSleepModeStatus eSleepAction;
 
         /* THIS FUNCTION IS CALLED WITH THE SCHEDULER SUSPENDED. */
 
@@ -560,43 +570,46 @@ static void prvSetupTimerInterrupt( void )
         }
 
         /* Calculate the reload value required to wait xExpectedIdleTime tick
-        periods. */
+         * periods. */
         ulMatchValue = ulMatchValueForOneTick * xExpectedIdleTime;
+
         if( ulMatchValue > ulStoppedTimerCompensation )
         {
             /* Compensate for the fact that the CMT is going to be stopped
-            momentarily. */
+             * momentarily. */
             ulMatchValue -= ulStoppedTimerCompensation;
         }
 
         /* Stop the CMT momentarily.  The time the CMT is stopped for is
-        accounted for as best it can be, but using the tickless mode will
-        inevitably result in some tiny drift of the time maintained by the
-        kernel with respect to calendar time. */
+         * accounted for as best it can be, but using the tickless mode will
+         * inevitably result in some tiny drift of the time maintained by the
+         * kernel with respect to calendar time. */
         CMT.CMSTR0.BIT.STR0 = 0;
+
         while( CMT.CMSTR0.BIT.STR0 == 1 )
         {
             /* Nothing to do here. */
         }
 
         /* Critical section using the global interrupt bit as the i bit is
-        automatically reset by the WAIT instruction. */
-        __asm volatile( "CLRPSW i" );
+         * automatically reset by the WAIT instruction. */
+        __asm volatile ( "CLRPSW i" );
 
         /* The tick flag is set to false before sleeping.  If it is true when
-        sleep mode is exited then sleep mode was probably exited because the
-        tick was suppressed for the entire xExpectedIdleTime period. */
+         * sleep mode is exited then sleep mode was probably exited because the
+         * tick was suppressed for the entire xExpectedIdleTime period. */
         ulTickFlag = pdFALSE;
 
         /* If a context switch is pending then abandon the low power entry as
-        the context switch might have been pended by an external interrupt that
-        requires processing. */
+         * the context switch might have been pended by an external interrupt that
+         * requires processing. */
         eSleepAction = eTaskConfirmSleepModeStatus();
+
         if( eSleepAction == eAbortSleep )
         {
             /* Restart tick. */
             CMT.CMSTR0.BIT.STR0 = 1;
-            __asm volatile( "SETPSW i" );
+            __asm volatile ( "SETPSW i" );
         }
         else if( eSleepAction == eNoTasksWaitingTimeout )
         {
@@ -610,7 +623,7 @@ static void prvSetupTimerInterrupt( void )
             SYSTEM.PRCR.WORD = portLOCK_KEY;
 
             /* Sleep until something happens.  Calling prvSleep() will
-            automatically reset the i bit in the PSW. */
+             * automatically reset the i bit in the PSW. */
             prvSleep( xExpectedIdleTime );
 
             /* Restart the CMT. */
@@ -630,7 +643,7 @@ static void prvSetupTimerInterrupt( void )
             SYSTEM.PRCR.WORD = portLOCK_KEY;
 
             /* Adjust the match value to take into account that the current
-            time slice is already partially complete. */
+             * time slice is already partially complete. */
             ulMatchValue -= ( uint32_t ) CMT0.CMCNT;
             CMT0.CMCOR = ( uint16_t ) ulMatchValue;
 
@@ -639,14 +652,15 @@ static void prvSetupTimerInterrupt( void )
             CMT.CMSTR0.BIT.STR0 = 1;
 
             /* Sleep until something happens.  Calling prvSleep() will
-            automatically reset the i bit in the PSW. */
+             * automatically reset the i bit in the PSW. */
             prvSleep( xExpectedIdleTime );
 
             /* Stop CMT.  Again, the time the SysTick is stopped for is
-            accounted for as best it can be, but using the tickless mode will
-            inevitably result in some tiny drift of the time maintained by the
-            kernel with respect to calendar time. */
+             * accounted for as best it can be, but using the tickless mode will
+             * inevitably result in some tiny drift of the time maintained by the
+             * kernel with respect to calendar time. */
             CMT.CMSTR0.BIT.STR0 = 0;
+
             while( CMT.CMSTR0.BIT.STR0 == 1 )
             {
                 /* Nothing to do here. */
@@ -657,42 +671,42 @@ static void prvSetupTimerInterrupt( void )
             if( ulTickFlag != pdFALSE )
             {
                 /* The tick interrupt has already executed, although because
-                this function is called with the scheduler suspended the actual
-                tick processing will not occur until after this function has
-                exited.  Reset the match value with whatever remains of this
-                tick period. */
+                 * this function is called with the scheduler suspended the actual
+                 * tick processing will not occur until after this function has
+                 * exited.  Reset the match value with whatever remains of this
+                 * tick period. */
                 ulMatchValue = ulMatchValueForOneTick - ulCurrentCount;
                 CMT0.CMCOR = ( uint16_t ) ulMatchValue;
 
                 /* The tick interrupt handler will already have pended the tick
-                processing in the kernel.  As the pending tick will be
-                processed as soon as this function exits, the tick value
-                maintained by the tick is stepped forward by one less than the
-                time spent sleeping.  The actual stepping of the tick appears
-                later in this function. */
+                 * processing in the kernel.  As the pending tick will be
+                 * processed as soon as this function exits, the tick value
+                 * maintained by the tick is stepped forward by one less than the
+                 * time spent sleeping.  The actual stepping of the tick appears
+                 * later in this function. */
                 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
             }
             else
             {
                 /* Something other than the tick interrupt ended the sleep.
-                How many complete tick periods passed while the processor was
-                sleeping? */
+                 * How many complete tick periods passed while the processor was
+                 * sleeping? */
                 ulCompleteTickPeriods = ulCurrentCount / ulMatchValueForOneTick;
 
                 /* The match value is set to whatever fraction of a single tick
-                period remains. */
+                 * period remains. */
                 ulMatchValue = ulCurrentCount - ( ulCompleteTickPeriods * ulMatchValueForOneTick );
                 CMT0.CMCOR = ( uint16_t ) ulMatchValue;
             }
 
             /* Restart the CMT so it runs up to the match value.  The match value
-            will get set to the value required to generate exactly one tick period
-            the next time the CMT interrupt executes. */
+             * will get set to the value required to generate exactly one tick period
+             * the next time the CMT interrupt executes. */
             CMT0.CMCNT = 0;
             CMT.CMSTR0.BIT.STR0 = 1;
 
             /* Wind the tick forward by the number of tick periods that the CPU
-            remained in a low power state. */
+             * remained in a low power state. */
             vTaskStepTick( ulCompleteTickPeriods );
         }
     }
diff --git a/portable/GCC/RX100/portmacro.h b/portable/GCC/RX100/portmacro.h
index 4556e147a..b32d2007b 100644
--- a/portable/GCC/RX100/portmacro.h
+++ b/portable/GCC/RX100/portmacro.h
@@ -45,80 +45,81 @@
  * These settings should not be altered.
  *-----------------------------------------------------------
  */
+
 /* When the FIT configurator or the Smart Configurator is used, platform.h has to be
  * used. */
 #ifndef configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H
-    #define configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H 0
+    #define configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H    0
 #endif
 
 /* Type definitions - these are a bit legacy and not really used now, other than
-portSTACK_TYPE and portBASE_TYPE. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint32_t
-#define portBASE_TYPE   long
+ * portSTACK_TYPE and portBASE_TYPE. */
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-    not need to be guarded with a critical section. */
-    #define portTICK_TYPE_IS_ATOMIC 1
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+    #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portBYTE_ALIGNMENT          8   /* Could make four, according to manual. */
-#define portSTACK_GROWTH            -1
-#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portNOP()                   __asm volatile( "NOP" )
+#define portBYTE_ALIGNMENT    8         /* Could make four, according to manual. */
+#define portSTACK_GROWTH      -1
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()    __asm volatile ( "NOP" )
 
 /* Save clobbered register, set ITU SWINR (at address 0x872E0), read the value
-back to ensure it is set before continuing, then restore the clobbered
-register. */
-#define portYIELD()                         \
-    __asm volatile                          \
-    (                                       \
-        "MOV.L #0x872E0, r5         \n\t"   \
-        "MOV.B #1, [r5]             \n\t"   \
-        "MOV.L [r5], r5             \n\t"   \
-        ::: "r5"                            \
+ * back to ensure it is set before continuing, then restore the clobbered
+ * register. */
+#define portYIELD()                       \
+    __asm volatile                        \
+    (                                     \
+        "MOV.L #0x872E0, r5         \n\t" \
+        "MOV.B #1, [r5]             \n\t" \
+        "MOV.L [r5], r5             \n\t" \
+        ::: "r5"                          \
     )
 
-#define portYIELD_FROM_ISR( x ) do { if( x != pdFALSE ) { portYIELD(); } } while( 0 )
+#define portYIELD_FROM_ISR( x )                           do { if( x != pdFALSE ) { portYIELD(); } } while( 0 )
 
 /* These macros should not be called directly, but through the
-taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
-performed if configASSERT() is defined to ensure an assertion handler does not
-inadvertently attempt to lower the IPL when the call to assert was triggered
-because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
-when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
-functions are those that end in FromISR.  FreeRTOS maintains a separate
-interrupt API to ensure API function and interrupt entry is as fast and as
-simple as possible. */
-#define portENABLE_INTERRUPTS()     __asm volatile ( "MVTIPL    #0" )
+ * taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
+ * performed if configASSERT() is defined to ensure an assertion handler does not
+ * inadvertently attempt to lower the IPL when the call to assert was triggered
+ * because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
+ * when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
+ * functions are those that end in FromISR.  FreeRTOS maintains a separate
+ * interrupt API to ensure API function and interrupt entry is as fast and as
+ * simple as possible. */
+#define portENABLE_INTERRUPTS()                           __asm volatile ( "MVTIPL    #0" )
 #ifdef configASSERT
-    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
-    #define portDISABLE_INTERRUPTS()    if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile ( "MVTIPL    %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
+    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+    #define portDISABLE_INTERRUPTS()                      if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile( "MVTIPL    %0" ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
 #else
-    #define portDISABLE_INTERRUPTS()    __asm volatile ( "MVTIPL    %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
+    #define portDISABLE_INTERRUPTS()                      __asm volatile ( "MVTIPL    %0" ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
 #endif
 
 /* Critical nesting counts are stored in the TCB. */
-#define portCRITICAL_NESTING_IN_TCB ( 1 )
+#define portCRITICAL_NESTING_IN_TCB    ( 1 )
 
 /* The critical nesting functions defined within tasks.c. */
 extern void vTaskEnterCritical( void );
@@ -127,24 +128,24 @@ extern void vTaskExitCritical( void );
 #define portEXIT_CRITICAL()     vTaskExitCritical()
 
 /* As this port allows interrupt nesting... */
-uint32_t ulPortGetIPL( void ) __attribute__((naked));
-void vPortSetIPL( uint32_t ulNewIPL ) __attribute__((naked));
-#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortGetIPL(); portDISABLE_INTERRUPTS()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) vPortSetIPL( uxSavedInterruptStatus )
+uint32_t ulPortGetIPL( void ) __attribute__( ( naked ) );
+void vPortSetIPL( uint32_t ulNewIPL ) __attribute__( ( naked ) );
+#define portSET_INTERRUPT_MASK_FROM_ISR()                              ulPortGetIPL(); portDISABLE_INTERRUPTS()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus )    vPortSetIPL( uxSavedInterruptStatus )
 
 /* Tickless idle/low power functionality. */
 #if configUSE_TICKLESS_IDLE == 1
     #ifndef portSUPPRESS_TICKS_AND_SLEEP
         extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
-        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
     #endif
 #endif
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/GCC/RX200/port.c b/portable/GCC/RX200/port.c
index 0f3770ac3..6261bc75c 100644
--- a/portable/GCC/RX200/port.c
+++ b/portable/GCC/RX200/port.c
@@ -27,8 +27,8 @@
  */
 
 /*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the SH2A port.
- *----------------------------------------------------------*/
+* Implementation of functions defined in portable.h for the SH2A port.
+*----------------------------------------------------------*/
 
 /* Scheduler includes. */
 #include "FreeRTOS.h"
@@ -51,17 +51,17 @@
 /*-----------------------------------------------------------*/
 
 /* Tasks should start with interrupts enabled and in Supervisor mode, therefore
-PSW is set with U and I set, and PM and IPL clear. */
+ * PSW is set with U and I set, and PM and IPL clear. */
 #define portINITIAL_PSW     ( ( StackType_t ) 0x00030000 )
 #define portINITIAL_FPSW    ( ( StackType_t ) 0x00000100 )
 
 /* These macros allow a critical section to be added around the call to
-xTaskIncrementTick(), which is only ever called from interrupts at the kernel
-priority - ie a known priority.  Therefore these local macros are a slight
-optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,
-which would require the old IPL to be read first and stored in a local variable. */
-#define portMASK_INTERRUPTS_FROM_KERNEL_ISR()   __asm volatile ( "MVTIPL    %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
-#define portUNMASK_INTERRUPTS_FROM_KERNEL_ISR()     __asm volatile ( "MVTIPL    %0" ::"i"(configKERNEL_INTERRUPT_PRIORITY) )
+ * xTaskIncrementTick(), which is only ever called from interrupts at the kernel
+ * priority - ie a known priority.  Therefore these local macros are a slight
+ * optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,
+ * which would require the old IPL to be read first and stored in a local variable. */
+#define portMASK_INTERRUPTS_FROM_KERNEL_ISR()      __asm volatile ( "MVTIPL    %0" ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+#define portUNMASK_INTERRUPTS_FROM_KERNEL_ISR()    __asm volatile ( "MVTIPL    %0" ::"i" ( configKERNEL_INTERRUPT_PRIORITY ) )
 
 /*-----------------------------------------------------------*/
 
@@ -69,7 +69,7 @@ which would require the old IPL to be read first and stored in a local variable.
  * Function to start the first task executing - written in asm code as direct
  * access to registers is required.
  */
-static void prvStartFirstTask( void ) __attribute__((naked));
+static void prvStartFirstTask( void ) __attribute__( ( naked ) );
 
 
 /*
@@ -105,14 +105,16 @@ static void prvStartFirstTask( void ) __attribute__((naked));
 
 /*-----------------------------------------------------------*/
 
-extern void *pxCurrentTCB;
+extern void * pxCurrentTCB;
 
 /*-----------------------------------------------------------*/
 
 /*
  * See header file for description.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
     /* R0 is not included as it is the stack pointer. */
 
@@ -123,8 +125,8 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
     *pxTopOfStack = ( StackType_t ) pxCode;
 
     /* When debugging it can be useful if every register is set to a known
-    value.  Otherwise code space can be saved by just setting the registers
-    that need to be set. */
+     * value.  Otherwise code space can be saved by just setting the registers
+     * that need to be set. */
     #ifdef USE_FULL_REGISTER_INITIALISATION
     {
         pxTopOfStack--;
@@ -157,11 +159,11 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
         *pxTopOfStack = 0x22222222;
         pxTopOfStack--;
     }
-    #else
+    #else /* ifdef USE_FULL_REGISTER_INITIALISATION */
     {
         pxTopOfStack -= 15;
     }
-    #endif
+    #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */
 
     *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
     pxTopOfStack--;
@@ -185,14 +187,14 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
 
 BaseType_t xPortStartScheduler( void )
 {
-extern void vApplicationSetupTimerInterrupt( void );
+    extern void vApplicationSetupTimerInterrupt( void );
 
     /* Use pxCurrentTCB just so it does not get optimised away. */
     if( pxCurrentTCB != NULL )
     {
         /* Call an application function to set up the timer that will generate the
-        tick interrupt.  This way the application can decide which peripheral to
-        use.  A demo application is provided to show a suitable example. */
+         * tick interrupt.  This way the application can decide which peripheral to
+         * use.  A demo application is provided to show a suitable example. */
         vApplicationSetupTimerInterrupt();
 
         /* Enable the software interrupt. */
@@ -216,7 +218,7 @@ extern void vApplicationSetupTimerInterrupt( void );
 void vPortEndScheduler( void )
 {
     /* Not implemented in ports where there is nothing to return to.
-    Artificially force an assert. */
+     * Artificially force an assert. */
     configASSERT( pxCurrentTCB == NULL );
 }
 /*-----------------------------------------------------------*/
@@ -225,19 +227,22 @@ static void prvStartFirstTask( void )
 {
     __asm volatile
     (
+
         /* When starting the scheduler there is nothing that needs moving to the
-        interrupt stack because the function is not called from an interrupt.
-        Just ensure the current stack is the user stack. */
+         * interrupt stack because the function is not called from an interrupt.
+         * Just ensure the current stack is the user stack. */
         "SETPSW     U                       \n" \
 
+
         /* Obtain the location of the stack associated with which ever task
-        pxCurrentTCB is currently pointing to. */
+         * pxCurrentTCB is currently pointing to. */
         "MOV.L      #_pxCurrentTCB, R15     \n" \
         "MOV.L      [R15], R15              \n" \
         "MOV.L      [R15], R0               \n" \
 
+
         /* Restore the registers from the stack of the task pointed to by
-        pxCurrentTCB. */
+         * pxCurrentTCB. */
         "POP        R15                     \n" \
 
         /* Accumulator low 32 bits. */
@@ -285,10 +290,11 @@ void vSoftwareInterruptISR( void )
         /* Re-enable interrupts. */
         "SETPSW     I                           \n" \
 
-        /* Move the data that was automatically pushed onto the interrupt stack when
-        the interrupt occurred from the interrupt stack to the user stack.
 
-        R15 is saved before it is clobbered. */
+        /* Move the data that was automatically pushed onto the interrupt stack when
+         * the interrupt occurred from the interrupt stack to the user stack.
+         *
+         * R15 is saved before it is clobbered. */
         "PUSH.L     R15                         \n" \
 
         /* Read the user stack pointer. */
@@ -335,8 +341,9 @@ void vSoftwareInterruptISR( void )
         "MOV.L      [ R15 ], R15                \n" \
         "MOV.L      R0, [ R15 ]                 \n" \
 
+
         /* Ensure the interrupt mask is set to the syscall priority while the kernel
-        structures are being accessed. */
+         * structures are being accessed. */
         "MVTIPL     %0                          \n" \
 
         /* Select the next task to run. */
@@ -345,14 +352,16 @@ void vSoftwareInterruptISR( void )
         /* Reset the interrupt mask as no more data structure access is required. */
         "MVTIPL     %1                          \n" \
 
+
         /* Load the stack pointer of the task that is now selected as the Running
-        state task from its TCB. */
+         * state task from its TCB. */
         "MOV.L      #_pxCurrentTCB,R15          \n" \
         "MOV.L      [ R15 ], R15                \n" \
         "MOV.L      [ R15 ], R0                 \n" \
 
+
         /* Restore the context of the new task.  The PSW (Program Status Word) and
-        PC will be popped by the RTE instruction. */
+         * PC will be popped by the RTE instruction. */
         "POP        R15                         \n" \
 
         /* Accumulator low 32 bits. */
@@ -383,7 +392,7 @@ void vSoftwareInterruptISR( void )
         "RTE                                    \n" \
         "NOP                                    \n" \
         "NOP                                      "
-        :: "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY), "i"(configKERNEL_INTERRUPT_PRIORITY)
+        ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ), "i" ( configKERNEL_INTERRUPT_PRIORITY )
     );
 }
 /*-----------------------------------------------------------*/
@@ -391,10 +400,10 @@ void vSoftwareInterruptISR( void )
 void vTickISR( void )
 {
     /* Re-enabled interrupts. */
-    __asm volatile( "SETPSW I" );
+    __asm volatile ( "SETPSW I" );
 
     /* Increment the tick, and perform any processing the new tick value
-    necessitates.  Ensure IPL is at the max syscall value first. */
+     * necessitates.  Ensure IPL is at the max syscall value first. */
     portMASK_INTERRUPTS_FROM_KERNEL_ISR();
     {
         if( xTaskIncrementTick() != pdFALSE )
@@ -432,5 +441,5 @@ void vPortSetIPL( uint32_t ulNewIPL )
         "MVTC   R5, PSW         \n" \
         "POP    R5              \n" \
         "RTS                      "
-     );
+    );
 }
diff --git a/portable/GCC/RX200/portmacro.h b/portable/GCC/RX200/portmacro.h
index 40682825d..2f153f87c 100644
--- a/portable/GCC/RX200/portmacro.h
+++ b/portable/GCC/RX200/portmacro.h
@@ -49,79 +49,79 @@
 /* When the FIT configurator or the Smart Configurator is used, platform.h has to be
  * used. */
 #ifndef configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H
-    #define configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H 0
+    #define configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H    0
 #endif
 
 /* Type definitions - these are a bit legacy and not really used now, other than
-portSTACK_TYPE and portBASE_TYPE. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint32_t
-#define portBASE_TYPE   long
+ * portSTACK_TYPE and portBASE_TYPE. */
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-    not need to be guarded with a critical section. */
-    #define portTICK_TYPE_IS_ATOMIC 1
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+    #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portBYTE_ALIGNMENT          8   /* Could make four, according to manual. */
-#define portSTACK_GROWTH            -1
-#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portNOP()                   __asm volatile( "NOP" )
+#define portBYTE_ALIGNMENT    8         /* Could make four, according to manual. */
+#define portSTACK_GROWTH      -1
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()    __asm volatile ( "NOP" )
 
 /* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;"
-where portITU_SWINTR is the location of the software interrupt register
-(0x000872E0).  Don't rely on the assembler to select a register, so instead
-save and restore clobbered registers manually. */
-#define portYIELD()                         \
-    __asm volatile                          \
-    (                                       \
-        "PUSH.L R10                 \n"     \
-        "MOV.L  #0x872E0, R10       \n"     \
-        "MOV.B  #0x1, [R10]         \n"     \
-        "MOV.L  [R10], R10          \n"     \
-        "POP    R10                 \n"     \
+ * where portITU_SWINTR is the location of the software interrupt register
+ * (0x000872E0).  Don't rely on the assembler to select a register, so instead
+ * save and restore clobbered registers manually. */
+#define portYIELD()                     \
+    __asm volatile                      \
+    (                                   \
+        "PUSH.L R10                 \n" \
+        "MOV.L  #0x872E0, R10       \n" \
+        "MOV.B  #0x1, [R10]         \n" \
+        "MOV.L  [R10], R10          \n" \
+        "POP    R10                 \n" \
     )
 
-#define portYIELD_FROM_ISR( x ) if( x != pdFALSE ) portYIELD()
+#define portYIELD_FROM_ISR( x )                           if( x != pdFALSE ) portYIELD( )
 
 /* These macros should not be called directly, but through the
-taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
-performed if configASSERT() is defined to ensure an assertion handler does not
-inadvertently attempt to lower the IPL when the call to assert was triggered
-because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
-when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
-functions are those that end in FromISR.  FreeRTOS maintains a separate
-interrupt API to ensure API function and interrupt entry is as fast and as
-simple as possible. */
-#define portENABLE_INTERRUPTS()     __asm volatile ( "MVTIPL    #0" )
+ * taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
+ * performed if configASSERT() is defined to ensure an assertion handler does not
+ * inadvertently attempt to lower the IPL when the call to assert was triggered
+ * because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
+ * when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
+ * functions are those that end in FromISR.  FreeRTOS maintains a separate
+ * interrupt API to ensure API function and interrupt entry is as fast and as
+ * simple as possible. */
+#define portENABLE_INTERRUPTS()                           __asm volatile ( "MVTIPL    #0" )
 #ifdef configASSERT
-    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
-    #define portDISABLE_INTERRUPTS()    if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile ( "MVTIPL    %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
+    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+    #define portDISABLE_INTERRUPTS()                      if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile( "MVTIPL    %0" ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
 #else
-    #define portDISABLE_INTERRUPTS()    __asm volatile ( "MVTIPL    %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
+    #define portDISABLE_INTERRUPTS()                      __asm volatile ( "MVTIPL    %0" ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
 #endif
 
 /* Critical nesting counts are stored in the TCB. */
-#define portCRITICAL_NESTING_IN_TCB ( 1 )
+#define portCRITICAL_NESTING_IN_TCB    ( 1 )
 
 /* The critical nesting functions defined within tasks.c. */
 extern void vTaskEnterCritical( void );
@@ -130,16 +130,16 @@ extern void vTaskExitCritical( void );
 #define portEXIT_CRITICAL()     vTaskExitCritical()
 
 /* As this port allows interrupt nesting... */
-uint32_t ulPortGetIPL( void ) __attribute__((naked));
-void vPortSetIPL( uint32_t ulNewIPL ) __attribute__((naked));
-#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortGetIPL(); portDISABLE_INTERRUPTS()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) vPortSetIPL( uxSavedInterruptStatus )
+uint32_t ulPortGetIPL( void ) __attribute__( ( naked ) );
+void vPortSetIPL( uint32_t ulNewIPL ) __attribute__( ( naked ) );
+#define portSET_INTERRUPT_MASK_FROM_ISR()                              ulPortGetIPL(); portDISABLE_INTERRUPTS()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus )    vPortSetIPL( uxSavedInterruptStatus )
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/GCC/RX600/port.c b/portable/GCC/RX600/port.c
index 0bc99683f..94747bdbe 100644
--- a/portable/GCC/RX600/port.c
+++ b/portable/GCC/RX600/port.c
@@ -27,8 +27,8 @@
  */
 
 /*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the SH2A port.
- *----------------------------------------------------------*/
+* Implementation of functions defined in portable.h for the SH2A port.
+*----------------------------------------------------------*/
 
 /* Scheduler includes. */
 #include "FreeRTOS.h"
@@ -52,17 +52,17 @@
 /*-----------------------------------------------------------*/
 
 /* Tasks should start with interrupts enabled and in Supervisor mode, therefore
-PSW is set with U and I set, and PM and IPL clear. */
+ * PSW is set with U and I set, and PM and IPL clear. */
 #define portINITIAL_PSW     ( ( StackType_t ) 0x00030000 )
 #define portINITIAL_FPSW    ( ( StackType_t ) 0x00000100 )
 
 /* These macros allow a critical section to be added around the call to
-xTaskIncrementTick(), which is only ever called from interrupts at the kernel
-priority - ie a known priority.  Therefore these local macros are a slight
-optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,
-which would require the old IPL to be read first and stored in a local variable. */
-#define portDISABLE_INTERRUPTS_FROM_KERNEL_ISR()    __asm volatile ( "MVTIPL    %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
-#define portENABLE_INTERRUPTS_FROM_KERNEL_ISR()     __asm volatile ( "MVTIPL    %0" ::"i"(configKERNEL_INTERRUPT_PRIORITY) )
+ * xTaskIncrementTick(), which is only ever called from interrupts at the kernel
+ * priority - ie a known priority.  Therefore these local macros are a slight
+ * optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,
+ * which would require the old IPL to be read first and stored in a local variable. */
+#define portDISABLE_INTERRUPTS_FROM_KERNEL_ISR()    __asm volatile ( "MVTIPL    %0" ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+#define portENABLE_INTERRUPTS_FROM_KERNEL_ISR()     __asm volatile ( "MVTIPL    %0" ::"i" ( configKERNEL_INTERRUPT_PRIORITY ) )
 
 /*-----------------------------------------------------------*/
 
@@ -70,7 +70,8 @@ which would require the old IPL to be read first and stored in a local variable.
  * Function to start the first task executing - written in asm code as direct
  * access to registers is required.
  */
-static void prvStartFirstTask( void ) __attribute__((naked));
+static void prvStartFirstTask( void ) __attribute__( ( naked ) );
+
 /*
  * Software interrupt handler.  Performs the actual context switch (saving and
  * restoring of registers).  Written in asm code as direct register access is
@@ -104,14 +105,16 @@ static void prvStartFirstTask( void ) __attribute__((naked));
 
 /*-----------------------------------------------------------*/
 
-extern void *pxCurrentTCB;
+extern void * pxCurrentTCB;
 
 /*-----------------------------------------------------------*/
 
 /*
  * See header file for description.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
     /* R0 is not included as it is the stack pointer. */
 
@@ -122,8 +125,8 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
     *pxTopOfStack = ( StackType_t ) pxCode;
 
     /* When debugging it can be useful if every register is set to a known
-    value.  Otherwise code space can be saved by just setting the registers
-    that need to be set. */
+     * value.  Otherwise code space can be saved by just setting the registers
+     * that need to be set. */
     #ifdef USE_FULL_REGISTER_INITIALISATION
     {
         pxTopOfStack--;
@@ -156,11 +159,11 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
         *pxTopOfStack = 0x22222222;
         pxTopOfStack--;
     }
-    #else
+    #else /* ifdef USE_FULL_REGISTER_INITIALISATION */
     {
         pxTopOfStack -= 15;
     }
-    #endif
+    #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */
 
     *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
     pxTopOfStack--;
@@ -176,14 +179,14 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
 
 BaseType_t xPortStartScheduler( void )
 {
-extern void vApplicationSetupTimerInterrupt( void );
+    extern void vApplicationSetupTimerInterrupt( void );
 
     /* Use pxCurrentTCB just so it does not get optimised away. */
     if( pxCurrentTCB != NULL )
     {
         /* Call an application function to set up the timer that will generate the
-        tick interrupt.  This way the application can decide which peripheral to
-        use.  A demo application is provided to show a suitable example. */
+         * tick interrupt.  This way the application can decide which peripheral to
+         * use.  A demo application is provided to show a suitable example. */
         vApplicationSetupTimerInterrupt();
 
         /* Enable the software interrupt. */
@@ -207,7 +210,7 @@ extern void vApplicationSetupTimerInterrupt( void );
 void vPortEndScheduler( void )
 {
     /* Not implemented in ports where there is nothing to return to.
-    Artificially force an assert. */
+     * Artificially force an assert. */
     configASSERT( pxCurrentTCB == NULL );
 }
 /*-----------------------------------------------------------*/
@@ -216,19 +219,22 @@ static void prvStartFirstTask( void )
 {
     __asm volatile
     (
+
         /* When starting the scheduler there is nothing that needs moving to the
-        interrupt stack because the function is not called from an interrupt.
-        Just ensure the current stack is the user stack. */
+         * interrupt stack because the function is not called from an interrupt.
+         * Just ensure the current stack is the user stack. */
         "SETPSW     U                       \n" \
 
+
         /* Obtain the location of the stack associated with which ever task
-        pxCurrentTCB is currently pointing to. */
+         * pxCurrentTCB is currently pointing to. */
         "MOV.L      #_pxCurrentTCB, R15     \n" \
         "MOV.L      [R15], R15              \n" \
         "MOV.L      [R15], R0               \n" \
 
+
         /* Restore the registers from the stack of the task pointed to by
-        pxCurrentTCB. */
+         * pxCurrentTCB. */
         "POP        R15                     \n" \
 
         /* Accumulator low 32 bits. */
@@ -260,10 +266,11 @@ void vSoftwareInterruptISR( void )
         /* Re-enable interrupts. */
         "SETPSW     I                           \n" \
 
-        /* Move the data that was automatically pushed onto the interrupt stack when
-        the interrupt occurred from the interrupt stack to the user stack.
 
-        R15 is saved before it is clobbered. */
+        /* Move the data that was automatically pushed onto the interrupt stack when
+         * the interrupt occurred from the interrupt stack to the user stack.
+         *
+         * R15 is saved before it is clobbered. */
         "PUSH.L     R15                         \n" \
 
         /* Read the user stack pointer. */
@@ -305,8 +312,9 @@ void vSoftwareInterruptISR( void )
         "MOV.L      [ R15 ], R15                \n" \
         "MOV.L      R0, [ R15 ]                 \n" \
 
+
         /* Ensure the interrupt mask is set to the syscall priority while the kernel
-        structures are being accessed. */
+         * structures are being accessed. */
         "MVTIPL     %0                          \n" \
 
         /* Select the next task to run. */
@@ -315,14 +323,16 @@ void vSoftwareInterruptISR( void )
         /* Reset the interrupt mask as no more data structure access is required. */
         "MVTIPL     %1                          \n" \
 
+
         /* Load the stack pointer of the task that is now selected as the Running
-        state task from its TCB. */
+         * state task from its TCB. */
         "MOV.L      #_pxCurrentTCB,R15          \n" \
         "MOV.L      [ R15 ], R15                \n" \
         "MOV.L      [ R15 ], R0                 \n" \
 
+
         /* Restore the context of the new task.  The PSW (Program Status Word) and
-        PC will be popped by the RTE instruction. */
+         * PC will be popped by the RTE instruction. */
         "POP        R15                         \n" \
         "MVTACLO    R15                         \n" \
         "POP        R15                         \n" \
@@ -333,7 +343,7 @@ void vSoftwareInterruptISR( void )
         "RTE                                    \n" \
         "NOP                                    \n" \
         "NOP                                      "
-        :: "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY), "i"(configKERNEL_INTERRUPT_PRIORITY)
+        ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ), "i" ( configKERNEL_INTERRUPT_PRIORITY )
     );
 }
 /*-----------------------------------------------------------*/
@@ -341,10 +351,10 @@ void vSoftwareInterruptISR( void )
 void vTickISR( void )
 {
     /* Re-enabled interrupts. */
-    __asm volatile( "SETPSW I" );
+    __asm volatile ( "SETPSW I" );
 
     /* Increment the tick, and perform any processing the new tick value
-    necessitates.  Ensure IPL is at the max syscall value first. */
+     * necessitates.  Ensure IPL is at the max syscall value first. */
     portDISABLE_INTERRUPTS_FROM_KERNEL_ISR();
     {
         if( xTaskIncrementTick() != pdFALSE )
@@ -385,5 +395,5 @@ void vPortSetIPL( uint32_t ulNewIPL )
         "MVTC   R5, PSW         \n" \
         "POP    R5              \n" \
         "RTS                      "
-     );
+    );
 }
diff --git a/portable/GCC/RX600/portmacro.h b/portable/GCC/RX600/portmacro.h
index 7e7bbe88b..7d1fdb6c7 100644
--- a/portable/GCC/RX600/portmacro.h
+++ b/portable/GCC/RX600/portmacro.h
@@ -49,79 +49,79 @@
 /* When the FIT configurator or the Smart Configurator is used, platform.h has to be
  * used. */
 #ifndef configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H
-    #define configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H 0
+    #define configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H    0
 #endif
 
 /* Type definitions - these are a bit legacy and not really used now, other than
-portSTACK_TYPE and portBASE_TYPE. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint32_t
-#define portBASE_TYPE   long
+ * portSTACK_TYPE and portBASE_TYPE. */
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-    not need to be guarded with a critical section. */
-    #define portTICK_TYPE_IS_ATOMIC 1
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+    #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portBYTE_ALIGNMENT          8   /* Could make four, according to manual. */
-#define portSTACK_GROWTH            -1
-#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portNOP()                   __asm volatile( "NOP" )
+#define portBYTE_ALIGNMENT    8         /* Could make four, according to manual. */
+#define portSTACK_GROWTH      -1
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()    __asm volatile ( "NOP" )
 
 /* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;"
-where portITU_SWINTR is the location of the software interrupt register
-(0x000872E0).  Don't rely on the assembler to select a register, so instead
-save and restore clobbered registers manually. */
-#define portYIELD()                         \
-    __asm volatile                          \
-    (                                       \
-        "PUSH.L R10                 \n"     \
-        "MOV.L  #0x872E0, R10       \n"     \
-        "MOV.B  #0x1, [R10]         \n"     \
-        "MOV.L  [R10], R10          \n"     \
-        "POP    R10                 \n"     \
+ * where portITU_SWINTR is the location of the software interrupt register
+ * (0x000872E0).  Don't rely on the assembler to select a register, so instead
+ * save and restore clobbered registers manually. */
+#define portYIELD()                     \
+    __asm volatile                      \
+    (                                   \
+        "PUSH.L R10                 \n" \
+        "MOV.L  #0x872E0, R10       \n" \
+        "MOV.B  #0x1, [R10]         \n" \
+        "MOV.L  [R10], R10          \n" \
+        "POP    R10                 \n" \
     )
 
-#define portYIELD_FROM_ISR( x ) do { if( x != pdFALSE ) portYIELD(); } while( 0 )
+#define portYIELD_FROM_ISR( x )                           do { if( x != pdFALSE ) portYIELD( ); } while( 0 )
 
 /* These macros should not be called directly, but through the
-taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
-performed if configASSERT() is defined to ensure an assertion handler does not
-inadvertently attempt to lower the IPL when the call to assert was triggered
-because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
-when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
-functions are those that end in FromISR.  FreeRTOS maintains a separate
-interrupt API to ensure API function and interrupt entry is as fast and as
-simple as possible. */
-#define portENABLE_INTERRUPTS()     __asm volatile ( "MVTIPL    #0" )
+ * taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
+ * performed if configASSERT() is defined to ensure an assertion handler does not
+ * inadvertently attempt to lower the IPL when the call to assert was triggered
+ * because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
+ * when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
+ * functions are those that end in FromISR.  FreeRTOS maintains a separate
+ * interrupt API to ensure API function and interrupt entry is as fast and as
+ * simple as possible. */
+#define portENABLE_INTERRUPTS()                           __asm volatile ( "MVTIPL    #0" )
 #ifdef configASSERT
-    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
-    #define portDISABLE_INTERRUPTS()    if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile ( "MVTIPL    %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
+    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+    #define portDISABLE_INTERRUPTS()                      if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile( "MVTIPL    %0" ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
 #else
-    #define portDISABLE_INTERRUPTS()    __asm volatile ( "MVTIPL    %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
+    #define portDISABLE_INTERRUPTS()                      __asm volatile ( "MVTIPL    %0" ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
 #endif
 
 /* Critical nesting counts are stored in the TCB. */
-#define portCRITICAL_NESTING_IN_TCB ( 1 )
+#define portCRITICAL_NESTING_IN_TCB    ( 1 )
 
 /* The critical nesting functions defined within tasks.c. */
 extern void vTaskEnterCritical( void );
@@ -130,16 +130,16 @@ extern void vTaskExitCritical( void );
 #define portEXIT_CRITICAL()     vTaskExitCritical()
 
 /* As this port allows interrupt nesting... */
-uint32_t ulPortGetIPL( void ) __attribute__((naked));
-void vPortSetIPL( uint32_t ulNewIPL ) __attribute__((naked));
-#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortGetIPL(); portDISABLE_INTERRUPTS()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) vPortSetIPL( uxSavedInterruptStatus )
+uint32_t ulPortGetIPL( void ) __attribute__( ( naked ) );
+void vPortSetIPL( uint32_t ulNewIPL ) __attribute__( ( naked ) );
+#define portSET_INTERRUPT_MASK_FROM_ISR()                              ulPortGetIPL(); portDISABLE_INTERRUPTS()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus )    vPortSetIPL( uxSavedInterruptStatus )
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/GCC/RX600v2/port.c b/portable/GCC/RX600v2/port.c
index ca96d8118..56212de9c 100644
--- a/portable/GCC/RX600v2/port.c
+++ b/portable/GCC/RX600v2/port.c
@@ -27,8 +27,8 @@
  */
 
 /*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the SH2A port.
- *----------------------------------------------------------*/
+* Implementation of functions defined in portable.h for the SH2A port.
+*----------------------------------------------------------*/
 
 /* Scheduler includes. */
 #include "FreeRTOS.h"
@@ -51,17 +51,17 @@
 /*-----------------------------------------------------------*/
 
 /* Tasks should start with interrupts enabled and in Supervisor mode, therefore
-PSW is set with U and I set, and PM and IPL clear. */
+ * PSW is set with U and I set, and PM and IPL clear. */
 #define portINITIAL_PSW     ( ( StackType_t ) 0x00030000 )
 #define portINITIAL_FPSW    ( ( StackType_t ) 0x00000100 )
 
 /* These macros allow a critical section to be added around the call to
-xTaskIncrementTick(), which is only ever called from interrupts at the kernel
-priority - ie a known priority.  Therefore these local macros are a slight
-optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,
-which would require the old IPL to be read first and stored in a local variable. */
-#define portMASK_INTERRUPTS_FROM_KERNEL_ISR()   __asm volatile ( "MVTIPL    %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
-#define portUNMASK_INTERRUPTS_FROM_KERNEL_ISR()     __asm volatile ( "MVTIPL    %0" ::"i"(configKERNEL_INTERRUPT_PRIORITY) )
+ * xTaskIncrementTick(), which is only ever called from interrupts at the kernel
+ * priority - ie a known priority.  Therefore these local macros are a slight
+ * optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,
+ * which would require the old IPL to be read first and stored in a local variable. */
+#define portMASK_INTERRUPTS_FROM_KERNEL_ISR()      __asm volatile ( "MVTIPL    %0" ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+#define portUNMASK_INTERRUPTS_FROM_KERNEL_ISR()    __asm volatile ( "MVTIPL    %0" ::"i" ( configKERNEL_INTERRUPT_PRIORITY ) )
 
 /*-----------------------------------------------------------*/
 
@@ -69,7 +69,7 @@ which would require the old IPL to be read first and stored in a local variable.
  * Function to start the first task executing - written in asm code as direct
  * access to registers is required.
  */
-static void prvStartFirstTask( void ) __attribute__((naked));
+static void prvStartFirstTask( void ) __attribute__( ( naked ) );
 
 /*
  * Software interrupt handler.  Performs the actual context switch (saving and
@@ -77,10 +77,10 @@ static void prvStartFirstTask( void ) __attribute__((naked));
  * required.
  */
 #if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
-R_BSP_PRAGMA_INTERRUPT( vSoftwareInterruptISR, VECT( ICU, SWINT ) )
-R_BSP_ATTRIB_INTERRUPT void vSoftwareInterruptISR( void ) __attribute__( ( naked ) );
+    R_BSP_PRAGMA_INTERRUPT( vSoftwareInterruptISR, VECT( ICU, SWINT ) )
+    R_BSP_ATTRIB_INTERRUPT void vSoftwareInterruptISR( void ) __attribute__( ( naked ) );
 #else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
-void vSoftwareInterruptISR( void ) __attribute__((naked));
+    void vSoftwareInterruptISR( void ) __attribute__( ( naked ) );
 #endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H  */
 
 /*
@@ -99,14 +99,16 @@ void vSoftwareInterruptISR( void ) __attribute__((naked));
 #endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
 /*-----------------------------------------------------------*/
 
-extern void *pxCurrentTCB;
+extern void * pxCurrentTCB;
 
 /*-----------------------------------------------------------*/
 
 /*
  * See header file for description.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
     /* R0 is not included as it is the stack pointer. */
 
@@ -117,8 +119,8 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
     *pxTopOfStack = ( StackType_t ) pxCode;
 
     /* When debugging it can be useful if every register is set to a known
-    value.  Otherwise code space can be saved by just setting the registers
-    that need to be set. */
+     * value.  Otherwise code space can be saved by just setting the registers
+     * that need to be set. */
     #ifdef USE_FULL_REGISTER_INITIALISATION
     {
         pxTopOfStack--;
@@ -151,11 +153,11 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
         *pxTopOfStack = 0x22222222;
         pxTopOfStack--;
     }
-    #else
+    #else /* ifdef USE_FULL_REGISTER_INITIALISATION */
     {
         pxTopOfStack -= 15;
     }
-    #endif
+    #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */
 
     *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
     pxTopOfStack--;
@@ -179,14 +181,14 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
 
 BaseType_t xPortStartScheduler( void )
 {
-extern void vApplicationSetupTimerInterrupt( void );
+    extern void vApplicationSetupTimerInterrupt( void );
 
     /* Use pxCurrentTCB just so it does not get optimised away. */
     if( pxCurrentTCB != NULL )
     {
         /* Call an application function to set up the timer that will generate the
-        tick interrupt.  This way the application can decide which peripheral to
-        use.  A demo application is provided to show a suitable example. */
+         * tick interrupt.  This way the application can decide which peripheral to
+         * use.  A demo application is provided to show a suitable example. */
         vApplicationSetupTimerInterrupt();
 
         /* Enable the software interrupt. */
@@ -210,7 +212,7 @@ extern void vApplicationSetupTimerInterrupt( void );
 void vPortEndScheduler( void )
 {
     /* Not implemented in ports where there is nothing to return to.
-    Artificially force an assert. */
+     * Artificially force an assert. */
     configASSERT( pxCurrentTCB == NULL );
 }
 /*-----------------------------------------------------------*/
@@ -219,19 +221,22 @@ static void prvStartFirstTask( void )
 {
     __asm volatile
     (
+
         /* When starting the scheduler there is nothing that needs moving to the
-        interrupt stack because the function is not called from an interrupt.
-        Just ensure the current stack is the user stack. */
+         * interrupt stack because the function is not called from an interrupt.
+         * Just ensure the current stack is the user stack. */
         "SETPSW     U                       \n" \
 
+
         /* Obtain the location of the stack associated with which ever task
-        pxCurrentTCB is currently pointing to. */
+         * pxCurrentTCB is currently pointing to. */
         "MOV.L      #_pxCurrentTCB, R15     \n" \
         "MOV.L      [R15], R15              \n" \
         "MOV.L      [R15], R0               \n" \
 
+
         /* Restore the registers from the stack of the task pointed to by
-        pxCurrentTCB. */
+         * pxCurrentTCB. */
         "POP        R15                     \n" \
 
         /* Accumulator low 32 bits. */
@@ -279,10 +284,11 @@ void vSoftwareInterruptISR( void )
         /* Re-enable interrupts. */
         "SETPSW     I                           \n" \
 
-        /* Move the data that was automatically pushed onto the interrupt stack when
-        the interrupt occurred from the interrupt stack to the user stack.
 
-        R15 is saved before it is clobbered. */
+        /* Move the data that was automatically pushed onto the interrupt stack when
+         * the interrupt occurred from the interrupt stack to the user stack.
+         *
+         * R15 is saved before it is clobbered. */
         "PUSH.L     R15                         \n" \
 
         /* Read the user stack pointer. */
@@ -329,8 +335,9 @@ void vSoftwareInterruptISR( void )
         "MOV.L      [ R15 ], R15                \n" \
         "MOV.L      R0, [ R15 ]                 \n" \
 
+
         /* Ensure the interrupt mask is set to the syscall priority while the kernel
-        structures are being accessed. */
+         * structures are being accessed. */
         "MVTIPL     %0                          \n" \
 
         /* Select the next task to run. */
@@ -339,14 +346,16 @@ void vSoftwareInterruptISR( void )
         /* Reset the interrupt mask as no more data structure access is required. */
         "MVTIPL     %1                          \n" \
 
+
         /* Load the stack pointer of the task that is now selected as the Running
-        state task from its TCB. */
+         * state task from its TCB. */
         "MOV.L      #_pxCurrentTCB,R15          \n" \
         "MOV.L      [ R15 ], R15                \n" \
         "MOV.L      [ R15 ], R0                 \n" \
 
+
         /* Restore the context of the new task.  The PSW (Program Status Word) and
-        PC will be popped by the RTE instruction. */
+         * PC will be popped by the RTE instruction. */
         "POP        R15                         \n" \
 
         /* Accumulator low 32 bits. */
@@ -377,7 +386,7 @@ void vSoftwareInterruptISR( void )
         "RTE                                    \n" \
         "NOP                                    \n" \
         "NOP                                      "
-        :: "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY), "i"(configKERNEL_INTERRUPT_PRIORITY)
+        ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ), "i" ( configKERNEL_INTERRUPT_PRIORITY )
     );
 }
 /*-----------------------------------------------------------*/
@@ -385,10 +394,10 @@ void vSoftwareInterruptISR( void )
 void vTickISR( void )
 {
     /* Re-enabled interrupts. */
-    __asm volatile( "SETPSW I" );
+    __asm volatile ( "SETPSW I" );
 
     /* Increment the tick, and perform any processing the new tick value
-    necessitates.  Ensure IPL is at the max syscall value first. */
+     * necessitates.  Ensure IPL is at the max syscall value first. */
     portMASK_INTERRUPTS_FROM_KERNEL_ISR();
     {
         if( xTaskIncrementTick() != pdFALSE )
@@ -429,5 +438,5 @@ void vPortSetIPL( uint32_t ulNewIPL )
         "MVTC   R5, PSW         \n" \
         "POP    R5              \n" \
         "RTS                      "
-     );
+    );
 }
diff --git a/portable/GCC/RX600v2/portmacro.h b/portable/GCC/RX600v2/portmacro.h
index 7e7bbe88b..7d1fdb6c7 100644
--- a/portable/GCC/RX600v2/portmacro.h
+++ b/portable/GCC/RX600v2/portmacro.h
@@ -49,79 +49,79 @@
 /* When the FIT configurator or the Smart Configurator is used, platform.h has to be
  * used. */
 #ifndef configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H
-    #define configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H 0
+    #define configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H    0
 #endif
 
 /* Type definitions - these are a bit legacy and not really used now, other than
-portSTACK_TYPE and portBASE_TYPE. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint32_t
-#define portBASE_TYPE   long
+ * portSTACK_TYPE and portBASE_TYPE. */
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-    not need to be guarded with a critical section. */
-    #define portTICK_TYPE_IS_ATOMIC 1
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+    #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portBYTE_ALIGNMENT          8   /* Could make four, according to manual. */
-#define portSTACK_GROWTH            -1
-#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portNOP()                   __asm volatile( "NOP" )
+#define portBYTE_ALIGNMENT    8         /* Could make four, according to manual. */
+#define portSTACK_GROWTH      -1
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()    __asm volatile ( "NOP" )
 
 /* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;"
-where portITU_SWINTR is the location of the software interrupt register
-(0x000872E0).  Don't rely on the assembler to select a register, so instead
-save and restore clobbered registers manually. */
-#define portYIELD()                         \
-    __asm volatile                          \
-    (                                       \
-        "PUSH.L R10                 \n"     \
-        "MOV.L  #0x872E0, R10       \n"     \
-        "MOV.B  #0x1, [R10]         \n"     \
-        "MOV.L  [R10], R10          \n"     \
-        "POP    R10                 \n"     \
+ * where portITU_SWINTR is the location of the software interrupt register
+ * (0x000872E0).  Don't rely on the assembler to select a register, so instead
+ * save and restore clobbered registers manually. */
+#define portYIELD()                     \
+    __asm volatile                      \
+    (                                   \
+        "PUSH.L R10                 \n" \
+        "MOV.L  #0x872E0, R10       \n" \
+        "MOV.B  #0x1, [R10]         \n" \
+        "MOV.L  [R10], R10          \n" \
+        "POP    R10                 \n" \
     )
 
-#define portYIELD_FROM_ISR( x ) do { if( x != pdFALSE ) portYIELD(); } while( 0 )
+#define portYIELD_FROM_ISR( x )                           do { if( x != pdFALSE ) portYIELD( ); } while( 0 )
 
 /* These macros should not be called directly, but through the
-taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
-performed if configASSERT() is defined to ensure an assertion handler does not
-inadvertently attempt to lower the IPL when the call to assert was triggered
-because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
-when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
-functions are those that end in FromISR.  FreeRTOS maintains a separate
-interrupt API to ensure API function and interrupt entry is as fast and as
-simple as possible. */
-#define portENABLE_INTERRUPTS()     __asm volatile ( "MVTIPL    #0" )
+ * taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
+ * performed if configASSERT() is defined to ensure an assertion handler does not
+ * inadvertently attempt to lower the IPL when the call to assert was triggered
+ * because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
+ * when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
+ * functions are those that end in FromISR.  FreeRTOS maintains a separate
+ * interrupt API to ensure API function and interrupt entry is as fast and as
+ * simple as possible. */
+#define portENABLE_INTERRUPTS()                           __asm volatile ( "MVTIPL    #0" )
 #ifdef configASSERT
-    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
-    #define portDISABLE_INTERRUPTS()    if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile ( "MVTIPL    %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
+    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+    #define portDISABLE_INTERRUPTS()                      if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile( "MVTIPL    %0" ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
 #else
-    #define portDISABLE_INTERRUPTS()    __asm volatile ( "MVTIPL    %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
+    #define portDISABLE_INTERRUPTS()                      __asm volatile ( "MVTIPL    %0" ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
 #endif
 
 /* Critical nesting counts are stored in the TCB. */
-#define portCRITICAL_NESTING_IN_TCB ( 1 )
+#define portCRITICAL_NESTING_IN_TCB    ( 1 )
 
 /* The critical nesting functions defined within tasks.c. */
 extern void vTaskEnterCritical( void );
@@ -130,16 +130,16 @@ extern void vTaskExitCritical( void );
 #define portEXIT_CRITICAL()     vTaskExitCritical()
 
 /* As this port allows interrupt nesting... */
-uint32_t ulPortGetIPL( void ) __attribute__((naked));
-void vPortSetIPL( uint32_t ulNewIPL ) __attribute__((naked));
-#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortGetIPL(); portDISABLE_INTERRUPTS()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) vPortSetIPL( uxSavedInterruptStatus )
+uint32_t ulPortGetIPL( void ) __attribute__( ( naked ) );
+void vPortSetIPL( uint32_t ulNewIPL ) __attribute__( ( naked ) );
+#define portSET_INTERRUPT_MASK_FROM_ISR()                              ulPortGetIPL(); portDISABLE_INTERRUPTS()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus )    vPortSetIPL( uxSavedInterruptStatus )
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/GCC/RX700v3_DPFPU/port.c b/portable/GCC/RX700v3_DPFPU/port.c
index c89e7ee2a..7aa1e741c 100644
--- a/portable/GCC/RX700v3_DPFPU/port.c
+++ b/portable/GCC/RX700v3_DPFPU/port.c
@@ -54,22 +54,22 @@
 
 /* Tasks should start with interrupts enabled and in Supervisor mode, therefore
  * PSW is set with U and I set, and PM and IPL clear. */
-#define portINITIAL_PSW     ( ( StackType_t ) 0x00030000 )
-#define portINITIAL_FPSW    ( ( StackType_t ) 0x00000100 )
-#define portINITIAL_DPSW    ( ( StackType_t ) 0x00000100 )
-#define portINITIAL_DCMR    ( ( StackType_t ) 0x00000000 )
-#define portINITIAL_DECNT   ( ( StackType_t ) 0x00000001 )
+#define portINITIAL_PSW                  ( ( StackType_t ) 0x00030000 )
+#define portINITIAL_FPSW                 ( ( StackType_t ) 0x00000100 )
+#define portINITIAL_DPSW                 ( ( StackType_t ) 0x00000100 )
+#define portINITIAL_DCMR                 ( ( StackType_t ) 0x00000000 )
+#define portINITIAL_DECNT                ( ( StackType_t ) 0x00000001 )
 
 /* Tasks are not created with a DPFPU context, but can be given a DPFPU context
  * after they have been created.  A variable is stored as part of the tasks context
  * that holds portNO_DPFPU_CONTEXT if the task does not have a DPFPU context, or
  * any other value if the task does have a DPFPU context. */
-#define portNO_DPFPU_CONTEXT    ( ( StackType_t ) 0 )
-#define portHAS_DPFPU_CONTEXT   ( ( StackType_t ) 1 )
+#define portNO_DPFPU_CONTEXT             ( ( StackType_t ) 0 )
+#define portHAS_DPFPU_CONTEXT            ( ( StackType_t ) 1 )
 
 /* The space on the stack required to hold the DPFPU data registers.  This is 16
  * 64-bit registers. */
-#define portDPFPU_DATA_REGISTER_WORDS   ( 16 * 2 )
+#define portDPFPU_DATA_REGISTER_WORDS    ( 16 * 2 )
 
 /* These macros allow a critical section to be added around the call to
  * xTaskIncrementTick(), which is only ever called from interrupts at the kernel
@@ -154,41 +154,41 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
      * value.  Otherwise code space can be saved by just setting the registers
      * that need to be set. */
     #ifdef USE_FULL_REGISTER_INITIALISATION
-        {
-            pxTopOfStack--;
-            *pxTopOfStack = 0xffffffff; /* r15. */
-            pxTopOfStack--;
-            *pxTopOfStack = 0xeeeeeeee;
-            pxTopOfStack--;
-            *pxTopOfStack = 0xdddddddd;
-            pxTopOfStack--;
-            *pxTopOfStack = 0xcccccccc;
-            pxTopOfStack--;
-            *pxTopOfStack = 0xbbbbbbbb;
-            pxTopOfStack--;
-            *pxTopOfStack = 0xaaaaaaaa;
-            pxTopOfStack--;
-            *pxTopOfStack = 0x99999999;
-            pxTopOfStack--;
-            *pxTopOfStack = 0x88888888;
-            pxTopOfStack--;
-            *pxTopOfStack = 0x77777777;
-            pxTopOfStack--;
-            *pxTopOfStack = 0x66666666;
-            pxTopOfStack--;
-            *pxTopOfStack = 0x55555555;
-            pxTopOfStack--;
-            *pxTopOfStack = 0x44444444;
-            pxTopOfStack--;
-            *pxTopOfStack = 0x33333333;
-            pxTopOfStack--;
-            *pxTopOfStack = 0x22222222;
-            pxTopOfStack--;
-        }
+    {
+        pxTopOfStack--;
+        *pxTopOfStack = 0xffffffff; /* r15. */
+        pxTopOfStack--;
+        *pxTopOfStack = 0xeeeeeeee;
+        pxTopOfStack--;
+        *pxTopOfStack = 0xdddddddd;
+        pxTopOfStack--;
+        *pxTopOfStack = 0xcccccccc;
+        pxTopOfStack--;
+        *pxTopOfStack = 0xbbbbbbbb;
+        pxTopOfStack--;
+        *pxTopOfStack = 0xaaaaaaaa;
+        pxTopOfStack--;
+        *pxTopOfStack = 0x99999999;
+        pxTopOfStack--;
+        *pxTopOfStack = 0x88888888;
+        pxTopOfStack--;
+        *pxTopOfStack = 0x77777777;
+        pxTopOfStack--;
+        *pxTopOfStack = 0x66666666;
+        pxTopOfStack--;
+        *pxTopOfStack = 0x55555555;
+        pxTopOfStack--;
+        *pxTopOfStack = 0x44444444;
+        pxTopOfStack--;
+        *pxTopOfStack = 0x33333333;
+        pxTopOfStack--;
+        *pxTopOfStack = 0x22222222;
+        pxTopOfStack--;
+    }
     #else /* ifdef USE_FULL_REGISTER_INITIALISATION */
-        {
-            pxTopOfStack -= 15;
-        }
+    {
+        pxTopOfStack -= 15;
+    }
     #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */
 
     *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
@@ -208,73 +208,73 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
     *pxTopOfStack = 0x66666666; /* Accumulator 0. */
 
     #if ( configUSE_TASK_DPFPU_SUPPORT == 1 )
-        {
-            /* The task will start without a DPFPU context.  A task that
-             * uses the DPFPU hardware must call vPortTaskUsesDPFPU() before
-             * executing any floating point instructions. */
-            pxTopOfStack--;
-            *pxTopOfStack = portNO_DPFPU_CONTEXT;
-        }
+    {
+        /* The task will start without a DPFPU context.  A task that
+         * uses the DPFPU hardware must call vPortTaskUsesDPFPU() before
+         * executing any floating point instructions. */
+        pxTopOfStack--;
+        *pxTopOfStack = portNO_DPFPU_CONTEXT;
+    }
     #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 )
+    {
+        /* The task will start with a DPFPU context.  Leave enough
+         * space for the registers - and ensure they are initialised if desired. */
+        #ifdef USE_FULL_REGISTER_INITIALISATION
         {
-            /* The task will start with a DPFPU context.  Leave enough
-             * space for the registers - and ensure they are initialised if desired. */
-            #ifdef USE_FULL_REGISTER_INITIALISATION
-                {
-                    pxTopOfStack -= 2;
-                    *(double *)pxTopOfStack = 1515.1515; /* DR15. */
-                    pxTopOfStack -= 2;
-                    *(double *)pxTopOfStack = 1414.1414; /* DR14. */
-                    pxTopOfStack -= 2;
-                    *(double *)pxTopOfStack = 1313.1313; /* DR13. */
-                    pxTopOfStack -= 2;
-                    *(double *)pxTopOfStack = 1212.1212; /* DR12. */
-                    pxTopOfStack -= 2;
-                    *(double *)pxTopOfStack = 1111.1111; /* DR11. */
-                    pxTopOfStack -= 2;
-                    *(double *)pxTopOfStack = 1010.1010; /* DR10. */
-                    pxTopOfStack -= 2;
-                    *(double *)pxTopOfStack =  909.0909; /* DR9. */
-                    pxTopOfStack -= 2;
-                    *(double *)pxTopOfStack =  808.0808; /* DR8. */
-                    pxTopOfStack -= 2;
-                    *(double *)pxTopOfStack =  707.0707; /* DR7. */
-                    pxTopOfStack -= 2;
-                    *(double *)pxTopOfStack =  606.0606; /* DR6. */
-                    pxTopOfStack -= 2;
-                    *(double *)pxTopOfStack =  505.0505; /* DR5. */
-                    pxTopOfStack -= 2;
-                    *(double *)pxTopOfStack =  404.0404; /* DR4. */
-                    pxTopOfStack -= 2;
-                    *(double *)pxTopOfStack =  303.0303; /* DR3. */
-                    pxTopOfStack -= 2;
-                    *(double *)pxTopOfStack =  202.0202; /* DR2. */
-                    pxTopOfStack -= 2;
-                    *(double *)pxTopOfStack =  101.0101; /* DR1. */
-                    pxTopOfStack -= 2;
-                    *(double *)pxTopOfStack = 9876.54321;/* DR0. */
-                }
-            #else /* ifdef USE_FULL_REGISTER_INITIALISATION */
-                {
-                    pxTopOfStack -= portDPFPU_DATA_REGISTER_WORDS;
-                    memset( pxTopOfStack, 0x00, portDPFPU_DATA_REGISTER_WORDS * sizeof( StackType_t ) );
-                }
-            #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */
-            pxTopOfStack--;
-            *pxTopOfStack = portINITIAL_DECNT; /* DECNT. */
-            pxTopOfStack--;
-            *pxTopOfStack = portINITIAL_DCMR;  /* DCMR. */
-            pxTopOfStack--;
-            *pxTopOfStack = portINITIAL_DPSW;  /* DPSW. */
+            pxTopOfStack -= 2;
+            *( double * ) pxTopOfStack = 1515.1515;  /* DR15. */
+            pxTopOfStack -= 2;
+            *( double * ) pxTopOfStack = 1414.1414;  /* DR14. */
+            pxTopOfStack -= 2;
+            *( double * ) pxTopOfStack = 1313.1313;  /* DR13. */
+            pxTopOfStack -= 2;
+            *( double * ) pxTopOfStack = 1212.1212;  /* DR12. */
+            pxTopOfStack -= 2;
+            *( double * ) pxTopOfStack = 1111.1111;  /* DR11. */
+            pxTopOfStack -= 2;
+            *( double * ) pxTopOfStack = 1010.1010;  /* DR10. */
+            pxTopOfStack -= 2;
+            *( double * ) pxTopOfStack = 909.0909;   /* DR9. */
+            pxTopOfStack -= 2;
+            *( double * ) pxTopOfStack = 808.0808;   /* DR8. */
+            pxTopOfStack -= 2;
+            *( double * ) pxTopOfStack = 707.0707;   /* DR7. */
+            pxTopOfStack -= 2;
+            *( double * ) pxTopOfStack = 606.0606;   /* DR6. */
+            pxTopOfStack -= 2;
+            *( double * ) pxTopOfStack = 505.0505;   /* DR5. */
+            pxTopOfStack -= 2;
+            *( double * ) pxTopOfStack = 404.0404;   /* DR4. */
+            pxTopOfStack -= 2;
+            *( double * ) pxTopOfStack = 303.0303;   /* DR3. */
+            pxTopOfStack -= 2;
+            *( double * ) pxTopOfStack = 202.0202;   /* DR2. */
+            pxTopOfStack -= 2;
+            *( double * ) pxTopOfStack = 101.0101;   /* DR1. */
+            pxTopOfStack -= 2;
+            *( double * ) pxTopOfStack = 9876.54321; /* DR0. */
         }
+        #else /* ifdef USE_FULL_REGISTER_INITIALISATION */
+        {
+            pxTopOfStack -= portDPFPU_DATA_REGISTER_WORDS;
+            memset( pxTopOfStack, 0x00, portDPFPU_DATA_REGISTER_WORDS * sizeof( StackType_t ) );
+        }
+        #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */
+        pxTopOfStack--;
+        *pxTopOfStack = portINITIAL_DECNT; /* DECNT. */
+        pxTopOfStack--;
+        *pxTopOfStack = portINITIAL_DCMR;  /* DCMR. */
+        pxTopOfStack--;
+        *pxTopOfStack = portINITIAL_DPSW;  /* DPSW. */
+    }
     #elif ( configUSE_TASK_DPFPU_SUPPORT == 0 )
-        {
-            /* Omit DPFPU support. */
-        }
+    {
+        /* Omit DPFPU support. */
+    }
     #else /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */
-        {
-            #error Invalid configUSE_TASK_DPFPU_SUPPORT setting - configUSE_TASK_DPFPU_SUPPORT must be set to 0, 1, 2, or left undefined.
-        }
+    {
+        #error Invalid configUSE_TASK_DPFPU_SUPPORT setting - configUSE_TASK_DPFPU_SUPPORT must be set to 0, 1, 2, or left undefined.
+    }
     #endif /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */
 
     return pxTopOfStack;
@@ -339,14 +339,14 @@ static void prvStartFirstTask( void )
         /* When starting the scheduler there is nothing that needs moving to the
          * interrupt stack because the function is not called from an interrupt.
          * Just ensure the current stack is the user stack. */
-        "SETPSW     U                       \n"\
+        "SETPSW     U                       \n" \
 
 
         /* Obtain the location of the stack associated with which ever task
          * pxCurrentTCB is currently pointing to. */
-        "MOV.L      #_pxCurrentTCB, R15     \n"\
-        "MOV.L      [R15], R15              \n"\
-        "MOV.L      [R15], R0               \n"\
+        "MOV.L      #_pxCurrentTCB, R15     \n" \
+        "MOV.L      [R15], R15              \n" \
+        "MOV.L      [R15], R0               \n" \
 
 
         /* Restore the registers from the stack of the task pointed to by
@@ -356,53 +356,52 @@ static void prvStartFirstTask( void )
 
             /* The restored ulPortTaskHasDPFPUContext is to be zero here.
              * So, it is never necessary to restore the DPFPU context here. */
-            "POP        R15                                 \n"\
-            "MOV.L      #_ulPortTaskHasDPFPUContext, R14    \n"\
-            "MOV.L      R15, [R14]                          \n"\
+            "POP        R15                                 \n" \
+            "MOV.L      #_ulPortTaskHasDPFPUContext, R14    \n" \
+            "MOV.L      R15, [R14]                          \n" \
 
         #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 )
-
             /* Restore the DPFPU context. */
-            "DPOPM.L    DPSW-DECNT              \n"\
-            "DPOPM.D    DR0-DR15                \n"\
+            "DPOPM.L    DPSW-DECNT              \n" \
+            "DPOPM.D    DR0-DR15                \n" \
 
         #endif /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */
 
-        "POP        R15                     \n"\
+        "POP        R15                     \n" \
 
         /* Accumulator low 32 bits. */
-        "MVTACLO    R15, A0                 \n"\
-        "POP        R15                     \n"\
+        "MVTACLO    R15, A0                 \n" \
+        "POP        R15                     \n" \
 
         /* Accumulator high 32 bits. */
-        "MVTACHI    R15, A0                 \n"\
-        "POP        R15                     \n"\
+        "MVTACHI    R15, A0                 \n" \
+        "POP        R15                     \n" \
 
         /* Accumulator guard. */
-        "MVTACGU    R15, A0                 \n"\
-        "POP        R15                     \n"\
+        "MVTACGU    R15, A0                 \n" \
+        "POP        R15                     \n" \
 
         /* Accumulator low 32 bits. */
-        "MVTACLO    R15, A1                 \n"\
-        "POP        R15                     \n"\
+        "MVTACLO    R15, A1                 \n" \
+        "POP        R15                     \n" \
 
         /* Accumulator high 32 bits. */
-        "MVTACHI    R15, A1                 \n"\
-        "POP        R15                     \n"\
+        "MVTACHI    R15, A1                 \n" \
+        "POP        R15                     \n" \
 
         /* Accumulator guard. */
-        "MVTACGU    R15, A1                 \n"\
-        "POP        R15                     \n"\
+        "MVTACGU    R15, A1                 \n" \
+        "POP        R15                     \n" \
 
         /* Floating point status word. */
-        "MVTC       R15, FPSW               \n"\
+        "MVTC       R15, FPSW               \n" \
 
         /* R1 to R15 - R0 is not included as it is the SP. */
-        "POPM       R1-R15                  \n"\
+        "POPM       R1-R15                  \n" \
 
         /* This pops the remaining registers. */
-        "RTE                                \n"\
-        "NOP                                \n"\
+        "RTE                                \n" \
+        "NOP                                \n" \
         "NOP                                \n"
     );
 }
@@ -413,100 +412,99 @@ void vSoftwareInterruptISR( void )
     __asm volatile
     (
         /* Re-enable interrupts. */
-        "SETPSW     I                           \n"\
+        "SETPSW     I                           \n" \
 
 
         /* Move the data that was automatically pushed onto the interrupt stack when
          * the interrupt occurred from the interrupt stack to the user stack.
          *
          * R15 is saved before it is clobbered. */
-        "PUSH.L     R15                         \n"\
+        "PUSH.L     R15                         \n" \
 
         /* Read the user stack pointer. */
-        "MVFC       USP, R15                    \n"\
+        "MVFC       USP, R15                    \n" \
 
         /* Move the address down to the data being moved. */
-        "SUB        #12, R15                    \n"\
-        "MVTC       R15, USP                    \n"\
+        "SUB        #12, R15                    \n" \
+        "MVTC       R15, USP                    \n" \
 
         /* Copy the data across, R15, then PC, then PSW. */
-        "MOV.L      [ R0 ], [ R15 ]             \n"\
-        "MOV.L      4[ R0 ], 4[ R15 ]           \n"\
-        "MOV.L      8[ R0 ], 8[ R15 ]           \n"\
+        "MOV.L      [ R0 ], [ R15 ]             \n" \
+        "MOV.L      4[ R0 ], 4[ R15 ]           \n" \
+        "MOV.L      8[ R0 ], 8[ R15 ]           \n" \
 
         /* Move the interrupt stack pointer to its new correct position. */
-        "ADD        #12, R0                     \n"\
+        "ADD        #12, R0                     \n" \
 
         /* All the rest of the registers are saved directly to the user stack. */
-        "SETPSW     U                           \n"\
+        "SETPSW     U                           \n" \
 
         /* Save the rest of the general registers (R15 has been saved already). */
-        "PUSHM      R1-R14                      \n"\
+        "PUSHM      R1-R14                      \n" \
 
         /* Save the FPSW and accumulators. */
-        "MVFC       FPSW, R15                   \n"\
-        "PUSH.L     R15                         \n"\
-        "MVFACGU    #0, A1, R15                 \n"\
-        "PUSH.L     R15                         \n"\
-        "MVFACHI    #0, A1, R15                 \n"\
-        "PUSH.L     R15                         \n"\
+        "MVFC       FPSW, R15                   \n"                       \
+        "PUSH.L     R15                         \n"                       \
+        "MVFACGU    #0, A1, R15                 \n"                       \
+        "PUSH.L     R15                         \n"                       \
+        "MVFACHI    #0, A1, R15                 \n"                       \
+        "PUSH.L     R15                         \n"                       \
         "MVFACLO    #0, A1, R15                 \n" /* Low order word. */ \
-        "PUSH.L     R15                         \n"\
-        "MVFACGU    #0, A0, R15                 \n"\
-        "PUSH.L     R15                         \n"\
-        "MVFACHI    #0, A0, R15                 \n"\
-        "PUSH.L     R15                         \n"\
+        "PUSH.L     R15                         \n"                       \
+        "MVFACGU    #0, A0, R15                 \n"                       \
+        "PUSH.L     R15                         \n"                       \
+        "MVFACHI    #0, A0, R15                 \n"                       \
+        "PUSH.L     R15                         \n"                       \
         "MVFACLO    #0, A0, R15                 \n" /* Low order word. */ \
-        "PUSH.L     R15                         \n"\
+        "PUSH.L     R15                         \n"                       \
 
         #if ( configUSE_TASK_DPFPU_SUPPORT == 1 )
 
             /* Does the task have a DPFPU context that needs saving?  If
              * ulPortTaskHasDPFPUContext is 0 then no. */
-            "MOV.L      #_ulPortTaskHasDPFPUContext, R15    \n"\
-            "MOV.L      [R15], R15                          \n"\
-            "CMP        #0, R15                             \n"\
+            "MOV.L      #_ulPortTaskHasDPFPUContext, R15    \n" \
+            "MOV.L      [R15], R15                          \n" \
+            "CMP        #0, R15                             \n" \
 
             /* Save the DPFPU context, if any. */
-            "BEQ.B      ?+                          \n"\
-            "DPUSHM.D   DR0-DR15                    \n"\
-            "DPUSHM.L   DPSW-DECNT                  \n"\
-            "?:                                     \n"\
+            "BEQ.B      ?+                          \n" \
+            "DPUSHM.D   DR0-DR15                    \n" \
+            "DPUSHM.L   DPSW-DECNT                  \n" \
+            "?:                                     \n" \
 
             /* Save ulPortTaskHasDPFPUContext itself. */
-            "PUSH.L     R15                         \n"\
+            "PUSH.L     R15                         \n" \
 
         #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 )
-
             /* Save the DPFPU context, always. */
-            "DPUSHM.D   DR0-DR15                    \n"\
-            "DPUSHM.L   DPSW-DECNT                  \n"\
+            "DPUSHM.D   DR0-DR15                    \n" \
+            "DPUSHM.L   DPSW-DECNT                  \n" \
 
         #endif /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */
 
 
         /* Save the stack pointer to the TCB. */
-        "MOV.L      #_pxCurrentTCB, R15         \n"\
-        "MOV.L      [ R15 ], R15                \n"\
-        "MOV.L      R0, [ R15 ]                 \n"\
+        "MOV.L      #_pxCurrentTCB, R15         \n" \
+        "MOV.L      [ R15 ], R15                \n" \
+        "MOV.L      R0, [ R15 ]                 \n" \
 
 
         /* Ensure the interrupt mask is set to the syscall priority while the kernel
          * structures are being accessed. */
-        "MVTIPL     %0                          \n"\
+        "MVTIPL     %0                          \n" \
 
         /* Select the next task to run. */
-        "BSR.A      _vTaskSwitchContext         \n"\
+        "BSR.A      _vTaskSwitchContext         \n" \
 
         /* Reset the interrupt mask as no more data structure access is required. */
-        "MVTIPL     %1                          \n"\
+        "MVTIPL     %1                          \n" \
 
 
         /* Load the stack pointer of the task that is now selected as the Running
          * state task from its TCB. */
-        "MOV.L      #_pxCurrentTCB,R15          \n"\
-        "MOV.L      [ R15 ], R15                \n"\
-        "MOV.L      [ R15 ], R0                 \n"\
+        "MOV.L      #_pxCurrentTCB,R15          \n" \
+        "MOV.L      [ R15 ], R15                \n" \
+        "MOV.L      [ R15 ], R0                 \n" \
 
 
         /* Restore the context of the new task.  The PSW (Program Status Word) and
@@ -516,54 +514,53 @@ void vSoftwareInterruptISR( void )
 
             /* Is there a DPFPU context to restore?  If the restored
              * ulPortTaskHasDPFPUContext is zero then no. */
-            "POP        R15                                 \n"\
-            "MOV.L      #_ulPortTaskHasDPFPUContext, R14    \n"\
-            "MOV.L      R15, [R14]                          \n"\
-            "CMP        #0, R15                             \n"\
+            "POP        R15                                 \n" \
+            "MOV.L      #_ulPortTaskHasDPFPUContext, R14    \n" \
+            "MOV.L      R15, [R14]                          \n" \
+            "CMP        #0, R15                             \n" \
 
             /* Restore the DPFPU context, if any. */
-            "BEQ.B      ?+                          \n"\
-            "DPOPM.L    DPSW-DECNT                  \n"\
-            "DPOPM.D    DR0-DR15                    \n"\
-            "?:                                     \n"\
+            "BEQ.B      ?+                          \n" \
+            "DPOPM.L    DPSW-DECNT                  \n" \
+            "DPOPM.D    DR0-DR15                    \n" \
+            "?:                                     \n" \
 
         #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 )
-
             /* Restore the DPFPU context, always. */
-            "DPOPM.L    DPSW-DECNT                  \n"\
-            "DPOPM.D    DR0-DR15                    \n"\
+            "DPOPM.L    DPSW-DECNT                  \n" \
+            "DPOPM.D    DR0-DR15                    \n" \
 
         #endif /* if( configUSE_TASK_DPFPU_SUPPORT == 1 ) */
 
-        "POP        R15                         \n"\
+        "POP        R15                         \n" \
 
         /* Accumulator low 32 bits. */
-        "MVTACLO    R15, A0                     \n"\
-        "POP        R15                         \n"\
+        "MVTACLO    R15, A0                     \n" \
+        "POP        R15                         \n" \
 
         /* Accumulator high 32 bits. */
-        "MVTACHI    R15, A0                     \n"\
-        "POP        R15                         \n"\
+        "MVTACHI    R15, A0                     \n" \
+        "POP        R15                         \n" \
 
         /* Accumulator guard. */
-        "MVTACGU    R15, A0                     \n"\
-        "POP        R15                         \n"\
+        "MVTACGU    R15, A0                     \n" \
+        "POP        R15                         \n" \
 
         /* Accumulator low 32 bits. */
-        "MVTACLO    R15, A1                     \n"\
-        "POP        R15                         \n"\
+        "MVTACLO    R15, A1                     \n" \
+        "POP        R15                         \n" \
 
         /* Accumulator high 32 bits. */
-        "MVTACHI    R15, A1                     \n"\
-        "POP        R15                         \n"\
+        "MVTACHI    R15, A1                     \n" \
+        "POP        R15                         \n" \
 
         /* Accumulator guard. */
-        "MVTACGU    R15, A1                     \n"\
-        "POP        R15                         \n"\
-        "MVTC       R15, FPSW                   \n"\
-        "POPM       R1-R15                      \n"\
-        "RTE                                    \n"\
-        "NOP                                    \n"\
+        "MVTACGU    R15, A1                     \n" \
+        "POP        R15                         \n" \
+        "MVTC       R15, FPSW                   \n" \
+        "POPM       R1-R15                      \n" \
+        "RTE                                    \n" \
+        "NOP                                    \n" \
         "NOP                                      "
         ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ), "i" ( configKERNEL_INTERRUPT_PRIORITY )
     );
@@ -573,7 +570,7 @@ void vSoftwareInterruptISR( void )
 void vTickISR( void )
 {
     /* Re-enabled interrupts. */
-    __asm volatile ( "SETPSW    I");
+    __asm volatile ( "SETPSW    I" );
 
     /* Increment the tick, and perform any processing the new tick value
      * necessitates.  Ensure IPL is at the max syscall value first. */
@@ -592,8 +589,8 @@ uint32_t ulPortGetIPL( void )
 {
     __asm volatile
     (
-        "MVFC   PSW, R1         \n"\
-        "SHLR   #24, R1         \n"\
+        "MVFC   PSW, R1         \n" \
+        "SHLR   #24, R1         \n" \
         "RTS                      "
     );
 
@@ -609,13 +606,13 @@ void vPortSetIPL( uint32_t ulNewIPL )
 
     __asm volatile
     (
-        "PUSH   R5              \n"\
-        "MVFC   PSW, R5         \n"\
-        "SHLL   #24, R1         \n"\
-        "AND    #-0F000001H, R5 \n"\
-        "OR     R1, R5          \n"\
-        "MVTC   R5, PSW         \n"\
-        "POP    R5              \n"\
+        "PUSH   R5              \n" \
+        "MVFC   PSW, R5         \n" \
+        "SHLL   #24, R1         \n" \
+        "AND    #-0F000001H, R5 \n" \
+        "OR     R1, R5          \n" \
+        "MVTC   R5, PSW         \n" \
+        "POP    R5              \n" \
         "RTS                      "
     );
 }
diff --git a/portable/GCC/RX700v3_DPFPU/portmacro.h b/portable/GCC/RX700v3_DPFPU/portmacro.h
index 881610515..8e67724e9 100644
--- a/portable/GCC/RX700v3_DPFPU/portmacro.h
+++ b/portable/GCC/RX700v3_DPFPU/portmacro.h
@@ -28,7 +28,7 @@
 
 
 #ifndef PORTMACRO_H
-    #define PORTMACRO_H
+#define PORTMACRO_H
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
@@ -48,9 +48,9 @@
 
 /* When the FIT configurator or the Smart Configurator is used, platform.h has to be
  * used. */
-    #ifndef configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H
-        #define configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H 0
-    #endif
+#ifndef configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H
+    #define configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H    0
+#endif
 
 /* If configUSE_TASK_DPFPU_SUPPORT is set to 1 (or undefined) then each task will
  * be created without a DPFPU context, and a task must call vTaskUsesDPFPU() before
@@ -58,74 +58,74 @@
  * tasks are created with a DPFPU context by default, and calling vTaskUsesDPFPU() has
  * no effect.  If configUSE_TASK_DPFPU_SUPPORT is set to 0 then tasks never take care
  * of any DPFPU context (even if DPFPU registers are used). */
-    #ifndef configUSE_TASK_DPFPU_SUPPORT
-        #define configUSE_TASK_DPFPU_SUPPORT 1
-    #endif
+#ifndef configUSE_TASK_DPFPU_SUPPORT
+    #define configUSE_TASK_DPFPU_SUPPORT    1
+#endif
 
 /*-----------------------------------------------------------*/
 
 /* Type definitions - these are a bit legacy and not really used now, other than
  * portSTACK_TYPE and portBASE_TYPE. */
-    #define portCHAR          char
-    #define portFLOAT         float
-    #define portDOUBLE        double
-    #define portLONG          long
-    #define portSHORT         short
-    #define portSTACK_TYPE    uint32_t
-    #define portBASE_TYPE     long
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-    typedef portSTACK_TYPE   StackType_t;
-    typedef long             BaseType_t;
-    typedef unsigned long    UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
-    #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-        typedef uint16_t     TickType_t;
-        #define portMAX_DELAY              ( TickType_t ) 0xffff
-    #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-        typedef uint32_t     TickType_t;
-        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
  * not need to be guarded with a critical section. */
-        #define portTICK_TYPE_IS_ATOMIC    1
-    #else
-        #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
-    #endif
+    #define portTICK_TYPE_IS_ATOMIC    1
+#else
+    #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+#endif
 
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-    #define portBYTE_ALIGNMENT    8     /* Could make four, according to manual. */
-    #define portSTACK_GROWTH      -1
-    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-    #define portNOP()    __asm volatile ( "NOP" )
+#define portBYTE_ALIGNMENT    8         /* Could make four, according to manual. */
+#define portSTACK_GROWTH      -1
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()    __asm volatile ( "NOP" )
 
 /* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;"
  * where portITU_SWINTR is the location of the software interrupt register
  * (0x000872E0).  Don't rely on the assembler to select a register, so instead
  * save and restore clobbered registers manually. */
-    #define portYIELD()           \
-    __asm volatile                \
-    (                             \
-        "PUSH.L R10                 \n"\
-        "MOV.L  #0x872E0, R10       \n"\
-        "MOV.B  #0x1, [R10]         \n"\
-        "CMP    [R10].UB, R10       \n"\
-        "POP    R10                 \n"\
-        :::"cc"                     \
+#define portYIELD()                     \
+    __asm volatile                      \
+    (                                   \
+        "PUSH.L R10                 \n" \
+        "MOV.L  #0x872E0, R10       \n" \
+        "MOV.B  #0x1, [R10]         \n" \
+        "CMP    [R10].UB, R10       \n" \
+        "POP    R10                 \n" \
+        ::: "cc"                        \
     )
 
-    #define portYIELD_FROM_ISR( x )                           do { if( ( x ) != pdFALSE ) portYIELD(); } while( 0 )
+#define portYIELD_FROM_ISR( x )    do { if( ( x ) != pdFALSE ) portYIELD( ); } while( 0 )
 
 /* Workaround to reduce errors/warnings caused by e2 studio CDT's INDEXER and CODAN. */
-    #ifdef __CDT_PARSER__
+#ifdef __CDT_PARSER__
     #ifndef __asm
-    #define __asm asm
+        #define __asm    asm
     #endif
     #ifndef __attribute__
-    #define __attribute__( ... )
-    #endif
+        #define __attribute__( ... )
     #endif
+#endif
 
 /* These macros should not be called directly, but through the
  * taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
@@ -136,34 +136,34 @@
  * functions are those that end in FromISR.  FreeRTOS maintains a separate
  * interrupt API to ensure API function and interrupt entry is as fast and as
  * simple as possible. */
-    #define portENABLE_INTERRUPTS()                           __asm volatile ( "MVTIPL  #0")
-    #ifdef configASSERT
-        #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
-        #define portDISABLE_INTERRUPTS()                      if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile ( "MVTIPL  %0"::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
-    #else
-        #define portDISABLE_INTERRUPTS()                      __asm volatile ( "MVTIPL  %0"::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
-    #endif
+#define portENABLE_INTERRUPTS()                           __asm volatile ( "MVTIPL  #0" )
+#ifdef configASSERT
+    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+    #define portDISABLE_INTERRUPTS()                      if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile( "MVTIPL  %0" ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+#else
+    #define portDISABLE_INTERRUPTS()                      __asm volatile ( "MVTIPL  %0" ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+#endif
 
 /* Critical nesting counts are stored in the TCB. */
-    #define portCRITICAL_NESTING_IN_TCB    ( 1 )
+#define portCRITICAL_NESTING_IN_TCB    ( 1 )
 
 /* The critical nesting functions defined within tasks.c. */
-    extern void vTaskEnterCritical( void );
-    extern void vTaskExitCritical( void );
-    #define portENTER_CRITICAL()    vTaskEnterCritical()
-    #define portEXIT_CRITICAL()     vTaskExitCritical()
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+#define portENTER_CRITICAL()    vTaskEnterCritical()
+#define portEXIT_CRITICAL()     vTaskExitCritical()
 
 /* As this port allows interrupt nesting... */
-    uint32_t ulPortGetIPL( void ) __attribute__( ( naked ) );
-    void vPortSetIPL( uint32_t ulNewIPL ) __attribute__( ( naked ) );
-    #define portSET_INTERRUPT_MASK_FROM_ISR()                              ulPortGetIPL(); portDISABLE_INTERRUPTS()
-    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus )    vPortSetIPL( uxSavedInterruptStatus )
+uint32_t ulPortGetIPL( void ) __attribute__( ( naked ) );
+void vPortSetIPL( uint32_t ulNewIPL ) __attribute__( ( naked ) );
+#define portSET_INTERRUPT_MASK_FROM_ISR()                              ulPortGetIPL(); portDISABLE_INTERRUPTS()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus )    vPortSetIPL( uxSavedInterruptStatus )
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
-    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
 /*-----------------------------------------------------------*/
 
@@ -172,17 +172,18 @@
  * themselves a DPFPU context before using any DPFPU instructions.  If
  * configUSE_TASK_DPFPU_SUPPORT is set to 2 then all tasks will have a DPFPU context
  * by default. */
-    #if( configUSE_TASK_DPFPU_SUPPORT == 1 )
-        void vPortTaskUsesDPFPU( void );
-    #else
+#if ( configUSE_TASK_DPFPU_SUPPORT == 1 )
+    void vPortTaskUsesDPFPU( void );
+#else
+
 /* Each task has a DPFPU context already, so define this function away to
  * nothing to prevent it being called accidentally. */
-        #define vPortTaskUsesDPFPU()
-    #endif
-    #define portTASK_USES_DPFPU() vPortTaskUsesDPFPU()
+    #define vPortTaskUsesDPFPU()
+#endif
+#define portTASK_USES_DPFPU()             vPortTaskUsesDPFPU()
 
 /* Definition to allow compatibility with existing FreeRTOS Demo using flop.c. */
-    #define portTASK_USES_FLOATING_POINT() vPortTaskUsesDPFPU()
+#define portTASK_USES_FLOATING_POINT()    vPortTaskUsesDPFPU()
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/GCC/STR75x/port.c b/portable/GCC/STR75x/port.c
index bd3b3ef78..09fab1897 100644
--- a/portable/GCC/STR75x/port.c
+++ b/portable/GCC/STR75x/port.c
@@ -27,9 +27,9 @@
  */
 
 /*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the ST STR75x ARM7
- * port.
- *----------------------------------------------------------*/
+* Implementation of functions defined in portable.h for the ST STR75x ARM7
+* port.
+*----------------------------------------------------------*/
 
 /* Library includes. */
 #include "75x_tb.h"
@@ -40,15 +40,15 @@
 #include "task.h"
 
 /* Constants required to setup the initial stack. */
-#define portINITIAL_SPSR                ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
-#define portTHUMB_MODE_BIT              ( ( StackType_t ) 0x20 )
-#define portINSTRUCTION_SIZE            ( ( StackType_t ) 4 )
+#define portINITIAL_SPSR           ( ( StackType_t ) 0x1f )      /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT         ( ( StackType_t ) 0x20 )
+#define portINSTRUCTION_SIZE       ( ( StackType_t ) 4 )
 
 /* Constants required to handle critical sections. */
-#define portNO_CRITICAL_NESTING         ( ( uint32_t ) 0 )
+#define portNO_CRITICAL_NESTING    ( ( uint32_t ) 0 )
 
 /* Prescale used on the timer clock when calculating the tick period. */
-#define portPRESCALE 20
+#define portPRESCALE               20
 
 
 /*-----------------------------------------------------------*/
@@ -64,56 +64,58 @@ static void prvSetupTimerInterrupt( void );
  *
  * See header file for description.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
-StackType_t *pxOriginalTOS;
+    StackType_t * pxOriginalTOS;
 
     pxOriginalTOS = pxTopOfStack;
 
     /* To ensure asserts in tasks.c don't fail, although in this case the assert
-    is not really required. */
+     * is not really required. */
     pxTopOfStack--;
 
     /* Setup the initial stack of the task.  The stack is set exactly as
-    expected by the portRESTORE_CONTEXT() macro. */
+     * expected by the portRESTORE_CONTEXT() macro. */
 
     /* First on the stack is the return address - which in this case is the
-    start of the task.  The offset is added to make the return address appear
-    as it would within an IRQ ISR. */
+     * start of the task.  The offset is added to make the return address appear
+     * as it would within an IRQ ISR. */
     *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
     pxTopOfStack--;
 
-    *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */
+    *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa;    /* R14 */
     pxTopOfStack--;
     *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
+    *pxTopOfStack = ( StackType_t ) 0x12121212;    /* R12 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
+    *pxTopOfStack = ( StackType_t ) 0x11111111;    /* R11 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
+    *pxTopOfStack = ( StackType_t ) 0x10101010;    /* R10 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
+    *pxTopOfStack = ( StackType_t ) 0x09090909;    /* R9 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
+    *pxTopOfStack = ( StackType_t ) 0x08080808;    /* R8 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
+    *pxTopOfStack = ( StackType_t ) 0x07070707;    /* R7 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
+    *pxTopOfStack = ( StackType_t ) 0x06060606;    /* R6 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
+    *pxTopOfStack = ( StackType_t ) 0x05050505;    /* R5 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
+    *pxTopOfStack = ( StackType_t ) 0x04040404;    /* R4 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
+    *pxTopOfStack = ( StackType_t ) 0x03030303;    /* R3 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
+    *pxTopOfStack = ( StackType_t ) 0x02020202;    /* R2 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
+    *pxTopOfStack = ( StackType_t ) 0x01010101;    /* R1 */
     pxTopOfStack--;
 
     /* When the task starts is will expect to find the function parameter in
-    R0. */
+     * R0. */
     *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
     pxTopOfStack--;
 
@@ -130,8 +132,8 @@ StackType_t *pxOriginalTOS;
     pxTopOfStack--;
 
     /* Interrupt flags cannot always be stored on the stack and will
-    instead be stored in a variable, which is then saved as part of the
-    tasks context. */
+     * instead be stored in a variable, which is then saved as part of the
+     * tasks context. */
     *pxTopOfStack = portNO_CRITICAL_NESTING;
 
     return pxTopOfStack;
@@ -140,10 +142,10 @@ StackType_t *pxOriginalTOS;
 
 BaseType_t xPortStartScheduler( void )
 {
-extern void vPortISRStartFirstTask( void );
+    extern void vPortISRStartFirstTask( void );
 
     /* Start the timer that generates the tick ISR.  Interrupts are disabled
-    here already. */
+     * here already. */
     prvSetupTimerInterrupt();
 
     /* Start the first task. */
@@ -157,35 +159,35 @@ extern void vPortISRStartFirstTask( void );
 void vPortEndScheduler( void )
 {
     /* It is unlikely that the ARM port will require this function as there
-    is nothing to return to.  */
+     * is nothing to return to.  */
 }
 /*-----------------------------------------------------------*/
 
 static void prvSetupTimerInterrupt( void )
 {
-EIC_IRQInitTypeDef  EIC_IRQInitStructure;
-TB_InitTypeDef      TB_InitStructure;
+    EIC_IRQInitTypeDef EIC_IRQInitStructure;
+    TB_InitTypeDef TB_InitStructure;
 
     /* Setup the EIC for the TB. */
     EIC_IRQInitStructure.EIC_IRQChannelCmd = ENABLE;
     EIC_IRQInitStructure.EIC_IRQChannel = TB_IRQChannel;
     EIC_IRQInitStructure.EIC_IRQChannelPriority = 1;
-    EIC_IRQInit(&EIC_IRQInitStructure);
+    EIC_IRQInit( &EIC_IRQInitStructure );
 
     /* Setup the TB for the generation of the tick interrupt. */
     TB_InitStructure.TB_Mode = TB_Mode_Timing;
     TB_InitStructure.TB_CounterMode = TB_CounterMode_Down;
     TB_InitStructure.TB_Prescaler = portPRESCALE - 1;
     TB_InitStructure.TB_AutoReload = ( ( configCPU_CLOCK_HZ / portPRESCALE ) / configTICK_RATE_HZ );
-    TB_Init(&TB_InitStructure);
+    TB_Init( &TB_InitStructure );
 
     /* Enable TB Update interrupt */
-    TB_ITConfig(TB_IT_Update, ENABLE);
+    TB_ITConfig( TB_IT_Update, ENABLE );
 
     /* Clear TB Update interrupt pending bit */
-    TB_ClearITPendingBit(TB_IT_Update);
+    TB_ClearITPendingBit( TB_IT_Update );
 
     /* Enable TB */
-    TB_Cmd(ENABLE);
+    TB_Cmd( ENABLE );
 }
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/STR75x/portISR.c b/portable/GCC/STR75x/portISR.c
index fd66e4cfd..569a6c7d3 100644
--- a/portable/GCC/STR75x/portISR.c
+++ b/portable/GCC/STR75x/portISR.c
@@ -28,20 +28,20 @@
 
 
 /*-----------------------------------------------------------
- * Components that can be compiled to either ARM or THUMB mode are
- * contained in port.c  The ISR routines, which can only be compiled
- * to ARM mode, are contained in this file.
- *----------------------------------------------------------*/
+* Components that can be compiled to either ARM or THUMB mode are
+* contained in port.c  The ISR routines, which can only be compiled
+* to ARM mode, are contained in this file.
+*----------------------------------------------------------*/
 
 /*
-*/
+ */
 
 /* Scheduler includes. */
 #include "FreeRTOS.h"
 #include "task.h"
 
 /* Constants required to handle critical sections. */
-#define portNO_CRITICAL_NESTING     ( ( uint32_t ) 0 )
+#define portNO_CRITICAL_NESTING    ( ( uint32_t ) 0 )
 
 volatile uint32_t ulCriticalNesting = 9999UL;
 
@@ -57,40 +57,40 @@ void vPortISRStartFirstTask( void );
 void vPortISRStartFirstTask( void )
 {
     /* Simply start the scheduler.  This is included here as it can only be
-    called from ARM mode. */
-    asm volatile (                                                      \
-    "LDR        R0, =pxCurrentTCB                               \n\t"   \
-    "LDR        R0, [R0]                                        \n\t"   \
-    "LDR        LR, [R0]                                        \n\t"   \
-                                                                        \
-    /* The critical nesting depth is the first item on the stack. */    \
-    /* Load it into the ulCriticalNesting variable. */                  \
-    "LDR        R0, =ulCriticalNesting                          \n\t"   \
-    "LDMFD  LR!, {R1}                                           \n\t"   \
-    "STR        R1, [R0]                                        \n\t"   \
-                                                                        \
-    /* Get the SPSR from the stack. */                                  \
-    "LDMFD  LR!, {R0}                                           \n\t"   \
-    "MSR        SPSR, R0                                        \n\t"   \
-                                                                        \
-    /* Restore all system mode registers for the task. */               \
-    "LDMFD  LR, {R0-R14}^                                       \n\t"   \
-    "NOP                                                        \n\t"   \
-                                                                        \
-    /* Restore the return address. */                                   \
-    "LDR        LR, [LR, #+60]                                  \n\t"   \
-                                                                        \
-    /* And return - correcting the offset in the LR to obtain the */    \
-    /* correct address. */                                              \
-    "SUBS PC, LR, #4                                            \n\t"   \
-    );
+     * called from ARM mode. */
+    asm volatile (                                                        \
+        "LDR        R0, =pxCurrentTCB                               \n\t" \
+        "LDR        R0, [R0]                                        \n\t" \
+        "LDR        LR, [R0]                                        \n\t" \
+                                                                          \
+        /* The critical nesting depth is the first item on the stack. */  \
+        /* Load it into the ulCriticalNesting variable. */                \
+        "LDR        R0, =ulCriticalNesting                          \n\t" \
+        "LDMFD  LR!, {R1}                                           \n\t" \
+        "STR        R1, [R0]                                        \n\t" \
+                                                                          \
+        /* Get the SPSR from the stack. */                                \
+        "LDMFD  LR!, {R0}                                           \n\t" \
+        "MSR        SPSR, R0                                        \n\t" \
+                                                                          \
+        /* Restore all system mode registers for the task. */             \
+        "LDMFD  LR, {R0-R14}^                                       \n\t" \
+        "NOP                                                        \n\t" \
+                                                                          \
+        /* Restore the return address. */                                 \
+        "LDR        LR, [LR, #+60]                                  \n\t" \
+                                                                          \
+        /* And return - correcting the offset in the LR to obtain the */  \
+        /* correct address. */                                            \
+        "SUBS PC, LR, #4                                            \n\t" \
+        );
 }
 /*-----------------------------------------------------------*/
 
 void vPortTickISR( void )
 {
     /* Increment the RTOS tick count, then look for the highest priority
-    task that is ready to run. */
+     * task that is ready to run. */
     if( xTaskIncrementTick() != pdFALSE )
     {
         vTaskSwitchContext();
@@ -110,29 +110,29 @@ void vPortTickISR( void )
  */
 #ifdef THUMB_INTERWORK
 
-    void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
-    void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
+    void vPortDisableInterruptsFromThumb( void ) __attribute__( ( naked ) );
+    void vPortEnableInterruptsFromThumb( void ) __attribute__( ( naked ) );
 
     void vPortDisableInterruptsFromThumb( void )
     {
         asm volatile (
-            "STMDB  SP!, {R0}       \n\t"   /* Push R0.                                 */
-            "MRS    R0, CPSR        \n\t"   /* Get CPSR.                                */
-            "ORR    R0, R0, #0xC0   \n\t"   /* Disable IRQ, FIQ.                        */
-            "MSR    CPSR, R0        \n\t"   /* Write back modified value.               */
-            "LDMIA  SP!, {R0}       \n\t"   /* Pop R0.                                  */
-            "BX     R14" );                 /* Return back to thumb.                    */
+            "STMDB  SP!, {R0}       \n\t" /* Push R0.                                 */
+            "MRS    R0, CPSR        \n\t" /* Get CPSR.                                */
+            "ORR    R0, R0, #0xC0   \n\t" /* Disable IRQ, FIQ.                        */
+            "MSR    CPSR, R0        \n\t" /* Write back modified value.               */
+            "LDMIA  SP!, {R0}       \n\t" /* Pop R0.                                  */
+            "BX     R14" );               /* Return back to thumb.                    */
     }
 
     void vPortEnableInterruptsFromThumb( void )
     {
         asm volatile (
-            "STMDB  SP!, {R0}       \n\t"   /* Push R0.                                 */
-            "MRS    R0, CPSR        \n\t"   /* Get CPSR.                                */
-            "BIC    R0, R0, #0xC0   \n\t"   /* Enable IRQ, FIQ.                         */
-            "MSR    CPSR, R0        \n\t"   /* Write back modified value.               */
-            "LDMIA  SP!, {R0}       \n\t"   /* Pop R0.                                  */
-            "BX     R14" );                 /* Return back to thumb.                    */
+            "STMDB  SP!, {R0}       \n\t" /* Push R0.                                 */
+            "MRS    R0, CPSR        \n\t" /* Get CPSR.                                */
+            "BIC    R0, R0, #0xC0   \n\t" /* Enable IRQ, FIQ.                         */
+            "MSR    CPSR, R0        \n\t" /* Write back modified value.               */
+            "LDMIA  SP!, {R0}       \n\t" /* Pop R0.                                  */
+            "BX     R14" );               /* Return back to thumb.                    */
     }
 
 #endif /* THUMB_INTERWORK */
@@ -142,15 +142,15 @@ void vPortEnterCritical( void )
 {
     /* Disable interrupts as per portDISABLE_INTERRUPTS();                          */
     asm volatile (
-        "STMDB  SP!, {R0}           \n\t"   /* Push R0.                             */
-        "MRS    R0, CPSR            \n\t"   /* Get CPSR.                            */
-        "ORR    R0, R0, #0xC0       \n\t"   /* Disable IRQ, FIQ.                    */
-        "MSR    CPSR, R0            \n\t"   /* Write back modified value.           */
-        "LDMIA  SP!, {R0}" );               /* Pop R0.                              */
+        "STMDB  SP!, {R0}           \n\t" /* Push R0.                             */
+        "MRS    R0, CPSR            \n\t" /* Get CPSR.                            */
+        "ORR    R0, R0, #0xC0       \n\t" /* Disable IRQ, FIQ.                    */
+        "MSR    CPSR, R0            \n\t" /* Write back modified value.           */
+        "LDMIA  SP!, {R0}" );             /* Pop R0.                              */
 
-    /* Now interrupts are disabled ulCriticalNesting can be accessed
-    directly.  Increment ulCriticalNesting to keep a count of how many times
-    portENTER_CRITICAL() has been called. */
+    /* Now that interrupts are disabled, ulCriticalNesting can be accessed
+     * directly.  Increment ulCriticalNesting to keep a count of how many times
+     * portENTER_CRITICAL() has been called. */
     ulCriticalNesting++;
 }
 /*-----------------------------------------------------------*/
@@ -163,16 +163,16 @@ void vPortExitCritical( void )
         ulCriticalNesting--;
 
         /* If the nesting level has reached zero then interrupts should be
-        re-enabled. */
+         * re-enabled. */
         if( ulCriticalNesting == portNO_CRITICAL_NESTING )
         {
             /* Enable interrupts as per portEXIT_CRITICAL().                    */
             asm volatile (
-                "STMDB  SP!, {R0}       \n\t"   /* Push R0.                     */
-                "MRS    R0, CPSR        \n\t"   /* Get CPSR.                    */
-                "BIC    R0, R0, #0xC0   \n\t"   /* Enable IRQ, FIQ.             */
-                "MSR    CPSR, R0        \n\t"   /* Write back modified value.   */
-                "LDMIA  SP!, {R0}" );           /* Pop R0.                      */
+                "STMDB  SP!, {R0}       \n\t" /* Push R0.                     */
+                "MRS    R0, CPSR        \n\t" /* Get CPSR.                    */
+                "BIC    R0, R0, #0xC0   \n\t" /* Enable IRQ, FIQ.             */
+                "MSR    CPSR, R0        \n\t" /* Write back modified value.   */
+                "LDMIA  SP!, {R0}" );         /* Pop R0.                      */
         }
     }
 }
diff --git a/portable/GCC/STR75x/portmacro.h b/portable/GCC/STR75x/portmacro.h
index 876783dcb..10c13c717 100644
--- a/portable/GCC/STR75x/portmacro.h
+++ b/portable/GCC/STR75x/portmacro.h
@@ -47,38 +47,39 @@
  */
 
 /* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint32_t
-#define portBASE_TYPE   long
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY ( TickType_t )    ( 0xFFFFFFFFUL )
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) ( 0xFFFFFFFFUL )
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portSTACK_GROWTH            ( -1 )
-#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT          8
-#define portYIELD()                 asm volatile ( "SWI 0" )
-#define portNOP()                   asm volatile ( "NOP" )
+#define portSTACK_GROWTH      ( -1 )
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT    8
+#define portYIELD()    asm volatile ( "SWI 0" )
+#define portNOP()      asm volatile ( "NOP" )
 /*-----------------------------------------------------------*/
 
 /* Critical section handling. */
+
 /*
  * The interrupt management utilities can only be called from ARM mode.  When
  * THUMB_INTERWORK is defined the utilities are defined as functions in
@@ -88,54 +89,54 @@ typedef unsigned long UBaseType_t;
 
 #ifdef THUMB_INTERWORK
 
-    extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
-    extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
+    extern void vPortDisableInterruptsFromThumb( void ) __attribute__( ( naked ) );
+    extern void vPortEnableInterruptsFromThumb( void ) __attribute__( ( naked ) );
 
     #define portDISABLE_INTERRUPTS()    vPortDisableInterruptsFromThumb()
     #define portENABLE_INTERRUPTS()     vPortEnableInterruptsFromThumb()
 
 #else
 
-    #define portDISABLE_INTERRUPTS()                                            \
-        asm volatile (                                                          \
-            "STMDB  SP!, {R0}       \n\t"   /* Push R0.                     */  \
-            "MRS    R0, CPSR        \n\t"   /* Get CPSR.                    */  \
-            "ORR    R0, R0, #0xC0   \n\t"   /* Disable IRQ, FIQ.            */  \
-            "MSR    CPSR, R0        \n\t"   /* Write back modified value.   */  \
-            "LDMIA  SP!, {R0}           " ) /* Pop R0.                      */
+    #define portDISABLE_INTERRUPTS()                                       \
+    asm volatile (                                                         \
+        "STMDB  SP!, {R0}       \n\t"   /* Push R0.                     */ \
+        "MRS    R0, CPSR        \n\t"   /* Get CPSR.                    */ \
+        "ORR    R0, R0, #0xC0   \n\t"   /* Disable IRQ, FIQ.            */ \
+        "MSR    CPSR, R0        \n\t"   /* Write back modified value.   */ \
+        "LDMIA  SP!, {R0}           " ) /* Pop R0.                      */
 
-    #define portENABLE_INTERRUPTS()                                             \
-        asm volatile (                                                          \
-            "STMDB  SP!, {R0}       \n\t"   /* Push R0.                     */  \
-            "MRS    R0, CPSR        \n\t"   /* Get CPSR.                    */  \
-            "BIC    R0, R0, #0xC0   \n\t"   /* Enable IRQ, FIQ.             */  \
-            "MSR    CPSR, R0        \n\t"   /* Write back modified value.   */  \
-            "LDMIA  SP!, {R0}           " ) /* Pop R0.                      */
+    #define portENABLE_INTERRUPTS()                                        \
+    asm volatile (                                                         \
+        "STMDB  SP!, {R0}       \n\t"   /* Push R0.                     */ \
+        "MRS    R0, CPSR        \n\t"   /* Get CPSR.                    */ \
+        "BIC    R0, R0, #0xC0   \n\t"   /* Enable IRQ, FIQ.             */ \
+        "MSR    CPSR, R0        \n\t"   /* Write back modified value.   */ \
+        "LDMIA  SP!, {R0}           " ) /* Pop R0.                      */
 
 #endif /* THUMB_INTERWORK */
 
 extern void vPortEnterCritical( void );
 extern void vPortExitCritical( void );
 
-#define portENTER_CRITICAL()        vPortEnterCritical();
-#define portEXIT_CRITICAL()         vPortExitCritical();
+#define portENTER_CRITICAL()    vPortEnterCritical();
+#define portEXIT_CRITICAL()     vPortExitCritical();
 /*-----------------------------------------------------------*/
 
 /* Task utilities. */
-#define portEND_SWITCHING_ISR( xSwitchRequired )    \
-{                                                   \
-extern void vTaskSwitchContext( void );             \
-                                                    \
-    if( xSwitchRequired )                           \
-    {                                               \
-        vTaskSwitchContext();                       \
-    }                                               \
-}
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+    {                                            \
+        extern void vTaskSwitchContext( void );  \
+                                                 \
+        if( xSwitchRequired )                    \
+        {                                        \
+            vTaskSwitchContext();                \
+        }                                        \
+    }
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/GCC/TriCore_1782/port.c b/portable/GCC/TriCore_1782/port.c
index 173fed0ad..f8f54922a 100644
--- a/portable/GCC/TriCore_1782/port.c
+++ b/portable/GCC/TriCore_1782/port.c
@@ -57,23 +57,23 @@
 #define portINITIAL_SYSCON                              ( 0x00000000UL ) /* MPU Disable. */
 
 /* CSA manipulation macros. */
-#define portCSA_FCX_MASK                    ( 0x000FFFFFUL )
+#define portCSA_FCX_MASK                                ( 0x000FFFFFUL )
 
 /* OS Interrupt and Trap mechanisms. */
-#define portRESTORE_PSW_MASK                ( ~( 0x000000FFUL ) )
-#define portSYSCALL_TRAP                    ( 6 )
+#define portRESTORE_PSW_MASK                            ( ~( 0x000000FFUL ) )
+#define portSYSCALL_TRAP                                ( 6 )
 
 /* Each CSA contains 16 words of data. */
-#define portNUM_WORDS_IN_CSA                ( 16 )
+#define portNUM_WORDS_IN_CSA                            ( 16 )
 
 /* The interrupt enable bit in the PCP_SRC register. */
-#define portENABLE_CPU_INTERRUPT            ( 1U << 12U )
+#define portENABLE_CPU_INTERRUPT                        ( 1U << 12U )
 /*-----------------------------------------------------------*/
 
 /*
  * Perform any hardware configuration necessary to generate the tick interrupt.
  */
-static void prvSystemTickHandler( int ) __attribute__((longcall));
+static void prvSystemTickHandler( int ) __attribute__( ( longcall ) );
 static void prvSetupTimerInterrupt( void );
 
 /*
@@ -89,37 +89,39 @@ static void prvInterruptYield( int iTrapIdentification );
 /*-----------------------------------------------------------*/
 
 /* This reference is required by the save/restore context macros. */
-extern volatile uint32_t *pxCurrentTCB;
+extern volatile uint32_t * pxCurrentTCB;
 
 /* Precalculate the compare match value at compile time. */
 static const uint32_t ulCompareMatchValue = ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ );
 
 /*-----------------------------------------------------------*/
 
-StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
-uint32_t *pulUpperCSA = NULL;
-uint32_t *pulLowerCSA = NULL;
+    uint32_t * pulUpperCSA = NULL;
+    uint32_t * pulLowerCSA = NULL;
 
     /* 16 Address Registers (4 Address registers are global), 16 Data
-    Registers, and 3 System Registers.
-
-    There are 3 registers that track the CSAs.
-        FCX points to the head of globally free set of CSAs.
-        PCX for the task needs to point to Lower->Upper->NULL arrangement.
-        LCX points to the last free CSA so that corrective action can be taken.
-
-    Need two CSAs to store the context of a task.
-        The upper context contains D8-D15, A10-A15, PSW and PCXI->NULL.
-        The lower context contains D0-D7, A2-A7, A11 and PCXI->UpperContext.
-        The pxCurrentTCB->pxTopOfStack points to the Lower Context RSLCX matching the initial BISR.
-        The Lower Context points to the Upper Context ready for the return from the interrupt handler.
-
-     The Real stack pointer for the task is stored in the A10 which is restored
-     with the upper context. */
+     * Registers, and 3 System Registers.
+     *
+     * There are 3 registers that track the CSAs.
+     *  FCX points to the head of globally free set of CSAs.
+     *  PCX for the task needs to point to Lower->Upper->NULL arrangement.
+     *  LCX points to the last free CSA so that corrective action can be taken.
+     *
+     * Need two CSAs to store the context of a task.
+     *  The upper context contains D8-D15, A10-A15, PSW and PCXI->NULL.
+     *  The lower context contains D0-D7, A2-A7, A11 and PCXI->UpperContext.
+     *  The pxCurrentTCB->pxTopOfStack points to the Lower Context RSLCX matching the initial BISR.
+     *  The Lower Context points to the Upper Context ready for the return from the interrupt handler.
+     *
+     * The Real stack pointer for the task is stored in the A10 which is restored
+     * with the upper context. */
 
     /* Have to disable interrupts here because the CSAs are going to be
-    manipulated. */
+     * manipulated. */
     portENTER_CRITICAL();
     {
         /* DSync to ensure that buffering is not a problem. */
@@ -127,6 +129,7 @@ uint32_t *pulLowerCSA = NULL;
 
         /* Consume two free CSAs. */
         pulLowerCSA = portCSA_TO_ADDRESS( __MFCR( $FCX ) );
+
         if( NULL != pulLowerCSA )
         {
             /* The Lower Links to the Upper. */
@@ -155,21 +158,21 @@ uint32_t *pulLowerCSA = NULL;
     memset( pulUpperCSA, 0, portNUM_WORDS_IN_CSA * sizeof( uint32_t ) );
 
     /* Upper Context. */
-    pulUpperCSA[ 2 ] = ( uint32_t )pxTopOfStack;        /* A10; Stack Return aka Stack Pointer */
-    pulUpperCSA[ 1 ] = portSYSTEM_PROGRAM_STATUS_WORD;      /* PSW  */
+    pulUpperCSA[ 2 ] = ( uint32_t ) pxTopOfStack;      /* A10; Stack Return aka Stack Pointer */
+    pulUpperCSA[ 1 ] = portSYSTEM_PROGRAM_STATUS_WORD; /* PSW  */
 
     /* Clear the lower CSA. */
     memset( pulLowerCSA, 0, portNUM_WORDS_IN_CSA * sizeof( uint32_t ) );
 
     /* Lower Context. */
-    pulLowerCSA[ 8 ] = ( uint32_t ) pvParameters;       /* A4;  Address Type Parameter Register */
-    pulLowerCSA[ 1 ] = ( uint32_t ) pxCode;         /* A11; Return Address aka RA */
+    pulLowerCSA[ 8 ] = ( uint32_t ) pvParameters; /* A4;  Address Type Parameter Register */
+    pulLowerCSA[ 1 ] = ( uint32_t ) pxCode;       /* A11; Return Address aka RA */
 
     /* PCXI pointing to the Upper context. */
     pulLowerCSA[ 0 ] = ( portINITIAL_PCXI_UPPER_CONTEXT_WORD | ( uint32_t ) portADDRESS_TO_CSA( pulUpperCSA ) );
 
     /* Save the link to the CSA in the top of stack. */
-    pxTopOfStack = (uint32_t * ) portADDRESS_TO_CSA( pulLowerCSA );
+    pxTopOfStack = ( uint32_t * ) portADDRESS_TO_CSA( pulLowerCSA );
 
     /* DSync to ensure that buffering is not a problem. */
     _dsync();
@@ -180,13 +183,13 @@ uint32_t *pulLowerCSA = NULL;
 
 int32_t xPortStartScheduler( void )
 {
-extern void vTrapInstallHandlers( void );
-uint32_t ulMFCR = 0UL;
-uint32_t *pulUpperCSA = NULL;
-uint32_t *pulLowerCSA = NULL;
+    extern void vTrapInstallHandlers( void );
+    uint32_t ulMFCR = 0UL;
+    uint32_t * pulUpperCSA = NULL;
+    uint32_t * pulLowerCSA = NULL;
 
     /* Interrupts at or below configMAX_SYSCALL_INTERRUPT_PRIORITY are disable
-    when this function is called. */
+     * when this function is called. */
 
     /* Set-up the timer interrupt. */
     prvSetupTimerInterrupt();
@@ -202,8 +205,9 @@ uint32_t *pulLowerCSA = NULL;
     }
 
     /* Enable then install the priority 1 interrupt for pending context
-    switches from an ISR.  See mod_SRC in the TriCore manual. */
-    CPU_SRC0.reg =  ( portENABLE_CPU_INTERRUPT ) | ( configKERNEL_YIELD_PRIORITY );
+     * switches from an ISR.  See mod_SRC in the TriCore manual. */
+    CPU_SRC0.reg = ( portENABLE_CPU_INTERRUPT ) | ( configKERNEL_YIELD_PRIORITY );
+
     if( 0 == _install_int_handler( configKERNEL_YIELD_PRIORITY, prvInterruptYield, 0 ) )
     {
         /* Failed to install the yield handler, force an assert. */
@@ -219,7 +223,7 @@ uint32_t *pulLowerCSA = NULL;
     /* ENDINIT has already been applied in the 'cstart.c' code. */
 
     /* Clear the PSW.CDC to enable the use of an RFE without it generating an
-    exception because this code is not genuinely in an exception. */
+     * exception because this code is not genuinely in an exception. */
     ulMFCR = __MFCR( $PSW );
     ulMFCR &= portRESTORE_PSW_MASK;
     _dsync();
@@ -228,7 +232,7 @@ uint32_t *pulLowerCSA = NULL;
 
     /* Finally, perform the equivalent of a portRESTORE_CONTEXT() */
     pulLowerCSA = portCSA_TO_ADDRESS( ( *pxCurrentTCB ) );
-    pulUpperCSA = portCSA_TO_ADDRESS( pulLowerCSA[0] );
+    pulUpperCSA = portCSA_TO_ADDRESS( pulLowerCSA[ 0 ] );
     _dsync();
     _mtcr( $PCXI, *pxCurrentTCB );
     _isync();
@@ -237,7 +241,7 @@ uint32_t *pulLowerCSA = NULL;
     _nop();
 
     /* Return to the first task selected to execute. */
-    __asm volatile( "rfe" );
+    __asm volatile ( "rfe" );
 
     /* Will not get here. */
     return 0;
@@ -250,7 +254,9 @@ static void prvSetupTimerInterrupt( void )
     unlock_wdtcon();
     {
         /* Wait until access to Endint protected register is enabled. */
-        while( 0 != ( WDT_CON0.reg & 0x1UL ) );
+        while( 0 != ( WDT_CON0.reg & 0x1UL ) )
+        {
+        }
 
         /* RMC == 1 so STM Clock == FPI */
         STM_CLC.reg = ( 1UL << 8 );
@@ -285,11 +291,11 @@ static void prvSetupTimerInterrupt( void )
 
 static void prvSystemTickHandler( int iArg )
 {
-uint32_t ulSavedInterruptMask;
-uint32_t *pxUpperCSA = NULL;
-uint32_t xUpperCSA = 0UL;
-extern volatile uint32_t *pxCurrentTCB;
-int32_t lYieldRequired;
+    uint32_t ulSavedInterruptMask;
+    uint32_t * pxUpperCSA = NULL;
+    uint32_t xUpperCSA = 0UL;
+    extern volatile uint32_t * pxCurrentTCB;
+    int32_t lYieldRequired;
 
     /* Just to avoid compiler warnings about unused parameters. */
     ( void ) iArg;
@@ -298,22 +304,22 @@ int32_t lYieldRequired;
     STM_ISRR.reg = 1UL;
 
     /* Reload the Compare Match register for X ticks into the future.
-
-    If critical section or interrupt nesting budgets are exceeded, then
-    it is possible that the calculated next compare match value is in the
-    past.  If this occurs (unlikely), it is possible that the resulting
-    time slippage will exceed a single tick period.  Any adverse effect of
-    this is time bounded by the fact that only the first n bits of the 56 bit
-    STM timer are being used for a compare match, so another compare match
-    will occur after an overflow in just those n bits (not the entire 56 bits).
-    As an example, if the peripheral clock is 75MHz, and the tick rate is 1KHz,
-    a missed tick could result in the next tick interrupt occurring within a
-    time that is 1.7 times the desired period.  The fact that this is greater
-    than a single tick period is an effect of using a timer that cannot be
-    automatically reset, in hardware, by the occurrence of a tick interrupt.
-    Changing the tick source to a timer that has an automatic reset on compare
-    match (such as a GPTA timer) will reduce the maximum possible additional
-    period to exactly 1 times the desired period. */
+     *
+     * If critical section or interrupt nesting budgets are exceeded, then
+     * it is possible that the calculated next compare match value is in the
+     * past.  If this occurs (unlikely), it is possible that the resulting
+     * time slippage will exceed a single tick period.  Any adverse effect of
+     * this is time bounded by the fact that only the first n bits of the 56 bit
+     * STM timer are being used for a compare match, so another compare match
+     * will occur after an overflow in just those n bits (not the entire 56 bits).
+     * As an example, if the peripheral clock is 75MHz, and the tick rate is 1KHz,
+     * a missed tick could result in the next tick interrupt occurring within a
+     * time that is 1.7 times the desired period.  The fact that this is greater
+     * than a single tick period is an effect of using a timer that cannot be
+     * automatically reset, in hardware, by the occurrence of a tick interrupt.
+     * Changing the tick source to a timer that has an automatic reset on compare
+     * match (such as a GPTA timer) will reduce the maximum possible additional
+     * period to exactly 1 times the desired period. */
     STM_CMP0.reg += ulCompareMatchValue;
 
     /* Kernel API calls require Critical Sections. */
@@ -327,24 +333,24 @@ int32_t lYieldRequired;
     if( lYieldRequired != pdFALSE )
     {
         /* Save the context of a task.
-        The upper context is automatically saved when entering a trap or interrupt.
-        Need to save the lower context as well and copy the PCXI CSA ID into
-        pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the
-        TCB of a task.
-
-        Call vTaskSwitchContext to select the next task, note that this changes the
-        value of pxCurrentTCB so that it needs to be reloaded.
-
-        Call vPortSetMPURegisterSetOne to change the MPU mapping for the task
-        that has just been switched in.
-
-        Load the context of the task.
-        Need to restore the lower context by loading the CSA from
-        pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack).
-        In the Interrupt handler post-amble, RSLCX will restore the lower context
-        of the task. RFE will restore the upper context of the task, jump to the
-        return address and restore the previous state of interrupts being
-        enabled/disabled. */
+         * The upper context is automatically saved when entering a trap or interrupt.
+         * Need to save the lower context as well and copy the PCXI CSA ID into
+         * pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the
+         * TCB of a task.
+         *
+         * Call vTaskSwitchContext to select the next task, note that this changes the
+         * value of pxCurrentTCB so that it needs to be reloaded.
+         *
+         * Call vPortSetMPURegisterSetOne to change the MPU mapping for the task
+         * that has just been switched in.
+         *
+         * Load the context of the task.
+         * Need to restore the lower context by loading the CSA from
+         * pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack).
+         * In the Interrupt handler post-amble, RSLCX will restore the lower context
+         * of the task. RFE will restore the upper context of the task, jump to the
+         * return address and restore the previous state of interrupts being
+         * enabled/disabled. */
         _disable();
         _dsync();
         xUpperCSA = __MFCR( $PCXI );
@@ -376,34 +382,34 @@ int32_t lYieldRequired;
  * than they can be freed assuming that tasks are being spawned and
  * deleted frequently.
  */
-void vPortReclaimCSA( uint32_t *pxTCB )
+void vPortReclaimCSA( uint32_t * pxTCB )
 {
-uint32_t pxHeadCSA, pxTailCSA, pxFreeCSA;
-uint32_t *pulNextCSA;
+    uint32_t pxHeadCSA, pxTailCSA, pxFreeCSA;
+    uint32_t * pulNextCSA;
 
     /* A pointer to the first CSA in the list of CSAs consumed by the task is
-    stored in the first element of the tasks TCB structure (where the stack
-    pointer would be on a traditional stack based architecture). */
+     * stored in the first element of the tasks TCB structure (where the stack
+     * pointer would be on a traditional stack based architecture). */
     pxHeadCSA = ( *pxTCB ) & portCSA_FCX_MASK;
 
     /* Mask off everything in the CSA link field other than the address.  If
-    the address is NULL, then the CSA is not linking anywhere and there is
-    nothing to do. */
+     * the address is NULL, then the CSA is not linking anywhere and there is
+     * nothing to do. */
     pxTailCSA = pxHeadCSA;
 
     /* Convert the link value to contain just a raw address and store this
-    in a local variable. */
+     * in a local variable. */
     pulNextCSA = portCSA_TO_ADDRESS( pxTailCSA );
 
     /* Iterate over the CSAs that were consumed as part of the task.  The
-    first field in the CSA is the pointer to then next CSA.  Mask off
-    everything in the pointer to the next CSA, other than the link address.
-    If this is NULL, then the CSA currently being pointed to is the last in
-    the chain. */
+     * first field in the CSA is the pointer to then next CSA.  Mask off
+     * everything in the pointer to the next CSA, other than the link address.
+     * If this is NULL, then the CSA currently being pointed to is the last in
+     * the chain. */
     while( 0UL != ( pulNextCSA[ 0 ] & portCSA_FCX_MASK ) )
     {
         /* Clear all bits of the pointer to the next in the chain, other
-        than the address bits themselves. */
+         * than the address bits themselves. */
         pulNextCSA[ 0 ] = pulNextCSA[ 0 ] & portCSA_FCX_MASK;
 
         /* Move the pointer to point to the next CSA in the list. */
@@ -439,32 +445,33 @@ void vPortEndScheduler( void )
 
 static void prvTrapYield( int iTrapIdentification )
 {
-uint32_t *pxUpperCSA = NULL;
-uint32_t xUpperCSA = 0UL;
-extern volatile uint32_t *pxCurrentTCB;
+    uint32_t * pxUpperCSA = NULL;
+    uint32_t xUpperCSA = 0UL;
+    extern volatile uint32_t * pxCurrentTCB;
 
     switch( iTrapIdentification )
     {
         case portSYSCALL_TASK_YIELD:
+
             /* Save the context of a task.
-            The upper context is automatically saved when entering a trap or interrupt.
-            Need to save the lower context as well and copy the PCXI CSA ID into
-            pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the
-            TCB of a task.
-
-            Call vTaskSwitchContext to select the next task, note that this changes the
-            value of pxCurrentTCB so that it needs to be reloaded.
-
-            Call vPortSetMPURegisterSetOne to change the MPU mapping for the task
-            that has just been switched in.
-
-            Load the context of the task.
-            Need to restore the lower context by loading the CSA from
-            pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack).
-            In the Interrupt handler post-amble, RSLCX will restore the lower context
-            of the task. RFE will restore the upper context of the task, jump to the
-            return address and restore the previous state of interrupts being
-            enabled/disabled. */
+             * The upper context is automatically saved when entering a trap or interrupt.
+             * Need to save the lower context as well and copy the PCXI CSA ID into
+             * pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the
+             * TCB of a task.
+             *
+             * Call vTaskSwitchContext to select the next task, note that this changes the
+             * value of pxCurrentTCB so that it needs to be reloaded.
+             *
+             * Call vPortSetMPURegisterSetOne to change the MPU mapping for the task
+             * that has just been switched in.
+             *
+             * Load the context of the task.
+             * Need to restore the lower context by loading the CSA from
+             * pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack).
+             * In the Interrupt handler post-amble, RSLCX will restore the lower context
+             * of the task. RFE will restore the upper context of the task, jump to the
+             * return address and restore the previous state of interrupts being
+             * enabled/disabled. */
             _disable();
             _dsync();
             xUpperCSA = __MFCR( $PCXI );
@@ -486,32 +493,32 @@ extern volatile uint32_t *pxCurrentTCB;
 
 static void prvInterruptYield( int iId )
 {
-uint32_t *pxUpperCSA = NULL;
-uint32_t xUpperCSA = 0UL;
-extern volatile uint32_t *pxCurrentTCB;
+    uint32_t * pxUpperCSA = NULL;
+    uint32_t xUpperCSA = 0UL;
+    extern volatile uint32_t * pxCurrentTCB;
 
     /* Just to remove compiler warnings. */
     ( void ) iId;
 
     /* Save the context of a task.
-    The upper context is automatically saved when entering a trap or interrupt.
-    Need to save the lower context as well and copy the PCXI CSA ID into
-    pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the
-    TCB of a task.
-
-    Call vTaskSwitchContext to select the next task, note that this changes the
-    value of pxCurrentTCB so that it needs to be reloaded.
-
-    Call vPortSetMPURegisterSetOne to change the MPU mapping for the task
-    that has just been switched in.
-
-    Load the context of the task.
-    Need to restore the lower context by loading the CSA from
-    pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack).
-    In the Interrupt handler post-amble, RSLCX will restore the lower context
-    of the task. RFE will restore the upper context of the task, jump to the
-    return address and restore the previous state of interrupts being
-    enabled/disabled. */
+     * The upper context is automatically saved when entering a trap or interrupt.
+     * Need to save the lower context as well and copy the PCXI CSA ID into
+     * pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the
+     * TCB of a task.
+     *
+     * Call vTaskSwitchContext to select the next task, note that this changes the
+     * value of pxCurrentTCB so that it needs to be reloaded.
+     *
+     * Call vPortSetMPURegisterSetOne to change the MPU mapping for the task
+     * that has just been switched in.
+     *
+     * Load the context of the task.
+     * Need to restore the lower context by loading the CSA from
+     * pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack).
+     * In the Interrupt handler post-amble, RSLCX will restore the lower context
+     * of the task. RFE will restore the upper context of the task, jump to the
+     * return address and restore the previous state of interrupts being
+     * enabled/disabled. */
     _disable();
     _dsync();
     xUpperCSA = __MFCR( $PCXI );
@@ -526,7 +533,7 @@ extern volatile uint32_t *pxCurrentTCB;
 
 uint32_t uxPortSetInterruptMaskFromISR( void )
 {
-uint32_t uxReturn = 0UL;
+    uint32_t uxReturn = 0UL;
 
     _disable();
     uxReturn = __MFCR( $ICR );
@@ -535,6 +542,6 @@ uint32_t uxReturn = 0UL;
     _enable();
 
     /* Return just the interrupt mask bits. */
-    return ( uxReturn & portCCPN_MASK );
+    return( uxReturn & portCCPN_MASK );
 }
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/TriCore_1782/portmacro.h b/portable/GCC/TriCore_1782/portmacro.h
index d17c7bc68..8c1a9c0eb 100644
--- a/portable/GCC/TriCore_1782/portmacro.h
+++ b/portable/GCC/TriCore_1782/portmacro.h
@@ -50,126 +50,132 @@
  */
 
 /* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint32_t
-#define portBASE_TYPE   long
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-    not need to be guarded with a critical section. */
-    #define portTICK_TYPE_IS_ATOMIC 1
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+    #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
 /*---------------------------------------------------------------------------*/
 
 /* Architecture specifics. */
-#define portSTACK_GROWTH                            ( -1 )
-#define portTICK_PERIOD_MS                          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT                          4
-#define portNOP()                                   __asm volatile( " nop " )
-#define portCRITICAL_NESTING_IN_TCB                 1
-#define portRESTORE_FIRST_TASK_PRIORITY_LEVEL       1
+#define portSTACK_GROWTH                         ( -1 )
+#define portTICK_PERIOD_MS                       ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT                       4
+#define portNOP()    __asm volatile ( " nop " )
+#define portCRITICAL_NESTING_IN_TCB              1
+#define portRESTORE_FIRST_TASK_PRIORITY_LEVEL    1
 
 
 /*---------------------------------------------------------------------------*/
 
-typedef struct MPU_SETTINGS { uint32_t ulNotUsed; } xMPU_SETTINGS;
+typedef struct MPU_SETTINGS
+{
+    uint32_t ulNotUsed;
+} xMPU_SETTINGS;
 
 /* Define away the instruction from the Restore Context Macro. */
-#define portPRIVILEGE_BIT                           0x0UL
+#define portPRIVILEGE_BIT    0x0UL
 
-#define portCCPN_MASK                       ( 0x000000FFUL )
+#define portCCPN_MASK        ( 0x000000FFUL )
 
 extern void vTaskEnterCritical( void );
 extern void vTaskExitCritical( void );
-#define portENTER_CRITICAL()            vTaskEnterCritical()
-#define portEXIT_CRITICAL()             vTaskExitCritical()
+#define portENTER_CRITICAL()    vTaskEnterCritical()
+#define portEXIT_CRITICAL()     vTaskExitCritical()
 /*---------------------------------------------------------------------------*/
 
 /* CSA Manipulation. */
-#define portCSA_TO_ADDRESS( pCSA )          ( ( uint32_t * )( ( ( ( pCSA ) & 0x000F0000 ) << 12 ) | ( ( ( pCSA ) & 0x0000FFFF ) << 6 ) ) )
-#define portADDRESS_TO_CSA( pAddress )      ( ( uint32_t )( ( ( ( (uint32_t)( pAddress ) ) & 0xF0000000 ) >> 12 ) | ( ( ( uint32_t )( pAddress ) & 0x003FFFC0 ) >> 6 ) ) )
+#define portCSA_TO_ADDRESS( pCSA )        ( ( uint32_t * ) ( ( ( ( pCSA ) & 0x000F0000 ) << 12 ) | ( ( ( pCSA ) & 0x0000FFFF ) << 6 ) ) )
+#define portADDRESS_TO_CSA( pAddress )    ( ( uint32_t ) ( ( ( ( ( uint32_t ) ( pAddress ) ) & 0xF0000000 ) >> 12 ) | ( ( ( uint32_t ) ( pAddress ) & 0x003FFFC0 ) >> 6 ) ) )
 /*---------------------------------------------------------------------------*/
 
-#define portYIELD()                             _syscall( 0 )
+#define portYIELD()                       _syscall( 0 )
 /* Port Restore is implicit in the platform when the function is returned from the original PSW is automatically replaced. */
-#define portSYSCALL_TASK_YIELD                  0
-#define portSYSCALL_RAISE_PRIORITY              1
+#define portSYSCALL_TASK_YIELD        0
+#define portSYSCALL_RAISE_PRIORITY    1
 /*---------------------------------------------------------------------------*/
 
 /* Critical section management. */
 
 /* Set ICR.CCPN to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-#define portDISABLE_INTERRUPTS()    {                                                                                                   \
-                                        uint32_t ulICR;                                                                         \
-                                        _disable();                                                                                     \
-                                        ulICR = __MFCR( $ICR );         /* Get current ICR value. */                                        \
-                                        ulICR &= ~portCCPN_MASK;    /* Clear down mask bits. */                                         \
-                                        ulICR |= configMAX_SYSCALL_INTERRUPT_PRIORITY; /* Set mask bits to required priority mask. */   \
-                                        _mtcr( $ICR, ulICR );       /* Write back updated ICR. */                                       \
-                                        _isync();                                                                                       \
-                                        _enable();                                                                                      \
-                                    }
+#define portDISABLE_INTERRUPTS()                                                                      \
+    {                                                                                                 \
+        uint32_t ulICR;                                                                               \
+        _disable();                                                                                   \
+        ulICR = __MFCR( $ICR );                        /* Get current ICR value. */                   \
+        ulICR &= ~portCCPN_MASK;                       /* Clear down mask bits. */                    \
+        ulICR |= configMAX_SYSCALL_INTERRUPT_PRIORITY; /* Set mask bits to required priority mask. */ \
+        _mtcr( $ICR, ulICR );                          /* Write back updated ICR. */                  \
+        _isync();                                                                                     \
+        _enable();                                                                                    \
+    }
 
 /* Clear ICR.CCPN to allow all interrupt priorities. */
-#define portENABLE_INTERRUPTS()     {                                                                   \
-                                        uint32_t ulICR;                                         \
-                                        _disable();                                                     \
-                                        ulICR = __MFCR( $ICR );     /* Get current ICR value. */        \
-                                        ulICR &= ~portCCPN_MASK;    /* Clear down mask bits. */         \
-                                        _mtcr( $ICR, ulICR );       /* Write back updated ICR. */       \
-                                        _isync();                                                       \
-                                        _enable();                                                      \
-                                    }
+#define portENABLE_INTERRUPTS()                                \
+    {                                                          \
+        uint32_t ulICR;                                        \
+        _disable();                                            \
+        ulICR = __MFCR( $ICR );  /* Get current ICR value. */  \
+        ulICR &= ~portCCPN_MASK; /* Clear down mask bits. */   \
+        _mtcr( $ICR, ulICR );    /* Write back updated ICR. */ \
+        _isync();                                              \
+        _enable();                                             \
+    }
 
 /* Set ICR.CCPN to uxSavedMaskValue. */
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedMaskValue )   {                                                                                       \
-                                                                    uint32_t ulICR;                                                             \
-                                                                    _disable();                                                                         \
-                                                                    ulICR = __MFCR( $ICR );     /* Get current ICR value. */                            \
-                                                                    ulICR &= ~portCCPN_MASK;    /* Clear down mask bits. */                             \
-                                                                    ulICR |= uxSavedMaskValue;  /* Set mask bits to previously saved mask value. */     \
-                                                                    _mtcr( $ICR, ulICR );       /* Write back updated ICR. */                           \
-                                                                    _isync();                                                                           \
-                                                                    _enable();                                                                          \
-                                                                }
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedMaskValue )                          \
+    {                                                                                  \
+        uint32_t ulICR;                                                                \
+        _disable();                                                                    \
+        ulICR = __MFCR( $ICR );    /* Get current ICR value. */                        \
+        ulICR &= ~portCCPN_MASK;   /* Clear down mask bits. */                         \
+        ulICR |= uxSavedMaskValue; /* Set mask bits to previously saved mask value. */ \
+        _mtcr( $ICR, ulICR );      /* Write back updated ICR. */                       \
+        _isync();                                                                      \
+        _enable();                                                                     \
+    }
 
 
 /* Set ICR.CCPN to configMAX_SYSCALL_INTERRUPT_PRIORITY */
 extern uint32_t uxPortSetInterruptMaskFromISR( void );
-#define portSET_INTERRUPT_MASK_FROM_ISR()   uxPortSetInterruptMaskFromISR()
+#define portSET_INTERRUPT_MASK_FROM_ISR()                 uxPortSetInterruptMaskFromISR()
 
 /* Pend a priority 1 interrupt, which will take care of the context switch. */
-#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken )      do { if( xHigherPriorityTaskWoken != pdFALSE ) { CPU_SRC0.bits.SETR = 1; _isync(); } } while( 0 )
+#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken )    do { if( xHigherPriorityTaskWoken != pdFALSE ) { CPU_SRC0.bits.SETR = 1; _isync(); } } while( 0 )
 
 /*---------------------------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 /*---------------------------------------------------------------------------*/
 
 /*
  * Port specific clean up macro required to free the CSAs that were consumed by
  * a task that has since been deleted.
  */
-void vPortReclaimCSA( uint32_t *pxTCB );
-#define portCLEAN_UP_TCB( pxTCB )       vPortReclaimCSA( ( uint32_t * ) ( pxTCB ) )
+void vPortReclaimCSA( uint32_t * pxTCB );
+#define portCLEAN_UP_TCB( pxTCB )    vPortReclaimCSA( ( uint32_t * ) ( pxTCB ) )
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/GCC/TriCore_1782/porttrap.c b/portable/GCC/TriCore_1782/porttrap.c
index 79d6ea050..732a406b6 100644
--- a/portable/GCC/TriCore_1782/porttrap.c
+++ b/portable/GCC/TriCore_1782/porttrap.c
@@ -38,7 +38,7 @@
 /*
  * This reference is required by the Save/Restore Context Macros.
  */
-extern volatile uint32_t *pxCurrentTCB;
+extern volatile uint32_t * pxCurrentTCB;
 /*-----------------------------------------------------------*/
 
 /*
@@ -51,57 +51,57 @@ extern volatile uint32_t *pxCurrentTCB;
  */
 
 /* The Trap Classes. */
-#define portMMU_TRAP                                        0
-#define portIPT_TRAP                                        1
-#define portIE_TRAP                                         2
-#define portCM_TRAP                                         3
-#define portSBP_TRAP                                        4
-#define portASSERT_TRAP                                     5
-#define portNMI_TRAP                                        7
+#define portMMU_TRAP                                                      0
+#define portIPT_TRAP                                                      1
+#define portIE_TRAP                                                       2
+#define portCM_TRAP                                                       3
+#define portSBP_TRAP                                                      4
+#define portASSERT_TRAP                                                   5
+#define portNMI_TRAP                                                      7
 
 /* MMU Trap Identifications. */
-#define portTIN_MMU_VIRTUAL_ADDRESS_FILL                    0
-#define portTIN_MMU_VIRTUAL_ADDRESS_PROTECTION              1
+#define portTIN_MMU_VIRTUAL_ADDRESS_FILL                                  0
+#define portTIN_MMU_VIRTUAL_ADDRESS_PROTECTION                            1
 
 /* Internal Protection Trap Identifications. */
-#define portTIN_IPT_PRIVILIGED_INSTRUCTION                  1
-#define portTIN_IPT_MEMORY_PROTECTION_READ                  2
-#define portTIN_IPT_MEMORY_PROTECTION_WRITE                 3
-#define portTIN_IPT_MEMORY_PROTECTION_EXECUTION             4
-#define portTIN_IPT_MEMORY_PROTECTION_PERIPHERAL_ACCESS     5
-#define portTIN_IPT_MEMORY_PROTECTION_NULL_ADDRESS          6
-#define portTIN_IPT_MEMORY_PROTECTION_GLOBAL_REGISTER_WRITE_PROTECTION  7
+#define portTIN_IPT_PRIVILEGED_INSTRUCTION                                1
+#define portTIN_IPT_MEMORY_PROTECTION_READ                                2
+#define portTIN_IPT_MEMORY_PROTECTION_WRITE                               3
+#define portTIN_IPT_MEMORY_PROTECTION_EXECUTION                           4
+#define portTIN_IPT_MEMORY_PROTECTION_PERIPHERAL_ACCESS                   5
+#define portTIN_IPT_MEMORY_PROTECTION_NULL_ADDRESS                        6
+#define portTIN_IPT_MEMORY_PROTECTION_GLOBAL_REGISTER_WRITE_PROTECTION    7
 
 /* Instruction Error Trap Identifications. */
-#define portTIN_IE_ILLEGAL_OPCODE                           1
-#define portTIN_IE_UNIMPLEMENTED_OPCODE                     2
-#define portTIN_IE_INVALID_OPERAND                          3
-#define portTIN_IE_DATA_ADDRESS_ALIGNMENT                   4
-#define portTIN_IE_INVALID_LOCAL_MEMORY_ADDRESS             5
+#define portTIN_IE_ILLEGAL_OPCODE                                         1
+#define portTIN_IE_UNIMPLEMENTED_OPCODE                                   2
+#define portTIN_IE_INVALID_OPERAND                                        3
+#define portTIN_IE_DATA_ADDRESS_ALIGNMENT                                 4
+#define portTIN_IE_INVALID_LOCAL_MEMORY_ADDRESS                           5
 
 /* Context Management Trap Identifications. */
-#define portTIN_CM_FREE_CONTEXT_LIST_DEPLETION              1
-#define portTIN_CM_CALL_DEPTH_OVERFLOW                      2
-#define portTIN_CM_CALL_DEPTH_UNDEFLOW                      3
-#define portTIN_CM_FREE_CONTEXT_LIST_UNDERFLOW              4
-#define portTIN_CM_CALL_STACK_UNDERFLOW                     5
-#define portTIN_CM_CONTEXT_TYPE                             6
-#define portTIN_CM_NESTING_ERROR                            7
+#define portTIN_CM_FREE_CONTEXT_LIST_DEPLETION                            1
+#define portTIN_CM_CALL_DEPTH_OVERFLOW                                    2
+#define portTIN_CM_CALL_DEPTH_UNDEFLOW                                    3
+#define portTIN_CM_FREE_CONTEXT_LIST_UNDERFLOW                            4
+#define portTIN_CM_CALL_STACK_UNDERFLOW                                   5
+#define portTIN_CM_CONTEXT_TYPE                                           6
+#define portTIN_CM_NESTING_ERROR                                          7
 
 /* System Bus and Peripherals Trap Identifications. */
-#define portTIN_SBP_PROGRAM_FETCH_SYNCHRONOUS_ERROR         1
-#define portTIN_SBP_DATA_ACCESS_SYNCHRONOUS_ERROR           2
-#define portTIN_SBP_DATA_ACCESS_ASYNCHRONOUS_ERROR          3
-#define portTIN_SBP_COPROCESSOR_TRAP_ASYNCHRONOUS_ERROR     4
-#define portTIN_SBP_PROGRAM_MEMORY_INTEGRITY_ERROR          5
-#define portTIN_SBP_DATA_MEMORY_INTEGRITY_ERROR             6
+#define portTIN_SBP_PROGRAM_FETCH_SYNCHRONOUS_ERROR                       1
+#define portTIN_SBP_DATA_ACCESS_SYNCHRONOUS_ERROR                         2
+#define portTIN_SBP_DATA_ACCESS_ASYNCHRONOUS_ERROR                        3
+#define portTIN_SBP_COPROCESSOR_TRAP_ASYNCHRONOUS_ERROR                   4
+#define portTIN_SBP_PROGRAM_MEMORY_INTEGRITY_ERROR                        5
+#define portTIN_SBP_DATA_MEMORY_INTEGRITY_ERROR                           6
 
 /* Assertion Trap Identifications. */
-#define portTIN_ASSERT_ARITHMETIC_OVERFLOW                  1
-#define portTIN_ASSERT_STICKY_ARITHMETIC_OVERFLOW           2
+#define portTIN_ASSERT_ARITHMETIC_OVERFLOW                                1
+#define portTIN_ASSERT_STICKY_ARITHMETIC_OVERFLOW                         2
 
 /* Non-maskable Interrupt Trap Identifications. */
-#define portTIN_NMI_NON_MASKABLE_INTERRUPT                  0
+#define portTIN_NMI_NON_MASKABLE_INTERRUPT                                0
 /*---------------------------------------------------------------------------*/
 
 void vMMUTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
@@ -115,37 +115,37 @@ void vNonMaskableInterruptTrap( int iTrapIdentification ) __attribute__( ( longc
 
 void vTrapInstallHandlers( void )
 {
-    if( 0 == _install_trap_handler ( portMMU_TRAP, vMMUTrap ) )
+    if( 0 == _install_trap_handler( portMMU_TRAP, vMMUTrap ) )
     {
         _debug();
     }
 
-    if( 0 == _install_trap_handler ( portIPT_TRAP, vInternalProtectionTrap ) )
+    if( 0 == _install_trap_handler( portIPT_TRAP, vInternalProtectionTrap ) )
     {
         _debug();
     }
 
-    if( 0 == _install_trap_handler ( portIE_TRAP, vInstructionErrorTrap ) )
+    if( 0 == _install_trap_handler( portIE_TRAP, vInstructionErrorTrap ) )
     {
         _debug();
     }
 
-    if( 0 == _install_trap_handler ( portCM_TRAP, vContextManagementTrap ) )
+    if( 0 == _install_trap_handler( portCM_TRAP, vContextManagementTrap ) )
     {
         _debug();
     }
 
-    if( 0 == _install_trap_handler ( portSBP_TRAP, vSystemBusAndPeripheralsTrap ) )
+    if( 0 == _install_trap_handler( portSBP_TRAP, vSystemBusAndPeripheralsTrap ) )
     {
         _debug();
     }
 
-    if( 0 == _install_trap_handler ( portASSERT_TRAP, vAssertionTrap ) )
+    if( 0 == _install_trap_handler( portASSERT_TRAP, vAssertionTrap ) )
     {
         _debug();
     }
 
-    if( 0 == _install_trap_handler ( portNMI_TRAP, vNonMaskableInterruptTrap ) )
+    if( 0 == _install_trap_handler( portNMI_TRAP, vNonMaskableInterruptTrap ) )
     {
         _debug();
     }
@@ -156,11 +156,11 @@ void vMMUTrap( int iTrapIdentification )
 {
     switch( iTrapIdentification )
     {
-    case portTIN_MMU_VIRTUAL_ADDRESS_FILL:
-    case portTIN_MMU_VIRTUAL_ADDRESS_PROTECTION:
-    default:
-        _debug();
-        break;
+        case portTIN_MMU_VIRTUAL_ADDRESS_FILL:
+        case portTIN_MMU_VIRTUAL_ADDRESS_PROTECTION:
+        default:
+            _debug();
+            break;
     }
 }
 /*---------------------------------------------------------------------------*/
@@ -170,26 +170,26 @@ void vInternalProtectionTrap( int iTrapIdentification )
     /* Deliberate fall through to default. */
     switch( iTrapIdentification )
     {
-        case portTIN_IPT_PRIVILIGED_INSTRUCTION:
-            /* Instruction is not allowed at current execution level, eg DISABLE at User-0. */
+        case portTIN_IPT_PRIVILEGED_INSTRUCTION:
+        /* Instruction is not allowed at current execution level, eg DISABLE at User-0. */
 
         case portTIN_IPT_MEMORY_PROTECTION_READ:
-            /* Load word using invalid address. */
+        /* Load word using invalid address. */
 
         case portTIN_IPT_MEMORY_PROTECTION_WRITE:
-            /* Store Word using invalid address. */
+        /* Store Word using invalid address. */
 
         case portTIN_IPT_MEMORY_PROTECTION_EXECUTION:
-            /* PC jumped to an address outside of the valid range. */
+        /* PC jumped to an address outside of the valid range. */
 
         case portTIN_IPT_MEMORY_PROTECTION_PERIPHERAL_ACCESS:
-            /* Access to a peripheral denied at current execution level. */
+        /* Access to a peripheral denied at current execution level. */
 
         case portTIN_IPT_MEMORY_PROTECTION_NULL_ADDRESS:
-            /* NULL Pointer. */
+        /* NULL Pointer. */
 
         case portTIN_IPT_MEMORY_PROTECTION_GLOBAL_REGISTER_WRITE_PROTECTION:
-            /* Tried to modify a global address pointer register. */
+        /* Tried to modify a global address pointer register. */
 
         default:
 
diff --git a/portable/IAR/78K0R/ISR_Support.h b/portable/IAR/78K0R/ISR_Support.h
index 4eeb07774..2fa110c70 100644
--- a/portable/IAR/78K0R/ISR_Support.h
+++ b/portable/IAR/78K0R/ISR_Support.h
@@ -1,83 +1,112 @@
-;/*
-; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
-; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
-; *
-; * SPDX-License-Identifier: MIT
-; *
-; * Permission is hereby granted, free of charge, to any person obtaining a copy of
-; * this software and associated documentation files (the "Software"), to deal in
-; * the Software without restriction, including without limitation the rights to
-; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
-; * the Software, and to permit persons to whom the Software is furnished to do so,
-; * subject to the following conditions:
-; *
-; * The above copyright notice and this permission notice shall be included in all
-; * copies or substantial portions of the Software.
-; *
-; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-; *
-; * https://www.FreeRTOS.org
-; * https://github.com/FreeRTOS
-; *
-; */
+; /*
+   * ; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+   * ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+   * ; *
+   * ; * SPDX-License-Identifier: MIT
+   * ; *
+   * ; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+   * ; * this software and associated documentation files (the "Software"), to deal in
+   * ; * the Software without restriction, including without limitation the rights to
+   * ; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+   * ; * the Software, and to permit persons to whom the Software is furnished to do so,
+   * ; * subject to the following conditions:
+   * ; *
+   * ; * The above copyright notice and this permission notice shall be included in all
+   * ; * copies or substantial portions of the Software.
+   * ; *
+   * ; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+   * ; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+   * ; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+   * ; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+   * ; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+   * ; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+   * ; *
+   * ; * https://www.FreeRTOS.org
+   * ; * https://github.com/FreeRTOS
+   * ; *
+   * ; */
 
 #include "FreeRTOSConfig.h"
 
-; Variables used by scheduler
-;------------------------------------------------------------------------------
-    EXTERN    pxCurrentTCB
-    EXTERN    usCriticalNesting
+;
+Variables used by scheduler
+;
+------------------------------------------------------------------------------
+EXTERN pxCurrentTCB
+EXTERN usCriticalNesting
 
-;------------------------------------------------------------------------------
-;   portSAVE_CONTEXT MACRO
-;   Saves the context of the general purpose registers, CS and ES (only in far
-;   memory mode) registers the usCriticalNesting Value and the Stack Pointer
-;   of the active Task onto the task stack
-;------------------------------------------------------------------------------
+;
+------------------------------------------------------------------------------
+;
+portSAVE_CONTEXT MACRO
+;
+Saves the context of the general purpose registers, CS and ES( only in far
+                                                               ;
+                                                               memory mode ) registers the usCriticalNesting Value and the Stack Pointer
+;
+of the active Task onto the task stack
+;
+------------------------------------------------------------------------------
 portSAVE_CONTEXT MACRO
 
-    PUSH      AX                    ; Save AX Register to stack.
-    PUSH      HL
-    MOV       A, CS                 ; Save CS register.
-    XCH       A, X
-    MOV       A, ES                 ; Save ES register.
-    PUSH      AX
-    PUSH      DE                    ; Save the remaining general purpose registers.
-    PUSH      BC
-    MOVW      AX, usCriticalNesting ; Save the usCriticalNesting value.
-    PUSH      AX
-    MOVW      AX, pxCurrentTCB      ; Save the Stack pointer.
-    MOVW      HL, AX
-    MOVW      AX, SP
-    MOVW      [HL], AX
-    ENDM
-;------------------------------------------------------------------------------
+PUSH AX;
+Save AX Register to stack.
+   PUSH HL
+MOV A, CS;
+Save CS register.
+   XCH A, X
+MOV A, ES;
+Save ES register.
+   PUSH AX
+PUSH DE;
+Save the remaining general purpose registers.
+   PUSH BC
+MOVW AX, usCriticalNesting;
+Save the usCriticalNesting value.
+   PUSH AX
+MOVW AX, pxCurrentTCB;
+Save the Stack pointer.
+   MOVW HL, AX
+MOVW AX, SP
+        MOVW[ HL ], AX
+        ENDM
+;
+------------------------------------------------------------------------------
 
-;------------------------------------------------------------------------------
-;   portRESTORE_CONTEXT MACRO
-;   Restores the task Stack Pointer then use this to restore usCriticalNesting,
-;   general purpose registers and the CS and ES (only in far memory mode)
-;   of the selected task from the task stack
-;------------------------------------------------------------------------------
+;
+------------------------------------------------------------------------------
+;
 portRESTORE_CONTEXT MACRO
-    MOVW      AX, pxCurrentTCB      ; Restore the Stack pointer.
-    MOVW      HL, AX
-    MOVW      AX, [HL]
-    MOVW      SP, AX
-    POP       AX                    ; Restore usCriticalNesting value.
-    MOVW      usCriticalNesting, AX
-    POP       BC                    ; Restore the necessary general purpose registers.
-    POP       DE
-    POP       AX                    ; Restore the ES register.
-    MOV       ES, A
-    XCH       A, X                  ; Restore the CS register.
-    MOV       CS, A
-    POP       HL                    ; Restore general purpose register HL.
-    POP       AX                    ; Restore AX.
-    ENDM
-;------------------------------------------------------------------------------
+;
+Restores the task Stack Pointer then use this to restore usCriticalNesting,
+;
+general purpose registers and the CS and ES( only in far memory mode )
+;
+of the selected task from the task stack
+;
+------------------------------------------------------------------------------
+portRESTORE_CONTEXT MACRO
+MOVW AX, pxCurrentTCB;
+Restore the Stack pointer.
+   MOVW HL, AX
+MOVW AX, [ HL ]
+MOVW SP, AX
+POP AX;
+Restore usCriticalNesting value.
+   MOVW usCriticalNesting, AX
+POP BC;
+Restore the necessary general purpose registers.
+   POP DE
+POP AX;
+Restore the ES register.
+   MOV ES, A
+XCH A, X;
+Restore the CS register.
+   MOV CS, A
+POP HL;
+Restore general purpose register HL.
+   POP AX;
+Restore AX.
+   ENDM
+;
+------------------------------------------------------------------------------
diff --git a/portable/IAR/78K0R/port.c b/portable/IAR/78K0R/port.c
index 75f5a3e1d..97d390300 100644
--- a/portable/IAR/78K0R/port.c
+++ b/portable/IAR/78K0R/port.c
@@ -34,8 +34,8 @@
 #include "task.h"
 
 /* The critical nesting value is initialised to a non zero value to ensure
-interrupts don't accidentally become enabled before the scheduler is started. */
-#define portINITIAL_CRITICAL_NESTING  (( uint16_t ) 10)
+ * interrupts don't accidentally become enabled before the scheduler is started. */
+#define portINITIAL_CRITICAL_NESTING    ( ( uint16_t ) 10 )
 
 /* Initial PSW value allocated to a newly created task.
  *   1100011000000000
@@ -48,25 +48,25 @@ interrupts don't accidentally become enabled before the scheduler is started. */
  *   |--------------------- Zero Flag set
  *   ---------------------- Global Interrupt Flag set (enabled)
  */
-#define portPSW       (0xc6UL)
+#define portPSW                         ( 0xc6UL )
 
 /* We require the address of the pxCurrentTCB variable, but don't want to know
-any details of its type. */
+ * any details of its type. */
 typedef void TCB_t;
 extern volatile TCB_t * volatile pxCurrentTCB;
 
 /* Most ports implement critical sections by placing the interrupt flags on
-the stack before disabling interrupts.  Exiting the critical section is then
-simply a case of popping the flags from the stack.  As 78K0 IAR does not use
-a frame pointer this cannot be done as modifying the stack will clobber all
-the stack variables.  Instead each task maintains a count of the critical
-section nesting depth.  Each time a critical section is entered the count is
-incremented.  Each time a critical section is left the count is decremented -
-with interrupts only being re-enabled if the count is zero.
-
-usCriticalNesting will get set to zero when the scheduler starts, but must
-not be initialised to zero as this will cause problems during the startup
-sequence. */
+ * the stack before disabling interrupts.  Exiting the critical section is then
+ * simply a case of popping the flags from the stack.  As 78K0 IAR does not use
+ * a frame pointer this cannot be done as modifying the stack will clobber all
+ * the stack variables.  Instead each task maintains a count of the critical
+ * section nesting depth.  Each time a critical section is entered the count is
+ * incremented.  Each time a critical section is left the count is decremented -
+ * with interrupts only being re-enabled if the count is zero.
+ *
+ * usCriticalNesting will get set to zero when the scheduler starts, but must
+ * not be initialised to zero as this will cause problems during the startup
+ * sequence. */
 volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;
 /*-----------------------------------------------------------*/
 
@@ -82,30 +82,32 @@ static void prvSetupTimerInterrupt( void );
  *
  * See the header file portable.h.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
-uint32_t *pulLocal;
+    uint32_t * pulLocal;
 
     #if configMEMORY_MODE == 1
     {
         /* Parameters are passed in on the stack, and written using a 32bit value
-        hence a space is left for the second two bytes. */
+         * hence a space is left for the second two bytes. */
         pxTopOfStack--;
 
         /* Write in the parameter value. */
-        pulLocal =  ( uint32_t * ) pxTopOfStack;
+        pulLocal = ( uint32_t * ) pxTopOfStack;
         *pulLocal = ( uint32_t ) pvParameters;
         pxTopOfStack--;
 
         /* These values are just spacers.  The return address of the function
-        would normally be written here. */
+         * would normally be written here. */
         *pxTopOfStack = ( StackType_t ) 0xcdcd;
         pxTopOfStack--;
         *pxTopOfStack = ( StackType_t ) 0xcdcd;
         pxTopOfStack--;
 
         /* The start address / PSW value is also written in as a 32bit value,
-        so leave a space for the second two bytes. */
+         * so leave a space for the second two bytes. */
         pxTopOfStack--;
 
         /* Task function start address combined with the PSW. */
@@ -117,11 +119,11 @@ uint32_t *pulLocal;
         *pxTopOfStack = ( StackType_t ) 0x1111;
         pxTopOfStack--;
     }
-    #else
+    #else /* if configMEMORY_MODE == 1 */
     {
         /* Task function address is written to the stack first.  As it is
-        written as a 32bit value a space is left on the stack for the second
-        two bytes. */
+         * written as a 32bit value a space is left on the stack for the second
+         * two bytes. */
         pxTopOfStack--;
 
         /* Task function start address combined with the PSW. */
@@ -133,7 +135,7 @@ uint32_t *pulLocal;
         *pxTopOfStack = ( StackType_t ) pvParameters;
         pxTopOfStack--;
     }
-    #endif
+    #endif /* if configMEMORY_MODE == 1 */
 
     /* An initial value for the HL register. */
     *pxTopOfStack = ( StackType_t ) 0x2222;
@@ -150,11 +152,11 @@ uint32_t *pulLocal;
     pxTopOfStack--;
 
     /* Finally the critical section nesting count is set to zero when the task
-    first starts. */
+     * first starts. */
     *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;
 
     /* Return a pointer to the top of the stack we have generated so this can
-    be stored in the task control block for the task. */
+     * be stored in the task control block for the task. */
     return pxTopOfStack;
 }
 /*-----------------------------------------------------------*/
@@ -162,7 +164,7 @@ uint32_t *pulLocal;
 BaseType_t xPortStartScheduler( void )
 {
     /* Setup the hardware to generate the tick.  Interrupts are disabled when
-    this function is called. */
+     * this function is called. */
     prvSetupTimerInterrupt();
 
     /* Restore the context of the first task that is going to run. */
@@ -176,7 +178,7 @@ BaseType_t xPortStartScheduler( void )
 void vPortEndScheduler( void )
 {
     /* It is unlikely that the 78K0R port will get stopped.  If required simply
-    disable the tick interrupt here. */
+     * disable the tick interrupt here. */
 }
 /*-----------------------------------------------------------*/
 
@@ -191,7 +193,7 @@ static void prvSetupTimerInterrupt( void )
     TT0 = 0xff;
 
     /* Interrupt of Timer Array Unit Channel 5 is disabled to set the interrupt
-    priority. */
+     * priority. */
     TMMK05 = 1;
 
     /* Clear Timer Array Unit Channel 5 interrupt flag. */
diff --git a/portable/IAR/78K0R/portmacro.h b/portable/IAR/78K0R/portmacro.h
index 03bb5dee7..206b82c22 100644
--- a/portable/IAR/78K0R/portmacro.h
+++ b/portable/IAR/78K0R/portmacro.h
@@ -47,100 +47,100 @@
 
 /* Type definitions. */
 
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint16_t
-#define portBASE_TYPE   short
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint16_t
+#define portBASE_TYPE     short
 
-typedef portSTACK_TYPE StackType_t;
-typedef short BaseType_t;
-typedef unsigned short UBaseType_t;
+typedef portSTACK_TYPE     StackType_t;
+typedef short              BaseType_t;
+typedef unsigned short     UBaseType_t;
 
 #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef unsigned int TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
+    typedef unsigned int   TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY ( TickType_t )    ( 0xFFFFFFFFUL )
+    typedef uint32_t       TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) ( 0xFFFFFFFFUL )
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
 /*-----------------------------------------------------------*/
 
 /* Interrupt control macros. */
-#define portDISABLE_INTERRUPTS() __asm ( "DI" )
-#define portENABLE_INTERRUPTS()  __asm ( "EI" )
+#define portDISABLE_INTERRUPTS()    __asm( "DI" )
+#define portENABLE_INTERRUPTS()     __asm( "EI" )
 /*-----------------------------------------------------------*/
 
 /* Critical section control macros. */
-#define portNO_CRITICAL_SECTION_NESTING     ( ( uint16_t ) 0 )
+#define portNO_CRITICAL_SECTION_NESTING    ( ( uint16_t ) 0 )
 
-#define portENTER_CRITICAL()                                                    \
-{                                                                               \
-extern volatile uint16_t usCriticalNesting;                         \
-                                                                                \
-    portDISABLE_INTERRUPTS();                                                   \
-                                                                                \
-    /* Now interrupts are disabled ulCriticalNesting can be accessed */         \
-    /* directly.  Increment ulCriticalNesting to keep a count of how many */    \
-    /* times portENTER_CRITICAL() has been called. */                           \
-    usCriticalNesting++;                                                        \
-}
+#define portENTER_CRITICAL()                                                      \
+    {                                                                             \
+        extern volatile uint16_t usCriticalNesting;                               \
+                                                                                  \
+        portDISABLE_INTERRUPTS();                                                 \
+                                                                                  \
+        /* Now that interrupts are disabled, ulCriticalNesting can be accessed */ \
+        /* directly.  Increment ulCriticalNesting to keep a count of how many */  \
+        /* times portENTER_CRITICAL() has been called. */                         \
+        usCriticalNesting++;                                                      \
+    }
 
-#define portEXIT_CRITICAL()                                                     \
-{                                                                               \
-extern volatile uint16_t usCriticalNesting;                         \
-                                                                                \
-    if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING )                   \
-    {                                                                           \
-        /* Decrement the nesting count as we are leaving a critical section. */ \
-        usCriticalNesting--;                                                    \
-                                                                                \
-        /* If the nesting level has reached zero then interrupts should be */   \
-        /* re-enabled. */                                                       \
-        if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING )              \
-        {                                                                       \
-            portENABLE_INTERRUPTS();                                            \
-        }                                                                       \
-    }                                                                           \
-}
+#define portEXIT_CRITICAL()                                                         \
+    {                                                                               \
+        extern volatile uint16_t usCriticalNesting;                                 \
+                                                                                    \
+        if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING )                   \
+        {                                                                           \
+            /* Decrement the nesting count as we are leaving a critical section. */ \
+            usCriticalNesting--;                                                    \
+                                                                                    \
+            /* If the nesting level has reached zero then interrupts should be */   \
+            /* re-enabled. */                                                       \
+            if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING )              \
+            {                                                                       \
+                portENABLE_INTERRUPTS();                                            \
+            }                                                                       \
+        }                                                                           \
+    }
 /*-----------------------------------------------------------*/
 
 /* Task utilities. */
 extern void vPortStart( void );
-#define portYIELD() __asm( "BRK" )
-#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) do { if( xHigherPriorityTaskWoken ) vTaskSwitchContext(); } while( 0 )
-#define portNOP()   __asm( "NOP" )
+#define portYIELD()                                       __asm( "BRK" )
+#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken )    do { if( xHigherPriorityTaskWoken ) vTaskSwitchContext( ); } while( 0 )
+#define portNOP()                                         __asm( "NOP" )
 /*-----------------------------------------------------------*/
 
-/* Hardwware specifics. */
-#define portBYTE_ALIGNMENT  2
-#define portSTACK_GROWTH    ( -1 )
-#define portTICK_PERIOD_MS  ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT    2
+#define portSTACK_GROWTH      ( -1 )
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
 
-static __interrupt void P0_isr   (void);
+static __interrupt void P0_isr( void );
 
 /* --------------------------------------------------------------------------*/
 /* Option-bytes and security ID                                              */
 /* --------------------------------------------------------------------------*/
-#define OPT_BYTES_SIZE     4
-#define SECU_ID_SIZE       10
-#define WATCHDOG_DISABLED  0x00
-#define LVI_ENABLED        0xFE
-#define LVI_DISABLED       0xFF
-#define RESERVED_FF        0xFF
-#define OCD_DISABLED       0x04
-#define OCD_ENABLED        0x81
-#define OCD_ENABLED_ERASE  0x80
+#define OPT_BYTES_SIZE       4
+#define SECU_ID_SIZE         10
+#define WATCHDOG_DISABLED    0x00
+#define LVI_ENABLED          0xFE
+#define LVI_DISABLED         0xFF
+#define RESERVED_FF          0xFF
+#define OCD_DISABLED         0x04
+#define OCD_ENABLED          0x81
+#define OCD_ENABLED_ERASE    0x80
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/IAR/ARM_CA5_No_GIC/port.c b/portable/IAR/ARM_CA5_No_GIC/port.c
index b1c21586d..3cb7c0db2 100644
--- a/portable/IAR/ARM_CA5_No_GIC/port.c
+++ b/portable/IAR/ARM_CA5_No_GIC/port.c
@@ -35,7 +35,7 @@
 
 #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
     /* Check the configuration. */
-    #if( configMAX_PRIORITIES > 32 )
+    #if ( configMAX_PRIORITIES > 32 )
         #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
     #endif
 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
@@ -49,27 +49,27 @@
 #endif
 
 /* A critical section is exited when the critical section nesting count reaches
-this value. */
-#define portNO_CRITICAL_NESTING         ( ( uint32_t ) 0 )
+ * this value. */
+#define portNO_CRITICAL_NESTING          ( ( uint32_t ) 0 )
 
 /* Tasks are not created with a floating point context, but can be given a
-floating point context after they have been created.  A variable is stored as
-part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
-does not have an FPU context, or any other value if the task does have an FPU
-context. */
-#define portNO_FLOATING_POINT_CONTEXT   ( ( StackType_t ) 0 )
+ * floating point context after they have been created.  A variable is stored as
+ * part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
+ * does not have an FPU context, or any other value if the task does have an FPU
+ * context. */
+#define portNO_FLOATING_POINT_CONTEXT    ( ( StackType_t ) 0 )
 
 /* Constants required to setup the initial task context. */
-#define portINITIAL_SPSR                ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
-#define portTHUMB_MODE_BIT              ( ( StackType_t ) 0x20 )
-#define portTHUMB_MODE_ADDRESS          ( 0x01UL )
+#define portINITIAL_SPSR                 ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT               ( ( StackType_t ) 0x20 )
+#define portTHUMB_MODE_ADDRESS           ( 0x01UL )
 
 /* Masks all bits in the APSR other than the mode bits. */
-#define portAPSR_MODE_BITS_MASK         ( 0x1F )
+#define portAPSR_MODE_BITS_MASK          ( 0x1F )
 
 /* The value of the mode bits in the APSR when the CPU is executing in user
-mode. */
-#define portAPSR_USER_MODE              ( 0x10 )
+ * mode. */
+#define portAPSR_USER_MODE               ( 0x10 )
 
 /*-----------------------------------------------------------*/
 
@@ -87,21 +87,21 @@ static void prvTaskExitError( void );
 /*-----------------------------------------------------------*/
 
 /* A variable is used to keep track of the critical section nesting.  This
-variable has to be stored as part of the task context and must be initialised to
-a non zero value to ensure interrupts don't inadvertently become unmasked before
-the scheduler starts.  As it is stored as part of the task context it will
-automatically be set to 0 when the first task is started. */
+ * variable has to be stored as part of the task context and must be initialised to
+ * a non zero value to ensure interrupts don't inadvertently become unmasked before
+ * the scheduler starts.  As it is stored as part of the task context it will
+ * automatically be set to 0 when the first task is started. */
 volatile uint32_t ulCriticalNesting = 9999UL;
 
 /* Saved as part of the task context.  If ulPortTaskHasFPUContext is non-zero
-then a floating point context must be saved and restored for the task. */
+ * then a floating point context must be saved and restored for the task. */
 uint32_t ulPortTaskHasFPUContext = pdFALSE;
 
 /* Set to 1 to pend a context switch from an ISR. */
 uint32_t ulPortYieldRequired = pdFALSE;
 
 /* Counts the interrupt nesting depth.  A context switch is only performed if
-if the nesting depth is 0. */
+ * if the nesting depth is 0. */
 uint32_t ulPortInterruptNesting = 0UL;
 
 
@@ -110,14 +110,16 @@ uint32_t ulPortInterruptNesting = 0UL;
 /*
  * See header file for description.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
     /* Setup the initial stack of the task.  The stack is set exactly as
-    expected by the portRESTORE_CONTEXT() macro.
-
-    The fist real value on the stack is the status register, which is set for
-    system mode, with interrupts enabled.  A few NULLs are added first to ensure
-    GDB does not try decoding a non-existent return address. */
+     * expected by the portRESTORE_CONTEXT() macro.
+     *
+     * The fist real value on the stack is the status register, which is set for
+     * system mode, with interrupts enabled.  A few NULLs are added first to ensure
+     * GDB does not try decoding a non-existent return address. */
     *pxTopOfStack = NULL;
     pxTopOfStack--;
     *pxTopOfStack = NULL;
@@ -139,43 +141,43 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
     pxTopOfStack--;
 
     /* Next all the registers other than the stack pointer. */
-    *pxTopOfStack = ( StackType_t ) prvTaskExitError;   /* R14 */
+    *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* R14 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
+    *pxTopOfStack = ( StackType_t ) 0x12121212;       /* R12 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
+    *pxTopOfStack = ( StackType_t ) 0x11111111;       /* R11 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
+    *pxTopOfStack = ( StackType_t ) 0x10101010;       /* R10 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
+    *pxTopOfStack = ( StackType_t ) 0x09090909;       /* R9 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
+    *pxTopOfStack = ( StackType_t ) 0x08080808;       /* R8 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
+    *pxTopOfStack = ( StackType_t ) 0x07070707;       /* R7 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
+    *pxTopOfStack = ( StackType_t ) 0x06060606;       /* R6 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
+    *pxTopOfStack = ( StackType_t ) 0x05050505;       /* R5 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
+    *pxTopOfStack = ( StackType_t ) 0x04040404;       /* R4 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
+    *pxTopOfStack = ( StackType_t ) 0x03030303;       /* R3 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
+    *pxTopOfStack = ( StackType_t ) 0x02020202;       /* R2 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
+    *pxTopOfStack = ( StackType_t ) 0x01010101;       /* R1 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+    *pxTopOfStack = ( StackType_t ) pvParameters;     /* R0 */
     pxTopOfStack--;
 
     /* The task will start with a critical nesting count of 0 as interrupts are
-    enabled. */
+     * enabled. */
     *pxTopOfStack = portNO_CRITICAL_NESTING;
     pxTopOfStack--;
 
     /* The task will start without a floating point context.  A task that uses
-    the floating point hardware must call vPortTaskUsesFPU() before executing
-    any floating point instructions. */
+     * the floating point hardware must call vPortTaskUsesFPU() before executing
+     * any floating point instructions. */
     *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
 
     return pxTopOfStack;
@@ -185,24 +187,28 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
 static void prvTaskExitError( void )
 {
     /* A function that implements a task must not exit or attempt to return to
-    its caller as there is nothing to return to.  If a task wants to exit it
-    should instead call vTaskDelete( NULL ).
-
-    Artificially force an assert() to be triggered if configASSERT() is
-    defined, then stop here so application writers can catch the error. */
+     * its caller as there is nothing to return to.  If a task wants to exit it
+     * should instead call vTaskDelete( NULL ).
+     *
+     * Artificially force an assert() to be triggered if configASSERT() is
+     * defined, then stop here so application writers can catch the error. */
     configASSERT( ulPortInterruptNesting == ~0UL );
     portDISABLE_INTERRUPTS();
-    for( ;; );
+
+    for( ; ; )
+    {
+    }
 }
 /*-----------------------------------------------------------*/
 
 BaseType_t xPortStartScheduler( void )
 {
-uint32_t ulAPSR;
+    uint32_t ulAPSR;
 
     /* Only continue if the CPU is not in User mode.  The CPU must be in a
-    Privileged mode for the scheduler to start. */
+     * Privileged mode for the scheduler to start. */
     __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) );
+
     ulAPSR &= portAPSR_MODE_BITS_MASK;
     configASSERT( ulAPSR != portAPSR_USER_MODE );
 
@@ -214,8 +220,8 @@ uint32_t ulAPSR;
     }
 
     /* Will only get here if vTaskStartScheduler() was called with the CPU in
-    a non-privileged mode or the binary point register was not set to its lowest
-    possible value. */
+     * a non-privileged mode or the binary point register was not set to its lowest
+     * possible value. */
     return 0;
 }
 /*-----------------------------------------------------------*/
@@ -223,7 +229,7 @@ uint32_t ulAPSR;
 void vPortEndScheduler( void )
 {
     /* Not implemented in ports where there is nothing to return to.
-    Artificially force an assert. */
+     * Artificially force an assert. */
     configASSERT( ulCriticalNesting == 1000UL );
 }
 /*-----------------------------------------------------------*/
@@ -232,16 +238,16 @@ void vPortEnterCritical( void )
 {
     portDISABLE_INTERRUPTS();
 
-    /* Now interrupts are disabled ulCriticalNesting can be accessed
-    directly.  Increment ulCriticalNesting to keep a count of how many times
-    portENTER_CRITICAL() has been called. */
+    /* Now that interrupts are disabled, ulCriticalNesting can be accessed
+     * directly.  Increment ulCriticalNesting to keep a count of how many times
+     * portENTER_CRITICAL() has been called. */
     ulCriticalNesting++;
 
     /* This is not the interrupt safe version of the enter critical function so
-    assert() if it is being called from an interrupt context.  Only API
-    functions that end in "FromISR" can be used in an interrupt.  Only assert if
-    the critical nesting count is 1 to protect against recursive calls if the
-    assert function also uses a critical section. */
+     * assert() if it is being called from an interrupt context.  Only API
+     * functions that end in "FromISR" can be used in an interrupt.  Only assert if
+     * the critical nesting count is 1 to protect against recursive calls if the
+     * assert function also uses a critical section. */
     if( ulCriticalNesting == 1 )
     {
         configASSERT( ulPortInterruptNesting == 0 );
@@ -254,15 +260,15 @@ void vPortExitCritical( void )
     if( ulCriticalNesting > portNO_CRITICAL_NESTING )
     {
         /* Decrement the nesting count as the critical section is being
-        exited. */
+         * exited. */
         ulCriticalNesting--;
 
         /* If the nesting level has reached zero then all interrupt
-        priorities must be re-enabled. */
+         * priorities must be re-enabled. */
         if( ulCriticalNesting == portNO_CRITICAL_NESTING )
         {
             /* Critical nesting has reached zero so all interrupt priorities
-            should be unmasked. */
+             * should be unmasked. */
             portENABLE_INTERRUPTS();
         }
     }
@@ -286,13 +292,13 @@ void FreeRTOS_Tick_Handler( void )
 
 void vPortTaskUsesFPU( void )
 {
-uint32_t ulInitialFPSCR = 0;
+    uint32_t ulInitialFPSCR = 0;
 
     /* A task is registering the fact that it needs an FPU context.  Set the
-    FPU flag (which is saved as part of the task context). */
+     * FPU flag (which is saved as part of the task context). */
     ulPortTaskHasFPUContext = pdTRUE;
 
     /* Initialise the floating point status register. */
-    __asm( "FMXR    FPSCR, %0" :: "r" (ulInitialFPSCR) );
+    __asm( "FMXR    FPSCR, %0" ::"r" ( ulInitialFPSCR ) );
 }
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CA5_No_GIC/portASM.h b/portable/IAR/ARM_CA5_No_GIC/portASM.h
index 1a9006df3..85050e523 100644
--- a/portable/IAR/ARM_CA5_No_GIC/portASM.h
+++ b/portable/IAR/ARM_CA5_No_GIC/portASM.h
@@ -1,109 +1,158 @@
-;/*
-; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
-; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
-; *
-; * SPDX-License-Identifier: MIT
-; *
-; * Permission is hereby granted, free of charge, to any person obtaining a copy of
-; * this software and associated documentation files (the "Software"), to deal in
-; * the Software without restriction, including without limitation the rights to
-; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
-; * the Software, and to permit persons to whom the Software is furnished to do so,
-; * subject to the following conditions:
-; *
-; * The above copyright notice and this permission notice shall be included in all
-; * copies or substantial portions of the Software.
-; *
-; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-; *
-; * https://www.FreeRTOS.org
-; * https://github.com/FreeRTOS
-; *
-; */
+; /*
+   * ; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+   * ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+   * ; *
+   * ; * SPDX-License-Identifier: MIT
+   * ; *
+   * ; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+   * ; * this software and associated documentation files (the "Software"), to deal in
+   * ; * the Software without restriction, including without limitation the rights to
+   * ; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+   * ; * the Software, and to permit persons to whom the Software is furnished to do so,
+   * ; * subject to the following conditions:
+   * ; *
+   * ; * The above copyright notice and this permission notice shall be included in all
+   * ; * copies or substantial portions of the Software.
+   * ; *
+   * ; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+   * ; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+   * ; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+   * ; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+   * ; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+   * ; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+   * ; *
+   * ; * https://www.FreeRTOS.org
+   * ; * https://github.com/FreeRTOS
+   * ; *
+   * ; */
 
-    EXTERN  vTaskSwitchContext
-    EXTERN  ulCriticalNesting
-    EXTERN  pxCurrentTCB
-    EXTERN  ulPortTaskHasFPUContext
-    EXTERN  ulAsmAPIPriorityMask
+EXTERN vTaskSwitchContext
+EXTERN ulCriticalNesting
+EXTERN pxCurrentTCB
+EXTERN ulPortTaskHasFPUContext
+EXTERN ulAsmAPIPriorityMask
 
 portSAVE_CONTEXT macro
 
-    ; Save the LR and SPSR onto the system mode stack before switching to
-    ; system mode to save the remaining system mode registers
-    SRSDB   sp!, #SYS_MODE
-    CPS     #SYS_MODE
-    PUSH    {R0-R12, R14}
+;
+Save the LR and SPSR onto the system mode stack before switching to
+;
+system mode to save the remaining system mode registers
+SRSDB sp !, # SYS_MODE
+      CPS     # SYS_MODE
+      PUSH    {
+    R0 - R12, R14
+}
 
-    ; Push the critical nesting count
-    LDR     R2, =ulCriticalNesting
-    LDR     R1, [R2]
-    PUSH    {R1}
+;
+Push the critical nesting count
+LDR R2, = ulCriticalNesting
+          LDR R1, [ R2 ]
+PUSH    {
+    R1
+}
 
-    ; Does the task have a floating point context that needs saving?  If
-    ; ulPortTaskHasFPUContext is 0 then no.
-    LDR     R2, =ulPortTaskHasFPUContext
-    LDR     R3, [R2]
-    CMP     R3, #0
+;
+Does the task have a floating point context that needs saving ? If
+;
+ulPortTaskHasFPUContext is 0 then no.
+   LDR R2, = ulPortTaskHasFPUContext
+             LDR R3, [ R2 ]
+CMP R3, # 0
+
+;
+Save the floating point context,
+
+if any
+FMRXNE R1, FPSCR
+                        VPUSHNE {
+    D0 - D15
+}
 
-    ; Save the floating point context, if any
-    FMRXNE  R1,  FPSCR
-    VPUSHNE {D0-D15}
 #if configFPU_D32 == 1
-    VPUSHNE {D16-D31}
-#endif ; configFPU_D32
-    PUSHNE  {R1}
+VPUSHNE {
+    D16 - D31
+}
+#endif; configFPU_D32
+PUSHNE  {
+    R1
+}
 
-    ; Save ulPortTaskHasFPUContext itself
-    PUSH    {R3}
+;
+Save ulPortTaskHasFPUContext itself
+    PUSH    {
+    R3
+}
 
-    ; Save the stack pointer in the TCB
-    LDR     R0, =pxCurrentTCB
-    LDR     R1, [R0]
-    STR     SP, [R1]
+;
+Save the stack pointer in the TCB
+LDR R0, = pxCurrentTCB
+          LDR R1, [ R0 ]
+STR SP, [ R1 ]
 
-    endm
+endm
 
 ; /**********************************************************************/
 
 portRESTORE_CONTEXT macro
 
-    ; Set the SP to point to the stack of the task being restored.
-    LDR     R0, =pxCurrentTCB
-    LDR     R1, [R0]
-    LDR     SP, [R1]
+;
+Set the SP to point to the stack of the task being restored.
+   LDR R0, = pxCurrentTCB
+             LDR R1, [ R0 ]
+LDR SP, [ R1 ]
 
-    ; Is there a floating point context to restore?  If the restored
-    ; ulPortTaskHasFPUContext is zero then no.
-    LDR     R0, =ulPortTaskHasFPUContext
-    POP     {R1}
-    STR     R1, [R0]
-    CMP     R1, #0
+;
+Is there a floating point context to restore ? If the restored
+;
+ulPortTaskHasFPUContext is zero then no.
+   LDR R0, = ulPortTaskHasFPUContext
+             POP     {
+    R1
+}
+STR R1, [ R0 ]
+CMP R1, # 0
+
+;
+Restore the floating point context,
+
+if any
+                           POPNE   {
+    R0
+}
 
-    ; Restore the floating point context, if any
-    POPNE   {R0}
 #if configFPU_D32 == 1
-    VPOPNE  {D16-D31}
-#endif ; configFPU_D32
-    VPOPNE  {D0-D15}
-    VMSRNE  FPSCR, R0
+VPOPNE  {
+    D16 - D31
+}
+#endif; configFPU_D32
+VPOPNE  {
+    D0 - D15
+}
+VMSRNE FPSCR, R0
 
-    ; Restore the critical section nesting depth
-    LDR     R0, =ulCriticalNesting
-    POP     {R1}
-    STR     R1, [R0]
+;
+Restore the critical section nesting depth
+LDR R0, = ulCriticalNesting
+          POP     {
+    R1
+}
+STR R1, [ R0 ]
 
-    ; Restore all system mode registers other than the SP (which is already
-    ; being used)
-    POP     {R0-R12, R14}
+;
+Restore all system mode registers other than the SP( which is already
+                                                     ;
+                                                     being used )
+POP
+{
+    R0 - R12, R14
+}
 
-    ; Return to the task code, loading CPSR on the way.  CPSR has the interrupt
-    ; enable bit set appropriately for the task about to execute.
-    RFEIA   sp!
+Return to the task code, loading CPSR on the way.CPSR has the interrupt
+;
+enable bit set appropriately
 
-    endm
+for the task about to execute.
+   RFEIA sp !
+
+endm
diff --git a/portable/IAR/ARM_CA5_No_GIC/portmacro.h b/portable/IAR/ARM_CA5_No_GIC/portmacro.h
index b1dcf3878..82794345d 100644
--- a/portable/IAR/ARM_CA5_No_GIC/portmacro.h
+++ b/portable/IAR/ARM_CA5_No_GIC/portmacro.h
@@ -42,117 +42,117 @@
 
 
 
-    /*-----------------------------------------------------------
-     * Port specific definitions.
-     *
-     * The settings in this file configure FreeRTOS correctly for the given hardware
-     * and compiler.
-     *
-     * These settings should not be altered.
-     *-----------------------------------------------------------
-     */
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
 
-    /* Type definitions. */
-    #define portCHAR        char
-    #define portFLOAT       float
-    #define portDOUBLE      double
-    #define portLONG        long
-    #define portSHORT       short
-    #define portSTACK_TYPE  uint32_t
-    #define portBASE_TYPE   long
+/* Type definitions. */
+    #define portCHAR          char
+    #define portFLOAT         float
+    #define portDOUBLE        double
+    #define portLONG          long
+    #define portSHORT         short
+    #define portSTACK_TYPE    uint32_t
+    #define portBASE_TYPE     long
 
-    typedef portSTACK_TYPE StackType_t;
-    typedef long BaseType_t;
-    typedef unsigned long UBaseType_t;
+    typedef portSTACK_TYPE   StackType_t;
+    typedef long             BaseType_t;
+    typedef unsigned long    UBaseType_t;
 
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+    typedef uint32_t         TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-    not need to be guarded with a critical section. */
-    #define portTICK_TYPE_IS_ATOMIC 1
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+    #define portTICK_TYPE_IS_ATOMIC    1
 
-    /*-----------------------------------------------------------*/
+/*-----------------------------------------------------------*/
 
-    /* Hardware specifics. */
-    #define portSTACK_GROWTH            ( -1 )
-    #define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-    #define portBYTE_ALIGNMENT          8
+/* Hardware specifics. */
+    #define portSTACK_GROWTH      ( -1 )
+    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+    #define portBYTE_ALIGNMENT    8
 
-    /*-----------------------------------------------------------*/
+/*-----------------------------------------------------------*/
 
-    /* Task utilities. */
+/* Task utilities. */
 
-    /* Called at the end of an ISR that can cause a context switch. */
-    #define portEND_SWITCHING_ISR( xSwitchRequired )\
-    {                                               \
-    extern uint32_t ulPortYieldRequired;            \
-                                                    \
-        if( xSwitchRequired != pdFALSE )            \
-        {                                           \
-            ulPortYieldRequired = pdTRUE;           \
-        }                                           \
+/* Called at the end of an ISR that can cause a context switch. */
+    #define portEND_SWITCHING_ISR( xSwitchRequired ) \
+    {                                                \
+        extern uint32_t ulPortYieldRequired;         \
+                                                     \
+        if( xSwitchRequired != pdFALSE )             \
+        {                                            \
+            ulPortYieldRequired = pdTRUE;            \
+        }                                            \
     }
 
-    #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
-    #define portYIELD() __asm volatile ( "SWI 0" ); __ISB()
+    #define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
+    #define portYIELD()                __asm volatile ( "SWI 0" ); __ISB()
 
 
-    /*-----------------------------------------------------------
-     * Critical section control
-     *----------------------------------------------------------*/
+/*-----------------------------------------------------------
+* Critical section control
+*----------------------------------------------------------*/
 
     extern void vPortEnterCritical( void );
     extern void vPortExitCritical( void );
     extern uint32_t ulPortSetInterruptMask( void );
     extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
 
-    #define portENTER_CRITICAL()        vPortEnterCritical();
-    #define portEXIT_CRITICAL()         vPortExitCritical();
-    #define portDISABLE_INTERRUPTS()    __disable_irq(); __DSB(); __ISB() /* No priority mask register so global disable is used. */
-    #define portENABLE_INTERRUPTS()     __enable_irq()
-    #define portSET_INTERRUPT_MASK_FROM_ISR()       __get_interrupt_state(); __disable_irq() /* No priority mask register so global disable is used. */
-    #define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)    __set_interrupt_state(x)
+    #define portENTER_CRITICAL()                      vPortEnterCritical();
+    #define portEXIT_CRITICAL()                       vPortExitCritical();
+    #define portDISABLE_INTERRUPTS()                  __disable_irq(); __DSB(); __ISB()        /* No priority mask register so global disable is used. */
+    #define portENABLE_INTERRUPTS()                   __enable_irq()
+    #define portSET_INTERRUPT_MASK_FROM_ISR()         __get_interrupt_state(); __disable_irq() /* No priority mask register so global disable is used. */
+    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    __set_interrupt_state( x )
 
-    /*-----------------------------------------------------------*/
+/*-----------------------------------------------------------*/
 
-    /* Task function macros as described on the FreeRTOS.org WEB site.  These are
-    not required for this port but included in case common demo code that uses these
-    macros is used. */
-    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )  void vFunction( void *pvParameters )
-    #define portTASK_FUNCTION( vFunction, pvParameters )    void vFunction( void *pvParameters )
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+ * not required for this port but included in case common demo code that uses these
+ * macros is used. */
+    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
-    /* Prototype of the FreeRTOS tick handler.  This must be installed as the
-    handler for whichever peripheral is used to generate the RTOS tick. */
+/* Prototype of the FreeRTOS tick handler.  This must be installed as the
+ * handler for whichever peripheral is used to generate the RTOS tick. */
     void FreeRTOS_Tick_Handler( void );
 
-    /* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
-    before any floating point instructions are executed. */
+/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
+ * before any floating point instructions are executed. */
     void vPortTaskUsesFPU( void );
-    #define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
+    #define portTASK_USES_FLOATING_POINT()    vPortTaskUsesFPU()
 
-    /* Architecture specific optimisations. */
+/* Architecture specific optimisations. */
     #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
     #endif
 
     #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
 
-        /* Store/clear the ready priorities in a bit map. */
-        #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-        #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+/* Store/clear the ready priorities in a bit map. */
+        #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+        #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 
-        /*-----------------------------------------------------------*/
+/*-----------------------------------------------------------*/
 
-        #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __CLZ( uxReadyPriorities ) )
+        #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31 - __CLZ( uxReadyPriorities ) )
 
     #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 
-    #define portNOP() __asm volatile( "NOP" )
+    #define portNOP()    __asm volatile ( "NOP" )
 
-    /* Suppress warnings that are generated by the IAR tools, but cannot be
-    fixed in the source code because to do so would cause other compilers to
-    generate warnings. */
+/* Suppress warnings that are generated by the IAR tools, but cannot be
+ * fixed in the source code because to do so would cause other compilers to
+ * generate warnings. */
     #pragma diag_suppress=Pe191
     #pragma diag_suppress=Pa082
 
diff --git a/portable/IAR/ARM_CA9/port.c b/portable/IAR/ARM_CA9/port.c
index aa6fcf881..3f87288ae 100644
--- a/portable/IAR/ARM_CA9/port.c
+++ b/portable/IAR/ARM_CA9/port.c
@@ -37,43 +37,43 @@
 #include "task.h"
 
 #ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS
-    #error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+    #error "configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined.  See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
 #endif
 
 #ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET
-    #error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+    #error "configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined.  See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
 #endif
 
 #ifndef configUNIQUE_INTERRUPT_PRIORITIES
-    #error configUNIQUE_INTERRUPT_PRIORITIES must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+    #error "configUNIQUE_INTERRUPT_PRIORITIES must be defined.  See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
 #endif
 
 #ifndef configSETUP_TICK_INTERRUPT
-    #error configSETUP_TICK_INTERRUPT() must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+    #error "configSETUP_TICK_INTERRUPT() must be defined.  See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
 #endif /* configSETUP_TICK_INTERRUPT */
 
 #ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
-    #error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+    #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be defined.  See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
 #endif
 
 #if configMAX_API_CALL_INTERRUPT_PRIORITY == 0
-    #error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0
+    #error "configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0"
 #endif
 
 #if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES
-    #error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority
+    #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority"
 #endif
 
 #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
     /* Check the configuration. */
-    #if( configMAX_PRIORITIES > 32 )
-        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+    #if ( configMAX_PRIORITIES > 32 )
+        #error "configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice."
     #endif
 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 
 /* In case security extensions are implemented. */
 #if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
-    #error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
+    #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )"
 #endif
 
 #ifndef configCLEAR_TICK_INTERRUPT
@@ -81,45 +81,45 @@
 #endif
 
 /* A critical section is exited when the critical section nesting count reaches
-this value. */
-#define portNO_CRITICAL_NESTING         ( ( uint32_t ) 0 )
+ * this value. */
+#define portNO_CRITICAL_NESTING          ( ( uint32_t ) 0 )
 
 /* In all GICs 255 can be written to the priority mask register to unmask all
-(but the lowest) interrupt priority. */
-#define portUNMASK_VALUE                ( 0xFFUL )
+ * (but the lowest) interrupt priority. */
+#define portUNMASK_VALUE                 ( 0xFFUL )
 
 /* Tasks are not created with a floating point context, but can be given a
-floating point context after they have been created.  A variable is stored as
-part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
-does not have an FPU context, or any other value if the task does have an FPU
-context. */
-#define portNO_FLOATING_POINT_CONTEXT   ( ( StackType_t ) 0 )
+ * floating point context after they have been created.  A variable is stored as
+ * part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
+ * does not have an FPU context, or any other value if the task does have an FPU
+ * context. */
+#define portNO_FLOATING_POINT_CONTEXT    ( ( StackType_t ) 0 )
 
 /* Constants required to setup the initial task context. */
-#define portINITIAL_SPSR                ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
-#define portTHUMB_MODE_BIT              ( ( StackType_t ) 0x20 )
-#define portTHUMB_MODE_ADDRESS          ( 0x01UL )
+#define portINITIAL_SPSR                 ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT               ( ( StackType_t ) 0x20 )
+#define portTHUMB_MODE_ADDRESS           ( 0x01UL )
 
 /* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary
-point is zero. */
-#define portBINARY_POINT_BITS           ( ( uint8_t ) 0x03 )
+ * point is zero. */
+#define portBINARY_POINT_BITS            ( ( uint8_t ) 0x03 )
 
 /* Masks all bits in the APSR other than the mode bits. */
-#define portAPSR_MODE_BITS_MASK         ( 0x1F )
+#define portAPSR_MODE_BITS_MASK          ( 0x1F )
 
 /* The value of the mode bits in the APSR when the CPU is executing in user
-mode. */
-#define portAPSR_USER_MODE              ( 0x10 )
+ * mode. */
+#define portAPSR_USER_MODE               ( 0x10 )
 
 /* Macro to unmask all interrupt priorities. */
-#define portCLEAR_INTERRUPT_MASK()                                          \
-{                                                                           \
-    __disable_irq();                                                        \
-    portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE;                   \
-    __asm(  "DSB        \n"                                                 \
-            "ISB        \n" );                                              \
-    __enable_irq();                                                         \
-}
+#define portCLEAR_INTERRUPT_MASK()                            \
+    {                                                         \
+        __disable_irq();                                      \
+        portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \
+        __asm( "DSB        \n"                                \
+               "ISB        \n" );                             \
+        __enable_irq();                                       \
+    }
 
 /*-----------------------------------------------------------*/
 
@@ -137,21 +137,21 @@ static void prvTaskExitError( void );
 /*-----------------------------------------------------------*/
 
 /* A variable is used to keep track of the critical section nesting.  This
-variable has to be stored as part of the task context and must be initialised to
-a non zero value to ensure interrupts don't inadvertently become unmasked before
-the scheduler starts.  As it is stored as part of the task context it will
-automatically be set to 0 when the first task is started. */
+ * variable has to be stored as part of the task context and must be initialised to
+ * a non zero value to ensure interrupts don't inadvertently become unmasked before
+ * the scheduler starts.  As it is stored as part of the task context it will
+ * automatically be set to 0 when the first task is started. */
 volatile uint32_t ulCriticalNesting = 9999UL;
 
 /* Saved as part of the task context.  If ulPortTaskHasFPUContext is non-zero
-then a floating point context must be saved and restored for the task. */
+ * then a floating point context must be saved and restored for the task. */
 uint32_t ulPortTaskHasFPUContext = pdFALSE;
 
 /* Set to 1 to pend a context switch from an ISR. */
 uint32_t ulPortYieldRequired = pdFALSE;
 
 /* Counts the interrupt nesting depth.  A context switch is only performed if
-if the nesting depth is 0. */
+ * if the nesting depth is 0. */
 uint32_t ulPortInterruptNesting = 0UL;
 
 
@@ -160,14 +160,16 @@ uint32_t ulPortInterruptNesting = 0UL;
 /*
  * See header file for description.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
     /* Setup the initial stack of the task.  The stack is set exactly as
-    expected by the portRESTORE_CONTEXT() macro.
-
-    The fist real value on the stack is the status register, which is set for
-    system mode, with interrupts enabled.  A few NULLs are added first to ensure
-    GDB does not try decoding a non-existent return address. */
+     * expected by the portRESTORE_CONTEXT() macro.
+     *
+     * The fist real value on the stack is the status register, which is set for
+     * system mode, with interrupts enabled.  A few NULLs are added first to ensure
+     * GDB does not try decoding a non-existent return address. */
     *pxTopOfStack = NULL;
     pxTopOfStack--;
     *pxTopOfStack = NULL;
@@ -189,43 +191,43 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
     pxTopOfStack--;
 
     /* Next all the registers other than the stack pointer. */
-    *pxTopOfStack = ( StackType_t ) prvTaskExitError;   /* R14 */
+    *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* R14 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
+    *pxTopOfStack = ( StackType_t ) 0x12121212;       /* R12 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
+    *pxTopOfStack = ( StackType_t ) 0x11111111;       /* R11 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
+    *pxTopOfStack = ( StackType_t ) 0x10101010;       /* R10 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
+    *pxTopOfStack = ( StackType_t ) 0x09090909;       /* R9 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
+    *pxTopOfStack = ( StackType_t ) 0x08080808;       /* R8 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
+    *pxTopOfStack = ( StackType_t ) 0x07070707;       /* R7 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
+    *pxTopOfStack = ( StackType_t ) 0x06060606;       /* R6 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
+    *pxTopOfStack = ( StackType_t ) 0x05050505;       /* R5 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
+    *pxTopOfStack = ( StackType_t ) 0x04040404;       /* R4 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
+    *pxTopOfStack = ( StackType_t ) 0x03030303;       /* R3 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
+    *pxTopOfStack = ( StackType_t ) 0x02020202;       /* R2 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
+    *pxTopOfStack = ( StackType_t ) 0x01010101;       /* R1 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+    *pxTopOfStack = ( StackType_t ) pvParameters;     /* R0 */
     pxTopOfStack--;
 
     /* The task will start with a critical nesting count of 0 as interrupts are
-    enabled. */
+     * enabled. */
     *pxTopOfStack = portNO_CRITICAL_NESTING;
     pxTopOfStack--;
 
     /* The task will start without a floating point context.  A task that uses
-    the floating point hardware must call vPortTaskUsesFPU() before executing
-    any floating point instructions. */
+     * the floating point hardware must call vPortTaskUsesFPU() before executing
+     * any floating point instructions. */
     *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
 
     return pxTopOfStack;
@@ -235,32 +237,36 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
 static void prvTaskExitError( void )
 {
     /* A function that implements a task must not exit or attempt to return to
-    its caller as there is nothing to return to.  If a task wants to exit it
-    should instead call vTaskDelete( NULL ).
-
-    Artificially force an assert() to be triggered if configASSERT() is
-    defined, then stop here so application writers can catch the error. */
+     * its caller as there is nothing to return to.  If a task wants to exit it
+     * should instead call vTaskDelete( NULL ).
+     *
+     * Artificially force an assert() to be triggered if configASSERT() is
+     * defined, then stop here so application writers can catch the error. */
     configASSERT( ulPortInterruptNesting == ~0UL );
     portDISABLE_INTERRUPTS();
-    for( ;; );
+
+    for( ; ; )
+    {
+    }
 }
 /*-----------------------------------------------------------*/
 
 BaseType_t xPortStartScheduler( void )
 {
-uint32_t ulAPSR;
+    uint32_t ulAPSR;
 
     /* Only continue if the CPU is not in User mode.  The CPU must be in a
-    Privileged mode for the scheduler to start. */
+     * Privileged mode for the scheduler to start. */
     __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) );
+
     ulAPSR &= portAPSR_MODE_BITS_MASK;
     configASSERT( ulAPSR != portAPSR_USER_MODE );
 
     if( ulAPSR != portAPSR_USER_MODE )
     {
         /* Only continue if the binary point value is set to its lowest possible
-        setting.  See the comments in vPortValidateInterruptPriority() below for
-        more information. */
+         * setting.  See the comments in vPortValidateInterruptPriority() below for
+         * more information. */
         configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
 
         if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )
@@ -274,8 +280,8 @@ uint32_t ulAPSR;
     }
 
     /* Will only get here if vTaskStartScheduler() was called with the CPU in
-    a non-privileged mode or the binary point register was not set to its lowest
-    possible value. */
+     * a non-privileged mode or the binary point register was not set to its lowest
+     * possible value. */
     return 0;
 }
 /*-----------------------------------------------------------*/
@@ -283,7 +289,7 @@ uint32_t ulAPSR;
 void vPortEndScheduler( void )
 {
     /* Not implemented in ports where there is nothing to return to.
-    Artificially force an assert. */
+     * Artificially force an assert. */
     configASSERT( ulCriticalNesting == 1000UL );
 }
 /*-----------------------------------------------------------*/
@@ -293,16 +299,16 @@ void vPortEnterCritical( void )
     /* Disable interrupts as per portDISABLE_INTERRUPTS();  */
     ulPortSetInterruptMask();
 
-    /* Now interrupts are disabled ulCriticalNesting can be accessed
-    directly.  Increment ulCriticalNesting to keep a count of how many times
-    portENTER_CRITICAL() has been called. */
+    /* Now that interrupts are disabled, ulCriticalNesting can be accessed
+     * directly.  Increment ulCriticalNesting to keep a count of how many times
+     * portENTER_CRITICAL() has been called. */
     ulCriticalNesting++;
 
     /* This is not the interrupt safe version of the enter critical function so
-    assert() if it is being called from an interrupt context.  Only API
-    functions that end in "FromISR" can be used in an interrupt.  Only assert if
-    the critical nesting count is 1 to protect against recursive calls if the
-    assert function also uses a critical section. */
+     * assert() if it is being called from an interrupt context.  Only API
+     * functions that end in "FromISR" can be used in an interrupt.  Only assert if
+     * the critical nesting count is 1 to protect against recursive calls if the
+     * assert function also uses a critical section. */
     if( ulCriticalNesting == 1 )
     {
         configASSERT( ulPortInterruptNesting == 0 );
@@ -315,15 +321,15 @@ void vPortExitCritical( void )
     if( ulCriticalNesting > portNO_CRITICAL_NESTING )
     {
         /* Decrement the nesting count as the critical section is being
-        exited. */
+         * exited. */
         ulCriticalNesting--;
 
         /* If the nesting level has reached zero then all interrupt
-        priorities must be re-enabled. */
+         * priorities must be re-enabled. */
         if( ulCriticalNesting == portNO_CRITICAL_NESTING )
         {
             /* Critical nesting has reached zero so all interrupt priorities
-            should be unmasked. */
+             * should be unmasked. */
             portCLEAR_INTERRUPT_MASK();
         }
     }
@@ -333,12 +339,12 @@ void vPortExitCritical( void )
 void FreeRTOS_Tick_Handler( void )
 {
     /* Set interrupt mask before altering scheduler structures.   The tick
-    handler runs at the lowest priority, so interrupts cannot already be masked,
-    so there is no need to save and restore the current mask value. */
+     * handler runs at the lowest priority, so interrupts cannot already be masked,
+     * so there is no need to save and restore the current mask value. */
     __disable_irq();
     portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
-    __asm(  "DSB        \n"
-            "ISB        \n" );
+    __asm( "DSB        \n"
+           "ISB        \n" );
     __enable_irq();
 
     /* Increment the RTOS tick. */
@@ -355,14 +361,14 @@ void FreeRTOS_Tick_Handler( void )
 
 void vPortTaskUsesFPU( void )
 {
-uint32_t ulInitialFPSCR = 0;
+    uint32_t ulInitialFPSCR = 0;
 
     /* A task is registering the fact that it needs an FPU context.  Set the
-    FPU flag (which is saved as part of the task context). */
+     * FPU flag (which is saved as part of the task context). */
     ulPortTaskHasFPUContext = pdTRUE;
 
     /* Initialise the floating point status register. */
-    __asm( "FMXR    FPSCR, %0" :: "r" (ulInitialFPSCR) );
+    __asm( "FMXR    FPSCR, %0" ::"r" ( ulInitialFPSCR ) );
 }
 /*-----------------------------------------------------------*/
 
@@ -377,9 +383,10 @@ void vPortClearInterruptMask( uint32_t ulNewMaskValue )
 
 uint32_t ulPortSetInterruptMask( void )
 {
-uint32_t ulReturn;
+    uint32_t ulReturn;
 
     __disable_irq();
+
     if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
     {
         /* Interrupts were already masked. */
@@ -389,49 +396,50 @@ uint32_t ulReturn;
     {
         ulReturn = pdFALSE;
         portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
-        __asm(  "DSB        \n"
-                "ISB        \n" );
+        __asm( "DSB        \n"
+               "ISB        \n" );
     }
+
     __enable_irq();
 
     return ulReturn;
 }
 /*-----------------------------------------------------------*/
 
-#if( configASSERT_DEFINED == 1 )
+#if ( configASSERT_DEFINED == 1 )
 
     void vPortValidateInterruptPriority( void )
     {
         /* The following assertion will fail if a service routine (ISR) for
-        an interrupt that has been assigned a priority above
-        configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
-        function.  ISR safe FreeRTOS API functions must *only* be called
-        from interrupts that have been assigned a priority at or below
-        configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
-        Numerically low interrupt priority numbers represent logically high
-        interrupt priorities, therefore the priority of the interrupt must
-        be set to a value equal to or numerically *higher* than
-        configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
-        FreeRTOS maintains separate thread and ISR API functions to ensure
-        interrupt entry is as fast and simple as possible.
-
-        The following links provide detailed information:
-        https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
-        https://www.FreeRTOS.org/FAQHelp.html */
+         * an interrupt that has been assigned a priority above
+         * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+         * function.  ISR safe FreeRTOS API functions must *only* be called
+         * from interrupts that have been assigned a priority at or below
+         * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+         *
+         * Numerically low interrupt priority numbers represent logically high
+         * interrupt priorities, therefore the priority of the interrupt must
+         * be set to a value equal to or numerically *higher* than
+         * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+         *
+         * FreeRTOS maintains separate thread and ISR API functions to ensure
+         * interrupt entry is as fast and simple as possible.
+         *
+         * The following links provide detailed information:
+         * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+         * https://www.FreeRTOS.org/FAQHelp.html */
         configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
 
         /* Priority grouping:  The interrupt controller (GIC) allows the bits
-        that define each interrupt's priority to be split between bits that
-        define the interrupt's pre-emption priority bits and bits that define
-        the interrupt's sub-priority.  For simplicity all bits must be defined
-        to be pre-emption priority bits.  The following assertion will fail if
-        this is not the case (if some bits represent a sub-priority).
-
-        The priority grouping is configured by the GIC's binary point register
-        (ICCBPR).  Writting 0 to ICCBPR will ensure it is set to its lowest
-        possible value (which may be above 0). */
+         * that define each interrupt's priority to be split between bits that
+         * define the interrupt's pre-emption priority bits and bits that define
+         * the interrupt's sub-priority.  For simplicity all bits must be defined
+         * to be pre-emption priority bits.  The following assertion will fail if
+         * this is not the case (if some bits represent a sub-priority).
+         *
+         * The priority grouping is configured by the GIC's binary point register
+         * (ICCBPR).  Writting 0 to ICCBPR will ensure it is set to its lowest
+         * possible value (which may be above 0). */
         configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
     }
 
diff --git a/portable/IAR/ARM_CA9/portASM.h b/portable/IAR/ARM_CA9/portASM.h
index e6df989da..8c21efed5 100644
--- a/portable/IAR/ARM_CA9/portASM.h
+++ b/portable/IAR/ARM_CA9/portASM.h
@@ -1,111 +1,160 @@
-;/*
-; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
-; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
-; *
-; * SPDX-License-Identifier: MIT
-; *
-; * Permission is hereby granted, free of charge, to any person obtaining a copy of
-; * this software and associated documentation files (the "Software"), to deal in
-; * the Software without restriction, including without limitation the rights to
-; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
-; * the Software, and to permit persons to whom the Software is furnished to do so,
-; * subject to the following conditions:
-; *
-; * The above copyright notice and this permission notice shall be included in all
-; * copies or substantial portions of the Software.
-; *
-; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-; *
-; * https://www.FreeRTOS.org
-; * https://github.com/FreeRTOS
-; *
-; */
+; /*
+   * ; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+   * ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+   * ; *
+   * ; * SPDX-License-Identifier: MIT
+   * ; *
+   * ; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+   * ; * this software and associated documentation files (the "Software"), to deal in
+   * ; * the Software without restriction, including without limitation the rights to
+   * ; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+   * ; * the Software, and to permit persons to whom the Software is furnished to do so,
+   * ; * subject to the following conditions:
+   * ; *
+   * ; * The above copyright notice and this permission notice shall be included in all
+   * ; * copies or substantial portions of the Software.
+   * ; *
+   * ; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+   * ; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+   * ; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+   * ; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+   * ; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+   * ; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+   * ; *
+   * ; * https://www.FreeRTOS.org
+   * ; * https://github.com/FreeRTOS
+   * ; *
+   * ; */
 
-    EXTERN  vTaskSwitchContext
-    EXTERN  ulCriticalNesting
-    EXTERN  pxCurrentTCB
-    EXTERN  ulPortTaskHasFPUContext
-    EXTERN  ulAsmAPIPriorityMask
+EXTERN vTaskSwitchContext
+EXTERN ulCriticalNesting
+EXTERN pxCurrentTCB
+EXTERN ulPortTaskHasFPUContext
+EXTERN ulAsmAPIPriorityMask
 
 portSAVE_CONTEXT macro
 
-    ; Save the LR and SPSR onto the system mode stack before switching to
-    ; system mode to save the remaining system mode registers
-    SRSDB   sp!, #SYS_MODE
-    CPS     #SYS_MODE
-    PUSH    {R0-R12, R14}
+;
+Save the LR and SPSR onto the system mode stack before switching to
+;
+system mode to save the remaining system mode registers
+SRSDB sp !, # SYS_MODE
+      CPS     # SYS_MODE
+      PUSH    {
+    R0 - R12, R14
+}
 
-    ; Push the critical nesting count
-    LDR     R2, =ulCriticalNesting
-    LDR     R1, [R2]
-    PUSH    {R1}
+;
+Push the critical nesting count
+LDR R2, = ulCriticalNesting
+          LDR R1, [ R2 ]
+PUSH    {
+    R1
+}
 
-    ; Does the task have a floating point context that needs saving?  If
-    ; ulPortTaskHasFPUContext is 0 then no.
-    LDR     R2, =ulPortTaskHasFPUContext
-    LDR     R3, [R2]
-    CMP     R3, #0
+;
+Does the task have a floating point context that needs saving ? If
+;
+ulPortTaskHasFPUContext is 0 then no.
+   LDR R2, = ulPortTaskHasFPUContext
+             LDR R3, [ R2 ]
+CMP R3, # 0
 
-    ; Save the floating point context, if any
-    FMRXNE  R1,  FPSCR
-    VPUSHNE {D0-D15}
-    VPUSHNE {D16-D31}
-    PUSHNE  {R1}
+;
+Save the floating point context,
 
-    ; Save ulPortTaskHasFPUContext itself
-    PUSH    {R3}
+if any
+FMRXNE R1, FPSCR
+                        VPUSHNE {
+    D0 - D15
+}
 
-    ; Save the stack pointer in the TCB
-    LDR     R0, =pxCurrentTCB
-    LDR     R1, [R0]
-    STR     SP, [R1]
+VPUSHNE {
+    D16 - D31
+}
+PUSHNE  {
+    R1
+}
 
-    endm
+;
+Save ulPortTaskHasFPUContext itself
+    PUSH    {
+    R3
+}
+
+;
+Save the stack pointer in the TCB
+LDR R0, = pxCurrentTCB
+          LDR R1, [ R0 ]
+STR SP, [ R1 ]
+
+endm
 
 ; /**********************************************************************/
 
 portRESTORE_CONTEXT macro
 
-    ; Set the SP to point to the stack of the task being restored.
-    LDR     R0, =pxCurrentTCB
-    LDR     R1, [R0]
-    LDR     SP, [R1]
+;
+Set the SP to point to the stack of the task being restored.
+   LDR R0, = pxCurrentTCB
+             LDR R1, [ R0 ]
+LDR SP, [ R1 ]
 
-    ; Is there a floating point context to restore?  If the restored
-    ; ulPortTaskHasFPUContext is zero then no.
-    LDR     R0, =ulPortTaskHasFPUContext
-    POP     {R1}
-    STR     R1, [R0]
-    CMP     R1, #0
+;
+Is there a floating point context to restore ? If the restored
+;
+ulPortTaskHasFPUContext is zero then no.
+   LDR R0, = ulPortTaskHasFPUContext
+             POP     {
+    R1
+}
+STR R1, [ R0 ]
+CMP R1, # 0
 
-    ; Restore the floating point context, if any
-    POPNE   {R0}
-    VPOPNE  {D16-D31}
-    VPOPNE  {D0-D15}
-    VMSRNE  FPSCR, R0
+;
+Restore the floating point context,
 
-    ; Restore the critical section nesting depth
-    LDR     R0, =ulCriticalNesting
-    POP     {R1}
-    STR     R1, [R0]
+if any
+                           POPNE   {
+    R0
+}
 
-    ; Ensure the priority mask is correct for the critical nesting depth
-    LDR     R2, =portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS
-    CMP     R1, #0
-    MOVEQ   R4, #255
-    LDRNE   R4, =( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT )
-    STR     R4, [r2]
+VPOPNE  {
+    D16 - D31
+}
+VPOPNE  {
+    D0 - D15
+}
+VMSRNE FPSCR, R0
 
-    ; Restore all system mode registers other than the SP (which is already
-    ; being used)
-    POP     {R0-R12, R14}
+;
+Restore the critical section nesting depth
+LDR R0, = ulCriticalNesting
+          POP     {
+    R1
+}
+STR R1, [ R0 ]
 
-    ; Return to the task code, loading CPSR on the way.
-    RFEIA   sp!
+;
+Ensure the priority mask is correct
 
-    endm
+for the critical nesting depth
+LDR R2, = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS
+          CMP R1, # 0
+MOVEQ R4, # 255
+LDRNE R4, = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT )
+            STR R4, [ r2 ]
+
+;
+Restore all system mode registers other than the SP( which is already
+                                                     ;
+                                                     being used )
+POP
+{
+    R0 - R12, R14
+}
+
+Return to the task code, loading CPSR on the way.
+   RFEIA sp !
+
+endm
diff --git a/portable/IAR/ARM_CA9/portmacro.h b/portable/IAR/ARM_CA9/portmacro.h
index bce3013b5..4782a5a66 100644
--- a/portable/IAR/ARM_CA9/portmacro.h
+++ b/portable/IAR/ARM_CA9/portmacro.h
@@ -40,127 +40,127 @@
 
     #include <intrinsics.h>
 
-    /*-----------------------------------------------------------
-     * Port specific definitions.
-     *
-     * The settings in this file configure FreeRTOS correctly for the given hardware
-     * and compiler.
-     *
-     * These settings should not be altered.
-     *-----------------------------------------------------------
-     */
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
 
-    /* Type definitions. */
-    #define portCHAR        char
-    #define portFLOAT       float
-    #define portDOUBLE      double
-    #define portLONG        long
-    #define portSHORT       short
-    #define portSTACK_TYPE  uint32_t
-    #define portBASE_TYPE   long
+/* Type definitions. */
+    #define portCHAR          char
+    #define portFLOAT         float
+    #define portDOUBLE        double
+    #define portLONG          long
+    #define portSHORT         short
+    #define portSTACK_TYPE    uint32_t
+    #define portBASE_TYPE     long
 
-    typedef portSTACK_TYPE StackType_t;
-    typedef long BaseType_t;
-    typedef unsigned long UBaseType_t;
+    typedef portSTACK_TYPE   StackType_t;
+    typedef long             BaseType_t;
+    typedef unsigned long    UBaseType_t;
 
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+    typedef uint32_t         TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-    not need to be guarded with a critical section. */
-    #define portTICK_TYPE_IS_ATOMIC 1
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+    #define portTICK_TYPE_IS_ATOMIC    1
 
-    /*-----------------------------------------------------------*/
+/*-----------------------------------------------------------*/
 
-    /* Hardware specifics. */
-    #define portSTACK_GROWTH            ( -1 )
-    #define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-    #define portBYTE_ALIGNMENT          8
+/* Hardware specifics. */
+    #define portSTACK_GROWTH      ( -1 )
+    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+    #define portBYTE_ALIGNMENT    8
 
-    /*-----------------------------------------------------------*/
+/*-----------------------------------------------------------*/
 
-    /* Task utilities. */
+/* Task utilities. */
 
-    /* Called at the end of an ISR that can cause a context switch. */
-    #define portEND_SWITCHING_ISR( xSwitchRequired )\
-    {                                               \
-    extern uint32_t ulPortYieldRequired;            \
-                                                    \
-        if( xSwitchRequired != pdFALSE )            \
-        {                                           \
-            ulPortYieldRequired = pdTRUE;           \
-        }                                           \
+/* Called at the end of an ISR that can cause a context switch. */
+    #define portEND_SWITCHING_ISR( xSwitchRequired ) \
+    {                                                \
+        extern uint32_t ulPortYieldRequired;         \
+                                                     \
+        if( xSwitchRequired != pdFALSE )             \
+        {                                            \
+            ulPortYieldRequired = pdTRUE;            \
+        }                                            \
     }
 
-    #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
-    #define portYIELD() __asm( "SWI 0" );
+    #define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
+    #define portYIELD()                __asm( "SWI 0" );
 
 
-    /*-----------------------------------------------------------
-     * Critical section control
-     *----------------------------------------------------------*/
+/*-----------------------------------------------------------
+* Critical section control
+*----------------------------------------------------------*/
 
     extern void vPortEnterCritical( void );
     extern void vPortExitCritical( void );
     extern uint32_t ulPortSetInterruptMask( void );
     extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
 
-    /* These macros do not globally disable/enable interrupts.  They do mask off
-    interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
-    #define portENTER_CRITICAL()        vPortEnterCritical();
-    #define portEXIT_CRITICAL()         vPortExitCritical();
-    #define portDISABLE_INTERRUPTS()    ulPortSetInterruptMask()
-    #define portENABLE_INTERRUPTS()     vPortClearInterruptMask( 0 )
-    #define portSET_INTERRUPT_MASK_FROM_ISR()       ulPortSetInterruptMask()
-    #define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)    vPortClearInterruptMask(x)
+/* These macros do not globally disable/enable interrupts.  They do mask off
+ * interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
+    #define portENTER_CRITICAL()                      vPortEnterCritical();
+    #define portEXIT_CRITICAL()                       vPortExitCritical();
+    #define portDISABLE_INTERRUPTS()                  ulPortSetInterruptMask()
+    #define portENABLE_INTERRUPTS()                   vPortClearInterruptMask( 0 )
+    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulPortSetInterruptMask()
+    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vPortClearInterruptMask( x )
 
-    /*-----------------------------------------------------------*/
+/*-----------------------------------------------------------*/
 
-    /* Task function macros as described on the FreeRTOS.org WEB site.  These are
-    not required for this port but included in case common demo code that uses these
-    macros is used. */
-    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )  void vFunction( void *pvParameters )
-    #define portTASK_FUNCTION( vFunction, pvParameters )    void vFunction( void *pvParameters )
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+ * not required for this port but included in case common demo code that uses these
+ * macros is used. */
+    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
-    /* Prototype of the FreeRTOS tick handler.  This must be installed as the
-    handler for whichever peripheral is used to generate the RTOS tick. */
+/* Prototype of the FreeRTOS tick handler.  This must be installed as the
+ * handler for whichever peripheral is used to generate the RTOS tick. */
     void FreeRTOS_Tick_Handler( void );
 
-    /* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
-    before any floating point instructions are executed. */
+/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
+ * before any floating point instructions are executed. */
     void vPortTaskUsesFPU( void );
-    #define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
+    #define portTASK_USES_FLOATING_POINT()    vPortTaskUsesFPU()
 
-    #define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
-    #define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
+    #define portLOWEST_INTERRUPT_PRIORITY           ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
+    #define portLOWEST_USABLE_INTERRUPT_PRIORITY    ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
 
-    /* Architecture specific optimisations. */
+/* Architecture specific optimisations. */
     #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
     #endif
 
     #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
 
-        /* Store/clear the ready priorities in a bit map. */
-        #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-        #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+/* Store/clear the ready priorities in a bit map. */
+        #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+        #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 
-        /*-----------------------------------------------------------*/
+/*-----------------------------------------------------------*/
 
-        #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __CLZ( uxReadyPriorities ) )
+        #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31 - __CLZ( uxReadyPriorities ) )
 
     #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 
     #ifdef configASSERT
         void vPortValidateInterruptPriority( void );
-        #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()  vPortValidateInterruptPriority()
+        #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
     #endif /* configASSERT */
 
-    #define portNOP() __asm volatile( "NOP" )
+    #define portNOP()                                         __asm volatile ( "NOP" )
 
-    /* Suppress warnings that are generated by the IAR tools, but cannot be
-    fixed in the source code because to do so would cause other compilers to
-    generate warnings. */
+/* Suppress warnings that are generated by the IAR tools, but cannot be
+ * fixed in the source code because to do so would cause other compilers to
+ * generate warnings. */
     #pragma diag_suppress=Pe191
     #pragma diag_suppress=Pa082
 
@@ -168,40 +168,40 @@
 
 
 /* The number of bits to shift for an interrupt priority is dependent on the
-number of bits implemented by the interrupt controller. */
+ * number of bits implemented by the interrupt controller. */
 #if configUNIQUE_INTERRUPT_PRIORITIES == 16
-    #define portPRIORITY_SHIFT 4
-    #define portMAX_BINARY_POINT_VALUE  3
+    #define portPRIORITY_SHIFT            4
+    #define portMAX_BINARY_POINT_VALUE    3
 #elif configUNIQUE_INTERRUPT_PRIORITIES == 32
-    #define portPRIORITY_SHIFT 3
-    #define portMAX_BINARY_POINT_VALUE  2
+    #define portPRIORITY_SHIFT            3
+    #define portMAX_BINARY_POINT_VALUE    2
 #elif configUNIQUE_INTERRUPT_PRIORITIES == 64
-    #define portPRIORITY_SHIFT 2
-    #define portMAX_BINARY_POINT_VALUE  1
+    #define portPRIORITY_SHIFT            2
+    #define portMAX_BINARY_POINT_VALUE    1
 #elif configUNIQUE_INTERRUPT_PRIORITIES == 128
-    #define portPRIORITY_SHIFT 1
-    #define portMAX_BINARY_POINT_VALUE  0
+    #define portPRIORITY_SHIFT            1
+    #define portMAX_BINARY_POINT_VALUE    0
 #elif configUNIQUE_INTERRUPT_PRIORITIES == 256
-    #define portPRIORITY_SHIFT 0
-    #define portMAX_BINARY_POINT_VALUE  0
-#else
+    #define portPRIORITY_SHIFT            0
+    #define portMAX_BINARY_POINT_VALUE    0
+#else /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */
     #error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting.  configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware
-#endif
+#endif /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */
 
 /* Interrupt controller access addresses. */
-#define portICCPMR_PRIORITY_MASK_OFFSET                         ( 0x04 )
-#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET                 ( 0x0C )
-#define portICCEOIR_END_OF_INTERRUPT_OFFSET                     ( 0x10 )
-#define portICCBPR_BINARY_POINT_OFFSET                          ( 0x08 )
-#define portICCRPR_RUNNING_PRIORITY_OFFSET                      ( 0x14 )
+#define portICCPMR_PRIORITY_MASK_OFFSET                      ( 0x04 )
+#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET              ( 0x0C )
+#define portICCEOIR_END_OF_INTERRUPT_OFFSET                  ( 0x10 )
+#define portICCBPR_BINARY_POINT_OFFSET                       ( 0x08 )
+#define portICCRPR_RUNNING_PRIORITY_OFFSET                   ( 0x14 )
 
-#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS      ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )
-#define portICCPMR_PRIORITY_MASK_REGISTER                   ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )
-#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS   ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )
-#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS       ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )
-#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS           ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )
-#define portICCBPR_BINARY_POINT_REGISTER                    ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
-#define portICCRPR_RUNNING_PRIORITY_REGISTER                ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )
+#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS       ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )
+#define portICCPMR_PRIORITY_MASK_REGISTER                    ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )
+#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS    ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )
+#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS        ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )
+#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS            ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )
+#define portICCBPR_BINARY_POINT_REGISTER                     ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
+#define portICCRPR_RUNNING_PRIORITY_REGISTER                 ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/IAR/ARM_CM23/non_secure/port.c b/portable/IAR/ARM_CM23/non_secure/port.c
index 80410e82e..c940c304b 100644
--- a/portable/IAR/ARM_CM23/non_secure/port.c
+++ b/portable/IAR/ARM_CM23/non_secure/port.c
@@ -110,8 +110,8 @@
 /**
  * @brief Constants used during system call enter and exit.
  */
-#define portPSR_STACK_PADDING_MASK                ( 1UL << 9UL )
-#define portEXC_RETURN_STACK_FRAME_TYPE_MASK      ( 1UL << 4UL )
+#define portPSR_STACK_PADDING_MASK              ( 1UL << 9UL )
+#define portEXC_RETURN_STACK_FRAME_TYPE_MASK    ( 1UL << 4UL )
 /*-----------------------------------------------------------*/
 
 /**
@@ -133,81 +133,81 @@
 /**
  * @brief Offsets in the stack to the parameters when inside the SVC handler.
  */
-#define portOFFSET_TO_LR                    ( 5 )
-#define portOFFSET_TO_PC                    ( 6 )
-#define portOFFSET_TO_PSR                   ( 7 )
+#define portOFFSET_TO_LR     ( 5 )
+#define portOFFSET_TO_PC     ( 6 )
+#define portOFFSET_TO_PSR    ( 7 )
 /*-----------------------------------------------------------*/
 
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                      ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                      ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                       ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                      ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                      ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                     ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                     ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK  ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK               ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK               ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK               ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK               ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK               ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK               ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK               ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK               ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0              ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1              ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2              ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3              ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4              ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5              ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6              ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7              ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE            ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT      ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                      ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE             ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -216,11 +216,11 @@
 
 /* Extract last address of the MPU region as encoded in the
  * RLAR (Region Limit Address Register) value. */
-#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar )  \
+#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar ) \
     ( ( ( rlar ) & portMPU_RLAR_ADDRESS_MASK ) | ~portMPU_RLAR_ADDRESS_MASK )
 
 /* Does addr lies within [start, end] address range? */
-#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end )    \
+#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \
     ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) )
 
 /* Is the access request satisfied by the available permissions? */
@@ -422,54 +422,57 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the system call stack so that upon returning from
-     * SVC, the system call stack is used.
-     *
-     * It is used for the system calls with up to 4 parameters.
-     *
-     * @param pulTaskStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the system call stack so that upon returning from
+ * SVC, the system call stack is used.
+ *
+ * It is used for the system calls with up to 4 parameters.
+ *
+ * @param pulTaskStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallEnter( uint32_t * pulTaskStack,
+                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the system call stack so that upon returning from
-     * SVC, the system call stack is used.
-     *
-     * It is used for the system calls with 5 parameters.
-     *
-     * @param pulTaskStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the system call stack so that upon returning from
+ * SVC, the system call stack is used.
+ *
+ * It is used for the system calls with 5 parameters.
+ *
+ * @param pulTaskStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallEnter_1( uint32_t * pulTaskStack,
+                             uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the task stack so that upon returning from
-     * SVC, the task stack is used again.
-     *
-     * @param pulSystemCallStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the task stack so that upon returning from
+ * SVC, the task stack is used again.
+ *
+ * @param pulSystemCallStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallExit( uint32_t * pulSystemCallStack,
+                          uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Checks whether or not the calling task is privileged.
-     *
-     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
-     */
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
     BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
 
 #endif /* configENABLE_MPU == 1 */
@@ -1086,18 +1089,18 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             vRestoreContextOfFirstTask();
             break;
 
-        #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
-            case portSVC_RAISE_PRIVILEGE:
+            #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+                case portSVC_RAISE_PRIVILEGE:
 
-                /* Only raise the privilege, if the svc was raised from any of
-                 * the system calls. */
-                if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
-                    ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
-                {
-                    vRaisePrivilege();
-                }
-                break;
-        #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+                    /* Only raise the privilege, if the svc was raised from any of
+                     * the system calls. */
+                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+                    {
+                        vRaisePrivilege();
+                    }
+                    break;
+            #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
         default:
             /* Incorrect SVC call. */
@@ -1108,513 +1111,526 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulSystemCallStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallEnter( uint32_t * pulTaskStack,
+                           uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulSystemCallStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        /* This is not NULL only for the duration of the system call. */
-        configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+        #if defined( __ARMCC_VERSION )
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+
+            /* This is not NULL only for the duration of the system call. */
+            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the system call stack for the stack frame. */
+            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulSystemCallStack[ i ] = pulTaskStack[ i ];
+            }
+
+            /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
+             * restore it when we exit from the system call. */
+            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* Use the pulSystemCallStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+
+            /* Remember the location where we should copy the stack frame when we exit from
+             * the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+
+            /* Record if the hardware used padding to force the stack pointer
+             * to be double word aligned. */
+            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
+            {
+                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
             }
+
+            /* We ensure in pxPortInitialiseStack that the system call stack is
+             * double word aligned and therefore, there is no need of padding.
+             * Clear the bit[9] of stacked xPSR. */
+            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
+
+            /* Raise the privilege for the duration of the system call. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " bics r0, r1         \n" /* Clear nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the system call stack for the stack frame. */
-        pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulSystemCallStack[ i ] = pulTaskStack[ i ];
-        }
-
-        /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
-         * restore it when we exit from the system call. */
-        pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-        __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* Use the pulSystemCallStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-
-        /* Remember the location where we should copy the stack frame when we exit from
-         * the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-        /* Record if the hardware used padding to force the stack pointer
-         * to be double word aligned. */
-        if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-        {
-            pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-        }
-        else
-        {
-            pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-        }
-
-        /* We ensure in pxPortInitialiseStack that the system call stack is
-         * double word aligned and therefore, there is no need of padding.
-         * Clear the bit[9] of stacked xPSR. */
-        pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-        /* Raise the privilege for the duration of the system call. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " bics r0, r1         \n" /* Clear nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulSystemCallStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallEnter_1( uint32_t * pulTaskStack,
+                             uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulSystemCallStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        /* This is not NULL only for the duration of the system call. */
-        configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+        #if defined( __ARMCC_VERSION )
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+
+            /* This is not NULL only for the duration of the system call. */
+            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the system call stack for the stack frame and
+             * the parameter passed on the stack. We only need to copy one
+             * parameter but we still reserve 2 spaces to keep the stack
+             * double word aligned. */
+            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulSystemCallStack[ i ] = pulTaskStack[ i ];
+            }
+
+            /* Copy the parameter which is passed the stack. */
+            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
+            {
+                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
+
+                /* Record if the hardware used padding to force the stack pointer
+                 * to be double word aligned. */
+                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
+
+                /* Record if the hardware used padding to force the stack pointer
+                 * to be double word aligned. */
+                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
             }
+
+            /* Store the value of the LR and PSPLIM registers before the SVC was raised.
+             * We need to restore it when we exit from the system call. */
+            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* Use the pulSystemCallStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+
+            /* Remember the location where we should copy the stack frame when we exit from
+             * the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+
+            /* We ensure in pxPortInitialiseStack that the system call stack is
+             * double word aligned and therefore, there is no need of padding.
+             * Clear the bit[9] of stacked xPSR. */
+            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
+
+            /* Raise the privilege for the duration of the system call. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " bics r0, r1         \n" /* Clear nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the system call stack for the stack frame and
-         * the parameter passed on the stack. We only need to copy one
-         * parameter but we still reserve 2 spaces to keep the stack
-         * double word aligned. */
-        pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulSystemCallStack[ i ] = pulTaskStack[ i ];
-        }
-
-        /* Copy the parameter which is passed the stack. */
-        if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-        {
-            pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
-            /* Record if the hardware used padding to force the stack pointer
-             * to be double word aligned. */
-            pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-        }
-        else
-        {
-            pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
-            /* Record if the hardware used padding to force the stack pointer
-             * to be double word aligned. */
-            pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-        }
-
-        /* Store the value of the LR and PSPLIM registers before the SVC was raised.
-         * We need to restore it when we exit from the system call. */
-        pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-        __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* Use the pulSystemCallStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-
-        /* Remember the location where we should copy the stack frame when we exit from
-         * the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-        /* We ensure in pxPortInitialiseStack that the system call stack is
-         * double word aligned and therefore, there is no need of padding.
-         * Clear the bit[9] of stacked xPSR. */
-        pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-        /* Raise the privilege for the duration of the system call. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " bics r0, r1         \n" /* Clear nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulTaskStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallExit( uint32_t * pulSystemCallStack,
+                          uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulTaskStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+        #if defined( __ARMCC_VERSION )
+
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the task stack for the stack frame. */
+            pulTaskStack = pulTaskStack - ulStackFrameSize;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulTaskStack[ i ] = pulSystemCallStack[ i ];
+            }
+
+            /* Use the pulTaskStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
+
+            /* Restore the LR and PSPLIM to what they were at the time of
+             * system call entry. */
+            pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* If the hardware used padding to force the stack pointer
+             * to be double word aligned, set the stacked xPSR bit[9],
+             * otherwise clear it. */
+            if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG )
+            {
+                pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
             }
+
+            /* This is not NULL only for the duration of the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
+
+            /* Drop the privilege before returning to the thread mode. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " orrs r0, r1         \n" /* Set nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the task stack for the stack frame. */
-        pulTaskStack = pulTaskStack - ulStackFrameSize;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulTaskStack[ i ] = pulSystemCallStack[ i ];
-        }
-
-        /* Use the pulTaskStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
-
-        /* Restore the LR and PSPLIM to what they were at the time of
-         * system call entry. */
-        pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* If the hardware used padding to force the stack pointer
-         * to be double word aligned, set the stacked xPSR bit[9],
-         * otherwise clear it. */
-        if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG )
-        {
-            pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK;
-        }
-        else
-        {
-            pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-        }
-
-        /* This is not NULL only for the duration of the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
-
-        /* Drop the privilege before returning to the thread mode. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " orrs r0, r1         \n" /* Set nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */
-{
-    BaseType_t xTaskIsPrivileged = pdFALSE;
-    const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
-
-    if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+    BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */
     {
-        xTaskIsPrivileged = pdTRUE;
-    }
+        BaseType_t xTaskIsPrivileged = pdFALSE;
+        const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
 
-    return xTaskIsPrivileged;
-}
+        if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+        {
+            xTaskIsPrivileged = pdTRUE;
+        }
+
+        return xTaskIsPrivileged;
+    }
 
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
-#if( configENABLE_MPU == 1 )
+#if ( configENABLE_MPU == 1 )
 
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     StackType_t * pxEndOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters,
-                                     BaseType_t xRunPrivileged,
-                                     xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
-{
-    uint32_t ulIndex = 0;
-
-    xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
-    ulIndex++;
-
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
-    ulIndex++;
-
-    #if ( configENABLE_TRUSTZONE == 1 )
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters,
+                                         BaseType_t xRunPrivileged,
+                                         xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
     {
-        xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT;  /* xSecureContext. */
+        uint32_t ulIndex = 0;
+
+        xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
         ulIndex++;
-    }
-    #endif /* configENABLE_TRUSTZONE */
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
-    ulIndex++;
-    if( xRunPrivileged == pdTRUE )
-    {
-        xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */
         ulIndex++;
-    }
-    else
-    {
-        xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */
         ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
+        ulIndex++;
+
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters;            /* r0. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x01010101;                           /* r1. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x02020202;                           /* r2. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x03030303;                           /* r3. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x12121212;                           /* r12. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode;                  /* PC. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR;                     /* xPSR. */
+        ulIndex++;
+
+        #if ( configENABLE_TRUSTZONE == 1 )
+        {
+            xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT; /* xSecureContext. */
+            ulIndex++;
+        }
+        #endif /* configENABLE_TRUSTZONE */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
+        ulIndex++;
+
+        if( xRunPrivileged == pdTRUE )
+        {
+            xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
+            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+            ulIndex++;
+        }
+        else
+        {
+            xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
+            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+            ulIndex++;
+        }
+
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
+        ulIndex++;
+
+        #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+        {
+            /* Ensure that the system call stack is double word aligned. */
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] );
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) &
+                                                                                     ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
+
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] );
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) +
+                                                                                            ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) &
+                                                                                          ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
+
+            /* This is not NULL only for the duration of a system call. */
+            xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL;
+        }
+        #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
+
+        return &( xMPUSettings->ulContext[ ulIndex ] );
     }
-    xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
-    ulIndex++;
-
-    #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
-    {
-        /* Ensure that the system call stack is double word aligned. */
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] );
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) &
-                                                                                 ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
-
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] );
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) +
-                                                                                        ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) &
-                                                                                      ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
-
-        /* This is not NULL only for the duration of a system call. */
-        xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL;
-    }
-    #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
-
-    return &( xMPUSettings->ulContext[ ulIndex ] );
-}
 
 #else /* configENABLE_MPU */
 
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     StackType_t * pxEndOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters ) /* PRIVILEGED_FUNCTION */
-{
-    /* Simulate the stack frame as it would be created by a context switch
-     * interrupt. */
-    #if ( portPRELOAD_REGISTERS == 0 )
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters ) /* PRIVILEGED_FUNCTION */
     {
-        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-        pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
-        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-        pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
-        *pxTopOfStack = portINITIAL_EXC_RETURN;
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
-
-        #if ( configENABLE_TRUSTZONE == 1 )
+        /* Simulate the stack frame as it would be created by a context switch
+         * interrupt. */
+        #if ( portPRELOAD_REGISTERS == 0 )
         {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
-        }
-        #endif /* configENABLE_TRUSTZONE */
-    }
-    #else /* portPRELOAD_REGISTERS */
-    {
-        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
-        pxTopOfStack--;
-        *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
+            pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
+            *pxTopOfStack = portINITIAL_EXC_RETURN;
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+            #if ( configENABLE_TRUSTZONE == 1 )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+            }
+            #endif /* configENABLE_TRUSTZONE */
+        }
+        #else /* portPRELOAD_REGISTERS */
         {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
-        }
-        #endif /* configENABLE_TRUSTZONE */
-    }
-    #endif /* portPRELOAD_REGISTERS */
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
+            pxTopOfStack--;
+            *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack;            /* Slot used to hold this task's PSPLIM value. */
 
-    return pxTopOfStack;
-}
+            #if ( configENABLE_TRUSTZONE == 1 )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+            }
+            #endif /* configENABLE_TRUSTZONE */
+        }
+        #endif /* portPRELOAD_REGISTERS */
+
+        return pxTopOfStack;
+    }
 
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM23/non_secure/portmacro.h b/portable/IAR/ARM_CM23/non_secure/portmacro.h
index 76ba7172e..e426f5b9a 100644
--- a/portable/IAR/ARM_CM23/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM23/non_secure/portmacro.h
@@ -48,9 +48,9 @@
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME                       "Cortex-M23"
-#define portHAS_ARMV8M_MAIN_EXTENSION       0
-#define portDONT_DISCARD                    __root
+#define portARCH_NAME                    "Cortex-M23"
+#define portHAS_ARMV8M_MAIN_EXTENSION    0
+#define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
 /* ARMv8-M common port configurations. */
diff --git a/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h
index e5ffdb48b..62e462a27 100644
--- a/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h
@@ -81,8 +81,8 @@ typedef unsigned long    UBaseType_t;
     typedef uint32_t     TickType_t;
     #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-     * not need to be guarded with a critical section. */
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
     #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -117,7 +117,7 @@ extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGE
 extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
 
 #if ( configENABLE_TRUSTZONE == 1 )
-    extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize );     /* __attribute__ (( naked )) */
+    extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
     extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
 #endif /* configENABLE_TRUSTZONE */
 
@@ -188,13 +188,13 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Settings to define an MPU region.
-     */
+/**
+ * @brief Settings to define an MPU region.
+ */
     typedef struct MPURegionSettings
     {
-        uint32_t ulRBAR;     /**< RBAR for the region. */
-        uint32_t ulRLAR;     /**< RLAR for the region. */
+        uint32_t ulRBAR; /**< RBAR for the region. */
+        uint32_t ulRLAR; /**< RLAR for the region. */
     } MPURegionSettings_t;
 
     #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
@@ -203,9 +203,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-        /**
-         * @brief System call stack.
-         */
+/**
+ * @brief System call stack.
+ */
         typedef struct SYSTEM_CALL_STACK_INFO
         {
             uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ];
@@ -218,74 +218,74 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
-    /**
-     * @brief MPU settings as stored in the TCB.
-     */
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
     #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
 
-        #if( configENABLE_TRUSTZONE == 1 )
+        #if ( configENABLE_TRUSTZONE == 1 )
 
-            /*
-             * +-----------+---------------+----------+-----------------+------------------------------+-----+
-             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
-             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
-             * +-----------+---------------+----------+-----------------+------------------------------+-----+
-             *
-             * <-----------><--------------><---------><----------------><-----------------------------><---->
-             *      16             16            8               8                     5                   1
-             */
-            #define MAX_CONTEXT_SIZE 54
+/*
+ * +-----------+---------------+----------+-----------------+------------------------------+-----+
+ * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+ * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+ * +-----------+---------------+----------+-----------------+------------------------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><-----------------------------><---->
+ *      16             16            8               8                     5                   1
+ */
+            #define MAX_CONTEXT_SIZE    54
 
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-            /*
-             * +-----------+---------------+----------+-----------------+----------------------+-----+
-             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
-             * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
-             * +-----------+---------------+----------+-----------------+----------------------+-----+
-             *
-             * <-----------><--------------><---------><----------------><---------------------><---->
-             *      16             16            8               8                  4              1
-             */
-            #define MAX_CONTEXT_SIZE 53
+/*
+ * +-----------+---------------+----------+-----------------+----------------------+-----+
+ * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+ * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
+ * +-----------+---------------+----------+-----------------+----------------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><---------------------><---->
+ *      16             16            8               8                  4              1
+ */
+            #define MAX_CONTEXT_SIZE    53
 
         #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
 
     #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-        #if( configENABLE_TRUSTZONE == 1 )
+        #if ( configENABLE_TRUSTZONE == 1 )
 
-            /*
-             * +----------+-----------------+------------------------------+-----+
-             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
-             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
-             * +----------+-----------------+------------------------------+-----+
-             *
-             * <---------><----------------><------------------------------><---->
-             *     8               8                      5                   1
-             */
-            #define MAX_CONTEXT_SIZE 22
+/*
+ * +----------+-----------------+------------------------------+-----+
+ * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+ * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+ * +----------+-----------------+------------------------------+-----+
+ *
+ * <---------><----------------><------------------------------><---->
+ *     8               8                      5                   1
+ */
+            #define MAX_CONTEXT_SIZE    22
 
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-            /*
-             * +----------+-----------------+----------------------+-----+
-             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
-             * |          | PC, xPSR        | EXC_RETURN           |     |
-             * +----------+-----------------+----------------------+-----+
-             *
-             * <---------><----------------><----------------------><---->
-             *     8               8                  4              1
-             */
-            #define MAX_CONTEXT_SIZE 21
+/*
+ * +----------+-----------------+----------------------+-----+
+ * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+ * |          | PC, xPSR        | EXC_RETURN           |     |
+ * +----------+-----------------+----------------------+-----+
+ *
+ * <---------><----------------><----------------------><---->
+ *     8               8                  4              1
+ */
+            #define MAX_CONTEXT_SIZE    21
 
         #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
 
     #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-    /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
-    #define portSTACK_FRAME_HAS_PADDING_FLAG     ( 1UL << 0UL )
-    #define portTASK_IS_PRIVILEGED_FLAG          ( 1UL << 1UL )
+/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
+    #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
+    #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
     typedef struct MPU_SETTINGS
     {
@@ -364,49 +364,49 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-    /**
-     * @brief Allocate a secure context for the task.
-     *
-     * Tasks are not created with a secure context. Any task that is going to call
-     * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
-     * secure context before it calls any secure function.
-     *
-     * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
-     */
+/**
+ * @brief Allocate a secure context for the task.
+ *
+ * Tasks are not created with a secure context. Any task that is going to call
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+ * secure context before it calls any secure function.
+ *
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+ */
     #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
 
-    /**
-     * @brief Called when a task is deleted to delete the task's secure context,
-     * if it has one.
-     *
-     * @param[in] pxTCB The TCB of the task being deleted.
-     */
+/**
+ * @brief Called when a task is deleted to delete the task's secure context,
+ * if it has one.
+ *
+ * @param[in] pxTCB The TCB of the task being deleted.
+ */
     #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
 #endif /* configENABLE_TRUSTZONE */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Checks whether or not the processor is privileged.
-     *
-     * @return 1 if the processor is already privileged, 0 otherwise.
-     */
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
     #define portIS_PRIVILEGED()      xIsPrivileged()
 
-    /**
-     * @brief Raise an SVC request to raise privilege.
-     *
-     * The SVC handler checks that the SVC was raised from a system call and only
-     * then it raises the privilege. If this is called from any other place,
-     * the privilege is not raised.
-     */
+/**
+ * @brief Raise an SVC request to raise privilege.
+ *
+ * The SVC handler checks that the SVC was raised from a system call and only
+ * then it raises the privilege. If this is called from any other place,
+ * the privilege is not raised.
+ */
     #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
 
-    /**
-     * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
-     * register.
-     */
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
     #define portRESET_PRIVILEGE()    vResetPrivilege()
 #else
     #define portIS_PRIVILEGED()
@@ -419,12 +419,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     extern BaseType_t xPortIsTaskPrivileged( void );
 
-    /**
-     * @brief Checks whether or not the calling task is privileged.
-     *
-     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
-     */
-    #define portIS_TASK_PRIVILEGED()      xPortIsTaskPrivileged()
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
+    #define portIS_TASK_PRIVILEGED()    xPortIsTaskPrivileged()
 
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
@@ -439,9 +439,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * based on whether or not Mainline extension is implemented. */
 #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
     #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
-        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
     #else
-        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    0
     #endif
 #endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
 
@@ -450,9 +450,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  */
 #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
 
-    /**
-     * @brief Count the number of leading zeros in a 32-bit value.
-     */
+/**
+ * @brief Count the number of leading zeros in a 32-bit value.
+ */
     static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
     {
         uint32_t ulReturn;
@@ -462,7 +462,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         return ulReturn;
     }
 
-    /* Check the configuration. */
+/* Check the configuration. */
     #if ( configMAX_PRIORITIES > 32 )
         #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
     #endif
@@ -471,16 +471,16 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection.  Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
     #endif
 
-    /**
-     * @brief Store/clear the ready priorities in a bit map.
-     */
-    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+/**
+ * @brief Store/clear the ready priorities in a bit map.
+ */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )      ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )       ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 
-    /**
-     * @brief Get the priority of the highest-priority task that is ready to execute.
-     */
-    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )   uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+/**
+ * @brief Get the priority of the highest-priority task that is ready to execute.
+ */
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
 
 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM23/secure/secure_context.c b/portable/IAR/ARM_CM23/secure/secure_context.c
index 0730d574d..7d2171996 100644
--- a/portable/IAR/ARM_CM23/secure/secure_context.c
+++ b/portable/IAR/ARM_CM23/secure/secure_context.c
@@ -65,7 +65,7 @@
  * @brief Maximum number of secure contexts.
  */
 #ifndef secureconfigMAX_SECURE_CONTEXTS
-    #define secureconfigMAX_SECURE_CONTEXTS        8UL
+    #define secureconfigMAX_SECURE_CONTEXTS    8UL
 #endif
 /*-----------------------------------------------------------*/
 
@@ -164,15 +164,15 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
         }
 
         #if ( configENABLE_MPU == 1 )
-            {
-                /* Configure thread mode to use PSP and to be unprivileged. */
-                secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
-            }
+        {
+            /* Configure thread mode to use PSP and to be unprivileged. */
+            secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
+        }
         #else /* configENABLE_MPU */
-            {
-                /* Configure thread mode to use PSP and to be privileged. */
-                secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
-            }
+        {
+            /* Configure thread mode to use PSP and to be privileged. */
+            secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
+        }
         #endif /* configENABLE_MPU */
     }
 }
@@ -219,16 +219,16 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
             if( pucStackMemory != NULL )
             {
                 /* Since stack grows down, the starting point will be the last
-                 * location. Note that this location is next to the last
-                 * allocated byte for stack (excluding the space for seal values)
-                 * because the hardware decrements the stack pointer before
-                 * writing i.e. if stack pointer is 0x2, a push operation will
-                 * decrement the stack pointer to 0x1 and then write at 0x1. */
+                * location. Note that this location is next to the last
+                * allocated byte for stack (excluding the space for seal values)
+                * because the hardware decrements the stack pointer before
+                * writing i.e. if stack pointer is 0x2, a push operation will
+                * decrement the stack pointer to 0x1 and then write at 0x1. */
                 xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize;
 
                 /* Seal the created secure process stack. */
-                *( uint32_t * )( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE;
-                *( uint32_t * )( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE;
+                *( uint32_t * ) ( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE;
+                *( uint32_t * ) ( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE;
 
                 /* The stack cannot go beyond this location. This value is
                  * programmed in the PSPLIM register on context switch.*/
@@ -237,32 +237,32 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
                 xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle;
 
                 #if ( configENABLE_MPU == 1 )
+                {
+                    /* Store the correct CONTROL value for the task on the stack.
+                     * This value is programmed in the CONTROL register on
+                     * context switch. */
+                    pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart;
+                    pulCurrentStackPointer--;
+
+                    if( ulIsTaskPrivileged )
                     {
-                        /* Store the correct CONTROL value for the task on the stack.
-                         * This value is programmed in the CONTROL register on
-                         * context switch. */
-                        pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart;
-                        pulCurrentStackPointer--;
-
-                        if( ulIsTaskPrivileged )
-                        {
-                            *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
-                        }
-                        else
-                        {
-                            *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
-                        }
-
-                        /* Store the current stack pointer. This value is programmed in
-                         * the PSP register on context switch. */
-                        xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+                        *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
                     }
+                    else
+                    {
+                        *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
+                    }
+
+                    /* Store the current stack pointer. This value is programmed in
+                     * the PSP register on context switch. */
+                    xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+                }
                 #else /* configENABLE_MPU */
-                    {
-                        /* Current SP is set to the starting of the stack. This
-                         * value programmed in the PSP register on context switch. */
-                        xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart;
-                    }
+                {
+                    /* Current SP is set to the starting of the stack. This
+                     * value programmed in the PSP register on context switch. */
+                    xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart;
+                }
                 #endif /* configENABLE_MPU */
 
                 /* Ensure to never return 0 as a valid context handle. */
@@ -275,7 +275,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
 }
 /*-----------------------------------------------------------*/
 
-secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle,
+                                                              void * pvTaskHandle )
 {
     uint32_t ulIPSR, ulSecureContextIndex;
 
@@ -306,7 +307,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandl
 }
 /*-----------------------------------------------------------*/
 
-secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle,
+                                                              void * pvTaskHandle )
 {
     uint8_t * pucStackLimit;
     uint32_t ulSecureContextIndex;
@@ -328,7 +330,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandl
 }
 /*-----------------------------------------------------------*/
 
-secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle,
+                                                              void * pvTaskHandle )
 {
     uint8_t * pucStackLimit;
     uint32_t ulSecureContextIndex;
diff --git a/portable/IAR/ARM_CM23/secure/secure_context.h b/portable/IAR/ARM_CM23/secure/secure_context.h
index d0adbaf01..0bf776198 100644
--- a/portable/IAR/ARM_CM23/secure/secure_context.h
+++ b/portable/IAR/ARM_CM23/secure/secure_context.h
@@ -38,12 +38,12 @@
 /**
  * @brief PSP value when no secure context is loaded.
  */
-#define securecontextNO_STACK               0x0
+#define securecontextNO_STACK              0x0
 
 /**
  * @brief Invalid context ID.
  */
-#define securecontextINVALID_CONTEXT_ID     0UL
+#define securecontextINVALID_CONTEXT_ID    0UL
 /*-----------------------------------------------------------*/
 
 /**
@@ -108,7 +108,8 @@ void SecureContext_Init( void );
  * @param[in] xSecureContextHandle Context handle corresponding to the
  * context to be freed.
  */
-void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle,
+                                void * pvTaskHandle );
 
 /**
  * @brief Loads the given context.
@@ -119,7 +120,8 @@ void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void
  * @param[in] xSecureContextHandle Context handle corresponding to the context
  * to be loaded.
  */
-void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle,
+                                void * pvTaskHandle );
 
 /**
  * @brief Saves the given context.
@@ -130,6 +132,7 @@ void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void
  * @param[in] xSecureContextHandle Context handle corresponding to the context
  * to be saved.
  */
-void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle,
+                                void * pvTaskHandle );
 
 #endif /* __SECURE_CONTEXT_H__ */
diff --git a/portable/IAR/ARM_CM23/secure/secure_heap.c b/portable/IAR/ARM_CM23/secure/secure_heap.c
index f3b80df54..1ec3bdbdb 100644
--- a/portable/IAR/ARM_CM23/secure/secure_heap.c
+++ b/portable/IAR/ARM_CM23/secure/secure_heap.c
@@ -67,7 +67,7 @@
 #define secureheapSIZE_MAX              ( ~( ( size_t ) 0 ) )
 
 /* Check if adding a and b will result in overflow. */
-#define secureheapADD_WILL_OVERFLOW( a, b )         ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) )
+#define secureheapADD_WILL_OVERFLOW( a, b )    ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) )
 
 /* MSB of the xBlockSize member of an BlockLink_t structure is used to track
  * the allocation status of a block.  When MSB of the xBlockSize member of
@@ -397,17 +397,17 @@ void * pvPortMalloc( size_t xWantedSize )
     traceMALLOC( pvReturn, xWantedSize );
 
     #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
+    {
+        if( pvReturn == NULL )
         {
-            if( pvReturn == NULL )
-            {
-                extern void vApplicationMallocFailedHook( void );
-                vApplicationMallocFailedHook();
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
+            extern void vApplicationMallocFailedHook( void );
+            vApplicationMallocFailedHook();
         }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
     #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */
 
     secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );
diff --git a/portable/IAR/ARM_CM23/secure/secure_init.c b/portable/IAR/ARM_CM23/secure/secure_init.c
index dc19ebc7d..b89c5f644 100644
--- a/portable/IAR/ARM_CM23/secure/secure_init.c
+++ b/portable/IAR/ARM_CM23/secure/secure_init.c
@@ -93,7 +93,7 @@ secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )
          * permitted. CP11 should be programmed to the same value as CP10. */
         *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
 
-        /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
+        /* LSPENS = 0 ==> LSPEN is writable from non-secure state. This ensures
          * that we can enable/disable lazy stacking in port.c file. */
         *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK );
 
diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
index 80410e82e..c940c304b 100644
--- a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
@@ -110,8 +110,8 @@
 /**
  * @brief Constants used during system call enter and exit.
  */
-#define portPSR_STACK_PADDING_MASK                ( 1UL << 9UL )
-#define portEXC_RETURN_STACK_FRAME_TYPE_MASK      ( 1UL << 4UL )
+#define portPSR_STACK_PADDING_MASK              ( 1UL << 9UL )
+#define portEXC_RETURN_STACK_FRAME_TYPE_MASK    ( 1UL << 4UL )
 /*-----------------------------------------------------------*/
 
 /**
@@ -133,81 +133,81 @@
 /**
  * @brief Offsets in the stack to the parameters when inside the SVC handler.
  */
-#define portOFFSET_TO_LR                    ( 5 )
-#define portOFFSET_TO_PC                    ( 6 )
-#define portOFFSET_TO_PSR                   ( 7 )
+#define portOFFSET_TO_LR     ( 5 )
+#define portOFFSET_TO_PC     ( 6 )
+#define portOFFSET_TO_PSR    ( 7 )
 /*-----------------------------------------------------------*/
 
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                      ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                      ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                       ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                      ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                      ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                     ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                     ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK  ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK               ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK               ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK               ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK               ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK               ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK               ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK               ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK               ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0              ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1              ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2              ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3              ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4              ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5              ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6              ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7              ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE            ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT      ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                      ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE             ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -216,11 +216,11 @@
 
 /* Extract last address of the MPU region as encoded in the
  * RLAR (Region Limit Address Register) value. */
-#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar )  \
+#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar ) \
     ( ( ( rlar ) & portMPU_RLAR_ADDRESS_MASK ) | ~portMPU_RLAR_ADDRESS_MASK )
 
 /* Does addr lies within [start, end] address range? */
-#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end )    \
+#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \
     ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) )
 
 /* Is the access request satisfied by the available permissions? */
@@ -422,54 +422,57 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the system call stack so that upon returning from
-     * SVC, the system call stack is used.
-     *
-     * It is used for the system calls with up to 4 parameters.
-     *
-     * @param pulTaskStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the system call stack so that upon returning from
+ * SVC, the system call stack is used.
+ *
+ * It is used for the system calls with up to 4 parameters.
+ *
+ * @param pulTaskStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallEnter( uint32_t * pulTaskStack,
+                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the system call stack so that upon returning from
-     * SVC, the system call stack is used.
-     *
-     * It is used for the system calls with 5 parameters.
-     *
-     * @param pulTaskStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the system call stack so that upon returning from
+ * SVC, the system call stack is used.
+ *
+ * It is used for the system calls with 5 parameters.
+ *
+ * @param pulTaskStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallEnter_1( uint32_t * pulTaskStack,
+                             uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the task stack so that upon returning from
-     * SVC, the task stack is used again.
-     *
-     * @param pulSystemCallStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the task stack so that upon returning from
+ * SVC, the task stack is used again.
+ *
+ * @param pulSystemCallStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallExit( uint32_t * pulSystemCallStack,
+                          uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Checks whether or not the calling task is privileged.
-     *
-     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
-     */
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
     BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
 
 #endif /* configENABLE_MPU == 1 */
@@ -1086,18 +1089,18 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             vRestoreContextOfFirstTask();
             break;
 
-        #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
-            case portSVC_RAISE_PRIVILEGE:
+            #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+                case portSVC_RAISE_PRIVILEGE:
 
-                /* Only raise the privilege, if the svc was raised from any of
-                 * the system calls. */
-                if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
-                    ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
-                {
-                    vRaisePrivilege();
-                }
-                break;
-        #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+                    /* Only raise the privilege, if the svc was raised from any of
+                     * the system calls. */
+                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+                    {
+                        vRaisePrivilege();
+                    }
+                    break;
+            #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
         default:
             /* Incorrect SVC call. */
@@ -1108,513 +1111,526 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulSystemCallStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallEnter( uint32_t * pulTaskStack,
+                           uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulSystemCallStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        /* This is not NULL only for the duration of the system call. */
-        configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+        #if defined( __ARMCC_VERSION )
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+
+            /* This is not NULL only for the duration of the system call. */
+            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the system call stack for the stack frame. */
+            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulSystemCallStack[ i ] = pulTaskStack[ i ];
+            }
+
+            /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
+             * restore it when we exit from the system call. */
+            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* Use the pulSystemCallStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+
+            /* Remember the location where we should copy the stack frame when we exit from
+             * the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+
+            /* Record if the hardware used padding to force the stack pointer
+             * to be double word aligned. */
+            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
+            {
+                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
             }
+
+            /* We ensure in pxPortInitialiseStack that the system call stack is
+             * double word aligned and therefore, there is no need of padding.
+             * Clear the bit[9] of stacked xPSR. */
+            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
+
+            /* Raise the privilege for the duration of the system call. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " bics r0, r1         \n" /* Clear nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the system call stack for the stack frame. */
-        pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulSystemCallStack[ i ] = pulTaskStack[ i ];
-        }
-
-        /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
-         * restore it when we exit from the system call. */
-        pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-        __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* Use the pulSystemCallStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-
-        /* Remember the location where we should copy the stack frame when we exit from
-         * the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-        /* Record if the hardware used padding to force the stack pointer
-         * to be double word aligned. */
-        if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-        {
-            pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-        }
-        else
-        {
-            pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-        }
-
-        /* We ensure in pxPortInitialiseStack that the system call stack is
-         * double word aligned and therefore, there is no need of padding.
-         * Clear the bit[9] of stacked xPSR. */
-        pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-        /* Raise the privilege for the duration of the system call. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " bics r0, r1         \n" /* Clear nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulSystemCallStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallEnter_1( uint32_t * pulTaskStack,
+                             uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulSystemCallStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        /* This is not NULL only for the duration of the system call. */
-        configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+        #if defined( __ARMCC_VERSION )
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+
+            /* This is not NULL only for the duration of the system call. */
+            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the system call stack for the stack frame and
+             * the parameter passed on the stack. We only need to copy one
+             * parameter but we still reserve 2 spaces to keep the stack
+             * double word aligned. */
+            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulSystemCallStack[ i ] = pulTaskStack[ i ];
+            }
+
+            /* Copy the parameter which is passed the stack. */
+            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
+            {
+                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
+
+                /* Record if the hardware used padding to force the stack pointer
+                 * to be double word aligned. */
+                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
+
+                /* Record if the hardware used padding to force the stack pointer
+                 * to be double word aligned. */
+                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
             }
+
+            /* Store the value of the LR and PSPLIM registers before the SVC was raised.
+             * We need to restore it when we exit from the system call. */
+            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* Use the pulSystemCallStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+
+            /* Remember the location where we should copy the stack frame when we exit from
+             * the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+
+            /* We ensure in pxPortInitialiseStack that the system call stack is
+             * double word aligned and therefore, there is no need of padding.
+             * Clear the bit[9] of stacked xPSR. */
+            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
+
+            /* Raise the privilege for the duration of the system call. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " bics r0, r1         \n" /* Clear nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the system call stack for the stack frame and
-         * the parameter passed on the stack. We only need to copy one
-         * parameter but we still reserve 2 spaces to keep the stack
-         * double word aligned. */
-        pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulSystemCallStack[ i ] = pulTaskStack[ i ];
-        }
-
-        /* Copy the parameter which is passed the stack. */
-        if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-        {
-            pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
-            /* Record if the hardware used padding to force the stack pointer
-             * to be double word aligned. */
-            pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-        }
-        else
-        {
-            pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
-            /* Record if the hardware used padding to force the stack pointer
-             * to be double word aligned. */
-            pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-        }
-
-        /* Store the value of the LR and PSPLIM registers before the SVC was raised.
-         * We need to restore it when we exit from the system call. */
-        pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-        __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* Use the pulSystemCallStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-
-        /* Remember the location where we should copy the stack frame when we exit from
-         * the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-        /* We ensure in pxPortInitialiseStack that the system call stack is
-         * double word aligned and therefore, there is no need of padding.
-         * Clear the bit[9] of stacked xPSR. */
-        pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-        /* Raise the privilege for the duration of the system call. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " bics r0, r1         \n" /* Clear nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulTaskStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallExit( uint32_t * pulSystemCallStack,
+                          uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulTaskStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+        #if defined( __ARMCC_VERSION )
+
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the task stack for the stack frame. */
+            pulTaskStack = pulTaskStack - ulStackFrameSize;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulTaskStack[ i ] = pulSystemCallStack[ i ];
+            }
+
+            /* Use the pulTaskStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
+
+            /* Restore the LR and PSPLIM to what they were at the time of
+             * system call entry. */
+            pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* If the hardware used padding to force the stack pointer
+             * to be double word aligned, set the stacked xPSR bit[9],
+             * otherwise clear it. */
+            if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG )
+            {
+                pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
             }
+
+            /* This is not NULL only for the duration of the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
+
+            /* Drop the privilege before returning to the thread mode. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " orrs r0, r1         \n" /* Set nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the task stack for the stack frame. */
-        pulTaskStack = pulTaskStack - ulStackFrameSize;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulTaskStack[ i ] = pulSystemCallStack[ i ];
-        }
-
-        /* Use the pulTaskStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
-
-        /* Restore the LR and PSPLIM to what they were at the time of
-         * system call entry. */
-        pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* If the hardware used padding to force the stack pointer
-         * to be double word aligned, set the stacked xPSR bit[9],
-         * otherwise clear it. */
-        if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG )
-        {
-            pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK;
-        }
-        else
-        {
-            pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-        }
-
-        /* This is not NULL only for the duration of the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
-
-        /* Drop the privilege before returning to the thread mode. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " orrs r0, r1         \n" /* Set nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */
-{
-    BaseType_t xTaskIsPrivileged = pdFALSE;
-    const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
-
-    if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+    BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */
     {
-        xTaskIsPrivileged = pdTRUE;
-    }
+        BaseType_t xTaskIsPrivileged = pdFALSE;
+        const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
 
-    return xTaskIsPrivileged;
-}
+        if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+        {
+            xTaskIsPrivileged = pdTRUE;
+        }
+
+        return xTaskIsPrivileged;
+    }
 
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
-#if( configENABLE_MPU == 1 )
+#if ( configENABLE_MPU == 1 )
 
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     StackType_t * pxEndOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters,
-                                     BaseType_t xRunPrivileged,
-                                     xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
-{
-    uint32_t ulIndex = 0;
-
-    xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
-    ulIndex++;
-
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
-    ulIndex++;
-
-    #if ( configENABLE_TRUSTZONE == 1 )
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters,
+                                         BaseType_t xRunPrivileged,
+                                         xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
     {
-        xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT;  /* xSecureContext. */
+        uint32_t ulIndex = 0;
+
+        xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
         ulIndex++;
-    }
-    #endif /* configENABLE_TRUSTZONE */
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
-    ulIndex++;
-    if( xRunPrivileged == pdTRUE )
-    {
-        xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */
         ulIndex++;
-    }
-    else
-    {
-        xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */
         ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
+        ulIndex++;
+
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters;            /* r0. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x01010101;                           /* r1. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x02020202;                           /* r2. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x03030303;                           /* r3. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x12121212;                           /* r12. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode;                  /* PC. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR;                     /* xPSR. */
+        ulIndex++;
+
+        #if ( configENABLE_TRUSTZONE == 1 )
+        {
+            xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT; /* xSecureContext. */
+            ulIndex++;
+        }
+        #endif /* configENABLE_TRUSTZONE */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
+        ulIndex++;
+
+        if( xRunPrivileged == pdTRUE )
+        {
+            xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
+            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+            ulIndex++;
+        }
+        else
+        {
+            xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
+            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+            ulIndex++;
+        }
+
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
+        ulIndex++;
+
+        #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+        {
+            /* Ensure that the system call stack is double word aligned. */
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] );
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) &
+                                                                                     ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
+
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] );
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) +
+                                                                                            ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) &
+                                                                                          ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
+
+            /* This is not NULL only for the duration of a system call. */
+            xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL;
+        }
+        #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
+
+        return &( xMPUSettings->ulContext[ ulIndex ] );
     }
-    xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
-    ulIndex++;
-
-    #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
-    {
-        /* Ensure that the system call stack is double word aligned. */
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] );
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) &
-                                                                                 ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
-
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] );
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) +
-                                                                                        ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) &
-                                                                                      ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
-
-        /* This is not NULL only for the duration of a system call. */
-        xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL;
-    }
-    #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
-
-    return &( xMPUSettings->ulContext[ ulIndex ] );
-}
 
 #else /* configENABLE_MPU */
 
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     StackType_t * pxEndOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters ) /* PRIVILEGED_FUNCTION */
-{
-    /* Simulate the stack frame as it would be created by a context switch
-     * interrupt. */
-    #if ( portPRELOAD_REGISTERS == 0 )
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters ) /* PRIVILEGED_FUNCTION */
     {
-        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-        pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
-        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-        pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
-        *pxTopOfStack = portINITIAL_EXC_RETURN;
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
-
-        #if ( configENABLE_TRUSTZONE == 1 )
+        /* Simulate the stack frame as it would be created by a context switch
+         * interrupt. */
+        #if ( portPRELOAD_REGISTERS == 0 )
         {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
-        }
-        #endif /* configENABLE_TRUSTZONE */
-    }
-    #else /* portPRELOAD_REGISTERS */
-    {
-        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
-        pxTopOfStack--;
-        *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
+            pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
+            *pxTopOfStack = portINITIAL_EXC_RETURN;
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+            #if ( configENABLE_TRUSTZONE == 1 )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+            }
+            #endif /* configENABLE_TRUSTZONE */
+        }
+        #else /* portPRELOAD_REGISTERS */
         {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
-        }
-        #endif /* configENABLE_TRUSTZONE */
-    }
-    #endif /* portPRELOAD_REGISTERS */
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
+            pxTopOfStack--;
+            *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack;            /* Slot used to hold this task's PSPLIM value. */
 
-    return pxTopOfStack;
-}
+            #if ( configENABLE_TRUSTZONE == 1 )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+            }
+            #endif /* configENABLE_TRUSTZONE */
+        }
+        #endif /* portPRELOAD_REGISTERS */
+
+        return pxTopOfStack;
+    }
 
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h b/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h
index 76ba7172e..e426f5b9a 100644
--- a/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h
@@ -48,9 +48,9 @@
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME                       "Cortex-M23"
-#define portHAS_ARMV8M_MAIN_EXTENSION       0
-#define portDONT_DISCARD                    __root
+#define portARCH_NAME                    "Cortex-M23"
+#define portHAS_ARMV8M_MAIN_EXTENSION    0
+#define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
 /* ARMv8-M common port configurations. */
diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h
index e5ffdb48b..62e462a27 100644
--- a/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h
@@ -81,8 +81,8 @@ typedef unsigned long    UBaseType_t;
     typedef uint32_t     TickType_t;
     #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-     * not need to be guarded with a critical section. */
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
     #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -117,7 +117,7 @@ extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGE
 extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
 
 #if ( configENABLE_TRUSTZONE == 1 )
-    extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize );     /* __attribute__ (( naked )) */
+    extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
     extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
 #endif /* configENABLE_TRUSTZONE */
 
@@ -188,13 +188,13 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Settings to define an MPU region.
-     */
+/**
+ * @brief Settings to define an MPU region.
+ */
     typedef struct MPURegionSettings
     {
-        uint32_t ulRBAR;     /**< RBAR for the region. */
-        uint32_t ulRLAR;     /**< RLAR for the region. */
+        uint32_t ulRBAR; /**< RBAR for the region. */
+        uint32_t ulRLAR; /**< RLAR for the region. */
     } MPURegionSettings_t;
 
     #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
@@ -203,9 +203,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-        /**
-         * @brief System call stack.
-         */
+/**
+ * @brief System call stack.
+ */
         typedef struct SYSTEM_CALL_STACK_INFO
         {
             uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ];
@@ -218,74 +218,74 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
-    /**
-     * @brief MPU settings as stored in the TCB.
-     */
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
     #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
 
-        #if( configENABLE_TRUSTZONE == 1 )
+        #if ( configENABLE_TRUSTZONE == 1 )
 
-            /*
-             * +-----------+---------------+----------+-----------------+------------------------------+-----+
-             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
-             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
-             * +-----------+---------------+----------+-----------------+------------------------------+-----+
-             *
-             * <-----------><--------------><---------><----------------><-----------------------------><---->
-             *      16             16            8               8                     5                   1
-             */
-            #define MAX_CONTEXT_SIZE 54
+/*
+ * +-----------+---------------+----------+-----------------+------------------------------+-----+
+ * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+ * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+ * +-----------+---------------+----------+-----------------+------------------------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><-----------------------------><---->
+ *      16             16            8               8                     5                   1
+ */
+            #define MAX_CONTEXT_SIZE    54
 
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-            /*
-             * +-----------+---------------+----------+-----------------+----------------------+-----+
-             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
-             * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
-             * +-----------+---------------+----------+-----------------+----------------------+-----+
-             *
-             * <-----------><--------------><---------><----------------><---------------------><---->
-             *      16             16            8               8                  4              1
-             */
-            #define MAX_CONTEXT_SIZE 53
+/*
+ * +-----------+---------------+----------+-----------------+----------------------+-----+
+ * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+ * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
+ * +-----------+---------------+----------+-----------------+----------------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><---------------------><---->
+ *      16             16            8               8                  4              1
+ */
+            #define MAX_CONTEXT_SIZE    53
 
         #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
 
     #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-        #if( configENABLE_TRUSTZONE == 1 )
+        #if ( configENABLE_TRUSTZONE == 1 )
 
-            /*
-             * +----------+-----------------+------------------------------+-----+
-             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
-             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
-             * +----------+-----------------+------------------------------+-----+
-             *
-             * <---------><----------------><------------------------------><---->
-             *     8               8                      5                   1
-             */
-            #define MAX_CONTEXT_SIZE 22
+/*
+ * +----------+-----------------+------------------------------+-----+
+ * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+ * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+ * +----------+-----------------+------------------------------+-----+
+ *
+ * <---------><----------------><------------------------------><---->
+ *     8               8                      5                   1
+ */
+            #define MAX_CONTEXT_SIZE    22
 
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-            /*
-             * +----------+-----------------+----------------------+-----+
-             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
-             * |          | PC, xPSR        | EXC_RETURN           |     |
-             * +----------+-----------------+----------------------+-----+
-             *
-             * <---------><----------------><----------------------><---->
-             *     8               8                  4              1
-             */
-            #define MAX_CONTEXT_SIZE 21
+/*
+ * +----------+-----------------+----------------------+-----+
+ * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+ * |          | PC, xPSR        | EXC_RETURN           |     |
+ * +----------+-----------------+----------------------+-----+
+ *
+ * <---------><----------------><----------------------><---->
+ *     8               8                  4              1
+ */
+            #define MAX_CONTEXT_SIZE    21
 
         #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
 
     #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-    /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
-    #define portSTACK_FRAME_HAS_PADDING_FLAG     ( 1UL << 0UL )
-    #define portTASK_IS_PRIVILEGED_FLAG          ( 1UL << 1UL )
+/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
+    #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
+    #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
     typedef struct MPU_SETTINGS
     {
@@ -364,49 +364,49 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-    /**
-     * @brief Allocate a secure context for the task.
-     *
-     * Tasks are not created with a secure context. Any task that is going to call
-     * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
-     * secure context before it calls any secure function.
-     *
-     * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
-     */
+/**
+ * @brief Allocate a secure context for the task.
+ *
+ * Tasks are not created with a secure context. Any task that is going to call
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+ * secure context before it calls any secure function.
+ *
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+ */
     #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
 
-    /**
-     * @brief Called when a task is deleted to delete the task's secure context,
-     * if it has one.
-     *
-     * @param[in] pxTCB The TCB of the task being deleted.
-     */
+/**
+ * @brief Called when a task is deleted to delete the task's secure context,
+ * if it has one.
+ *
+ * @param[in] pxTCB The TCB of the task being deleted.
+ */
     #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
 #endif /* configENABLE_TRUSTZONE */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Checks whether or not the processor is privileged.
-     *
-     * @return 1 if the processor is already privileged, 0 otherwise.
-     */
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
     #define portIS_PRIVILEGED()      xIsPrivileged()
 
-    /**
-     * @brief Raise an SVC request to raise privilege.
-     *
-     * The SVC handler checks that the SVC was raised from a system call and only
-     * then it raises the privilege. If this is called from any other place,
-     * the privilege is not raised.
-     */
+/**
+ * @brief Raise an SVC request to raise privilege.
+ *
+ * The SVC handler checks that the SVC was raised from a system call and only
+ * then it raises the privilege. If this is called from any other place,
+ * the privilege is not raised.
+ */
     #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
 
-    /**
-     * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
-     * register.
-     */
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
     #define portRESET_PRIVILEGE()    vResetPrivilege()
 #else
     #define portIS_PRIVILEGED()
@@ -419,12 +419,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     extern BaseType_t xPortIsTaskPrivileged( void );
 
-    /**
-     * @brief Checks whether or not the calling task is privileged.
-     *
-     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
-     */
-    #define portIS_TASK_PRIVILEGED()      xPortIsTaskPrivileged()
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
+    #define portIS_TASK_PRIVILEGED()    xPortIsTaskPrivileged()
 
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
@@ -439,9 +439,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * based on whether or not Mainline extension is implemented. */
 #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
     #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
-        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
     #else
-        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    0
     #endif
 #endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
 
@@ -450,9 +450,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  */
 #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
 
-    /**
-     * @brief Count the number of leading zeros in a 32-bit value.
-     */
+/**
+ * @brief Count the number of leading zeros in a 32-bit value.
+ */
     static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
     {
         uint32_t ulReturn;
@@ -462,7 +462,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         return ulReturn;
     }
 
-    /* Check the configuration. */
+/* Check the configuration. */
     #if ( configMAX_PRIORITIES > 32 )
         #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
     #endif
@@ -471,16 +471,16 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection.  Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
     #endif
 
-    /**
-     * @brief Store/clear the ready priorities in a bit map.
-     */
-    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+/**
+ * @brief Store/clear the ready priorities in a bit map.
+ */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )      ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )       ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 
-    /**
-     * @brief Get the priority of the highest-priority task that is ready to execute.
-     */
-    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )   uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+/**
+ * @brief Get the priority of the highest-priority task that is ready to execute.
+ */
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
 
 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM3/port.c b/portable/IAR/ARM_CM3/port.c
old mode 100755
new mode 100644
index d2298f4c1..5d44bdb32
--- a/portable/IAR/ARM_CM3/port.c
+++ b/portable/IAR/ARM_CM3/port.c
@@ -257,22 +257,22 @@ BaseType_t xPortStartScheduler( void )
         if( ulImplementedPrioBits == 8 )
         {
             /* When the hardware implements 8 priority bits, there is no way for
-            * the software to configure PRIGROUP to not have sub-priorities. As
-            * a result, the least significant bit is always used for sub-priority
-            * and there are 128 preemption priorities and 2 sub-priorities.
-            *
-            * This may cause some confusion in some cases - for example, if
-            * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
-            * priority interrupts will be masked in Critical Sections as those
-            * are at the same preemption priority. This may appear confusing as
-            * 4 is higher (numerically lower) priority than
-            * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
-            * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
-            * to 4, this confusion does not happen and the behaviour remains the same.
-            *
-            * The following assert ensures that the sub-priority bit in the
-            * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
-            * confusion. */
+             * the software to configure PRIGROUP to not have sub-priorities. As
+             * a result, the least significant bit is always used for sub-priority
+             * and there are 128 preemption priorities and 2 sub-priorities.
+             *
+             * This may cause some confusion in some cases - for example, if
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
+             * priority interrupts will be masked in Critical Sections as those
+             * are at the same preemption priority. This may appear confusing as
+             * 4 is higher (numerically lower) priority than
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
+             * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
+             * to 4, this confusion does not happen and the behaviour remains the same.
+             *
+             * The following assert ensures that the sub-priority bit in the
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
+             * confusion. */
             configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
             ulMaxPRIGROUPValue = 0;
         }
diff --git a/portable/IAR/ARM_CM3/portmacro.h b/portable/IAR/ARM_CM3/portmacro.h
index 92763ac78..7c7d5356d 100644
--- a/portable/IAR/ARM_CM3/portmacro.h
+++ b/portable/IAR/ARM_CM3/portmacro.h
@@ -28,7 +28,7 @@
 
 
 #ifndef PORTMACRO_H
-    #define PORTMACRO_H
+#define PORTMACRO_H
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
@@ -47,50 +47,50 @@
  */
 
 /* IAR includes. */
-    #include <intrinsics.h>
+#include <intrinsics.h>
 
 /* Type definitions. */
-    #define portCHAR          char
-    #define portFLOAT         float
-    #define portDOUBLE        double
-    #define portLONG          long
-    #define portSHORT         short
-    #define portSTACK_TYPE    uint32_t
-    #define portBASE_TYPE     long
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-    typedef portSTACK_TYPE   StackType_t;
-    typedef long             BaseType_t;
-    typedef unsigned long    UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
-    #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-        typedef uint16_t     TickType_t;
-        #define portMAX_DELAY              ( TickType_t ) 0xffff
-    #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-        typedef uint32_t     TickType_t;
-        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
  * not need to be guarded with a critical section. */
-        #define portTICK_TYPE_IS_ATOMIC    1
-    #else
-        #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
-    #endif
+    #define portTICK_TYPE_IS_ATOMIC    1
+#else
+    #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+#endif
 /*-----------------------------------------------------------*/
 
 /* Architecture specifics. */
-    #define portSTACK_GROWTH      ( -1 )
-    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-    #define portBYTE_ALIGNMENT    8
+#define portSTACK_GROWTH      ( -1 )
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT    8
 /*-----------------------------------------------------------*/
 
 /* Compiler directives. */
-    #define portWEAK_SYMBOL    __attribute__( ( weak ) )
+#define portWEAK_SYMBOL    __attribute__( ( weak ) )
 
 /*-----------------------------------------------------------*/
 
 
 /* Scheduler utilities. */
-    #define portYIELD()                                 \
+#define portYIELD()                                     \
     {                                                   \
         /* Set a PendSV to request a context switch. */ \
         portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
@@ -98,112 +98,112 @@
         __ISB();                                        \
     }
 
-    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
-    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-    #define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 )
-    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+#define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired != pdFALSE ) portYIELD( ); } while( 0 )
+#define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
 
 /*-----------------------------------------------------------*/
 
 /* Architecture specific optimisations. */
-    #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
-    #endif
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+    #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
+#endif
 
-    #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
 
 /* Check the configuration. */
-        #if ( configMAX_PRIORITIES > 32 )
-            #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
-        #endif
+    #if ( configMAX_PRIORITIES > 32 )
+        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+    #endif
 
 /* Store/clear the ready priorities in a bit map. */
-        #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-        #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 
 /*-----------------------------------------------------------*/
 
-        #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ( ( uint32_t ) __CLZ( ( uxReadyPriorities ) ) ) )
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ( ( uint32_t ) __CLZ( ( uxReadyPriorities ) ) ) )
 
-    #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 /*-----------------------------------------------------------*/
 
 /* Critical section management. */
-    extern void vPortEnterCritical( void );
-    extern void vPortExitCritical( void );
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
 
-    #define portDISABLE_INTERRUPTS()                           \
+#define portDISABLE_INTERRUPTS()                               \
     {                                                          \
         __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \
         __DSB();                                               \
         __ISB();                                               \
     }
 
-    #define portENABLE_INTERRUPTS()                   __set_BASEPRI( 0 )
-    #define portENTER_CRITICAL()                      vPortEnterCritical()
-    #define portEXIT_CRITICAL()                       vPortExitCritical()
-    #define portSET_INTERRUPT_MASK_FROM_ISR()         __get_BASEPRI(); portDISABLE_INTERRUPTS()
-    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    __set_BASEPRI( x )
+#define portENABLE_INTERRUPTS()                   __set_BASEPRI( 0 )
+#define portENTER_CRITICAL()                      vPortEnterCritical()
+#define portEXIT_CRITICAL()                       vPortExitCritical()
+#define portSET_INTERRUPT_MASK_FROM_ISR()         __get_BASEPRI(); portDISABLE_INTERRUPTS()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    __set_BASEPRI( x )
 /*-----------------------------------------------------------*/
 
 /* Tickless idle/low power functionality. */
-    #ifndef portSUPPRESS_TICKS_AND_SLEEP
-        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
-        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
-    #endif
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+    extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+    #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site.  These are
  * not necessary for to use this port.  They are defined so the common demo files
  * (which build with all the ports) will build. */
-    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
-    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 /*-----------------------------------------------------------*/
 
-    #ifdef configASSERT
-        void vPortValidateInterruptPriority( void );
-        #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
-    #endif
+#ifdef configASSERT
+    void vPortValidateInterruptPriority( void );
+    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
+#endif
 
 /* portNOP() is not required by this port. */
-    #define portNOP()
+#define portNOP()
 
-    #define portINLINE              __inline
+#define portINLINE              __inline
 
-    #ifndef portFORCE_INLINE
-        #define portFORCE_INLINE    inline __attribute__( ( always_inline ) )
-    #endif
+#ifndef portFORCE_INLINE
+    #define portFORCE_INLINE    inline __attribute__( ( always_inline ) )
+#endif
 
 /*-----------------------------------------------------------*/
 
-    portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
+portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
+{
+    uint32_t ulCurrentInterrupt;
+    BaseType_t xReturn;
+
+    /* Obtain the number of the currently executing interrupt. */
+    __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+    if( ulCurrentInterrupt == 0 )
     {
-        uint32_t ulCurrentInterrupt;
-        BaseType_t xReturn;
-
-        /* Obtain the number of the currently executing interrupt. */
-        __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
-
-        if( ulCurrentInterrupt == 0 )
-        {
-            xReturn = pdFALSE;
-        }
-        else
-        {
-            xReturn = pdTRUE;
-        }
-
-        return xReturn;
+        xReturn = pdFALSE;
     }
+    else
+    {
+        xReturn = pdTRUE;
+    }
+
+    return xReturn;
+}
 
 /*-----------------------------------------------------------*/
 
 /* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
  * the source code because to do so would cause other compilers to generate
  * warnings. */
-    #pragma diag_suppress=Pe191
-    #pragma diag_suppress=Pa082
+#pragma diag_suppress=Pe191
+#pragma diag_suppress=Pa082
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/IAR/ARM_CM33/non_secure/port.c b/portable/IAR/ARM_CM33/non_secure/port.c
index 80410e82e..c940c304b 100644
--- a/portable/IAR/ARM_CM33/non_secure/port.c
+++ b/portable/IAR/ARM_CM33/non_secure/port.c
@@ -110,8 +110,8 @@
 /**
  * @brief Constants used during system call enter and exit.
  */
-#define portPSR_STACK_PADDING_MASK                ( 1UL << 9UL )
-#define portEXC_RETURN_STACK_FRAME_TYPE_MASK      ( 1UL << 4UL )
+#define portPSR_STACK_PADDING_MASK              ( 1UL << 9UL )
+#define portEXC_RETURN_STACK_FRAME_TYPE_MASK    ( 1UL << 4UL )
 /*-----------------------------------------------------------*/
 
 /**
@@ -133,81 +133,81 @@
 /**
  * @brief Offsets in the stack to the parameters when inside the SVC handler.
  */
-#define portOFFSET_TO_LR                    ( 5 )
-#define portOFFSET_TO_PC                    ( 6 )
-#define portOFFSET_TO_PSR                   ( 7 )
+#define portOFFSET_TO_LR     ( 5 )
+#define portOFFSET_TO_PC     ( 6 )
+#define portOFFSET_TO_PSR    ( 7 )
 /*-----------------------------------------------------------*/
 
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                      ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                      ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                       ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                      ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                      ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                     ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                     ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK  ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK               ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK               ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK               ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK               ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK               ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK               ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK               ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK               ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0              ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1              ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2              ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3              ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4              ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5              ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6              ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7              ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE            ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT      ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                      ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE             ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -216,11 +216,11 @@
 
 /* Extract last address of the MPU region as encoded in the
  * RLAR (Region Limit Address Register) value. */
-#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar )  \
+#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar ) \
     ( ( ( rlar ) & portMPU_RLAR_ADDRESS_MASK ) | ~portMPU_RLAR_ADDRESS_MASK )
 
 /* Does addr lies within [start, end] address range? */
-#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end )    \
+#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \
     ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) )
 
 /* Is the access request satisfied by the available permissions? */
@@ -422,54 +422,57 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the system call stack so that upon returning from
-     * SVC, the system call stack is used.
-     *
-     * It is used for the system calls with up to 4 parameters.
-     *
-     * @param pulTaskStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the system call stack so that upon returning from
+ * SVC, the system call stack is used.
+ *
+ * It is used for the system calls with up to 4 parameters.
+ *
+ * @param pulTaskStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallEnter( uint32_t * pulTaskStack,
+                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the system call stack so that upon returning from
-     * SVC, the system call stack is used.
-     *
-     * It is used for the system calls with 5 parameters.
-     *
-     * @param pulTaskStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the system call stack so that upon returning from
+ * SVC, the system call stack is used.
+ *
+ * It is used for the system calls with 5 parameters.
+ *
+ * @param pulTaskStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallEnter_1( uint32_t * pulTaskStack,
+                             uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the task stack so that upon returning from
-     * SVC, the task stack is used again.
-     *
-     * @param pulSystemCallStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the task stack so that upon returning from
+ * SVC, the task stack is used again.
+ *
+ * @param pulSystemCallStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallExit( uint32_t * pulSystemCallStack,
+                          uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Checks whether or not the calling task is privileged.
-     *
-     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
-     */
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
     BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
 
 #endif /* configENABLE_MPU == 1 */
@@ -1086,18 +1089,18 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             vRestoreContextOfFirstTask();
             break;
 
-        #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
-            case portSVC_RAISE_PRIVILEGE:
+            #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+                case portSVC_RAISE_PRIVILEGE:
 
-                /* Only raise the privilege, if the svc was raised from any of
-                 * the system calls. */
-                if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
-                    ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
-                {
-                    vRaisePrivilege();
-                }
-                break;
-        #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+                    /* Only raise the privilege, if the svc was raised from any of
+                     * the system calls. */
+                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+                    {
+                        vRaisePrivilege();
+                    }
+                    break;
+            #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
         default:
             /* Incorrect SVC call. */
@@ -1108,513 +1111,526 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulSystemCallStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallEnter( uint32_t * pulTaskStack,
+                           uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulSystemCallStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        /* This is not NULL only for the duration of the system call. */
-        configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+        #if defined( __ARMCC_VERSION )
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+
+            /* This is not NULL only for the duration of the system call. */
+            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the system call stack for the stack frame. */
+            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulSystemCallStack[ i ] = pulTaskStack[ i ];
+            }
+
+            /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
+             * restore it when we exit from the system call. */
+            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* Use the pulSystemCallStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+
+            /* Remember the location where we should copy the stack frame when we exit from
+             * the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+
+            /* Record if the hardware used padding to force the stack pointer
+             * to be double word aligned. */
+            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
+            {
+                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
             }
+
+            /* We ensure in pxPortInitialiseStack that the system call stack is
+             * double word aligned and therefore, there is no need of padding.
+             * Clear the bit[9] of stacked xPSR. */
+            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
+
+            /* Raise the privilege for the duration of the system call. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " bics r0, r1         \n" /* Clear nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the system call stack for the stack frame. */
-        pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulSystemCallStack[ i ] = pulTaskStack[ i ];
-        }
-
-        /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
-         * restore it when we exit from the system call. */
-        pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-        __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* Use the pulSystemCallStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-
-        /* Remember the location where we should copy the stack frame when we exit from
-         * the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-        /* Record if the hardware used padding to force the stack pointer
-         * to be double word aligned. */
-        if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-        {
-            pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-        }
-        else
-        {
-            pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-        }
-
-        /* We ensure in pxPortInitialiseStack that the system call stack is
-         * double word aligned and therefore, there is no need of padding.
-         * Clear the bit[9] of stacked xPSR. */
-        pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-        /* Raise the privilege for the duration of the system call. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " bics r0, r1         \n" /* Clear nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulSystemCallStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallEnter_1( uint32_t * pulTaskStack,
+                             uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulSystemCallStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        /* This is not NULL only for the duration of the system call. */
-        configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+        #if defined( __ARMCC_VERSION )
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+
+            /* This is not NULL only for the duration of the system call. */
+            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the system call stack for the stack frame and
+             * the parameter passed on the stack. We only need to copy one
+             * parameter but we still reserve 2 spaces to keep the stack
+             * double word aligned. */
+            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulSystemCallStack[ i ] = pulTaskStack[ i ];
+            }
+
+            /* Copy the parameter which is passed the stack. */
+            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
+            {
+                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
+
+                /* Record if the hardware used padding to force the stack pointer
+                 * to be double word aligned. */
+                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
+
+                /* Record if the hardware used padding to force the stack pointer
+                 * to be double word aligned. */
+                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
             }
+
+            /* Store the value of the LR and PSPLIM registers before the SVC was raised.
+             * We need to restore it when we exit from the system call. */
+            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* Use the pulSystemCallStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+
+            /* Remember the location where we should copy the stack frame when we exit from
+             * the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+
+            /* We ensure in pxPortInitialiseStack that the system call stack is
+             * double word aligned and therefore, there is no need of padding.
+             * Clear the bit[9] of stacked xPSR. */
+            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
+
+            /* Raise the privilege for the duration of the system call. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " bics r0, r1         \n" /* Clear nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the system call stack for the stack frame and
-         * the parameter passed on the stack. We only need to copy one
-         * parameter but we still reserve 2 spaces to keep the stack
-         * double word aligned. */
-        pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulSystemCallStack[ i ] = pulTaskStack[ i ];
-        }
-
-        /* Copy the parameter which is passed the stack. */
-        if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-        {
-            pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
-            /* Record if the hardware used padding to force the stack pointer
-             * to be double word aligned. */
-            pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-        }
-        else
-        {
-            pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
-            /* Record if the hardware used padding to force the stack pointer
-             * to be double word aligned. */
-            pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-        }
-
-        /* Store the value of the LR and PSPLIM registers before the SVC was raised.
-         * We need to restore it when we exit from the system call. */
-        pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-        __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* Use the pulSystemCallStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-
-        /* Remember the location where we should copy the stack frame when we exit from
-         * the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-        /* We ensure in pxPortInitialiseStack that the system call stack is
-         * double word aligned and therefore, there is no need of padding.
-         * Clear the bit[9] of stacked xPSR. */
-        pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-        /* Raise the privilege for the duration of the system call. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " bics r0, r1         \n" /* Clear nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulTaskStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallExit( uint32_t * pulSystemCallStack,
+                          uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulTaskStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+        #if defined( __ARMCC_VERSION )
+
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the task stack for the stack frame. */
+            pulTaskStack = pulTaskStack - ulStackFrameSize;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulTaskStack[ i ] = pulSystemCallStack[ i ];
+            }
+
+            /* Use the pulTaskStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
+
+            /* Restore the LR and PSPLIM to what they were at the time of
+             * system call entry. */
+            pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* If the hardware used padding to force the stack pointer
+             * to be double word aligned, set the stacked xPSR bit[9],
+             * otherwise clear it. */
+            if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG )
+            {
+                pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
             }
+
+            /* This is not NULL only for the duration of the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
+
+            /* Drop the privilege before returning to the thread mode. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " orrs r0, r1         \n" /* Set nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the task stack for the stack frame. */
-        pulTaskStack = pulTaskStack - ulStackFrameSize;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulTaskStack[ i ] = pulSystemCallStack[ i ];
-        }
-
-        /* Use the pulTaskStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
-
-        /* Restore the LR and PSPLIM to what they were at the time of
-         * system call entry. */
-        pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* If the hardware used padding to force the stack pointer
-         * to be double word aligned, set the stacked xPSR bit[9],
-         * otherwise clear it. */
-        if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG )
-        {
-            pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK;
-        }
-        else
-        {
-            pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-        }
-
-        /* This is not NULL only for the duration of the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
-
-        /* Drop the privilege before returning to the thread mode. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " orrs r0, r1         \n" /* Set nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */
-{
-    BaseType_t xTaskIsPrivileged = pdFALSE;
-    const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
-
-    if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+    BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */
     {
-        xTaskIsPrivileged = pdTRUE;
-    }
+        BaseType_t xTaskIsPrivileged = pdFALSE;
+        const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
 
-    return xTaskIsPrivileged;
-}
+        if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+        {
+            xTaskIsPrivileged = pdTRUE;
+        }
+
+        return xTaskIsPrivileged;
+    }
 
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
-#if( configENABLE_MPU == 1 )
+#if ( configENABLE_MPU == 1 )
 
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     StackType_t * pxEndOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters,
-                                     BaseType_t xRunPrivileged,
-                                     xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
-{
-    uint32_t ulIndex = 0;
-
-    xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
-    ulIndex++;
-
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
-    ulIndex++;
-
-    #if ( configENABLE_TRUSTZONE == 1 )
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters,
+                                         BaseType_t xRunPrivileged,
+                                         xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
     {
-        xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT;  /* xSecureContext. */
+        uint32_t ulIndex = 0;
+
+        xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
         ulIndex++;
-    }
-    #endif /* configENABLE_TRUSTZONE */
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
-    ulIndex++;
-    if( xRunPrivileged == pdTRUE )
-    {
-        xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */
         ulIndex++;
-    }
-    else
-    {
-        xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */
         ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
+        ulIndex++;
+
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters;            /* r0. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x01010101;                           /* r1. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x02020202;                           /* r2. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x03030303;                           /* r3. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x12121212;                           /* r12. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode;                  /* PC. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR;                     /* xPSR. */
+        ulIndex++;
+
+        #if ( configENABLE_TRUSTZONE == 1 )
+        {
+            xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT; /* xSecureContext. */
+            ulIndex++;
+        }
+        #endif /* configENABLE_TRUSTZONE */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
+        ulIndex++;
+
+        if( xRunPrivileged == pdTRUE )
+        {
+            xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
+            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+            ulIndex++;
+        }
+        else
+        {
+            xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
+            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+            ulIndex++;
+        }
+
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
+        ulIndex++;
+
+        #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+        {
+            /* Ensure that the system call stack is double word aligned. */
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] );
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) &
+                                                                                     ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
+
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] );
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) +
+                                                                                            ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) &
+                                                                                          ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
+
+            /* This is not NULL only for the duration of a system call. */
+            xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL;
+        }
+        #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
+
+        return &( xMPUSettings->ulContext[ ulIndex ] );
     }
-    xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
-    ulIndex++;
-
-    #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
-    {
-        /* Ensure that the system call stack is double word aligned. */
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] );
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) &
-                                                                                 ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
-
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] );
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) +
-                                                                                        ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) &
-                                                                                      ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
-
-        /* This is not NULL only for the duration of a system call. */
-        xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL;
-    }
-    #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
-
-    return &( xMPUSettings->ulContext[ ulIndex ] );
-}
 
 #else /* configENABLE_MPU */
 
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     StackType_t * pxEndOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters ) /* PRIVILEGED_FUNCTION */
-{
-    /* Simulate the stack frame as it would be created by a context switch
-     * interrupt. */
-    #if ( portPRELOAD_REGISTERS == 0 )
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters ) /* PRIVILEGED_FUNCTION */
     {
-        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-        pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
-        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-        pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
-        *pxTopOfStack = portINITIAL_EXC_RETURN;
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
-
-        #if ( configENABLE_TRUSTZONE == 1 )
+        /* Simulate the stack frame as it would be created by a context switch
+         * interrupt. */
+        #if ( portPRELOAD_REGISTERS == 0 )
         {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
-        }
-        #endif /* configENABLE_TRUSTZONE */
-    }
-    #else /* portPRELOAD_REGISTERS */
-    {
-        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
-        pxTopOfStack--;
-        *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
+            pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
+            *pxTopOfStack = portINITIAL_EXC_RETURN;
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+            #if ( configENABLE_TRUSTZONE == 1 )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+            }
+            #endif /* configENABLE_TRUSTZONE */
+        }
+        #else /* portPRELOAD_REGISTERS */
         {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
-        }
-        #endif /* configENABLE_TRUSTZONE */
-    }
-    #endif /* portPRELOAD_REGISTERS */
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
+            pxTopOfStack--;
+            *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack;            /* Slot used to hold this task's PSPLIM value. */
 
-    return pxTopOfStack;
-}
+            #if ( configENABLE_TRUSTZONE == 1 )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+            }
+            #endif /* configENABLE_TRUSTZONE */
+        }
+        #endif /* portPRELOAD_REGISTERS */
+
+        return pxTopOfStack;
+    }
 
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM33/non_secure/portmacro.h b/portable/IAR/ARM_CM33/non_secure/portmacro.h
index 145f5246e..a707fc658 100644
--- a/portable/IAR/ARM_CM33/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM33/non_secure/portmacro.h
@@ -48,12 +48,12 @@
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME                       "Cortex-M33"
-#define portHAS_ARMV8M_MAIN_EXTENSION       1
-#define portDONT_DISCARD                    __root
+#define portARCH_NAME                    "Cortex-M33"
+#define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
-#if( configTOTAL_MPU_REGIONS == 16 )
+#if ( configTOTAL_MPU_REGIONS == 16 )
     #error 16 MPU regions are not yet supported for this port.
 #endif
 /*-----------------------------------------------------------*/
@@ -65,8 +65,8 @@
 /**
  * @brief Critical section management.
  */
-#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()
-#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )
+#define portDISABLE_INTERRUPTS()    ulSetInterruptMask()
+#define portENABLE_INTERRUPTS()     vClearInterruptMask( 0 )
 /*-----------------------------------------------------------*/
 
 /* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
diff --git a/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h
index e5ffdb48b..62e462a27 100644
--- a/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h
@@ -81,8 +81,8 @@ typedef unsigned long    UBaseType_t;
     typedef uint32_t     TickType_t;
     #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-     * not need to be guarded with a critical section. */
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
     #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -117,7 +117,7 @@ extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGE
 extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
 
 #if ( configENABLE_TRUSTZONE == 1 )
-    extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize );     /* __attribute__ (( naked )) */
+    extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
     extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
 #endif /* configENABLE_TRUSTZONE */
 
@@ -188,13 +188,13 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Settings to define an MPU region.
-     */
+/**
+ * @brief Settings to define an MPU region.
+ */
     typedef struct MPURegionSettings
     {
-        uint32_t ulRBAR;     /**< RBAR for the region. */
-        uint32_t ulRLAR;     /**< RLAR for the region. */
+        uint32_t ulRBAR; /**< RBAR for the region. */
+        uint32_t ulRLAR; /**< RLAR for the region. */
     } MPURegionSettings_t;
 
     #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
@@ -203,9 +203,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-        /**
-         * @brief System call stack.
-         */
+/**
+ * @brief System call stack.
+ */
         typedef struct SYSTEM_CALL_STACK_INFO
         {
             uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ];
@@ -218,74 +218,74 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
-    /**
-     * @brief MPU settings as stored in the TCB.
-     */
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
     #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
 
-        #if( configENABLE_TRUSTZONE == 1 )
+        #if ( configENABLE_TRUSTZONE == 1 )
 
-            /*
-             * +-----------+---------------+----------+-----------------+------------------------------+-----+
-             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
-             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
-             * +-----------+---------------+----------+-----------------+------------------------------+-----+
-             *
-             * <-----------><--------------><---------><----------------><-----------------------------><---->
-             *      16             16            8               8                     5                   1
-             */
-            #define MAX_CONTEXT_SIZE 54
+/*
+ * +-----------+---------------+----------+-----------------+------------------------------+-----+
+ * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+ * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+ * +-----------+---------------+----------+-----------------+------------------------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><-----------------------------><---->
+ *      16             16            8               8                     5                   1
+ */
+            #define MAX_CONTEXT_SIZE    54
 
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-            /*
-             * +-----------+---------------+----------+-----------------+----------------------+-----+
-             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
-             * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
-             * +-----------+---------------+----------+-----------------+----------------------+-----+
-             *
-             * <-----------><--------------><---------><----------------><---------------------><---->
-             *      16             16            8               8                  4              1
-             */
-            #define MAX_CONTEXT_SIZE 53
+/*
+ * +-----------+---------------+----------+-----------------+----------------------+-----+
+ * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+ * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
+ * +-----------+---------------+----------+-----------------+----------------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><---------------------><---->
+ *      16             16            8               8                  4              1
+ */
+            #define MAX_CONTEXT_SIZE    53
 
         #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
 
     #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-        #if( configENABLE_TRUSTZONE == 1 )
+        #if ( configENABLE_TRUSTZONE == 1 )
 
-            /*
-             * +----------+-----------------+------------------------------+-----+
-             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
-             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
-             * +----------+-----------------+------------------------------+-----+
-             *
-             * <---------><----------------><------------------------------><---->
-             *     8               8                      5                   1
-             */
-            #define MAX_CONTEXT_SIZE 22
+/*
+ * +----------+-----------------+------------------------------+-----+
+ * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+ * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+ * +----------+-----------------+------------------------------+-----+
+ *
+ * <---------><----------------><------------------------------><---->
+ *     8               8                      5                   1
+ */
+            #define MAX_CONTEXT_SIZE    22
 
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-            /*
-             * +----------+-----------------+----------------------+-----+
-             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
-             * |          | PC, xPSR        | EXC_RETURN           |     |
-             * +----------+-----------------+----------------------+-----+
-             *
-             * <---------><----------------><----------------------><---->
-             *     8               8                  4              1
-             */
-            #define MAX_CONTEXT_SIZE 21
+/*
+ * +----------+-----------------+----------------------+-----+
+ * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+ * |          | PC, xPSR        | EXC_RETURN           |     |
+ * +----------+-----------------+----------------------+-----+
+ *
+ * <---------><----------------><----------------------><---->
+ *     8               8                  4              1
+ */
+            #define MAX_CONTEXT_SIZE    21
 
         #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
 
     #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-    /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
-    #define portSTACK_FRAME_HAS_PADDING_FLAG     ( 1UL << 0UL )
-    #define portTASK_IS_PRIVILEGED_FLAG          ( 1UL << 1UL )
+/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
+    #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
+    #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
     typedef struct MPU_SETTINGS
     {
@@ -364,49 +364,49 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-    /**
-     * @brief Allocate a secure context for the task.
-     *
-     * Tasks are not created with a secure context. Any task that is going to call
-     * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
-     * secure context before it calls any secure function.
-     *
-     * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
-     */
+/**
+ * @brief Allocate a secure context for the task.
+ *
+ * Tasks are not created with a secure context. Any task that is going to call
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+ * secure context before it calls any secure function.
+ *
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+ */
     #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
 
-    /**
-     * @brief Called when a task is deleted to delete the task's secure context,
-     * if it has one.
-     *
-     * @param[in] pxTCB The TCB of the task being deleted.
-     */
+/**
+ * @brief Called when a task is deleted to delete the task's secure context,
+ * if it has one.
+ *
+ * @param[in] pxTCB The TCB of the task being deleted.
+ */
     #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
 #endif /* configENABLE_TRUSTZONE */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Checks whether or not the processor is privileged.
-     *
-     * @return 1 if the processor is already privileged, 0 otherwise.
-     */
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
     #define portIS_PRIVILEGED()      xIsPrivileged()
 
-    /**
-     * @brief Raise an SVC request to raise privilege.
-     *
-     * The SVC handler checks that the SVC was raised from a system call and only
-     * then it raises the privilege. If this is called from any other place,
-     * the privilege is not raised.
-     */
+/**
+ * @brief Raise an SVC request to raise privilege.
+ *
+ * The SVC handler checks that the SVC was raised from a system call and only
+ * then it raises the privilege. If this is called from any other place,
+ * the privilege is not raised.
+ */
     #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
 
-    /**
-     * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
-     * register.
-     */
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
     #define portRESET_PRIVILEGE()    vResetPrivilege()
 #else
     #define portIS_PRIVILEGED()
@@ -419,12 +419,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     extern BaseType_t xPortIsTaskPrivileged( void );
 
-    /**
-     * @brief Checks whether or not the calling task is privileged.
-     *
-     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
-     */
-    #define portIS_TASK_PRIVILEGED()      xPortIsTaskPrivileged()
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
+    #define portIS_TASK_PRIVILEGED()    xPortIsTaskPrivileged()
 
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
@@ -439,9 +439,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * based on whether or not Mainline extension is implemented. */
 #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
     #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
-        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
     #else
-        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    0
     #endif
 #endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
 
@@ -450,9 +450,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  */
 #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
 
-    /**
-     * @brief Count the number of leading zeros in a 32-bit value.
-     */
+/**
+ * @brief Count the number of leading zeros in a 32-bit value.
+ */
     static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
     {
         uint32_t ulReturn;
@@ -462,7 +462,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         return ulReturn;
     }
 
-    /* Check the configuration. */
+/* Check the configuration. */
     #if ( configMAX_PRIORITIES > 32 )
         #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
     #endif
@@ -471,16 +471,16 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection.  Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
     #endif
 
-    /**
-     * @brief Store/clear the ready priorities in a bit map.
-     */
-    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+/**
+ * @brief Store/clear the ready priorities in a bit map.
+ */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )      ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )       ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 
-    /**
-     * @brief Get the priority of the highest-priority task that is ready to execute.
-     */
-    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )   uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+/**
+ * @brief Get the priority of the highest-priority task that is ready to execute.
+ */
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
 
 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM33/secure/secure_context.c b/portable/IAR/ARM_CM33/secure/secure_context.c
index 0730d574d..7d2171996 100644
--- a/portable/IAR/ARM_CM33/secure/secure_context.c
+++ b/portable/IAR/ARM_CM33/secure/secure_context.c
@@ -65,7 +65,7 @@
  * @brief Maximum number of secure contexts.
  */
 #ifndef secureconfigMAX_SECURE_CONTEXTS
-    #define secureconfigMAX_SECURE_CONTEXTS        8UL
+    #define secureconfigMAX_SECURE_CONTEXTS    8UL
 #endif
 /*-----------------------------------------------------------*/
 
@@ -164,15 +164,15 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
         }
 
         #if ( configENABLE_MPU == 1 )
-            {
-                /* Configure thread mode to use PSP and to be unprivileged. */
-                secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
-            }
+        {
+            /* Configure thread mode to use PSP and to be unprivileged. */
+            secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
+        }
         #else /* configENABLE_MPU */
-            {
-                /* Configure thread mode to use PSP and to be privileged. */
-                secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
-            }
+        {
+            /* Configure thread mode to use PSP and to be privileged. */
+            secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
+        }
         #endif /* configENABLE_MPU */
     }
 }
@@ -219,16 +219,16 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
             if( pucStackMemory != NULL )
             {
                 /* Since stack grows down, the starting point will be the last
-                 * location. Note that this location is next to the last
-                 * allocated byte for stack (excluding the space for seal values)
-                 * because the hardware decrements the stack pointer before
-                 * writing i.e. if stack pointer is 0x2, a push operation will
-                 * decrement the stack pointer to 0x1 and then write at 0x1. */
+                * location. Note that this location is next to the last
+                * allocated byte for stack (excluding the space for seal values)
+                * because the hardware decrements the stack pointer before
+                * writing i.e. if stack pointer is 0x2, a push operation will
+                * decrement the stack pointer to 0x1 and then write at 0x1. */
                 xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize;
 
                 /* Seal the created secure process stack. */
-                *( uint32_t * )( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE;
-                *( uint32_t * )( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE;
+                *( uint32_t * ) ( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE;
+                *( uint32_t * ) ( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE;
 
                 /* The stack cannot go beyond this location. This value is
                  * programmed in the PSPLIM register on context switch.*/
@@ -237,32 +237,32 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
                 xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle;
 
                 #if ( configENABLE_MPU == 1 )
+                {
+                    /* Store the correct CONTROL value for the task on the stack.
+                     * This value is programmed in the CONTROL register on
+                     * context switch. */
+                    pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart;
+                    pulCurrentStackPointer--;
+
+                    if( ulIsTaskPrivileged )
                     {
-                        /* Store the correct CONTROL value for the task on the stack.
-                         * This value is programmed in the CONTROL register on
-                         * context switch. */
-                        pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart;
-                        pulCurrentStackPointer--;
-
-                        if( ulIsTaskPrivileged )
-                        {
-                            *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
-                        }
-                        else
-                        {
-                            *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
-                        }
-
-                        /* Store the current stack pointer. This value is programmed in
-                         * the PSP register on context switch. */
-                        xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+                        *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
                     }
+                    else
+                    {
+                        *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
+                    }
+
+                    /* Store the current stack pointer. This value is programmed in
+                     * the PSP register on context switch. */
+                    xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+                }
                 #else /* configENABLE_MPU */
-                    {
-                        /* Current SP is set to the starting of the stack. This
-                         * value programmed in the PSP register on context switch. */
-                        xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart;
-                    }
+                {
+                    /* Current SP is set to the starting of the stack. This
+                     * value programmed in the PSP register on context switch. */
+                    xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart;
+                }
                 #endif /* configENABLE_MPU */
 
                 /* Ensure to never return 0 as a valid context handle. */
@@ -275,7 +275,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
 }
 /*-----------------------------------------------------------*/
 
-secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle,
+                                                              void * pvTaskHandle )
 {
     uint32_t ulIPSR, ulSecureContextIndex;
 
@@ -306,7 +307,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandl
 }
 /*-----------------------------------------------------------*/
 
-secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle,
+                                                              void * pvTaskHandle )
 {
     uint8_t * pucStackLimit;
     uint32_t ulSecureContextIndex;
@@ -328,7 +330,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandl
 }
 /*-----------------------------------------------------------*/
 
-secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle,
+                                                              void * pvTaskHandle )
 {
     uint8_t * pucStackLimit;
     uint32_t ulSecureContextIndex;
diff --git a/portable/IAR/ARM_CM33/secure/secure_context.h b/portable/IAR/ARM_CM33/secure/secure_context.h
index d0adbaf01..0bf776198 100644
--- a/portable/IAR/ARM_CM33/secure/secure_context.h
+++ b/portable/IAR/ARM_CM33/secure/secure_context.h
@@ -38,12 +38,12 @@
 /**
  * @brief PSP value when no secure context is loaded.
  */
-#define securecontextNO_STACK               0x0
+#define securecontextNO_STACK              0x0
 
 /**
  * @brief Invalid context ID.
  */
-#define securecontextINVALID_CONTEXT_ID     0UL
+#define securecontextINVALID_CONTEXT_ID    0UL
 /*-----------------------------------------------------------*/
 
 /**
@@ -108,7 +108,8 @@ void SecureContext_Init( void );
  * @param[in] xSecureContextHandle Context handle corresponding to the
  * context to be freed.
  */
-void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle,
+                                void * pvTaskHandle );
 
 /**
  * @brief Loads the given context.
@@ -119,7 +120,8 @@ void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void
  * @param[in] xSecureContextHandle Context handle corresponding to the context
  * to be loaded.
  */
-void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle,
+                                void * pvTaskHandle );
 
 /**
  * @brief Saves the given context.
@@ -130,6 +132,7 @@ void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void
  * @param[in] xSecureContextHandle Context handle corresponding to the context
  * to be saved.
  */
-void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle,
+                                void * pvTaskHandle );
 
 #endif /* __SECURE_CONTEXT_H__ */
diff --git a/portable/IAR/ARM_CM33/secure/secure_heap.c b/portable/IAR/ARM_CM33/secure/secure_heap.c
index f3b80df54..1ec3bdbdb 100644
--- a/portable/IAR/ARM_CM33/secure/secure_heap.c
+++ b/portable/IAR/ARM_CM33/secure/secure_heap.c
@@ -67,7 +67,7 @@
 #define secureheapSIZE_MAX              ( ~( ( size_t ) 0 ) )
 
 /* Check if adding a and b will result in overflow. */
-#define secureheapADD_WILL_OVERFLOW( a, b )         ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) )
+#define secureheapADD_WILL_OVERFLOW( a, b )    ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) )
 
 /* MSB of the xBlockSize member of an BlockLink_t structure is used to track
  * the allocation status of a block.  When MSB of the xBlockSize member of
@@ -397,17 +397,17 @@ void * pvPortMalloc( size_t xWantedSize )
     traceMALLOC( pvReturn, xWantedSize );
 
     #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
+    {
+        if( pvReturn == NULL )
         {
-            if( pvReturn == NULL )
-            {
-                extern void vApplicationMallocFailedHook( void );
-                vApplicationMallocFailedHook();
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
+            extern void vApplicationMallocFailedHook( void );
+            vApplicationMallocFailedHook();
         }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
     #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */
 
     secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );
diff --git a/portable/IAR/ARM_CM33/secure/secure_init.c b/portable/IAR/ARM_CM33/secure/secure_init.c
index dc19ebc7d..b89c5f644 100644
--- a/portable/IAR/ARM_CM33/secure/secure_init.c
+++ b/portable/IAR/ARM_CM33/secure/secure_init.c
@@ -93,7 +93,7 @@ secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )
          * permitted. CP11 should be programmed to the same value as CP10. */
         *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
 
-        /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
+        /* LSPENS = 0 ==> LSPEN is writable from non-secure state. This ensures
          * that we can enable/disable lazy stacking in port.c file. */
         *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK );
 
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
index 80410e82e..c940c304b 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
@@ -110,8 +110,8 @@
 /**
  * @brief Constants used during system call enter and exit.
  */
-#define portPSR_STACK_PADDING_MASK                ( 1UL << 9UL )
-#define portEXC_RETURN_STACK_FRAME_TYPE_MASK      ( 1UL << 4UL )
+#define portPSR_STACK_PADDING_MASK              ( 1UL << 9UL )
+#define portEXC_RETURN_STACK_FRAME_TYPE_MASK    ( 1UL << 4UL )
 /*-----------------------------------------------------------*/
 
 /**
@@ -133,81 +133,81 @@
 /**
  * @brief Offsets in the stack to the parameters when inside the SVC handler.
  */
-#define portOFFSET_TO_LR                    ( 5 )
-#define portOFFSET_TO_PC                    ( 6 )
-#define portOFFSET_TO_PSR                   ( 7 )
+#define portOFFSET_TO_LR     ( 5 )
+#define portOFFSET_TO_PC     ( 6 )
+#define portOFFSET_TO_PSR    ( 7 )
 /*-----------------------------------------------------------*/
 
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                      ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                      ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                       ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                      ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                      ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                     ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                     ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK  ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK               ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK               ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK               ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK               ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK               ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK               ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK               ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK               ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0              ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1              ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2              ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3              ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4              ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5              ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6              ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7              ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE            ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT      ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                      ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE             ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -216,11 +216,11 @@
 
 /* Extract last address of the MPU region as encoded in the
  * RLAR (Region Limit Address Register) value. */
-#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar )  \
+#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar ) \
     ( ( ( rlar ) & portMPU_RLAR_ADDRESS_MASK ) | ~portMPU_RLAR_ADDRESS_MASK )
 
 /* Does addr lies within [start, end] address range? */
-#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end )    \
+#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \
     ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) )
 
 /* Is the access request satisfied by the available permissions? */
@@ -422,54 +422,57 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the system call stack so that upon returning from
-     * SVC, the system call stack is used.
-     *
-     * It is used for the system calls with up to 4 parameters.
-     *
-     * @param pulTaskStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the system call stack so that upon returning from
+ * SVC, the system call stack is used.
+ *
+ * It is used for the system calls with up to 4 parameters.
+ *
+ * @param pulTaskStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallEnter( uint32_t * pulTaskStack,
+                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the system call stack so that upon returning from
-     * SVC, the system call stack is used.
-     *
-     * It is used for the system calls with 5 parameters.
-     *
-     * @param pulTaskStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the system call stack so that upon returning from
+ * SVC, the system call stack is used.
+ *
+ * It is used for the system calls with 5 parameters.
+ *
+ * @param pulTaskStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallEnter_1( uint32_t * pulTaskStack,
+                             uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the task stack so that upon returning from
-     * SVC, the task stack is used again.
-     *
-     * @param pulSystemCallStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the task stack so that upon returning from
+ * SVC, the task stack is used again.
+ *
+ * @param pulSystemCallStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallExit( uint32_t * pulSystemCallStack,
+                          uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Checks whether or not the calling task is privileged.
-     *
-     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
-     */
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
     BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
 
 #endif /* configENABLE_MPU == 1 */
@@ -1086,18 +1089,18 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             vRestoreContextOfFirstTask();
             break;
 
-        #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
-            case portSVC_RAISE_PRIVILEGE:
+            #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+                case portSVC_RAISE_PRIVILEGE:
 
-                /* Only raise the privilege, if the svc was raised from any of
-                 * the system calls. */
-                if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
-                    ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
-                {
-                    vRaisePrivilege();
-                }
-                break;
-        #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+                    /* Only raise the privilege, if the svc was raised from any of
+                     * the system calls. */
+                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+                    {
+                        vRaisePrivilege();
+                    }
+                    break;
+            #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
         default:
             /* Incorrect SVC call. */
@@ -1108,513 +1111,526 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulSystemCallStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallEnter( uint32_t * pulTaskStack,
+                           uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulSystemCallStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        /* This is not NULL only for the duration of the system call. */
-        configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+        #if defined( __ARMCC_VERSION )
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+
+            /* This is not NULL only for the duration of the system call. */
+            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the system call stack for the stack frame. */
+            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulSystemCallStack[ i ] = pulTaskStack[ i ];
+            }
+
+            /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
+             * restore it when we exit from the system call. */
+            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* Use the pulSystemCallStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+
+            /* Remember the location where we should copy the stack frame when we exit from
+             * the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+
+            /* Record if the hardware used padding to force the stack pointer
+             * to be double word aligned. */
+            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
+            {
+                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
             }
+
+            /* We ensure in pxPortInitialiseStack that the system call stack is
+             * double word aligned and therefore, there is no need of padding.
+             * Clear the bit[9] of stacked xPSR. */
+            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
+
+            /* Raise the privilege for the duration of the system call. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " bics r0, r1         \n" /* Clear nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the system call stack for the stack frame. */
-        pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulSystemCallStack[ i ] = pulTaskStack[ i ];
-        }
-
-        /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
-         * restore it when we exit from the system call. */
-        pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-        __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* Use the pulSystemCallStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-
-        /* Remember the location where we should copy the stack frame when we exit from
-         * the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-        /* Record if the hardware used padding to force the stack pointer
-         * to be double word aligned. */
-        if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-        {
-            pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-        }
-        else
-        {
-            pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-        }
-
-        /* We ensure in pxPortInitialiseStack that the system call stack is
-         * double word aligned and therefore, there is no need of padding.
-         * Clear the bit[9] of stacked xPSR. */
-        pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-        /* Raise the privilege for the duration of the system call. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " bics r0, r1         \n" /* Clear nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulSystemCallStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallEnter_1( uint32_t * pulTaskStack,
+                             uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulSystemCallStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        /* This is not NULL only for the duration of the system call. */
-        configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+        #if defined( __ARMCC_VERSION )
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+
+            /* This is not NULL only for the duration of the system call. */
+            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the system call stack for the stack frame and
+             * the parameter passed on the stack. We only need to copy one
+             * parameter but we still reserve 2 spaces to keep the stack
+             * double word aligned. */
+            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulSystemCallStack[ i ] = pulTaskStack[ i ];
+            }
+
+            /* Copy the parameter which is passed the stack. */
+            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
+            {
+                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
+
+                /* Record if the hardware used padding to force the stack pointer
+                 * to be double word aligned. */
+                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
+
+                /* Record if the hardware used padding to force the stack pointer
+                 * to be double word aligned. */
+                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
             }
+
+            /* Store the value of the LR and PSPLIM registers before the SVC was raised.
+             * We need to restore it when we exit from the system call. */
+            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* Use the pulSystemCallStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+
+            /* Remember the location where we should copy the stack frame when we exit from
+             * the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+
+            /* We ensure in pxPortInitialiseStack that the system call stack is
+             * double word aligned and therefore, there is no need of padding.
+             * Clear the bit[9] of stacked xPSR. */
+            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
+
+            /* Raise the privilege for the duration of the system call. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " bics r0, r1         \n" /* Clear nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the system call stack for the stack frame and
-         * the parameter passed on the stack. We only need to copy one
-         * parameter but we still reserve 2 spaces to keep the stack
-         * double word aligned. */
-        pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulSystemCallStack[ i ] = pulTaskStack[ i ];
-        }
-
-        /* Copy the parameter which is passed the stack. */
-        if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-        {
-            pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
-            /* Record if the hardware used padding to force the stack pointer
-             * to be double word aligned. */
-            pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-        }
-        else
-        {
-            pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
-            /* Record if the hardware used padding to force the stack pointer
-             * to be double word aligned. */
-            pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-        }
-
-        /* Store the value of the LR and PSPLIM registers before the SVC was raised.
-         * We need to restore it when we exit from the system call. */
-        pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-        __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* Use the pulSystemCallStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-
-        /* Remember the location where we should copy the stack frame when we exit from
-         * the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-        /* We ensure in pxPortInitialiseStack that the system call stack is
-         * double word aligned and therefore, there is no need of padding.
-         * Clear the bit[9] of stacked xPSR. */
-        pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-        /* Raise the privilege for the duration of the system call. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " bics r0, r1         \n" /* Clear nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulTaskStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallExit( uint32_t * pulSystemCallStack,
+                          uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulTaskStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+        #if defined( __ARMCC_VERSION )
+
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the task stack for the stack frame. */
+            pulTaskStack = pulTaskStack - ulStackFrameSize;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulTaskStack[ i ] = pulSystemCallStack[ i ];
+            }
+
+            /* Use the pulTaskStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
+
+            /* Restore the LR and PSPLIM to what they were at the time of
+             * system call entry. */
+            pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* If the hardware used padding to force the stack pointer
+             * to be double word aligned, set the stacked xPSR bit[9],
+             * otherwise clear it. */
+            if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG )
+            {
+                pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
             }
+
+            /* This is not NULL only for the duration of the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
+
+            /* Drop the privilege before returning to the thread mode. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " orrs r0, r1         \n" /* Set nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the task stack for the stack frame. */
-        pulTaskStack = pulTaskStack - ulStackFrameSize;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulTaskStack[ i ] = pulSystemCallStack[ i ];
-        }
-
-        /* Use the pulTaskStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
-
-        /* Restore the LR and PSPLIM to what they were at the time of
-         * system call entry. */
-        pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* If the hardware used padding to force the stack pointer
-         * to be double word aligned, set the stacked xPSR bit[9],
-         * otherwise clear it. */
-        if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG )
-        {
-            pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK;
-        }
-        else
-        {
-            pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-        }
-
-        /* This is not NULL only for the duration of the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
-
-        /* Drop the privilege before returning to the thread mode. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " orrs r0, r1         \n" /* Set nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */
-{
-    BaseType_t xTaskIsPrivileged = pdFALSE;
-    const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
-
-    if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+    BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */
     {
-        xTaskIsPrivileged = pdTRUE;
-    }
+        BaseType_t xTaskIsPrivileged = pdFALSE;
+        const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
 
-    return xTaskIsPrivileged;
-}
+        if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+        {
+            xTaskIsPrivileged = pdTRUE;
+        }
+
+        return xTaskIsPrivileged;
+    }
 
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
-#if( configENABLE_MPU == 1 )
+#if ( configENABLE_MPU == 1 )
 
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     StackType_t * pxEndOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters,
-                                     BaseType_t xRunPrivileged,
-                                     xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
-{
-    uint32_t ulIndex = 0;
-
-    xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
-    ulIndex++;
-
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
-    ulIndex++;
-
-    #if ( configENABLE_TRUSTZONE == 1 )
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters,
+                                         BaseType_t xRunPrivileged,
+                                         xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
     {
-        xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT;  /* xSecureContext. */
+        uint32_t ulIndex = 0;
+
+        xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
         ulIndex++;
-    }
-    #endif /* configENABLE_TRUSTZONE */
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
-    ulIndex++;
-    if( xRunPrivileged == pdTRUE )
-    {
-        xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */
         ulIndex++;
-    }
-    else
-    {
-        xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */
         ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
+        ulIndex++;
+
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters;            /* r0. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x01010101;                           /* r1. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x02020202;                           /* r2. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x03030303;                           /* r3. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x12121212;                           /* r12. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode;                  /* PC. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR;                     /* xPSR. */
+        ulIndex++;
+
+        #if ( configENABLE_TRUSTZONE == 1 )
+        {
+            xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT; /* xSecureContext. */
+            ulIndex++;
+        }
+        #endif /* configENABLE_TRUSTZONE */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
+        ulIndex++;
+
+        if( xRunPrivileged == pdTRUE )
+        {
+            xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
+            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+            ulIndex++;
+        }
+        else
+        {
+            xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
+            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+            ulIndex++;
+        }
+
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
+        ulIndex++;
+
+        #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+        {
+            /* Ensure that the system call stack is double word aligned. */
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] );
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) &
+                                                                                     ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
+
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] );
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) +
+                                                                                            ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) &
+                                                                                          ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
+
+            /* This is not NULL only for the duration of a system call. */
+            xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL;
+        }
+        #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
+
+        return &( xMPUSettings->ulContext[ ulIndex ] );
     }
-    xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
-    ulIndex++;
-
-    #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
-    {
-        /* Ensure that the system call stack is double word aligned. */
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] );
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) &
-                                                                                 ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
-
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] );
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) +
-                                                                                        ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) &
-                                                                                      ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
-
-        /* This is not NULL only for the duration of a system call. */
-        xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL;
-    }
-    #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
-
-    return &( xMPUSettings->ulContext[ ulIndex ] );
-}
 
 #else /* configENABLE_MPU */
 
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     StackType_t * pxEndOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters ) /* PRIVILEGED_FUNCTION */
-{
-    /* Simulate the stack frame as it would be created by a context switch
-     * interrupt. */
-    #if ( portPRELOAD_REGISTERS == 0 )
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters ) /* PRIVILEGED_FUNCTION */
     {
-        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-        pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
-        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-        pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
-        *pxTopOfStack = portINITIAL_EXC_RETURN;
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
-
-        #if ( configENABLE_TRUSTZONE == 1 )
+        /* Simulate the stack frame as it would be created by a context switch
+         * interrupt. */
+        #if ( portPRELOAD_REGISTERS == 0 )
         {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
-        }
-        #endif /* configENABLE_TRUSTZONE */
-    }
-    #else /* portPRELOAD_REGISTERS */
-    {
-        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
-        pxTopOfStack--;
-        *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
+            pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
+            *pxTopOfStack = portINITIAL_EXC_RETURN;
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+            #if ( configENABLE_TRUSTZONE == 1 )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+            }
+            #endif /* configENABLE_TRUSTZONE */
+        }
+        #else /* portPRELOAD_REGISTERS */
         {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
-        }
-        #endif /* configENABLE_TRUSTZONE */
-    }
-    #endif /* portPRELOAD_REGISTERS */
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
+            pxTopOfStack--;
+            *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack;            /* Slot used to hold this task's PSPLIM value. */
 
-    return pxTopOfStack;
-}
+            #if ( configENABLE_TRUSTZONE == 1 )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+            }
+            #endif /* configENABLE_TRUSTZONE */
+        }
+        #endif /* portPRELOAD_REGISTERS */
+
+        return pxTopOfStack;
+    }
 
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h b/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h
index 445f0765a..64d39e3b9 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h
@@ -48,16 +48,16 @@
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME                       "Cortex-M33"
-#define portHAS_ARMV8M_MAIN_EXTENSION       1
-#define portDONT_DISCARD                    __root
+#define portARCH_NAME                    "Cortex-M33"
+#define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
 /* ARMv8-M common port configurations. */
 #include "portmacrocommon.h"
 /*-----------------------------------------------------------*/
 
-#if( configTOTAL_MPU_REGIONS == 16 )
+#if ( configTOTAL_MPU_REGIONS == 16 )
     #error 16 MPU regions are not yet supported for this port.
 #endif
 /*-----------------------------------------------------------*/
@@ -65,8 +65,8 @@
 /**
  * @brief Critical section management.
  */
-#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()
-#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )
+#define portDISABLE_INTERRUPTS()    ulSetInterruptMask()
+#define portENABLE_INTERRUPTS()     vClearInterruptMask( 0 )
 /*-----------------------------------------------------------*/
 
 /* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h
index e5ffdb48b..62e462a27 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h
@@ -81,8 +81,8 @@ typedef unsigned long    UBaseType_t;
     typedef uint32_t     TickType_t;
     #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-     * not need to be guarded with a critical section. */
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
     #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -117,7 +117,7 @@ extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGE
 extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
 
 #if ( configENABLE_TRUSTZONE == 1 )
-    extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize );     /* __attribute__ (( naked )) */
+    extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
     extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
 #endif /* configENABLE_TRUSTZONE */
 
@@ -188,13 +188,13 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Settings to define an MPU region.
-     */
+/**
+ * @brief Settings to define an MPU region.
+ */
     typedef struct MPURegionSettings
     {
-        uint32_t ulRBAR;     /**< RBAR for the region. */
-        uint32_t ulRLAR;     /**< RLAR for the region. */
+        uint32_t ulRBAR; /**< RBAR for the region. */
+        uint32_t ulRLAR; /**< RLAR for the region. */
     } MPURegionSettings_t;
 
     #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
@@ -203,9 +203,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-        /**
-         * @brief System call stack.
-         */
+/**
+ * @brief System call stack.
+ */
         typedef struct SYSTEM_CALL_STACK_INFO
         {
             uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ];
@@ -218,74 +218,74 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
-    /**
-     * @brief MPU settings as stored in the TCB.
-     */
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
     #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
 
-        #if( configENABLE_TRUSTZONE == 1 )
+        #if ( configENABLE_TRUSTZONE == 1 )
 
-            /*
-             * +-----------+---------------+----------+-----------------+------------------------------+-----+
-             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
-             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
-             * +-----------+---------------+----------+-----------------+------------------------------+-----+
-             *
-             * <-----------><--------------><---------><----------------><-----------------------------><---->
-             *      16             16            8               8                     5                   1
-             */
-            #define MAX_CONTEXT_SIZE 54
+/*
+ * +-----------+---------------+----------+-----------------+------------------------------+-----+
+ * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+ * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+ * +-----------+---------------+----------+-----------------+------------------------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><-----------------------------><---->
+ *      16             16            8               8                     5                   1
+ */
+            #define MAX_CONTEXT_SIZE    54
 
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-            /*
-             * +-----------+---------------+----------+-----------------+----------------------+-----+
-             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
-             * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
-             * +-----------+---------------+----------+-----------------+----------------------+-----+
-             *
-             * <-----------><--------------><---------><----------------><---------------------><---->
-             *      16             16            8               8                  4              1
-             */
-            #define MAX_CONTEXT_SIZE 53
+/*
+ * +-----------+---------------+----------+-----------------+----------------------+-----+
+ * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+ * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
+ * +-----------+---------------+----------+-----------------+----------------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><---------------------><---->
+ *      16             16            8               8                  4              1
+ */
+            #define MAX_CONTEXT_SIZE    53
 
         #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
 
     #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-        #if( configENABLE_TRUSTZONE == 1 )
+        #if ( configENABLE_TRUSTZONE == 1 )
 
-            /*
-             * +----------+-----------------+------------------------------+-----+
-             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
-             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
-             * +----------+-----------------+------------------------------+-----+
-             *
-             * <---------><----------------><------------------------------><---->
-             *     8               8                      5                   1
-             */
-            #define MAX_CONTEXT_SIZE 22
+/*
+ * +----------+-----------------+------------------------------+-----+
+ * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+ * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+ * +----------+-----------------+------------------------------+-----+
+ *
+ * <---------><----------------><------------------------------><---->
+ *     8               8                      5                   1
+ */
+            #define MAX_CONTEXT_SIZE    22
 
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-            /*
-             * +----------+-----------------+----------------------+-----+
-             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
-             * |          | PC, xPSR        | EXC_RETURN           |     |
-             * +----------+-----------------+----------------------+-----+
-             *
-             * <---------><----------------><----------------------><---->
-             *     8               8                  4              1
-             */
-            #define MAX_CONTEXT_SIZE 21
+/*
+ * +----------+-----------------+----------------------+-----+
+ * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+ * |          | PC, xPSR        | EXC_RETURN           |     |
+ * +----------+-----------------+----------------------+-----+
+ *
+ * <---------><----------------><----------------------><---->
+ *     8               8                  4              1
+ */
+            #define MAX_CONTEXT_SIZE    21
 
         #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
 
     #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-    /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
-    #define portSTACK_FRAME_HAS_PADDING_FLAG     ( 1UL << 0UL )
-    #define portTASK_IS_PRIVILEGED_FLAG          ( 1UL << 1UL )
+/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
+    #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
+    #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
     typedef struct MPU_SETTINGS
     {
@@ -364,49 +364,49 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-    /**
-     * @brief Allocate a secure context for the task.
-     *
-     * Tasks are not created with a secure context. Any task that is going to call
-     * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
-     * secure context before it calls any secure function.
-     *
-     * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
-     */
+/**
+ * @brief Allocate a secure context for the task.
+ *
+ * Tasks are not created with a secure context. Any task that is going to call
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+ * secure context before it calls any secure function.
+ *
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+ */
     #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
 
-    /**
-     * @brief Called when a task is deleted to delete the task's secure context,
-     * if it has one.
-     *
-     * @param[in] pxTCB The TCB of the task being deleted.
-     */
+/**
+ * @brief Called when a task is deleted to delete the task's secure context,
+ * if it has one.
+ *
+ * @param[in] pxTCB The TCB of the task being deleted.
+ */
     #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
 #endif /* configENABLE_TRUSTZONE */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Checks whether or not the processor is privileged.
-     *
-     * @return 1 if the processor is already privileged, 0 otherwise.
-     */
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
     #define portIS_PRIVILEGED()      xIsPrivileged()
 
-    /**
-     * @brief Raise an SVC request to raise privilege.
-     *
-     * The SVC handler checks that the SVC was raised from a system call and only
-     * then it raises the privilege. If this is called from any other place,
-     * the privilege is not raised.
-     */
+/**
+ * @brief Raise an SVC request to raise privilege.
+ *
+ * The SVC handler checks that the SVC was raised from a system call and only
+ * then it raises the privilege. If this is called from any other place,
+ * the privilege is not raised.
+ */
     #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
 
-    /**
-     * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
-     * register.
-     */
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
     #define portRESET_PRIVILEGE()    vResetPrivilege()
 #else
     #define portIS_PRIVILEGED()
@@ -419,12 +419,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     extern BaseType_t xPortIsTaskPrivileged( void );
 
-    /**
-     * @brief Checks whether or not the calling task is privileged.
-     *
-     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
-     */
-    #define portIS_TASK_PRIVILEGED()      xPortIsTaskPrivileged()
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
+    #define portIS_TASK_PRIVILEGED()    xPortIsTaskPrivileged()
 
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
@@ -439,9 +439,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * based on whether or not Mainline extension is implemented. */
 #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
     #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
-        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
     #else
-        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    0
     #endif
 #endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
 
@@ -450,9 +450,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  */
 #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
 
-    /**
-     * @brief Count the number of leading zeros in a 32-bit value.
-     */
+/**
+ * @brief Count the number of leading zeros in a 32-bit value.
+ */
     static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
     {
         uint32_t ulReturn;
@@ -462,7 +462,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         return ulReturn;
     }
 
-    /* Check the configuration. */
+/* Check the configuration. */
     #if ( configMAX_PRIORITIES > 32 )
         #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
     #endif
@@ -471,16 +471,16 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection.  Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
     #endif
 
-    /**
-     * @brief Store/clear the ready priorities in a bit map.
-     */
-    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+/**
+ * @brief Store/clear the ready priorities in a bit map.
+ */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )      ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )       ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 
-    /**
-     * @brief Get the priority of the highest-priority task that is ready to execute.
-     */
-    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )   uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+/**
+ * @brief Get the priority of the highest-priority task that is ready to execute.
+ */
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
 
 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM35P/non_secure/port.c b/portable/IAR/ARM_CM35P/non_secure/port.c
index 80410e82e..c940c304b 100644
--- a/portable/IAR/ARM_CM35P/non_secure/port.c
+++ b/portable/IAR/ARM_CM35P/non_secure/port.c
@@ -110,8 +110,8 @@
 /**
  * @brief Constants used during system call enter and exit.
  */
-#define portPSR_STACK_PADDING_MASK                ( 1UL << 9UL )
-#define portEXC_RETURN_STACK_FRAME_TYPE_MASK      ( 1UL << 4UL )
+#define portPSR_STACK_PADDING_MASK              ( 1UL << 9UL )
+#define portEXC_RETURN_STACK_FRAME_TYPE_MASK    ( 1UL << 4UL )
 /*-----------------------------------------------------------*/
 
 /**
@@ -133,81 +133,81 @@
 /**
  * @brief Offsets in the stack to the parameters when inside the SVC handler.
  */
-#define portOFFSET_TO_LR                    ( 5 )
-#define portOFFSET_TO_PC                    ( 6 )
-#define portOFFSET_TO_PSR                   ( 7 )
+#define portOFFSET_TO_LR     ( 5 )
+#define portOFFSET_TO_PC     ( 6 )
+#define portOFFSET_TO_PSR    ( 7 )
 /*-----------------------------------------------------------*/
 
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                      ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                      ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                       ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                      ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                      ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                     ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                     ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK  ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK               ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK               ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK               ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK               ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK               ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK               ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK               ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK               ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0              ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1              ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2              ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3              ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4              ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5              ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6              ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7              ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE            ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT      ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                      ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE             ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -216,11 +216,11 @@
 
 /* Extract last address of the MPU region as encoded in the
  * RLAR (Region Limit Address Register) value. */
-#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar )  \
+#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar ) \
     ( ( ( rlar ) & portMPU_RLAR_ADDRESS_MASK ) | ~portMPU_RLAR_ADDRESS_MASK )
 
 /* Does addr lies within [start, end] address range? */
-#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end )    \
+#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \
     ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) )
 
 /* Is the access request satisfied by the available permissions? */
@@ -422,54 +422,57 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the system call stack so that upon returning from
-     * SVC, the system call stack is used.
-     *
-     * It is used for the system calls with up to 4 parameters.
-     *
-     * @param pulTaskStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the system call stack so that upon returning from
+ * SVC, the system call stack is used.
+ *
+ * It is used for the system calls with up to 4 parameters.
+ *
+ * @param pulTaskStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallEnter( uint32_t * pulTaskStack,
+                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the system call stack so that upon returning from
-     * SVC, the system call stack is used.
-     *
-     * It is used for the system calls with 5 parameters.
-     *
-     * @param pulTaskStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the system call stack so that upon returning from
+ * SVC, the system call stack is used.
+ *
+ * It is used for the system calls with 5 parameters.
+ *
+ * @param pulTaskStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallEnter_1( uint32_t * pulTaskStack,
+                             uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the task stack so that upon returning from
-     * SVC, the task stack is used again.
-     *
-     * @param pulSystemCallStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the task stack so that upon returning from
+ * SVC, the task stack is used again.
+ *
+ * @param pulSystemCallStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallExit( uint32_t * pulSystemCallStack,
+                          uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Checks whether or not the calling task is privileged.
-     *
-     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
-     */
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
     BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
 
 #endif /* configENABLE_MPU == 1 */
@@ -1086,18 +1089,18 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             vRestoreContextOfFirstTask();
             break;
 
-        #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
-            case portSVC_RAISE_PRIVILEGE:
+            #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+                case portSVC_RAISE_PRIVILEGE:
 
-                /* Only raise the privilege, if the svc was raised from any of
-                 * the system calls. */
-                if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
-                    ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
-                {
-                    vRaisePrivilege();
-                }
-                break;
-        #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+                    /* Only raise the privilege, if the svc was raised from any of
+                     * the system calls. */
+                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+                    {
+                        vRaisePrivilege();
+                    }
+                    break;
+            #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
         default:
             /* Incorrect SVC call. */
@@ -1108,513 +1111,526 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulSystemCallStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallEnter( uint32_t * pulTaskStack,
+                           uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulSystemCallStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        /* This is not NULL only for the duration of the system call. */
-        configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+        #if defined( __ARMCC_VERSION )
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+
+            /* This is not NULL only for the duration of the system call. */
+            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the system call stack for the stack frame. */
+            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulSystemCallStack[ i ] = pulTaskStack[ i ];
+            }
+
+            /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
+             * restore it when we exit from the system call. */
+            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* Use the pulSystemCallStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+
+            /* Remember the location where we should copy the stack frame when we exit from
+             * the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+
+            /* Record if the hardware used padding to force the stack pointer
+             * to be double word aligned. */
+            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
+            {
+                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
             }
+
+            /* We ensure in pxPortInitialiseStack that the system call stack is
+             * double word aligned and therefore, there is no need of padding.
+             * Clear the bit[9] of stacked xPSR. */
+            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
+
+            /* Raise the privilege for the duration of the system call. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " bics r0, r1         \n" /* Clear nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the system call stack for the stack frame. */
-        pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulSystemCallStack[ i ] = pulTaskStack[ i ];
-        }
-
-        /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
-         * restore it when we exit from the system call. */
-        pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-        __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* Use the pulSystemCallStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-
-        /* Remember the location where we should copy the stack frame when we exit from
-         * the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-        /* Record if the hardware used padding to force the stack pointer
-         * to be double word aligned. */
-        if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-        {
-            pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-        }
-        else
-        {
-            pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-        }
-
-        /* We ensure in pxPortInitialiseStack that the system call stack is
-         * double word aligned and therefore, there is no need of padding.
-         * Clear the bit[9] of stacked xPSR. */
-        pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-        /* Raise the privilege for the duration of the system call. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " bics r0, r1         \n" /* Clear nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulSystemCallStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallEnter_1( uint32_t * pulTaskStack,
+                             uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulSystemCallStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        /* This is not NULL only for the duration of the system call. */
-        configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+        #if defined( __ARMCC_VERSION )
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+
+            /* This is not NULL only for the duration of the system call. */
+            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the system call stack for the stack frame and
+             * the parameter passed on the stack. We only need to copy one
+             * parameter but we still reserve 2 spaces to keep the stack
+             * double word aligned. */
+            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulSystemCallStack[ i ] = pulTaskStack[ i ];
+            }
+
+            /* Copy the parameter which is passed the stack. */
+            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
+            {
+                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
+
+                /* Record if the hardware used padding to force the stack pointer
+                 * to be double word aligned. */
+                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
+
+                /* Record if the hardware used padding to force the stack pointer
+                 * to be double word aligned. */
+                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
             }
+
+            /* Store the value of the LR and PSPLIM registers before the SVC was raised.
+             * We need to restore it when we exit from the system call. */
+            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* Use the pulSystemCallStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+
+            /* Remember the location where we should copy the stack frame when we exit from
+             * the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+
+            /* We ensure in pxPortInitialiseStack that the system call stack is
+             * double word aligned and therefore, there is no need of padding.
+             * Clear the bit[9] of stacked xPSR. */
+            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
+
+            /* Raise the privilege for the duration of the system call. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " bics r0, r1         \n" /* Clear nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the system call stack for the stack frame and
-         * the parameter passed on the stack. We only need to copy one
-         * parameter but we still reserve 2 spaces to keep the stack
-         * double word aligned. */
-        pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulSystemCallStack[ i ] = pulTaskStack[ i ];
-        }
-
-        /* Copy the parameter which is passed the stack. */
-        if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-        {
-            pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
-            /* Record if the hardware used padding to force the stack pointer
-             * to be double word aligned. */
-            pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-        }
-        else
-        {
-            pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
-            /* Record if the hardware used padding to force the stack pointer
-             * to be double word aligned. */
-            pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-        }
-
-        /* Store the value of the LR and PSPLIM registers before the SVC was raised.
-         * We need to restore it when we exit from the system call. */
-        pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-        __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* Use the pulSystemCallStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-
-        /* Remember the location where we should copy the stack frame when we exit from
-         * the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-        /* We ensure in pxPortInitialiseStack that the system call stack is
-         * double word aligned and therefore, there is no need of padding.
-         * Clear the bit[9] of stacked xPSR. */
-        pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-        /* Raise the privilege for the duration of the system call. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " bics r0, r1         \n" /* Clear nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulTaskStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallExit( uint32_t * pulSystemCallStack,
+                          uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulTaskStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+        #if defined( __ARMCC_VERSION )
+
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the task stack for the stack frame. */
+            pulTaskStack = pulTaskStack - ulStackFrameSize;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulTaskStack[ i ] = pulSystemCallStack[ i ];
+            }
+
+            /* Use the pulTaskStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
+
+            /* Restore the LR and PSPLIM to what they were at the time of
+             * system call entry. */
+            pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* If the hardware used padding to force the stack pointer
+             * to be double word aligned, set the stacked xPSR bit[9],
+             * otherwise clear it. */
+            if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG )
+            {
+                pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
             }
+
+            /* This is not NULL only for the duration of the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
+
+            /* Drop the privilege before returning to the thread mode. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " orrs r0, r1         \n" /* Set nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the task stack for the stack frame. */
-        pulTaskStack = pulTaskStack - ulStackFrameSize;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulTaskStack[ i ] = pulSystemCallStack[ i ];
-        }
-
-        /* Use the pulTaskStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
-
-        /* Restore the LR and PSPLIM to what they were at the time of
-         * system call entry. */
-        pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* If the hardware used padding to force the stack pointer
-         * to be double word aligned, set the stacked xPSR bit[9],
-         * otherwise clear it. */
-        if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG )
-        {
-            pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK;
-        }
-        else
-        {
-            pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-        }
-
-        /* This is not NULL only for the duration of the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
-
-        /* Drop the privilege before returning to the thread mode. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " orrs r0, r1         \n" /* Set nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */
-{
-    BaseType_t xTaskIsPrivileged = pdFALSE;
-    const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
-
-    if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+    BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */
     {
-        xTaskIsPrivileged = pdTRUE;
-    }
+        BaseType_t xTaskIsPrivileged = pdFALSE;
+        const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
 
-    return xTaskIsPrivileged;
-}
+        if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+        {
+            xTaskIsPrivileged = pdTRUE;
+        }
+
+        return xTaskIsPrivileged;
+    }
 
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
-#if( configENABLE_MPU == 1 )
+#if ( configENABLE_MPU == 1 )
 
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     StackType_t * pxEndOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters,
-                                     BaseType_t xRunPrivileged,
-                                     xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
-{
-    uint32_t ulIndex = 0;
-
-    xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
-    ulIndex++;
-
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
-    ulIndex++;
-
-    #if ( configENABLE_TRUSTZONE == 1 )
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters,
+                                         BaseType_t xRunPrivileged,
+                                         xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
     {
-        xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT;  /* xSecureContext. */
+        uint32_t ulIndex = 0;
+
+        xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
         ulIndex++;
-    }
-    #endif /* configENABLE_TRUSTZONE */
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
-    ulIndex++;
-    if( xRunPrivileged == pdTRUE )
-    {
-        xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */
         ulIndex++;
-    }
-    else
-    {
-        xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */
         ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
+        ulIndex++;
+
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters;            /* r0. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x01010101;                           /* r1. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x02020202;                           /* r2. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x03030303;                           /* r3. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x12121212;                           /* r12. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode;                  /* PC. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR;                     /* xPSR. */
+        ulIndex++;
+
+        #if ( configENABLE_TRUSTZONE == 1 )
+        {
+            xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT; /* xSecureContext. */
+            ulIndex++;
+        }
+        #endif /* configENABLE_TRUSTZONE */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
+        ulIndex++;
+
+        if( xRunPrivileged == pdTRUE )
+        {
+            xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
+            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+            ulIndex++;
+        }
+        else
+        {
+            xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
+            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+            ulIndex++;
+        }
+
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
+        ulIndex++;
+
+        #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+        {
+            /* Ensure that the system call stack is double word aligned. */
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] );
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) &
+                                                                                     ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
+
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] );
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) +
+                                                                                            ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) &
+                                                                                          ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
+
+            /* This is not NULL only for the duration of a system call. */
+            xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL;
+        }
+        #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
+
+        return &( xMPUSettings->ulContext[ ulIndex ] );
     }
-    xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
-    ulIndex++;
-
-    #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
-    {
-        /* Ensure that the system call stack is double word aligned. */
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] );
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) &
-                                                                                 ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
-
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] );
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) +
-                                                                                        ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) &
-                                                                                      ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
-
-        /* This is not NULL only for the duration of a system call. */
-        xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL;
-    }
-    #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
-
-    return &( xMPUSettings->ulContext[ ulIndex ] );
-}
 
 #else /* configENABLE_MPU */
 
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     StackType_t * pxEndOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters ) /* PRIVILEGED_FUNCTION */
-{
-    /* Simulate the stack frame as it would be created by a context switch
-     * interrupt. */
-    #if ( portPRELOAD_REGISTERS == 0 )
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters ) /* PRIVILEGED_FUNCTION */
     {
-        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-        pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
-        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-        pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
-        *pxTopOfStack = portINITIAL_EXC_RETURN;
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
-
-        #if ( configENABLE_TRUSTZONE == 1 )
+        /* Simulate the stack frame as it would be created by a context switch
+         * interrupt. */
+        #if ( portPRELOAD_REGISTERS == 0 )
         {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
-        }
-        #endif /* configENABLE_TRUSTZONE */
-    }
-    #else /* portPRELOAD_REGISTERS */
-    {
-        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
-        pxTopOfStack--;
-        *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
+            pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
+            *pxTopOfStack = portINITIAL_EXC_RETURN;
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+            #if ( configENABLE_TRUSTZONE == 1 )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+            }
+            #endif /* configENABLE_TRUSTZONE */
+        }
+        #else /* portPRELOAD_REGISTERS */
         {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
-        }
-        #endif /* configENABLE_TRUSTZONE */
-    }
-    #endif /* portPRELOAD_REGISTERS */
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
+            pxTopOfStack--;
+            *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack;            /* Slot used to hold this task's PSPLIM value. */
 
-    return pxTopOfStack;
-}
+            #if ( configENABLE_TRUSTZONE == 1 )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+            }
+            #endif /* configENABLE_TRUSTZONE */
+        }
+        #endif /* portPRELOAD_REGISTERS */
+
+        return pxTopOfStack;
+    }
 
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM35P/non_secure/portmacro.h b/portable/IAR/ARM_CM35P/non_secure/portmacro.h
index 5669c1f60..82bfaeb79 100644
--- a/portable/IAR/ARM_CM35P/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM35P/non_secure/portmacro.h
@@ -48,16 +48,16 @@
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME                       "Cortex-M35P"
-#define portHAS_ARMV8M_MAIN_EXTENSION       1
-#define portDONT_DISCARD                    __root
+#define portARCH_NAME                    "Cortex-M35P"
+#define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
 /* ARMv8-M common port configurations. */
 #include "portmacrocommon.h"
 /*-----------------------------------------------------------*/
 
-#if( configTOTAL_MPU_REGIONS == 16 )
+#if ( configTOTAL_MPU_REGIONS == 16 )
     #error 16 MPU regions are not yet supported for this port.
 #endif
 /*-----------------------------------------------------------*/
@@ -65,8 +65,8 @@
 /**
  * @brief Critical section management.
  */
-#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()
-#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )
+#define portDISABLE_INTERRUPTS()    ulSetInterruptMask()
+#define portENABLE_INTERRUPTS()     vClearInterruptMask( 0 )
 /*-----------------------------------------------------------*/
 
 /* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
diff --git a/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h
index e5ffdb48b..62e462a27 100644
--- a/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h
@@ -81,8 +81,8 @@ typedef unsigned long    UBaseType_t;
     typedef uint32_t     TickType_t;
     #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-     * not need to be guarded with a critical section. */
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
     #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -117,7 +117,7 @@ extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGE
 extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
 
 #if ( configENABLE_TRUSTZONE == 1 )
-    extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize );     /* __attribute__ (( naked )) */
+    extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
     extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
 #endif /* configENABLE_TRUSTZONE */
 
@@ -188,13 +188,13 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Settings to define an MPU region.
-     */
+/**
+ * @brief Settings to define an MPU region.
+ */
     typedef struct MPURegionSettings
     {
-        uint32_t ulRBAR;     /**< RBAR for the region. */
-        uint32_t ulRLAR;     /**< RLAR for the region. */
+        uint32_t ulRBAR; /**< RBAR for the region. */
+        uint32_t ulRLAR; /**< RLAR for the region. */
     } MPURegionSettings_t;
 
     #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
@@ -203,9 +203,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-        /**
-         * @brief System call stack.
-         */
+/**
+ * @brief System call stack.
+ */
         typedef struct SYSTEM_CALL_STACK_INFO
         {
             uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ];
@@ -218,74 +218,74 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
-    /**
-     * @brief MPU settings as stored in the TCB.
-     */
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
     #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
 
-        #if( configENABLE_TRUSTZONE == 1 )
+        #if ( configENABLE_TRUSTZONE == 1 )
 
-            /*
-             * +-----------+---------------+----------+-----------------+------------------------------+-----+
-             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
-             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
-             * +-----------+---------------+----------+-----------------+------------------------------+-----+
-             *
-             * <-----------><--------------><---------><----------------><-----------------------------><---->
-             *      16             16            8               8                     5                   1
-             */
-            #define MAX_CONTEXT_SIZE 54
+/*
+ * +-----------+---------------+----------+-----------------+------------------------------+-----+
+ * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+ * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+ * +-----------+---------------+----------+-----------------+------------------------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><-----------------------------><---->
+ *      16             16            8               8                     5                   1
+ */
+            #define MAX_CONTEXT_SIZE    54
 
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-            /*
-             * +-----------+---------------+----------+-----------------+----------------------+-----+
-             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
-             * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
-             * +-----------+---------------+----------+-----------------+----------------------+-----+
-             *
-             * <-----------><--------------><---------><----------------><---------------------><---->
-             *      16             16            8               8                  4              1
-             */
-            #define MAX_CONTEXT_SIZE 53
+/*
+ * +-----------+---------------+----------+-----------------+----------------------+-----+
+ * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+ * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
+ * +-----------+---------------+----------+-----------------+----------------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><---------------------><---->
+ *      16             16            8               8                  4              1
+ */
+            #define MAX_CONTEXT_SIZE    53
 
         #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
 
     #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-        #if( configENABLE_TRUSTZONE == 1 )
+        #if ( configENABLE_TRUSTZONE == 1 )
 
-            /*
-             * +----------+-----------------+------------------------------+-----+
-             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
-             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
-             * +----------+-----------------+------------------------------+-----+
-             *
-             * <---------><----------------><------------------------------><---->
-             *     8               8                      5                   1
-             */
-            #define MAX_CONTEXT_SIZE 22
+/*
+ * +----------+-----------------+------------------------------+-----+
+ * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+ * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+ * +----------+-----------------+------------------------------+-----+
+ *
+ * <---------><----------------><------------------------------><---->
+ *     8               8                      5                   1
+ */
+            #define MAX_CONTEXT_SIZE    22
 
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-            /*
-             * +----------+-----------------+----------------------+-----+
-             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
-             * |          | PC, xPSR        | EXC_RETURN           |     |
-             * +----------+-----------------+----------------------+-----+
-             *
-             * <---------><----------------><----------------------><---->
-             *     8               8                  4              1
-             */
-            #define MAX_CONTEXT_SIZE 21
+/*
+ * +----------+-----------------+----------------------+-----+
+ * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+ * |          | PC, xPSR        | EXC_RETURN           |     |
+ * +----------+-----------------+----------------------+-----+
+ *
+ * <---------><----------------><----------------------><---->
+ *     8               8                  4              1
+ */
+            #define MAX_CONTEXT_SIZE    21
 
         #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
 
     #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-    /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
-    #define portSTACK_FRAME_HAS_PADDING_FLAG     ( 1UL << 0UL )
-    #define portTASK_IS_PRIVILEGED_FLAG          ( 1UL << 1UL )
+/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
+    #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
+    #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
     typedef struct MPU_SETTINGS
     {
@@ -364,49 +364,49 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-    /**
-     * @brief Allocate a secure context for the task.
-     *
-     * Tasks are not created with a secure context. Any task that is going to call
-     * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
-     * secure context before it calls any secure function.
-     *
-     * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
-     */
+/**
+ * @brief Allocate a secure context for the task.
+ *
+ * Tasks are not created with a secure context. Any task that is going to call
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+ * secure context before it calls any secure function.
+ *
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+ */
     #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
 
-    /**
-     * @brief Called when a task is deleted to delete the task's secure context,
-     * if it has one.
-     *
-     * @param[in] pxTCB The TCB of the task being deleted.
-     */
+/**
+ * @brief Called when a task is deleted to delete the task's secure context,
+ * if it has one.
+ *
+ * @param[in] pxTCB The TCB of the task being deleted.
+ */
     #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
 #endif /* configENABLE_TRUSTZONE */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Checks whether or not the processor is privileged.
-     *
-     * @return 1 if the processor is already privileged, 0 otherwise.
-     */
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
     #define portIS_PRIVILEGED()      xIsPrivileged()
 
-    /**
-     * @brief Raise an SVC request to raise privilege.
-     *
-     * The SVC handler checks that the SVC was raised from a system call and only
-     * then it raises the privilege. If this is called from any other place,
-     * the privilege is not raised.
-     */
+/**
+ * @brief Raise an SVC request to raise privilege.
+ *
+ * The SVC handler checks that the SVC was raised from a system call and only
+ * then it raises the privilege. If this is called from any other place,
+ * the privilege is not raised.
+ */
     #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
 
-    /**
-     * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
-     * register.
-     */
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
     #define portRESET_PRIVILEGE()    vResetPrivilege()
 #else
     #define portIS_PRIVILEGED()
@@ -419,12 +419,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     extern BaseType_t xPortIsTaskPrivileged( void );
 
-    /**
-     * @brief Checks whether or not the calling task is privileged.
-     *
-     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
-     */
-    #define portIS_TASK_PRIVILEGED()      xPortIsTaskPrivileged()
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
+    #define portIS_TASK_PRIVILEGED()    xPortIsTaskPrivileged()
 
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
@@ -439,9 +439,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * based on whether or not Mainline extension is implemented. */
 #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
     #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
-        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
     #else
-        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    0
     #endif
 #endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
 
@@ -450,9 +450,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  */
 #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
 
-    /**
-     * @brief Count the number of leading zeros in a 32-bit value.
-     */
+/**
+ * @brief Count the number of leading zeros in a 32-bit value.
+ */
     static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
     {
         uint32_t ulReturn;
@@ -462,7 +462,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         return ulReturn;
     }
 
-    /* Check the configuration. */
+/* Check the configuration. */
     #if ( configMAX_PRIORITIES > 32 )
         #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
     #endif
@@ -471,16 +471,16 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection.  Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
     #endif
 
-    /**
-     * @brief Store/clear the ready priorities in a bit map.
-     */
-    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+/**
+ * @brief Store/clear the ready priorities in a bit map.
+ */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )      ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )       ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 
-    /**
-     * @brief Get the priority of the highest-priority task that is ready to execute.
-     */
-    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )   uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+/**
+ * @brief Get the priority of the highest-priority task that is ready to execute.
+ */
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
 
 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM35P/secure/secure_context.c b/portable/IAR/ARM_CM35P/secure/secure_context.c
index 0730d574d..7d2171996 100644
--- a/portable/IAR/ARM_CM35P/secure/secure_context.c
+++ b/portable/IAR/ARM_CM35P/secure/secure_context.c
@@ -65,7 +65,7 @@
  * @brief Maximum number of secure contexts.
  */
 #ifndef secureconfigMAX_SECURE_CONTEXTS
-    #define secureconfigMAX_SECURE_CONTEXTS        8UL
+    #define secureconfigMAX_SECURE_CONTEXTS    8UL
 #endif
 /*-----------------------------------------------------------*/
 
@@ -164,15 +164,15 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
         }
 
         #if ( configENABLE_MPU == 1 )
-            {
-                /* Configure thread mode to use PSP and to be unprivileged. */
-                secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
-            }
+        {
+            /* Configure thread mode to use PSP and to be unprivileged. */
+            secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
+        }
         #else /* configENABLE_MPU */
-            {
-                /* Configure thread mode to use PSP and to be privileged. */
-                secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
-            }
+        {
+            /* Configure thread mode to use PSP and to be privileged. */
+            secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
+        }
         #endif /* configENABLE_MPU */
     }
 }
@@ -219,16 +219,16 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
             if( pucStackMemory != NULL )
             {
                 /* Since stack grows down, the starting point will be the last
-                 * location. Note that this location is next to the last
-                 * allocated byte for stack (excluding the space for seal values)
-                 * because the hardware decrements the stack pointer before
-                 * writing i.e. if stack pointer is 0x2, a push operation will
-                 * decrement the stack pointer to 0x1 and then write at 0x1. */
+                * location. Note that this location is next to the last
+                * allocated byte for stack (excluding the space for seal values)
+                * because the hardware decrements the stack pointer before
+                * writing i.e. if stack pointer is 0x2, a push operation will
+                * decrement the stack pointer to 0x1 and then write at 0x1. */
                 xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize;
 
                 /* Seal the created secure process stack. */
-                *( uint32_t * )( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE;
-                *( uint32_t * )( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE;
+                *( uint32_t * ) ( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE;
+                *( uint32_t * ) ( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE;
 
                 /* The stack cannot go beyond this location. This value is
                  * programmed in the PSPLIM register on context switch.*/
@@ -237,32 +237,32 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
                 xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle;
 
                 #if ( configENABLE_MPU == 1 )
+                {
+                    /* Store the correct CONTROL value for the task on the stack.
+                     * This value is programmed in the CONTROL register on
+                     * context switch. */
+                    pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart;
+                    pulCurrentStackPointer--;
+
+                    if( ulIsTaskPrivileged )
                     {
-                        /* Store the correct CONTROL value for the task on the stack.
-                         * This value is programmed in the CONTROL register on
-                         * context switch. */
-                        pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart;
-                        pulCurrentStackPointer--;
-
-                        if( ulIsTaskPrivileged )
-                        {
-                            *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
-                        }
-                        else
-                        {
-                            *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
-                        }
-
-                        /* Store the current stack pointer. This value is programmed in
-                         * the PSP register on context switch. */
-                        xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+                        *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
                     }
+                    else
+                    {
+                        *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
+                    }
+
+                    /* Store the current stack pointer. This value is programmed in
+                     * the PSP register on context switch. */
+                    xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+                }
                 #else /* configENABLE_MPU */
-                    {
-                        /* Current SP is set to the starting of the stack. This
-                         * value programmed in the PSP register on context switch. */
-                        xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart;
-                    }
+                {
+                    /* Current SP is set to the starting of the stack. This
+                     * value programmed in the PSP register on context switch. */
+                    xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart;
+                }
                 #endif /* configENABLE_MPU */
 
                 /* Ensure to never return 0 as a valid context handle. */
@@ -275,7 +275,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
 }
 /*-----------------------------------------------------------*/
 
-secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle,
+                                                              void * pvTaskHandle )
 {
     uint32_t ulIPSR, ulSecureContextIndex;
 
@@ -306,7 +307,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandl
 }
 /*-----------------------------------------------------------*/
 
-secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle,
+                                                              void * pvTaskHandle )
 {
     uint8_t * pucStackLimit;
     uint32_t ulSecureContextIndex;
@@ -328,7 +330,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandl
 }
 /*-----------------------------------------------------------*/
 
-secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle,
+                                                              void * pvTaskHandle )
 {
     uint8_t * pucStackLimit;
     uint32_t ulSecureContextIndex;
diff --git a/portable/IAR/ARM_CM35P/secure/secure_context.h b/portable/IAR/ARM_CM35P/secure/secure_context.h
index d0adbaf01..0bf776198 100644
--- a/portable/IAR/ARM_CM35P/secure/secure_context.h
+++ b/portable/IAR/ARM_CM35P/secure/secure_context.h
@@ -38,12 +38,12 @@
 /**
  * @brief PSP value when no secure context is loaded.
  */
-#define securecontextNO_STACK               0x0
+#define securecontextNO_STACK              0x0
 
 /**
  * @brief Invalid context ID.
  */
-#define securecontextINVALID_CONTEXT_ID     0UL
+#define securecontextINVALID_CONTEXT_ID    0UL
 /*-----------------------------------------------------------*/
 
 /**
@@ -108,7 +108,8 @@ void SecureContext_Init( void );
  * @param[in] xSecureContextHandle Context handle corresponding to the
  * context to be freed.
  */
-void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle,
+                                void * pvTaskHandle );
 
 /**
  * @brief Loads the given context.
@@ -119,7 +120,8 @@ void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void
  * @param[in] xSecureContextHandle Context handle corresponding to the context
  * to be loaded.
  */
-void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle,
+                                void * pvTaskHandle );
 
 /**
  * @brief Saves the given context.
@@ -130,6 +132,7 @@ void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void
  * @param[in] xSecureContextHandle Context handle corresponding to the context
  * to be saved.
  */
-void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle,
+                                void * pvTaskHandle );
 
 #endif /* __SECURE_CONTEXT_H__ */
diff --git a/portable/IAR/ARM_CM35P/secure/secure_heap.c b/portable/IAR/ARM_CM35P/secure/secure_heap.c
index f3b80df54..1ec3bdbdb 100644
--- a/portable/IAR/ARM_CM35P/secure/secure_heap.c
+++ b/portable/IAR/ARM_CM35P/secure/secure_heap.c
@@ -67,7 +67,7 @@
 #define secureheapSIZE_MAX              ( ~( ( size_t ) 0 ) )
 
 /* Check if adding a and b will result in overflow. */
-#define secureheapADD_WILL_OVERFLOW( a, b )         ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) )
+#define secureheapADD_WILL_OVERFLOW( a, b )    ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) )
 
 /* MSB of the xBlockSize member of an BlockLink_t structure is used to track
  * the allocation status of a block.  When MSB of the xBlockSize member of
@@ -397,17 +397,17 @@ void * pvPortMalloc( size_t xWantedSize )
     traceMALLOC( pvReturn, xWantedSize );
 
     #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
+    {
+        if( pvReturn == NULL )
         {
-            if( pvReturn == NULL )
-            {
-                extern void vApplicationMallocFailedHook( void );
-                vApplicationMallocFailedHook();
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
+            extern void vApplicationMallocFailedHook( void );
+            vApplicationMallocFailedHook();
         }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
     #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */
 
     secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );
diff --git a/portable/IAR/ARM_CM35P/secure/secure_init.c b/portable/IAR/ARM_CM35P/secure/secure_init.c
index dc19ebc7d..b89c5f644 100644
--- a/portable/IAR/ARM_CM35P/secure/secure_init.c
+++ b/portable/IAR/ARM_CM35P/secure/secure_init.c
@@ -93,7 +93,7 @@ secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )
          * permitted. CP11 should be programmed to the same value as CP10. */
         *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
 
-        /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
+        /* LSPENS = 0 ==> LSPEN is writable from non-secure state. This ensures
          * that we can enable/disable lazy stacking in port.c file. */
         *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK );
 
diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c b/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
index 80410e82e..c940c304b 100644
--- a/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
@@ -110,8 +110,8 @@
 /**
  * @brief Constants used during system call enter and exit.
  */
-#define portPSR_STACK_PADDING_MASK                ( 1UL << 9UL )
-#define portEXC_RETURN_STACK_FRAME_TYPE_MASK      ( 1UL << 4UL )
+#define portPSR_STACK_PADDING_MASK              ( 1UL << 9UL )
+#define portEXC_RETURN_STACK_FRAME_TYPE_MASK    ( 1UL << 4UL )
 /*-----------------------------------------------------------*/
 
 /**
@@ -133,81 +133,81 @@
 /**
  * @brief Offsets in the stack to the parameters when inside the SVC handler.
  */
-#define portOFFSET_TO_LR                    ( 5 )
-#define portOFFSET_TO_PC                    ( 6 )
-#define portOFFSET_TO_PSR                   ( 7 )
+#define portOFFSET_TO_LR     ( 5 )
+#define portOFFSET_TO_PC     ( 6 )
+#define portOFFSET_TO_PSR    ( 7 )
 /*-----------------------------------------------------------*/
 
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                      ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                      ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                       ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                      ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                      ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                     ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                     ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK  ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK               ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK               ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK               ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK               ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK               ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK               ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK               ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK               ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0              ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1              ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2              ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3              ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4              ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5              ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6              ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7              ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE            ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT      ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                      ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE             ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -216,11 +216,11 @@
 
 /* Extract last address of the MPU region as encoded in the
  * RLAR (Region Limit Address Register) value. */
-#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar )  \
+#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar ) \
     ( ( ( rlar ) & portMPU_RLAR_ADDRESS_MASK ) | ~portMPU_RLAR_ADDRESS_MASK )
 
 /* Does addr lies within [start, end] address range? */
-#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end )    \
+#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \
     ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) )
 
 /* Is the access request satisfied by the available permissions? */
@@ -422,54 +422,57 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the system call stack so that upon returning from
-     * SVC, the system call stack is used.
-     *
-     * It is used for the system calls with up to 4 parameters.
-     *
-     * @param pulTaskStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the system call stack so that upon returning from
+ * SVC, the system call stack is used.
+ *
+ * It is used for the system calls with up to 4 parameters.
+ *
+ * @param pulTaskStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallEnter( uint32_t * pulTaskStack,
+                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the system call stack so that upon returning from
-     * SVC, the system call stack is used.
-     *
-     * It is used for the system calls with 5 parameters.
-     *
-     * @param pulTaskStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the system call stack so that upon returning from
+ * SVC, the system call stack is used.
+ *
+ * It is used for the system calls with 5 parameters.
+ *
+ * @param pulTaskStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallEnter_1( uint32_t * pulTaskStack,
+                             uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the task stack so that upon returning from
-     * SVC, the task stack is used again.
-     *
-     * @param pulSystemCallStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the task stack so that upon returning from
+ * SVC, the task stack is used again.
+ *
+ * @param pulSystemCallStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallExit( uint32_t * pulSystemCallStack,
+                          uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Checks whether or not the calling task is privileged.
-     *
-     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
-     */
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
     BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
 
 #endif /* configENABLE_MPU == 1 */
@@ -1086,18 +1089,18 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             vRestoreContextOfFirstTask();
             break;
 
-        #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
-            case portSVC_RAISE_PRIVILEGE:
+            #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+                case portSVC_RAISE_PRIVILEGE:
 
-                /* Only raise the privilege, if the svc was raised from any of
-                 * the system calls. */
-                if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
-                    ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
-                {
-                    vRaisePrivilege();
-                }
-                break;
-        #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+                    /* Only raise the privilege, if the svc was raised from any of
+                     * the system calls. */
+                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+                    {
+                        vRaisePrivilege();
+                    }
+                    break;
+            #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
         default:
             /* Incorrect SVC call. */
@@ -1108,513 +1111,526 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulSystemCallStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallEnter( uint32_t * pulTaskStack,
+                           uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulSystemCallStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        /* This is not NULL only for the duration of the system call. */
-        configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+        #if defined( __ARMCC_VERSION )
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+
+            /* This is not NULL only for the duration of the system call. */
+            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the system call stack for the stack frame. */
+            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulSystemCallStack[ i ] = pulTaskStack[ i ];
+            }
+
+            /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
+             * restore it when we exit from the system call. */
+            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* Use the pulSystemCallStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+
+            /* Remember the location where we should copy the stack frame when we exit from
+             * the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+
+            /* Record if the hardware used padding to force the stack pointer
+             * to be double word aligned. */
+            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
+            {
+                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
             }
+
+            /* We ensure in pxPortInitialiseStack that the system call stack is
+             * double word aligned and therefore, there is no need of padding.
+             * Clear the bit[9] of stacked xPSR. */
+            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
+
+            /* Raise the privilege for the duration of the system call. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " bics r0, r1         \n" /* Clear nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the system call stack for the stack frame. */
-        pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulSystemCallStack[ i ] = pulTaskStack[ i ];
-        }
-
-        /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
-         * restore it when we exit from the system call. */
-        pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-        __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* Use the pulSystemCallStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-
-        /* Remember the location where we should copy the stack frame when we exit from
-         * the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-        /* Record if the hardware used padding to force the stack pointer
-         * to be double word aligned. */
-        if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-        {
-            pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-        }
-        else
-        {
-            pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-        }
-
-        /* We ensure in pxPortInitialiseStack that the system call stack is
-         * double word aligned and therefore, there is no need of padding.
-         * Clear the bit[9] of stacked xPSR. */
-        pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-        /* Raise the privilege for the duration of the system call. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " bics r0, r1         \n" /* Clear nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulSystemCallStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallEnter_1( uint32_t * pulTaskStack,
+                             uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulSystemCallStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        /* This is not NULL only for the duration of the system call. */
-        configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+        #if defined( __ARMCC_VERSION )
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+
+            /* This is not NULL only for the duration of the system call. */
+            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the system call stack for the stack frame and
+             * the parameter passed on the stack. We only need to copy one
+             * parameter but we still reserve 2 spaces to keep the stack
+             * double word aligned. */
+            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulSystemCallStack[ i ] = pulTaskStack[ i ];
+            }
+
+            /* Copy the parameter which is passed the stack. */
+            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
+            {
+                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
+
+                /* Record if the hardware used padding to force the stack pointer
+                 * to be double word aligned. */
+                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
+
+                /* Record if the hardware used padding to force the stack pointer
+                 * to be double word aligned. */
+                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
             }
+
+            /* Store the value of the LR and PSPLIM registers before the SVC was raised.
+             * We need to restore it when we exit from the system call. */
+            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* Use the pulSystemCallStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+
+            /* Remember the location where we should copy the stack frame when we exit from
+             * the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+
+            /* We ensure in pxPortInitialiseStack that the system call stack is
+             * double word aligned and therefore, there is no need of padding.
+             * Clear the bit[9] of stacked xPSR. */
+            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
+
+            /* Raise the privilege for the duration of the system call. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " bics r0, r1         \n" /* Clear nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the system call stack for the stack frame and
-         * the parameter passed on the stack. We only need to copy one
-         * parameter but we still reserve 2 spaces to keep the stack
-         * double word aligned. */
-        pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulSystemCallStack[ i ] = pulTaskStack[ i ];
-        }
-
-        /* Copy the parameter which is passed the stack. */
-        if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-        {
-            pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
-            /* Record if the hardware used padding to force the stack pointer
-             * to be double word aligned. */
-            pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-        }
-        else
-        {
-            pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
-            /* Record if the hardware used padding to force the stack pointer
-             * to be double word aligned. */
-            pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-        }
-
-        /* Store the value of the LR and PSPLIM registers before the SVC was raised.
-         * We need to restore it when we exit from the system call. */
-        pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-        __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* Use the pulSystemCallStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-
-        /* Remember the location where we should copy the stack frame when we exit from
-         * the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-        /* We ensure in pxPortInitialiseStack that the system call stack is
-         * double word aligned and therefore, there is no need of padding.
-         * Clear the bit[9] of stacked xPSR. */
-        pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-        /* Raise the privilege for the duration of the system call. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " bics r0, r1         \n" /* Clear nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulTaskStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallExit( uint32_t * pulSystemCallStack,
+                          uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulTaskStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+        #if defined( __ARMCC_VERSION )
+
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the task stack for the stack frame. */
+            pulTaskStack = pulTaskStack - ulStackFrameSize;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulTaskStack[ i ] = pulSystemCallStack[ i ];
+            }
+
+            /* Use the pulTaskStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
+
+            /* Restore the LR and PSPLIM to what they were at the time of
+             * system call entry. */
+            pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* If the hardware used padding to force the stack pointer
+             * to be double word aligned, set the stacked xPSR bit[9],
+             * otherwise clear it. */
+            if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG )
+            {
+                pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
             }
+
+            /* This is not NULL only for the duration of the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
+
+            /* Drop the privilege before returning to the thread mode. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " orrs r0, r1         \n" /* Set nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the task stack for the stack frame. */
-        pulTaskStack = pulTaskStack - ulStackFrameSize;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulTaskStack[ i ] = pulSystemCallStack[ i ];
-        }
-
-        /* Use the pulTaskStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
-
-        /* Restore the LR and PSPLIM to what they were at the time of
-         * system call entry. */
-        pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* If the hardware used padding to force the stack pointer
-         * to be double word aligned, set the stacked xPSR bit[9],
-         * otherwise clear it. */
-        if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG )
-        {
-            pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK;
-        }
-        else
-        {
-            pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-        }
-
-        /* This is not NULL only for the duration of the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
-
-        /* Drop the privilege before returning to the thread mode. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " orrs r0, r1         \n" /* Set nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */
-{
-    BaseType_t xTaskIsPrivileged = pdFALSE;
-    const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
-
-    if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+    BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */
     {
-        xTaskIsPrivileged = pdTRUE;
-    }
+        BaseType_t xTaskIsPrivileged = pdFALSE;
+        const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
 
-    return xTaskIsPrivileged;
-}
+        if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+        {
+            xTaskIsPrivileged = pdTRUE;
+        }
+
+        return xTaskIsPrivileged;
+    }
 
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
-#if( configENABLE_MPU == 1 )
+#if ( configENABLE_MPU == 1 )
 
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     StackType_t * pxEndOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters,
-                                     BaseType_t xRunPrivileged,
-                                     xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
-{
-    uint32_t ulIndex = 0;
-
-    xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
-    ulIndex++;
-
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
-    ulIndex++;
-
-    #if ( configENABLE_TRUSTZONE == 1 )
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters,
+                                         BaseType_t xRunPrivileged,
+                                         xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
     {
-        xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT;  /* xSecureContext. */
+        uint32_t ulIndex = 0;
+
+        xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
         ulIndex++;
-    }
-    #endif /* configENABLE_TRUSTZONE */
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
-    ulIndex++;
-    if( xRunPrivileged == pdTRUE )
-    {
-        xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */
         ulIndex++;
-    }
-    else
-    {
-        xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */
         ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
+        ulIndex++;
+
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters;            /* r0. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x01010101;                           /* r1. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x02020202;                           /* r2. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x03030303;                           /* r3. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x12121212;                           /* r12. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode;                  /* PC. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR;                     /* xPSR. */
+        ulIndex++;
+
+        #if ( configENABLE_TRUSTZONE == 1 )
+        {
+            xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT; /* xSecureContext. */
+            ulIndex++;
+        }
+        #endif /* configENABLE_TRUSTZONE */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
+        ulIndex++;
+
+        if( xRunPrivileged == pdTRUE )
+        {
+            xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
+            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+            ulIndex++;
+        }
+        else
+        {
+            xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
+            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+            ulIndex++;
+        }
+
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
+        ulIndex++;
+
+        #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+        {
+            /* Ensure that the system call stack is double word aligned. */
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] );
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) &
+                                                                                     ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
+
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] );
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) +
+                                                                                            ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) &
+                                                                                          ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
+
+            /* This is not NULL only for the duration of a system call. */
+            xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL;
+        }
+        #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
+
+        return &( xMPUSettings->ulContext[ ulIndex ] );
     }
-    xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
-    ulIndex++;
-
-    #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
-    {
-        /* Ensure that the system call stack is double word aligned. */
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] );
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) &
-                                                                                 ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
-
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] );
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) +
-                                                                                        ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) &
-                                                                                      ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
-
-        /* This is not NULL only for the duration of a system call. */
-        xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL;
-    }
-    #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
-
-    return &( xMPUSettings->ulContext[ ulIndex ] );
-}
 
 #else /* configENABLE_MPU */
 
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     StackType_t * pxEndOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters ) /* PRIVILEGED_FUNCTION */
-{
-    /* Simulate the stack frame as it would be created by a context switch
-     * interrupt. */
-    #if ( portPRELOAD_REGISTERS == 0 )
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters ) /* PRIVILEGED_FUNCTION */
     {
-        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-        pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
-        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-        pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
-        *pxTopOfStack = portINITIAL_EXC_RETURN;
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
-
-        #if ( configENABLE_TRUSTZONE == 1 )
+        /* Simulate the stack frame as it would be created by a context switch
+         * interrupt. */
+        #if ( portPRELOAD_REGISTERS == 0 )
         {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
-        }
-        #endif /* configENABLE_TRUSTZONE */
-    }
-    #else /* portPRELOAD_REGISTERS */
-    {
-        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
-        pxTopOfStack--;
-        *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
+            pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
+            *pxTopOfStack = portINITIAL_EXC_RETURN;
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+            #if ( configENABLE_TRUSTZONE == 1 )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+            }
+            #endif /* configENABLE_TRUSTZONE */
+        }
+        #else /* portPRELOAD_REGISTERS */
         {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
-        }
-        #endif /* configENABLE_TRUSTZONE */
-    }
-    #endif /* portPRELOAD_REGISTERS */
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
+            pxTopOfStack--;
+            *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack;            /* Slot used to hold this task's PSPLIM value. */
 
-    return pxTopOfStack;
-}
+            #if ( configENABLE_TRUSTZONE == 1 )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+            }
+            #endif /* configENABLE_TRUSTZONE */
+        }
+        #endif /* portPRELOAD_REGISTERS */
+
+        return pxTopOfStack;
+    }
 
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacro.h b/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacro.h
index 5669c1f60..82bfaeb79 100644
--- a/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacro.h
@@ -48,16 +48,16 @@
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME                       "Cortex-M35P"
-#define portHAS_ARMV8M_MAIN_EXTENSION       1
-#define portDONT_DISCARD                    __root
+#define portARCH_NAME                    "Cortex-M35P"
+#define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
 /* ARMv8-M common port configurations. */
 #include "portmacrocommon.h"
 /*-----------------------------------------------------------*/
 
-#if( configTOTAL_MPU_REGIONS == 16 )
+#if ( configTOTAL_MPU_REGIONS == 16 )
     #error 16 MPU regions are not yet supported for this port.
 #endif
 /*-----------------------------------------------------------*/
@@ -65,8 +65,8 @@
 /**
  * @brief Critical section management.
  */
-#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()
-#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )
+#define portDISABLE_INTERRUPTS()    ulSetInterruptMask()
+#define portENABLE_INTERRUPTS()     vClearInterruptMask( 0 )
 /*-----------------------------------------------------------*/
 
 /* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
index e5ffdb48b..62e462a27 100644
--- a/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
@@ -81,8 +81,8 @@ typedef unsigned long    UBaseType_t;
     typedef uint32_t     TickType_t;
     #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-     * not need to be guarded with a critical section. */
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
     #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -117,7 +117,7 @@ extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGE
 extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
 
 #if ( configENABLE_TRUSTZONE == 1 )
-    extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize );     /* __attribute__ (( naked )) */
+    extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
     extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
 #endif /* configENABLE_TRUSTZONE */
 
@@ -188,13 +188,13 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Settings to define an MPU region.
-     */
+/**
+ * @brief Settings to define an MPU region.
+ */
     typedef struct MPURegionSettings
     {
-        uint32_t ulRBAR;     /**< RBAR for the region. */
-        uint32_t ulRLAR;     /**< RLAR for the region. */
+        uint32_t ulRBAR; /**< RBAR for the region. */
+        uint32_t ulRLAR; /**< RLAR for the region. */
     } MPURegionSettings_t;
 
     #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
@@ -203,9 +203,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-        /**
-         * @brief System call stack.
-         */
+/**
+ * @brief System call stack.
+ */
         typedef struct SYSTEM_CALL_STACK_INFO
         {
             uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ];
@@ -218,74 +218,74 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
-    /**
-     * @brief MPU settings as stored in the TCB.
-     */
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
     #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
 
-        #if( configENABLE_TRUSTZONE == 1 )
+        #if ( configENABLE_TRUSTZONE == 1 )
 
-            /*
-             * +-----------+---------------+----------+-----------------+------------------------------+-----+
-             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
-             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
-             * +-----------+---------------+----------+-----------------+------------------------------+-----+
-             *
-             * <-----------><--------------><---------><----------------><-----------------------------><---->
-             *      16             16            8               8                     5                   1
-             */
-            #define MAX_CONTEXT_SIZE 54
+/*
+ * +-----------+---------------+----------+-----------------+------------------------------+-----+
+ * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+ * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+ * +-----------+---------------+----------+-----------------+------------------------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><-----------------------------><---->
+ *      16             16            8               8                     5                   1
+ */
+            #define MAX_CONTEXT_SIZE    54
 
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-            /*
-             * +-----------+---------------+----------+-----------------+----------------------+-----+
-             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
-             * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
-             * +-----------+---------------+----------+-----------------+----------------------+-----+
-             *
-             * <-----------><--------------><---------><----------------><---------------------><---->
-             *      16             16            8               8                  4              1
-             */
-            #define MAX_CONTEXT_SIZE 53
+/*
+ * +-----------+---------------+----------+-----------------+----------------------+-----+
+ * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+ * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
+ * +-----------+---------------+----------+-----------------+----------------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><---------------------><---->
+ *      16             16            8               8                  4              1
+ */
+            #define MAX_CONTEXT_SIZE    53
 
         #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
 
     #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-        #if( configENABLE_TRUSTZONE == 1 )
+        #if ( configENABLE_TRUSTZONE == 1 )
 
-            /*
-             * +----------+-----------------+------------------------------+-----+
-             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
-             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
-             * +----------+-----------------+------------------------------+-----+
-             *
-             * <---------><----------------><------------------------------><---->
-             *     8               8                      5                   1
-             */
-            #define MAX_CONTEXT_SIZE 22
+/*
+ * +----------+-----------------+------------------------------+-----+
+ * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+ * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+ * +----------+-----------------+------------------------------+-----+
+ *
+ * <---------><----------------><------------------------------><---->
+ *     8               8                      5                   1
+ */
+            #define MAX_CONTEXT_SIZE    22
 
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-            /*
-             * +----------+-----------------+----------------------+-----+
-             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
-             * |          | PC, xPSR        | EXC_RETURN           |     |
-             * +----------+-----------------+----------------------+-----+
-             *
-             * <---------><----------------><----------------------><---->
-             *     8               8                  4              1
-             */
-            #define MAX_CONTEXT_SIZE 21
+/*
+ * +----------+-----------------+----------------------+-----+
+ * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+ * |          | PC, xPSR        | EXC_RETURN           |     |
+ * +----------+-----------------+----------------------+-----+
+ *
+ * <---------><----------------><----------------------><---->
+ *     8               8                  4              1
+ */
+            #define MAX_CONTEXT_SIZE    21
 
         #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
 
     #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-    /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
-    #define portSTACK_FRAME_HAS_PADDING_FLAG     ( 1UL << 0UL )
-    #define portTASK_IS_PRIVILEGED_FLAG          ( 1UL << 1UL )
+/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
+    #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
+    #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
     typedef struct MPU_SETTINGS
     {
@@ -364,49 +364,49 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-    /**
-     * @brief Allocate a secure context for the task.
-     *
-     * Tasks are not created with a secure context. Any task that is going to call
-     * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
-     * secure context before it calls any secure function.
-     *
-     * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
-     */
+/**
+ * @brief Allocate a secure context for the task.
+ *
+ * Tasks are not created with a secure context. Any task that is going to call
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+ * secure context before it calls any secure function.
+ *
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+ */
     #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
 
-    /**
-     * @brief Called when a task is deleted to delete the task's secure context,
-     * if it has one.
-     *
-     * @param[in] pxTCB The TCB of the task being deleted.
-     */
+/**
+ * @brief Called when a task is deleted to delete the task's secure context,
+ * if it has one.
+ *
+ * @param[in] pxTCB The TCB of the task being deleted.
+ */
     #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
 #endif /* configENABLE_TRUSTZONE */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Checks whether or not the processor is privileged.
-     *
-     * @return 1 if the processor is already privileged, 0 otherwise.
-     */
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
     #define portIS_PRIVILEGED()      xIsPrivileged()
 
-    /**
-     * @brief Raise an SVC request to raise privilege.
-     *
-     * The SVC handler checks that the SVC was raised from a system call and only
-     * then it raises the privilege. If this is called from any other place,
-     * the privilege is not raised.
-     */
+/**
+ * @brief Raise an SVC request to raise privilege.
+ *
+ * The SVC handler checks that the SVC was raised from a system call and only
+ * then it raises the privilege. If this is called from any other place,
+ * the privilege is not raised.
+ */
     #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
 
-    /**
-     * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
-     * register.
-     */
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
     #define portRESET_PRIVILEGE()    vResetPrivilege()
 #else
     #define portIS_PRIVILEGED()
@@ -419,12 +419,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     extern BaseType_t xPortIsTaskPrivileged( void );
 
-    /**
-     * @brief Checks whether or not the calling task is privileged.
-     *
-     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
-     */
-    #define portIS_TASK_PRIVILEGED()      xPortIsTaskPrivileged()
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
+    #define portIS_TASK_PRIVILEGED()    xPortIsTaskPrivileged()
 
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
@@ -439,9 +439,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * based on whether or not Mainline extension is implemented. */
 #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
     #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
-        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
     #else
-        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    0
     #endif
 #endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
 
@@ -450,9 +450,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  */
 #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
 
-    /**
-     * @brief Count the number of leading zeros in a 32-bit value.
-     */
+/**
+ * @brief Count the number of leading zeros in a 32-bit value.
+ */
     static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
     {
         uint32_t ulReturn;
@@ -462,7 +462,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         return ulReturn;
     }
 
-    /* Check the configuration. */
+/* Check the configuration. */
     #if ( configMAX_PRIORITIES > 32 )
         #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
     #endif
@@ -471,16 +471,16 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection.  Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
     #endif
 
-    /**
-     * @brief Store/clear the ready priorities in a bit map.
-     */
-    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+/**
+ * @brief Store/clear the ready priorities in a bit map.
+ */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )      ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )       ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 
-    /**
-     * @brief Get the priority of the highest-priority task that is ready to execute.
-     */
-    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )   uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+/**
+ * @brief Get the priority of the highest-priority task that is ready to execute.
+ */
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
 
 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM4F/port.c b/portable/IAR/ARM_CM4F/port.c
old mode 100755
new mode 100644
index 8234c7dd8..dd328160b
--- a/portable/IAR/ARM_CM4F/port.c
+++ b/portable/IAR/ARM_CM4F/port.c
@@ -295,22 +295,22 @@ BaseType_t xPortStartScheduler( void )
         if( ulImplementedPrioBits == 8 )
         {
             /* When the hardware implements 8 priority bits, there is no way for
-            * the software to configure PRIGROUP to not have sub-priorities. As
-            * a result, the least significant bit is always used for sub-priority
-            * and there are 128 preemption priorities and 2 sub-priorities.
-            *
-            * This may cause some confusion in some cases - for example, if
-            * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
-            * priority interrupts will be masked in Critical Sections as those
-            * are at the same preemption priority. This may appear confusing as
-            * 4 is higher (numerically lower) priority than
-            * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
-            * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
-            * to 4, this confusion does not happen and the behaviour remains the same.
-            *
-            * The following assert ensures that the sub-priority bit in the
-            * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
-            * confusion. */
+             * the software to configure PRIGROUP to not have sub-priorities. As
+             * a result, the least significant bit is always used for sub-priority
+             * and there are 128 preemption priorities and 2 sub-priorities.
+             *
+             * This may cause some confusion in some cases - for example, if
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
+             * priority interrupts will be masked in Critical Sections as those
+             * are at the same preemption priority. This may appear confusing as
+             * 4 is higher (numerically lower) priority than
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
+             * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
+             * to 4, this confusion does not happen and the behaviour remains the same.
+             *
+             * The following assert ensures that the sub-priority bit in the
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
+             * confusion. */
             configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
             ulMaxPRIGROUPValue = 0;
         }
diff --git a/portable/IAR/ARM_CM4F/portmacro.h b/portable/IAR/ARM_CM4F/portmacro.h
index 02f1d6ff0..5c4369418 100644
--- a/portable/IAR/ARM_CM4F/portmacro.h
+++ b/portable/IAR/ARM_CM4F/portmacro.h
@@ -27,7 +27,7 @@
  */
 
 #ifndef PORTMACRO_H
-    #define PORTMACRO_H
+#define PORTMACRO_H
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
@@ -46,50 +46,50 @@
  */
 
 /* IAR includes. */
-    #include <intrinsics.h>
+#include <intrinsics.h>
 
 /* Type definitions. */
-    #define portCHAR          char
-    #define portFLOAT         float
-    #define portDOUBLE        double
-    #define portLONG          long
-    #define portSHORT         short
-    #define portSTACK_TYPE    uint32_t
-    #define portBASE_TYPE     long
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-    typedef portSTACK_TYPE   StackType_t;
-    typedef long             BaseType_t;
-    typedef unsigned long    UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
-    #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-        typedef uint16_t     TickType_t;
-        #define portMAX_DELAY              ( TickType_t ) 0xffff
-    #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-        typedef uint32_t     TickType_t;
-        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
  * not need to be guarded with a critical section. */
-        #define portTICK_TYPE_IS_ATOMIC    1
-    #else
-        #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
-    #endif
+    #define portTICK_TYPE_IS_ATOMIC    1
+#else
+    #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+#endif
 /*-----------------------------------------------------------*/
 
 /* Architecture specifics. */
-    #define portSTACK_GROWTH      ( -1 )
-    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-    #define portBYTE_ALIGNMENT    8
+#define portSTACK_GROWTH      ( -1 )
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT    8
 /*-----------------------------------------------------------*/
 
 /* Compiler directives. */
-    #define portWEAK_SYMBOL    __attribute__( ( weak ) )
+#define portWEAK_SYMBOL    __attribute__( ( weak ) )
 
 /*-----------------------------------------------------------*/
 
 
 /* Scheduler utilities. */
-    #define portYIELD()                                 \
+#define portYIELD()                                     \
     {                                                   \
         /* Set a PendSV to request a context switch. */ \
         portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
@@ -97,112 +97,112 @@
         __ISB();                                        \
     }
 
-    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
-    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-    #define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 )
-    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+#define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired != pdFALSE ) portYIELD( ); } while( 0 )
+#define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
 
 /*-----------------------------------------------------------*/
 
 /* Architecture specific optimisations. */
-    #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
-    #endif
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+    #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
+#endif
 
-    #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
 
 /* Check the configuration. */
-        #if ( configMAX_PRIORITIES > 32 )
-            #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
-        #endif
+    #if ( configMAX_PRIORITIES > 32 )
+        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+    #endif
 
 /* Store/clear the ready priorities in a bit map. */
-        #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-        #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 
 /*-----------------------------------------------------------*/
 
-        #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ( ( uint32_t ) __CLZ( ( uxReadyPriorities ) ) ) )
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ( ( uint32_t ) __CLZ( ( uxReadyPriorities ) ) ) )
 
-    #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 /*-----------------------------------------------------------*/
 
 /* Critical section management. */
-    extern void vPortEnterCritical( void );
-    extern void vPortExitCritical( void );
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
 
-    #define portDISABLE_INTERRUPTS()                           \
+#define portDISABLE_INTERRUPTS()                               \
     {                                                          \
         __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \
         __DSB();                                               \
         __ISB();                                               \
     }
 
-    #define portENABLE_INTERRUPTS()                   __set_BASEPRI( 0 )
-    #define portENTER_CRITICAL()                      vPortEnterCritical()
-    #define portEXIT_CRITICAL()                       vPortExitCritical()
-    #define portSET_INTERRUPT_MASK_FROM_ISR()         __get_BASEPRI(); portDISABLE_INTERRUPTS()
-    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    __set_BASEPRI( x )
+#define portENABLE_INTERRUPTS()                   __set_BASEPRI( 0 )
+#define portENTER_CRITICAL()                      vPortEnterCritical()
+#define portEXIT_CRITICAL()                       vPortExitCritical()
+#define portSET_INTERRUPT_MASK_FROM_ISR()         __get_BASEPRI(); portDISABLE_INTERRUPTS()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    __set_BASEPRI( x )
 /*-----------------------------------------------------------*/
 
 /* Tickless idle/low power functionality. */
-    #ifndef portSUPPRESS_TICKS_AND_SLEEP
-        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
-        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
-    #endif
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+    extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+    #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site.  These are
  * not necessary for to use this port.  They are defined so the common demo files
  * (which build with all the ports) will build. */
-    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
-    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 /*-----------------------------------------------------------*/
 
-    #ifdef configASSERT
-        void vPortValidateInterruptPriority( void );
-        #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
-    #endif
+#ifdef configASSERT
+    void vPortValidateInterruptPriority( void );
+    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
+#endif
 
 /* portNOP() is not required by this port. */
-    #define portNOP()
+#define portNOP()
 
-    #define portINLINE              __inline
+#define portINLINE              __inline
 
-    #ifndef portFORCE_INLINE
-        #define portFORCE_INLINE    inline __attribute__( ( always_inline ) )
-    #endif
+#ifndef portFORCE_INLINE
+    #define portFORCE_INLINE    inline __attribute__( ( always_inline ) )
+#endif
 
 /*-----------------------------------------------------------*/
 
-    portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
+portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
+{
+    uint32_t ulCurrentInterrupt;
+    BaseType_t xReturn;
+
+    /* Obtain the number of the currently executing interrupt. */
+    __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+    if( ulCurrentInterrupt == 0 )
     {
-        uint32_t ulCurrentInterrupt;
-        BaseType_t xReturn;
-
-        /* Obtain the number of the currently executing interrupt. */
-        __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
-
-        if( ulCurrentInterrupt == 0 )
-        {
-            xReturn = pdFALSE;
-        }
-        else
-        {
-            xReturn = pdTRUE;
-        }
-
-        return xReturn;
+        xReturn = pdFALSE;
     }
+    else
+    {
+        xReturn = pdTRUE;
+    }
+
+    return xReturn;
+}
 
 /*-----------------------------------------------------------*/
 
 /* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
  * the source code because to do so would cause other compilers to generate
  * warnings. */
-    #pragma diag_suppress=Pe191
-    #pragma diag_suppress=Pa082
+#pragma diag_suppress=Pe191
+#pragma diag_suppress=Pa082
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/IAR/ARM_CM4F_MPU/port.c b/portable/IAR/ARM_CM4F_MPU/port.c
old mode 100755
new mode 100644
index d24297e28..5cd257044
--- a/portable/IAR/ARM_CM4F_MPU/port.c
+++ b/portable/IAR/ARM_CM4F_MPU/port.c
@@ -232,44 +232,47 @@ extern void vPortRestoreContextOfFirstTask( void ) PRIVILEGED_FUNCTION;
 
 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
 
-    /**
-     * @brief Sets up the system call stack so that upon returning from
-     * SVC, the system call stack is used.
-     *
-     * It is used for the system calls with up to 4 parameters.
-     *
-     * @param pulTaskStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the system call stack so that upon returning from
+ * SVC, the system call stack is used.
+ *
+ * It is used for the system calls with up to 4 parameters.
+ *
+ * @param pulTaskStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallEnter( uint32_t * pulTaskStack,
+                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
 
-    /**
-     * @brief Sets up the system call stack so that upon returning from
-     * SVC, the system call stack is used.
-     *
-     * It is used for the system calls with 5 parameters.
-     *
-     * @param pulTaskStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the system call stack so that upon returning from
+ * SVC, the system call stack is used.
+ *
+ * It is used for the system calls with 5 parameters.
+ *
+ * @param pulTaskStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallEnter_1( uint32_t * pulTaskStack,
+                             uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
 
-    /**
-     * @brief Sets up the task stack so that upon returning from
-     * SVC, the task stack is used again.
-     *
-     * @param pulSystemCallStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the task stack so that upon returning from
+ * SVC, the task stack is used again.
+ *
+ * @param pulSystemCallStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallExit( uint32_t * pulSystemCallStack,
+                          uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
@@ -318,25 +321,26 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
         xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
         xMPUSettings->ulContext[ 0 ] = portINITIAL_CONTROL_IF_UNPRIVILEGED;
     }
-    xMPUSettings->ulContext[ 1 ] = 0x04040404; /* r4. */
-    xMPUSettings->ulContext[ 2 ] = 0x05050505; /* r5. */
-    xMPUSettings->ulContext[ 3 ] = 0x06060606; /* r6. */
-    xMPUSettings->ulContext[ 4 ] = 0x07070707; /* r7. */
-    xMPUSettings->ulContext[ 5 ] = 0x08080808; /* r8. */
-    xMPUSettings->ulContext[ 6 ] = 0x09090909; /* r9. */
-    xMPUSettings->ulContext[ 7 ] = 0x10101010; /* r10. */
-    xMPUSettings->ulContext[ 8 ] = 0x11111111; /* r11. */
-    xMPUSettings->ulContext[ 9 ] = portINITIAL_EXC_RETURN; /* EXC_RETURN. */
 
-    xMPUSettings->ulContext[ 10 ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
-    xMPUSettings->ulContext[ 11 ] = ( uint32_t ) pvParameters; /* r0. */
-    xMPUSettings->ulContext[ 12 ] = 0x01010101; /* r1. */
-    xMPUSettings->ulContext[ 13 ] = 0x02020202; /* r2. */
-    xMPUSettings->ulContext[ 14 ] = 0x03030303; /* r3. */
-    xMPUSettings->ulContext[ 15 ] = 0x12121212; /* r12. */
-    xMPUSettings->ulContext[ 16 ] = 0; /* LR. */
+    xMPUSettings->ulContext[ 1 ] = 0x04040404;                                        /* r4. */
+    xMPUSettings->ulContext[ 2 ] = 0x05050505;                                        /* r5. */
+    xMPUSettings->ulContext[ 3 ] = 0x06060606;                                        /* r6. */
+    xMPUSettings->ulContext[ 4 ] = 0x07070707;                                        /* r7. */
+    xMPUSettings->ulContext[ 5 ] = 0x08080808;                                        /* r8. */
+    xMPUSettings->ulContext[ 6 ] = 0x09090909;                                        /* r9. */
+    xMPUSettings->ulContext[ 7 ] = 0x10101010;                                        /* r10. */
+    xMPUSettings->ulContext[ 8 ] = 0x11111111;                                        /* r11. */
+    xMPUSettings->ulContext[ 9 ] = portINITIAL_EXC_RETURN;                            /* EXC_RETURN. */
+
+    xMPUSettings->ulContext[ 10 ] = ( uint32_t ) ( pxTopOfStack - 8 );                /* PSP with the hardware saved stack. */
+    xMPUSettings->ulContext[ 11 ] = ( uint32_t ) pvParameters;                        /* r0. */
+    xMPUSettings->ulContext[ 12 ] = 0x01010101;                                       /* r1. */
+    xMPUSettings->ulContext[ 13 ] = 0x02020202;                                       /* r2. */
+    xMPUSettings->ulContext[ 14 ] = 0x03030303;                                       /* r3. */
+    xMPUSettings->ulContext[ 15 ] = 0x12121212;                                       /* r12. */
+    xMPUSettings->ulContext[ 16 ] = 0;                                                /* LR. */
     xMPUSettings->ulContext[ 17 ] = ( ( uint32_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC. */
-    xMPUSettings->ulContext[ 18 ] = portINITIAL_XPSR; /* xPSR. */
+    xMPUSettings->ulContext[ 18 ] = portINITIAL_XPSR;                                 /* xPSR. */
 
     #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
     {
@@ -416,7 +420,7 @@ void vPortSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
                         ::: "r1", "memory"
                     );
                     break;
-            #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
+                    #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
 
                 default: /* Unknown SVC call. */
                     break;
@@ -426,288 +430,299 @@ void vPortSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
 
 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
 
-void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulSystemCallStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallEnter( uint32_t * pulTaskStack,
+                           uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulSystemCallStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        /* This is not NULL only for the duration of the system call. */
-        configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+        #if defined( __ARMCC_VERSION )
 
-        if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            /* Extended frame i.e. FPU in use. */
-            ulStackFrameSize = 26;
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+
+            /* This is not NULL only for the duration of the system call. */
+            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+
+            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            {
+                /* Extended frame i.e. FPU in use. */
+                ulStackFrameSize = 26;
+                __asm volatile (
+                    " vpush {s0}         \n" /* Trigger lazy stacking. */
+                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                    ::: "memory"
+                    );
+            }
+            else
+            {
+                /* Standard frame i.e. FPU not in use. */
+                ulStackFrameSize = 8;
+            }
+
+            /* Make space on the system call stack for the stack frame. */
+            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulSystemCallStack[ i ] = pulTaskStack[ i ];
+            }
+
+            /* Use the pulSystemCallStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
+
+            /* Raise the privilege for the duration of the system call. */
             __asm volatile (
-                                " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                ::: "memory"
-                           );
+                " mrs r1, control     \n" /* Obtain current control value. */
+                " bic r1, #1          \n" /* Clear nPRIV bit. */
+                " msr control, r1     \n" /* Write back new control value. */
+                ::: "r1", "memory"
+                );
+
+            /* Remember the location where we should copy the stack frame when we exit from
+             * the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+
+            /* Store the value of the Link Register before the SVC was raised. We need to
+             * restore it when we exit from the system call. */
+            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+
+            /* Record if the hardware used padding to force the stack pointer
+             * to be double word aligned. */
+            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
+            {
+                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
+            }
+            else
+            {
+                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
+            }
+
+            /* We ensure in pxPortInitialiseStack that the system call stack is
+             * double word aligned and therefore, there is no need of padding.
+             * Clear the bit[9] of stacked xPSR. */
+            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
         }
-        else
-        {
-            /* Standard frame i.e. FPU not in use. */
-            ulStackFrameSize = 8;
-        }
-
-        /* Make space on the system call stack for the stack frame. */
-        pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulSystemCallStack[ i ] = pulTaskStack[ i ];
-        }
-
-        /* Use the pulSystemCallStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-
-        /* Raise the privilege for the duration of the system call. */
-        __asm volatile (
-                            " mrs r1, control     \n" /* Obtain current control value. */
-                            " bic r1, #1          \n" /* Clear nPRIV bit. */
-                            " msr control, r1     \n" /* Write back new control value. */
-                            ::: "r1", "memory"
-                        );
-
-        /* Remember the location where we should copy the stack frame when we exit from
-         * the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-        /* Store the value of the Link Register before the SVC was raised. We need to
-         * restore it when we exit from the system call. */
-        pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-
-        /* Record if the hardware used padding to force the stack pointer
-         * to be double word aligned. */
-        if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-        {
-            pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-        }
-        else
-        {
-            pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-        }
-
-        /* We ensure in pxPortInitialiseStack that the system call stack is
-         * double word aligned and therefore, there is no need of padding.
-         * Clear the bit[9] of stacked xPSR. */
-        pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
     }
-}
 
 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
 
-void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulSystemCallStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallEnter_1( uint32_t * pulTaskStack,
+                             uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulSystemCallStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        /* This is not NULL only for the duration of the system call. */
-        configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+        #if defined( __ARMCC_VERSION )
 
-        if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            /* Extended frame i.e. FPU in use. */
-            ulStackFrameSize = 26;
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+
+            /* This is not NULL only for the duration of the system call. */
+            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+
+            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            {
+                /* Extended frame i.e. FPU in use. */
+                ulStackFrameSize = 26;
+                __asm volatile (
+                    " vpush {s0}         \n" /* Trigger lazy stacking. */
+                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                    ::: "memory"
+                    );
+            }
+            else
+            {
+                /* Standard frame i.e. FPU not in use. */
+                ulStackFrameSize = 8;
+            }
+
+            /* Make space on the system call stack for the stack frame and
+             * the parameter passed on the stack. We only need to copy one
+             * parameter but we still reserve 2 spaces to keep the stack
+             * double word aligned. */
+            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulSystemCallStack[ i ] = pulTaskStack[ i ];
+            }
+
+            /* Copy the parameter which is passed the stack. */
+            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
+            {
+                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
+
+                /* Record if the hardware used padding to force the stack pointer
+                 * to be double word aligned. */
+                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
+            }
+            else
+            {
+                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
+
+                /* Record if the hardware used padding to force the stack pointer
+                 * to be double word aligned. */
+                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
+            }
+
+            /* Use the pulSystemCallStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
+
+            /* Raise the privilege for the duration of the system call. */
             __asm volatile (
-                                " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                ::: "memory"
-                           );
+                " mrs r1, control     \n" /* Obtain current control value. */
+                " bic r1, #1          \n" /* Clear nPRIV bit. */
+                " msr control, r1     \n" /* Write back new control value. */
+                ::: "r1", "memory"
+                );
+
+            /* Remember the location where we should copy the stack frame when we exit from
+             * the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+
+            /* Store the value of the Link Register before the SVC was raised. We need to
+             * restore it when we exit from the system call. */
+            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+
+            /* We ensure in pxPortInitialiseStack that the system call stack is
+             * double word aligned and therefore, there is no need of padding.
+             * Clear the bit[9] of stacked xPSR. */
+            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
         }
-        else
-        {
-            /* Standard frame i.e. FPU not in use. */
-            ulStackFrameSize = 8;
-        }
-
-        /* Make space on the system call stack for the stack frame and
-         * the parameter passed on the stack. We only need to copy one
-         * parameter but we still reserve 2 spaces to keep the stack
-         * double word aligned. */
-        pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulSystemCallStack[ i ] = pulTaskStack[ i ];
-        }
-
-        /* Copy the parameter which is passed the stack. */
-        if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-        {
-            pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
-            /* Record if the hardware used padding to force the stack pointer
-             * to be double word aligned. */
-            pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-        }
-        else
-        {
-            pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
-            /* Record if the hardware used padding to force the stack pointer
-             * to be double word aligned. */
-            pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-        }
-
-        /* Use the pulSystemCallStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-
-        /* Raise the privilege for the duration of the system call. */
-        __asm volatile (
-                            " mrs r1, control     \n" /* Obtain current control value. */
-                            " bic r1, #1          \n" /* Clear nPRIV bit. */
-                            " msr control, r1     \n" /* Write back new control value. */
-                            ::: "r1", "memory"
-                        );
-
-        /* Remember the location where we should copy the stack frame when we exit from
-         * the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-        /* Store the value of the Link Register before the SVC was raised. We need to
-         * restore it when we exit from the system call. */
-        pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-
-        /* We ensure in pxPortInitialiseStack that the system call stack is
-         * double word aligned and therefore, there is no need of padding.
-         * Clear the bit[9] of stacked xPSR. */
-        pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
     }
-}
 
 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
 
-void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulTaskStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallExit( uint32_t * pulSystemCallStack,
+                          uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulTaskStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+        #if defined( __ARMCC_VERSION )
+
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            /* Extended frame i.e. FPU in use. */
-            ulStackFrameSize = 26;
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
+
+            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            {
+                /* Extended frame i.e. FPU in use. */
+                ulStackFrameSize = 26;
+                __asm volatile (
+                    " vpush {s0}         \n" /* Trigger lazy stacking. */
+                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                    ::: "memory"
+                    );
+            }
+            else
+            {
+                /* Standard frame i.e. FPU not in use. */
+                ulStackFrameSize = 8;
+            }
+
+            /* Make space on the task stack for the stack frame. */
+            pulTaskStack = pulTaskStack - ulStackFrameSize;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulTaskStack[ i ] = pulSystemCallStack[ i ];
+            }
+
+            /* Use the pulTaskStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
+
+            /* Drop the privilege before returning to the thread mode. */
             __asm volatile (
-                                " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                ::: "memory"
-                        );
+                " mrs r1, control     \n" /* Obtain current control value. */
+                " orr r1, #1          \n" /* Set nPRIV bit. */
+                " msr control, r1     \n" /* Write back new control value. */
+                ::: "r1", "memory"
+                );
+
+            /* Restore the stacked link register to what it was at the time of
+             * system call entry. */
+            pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+
+            /* If the hardware used padding to force the stack pointer
+             * to be double word aligned, set the stacked xPSR bit[9],
+             * otherwise clear it. */
+            if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG )
+            {
+                pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK;
+            }
+            else
+            {
+                pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
+            }
+
+            /* This is not NULL only for the duration of the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
         }
-        else
-        {
-            /* Standard frame i.e. FPU not in use. */
-            ulStackFrameSize = 8;
-        }
-
-        /* Make space on the task stack for the stack frame. */
-        pulTaskStack = pulTaskStack - ulStackFrameSize;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulTaskStack[ i ] = pulSystemCallStack[ i ];
-        }
-
-        /* Use the pulTaskStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
-
-        /* Drop the privilege before returning to the thread mode. */
-        __asm volatile (
-                            " mrs r1, control     \n" /* Obtain current control value. */
-                            " orr r1, #1          \n" /* Set nPRIV bit. */
-                            " msr control, r1     \n" /* Write back new control value. */
-                            ::: "r1", "memory"
-                        );
-
-        /* Restore the stacked link register to what it was at the time of
-         * system call entry. */
-        pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
-
-        /* If the hardware used padding to force the stack pointer
-         * to be double word aligned, set the stacked xPSR bit[9],
-         * otherwise clear it. */
-        if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG )
-        {
-            pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK;
-        }
-        else
-        {
-            pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-        }
-
-        /* This is not NULL only for the duration of the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
     }
-}
 
 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
@@ -793,22 +808,22 @@ BaseType_t xPortStartScheduler( void )
         if( ulImplementedPrioBits == 8 )
         {
             /* When the hardware implements 8 priority bits, there is no way for
-            * the software to configure PRIGROUP to not have sub-priorities. As
-            * a result, the least significant bit is always used for sub-priority
-            * and there are 128 preemption priorities and 2 sub-priorities.
-            *
-            * This may cause some confusion in some cases - for example, if
-            * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
-            * priority interrupts will be masked in Critical Sections as those
-            * are at the same preemption priority. This may appear confusing as
-            * 4 is higher (numerically lower) priority than
-            * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
-            * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
-            * to 4, this confusion does not happen and the behaviour remains the same.
-            *
-            * The following assert ensures that the sub-priority bit in the
-            * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
-            * confusion. */
+             * the software to configure PRIGROUP to not have sub-priorities. As
+             * a result, the least significant bit is always used for sub-priority
+             * and there are 128 preemption priorities and 2 sub-priorities.
+             *
+             * This may cause some confusion in some cases - for example, if
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
+             * priority interrupts will be masked in Critical Sections as those
+             * are at the same preemption priority. This may appear confusing as
+             * 4 is higher (numerically lower) priority than
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
+             * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
+             * to 4, this confusion does not happen and the behaviour remains the same.
+             *
+             * The following assert ensures that the sub-priority bit in the
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
+             * confusion. */
             configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
             ulMaxPRIGROUPValue = 0;
         }
@@ -1122,10 +1137,10 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
             ( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |
             ( portMPU_REGION_ENABLE );
 
-          xMPUSettings->xRegionSettings[ 0 ].ulRegionStartAddress = ( uint32_t ) __SRAM_segment_start__;
-          xMPUSettings->xRegionSettings[ 0 ].ulRegionEndAddress = ( uint32_t ) __SRAM_segment_end__;
-          xMPUSettings->xRegionSettings[ 0 ].ulRegionPermissions = ( tskMPU_READ_PERMISSION |
-                                                                     tskMPU_WRITE_PERMISSION );
+        xMPUSettings->xRegionSettings[ 0 ].ulRegionStartAddress = ( uint32_t ) __SRAM_segment_start__;
+        xMPUSettings->xRegionSettings[ 0 ].ulRegionEndAddress = ( uint32_t ) __SRAM_segment_end__;
+        xMPUSettings->xRegionSettings[ 0 ].ulRegionPermissions = ( tskMPU_READ_PERMISSION |
+                                                                   tskMPU_WRITE_PERMISSION );
 
         /* Invalidate user configurable regions. */
         for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
@@ -1163,7 +1178,6 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
                                                                                    ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1UL );
             xMPUSettings->xRegionSettings[ 0 ].ulRegionPermissions = ( tskMPU_READ_PERMISSION |
                                                                        tskMPU_WRITE_PERMISSION );
-
         }
 
         lIndex = 0;
@@ -1185,14 +1199,16 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
                     ( xRegions[ lIndex ].ulParameters ) |
                     ( portMPU_REGION_ENABLE );
 
-                xMPUSettings->xRegionSettings[ ul ].ulRegionStartAddress = ( uint32_t) xRegions[ lIndex ].pvBaseAddress;
+                xMPUSettings->xRegionSettings[ ul ].ulRegionStartAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress;
                 xMPUSettings->xRegionSettings[ ul ].ulRegionEndAddress = ( uint32_t ) ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1UL );
                 xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = 0UL;
+
                 if( ( ( xRegions[ lIndex ].ulParameters & portMPU_REGION_READ_ONLY ) == portMPU_REGION_READ_ONLY ) ||
                     ( ( xRegions[ lIndex ].ulParameters & portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ) == portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ) )
                 {
                     xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = tskMPU_READ_PERMISSION;
                 }
+
                 if( ( xRegions[ lIndex ].ulParameters & portMPU_REGION_READ_WRITE ) == portMPU_REGION_READ_WRITE )
                 {
                     xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = ( tskMPU_READ_PERMISSION | tskMPU_WRITE_PERMISSION );
diff --git a/portable/IAR/ARM_CM4F_MPU/portmacro.h b/portable/IAR/ARM_CM4F_MPU/portmacro.h
index 4be102d6f..799836b95 100644
--- a/portable/IAR/ARM_CM4F_MPU/portmacro.h
+++ b/portable/IAR/ARM_CM4F_MPU/portmacro.h
@@ -65,7 +65,7 @@ typedef unsigned long    UBaseType_t;
 #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
     typedef uint16_t     TickType_t;
     #define portMAX_DELAY              ( TickType_t ) 0xffff
-#elif ( configTICK_TYPE_WIDTH_IN_BITS  == TICK_TYPE_WIDTH_32_BITS )
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
     typedef uint32_t     TickType_t;
     #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
@@ -73,13 +73,13 @@ typedef unsigned long    UBaseType_t;
  * not need to be guarded with a critical section. */
     #define portTICK_TYPE_IS_ATOMIC    1
 #else
-    #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+    #error "configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width."
 #endif
 
 /* Errata 837070 workaround must be enabled on Cortex-M7 r0p0
  * and r0p1 cores. */
 #ifndef configENABLE_ERRATA_837070_WORKAROUND
-    #define configENABLE_ERRATA_837070_WORKAROUND 0
+    #define configENABLE_ERRATA_837070_WORKAROUND    0
 #endif
 /*-----------------------------------------------------------*/
 
@@ -210,7 +210,7 @@ typedef struct MPU_REGION_SETTINGS
 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
 
     #ifndef configSYSTEM_CALL_STACK_SIZE
-        #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
+        #error "configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2."
     #endif
 
     typedef struct SYSTEM_CALL_STACK_INFO
@@ -223,11 +223,11 @@ typedef struct MPU_REGION_SETTINGS
 
 #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
-#define MAX_CONTEXT_SIZE 52
+#define MAX_CONTEXT_SIZE                    52
 
 /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
-#define portSTACK_FRAME_HAS_PADDING_FLAG     ( 1UL << 0UL )
-#define portTASK_IS_PRIVILEGED_FLAG          ( 1UL << 1UL )
+#define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
+#define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
 typedef struct MPU_SETTINGS
 {
@@ -248,16 +248,16 @@ typedef struct MPU_SETTINGS
 /*-----------------------------------------------------------*/
 
 /* SVC numbers for various services. */
-#define portSVC_START_SCHEDULER     0
-#define portSVC_YIELD               1
-#define portSVC_RAISE_PRIVILEGE     2
-#define portSVC_SYSTEM_CALL_ENTER   3   /* System calls with upto 4 parameters. */
-#define portSVC_SYSTEM_CALL_ENTER_1 4   /* System calls with 5 parameters. */
-#define portSVC_SYSTEM_CALL_EXIT    5
+#define portSVC_START_SCHEDULER        0
+#define portSVC_YIELD                  1
+#define portSVC_RAISE_PRIVILEGE        2
+#define portSVC_SYSTEM_CALL_ENTER      3 /* System calls with upto 4 parameters. */
+#define portSVC_SYSTEM_CALL_ENTER_1    4 /* System calls with 5 parameters. */
+#define portSVC_SYSTEM_CALL_EXIT       5
 
 /* Scheduler utilities. */
 
-#define portYIELD()    __asm volatile ( "   SVC %0  \n"::"i" ( portSVC_YIELD ) : "memory" )
+#define portYIELD()    __asm volatile ( "   SVC %0  \n" ::"i" ( portSVC_YIELD ) : "memory" )
 #define portYIELD_WITHIN_API()                          \
     {                                                   \
         /* Set a PendSV to request a context switch. */ \
@@ -268,7 +268,7 @@ typedef struct MPU_SETTINGS
 
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired != pdFALSE ) portYIELD_WITHIN_API(); } while( 0 )
+#define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired != pdFALSE ) portYIELD_WITHIN_API( ); } while( 0 )
 #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
@@ -281,7 +281,7 @@ typedef struct MPU_SETTINGS
 
 /* Check the configuration. */
     #if ( configMAX_PRIORITIES > 32 )
-        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+        #error "configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice."
     #endif
 
 /* Store/clear the ready priorities in a bit map. */
@@ -299,23 +299,23 @@ typedef struct MPU_SETTINGS
 extern void vPortEnterCritical( void );
 extern void vPortExitCritical( void );
 
-#if( configENABLE_ERRATA_837070_WORKAROUND == 1 )
-    #define portDISABLE_INTERRUPTS()                               \
-        {                                                          \
-            __disable_interrupt();                                 \
-            __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \
-            __DSB();                                               \
-            __ISB();                                               \
-            __enable_interrupt();                                  \
-        }
+#if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
+    #define portDISABLE_INTERRUPTS()                           \
+    {                                                          \
+        __disable_interrupt();                                 \
+        __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \
+        __DSB();                                               \
+        __ISB();                                               \
+        __enable_interrupt();                                  \
+    }
 #else
-    #define portDISABLE_INTERRUPTS()                               \
-        {                                                          \
-            __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \
-            __DSB();                                               \
-            __ISB();                                               \
-        }
-#endif
+    #define portDISABLE_INTERRUPTS()                           \
+    {                                                          \
+        __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \
+        __DSB();                                               \
+        __ISB();                                               \
+    }
+#endif /* if ( configENABLE_ERRATA_837070_WORKAROUND == 1 ) */
 
 #define portENABLE_INTERRUPTS()                   __set_BASEPRI( 0 )
 #define portENTER_CRITICAL()                      vPortEnterCritical()
@@ -399,11 +399,11 @@ extern BaseType_t xPortIsTaskPrivileged( void );
  *
  * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
  */
-#define portIS_TASK_PRIVILEGED()      xPortIsTaskPrivileged()
+#define portIS_TASK_PRIVILEGED()    xPortIsTaskPrivileged()
 /*-----------------------------------------------------------*/
 
 #ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY
-    #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. https://www.FreeRTOS.org/FreeRTOS-V10.3.x.html"
+    #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. www.FreeRTOS.org/FreeRTOS-V10.3.x.html"
     #define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY    0
 #endif
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM55/non_secure/port.c b/portable/IAR/ARM_CM55/non_secure/port.c
index 80410e82e..c940c304b 100644
--- a/portable/IAR/ARM_CM55/non_secure/port.c
+++ b/portable/IAR/ARM_CM55/non_secure/port.c
@@ -110,8 +110,8 @@
 /**
  * @brief Constants used during system call enter and exit.
  */
-#define portPSR_STACK_PADDING_MASK                ( 1UL << 9UL )
-#define portEXC_RETURN_STACK_FRAME_TYPE_MASK      ( 1UL << 4UL )
+#define portPSR_STACK_PADDING_MASK              ( 1UL << 9UL )
+#define portEXC_RETURN_STACK_FRAME_TYPE_MASK    ( 1UL << 4UL )
 /*-----------------------------------------------------------*/
 
 /**
@@ -133,81 +133,81 @@
 /**
  * @brief Offsets in the stack to the parameters when inside the SVC handler.
  */
-#define portOFFSET_TO_LR                    ( 5 )
-#define portOFFSET_TO_PC                    ( 6 )
-#define portOFFSET_TO_PSR                   ( 7 )
+#define portOFFSET_TO_LR     ( 5 )
+#define portOFFSET_TO_PC     ( 6 )
+#define portOFFSET_TO_PSR    ( 7 )
 /*-----------------------------------------------------------*/
 
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                      ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                      ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                       ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                      ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                      ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                     ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                     ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK  ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK               ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK               ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK               ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK               ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK               ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK               ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK               ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK               ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0              ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1              ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2              ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3              ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4              ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5              ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6              ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7              ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE            ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT      ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                      ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE             ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -216,11 +216,11 @@
 
 /* Extract last address of the MPU region as encoded in the
  * RLAR (Region Limit Address Register) value. */
-#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar )  \
+#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar ) \
     ( ( ( rlar ) & portMPU_RLAR_ADDRESS_MASK ) | ~portMPU_RLAR_ADDRESS_MASK )
 
 /* Does addr lies within [start, end] address range? */
-#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end )    \
+#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \
     ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) )
 
 /* Is the access request satisfied by the available permissions? */
@@ -422,54 +422,57 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the system call stack so that upon returning from
-     * SVC, the system call stack is used.
-     *
-     * It is used for the system calls with up to 4 parameters.
-     *
-     * @param pulTaskStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the system call stack so that upon returning from
+ * SVC, the system call stack is used.
+ *
+ * It is used for the system calls with up to 4 parameters.
+ *
+ * @param pulTaskStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallEnter( uint32_t * pulTaskStack,
+                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the system call stack so that upon returning from
-     * SVC, the system call stack is used.
-     *
-     * It is used for the system calls with 5 parameters.
-     *
-     * @param pulTaskStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the system call stack so that upon returning from
+ * SVC, the system call stack is used.
+ *
+ * It is used for the system calls with 5 parameters.
+ *
+ * @param pulTaskStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallEnter_1( uint32_t * pulTaskStack,
+                             uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the task stack so that upon returning from
-     * SVC, the task stack is used again.
-     *
-     * @param pulSystemCallStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the task stack so that upon returning from
+ * SVC, the task stack is used again.
+ *
+ * @param pulSystemCallStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallExit( uint32_t * pulSystemCallStack,
+                          uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Checks whether or not the calling task is privileged.
-     *
-     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
-     */
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
     BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
 
 #endif /* configENABLE_MPU == 1 */
@@ -1086,18 +1089,18 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             vRestoreContextOfFirstTask();
             break;
 
-        #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
-            case portSVC_RAISE_PRIVILEGE:
+            #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+                case portSVC_RAISE_PRIVILEGE:
 
-                /* Only raise the privilege, if the svc was raised from any of
-                 * the system calls. */
-                if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
-                    ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
-                {
-                    vRaisePrivilege();
-                }
-                break;
-        #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+                    /* Only raise the privilege, if the svc was raised from any of
+                     * the system calls. */
+                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+                    {
+                        vRaisePrivilege();
+                    }
+                    break;
+            #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
         default:
             /* Incorrect SVC call. */
@@ -1108,513 +1111,526 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulSystemCallStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallEnter( uint32_t * pulTaskStack,
+                           uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulSystemCallStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        /* This is not NULL only for the duration of the system call. */
-        configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+        #if defined( __ARMCC_VERSION )
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+
+            /* This is not NULL only for the duration of the system call. */
+            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the system call stack for the stack frame. */
+            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulSystemCallStack[ i ] = pulTaskStack[ i ];
+            }
+
+            /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
+             * restore it when we exit from the system call. */
+            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* Use the pulSystemCallStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+
+            /* Remember the location where we should copy the stack frame when we exit from
+             * the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+
+            /* Record if the hardware used padding to force the stack pointer
+             * to be double word aligned. */
+            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
+            {
+                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
             }
+
+            /* We ensure in pxPortInitialiseStack that the system call stack is
+             * double word aligned and therefore, there is no need of padding.
+             * Clear the bit[9] of stacked xPSR. */
+            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
+
+            /* Raise the privilege for the duration of the system call. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " bics r0, r1         \n" /* Clear nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the system call stack for the stack frame. */
-        pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulSystemCallStack[ i ] = pulTaskStack[ i ];
-        }
-
-        /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
-         * restore it when we exit from the system call. */
-        pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-        __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* Use the pulSystemCallStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-
-        /* Remember the location where we should copy the stack frame when we exit from
-         * the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-        /* Record if the hardware used padding to force the stack pointer
-         * to be double word aligned. */
-        if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-        {
-            pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-        }
-        else
-        {
-            pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-        }
-
-        /* We ensure in pxPortInitialiseStack that the system call stack is
-         * double word aligned and therefore, there is no need of padding.
-         * Clear the bit[9] of stacked xPSR. */
-        pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-        /* Raise the privilege for the duration of the system call. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " bics r0, r1         \n" /* Clear nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulSystemCallStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallEnter_1( uint32_t * pulTaskStack,
+                             uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulSystemCallStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        /* This is not NULL only for the duration of the system call. */
-        configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+        #if defined( __ARMCC_VERSION )
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+
+            /* This is not NULL only for the duration of the system call. */
+            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the system call stack for the stack frame and
+             * the parameter passed on the stack. We only need to copy one
+             * parameter but we still reserve 2 spaces to keep the stack
+             * double word aligned. */
+            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulSystemCallStack[ i ] = pulTaskStack[ i ];
+            }
+
+            /* Copy the parameter which is passed the stack. */
+            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
+            {
+                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
+
+                /* Record if the hardware used padding to force the stack pointer
+                 * to be double word aligned. */
+                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
+
+                /* Record if the hardware used padding to force the stack pointer
+                 * to be double word aligned. */
+                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
             }
+
+            /* Store the value of the LR and PSPLIM registers before the SVC was raised.
+             * We need to restore it when we exit from the system call. */
+            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* Use the pulSystemCallStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+
+            /* Remember the location where we should copy the stack frame when we exit from
+             * the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+
+            /* We ensure in pxPortInitialiseStack that the system call stack is
+             * double word aligned and therefore, there is no need of padding.
+             * Clear the bit[9] of stacked xPSR. */
+            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
+
+            /* Raise the privilege for the duration of the system call. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " bics r0, r1         \n" /* Clear nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the system call stack for the stack frame and
-         * the parameter passed on the stack. We only need to copy one
-         * parameter but we still reserve 2 spaces to keep the stack
-         * double word aligned. */
-        pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulSystemCallStack[ i ] = pulTaskStack[ i ];
-        }
-
-        /* Copy the parameter which is passed the stack. */
-        if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-        {
-            pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
-            /* Record if the hardware used padding to force the stack pointer
-             * to be double word aligned. */
-            pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-        }
-        else
-        {
-            pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
-            /* Record if the hardware used padding to force the stack pointer
-             * to be double word aligned. */
-            pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-        }
-
-        /* Store the value of the LR and PSPLIM registers before the SVC was raised.
-         * We need to restore it when we exit from the system call. */
-        pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-        __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* Use the pulSystemCallStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-
-        /* Remember the location where we should copy the stack frame when we exit from
-         * the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-        /* We ensure in pxPortInitialiseStack that the system call stack is
-         * double word aligned and therefore, there is no need of padding.
-         * Clear the bit[9] of stacked xPSR. */
-        pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-        /* Raise the privilege for the duration of the system call. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " bics r0, r1         \n" /* Clear nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulTaskStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallExit( uint32_t * pulSystemCallStack,
+                          uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulTaskStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+        #if defined( __ARMCC_VERSION )
+
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the task stack for the stack frame. */
+            pulTaskStack = pulTaskStack - ulStackFrameSize;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulTaskStack[ i ] = pulSystemCallStack[ i ];
+            }
+
+            /* Use the pulTaskStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
+
+            /* Restore the LR and PSPLIM to what they were at the time of
+             * system call entry. */
+            pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* If the hardware used padding to force the stack pointer
+             * to be double word aligned, set the stacked xPSR bit[9],
+             * otherwise clear it. */
+            if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG )
+            {
+                pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
             }
+
+            /* This is not NULL only for the duration of the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
+
+            /* Drop the privilege before returning to the thread mode. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " orrs r0, r1         \n" /* Set nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the task stack for the stack frame. */
-        pulTaskStack = pulTaskStack - ulStackFrameSize;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulTaskStack[ i ] = pulSystemCallStack[ i ];
-        }
-
-        /* Use the pulTaskStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
-
-        /* Restore the LR and PSPLIM to what they were at the time of
-         * system call entry. */
-        pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* If the hardware used padding to force the stack pointer
-         * to be double word aligned, set the stacked xPSR bit[9],
-         * otherwise clear it. */
-        if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG )
-        {
-            pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK;
-        }
-        else
-        {
-            pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-        }
-
-        /* This is not NULL only for the duration of the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
-
-        /* Drop the privilege before returning to the thread mode. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " orrs r0, r1         \n" /* Set nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */
-{
-    BaseType_t xTaskIsPrivileged = pdFALSE;
-    const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
-
-    if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+    BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */
     {
-        xTaskIsPrivileged = pdTRUE;
-    }
+        BaseType_t xTaskIsPrivileged = pdFALSE;
+        const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
 
-    return xTaskIsPrivileged;
-}
+        if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+        {
+            xTaskIsPrivileged = pdTRUE;
+        }
+
+        return xTaskIsPrivileged;
+    }
 
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
-#if( configENABLE_MPU == 1 )
+#if ( configENABLE_MPU == 1 )
 
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     StackType_t * pxEndOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters,
-                                     BaseType_t xRunPrivileged,
-                                     xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
-{
-    uint32_t ulIndex = 0;
-
-    xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
-    ulIndex++;
-
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
-    ulIndex++;
-
-    #if ( configENABLE_TRUSTZONE == 1 )
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters,
+                                         BaseType_t xRunPrivileged,
+                                         xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
     {
-        xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT;  /* xSecureContext. */
+        uint32_t ulIndex = 0;
+
+        xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
         ulIndex++;
-    }
-    #endif /* configENABLE_TRUSTZONE */
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
-    ulIndex++;
-    if( xRunPrivileged == pdTRUE )
-    {
-        xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */
         ulIndex++;
-    }
-    else
-    {
-        xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */
         ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
+        ulIndex++;
+
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters;            /* r0. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x01010101;                           /* r1. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x02020202;                           /* r2. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x03030303;                           /* r3. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x12121212;                           /* r12. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode;                  /* PC. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR;                     /* xPSR. */
+        ulIndex++;
+
+        #if ( configENABLE_TRUSTZONE == 1 )
+        {
+            xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT; /* xSecureContext. */
+            ulIndex++;
+        }
+        #endif /* configENABLE_TRUSTZONE */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
+        ulIndex++;
+
+        if( xRunPrivileged == pdTRUE )
+        {
+            xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
+            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+            ulIndex++;
+        }
+        else
+        {
+            xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
+            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+            ulIndex++;
+        }
+
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
+        ulIndex++;
+
+        #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+        {
+            /* Ensure that the system call stack is double word aligned. */
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] );
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) &
+                                                                                     ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
+
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] );
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) +
+                                                                                            ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) &
+                                                                                          ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
+
+            /* This is not NULL only for the duration of a system call. */
+            xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL;
+        }
+        #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
+
+        return &( xMPUSettings->ulContext[ ulIndex ] );
     }
-    xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
-    ulIndex++;
-
-    #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
-    {
-        /* Ensure that the system call stack is double word aligned. */
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] );
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) &
-                                                                                 ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
-
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] );
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) +
-                                                                                        ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) &
-                                                                                      ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
-
-        /* This is not NULL only for the duration of a system call. */
-        xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL;
-    }
-    #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
-
-    return &( xMPUSettings->ulContext[ ulIndex ] );
-}
 
 #else /* configENABLE_MPU */
 
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     StackType_t * pxEndOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters ) /* PRIVILEGED_FUNCTION */
-{
-    /* Simulate the stack frame as it would be created by a context switch
-     * interrupt. */
-    #if ( portPRELOAD_REGISTERS == 0 )
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters ) /* PRIVILEGED_FUNCTION */
     {
-        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-        pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
-        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-        pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
-        *pxTopOfStack = portINITIAL_EXC_RETURN;
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
-
-        #if ( configENABLE_TRUSTZONE == 1 )
+        /* Simulate the stack frame as it would be created by a context switch
+         * interrupt. */
+        #if ( portPRELOAD_REGISTERS == 0 )
         {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
-        }
-        #endif /* configENABLE_TRUSTZONE */
-    }
-    #else /* portPRELOAD_REGISTERS */
-    {
-        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
-        pxTopOfStack--;
-        *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
+            pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
+            *pxTopOfStack = portINITIAL_EXC_RETURN;
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+            #if ( configENABLE_TRUSTZONE == 1 )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+            }
+            #endif /* configENABLE_TRUSTZONE */
+        }
+        #else /* portPRELOAD_REGISTERS */
         {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
-        }
-        #endif /* configENABLE_TRUSTZONE */
-    }
-    #endif /* portPRELOAD_REGISTERS */
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
+            pxTopOfStack--;
+            *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack;            /* Slot used to hold this task's PSPLIM value. */
 
-    return pxTopOfStack;
-}
+            #if ( configENABLE_TRUSTZONE == 1 )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+            }
+            #endif /* configENABLE_TRUSTZONE */
+        }
+        #endif /* portPRELOAD_REGISTERS */
+
+        return pxTopOfStack;
+    }
 
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM55/non_secure/portmacro.h b/portable/IAR/ARM_CM55/non_secure/portmacro.h
index 10596e8e5..1338d25be 100644
--- a/portable/IAR/ARM_CM55/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM55/non_secure/portmacro.h
@@ -53,16 +53,16 @@
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME                       "Cortex-M55"
-#define portHAS_ARMV8M_MAIN_EXTENSION       1
-#define portDONT_DISCARD                    __root
+#define portARCH_NAME                    "Cortex-M55"
+#define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
 /* ARMv8-M common port configurations. */
 #include "portmacrocommon.h"
 /*-----------------------------------------------------------*/
 
-#if( configTOTAL_MPU_REGIONS == 16 )
+#if ( configTOTAL_MPU_REGIONS == 16 )
     #error 16 MPU regions are not yet supported for this port.
 #endif
 /*-----------------------------------------------------------*/
@@ -70,8 +70,8 @@
 /**
  * @brief Critical section management.
  */
-#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()
-#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )
+#define portDISABLE_INTERRUPTS()    ulSetInterruptMask()
+#define portENABLE_INTERRUPTS()     vClearInterruptMask( 0 )
 /*-----------------------------------------------------------*/
 
 /* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
diff --git a/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h
index e5ffdb48b..62e462a27 100644
--- a/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h
@@ -81,8 +81,8 @@ typedef unsigned long    UBaseType_t;
     typedef uint32_t     TickType_t;
     #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-     * not need to be guarded with a critical section. */
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
     #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -117,7 +117,7 @@ extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGE
 extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
 
 #if ( configENABLE_TRUSTZONE == 1 )
-    extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize );     /* __attribute__ (( naked )) */
+    extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
     extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
 #endif /* configENABLE_TRUSTZONE */
 
@@ -188,13 +188,13 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Settings to define an MPU region.
-     */
+/**
+ * @brief Settings to define an MPU region.
+ */
     typedef struct MPURegionSettings
     {
-        uint32_t ulRBAR;     /**< RBAR for the region. */
-        uint32_t ulRLAR;     /**< RLAR for the region. */
+        uint32_t ulRBAR; /**< RBAR for the region. */
+        uint32_t ulRLAR; /**< RLAR for the region. */
     } MPURegionSettings_t;
 
     #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
@@ -203,9 +203,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-        /**
-         * @brief System call stack.
-         */
+/**
+ * @brief System call stack.
+ */
         typedef struct SYSTEM_CALL_STACK_INFO
         {
             uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ];
@@ -218,74 +218,74 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
-    /**
-     * @brief MPU settings as stored in the TCB.
-     */
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
     #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
 
-        #if( configENABLE_TRUSTZONE == 1 )
+        #if ( configENABLE_TRUSTZONE == 1 )
 
-            /*
-             * +-----------+---------------+----------+-----------------+------------------------------+-----+
-             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
-             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
-             * +-----------+---------------+----------+-----------------+------------------------------+-----+
-             *
-             * <-----------><--------------><---------><----------------><-----------------------------><---->
-             *      16             16            8               8                     5                   1
-             */
-            #define MAX_CONTEXT_SIZE 54
+/*
+ * +-----------+---------------+----------+-----------------+------------------------------+-----+
+ * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+ * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+ * +-----------+---------------+----------+-----------------+------------------------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><-----------------------------><---->
+ *      16             16            8               8                     5                   1
+ */
+            #define MAX_CONTEXT_SIZE    54
 
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-            /*
-             * +-----------+---------------+----------+-----------------+----------------------+-----+
-             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
-             * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
-             * +-----------+---------------+----------+-----------------+----------------------+-----+
-             *
-             * <-----------><--------------><---------><----------------><---------------------><---->
-             *      16             16            8               8                  4              1
-             */
-            #define MAX_CONTEXT_SIZE 53
+/*
+ * +-----------+---------------+----------+-----------------+----------------------+-----+
+ * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+ * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
+ * +-----------+---------------+----------+-----------------+----------------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><---------------------><---->
+ *      16             16            8               8                  4              1
+ */
+            #define MAX_CONTEXT_SIZE    53
 
         #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
 
     #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-        #if( configENABLE_TRUSTZONE == 1 )
+        #if ( configENABLE_TRUSTZONE == 1 )
 
-            /*
-             * +----------+-----------------+------------------------------+-----+
-             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
-             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
-             * +----------+-----------------+------------------------------+-----+
-             *
-             * <---------><----------------><------------------------------><---->
-             *     8               8                      5                   1
-             */
-            #define MAX_CONTEXT_SIZE 22
+/*
+ * +----------+-----------------+------------------------------+-----+
+ * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+ * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+ * +----------+-----------------+------------------------------+-----+
+ *
+ * <---------><----------------><------------------------------><---->
+ *     8               8                      5                   1
+ */
+            #define MAX_CONTEXT_SIZE    22
 
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-            /*
-             * +----------+-----------------+----------------------+-----+
-             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
-             * |          | PC, xPSR        | EXC_RETURN           |     |
-             * +----------+-----------------+----------------------+-----+
-             *
-             * <---------><----------------><----------------------><---->
-             *     8               8                  4              1
-             */
-            #define MAX_CONTEXT_SIZE 21
+/*
+ * +----------+-----------------+----------------------+-----+
+ * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+ * |          | PC, xPSR        | EXC_RETURN           |     |
+ * +----------+-----------------+----------------------+-----+
+ *
+ * <---------><----------------><----------------------><---->
+ *     8               8                  4              1
+ */
+            #define MAX_CONTEXT_SIZE    21
 
         #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
 
     #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-    /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
-    #define portSTACK_FRAME_HAS_PADDING_FLAG     ( 1UL << 0UL )
-    #define portTASK_IS_PRIVILEGED_FLAG          ( 1UL << 1UL )
+/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
+    #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
+    #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
     typedef struct MPU_SETTINGS
     {
@@ -364,49 +364,49 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-    /**
-     * @brief Allocate a secure context for the task.
-     *
-     * Tasks are not created with a secure context. Any task that is going to call
-     * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
-     * secure context before it calls any secure function.
-     *
-     * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
-     */
+/**
+ * @brief Allocate a secure context for the task.
+ *
+ * Tasks are not created with a secure context. Any task that is going to call
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+ * secure context before it calls any secure function.
+ *
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+ */
     #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
 
-    /**
-     * @brief Called when a task is deleted to delete the task's secure context,
-     * if it has one.
-     *
-     * @param[in] pxTCB The TCB of the task being deleted.
-     */
+/**
+ * @brief Called when a task is deleted to delete the task's secure context,
+ * if it has one.
+ *
+ * @param[in] pxTCB The TCB of the task being deleted.
+ */
     #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
 #endif /* configENABLE_TRUSTZONE */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Checks whether or not the processor is privileged.
-     *
-     * @return 1 if the processor is already privileged, 0 otherwise.
-     */
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
     #define portIS_PRIVILEGED()      xIsPrivileged()
 
-    /**
-     * @brief Raise an SVC request to raise privilege.
-     *
-     * The SVC handler checks that the SVC was raised from a system call and only
-     * then it raises the privilege. If this is called from any other place,
-     * the privilege is not raised.
-     */
+/**
+ * @brief Raise an SVC request to raise privilege.
+ *
+ * The SVC handler checks that the SVC was raised from a system call and only
+ * then it raises the privilege. If this is called from any other place,
+ * the privilege is not raised.
+ */
     #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
 
-    /**
-     * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
-     * register.
-     */
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
     #define portRESET_PRIVILEGE()    vResetPrivilege()
 #else
     #define portIS_PRIVILEGED()
@@ -419,12 +419,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     extern BaseType_t xPortIsTaskPrivileged( void );
 
-    /**
-     * @brief Checks whether or not the calling task is privileged.
-     *
-     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
-     */
-    #define portIS_TASK_PRIVILEGED()      xPortIsTaskPrivileged()
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
+    #define portIS_TASK_PRIVILEGED()    xPortIsTaskPrivileged()
 
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
@@ -439,9 +439,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * based on whether or not Mainline extension is implemented. */
 #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
     #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
-        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
     #else
-        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    0
     #endif
 #endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
 
@@ -450,9 +450,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  */
 #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
 
-    /**
-     * @brief Count the number of leading zeros in a 32-bit value.
-     */
+/**
+ * @brief Count the number of leading zeros in a 32-bit value.
+ */
     static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
     {
         uint32_t ulReturn;
@@ -462,7 +462,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         return ulReturn;
     }
 
-    /* Check the configuration. */
+/* Check the configuration. */
     #if ( configMAX_PRIORITIES > 32 )
         #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
     #endif
@@ -471,16 +471,16 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection.  Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
     #endif
 
-    /**
-     * @brief Store/clear the ready priorities in a bit map.
-     */
-    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+/**
+ * @brief Store/clear the ready priorities in a bit map.
+ */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )      ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )       ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 
-    /**
-     * @brief Get the priority of the highest-priority task that is ready to execute.
-     */
-    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )   uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+/**
+ * @brief Get the priority of the highest-priority task that is ready to execute.
+ */
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
 
 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM55/secure/secure_context.c b/portable/IAR/ARM_CM55/secure/secure_context.c
index 0730d574d..7d2171996 100644
--- a/portable/IAR/ARM_CM55/secure/secure_context.c
+++ b/portable/IAR/ARM_CM55/secure/secure_context.c
@@ -65,7 +65,7 @@
  * @brief Maximum number of secure contexts.
  */
 #ifndef secureconfigMAX_SECURE_CONTEXTS
-    #define secureconfigMAX_SECURE_CONTEXTS        8UL
+    #define secureconfigMAX_SECURE_CONTEXTS    8UL
 #endif
 /*-----------------------------------------------------------*/
 
@@ -164,15 +164,15 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
         }
 
         #if ( configENABLE_MPU == 1 )
-            {
-                /* Configure thread mode to use PSP and to be unprivileged. */
-                secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
-            }
+        {
+            /* Configure thread mode to use PSP and to be unprivileged. */
+            secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
+        }
         #else /* configENABLE_MPU */
-            {
-                /* Configure thread mode to use PSP and to be privileged. */
-                secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
-            }
+        {
+            /* Configure thread mode to use PSP and to be privileged. */
+            secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
+        }
         #endif /* configENABLE_MPU */
     }
 }
@@ -219,16 +219,16 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
             if( pucStackMemory != NULL )
             {
                 /* Since stack grows down, the starting point will be the last
-                 * location. Note that this location is next to the last
-                 * allocated byte for stack (excluding the space for seal values)
-                 * because the hardware decrements the stack pointer before
-                 * writing i.e. if stack pointer is 0x2, a push operation will
-                 * decrement the stack pointer to 0x1 and then write at 0x1. */
+                * location. Note that this location is next to the last
+                * allocated byte for stack (excluding the space for seal values)
+                * because the hardware decrements the stack pointer before
+                * writing i.e. if stack pointer is 0x2, a push operation will
+                * decrement the stack pointer to 0x1 and then write at 0x1. */
                 xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize;
 
                 /* Seal the created secure process stack. */
-                *( uint32_t * )( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE;
-                *( uint32_t * )( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE;
+                *( uint32_t * ) ( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE;
+                *( uint32_t * ) ( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE;
 
                 /* The stack cannot go beyond this location. This value is
                  * programmed in the PSPLIM register on context switch.*/
@@ -237,32 +237,32 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
                 xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle;
 
                 #if ( configENABLE_MPU == 1 )
+                {
+                    /* Store the correct CONTROL value for the task on the stack.
+                     * This value is programmed in the CONTROL register on
+                     * context switch. */
+                    pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart;
+                    pulCurrentStackPointer--;
+
+                    if( ulIsTaskPrivileged )
                     {
-                        /* Store the correct CONTROL value for the task on the stack.
-                         * This value is programmed in the CONTROL register on
-                         * context switch. */
-                        pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart;
-                        pulCurrentStackPointer--;
-
-                        if( ulIsTaskPrivileged )
-                        {
-                            *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
-                        }
-                        else
-                        {
-                            *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
-                        }
-
-                        /* Store the current stack pointer. This value is programmed in
-                         * the PSP register on context switch. */
-                        xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+                        *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
                     }
+                    else
+                    {
+                        *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
+                    }
+
+                    /* Store the current stack pointer. This value is programmed in
+                     * the PSP register on context switch. */
+                    xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+                }
                 #else /* configENABLE_MPU */
-                    {
-                        /* Current SP is set to the starting of the stack. This
-                         * value programmed in the PSP register on context switch. */
-                        xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart;
-                    }
+                {
+                    /* Current SP is set to the starting of the stack. This
+                     * value programmed in the PSP register on context switch. */
+                    xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart;
+                }
                 #endif /* configENABLE_MPU */
 
                 /* Ensure to never return 0 as a valid context handle. */
@@ -275,7 +275,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
 }
 /*-----------------------------------------------------------*/
 
-secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle,
+                                                              void * pvTaskHandle )
 {
     uint32_t ulIPSR, ulSecureContextIndex;
 
@@ -306,7 +307,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandl
 }
 /*-----------------------------------------------------------*/
 
-secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle,
+                                                              void * pvTaskHandle )
 {
     uint8_t * pucStackLimit;
     uint32_t ulSecureContextIndex;
@@ -328,7 +330,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandl
 }
 /*-----------------------------------------------------------*/
 
-secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle,
+                                                              void * pvTaskHandle )
 {
     uint8_t * pucStackLimit;
     uint32_t ulSecureContextIndex;
diff --git a/portable/IAR/ARM_CM55/secure/secure_context.h b/portable/IAR/ARM_CM55/secure/secure_context.h
index d0adbaf01..0bf776198 100644
--- a/portable/IAR/ARM_CM55/secure/secure_context.h
+++ b/portable/IAR/ARM_CM55/secure/secure_context.h
@@ -38,12 +38,12 @@
 /**
  * @brief PSP value when no secure context is loaded.
  */
-#define securecontextNO_STACK               0x0
+#define securecontextNO_STACK              0x0
 
 /**
  * @brief Invalid context ID.
  */
-#define securecontextINVALID_CONTEXT_ID     0UL
+#define securecontextINVALID_CONTEXT_ID    0UL
 /*-----------------------------------------------------------*/
 
 /**
@@ -108,7 +108,8 @@ void SecureContext_Init( void );
  * @param[in] xSecureContextHandle Context handle corresponding to the
  * context to be freed.
  */
-void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle,
+                                void * pvTaskHandle );
 
 /**
  * @brief Loads the given context.
@@ -119,7 +120,8 @@ void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void
  * @param[in] xSecureContextHandle Context handle corresponding to the context
  * to be loaded.
  */
-void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle,
+                                void * pvTaskHandle );
 
 /**
  * @brief Saves the given context.
@@ -130,6 +132,7 @@ void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void
  * @param[in] xSecureContextHandle Context handle corresponding to the context
  * to be saved.
  */
-void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle,
+                                void * pvTaskHandle );
 
 #endif /* __SECURE_CONTEXT_H__ */
diff --git a/portable/IAR/ARM_CM55/secure/secure_heap.c b/portable/IAR/ARM_CM55/secure/secure_heap.c
index f3b80df54..1ec3bdbdb 100644
--- a/portable/IAR/ARM_CM55/secure/secure_heap.c
+++ b/portable/IAR/ARM_CM55/secure/secure_heap.c
@@ -67,7 +67,7 @@
 #define secureheapSIZE_MAX              ( ~( ( size_t ) 0 ) )
 
 /* Check if adding a and b will result in overflow. */
-#define secureheapADD_WILL_OVERFLOW( a, b )         ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) )
+#define secureheapADD_WILL_OVERFLOW( a, b )    ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) )
 
 /* MSB of the xBlockSize member of an BlockLink_t structure is used to track
  * the allocation status of a block.  When MSB of the xBlockSize member of
@@ -397,17 +397,17 @@ void * pvPortMalloc( size_t xWantedSize )
     traceMALLOC( pvReturn, xWantedSize );
 
     #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
+    {
+        if( pvReturn == NULL )
         {
-            if( pvReturn == NULL )
-            {
-                extern void vApplicationMallocFailedHook( void );
-                vApplicationMallocFailedHook();
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
+            extern void vApplicationMallocFailedHook( void );
+            vApplicationMallocFailedHook();
         }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
     #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */
 
     secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );
diff --git a/portable/IAR/ARM_CM55/secure/secure_init.c b/portable/IAR/ARM_CM55/secure/secure_init.c
index dc19ebc7d..b89c5f644 100644
--- a/portable/IAR/ARM_CM55/secure/secure_init.c
+++ b/portable/IAR/ARM_CM55/secure/secure_init.c
@@ -93,7 +93,7 @@ secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )
          * permitted. CP11 should be programmed to the same value as CP10. */
         *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
 
-        /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
+        /* LSPENS = 0 ==> LSPEN is writable from non-secure state. This ensures
          * that we can enable/disable lazy stacking in port.c file. */
         *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK );
 
diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/port.c b/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
index 80410e82e..c940c304b 100644
--- a/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
@@ -110,8 +110,8 @@
 /**
  * @brief Constants used during system call enter and exit.
  */
-#define portPSR_STACK_PADDING_MASK                ( 1UL << 9UL )
-#define portEXC_RETURN_STACK_FRAME_TYPE_MASK      ( 1UL << 4UL )
+#define portPSR_STACK_PADDING_MASK              ( 1UL << 9UL )
+#define portEXC_RETURN_STACK_FRAME_TYPE_MASK    ( 1UL << 4UL )
 /*-----------------------------------------------------------*/
 
 /**
@@ -133,81 +133,81 @@
 /**
  * @brief Offsets in the stack to the parameters when inside the SVC handler.
  */
-#define portOFFSET_TO_LR                    ( 5 )
-#define portOFFSET_TO_PC                    ( 6 )
-#define portOFFSET_TO_PSR                   ( 7 )
+#define portOFFSET_TO_LR     ( 5 )
+#define portOFFSET_TO_PC     ( 6 )
+#define portOFFSET_TO_PSR    ( 7 )
 /*-----------------------------------------------------------*/
 
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                      ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                      ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                       ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                      ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                      ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                     ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                     ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK  ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK               ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK               ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK               ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK               ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK               ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK               ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK               ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK               ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0              ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1              ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2              ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3              ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4              ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5              ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6              ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7              ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE            ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT      ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                      ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE             ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -216,11 +216,11 @@
 
 /* Extract last address of the MPU region as encoded in the
  * RLAR (Region Limit Address Register) value. */
-#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar )  \
+#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar ) \
     ( ( ( rlar ) & portMPU_RLAR_ADDRESS_MASK ) | ~portMPU_RLAR_ADDRESS_MASK )
 
 /* Does addr lies within [start, end] address range? */
-#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end )    \
+#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \
     ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) )
 
 /* Is the access request satisfied by the available permissions? */
@@ -422,54 +422,57 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the system call stack so that upon returning from
-     * SVC, the system call stack is used.
-     *
-     * It is used for the system calls with up to 4 parameters.
-     *
-     * @param pulTaskStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the system call stack so that upon returning from
+ * SVC, the system call stack is used.
+ *
+ * It is used for the system calls with up to 4 parameters.
+ *
+ * @param pulTaskStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallEnter( uint32_t * pulTaskStack,
+                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the system call stack so that upon returning from
-     * SVC, the system call stack is used.
-     *
-     * It is used for the system calls with 5 parameters.
-     *
-     * @param pulTaskStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the system call stack so that upon returning from
+ * SVC, the system call stack is used.
+ *
+ * It is used for the system calls with 5 parameters.
+ *
+ * @param pulTaskStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallEnter_1( uint32_t * pulTaskStack,
+                             uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the task stack so that upon returning from
-     * SVC, the task stack is used again.
-     *
-     * @param pulSystemCallStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the task stack so that upon returning from
+ * SVC, the task stack is used again.
+ *
+ * @param pulSystemCallStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallExit( uint32_t * pulSystemCallStack,
+                          uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Checks whether or not the calling task is privileged.
-     *
-     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
-     */
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
     BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
 
 #endif /* configENABLE_MPU == 1 */
@@ -1086,18 +1089,18 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             vRestoreContextOfFirstTask();
             break;
 
-        #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
-            case portSVC_RAISE_PRIVILEGE:
+            #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+                case portSVC_RAISE_PRIVILEGE:
 
-                /* Only raise the privilege, if the svc was raised from any of
-                 * the system calls. */
-                if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
-                    ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
-                {
-                    vRaisePrivilege();
-                }
-                break;
-        #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+                    /* Only raise the privilege, if the svc was raised from any of
+                     * the system calls. */
+                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+                    {
+                        vRaisePrivilege();
+                    }
+                    break;
+            #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
         default:
             /* Incorrect SVC call. */
@@ -1108,513 +1111,526 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulSystemCallStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallEnter( uint32_t * pulTaskStack,
+                           uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulSystemCallStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        /* This is not NULL only for the duration of the system call. */
-        configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+        #if defined( __ARMCC_VERSION )
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+
+            /* This is not NULL only for the duration of the system call. */
+            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the system call stack for the stack frame. */
+            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulSystemCallStack[ i ] = pulTaskStack[ i ];
+            }
+
+            /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
+             * restore it when we exit from the system call. */
+            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* Use the pulSystemCallStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+
+            /* Remember the location where we should copy the stack frame when we exit from
+             * the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+
+            /* Record if the hardware used padding to force the stack pointer
+             * to be double word aligned. */
+            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
+            {
+                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
             }
+
+            /* We ensure in pxPortInitialiseStack that the system call stack is
+             * double word aligned and therefore, there is no need of padding.
+             * Clear the bit[9] of stacked xPSR. */
+            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
+
+            /* Raise the privilege for the duration of the system call. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " bics r0, r1         \n" /* Clear nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the system call stack for the stack frame. */
-        pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulSystemCallStack[ i ] = pulTaskStack[ i ];
-        }
-
-        /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
-         * restore it when we exit from the system call. */
-        pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-        __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* Use the pulSystemCallStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-
-        /* Remember the location where we should copy the stack frame when we exit from
-         * the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-        /* Record if the hardware used padding to force the stack pointer
-         * to be double word aligned. */
-        if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-        {
-            pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-        }
-        else
-        {
-            pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-        }
-
-        /* We ensure in pxPortInitialiseStack that the system call stack is
-         * double word aligned and therefore, there is no need of padding.
-         * Clear the bit[9] of stacked xPSR. */
-        pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-        /* Raise the privilege for the duration of the system call. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " bics r0, r1         \n" /* Clear nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulSystemCallStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallEnter_1( uint32_t * pulTaskStack,
+                             uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulSystemCallStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        /* This is not NULL only for the duration of the system call. */
-        configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+        #if defined( __ARMCC_VERSION )
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+
+            /* This is not NULL only for the duration of the system call. */
+            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the system call stack for the stack frame and
+             * the parameter passed on the stack. We only need to copy one
+             * parameter but we still reserve 2 spaces to keep the stack
+             * double word aligned. */
+            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulSystemCallStack[ i ] = pulTaskStack[ i ];
+            }
+
+            /* Copy the parameter which is passed the stack. */
+            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
+            {
+                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
+
+                /* Record if the hardware used padding to force the stack pointer
+                 * to be double word aligned. */
+                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
+
+                /* Record if the hardware used padding to force the stack pointer
+                 * to be double word aligned. */
+                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
             }
+
+            /* Store the value of the LR and PSPLIM registers before the SVC was raised.
+             * We need to restore it when we exit from the system call. */
+            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* Use the pulSystemCallStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+
+            /* Remember the location where we should copy the stack frame when we exit from
+             * the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+
+            /* We ensure in pxPortInitialiseStack that the system call stack is
+             * double word aligned and therefore, there is no need of padding.
+             * Clear the bit[9] of stacked xPSR. */
+            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
+
+            /* Raise the privilege for the duration of the system call. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " bics r0, r1         \n" /* Clear nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the system call stack for the stack frame and
-         * the parameter passed on the stack. We only need to copy one
-         * parameter but we still reserve 2 spaces to keep the stack
-         * double word aligned. */
-        pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulSystemCallStack[ i ] = pulTaskStack[ i ];
-        }
-
-        /* Copy the parameter which is passed the stack. */
-        if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-        {
-            pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
-            /* Record if the hardware used padding to force the stack pointer
-             * to be double word aligned. */
-            pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-        }
-        else
-        {
-            pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
-            /* Record if the hardware used padding to force the stack pointer
-             * to be double word aligned. */
-            pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-        }
-
-        /* Store the value of the LR and PSPLIM registers before the SVC was raised.
-         * We need to restore it when we exit from the system call. */
-        pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-        __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* Use the pulSystemCallStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-
-        /* Remember the location where we should copy the stack frame when we exit from
-         * the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-        /* We ensure in pxPortInitialiseStack that the system call stack is
-         * double word aligned and therefore, there is no need of padding.
-         * Clear the bit[9] of stacked xPSR. */
-        pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-        /* Raise the privilege for the duration of the system call. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " bics r0, r1         \n" /* Clear nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulTaskStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallExit( uint32_t * pulSystemCallStack,
+                          uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulTaskStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+        #if defined( __ARMCC_VERSION )
+
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the task stack for the stack frame. */
+            pulTaskStack = pulTaskStack - ulStackFrameSize;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulTaskStack[ i ] = pulSystemCallStack[ i ];
+            }
+
+            /* Use the pulTaskStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
+
+            /* Restore the LR and PSPLIM to what they were at the time of
+             * system call entry. */
+            pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* If the hardware used padding to force the stack pointer
+             * to be double word aligned, set the stacked xPSR bit[9],
+             * otherwise clear it. */
+            if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG )
+            {
+                pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
             }
+
+            /* This is not NULL only for the duration of the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
+
+            /* Drop the privilege before returning to the thread mode. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " orrs r0, r1         \n" /* Set nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the task stack for the stack frame. */
-        pulTaskStack = pulTaskStack - ulStackFrameSize;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulTaskStack[ i ] = pulSystemCallStack[ i ];
-        }
-
-        /* Use the pulTaskStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
-
-        /* Restore the LR and PSPLIM to what they were at the time of
-         * system call entry. */
-        pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* If the hardware used padding to force the stack pointer
-         * to be double word aligned, set the stacked xPSR bit[9],
-         * otherwise clear it. */
-        if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG )
-        {
-            pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK;
-        }
-        else
-        {
-            pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-        }
-
-        /* This is not NULL only for the duration of the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
-
-        /* Drop the privilege before returning to the thread mode. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " orrs r0, r1         \n" /* Set nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */
-{
-    BaseType_t xTaskIsPrivileged = pdFALSE;
-    const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
-
-    if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+    BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */
     {
-        xTaskIsPrivileged = pdTRUE;
-    }
+        BaseType_t xTaskIsPrivileged = pdFALSE;
+        const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
 
-    return xTaskIsPrivileged;
-}
+        if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+        {
+            xTaskIsPrivileged = pdTRUE;
+        }
+
+        return xTaskIsPrivileged;
+    }
 
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
-#if( configENABLE_MPU == 1 )
+#if ( configENABLE_MPU == 1 )
 
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     StackType_t * pxEndOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters,
-                                     BaseType_t xRunPrivileged,
-                                     xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
-{
-    uint32_t ulIndex = 0;
-
-    xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
-    ulIndex++;
-
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
-    ulIndex++;
-
-    #if ( configENABLE_TRUSTZONE == 1 )
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters,
+                                         BaseType_t xRunPrivileged,
+                                         xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
     {
-        xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT;  /* xSecureContext. */
+        uint32_t ulIndex = 0;
+
+        xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
         ulIndex++;
-    }
-    #endif /* configENABLE_TRUSTZONE */
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
-    ulIndex++;
-    if( xRunPrivileged == pdTRUE )
-    {
-        xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */
         ulIndex++;
-    }
-    else
-    {
-        xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */
         ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
+        ulIndex++;
+
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters;            /* r0. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x01010101;                           /* r1. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x02020202;                           /* r2. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x03030303;                           /* r3. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x12121212;                           /* r12. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode;                  /* PC. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR;                     /* xPSR. */
+        ulIndex++;
+
+        #if ( configENABLE_TRUSTZONE == 1 )
+        {
+            xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT; /* xSecureContext. */
+            ulIndex++;
+        }
+        #endif /* configENABLE_TRUSTZONE */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
+        ulIndex++;
+
+        if( xRunPrivileged == pdTRUE )
+        {
+            xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
+            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+            ulIndex++;
+        }
+        else
+        {
+            xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
+            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+            ulIndex++;
+        }
+
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
+        ulIndex++;
+
+        #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+        {
+            /* Ensure that the system call stack is double word aligned. */
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] );
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) &
+                                                                                     ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
+
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] );
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) +
+                                                                                            ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) &
+                                                                                          ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
+
+            /* This is not NULL only for the duration of a system call. */
+            xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL;
+        }
+        #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
+
+        return &( xMPUSettings->ulContext[ ulIndex ] );
     }
-    xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
-    ulIndex++;
-
-    #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
-    {
-        /* Ensure that the system call stack is double word aligned. */
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] );
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) &
-                                                                                 ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
-
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] );
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) +
-                                                                                        ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) &
-                                                                                      ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
-
-        /* This is not NULL only for the duration of a system call. */
-        xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL;
-    }
-    #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
-
-    return &( xMPUSettings->ulContext[ ulIndex ] );
-}
 
 #else /* configENABLE_MPU */
 
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     StackType_t * pxEndOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters ) /* PRIVILEGED_FUNCTION */
-{
-    /* Simulate the stack frame as it would be created by a context switch
-     * interrupt. */
-    #if ( portPRELOAD_REGISTERS == 0 )
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters ) /* PRIVILEGED_FUNCTION */
     {
-        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-        pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
-        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-        pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
-        *pxTopOfStack = portINITIAL_EXC_RETURN;
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
-
-        #if ( configENABLE_TRUSTZONE == 1 )
+        /* Simulate the stack frame as it would be created by a context switch
+         * interrupt. */
+        #if ( portPRELOAD_REGISTERS == 0 )
         {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
-        }
-        #endif /* configENABLE_TRUSTZONE */
-    }
-    #else /* portPRELOAD_REGISTERS */
-    {
-        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
-        pxTopOfStack--;
-        *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
+            pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
+            *pxTopOfStack = portINITIAL_EXC_RETURN;
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+            #if ( configENABLE_TRUSTZONE == 1 )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+            }
+            #endif /* configENABLE_TRUSTZONE */
+        }
+        #else /* portPRELOAD_REGISTERS */
         {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
-        }
-        #endif /* configENABLE_TRUSTZONE */
-    }
-    #endif /* portPRELOAD_REGISTERS */
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
+            pxTopOfStack--;
+            *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack;            /* Slot used to hold this task's PSPLIM value. */
 
-    return pxTopOfStack;
-}
+            #if ( configENABLE_TRUSTZONE == 1 )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+            }
+            #endif /* configENABLE_TRUSTZONE */
+        }
+        #endif /* portPRELOAD_REGISTERS */
+
+        return pxTopOfStack;
+    }
 
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/portmacro.h b/portable/IAR/ARM_CM55_NTZ/non_secure/portmacro.h
index 10596e8e5..1338d25be 100644
--- a/portable/IAR/ARM_CM55_NTZ/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM55_NTZ/non_secure/portmacro.h
@@ -53,16 +53,16 @@
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME                       "Cortex-M55"
-#define portHAS_ARMV8M_MAIN_EXTENSION       1
-#define portDONT_DISCARD                    __root
+#define portARCH_NAME                    "Cortex-M55"
+#define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
 /* ARMv8-M common port configurations. */
 #include "portmacrocommon.h"
 /*-----------------------------------------------------------*/
 
-#if( configTOTAL_MPU_REGIONS == 16 )
+#if ( configTOTAL_MPU_REGIONS == 16 )
     #error 16 MPU regions are not yet supported for this port.
 #endif
 /*-----------------------------------------------------------*/
@@ -70,8 +70,8 @@
 /**
  * @brief Critical section management.
  */
-#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()
-#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )
+#define portDISABLE_INTERRUPTS()    ulSetInterruptMask()
+#define portENABLE_INTERRUPTS()     vClearInterruptMask( 0 )
 /*-----------------------------------------------------------*/
 
 /* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h
index e5ffdb48b..62e462a27 100644
--- a/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h
@@ -81,8 +81,8 @@ typedef unsigned long    UBaseType_t;
     typedef uint32_t     TickType_t;
     #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-     * not need to be guarded with a critical section. */
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
     #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -117,7 +117,7 @@ extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGE
 extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
 
 #if ( configENABLE_TRUSTZONE == 1 )
-    extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize );     /* __attribute__ (( naked )) */
+    extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
     extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
 #endif /* configENABLE_TRUSTZONE */
 
@@ -188,13 +188,13 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Settings to define an MPU region.
-     */
+/**
+ * @brief Settings to define an MPU region.
+ */
     typedef struct MPURegionSettings
     {
-        uint32_t ulRBAR;     /**< RBAR for the region. */
-        uint32_t ulRLAR;     /**< RLAR for the region. */
+        uint32_t ulRBAR; /**< RBAR for the region. */
+        uint32_t ulRLAR; /**< RLAR for the region. */
     } MPURegionSettings_t;
 
     #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
@@ -203,9 +203,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-        /**
-         * @brief System call stack.
-         */
+/**
+ * @brief System call stack.
+ */
         typedef struct SYSTEM_CALL_STACK_INFO
         {
             uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ];
@@ -218,74 +218,74 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
-    /**
-     * @brief MPU settings as stored in the TCB.
-     */
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
     #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
 
-        #if( configENABLE_TRUSTZONE == 1 )
+        #if ( configENABLE_TRUSTZONE == 1 )
 
-            /*
-             * +-----------+---------------+----------+-----------------+------------------------------+-----+
-             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
-             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
-             * +-----------+---------------+----------+-----------------+------------------------------+-----+
-             *
-             * <-----------><--------------><---------><----------------><-----------------------------><---->
-             *      16             16            8               8                     5                   1
-             */
-            #define MAX_CONTEXT_SIZE 54
+/*
+ * +-----------+---------------+----------+-----------------+------------------------------+-----+
+ * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+ * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+ * +-----------+---------------+----------+-----------------+------------------------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><-----------------------------><---->
+ *      16             16            8               8                     5                   1
+ */
+            #define MAX_CONTEXT_SIZE    54
 
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-            /*
-             * +-----------+---------------+----------+-----------------+----------------------+-----+
-             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
-             * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
-             * +-----------+---------------+----------+-----------------+----------------------+-----+
-             *
-             * <-----------><--------------><---------><----------------><---------------------><---->
-             *      16             16            8               8                  4              1
-             */
-            #define MAX_CONTEXT_SIZE 53
+/*
+ * +-----------+---------------+----------+-----------------+----------------------+-----+
+ * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+ * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
+ * +-----------+---------------+----------+-----------------+----------------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><---------------------><---->
+ *      16             16            8               8                  4              1
+ */
+            #define MAX_CONTEXT_SIZE    53
 
         #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
 
     #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-        #if( configENABLE_TRUSTZONE == 1 )
+        #if ( configENABLE_TRUSTZONE == 1 )
 
-            /*
-             * +----------+-----------------+------------------------------+-----+
-             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
-             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
-             * +----------+-----------------+------------------------------+-----+
-             *
-             * <---------><----------------><------------------------------><---->
-             *     8               8                      5                   1
-             */
-            #define MAX_CONTEXT_SIZE 22
+/*
+ * +----------+-----------------+------------------------------+-----+
+ * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+ * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+ * +----------+-----------------+------------------------------+-----+
+ *
+ * <---------><----------------><------------------------------><---->
+ *     8               8                      5                   1
+ */
+            #define MAX_CONTEXT_SIZE    22
 
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-            /*
-             * +----------+-----------------+----------------------+-----+
-             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
-             * |          | PC, xPSR        | EXC_RETURN           |     |
-             * +----------+-----------------+----------------------+-----+
-             *
-             * <---------><----------------><----------------------><---->
-             *     8               8                  4              1
-             */
-            #define MAX_CONTEXT_SIZE 21
+/*
+ * +----------+-----------------+----------------------+-----+
+ * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+ * |          | PC, xPSR        | EXC_RETURN           |     |
+ * +----------+-----------------+----------------------+-----+
+ *
+ * <---------><----------------><----------------------><---->
+ *     8               8                  4              1
+ */
+            #define MAX_CONTEXT_SIZE    21
 
         #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
 
     #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-    /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
-    #define portSTACK_FRAME_HAS_PADDING_FLAG     ( 1UL << 0UL )
-    #define portTASK_IS_PRIVILEGED_FLAG          ( 1UL << 1UL )
+/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
+    #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
+    #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
     typedef struct MPU_SETTINGS
     {
@@ -364,49 +364,49 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-    /**
-     * @brief Allocate a secure context for the task.
-     *
-     * Tasks are not created with a secure context. Any task that is going to call
-     * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
-     * secure context before it calls any secure function.
-     *
-     * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
-     */
+/**
+ * @brief Allocate a secure context for the task.
+ *
+ * Tasks are not created with a secure context. Any task that is going to call
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+ * secure context before it calls any secure function.
+ *
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+ */
     #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
 
-    /**
-     * @brief Called when a task is deleted to delete the task's secure context,
-     * if it has one.
-     *
-     * @param[in] pxTCB The TCB of the task being deleted.
-     */
+/**
+ * @brief Called when a task is deleted to delete the task's secure context,
+ * if it has one.
+ *
+ * @param[in] pxTCB The TCB of the task being deleted.
+ */
     #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
 #endif /* configENABLE_TRUSTZONE */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Checks whether or not the processor is privileged.
-     *
-     * @return 1 if the processor is already privileged, 0 otherwise.
-     */
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
     #define portIS_PRIVILEGED()      xIsPrivileged()
 
-    /**
-     * @brief Raise an SVC request to raise privilege.
-     *
-     * The SVC handler checks that the SVC was raised from a system call and only
-     * then it raises the privilege. If this is called from any other place,
-     * the privilege is not raised.
-     */
+/**
+ * @brief Raise an SVC request to raise privilege.
+ *
+ * The SVC handler checks that the SVC was raised from a system call and only
+ * then it raises the privilege. If this is called from any other place,
+ * the privilege is not raised.
+ */
     #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
 
-    /**
-     * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
-     * register.
-     */
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
     #define portRESET_PRIVILEGE()    vResetPrivilege()
 #else
     #define portIS_PRIVILEGED()
@@ -419,12 +419,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     extern BaseType_t xPortIsTaskPrivileged( void );
 
-    /**
-     * @brief Checks whether or not the calling task is privileged.
-     *
-     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
-     */
-    #define portIS_TASK_PRIVILEGED()      xPortIsTaskPrivileged()
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
+    #define portIS_TASK_PRIVILEGED()    xPortIsTaskPrivileged()
 
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
@@ -439,9 +439,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * based on whether or not Mainline extension is implemented. */
 #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
     #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
-        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
     #else
-        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    0
     #endif
 #endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
 
@@ -450,9 +450,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  */
 #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
 
-    /**
-     * @brief Count the number of leading zeros in a 32-bit value.
-     */
+/**
+ * @brief Count the number of leading zeros in a 32-bit value.
+ */
     static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
     {
         uint32_t ulReturn;
@@ -462,7 +462,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         return ulReturn;
     }
 
-    /* Check the configuration. */
+/* Check the configuration. */
     #if ( configMAX_PRIORITIES > 32 )
         #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
     #endif
@@ -471,16 +471,16 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection.  Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
     #endif
 
-    /**
-     * @brief Store/clear the ready priorities in a bit map.
-     */
-    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+/**
+ * @brief Store/clear the ready priorities in a bit map.
+ */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )      ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )       ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 
-    /**
-     * @brief Get the priority of the highest-priority task that is ready to execute.
-     */
-    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )   uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+/**
+ * @brief Get the priority of the highest-priority task that is ready to execute.
+ */
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
 
 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM7/r0p1/port.c b/portable/IAR/ARM_CM7/r0p1/port.c
old mode 100755
new mode 100644
index fa26a9404..6d2c122d1
--- a/portable/IAR/ARM_CM7/r0p1/port.c
+++ b/portable/IAR/ARM_CM7/r0p1/port.c
@@ -283,22 +283,22 @@ BaseType_t xPortStartScheduler( void )
         if( ulImplementedPrioBits == 8 )
         {
             /* When the hardware implements 8 priority bits, there is no way for
-            * the software to configure PRIGROUP to not have sub-priorities. As
-            * a result, the least significant bit is always used for sub-priority
-            * and there are 128 preemption priorities and 2 sub-priorities.
-            *
-            * This may cause some confusion in some cases - for example, if
-            * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
-            * priority interrupts will be masked in Critical Sections as those
-            * are at the same preemption priority. This may appear confusing as
-            * 4 is higher (numerically lower) priority than
-            * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
-            * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
-            * to 4, this confusion does not happen and the behaviour remains the same.
-            *
-            * The following assert ensures that the sub-priority bit in the
-            * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
-            * confusion. */
+             * the software to configure PRIGROUP to not have sub-priorities. As
+             * a result, the least significant bit is always used for sub-priority
+             * and there are 128 preemption priorities and 2 sub-priorities.
+             *
+             * This may cause some confusion in some cases - for example, if
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
+             * priority interrupts will be masked in Critical Sections as those
+             * are at the same preemption priority. This may appear confusing as
+             * 4 is higher (numerically lower) priority than
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
+             * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
+             * to 4, this confusion does not happen and the behaviour remains the same.
+             *
+             * The following assert ensures that the sub-priority bit in the
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
+             * confusion. */
             configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
             ulMaxPRIGROUPValue = 0;
         }
diff --git a/portable/IAR/ARM_CM7/r0p1/portmacro.h b/portable/IAR/ARM_CM7/r0p1/portmacro.h
index a2a2d8788..5f1c0488c 100644
--- a/portable/IAR/ARM_CM7/r0p1/portmacro.h
+++ b/portable/IAR/ARM_CM7/r0p1/portmacro.h
@@ -27,7 +27,7 @@
  */
 
 #ifndef PORTMACRO_H
-    #define PORTMACRO_H
+#define PORTMACRO_H
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
@@ -46,50 +46,50 @@
  */
 
 /* IAR includes. */
-    #include <intrinsics.h>
+#include <intrinsics.h>
 
 /* Type definitions. */
-    #define portCHAR          char
-    #define portFLOAT         float
-    #define portDOUBLE        double
-    #define portLONG          long
-    #define portSHORT         short
-    #define portSTACK_TYPE    uint32_t
-    #define portBASE_TYPE     long
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-    typedef portSTACK_TYPE   StackType_t;
-    typedef long             BaseType_t;
-    typedef unsigned long    UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
-    #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-        typedef uint16_t     TickType_t;
-        #define portMAX_DELAY              ( TickType_t ) 0xffff
-    #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-        typedef uint32_t     TickType_t;
-        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
  * not need to be guarded with a critical section. */
-        #define portTICK_TYPE_IS_ATOMIC    1
-    #else
-        #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
-    #endif
+    #define portTICK_TYPE_IS_ATOMIC    1
+#else
+    #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+#endif
 /*-----------------------------------------------------------*/
 
 /* Architecture specifics. */
-    #define portSTACK_GROWTH      ( -1 )
-    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-    #define portBYTE_ALIGNMENT    8
+#define portSTACK_GROWTH      ( -1 )
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT    8
 /*-----------------------------------------------------------*/
 
 /* Compiler directives. */
-    #define portWEAK_SYMBOL    __attribute__( ( weak ) )
+#define portWEAK_SYMBOL    __attribute__( ( weak ) )
 
 /*-----------------------------------------------------------*/
 
 
 /* Scheduler utilities. */
-    #define portYIELD()                                 \
+#define portYIELD()                                     \
     {                                                   \
         /* Set a PendSV to request a context switch. */ \
         portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
@@ -97,41 +97,41 @@
         __ISB();                                        \
     }
 
-    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
-    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-    #define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 )
-    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+#define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired != pdFALSE ) portYIELD( ); } while( 0 )
+#define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
 
 /*-----------------------------------------------------------*/
 
 /* Architecture specific optimisations. */
-    #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
-    #endif
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+    #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
+#endif
 
-    #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
 
 /* Check the configuration. */
-        #if ( configMAX_PRIORITIES > 32 )
-            #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
-        #endif
+    #if ( configMAX_PRIORITIES > 32 )
+        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+    #endif
 
 /* Store/clear the ready priorities in a bit map. */
-        #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-        #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 
 /*-----------------------------------------------------------*/
 
-        #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ( ( uint32_t ) __CLZ( ( uxReadyPriorities ) ) ) )
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ( ( uint32_t ) __CLZ( ( uxReadyPriorities ) ) ) )
 
-    #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 /*-----------------------------------------------------------*/
 
 /* Critical section management. */
-    extern void vPortEnterCritical( void );
-    extern void vPortExitCritical( void );
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
 
-    #define portDISABLE_INTERRUPTS()                           \
+#define portDISABLE_INTERRUPTS()                               \
     {                                                          \
         /* Errata work around. */                              \
         __disable_interrupt();                                 \
@@ -141,71 +141,71 @@
         __enable_interrupt();                                  \
     }
 
-    #define portENABLE_INTERRUPTS()                   __set_BASEPRI( 0 )
-    #define portENTER_CRITICAL()                      vPortEnterCritical()
-    #define portEXIT_CRITICAL()                       vPortExitCritical()
-    #define portSET_INTERRUPT_MASK_FROM_ISR()         __get_BASEPRI(); portDISABLE_INTERRUPTS()
-    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    __set_BASEPRI( x )
+#define portENABLE_INTERRUPTS()                   __set_BASEPRI( 0 )
+#define portENTER_CRITICAL()                      vPortEnterCritical()
+#define portEXIT_CRITICAL()                       vPortExitCritical()
+#define portSET_INTERRUPT_MASK_FROM_ISR()         __get_BASEPRI(); portDISABLE_INTERRUPTS()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    __set_BASEPRI( x )
 /*-----------------------------------------------------------*/
 
 /* Tickless idle/low power functionality. */
-    #ifndef portSUPPRESS_TICKS_AND_SLEEP
-        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
-        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
-    #endif
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+    extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+    #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site.  These are
  * not necessary for to use this port.  They are defined so the common demo files
  * (which build with all the ports) will build. */
-    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
-    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 /*-----------------------------------------------------------*/
 
-    #ifdef configASSERT
-        void vPortValidateInterruptPriority( void );
-        #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
-    #endif
+#ifdef configASSERT
+    void vPortValidateInterruptPriority( void );
+    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
+#endif
 
 /* portNOP() is not required by this port. */
-    #define portNOP()
+#define portNOP()
 
-    #define portINLINE              __inline
+#define portINLINE              __inline
 
-    #ifndef portFORCE_INLINE
-        #define portFORCE_INLINE    inline __attribute__( ( always_inline ) )
-    #endif
+#ifndef portFORCE_INLINE
+    #define portFORCE_INLINE    inline __attribute__( ( always_inline ) )
+#endif
 
 /*-----------------------------------------------------------*/
 
-    portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
+portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
+{
+    uint32_t ulCurrentInterrupt;
+    BaseType_t xReturn;
+
+    /* Obtain the number of the currently executing interrupt. */
+    __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+    if( ulCurrentInterrupt == 0 )
     {
-        uint32_t ulCurrentInterrupt;
-        BaseType_t xReturn;
-
-        /* Obtain the number of the currently executing interrupt. */
-        __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
-
-        if( ulCurrentInterrupt == 0 )
-        {
-            xReturn = pdFALSE;
-        }
-        else
-        {
-            xReturn = pdTRUE;
-        }
-
-        return xReturn;
+        xReturn = pdFALSE;
     }
+    else
+    {
+        xReturn = pdTRUE;
+    }
+
+    return xReturn;
+}
 
 /*-----------------------------------------------------------*/
 
 /* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
  * the source code because to do so would cause other compilers to generate
  * warnings. */
-    #pragma diag_suppress=Pe191
-    #pragma diag_suppress=Pa082
+#pragma diag_suppress=Pe191
+#pragma diag_suppress=Pa082
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/IAR/ARM_CM85/non_secure/port.c b/portable/IAR/ARM_CM85/non_secure/port.c
index 80410e82e..c940c304b 100644
--- a/portable/IAR/ARM_CM85/non_secure/port.c
+++ b/portable/IAR/ARM_CM85/non_secure/port.c
@@ -110,8 +110,8 @@
 /**
  * @brief Constants used during system call enter and exit.
  */
-#define portPSR_STACK_PADDING_MASK                ( 1UL << 9UL )
-#define portEXC_RETURN_STACK_FRAME_TYPE_MASK      ( 1UL << 4UL )
+#define portPSR_STACK_PADDING_MASK              ( 1UL << 9UL )
+#define portEXC_RETURN_STACK_FRAME_TYPE_MASK    ( 1UL << 4UL )
 /*-----------------------------------------------------------*/
 
 /**
@@ -133,81 +133,81 @@
 /**
  * @brief Offsets in the stack to the parameters when inside the SVC handler.
  */
-#define portOFFSET_TO_LR                    ( 5 )
-#define portOFFSET_TO_PC                    ( 6 )
-#define portOFFSET_TO_PSR                   ( 7 )
+#define portOFFSET_TO_LR     ( 5 )
+#define portOFFSET_TO_PC     ( 6 )
+#define portOFFSET_TO_PSR    ( 7 )
 /*-----------------------------------------------------------*/
 
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                      ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                      ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                       ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                      ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                      ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                     ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                     ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK  ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK               ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK               ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK               ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK               ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK               ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK               ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK               ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK               ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0              ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1              ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2              ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3              ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4              ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5              ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6              ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7              ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE            ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT      ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                      ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE             ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -216,11 +216,11 @@
 
 /* Extract last address of the MPU region as encoded in the
  * RLAR (Region Limit Address Register) value. */
-#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar )  \
+#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar ) \
     ( ( ( rlar ) & portMPU_RLAR_ADDRESS_MASK ) | ~portMPU_RLAR_ADDRESS_MASK )
 
 /* Does addr lies within [start, end] address range? */
-#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end )    \
+#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \
     ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) )
 
 /* Is the access request satisfied by the available permissions? */
@@ -422,54 +422,57 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the system call stack so that upon returning from
-     * SVC, the system call stack is used.
-     *
-     * It is used for the system calls with up to 4 parameters.
-     *
-     * @param pulTaskStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the system call stack so that upon returning from
+ * SVC, the system call stack is used.
+ *
+ * It is used for the system calls with up to 4 parameters.
+ *
+ * @param pulTaskStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallEnter( uint32_t * pulTaskStack,
+                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the system call stack so that upon returning from
-     * SVC, the system call stack is used.
-     *
-     * It is used for the system calls with 5 parameters.
-     *
-     * @param pulTaskStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the system call stack so that upon returning from
+ * SVC, the system call stack is used.
+ *
+ * It is used for the system calls with 5 parameters.
+ *
+ * @param pulTaskStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallEnter_1( uint32_t * pulTaskStack,
+                             uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the task stack so that upon returning from
-     * SVC, the task stack is used again.
-     *
-     * @param pulSystemCallStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the task stack so that upon returning from
+ * SVC, the task stack is used again.
+ *
+ * @param pulSystemCallStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallExit( uint32_t * pulSystemCallStack,
+                          uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Checks whether or not the calling task is privileged.
-     *
-     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
-     */
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
     BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
 
 #endif /* configENABLE_MPU == 1 */
@@ -1086,18 +1089,18 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             vRestoreContextOfFirstTask();
             break;
 
-        #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
-            case portSVC_RAISE_PRIVILEGE:
+            #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+                case portSVC_RAISE_PRIVILEGE:
 
-                /* Only raise the privilege, if the svc was raised from any of
-                 * the system calls. */
-                if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
-                    ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
-                {
-                    vRaisePrivilege();
-                }
-                break;
-        #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+                    /* Only raise the privilege, if the svc was raised from any of
+                     * the system calls. */
+                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+                    {
+                        vRaisePrivilege();
+                    }
+                    break;
+            #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
         default:
             /* Incorrect SVC call. */
@@ -1108,513 +1111,526 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulSystemCallStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallEnter( uint32_t * pulTaskStack,
+                           uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulSystemCallStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        /* This is not NULL only for the duration of the system call. */
-        configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+        #if defined( __ARMCC_VERSION )
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+
+            /* This is not NULL only for the duration of the system call. */
+            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the system call stack for the stack frame. */
+            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulSystemCallStack[ i ] = pulTaskStack[ i ];
+            }
+
+            /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
+             * restore it when we exit from the system call. */
+            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* Use the pulSystemCallStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+
+            /* Remember the location where we should copy the stack frame when we exit from
+             * the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+
+            /* Record if the hardware used padding to force the stack pointer
+             * to be double word aligned. */
+            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
+            {
+                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
             }
+
+            /* We ensure in pxPortInitialiseStack that the system call stack is
+             * double word aligned and therefore, there is no need of padding.
+             * Clear the bit[9] of stacked xPSR. */
+            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
+
+            /* Raise the privilege for the duration of the system call. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " bics r0, r1         \n" /* Clear nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the system call stack for the stack frame. */
-        pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulSystemCallStack[ i ] = pulTaskStack[ i ];
-        }
-
-        /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
-         * restore it when we exit from the system call. */
-        pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-        __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* Use the pulSystemCallStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-
-        /* Remember the location where we should copy the stack frame when we exit from
-         * the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-        /* Record if the hardware used padding to force the stack pointer
-         * to be double word aligned. */
-        if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-        {
-            pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-        }
-        else
-        {
-            pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-        }
-
-        /* We ensure in pxPortInitialiseStack that the system call stack is
-         * double word aligned and therefore, there is no need of padding.
-         * Clear the bit[9] of stacked xPSR. */
-        pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-        /* Raise the privilege for the duration of the system call. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " bics r0, r1         \n" /* Clear nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulSystemCallStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallEnter_1( uint32_t * pulTaskStack,
+                             uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulSystemCallStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        /* This is not NULL only for the duration of the system call. */
-        configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+        #if defined( __ARMCC_VERSION )
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+
+            /* This is not NULL only for the duration of the system call. */
+            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the system call stack for the stack frame and
+             * the parameter passed on the stack. We only need to copy one
+             * parameter but we still reserve 2 spaces to keep the stack
+             * double word aligned. */
+            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulSystemCallStack[ i ] = pulTaskStack[ i ];
+            }
+
+            /* Copy the parameter which is passed the stack. */
+            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
+            {
+                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
+
+                /* Record if the hardware used padding to force the stack pointer
+                 * to be double word aligned. */
+                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
+
+                /* Record if the hardware used padding to force the stack pointer
+                 * to be double word aligned. */
+                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
             }
+
+            /* Store the value of the LR and PSPLIM registers before the SVC was raised.
+             * We need to restore it when we exit from the system call. */
+            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* Use the pulSystemCallStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+
+            /* Remember the location where we should copy the stack frame when we exit from
+             * the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+
+            /* We ensure in pxPortInitialiseStack that the system call stack is
+             * double word aligned and therefore, there is no need of padding.
+             * Clear the bit[9] of stacked xPSR. */
+            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
+
+            /* Raise the privilege for the duration of the system call. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " bics r0, r1         \n" /* Clear nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the system call stack for the stack frame and
-         * the parameter passed on the stack. We only need to copy one
-         * parameter but we still reserve 2 spaces to keep the stack
-         * double word aligned. */
-        pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulSystemCallStack[ i ] = pulTaskStack[ i ];
-        }
-
-        /* Copy the parameter which is passed the stack. */
-        if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-        {
-            pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
-            /* Record if the hardware used padding to force the stack pointer
-             * to be double word aligned. */
-            pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-        }
-        else
-        {
-            pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
-            /* Record if the hardware used padding to force the stack pointer
-             * to be double word aligned. */
-            pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-        }
-
-        /* Store the value of the LR and PSPLIM registers before the SVC was raised.
-         * We need to restore it when we exit from the system call. */
-        pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-        __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* Use the pulSystemCallStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-
-        /* Remember the location where we should copy the stack frame when we exit from
-         * the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-        /* We ensure in pxPortInitialiseStack that the system call stack is
-         * double word aligned and therefore, there is no need of padding.
-         * Clear the bit[9] of stacked xPSR. */
-        pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-        /* Raise the privilege for the duration of the system call. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " bics r0, r1         \n" /* Clear nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulTaskStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallExit( uint32_t * pulSystemCallStack,
+                          uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulTaskStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+        #if defined( __ARMCC_VERSION )
+
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the task stack for the stack frame. */
+            pulTaskStack = pulTaskStack - ulStackFrameSize;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulTaskStack[ i ] = pulSystemCallStack[ i ];
+            }
+
+            /* Use the pulTaskStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
+
+            /* Restore the LR and PSPLIM to what they were at the time of
+             * system call entry. */
+            pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* If the hardware used padding to force the stack pointer
+             * to be double word aligned, set the stacked xPSR bit[9],
+             * otherwise clear it. */
+            if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG )
+            {
+                pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
             }
+
+            /* This is not NULL only for the duration of the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
+
+            /* Drop the privilege before returning to the thread mode. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " orrs r0, r1         \n" /* Set nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the task stack for the stack frame. */
-        pulTaskStack = pulTaskStack - ulStackFrameSize;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulTaskStack[ i ] = pulSystemCallStack[ i ];
-        }
-
-        /* Use the pulTaskStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
-
-        /* Restore the LR and PSPLIM to what they were at the time of
-         * system call entry. */
-        pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* If the hardware used padding to force the stack pointer
-         * to be double word aligned, set the stacked xPSR bit[9],
-         * otherwise clear it. */
-        if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG )
-        {
-            pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK;
-        }
-        else
-        {
-            pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-        }
-
-        /* This is not NULL only for the duration of the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
-
-        /* Drop the privilege before returning to the thread mode. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " orrs r0, r1         \n" /* Set nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */
-{
-    BaseType_t xTaskIsPrivileged = pdFALSE;
-    const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
-
-    if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+    BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */
     {
-        xTaskIsPrivileged = pdTRUE;
-    }
+        BaseType_t xTaskIsPrivileged = pdFALSE;
+        const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
 
-    return xTaskIsPrivileged;
-}
+        if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+        {
+            xTaskIsPrivileged = pdTRUE;
+        }
+
+        return xTaskIsPrivileged;
+    }
 
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
-#if( configENABLE_MPU == 1 )
+#if ( configENABLE_MPU == 1 )
 
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     StackType_t * pxEndOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters,
-                                     BaseType_t xRunPrivileged,
-                                     xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
-{
-    uint32_t ulIndex = 0;
-
-    xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
-    ulIndex++;
-
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
-    ulIndex++;
-
-    #if ( configENABLE_TRUSTZONE == 1 )
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters,
+                                         BaseType_t xRunPrivileged,
+                                         xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
     {
-        xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT;  /* xSecureContext. */
+        uint32_t ulIndex = 0;
+
+        xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
         ulIndex++;
-    }
-    #endif /* configENABLE_TRUSTZONE */
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
-    ulIndex++;
-    if( xRunPrivileged == pdTRUE )
-    {
-        xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */
         ulIndex++;
-    }
-    else
-    {
-        xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */
         ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
+        ulIndex++;
+
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters;            /* r0. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x01010101;                           /* r1. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x02020202;                           /* r2. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x03030303;                           /* r3. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x12121212;                           /* r12. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode;                  /* PC. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR;                     /* xPSR. */
+        ulIndex++;
+
+        #if ( configENABLE_TRUSTZONE == 1 )
+        {
+            xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT; /* xSecureContext. */
+            ulIndex++;
+        }
+        #endif /* configENABLE_TRUSTZONE */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
+        ulIndex++;
+
+        if( xRunPrivileged == pdTRUE )
+        {
+            xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
+            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+            ulIndex++;
+        }
+        else
+        {
+            xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
+            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+            ulIndex++;
+        }
+
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
+        ulIndex++;
+
+        #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+        {
+            /* Ensure that the system call stack is double word aligned. */
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] );
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) &
+                                                                                     ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
+
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] );
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) +
+                                                                                            ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) &
+                                                                                          ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
+
+            /* This is not NULL only for the duration of a system call. */
+            xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL;
+        }
+        #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
+
+        return &( xMPUSettings->ulContext[ ulIndex ] );
     }
-    xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
-    ulIndex++;
-
-    #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
-    {
-        /* Ensure that the system call stack is double word aligned. */
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] );
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) &
-                                                                                 ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
-
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] );
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) +
-                                                                                        ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) &
-                                                                                      ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
-
-        /* This is not NULL only for the duration of a system call. */
-        xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL;
-    }
-    #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
-
-    return &( xMPUSettings->ulContext[ ulIndex ] );
-}
 
 #else /* configENABLE_MPU */
 
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     StackType_t * pxEndOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters ) /* PRIVILEGED_FUNCTION */
-{
-    /* Simulate the stack frame as it would be created by a context switch
-     * interrupt. */
-    #if ( portPRELOAD_REGISTERS == 0 )
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters ) /* PRIVILEGED_FUNCTION */
     {
-        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-        pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
-        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-        pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
-        *pxTopOfStack = portINITIAL_EXC_RETURN;
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
-
-        #if ( configENABLE_TRUSTZONE == 1 )
+        /* Simulate the stack frame as it would be created by a context switch
+         * interrupt. */
+        #if ( portPRELOAD_REGISTERS == 0 )
         {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
-        }
-        #endif /* configENABLE_TRUSTZONE */
-    }
-    #else /* portPRELOAD_REGISTERS */
-    {
-        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
-        pxTopOfStack--;
-        *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
+            pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
+            *pxTopOfStack = portINITIAL_EXC_RETURN;
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+            #if ( configENABLE_TRUSTZONE == 1 )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+            }
+            #endif /* configENABLE_TRUSTZONE */
+        }
+        #else /* portPRELOAD_REGISTERS */
         {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
-        }
-        #endif /* configENABLE_TRUSTZONE */
-    }
-    #endif /* portPRELOAD_REGISTERS */
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
+            pxTopOfStack--;
+            *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack;            /* Slot used to hold this task's PSPLIM value. */
 
-    return pxTopOfStack;
-}
+            #if ( configENABLE_TRUSTZONE == 1 )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+            }
+            #endif /* configENABLE_TRUSTZONE */
+        }
+        #endif /* portPRELOAD_REGISTERS */
+
+        return pxTopOfStack;
+    }
 
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM85/non_secure/portmacro.h b/portable/IAR/ARM_CM85/non_secure/portmacro.h
index 374150262..cffcb20d9 100644
--- a/portable/IAR/ARM_CM85/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM85/non_secure/portmacro.h
@@ -53,16 +53,16 @@
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME                       "Cortex-M85"
-#define portHAS_ARMV8M_MAIN_EXTENSION       1
-#define portDONT_DISCARD                    __root
+#define portARCH_NAME                    "Cortex-M85"
+#define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
 /* ARMv8-M common port configurations. */
 #include "portmacrocommon.h"
 /*-----------------------------------------------------------*/
 
-#if( configTOTAL_MPU_REGIONS == 16 )
+#if ( configTOTAL_MPU_REGIONS == 16 )
     #error 16 MPU regions are not yet supported for this port.
 #endif
 /*-----------------------------------------------------------*/
@@ -70,8 +70,8 @@
 /**
  * @brief Critical section management.
  */
-#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()
-#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )
+#define portDISABLE_INTERRUPTS()    ulSetInterruptMask()
+#define portENABLE_INTERRUPTS()     vClearInterruptMask( 0 )
 /*-----------------------------------------------------------*/
 
 /* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
diff --git a/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h
index e5ffdb48b..62e462a27 100644
--- a/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h
@@ -81,8 +81,8 @@ typedef unsigned long    UBaseType_t;
     typedef uint32_t     TickType_t;
     #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-     * not need to be guarded with a critical section. */
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
     #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -117,7 +117,7 @@ extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGE
 extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
 
 #if ( configENABLE_TRUSTZONE == 1 )
-    extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize );     /* __attribute__ (( naked )) */
+    extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
     extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
 #endif /* configENABLE_TRUSTZONE */
 
@@ -188,13 +188,13 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Settings to define an MPU region.
-     */
+/**
+ * @brief Settings to define an MPU region.
+ */
     typedef struct MPURegionSettings
     {
-        uint32_t ulRBAR;     /**< RBAR for the region. */
-        uint32_t ulRLAR;     /**< RLAR for the region. */
+        uint32_t ulRBAR; /**< RBAR for the region. */
+        uint32_t ulRLAR; /**< RLAR for the region. */
     } MPURegionSettings_t;
 
     #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
@@ -203,9 +203,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-        /**
-         * @brief System call stack.
-         */
+/**
+ * @brief System call stack.
+ */
         typedef struct SYSTEM_CALL_STACK_INFO
         {
             uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ];
@@ -218,74 +218,74 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
-    /**
-     * @brief MPU settings as stored in the TCB.
-     */
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
     #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
 
-        #if( configENABLE_TRUSTZONE == 1 )
+        #if ( configENABLE_TRUSTZONE == 1 )
 
-            /*
-             * +-----------+---------------+----------+-----------------+------------------------------+-----+
-             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
-             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
-             * +-----------+---------------+----------+-----------------+------------------------------+-----+
-             *
-             * <-----------><--------------><---------><----------------><-----------------------------><---->
-             *      16             16            8               8                     5                   1
-             */
-            #define MAX_CONTEXT_SIZE 54
+/*
+ * +-----------+---------------+----------+-----------------+------------------------------+-----+
+ * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+ * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+ * +-----------+---------------+----------+-----------------+------------------------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><-----------------------------><---->
+ *      16             16            8               8                     5                   1
+ */
+            #define MAX_CONTEXT_SIZE    54
 
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-            /*
-             * +-----------+---------------+----------+-----------------+----------------------+-----+
-             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
-             * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
-             * +-----------+---------------+----------+-----------------+----------------------+-----+
-             *
-             * <-----------><--------------><---------><----------------><---------------------><---->
-             *      16             16            8               8                  4              1
-             */
-            #define MAX_CONTEXT_SIZE 53
+/*
+ * +-----------+---------------+----------+-----------------+----------------------+-----+
+ * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+ * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
+ * +-----------+---------------+----------+-----------------+----------------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><---------------------><---->
+ *      16             16            8               8                  4              1
+ */
+            #define MAX_CONTEXT_SIZE    53
 
         #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
 
     #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-        #if( configENABLE_TRUSTZONE == 1 )
+        #if ( configENABLE_TRUSTZONE == 1 )
 
-            /*
-             * +----------+-----------------+------------------------------+-----+
-             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
-             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
-             * +----------+-----------------+------------------------------+-----+
-             *
-             * <---------><----------------><------------------------------><---->
-             *     8               8                      5                   1
-             */
-            #define MAX_CONTEXT_SIZE 22
+/*
+ * +----------+-----------------+------------------------------+-----+
+ * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+ * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+ * +----------+-----------------+------------------------------+-----+
+ *
+ * <---------><----------------><------------------------------><---->
+ *     8               8                      5                   1
+ */
+            #define MAX_CONTEXT_SIZE    22
 
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-            /*
-             * +----------+-----------------+----------------------+-----+
-             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
-             * |          | PC, xPSR        | EXC_RETURN           |     |
-             * +----------+-----------------+----------------------+-----+
-             *
-             * <---------><----------------><----------------------><---->
-             *     8               8                  4              1
-             */
-            #define MAX_CONTEXT_SIZE 21
+/*
+ * +----------+-----------------+----------------------+-----+
+ * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+ * |          | PC, xPSR        | EXC_RETURN           |     |
+ * +----------+-----------------+----------------------+-----+
+ *
+ * <---------><----------------><----------------------><---->
+ *     8               8                  4              1
+ */
+            #define MAX_CONTEXT_SIZE    21
 
         #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
 
     #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-    /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
-    #define portSTACK_FRAME_HAS_PADDING_FLAG     ( 1UL << 0UL )
-    #define portTASK_IS_PRIVILEGED_FLAG          ( 1UL << 1UL )
+/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
+    #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
+    #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
     typedef struct MPU_SETTINGS
     {
@@ -364,49 +364,49 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-    /**
-     * @brief Allocate a secure context for the task.
-     *
-     * Tasks are not created with a secure context. Any task that is going to call
-     * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
-     * secure context before it calls any secure function.
-     *
-     * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
-     */
+/**
+ * @brief Allocate a secure context for the task.
+ *
+ * Tasks are not created with a secure context. Any task that is going to call
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+ * secure context before it calls any secure function.
+ *
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+ */
     #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
 
-    /**
-     * @brief Called when a task is deleted to delete the task's secure context,
-     * if it has one.
-     *
-     * @param[in] pxTCB The TCB of the task being deleted.
-     */
+/**
+ * @brief Called when a task is deleted to delete the task's secure context,
+ * if it has one.
+ *
+ * @param[in] pxTCB The TCB of the task being deleted.
+ */
     #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
 #endif /* configENABLE_TRUSTZONE */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Checks whether or not the processor is privileged.
-     *
-     * @return 1 if the processor is already privileged, 0 otherwise.
-     */
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
     #define portIS_PRIVILEGED()      xIsPrivileged()
 
-    /**
-     * @brief Raise an SVC request to raise privilege.
-     *
-     * The SVC handler checks that the SVC was raised from a system call and only
-     * then it raises the privilege. If this is called from any other place,
-     * the privilege is not raised.
-     */
+/**
+ * @brief Raise an SVC request to raise privilege.
+ *
+ * The SVC handler checks that the SVC was raised from a system call and only
+ * then it raises the privilege. If this is called from any other place,
+ * the privilege is not raised.
+ */
     #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
 
-    /**
-     * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
-     * register.
-     */
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
     #define portRESET_PRIVILEGE()    vResetPrivilege()
 #else
     #define portIS_PRIVILEGED()
@@ -419,12 +419,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     extern BaseType_t xPortIsTaskPrivileged( void );
 
-    /**
-     * @brief Checks whether or not the calling task is privileged.
-     *
-     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
-     */
-    #define portIS_TASK_PRIVILEGED()      xPortIsTaskPrivileged()
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
+    #define portIS_TASK_PRIVILEGED()    xPortIsTaskPrivileged()
 
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
@@ -439,9 +439,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * based on whether or not Mainline extension is implemented. */
 #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
     #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
-        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
     #else
-        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    0
     #endif
 #endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
 
@@ -450,9 +450,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  */
 #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
 
-    /**
-     * @brief Count the number of leading zeros in a 32-bit value.
-     */
+/**
+ * @brief Count the number of leading zeros in a 32-bit value.
+ */
     static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
     {
         uint32_t ulReturn;
@@ -462,7 +462,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         return ulReturn;
     }
 
-    /* Check the configuration. */
+/* Check the configuration. */
     #if ( configMAX_PRIORITIES > 32 )
         #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
     #endif
@@ -471,16 +471,16 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection.  Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
     #endif
 
-    /**
-     * @brief Store/clear the ready priorities in a bit map.
-     */
-    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+/**
+ * @brief Store/clear the ready priorities in a bit map.
+ */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )      ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )       ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 
-    /**
-     * @brief Get the priority of the highest-priority task that is ready to execute.
-     */
-    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )   uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+/**
+ * @brief Get the priority of the highest-priority task that is ready to execute.
+ */
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
 
 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM85/secure/secure_context.c b/portable/IAR/ARM_CM85/secure/secure_context.c
index 0730d574d..7d2171996 100644
--- a/portable/IAR/ARM_CM85/secure/secure_context.c
+++ b/portable/IAR/ARM_CM85/secure/secure_context.c
@@ -65,7 +65,7 @@
  * @brief Maximum number of secure contexts.
  */
 #ifndef secureconfigMAX_SECURE_CONTEXTS
-    #define secureconfigMAX_SECURE_CONTEXTS        8UL
+    #define secureconfigMAX_SECURE_CONTEXTS    8UL
 #endif
 /*-----------------------------------------------------------*/
 
@@ -164,15 +164,15 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
         }
 
         #if ( configENABLE_MPU == 1 )
-            {
-                /* Configure thread mode to use PSP and to be unprivileged. */
-                secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
-            }
+        {
+            /* Configure thread mode to use PSP and to be unprivileged. */
+            secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
+        }
         #else /* configENABLE_MPU */
-            {
-                /* Configure thread mode to use PSP and to be privileged. */
-                secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
-            }
+        {
+            /* Configure thread mode to use PSP and to be privileged. */
+            secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
+        }
         #endif /* configENABLE_MPU */
     }
 }
@@ -219,16 +219,16 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
             if( pucStackMemory != NULL )
             {
                 /* Since stack grows down, the starting point will be the last
-                 * location. Note that this location is next to the last
-                 * allocated byte for stack (excluding the space for seal values)
-                 * because the hardware decrements the stack pointer before
-                 * writing i.e. if stack pointer is 0x2, a push operation will
-                 * decrement the stack pointer to 0x1 and then write at 0x1. */
+                * location. Note that this location is next to the last
+                * allocated byte for stack (excluding the space for seal values)
+                * because the hardware decrements the stack pointer before
+                * writing i.e. if stack pointer is 0x2, a push operation will
+                * decrement the stack pointer to 0x1 and then write at 0x1. */
                 xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize;
 
                 /* Seal the created secure process stack. */
-                *( uint32_t * )( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE;
-                *( uint32_t * )( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE;
+                *( uint32_t * ) ( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE;
+                *( uint32_t * ) ( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE;
 
                 /* The stack cannot go beyond this location. This value is
                  * programmed in the PSPLIM register on context switch.*/
@@ -237,32 +237,32 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
                 xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle;
 
                 #if ( configENABLE_MPU == 1 )
+                {
+                    /* Store the correct CONTROL value for the task on the stack.
+                     * This value is programmed in the CONTROL register on
+                     * context switch. */
+                    pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart;
+                    pulCurrentStackPointer--;
+
+                    if( ulIsTaskPrivileged )
                     {
-                        /* Store the correct CONTROL value for the task on the stack.
-                         * This value is programmed in the CONTROL register on
-                         * context switch. */
-                        pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart;
-                        pulCurrentStackPointer--;
-
-                        if( ulIsTaskPrivileged )
-                        {
-                            *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
-                        }
-                        else
-                        {
-                            *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
-                        }
-
-                        /* Store the current stack pointer. This value is programmed in
-                         * the PSP register on context switch. */
-                        xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+                        *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
                     }
+                    else
+                    {
+                        *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
+                    }
+
+                    /* Store the current stack pointer. This value is programmed in
+                     * the PSP register on context switch. */
+                    xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+                }
                 #else /* configENABLE_MPU */
-                    {
-                        /* Current SP is set to the starting of the stack. This
-                         * value programmed in the PSP register on context switch. */
-                        xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart;
-                    }
+                {
+                    /* Current SP is set to the starting of the stack. This
+                     * value programmed in the PSP register on context switch. */
+                    xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart;
+                }
                 #endif /* configENABLE_MPU */
 
                 /* Ensure to never return 0 as a valid context handle. */
@@ -275,7 +275,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
 }
 /*-----------------------------------------------------------*/
 
-secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle,
+                                                              void * pvTaskHandle )
 {
     uint32_t ulIPSR, ulSecureContextIndex;
 
@@ -306,7 +307,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandl
 }
 /*-----------------------------------------------------------*/
 
-secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle,
+                                                              void * pvTaskHandle )
 {
     uint8_t * pucStackLimit;
     uint32_t ulSecureContextIndex;
@@ -328,7 +330,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandl
 }
 /*-----------------------------------------------------------*/
 
-secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle,
+                                                              void * pvTaskHandle )
 {
     uint8_t * pucStackLimit;
     uint32_t ulSecureContextIndex;
diff --git a/portable/IAR/ARM_CM85/secure/secure_context.h b/portable/IAR/ARM_CM85/secure/secure_context.h
index d0adbaf01..0bf776198 100644
--- a/portable/IAR/ARM_CM85/secure/secure_context.h
+++ b/portable/IAR/ARM_CM85/secure/secure_context.h
@@ -38,12 +38,12 @@
 /**
  * @brief PSP value when no secure context is loaded.
  */
-#define securecontextNO_STACK               0x0
+#define securecontextNO_STACK              0x0
 
 /**
  * @brief Invalid context ID.
  */
-#define securecontextINVALID_CONTEXT_ID     0UL
+#define securecontextINVALID_CONTEXT_ID    0UL
 /*-----------------------------------------------------------*/
 
 /**
@@ -108,7 +108,8 @@ void SecureContext_Init( void );
  * @param[in] xSecureContextHandle Context handle corresponding to the
  * context to be freed.
  */
-void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle,
+                                void * pvTaskHandle );
 
 /**
  * @brief Loads the given context.
@@ -119,7 +120,8 @@ void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void
  * @param[in] xSecureContextHandle Context handle corresponding to the context
  * to be loaded.
  */
-void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle,
+                                void * pvTaskHandle );
 
 /**
  * @brief Saves the given context.
@@ -130,6 +132,7 @@ void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void
  * @param[in] xSecureContextHandle Context handle corresponding to the context
  * to be saved.
  */
-void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle,
+                                void * pvTaskHandle );
 
 #endif /* __SECURE_CONTEXT_H__ */
diff --git a/portable/IAR/ARM_CM85/secure/secure_heap.c b/portable/IAR/ARM_CM85/secure/secure_heap.c
index f3b80df54..1ec3bdbdb 100644
--- a/portable/IAR/ARM_CM85/secure/secure_heap.c
+++ b/portable/IAR/ARM_CM85/secure/secure_heap.c
@@ -67,7 +67,7 @@
 #define secureheapSIZE_MAX              ( ~( ( size_t ) 0 ) )
 
 /* Check if adding a and b will result in overflow. */
-#define secureheapADD_WILL_OVERFLOW( a, b )         ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) )
+#define secureheapADD_WILL_OVERFLOW( a, b )    ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) )
 
 /* MSB of the xBlockSize member of an BlockLink_t structure is used to track
  * the allocation status of a block.  When MSB of the xBlockSize member of
@@ -397,17 +397,17 @@ void * pvPortMalloc( size_t xWantedSize )
     traceMALLOC( pvReturn, xWantedSize );
 
     #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
+    {
+        if( pvReturn == NULL )
         {
-            if( pvReturn == NULL )
-            {
-                extern void vApplicationMallocFailedHook( void );
-                vApplicationMallocFailedHook();
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
+            extern void vApplicationMallocFailedHook( void );
+            vApplicationMallocFailedHook();
         }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
     #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */
 
     secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );
diff --git a/portable/IAR/ARM_CM85/secure/secure_init.c b/portable/IAR/ARM_CM85/secure/secure_init.c
index dc19ebc7d..b89c5f644 100644
--- a/portable/IAR/ARM_CM85/secure/secure_init.c
+++ b/portable/IAR/ARM_CM85/secure/secure_init.c
@@ -93,7 +93,7 @@ secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )
          * permitted. CP11 should be programmed to the same value as CP10. */
         *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
 
-        /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
+        /* LSPENS = 0 ==> LSPEN is writable from non-secure state. This ensures
          * that we can enable/disable lazy stacking in port.c file. */
         *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK );
 
diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/port.c b/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
index 80410e82e..c940c304b 100644
--- a/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
@@ -110,8 +110,8 @@
 /**
  * @brief Constants used during system call enter and exit.
  */
-#define portPSR_STACK_PADDING_MASK                ( 1UL << 9UL )
-#define portEXC_RETURN_STACK_FRAME_TYPE_MASK      ( 1UL << 4UL )
+#define portPSR_STACK_PADDING_MASK              ( 1UL << 9UL )
+#define portEXC_RETURN_STACK_FRAME_TYPE_MASK    ( 1UL << 4UL )
 /*-----------------------------------------------------------*/
 
 /**
@@ -133,81 +133,81 @@
 /**
  * @brief Offsets in the stack to the parameters when inside the SVC handler.
  */
-#define portOFFSET_TO_LR                    ( 5 )
-#define portOFFSET_TO_PC                    ( 6 )
-#define portOFFSET_TO_PSR                   ( 7 )
+#define portOFFSET_TO_LR     ( 5 )
+#define portOFFSET_TO_PC     ( 6 )
+#define portOFFSET_TO_PSR    ( 7 )
 /*-----------------------------------------------------------*/
 
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                      ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                      ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                       ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                      ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                      ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                     ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                     ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK  ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK               ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK               ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK               ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK               ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK               ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK               ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK               ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK               ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0              ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1              ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2              ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3              ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4              ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5              ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6              ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7              ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE            ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT      ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                      ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE             ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -216,11 +216,11 @@
 
 /* Extract last address of the MPU region as encoded in the
  * RLAR (Region Limit Address Register) value. */
-#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar )  \
+#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar ) \
     ( ( ( rlar ) & portMPU_RLAR_ADDRESS_MASK ) | ~portMPU_RLAR_ADDRESS_MASK )
 
 /* Does addr lies within [start, end] address range? */
-#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end )    \
+#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \
     ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) )
 
 /* Is the access request satisfied by the available permissions? */
@@ -422,54 +422,57 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the system call stack so that upon returning from
-     * SVC, the system call stack is used.
-     *
-     * It is used for the system calls with up to 4 parameters.
-     *
-     * @param pulTaskStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the system call stack so that upon returning from
+ * SVC, the system call stack is used.
+ *
+ * It is used for the system calls with up to 4 parameters.
+ *
+ * @param pulTaskStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallEnter( uint32_t * pulTaskStack,
+                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the system call stack so that upon returning from
-     * SVC, the system call stack is used.
-     *
-     * It is used for the system calls with 5 parameters.
-     *
-     * @param pulTaskStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the system call stack so that upon returning from
+ * SVC, the system call stack is used.
+ *
+ * It is used for the system calls with 5 parameters.
+ *
+ * @param pulTaskStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallEnter_1( uint32_t * pulTaskStack,
+                             uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    /**
-     * @brief Sets up the task stack so that upon returning from
-     * SVC, the task stack is used again.
-     *
-     * @param pulSystemCallStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the task stack so that upon returning from
+ * SVC, the task stack is used again.
+ *
+ * @param pulSystemCallStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallExit( uint32_t * pulSystemCallStack,
+                          uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Checks whether or not the calling task is privileged.
-     *
-     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
-     */
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
     BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
 
 #endif /* configENABLE_MPU == 1 */
@@ -1086,18 +1089,18 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             vRestoreContextOfFirstTask();
             break;
 
-        #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
-            case portSVC_RAISE_PRIVILEGE:
+            #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+                case portSVC_RAISE_PRIVILEGE:
 
-                /* Only raise the privilege, if the svc was raised from any of
-                 * the system calls. */
-                if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
-                    ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
-                {
-                    vRaisePrivilege();
-                }
-                break;
-        #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+                    /* Only raise the privilege, if the svc was raised from any of
+                     * the system calls. */
+                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+                    {
+                        vRaisePrivilege();
+                    }
+                    break;
+            #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
         default:
             /* Incorrect SVC call. */
@@ -1108,513 +1111,526 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulSystemCallStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallEnter( uint32_t * pulTaskStack,
+                           uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulSystemCallStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        /* This is not NULL only for the duration of the system call. */
-        configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+        #if defined( __ARMCC_VERSION )
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+
+            /* This is not NULL only for the duration of the system call. */
+            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the system call stack for the stack frame. */
+            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulSystemCallStack[ i ] = pulTaskStack[ i ];
+            }
+
+            /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
+             * restore it when we exit from the system call. */
+            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* Use the pulSystemCallStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+
+            /* Remember the location where we should copy the stack frame when we exit from
+             * the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+
+            /* Record if the hardware used padding to force the stack pointer
+             * to be double word aligned. */
+            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
+            {
+                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
             }
+
+            /* We ensure in pxPortInitialiseStack that the system call stack is
+             * double word aligned and therefore, there is no need of padding.
+             * Clear the bit[9] of stacked xPSR. */
+            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
+
+            /* Raise the privilege for the duration of the system call. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " bics r0, r1         \n" /* Clear nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the system call stack for the stack frame. */
-        pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulSystemCallStack[ i ] = pulTaskStack[ i ];
-        }
-
-        /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
-         * restore it when we exit from the system call. */
-        pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-        __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* Use the pulSystemCallStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-
-        /* Remember the location where we should copy the stack frame when we exit from
-         * the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-        /* Record if the hardware used padding to force the stack pointer
-         * to be double word aligned. */
-        if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-        {
-            pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-        }
-        else
-        {
-            pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-        }
-
-        /* We ensure in pxPortInitialiseStack that the system call stack is
-         * double word aligned and therefore, there is no need of padding.
-         * Clear the bit[9] of stacked xPSR. */
-        pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-        /* Raise the privilege for the duration of the system call. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " bics r0, r1         \n" /* Clear nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulSystemCallStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallEnter_1( uint32_t * pulTaskStack,
+                             uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulSystemCallStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        /* This is not NULL only for the duration of the system call. */
-        configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+        #if defined( __ARMCC_VERSION )
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+
+            /* This is not NULL only for the duration of the system call. */
+            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the system call stack for the stack frame and
+             * the parameter passed on the stack. We only need to copy one
+             * parameter but we still reserve 2 spaces to keep the stack
+             * double word aligned. */
+            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulSystemCallStack[ i ] = pulTaskStack[ i ];
+            }
+
+            /* Copy the parameter which is passed the stack. */
+            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
+            {
+                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
+
+                /* Record if the hardware used padding to force the stack pointer
+                 * to be double word aligned. */
+                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
+
+                /* Record if the hardware used padding to force the stack pointer
+                 * to be double word aligned. */
+                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
             }
+
+            /* Store the value of the LR and PSPLIM registers before the SVC was raised.
+             * We need to restore it when we exit from the system call. */
+            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* Use the pulSystemCallStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+
+            /* Remember the location where we should copy the stack frame when we exit from
+             * the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+
+            /* We ensure in pxPortInitialiseStack that the system call stack is
+             * double word aligned and therefore, there is no need of padding.
+             * Clear the bit[9] of stacked xPSR. */
+            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
+
+            /* Raise the privilege for the duration of the system call. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " bics r0, r1         \n" /* Clear nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the system call stack for the stack frame and
-         * the parameter passed on the stack. We only need to copy one
-         * parameter but we still reserve 2 spaces to keep the stack
-         * double word aligned. */
-        pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulSystemCallStack[ i ] = pulTaskStack[ i ];
-        }
-
-        /* Copy the parameter which is passed the stack. */
-        if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-        {
-            pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
-            /* Record if the hardware used padding to force the stack pointer
-             * to be double word aligned. */
-            pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-        }
-        else
-        {
-            pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
-            /* Record if the hardware used padding to force the stack pointer
-             * to be double word aligned. */
-            pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-        }
-
-        /* Store the value of the LR and PSPLIM registers before the SVC was raised.
-         * We need to restore it when we exit from the system call. */
-        pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-        __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* Use the pulSystemCallStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-
-        /* Remember the location where we should copy the stack frame when we exit from
-         * the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-        /* We ensure in pxPortInitialiseStack that the system call stack is
-         * double word aligned and therefore, there is no need of padding.
-         * Clear the bit[9] of stacked xPSR. */
-        pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-        /* Raise the privilege for the duration of the system call. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " bics r0, r1         \n" /* Clear nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulTaskStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-    #if defined( __ARMCC_VERSION )
-        /* Declaration when these variable are defined in code instead of being
-         * exported from linker scripts. */
-        extern uint32_t * __syscalls_flash_start__;
-        extern uint32_t * __syscalls_flash_end__;
-    #else
-        /* Declaration when these variable are exported from linker scripts. */
-        extern uint32_t __syscalls_flash_start__[];
-        extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if defined( __ARMCC_VERSION ) */
-
-    ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallExit( uint32_t * pulSystemCallStack,
+                          uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulTaskStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
-        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+        #if defined( __ARMCC_VERSION )
+
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
+
+            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                                    ::: "memory"
-                            );
+                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+                {
+                    /* Extended frame i.e. FPU in use. */
+                    ulStackFrameSize = 26;
+                    __asm volatile (
+                        " vpush {s0}         \n" /* Trigger lazy stacking. */
+                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
+                        ::: "memory"
+                        );
+                }
+                else
+                {
+                    /* Standard frame i.e. FPU not in use. */
+                    ulStackFrameSize = 8;
+                }
+            }
+            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+            {
+                ulStackFrameSize = 8;
+            }
+            #endif /* configENABLE_FPU || configENABLE_MVE */
+
+            /* Make space on the task stack for the stack frame. */
+            pulTaskStack = pulTaskStack - ulStackFrameSize;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulTaskStack[ i ] = pulSystemCallStack[ i ];
+            }
+
+            /* Use the pulTaskStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
+
+            /* Restore the LR and PSPLIM to what they were at the time of
+             * system call entry. */
+            pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+
+            /* If the hardware used padding to force the stack pointer
+             * to be double word aligned, set the stacked xPSR bit[9],
+             * otherwise clear it. */
+            if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG )
+            {
+                pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK;
             }
             else
             {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
             }
+
+            /* This is not NULL only for the duration of the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
+
+            /* Drop the privilege before returning to the thread mode. */
+            __asm volatile (
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " orrs r0, r1         \n" /* Set nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+                );
         }
-        #else
-        {
-            ulStackFrameSize = 8;
-        }
-        #endif /* configENABLE_FPU || configENABLE_MVE */
-
-        /* Make space on the task stack for the stack frame. */
-        pulTaskStack = pulTaskStack - ulStackFrameSize;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulTaskStack[ i ] = pulSystemCallStack[ i ];
-        }
-
-        /* Use the pulTaskStack in thread mode. */
-        __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
-
-        /* Restore the LR and PSPLIM to what they were at the time of
-         * system call entry. */
-        pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
-        __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-
-        /* If the hardware used padding to force the stack pointer
-         * to be double word aligned, set the stacked xPSR bit[9],
-         * otherwise clear it. */
-        if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG )
-        {
-            pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK;
-        }
-        else
-        {
-            pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-        }
-
-        /* This is not NULL only for the duration of the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
-
-        /* Drop the privilege before returning to the thread mode. */
-        __asm volatile (
-                            " mrs r0, control     \n" /* Obtain current control value. */
-                            " movs r1, #1         \n" /* r1 = 1. */
-                            " orrs r0, r1         \n" /* Set nPRIV bit. */
-                            " msr control, r0     \n" /* Write back new control value. */
-                            ::: "r0", "r1", "memory"
-                        );
     }
-}
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */
-{
-    BaseType_t xTaskIsPrivileged = pdFALSE;
-    const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
-
-    if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+    BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */
     {
-        xTaskIsPrivileged = pdTRUE;
-    }
+        BaseType_t xTaskIsPrivileged = pdFALSE;
+        const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
 
-    return xTaskIsPrivileged;
-}
+        if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+        {
+            xTaskIsPrivileged = pdTRUE;
+        }
+
+        return xTaskIsPrivileged;
+    }
 
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
-#if( configENABLE_MPU == 1 )
+#if ( configENABLE_MPU == 1 )
 
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     StackType_t * pxEndOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters,
-                                     BaseType_t xRunPrivileged,
-                                     xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
-{
-    uint32_t ulIndex = 0;
-
-    xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
-    ulIndex++;
-
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
-    ulIndex++;
-
-    #if ( configENABLE_TRUSTZONE == 1 )
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters,
+                                         BaseType_t xRunPrivileged,
+                                         xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
     {
-        xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT;  /* xSecureContext. */
+        uint32_t ulIndex = 0;
+
+        xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
         ulIndex++;
-    }
-    #endif /* configENABLE_TRUSTZONE */
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
-    ulIndex++;
-    xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
-    ulIndex++;
-    if( xRunPrivileged == pdTRUE )
-    {
-        xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */
         ulIndex++;
-    }
-    else
-    {
-        xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */
         ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
+        ulIndex++;
+
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters;            /* r0. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x01010101;                           /* r1. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x02020202;                           /* r2. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x03030303;                           /* r3. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = 0x12121212;                           /* r12. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode;                  /* PC. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR;                     /* xPSR. */
+        ulIndex++;
+
+        #if ( configENABLE_TRUSTZONE == 1 )
+        {
+            xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT; /* xSecureContext. */
+            ulIndex++;
+        }
+        #endif /* configENABLE_TRUSTZONE */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
+        ulIndex++;
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
+        ulIndex++;
+
+        if( xRunPrivileged == pdTRUE )
+        {
+            xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
+            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+            ulIndex++;
+        }
+        else
+        {
+            xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
+            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+            ulIndex++;
+        }
+
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
+        ulIndex++;
+
+        #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+        {
+            /* Ensure that the system call stack is double word aligned. */
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] );
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) &
+                                                                                     ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
+
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] );
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) +
+                                                                                            ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) &
+                                                                                          ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
+
+            /* This is not NULL only for the duration of a system call. */
+            xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL;
+        }
+        #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
+
+        return &( xMPUSettings->ulContext[ ulIndex ] );
     }
-    xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
-    ulIndex++;
-
-    #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
-    {
-        /* Ensure that the system call stack is double word aligned. */
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] );
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) &
-                                                                                 ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
-
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] );
-        xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) +
-                                                                                        ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) &
-                                                                                      ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
-
-        /* This is not NULL only for the duration of a system call. */
-        xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL;
-    }
-    #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
-
-    return &( xMPUSettings->ulContext[ ulIndex ] );
-}
 
 #else /* configENABLE_MPU */
 
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     StackType_t * pxEndOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters ) /* PRIVILEGED_FUNCTION */
-{
-    /* Simulate the stack frame as it would be created by a context switch
-     * interrupt. */
-    #if ( portPRELOAD_REGISTERS == 0 )
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters ) /* PRIVILEGED_FUNCTION */
     {
-        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-        pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
-        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-        pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
-        *pxTopOfStack = portINITIAL_EXC_RETURN;
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
-
-        #if ( configENABLE_TRUSTZONE == 1 )
+        /* Simulate the stack frame as it would be created by a context switch
+         * interrupt. */
+        #if ( portPRELOAD_REGISTERS == 0 )
         {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
-        }
-        #endif /* configENABLE_TRUSTZONE */
-    }
-    #else /* portPRELOAD_REGISTERS */
-    {
-        pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-        *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
-        pxTopOfStack--;
-        *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
+            pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
+            *pxTopOfStack = portINITIAL_EXC_RETURN;
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+            #if ( configENABLE_TRUSTZONE == 1 )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+            }
+            #endif /* configENABLE_TRUSTZONE */
+        }
+        #else /* portPRELOAD_REGISTERS */
         {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
-        }
-        #endif /* configENABLE_TRUSTZONE */
-    }
-    #endif /* portPRELOAD_REGISTERS */
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
+            pxTopOfStack--;
+            *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack;            /* Slot used to hold this task's PSPLIM value. */
 
-    return pxTopOfStack;
-}
+            #if ( configENABLE_TRUSTZONE == 1 )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+            }
+            #endif /* configENABLE_TRUSTZONE */
+        }
+        #endif /* portPRELOAD_REGISTERS */
+
+        return pxTopOfStack;
+    }
 
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/portmacro.h b/portable/IAR/ARM_CM85_NTZ/non_secure/portmacro.h
index 374150262..cffcb20d9 100644
--- a/portable/IAR/ARM_CM85_NTZ/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM85_NTZ/non_secure/portmacro.h
@@ -53,16 +53,16 @@
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME                       "Cortex-M85"
-#define portHAS_ARMV8M_MAIN_EXTENSION       1
-#define portDONT_DISCARD                    __root
+#define portARCH_NAME                    "Cortex-M85"
+#define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
 /* ARMv8-M common port configurations. */
 #include "portmacrocommon.h"
 /*-----------------------------------------------------------*/
 
-#if( configTOTAL_MPU_REGIONS == 16 )
+#if ( configTOTAL_MPU_REGIONS == 16 )
     #error 16 MPU regions are not yet supported for this port.
 #endif
 /*-----------------------------------------------------------*/
@@ -70,8 +70,8 @@
 /**
  * @brief Critical section management.
  */
-#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()
-#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )
+#define portDISABLE_INTERRUPTS()    ulSetInterruptMask()
+#define portENABLE_INTERRUPTS()     vClearInterruptMask( 0 )
 /*-----------------------------------------------------------*/
 
 /* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h
index e5ffdb48b..62e462a27 100644
--- a/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h
@@ -81,8 +81,8 @@ typedef unsigned long    UBaseType_t;
     typedef uint32_t     TickType_t;
     #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-     * not need to be guarded with a critical section. */
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
     #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -117,7 +117,7 @@ extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGE
 extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
 
 #if ( configENABLE_TRUSTZONE == 1 )
-    extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize );     /* __attribute__ (( naked )) */
+    extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
     extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
 #endif /* configENABLE_TRUSTZONE */
 
@@ -188,13 +188,13 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Settings to define an MPU region.
-     */
+/**
+ * @brief Settings to define an MPU region.
+ */
     typedef struct MPURegionSettings
     {
-        uint32_t ulRBAR;     /**< RBAR for the region. */
-        uint32_t ulRLAR;     /**< RLAR for the region. */
+        uint32_t ulRBAR; /**< RBAR for the region. */
+        uint32_t ulRLAR; /**< RLAR for the region. */
     } MPURegionSettings_t;
 
     #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
@@ -203,9 +203,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-        /**
-         * @brief System call stack.
-         */
+/**
+ * @brief System call stack.
+ */
         typedef struct SYSTEM_CALL_STACK_INFO
         {
             uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ];
@@ -218,74 +218,74 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
-    /**
-     * @brief MPU settings as stored in the TCB.
-     */
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
     #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
 
-        #if( configENABLE_TRUSTZONE == 1 )
+        #if ( configENABLE_TRUSTZONE == 1 )
 
-            /*
-             * +-----------+---------------+----------+-----------------+------------------------------+-----+
-             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
-             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
-             * +-----------+---------------+----------+-----------------+------------------------------+-----+
-             *
-             * <-----------><--------------><---------><----------------><-----------------------------><---->
-             *      16             16            8               8                     5                   1
-             */
-            #define MAX_CONTEXT_SIZE 54
+/*
+ * +-----------+---------------+----------+-----------------+------------------------------+-----+
+ * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+ * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+ * +-----------+---------------+----------+-----------------+------------------------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><-----------------------------><---->
+ *      16             16            8               8                     5                   1
+ */
+            #define MAX_CONTEXT_SIZE    54
 
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-            /*
-             * +-----------+---------------+----------+-----------------+----------------------+-----+
-             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
-             * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
-             * +-----------+---------------+----------+-----------------+----------------------+-----+
-             *
-             * <-----------><--------------><---------><----------------><---------------------><---->
-             *      16             16            8               8                  4              1
-             */
-            #define MAX_CONTEXT_SIZE 53
+/*
+ * +-----------+---------------+----------+-----------------+----------------------+-----+
+ * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+ * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
+ * +-----------+---------------+----------+-----------------+----------------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><---------------------><---->
+ *      16             16            8               8                  4              1
+ */
+            #define MAX_CONTEXT_SIZE    53
 
         #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
 
     #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-        #if( configENABLE_TRUSTZONE == 1 )
+        #if ( configENABLE_TRUSTZONE == 1 )
 
-            /*
-             * +----------+-----------------+------------------------------+-----+
-             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
-             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
-             * +----------+-----------------+------------------------------+-----+
-             *
-             * <---------><----------------><------------------------------><---->
-             *     8               8                      5                   1
-             */
-            #define MAX_CONTEXT_SIZE 22
+/*
+ * +----------+-----------------+------------------------------+-----+
+ * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+ * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+ * +----------+-----------------+------------------------------+-----+
+ *
+ * <---------><----------------><------------------------------><---->
+ *     8               8                      5                   1
+ */
+            #define MAX_CONTEXT_SIZE    22
 
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-            /*
-             * +----------+-----------------+----------------------+-----+
-             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
-             * |          | PC, xPSR        | EXC_RETURN           |     |
-             * +----------+-----------------+----------------------+-----+
-             *
-             * <---------><----------------><----------------------><---->
-             *     8               8                  4              1
-             */
-            #define MAX_CONTEXT_SIZE 21
+/*
+ * +----------+-----------------+----------------------+-----+
+ * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+ * |          | PC, xPSR        | EXC_RETURN           |     |
+ * +----------+-----------------+----------------------+-----+
+ *
+ * <---------><----------------><----------------------><---->
+ *     8               8                  4              1
+ */
+            #define MAX_CONTEXT_SIZE    21
 
         #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
 
     #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-    /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
-    #define portSTACK_FRAME_HAS_PADDING_FLAG     ( 1UL << 0UL )
-    #define portTASK_IS_PRIVILEGED_FLAG          ( 1UL << 1UL )
+/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
+    #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
+    #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
     typedef struct MPU_SETTINGS
     {
@@ -364,49 +364,49 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-    /**
-     * @brief Allocate a secure context for the task.
-     *
-     * Tasks are not created with a secure context. Any task that is going to call
-     * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
-     * secure context before it calls any secure function.
-     *
-     * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
-     */
+/**
+ * @brief Allocate a secure context for the task.
+ *
+ * Tasks are not created with a secure context. Any task that is going to call
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+ * secure context before it calls any secure function.
+ *
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+ */
     #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
 
-    /**
-     * @brief Called when a task is deleted to delete the task's secure context,
-     * if it has one.
-     *
-     * @param[in] pxTCB The TCB of the task being deleted.
-     */
+/**
+ * @brief Called when a task is deleted to delete the task's secure context,
+ * if it has one.
+ *
+ * @param[in] pxTCB The TCB of the task being deleted.
+ */
     #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
 #endif /* configENABLE_TRUSTZONE */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
 
-    /**
-     * @brief Checks whether or not the processor is privileged.
-     *
-     * @return 1 if the processor is already privileged, 0 otherwise.
-     */
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
     #define portIS_PRIVILEGED()      xIsPrivileged()
 
-    /**
-     * @brief Raise an SVC request to raise privilege.
-     *
-     * The SVC handler checks that the SVC was raised from a system call and only
-     * then it raises the privilege. If this is called from any other place,
-     * the privilege is not raised.
-     */
+/**
+ * @brief Raise an SVC request to raise privilege.
+ *
+ * The SVC handler checks that the SVC was raised from a system call and only
+ * then it raises the privilege. If this is called from any other place,
+ * the privilege is not raised.
+ */
     #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
 
-    /**
-     * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
-     * register.
-     */
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
     #define portRESET_PRIVILEGE()    vResetPrivilege()
 #else
     #define portIS_PRIVILEGED()
@@ -419,12 +419,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     extern BaseType_t xPortIsTaskPrivileged( void );
 
-    /**
-     * @brief Checks whether or not the calling task is privileged.
-     *
-     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
-     */
-    #define portIS_TASK_PRIVILEGED()      xPortIsTaskPrivileged()
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
+    #define portIS_TASK_PRIVILEGED()    xPortIsTaskPrivileged()
 
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
@@ -439,9 +439,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * based on whether or not Mainline extension is implemented. */
 #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
     #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
-        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
     #else
-        #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    0
     #endif
 #endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
 
@@ -450,9 +450,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  */
 #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
 
-    /**
-     * @brief Count the number of leading zeros in a 32-bit value.
-     */
+/**
+ * @brief Count the number of leading zeros in a 32-bit value.
+ */
     static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
     {
         uint32_t ulReturn;
@@ -462,7 +462,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         return ulReturn;
     }
 
-    /* Check the configuration. */
+/* Check the configuration. */
     #if ( configMAX_PRIORITIES > 32 )
         #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
     #endif
@@ -471,16 +471,16 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection.  Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
     #endif
 
-    /**
-     * @brief Store/clear the ready priorities in a bit map.
-     */
-    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+/**
+ * @brief Store/clear the ready priorities in a bit map.
+ */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )      ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )       ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 
-    /**
-     * @brief Get the priority of the highest-priority task that is ready to execute.
-     */
-    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )   uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+/**
+ * @brief Get the priority of the highest-priority task that is ready to execute.
+ */
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
 
 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CRx_No_GIC/port.c b/portable/IAR/ARM_CRx_No_GIC/port.c
index 799a20e17..235585642 100644
--- a/portable/IAR/ARM_CRx_No_GIC/port.c
+++ b/portable/IAR/ARM_CRx_No_GIC/port.c
@@ -35,7 +35,7 @@
 
 #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
     /* Check the configuration. */
-    #if( configMAX_PRIORITIES > 32 )
+    #if ( configMAX_PRIORITIES > 32 )
         #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
     #endif
 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
@@ -49,35 +49,35 @@
 #endif
 
 /* A critical section is exited when the critical section nesting count reaches
-this value. */
-#define portNO_CRITICAL_NESTING         ( ( uint32_t ) 0 )
+ * this value. */
+#define portNO_CRITICAL_NESTING          ( ( uint32_t ) 0 )
 
 /* Tasks are not created with a floating point context, but can be given a
-floating point context after they have been created.  A variable is stored as
-part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
-does not have an FPU context, or any other value if the task does have an FPU
-context. */
-#define portNO_FLOATING_POINT_CONTEXT   ( ( StackType_t ) 0 )
+ * floating point context after they have been created.  A variable is stored as
+ * part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
+ * does not have an FPU context, or any other value if the task does have an FPU
+ * context. */
+#define portNO_FLOATING_POINT_CONTEXT    ( ( StackType_t ) 0 )
 
 /* Constants required to setup the initial task context. */
-#define portINITIAL_SPSR                ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */
-#define portTHUMB_MODE_BIT              ( ( StackType_t ) 0x20 )
-#define portTHUMB_MODE_ADDRESS          ( 0x01UL )
+#define portINITIAL_SPSR                 ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */
+#define portTHUMB_MODE_BIT               ( ( StackType_t ) 0x20 )
+#define portTHUMB_MODE_ADDRESS           ( 0x01UL )
 
 /* Masks all bits in the APSR other than the mode bits. */
-#define portAPSR_MODE_BITS_MASK         ( 0x1F )
+#define portAPSR_MODE_BITS_MASK          ( 0x1F )
 
 /* The value of the mode bits in the APSR when the CPU is executing in user
-mode. */
-#define portAPSR_USER_MODE              ( 0x10 )
+ * mode. */
+#define portAPSR_USER_MODE               ( 0x10 )
 
 /* Let the user override the pre-loading of the initial LR with the address of
-prvTaskExitError() in case it messes up unwinding of the stack in the
-debugger. */
+ * prvTaskExitError() in case it messes up unwinding of the stack in the
+ * debugger. */
 #ifdef configTASK_RETURN_ADDRESS
-    #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
+    #define portTASK_RETURN_ADDRESS    configTASK_RETURN_ADDRESS
 #else
-    #define portTASK_RETURN_ADDRESS prvTaskExitError
+    #define portTASK_RETURN_ADDRESS    prvTaskExitError
 #endif
 
 /*-----------------------------------------------------------*/
@@ -96,21 +96,21 @@ static void prvTaskExitError( void );
 /*-----------------------------------------------------------*/
 
 /* A variable is used to keep track of the critical section nesting.  This
-variable has to be stored as part of the task context and must be initialised to
-a non zero value to ensure interrupts don't inadvertently become unmasked before
-the scheduler starts.  As it is stored as part of the task context it will
-automatically be set to 0 when the first task is started. */
+ * variable has to be stored as part of the task context and must be initialised to
+ * a non zero value to ensure interrupts don't inadvertently become unmasked before
+ * the scheduler starts.  As it is stored as part of the task context it will
+ * automatically be set to 0 when the first task is started. */
 volatile uint32_t ulCriticalNesting = 9999UL;
 
 /* Saved as part of the task context.  If ulPortTaskHasFPUContext is non-zero then
-a floating point context must be saved and restored for the task. */
+ * a floating point context must be saved and restored for the task. */
 volatile uint32_t ulPortTaskHasFPUContext = pdFALSE;
 
 /* Set to 1 to pend a context switch from an ISR. */
 volatile uint32_t ulPortYieldRequired = pdFALSE;
 
 /* Counts the interrupt nesting depth.  A context switch is only performed if
-if the nesting depth is 0. */
+ * if the nesting depth is 0. */
 volatile uint32_t ulPortInterruptNesting = 0UL;
 
 /*-----------------------------------------------------------*/
@@ -118,14 +118,16 @@ volatile uint32_t ulPortInterruptNesting = 0UL;
 /*
  * See header file for description.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
     /* Setup the initial stack of the task.  The stack is set exactly as
-    expected by the portRESTORE_CONTEXT() macro.
-
-    The fist real value on the stack is the status register, which is set for
-    system mode, with interrupts enabled.  A few NULLs are added first to ensure
-    GDB does not try decoding a non-existent return address. */
+     * expected by the portRESTORE_CONTEXT() macro.
+     *
+     * The fist real value on the stack is the status register, which is set for
+     * system mode, with interrupts enabled.  A few NULLs are added first to ensure
+     * GDB does not try decoding a non-existent return address. */
     *pxTopOfStack = ( StackType_t ) NULL;
     pxTopOfStack--;
     *pxTopOfStack = ( StackType_t ) NULL;
@@ -147,43 +149,43 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
     pxTopOfStack--;
 
     /* Next all the registers other than the stack pointer. */
-    *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;    /* R14 */
+    *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* R14 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
+    *pxTopOfStack = ( StackType_t ) 0x12121212;              /* R12 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
+    *pxTopOfStack = ( StackType_t ) 0x11111111;              /* R11 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
+    *pxTopOfStack = ( StackType_t ) 0x10101010;              /* R10 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
+    *pxTopOfStack = ( StackType_t ) 0x09090909;              /* R9 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
+    *pxTopOfStack = ( StackType_t ) 0x08080808;              /* R8 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
+    *pxTopOfStack = ( StackType_t ) 0x07070707;              /* R7 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
+    *pxTopOfStack = ( StackType_t ) 0x06060606;              /* R6 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
+    *pxTopOfStack = ( StackType_t ) 0x05050505;              /* R5 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
+    *pxTopOfStack = ( StackType_t ) 0x04040404;              /* R4 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
+    *pxTopOfStack = ( StackType_t ) 0x03030303;              /* R3 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
+    *pxTopOfStack = ( StackType_t ) 0x02020202;              /* R2 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
+    *pxTopOfStack = ( StackType_t ) 0x01010101;              /* R1 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+    *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */
     pxTopOfStack--;
 
     /* The task will start with a critical nesting count of 0 as interrupts are
-    enabled. */
+     * enabled. */
     *pxTopOfStack = portNO_CRITICAL_NESTING;
     pxTopOfStack--;
 
     /* The task will start without a floating point context.  A task that uses
-    the floating point hardware must call vPortTaskUsesFPU() before executing
-    any floating point instructions. */
+     * the floating point hardware must call vPortTaskUsesFPU() before executing
+     * any floating point instructions. */
     *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
 
     return pxTopOfStack;
@@ -193,24 +195,28 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
 static void prvTaskExitError( void )
 {
     /* A function that implements a task must not exit or attempt to return to
-    its caller as there is nothing to return to.  If a task wants to exit it
-    should instead call vTaskDelete( NULL ).
-
-    Artificially force an assert() to be triggered if configASSERT() is
-    defined, then stop here so application writers can catch the error. */
+     * its caller as there is nothing to return to.  If a task wants to exit it
+     * should instead call vTaskDelete( NULL ).
+     *
+     * Artificially force an assert() to be triggered if configASSERT() is
+     * defined, then stop here so application writers can catch the error. */
     configASSERT( ulPortInterruptNesting == ~0UL );
     portDISABLE_INTERRUPTS();
-    for( ;; );
+
+    for( ; ; )
+    {
+    }
 }
 /*-----------------------------------------------------------*/
 
 BaseType_t xPortStartScheduler( void )
 {
-uint32_t ulAPSR;
+    uint32_t ulAPSR;
 
     /* Only continue if the CPU is not in User mode.  The CPU must be in a
-    Privileged mode for the scheduler to start. */
+     * Privileged mode for the scheduler to start. */
     __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) );
+
     ulAPSR &= portAPSR_MODE_BITS_MASK;
     configASSERT( ulAPSR != portAPSR_USER_MODE );
 
@@ -225,10 +231,10 @@ uint32_t ulAPSR;
     }
 
     /* Will only get here if vTaskStartScheduler() was called with the CPU in
-    a non-privileged mode or the binary point register was not set to its lowest
-    possible value.  prvTaskExitError() is referenced to prevent a compiler
-    warning about it being defined but not referenced in the case that the user
-    defines their own exit address. */
+     * a non-privileged mode or the binary point register was not set to its lowest
+     * possible value.  prvTaskExitError() is referenced to prevent a compiler
+     * warning about it being defined but not referenced in the case that the user
+     * defines their own exit address. */
     ( void ) prvTaskExitError;
     return 0;
 }
@@ -237,7 +243,7 @@ uint32_t ulAPSR;
 void vPortEndScheduler( void )
 {
     /* Not implemented in ports where there is nothing to return to.
-    Artificially force an assert. */
+     * Artificially force an assert. */
     configASSERT( ulCriticalNesting == 1000UL );
 }
 /*-----------------------------------------------------------*/
@@ -246,16 +252,16 @@ void vPortEnterCritical( void )
 {
     portDISABLE_INTERRUPTS();
 
-    /* Now interrupts are disabled ulCriticalNesting can be accessed
-    directly.  Increment ulCriticalNesting to keep a count of how many times
-    portENTER_CRITICAL() has been called. */
+    /* Now that interrupts are disabled, ulCriticalNesting can be accessed
+     * directly.  Increment ulCriticalNesting to keep a count of how many times
+     * portENTER_CRITICAL() has been called. */
     ulCriticalNesting++;
 
     /* This is not the interrupt safe version of the enter critical function so
-    assert() if it is being called from an interrupt context.  Only API
-    functions that end in "FromISR" can be used in an interrupt.  Only assert if
-    the critical nesting count is 1 to protect against recursive calls if the
-    assert function also uses a critical section. */
+     * assert() if it is being called from an interrupt context.  Only API
+     * functions that end in "FromISR" can be used in an interrupt.  Only assert if
+     * the critical nesting count is 1 to protect against recursive calls if the
+     * assert function also uses a critical section. */
     if( ulCriticalNesting == 1 )
     {
         configASSERT( ulPortInterruptNesting == 0 );
@@ -268,15 +274,15 @@ void vPortExitCritical( void )
     if( ulCriticalNesting > portNO_CRITICAL_NESTING )
     {
         /* Decrement the nesting count as the critical section is being
-        exited. */
+         * exited. */
         ulCriticalNesting--;
 
         /* If the nesting level has reached zero then all interrupt
-        priorities must be re-enabled. */
+         * priorities must be re-enabled. */
         if( ulCriticalNesting == portNO_CRITICAL_NESTING )
         {
             /* Critical nesting has reached zero so all interrupt priorities
-            should be unmasked. */
+             * should be unmasked. */
             portENABLE_INTERRUPTS();
         }
     }
@@ -285,7 +291,7 @@ void vPortExitCritical( void )
 
 void FreeRTOS_Tick_Handler( void )
 {
-uint32_t ulInterruptStatus;
+    uint32_t ulInterruptStatus;
 
     ulInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
 
@@ -303,13 +309,13 @@ uint32_t ulInterruptStatus;
 
 void vPortTaskUsesFPU( void )
 {
-uint32_t ulInitialFPSCR = 0;
+    uint32_t ulInitialFPSCR = 0;
 
     /* A task is registering the fact that it needs an FPU context.  Set the
-    FPU flag (which is saved as part of the task context). */
+     * FPU flag (which is saved as part of the task context). */
     ulPortTaskHasFPUContext = pdTRUE;
 
     /* Initialise the floating point status register. */
-    __asm volatile ( "FMXR  FPSCR, %0" :: "r" (ulInitialFPSCR) );
+    __asm volatile ( "FMXR  FPSCR, %0" ::"r" ( ulInitialFPSCR ) );
 }
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CRx_No_GIC/portmacro.h b/portable/IAR/ARM_CRx_No_GIC/portmacro.h
index 82853af3c..d7c18b1f7 100644
--- a/portable/IAR/ARM_CRx_No_GIC/portmacro.h
+++ b/portable/IAR/ARM_CRx_No_GIC/portmacro.h
@@ -48,55 +48,56 @@
  */
 
 /* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint32_t
-#define portBASE_TYPE   long
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
-typedef uint32_t TickType_t;
-#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+typedef uint32_t         TickType_t;
+#define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-not need to be guarded with a critical section. */
-#define portTICK_TYPE_IS_ATOMIC 1
+ * not need to be guarded with a critical section. */
+#define portTICK_TYPE_IS_ATOMIC    1
 
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portSTACK_GROWTH            ( -1 )
-#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT          8
+#define portSTACK_GROWTH      ( -1 )
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT    8
 
 /*-----------------------------------------------------------*/
 
 /* Task utilities. */
 
 /* Called at the end of an ISR that can cause a context switch. */
-#define portEND_SWITCHING_ISR( xSwitchRequired )\
-{                                               \
-extern volatile uint32_t ulPortYieldRequired;   \
-                                                \
-    if( xSwitchRequired != pdFALSE )            \
-    {                                           \
-        ulPortYieldRequired = pdTRUE;           \
-    }                                           \
-}
+#define portEND_SWITCHING_ISR( xSwitchRequired )      \
+    {                                                 \
+        extern volatile uint32_t ulPortYieldRequired; \
+                                                      \
+        if( xSwitchRequired != pdFALSE )              \
+        {                                             \
+            ulPortYieldRequired = pdTRUE;             \
+        }                                             \
+    }
 
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
-#define portYIELD() __asm volatile ( "SWI 0     \n"             \
-                                     "ISB         " );
+#define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
+#define portYIELD()                 \
+    __asm volatile ( "SWI 0     \n" \
+                     "ISB         " );
 
 
 /*-----------------------------------------------------------
- * Critical section control
- *----------------------------------------------------------*/
+* Critical section control
+*----------------------------------------------------------*/
 
 extern void vPortEnterCritical( void );
 extern void vPortExitCritical( void );
@@ -108,70 +109,72 @@ extern void vPortInstallFreeRTOSVectorTable( void );
 #define portINTERRUPT_ENABLE_BIT    ( 1 << 7 )
 
 /* In the absence of a priority mask register, these functions and macros
-globally enable and disable interrupts. */
-#define portENTER_CRITICAL()        vPortEnterCritical();
-#define portEXIT_CRITICAL()         vPortExitCritical();
-#define portENABLE_INTERRUPTS()     __asm volatile ( "CPSIE i   \n" );
-#define portDISABLE_INTERRUPTS()    __asm volatile ( "CPSID i   \n"     \
-                                                     "DSB       \n"     \
-                                                     "ISB         " );
+ * globally enable and disable interrupts. */
+#define portENTER_CRITICAL()       vPortEnterCritical();
+#define portEXIT_CRITICAL()        vPortExitCritical();
+#define portENABLE_INTERRUPTS()    __asm volatile ( "CPSIE i   \n" );
+#define portDISABLE_INTERRUPTS()    \
+    __asm volatile ( "CPSID i   \n" \
+                     "DSB       \n" \
+                     "ISB         " );
 #pragma inline
 static inline uint32_t portINLINE_SET_INTERRUPT_MASK_FROM_ISR( void )
 {
-volatile uint32_t ulCPSR;
+    volatile uint32_t ulCPSR;
+
+    __asm volatile ( "MRS %0, CPSR" : "=r" ( ulCPSR ) );
 
-    __asm volatile ( "MRS %0, CPSR" : "=r" (ulCPSR) );
     ulCPSR &= portINTERRUPT_ENABLE_BIT;
     portDISABLE_INTERRUPTS();
     return ulCPSR;
 }
 
-#define portSET_INTERRUPT_MASK_FROM_ISR() portINLINE_SET_INTERRUPT_MASK_FROM_ISR()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)    do { if( x == 0 ) portENABLE_INTERRUPTS(); } while( 0 )
+#define portSET_INTERRUPT_MASK_FROM_ISR()         portINLINE_SET_INTERRUPT_MASK_FROM_ISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    do { if( x == 0 ) portENABLE_INTERRUPTS( ); } while( 0 )
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site.  These are
-not required for this port but included in case common demo code that uses these
-macros is used. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )  void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )    void vFunction( void *pvParameters )
+ * not required for this port but included in case common demo code that uses these
+ * macros is used. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
 /* Prototype of the FreeRTOS tick handler.  This must be installed as the
-handler for whichever peripheral is used to generate the RTOS tick. */
+ * handler for whichever peripheral is used to generate the RTOS tick. */
 void FreeRTOS_Tick_Handler( void );
 
 /* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
-before any floating point instructions are executed. */
+ * before any floating point instructions are executed. */
 void vPortTaskUsesFPU( void );
-#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
+#define portTASK_USES_FLOATING_POINT()    vPortTaskUsesFPU()
 
-#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
-#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
+#define portLOWEST_INTERRUPT_PRIORITY           ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
+#define portLOWEST_USABLE_INTERRUPT_PRIORITY    ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
 
 /* Architecture specific optimisations. */
 #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-    #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+    #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
 #endif
 
 #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
 
-    /* Store/clear the ready priorities in a bit map. */
-    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+/* Store/clear the ready priorities in a bit map. */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 
-    /*-----------------------------------------------------------*/
+/*-----------------------------------------------------------*/
 
-    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __CLZ( uxReadyPriorities ) )
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ( uint32_t ) __CLZ( uxReadyPriorities ) )
 
 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 
-#define portNOP() __asm volatile( "NOP" )
-#define portINLINE inline
+#define portNOP()    __asm volatile ( "NOP" )
+#define portINLINE    inline
 
 /* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
-the source code because to do so would cause other compilers to generate
-warnings. */
+ * the source code because to do so would cause other compilers to generate
+ * warnings. */
 #pragma diag_suppress=Pe191
 #pragma diag_suppress=Pa082
 
diff --git a/portable/IAR/ATMega323/port.c b/portable/IAR/ATMega323/port.c
index 19aac2476..991713789 100644
--- a/portable/IAR/ATMega323/port.c
+++ b/portable/IAR/ATMega323/port.c
@@ -32,8 +32,8 @@
 #include "task.h"
 
 /*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the AVR/IAR port.
- *----------------------------------------------------------*/
+* Implementation of functions defined in portable.h for the AVR/IAR port.
+*----------------------------------------------------------*/
 
 /* Start tasks with interrupts enables. */
 #define portFLAGS_INT_ENABLED                   ( ( StackType_t ) 0x80 )
@@ -49,8 +49,8 @@
 /*-----------------------------------------------------------*/
 
 /* Stores the critical section nesting.  This must not be initialised to 0.
-It will be initialised when a task starts. */
-#define portNO_CRITICAL_NESTING                 ( ( UBaseType_t ) 0 )
+ * It will be initialised when a task starts. */
+#define portNO_CRITICAL_NESTING    ( ( UBaseType_t ) 0 )
 UBaseType_t uxCriticalNesting = 0x50;
 
 
@@ -71,13 +71,15 @@ extern void vPortStart( void );
 /*
  * See header file for description.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
-uint16_t usAddress;
-StackType_t *pxTopOfHardwareStack;
+    uint16_t usAddress;
+    StackType_t * pxTopOfHardwareStack;
 
     /* Place a few bytes of known values on the bottom of the stack.
-    This is just useful for debugging. */
+     * This is just useful for debugging. */
 
     *pxTopOfStack = 0x11;
     pxTopOfStack--;
@@ -87,7 +89,7 @@ StackType_t *pxTopOfHardwareStack;
     pxTopOfStack--;
 
     /* Remember where the top of the hardware stack is - this is required
-    below. */
+     * below. */
     pxTopOfHardwareStack = pxTopOfStack;
 
 
@@ -98,20 +100,20 @@ StackType_t *pxTopOfHardwareStack;
 
 
     /* The IAR compiler requires two stacks per task.  First there is the
-    hardware call stack which uses the AVR stack pointer.  Second there is the
-    software stack (local variables, parameter passing, etc.) which uses the
-    AVR Y register.
-
-    This function places both stacks within the memory block passed in as the
-    first parameter.  The hardware stack is placed at the bottom of the memory
-    block.  A gap is then left for the hardware stack to grow.  Next the software
-    stack is placed.  The amount of space between the software and hardware
-    stacks is defined by configCALL_STACK_SIZE.
-
-
-
-    The first part of the stack is the hardware stack.  Place the start
-    address of the task on the hardware stack. */
+     * hardware call stack which uses the AVR stack pointer.  Second there is the
+     * software stack (local variables, parameter passing, etc.) which uses the
+     * AVR Y register.
+     *
+     * This function places both stacks within the memory block passed in as the
+     * first parameter.  The hardware stack is placed at the bottom of the memory
+     * block.  A gap is then left for the hardware stack to grow.  Next the software
+     * stack is placed.  The amount of space between the software and hardware
+     * stacks is defined by configCALL_STACK_SIZE.
+     *
+     *
+     *
+     * The first part of the stack is the hardware stack.  Place the start
+     * address of the task on the hardware stack. */
     usAddress = ( uint16_t ) pxCode;
     *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
     pxTopOfStack--;
@@ -122,23 +124,23 @@ StackType_t *pxTopOfHardwareStack;
 
 
     /* Leave enough space for the hardware stack before starting the software
-    stack.  The '- 2' is because we have already used two spaces for the
-    address of the start of the task. */
+     * stack.  The '- 2' is because we have already used two spaces for the
+     * address of the start of the task. */
     pxTopOfStack -= ( configCALL_STACK_SIZE - 2 );
 
 
 
     /* Next simulate the stack as if after a call to portSAVE_CONTEXT().
-    portSAVE_CONTEXT places the flags on the stack immediately after r0
-    to ensure the interrupts get disabled as soon as possible, and so ensuring
-    the stack use is minimal should a context switch interrupt occur. */
-    *pxTopOfStack = ( StackType_t ) 0x00;   /* R0 */
+     *  portSAVE_CONTEXT places the flags on the stack immediately after r0
+     *  to ensure the interrupts get disabled as soon as possible, and so ensuring
+     *  the stack use is minimal should a context switch interrupt occur. */
+    *pxTopOfStack = ( StackType_t ) 0x00; /* R0 */
     pxTopOfStack--;
     *pxTopOfStack = portFLAGS_INT_ENABLED;
     pxTopOfStack--;
 
     /* Next place the address of the hardware stack.  This is required so
-    the AVR stack pointer can be restored to point to the hardware stack. */
+     * the AVR stack pointer can be restored to point to the hardware stack. */
     pxTopOfHardwareStack -= portBYTES_USED_BY_RETURN_ADDRESS;
     usAddress = ( uint16_t ) pxTopOfHardwareStack;
 
@@ -153,37 +155,36 @@ StackType_t *pxTopOfHardwareStack;
 
 
 
-
     /* Now the remaining registers. */
-    *pxTopOfStack = ( StackType_t ) 0x01;   /* R1 */
+    *pxTopOfStack = ( StackType_t ) 0x01; /* R1 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x02;   /* R2 */
+    *pxTopOfStack = ( StackType_t ) 0x02; /* R2 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x03;   /* R3 */
+    *pxTopOfStack = ( StackType_t ) 0x03; /* R3 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x04;   /* R4 */
+    *pxTopOfStack = ( StackType_t ) 0x04; /* R4 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x05;   /* R5 */
+    *pxTopOfStack = ( StackType_t ) 0x05; /* R5 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x06;   /* R6 */
+    *pxTopOfStack = ( StackType_t ) 0x06; /* R6 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x07;   /* R7 */
+    *pxTopOfStack = ( StackType_t ) 0x07; /* R7 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x08;   /* R8 */
+    *pxTopOfStack = ( StackType_t ) 0x08; /* R8 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x09;   /* R9 */
+    *pxTopOfStack = ( StackType_t ) 0x09; /* R9 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x10;   /* R10 */
+    *pxTopOfStack = ( StackType_t ) 0x10; /* R10 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x11;   /* R11 */
+    *pxTopOfStack = ( StackType_t ) 0x11; /* R11 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x12;   /* R12 */
+    *pxTopOfStack = ( StackType_t ) 0x12; /* R12 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x13;   /* R13 */
+    *pxTopOfStack = ( StackType_t ) 0x13; /* R13 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x14;   /* R14 */
+    *pxTopOfStack = ( StackType_t ) 0x14; /* R14 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x15;   /* R15 */
+    *pxTopOfStack = ( StackType_t ) 0x15; /* R15 */
     pxTopOfStack--;
 
     /* Place the parameter on the stack in the expected location. */
@@ -195,36 +196,36 @@ StackType_t *pxTopOfHardwareStack;
     *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
     pxTopOfStack--;
 
-    *pxTopOfStack = ( StackType_t ) 0x18;   /* R18 */
+    *pxTopOfStack = ( StackType_t ) 0x18; /* R18 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x19;   /* R19 */
+    *pxTopOfStack = ( StackType_t ) 0x19; /* R19 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x20;   /* R20 */
+    *pxTopOfStack = ( StackType_t ) 0x20; /* R20 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x21;   /* R21 */
+    *pxTopOfStack = ( StackType_t ) 0x21; /* R21 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x22;   /* R22 */
+    *pxTopOfStack = ( StackType_t ) 0x22; /* R22 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x23;   /* R23 */
+    *pxTopOfStack = ( StackType_t ) 0x23; /* R23 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x24;   /* R24 */
+    *pxTopOfStack = ( StackType_t ) 0x24; /* R24 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x25;   /* R25 */
+    *pxTopOfStack = ( StackType_t ) 0x25; /* R25 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x26;   /* R26 X */
+    *pxTopOfStack = ( StackType_t ) 0x26; /* R26 X */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x27;   /* R27 */
+    *pxTopOfStack = ( StackType_t ) 0x27; /* R27 */
     pxTopOfStack--;
 
     /* The Y register is not stored as it is used as the software stack and
-    gets saved into the task control block. */
+     * gets saved into the task control block. */
 
-    *pxTopOfStack = ( StackType_t ) 0x30;   /* R30 Z */
+    *pxTopOfStack = ( StackType_t ) 0x30;  /* R30 Z */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x031;  /* R31 */
+    *pxTopOfStack = ( StackType_t ) 0x031; /* R31 */
 
     pxTopOfStack--;
-    *pxTopOfStack = portNO_CRITICAL_NESTING;    /* Critical nesting is zero when the task starts. */
+    *pxTopOfStack = portNO_CRITICAL_NESTING; /* Critical nesting is zero when the task starts. */
 
     /*lint +e950 +e611 +e923 */
 
@@ -238,8 +239,8 @@ BaseType_t xPortStartScheduler( void )
     prvSetupTimerInterrupt();
 
     /* Restore the context of the first task that is going to run.
-    Normally we would just call portRESTORE_CONTEXT() here, but as the IAR
-    compiler does not fully support inline assembler we have to make a call.*/
+     * Normally we would just call portRESTORE_CONTEXT() here, but as the IAR
+     * compiler does not fully support inline assembler we have to make a call.*/
     vPortStart();
 
     /* Should not get here! */
@@ -250,7 +251,7 @@ BaseType_t xPortStartScheduler( void )
 void vPortEndScheduler( void )
 {
     /* It is unlikely that the AVR port will get stopped.  If required simply
-    disable the tick interrupt here. */
+     * disable the tick interrupt here. */
 }
 /*-----------------------------------------------------------*/
 
@@ -259,11 +260,11 @@ void vPortEndScheduler( void )
  */
 static void prvSetupTimerInterrupt( void )
 {
-uint32_t ulCompareMatch;
-uint8_t ucHighByte, ucLowByte;
+    uint32_t ulCompareMatch;
+    uint8_t ucHighByte, ucLowByte;
 
     /* Using 16bit timer 1 to generate the tick.  Correct fuses must be
-    selected for the configCPU_CLOCK_HZ clock. */
+     * selected for the configCPU_CLOCK_HZ clock. */
 
     ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
 
@@ -274,7 +275,7 @@ uint8_t ucHighByte, ucLowByte;
     ulCompareMatch -= ( uint32_t ) 1;
 
     /* Setup compare match value for compare match A.  Interrupts are disabled
-    before this is called so we need not worry here. */
+     * before this is called so we need not worry here. */
     ucLowByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff );
     ulCompareMatch >>= 8;
     ucHighByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff );
@@ -286,39 +287,39 @@ uint8_t ucHighByte, ucLowByte;
     TCCR1B = ucLowByte;
 
     /* Enable the interrupt - this is okay as interrupt are currently globally
-    disabled. */
+     * disabled. */
     TIMSK |= portCOMPARE_MATCH_A_INTERRUPT_ENABLE;
 }
 /*-----------------------------------------------------------*/
 
 #if configUSE_PREEMPTION == 1
 
-    /*
-     * Tick ISR for preemptive scheduler.  We can use a __task attribute as
-     * the context is saved at the start of vPortYieldFromTick().  The tick
-     * count is incremented after the context is saved.
-     */
+/*
+ * Tick ISR for preemptive scheduler.  We can use a __task attribute as
+ * the context is saved at the start of vPortYieldFromTick().  The tick
+ * count is incremented after the context is saved.
+ */
     __task void SIG_OUTPUT_COMPARE1A( void )
     {
         vPortYieldFromTick();
-        asm( "reti" );
+        asm ( "reti" );
     }
 
 #else
 
-    /*
-     * Tick ISR for the cooperative scheduler.  All this does is increment the
-     * tick count.  We don't need to switch context, this can only be done by
-     * manual calls to taskYIELD();
-     *
-     * THE INTERRUPT VECTOR IS POPULATED IN portmacro.s90.  DO NOT INSTALL
-     * IT HERE USING THE USUAL PRAGMA.
-     */
+/*
+ * Tick ISR for the cooperative scheduler.  All this does is increment the
+ * tick count.  We don't need to switch context, this can only be done by
+ * manual calls to taskYIELD();
+ *
+ * THE INTERRUPT VECTOR IS POPULATED IN portmacro.s90.  DO NOT INSTALL
+ * IT HERE USING THE USUAL PRAGMA.
+ */
     __interrupt void SIG_OUTPUT_COMPARE1A( void )
     {
         xTaskIncrementTick();
     }
-#endif
+#endif /* if configUSE_PREEMPTION == 1 */
 /*-----------------------------------------------------------*/
 
 void vPortEnterCritical( void )
@@ -331,6 +332,7 @@ void vPortEnterCritical( void )
 void vPortExitCritical( void )
 {
     uxCriticalNesting--;
+
     if( uxCriticalNesting == portNO_CRITICAL_NESTING )
     {
         portENABLE_INTERRUPTS();
diff --git a/portable/IAR/ATMega323/portmacro.h b/portable/IAR/ATMega323/portmacro.h
index cbc7b2d15..0a870ae21 100644
--- a/portable/IAR/ATMega323/portmacro.h
+++ b/portable/IAR/ATMega323/portmacro.h
@@ -27,11 +27,11 @@
  */
 
 /*
-Changes from V1.2.3
-
-    + portCPU_CLOSK_HZ definition changed to 8MHz base 10, previously it
-      base 16.
-*/
+ * Changes from V1.2.3
+ *
+ + portCPU_CLOCK_HZ definition changed to 8MHz base 10, previously it
+ +    base 16.
+ */
 
 #ifndef PORTMACRO_H
 #define PORTMACRO_H
@@ -53,25 +53,25 @@ Changes from V1.2.3
  */
 
 /* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       int
-#define portSTACK_TYPE  uint8_t
-#define portBASE_TYPE   char
-#define portPOINTER_SIZE_TYPE uint16_t
+#define portCHAR                 char
+#define portFLOAT                float
+#define portDOUBLE               double
+#define portLONG                 long
+#define portSHORT                int
+#define portSTACK_TYPE           uint8_t
+#define portBASE_TYPE            char
+#define portPOINTER_SIZE_TYPE    uint16_t
 
-typedef portSTACK_TYPE StackType_t;
-typedef signed char BaseType_t;
-typedef unsigned char UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef signed char      BaseType_t;
+typedef unsigned char    UBaseType_t;
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY ( TickType_t )    ( 0xFFFFFFFFUL )
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) ( 0xFFFFFFFFUL )
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
@@ -81,32 +81,32 @@ typedef unsigned char UBaseType_t;
 /* Critical section management. */
 extern void vPortEnterCritical( void );
 extern void vPortExitCritical( void );
-#define portENTER_CRITICAL()    vPortEnterCritical()
-#define portEXIT_CRITICAL()     vPortExitCritical()
+#define portENTER_CRITICAL()        vPortEnterCritical()
+#define portEXIT_CRITICAL()         vPortExitCritical()
 
-#define portDISABLE_INTERRUPTS()    asm( "cli" )
-#define portENABLE_INTERRUPTS()     asm( "sei" )
+#define portDISABLE_INTERRUPTS()    asm ( "cli" )
+#define portENABLE_INTERRUPTS()     asm ( "sei" )
 /*-----------------------------------------------------------*/
 
 /* Architecture specifics. */
-#define portSTACK_GROWTH            ( -1 )
-#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT          1
-#define portNOP()                   asm( "nop" )
+#define portSTACK_GROWTH      ( -1 )
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT    1
+#define portNOP()    asm ( "nop" )
 /*-----------------------------------------------------------*/
 
 /* Kernel utilities. */
 void vPortYield( void );
-#define portYIELD() vPortYield()
+#define portYIELD()                vPortYield()
 
 #ifdef IAR_MEGA_AVR
-    #define outb( PORT, VALUE ) PORT = VALUE
+    #define outb( PORT, VALUE )    PORT = VALUE
 #endif
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/IAR/AVR32_UC3/port.c b/portable/IAR/AVR32_UC3/port.c
index 00d51af2a..94fa1e37a 100644
--- a/portable/IAR/AVR32_UC3/port.c
+++ b/portable/IAR/AVR32_UC3/port.c
@@ -27,6 +27,7 @@
  */
 
 /*This file has been prepared for Doxygen automatic documentation generation.*/
+
 /*! \file *********************************************************************
  *
  * \brief FreeRTOS port source for AVR32 UC3.
@@ -82,20 +83,20 @@
     #include "usart.h"
 #endif
 
-#if( configTICK_USE_TC==1 )
+#if ( configTICK_USE_TC == 1 )
     #include "tc.h"
 #endif
 
 
 /* Constants required to setup the task context. */
-#define portINITIAL_SR            ( ( StackType_t ) 0x00400000 ) /* AVR32 : [M2:M0]=001 I1M=0 I0M=0, GM=0 */
-#define portINSTRUCTION_SIZE      ( ( StackType_t ) 0 )
+#define portINITIAL_SR             ( ( StackType_t ) 0x00400000 ) /* AVR32 : [M2:M0]=001 I1M=0 I0M=0, GM=0 */
+#define portINSTRUCTION_SIZE       ( ( StackType_t ) 0 )
 
 /* Each task maintains its own critical nesting variable. */
-#define portNO_CRITICAL_NESTING   ( ( uint32_t ) 0 )
+#define portNO_CRITICAL_NESTING    ( ( uint32_t ) 0 )
 volatile uint32_t ulCriticalNesting = 9999UL;
 
-#if( configTICK_USE_TC==0 )
+#if ( configTICK_USE_TC == 0 )
     static void prvScheduleNextTick( void );
 #else
     static void prvClearTcInt( void );
@@ -110,11 +111,11 @@ static void prvSetupTimerInterrupt( void );
  * Low-level initialization routine called during startup, before the main
  * function.
  */
-int __low_level_init(void)
+int __low_level_init( void )
 {
     #if configHEAP_INIT
-        #pragma segment = "HEAP"
-        BaseType_t *pxMem;
+    #pragma segment = "HEAP"
+        BaseType_t * pxMem;
     #endif
 
     /* Enable exceptions. */
@@ -144,21 +145,21 @@ int __low_level_init(void)
 
         static const usart_options_t DBG_USART_OPTIONS =
         {
-            .baudrate = configDBG_USART_BAUDRATE,
-            .charlength = 8,
-            .paritytype = USART_NO_PARITY,
-            .stopbits = USART_1_STOPBIT,
+            .baudrate    = configDBG_USART_BAUDRATE,
+            .charlength  = 8,
+            .paritytype  = USART_NO_PARITY,
+            .stopbits    = USART_1_STOPBIT,
             .channelmode = USART_NORMAL_CHMODE
         };
 
         /* Initialize the USART used for the debug trace with the configured parameters. */
-        extern volatile avr32_usart_t *volatile stdio_usart_base;
+        extern volatile avr32_usart_t * volatile stdio_usart_base;
         stdio_usart_base = configDBG_USART;
         gpio_enable_module( DBG_USART_GPIO_MAP,
-                            sizeof( DBG_USART_GPIO_MAP ) / sizeof( DBG_USART_GPIO_MAP[0] ) );
-        usart_init_rs232(configDBG_USART, &DBG_USART_OPTIONS, configCPU_CLOCK_HZ);
+                            sizeof( DBG_USART_GPIO_MAP ) / sizeof( DBG_USART_GPIO_MAP[ 0 ] ) );
+        usart_init_rs232( configDBG_USART, &DBG_USART_OPTIONS, configCPU_CLOCK_HZ );
     }
-    #endif
+    #endif /* if configDBG */
 
     /* Request initialization of data segments. */
     return 1;
@@ -166,9 +167,10 @@ int __low_level_init(void)
 /*-----------------------------------------------------------*/
 
 /* Added as there is no such function in FreeRTOS. */
-void *pvPortRealloc( void *pv, size_t xWantedSize )
+void * pvPortRealloc( void * pv,
+                      size_t xWantedSize )
 {
-void *pvReturn;
+    void * pvReturn;
 
     vTaskSuspendAll();
     {
@@ -181,28 +183,30 @@ void *pvReturn;
 /*-----------------------------------------------------------*/
 
 /* The cooperative scheduler requires a normal IRQ service routine to
-simply increment the system tick. */
+ * simply increment the system tick. */
+
 /* The preemptive scheduler is defined as "naked" as the full context is saved
-on entry as part of the context switch. */
-#pragma shadow_registers = full   // Naked.
+ * on entry as part of the context switch. */
+#pragma shadow_registers = full /* Naked. */
 static void vTick( void )
 {
     /* Save the context of the interrupted task. */
     portSAVE_CONTEXT_OS_INT();
 
-    #if( configTICK_USE_TC==1 )
+    #if ( configTICK_USE_TC == 1 )
         /* Clear the interrupt flag. */
         prvClearTcInt();
     #else
+
         /* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)
-        clock cycles from now. */
+         * clock cycles from now. */
         prvScheduleNextTick();
     #endif
 
     /* Because FreeRTOS is not supposed to run with nested interrupts, put all OS
-    calls in a critical section . */
+     * calls in a critical section . */
     portENTER_CRITICAL();
-        xTaskIncrementTick();
+    xTaskIncrementTick();
     portEXIT_CRITICAL();
 
     /* Restore the context of the "elected task". */
@@ -210,7 +214,7 @@ static void vTick( void )
 }
 /*-----------------------------------------------------------*/
 
-#pragma shadow_registers = full   // Naked.
+#pragma shadow_registers = full /* Naked. */
 void SCALLYield( void )
 {
     /* Save the context of the interrupted task. */
@@ -221,18 +225,18 @@ void SCALLYield( void )
 /*-----------------------------------------------------------*/
 
 /* The code generated by the GCC compiler uses the stack in different ways at
-different optimisation levels.  The interrupt flags can therefore not always
-be saved to the stack.  Instead the critical section nesting level is stored
-in a variable, which is then saved as part of the stack context. */
+ * different optimisation levels.  The interrupt flags can therefore not always
+ * be saved to the stack.  Instead the critical section nesting level is stored
+ * in a variable, which is then saved as part of the stack context. */
 #pragma optimize = no_inline
 void vPortEnterCritical( void )
 {
     /* Disable interrupts */
     portDISABLE_INTERRUPTS();
 
-    /* Now interrupts are disabled ulCriticalNesting can be accessed
-     directly.  Increment ulCriticalNesting to keep a count of how many times
-     portENTER_CRITICAL() has been called. */
+    /* Now that interrupts are disabled, ulCriticalNesting can be accessed
+     * directly.  Increment ulCriticalNesting to keep a count of how many times
+     * portENTER_CRITICAL() has been called. */
     ulCriticalNesting++;
 }
 /*-----------------------------------------------------------*/
@@ -240,9 +244,10 @@ void vPortEnterCritical( void )
 #pragma optimize = no_inline
 void vPortExitCritical( void )
 {
-    if(ulCriticalNesting > portNO_CRITICAL_NESTING)
+    if( ulCriticalNesting > portNO_CRITICAL_NESTING )
     {
         ulCriticalNesting--;
+
         if( ulCriticalNesting == portNO_CRITICAL_NESTING )
         {
             /* Enable all interrupt/exception. */
@@ -258,30 +263,32 @@ void vPortExitCritical( void )
  *
  * See header file for description.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
     /* Setup the initial stack of the task.  The stack is set exactly as
-    expected by the portRESTORE_CONTEXT() macro. */
+     * expected by the portRESTORE_CONTEXT() macro. */
 
     /* When the task starts, it will expect to find the function parameter in R12. */
     pxTopOfStack--;
-    *pxTopOfStack-- = ( StackType_t ) 0x08080808;                   /* R8 */
-    *pxTopOfStack-- = ( StackType_t ) 0x09090909;                   /* R9 */
-    *pxTopOfStack-- = ( StackType_t ) 0x0A0A0A0A;                   /* R10 */
-    *pxTopOfStack-- = ( StackType_t ) 0x0B0B0B0B;                   /* R11 */
-    *pxTopOfStack-- = ( StackType_t ) pvParameters;                 /* R12 */
-    *pxTopOfStack-- = ( StackType_t ) 0xDEADBEEF;                   /* R14/LR */
+    *pxTopOfStack-- = ( StackType_t ) 0x08080808;                    /* R8 */
+    *pxTopOfStack-- = ( StackType_t ) 0x09090909;                    /* R9 */
+    *pxTopOfStack-- = ( StackType_t ) 0x0A0A0A0A;                    /* R10 */
+    *pxTopOfStack-- = ( StackType_t ) 0x0B0B0B0B;                    /* R11 */
+    *pxTopOfStack-- = ( StackType_t ) pvParameters;                  /* R12 */
+    *pxTopOfStack-- = ( StackType_t ) 0xDEADBEEF;                    /* R14/LR */
     *pxTopOfStack-- = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; /* R15/PC */
-    *pxTopOfStack-- = ( StackType_t ) portINITIAL_SR;               /* SR */
-    *pxTopOfStack-- = ( StackType_t ) 0xFF0000FF;                   /* R0 */
-    *pxTopOfStack-- = ( StackType_t ) 0x01010101;                   /* R1 */
-    *pxTopOfStack-- = ( StackType_t ) 0x02020202;                   /* R2 */
-    *pxTopOfStack-- = ( StackType_t ) 0x03030303;                   /* R3 */
-    *pxTopOfStack-- = ( StackType_t ) 0x04040404;                   /* R4 */
-    *pxTopOfStack-- = ( StackType_t ) 0x05050505;                   /* R5 */
-    *pxTopOfStack-- = ( StackType_t ) 0x06060606;                   /* R6 */
-    *pxTopOfStack-- = ( StackType_t ) 0x07070707;                   /* R7 */
-    *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_NESTING;            /* ulCriticalNesting */
+    *pxTopOfStack-- = ( StackType_t ) portINITIAL_SR;                /* SR */
+    *pxTopOfStack-- = ( StackType_t ) 0xFF0000FF;                    /* R0 */
+    *pxTopOfStack-- = ( StackType_t ) 0x01010101;                    /* R1 */
+    *pxTopOfStack-- = ( StackType_t ) 0x02020202;                    /* R2 */
+    *pxTopOfStack-- = ( StackType_t ) 0x03030303;                    /* R3 */
+    *pxTopOfStack-- = ( StackType_t ) 0x04040404;                    /* R4 */
+    *pxTopOfStack-- = ( StackType_t ) 0x05050505;                    /* R5 */
+    *pxTopOfStack-- = ( StackType_t ) 0x06060606;                    /* R6 */
+    *pxTopOfStack-- = ( StackType_t ) 0x07070707;                    /* R7 */
+    *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_NESTING;         /* ulCriticalNesting */
 
     return pxTopOfStack;
 }
@@ -290,7 +297,7 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
 BaseType_t xPortStartScheduler( void )
 {
     /* Start the timer that generates the tick ISR.  Interrupts are disabled
-    here already. */
+     * here already. */
     prvSetupTimerInterrupt();
 
     /* Start the first task. */
@@ -304,132 +311,136 @@ BaseType_t xPortStartScheduler( void )
 void vPortEndScheduler( void )
 {
     /* It is unlikely that the AVR32 port will require this function as there
-    is nothing to return to.  */
+     * is nothing to return to.  */
 }
 /*-----------------------------------------------------------*/
 
 /* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)
-clock cycles from now. */
-#if( configTICK_USE_TC==0 )
-    static void prvScheduleFirstTick(void)
+ * clock cycles from now. */
+#if ( configTICK_USE_TC == 0 )
+    static void prvScheduleFirstTick( void )
     {
         uint32_t lCycles;
 
-        lCycles = Get_system_register(AVR32_COUNT);
-        lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
-        // If lCycles ends up to be 0, make it 1 so that the COMPARE and exception
-        // generation feature does not get disabled.
-        if(0 == lCycles)
+        lCycles = Get_system_register( AVR32_COUNT );
+        lCycles += ( configCPU_CLOCK_HZ / configTICK_RATE_HZ );
+
+        /* If lCycles ends up to be 0, make it 1 so that the COMPARE and exception */
+        /* generation feature does not get disabled. */
+        if( 0 == lCycles )
         {
             lCycles++;
         }
-        Set_system_register(AVR32_COMPARE, lCycles);
+
+        Set_system_register( AVR32_COMPARE, lCycles );
     }
 
     #pragma optimize = no_inline
-    static void prvScheduleNextTick(void)
+    static void prvScheduleNextTick( void )
     {
         uint32_t lCycles, lCount;
 
-        lCycles = Get_system_register(AVR32_COMPARE);
-        lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
-        // If lCycles ends up to be 0, make it 1 so that the COMPARE and exception
-        // generation feature does not get disabled.
-        if(0 == lCycles)
+        lCycles = Get_system_register( AVR32_COMPARE );
+        lCycles += ( configCPU_CLOCK_HZ / configTICK_RATE_HZ );
+
+        /* If lCycles ends up to be 0, make it 1 so that the COMPARE and exception */
+        /* generation feature does not get disabled. */
+        if( 0 == lCycles )
         {
             lCycles++;
         }
-        lCount = Get_system_register(AVR32_COUNT);
+
+        lCount = Get_system_register( AVR32_COUNT );
+
         if( lCycles < lCount )
-        {       // We missed a tick, recover for the next.
-            lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
+        { /* We missed a tick, recover for the next. */
+            lCycles += ( configCPU_CLOCK_HZ / configTICK_RATE_HZ );
         }
-        Set_system_register(AVR32_COMPARE, lCycles);
+
+        Set_system_register( AVR32_COMPARE, lCycles );
     }
-#else
+#else /* if ( configTICK_USE_TC == 0 ) */
     #pragma optimize = no_inline
-    static void prvClearTcInt(void)
+    static void prvClearTcInt( void )
     {
-        AVR32_TC.channel[configTICK_TC_CHANNEL].sr;
+        AVR32_TC.channel[ configTICK_TC_CHANNEL ].sr;
     }
-#endif
+#endif /* if ( configTICK_USE_TC == 0 ) */
 /*-----------------------------------------------------------*/
 
 /* Setup the timer to generate the tick interrupts. */
-static void prvSetupTimerInterrupt(void)
+static void prvSetupTimerInterrupt( void )
 {
-    #if( configTICK_USE_TC==1 )
+    #if ( configTICK_USE_TC == 1 )
+        volatile avr32_tc_t * tc = &AVR32_TC;
 
-        volatile avr32_tc_t *tc = &AVR32_TC;
-
-        // Options for waveform genration.
+        /* Options for waveform genration. */
         tc_waveform_opt_t waveform_opt =
         {
-        .channel  = configTICK_TC_CHANNEL,             /* Channel selection. */
+            .channel = configTICK_TC_CHANNEL,              /* Channel selection. */
 
-        .bswtrg   = TC_EVT_EFFECT_NOOP,                /* Software trigger effect on TIOB. */
-        .beevt    = TC_EVT_EFFECT_NOOP,                /* External event effect on TIOB. */
-        .bcpc     = TC_EVT_EFFECT_NOOP,                /* RC compare effect on TIOB. */
-        .bcpb     = TC_EVT_EFFECT_NOOP,                /* RB compare effect on TIOB. */
+            .bswtrg  = TC_EVT_EFFECT_NOOP,                 /* Software trigger effect on TIOB. */
+            .beevt   = TC_EVT_EFFECT_NOOP,                 /* External event effect on TIOB. */
+            .bcpc    = TC_EVT_EFFECT_NOOP,                 /* RC compare effect on TIOB. */
+            .bcpb    = TC_EVT_EFFECT_NOOP,                 /* RB compare effect on TIOB. */
 
-        .aswtrg   = TC_EVT_EFFECT_NOOP,                /* Software trigger effect on TIOA. */
-        .aeevt    = TC_EVT_EFFECT_NOOP,                /* External event effect on TIOA. */
-        .acpc     = TC_EVT_EFFECT_NOOP,                /* RC compare effect on TIOA: toggle. */
-        .acpa     = TC_EVT_EFFECT_NOOP,                /* RA compare effect on TIOA: toggle (other possibilities are none, set and clear). */
+            .aswtrg  = TC_EVT_EFFECT_NOOP,                 /* Software trigger effect on TIOA. */
+            .aeevt   = TC_EVT_EFFECT_NOOP,                 /* External event effect on TIOA. */
+            .acpc    = TC_EVT_EFFECT_NOOP,                 /* RC compare effect on TIOA: toggle. */
+            .acpa    = TC_EVT_EFFECT_NOOP,                 /* RA compare effect on TIOA: toggle (other possibilities are none, set and clear). */
 
-        .wavsel   = TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER,/* Waveform selection: Up mode without automatic trigger on RC compare. */
-        .enetrg   = FALSE,                             /* External event trigger enable. */
-        .eevt     = 0,                                 /* External event selection. */
-        .eevtedg  = TC_SEL_NO_EDGE,                    /* External event edge selection. */
-        .cpcdis   = FALSE,                             /* Counter disable when RC compare. */
-        .cpcstop  = FALSE,                             /* Counter clock stopped with RC compare. */
+            .wavsel  = TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER, /* Waveform selection: Up mode without automatic trigger on RC compare. */
+            .enetrg  = FALSE,                              /* External event trigger enable. */
+            .eevt    = 0,                                  /* External event selection. */
+            .eevtedg = TC_SEL_NO_EDGE,                     /* External event edge selection. */
+            .cpcdis  = FALSE,                              /* Counter disable when RC compare. */
+            .cpcstop = FALSE,                              /* Counter clock stopped with RC compare. */
 
-        .burst    = FALSE,                             /* Burst signal selection. */
-        .clki     = FALSE,                             /* Clock inversion. */
-        .tcclks   = TC_CLOCK_SOURCE_TC2                /* Internal source clock 2. */
+            .burst   = FALSE,                              /* Burst signal selection. */
+            .clki    = FALSE,                              /* Clock inversion. */
+            .tcclks  = TC_CLOCK_SOURCE_TC2                 /* Internal source clock 2. */
         };
 
         tc_interrupt_t tc_interrupt =
         {
-            .etrgs=0,
-            .ldrbs=0,
-            .ldras=0,
-            .cpcs =1,
-            .cpbs =0,
-            .cpas =0,
-            .lovrs=0,
-            .covfs=0,
+            .etrgs = 0,
+            .ldrbs = 0,
+            .ldras = 0,
+            .cpcs  = 1,
+            .cpbs  = 0,
+            .cpas  = 0,
+            .lovrs = 0,
+            .covfs = 0,
         };
-
-    #endif
+    #endif /* if ( configTICK_USE_TC == 1 ) */
 
     /* Disable all interrupt/exception. */
     portDISABLE_INTERRUPTS();
 
     /* Register the compare interrupt handler to the interrupt controller and
-    enable the compare interrupt. */
+     * enable the compare interrupt. */
 
-    #if( configTICK_USE_TC==1 )
+    #if ( configTICK_USE_TC == 1 )
     {
-        INTC_register_interrupt((__int_handler)&vTick, configTICK_TC_IRQ, INT0);
+        INTC_register_interrupt( ( __int_handler ) & vTick, configTICK_TC_IRQ, INT0 );
 
         /* Initialize the timer/counter. */
-        tc_init_waveform(tc, &waveform_opt);
+        tc_init_waveform( tc, &waveform_opt );
 
         /* Set the compare triggers.
-        Remember TC counter is 16-bits, so counting second is not possible!
-        That's why we configure it to count ms. */
-        tc_write_rc( tc, configTICK_TC_CHANNEL, ( configPBA_CLOCK_HZ / 4) / configTICK_RATE_HZ );
+         * Remember TC counter is 16-bits, so counting second is not possible!
+         * That's why we configure it to count ms. */
+        tc_write_rc( tc, configTICK_TC_CHANNEL, ( configPBA_CLOCK_HZ / 4 ) / configTICK_RATE_HZ );
 
         tc_configure_interrupts( tc, configTICK_TC_CHANNEL, &tc_interrupt );
 
         /* Start the timer/counter. */
-        tc_start(tc, configTICK_TC_CHANNEL);
+        tc_start( tc, configTICK_TC_CHANNEL );
     }
-    #else
+    #else /* if ( configTICK_USE_TC == 1 ) */
     {
-        INTC_register_interrupt((__int_handler)&vTick, AVR32_CORE_COMPARE_IRQ, INT0);
+        INTC_register_interrupt( ( __int_handler ) & vTick, AVR32_CORE_COMPARE_IRQ, INT0 );
         prvScheduleFirstTick();
     }
-    #endif
+    #endif /* if ( configTICK_USE_TC == 1 ) */
 }
diff --git a/portable/IAR/AVR32_UC3/portmacro.h b/portable/IAR/AVR32_UC3/portmacro.h
index 98aa5be07..42f4bfe65 100644
--- a/portable/IAR/AVR32_UC3/portmacro.h
+++ b/portable/IAR/AVR32_UC3/portmacro.h
@@ -27,6 +27,7 @@
  */
 
 /*This file has been prepared for Doxygen automatic documentation generation.*/
+
 /*! \file *********************************************************************
  *
  * \brief FreeRTOS port header for AVR32 UC3.
@@ -95,31 +96,31 @@
 
 
 /* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint32_t
-#define portBASE_TYPE   long
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
 
-#define TASK_DELAY_MS(x)   ( (x)        /portTICK_PERIOD_MS )
-#define TASK_DELAY_S(x)    ( (x)*1000   /portTICK_PERIOD_MS )
-#define TASK_DELAY_MIN(x)  ( (x)*60*1000/portTICK_PERIOD_MS )
+#define TASK_DELAY_MS( x )     ( ( x ) / portTICK_PERIOD_MS )
+#define TASK_DELAY_S( x )      ( ( x ) * 1000 / portTICK_PERIOD_MS )
+#define TASK_DELAY_MIN( x )    ( ( x ) * 60 * 1000 / portTICK_PERIOD_MS )
 
-#define configTICK_TC_IRQ             ATPASTE2(AVR32_TC_IRQ, configTICK_TC_CHANNEL)
+#define configTICK_TC_IRQ    ATPASTE2( AVR32_TC_IRQ, configTICK_TC_CHANNEL )
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-  typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t   TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY ( TickType_t )    ( 0xFFFFFFFFUL )
+    typedef uint32_t   TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) ( 0xFFFFFFFFUL )
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
@@ -127,23 +128,23 @@ typedef unsigned long UBaseType_t;
 
 /* Architecture specifics. */
 #define portSTACK_GROWTH      ( -1 )
-#define portTICK_PERIOD_MS      ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT       4
-#define portNOP()             {__asm__ __volatile__ ("nop");}
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT    4
+#define portNOP()    { __asm__ __volatile__ ( "nop" ); }
 /*-----------------------------------------------------------*/
 
 
 /*-----------------------------------------------------------*/
 
 /* INTC-specific. */
-#define DISABLE_ALL_EXCEPTIONS()    Disable_global_exception()
-#define ENABLE_ALL_EXCEPTIONS()     Enable_global_exception()
+#define DISABLE_ALL_EXCEPTIONS()        Disable_global_exception()
+#define ENABLE_ALL_EXCEPTIONS()         Enable_global_exception()
 
-#define DISABLE_ALL_INTERRUPTS()    Disable_global_interrupt()
-#define ENABLE_ALL_INTERRUPTS()     Enable_global_interrupt()
+#define DISABLE_ALL_INTERRUPTS()        Disable_global_interrupt()
+#define ENABLE_ALL_INTERRUPTS()         Enable_global_interrupt()
 
-#define DISABLE_INT_LEVEL(int_lev)  Disable_interrupt_level(int_lev)
-#define ENABLE_INT_LEVEL(int_lev)   Enable_interrupt_level(int_lev)
+#define DISABLE_INT_LEVEL( int_lev )    Disable_interrupt_level( int_lev )
+#define ENABLE_INT_LEVEL( int_lev )     Enable_interrupt_level( int_lev )
 
 
 /*
@@ -160,31 +161,32 @@ typedef unsigned long UBaseType_t;
  * which is interrupt-unsafe with the current __malloc_lock and __malloc_unlock.
  */
 #if configDBG
-    #define portDBG_TRACE(...)                                              \
-    {                                                                       \
-      fputs(__FILE__ ":" ASTRINGZ(__LINE__) ": ", stdout);                  \
-      printf(__VA_ARGS__);                                                  \
-      fputs("\r\n", stdout);                                                \
+    #define portDBG_TRACE( ... )                                 \
+    {                                                            \
+        fputs( __FILE__ ":" ASTRINGZ( __LINE__ ) ": ", stdout ); \
+        printf( __VA_ARGS__ );                                   \
+        fputs( "\r\n", stdout );                                 \
     }
 #else
-    #define portDBG_TRACE(...)
+    #define portDBG_TRACE( ... )
 #endif
 
 
 /* Critical section management. */
-#define portDISABLE_INTERRUPTS()  DISABLE_ALL_INTERRUPTS()
-#define portENABLE_INTERRUPTS()   ENABLE_ALL_INTERRUPTS()
+#define portDISABLE_INTERRUPTS()    DISABLE_ALL_INTERRUPTS()
+#define portENABLE_INTERRUPTS()     ENABLE_ALL_INTERRUPTS()
 
 
 extern void vPortEnterCritical( void );
 extern void vPortExitCritical( void );
 
-#define portENTER_CRITICAL()      vPortEnterCritical();
-#define portEXIT_CRITICAL()       vPortExitCritical();
+#define portENTER_CRITICAL()    vPortEnterCritical();
+#define portEXIT_CRITICAL()     vPortExitCritical();
 
 
 /* Added as there is no such function in FreeRTOS. */
-extern void *pvPortRealloc( void *pv, size_t xSize );
+extern void * pvPortRealloc( void * pv,
+                             size_t xSize );
 /*-----------------------------------------------------------*/
 
 
@@ -193,44 +195,44 @@ extern void *pvPortRealloc( void *pv, size_t xSize );
 /*
  * Restore Context for cases other than INTi.
  */
-#define portRESTORE_CONTEXT()                                                               \
-{                                                                                           \
-  extern volatile uint32_t ulCriticalNesting;                                       \
-  extern volatile void *volatile pxCurrentTCB;                                              \
-                                                                                            \
-  __asm__ __volatile__ (                                                                    \
-    /* Set SP to point to new stack */                                                      \
-    "mov     r8, LWRD("ASTRINGZ(pxCurrentTCB)")                                             \n\t"\
-    "orh     r8, HWRD("ASTRINGZ(pxCurrentTCB)")                                             \n\t"\
-    "ld.w    r0, r8[0]                                                                      \n\t"\
-    "ld.w    sp, r0[0]                                                                      \n\t"\
-                                                                                            \
-    /* Restore ulCriticalNesting variable */                                                \
-    "ld.w    r0, sp++                                                                       \n\t"\
-    "mov     r8, LWRD("ASTRINGZ(ulCriticalNesting)")                                        \n\t"\
-    "orh     r8, HWRD("ASTRINGZ(ulCriticalNesting)")                                        \n\t"\
-    "st.w    r8[0], r0                                                                      \n\t"\
-                                                                                            \
-    /* Restore R0..R7 */                                                                    \
-    "ldm     sp++, r0-r7                                                                    \n\t"\
-    /* R0-R7 should not be used below this line */                                          \
-    /* Skip PC and SR (will do it at the end) */                                            \
-    "sub     sp, -2*4                                                                       \n\t"\
-    /* Restore R8..R12 and LR */                                                            \
-    "ldm     sp++, r8-r12, lr                                                               \n\t"\
-    /* Restore SR */                                                                        \
-    "ld.w    r0, sp[-8*4]                                                                   \n\t" /* R0 is modified, is restored later. */\
-    "mtsr    "ASTRINGZ(AVR32_SR)", r0                                                       \n\t"\
-    /* Restore r0 */                                                                        \
-    "ld.w    r0, sp[-9*4]                                                                   \n\t"\
-    /* Restore PC */                                                                        \
-    "ld.w    pc, sp[-7*4]" /* Get PC from stack - PC is the 7th register saved */           \
-  );                                                                                        \
-                                                                                            \
-  /* Force import of global symbols from assembly */                                        \
-  ulCriticalNesting;                                                                        \
-  pxCurrentTCB;                                                                             \
-}
+#define portRESTORE_CONTEXT()                                                                                                                                                                                                                                                                                                                    \
+    {                                                                                                                                                                                                                                                                                                                                            \
+        extern volatile uint32_t ulCriticalNesting;                                                                                                                                                                                                                                                                                              \
+        extern volatile void * volatile pxCurrentTCB;                                                                                                                                                                                                                                                                                            \
+                                                                                                                                                                                                                                                                                                                                                 \
+        __asm__ __volatile__ (                                                                                                                                                                                                                                                                                                                   \
+            /* Set SP to point to new stack */                                                                                                                                                                                                                                                                                                   \
+            "mov     r8, LWRD("ASTRINGZ ( pxCurrentTCB ) ")                                             \n\t"                                                                                                                                                                                                                                    \
+                                                         "orh     r8, HWRD("ASTRINGZ ( pxCurrentTCB ) ")                                             \n\t"                                                                                                                                                                                       \
+                                                                                                      "ld.w    r0, r8[0]                                                                      \n\t"                                                                                                                                              \
+                                                                                                      "ld.w    sp, r0[0]                                                                      \n\t"                                                                                                                                              \
+                                                                                                                                                                                                                                                                                                                                                 \
+            /* Restore ulCriticalNesting variable */                                                                                                                                                                                                                                                                                             \
+                                                                                                      "ld.w    r0, sp++                                                                       \n\t"                                                                                                                                              \
+                                                                                                      "mov     r8, LWRD("ASTRINGZ ( ulCriticalNesting ) ")                                        \n\t"                                                                                                                                          \
+                                                                                                                                                        "orh     r8, HWRD("ASTRINGZ ( ulCriticalNesting ) ")                                        \n\t"                                                                                        \
+                                                                                                                                                                                                          "st.w    r8[0], r0                                                                      \n\t"                                          \
+                                                                                                                                                                                                                                                                                                                                                 \
+            /* Restore R0..R7 */                                                                                                                                                                                                                                                                                                                 \
+                                                                                                                                                                                                          "ldm     sp++, r0-r7                                                                    \n\t"                                          \
+            /* R0-R7 should not be used below this line */                                                                                                                                                                                                                                                                                       \
+            /* Skip PC and SR (will do it at the end) */                                                                                                                                                                                                                                                                                         \
+                                                                                                                                                                                                          "sub     sp, -2*4                                                                       \n\t"                                          \
+            /* Restore R8..R12 and LR */                                                                                                                                                                                                                                                                                                         \
+                                                                                                                                                                                                          "ldm     sp++, r8-r12, lr                                                               \n\t"                                          \
+            /* Restore SR */                                                                                                                                                                                                                                                                                                                     \
+                                                                                                                                                                                                          "ld.w    r0, sp[-8*4]                                                                   \n\t" /* R0 is modified, is restored later. */ \
+                                                                                                                                                                                                          "mtsr    "ASTRINGZ ( AVR32_SR ) ", r0                                                       \n\t"                                      \
+            /* Restore r0 */                                                                                                                                                                                                                                                                                                                     \
+                                                                                                                                                                                                                                          "ld.w    r0, sp[-9*4]                                                                   \n\t"          \
+            /* Restore PC */                                                                                                                                                                                                                                                                                                                     \
+                                                                                                                                                                                                                                          "ld.w    pc, sp[-7*4]" /* Get PC from stack - PC is the 7th register saved */                          \
+            );                                                                                                                                                                                                                                                                                                                                   \
+                                                                                                                                                                                                                                                                                                                                                 \
+        /* Force import of global symbols from assembly */                                                                                                                                                                                                                                                                                       \
+        ulCriticalNesting;                                                                                                                                                                                                                                                                                                                       \
+        pxCurrentTCB;                                                                                                                                                                                                                                                                                                                            \
+    }
 
 
 /*
@@ -241,25 +243,25 @@ extern void *pvPortRealloc( void *pv, size_t xSize );
  * are not the same between INT0..3 exceptions and the scall exception.
  */
 
-// Task context stack layout:
-  // R8  (*)
-  // R9  (*)
-  // R10 (*)
-  // R11 (*)
-  // R12 (*)
-  // R14/LR (*)
-  // R15/PC (*)
-  // SR (*)
-  // R0
-  // R1
-  // R2
-  // R3
-  // R4
-  // R5
-  // R6
-  // R7
-  // ulCriticalNesting
-// (*) automatically done for INT0..INT3, but not for SCALL
+/* Task context stack layout: */
+/* R8  (*) */
+/* R9  (*) */
+/* R10 (*) */
+/* R11 (*) */
+/* R12 (*) */
+/* R14/LR (*) */
+/* R15/PC (*) */
+/* SR (*) */
+/* R0 */
+/* R1 */
+/* R2 */
+/* R3 */
+/* R4 */
+/* R5 */
+/* R6 */
+/* R7 */
+/* ulCriticalNesting */
+/* (*) automatically done for INT0..INT3, but not for SCALL */
 
 /*
  * The ISR used for the scheduler tick depends on whether the cooperative or
@@ -270,139 +272,139 @@ extern void *pvPortRealloc( void *pv, size_t xSize );
 /*
  * portSAVE_CONTEXT_OS_INT() for OS Tick exception.
  */
-#define portSAVE_CONTEXT_OS_INT()                                                           \
-{                                                                                           \
-  /* Save R0..R7 */                                                                         \
-  __asm__ __volatile__ ("stm     --sp, r0-r7");                                             \
-                                                                                            \
-  /* With the cooperative scheduler, as there is no context switch by interrupt, */         \
-  /* there is also no context save. */                                                      \
-}
+    #define portSAVE_CONTEXT_OS_INT()                                                     \
+    {                                                                                     \
+        /* Save R0..R7 */                                                                 \
+        __asm__ __volatile__ ( "stm     --sp, r0-r7" );                                   \
+                                                                                          \
+        /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
+        /* there is also no context save. */                                              \
+    }
 
 /*
  * portRESTORE_CONTEXT_OS_INT() for Tick exception.
  */
-#define portRESTORE_CONTEXT_OS_INT()                                                        \
-{                                                                                           \
-  __asm__ __volatile__ (                                                                    \
-    /* Restore R0..R7 */                                                                    \
-    "ldm     sp++, r0-r7                                                                    \n\t"\
-                                                                                            \
-    /* With the cooperative scheduler, as there is no context switch by interrupt, */       \
-    /* there is also no context restore. */                                                 \
-    "rete"                                                                                  \
-  );                                                                                        \
-}
+    #define portRESTORE_CONTEXT_OS_INT()                                                                  \
+    {                                                                                                     \
+        __asm__ __volatile__ (                                                                            \
+            /* Restore R0..R7 */                                                                          \
+            "ldm     sp++, r0-r7                                                                    \n\t" \
+                                                                                                          \
+            /* With the cooperative scheduler, as there is no context switch by interrupt, */             \
+            /* there is also no context restore. */                                                       \
+            "rete"                                                                                        \
+            );                                                                                            \
+    }
 
-#else
+#else /* if configUSE_PREEMPTION == 0 */
 
 /*
  * portSAVE_CONTEXT_OS_INT() for OS Tick exception.
  */
-#define portSAVE_CONTEXT_OS_INT()                                                                   \
-{                                                                                                   \
-  extern volatile uint32_t ulCriticalNesting;                                               \
-  extern volatile void *volatile pxCurrentTCB;                                                      \
-                                                                                                    \
-  /* When we come here */                                                                           \
-  /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */                    \
-                                                                                                    \
-  __asm__ __volatile__ (                                                                            \
-    /* Save R0..R7 */                                                                               \
-    "stm     --sp, r0-r7                                                                            \n\t"\
-                                                                                                    \
-    /* Save ulCriticalNesting variable  - R0 is overwritten */                                      \
-    "mov     r8, LWRD("ASTRINGZ(ulCriticalNesting)")                                                \n\t"\
-    "orh     r8, HWRD("ASTRINGZ(ulCriticalNesting)")                                                \n\t"\
-    "ld.w    r0, r8[0]                                                                              \n\t"\
-    "st.w    --sp, r0                                                                               \n\t"\
-                                                                                                    \
-    /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */    \
-    /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
-    /* level and allow other lower interrupt level to occur). */                                    \
-    /* In this case we don't want to do a task switch because we don't know what the stack */       \
-    /* currently looks like (we don't know what the interrupted interrupt handler was doing). */    \
-    /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */       \
-    /* will just be restoring the interrupt handler, no way!!! */                                   \
-    /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */                  \
-    "ld.w    r0, sp[9*4]                                                                            \n\t" /* Read SR in stack */\
-    "bfextu  r0, r0, 22, 3                                                                          \n\t" /* Extract the mode bits to R0. */\
-    "cp.w    r0, 1                                                                                  \n\t" /* Compare the mode bits with supervisor mode(b'001) */\
-    "brhi    LABEL_INT_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)"                                       \n\t"\
-                                                                                                    \
-    /* Store SP in the first member of the structure pointed to by pxCurrentTCB */                  \
-    /* NOTE: we don't enter a critical section here because all interrupt handlers */               \
-    /* MUST perform a SAVE_CONTEXT/RESTORE_CONTEXT in the same way as */                            \
-    /* portSAVE_CONTEXT_OS_INT/port_RESTORE_CONTEXT_OS_INT if they call OS functions. */            \
-    /* => all interrupt handlers must use portENTER_SWITCHING_ISR/portEXIT_SWITCHING_ISR. */        \
-    "mov     r8, LWRD("ASTRINGZ(pxCurrentTCB)")                                                     \n\t"\
-    "orh     r8, HWRD("ASTRINGZ(pxCurrentTCB)")                                                     \n\t"\
-    "ld.w    r0, r8[0]                                                                              \n\t"\
-    "st.w    r0[0], sp                                                                              \n"\
-                                                                                                    \
-    "LABEL_INT_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)":"                                             \
-  );                                                                                                \
-}
+    #define portSAVE_CONTEXT_OS_INT()                                                                                                                                                                                                                                                                                                                                       \
+    {                                                                                                                                                                                                                                                                                                                                                                       \
+        extern volatile uint32_t ulCriticalNesting;                                                                                                                                                                                                                                                                                                                         \
+        extern volatile void * volatile pxCurrentTCB;                                                                                                                                                                                                                                                                                                                       \
+                                                                                                                                                                                                                                                                                                                                                                            \
+        /* When we come here */                                                                                                                                                                                                                                                                                                                                             \
+        /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */                                                                                                                                                                                                                                                                                      \
+                                                                                                                                                                                                                                                                                                                                                                            \
+        __asm__ __volatile__ (                                                                                                                                                                                                                                                                                                                                              \
+            /* Save R0..R7 */                                                                                                                                                                                                                                                                                                                                               \
+            "stm     --sp, r0-r7                                                                            \n\t"                                                                                                                                                                                                                                                           \
+                                                                                                                                                                                                                                                                                                                                                                            \
+            /* Save ulCriticalNesting variable  - R0 is overwritten */                                                                                                                                                                                                                                                                                                      \
+            "mov     r8, LWRD("ASTRINGZ ( ulCriticalNesting ) ")                                                \n\t"                                                                                                                                                                                                                                                       \
+                                                              "orh     r8, HWRD("ASTRINGZ ( ulCriticalNesting ) ")                                                \n\t"                                                                                                                                                                                                     \
+                                                                                                                "ld.w    r0, r8[0]                                                                              \n\t"                                                                                                                                                       \
+                                                                                                                "st.w    --sp, r0                                                                               \n\t"                                                                                                                                                       \
+                                                                                                                                                                                                                                                                                                                                                                            \
+            /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */                                                                                                                                                                                                                                                                    \
+            /* interrupt handler (which was of a higher priority level but decided to lower its priority */                                                                                                                                                                                                                                                                 \
+            /* level and allow other lower interrupt level to occur). */                                                                                                                                                                                                                                                                                                    \
+            /* In this case we don't want to do a task switch because we don't know what the stack */                                                                                                                                                                                                                                                                       \
+            /* currently looks like (we don't know what the interrupted interrupt handler was doing). */                                                                                                                                                                                                                                                                    \
+            /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */                                                                                                                                                                                                                                                                       \
+            /* will just be restoring the interrupt handler, no way!!! */                                                                                                                                                                                                                                                                                                   \
+            /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */                                                                                                                                                                                                                                                                                  \
+                                                                                                                "ld.w    r0, sp[9*4]                                                                            \n\t" /* Read SR in stack */                                                                                                                                \
+                                                                                                                "bfextu  r0, r0, 22, 3                                                                          \n\t" /* Extract the mode bits to R0. */                                                                                                                    \
+                                                                                                                "cp.w    r0, 1                                                                                  \n\t" /* Compare the mode bits with supervisor mode(b'001) */                                                                                               \
+                                                                                                                "brhi    LABEL_INT_SKIP_SAVE_CONTEXT_"ASTRINGZ ( __LINE__ ) "                                       \n\t"                                                                                                                                                   \
+                                                                                                                                                                                                                                                                                                                                                                            \
+            /* Store SP in the first member of the structure pointed to by pxCurrentTCB */                                                                                                                                                                                                                                                                                  \
+            /* NOTE: we don't enter a critical section here because all interrupt handlers */                                                                                                                                                                                                                                                                               \
+            /* MUST perform a SAVE_CONTEXT/RESTORE_CONTEXT in the same way as */                                                                                                                                                                                                                                                                                            \
+            /* portSAVE_CONTEXT_OS_INT/port_RESTORE_CONTEXT_OS_INT if they call OS functions. */                                                                                                                                                                                                                                                                            \
+            /* => all interrupt handlers must use portENTER_SWITCHING_ISR/portEXIT_SWITCHING_ISR. */                                                                                                                                                                                                                                                                        \
+                                                                                                                                                                            "mov     r8, LWRD("ASTRINGZ ( pxCurrentTCB ) ")                                                     \n\t"                                                                                       \
+                                                                                                                                                                                                                         "orh     r8, HWRD("ASTRINGZ ( pxCurrentTCB ) ")                                                     \n\t"                                          \
+                                                                                                                                                                                                                                                                      "ld.w    r0, r8[0]                                                                              \n\t" \
+                                                                                                                                                                                                                                                                      "st.w    r0[0], sp                                                                              \n"   \
+                                                                                                                                                                                                                                                                                                                                                                            \
+                                                                                                                                                                                                                                                                      "LABEL_INT_SKIP_SAVE_CONTEXT_"ASTRINGZ ( __LINE__ ) ":"                                               \
+            );                                                                                                                                                                                                                                                                                                                                                              \
+    }
 
 /*
  * portRESTORE_CONTEXT_OS_INT() for Tick exception.
  */
-#define portRESTORE_CONTEXT_OS_INT()                                                                \
-{                                                                                                   \
-  extern volatile uint32_t ulCriticalNesting;                                               \
-  extern volatile void *volatile pxCurrentTCB;                                                      \
-                                                                                                    \
-  /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */      \
-  /* interrupt handler (which was of a higher priority level but decided to lower its priority */   \
-  /* level and allow other lower interrupt level to occur). */                                      \
-  /* In this case we don't want to do a task switch because we don't know what the stack */         \
-  /* currently looks like (we don't know what the interrupted interrupt handler was doing). */      \
-  /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */         \
-  /* will just be restoring the interrupt handler, no way!!! */                                     \
-  __asm__ __volatile__ (                                                                            \
-    "ld.w    r0, sp[9*4]                                                                            \n\t" /* Read SR in stack */\
-    "bfextu  r0, r0, 22, 3                                                                          \n\t" /* Extract the mode bits to R0. */\
-    "cp.w    r0, 1                                                                                  \n\t" /* Compare the mode bits with supervisor mode(b'001) */\
-    "brhi    LABEL_INT_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)                                     \
-  );                                                                                                \
-                                                                                                    \
-  /* Else */                                                                                        \
-  /* because it is here safe, always call vTaskSwitchContext() since an OS tick occurred. */        \
-  /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */\
-  portENTER_CRITICAL();                                                                             \
-  vTaskSwitchContext();                                                                             \
-  portEXIT_CRITICAL();                                                                              \
-                                                                                                    \
-  /* Restore all registers */                                                                       \
-                                                                                                    \
-  __asm__ __volatile__ (                                                                            \
-    /* Set SP to point to new stack */                                                              \
-    "mov     r8, LWRD("ASTRINGZ(pxCurrentTCB)")                                                     \n\t"\
-    "orh     r8, HWRD("ASTRINGZ(pxCurrentTCB)")                                                     \n\t"\
-    "ld.w    r0, r8[0]                                                                              \n\t"\
-    "ld.w    sp, r0[0]                                                                              \n"\
-                                                                                                    \
-    "LABEL_INT_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)":                                           \n\t"\
-                                                                                                    \
-    /* Restore ulCriticalNesting variable */                                                        \
-    "ld.w    r0, sp++                                                                               \n\t"\
-    "mov     r8, LWRD("ASTRINGZ(ulCriticalNesting)")                                                \n\t"\
-    "orh     r8, HWRD("ASTRINGZ(ulCriticalNesting)")                                                \n\t"\
-    "st.w    r8[0], r0                                                                              \n\t"\
-                                                                                                    \
-    /* Restore R0..R7 */                                                                            \
-    "ldm     sp++, r0-r7                                                                            \n\t"\
-                                                                                                    \
-    /* Now, the stack should be R8..R12, LR, PC and SR */                                           \
-    "rete"                                                                                          \
-  );                                                                                                \
-                                                                                                    \
-  /* Force import of global symbols from assembly */                                                \
-  ulCriticalNesting;                                                                                \
-  pxCurrentTCB;                                                                                     \
-}
+    #define portRESTORE_CONTEXT_OS_INT()                                                                                                                                                                                                                                                                                                                               \
+    {                                                                                                                                                                                                                                                                                                                                                                  \
+        extern volatile uint32_t ulCriticalNesting;                                                                                                                                                                                                                                                                                                                    \
+        extern volatile void * volatile pxCurrentTCB;                                                                                                                                                                                                                                                                                                                  \
+                                                                                                                                                                                                                                                                                                                                                                       \
+        /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */                                                                                                                                                                                                                                                                   \
+        /* interrupt handler (which was of a higher priority level but decided to lower its priority */                                                                                                                                                                                                                                                                \
+        /* level and allow other lower interrupt level to occur). */                                                                                                                                                                                                                                                                                                   \
+        /* In this case we don't want to do a task switch because we don't know what the stack */                                                                                                                                                                                                                                                                      \
+        /* currently looks like (we don't know what the interrupted interrupt handler was doing). */                                                                                                                                                                                                                                                                   \
+        /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */                                                                                                                                                                                                                                                                      \
+        /* will just be restoring the interrupt handler, no way!!! */                                                                                                                                                                                                                                                                                                  \
+        __asm__ __volatile__ (                                                                                                                                                                                                                                                                                                                                         \
+            "ld.w    r0, sp[9*4]                                                                            \n\t" /* Read SR in stack */                                                                                                                                                                                                                               \
+            "bfextu  r0, r0, 22, 3                                                                          \n\t" /* Extract the mode bits to R0. */                                                                                                                                                                                                                   \
+            "cp.w    r0, 1                                                                                  \n\t" /* Compare the mode bits with supervisor mode(b'001) */                                                                                                                                                                                              \
+            "brhi    LABEL_INT_SKIP_RESTORE_CONTEXT_"ASTRINGZ ( __LINE__ )                                                                                                                                                                                                                                                                                             \
+            );                                                                                                                                                                                                                                                                                                                                                         \
+                                                                                                                                                                                                                                                                                                                                                                       \
+        /* Else */                                                                                                                                                                                                                                                                                                                                                     \
+        /* because it is here safe, always call vTaskSwitchContext() since an OS tick occurred. */                                                                                                                                                                                                                                                                     \
+        /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */                                                                                                                                                                                                                                                         \
+        portENTER_CRITICAL();                                                                                                                                                                                                                                                                                                                                          \
+        vTaskSwitchContext();                                                                                                                                                                                                                                                                                                                                          \
+        portEXIT_CRITICAL();                                                                                                                                                                                                                                                                                                                                           \
+                                                                                                                                                                                                                                                                                                                                                                       \
+        /* Restore all registers */                                                                                                                                                                                                                                                                                                                                    \
+                                                                                                                                                                                                                                                                                                                                                                       \
+        __asm__ __volatile__ (                                                                                                                                                                                                                                                                                                                                         \
+            /* Set SP to point to new stack */                                                                                                                                                                                                                                                                                                                         \
+            "mov     r8, LWRD("ASTRINGZ ( pxCurrentTCB ) ")                                                     \n\t"                                                                                                                                                                                                                                                  \
+                                                         "orh     r8, HWRD("ASTRINGZ ( pxCurrentTCB ) ")                                                     \n\t"                                                                                                                                                                                                     \
+                                                                                                      "ld.w    r0, r8[0]                                                                              \n\t"                                                                                                                                                            \
+                                                                                                      "ld.w    sp, r0[0]                                                                              \n"                                                                                                                                                              \
+                                                                                                                                                                                                                                                                                                                                                                       \
+                                                                                                      "LABEL_INT_SKIP_RESTORE_CONTEXT_"ASTRINGZ ( __LINE__ ) ":                                           \n\t"                                                                                                                                                        \
+                                                                                                                                                                                                                                                                                                                                                                       \
+            /* Restore ulCriticalNesting variable */                                                                                                                                                                                                                                                                                                                   \
+                                                                                                                                                             "ld.w    r0, sp++                                                                               \n\t"                                                                                                     \
+                                                                                                                                                             "mov     r8, LWRD("ASTRINGZ ( ulCriticalNesting ) ")                                                \n\t"                                                                                                 \
+                                                                                                                                                                                                               "orh     r8, HWRD("ASTRINGZ ( ulCriticalNesting ) ")                                                \n\t"                                               \
+                                                                                                                                                                                                                                                                 "st.w    r8[0], r0                                                                              \n\t" \
+                                                                                                                                                                                                                                                                                                                                                                       \
+            /* Restore R0..R7 */                                                                                                                                                                                                                                                                                                                                       \
+                                                                                                                                                                                                                                                                 "ldm     sp++, r0-r7                                                                            \n\t" \
+                                                                                                                                                                                                                                                                                                                                                                       \
+            /* Now, the stack should be R8..R12, LR, PC and SR */                                                                                                                                                                                                                                                                                                      \
+                                                                                                                                                                                                                                                                 "rete"                                                                                                \
+            );                                                                                                                                                                                                                                                                                                                                                         \
+                                                                                                                                                                                                                                                                                                                                                                       \
+        /* Force import of global symbols from assembly */                                                                                                                                                                                                                                                                                                             \
+        ulCriticalNesting;                                                                                                                                                                                                                                                                                                                                             \
+        pxCurrentTCB;                                                                                                                                                                                                                                                                                                                                                  \
+    }
 
-#endif
+#endif /* if configUSE_PREEMPTION == 0 */
 
 
 /*
@@ -411,119 +413,119 @@ extern void *pvPortRealloc( void *pv, size_t xSize );
  * NOTE: taskYIELD()(== SCALL) MUST NOT be called in a mode > supervisor mode.
  *
  */
-#define portSAVE_CONTEXT_SCALL()                                                                    \
-{                                                                                                   \
-  extern volatile uint32_t ulCriticalNesting;                                               \
-  extern volatile void *volatile pxCurrentTCB;                                                      \
-                                                                                                    \
-  /* Warning: the stack layout after SCALL doesn't match the one after an interrupt. */             \
-  /* If SR[M2:M0] == 001 */                                                                         \
-  /*    PC and SR are on the stack.  */                                                             \
-  /* Else (other modes) */                                                                          \
-  /*    Nothing on the stack. */                                                                    \
-                                                                                                    \
-  /* WARNING NOTE: the else case cannot happen as it is strictly forbidden to call */               \
-  /* vTaskDelay() and vTaskDelayUntil() OS functions (that result in a taskYield()) */              \
-  /* in an interrupt|exception handler. */                                                          \
-                                                                                                    \
-  __asm__ __volatile__ (                                                                            \
-    /* in order to save R0-R7 */                                                                    \
-    "sub     sp, 6*4                                                                                \n\t"\
-    /* Save R0..R7 */                                                                               \
-    "stm     --sp, r0-r7                                                                            \n\t"\
-                                                                                                    \
-    /* in order to save R8-R12 and LR */                                                            \
-    /* do not use SP if interrupts occurs, SP must be left at bottom of stack */                    \
-    "sub     r7, sp,-16*4                                                                           \n\t"\
-    /* Copy PC and SR in other places in the stack. */                                              \
-    "ld.w    r0, r7[-2*4]                                                                           \n\t" /* Read SR */\
-    "st.w    r7[-8*4], r0                                                                           \n\t" /* Copy SR */\
-    "ld.w    r0, r7[-1*4]                                                                           \n\t" /* Read PC */\
-    "st.w    r7[-7*4], r0                                                                           \n\t" /* Copy PC */\
-                                                                                                    \
-    /* Save R8..R12 and LR on the stack. */                                                         \
-    "stm     --r7, r8-r12, lr                                                                       \n\t"\
-                                                                                                    \
-    /* Arriving here we have the following stack organizations: */                                  \
-    /* R8..R12, LR, PC, SR, R0..R7. */                                                              \
-                                                                                                    \
-    /* Now we can finalize the save. */                                                             \
-                                                                                                    \
-    /* Save ulCriticalNesting variable  - R0 is overwritten */                                      \
-    "mov     r8, LWRD("ASTRINGZ(ulCriticalNesting)")                                                \n\t"\
-    "orh     r8, HWRD("ASTRINGZ(ulCriticalNesting)")                                                \n\t"\
-    "ld.w    r0, r8[0]                                                                              \n\t"\
-    "st.w    --sp, r0"                                                                              \
-  );                                                                                                \
-                                                                                                    \
-  /* Disable the its which may cause a context switch (i.e. cause a change of */                    \
-  /* pxCurrentTCB). */                                                                              \
-  /* Basically, all accesses to the pxCurrentTCB structure should be put in a */                    \
-  /* critical section because it is a global structure. */                                          \
-  portENTER_CRITICAL();                                                                             \
-                                                                                                    \
-  /* Store SP in the first member of the structure pointed to by pxCurrentTCB */                    \
-  __asm__ __volatile__ (                                                                            \
-    "mov     r8, LWRD("ASTRINGZ(pxCurrentTCB)")                                                     \n\t"\
-    "orh     r8, HWRD("ASTRINGZ(pxCurrentTCB)")                                                     \n\t"\
-    "ld.w    r0, r8[0]                                                                              \n\t"\
-    "st.w    r0[0], sp"                                                                             \
-  );                                                                                                \
-}
+#define portSAVE_CONTEXT_SCALL()                                                                                                                                                                                      \
+    {                                                                                                                                                                                                                 \
+        extern volatile uint32_t ulCriticalNesting;                                                                                                                                                                   \
+        extern volatile void * volatile pxCurrentTCB;                                                                                                                                                                 \
+                                                                                                                                                                                                                      \
+        /* Warning: the stack layout after SCALL doesn't match the one after an interrupt. */                                                                                                                         \
+        /* If SR[M2:M0] == 001 */                                                                                                                                                                                     \
+        /*    PC and SR are on the stack.  */                                                                                                                                                                         \
+        /* Else (other modes) */                                                                                                                                                                                      \
+        /*    Nothing on the stack. */                                                                                                                                                                                \
+                                                                                                                                                                                                                      \
+        /* WARNING NOTE: the else case cannot happen as it is strictly forbidden to call */                                                                                                                           \
+        /* vTaskDelay() and vTaskDelayUntil() OS functions (that result in a taskYield()) */                                                                                                                          \
+        /* in an interrupt|exception handler. */                                                                                                                                                                      \
+                                                                                                                                                                                                                      \
+        __asm__ __volatile__ (                                                                                                                                                                                        \
+            /* in order to save R0-R7 */                                                                                                                                                                              \
+            "sub     sp, 6*4                                                                                \n\t"                                                                                                     \
+            /* Save R0..R7 */                                                                                                                                                                                         \
+            "stm     --sp, r0-r7                                                                            \n\t"                                                                                                     \
+                                                                                                                                                                                                                      \
+            /* in order to save R8-R12 and LR */                                                                                                                                                                      \
+            /* do not use SP if interrupts occurs, SP must be left at bottom of stack */                                                                                                                              \
+            "sub     r7, sp,-16*4                                                                           \n\t"                                                                                                     \
+            /* Copy PC and SR in other places in the stack. */                                                                                                                                                        \
+            "ld.w    r0, r7[-2*4]                                                                           \n\t" /* Read SR */                                                                                       \
+            "st.w    r7[-8*4], r0                                                                           \n\t" /* Copy SR */                                                                                       \
+            "ld.w    r0, r7[-1*4]                                                                           \n\t" /* Read PC */                                                                                       \
+            "st.w    r7[-7*4], r0                                                                           \n\t" /* Copy PC */                                                                                       \
+                                                                                                                                                                                                                      \
+            /* Save R8..R12 and LR on the stack. */                                                                                                                                                                   \
+            "stm     --r7, r8-r12, lr                                                                       \n\t"                                                                                                     \
+                                                                                                                                                                                                                      \
+            /* Arriving here we have the following stack organizations: */                                                                                                                                            \
+            /* R8..R12, LR, PC, SR, R0..R7. */                                                                                                                                                                        \
+                                                                                                                                                                                                                      \
+            /* Now we can finalize the save. */                                                                                                                                                                       \
+                                                                                                                                                                                                                      \
+            /* Save ulCriticalNesting variable  - R0 is overwritten */                                                                                                                                                \
+            "mov     r8, LWRD("ASTRINGZ ( ulCriticalNesting ) ")                                                \n\t"                                                                                                 \
+                                                              "orh     r8, HWRD("ASTRINGZ ( ulCriticalNesting ) ")                                                \n\t"                                               \
+                                                                                                                "ld.w    r0, r8[0]                                                                              \n\t" \
+                                                                                                                "st.w    --sp, r0"                                                                                    \
+            );                                                                                                                                                                                                        \
+                                                                                                                                                                                                                      \
+        /* Disable the its which may cause a context switch (i.e. cause a change of */                                                                                                                                \
+        /* pxCurrentTCB). */                                                                                                                                                                                          \
+        /* Basically, all accesses to the pxCurrentTCB structure should be put in a */                                                                                                                                \
+        /* critical section because it is a global structure. */                                                                                                                                                      \
+        portENTER_CRITICAL();                                                                                                                                                                                         \
+                                                                                                                                                                                                                      \
+        /* Store SP in the first member of the structure pointed to by pxCurrentTCB */                                                                                                                                \
+        __asm__ __volatile__ (                                                                                                                                                                                        \
+            "mov     r8, LWRD("ASTRINGZ ( pxCurrentTCB ) ")                                                     \n\t"                                                                                                 \
+                                                         "orh     r8, HWRD("ASTRINGZ ( pxCurrentTCB ) ")                                                     \n\t"                                                    \
+                                                                                                      "ld.w    r0, r8[0]                                                                              \n\t"           \
+                                                                                                      "st.w    r0[0], sp"                                                                                             \
+            );                                                                                                                                                                                                        \
+    }
 
 /*
  * portRESTORE_CONTEXT() for SupervisorCALL exception.
  */
-#define portRESTORE_CONTEXT_SCALL()                                                                 \
-{                                                                                                   \
-  extern volatile uint32_t ulCriticalNesting;                                               \
-  extern volatile void *volatile pxCurrentTCB;                                                      \
-                                                                                                    \
-  /* Restore all registers */                                                                       \
-                                                                                                    \
-  /* Set SP to point to new stack */                                                                \
-  __asm__ __volatile__ (                                                                            \
-    "mov     r8, LWRD("ASTRINGZ(pxCurrentTCB)")                                                     \n\t"\
-    "orh     r8, HWRD("ASTRINGZ(pxCurrentTCB)")                                                     \n\t"\
-    "ld.w    r0, r8[0]                                                                              \n\t"\
-    "ld.w    sp, r0[0]"                                                                             \
-  );                                                                                                \
-                                                                                                    \
-  /* Leave pxCurrentTCB variable access critical section */                                         \
-  portEXIT_CRITICAL();                                                                              \
-                                                                                                    \
-  __asm__ __volatile__ (                                                                            \
-    /* Restore ulCriticalNesting variable */                                                        \
-    "ld.w    r0, sp++                                                                               \n\t"\
-    "mov     r8, LWRD("ASTRINGZ(ulCriticalNesting)")                                                \n\t"\
-    "orh     r8, HWRD("ASTRINGZ(ulCriticalNesting)")                                                \n\t"\
-    "st.w    r8[0], r0                                                                              \n\t"\
-                                                                                                    \
-    /* skip PC and SR */                                                                            \
-    /* do not use SP if interrupts occurs, SP must be left at bottom of stack */                    \
-    "sub     r7, sp, -10*4                                                                          \n\t"\
-    /* Restore r8-r12 and LR */                                                                     \
-    "ldm     r7++, r8-r12, lr                                                                       \n\t"\
-                                                                                                    \
-    /* RETS will take care of the extra PC and SR restore. */                                       \
-    /* So, we have to prepare the stack for this. */                                                \
-    "ld.w    r0, r7[-8*4]                                                                           \n\t" /* Read SR */\
-    "st.w    r7[-2*4], r0                                                                           \n\t" /* Copy SR */\
-    "ld.w    r0, r7[-7*4]                                                                           \n\t" /* Read PC */\
-    "st.w    r7[-1*4], r0                                                                           \n\t" /* Copy PC */\
-                                                                                                    \
-    /* Restore R0..R7 */                                                                            \
-    "ldm     sp++, r0-r7                                                                            \n\t"\
-                                                                                                    \
-    "sub     sp, -6*4                                                                               \n\t"\
-                                                                                                    \
-    "rets"                                                                                          \
-  );                                                                                                \
-                                                                                                    \
-  /* Force import of global symbols from assembly */                                                \
-  ulCriticalNesting;                                                                                \
-  pxCurrentTCB;                                                                                     \
-}
+#define portRESTORE_CONTEXT_SCALL()                                                                                                                                                                                                 \
+    {                                                                                                                                                                                                                               \
+        extern volatile uint32_t ulCriticalNesting;                                                                                                                                                                                 \
+        extern volatile void * volatile pxCurrentTCB;                                                                                                                                                                               \
+                                                                                                                                                                                                                                    \
+        /* Restore all registers */                                                                                                                                                                                                 \
+                                                                                                                                                                                                                                    \
+        /* Set SP to point to new stack */                                                                                                                                                                                          \
+        __asm__ __volatile__ (                                                                                                                                                                                                      \
+            "mov     r8, LWRD("ASTRINGZ ( pxCurrentTCB ) ")                                                     \n\t"                                                                                                               \
+                                                         "orh     r8, HWRD("ASTRINGZ ( pxCurrentTCB ) ")                                                     \n\t"                                                                  \
+                                                                                                      "ld.w    r0, r8[0]                                                                              \n\t"                         \
+                                                                                                      "ld.w    sp, r0[0]"                                                                                                           \
+            );                                                                                                                                                                                                                      \
+                                                                                                                                                                                                                                    \
+        /* Leave pxCurrentTCB variable access critical section */                                                                                                                                                                   \
+        portEXIT_CRITICAL();                                                                                                                                                                                                        \
+                                                                                                                                                                                                                                    \
+        __asm__ __volatile__ (                                                                                                                                                                                                      \
+            /* Restore ulCriticalNesting variable */                                                                                                                                                                                \
+            "ld.w    r0, sp++                                                                               \n\t"                                                                                                                   \
+            "mov     r8, LWRD("ASTRINGZ ( ulCriticalNesting ) ")                                                \n\t"                                                                                                               \
+                                                              "orh     r8, HWRD("ASTRINGZ ( ulCriticalNesting ) ")                                                \n\t"                                                             \
+                                                                                                                "st.w    r8[0], r0                                                                              \n\t"               \
+                                                                                                                                                                                                                                    \
+            /* skip PC and SR */                                                                                                                                                                                                    \
+            /* do not use SP if interrupts occurs, SP must be left at bottom of stack */                                                                                                                                            \
+                                                                                                                "sub     r7, sp, -10*4                                                                          \n\t"               \
+            /* Restore r8-r12 and LR */                                                                                                                                                                                             \
+                                                                                                                "ldm     r7++, r8-r12, lr                                                                       \n\t"               \
+                                                                                                                                                                                                                                    \
+            /* RETS will take care of the extra PC and SR restore. */                                                                                                                                                               \
+            /* So, we have to prepare the stack for this. */                                                                                                                                                                        \
+                                                                                                                "ld.w    r0, r7[-8*4]                                                                           \n\t" /* Read SR */ \
+                                                                                                                "st.w    r7[-2*4], r0                                                                           \n\t" /* Copy SR */ \
+                                                                                                                "ld.w    r0, r7[-7*4]                                                                           \n\t" /* Read PC */ \
+                                                                                                                "st.w    r7[-1*4], r0                                                                           \n\t" /* Copy PC */ \
+                                                                                                                                                                                                                                    \
+            /* Restore R0..R7 */                                                                                                                                                                                                    \
+                                                                                                                "ldm     sp++, r0-r7                                                                            \n\t"               \
+                                                                                                                                                                                                                                    \
+                                                                                                                "sub     sp, -6*4                                                                               \n\t"               \
+                                                                                                                                                                                                                                    \
+                                                                                                                "rets"                                                                                                              \
+            );                                                                                                                                                                                                                      \
+                                                                                                                                                                                                                                    \
+        /* Force import of global symbols from assembly */                                                                                                                                                                          \
+        ulCriticalNesting;                                                                                                                                                                                                          \
+        pxCurrentTCB;                                                                                                                                                                                                               \
+    }
 
 
 /*
@@ -536,150 +538,150 @@ extern void *pvPortRealloc( void *pv, size_t xSize );
  * ISR entry and exit macros.  These are only required if a task switch
  * is required from the ISR.
  */
-#define portENTER_SWITCHING_ISR()                                                                   \
-{                                                                                                   \
-  /* Save R0..R7 */                                                                                 \
-  __asm__ __volatile__ ("stm     --sp, r0-r7");                                                     \
-                                                                                                    \
-  /* With the cooperative scheduler, as there is no context switch by interrupt, */                 \
-  /* there is also no context save. */                                                              \
-}
+    #define portENTER_SWITCHING_ISR()                                                     \
+    {                                                                                     \
+        /* Save R0..R7 */                                                                 \
+        __asm__ __volatile__ ( "stm     --sp, r0-r7" );                                   \
+                                                                                          \
+        /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
+        /* there is also no context save. */                                              \
+    }
 
 /*
  * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1
  */
-#define portEXIT_SWITCHING_ISR()                                                                    \
-{                                                                                                   \
-  __asm__ __volatile__ (                                                                            \
-    /* Restore R0..R7 */                                                                            \
-    "ldm     sp++, r0-r7                                                                            \n\t"\
-                                                                                                    \
-    /* With the cooperative scheduler, as there is no context switch by interrupt, */               \
-    /* there is also no context restore. */                                                         \
-    "rete"                                                                                          \
-  );                                                                                                \
-}
+    #define portEXIT_SWITCHING_ISR()                                                                              \
+    {                                                                                                             \
+        __asm__ __volatile__ (                                                                                    \
+            /* Restore R0..R7 */                                                                                  \
+            "ldm     sp++, r0-r7                                                                            \n\t" \
+                                                                                                                  \
+            /* With the cooperative scheduler, as there is no context switch by interrupt, */                     \
+            /* there is also no context restore. */                                                               \
+            "rete"                                                                                                \
+            );                                                                                                    \
+    }
 
-#else
+#else /* if configUSE_PREEMPTION == 0 */
 
 /*
  * ISR entry and exit macros.  These are only required if a task switch
  * is required from the ISR.
  */
-#define portENTER_SWITCHING_ISR()                                                                   \
-{                                                                                                   \
-  extern volatile uint32_t ulCriticalNesting;                                               \
-  extern volatile void *volatile pxCurrentTCB;                                                      \
-                                                                                                    \
-  /* When we come here */                                                                           \
-  /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */                    \
-                                                                                                    \
-  __asm__ __volatile__ (                                                                            \
-    /* Save R0..R7 */                                                                               \
-    "stm     --sp, r0-r7                                                                            \n\t"\
-                                                                                                    \
-    /* Save ulCriticalNesting variable  - R0 is overwritten */                                      \
-    "mov     r8, LWRD("ASTRINGZ(ulCriticalNesting)")                                                \n\t"\
-    "orh     r8, HWRD("ASTRINGZ(ulCriticalNesting)")                                                \n\t"\
-    "ld.w    r0, r8[0]                                                                              \n\t"\
-    "st.w    --sp, r0                                                                               \n\t"\
-                                                                                                    \
-    /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */    \
-    /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
-    /* level and allow other lower interrupt level to occur). */                                    \
-    /* In this case we don't want to do a task switch because we don't know what the stack */       \
-    /* currently looks like (we don't know what the interrupted interrupt handler was doing). */    \
-    /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */       \
-    /* will just be restoring the interrupt handler, no way!!! */                                   \
-    /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */                  \
-    "ld.w    r0, sp[9*4]                                                                            \n\t" /* Read SR in stack */\
-    "bfextu  r0, r0, 22, 3                                                                          \n\t" /* Extract the mode bits to R0. */\
-    "cp.w    r0, 1                                                                                  \n\t" /* Compare the mode bits with supervisor mode(b'001) */\
-    "brhi    LABEL_ISR_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)"                                       \n\t"\
-                                                                                                    \
-    /* Store SP in the first member of the structure pointed to by pxCurrentTCB */                  \
-    "mov     r8, LWRD("ASTRINGZ(pxCurrentTCB)")                                                     \n\t"\
-    "orh     r8, HWRD("ASTRINGZ(pxCurrentTCB)")                                                     \n\t"\
-    "ld.w    r0, r8[0]                                                                              \n\t"\
-    "st.w    r0[0], sp                                                                              \n"\
-                                                                                                    \
-    "LABEL_ISR_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)":"                                             \
-  );                                                                                                \
-}
+    #define portENTER_SWITCHING_ISR()                                                                                                                                                                                                                                                                                                                                       \
+    {                                                                                                                                                                                                                                                                                                                                                                       \
+        extern volatile uint32_t ulCriticalNesting;                                                                                                                                                                                                                                                                                                                         \
+        extern volatile void * volatile pxCurrentTCB;                                                                                                                                                                                                                                                                                                                       \
+                                                                                                                                                                                                                                                                                                                                                                            \
+        /* When we come here */                                                                                                                                                                                                                                                                                                                                             \
+        /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */                                                                                                                                                                                                                                                                                      \
+                                                                                                                                                                                                                                                                                                                                                                            \
+        __asm__ __volatile__ (                                                                                                                                                                                                                                                                                                                                              \
+            /* Save R0..R7 */                                                                                                                                                                                                                                                                                                                                               \
+            "stm     --sp, r0-r7                                                                            \n\t"                                                                                                                                                                                                                                                           \
+                                                                                                                                                                                                                                                                                                                                                                            \
+            /* Save ulCriticalNesting variable  - R0 is overwritten */                                                                                                                                                                                                                                                                                                      \
+            "mov     r8, LWRD("ASTRINGZ ( ulCriticalNesting ) ")                                                \n\t"                                                                                                                                                                                                                                                       \
+                                                              "orh     r8, HWRD("ASTRINGZ ( ulCriticalNesting ) ")                                                \n\t"                                                                                                                                                                                                     \
+                                                                                                                "ld.w    r0, r8[0]                                                                              \n\t"                                                                                                                                                       \
+                                                                                                                "st.w    --sp, r0                                                                               \n\t"                                                                                                                                                       \
+                                                                                                                                                                                                                                                                                                                                                                            \
+            /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */                                                                                                                                                                                                                                                                    \
+            /* interrupt handler (which was of a higher priority level but decided to lower its priority */                                                                                                                                                                                                                                                                 \
+            /* level and allow other lower interrupt level to occur). */                                                                                                                                                                                                                                                                                                    \
+            /* In this case we don't want to do a task switch because we don't know what the stack */                                                                                                                                                                                                                                                                       \
+            /* currently looks like (we don't know what the interrupted interrupt handler was doing). */                                                                                                                                                                                                                                                                    \
+            /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */                                                                                                                                                                                                                                                                       \
+            /* will just be restoring the interrupt handler, no way!!! */                                                                                                                                                                                                                                                                                                   \
+            /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */                                                                                                                                                                                                                                                                                  \
+                                                                                                                "ld.w    r0, sp[9*4]                                                                            \n\t" /* Read SR in stack */                                                                                                                                \
+                                                                                                                "bfextu  r0, r0, 22, 3                                                                          \n\t" /* Extract the mode bits to R0. */                                                                                                                    \
+                                                                                                                "cp.w    r0, 1                                                                                  \n\t" /* Compare the mode bits with supervisor mode(b'001) */                                                                                               \
+                                                                                                                "brhi    LABEL_ISR_SKIP_SAVE_CONTEXT_"ASTRINGZ ( __LINE__ ) "                                       \n\t"                                                                                                                                                   \
+                                                                                                                                                                                                                                                                                                                                                                            \
+            /* Store SP in the first member of the structure pointed to by pxCurrentTCB */                                                                                                                                                                                                                                                                                  \
+                                                                                                                                                                            "mov     r8, LWRD("ASTRINGZ ( pxCurrentTCB ) ")                                                     \n\t"                                                                                       \
+                                                                                                                                                                                                                         "orh     r8, HWRD("ASTRINGZ ( pxCurrentTCB ) ")                                                     \n\t"                                          \
+                                                                                                                                                                                                                                                                      "ld.w    r0, r8[0]                                                                              \n\t" \
+                                                                                                                                                                                                                                                                      "st.w    r0[0], sp                                                                              \n"   \
+                                                                                                                                                                                                                                                                                                                                                                            \
+                                                                                                                                                                                                                                                                      "LABEL_ISR_SKIP_SAVE_CONTEXT_"ASTRINGZ ( __LINE__ ) ":"                                               \
+            );                                                                                                                                                                                                                                                                                                                                                              \
+    }
 
 
 /*
  * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1
  */
-#define portEXIT_SWITCHING_ISR()                                                                    \
-{                                                                                                   \
-  extern volatile uint32_t ulCriticalNesting;                                               \
-  extern volatile void *volatile pxCurrentTCB;                                                      \
-                                                                                                    \
-  __asm__ __volatile__ (                                                                            \
-    /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */    \
-    /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
-    /* level and allow other lower interrupt level to occur). */                                    \
-    /* In this case it's of no use to switch context and restore a new SP because we purposedly */  \
-    /* did not previously save SP in its TCB. */                                                    \
-    "ld.w    r0, sp[9*4]                                                                            \n\t" /* Read SR in stack */\
-    "bfextu  r0, r0, 22, 3                                                                          \n\t" /* Extract the mode bits to R0. */\
-    "cp.w    r0, 1                                                                                  \n\t" /* Compare the mode bits with supervisor mode(b'001) */\
-    "brhi    LABEL_ISR_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)"                                    \n\t"\
-                                                                                                    \
-    /* If a switch is required then we just need to call */                                         \
-    /* vTaskSwitchContext() as the context has already been */                                      \
-    /* saved. */                                                                                    \
-    "cp.w    r12, 1                                                                                 \n\t" /* Check if Switch context is required. */\
-    "brne    LABEL_ISR_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)":C"                                      \
-  );                                                                                                \
-                                                                                                    \
-  /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */\
-  portENTER_CRITICAL();                                                                             \
-  vTaskSwitchContext();                                                                             \
-  portEXIT_CRITICAL();                                                                              \
-                                                                                                    \
-  __asm__ __volatile__ (                                                                            \
-    "LABEL_ISR_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)":                                                \n\t"\
-    /* Restore the context of which ever task is now the highest */                                 \
-    /* priority that is ready to run. */                                                            \
-                                                                                                    \
-    /* Restore all registers */                                                                     \
-                                                                                                    \
-    /* Set SP to point to new stack */                                                              \
-    "mov     r8, LWRD("ASTRINGZ(pxCurrentTCB)")                                                     \n\t"\
-    "orh     r8, HWRD("ASTRINGZ(pxCurrentTCB)")                                                     \n\t"\
-    "ld.w    r0, r8[0]                                                                              \n\t"\
-    "ld.w    sp, r0[0]                                                                              \n"\
-                                                                                                    \
-    "LABEL_ISR_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)":                                           \n\t"\
-                                                                                                    \
-    /* Restore ulCriticalNesting variable */                                                        \
-    "ld.w    r0, sp++                                                                               \n\t"\
-    "mov     r8, LWRD("ASTRINGZ(ulCriticalNesting)")                                                \n\t"\
-    "orh     r8, HWRD("ASTRINGZ(ulCriticalNesting)")                                                \n\t"\
-    "st.w    r8[0], r0                                                                              \n\t"\
-                                                                                                    \
-    /* Restore R0..R7 */                                                                            \
-    "ldm     sp++, r0-r7                                                                            \n\t"\
-                                                                                                    \
-    /* Now, the stack should be R8..R12, LR, PC and SR  */                                          \
-    "rete"                                                                                          \
-  );                                                                                                \
-                                                                                                    \
-  /* Force import of global symbols from assembly */                                                \
-  ulCriticalNesting;                                                                                \
-  pxCurrentTCB;                                                                                     \
-}
+    #define portEXIT_SWITCHING_ISR()                                                                                                                                                                                                                                                                                                                                                                                     \
+    {                                                                                                                                                                                                                                                                                                                                                                                                                    \
+        extern volatile uint32_t ulCriticalNesting;                                                                                                                                                                                                                                                                                                                                                                      \
+        extern volatile void * volatile pxCurrentTCB;                                                                                                                                                                                                                                                                                                                                                                    \
+                                                                                                                                                                                                                                                                                                                                                                                                                         \
+        __asm__ __volatile__ (                                                                                                                                                                                                                                                                                                                                                                                           \
+            /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */                                                                                                                                                                                                                                                                                                                 \
+            /* interrupt handler (which was of a higher priority level but decided to lower its priority */                                                                                                                                                                                                                                                                                                              \
+            /* level and allow other lower interrupt level to occur). */                                                                                                                                                                                                                                                                                                                                                 \
+            /* In this case it's of no use to switch context and restore a new SP because we purposely */                                                                                                                                                                                                                                                                                                                \
+            /* did not previously save SP in its TCB. */                                                                                                                                                                                                                                                                                                                                                                 \
+            "ld.w    r0, sp[9*4]                                                                            \n\t" /* Read SR in stack */                                                                                                                                                                                                                                                                                 \
+            "bfextu  r0, r0, 22, 3                                                                          \n\t" /* Extract the mode bits to R0. */                                                                                                                                                                                                                                                                     \
+            "cp.w    r0, 1                                                                                  \n\t" /* Compare the mode bits with supervisor mode(b'001) */                                                                                                                                                                                                                                                \
+            "brhi    LABEL_ISR_SKIP_RESTORE_CONTEXT_"ASTRINGZ ( __LINE__ ) "                                    \n\t"                                                                                                                                                                                                                                                                                                    \
+                                                                                                                                                                                                                                                                                                                                                                                                                         \
+            /* If a switch is required then we just need to call */                                                                                                                                                                                                                                                                                                                                                      \
+            /* vTaskSwitchContext() as the context has already been */                                                                                                                                                                                                                                                                                                                                                   \
+            /* saved. */                                                                                                                                                                                                                                                                                                                                                                                                 \
+                                                                           "cp.w    r12, 1                                                                                 \n\t" /* Check if Switch context is required. */                                                                                                                                                                                              \
+                                                                           "brne    LABEL_ISR_RESTORE_CONTEXT_"ASTRINGZ ( __LINE__ ) ":C"                                                                                                                                                                                                                                                                                \
+            );                                                                                                                                                                                                                                                                                                                                                                                                           \
+                                                                                                                                                                                                                                                                                                                                                                                                                         \
+        /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */                                                                                                                                                                                                                                                                                                           \
+        portENTER_CRITICAL();                                                                                                                                                                                                                                                                                                                                                                                            \
+        vTaskSwitchContext();                                                                                                                                                                                                                                                                                                                                                                                            \
+        portEXIT_CRITICAL();                                                                                                                                                                                                                                                                                                                                                                                             \
+                                                                                                                                                                                                                                                                                                                                                                                                                         \
+        __asm__ __volatile__ (                                                                                                                                                                                                                                                                                                                                                                                           \
+            "LABEL_ISR_RESTORE_CONTEXT_"ASTRINGZ ( __LINE__ ) ":                                                \n\t"                                                                                                                                                                                                                                                                                                    \
+            /* Restore the context of which ever task is now the highest */                                                                                                                                                                                                                                                                                                                                              \
+            /* priority that is ready to run. */                                                                                                                                                                                                                                                                                                                                                                         \
+                                                                                                                                                                                                                                                                                                                                                                                                                         \
+            /* Restore all registers */                                                                                                                                                                                                                                                                                                                                                                                  \
+                                                                                                                                                                                                                                                                                                                                                                                                                         \
+            /* Set SP to point to new stack */                                                                                                                                                                                                                                                                                                                                                                           \
+                                                              "mov     r8, LWRD("ASTRINGZ ( pxCurrentTCB ) ")                                                     \n\t"                                                                                                                                                                                                                                                  \
+                                                                                                           "orh     r8, HWRD("ASTRINGZ ( pxCurrentTCB ) ")                                                     \n\t"                                                                                                                                                                                                     \
+                                                                                                                                                        "ld.w    r0, r8[0]                                                                              \n\t"                                                                                                                                                            \
+                                                                                                                                                        "ld.w    sp, r0[0]                                                                              \n"                                                                                                                                                              \
+                                                                                                                                                                                                                                                                                                                                                                                                                         \
+                                                                                                                                                        "LABEL_ISR_SKIP_RESTORE_CONTEXT_"ASTRINGZ ( __LINE__ ) ":                                           \n\t"                                                                                                                                                        \
+                                                                                                                                                                                                                                                                                                                                                                                                                         \
+            /* Restore ulCriticalNesting variable */                                                                                                                                                                                                                                                                                                                                                                     \
+                                                                                                                                                                                                               "ld.w    r0, sp++                                                                               \n\t"                                                                                                     \
+                                                                                                                                                                                                               "mov     r8, LWRD("ASTRINGZ ( ulCriticalNesting ) ")                                                \n\t"                                                                                                 \
+                                                                                                                                                                                                                                                                 "orh     r8, HWRD("ASTRINGZ ( ulCriticalNesting ) ")                                                \n\t"                                               \
+                                                                                                                                                                                                                                                                                                                   "st.w    r8[0], r0                                                                              \n\t" \
+                                                                                                                                                                                                                                                                                                                                                                                                                         \
+            /* Restore R0..R7 */                                                                                                                                                                                                                                                                                                                                                                                         \
+                                                                                                                                                                                                                                                                                                                   "ldm     sp++, r0-r7                                                                            \n\t" \
+                                                                                                                                                                                                                                                                                                                                                                                                                         \
+            /* Now, the stack should be R8..R12, LR, PC and SR  */                                                                                                                                                                                                                                                                                                                                                       \
+                                                                                                                                                                                                                                                                                                                   "rete"                                                                                                \
+            );                                                                                                                                                                                                                                                                                                                                                                                                           \
+                                                                                                                                                                                                                                                                                                                                                                                                                         \
+        /* Force import of global symbols from assembly */                                                                                                                                                                                                                                                                                                                                                               \
+        ulCriticalNesting;                                                                                                                                                                                                                                                                                                                                                                                               \
+        pxCurrentTCB;                                                                                                                                                                                                                                                                                                                                                                                                    \
+    }
 
-#endif
+#endif /* if configUSE_PREEMPTION == 0 */
 
 
-#define portYIELD()                 {__asm__ __volatile__ ("scall");}
+#define portYIELD()                                           { __asm__ __volatile__ ( "scall" ); }
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/IAR/AVR32_UC3/read.c b/portable/IAR/AVR32_UC3/read.c
index e0fbed04d..bbdc0781b 100644
--- a/portable/IAR/AVR32_UC3/read.c
+++ b/portable/IAR/AVR32_UC3/read.c
@@ -27,20 +27,21 @@
  */
 
 /*This file is prepared for Doxygen automatic documentation generation.*/
+
 /*! \file *********************************************************************
- *
- * \brief System-specific implementation of the \ref __read function used by
-          the standard library.
- *
- * - Compiler:           IAR EWAVR32
- * - Supported devices:  All AVR32 devices with a USART module can be used.
- * - AppNote:
- *
- * \author               Atmel Corporation (Now Microchip):
- *                                        https://www.microchip.com \n
- *                       Support and FAQ: https://www.microchip.com/support/
- *
- ******************************************************************************/
+*
+* \brief System-specific implementation of the \ref __read function used by
+*         the standard library.
+*
+* - Compiler:           IAR EWAVR32
+* - Supported devices:  All AVR32 devices with a USART module can be used.
+* - AppNote:
+*
+* \author               Atmel Corporation (Now Microchip):
+*                                        https://www.microchip.com \n
+*                       Support and FAQ: https://www.microchip.com/support/
+*
+******************************************************************************/
 
 /*
  * Copyright (c) 2007, Atmel Corporation All rights reserved.
@@ -82,7 +83,7 @@ _STD_BEGIN
 #pragma module_name = "?__read"
 
 
-extern volatile avr32_usart_t *volatile stdio_usart_base;
+extern volatile avr32_usart_t * volatile stdio_usart_base;
 
 
 /*! \brief Reads a number of bytes, at most \a size, into the memory area
@@ -95,28 +96,33 @@ extern volatile avr32_usart_t *volatile stdio_usart_base;
  * \return The number of bytes read, \c 0 at the end of the file, or
  *         \c _LLIO_ERROR on failure.
  */
-size_t __read(int handle, uint8_t *buffer, size_t size)
+size_t __read( int handle,
+               uint8_t * buffer,
+               size_t size )
 {
-  int nChars = 0;
+    int nChars = 0;
 
-  // This implementation only reads from stdin.
-  // For all other file handles, it returns failure.
-  if (handle != _LLIO_STDIN)
-  {
-    return _LLIO_ERROR;
-  }
+    /* This implementation only reads from stdin. */
+    /* For all other file handles, it returns failure. */
+    if( handle != _LLIO_STDIN )
+    {
+        return _LLIO_ERROR;
+    }
 
-  for (; size > 0; --size)
-  {
-    int c = usart_getchar(stdio_usart_base);
-    if (c < 0)
-      break;
+    for( ; size > 0; --size )
+    {
+        int c = usart_getchar( stdio_usart_base );
 
-    *buffer++ = c;
-    ++nChars;
-  }
+        if( c < 0 )
+        {
+            break;
+        }
 
-  return nChars;
+        *buffer++ = c;
+        ++nChars;
+    }
+
+    return nChars;
 }
 
 
diff --git a/portable/IAR/AVR32_UC3/write.c b/portable/IAR/AVR32_UC3/write.c
index c6e94292e..139f45277 100644
--- a/portable/IAR/AVR32_UC3/write.c
+++ b/portable/IAR/AVR32_UC3/write.c
@@ -27,20 +27,21 @@
  */
 
 /*This file is prepared for Doxygen automatic documentation generation.*/
+
 /*! \file *********************************************************************
- *
- * \brief System-specific implementation of the \ref __write function used by
-          the standard library.
- *
- * - Compiler:           IAR EWAVR32
- * - Supported devices:  All AVR32 devices with a USART module can be used.
- * - AppNote:
- *
- * \author               Atmel Corporation (Now Microchip):
- *                                        https://www.microchip.com \n
- *                       Support and FAQ: https://www.microchip.com/support
- *
- ******************************************************************************/
+*
+* \brief System-specific implementation of the \ref __write function used by
+*         the standard library.
+*
+* - Compiler:           IAR EWAVR32
+* - Supported devices:  All AVR32 devices with a USART module can be used.
+* - AppNote:
+*
+* \author               Atmel Corporation (Now Microchip):
+*                                        https://www.microchip.com \n
+*                       Support and FAQ: https://www.microchip.com/support
+*
+******************************************************************************/
 
 /*
  * Copyright (c) 2007, Atmel Corporation All rights reserved.
@@ -82,8 +83,8 @@ _STD_BEGIN
 #pragma module_name = "?__write"
 
 
-//! Pointer to the base of the USART module instance to use for stdio.
-__no_init volatile avr32_usart_t *volatile stdio_usart_base;
+/*! Pointer to the base of the USART module instance to use for stdio. */
+__no_init volatile avr32_usart_t * volatile stdio_usart_base;
 
 
 /*! \brief Writes a number of bytes, at most \a size, from the memory area
@@ -99,34 +100,36 @@ __no_init volatile avr32_usart_t *volatile stdio_usart_base;
  *
  * \return The number of bytes written, or \c _LLIO_ERROR on failure.
  */
-size_t __write(int handle, const uint8_t *buffer, size_t size)
+size_t __write( int handle,
+                const uint8_t * buffer,
+                size_t size )
 {
-  size_t nChars = 0;
+    size_t nChars = 0;
 
-  if (buffer == 0)
-  {
-    // This means that we should flush internal buffers.
-    return 0;
-  }
-
-  // This implementation only writes to stdout and stderr.
-  // For all other file handles, it returns failure.
-  if (handle != _LLIO_STDOUT && handle != _LLIO_STDERR)
-  {
-    return _LLIO_ERROR;
-  }
-
-  for (; size != 0; --size)
-  {
-    if (usart_putchar(stdio_usart_base, *buffer++) < 0)
+    if( buffer == 0 )
     {
-      return _LLIO_ERROR;
+        /* This means that we should flush internal buffers. */
+        return 0;
     }
 
-    ++nChars;
-  }
+    /* This implementation only writes to stdout and stderr. */
+    /* For all other file handles, it returns failure. */
+    if( ( handle != _LLIO_STDOUT ) && ( handle != _LLIO_STDERR ) )
+    {
+        return _LLIO_ERROR;
+    }
 
-  return nChars;
+    for( ; size != 0; --size )
+    {
+        if( usart_putchar( stdio_usart_base, *buffer++ ) < 0 )
+        {
+            return _LLIO_ERROR;
+        }
+
+        ++nChars;
+    }
+
+    return nChars;
 }
 
 
diff --git a/portable/IAR/AVR_AVRDx/portmacro.h b/portable/IAR/AVR_AVRDx/portmacro.h
index cb3cb7ec2..13c3f6e6b 100644
--- a/portable/IAR/AVR_AVRDx/portmacro.h
+++ b/portable/IAR/AVR_AVRDx/portmacro.h
@@ -64,8 +64,8 @@ typedef unsigned char    UBaseType_t;
     typedef uint16_t     TickType_t;
     #define portMAX_DELAY    ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY ( TickType_t )    ( 0xFFFFFFFFUL )
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) ( 0xFFFFFFFFUL )
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
diff --git a/portable/IAR/AVR_Mega0/portmacro.h b/portable/IAR/AVR_Mega0/portmacro.h
index cb3cb7ec2..13c3f6e6b 100644
--- a/portable/IAR/AVR_Mega0/portmacro.h
+++ b/portable/IAR/AVR_Mega0/portmacro.h
@@ -64,8 +64,8 @@ typedef unsigned char    UBaseType_t;
     typedef uint16_t     TickType_t;
     #define portMAX_DELAY    ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY ( TickType_t )    ( 0xFFFFFFFFUL )
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) ( 0xFFFFFFFFUL )
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
diff --git a/portable/IAR/AtmelSAM7S64/AT91SAM7S64.h b/portable/IAR/AtmelSAM7S64/AT91SAM7S64.h
index 107754719..2dbceba43 100644
--- a/portable/IAR/AtmelSAM7S64/AT91SAM7S64.h
+++ b/portable/IAR/AtmelSAM7S64/AT91SAM7S64.h
@@ -1,1914 +1,1936 @@
-// ----------------------------------------------------------------------------
-//          ATMEL Microcontroller Software Support  -  ROUSSET  -
-// ----------------------------------------------------------------------------
-//  The software is delivered "AS IS" without warranty or condition of any
-//  kind, either express, implied or statutory. This includes without
-//  limitation any warranty or condition with respect to merchantability or
-//  fitness for any particular purpose, or against the infringements of
-//  intellectual property rights of others.
-// ----------------------------------------------------------------------------
-// File Name           : AT91SAM7S64.h
-// Object              : AT91SAM7S64 definitions
-// Generated           : AT91 SW Application Group  07/16/2004 (07:43:08)
-//
-// CVS Reference       : /AT91SAM7S64.pl/1.12/Mon Jul 12 13:02:30 2004//
-// CVS Reference       : /SYSC_SAM7Sxx.pl/1.5/Mon Jul 12 16:22:12 2004//
-// CVS Reference       : /MC_SAM02.pl/1.3/Wed Mar 10 08:37:04 2004//
-// CVS Reference       : /UDP_1765B.pl/1.3/Fri Aug  2 14:45:38 2002//
-// CVS Reference       : /AIC_1796B.pl/1.1.1.1/Fri Jun 28 09:36:48 2002//
-// CVS Reference       : /lib_pmc_SAM.h/1.6/Tue Apr 27 13:53:52 2004//
-// CVS Reference       : /PIO_1725D.pl/1.1.1.1/Fri Jun 28 09:36:48 2002//
-// CVS Reference       : /DBGU_1754A.pl/1.4/Fri Jan 31 12:18:24 2003//
-// CVS Reference       : /US_1739C.pl/1.2/Mon Jul 12 17:26:24 2004//
-// CVS Reference       : /SPI2.pl/1.2/Fri Oct 17 08:13:40 2003//
-// CVS Reference       : /SSC_1762A.pl/1.2/Fri Nov  8 13:26:40 2002//
-// CVS Reference       : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//
-// CVS Reference       : /TWI_1761B.pl/1.4/Fri Feb  7 10:30:08 2003//
-// CVS Reference       : /PDC_1734B.pl/1.2/Thu Nov 21 16:38:24 2002//
-// CVS Reference       : /ADC_SAM.pl/1.7/Fri Oct 17 08:12:38 2003//
-// CVS Reference       : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//
-// ----------------------------------------------------------------------------
+/* ---------------------------------------------------------------------------- */
+/*          ATMEL Microcontroller Software Support  -  ROUSSET  - */
+/* ---------------------------------------------------------------------------- */
+/*  The software is delivered "AS IS" without warranty or condition of any */
+/*  kind, either express, implied or statutory. This includes without */
+/*  limitation any warranty or condition with respect to merchantability or */
+/*  fitness for any particular purpose, or against the infringements of */
+/*  intellectual property rights of others. */
+/* ---------------------------------------------------------------------------- */
+/* File Name           : AT91SAM7S64.h */
+/* Object              : AT91SAM7S64 definitions */
+/* Generated           : AT91 SW Application Group  07/16/2004 (07:43:08) */
+/* */
+/* CVS Reference       : /AT91SAM7S64.pl/1.12/Mon Jul 12 13:02:30 2004// */
+/* CVS Reference       : /SYSC_SAM7Sxx.pl/1.5/Mon Jul 12 16:22:12 2004// */
+/* CVS Reference       : /MC_SAM02.pl/1.3/Wed Mar 10 08:37:04 2004// */
+/* CVS Reference       : /UDP_1765B.pl/1.3/Fri Aug  2 14:45:38 2002// */
+/* CVS Reference       : /AIC_1796B.pl/1.1.1.1/Fri Jun 28 09:36:48 2002// */
+/* CVS Reference       : /lib_pmc_SAM.h/1.6/Tue Apr 27 13:53:52 2004// */
+/* CVS Reference       : /PIO_1725D.pl/1.1.1.1/Fri Jun 28 09:36:48 2002// */
+/* CVS Reference       : /DBGU_1754A.pl/1.4/Fri Jan 31 12:18:24 2003// */
+/* CVS Reference       : /US_1739C.pl/1.2/Mon Jul 12 17:26:24 2004// */
+/* CVS Reference       : /SPI2.pl/1.2/Fri Oct 17 08:13:40 2003// */
+/* CVS Reference       : /SSC_1762A.pl/1.2/Fri Nov  8 13:26:40 2002// */
+/* CVS Reference       : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// */
+/* CVS Reference       : /TWI_1761B.pl/1.4/Fri Feb  7 10:30:08 2003// */
+/* CVS Reference       : /PDC_1734B.pl/1.2/Thu Nov 21 16:38:24 2002// */
+/* CVS Reference       : /ADC_SAM.pl/1.7/Fri Oct 17 08:12:38 2003// */
+/* CVS Reference       : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// */
+/* ---------------------------------------------------------------------------- */
 
 #ifndef AT91SAM7S64_H
 #define AT91SAM7S64_H
 
-typedef volatile unsigned int AT91_REG;// Hardware register definition
+typedef volatile unsigned int AT91_REG; /* Hardware register definition */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR System Peripherals
-// *****************************************************************************
-typedef struct _AT91S_SYSC {
-    AT91_REG     SYSC_AIC_SMR[32];  // Source Mode Register
-    AT91_REG     SYSC_AIC_SVR[32];  // Source Vector Register
-    AT91_REG     SYSC_AIC_IVR;  // IRQ Vector Register
-    AT91_REG     SYSC_AIC_FVR;  // FIQ Vector Register
-    AT91_REG     SYSC_AIC_ISR;  // Interrupt Status Register
-    AT91_REG     SYSC_AIC_IPR;  // Interrupt Pending Register
-    AT91_REG     SYSC_AIC_IMR;  // Interrupt Mask Register
-    AT91_REG     SYSC_AIC_CISR;     // Core Interrupt Status Register
-    AT91_REG     Reserved0[2];  //
-    AT91_REG     SYSC_AIC_IECR;     // Interrupt Enable Command Register
-    AT91_REG     SYSC_AIC_IDCR;     // Interrupt Disable Command Register
-    AT91_REG     SYSC_AIC_ICCR;     // Interrupt Clear Command Register
-    AT91_REG     SYSC_AIC_ISCR;     // Interrupt Set Command Register
-    AT91_REG     SYSC_AIC_EOICR;    // End of Interrupt Command Register
-    AT91_REG     SYSC_AIC_SPU;  // Spurious Vector Register
-    AT91_REG     SYSC_AIC_DCR;  // Debug Control Register (Protect)
-    AT91_REG     Reserved1[1];  //
-    AT91_REG     SYSC_AIC_FFER;     // Fast Forcing Enable Register
-    AT91_REG     SYSC_AIC_FFDR;     // Fast Forcing Disable Register
-    AT91_REG     SYSC_AIC_FFSR;     // Fast Forcing Status Register
-    AT91_REG     Reserved2[45];     //
-    AT91_REG     SYSC_DBGU_CR;  // Control Register
-    AT91_REG     SYSC_DBGU_MR;  // Mode Register
-    AT91_REG     SYSC_DBGU_IER;     // Interrupt Enable Register
-    AT91_REG     SYSC_DBGU_IDR;     // Interrupt Disable Register
-    AT91_REG     SYSC_DBGU_IMR;     // Interrupt Mask Register
-    AT91_REG     SYSC_DBGU_CSR;     // Channel Status Register
-    AT91_REG     SYSC_DBGU_RHR;     // Receiver Holding Register
-    AT91_REG     SYSC_DBGU_THR;     // Transmitter Holding Register
-    AT91_REG     SYSC_DBGU_BRGR;    // Baud Rate Generator Register
-    AT91_REG     Reserved3[7];  //
-    AT91_REG     SYSC_DBGU_C1R;     // Chip ID1 Register
-    AT91_REG     SYSC_DBGU_C2R;     // Chip ID2 Register
-    AT91_REG     SYSC_DBGU_FNTR;    // Force NTRST Register
-    AT91_REG     Reserved4[45];     //
-    AT91_REG     SYSC_DBGU_RPR;     // Receive Pointer Register
-    AT91_REG     SYSC_DBGU_RCR;     // Receive Counter Register
-    AT91_REG     SYSC_DBGU_TPR;     // Transmit Pointer Register
-    AT91_REG     SYSC_DBGU_TCR;     // Transmit Counter Register
-    AT91_REG     SYSC_DBGU_RNPR;    // Receive Next Pointer Register
-    AT91_REG     SYSC_DBGU_RNCR;    // Receive Next Counter Register
-    AT91_REG     SYSC_DBGU_TNPR;    // Transmit Next Pointer Register
-    AT91_REG     SYSC_DBGU_TNCR;    // Transmit Next Counter Register
-    AT91_REG     SYSC_DBGU_PTCR;    // PDC Transfer Control Register
-    AT91_REG     SYSC_DBGU_PTSR;    // PDC Transfer Status Register
-    AT91_REG     Reserved5[54];     //
-    AT91_REG     SYSC_PIOA_PER;     // PIO Enable Register
-    AT91_REG     SYSC_PIOA_PDR;     // PIO Disable Register
-    AT91_REG     SYSC_PIOA_PSR;     // PIO Status Register
-    AT91_REG     Reserved6[1];  //
-    AT91_REG     SYSC_PIOA_OER;     // Output Enable Register
-    AT91_REG     SYSC_PIOA_ODR;     // Output Disable Registerr
-    AT91_REG     SYSC_PIOA_OSR;     // Output Status Register
-    AT91_REG     Reserved7[1];  //
-    AT91_REG     SYSC_PIOA_IFER;    // Input Filter Enable Register
-    AT91_REG     SYSC_PIOA_IFDR;    // Input Filter Disable Register
-    AT91_REG     SYSC_PIOA_IFSR;    // Input Filter Status Register
-    AT91_REG     Reserved8[1];  //
-    AT91_REG     SYSC_PIOA_SODR;    // Set Output Data Register
-    AT91_REG     SYSC_PIOA_CODR;    // Clear Output Data Register
-    AT91_REG     SYSC_PIOA_ODSR;    // Output Data Status Register
-    AT91_REG     SYSC_PIOA_PDSR;    // Pin Data Status Register
-    AT91_REG     SYSC_PIOA_IER;     // Interrupt Enable Register
-    AT91_REG     SYSC_PIOA_IDR;     // Interrupt Disable Register
-    AT91_REG     SYSC_PIOA_IMR;     // Interrupt Mask Register
-    AT91_REG     SYSC_PIOA_ISR;     // Interrupt Status Register
-    AT91_REG     SYSC_PIOA_MDER;    // Multi-driver Enable Register
-    AT91_REG     SYSC_PIOA_MDDR;    // Multi-driver Disable Register
-    AT91_REG     SYSC_PIOA_MDSR;    // Multi-driver Status Register
-    AT91_REG     Reserved9[1];  //
-    AT91_REG     SYSC_PIOA_PPUDR;   // Pull-up Disable Register
-    AT91_REG     SYSC_PIOA_PPUER;   // Pull-up Enable Register
-    AT91_REG     SYSC_PIOA_PPUSR;   // Pad Pull-up Status Register
-    AT91_REG     Reserved10[1];     //
-    AT91_REG     SYSC_PIOA_ASR;     // Select A Register
-    AT91_REG     SYSC_PIOA_BSR;     // Select B Register
-    AT91_REG     SYSC_PIOA_ABSR;    // AB Select Status Register
-    AT91_REG     Reserved11[9];     //
-    AT91_REG     SYSC_PIOA_OWER;    // Output Write Enable Register
-    AT91_REG     SYSC_PIOA_OWDR;    // Output Write Disable Register
-    AT91_REG     SYSC_PIOA_OWSR;    // Output Write Status Register
-    AT91_REG     Reserved12[469];   //
-    AT91_REG     SYSC_PMC_SCER;     // System Clock Enable Register
-    AT91_REG     SYSC_PMC_SCDR;     // System Clock Disable Register
-    AT91_REG     SYSC_PMC_SCSR;     // System Clock Status Register
-    AT91_REG     Reserved13[1];     //
-    AT91_REG     SYSC_PMC_PCER;     // Peripheral Clock Enable Register
-    AT91_REG     SYSC_PMC_PCDR;     // Peripheral Clock Disable Register
-    AT91_REG     SYSC_PMC_PCSR;     // Peripheral Clock Status Register
-    AT91_REG     Reserved14[1];     //
-    AT91_REG     SYSC_PMC_MOR;  // Main Oscillator Register
-    AT91_REG     SYSC_PMC_MCFR;     // Main Clock  Frequency Register
-    AT91_REG     Reserved15[1];     //
-    AT91_REG     SYSC_PMC_PLLR;     // PLL Register
-    AT91_REG     SYSC_PMC_MCKR;     // Master Clock Register
-    AT91_REG     Reserved16[3];     //
-    AT91_REG     SYSC_PMC_PCKR[8];  // Programmable Clock Register
-    AT91_REG     SYSC_PMC_IER;  // Interrupt Enable Register
-    AT91_REG     SYSC_PMC_IDR;  // Interrupt Disable Register
-    AT91_REG     SYSC_PMC_SR;   // Status Register
-    AT91_REG     SYSC_PMC_IMR;  // Interrupt Mask Register
-    AT91_REG     Reserved17[36];    //
-    AT91_REG     SYSC_RSTC_RCR;     // Reset Control Register
-    AT91_REG     SYSC_RSTC_RSR;     // Reset Status Register
-    AT91_REG     SYSC_RSTC_RMR;     // Reset Mode Register
-    AT91_REG     Reserved18[5];     //
-    AT91_REG     SYSC_RTTC_RTMR;    // Real-time Mode Register
-    AT91_REG     SYSC_RTTC_RTAR;    // Real-time Alarm Register
-    AT91_REG     SYSC_RTTC_RTVR;    // Real-time Value Register
-    AT91_REG     SYSC_RTTC_RTSR;    // Real-time Status Register
-    AT91_REG     SYSC_PITC_PIMR;    // Period Interval Mode Register
-    AT91_REG     SYSC_PITC_PISR;    // Period Interval Status Register
-    AT91_REG     SYSC_PITC_PIVR;    // Period Interval Value Register
-    AT91_REG     SYSC_PITC_PIIR;    // Period Interval Image Register
-    AT91_REG     SYSC_WDTC_WDCR;    // Watchdog Control Register
-    AT91_REG     SYSC_WDTC_WDMR;    // Watchdog Mode Register
-    AT91_REG     SYSC_WDTC_WDSR;    // Watchdog Status Register
-    AT91_REG     Reserved19[5];     //
-    AT91_REG     SYSC_SYSC_VRPM;    // Voltage Regulator Power Mode Register
-} AT91S_SYSC, *AT91PS_SYSC;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR System Peripherals */
+/* ***************************************************************************** */
+typedef struct _AT91S_SYSC
+{
+    AT91_REG SYSC_AIC_SMR[ 32 ]; /* Source Mode Register */
+    AT91_REG SYSC_AIC_SVR[ 32 ]; /* Source Vector Register */
+    AT91_REG SYSC_AIC_IVR;       /* IRQ Vector Register */
+    AT91_REG SYSC_AIC_FVR;       /* FIQ Vector Register */
+    AT91_REG SYSC_AIC_ISR;       /* Interrupt Status Register */
+    AT91_REG SYSC_AIC_IPR;       /* Interrupt Pending Register */
+    AT91_REG SYSC_AIC_IMR;       /* Interrupt Mask Register */
+    AT91_REG SYSC_AIC_CISR;      /* Core Interrupt Status Register */
+    AT91_REG Reserved0[ 2 ];     /* */
+    AT91_REG SYSC_AIC_IECR;      /* Interrupt Enable Command Register */
+    AT91_REG SYSC_AIC_IDCR;      /* Interrupt Disable Command Register */
+    AT91_REG SYSC_AIC_ICCR;      /* Interrupt Clear Command Register */
+    AT91_REG SYSC_AIC_ISCR;      /* Interrupt Set Command Register */
+    AT91_REG SYSC_AIC_EOICR;     /* End of Interrupt Command Register */
+    AT91_REG SYSC_AIC_SPU;       /* Spurious Vector Register */
+    AT91_REG SYSC_AIC_DCR;       /* Debug Control Register (Protect) */
+    AT91_REG Reserved1[ 1 ];     /* */
+    AT91_REG SYSC_AIC_FFER;      /* Fast Forcing Enable Register */
+    AT91_REG SYSC_AIC_FFDR;      /* Fast Forcing Disable Register */
+    AT91_REG SYSC_AIC_FFSR;      /* Fast Forcing Status Register */
+    AT91_REG Reserved2[ 45 ];    /* */
+    AT91_REG SYSC_DBGU_CR;       /* Control Register */
+    AT91_REG SYSC_DBGU_MR;       /* Mode Register */
+    AT91_REG SYSC_DBGU_IER;      /* Interrupt Enable Register */
+    AT91_REG SYSC_DBGU_IDR;      /* Interrupt Disable Register */
+    AT91_REG SYSC_DBGU_IMR;      /* Interrupt Mask Register */
+    AT91_REG SYSC_DBGU_CSR;      /* Channel Status Register */
+    AT91_REG SYSC_DBGU_RHR;      /* Receiver Holding Register */
+    AT91_REG SYSC_DBGU_THR;      /* Transmitter Holding Register */
+    AT91_REG SYSC_DBGU_BRGR;     /* Baud Rate Generator Register */
+    AT91_REG Reserved3[ 7 ];     /* */
+    AT91_REG SYSC_DBGU_C1R;      /* Chip ID1 Register */
+    AT91_REG SYSC_DBGU_C2R;      /* Chip ID2 Register */
+    AT91_REG SYSC_DBGU_FNTR;     /* Force NTRST Register */
+    AT91_REG Reserved4[ 45 ];    /* */
+    AT91_REG SYSC_DBGU_RPR;      /* Receive Pointer Register */
+    AT91_REG SYSC_DBGU_RCR;      /* Receive Counter Register */
+    AT91_REG SYSC_DBGU_TPR;      /* Transmit Pointer Register */
+    AT91_REG SYSC_DBGU_TCR;      /* Transmit Counter Register */
+    AT91_REG SYSC_DBGU_RNPR;     /* Receive Next Pointer Register */
+    AT91_REG SYSC_DBGU_RNCR;     /* Receive Next Counter Register */
+    AT91_REG SYSC_DBGU_TNPR;     /* Transmit Next Pointer Register */
+    AT91_REG SYSC_DBGU_TNCR;     /* Transmit Next Counter Register */
+    AT91_REG SYSC_DBGU_PTCR;     /* PDC Transfer Control Register */
+    AT91_REG SYSC_DBGU_PTSR;     /* PDC Transfer Status Register */
+    AT91_REG Reserved5[ 54 ];    /* */
+    AT91_REG SYSC_PIOA_PER;      /* PIO Enable Register */
+    AT91_REG SYSC_PIOA_PDR;      /* PIO Disable Register */
+    AT91_REG SYSC_PIOA_PSR;      /* PIO Status Register */
+    AT91_REG Reserved6[ 1 ];     /* */
+    AT91_REG SYSC_PIOA_OER;      /* Output Enable Register */
+    AT91_REG SYSC_PIOA_ODR;      /* Output Disable Registerr */
+    AT91_REG SYSC_PIOA_OSR;      /* Output Status Register */
+    AT91_REG Reserved7[ 1 ];     /* */
+    AT91_REG SYSC_PIOA_IFER;     /* Input Filter Enable Register */
+    AT91_REG SYSC_PIOA_IFDR;     /* Input Filter Disable Register */
+    AT91_REG SYSC_PIOA_IFSR;     /* Input Filter Status Register */
+    AT91_REG Reserved8[ 1 ];     /* */
+    AT91_REG SYSC_PIOA_SODR;     /* Set Output Data Register */
+    AT91_REG SYSC_PIOA_CODR;     /* Clear Output Data Register */
+    AT91_REG SYSC_PIOA_ODSR;     /* Output Data Status Register */
+    AT91_REG SYSC_PIOA_PDSR;     /* Pin Data Status Register */
+    AT91_REG SYSC_PIOA_IER;      /* Interrupt Enable Register */
+    AT91_REG SYSC_PIOA_IDR;      /* Interrupt Disable Register */
+    AT91_REG SYSC_PIOA_IMR;      /* Interrupt Mask Register */
+    AT91_REG SYSC_PIOA_ISR;      /* Interrupt Status Register */
+    AT91_REG SYSC_PIOA_MDER;     /* Multi-driver Enable Register */
+    AT91_REG SYSC_PIOA_MDDR;     /* Multi-driver Disable Register */
+    AT91_REG SYSC_PIOA_MDSR;     /* Multi-driver Status Register */
+    AT91_REG Reserved9[ 1 ];     /* */
+    AT91_REG SYSC_PIOA_PPUDR;    /* Pull-up Disable Register */
+    AT91_REG SYSC_PIOA_PPUER;    /* Pull-up Enable Register */
+    AT91_REG SYSC_PIOA_PPUSR;    /* Pad Pull-up Status Register */
+    AT91_REG Reserved10[ 1 ];    /* */
+    AT91_REG SYSC_PIOA_ASR;      /* Select A Register */
+    AT91_REG SYSC_PIOA_BSR;      /* Select B Register */
+    AT91_REG SYSC_PIOA_ABSR;     /* AB Select Status Register */
+    AT91_REG Reserved11[ 9 ];    /* */
+    AT91_REG SYSC_PIOA_OWER;     /* Output Write Enable Register */
+    AT91_REG SYSC_PIOA_OWDR;     /* Output Write Disable Register */
+    AT91_REG SYSC_PIOA_OWSR;     /* Output Write Status Register */
+    AT91_REG Reserved12[ 469 ];  /* */
+    AT91_REG SYSC_PMC_SCER;      /* System Clock Enable Register */
+    AT91_REG SYSC_PMC_SCDR;      /* System Clock Disable Register */
+    AT91_REG SYSC_PMC_SCSR;      /* System Clock Status Register */
+    AT91_REG Reserved13[ 1 ];    /* */
+    AT91_REG SYSC_PMC_PCER;      /* Peripheral Clock Enable Register */
+    AT91_REG SYSC_PMC_PCDR;      /* Peripheral Clock Disable Register */
+    AT91_REG SYSC_PMC_PCSR;      /* Peripheral Clock Status Register */
+    AT91_REG Reserved14[ 1 ];    /* */
+    AT91_REG SYSC_PMC_MOR;       /* Main Oscillator Register */
+    AT91_REG SYSC_PMC_MCFR;      /* Main Clock  Frequency Register */
+    AT91_REG Reserved15[ 1 ];    /* */
+    AT91_REG SYSC_PMC_PLLR;      /* PLL Register */
+    AT91_REG SYSC_PMC_MCKR;      /* Master Clock Register */
+    AT91_REG Reserved16[ 3 ];    /* */
+    AT91_REG SYSC_PMC_PCKR[ 8 ]; /* Programmable Clock Register */
+    AT91_REG SYSC_PMC_IER;       /* Interrupt Enable Register */
+    AT91_REG SYSC_PMC_IDR;       /* Interrupt Disable Register */
+    AT91_REG SYSC_PMC_SR;        /* Status Register */
+    AT91_REG SYSC_PMC_IMR;       /* Interrupt Mask Register */
+    AT91_REG Reserved17[ 36 ];   /* */
+    AT91_REG SYSC_RSTC_RCR;      /* Reset Control Register */
+    AT91_REG SYSC_RSTC_RSR;      /* Reset Status Register */
+    AT91_REG SYSC_RSTC_RMR;      /* Reset Mode Register */
+    AT91_REG Reserved18[ 5 ];    /* */
+    AT91_REG SYSC_RTTC_RTMR;     /* Real-time Mode Register */
+    AT91_REG SYSC_RTTC_RTAR;     /* Real-time Alarm Register */
+    AT91_REG SYSC_RTTC_RTVR;     /* Real-time Value Register */
+    AT91_REG SYSC_RTTC_RTSR;     /* Real-time Status Register */
+    AT91_REG SYSC_PITC_PIMR;     /* Period Interval Mode Register */
+    AT91_REG SYSC_PITC_PISR;     /* Period Interval Status Register */
+    AT91_REG SYSC_PITC_PIVR;     /* Period Interval Value Register */
+    AT91_REG SYSC_PITC_PIIR;     /* Period Interval Image Register */
+    AT91_REG SYSC_WDTC_WDCR;     /* Watchdog Control Register */
+    AT91_REG SYSC_WDTC_WDMR;     /* Watchdog Mode Register */
+    AT91_REG SYSC_WDTC_WDSR;     /* Watchdog Status Register */
+    AT91_REG Reserved19[ 5 ];    /* */
+    AT91_REG SYSC_SYSC_VRPM;     /* Voltage Regulator Power Mode Register */
+} AT91S_SYSC, * AT91PS_SYSC;
 
-// -------- VRPM : (SYSC Offset: 0xd60) Voltage Regulator Power Mode Register --------
-#define AT91C_SYSC_PSTDBY     ((unsigned int) 0x1 <<  0) // (SYSC) Voltage Regulator Power Mode
+/* -------- VRPM : (SYSC Offset: 0xd60) Voltage Regulator Power Mode Register -------- */
+#define AT91C_SYSC_PSTDBY    ( ( unsigned int ) 0x1 << 0 ) /* (SYSC) Voltage Regulator Power Mode */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
-// *****************************************************************************
-typedef struct _AT91S_AIC {
-    AT91_REG     AIC_SMR[32];   // Source Mode Register
-    AT91_REG     AIC_SVR[32];   // Source Vector Register
-    AT91_REG     AIC_IVR;   // IRQ Vector Register
-    AT91_REG     AIC_FVR;   // FIQ Vector Register
-    AT91_REG     AIC_ISR;   // Interrupt Status Register
-    AT91_REG     AIC_IPR;   // Interrupt Pending Register
-    AT91_REG     AIC_IMR;   // Interrupt Mask Register
-    AT91_REG     AIC_CISR;  // Core Interrupt Status Register
-    AT91_REG     Reserved0[2];  //
-    AT91_REG     AIC_IECR;  // Interrupt Enable Command Register
-    AT91_REG     AIC_IDCR;  // Interrupt Disable Command Register
-    AT91_REG     AIC_ICCR;  // Interrupt Clear Command Register
-    AT91_REG     AIC_ISCR;  // Interrupt Set Command Register
-    AT91_REG     AIC_EOICR;     // End of Interrupt Command Register
-    AT91_REG     AIC_SPU;   // Spurious Vector Register
-    AT91_REG     AIC_DCR;   // Debug Control Register (Protect)
-    AT91_REG     Reserved1[1];  //
-    AT91_REG     AIC_FFER;  // Fast Forcing Enable Register
-    AT91_REG     AIC_FFDR;  // Fast Forcing Disable Register
-    AT91_REG     AIC_FFSR;  // Fast Forcing Status Register
-} AT91S_AIC, *AT91PS_AIC;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller */
+/* ***************************************************************************** */
+typedef struct _AT91S_AIC
+{
+    AT91_REG AIC_SMR[ 32 ];  /* Source Mode Register */
+    AT91_REG AIC_SVR[ 32 ];  /* Source Vector Register */
+    AT91_REG AIC_IVR;        /* IRQ Vector Register */
+    AT91_REG AIC_FVR;        /* FIQ Vector Register */
+    AT91_REG AIC_ISR;        /* Interrupt Status Register */
+    AT91_REG AIC_IPR;        /* Interrupt Pending Register */
+    AT91_REG AIC_IMR;        /* Interrupt Mask Register */
+    AT91_REG AIC_CISR;       /* Core Interrupt Status Register */
+    AT91_REG Reserved0[ 2 ]; /* */
+    AT91_REG AIC_IECR;       /* Interrupt Enable Command Register */
+    AT91_REG AIC_IDCR;       /* Interrupt Disable Command Register */
+    AT91_REG AIC_ICCR;       /* Interrupt Clear Command Register */
+    AT91_REG AIC_ISCR;       /* Interrupt Set Command Register */
+    AT91_REG AIC_EOICR;      /* End of Interrupt Command Register */
+    AT91_REG AIC_SPU;        /* Spurious Vector Register */
+    AT91_REG AIC_DCR;        /* Debug Control Register (Protect) */
+    AT91_REG Reserved1[ 1 ]; /* */
+    AT91_REG AIC_FFER;       /* Fast Forcing Enable Register */
+    AT91_REG AIC_FFDR;       /* Fast Forcing Disable Register */
+    AT91_REG AIC_FFSR;       /* Fast Forcing Status Register */
+} AT91S_AIC, * AT91PS_AIC;
 
-// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
-#define AT91C_AIC_PRIOR       ((unsigned int) 0x7 <<  0) // (AIC) Priority Level
-#define     AT91C_AIC_PRIOR_LOWEST               ((unsigned int) 0x0) // (AIC) Lowest priority level
-#define     AT91C_AIC_PRIOR_HIGHEST              ((unsigned int) 0x7) // (AIC) Highest priority level
-#define AT91C_AIC_SRCTYPE     ((unsigned int) 0x3 <<  5) // (AIC) Interrupt Source Type
-#define     AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE  ((unsigned int) 0x0 <<  5) // (AIC) Internal Sources Code Label Level Sensitive
-#define     AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED   ((unsigned int) 0x1 <<  5) // (AIC) Internal Sources Code Label Edge triggered
-#define     AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL       ((unsigned int) 0x2 <<  5) // (AIC) External Sources Code Label High-level Sensitive
-#define     AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE    ((unsigned int) 0x3 <<  5) // (AIC) External Sources Code Label Positive Edge triggered
-// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
-#define AT91C_AIC_NFIQ        ((unsigned int) 0x1 <<  0) // (AIC) NFIQ Status
-#define AT91C_AIC_NIRQ        ((unsigned int) 0x1 <<  1) // (AIC) NIRQ Status
-// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
-#define AT91C_AIC_DCR_PROT    ((unsigned int) 0x1 <<  0) // (AIC) Protection Mode
-#define AT91C_AIC_DCR_GMSK    ((unsigned int) 0x1 <<  1) // (AIC) General Mask
+/* -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- */
+#define AT91C_AIC_PRIOR                              ( ( unsigned int ) 0x7 << 0 ) /* (AIC) Priority Level */
+#define     AT91C_AIC_PRIOR_LOWEST                   ( ( unsigned int ) 0x0 )      /* (AIC) Lowest priority level */
+#define     AT91C_AIC_PRIOR_HIGHEST                  ( ( unsigned int ) 0x7 )      /* (AIC) Highest priority level */
+#define AT91C_AIC_SRCTYPE                            ( ( unsigned int ) 0x3 << 5 ) /* (AIC) Interrupt Source Type */
+#define     AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE    ( ( unsigned int ) 0x0 << 5 ) /* (AIC) Internal Sources Code Label Level Sensitive */
+#define     AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED     ( ( unsigned int ) 0x1 << 5 ) /* (AIC) Internal Sources Code Label Edge triggered */
+#define     AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL         ( ( unsigned int ) 0x2 << 5 ) /* (AIC) External Sources Code Label High-level Sensitive */
+#define     AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE      ( ( unsigned int ) 0x3 << 5 ) /* (AIC) External Sources Code Label Positive Edge triggered */
+/* -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- */
+#define AT91C_AIC_NFIQ                               ( ( unsigned int ) 0x1 << 0 ) /* (AIC) NFIQ Status */
+#define AT91C_AIC_NIRQ                               ( ( unsigned int ) 0x1 << 1 ) /* (AIC) NIRQ Status */
+/* -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- */
+#define AT91C_AIC_DCR_PROT                           ( ( unsigned int ) 0x1 << 0 ) /* (AIC) Protection Mode */
+#define AT91C_AIC_DCR_GMSK                           ( ( unsigned int ) 0x1 << 1 ) /* (AIC) General Mask */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Debug Unit
-// *****************************************************************************
-typedef struct _AT91S_DBGU {
-    AT91_REG     DBGU_CR;   // Control Register
-    AT91_REG     DBGU_MR;   // Mode Register
-    AT91_REG     DBGU_IER;  // Interrupt Enable Register
-    AT91_REG     DBGU_IDR;  // Interrupt Disable Register
-    AT91_REG     DBGU_IMR;  // Interrupt Mask Register
-    AT91_REG     DBGU_CSR;  // Channel Status Register
-    AT91_REG     DBGU_RHR;  // Receiver Holding Register
-    AT91_REG     DBGU_THR;  // Transmitter Holding Register
-    AT91_REG     DBGU_BRGR;     // Baud Rate Generator Register
-    AT91_REG     Reserved0[7];  //
-    AT91_REG     DBGU_C1R;  // Chip ID1 Register
-    AT91_REG     DBGU_C2R;  // Chip ID2 Register
-    AT91_REG     DBGU_FNTR;     // Force NTRST Register
-    AT91_REG     Reserved1[45];     //
-    AT91_REG     DBGU_RPR;  // Receive Pointer Register
-    AT91_REG     DBGU_RCR;  // Receive Counter Register
-    AT91_REG     DBGU_TPR;  // Transmit Pointer Register
-    AT91_REG     DBGU_TCR;  // Transmit Counter Register
-    AT91_REG     DBGU_RNPR;     // Receive Next Pointer Register
-    AT91_REG     DBGU_RNCR;     // Receive Next Counter Register
-    AT91_REG     DBGU_TNPR;     // Transmit Next Pointer Register
-    AT91_REG     DBGU_TNCR;     // Transmit Next Counter Register
-    AT91_REG     DBGU_PTCR;     // PDC Transfer Control Register
-    AT91_REG     DBGU_PTSR;     // PDC Transfer Status Register
-} AT91S_DBGU, *AT91PS_DBGU;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Debug Unit */
+/* ***************************************************************************** */
+typedef struct _AT91S_DBGU
+{
+    AT91_REG DBGU_CR;         /* Control Register */
+    AT91_REG DBGU_MR;         /* Mode Register */
+    AT91_REG DBGU_IER;        /* Interrupt Enable Register */
+    AT91_REG DBGU_IDR;        /* Interrupt Disable Register */
+    AT91_REG DBGU_IMR;        /* Interrupt Mask Register */
+    AT91_REG DBGU_CSR;        /* Channel Status Register */
+    AT91_REG DBGU_RHR;        /* Receiver Holding Register */
+    AT91_REG DBGU_THR;        /* Transmitter Holding Register */
+    AT91_REG DBGU_BRGR;       /* Baud Rate Generator Register */
+    AT91_REG Reserved0[ 7 ];  /* */
+    AT91_REG DBGU_C1R;        /* Chip ID1 Register */
+    AT91_REG DBGU_C2R;        /* Chip ID2 Register */
+    AT91_REG DBGU_FNTR;       /* Force NTRST Register */
+    AT91_REG Reserved1[ 45 ]; /* */
+    AT91_REG DBGU_RPR;        /* Receive Pointer Register */
+    AT91_REG DBGU_RCR;        /* Receive Counter Register */
+    AT91_REG DBGU_TPR;        /* Transmit Pointer Register */
+    AT91_REG DBGU_TCR;        /* Transmit Counter Register */
+    AT91_REG DBGU_RNPR;       /* Receive Next Pointer Register */
+    AT91_REG DBGU_RNCR;       /* Receive Next Counter Register */
+    AT91_REG DBGU_TNPR;       /* Transmit Next Pointer Register */
+    AT91_REG DBGU_TNCR;       /* Transmit Next Counter Register */
+    AT91_REG DBGU_PTCR;       /* PDC Transfer Control Register */
+    AT91_REG DBGU_PTSR;       /* PDC Transfer Status Register */
+} AT91S_DBGU, * AT91PS_DBGU;
 
-// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
-#define AT91C_US_RSTRX        ((unsigned int) 0x1 <<  2) // (DBGU) Reset Receiver
-#define AT91C_US_RSTTX        ((unsigned int) 0x1 <<  3) // (DBGU) Reset Transmitter
-#define AT91C_US_RXEN         ((unsigned int) 0x1 <<  4) // (DBGU) Receiver Enable
-#define AT91C_US_RXDIS        ((unsigned int) 0x1 <<  5) // (DBGU) Receiver Disable
-#define AT91C_US_TXEN         ((unsigned int) 0x1 <<  6) // (DBGU) Transmitter Enable
-#define AT91C_US_TXDIS        ((unsigned int) 0x1 <<  7) // (DBGU) Transmitter Disable
-// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
-#define AT91C_US_PAR          ((unsigned int) 0x7 <<  9) // (DBGU) Parity type
-#define     AT91C_US_PAR_EVEN                 ((unsigned int) 0x0 <<  9) // (DBGU) Even Parity
-#define     AT91C_US_PAR_ODD                  ((unsigned int) 0x1 <<  9) // (DBGU) Odd Parity
-#define     AT91C_US_PAR_SPACE                ((unsigned int) 0x2 <<  9) // (DBGU) Parity forced to 0 (Space)
-#define     AT91C_US_PAR_MARK                 ((unsigned int) 0x3 <<  9) // (DBGU) Parity forced to 1 (Mark)
-#define     AT91C_US_PAR_NONE                 ((unsigned int) 0x4 <<  9) // (DBGU) No Parity
-#define     AT91C_US_PAR_MULTI_DROP           ((unsigned int) 0x6 <<  9) // (DBGU) Multi-drop mode
-#define AT91C_US_CHMODE       ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode
-#define     AT91C_US_CHMODE_NORMAL               ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
-#define     AT91C_US_CHMODE_AUTO                 ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
-#define     AT91C_US_CHMODE_LOCAL                ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
-#define     AT91C_US_CHMODE_REMOTE               ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
-// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
-#define AT91C_US_RXRDY        ((unsigned int) 0x1 <<  0) // (DBGU) RXRDY Interrupt
-#define AT91C_US_TXRDY        ((unsigned int) 0x1 <<  1) // (DBGU) TXRDY Interrupt
-#define AT91C_US_ENDRX        ((unsigned int) 0x1 <<  3) // (DBGU) End of Receive Transfer Interrupt
-#define AT91C_US_ENDTX        ((unsigned int) 0x1 <<  4) // (DBGU) End of Transmit Interrupt
-#define AT91C_US_OVRE         ((unsigned int) 0x1 <<  5) // (DBGU) Overrun Interrupt
-#define AT91C_US_FRAME        ((unsigned int) 0x1 <<  6) // (DBGU) Framing Error Interrupt
-#define AT91C_US_PARE         ((unsigned int) 0x1 <<  7) // (DBGU) Parity Error Interrupt
-#define AT91C_US_TXEMPTY      ((unsigned int) 0x1 <<  9) // (DBGU) TXEMPTY Interrupt
-#define AT91C_US_TXBUFE       ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt
-#define AT91C_US_RXBUFF       ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt
-#define AT91C_US_COMM_TX      ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt
-#define AT91C_US_COMM_RX      ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt
-// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
-// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
-// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
-// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
-#define AT91C_US_FORCE_NTRST  ((unsigned int) 0x1 <<  0) // (DBGU) Force NTRST in JTAG
+/* -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- */
+#define AT91C_US_RSTRX                 ( ( unsigned int ) 0x1 << 2 )  /* (DBGU) Reset Receiver */
+#define AT91C_US_RSTTX                 ( ( unsigned int ) 0x1 << 3 )  /* (DBGU) Reset Transmitter */
+#define AT91C_US_RXEN                  ( ( unsigned int ) 0x1 << 4 )  /* (DBGU) Receiver Enable */
+#define AT91C_US_RXDIS                 ( ( unsigned int ) 0x1 << 5 )  /* (DBGU) Receiver Disable */
+#define AT91C_US_TXEN                  ( ( unsigned int ) 0x1 << 6 )  /* (DBGU) Transmitter Enable */
+#define AT91C_US_TXDIS                 ( ( unsigned int ) 0x1 << 7 )  /* (DBGU) Transmitter Disable */
+/* -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- */
+#define AT91C_US_PAR                   ( ( unsigned int ) 0x7 << 9 )  /* (DBGU) Parity type */
+#define     AT91C_US_PAR_EVEN          ( ( unsigned int ) 0x0 << 9 )  /* (DBGU) Even Parity */
+#define     AT91C_US_PAR_ODD           ( ( unsigned int ) 0x1 << 9 )  /* (DBGU) Odd Parity */
+#define     AT91C_US_PAR_SPACE         ( ( unsigned int ) 0x2 << 9 )  /* (DBGU) Parity forced to 0 (Space) */
+#define     AT91C_US_PAR_MARK          ( ( unsigned int ) 0x3 << 9 )  /* (DBGU) Parity forced to 1 (Mark) */
+#define     AT91C_US_PAR_NONE          ( ( unsigned int ) 0x4 << 9 )  /* (DBGU) No Parity */
+#define     AT91C_US_PAR_MULTI_DROP    ( ( unsigned int ) 0x6 << 9 )  /* (DBGU) Multi-drop mode */
+#define AT91C_US_CHMODE                ( ( unsigned int ) 0x3 << 14 ) /* (DBGU) Channel Mode */
+#define     AT91C_US_CHMODE_NORMAL     ( ( unsigned int ) 0x0 << 14 ) /* (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. */
+#define     AT91C_US_CHMODE_AUTO       ( ( unsigned int ) 0x1 << 14 ) /* (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. */
+#define     AT91C_US_CHMODE_LOCAL      ( ( unsigned int ) 0x2 << 14 ) /* (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. */
+#define     AT91C_US_CHMODE_REMOTE     ( ( unsigned int ) 0x3 << 14 ) /* (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. */
+/* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */
+#define AT91C_US_RXRDY                 ( ( unsigned int ) 0x1 << 0 )  /* (DBGU) RXRDY Interrupt */
+#define AT91C_US_TXRDY                 ( ( unsigned int ) 0x1 << 1 )  /* (DBGU) TXRDY Interrupt */
+#define AT91C_US_ENDRX                 ( ( unsigned int ) 0x1 << 3 )  /* (DBGU) End of Receive Transfer Interrupt */
+#define AT91C_US_ENDTX                 ( ( unsigned int ) 0x1 << 4 )  /* (DBGU) End of Transmit Interrupt */
+#define AT91C_US_OVRE                  ( ( unsigned int ) 0x1 << 5 )  /* (DBGU) Overrun Interrupt */
+#define AT91C_US_FRAME                 ( ( unsigned int ) 0x1 << 6 )  /* (DBGU) Framing Error Interrupt */
+#define AT91C_US_PARE                  ( ( unsigned int ) 0x1 << 7 )  /* (DBGU) Parity Error Interrupt */
+#define AT91C_US_TXEMPTY               ( ( unsigned int ) 0x1 << 9 )  /* (DBGU) TXEMPTY Interrupt */
+#define AT91C_US_TXBUFE                ( ( unsigned int ) 0x1 << 11 ) /* (DBGU) TXBUFE Interrupt */
+#define AT91C_US_RXBUFF                ( ( unsigned int ) 0x1 << 12 ) /* (DBGU) RXBUFF Interrupt */
+#define AT91C_US_COMM_TX               ( ( unsigned int ) 0x1 << 30 ) /* (DBGU) COMM_TX Interrupt */
+#define AT91C_US_COMM_RX               ( ( unsigned int ) 0x1 << 31 ) /* (DBGU) COMM_RX Interrupt */
+/* -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- */
+/* -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- */
+/* -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- */
+/* -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- */
+#define AT91C_US_FORCE_NTRST    ( ( unsigned int ) 0x1 << 0 ) /* (DBGU) Force NTRST in JTAG */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Peripheral Data Controller
-// *****************************************************************************
-typedef struct _AT91S_PDC {
-    AT91_REG     PDC_RPR;   // Receive Pointer Register
-    AT91_REG     PDC_RCR;   // Receive Counter Register
-    AT91_REG     PDC_TPR;   // Transmit Pointer Register
-    AT91_REG     PDC_TCR;   // Transmit Counter Register
-    AT91_REG     PDC_RNPR;  // Receive Next Pointer Register
-    AT91_REG     PDC_RNCR;  // Receive Next Counter Register
-    AT91_REG     PDC_TNPR;  // Transmit Next Pointer Register
-    AT91_REG     PDC_TNCR;  // Transmit Next Counter Register
-    AT91_REG     PDC_PTCR;  // PDC Transfer Control Register
-    AT91_REG     PDC_PTSR;  // PDC Transfer Status Register
-} AT91S_PDC, *AT91PS_PDC;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Peripheral Data Controller */
+/* ***************************************************************************** */
+typedef struct _AT91S_PDC
+{
+    AT91_REG PDC_RPR;  /* Receive Pointer Register */
+    AT91_REG PDC_RCR;  /* Receive Counter Register */
+    AT91_REG PDC_TPR;  /* Transmit Pointer Register */
+    AT91_REG PDC_TCR;  /* Transmit Counter Register */
+    AT91_REG PDC_RNPR; /* Receive Next Pointer Register */
+    AT91_REG PDC_RNCR; /* Receive Next Counter Register */
+    AT91_REG PDC_TNPR; /* Transmit Next Pointer Register */
+    AT91_REG PDC_TNCR; /* Transmit Next Counter Register */
+    AT91_REG PDC_PTCR; /* PDC Transfer Control Register */
+    AT91_REG PDC_PTSR; /* PDC Transfer Status Register */
+} AT91S_PDC, * AT91PS_PDC;
 
-// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
-#define AT91C_PDC_RXTEN       ((unsigned int) 0x1 <<  0) // (PDC) Receiver Transfer Enable
-#define AT91C_PDC_RXTDIS      ((unsigned int) 0x1 <<  1) // (PDC) Receiver Transfer Disable
-#define AT91C_PDC_TXTEN       ((unsigned int) 0x1 <<  8) // (PDC) Transmitter Transfer Enable
-#define AT91C_PDC_TXTDIS      ((unsigned int) 0x1 <<  9) // (PDC) Transmitter Transfer Disable
-// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
+/* -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */
+#define AT91C_PDC_RXTEN     ( ( unsigned int ) 0x1 << 0 ) /* (PDC) Receiver Transfer Enable */
+#define AT91C_PDC_RXTDIS    ( ( unsigned int ) 0x1 << 1 ) /* (PDC) Receiver Transfer Disable */
+#define AT91C_PDC_TXTEN     ( ( unsigned int ) 0x1 << 8 ) /* (PDC) Transmitter Transfer Enable */
+#define AT91C_PDC_TXTDIS    ( ( unsigned int ) 0x1 << 9 ) /* (PDC) Transmitter Transfer Disable */
+/* -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
-// *****************************************************************************
-typedef struct _AT91S_PIO {
-    AT91_REG     PIO_PER;   // PIO Enable Register
-    AT91_REG     PIO_PDR;   // PIO Disable Register
-    AT91_REG     PIO_PSR;   // PIO Status Register
-    AT91_REG     Reserved0[1];  //
-    AT91_REG     PIO_OER;   // Output Enable Register
-    AT91_REG     PIO_ODR;   // Output Disable Registerr
-    AT91_REG     PIO_OSR;   // Output Status Register
-    AT91_REG     Reserved1[1];  //
-    AT91_REG     PIO_IFER;  // Input Filter Enable Register
-    AT91_REG     PIO_IFDR;  // Input Filter Disable Register
-    AT91_REG     PIO_IFSR;  // Input Filter Status Register
-    AT91_REG     Reserved2[1];  //
-    AT91_REG     PIO_SODR;  // Set Output Data Register
-    AT91_REG     PIO_CODR;  // Clear Output Data Register
-    AT91_REG     PIO_ODSR;  // Output Data Status Register
-    AT91_REG     PIO_PDSR;  // Pin Data Status Register
-    AT91_REG     PIO_IER;   // Interrupt Enable Register
-    AT91_REG     PIO_IDR;   // Interrupt Disable Register
-    AT91_REG     PIO_IMR;   // Interrupt Mask Register
-    AT91_REG     PIO_ISR;   // Interrupt Status Register
-    AT91_REG     PIO_MDER;  // Multi-driver Enable Register
-    AT91_REG     PIO_MDDR;  // Multi-driver Disable Register
-    AT91_REG     PIO_MDSR;  // Multi-driver Status Register
-    AT91_REG     Reserved3[1];  //
-    AT91_REG     PIO_PPUDR;     // Pull-up Disable Register
-    AT91_REG     PIO_PPUER;     // Pull-up Enable Register
-    AT91_REG     PIO_PPUSR;     // Pad Pull-up Status Register
-    AT91_REG     Reserved4[1];  //
-    AT91_REG     PIO_ASR;   // Select A Register
-    AT91_REG     PIO_BSR;   // Select B Register
-    AT91_REG     PIO_ABSR;  // AB Select Status Register
-    AT91_REG     Reserved5[9];  //
-    AT91_REG     PIO_OWER;  // Output Write Enable Register
-    AT91_REG     PIO_OWDR;  // Output Write Disable Register
-    AT91_REG     PIO_OWSR;  // Output Write Status Register
-} AT91S_PIO, *AT91PS_PIO;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Parallel Input Output Controller */
+/* ***************************************************************************** */
+typedef struct _AT91S_PIO
+{
+    AT91_REG PIO_PER;        /* PIO Enable Register */
+    AT91_REG PIO_PDR;        /* PIO Disable Register */
+    AT91_REG PIO_PSR;        /* PIO Status Register */
+    AT91_REG Reserved0[ 1 ]; /* */
+    AT91_REG PIO_OER;        /* Output Enable Register */
+    AT91_REG PIO_ODR;        /* Output Disable Registerr */
+    AT91_REG PIO_OSR;        /* Output Status Register */
+    AT91_REG Reserved1[ 1 ]; /* */
+    AT91_REG PIO_IFER;       /* Input Filter Enable Register */
+    AT91_REG PIO_IFDR;       /* Input Filter Disable Register */
+    AT91_REG PIO_IFSR;       /* Input Filter Status Register */
+    AT91_REG Reserved2[ 1 ]; /* */
+    AT91_REG PIO_SODR;       /* Set Output Data Register */
+    AT91_REG PIO_CODR;       /* Clear Output Data Register */
+    AT91_REG PIO_ODSR;       /* Output Data Status Register */
+    AT91_REG PIO_PDSR;       /* Pin Data Status Register */
+    AT91_REG PIO_IER;        /* Interrupt Enable Register */
+    AT91_REG PIO_IDR;        /* Interrupt Disable Register */
+    AT91_REG PIO_IMR;        /* Interrupt Mask Register */
+    AT91_REG PIO_ISR;        /* Interrupt Status Register */
+    AT91_REG PIO_MDER;       /* Multi-driver Enable Register */
+    AT91_REG PIO_MDDR;       /* Multi-driver Disable Register */
+    AT91_REG PIO_MDSR;       /* Multi-driver Status Register */
+    AT91_REG Reserved3[ 1 ]; /* */
+    AT91_REG PIO_PPUDR;      /* Pull-up Disable Register */
+    AT91_REG PIO_PPUER;      /* Pull-up Enable Register */
+    AT91_REG PIO_PPUSR;      /* Pad Pull-up Status Register */
+    AT91_REG Reserved4[ 1 ]; /* */
+    AT91_REG PIO_ASR;        /* Select A Register */
+    AT91_REG PIO_BSR;        /* Select B Register */
+    AT91_REG PIO_ABSR;       /* AB Select Status Register */
+    AT91_REG Reserved5[ 9 ]; /* */
+    AT91_REG PIO_OWER;       /* Output Write Enable Register */
+    AT91_REG PIO_OWDR;       /* Output Write Disable Register */
+    AT91_REG PIO_OWSR;       /* Output Write Status Register */
+} AT91S_PIO, * AT91PS_PIO;
 
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Clock Generator Controler
-// *****************************************************************************
-typedef struct _AT91S_CKGR {
-    AT91_REG     CKGR_MOR;  // Main Oscillator Register
-    AT91_REG     CKGR_MCFR;     // Main Clock  Frequency Register
-    AT91_REG     Reserved0[1];  //
-    AT91_REG     CKGR_PLLR;     // PLL Register
-} AT91S_CKGR, *AT91PS_CKGR;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Clock Generator Controller */
+/* ***************************************************************************** */
+typedef struct _AT91S_CKGR
+{
+    AT91_REG CKGR_MOR;       /* Main Oscillator Register */
+    AT91_REG CKGR_MCFR;      /* Main Clock  Frequency Register */
+    AT91_REG Reserved0[ 1 ]; /* */
+    AT91_REG CKGR_PLLR;      /* PLL Register */
+} AT91S_CKGR, * AT91PS_CKGR;
 
-// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
-#define AT91C_CKGR_MOSCEN     ((unsigned int) 0x1 <<  0) // (CKGR) Main Oscillator Enable
-#define AT91C_CKGR_OSCBYPASS  ((unsigned int) 0x1 <<  1) // (CKGR) Main Oscillator Bypass
-#define AT91C_CKGR_OSCOUNT    ((unsigned int) 0xFF <<  8) // (CKGR) Main Oscillator Start-up Time
-// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
-#define AT91C_CKGR_MAINF      ((unsigned int) 0xFFFF <<  0) // (CKGR) Main Clock Frequency
-#define AT91C_CKGR_MAINRDY    ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready
-// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
-#define AT91C_CKGR_DIV        ((unsigned int) 0xFF <<  0) // (CKGR) Divider Selected
-#define     AT91C_CKGR_DIV_0                    ((unsigned int) 0x0) // (CKGR) Divider output is 0
-#define     AT91C_CKGR_DIV_BYPASS               ((unsigned int) 0x1) // (CKGR) Divider is bypassed
-#define AT91C_CKGR_PLLCOUNT   ((unsigned int) 0x3F <<  8) // (CKGR) PLL Counter
-#define AT91C_CKGR_OUT        ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range
-#define     AT91C_CKGR_OUT_0                    ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet
-#define     AT91C_CKGR_OUT_1                    ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet
-#define     AT91C_CKGR_OUT_2                    ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet
-#define     AT91C_CKGR_OUT_3                    ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_MUL        ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier
-#define AT91C_CKGR_USBDIV     ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks
-#define     AT91C_CKGR_USBDIV_0                    ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output
-#define     AT91C_CKGR_USBDIV_1                    ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
-#define     AT91C_CKGR_USBDIV_2                    ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
+/* -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */
+#define AT91C_CKGR_MOSCEN            ( ( unsigned int ) 0x1 << 0 )    /* (CKGR) Main Oscillator Enable */
+#define AT91C_CKGR_OSCBYPASS         ( ( unsigned int ) 0x1 << 1 )    /* (CKGR) Main Oscillator Bypass */
+#define AT91C_CKGR_OSCOUNT           ( ( unsigned int ) 0xFF << 8 )   /* (CKGR) Main Oscillator Start-up Time */
+/* -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- */
+#define AT91C_CKGR_MAINF             ( ( unsigned int ) 0xFFFF << 0 ) /* (CKGR) Main Clock Frequency */
+#define AT91C_CKGR_MAINRDY           ( ( unsigned int ) 0x1 << 16 )   /* (CKGR) Main Clock Ready */
+/* -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- */
+#define AT91C_CKGR_DIV               ( ( unsigned int ) 0xFF << 0 )   /* (CKGR) Divider Selected */
+#define     AT91C_CKGR_DIV_0         ( ( unsigned int ) 0x0 )         /* (CKGR) Divider output is 0 */
+#define     AT91C_CKGR_DIV_BYPASS    ( ( unsigned int ) 0x1 )         /* (CKGR) Divider is bypassed */
+#define AT91C_CKGR_PLLCOUNT          ( ( unsigned int ) 0x3F << 8 )   /* (CKGR) PLL Counter */
+#define AT91C_CKGR_OUT               ( ( unsigned int ) 0x3 << 14 )   /* (CKGR) PLL Output Frequency Range */
+#define     AT91C_CKGR_OUT_0         ( ( unsigned int ) 0x0 << 14 )   /* (CKGR) Please refer to the PLL datasheet */
+#define     AT91C_CKGR_OUT_1         ( ( unsigned int ) 0x1 << 14 )   /* (CKGR) Please refer to the PLL datasheet */
+#define     AT91C_CKGR_OUT_2         ( ( unsigned int ) 0x2 << 14 )   /* (CKGR) Please refer to the PLL datasheet */
+#define     AT91C_CKGR_OUT_3         ( ( unsigned int ) 0x3 << 14 )   /* (CKGR) Please refer to the PLL datasheet */
+#define AT91C_CKGR_MUL               ( ( unsigned int ) 0x7FF << 16 ) /* (CKGR) PLL Multiplier */
+#define AT91C_CKGR_USBDIV            ( ( unsigned int ) 0x3 << 28 )   /* (CKGR) Divider for USB Clocks */
+#define     AT91C_CKGR_USBDIV_0      ( ( unsigned int ) 0x0 << 28 )   /* (CKGR) Divider output is PLL clock output */
+#define     AT91C_CKGR_USBDIV_1      ( ( unsigned int ) 0x1 << 28 )   /* (CKGR) Divider output is PLL clock output divided by 2 */
+#define     AT91C_CKGR_USBDIV_2      ( ( unsigned int ) 0x2 << 28 )   /* (CKGR) Divider output is PLL clock output divided by 4 */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Power Management Controler
-// *****************************************************************************
-typedef struct _AT91S_PMC {
-    AT91_REG     PMC_SCER;  // System Clock Enable Register
-    AT91_REG     PMC_SCDR;  // System Clock Disable Register
-    AT91_REG     PMC_SCSR;  // System Clock Status Register
-    AT91_REG     Reserved0[1];  //
-    AT91_REG     PMC_PCER;  // Peripheral Clock Enable Register
-    AT91_REG     PMC_PCDR;  // Peripheral Clock Disable Register
-    AT91_REG     PMC_PCSR;  // Peripheral Clock Status Register
-    AT91_REG     Reserved1[1];  //
-    AT91_REG     PMC_MOR;   // Main Oscillator Register
-    AT91_REG     PMC_MCFR;  // Main Clock  Frequency Register
-    AT91_REG     Reserved2[1];  //
-    AT91_REG     PMC_PLLR;  // PLL Register
-    AT91_REG     PMC_MCKR;  // Master Clock Register
-    AT91_REG     Reserved3[3];  //
-    AT91_REG     PMC_PCKR[8];   // Programmable Clock Register
-    AT91_REG     PMC_IER;   // Interrupt Enable Register
-    AT91_REG     PMC_IDR;   // Interrupt Disable Register
-    AT91_REG     PMC_SR;    // Status Register
-    AT91_REG     PMC_IMR;   // Interrupt Mask Register
-} AT91S_PMC, *AT91PS_PMC;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Power Management Controller */
+/* ***************************************************************************** */
+typedef struct _AT91S_PMC
+{
+    AT91_REG PMC_SCER;       /* System Clock Enable Register */
+    AT91_REG PMC_SCDR;       /* System Clock Disable Register */
+    AT91_REG PMC_SCSR;       /* System Clock Status Register */
+    AT91_REG Reserved0[ 1 ]; /* */
+    AT91_REG PMC_PCER;       /* Peripheral Clock Enable Register */
+    AT91_REG PMC_PCDR;       /* Peripheral Clock Disable Register */
+    AT91_REG PMC_PCSR;       /* Peripheral Clock Status Register */
+    AT91_REG Reserved1[ 1 ]; /* */
+    AT91_REG PMC_MOR;        /* Main Oscillator Register */
+    AT91_REG PMC_MCFR;       /* Main Clock  Frequency Register */
+    AT91_REG Reserved2[ 1 ]; /* */
+    AT91_REG PMC_PLLR;       /* PLL Register */
+    AT91_REG PMC_MCKR;       /* Master Clock Register */
+    AT91_REG Reserved3[ 3 ]; /* */
+    AT91_REG PMC_PCKR[ 8 ];  /* Programmable Clock Register */
+    AT91_REG PMC_IER;        /* Interrupt Enable Register */
+    AT91_REG PMC_IDR;        /* Interrupt Disable Register */
+    AT91_REG PMC_SR;         /* Status Register */
+    AT91_REG PMC_IMR;        /* Interrupt Mask Register */
+} AT91S_PMC, * AT91PS_PMC;
 
-// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
-#define AT91C_PMC_PCK         ((unsigned int) 0x1 <<  0) // (PMC) Processor Clock
-#define AT91C_PMC_UDP         ((unsigned int) 0x1 <<  7) // (PMC) USB Device Port Clock
-#define AT91C_PMC_PCK0        ((unsigned int) 0x1 <<  8) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK1        ((unsigned int) 0x1 <<  9) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK2        ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK3        ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output
-// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
-// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
-// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
-// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
-// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
-// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
-#define AT91C_PMC_CSS         ((unsigned int) 0x3 <<  0) // (PMC) Programmable Clock Selection
-#define     AT91C_PMC_CSS_SLOW_CLK             ((unsigned int) 0x0) // (PMC) Slow Clock is selected
-#define     AT91C_PMC_CSS_MAIN_CLK             ((unsigned int) 0x1) // (PMC) Main Clock is selected
-#define     AT91C_PMC_CSS_PLL_CLK              ((unsigned int) 0x3) // (PMC) Clock from PLL is selected
-#define AT91C_PMC_PRES        ((unsigned int) 0x7 <<  2) // (PMC) Programmable Clock Prescaler
-#define     AT91C_PMC_PRES_CLK                  ((unsigned int) 0x0 <<  2) // (PMC) Selected clock
-#define     AT91C_PMC_PRES_CLK_2                ((unsigned int) 0x1 <<  2) // (PMC) Selected clock divided by 2
-#define     AT91C_PMC_PRES_CLK_4                ((unsigned int) 0x2 <<  2) // (PMC) Selected clock divided by 4
-#define     AT91C_PMC_PRES_CLK_8                ((unsigned int) 0x3 <<  2) // (PMC) Selected clock divided by 8
-#define     AT91C_PMC_PRES_CLK_16               ((unsigned int) 0x4 <<  2) // (PMC) Selected clock divided by 16
-#define     AT91C_PMC_PRES_CLK_32               ((unsigned int) 0x5 <<  2) // (PMC) Selected clock divided by 32
-#define     AT91C_PMC_PRES_CLK_64               ((unsigned int) 0x6 <<  2) // (PMC) Selected clock divided by 64
-// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
-// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
-#define AT91C_PMC_MOSCS       ((unsigned int) 0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask
-#define AT91C_PMC_LOCK        ((unsigned int) 0x1 <<  2) // (PMC) PLL Status/Enable/Disable/Mask
-#define AT91C_PMC_MCKRDY      ((unsigned int) 0x1 <<  3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK0RDY     ((unsigned int) 0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK1RDY     ((unsigned int) 0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK2RDY     ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK3RDY     ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
-// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
-// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
-// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
+/* -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- */
+#define AT91C_PMC_PCK     ( ( unsigned int ) 0x1 << 0 )  /* (PMC) Processor Clock */
+#define AT91C_PMC_UDP     ( ( unsigned int ) 0x1 << 7 )  /* (PMC) USB Device Port Clock */
+#define AT91C_PMC_PCK0    ( ( unsigned int ) 0x1 << 8 )  /* (PMC) Programmable Clock Output */
+#define AT91C_PMC_PCK1    ( ( unsigned int ) 0x1 << 9 )  /* (PMC) Programmable Clock Output */
+#define AT91C_PMC_PCK2    ( ( unsigned int ) 0x1 << 10 ) /* (PMC) Programmable Clock Output */
+#define AT91C_PMC_PCK3    ( ( unsigned int ) 0x1 << 11 ) /* (PMC) Programmable Clock Output */
+/* -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- */
+/* -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- */
+/* -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- */
+/* -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- */
+/* -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- */
+/* -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- */
+#define AT91C_PMC_CSS                 ( ( unsigned int ) 0x3 << 0 ) /* (PMC) Programmable Clock Selection */
+#define     AT91C_PMC_CSS_SLOW_CLK    ( ( unsigned int ) 0x0 )      /* (PMC) Slow Clock is selected */
+#define     AT91C_PMC_CSS_MAIN_CLK    ( ( unsigned int ) 0x1 )      /* (PMC) Main Clock is selected */
+#define     AT91C_PMC_CSS_PLL_CLK     ( ( unsigned int ) 0x3 )      /* (PMC) Clock from PLL is selected */
+#define AT91C_PMC_PRES                ( ( unsigned int ) 0x7 << 2 ) /* (PMC) Programmable Clock Prescaler */
+#define     AT91C_PMC_PRES_CLK        ( ( unsigned int ) 0x0 << 2 ) /* (PMC) Selected clock */
+#define     AT91C_PMC_PRES_CLK_2      ( ( unsigned int ) 0x1 << 2 ) /* (PMC) Selected clock divided by 2 */
+#define     AT91C_PMC_PRES_CLK_4      ( ( unsigned int ) 0x2 << 2 ) /* (PMC) Selected clock divided by 4 */
+#define     AT91C_PMC_PRES_CLK_8      ( ( unsigned int ) 0x3 << 2 ) /* (PMC) Selected clock divided by 8 */
+#define     AT91C_PMC_PRES_CLK_16     ( ( unsigned int ) 0x4 << 2 ) /* (PMC) Selected clock divided by 16 */
+#define     AT91C_PMC_PRES_CLK_32     ( ( unsigned int ) 0x5 << 2 ) /* (PMC) Selected clock divided by 32 */
+#define     AT91C_PMC_PRES_CLK_64     ( ( unsigned int ) 0x6 << 2 ) /* (PMC) Selected clock divided by 64 */
+/* -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- */
+/* -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- */
+#define AT91C_PMC_MOSCS               ( ( unsigned int ) 0x1 << 0 )  /* (PMC) MOSC Status/Enable/Disable/Mask */
+#define AT91C_PMC_LOCK                ( ( unsigned int ) 0x1 << 2 )  /* (PMC) PLL Status/Enable/Disable/Mask */
+#define AT91C_PMC_MCKRDY              ( ( unsigned int ) 0x1 << 3 )  /* (PMC) MCK_RDY Status/Enable/Disable/Mask */
+#define AT91C_PMC_PCK0RDY             ( ( unsigned int ) 0x1 << 8 )  /* (PMC) PCK0_RDY Status/Enable/Disable/Mask */
+#define AT91C_PMC_PCK1RDY             ( ( unsigned int ) 0x1 << 9 )  /* (PMC) PCK1_RDY Status/Enable/Disable/Mask */
+#define AT91C_PMC_PCK2RDY             ( ( unsigned int ) 0x1 << 10 ) /* (PMC) PCK2_RDY Status/Enable/Disable/Mask */
+#define AT91C_PMC_PCK3RDY             ( ( unsigned int ) 0x1 << 11 ) /* (PMC) PCK3_RDY Status/Enable/Disable/Mask */
+/* -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- */
+/* -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- */
+/* -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Reset Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_RSTC {
-    AT91_REG     RSTC_RCR;  // Reset Control Register
-    AT91_REG     RSTC_RSR;  // Reset Status Register
-    AT91_REG     RSTC_RMR;  // Reset Mode Register
-} AT91S_RSTC, *AT91PS_RSTC;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Reset Controller Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_RSTC
+{
+    AT91_REG RSTC_RCR; /* Reset Control Register */
+    AT91_REG RSTC_RSR; /* Reset Status Register */
+    AT91_REG RSTC_RMR; /* Reset Mode Register */
+} AT91S_RSTC, * AT91PS_RSTC;
 
-// -------- SYSC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
-#define AT91C_SYSC_PROCRST    ((unsigned int) 0x1 <<  0) // (RSTC) Processor Reset
-#define AT91C_SYSC_ICERST     ((unsigned int) 0x1 <<  1) // (RSTC) ICE Interface Reset
-#define AT91C_SYSC_PERRST     ((unsigned int) 0x1 <<  2) // (RSTC) Peripheral Reset
-#define AT91C_SYSC_EXTRST     ((unsigned int) 0x1 <<  3) // (RSTC) External Reset
-#define AT91C_SYSC_KEY        ((unsigned int) 0xFF << 24) // (RSTC) Password
-// -------- SYSC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
-#define AT91C_SYSC_URSTS      ((unsigned int) 0x1 <<  0) // (RSTC) User Reset Status
-#define AT91C_SYSC_BODSTS     ((unsigned int) 0x1 <<  1) // (RSTC) Brown-out Detection Status
-#define AT91C_SYSC_RSTTYP     ((unsigned int) 0x7 <<  8) // (RSTC) Reset Type
-#define     AT91C_SYSC_RSTTYP_POWERUP              ((unsigned int) 0x0 <<  8) // (RSTC) Power-up Reset. VDDCORE rising.
-#define     AT91C_SYSC_RSTTYP_WATCHDOG             ((unsigned int) 0x2 <<  8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
-#define     AT91C_SYSC_RSTTYP_SOFTWARE             ((unsigned int) 0x3 <<  8) // (RSTC) Software Reset. Processor reset required by the software.
-#define     AT91C_SYSC_RSTTYP_USER                 ((unsigned int) 0x4 <<  8) // (RSTC) User Reset. NRST pin detected low.
-#define     AT91C_SYSC_RSTTYP_BROWNOUT             ((unsigned int) 0x5 <<  8) // (RSTC) Brown-out Reset.
-#define AT91C_SYSC_NRSTL      ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level
-#define AT91C_SYSC_SRCMP      ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress.
-// -------- SYSC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
-#define AT91C_SYSC_URSTEN     ((unsigned int) 0x1 <<  0) // (RSTC) User Reset Enable
-#define AT91C_SYSC_URSTIEN    ((unsigned int) 0x1 <<  4) // (RSTC) User Reset Interrupt Enable
-#define AT91C_SYSC_ERSTL      ((unsigned int) 0xF <<  8) // (RSTC) User Reset Enable
-#define AT91C_SYSC_BODIEN     ((unsigned int) 0x1 << 16) // (RSTC) Brown-out Detection Interrupt Enable
+/* -------- SYSC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- */
+#define AT91C_SYSC_PROCRST                ( ( unsigned int ) 0x1 << 0 )   /* (RSTC) Processor Reset */
+#define AT91C_SYSC_ICERST                 ( ( unsigned int ) 0x1 << 1 )   /* (RSTC) ICE Interface Reset */
+#define AT91C_SYSC_PERRST                 ( ( unsigned int ) 0x1 << 2 )   /* (RSTC) Peripheral Reset */
+#define AT91C_SYSC_EXTRST                 ( ( unsigned int ) 0x1 << 3 )   /* (RSTC) External Reset */
+#define AT91C_SYSC_KEY                    ( ( unsigned int ) 0xFF << 24 ) /* (RSTC) Password */
+/* -------- SYSC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- */
+#define AT91C_SYSC_URSTS                  ( ( unsigned int ) 0x1 << 0 )   /* (RSTC) User Reset Status */
+#define AT91C_SYSC_BODSTS                 ( ( unsigned int ) 0x1 << 1 )   /* (RSTC) Brown-out Detection Status */
+#define AT91C_SYSC_RSTTYP                 ( ( unsigned int ) 0x7 << 8 )   /* (RSTC) Reset Type */
+#define     AT91C_SYSC_RSTTYP_POWERUP     ( ( unsigned int ) 0x0 << 8 )   /* (RSTC) Power-up Reset. VDDCORE rising. */
+#define     AT91C_SYSC_RSTTYP_WATCHDOG    ( ( unsigned int ) 0x2 << 8 )   /* (RSTC) Watchdog Reset. Watchdog overflow occurred. */
+#define     AT91C_SYSC_RSTTYP_SOFTWARE    ( ( unsigned int ) 0x3 << 8 )   /* (RSTC) Software Reset. Processor reset required by the software. */
+#define     AT91C_SYSC_RSTTYP_USER        ( ( unsigned int ) 0x4 << 8 )   /* (RSTC) User Reset. NRST pin detected low. */
+#define     AT91C_SYSC_RSTTYP_BROWNOUT    ( ( unsigned int ) 0x5 << 8 )   /* (RSTC) Brown-out Reset. */
+#define AT91C_SYSC_NRSTL                  ( ( unsigned int ) 0x1 << 16 )  /* (RSTC) NRST pin level */
+#define AT91C_SYSC_SRCMP                  ( ( unsigned int ) 0x1 << 17 )  /* (RSTC) Software Reset Command in Progress. */
+/* -------- SYSC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- */
+#define AT91C_SYSC_URSTEN                 ( ( unsigned int ) 0x1 << 0 )   /* (RSTC) User Reset Enable */
+#define AT91C_SYSC_URSTIEN                ( ( unsigned int ) 0x1 << 4 )   /* (RSTC) User Reset Interrupt Enable */
+#define AT91C_SYSC_ERSTL                  ( ( unsigned int ) 0xF << 8 )   /* (RSTC) User Reset Enable */
+#define AT91C_SYSC_BODIEN                 ( ( unsigned int ) 0x1 << 16 )  /* (RSTC) Brown-out Detection Interrupt Enable */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_RTTC {
-    AT91_REG     RTTC_RTMR;     // Real-time Mode Register
-    AT91_REG     RTTC_RTAR;     // Real-time Alarm Register
-    AT91_REG     RTTC_RTVR;     // Real-time Value Register
-    AT91_REG     RTTC_RTSR;     // Real-time Status Register
-} AT91S_RTTC, *AT91PS_RTTC;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_RTTC
+{
+    AT91_REG RTTC_RTMR; /* Real-time Mode Register */
+    AT91_REG RTTC_RTAR; /* Real-time Alarm Register */
+    AT91_REG RTTC_RTVR; /* Real-time Value Register */
+    AT91_REG RTTC_RTSR; /* Real-time Status Register */
+} AT91S_RTTC, * AT91PS_RTTC;
 
-// -------- SYSC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
-#define AT91C_SYSC_RTPRES     ((unsigned int) 0xFFFF <<  0) // (RTTC) Real-time Timer Prescaler Value
-#define AT91C_SYSC_ALMIEN     ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable
-#define AT91C_SYSC_RTTINCIEN  ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
-#define AT91C_SYSC_RTTRST     ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart
-// -------- SYSC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
-#define AT91C_SYSC_ALMV       ((unsigned int) 0x0 <<  0) // (RTTC) Alarm Value
-// -------- SYSC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
-#define AT91C_SYSC_CRTV       ((unsigned int) 0x0 <<  0) // (RTTC) Current Real-time Value
-// -------- SYSC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
-#define AT91C_SYSC_ALMS       ((unsigned int) 0x1 <<  0) // (RTTC) Real-time Alarm Status
-#define AT91C_SYSC_RTTINC     ((unsigned int) 0x1 <<  1) // (RTTC) Real-time Timer Increment
+/* -------- SYSC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- */
+#define AT91C_SYSC_RTPRES       ( ( unsigned int ) 0xFFFF << 0 ) /* (RTTC) Real-time Timer Prescaler Value */
+#define AT91C_SYSC_ALMIEN       ( ( unsigned int ) 0x1 << 16 )   /* (RTTC) Alarm Interrupt Enable */
+#define AT91C_SYSC_RTTINCIEN    ( ( unsigned int ) 0x1 << 17 )   /* (RTTC) Real Time Timer Increment Interrupt Enable */
+#define AT91C_SYSC_RTTRST       ( ( unsigned int ) 0x1 << 18 )   /* (RTTC) Real Time Timer Restart */
+/* -------- SYSC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- */
+#define AT91C_SYSC_ALMV         ( ( unsigned int ) 0x0 << 0 )    /* (RTTC) Alarm Value */
+/* -------- SYSC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- */
+#define AT91C_SYSC_CRTV         ( ( unsigned int ) 0x0 << 0 )    /* (RTTC) Current Real-time Value */
+/* -------- SYSC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- */
+#define AT91C_SYSC_ALMS         ( ( unsigned int ) 0x1 << 0 )    /* (RTTC) Real-time Alarm Status */
+#define AT91C_SYSC_RTTINC       ( ( unsigned int ) 0x1 << 1 )    /* (RTTC) Real-time Timer Increment */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_PITC {
-    AT91_REG     PITC_PIMR;     // Period Interval Mode Register
-    AT91_REG     PITC_PISR;     // Period Interval Status Register
-    AT91_REG     PITC_PIVR;     // Period Interval Value Register
-    AT91_REG     PITC_PIIR;     // Period Interval Image Register
-} AT91S_PITC, *AT91PS_PITC;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_PITC
+{
+    AT91_REG PITC_PIMR; /* Period Interval Mode Register */
+    AT91_REG PITC_PISR; /* Period Interval Status Register */
+    AT91_REG PITC_PIVR; /* Period Interval Value Register */
+    AT91_REG PITC_PIIR; /* Period Interval Image Register */
+} AT91S_PITC, * AT91PS_PITC;
 
-// -------- SYSC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
-#define AT91C_SYSC_PIV        ((unsigned int) 0xFFFFF <<  0) // (PITC) Periodic Interval Value
-#define AT91C_SYSC_PITEN      ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled
-#define AT91C_SYSC_PITIEN     ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
-// -------- SYSC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
-#define AT91C_SYSC_PITS       ((unsigned int) 0x1 <<  0) // (PITC) Periodic Interval Timer Status
-// -------- SYSC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
-#define AT91C_SYSC_CPIV       ((unsigned int) 0xFFFFF <<  0) // (PITC) Current Periodic Interval Value
-#define AT91C_SYSC_PICNT      ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter
-// -------- SYSC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
+/* -------- SYSC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- */
+#define AT91C_SYSC_PIV       ( ( unsigned int ) 0xFFFFF << 0 ) /* (PITC) Periodic Interval Value */
+#define AT91C_SYSC_PITEN     ( ( unsigned int ) 0x1 << 24 )    /* (PITC) Periodic Interval Timer Enabled */
+#define AT91C_SYSC_PITIEN    ( ( unsigned int ) 0x1 << 25 )    /* (PITC) Periodic Interval Timer Interrupt Enable */
+/* -------- SYSC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- */
+#define AT91C_SYSC_PITS      ( ( unsigned int ) 0x1 << 0 )     /* (PITC) Periodic Interval Timer Status */
+/* -------- SYSC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- */
+#define AT91C_SYSC_CPIV      ( ( unsigned int ) 0xFFFFF << 0 ) /* (PITC) Current Periodic Interval Value */
+#define AT91C_SYSC_PICNT     ( ( unsigned int ) 0xFFF << 20 )  /* (PITC) Periodic Interval Counter */
+/* -------- SYSC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_WDTC {
-    AT91_REG     WDTC_WDCR;     // Watchdog Control Register
-    AT91_REG     WDTC_WDMR;     // Watchdog Mode Register
-    AT91_REG     WDTC_WDSR;     // Watchdog Status Register
-} AT91S_WDTC, *AT91PS_WDTC;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_WDTC
+{
+    AT91_REG WDTC_WDCR; /* Watchdog Control Register */
+    AT91_REG WDTC_WDMR; /* Watchdog Mode Register */
+    AT91_REG WDTC_WDSR; /* Watchdog Status Register */
+} AT91S_WDTC, * AT91PS_WDTC;
 
-// -------- SYSC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
-#define AT91C_SYSC_WDRSTT     ((unsigned int) 0x1 <<  0) // (WDTC) Watchdog Restart
-// -------- SYSC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
-#define AT91C_SYSC_WDV        ((unsigned int) 0xFFF <<  0) // (WDTC) Watchdog Timer Restart
-#define AT91C_SYSC_WDFIEN     ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
-#define AT91C_SYSC_WDRSTEN    ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable
-#define AT91C_SYSC_WDRPROC    ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart
-#define AT91C_SYSC_WDDIS      ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable
-#define AT91C_SYSC_WDD        ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value
-#define AT91C_SYSC_WDDBGHLT   ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt
-#define AT91C_SYSC_WDIDLEHLT  ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt
-// -------- SYSC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
-#define AT91C_SYSC_WDUNF      ((unsigned int) 0x1 <<  0) // (WDTC) Watchdog Underflow
-#define AT91C_SYSC_WDERR      ((unsigned int) 0x1 <<  1) // (WDTC) Watchdog Error
+/* -------- SYSC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- */
+#define AT91C_SYSC_WDRSTT       ( ( unsigned int ) 0x1 << 0 )    /* (WDTC) Watchdog Restart */
+/* -------- SYSC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- */
+#define AT91C_SYSC_WDV          ( ( unsigned int ) 0xFFF << 0 )  /* (WDTC) Watchdog Timer Restart */
+#define AT91C_SYSC_WDFIEN       ( ( unsigned int ) 0x1 << 12 )   /* (WDTC) Watchdog Fault Interrupt Enable */
+#define AT91C_SYSC_WDRSTEN      ( ( unsigned int ) 0x1 << 13 )   /* (WDTC) Watchdog Reset Enable */
+#define AT91C_SYSC_WDRPROC      ( ( unsigned int ) 0x1 << 14 )   /* (WDTC) Watchdog Timer Restart */
+#define AT91C_SYSC_WDDIS        ( ( unsigned int ) 0x1 << 15 )   /* (WDTC) Watchdog Disable */
+#define AT91C_SYSC_WDD          ( ( unsigned int ) 0xFFF << 16 ) /* (WDTC) Watchdog Delta Value */
+#define AT91C_SYSC_WDDBGHLT     ( ( unsigned int ) 0x1 << 28 )   /* (WDTC) Watchdog Debug Halt */
+#define AT91C_SYSC_WDIDLEHLT    ( ( unsigned int ) 0x1 << 29 )   /* (WDTC) Watchdog Idle Halt */
+/* -------- SYSC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- */
+#define AT91C_SYSC_WDUNF        ( ( unsigned int ) 0x1 << 0 )    /* (WDTC) Watchdog Underflow */
+#define AT91C_SYSC_WDERR        ( ( unsigned int ) 0x1 << 1 )    /* (WDTC) Watchdog Error */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Memory Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_MC {
-    AT91_REG     MC_RCR;    // MC Remap Control Register
-    AT91_REG     MC_ASR;    // MC Abort Status Register
-    AT91_REG     MC_AASR;   // MC Abort Address Status Register
-    AT91_REG     Reserved0[21];     //
-    AT91_REG     MC_FMR;    // MC Flash Mode Register
-    AT91_REG     MC_FCR;    // MC Flash Command Register
-    AT91_REG     MC_FSR;    // MC Flash Status Register
-} AT91S_MC, *AT91PS_MC;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Memory Controller Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_MC
+{
+    AT91_REG MC_RCR;          /* MC Remap Control Register */
+    AT91_REG MC_ASR;          /* MC Abort Status Register */
+    AT91_REG MC_AASR;         /* MC Abort Address Status Register */
+    AT91_REG Reserved0[ 21 ]; /* */
+    AT91_REG MC_FMR;          /* MC Flash Mode Register */
+    AT91_REG MC_FCR;          /* MC Flash Command Register */
+    AT91_REG MC_FSR;          /* MC Flash Status Register */
+} AT91S_MC, * AT91PS_MC;
 
-// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
-#define AT91C_MC_RCB          ((unsigned int) 0x1 <<  0) // (MC) Remap Command Bit
-// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
-#define AT91C_MC_UNDADD       ((unsigned int) 0x1 <<  0) // (MC) Undefined Addess Abort Status
-#define AT91C_MC_MISADD       ((unsigned int) 0x1 <<  1) // (MC) Misaligned Addess Abort Status
-#define AT91C_MC_ABTSZ        ((unsigned int) 0x3 <<  8) // (MC) Abort Size Status
-#define     AT91C_MC_ABTSZ_BYTE                 ((unsigned int) 0x0 <<  8) // (MC) Byte
-#define     AT91C_MC_ABTSZ_HWORD                ((unsigned int) 0x1 <<  8) // (MC) Half-word
-#define     AT91C_MC_ABTSZ_WORD                 ((unsigned int) 0x2 <<  8) // (MC) Word
-#define AT91C_MC_ABTTYP       ((unsigned int) 0x3 << 10) // (MC) Abort Type Status
-#define     AT91C_MC_ABTTYP_DATAR                ((unsigned int) 0x0 << 10) // (MC) Data Read
-#define     AT91C_MC_ABTTYP_DATAW                ((unsigned int) 0x1 << 10) // (MC) Data Write
-#define     AT91C_MC_ABTTYP_FETCH                ((unsigned int) 0x2 << 10) // (MC) Code Fetch
-#define AT91C_MC_MST0         ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source
-#define AT91C_MC_MST1         ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source
-#define AT91C_MC_SVMST0       ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source
-#define AT91C_MC_SVMST1       ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source
-// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
-#define AT91C_MC_FRDY         ((unsigned int) 0x1 <<  0) // (MC) Flash Ready
-#define AT91C_MC_LOCKE        ((unsigned int) 0x1 <<  2) // (MC) Lock Error
-#define AT91C_MC_PROGE        ((unsigned int) 0x1 <<  3) // (MC) Programming Error
-#define AT91C_MC_NEBP         ((unsigned int) 0x1 <<  7) // (MC) No Erase Before Programming
-#define AT91C_MC_FWS          ((unsigned int) 0x3 <<  8) // (MC) Flash Wait State
-#define     AT91C_MC_FWS_0FWS                 ((unsigned int) 0x0 <<  8) // (MC) 1 cycle for Read, 2 for Write operations
-#define     AT91C_MC_FWS_1FWS                 ((unsigned int) 0x1 <<  8) // (MC) 2 cycles for Read, 3 for Write operations
-#define     AT91C_MC_FWS_2FWS                 ((unsigned int) 0x2 <<  8) // (MC) 3 cycles for Read, 4 for Write operations
-#define     AT91C_MC_FWS_3FWS                 ((unsigned int) 0x3 <<  8) // (MC) 4 cycles for Read, 4 for Write operations
-#define AT91C_MC_FMCN         ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number
-// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
-#define AT91C_MC_FCMD         ((unsigned int) 0xF <<  0) // (MC) Flash Command
-#define     AT91C_MC_FCMD_START_PROG           ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN.
-#define     AT91C_MC_FCMD_LOCK                 ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define     AT91C_MC_FCMD_PROG_AND_LOCK        ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
-#define     AT91C_MC_FCMD_UNLOCK               ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define     AT91C_MC_FCMD_ERASE_ALL            ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
-#define     AT91C_MC_FCMD_SET_GP_NVM           ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits.
-#define     AT91C_MC_FCMD_CLR_GP_NVM           ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits.
-#define     AT91C_MC_FCMD_SET_SECURITY         ((unsigned int) 0xF) // (MC) Set Security Bit.
-#define AT91C_MC_PAGEN        ((unsigned int) 0x3FF <<  8) // (MC) Page Number
-#define AT91C_MC_KEY          ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key
-// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register --------
-#define AT91C_MC_SECURITY     ((unsigned int) 0x1 <<  4) // (MC) Security Bit Status
-#define AT91C_MC_GPNVM0       ((unsigned int) 0x1 <<  8) // (MC) Sector 0 Lock Status
-#define AT91C_MC_GPNVM1       ((unsigned int) 0x1 <<  9) // (MC) Sector 1 Lock Status
-#define AT91C_MC_GPNVM2       ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status
-#define AT91C_MC_GPNVM3       ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status
-#define AT91C_MC_GPNVM4       ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status
-#define AT91C_MC_GPNVM5       ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status
-#define AT91C_MC_GPNVM6       ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status
-#define AT91C_MC_GPNVM7       ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS0       ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status
-#define AT91C_MC_LOCKS1       ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status
-#define AT91C_MC_LOCKS2       ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status
-#define AT91C_MC_LOCKS3       ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status
-#define AT91C_MC_LOCKS4       ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status
-#define AT91C_MC_LOCKS5       ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status
-#define AT91C_MC_LOCKS6       ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status
-#define AT91C_MC_LOCKS7       ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS8       ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status
-#define AT91C_MC_LOCKS9       ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status
-#define AT91C_MC_LOCKS10      ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status
-#define AT91C_MC_LOCKS11      ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status
-#define AT91C_MC_LOCKS12      ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status
-#define AT91C_MC_LOCKS13      ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status
-#define AT91C_MC_LOCKS14      ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status
-#define AT91C_MC_LOCKS15      ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status
+/* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */
+#define AT91C_MC_RCB                       ( ( unsigned int ) 0x1 << 0 )   /* (MC) Remap Command Bit */
+/* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */
+#define AT91C_MC_UNDADD                    ( ( unsigned int ) 0x1 << 0 )   /* (MC) Undefined Addess Abort Status */
+#define AT91C_MC_MISADD                    ( ( unsigned int ) 0x1 << 1 )   /* (MC) Misaligned Addess Abort Status */
+#define AT91C_MC_ABTSZ                     ( ( unsigned int ) 0x3 << 8 )   /* (MC) Abort Size Status */
+#define     AT91C_MC_ABTSZ_BYTE            ( ( unsigned int ) 0x0 << 8 )   /* (MC) Byte */
+#define     AT91C_MC_ABTSZ_HWORD           ( ( unsigned int ) 0x1 << 8 )   /* (MC) Half-word */
+#define     AT91C_MC_ABTSZ_WORD            ( ( unsigned int ) 0x2 << 8 )   /* (MC) Word */
+#define AT91C_MC_ABTTYP                    ( ( unsigned int ) 0x3 << 10 )  /* (MC) Abort Type Status */
+#define     AT91C_MC_ABTTYP_DATAR          ( ( unsigned int ) 0x0 << 10 )  /* (MC) Data Read */
+#define     AT91C_MC_ABTTYP_DATAW          ( ( unsigned int ) 0x1 << 10 )  /* (MC) Data Write */
+#define     AT91C_MC_ABTTYP_FETCH          ( ( unsigned int ) 0x2 << 10 )  /* (MC) Code Fetch */
+#define AT91C_MC_MST0                      ( ( unsigned int ) 0x1 << 16 )  /* (MC) Master 0 Abort Source */
+#define AT91C_MC_MST1                      ( ( unsigned int ) 0x1 << 17 )  /* (MC) Master 1 Abort Source */
+#define AT91C_MC_SVMST0                    ( ( unsigned int ) 0x1 << 24 )  /* (MC) Saved Master 0 Abort Source */
+#define AT91C_MC_SVMST1                    ( ( unsigned int ) 0x1 << 25 )  /* (MC) Saved Master 1 Abort Source */
+/* -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- */
+#define AT91C_MC_FRDY                      ( ( unsigned int ) 0x1 << 0 )   /* (MC) Flash Ready */
+#define AT91C_MC_LOCKE                     ( ( unsigned int ) 0x1 << 2 )   /* (MC) Lock Error */
+#define AT91C_MC_PROGE                     ( ( unsigned int ) 0x1 << 3 )   /* (MC) Programming Error */
+#define AT91C_MC_NEBP                      ( ( unsigned int ) 0x1 << 7 )   /* (MC) No Erase Before Programming */
+#define AT91C_MC_FWS                       ( ( unsigned int ) 0x3 << 8 )   /* (MC) Flash Wait State */
+#define     AT91C_MC_FWS_0FWS              ( ( unsigned int ) 0x0 << 8 )   /* (MC) 1 cycle for Read, 2 for Write operations */
+#define     AT91C_MC_FWS_1FWS              ( ( unsigned int ) 0x1 << 8 )   /* (MC) 2 cycles for Read, 3 for Write operations */
+#define     AT91C_MC_FWS_2FWS              ( ( unsigned int ) 0x2 << 8 )   /* (MC) 3 cycles for Read, 4 for Write operations */
+#define     AT91C_MC_FWS_3FWS              ( ( unsigned int ) 0x3 << 8 )   /* (MC) 4 cycles for Read, 4 for Write operations */
+#define AT91C_MC_FMCN                      ( ( unsigned int ) 0xFF << 16 ) /* (MC) Flash Microsecond Cycle Number */
+/* -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- */
+#define AT91C_MC_FCMD                      ( ( unsigned int ) 0xF << 0 )   /* (MC) Flash Command */
+#define     AT91C_MC_FCMD_START_PROG       ( ( unsigned int ) 0x1 )        /* (MC) Starts the programming of th epage specified by PAGEN. */
+#define     AT91C_MC_FCMD_LOCK             ( ( unsigned int ) 0x2 )        /* (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */
+#define     AT91C_MC_FCMD_PROG_AND_LOCK    ( ( unsigned int ) 0x3 )        /* (MC) The lock sequence automatically happens after the programming sequence is completed. */
+#define     AT91C_MC_FCMD_UNLOCK           ( ( unsigned int ) 0x4 )        /* (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */
+#define     AT91C_MC_FCMD_ERASE_ALL        ( ( unsigned int ) 0x8 )        /* (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. */
+#define     AT91C_MC_FCMD_SET_GP_NVM       ( ( unsigned int ) 0xB )        /* (MC) Set General Purpose NVM bits. */
+#define     AT91C_MC_FCMD_CLR_GP_NVM       ( ( unsigned int ) 0xD )        /* (MC) Clear General Purpose NVM bits. */
+#define     AT91C_MC_FCMD_SET_SECURITY     ( ( unsigned int ) 0xF )        /* (MC) Set Security Bit. */
+#define AT91C_MC_PAGEN                     ( ( unsigned int ) 0x3FF << 8 ) /* (MC) Page Number */
+#define AT91C_MC_KEY                       ( ( unsigned int ) 0xFF << 24 ) /* (MC) Writing Protect Key */
+/* -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- */
+#define AT91C_MC_SECURITY                  ( ( unsigned int ) 0x1 << 4 )   /* (MC) Security Bit Status */
+#define AT91C_MC_GPNVM0                    ( ( unsigned int ) 0x1 << 8 )   /* (MC) Sector 0 Lock Status */
+#define AT91C_MC_GPNVM1                    ( ( unsigned int ) 0x1 << 9 )   /* (MC) Sector 1 Lock Status */
+#define AT91C_MC_GPNVM2                    ( ( unsigned int ) 0x1 << 10 )  /* (MC) Sector 2 Lock Status */
+#define AT91C_MC_GPNVM3                    ( ( unsigned int ) 0x1 << 11 )  /* (MC) Sector 3 Lock Status */
+#define AT91C_MC_GPNVM4                    ( ( unsigned int ) 0x1 << 12 )  /* (MC) Sector 4 Lock Status */
+#define AT91C_MC_GPNVM5                    ( ( unsigned int ) 0x1 << 13 )  /* (MC) Sector 5 Lock Status */
+#define AT91C_MC_GPNVM6                    ( ( unsigned int ) 0x1 << 14 )  /* (MC) Sector 6 Lock Status */
+#define AT91C_MC_GPNVM7                    ( ( unsigned int ) 0x1 << 15 )  /* (MC) Sector 7 Lock Status */
+#define AT91C_MC_LOCKS0                    ( ( unsigned int ) 0x1 << 16 )  /* (MC) Sector 0 Lock Status */
+#define AT91C_MC_LOCKS1                    ( ( unsigned int ) 0x1 << 17 )  /* (MC) Sector 1 Lock Status */
+#define AT91C_MC_LOCKS2                    ( ( unsigned int ) 0x1 << 18 )  /* (MC) Sector 2 Lock Status */
+#define AT91C_MC_LOCKS3                    ( ( unsigned int ) 0x1 << 19 )  /* (MC) Sector 3 Lock Status */
+#define AT91C_MC_LOCKS4                    ( ( unsigned int ) 0x1 << 20 )  /* (MC) Sector 4 Lock Status */
+#define AT91C_MC_LOCKS5                    ( ( unsigned int ) 0x1 << 21 )  /* (MC) Sector 5 Lock Status */
+#define AT91C_MC_LOCKS6                    ( ( unsigned int ) 0x1 << 22 )  /* (MC) Sector 6 Lock Status */
+#define AT91C_MC_LOCKS7                    ( ( unsigned int ) 0x1 << 23 )  /* (MC) Sector 7 Lock Status */
+#define AT91C_MC_LOCKS8                    ( ( unsigned int ) 0x1 << 24 )  /* (MC) Sector 8 Lock Status */
+#define AT91C_MC_LOCKS9                    ( ( unsigned int ) 0x1 << 25 )  /* (MC) Sector 9 Lock Status */
+#define AT91C_MC_LOCKS10                   ( ( unsigned int ) 0x1 << 26 )  /* (MC) Sector 10 Lock Status */
+#define AT91C_MC_LOCKS11                   ( ( unsigned int ) 0x1 << 27 )  /* (MC) Sector 11 Lock Status */
+#define AT91C_MC_LOCKS12                   ( ( unsigned int ) 0x1 << 28 )  /* (MC) Sector 12 Lock Status */
+#define AT91C_MC_LOCKS13                   ( ( unsigned int ) 0x1 << 29 )  /* (MC) Sector 13 Lock Status */
+#define AT91C_MC_LOCKS14                   ( ( unsigned int ) 0x1 << 30 )  /* (MC) Sector 14 Lock Status */
+#define AT91C_MC_LOCKS15                   ( ( unsigned int ) 0x1 << 31 )  /* (MC) Sector 15 Lock Status */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
-// *****************************************************************************
-typedef struct _AT91S_SPI {
-    AT91_REG     SPI_CR;    // Control Register
-    AT91_REG     SPI_MR;    // Mode Register
-    AT91_REG     SPI_RDR;   // Receive Data Register
-    AT91_REG     SPI_TDR;   // Transmit Data Register
-    AT91_REG     SPI_SR;    // Status Register
-    AT91_REG     SPI_IER;   // Interrupt Enable Register
-    AT91_REG     SPI_IDR;   // Interrupt Disable Register
-    AT91_REG     SPI_IMR;   // Interrupt Mask Register
-    AT91_REG     Reserved0[4];  //
-    AT91_REG     SPI_CSR[4];    // Chip Select Register
-    AT91_REG     Reserved1[48];     //
-    AT91_REG     SPI_RPR;   // Receive Pointer Register
-    AT91_REG     SPI_RCR;   // Receive Counter Register
-    AT91_REG     SPI_TPR;   // Transmit Pointer Register
-    AT91_REG     SPI_TCR;   // Transmit Counter Register
-    AT91_REG     SPI_RNPR;  // Receive Next Pointer Register
-    AT91_REG     SPI_RNCR;  // Receive Next Counter Register
-    AT91_REG     SPI_TNPR;  // Transmit Next Pointer Register
-    AT91_REG     SPI_TNCR;  // Transmit Next Counter Register
-    AT91_REG     SPI_PTCR;  // PDC Transfer Control Register
-    AT91_REG     SPI_PTSR;  // PDC Transfer Status Register
-} AT91S_SPI, *AT91PS_SPI;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Serial Parallel Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_SPI
+{
+    AT91_REG SPI_CR;          /* Control Register */
+    AT91_REG SPI_MR;          /* Mode Register */
+    AT91_REG SPI_RDR;         /* Receive Data Register */
+    AT91_REG SPI_TDR;         /* Transmit Data Register */
+    AT91_REG SPI_SR;          /* Status Register */
+    AT91_REG SPI_IER;         /* Interrupt Enable Register */
+    AT91_REG SPI_IDR;         /* Interrupt Disable Register */
+    AT91_REG SPI_IMR;         /* Interrupt Mask Register */
+    AT91_REG Reserved0[ 4 ];  /* */
+    AT91_REG SPI_CSR[ 4 ];    /* Chip Select Register */
+    AT91_REG Reserved1[ 48 ]; /* */
+    AT91_REG SPI_RPR;         /* Receive Pointer Register */
+    AT91_REG SPI_RCR;         /* Receive Counter Register */
+    AT91_REG SPI_TPR;         /* Transmit Pointer Register */
+    AT91_REG SPI_TCR;         /* Transmit Counter Register */
+    AT91_REG SPI_RNPR;        /* Receive Next Pointer Register */
+    AT91_REG SPI_RNCR;        /* Receive Next Counter Register */
+    AT91_REG SPI_TNPR;        /* Transmit Next Pointer Register */
+    AT91_REG SPI_TNCR;        /* Transmit Next Counter Register */
+    AT91_REG SPI_PTCR;        /* PDC Transfer Control Register */
+    AT91_REG SPI_PTSR;        /* PDC Transfer Status Register */
+} AT91S_SPI, * AT91PS_SPI;
 
-// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
-#define AT91C_SPI_SPIEN       ((unsigned int) 0x1 <<  0) // (SPI) SPI Enable
-#define AT91C_SPI_SPIDIS      ((unsigned int) 0x1 <<  1) // (SPI) SPI Disable
-#define AT91C_SPI_SWRST       ((unsigned int) 0x1 <<  7) // (SPI) SPI Software reset
-#define AT91C_SPI_LASTXFER    ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer
-// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
-#define AT91C_SPI_MSTR        ((unsigned int) 0x1 <<  0) // (SPI) Master/Slave Mode
-#define AT91C_SPI_PS          ((unsigned int) 0x1 <<  1) // (SPI) Peripheral Select
-#define     AT91C_SPI_PS_FIXED                ((unsigned int) 0x0 <<  1) // (SPI) Fixed Peripheral Select
-#define     AT91C_SPI_PS_VARIABLE             ((unsigned int) 0x1 <<  1) // (SPI) Variable Peripheral Select
-#define AT91C_SPI_PCSDEC      ((unsigned int) 0x1 <<  2) // (SPI) Chip Select Decode
-#define AT91C_SPI_FDIV        ((unsigned int) 0x1 <<  3) // (SPI) Clock Selection
-#define AT91C_SPI_MODFDIS     ((unsigned int) 0x1 <<  4) // (SPI) Mode Fault Detection
-#define AT91C_SPI_LLB         ((unsigned int) 0x1 <<  7) // (SPI) Clock Selection
-#define AT91C_SPI_PCS         ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select
-#define AT91C_SPI_DLYBCS      ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects
-// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
-#define AT91C_SPI_RD          ((unsigned int) 0xFFFF <<  0) // (SPI) Receive Data
-#define AT91C_SPI_RPCS        ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
-#define AT91C_SPI_TD          ((unsigned int) 0xFFFF <<  0) // (SPI) Transmit Data
-#define AT91C_SPI_TPCS        ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
-#define AT91C_SPI_RDRF        ((unsigned int) 0x1 <<  0) // (SPI) Receive Data Register Full
-#define AT91C_SPI_TDRE        ((unsigned int) 0x1 <<  1) // (SPI) Transmit Data Register Empty
-#define AT91C_SPI_MODF        ((unsigned int) 0x1 <<  2) // (SPI) Mode Fault Error
-#define AT91C_SPI_OVRES       ((unsigned int) 0x1 <<  3) // (SPI) Overrun Error Status
-#define AT91C_SPI_ENDRX       ((unsigned int) 0x1 <<  4) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_ENDTX       ((unsigned int) 0x1 <<  5) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_RXBUFF      ((unsigned int) 0x1 <<  6) // (SPI) RXBUFF Interrupt
-#define AT91C_SPI_TXBUFE      ((unsigned int) 0x1 <<  7) // (SPI) TXBUFE Interrupt
-#define AT91C_SPI_NSSR        ((unsigned int) 0x1 <<  8) // (SPI) NSSR Interrupt
-#define AT91C_SPI_TXEMPTY     ((unsigned int) 0x1 <<  9) // (SPI) TXEMPTY Interrupt
-#define AT91C_SPI_SPIENS      ((unsigned int) 0x1 << 16) // (SPI) Enable Status
-// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
-// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
-// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
-// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
-#define AT91C_SPI_CPOL        ((unsigned int) 0x1 <<  0) // (SPI) Clock Polarity
-#define AT91C_SPI_NCPHA       ((unsigned int) 0x1 <<  1) // (SPI) Clock Phase
-#define AT91C_SPI_CSAAT       ((unsigned int) 0x1 <<  2) // (SPI) Chip Select Active After Transfer
-#define AT91C_SPI_BITS        ((unsigned int) 0xF <<  4) // (SPI) Bits Per Transfer
-#define     AT91C_SPI_BITS_8                    ((unsigned int) 0x0 <<  4) // (SPI) 8 Bits Per transfer
-#define     AT91C_SPI_BITS_9                    ((unsigned int) 0x1 <<  4) // (SPI) 9 Bits Per transfer
-#define     AT91C_SPI_BITS_10                   ((unsigned int) 0x2 <<  4) // (SPI) 10 Bits Per transfer
-#define     AT91C_SPI_BITS_11                   ((unsigned int) 0x3 <<  4) // (SPI) 11 Bits Per transfer
-#define     AT91C_SPI_BITS_12                   ((unsigned int) 0x4 <<  4) // (SPI) 12 Bits Per transfer
-#define     AT91C_SPI_BITS_13                   ((unsigned int) 0x5 <<  4) // (SPI) 13 Bits Per transfer
-#define     AT91C_SPI_BITS_14                   ((unsigned int) 0x6 <<  4) // (SPI) 14 Bits Per transfer
-#define     AT91C_SPI_BITS_15                   ((unsigned int) 0x7 <<  4) // (SPI) 15 Bits Per transfer
-#define     AT91C_SPI_BITS_16                   ((unsigned int) 0x8 <<  4) // (SPI) 16 Bits Per transfer
-#define AT91C_SPI_SCBR        ((unsigned int) 0xFF <<  8) // (SPI) Serial Clock Baud Rate
-#define AT91C_SPI_DLYBS       ((unsigned int) 0xFF << 16) // (SPI) Serial Clock Baud Rate
-#define AT91C_SPI_DLYBCT      ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers
+/* -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */
+#define AT91C_SPI_SPIEN              ( ( unsigned int ) 0x1 << 0 )    /* (SPI) SPI Enable */
+#define AT91C_SPI_SPIDIS             ( ( unsigned int ) 0x1 << 1 )    /* (SPI) SPI Disable */
+#define AT91C_SPI_SWRST              ( ( unsigned int ) 0x1 << 7 )    /* (SPI) SPI Software reset */
+#define AT91C_SPI_LASTXFER           ( ( unsigned int ) 0x1 << 24 )   /* (SPI) SPI Last Transfer */
+/* -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- */
+#define AT91C_SPI_MSTR               ( ( unsigned int ) 0x1 << 0 )    /* (SPI) Master/Slave Mode */
+#define AT91C_SPI_PS                 ( ( unsigned int ) 0x1 << 1 )    /* (SPI) Peripheral Select */
+#define     AT91C_SPI_PS_FIXED       ( ( unsigned int ) 0x0 << 1 )    /* (SPI) Fixed Peripheral Select */
+#define     AT91C_SPI_PS_VARIABLE    ( ( unsigned int ) 0x1 << 1 )    /* (SPI) Variable Peripheral Select */
+#define AT91C_SPI_PCSDEC             ( ( unsigned int ) 0x1 << 2 )    /* (SPI) Chip Select Decode */
+#define AT91C_SPI_FDIV               ( ( unsigned int ) 0x1 << 3 )    /* (SPI) Clock Selection */
+#define AT91C_SPI_MODFDIS            ( ( unsigned int ) 0x1 << 4 )    /* (SPI) Mode Fault Detection */
+#define AT91C_SPI_LLB                ( ( unsigned int ) 0x1 << 7 )    /* (SPI) Clock Selection */
+#define AT91C_SPI_PCS                ( ( unsigned int ) 0xF << 16 )   /* (SPI) Peripheral Chip Select */
+#define AT91C_SPI_DLYBCS             ( ( unsigned int ) 0xFF << 24 )  /* (SPI) Delay Between Chip Selects */
+/* -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- */
+#define AT91C_SPI_RD                 ( ( unsigned int ) 0xFFFF << 0 ) /* (SPI) Receive Data */
+#define AT91C_SPI_RPCS               ( ( unsigned int ) 0xF << 16 )   /* (SPI) Peripheral Chip Select Status */
+/* -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- */
+#define AT91C_SPI_TD                 ( ( unsigned int ) 0xFFFF << 0 ) /* (SPI) Transmit Data */
+#define AT91C_SPI_TPCS               ( ( unsigned int ) 0xF << 16 )   /* (SPI) Peripheral Chip Select Status */
+/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
+#define AT91C_SPI_RDRF               ( ( unsigned int ) 0x1 << 0 )    /* (SPI) Receive Data Register Full */
+#define AT91C_SPI_TDRE               ( ( unsigned int ) 0x1 << 1 )    /* (SPI) Transmit Data Register Empty */
+#define AT91C_SPI_MODF               ( ( unsigned int ) 0x1 << 2 )    /* (SPI) Mode Fault Error */
+#define AT91C_SPI_OVRES              ( ( unsigned int ) 0x1 << 3 )    /* (SPI) Overrun Error Status */
+#define AT91C_SPI_ENDRX              ( ( unsigned int ) 0x1 << 4 )    /* (SPI) End of Receiver Transfer */
+#define AT91C_SPI_ENDTX              ( ( unsigned int ) 0x1 << 5 )    /* (SPI) End of Receiver Transfer */
+#define AT91C_SPI_RXBUFF             ( ( unsigned int ) 0x1 << 6 )    /* (SPI) RXBUFF Interrupt */
+#define AT91C_SPI_TXBUFE             ( ( unsigned int ) 0x1 << 7 )    /* (SPI) TXBUFE Interrupt */
+#define AT91C_SPI_NSSR               ( ( unsigned int ) 0x1 << 8 )    /* (SPI) NSSR Interrupt */
+#define AT91C_SPI_TXEMPTY            ( ( unsigned int ) 0x1 << 9 )    /* (SPI) TXEMPTY Interrupt */
+#define AT91C_SPI_SPIENS             ( ( unsigned int ) 0x1 << 16 )   /* (SPI) Enable Status */
+/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
+/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
+/* -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */
+/* -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */
+#define AT91C_SPI_CPOL           ( ( unsigned int ) 0x1 << 0 )   /* (SPI) Clock Polarity */
+#define AT91C_SPI_NCPHA          ( ( unsigned int ) 0x1 << 1 )   /* (SPI) Clock Phase */
+#define AT91C_SPI_CSAAT          ( ( unsigned int ) 0x1 << 2 )   /* (SPI) Chip Select Active After Transfer */
+#define AT91C_SPI_BITS           ( ( unsigned int ) 0xF << 4 )   /* (SPI) Bits Per Transfer */
+#define     AT91C_SPI_BITS_8     ( ( unsigned int ) 0x0 << 4 )   /* (SPI) 8 Bits Per transfer */
+#define     AT91C_SPI_BITS_9     ( ( unsigned int ) 0x1 << 4 )   /* (SPI) 9 Bits Per transfer */
+#define     AT91C_SPI_BITS_10    ( ( unsigned int ) 0x2 << 4 )   /* (SPI) 10 Bits Per transfer */
+#define     AT91C_SPI_BITS_11    ( ( unsigned int ) 0x3 << 4 )   /* (SPI) 11 Bits Per transfer */
+#define     AT91C_SPI_BITS_12    ( ( unsigned int ) 0x4 << 4 )   /* (SPI) 12 Bits Per transfer */
+#define     AT91C_SPI_BITS_13    ( ( unsigned int ) 0x5 << 4 )   /* (SPI) 13 Bits Per transfer */
+#define     AT91C_SPI_BITS_14    ( ( unsigned int ) 0x6 << 4 )   /* (SPI) 14 Bits Per transfer */
+#define     AT91C_SPI_BITS_15    ( ( unsigned int ) 0x7 << 4 )   /* (SPI) 15 Bits Per transfer */
+#define     AT91C_SPI_BITS_16    ( ( unsigned int ) 0x8 << 4 )   /* (SPI) 16 Bits Per transfer */
+#define AT91C_SPI_SCBR           ( ( unsigned int ) 0xFF << 8 )  /* (SPI) Serial Clock Baud Rate */
+#define AT91C_SPI_DLYBS          ( ( unsigned int ) 0xFF << 16 ) /* (SPI) Serial Clock Baud Rate */
+#define AT91C_SPI_DLYBCT         ( ( unsigned int ) 0xFF << 24 ) /* (SPI) Delay Between Consecutive Transfers */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
-// *****************************************************************************
-typedef struct _AT91S_ADC {
-    AT91_REG     ADC_CR;    // ADC Control Register
-    AT91_REG     ADC_MR;    // ADC Mode Register
-    AT91_REG     Reserved0[2];  //
-    AT91_REG     ADC_CHER;  // ADC Channel Enable Register
-    AT91_REG     ADC_CHDR;  // ADC Channel Disable Register
-    AT91_REG     ADC_CHSR;  // ADC Channel Status Register
-    AT91_REG     ADC_SR;    // ADC Status Register
-    AT91_REG     ADC_LCDR;  // ADC Last Converted Data Register
-    AT91_REG     ADC_IER;   // ADC Interrupt Enable Register
-    AT91_REG     ADC_IDR;   // ADC Interrupt Disable Register
-    AT91_REG     ADC_IMR;   // ADC Interrupt Mask Register
-    AT91_REG     ADC_CDR0;  // ADC Channel Data Register 0
-    AT91_REG     ADC_CDR1;  // ADC Channel Data Register 1
-    AT91_REG     ADC_CDR2;  // ADC Channel Data Register 2
-    AT91_REG     ADC_CDR3;  // ADC Channel Data Register 3
-    AT91_REG     ADC_CDR4;  // ADC Channel Data Register 4
-    AT91_REG     ADC_CDR5;  // ADC Channel Data Register 5
-    AT91_REG     ADC_CDR6;  // ADC Channel Data Register 6
-    AT91_REG     ADC_CDR7;  // ADC Channel Data Register 7
-    AT91_REG     Reserved1[44];     //
-    AT91_REG     ADC_RPR;   // Receive Pointer Register
-    AT91_REG     ADC_RCR;   // Receive Counter Register
-    AT91_REG     ADC_TPR;   // Transmit Pointer Register
-    AT91_REG     ADC_TCR;   // Transmit Counter Register
-    AT91_REG     ADC_RNPR;  // Receive Next Pointer Register
-    AT91_REG     ADC_RNCR;  // Receive Next Counter Register
-    AT91_REG     ADC_TNPR;  // Transmit Next Pointer Register
-    AT91_REG     ADC_TNCR;  // Transmit Next Counter Register
-    AT91_REG     ADC_PTCR;  // PDC Transfer Control Register
-    AT91_REG     ADC_PTSR;  // PDC Transfer Status Register
-} AT91S_ADC, *AT91PS_ADC;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor */
+/* ***************************************************************************** */
+typedef struct _AT91S_ADC
+{
+    AT91_REG ADC_CR;          /* ADC Control Register */
+    AT91_REG ADC_MR;          /* ADC Mode Register */
+    AT91_REG Reserved0[ 2 ];  /* */
+    AT91_REG ADC_CHER;        /* ADC Channel Enable Register */
+    AT91_REG ADC_CHDR;        /* ADC Channel Disable Register */
+    AT91_REG ADC_CHSR;        /* ADC Channel Status Register */
+    AT91_REG ADC_SR;          /* ADC Status Register */
+    AT91_REG ADC_LCDR;        /* ADC Last Converted Data Register */
+    AT91_REG ADC_IER;         /* ADC Interrupt Enable Register */
+    AT91_REG ADC_IDR;         /* ADC Interrupt Disable Register */
+    AT91_REG ADC_IMR;         /* ADC Interrupt Mask Register */
+    AT91_REG ADC_CDR0;        /* ADC Channel Data Register 0 */
+    AT91_REG ADC_CDR1;        /* ADC Channel Data Register 1 */
+    AT91_REG ADC_CDR2;        /* ADC Channel Data Register 2 */
+    AT91_REG ADC_CDR3;        /* ADC Channel Data Register 3 */
+    AT91_REG ADC_CDR4;        /* ADC Channel Data Register 4 */
+    AT91_REG ADC_CDR5;        /* ADC Channel Data Register 5 */
+    AT91_REG ADC_CDR6;        /* ADC Channel Data Register 6 */
+    AT91_REG ADC_CDR7;        /* ADC Channel Data Register 7 */
+    AT91_REG Reserved1[ 44 ]; /* */
+    AT91_REG ADC_RPR;         /* Receive Pointer Register */
+    AT91_REG ADC_RCR;         /* Receive Counter Register */
+    AT91_REG ADC_TPR;         /* Transmit Pointer Register */
+    AT91_REG ADC_TCR;         /* Transmit Counter Register */
+    AT91_REG ADC_RNPR;        /* Receive Next Pointer Register */
+    AT91_REG ADC_RNCR;        /* Receive Next Counter Register */
+    AT91_REG ADC_TNPR;        /* Transmit Next Pointer Register */
+    AT91_REG ADC_TNCR;        /* Transmit Next Counter Register */
+    AT91_REG ADC_PTCR;        /* PDC Transfer Control Register */
+    AT91_REG ADC_PTSR;        /* PDC Transfer Status Register */
+} AT91S_ADC, * AT91PS_ADC;
 
-// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
-#define AT91C_ADC_SWRST       ((unsigned int) 0x1 <<  0) // (ADC) Software Reset
-#define AT91C_ADC_START       ((unsigned int) 0x1 <<  1) // (ADC) Start Conversion
-// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
-#define AT91C_ADC_TRGEN       ((unsigned int) 0x1 <<  0) // (ADC) Trigger Enable
-#define     AT91C_ADC_TRGEN_DIS                  ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
-#define     AT91C_ADC_TRGEN_EN                   ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
-#define AT91C_ADC_TRGSEL      ((unsigned int) 0x7 <<  1) // (ADC) Trigger Selection
-#define     AT91C_ADC_TRGSEL_TIOA0                ((unsigned int) 0x0 <<  1) // (ADC) Selected TRGSEL = TIAO0
-#define     AT91C_ADC_TRGSEL_TIOA1                ((unsigned int) 0x1 <<  1) // (ADC) Selected TRGSEL = TIAO1
-#define     AT91C_ADC_TRGSEL_TIOA2                ((unsigned int) 0x2 <<  1) // (ADC) Selected TRGSEL = TIAO2
-#define     AT91C_ADC_TRGSEL_TIOA3                ((unsigned int) 0x3 <<  1) // (ADC) Selected TRGSEL = TIAO3
-#define     AT91C_ADC_TRGSEL_TIOA4                ((unsigned int) 0x4 <<  1) // (ADC) Selected TRGSEL = TIAO4
-#define     AT91C_ADC_TRGSEL_TIOA5                ((unsigned int) 0x5 <<  1) // (ADC) Selected TRGSEL = TIAO5
-#define     AT91C_ADC_TRGSEL_EXT                  ((unsigned int) 0x6 <<  1) // (ADC) Selected TRGSEL = External Trigger
-#define AT91C_ADC_LOWRES      ((unsigned int) 0x1 <<  4) // (ADC) Resolution.
-#define     AT91C_ADC_LOWRES_10_BIT               ((unsigned int) 0x0 <<  4) // (ADC) 10-bit resolution
-#define     AT91C_ADC_LOWRES_8_BIT                ((unsigned int) 0x1 <<  4) // (ADC) 8-bit resolution
-#define AT91C_ADC_SLEEP       ((unsigned int) 0x1 <<  5) // (ADC) Sleep Mode
-#define     AT91C_ADC_SLEEP_NORMAL_MODE          ((unsigned int) 0x0 <<  5) // (ADC) Normal Mode
-#define     AT91C_ADC_SLEEP_MODE                 ((unsigned int) 0x1 <<  5) // (ADC) Sleep Mode
-#define AT91C_ADC_PRESCAL     ((unsigned int) 0x3F <<  8) // (ADC) Prescaler rate selection
-#define AT91C_ADC_STARTUP     ((unsigned int) 0x1F << 16) // (ADC) Startup Time
-#define AT91C_ADC_SHTIM       ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time
-// --------     ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
-#define AT91C_ADC_CH0         ((unsigned int) 0x1 <<  0) // (ADC) Channel 0
-#define AT91C_ADC_CH1         ((unsigned int) 0x1 <<  1) // (ADC) Channel 1
-#define AT91C_ADC_CH2         ((unsigned int) 0x1 <<  2) // (ADC) Channel 2
-#define AT91C_ADC_CH3         ((unsigned int) 0x1 <<  3) // (ADC) Channel 3
-#define AT91C_ADC_CH4         ((unsigned int) 0x1 <<  4) // (ADC) Channel 4
-#define AT91C_ADC_CH5         ((unsigned int) 0x1 <<  5) // (ADC) Channel 5
-#define AT91C_ADC_CH6         ((unsigned int) 0x1 <<  6) // (ADC) Channel 6
-#define AT91C_ADC_CH7         ((unsigned int) 0x1 <<  7) // (ADC) Channel 7
-// --------     ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
-// --------     ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
-// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
-#define AT91C_ADC_EOC0        ((unsigned int) 0x1 <<  0) // (ADC) End of Conversion
-#define AT91C_ADC_EOC1        ((unsigned int) 0x1 <<  1) // (ADC) End of Conversion
-#define AT91C_ADC_EOC2        ((unsigned int) 0x1 <<  2) // (ADC) End of Conversion
-#define AT91C_ADC_EOC3        ((unsigned int) 0x1 <<  3) // (ADC) End of Conversion
-#define AT91C_ADC_EOC4        ((unsigned int) 0x1 <<  4) // (ADC) End of Conversion
-#define AT91C_ADC_EOC5        ((unsigned int) 0x1 <<  5) // (ADC) End of Conversion
-#define AT91C_ADC_EOC6        ((unsigned int) 0x1 <<  6) // (ADC) End of Conversion
-#define AT91C_ADC_EOC7        ((unsigned int) 0x1 <<  7) // (ADC) End of Conversion
-#define AT91C_ADC_OVRE0       ((unsigned int) 0x1 <<  8) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE1       ((unsigned int) 0x1 <<  9) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE2       ((unsigned int) 0x1 << 10) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE3       ((unsigned int) 0x1 << 11) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE4       ((unsigned int) 0x1 << 12) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE5       ((unsigned int) 0x1 << 13) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE6       ((unsigned int) 0x1 << 14) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE7       ((unsigned int) 0x1 << 15) // (ADC) Overrun Error
-#define AT91C_ADC_DRDY        ((unsigned int) 0x1 << 16) // (ADC) Data Ready
-#define AT91C_ADC_GOVRE       ((unsigned int) 0x1 << 17) // (ADC) General Overrun
-#define AT91C_ADC_ENDRX       ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer
-#define AT91C_ADC_RXBUFF      ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt
-// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
-#define AT91C_ADC_LDATA       ((unsigned int) 0x3FF <<  0) // (ADC) Last Data Converted
-// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
-// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
-// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
-// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
-#define AT91C_ADC_DATA        ((unsigned int) 0x3FF <<  0) // (ADC) Converted Data
-// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
-// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
-// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
-// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
-// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
-// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
-// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
+/* -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- */
+#define AT91C_ADC_SWRST                    ( ( unsigned int ) 0x1 << 0 )   /* (ADC) Software Reset */
+#define AT91C_ADC_START                    ( ( unsigned int ) 0x1 << 1 )   /* (ADC) Start Conversion */
+/* -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- */
+#define AT91C_ADC_TRGEN                    ( ( unsigned int ) 0x1 << 0 )   /* (ADC) Trigger Enable */
+#define     AT91C_ADC_TRGEN_DIS            ( ( unsigned int ) 0x0 )        /* (ADC) Hardware triggers are disabled. Starting a conversion is only possible by software */
+#define     AT91C_ADC_TRGEN_EN             ( ( unsigned int ) 0x1 )        /* (ADC) Hardware trigger selected by TRGSEL field is enabled. */
+#define AT91C_ADC_TRGSEL                   ( ( unsigned int ) 0x7 << 1 )   /* (ADC) Trigger Selection */
+#define     AT91C_ADC_TRGSEL_TIOA0         ( ( unsigned int ) 0x0 << 1 )   /* (ADC) Selected TRGSEL = TIAO0 */
+#define     AT91C_ADC_TRGSEL_TIOA1         ( ( unsigned int ) 0x1 << 1 )   /* (ADC) Selected TRGSEL = TIAO1 */
+#define     AT91C_ADC_TRGSEL_TIOA2         ( ( unsigned int ) 0x2 << 1 )   /* (ADC) Selected TRGSEL = TIAO2 */
+#define     AT91C_ADC_TRGSEL_TIOA3         ( ( unsigned int ) 0x3 << 1 )   /* (ADC) Selected TRGSEL = TIAO3 */
+#define     AT91C_ADC_TRGSEL_TIOA4         ( ( unsigned int ) 0x4 << 1 )   /* (ADC) Selected TRGSEL = TIAO4 */
+#define     AT91C_ADC_TRGSEL_TIOA5         ( ( unsigned int ) 0x5 << 1 )   /* (ADC) Selected TRGSEL = TIAO5 */
+#define     AT91C_ADC_TRGSEL_EXT           ( ( unsigned int ) 0x6 << 1 )   /* (ADC) Selected TRGSEL = External Trigger */
+#define AT91C_ADC_LOWRES                   ( ( unsigned int ) 0x1 << 4 )   /* (ADC) Resolution. */
+#define     AT91C_ADC_LOWRES_10_BIT        ( ( unsigned int ) 0x0 << 4 )   /* (ADC) 10-bit resolution */
+#define     AT91C_ADC_LOWRES_8_BIT         ( ( unsigned int ) 0x1 << 4 )   /* (ADC) 8-bit resolution */
+#define AT91C_ADC_SLEEP                    ( ( unsigned int ) 0x1 << 5 )   /* (ADC) Sleep Mode */
+#define     AT91C_ADC_SLEEP_NORMAL_MODE    ( ( unsigned int ) 0x0 << 5 )   /* (ADC) Normal Mode */
+#define     AT91C_ADC_SLEEP_MODE           ( ( unsigned int ) 0x1 << 5 )   /* (ADC) Sleep Mode */
+#define AT91C_ADC_PRESCAL                  ( ( unsigned int ) 0x3F << 8 )  /* (ADC) Prescaler rate selection */
+#define AT91C_ADC_STARTUP                  ( ( unsigned int ) 0x1F << 16 ) /* (ADC) Startup Time */
+#define AT91C_ADC_SHTIM                    ( ( unsigned int ) 0xF << 24 )  /* (ADC) Sample & Hold Time */
+/* --------     ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- */
+#define AT91C_ADC_CH0                      ( ( unsigned int ) 0x1 << 0 )   /* (ADC) Channel 0 */
+#define AT91C_ADC_CH1                      ( ( unsigned int ) 0x1 << 1 )   /* (ADC) Channel 1 */
+#define AT91C_ADC_CH2                      ( ( unsigned int ) 0x1 << 2 )   /* (ADC) Channel 2 */
+#define AT91C_ADC_CH3                      ( ( unsigned int ) 0x1 << 3 )   /* (ADC) Channel 3 */
+#define AT91C_ADC_CH4                      ( ( unsigned int ) 0x1 << 4 )   /* (ADC) Channel 4 */
+#define AT91C_ADC_CH5                      ( ( unsigned int ) 0x1 << 5 )   /* (ADC) Channel 5 */
+#define AT91C_ADC_CH6                      ( ( unsigned int ) 0x1 << 6 )   /* (ADC) Channel 6 */
+#define AT91C_ADC_CH7                      ( ( unsigned int ) 0x1 << 7 )   /* (ADC) Channel 7 */
+/* --------     ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- */
+/* --------     ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- */
+/* -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- */
+#define AT91C_ADC_EOC0      ( ( unsigned int ) 0x1 << 0 )   /* (ADC) End of Conversion */
+#define AT91C_ADC_EOC1      ( ( unsigned int ) 0x1 << 1 )   /* (ADC) End of Conversion */
+#define AT91C_ADC_EOC2      ( ( unsigned int ) 0x1 << 2 )   /* (ADC) End of Conversion */
+#define AT91C_ADC_EOC3      ( ( unsigned int ) 0x1 << 3 )   /* (ADC) End of Conversion */
+#define AT91C_ADC_EOC4      ( ( unsigned int ) 0x1 << 4 )   /* (ADC) End of Conversion */
+#define AT91C_ADC_EOC5      ( ( unsigned int ) 0x1 << 5 )   /* (ADC) End of Conversion */
+#define AT91C_ADC_EOC6      ( ( unsigned int ) 0x1 << 6 )   /* (ADC) End of Conversion */
+#define AT91C_ADC_EOC7      ( ( unsigned int ) 0x1 << 7 )   /* (ADC) End of Conversion */
+#define AT91C_ADC_OVRE0     ( ( unsigned int ) 0x1 << 8 )   /* (ADC) Overrun Error */
+#define AT91C_ADC_OVRE1     ( ( unsigned int ) 0x1 << 9 )   /* (ADC) Overrun Error */
+#define AT91C_ADC_OVRE2     ( ( unsigned int ) 0x1 << 10 )  /* (ADC) Overrun Error */
+#define AT91C_ADC_OVRE3     ( ( unsigned int ) 0x1 << 11 )  /* (ADC) Overrun Error */
+#define AT91C_ADC_OVRE4     ( ( unsigned int ) 0x1 << 12 )  /* (ADC) Overrun Error */
+#define AT91C_ADC_OVRE5     ( ( unsigned int ) 0x1 << 13 )  /* (ADC) Overrun Error */
+#define AT91C_ADC_OVRE6     ( ( unsigned int ) 0x1 << 14 )  /* (ADC) Overrun Error */
+#define AT91C_ADC_OVRE7     ( ( unsigned int ) 0x1 << 15 )  /* (ADC) Overrun Error */
+#define AT91C_ADC_DRDY      ( ( unsigned int ) 0x1 << 16 )  /* (ADC) Data Ready */
+#define AT91C_ADC_GOVRE     ( ( unsigned int ) 0x1 << 17 )  /* (ADC) General Overrun */
+#define AT91C_ADC_ENDRX     ( ( unsigned int ) 0x1 << 18 )  /* (ADC) End of Receiver Transfer */
+#define AT91C_ADC_RXBUFF    ( ( unsigned int ) 0x1 << 19 )  /* (ADC) RXBUFF Interrupt */
+/* -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- */
+#define AT91C_ADC_LDATA     ( ( unsigned int ) 0x3FF << 0 ) /* (ADC) Last Data Converted */
+/* -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- */
+/* -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- */
+/* -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- */
+/* -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- */
+#define AT91C_ADC_DATA    ( ( unsigned int ) 0x3FF << 0 )  /* (ADC) Converted Data */
+/* -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- */
+/* -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- */
+/* -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- */
+/* -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- */
+/* -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- */
+/* -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- */
+/* -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_SSC {
-    AT91_REG     SSC_CR;    // Control Register
-    AT91_REG     SSC_CMR;   // Clock Mode Register
-    AT91_REG     Reserved0[2];  //
-    AT91_REG     SSC_RCMR;  // Receive Clock ModeRegister
-    AT91_REG     SSC_RFMR;  // Receive Frame Mode Register
-    AT91_REG     SSC_TCMR;  // Transmit Clock Mode Register
-    AT91_REG     SSC_TFMR;  // Transmit Frame Mode Register
-    AT91_REG     SSC_RHR;   // Receive Holding Register
-    AT91_REG     SSC_THR;   // Transmit Holding Register
-    AT91_REG     Reserved1[2];  //
-    AT91_REG     SSC_RSHR;  // Receive Sync Holding Register
-    AT91_REG     SSC_TSHR;  // Transmit Sync Holding Register
-    AT91_REG     SSC_RC0R;  // Receive Compare 0 Register
-    AT91_REG     SSC_RC1R;  // Receive Compare 1 Register
-    AT91_REG     SSC_SR;    // Status Register
-    AT91_REG     SSC_IER;   // Interrupt Enable Register
-    AT91_REG     SSC_IDR;   // Interrupt Disable Register
-    AT91_REG     SSC_IMR;   // Interrupt Mask Register
-    AT91_REG     Reserved2[44];     //
-    AT91_REG     SSC_RPR;   // Receive Pointer Register
-    AT91_REG     SSC_RCR;   // Receive Counter Register
-    AT91_REG     SSC_TPR;   // Transmit Pointer Register
-    AT91_REG     SSC_TCR;   // Transmit Counter Register
-    AT91_REG     SSC_RNPR;  // Receive Next Pointer Register
-    AT91_REG     SSC_RNCR;  // Receive Next Counter Register
-    AT91_REG     SSC_TNPR;  // Transmit Next Pointer Register
-    AT91_REG     SSC_TNCR;  // Transmit Next Counter Register
-    AT91_REG     SSC_PTCR;  // PDC Transfer Control Register
-    AT91_REG     SSC_PTSR;  // PDC Transfer Status Register
-} AT91S_SSC, *AT91PS_SSC;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_SSC
+{
+    AT91_REG SSC_CR;          /* Control Register */
+    AT91_REG SSC_CMR;         /* Clock Mode Register */
+    AT91_REG Reserved0[ 2 ];  /* */
+    AT91_REG SSC_RCMR;        /* Receive Clock ModeRegister */
+    AT91_REG SSC_RFMR;        /* Receive Frame Mode Register */
+    AT91_REG SSC_TCMR;        /* Transmit Clock Mode Register */
+    AT91_REG SSC_TFMR;        /* Transmit Frame Mode Register */
+    AT91_REG SSC_RHR;         /* Receive Holding Register */
+    AT91_REG SSC_THR;         /* Transmit Holding Register */
+    AT91_REG Reserved1[ 2 ];  /* */
+    AT91_REG SSC_RSHR;        /* Receive Sync Holding Register */
+    AT91_REG SSC_TSHR;        /* Transmit Sync Holding Register */
+    AT91_REG SSC_RC0R;        /* Receive Compare 0 Register */
+    AT91_REG SSC_RC1R;        /* Receive Compare 1 Register */
+    AT91_REG SSC_SR;          /* Status Register */
+    AT91_REG SSC_IER;         /* Interrupt Enable Register */
+    AT91_REG SSC_IDR;         /* Interrupt Disable Register */
+    AT91_REG SSC_IMR;         /* Interrupt Mask Register */
+    AT91_REG Reserved2[ 44 ]; /* */
+    AT91_REG SSC_RPR;         /* Receive Pointer Register */
+    AT91_REG SSC_RCR;         /* Receive Counter Register */
+    AT91_REG SSC_TPR;         /* Transmit Pointer Register */
+    AT91_REG SSC_TCR;         /* Transmit Counter Register */
+    AT91_REG SSC_RNPR;        /* Receive Next Pointer Register */
+    AT91_REG SSC_RNCR;        /* Receive Next Counter Register */
+    AT91_REG SSC_TNPR;        /* Transmit Next Pointer Register */
+    AT91_REG SSC_TNCR;        /* Transmit Next Counter Register */
+    AT91_REG SSC_PTCR;        /* PDC Transfer Control Register */
+    AT91_REG SSC_PTSR;        /* PDC Transfer Status Register */
+} AT91S_SSC, * AT91PS_SSC;
 
-// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
-#define AT91C_SSC_RXEN        ((unsigned int) 0x1 <<  0) // (SSC) Receive Enable
-#define AT91C_SSC_RXDIS       ((unsigned int) 0x1 <<  1) // (SSC) Receive Disable
-#define AT91C_SSC_TXEN        ((unsigned int) 0x1 <<  8) // (SSC) Transmit Enable
-#define AT91C_SSC_TXDIS       ((unsigned int) 0x1 <<  9) // (SSC) Transmit Disable
-#define AT91C_SSC_SWRST       ((unsigned int) 0x1 << 15) // (SSC) Software Reset
-// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
-#define AT91C_SSC_CKS         ((unsigned int) 0x3 <<  0) // (SSC) Receive/Transmit Clock Selection
-#define     AT91C_SSC_CKS_DIV                  ((unsigned int) 0x0) // (SSC) Divided Clock
-#define     AT91C_SSC_CKS_TK                   ((unsigned int) 0x1) // (SSC) TK Clock signal
-#define     AT91C_SSC_CKS_RK                   ((unsigned int) 0x2) // (SSC) RK pin
-#define AT91C_SSC_CKO         ((unsigned int) 0x7 <<  2) // (SSC) Receive/Transmit Clock Output Mode Selection
-#define     AT91C_SSC_CKO_NONE                 ((unsigned int) 0x0 <<  2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
-#define     AT91C_SSC_CKO_CONTINOUS            ((unsigned int) 0x1 <<  2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
-#define     AT91C_SSC_CKO_DATA_TX              ((unsigned int) 0x2 <<  2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
-#define AT91C_SSC_CKI         ((unsigned int) 0x1 <<  5) // (SSC) Receive/Transmit Clock Inversion
-#define AT91C_SSC_CKG         ((unsigned int) 0x3 <<  6) // (SSC) Receive/Transmit Clock Gating Selection
-#define     AT91C_SSC_CKG_NONE                 ((unsigned int) 0x0 <<  6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock
-#define     AT91C_SSC_CKG_LOW                  ((unsigned int) 0x1 <<  6) // (SSC) Receive/Transmit Clock enabled only if RF Low
-#define     AT91C_SSC_CKG_HIGH                 ((unsigned int) 0x2 <<  6) // (SSC) Receive/Transmit Clock enabled only if RF High
-#define AT91C_SSC_START       ((unsigned int) 0xF <<  8) // (SSC) Receive/Transmit Start Selection
-#define     AT91C_SSC_START_CONTINOUS            ((unsigned int) 0x0 <<  8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
-#define     AT91C_SSC_START_TX                   ((unsigned int) 0x1 <<  8) // (SSC) Transmit/Receive start
-#define     AT91C_SSC_START_LOW_RF               ((unsigned int) 0x2 <<  8) // (SSC) Detection of a low level on RF input
-#define     AT91C_SSC_START_HIGH_RF              ((unsigned int) 0x3 <<  8) // (SSC) Detection of a high level on RF input
-#define     AT91C_SSC_START_FALL_RF              ((unsigned int) 0x4 <<  8) // (SSC) Detection of a falling edge on RF input
-#define     AT91C_SSC_START_RISE_RF              ((unsigned int) 0x5 <<  8) // (SSC) Detection of a rising edge on RF input
-#define     AT91C_SSC_START_LEVEL_RF             ((unsigned int) 0x6 <<  8) // (SSC) Detection of any level change on RF input
-#define     AT91C_SSC_START_EDGE_RF              ((unsigned int) 0x7 <<  8) // (SSC) Detection of any edge on RF input
-#define     AT91C_SSC_START_0                    ((unsigned int) 0x8 <<  8) // (SSC) Compare 0
-#define AT91C_SSC_STOP        ((unsigned int) 0x1 << 12) // (SSC) Receive Stop Selection
-#define AT91C_SSC_STTOUT      ((unsigned int) 0x1 << 15) // (SSC) Receive/Transmit Start Output Selection
-#define AT91C_SSC_STTDLY      ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay
-#define AT91C_SSC_PERIOD      ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
-// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
-#define AT91C_SSC_DATLEN      ((unsigned int) 0x1F <<  0) // (SSC) Data Length
-#define AT91C_SSC_LOOP        ((unsigned int) 0x1 <<  5) // (SSC) Loop Mode
-#define AT91C_SSC_MSBF        ((unsigned int) 0x1 <<  7) // (SSC) Most Significant Bit First
-#define AT91C_SSC_DATNB       ((unsigned int) 0xF <<  8) // (SSC) Data Number per Frame
-#define AT91C_SSC_FSLEN       ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length
-#define AT91C_SSC_FSOS        ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
-#define     AT91C_SSC_FSOS_NONE                 ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
-#define     AT91C_SSC_FSOS_NEGATIVE             ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
-#define     AT91C_SSC_FSOS_POSITIVE             ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
-#define     AT91C_SSC_FSOS_LOW                  ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
-#define     AT91C_SSC_FSOS_HIGH                 ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
-#define     AT91C_SSC_FSOS_TOGGLE               ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
-#define AT91C_SSC_FSEDGE      ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection
-// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
-// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
-#define AT91C_SSC_DATDEF      ((unsigned int) 0x1 <<  5) // (SSC) Data Default Value
-#define AT91C_SSC_FSDEN       ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable
-// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
-#define AT91C_SSC_TXRDY       ((unsigned int) 0x1 <<  0) // (SSC) Transmit Ready
-#define AT91C_SSC_TXEMPTY     ((unsigned int) 0x1 <<  1) // (SSC) Transmit Empty
-#define AT91C_SSC_ENDTX       ((unsigned int) 0x1 <<  2) // (SSC) End Of Transmission
-#define AT91C_SSC_TXBUFE      ((unsigned int) 0x1 <<  3) // (SSC) Transmit Buffer Empty
-#define AT91C_SSC_RXRDY       ((unsigned int) 0x1 <<  4) // (SSC) Receive Ready
-#define AT91C_SSC_OVRUN       ((unsigned int) 0x1 <<  5) // (SSC) Receive Overrun
-#define AT91C_SSC_ENDRX       ((unsigned int) 0x1 <<  6) // (SSC) End of Reception
-#define AT91C_SSC_RXBUFF      ((unsigned int) 0x1 <<  7) // (SSC) Receive Buffer Full
-#define AT91C_SSC_CP0         ((unsigned int) 0x1 <<  8) // (SSC) Compare 0
-#define AT91C_SSC_CP1         ((unsigned int) 0x1 <<  9) // (SSC) Compare 1
-#define AT91C_SSC_TXSYN       ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync
-#define AT91C_SSC_RXSYN       ((unsigned int) 0x1 << 11) // (SSC) Receive Sync
-#define AT91C_SSC_TXENA       ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable
-#define AT91C_SSC_RXENA       ((unsigned int) 0x1 << 17) // (SSC) Receive Enable
-// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
-// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
-// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
+/* -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- */
+#define AT91C_SSC_RXEN                    ( ( unsigned int ) 0x1 << 0 )   /* (SSC) Receive Enable */
+#define AT91C_SSC_RXDIS                   ( ( unsigned int ) 0x1 << 1 )   /* (SSC) Receive Disable */
+#define AT91C_SSC_TXEN                    ( ( unsigned int ) 0x1 << 8 )   /* (SSC) Transmit Enable */
+#define AT91C_SSC_TXDIS                   ( ( unsigned int ) 0x1 << 9 )   /* (SSC) Transmit Disable */
+#define AT91C_SSC_SWRST                   ( ( unsigned int ) 0x1 << 15 )  /* (SSC) Software Reset */
+/* -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- */
+#define AT91C_SSC_CKS                     ( ( unsigned int ) 0x3 << 0 )   /* (SSC) Receive/Transmit Clock Selection */
+#define     AT91C_SSC_CKS_DIV             ( ( unsigned int ) 0x0 )        /* (SSC) Divided Clock */
+#define     AT91C_SSC_CKS_TK              ( ( unsigned int ) 0x1 )        /* (SSC) TK Clock signal */
+#define     AT91C_SSC_CKS_RK              ( ( unsigned int ) 0x2 )        /* (SSC) RK pin */
+#define AT91C_SSC_CKO                     ( ( unsigned int ) 0x7 << 2 )   /* (SSC) Receive/Transmit Clock Output Mode Selection */
+#define     AT91C_SSC_CKO_NONE            ( ( unsigned int ) 0x0 << 2 )   /* (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only */
+#define     AT91C_SSC_CKO_CONTINUOUS      ( ( unsigned int ) 0x1 << 2 )   /* (SSC) Continuous Receive/Transmit Clock RK pin: Output */
+#define     AT91C_SSC_CKO_DATA_TX         ( ( unsigned int ) 0x2 << 2 )   /* (SSC) Receive/Transmit Clock only during data transfers RK pin: Output */
+#define AT91C_SSC_CKI                     ( ( unsigned int ) 0x1 << 5 )   /* (SSC) Receive/Transmit Clock Inversion */
+#define AT91C_SSC_CKG                     ( ( unsigned int ) 0x3 << 6 )   /* (SSC) Receive/Transmit Clock Gating Selection */
+#define     AT91C_SSC_CKG_NONE            ( ( unsigned int ) 0x0 << 6 )   /* (SSC) Receive/Transmit Clock Gating: None, continuous clock */
+#define     AT91C_SSC_CKG_LOW             ( ( unsigned int ) 0x1 << 6 )   /* (SSC) Receive/Transmit Clock enabled only if RF Low */
+#define     AT91C_SSC_CKG_HIGH            ( ( unsigned int ) 0x2 << 6 )   /* (SSC) Receive/Transmit Clock enabled only if RF High */
+#define AT91C_SSC_START                   ( ( unsigned int ) 0xF << 8 )   /* (SSC) Receive/Transmit Start Selection */
+#define     AT91C_SSC_START_CONTINUOUS    ( ( unsigned int ) 0x0 << 8 )   /* (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */
+#define     AT91C_SSC_START_TX            ( ( unsigned int ) 0x1 << 8 )   /* (SSC) Transmit/Receive start */
+#define     AT91C_SSC_START_LOW_RF        ( ( unsigned int ) 0x2 << 8 )   /* (SSC) Detection of a low level on RF input */
+#define     AT91C_SSC_START_HIGH_RF       ( ( unsigned int ) 0x3 << 8 )   /* (SSC) Detection of a high level on RF input */
+#define     AT91C_SSC_START_FALL_RF       ( ( unsigned int ) 0x4 << 8 )   /* (SSC) Detection of a falling edge on RF input */
+#define     AT91C_SSC_START_RISE_RF       ( ( unsigned int ) 0x5 << 8 )   /* (SSC) Detection of a rising edge on RF input */
+#define     AT91C_SSC_START_LEVEL_RF      ( ( unsigned int ) 0x6 << 8 )   /* (SSC) Detection of any level change on RF input */
+#define     AT91C_SSC_START_EDGE_RF       ( ( unsigned int ) 0x7 << 8 )   /* (SSC) Detection of any edge on RF input */
+#define     AT91C_SSC_START_0             ( ( unsigned int ) 0x8 << 8 )   /* (SSC) Compare 0 */
+#define AT91C_SSC_STOP                    ( ( unsigned int ) 0x1 << 12 )  /* (SSC) Receive Stop Selection */
+#define AT91C_SSC_STTOUT                  ( ( unsigned int ) 0x1 << 15 )  /* (SSC) Receive/Transmit Start Output Selection */
+#define AT91C_SSC_STTDLY                  ( ( unsigned int ) 0xFF << 16 ) /* (SSC) Receive/Transmit Start Delay */
+#define AT91C_SSC_PERIOD                  ( ( unsigned int ) 0xFF << 24 ) /* (SSC) Receive/Transmit Period Divider Selection */
+/* -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- */
+#define AT91C_SSC_DATLEN                  ( ( unsigned int ) 0x1F << 0 )  /* (SSC) Data Length */
+#define AT91C_SSC_LOOP                    ( ( unsigned int ) 0x1 << 5 )   /* (SSC) Loop Mode */
+#define AT91C_SSC_MSBF                    ( ( unsigned int ) 0x1 << 7 )   /* (SSC) Most Significant Bit First */
+#define AT91C_SSC_DATNB                   ( ( unsigned int ) 0xF << 8 )   /* (SSC) Data Number per Frame */
+#define AT91C_SSC_FSLEN                   ( ( unsigned int ) 0xF << 16 )  /* (SSC) Receive/Transmit Frame Sync length */
+#define AT91C_SSC_FSOS                    ( ( unsigned int ) 0x7 << 20 )  /* (SSC) Receive/Transmit Frame Sync Output Selection */
+#define     AT91C_SSC_FSOS_NONE           ( ( unsigned int ) 0x0 << 20 )  /* (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only */
+#define     AT91C_SSC_FSOS_NEGATIVE       ( ( unsigned int ) 0x1 << 20 )  /* (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse */
+#define     AT91C_SSC_FSOS_POSITIVE       ( ( unsigned int ) 0x2 << 20 )  /* (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse */
+#define     AT91C_SSC_FSOS_LOW            ( ( unsigned int ) 0x3 << 20 )  /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer */
+#define     AT91C_SSC_FSOS_HIGH           ( ( unsigned int ) 0x4 << 20 )  /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer */
+#define     AT91C_SSC_FSOS_TOGGLE         ( ( unsigned int ) 0x5 << 20 )  /* (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer */
+#define AT91C_SSC_FSEDGE                  ( ( unsigned int ) 0x1 << 24 )  /* (SSC) Frame Sync Edge Detection */
+/* -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- */
+/* -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- */
+#define AT91C_SSC_DATDEF                  ( ( unsigned int ) 0x1 << 5 )  /* (SSC) Data Default Value */
+#define AT91C_SSC_FSDEN                   ( ( unsigned int ) 0x1 << 23 ) /* (SSC) Frame Sync Data Enable */
+/* -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- */
+#define AT91C_SSC_TXRDY                   ( ( unsigned int ) 0x1 << 0 )  /* (SSC) Transmit Ready */
+#define AT91C_SSC_TXEMPTY                 ( ( unsigned int ) 0x1 << 1 )  /* (SSC) Transmit Empty */
+#define AT91C_SSC_ENDTX                   ( ( unsigned int ) 0x1 << 2 )  /* (SSC) End Of Transmission */
+#define AT91C_SSC_TXBUFE                  ( ( unsigned int ) 0x1 << 3 )  /* (SSC) Transmit Buffer Empty */
+#define AT91C_SSC_RXRDY                   ( ( unsigned int ) 0x1 << 4 )  /* (SSC) Receive Ready */
+#define AT91C_SSC_OVRUN                   ( ( unsigned int ) 0x1 << 5 )  /* (SSC) Receive Overrun */
+#define AT91C_SSC_ENDRX                   ( ( unsigned int ) 0x1 << 6 )  /* (SSC) End of Reception */
+#define AT91C_SSC_RXBUFF                  ( ( unsigned int ) 0x1 << 7 )  /* (SSC) Receive Buffer Full */
+#define AT91C_SSC_CP0                     ( ( unsigned int ) 0x1 << 8 )  /* (SSC) Compare 0 */
+#define AT91C_SSC_CP1                     ( ( unsigned int ) 0x1 << 9 )  /* (SSC) Compare 1 */
+#define AT91C_SSC_TXSYN                   ( ( unsigned int ) 0x1 << 10 ) /* (SSC) Transmit Sync */
+#define AT91C_SSC_RXSYN                   ( ( unsigned int ) 0x1 << 11 ) /* (SSC) Receive Sync */
+#define AT91C_SSC_TXENA                   ( ( unsigned int ) 0x1 << 16 ) /* (SSC) Transmit Enable */
+#define AT91C_SSC_RXENA                   ( ( unsigned int ) 0x1 << 17 ) /* (SSC) Receive Enable */
+/* -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- */
+/* -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- */
+/* -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Usart
-// *****************************************************************************
-typedef struct _AT91S_USART {
-    AT91_REG     US_CR;     // Control Register
-    AT91_REG     US_MR;     // Mode Register
-    AT91_REG     US_IER;    // Interrupt Enable Register
-    AT91_REG     US_IDR;    // Interrupt Disable Register
-    AT91_REG     US_IMR;    // Interrupt Mask Register
-    AT91_REG     US_CSR;    // Channel Status Register
-    AT91_REG     US_RHR;    // Receiver Holding Register
-    AT91_REG     US_THR;    // Transmitter Holding Register
-    AT91_REG     US_BRGR;   // Baud Rate Generator Register
-    AT91_REG     US_RTOR;   // Receiver Time-out Register
-    AT91_REG     US_TTGR;   // Transmitter Time-guard Register
-    AT91_REG     Reserved0[5];  //
-    AT91_REG     US_FIDI;   // FI_DI_Ratio Register
-    AT91_REG     US_NER;    // Nb Errors Register
-    AT91_REG     US_XXR;    // XON_XOFF Register
-    AT91_REG     US_IF;     // IRDA_FILTER Register
-    AT91_REG     Reserved1[44];     //
-    AT91_REG     US_RPR;    // Receive Pointer Register
-    AT91_REG     US_RCR;    // Receive Counter Register
-    AT91_REG     US_TPR;    // Transmit Pointer Register
-    AT91_REG     US_TCR;    // Transmit Counter Register
-    AT91_REG     US_RNPR;   // Receive Next Pointer Register
-    AT91_REG     US_RNCR;   // Receive Next Counter Register
-    AT91_REG     US_TNPR;   // Transmit Next Pointer Register
-    AT91_REG     US_TNCR;   // Transmit Next Counter Register
-    AT91_REG     US_PTCR;   // PDC Transfer Control Register
-    AT91_REG     US_PTSR;   // PDC Transfer Status Register
-} AT91S_USART, *AT91PS_USART;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Usart */
+/* ***************************************************************************** */
+typedef struct _AT91S_USART
+{
+    AT91_REG US_CR;           /* Control Register */
+    AT91_REG US_MR;           /* Mode Register */
+    AT91_REG US_IER;          /* Interrupt Enable Register */
+    AT91_REG US_IDR;          /* Interrupt Disable Register */
+    AT91_REG US_IMR;          /* Interrupt Mask Register */
+    AT91_REG US_CSR;          /* Channel Status Register */
+    AT91_REG US_RHR;          /* Receiver Holding Register */
+    AT91_REG US_THR;          /* Transmitter Holding Register */
+    AT91_REG US_BRGR;         /* Baud Rate Generator Register */
+    AT91_REG US_RTOR;         /* Receiver Time-out Register */
+    AT91_REG US_TTGR;         /* Transmitter Time-guard Register */
+    AT91_REG Reserved0[ 5 ];  /* */
+    AT91_REG US_FIDI;         /* FI_DI_Ratio Register */
+    AT91_REG US_NER;          /* Nb Errors Register */
+    AT91_REG US_XXR;          /* XON_XOFF Register */
+    AT91_REG US_IF;           /* IRDA_FILTER Register */
+    AT91_REG Reserved1[ 44 ]; /* */
+    AT91_REG US_RPR;          /* Receive Pointer Register */
+    AT91_REG US_RCR;          /* Receive Counter Register */
+    AT91_REG US_TPR;          /* Transmit Pointer Register */
+    AT91_REG US_TCR;          /* Transmit Counter Register */
+    AT91_REG US_RNPR;         /* Receive Next Pointer Register */
+    AT91_REG US_RNCR;         /* Receive Next Counter Register */
+    AT91_REG US_TNPR;         /* Transmit Next Pointer Register */
+    AT91_REG US_TNCR;         /* Transmit Next Counter Register */
+    AT91_REG US_PTCR;         /* PDC Transfer Control Register */
+    AT91_REG US_PTSR;         /* PDC Transfer Status Register */
+} AT91S_USART, * AT91PS_USART;
 
-// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
-#define AT91C_US_RSTSTA       ((unsigned int) 0x1 <<  8) // (USART) Reset Status Bits
-#define AT91C_US_STTBRK       ((unsigned int) 0x1 <<  9) // (USART) Start Break
-#define AT91C_US_STPBRK       ((unsigned int) 0x1 << 10) // (USART) Stop Break
-#define AT91C_US_STTTO        ((unsigned int) 0x1 << 11) // (USART) Start Time-out
-#define AT91C_US_SENDA        ((unsigned int) 0x1 << 12) // (USART) Send Address
-#define AT91C_US_RSTIT        ((unsigned int) 0x1 << 13) // (USART) Reset Iterations
-#define AT91C_US_RSTNACK      ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge
-#define AT91C_US_RETTO        ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out
-#define AT91C_US_DTREN        ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable
-#define AT91C_US_DTRDIS       ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable
-#define AT91C_US_RTSEN        ((unsigned int) 0x1 << 18) // (USART) Request to Send enable
-#define AT91C_US_RTSDIS       ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable
-// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
-#define AT91C_US_USMODE       ((unsigned int) 0xF <<  0) // (USART) Usart mode
-#define     AT91C_US_USMODE_NORMAL               ((unsigned int) 0x0) // (USART) Normal
-#define     AT91C_US_USMODE_RS485                ((unsigned int) 0x1) // (USART) RS485
-#define     AT91C_US_USMODE_HWHSH                ((unsigned int) 0x2) // (USART) Hardware Handshaking
-#define     AT91C_US_USMODE_MODEM                ((unsigned int) 0x3) // (USART) Modem
-#define     AT91C_US_USMODE_ISO7816_0            ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0
-#define     AT91C_US_USMODE_ISO7816_1            ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1
-#define     AT91C_US_USMODE_IRDA                 ((unsigned int) 0x8) // (USART) IrDA
-#define     AT91C_US_USMODE_SWHSH                ((unsigned int) 0xC) // (USART) Software Handshaking
-#define AT91C_US_CLKS         ((unsigned int) 0x3 <<  4) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define     AT91C_US_CLKS_CLOCK                ((unsigned int) 0x0 <<  4) // (USART) Clock
-#define     AT91C_US_CLKS_FDIV1                ((unsigned int) 0x1 <<  4) // (USART) fdiv1
-#define     AT91C_US_CLKS_SLOW                 ((unsigned int) 0x2 <<  4) // (USART) slow_clock (ARM)
-#define     AT91C_US_CLKS_EXT                  ((unsigned int) 0x3 <<  4) // (USART) External (SCK)
-#define AT91C_US_CHRL         ((unsigned int) 0x3 <<  6) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define     AT91C_US_CHRL_5_BITS               ((unsigned int) 0x0 <<  6) // (USART) Character Length: 5 bits
-#define     AT91C_US_CHRL_6_BITS               ((unsigned int) 0x1 <<  6) // (USART) Character Length: 6 bits
-#define     AT91C_US_CHRL_7_BITS               ((unsigned int) 0x2 <<  6) // (USART) Character Length: 7 bits
-#define     AT91C_US_CHRL_8_BITS               ((unsigned int) 0x3 <<  6) // (USART) Character Length: 8 bits
-#define AT91C_US_SYNC         ((unsigned int) 0x1 <<  8) // (USART) Synchronous Mode Select
-#define AT91C_US_NBSTOP       ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits
-#define     AT91C_US_NBSTOP_1_BIT                ((unsigned int) 0x0 << 12) // (USART) 1 stop bit
-#define     AT91C_US_NBSTOP_15_BIT               ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
-#define     AT91C_US_NBSTOP_2_BIT                ((unsigned int) 0x2 << 12) // (USART) 2 stop bits
-#define AT91C_US_MSBF         ((unsigned int) 0x1 << 16) // (USART) Bit Order
-#define AT91C_US_MODE9        ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length
-#define AT91C_US_CKLO         ((unsigned int) 0x1 << 18) // (USART) Clock Output Select
-#define AT91C_US_OVER         ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode
-#define AT91C_US_INACK        ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge
-#define AT91C_US_DSNACK       ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK
-#define AT91C_US_MAX_ITER     ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions
-#define AT91C_US_FILTER       ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter
-// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
-#define AT91C_US_RXBRK        ((unsigned int) 0x1 <<  2) // (USART) Break Received/End of Break
-#define AT91C_US_TIMEOUT      ((unsigned int) 0x1 <<  8) // (USART) Receiver Time-out
-#define AT91C_US_ITERATION    ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached
-#define AT91C_US_NACK         ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge
-#define AT91C_US_RIIC         ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag
-#define AT91C_US_DSRIC        ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag
-#define AT91C_US_DCDIC        ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag
-#define AT91C_US_CTSIC        ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag
-// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
-// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
-// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
-#define AT91C_US_RI           ((unsigned int) 0x1 << 20) // (USART) Image of RI Input
-#define AT91C_US_DSR          ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input
-#define AT91C_US_DCD          ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input
-#define AT91C_US_CTS          ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input
+/* -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- */
+#define AT91C_US_RSTSTA                  ( ( unsigned int ) 0x1 << 8 )  /* (USART) Reset Status Bits */
+#define AT91C_US_STTBRK                  ( ( unsigned int ) 0x1 << 9 )  /* (USART) Start Break */
+#define AT91C_US_STPBRK                  ( ( unsigned int ) 0x1 << 10 ) /* (USART) Stop Break */
+#define AT91C_US_STTTO                   ( ( unsigned int ) 0x1 << 11 ) /* (USART) Start Time-out */
+#define AT91C_US_SENDA                   ( ( unsigned int ) 0x1 << 12 ) /* (USART) Send Address */
+#define AT91C_US_RSTIT                   ( ( unsigned int ) 0x1 << 13 ) /* (USART) Reset Iterations */
+#define AT91C_US_RSTNACK                 ( ( unsigned int ) 0x1 << 14 ) /* (USART) Reset Non Acknowledge */
+#define AT91C_US_RETTO                   ( ( unsigned int ) 0x1 << 15 ) /* (USART) Rearm Time-out */
+#define AT91C_US_DTREN                   ( ( unsigned int ) 0x1 << 16 ) /* (USART) Data Terminal ready Enable */
+#define AT91C_US_DTRDIS                  ( ( unsigned int ) 0x1 << 17 ) /* (USART) Data Terminal ready Disable */
+#define AT91C_US_RTSEN                   ( ( unsigned int ) 0x1 << 18 ) /* (USART) Request to Send enable */
+#define AT91C_US_RTSDIS                  ( ( unsigned int ) 0x1 << 19 ) /* (USART) Request to Send Disable */
+/* -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- */
+#define AT91C_US_USMODE                  ( ( unsigned int ) 0xF << 0 )  /* (USART) Usart mode */
+#define     AT91C_US_USMODE_NORMAL       ( ( unsigned int ) 0x0 )       /* (USART) Normal */
+#define     AT91C_US_USMODE_RS485        ( ( unsigned int ) 0x1 )       /* (USART) RS485 */
+#define     AT91C_US_USMODE_HWHSH        ( ( unsigned int ) 0x2 )       /* (USART) Hardware Handshaking */
+#define     AT91C_US_USMODE_MODEM        ( ( unsigned int ) 0x3 )       /* (USART) Modem */
+#define     AT91C_US_USMODE_ISO7816_0    ( ( unsigned int ) 0x4 )       /* (USART) ISO7816 protocol: T = 0 */
+#define     AT91C_US_USMODE_ISO7816_1    ( ( unsigned int ) 0x6 )       /* (USART) ISO7816 protocol: T = 1 */
+#define     AT91C_US_USMODE_IRDA         ( ( unsigned int ) 0x8 )       /* (USART) IrDA */
+#define     AT91C_US_USMODE_SWHSH        ( ( unsigned int ) 0xC )       /* (USART) Software Handshaking */
+#define AT91C_US_CLKS                    ( ( unsigned int ) 0x3 << 4 )  /* (USART) Clock Selection (Baud Rate generator Input Clock */
+#define     AT91C_US_CLKS_CLOCK          ( ( unsigned int ) 0x0 << 4 )  /* (USART) Clock */
+#define     AT91C_US_CLKS_FDIV1          ( ( unsigned int ) 0x1 << 4 )  /* (USART) fdiv1 */
+#define     AT91C_US_CLKS_SLOW           ( ( unsigned int ) 0x2 << 4 )  /* (USART) slow_clock (ARM) */
+#define     AT91C_US_CLKS_EXT            ( ( unsigned int ) 0x3 << 4 )  /* (USART) External (SCK) */
+#define AT91C_US_CHRL                    ( ( unsigned int ) 0x3 << 6 )  /* (USART) Clock Selection (Baud Rate generator Input Clock */
+#define     AT91C_US_CHRL_5_BITS         ( ( unsigned int ) 0x0 << 6 )  /* (USART) Character Length: 5 bits */
+#define     AT91C_US_CHRL_6_BITS         ( ( unsigned int ) 0x1 << 6 )  /* (USART) Character Length: 6 bits */
+#define     AT91C_US_CHRL_7_BITS         ( ( unsigned int ) 0x2 << 6 )  /* (USART) Character Length: 7 bits */
+#define     AT91C_US_CHRL_8_BITS         ( ( unsigned int ) 0x3 << 6 )  /* (USART) Character Length: 8 bits */
+#define AT91C_US_SYNC                    ( ( unsigned int ) 0x1 << 8 )  /* (USART) Synchronous Mode Select */
+#define AT91C_US_NBSTOP                  ( ( unsigned int ) 0x3 << 12 ) /* (USART) Number of Stop bits */
+#define     AT91C_US_NBSTOP_1_BIT        ( ( unsigned int ) 0x0 << 12 ) /* (USART) 1 stop bit */
+#define     AT91C_US_NBSTOP_15_BIT       ( ( unsigned int ) 0x1 << 12 ) /* (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits */
+#define     AT91C_US_NBSTOP_2_BIT        ( ( unsigned int ) 0x2 << 12 ) /* (USART) 2 stop bits */
+#define AT91C_US_MSBF                    ( ( unsigned int ) 0x1 << 16 ) /* (USART) Bit Order */
+#define AT91C_US_MODE9                   ( ( unsigned int ) 0x1 << 17 ) /* (USART) 9-bit Character length */
+#define AT91C_US_CKLO                    ( ( unsigned int ) 0x1 << 18 ) /* (USART) Clock Output Select */
+#define AT91C_US_OVER                    ( ( unsigned int ) 0x1 << 19 ) /* (USART) Over Sampling Mode */
+#define AT91C_US_INACK                   ( ( unsigned int ) 0x1 << 20 ) /* (USART) Inhibit Non Acknowledge */
+#define AT91C_US_DSNACK                  ( ( unsigned int ) 0x1 << 21 ) /* (USART) Disable Successive NACK */
+#define AT91C_US_MAX_ITER                ( ( unsigned int ) 0x1 << 24 ) /* (USART) Number of Repetitions */
+#define AT91C_US_FILTER                  ( ( unsigned int ) 0x1 << 28 ) /* (USART) Receive Line Filter */
+/* -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- */
+#define AT91C_US_RXBRK                   ( ( unsigned int ) 0x1 << 2 )  /* (USART) Break Received/End of Break */
+#define AT91C_US_TIMEOUT                 ( ( unsigned int ) 0x1 << 8 )  /* (USART) Receiver Time-out */
+#define AT91C_US_ITERATION               ( ( unsigned int ) 0x1 << 10 ) /* (USART) Max number of Repetitions Reached */
+#define AT91C_US_NACK                    ( ( unsigned int ) 0x1 << 13 ) /* (USART) Non Acknowledge */
+#define AT91C_US_RIIC                    ( ( unsigned int ) 0x1 << 16 ) /* (USART) Ring INdicator Input Change Flag */
+#define AT91C_US_DSRIC                   ( ( unsigned int ) 0x1 << 17 ) /* (USART) Data Set Ready Input Change Flag */
+#define AT91C_US_DCDIC                   ( ( unsigned int ) 0x1 << 18 ) /* (USART) Data Carrier Flag */
+#define AT91C_US_CTSIC                   ( ( unsigned int ) 0x1 << 19 ) /* (USART) Clear To Send Input Change Flag */
+/* -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- */
+/* -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- */
+/* -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- */
+#define AT91C_US_RI     ( ( unsigned int ) 0x1 << 20 )   /* (USART) Image of RI Input */
+#define AT91C_US_DSR    ( ( unsigned int ) 0x1 << 21 )   /* (USART) Image of DSR Input */
+#define AT91C_US_DCD    ( ( unsigned int ) 0x1 << 22 )   /* (USART) Image of DCD Input */
+#define AT91C_US_CTS    ( ( unsigned int ) 0x1 << 23 )   /* (USART) Image of CTS Input */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Two-wire Interface
-// *****************************************************************************
-typedef struct _AT91S_TWI {
-    AT91_REG     TWI_CR;    // Control Register
-    AT91_REG     TWI_MMR;   // Master Mode Register
-    AT91_REG     TWI_SMR;   // Slave Mode Register
-    AT91_REG     TWI_IADR;  // Internal Address Register
-    AT91_REG     TWI_CWGR;  // Clock Waveform Generator Register
-    AT91_REG     Reserved0[3];  //
-    AT91_REG     TWI_SR;    // Status Register
-    AT91_REG     TWI_IER;   // Interrupt Enable Register
-    AT91_REG     TWI_IDR;   // Interrupt Disable Register
-    AT91_REG     TWI_IMR;   // Interrupt Mask Register
-    AT91_REG     TWI_RHR;   // Receive Holding Register
-    AT91_REG     TWI_THR;   // Transmit Holding Register
-} AT91S_TWI, *AT91PS_TWI;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Two-wire Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_TWI
+{
+    AT91_REG TWI_CR;         /* Control Register */
+    AT91_REG TWI_MMR;        /* Master Mode Register */
+    AT91_REG TWI_SMR;        /* Slave Mode Register */
+    AT91_REG TWI_IADR;       /* Internal Address Register */
+    AT91_REG TWI_CWGR;       /* Clock Waveform Generator Register */
+    AT91_REG Reserved0[ 3 ]; /* */
+    AT91_REG TWI_SR;         /* Status Register */
+    AT91_REG TWI_IER;        /* Interrupt Enable Register */
+    AT91_REG TWI_IDR;        /* Interrupt Disable Register */
+    AT91_REG TWI_IMR;        /* Interrupt Mask Register */
+    AT91_REG TWI_RHR;        /* Receive Holding Register */
+    AT91_REG TWI_THR;        /* Transmit Holding Register */
+} AT91S_TWI, * AT91PS_TWI;
 
-// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
-#define AT91C_TWI_START       ((unsigned int) 0x1 <<  0) // (TWI) Send a START Condition
-#define AT91C_TWI_STOP        ((unsigned int) 0x1 <<  1) // (TWI) Send a STOP Condition
-#define AT91C_TWI_MSEN        ((unsigned int) 0x1 <<  2) // (TWI) TWI Master Transfer Enabled
-#define AT91C_TWI_MSDIS       ((unsigned int) 0x1 <<  3) // (TWI) TWI Master Transfer Disabled
-#define AT91C_TWI_SVEN        ((unsigned int) 0x1 <<  4) // (TWI) TWI Slave Transfer Enabled
-#define AT91C_TWI_SVDIS       ((unsigned int) 0x1 <<  5) // (TWI) TWI Slave Transfer Disabled
-#define AT91C_TWI_SWRST       ((unsigned int) 0x1 <<  7) // (TWI) Software Reset
-// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
-#define AT91C_TWI_IADRSZ      ((unsigned int) 0x3 <<  8) // (TWI) Internal Device Address Size
-#define     AT91C_TWI_IADRSZ_NO                   ((unsigned int) 0x0 <<  8) // (TWI) No internal device address
-#define     AT91C_TWI_IADRSZ_1_BYTE               ((unsigned int) 0x1 <<  8) // (TWI) One-byte internal device address
-#define     AT91C_TWI_IADRSZ_2_BYTE               ((unsigned int) 0x2 <<  8) // (TWI) Two-byte internal device address
-#define     AT91C_TWI_IADRSZ_3_BYTE               ((unsigned int) 0x3 <<  8) // (TWI) Three-byte internal device address
-#define AT91C_TWI_MREAD       ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction
-#define AT91C_TWI_DADR        ((unsigned int) 0x7F << 16) // (TWI) Device Address
-// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register --------
-#define AT91C_TWI_SADR        ((unsigned int) 0x7F << 16) // (TWI) Slave Device Address
-// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
-#define AT91C_TWI_CLDIV       ((unsigned int) 0xFF <<  0) // (TWI) Clock Low Divider
-#define AT91C_TWI_CHDIV       ((unsigned int) 0xFF <<  8) // (TWI) Clock High Divider
-#define AT91C_TWI_CKDIV       ((unsigned int) 0x7 << 16) // (TWI) Clock Divider
-// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
-#define AT91C_TWI_TXCOMP      ((unsigned int) 0x1 <<  0) // (TWI) Transmission Completed
-#define AT91C_TWI_RXRDY       ((unsigned int) 0x1 <<  1) // (TWI) Receive holding register ReaDY
-#define AT91C_TWI_TXRDY       ((unsigned int) 0x1 <<  2) // (TWI) Transmit holding register ReaDY
-#define AT91C_TWI_SVREAD      ((unsigned int) 0x1 <<  3) // (TWI) Slave Read
-#define AT91C_TWI_SVACC       ((unsigned int) 0x1 <<  4) // (TWI) Slave Access
-#define AT91C_TWI_GCACC       ((unsigned int) 0x1 <<  5) // (TWI) General Call Access
-#define AT91C_TWI_OVRE        ((unsigned int) 0x1 <<  6) // (TWI) Overrun Error
-#define AT91C_TWI_UNRE        ((unsigned int) 0x1 <<  7) // (TWI) Underrun Error
-#define AT91C_TWI_NACK        ((unsigned int) 0x1 <<  8) // (TWI) Not Acknowledged
-#define AT91C_TWI_ARBLST      ((unsigned int) 0x1 <<  9) // (TWI) Arbitration Lost
-// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
-// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
-// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
+/* -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- */
+#define AT91C_TWI_START                ( ( unsigned int ) 0x1 << 0 )   /* (TWI) Send a START Condition */
+#define AT91C_TWI_STOP                 ( ( unsigned int ) 0x1 << 1 )   /* (TWI) Send a STOP Condition */
+#define AT91C_TWI_MSEN                 ( ( unsigned int ) 0x1 << 2 )   /* (TWI) TWI Master Transfer Enabled */
+#define AT91C_TWI_MSDIS                ( ( unsigned int ) 0x1 << 3 )   /* (TWI) TWI Master Transfer Disabled */
+#define AT91C_TWI_SVEN                 ( ( unsigned int ) 0x1 << 4 )   /* (TWI) TWI Slave Transfer Enabled */
+#define AT91C_TWI_SVDIS                ( ( unsigned int ) 0x1 << 5 )   /* (TWI) TWI Slave Transfer Disabled */
+#define AT91C_TWI_SWRST                ( ( unsigned int ) 0x1 << 7 )   /* (TWI) Software Reset */
+/* -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- */
+#define AT91C_TWI_IADRSZ               ( ( unsigned int ) 0x3 << 8 )   /* (TWI) Internal Device Address Size */
+#define     AT91C_TWI_IADRSZ_NO        ( ( unsigned int ) 0x0 << 8 )   /* (TWI) No internal device address */
+#define     AT91C_TWI_IADRSZ_1_BYTE    ( ( unsigned int ) 0x1 << 8 )   /* (TWI) One-byte internal device address */
+#define     AT91C_TWI_IADRSZ_2_BYTE    ( ( unsigned int ) 0x2 << 8 )   /* (TWI) Two-byte internal device address */
+#define     AT91C_TWI_IADRSZ_3_BYTE    ( ( unsigned int ) 0x3 << 8 )   /* (TWI) Three-byte internal device address */
+#define AT91C_TWI_MREAD                ( ( unsigned int ) 0x1 << 12 )  /* (TWI) Master Read Direction */
+#define AT91C_TWI_DADR                 ( ( unsigned int ) 0x7F << 16 ) /* (TWI) Device Address */
+/* -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- */
+#define AT91C_TWI_SADR                 ( ( unsigned int ) 0x7F << 16 ) /* (TWI) Slave Device Address */
+/* -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- */
+#define AT91C_TWI_CLDIV                ( ( unsigned int ) 0xFF << 0 )  /* (TWI) Clock Low Divider */
+#define AT91C_TWI_CHDIV                ( ( unsigned int ) 0xFF << 8 )  /* (TWI) Clock High Divider */
+#define AT91C_TWI_CKDIV                ( ( unsigned int ) 0x7 << 16 )  /* (TWI) Clock Divider */
+/* -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- */
+#define AT91C_TWI_TXCOMP               ( ( unsigned int ) 0x1 << 0 )   /* (TWI) Transmission Completed */
+#define AT91C_TWI_RXRDY                ( ( unsigned int ) 0x1 << 1 )   /* (TWI) Receive holding register ReaDY */
+#define AT91C_TWI_TXRDY                ( ( unsigned int ) 0x1 << 2 )   /* (TWI) Transmit holding register ReaDY */
+#define AT91C_TWI_SVREAD               ( ( unsigned int ) 0x1 << 3 )   /* (TWI) Slave Read */
+#define AT91C_TWI_SVACC                ( ( unsigned int ) 0x1 << 4 )   /* (TWI) Slave Access */
+#define AT91C_TWI_GCACC                ( ( unsigned int ) 0x1 << 5 )   /* (TWI) General Call Access */
+#define AT91C_TWI_OVRE                 ( ( unsigned int ) 0x1 << 6 )   /* (TWI) Overrun Error */
+#define AT91C_TWI_UNRE                 ( ( unsigned int ) 0x1 << 7 )   /* (TWI) Underrun Error */
+#define AT91C_TWI_NACK                 ( ( unsigned int ) 0x1 << 8 )   /* (TWI) Not Acknowledged */
+#define AT91C_TWI_ARBLST               ( ( unsigned int ) 0x1 << 9 )   /* (TWI) Arbitration Lost */
+/* -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- */
+/* -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- */
+/* -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
-// *****************************************************************************
-typedef struct _AT91S_TC {
-    AT91_REG     TC_CCR;    // Channel Control Register
-    AT91_REG     TC_CMR;    // Channel Mode Register (Capture Mode / Waveform Mode)
-    AT91_REG     Reserved0[2];  //
-    AT91_REG     TC_CV;     // Counter Value
-    AT91_REG     TC_RA;     // Register A
-    AT91_REG     TC_RB;     // Register B
-    AT91_REG     TC_RC;     // Register C
-    AT91_REG     TC_SR;     // Status Register
-    AT91_REG     TC_IER;    // Interrupt Enable Register
-    AT91_REG     TC_IDR;    // Interrupt Disable Register
-    AT91_REG     TC_IMR;    // Interrupt Mask Register
-} AT91S_TC, *AT91PS_TC;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_TC
+{
+    AT91_REG TC_CCR;         /* Channel Control Register */
+    AT91_REG TC_CMR;         /* Channel Mode Register (Capture Mode / Waveform Mode) */
+    AT91_REG Reserved0[ 2 ]; /* */
+    AT91_REG TC_CV;          /* Counter Value */
+    AT91_REG TC_RA;          /* Register A */
+    AT91_REG TC_RB;          /* Register B */
+    AT91_REG TC_RC;          /* Register C */
+    AT91_REG TC_SR;          /* Status Register */
+    AT91_REG TC_IER;         /* Interrupt Enable Register */
+    AT91_REG TC_IDR;         /* Interrupt Disable Register */
+    AT91_REG TC_IMR;         /* Interrupt Mask Register */
+} AT91S_TC, * AT91PS_TC;
 
-// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
-#define AT91C_TC_CLKEN        ((unsigned int) 0x1 <<  0) // (TC) Counter Clock Enable Command
-#define AT91C_TC_CLKDIS       ((unsigned int) 0x1 <<  1) // (TC) Counter Clock Disable Command
-#define AT91C_TC_SWTRG        ((unsigned int) 0x1 <<  2) // (TC) Software Trigger Command
-// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
-#define AT91C_TC_CLKS         ((unsigned int) 0x7 <<  0) // (TC) Clock Selection
-#define     AT91C_TC_CLKS_TIMER_DIV1_CLOCK     ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
-#define     AT91C_TC_CLKS_TIMER_DIV2_CLOCK     ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
-#define     AT91C_TC_CLKS_TIMER_DIV3_CLOCK     ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
-#define     AT91C_TC_CLKS_TIMER_DIV4_CLOCK     ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
-#define     AT91C_TC_CLKS_TIMER_DIV5_CLOCK     ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
-#define     AT91C_TC_CLKS_XC0                  ((unsigned int) 0x5) // (TC) Clock selected: XC0
-#define     AT91C_TC_CLKS_XC1                  ((unsigned int) 0x6) // (TC) Clock selected: XC1
-#define     AT91C_TC_CLKS_XC2                  ((unsigned int) 0x7) // (TC) Clock selected: XC2
-#define AT91C_TC_CLKI         ((unsigned int) 0x1 <<  3) // (TC) Clock Invert
-#define AT91C_TC_BURST        ((unsigned int) 0x3 <<  4) // (TC) Burst Signal Selection
-#define     AT91C_TC_BURST_NONE                 ((unsigned int) 0x0 <<  4) // (TC) The clock is not gated by an external signal
-#define     AT91C_TC_BURST_XC0                  ((unsigned int) 0x1 <<  4) // (TC) XC0 is ANDed with the selected clock
-#define     AT91C_TC_BURST_XC1                  ((unsigned int) 0x2 <<  4) // (TC) XC1 is ANDed with the selected clock
-#define     AT91C_TC_BURST_XC2                  ((unsigned int) 0x3 <<  4) // (TC) XC2 is ANDed with the selected clock
-#define AT91C_TC_CPCSTOP      ((unsigned int) 0x1 <<  6) // (TC) Counter Clock Stopped with RC Compare
-#define AT91C_TC_LDBSTOP      ((unsigned int) 0x1 <<  6) // (TC) Counter Clock Stopped with RB Loading
-#define AT91C_TC_LDBDIS       ((unsigned int) 0x1 <<  7) // (TC) Counter Clock Disabled with RB Loading
-#define AT91C_TC_CPCDIS       ((unsigned int) 0x1 <<  7) // (TC) Counter Clock Disable with RC Compare
-#define AT91C_TC_ETRGEDG      ((unsigned int) 0x3 <<  8) // (TC) External Trigger Edge Selection
-#define     AT91C_TC_ETRGEDG_NONE                 ((unsigned int) 0x0 <<  8) // (TC) Edge: None
-#define     AT91C_TC_ETRGEDG_RISING               ((unsigned int) 0x1 <<  8) // (TC) Edge: rising edge
-#define     AT91C_TC_ETRGEDG_FALLING              ((unsigned int) 0x2 <<  8) // (TC) Edge: falling edge
-#define     AT91C_TC_ETRGEDG_BOTH                 ((unsigned int) 0x3 <<  8) // (TC) Edge: each edge
-#define AT91C_TC_EEVTEDG      ((unsigned int) 0x3 <<  8) // (TC) External Event Edge Selection
-#define     AT91C_TC_EEVTEDG_NONE                 ((unsigned int) 0x0 <<  8) // (TC) Edge: None
-#define     AT91C_TC_EEVTEDG_RISING               ((unsigned int) 0x1 <<  8) // (TC) Edge: rising edge
-#define     AT91C_TC_EEVTEDG_FALLING              ((unsigned int) 0x2 <<  8) // (TC) Edge: falling edge
-#define     AT91C_TC_EEVTEDG_BOTH                 ((unsigned int) 0x3 <<  8) // (TC) Edge: each edge
-#define AT91C_TC_ABETRG       ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
-#define AT91C_TC_EEVT         ((unsigned int) 0x3 << 10) // (TC) External Event  Selection
-#define     AT91C_TC_EEVT_NONE                 ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
-#define     AT91C_TC_EEVT_RISING               ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
-#define     AT91C_TC_EEVT_FALLING              ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
-#define     AT91C_TC_EEVT_BOTH                 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
-#define AT91C_TC_ENETRG       ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable
-#define AT91C_TC_WAVESEL      ((unsigned int) 0x3 << 13) // (TC) Waveform  Selection
-#define     AT91C_TC_WAVESEL_UP                   ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
-#define     AT91C_TC_WAVESEL_UPDOWN               ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
-#define     AT91C_TC_WAVESEL_UP_AUTO              ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
-#define     AT91C_TC_WAVESEL_UPDOWN_AUTO          ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
-#define AT91C_TC_CPCTRG       ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable
-#define AT91C_TC_WAVE         ((unsigned int) 0x1 << 15) // (TC)
-#define AT91C_TC_LDRA         ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection
-#define     AT91C_TC_LDRA_NONE                 ((unsigned int) 0x0 << 16) // (TC) Edge: None
-#define     AT91C_TC_LDRA_RISING               ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA
-#define     AT91C_TC_LDRA_FALLING              ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA
-#define     AT91C_TC_LDRA_BOTH                 ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_ACPA         ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA
-#define     AT91C_TC_ACPA_NONE                 ((unsigned int) 0x0 << 16) // (TC) Effect: none
-#define     AT91C_TC_ACPA_SET                  ((unsigned int) 0x1 << 16) // (TC) Effect: set
-#define     AT91C_TC_ACPA_CLEAR                ((unsigned int) 0x2 << 16) // (TC) Effect: clear
-#define     AT91C_TC_ACPA_TOGGLE               ((unsigned int) 0x3 << 16) // (TC) Effect: toggle
-#define AT91C_TC_LDRB         ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection
-#define     AT91C_TC_LDRB_NONE                 ((unsigned int) 0x0 << 18) // (TC) Edge: None
-#define     AT91C_TC_LDRB_RISING               ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA
-#define     AT91C_TC_LDRB_FALLING              ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA
-#define     AT91C_TC_LDRB_BOTH                 ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_ACPC         ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA
-#define     AT91C_TC_ACPC_NONE                 ((unsigned int) 0x0 << 18) // (TC) Effect: none
-#define     AT91C_TC_ACPC_SET                  ((unsigned int) 0x1 << 18) // (TC) Effect: set
-#define     AT91C_TC_ACPC_CLEAR                ((unsigned int) 0x2 << 18) // (TC) Effect: clear
-#define     AT91C_TC_ACPC_TOGGLE               ((unsigned int) 0x3 << 18) // (TC) Effect: toggle
-#define AT91C_TC_AEEVT        ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA
-#define     AT91C_TC_AEEVT_NONE                 ((unsigned int) 0x0 << 20) // (TC) Effect: none
-#define     AT91C_TC_AEEVT_SET                  ((unsigned int) 0x1 << 20) // (TC) Effect: set
-#define     AT91C_TC_AEEVT_CLEAR                ((unsigned int) 0x2 << 20) // (TC) Effect: clear
-#define     AT91C_TC_AEEVT_TOGGLE               ((unsigned int) 0x3 << 20) // (TC) Effect: toggle
-#define AT91C_TC_ASWTRG       ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA
-#define     AT91C_TC_ASWTRG_NONE                 ((unsigned int) 0x0 << 22) // (TC) Effect: none
-#define     AT91C_TC_ASWTRG_SET                  ((unsigned int) 0x1 << 22) // (TC) Effect: set
-#define     AT91C_TC_ASWTRG_CLEAR                ((unsigned int) 0x2 << 22) // (TC) Effect: clear
-#define     AT91C_TC_ASWTRG_TOGGLE               ((unsigned int) 0x3 << 22) // (TC) Effect: toggle
-#define AT91C_TC_BCPB         ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB
-#define     AT91C_TC_BCPB_NONE                 ((unsigned int) 0x0 << 24) // (TC) Effect: none
-#define     AT91C_TC_BCPB_SET                  ((unsigned int) 0x1 << 24) // (TC) Effect: set
-#define     AT91C_TC_BCPB_CLEAR                ((unsigned int) 0x2 << 24) // (TC) Effect: clear
-#define     AT91C_TC_BCPB_TOGGLE               ((unsigned int) 0x3 << 24) // (TC) Effect: toggle
-#define AT91C_TC_BCPC         ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB
-#define     AT91C_TC_BCPC_NONE                 ((unsigned int) 0x0 << 26) // (TC) Effect: none
-#define     AT91C_TC_BCPC_SET                  ((unsigned int) 0x1 << 26) // (TC) Effect: set
-#define     AT91C_TC_BCPC_CLEAR                ((unsigned int) 0x2 << 26) // (TC) Effect: clear
-#define     AT91C_TC_BCPC_TOGGLE               ((unsigned int) 0x3 << 26) // (TC) Effect: toggle
-#define AT91C_TC_BEEVT        ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB
-#define     AT91C_TC_BEEVT_NONE                 ((unsigned int) 0x0 << 28) // (TC) Effect: none
-#define     AT91C_TC_BEEVT_SET                  ((unsigned int) 0x1 << 28) // (TC) Effect: set
-#define     AT91C_TC_BEEVT_CLEAR                ((unsigned int) 0x2 << 28) // (TC) Effect: clear
-#define     AT91C_TC_BEEVT_TOGGLE               ((unsigned int) 0x3 << 28) // (TC) Effect: toggle
-#define AT91C_TC_BSWTRG       ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB
-#define     AT91C_TC_BSWTRG_NONE                 ((unsigned int) 0x0 << 30) // (TC) Effect: none
-#define     AT91C_TC_BSWTRG_SET                  ((unsigned int) 0x1 << 30) // (TC) Effect: set
-#define     AT91C_TC_BSWTRG_CLEAR                ((unsigned int) 0x2 << 30) // (TC) Effect: clear
-#define     AT91C_TC_BSWTRG_TOGGLE               ((unsigned int) 0x3 << 30) // (TC) Effect: toggle
-// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
-#define AT91C_TC_COVFS        ((unsigned int) 0x1 <<  0) // (TC) Counter Overflow
-#define AT91C_TC_LOVRS        ((unsigned int) 0x1 <<  1) // (TC) Load Overrun
-#define AT91C_TC_CPAS         ((unsigned int) 0x1 <<  2) // (TC) RA Compare
-#define AT91C_TC_CPBS         ((unsigned int) 0x1 <<  3) // (TC) RB Compare
-#define AT91C_TC_CPCS         ((unsigned int) 0x1 <<  4) // (TC) RC Compare
-#define AT91C_TC_LDRAS        ((unsigned int) 0x1 <<  5) // (TC) RA Loading
-#define AT91C_TC_LDRBS        ((unsigned int) 0x1 <<  6) // (TC) RB Loading
-#define AT91C_TC_ETRCS        ((unsigned int) 0x1 <<  7) // (TC) External Trigger
-#define AT91C_TC_ETRGS        ((unsigned int) 0x1 << 16) // (TC) Clock Enabling
-#define AT91C_TC_MTIOA        ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror
-#define AT91C_TC_MTIOB        ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror
-// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
-// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
-// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
+/* -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- */
+#define AT91C_TC_CLKEN                        ( ( unsigned int ) 0x1 << 0 )  /* (TC) Counter Clock Enable Command */
+#define AT91C_TC_CLKDIS                       ( ( unsigned int ) 0x1 << 1 )  /* (TC) Counter Clock Disable Command */
+#define AT91C_TC_SWTRG                        ( ( unsigned int ) 0x1 << 2 )  /* (TC) Software Trigger Command */
+/* -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- */
+#define AT91C_TC_CLKS                         ( ( unsigned int ) 0x7 << 0 )  /* (TC) Clock Selection */
+#define     AT91C_TC_CLKS_TIMER_DIV1_CLOCK    ( ( unsigned int ) 0x0 )       /* (TC) Clock selected: TIMER_DIV1_CLOCK */
+#define     AT91C_TC_CLKS_TIMER_DIV2_CLOCK    ( ( unsigned int ) 0x1 )       /* (TC) Clock selected: TIMER_DIV2_CLOCK */
+#define     AT91C_TC_CLKS_TIMER_DIV3_CLOCK    ( ( unsigned int ) 0x2 )       /* (TC) Clock selected: TIMER_DIV3_CLOCK */
+#define     AT91C_TC_CLKS_TIMER_DIV4_CLOCK    ( ( unsigned int ) 0x3 )       /* (TC) Clock selected: TIMER_DIV4_CLOCK */
+#define     AT91C_TC_CLKS_TIMER_DIV5_CLOCK    ( ( unsigned int ) 0x4 )       /* (TC) Clock selected: TIMER_DIV5_CLOCK */
+#define     AT91C_TC_CLKS_XC0                 ( ( unsigned int ) 0x5 )       /* (TC) Clock selected: XC0 */
+#define     AT91C_TC_CLKS_XC1                 ( ( unsigned int ) 0x6 )       /* (TC) Clock selected: XC1 */
+#define     AT91C_TC_CLKS_XC2                 ( ( unsigned int ) 0x7 )       /* (TC) Clock selected: XC2 */
+#define AT91C_TC_CLKI                         ( ( unsigned int ) 0x1 << 3 )  /* (TC) Clock Invert */
+#define AT91C_TC_BURST                        ( ( unsigned int ) 0x3 << 4 )  /* (TC) Burst Signal Selection */
+#define     AT91C_TC_BURST_NONE               ( ( unsigned int ) 0x0 << 4 )  /* (TC) The clock is not gated by an external signal */
+#define     AT91C_TC_BURST_XC0                ( ( unsigned int ) 0x1 << 4 )  /* (TC) XC0 is ANDed with the selected clock */
+#define     AT91C_TC_BURST_XC1                ( ( unsigned int ) 0x2 << 4 )  /* (TC) XC1 is ANDed with the selected clock */
+#define     AT91C_TC_BURST_XC2                ( ( unsigned int ) 0x3 << 4 )  /* (TC) XC2 is ANDed with the selected clock */
+#define AT91C_TC_CPCSTOP                      ( ( unsigned int ) 0x1 << 6 )  /* (TC) Counter Clock Stopped with RC Compare */
+#define AT91C_TC_LDBSTOP                      ( ( unsigned int ) 0x1 << 6 )  /* (TC) Counter Clock Stopped with RB Loading */
+#define AT91C_TC_LDBDIS                       ( ( unsigned int ) 0x1 << 7 )  /* (TC) Counter Clock Disabled with RB Loading */
+#define AT91C_TC_CPCDIS                       ( ( unsigned int ) 0x1 << 7 )  /* (TC) Counter Clock Disable with RC Compare */
+#define AT91C_TC_ETRGEDG                      ( ( unsigned int ) 0x3 << 8 )  /* (TC) External Trigger Edge Selection */
+#define     AT91C_TC_ETRGEDG_NONE             ( ( unsigned int ) 0x0 << 8 )  /* (TC) Edge: None */
+#define     AT91C_TC_ETRGEDG_RISING           ( ( unsigned int ) 0x1 << 8 )  /* (TC) Edge: rising edge */
+#define     AT91C_TC_ETRGEDG_FALLING          ( ( unsigned int ) 0x2 << 8 )  /* (TC) Edge: falling edge */
+#define     AT91C_TC_ETRGEDG_BOTH             ( ( unsigned int ) 0x3 << 8 )  /* (TC) Edge: each edge */
+#define AT91C_TC_EEVTEDG                      ( ( unsigned int ) 0x3 << 8 )  /* (TC) External Event Edge Selection */
+#define     AT91C_TC_EEVTEDG_NONE             ( ( unsigned int ) 0x0 << 8 )  /* (TC) Edge: None */
+#define     AT91C_TC_EEVTEDG_RISING           ( ( unsigned int ) 0x1 << 8 )  /* (TC) Edge: rising edge */
+#define     AT91C_TC_EEVTEDG_FALLING          ( ( unsigned int ) 0x2 << 8 )  /* (TC) Edge: falling edge */
+#define     AT91C_TC_EEVTEDG_BOTH             ( ( unsigned int ) 0x3 << 8 )  /* (TC) Edge: each edge */
+#define AT91C_TC_ABETRG                       ( ( unsigned int ) 0x1 << 10 ) /* (TC) TIOA or TIOB External Trigger Selection */
+#define AT91C_TC_EEVT                         ( ( unsigned int ) 0x3 << 10 ) /* (TC) External Event  Selection */
+#define     AT91C_TC_EEVT_NONE                ( ( unsigned int ) 0x0 << 10 ) /* (TC) Signal selected as external event: TIOB TIOB direction: input */
+#define     AT91C_TC_EEVT_RISING              ( ( unsigned int ) 0x1 << 10 ) /* (TC) Signal selected as external event: XC0 TIOB direction: output */
+#define     AT91C_TC_EEVT_FALLING             ( ( unsigned int ) 0x2 << 10 ) /* (TC) Signal selected as external event: XC1 TIOB direction: output */
+#define     AT91C_TC_EEVT_BOTH                ( ( unsigned int ) 0x3 << 10 ) /* (TC) Signal selected as external event: XC2 TIOB direction: output */
+#define AT91C_TC_ENETRG                       ( ( unsigned int ) 0x1 << 12 ) /* (TC) External Event Trigger enable */
+#define AT91C_TC_WAVESEL                      ( ( unsigned int ) 0x3 << 13 ) /* (TC) Waveform  Selection */
+#define     AT91C_TC_WAVESEL_UP               ( ( unsigned int ) 0x0 << 13 ) /* (TC) UP mode without atomatic trigger on RC Compare */
+#define     AT91C_TC_WAVESEL_UPDOWN           ( ( unsigned int ) 0x1 << 13 ) /* (TC) UPDOWN mode without automatic trigger on RC Compare */
+#define     AT91C_TC_WAVESEL_UP_AUTO          ( ( unsigned int ) 0x2 << 13 ) /* (TC) UP mode with automatic trigger on RC Compare */
+#define     AT91C_TC_WAVESEL_UPDOWN_AUTO      ( ( unsigned int ) 0x3 << 13 ) /* (TC) UPDOWN mode with automatic trigger on RC Compare */
+#define AT91C_TC_CPCTRG                       ( ( unsigned int ) 0x1 << 14 ) /* (TC) RC Compare Trigger Enable */
+#define AT91C_TC_WAVE                         ( ( unsigned int ) 0x1 << 15 ) /* (TC) */
+#define AT91C_TC_LDRA                         ( ( unsigned int ) 0x3 << 16 ) /* (TC) RA Loading Selection */
+#define     AT91C_TC_LDRA_NONE                ( ( unsigned int ) 0x0 << 16 ) /* (TC) Edge: None */
+#define     AT91C_TC_LDRA_RISING              ( ( unsigned int ) 0x1 << 16 ) /* (TC) Edge: rising edge of TIOA */
+#define     AT91C_TC_LDRA_FALLING             ( ( unsigned int ) 0x2 << 16 ) /* (TC) Edge: falling edge of TIOA */
+#define     AT91C_TC_LDRA_BOTH                ( ( unsigned int ) 0x3 << 16 ) /* (TC) Edge: each edge of TIOA */
+#define AT91C_TC_ACPA                         ( ( unsigned int ) 0x3 << 16 ) /* (TC) RA Compare Effect on TIOA */
+#define     AT91C_TC_ACPA_NONE                ( ( unsigned int ) 0x0 << 16 ) /* (TC) Effect: none */
+#define     AT91C_TC_ACPA_SET                 ( ( unsigned int ) 0x1 << 16 ) /* (TC) Effect: set */
+#define     AT91C_TC_ACPA_CLEAR               ( ( unsigned int ) 0x2 << 16 ) /* (TC) Effect: clear */
+#define     AT91C_TC_ACPA_TOGGLE              ( ( unsigned int ) 0x3 << 16 ) /* (TC) Effect: toggle */
+#define AT91C_TC_LDRB                         ( ( unsigned int ) 0x3 << 18 ) /* (TC) RB Loading Selection */
+#define     AT91C_TC_LDRB_NONE                ( ( unsigned int ) 0x0 << 18 ) /* (TC) Edge: None */
+#define     AT91C_TC_LDRB_RISING              ( ( unsigned int ) 0x1 << 18 ) /* (TC) Edge: rising edge of TIOA */
+#define     AT91C_TC_LDRB_FALLING             ( ( unsigned int ) 0x2 << 18 ) /* (TC) Edge: falling edge of TIOA */
+#define     AT91C_TC_LDRB_BOTH                ( ( unsigned int ) 0x3 << 18 ) /* (TC) Edge: each edge of TIOA */
+#define AT91C_TC_ACPC                         ( ( unsigned int ) 0x3 << 18 ) /* (TC) RC Compare Effect on TIOA */
+#define     AT91C_TC_ACPC_NONE                ( ( unsigned int ) 0x0 << 18 ) /* (TC) Effect: none */
+#define     AT91C_TC_ACPC_SET                 ( ( unsigned int ) 0x1 << 18 ) /* (TC) Effect: set */
+#define     AT91C_TC_ACPC_CLEAR               ( ( unsigned int ) 0x2 << 18 ) /* (TC) Effect: clear */
+#define     AT91C_TC_ACPC_TOGGLE              ( ( unsigned int ) 0x3 << 18 ) /* (TC) Effect: toggle */
+#define AT91C_TC_AEEVT                        ( ( unsigned int ) 0x3 << 20 ) /* (TC) External Event Effect on TIOA */
+#define     AT91C_TC_AEEVT_NONE               ( ( unsigned int ) 0x0 << 20 ) /* (TC) Effect: none */
+#define     AT91C_TC_AEEVT_SET                ( ( unsigned int ) 0x1 << 20 ) /* (TC) Effect: set */
+#define     AT91C_TC_AEEVT_CLEAR              ( ( unsigned int ) 0x2 << 20 ) /* (TC) Effect: clear */
+#define     AT91C_TC_AEEVT_TOGGLE             ( ( unsigned int ) 0x3 << 20 ) /* (TC) Effect: toggle */
+#define AT91C_TC_ASWTRG                       ( ( unsigned int ) 0x3 << 22 ) /* (TC) Software Trigger Effect on TIOA */
+#define     AT91C_TC_ASWTRG_NONE              ( ( unsigned int ) 0x0 << 22 ) /* (TC) Effect: none */
+#define     AT91C_TC_ASWTRG_SET               ( ( unsigned int ) 0x1 << 22 ) /* (TC) Effect: set */
+#define     AT91C_TC_ASWTRG_CLEAR             ( ( unsigned int ) 0x2 << 22 ) /* (TC) Effect: clear */
+#define     AT91C_TC_ASWTRG_TOGGLE            ( ( unsigned int ) 0x3 << 22 ) /* (TC) Effect: toggle */
+#define AT91C_TC_BCPB                         ( ( unsigned int ) 0x3 << 24 ) /* (TC) RB Compare Effect on TIOB */
+#define     AT91C_TC_BCPB_NONE                ( ( unsigned int ) 0x0 << 24 ) /* (TC) Effect: none */
+#define     AT91C_TC_BCPB_SET                 ( ( unsigned int ) 0x1 << 24 ) /* (TC) Effect: set */
+#define     AT91C_TC_BCPB_CLEAR               ( ( unsigned int ) 0x2 << 24 ) /* (TC) Effect: clear */
+#define     AT91C_TC_BCPB_TOGGLE              ( ( unsigned int ) 0x3 << 24 ) /* (TC) Effect: toggle */
+#define AT91C_TC_BCPC                         ( ( unsigned int ) 0x3 << 26 ) /* (TC) RC Compare Effect on TIOB */
+#define     AT91C_TC_BCPC_NONE                ( ( unsigned int ) 0x0 << 26 ) /* (TC) Effect: none */
+#define     AT91C_TC_BCPC_SET                 ( ( unsigned int ) 0x1 << 26 ) /* (TC) Effect: set */
+#define     AT91C_TC_BCPC_CLEAR               ( ( unsigned int ) 0x2 << 26 ) /* (TC) Effect: clear */
+#define     AT91C_TC_BCPC_TOGGLE              ( ( unsigned int ) 0x3 << 26 ) /* (TC) Effect: toggle */
+#define AT91C_TC_BEEVT                        ( ( unsigned int ) 0x3 << 28 ) /* (TC) External Event Effect on TIOB */
+#define     AT91C_TC_BEEVT_NONE               ( ( unsigned int ) 0x0 << 28 ) /* (TC) Effect: none */
+#define     AT91C_TC_BEEVT_SET                ( ( unsigned int ) 0x1 << 28 ) /* (TC) Effect: set */
+#define     AT91C_TC_BEEVT_CLEAR              ( ( unsigned int ) 0x2 << 28 ) /* (TC) Effect: clear */
+#define     AT91C_TC_BEEVT_TOGGLE             ( ( unsigned int ) 0x3 << 28 ) /* (TC) Effect: toggle */
+#define AT91C_TC_BSWTRG                       ( ( unsigned int ) 0x3 << 30 ) /* (TC) Software Trigger Effect on TIOB */
+#define     AT91C_TC_BSWTRG_NONE              ( ( unsigned int ) 0x0 << 30 ) /* (TC) Effect: none */
+#define     AT91C_TC_BSWTRG_SET               ( ( unsigned int ) 0x1 << 30 ) /* (TC) Effect: set */
+#define     AT91C_TC_BSWTRG_CLEAR             ( ( unsigned int ) 0x2 << 30 ) /* (TC) Effect: clear */
+#define     AT91C_TC_BSWTRG_TOGGLE            ( ( unsigned int ) 0x3 << 30 ) /* (TC) Effect: toggle */
+/* -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- */
+#define AT91C_TC_COVFS                        ( ( unsigned int ) 0x1 << 0 )  /* (TC) Counter Overflow */
+#define AT91C_TC_LOVRS                        ( ( unsigned int ) 0x1 << 1 )  /* (TC) Load Overrun */
+#define AT91C_TC_CPAS                         ( ( unsigned int ) 0x1 << 2 )  /* (TC) RA Compare */
+#define AT91C_TC_CPBS                         ( ( unsigned int ) 0x1 << 3 )  /* (TC) RB Compare */
+#define AT91C_TC_CPCS                         ( ( unsigned int ) 0x1 << 4 )  /* (TC) RC Compare */
+#define AT91C_TC_LDRAS                        ( ( unsigned int ) 0x1 << 5 )  /* (TC) RA Loading */
+#define AT91C_TC_LDRBS                        ( ( unsigned int ) 0x1 << 6 )  /* (TC) RB Loading */
+#define AT91C_TC_ETRCS                        ( ( unsigned int ) 0x1 << 7 )  /* (TC) External Trigger */
+#define AT91C_TC_ETRGS                        ( ( unsigned int ) 0x1 << 16 ) /* (TC) Clock Enabling */
+#define AT91C_TC_MTIOA                        ( ( unsigned int ) 0x1 << 17 ) /* (TC) TIOA Mirror */
+#define AT91C_TC_MTIOB                        ( ( unsigned int ) 0x1 << 18 ) /* (TC) TIOA Mirror */
+/* -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- */
+/* -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- */
+/* -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Timer Counter Interface
-// *****************************************************************************
-typedef struct _AT91S_TCB {
-    AT91S_TC     TCB_TC0;   // TC Channel 0
-    AT91_REG     Reserved0[4];  //
-    AT91S_TC     TCB_TC1;   // TC Channel 1
-    AT91_REG     Reserved1[4];  //
-    AT91S_TC     TCB_TC2;   // TC Channel 2
-    AT91_REG     Reserved2[4];  //
-    AT91_REG     TCB_BCR;   // TC Block Control Register
-    AT91_REG     TCB_BMR;   // TC Block Mode Register
-} AT91S_TCB, *AT91PS_TCB;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Timer Counter Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_TCB
+{
+    AT91S_TC TCB_TC0;        /* TC Channel 0 */
+    AT91_REG Reserved0[ 4 ]; /* */
+    AT91S_TC TCB_TC1;        /* TC Channel 1 */
+    AT91_REG Reserved1[ 4 ]; /* */
+    AT91S_TC TCB_TC2;        /* TC Channel 2 */
+    AT91_REG Reserved2[ 4 ]; /* */
+    AT91_REG TCB_BCR;        /* TC Block Control Register */
+    AT91_REG TCB_BMR;        /* TC Block Mode Register */
+} AT91S_TCB, * AT91PS_TCB;
 
-// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
-#define AT91C_TCB_SYNC        ((unsigned int) 0x1 <<  0) // (TCB) Synchro Command
-// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
-#define AT91C_TCB_TC0XC0S     ((unsigned int) 0x1 <<  0) // (TCB) External Clock Signal 0 Selection
-#define     AT91C_TCB_TC0XC0S_TCLK0                ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0
-#define     AT91C_TCB_TC0XC0S_NONE                 ((unsigned int) 0x1) // (TCB) None signal connected to XC0
-#define     AT91C_TCB_TC0XC0S_TIOA1                ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0
-#define     AT91C_TCB_TC0XC0S_TIOA2                ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0
-#define AT91C_TCB_TC1XC1S     ((unsigned int) 0x1 <<  2) // (TCB) External Clock Signal 1 Selection
-#define     AT91C_TCB_TC1XC1S_TCLK1                ((unsigned int) 0x0 <<  2) // (TCB) TCLK1 connected to XC1
-#define     AT91C_TCB_TC1XC1S_NONE                 ((unsigned int) 0x1 <<  2) // (TCB) None signal connected to XC1
-#define     AT91C_TCB_TC1XC1S_TIOA0                ((unsigned int) 0x2 <<  2) // (TCB) TIOA0 connected to XC1
-#define     AT91C_TCB_TC1XC1S_TIOA2                ((unsigned int) 0x3 <<  2) // (TCB) TIOA2 connected to XC1
-#define AT91C_TCB_TC2XC2S     ((unsigned int) 0x1 <<  4) // (TCB) External Clock Signal 2 Selection
-#define     AT91C_TCB_TC2XC2S_TCLK2                ((unsigned int) 0x0 <<  4) // (TCB) TCLK2 connected to XC2
-#define     AT91C_TCB_TC2XC2S_NONE                 ((unsigned int) 0x1 <<  4) // (TCB) None signal connected to XC2
-#define     AT91C_TCB_TC2XC2S_TIOA0                ((unsigned int) 0x2 <<  4) // (TCB) TIOA0 connected to XC2
-#define     AT91C_TCB_TC2XC2S_TIOA2                ((unsigned int) 0x3 <<  4) // (TCB) TIOA2 connected to XC2
+/* -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- */
+#define AT91C_TCB_SYNC                 ( ( unsigned int ) 0x1 << 0 ) /* (TCB) Synchro Command */
+/* -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- */
+#define AT91C_TCB_TC0XC0S              ( ( unsigned int ) 0x1 << 0 ) /* (TCB) External Clock Signal 0 Selection */
+#define     AT91C_TCB_TC0XC0S_TCLK0    ( ( unsigned int ) 0x0 )      /* (TCB) TCLK0 connected to XC0 */
+#define     AT91C_TCB_TC0XC0S_NONE     ( ( unsigned int ) 0x1 )      /* (TCB) None signal connected to XC0 */
+#define     AT91C_TCB_TC0XC0S_TIOA1    ( ( unsigned int ) 0x2 )      /* (TCB) TIOA1 connected to XC0 */
+#define     AT91C_TCB_TC0XC0S_TIOA2    ( ( unsigned int ) 0x3 )      /* (TCB) TIOA2 connected to XC0 */
+#define AT91C_TCB_TC1XC1S              ( ( unsigned int ) 0x1 << 2 ) /* (TCB) External Clock Signal 1 Selection */
+#define     AT91C_TCB_TC1XC1S_TCLK1    ( ( unsigned int ) 0x0 << 2 ) /* (TCB) TCLK1 connected to XC1 */
+#define     AT91C_TCB_TC1XC1S_NONE     ( ( unsigned int ) 0x1 << 2 ) /* (TCB) None signal connected to XC1 */
+#define     AT91C_TCB_TC1XC1S_TIOA0    ( ( unsigned int ) 0x2 << 2 ) /* (TCB) TIOA0 connected to XC1 */
+#define     AT91C_TCB_TC1XC1S_TIOA2    ( ( unsigned int ) 0x3 << 2 ) /* (TCB) TIOA2 connected to XC1 */
+#define AT91C_TCB_TC2XC2S              ( ( unsigned int ) 0x1 << 4 ) /* (TCB) External Clock Signal 2 Selection */
+#define     AT91C_TCB_TC2XC2S_TCLK2    ( ( unsigned int ) 0x0 << 4 ) /* (TCB) TCLK2 connected to XC2 */
+#define     AT91C_TCB_TC2XC2S_NONE     ( ( unsigned int ) 0x1 << 4 ) /* (TCB) None signal connected to XC2 */
+#define     AT91C_TCB_TC2XC2S_TIOA0    ( ( unsigned int ) 0x2 << 4 ) /* (TCB) TIOA0 connected to XC2 */
+#define     AT91C_TCB_TC2XC2S_TIOA2    ( ( unsigned int ) 0x3 << 4 ) /* (TCB) TIOA2 connected to XC2 */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR PWMC Channel Interface
-// *****************************************************************************
-typedef struct _AT91S_PWMC_CH {
-    AT91_REG     PWMC_CMR;  // Channel Mode Register
-    AT91_REG     PWMC_CDTYR;    // Channel Duty Cycle Register
-    AT91_REG     PWMC_CPRDR;    // Channel Period Register
-    AT91_REG     PWMC_CCNTR;    // Channel Counter Register
-    AT91_REG     PWMC_CUPDR;    // Channel Update Register
-    AT91_REG     PWMC_Reserved[3];  // Reserved
-} AT91S_PWMC_CH, *AT91PS_PWMC_CH;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR PWMC Channel Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_PWMC_CH
+{
+    AT91_REG PWMC_CMR;           /* Channel Mode Register */
+    AT91_REG PWMC_CDTYR;         /* Channel Duty Cycle Register */
+    AT91_REG PWMC_CPRDR;         /* Channel Period Register */
+    AT91_REG PWMC_CCNTR;         /* Channel Counter Register */
+    AT91_REG PWMC_CUPDR;         /* Channel Update Register */
+    AT91_REG PWMC_Reserved[ 3 ]; /* Reserved */
+} AT91S_PWMC_CH, * AT91PS_PWMC_CH;
 
-// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
-#define AT91C_PWMC_CPRE       ((unsigned int) 0xF <<  0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
-#define     AT91C_PWMC_CPRE_MCK                  ((unsigned int) 0x0) // (PWMC_CH)
-#define     AT91C_PWMC_CPRE_MCKA                 ((unsigned int) 0xB) // (PWMC_CH)
-#define     AT91C_PWMC_CPRE_MCKB                 ((unsigned int) 0xC) // (PWMC_CH)
-#define AT91C_PWMC_CALG       ((unsigned int) 0x1 <<  8) // (PWMC_CH) Channel Alignment
-#define AT91C_PWMC_CPOL       ((unsigned int) 0x1 <<  9) // (PWMC_CH) Channel Polarity
-#define AT91C_PWMC_CPD        ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period
-// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
-#define AT91C_PWMC_CDTY       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Duty Cycle
-// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
-#define AT91C_PWMC_CPRD       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Period
-// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
-#define AT91C_PWMC_CCNT       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Counter
-// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
-#define AT91C_PWMC_CUPD       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Update
+/* -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- */
+#define AT91C_PWMC_CPRE             ( ( unsigned int ) 0xF << 0 )  /* (PWMC_CH) Channel Pre-scaler : PWMC_CLKx */
+#define     AT91C_PWMC_CPRE_MCK     ( ( unsigned int ) 0x0 )       /* (PWMC_CH) */
+#define     AT91C_PWMC_CPRE_MCKA    ( ( unsigned int ) 0xB )       /* (PWMC_CH) */
+#define     AT91C_PWMC_CPRE_MCKB    ( ( unsigned int ) 0xC )       /* (PWMC_CH) */
+#define AT91C_PWMC_CALG             ( ( unsigned int ) 0x1 << 8 )  /* (PWMC_CH) Channel Alignment */
+#define AT91C_PWMC_CPOL             ( ( unsigned int ) 0x1 << 9 )  /* (PWMC_CH) Channel Polarity */
+#define AT91C_PWMC_CPD              ( ( unsigned int ) 0x1 << 10 ) /* (PWMC_CH) Channel Update Period */
+/* -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- */
+#define AT91C_PWMC_CDTY             ( ( unsigned int ) 0x0 << 0 )  /* (PWMC_CH) Channel Duty Cycle */
+/* -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- */
+#define AT91C_PWMC_CPRD             ( ( unsigned int ) 0x0 << 0 )  /* (PWMC_CH) Channel Period */
+/* -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- */
+#define AT91C_PWMC_CCNT             ( ( unsigned int ) 0x0 << 0 )  /* (PWMC_CH) Channel Counter */
+/* -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- */
+#define AT91C_PWMC_CUPD             ( ( unsigned int ) 0x0 << 0 )  /* (PWMC_CH) Channel Update */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_PWMC {
-    AT91_REG     PWMC_MR;   // PWMC Mode Register
-    AT91_REG     PWMC_ENA;  // PWMC Enable Register
-    AT91_REG     PWMC_DIS;  // PWMC Disable Register
-    AT91_REG     PWMC_SR;   // PWMC Status Register
-    AT91_REG     PWMC_IER;  // PWMC Interrupt Enable Register
-    AT91_REG     PWMC_IDR;  // PWMC Interrupt Disable Register
-    AT91_REG     PWMC_IMR;  // PWMC Interrupt Mask Register
-    AT91_REG     PWMC_ISR;  // PWMC Interrupt Status Register
-    AT91_REG     Reserved0[55];     //
-    AT91_REG     PWMC_VR;   // PWMC Version Register
-    AT91_REG     Reserved1[64];     //
-    AT91S_PWMC_CH    PWMC_CH[32];   // PWMC Channel 0
-} AT91S_PWMC, *AT91PS_PWMC;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_PWMC
+{
+    AT91_REG PWMC_MR;            /* PWMC Mode Register */
+    AT91_REG PWMC_ENA;           /* PWMC Enable Register */
+    AT91_REG PWMC_DIS;           /* PWMC Disable Register */
+    AT91_REG PWMC_SR;            /* PWMC Status Register */
+    AT91_REG PWMC_IER;           /* PWMC Interrupt Enable Register */
+    AT91_REG PWMC_IDR;           /* PWMC Interrupt Disable Register */
+    AT91_REG PWMC_IMR;           /* PWMC Interrupt Mask Register */
+    AT91_REG PWMC_ISR;           /* PWMC Interrupt Status Register */
+    AT91_REG Reserved0[ 55 ];    /* */
+    AT91_REG PWMC_VR;            /* PWMC Version Register */
+    AT91_REG Reserved1[ 64 ];    /* */
+    AT91S_PWMC_CH PWMC_CH[ 32 ]; /* PWMC Channel 0 */
+} AT91S_PWMC, * AT91PS_PWMC;
 
-// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
-#define AT91C_PWMC_DIVA       ((unsigned int) 0xFF <<  0) // (PWMC) CLKA divide factor.
-#define AT91C_PWMC_PREA       ((unsigned int) 0xF <<  8) // (PWMC) Divider Input Clock Prescaler A
-#define     AT91C_PWMC_PREA_MCK                  ((unsigned int) 0x0 <<  8) // (PWMC)
-#define AT91C_PWMC_DIVB       ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor.
-#define AT91C_PWMC_PREB       ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B
-#define     AT91C_PWMC_PREB_MCK                  ((unsigned int) 0x0 << 24) // (PWMC)
-// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
-#define AT91C_PWMC_CHID0      ((unsigned int) 0x1 <<  0) // (PWMC) Channel ID 0
-#define AT91C_PWMC_CHID1      ((unsigned int) 0x1 <<  1) // (PWMC) Channel ID 1
-#define AT91C_PWMC_CHID2      ((unsigned int) 0x1 <<  2) // (PWMC) Channel ID 2
-#define AT91C_PWMC_CHID3      ((unsigned int) 0x1 <<  3) // (PWMC) Channel ID 3
-#define AT91C_PWMC_CHID4      ((unsigned int) 0x1 <<  4) // (PWMC) Channel ID 4
-#define AT91C_PWMC_CHID5      ((unsigned int) 0x1 <<  5) // (PWMC) Channel ID 5
-#define AT91C_PWMC_CHID6      ((unsigned int) 0x1 <<  6) // (PWMC) Channel ID 6
-#define AT91C_PWMC_CHID7      ((unsigned int) 0x1 <<  7) // (PWMC) Channel ID 7
-// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
-// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
-// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
-// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
-// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
-// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
+/* -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- */
+#define AT91C_PWMC_DIVA            ( ( unsigned int ) 0xFF << 0 )  /* (PWMC) CLKA divide factor. */
+#define AT91C_PWMC_PREA            ( ( unsigned int ) 0xF << 8 )   /* (PWMC) Divider Input Clock Prescaler A */
+#define     AT91C_PWMC_PREA_MCK    ( ( unsigned int ) 0x0 << 8 )   /* (PWMC) */
+#define AT91C_PWMC_DIVB            ( ( unsigned int ) 0xFF << 16 ) /* (PWMC) CLKB divide factor. */
+#define AT91C_PWMC_PREB            ( ( unsigned int ) 0xF << 24 )  /* (PWMC) Divider Input Clock Prescaler B */
+#define     AT91C_PWMC_PREB_MCK    ( ( unsigned int ) 0x0 << 24 )  /* (PWMC) */
+/* -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- */
+#define AT91C_PWMC_CHID0           ( ( unsigned int ) 0x1 << 0 )   /* (PWMC) Channel ID 0 */
+#define AT91C_PWMC_CHID1           ( ( unsigned int ) 0x1 << 1 )   /* (PWMC) Channel ID 1 */
+#define AT91C_PWMC_CHID2           ( ( unsigned int ) 0x1 << 2 )   /* (PWMC) Channel ID 2 */
+#define AT91C_PWMC_CHID3           ( ( unsigned int ) 0x1 << 3 )   /* (PWMC) Channel ID 3 */
+#define AT91C_PWMC_CHID4           ( ( unsigned int ) 0x1 << 4 )   /* (PWMC) Channel ID 4 */
+#define AT91C_PWMC_CHID5           ( ( unsigned int ) 0x1 << 5 )   /* (PWMC) Channel ID 5 */
+#define AT91C_PWMC_CHID6           ( ( unsigned int ) 0x1 << 6 )   /* (PWMC) Channel ID 6 */
+#define AT91C_PWMC_CHID7           ( ( unsigned int ) 0x1 << 7 )   /* (PWMC) Channel ID 7 */
+/* -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- */
+/* -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- */
+/* -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- */
+/* -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- */
+/* -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- */
+/* -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR USB Device Interface
-// *****************************************************************************
-typedef struct _AT91S_UDP {
-    AT91_REG     UDP_NUM;   // Frame Number Register
-    AT91_REG     UDP_GLBSTATE;  // Global State Register
-    AT91_REG     UDP_FADDR;     // Function Address Register
-    AT91_REG     Reserved0[1];  //
-    AT91_REG     UDP_IER;   // Interrupt Enable Register
-    AT91_REG     UDP_IDR;   // Interrupt Disable Register
-    AT91_REG     UDP_IMR;   // Interrupt Mask Register
-    AT91_REG     UDP_ISR;   // Interrupt Status Register
-    AT91_REG     UDP_ICR;   // Interrupt Clear Register
-    AT91_REG     Reserved1[1];  //
-    AT91_REG     UDP_RSTEP;     // Reset Endpoint Register
-    AT91_REG     Reserved2[1];  //
-    AT91_REG     UDP_CSR[8];    // Endpoint Control and Status Register
-    AT91_REG     UDP_FDR[8];    // Endpoint FIFO Data Register
-} AT91S_UDP, *AT91PS_UDP;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR USB Device Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_UDP
+{
+    AT91_REG UDP_NUM;        /* Frame Number Register */
+    AT91_REG UDP_GLBSTATE;   /* Global State Register */
+    AT91_REG UDP_FADDR;      /* Function Address Register */
+    AT91_REG Reserved0[ 1 ]; /* */
+    AT91_REG UDP_IER;        /* Interrupt Enable Register */
+    AT91_REG UDP_IDR;        /* Interrupt Disable Register */
+    AT91_REG UDP_IMR;        /* Interrupt Mask Register */
+    AT91_REG UDP_ISR;        /* Interrupt Status Register */
+    AT91_REG UDP_ICR;        /* Interrupt Clear Register */
+    AT91_REG Reserved1[ 1 ]; /* */
+    AT91_REG UDP_RSTEP;      /* Reset Endpoint Register */
+    AT91_REG Reserved2[ 1 ]; /* */
+    AT91_REG UDP_CSR[ 8 ];   /* Endpoint Control and Status Register */
+    AT91_REG UDP_FDR[ 8 ];   /* Endpoint FIFO Data Register */
+} AT91S_UDP, * AT91PS_UDP;
 
-// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
-#define AT91C_UDP_FRM_NUM     ((unsigned int) 0x7FF <<  0) // (UDP) Frame Number as Defined in the Packet Field Formats
-#define AT91C_UDP_FRM_ERR     ((unsigned int) 0x1 << 16) // (UDP) Frame Error
-#define AT91C_UDP_FRM_OK      ((unsigned int) 0x1 << 17) // (UDP) Frame OK
-// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
-#define AT91C_UDP_FADDEN      ((unsigned int) 0x1 <<  0) // (UDP) Function Address Enable
-#define AT91C_UDP_CONFG       ((unsigned int) 0x1 <<  1) // (UDP) Configured
-#define AT91C_UDP_RMWUPE      ((unsigned int) 0x1 <<  2) // (UDP) Remote Wake Up Enable
-#define AT91C_UDP_RSMINPR     ((unsigned int) 0x1 <<  3) // (UDP) A Resume Has Been Sent to the Host
-// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
-#define AT91C_UDP_FADD        ((unsigned int) 0xFF <<  0) // (UDP) Function Address Value
-#define AT91C_UDP_FEN         ((unsigned int) 0x1 <<  8) // (UDP) Function Enable
-// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
-#define AT91C_UDP_EPINT0      ((unsigned int) 0x1 <<  0) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT1      ((unsigned int) 0x1 <<  1) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT2      ((unsigned int) 0x1 <<  2) // (UDP) Endpoint 2 Interrupt
-#define AT91C_UDP_EPINT3      ((unsigned int) 0x1 <<  3) // (UDP) Endpoint 3 Interrupt
-#define AT91C_UDP_EPINT4      ((unsigned int) 0x1 <<  4) // (UDP) Endpoint 4 Interrupt
-#define AT91C_UDP_EPINT5      ((unsigned int) 0x1 <<  5) // (UDP) Endpoint 5 Interrupt
-#define AT91C_UDP_EPINT6      ((unsigned int) 0x1 <<  6) // (UDP) Endpoint 6 Interrupt
-#define AT91C_UDP_EPINT7      ((unsigned int) 0x1 <<  7) // (UDP) Endpoint 7 Interrupt
-#define AT91C_UDP_RXSUSP      ((unsigned int) 0x1 <<  8) // (UDP) USB Suspend Interrupt
-#define AT91C_UDP_RXRSM       ((unsigned int) 0x1 <<  9) // (UDP) USB Resume Interrupt
-#define AT91C_UDP_EXTRSM      ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt
-#define AT91C_UDP_SOFINT      ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt
-#define AT91C_UDP_WAKEUP      ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt
-// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
-// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
-// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
-#define AT91C_UDP_ENDBUSRES   ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
-// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
-// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
-#define AT91C_UDP_EP0         ((unsigned int) 0x1 <<  0) // (UDP) Reset Endpoint 0
-#define AT91C_UDP_EP1         ((unsigned int) 0x1 <<  1) // (UDP) Reset Endpoint 1
-#define AT91C_UDP_EP2         ((unsigned int) 0x1 <<  2) // (UDP) Reset Endpoint 2
-#define AT91C_UDP_EP3         ((unsigned int) 0x1 <<  3) // (UDP) Reset Endpoint 3
-#define AT91C_UDP_EP4         ((unsigned int) 0x1 <<  4) // (UDP) Reset Endpoint 4
-#define AT91C_UDP_EP5         ((unsigned int) 0x1 <<  5) // (UDP) Reset Endpoint 5
-#define AT91C_UDP_EP6         ((unsigned int) 0x1 <<  6) // (UDP) Reset Endpoint 6
-#define AT91C_UDP_EP7         ((unsigned int) 0x1 <<  7) // (UDP) Reset Endpoint 7
-// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
-#define AT91C_UDP_TXCOMP      ((unsigned int) 0x1 <<  0) // (UDP) Generates an IN packet with data previously written in the DPR
-#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 <<  1) // (UDP) Receive Data Bank 0
-#define AT91C_UDP_RXSETUP     ((unsigned int) 0x1 <<  2) // (UDP) Sends STALL to the Host (Control endpoints)
-#define AT91C_UDP_ISOERROR    ((unsigned int) 0x1 <<  3) // (UDP) Isochronous error (Isochronous endpoints)
-#define AT91C_UDP_TXPKTRDY    ((unsigned int) 0x1 <<  4) // (UDP) Transmit Packet Ready
-#define AT91C_UDP_FORCESTALL  ((unsigned int) 0x1 <<  5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
-#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 <<  6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
-#define AT91C_UDP_DIR         ((unsigned int) 0x1 <<  7) // (UDP) Transfer Direction
-#define AT91C_UDP_EPTYPE      ((unsigned int) 0x7 <<  8) // (UDP) Endpoint type
-#define     AT91C_UDP_EPTYPE_CTRL                 ((unsigned int) 0x0 <<  8) // (UDP) Control
-#define     AT91C_UDP_EPTYPE_ISO_OUT              ((unsigned int) 0x1 <<  8) // (UDP) Isochronous OUT
-#define     AT91C_UDP_EPTYPE_BULK_OUT             ((unsigned int) 0x2 <<  8) // (UDP) Bulk OUT
-#define     AT91C_UDP_EPTYPE_INT_OUT              ((unsigned int) 0x3 <<  8) // (UDP) Interrupt OUT
-#define     AT91C_UDP_EPTYPE_ISO_IN               ((unsigned int) 0x5 <<  8) // (UDP) Isochronous IN
-#define     AT91C_UDP_EPTYPE_BULK_IN              ((unsigned int) 0x6 <<  8) // (UDP) Bulk IN
-#define     AT91C_UDP_EPTYPE_INT_IN               ((unsigned int) 0x7 <<  8) // (UDP) Interrupt IN
-#define AT91C_UDP_DTGLE       ((unsigned int) 0x1 << 11) // (UDP) Data Toggle
-#define AT91C_UDP_EPEDS       ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable
-#define AT91C_UDP_RXBYTECNT   ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
+/* -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- */
+#define AT91C_UDP_FRM_NUM    ( ( unsigned int ) 0x7FF << 0 ) /* (UDP) Frame Number as Defined in the Packet Field Formats */
+#define AT91C_UDP_FRM_ERR    ( ( unsigned int ) 0x1 << 16 )  /* (UDP) Frame Error */
+#define AT91C_UDP_FRM_OK     ( ( unsigned int ) 0x1 << 17 )  /* (UDP) Frame OK */
+/* -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- */
+#define AT91C_UDP_FADDEN     ( ( unsigned int ) 0x1 << 0 )   /* (UDP) Function Address Enable */
+#define AT91C_UDP_CONFG      ( ( unsigned int ) 0x1 << 1 )   /* (UDP) Configured */
+#define AT91C_UDP_RMWUPE     ( ( unsigned int ) 0x1 << 2 )   /* (UDP) Remote Wake Up Enable */
+#define AT91C_UDP_RSMINPR    ( ( unsigned int ) 0x1 << 3 )   /* (UDP) A Resume Has Been Sent to the Host */
+/* -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- */
+#define AT91C_UDP_FADD       ( ( unsigned int ) 0xFF << 0 )  /* (UDP) Function Address Value */
+#define AT91C_UDP_FEN        ( ( unsigned int ) 0x1 << 8 )   /* (UDP) Function Enable */
+/* -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- */
+#define AT91C_UDP_EPINT0     ( ( unsigned int ) 0x1 << 0 )   /* (UDP) Endpoint 0 Interrupt */
+#define AT91C_UDP_EPINT1     ( ( unsigned int ) 0x1 << 1 )   /* (UDP) Endpoint 0 Interrupt */
+#define AT91C_UDP_EPINT2     ( ( unsigned int ) 0x1 << 2 )   /* (UDP) Endpoint 2 Interrupt */
+#define AT91C_UDP_EPINT3     ( ( unsigned int ) 0x1 << 3 )   /* (UDP) Endpoint 3 Interrupt */
+#define AT91C_UDP_EPINT4     ( ( unsigned int ) 0x1 << 4 )   /* (UDP) Endpoint 4 Interrupt */
+#define AT91C_UDP_EPINT5     ( ( unsigned int ) 0x1 << 5 )   /* (UDP) Endpoint 5 Interrupt */
+#define AT91C_UDP_EPINT6     ( ( unsigned int ) 0x1 << 6 )   /* (UDP) Endpoint 6 Interrupt */
+#define AT91C_UDP_EPINT7     ( ( unsigned int ) 0x1 << 7 )   /* (UDP) Endpoint 7 Interrupt */
+#define AT91C_UDP_RXSUSP     ( ( unsigned int ) 0x1 << 8 )   /* (UDP) USB Suspend Interrupt */
+#define AT91C_UDP_RXRSM      ( ( unsigned int ) 0x1 << 9 )   /* (UDP) USB Resume Interrupt */
+#define AT91C_UDP_EXTRSM     ( ( unsigned int ) 0x1 << 10 )  /* (UDP) USB External Resume Interrupt */
+#define AT91C_UDP_SOFINT     ( ( unsigned int ) 0x1 << 11 )  /* (UDP) USB Start Of frame Interrupt */
+#define AT91C_UDP_WAKEUP     ( ( unsigned int ) 0x1 << 13 )  /* (UDP) USB Resume Interrupt */
+/* -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- */
+/* -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- */
+/* -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- */
+#define AT91C_UDP_ENDBUSRES              ( ( unsigned int ) 0x1 << 12 ) /* (UDP) USB End Of Bus Reset Interrupt */
+/* -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- */
+/* -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- */
+#define AT91C_UDP_EP0                    ( ( unsigned int ) 0x1 << 0 )    /* (UDP) Reset Endpoint 0 */
+#define AT91C_UDP_EP1                    ( ( unsigned int ) 0x1 << 1 )    /* (UDP) Reset Endpoint 1 */
+#define AT91C_UDP_EP2                    ( ( unsigned int ) 0x1 << 2 )    /* (UDP) Reset Endpoint 2 */
+#define AT91C_UDP_EP3                    ( ( unsigned int ) 0x1 << 3 )    /* (UDP) Reset Endpoint 3 */
+#define AT91C_UDP_EP4                    ( ( unsigned int ) 0x1 << 4 )    /* (UDP) Reset Endpoint 4 */
+#define AT91C_UDP_EP5                    ( ( unsigned int ) 0x1 << 5 )    /* (UDP) Reset Endpoint 5 */
+#define AT91C_UDP_EP6                    ( ( unsigned int ) 0x1 << 6 )    /* (UDP) Reset Endpoint 6 */
+#define AT91C_UDP_EP7                    ( ( unsigned int ) 0x1 << 7 )    /* (UDP) Reset Endpoint 7 */
+/* -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- */
+#define AT91C_UDP_TXCOMP                 ( ( unsigned int ) 0x1 << 0 )    /* (UDP) Generates an IN packet with data previously written in the DPR */
+#define AT91C_UDP_RX_DATA_BK0            ( ( unsigned int ) 0x1 << 1 )    /* (UDP) Receive Data Bank 0 */
+#define AT91C_UDP_RXSETUP                ( ( unsigned int ) 0x1 << 2 )    /* (UDP) Sends STALL to the Host (Control endpoints) */
+#define AT91C_UDP_ISOERROR               ( ( unsigned int ) 0x1 << 3 )    /* (UDP) Isochronous error (Isochronous endpoints) */
+#define AT91C_UDP_TXPKTRDY               ( ( unsigned int ) 0x1 << 4 )    /* (UDP) Transmit Packet Ready */
+#define AT91C_UDP_FORCESTALL             ( ( unsigned int ) 0x1 << 5 )    /* (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). */
+#define AT91C_UDP_RX_DATA_BK1            ( ( unsigned int ) 0x1 << 6 )    /* (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). */
+#define AT91C_UDP_DIR                    ( ( unsigned int ) 0x1 << 7 )    /* (UDP) Transfer Direction */
+#define AT91C_UDP_EPTYPE                 ( ( unsigned int ) 0x7 << 8 )    /* (UDP) Endpoint type */
+#define     AT91C_UDP_EPTYPE_CTRL        ( ( unsigned int ) 0x0 << 8 )    /* (UDP) Control */
+#define     AT91C_UDP_EPTYPE_ISO_OUT     ( ( unsigned int ) 0x1 << 8 )    /* (UDP) Isochronous OUT */
+#define     AT91C_UDP_EPTYPE_BULK_OUT    ( ( unsigned int ) 0x2 << 8 )    /* (UDP) Bulk OUT */
+#define     AT91C_UDP_EPTYPE_INT_OUT     ( ( unsigned int ) 0x3 << 8 )    /* (UDP) Interrupt OUT */
+#define     AT91C_UDP_EPTYPE_ISO_IN      ( ( unsigned int ) 0x5 << 8 )    /* (UDP) Isochronous IN */
+#define     AT91C_UDP_EPTYPE_BULK_IN     ( ( unsigned int ) 0x6 << 8 )    /* (UDP) Bulk IN */
+#define     AT91C_UDP_EPTYPE_INT_IN      ( ( unsigned int ) 0x7 << 8 )    /* (UDP) Interrupt IN */
+#define AT91C_UDP_DTGLE                  ( ( unsigned int ) 0x1 << 11 )   /* (UDP) Data Toggle */
+#define AT91C_UDP_EPEDS                  ( ( unsigned int ) 0x1 << 15 )   /* (UDP) Endpoint Enable Disable */
+#define AT91C_UDP_RXBYTECNT              ( ( unsigned int ) 0x7FF << 16 ) /* (UDP) Number Of Bytes Available in the FIFO */
 
-// *****************************************************************************
-//               REGISTER ADDRESS DEFINITION FOR AT91SAM7S64
-// *****************************************************************************
-// ========== Register definition for SYSC peripheral ==========
-#define AT91C_SYSC_SYSC_VRPM ((AT91_REG *)  0xFFFFFD60) // (SYSC) Voltage Regulator Power Mode Register
-// ========== Register definition for AIC peripheral ==========
-#define AT91C_AIC_ICCR  ((AT91_REG *)   0xFFFFF128) // (AIC) Interrupt Clear Command Register
-#define AT91C_AIC_IECR  ((AT91_REG *)   0xFFFFF120) // (AIC) Interrupt Enable Command Register
-#define AT91C_AIC_SMR   ((AT91_REG *)   0xFFFFF000) // (AIC) Source Mode Register
-#define AT91C_AIC_ISCR  ((AT91_REG *)   0xFFFFF12C) // (AIC) Interrupt Set Command Register
-#define AT91C_AIC_EOICR ((AT91_REG *)   0xFFFFF130) // (AIC) End of Interrupt Command Register
-#define AT91C_AIC_DCR   ((AT91_REG *)   0xFFFFF138) // (AIC) Debug Control Register (Protect)
-#define AT91C_AIC_FFER  ((AT91_REG *)   0xFFFFF140) // (AIC) Fast Forcing Enable Register
-#define AT91C_AIC_SVR   ((AT91_REG *)   0xFFFFF080) // (AIC) Source Vector Register
-#define AT91C_AIC_SPU   ((AT91_REG *)   0xFFFFF134) // (AIC) Spurious Vector Register
-#define AT91C_AIC_FFDR  ((AT91_REG *)   0xFFFFF144) // (AIC) Fast Forcing Disable Register
-#define AT91C_AIC_FVR   ((AT91_REG *)   0xFFFFF104) // (AIC) FIQ Vector Register
-#define AT91C_AIC_FFSR  ((AT91_REG *)   0xFFFFF148) // (AIC) Fast Forcing Status Register
-#define AT91C_AIC_IMR   ((AT91_REG *)   0xFFFFF110) // (AIC) Interrupt Mask Register
-#define AT91C_AIC_ISR   ((AT91_REG *)   0xFFFFF108) // (AIC) Interrupt Status Register
-#define AT91C_AIC_IVR   ((AT91_REG *)   0xFFFFF100) // (AIC) IRQ Vector Register
-#define AT91C_AIC_IDCR  ((AT91_REG *)   0xFFFFF124) // (AIC) Interrupt Disable Command Register
-#define AT91C_AIC_CISR  ((AT91_REG *)   0xFFFFF114) // (AIC) Core Interrupt Status Register
-#define AT91C_AIC_IPR   ((AT91_REG *)   0xFFFFF10C) // (AIC) Interrupt Pending Register
-// ========== Register definition for DBGU peripheral ==========
-#define AT91C_DBGU_C2R  ((AT91_REG *)   0xFFFFF244) // (DBGU) Chip ID2 Register
-#define AT91C_DBGU_THR  ((AT91_REG *)   0xFFFFF21C) // (DBGU) Transmitter Holding Register
-#define AT91C_DBGU_CSR  ((AT91_REG *)   0xFFFFF214) // (DBGU) Channel Status Register
-#define AT91C_DBGU_IDR  ((AT91_REG *)   0xFFFFF20C) // (DBGU) Interrupt Disable Register
-#define AT91C_DBGU_MR   ((AT91_REG *)   0xFFFFF204) // (DBGU) Mode Register
-#define AT91C_DBGU_FNTR ((AT91_REG *)   0xFFFFF248) // (DBGU) Force NTRST Register
-#define AT91C_DBGU_C1R  ((AT91_REG *)   0xFFFFF240) // (DBGU) Chip ID1 Register
-#define AT91C_DBGU_BRGR ((AT91_REG *)   0xFFFFF220) // (DBGU) Baud Rate Generator Register
-#define AT91C_DBGU_RHR  ((AT91_REG *)   0xFFFFF218) // (DBGU) Receiver Holding Register
-#define AT91C_DBGU_IMR  ((AT91_REG *)   0xFFFFF210) // (DBGU) Interrupt Mask Register
-#define AT91C_DBGU_IER  ((AT91_REG *)   0xFFFFF208) // (DBGU) Interrupt Enable Register
-#define AT91C_DBGU_CR   ((AT91_REG *)   0xFFFFF200) // (DBGU) Control Register
-// ========== Register definition for PDC_DBGU peripheral ==========
-#define AT91C_DBGU_TNCR ((AT91_REG *)   0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
-#define AT91C_DBGU_RNCR ((AT91_REG *)   0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
-#define AT91C_DBGU_PTCR ((AT91_REG *)   0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
-#define AT91C_DBGU_PTSR ((AT91_REG *)   0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
-#define AT91C_DBGU_RCR  ((AT91_REG *)   0xFFFFF304) // (PDC_DBGU) Receive Counter Register
-#define AT91C_DBGU_TCR  ((AT91_REG *)   0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
-#define AT91C_DBGU_RPR  ((AT91_REG *)   0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
-#define AT91C_DBGU_TPR  ((AT91_REG *)   0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
-#define AT91C_DBGU_RNPR ((AT91_REG *)   0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
-#define AT91C_DBGU_TNPR ((AT91_REG *)   0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
-// ========== Register definition for PIOA peripheral ==========
-#define AT91C_PIOA_IMR  ((AT91_REG *)   0xFFFFF448) // (PIOA) Interrupt Mask Register
-#define AT91C_PIOA_IER  ((AT91_REG *)   0xFFFFF440) // (PIOA) Interrupt Enable Register
-#define AT91C_PIOA_OWDR ((AT91_REG *)   0xFFFFF4A4) // (PIOA) Output Write Disable Register
-#define AT91C_PIOA_ISR  ((AT91_REG *)   0xFFFFF44C) // (PIOA) Interrupt Status Register
-#define AT91C_PIOA_PPUDR ((AT91_REG *)  0xFFFFF460) // (PIOA) Pull-up Disable Register
-#define AT91C_PIOA_MDSR ((AT91_REG *)   0xFFFFF458) // (PIOA) Multi-driver Status Register
-#define AT91C_PIOA_MDER ((AT91_REG *)   0xFFFFF450) // (PIOA) Multi-driver Enable Register
-#define AT91C_PIOA_PER  ((AT91_REG *)   0xFFFFF400) // (PIOA) PIO Enable Register
-#define AT91C_PIOA_PSR  ((AT91_REG *)   0xFFFFF408) // (PIOA) PIO Status Register
-#define AT91C_PIOA_OER  ((AT91_REG *)   0xFFFFF410) // (PIOA) Output Enable Register
-#define AT91C_PIOA_BSR  ((AT91_REG *)   0xFFFFF474) // (PIOA) Select B Register
-#define AT91C_PIOA_PPUER ((AT91_REG *)  0xFFFFF464) // (PIOA) Pull-up Enable Register
-#define AT91C_PIOA_MDDR ((AT91_REG *)   0xFFFFF454) // (PIOA) Multi-driver Disable Register
-#define AT91C_PIOA_PDR  ((AT91_REG *)   0xFFFFF404) // (PIOA) PIO Disable Register
-#define AT91C_PIOA_ODR  ((AT91_REG *)   0xFFFFF414) // (PIOA) Output Disable Registerr
-#define AT91C_PIOA_IFDR ((AT91_REG *)   0xFFFFF424) // (PIOA) Input Filter Disable Register
-#define AT91C_PIOA_ABSR ((AT91_REG *)   0xFFFFF478) // (PIOA) AB Select Status Register
-#define AT91C_PIOA_ASR  ((AT91_REG *)   0xFFFFF470) // (PIOA) Select A Register
-#define AT91C_PIOA_PPUSR ((AT91_REG *)  0xFFFFF468) // (PIOA) Pad Pull-up Status Register
-#define AT91C_PIOA_ODSR ((AT91_REG *)   0xFFFFF438) // (PIOA) Output Data Status Register
-#define AT91C_PIOA_SODR ((AT91_REG *)   0xFFFFF430) // (PIOA) Set Output Data Register
-#define AT91C_PIOA_IFSR ((AT91_REG *)   0xFFFFF428) // (PIOA) Input Filter Status Register
-#define AT91C_PIOA_IFER ((AT91_REG *)   0xFFFFF420) // (PIOA) Input Filter Enable Register
-#define AT91C_PIOA_OSR  ((AT91_REG *)   0xFFFFF418) // (PIOA) Output Status Register
-#define AT91C_PIOA_IDR  ((AT91_REG *)   0xFFFFF444) // (PIOA) Interrupt Disable Register
-#define AT91C_PIOA_PDSR ((AT91_REG *)   0xFFFFF43C) // (PIOA) Pin Data Status Register
-#define AT91C_PIOA_CODR ((AT91_REG *)   0xFFFFF434) // (PIOA) Clear Output Data Register
-#define AT91C_PIOA_OWSR ((AT91_REG *)   0xFFFFF4A8) // (PIOA) Output Write Status Register
-#define AT91C_PIOA_OWER ((AT91_REG *)   0xFFFFF4A0) // (PIOA) Output Write Enable Register
-// ========== Register definition for CKGR peripheral ==========
-#define AT91C_CKGR_PLLR ((AT91_REG *)   0xFFFFFC2C) // (CKGR) PLL Register
-#define AT91C_CKGR_MCFR ((AT91_REG *)   0xFFFFFC24) // (CKGR) Main Clock  Frequency Register
-#define AT91C_CKGR_MOR  ((AT91_REG *)   0xFFFFFC20) // (CKGR) Main Oscillator Register
-// ========== Register definition for PMC peripheral ==========
-#define AT91C_PMC_SCSR  ((AT91_REG *)   0xFFFFFC08) // (PMC) System Clock Status Register
-#define AT91C_PMC_SCER  ((AT91_REG *)   0xFFFFFC00) // (PMC) System Clock Enable Register
-#define AT91C_PMC_IMR   ((AT91_REG *)   0xFFFFFC6C) // (PMC) Interrupt Mask Register
-#define AT91C_PMC_IDR   ((AT91_REG *)   0xFFFFFC64) // (PMC) Interrupt Disable Register
-#define AT91C_PMC_PCDR  ((AT91_REG *)   0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
-#define AT91C_PMC_SCDR  ((AT91_REG *)   0xFFFFFC04) // (PMC) System Clock Disable Register
-#define AT91C_PMC_SR    ((AT91_REG *)   0xFFFFFC68) // (PMC) Status Register
-#define AT91C_PMC_IER   ((AT91_REG *)   0xFFFFFC60) // (PMC) Interrupt Enable Register
-#define AT91C_PMC_MCKR  ((AT91_REG *)   0xFFFFFC30) // (PMC) Master Clock Register
-#define AT91C_PMC_MOR   ((AT91_REG *)   0xFFFFFC20) // (PMC) Main Oscillator Register
-#define AT91C_PMC_PCER  ((AT91_REG *)   0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
-#define AT91C_PMC_PCSR  ((AT91_REG *)   0xFFFFFC18) // (PMC) Peripheral Clock Status Register
-#define AT91C_PMC_PLLR  ((AT91_REG *)   0xFFFFFC2C) // (PMC) PLL Register
-#define AT91C_PMC_MCFR  ((AT91_REG *)   0xFFFFFC24) // (PMC) Main Clock  Frequency Register
-#define AT91C_PMC_PCKR  ((AT91_REG *)   0xFFFFFC40) // (PMC) Programmable Clock Register
-// ========== Register definition for RSTC peripheral ==========
-#define AT91C_RSTC_RSR  ((AT91_REG *)   0xFFFFFD04) // (RSTC) Reset Status Register
-#define AT91C_RSTC_RMR  ((AT91_REG *)   0xFFFFFD08) // (RSTC) Reset Mode Register
-#define AT91C_RSTC_RCR  ((AT91_REG *)   0xFFFFFD00) // (RSTC) Reset Control Register
-// ========== Register definition for RTTC peripheral ==========
-#define AT91C_RTTC_RTSR ((AT91_REG *)   0xFFFFFD2C) // (RTTC) Real-time Status Register
-#define AT91C_RTTC_RTAR ((AT91_REG *)   0xFFFFFD24) // (RTTC) Real-time Alarm Register
-#define AT91C_RTTC_RTVR ((AT91_REG *)   0xFFFFFD28) // (RTTC) Real-time Value Register
-#define AT91C_RTTC_RTMR ((AT91_REG *)   0xFFFFFD20) // (RTTC) Real-time Mode Register
-// ========== Register definition for PITC peripheral ==========
-#define AT91C_PITC_PIIR ((AT91_REG *)   0xFFFFFD3C) // (PITC) Period Interval Image Register
-#define AT91C_PITC_PISR ((AT91_REG *)   0xFFFFFD34) // (PITC) Period Interval Status Register
-#define AT91C_PITC_PIVR ((AT91_REG *)   0xFFFFFD38) // (PITC) Period Interval Value Register
-#define AT91C_PITC_PIMR ((AT91_REG *)   0xFFFFFD30) // (PITC) Period Interval Mode Register
-// ========== Register definition for WDTC peripheral ==========
-#define AT91C_WDTC_WDMR ((AT91_REG *)   0xFFFFFD44) // (WDTC) Watchdog Mode Register
-#define AT91C_WDTC_WDSR ((AT91_REG *)   0xFFFFFD48) // (WDTC) Watchdog Status Register
-#define AT91C_WDTC_WDCR ((AT91_REG *)   0xFFFFFD40) // (WDTC) Watchdog Control Register
-// ========== Register definition for MC peripheral ==========
-#define AT91C_MC_FCR    ((AT91_REG *)   0xFFFFFF64) // (MC) MC Flash Command Register
-#define AT91C_MC_ASR    ((AT91_REG *)   0xFFFFFF04) // (MC) MC Abort Status Register
-#define AT91C_MC_FSR    ((AT91_REG *)   0xFFFFFF68) // (MC) MC Flash Status Register
-#define AT91C_MC_FMR    ((AT91_REG *)   0xFFFFFF60) // (MC) MC Flash Mode Register
-#define AT91C_MC_AASR   ((AT91_REG *)   0xFFFFFF08) // (MC) MC Abort Address Status Register
-#define AT91C_MC_RCR    ((AT91_REG *)   0xFFFFFF00) // (MC) MC Remap Control Register
-// ========== Register definition for PDC_SPI peripheral ==========
-#define AT91C_SPI_PTCR  ((AT91_REG *)   0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register
-#define AT91C_SPI_TNPR  ((AT91_REG *)   0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register
-#define AT91C_SPI_RNPR  ((AT91_REG *)   0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register
-#define AT91C_SPI_TPR   ((AT91_REG *)   0xFFFE0108) // (PDC_SPI) Transmit Pointer Register
-#define AT91C_SPI_RPR   ((AT91_REG *)   0xFFFE0100) // (PDC_SPI) Receive Pointer Register
-#define AT91C_SPI_PTSR  ((AT91_REG *)   0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register
-#define AT91C_SPI_TNCR  ((AT91_REG *)   0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register
-#define AT91C_SPI_RNCR  ((AT91_REG *)   0xFFFE0114) // (PDC_SPI) Receive Next Counter Register
-#define AT91C_SPI_TCR   ((AT91_REG *)   0xFFFE010C) // (PDC_SPI) Transmit Counter Register
-#define AT91C_SPI_RCR   ((AT91_REG *)   0xFFFE0104) // (PDC_SPI) Receive Counter Register
-// ========== Register definition for SPI peripheral ==========
-#define AT91C_SPI_CSR   ((AT91_REG *)   0xFFFE0030) // (SPI) Chip Select Register
-#define AT91C_SPI_IDR   ((AT91_REG *)   0xFFFE0018) // (SPI) Interrupt Disable Register
-#define AT91C_SPI_SR    ((AT91_REG *)   0xFFFE0010) // (SPI) Status Register
-#define AT91C_SPI_RDR   ((AT91_REG *)   0xFFFE0008) // (SPI) Receive Data Register
-#define AT91C_SPI_CR    ((AT91_REG *)   0xFFFE0000) // (SPI) Control Register
-#define AT91C_SPI_IMR   ((AT91_REG *)   0xFFFE001C) // (SPI) Interrupt Mask Register
-#define AT91C_SPI_IER   ((AT91_REG *)   0xFFFE0014) // (SPI) Interrupt Enable Register
-#define AT91C_SPI_TDR   ((AT91_REG *)   0xFFFE000C) // (SPI) Transmit Data Register
-#define AT91C_SPI_MR    ((AT91_REG *)   0xFFFE0004) // (SPI) Mode Register
-// ========== Register definition for PDC_ADC peripheral ==========
-#define AT91C_ADC_PTCR  ((AT91_REG *)   0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
-#define AT91C_ADC_TNPR  ((AT91_REG *)   0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
-#define AT91C_ADC_RNPR  ((AT91_REG *)   0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
-#define AT91C_ADC_TPR   ((AT91_REG *)   0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
-#define AT91C_ADC_RPR   ((AT91_REG *)   0xFFFD8100) // (PDC_ADC) Receive Pointer Register
-#define AT91C_ADC_PTSR  ((AT91_REG *)   0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
-#define AT91C_ADC_TNCR  ((AT91_REG *)   0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
-#define AT91C_ADC_RNCR  ((AT91_REG *)   0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
-#define AT91C_ADC_TCR   ((AT91_REG *)   0xFFFD810C) // (PDC_ADC) Transmit Counter Register
-#define AT91C_ADC_RCR   ((AT91_REG *)   0xFFFD8104) // (PDC_ADC) Receive Counter Register
-// ========== Register definition for ADC peripheral ==========
-#define AT91C_ADC_IMR   ((AT91_REG *)   0xFFFD802C) // (ADC) ADC Interrupt Mask Register
-#define AT91C_ADC_CDR4  ((AT91_REG *)   0xFFFD8040) // (ADC) ADC Channel Data Register 4
-#define AT91C_ADC_CDR2  ((AT91_REG *)   0xFFFD8038) // (ADC) ADC Channel Data Register 2
-#define AT91C_ADC_CDR0  ((AT91_REG *)   0xFFFD8030) // (ADC) ADC Channel Data Register 0
-#define AT91C_ADC_CDR7  ((AT91_REG *)   0xFFFD804C) // (ADC) ADC Channel Data Register 7
-#define AT91C_ADC_CDR1  ((AT91_REG *)   0xFFFD8034) // (ADC) ADC Channel Data Register 1
-#define AT91C_ADC_CDR3  ((AT91_REG *)   0xFFFD803C) // (ADC) ADC Channel Data Register 3
-#define AT91C_ADC_CDR5  ((AT91_REG *)   0xFFFD8044) // (ADC) ADC Channel Data Register 5
-#define AT91C_ADC_MR    ((AT91_REG *)   0xFFFD8004) // (ADC) ADC Mode Register
-#define AT91C_ADC_CDR6  ((AT91_REG *)   0xFFFD8048) // (ADC) ADC Channel Data Register 6
-#define AT91C_ADC_CR    ((AT91_REG *)   0xFFFD8000) // (ADC) ADC Control Register
-#define AT91C_ADC_CHER  ((AT91_REG *)   0xFFFD8010) // (ADC) ADC Channel Enable Register
-#define AT91C_ADC_CHSR  ((AT91_REG *)   0xFFFD8018) // (ADC) ADC Channel Status Register
-#define AT91C_ADC_IER   ((AT91_REG *)   0xFFFD8024) // (ADC) ADC Interrupt Enable Register
-#define AT91C_ADC_SR    ((AT91_REG *)   0xFFFD801C) // (ADC) ADC Status Register
-#define AT91C_ADC_CHDR  ((AT91_REG *)   0xFFFD8014) // (ADC) ADC Channel Disable Register
-#define AT91C_ADC_IDR   ((AT91_REG *)   0xFFFD8028) // (ADC) ADC Interrupt Disable Register
-#define AT91C_ADC_LCDR  ((AT91_REG *)   0xFFFD8020) // (ADC) ADC Last Converted Data Register
-// ========== Register definition for PDC_SSC peripheral ==========
-#define AT91C_SSC_PTCR  ((AT91_REG *)   0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
-#define AT91C_SSC_TNPR  ((AT91_REG *)   0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
-#define AT91C_SSC_RNPR  ((AT91_REG *)   0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
-#define AT91C_SSC_TPR   ((AT91_REG *)   0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
-#define AT91C_SSC_RPR   ((AT91_REG *)   0xFFFD4100) // (PDC_SSC) Receive Pointer Register
-#define AT91C_SSC_PTSR  ((AT91_REG *)   0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
-#define AT91C_SSC_TNCR  ((AT91_REG *)   0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
-#define AT91C_SSC_RNCR  ((AT91_REG *)   0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
-#define AT91C_SSC_TCR   ((AT91_REG *)   0xFFFD410C) // (PDC_SSC) Transmit Counter Register
-#define AT91C_SSC_RCR   ((AT91_REG *)   0xFFFD4104) // (PDC_SSC) Receive Counter Register
-// ========== Register definition for SSC peripheral ==========
-#define AT91C_SSC_RFMR  ((AT91_REG *)   0xFFFD4014) // (SSC) Receive Frame Mode Register
-#define AT91C_SSC_CMR   ((AT91_REG *)   0xFFFD4004) // (SSC) Clock Mode Register
-#define AT91C_SSC_IDR   ((AT91_REG *)   0xFFFD4048) // (SSC) Interrupt Disable Register
-#define AT91C_SSC_SR    ((AT91_REG *)   0xFFFD4040) // (SSC) Status Register
-#define AT91C_SSC_RC0R  ((AT91_REG *)   0xFFFD4038) // (SSC) Receive Compare 0 Register
-#define AT91C_SSC_RSHR  ((AT91_REG *)   0xFFFD4030) // (SSC) Receive Sync Holding Register
-#define AT91C_SSC_RHR   ((AT91_REG *)   0xFFFD4020) // (SSC) Receive Holding Register
-#define AT91C_SSC_TCMR  ((AT91_REG *)   0xFFFD4018) // (SSC) Transmit Clock Mode Register
-#define AT91C_SSC_RCMR  ((AT91_REG *)   0xFFFD4010) // (SSC) Receive Clock ModeRegister
-#define AT91C_SSC_CR    ((AT91_REG *)   0xFFFD4000) // (SSC) Control Register
-#define AT91C_SSC_IMR   ((AT91_REG *)   0xFFFD404C) // (SSC) Interrupt Mask Register
-#define AT91C_SSC_IER   ((AT91_REG *)   0xFFFD4044) // (SSC) Interrupt Enable Register
-#define AT91C_SSC_RC1R  ((AT91_REG *)   0xFFFD403C) // (SSC) Receive Compare 1 Register
-#define AT91C_SSC_TSHR  ((AT91_REG *)   0xFFFD4034) // (SSC) Transmit Sync Holding Register
-#define AT91C_SSC_THR   ((AT91_REG *)   0xFFFD4024) // (SSC) Transmit Holding Register
-#define AT91C_SSC_TFMR  ((AT91_REG *)   0xFFFD401C) // (SSC) Transmit Frame Mode Register
-// ========== Register definition for PDC_US1 peripheral ==========
-#define AT91C_US1_PTSR  ((AT91_REG *)   0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
-#define AT91C_US1_TNCR  ((AT91_REG *)   0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
-#define AT91C_US1_RNCR  ((AT91_REG *)   0xFFFC4114) // (PDC_US1) Receive Next Counter Register
-#define AT91C_US1_TCR   ((AT91_REG *)   0xFFFC410C) // (PDC_US1) Transmit Counter Register
-#define AT91C_US1_RCR   ((AT91_REG *)   0xFFFC4104) // (PDC_US1) Receive Counter Register
-#define AT91C_US1_PTCR  ((AT91_REG *)   0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
-#define AT91C_US1_TNPR  ((AT91_REG *)   0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
-#define AT91C_US1_RNPR  ((AT91_REG *)   0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
-#define AT91C_US1_TPR   ((AT91_REG *)   0xFFFC4108) // (PDC_US1) Transmit Pointer Register
-#define AT91C_US1_RPR   ((AT91_REG *)   0xFFFC4100) // (PDC_US1) Receive Pointer Register
-// ========== Register definition for US1 peripheral ==========
-#define AT91C_US1_XXR   ((AT91_REG *)   0xFFFC4048) // (US1) XON_XOFF Register
-#define AT91C_US1_RHR   ((AT91_REG *)   0xFFFC4018) // (US1) Receiver Holding Register
-#define AT91C_US1_IMR   ((AT91_REG *)   0xFFFC4010) // (US1) Interrupt Mask Register
-#define AT91C_US1_IER   ((AT91_REG *)   0xFFFC4008) // (US1) Interrupt Enable Register
-#define AT91C_US1_CR    ((AT91_REG *)   0xFFFC4000) // (US1) Control Register
-#define AT91C_US1_RTOR  ((AT91_REG *)   0xFFFC4024) // (US1) Receiver Time-out Register
-#define AT91C_US1_THR   ((AT91_REG *)   0xFFFC401C) // (US1) Transmitter Holding Register
-#define AT91C_US1_CSR   ((AT91_REG *)   0xFFFC4014) // (US1) Channel Status Register
-#define AT91C_US1_IDR   ((AT91_REG *)   0xFFFC400C) // (US1) Interrupt Disable Register
-#define AT91C_US1_FIDI  ((AT91_REG *)   0xFFFC4040) // (US1) FI_DI_Ratio Register
-#define AT91C_US1_BRGR  ((AT91_REG *)   0xFFFC4020) // (US1) Baud Rate Generator Register
-#define AT91C_US1_TTGR  ((AT91_REG *)   0xFFFC4028) // (US1) Transmitter Time-guard Register
-#define AT91C_US1_IF    ((AT91_REG *)   0xFFFC404C) // (US1) IRDA_FILTER Register
-#define AT91C_US1_NER   ((AT91_REG *)   0xFFFC4044) // (US1) Nb Errors Register
-#define AT91C_US1_MR    ((AT91_REG *)   0xFFFC4004) // (US1) Mode Register
-// ========== Register definition for PDC_US0 peripheral ==========
-#define AT91C_US0_PTCR  ((AT91_REG *)   0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
-#define AT91C_US0_TNPR  ((AT91_REG *)   0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
-#define AT91C_US0_RNPR  ((AT91_REG *)   0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
-#define AT91C_US0_TPR   ((AT91_REG *)   0xFFFC0108) // (PDC_US0) Transmit Pointer Register
-#define AT91C_US0_RPR   ((AT91_REG *)   0xFFFC0100) // (PDC_US0) Receive Pointer Register
-#define AT91C_US0_PTSR  ((AT91_REG *)   0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
-#define AT91C_US0_TNCR  ((AT91_REG *)   0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
-#define AT91C_US0_RNCR  ((AT91_REG *)   0xFFFC0114) // (PDC_US0) Receive Next Counter Register
-#define AT91C_US0_TCR   ((AT91_REG *)   0xFFFC010C) // (PDC_US0) Transmit Counter Register
-#define AT91C_US0_RCR   ((AT91_REG *)   0xFFFC0104) // (PDC_US0) Receive Counter Register
-// ========== Register definition for US0 peripheral ==========
-#define AT91C_US0_TTGR  ((AT91_REG *)   0xFFFC0028) // (US0) Transmitter Time-guard Register
-#define AT91C_US0_BRGR  ((AT91_REG *)   0xFFFC0020) // (US0) Baud Rate Generator Register
-#define AT91C_US0_RHR   ((AT91_REG *)   0xFFFC0018) // (US0) Receiver Holding Register
-#define AT91C_US0_IMR   ((AT91_REG *)   0xFFFC0010) // (US0) Interrupt Mask Register
-#define AT91C_US0_NER   ((AT91_REG *)   0xFFFC0044) // (US0) Nb Errors Register
-#define AT91C_US0_RTOR  ((AT91_REG *)   0xFFFC0024) // (US0) Receiver Time-out Register
-#define AT91C_US0_XXR   ((AT91_REG *)   0xFFFC0048) // (US0) XON_XOFF Register
-#define AT91C_US0_FIDI  ((AT91_REG *)   0xFFFC0040) // (US0) FI_DI_Ratio Register
-#define AT91C_US0_CR    ((AT91_REG *)   0xFFFC0000) // (US0) Control Register
-#define AT91C_US0_IER   ((AT91_REG *)   0xFFFC0008) // (US0) Interrupt Enable Register
-#define AT91C_US0_IF    ((AT91_REG *)   0xFFFC004C) // (US0) IRDA_FILTER Register
-#define AT91C_US0_MR    ((AT91_REG *)   0xFFFC0004) // (US0) Mode Register
-#define AT91C_US0_IDR   ((AT91_REG *)   0xFFFC000C) // (US0) Interrupt Disable Register
-#define AT91C_US0_CSR   ((AT91_REG *)   0xFFFC0014) // (US0) Channel Status Register
-#define AT91C_US0_THR   ((AT91_REG *)   0xFFFC001C) // (US0) Transmitter Holding Register
-// ========== Register definition for TWI peripheral ==========
-#define AT91C_TWI_RHR   ((AT91_REG *)   0xFFFB8030) // (TWI) Receive Holding Register
-#define AT91C_TWI_IDR   ((AT91_REG *)   0xFFFB8028) // (TWI) Interrupt Disable Register
-#define AT91C_TWI_SR    ((AT91_REG *)   0xFFFB8020) // (TWI) Status Register
-#define AT91C_TWI_CWGR  ((AT91_REG *)   0xFFFB8010) // (TWI) Clock Waveform Generator Register
-#define AT91C_TWI_SMR   ((AT91_REG *)   0xFFFB8008) // (TWI) Slave Mode Register
-#define AT91C_TWI_CR    ((AT91_REG *)   0xFFFB8000) // (TWI) Control Register
-#define AT91C_TWI_THR   ((AT91_REG *)   0xFFFB8034) // (TWI) Transmit Holding Register
-#define AT91C_TWI_IMR   ((AT91_REG *)   0xFFFB802C) // (TWI) Interrupt Mask Register
-#define AT91C_TWI_IER   ((AT91_REG *)   0xFFFB8024) // (TWI) Interrupt Enable Register
-#define AT91C_TWI_IADR  ((AT91_REG *)   0xFFFB800C) // (TWI) Internal Address Register
-#define AT91C_TWI_MMR   ((AT91_REG *)   0xFFFB8004) // (TWI) Master Mode Register
-// ========== Register definition for TC2 peripheral ==========
-#define AT91C_TC2_IMR   ((AT91_REG *)   0xFFFA00AC) // (TC2) Interrupt Mask Register
-#define AT91C_TC2_IER   ((AT91_REG *)   0xFFFA00A4) // (TC2) Interrupt Enable Register
-#define AT91C_TC2_RC    ((AT91_REG *)   0xFFFA009C) // (TC2) Register C
-#define AT91C_TC2_RA    ((AT91_REG *)   0xFFFA0094) // (TC2) Register A
-#define AT91C_TC2_CMR   ((AT91_REG *)   0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC2_IDR   ((AT91_REG *)   0xFFFA00A8) // (TC2) Interrupt Disable Register
-#define AT91C_TC2_SR    ((AT91_REG *)   0xFFFA00A0) // (TC2) Status Register
-#define AT91C_TC2_RB    ((AT91_REG *)   0xFFFA0098) // (TC2) Register B
-#define AT91C_TC2_CV    ((AT91_REG *)   0xFFFA0090) // (TC2) Counter Value
-#define AT91C_TC2_CCR   ((AT91_REG *)   0xFFFA0080) // (TC2) Channel Control Register
-// ========== Register definition for TC1 peripheral ==========
-#define AT91C_TC1_IMR   ((AT91_REG *)   0xFFFA006C) // (TC1) Interrupt Mask Register
-#define AT91C_TC1_IER   ((AT91_REG *)   0xFFFA0064) // (TC1) Interrupt Enable Register
-#define AT91C_TC1_RC    ((AT91_REG *)   0xFFFA005C) // (TC1) Register C
-#define AT91C_TC1_RA    ((AT91_REG *)   0xFFFA0054) // (TC1) Register A
-#define AT91C_TC1_CMR   ((AT91_REG *)   0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC1_IDR   ((AT91_REG *)   0xFFFA0068) // (TC1) Interrupt Disable Register
-#define AT91C_TC1_SR    ((AT91_REG *)   0xFFFA0060) // (TC1) Status Register
-#define AT91C_TC1_RB    ((AT91_REG *)   0xFFFA0058) // (TC1) Register B
-#define AT91C_TC1_CV    ((AT91_REG *)   0xFFFA0050) // (TC1) Counter Value
-#define AT91C_TC1_CCR   ((AT91_REG *)   0xFFFA0040) // (TC1) Channel Control Register
-// ========== Register definition for TC0 peripheral ==========
-#define AT91C_TC0_IMR   ((AT91_REG *)   0xFFFA002C) // (TC0) Interrupt Mask Register
-#define AT91C_TC0_IER   ((AT91_REG *)   0xFFFA0024) // (TC0) Interrupt Enable Register
-#define AT91C_TC0_RC    ((AT91_REG *)   0xFFFA001C) // (TC0) Register C
-#define AT91C_TC0_RA    ((AT91_REG *)   0xFFFA0014) // (TC0) Register A
-#define AT91C_TC0_CMR   ((AT91_REG *)   0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC0_IDR   ((AT91_REG *)   0xFFFA0028) // (TC0) Interrupt Disable Register
-#define AT91C_TC0_SR    ((AT91_REG *)   0xFFFA0020) // (TC0) Status Register
-#define AT91C_TC0_RB    ((AT91_REG *)   0xFFFA0018) // (TC0) Register B
-#define AT91C_TC0_CV    ((AT91_REG *)   0xFFFA0010) // (TC0) Counter Value
-#define AT91C_TC0_CCR   ((AT91_REG *)   0xFFFA0000) // (TC0) Channel Control Register
-// ========== Register definition for TCB peripheral ==========
-#define AT91C_TCB_BMR   ((AT91_REG *)   0xFFFA00C4) // (TCB) TC Block Mode Register
-#define AT91C_TCB_BCR   ((AT91_REG *)   0xFFFA00C0) // (TCB) TC Block Control Register
-// ========== Register definition for PWMC_CH3 peripheral ==========
-#define AT91C_CH3_CUPDR ((AT91_REG *)   0xFFFCC270) // (PWMC_CH3) Channel Update Register
-#define AT91C_CH3_CPRDR ((AT91_REG *)   0xFFFCC268) // (PWMC_CH3) Channel Period Register
-#define AT91C_CH3_CMR   ((AT91_REG *)   0xFFFCC260) // (PWMC_CH3) Channel Mode Register
-#define AT91C_CH3_Reserved ((AT91_REG *)    0xFFFCC274) // (PWMC_CH3) Reserved
-#define AT91C_CH3_CCNTR ((AT91_REG *)   0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
-#define AT91C_CH3_CDTYR ((AT91_REG *)   0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
-// ========== Register definition for PWMC_CH2 peripheral ==========
-#define AT91C_CH2_CUPDR ((AT91_REG *)   0xFFFCC250) // (PWMC_CH2) Channel Update Register
-#define AT91C_CH2_CPRDR ((AT91_REG *)   0xFFFCC248) // (PWMC_CH2) Channel Period Register
-#define AT91C_CH2_CMR   ((AT91_REG *)   0xFFFCC240) // (PWMC_CH2) Channel Mode Register
-#define AT91C_CH2_Reserved ((AT91_REG *)    0xFFFCC254) // (PWMC_CH2) Reserved
-#define AT91C_CH2_CCNTR ((AT91_REG *)   0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
-#define AT91C_CH2_CDTYR ((AT91_REG *)   0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
-// ========== Register definition for PWMC_CH1 peripheral ==========
-#define AT91C_CH1_CUPDR ((AT91_REG *)   0xFFFCC230) // (PWMC_CH1) Channel Update Register
-#define AT91C_CH1_CPRDR ((AT91_REG *)   0xFFFCC228) // (PWMC_CH1) Channel Period Register
-#define AT91C_CH1_CMR   ((AT91_REG *)   0xFFFCC220) // (PWMC_CH1) Channel Mode Register
-#define AT91C_CH1_Reserved ((AT91_REG *)    0xFFFCC234) // (PWMC_CH1) Reserved
-#define AT91C_CH1_CCNTR ((AT91_REG *)   0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
-#define AT91C_CH1_CDTYR ((AT91_REG *)   0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
-// ========== Register definition for PWMC_CH0 peripheral ==========
-#define AT91C_CH0_CUPDR ((AT91_REG *)   0xFFFCC210) // (PWMC_CH0) Channel Update Register
-#define AT91C_CH0_CPRDR ((AT91_REG *)   0xFFFCC208) // (PWMC_CH0) Channel Period Register
-#define AT91C_CH0_CMR   ((AT91_REG *)   0xFFFCC200) // (PWMC_CH0) Channel Mode Register
-#define AT91C_CH0_Reserved ((AT91_REG *)    0xFFFCC214) // (PWMC_CH0) Reserved
-#define AT91C_CH0_CCNTR ((AT91_REG *)   0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
-#define AT91C_CH0_CDTYR ((AT91_REG *)   0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
-// ========== Register definition for PWMC peripheral ==========
-#define AT91C_PWMC_VR   ((AT91_REG *)   0xFFFCC0FC) // (PWMC) PWMC Version Register
-#define AT91C_PWMC_ISR  ((AT91_REG *)   0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
-#define AT91C_PWMC_IDR  ((AT91_REG *)   0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
-#define AT91C_PWMC_SR   ((AT91_REG *)   0xFFFCC00C) // (PWMC) PWMC Status Register
-#define AT91C_PWMC_ENA  ((AT91_REG *)   0xFFFCC004) // (PWMC) PWMC Enable Register
-#define AT91C_PWMC_IMR  ((AT91_REG *)   0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
-#define AT91C_PWMC_MR   ((AT91_REG *)   0xFFFCC000) // (PWMC) PWMC Mode Register
-#define AT91C_PWMC_DIS  ((AT91_REG *)   0xFFFCC008) // (PWMC) PWMC Disable Register
-#define AT91C_PWMC_IER  ((AT91_REG *)   0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
-// ========== Register definition for UDP peripheral ==========
-#define AT91C_UDP_ISR   ((AT91_REG *)   0xFFFB001C) // (UDP) Interrupt Status Register
-#define AT91C_UDP_IDR   ((AT91_REG *)   0xFFFB0014) // (UDP) Interrupt Disable Register
-#define AT91C_UDP_GLBSTATE ((AT91_REG *)    0xFFFB0004) // (UDP) Global State Register
-#define AT91C_UDP_FDR   ((AT91_REG *)   0xFFFB0050) // (UDP) Endpoint FIFO Data Register
-#define AT91C_UDP_CSR   ((AT91_REG *)   0xFFFB0030) // (UDP) Endpoint Control and Status Register
-#define AT91C_UDP_RSTEP ((AT91_REG *)   0xFFFB0028) // (UDP) Reset Endpoint Register
-#define AT91C_UDP_ICR   ((AT91_REG *)   0xFFFB0020) // (UDP) Interrupt Clear Register
-#define AT91C_UDP_IMR   ((AT91_REG *)   0xFFFB0018) // (UDP) Interrupt Mask Register
-#define AT91C_UDP_IER   ((AT91_REG *)   0xFFFB0010) // (UDP) Interrupt Enable Register
-#define AT91C_UDP_FADDR ((AT91_REG *)   0xFFFB0008) // (UDP) Function Address Register
-#define AT91C_UDP_NUM   ((AT91_REG *)   0xFFFB0000) // (UDP) Frame Number Register
+/* ***************************************************************************** */
+/*               REGISTER ADDRESS DEFINITION FOR AT91SAM7S64 */
+/* ***************************************************************************** */
+/* ========== Register definition for SYSC peripheral ========== */
+#define AT91C_SYSC_SYSC_VRPM    ( ( AT91_REG * ) 0xFFFFFD60 ) /* (SYSC) Voltage Regulator Power Mode Register */
+/* ========== Register definition for AIC peripheral ========== */
+#define AT91C_AIC_ICCR          ( ( AT91_REG * ) 0xFFFFF128 ) /* (AIC) Interrupt Clear Command Register */
+#define AT91C_AIC_IECR          ( ( AT91_REG * ) 0xFFFFF120 ) /* (AIC) Interrupt Enable Command Register */
+#define AT91C_AIC_SMR           ( ( AT91_REG * ) 0xFFFFF000 ) /* (AIC) Source Mode Register */
+#define AT91C_AIC_ISCR          ( ( AT91_REG * ) 0xFFFFF12C ) /* (AIC) Interrupt Set Command Register */
+#define AT91C_AIC_EOICR         ( ( AT91_REG * ) 0xFFFFF130 ) /* (AIC) End of Interrupt Command Register */
+#define AT91C_AIC_DCR           ( ( AT91_REG * ) 0xFFFFF138 ) /* (AIC) Debug Control Register (Protect) */
+#define AT91C_AIC_FFER          ( ( AT91_REG * ) 0xFFFFF140 ) /* (AIC) Fast Forcing Enable Register */
+#define AT91C_AIC_SVR           ( ( AT91_REG * ) 0xFFFFF080 ) /* (AIC) Source Vector Register */
+#define AT91C_AIC_SPU           ( ( AT91_REG * ) 0xFFFFF134 ) /* (AIC) Spurious Vector Register */
+#define AT91C_AIC_FFDR          ( ( AT91_REG * ) 0xFFFFF144 ) /* (AIC) Fast Forcing Disable Register */
+#define AT91C_AIC_FVR           ( ( AT91_REG * ) 0xFFFFF104 ) /* (AIC) FIQ Vector Register */
+#define AT91C_AIC_FFSR          ( ( AT91_REG * ) 0xFFFFF148 ) /* (AIC) Fast Forcing Status Register */
+#define AT91C_AIC_IMR           ( ( AT91_REG * ) 0xFFFFF110 ) /* (AIC) Interrupt Mask Register */
+#define AT91C_AIC_ISR           ( ( AT91_REG * ) 0xFFFFF108 ) /* (AIC) Interrupt Status Register */
+#define AT91C_AIC_IVR           ( ( AT91_REG * ) 0xFFFFF100 ) /* (AIC) IRQ Vector Register */
+#define AT91C_AIC_IDCR          ( ( AT91_REG * ) 0xFFFFF124 ) /* (AIC) Interrupt Disable Command Register */
+#define AT91C_AIC_CISR          ( ( AT91_REG * ) 0xFFFFF114 ) /* (AIC) Core Interrupt Status Register */
+#define AT91C_AIC_IPR           ( ( AT91_REG * ) 0xFFFFF10C ) /* (AIC) Interrupt Pending Register */
+/* ========== Register definition for DBGU peripheral ========== */
+#define AT91C_DBGU_C2R          ( ( AT91_REG * ) 0xFFFFF244 ) /* (DBGU) Chip ID2 Register */
+#define AT91C_DBGU_THR          ( ( AT91_REG * ) 0xFFFFF21C ) /* (DBGU) Transmitter Holding Register */
+#define AT91C_DBGU_CSR          ( ( AT91_REG * ) 0xFFFFF214 ) /* (DBGU) Channel Status Register */
+#define AT91C_DBGU_IDR          ( ( AT91_REG * ) 0xFFFFF20C ) /* (DBGU) Interrupt Disable Register */
+#define AT91C_DBGU_MR           ( ( AT91_REG * ) 0xFFFFF204 ) /* (DBGU) Mode Register */
+#define AT91C_DBGU_FNTR         ( ( AT91_REG * ) 0xFFFFF248 ) /* (DBGU) Force NTRST Register */
+#define AT91C_DBGU_C1R          ( ( AT91_REG * ) 0xFFFFF240 ) /* (DBGU) Chip ID1 Register */
+#define AT91C_DBGU_BRGR         ( ( AT91_REG * ) 0xFFFFF220 ) /* (DBGU) Baud Rate Generator Register */
+#define AT91C_DBGU_RHR          ( ( AT91_REG * ) 0xFFFFF218 ) /* (DBGU) Receiver Holding Register */
+#define AT91C_DBGU_IMR          ( ( AT91_REG * ) 0xFFFFF210 ) /* (DBGU) Interrupt Mask Register */
+#define AT91C_DBGU_IER          ( ( AT91_REG * ) 0xFFFFF208 ) /* (DBGU) Interrupt Enable Register */
+#define AT91C_DBGU_CR           ( ( AT91_REG * ) 0xFFFFF200 ) /* (DBGU) Control Register */
+/* ========== Register definition for PDC_DBGU peripheral ========== */
+#define AT91C_DBGU_TNCR         ( ( AT91_REG * ) 0xFFFFF31C ) /* (PDC_DBGU) Transmit Next Counter Register */
+#define AT91C_DBGU_RNCR         ( ( AT91_REG * ) 0xFFFFF314 ) /* (PDC_DBGU) Receive Next Counter Register */
+#define AT91C_DBGU_PTCR         ( ( AT91_REG * ) 0xFFFFF320 ) /* (PDC_DBGU) PDC Transfer Control Register */
+#define AT91C_DBGU_PTSR         ( ( AT91_REG * ) 0xFFFFF324 ) /* (PDC_DBGU) PDC Transfer Status Register */
+#define AT91C_DBGU_RCR          ( ( AT91_REG * ) 0xFFFFF304 ) /* (PDC_DBGU) Receive Counter Register */
+#define AT91C_DBGU_TCR          ( ( AT91_REG * ) 0xFFFFF30C ) /* (PDC_DBGU) Transmit Counter Register */
+#define AT91C_DBGU_RPR          ( ( AT91_REG * ) 0xFFFFF300 ) /* (PDC_DBGU) Receive Pointer Register */
+#define AT91C_DBGU_TPR          ( ( AT91_REG * ) 0xFFFFF308 ) /* (PDC_DBGU) Transmit Pointer Register */
+#define AT91C_DBGU_RNPR         ( ( AT91_REG * ) 0xFFFFF310 ) /* (PDC_DBGU) Receive Next Pointer Register */
+#define AT91C_DBGU_TNPR         ( ( AT91_REG * ) 0xFFFFF318 ) /* (PDC_DBGU) Transmit Next Pointer Register */
+/* ========== Register definition for PIOA peripheral ========== */
+#define AT91C_PIOA_IMR          ( ( AT91_REG * ) 0xFFFFF448 ) /* (PIOA) Interrupt Mask Register */
+#define AT91C_PIOA_IER          ( ( AT91_REG * ) 0xFFFFF440 ) /* (PIOA) Interrupt Enable Register */
+#define AT91C_PIOA_OWDR         ( ( AT91_REG * ) 0xFFFFF4A4 ) /* (PIOA) Output Write Disable Register */
+#define AT91C_PIOA_ISR          ( ( AT91_REG * ) 0xFFFFF44C ) /* (PIOA) Interrupt Status Register */
+#define AT91C_PIOA_PPUDR        ( ( AT91_REG * ) 0xFFFFF460 ) /* (PIOA) Pull-up Disable Register */
+#define AT91C_PIOA_MDSR         ( ( AT91_REG * ) 0xFFFFF458 ) /* (PIOA) Multi-driver Status Register */
+#define AT91C_PIOA_MDER         ( ( AT91_REG * ) 0xFFFFF450 ) /* (PIOA) Multi-driver Enable Register */
+#define AT91C_PIOA_PER          ( ( AT91_REG * ) 0xFFFFF400 ) /* (PIOA) PIO Enable Register */
+#define AT91C_PIOA_PSR          ( ( AT91_REG * ) 0xFFFFF408 ) /* (PIOA) PIO Status Register */
+#define AT91C_PIOA_OER          ( ( AT91_REG * ) 0xFFFFF410 ) /* (PIOA) Output Enable Register */
+#define AT91C_PIOA_BSR          ( ( AT91_REG * ) 0xFFFFF474 ) /* (PIOA) Select B Register */
+#define AT91C_PIOA_PPUER        ( ( AT91_REG * ) 0xFFFFF464 ) /* (PIOA) Pull-up Enable Register */
+#define AT91C_PIOA_MDDR         ( ( AT91_REG * ) 0xFFFFF454 ) /* (PIOA) Multi-driver Disable Register */
+#define AT91C_PIOA_PDR          ( ( AT91_REG * ) 0xFFFFF404 ) /* (PIOA) PIO Disable Register */
+#define AT91C_PIOA_ODR          ( ( AT91_REG * ) 0xFFFFF414 ) /* (PIOA) Output Disable Registerr */
+#define AT91C_PIOA_IFDR         ( ( AT91_REG * ) 0xFFFFF424 ) /* (PIOA) Input Filter Disable Register */
+#define AT91C_PIOA_ABSR         ( ( AT91_REG * ) 0xFFFFF478 ) /* (PIOA) AB Select Status Register */
+#define AT91C_PIOA_ASR          ( ( AT91_REG * ) 0xFFFFF470 ) /* (PIOA) Select A Register */
+#define AT91C_PIOA_PPUSR        ( ( AT91_REG * ) 0xFFFFF468 ) /* (PIOA) Pad Pull-up Status Register */
+#define AT91C_PIOA_ODSR         ( ( AT91_REG * ) 0xFFFFF438 ) /* (PIOA) Output Data Status Register */
+#define AT91C_PIOA_SODR         ( ( AT91_REG * ) 0xFFFFF430 ) /* (PIOA) Set Output Data Register */
+#define AT91C_PIOA_IFSR         ( ( AT91_REG * ) 0xFFFFF428 ) /* (PIOA) Input Filter Status Register */
+#define AT91C_PIOA_IFER         ( ( AT91_REG * ) 0xFFFFF420 ) /* (PIOA) Input Filter Enable Register */
+#define AT91C_PIOA_OSR          ( ( AT91_REG * ) 0xFFFFF418 ) /* (PIOA) Output Status Register */
+#define AT91C_PIOA_IDR          ( ( AT91_REG * ) 0xFFFFF444 ) /* (PIOA) Interrupt Disable Register */
+#define AT91C_PIOA_PDSR         ( ( AT91_REG * ) 0xFFFFF43C ) /* (PIOA) Pin Data Status Register */
+#define AT91C_PIOA_CODR         ( ( AT91_REG * ) 0xFFFFF434 ) /* (PIOA) Clear Output Data Register */
+#define AT91C_PIOA_OWSR         ( ( AT91_REG * ) 0xFFFFF4A8 ) /* (PIOA) Output Write Status Register */
+#define AT91C_PIOA_OWER         ( ( AT91_REG * ) 0xFFFFF4A0 ) /* (PIOA) Output Write Enable Register */
+/* ========== Register definition for CKGR peripheral ========== */
+#define AT91C_CKGR_PLLR         ( ( AT91_REG * ) 0xFFFFFC2C ) /* (CKGR) PLL Register */
+#define AT91C_CKGR_MCFR         ( ( AT91_REG * ) 0xFFFFFC24 ) /* (CKGR) Main Clock  Frequency Register */
+#define AT91C_CKGR_MOR          ( ( AT91_REG * ) 0xFFFFFC20 ) /* (CKGR) Main Oscillator Register */
+/* ========== Register definition for PMC peripheral ========== */
+#define AT91C_PMC_SCSR          ( ( AT91_REG * ) 0xFFFFFC08 ) /* (PMC) System Clock Status Register */
+#define AT91C_PMC_SCER          ( ( AT91_REG * ) 0xFFFFFC00 ) /* (PMC) System Clock Enable Register */
+#define AT91C_PMC_IMR           ( ( AT91_REG * ) 0xFFFFFC6C ) /* (PMC) Interrupt Mask Register */
+#define AT91C_PMC_IDR           ( ( AT91_REG * ) 0xFFFFFC64 ) /* (PMC) Interrupt Disable Register */
+#define AT91C_PMC_PCDR          ( ( AT91_REG * ) 0xFFFFFC14 ) /* (PMC) Peripheral Clock Disable Register */
+#define AT91C_PMC_SCDR          ( ( AT91_REG * ) 0xFFFFFC04 ) /* (PMC) System Clock Disable Register */
+#define AT91C_PMC_SR            ( ( AT91_REG * ) 0xFFFFFC68 ) /* (PMC) Status Register */
+#define AT91C_PMC_IER           ( ( AT91_REG * ) 0xFFFFFC60 ) /* (PMC) Interrupt Enable Register */
+#define AT91C_PMC_MCKR          ( ( AT91_REG * ) 0xFFFFFC30 ) /* (PMC) Master Clock Register */
+#define AT91C_PMC_MOR           ( ( AT91_REG * ) 0xFFFFFC20 ) /* (PMC) Main Oscillator Register */
+#define AT91C_PMC_PCER          ( ( AT91_REG * ) 0xFFFFFC10 ) /* (PMC) Peripheral Clock Enable Register */
+#define AT91C_PMC_PCSR          ( ( AT91_REG * ) 0xFFFFFC18 ) /* (PMC) Peripheral Clock Status Register */
+#define AT91C_PMC_PLLR          ( ( AT91_REG * ) 0xFFFFFC2C ) /* (PMC) PLL Register */
+#define AT91C_PMC_MCFR          ( ( AT91_REG * ) 0xFFFFFC24 ) /* (PMC) Main Clock  Frequency Register */
+#define AT91C_PMC_PCKR          ( ( AT91_REG * ) 0xFFFFFC40 ) /* (PMC) Programmable Clock Register */
+/* ========== Register definition for RSTC peripheral ========== */
+#define AT91C_RSTC_RSR          ( ( AT91_REG * ) 0xFFFFFD04 ) /* (RSTC) Reset Status Register */
+#define AT91C_RSTC_RMR          ( ( AT91_REG * ) 0xFFFFFD08 ) /* (RSTC) Reset Mode Register */
+#define AT91C_RSTC_RCR          ( ( AT91_REG * ) 0xFFFFFD00 ) /* (RSTC) Reset Control Register */
+/* ========== Register definition for RTTC peripheral ========== */
+#define AT91C_RTTC_RTSR         ( ( AT91_REG * ) 0xFFFFFD2C ) /* (RTTC) Real-time Status Register */
+#define AT91C_RTTC_RTAR         ( ( AT91_REG * ) 0xFFFFFD24 ) /* (RTTC) Real-time Alarm Register */
+#define AT91C_RTTC_RTVR         ( ( AT91_REG * ) 0xFFFFFD28 ) /* (RTTC) Real-time Value Register */
+#define AT91C_RTTC_RTMR         ( ( AT91_REG * ) 0xFFFFFD20 ) /* (RTTC) Real-time Mode Register */
+/* ========== Register definition for PITC peripheral ========== */
+#define AT91C_PITC_PIIR         ( ( AT91_REG * ) 0xFFFFFD3C ) /* (PITC) Period Interval Image Register */
+#define AT91C_PITC_PISR         ( ( AT91_REG * ) 0xFFFFFD34 ) /* (PITC) Period Interval Status Register */
+#define AT91C_PITC_PIVR         ( ( AT91_REG * ) 0xFFFFFD38 ) /* (PITC) Period Interval Value Register */
+#define AT91C_PITC_PIMR         ( ( AT91_REG * ) 0xFFFFFD30 ) /* (PITC) Period Interval Mode Register */
+/* ========== Register definition for WDTC peripheral ========== */
+#define AT91C_WDTC_WDMR         ( ( AT91_REG * ) 0xFFFFFD44 ) /* (WDTC) Watchdog Mode Register */
+#define AT91C_WDTC_WDSR         ( ( AT91_REG * ) 0xFFFFFD48 ) /* (WDTC) Watchdog Status Register */
+#define AT91C_WDTC_WDCR         ( ( AT91_REG * ) 0xFFFFFD40 ) /* (WDTC) Watchdog Control Register */
+/* ========== Register definition for MC peripheral ========== */
+#define AT91C_MC_FCR            ( ( AT91_REG * ) 0xFFFFFF64 ) /* (MC) MC Flash Command Register */
+#define AT91C_MC_ASR            ( ( AT91_REG * ) 0xFFFFFF04 ) /* (MC) MC Abort Status Register */
+#define AT91C_MC_FSR            ( ( AT91_REG * ) 0xFFFFFF68 ) /* (MC) MC Flash Status Register */
+#define AT91C_MC_FMR            ( ( AT91_REG * ) 0xFFFFFF60 ) /* (MC) MC Flash Mode Register */
+#define AT91C_MC_AASR           ( ( AT91_REG * ) 0xFFFFFF08 ) /* (MC) MC Abort Address Status Register */
+#define AT91C_MC_RCR            ( ( AT91_REG * ) 0xFFFFFF00 ) /* (MC) MC Remap Control Register */
+/* ========== Register definition for PDC_SPI peripheral ========== */
+#define AT91C_SPI_PTCR          ( ( AT91_REG * ) 0xFFFE0120 ) /* (PDC_SPI) PDC Transfer Control Register */
+#define AT91C_SPI_TNPR          ( ( AT91_REG * ) 0xFFFE0118 ) /* (PDC_SPI) Transmit Next Pointer Register */
+#define AT91C_SPI_RNPR          ( ( AT91_REG * ) 0xFFFE0110 ) /* (PDC_SPI) Receive Next Pointer Register */
+#define AT91C_SPI_TPR           ( ( AT91_REG * ) 0xFFFE0108 ) /* (PDC_SPI) Transmit Pointer Register */
+#define AT91C_SPI_RPR           ( ( AT91_REG * ) 0xFFFE0100 ) /* (PDC_SPI) Receive Pointer Register */
+#define AT91C_SPI_PTSR          ( ( AT91_REG * ) 0xFFFE0124 ) /* (PDC_SPI) PDC Transfer Status Register */
+#define AT91C_SPI_TNCR          ( ( AT91_REG * ) 0xFFFE011C ) /* (PDC_SPI) Transmit Next Counter Register */
+#define AT91C_SPI_RNCR          ( ( AT91_REG * ) 0xFFFE0114 ) /* (PDC_SPI) Receive Next Counter Register */
+#define AT91C_SPI_TCR           ( ( AT91_REG * ) 0xFFFE010C ) /* (PDC_SPI) Transmit Counter Register */
+#define AT91C_SPI_RCR           ( ( AT91_REG * ) 0xFFFE0104 ) /* (PDC_SPI) Receive Counter Register */
+/* ========== Register definition for SPI peripheral ========== */
+#define AT91C_SPI_CSR           ( ( AT91_REG * ) 0xFFFE0030 ) /* (SPI) Chip Select Register */
+#define AT91C_SPI_IDR           ( ( AT91_REG * ) 0xFFFE0018 ) /* (SPI) Interrupt Disable Register */
+#define AT91C_SPI_SR            ( ( AT91_REG * ) 0xFFFE0010 ) /* (SPI) Status Register */
+#define AT91C_SPI_RDR           ( ( AT91_REG * ) 0xFFFE0008 ) /* (SPI) Receive Data Register */
+#define AT91C_SPI_CR            ( ( AT91_REG * ) 0xFFFE0000 ) /* (SPI) Control Register */
+#define AT91C_SPI_IMR           ( ( AT91_REG * ) 0xFFFE001C ) /* (SPI) Interrupt Mask Register */
+#define AT91C_SPI_IER           ( ( AT91_REG * ) 0xFFFE0014 ) /* (SPI) Interrupt Enable Register */
+#define AT91C_SPI_TDR           ( ( AT91_REG * ) 0xFFFE000C ) /* (SPI) Transmit Data Register */
+#define AT91C_SPI_MR            ( ( AT91_REG * ) 0xFFFE0004 ) /* (SPI) Mode Register */
+/* ========== Register definition for PDC_ADC peripheral ========== */
+#define AT91C_ADC_PTCR          ( ( AT91_REG * ) 0xFFFD8120 ) /* (PDC_ADC) PDC Transfer Control Register */
+#define AT91C_ADC_TNPR          ( ( AT91_REG * ) 0xFFFD8118 ) /* (PDC_ADC) Transmit Next Pointer Register */
+#define AT91C_ADC_RNPR          ( ( AT91_REG * ) 0xFFFD8110 ) /* (PDC_ADC) Receive Next Pointer Register */
+#define AT91C_ADC_TPR           ( ( AT91_REG * ) 0xFFFD8108 ) /* (PDC_ADC) Transmit Pointer Register */
+#define AT91C_ADC_RPR           ( ( AT91_REG * ) 0xFFFD8100 ) /* (PDC_ADC) Receive Pointer Register */
+#define AT91C_ADC_PTSR          ( ( AT91_REG * ) 0xFFFD8124 ) /* (PDC_ADC) PDC Transfer Status Register */
+#define AT91C_ADC_TNCR          ( ( AT91_REG * ) 0xFFFD811C ) /* (PDC_ADC) Transmit Next Counter Register */
+#define AT91C_ADC_RNCR          ( ( AT91_REG * ) 0xFFFD8114 ) /* (PDC_ADC) Receive Next Counter Register */
+#define AT91C_ADC_TCR           ( ( AT91_REG * ) 0xFFFD810C ) /* (PDC_ADC) Transmit Counter Register */
+#define AT91C_ADC_RCR           ( ( AT91_REG * ) 0xFFFD8104 ) /* (PDC_ADC) Receive Counter Register */
+/* ========== Register definition for ADC peripheral ========== */
+#define AT91C_ADC_IMR           ( ( AT91_REG * ) 0xFFFD802C ) /* (ADC) ADC Interrupt Mask Register */
+#define AT91C_ADC_CDR4          ( ( AT91_REG * ) 0xFFFD8040 ) /* (ADC) ADC Channel Data Register 4 */
+#define AT91C_ADC_CDR2          ( ( AT91_REG * ) 0xFFFD8038 ) /* (ADC) ADC Channel Data Register 2 */
+#define AT91C_ADC_CDR0          ( ( AT91_REG * ) 0xFFFD8030 ) /* (ADC) ADC Channel Data Register 0 */
+#define AT91C_ADC_CDR7          ( ( AT91_REG * ) 0xFFFD804C ) /* (ADC) ADC Channel Data Register 7 */
+#define AT91C_ADC_CDR1          ( ( AT91_REG * ) 0xFFFD8034 ) /* (ADC) ADC Channel Data Register 1 */
+#define AT91C_ADC_CDR3          ( ( AT91_REG * ) 0xFFFD803C ) /* (ADC) ADC Channel Data Register 3 */
+#define AT91C_ADC_CDR5          ( ( AT91_REG * ) 0xFFFD8044 ) /* (ADC) ADC Channel Data Register 5 */
+#define AT91C_ADC_MR            ( ( AT91_REG * ) 0xFFFD8004 ) /* (ADC) ADC Mode Register */
+#define AT91C_ADC_CDR6          ( ( AT91_REG * ) 0xFFFD8048 ) /* (ADC) ADC Channel Data Register 6 */
+#define AT91C_ADC_CR            ( ( AT91_REG * ) 0xFFFD8000 ) /* (ADC) ADC Control Register */
+#define AT91C_ADC_CHER          ( ( AT91_REG * ) 0xFFFD8010 ) /* (ADC) ADC Channel Enable Register */
+#define AT91C_ADC_CHSR          ( ( AT91_REG * ) 0xFFFD8018 ) /* (ADC) ADC Channel Status Register */
+#define AT91C_ADC_IER           ( ( AT91_REG * ) 0xFFFD8024 ) /* (ADC) ADC Interrupt Enable Register */
+#define AT91C_ADC_SR            ( ( AT91_REG * ) 0xFFFD801C ) /* (ADC) ADC Status Register */
+#define AT91C_ADC_CHDR          ( ( AT91_REG * ) 0xFFFD8014 ) /* (ADC) ADC Channel Disable Register */
+#define AT91C_ADC_IDR           ( ( AT91_REG * ) 0xFFFD8028 ) /* (ADC) ADC Interrupt Disable Register */
+#define AT91C_ADC_LCDR          ( ( AT91_REG * ) 0xFFFD8020 ) /* (ADC) ADC Last Converted Data Register */
+/* ========== Register definition for PDC_SSC peripheral ========== */
+#define AT91C_SSC_PTCR          ( ( AT91_REG * ) 0xFFFD4120 ) /* (PDC_SSC) PDC Transfer Control Register */
+#define AT91C_SSC_TNPR          ( ( AT91_REG * ) 0xFFFD4118 ) /* (PDC_SSC) Transmit Next Pointer Register */
+#define AT91C_SSC_RNPR          ( ( AT91_REG * ) 0xFFFD4110 ) /* (PDC_SSC) Receive Next Pointer Register */
+#define AT91C_SSC_TPR           ( ( AT91_REG * ) 0xFFFD4108 ) /* (PDC_SSC) Transmit Pointer Register */
+#define AT91C_SSC_RPR           ( ( AT91_REG * ) 0xFFFD4100 ) /* (PDC_SSC) Receive Pointer Register */
+#define AT91C_SSC_PTSR          ( ( AT91_REG * ) 0xFFFD4124 ) /* (PDC_SSC) PDC Transfer Status Register */
+#define AT91C_SSC_TNCR          ( ( AT91_REG * ) 0xFFFD411C ) /* (PDC_SSC) Transmit Next Counter Register */
+#define AT91C_SSC_RNCR          ( ( AT91_REG * ) 0xFFFD4114 ) /* (PDC_SSC) Receive Next Counter Register */
+#define AT91C_SSC_TCR           ( ( AT91_REG * ) 0xFFFD410C ) /* (PDC_SSC) Transmit Counter Register */
+#define AT91C_SSC_RCR           ( ( AT91_REG * ) 0xFFFD4104 ) /* (PDC_SSC) Receive Counter Register */
+/* ========== Register definition for SSC peripheral ========== */
+#define AT91C_SSC_RFMR          ( ( AT91_REG * ) 0xFFFD4014 ) /* (SSC) Receive Frame Mode Register */
+#define AT91C_SSC_CMR           ( ( AT91_REG * ) 0xFFFD4004 ) /* (SSC) Clock Mode Register */
+#define AT91C_SSC_IDR           ( ( AT91_REG * ) 0xFFFD4048 ) /* (SSC) Interrupt Disable Register */
+#define AT91C_SSC_SR            ( ( AT91_REG * ) 0xFFFD4040 ) /* (SSC) Status Register */
+#define AT91C_SSC_RC0R          ( ( AT91_REG * ) 0xFFFD4038 ) /* (SSC) Receive Compare 0 Register */
+#define AT91C_SSC_RSHR          ( ( AT91_REG * ) 0xFFFD4030 ) /* (SSC) Receive Sync Holding Register */
+#define AT91C_SSC_RHR           ( ( AT91_REG * ) 0xFFFD4020 ) /* (SSC) Receive Holding Register */
+#define AT91C_SSC_TCMR          ( ( AT91_REG * ) 0xFFFD4018 ) /* (SSC) Transmit Clock Mode Register */
+#define AT91C_SSC_RCMR          ( ( AT91_REG * ) 0xFFFD4010 ) /* (SSC) Receive Clock ModeRegister */
+#define AT91C_SSC_CR            ( ( AT91_REG * ) 0xFFFD4000 ) /* (SSC) Control Register */
+#define AT91C_SSC_IMR           ( ( AT91_REG * ) 0xFFFD404C ) /* (SSC) Interrupt Mask Register */
+#define AT91C_SSC_IER           ( ( AT91_REG * ) 0xFFFD4044 ) /* (SSC) Interrupt Enable Register */
+#define AT91C_SSC_RC1R          ( ( AT91_REG * ) 0xFFFD403C ) /* (SSC) Receive Compare 1 Register */
+#define AT91C_SSC_TSHR          ( ( AT91_REG * ) 0xFFFD4034 ) /* (SSC) Transmit Sync Holding Register */
+#define AT91C_SSC_THR           ( ( AT91_REG * ) 0xFFFD4024 ) /* (SSC) Transmit Holding Register */
+#define AT91C_SSC_TFMR          ( ( AT91_REG * ) 0xFFFD401C ) /* (SSC) Transmit Frame Mode Register */
+/* ========== Register definition for PDC_US1 peripheral ========== */
+#define AT91C_US1_PTSR          ( ( AT91_REG * ) 0xFFFC4124 ) /* (PDC_US1) PDC Transfer Status Register */
+#define AT91C_US1_TNCR          ( ( AT91_REG * ) 0xFFFC411C ) /* (PDC_US1) Transmit Next Counter Register */
+#define AT91C_US1_RNCR          ( ( AT91_REG * ) 0xFFFC4114 ) /* (PDC_US1) Receive Next Counter Register */
+#define AT91C_US1_TCR           ( ( AT91_REG * ) 0xFFFC410C ) /* (PDC_US1) Transmit Counter Register */
+#define AT91C_US1_RCR           ( ( AT91_REG * ) 0xFFFC4104 ) /* (PDC_US1) Receive Counter Register */
+#define AT91C_US1_PTCR          ( ( AT91_REG * ) 0xFFFC4120 ) /* (PDC_US1) PDC Transfer Control Register */
+#define AT91C_US1_TNPR          ( ( AT91_REG * ) 0xFFFC4118 ) /* (PDC_US1) Transmit Next Pointer Register */
+#define AT91C_US1_RNPR          ( ( AT91_REG * ) 0xFFFC4110 ) /* (PDC_US1) Receive Next Pointer Register */
+#define AT91C_US1_TPR           ( ( AT91_REG * ) 0xFFFC4108 ) /* (PDC_US1) Transmit Pointer Register */
+#define AT91C_US1_RPR           ( ( AT91_REG * ) 0xFFFC4100 ) /* (PDC_US1) Receive Pointer Register */
+/* ========== Register definition for US1 peripheral ========== */
+#define AT91C_US1_XXR           ( ( AT91_REG * ) 0xFFFC4048 ) /* (US1) XON_XOFF Register */
+#define AT91C_US1_RHR           ( ( AT91_REG * ) 0xFFFC4018 ) /* (US1) Receiver Holding Register */
+#define AT91C_US1_IMR           ( ( AT91_REG * ) 0xFFFC4010 ) /* (US1) Interrupt Mask Register */
+#define AT91C_US1_IER           ( ( AT91_REG * ) 0xFFFC4008 ) /* (US1) Interrupt Enable Register */
+#define AT91C_US1_CR            ( ( AT91_REG * ) 0xFFFC4000 ) /* (US1) Control Register */
+#define AT91C_US1_RTOR          ( ( AT91_REG * ) 0xFFFC4024 ) /* (US1) Receiver Time-out Register */
+#define AT91C_US1_THR           ( ( AT91_REG * ) 0xFFFC401C ) /* (US1) Transmitter Holding Register */
+#define AT91C_US1_CSR           ( ( AT91_REG * ) 0xFFFC4014 ) /* (US1) Channel Status Register */
+#define AT91C_US1_IDR           ( ( AT91_REG * ) 0xFFFC400C ) /* (US1) Interrupt Disable Register */
+#define AT91C_US1_FIDI          ( ( AT91_REG * ) 0xFFFC4040 ) /* (US1) FI_DI_Ratio Register */
+#define AT91C_US1_BRGR          ( ( AT91_REG * ) 0xFFFC4020 ) /* (US1) Baud Rate Generator Register */
+#define AT91C_US1_TTGR          ( ( AT91_REG * ) 0xFFFC4028 ) /* (US1) Transmitter Time-guard Register */
+#define AT91C_US1_IF            ( ( AT91_REG * ) 0xFFFC404C ) /* (US1) IRDA_FILTER Register */
+#define AT91C_US1_NER           ( ( AT91_REG * ) 0xFFFC4044 ) /* (US1) Nb Errors Register */
+#define AT91C_US1_MR            ( ( AT91_REG * ) 0xFFFC4004 ) /* (US1) Mode Register */
+/* ========== Register definition for PDC_US0 peripheral ========== */
+#define AT91C_US0_PTCR          ( ( AT91_REG * ) 0xFFFC0120 ) /* (PDC_US0) PDC Transfer Control Register */
+#define AT91C_US0_TNPR          ( ( AT91_REG * ) 0xFFFC0118 ) /* (PDC_US0) Transmit Next Pointer Register */
+#define AT91C_US0_RNPR          ( ( AT91_REG * ) 0xFFFC0110 ) /* (PDC_US0) Receive Next Pointer Register */
+#define AT91C_US0_TPR           ( ( AT91_REG * ) 0xFFFC0108 ) /* (PDC_US0) Transmit Pointer Register */
+#define AT91C_US0_RPR           ( ( AT91_REG * ) 0xFFFC0100 ) /* (PDC_US0) Receive Pointer Register */
+#define AT91C_US0_PTSR          ( ( AT91_REG * ) 0xFFFC0124 ) /* (PDC_US0) PDC Transfer Status Register */
+#define AT91C_US0_TNCR          ( ( AT91_REG * ) 0xFFFC011C ) /* (PDC_US0) Transmit Next Counter Register */
+#define AT91C_US0_RNCR          ( ( AT91_REG * ) 0xFFFC0114 ) /* (PDC_US0) Receive Next Counter Register */
+#define AT91C_US0_TCR           ( ( AT91_REG * ) 0xFFFC010C ) /* (PDC_US0) Transmit Counter Register */
+#define AT91C_US0_RCR           ( ( AT91_REG * ) 0xFFFC0104 ) /* (PDC_US0) Receive Counter Register */
+/* ========== Register definition for US0 peripheral ========== */
+#define AT91C_US0_TTGR          ( ( AT91_REG * ) 0xFFFC0028 ) /* (US0) Transmitter Time-guard Register */
+#define AT91C_US0_BRGR          ( ( AT91_REG * ) 0xFFFC0020 ) /* (US0) Baud Rate Generator Register */
+#define AT91C_US0_RHR           ( ( AT91_REG * ) 0xFFFC0018 ) /* (US0) Receiver Holding Register */
+#define AT91C_US0_IMR           ( ( AT91_REG * ) 0xFFFC0010 ) /* (US0) Interrupt Mask Register */
+#define AT91C_US0_NER           ( ( AT91_REG * ) 0xFFFC0044 ) /* (US0) Nb Errors Register */
+#define AT91C_US0_RTOR          ( ( AT91_REG * ) 0xFFFC0024 ) /* (US0) Receiver Time-out Register */
+#define AT91C_US0_XXR           ( ( AT91_REG * ) 0xFFFC0048 ) /* (US0) XON_XOFF Register */
+#define AT91C_US0_FIDI          ( ( AT91_REG * ) 0xFFFC0040 ) /* (US0) FI_DI_Ratio Register */
+#define AT91C_US0_CR            ( ( AT91_REG * ) 0xFFFC0000 ) /* (US0) Control Register */
+#define AT91C_US0_IER           ( ( AT91_REG * ) 0xFFFC0008 ) /* (US0) Interrupt Enable Register */
+#define AT91C_US0_IF            ( ( AT91_REG * ) 0xFFFC004C ) /* (US0) IRDA_FILTER Register */
+#define AT91C_US0_MR            ( ( AT91_REG * ) 0xFFFC0004 ) /* (US0) Mode Register */
+#define AT91C_US0_IDR           ( ( AT91_REG * ) 0xFFFC000C ) /* (US0) Interrupt Disable Register */
+#define AT91C_US0_CSR           ( ( AT91_REG * ) 0xFFFC0014 ) /* (US0) Channel Status Register */
+#define AT91C_US0_THR           ( ( AT91_REG * ) 0xFFFC001C ) /* (US0) Transmitter Holding Register */
+/* ========== Register definition for TWI peripheral ========== */
+#define AT91C_TWI_RHR           ( ( AT91_REG * ) 0xFFFB8030 ) /* (TWI) Receive Holding Register */
+#define AT91C_TWI_IDR           ( ( AT91_REG * ) 0xFFFB8028 ) /* (TWI) Interrupt Disable Register */
+#define AT91C_TWI_SR            ( ( AT91_REG * ) 0xFFFB8020 ) /* (TWI) Status Register */
+#define AT91C_TWI_CWGR          ( ( AT91_REG * ) 0xFFFB8010 ) /* (TWI) Clock Waveform Generator Register */
+#define AT91C_TWI_SMR           ( ( AT91_REG * ) 0xFFFB8008 ) /* (TWI) Slave Mode Register */
+#define AT91C_TWI_CR            ( ( AT91_REG * ) 0xFFFB8000 ) /* (TWI) Control Register */
+#define AT91C_TWI_THR           ( ( AT91_REG * ) 0xFFFB8034 ) /* (TWI) Transmit Holding Register */
+#define AT91C_TWI_IMR           ( ( AT91_REG * ) 0xFFFB802C ) /* (TWI) Interrupt Mask Register */
+#define AT91C_TWI_IER           ( ( AT91_REG * ) 0xFFFB8024 ) /* (TWI) Interrupt Enable Register */
+#define AT91C_TWI_IADR          ( ( AT91_REG * ) 0xFFFB800C ) /* (TWI) Internal Address Register */
+#define AT91C_TWI_MMR           ( ( AT91_REG * ) 0xFFFB8004 ) /* (TWI) Master Mode Register */
+/* ========== Register definition for TC2 peripheral ========== */
+#define AT91C_TC2_IMR           ( ( AT91_REG * ) 0xFFFA00AC ) /* (TC2) Interrupt Mask Register */
+#define AT91C_TC2_IER           ( ( AT91_REG * ) 0xFFFA00A4 ) /* (TC2) Interrupt Enable Register */
+#define AT91C_TC2_RC            ( ( AT91_REG * ) 0xFFFA009C ) /* (TC2) Register C */
+#define AT91C_TC2_RA            ( ( AT91_REG * ) 0xFFFA0094 ) /* (TC2) Register A */
+#define AT91C_TC2_CMR           ( ( AT91_REG * ) 0xFFFA0084 ) /* (TC2) Channel Mode Register (Capture Mode / Waveform Mode) */
+#define AT91C_TC2_IDR           ( ( AT91_REG * ) 0xFFFA00A8 ) /* (TC2) Interrupt Disable Register */
+#define AT91C_TC2_SR            ( ( AT91_REG * ) 0xFFFA00A0 ) /* (TC2) Status Register */
+#define AT91C_TC2_RB            ( ( AT91_REG * ) 0xFFFA0098 ) /* (TC2) Register B */
+#define AT91C_TC2_CV            ( ( AT91_REG * ) 0xFFFA0090 ) /* (TC2) Counter Value */
+#define AT91C_TC2_CCR           ( ( AT91_REG * ) 0xFFFA0080 ) /* (TC2) Channel Control Register */
+/* ========== Register definition for TC1 peripheral ========== */
+#define AT91C_TC1_IMR           ( ( AT91_REG * ) 0xFFFA006C ) /* (TC1) Interrupt Mask Register */
+#define AT91C_TC1_IER           ( ( AT91_REG * ) 0xFFFA0064 ) /* (TC1) Interrupt Enable Register */
+#define AT91C_TC1_RC            ( ( AT91_REG * ) 0xFFFA005C ) /* (TC1) Register C */
+#define AT91C_TC1_RA            ( ( AT91_REG * ) 0xFFFA0054 ) /* (TC1) Register A */
+#define AT91C_TC1_CMR           ( ( AT91_REG * ) 0xFFFA0044 ) /* (TC1) Channel Mode Register (Capture Mode / Waveform Mode) */
+#define AT91C_TC1_IDR           ( ( AT91_REG * ) 0xFFFA0068 ) /* (TC1) Interrupt Disable Register */
+#define AT91C_TC1_SR            ( ( AT91_REG * ) 0xFFFA0060 ) /* (TC1) Status Register */
+#define AT91C_TC1_RB            ( ( AT91_REG * ) 0xFFFA0058 ) /* (TC1) Register B */
+#define AT91C_TC1_CV            ( ( AT91_REG * ) 0xFFFA0050 ) /* (TC1) Counter Value */
+#define AT91C_TC1_CCR           ( ( AT91_REG * ) 0xFFFA0040 ) /* (TC1) Channel Control Register */
+/* ========== Register definition for TC0 peripheral ========== */
+#define AT91C_TC0_IMR           ( ( AT91_REG * ) 0xFFFA002C ) /* (TC0) Interrupt Mask Register */
+#define AT91C_TC0_IER           ( ( AT91_REG * ) 0xFFFA0024 ) /* (TC0) Interrupt Enable Register */
+#define AT91C_TC0_RC            ( ( AT91_REG * ) 0xFFFA001C ) /* (TC0) Register C */
+#define AT91C_TC0_RA            ( ( AT91_REG * ) 0xFFFA0014 ) /* (TC0) Register A */
+#define AT91C_TC0_CMR           ( ( AT91_REG * ) 0xFFFA0004 ) /* (TC0) Channel Mode Register (Capture Mode / Waveform Mode) */
+#define AT91C_TC0_IDR           ( ( AT91_REG * ) 0xFFFA0028 ) /* (TC0) Interrupt Disable Register */
+#define AT91C_TC0_SR            ( ( AT91_REG * ) 0xFFFA0020 ) /* (TC0) Status Register */
+#define AT91C_TC0_RB            ( ( AT91_REG * ) 0xFFFA0018 ) /* (TC0) Register B */
+#define AT91C_TC0_CV            ( ( AT91_REG * ) 0xFFFA0010 ) /* (TC0) Counter Value */
+#define AT91C_TC0_CCR           ( ( AT91_REG * ) 0xFFFA0000 ) /* (TC0) Channel Control Register */
+/* ========== Register definition for TCB peripheral ========== */
+#define AT91C_TCB_BMR           ( ( AT91_REG * ) 0xFFFA00C4 ) /* (TCB) TC Block Mode Register */
+#define AT91C_TCB_BCR           ( ( AT91_REG * ) 0xFFFA00C0 ) /* (TCB) TC Block Control Register */
+/* ========== Register definition for PWMC_CH3 peripheral ========== */
+#define AT91C_CH3_CUPDR         ( ( AT91_REG * ) 0xFFFCC270 ) /* (PWMC_CH3) Channel Update Register */
+#define AT91C_CH3_CPRDR         ( ( AT91_REG * ) 0xFFFCC268 ) /* (PWMC_CH3) Channel Period Register */
+#define AT91C_CH3_CMR           ( ( AT91_REG * ) 0xFFFCC260 ) /* (PWMC_CH3) Channel Mode Register */
+#define AT91C_CH3_Reserved      ( ( AT91_REG * ) 0xFFFCC274 ) /* (PWMC_CH3) Reserved */
+#define AT91C_CH3_CCNTR         ( ( AT91_REG * ) 0xFFFCC26C ) /* (PWMC_CH3) Channel Counter Register */
+#define AT91C_CH3_CDTYR         ( ( AT91_REG * ) 0xFFFCC264 ) /* (PWMC_CH3) Channel Duty Cycle Register */
+/* ========== Register definition for PWMC_CH2 peripheral ========== */
+#define AT91C_CH2_CUPDR         ( ( AT91_REG * ) 0xFFFCC250 ) /* (PWMC_CH2) Channel Update Register */
+#define AT91C_CH2_CPRDR         ( ( AT91_REG * ) 0xFFFCC248 ) /* (PWMC_CH2) Channel Period Register */
+#define AT91C_CH2_CMR           ( ( AT91_REG * ) 0xFFFCC240 ) /* (PWMC_CH2) Channel Mode Register */
+#define AT91C_CH2_Reserved      ( ( AT91_REG * ) 0xFFFCC254 ) /* (PWMC_CH2) Reserved */
+#define AT91C_CH2_CCNTR         ( ( AT91_REG * ) 0xFFFCC24C ) /* (PWMC_CH2) Channel Counter Register */
+#define AT91C_CH2_CDTYR         ( ( AT91_REG * ) 0xFFFCC244 ) /* (PWMC_CH2) Channel Duty Cycle Register */
+/* ========== Register definition for PWMC_CH1 peripheral ========== */
+#define AT91C_CH1_CUPDR         ( ( AT91_REG * ) 0xFFFCC230 ) /* (PWMC_CH1) Channel Update Register */
+#define AT91C_CH1_CPRDR         ( ( AT91_REG * ) 0xFFFCC228 ) /* (PWMC_CH1) Channel Period Register */
+#define AT91C_CH1_CMR           ( ( AT91_REG * ) 0xFFFCC220 ) /* (PWMC_CH1) Channel Mode Register */
+#define AT91C_CH1_Reserved      ( ( AT91_REG * ) 0xFFFCC234 ) /* (PWMC_CH1) Reserved */
+#define AT91C_CH1_CCNTR         ( ( AT91_REG * ) 0xFFFCC22C ) /* (PWMC_CH1) Channel Counter Register */
+#define AT91C_CH1_CDTYR         ( ( AT91_REG * ) 0xFFFCC224 ) /* (PWMC_CH1) Channel Duty Cycle Register */
+/* ========== Register definition for PWMC_CH0 peripheral ========== */
+#define AT91C_CH0_CUPDR         ( ( AT91_REG * ) 0xFFFCC210 ) /* (PWMC_CH0) Channel Update Register */
+#define AT91C_CH0_CPRDR         ( ( AT91_REG * ) 0xFFFCC208 ) /* (PWMC_CH0) Channel Period Register */
+#define AT91C_CH0_CMR           ( ( AT91_REG * ) 0xFFFCC200 ) /* (PWMC_CH0) Channel Mode Register */
+#define AT91C_CH0_Reserved      ( ( AT91_REG * ) 0xFFFCC214 ) /* (PWMC_CH0) Reserved */
+#define AT91C_CH0_CCNTR         ( ( AT91_REG * ) 0xFFFCC20C ) /* (PWMC_CH0) Channel Counter Register */
+#define AT91C_CH0_CDTYR         ( ( AT91_REG * ) 0xFFFCC204 ) /* (PWMC_CH0) Channel Duty Cycle Register */
+/* ========== Register definition for PWMC peripheral ========== */
+#define AT91C_PWMC_VR           ( ( AT91_REG * ) 0xFFFCC0FC ) /* (PWMC) PWMC Version Register */
+#define AT91C_PWMC_ISR          ( ( AT91_REG * ) 0xFFFCC01C ) /* (PWMC) PWMC Interrupt Status Register */
+#define AT91C_PWMC_IDR          ( ( AT91_REG * ) 0xFFFCC014 ) /* (PWMC) PWMC Interrupt Disable Register */
+#define AT91C_PWMC_SR           ( ( AT91_REG * ) 0xFFFCC00C ) /* (PWMC) PWMC Status Register */
+#define AT91C_PWMC_ENA          ( ( AT91_REG * ) 0xFFFCC004 ) /* (PWMC) PWMC Enable Register */
+#define AT91C_PWMC_IMR          ( ( AT91_REG * ) 0xFFFCC018 ) /* (PWMC) PWMC Interrupt Mask Register */
+#define AT91C_PWMC_MR           ( ( AT91_REG * ) 0xFFFCC000 ) /* (PWMC) PWMC Mode Register */
+#define AT91C_PWMC_DIS          ( ( AT91_REG * ) 0xFFFCC008 ) /* (PWMC) PWMC Disable Register */
+#define AT91C_PWMC_IER          ( ( AT91_REG * ) 0xFFFCC010 ) /* (PWMC) PWMC Interrupt Enable Register */
+/* ========== Register definition for UDP peripheral ========== */
+#define AT91C_UDP_ISR           ( ( AT91_REG * ) 0xFFFB001C ) /* (UDP) Interrupt Status Register */
+#define AT91C_UDP_IDR           ( ( AT91_REG * ) 0xFFFB0014 ) /* (UDP) Interrupt Disable Register */
+#define AT91C_UDP_GLBSTATE      ( ( AT91_REG * ) 0xFFFB0004 ) /* (UDP) Global State Register */
+#define AT91C_UDP_FDR           ( ( AT91_REG * ) 0xFFFB0050 ) /* (UDP) Endpoint FIFO Data Register */
+#define AT91C_UDP_CSR           ( ( AT91_REG * ) 0xFFFB0030 ) /* (UDP) Endpoint Control and Status Register */
+#define AT91C_UDP_RSTEP         ( ( AT91_REG * ) 0xFFFB0028 ) /* (UDP) Reset Endpoint Register */
+#define AT91C_UDP_ICR           ( ( AT91_REG * ) 0xFFFB0020 ) /* (UDP) Interrupt Clear Register */
+#define AT91C_UDP_IMR           ( ( AT91_REG * ) 0xFFFB0018 ) /* (UDP) Interrupt Mask Register */
+#define AT91C_UDP_IER           ( ( AT91_REG * ) 0xFFFB0010 ) /* (UDP) Interrupt Enable Register */
+#define AT91C_UDP_FADDR         ( ( AT91_REG * ) 0xFFFB0008 ) /* (UDP) Function Address Register */
+#define AT91C_UDP_NUM           ( ( AT91_REG * ) 0xFFFB0000 ) /* (UDP) Frame Number Register */
 
-// *****************************************************************************
-//               PIO DEFINITIONS FOR AT91SAM7S64
-// *****************************************************************************
-#define AT91C_PIO_PA0        ((unsigned int) 1 <<  0) // Pin Controlled by PA0
-#define AT91C_PA0_PWM0     ((unsigned int) AT91C_PIO_PA0) //  PWM Channel 0
-#define AT91C_PA0_TIOA0    ((unsigned int) AT91C_PIO_PA0) //  Timer Counter 0 Multipurpose Timer I/O Pin A
-#define AT91C_PIO_PA1        ((unsigned int) 1 <<  1) // Pin Controlled by PA1
-#define AT91C_PA1_PWM1     ((unsigned int) AT91C_PIO_PA1) //  PWM Channel 1
-#define AT91C_PA1_TIOB0    ((unsigned int) AT91C_PIO_PA1) //  Timer Counter 0 Multipurpose Timer I/O Pin B
-#define AT91C_PIO_PA10       ((unsigned int) 1 << 10) // Pin Controlled by PA10
-#define AT91C_PA10_DTXD     ((unsigned int) AT91C_PIO_PA10) //  DBGU Debug Transmit Data
-#define AT91C_PA10_NPCS2    ((unsigned int) AT91C_PIO_PA10) //  SPI Peripheral Chip Select 2
-#define AT91C_PIO_PA11       ((unsigned int) 1 << 11) // Pin Controlled by PA11
-#define AT91C_PA11_NPCS0    ((unsigned int) AT91C_PIO_PA11) //  SPI Peripheral Chip Select 0
-#define AT91C_PA11_PWM0     ((unsigned int) AT91C_PIO_PA11) //  PWM Channel 0
-#define AT91C_PIO_PA12       ((unsigned int) 1 << 12) // Pin Controlled by PA12
-#define AT91C_PA12_MISO     ((unsigned int) AT91C_PIO_PA12) //  SPI Master In Slave
-#define AT91C_PA12_PWM1     ((unsigned int) AT91C_PIO_PA12) //  PWM Channel 1
-#define AT91C_PIO_PA13       ((unsigned int) 1 << 13) // Pin Controlled by PA13
-#define AT91C_PA13_MOSI     ((unsigned int) AT91C_PIO_PA13) //  SPI Master Out Slave
-#define AT91C_PA13_PWM2     ((unsigned int) AT91C_PIO_PA13) //  PWM Channel 2
-#define AT91C_PIO_PA14       ((unsigned int) 1 << 14) // Pin Controlled by PA14
-#define AT91C_PA14_SPCK     ((unsigned int) AT91C_PIO_PA14) //  SPI Serial Clock
-#define AT91C_PA14_PWM3     ((unsigned int) AT91C_PIO_PA14) //  PWM Channel 3
-#define AT91C_PIO_PA15       ((unsigned int) 1 << 15) // Pin Controlled by PA15
-#define AT91C_PA15_TF       ((unsigned int) AT91C_PIO_PA15) //  SSC Transmit Frame Sync
-#define AT91C_PA15_TIOA1    ((unsigned int) AT91C_PIO_PA15) //  Timer Counter 1 Multipurpose Timer I/O Pin A
-#define AT91C_PIO_PA16       ((unsigned int) 1 << 16) // Pin Controlled by PA16
-#define AT91C_PA16_TK       ((unsigned int) AT91C_PIO_PA16) //  SSC Transmit Clock
-#define AT91C_PA16_TIOB1    ((unsigned int) AT91C_PIO_PA16) //  Timer Counter 1 Multipurpose Timer I/O Pin B
-#define AT91C_PIO_PA17       ((unsigned int) 1 << 17) // Pin Controlled by PA17
-#define AT91C_PA17_TD       ((unsigned int) AT91C_PIO_PA17) //  SSC Transmit data
-#define AT91C_PA17_PCK1     ((unsigned int) AT91C_PIO_PA17) //  PMC Programmable Clock Output 1
-#define AT91C_PIO_PA18       ((unsigned int) 1 << 18) // Pin Controlled by PA18
-#define AT91C_PA18_RD       ((unsigned int) AT91C_PIO_PA18) //  SSC Receive Data
-#define AT91C_PA18_PCK2     ((unsigned int) AT91C_PIO_PA18) //  PMC Programmable Clock Output 2
-#define AT91C_PIO_PA19       ((unsigned int) 1 << 19) // Pin Controlled by PA19
-#define AT91C_PA19_RK       ((unsigned int) AT91C_PIO_PA19) //  SSC Receive Clock
-#define AT91C_PA19_FIQ      ((unsigned int) AT91C_PIO_PA19) //  AIC Fast Interrupt Input
-#define AT91C_PIO_PA2        ((unsigned int) 1 <<  2) // Pin Controlled by PA2
-#define AT91C_PA2_PWM2     ((unsigned int) AT91C_PIO_PA2) //  PWM Channel 2
-#define AT91C_PA2_SCK0     ((unsigned int) AT91C_PIO_PA2) //  USART 0 Serial Clock
-#define AT91C_PIO_PA20       ((unsigned int) 1 << 20) // Pin Controlled by PA20
-#define AT91C_PA20_RF       ((unsigned int) AT91C_PIO_PA20) //  SSC Receive Frame Sync
-#define AT91C_PA20_IRQ0     ((unsigned int) AT91C_PIO_PA20) //  External Interrupt 0
-#define AT91C_PIO_PA21       ((unsigned int) 1 << 21) // Pin Controlled by PA21
-#define AT91C_PA21_RXD1     ((unsigned int) AT91C_PIO_PA21) //  USART 1 Receive Data
-#define AT91C_PA21_PCK1     ((unsigned int) AT91C_PIO_PA21) //  PMC Programmable Clock Output 1
-#define AT91C_PIO_PA22       ((unsigned int) 1 << 22) // Pin Controlled by PA22
-#define AT91C_PA22_TXD1     ((unsigned int) AT91C_PIO_PA22) //  USART 1 Transmit Data
-#define AT91C_PA22_NPCS3    ((unsigned int) AT91C_PIO_PA22) //  SPI Peripheral Chip Select 3
-#define AT91C_PIO_PA23       ((unsigned int) 1 << 23) // Pin Controlled by PA23
-#define AT91C_PA23_SCK1     ((unsigned int) AT91C_PIO_PA23) //  USART 1 Serial Clock
-#define AT91C_PA23_PWM0     ((unsigned int) AT91C_PIO_PA23) //  PWM Channel 0
-#define AT91C_PIO_PA24       ((unsigned int) 1 << 24) // Pin Controlled by PA24
-#define AT91C_PA24_RTS1     ((unsigned int) AT91C_PIO_PA24) //  USART 1 Ready To Send
-#define AT91C_PA24_PWM1     ((unsigned int) AT91C_PIO_PA24) //  PWM Channel 1
-#define AT91C_PIO_PA25       ((unsigned int) 1 << 25) // Pin Controlled by PA25
-#define AT91C_PA25_CTS1     ((unsigned int) AT91C_PIO_PA25) //  USART 1 Clear To Send
-#define AT91C_PA25_PWM2     ((unsigned int) AT91C_PIO_PA25) //  PWM Channel 2
-#define AT91C_PIO_PA26       ((unsigned int) 1 << 26) // Pin Controlled by PA26
-#define AT91C_PA26_DCD1     ((unsigned int) AT91C_PIO_PA26) //  USART 1 Data Carrier Detect
-#define AT91C_PA26_TIOA2    ((unsigned int) AT91C_PIO_PA26) //  Timer Counter 2 Multipurpose Timer I/O Pin A
-#define AT91C_PIO_PA27       ((unsigned int) 1 << 27) // Pin Controlled by PA27
-#define AT91C_PA27_DTR1     ((unsigned int) AT91C_PIO_PA27) //  USART 1 Data Terminal ready
-#define AT91C_PA27_TIOB2    ((unsigned int) AT91C_PIO_PA27) //  Timer Counter 2 Multipurpose Timer I/O Pin B
-#define AT91C_PIO_PA28       ((unsigned int) 1 << 28) // Pin Controlled by PA28
-#define AT91C_PA28_DSR1     ((unsigned int) AT91C_PIO_PA28) //  USART 1 Data Set ready
-#define AT91C_PA28_TCLK1    ((unsigned int) AT91C_PIO_PA28) //  Timer Counter 1 external clock input
-#define AT91C_PIO_PA29       ((unsigned int) 1 << 29) // Pin Controlled by PA29
-#define AT91C_PA29_RI1      ((unsigned int) AT91C_PIO_PA29) //  USART 1 Ring Indicator
-#define AT91C_PA29_TCLK2    ((unsigned int) AT91C_PIO_PA29) //  Timer Counter 2 external clock input
-#define AT91C_PIO_PA3        ((unsigned int) 1 <<  3) // Pin Controlled by PA3
-#define AT91C_PA3_TWD      ((unsigned int) AT91C_PIO_PA3) //  TWI Two-wire Serial Data
-#define AT91C_PA3_NPCS3    ((unsigned int) AT91C_PIO_PA3) //  SPI Peripheral Chip Select 3
-#define AT91C_PIO_PA30       ((unsigned int) 1 << 30) // Pin Controlled by PA30
-#define AT91C_PA30_IRQ1     ((unsigned int) AT91C_PIO_PA30) //  External Interrupt 1
-#define AT91C_PA30_NPCS2    ((unsigned int) AT91C_PIO_PA30) //  SPI Peripheral Chip Select 2
-#define AT91C_PIO_PA31       ((unsigned int) 1 << 31) // Pin Controlled by PA31
-#define AT91C_PA31_NPCS1    ((unsigned int) AT91C_PIO_PA31) //  SPI Peripheral Chip Select 1
-#define AT91C_PA31_PCK2     ((unsigned int) AT91C_PIO_PA31) //  PMC Programmable Clock Output 2
-#define AT91C_PIO_PA4        ((unsigned int) 1 <<  4) // Pin Controlled by PA4
-#define AT91C_PA4_TWCK     ((unsigned int) AT91C_PIO_PA4) //  TWI Two-wire Serial Clock
-#define AT91C_PA4_TCLK0    ((unsigned int) AT91C_PIO_PA4) //  Timer Counter 0 external clock input
-#define AT91C_PIO_PA5        ((unsigned int) 1 <<  5) // Pin Controlled by PA5
-#define AT91C_PA5_RXD0     ((unsigned int) AT91C_PIO_PA5) //  USART 0 Receive Data
-#define AT91C_PA5_NPCS3    ((unsigned int) AT91C_PIO_PA5) //  SPI Peripheral Chip Select 3
-#define AT91C_PIO_PA6        ((unsigned int) 1 <<  6) // Pin Controlled by PA6
-#define AT91C_PA6_TXD0     ((unsigned int) AT91C_PIO_PA6) //  USART 0 Transmit Data
-#define AT91C_PA6_PCK0     ((unsigned int) AT91C_PIO_PA6) //  PMC Programmable Clock Output 0
-#define AT91C_PIO_PA7        ((unsigned int) 1 <<  7) // Pin Controlled by PA7
-#define AT91C_PA7_RTS0     ((unsigned int) AT91C_PIO_PA7) //  USART 0 Ready To Send
-#define AT91C_PA7_PWM3     ((unsigned int) AT91C_PIO_PA7) //  PWM Channel 3
-#define AT91C_PIO_PA8        ((unsigned int) 1 <<  8) // Pin Controlled by PA8
-#define AT91C_PA8_CTS0     ((unsigned int) AT91C_PIO_PA8) //  USART 0 Clear To Send
-#define AT91C_PA8_ADTRG    ((unsigned int) AT91C_PIO_PA8) //  ADC External Trigger
-#define AT91C_PIO_PA9        ((unsigned int) 1 <<  9) // Pin Controlled by PA9
-#define AT91C_PA9_DRXD     ((unsigned int) AT91C_PIO_PA9) //  DBGU Debug Receive Data
-#define AT91C_PA9_NPCS1    ((unsigned int) AT91C_PIO_PA9) //  SPI Peripheral Chip Select 1
+/* ***************************************************************************** */
+/*               PIO DEFINITIONS FOR AT91SAM7S64 */
+/* ***************************************************************************** */
+#define AT91C_PIO_PA0       ( ( unsigned int ) 1 << 0 )         /* Pin Controlled by PA0 */
+#define AT91C_PA0_PWM0      ( ( unsigned int ) AT91C_PIO_PA0 )  /*  PWM Channel 0 */
+#define AT91C_PA0_TIOA0     ( ( unsigned int ) AT91C_PIO_PA0 )  /*  Timer Counter 0 Multipurpose Timer I/O Pin A */
+#define AT91C_PIO_PA1       ( ( unsigned int ) 1 << 1 )         /* Pin Controlled by PA1 */
+#define AT91C_PA1_PWM1      ( ( unsigned int ) AT91C_PIO_PA1 )  /*  PWM Channel 1 */
+#define AT91C_PA1_TIOB0     ( ( unsigned int ) AT91C_PIO_PA1 )  /*  Timer Counter 0 Multipurpose Timer I/O Pin B */
+#define AT91C_PIO_PA10      ( ( unsigned int ) 1 << 10 )        /* Pin Controlled by PA10 */
+#define AT91C_PA10_DTXD     ( ( unsigned int ) AT91C_PIO_PA10 ) /*  DBGU Debug Transmit Data */
+#define AT91C_PA10_NPCS2    ( ( unsigned int ) AT91C_PIO_PA10 ) /*  SPI Peripheral Chip Select 2 */
+#define AT91C_PIO_PA11      ( ( unsigned int ) 1 << 11 )        /* Pin Controlled by PA11 */
+#define AT91C_PA11_NPCS0    ( ( unsigned int ) AT91C_PIO_PA11 ) /*  SPI Peripheral Chip Select 0 */
+#define AT91C_PA11_PWM0     ( ( unsigned int ) AT91C_PIO_PA11 ) /*  PWM Channel 0 */
+#define AT91C_PIO_PA12      ( ( unsigned int ) 1 << 12 )        /* Pin Controlled by PA12 */
+#define AT91C_PA12_MISO     ( ( unsigned int ) AT91C_PIO_PA12 ) /*  SPI Master In Slave */
+#define AT91C_PA12_PWM1     ( ( unsigned int ) AT91C_PIO_PA12 ) /*  PWM Channel 1 */
+#define AT91C_PIO_PA13      ( ( unsigned int ) 1 << 13 )        /* Pin Controlled by PA13 */
+#define AT91C_PA13_MOSI     ( ( unsigned int ) AT91C_PIO_PA13 ) /*  SPI Master Out Slave */
+#define AT91C_PA13_PWM2     ( ( unsigned int ) AT91C_PIO_PA13 ) /*  PWM Channel 2 */
+#define AT91C_PIO_PA14      ( ( unsigned int ) 1 << 14 )        /* Pin Controlled by PA14 */
+#define AT91C_PA14_SPCK     ( ( unsigned int ) AT91C_PIO_PA14 ) /*  SPI Serial Clock */
+#define AT91C_PA14_PWM3     ( ( unsigned int ) AT91C_PIO_PA14 ) /*  PWM Channel 3 */
+#define AT91C_PIO_PA15      ( ( unsigned int ) 1 << 15 )        /* Pin Controlled by PA15 */
+#define AT91C_PA15_TF       ( ( unsigned int ) AT91C_PIO_PA15 ) /*  SSC Transmit Frame Sync */
+#define AT91C_PA15_TIOA1    ( ( unsigned int ) AT91C_PIO_PA15 ) /*  Timer Counter 1 Multipurpose Timer I/O Pin A */
+#define AT91C_PIO_PA16      ( ( unsigned int ) 1 << 16 )        /* Pin Controlled by PA16 */
+#define AT91C_PA16_TK       ( ( unsigned int ) AT91C_PIO_PA16 ) /*  SSC Transmit Clock */
+#define AT91C_PA16_TIOB1    ( ( unsigned int ) AT91C_PIO_PA16 ) /*  Timer Counter 1 Multipurpose Timer I/O Pin B */
+#define AT91C_PIO_PA17      ( ( unsigned int ) 1 << 17 )        /* Pin Controlled by PA17 */
+#define AT91C_PA17_TD       ( ( unsigned int ) AT91C_PIO_PA17 ) /*  SSC Transmit data */
+#define AT91C_PA17_PCK1     ( ( unsigned int ) AT91C_PIO_PA17 ) /*  PMC Programmable Clock Output 1 */
+#define AT91C_PIO_PA18      ( ( unsigned int ) 1 << 18 )        /* Pin Controlled by PA18 */
+#define AT91C_PA18_RD       ( ( unsigned int ) AT91C_PIO_PA18 ) /*  SSC Receive Data */
+#define AT91C_PA18_PCK2     ( ( unsigned int ) AT91C_PIO_PA18 ) /*  PMC Programmable Clock Output 2 */
+#define AT91C_PIO_PA19      ( ( unsigned int ) 1 << 19 )        /* Pin Controlled by PA19 */
+#define AT91C_PA19_RK       ( ( unsigned int ) AT91C_PIO_PA19 ) /*  SSC Receive Clock */
+#define AT91C_PA19_FIQ      ( ( unsigned int ) AT91C_PIO_PA19 ) /*  AIC Fast Interrupt Input */
+#define AT91C_PIO_PA2       ( ( unsigned int ) 1 << 2 )         /* Pin Controlled by PA2 */
+#define AT91C_PA2_PWM2      ( ( unsigned int ) AT91C_PIO_PA2 )  /*  PWM Channel 2 */
+#define AT91C_PA2_SCK0      ( ( unsigned int ) AT91C_PIO_PA2 )  /*  USART 0 Serial Clock */
+#define AT91C_PIO_PA20      ( ( unsigned int ) 1 << 20 )        /* Pin Controlled by PA20 */
+#define AT91C_PA20_RF       ( ( unsigned int ) AT91C_PIO_PA20 ) /*  SSC Receive Frame Sync */
+#define AT91C_PA20_IRQ0     ( ( unsigned int ) AT91C_PIO_PA20 ) /*  External Interrupt 0 */
+#define AT91C_PIO_PA21      ( ( unsigned int ) 1 << 21 )        /* Pin Controlled by PA21 */
+#define AT91C_PA21_RXD1     ( ( unsigned int ) AT91C_PIO_PA21 ) /*  USART 1 Receive Data */
+#define AT91C_PA21_PCK1     ( ( unsigned int ) AT91C_PIO_PA21 ) /*  PMC Programmable Clock Output 1 */
+#define AT91C_PIO_PA22      ( ( unsigned int ) 1 << 22 )        /* Pin Controlled by PA22 */
+#define AT91C_PA22_TXD1     ( ( unsigned int ) AT91C_PIO_PA22 ) /*  USART 1 Transmit Data */
+#define AT91C_PA22_NPCS3    ( ( unsigned int ) AT91C_PIO_PA22 ) /*  SPI Peripheral Chip Select 3 */
+#define AT91C_PIO_PA23      ( ( unsigned int ) 1 << 23 )        /* Pin Controlled by PA23 */
+#define AT91C_PA23_SCK1     ( ( unsigned int ) AT91C_PIO_PA23 ) /*  USART 1 Serial Clock */
+#define AT91C_PA23_PWM0     ( ( unsigned int ) AT91C_PIO_PA23 ) /*  PWM Channel 0 */
+#define AT91C_PIO_PA24      ( ( unsigned int ) 1 << 24 )        /* Pin Controlled by PA24 */
+#define AT91C_PA24_RTS1     ( ( unsigned int ) AT91C_PIO_PA24 ) /*  USART 1 Ready To Send */
+#define AT91C_PA24_PWM1     ( ( unsigned int ) AT91C_PIO_PA24 ) /*  PWM Channel 1 */
+#define AT91C_PIO_PA25      ( ( unsigned int ) 1 << 25 )        /* Pin Controlled by PA25 */
+#define AT91C_PA25_CTS1     ( ( unsigned int ) AT91C_PIO_PA25 ) /*  USART 1 Clear To Send */
+#define AT91C_PA25_PWM2     ( ( unsigned int ) AT91C_PIO_PA25 ) /*  PWM Channel 2 */
+#define AT91C_PIO_PA26      ( ( unsigned int ) 1 << 26 )        /* Pin Controlled by PA26 */
+#define AT91C_PA26_DCD1     ( ( unsigned int ) AT91C_PIO_PA26 ) /*  USART 1 Data Carrier Detect */
+#define AT91C_PA26_TIOA2    ( ( unsigned int ) AT91C_PIO_PA26 ) /*  Timer Counter 2 Multipurpose Timer I/O Pin A */
+#define AT91C_PIO_PA27      ( ( unsigned int ) 1 << 27 )        /* Pin Controlled by PA27 */
+#define AT91C_PA27_DTR1     ( ( unsigned int ) AT91C_PIO_PA27 ) /*  USART 1 Data Terminal ready */
+#define AT91C_PA27_TIOB2    ( ( unsigned int ) AT91C_PIO_PA27 ) /*  Timer Counter 2 Multipurpose Timer I/O Pin B */
+#define AT91C_PIO_PA28      ( ( unsigned int ) 1 << 28 )        /* Pin Controlled by PA28 */
+#define AT91C_PA28_DSR1     ( ( unsigned int ) AT91C_PIO_PA28 ) /*  USART 1 Data Set ready */
+#define AT91C_PA28_TCLK1    ( ( unsigned int ) AT91C_PIO_PA28 ) /*  Timer Counter 1 external clock input */
+#define AT91C_PIO_PA29      ( ( unsigned int ) 1 << 29 )        /* Pin Controlled by PA29 */
+#define AT91C_PA29_RI1      ( ( unsigned int ) AT91C_PIO_PA29 ) /*  USART 1 Ring Indicator */
+#define AT91C_PA29_TCLK2    ( ( unsigned int ) AT91C_PIO_PA29 ) /*  Timer Counter 2 external clock input */
+#define AT91C_PIO_PA3       ( ( unsigned int ) 1 << 3 )         /* Pin Controlled by PA3 */
+#define AT91C_PA3_TWD       ( ( unsigned int ) AT91C_PIO_PA3 )  /*  TWI Two-wire Serial Data */
+#define AT91C_PA3_NPCS3     ( ( unsigned int ) AT91C_PIO_PA3 )  /*  SPI Peripheral Chip Select 3 */
+#define AT91C_PIO_PA30      ( ( unsigned int ) 1 << 30 )        /* Pin Controlled by PA30 */
+#define AT91C_PA30_IRQ1     ( ( unsigned int ) AT91C_PIO_PA30 ) /*  External Interrupt 1 */
+#define AT91C_PA30_NPCS2    ( ( unsigned int ) AT91C_PIO_PA30 ) /*  SPI Peripheral Chip Select 2 */
+#define AT91C_PIO_PA31      ( ( unsigned int ) 1 << 31 )        /* Pin Controlled by PA31 */
+#define AT91C_PA31_NPCS1    ( ( unsigned int ) AT91C_PIO_PA31 ) /*  SPI Peripheral Chip Select 1 */
+#define AT91C_PA31_PCK2     ( ( unsigned int ) AT91C_PIO_PA31 ) /*  PMC Programmable Clock Output 2 */
+#define AT91C_PIO_PA4       ( ( unsigned int ) 1 << 4 )         /* Pin Controlled by PA4 */
+#define AT91C_PA4_TWCK      ( ( unsigned int ) AT91C_PIO_PA4 )  /*  TWI Two-wire Serial Clock */
+#define AT91C_PA4_TCLK0     ( ( unsigned int ) AT91C_PIO_PA4 )  /*  Timer Counter 0 external clock input */
+#define AT91C_PIO_PA5       ( ( unsigned int ) 1 << 5 )         /* Pin Controlled by PA5 */
+#define AT91C_PA5_RXD0      ( ( unsigned int ) AT91C_PIO_PA5 )  /*  USART 0 Receive Data */
+#define AT91C_PA5_NPCS3     ( ( unsigned int ) AT91C_PIO_PA5 )  /*  SPI Peripheral Chip Select 3 */
+#define AT91C_PIO_PA6       ( ( unsigned int ) 1 << 6 )         /* Pin Controlled by PA6 */
+#define AT91C_PA6_TXD0      ( ( unsigned int ) AT91C_PIO_PA6 )  /*  USART 0 Transmit Data */
+#define AT91C_PA6_PCK0      ( ( unsigned int ) AT91C_PIO_PA6 )  /*  PMC Programmable Clock Output 0 */
+#define AT91C_PIO_PA7       ( ( unsigned int ) 1 << 7 )         /* Pin Controlled by PA7 */
+#define AT91C_PA7_RTS0      ( ( unsigned int ) AT91C_PIO_PA7 )  /*  USART 0 Ready To Send */
+#define AT91C_PA7_PWM3      ( ( unsigned int ) AT91C_PIO_PA7 )  /*  PWM Channel 3 */
+#define AT91C_PIO_PA8       ( ( unsigned int ) 1 << 8 )         /* Pin Controlled by PA8 */
+#define AT91C_PA8_CTS0      ( ( unsigned int ) AT91C_PIO_PA8 )  /*  USART 0 Clear To Send */
+#define AT91C_PA8_ADTRG     ( ( unsigned int ) AT91C_PIO_PA8 )  /*  ADC External Trigger */
+#define AT91C_PIO_PA9       ( ( unsigned int ) 1 << 9 )         /* Pin Controlled by PA9 */
+#define AT91C_PA9_DRXD      ( ( unsigned int ) AT91C_PIO_PA9 )  /*  DBGU Debug Receive Data */
+#define AT91C_PA9_NPCS1     ( ( unsigned int ) AT91C_PIO_PA9 )  /*  SPI Peripheral Chip Select 1 */
 
-// *****************************************************************************
-//               PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64
-// *****************************************************************************
-#define AT91C_ID_FIQ    ((unsigned int)  0) // Advanced Interrupt Controller (FIQ)
-#define AT91C_ID_SYS    ((unsigned int)  1) // System Peripheral
-#define AT91C_ID_PIOA   ((unsigned int)  2) // Parallel IO Controller
-#define AT91C_ID_3_Reserved ((unsigned int)  3) // Reserved
-#define AT91C_ID_ADC    ((unsigned int)  4) // Analog-to-Digital Converter
-#define AT91C_ID_SPI    ((unsigned int)  5) // Serial Peripheral Interface
-#define AT91C_ID_US0    ((unsigned int)  6) // USART 0
-#define AT91C_ID_US1    ((unsigned int)  7) // USART 1
-#define AT91C_ID_SSC    ((unsigned int)  8) // Serial Synchronous Controller
-#define AT91C_ID_TWI    ((unsigned int)  9) // Two-Wire Interface
-#define AT91C_ID_PWMC   ((unsigned int) 10) // PWM Controller
-#define AT91C_ID_UDP    ((unsigned int) 11) // USB Device Port
-#define AT91C_ID_TC0    ((unsigned int) 12) // Timer Counter 0
-#define AT91C_ID_TC1    ((unsigned int) 13) // Timer Counter 1
-#define AT91C_ID_TC2    ((unsigned int) 14) // Timer Counter 2
-#define AT91C_ID_15_Reserved ((unsigned int) 15) // Reserved
-#define AT91C_ID_16_Reserved ((unsigned int) 16) // Reserved
-#define AT91C_ID_17_Reserved ((unsigned int) 17) // Reserved
-#define AT91C_ID_18_Reserved ((unsigned int) 18) // Reserved
-#define AT91C_ID_19_Reserved ((unsigned int) 19) // Reserved
-#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved
-#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved
-#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved
-#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved
-#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved
-#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved
-#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved
-#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved
-#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved
-#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved
-#define AT91C_ID_IRQ0   ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0)
-#define AT91C_ID_IRQ1   ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1)
+/* ***************************************************************************** */
+/*               PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64 */
+/* ***************************************************************************** */
+#define AT91C_ID_FIQ            ( ( unsigned int ) 0 )  /* Advanced Interrupt Controller (FIQ) */
+#define AT91C_ID_SYS            ( ( unsigned int ) 1 )  /* System Peripheral */
+#define AT91C_ID_PIOA           ( ( unsigned int ) 2 )  /* Parallel IO Controller */
+#define AT91C_ID_3_Reserved     ( ( unsigned int ) 3 )  /* Reserved */
+#define AT91C_ID_ADC            ( ( unsigned int ) 4 )  /* Analog-to-Digital Converter */
+#define AT91C_ID_SPI            ( ( unsigned int ) 5 )  /* Serial Peripheral Interface */
+#define AT91C_ID_US0            ( ( unsigned int ) 6 )  /* USART 0 */
+#define AT91C_ID_US1            ( ( unsigned int ) 7 )  /* USART 1 */
+#define AT91C_ID_SSC            ( ( unsigned int ) 8 )  /* Serial Synchronous Controller */
+#define AT91C_ID_TWI            ( ( unsigned int ) 9 )  /* Two-Wire Interface */
+#define AT91C_ID_PWMC           ( ( unsigned int ) 10 ) /* PWM Controller */
+#define AT91C_ID_UDP            ( ( unsigned int ) 11 ) /* USB Device Port */
+#define AT91C_ID_TC0            ( ( unsigned int ) 12 ) /* Timer Counter 0 */
+#define AT91C_ID_TC1            ( ( unsigned int ) 13 ) /* Timer Counter 1 */
+#define AT91C_ID_TC2            ( ( unsigned int ) 14 ) /* Timer Counter 2 */
+#define AT91C_ID_15_Reserved    ( ( unsigned int ) 15 ) /* Reserved */
+#define AT91C_ID_16_Reserved    ( ( unsigned int ) 16 ) /* Reserved */
+#define AT91C_ID_17_Reserved    ( ( unsigned int ) 17 ) /* Reserved */
+#define AT91C_ID_18_Reserved    ( ( unsigned int ) 18 ) /* Reserved */
+#define AT91C_ID_19_Reserved    ( ( unsigned int ) 19 ) /* Reserved */
+#define AT91C_ID_20_Reserved    ( ( unsigned int ) 20 ) /* Reserved */
+#define AT91C_ID_21_Reserved    ( ( unsigned int ) 21 ) /* Reserved */
+#define AT91C_ID_22_Reserved    ( ( unsigned int ) 22 ) /* Reserved */
+#define AT91C_ID_23_Reserved    ( ( unsigned int ) 23 ) /* Reserved */
+#define AT91C_ID_24_Reserved    ( ( unsigned int ) 24 ) /* Reserved */
+#define AT91C_ID_25_Reserved    ( ( unsigned int ) 25 ) /* Reserved */
+#define AT91C_ID_26_Reserved    ( ( unsigned int ) 26 ) /* Reserved */
+#define AT91C_ID_27_Reserved    ( ( unsigned int ) 27 ) /* Reserved */
+#define AT91C_ID_28_Reserved    ( ( unsigned int ) 28 ) /* Reserved */
+#define AT91C_ID_29_Reserved    ( ( unsigned int ) 29 ) /* Reserved */
+#define AT91C_ID_IRQ0           ( ( unsigned int ) 30 ) /* Advanced Interrupt Controller (IRQ0) */
+#define AT91C_ID_IRQ1           ( ( unsigned int ) 31 ) /* Advanced Interrupt Controller (IRQ1) */
 
-// *****************************************************************************
-//               BASE ADDRESS DEFINITIONS FOR AT91SAM7S64
-// *****************************************************************************
-#define AT91C_BASE_SYSC      ((AT91PS_SYSC)     0xFFFFF000) // (SYSC) Base Address
-#define AT91C_BASE_AIC       ((AT91PS_AIC)  0xFFFFF000) // (AIC) Base Address
-#define AT91C_BASE_DBGU      ((AT91PS_DBGU)     0xFFFFF200) // (DBGU) Base Address
-#define AT91C_BASE_PDC_DBGU  ((AT91PS_PDC)  0xFFFFF300) // (PDC_DBGU) Base Address
-#define AT91C_BASE_PIOA      ((AT91PS_PIO)  0xFFFFF400) // (PIOA) Base Address
-#define AT91C_BASE_CKGR      ((AT91PS_CKGR)     0xFFFFFC20) // (CKGR) Base Address
-#define AT91C_BASE_PMC       ((AT91PS_PMC)  0xFFFFFC00) // (PMC) Base Address
-#define AT91C_BASE_RSTC      ((AT91PS_RSTC)     0xFFFFFD00) // (RSTC) Base Address
-#define AT91C_BASE_RTTC      ((AT91PS_RTTC)     0xFFFFFD20) // (RTTC) Base Address
-#define AT91C_BASE_PITC      ((AT91PS_PITC)     0xFFFFFD30) // (PITC) Base Address
-#define AT91C_BASE_WDTC      ((AT91PS_WDTC)     0xFFFFFD40) // (WDTC) Base Address
-#define AT91C_BASE_MC        ((AT91PS_MC)   0xFFFFFF00) // (MC) Base Address
-#define AT91C_BASE_PDC_SPI   ((AT91PS_PDC)  0xFFFE0100) // (PDC_SPI) Base Address
-#define AT91C_BASE_SPI       ((AT91PS_SPI)  0xFFFE0000) // (SPI) Base Address
-#define AT91C_BASE_PDC_ADC   ((AT91PS_PDC)  0xFFFD8100) // (PDC_ADC) Base Address
-#define AT91C_BASE_ADC       ((AT91PS_ADC)  0xFFFD8000) // (ADC) Base Address
-#define AT91C_BASE_PDC_SSC   ((AT91PS_PDC)  0xFFFD4100) // (PDC_SSC) Base Address
-#define AT91C_BASE_SSC       ((AT91PS_SSC)  0xFFFD4000) // (SSC) Base Address
-#define AT91C_BASE_PDC_US1   ((AT91PS_PDC)  0xFFFC4100) // (PDC_US1) Base Address
-#define AT91C_BASE_US1       ((AT91PS_USART)    0xFFFC4000) // (US1) Base Address
-#define AT91C_BASE_PDC_US0   ((AT91PS_PDC)  0xFFFC0100) // (PDC_US0) Base Address
-#define AT91C_BASE_US0       ((AT91PS_USART)    0xFFFC0000) // (US0) Base Address
-#define AT91C_BASE_TWI       ((AT91PS_TWI)  0xFFFB8000) // (TWI) Base Address
-#define AT91C_BASE_TC2       ((AT91PS_TC)   0xFFFA0080) // (TC2) Base Address
-#define AT91C_BASE_TC1       ((AT91PS_TC)   0xFFFA0040) // (TC1) Base Address
-#define AT91C_BASE_TC0       ((AT91PS_TC)   0xFFFA0000) // (TC0) Base Address
-#define AT91C_BASE_TCB       ((AT91PS_TCB)  0xFFFA0000) // (TCB) Base Address
-#define AT91C_BASE_PWMC_CH3  ((AT91PS_PWMC_CH)  0xFFFCC260) // (PWMC_CH3) Base Address
-#define AT91C_BASE_PWMC_CH2  ((AT91PS_PWMC_CH)  0xFFFCC240) // (PWMC_CH2) Base Address
-#define AT91C_BASE_PWMC_CH1  ((AT91PS_PWMC_CH)  0xFFFCC220) // (PWMC_CH1) Base Address
-#define AT91C_BASE_PWMC_CH0  ((AT91PS_PWMC_CH)  0xFFFCC200) // (PWMC_CH0) Base Address
-#define AT91C_BASE_PWMC      ((AT91PS_PWMC)     0xFFFCC000) // (PWMC) Base Address
-#define AT91C_BASE_UDP       ((AT91PS_UDP)  0xFFFB0000) // (UDP) Base Address
+/* ***************************************************************************** */
+/*               BASE ADDRESS DEFINITIONS FOR AT91SAM7S64 */
+/* ***************************************************************************** */
+#define AT91C_BASE_SYSC        ( ( AT91PS_SYSC ) 0xFFFFF000 )    /* (SYSC) Base Address */
+#define AT91C_BASE_AIC         ( ( AT91PS_AIC ) 0xFFFFF000 )     /* (AIC) Base Address */
+#define AT91C_BASE_DBGU        ( ( AT91PS_DBGU ) 0xFFFFF200 )    /* (DBGU) Base Address */
+#define AT91C_BASE_PDC_DBGU    ( ( AT91PS_PDC ) 0xFFFFF300 )     /* (PDC_DBGU) Base Address */
+#define AT91C_BASE_PIOA        ( ( AT91PS_PIO ) 0xFFFFF400 )     /* (PIOA) Base Address */
+#define AT91C_BASE_CKGR        ( ( AT91PS_CKGR ) 0xFFFFFC20 )    /* (CKGR) Base Address */
+#define AT91C_BASE_PMC         ( ( AT91PS_PMC ) 0xFFFFFC00 )     /* (PMC) Base Address */
+#define AT91C_BASE_RSTC        ( ( AT91PS_RSTC ) 0xFFFFFD00 )    /* (RSTC) Base Address */
+#define AT91C_BASE_RTTC        ( ( AT91PS_RTTC ) 0xFFFFFD20 )    /* (RTTC) Base Address */
+#define AT91C_BASE_PITC        ( ( AT91PS_PITC ) 0xFFFFFD30 )    /* (PITC) Base Address */
+#define AT91C_BASE_WDTC        ( ( AT91PS_WDTC ) 0xFFFFFD40 )    /* (WDTC) Base Address */
+#define AT91C_BASE_MC          ( ( AT91PS_MC ) 0xFFFFFF00 )      /* (MC) Base Address */
+#define AT91C_BASE_PDC_SPI     ( ( AT91PS_PDC ) 0xFFFE0100 )     /* (PDC_SPI) Base Address */
+#define AT91C_BASE_SPI         ( ( AT91PS_SPI ) 0xFFFE0000 )     /* (SPI) Base Address */
+#define AT91C_BASE_PDC_ADC     ( ( AT91PS_PDC ) 0xFFFD8100 )     /* (PDC_ADC) Base Address */
+#define AT91C_BASE_ADC         ( ( AT91PS_ADC ) 0xFFFD8000 )     /* (ADC) Base Address */
+#define AT91C_BASE_PDC_SSC     ( ( AT91PS_PDC ) 0xFFFD4100 )     /* (PDC_SSC) Base Address */
+#define AT91C_BASE_SSC         ( ( AT91PS_SSC ) 0xFFFD4000 )     /* (SSC) Base Address */
+#define AT91C_BASE_PDC_US1     ( ( AT91PS_PDC ) 0xFFFC4100 )     /* (PDC_US1) Base Address */
+#define AT91C_BASE_US1         ( ( AT91PS_USART ) 0xFFFC4000 )   /* (US1) Base Address */
+#define AT91C_BASE_PDC_US0     ( ( AT91PS_PDC ) 0xFFFC0100 )     /* (PDC_US0) Base Address */
+#define AT91C_BASE_US0         ( ( AT91PS_USART ) 0xFFFC0000 )   /* (US0) Base Address */
+#define AT91C_BASE_TWI         ( ( AT91PS_TWI ) 0xFFFB8000 )     /* (TWI) Base Address */
+#define AT91C_BASE_TC2         ( ( AT91PS_TC ) 0xFFFA0080 )      /* (TC2) Base Address */
+#define AT91C_BASE_TC1         ( ( AT91PS_TC ) 0xFFFA0040 )      /* (TC1) Base Address */
+#define AT91C_BASE_TC0         ( ( AT91PS_TC ) 0xFFFA0000 )      /* (TC0) Base Address */
+#define AT91C_BASE_TCB         ( ( AT91PS_TCB ) 0xFFFA0000 )     /* (TCB) Base Address */
+#define AT91C_BASE_PWMC_CH3    ( ( AT91PS_PWMC_CH ) 0xFFFCC260 ) /* (PWMC_CH3) Base Address */
+#define AT91C_BASE_PWMC_CH2    ( ( AT91PS_PWMC_CH ) 0xFFFCC240 ) /* (PWMC_CH2) Base Address */
+#define AT91C_BASE_PWMC_CH1    ( ( AT91PS_PWMC_CH ) 0xFFFCC220 ) /* (PWMC_CH1) Base Address */
+#define AT91C_BASE_PWMC_CH0    ( ( AT91PS_PWMC_CH ) 0xFFFCC200 ) /* (PWMC_CH0) Base Address */
+#define AT91C_BASE_PWMC        ( ( AT91PS_PWMC ) 0xFFFCC000 )    /* (PWMC) Base Address */
+#define AT91C_BASE_UDP         ( ( AT91PS_UDP ) 0xFFFB0000 )     /* (UDP) Base Address */
 
-// *****************************************************************************
-//               MEMORY MAPPING DEFINITIONS FOR AT91SAM7S64
-// *****************************************************************************
-#define AT91C_ISRAM  ((char *)  0x00200000) // Internal SRAM base address
-#define AT91C_ISRAM_SIZE     ((unsigned int) 0x00004000) // Internal SRAM size in byte (16 Kbyte)
-#define AT91C_IFLASH     ((char *)  0x00100000) // Internal ROM base address
-#define AT91C_IFLASH_SIZE    ((unsigned int) 0x00010000) // Internal ROM size in byte (64 Kbyte)
+/* ***************************************************************************** */
+/*               MEMORY MAPPING DEFINITIONS FOR AT91SAM7S64 */
+/* ***************************************************************************** */
+#define AT91C_ISRAM          ( ( char * ) 0x00200000 )       /* Internal SRAM base address */
+#define AT91C_ISRAM_SIZE     ( ( unsigned int ) 0x00004000 ) /* Internal SRAM size in byte (16 Kbyte) */
+#define AT91C_IFLASH         ( ( char * ) 0x00100000 )       /* Internal ROM base address */
+#define AT91C_IFLASH_SIZE    ( ( unsigned int ) 0x00010000 ) /* Internal ROM size in byte (64 Kbyte) */
 
-#endif
+#endif /* ifndef AT91SAM7S64_H */
diff --git a/portable/IAR/AtmelSAM7S64/AT91SAM7S64_inc.h b/portable/IAR/AtmelSAM7S64/AT91SAM7S64_inc.h
index 77e866941..9d95f3eb7 100644
--- a/portable/IAR/AtmelSAM7S64/AT91SAM7S64_inc.h
+++ b/portable/IAR/AtmelSAM7S64/AT91SAM7S64_inc.h
@@ -1,1810 +1,1810 @@
-// ----------------------------------------------------------------------------
-//          ATMEL Microcontroller Software Support  -  ROUSSET  -
-// ----------------------------------------------------------------------------
-//  The software is delivered "AS IS" without warranty or condition of any
-//  kind, either express, implied or statutory. This includes without
-//  limitation any warranty or condition with respect to merchantability or
-//  fitness for any particular purpose, or against the infringements of
-//  intellectual property rights of others.
-// ----------------------------------------------------------------------------
-// File Name           : AT91SAM7S64.h
-// Object              : AT91SAM7S64 definitions
-// Generated           : AT91 SW Application Group  07/16/2004 (07:43:09)
-//
-// CVS Reference       : /AT91SAM7S64.pl/1.12/Mon Jul 12 13:02:30 2004//
-// CVS Reference       : /SYSC_SAM7Sxx.pl/1.5/Mon Jul 12 16:22:12 2004//
-// CVS Reference       : /MC_SAM02.pl/1.3/Wed Mar 10 08:37:04 2004//
-// CVS Reference       : /UDP_1765B.pl/1.3/Fri Aug  2 14:45:38 2002//
-// CVS Reference       : /AIC_1796B.pl/1.1.1.1/Fri Jun 28 09:36:48 2002//
-// CVS Reference       : /lib_pmc_SAM.h/1.6/Tue Apr 27 13:53:52 2004//
-// CVS Reference       : /PIO_1725D.pl/1.1.1.1/Fri Jun 28 09:36:48 2002//
-// CVS Reference       : /DBGU_1754A.pl/1.4/Fri Jan 31 12:18:24 2003//
-// CVS Reference       : /US_1739C.pl/1.2/Mon Jul 12 17:26:24 2004//
-// CVS Reference       : /SPI2.pl/1.2/Fri Oct 17 08:13:40 2003//
-// CVS Reference       : /SSC_1762A.pl/1.2/Fri Nov  8 13:26:40 2002//
-// CVS Reference       : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//
-// CVS Reference       : /TWI_1761B.pl/1.4/Fri Feb  7 10:30:08 2003//
-// CVS Reference       : /PDC_1734B.pl/1.2/Thu Nov 21 16:38:24 2002//
-// CVS Reference       : /ADC_SAM.pl/1.7/Fri Oct 17 08:12:38 2003//
-// CVS Reference       : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//
-// ----------------------------------------------------------------------------
+/* ---------------------------------------------------------------------------- */
+/*          ATMEL Microcontroller Software Support  -  ROUSSET  - */
+/* ---------------------------------------------------------------------------- */
+/*  The software is delivered "AS IS" without warranty or condition of any */
+/*  kind, either express, implied or statutory. This includes without */
+/*  limitation any warranty or condition with respect to merchantability or */
+/*  fitness for any particular purpose, or against the infringements of */
+/*  intellectual property rights of others. */
+/* ---------------------------------------------------------------------------- */
+/* File Name           : AT91SAM7S64.h */
+/* Object              : AT91SAM7S64 definitions */
+/* Generated           : AT91 SW Application Group  07/16/2004 (07:43:09) */
+/* */
+/* CVS Reference       : /AT91SAM7S64.pl/1.12/Mon Jul 12 13:02:30 2004// */
+/* CVS Reference       : /SYSC_SAM7Sxx.pl/1.5/Mon Jul 12 16:22:12 2004// */
+/* CVS Reference       : /MC_SAM02.pl/1.3/Wed Mar 10 08:37:04 2004// */
+/* CVS Reference       : /UDP_1765B.pl/1.3/Fri Aug  2 14:45:38 2002// */
+/* CVS Reference       : /AIC_1796B.pl/1.1.1.1/Fri Jun 28 09:36:48 2002// */
+/* CVS Reference       : /lib_pmc_SAM.h/1.6/Tue Apr 27 13:53:52 2004// */
+/* CVS Reference       : /PIO_1725D.pl/1.1.1.1/Fri Jun 28 09:36:48 2002// */
+/* CVS Reference       : /DBGU_1754A.pl/1.4/Fri Jan 31 12:18:24 2003// */
+/* CVS Reference       : /US_1739C.pl/1.2/Mon Jul 12 17:26:24 2004// */
+/* CVS Reference       : /SPI2.pl/1.2/Fri Oct 17 08:13:40 2003// */
+/* CVS Reference       : /SSC_1762A.pl/1.2/Fri Nov  8 13:26:40 2002// */
+/* CVS Reference       : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// */
+/* CVS Reference       : /TWI_1761B.pl/1.4/Fri Feb  7 10:30:08 2003// */
+/* CVS Reference       : /PDC_1734B.pl/1.2/Thu Nov 21 16:38:24 2002// */
+/* CVS Reference       : /ADC_SAM.pl/1.7/Fri Oct 17 08:12:38 2003// */
+/* CVS Reference       : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// */
+/* ---------------------------------------------------------------------------- */
 
-// Hardware register definition
+/* Hardware register definition */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR System Peripherals
-// *****************************************************************************
-// *** Register offset in AT91S_SYSC structure ***
-#define SYSC_AIC_SMR    ( 0) // Source Mode Register
-#define SYSC_AIC_SVR    (128) // Source Vector Register
-#define SYSC_AIC_IVR    (256) // IRQ Vector Register
-#define SYSC_AIC_FVR    (260) // FIQ Vector Register
-#define SYSC_AIC_ISR    (264) // Interrupt Status Register
-#define SYSC_AIC_IPR    (268) // Interrupt Pending Register
-#define SYSC_AIC_IMR    (272) // Interrupt Mask Register
-#define SYSC_AIC_CISR   (276) // Core Interrupt Status Register
-#define SYSC_AIC_IECR   (288) // Interrupt Enable Command Register
-#define SYSC_AIC_IDCR   (292) // Interrupt Disable Command Register
-#define SYSC_AIC_ICCR   (296) // Interrupt Clear Command Register
-#define SYSC_AIC_ISCR   (300) // Interrupt Set Command Register
-#define SYSC_AIC_EOICR  (304) // End of Interrupt Command Register
-#define SYSC_AIC_SPU    (308) // Spurious Vector Register
-#define SYSC_AIC_DCR    (312) // Debug Control Register (Protect)
-#define SYSC_AIC_FFER   (320) // Fast Forcing Enable Register
-#define SYSC_AIC_FFDR   (324) // Fast Forcing Disable Register
-#define SYSC_AIC_FFSR   (328) // Fast Forcing Status Register
-#define SYSC_DBGU_CR    (512) // Control Register
-#define SYSC_DBGU_MR    (516) // Mode Register
-#define SYSC_DBGU_IER   (520) // Interrupt Enable Register
-#define SYSC_DBGU_IDR   (524) // Interrupt Disable Register
-#define SYSC_DBGU_IMR   (528) // Interrupt Mask Register
-#define SYSC_DBGU_CSR   (532) // Channel Status Register
-#define SYSC_DBGU_RHR   (536) // Receiver Holding Register
-#define SYSC_DBGU_THR   (540) // Transmitter Holding Register
-#define SYSC_DBGU_BRGR  (544) // Baud Rate Generator Register
-#define SYSC_DBGU_C1R   (576) // Chip ID1 Register
-#define SYSC_DBGU_C2R   (580) // Chip ID2 Register
-#define SYSC_DBGU_FNTR  (584) // Force NTRST Register
-#define SYSC_DBGU_RPR   (768) // Receive Pointer Register
-#define SYSC_DBGU_RCR   (772) // Receive Counter Register
-#define SYSC_DBGU_TPR   (776) // Transmit Pointer Register
-#define SYSC_DBGU_TCR   (780) // Transmit Counter Register
-#define SYSC_DBGU_RNPR  (784) // Receive Next Pointer Register
-#define SYSC_DBGU_RNCR  (788) // Receive Next Counter Register
-#define SYSC_DBGU_TNPR  (792) // Transmit Next Pointer Register
-#define SYSC_DBGU_TNCR  (796) // Transmit Next Counter Register
-#define SYSC_DBGU_PTCR  (800) // PDC Transfer Control Register
-#define SYSC_DBGU_PTSR  (804) // PDC Transfer Status Register
-#define SYSC_PIOA_PER   (1024) // PIO Enable Register
-#define SYSC_PIOA_PDR   (1028) // PIO Disable Register
-#define SYSC_PIOA_PSR   (1032) // PIO Status Register
-#define SYSC_PIOA_OER   (1040) // Output Enable Register
-#define SYSC_PIOA_ODR   (1044) // Output Disable Registerr
-#define SYSC_PIOA_OSR   (1048) // Output Status Register
-#define SYSC_PIOA_IFER  (1056) // Input Filter Enable Register
-#define SYSC_PIOA_IFDR  (1060) // Input Filter Disable Register
-#define SYSC_PIOA_IFSR  (1064) // Input Filter Status Register
-#define SYSC_PIOA_SODR  (1072) // Set Output Data Register
-#define SYSC_PIOA_CODR  (1076) // Clear Output Data Register
-#define SYSC_PIOA_ODSR  (1080) // Output Data Status Register
-#define SYSC_PIOA_PDSR  (1084) // Pin Data Status Register
-#define SYSC_PIOA_IER   (1088) // Interrupt Enable Register
-#define SYSC_PIOA_IDR   (1092) // Interrupt Disable Register
-#define SYSC_PIOA_IMR   (1096) // Interrupt Mask Register
-#define SYSC_PIOA_ISR   (1100) // Interrupt Status Register
-#define SYSC_PIOA_MDER  (1104) // Multi-driver Enable Register
-#define SYSC_PIOA_MDDR  (1108) // Multi-driver Disable Register
-#define SYSC_PIOA_MDSR  (1112) // Multi-driver Status Register
-#define SYSC_PIOA_PPUDR (1120) // Pull-up Disable Register
-#define SYSC_PIOA_PPUER (1124) // Pull-up Enable Register
-#define SYSC_PIOA_PPUSR (1128) // Pad Pull-up Status Register
-#define SYSC_PIOA_ASR   (1136) // Select A Register
-#define SYSC_PIOA_BSR   (1140) // Select B Register
-#define SYSC_PIOA_ABSR  (1144) // AB Select Status Register
-#define SYSC_PIOA_OWER  (1184) // Output Write Enable Register
-#define SYSC_PIOA_OWDR  (1188) // Output Write Disable Register
-#define SYSC_PIOA_OWSR  (1192) // Output Write Status Register
-#define SYSC_PMC_SCER   (3072) // System Clock Enable Register
-#define SYSC_PMC_SCDR   (3076) // System Clock Disable Register
-#define SYSC_PMC_SCSR   (3080) // System Clock Status Register
-#define SYSC_PMC_PCER   (3088) // Peripheral Clock Enable Register
-#define SYSC_PMC_PCDR   (3092) // Peripheral Clock Disable Register
-#define SYSC_PMC_PCSR   (3096) // Peripheral Clock Status Register
-#define SYSC_PMC_MOR    (3104) // Main Oscillator Register
-#define SYSC_PMC_MCFR   (3108) // Main Clock  Frequency Register
-#define SYSC_PMC_PLLR   (3116) // PLL Register
-#define SYSC_PMC_MCKR   (3120) // Master Clock Register
-#define SYSC_PMC_PCKR   (3136) // Programmable Clock Register
-#define SYSC_PMC_IER    (3168) // Interrupt Enable Register
-#define SYSC_PMC_IDR    (3172) // Interrupt Disable Register
-#define SYSC_PMC_SR     (3176) // Status Register
-#define SYSC_PMC_IMR    (3180) // Interrupt Mask Register
-#define SYSC_RSTC_RCR   (3328) // Reset Control Register
-#define SYSC_RSTC_RSR   (3332) // Reset Status Register
-#define SYSC_RSTC_RMR   (3336) // Reset Mode Register
-#define SYSC_RTTC_RTMR  (3360) // Real-time Mode Register
-#define SYSC_RTTC_RTAR  (3364) // Real-time Alarm Register
-#define SYSC_RTTC_RTVR  (3368) // Real-time Value Register
-#define SYSC_RTTC_RTSR  (3372) // Real-time Status Register
-#define SYSC_PITC_PIMR  (3376) // Period Interval Mode Register
-#define SYSC_PITC_PISR  (3380) // Period Interval Status Register
-#define SYSC_PITC_PIVR  (3384) // Period Interval Value Register
-#define SYSC_PITC_PIIR  (3388) // Period Interval Image Register
-#define SYSC_WDTC_WDCR  (3392) // Watchdog Control Register
-#define SYSC_WDTC_WDMR  (3396) // Watchdog Mode Register
-#define SYSC_WDTC_WDSR  (3400) // Watchdog Status Register
-#define SYSC_SYSC_VRPM  (3424) // Voltage Regulator Power Mode Register
-// -------- VRPM : (SYSC Offset: 0xd60) Voltage Regulator Power Mode Register --------
-#define AT91C_SYSC_PSTDBY         (0x1 <<  0) // (SYSC) Voltage Regulator Power Mode
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR System Peripherals */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_SYSC structure *** */
+#define SYSC_AIC_SMR         ( 0 )        /* Source Mode Register */
+#define SYSC_AIC_SVR         ( 128 )      /* Source Vector Register */
+#define SYSC_AIC_IVR         ( 256 )      /* IRQ Vector Register */
+#define SYSC_AIC_FVR         ( 260 )      /* FIQ Vector Register */
+#define SYSC_AIC_ISR         ( 264 )      /* Interrupt Status Register */
+#define SYSC_AIC_IPR         ( 268 )      /* Interrupt Pending Register */
+#define SYSC_AIC_IMR         ( 272 )      /* Interrupt Mask Register */
+#define SYSC_AIC_CISR        ( 276 )      /* Core Interrupt Status Register */
+#define SYSC_AIC_IECR        ( 288 )      /* Interrupt Enable Command Register */
+#define SYSC_AIC_IDCR        ( 292 )      /* Interrupt Disable Command Register */
+#define SYSC_AIC_ICCR        ( 296 )      /* Interrupt Clear Command Register */
+#define SYSC_AIC_ISCR        ( 300 )      /* Interrupt Set Command Register */
+#define SYSC_AIC_EOICR       ( 304 )      /* End of Interrupt Command Register */
+#define SYSC_AIC_SPU         ( 308 )      /* Spurious Vector Register */
+#define SYSC_AIC_DCR         ( 312 )      /* Debug Control Register (Protect) */
+#define SYSC_AIC_FFER        ( 320 )      /* Fast Forcing Enable Register */
+#define SYSC_AIC_FFDR        ( 324 )      /* Fast Forcing Disable Register */
+#define SYSC_AIC_FFSR        ( 328 )      /* Fast Forcing Status Register */
+#define SYSC_DBGU_CR         ( 512 )      /* Control Register */
+#define SYSC_DBGU_MR         ( 516 )      /* Mode Register */
+#define SYSC_DBGU_IER        ( 520 )      /* Interrupt Enable Register */
+#define SYSC_DBGU_IDR        ( 524 )      /* Interrupt Disable Register */
+#define SYSC_DBGU_IMR        ( 528 )      /* Interrupt Mask Register */
+#define SYSC_DBGU_CSR        ( 532 )      /* Channel Status Register */
+#define SYSC_DBGU_RHR        ( 536 )      /* Receiver Holding Register */
+#define SYSC_DBGU_THR        ( 540 )      /* Transmitter Holding Register */
+#define SYSC_DBGU_BRGR       ( 544 )      /* Baud Rate Generator Register */
+#define SYSC_DBGU_C1R        ( 576 )      /* Chip ID1 Register */
+#define SYSC_DBGU_C2R        ( 580 )      /* Chip ID2 Register */
+#define SYSC_DBGU_FNTR       ( 584 )      /* Force NTRST Register */
+#define SYSC_DBGU_RPR        ( 768 )      /* Receive Pointer Register */
+#define SYSC_DBGU_RCR        ( 772 )      /* Receive Counter Register */
+#define SYSC_DBGU_TPR        ( 776 )      /* Transmit Pointer Register */
+#define SYSC_DBGU_TCR        ( 780 )      /* Transmit Counter Register */
+#define SYSC_DBGU_RNPR       ( 784 )      /* Receive Next Pointer Register */
+#define SYSC_DBGU_RNCR       ( 788 )      /* Receive Next Counter Register */
+#define SYSC_DBGU_TNPR       ( 792 )      /* Transmit Next Pointer Register */
+#define SYSC_DBGU_TNCR       ( 796 )      /* Transmit Next Counter Register */
+#define SYSC_DBGU_PTCR       ( 800 )      /* PDC Transfer Control Register */
+#define SYSC_DBGU_PTSR       ( 804 )      /* PDC Transfer Status Register */
+#define SYSC_PIOA_PER        ( 1024 )     /* PIO Enable Register */
+#define SYSC_PIOA_PDR        ( 1028 )     /* PIO Disable Register */
+#define SYSC_PIOA_PSR        ( 1032 )     /* PIO Status Register */
+#define SYSC_PIOA_OER        ( 1040 )     /* Output Enable Register */
+#define SYSC_PIOA_ODR        ( 1044 )     /* Output Disable Registerr */
+#define SYSC_PIOA_OSR        ( 1048 )     /* Output Status Register */
+#define SYSC_PIOA_IFER       ( 1056 )     /* Input Filter Enable Register */
+#define SYSC_PIOA_IFDR       ( 1060 )     /* Input Filter Disable Register */
+#define SYSC_PIOA_IFSR       ( 1064 )     /* Input Filter Status Register */
+#define SYSC_PIOA_SODR       ( 1072 )     /* Set Output Data Register */
+#define SYSC_PIOA_CODR       ( 1076 )     /* Clear Output Data Register */
+#define SYSC_PIOA_ODSR       ( 1080 )     /* Output Data Status Register */
+#define SYSC_PIOA_PDSR       ( 1084 )     /* Pin Data Status Register */
+#define SYSC_PIOA_IER        ( 1088 )     /* Interrupt Enable Register */
+#define SYSC_PIOA_IDR        ( 1092 )     /* Interrupt Disable Register */
+#define SYSC_PIOA_IMR        ( 1096 )     /* Interrupt Mask Register */
+#define SYSC_PIOA_ISR        ( 1100 )     /* Interrupt Status Register */
+#define SYSC_PIOA_MDER       ( 1104 )     /* Multi-driver Enable Register */
+#define SYSC_PIOA_MDDR       ( 1108 )     /* Multi-driver Disable Register */
+#define SYSC_PIOA_MDSR       ( 1112 )     /* Multi-driver Status Register */
+#define SYSC_PIOA_PPUDR      ( 1120 )     /* Pull-up Disable Register */
+#define SYSC_PIOA_PPUER      ( 1124 )     /* Pull-up Enable Register */
+#define SYSC_PIOA_PPUSR      ( 1128 )     /* Pad Pull-up Status Register */
+#define SYSC_PIOA_ASR        ( 1136 )     /* Select A Register */
+#define SYSC_PIOA_BSR        ( 1140 )     /* Select B Register */
+#define SYSC_PIOA_ABSR       ( 1144 )     /* AB Select Status Register */
+#define SYSC_PIOA_OWER       ( 1184 )     /* Output Write Enable Register */
+#define SYSC_PIOA_OWDR       ( 1188 )     /* Output Write Disable Register */
+#define SYSC_PIOA_OWSR       ( 1192 )     /* Output Write Status Register */
+#define SYSC_PMC_SCER        ( 3072 )     /* System Clock Enable Register */
+#define SYSC_PMC_SCDR        ( 3076 )     /* System Clock Disable Register */
+#define SYSC_PMC_SCSR        ( 3080 )     /* System Clock Status Register */
+#define SYSC_PMC_PCER        ( 3088 )     /* Peripheral Clock Enable Register */
+#define SYSC_PMC_PCDR        ( 3092 )     /* Peripheral Clock Disable Register */
+#define SYSC_PMC_PCSR        ( 3096 )     /* Peripheral Clock Status Register */
+#define SYSC_PMC_MOR         ( 3104 )     /* Main Oscillator Register */
+#define SYSC_PMC_MCFR        ( 3108 )     /* Main Clock  Frequency Register */
+#define SYSC_PMC_PLLR        ( 3116 )     /* PLL Register */
+#define SYSC_PMC_MCKR        ( 3120 )     /* Master Clock Register */
+#define SYSC_PMC_PCKR        ( 3136 )     /* Programmable Clock Register */
+#define SYSC_PMC_IER         ( 3168 )     /* Interrupt Enable Register */
+#define SYSC_PMC_IDR         ( 3172 )     /* Interrupt Disable Register */
+#define SYSC_PMC_SR          ( 3176 )     /* Status Register */
+#define SYSC_PMC_IMR         ( 3180 )     /* Interrupt Mask Register */
+#define SYSC_RSTC_RCR        ( 3328 )     /* Reset Control Register */
+#define SYSC_RSTC_RSR        ( 3332 )     /* Reset Status Register */
+#define SYSC_RSTC_RMR        ( 3336 )     /* Reset Mode Register */
+#define SYSC_RTTC_RTMR       ( 3360 )     /* Real-time Mode Register */
+#define SYSC_RTTC_RTAR       ( 3364 )     /* Real-time Alarm Register */
+#define SYSC_RTTC_RTVR       ( 3368 )     /* Real-time Value Register */
+#define SYSC_RTTC_RTSR       ( 3372 )     /* Real-time Status Register */
+#define SYSC_PITC_PIMR       ( 3376 )     /* Period Interval Mode Register */
+#define SYSC_PITC_PISR       ( 3380 )     /* Period Interval Status Register */
+#define SYSC_PITC_PIVR       ( 3384 )     /* Period Interval Value Register */
+#define SYSC_PITC_PIIR       ( 3388 )     /* Period Interval Image Register */
+#define SYSC_WDTC_WDCR       ( 3392 )     /* Watchdog Control Register */
+#define SYSC_WDTC_WDMR       ( 3396 )     /* Watchdog Mode Register */
+#define SYSC_WDTC_WDSR       ( 3400 )     /* Watchdog Status Register */
+#define SYSC_SYSC_VRPM       ( 3424 )     /* Voltage Regulator Power Mode Register */
+/* -------- VRPM : (SYSC Offset: 0xd60) Voltage Regulator Power Mode Register -------- */
+#define AT91C_SYSC_PSTDBY    ( 0x1 << 0 ) /* (SYSC) Voltage Regulator Power Mode */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
-// *****************************************************************************
-// *** Register offset in AT91S_AIC structure ***
-#define AIC_SMR         ( 0) // Source Mode Register
-#define AIC_SVR         (128) // Source Vector Register
-#define AIC_IVR         (256) // IRQ Vector Register
-#define AIC_FVR         (260) // FIQ Vector Register
-#define AIC_ISR         (264) // Interrupt Status Register
-#define AIC_IPR         (268) // Interrupt Pending Register
-#define AIC_IMR         (272) // Interrupt Mask Register
-#define AIC_CISR        (276) // Core Interrupt Status Register
-#define AIC_IECR        (288) // Interrupt Enable Command Register
-#define AIC_IDCR        (292) // Interrupt Disable Command Register
-#define AIC_ICCR        (296) // Interrupt Clear Command Register
-#define AIC_ISCR        (300) // Interrupt Set Command Register
-#define AIC_EOICR       (304) // End of Interrupt Command Register
-#define AIC_SPU         (308) // Spurious Vector Register
-#define AIC_DCR         (312) // Debug Control Register (Protect)
-#define AIC_FFER        (320) // Fast Forcing Enable Register
-#define AIC_FFDR        (324) // Fast Forcing Disable Register
-#define AIC_FFSR        (328) // Fast Forcing Status Register
-// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
-#define AT91C_AIC_PRIOR           (0x7 <<  0) // (AIC) Priority Level
-#define     AT91C_AIC_PRIOR_LOWEST               (0x0) // (AIC) Lowest priority level
-#define     AT91C_AIC_PRIOR_HIGHEST              (0x7) // (AIC) Highest priority level
-#define AT91C_AIC_SRCTYPE         (0x3 <<  5) // (AIC) Interrupt Source Type
-#define     AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE  (0x0 <<  5) // (AIC) Internal Sources Code Label Level Sensitive
-#define     AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED   (0x1 <<  5) // (AIC) Internal Sources Code Label Edge triggered
-#define     AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL       (0x2 <<  5) // (AIC) External Sources Code Label High-level Sensitive
-#define     AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE    (0x3 <<  5) // (AIC) External Sources Code Label Positive Edge triggered
-// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
-#define AT91C_AIC_NFIQ            (0x1 <<  0) // (AIC) NFIQ Status
-#define AT91C_AIC_NIRQ            (0x1 <<  1) // (AIC) NIRQ Status
-// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
-#define AT91C_AIC_DCR_PROT        (0x1 <<  0) // (AIC) Protection Mode
-#define AT91C_AIC_DCR_GMSK        (0x1 <<  1) // (AIC) General Mask
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_AIC structure *** */
+#define AIC_SMR                                      ( 0 )        /* Source Mode Register */
+#define AIC_SVR                                      ( 128 )      /* Source Vector Register */
+#define AIC_IVR                                      ( 256 )      /* IRQ Vector Register */
+#define AIC_FVR                                      ( 260 )      /* FIQ Vector Register */
+#define AIC_ISR                                      ( 264 )      /* Interrupt Status Register */
+#define AIC_IPR                                      ( 268 )      /* Interrupt Pending Register */
+#define AIC_IMR                                      ( 272 )      /* Interrupt Mask Register */
+#define AIC_CISR                                     ( 276 )      /* Core Interrupt Status Register */
+#define AIC_IECR                                     ( 288 )      /* Interrupt Enable Command Register */
+#define AIC_IDCR                                     ( 292 )      /* Interrupt Disable Command Register */
+#define AIC_ICCR                                     ( 296 )      /* Interrupt Clear Command Register */
+#define AIC_ISCR                                     ( 300 )      /* Interrupt Set Command Register */
+#define AIC_EOICR                                    ( 304 )      /* End of Interrupt Command Register */
+#define AIC_SPU                                      ( 308 )      /* Spurious Vector Register */
+#define AIC_DCR                                      ( 312 )      /* Debug Control Register (Protect) */
+#define AIC_FFER                                     ( 320 )      /* Fast Forcing Enable Register */
+#define AIC_FFDR                                     ( 324 )      /* Fast Forcing Disable Register */
+#define AIC_FFSR                                     ( 328 )      /* Fast Forcing Status Register */
+/* -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- */
+#define AT91C_AIC_PRIOR                              ( 0x7 << 0 ) /* (AIC) Priority Level */
+#define     AT91C_AIC_PRIOR_LOWEST                   ( 0x0 )      /* (AIC) Lowest priority level */
+#define     AT91C_AIC_PRIOR_HIGHEST                  ( 0x7 )      /* (AIC) Highest priority level */
+#define AT91C_AIC_SRCTYPE                            ( 0x3 << 5 ) /* (AIC) Interrupt Source Type */
+#define     AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE    ( 0x0 << 5 ) /* (AIC) Internal Sources Code Label Level Sensitive */
+#define     AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED     ( 0x1 << 5 ) /* (AIC) Internal Sources Code Label Edge triggered */
+#define     AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL         ( 0x2 << 5 ) /* (AIC) External Sources Code Label High-level Sensitive */
+#define     AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE      ( 0x3 << 5 ) /* (AIC) External Sources Code Label Positive Edge triggered */
+/* -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- */
+#define AT91C_AIC_NFIQ                               ( 0x1 << 0 ) /* (AIC) NFIQ Status */
+#define AT91C_AIC_NIRQ                               ( 0x1 << 1 ) /* (AIC) NIRQ Status */
+/* -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- */
+#define AT91C_AIC_DCR_PROT                           ( 0x1 << 0 ) /* (AIC) Protection Mode */
+#define AT91C_AIC_DCR_GMSK                           ( 0x1 << 1 ) /* (AIC) General Mask */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Debug Unit
-// *****************************************************************************
-// *** Register offset in AT91S_DBGU structure ***
-#define DBGU_CR         ( 0) // Control Register
-#define DBGU_MR         ( 4) // Mode Register
-#define DBGU_IER        ( 8) // Interrupt Enable Register
-#define DBGU_IDR        (12) // Interrupt Disable Register
-#define DBGU_IMR        (16) // Interrupt Mask Register
-#define DBGU_CSR        (20) // Channel Status Register
-#define DBGU_RHR        (24) // Receiver Holding Register
-#define DBGU_THR        (28) // Transmitter Holding Register
-#define DBGU_BRGR       (32) // Baud Rate Generator Register
-#define DBGU_C1R        (64) // Chip ID1 Register
-#define DBGU_C2R        (68) // Chip ID2 Register
-#define DBGU_FNTR       (72) // Force NTRST Register
-#define DBGU_RPR        (256) // Receive Pointer Register
-#define DBGU_RCR        (260) // Receive Counter Register
-#define DBGU_TPR        (264) // Transmit Pointer Register
-#define DBGU_TCR        (268) // Transmit Counter Register
-#define DBGU_RNPR       (272) // Receive Next Pointer Register
-#define DBGU_RNCR       (276) // Receive Next Counter Register
-#define DBGU_TNPR       (280) // Transmit Next Pointer Register
-#define DBGU_TNCR       (284) // Transmit Next Counter Register
-#define DBGU_PTCR       (288) // PDC Transfer Control Register
-#define DBGU_PTSR       (292) // PDC Transfer Status Register
-// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
-#define AT91C_US_RSTRX            (0x1 <<  2) // (DBGU) Reset Receiver
-#define AT91C_US_RSTTX            (0x1 <<  3) // (DBGU) Reset Transmitter
-#define AT91C_US_RXEN             (0x1 <<  4) // (DBGU) Receiver Enable
-#define AT91C_US_RXDIS            (0x1 <<  5) // (DBGU) Receiver Disable
-#define AT91C_US_TXEN             (0x1 <<  6) // (DBGU) Transmitter Enable
-#define AT91C_US_TXDIS            (0x1 <<  7) // (DBGU) Transmitter Disable
-// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
-#define AT91C_US_PAR              (0x7 <<  9) // (DBGU) Parity type
-#define     AT91C_US_PAR_EVEN                 (0x0 <<  9) // (DBGU) Even Parity
-#define     AT91C_US_PAR_ODD                  (0x1 <<  9) // (DBGU) Odd Parity
-#define     AT91C_US_PAR_SPACE                (0x2 <<  9) // (DBGU) Parity forced to 0 (Space)
-#define     AT91C_US_PAR_MARK                 (0x3 <<  9) // (DBGU) Parity forced to 1 (Mark)
-#define     AT91C_US_PAR_NONE                 (0x4 <<  9) // (DBGU) No Parity
-#define     AT91C_US_PAR_MULTI_DROP           (0x6 <<  9) // (DBGU) Multi-drop mode
-#define AT91C_US_CHMODE           (0x3 << 14) // (DBGU) Channel Mode
-#define     AT91C_US_CHMODE_NORMAL               (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
-#define     AT91C_US_CHMODE_AUTO                 (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
-#define     AT91C_US_CHMODE_LOCAL                (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
-#define     AT91C_US_CHMODE_REMOTE               (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
-// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
-#define AT91C_US_RXRDY            (0x1 <<  0) // (DBGU) RXRDY Interrupt
-#define AT91C_US_TXRDY            (0x1 <<  1) // (DBGU) TXRDY Interrupt
-#define AT91C_US_ENDRX            (0x1 <<  3) // (DBGU) End of Receive Transfer Interrupt
-#define AT91C_US_ENDTX            (0x1 <<  4) // (DBGU) End of Transmit Interrupt
-#define AT91C_US_OVRE             (0x1 <<  5) // (DBGU) Overrun Interrupt
-#define AT91C_US_FRAME            (0x1 <<  6) // (DBGU) Framing Error Interrupt
-#define AT91C_US_PARE             (0x1 <<  7) // (DBGU) Parity Error Interrupt
-#define AT91C_US_TXEMPTY          (0x1 <<  9) // (DBGU) TXEMPTY Interrupt
-#define AT91C_US_TXBUFE           (0x1 << 11) // (DBGU) TXBUFE Interrupt
-#define AT91C_US_RXBUFF           (0x1 << 12) // (DBGU) RXBUFF Interrupt
-#define AT91C_US_COMM_TX          (0x1 << 30) // (DBGU) COMM_TX Interrupt
-#define AT91C_US_COMM_RX          (0x1 << 31) // (DBGU) COMM_RX Interrupt
-// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
-// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
-// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
-// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
-#define AT91C_US_FORCE_NTRST      (0x1 <<  0) // (DBGU) Force NTRST in JTAG
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Debug Unit */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_DBGU structure *** */
+#define DBGU_CR                        ( 0 )         /* Control Register */
+#define DBGU_MR                        ( 4 )         /* Mode Register */
+#define DBGU_IER                       ( 8 )         /* Interrupt Enable Register */
+#define DBGU_IDR                       ( 12 )        /* Interrupt Disable Register */
+#define DBGU_IMR                       ( 16 )        /* Interrupt Mask Register */
+#define DBGU_CSR                       ( 20 )        /* Channel Status Register */
+#define DBGU_RHR                       ( 24 )        /* Receiver Holding Register */
+#define DBGU_THR                       ( 28 )        /* Transmitter Holding Register */
+#define DBGU_BRGR                      ( 32 )        /* Baud Rate Generator Register */
+#define DBGU_C1R                       ( 64 )        /* Chip ID1 Register */
+#define DBGU_C2R                       ( 68 )        /* Chip ID2 Register */
+#define DBGU_FNTR                      ( 72 )        /* Force NTRST Register */
+#define DBGU_RPR                       ( 256 )       /* Receive Pointer Register */
+#define DBGU_RCR                       ( 260 )       /* Receive Counter Register */
+#define DBGU_TPR                       ( 264 )       /* Transmit Pointer Register */
+#define DBGU_TCR                       ( 268 )       /* Transmit Counter Register */
+#define DBGU_RNPR                      ( 272 )       /* Receive Next Pointer Register */
+#define DBGU_RNCR                      ( 276 )       /* Receive Next Counter Register */
+#define DBGU_TNPR                      ( 280 )       /* Transmit Next Pointer Register */
+#define DBGU_TNCR                      ( 284 )       /* Transmit Next Counter Register */
+#define DBGU_PTCR                      ( 288 )       /* PDC Transfer Control Register */
+#define DBGU_PTSR                      ( 292 )       /* PDC Transfer Status Register */
+/* -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- */
+#define AT91C_US_RSTRX                 ( 0x1 << 2 )  /* (DBGU) Reset Receiver */
+#define AT91C_US_RSTTX                 ( 0x1 << 3 )  /* (DBGU) Reset Transmitter */
+#define AT91C_US_RXEN                  ( 0x1 << 4 )  /* (DBGU) Receiver Enable */
+#define AT91C_US_RXDIS                 ( 0x1 << 5 )  /* (DBGU) Receiver Disable */
+#define AT91C_US_TXEN                  ( 0x1 << 6 )  /* (DBGU) Transmitter Enable */
+#define AT91C_US_TXDIS                 ( 0x1 << 7 )  /* (DBGU) Transmitter Disable */
+/* -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- */
+#define AT91C_US_PAR                   ( 0x7 << 9 )  /* (DBGU) Parity type */
+#define     AT91C_US_PAR_EVEN          ( 0x0 << 9 )  /* (DBGU) Even Parity */
+#define     AT91C_US_PAR_ODD           ( 0x1 << 9 )  /* (DBGU) Odd Parity */
+#define     AT91C_US_PAR_SPACE         ( 0x2 << 9 )  /* (DBGU) Parity forced to 0 (Space) */
+#define     AT91C_US_PAR_MARK          ( 0x3 << 9 )  /* (DBGU) Parity forced to 1 (Mark) */
+#define     AT91C_US_PAR_NONE          ( 0x4 << 9 )  /* (DBGU) No Parity */
+#define     AT91C_US_PAR_MULTI_DROP    ( 0x6 << 9 )  /* (DBGU) Multi-drop mode */
+#define AT91C_US_CHMODE                ( 0x3 << 14 ) /* (DBGU) Channel Mode */
+#define     AT91C_US_CHMODE_NORMAL     ( 0x0 << 14 ) /* (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. */
+#define     AT91C_US_CHMODE_AUTO       ( 0x1 << 14 ) /* (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. */
+#define     AT91C_US_CHMODE_LOCAL      ( 0x2 << 14 ) /* (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. */
+#define     AT91C_US_CHMODE_REMOTE     ( 0x3 << 14 ) /* (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. */
+/* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */
+#define AT91C_US_RXRDY                 ( 0x1 << 0 )  /* (DBGU) RXRDY Interrupt */
+#define AT91C_US_TXRDY                 ( 0x1 << 1 )  /* (DBGU) TXRDY Interrupt */
+#define AT91C_US_ENDRX                 ( 0x1 << 3 )  /* (DBGU) End of Receive Transfer Interrupt */
+#define AT91C_US_ENDTX                 ( 0x1 << 4 )  /* (DBGU) End of Transmit Interrupt */
+#define AT91C_US_OVRE                  ( 0x1 << 5 )  /* (DBGU) Overrun Interrupt */
+#define AT91C_US_FRAME                 ( 0x1 << 6 )  /* (DBGU) Framing Error Interrupt */
+#define AT91C_US_PARE                  ( 0x1 << 7 )  /* (DBGU) Parity Error Interrupt */
+#define AT91C_US_TXEMPTY               ( 0x1 << 9 )  /* (DBGU) TXEMPTY Interrupt */
+#define AT91C_US_TXBUFE                ( 0x1 << 11 ) /* (DBGU) TXBUFE Interrupt */
+#define AT91C_US_RXBUFF                ( 0x1 << 12 ) /* (DBGU) RXBUFF Interrupt */
+#define AT91C_US_COMM_TX               ( 0x1 << 30 ) /* (DBGU) COMM_TX Interrupt */
+#define AT91C_US_COMM_RX               ( 0x1 << 31 ) /* (DBGU) COMM_RX Interrupt */
+/* -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- */
+/* -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- */
+/* -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- */
+/* -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- */
+#define AT91C_US_FORCE_NTRST    ( 0x1 << 0 )  /* (DBGU) Force NTRST in JTAG */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Peripheral Data Controller
-// *****************************************************************************
-// *** Register offset in AT91S_PDC structure ***
-#define PDC_RPR         ( 0) // Receive Pointer Register
-#define PDC_RCR         ( 4) // Receive Counter Register
-#define PDC_TPR         ( 8) // Transmit Pointer Register
-#define PDC_TCR         (12) // Transmit Counter Register
-#define PDC_RNPR        (16) // Receive Next Pointer Register
-#define PDC_RNCR        (20) // Receive Next Counter Register
-#define PDC_TNPR        (24) // Transmit Next Pointer Register
-#define PDC_TNCR        (28) // Transmit Next Counter Register
-#define PDC_PTCR        (32) // PDC Transfer Control Register
-#define PDC_PTSR        (36) // PDC Transfer Status Register
-// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
-#define AT91C_PDC_RXTEN           (0x1 <<  0) // (PDC) Receiver Transfer Enable
-#define AT91C_PDC_RXTDIS          (0x1 <<  1) // (PDC) Receiver Transfer Disable
-#define AT91C_PDC_TXTEN           (0x1 <<  8) // (PDC) Transmitter Transfer Enable
-#define AT91C_PDC_TXTDIS          (0x1 <<  9) // (PDC) Transmitter Transfer Disable
-// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Peripheral Data Controller */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_PDC structure *** */
+#define PDC_RPR             ( 0 )        /* Receive Pointer Register */
+#define PDC_RCR             ( 4 )        /* Receive Counter Register */
+#define PDC_TPR             ( 8 )        /* Transmit Pointer Register */
+#define PDC_TCR             ( 12 )       /* Transmit Counter Register */
+#define PDC_RNPR            ( 16 )       /* Receive Next Pointer Register */
+#define PDC_RNCR            ( 20 )       /* Receive Next Counter Register */
+#define PDC_TNPR            ( 24 )       /* Transmit Next Pointer Register */
+#define PDC_TNCR            ( 28 )       /* Transmit Next Counter Register */
+#define PDC_PTCR            ( 32 )       /* PDC Transfer Control Register */
+#define PDC_PTSR            ( 36 )       /* PDC Transfer Status Register */
+/* -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */
+#define AT91C_PDC_RXTEN     ( 0x1 << 0 ) /* (PDC) Receiver Transfer Enable */
+#define AT91C_PDC_RXTDIS    ( 0x1 << 1 ) /* (PDC) Receiver Transfer Disable */
+#define AT91C_PDC_TXTEN     ( 0x1 << 8 ) /* (PDC) Transmitter Transfer Enable */
+#define AT91C_PDC_TXTDIS    ( 0x1 << 9 ) /* (PDC) Transmitter Transfer Disable */
+/* -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
-// *****************************************************************************
-// *** Register offset in AT91S_PIO structure ***
-#define PIO_PER         ( 0) // PIO Enable Register
-#define PIO_PDR         ( 4) // PIO Disable Register
-#define PIO_PSR         ( 8) // PIO Status Register
-#define PIO_OER         (16) // Output Enable Register
-#define PIO_ODR         (20) // Output Disable Registerr
-#define PIO_OSR         (24) // Output Status Register
-#define PIO_IFER        (32) // Input Filter Enable Register
-#define PIO_IFDR        (36) // Input Filter Disable Register
-#define PIO_IFSR        (40) // Input Filter Status Register
-#define PIO_SODR        (48) // Set Output Data Register
-#define PIO_CODR        (52) // Clear Output Data Register
-#define PIO_ODSR        (56) // Output Data Status Register
-#define PIO_PDSR        (60) // Pin Data Status Register
-#define PIO_IER         (64) // Interrupt Enable Register
-#define PIO_IDR         (68) // Interrupt Disable Register
-#define PIO_IMR         (72) // Interrupt Mask Register
-#define PIO_ISR         (76) // Interrupt Status Register
-#define PIO_MDER        (80) // Multi-driver Enable Register
-#define PIO_MDDR        (84) // Multi-driver Disable Register
-#define PIO_MDSR        (88) // Multi-driver Status Register
-#define PIO_PPUDR       (96) // Pull-up Disable Register
-#define PIO_PPUER       (100) // Pull-up Enable Register
-#define PIO_PPUSR       (104) // Pad Pull-up Status Register
-#define PIO_ASR         (112) // Select A Register
-#define PIO_BSR         (116) // Select B Register
-#define PIO_ABSR        (120) // AB Select Status Register
-#define PIO_OWER        (160) // Output Write Enable Register
-#define PIO_OWDR        (164) // Output Write Disable Register
-#define PIO_OWSR        (168) // Output Write Status Register
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Parallel Input Output Controller */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_PIO structure *** */
+#define PIO_PER      ( 0 )   /* PIO Enable Register */
+#define PIO_PDR      ( 4 )   /* PIO Disable Register */
+#define PIO_PSR      ( 8 )   /* PIO Status Register */
+#define PIO_OER      ( 16 )  /* Output Enable Register */
+#define PIO_ODR      ( 20 )  /* Output Disable Registerr */
+#define PIO_OSR      ( 24 )  /* Output Status Register */
+#define PIO_IFER     ( 32 )  /* Input Filter Enable Register */
+#define PIO_IFDR     ( 36 )  /* Input Filter Disable Register */
+#define PIO_IFSR     ( 40 )  /* Input Filter Status Register */
+#define PIO_SODR     ( 48 )  /* Set Output Data Register */
+#define PIO_CODR     ( 52 )  /* Clear Output Data Register */
+#define PIO_ODSR     ( 56 )  /* Output Data Status Register */
+#define PIO_PDSR     ( 60 )  /* Pin Data Status Register */
+#define PIO_IER      ( 64 )  /* Interrupt Enable Register */
+#define PIO_IDR      ( 68 )  /* Interrupt Disable Register */
+#define PIO_IMR      ( 72 )  /* Interrupt Mask Register */
+#define PIO_ISR      ( 76 )  /* Interrupt Status Register */
+#define PIO_MDER     ( 80 )  /* Multi-driver Enable Register */
+#define PIO_MDDR     ( 84 )  /* Multi-driver Disable Register */
+#define PIO_MDSR     ( 88 )  /* Multi-driver Status Register */
+#define PIO_PPUDR    ( 96 )  /* Pull-up Disable Register */
+#define PIO_PPUER    ( 100 ) /* Pull-up Enable Register */
+#define PIO_PPUSR    ( 104 ) /* Pad Pull-up Status Register */
+#define PIO_ASR      ( 112 ) /* Select A Register */
+#define PIO_BSR      ( 116 ) /* Select B Register */
+#define PIO_ABSR     ( 120 ) /* AB Select Status Register */
+#define PIO_OWER     ( 160 ) /* Output Write Enable Register */
+#define PIO_OWDR     ( 164 ) /* Output Write Disable Register */
+#define PIO_OWSR     ( 168 ) /* Output Write Status Register */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Clock Generator Controler
-// *****************************************************************************
-// *** Register offset in AT91S_CKGR structure ***
-#define CKGR_MOR        ( 0) // Main Oscillator Register
-#define CKGR_MCFR       ( 4) // Main Clock  Frequency Register
-#define CKGR_PLLR       (12) // PLL Register
-// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
-#define AT91C_CKGR_MOSCEN         (0x1 <<  0) // (CKGR) Main Oscillator Enable
-#define AT91C_CKGR_OSCBYPASS      (0x1 <<  1) // (CKGR) Main Oscillator Bypass
-#define AT91C_CKGR_OSCOUNT        (0xFF <<  8) // (CKGR) Main Oscillator Start-up Time
-// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
-#define AT91C_CKGR_MAINF          (0xFFFF <<  0) // (CKGR) Main Clock Frequency
-#define AT91C_CKGR_MAINRDY        (0x1 << 16) // (CKGR) Main Clock Ready
-// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
-#define AT91C_CKGR_DIV            (0xFF <<  0) // (CKGR) Divider Selected
-#define     AT91C_CKGR_DIV_0                    (0x0) // (CKGR) Divider output is 0
-#define     AT91C_CKGR_DIV_BYPASS               (0x1) // (CKGR) Divider is bypassed
-#define AT91C_CKGR_PLLCOUNT       (0x3F <<  8) // (CKGR) PLL Counter
-#define AT91C_CKGR_OUT            (0x3 << 14) // (CKGR) PLL Output Frequency Range
-#define     AT91C_CKGR_OUT_0                    (0x0 << 14) // (CKGR) Please refer to the PLL datasheet
-#define     AT91C_CKGR_OUT_1                    (0x1 << 14) // (CKGR) Please refer to the PLL datasheet
-#define     AT91C_CKGR_OUT_2                    (0x2 << 14) // (CKGR) Please refer to the PLL datasheet
-#define     AT91C_CKGR_OUT_3                    (0x3 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_MUL            (0x7FF << 16) // (CKGR) PLL Multiplier
-#define AT91C_CKGR_USBDIV         (0x3 << 28) // (CKGR) Divider for USB Clocks
-#define     AT91C_CKGR_USBDIV_0                    (0x0 << 28) // (CKGR) Divider output is PLL clock output
-#define     AT91C_CKGR_USBDIV_1                    (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
-#define     AT91C_CKGR_USBDIV_2                    (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Clock Generator Controller */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_CKGR structure *** */
+#define CKGR_MOR                     ( 0 )           /* Main Oscillator Register */
+#define CKGR_MCFR                    ( 4 )           /* Main Clock  Frequency Register */
+#define CKGR_PLLR                    ( 12 )          /* PLL Register */
+/* -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */
+#define AT91C_CKGR_MOSCEN            ( 0x1 << 0 )    /* (CKGR) Main Oscillator Enable */
+#define AT91C_CKGR_OSCBYPASS         ( 0x1 << 1 )    /* (CKGR) Main Oscillator Bypass */
+#define AT91C_CKGR_OSCOUNT           ( 0xFF << 8 )   /* (CKGR) Main Oscillator Start-up Time */
+/* -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- */
+#define AT91C_CKGR_MAINF             ( 0xFFFF << 0 ) /* (CKGR) Main Clock Frequency */
+#define AT91C_CKGR_MAINRDY           ( 0x1 << 16 )   /* (CKGR) Main Clock Ready */
+/* -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- */
+#define AT91C_CKGR_DIV               ( 0xFF << 0 )   /* (CKGR) Divider Selected */
+#define     AT91C_CKGR_DIV_0         ( 0x0 )         /* (CKGR) Divider output is 0 */
+#define     AT91C_CKGR_DIV_BYPASS    ( 0x1 )         /* (CKGR) Divider is bypassed */
+#define AT91C_CKGR_PLLCOUNT          ( 0x3F << 8 )   /* (CKGR) PLL Counter */
+#define AT91C_CKGR_OUT               ( 0x3 << 14 )   /* (CKGR) PLL Output Frequency Range */
+#define     AT91C_CKGR_OUT_0         ( 0x0 << 14 )   /* (CKGR) Please refer to the PLL datasheet */
+#define     AT91C_CKGR_OUT_1         ( 0x1 << 14 )   /* (CKGR) Please refer to the PLL datasheet */
+#define     AT91C_CKGR_OUT_2         ( 0x2 << 14 )   /* (CKGR) Please refer to the PLL datasheet */
+#define     AT91C_CKGR_OUT_3         ( 0x3 << 14 )   /* (CKGR) Please refer to the PLL datasheet */
+#define AT91C_CKGR_MUL               ( 0x7FF << 16 ) /* (CKGR) PLL Multiplier */
+#define AT91C_CKGR_USBDIV            ( 0x3 << 28 )   /* (CKGR) Divider for USB Clocks */
+#define     AT91C_CKGR_USBDIV_0      ( 0x0 << 28 )   /* (CKGR) Divider output is PLL clock output */
+#define     AT91C_CKGR_USBDIV_1      ( 0x1 << 28 )   /* (CKGR) Divider output is PLL clock output divided by 2 */
+#define     AT91C_CKGR_USBDIV_2      ( 0x2 << 28 )   /* (CKGR) Divider output is PLL clock output divided by 4 */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Power Management Controler
-// *****************************************************************************
-// *** Register offset in AT91S_PMC structure ***
-#define PMC_SCER        ( 0) // System Clock Enable Register
-#define PMC_SCDR        ( 4) // System Clock Disable Register
-#define PMC_SCSR        ( 8) // System Clock Status Register
-#define PMC_PCER        (16) // Peripheral Clock Enable Register
-#define PMC_PCDR        (20) // Peripheral Clock Disable Register
-#define PMC_PCSR        (24) // Peripheral Clock Status Register
-#define PMC_MOR         (32) // Main Oscillator Register
-#define PMC_MCFR        (36) // Main Clock  Frequency Register
-#define PMC_PLLR        (44) // PLL Register
-#define PMC_MCKR        (48) // Master Clock Register
-#define PMC_PCKR        (64) // Programmable Clock Register
-#define PMC_IER         (96) // Interrupt Enable Register
-#define PMC_IDR         (100) // Interrupt Disable Register
-#define PMC_SR          (104) // Status Register
-#define PMC_IMR         (108) // Interrupt Mask Register
-// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
-#define AT91C_PMC_PCK             (0x1 <<  0) // (PMC) Processor Clock
-#define AT91C_PMC_UDP             (0x1 <<  7) // (PMC) USB Device Port Clock
-#define AT91C_PMC_PCK0            (0x1 <<  8) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK1            (0x1 <<  9) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK2            (0x1 << 10) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK3            (0x1 << 11) // (PMC) Programmable Clock Output
-// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
-// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
-// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
-// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
-// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
-// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
-#define AT91C_PMC_CSS             (0x3 <<  0) // (PMC) Programmable Clock Selection
-#define     AT91C_PMC_CSS_SLOW_CLK             (0x0) // (PMC) Slow Clock is selected
-#define     AT91C_PMC_CSS_MAIN_CLK             (0x1) // (PMC) Main Clock is selected
-#define     AT91C_PMC_CSS_PLL_CLK              (0x3) // (PMC) Clock from PLL is selected
-#define AT91C_PMC_PRES            (0x7 <<  2) // (PMC) Programmable Clock Prescaler
-#define     AT91C_PMC_PRES_CLK                  (0x0 <<  2) // (PMC) Selected clock
-#define     AT91C_PMC_PRES_CLK_2                (0x1 <<  2) // (PMC) Selected clock divided by 2
-#define     AT91C_PMC_PRES_CLK_4                (0x2 <<  2) // (PMC) Selected clock divided by 4
-#define     AT91C_PMC_PRES_CLK_8                (0x3 <<  2) // (PMC) Selected clock divided by 8
-#define     AT91C_PMC_PRES_CLK_16               (0x4 <<  2) // (PMC) Selected clock divided by 16
-#define     AT91C_PMC_PRES_CLK_32               (0x5 <<  2) // (PMC) Selected clock divided by 32
-#define     AT91C_PMC_PRES_CLK_64               (0x6 <<  2) // (PMC) Selected clock divided by 64
-// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
-// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
-#define AT91C_PMC_MOSCS           (0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask
-#define AT91C_PMC_LOCK            (0x1 <<  2) // (PMC) PLL Status/Enable/Disable/Mask
-#define AT91C_PMC_MCKRDY          (0x1 <<  3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK0RDY         (0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK1RDY         (0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK2RDY         (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK3RDY         (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
-// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
-// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
-// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Power Management Controller */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_PMC structure *** */
+#define PMC_SCER          ( 0 )         /* System Clock Enable Register */
+#define PMC_SCDR          ( 4 )         /* System Clock Disable Register */
+#define PMC_SCSR          ( 8 )         /* System Clock Status Register */
+#define PMC_PCER          ( 16 )        /* Peripheral Clock Enable Register */
+#define PMC_PCDR          ( 20 )        /* Peripheral Clock Disable Register */
+#define PMC_PCSR          ( 24 )        /* Peripheral Clock Status Register */
+#define PMC_MOR           ( 32 )        /* Main Oscillator Register */
+#define PMC_MCFR          ( 36 )        /* Main Clock  Frequency Register */
+#define PMC_PLLR          ( 44 )        /* PLL Register */
+#define PMC_MCKR          ( 48 )        /* Master Clock Register */
+#define PMC_PCKR          ( 64 )        /* Programmable Clock Register */
+#define PMC_IER           ( 96 )        /* Interrupt Enable Register */
+#define PMC_IDR           ( 100 )       /* Interrupt Disable Register */
+#define PMC_SR            ( 104 )       /* Status Register */
+#define PMC_IMR           ( 108 )       /* Interrupt Mask Register */
+/* -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- */
+#define AT91C_PMC_PCK     ( 0x1 << 0 )  /* (PMC) Processor Clock */
+#define AT91C_PMC_UDP     ( 0x1 << 7 )  /* (PMC) USB Device Port Clock */
+#define AT91C_PMC_PCK0    ( 0x1 << 8 )  /* (PMC) Programmable Clock Output */
+#define AT91C_PMC_PCK1    ( 0x1 << 9 )  /* (PMC) Programmable Clock Output */
+#define AT91C_PMC_PCK2    ( 0x1 << 10 ) /* (PMC) Programmable Clock Output */
+#define AT91C_PMC_PCK3    ( 0x1 << 11 ) /* (PMC) Programmable Clock Output */
+/* -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- */
+/* -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- */
+/* -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- */
+/* -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- */
+/* -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- */
+/* -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- */
+#define AT91C_PMC_CSS                 ( 0x3 << 0 ) /* (PMC) Programmable Clock Selection */
+#define     AT91C_PMC_CSS_SLOW_CLK    ( 0x0 )      /* (PMC) Slow Clock is selected */
+#define     AT91C_PMC_CSS_MAIN_CLK    ( 0x1 )      /* (PMC) Main Clock is selected */
+#define     AT91C_PMC_CSS_PLL_CLK     ( 0x3 )      /* (PMC) Clock from PLL is selected */
+#define AT91C_PMC_PRES                ( 0x7 << 2 ) /* (PMC) Programmable Clock Prescaler */
+#define     AT91C_PMC_PRES_CLK        ( 0x0 << 2 ) /* (PMC) Selected clock */
+#define     AT91C_PMC_PRES_CLK_2      ( 0x1 << 2 ) /* (PMC) Selected clock divided by 2 */
+#define     AT91C_PMC_PRES_CLK_4      ( 0x2 << 2 ) /* (PMC) Selected clock divided by 4 */
+#define     AT91C_PMC_PRES_CLK_8      ( 0x3 << 2 ) /* (PMC) Selected clock divided by 8 */
+#define     AT91C_PMC_PRES_CLK_16     ( 0x4 << 2 ) /* (PMC) Selected clock divided by 16 */
+#define     AT91C_PMC_PRES_CLK_32     ( 0x5 << 2 ) /* (PMC) Selected clock divided by 32 */
+#define     AT91C_PMC_PRES_CLK_64     ( 0x6 << 2 ) /* (PMC) Selected clock divided by 64 */
+/* -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- */
+/* -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- */
+#define AT91C_PMC_MOSCS               ( 0x1 << 0 )  /* (PMC) MOSC Status/Enable/Disable/Mask */
+#define AT91C_PMC_LOCK                ( 0x1 << 2 )  /* (PMC) PLL Status/Enable/Disable/Mask */
+#define AT91C_PMC_MCKRDY              ( 0x1 << 3 )  /* (PMC) MCK_RDY Status/Enable/Disable/Mask */
+#define AT91C_PMC_PCK0RDY             ( 0x1 << 8 )  /* (PMC) PCK0_RDY Status/Enable/Disable/Mask */
+#define AT91C_PMC_PCK1RDY             ( 0x1 << 9 )  /* (PMC) PCK1_RDY Status/Enable/Disable/Mask */
+#define AT91C_PMC_PCK2RDY             ( 0x1 << 10 ) /* (PMC) PCK2_RDY Status/Enable/Disable/Mask */
+#define AT91C_PMC_PCK3RDY             ( 0x1 << 11 ) /* (PMC) PCK3_RDY Status/Enable/Disable/Mask */
+/* -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- */
+/* -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- */
+/* -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Reset Controller Interface
-// *****************************************************************************
-// *** Register offset in AT91S_RSTC structure ***
-#define RSTC_RCR        ( 0) // Reset Control Register
-#define RSTC_RSR        ( 4) // Reset Status Register
-#define RSTC_RMR        ( 8) // Reset Mode Register
-// -------- SYSC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
-#define AT91C_SYSC_PROCRST        (0x1 <<  0) // (RSTC) Processor Reset
-#define AT91C_SYSC_ICERST         (0x1 <<  1) // (RSTC) ICE Interface Reset
-#define AT91C_SYSC_PERRST         (0x1 <<  2) // (RSTC) Peripheral Reset
-#define AT91C_SYSC_EXTRST         (0x1 <<  3) // (RSTC) External Reset
-#define AT91C_SYSC_KEY            (0xFF << 24) // (RSTC) Password
-// -------- SYSC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
-#define AT91C_SYSC_URSTS          (0x1 <<  0) // (RSTC) User Reset Status
-#define AT91C_SYSC_BODSTS         (0x1 <<  1) // (RSTC) Brown-out Detection Status
-#define AT91C_SYSC_RSTTYP         (0x7 <<  8) // (RSTC) Reset Type
-#define     AT91C_SYSC_RSTTYP_POWERUP              (0x0 <<  8) // (RSTC) Power-up Reset. VDDCORE rising.
-#define     AT91C_SYSC_RSTTYP_WATCHDOG             (0x2 <<  8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
-#define     AT91C_SYSC_RSTTYP_SOFTWARE             (0x3 <<  8) // (RSTC) Software Reset. Processor reset required by the software.
-#define     AT91C_SYSC_RSTTYP_USER                 (0x4 <<  8) // (RSTC) User Reset. NRST pin detected low.
-#define     AT91C_SYSC_RSTTYP_BROWNOUT             (0x5 <<  8) // (RSTC) Brown-out Reset.
-#define AT91C_SYSC_NRSTL          (0x1 << 16) // (RSTC) NRST pin level
-#define AT91C_SYSC_SRCMP          (0x1 << 17) // (RSTC) Software Reset Command in Progress.
-// -------- SYSC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
-#define AT91C_SYSC_URSTEN         (0x1 <<  0) // (RSTC) User Reset Enable
-#define AT91C_SYSC_URSTIEN        (0x1 <<  4) // (RSTC) User Reset Interrupt Enable
-#define AT91C_SYSC_ERSTL          (0xF <<  8) // (RSTC) User Reset Enable
-#define AT91C_SYSC_BODIEN         (0x1 << 16) // (RSTC) Brown-out Detection Interrupt Enable
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Reset Controller Interface */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_RSTC structure *** */
+#define RSTC_RCR                          ( 0 )          /* Reset Control Register */
+#define RSTC_RSR                          ( 4 )          /* Reset Status Register */
+#define RSTC_RMR                          ( 8 )          /* Reset Mode Register */
+/* -------- SYSC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- */
+#define AT91C_SYSC_PROCRST                ( 0x1 << 0 )   /* (RSTC) Processor Reset */
+#define AT91C_SYSC_ICERST                 ( 0x1 << 1 )   /* (RSTC) ICE Interface Reset */
+#define AT91C_SYSC_PERRST                 ( 0x1 << 2 )   /* (RSTC) Peripheral Reset */
+#define AT91C_SYSC_EXTRST                 ( 0x1 << 3 )   /* (RSTC) External Reset */
+#define AT91C_SYSC_KEY                    ( 0xFF << 24 ) /* (RSTC) Password */
+/* -------- SYSC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- */
+#define AT91C_SYSC_URSTS                  ( 0x1 << 0 )   /* (RSTC) User Reset Status */
+#define AT91C_SYSC_BODSTS                 ( 0x1 << 1 )   /* (RSTC) Brown-out Detection Status */
+#define AT91C_SYSC_RSTTYP                 ( 0x7 << 8 )   /* (RSTC) Reset Type */
+#define     AT91C_SYSC_RSTTYP_POWERUP     ( 0x0 << 8 )   /* (RSTC) Power-up Reset. VDDCORE rising. */
+#define     AT91C_SYSC_RSTTYP_WATCHDOG    ( 0x2 << 8 )   /* (RSTC) Watchdog Reset. Watchdog overflow occurred. */
+#define     AT91C_SYSC_RSTTYP_SOFTWARE    ( 0x3 << 8 )   /* (RSTC) Software Reset. Processor reset required by the software. */
+#define     AT91C_SYSC_RSTTYP_USER        ( 0x4 << 8 )   /* (RSTC) User Reset. NRST pin detected low. */
+#define     AT91C_SYSC_RSTTYP_BROWNOUT    ( 0x5 << 8 )   /* (RSTC) Brown-out Reset. */
+#define AT91C_SYSC_NRSTL                  ( 0x1 << 16 )  /* (RSTC) NRST pin level */
+#define AT91C_SYSC_SRCMP                  ( 0x1 << 17 )  /* (RSTC) Software Reset Command in Progress. */
+/* -------- SYSC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- */
+#define AT91C_SYSC_URSTEN                 ( 0x1 << 0 )   /* (RSTC) User Reset Enable */
+#define AT91C_SYSC_URSTIEN                ( 0x1 << 4 )   /* (RSTC) User Reset Interrupt Enable */
+#define AT91C_SYSC_ERSTL                  ( 0xF << 8 )   /* (RSTC) User Reset Enable */
+#define AT91C_SYSC_BODIEN                 ( 0x1 << 16 )  /* (RSTC) Brown-out Detection Interrupt Enable */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
-// *****************************************************************************
-// *** Register offset in AT91S_RTTC structure ***
-#define RTTC_RTMR       ( 0) // Real-time Mode Register
-#define RTTC_RTAR       ( 4) // Real-time Alarm Register
-#define RTTC_RTVR       ( 8) // Real-time Value Register
-#define RTTC_RTSR       (12) // Real-time Status Register
-// -------- SYSC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
-#define AT91C_SYSC_RTPRES         (0xFFFF <<  0) // (RTTC) Real-time Timer Prescaler Value
-#define AT91C_SYSC_ALMIEN         (0x1 << 16) // (RTTC) Alarm Interrupt Enable
-#define AT91C_SYSC_RTTINCIEN      (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
-#define AT91C_SYSC_RTTRST         (0x1 << 18) // (RTTC) Real Time Timer Restart
-// -------- SYSC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
-#define AT91C_SYSC_ALMV           (0x0 <<  0) // (RTTC) Alarm Value
-// -------- SYSC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
-#define AT91C_SYSC_CRTV           (0x0 <<  0) // (RTTC) Current Real-time Value
-// -------- SYSC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
-#define AT91C_SYSC_ALMS           (0x1 <<  0) // (RTTC) Real-time Alarm Status
-#define AT91C_SYSC_RTTINC         (0x1 <<  1) // (RTTC) Real-time Timer Increment
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_RTTC structure *** */
+#define RTTC_RTMR               ( 0 )           /* Real-time Mode Register */
+#define RTTC_RTAR               ( 4 )           /* Real-time Alarm Register */
+#define RTTC_RTVR               ( 8 )           /* Real-time Value Register */
+#define RTTC_RTSR               ( 12 )          /* Real-time Status Register */
+/* -------- SYSC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- */
+#define AT91C_SYSC_RTPRES       ( 0xFFFF << 0 ) /* (RTTC) Real-time Timer Prescaler Value */
+#define AT91C_SYSC_ALMIEN       ( 0x1 << 16 )   /* (RTTC) Alarm Interrupt Enable */
+#define AT91C_SYSC_RTTINCIEN    ( 0x1 << 17 )   /* (RTTC) Real Time Timer Increment Interrupt Enable */
+#define AT91C_SYSC_RTTRST       ( 0x1 << 18 )   /* (RTTC) Real Time Timer Restart */
+/* -------- SYSC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- */
+#define AT91C_SYSC_ALMV         ( 0x0 << 0 )    /* (RTTC) Alarm Value */
+/* -------- SYSC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- */
+#define AT91C_SYSC_CRTV         ( 0x0 << 0 )    /* (RTTC) Current Real-time Value */
+/* -------- SYSC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- */
+#define AT91C_SYSC_ALMS         ( 0x1 << 0 )    /* (RTTC) Real-time Alarm Status */
+#define AT91C_SYSC_RTTINC       ( 0x1 << 1 )    /* (RTTC) Real-time Timer Increment */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
-// *****************************************************************************
-// *** Register offset in AT91S_PITC structure ***
-#define PITC_PIMR       ( 0) // Period Interval Mode Register
-#define PITC_PISR       ( 4) // Period Interval Status Register
-#define PITC_PIVR       ( 8) // Period Interval Value Register
-#define PITC_PIIR       (12) // Period Interval Image Register
-// -------- SYSC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
-#define AT91C_SYSC_PIV            (0xFFFFF <<  0) // (PITC) Periodic Interval Value
-#define AT91C_SYSC_PITEN          (0x1 << 24) // (PITC) Periodic Interval Timer Enabled
-#define AT91C_SYSC_PITIEN         (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
-// -------- SYSC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
-#define AT91C_SYSC_PITS           (0x1 <<  0) // (PITC) Periodic Interval Timer Status
-// -------- SYSC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
-#define AT91C_SYSC_CPIV           (0xFFFFF <<  0) // (PITC) Current Periodic Interval Value
-#define AT91C_SYSC_PICNT          (0xFFF << 20) // (PITC) Periodic Interval Counter
-// -------- SYSC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_PITC structure *** */
+#define PITC_PIMR            ( 0 )            /* Period Interval Mode Register */
+#define PITC_PISR            ( 4 )            /* Period Interval Status Register */
+#define PITC_PIVR            ( 8 )            /* Period Interval Value Register */
+#define PITC_PIIR            ( 12 )           /* Period Interval Image Register */
+/* -------- SYSC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- */
+#define AT91C_SYSC_PIV       ( 0xFFFFF << 0 ) /* (PITC) Periodic Interval Value */
+#define AT91C_SYSC_PITEN     ( 0x1 << 24 )    /* (PITC) Periodic Interval Timer Enabled */
+#define AT91C_SYSC_PITIEN    ( 0x1 << 25 )    /* (PITC) Periodic Interval Timer Interrupt Enable */
+/* -------- SYSC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- */
+#define AT91C_SYSC_PITS      ( 0x1 << 0 )     /* (PITC) Periodic Interval Timer Status */
+/* -------- SYSC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- */
+#define AT91C_SYSC_CPIV      ( 0xFFFFF << 0 ) /* (PITC) Current Periodic Interval Value */
+#define AT91C_SYSC_PICNT     ( 0xFFF << 20 )  /* (PITC) Periodic Interval Counter */
+/* -------- SYSC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
-// *****************************************************************************
-// *** Register offset in AT91S_WDTC structure ***
-#define WDTC_WDCR       ( 0) // Watchdog Control Register
-#define WDTC_WDMR       ( 4) // Watchdog Mode Register
-#define WDTC_WDSR       ( 8) // Watchdog Status Register
-// -------- SYSC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
-#define AT91C_SYSC_WDRSTT         (0x1 <<  0) // (WDTC) Watchdog Restart
-// -------- SYSC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
-#define AT91C_SYSC_WDV            (0xFFF <<  0) // (WDTC) Watchdog Timer Restart
-#define AT91C_SYSC_WDFIEN         (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
-#define AT91C_SYSC_WDRSTEN        (0x1 << 13) // (WDTC) Watchdog Reset Enable
-#define AT91C_SYSC_WDRPROC        (0x1 << 14) // (WDTC) Watchdog Timer Restart
-#define AT91C_SYSC_WDDIS          (0x1 << 15) // (WDTC) Watchdog Disable
-#define AT91C_SYSC_WDD            (0xFFF << 16) // (WDTC) Watchdog Delta Value
-#define AT91C_SYSC_WDDBGHLT       (0x1 << 28) // (WDTC) Watchdog Debug Halt
-#define AT91C_SYSC_WDIDLEHLT      (0x1 << 29) // (WDTC) Watchdog Idle Halt
-// -------- SYSC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
-#define AT91C_SYSC_WDUNF          (0x1 <<  0) // (WDTC) Watchdog Underflow
-#define AT91C_SYSC_WDERR          (0x1 <<  1) // (WDTC) Watchdog Error
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_WDTC structure *** */
+#define WDTC_WDCR               ( 0 )           /* Watchdog Control Register */
+#define WDTC_WDMR               ( 4 )           /* Watchdog Mode Register */
+#define WDTC_WDSR               ( 8 )           /* Watchdog Status Register */
+/* -------- SYSC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- */
+#define AT91C_SYSC_WDRSTT       ( 0x1 << 0 )    /* (WDTC) Watchdog Restart */
+/* -------- SYSC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- */
+#define AT91C_SYSC_WDV          ( 0xFFF << 0 )  /* (WDTC) Watchdog Timer Restart */
+#define AT91C_SYSC_WDFIEN       ( 0x1 << 12 )   /* (WDTC) Watchdog Fault Interrupt Enable */
+#define AT91C_SYSC_WDRSTEN      ( 0x1 << 13 )   /* (WDTC) Watchdog Reset Enable */
+#define AT91C_SYSC_WDRPROC      ( 0x1 << 14 )   /* (WDTC) Watchdog Timer Restart */
+#define AT91C_SYSC_WDDIS        ( 0x1 << 15 )   /* (WDTC) Watchdog Disable */
+#define AT91C_SYSC_WDD          ( 0xFFF << 16 ) /* (WDTC) Watchdog Delta Value */
+#define AT91C_SYSC_WDDBGHLT     ( 0x1 << 28 )   /* (WDTC) Watchdog Debug Halt */
+#define AT91C_SYSC_WDIDLEHLT    ( 0x1 << 29 )   /* (WDTC) Watchdog Idle Halt */
+/* -------- SYSC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- */
+#define AT91C_SYSC_WDUNF        ( 0x1 << 0 )    /* (WDTC) Watchdog Underflow */
+#define AT91C_SYSC_WDERR        ( 0x1 << 1 )    /* (WDTC) Watchdog Error */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Memory Controller Interface
-// *****************************************************************************
-// *** Register offset in AT91S_MC structure ***
-#define MC_RCR          ( 0) // MC Remap Control Register
-#define MC_ASR          ( 4) // MC Abort Status Register
-#define MC_AASR         ( 8) // MC Abort Address Status Register
-#define MC_FMR          (96) // MC Flash Mode Register
-#define MC_FCR          (100) // MC Flash Command Register
-#define MC_FSR          (104) // MC Flash Status Register
-// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
-#define AT91C_MC_RCB              (0x1 <<  0) // (MC) Remap Command Bit
-// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
-#define AT91C_MC_UNDADD           (0x1 <<  0) // (MC) Undefined Addess Abort Status
-#define AT91C_MC_MISADD           (0x1 <<  1) // (MC) Misaligned Addess Abort Status
-#define AT91C_MC_ABTSZ            (0x3 <<  8) // (MC) Abort Size Status
-#define     AT91C_MC_ABTSZ_BYTE                 (0x0 <<  8) // (MC) Byte
-#define     AT91C_MC_ABTSZ_HWORD                (0x1 <<  8) // (MC) Half-word
-#define     AT91C_MC_ABTSZ_WORD                 (0x2 <<  8) // (MC) Word
-#define AT91C_MC_ABTTYP           (0x3 << 10) // (MC) Abort Type Status
-#define     AT91C_MC_ABTTYP_DATAR                (0x0 << 10) // (MC) Data Read
-#define     AT91C_MC_ABTTYP_DATAW                (0x1 << 10) // (MC) Data Write
-#define     AT91C_MC_ABTTYP_FETCH                (0x2 << 10) // (MC) Code Fetch
-#define AT91C_MC_MST0             (0x1 << 16) // (MC) Master 0 Abort Source
-#define AT91C_MC_MST1             (0x1 << 17) // (MC) Master 1 Abort Source
-#define AT91C_MC_SVMST0           (0x1 << 24) // (MC) Saved Master 0 Abort Source
-#define AT91C_MC_SVMST1           (0x1 << 25) // (MC) Saved Master 1 Abort Source
-// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
-#define AT91C_MC_FRDY             (0x1 <<  0) // (MC) Flash Ready
-#define AT91C_MC_LOCKE            (0x1 <<  2) // (MC) Lock Error
-#define AT91C_MC_PROGE            (0x1 <<  3) // (MC) Programming Error
-#define AT91C_MC_NEBP             (0x1 <<  7) // (MC) No Erase Before Programming
-#define AT91C_MC_FWS              (0x3 <<  8) // (MC) Flash Wait State
-#define     AT91C_MC_FWS_0FWS                 (0x0 <<  8) // (MC) 1 cycle for Read, 2 for Write operations
-#define     AT91C_MC_FWS_1FWS                 (0x1 <<  8) // (MC) 2 cycles for Read, 3 for Write operations
-#define     AT91C_MC_FWS_2FWS                 (0x2 <<  8) // (MC) 3 cycles for Read, 4 for Write operations
-#define     AT91C_MC_FWS_3FWS                 (0x3 <<  8) // (MC) 4 cycles for Read, 4 for Write operations
-#define AT91C_MC_FMCN             (0xFF << 16) // (MC) Flash Microsecond Cycle Number
-// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
-#define AT91C_MC_FCMD             (0xF <<  0) // (MC) Flash Command
-#define     AT91C_MC_FCMD_START_PROG           (0x1) // (MC) Starts the programming of th epage specified by PAGEN.
-#define     AT91C_MC_FCMD_LOCK                 (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define     AT91C_MC_FCMD_PROG_AND_LOCK        (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
-#define     AT91C_MC_FCMD_UNLOCK               (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define     AT91C_MC_FCMD_ERASE_ALL            (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
-#define     AT91C_MC_FCMD_SET_GP_NVM           (0xB) // (MC) Set General Purpose NVM bits.
-#define     AT91C_MC_FCMD_CLR_GP_NVM           (0xD) // (MC) Clear General Purpose NVM bits.
-#define     AT91C_MC_FCMD_SET_SECURITY         (0xF) // (MC) Set Security Bit.
-#define AT91C_MC_PAGEN            (0x3FF <<  8) // (MC) Page Number
-#define AT91C_MC_KEY              (0xFF << 24) // (MC) Writing Protect Key
-// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register --------
-#define AT91C_MC_SECURITY         (0x1 <<  4) // (MC) Security Bit Status
-#define AT91C_MC_GPNVM0           (0x1 <<  8) // (MC) Sector 0 Lock Status
-#define AT91C_MC_GPNVM1           (0x1 <<  9) // (MC) Sector 1 Lock Status
-#define AT91C_MC_GPNVM2           (0x1 << 10) // (MC) Sector 2 Lock Status
-#define AT91C_MC_GPNVM3           (0x1 << 11) // (MC) Sector 3 Lock Status
-#define AT91C_MC_GPNVM4           (0x1 << 12) // (MC) Sector 4 Lock Status
-#define AT91C_MC_GPNVM5           (0x1 << 13) // (MC) Sector 5 Lock Status
-#define AT91C_MC_GPNVM6           (0x1 << 14) // (MC) Sector 6 Lock Status
-#define AT91C_MC_GPNVM7           (0x1 << 15) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS0           (0x1 << 16) // (MC) Sector 0 Lock Status
-#define AT91C_MC_LOCKS1           (0x1 << 17) // (MC) Sector 1 Lock Status
-#define AT91C_MC_LOCKS2           (0x1 << 18) // (MC) Sector 2 Lock Status
-#define AT91C_MC_LOCKS3           (0x1 << 19) // (MC) Sector 3 Lock Status
-#define AT91C_MC_LOCKS4           (0x1 << 20) // (MC) Sector 4 Lock Status
-#define AT91C_MC_LOCKS5           (0x1 << 21) // (MC) Sector 5 Lock Status
-#define AT91C_MC_LOCKS6           (0x1 << 22) // (MC) Sector 6 Lock Status
-#define AT91C_MC_LOCKS7           (0x1 << 23) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS8           (0x1 << 24) // (MC) Sector 8 Lock Status
-#define AT91C_MC_LOCKS9           (0x1 << 25) // (MC) Sector 9 Lock Status
-#define AT91C_MC_LOCKS10          (0x1 << 26) // (MC) Sector 10 Lock Status
-#define AT91C_MC_LOCKS11          (0x1 << 27) // (MC) Sector 11 Lock Status
-#define AT91C_MC_LOCKS12          (0x1 << 28) // (MC) Sector 12 Lock Status
-#define AT91C_MC_LOCKS13          (0x1 << 29) // (MC) Sector 13 Lock Status
-#define AT91C_MC_LOCKS14          (0x1 << 30) // (MC) Sector 14 Lock Status
-#define AT91C_MC_LOCKS15          (0x1 << 31) // (MC) Sector 15 Lock Status
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Memory Controller Interface */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_MC structure *** */
+#define MC_RCR                             ( 0 )          /* MC Remap Control Register */
+#define MC_ASR                             ( 4 )          /* MC Abort Status Register */
+#define MC_AASR                            ( 8 )          /* MC Abort Address Status Register */
+#define MC_FMR                             ( 96 )         /* MC Flash Mode Register */
+#define MC_FCR                             ( 100 )        /* MC Flash Command Register */
+#define MC_FSR                             ( 104 )        /* MC Flash Status Register */
+/* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */
+#define AT91C_MC_RCB                       ( 0x1 << 0 )   /* (MC) Remap Command Bit */
+/* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */
+#define AT91C_MC_UNDADD                    ( 0x1 << 0 )   /* (MC) Undefined Addess Abort Status */
+#define AT91C_MC_MISADD                    ( 0x1 << 1 )   /* (MC) Misaligned Addess Abort Status */
+#define AT91C_MC_ABTSZ                     ( 0x3 << 8 )   /* (MC) Abort Size Status */
+#define     AT91C_MC_ABTSZ_BYTE            ( 0x0 << 8 )   /* (MC) Byte */
+#define     AT91C_MC_ABTSZ_HWORD           ( 0x1 << 8 )   /* (MC) Half-word */
+#define     AT91C_MC_ABTSZ_WORD            ( 0x2 << 8 )   /* (MC) Word */
+#define AT91C_MC_ABTTYP                    ( 0x3 << 10 )  /* (MC) Abort Type Status */
+#define     AT91C_MC_ABTTYP_DATAR          ( 0x0 << 10 )  /* (MC) Data Read */
+#define     AT91C_MC_ABTTYP_DATAW          ( 0x1 << 10 )  /* (MC) Data Write */
+#define     AT91C_MC_ABTTYP_FETCH          ( 0x2 << 10 )  /* (MC) Code Fetch */
+#define AT91C_MC_MST0                      ( 0x1 << 16 )  /* (MC) Master 0 Abort Source */
+#define AT91C_MC_MST1                      ( 0x1 << 17 )  /* (MC) Master 1 Abort Source */
+#define AT91C_MC_SVMST0                    ( 0x1 << 24 )  /* (MC) Saved Master 0 Abort Source */
+#define AT91C_MC_SVMST1                    ( 0x1 << 25 )  /* (MC) Saved Master 1 Abort Source */
+/* -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- */
+#define AT91C_MC_FRDY                      ( 0x1 << 0 )   /* (MC) Flash Ready */
+#define AT91C_MC_LOCKE                     ( 0x1 << 2 )   /* (MC) Lock Error */
+#define AT91C_MC_PROGE                     ( 0x1 << 3 )   /* (MC) Programming Error */
+#define AT91C_MC_NEBP                      ( 0x1 << 7 )   /* (MC) No Erase Before Programming */
+#define AT91C_MC_FWS                       ( 0x3 << 8 )   /* (MC) Flash Wait State */
+#define     AT91C_MC_FWS_0FWS              ( 0x0 << 8 )   /* (MC) 1 cycle for Read, 2 for Write operations */
+#define     AT91C_MC_FWS_1FWS              ( 0x1 << 8 )   /* (MC) 2 cycles for Read, 3 for Write operations */
+#define     AT91C_MC_FWS_2FWS              ( 0x2 << 8 )   /* (MC) 3 cycles for Read, 4 for Write operations */
+#define     AT91C_MC_FWS_3FWS              ( 0x3 << 8 )   /* (MC) 4 cycles for Read, 4 for Write operations */
+#define AT91C_MC_FMCN                      ( 0xFF << 16 ) /* (MC) Flash Microsecond Cycle Number */
+/* -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- */
+#define AT91C_MC_FCMD                      ( 0xF << 0 )   /* (MC) Flash Command */
+#define     AT91C_MC_FCMD_START_PROG       ( 0x1 )        /* (MC) Starts the programming of th epage specified by PAGEN. */
+#define     AT91C_MC_FCMD_LOCK             ( 0x2 )        /* (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */
+#define     AT91C_MC_FCMD_PROG_AND_LOCK    ( 0x3 )        /* (MC) The lock sequence automatically happens after the programming sequence is completed. */
+#define     AT91C_MC_FCMD_UNLOCK           ( 0x4 )        /* (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */
+#define     AT91C_MC_FCMD_ERASE_ALL        ( 0x8 )        /* (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. */
+#define     AT91C_MC_FCMD_SET_GP_NVM       ( 0xB )        /* (MC) Set General Purpose NVM bits. */
+#define     AT91C_MC_FCMD_CLR_GP_NVM       ( 0xD )        /* (MC) Clear General Purpose NVM bits. */
+#define     AT91C_MC_FCMD_SET_SECURITY     ( 0xF )        /* (MC) Set Security Bit. */
+#define AT91C_MC_PAGEN                     ( 0x3FF << 8 ) /* (MC) Page Number */
+#define AT91C_MC_KEY                       ( 0xFF << 24 ) /* (MC) Writing Protect Key */
+/* -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- */
+#define AT91C_MC_SECURITY                  ( 0x1 << 4 )   /* (MC) Security Bit Status */
+#define AT91C_MC_GPNVM0                    ( 0x1 << 8 )   /* (MC) Sector 0 Lock Status */
+#define AT91C_MC_GPNVM1                    ( 0x1 << 9 )   /* (MC) Sector 1 Lock Status */
+#define AT91C_MC_GPNVM2                    ( 0x1 << 10 )  /* (MC) Sector 2 Lock Status */
+#define AT91C_MC_GPNVM3                    ( 0x1 << 11 )  /* (MC) Sector 3 Lock Status */
+#define AT91C_MC_GPNVM4                    ( 0x1 << 12 )  /* (MC) Sector 4 Lock Status */
+#define AT91C_MC_GPNVM5                    ( 0x1 << 13 )  /* (MC) Sector 5 Lock Status */
+#define AT91C_MC_GPNVM6                    ( 0x1 << 14 )  /* (MC) Sector 6 Lock Status */
+#define AT91C_MC_GPNVM7                    ( 0x1 << 15 )  /* (MC) Sector 7 Lock Status */
+#define AT91C_MC_LOCKS0                    ( 0x1 << 16 )  /* (MC) Sector 0 Lock Status */
+#define AT91C_MC_LOCKS1                    ( 0x1 << 17 )  /* (MC) Sector 1 Lock Status */
+#define AT91C_MC_LOCKS2                    ( 0x1 << 18 )  /* (MC) Sector 2 Lock Status */
+#define AT91C_MC_LOCKS3                    ( 0x1 << 19 )  /* (MC) Sector 3 Lock Status */
+#define AT91C_MC_LOCKS4                    ( 0x1 << 20 )  /* (MC) Sector 4 Lock Status */
+#define AT91C_MC_LOCKS5                    ( 0x1 << 21 )  /* (MC) Sector 5 Lock Status */
+#define AT91C_MC_LOCKS6                    ( 0x1 << 22 )  /* (MC) Sector 6 Lock Status */
+#define AT91C_MC_LOCKS7                    ( 0x1 << 23 )  /* (MC) Sector 7 Lock Status */
+#define AT91C_MC_LOCKS8                    ( 0x1 << 24 )  /* (MC) Sector 8 Lock Status */
+#define AT91C_MC_LOCKS9                    ( 0x1 << 25 )  /* (MC) Sector 9 Lock Status */
+#define AT91C_MC_LOCKS10                   ( 0x1 << 26 )  /* (MC) Sector 10 Lock Status */
+#define AT91C_MC_LOCKS11                   ( 0x1 << 27 )  /* (MC) Sector 11 Lock Status */
+#define AT91C_MC_LOCKS12                   ( 0x1 << 28 )  /* (MC) Sector 12 Lock Status */
+#define AT91C_MC_LOCKS13                   ( 0x1 << 29 )  /* (MC) Sector 13 Lock Status */
+#define AT91C_MC_LOCKS14                   ( 0x1 << 30 )  /* (MC) Sector 14 Lock Status */
+#define AT91C_MC_LOCKS15                   ( 0x1 << 31 )  /* (MC) Sector 15 Lock Status */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
-// *****************************************************************************
-// *** Register offset in AT91S_SPI structure ***
-#define SPI_CR          ( 0) // Control Register
-#define SPI_MR          ( 4) // Mode Register
-#define SPI_RDR         ( 8) // Receive Data Register
-#define SPI_TDR         (12) // Transmit Data Register
-#define SPI_SR          (16) // Status Register
-#define SPI_IER         (20) // Interrupt Enable Register
-#define SPI_IDR         (24) // Interrupt Disable Register
-#define SPI_IMR         (28) // Interrupt Mask Register
-#define SPI_CSR         (48) // Chip Select Register
-#define SPI_RPR         (256) // Receive Pointer Register
-#define SPI_RCR         (260) // Receive Counter Register
-#define SPI_TPR         (264) // Transmit Pointer Register
-#define SPI_TCR         (268) // Transmit Counter Register
-#define SPI_RNPR        (272) // Receive Next Pointer Register
-#define SPI_RNCR        (276) // Receive Next Counter Register
-#define SPI_TNPR        (280) // Transmit Next Pointer Register
-#define SPI_TNCR        (284) // Transmit Next Counter Register
-#define SPI_PTCR        (288) // PDC Transfer Control Register
-#define SPI_PTSR        (292) // PDC Transfer Status Register
-// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
-#define AT91C_SPI_SPIEN           (0x1 <<  0) // (SPI) SPI Enable
-#define AT91C_SPI_SPIDIS          (0x1 <<  1) // (SPI) SPI Disable
-#define AT91C_SPI_SWRST           (0x1 <<  7) // (SPI) SPI Software reset
-#define AT91C_SPI_LASTXFER        (0x1 << 24) // (SPI) SPI Last Transfer
-// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
-#define AT91C_SPI_MSTR            (0x1 <<  0) // (SPI) Master/Slave Mode
-#define AT91C_SPI_PS              (0x1 <<  1) // (SPI) Peripheral Select
-#define     AT91C_SPI_PS_FIXED                (0x0 <<  1) // (SPI) Fixed Peripheral Select
-#define     AT91C_SPI_PS_VARIABLE             (0x1 <<  1) // (SPI) Variable Peripheral Select
-#define AT91C_SPI_PCSDEC          (0x1 <<  2) // (SPI) Chip Select Decode
-#define AT91C_SPI_FDIV            (0x1 <<  3) // (SPI) Clock Selection
-#define AT91C_SPI_MODFDIS         (0x1 <<  4) // (SPI) Mode Fault Detection
-#define AT91C_SPI_LLB             (0x1 <<  7) // (SPI) Clock Selection
-#define AT91C_SPI_PCS             (0xF << 16) // (SPI) Peripheral Chip Select
-#define AT91C_SPI_DLYBCS          (0xFF << 24) // (SPI) Delay Between Chip Selects
-// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
-#define AT91C_SPI_RD              (0xFFFF <<  0) // (SPI) Receive Data
-#define AT91C_SPI_RPCS            (0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
-#define AT91C_SPI_TD              (0xFFFF <<  0) // (SPI) Transmit Data
-#define AT91C_SPI_TPCS            (0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
-#define AT91C_SPI_RDRF            (0x1 <<  0) // (SPI) Receive Data Register Full
-#define AT91C_SPI_TDRE            (0x1 <<  1) // (SPI) Transmit Data Register Empty
-#define AT91C_SPI_MODF            (0x1 <<  2) // (SPI) Mode Fault Error
-#define AT91C_SPI_OVRES           (0x1 <<  3) // (SPI) Overrun Error Status
-#define AT91C_SPI_ENDRX           (0x1 <<  4) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_ENDTX           (0x1 <<  5) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_RXBUFF          (0x1 <<  6) // (SPI) RXBUFF Interrupt
-#define AT91C_SPI_TXBUFE          (0x1 <<  7) // (SPI) TXBUFE Interrupt
-#define AT91C_SPI_NSSR            (0x1 <<  8) // (SPI) NSSR Interrupt
-#define AT91C_SPI_TXEMPTY         (0x1 <<  9) // (SPI) TXEMPTY Interrupt
-#define AT91C_SPI_SPIENS          (0x1 << 16) // (SPI) Enable Status
-// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
-// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
-// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
-// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
-#define AT91C_SPI_CPOL            (0x1 <<  0) // (SPI) Clock Polarity
-#define AT91C_SPI_NCPHA           (0x1 <<  1) // (SPI) Clock Phase
-#define AT91C_SPI_CSAAT           (0x1 <<  2) // (SPI) Chip Select Active After Transfer
-#define AT91C_SPI_BITS            (0xF <<  4) // (SPI) Bits Per Transfer
-#define     AT91C_SPI_BITS_8                    (0x0 <<  4) // (SPI) 8 Bits Per transfer
-#define     AT91C_SPI_BITS_9                    (0x1 <<  4) // (SPI) 9 Bits Per transfer
-#define     AT91C_SPI_BITS_10                   (0x2 <<  4) // (SPI) 10 Bits Per transfer
-#define     AT91C_SPI_BITS_11                   (0x3 <<  4) // (SPI) 11 Bits Per transfer
-#define     AT91C_SPI_BITS_12                   (0x4 <<  4) // (SPI) 12 Bits Per transfer
-#define     AT91C_SPI_BITS_13                   (0x5 <<  4) // (SPI) 13 Bits Per transfer
-#define     AT91C_SPI_BITS_14                   (0x6 <<  4) // (SPI) 14 Bits Per transfer
-#define     AT91C_SPI_BITS_15                   (0x7 <<  4) // (SPI) 15 Bits Per transfer
-#define     AT91C_SPI_BITS_16                   (0x8 <<  4) // (SPI) 16 Bits Per transfer
-#define AT91C_SPI_SCBR            (0xFF <<  8) // (SPI) Serial Clock Baud Rate
-#define AT91C_SPI_DLYBS           (0xFF << 16) // (SPI) Serial Clock Baud Rate
-#define AT91C_SPI_DLYBCT          (0xFF << 24) // (SPI) Delay Between Consecutive Transfers
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Serial Parallel Interface */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_SPI structure *** */
+#define SPI_CR                       ( 0 )           /* Control Register */
+#define SPI_MR                       ( 4 )           /* Mode Register */
+#define SPI_RDR                      ( 8 )           /* Receive Data Register */
+#define SPI_TDR                      ( 12 )          /* Transmit Data Register */
+#define SPI_SR                       ( 16 )          /* Status Register */
+#define SPI_IER                      ( 20 )          /* Interrupt Enable Register */
+#define SPI_IDR                      ( 24 )          /* Interrupt Disable Register */
+#define SPI_IMR                      ( 28 )          /* Interrupt Mask Register */
+#define SPI_CSR                      ( 48 )          /* Chip Select Register */
+#define SPI_RPR                      ( 256 )         /* Receive Pointer Register */
+#define SPI_RCR                      ( 260 )         /* Receive Counter Register */
+#define SPI_TPR                      ( 264 )         /* Transmit Pointer Register */
+#define SPI_TCR                      ( 268 )         /* Transmit Counter Register */
+#define SPI_RNPR                     ( 272 )         /* Receive Next Pointer Register */
+#define SPI_RNCR                     ( 276 )         /* Receive Next Counter Register */
+#define SPI_TNPR                     ( 280 )         /* Transmit Next Pointer Register */
+#define SPI_TNCR                     ( 284 )         /* Transmit Next Counter Register */
+#define SPI_PTCR                     ( 288 )         /* PDC Transfer Control Register */
+#define SPI_PTSR                     ( 292 )         /* PDC Transfer Status Register */
+/* -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */
+#define AT91C_SPI_SPIEN              ( 0x1 << 0 )    /* (SPI) SPI Enable */
+#define AT91C_SPI_SPIDIS             ( 0x1 << 1 )    /* (SPI) SPI Disable */
+#define AT91C_SPI_SWRST              ( 0x1 << 7 )    /* (SPI) SPI Software reset */
+#define AT91C_SPI_LASTXFER           ( 0x1 << 24 )   /* (SPI) SPI Last Transfer */
+/* -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- */
+#define AT91C_SPI_MSTR               ( 0x1 << 0 )    /* (SPI) Master/Slave Mode */
+#define AT91C_SPI_PS                 ( 0x1 << 1 )    /* (SPI) Peripheral Select */
+#define     AT91C_SPI_PS_FIXED       ( 0x0 << 1 )    /* (SPI) Fixed Peripheral Select */
+#define     AT91C_SPI_PS_VARIABLE    ( 0x1 << 1 )    /* (SPI) Variable Peripheral Select */
+#define AT91C_SPI_PCSDEC             ( 0x1 << 2 )    /* (SPI) Chip Select Decode */
+#define AT91C_SPI_FDIV               ( 0x1 << 3 )    /* (SPI) Clock Selection */
+#define AT91C_SPI_MODFDIS            ( 0x1 << 4 )    /* (SPI) Mode Fault Detection */
+#define AT91C_SPI_LLB                ( 0x1 << 7 )    /* (SPI) Clock Selection */
+#define AT91C_SPI_PCS                ( 0xF << 16 )   /* (SPI) Peripheral Chip Select */
+#define AT91C_SPI_DLYBCS             ( 0xFF << 24 )  /* (SPI) Delay Between Chip Selects */
+/* -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- */
+#define AT91C_SPI_RD                 ( 0xFFFF << 0 ) /* (SPI) Receive Data */
+#define AT91C_SPI_RPCS               ( 0xF << 16 )   /* (SPI) Peripheral Chip Select Status */
+/* -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- */
+#define AT91C_SPI_TD                 ( 0xFFFF << 0 ) /* (SPI) Transmit Data */
+#define AT91C_SPI_TPCS               ( 0xF << 16 )   /* (SPI) Peripheral Chip Select Status */
+/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
+#define AT91C_SPI_RDRF               ( 0x1 << 0 )    /* (SPI) Receive Data Register Full */
+#define AT91C_SPI_TDRE               ( 0x1 << 1 )    /* (SPI) Transmit Data Register Empty */
+#define AT91C_SPI_MODF               ( 0x1 << 2 )    /* (SPI) Mode Fault Error */
+#define AT91C_SPI_OVRES              ( 0x1 << 3 )    /* (SPI) Overrun Error Status */
+#define AT91C_SPI_ENDRX              ( 0x1 << 4 )    /* (SPI) End of Receiver Transfer */
+#define AT91C_SPI_ENDTX              ( 0x1 << 5 )    /* (SPI) End of Receiver Transfer */
+#define AT91C_SPI_RXBUFF             ( 0x1 << 6 )    /* (SPI) RXBUFF Interrupt */
+#define AT91C_SPI_TXBUFE             ( 0x1 << 7 )    /* (SPI) TXBUFE Interrupt */
+#define AT91C_SPI_NSSR               ( 0x1 << 8 )    /* (SPI) NSSR Interrupt */
+#define AT91C_SPI_TXEMPTY            ( 0x1 << 9 )    /* (SPI) TXEMPTY Interrupt */
+#define AT91C_SPI_SPIENS             ( 0x1 << 16 )   /* (SPI) Enable Status */
+/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
+/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
+/* -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */
+/* -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */
+#define AT91C_SPI_CPOL           ( 0x1 << 0 )   /* (SPI) Clock Polarity */
+#define AT91C_SPI_NCPHA          ( 0x1 << 1 )   /* (SPI) Clock Phase */
+#define AT91C_SPI_CSAAT          ( 0x1 << 2 )   /* (SPI) Chip Select Active After Transfer */
+#define AT91C_SPI_BITS           ( 0xF << 4 )   /* (SPI) Bits Per Transfer */
+#define     AT91C_SPI_BITS_8     ( 0x0 << 4 )   /* (SPI) 8 Bits Per transfer */
+#define     AT91C_SPI_BITS_9     ( 0x1 << 4 )   /* (SPI) 9 Bits Per transfer */
+#define     AT91C_SPI_BITS_10    ( 0x2 << 4 )   /* (SPI) 10 Bits Per transfer */
+#define     AT91C_SPI_BITS_11    ( 0x3 << 4 )   /* (SPI) 11 Bits Per transfer */
+#define     AT91C_SPI_BITS_12    ( 0x4 << 4 )   /* (SPI) 12 Bits Per transfer */
+#define     AT91C_SPI_BITS_13    ( 0x5 << 4 )   /* (SPI) 13 Bits Per transfer */
+#define     AT91C_SPI_BITS_14    ( 0x6 << 4 )   /* (SPI) 14 Bits Per transfer */
+#define     AT91C_SPI_BITS_15    ( 0x7 << 4 )   /* (SPI) 15 Bits Per transfer */
+#define     AT91C_SPI_BITS_16    ( 0x8 << 4 )   /* (SPI) 16 Bits Per transfer */
+#define AT91C_SPI_SCBR           ( 0xFF << 8 )  /* (SPI) Serial Clock Baud Rate */
+#define AT91C_SPI_DLYBS          ( 0xFF << 16 ) /* (SPI) Serial Clock Baud Rate */
+#define AT91C_SPI_DLYBCT         ( 0xFF << 24 ) /* (SPI) Delay Between Consecutive Transfers */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
-// *****************************************************************************
-// *** Register offset in AT91S_ADC structure ***
-#define ADC_CR          ( 0) // ADC Control Register
-#define ADC_MR          ( 4) // ADC Mode Register
-#define ADC_CHER        (16) // ADC Channel Enable Register
-#define ADC_CHDR        (20) // ADC Channel Disable Register
-#define ADC_CHSR        (24) // ADC Channel Status Register
-#define ADC_SR          (28) // ADC Status Register
-#define ADC_LCDR        (32) // ADC Last Converted Data Register
-#define ADC_IER         (36) // ADC Interrupt Enable Register
-#define ADC_IDR         (40) // ADC Interrupt Disable Register
-#define ADC_IMR         (44) // ADC Interrupt Mask Register
-#define ADC_CDR0        (48) // ADC Channel Data Register 0
-#define ADC_CDR1        (52) // ADC Channel Data Register 1
-#define ADC_CDR2        (56) // ADC Channel Data Register 2
-#define ADC_CDR3        (60) // ADC Channel Data Register 3
-#define ADC_CDR4        (64) // ADC Channel Data Register 4
-#define ADC_CDR5        (68) // ADC Channel Data Register 5
-#define ADC_CDR6        (72) // ADC Channel Data Register 6
-#define ADC_CDR7        (76) // ADC Channel Data Register 7
-#define ADC_RPR         (256) // Receive Pointer Register
-#define ADC_RCR         (260) // Receive Counter Register
-#define ADC_TPR         (264) // Transmit Pointer Register
-#define ADC_TCR         (268) // Transmit Counter Register
-#define ADC_RNPR        (272) // Receive Next Pointer Register
-#define ADC_RNCR        (276) // Receive Next Counter Register
-#define ADC_TNPR        (280) // Transmit Next Pointer Register
-#define ADC_TNCR        (284) // Transmit Next Counter Register
-#define ADC_PTCR        (288) // PDC Transfer Control Register
-#define ADC_PTSR        (292) // PDC Transfer Status Register
-// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
-#define AT91C_ADC_SWRST           (0x1 <<  0) // (ADC) Software Reset
-#define AT91C_ADC_START           (0x1 <<  1) // (ADC) Start Conversion
-// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
-#define AT91C_ADC_TRGEN           (0x1 <<  0) // (ADC) Trigger Enable
-#define     AT91C_ADC_TRGEN_DIS                  (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
-#define     AT91C_ADC_TRGEN_EN                   (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
-#define AT91C_ADC_TRGSEL          (0x7 <<  1) // (ADC) Trigger Selection
-#define     AT91C_ADC_TRGSEL_TIOA0                (0x0 <<  1) // (ADC) Selected TRGSEL = TIAO0
-#define     AT91C_ADC_TRGSEL_TIOA1                (0x1 <<  1) // (ADC) Selected TRGSEL = TIAO1
-#define     AT91C_ADC_TRGSEL_TIOA2                (0x2 <<  1) // (ADC) Selected TRGSEL = TIAO2
-#define     AT91C_ADC_TRGSEL_TIOA3                (0x3 <<  1) // (ADC) Selected TRGSEL = TIAO3
-#define     AT91C_ADC_TRGSEL_TIOA4                (0x4 <<  1) // (ADC) Selected TRGSEL = TIAO4
-#define     AT91C_ADC_TRGSEL_TIOA5                (0x5 <<  1) // (ADC) Selected TRGSEL = TIAO5
-#define     AT91C_ADC_TRGSEL_EXT                  (0x6 <<  1) // (ADC) Selected TRGSEL = External Trigger
-#define AT91C_ADC_LOWRES          (0x1 <<  4) // (ADC) Resolution.
-#define     AT91C_ADC_LOWRES_10_BIT               (0x0 <<  4) // (ADC) 10-bit resolution
-#define     AT91C_ADC_LOWRES_8_BIT                (0x1 <<  4) // (ADC) 8-bit resolution
-#define AT91C_ADC_SLEEP           (0x1 <<  5) // (ADC) Sleep Mode
-#define     AT91C_ADC_SLEEP_NORMAL_MODE          (0x0 <<  5) // (ADC) Normal Mode
-#define     AT91C_ADC_SLEEP_MODE                 (0x1 <<  5) // (ADC) Sleep Mode
-#define AT91C_ADC_PRESCAL         (0x3F <<  8) // (ADC) Prescaler rate selection
-#define AT91C_ADC_STARTUP         (0x1F << 16) // (ADC) Startup Time
-#define AT91C_ADC_SHTIM           (0xF << 24) // (ADC) Sample & Hold Time
-// --------     ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
-#define AT91C_ADC_CH0             (0x1 <<  0) // (ADC) Channel 0
-#define AT91C_ADC_CH1             (0x1 <<  1) // (ADC) Channel 1
-#define AT91C_ADC_CH2             (0x1 <<  2) // (ADC) Channel 2
-#define AT91C_ADC_CH3             (0x1 <<  3) // (ADC) Channel 3
-#define AT91C_ADC_CH4             (0x1 <<  4) // (ADC) Channel 4
-#define AT91C_ADC_CH5             (0x1 <<  5) // (ADC) Channel 5
-#define AT91C_ADC_CH6             (0x1 <<  6) // (ADC) Channel 6
-#define AT91C_ADC_CH7             (0x1 <<  7) // (ADC) Channel 7
-// --------     ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
-// --------     ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
-// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
-#define AT91C_ADC_EOC0            (0x1 <<  0) // (ADC) End of Conversion
-#define AT91C_ADC_EOC1            (0x1 <<  1) // (ADC) End of Conversion
-#define AT91C_ADC_EOC2            (0x1 <<  2) // (ADC) End of Conversion
-#define AT91C_ADC_EOC3            (0x1 <<  3) // (ADC) End of Conversion
-#define AT91C_ADC_EOC4            (0x1 <<  4) // (ADC) End of Conversion
-#define AT91C_ADC_EOC5            (0x1 <<  5) // (ADC) End of Conversion
-#define AT91C_ADC_EOC6            (0x1 <<  6) // (ADC) End of Conversion
-#define AT91C_ADC_EOC7            (0x1 <<  7) // (ADC) End of Conversion
-#define AT91C_ADC_OVRE0           (0x1 <<  8) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE1           (0x1 <<  9) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE2           (0x1 << 10) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE3           (0x1 << 11) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE4           (0x1 << 12) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE5           (0x1 << 13) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE6           (0x1 << 14) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE7           (0x1 << 15) // (ADC) Overrun Error
-#define AT91C_ADC_DRDY            (0x1 << 16) // (ADC) Data Ready
-#define AT91C_ADC_GOVRE           (0x1 << 17) // (ADC) General Overrun
-#define AT91C_ADC_ENDRX           (0x1 << 18) // (ADC) End of Receiver Transfer
-#define AT91C_ADC_RXBUFF          (0x1 << 19) // (ADC) RXBUFF Interrupt
-// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
-#define AT91C_ADC_LDATA           (0x3FF <<  0) // (ADC) Last Data Converted
-// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
-// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
-// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
-// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
-#define AT91C_ADC_DATA            (0x3FF <<  0) // (ADC) Converted Data
-// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
-// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
-// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
-// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
-// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
-// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
-// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_ADC structure *** */
+#define ADC_CR                             ( 0 )          /* ADC Control Register */
+#define ADC_MR                             ( 4 )          /* ADC Mode Register */
+#define ADC_CHER                           ( 16 )         /* ADC Channel Enable Register */
+#define ADC_CHDR                           ( 20 )         /* ADC Channel Disable Register */
+#define ADC_CHSR                           ( 24 )         /* ADC Channel Status Register */
+#define ADC_SR                             ( 28 )         /* ADC Status Register */
+#define ADC_LCDR                           ( 32 )         /* ADC Last Converted Data Register */
+#define ADC_IER                            ( 36 )         /* ADC Interrupt Enable Register */
+#define ADC_IDR                            ( 40 )         /* ADC Interrupt Disable Register */
+#define ADC_IMR                            ( 44 )         /* ADC Interrupt Mask Register */
+#define ADC_CDR0                           ( 48 )         /* ADC Channel Data Register 0 */
+#define ADC_CDR1                           ( 52 )         /* ADC Channel Data Register 1 */
+#define ADC_CDR2                           ( 56 )         /* ADC Channel Data Register 2 */
+#define ADC_CDR3                           ( 60 )         /* ADC Channel Data Register 3 */
+#define ADC_CDR4                           ( 64 )         /* ADC Channel Data Register 4 */
+#define ADC_CDR5                           ( 68 )         /* ADC Channel Data Register 5 */
+#define ADC_CDR6                           ( 72 )         /* ADC Channel Data Register 6 */
+#define ADC_CDR7                           ( 76 )         /* ADC Channel Data Register 7 */
+#define ADC_RPR                            ( 256 )        /* Receive Pointer Register */
+#define ADC_RCR                            ( 260 )        /* Receive Counter Register */
+#define ADC_TPR                            ( 264 )        /* Transmit Pointer Register */
+#define ADC_TCR                            ( 268 )        /* Transmit Counter Register */
+#define ADC_RNPR                           ( 272 )        /* Receive Next Pointer Register */
+#define ADC_RNCR                           ( 276 )        /* Receive Next Counter Register */
+#define ADC_TNPR                           ( 280 )        /* Transmit Next Pointer Register */
+#define ADC_TNCR                           ( 284 )        /* Transmit Next Counter Register */
+#define ADC_PTCR                           ( 288 )        /* PDC Transfer Control Register */
+#define ADC_PTSR                           ( 292 )        /* PDC Transfer Status Register */
+/* -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- */
+#define AT91C_ADC_SWRST                    ( 0x1 << 0 )   /* (ADC) Software Reset */
+#define AT91C_ADC_START                    ( 0x1 << 1 )   /* (ADC) Start Conversion */
+/* -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- */
+#define AT91C_ADC_TRGEN                    ( 0x1 << 0 )   /* (ADC) Trigger Enable */
+#define     AT91C_ADC_TRGEN_DIS            ( 0x0 )        /* (ADC) Hardware triggers are disabled. Starting a conversion is only possible by software */
+#define     AT91C_ADC_TRGEN_EN             ( 0x1 )        /* (ADC) Hardware trigger selected by TRGSEL field is enabled. */
+#define AT91C_ADC_TRGSEL                   ( 0x7 << 1 )   /* (ADC) Trigger Selection */
+#define     AT91C_ADC_TRGSEL_TIOA0         ( 0x0 << 1 )   /* (ADC) Selected TRGSEL = TIAO0 */
+#define     AT91C_ADC_TRGSEL_TIOA1         ( 0x1 << 1 )   /* (ADC) Selected TRGSEL = TIAO1 */
+#define     AT91C_ADC_TRGSEL_TIOA2         ( 0x2 << 1 )   /* (ADC) Selected TRGSEL = TIAO2 */
+#define     AT91C_ADC_TRGSEL_TIOA3         ( 0x3 << 1 )   /* (ADC) Selected TRGSEL = TIAO3 */
+#define     AT91C_ADC_TRGSEL_TIOA4         ( 0x4 << 1 )   /* (ADC) Selected TRGSEL = TIAO4 */
+#define     AT91C_ADC_TRGSEL_TIOA5         ( 0x5 << 1 )   /* (ADC) Selected TRGSEL = TIAO5 */
+#define     AT91C_ADC_TRGSEL_EXT           ( 0x6 << 1 )   /* (ADC) Selected TRGSEL = External Trigger */
+#define AT91C_ADC_LOWRES                   ( 0x1 << 4 )   /* (ADC) Resolution. */
+#define     AT91C_ADC_LOWRES_10_BIT        ( 0x0 << 4 )   /* (ADC) 10-bit resolution */
+#define     AT91C_ADC_LOWRES_8_BIT         ( 0x1 << 4 )   /* (ADC) 8-bit resolution */
+#define AT91C_ADC_SLEEP                    ( 0x1 << 5 )   /* (ADC) Sleep Mode */
+#define     AT91C_ADC_SLEEP_NORMAL_MODE    ( 0x0 << 5 )   /* (ADC) Normal Mode */
+#define     AT91C_ADC_SLEEP_MODE           ( 0x1 << 5 )   /* (ADC) Sleep Mode */
+#define AT91C_ADC_PRESCAL                  ( 0x3F << 8 )  /* (ADC) Prescaler rate selection */
+#define AT91C_ADC_STARTUP                  ( 0x1F << 16 ) /* (ADC) Startup Time */
+#define AT91C_ADC_SHTIM                    ( 0xF << 24 )  /* (ADC) Sample & Hold Time */
+/* --------     ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- */
+#define AT91C_ADC_CH0                      ( 0x1 << 0 )   /* (ADC) Channel 0 */
+#define AT91C_ADC_CH1                      ( 0x1 << 1 )   /* (ADC) Channel 1 */
+#define AT91C_ADC_CH2                      ( 0x1 << 2 )   /* (ADC) Channel 2 */
+#define AT91C_ADC_CH3                      ( 0x1 << 3 )   /* (ADC) Channel 3 */
+#define AT91C_ADC_CH4                      ( 0x1 << 4 )   /* (ADC) Channel 4 */
+#define AT91C_ADC_CH5                      ( 0x1 << 5 )   /* (ADC) Channel 5 */
+#define AT91C_ADC_CH6                      ( 0x1 << 6 )   /* (ADC) Channel 6 */
+#define AT91C_ADC_CH7                      ( 0x1 << 7 )   /* (ADC) Channel 7 */
+/* --------     ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- */
+/* --------     ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- */
+/* -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- */
+#define AT91C_ADC_EOC0      ( 0x1 << 0 )      /* (ADC) End of Conversion */
+#define AT91C_ADC_EOC1      ( 0x1 << 1 )      /* (ADC) End of Conversion */
+#define AT91C_ADC_EOC2      ( 0x1 << 2 )      /* (ADC) End of Conversion */
+#define AT91C_ADC_EOC3      ( 0x1 << 3 )      /* (ADC) End of Conversion */
+#define AT91C_ADC_EOC4      ( 0x1 << 4 )      /* (ADC) End of Conversion */
+#define AT91C_ADC_EOC5      ( 0x1 << 5 )      /* (ADC) End of Conversion */
+#define AT91C_ADC_EOC6      ( 0x1 << 6 )      /* (ADC) End of Conversion */
+#define AT91C_ADC_EOC7      ( 0x1 << 7 )      /* (ADC) End of Conversion */
+#define AT91C_ADC_OVRE0     ( 0x1 << 8 )      /* (ADC) Overrun Error */
+#define AT91C_ADC_OVRE1     ( 0x1 << 9 )      /* (ADC) Overrun Error */
+#define AT91C_ADC_OVRE2     ( 0x1 << 10 )     /* (ADC) Overrun Error */
+#define AT91C_ADC_OVRE3     ( 0x1 << 11 )     /* (ADC) Overrun Error */
+#define AT91C_ADC_OVRE4     ( 0x1 << 12 )     /* (ADC) Overrun Error */
+#define AT91C_ADC_OVRE5     ( 0x1 << 13 )     /* (ADC) Overrun Error */
+#define AT91C_ADC_OVRE6     ( 0x1 << 14 )     /* (ADC) Overrun Error */
+#define AT91C_ADC_OVRE7     ( 0x1 << 15 )     /* (ADC) Overrun Error */
+#define AT91C_ADC_DRDY      ( 0x1 << 16 )     /* (ADC) Data Ready */
+#define AT91C_ADC_GOVRE     ( 0x1 << 17 )     /* (ADC) General Overrun */
+#define AT91C_ADC_ENDRX     ( 0x1 << 18 )     /* (ADC) End of Receiver Transfer */
+#define AT91C_ADC_RXBUFF    ( 0x1 << 19 )     /* (ADC) RXBUFF Interrupt */
+/* -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- */
+#define AT91C_ADC_LDATA     ( 0x3FF << 0 )    /* (ADC) Last Data Converted */
+/* -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- */
+/* -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- */
+/* -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- */
+/* -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- */
+#define AT91C_ADC_DATA    ( 0x3FF << 0 )        /* (ADC) Converted Data */
+/* -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- */
+/* -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- */
+/* -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- */
+/* -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- */
+/* -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- */
+/* -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- */
+/* -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
-// *****************************************************************************
-// *** Register offset in AT91S_SSC structure ***
-#define SSC_CR          ( 0) // Control Register
-#define SSC_CMR         ( 4) // Clock Mode Register
-#define SSC_RCMR        (16) // Receive Clock ModeRegister
-#define SSC_RFMR        (20) // Receive Frame Mode Register
-#define SSC_TCMR        (24) // Transmit Clock Mode Register
-#define SSC_TFMR        (28) // Transmit Frame Mode Register
-#define SSC_RHR         (32) // Receive Holding Register
-#define SSC_THR         (36) // Transmit Holding Register
-#define SSC_RSHR        (48) // Receive Sync Holding Register
-#define SSC_TSHR        (52) // Transmit Sync Holding Register
-#define SSC_RC0R        (56) // Receive Compare 0 Register
-#define SSC_RC1R        (60) // Receive Compare 1 Register
-#define SSC_SR          (64) // Status Register
-#define SSC_IER         (68) // Interrupt Enable Register
-#define SSC_IDR         (72) // Interrupt Disable Register
-#define SSC_IMR         (76) // Interrupt Mask Register
-#define SSC_RPR         (256) // Receive Pointer Register
-#define SSC_RCR         (260) // Receive Counter Register
-#define SSC_TPR         (264) // Transmit Pointer Register
-#define SSC_TCR         (268) // Transmit Counter Register
-#define SSC_RNPR        (272) // Receive Next Pointer Register
-#define SSC_RNCR        (276) // Receive Next Counter Register
-#define SSC_TNPR        (280) // Transmit Next Pointer Register
-#define SSC_TNCR        (284) // Transmit Next Counter Register
-#define SSC_PTCR        (288) // PDC Transfer Control Register
-#define SSC_PTSR        (292) // PDC Transfer Status Register
-// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
-#define AT91C_SSC_RXEN            (0x1 <<  0) // (SSC) Receive Enable
-#define AT91C_SSC_RXDIS           (0x1 <<  1) // (SSC) Receive Disable
-#define AT91C_SSC_TXEN            (0x1 <<  8) // (SSC) Transmit Enable
-#define AT91C_SSC_TXDIS           (0x1 <<  9) // (SSC) Transmit Disable
-#define AT91C_SSC_SWRST           (0x1 << 15) // (SSC) Software Reset
-// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
-#define AT91C_SSC_CKS             (0x3 <<  0) // (SSC) Receive/Transmit Clock Selection
-#define     AT91C_SSC_CKS_DIV                  (0x0) // (SSC) Divided Clock
-#define     AT91C_SSC_CKS_TK                   (0x1) // (SSC) TK Clock signal
-#define     AT91C_SSC_CKS_RK                   (0x2) // (SSC) RK pin
-#define AT91C_SSC_CKO             (0x7 <<  2) // (SSC) Receive/Transmit Clock Output Mode Selection
-#define     AT91C_SSC_CKO_NONE                 (0x0 <<  2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
-#define     AT91C_SSC_CKO_CONTINOUS            (0x1 <<  2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
-#define     AT91C_SSC_CKO_DATA_TX              (0x2 <<  2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
-#define AT91C_SSC_CKI             (0x1 <<  5) // (SSC) Receive/Transmit Clock Inversion
-#define AT91C_SSC_CKG             (0x3 <<  6) // (SSC) Receive/Transmit Clock Gating Selection
-#define     AT91C_SSC_CKG_NONE                 (0x0 <<  6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock
-#define     AT91C_SSC_CKG_LOW                  (0x1 <<  6) // (SSC) Receive/Transmit Clock enabled only if RF Low
-#define     AT91C_SSC_CKG_HIGH                 (0x2 <<  6) // (SSC) Receive/Transmit Clock enabled only if RF High
-#define AT91C_SSC_START           (0xF <<  8) // (SSC) Receive/Transmit Start Selection
-#define     AT91C_SSC_START_CONTINOUS            (0x0 <<  8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
-#define     AT91C_SSC_START_TX                   (0x1 <<  8) // (SSC) Transmit/Receive start
-#define     AT91C_SSC_START_LOW_RF               (0x2 <<  8) // (SSC) Detection of a low level on RF input
-#define     AT91C_SSC_START_HIGH_RF              (0x3 <<  8) // (SSC) Detection of a high level on RF input
-#define     AT91C_SSC_START_FALL_RF              (0x4 <<  8) // (SSC) Detection of a falling edge on RF input
-#define     AT91C_SSC_START_RISE_RF              (0x5 <<  8) // (SSC) Detection of a rising edge on RF input
-#define     AT91C_SSC_START_LEVEL_RF             (0x6 <<  8) // (SSC) Detection of any level change on RF input
-#define     AT91C_SSC_START_EDGE_RF              (0x7 <<  8) // (SSC) Detection of any edge on RF input
-#define     AT91C_SSC_START_0                    (0x8 <<  8) // (SSC) Compare 0
-#define AT91C_SSC_STOP            (0x1 << 12) // (SSC) Receive Stop Selection
-#define AT91C_SSC_STTOUT          (0x1 << 15) // (SSC) Receive/Transmit Start Output Selection
-#define AT91C_SSC_STTDLY          (0xFF << 16) // (SSC) Receive/Transmit Start Delay
-#define AT91C_SSC_PERIOD          (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
-// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
-#define AT91C_SSC_DATLEN          (0x1F <<  0) // (SSC) Data Length
-#define AT91C_SSC_LOOP            (0x1 <<  5) // (SSC) Loop Mode
-#define AT91C_SSC_MSBF            (0x1 <<  7) // (SSC) Most Significant Bit First
-#define AT91C_SSC_DATNB           (0xF <<  8) // (SSC) Data Number per Frame
-#define AT91C_SSC_FSLEN           (0xF << 16) // (SSC) Receive/Transmit Frame Sync length
-#define AT91C_SSC_FSOS            (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
-#define     AT91C_SSC_FSOS_NONE                 (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
-#define     AT91C_SSC_FSOS_NEGATIVE             (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
-#define     AT91C_SSC_FSOS_POSITIVE             (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
-#define     AT91C_SSC_FSOS_LOW                  (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
-#define     AT91C_SSC_FSOS_HIGH                 (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
-#define     AT91C_SSC_FSOS_TOGGLE               (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
-#define AT91C_SSC_FSEDGE          (0x1 << 24) // (SSC) Frame Sync Edge Detection
-// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
-// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
-#define AT91C_SSC_DATDEF          (0x1 <<  5) // (SSC) Data Default Value
-#define AT91C_SSC_FSDEN           (0x1 << 23) // (SSC) Frame Sync Data Enable
-// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
-#define AT91C_SSC_TXRDY           (0x1 <<  0) // (SSC) Transmit Ready
-#define AT91C_SSC_TXEMPTY         (0x1 <<  1) // (SSC) Transmit Empty
-#define AT91C_SSC_ENDTX           (0x1 <<  2) // (SSC) End Of Transmission
-#define AT91C_SSC_TXBUFE          (0x1 <<  3) // (SSC) Transmit Buffer Empty
-#define AT91C_SSC_RXRDY           (0x1 <<  4) // (SSC) Receive Ready
-#define AT91C_SSC_OVRUN           (0x1 <<  5) // (SSC) Receive Overrun
-#define AT91C_SSC_ENDRX           (0x1 <<  6) // (SSC) End of Reception
-#define AT91C_SSC_RXBUFF          (0x1 <<  7) // (SSC) Receive Buffer Full
-#define AT91C_SSC_CP0             (0x1 <<  8) // (SSC) Compare 0
-#define AT91C_SSC_CP1             (0x1 <<  9) // (SSC) Compare 1
-#define AT91C_SSC_TXSYN           (0x1 << 10) // (SSC) Transmit Sync
-#define AT91C_SSC_RXSYN           (0x1 << 11) // (SSC) Receive Sync
-#define AT91C_SSC_TXENA           (0x1 << 16) // (SSC) Transmit Enable
-#define AT91C_SSC_RXENA           (0x1 << 17) // (SSC) Receive Enable
-// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
-// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
-// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_SSC structure *** */
+#define SSC_CR                            ( 0 )          /* Control Register */
+#define SSC_CMR                           ( 4 )          /* Clock Mode Register */
+#define SSC_RCMR                          ( 16 )         /* Receive Clock ModeRegister */
+#define SSC_RFMR                          ( 20 )         /* Receive Frame Mode Register */
+#define SSC_TCMR                          ( 24 )         /* Transmit Clock Mode Register */
+#define SSC_TFMR                          ( 28 )         /* Transmit Frame Mode Register */
+#define SSC_RHR                           ( 32 )         /* Receive Holding Register */
+#define SSC_THR                           ( 36 )         /* Transmit Holding Register */
+#define SSC_RSHR                          ( 48 )         /* Receive Sync Holding Register */
+#define SSC_TSHR                          ( 52 )         /* Transmit Sync Holding Register */
+#define SSC_RC0R                          ( 56 )         /* Receive Compare 0 Register */
+#define SSC_RC1R                          ( 60 )         /* Receive Compare 1 Register */
+#define SSC_SR                            ( 64 )         /* Status Register */
+#define SSC_IER                           ( 68 )         /* Interrupt Enable Register */
+#define SSC_IDR                           ( 72 )         /* Interrupt Disable Register */
+#define SSC_IMR                           ( 76 )         /* Interrupt Mask Register */
+#define SSC_RPR                           ( 256 )        /* Receive Pointer Register */
+#define SSC_RCR                           ( 260 )        /* Receive Counter Register */
+#define SSC_TPR                           ( 264 )        /* Transmit Pointer Register */
+#define SSC_TCR                           ( 268 )        /* Transmit Counter Register */
+#define SSC_RNPR                          ( 272 )        /* Receive Next Pointer Register */
+#define SSC_RNCR                          ( 276 )        /* Receive Next Counter Register */
+#define SSC_TNPR                          ( 280 )        /* Transmit Next Pointer Register */
+#define SSC_TNCR                          ( 284 )        /* Transmit Next Counter Register */
+#define SSC_PTCR                          ( 288 )        /* PDC Transfer Control Register */
+#define SSC_PTSR                          ( 292 )        /* PDC Transfer Status Register */
+/* -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- */
+#define AT91C_SSC_RXEN                    ( 0x1 << 0 )   /* (SSC) Receive Enable */
+#define AT91C_SSC_RXDIS                   ( 0x1 << 1 )   /* (SSC) Receive Disable */
+#define AT91C_SSC_TXEN                    ( 0x1 << 8 )   /* (SSC) Transmit Enable */
+#define AT91C_SSC_TXDIS                   ( 0x1 << 9 )   /* (SSC) Transmit Disable */
+#define AT91C_SSC_SWRST                   ( 0x1 << 15 )  /* (SSC) Software Reset */
+/* -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- */
+#define AT91C_SSC_CKS                     ( 0x3 << 0 )   /* (SSC) Receive/Transmit Clock Selection */
+#define     AT91C_SSC_CKS_DIV             ( 0x0 )        /* (SSC) Divided Clock */
+#define     AT91C_SSC_CKS_TK              ( 0x1 )        /* (SSC) TK Clock signal */
+#define     AT91C_SSC_CKS_RK              ( 0x2 )        /* (SSC) RK pin */
+#define AT91C_SSC_CKO                     ( 0x7 << 2 )   /* (SSC) Receive/Transmit Clock Output Mode Selection */
+#define     AT91C_SSC_CKO_NONE            ( 0x0 << 2 )   /* (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only */
+#define     AT91C_SSC_CKO_CONTINUOUS      ( 0x1 << 2 )   /* (SSC) Continuous Receive/Transmit Clock RK pin: Output */
+#define     AT91C_SSC_CKO_DATA_TX         ( 0x2 << 2 )   /* (SSC) Receive/Transmit Clock only during data transfers RK pin: Output */
+#define AT91C_SSC_CKI                     ( 0x1 << 5 )   /* (SSC) Receive/Transmit Clock Inversion */
+#define AT91C_SSC_CKG                     ( 0x3 << 6 )   /* (SSC) Receive/Transmit Clock Gating Selection */
+#define     AT91C_SSC_CKG_NONE            ( 0x0 << 6 )   /* (SSC) Receive/Transmit Clock Gating: None, continuous clock */
+#define     AT91C_SSC_CKG_LOW             ( 0x1 << 6 )   /* (SSC) Receive/Transmit Clock enabled only if RF Low */
+#define     AT91C_SSC_CKG_HIGH            ( 0x2 << 6 )   /* (SSC) Receive/Transmit Clock enabled only if RF High */
+#define AT91C_SSC_START                   ( 0xF << 8 )   /* (SSC) Receive/Transmit Start Selection */
+#define     AT91C_SSC_START_CONTINUOUS    ( 0x0 << 8 )   /* (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */
+#define     AT91C_SSC_START_TX            ( 0x1 << 8 )   /* (SSC) Transmit/Receive start */
+#define     AT91C_SSC_START_LOW_RF        ( 0x2 << 8 )   /* (SSC) Detection of a low level on RF input */
+#define     AT91C_SSC_START_HIGH_RF       ( 0x3 << 8 )   /* (SSC) Detection of a high level on RF input */
+#define     AT91C_SSC_START_FALL_RF       ( 0x4 << 8 )   /* (SSC) Detection of a falling edge on RF input */
+#define     AT91C_SSC_START_RISE_RF       ( 0x5 << 8 )   /* (SSC) Detection of a rising edge on RF input */
+#define     AT91C_SSC_START_LEVEL_RF      ( 0x6 << 8 )   /* (SSC) Detection of any level change on RF input */
+#define     AT91C_SSC_START_EDGE_RF       ( 0x7 << 8 )   /* (SSC) Detection of any edge on RF input */
+#define     AT91C_SSC_START_0             ( 0x8 << 8 )   /* (SSC) Compare 0 */
+#define AT91C_SSC_STOP                    ( 0x1 << 12 )  /* (SSC) Receive Stop Selection */
+#define AT91C_SSC_STTOUT                  ( 0x1 << 15 )  /* (SSC) Receive/Transmit Start Output Selection */
+#define AT91C_SSC_STTDLY                  ( 0xFF << 16 ) /* (SSC) Receive/Transmit Start Delay */
+#define AT91C_SSC_PERIOD                  ( 0xFF << 24 ) /* (SSC) Receive/Transmit Period Divider Selection */
+/* -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- */
+#define AT91C_SSC_DATLEN                  ( 0x1F << 0 )  /* (SSC) Data Length */
+#define AT91C_SSC_LOOP                    ( 0x1 << 5 )   /* (SSC) Loop Mode */
+#define AT91C_SSC_MSBF                    ( 0x1 << 7 )   /* (SSC) Most Significant Bit First */
+#define AT91C_SSC_DATNB                   ( 0xF << 8 )   /* (SSC) Data Number per Frame */
+#define AT91C_SSC_FSLEN                   ( 0xF << 16 )  /* (SSC) Receive/Transmit Frame Sync length */
+#define AT91C_SSC_FSOS                    ( 0x7 << 20 )  /* (SSC) Receive/Transmit Frame Sync Output Selection */
+#define     AT91C_SSC_FSOS_NONE           ( 0x0 << 20 )  /* (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only */
+#define     AT91C_SSC_FSOS_NEGATIVE       ( 0x1 << 20 )  /* (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse */
+#define     AT91C_SSC_FSOS_POSITIVE       ( 0x2 << 20 )  /* (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse */
+#define     AT91C_SSC_FSOS_LOW            ( 0x3 << 20 )  /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer */
+#define     AT91C_SSC_FSOS_HIGH           ( 0x4 << 20 )  /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer */
+#define     AT91C_SSC_FSOS_TOGGLE         ( 0x5 << 20 )  /* (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer */
+#define AT91C_SSC_FSEDGE                  ( 0x1 << 24 )  /* (SSC) Frame Sync Edge Detection */
+/* -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- */
+/* -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- */
+#define AT91C_SSC_DATDEF                  ( 0x1 << 5 )  /* (SSC) Data Default Value */
+#define AT91C_SSC_FSDEN                   ( 0x1 << 23 ) /* (SSC) Frame Sync Data Enable */
+/* -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- */
+#define AT91C_SSC_TXRDY                   ( 0x1 << 0 )  /* (SSC) Transmit Ready */
+#define AT91C_SSC_TXEMPTY                 ( 0x1 << 1 )  /* (SSC) Transmit Empty */
+#define AT91C_SSC_ENDTX                   ( 0x1 << 2 )  /* (SSC) End Of Transmission */
+#define AT91C_SSC_TXBUFE                  ( 0x1 << 3 )  /* (SSC) Transmit Buffer Empty */
+#define AT91C_SSC_RXRDY                   ( 0x1 << 4 )  /* (SSC) Receive Ready */
+#define AT91C_SSC_OVRUN                   ( 0x1 << 5 )  /* (SSC) Receive Overrun */
+#define AT91C_SSC_ENDRX                   ( 0x1 << 6 )  /* (SSC) End of Reception */
+#define AT91C_SSC_RXBUFF                  ( 0x1 << 7 )  /* (SSC) Receive Buffer Full */
+#define AT91C_SSC_CP0                     ( 0x1 << 8 )  /* (SSC) Compare 0 */
+#define AT91C_SSC_CP1                     ( 0x1 << 9 )  /* (SSC) Compare 1 */
+#define AT91C_SSC_TXSYN                   ( 0x1 << 10 ) /* (SSC) Transmit Sync */
+#define AT91C_SSC_RXSYN                   ( 0x1 << 11 ) /* (SSC) Receive Sync */
+#define AT91C_SSC_TXENA                   ( 0x1 << 16 ) /* (SSC) Transmit Enable */
+#define AT91C_SSC_RXENA                   ( 0x1 << 17 ) /* (SSC) Receive Enable */
+/* -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- */
+/* -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- */
+/* -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Usart
-// *****************************************************************************
-// *** Register offset in AT91S_USART structure ***
-#define US_CR           ( 0) // Control Register
-#define US_MR           ( 4) // Mode Register
-#define US_IER          ( 8) // Interrupt Enable Register
-#define US_IDR          (12) // Interrupt Disable Register
-#define US_IMR          (16) // Interrupt Mask Register
-#define US_CSR          (20) // Channel Status Register
-#define US_RHR          (24) // Receiver Holding Register
-#define US_THR          (28) // Transmitter Holding Register
-#define US_BRGR         (32) // Baud Rate Generator Register
-#define US_RTOR         (36) // Receiver Time-out Register
-#define US_TTGR         (40) // Transmitter Time-guard Register
-#define US_FIDI         (64) // FI_DI_Ratio Register
-#define US_NER          (68) // Nb Errors Register
-#define US_XXR          (72) // XON_XOFF Register
-#define US_IF           (76) // IRDA_FILTER Register
-#define US_RPR          (256) // Receive Pointer Register
-#define US_RCR          (260) // Receive Counter Register
-#define US_TPR          (264) // Transmit Pointer Register
-#define US_TCR          (268) // Transmit Counter Register
-#define US_RNPR         (272) // Receive Next Pointer Register
-#define US_RNCR         (276) // Receive Next Counter Register
-#define US_TNPR         (280) // Transmit Next Pointer Register
-#define US_TNCR         (284) // Transmit Next Counter Register
-#define US_PTCR         (288) // PDC Transfer Control Register
-#define US_PTSR         (292) // PDC Transfer Status Register
-// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
-#define AT91C_US_RSTSTA           (0x1 <<  8) // (USART) Reset Status Bits
-#define AT91C_US_STTBRK           (0x1 <<  9) // (USART) Start Break
-#define AT91C_US_STPBRK           (0x1 << 10) // (USART) Stop Break
-#define AT91C_US_STTTO            (0x1 << 11) // (USART) Start Time-out
-#define AT91C_US_SENDA            (0x1 << 12) // (USART) Send Address
-#define AT91C_US_RSTIT            (0x1 << 13) // (USART) Reset Iterations
-#define AT91C_US_RSTNACK          (0x1 << 14) // (USART) Reset Non Acknowledge
-#define AT91C_US_RETTO            (0x1 << 15) // (USART) Rearm Time-out
-#define AT91C_US_DTREN            (0x1 << 16) // (USART) Data Terminal ready Enable
-#define AT91C_US_DTRDIS           (0x1 << 17) // (USART) Data Terminal ready Disable
-#define AT91C_US_RTSEN            (0x1 << 18) // (USART) Request to Send enable
-#define AT91C_US_RTSDIS           (0x1 << 19) // (USART) Request to Send Disable
-// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
-#define AT91C_US_USMODE           (0xF <<  0) // (USART) Usart mode
-#define     AT91C_US_USMODE_NORMAL               (0x0) // (USART) Normal
-#define     AT91C_US_USMODE_RS485                (0x1) // (USART) RS485
-#define     AT91C_US_USMODE_HWHSH                (0x2) // (USART) Hardware Handshaking
-#define     AT91C_US_USMODE_MODEM                (0x3) // (USART) Modem
-#define     AT91C_US_USMODE_ISO7816_0            (0x4) // (USART) ISO7816 protocol: T = 0
-#define     AT91C_US_USMODE_ISO7816_1            (0x6) // (USART) ISO7816 protocol: T = 1
-#define     AT91C_US_USMODE_IRDA                 (0x8) // (USART) IrDA
-#define     AT91C_US_USMODE_SWHSH                (0xC) // (USART) Software Handshaking
-#define AT91C_US_CLKS             (0x3 <<  4) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define     AT91C_US_CLKS_CLOCK                (0x0 <<  4) // (USART) Clock
-#define     AT91C_US_CLKS_FDIV1                (0x1 <<  4) // (USART) fdiv1
-#define     AT91C_US_CLKS_SLOW                 (0x2 <<  4) // (USART) slow_clock (ARM)
-#define     AT91C_US_CLKS_EXT                  (0x3 <<  4) // (USART) External (SCK)
-#define AT91C_US_CHRL             (0x3 <<  6) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define     AT91C_US_CHRL_5_BITS               (0x0 <<  6) // (USART) Character Length: 5 bits
-#define     AT91C_US_CHRL_6_BITS               (0x1 <<  6) // (USART) Character Length: 6 bits
-#define     AT91C_US_CHRL_7_BITS               (0x2 <<  6) // (USART) Character Length: 7 bits
-#define     AT91C_US_CHRL_8_BITS               (0x3 <<  6) // (USART) Character Length: 8 bits
-#define AT91C_US_SYNC             (0x1 <<  8) // (USART) Synchronous Mode Select
-#define AT91C_US_NBSTOP           (0x3 << 12) // (USART) Number of Stop bits
-#define     AT91C_US_NBSTOP_1_BIT                (0x0 << 12) // (USART) 1 stop bit
-#define     AT91C_US_NBSTOP_15_BIT               (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
-#define     AT91C_US_NBSTOP_2_BIT                (0x2 << 12) // (USART) 2 stop bits
-#define AT91C_US_MSBF             (0x1 << 16) // (USART) Bit Order
-#define AT91C_US_MODE9            (0x1 << 17) // (USART) 9-bit Character length
-#define AT91C_US_CKLO             (0x1 << 18) // (USART) Clock Output Select
-#define AT91C_US_OVER             (0x1 << 19) // (USART) Over Sampling Mode
-#define AT91C_US_INACK            (0x1 << 20) // (USART) Inhibit Non Acknowledge
-#define AT91C_US_DSNACK           (0x1 << 21) // (USART) Disable Successive NACK
-#define AT91C_US_MAX_ITER         (0x1 << 24) // (USART) Number of Repetitions
-#define AT91C_US_FILTER           (0x1 << 28) // (USART) Receive Line Filter
-// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
-#define AT91C_US_RXBRK            (0x1 <<  2) // (USART) Break Received/End of Break
-#define AT91C_US_TIMEOUT          (0x1 <<  8) // (USART) Receiver Time-out
-#define AT91C_US_ITERATION        (0x1 << 10) // (USART) Max number of Repetitions Reached
-#define AT91C_US_NACK             (0x1 << 13) // (USART) Non Acknowledge
-#define AT91C_US_RIIC             (0x1 << 16) // (USART) Ring INdicator Input Change Flag
-#define AT91C_US_DSRIC            (0x1 << 17) // (USART) Data Set Ready Input Change Flag
-#define AT91C_US_DCDIC            (0x1 << 18) // (USART) Data Carrier Flag
-#define AT91C_US_CTSIC            (0x1 << 19) // (USART) Clear To Send Input Change Flag
-// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
-// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
-// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
-#define AT91C_US_RI               (0x1 << 20) // (USART) Image of RI Input
-#define AT91C_US_DSR              (0x1 << 21) // (USART) Image of DSR Input
-#define AT91C_US_DCD              (0x1 << 22) // (USART) Image of DCD Input
-#define AT91C_US_CTS              (0x1 << 23) // (USART) Image of CTS Input
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Usart */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_USART structure *** */
+#define US_CR                            ( 0 )         /* Control Register */
+#define US_MR                            ( 4 )         /* Mode Register */
+#define US_IER                           ( 8 )         /* Interrupt Enable Register */
+#define US_IDR                           ( 12 )        /* Interrupt Disable Register */
+#define US_IMR                           ( 16 )        /* Interrupt Mask Register */
+#define US_CSR                           ( 20 )        /* Channel Status Register */
+#define US_RHR                           ( 24 )        /* Receiver Holding Register */
+#define US_THR                           ( 28 )        /* Transmitter Holding Register */
+#define US_BRGR                          ( 32 )        /* Baud Rate Generator Register */
+#define US_RTOR                          ( 36 )        /* Receiver Time-out Register */
+#define US_TTGR                          ( 40 )        /* Transmitter Time-guard Register */
+#define US_FIDI                          ( 64 )        /* FI_DI_Ratio Register */
+#define US_NER                           ( 68 )        /* Nb Errors Register */
+#define US_XXR                           ( 72 )        /* XON_XOFF Register */
+#define US_IF                            ( 76 )        /* IRDA_FILTER Register */
+#define US_RPR                           ( 256 )       /* Receive Pointer Register */
+#define US_RCR                           ( 260 )       /* Receive Counter Register */
+#define US_TPR                           ( 264 )       /* Transmit Pointer Register */
+#define US_TCR                           ( 268 )       /* Transmit Counter Register */
+#define US_RNPR                          ( 272 )       /* Receive Next Pointer Register */
+#define US_RNCR                          ( 276 )       /* Receive Next Counter Register */
+#define US_TNPR                          ( 280 )       /* Transmit Next Pointer Register */
+#define US_TNCR                          ( 284 )       /* Transmit Next Counter Register */
+#define US_PTCR                          ( 288 )       /* PDC Transfer Control Register */
+#define US_PTSR                          ( 292 )       /* PDC Transfer Status Register */
+/* -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- */
+#define AT91C_US_RSTSTA                  ( 0x1 << 8 )  /* (USART) Reset Status Bits */
+#define AT91C_US_STTBRK                  ( 0x1 << 9 )  /* (USART) Start Break */
+#define AT91C_US_STPBRK                  ( 0x1 << 10 ) /* (USART) Stop Break */
+#define AT91C_US_STTTO                   ( 0x1 << 11 ) /* (USART) Start Time-out */
+#define AT91C_US_SENDA                   ( 0x1 << 12 ) /* (USART) Send Address */
+#define AT91C_US_RSTIT                   ( 0x1 << 13 ) /* (USART) Reset Iterations */
+#define AT91C_US_RSTNACK                 ( 0x1 << 14 ) /* (USART) Reset Non Acknowledge */
+#define AT91C_US_RETTO                   ( 0x1 << 15 ) /* (USART) Rearm Time-out */
+#define AT91C_US_DTREN                   ( 0x1 << 16 ) /* (USART) Data Terminal ready Enable */
+#define AT91C_US_DTRDIS                  ( 0x1 << 17 ) /* (USART) Data Terminal ready Disable */
+#define AT91C_US_RTSEN                   ( 0x1 << 18 ) /* (USART) Request to Send enable */
+#define AT91C_US_RTSDIS                  ( 0x1 << 19 ) /* (USART) Request to Send Disable */
+/* -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- */
+#define AT91C_US_USMODE                  ( 0xF << 0 )  /* (USART) Usart mode */
+#define     AT91C_US_USMODE_NORMAL       ( 0x0 )       /* (USART) Normal */
+#define     AT91C_US_USMODE_RS485        ( 0x1 )       /* (USART) RS485 */
+#define     AT91C_US_USMODE_HWHSH        ( 0x2 )       /* (USART) Hardware Handshaking */
+#define     AT91C_US_USMODE_MODEM        ( 0x3 )       /* (USART) Modem */
+#define     AT91C_US_USMODE_ISO7816_0    ( 0x4 )       /* (USART) ISO7816 protocol: T = 0 */
+#define     AT91C_US_USMODE_ISO7816_1    ( 0x6 )       /* (USART) ISO7816 protocol: T = 1 */
+#define     AT91C_US_USMODE_IRDA         ( 0x8 )       /* (USART) IrDA */
+#define     AT91C_US_USMODE_SWHSH        ( 0xC )       /* (USART) Software Handshaking */
+#define AT91C_US_CLKS                    ( 0x3 << 4 )  /* (USART) Clock Selection (Baud Rate generator Input Clock */
+#define     AT91C_US_CLKS_CLOCK          ( 0x0 << 4 )  /* (USART) Clock */
+#define     AT91C_US_CLKS_FDIV1          ( 0x1 << 4 )  /* (USART) fdiv1 */
+#define     AT91C_US_CLKS_SLOW           ( 0x2 << 4 )  /* (USART) slow_clock (ARM) */
+#define     AT91C_US_CLKS_EXT            ( 0x3 << 4 )  /* (USART) External (SCK) */
+#define AT91C_US_CHRL                    ( 0x3 << 6 )  /* (USART) Clock Selection (Baud Rate generator Input Clock */
+#define     AT91C_US_CHRL_5_BITS         ( 0x0 << 6 )  /* (USART) Character Length: 5 bits */
+#define     AT91C_US_CHRL_6_BITS         ( 0x1 << 6 )  /* (USART) Character Length: 6 bits */
+#define     AT91C_US_CHRL_7_BITS         ( 0x2 << 6 )  /* (USART) Character Length: 7 bits */
+#define     AT91C_US_CHRL_8_BITS         ( 0x3 << 6 )  /* (USART) Character Length: 8 bits */
+#define AT91C_US_SYNC                    ( 0x1 << 8 )  /* (USART) Synchronous Mode Select */
+#define AT91C_US_NBSTOP                  ( 0x3 << 12 ) /* (USART) Number of Stop bits */
+#define     AT91C_US_NBSTOP_1_BIT        ( 0x0 << 12 ) /* (USART) 1 stop bit */
+#define     AT91C_US_NBSTOP_15_BIT       ( 0x1 << 12 ) /* (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits */
+#define     AT91C_US_NBSTOP_2_BIT        ( 0x2 << 12 ) /* (USART) 2 stop bits */
+#define AT91C_US_MSBF                    ( 0x1 << 16 ) /* (USART) Bit Order */
+#define AT91C_US_MODE9                   ( 0x1 << 17 ) /* (USART) 9-bit Character length */
+#define AT91C_US_CKLO                    ( 0x1 << 18 ) /* (USART) Clock Output Select */
+#define AT91C_US_OVER                    ( 0x1 << 19 ) /* (USART) Over Sampling Mode */
+#define AT91C_US_INACK                   ( 0x1 << 20 ) /* (USART) Inhibit Non Acknowledge */
+#define AT91C_US_DSNACK                  ( 0x1 << 21 ) /* (USART) Disable Successive NACK */
+#define AT91C_US_MAX_ITER                ( 0x1 << 24 ) /* (USART) Number of Repetitions */
+#define AT91C_US_FILTER                  ( 0x1 << 28 ) /* (USART) Receive Line Filter */
+/* -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- */
+#define AT91C_US_RXBRK                   ( 0x1 << 2 )  /* (USART) Break Received/End of Break */
+#define AT91C_US_TIMEOUT                 ( 0x1 << 8 )  /* (USART) Receiver Time-out */
+#define AT91C_US_ITERATION               ( 0x1 << 10 ) /* (USART) Max number of Repetitions Reached */
+#define AT91C_US_NACK                    ( 0x1 << 13 ) /* (USART) Non Acknowledge */
+#define AT91C_US_RIIC                    ( 0x1 << 16 ) /* (USART) Ring INdicator Input Change Flag */
+#define AT91C_US_DSRIC                   ( 0x1 << 17 ) /* (USART) Data Set Ready Input Change Flag */
+#define AT91C_US_DCDIC                   ( 0x1 << 18 ) /* (USART) Data Carrier Flag */
+#define AT91C_US_CTSIC                   ( 0x1 << 19 ) /* (USART) Clear To Send Input Change Flag */
+/* -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- */
+/* -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- */
+/* -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- */
+#define AT91C_US_RI     ( 0x1 << 20 )         /* (USART) Image of RI Input */
+#define AT91C_US_DSR    ( 0x1 << 21 )         /* (USART) Image of DSR Input */
+#define AT91C_US_DCD    ( 0x1 << 22 )         /* (USART) Image of DCD Input */
+#define AT91C_US_CTS    ( 0x1 << 23 )         /* (USART) Image of CTS Input */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Two-wire Interface
-// *****************************************************************************
-// *** Register offset in AT91S_TWI structure ***
-#define TWI_CR          ( 0) // Control Register
-#define TWI_MMR         ( 4) // Master Mode Register
-#define TWI_SMR         ( 8) // Slave Mode Register
-#define TWI_IADR        (12) // Internal Address Register
-#define TWI_CWGR        (16) // Clock Waveform Generator Register
-#define TWI_SR          (32) // Status Register
-#define TWI_IER         (36) // Interrupt Enable Register
-#define TWI_IDR         (40) // Interrupt Disable Register
-#define TWI_IMR         (44) // Interrupt Mask Register
-#define TWI_RHR         (48) // Receive Holding Register
-#define TWI_THR         (52) // Transmit Holding Register
-// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
-#define AT91C_TWI_START           (0x1 <<  0) // (TWI) Send a START Condition
-#define AT91C_TWI_STOP            (0x1 <<  1) // (TWI) Send a STOP Condition
-#define AT91C_TWI_MSEN            (0x1 <<  2) // (TWI) TWI Master Transfer Enabled
-#define AT91C_TWI_MSDIS           (0x1 <<  3) // (TWI) TWI Master Transfer Disabled
-#define AT91C_TWI_SVEN            (0x1 <<  4) // (TWI) TWI Slave Transfer Enabled
-#define AT91C_TWI_SVDIS           (0x1 <<  5) // (TWI) TWI Slave Transfer Disabled
-#define AT91C_TWI_SWRST           (0x1 <<  7) // (TWI) Software Reset
-// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
-#define AT91C_TWI_IADRSZ          (0x3 <<  8) // (TWI) Internal Device Address Size
-#define     AT91C_TWI_IADRSZ_NO                   (0x0 <<  8) // (TWI) No internal device address
-#define     AT91C_TWI_IADRSZ_1_BYTE               (0x1 <<  8) // (TWI) One-byte internal device address
-#define     AT91C_TWI_IADRSZ_2_BYTE               (0x2 <<  8) // (TWI) Two-byte internal device address
-#define     AT91C_TWI_IADRSZ_3_BYTE               (0x3 <<  8) // (TWI) Three-byte internal device address
-#define AT91C_TWI_MREAD           (0x1 << 12) // (TWI) Master Read Direction
-#define AT91C_TWI_DADR            (0x7F << 16) // (TWI) Device Address
-// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register --------
-#define AT91C_TWI_SADR            (0x7F << 16) // (TWI) Slave Device Address
-// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
-#define AT91C_TWI_CLDIV           (0xFF <<  0) // (TWI) Clock Low Divider
-#define AT91C_TWI_CHDIV           (0xFF <<  8) // (TWI) Clock High Divider
-#define AT91C_TWI_CKDIV           (0x7 << 16) // (TWI) Clock Divider
-// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
-#define AT91C_TWI_TXCOMP          (0x1 <<  0) // (TWI) Transmission Completed
-#define AT91C_TWI_RXRDY           (0x1 <<  1) // (TWI) Receive holding register ReaDY
-#define AT91C_TWI_TXRDY           (0x1 <<  2) // (TWI) Transmit holding register ReaDY
-#define AT91C_TWI_SVREAD          (0x1 <<  3) // (TWI) Slave Read
-#define AT91C_TWI_SVACC           (0x1 <<  4) // (TWI) Slave Access
-#define AT91C_TWI_GCACC           (0x1 <<  5) // (TWI) General Call Access
-#define AT91C_TWI_OVRE            (0x1 <<  6) // (TWI) Overrun Error
-#define AT91C_TWI_UNRE            (0x1 <<  7) // (TWI) Underrun Error
-#define AT91C_TWI_NACK            (0x1 <<  8) // (TWI) Not Acknowledged
-#define AT91C_TWI_ARBLST          (0x1 <<  9) // (TWI) Arbitration Lost
-// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
-// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
-// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Two-wire Interface */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_TWI structure *** */
+#define TWI_CR                         ( 0 )          /* Control Register */
+#define TWI_MMR                        ( 4 )          /* Master Mode Register */
+#define TWI_SMR                        ( 8 )          /* Slave Mode Register */
+#define TWI_IADR                       ( 12 )         /* Internal Address Register */
+#define TWI_CWGR                       ( 16 )         /* Clock Waveform Generator Register */
+#define TWI_SR                         ( 32 )         /* Status Register */
+#define TWI_IER                        ( 36 )         /* Interrupt Enable Register */
+#define TWI_IDR                        ( 40 )         /* Interrupt Disable Register */
+#define TWI_IMR                        ( 44 )         /* Interrupt Mask Register */
+#define TWI_RHR                        ( 48 )         /* Receive Holding Register */
+#define TWI_THR                        ( 52 )         /* Transmit Holding Register */
+/* -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- */
+#define AT91C_TWI_START                ( 0x1 << 0 )   /* (TWI) Send a START Condition */
+#define AT91C_TWI_STOP                 ( 0x1 << 1 )   /* (TWI) Send a STOP Condition */
+#define AT91C_TWI_MSEN                 ( 0x1 << 2 )   /* (TWI) TWI Master Transfer Enabled */
+#define AT91C_TWI_MSDIS                ( 0x1 << 3 )   /* (TWI) TWI Master Transfer Disabled */
+#define AT91C_TWI_SVEN                 ( 0x1 << 4 )   /* (TWI) TWI Slave Transfer Enabled */
+#define AT91C_TWI_SVDIS                ( 0x1 << 5 )   /* (TWI) TWI Slave Transfer Disabled */
+#define AT91C_TWI_SWRST                ( 0x1 << 7 )   /* (TWI) Software Reset */
+/* -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- */
+#define AT91C_TWI_IADRSZ               ( 0x3 << 8 )   /* (TWI) Internal Device Address Size */
+#define     AT91C_TWI_IADRSZ_NO        ( 0x0 << 8 )   /* (TWI) No internal device address */
+#define     AT91C_TWI_IADRSZ_1_BYTE    ( 0x1 << 8 )   /* (TWI) One-byte internal device address */
+#define     AT91C_TWI_IADRSZ_2_BYTE    ( 0x2 << 8 )   /* (TWI) Two-byte internal device address */
+#define     AT91C_TWI_IADRSZ_3_BYTE    ( 0x3 << 8 )   /* (TWI) Three-byte internal device address */
+#define AT91C_TWI_MREAD                ( 0x1 << 12 )  /* (TWI) Master Read Direction */
+#define AT91C_TWI_DADR                 ( 0x7F << 16 ) /* (TWI) Device Address */
+/* -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- */
+#define AT91C_TWI_SADR                 ( 0x7F << 16 ) /* (TWI) Slave Device Address */
+/* -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- */
+#define AT91C_TWI_CLDIV                ( 0xFF << 0 )  /* (TWI) Clock Low Divider */
+#define AT91C_TWI_CHDIV                ( 0xFF << 8 )  /* (TWI) Clock High Divider */
+#define AT91C_TWI_CKDIV                ( 0x7 << 16 )  /* (TWI) Clock Divider */
+/* -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- */
+#define AT91C_TWI_TXCOMP               ( 0x1 << 0 )   /* (TWI) Transmission Completed */
+#define AT91C_TWI_RXRDY                ( 0x1 << 1 )   /* (TWI) Receive holding register ReaDY */
+#define AT91C_TWI_TXRDY                ( 0x1 << 2 )   /* (TWI) Transmit holding register ReaDY */
+#define AT91C_TWI_SVREAD               ( 0x1 << 3 )   /* (TWI) Slave Read */
+#define AT91C_TWI_SVACC                ( 0x1 << 4 )   /* (TWI) Slave Access */
+#define AT91C_TWI_GCACC                ( 0x1 << 5 )   /* (TWI) General Call Access */
+#define AT91C_TWI_OVRE                 ( 0x1 << 6 )   /* (TWI) Overrun Error */
+#define AT91C_TWI_UNRE                 ( 0x1 << 7 )   /* (TWI) Underrun Error */
+#define AT91C_TWI_NACK                 ( 0x1 << 8 )   /* (TWI) Not Acknowledged */
+#define AT91C_TWI_ARBLST               ( 0x1 << 9 )   /* (TWI) Arbitration Lost */
+/* -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- */
+/* -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- */
+/* -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
-// *****************************************************************************
-// *** Register offset in AT91S_TC structure ***
-#define TC_CCR          ( 0) // Channel Control Register
-#define TC_CMR          ( 4) // Channel Mode Register (Capture Mode / Waveform Mode)
-#define TC_CV           (16) // Counter Value
-#define TC_RA           (20) // Register A
-#define TC_RB           (24) // Register B
-#define TC_RC           (28) // Register C
-#define TC_SR           (32) // Status Register
-#define TC_IER          (36) // Interrupt Enable Register
-#define TC_IDR          (40) // Interrupt Disable Register
-#define TC_IMR          (44) // Interrupt Mask Register
-// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
-#define AT91C_TC_CLKEN            (0x1 <<  0) // (TC) Counter Clock Enable Command
-#define AT91C_TC_CLKDIS           (0x1 <<  1) // (TC) Counter Clock Disable Command
-#define AT91C_TC_SWTRG            (0x1 <<  2) // (TC) Software Trigger Command
-// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
-#define AT91C_TC_CLKS             (0x7 <<  0) // (TC) Clock Selection
-#define     AT91C_TC_CLKS_TIMER_DIV1_CLOCK     (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
-#define     AT91C_TC_CLKS_TIMER_DIV2_CLOCK     (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
-#define     AT91C_TC_CLKS_TIMER_DIV3_CLOCK     (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
-#define     AT91C_TC_CLKS_TIMER_DIV4_CLOCK     (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
-#define     AT91C_TC_CLKS_TIMER_DIV5_CLOCK     (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
-#define     AT91C_TC_CLKS_XC0                  (0x5) // (TC) Clock selected: XC0
-#define     AT91C_TC_CLKS_XC1                  (0x6) // (TC) Clock selected: XC1
-#define     AT91C_TC_CLKS_XC2                  (0x7) // (TC) Clock selected: XC2
-#define AT91C_TC_CLKI             (0x1 <<  3) // (TC) Clock Invert
-#define AT91C_TC_BURST            (0x3 <<  4) // (TC) Burst Signal Selection
-#define     AT91C_TC_BURST_NONE                 (0x0 <<  4) // (TC) The clock is not gated by an external signal
-#define     AT91C_TC_BURST_XC0                  (0x1 <<  4) // (TC) XC0 is ANDed with the selected clock
-#define     AT91C_TC_BURST_XC1                  (0x2 <<  4) // (TC) XC1 is ANDed with the selected clock
-#define     AT91C_TC_BURST_XC2                  (0x3 <<  4) // (TC) XC2 is ANDed with the selected clock
-#define AT91C_TC_CPCSTOP          (0x1 <<  6) // (TC) Counter Clock Stopped with RC Compare
-#define AT91C_TC_LDBSTOP          (0x1 <<  6) // (TC) Counter Clock Stopped with RB Loading
-#define AT91C_TC_LDBDIS           (0x1 <<  7) // (TC) Counter Clock Disabled with RB Loading
-#define AT91C_TC_CPCDIS           (0x1 <<  7) // (TC) Counter Clock Disable with RC Compare
-#define AT91C_TC_ETRGEDG          (0x3 <<  8) // (TC) External Trigger Edge Selection
-#define     AT91C_TC_ETRGEDG_NONE                 (0x0 <<  8) // (TC) Edge: None
-#define     AT91C_TC_ETRGEDG_RISING               (0x1 <<  8) // (TC) Edge: rising edge
-#define     AT91C_TC_ETRGEDG_FALLING              (0x2 <<  8) // (TC) Edge: falling edge
-#define     AT91C_TC_ETRGEDG_BOTH                 (0x3 <<  8) // (TC) Edge: each edge
-#define AT91C_TC_EEVTEDG          (0x3 <<  8) // (TC) External Event Edge Selection
-#define     AT91C_TC_EEVTEDG_NONE                 (0x0 <<  8) // (TC) Edge: None
-#define     AT91C_TC_EEVTEDG_RISING               (0x1 <<  8) // (TC) Edge: rising edge
-#define     AT91C_TC_EEVTEDG_FALLING              (0x2 <<  8) // (TC) Edge: falling edge
-#define     AT91C_TC_EEVTEDG_BOTH                 (0x3 <<  8) // (TC) Edge: each edge
-#define AT91C_TC_ABETRG           (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
-#define AT91C_TC_EEVT             (0x3 << 10) // (TC) External Event  Selection
-#define     AT91C_TC_EEVT_NONE                 (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
-#define     AT91C_TC_EEVT_RISING               (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
-#define     AT91C_TC_EEVT_FALLING              (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
-#define     AT91C_TC_EEVT_BOTH                 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
-#define AT91C_TC_ENETRG           (0x1 << 12) // (TC) External Event Trigger enable
-#define AT91C_TC_WAVESEL          (0x3 << 13) // (TC) Waveform  Selection
-#define     AT91C_TC_WAVESEL_UP                   (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
-#define     AT91C_TC_WAVESEL_UPDOWN               (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
-#define     AT91C_TC_WAVESEL_UP_AUTO              (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
-#define     AT91C_TC_WAVESEL_UPDOWN_AUTO          (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
-#define AT91C_TC_CPCTRG           (0x1 << 14) // (TC) RC Compare Trigger Enable
-#define AT91C_TC_WAVE             (0x1 << 15) // (TC)
-#define AT91C_TC_LDRA             (0x3 << 16) // (TC) RA Loading Selection
-#define     AT91C_TC_LDRA_NONE                 (0x0 << 16) // (TC) Edge: None
-#define     AT91C_TC_LDRA_RISING               (0x1 << 16) // (TC) Edge: rising edge of TIOA
-#define     AT91C_TC_LDRA_FALLING              (0x2 << 16) // (TC) Edge: falling edge of TIOA
-#define     AT91C_TC_LDRA_BOTH                 (0x3 << 16) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_ACPA             (0x3 << 16) // (TC) RA Compare Effect on TIOA
-#define     AT91C_TC_ACPA_NONE                 (0x0 << 16) // (TC) Effect: none
-#define     AT91C_TC_ACPA_SET                  (0x1 << 16) // (TC) Effect: set
-#define     AT91C_TC_ACPA_CLEAR                (0x2 << 16) // (TC) Effect: clear
-#define     AT91C_TC_ACPA_TOGGLE               (0x3 << 16) // (TC) Effect: toggle
-#define AT91C_TC_LDRB             (0x3 << 18) // (TC) RB Loading Selection
-#define     AT91C_TC_LDRB_NONE                 (0x0 << 18) // (TC) Edge: None
-#define     AT91C_TC_LDRB_RISING               (0x1 << 18) // (TC) Edge: rising edge of TIOA
-#define     AT91C_TC_LDRB_FALLING              (0x2 << 18) // (TC) Edge: falling edge of TIOA
-#define     AT91C_TC_LDRB_BOTH                 (0x3 << 18) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_ACPC             (0x3 << 18) // (TC) RC Compare Effect on TIOA
-#define     AT91C_TC_ACPC_NONE                 (0x0 << 18) // (TC) Effect: none
-#define     AT91C_TC_ACPC_SET                  (0x1 << 18) // (TC) Effect: set
-#define     AT91C_TC_ACPC_CLEAR                (0x2 << 18) // (TC) Effect: clear
-#define     AT91C_TC_ACPC_TOGGLE               (0x3 << 18) // (TC) Effect: toggle
-#define AT91C_TC_AEEVT            (0x3 << 20) // (TC) External Event Effect on TIOA
-#define     AT91C_TC_AEEVT_NONE                 (0x0 << 20) // (TC) Effect: none
-#define     AT91C_TC_AEEVT_SET                  (0x1 << 20) // (TC) Effect: set
-#define     AT91C_TC_AEEVT_CLEAR                (0x2 << 20) // (TC) Effect: clear
-#define     AT91C_TC_AEEVT_TOGGLE               (0x3 << 20) // (TC) Effect: toggle
-#define AT91C_TC_ASWTRG           (0x3 << 22) // (TC) Software Trigger Effect on TIOA
-#define     AT91C_TC_ASWTRG_NONE                 (0x0 << 22) // (TC) Effect: none
-#define     AT91C_TC_ASWTRG_SET                  (0x1 << 22) // (TC) Effect: set
-#define     AT91C_TC_ASWTRG_CLEAR                (0x2 << 22) // (TC) Effect: clear
-#define     AT91C_TC_ASWTRG_TOGGLE               (0x3 << 22) // (TC) Effect: toggle
-#define AT91C_TC_BCPB             (0x3 << 24) // (TC) RB Compare Effect on TIOB
-#define     AT91C_TC_BCPB_NONE                 (0x0 << 24) // (TC) Effect: none
-#define     AT91C_TC_BCPB_SET                  (0x1 << 24) // (TC) Effect: set
-#define     AT91C_TC_BCPB_CLEAR                (0x2 << 24) // (TC) Effect: clear
-#define     AT91C_TC_BCPB_TOGGLE               (0x3 << 24) // (TC) Effect: toggle
-#define AT91C_TC_BCPC             (0x3 << 26) // (TC) RC Compare Effect on TIOB
-#define     AT91C_TC_BCPC_NONE                 (0x0 << 26) // (TC) Effect: none
-#define     AT91C_TC_BCPC_SET                  (0x1 << 26) // (TC) Effect: set
-#define     AT91C_TC_BCPC_CLEAR                (0x2 << 26) // (TC) Effect: clear
-#define     AT91C_TC_BCPC_TOGGLE               (0x3 << 26) // (TC) Effect: toggle
-#define AT91C_TC_BEEVT            (0x3 << 28) // (TC) External Event Effect on TIOB
-#define     AT91C_TC_BEEVT_NONE                 (0x0 << 28) // (TC) Effect: none
-#define     AT91C_TC_BEEVT_SET                  (0x1 << 28) // (TC) Effect: set
-#define     AT91C_TC_BEEVT_CLEAR                (0x2 << 28) // (TC) Effect: clear
-#define     AT91C_TC_BEEVT_TOGGLE               (0x3 << 28) // (TC) Effect: toggle
-#define AT91C_TC_BSWTRG           (0x3 << 30) // (TC) Software Trigger Effect on TIOB
-#define     AT91C_TC_BSWTRG_NONE                 (0x0 << 30) // (TC) Effect: none
-#define     AT91C_TC_BSWTRG_SET                  (0x1 << 30) // (TC) Effect: set
-#define     AT91C_TC_BSWTRG_CLEAR                (0x2 << 30) // (TC) Effect: clear
-#define     AT91C_TC_BSWTRG_TOGGLE               (0x3 << 30) // (TC) Effect: toggle
-// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
-#define AT91C_TC_COVFS            (0x1 <<  0) // (TC) Counter Overflow
-#define AT91C_TC_LOVRS            (0x1 <<  1) // (TC) Load Overrun
-#define AT91C_TC_CPAS             (0x1 <<  2) // (TC) RA Compare
-#define AT91C_TC_CPBS             (0x1 <<  3) // (TC) RB Compare
-#define AT91C_TC_CPCS             (0x1 <<  4) // (TC) RC Compare
-#define AT91C_TC_LDRAS            (0x1 <<  5) // (TC) RA Loading
-#define AT91C_TC_LDRBS            (0x1 <<  6) // (TC) RB Loading
-#define AT91C_TC_ETRCS            (0x1 <<  7) // (TC) External Trigger
-#define AT91C_TC_ETRGS            (0x1 << 16) // (TC) Clock Enabling
-#define AT91C_TC_MTIOA            (0x1 << 17) // (TC) TIOA Mirror
-#define AT91C_TC_MTIOB            (0x1 << 18) // (TC) TIOA Mirror
-// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
-// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
-// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_TC structure *** */
+#define TC_CCR                                ( 0 )         /* Channel Control Register */
+#define TC_CMR                                ( 4 )         /* Channel Mode Register (Capture Mode / Waveform Mode) */
+#define TC_CV                                 ( 16 )        /* Counter Value */
+#define TC_RA                                 ( 20 )        /* Register A */
+#define TC_RB                                 ( 24 )        /* Register B */
+#define TC_RC                                 ( 28 )        /* Register C */
+#define TC_SR                                 ( 32 )        /* Status Register */
+#define TC_IER                                ( 36 )        /* Interrupt Enable Register */
+#define TC_IDR                                ( 40 )        /* Interrupt Disable Register */
+#define TC_IMR                                ( 44 )        /* Interrupt Mask Register */
+/* -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- */
+#define AT91C_TC_CLKEN                        ( 0x1 << 0 )  /* (TC) Counter Clock Enable Command */
+#define AT91C_TC_CLKDIS                       ( 0x1 << 1 )  /* (TC) Counter Clock Disable Command */
+#define AT91C_TC_SWTRG                        ( 0x1 << 2 )  /* (TC) Software Trigger Command */
+/* -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- */
+#define AT91C_TC_CLKS                         ( 0x7 << 0 )  /* (TC) Clock Selection */
+#define     AT91C_TC_CLKS_TIMER_DIV1_CLOCK    ( 0x0 )       /* (TC) Clock selected: TIMER_DIV1_CLOCK */
+#define     AT91C_TC_CLKS_TIMER_DIV2_CLOCK    ( 0x1 )       /* (TC) Clock selected: TIMER_DIV2_CLOCK */
+#define     AT91C_TC_CLKS_TIMER_DIV3_CLOCK    ( 0x2 )       /* (TC) Clock selected: TIMER_DIV3_CLOCK */
+#define     AT91C_TC_CLKS_TIMER_DIV4_CLOCK    ( 0x3 )       /* (TC) Clock selected: TIMER_DIV4_CLOCK */
+#define     AT91C_TC_CLKS_TIMER_DIV5_CLOCK    ( 0x4 )       /* (TC) Clock selected: TIMER_DIV5_CLOCK */
+#define     AT91C_TC_CLKS_XC0                 ( 0x5 )       /* (TC) Clock selected: XC0 */
+#define     AT91C_TC_CLKS_XC1                 ( 0x6 )       /* (TC) Clock selected: XC1 */
+#define     AT91C_TC_CLKS_XC2                 ( 0x7 )       /* (TC) Clock selected: XC2 */
+#define AT91C_TC_CLKI                         ( 0x1 << 3 )  /* (TC) Clock Invert */
+#define AT91C_TC_BURST                        ( 0x3 << 4 )  /* (TC) Burst Signal Selection */
+#define     AT91C_TC_BURST_NONE               ( 0x0 << 4 )  /* (TC) The clock is not gated by an external signal */
+#define     AT91C_TC_BURST_XC0                ( 0x1 << 4 )  /* (TC) XC0 is ANDed with the selected clock */
+#define     AT91C_TC_BURST_XC1                ( 0x2 << 4 )  /* (TC) XC1 is ANDed with the selected clock */
+#define     AT91C_TC_BURST_XC2                ( 0x3 << 4 )  /* (TC) XC2 is ANDed with the selected clock */
+#define AT91C_TC_CPCSTOP                      ( 0x1 << 6 )  /* (TC) Counter Clock Stopped with RC Compare */
+#define AT91C_TC_LDBSTOP                      ( 0x1 << 6 )  /* (TC) Counter Clock Stopped with RB Loading */
+#define AT91C_TC_LDBDIS                       ( 0x1 << 7 )  /* (TC) Counter Clock Disabled with RB Loading */
+#define AT91C_TC_CPCDIS                       ( 0x1 << 7 )  /* (TC) Counter Clock Disable with RC Compare */
+#define AT91C_TC_ETRGEDG                      ( 0x3 << 8 )  /* (TC) External Trigger Edge Selection */
+#define     AT91C_TC_ETRGEDG_NONE             ( 0x0 << 8 )  /* (TC) Edge: None */
+#define     AT91C_TC_ETRGEDG_RISING           ( 0x1 << 8 )  /* (TC) Edge: rising edge */
+#define     AT91C_TC_ETRGEDG_FALLING          ( 0x2 << 8 )  /* (TC) Edge: falling edge */
+#define     AT91C_TC_ETRGEDG_BOTH             ( 0x3 << 8 )  /* (TC) Edge: each edge */
+#define AT91C_TC_EEVTEDG                      ( 0x3 << 8 )  /* (TC) External Event Edge Selection */
+#define     AT91C_TC_EEVTEDG_NONE             ( 0x0 << 8 )  /* (TC) Edge: None */
+#define     AT91C_TC_EEVTEDG_RISING           ( 0x1 << 8 )  /* (TC) Edge: rising edge */
+#define     AT91C_TC_EEVTEDG_FALLING          ( 0x2 << 8 )  /* (TC) Edge: falling edge */
+#define     AT91C_TC_EEVTEDG_BOTH             ( 0x3 << 8 )  /* (TC) Edge: each edge */
+#define AT91C_TC_ABETRG                       ( 0x1 << 10 ) /* (TC) TIOA or TIOB External Trigger Selection */
+#define AT91C_TC_EEVT                         ( 0x3 << 10 ) /* (TC) External Event  Selection */
+#define     AT91C_TC_EEVT_NONE                ( 0x0 << 10 ) /* (TC) Signal selected as external event: TIOB TIOB direction: input */
+#define     AT91C_TC_EEVT_RISING              ( 0x1 << 10 ) /* (TC) Signal selected as external event: XC0 TIOB direction: output */
+#define     AT91C_TC_EEVT_FALLING             ( 0x2 << 10 ) /* (TC) Signal selected as external event: XC1 TIOB direction: output */
+#define     AT91C_TC_EEVT_BOTH                ( 0x3 << 10 ) /* (TC) Signal selected as external event: XC2 TIOB direction: output */
+#define AT91C_TC_ENETRG                       ( 0x1 << 12 ) /* (TC) External Event Trigger enable */
+#define AT91C_TC_WAVESEL                      ( 0x3 << 13 ) /* (TC) Waveform  Selection */
+#define     AT91C_TC_WAVESEL_UP               ( 0x0 << 13 ) /* (TC) UP mode without atomatic trigger on RC Compare */
+#define     AT91C_TC_WAVESEL_UPDOWN           ( 0x1 << 13 ) /* (TC) UPDOWN mode without automatic trigger on RC Compare */
+#define     AT91C_TC_WAVESEL_UP_AUTO          ( 0x2 << 13 ) /* (TC) UP mode with automatic trigger on RC Compare */
+#define     AT91C_TC_WAVESEL_UPDOWN_AUTO      ( 0x3 << 13 ) /* (TC) UPDOWN mode with automatic trigger on RC Compare */
+#define AT91C_TC_CPCTRG                       ( 0x1 << 14 ) /* (TC) RC Compare Trigger Enable */
+#define AT91C_TC_WAVE                         ( 0x1 << 15 ) /* (TC) */
+#define AT91C_TC_LDRA                         ( 0x3 << 16 ) /* (TC) RA Loading Selection */
+#define     AT91C_TC_LDRA_NONE                ( 0x0 << 16 ) /* (TC) Edge: None */
+#define     AT91C_TC_LDRA_RISING              ( 0x1 << 16 ) /* (TC) Edge: rising edge of TIOA */
+#define     AT91C_TC_LDRA_FALLING             ( 0x2 << 16 ) /* (TC) Edge: falling edge of TIOA */
+#define     AT91C_TC_LDRA_BOTH                ( 0x3 << 16 ) /* (TC) Edge: each edge of TIOA */
+#define AT91C_TC_ACPA                         ( 0x3 << 16 ) /* (TC) RA Compare Effect on TIOA */
+#define     AT91C_TC_ACPA_NONE                ( 0x0 << 16 ) /* (TC) Effect: none */
+#define     AT91C_TC_ACPA_SET                 ( 0x1 << 16 ) /* (TC) Effect: set */
+#define     AT91C_TC_ACPA_CLEAR               ( 0x2 << 16 ) /* (TC) Effect: clear */
+#define     AT91C_TC_ACPA_TOGGLE              ( 0x3 << 16 ) /* (TC) Effect: toggle */
+#define AT91C_TC_LDRB                         ( 0x3 << 18 ) /* (TC) RB Loading Selection */
+#define     AT91C_TC_LDRB_NONE                ( 0x0 << 18 ) /* (TC) Edge: None */
+#define     AT91C_TC_LDRB_RISING              ( 0x1 << 18 ) /* (TC) Edge: rising edge of TIOA */
+#define     AT91C_TC_LDRB_FALLING             ( 0x2 << 18 ) /* (TC) Edge: falling edge of TIOA */
+#define     AT91C_TC_LDRB_BOTH                ( 0x3 << 18 ) /* (TC) Edge: each edge of TIOA */
+#define AT91C_TC_ACPC                         ( 0x3 << 18 ) /* (TC) RC Compare Effect on TIOA */
+#define     AT91C_TC_ACPC_NONE                ( 0x0 << 18 ) /* (TC) Effect: none */
+#define     AT91C_TC_ACPC_SET                 ( 0x1 << 18 ) /* (TC) Effect: set */
+#define     AT91C_TC_ACPC_CLEAR               ( 0x2 << 18 ) /* (TC) Effect: clear */
+#define     AT91C_TC_ACPC_TOGGLE              ( 0x3 << 18 ) /* (TC) Effect: toggle */
+#define AT91C_TC_AEEVT                        ( 0x3 << 20 ) /* (TC) External Event Effect on TIOA */
+#define     AT91C_TC_AEEVT_NONE               ( 0x0 << 20 ) /* (TC) Effect: none */
+#define     AT91C_TC_AEEVT_SET                ( 0x1 << 20 ) /* (TC) Effect: set */
+#define     AT91C_TC_AEEVT_CLEAR              ( 0x2 << 20 ) /* (TC) Effect: clear */
+#define     AT91C_TC_AEEVT_TOGGLE             ( 0x3 << 20 ) /* (TC) Effect: toggle */
+#define AT91C_TC_ASWTRG                       ( 0x3 << 22 ) /* (TC) Software Trigger Effect on TIOA */
+#define     AT91C_TC_ASWTRG_NONE              ( 0x0 << 22 ) /* (TC) Effect: none */
+#define     AT91C_TC_ASWTRG_SET               ( 0x1 << 22 ) /* (TC) Effect: set */
+#define     AT91C_TC_ASWTRG_CLEAR             ( 0x2 << 22 ) /* (TC) Effect: clear */
+#define     AT91C_TC_ASWTRG_TOGGLE            ( 0x3 << 22 ) /* (TC) Effect: toggle */
+#define AT91C_TC_BCPB                         ( 0x3 << 24 ) /* (TC) RB Compare Effect on TIOB */
+#define     AT91C_TC_BCPB_NONE                ( 0x0 << 24 ) /* (TC) Effect: none */
+#define     AT91C_TC_BCPB_SET                 ( 0x1 << 24 ) /* (TC) Effect: set */
+#define     AT91C_TC_BCPB_CLEAR               ( 0x2 << 24 ) /* (TC) Effect: clear */
+#define     AT91C_TC_BCPB_TOGGLE              ( 0x3 << 24 ) /* (TC) Effect: toggle */
+#define AT91C_TC_BCPC                         ( 0x3 << 26 ) /* (TC) RC Compare Effect on TIOB */
+#define     AT91C_TC_BCPC_NONE                ( 0x0 << 26 ) /* (TC) Effect: none */
+#define     AT91C_TC_BCPC_SET                 ( 0x1 << 26 ) /* (TC) Effect: set */
+#define     AT91C_TC_BCPC_CLEAR               ( 0x2 << 26 ) /* (TC) Effect: clear */
+#define     AT91C_TC_BCPC_TOGGLE              ( 0x3 << 26 ) /* (TC) Effect: toggle */
+#define AT91C_TC_BEEVT                        ( 0x3 << 28 ) /* (TC) External Event Effect on TIOB */
+#define     AT91C_TC_BEEVT_NONE               ( 0x0 << 28 ) /* (TC) Effect: none */
+#define     AT91C_TC_BEEVT_SET                ( 0x1 << 28 ) /* (TC) Effect: set */
+#define     AT91C_TC_BEEVT_CLEAR              ( 0x2 << 28 ) /* (TC) Effect: clear */
+#define     AT91C_TC_BEEVT_TOGGLE             ( 0x3 << 28 ) /* (TC) Effect: toggle */
+#define AT91C_TC_BSWTRG                       ( 0x3 << 30 ) /* (TC) Software Trigger Effect on TIOB */
+#define     AT91C_TC_BSWTRG_NONE              ( 0x0 << 30 ) /* (TC) Effect: none */
+#define     AT91C_TC_BSWTRG_SET               ( 0x1 << 30 ) /* (TC) Effect: set */
+#define     AT91C_TC_BSWTRG_CLEAR             ( 0x2 << 30 ) /* (TC) Effect: clear */
+#define     AT91C_TC_BSWTRG_TOGGLE            ( 0x3 << 30 ) /* (TC) Effect: toggle */
+/* -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- */
+#define AT91C_TC_COVFS                        ( 0x1 << 0 )  /* (TC) Counter Overflow */
+#define AT91C_TC_LOVRS                        ( 0x1 << 1 )  /* (TC) Load Overrun */
+#define AT91C_TC_CPAS                         ( 0x1 << 2 )  /* (TC) RA Compare */
+#define AT91C_TC_CPBS                         ( 0x1 << 3 )  /* (TC) RB Compare */
+#define AT91C_TC_CPCS                         ( 0x1 << 4 )  /* (TC) RC Compare */
+#define AT91C_TC_LDRAS                        ( 0x1 << 5 )  /* (TC) RA Loading */
+#define AT91C_TC_LDRBS                        ( 0x1 << 6 )  /* (TC) RB Loading */
+#define AT91C_TC_ETRCS                        ( 0x1 << 7 )  /* (TC) External Trigger */
+#define AT91C_TC_ETRGS                        ( 0x1 << 16 ) /* (TC) Clock Enabling */
+#define AT91C_TC_MTIOA                        ( 0x1 << 17 ) /* (TC) TIOA Mirror */
+#define AT91C_TC_MTIOB                        ( 0x1 << 18 ) /* (TC) TIOA Mirror */
+/* -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- */
+/* -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- */
+/* -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Timer Counter Interface
-// *****************************************************************************
-// *** Register offset in AT91S_TCB structure ***
-#define TCB_TC0         ( 0) // TC Channel 0
-#define TCB_TC1         (64) // TC Channel 1
-#define TCB_TC2         (128) // TC Channel 2
-#define TCB_BCR         (192) // TC Block Control Register
-#define TCB_BMR         (196) // TC Block Mode Register
-// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
-#define AT91C_TCB_SYNC            (0x1 <<  0) // (TCB) Synchro Command
-// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
-#define AT91C_TCB_TC0XC0S         (0x1 <<  0) // (TCB) External Clock Signal 0 Selection
-#define     AT91C_TCB_TC0XC0S_TCLK0                (0x0) // (TCB) TCLK0 connected to XC0
-#define     AT91C_TCB_TC0XC0S_NONE                 (0x1) // (TCB) None signal connected to XC0
-#define     AT91C_TCB_TC0XC0S_TIOA1                (0x2) // (TCB) TIOA1 connected to XC0
-#define     AT91C_TCB_TC0XC0S_TIOA2                (0x3) // (TCB) TIOA2 connected to XC0
-#define AT91C_TCB_TC1XC1S         (0x1 <<  2) // (TCB) External Clock Signal 1 Selection
-#define     AT91C_TCB_TC1XC1S_TCLK1                (0x0 <<  2) // (TCB) TCLK1 connected to XC1
-#define     AT91C_TCB_TC1XC1S_NONE                 (0x1 <<  2) // (TCB) None signal connected to XC1
-#define     AT91C_TCB_TC1XC1S_TIOA0                (0x2 <<  2) // (TCB) TIOA0 connected to XC1
-#define     AT91C_TCB_TC1XC1S_TIOA2                (0x3 <<  2) // (TCB) TIOA2 connected to XC1
-#define AT91C_TCB_TC2XC2S         (0x1 <<  4) // (TCB) External Clock Signal 2 Selection
-#define     AT91C_TCB_TC2XC2S_TCLK2                (0x0 <<  4) // (TCB) TCLK2 connected to XC2
-#define     AT91C_TCB_TC2XC2S_NONE                 (0x1 <<  4) // (TCB) None signal connected to XC2
-#define     AT91C_TCB_TC2XC2S_TIOA0                (0x2 <<  4) // (TCB) TIOA0 connected to XC2
-#define     AT91C_TCB_TC2XC2S_TIOA2                (0x3 <<  4) // (TCB) TIOA2 connected to XC2
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Timer Counter Interface */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_TCB structure *** */
+#define TCB_TC0                        ( 0 )        /* TC Channel 0 */
+#define TCB_TC1                        ( 64 )       /* TC Channel 1 */
+#define TCB_TC2                        ( 128 )      /* TC Channel 2 */
+#define TCB_BCR                        ( 192 )      /* TC Block Control Register */
+#define TCB_BMR                        ( 196 )      /* TC Block Mode Register */
+/* -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- */
+#define AT91C_TCB_SYNC                 ( 0x1 << 0 ) /* (TCB) Synchro Command */
+/* -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- */
+#define AT91C_TCB_TC0XC0S              ( 0x1 << 0 ) /* (TCB) External Clock Signal 0 Selection */
+#define     AT91C_TCB_TC0XC0S_TCLK0    ( 0x0 )      /* (TCB) TCLK0 connected to XC0 */
+#define     AT91C_TCB_TC0XC0S_NONE     ( 0x1 )      /* (TCB) None signal connected to XC0 */
+#define     AT91C_TCB_TC0XC0S_TIOA1    ( 0x2 )      /* (TCB) TIOA1 connected to XC0 */
+#define     AT91C_TCB_TC0XC0S_TIOA2    ( 0x3 )      /* (TCB) TIOA2 connected to XC0 */
+#define AT91C_TCB_TC1XC1S              ( 0x1 << 2 ) /* (TCB) External Clock Signal 1 Selection */
+#define     AT91C_TCB_TC1XC1S_TCLK1    ( 0x0 << 2 ) /* (TCB) TCLK1 connected to XC1 */
+#define     AT91C_TCB_TC1XC1S_NONE     ( 0x1 << 2 ) /* (TCB) None signal connected to XC1 */
+#define     AT91C_TCB_TC1XC1S_TIOA0    ( 0x2 << 2 ) /* (TCB) TIOA0 connected to XC1 */
+#define     AT91C_TCB_TC1XC1S_TIOA2    ( 0x3 << 2 ) /* (TCB) TIOA2 connected to XC1 */
+#define AT91C_TCB_TC2XC2S              ( 0x1 << 4 ) /* (TCB) External Clock Signal 2 Selection */
+#define     AT91C_TCB_TC2XC2S_TCLK2    ( 0x0 << 4 ) /* (TCB) TCLK2 connected to XC2 */
+#define     AT91C_TCB_TC2XC2S_NONE     ( 0x1 << 4 ) /* (TCB) None signal connected to XC2 */
+#define     AT91C_TCB_TC2XC2S_TIOA0    ( 0x2 << 4 ) /* (TCB) TIOA0 connected to XC2 */
+#define     AT91C_TCB_TC2XC2S_TIOA2    ( 0x3 << 4 ) /* (TCB) TIOA2 connected to XC2 */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR PWMC Channel Interface
-// *****************************************************************************
-// *** Register offset in AT91S_PWMC_CH structure ***
-#define PWMC_CMR        ( 0) // Channel Mode Register
-#define PWMC_CDTYR      ( 4) // Channel Duty Cycle Register
-#define PWMC_CPRDR      ( 8) // Channel Period Register
-#define PWMC_CCNTR      (12) // Channel Counter Register
-#define PWMC_CUPDR      (16) // Channel Update Register
-#define PWMC_Reserved   (20) // Reserved
-// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
-#define AT91C_PWMC_CPRE           (0xF <<  0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
-#define     AT91C_PWMC_CPRE_MCK                  (0x0) // (PWMC_CH)
-#define     AT91C_PWMC_CPRE_MCKA                 (0xB) // (PWMC_CH)
-#define     AT91C_PWMC_CPRE_MCKB                 (0xC) // (PWMC_CH)
-#define AT91C_PWMC_CALG           (0x1 <<  8) // (PWMC_CH) Channel Alignment
-#define AT91C_PWMC_CPOL           (0x1 <<  9) // (PWMC_CH) Channel Polarity
-#define AT91C_PWMC_CPD            (0x1 << 10) // (PWMC_CH) Channel Update Period
-// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
-#define AT91C_PWMC_CDTY           (0x0 <<  0) // (PWMC_CH) Channel Duty Cycle
-// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
-#define AT91C_PWMC_CPRD           (0x0 <<  0) // (PWMC_CH) Channel Period
-// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
-#define AT91C_PWMC_CCNT           (0x0 <<  0) // (PWMC_CH) Channel Counter
-// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
-#define AT91C_PWMC_CUPD           (0x0 <<  0) // (PWMC_CH) Channel Update
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR PWMC Channel Interface */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_PWMC_CH structure *** */
+#define PWMC_CMR                    ( 0 )         /* Channel Mode Register */
+#define PWMC_CDTYR                  ( 4 )         /* Channel Duty Cycle Register */
+#define PWMC_CPRDR                  ( 8 )         /* Channel Period Register */
+#define PWMC_CCNTR                  ( 12 )        /* Channel Counter Register */
+#define PWMC_CUPDR                  ( 16 )        /* Channel Update Register */
+#define PWMC_Reserved               ( 20 )        /* Reserved */
+/* -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- */
+#define AT91C_PWMC_CPRE             ( 0xF << 0 )  /* (PWMC_CH) Channel Pre-scaler : PWMC_CLKx */
+#define     AT91C_PWMC_CPRE_MCK     ( 0x0 )       /* (PWMC_CH) */
+#define     AT91C_PWMC_CPRE_MCKA    ( 0xB )       /* (PWMC_CH) */
+#define     AT91C_PWMC_CPRE_MCKB    ( 0xC )       /* (PWMC_CH) */
+#define AT91C_PWMC_CALG             ( 0x1 << 8 )  /* (PWMC_CH) Channel Alignment */
+#define AT91C_PWMC_CPOL             ( 0x1 << 9 )  /* (PWMC_CH) Channel Polarity */
+#define AT91C_PWMC_CPD              ( 0x1 << 10 ) /* (PWMC_CH) Channel Update Period */
+/* -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- */
+#define AT91C_PWMC_CDTY             ( 0x0 << 0 )  /* (PWMC_CH) Channel Duty Cycle */
+/* -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- */
+#define AT91C_PWMC_CPRD             ( 0x0 << 0 )  /* (PWMC_CH) Channel Period */
+/* -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- */
+#define AT91C_PWMC_CCNT             ( 0x0 << 0 )  /* (PWMC_CH) Channel Counter */
+/* -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- */
+#define AT91C_PWMC_CUPD             ( 0x0 << 0 )  /* (PWMC_CH) Channel Update */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface
-// *****************************************************************************
-// *** Register offset in AT91S_PWMC structure ***
-#define PWMC_MR         ( 0) // PWMC Mode Register
-#define PWMC_ENA        ( 4) // PWMC Enable Register
-#define PWMC_DIS        ( 8) // PWMC Disable Register
-#define PWMC_SR         (12) // PWMC Status Register
-#define PWMC_IER        (16) // PWMC Interrupt Enable Register
-#define PWMC_IDR        (20) // PWMC Interrupt Disable Register
-#define PWMC_IMR        (24) // PWMC Interrupt Mask Register
-#define PWMC_ISR        (28) // PWMC Interrupt Status Register
-#define PWMC_VR         (252) // PWMC Version Register
-#define PWMC_CH         (512) // PWMC Channel 0
-// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
-#define AT91C_PWMC_DIVA           (0xFF <<  0) // (PWMC) CLKA divide factor.
-#define AT91C_PWMC_PREA           (0xF <<  8) // (PWMC) Divider Input Clock Prescaler A
-#define     AT91C_PWMC_PREA_MCK                  (0x0 <<  8) // (PWMC)
-#define AT91C_PWMC_DIVB           (0xFF << 16) // (PWMC) CLKB divide factor.
-#define AT91C_PWMC_PREB           (0xF << 24) // (PWMC) Divider Input Clock Prescaler B
-#define     AT91C_PWMC_PREB_MCK                  (0x0 << 24) // (PWMC)
-// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
-#define AT91C_PWMC_CHID0          (0x1 <<  0) // (PWMC) Channel ID 0
-#define AT91C_PWMC_CHID1          (0x1 <<  1) // (PWMC) Channel ID 1
-#define AT91C_PWMC_CHID2          (0x1 <<  2) // (PWMC) Channel ID 2
-#define AT91C_PWMC_CHID3          (0x1 <<  3) // (PWMC) Channel ID 3
-#define AT91C_PWMC_CHID4          (0x1 <<  4) // (PWMC) Channel ID 4
-#define AT91C_PWMC_CHID5          (0x1 <<  5) // (PWMC) Channel ID 5
-#define AT91C_PWMC_CHID6          (0x1 <<  6) // (PWMC) Channel ID 6
-#define AT91C_PWMC_CHID7          (0x1 <<  7) // (PWMC) Channel ID 7
-// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
-// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
-// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
-// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
-// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
-// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_PWMC structure *** */
+#define PWMC_MR                    ( 0 )          /* PWMC Mode Register */
+#define PWMC_ENA                   ( 4 )          /* PWMC Enable Register */
+#define PWMC_DIS                   ( 8 )          /* PWMC Disable Register */
+#define PWMC_SR                    ( 12 )         /* PWMC Status Register */
+#define PWMC_IER                   ( 16 )         /* PWMC Interrupt Enable Register */
+#define PWMC_IDR                   ( 20 )         /* PWMC Interrupt Disable Register */
+#define PWMC_IMR                   ( 24 )         /* PWMC Interrupt Mask Register */
+#define PWMC_ISR                   ( 28 )         /* PWMC Interrupt Status Register */
+#define PWMC_VR                    ( 252 )        /* PWMC Version Register */
+#define PWMC_CH                    ( 512 )        /* PWMC Channel 0 */
+/* -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- */
+#define AT91C_PWMC_DIVA            ( 0xFF << 0 )  /* (PWMC) CLKA divide factor. */
+#define AT91C_PWMC_PREA            ( 0xF << 8 )   /* (PWMC) Divider Input Clock Prescaler A */
+#define     AT91C_PWMC_PREA_MCK    ( 0x0 << 8 )   /* (PWMC) */
+#define AT91C_PWMC_DIVB            ( 0xFF << 16 ) /* (PWMC) CLKB divide factor. */
+#define AT91C_PWMC_PREB            ( 0xF << 24 )  /* (PWMC) Divider Input Clock Prescaler B */
+#define     AT91C_PWMC_PREB_MCK    ( 0x0 << 24 )  /* (PWMC) */
+/* -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- */
+#define AT91C_PWMC_CHID0           ( 0x1 << 0 )   /* (PWMC) Channel ID 0 */
+#define AT91C_PWMC_CHID1           ( 0x1 << 1 )   /* (PWMC) Channel ID 1 */
+#define AT91C_PWMC_CHID2           ( 0x1 << 2 )   /* (PWMC) Channel ID 2 */
+#define AT91C_PWMC_CHID3           ( 0x1 << 3 )   /* (PWMC) Channel ID 3 */
+#define AT91C_PWMC_CHID4           ( 0x1 << 4 )   /* (PWMC) Channel ID 4 */
+#define AT91C_PWMC_CHID5           ( 0x1 << 5 )   /* (PWMC) Channel ID 5 */
+#define AT91C_PWMC_CHID6           ( 0x1 << 6 )   /* (PWMC) Channel ID 6 */
+#define AT91C_PWMC_CHID7           ( 0x1 << 7 )   /* (PWMC) Channel ID 7 */
+/* -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- */
+/* -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- */
+/* -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- */
+/* -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- */
+/* -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- */
+/* -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR USB Device Interface
-// *****************************************************************************
-// *** Register offset in AT91S_UDP structure ***
-#define UDP_NUM         ( 0) // Frame Number Register
-#define UDP_GLBSTATE    ( 4) // Global State Register
-#define UDP_FADDR       ( 8) // Function Address Register
-#define UDP_IER         (16) // Interrupt Enable Register
-#define UDP_IDR         (20) // Interrupt Disable Register
-#define UDP_IMR         (24) // Interrupt Mask Register
-#define UDP_ISR         (28) // Interrupt Status Register
-#define UDP_ICR         (32) // Interrupt Clear Register
-#define UDP_RSTEP       (40) // Reset Endpoint Register
-#define UDP_CSR         (48) // Endpoint Control and Status Register
-#define UDP_FDR         (80) // Endpoint FIFO Data Register
-// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
-#define AT91C_UDP_FRM_NUM         (0x7FF <<  0) // (UDP) Frame Number as Defined in the Packet Field Formats
-#define AT91C_UDP_FRM_ERR         (0x1 << 16) // (UDP) Frame Error
-#define AT91C_UDP_FRM_OK          (0x1 << 17) // (UDP) Frame OK
-// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
-#define AT91C_UDP_FADDEN          (0x1 <<  0) // (UDP) Function Address Enable
-#define AT91C_UDP_CONFG           (0x1 <<  1) // (UDP) Configured
-#define AT91C_UDP_RMWUPE          (0x1 <<  2) // (UDP) Remote Wake Up Enable
-#define AT91C_UDP_RSMINPR         (0x1 <<  3) // (UDP) A Resume Has Been Sent to the Host
-// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
-#define AT91C_UDP_FADD            (0xFF <<  0) // (UDP) Function Address Value
-#define AT91C_UDP_FEN             (0x1 <<  8) // (UDP) Function Enable
-// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
-#define AT91C_UDP_EPINT0          (0x1 <<  0) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT1          (0x1 <<  1) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT2          (0x1 <<  2) // (UDP) Endpoint 2 Interrupt
-#define AT91C_UDP_EPINT3          (0x1 <<  3) // (UDP) Endpoint 3 Interrupt
-#define AT91C_UDP_EPINT4          (0x1 <<  4) // (UDP) Endpoint 4 Interrupt
-#define AT91C_UDP_EPINT5          (0x1 <<  5) // (UDP) Endpoint 5 Interrupt
-#define AT91C_UDP_EPINT6          (0x1 <<  6) // (UDP) Endpoint 6 Interrupt
-#define AT91C_UDP_EPINT7          (0x1 <<  7) // (UDP) Endpoint 7 Interrupt
-#define AT91C_UDP_RXSUSP          (0x1 <<  8) // (UDP) USB Suspend Interrupt
-#define AT91C_UDP_RXRSM           (0x1 <<  9) // (UDP) USB Resume Interrupt
-#define AT91C_UDP_EXTRSM          (0x1 << 10) // (UDP) USB External Resume Interrupt
-#define AT91C_UDP_SOFINT          (0x1 << 11) // (UDP) USB Start Of frame Interrupt
-#define AT91C_UDP_WAKEUP          (0x1 << 13) // (UDP) USB Resume Interrupt
-// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
-// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
-// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
-#define AT91C_UDP_ENDBUSRES       (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
-// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
-// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
-#define AT91C_UDP_EP0             (0x1 <<  0) // (UDP) Reset Endpoint 0
-#define AT91C_UDP_EP1             (0x1 <<  1) // (UDP) Reset Endpoint 1
-#define AT91C_UDP_EP2             (0x1 <<  2) // (UDP) Reset Endpoint 2
-#define AT91C_UDP_EP3             (0x1 <<  3) // (UDP) Reset Endpoint 3
-#define AT91C_UDP_EP4             (0x1 <<  4) // (UDP) Reset Endpoint 4
-#define AT91C_UDP_EP5             (0x1 <<  5) // (UDP) Reset Endpoint 5
-#define AT91C_UDP_EP6             (0x1 <<  6) // (UDP) Reset Endpoint 6
-#define AT91C_UDP_EP7             (0x1 <<  7) // (UDP) Reset Endpoint 7
-// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
-#define AT91C_UDP_TXCOMP          (0x1 <<  0) // (UDP) Generates an IN packet with data previously written in the DPR
-#define AT91C_UDP_RX_DATA_BK0     (0x1 <<  1) // (UDP) Receive Data Bank 0
-#define AT91C_UDP_RXSETUP         (0x1 <<  2) // (UDP) Sends STALL to the Host (Control endpoints)
-#define AT91C_UDP_ISOERROR        (0x1 <<  3) // (UDP) Isochronous error (Isochronous endpoints)
-#define AT91C_UDP_TXPKTRDY        (0x1 <<  4) // (UDP) Transmit Packet Ready
-#define AT91C_UDP_FORCESTALL      (0x1 <<  5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
-#define AT91C_UDP_RX_DATA_BK1     (0x1 <<  6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
-#define AT91C_UDP_DIR             (0x1 <<  7) // (UDP) Transfer Direction
-#define AT91C_UDP_EPTYPE          (0x7 <<  8) // (UDP) Endpoint type
-#define     AT91C_UDP_EPTYPE_CTRL                 (0x0 <<  8) // (UDP) Control
-#define     AT91C_UDP_EPTYPE_ISO_OUT              (0x1 <<  8) // (UDP) Isochronous OUT
-#define     AT91C_UDP_EPTYPE_BULK_OUT             (0x2 <<  8) // (UDP) Bulk OUT
-#define     AT91C_UDP_EPTYPE_INT_OUT              (0x3 <<  8) // (UDP) Interrupt OUT
-#define     AT91C_UDP_EPTYPE_ISO_IN               (0x5 <<  8) // (UDP) Isochronous IN
-#define     AT91C_UDP_EPTYPE_BULK_IN              (0x6 <<  8) // (UDP) Bulk IN
-#define     AT91C_UDP_EPTYPE_INT_IN               (0x7 <<  8) // (UDP) Interrupt IN
-#define AT91C_UDP_DTGLE           (0x1 << 11) // (UDP) Data Toggle
-#define AT91C_UDP_EPEDS           (0x1 << 15) // (UDP) Endpoint Enable Disable
-#define AT91C_UDP_RXBYTECNT       (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR USB Device Interface */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_UDP structure *** */
+#define UDP_NUM              ( 0 )          /* Frame Number Register */
+#define UDP_GLBSTATE         ( 4 )          /* Global State Register */
+#define UDP_FADDR            ( 8 )          /* Function Address Register */
+#define UDP_IER              ( 16 )         /* Interrupt Enable Register */
+#define UDP_IDR              ( 20 )         /* Interrupt Disable Register */
+#define UDP_IMR              ( 24 )         /* Interrupt Mask Register */
+#define UDP_ISR              ( 28 )         /* Interrupt Status Register */
+#define UDP_ICR              ( 32 )         /* Interrupt Clear Register */
+#define UDP_RSTEP            ( 40 )         /* Reset Endpoint Register */
+#define UDP_CSR              ( 48 )         /* Endpoint Control and Status Register */
+#define UDP_FDR              ( 80 )         /* Endpoint FIFO Data Register */
+/* -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- */
+#define AT91C_UDP_FRM_NUM    ( 0x7FF << 0 ) /* (UDP) Frame Number as Defined in the Packet Field Formats */
+#define AT91C_UDP_FRM_ERR    ( 0x1 << 16 )  /* (UDP) Frame Error */
+#define AT91C_UDP_FRM_OK     ( 0x1 << 17 )  /* (UDP) Frame OK */
+/* -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- */
+#define AT91C_UDP_FADDEN     ( 0x1 << 0 )   /* (UDP) Function Address Enable */
+#define AT91C_UDP_CONFG      ( 0x1 << 1 )   /* (UDP) Configured */
+#define AT91C_UDP_RMWUPE     ( 0x1 << 2 )   /* (UDP) Remote Wake Up Enable */
+#define AT91C_UDP_RSMINPR    ( 0x1 << 3 )   /* (UDP) A Resume Has Been Sent to the Host */
+/* -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- */
+#define AT91C_UDP_FADD       ( 0xFF << 0 )  /* (UDP) Function Address Value */
+#define AT91C_UDP_FEN        ( 0x1 << 8 )   /* (UDP) Function Enable */
+/* -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- */
+#define AT91C_UDP_EPINT0     ( 0x1 << 0 )   /* (UDP) Endpoint 0 Interrupt */
+#define AT91C_UDP_EPINT1     ( 0x1 << 1 )   /* (UDP) Endpoint 0 Interrupt */
+#define AT91C_UDP_EPINT2     ( 0x1 << 2 )   /* (UDP) Endpoint 2 Interrupt */
+#define AT91C_UDP_EPINT3     ( 0x1 << 3 )   /* (UDP) Endpoint 3 Interrupt */
+#define AT91C_UDP_EPINT4     ( 0x1 << 4 )   /* (UDP) Endpoint 4 Interrupt */
+#define AT91C_UDP_EPINT5     ( 0x1 << 5 )   /* (UDP) Endpoint 5 Interrupt */
+#define AT91C_UDP_EPINT6     ( 0x1 << 6 )   /* (UDP) Endpoint 6 Interrupt */
+#define AT91C_UDP_EPINT7     ( 0x1 << 7 )   /* (UDP) Endpoint 7 Interrupt */
+#define AT91C_UDP_RXSUSP     ( 0x1 << 8 )   /* (UDP) USB Suspend Interrupt */
+#define AT91C_UDP_RXRSM      ( 0x1 << 9 )   /* (UDP) USB Resume Interrupt */
+#define AT91C_UDP_EXTRSM     ( 0x1 << 10 )  /* (UDP) USB External Resume Interrupt */
+#define AT91C_UDP_SOFINT     ( 0x1 << 11 )  /* (UDP) USB Start Of frame Interrupt */
+#define AT91C_UDP_WAKEUP     ( 0x1 << 13 )  /* (UDP) USB Resume Interrupt */
+/* -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- */
+/* -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- */
+/* -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- */
+#define AT91C_UDP_ENDBUSRES              ( 0x1 << 12 ) /* (UDP) USB End Of Bus Reset Interrupt */
+/* -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- */
+/* -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- */
+#define AT91C_UDP_EP0                    ( 0x1 << 0 )    /* (UDP) Reset Endpoint 0 */
+#define AT91C_UDP_EP1                    ( 0x1 << 1 )    /* (UDP) Reset Endpoint 1 */
+#define AT91C_UDP_EP2                    ( 0x1 << 2 )    /* (UDP) Reset Endpoint 2 */
+#define AT91C_UDP_EP3                    ( 0x1 << 3 )    /* (UDP) Reset Endpoint 3 */
+#define AT91C_UDP_EP4                    ( 0x1 << 4 )    /* (UDP) Reset Endpoint 4 */
+#define AT91C_UDP_EP5                    ( 0x1 << 5 )    /* (UDP) Reset Endpoint 5 */
+#define AT91C_UDP_EP6                    ( 0x1 << 6 )    /* (UDP) Reset Endpoint 6 */
+#define AT91C_UDP_EP7                    ( 0x1 << 7 )    /* (UDP) Reset Endpoint 7 */
+/* -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- */
+#define AT91C_UDP_TXCOMP                 ( 0x1 << 0 )    /* (UDP) Generates an IN packet with data previously written in the DPR */
+#define AT91C_UDP_RX_DATA_BK0            ( 0x1 << 1 )    /* (UDP) Receive Data Bank 0 */
+#define AT91C_UDP_RXSETUP                ( 0x1 << 2 )    /* (UDP) Sends STALL to the Host (Control endpoints) */
+#define AT91C_UDP_ISOERROR               ( 0x1 << 3 )    /* (UDP) Isochronous error (Isochronous endpoints) */
+#define AT91C_UDP_TXPKTRDY               ( 0x1 << 4 )    /* (UDP) Transmit Packet Ready */
+#define AT91C_UDP_FORCESTALL             ( 0x1 << 5 )    /* (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). */
+#define AT91C_UDP_RX_DATA_BK1            ( 0x1 << 6 )    /* (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). */
+#define AT91C_UDP_DIR                    ( 0x1 << 7 )    /* (UDP) Transfer Direction */
+#define AT91C_UDP_EPTYPE                 ( 0x7 << 8 )    /* (UDP) Endpoint type */
+#define     AT91C_UDP_EPTYPE_CTRL        ( 0x0 << 8 )    /* (UDP) Control */
+#define     AT91C_UDP_EPTYPE_ISO_OUT     ( 0x1 << 8 )    /* (UDP) Isochronous OUT */
+#define     AT91C_UDP_EPTYPE_BULK_OUT    ( 0x2 << 8 )    /* (UDP) Bulk OUT */
+#define     AT91C_UDP_EPTYPE_INT_OUT     ( 0x3 << 8 )    /* (UDP) Interrupt OUT */
+#define     AT91C_UDP_EPTYPE_ISO_IN      ( 0x5 << 8 )    /* (UDP) Isochronous IN */
+#define     AT91C_UDP_EPTYPE_BULK_IN     ( 0x6 << 8 )    /* (UDP) Bulk IN */
+#define     AT91C_UDP_EPTYPE_INT_IN      ( 0x7 << 8 )    /* (UDP) Interrupt IN */
+#define AT91C_UDP_DTGLE                  ( 0x1 << 11 )   /* (UDP) Data Toggle */
+#define AT91C_UDP_EPEDS                  ( 0x1 << 15 )   /* (UDP) Endpoint Enable Disable */
+#define AT91C_UDP_RXBYTECNT              ( 0x7FF << 16 ) /* (UDP) Number Of Bytes Available in the FIFO */
 
-// *****************************************************************************
-//               REGISTER ADDRESS DEFINITION FOR AT91SAM7S64
-// *****************************************************************************
-// ========== Register definition for SYSC peripheral ==========
-#define AT91C_SYSC_SYSC_VRPM      (0xFFFFFD60) // (SYSC) Voltage Regulator Power Mode Register
-// ========== Register definition for AIC peripheral ==========
-#define AT91C_AIC_ICCR            (0xFFFFF128) // (AIC) Interrupt Clear Command Register
-#define AT91C_AIC_IECR            (0xFFFFF120) // (AIC) Interrupt Enable Command Register
-#define AT91C_AIC_SMR             (0xFFFFF000) // (AIC) Source Mode Register
-#define AT91C_AIC_ISCR            (0xFFFFF12C) // (AIC) Interrupt Set Command Register
-#define AT91C_AIC_EOICR           (0xFFFFF130) // (AIC) End of Interrupt Command Register
-#define AT91C_AIC_DCR             (0xFFFFF138) // (AIC) Debug Control Register (Protect)
-#define AT91C_AIC_FFER            (0xFFFFF140) // (AIC) Fast Forcing Enable Register
-#define AT91C_AIC_SVR             (0xFFFFF080) // (AIC) Source Vector Register
-#define AT91C_AIC_SPU             (0xFFFFF134) // (AIC) Spurious Vector Register
-#define AT91C_AIC_FFDR            (0xFFFFF144) // (AIC) Fast Forcing Disable Register
-#define AT91C_AIC_FVR             (0xFFFFF104) // (AIC) FIQ Vector Register
-#define AT91C_AIC_FFSR            (0xFFFFF148) // (AIC) Fast Forcing Status Register
-#define AT91C_AIC_IMR             (0xFFFFF110) // (AIC) Interrupt Mask Register
-#define AT91C_AIC_ISR             (0xFFFFF108) // (AIC) Interrupt Status Register
-#define AT91C_AIC_IVR             (0xFFFFF100) // (AIC) IRQ Vector Register
-#define AT91C_AIC_IDCR            (0xFFFFF124) // (AIC) Interrupt Disable Command Register
-#define AT91C_AIC_CISR            (0xFFFFF114) // (AIC) Core Interrupt Status Register
-#define AT91C_AIC_IPR             (0xFFFFF10C) // (AIC) Interrupt Pending Register
-// ========== Register definition for DBGU peripheral ==========
-#define AT91C_DBGU_C2R            (0xFFFFF244) // (DBGU) Chip ID2 Register
-#define AT91C_DBGU_THR            (0xFFFFF21C) // (DBGU) Transmitter Holding Register
-#define AT91C_DBGU_CSR            (0xFFFFF214) // (DBGU) Channel Status Register
-#define AT91C_DBGU_IDR            (0xFFFFF20C) // (DBGU) Interrupt Disable Register
-#define AT91C_DBGU_MR             (0xFFFFF204) // (DBGU) Mode Register
-#define AT91C_DBGU_FNTR           (0xFFFFF248) // (DBGU) Force NTRST Register
-#define AT91C_DBGU_C1R            (0xFFFFF240) // (DBGU) Chip ID1 Register
-#define AT91C_DBGU_BRGR           (0xFFFFF220) // (DBGU) Baud Rate Generator Register
-#define AT91C_DBGU_RHR            (0xFFFFF218) // (DBGU) Receiver Holding Register
-#define AT91C_DBGU_IMR            (0xFFFFF210) // (DBGU) Interrupt Mask Register
-#define AT91C_DBGU_IER            (0xFFFFF208) // (DBGU) Interrupt Enable Register
-#define AT91C_DBGU_CR             (0xFFFFF200) // (DBGU) Control Register
-// ========== Register definition for PDC_DBGU peripheral ==========
-#define AT91C_DBGU_TNCR           (0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
-#define AT91C_DBGU_RNCR           (0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
-#define AT91C_DBGU_PTCR           (0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
-#define AT91C_DBGU_PTSR           (0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
-#define AT91C_DBGU_RCR            (0xFFFFF304) // (PDC_DBGU) Receive Counter Register
-#define AT91C_DBGU_TCR            (0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
-#define AT91C_DBGU_RPR            (0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
-#define AT91C_DBGU_TPR            (0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
-#define AT91C_DBGU_RNPR           (0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
-#define AT91C_DBGU_TNPR           (0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
-// ========== Register definition for PIOA peripheral ==========
-#define AT91C_PIOA_IMR            (0xFFFFF448) // (PIOA) Interrupt Mask Register
-#define AT91C_PIOA_IER            (0xFFFFF440) // (PIOA) Interrupt Enable Register
-#define AT91C_PIOA_OWDR           (0xFFFFF4A4) // (PIOA) Output Write Disable Register
-#define AT91C_PIOA_ISR            (0xFFFFF44C) // (PIOA) Interrupt Status Register
-#define AT91C_PIOA_PPUDR          (0xFFFFF460) // (PIOA) Pull-up Disable Register
-#define AT91C_PIOA_MDSR           (0xFFFFF458) // (PIOA) Multi-driver Status Register
-#define AT91C_PIOA_MDER           (0xFFFFF450) // (PIOA) Multi-driver Enable Register
-#define AT91C_PIOA_PER            (0xFFFFF400) // (PIOA) PIO Enable Register
-#define AT91C_PIOA_PSR            (0xFFFFF408) // (PIOA) PIO Status Register
-#define AT91C_PIOA_OER            (0xFFFFF410) // (PIOA) Output Enable Register
-#define AT91C_PIOA_BSR            (0xFFFFF474) // (PIOA) Select B Register
-#define AT91C_PIOA_PPUER          (0xFFFFF464) // (PIOA) Pull-up Enable Register
-#define AT91C_PIOA_MDDR           (0xFFFFF454) // (PIOA) Multi-driver Disable Register
-#define AT91C_PIOA_PDR            (0xFFFFF404) // (PIOA) PIO Disable Register
-#define AT91C_PIOA_ODR            (0xFFFFF414) // (PIOA) Output Disable Registerr
-#define AT91C_PIOA_IFDR           (0xFFFFF424) // (PIOA) Input Filter Disable Register
-#define AT91C_PIOA_ABSR           (0xFFFFF478) // (PIOA) AB Select Status Register
-#define AT91C_PIOA_ASR            (0xFFFFF470) // (PIOA) Select A Register
-#define AT91C_PIOA_PPUSR          (0xFFFFF468) // (PIOA) Pad Pull-up Status Register
-#define AT91C_PIOA_ODSR           (0xFFFFF438) // (PIOA) Output Data Status Register
-#define AT91C_PIOA_SODR           (0xFFFFF430) // (PIOA) Set Output Data Register
-#define AT91C_PIOA_IFSR           (0xFFFFF428) // (PIOA) Input Filter Status Register
-#define AT91C_PIOA_IFER           (0xFFFFF420) // (PIOA) Input Filter Enable Register
-#define AT91C_PIOA_OSR            (0xFFFFF418) // (PIOA) Output Status Register
-#define AT91C_PIOA_IDR            (0xFFFFF444) // (PIOA) Interrupt Disable Register
-#define AT91C_PIOA_PDSR           (0xFFFFF43C) // (PIOA) Pin Data Status Register
-#define AT91C_PIOA_CODR           (0xFFFFF434) // (PIOA) Clear Output Data Register
-#define AT91C_PIOA_OWSR           (0xFFFFF4A8) // (PIOA) Output Write Status Register
-#define AT91C_PIOA_OWER           (0xFFFFF4A0) // (PIOA) Output Write Enable Register
-// ========== Register definition for CKGR peripheral ==========
-#define AT91C_CKGR_PLLR           (0xFFFFFC2C) // (CKGR) PLL Register
-#define AT91C_CKGR_MCFR           (0xFFFFFC24) // (CKGR) Main Clock  Frequency Register
-#define AT91C_CKGR_MOR            (0xFFFFFC20) // (CKGR) Main Oscillator Register
-// ========== Register definition for PMC peripheral ==========
-#define AT91C_PMC_SCSR            (0xFFFFFC08) // (PMC) System Clock Status Register
-#define AT91C_PMC_SCER            (0xFFFFFC00) // (PMC) System Clock Enable Register
-#define AT91C_PMC_IMR             (0xFFFFFC6C) // (PMC) Interrupt Mask Register
-#define AT91C_PMC_IDR             (0xFFFFFC64) // (PMC) Interrupt Disable Register
-#define AT91C_PMC_PCDR            (0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
-#define AT91C_PMC_SCDR            (0xFFFFFC04) // (PMC) System Clock Disable Register
-#define AT91C_PMC_SR              (0xFFFFFC68) // (PMC) Status Register
-#define AT91C_PMC_IER             (0xFFFFFC60) // (PMC) Interrupt Enable Register
-#define AT91C_PMC_MCKR            (0xFFFFFC30) // (PMC) Master Clock Register
-#define AT91C_PMC_MOR             (0xFFFFFC20) // (PMC) Main Oscillator Register
-#define AT91C_PMC_PCER            (0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
-#define AT91C_PMC_PCSR            (0xFFFFFC18) // (PMC) Peripheral Clock Status Register
-#define AT91C_PMC_PLLR            (0xFFFFFC2C) // (PMC) PLL Register
-#define AT91C_PMC_MCFR            (0xFFFFFC24) // (PMC) Main Clock  Frequency Register
-#define AT91C_PMC_PCKR            (0xFFFFFC40) // (PMC) Programmable Clock Register
-// ========== Register definition for RSTC peripheral ==========
-#define AT91C_RSTC_RSR            (0xFFFFFD04) // (RSTC) Reset Status Register
-#define AT91C_RSTC_RMR            (0xFFFFFD08) // (RSTC) Reset Mode Register
-#define AT91C_RSTC_RCR            (0xFFFFFD00) // (RSTC) Reset Control Register
-// ========== Register definition for RTTC peripheral ==========
-#define AT91C_RTTC_RTSR           (0xFFFFFD2C) // (RTTC) Real-time Status Register
-#define AT91C_RTTC_RTAR           (0xFFFFFD24) // (RTTC) Real-time Alarm Register
-#define AT91C_RTTC_RTVR           (0xFFFFFD28) // (RTTC) Real-time Value Register
-#define AT91C_RTTC_RTMR           (0xFFFFFD20) // (RTTC) Real-time Mode Register
-// ========== Register definition for PITC peripheral ==========
-#define AT91C_PITC_PIIR           (0xFFFFFD3C) // (PITC) Period Interval Image Register
-#define AT91C_PITC_PISR           (0xFFFFFD34) // (PITC) Period Interval Status Register
-#define AT91C_PITC_PIVR           (0xFFFFFD38) // (PITC) Period Interval Value Register
-#define AT91C_PITC_PIMR           (0xFFFFFD30) // (PITC) Period Interval Mode Register
-// ========== Register definition for WDTC peripheral ==========
-#define AT91C_WDTC_WDMR           (0xFFFFFD44) // (WDTC) Watchdog Mode Register
-#define AT91C_WDTC_WDSR           (0xFFFFFD48) // (WDTC) Watchdog Status Register
-#define AT91C_WDTC_WDCR           (0xFFFFFD40) // (WDTC) Watchdog Control Register
-// ========== Register definition for MC peripheral ==========
-#define AT91C_MC_FCR              (0xFFFFFF64) // (MC) MC Flash Command Register
-#define AT91C_MC_ASR              (0xFFFFFF04) // (MC) MC Abort Status Register
-#define AT91C_MC_FSR              (0xFFFFFF68) // (MC) MC Flash Status Register
-#define AT91C_MC_FMR              (0xFFFFFF60) // (MC) MC Flash Mode Register
-#define AT91C_MC_AASR             (0xFFFFFF08) // (MC) MC Abort Address Status Register
-#define AT91C_MC_RCR              (0xFFFFFF00) // (MC) MC Remap Control Register
-// ========== Register definition for PDC_SPI peripheral ==========
-#define AT91C_SPI_PTCR            (0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register
-#define AT91C_SPI_TNPR            (0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register
-#define AT91C_SPI_RNPR            (0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register
-#define AT91C_SPI_TPR             (0xFFFE0108) // (PDC_SPI) Transmit Pointer Register
-#define AT91C_SPI_RPR             (0xFFFE0100) // (PDC_SPI) Receive Pointer Register
-#define AT91C_SPI_PTSR            (0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register
-#define AT91C_SPI_TNCR            (0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register
-#define AT91C_SPI_RNCR            (0xFFFE0114) // (PDC_SPI) Receive Next Counter Register
-#define AT91C_SPI_TCR             (0xFFFE010C) // (PDC_SPI) Transmit Counter Register
-#define AT91C_SPI_RCR             (0xFFFE0104) // (PDC_SPI) Receive Counter Register
-// ========== Register definition for SPI peripheral ==========
-#define AT91C_SPI_CSR             (0xFFFE0030) // (SPI) Chip Select Register
-#define AT91C_SPI_IDR             (0xFFFE0018) // (SPI) Interrupt Disable Register
-#define AT91C_SPI_SR              (0xFFFE0010) // (SPI) Status Register
-#define AT91C_SPI_RDR             (0xFFFE0008) // (SPI) Receive Data Register
-#define AT91C_SPI_CR              (0xFFFE0000) // (SPI) Control Register
-#define AT91C_SPI_IMR             (0xFFFE001C) // (SPI) Interrupt Mask Register
-#define AT91C_SPI_IER             (0xFFFE0014) // (SPI) Interrupt Enable Register
-#define AT91C_SPI_TDR             (0xFFFE000C) // (SPI) Transmit Data Register
-#define AT91C_SPI_MR              (0xFFFE0004) // (SPI) Mode Register
-// ========== Register definition for PDC_ADC peripheral ==========
-#define AT91C_ADC_PTCR            (0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
-#define AT91C_ADC_TNPR            (0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
-#define AT91C_ADC_RNPR            (0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
-#define AT91C_ADC_TPR             (0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
-#define AT91C_ADC_RPR             (0xFFFD8100) // (PDC_ADC) Receive Pointer Register
-#define AT91C_ADC_PTSR            (0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
-#define AT91C_ADC_TNCR            (0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
-#define AT91C_ADC_RNCR            (0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
-#define AT91C_ADC_TCR             (0xFFFD810C) // (PDC_ADC) Transmit Counter Register
-#define AT91C_ADC_RCR             (0xFFFD8104) // (PDC_ADC) Receive Counter Register
-// ========== Register definition for ADC peripheral ==========
-#define AT91C_ADC_IMR             (0xFFFD802C) // (ADC) ADC Interrupt Mask Register
-#define AT91C_ADC_CDR4            (0xFFFD8040) // (ADC) ADC Channel Data Register 4
-#define AT91C_ADC_CDR2            (0xFFFD8038) // (ADC) ADC Channel Data Register 2
-#define AT91C_ADC_CDR0            (0xFFFD8030) // (ADC) ADC Channel Data Register 0
-#define AT91C_ADC_CDR7            (0xFFFD804C) // (ADC) ADC Channel Data Register 7
-#define AT91C_ADC_CDR1            (0xFFFD8034) // (ADC) ADC Channel Data Register 1
-#define AT91C_ADC_CDR3            (0xFFFD803C) // (ADC) ADC Channel Data Register 3
-#define AT91C_ADC_CDR5            (0xFFFD8044) // (ADC) ADC Channel Data Register 5
-#define AT91C_ADC_MR              (0xFFFD8004) // (ADC) ADC Mode Register
-#define AT91C_ADC_CDR6            (0xFFFD8048) // (ADC) ADC Channel Data Register 6
-#define AT91C_ADC_CR              (0xFFFD8000) // (ADC) ADC Control Register
-#define AT91C_ADC_CHER            (0xFFFD8010) // (ADC) ADC Channel Enable Register
-#define AT91C_ADC_CHSR            (0xFFFD8018) // (ADC) ADC Channel Status Register
-#define AT91C_ADC_IER             (0xFFFD8024) // (ADC) ADC Interrupt Enable Register
-#define AT91C_ADC_SR              (0xFFFD801C) // (ADC) ADC Status Register
-#define AT91C_ADC_CHDR            (0xFFFD8014) // (ADC) ADC Channel Disable Register
-#define AT91C_ADC_IDR             (0xFFFD8028) // (ADC) ADC Interrupt Disable Register
-#define AT91C_ADC_LCDR            (0xFFFD8020) // (ADC) ADC Last Converted Data Register
-// ========== Register definition for PDC_SSC peripheral ==========
-#define AT91C_SSC_PTCR            (0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
-#define AT91C_SSC_TNPR            (0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
-#define AT91C_SSC_RNPR            (0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
-#define AT91C_SSC_TPR             (0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
-#define AT91C_SSC_RPR             (0xFFFD4100) // (PDC_SSC) Receive Pointer Register
-#define AT91C_SSC_PTSR            (0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
-#define AT91C_SSC_TNCR            (0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
-#define AT91C_SSC_RNCR            (0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
-#define AT91C_SSC_TCR             (0xFFFD410C) // (PDC_SSC) Transmit Counter Register
-#define AT91C_SSC_RCR             (0xFFFD4104) // (PDC_SSC) Receive Counter Register
-// ========== Register definition for SSC peripheral ==========
-#define AT91C_SSC_RFMR            (0xFFFD4014) // (SSC) Receive Frame Mode Register
-#define AT91C_SSC_CMR             (0xFFFD4004) // (SSC) Clock Mode Register
-#define AT91C_SSC_IDR             (0xFFFD4048) // (SSC) Interrupt Disable Register
-#define AT91C_SSC_SR              (0xFFFD4040) // (SSC) Status Register
-#define AT91C_SSC_RC0R            (0xFFFD4038) // (SSC) Receive Compare 0 Register
-#define AT91C_SSC_RSHR            (0xFFFD4030) // (SSC) Receive Sync Holding Register
-#define AT91C_SSC_RHR             (0xFFFD4020) // (SSC) Receive Holding Register
-#define AT91C_SSC_TCMR            (0xFFFD4018) // (SSC) Transmit Clock Mode Register
-#define AT91C_SSC_RCMR            (0xFFFD4010) // (SSC) Receive Clock ModeRegister
-#define AT91C_SSC_CR              (0xFFFD4000) // (SSC) Control Register
-#define AT91C_SSC_IMR             (0xFFFD404C) // (SSC) Interrupt Mask Register
-#define AT91C_SSC_IER             (0xFFFD4044) // (SSC) Interrupt Enable Register
-#define AT91C_SSC_RC1R            (0xFFFD403C) // (SSC) Receive Compare 1 Register
-#define AT91C_SSC_TSHR            (0xFFFD4034) // (SSC) Transmit Sync Holding Register
-#define AT91C_SSC_THR             (0xFFFD4024) // (SSC) Transmit Holding Register
-#define AT91C_SSC_TFMR            (0xFFFD401C) // (SSC) Transmit Frame Mode Register
-// ========== Register definition for PDC_US1 peripheral ==========
-#define AT91C_US1_PTSR            (0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
-#define AT91C_US1_TNCR            (0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
-#define AT91C_US1_RNCR            (0xFFFC4114) // (PDC_US1) Receive Next Counter Register
-#define AT91C_US1_TCR             (0xFFFC410C) // (PDC_US1) Transmit Counter Register
-#define AT91C_US1_RCR             (0xFFFC4104) // (PDC_US1) Receive Counter Register
-#define AT91C_US1_PTCR            (0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
-#define AT91C_US1_TNPR            (0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
-#define AT91C_US1_RNPR            (0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
-#define AT91C_US1_TPR             (0xFFFC4108) // (PDC_US1) Transmit Pointer Register
-#define AT91C_US1_RPR             (0xFFFC4100) // (PDC_US1) Receive Pointer Register
-// ========== Register definition for US1 peripheral ==========
-#define AT91C_US1_XXR             (0xFFFC4048) // (US1) XON_XOFF Register
-#define AT91C_US1_RHR             (0xFFFC4018) // (US1) Receiver Holding Register
-#define AT91C_US1_IMR             (0xFFFC4010) // (US1) Interrupt Mask Register
-#define AT91C_US1_IER             (0xFFFC4008) // (US1) Interrupt Enable Register
-#define AT91C_US1_CR              (0xFFFC4000) // (US1) Control Register
-#define AT91C_US1_RTOR            (0xFFFC4024) // (US1) Receiver Time-out Register
-#define AT91C_US1_THR             (0xFFFC401C) // (US1) Transmitter Holding Register
-#define AT91C_US1_CSR             (0xFFFC4014) // (US1) Channel Status Register
-#define AT91C_US1_IDR             (0xFFFC400C) // (US1) Interrupt Disable Register
-#define AT91C_US1_FIDI            (0xFFFC4040) // (US1) FI_DI_Ratio Register
-#define AT91C_US1_BRGR            (0xFFFC4020) // (US1) Baud Rate Generator Register
-#define AT91C_US1_TTGR            (0xFFFC4028) // (US1) Transmitter Time-guard Register
-#define AT91C_US1_IF              (0xFFFC404C) // (US1) IRDA_FILTER Register
-#define AT91C_US1_NER             (0xFFFC4044) // (US1) Nb Errors Register
-#define AT91C_US1_MR              (0xFFFC4004) // (US1) Mode Register
-// ========== Register definition for PDC_US0 peripheral ==========
-#define AT91C_US0_PTCR            (0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
-#define AT91C_US0_TNPR            (0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
-#define AT91C_US0_RNPR            (0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
-#define AT91C_US0_TPR             (0xFFFC0108) // (PDC_US0) Transmit Pointer Register
-#define AT91C_US0_RPR             (0xFFFC0100) // (PDC_US0) Receive Pointer Register
-#define AT91C_US0_PTSR            (0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
-#define AT91C_US0_TNCR            (0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
-#define AT91C_US0_RNCR            (0xFFFC0114) // (PDC_US0) Receive Next Counter Register
-#define AT91C_US0_TCR             (0xFFFC010C) // (PDC_US0) Transmit Counter Register
-#define AT91C_US0_RCR             (0xFFFC0104) // (PDC_US0) Receive Counter Register
-// ========== Register definition for US0 peripheral ==========
-#define AT91C_US0_TTGR            (0xFFFC0028) // (US0) Transmitter Time-guard Register
-#define AT91C_US0_BRGR            (0xFFFC0020) // (US0) Baud Rate Generator Register
-#define AT91C_US0_RHR             (0xFFFC0018) // (US0) Receiver Holding Register
-#define AT91C_US0_IMR             (0xFFFC0010) // (US0) Interrupt Mask Register
-#define AT91C_US0_NER             (0xFFFC0044) // (US0) Nb Errors Register
-#define AT91C_US0_RTOR            (0xFFFC0024) // (US0) Receiver Time-out Register
-#define AT91C_US0_XXR             (0xFFFC0048) // (US0) XON_XOFF Register
-#define AT91C_US0_FIDI            (0xFFFC0040) // (US0) FI_DI_Ratio Register
-#define AT91C_US0_CR              (0xFFFC0000) // (US0) Control Register
-#define AT91C_US0_IER             (0xFFFC0008) // (US0) Interrupt Enable Register
-#define AT91C_US0_IF              (0xFFFC004C) // (US0) IRDA_FILTER Register
-#define AT91C_US0_MR              (0xFFFC0004) // (US0) Mode Register
-#define AT91C_US0_IDR             (0xFFFC000C) // (US0) Interrupt Disable Register
-#define AT91C_US0_CSR             (0xFFFC0014) // (US0) Channel Status Register
-#define AT91C_US0_THR             (0xFFFC001C) // (US0) Transmitter Holding Register
-// ========== Register definition for TWI peripheral ==========
-#define AT91C_TWI_RHR             (0xFFFB8030) // (TWI) Receive Holding Register
-#define AT91C_TWI_IDR             (0xFFFB8028) // (TWI) Interrupt Disable Register
-#define AT91C_TWI_SR              (0xFFFB8020) // (TWI) Status Register
-#define AT91C_TWI_CWGR            (0xFFFB8010) // (TWI) Clock Waveform Generator Register
-#define AT91C_TWI_SMR             (0xFFFB8008) // (TWI) Slave Mode Register
-#define AT91C_TWI_CR              (0xFFFB8000) // (TWI) Control Register
-#define AT91C_TWI_THR             (0xFFFB8034) // (TWI) Transmit Holding Register
-#define AT91C_TWI_IMR             (0xFFFB802C) // (TWI) Interrupt Mask Register
-#define AT91C_TWI_IER             (0xFFFB8024) // (TWI) Interrupt Enable Register
-#define AT91C_TWI_IADR            (0xFFFB800C) // (TWI) Internal Address Register
-#define AT91C_TWI_MMR             (0xFFFB8004) // (TWI) Master Mode Register
-// ========== Register definition for TC2 peripheral ==========
-#define AT91C_TC2_IMR             (0xFFFA00AC) // (TC2) Interrupt Mask Register
-#define AT91C_TC2_IER             (0xFFFA00A4) // (TC2) Interrupt Enable Register
-#define AT91C_TC2_RC              (0xFFFA009C) // (TC2) Register C
-#define AT91C_TC2_RA              (0xFFFA0094) // (TC2) Register A
-#define AT91C_TC2_CMR             (0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC2_IDR             (0xFFFA00A8) // (TC2) Interrupt Disable Register
-#define AT91C_TC2_SR              (0xFFFA00A0) // (TC2) Status Register
-#define AT91C_TC2_RB              (0xFFFA0098) // (TC2) Register B
-#define AT91C_TC2_CV              (0xFFFA0090) // (TC2) Counter Value
-#define AT91C_TC2_CCR             (0xFFFA0080) // (TC2) Channel Control Register
-// ========== Register definition for TC1 peripheral ==========
-#define AT91C_TC1_IMR             (0xFFFA006C) // (TC1) Interrupt Mask Register
-#define AT91C_TC1_IER             (0xFFFA0064) // (TC1) Interrupt Enable Register
-#define AT91C_TC1_RC              (0xFFFA005C) // (TC1) Register C
-#define AT91C_TC1_RA              (0xFFFA0054) // (TC1) Register A
-#define AT91C_TC1_CMR             (0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC1_IDR             (0xFFFA0068) // (TC1) Interrupt Disable Register
-#define AT91C_TC1_SR              (0xFFFA0060) // (TC1) Status Register
-#define AT91C_TC1_RB              (0xFFFA0058) // (TC1) Register B
-#define AT91C_TC1_CV              (0xFFFA0050) // (TC1) Counter Value
-#define AT91C_TC1_CCR             (0xFFFA0040) // (TC1) Channel Control Register
-// ========== Register definition for TC0 peripheral ==========
-#define AT91C_TC0_IMR             (0xFFFA002C) // (TC0) Interrupt Mask Register
-#define AT91C_TC0_IER             (0xFFFA0024) // (TC0) Interrupt Enable Register
-#define AT91C_TC0_RC              (0xFFFA001C) // (TC0) Register C
-#define AT91C_TC0_RA              (0xFFFA0014) // (TC0) Register A
-#define AT91C_TC0_CMR             (0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC0_IDR             (0xFFFA0028) // (TC0) Interrupt Disable Register
-#define AT91C_TC0_SR              (0xFFFA0020) // (TC0) Status Register
-#define AT91C_TC0_RB              (0xFFFA0018) // (TC0) Register B
-#define AT91C_TC0_CV              (0xFFFA0010) // (TC0) Counter Value
-#define AT91C_TC0_CCR             (0xFFFA0000) // (TC0) Channel Control Register
-// ========== Register definition for TCB peripheral ==========
-#define AT91C_TCB_BMR             (0xFFFA00C4) // (TCB) TC Block Mode Register
-#define AT91C_TCB_BCR             (0xFFFA00C0) // (TCB) TC Block Control Register
-// ========== Register definition for PWMC_CH3 peripheral ==========
-#define AT91C_CH3_CUPDR           (0xFFFCC270) // (PWMC_CH3) Channel Update Register
-#define AT91C_CH3_CPRDR           (0xFFFCC268) // (PWMC_CH3) Channel Period Register
-#define AT91C_CH3_CMR             (0xFFFCC260) // (PWMC_CH3) Channel Mode Register
-#define AT91C_CH3_Reserved        (0xFFFCC274) // (PWMC_CH3) Reserved
-#define AT91C_CH3_CCNTR           (0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
-#define AT91C_CH3_CDTYR           (0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
-// ========== Register definition for PWMC_CH2 peripheral ==========
-#define AT91C_CH2_CUPDR           (0xFFFCC250) // (PWMC_CH2) Channel Update Register
-#define AT91C_CH2_CPRDR           (0xFFFCC248) // (PWMC_CH2) Channel Period Register
-#define AT91C_CH2_CMR             (0xFFFCC240) // (PWMC_CH2) Channel Mode Register
-#define AT91C_CH2_Reserved        (0xFFFCC254) // (PWMC_CH2) Reserved
-#define AT91C_CH2_CCNTR           (0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
-#define AT91C_CH2_CDTYR           (0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
-// ========== Register definition for PWMC_CH1 peripheral ==========
-#define AT91C_CH1_CUPDR           (0xFFFCC230) // (PWMC_CH1) Channel Update Register
-#define AT91C_CH1_CPRDR           (0xFFFCC228) // (PWMC_CH1) Channel Period Register
-#define AT91C_CH1_CMR             (0xFFFCC220) // (PWMC_CH1) Channel Mode Register
-#define AT91C_CH1_Reserved        (0xFFFCC234) // (PWMC_CH1) Reserved
-#define AT91C_CH1_CCNTR           (0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
-#define AT91C_CH1_CDTYR           (0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
-// ========== Register definition for PWMC_CH0 peripheral ==========
-#define AT91C_CH0_CUPDR           (0xFFFCC210) // (PWMC_CH0) Channel Update Register
-#define AT91C_CH0_CPRDR           (0xFFFCC208) // (PWMC_CH0) Channel Period Register
-#define AT91C_CH0_CMR             (0xFFFCC200) // (PWMC_CH0) Channel Mode Register
-#define AT91C_CH0_Reserved        (0xFFFCC214) // (PWMC_CH0) Reserved
-#define AT91C_CH0_CCNTR           (0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
-#define AT91C_CH0_CDTYR           (0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
-// ========== Register definition for PWMC peripheral ==========
-#define AT91C_PWMC_VR             (0xFFFCC0FC) // (PWMC) PWMC Version Register
-#define AT91C_PWMC_ISR            (0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
-#define AT91C_PWMC_IDR            (0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
-#define AT91C_PWMC_SR             (0xFFFCC00C) // (PWMC) PWMC Status Register
-#define AT91C_PWMC_ENA            (0xFFFCC004) // (PWMC) PWMC Enable Register
-#define AT91C_PWMC_IMR            (0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
-#define AT91C_PWMC_MR             (0xFFFCC000) // (PWMC) PWMC Mode Register
-#define AT91C_PWMC_DIS            (0xFFFCC008) // (PWMC) PWMC Disable Register
-#define AT91C_PWMC_IER            (0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
-// ========== Register definition for UDP peripheral ==========
-#define AT91C_UDP_ISR             (0xFFFB001C) // (UDP) Interrupt Status Register
-#define AT91C_UDP_IDR             (0xFFFB0014) // (UDP) Interrupt Disable Register
-#define AT91C_UDP_GLBSTATE        (0xFFFB0004) // (UDP) Global State Register
-#define AT91C_UDP_FDR             (0xFFFB0050) // (UDP) Endpoint FIFO Data Register
-#define AT91C_UDP_CSR             (0xFFFB0030) // (UDP) Endpoint Control and Status Register
-#define AT91C_UDP_RSTEP           (0xFFFB0028) // (UDP) Reset Endpoint Register
-#define AT91C_UDP_ICR             (0xFFFB0020) // (UDP) Interrupt Clear Register
-#define AT91C_UDP_IMR             (0xFFFB0018) // (UDP) Interrupt Mask Register
-#define AT91C_UDP_IER             (0xFFFB0010) // (UDP) Interrupt Enable Register
-#define AT91C_UDP_FADDR           (0xFFFB0008) // (UDP) Function Address Register
-#define AT91C_UDP_NUM             (0xFFFB0000) // (UDP) Frame Number Register
+/* ***************************************************************************** */
+/*               REGISTER ADDRESS DEFINITION FOR AT91SAM7S64 */
+/* ***************************************************************************** */
+/* ========== Register definition for SYSC peripheral ========== */
+#define AT91C_SYSC_SYSC_VRPM    ( 0xFFFFFD60 ) /* (SYSC) Voltage Regulator Power Mode Register */
+/* ========== Register definition for AIC peripheral ========== */
+#define AT91C_AIC_ICCR          ( 0xFFFFF128 ) /* (AIC) Interrupt Clear Command Register */
+#define AT91C_AIC_IECR          ( 0xFFFFF120 ) /* (AIC) Interrupt Enable Command Register */
+#define AT91C_AIC_SMR           ( 0xFFFFF000 ) /* (AIC) Source Mode Register */
+#define AT91C_AIC_ISCR          ( 0xFFFFF12C ) /* (AIC) Interrupt Set Command Register */
+#define AT91C_AIC_EOICR         ( 0xFFFFF130 ) /* (AIC) End of Interrupt Command Register */
+#define AT91C_AIC_DCR           ( 0xFFFFF138 ) /* (AIC) Debug Control Register (Protect) */
+#define AT91C_AIC_FFER          ( 0xFFFFF140 ) /* (AIC) Fast Forcing Enable Register */
+#define AT91C_AIC_SVR           ( 0xFFFFF080 ) /* (AIC) Source Vector Register */
+#define AT91C_AIC_SPU           ( 0xFFFFF134 ) /* (AIC) Spurious Vector Register */
+#define AT91C_AIC_FFDR          ( 0xFFFFF144 ) /* (AIC) Fast Forcing Disable Register */
+#define AT91C_AIC_FVR           ( 0xFFFFF104 ) /* (AIC) FIQ Vector Register */
+#define AT91C_AIC_FFSR          ( 0xFFFFF148 ) /* (AIC) Fast Forcing Status Register */
+#define AT91C_AIC_IMR           ( 0xFFFFF110 ) /* (AIC) Interrupt Mask Register */
+#define AT91C_AIC_ISR           ( 0xFFFFF108 ) /* (AIC) Interrupt Status Register */
+#define AT91C_AIC_IVR           ( 0xFFFFF100 ) /* (AIC) IRQ Vector Register */
+#define AT91C_AIC_IDCR          ( 0xFFFFF124 ) /* (AIC) Interrupt Disable Command Register */
+#define AT91C_AIC_CISR          ( 0xFFFFF114 ) /* (AIC) Core Interrupt Status Register */
+#define AT91C_AIC_IPR           ( 0xFFFFF10C ) /* (AIC) Interrupt Pending Register */
+/* ========== Register definition for DBGU peripheral ========== */
+#define AT91C_DBGU_C2R          ( 0xFFFFF244 ) /* (DBGU) Chip ID2 Register */
+#define AT91C_DBGU_THR          ( 0xFFFFF21C ) /* (DBGU) Transmitter Holding Register */
+#define AT91C_DBGU_CSR          ( 0xFFFFF214 ) /* (DBGU) Channel Status Register */
+#define AT91C_DBGU_IDR          ( 0xFFFFF20C ) /* (DBGU) Interrupt Disable Register */
+#define AT91C_DBGU_MR           ( 0xFFFFF204 ) /* (DBGU) Mode Register */
+#define AT91C_DBGU_FNTR         ( 0xFFFFF248 ) /* (DBGU) Force NTRST Register */
+#define AT91C_DBGU_C1R          ( 0xFFFFF240 ) /* (DBGU) Chip ID1 Register */
+#define AT91C_DBGU_BRGR         ( 0xFFFFF220 ) /* (DBGU) Baud Rate Generator Register */
+#define AT91C_DBGU_RHR          ( 0xFFFFF218 ) /* (DBGU) Receiver Holding Register */
+#define AT91C_DBGU_IMR          ( 0xFFFFF210 ) /* (DBGU) Interrupt Mask Register */
+#define AT91C_DBGU_IER          ( 0xFFFFF208 ) /* (DBGU) Interrupt Enable Register */
+#define AT91C_DBGU_CR           ( 0xFFFFF200 ) /* (DBGU) Control Register */
+/* ========== Register definition for PDC_DBGU peripheral ========== */
+#define AT91C_DBGU_TNCR         ( 0xFFFFF31C ) /* (PDC_DBGU) Transmit Next Counter Register */
+#define AT91C_DBGU_RNCR         ( 0xFFFFF314 ) /* (PDC_DBGU) Receive Next Counter Register */
+#define AT91C_DBGU_PTCR         ( 0xFFFFF320 ) /* (PDC_DBGU) PDC Transfer Control Register */
+#define AT91C_DBGU_PTSR         ( 0xFFFFF324 ) /* (PDC_DBGU) PDC Transfer Status Register */
+#define AT91C_DBGU_RCR          ( 0xFFFFF304 ) /* (PDC_DBGU) Receive Counter Register */
+#define AT91C_DBGU_TCR          ( 0xFFFFF30C ) /* (PDC_DBGU) Transmit Counter Register */
+#define AT91C_DBGU_RPR          ( 0xFFFFF300 ) /* (PDC_DBGU) Receive Pointer Register */
+#define AT91C_DBGU_TPR          ( 0xFFFFF308 ) /* (PDC_DBGU) Transmit Pointer Register */
+#define AT91C_DBGU_RNPR         ( 0xFFFFF310 ) /* (PDC_DBGU) Receive Next Pointer Register */
+#define AT91C_DBGU_TNPR         ( 0xFFFFF318 ) /* (PDC_DBGU) Transmit Next Pointer Register */
+/* ========== Register definition for PIOA peripheral ========== */
+#define AT91C_PIOA_IMR          ( 0xFFFFF448 ) /* (PIOA) Interrupt Mask Register */
+#define AT91C_PIOA_IER          ( 0xFFFFF440 ) /* (PIOA) Interrupt Enable Register */
+#define AT91C_PIOA_OWDR         ( 0xFFFFF4A4 ) /* (PIOA) Output Write Disable Register */
+#define AT91C_PIOA_ISR          ( 0xFFFFF44C ) /* (PIOA) Interrupt Status Register */
+#define AT91C_PIOA_PPUDR        ( 0xFFFFF460 ) /* (PIOA) Pull-up Disable Register */
+#define AT91C_PIOA_MDSR         ( 0xFFFFF458 ) /* (PIOA) Multi-driver Status Register */
+#define AT91C_PIOA_MDER         ( 0xFFFFF450 ) /* (PIOA) Multi-driver Enable Register */
+#define AT91C_PIOA_PER          ( 0xFFFFF400 ) /* (PIOA) PIO Enable Register */
+#define AT91C_PIOA_PSR          ( 0xFFFFF408 ) /* (PIOA) PIO Status Register */
+#define AT91C_PIOA_OER          ( 0xFFFFF410 ) /* (PIOA) Output Enable Register */
+#define AT91C_PIOA_BSR          ( 0xFFFFF474 ) /* (PIOA) Select B Register */
+#define AT91C_PIOA_PPUER        ( 0xFFFFF464 ) /* (PIOA) Pull-up Enable Register */
+#define AT91C_PIOA_MDDR         ( 0xFFFFF454 ) /* (PIOA) Multi-driver Disable Register */
+#define AT91C_PIOA_PDR          ( 0xFFFFF404 ) /* (PIOA) PIO Disable Register */
+#define AT91C_PIOA_ODR          ( 0xFFFFF414 ) /* (PIOA) Output Disable Registerr */
+#define AT91C_PIOA_IFDR         ( 0xFFFFF424 ) /* (PIOA) Input Filter Disable Register */
+#define AT91C_PIOA_ABSR         ( 0xFFFFF478 ) /* (PIOA) AB Select Status Register */
+#define AT91C_PIOA_ASR          ( 0xFFFFF470 ) /* (PIOA) Select A Register */
+#define AT91C_PIOA_PPUSR        ( 0xFFFFF468 ) /* (PIOA) Pad Pull-up Status Register */
+#define AT91C_PIOA_ODSR         ( 0xFFFFF438 ) /* (PIOA) Output Data Status Register */
+#define AT91C_PIOA_SODR         ( 0xFFFFF430 ) /* (PIOA) Set Output Data Register */
+#define AT91C_PIOA_IFSR         ( 0xFFFFF428 ) /* (PIOA) Input Filter Status Register */
+#define AT91C_PIOA_IFER         ( 0xFFFFF420 ) /* (PIOA) Input Filter Enable Register */
+#define AT91C_PIOA_OSR          ( 0xFFFFF418 ) /* (PIOA) Output Status Register */
+#define AT91C_PIOA_IDR          ( 0xFFFFF444 ) /* (PIOA) Interrupt Disable Register */
+#define AT91C_PIOA_PDSR         ( 0xFFFFF43C ) /* (PIOA) Pin Data Status Register */
+#define AT91C_PIOA_CODR         ( 0xFFFFF434 ) /* (PIOA) Clear Output Data Register */
+#define AT91C_PIOA_OWSR         ( 0xFFFFF4A8 ) /* (PIOA) Output Write Status Register */
+#define AT91C_PIOA_OWER         ( 0xFFFFF4A0 ) /* (PIOA) Output Write Enable Register */
+/* ========== Register definition for CKGR peripheral ========== */
+#define AT91C_CKGR_PLLR         ( 0xFFFFFC2C ) /* (CKGR) PLL Register */
+#define AT91C_CKGR_MCFR         ( 0xFFFFFC24 ) /* (CKGR) Main Clock  Frequency Register */
+#define AT91C_CKGR_MOR          ( 0xFFFFFC20 ) /* (CKGR) Main Oscillator Register */
+/* ========== Register definition for PMC peripheral ========== */
+#define AT91C_PMC_SCSR          ( 0xFFFFFC08 ) /* (PMC) System Clock Status Register */
+#define AT91C_PMC_SCER          ( 0xFFFFFC00 ) /* (PMC) System Clock Enable Register */
+#define AT91C_PMC_IMR           ( 0xFFFFFC6C ) /* (PMC) Interrupt Mask Register */
+#define AT91C_PMC_IDR           ( 0xFFFFFC64 ) /* (PMC) Interrupt Disable Register */
+#define AT91C_PMC_PCDR          ( 0xFFFFFC14 ) /* (PMC) Peripheral Clock Disable Register */
+#define AT91C_PMC_SCDR          ( 0xFFFFFC04 ) /* (PMC) System Clock Disable Register */
+#define AT91C_PMC_SR            ( 0xFFFFFC68 ) /* (PMC) Status Register */
+#define AT91C_PMC_IER           ( 0xFFFFFC60 ) /* (PMC) Interrupt Enable Register */
+#define AT91C_PMC_MCKR          ( 0xFFFFFC30 ) /* (PMC) Master Clock Register */
+#define AT91C_PMC_MOR           ( 0xFFFFFC20 ) /* (PMC) Main Oscillator Register */
+#define AT91C_PMC_PCER          ( 0xFFFFFC10 ) /* (PMC) Peripheral Clock Enable Register */
+#define AT91C_PMC_PCSR          ( 0xFFFFFC18 ) /* (PMC) Peripheral Clock Status Register */
+#define AT91C_PMC_PLLR          ( 0xFFFFFC2C ) /* (PMC) PLL Register */
+#define AT91C_PMC_MCFR          ( 0xFFFFFC24 ) /* (PMC) Main Clock  Frequency Register */
+#define AT91C_PMC_PCKR          ( 0xFFFFFC40 ) /* (PMC) Programmable Clock Register */
+/* ========== Register definition for RSTC peripheral ========== */
+#define AT91C_RSTC_RSR          ( 0xFFFFFD04 ) /* (RSTC) Reset Status Register */
+#define AT91C_RSTC_RMR          ( 0xFFFFFD08 ) /* (RSTC) Reset Mode Register */
+#define AT91C_RSTC_RCR          ( 0xFFFFFD00 ) /* (RSTC) Reset Control Register */
+/* ========== Register definition for RTTC peripheral ========== */
+#define AT91C_RTTC_RTSR         ( 0xFFFFFD2C ) /* (RTTC) Real-time Status Register */
+#define AT91C_RTTC_RTAR         ( 0xFFFFFD24 ) /* (RTTC) Real-time Alarm Register */
+#define AT91C_RTTC_RTVR         ( 0xFFFFFD28 ) /* (RTTC) Real-time Value Register */
+#define AT91C_RTTC_RTMR         ( 0xFFFFFD20 ) /* (RTTC) Real-time Mode Register */
+/* ========== Register definition for PITC peripheral ========== */
+#define AT91C_PITC_PIIR         ( 0xFFFFFD3C ) /* (PITC) Period Interval Image Register */
+#define AT91C_PITC_PISR         ( 0xFFFFFD34 ) /* (PITC) Period Interval Status Register */
+#define AT91C_PITC_PIVR         ( 0xFFFFFD38 ) /* (PITC) Period Interval Value Register */
+#define AT91C_PITC_PIMR         ( 0xFFFFFD30 ) /* (PITC) Period Interval Mode Register */
+/* ========== Register definition for WDTC peripheral ========== */
+#define AT91C_WDTC_WDMR         ( 0xFFFFFD44 ) /* (WDTC) Watchdog Mode Register */
+#define AT91C_WDTC_WDSR         ( 0xFFFFFD48 ) /* (WDTC) Watchdog Status Register */
+#define AT91C_WDTC_WDCR         ( 0xFFFFFD40 ) /* (WDTC) Watchdog Control Register */
+/* ========== Register definition for MC peripheral ========== */
+#define AT91C_MC_FCR            ( 0xFFFFFF64 ) /* (MC) MC Flash Command Register */
+#define AT91C_MC_ASR            ( 0xFFFFFF04 ) /* (MC) MC Abort Status Register */
+#define AT91C_MC_FSR            ( 0xFFFFFF68 ) /* (MC) MC Flash Status Register */
+#define AT91C_MC_FMR            ( 0xFFFFFF60 ) /* (MC) MC Flash Mode Register */
+#define AT91C_MC_AASR           ( 0xFFFFFF08 ) /* (MC) MC Abort Address Status Register */
+#define AT91C_MC_RCR            ( 0xFFFFFF00 ) /* (MC) MC Remap Control Register */
+/* ========== Register definition for PDC_SPI peripheral ========== */
+#define AT91C_SPI_PTCR          ( 0xFFFE0120 ) /* (PDC_SPI) PDC Transfer Control Register */
+#define AT91C_SPI_TNPR          ( 0xFFFE0118 ) /* (PDC_SPI) Transmit Next Pointer Register */
+#define AT91C_SPI_RNPR          ( 0xFFFE0110 ) /* (PDC_SPI) Receive Next Pointer Register */
+#define AT91C_SPI_TPR           ( 0xFFFE0108 ) /* (PDC_SPI) Transmit Pointer Register */
+#define AT91C_SPI_RPR           ( 0xFFFE0100 ) /* (PDC_SPI) Receive Pointer Register */
+#define AT91C_SPI_PTSR          ( 0xFFFE0124 ) /* (PDC_SPI) PDC Transfer Status Register */
+#define AT91C_SPI_TNCR          ( 0xFFFE011C ) /* (PDC_SPI) Transmit Next Counter Register */
+#define AT91C_SPI_RNCR          ( 0xFFFE0114 ) /* (PDC_SPI) Receive Next Counter Register */
+#define AT91C_SPI_TCR           ( 0xFFFE010C ) /* (PDC_SPI) Transmit Counter Register */
+#define AT91C_SPI_RCR           ( 0xFFFE0104 ) /* (PDC_SPI) Receive Counter Register */
+/* ========== Register definition for SPI peripheral ========== */
+#define AT91C_SPI_CSR           ( 0xFFFE0030 ) /* (SPI) Chip Select Register */
+#define AT91C_SPI_IDR           ( 0xFFFE0018 ) /* (SPI) Interrupt Disable Register */
+#define AT91C_SPI_SR            ( 0xFFFE0010 ) /* (SPI) Status Register */
+#define AT91C_SPI_RDR           ( 0xFFFE0008 ) /* (SPI) Receive Data Register */
+#define AT91C_SPI_CR            ( 0xFFFE0000 ) /* (SPI) Control Register */
+#define AT91C_SPI_IMR           ( 0xFFFE001C ) /* (SPI) Interrupt Mask Register */
+#define AT91C_SPI_IER           ( 0xFFFE0014 ) /* (SPI) Interrupt Enable Register */
+#define AT91C_SPI_TDR           ( 0xFFFE000C ) /* (SPI) Transmit Data Register */
+#define AT91C_SPI_MR            ( 0xFFFE0004 ) /* (SPI) Mode Register */
+/* ========== Register definition for PDC_ADC peripheral ========== */
+#define AT91C_ADC_PTCR          ( 0xFFFD8120 ) /* (PDC_ADC) PDC Transfer Control Register */
+#define AT91C_ADC_TNPR          ( 0xFFFD8118 ) /* (PDC_ADC) Transmit Next Pointer Register */
+#define AT91C_ADC_RNPR          ( 0xFFFD8110 ) /* (PDC_ADC) Receive Next Pointer Register */
+#define AT91C_ADC_TPR           ( 0xFFFD8108 ) /* (PDC_ADC) Transmit Pointer Register */
+#define AT91C_ADC_RPR           ( 0xFFFD8100 ) /* (PDC_ADC) Receive Pointer Register */
+#define AT91C_ADC_PTSR          ( 0xFFFD8124 ) /* (PDC_ADC) PDC Transfer Status Register */
+#define AT91C_ADC_TNCR          ( 0xFFFD811C ) /* (PDC_ADC) Transmit Next Counter Register */
+#define AT91C_ADC_RNCR          ( 0xFFFD8114 ) /* (PDC_ADC) Receive Next Counter Register */
+#define AT91C_ADC_TCR           ( 0xFFFD810C ) /* (PDC_ADC) Transmit Counter Register */
+#define AT91C_ADC_RCR           ( 0xFFFD8104 ) /* (PDC_ADC) Receive Counter Register */
+/* ========== Register definition for ADC peripheral ========== */
+#define AT91C_ADC_IMR           ( 0xFFFD802C ) /* (ADC) ADC Interrupt Mask Register */
+#define AT91C_ADC_CDR4          ( 0xFFFD8040 ) /* (ADC) ADC Channel Data Register 4 */
+#define AT91C_ADC_CDR2          ( 0xFFFD8038 ) /* (ADC) ADC Channel Data Register 2 */
+#define AT91C_ADC_CDR0          ( 0xFFFD8030 ) /* (ADC) ADC Channel Data Register 0 */
+#define AT91C_ADC_CDR7          ( 0xFFFD804C ) /* (ADC) ADC Channel Data Register 7 */
+#define AT91C_ADC_CDR1          ( 0xFFFD8034 ) /* (ADC) ADC Channel Data Register 1 */
+#define AT91C_ADC_CDR3          ( 0xFFFD803C ) /* (ADC) ADC Channel Data Register 3 */
+#define AT91C_ADC_CDR5          ( 0xFFFD8044 ) /* (ADC) ADC Channel Data Register 5 */
+#define AT91C_ADC_MR            ( 0xFFFD8004 ) /* (ADC) ADC Mode Register */
+#define AT91C_ADC_CDR6          ( 0xFFFD8048 ) /* (ADC) ADC Channel Data Register 6 */
+#define AT91C_ADC_CR            ( 0xFFFD8000 ) /* (ADC) ADC Control Register */
+#define AT91C_ADC_CHER          ( 0xFFFD8010 ) /* (ADC) ADC Channel Enable Register */
+#define AT91C_ADC_CHSR          ( 0xFFFD8018 ) /* (ADC) ADC Channel Status Register */
+#define AT91C_ADC_IER           ( 0xFFFD8024 ) /* (ADC) ADC Interrupt Enable Register */
+#define AT91C_ADC_SR            ( 0xFFFD801C ) /* (ADC) ADC Status Register */
+#define AT91C_ADC_CHDR          ( 0xFFFD8014 ) /* (ADC) ADC Channel Disable Register */
+#define AT91C_ADC_IDR           ( 0xFFFD8028 ) /* (ADC) ADC Interrupt Disable Register */
+#define AT91C_ADC_LCDR          ( 0xFFFD8020 ) /* (ADC) ADC Last Converted Data Register */
+/* ========== Register definition for PDC_SSC peripheral ========== */
+#define AT91C_SSC_PTCR          ( 0xFFFD4120 ) /* (PDC_SSC) PDC Transfer Control Register */
+#define AT91C_SSC_TNPR          ( 0xFFFD4118 ) /* (PDC_SSC) Transmit Next Pointer Register */
+#define AT91C_SSC_RNPR          ( 0xFFFD4110 ) /* (PDC_SSC) Receive Next Pointer Register */
+#define AT91C_SSC_TPR           ( 0xFFFD4108 ) /* (PDC_SSC) Transmit Pointer Register */
+#define AT91C_SSC_RPR           ( 0xFFFD4100 ) /* (PDC_SSC) Receive Pointer Register */
+#define AT91C_SSC_PTSR          ( 0xFFFD4124 ) /* (PDC_SSC) PDC Transfer Status Register */
+#define AT91C_SSC_TNCR          ( 0xFFFD411C ) /* (PDC_SSC) Transmit Next Counter Register */
+#define AT91C_SSC_RNCR          ( 0xFFFD4114 ) /* (PDC_SSC) Receive Next Counter Register */
+#define AT91C_SSC_TCR           ( 0xFFFD410C ) /* (PDC_SSC) Transmit Counter Register */
+#define AT91C_SSC_RCR           ( 0xFFFD4104 ) /* (PDC_SSC) Receive Counter Register */
+/* ========== Register definition for SSC peripheral ========== */
+#define AT91C_SSC_RFMR          ( 0xFFFD4014 ) /* (SSC) Receive Frame Mode Register */
+#define AT91C_SSC_CMR           ( 0xFFFD4004 ) /* (SSC) Clock Mode Register */
+#define AT91C_SSC_IDR           ( 0xFFFD4048 ) /* (SSC) Interrupt Disable Register */
+#define AT91C_SSC_SR            ( 0xFFFD4040 ) /* (SSC) Status Register */
+#define AT91C_SSC_RC0R          ( 0xFFFD4038 ) /* (SSC) Receive Compare 0 Register */
+#define AT91C_SSC_RSHR          ( 0xFFFD4030 ) /* (SSC) Receive Sync Holding Register */
+#define AT91C_SSC_RHR           ( 0xFFFD4020 ) /* (SSC) Receive Holding Register */
+#define AT91C_SSC_TCMR          ( 0xFFFD4018 ) /* (SSC) Transmit Clock Mode Register */
+#define AT91C_SSC_RCMR          ( 0xFFFD4010 ) /* (SSC) Receive Clock ModeRegister */
+#define AT91C_SSC_CR            ( 0xFFFD4000 ) /* (SSC) Control Register */
+#define AT91C_SSC_IMR           ( 0xFFFD404C ) /* (SSC) Interrupt Mask Register */
+#define AT91C_SSC_IER           ( 0xFFFD4044 ) /* (SSC) Interrupt Enable Register */
+#define AT91C_SSC_RC1R          ( 0xFFFD403C ) /* (SSC) Receive Compare 1 Register */
+#define AT91C_SSC_TSHR          ( 0xFFFD4034 ) /* (SSC) Transmit Sync Holding Register */
+#define AT91C_SSC_THR           ( 0xFFFD4024 ) /* (SSC) Transmit Holding Register */
+#define AT91C_SSC_TFMR          ( 0xFFFD401C ) /* (SSC) Transmit Frame Mode Register */
+/* ========== Register definition for PDC_US1 peripheral ========== */
+#define AT91C_US1_PTSR          ( 0xFFFC4124 ) /* (PDC_US1) PDC Transfer Status Register */
+#define AT91C_US1_TNCR          ( 0xFFFC411C ) /* (PDC_US1) Transmit Next Counter Register */
+#define AT91C_US1_RNCR          ( 0xFFFC4114 ) /* (PDC_US1) Receive Next Counter Register */
+#define AT91C_US1_TCR           ( 0xFFFC410C ) /* (PDC_US1) Transmit Counter Register */
+#define AT91C_US1_RCR           ( 0xFFFC4104 ) /* (PDC_US1) Receive Counter Register */
+#define AT91C_US1_PTCR          ( 0xFFFC4120 ) /* (PDC_US1) PDC Transfer Control Register */
+#define AT91C_US1_TNPR          ( 0xFFFC4118 ) /* (PDC_US1) Transmit Next Pointer Register */
+#define AT91C_US1_RNPR          ( 0xFFFC4110 ) /* (PDC_US1) Receive Next Pointer Register */
+#define AT91C_US1_TPR           ( 0xFFFC4108 ) /* (PDC_US1) Transmit Pointer Register */
+#define AT91C_US1_RPR           ( 0xFFFC4100 ) /* (PDC_US1) Receive Pointer Register */
+/* ========== Register definition for US1 peripheral ========== */
+#define AT91C_US1_XXR           ( 0xFFFC4048 ) /* (US1) XON_XOFF Register */
+#define AT91C_US1_RHR           ( 0xFFFC4018 ) /* (US1) Receiver Holding Register */
+#define AT91C_US1_IMR           ( 0xFFFC4010 ) /* (US1) Interrupt Mask Register */
+#define AT91C_US1_IER           ( 0xFFFC4008 ) /* (US1) Interrupt Enable Register */
+#define AT91C_US1_CR            ( 0xFFFC4000 ) /* (US1) Control Register */
+#define AT91C_US1_RTOR          ( 0xFFFC4024 ) /* (US1) Receiver Time-out Register */
+#define AT91C_US1_THR           ( 0xFFFC401C ) /* (US1) Transmitter Holding Register */
+#define AT91C_US1_CSR           ( 0xFFFC4014 ) /* (US1) Channel Status Register */
+#define AT91C_US1_IDR           ( 0xFFFC400C ) /* (US1) Interrupt Disable Register */
+#define AT91C_US1_FIDI          ( 0xFFFC4040 ) /* (US1) FI_DI_Ratio Register */
+#define AT91C_US1_BRGR          ( 0xFFFC4020 ) /* (US1) Baud Rate Generator Register */
+#define AT91C_US1_TTGR          ( 0xFFFC4028 ) /* (US1) Transmitter Time-guard Register */
+#define AT91C_US1_IF            ( 0xFFFC404C ) /* (US1) IRDA_FILTER Register */
+#define AT91C_US1_NER           ( 0xFFFC4044 ) /* (US1) Nb Errors Register */
+#define AT91C_US1_MR            ( 0xFFFC4004 ) /* (US1) Mode Register */
+/* ========== Register definition for PDC_US0 peripheral ========== */
+#define AT91C_US0_PTCR          ( 0xFFFC0120 ) /* (PDC_US0) PDC Transfer Control Register */
+#define AT91C_US0_TNPR          ( 0xFFFC0118 ) /* (PDC_US0) Transmit Next Pointer Register */
+#define AT91C_US0_RNPR          ( 0xFFFC0110 ) /* (PDC_US0) Receive Next Pointer Register */
+#define AT91C_US0_TPR           ( 0xFFFC0108 ) /* (PDC_US0) Transmit Pointer Register */
+#define AT91C_US0_RPR           ( 0xFFFC0100 ) /* (PDC_US0) Receive Pointer Register */
+#define AT91C_US0_PTSR          ( 0xFFFC0124 ) /* (PDC_US0) PDC Transfer Status Register */
+#define AT91C_US0_TNCR          ( 0xFFFC011C ) /* (PDC_US0) Transmit Next Counter Register */
+#define AT91C_US0_RNCR          ( 0xFFFC0114 ) /* (PDC_US0) Receive Next Counter Register */
+#define AT91C_US0_TCR           ( 0xFFFC010C ) /* (PDC_US0) Transmit Counter Register */
+#define AT91C_US0_RCR           ( 0xFFFC0104 ) /* (PDC_US0) Receive Counter Register */
+/* ========== Register definition for US0 peripheral ========== */
+#define AT91C_US0_TTGR          ( 0xFFFC0028 ) /* (US0) Transmitter Time-guard Register */
+#define AT91C_US0_BRGR          ( 0xFFFC0020 ) /* (US0) Baud Rate Generator Register */
+#define AT91C_US0_RHR           ( 0xFFFC0018 ) /* (US0) Receiver Holding Register */
+#define AT91C_US0_IMR           ( 0xFFFC0010 ) /* (US0) Interrupt Mask Register */
+#define AT91C_US0_NER           ( 0xFFFC0044 ) /* (US0) Nb Errors Register */
+#define AT91C_US0_RTOR          ( 0xFFFC0024 ) /* (US0) Receiver Time-out Register */
+#define AT91C_US0_XXR           ( 0xFFFC0048 ) /* (US0) XON_XOFF Register */
+#define AT91C_US0_FIDI          ( 0xFFFC0040 ) /* (US0) FI_DI_Ratio Register */
+#define AT91C_US0_CR            ( 0xFFFC0000 ) /* (US0) Control Register */
+#define AT91C_US0_IER           ( 0xFFFC0008 ) /* (US0) Interrupt Enable Register */
+#define AT91C_US0_IF            ( 0xFFFC004C ) /* (US0) IRDA_FILTER Register */
+#define AT91C_US0_MR            ( 0xFFFC0004 ) /* (US0) Mode Register */
+#define AT91C_US0_IDR           ( 0xFFFC000C ) /* (US0) Interrupt Disable Register */
+#define AT91C_US0_CSR           ( 0xFFFC0014 ) /* (US0) Channel Status Register */
+#define AT91C_US0_THR           ( 0xFFFC001C ) /* (US0) Transmitter Holding Register */
+/* ========== Register definition for TWI peripheral ========== */
+#define AT91C_TWI_RHR           ( 0xFFFB8030 ) /* (TWI) Receive Holding Register */
+#define AT91C_TWI_IDR           ( 0xFFFB8028 ) /* (TWI) Interrupt Disable Register */
+#define AT91C_TWI_SR            ( 0xFFFB8020 ) /* (TWI) Status Register */
+#define AT91C_TWI_CWGR          ( 0xFFFB8010 ) /* (TWI) Clock Waveform Generator Register */
+#define AT91C_TWI_SMR           ( 0xFFFB8008 ) /* (TWI) Slave Mode Register */
+#define AT91C_TWI_CR            ( 0xFFFB8000 ) /* (TWI) Control Register */
+#define AT91C_TWI_THR           ( 0xFFFB8034 ) /* (TWI) Transmit Holding Register */
+#define AT91C_TWI_IMR           ( 0xFFFB802C ) /* (TWI) Interrupt Mask Register */
+#define AT91C_TWI_IER           ( 0xFFFB8024 ) /* (TWI) Interrupt Enable Register */
+#define AT91C_TWI_IADR          ( 0xFFFB800C ) /* (TWI) Internal Address Register */
+#define AT91C_TWI_MMR           ( 0xFFFB8004 ) /* (TWI) Master Mode Register */
+/* ========== Register definition for TC2 peripheral ========== */
+#define AT91C_TC2_IMR           ( 0xFFFA00AC ) /* (TC2) Interrupt Mask Register */
+#define AT91C_TC2_IER           ( 0xFFFA00A4 ) /* (TC2) Interrupt Enable Register */
+#define AT91C_TC2_RC            ( 0xFFFA009C ) /* (TC2) Register C */
+#define AT91C_TC2_RA            ( 0xFFFA0094 ) /* (TC2) Register A */
+#define AT91C_TC2_CMR           ( 0xFFFA0084 ) /* (TC2) Channel Mode Register (Capture Mode / Waveform Mode) */
+#define AT91C_TC2_IDR           ( 0xFFFA00A8 ) /* (TC2) Interrupt Disable Register */
+#define AT91C_TC2_SR            ( 0xFFFA00A0 ) /* (TC2) Status Register */
+#define AT91C_TC2_RB            ( 0xFFFA0098 ) /* (TC2) Register B */
+#define AT91C_TC2_CV            ( 0xFFFA0090 ) /* (TC2) Counter Value */
+#define AT91C_TC2_CCR           ( 0xFFFA0080 ) /* (TC2) Channel Control Register */
+/* ========== Register definition for TC1 peripheral ========== */
+#define AT91C_TC1_IMR           ( 0xFFFA006C ) /* (TC1) Interrupt Mask Register */
+#define AT91C_TC1_IER           ( 0xFFFA0064 ) /* (TC1) Interrupt Enable Register */
+#define AT91C_TC1_RC            ( 0xFFFA005C ) /* (TC1) Register C */
+#define AT91C_TC1_RA            ( 0xFFFA0054 ) /* (TC1) Register A */
+#define AT91C_TC1_CMR           ( 0xFFFA0044 ) /* (TC1) Channel Mode Register (Capture Mode / Waveform Mode) */
+#define AT91C_TC1_IDR           ( 0xFFFA0068 ) /* (TC1) Interrupt Disable Register */
+#define AT91C_TC1_SR            ( 0xFFFA0060 ) /* (TC1) Status Register */
+#define AT91C_TC1_RB            ( 0xFFFA0058 ) /* (TC1) Register B */
+#define AT91C_TC1_CV            ( 0xFFFA0050 ) /* (TC1) Counter Value */
+#define AT91C_TC1_CCR           ( 0xFFFA0040 ) /* (TC1) Channel Control Register */
+/* ========== Register definition for TC0 peripheral ========== */
+#define AT91C_TC0_IMR           ( 0xFFFA002C ) /* (TC0) Interrupt Mask Register */
+#define AT91C_TC0_IER           ( 0xFFFA0024 ) /* (TC0) Interrupt Enable Register */
+#define AT91C_TC0_RC            ( 0xFFFA001C ) /* (TC0) Register C */
+#define AT91C_TC0_RA            ( 0xFFFA0014 ) /* (TC0) Register A */
+#define AT91C_TC0_CMR           ( 0xFFFA0004 ) /* (TC0) Channel Mode Register (Capture Mode / Waveform Mode) */
+#define AT91C_TC0_IDR           ( 0xFFFA0028 ) /* (TC0) Interrupt Disable Register */
+#define AT91C_TC0_SR            ( 0xFFFA0020 ) /* (TC0) Status Register */
+#define AT91C_TC0_RB            ( 0xFFFA0018 ) /* (TC0) Register B */
+#define AT91C_TC0_CV            ( 0xFFFA0010 ) /* (TC0) Counter Value */
+#define AT91C_TC0_CCR           ( 0xFFFA0000 ) /* (TC0) Channel Control Register */
+/* ========== Register definition for TCB peripheral ========== */
+#define AT91C_TCB_BMR           ( 0xFFFA00C4 ) /* (TCB) TC Block Mode Register */
+#define AT91C_TCB_BCR           ( 0xFFFA00C0 ) /* (TCB) TC Block Control Register */
+/* ========== Register definition for PWMC_CH3 peripheral ========== */
+#define AT91C_CH3_CUPDR         ( 0xFFFCC270 ) /* (PWMC_CH3) Channel Update Register */
+#define AT91C_CH3_CPRDR         ( 0xFFFCC268 ) /* (PWMC_CH3) Channel Period Register */
+#define AT91C_CH3_CMR           ( 0xFFFCC260 ) /* (PWMC_CH3) Channel Mode Register */
+#define AT91C_CH3_Reserved      ( 0xFFFCC274 ) /* (PWMC_CH3) Reserved */
+#define AT91C_CH3_CCNTR         ( 0xFFFCC26C ) /* (PWMC_CH3) Channel Counter Register */
+#define AT91C_CH3_CDTYR         ( 0xFFFCC264 ) /* (PWMC_CH3) Channel Duty Cycle Register */
+/* ========== Register definition for PWMC_CH2 peripheral ========== */
+#define AT91C_CH2_CUPDR         ( 0xFFFCC250 ) /* (PWMC_CH2) Channel Update Register */
+#define AT91C_CH2_CPRDR         ( 0xFFFCC248 ) /* (PWMC_CH2) Channel Period Register */
+#define AT91C_CH2_CMR           ( 0xFFFCC240 ) /* (PWMC_CH2) Channel Mode Register */
+#define AT91C_CH2_Reserved      ( 0xFFFCC254 ) /* (PWMC_CH2) Reserved */
+#define AT91C_CH2_CCNTR         ( 0xFFFCC24C ) /* (PWMC_CH2) Channel Counter Register */
+#define AT91C_CH2_CDTYR         ( 0xFFFCC244 ) /* (PWMC_CH2) Channel Duty Cycle Register */
+/* ========== Register definition for PWMC_CH1 peripheral ========== */
+#define AT91C_CH1_CUPDR         ( 0xFFFCC230 ) /* (PWMC_CH1) Channel Update Register */
+#define AT91C_CH1_CPRDR         ( 0xFFFCC228 ) /* (PWMC_CH1) Channel Period Register */
+#define AT91C_CH1_CMR           ( 0xFFFCC220 ) /* (PWMC_CH1) Channel Mode Register */
+#define AT91C_CH1_Reserved      ( 0xFFFCC234 ) /* (PWMC_CH1) Reserved */
+#define AT91C_CH1_CCNTR         ( 0xFFFCC22C ) /* (PWMC_CH1) Channel Counter Register */
+#define AT91C_CH1_CDTYR         ( 0xFFFCC224 ) /* (PWMC_CH1) Channel Duty Cycle Register */
+/* ========== Register definition for PWMC_CH0 peripheral ========== */
+#define AT91C_CH0_CUPDR         ( 0xFFFCC210 ) /* (PWMC_CH0) Channel Update Register */
+#define AT91C_CH0_CPRDR         ( 0xFFFCC208 ) /* (PWMC_CH0) Channel Period Register */
+#define AT91C_CH0_CMR           ( 0xFFFCC200 ) /* (PWMC_CH0) Channel Mode Register */
+#define AT91C_CH0_Reserved      ( 0xFFFCC214 ) /* (PWMC_CH0) Reserved */
+#define AT91C_CH0_CCNTR         ( 0xFFFCC20C ) /* (PWMC_CH0) Channel Counter Register */
+#define AT91C_CH0_CDTYR         ( 0xFFFCC204 ) /* (PWMC_CH0) Channel Duty Cycle Register */
+/* ========== Register definition for PWMC peripheral ========== */
+#define AT91C_PWMC_VR           ( 0xFFFCC0FC ) /* (PWMC) PWMC Version Register */
+#define AT91C_PWMC_ISR          ( 0xFFFCC01C ) /* (PWMC) PWMC Interrupt Status Register */
+#define AT91C_PWMC_IDR          ( 0xFFFCC014 ) /* (PWMC) PWMC Interrupt Disable Register */
+#define AT91C_PWMC_SR           ( 0xFFFCC00C ) /* (PWMC) PWMC Status Register */
+#define AT91C_PWMC_ENA          ( 0xFFFCC004 ) /* (PWMC) PWMC Enable Register */
+#define AT91C_PWMC_IMR          ( 0xFFFCC018 ) /* (PWMC) PWMC Interrupt Mask Register */
+#define AT91C_PWMC_MR           ( 0xFFFCC000 ) /* (PWMC) PWMC Mode Register */
+#define AT91C_PWMC_DIS          ( 0xFFFCC008 ) /* (PWMC) PWMC Disable Register */
+#define AT91C_PWMC_IER          ( 0xFFFCC010 ) /* (PWMC) PWMC Interrupt Enable Register */
+/* ========== Register definition for UDP peripheral ========== */
+#define AT91C_UDP_ISR           ( 0xFFFB001C ) /* (UDP) Interrupt Status Register */
+#define AT91C_UDP_IDR           ( 0xFFFB0014 ) /* (UDP) Interrupt Disable Register */
+#define AT91C_UDP_GLBSTATE      ( 0xFFFB0004 ) /* (UDP) Global State Register */
+#define AT91C_UDP_FDR           ( 0xFFFB0050 ) /* (UDP) Endpoint FIFO Data Register */
+#define AT91C_UDP_CSR           ( 0xFFFB0030 ) /* (UDP) Endpoint Control and Status Register */
+#define AT91C_UDP_RSTEP         ( 0xFFFB0028 ) /* (UDP) Reset Endpoint Register */
+#define AT91C_UDP_ICR           ( 0xFFFB0020 ) /* (UDP) Interrupt Clear Register */
+#define AT91C_UDP_IMR           ( 0xFFFB0018 ) /* (UDP) Interrupt Mask Register */
+#define AT91C_UDP_IER           ( 0xFFFB0010 ) /* (UDP) Interrupt Enable Register */
+#define AT91C_UDP_FADDR         ( 0xFFFB0008 ) /* (UDP) Function Address Register */
+#define AT91C_UDP_NUM           ( 0xFFFB0000 ) /* (UDP) Frame Number Register */
 
-// *****************************************************************************
-//               PIO DEFINITIONS FOR AT91SAM7S64
-// *****************************************************************************
-#define AT91C_PIO_PA0             (1 <<  0) // Pin Controlled by PA0
-#define AT91C_PA0_PWM0            (AT91C_PIO_PA0) //  PWM Channel 0
-#define AT91C_PA0_TIOA0           (AT91C_PIO_PA0) //  Timer Counter 0 Multipurpose Timer I/O Pin A
-#define AT91C_PIO_PA1             (1 <<  1) // Pin Controlled by PA1
-#define AT91C_PA1_PWM1            (AT91C_PIO_PA1) //  PWM Channel 1
-#define AT91C_PA1_TIOB0           (AT91C_PIO_PA1) //  Timer Counter 0 Multipurpose Timer I/O Pin B
-#define AT91C_PIO_PA10            (1 << 10) // Pin Controlled by PA10
-#define AT91C_PA10_DTXD           (AT91C_PIO_PA10) //  DBGU Debug Transmit Data
-#define AT91C_PA10_NPCS2          (AT91C_PIO_PA10) //  SPI Peripheral Chip Select 2
-#define AT91C_PIO_PA11            (1 << 11) // Pin Controlled by PA11
-#define AT91C_PA11_NPCS0          (AT91C_PIO_PA11) //  SPI Peripheral Chip Select 0
-#define AT91C_PA11_PWM0           (AT91C_PIO_PA11) //  PWM Channel 0
-#define AT91C_PIO_PA12            (1 << 12) // Pin Controlled by PA12
-#define AT91C_PA12_MISO           (AT91C_PIO_PA12) //  SPI Master In Slave
-#define AT91C_PA12_PWM1           (AT91C_PIO_PA12) //  PWM Channel 1
-#define AT91C_PIO_PA13            (1 << 13) // Pin Controlled by PA13
-#define AT91C_PA13_MOSI           (AT91C_PIO_PA13) //  SPI Master Out Slave
-#define AT91C_PA13_PWM2           (AT91C_PIO_PA13) //  PWM Channel 2
-#define AT91C_PIO_PA14            (1 << 14) // Pin Controlled by PA14
-#define AT91C_PA14_SPCK           (AT91C_PIO_PA14) //  SPI Serial Clock
-#define AT91C_PA14_PWM3           (AT91C_PIO_PA14) //  PWM Channel 3
-#define AT91C_PIO_PA15            (1 << 15) // Pin Controlled by PA15
-#define AT91C_PA15_TF             (AT91C_PIO_PA15) //  SSC Transmit Frame Sync
-#define AT91C_PA15_TIOA1          (AT91C_PIO_PA15) //  Timer Counter 1 Multipurpose Timer I/O Pin A
-#define AT91C_PIO_PA16            (1 << 16) // Pin Controlled by PA16
-#define AT91C_PA16_TK             (AT91C_PIO_PA16) //  SSC Transmit Clock
-#define AT91C_PA16_TIOB1          (AT91C_PIO_PA16) //  Timer Counter 1 Multipurpose Timer I/O Pin B
-#define AT91C_PIO_PA17            (1 << 17) // Pin Controlled by PA17
-#define AT91C_PA17_TD             (AT91C_PIO_PA17) //  SSC Transmit data
-#define AT91C_PA17_PCK1           (AT91C_PIO_PA17) //  PMC Programmable Clock Output 1
-#define AT91C_PIO_PA18            (1 << 18) // Pin Controlled by PA18
-#define AT91C_PA18_RD             (AT91C_PIO_PA18) //  SSC Receive Data
-#define AT91C_PA18_PCK2           (AT91C_PIO_PA18) //  PMC Programmable Clock Output 2
-#define AT91C_PIO_PA19            (1 << 19) // Pin Controlled by PA19
-#define AT91C_PA19_RK             (AT91C_PIO_PA19) //  SSC Receive Clock
-#define AT91C_PA19_FIQ            (AT91C_PIO_PA19) //  AIC Fast Interrupt Input
-#define AT91C_PIO_PA2             (1 <<  2) // Pin Controlled by PA2
-#define AT91C_PA2_PWM2            (AT91C_PIO_PA2) //  PWM Channel 2
-#define AT91C_PA2_SCK0            (AT91C_PIO_PA2) //  USART 0 Serial Clock
-#define AT91C_PIO_PA20            (1 << 20) // Pin Controlled by PA20
-#define AT91C_PA20_RF             (AT91C_PIO_PA20) //  SSC Receive Frame Sync
-#define AT91C_PA20_IRQ0           (AT91C_PIO_PA20) //  External Interrupt 0
-#define AT91C_PIO_PA21            (1 << 21) // Pin Controlled by PA21
-#define AT91C_PA21_RXD1           (AT91C_PIO_PA21) //  USART 1 Receive Data
-#define AT91C_PA21_PCK1           (AT91C_PIO_PA21) //  PMC Programmable Clock Output 1
-#define AT91C_PIO_PA22            (1 << 22) // Pin Controlled by PA22
-#define AT91C_PA22_TXD1           (AT91C_PIO_PA22) //  USART 1 Transmit Data
-#define AT91C_PA22_NPCS3          (AT91C_PIO_PA22) //  SPI Peripheral Chip Select 3
-#define AT91C_PIO_PA23            (1 << 23) // Pin Controlled by PA23
-#define AT91C_PA23_SCK1           (AT91C_PIO_PA23) //  USART 1 Serial Clock
-#define AT91C_PA23_PWM0           (AT91C_PIO_PA23) //  PWM Channel 0
-#define AT91C_PIO_PA24            (1 << 24) // Pin Controlled by PA24
-#define AT91C_PA24_RTS1           (AT91C_PIO_PA24) //  USART 1 Ready To Send
-#define AT91C_PA24_PWM1           (AT91C_PIO_PA24) //  PWM Channel 1
-#define AT91C_PIO_PA25            (1 << 25) // Pin Controlled by PA25
-#define AT91C_PA25_CTS1           (AT91C_PIO_PA25) //  USART 1 Clear To Send
-#define AT91C_PA25_PWM2           (AT91C_PIO_PA25) //  PWM Channel 2
-#define AT91C_PIO_PA26            (1 << 26) // Pin Controlled by PA26
-#define AT91C_PA26_DCD1           (AT91C_PIO_PA26) //  USART 1 Data Carrier Detect
-#define AT91C_PA26_TIOA2          (AT91C_PIO_PA26) //  Timer Counter 2 Multipurpose Timer I/O Pin A
-#define AT91C_PIO_PA27            (1 << 27) // Pin Controlled by PA27
-#define AT91C_PA27_DTR1           (AT91C_PIO_PA27) //  USART 1 Data Terminal ready
-#define AT91C_PA27_TIOB2          (AT91C_PIO_PA27) //  Timer Counter 2 Multipurpose Timer I/O Pin B
-#define AT91C_PIO_PA28            (1 << 28) // Pin Controlled by PA28
-#define AT91C_PA28_DSR1           (AT91C_PIO_PA28) //  USART 1 Data Set ready
-#define AT91C_PA28_TCLK1          (AT91C_PIO_PA28) //  Timer Counter 1 external clock input
-#define AT91C_PIO_PA29            (1 << 29) // Pin Controlled by PA29
-#define AT91C_PA29_RI1            (AT91C_PIO_PA29) //  USART 1 Ring Indicator
-#define AT91C_PA29_TCLK2          (AT91C_PIO_PA29) //  Timer Counter 2 external clock input
-#define AT91C_PIO_PA3             (1 <<  3) // Pin Controlled by PA3
-#define AT91C_PA3_TWD             (AT91C_PIO_PA3) //  TWI Two-wire Serial Data
-#define AT91C_PA3_NPCS3           (AT91C_PIO_PA3) //  SPI Peripheral Chip Select 3
-#define AT91C_PIO_PA30            (1 << 30) // Pin Controlled by PA30
-#define AT91C_PA30_IRQ1           (AT91C_PIO_PA30) //  External Interrupt 1
-#define AT91C_PA30_NPCS2          (AT91C_PIO_PA30) //  SPI Peripheral Chip Select 2
-#define AT91C_PIO_PA31            (1 << 31) // Pin Controlled by PA31
-#define AT91C_PA31_NPCS1          (AT91C_PIO_PA31) //  SPI Peripheral Chip Select 1
-#define AT91C_PA31_PCK2           (AT91C_PIO_PA31) //  PMC Programmable Clock Output 2
-#define AT91C_PIO_PA4             (1 <<  4) // Pin Controlled by PA4
-#define AT91C_PA4_TWCK            (AT91C_PIO_PA4) //  TWI Two-wire Serial Clock
-#define AT91C_PA4_TCLK0           (AT91C_PIO_PA4) //  Timer Counter 0 external clock input
-#define AT91C_PIO_PA5             (1 <<  5) // Pin Controlled by PA5
-#define AT91C_PA5_RXD0            (AT91C_PIO_PA5) //  USART 0 Receive Data
-#define AT91C_PA5_NPCS3           (AT91C_PIO_PA5) //  SPI Peripheral Chip Select 3
-#define AT91C_PIO_PA6             (1 <<  6) // Pin Controlled by PA6
-#define AT91C_PA6_TXD0            (AT91C_PIO_PA6) //  USART 0 Transmit Data
-#define AT91C_PA6_PCK0            (AT91C_PIO_PA6) //  PMC Programmable Clock Output 0
-#define AT91C_PIO_PA7             (1 <<  7) // Pin Controlled by PA7
-#define AT91C_PA7_RTS0            (AT91C_PIO_PA7) //  USART 0 Ready To Send
-#define AT91C_PA7_PWM3            (AT91C_PIO_PA7) //  PWM Channel 3
-#define AT91C_PIO_PA8             (1 <<  8) // Pin Controlled by PA8
-#define AT91C_PA8_CTS0            (AT91C_PIO_PA8) //  USART 0 Clear To Send
-#define AT91C_PA8_ADTRG           (AT91C_PIO_PA8) //  ADC External Trigger
-#define AT91C_PIO_PA9             (1 <<  9) // Pin Controlled by PA9
-#define AT91C_PA9_DRXD            (AT91C_PIO_PA9) //  DBGU Debug Receive Data
-#define AT91C_PA9_NPCS1           (AT91C_PIO_PA9) //  SPI Peripheral Chip Select 1
+/* ***************************************************************************** */
+/*               PIO DEFINITIONS FOR AT91SAM7S64 */
+/* ***************************************************************************** */
+#define AT91C_PIO_PA0       ( 1 << 0 )         /* Pin Controlled by PA0 */
+#define AT91C_PA0_PWM0      ( AT91C_PIO_PA0 )  /*  PWM Channel 0 */
+#define AT91C_PA0_TIOA0     ( AT91C_PIO_PA0 )  /*  Timer Counter 0 Multipurpose Timer I/O Pin A */
+#define AT91C_PIO_PA1       ( 1 << 1 )         /* Pin Controlled by PA1 */
+#define AT91C_PA1_PWM1      ( AT91C_PIO_PA1 )  /*  PWM Channel 1 */
+#define AT91C_PA1_TIOB0     ( AT91C_PIO_PA1 )  /*  Timer Counter 0 Multipurpose Timer I/O Pin B */
+#define AT91C_PIO_PA10      ( 1 << 10 )        /* Pin Controlled by PA10 */
+#define AT91C_PA10_DTXD     ( AT91C_PIO_PA10 ) /*  DBGU Debug Transmit Data */
+#define AT91C_PA10_NPCS2    ( AT91C_PIO_PA10 ) /*  SPI Peripheral Chip Select 2 */
+#define AT91C_PIO_PA11      ( 1 << 11 )        /* Pin Controlled by PA11 */
+#define AT91C_PA11_NPCS0    ( AT91C_PIO_PA11 ) /*  SPI Peripheral Chip Select 0 */
+#define AT91C_PA11_PWM0     ( AT91C_PIO_PA11 ) /*  PWM Channel 0 */
+#define AT91C_PIO_PA12      ( 1 << 12 )        /* Pin Controlled by PA12 */
+#define AT91C_PA12_MISO     ( AT91C_PIO_PA12 ) /*  SPI Master In Slave */
+#define AT91C_PA12_PWM1     ( AT91C_PIO_PA12 ) /*  PWM Channel 1 */
+#define AT91C_PIO_PA13      ( 1 << 13 )        /* Pin Controlled by PA13 */
+#define AT91C_PA13_MOSI     ( AT91C_PIO_PA13 ) /*  SPI Master Out Slave */
+#define AT91C_PA13_PWM2     ( AT91C_PIO_PA13 ) /*  PWM Channel 2 */
+#define AT91C_PIO_PA14      ( 1 << 14 )        /* Pin Controlled by PA14 */
+#define AT91C_PA14_SPCK     ( AT91C_PIO_PA14 ) /*  SPI Serial Clock */
+#define AT91C_PA14_PWM3     ( AT91C_PIO_PA14 ) /*  PWM Channel 3 */
+#define AT91C_PIO_PA15      ( 1 << 15 )        /* Pin Controlled by PA15 */
+#define AT91C_PA15_TF       ( AT91C_PIO_PA15 ) /*  SSC Transmit Frame Sync */
+#define AT91C_PA15_TIOA1    ( AT91C_PIO_PA15 ) /*  Timer Counter 1 Multipurpose Timer I/O Pin A */
+#define AT91C_PIO_PA16      ( 1 << 16 )        /* Pin Controlled by PA16 */
+#define AT91C_PA16_TK       ( AT91C_PIO_PA16 ) /*  SSC Transmit Clock */
+#define AT91C_PA16_TIOB1    ( AT91C_PIO_PA16 ) /*  Timer Counter 1 Multipurpose Timer I/O Pin B */
+#define AT91C_PIO_PA17      ( 1 << 17 )        /* Pin Controlled by PA17 */
+#define AT91C_PA17_TD       ( AT91C_PIO_PA17 ) /*  SSC Transmit data */
+#define AT91C_PA17_PCK1     ( AT91C_PIO_PA17 ) /*  PMC Programmable Clock Output 1 */
+#define AT91C_PIO_PA18      ( 1 << 18 )        /* Pin Controlled by PA18 */
+#define AT91C_PA18_RD       ( AT91C_PIO_PA18 ) /*  SSC Receive Data */
+#define AT91C_PA18_PCK2     ( AT91C_PIO_PA18 ) /*  PMC Programmable Clock Output 2 */
+#define AT91C_PIO_PA19      ( 1 << 19 )        /* Pin Controlled by PA19 */
+#define AT91C_PA19_RK       ( AT91C_PIO_PA19 ) /*  SSC Receive Clock */
+#define AT91C_PA19_FIQ      ( AT91C_PIO_PA19 ) /*  AIC Fast Interrupt Input */
+#define AT91C_PIO_PA2       ( 1 << 2 )         /* Pin Controlled by PA2 */
+#define AT91C_PA2_PWM2      ( AT91C_PIO_PA2 )  /*  PWM Channel 2 */
+#define AT91C_PA2_SCK0      ( AT91C_PIO_PA2 )  /*  USART 0 Serial Clock */
+#define AT91C_PIO_PA20      ( 1 << 20 )        /* Pin Controlled by PA20 */
+#define AT91C_PA20_RF       ( AT91C_PIO_PA20 ) /*  SSC Receive Frame Sync */
+#define AT91C_PA20_IRQ0     ( AT91C_PIO_PA20 ) /*  External Interrupt 0 */
+#define AT91C_PIO_PA21      ( 1 << 21 )        /* Pin Controlled by PA21 */
+#define AT91C_PA21_RXD1     ( AT91C_PIO_PA21 ) /*  USART 1 Receive Data */
+#define AT91C_PA21_PCK1     ( AT91C_PIO_PA21 ) /*  PMC Programmable Clock Output 1 */
+#define AT91C_PIO_PA22      ( 1 << 22 )        /* Pin Controlled by PA22 */
+#define AT91C_PA22_TXD1     ( AT91C_PIO_PA22 ) /*  USART 1 Transmit Data */
+#define AT91C_PA22_NPCS3    ( AT91C_PIO_PA22 ) /*  SPI Peripheral Chip Select 3 */
+#define AT91C_PIO_PA23      ( 1 << 23 )        /* Pin Controlled by PA23 */
+#define AT91C_PA23_SCK1     ( AT91C_PIO_PA23 ) /*  USART 1 Serial Clock */
+#define AT91C_PA23_PWM0     ( AT91C_PIO_PA23 ) /*  PWM Channel 0 */
+#define AT91C_PIO_PA24      ( 1 << 24 )        /* Pin Controlled by PA24 */
+#define AT91C_PA24_RTS1     ( AT91C_PIO_PA24 ) /*  USART 1 Ready To Send */
+#define AT91C_PA24_PWM1     ( AT91C_PIO_PA24 ) /*  PWM Channel 1 */
+#define AT91C_PIO_PA25      ( 1 << 25 )        /* Pin Controlled by PA25 */
+#define AT91C_PA25_CTS1     ( AT91C_PIO_PA25 ) /*  USART 1 Clear To Send */
+#define AT91C_PA25_PWM2     ( AT91C_PIO_PA25 ) /*  PWM Channel 2 */
+#define AT91C_PIO_PA26      ( 1 << 26 )        /* Pin Controlled by PA26 */
+#define AT91C_PA26_DCD1     ( AT91C_PIO_PA26 ) /*  USART 1 Data Carrier Detect */
+#define AT91C_PA26_TIOA2    ( AT91C_PIO_PA26 ) /*  Timer Counter 2 Multipurpose Timer I/O Pin A */
+#define AT91C_PIO_PA27      ( 1 << 27 )        /* Pin Controlled by PA27 */
+#define AT91C_PA27_DTR1     ( AT91C_PIO_PA27 ) /*  USART 1 Data Terminal ready */
+#define AT91C_PA27_TIOB2    ( AT91C_PIO_PA27 ) /*  Timer Counter 2 Multipurpose Timer I/O Pin B */
+#define AT91C_PIO_PA28      ( 1 << 28 )        /* Pin Controlled by PA28 */
+#define AT91C_PA28_DSR1     ( AT91C_PIO_PA28 ) /*  USART 1 Data Set ready */
+#define AT91C_PA28_TCLK1    ( AT91C_PIO_PA28 ) /*  Timer Counter 1 external clock input */
+#define AT91C_PIO_PA29      ( 1 << 29 )        /* Pin Controlled by PA29 */
+#define AT91C_PA29_RI1      ( AT91C_PIO_PA29 ) /*  USART 1 Ring Indicator */
+#define AT91C_PA29_TCLK2    ( AT91C_PIO_PA29 ) /*  Timer Counter 2 external clock input */
+#define AT91C_PIO_PA3       ( 1 << 3 )         /* Pin Controlled by PA3 */
+#define AT91C_PA3_TWD       ( AT91C_PIO_PA3 )  /*  TWI Two-wire Serial Data */
+#define AT91C_PA3_NPCS3     ( AT91C_PIO_PA3 )  /*  SPI Peripheral Chip Select 3 */
+#define AT91C_PIO_PA30      ( 1 << 30 )        /* Pin Controlled by PA30 */
+#define AT91C_PA30_IRQ1     ( AT91C_PIO_PA30 ) /*  External Interrupt 1 */
+#define AT91C_PA30_NPCS2    ( AT91C_PIO_PA30 ) /*  SPI Peripheral Chip Select 2 */
+#define AT91C_PIO_PA31      ( 1 << 31 )        /* Pin Controlled by PA31 */
+#define AT91C_PA31_NPCS1    ( AT91C_PIO_PA31 ) /*  SPI Peripheral Chip Select 1 */
+#define AT91C_PA31_PCK2     ( AT91C_PIO_PA31 ) /*  PMC Programmable Clock Output 2 */
+#define AT91C_PIO_PA4       ( 1 << 4 )         /* Pin Controlled by PA4 */
+#define AT91C_PA4_TWCK      ( AT91C_PIO_PA4 )  /*  TWI Two-wire Serial Clock */
+#define AT91C_PA4_TCLK0     ( AT91C_PIO_PA4 )  /*  Timer Counter 0 external clock input */
+#define AT91C_PIO_PA5       ( 1 << 5 )         /* Pin Controlled by PA5 */
+#define AT91C_PA5_RXD0      ( AT91C_PIO_PA5 )  /*  USART 0 Receive Data */
+#define AT91C_PA5_NPCS3     ( AT91C_PIO_PA5 )  /*  SPI Peripheral Chip Select 3 */
+#define AT91C_PIO_PA6       ( 1 << 6 )         /* Pin Controlled by PA6 */
+#define AT91C_PA6_TXD0      ( AT91C_PIO_PA6 )  /*  USART 0 Transmit Data */
+#define AT91C_PA6_PCK0      ( AT91C_PIO_PA6 )  /*  PMC Programmable Clock Output 0 */
+#define AT91C_PIO_PA7       ( 1 << 7 )         /* Pin Controlled by PA7 */
+#define AT91C_PA7_RTS0      ( AT91C_PIO_PA7 )  /*  USART 0 Ready To Send */
+#define AT91C_PA7_PWM3      ( AT91C_PIO_PA7 )  /*  PWM Channel 3 */
+#define AT91C_PIO_PA8       ( 1 << 8 )         /* Pin Controlled by PA8 */
+#define AT91C_PA8_CTS0      ( AT91C_PIO_PA8 )  /*  USART 0 Clear To Send */
+#define AT91C_PA8_ADTRG     ( AT91C_PIO_PA8 )  /*  ADC External Trigger */
+#define AT91C_PIO_PA9       ( 1 << 9 )         /* Pin Controlled by PA9 */
+#define AT91C_PA9_DRXD      ( AT91C_PIO_PA9 )  /*  DBGU Debug Receive Data */
+#define AT91C_PA9_NPCS1     ( AT91C_PIO_PA9 )  /*  SPI Peripheral Chip Select 1 */
 
-// *****************************************************************************
-//               PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64
-// *****************************************************************************
-#define AT91C_ID_FIQ              ( 0) // Advanced Interrupt Controller (FIQ)
-#define AT91C_ID_SYS              ( 1) // System Peripheral
-#define AT91C_ID_PIOA             ( 2) // Parallel IO Controller
-#define AT91C_ID_3_Reserved       ( 3) // Reserved
-#define AT91C_ID_ADC              ( 4) // Analog-to-Digital Converter
-#define AT91C_ID_SPI              ( 5) // Serial Peripheral Interface
-#define AT91C_ID_US0              ( 6) // USART 0
-#define AT91C_ID_US1              ( 7) // USART 1
-#define AT91C_ID_SSC              ( 8) // Serial Synchronous Controller
-#define AT91C_ID_TWI              ( 9) // Two-Wire Interface
-#define AT91C_ID_PWMC             (10) // PWM Controller
-#define AT91C_ID_UDP              (11) // USB Device Port
-#define AT91C_ID_TC0              (12) // Timer Counter 0
-#define AT91C_ID_TC1              (13) // Timer Counter 1
-#define AT91C_ID_TC2              (14) // Timer Counter 2
-#define AT91C_ID_15_Reserved      (15) // Reserved
-#define AT91C_ID_16_Reserved      (16) // Reserved
-#define AT91C_ID_17_Reserved      (17) // Reserved
-#define AT91C_ID_18_Reserved      (18) // Reserved
-#define AT91C_ID_19_Reserved      (19) // Reserved
-#define AT91C_ID_20_Reserved      (20) // Reserved
-#define AT91C_ID_21_Reserved      (21) // Reserved
-#define AT91C_ID_22_Reserved      (22) // Reserved
-#define AT91C_ID_23_Reserved      (23) // Reserved
-#define AT91C_ID_24_Reserved      (24) // Reserved
-#define AT91C_ID_25_Reserved      (25) // Reserved
-#define AT91C_ID_26_Reserved      (26) // Reserved
-#define AT91C_ID_27_Reserved      (27) // Reserved
-#define AT91C_ID_28_Reserved      (28) // Reserved
-#define AT91C_ID_29_Reserved      (29) // Reserved
-#define AT91C_ID_IRQ0             (30) // Advanced Interrupt Controller (IRQ0)
-#define AT91C_ID_IRQ1             (31) // Advanced Interrupt Controller (IRQ1)
+/* ***************************************************************************** */
+/*               PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64 */
+/* ***************************************************************************** */
+#define AT91C_ID_FIQ            ( 0 )  /* Advanced Interrupt Controller (FIQ) */
+#define AT91C_ID_SYS            ( 1 )  /* System Peripheral */
+#define AT91C_ID_PIOA           ( 2 )  /* Parallel IO Controller */
+#define AT91C_ID_3_Reserved     ( 3 )  /* Reserved */
+#define AT91C_ID_ADC            ( 4 )  /* Analog-to-Digital Converter */
+#define AT91C_ID_SPI            ( 5 )  /* Serial Peripheral Interface */
+#define AT91C_ID_US0            ( 6 )  /* USART 0 */
+#define AT91C_ID_US1            ( 7 )  /* USART 1 */
+#define AT91C_ID_SSC            ( 8 )  /* Serial Synchronous Controller */
+#define AT91C_ID_TWI            ( 9 )  /* Two-Wire Interface */
+#define AT91C_ID_PWMC           ( 10 ) /* PWM Controller */
+#define AT91C_ID_UDP            ( 11 ) /* USB Device Port */
+#define AT91C_ID_TC0            ( 12 ) /* Timer Counter 0 */
+#define AT91C_ID_TC1            ( 13 ) /* Timer Counter 1 */
+#define AT91C_ID_TC2            ( 14 ) /* Timer Counter 2 */
+#define AT91C_ID_15_Reserved    ( 15 ) /* Reserved */
+#define AT91C_ID_16_Reserved    ( 16 ) /* Reserved */
+#define AT91C_ID_17_Reserved    ( 17 ) /* Reserved */
+#define AT91C_ID_18_Reserved    ( 18 ) /* Reserved */
+#define AT91C_ID_19_Reserved    ( 19 ) /* Reserved */
+#define AT91C_ID_20_Reserved    ( 20 ) /* Reserved */
+#define AT91C_ID_21_Reserved    ( 21 ) /* Reserved */
+#define AT91C_ID_22_Reserved    ( 22 ) /* Reserved */
+#define AT91C_ID_23_Reserved    ( 23 ) /* Reserved */
+#define AT91C_ID_24_Reserved    ( 24 ) /* Reserved */
+#define AT91C_ID_25_Reserved    ( 25 ) /* Reserved */
+#define AT91C_ID_26_Reserved    ( 26 ) /* Reserved */
+#define AT91C_ID_27_Reserved    ( 27 ) /* Reserved */
+#define AT91C_ID_28_Reserved    ( 28 ) /* Reserved */
+#define AT91C_ID_29_Reserved    ( 29 ) /* Reserved */
+#define AT91C_ID_IRQ0           ( 30 ) /* Advanced Interrupt Controller (IRQ0) */
+#define AT91C_ID_IRQ1           ( 31 ) /* Advanced Interrupt Controller (IRQ1) */
 
-// *****************************************************************************
-//               BASE ADDRESS DEFINITIONS FOR AT91SAM7S64
-// *****************************************************************************
-#define AT91C_BASE_SYSC           (0xFFFFF000) // (SYSC) Base Address
-#define AT91C_BASE_AIC            (0xFFFFF000) // (AIC) Base Address
-#define AT91C_BASE_DBGU           (0xFFFFF200) // (DBGU) Base Address
-#define AT91C_BASE_PDC_DBGU       (0xFFFFF300) // (PDC_DBGU) Base Address
-#define AT91C_BASE_PIOA           (0xFFFFF400) // (PIOA) Base Address
-#define AT91C_BASE_CKGR           (0xFFFFFC20) // (CKGR) Base Address
-#define AT91C_BASE_PMC            (0xFFFFFC00) // (PMC) Base Address
-#define AT91C_BASE_RSTC           (0xFFFFFD00) // (RSTC) Base Address
-#define AT91C_BASE_RTTC           (0xFFFFFD20) // (RTTC) Base Address
-#define AT91C_BASE_PITC           (0xFFFFFD30) // (PITC) Base Address
-#define AT91C_BASE_WDTC           (0xFFFFFD40) // (WDTC) Base Address
-#define AT91C_BASE_MC             (0xFFFFFF00) // (MC) Base Address
-#define AT91C_BASE_PDC_SPI        (0xFFFE0100) // (PDC_SPI) Base Address
-#define AT91C_BASE_SPI            (0xFFFE0000) // (SPI) Base Address
-#define AT91C_BASE_PDC_ADC        (0xFFFD8100) // (PDC_ADC) Base Address
-#define AT91C_BASE_ADC            (0xFFFD8000) // (ADC) Base Address
-#define AT91C_BASE_PDC_SSC        (0xFFFD4100) // (PDC_SSC) Base Address
-#define AT91C_BASE_SSC            (0xFFFD4000) // (SSC) Base Address
-#define AT91C_BASE_PDC_US1        (0xFFFC4100) // (PDC_US1) Base Address
-#define AT91C_BASE_US1            (0xFFFC4000) // (US1) Base Address
-#define AT91C_BASE_PDC_US0        (0xFFFC0100) // (PDC_US0) Base Address
-#define AT91C_BASE_US0            (0xFFFC0000) // (US0) Base Address
-#define AT91C_BASE_TWI            (0xFFFB8000) // (TWI) Base Address
-#define AT91C_BASE_TC2            (0xFFFA0080) // (TC2) Base Address
-#define AT91C_BASE_TC1            (0xFFFA0040) // (TC1) Base Address
-#define AT91C_BASE_TC0            (0xFFFA0000) // (TC0) Base Address
-#define AT91C_BASE_TCB            (0xFFFA0000) // (TCB) Base Address
-#define AT91C_BASE_PWMC_CH3       (0xFFFCC260) // (PWMC_CH3) Base Address
-#define AT91C_BASE_PWMC_CH2       (0xFFFCC240) // (PWMC_CH2) Base Address
-#define AT91C_BASE_PWMC_CH1       (0xFFFCC220) // (PWMC_CH1) Base Address
-#define AT91C_BASE_PWMC_CH0       (0xFFFCC200) // (PWMC_CH0) Base Address
-#define AT91C_BASE_PWMC           (0xFFFCC000) // (PWMC) Base Address
-#define AT91C_BASE_UDP            (0xFFFB0000) // (UDP) Base Address
+/* ***************************************************************************** */
+/*               BASE ADDRESS DEFINITIONS FOR AT91SAM7S64 */
+/* ***************************************************************************** */
+#define AT91C_BASE_SYSC        ( 0xFFFFF000 )  /* (SYSC) Base Address */
+#define AT91C_BASE_AIC         ( 0xFFFFF000 )  /* (AIC) Base Address */
+#define AT91C_BASE_DBGU        ( 0xFFFFF200 )  /* (DBGU) Base Address */
+#define AT91C_BASE_PDC_DBGU    ( 0xFFFFF300 )  /* (PDC_DBGU) Base Address */
+#define AT91C_BASE_PIOA        ( 0xFFFFF400 )  /* (PIOA) Base Address */
+#define AT91C_BASE_CKGR        ( 0xFFFFFC20 )  /* (CKGR) Base Address */
+#define AT91C_BASE_PMC         ( 0xFFFFFC00 )  /* (PMC) Base Address */
+#define AT91C_BASE_RSTC        ( 0xFFFFFD00 )  /* (RSTC) Base Address */
+#define AT91C_BASE_RTTC        ( 0xFFFFFD20 )  /* (RTTC) Base Address */
+#define AT91C_BASE_PITC        ( 0xFFFFFD30 )  /* (PITC) Base Address */
+#define AT91C_BASE_WDTC        ( 0xFFFFFD40 )  /* (WDTC) Base Address */
+#define AT91C_BASE_MC          ( 0xFFFFFF00 )  /* (MC) Base Address */
+#define AT91C_BASE_PDC_SPI     ( 0xFFFE0100 )  /* (PDC_SPI) Base Address */
+#define AT91C_BASE_SPI         ( 0xFFFE0000 )  /* (SPI) Base Address */
+#define AT91C_BASE_PDC_ADC     ( 0xFFFD8100 )  /* (PDC_ADC) Base Address */
+#define AT91C_BASE_ADC         ( 0xFFFD8000 )  /* (ADC) Base Address */
+#define AT91C_BASE_PDC_SSC     ( 0xFFFD4100 )  /* (PDC_SSC) Base Address */
+#define AT91C_BASE_SSC         ( 0xFFFD4000 )  /* (SSC) Base Address */
+#define AT91C_BASE_PDC_US1     ( 0xFFFC4100 )  /* (PDC_US1) Base Address */
+#define AT91C_BASE_US1         ( 0xFFFC4000 )  /* (US1) Base Address */
+#define AT91C_BASE_PDC_US0     ( 0xFFFC0100 )  /* (PDC_US0) Base Address */
+#define AT91C_BASE_US0         ( 0xFFFC0000 )  /* (US0) Base Address */
+#define AT91C_BASE_TWI         ( 0xFFFB8000 )  /* (TWI) Base Address */
+#define AT91C_BASE_TC2         ( 0xFFFA0080 )  /* (TC2) Base Address */
+#define AT91C_BASE_TC1         ( 0xFFFA0040 )  /* (TC1) Base Address */
+#define AT91C_BASE_TC0         ( 0xFFFA0000 )  /* (TC0) Base Address */
+#define AT91C_BASE_TCB         ( 0xFFFA0000 )  /* (TCB) Base Address */
+#define AT91C_BASE_PWMC_CH3    ( 0xFFFCC260 )  /* (PWMC_CH3) Base Address */
+#define AT91C_BASE_PWMC_CH2    ( 0xFFFCC240 )  /* (PWMC_CH2) Base Address */
+#define AT91C_BASE_PWMC_CH1    ( 0xFFFCC220 )  /* (PWMC_CH1) Base Address */
+#define AT91C_BASE_PWMC_CH0    ( 0xFFFCC200 )  /* (PWMC_CH0) Base Address */
+#define AT91C_BASE_PWMC        ( 0xFFFCC000 )  /* (PWMC) Base Address */
+#define AT91C_BASE_UDP         ( 0xFFFB0000 )  /* (UDP) Base Address */
 
-// *****************************************************************************
-//               MEMORY MAPPING DEFINITIONS FOR AT91SAM7S64
-// *****************************************************************************
-#define AT91C_ISRAM               (0x00200000) // Internal SRAM base address
-#define AT91C_ISRAM_SIZE             (0x00004000) // Internal SRAM size in byte (16 Kbyte)
-#define AT91C_IFLASH                 (0x00100000) // Internal ROM base address
-#define AT91C_IFLASH_SIZE           (0x00010000) // Internal ROM size in byte (64 Kbyte)
+/* ***************************************************************************** */
+/*               MEMORY MAPPING DEFINITIONS FOR AT91SAM7S64 */
+/* ***************************************************************************** */
+#define AT91C_ISRAM          ( 0x00200000 )    /* Internal SRAM base address */
+#define AT91C_ISRAM_SIZE     ( 0x00004000 )    /* Internal SRAM size in byte (16 Kbyte) */
+#define AT91C_IFLASH         ( 0x00100000 )    /* Internal ROM base address */
+#define AT91C_IFLASH_SIZE    ( 0x00010000 )    /* Internal ROM size in byte (64 Kbyte) */
diff --git a/portable/IAR/AtmelSAM7S64/AT91SAM7X128.h b/portable/IAR/AtmelSAM7S64/AT91SAM7X128.h
index 3ebad2527..b8a7652f4 100644
--- a/portable/IAR/AtmelSAM7S64/AT91SAM7X128.h
+++ b/portable/IAR/AtmelSAM7S64/AT91SAM7X128.h
@@ -1,2715 +1,2743 @@
-//  ----------------------------------------------------------------------------
-//          ATMEL Microcontroller Software Support  -  ROUSSET  -
-//  ----------------------------------------------------------------------------
-//  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
-//  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
-//  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
-//  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
-//  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-//  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-//  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-//  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//  ----------------------------------------------------------------------------
-// File Name           : AT91SAM7X128.h
-// Object              : AT91SAM7X128 definitions
-// Generated           : AT91 SW Application Group  05/20/2005 (16:22:23)
-//
-// CVS Reference       : /AT91SAM7X128.pl/1.14/Tue May 10 12:12:05 2005//
-// CVS Reference       : /SYS_SAM7X.pl/1.3/Tue Feb  1 17:01:43 2005//
-// CVS Reference       : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005//
-// CVS Reference       : /PMC_SAM7X.pl/1.4/Tue Feb  8 13:58:10 2005//
-// CVS Reference       : /RSTC_SAM7X.pl/1.1/Tue Feb  1 16:16:26 2005//
-// CVS Reference       : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005//
-// CVS Reference       : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005//
-// CVS Reference       : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//
-// CVS Reference       : /PIO_6057A.pl/1.2/Thu Feb  3 10:18:28 2005//
-// CVS Reference       : /RTTC_6081A.pl/1.2/Tue Nov  9 14:43:58 2004//
-// CVS Reference       : /PITC_6079A.pl/1.2/Tue Nov  9 14:43:56 2004//
-// CVS Reference       : /WDTC_6080A.pl/1.3/Tue Nov  9 14:44:00 2004//
-// CVS Reference       : /VREG_6085B.pl/1.1/Tue Feb  1 16:05:48 2005//
-// CVS Reference       : /PDC_6074C.pl/1.2/Thu Feb  3 08:48:54 2005//
-// CVS Reference       : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//
-// CVS Reference       : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//
-// CVS Reference       : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//
-// CVS Reference       : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//
-// CVS Reference       : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//
-// CVS Reference       : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//
-// CVS Reference       : /CAN_6019B.pl/1.1/Tue Mar  8 12:42:22 2005//
-// CVS Reference       : /EMACB_6119A.pl/1.5/Thu Feb  3 15:52:04 2005//
-// CVS Reference       : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//
-// CVS Reference       : /AES_6149A.pl/1.10/Mon Feb  7 09:44:25 2005//
-// CVS Reference       : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005//
-//  ----------------------------------------------------------------------------
+/*  ---------------------------------------------------------------------------- */
+/*          ATMEL Microcontroller Software Support  -  ROUSSET  - */
+/*  ---------------------------------------------------------------------------- */
+/*  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
+/*  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
+/*  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
+/*  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
+/*  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
+/*  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
+/*  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/*  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
+/*  ---------------------------------------------------------------------------- */
+/* File Name           : AT91SAM7X128.h */
+/* Object              : AT91SAM7X128 definitions */
+/* Generated           : AT91 SW Application Group  05/20/2005 (16:22:23) */
+/* */
+/* CVS Reference       : /AT91SAM7X128.pl/1.14/Tue May 10 12:12:05 2005// */
+/* CVS Reference       : /SYS_SAM7X.pl/1.3/Tue Feb  1 17:01:43 2005// */
+/* CVS Reference       : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// */
+/* CVS Reference       : /PMC_SAM7X.pl/1.4/Tue Feb  8 13:58:10 2005// */
+/* CVS Reference       : /RSTC_SAM7X.pl/1.1/Tue Feb  1 16:16:26 2005// */
+/* CVS Reference       : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// */
+/* CVS Reference       : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// */
+/* CVS Reference       : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// */
+/* CVS Reference       : /PIO_6057A.pl/1.2/Thu Feb  3 10:18:28 2005// */
+/* CVS Reference       : /RTTC_6081A.pl/1.2/Tue Nov  9 14:43:58 2004// */
+/* CVS Reference       : /PITC_6079A.pl/1.2/Tue Nov  9 14:43:56 2004// */
+/* CVS Reference       : /WDTC_6080A.pl/1.3/Tue Nov  9 14:44:00 2004// */
+/* CVS Reference       : /VREG_6085B.pl/1.1/Tue Feb  1 16:05:48 2005// */
+/* CVS Reference       : /PDC_6074C.pl/1.2/Thu Feb  3 08:48:54 2005// */
+/* CVS Reference       : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// */
+/* CVS Reference       : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// */
+/* CVS Reference       : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// */
+/* CVS Reference       : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// */
+/* CVS Reference       : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// */
+/* CVS Reference       : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// */
+/* CVS Reference       : /CAN_6019B.pl/1.1/Tue Mar  8 12:42:22 2005// */
+/* CVS Reference       : /EMACB_6119A.pl/1.5/Thu Feb  3 15:52:04 2005// */
+/* CVS Reference       : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// */
+/* CVS Reference       : /AES_6149A.pl/1.10/Mon Feb  7 09:44:25 2005// */
+/* CVS Reference       : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// */
+/*  ---------------------------------------------------------------------------- */
 
 #ifndef AT91SAM7X128_H
 #define AT91SAM7X128_H
 
-typedef volatile unsigned int AT91_REG;// Hardware register definition
+typedef volatile unsigned int AT91_REG; /* Hardware register definition */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR System Peripherals
-// *****************************************************************************
-typedef struct _AT91S_SYS {
-    AT91_REG     AIC_SMR[32];   // Source Mode Register
-    AT91_REG     AIC_SVR[32];   // Source Vector Register
-    AT91_REG     AIC_IVR;   // IRQ Vector Register
-    AT91_REG     AIC_FVR;   // FIQ Vector Register
-    AT91_REG     AIC_ISR;   // Interrupt Status Register
-    AT91_REG     AIC_IPR;   // Interrupt Pending Register
-    AT91_REG     AIC_IMR;   // Interrupt Mask Register
-    AT91_REG     AIC_CISR;  // Core Interrupt Status Register
-    AT91_REG     Reserved0[2];  //
-    AT91_REG     AIC_IECR;  // Interrupt Enable Command Register
-    AT91_REG     AIC_IDCR;  // Interrupt Disable Command Register
-    AT91_REG     AIC_ICCR;  // Interrupt Clear Command Register
-    AT91_REG     AIC_ISCR;  // Interrupt Set Command Register
-    AT91_REG     AIC_EOICR;     // End of Interrupt Command Register
-    AT91_REG     AIC_SPU;   // Spurious Vector Register
-    AT91_REG     AIC_DCR;   // Debug Control Register (Protect)
-    AT91_REG     Reserved1[1];  //
-    AT91_REG     AIC_FFER;  // Fast Forcing Enable Register
-    AT91_REG     AIC_FFDR;  // Fast Forcing Disable Register
-    AT91_REG     AIC_FFSR;  // Fast Forcing Status Register
-    AT91_REG     Reserved2[45];     //
-    AT91_REG     DBGU_CR;   // Control Register
-    AT91_REG     DBGU_MR;   // Mode Register
-    AT91_REG     DBGU_IER;  // Interrupt Enable Register
-    AT91_REG     DBGU_IDR;  // Interrupt Disable Register
-    AT91_REG     DBGU_IMR;  // Interrupt Mask Register
-    AT91_REG     DBGU_CSR;  // Channel Status Register
-    AT91_REG     DBGU_RHR;  // Receiver Holding Register
-    AT91_REG     DBGU_THR;  // Transmitter Holding Register
-    AT91_REG     DBGU_BRGR;     // Baud Rate Generator Register
-    AT91_REG     Reserved3[7];  //
-    AT91_REG     DBGU_CIDR;     // Chip ID Register
-    AT91_REG     DBGU_EXID;     // Chip ID Extension Register
-    AT91_REG     DBGU_FNTR;     // Force NTRST Register
-    AT91_REG     Reserved4[45];     //
-    AT91_REG     DBGU_RPR;  // Receive Pointer Register
-    AT91_REG     DBGU_RCR;  // Receive Counter Register
-    AT91_REG     DBGU_TPR;  // Transmit Pointer Register
-    AT91_REG     DBGU_TCR;  // Transmit Counter Register
-    AT91_REG     DBGU_RNPR;     // Receive Next Pointer Register
-    AT91_REG     DBGU_RNCR;     // Receive Next Counter Register
-    AT91_REG     DBGU_TNPR;     // Transmit Next Pointer Register
-    AT91_REG     DBGU_TNCR;     // Transmit Next Counter Register
-    AT91_REG     DBGU_PTCR;     // PDC Transfer Control Register
-    AT91_REG     DBGU_PTSR;     // PDC Transfer Status Register
-    AT91_REG     Reserved5[54];     //
-    AT91_REG     PIOA_PER;  // PIO Enable Register
-    AT91_REG     PIOA_PDR;  // PIO Disable Register
-    AT91_REG     PIOA_PSR;  // PIO Status Register
-    AT91_REG     Reserved6[1];  //
-    AT91_REG     PIOA_OER;  // Output Enable Register
-    AT91_REG     PIOA_ODR;  // Output Disable Registerr
-    AT91_REG     PIOA_OSR;  // Output Status Register
-    AT91_REG     Reserved7[1];  //
-    AT91_REG     PIOA_IFER;     // Input Filter Enable Register
-    AT91_REG     PIOA_IFDR;     // Input Filter Disable Register
-    AT91_REG     PIOA_IFSR;     // Input Filter Status Register
-    AT91_REG     Reserved8[1];  //
-    AT91_REG     PIOA_SODR;     // Set Output Data Register
-    AT91_REG     PIOA_CODR;     // Clear Output Data Register
-    AT91_REG     PIOA_ODSR;     // Output Data Status Register
-    AT91_REG     PIOA_PDSR;     // Pin Data Status Register
-    AT91_REG     PIOA_IER;  // Interrupt Enable Register
-    AT91_REG     PIOA_IDR;  // Interrupt Disable Register
-    AT91_REG     PIOA_IMR;  // Interrupt Mask Register
-    AT91_REG     PIOA_ISR;  // Interrupt Status Register
-    AT91_REG     PIOA_MDER;     // Multi-driver Enable Register
-    AT91_REG     PIOA_MDDR;     // Multi-driver Disable Register
-    AT91_REG     PIOA_MDSR;     // Multi-driver Status Register
-    AT91_REG     Reserved9[1];  //
-    AT91_REG     PIOA_PPUDR;    // Pull-up Disable Register
-    AT91_REG     PIOA_PPUER;    // Pull-up Enable Register
-    AT91_REG     PIOA_PPUSR;    // Pull-up Status Register
-    AT91_REG     Reserved10[1];     //
-    AT91_REG     PIOA_ASR;  // Select A Register
-    AT91_REG     PIOA_BSR;  // Select B Register
-    AT91_REG     PIOA_ABSR;     // AB Select Status Register
-    AT91_REG     Reserved11[9];     //
-    AT91_REG     PIOA_OWER;     // Output Write Enable Register
-    AT91_REG     PIOA_OWDR;     // Output Write Disable Register
-    AT91_REG     PIOA_OWSR;     // Output Write Status Register
-    AT91_REG     Reserved12[85];    //
-    AT91_REG     PIOB_PER;  // PIO Enable Register
-    AT91_REG     PIOB_PDR;  // PIO Disable Register
-    AT91_REG     PIOB_PSR;  // PIO Status Register
-    AT91_REG     Reserved13[1];     //
-    AT91_REG     PIOB_OER;  // Output Enable Register
-    AT91_REG     PIOB_ODR;  // Output Disable Registerr
-    AT91_REG     PIOB_OSR;  // Output Status Register
-    AT91_REG     Reserved14[1];     //
-    AT91_REG     PIOB_IFER;     // Input Filter Enable Register
-    AT91_REG     PIOB_IFDR;     // Input Filter Disable Register
-    AT91_REG     PIOB_IFSR;     // Input Filter Status Register
-    AT91_REG     Reserved15[1];     //
-    AT91_REG     PIOB_SODR;     // Set Output Data Register
-    AT91_REG     PIOB_CODR;     // Clear Output Data Register
-    AT91_REG     PIOB_ODSR;     // Output Data Status Register
-    AT91_REG     PIOB_PDSR;     // Pin Data Status Register
-    AT91_REG     PIOB_IER;  // Interrupt Enable Register
-    AT91_REG     PIOB_IDR;  // Interrupt Disable Register
-    AT91_REG     PIOB_IMR;  // Interrupt Mask Register
-    AT91_REG     PIOB_ISR;  // Interrupt Status Register
-    AT91_REG     PIOB_MDER;     // Multi-driver Enable Register
-    AT91_REG     PIOB_MDDR;     // Multi-driver Disable Register
-    AT91_REG     PIOB_MDSR;     // Multi-driver Status Register
-    AT91_REG     Reserved16[1];     //
-    AT91_REG     PIOB_PPUDR;    // Pull-up Disable Register
-    AT91_REG     PIOB_PPUER;    // Pull-up Enable Register
-    AT91_REG     PIOB_PPUSR;    // Pull-up Status Register
-    AT91_REG     Reserved17[1];     //
-    AT91_REG     PIOB_ASR;  // Select A Register
-    AT91_REG     PIOB_BSR;  // Select B Register
-    AT91_REG     PIOB_ABSR;     // AB Select Status Register
-    AT91_REG     Reserved18[9];     //
-    AT91_REG     PIOB_OWER;     // Output Write Enable Register
-    AT91_REG     PIOB_OWDR;     // Output Write Disable Register
-    AT91_REG     PIOB_OWSR;     // Output Write Status Register
-    AT91_REG     Reserved19[341];   //
-    AT91_REG     PMC_SCER;  // System Clock Enable Register
-    AT91_REG     PMC_SCDR;  // System Clock Disable Register
-    AT91_REG     PMC_SCSR;  // System Clock Status Register
-    AT91_REG     Reserved20[1];     //
-    AT91_REG     PMC_PCER;  // Peripheral Clock Enable Register
-    AT91_REG     PMC_PCDR;  // Peripheral Clock Disable Register
-    AT91_REG     PMC_PCSR;  // Peripheral Clock Status Register
-    AT91_REG     Reserved21[1];     //
-    AT91_REG     PMC_MOR;   // Main Oscillator Register
-    AT91_REG     PMC_MCFR;  // Main Clock  Frequency Register
-    AT91_REG     Reserved22[1];     //
-    AT91_REG     PMC_PLLR;  // PLL Register
-    AT91_REG     PMC_MCKR;  // Master Clock Register
-    AT91_REG     Reserved23[3];     //
-    AT91_REG     PMC_PCKR[4];   // Programmable Clock Register
-    AT91_REG     Reserved24[4];     //
-    AT91_REG     PMC_IER;   // Interrupt Enable Register
-    AT91_REG     PMC_IDR;   // Interrupt Disable Register
-    AT91_REG     PMC_SR;    // Status Register
-    AT91_REG     PMC_IMR;   // Interrupt Mask Register
-    AT91_REG     Reserved25[36];    //
-    AT91_REG     RSTC_RCR;  // Reset Control Register
-    AT91_REG     RSTC_RSR;  // Reset Status Register
-    AT91_REG     RSTC_RMR;  // Reset Mode Register
-    AT91_REG     Reserved26[5];     //
-    AT91_REG     RTTC_RTMR;     // Real-time Mode Register
-    AT91_REG     RTTC_RTAR;     // Real-time Alarm Register
-    AT91_REG     RTTC_RTVR;     // Real-time Value Register
-    AT91_REG     RTTC_RTSR;     // Real-time Status Register
-    AT91_REG     PITC_PIMR;     // Period Interval Mode Register
-    AT91_REG     PITC_PISR;     // Period Interval Status Register
-    AT91_REG     PITC_PIVR;     // Period Interval Value Register
-    AT91_REG     PITC_PIIR;     // Period Interval Image Register
-    AT91_REG     WDTC_WDCR;     // Watchdog Control Register
-    AT91_REG     WDTC_WDMR;     // Watchdog Mode Register
-    AT91_REG     WDTC_WDSR;     // Watchdog Status Register
-    AT91_REG     Reserved27[5];     //
-    AT91_REG     VREG_MR;   // Voltage Regulator Mode Register
-} AT91S_SYS, *AT91PS_SYS;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR System Peripherals */
+/* ***************************************************************************** */
+typedef struct _AT91S_SYS
+{
+    AT91_REG AIC_SMR[ 32 ];     /* Source Mode Register */
+    AT91_REG AIC_SVR[ 32 ];     /* Source Vector Register */
+    AT91_REG AIC_IVR;           /* IRQ Vector Register */
+    AT91_REG AIC_FVR;           /* FIQ Vector Register */
+    AT91_REG AIC_ISR;           /* Interrupt Status Register */
+    AT91_REG AIC_IPR;           /* Interrupt Pending Register */
+    AT91_REG AIC_IMR;           /* Interrupt Mask Register */
+    AT91_REG AIC_CISR;          /* Core Interrupt Status Register */
+    AT91_REG Reserved0[ 2 ];    /* */
+    AT91_REG AIC_IECR;          /* Interrupt Enable Command Register */
+    AT91_REG AIC_IDCR;          /* Interrupt Disable Command Register */
+    AT91_REG AIC_ICCR;          /* Interrupt Clear Command Register */
+    AT91_REG AIC_ISCR;          /* Interrupt Set Command Register */
+    AT91_REG AIC_EOICR;         /* End of Interrupt Command Register */
+    AT91_REG AIC_SPU;           /* Spurious Vector Register */
+    AT91_REG AIC_DCR;           /* Debug Control Register (Protect) */
+    AT91_REG Reserved1[ 1 ];    /* */
+    AT91_REG AIC_FFER;          /* Fast Forcing Enable Register */
+    AT91_REG AIC_FFDR;          /* Fast Forcing Disable Register */
+    AT91_REG AIC_FFSR;          /* Fast Forcing Status Register */
+    AT91_REG Reserved2[ 45 ];   /* */
+    AT91_REG DBGU_CR;           /* Control Register */
+    AT91_REG DBGU_MR;           /* Mode Register */
+    AT91_REG DBGU_IER;          /* Interrupt Enable Register */
+    AT91_REG DBGU_IDR;          /* Interrupt Disable Register */
+    AT91_REG DBGU_IMR;          /* Interrupt Mask Register */
+    AT91_REG DBGU_CSR;          /* Channel Status Register */
+    AT91_REG DBGU_RHR;          /* Receiver Holding Register */
+    AT91_REG DBGU_THR;          /* Transmitter Holding Register */
+    AT91_REG DBGU_BRGR;         /* Baud Rate Generator Register */
+    AT91_REG Reserved3[ 7 ];    /* */
+    AT91_REG DBGU_CIDR;         /* Chip ID Register */
+    AT91_REG DBGU_EXID;         /* Chip ID Extension Register */
+    AT91_REG DBGU_FNTR;         /* Force NTRST Register */
+    AT91_REG Reserved4[ 45 ];   /* */
+    AT91_REG DBGU_RPR;          /* Receive Pointer Register */
+    AT91_REG DBGU_RCR;          /* Receive Counter Register */
+    AT91_REG DBGU_TPR;          /* Transmit Pointer Register */
+    AT91_REG DBGU_TCR;          /* Transmit Counter Register */
+    AT91_REG DBGU_RNPR;         /* Receive Next Pointer Register */
+    AT91_REG DBGU_RNCR;         /* Receive Next Counter Register */
+    AT91_REG DBGU_TNPR;         /* Transmit Next Pointer Register */
+    AT91_REG DBGU_TNCR;         /* Transmit Next Counter Register */
+    AT91_REG DBGU_PTCR;         /* PDC Transfer Control Register */
+    AT91_REG DBGU_PTSR;         /* PDC Transfer Status Register */
+    AT91_REG Reserved5[ 54 ];   /* */
+    AT91_REG PIOA_PER;          /* PIO Enable Register */
+    AT91_REG PIOA_PDR;          /* PIO Disable Register */
+    AT91_REG PIOA_PSR;          /* PIO Status Register */
+    AT91_REG Reserved6[ 1 ];    /* */
+    AT91_REG PIOA_OER;          /* Output Enable Register */
+    AT91_REG PIOA_ODR;          /* Output Disable Registerr */
+    AT91_REG PIOA_OSR;          /* Output Status Register */
+    AT91_REG Reserved7[ 1 ];    /* */
+    AT91_REG PIOA_IFER;         /* Input Filter Enable Register */
+    AT91_REG PIOA_IFDR;         /* Input Filter Disable Register */
+    AT91_REG PIOA_IFSR;         /* Input Filter Status Register */
+    AT91_REG Reserved8[ 1 ];    /* */
+    AT91_REG PIOA_SODR;         /* Set Output Data Register */
+    AT91_REG PIOA_CODR;         /* Clear Output Data Register */
+    AT91_REG PIOA_ODSR;         /* Output Data Status Register */
+    AT91_REG PIOA_PDSR;         /* Pin Data Status Register */
+    AT91_REG PIOA_IER;          /* Interrupt Enable Register */
+    AT91_REG PIOA_IDR;          /* Interrupt Disable Register */
+    AT91_REG PIOA_IMR;          /* Interrupt Mask Register */
+    AT91_REG PIOA_ISR;          /* Interrupt Status Register */
+    AT91_REG PIOA_MDER;         /* Multi-driver Enable Register */
+    AT91_REG PIOA_MDDR;         /* Multi-driver Disable Register */
+    AT91_REG PIOA_MDSR;         /* Multi-driver Status Register */
+    AT91_REG Reserved9[ 1 ];    /* */
+    AT91_REG PIOA_PPUDR;        /* Pull-up Disable Register */
+    AT91_REG PIOA_PPUER;        /* Pull-up Enable Register */
+    AT91_REG PIOA_PPUSR;        /* Pull-up Status Register */
+    AT91_REG Reserved10[ 1 ];   /* */
+    AT91_REG PIOA_ASR;          /* Select A Register */
+    AT91_REG PIOA_BSR;          /* Select B Register */
+    AT91_REG PIOA_ABSR;         /* AB Select Status Register */
+    AT91_REG Reserved11[ 9 ];   /* */
+    AT91_REG PIOA_OWER;         /* Output Write Enable Register */
+    AT91_REG PIOA_OWDR;         /* Output Write Disable Register */
+    AT91_REG PIOA_OWSR;         /* Output Write Status Register */
+    AT91_REG Reserved12[ 85 ];  /* */
+    AT91_REG PIOB_PER;          /* PIO Enable Register */
+    AT91_REG PIOB_PDR;          /* PIO Disable Register */
+    AT91_REG PIOB_PSR;          /* PIO Status Register */
+    AT91_REG Reserved13[ 1 ];   /* */
+    AT91_REG PIOB_OER;          /* Output Enable Register */
+    AT91_REG PIOB_ODR;          /* Output Disable Registerr */
+    AT91_REG PIOB_OSR;          /* Output Status Register */
+    AT91_REG Reserved14[ 1 ];   /* */
+    AT91_REG PIOB_IFER;         /* Input Filter Enable Register */
+    AT91_REG PIOB_IFDR;         /* Input Filter Disable Register */
+    AT91_REG PIOB_IFSR;         /* Input Filter Status Register */
+    AT91_REG Reserved15[ 1 ];   /* */
+    AT91_REG PIOB_SODR;         /* Set Output Data Register */
+    AT91_REG PIOB_CODR;         /* Clear Output Data Register */
+    AT91_REG PIOB_ODSR;         /* Output Data Status Register */
+    AT91_REG PIOB_PDSR;         /* Pin Data Status Register */
+    AT91_REG PIOB_IER;          /* Interrupt Enable Register */
+    AT91_REG PIOB_IDR;          /* Interrupt Disable Register */
+    AT91_REG PIOB_IMR;          /* Interrupt Mask Register */
+    AT91_REG PIOB_ISR;          /* Interrupt Status Register */
+    AT91_REG PIOB_MDER;         /* Multi-driver Enable Register */
+    AT91_REG PIOB_MDDR;         /* Multi-driver Disable Register */
+    AT91_REG PIOB_MDSR;         /* Multi-driver Status Register */
+    AT91_REG Reserved16[ 1 ];   /* */
+    AT91_REG PIOB_PPUDR;        /* Pull-up Disable Register */
+    AT91_REG PIOB_PPUER;        /* Pull-up Enable Register */
+    AT91_REG PIOB_PPUSR;        /* Pull-up Status Register */
+    AT91_REG Reserved17[ 1 ];   /* */
+    AT91_REG PIOB_ASR;          /* Select A Register */
+    AT91_REG PIOB_BSR;          /* Select B Register */
+    AT91_REG PIOB_ABSR;         /* AB Select Status Register */
+    AT91_REG Reserved18[ 9 ];   /* */
+    AT91_REG PIOB_OWER;         /* Output Write Enable Register */
+    AT91_REG PIOB_OWDR;         /* Output Write Disable Register */
+    AT91_REG PIOB_OWSR;         /* Output Write Status Register */
+    AT91_REG Reserved19[ 341 ]; /* */
+    AT91_REG PMC_SCER;          /* System Clock Enable Register */
+    AT91_REG PMC_SCDR;          /* System Clock Disable Register */
+    AT91_REG PMC_SCSR;          /* System Clock Status Register */
+    AT91_REG Reserved20[ 1 ];   /* */
+    AT91_REG PMC_PCER;          /* Peripheral Clock Enable Register */
+    AT91_REG PMC_PCDR;          /* Peripheral Clock Disable Register */
+    AT91_REG PMC_PCSR;          /* Peripheral Clock Status Register */
+    AT91_REG Reserved21[ 1 ];   /* */
+    AT91_REG PMC_MOR;           /* Main Oscillator Register */
+    AT91_REG PMC_MCFR;          /* Main Clock  Frequency Register */
+    AT91_REG Reserved22[ 1 ];   /* */
+    AT91_REG PMC_PLLR;          /* PLL Register */
+    AT91_REG PMC_MCKR;          /* Master Clock Register */
+    AT91_REG Reserved23[ 3 ];   /* */
+    AT91_REG PMC_PCKR[ 4 ];     /* Programmable Clock Register */
+    AT91_REG Reserved24[ 4 ];   /* */
+    AT91_REG PMC_IER;           /* Interrupt Enable Register */
+    AT91_REG PMC_IDR;           /* Interrupt Disable Register */
+    AT91_REG PMC_SR;            /* Status Register */
+    AT91_REG PMC_IMR;           /* Interrupt Mask Register */
+    AT91_REG Reserved25[ 36 ];  /* */
+    AT91_REG RSTC_RCR;          /* Reset Control Register */
+    AT91_REG RSTC_RSR;          /* Reset Status Register */
+    AT91_REG RSTC_RMR;          /* Reset Mode Register */
+    AT91_REG Reserved26[ 5 ];   /* */
+    AT91_REG RTTC_RTMR;         /* Real-time Mode Register */
+    AT91_REG RTTC_RTAR;         /* Real-time Alarm Register */
+    AT91_REG RTTC_RTVR;         /* Real-time Value Register */
+    AT91_REG RTTC_RTSR;         /* Real-time Status Register */
+    AT91_REG PITC_PIMR;         /* Period Interval Mode Register */
+    AT91_REG PITC_PISR;         /* Period Interval Status Register */
+    AT91_REG PITC_PIVR;         /* Period Interval Value Register */
+    AT91_REG PITC_PIIR;         /* Period Interval Image Register */
+    AT91_REG WDTC_WDCR;         /* Watchdog Control Register */
+    AT91_REG WDTC_WDMR;         /* Watchdog Mode Register */
+    AT91_REG WDTC_WDSR;         /* Watchdog Status Register */
+    AT91_REG Reserved27[ 5 ];   /* */
+    AT91_REG VREG_MR;           /* Voltage Regulator Mode Register */
+} AT91S_SYS, * AT91PS_SYS;
 
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
-// *****************************************************************************
-typedef struct _AT91S_AIC {
-    AT91_REG     AIC_SMR[32];   // Source Mode Register
-    AT91_REG     AIC_SVR[32];   // Source Vector Register
-    AT91_REG     AIC_IVR;   // IRQ Vector Register
-    AT91_REG     AIC_FVR;   // FIQ Vector Register
-    AT91_REG     AIC_ISR;   // Interrupt Status Register
-    AT91_REG     AIC_IPR;   // Interrupt Pending Register
-    AT91_REG     AIC_IMR;   // Interrupt Mask Register
-    AT91_REG     AIC_CISR;  // Core Interrupt Status Register
-    AT91_REG     Reserved0[2];  //
-    AT91_REG     AIC_IECR;  // Interrupt Enable Command Register
-    AT91_REG     AIC_IDCR;  // Interrupt Disable Command Register
-    AT91_REG     AIC_ICCR;  // Interrupt Clear Command Register
-    AT91_REG     AIC_ISCR;  // Interrupt Set Command Register
-    AT91_REG     AIC_EOICR;     // End of Interrupt Command Register
-    AT91_REG     AIC_SPU;   // Spurious Vector Register
-    AT91_REG     AIC_DCR;   // Debug Control Register (Protect)
-    AT91_REG     Reserved1[1];  //
-    AT91_REG     AIC_FFER;  // Fast Forcing Enable Register
-    AT91_REG     AIC_FFDR;  // Fast Forcing Disable Register
-    AT91_REG     AIC_FFSR;  // Fast Forcing Status Register
-} AT91S_AIC, *AT91PS_AIC;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller */
+/* ***************************************************************************** */
+typedef struct _AT91S_AIC
+{
+    AT91_REG AIC_SMR[ 32 ];  /* Source Mode Register */
+    AT91_REG AIC_SVR[ 32 ];  /* Source Vector Register */
+    AT91_REG AIC_IVR;        /* IRQ Vector Register */
+    AT91_REG AIC_FVR;        /* FIQ Vector Register */
+    AT91_REG AIC_ISR;        /* Interrupt Status Register */
+    AT91_REG AIC_IPR;        /* Interrupt Pending Register */
+    AT91_REG AIC_IMR;        /* Interrupt Mask Register */
+    AT91_REG AIC_CISR;       /* Core Interrupt Status Register */
+    AT91_REG Reserved0[ 2 ]; /* */
+    AT91_REG AIC_IECR;       /* Interrupt Enable Command Register */
+    AT91_REG AIC_IDCR;       /* Interrupt Disable Command Register */
+    AT91_REG AIC_ICCR;       /* Interrupt Clear Command Register */
+    AT91_REG AIC_ISCR;       /* Interrupt Set Command Register */
+    AT91_REG AIC_EOICR;      /* End of Interrupt Command Register */
+    AT91_REG AIC_SPU;        /* Spurious Vector Register */
+    AT91_REG AIC_DCR;        /* Debug Control Register (Protect) */
+    AT91_REG Reserved1[ 1 ]; /* */
+    AT91_REG AIC_FFER;       /* Fast Forcing Enable Register */
+    AT91_REG AIC_FFDR;       /* Fast Forcing Disable Register */
+    AT91_REG AIC_FFSR;       /* Fast Forcing Status Register */
+} AT91S_AIC, * AT91PS_AIC;
 
-// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
-#define AT91C_AIC_PRIOR       ((unsigned int) 0x7 <<  0) // (AIC) Priority Level
-#define     AT91C_AIC_PRIOR_LOWEST               ((unsigned int) 0x0) // (AIC) Lowest priority level
-#define     AT91C_AIC_PRIOR_HIGHEST              ((unsigned int) 0x7) // (AIC) Highest priority level
-#define AT91C_AIC_SRCTYPE     ((unsigned int) 0x3 <<  5) // (AIC) Interrupt Source Type
-#define     AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL       ((unsigned int) 0x0 <<  5) // (AIC) Internal Sources Code Label High-level Sensitive
-#define     AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL        ((unsigned int) 0x0 <<  5) // (AIC) External Sources Code Label Low-level Sensitive
-#define     AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE    ((unsigned int) 0x1 <<  5) // (AIC) Internal Sources Code Label Positive Edge triggered
-#define     AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE    ((unsigned int) 0x1 <<  5) // (AIC) External Sources Code Label Negative Edge triggered
-#define     AT91C_AIC_SRCTYPE_HIGH_LEVEL           ((unsigned int) 0x2 <<  5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
-#define     AT91C_AIC_SRCTYPE_POSITIVE_EDGE        ((unsigned int) 0x3 <<  5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
-// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
-#define AT91C_AIC_NFIQ        ((unsigned int) 0x1 <<  0) // (AIC) NFIQ Status
-#define AT91C_AIC_NIRQ        ((unsigned int) 0x1 <<  1) // (AIC) NIRQ Status
-// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
-#define AT91C_AIC_DCR_PROT    ((unsigned int) 0x1 <<  0) // (AIC) Protection Mode
-#define AT91C_AIC_DCR_GMSK    ((unsigned int) 0x1 <<  1) // (AIC) General Mask
+/* -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- */
+#define AT91C_AIC_PRIOR                            ( ( unsigned int ) 0x7 << 0 ) /* (AIC) Priority Level */
+#define     AT91C_AIC_PRIOR_LOWEST                 ( ( unsigned int ) 0x0 )      /* (AIC) Lowest priority level */
+#define     AT91C_AIC_PRIOR_HIGHEST                ( ( unsigned int ) 0x7 )      /* (AIC) Highest priority level */
+#define AT91C_AIC_SRCTYPE                          ( ( unsigned int ) 0x3 << 5 ) /* (AIC) Interrupt Source Type */
+#define     AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL       ( ( unsigned int ) 0x0 << 5 ) /* (AIC) Internal Sources Code Label High-level Sensitive */
+#define     AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL        ( ( unsigned int ) 0x0 << 5 ) /* (AIC) External Sources Code Label Low-level Sensitive */
+#define     AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE    ( ( unsigned int ) 0x1 << 5 ) /* (AIC) Internal Sources Code Label Positive Edge triggered */
+#define     AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE    ( ( unsigned int ) 0x1 << 5 ) /* (AIC) External Sources Code Label Negative Edge triggered */
+#define     AT91C_AIC_SRCTYPE_HIGH_LEVEL           ( ( unsigned int ) 0x2 << 5 ) /* (AIC) Internal Or External Sources Code Label High-level Sensitive */
+#define     AT91C_AIC_SRCTYPE_POSITIVE_EDGE        ( ( unsigned int ) 0x3 << 5 ) /* (AIC) Internal Or External Sources Code Label Positive Edge triggered */
+/* -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- */
+#define AT91C_AIC_NFIQ                             ( ( unsigned int ) 0x1 << 0 ) /* (AIC) NFIQ Status */
+#define AT91C_AIC_NIRQ                             ( ( unsigned int ) 0x1 << 1 ) /* (AIC) NIRQ Status */
+/* -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- */
+#define AT91C_AIC_DCR_PROT                         ( ( unsigned int ) 0x1 << 0 ) /* (AIC) Protection Mode */
+#define AT91C_AIC_DCR_GMSK                         ( ( unsigned int ) 0x1 << 1 ) /* (AIC) General Mask */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller
-// *****************************************************************************
-typedef struct _AT91S_PDC {
-    AT91_REG     PDC_RPR;   // Receive Pointer Register
-    AT91_REG     PDC_RCR;   // Receive Counter Register
-    AT91_REG     PDC_TPR;   // Transmit Pointer Register
-    AT91_REG     PDC_TCR;   // Transmit Counter Register
-    AT91_REG     PDC_RNPR;  // Receive Next Pointer Register
-    AT91_REG     PDC_RNCR;  // Receive Next Counter Register
-    AT91_REG     PDC_TNPR;  // Transmit Next Pointer Register
-    AT91_REG     PDC_TNCR;  // Transmit Next Counter Register
-    AT91_REG     PDC_PTCR;  // PDC Transfer Control Register
-    AT91_REG     PDC_PTSR;  // PDC Transfer Status Register
-} AT91S_PDC, *AT91PS_PDC;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller */
+/* ***************************************************************************** */
+typedef struct _AT91S_PDC
+{
+    AT91_REG PDC_RPR;  /* Receive Pointer Register */
+    AT91_REG PDC_RCR;  /* Receive Counter Register */
+    AT91_REG PDC_TPR;  /* Transmit Pointer Register */
+    AT91_REG PDC_TCR;  /* Transmit Counter Register */
+    AT91_REG PDC_RNPR; /* Receive Next Pointer Register */
+    AT91_REG PDC_RNCR; /* Receive Next Counter Register */
+    AT91_REG PDC_TNPR; /* Transmit Next Pointer Register */
+    AT91_REG PDC_TNCR; /* Transmit Next Counter Register */
+    AT91_REG PDC_PTCR; /* PDC Transfer Control Register */
+    AT91_REG PDC_PTSR; /* PDC Transfer Status Register */
+} AT91S_PDC, * AT91PS_PDC;
 
-// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
-#define AT91C_PDC_RXTEN       ((unsigned int) 0x1 <<  0) // (PDC) Receiver Transfer Enable
-#define AT91C_PDC_RXTDIS      ((unsigned int) 0x1 <<  1) // (PDC) Receiver Transfer Disable
-#define AT91C_PDC_TXTEN       ((unsigned int) 0x1 <<  8) // (PDC) Transmitter Transfer Enable
-#define AT91C_PDC_TXTDIS      ((unsigned int) 0x1 <<  9) // (PDC) Transmitter Transfer Disable
-// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
+/* -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */
+#define AT91C_PDC_RXTEN     ( ( unsigned int ) 0x1 << 0 ) /* (PDC) Receiver Transfer Enable */
+#define AT91C_PDC_RXTDIS    ( ( unsigned int ) 0x1 << 1 ) /* (PDC) Receiver Transfer Disable */
+#define AT91C_PDC_TXTEN     ( ( unsigned int ) 0x1 << 8 ) /* (PDC) Transmitter Transfer Enable */
+#define AT91C_PDC_TXTDIS    ( ( unsigned int ) 0x1 << 9 ) /* (PDC) Transmitter Transfer Disable */
+/* -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Debug Unit
-// *****************************************************************************
-typedef struct _AT91S_DBGU {
-    AT91_REG     DBGU_CR;   // Control Register
-    AT91_REG     DBGU_MR;   // Mode Register
-    AT91_REG     DBGU_IER;  // Interrupt Enable Register
-    AT91_REG     DBGU_IDR;  // Interrupt Disable Register
-    AT91_REG     DBGU_IMR;  // Interrupt Mask Register
-    AT91_REG     DBGU_CSR;  // Channel Status Register
-    AT91_REG     DBGU_RHR;  // Receiver Holding Register
-    AT91_REG     DBGU_THR;  // Transmitter Holding Register
-    AT91_REG     DBGU_BRGR;     // Baud Rate Generator Register
-    AT91_REG     Reserved0[7];  //
-    AT91_REG     DBGU_CIDR;     // Chip ID Register
-    AT91_REG     DBGU_EXID;     // Chip ID Extension Register
-    AT91_REG     DBGU_FNTR;     // Force NTRST Register
-    AT91_REG     Reserved1[45];     //
-    AT91_REG     DBGU_RPR;  // Receive Pointer Register
-    AT91_REG     DBGU_RCR;  // Receive Counter Register
-    AT91_REG     DBGU_TPR;  // Transmit Pointer Register
-    AT91_REG     DBGU_TCR;  // Transmit Counter Register
-    AT91_REG     DBGU_RNPR;     // Receive Next Pointer Register
-    AT91_REG     DBGU_RNCR;     // Receive Next Counter Register
-    AT91_REG     DBGU_TNPR;     // Transmit Next Pointer Register
-    AT91_REG     DBGU_TNCR;     // Transmit Next Counter Register
-    AT91_REG     DBGU_PTCR;     // PDC Transfer Control Register
-    AT91_REG     DBGU_PTSR;     // PDC Transfer Status Register
-} AT91S_DBGU, *AT91PS_DBGU;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Debug Unit */
+/* ***************************************************************************** */
+typedef struct _AT91S_DBGU
+{
+    AT91_REG DBGU_CR;         /* Control Register */
+    AT91_REG DBGU_MR;         /* Mode Register */
+    AT91_REG DBGU_IER;        /* Interrupt Enable Register */
+    AT91_REG DBGU_IDR;        /* Interrupt Disable Register */
+    AT91_REG DBGU_IMR;        /* Interrupt Mask Register */
+    AT91_REG DBGU_CSR;        /* Channel Status Register */
+    AT91_REG DBGU_RHR;        /* Receiver Holding Register */
+    AT91_REG DBGU_THR;        /* Transmitter Holding Register */
+    AT91_REG DBGU_BRGR;       /* Baud Rate Generator Register */
+    AT91_REG Reserved0[ 7 ];  /* */
+    AT91_REG DBGU_CIDR;       /* Chip ID Register */
+    AT91_REG DBGU_EXID;       /* Chip ID Extension Register */
+    AT91_REG DBGU_FNTR;       /* Force NTRST Register */
+    AT91_REG Reserved1[ 45 ]; /* */
+    AT91_REG DBGU_RPR;        /* Receive Pointer Register */
+    AT91_REG DBGU_RCR;        /* Receive Counter Register */
+    AT91_REG DBGU_TPR;        /* Transmit Pointer Register */
+    AT91_REG DBGU_TCR;        /* Transmit Counter Register */
+    AT91_REG DBGU_RNPR;       /* Receive Next Pointer Register */
+    AT91_REG DBGU_RNCR;       /* Receive Next Counter Register */
+    AT91_REG DBGU_TNPR;       /* Transmit Next Pointer Register */
+    AT91_REG DBGU_TNCR;       /* Transmit Next Counter Register */
+    AT91_REG DBGU_PTCR;       /* PDC Transfer Control Register */
+    AT91_REG DBGU_PTSR;       /* PDC Transfer Status Register */
+} AT91S_DBGU, * AT91PS_DBGU;
 
-// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
-#define AT91C_US_RSTRX        ((unsigned int) 0x1 <<  2) // (DBGU) Reset Receiver
-#define AT91C_US_RSTTX        ((unsigned int) 0x1 <<  3) // (DBGU) Reset Transmitter
-#define AT91C_US_RXEN         ((unsigned int) 0x1 <<  4) // (DBGU) Receiver Enable
-#define AT91C_US_RXDIS        ((unsigned int) 0x1 <<  5) // (DBGU) Receiver Disable
-#define AT91C_US_TXEN         ((unsigned int) 0x1 <<  6) // (DBGU) Transmitter Enable
-#define AT91C_US_TXDIS        ((unsigned int) 0x1 <<  7) // (DBGU) Transmitter Disable
-#define AT91C_US_RSTSTA       ((unsigned int) 0x1 <<  8) // (DBGU) Reset Status Bits
-// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
-#define AT91C_US_PAR          ((unsigned int) 0x7 <<  9) // (DBGU) Parity type
-#define     AT91C_US_PAR_EVEN                 ((unsigned int) 0x0 <<  9) // (DBGU) Even Parity
-#define     AT91C_US_PAR_ODD                  ((unsigned int) 0x1 <<  9) // (DBGU) Odd Parity
-#define     AT91C_US_PAR_SPACE                ((unsigned int) 0x2 <<  9) // (DBGU) Parity forced to 0 (Space)
-#define     AT91C_US_PAR_MARK                 ((unsigned int) 0x3 <<  9) // (DBGU) Parity forced to 1 (Mark)
-#define     AT91C_US_PAR_NONE                 ((unsigned int) 0x4 <<  9) // (DBGU) No Parity
-#define     AT91C_US_PAR_MULTI_DROP           ((unsigned int) 0x6 <<  9) // (DBGU) Multi-drop mode
-#define AT91C_US_CHMODE       ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode
-#define     AT91C_US_CHMODE_NORMAL               ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
-#define     AT91C_US_CHMODE_AUTO                 ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
-#define     AT91C_US_CHMODE_LOCAL                ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
-#define     AT91C_US_CHMODE_REMOTE               ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
-// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
-#define AT91C_US_RXRDY        ((unsigned int) 0x1 <<  0) // (DBGU) RXRDY Interrupt
-#define AT91C_US_TXRDY        ((unsigned int) 0x1 <<  1) // (DBGU) TXRDY Interrupt
-#define AT91C_US_ENDRX        ((unsigned int) 0x1 <<  3) // (DBGU) End of Receive Transfer Interrupt
-#define AT91C_US_ENDTX        ((unsigned int) 0x1 <<  4) // (DBGU) End of Transmit Interrupt
-#define AT91C_US_OVRE         ((unsigned int) 0x1 <<  5) // (DBGU) Overrun Interrupt
-#define AT91C_US_FRAME        ((unsigned int) 0x1 <<  6) // (DBGU) Framing Error Interrupt
-#define AT91C_US_PARE         ((unsigned int) 0x1 <<  7) // (DBGU) Parity Error Interrupt
-#define AT91C_US_TXEMPTY      ((unsigned int) 0x1 <<  9) // (DBGU) TXEMPTY Interrupt
-#define AT91C_US_TXBUFE       ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt
-#define AT91C_US_RXBUFF       ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt
-#define AT91C_US_COMM_TX      ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt
-#define AT91C_US_COMM_RX      ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt
-// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
-// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
-// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
-// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
-#define AT91C_US_FORCE_NTRST  ((unsigned int) 0x1 <<  0) // (DBGU) Force NTRST in JTAG
+/* -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- */
+#define AT91C_US_RSTRX                 ( ( unsigned int ) 0x1 << 2 )  /* (DBGU) Reset Receiver */
+#define AT91C_US_RSTTX                 ( ( unsigned int ) 0x1 << 3 )  /* (DBGU) Reset Transmitter */
+#define AT91C_US_RXEN                  ( ( unsigned int ) 0x1 << 4 )  /* (DBGU) Receiver Enable */
+#define AT91C_US_RXDIS                 ( ( unsigned int ) 0x1 << 5 )  /* (DBGU) Receiver Disable */
+#define AT91C_US_TXEN                  ( ( unsigned int ) 0x1 << 6 )  /* (DBGU) Transmitter Enable */
+#define AT91C_US_TXDIS                 ( ( unsigned int ) 0x1 << 7 )  /* (DBGU) Transmitter Disable */
+#define AT91C_US_RSTSTA                ( ( unsigned int ) 0x1 << 8 )  /* (DBGU) Reset Status Bits */
+/* -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- */
+#define AT91C_US_PAR                   ( ( unsigned int ) 0x7 << 9 )  /* (DBGU) Parity type */
+#define     AT91C_US_PAR_EVEN          ( ( unsigned int ) 0x0 << 9 )  /* (DBGU) Even Parity */
+#define     AT91C_US_PAR_ODD           ( ( unsigned int ) 0x1 << 9 )  /* (DBGU) Odd Parity */
+#define     AT91C_US_PAR_SPACE         ( ( unsigned int ) 0x2 << 9 )  /* (DBGU) Parity forced to 0 (Space) */
+#define     AT91C_US_PAR_MARK          ( ( unsigned int ) 0x3 << 9 )  /* (DBGU) Parity forced to 1 (Mark) */
+#define     AT91C_US_PAR_NONE          ( ( unsigned int ) 0x4 << 9 )  /* (DBGU) No Parity */
+#define     AT91C_US_PAR_MULTI_DROP    ( ( unsigned int ) 0x6 << 9 )  /* (DBGU) Multi-drop mode */
+#define AT91C_US_CHMODE                ( ( unsigned int ) 0x3 << 14 ) /* (DBGU) Channel Mode */
+#define     AT91C_US_CHMODE_NORMAL     ( ( unsigned int ) 0x0 << 14 ) /* (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. */
+#define     AT91C_US_CHMODE_AUTO       ( ( unsigned int ) 0x1 << 14 ) /* (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. */
+#define     AT91C_US_CHMODE_LOCAL      ( ( unsigned int ) 0x2 << 14 ) /* (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. */
+#define     AT91C_US_CHMODE_REMOTE     ( ( unsigned int ) 0x3 << 14 ) /* (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. */
+/* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */
+#define AT91C_US_RXRDY                 ( ( unsigned int ) 0x1 << 0 )  /* (DBGU) RXRDY Interrupt */
+#define AT91C_US_TXRDY                 ( ( unsigned int ) 0x1 << 1 )  /* (DBGU) TXRDY Interrupt */
+#define AT91C_US_ENDRX                 ( ( unsigned int ) 0x1 << 3 )  /* (DBGU) End of Receive Transfer Interrupt */
+#define AT91C_US_ENDTX                 ( ( unsigned int ) 0x1 << 4 )  /* (DBGU) End of Transmit Interrupt */
+#define AT91C_US_OVRE                  ( ( unsigned int ) 0x1 << 5 )  /* (DBGU) Overrun Interrupt */
+#define AT91C_US_FRAME                 ( ( unsigned int ) 0x1 << 6 )  /* (DBGU) Framing Error Interrupt */
+#define AT91C_US_PARE                  ( ( unsigned int ) 0x1 << 7 )  /* (DBGU) Parity Error Interrupt */
+#define AT91C_US_TXEMPTY               ( ( unsigned int ) 0x1 << 9 )  /* (DBGU) TXEMPTY Interrupt */
+#define AT91C_US_TXBUFE                ( ( unsigned int ) 0x1 << 11 ) /* (DBGU) TXBUFE Interrupt */
+#define AT91C_US_RXBUFF                ( ( unsigned int ) 0x1 << 12 ) /* (DBGU) RXBUFF Interrupt */
+#define AT91C_US_COMM_TX               ( ( unsigned int ) 0x1 << 30 ) /* (DBGU) COMM_TX Interrupt */
+#define AT91C_US_COMM_RX               ( ( unsigned int ) 0x1 << 31 ) /* (DBGU) COMM_RX Interrupt */
+/* -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- */
+/* -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- */
+/* -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- */
+/* -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- */
+#define AT91C_US_FORCE_NTRST    ( ( unsigned int ) 0x1 << 0 ) /* (DBGU) Force NTRST in JTAG */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
-// *****************************************************************************
-typedef struct _AT91S_PIO {
-    AT91_REG     PIO_PER;   // PIO Enable Register
-    AT91_REG     PIO_PDR;   // PIO Disable Register
-    AT91_REG     PIO_PSR;   // PIO Status Register
-    AT91_REG     Reserved0[1];  //
-    AT91_REG     PIO_OER;   // Output Enable Register
-    AT91_REG     PIO_ODR;   // Output Disable Registerr
-    AT91_REG     PIO_OSR;   // Output Status Register
-    AT91_REG     Reserved1[1];  //
-    AT91_REG     PIO_IFER;  // Input Filter Enable Register
-    AT91_REG     PIO_IFDR;  // Input Filter Disable Register
-    AT91_REG     PIO_IFSR;  // Input Filter Status Register
-    AT91_REG     Reserved2[1];  //
-    AT91_REG     PIO_SODR;  // Set Output Data Register
-    AT91_REG     PIO_CODR;  // Clear Output Data Register
-    AT91_REG     PIO_ODSR;  // Output Data Status Register
-    AT91_REG     PIO_PDSR;  // Pin Data Status Register
-    AT91_REG     PIO_IER;   // Interrupt Enable Register
-    AT91_REG     PIO_IDR;   // Interrupt Disable Register
-    AT91_REG     PIO_IMR;   // Interrupt Mask Register
-    AT91_REG     PIO_ISR;   // Interrupt Status Register
-    AT91_REG     PIO_MDER;  // Multi-driver Enable Register
-    AT91_REG     PIO_MDDR;  // Multi-driver Disable Register
-    AT91_REG     PIO_MDSR;  // Multi-driver Status Register
-    AT91_REG     Reserved3[1];  //
-    AT91_REG     PIO_PPUDR;     // Pull-up Disable Register
-    AT91_REG     PIO_PPUER;     // Pull-up Enable Register
-    AT91_REG     PIO_PPUSR;     // Pull-up Status Register
-    AT91_REG     Reserved4[1];  //
-    AT91_REG     PIO_ASR;   // Select A Register
-    AT91_REG     PIO_BSR;   // Select B Register
-    AT91_REG     PIO_ABSR;  // AB Select Status Register
-    AT91_REG     Reserved5[9];  //
-    AT91_REG     PIO_OWER;  // Output Write Enable Register
-    AT91_REG     PIO_OWDR;  // Output Write Disable Register
-    AT91_REG     PIO_OWSR;  // Output Write Status Register
-} AT91S_PIO, *AT91PS_PIO;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Parallel Input Output Controller */
+/* ***************************************************************************** */
+typedef struct _AT91S_PIO
+{
+    AT91_REG PIO_PER;        /* PIO Enable Register */
+    AT91_REG PIO_PDR;        /* PIO Disable Register */
+    AT91_REG PIO_PSR;        /* PIO Status Register */
+    AT91_REG Reserved0[ 1 ]; /* */
+    AT91_REG PIO_OER;        /* Output Enable Register */
+    AT91_REG PIO_ODR;        /* Output Disable Registerr */
+    AT91_REG PIO_OSR;        /* Output Status Register */
+    AT91_REG Reserved1[ 1 ]; /* */
+    AT91_REG PIO_IFER;       /* Input Filter Enable Register */
+    AT91_REG PIO_IFDR;       /* Input Filter Disable Register */
+    AT91_REG PIO_IFSR;       /* Input Filter Status Register */
+    AT91_REG Reserved2[ 1 ]; /* */
+    AT91_REG PIO_SODR;       /* Set Output Data Register */
+    AT91_REG PIO_CODR;       /* Clear Output Data Register */
+    AT91_REG PIO_ODSR;       /* Output Data Status Register */
+    AT91_REG PIO_PDSR;       /* Pin Data Status Register */
+    AT91_REG PIO_IER;        /* Interrupt Enable Register */
+    AT91_REG PIO_IDR;        /* Interrupt Disable Register */
+    AT91_REG PIO_IMR;        /* Interrupt Mask Register */
+    AT91_REG PIO_ISR;        /* Interrupt Status Register */
+    AT91_REG PIO_MDER;       /* Multi-driver Enable Register */
+    AT91_REG PIO_MDDR;       /* Multi-driver Disable Register */
+    AT91_REG PIO_MDSR;       /* Multi-driver Status Register */
+    AT91_REG Reserved3[ 1 ]; /* */
+    AT91_REG PIO_PPUDR;      /* Pull-up Disable Register */
+    AT91_REG PIO_PPUER;      /* Pull-up Enable Register */
+    AT91_REG PIO_PPUSR;      /* Pull-up Status Register */
+    AT91_REG Reserved4[ 1 ]; /* */
+    AT91_REG PIO_ASR;        /* Select A Register */
+    AT91_REG PIO_BSR;        /* Select B Register */
+    AT91_REG PIO_ABSR;       /* AB Select Status Register */
+    AT91_REG Reserved5[ 9 ]; /* */
+    AT91_REG PIO_OWER;       /* Output Write Enable Register */
+    AT91_REG PIO_OWDR;       /* Output Write Disable Register */
+    AT91_REG PIO_OWSR;       /* Output Write Status Register */
+} AT91S_PIO, * AT91PS_PIO;
 
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Clock Generator Controler
-// *****************************************************************************
-typedef struct _AT91S_CKGR {
-    AT91_REG     CKGR_MOR;  // Main Oscillator Register
-    AT91_REG     CKGR_MCFR;     // Main Clock  Frequency Register
-    AT91_REG     Reserved0[1];  //
-    AT91_REG     CKGR_PLLR;     // PLL Register
-} AT91S_CKGR, *AT91PS_CKGR;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Clock Generator Controller */
+/* ***************************************************************************** */
+typedef struct _AT91S_CKGR
+{
+    AT91_REG CKGR_MOR;       /* Main Oscillator Register */
+    AT91_REG CKGR_MCFR;      /* Main Clock  Frequency Register */
+    AT91_REG Reserved0[ 1 ]; /* */
+    AT91_REG CKGR_PLLR;      /* PLL Register */
+} AT91S_CKGR, * AT91PS_CKGR;
 
-// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
-#define AT91C_CKGR_MOSCEN     ((unsigned int) 0x1 <<  0) // (CKGR) Main Oscillator Enable
-#define AT91C_CKGR_OSCBYPASS  ((unsigned int) 0x1 <<  1) // (CKGR) Main Oscillator Bypass
-#define AT91C_CKGR_OSCOUNT    ((unsigned int) 0xFF <<  8) // (CKGR) Main Oscillator Start-up Time
-// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
-#define AT91C_CKGR_MAINF      ((unsigned int) 0xFFFF <<  0) // (CKGR) Main Clock Frequency
-#define AT91C_CKGR_MAINRDY    ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready
-// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
-#define AT91C_CKGR_DIV        ((unsigned int) 0xFF <<  0) // (CKGR) Divider Selected
-#define     AT91C_CKGR_DIV_0                    ((unsigned int) 0x0) // (CKGR) Divider output is 0
-#define     AT91C_CKGR_DIV_BYPASS               ((unsigned int) 0x1) // (CKGR) Divider is bypassed
-#define AT91C_CKGR_PLLCOUNT   ((unsigned int) 0x3F <<  8) // (CKGR) PLL Counter
-#define AT91C_CKGR_OUT        ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range
-#define     AT91C_CKGR_OUT_0                    ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet
-#define     AT91C_CKGR_OUT_1                    ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet
-#define     AT91C_CKGR_OUT_2                    ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet
-#define     AT91C_CKGR_OUT_3                    ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_MUL        ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier
-#define AT91C_CKGR_USBDIV     ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks
-#define     AT91C_CKGR_USBDIV_0                    ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output
-#define     AT91C_CKGR_USBDIV_1                    ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
-#define     AT91C_CKGR_USBDIV_2                    ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
+/* -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */
+#define AT91C_CKGR_MOSCEN            ( ( unsigned int ) 0x1 << 0 )    /* (CKGR) Main Oscillator Enable */
+#define AT91C_CKGR_OSCBYPASS         ( ( unsigned int ) 0x1 << 1 )    /* (CKGR) Main Oscillator Bypass */
+#define AT91C_CKGR_OSCOUNT           ( ( unsigned int ) 0xFF << 8 )   /* (CKGR) Main Oscillator Start-up Time */
+/* -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- */
+#define AT91C_CKGR_MAINF             ( ( unsigned int ) 0xFFFF << 0 ) /* (CKGR) Main Clock Frequency */
+#define AT91C_CKGR_MAINRDY           ( ( unsigned int ) 0x1 << 16 )   /* (CKGR) Main Clock Ready */
+/* -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- */
+#define AT91C_CKGR_DIV               ( ( unsigned int ) 0xFF << 0 )   /* (CKGR) Divider Selected */
+#define     AT91C_CKGR_DIV_0         ( ( unsigned int ) 0x0 )         /* (CKGR) Divider output is 0 */
+#define     AT91C_CKGR_DIV_BYPASS    ( ( unsigned int ) 0x1 )         /* (CKGR) Divider is bypassed */
+#define AT91C_CKGR_PLLCOUNT          ( ( unsigned int ) 0x3F << 8 )   /* (CKGR) PLL Counter */
+#define AT91C_CKGR_OUT               ( ( unsigned int ) 0x3 << 14 )   /* (CKGR) PLL Output Frequency Range */
+#define     AT91C_CKGR_OUT_0         ( ( unsigned int ) 0x0 << 14 )   /* (CKGR) Please refer to the PLL datasheet */
+#define     AT91C_CKGR_OUT_1         ( ( unsigned int ) 0x1 << 14 )   /* (CKGR) Please refer to the PLL datasheet */
+#define     AT91C_CKGR_OUT_2         ( ( unsigned int ) 0x2 << 14 )   /* (CKGR) Please refer to the PLL datasheet */
+#define     AT91C_CKGR_OUT_3         ( ( unsigned int ) 0x3 << 14 )   /* (CKGR) Please refer to the PLL datasheet */
+#define AT91C_CKGR_MUL               ( ( unsigned int ) 0x7FF << 16 ) /* (CKGR) PLL Multiplier */
+#define AT91C_CKGR_USBDIV            ( ( unsigned int ) 0x3 << 28 )   /* (CKGR) Divider for USB Clocks */
+#define     AT91C_CKGR_USBDIV_0      ( ( unsigned int ) 0x0 << 28 )   /* (CKGR) Divider output is PLL clock output */
+#define     AT91C_CKGR_USBDIV_1      ( ( unsigned int ) 0x1 << 28 )   /* (CKGR) Divider output is PLL clock output divided by 2 */
+#define     AT91C_CKGR_USBDIV_2      ( ( unsigned int ) 0x2 << 28 )   /* (CKGR) Divider output is PLL clock output divided by 4 */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Power Management Controler
-// *****************************************************************************
-typedef struct _AT91S_PMC {
-    AT91_REG     PMC_SCER;  // System Clock Enable Register
-    AT91_REG     PMC_SCDR;  // System Clock Disable Register
-    AT91_REG     PMC_SCSR;  // System Clock Status Register
-    AT91_REG     Reserved0[1];  //
-    AT91_REG     PMC_PCER;  // Peripheral Clock Enable Register
-    AT91_REG     PMC_PCDR;  // Peripheral Clock Disable Register
-    AT91_REG     PMC_PCSR;  // Peripheral Clock Status Register
-    AT91_REG     Reserved1[1];  //
-    AT91_REG     PMC_MOR;   // Main Oscillator Register
-    AT91_REG     PMC_MCFR;  // Main Clock  Frequency Register
-    AT91_REG     Reserved2[1];  //
-    AT91_REG     PMC_PLLR;  // PLL Register
-    AT91_REG     PMC_MCKR;  // Master Clock Register
-    AT91_REG     Reserved3[3];  //
-    AT91_REG     PMC_PCKR[4];   // Programmable Clock Register
-    AT91_REG     Reserved4[4];  //
-    AT91_REG     PMC_IER;   // Interrupt Enable Register
-    AT91_REG     PMC_IDR;   // Interrupt Disable Register
-    AT91_REG     PMC_SR;    // Status Register
-    AT91_REG     PMC_IMR;   // Interrupt Mask Register
-} AT91S_PMC, *AT91PS_PMC;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Power Management Controller */
+/* ***************************************************************************** */
+typedef struct _AT91S_PMC
+{
+    AT91_REG PMC_SCER;       /* System Clock Enable Register */
+    AT91_REG PMC_SCDR;       /* System Clock Disable Register */
+    AT91_REG PMC_SCSR;       /* System Clock Status Register */
+    AT91_REG Reserved0[ 1 ]; /* */
+    AT91_REG PMC_PCER;       /* Peripheral Clock Enable Register */
+    AT91_REG PMC_PCDR;       /* Peripheral Clock Disable Register */
+    AT91_REG PMC_PCSR;       /* Peripheral Clock Status Register */
+    AT91_REG Reserved1[ 1 ]; /* */
+    AT91_REG PMC_MOR;        /* Main Oscillator Register */
+    AT91_REG PMC_MCFR;       /* Main Clock  Frequency Register */
+    AT91_REG Reserved2[ 1 ]; /* */
+    AT91_REG PMC_PLLR;       /* PLL Register */
+    AT91_REG PMC_MCKR;       /* Master Clock Register */
+    AT91_REG Reserved3[ 3 ]; /* */
+    AT91_REG PMC_PCKR[ 4 ];  /* Programmable Clock Register */
+    AT91_REG Reserved4[ 4 ]; /* */
+    AT91_REG PMC_IER;        /* Interrupt Enable Register */
+    AT91_REG PMC_IDR;        /* Interrupt Disable Register */
+    AT91_REG PMC_SR;         /* Status Register */
+    AT91_REG PMC_IMR;        /* Interrupt Mask Register */
+} AT91S_PMC, * AT91PS_PMC;
 
-// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
-#define AT91C_PMC_PCK         ((unsigned int) 0x1 <<  0) // (PMC) Processor Clock
-#define AT91C_PMC_UDP         ((unsigned int) 0x1 <<  7) // (PMC) USB Device Port Clock
-#define AT91C_PMC_PCK0        ((unsigned int) 0x1 <<  8) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK1        ((unsigned int) 0x1 <<  9) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK2        ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK3        ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output
-// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
-// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
-// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
-// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
-// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
-// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
-#define AT91C_PMC_CSS         ((unsigned int) 0x3 <<  0) // (PMC) Programmable Clock Selection
-#define     AT91C_PMC_CSS_SLOW_CLK             ((unsigned int) 0x0) // (PMC) Slow Clock is selected
-#define     AT91C_PMC_CSS_MAIN_CLK             ((unsigned int) 0x1) // (PMC) Main Clock is selected
-#define     AT91C_PMC_CSS_PLL_CLK              ((unsigned int) 0x3) // (PMC) Clock from PLL is selected
-#define AT91C_PMC_PRES        ((unsigned int) 0x7 <<  2) // (PMC) Programmable Clock Prescaler
-#define     AT91C_PMC_PRES_CLK                  ((unsigned int) 0x0 <<  2) // (PMC) Selected clock
-#define     AT91C_PMC_PRES_CLK_2                ((unsigned int) 0x1 <<  2) // (PMC) Selected clock divided by 2
-#define     AT91C_PMC_PRES_CLK_4                ((unsigned int) 0x2 <<  2) // (PMC) Selected clock divided by 4
-#define     AT91C_PMC_PRES_CLK_8                ((unsigned int) 0x3 <<  2) // (PMC) Selected clock divided by 8
-#define     AT91C_PMC_PRES_CLK_16               ((unsigned int) 0x4 <<  2) // (PMC) Selected clock divided by 16
-#define     AT91C_PMC_PRES_CLK_32               ((unsigned int) 0x5 <<  2) // (PMC) Selected clock divided by 32
-#define     AT91C_PMC_PRES_CLK_64               ((unsigned int) 0x6 <<  2) // (PMC) Selected clock divided by 64
-// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
-// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
-#define AT91C_PMC_MOSCS       ((unsigned int) 0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask
-#define AT91C_PMC_LOCK        ((unsigned int) 0x1 <<  2) // (PMC) PLL Status/Enable/Disable/Mask
-#define AT91C_PMC_MCKRDY      ((unsigned int) 0x1 <<  3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK0RDY     ((unsigned int) 0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK1RDY     ((unsigned int) 0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK2RDY     ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK3RDY     ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
-// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
-// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
-// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
+/* -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- */
+#define AT91C_PMC_PCK     ( ( unsigned int ) 0x1 << 0 )  /* (PMC) Processor Clock */
+#define AT91C_PMC_UDP     ( ( unsigned int ) 0x1 << 7 )  /* (PMC) USB Device Port Clock */
+#define AT91C_PMC_PCK0    ( ( unsigned int ) 0x1 << 8 )  /* (PMC) Programmable Clock Output */
+#define AT91C_PMC_PCK1    ( ( unsigned int ) 0x1 << 9 )  /* (PMC) Programmable Clock Output */
+#define AT91C_PMC_PCK2    ( ( unsigned int ) 0x1 << 10 ) /* (PMC) Programmable Clock Output */
+#define AT91C_PMC_PCK3    ( ( unsigned int ) 0x1 << 11 ) /* (PMC) Programmable Clock Output */
+/* -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- */
+/* -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- */
+/* -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- */
+/* -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- */
+/* -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- */
+/* -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- */
+#define AT91C_PMC_CSS                 ( ( unsigned int ) 0x3 << 0 ) /* (PMC) Programmable Clock Selection */
+#define     AT91C_PMC_CSS_SLOW_CLK    ( ( unsigned int ) 0x0 )      /* (PMC) Slow Clock is selected */
+#define     AT91C_PMC_CSS_MAIN_CLK    ( ( unsigned int ) 0x1 )      /* (PMC) Main Clock is selected */
+#define     AT91C_PMC_CSS_PLL_CLK     ( ( unsigned int ) 0x3 )      /* (PMC) Clock from PLL is selected */
+#define AT91C_PMC_PRES                ( ( unsigned int ) 0x7 << 2 ) /* (PMC) Programmable Clock Prescaler */
+#define     AT91C_PMC_PRES_CLK        ( ( unsigned int ) 0x0 << 2 ) /* (PMC) Selected clock */
+#define     AT91C_PMC_PRES_CLK_2      ( ( unsigned int ) 0x1 << 2 ) /* (PMC) Selected clock divided by 2 */
+#define     AT91C_PMC_PRES_CLK_4      ( ( unsigned int ) 0x2 << 2 ) /* (PMC) Selected clock divided by 4 */
+#define     AT91C_PMC_PRES_CLK_8      ( ( unsigned int ) 0x3 << 2 ) /* (PMC) Selected clock divided by 8 */
+#define     AT91C_PMC_PRES_CLK_16     ( ( unsigned int ) 0x4 << 2 ) /* (PMC) Selected clock divided by 16 */
+#define     AT91C_PMC_PRES_CLK_32     ( ( unsigned int ) 0x5 << 2 ) /* (PMC) Selected clock divided by 32 */
+#define     AT91C_PMC_PRES_CLK_64     ( ( unsigned int ) 0x6 << 2 ) /* (PMC) Selected clock divided by 64 */
+/* -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- */
+/* -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- */
+#define AT91C_PMC_MOSCS               ( ( unsigned int ) 0x1 << 0 )  /* (PMC) MOSC Status/Enable/Disable/Mask */
+#define AT91C_PMC_LOCK                ( ( unsigned int ) 0x1 << 2 )  /* (PMC) PLL Status/Enable/Disable/Mask */
+#define AT91C_PMC_MCKRDY              ( ( unsigned int ) 0x1 << 3 )  /* (PMC) MCK_RDY Status/Enable/Disable/Mask */
+#define AT91C_PMC_PCK0RDY             ( ( unsigned int ) 0x1 << 8 )  /* (PMC) PCK0_RDY Status/Enable/Disable/Mask */
+#define AT91C_PMC_PCK1RDY             ( ( unsigned int ) 0x1 << 9 )  /* (PMC) PCK1_RDY Status/Enable/Disable/Mask */
+#define AT91C_PMC_PCK2RDY             ( ( unsigned int ) 0x1 << 10 ) /* (PMC) PCK2_RDY Status/Enable/Disable/Mask */
+#define AT91C_PMC_PCK3RDY             ( ( unsigned int ) 0x1 << 11 ) /* (PMC) PCK3_RDY Status/Enable/Disable/Mask */
+/* -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- */
+/* -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- */
+/* -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Reset Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_RSTC {
-    AT91_REG     RSTC_RCR;  // Reset Control Register
-    AT91_REG     RSTC_RSR;  // Reset Status Register
-    AT91_REG     RSTC_RMR;  // Reset Mode Register
-} AT91S_RSTC, *AT91PS_RSTC;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Reset Controller Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_RSTC
+{
+    AT91_REG RSTC_RCR; /* Reset Control Register */
+    AT91_REG RSTC_RSR; /* Reset Status Register */
+    AT91_REG RSTC_RMR; /* Reset Mode Register */
+} AT91S_RSTC, * AT91PS_RSTC;
 
-// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
-#define AT91C_RSTC_PROCRST    ((unsigned int) 0x1 <<  0) // (RSTC) Processor Reset
-#define AT91C_RSTC_PERRST     ((unsigned int) 0x1 <<  2) // (RSTC) Peripheral Reset
-#define AT91C_RSTC_EXTRST     ((unsigned int) 0x1 <<  3) // (RSTC) External Reset
-#define AT91C_RSTC_KEY        ((unsigned int) 0xFF << 24) // (RSTC) Password
-// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
-#define AT91C_RSTC_URSTS      ((unsigned int) 0x1 <<  0) // (RSTC) User Reset Status
-#define AT91C_RSTC_BODSTS     ((unsigned int) 0x1 <<  1) // (RSTC) Brownout Detection Status
-#define AT91C_RSTC_RSTTYP     ((unsigned int) 0x7 <<  8) // (RSTC) Reset Type
-#define     AT91C_RSTC_RSTTYP_POWERUP              ((unsigned int) 0x0 <<  8) // (RSTC) Power-up Reset. VDDCORE rising.
-#define     AT91C_RSTC_RSTTYP_WAKEUP               ((unsigned int) 0x1 <<  8) // (RSTC) WakeUp Reset. VDDCORE rising.
-#define     AT91C_RSTC_RSTTYP_WATCHDOG             ((unsigned int) 0x2 <<  8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
-#define     AT91C_RSTC_RSTTYP_SOFTWARE             ((unsigned int) 0x3 <<  8) // (RSTC) Software Reset. Processor reset required by the software.
-#define     AT91C_RSTC_RSTTYP_USER                 ((unsigned int) 0x4 <<  8) // (RSTC) User Reset. NRST pin detected low.
-#define     AT91C_RSTC_RSTTYP_BROWNOUT             ((unsigned int) 0x5 <<  8) // (RSTC) Brownout Reset occured.
-#define AT91C_RSTC_NRSTL      ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level
-#define AT91C_RSTC_SRCMP      ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress.
-// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
-#define AT91C_RSTC_URSTEN     ((unsigned int) 0x1 <<  0) // (RSTC) User Reset Enable
-#define AT91C_RSTC_URSTIEN    ((unsigned int) 0x1 <<  4) // (RSTC) User Reset Interrupt Enable
-#define AT91C_RSTC_ERSTL      ((unsigned int) 0xF <<  8) // (RSTC) User Reset Enable
-#define AT91C_RSTC_BODIEN     ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
+/* -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- */
+#define AT91C_RSTC_PROCRST                ( ( unsigned int ) 0x1 << 0 )   /* (RSTC) Processor Reset */
+#define AT91C_RSTC_PERRST                 ( ( unsigned int ) 0x1 << 2 )   /* (RSTC) Peripheral Reset */
+#define AT91C_RSTC_EXTRST                 ( ( unsigned int ) 0x1 << 3 )   /* (RSTC) External Reset */
+#define AT91C_RSTC_KEY                    ( ( unsigned int ) 0xFF << 24 ) /* (RSTC) Password */
+/* -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- */
+#define AT91C_RSTC_URSTS                  ( ( unsigned int ) 0x1 << 0 )   /* (RSTC) User Reset Status */
+#define AT91C_RSTC_BODSTS                 ( ( unsigned int ) 0x1 << 1 )   /* (RSTC) Brownout Detection Status */
+#define AT91C_RSTC_RSTTYP                 ( ( unsigned int ) 0x7 << 8 )   /* (RSTC) Reset Type */
+#define     AT91C_RSTC_RSTTYP_POWERUP     ( ( unsigned int ) 0x0 << 8 )   /* (RSTC) Power-up Reset. VDDCORE rising. */
+#define     AT91C_RSTC_RSTTYP_WAKEUP      ( ( unsigned int ) 0x1 << 8 )   /* (RSTC) WakeUp Reset. VDDCORE rising. */
+#define     AT91C_RSTC_RSTTYP_WATCHDOG    ( ( unsigned int ) 0x2 << 8 )   /* (RSTC) Watchdog Reset. Watchdog overflow occurred. */
+#define     AT91C_RSTC_RSTTYP_SOFTWARE    ( ( unsigned int ) 0x3 << 8 )   /* (RSTC) Software Reset. Processor reset required by the software. */
+#define     AT91C_RSTC_RSTTYP_USER        ( ( unsigned int ) 0x4 << 8 )   /* (RSTC) User Reset. NRST pin detected low. */
+#define     AT91C_RSTC_RSTTYP_BROWNOUT    ( ( unsigned int ) 0x5 << 8 )   /* (RSTC) Brownout Reset occurred. */
+#define AT91C_RSTC_NRSTL                  ( ( unsigned int ) 0x1 << 16 )  /* (RSTC) NRST pin level */
+#define AT91C_RSTC_SRCMP                  ( ( unsigned int ) 0x1 << 17 )  /* (RSTC) Software Reset Command in Progress. */
+/* -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- */
+#define AT91C_RSTC_URSTEN                 ( ( unsigned int ) 0x1 << 0 )   /* (RSTC) User Reset Enable */
+#define AT91C_RSTC_URSTIEN                ( ( unsigned int ) 0x1 << 4 )   /* (RSTC) User Reset Interrupt Enable */
+#define AT91C_RSTC_ERSTL                  ( ( unsigned int ) 0xF << 8 )   /* (RSTC) User Reset Enable */
+#define AT91C_RSTC_BODIEN                 ( ( unsigned int ) 0x1 << 16 )  /* (RSTC) Brownout Detection Interrupt Enable */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_RTTC {
-    AT91_REG     RTTC_RTMR;     // Real-time Mode Register
-    AT91_REG     RTTC_RTAR;     // Real-time Alarm Register
-    AT91_REG     RTTC_RTVR;     // Real-time Value Register
-    AT91_REG     RTTC_RTSR;     // Real-time Status Register
-} AT91S_RTTC, *AT91PS_RTTC;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_RTTC
+{
+    AT91_REG RTTC_RTMR; /* Real-time Mode Register */
+    AT91_REG RTTC_RTAR; /* Real-time Alarm Register */
+    AT91_REG RTTC_RTVR; /* Real-time Value Register */
+    AT91_REG RTTC_RTSR; /* Real-time Status Register */
+} AT91S_RTTC, * AT91PS_RTTC;
 
-// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
-#define AT91C_RTTC_RTPRES     ((unsigned int) 0xFFFF <<  0) // (RTTC) Real-time Timer Prescaler Value
-#define AT91C_RTTC_ALMIEN     ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable
-#define AT91C_RTTC_RTTINCIEN  ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
-#define AT91C_RTTC_RTTRST     ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart
-// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
-#define AT91C_RTTC_ALMV       ((unsigned int) 0x0 <<  0) // (RTTC) Alarm Value
-// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
-#define AT91C_RTTC_CRTV       ((unsigned int) 0x0 <<  0) // (RTTC) Current Real-time Value
-// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
-#define AT91C_RTTC_ALMS       ((unsigned int) 0x1 <<  0) // (RTTC) Real-time Alarm Status
-#define AT91C_RTTC_RTTINC     ((unsigned int) 0x1 <<  1) // (RTTC) Real-time Timer Increment
+/* -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- */
+#define AT91C_RTTC_RTPRES       ( ( unsigned int ) 0xFFFF << 0 ) /* (RTTC) Real-time Timer Prescaler Value */
+#define AT91C_RTTC_ALMIEN       ( ( unsigned int ) 0x1 << 16 )   /* (RTTC) Alarm Interrupt Enable */
+#define AT91C_RTTC_RTTINCIEN    ( ( unsigned int ) 0x1 << 17 )   /* (RTTC) Real Time Timer Increment Interrupt Enable */
+#define AT91C_RTTC_RTTRST       ( ( unsigned int ) 0x1 << 18 )   /* (RTTC) Real Time Timer Restart */
+/* -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- */
+#define AT91C_RTTC_ALMV         ( ( unsigned int ) 0x0 << 0 )    /* (RTTC) Alarm Value */
+/* -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- */
+#define AT91C_RTTC_CRTV         ( ( unsigned int ) 0x0 << 0 )    /* (RTTC) Current Real-time Value */
+/* -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- */
+#define AT91C_RTTC_ALMS         ( ( unsigned int ) 0x1 << 0 )    /* (RTTC) Real-time Alarm Status */
+#define AT91C_RTTC_RTTINC       ( ( unsigned int ) 0x1 << 1 )    /* (RTTC) Real-time Timer Increment */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_PITC {
-    AT91_REG     PITC_PIMR;     // Period Interval Mode Register
-    AT91_REG     PITC_PISR;     // Period Interval Status Register
-    AT91_REG     PITC_PIVR;     // Period Interval Value Register
-    AT91_REG     PITC_PIIR;     // Period Interval Image Register
-} AT91S_PITC, *AT91PS_PITC;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_PITC
+{
+    AT91_REG PITC_PIMR; /* Period Interval Mode Register */
+    AT91_REG PITC_PISR; /* Period Interval Status Register */
+    AT91_REG PITC_PIVR; /* Period Interval Value Register */
+    AT91_REG PITC_PIIR; /* Period Interval Image Register */
+} AT91S_PITC, * AT91PS_PITC;
 
-// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
-#define AT91C_PITC_PIV        ((unsigned int) 0xFFFFF <<  0) // (PITC) Periodic Interval Value
-#define AT91C_PITC_PITEN      ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled
-#define AT91C_PITC_PITIEN     ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
-// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
-#define AT91C_PITC_PITS       ((unsigned int) 0x1 <<  0) // (PITC) Periodic Interval Timer Status
-// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
-#define AT91C_PITC_CPIV       ((unsigned int) 0xFFFFF <<  0) // (PITC) Current Periodic Interval Value
-#define AT91C_PITC_PICNT      ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter
-// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
+/* -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- */
+#define AT91C_PITC_PIV       ( ( unsigned int ) 0xFFFFF << 0 ) /* (PITC) Periodic Interval Value */
+#define AT91C_PITC_PITEN     ( ( unsigned int ) 0x1 << 24 )    /* (PITC) Periodic Interval Timer Enabled */
+#define AT91C_PITC_PITIEN    ( ( unsigned int ) 0x1 << 25 )    /* (PITC) Periodic Interval Timer Interrupt Enable */
+/* -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- */
+#define AT91C_PITC_PITS      ( ( unsigned int ) 0x1 << 0 )     /* (PITC) Periodic Interval Timer Status */
+/* -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- */
+#define AT91C_PITC_CPIV      ( ( unsigned int ) 0xFFFFF << 0 ) /* (PITC) Current Periodic Interval Value */
+#define AT91C_PITC_PICNT     ( ( unsigned int ) 0xFFF << 20 )  /* (PITC) Periodic Interval Counter */
+/* -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_WDTC {
-    AT91_REG     WDTC_WDCR;     // Watchdog Control Register
-    AT91_REG     WDTC_WDMR;     // Watchdog Mode Register
-    AT91_REG     WDTC_WDSR;     // Watchdog Status Register
-} AT91S_WDTC, *AT91PS_WDTC;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_WDTC
+{
+    AT91_REG WDTC_WDCR; /* Watchdog Control Register */
+    AT91_REG WDTC_WDMR; /* Watchdog Mode Register */
+    AT91_REG WDTC_WDSR; /* Watchdog Status Register */
+} AT91S_WDTC, * AT91PS_WDTC;
 
-// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
-#define AT91C_WDTC_WDRSTT     ((unsigned int) 0x1 <<  0) // (WDTC) Watchdog Restart
-#define AT91C_WDTC_KEY        ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password
-// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
-#define AT91C_WDTC_WDV        ((unsigned int) 0xFFF <<  0) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDFIEN     ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
-#define AT91C_WDTC_WDRSTEN    ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable
-#define AT91C_WDTC_WDRPROC    ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDDIS      ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable
-#define AT91C_WDTC_WDD        ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value
-#define AT91C_WDTC_WDDBGHLT   ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt
-#define AT91C_WDTC_WDIDLEHLT  ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt
-// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
-#define AT91C_WDTC_WDUNF      ((unsigned int) 0x1 <<  0) // (WDTC) Watchdog Underflow
-#define AT91C_WDTC_WDERR      ((unsigned int) 0x1 <<  1) // (WDTC) Watchdog Error
+/* -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- */
+#define AT91C_WDTC_WDRSTT       ( ( unsigned int ) 0x1 << 0 )    /* (WDTC) Watchdog Restart */
+#define AT91C_WDTC_KEY          ( ( unsigned int ) 0xFF << 24 )  /* (WDTC) Watchdog KEY Password */
+/* -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- */
+#define AT91C_WDTC_WDV          ( ( unsigned int ) 0xFFF << 0 )  /* (WDTC) Watchdog Timer Restart */
+#define AT91C_WDTC_WDFIEN       ( ( unsigned int ) 0x1 << 12 )   /* (WDTC) Watchdog Fault Interrupt Enable */
+#define AT91C_WDTC_WDRSTEN      ( ( unsigned int ) 0x1 << 13 )   /* (WDTC) Watchdog Reset Enable */
+#define AT91C_WDTC_WDRPROC      ( ( unsigned int ) 0x1 << 14 )   /* (WDTC) Watchdog Timer Restart */
+#define AT91C_WDTC_WDDIS        ( ( unsigned int ) 0x1 << 15 )   /* (WDTC) Watchdog Disable */
+#define AT91C_WDTC_WDD          ( ( unsigned int ) 0xFFF << 16 ) /* (WDTC) Watchdog Delta Value */
+#define AT91C_WDTC_WDDBGHLT     ( ( unsigned int ) 0x1 << 28 )   /* (WDTC) Watchdog Debug Halt */
+#define AT91C_WDTC_WDIDLEHLT    ( ( unsigned int ) 0x1 << 29 )   /* (WDTC) Watchdog Idle Halt */
+/* -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- */
+#define AT91C_WDTC_WDUNF        ( ( unsigned int ) 0x1 << 0 )    /* (WDTC) Watchdog Underflow */
+#define AT91C_WDTC_WDERR        ( ( unsigned int ) 0x1 << 1 )    /* (WDTC) Watchdog Error */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Voltage Regulator Mode Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_VREG {
-    AT91_REG     VREG_MR;   // Voltage Regulator Mode Register
-} AT91S_VREG, *AT91PS_VREG;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Voltage Regulator Mode Controller Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_VREG
+{
+    AT91_REG VREG_MR; /* Voltage Regulator Mode Register */
+} AT91S_VREG, * AT91PS_VREG;
 
-// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register --------
-#define AT91C_VREG_PSTDBY     ((unsigned int) 0x1 <<  0) // (VREG) Voltage Regulator Power Standby Mode
+/* -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- */
+#define AT91C_VREG_PSTDBY    ( ( unsigned int ) 0x1 << 0 ) /* (VREG) Voltage Regulator Power Standby Mode */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Memory Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_MC {
-    AT91_REG     MC_RCR;    // MC Remap Control Register
-    AT91_REG     MC_ASR;    // MC Abort Status Register
-    AT91_REG     MC_AASR;   // MC Abort Address Status Register
-    AT91_REG     Reserved0[21];     //
-    AT91_REG     MC_FMR;    // MC Flash Mode Register
-    AT91_REG     MC_FCR;    // MC Flash Command Register
-    AT91_REG     MC_FSR;    // MC Flash Status Register
-} AT91S_MC, *AT91PS_MC;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Memory Controller Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_MC
+{
+    AT91_REG MC_RCR;          /* MC Remap Control Register */
+    AT91_REG MC_ASR;          /* MC Abort Status Register */
+    AT91_REG MC_AASR;         /* MC Abort Address Status Register */
+    AT91_REG Reserved0[ 21 ]; /* */
+    AT91_REG MC_FMR;          /* MC Flash Mode Register */
+    AT91_REG MC_FCR;          /* MC Flash Command Register */
+    AT91_REG MC_FSR;          /* MC Flash Status Register */
+} AT91S_MC, * AT91PS_MC;
 
-// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
-#define AT91C_MC_RCB          ((unsigned int) 0x1 <<  0) // (MC) Remap Command Bit
-// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
-#define AT91C_MC_UNDADD       ((unsigned int) 0x1 <<  0) // (MC) Undefined Addess Abort Status
-#define AT91C_MC_MISADD       ((unsigned int) 0x1 <<  1) // (MC) Misaligned Addess Abort Status
-#define AT91C_MC_ABTSZ        ((unsigned int) 0x3 <<  8) // (MC) Abort Size Status
-#define     AT91C_MC_ABTSZ_BYTE                 ((unsigned int) 0x0 <<  8) // (MC) Byte
-#define     AT91C_MC_ABTSZ_HWORD                ((unsigned int) 0x1 <<  8) // (MC) Half-word
-#define     AT91C_MC_ABTSZ_WORD                 ((unsigned int) 0x2 <<  8) // (MC) Word
-#define AT91C_MC_ABTTYP       ((unsigned int) 0x3 << 10) // (MC) Abort Type Status
-#define     AT91C_MC_ABTTYP_DATAR                ((unsigned int) 0x0 << 10) // (MC) Data Read
-#define     AT91C_MC_ABTTYP_DATAW                ((unsigned int) 0x1 << 10) // (MC) Data Write
-#define     AT91C_MC_ABTTYP_FETCH                ((unsigned int) 0x2 << 10) // (MC) Code Fetch
-#define AT91C_MC_MST0         ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source
-#define AT91C_MC_MST1         ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source
-#define AT91C_MC_SVMST0       ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source
-#define AT91C_MC_SVMST1       ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source
-// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
-#define AT91C_MC_FRDY         ((unsigned int) 0x1 <<  0) // (MC) Flash Ready
-#define AT91C_MC_LOCKE        ((unsigned int) 0x1 <<  2) // (MC) Lock Error
-#define AT91C_MC_PROGE        ((unsigned int) 0x1 <<  3) // (MC) Programming Error
-#define AT91C_MC_NEBP         ((unsigned int) 0x1 <<  7) // (MC) No Erase Before Programming
-#define AT91C_MC_FWS          ((unsigned int) 0x3 <<  8) // (MC) Flash Wait State
-#define     AT91C_MC_FWS_0FWS                 ((unsigned int) 0x0 <<  8) // (MC) 1 cycle for Read, 2 for Write operations
-#define     AT91C_MC_FWS_1FWS                 ((unsigned int) 0x1 <<  8) // (MC) 2 cycles for Read, 3 for Write operations
-#define     AT91C_MC_FWS_2FWS                 ((unsigned int) 0x2 <<  8) // (MC) 3 cycles for Read, 4 for Write operations
-#define     AT91C_MC_FWS_3FWS                 ((unsigned int) 0x3 <<  8) // (MC) 4 cycles for Read, 4 for Write operations
-#define AT91C_MC_FMCN         ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number
-// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
-#define AT91C_MC_FCMD         ((unsigned int) 0xF <<  0) // (MC) Flash Command
-#define     AT91C_MC_FCMD_START_PROG           ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN.
-#define     AT91C_MC_FCMD_LOCK                 ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define     AT91C_MC_FCMD_PROG_AND_LOCK        ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
-#define     AT91C_MC_FCMD_UNLOCK               ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define     AT91C_MC_FCMD_ERASE_ALL            ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
-#define     AT91C_MC_FCMD_SET_GP_NVM           ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits.
-#define     AT91C_MC_FCMD_CLR_GP_NVM           ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits.
-#define     AT91C_MC_FCMD_SET_SECURITY         ((unsigned int) 0xF) // (MC) Set Security Bit.
-#define AT91C_MC_PAGEN        ((unsigned int) 0x3FF <<  8) // (MC) Page Number
-#define AT91C_MC_KEY          ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key
-// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register --------
-#define AT91C_MC_SECURITY     ((unsigned int) 0x1 <<  4) // (MC) Security Bit Status
-#define AT91C_MC_GPNVM0       ((unsigned int) 0x1 <<  8) // (MC) Sector 0 Lock Status
-#define AT91C_MC_GPNVM1       ((unsigned int) 0x1 <<  9) // (MC) Sector 1 Lock Status
-#define AT91C_MC_GPNVM2       ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status
-#define AT91C_MC_GPNVM3       ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status
-#define AT91C_MC_GPNVM4       ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status
-#define AT91C_MC_GPNVM5       ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status
-#define AT91C_MC_GPNVM6       ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status
-#define AT91C_MC_GPNVM7       ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS0       ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status
-#define AT91C_MC_LOCKS1       ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status
-#define AT91C_MC_LOCKS2       ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status
-#define AT91C_MC_LOCKS3       ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status
-#define AT91C_MC_LOCKS4       ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status
-#define AT91C_MC_LOCKS5       ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status
-#define AT91C_MC_LOCKS6       ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status
-#define AT91C_MC_LOCKS7       ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS8       ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status
-#define AT91C_MC_LOCKS9       ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status
-#define AT91C_MC_LOCKS10      ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status
-#define AT91C_MC_LOCKS11      ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status
-#define AT91C_MC_LOCKS12      ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status
-#define AT91C_MC_LOCKS13      ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status
-#define AT91C_MC_LOCKS14      ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status
-#define AT91C_MC_LOCKS15      ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status
+/* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */
+#define AT91C_MC_RCB                       ( ( unsigned int ) 0x1 << 0 )   /* (MC) Remap Command Bit */
+/* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */
+#define AT91C_MC_UNDADD                    ( ( unsigned int ) 0x1 << 0 )   /* (MC) Undefined Addess Abort Status */
+#define AT91C_MC_MISADD                    ( ( unsigned int ) 0x1 << 1 )   /* (MC) Misaligned Addess Abort Status */
+#define AT91C_MC_ABTSZ                     ( ( unsigned int ) 0x3 << 8 )   /* (MC) Abort Size Status */
+#define     AT91C_MC_ABTSZ_BYTE            ( ( unsigned int ) 0x0 << 8 )   /* (MC) Byte */
+#define     AT91C_MC_ABTSZ_HWORD           ( ( unsigned int ) 0x1 << 8 )   /* (MC) Half-word */
+#define     AT91C_MC_ABTSZ_WORD            ( ( unsigned int ) 0x2 << 8 )   /* (MC) Word */
+#define AT91C_MC_ABTTYP                    ( ( unsigned int ) 0x3 << 10 )  /* (MC) Abort Type Status */
+#define     AT91C_MC_ABTTYP_DATAR          ( ( unsigned int ) 0x0 << 10 )  /* (MC) Data Read */
+#define     AT91C_MC_ABTTYP_DATAW          ( ( unsigned int ) 0x1 << 10 )  /* (MC) Data Write */
+#define     AT91C_MC_ABTTYP_FETCH          ( ( unsigned int ) 0x2 << 10 )  /* (MC) Code Fetch */
+#define AT91C_MC_MST0                      ( ( unsigned int ) 0x1 << 16 )  /* (MC) Master 0 Abort Source */
+#define AT91C_MC_MST1                      ( ( unsigned int ) 0x1 << 17 )  /* (MC) Master 1 Abort Source */
+#define AT91C_MC_SVMST0                    ( ( unsigned int ) 0x1 << 24 )  /* (MC) Saved Master 0 Abort Source */
+#define AT91C_MC_SVMST1                    ( ( unsigned int ) 0x1 << 25 )  /* (MC) Saved Master 1 Abort Source */
+/* -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- */
+#define AT91C_MC_FRDY                      ( ( unsigned int ) 0x1 << 0 )   /* (MC) Flash Ready */
+#define AT91C_MC_LOCKE                     ( ( unsigned int ) 0x1 << 2 )   /* (MC) Lock Error */
+#define AT91C_MC_PROGE                     ( ( unsigned int ) 0x1 << 3 )   /* (MC) Programming Error */
+#define AT91C_MC_NEBP                      ( ( unsigned int ) 0x1 << 7 )   /* (MC) No Erase Before Programming */
+#define AT91C_MC_FWS                       ( ( unsigned int ) 0x3 << 8 )   /* (MC) Flash Wait State */
+#define     AT91C_MC_FWS_0FWS              ( ( unsigned int ) 0x0 << 8 )   /* (MC) 1 cycle for Read, 2 for Write operations */
+#define     AT91C_MC_FWS_1FWS              ( ( unsigned int ) 0x1 << 8 )   /* (MC) 2 cycles for Read, 3 for Write operations */
+#define     AT91C_MC_FWS_2FWS              ( ( unsigned int ) 0x2 << 8 )   /* (MC) 3 cycles for Read, 4 for Write operations */
+#define     AT91C_MC_FWS_3FWS              ( ( unsigned int ) 0x3 << 8 )   /* (MC) 4 cycles for Read, 4 for Write operations */
+#define AT91C_MC_FMCN                      ( ( unsigned int ) 0xFF << 16 ) /* (MC) Flash Microsecond Cycle Number */
+/* -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- */
+#define AT91C_MC_FCMD                      ( ( unsigned int ) 0xF << 0 )   /* (MC) Flash Command */
+#define     AT91C_MC_FCMD_START_PROG       ( ( unsigned int ) 0x1 )        /* (MC) Starts the programming of th epage specified by PAGEN. */
+#define     AT91C_MC_FCMD_LOCK             ( ( unsigned int ) 0x2 )        /* (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */
+#define     AT91C_MC_FCMD_PROG_AND_LOCK    ( ( unsigned int ) 0x3 )        /* (MC) The lock sequence automatically happens after the programming sequence is completed. */
+#define     AT91C_MC_FCMD_UNLOCK           ( ( unsigned int ) 0x4 )        /* (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */
+#define     AT91C_MC_FCMD_ERASE_ALL        ( ( unsigned int ) 0x8 )        /* (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. */
+#define     AT91C_MC_FCMD_SET_GP_NVM       ( ( unsigned int ) 0xB )        /* (MC) Set General Purpose NVM bits. */
+#define     AT91C_MC_FCMD_CLR_GP_NVM       ( ( unsigned int ) 0xD )        /* (MC) Clear General Purpose NVM bits. */
+#define     AT91C_MC_FCMD_SET_SECURITY     ( ( unsigned int ) 0xF )        /* (MC) Set Security Bit. */
+#define AT91C_MC_PAGEN                     ( ( unsigned int ) 0x3FF << 8 ) /* (MC) Page Number */
+#define AT91C_MC_KEY                       ( ( unsigned int ) 0xFF << 24 ) /* (MC) Writing Protect Key */
+/* -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- */
+#define AT91C_MC_SECURITY                  ( ( unsigned int ) 0x1 << 4 )   /* (MC) Security Bit Status */
+#define AT91C_MC_GPNVM0                    ( ( unsigned int ) 0x1 << 8 )   /* (MC) Sector 0 Lock Status */
+#define AT91C_MC_GPNVM1                    ( ( unsigned int ) 0x1 << 9 )   /* (MC) Sector 1 Lock Status */
+#define AT91C_MC_GPNVM2                    ( ( unsigned int ) 0x1 << 10 )  /* (MC) Sector 2 Lock Status */
+#define AT91C_MC_GPNVM3                    ( ( unsigned int ) 0x1 << 11 )  /* (MC) Sector 3 Lock Status */
+#define AT91C_MC_GPNVM4                    ( ( unsigned int ) 0x1 << 12 )  /* (MC) Sector 4 Lock Status */
+#define AT91C_MC_GPNVM5                    ( ( unsigned int ) 0x1 << 13 )  /* (MC) Sector 5 Lock Status */
+#define AT91C_MC_GPNVM6                    ( ( unsigned int ) 0x1 << 14 )  /* (MC) Sector 6 Lock Status */
+#define AT91C_MC_GPNVM7                    ( ( unsigned int ) 0x1 << 15 )  /* (MC) Sector 7 Lock Status */
+#define AT91C_MC_LOCKS0                    ( ( unsigned int ) 0x1 << 16 )  /* (MC) Sector 0 Lock Status */
+#define AT91C_MC_LOCKS1                    ( ( unsigned int ) 0x1 << 17 )  /* (MC) Sector 1 Lock Status */
+#define AT91C_MC_LOCKS2                    ( ( unsigned int ) 0x1 << 18 )  /* (MC) Sector 2 Lock Status */
+#define AT91C_MC_LOCKS3                    ( ( unsigned int ) 0x1 << 19 )  /* (MC) Sector 3 Lock Status */
+#define AT91C_MC_LOCKS4                    ( ( unsigned int ) 0x1 << 20 )  /* (MC) Sector 4 Lock Status */
+#define AT91C_MC_LOCKS5                    ( ( unsigned int ) 0x1 << 21 )  /* (MC) Sector 5 Lock Status */
+#define AT91C_MC_LOCKS6                    ( ( unsigned int ) 0x1 << 22 )  /* (MC) Sector 6 Lock Status */
+#define AT91C_MC_LOCKS7                    ( ( unsigned int ) 0x1 << 23 )  /* (MC) Sector 7 Lock Status */
+#define AT91C_MC_LOCKS8                    ( ( unsigned int ) 0x1 << 24 )  /* (MC) Sector 8 Lock Status */
+#define AT91C_MC_LOCKS9                    ( ( unsigned int ) 0x1 << 25 )  /* (MC) Sector 9 Lock Status */
+#define AT91C_MC_LOCKS10                   ( ( unsigned int ) 0x1 << 26 )  /* (MC) Sector 10 Lock Status */
+#define AT91C_MC_LOCKS11                   ( ( unsigned int ) 0x1 << 27 )  /* (MC) Sector 11 Lock Status */
+#define AT91C_MC_LOCKS12                   ( ( unsigned int ) 0x1 << 28 )  /* (MC) Sector 12 Lock Status */
+#define AT91C_MC_LOCKS13                   ( ( unsigned int ) 0x1 << 29 )  /* (MC) Sector 13 Lock Status */
+#define AT91C_MC_LOCKS14                   ( ( unsigned int ) 0x1 << 30 )  /* (MC) Sector 14 Lock Status */
+#define AT91C_MC_LOCKS15                   ( ( unsigned int ) 0x1 << 31 )  /* (MC) Sector 15 Lock Status */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
-// *****************************************************************************
-typedef struct _AT91S_SPI {
-    AT91_REG     SPI_CR;    // Control Register
-    AT91_REG     SPI_MR;    // Mode Register
-    AT91_REG     SPI_RDR;   // Receive Data Register
-    AT91_REG     SPI_TDR;   // Transmit Data Register
-    AT91_REG     SPI_SR;    // Status Register
-    AT91_REG     SPI_IER;   // Interrupt Enable Register
-    AT91_REG     SPI_IDR;   // Interrupt Disable Register
-    AT91_REG     SPI_IMR;   // Interrupt Mask Register
-    AT91_REG     Reserved0[4];  //
-    AT91_REG     SPI_CSR[4];    // Chip Select Register
-    AT91_REG     Reserved1[48];     //
-    AT91_REG     SPI_RPR;   // Receive Pointer Register
-    AT91_REG     SPI_RCR;   // Receive Counter Register
-    AT91_REG     SPI_TPR;   // Transmit Pointer Register
-    AT91_REG     SPI_TCR;   // Transmit Counter Register
-    AT91_REG     SPI_RNPR;  // Receive Next Pointer Register
-    AT91_REG     SPI_RNCR;  // Receive Next Counter Register
-    AT91_REG     SPI_TNPR;  // Transmit Next Pointer Register
-    AT91_REG     SPI_TNCR;  // Transmit Next Counter Register
-    AT91_REG     SPI_PTCR;  // PDC Transfer Control Register
-    AT91_REG     SPI_PTSR;  // PDC Transfer Status Register
-} AT91S_SPI, *AT91PS_SPI;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Serial Parallel Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_SPI
+{
+    AT91_REG SPI_CR;          /* Control Register */
+    AT91_REG SPI_MR;          /* Mode Register */
+    AT91_REG SPI_RDR;         /* Receive Data Register */
+    AT91_REG SPI_TDR;         /* Transmit Data Register */
+    AT91_REG SPI_SR;          /* Status Register */
+    AT91_REG SPI_IER;         /* Interrupt Enable Register */
+    AT91_REG SPI_IDR;         /* Interrupt Disable Register */
+    AT91_REG SPI_IMR;         /* Interrupt Mask Register */
+    AT91_REG Reserved0[ 4 ];  /* */
+    AT91_REG SPI_CSR[ 4 ];    /* Chip Select Register */
+    AT91_REG Reserved1[ 48 ]; /* */
+    AT91_REG SPI_RPR;         /* Receive Pointer Register */
+    AT91_REG SPI_RCR;         /* Receive Counter Register */
+    AT91_REG SPI_TPR;         /* Transmit Pointer Register */
+    AT91_REG SPI_TCR;         /* Transmit Counter Register */
+    AT91_REG SPI_RNPR;        /* Receive Next Pointer Register */
+    AT91_REG SPI_RNCR;        /* Receive Next Counter Register */
+    AT91_REG SPI_TNPR;        /* Transmit Next Pointer Register */
+    AT91_REG SPI_TNCR;        /* Transmit Next Counter Register */
+    AT91_REG SPI_PTCR;        /* PDC Transfer Control Register */
+    AT91_REG SPI_PTSR;        /* PDC Transfer Status Register */
+} AT91S_SPI, * AT91PS_SPI;
 
-// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
-#define AT91C_SPI_SPIEN       ((unsigned int) 0x1 <<  0) // (SPI) SPI Enable
-#define AT91C_SPI_SPIDIS      ((unsigned int) 0x1 <<  1) // (SPI) SPI Disable
-#define AT91C_SPI_SWRST       ((unsigned int) 0x1 <<  7) // (SPI) SPI Software reset
-#define AT91C_SPI_LASTXFER    ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer
-// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
-#define AT91C_SPI_MSTR        ((unsigned int) 0x1 <<  0) // (SPI) Master/Slave Mode
-#define AT91C_SPI_PS          ((unsigned int) 0x1 <<  1) // (SPI) Peripheral Select
-#define     AT91C_SPI_PS_FIXED                ((unsigned int) 0x0 <<  1) // (SPI) Fixed Peripheral Select
-#define     AT91C_SPI_PS_VARIABLE             ((unsigned int) 0x1 <<  1) // (SPI) Variable Peripheral Select
-#define AT91C_SPI_PCSDEC      ((unsigned int) 0x1 <<  2) // (SPI) Chip Select Decode
-#define AT91C_SPI_FDIV        ((unsigned int) 0x1 <<  3) // (SPI) Clock Selection
-#define AT91C_SPI_MODFDIS     ((unsigned int) 0x1 <<  4) // (SPI) Mode Fault Detection
-#define AT91C_SPI_LLB         ((unsigned int) 0x1 <<  7) // (SPI) Clock Selection
-#define AT91C_SPI_PCS         ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select
-#define AT91C_SPI_DLYBCS      ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects
-// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
-#define AT91C_SPI_RD          ((unsigned int) 0xFFFF <<  0) // (SPI) Receive Data
-#define AT91C_SPI_RPCS        ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
-#define AT91C_SPI_TD          ((unsigned int) 0xFFFF <<  0) // (SPI) Transmit Data
-#define AT91C_SPI_TPCS        ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
-#define AT91C_SPI_RDRF        ((unsigned int) 0x1 <<  0) // (SPI) Receive Data Register Full
-#define AT91C_SPI_TDRE        ((unsigned int) 0x1 <<  1) // (SPI) Transmit Data Register Empty
-#define AT91C_SPI_MODF        ((unsigned int) 0x1 <<  2) // (SPI) Mode Fault Error
-#define AT91C_SPI_OVRES       ((unsigned int) 0x1 <<  3) // (SPI) Overrun Error Status
-#define AT91C_SPI_ENDRX       ((unsigned int) 0x1 <<  4) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_ENDTX       ((unsigned int) 0x1 <<  5) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_RXBUFF      ((unsigned int) 0x1 <<  6) // (SPI) RXBUFF Interrupt
-#define AT91C_SPI_TXBUFE      ((unsigned int) 0x1 <<  7) // (SPI) TXBUFE Interrupt
-#define AT91C_SPI_NSSR        ((unsigned int) 0x1 <<  8) // (SPI) NSSR Interrupt
-#define AT91C_SPI_TXEMPTY     ((unsigned int) 0x1 <<  9) // (SPI) TXEMPTY Interrupt
-#define AT91C_SPI_SPIENS      ((unsigned int) 0x1 << 16) // (SPI) Enable Status
-// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
-// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
-// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
-// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
-#define AT91C_SPI_CPOL        ((unsigned int) 0x1 <<  0) // (SPI) Clock Polarity
-#define AT91C_SPI_NCPHA       ((unsigned int) 0x1 <<  1) // (SPI) Clock Phase
-#define AT91C_SPI_CSAAT       ((unsigned int) 0x1 <<  3) // (SPI) Chip Select Active After Transfer
-#define AT91C_SPI_BITS        ((unsigned int) 0xF <<  4) // (SPI) Bits Per Transfer
-#define     AT91C_SPI_BITS_8                    ((unsigned int) 0x0 <<  4) // (SPI) 8 Bits Per transfer
-#define     AT91C_SPI_BITS_9                    ((unsigned int) 0x1 <<  4) // (SPI) 9 Bits Per transfer
-#define     AT91C_SPI_BITS_10                   ((unsigned int) 0x2 <<  4) // (SPI) 10 Bits Per transfer
-#define     AT91C_SPI_BITS_11                   ((unsigned int) 0x3 <<  4) // (SPI) 11 Bits Per transfer
-#define     AT91C_SPI_BITS_12                   ((unsigned int) 0x4 <<  4) // (SPI) 12 Bits Per transfer
-#define     AT91C_SPI_BITS_13                   ((unsigned int) 0x5 <<  4) // (SPI) 13 Bits Per transfer
-#define     AT91C_SPI_BITS_14                   ((unsigned int) 0x6 <<  4) // (SPI) 14 Bits Per transfer
-#define     AT91C_SPI_BITS_15                   ((unsigned int) 0x7 <<  4) // (SPI) 15 Bits Per transfer
-#define     AT91C_SPI_BITS_16                   ((unsigned int) 0x8 <<  4) // (SPI) 16 Bits Per transfer
-#define AT91C_SPI_SCBR        ((unsigned int) 0xFF <<  8) // (SPI) Serial Clock Baud Rate
-#define AT91C_SPI_DLYBS       ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK
-#define AT91C_SPI_DLYBCT      ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers
+/* -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */
+#define AT91C_SPI_SPIEN              ( ( unsigned int ) 0x1 << 0 )    /* (SPI) SPI Enable */
+#define AT91C_SPI_SPIDIS             ( ( unsigned int ) 0x1 << 1 )    /* (SPI) SPI Disable */
+#define AT91C_SPI_SWRST              ( ( unsigned int ) 0x1 << 7 )    /* (SPI) SPI Software reset */
+#define AT91C_SPI_LASTXFER           ( ( unsigned int ) 0x1 << 24 )   /* (SPI) SPI Last Transfer */
+/* -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- */
+#define AT91C_SPI_MSTR               ( ( unsigned int ) 0x1 << 0 )    /* (SPI) Master/Slave Mode */
+#define AT91C_SPI_PS                 ( ( unsigned int ) 0x1 << 1 )    /* (SPI) Peripheral Select */
+#define     AT91C_SPI_PS_FIXED       ( ( unsigned int ) 0x0 << 1 )    /* (SPI) Fixed Peripheral Select */
+#define     AT91C_SPI_PS_VARIABLE    ( ( unsigned int ) 0x1 << 1 )    /* (SPI) Variable Peripheral Select */
+#define AT91C_SPI_PCSDEC             ( ( unsigned int ) 0x1 << 2 )    /* (SPI) Chip Select Decode */
+#define AT91C_SPI_FDIV               ( ( unsigned int ) 0x1 << 3 )    /* (SPI) Clock Selection */
+#define AT91C_SPI_MODFDIS            ( ( unsigned int ) 0x1 << 4 )    /* (SPI) Mode Fault Detection */
+#define AT91C_SPI_LLB                ( ( unsigned int ) 0x1 << 7 )    /* (SPI) Clock Selection */
+#define AT91C_SPI_PCS                ( ( unsigned int ) 0xF << 16 )   /* (SPI) Peripheral Chip Select */
+#define AT91C_SPI_DLYBCS             ( ( unsigned int ) 0xFF << 24 )  /* (SPI) Delay Between Chip Selects */
+/* -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- */
+#define AT91C_SPI_RD                 ( ( unsigned int ) 0xFFFF << 0 ) /* (SPI) Receive Data */
+#define AT91C_SPI_RPCS               ( ( unsigned int ) 0xF << 16 )   /* (SPI) Peripheral Chip Select Status */
+/* -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- */
+#define AT91C_SPI_TD                 ( ( unsigned int ) 0xFFFF << 0 ) /* (SPI) Transmit Data */
+#define AT91C_SPI_TPCS               ( ( unsigned int ) 0xF << 16 )   /* (SPI) Peripheral Chip Select Status */
+/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
+#define AT91C_SPI_RDRF               ( ( unsigned int ) 0x1 << 0 )    /* (SPI) Receive Data Register Full */
+#define AT91C_SPI_TDRE               ( ( unsigned int ) 0x1 << 1 )    /* (SPI) Transmit Data Register Empty */
+#define AT91C_SPI_MODF               ( ( unsigned int ) 0x1 << 2 )    /* (SPI) Mode Fault Error */
+#define AT91C_SPI_OVRES              ( ( unsigned int ) 0x1 << 3 )    /* (SPI) Overrun Error Status */
+#define AT91C_SPI_ENDRX              ( ( unsigned int ) 0x1 << 4 )    /* (SPI) End of Receiver Transfer */
+#define AT91C_SPI_ENDTX              ( ( unsigned int ) 0x1 << 5 )    /* (SPI) End of Receiver Transfer */
+#define AT91C_SPI_RXBUFF             ( ( unsigned int ) 0x1 << 6 )    /* (SPI) RXBUFF Interrupt */
+#define AT91C_SPI_TXBUFE             ( ( unsigned int ) 0x1 << 7 )    /* (SPI) TXBUFE Interrupt */
+#define AT91C_SPI_NSSR               ( ( unsigned int ) 0x1 << 8 )    /* (SPI) NSSR Interrupt */
+#define AT91C_SPI_TXEMPTY            ( ( unsigned int ) 0x1 << 9 )    /* (SPI) TXEMPTY Interrupt */
+#define AT91C_SPI_SPIENS             ( ( unsigned int ) 0x1 << 16 )   /* (SPI) Enable Status */
+/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
+/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
+/* -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */
+/* -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */
+#define AT91C_SPI_CPOL           ( ( unsigned int ) 0x1 << 0 )   /* (SPI) Clock Polarity */
+#define AT91C_SPI_NCPHA          ( ( unsigned int ) 0x1 << 1 )   /* (SPI) Clock Phase */
+#define AT91C_SPI_CSAAT          ( ( unsigned int ) 0x1 << 3 )   /* (SPI) Chip Select Active After Transfer */
+#define AT91C_SPI_BITS           ( ( unsigned int ) 0xF << 4 )   /* (SPI) Bits Per Transfer */
+#define     AT91C_SPI_BITS_8     ( ( unsigned int ) 0x0 << 4 )   /* (SPI) 8 Bits Per transfer */
+#define     AT91C_SPI_BITS_9     ( ( unsigned int ) 0x1 << 4 )   /* (SPI) 9 Bits Per transfer */
+#define     AT91C_SPI_BITS_10    ( ( unsigned int ) 0x2 << 4 )   /* (SPI) 10 Bits Per transfer */
+#define     AT91C_SPI_BITS_11    ( ( unsigned int ) 0x3 << 4 )   /* (SPI) 11 Bits Per transfer */
+#define     AT91C_SPI_BITS_12    ( ( unsigned int ) 0x4 << 4 )   /* (SPI) 12 Bits Per transfer */
+#define     AT91C_SPI_BITS_13    ( ( unsigned int ) 0x5 << 4 )   /* (SPI) 13 Bits Per transfer */
+#define     AT91C_SPI_BITS_14    ( ( unsigned int ) 0x6 << 4 )   /* (SPI) 14 Bits Per transfer */
+#define     AT91C_SPI_BITS_15    ( ( unsigned int ) 0x7 << 4 )   /* (SPI) 15 Bits Per transfer */
+#define     AT91C_SPI_BITS_16    ( ( unsigned int ) 0x8 << 4 )   /* (SPI) 16 Bits Per transfer */
+#define AT91C_SPI_SCBR           ( ( unsigned int ) 0xFF << 8 )  /* (SPI) Serial Clock Baud Rate */
+#define AT91C_SPI_DLYBS          ( ( unsigned int ) 0xFF << 16 ) /* (SPI) Delay Before SPCK */
+#define AT91C_SPI_DLYBCT         ( ( unsigned int ) 0xFF << 24 ) /* (SPI) Delay Between Consecutive Transfers */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Usart
-// *****************************************************************************
-typedef struct _AT91S_USART {
-    AT91_REG     US_CR;     // Control Register
-    AT91_REG     US_MR;     // Mode Register
-    AT91_REG     US_IER;    // Interrupt Enable Register
-    AT91_REG     US_IDR;    // Interrupt Disable Register
-    AT91_REG     US_IMR;    // Interrupt Mask Register
-    AT91_REG     US_CSR;    // Channel Status Register
-    AT91_REG     US_RHR;    // Receiver Holding Register
-    AT91_REG     US_THR;    // Transmitter Holding Register
-    AT91_REG     US_BRGR;   // Baud Rate Generator Register
-    AT91_REG     US_RTOR;   // Receiver Time-out Register
-    AT91_REG     US_TTGR;   // Transmitter Time-guard Register
-    AT91_REG     Reserved0[5];  //
-    AT91_REG     US_FIDI;   // FI_DI_Ratio Register
-    AT91_REG     US_NER;    // Nb Errors Register
-    AT91_REG     Reserved1[1];  //
-    AT91_REG     US_IF;     // IRDA_FILTER Register
-    AT91_REG     Reserved2[44];     //
-    AT91_REG     US_RPR;    // Receive Pointer Register
-    AT91_REG     US_RCR;    // Receive Counter Register
-    AT91_REG     US_TPR;    // Transmit Pointer Register
-    AT91_REG     US_TCR;    // Transmit Counter Register
-    AT91_REG     US_RNPR;   // Receive Next Pointer Register
-    AT91_REG     US_RNCR;   // Receive Next Counter Register
-    AT91_REG     US_TNPR;   // Transmit Next Pointer Register
-    AT91_REG     US_TNCR;   // Transmit Next Counter Register
-    AT91_REG     US_PTCR;   // PDC Transfer Control Register
-    AT91_REG     US_PTSR;   // PDC Transfer Status Register
-} AT91S_USART, *AT91PS_USART;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Usart */
+/* ***************************************************************************** */
+typedef struct _AT91S_USART
+{
+    AT91_REG US_CR;           /* Control Register */
+    AT91_REG US_MR;           /* Mode Register */
+    AT91_REG US_IER;          /* Interrupt Enable Register */
+    AT91_REG US_IDR;          /* Interrupt Disable Register */
+    AT91_REG US_IMR;          /* Interrupt Mask Register */
+    AT91_REG US_CSR;          /* Channel Status Register */
+    AT91_REG US_RHR;          /* Receiver Holding Register */
+    AT91_REG US_THR;          /* Transmitter Holding Register */
+    AT91_REG US_BRGR;         /* Baud Rate Generator Register */
+    AT91_REG US_RTOR;         /* Receiver Time-out Register */
+    AT91_REG US_TTGR;         /* Transmitter Time-guard Register */
+    AT91_REG Reserved0[ 5 ];  /* */
+    AT91_REG US_FIDI;         /* FI_DI_Ratio Register */
+    AT91_REG US_NER;          /* Nb Errors Register */
+    AT91_REG Reserved1[ 1 ];  /* */
+    AT91_REG US_IF;           /* IRDA_FILTER Register */
+    AT91_REG Reserved2[ 44 ]; /* */
+    AT91_REG US_RPR;          /* Receive Pointer Register */
+    AT91_REG US_RCR;          /* Receive Counter Register */
+    AT91_REG US_TPR;          /* Transmit Pointer Register */
+    AT91_REG US_TCR;          /* Transmit Counter Register */
+    AT91_REG US_RNPR;         /* Receive Next Pointer Register */
+    AT91_REG US_RNCR;         /* Receive Next Counter Register */
+    AT91_REG US_TNPR;         /* Transmit Next Pointer Register */
+    AT91_REG US_TNCR;         /* Transmit Next Counter Register */
+    AT91_REG US_PTCR;         /* PDC Transfer Control Register */
+    AT91_REG US_PTSR;         /* PDC Transfer Status Register */
+} AT91S_USART, * AT91PS_USART;
 
-// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
-#define AT91C_US_STTBRK       ((unsigned int) 0x1 <<  9) // (USART) Start Break
-#define AT91C_US_STPBRK       ((unsigned int) 0x1 << 10) // (USART) Stop Break
-#define AT91C_US_STTTO        ((unsigned int) 0x1 << 11) // (USART) Start Time-out
-#define AT91C_US_SENDA        ((unsigned int) 0x1 << 12) // (USART) Send Address
-#define AT91C_US_RSTIT        ((unsigned int) 0x1 << 13) // (USART) Reset Iterations
-#define AT91C_US_RSTNACK      ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge
-#define AT91C_US_RETTO        ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out
-#define AT91C_US_DTREN        ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable
-#define AT91C_US_DTRDIS       ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable
-#define AT91C_US_RTSEN        ((unsigned int) 0x1 << 18) // (USART) Request to Send enable
-#define AT91C_US_RTSDIS       ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable
-// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
-#define AT91C_US_USMODE       ((unsigned int) 0xF <<  0) // (USART) Usart mode
-#define     AT91C_US_USMODE_NORMAL               ((unsigned int) 0x0) // (USART) Normal
-#define     AT91C_US_USMODE_RS485                ((unsigned int) 0x1) // (USART) RS485
-#define     AT91C_US_USMODE_HWHSH                ((unsigned int) 0x2) // (USART) Hardware Handshaking
-#define     AT91C_US_USMODE_MODEM                ((unsigned int) 0x3) // (USART) Modem
-#define     AT91C_US_USMODE_ISO7816_0            ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0
-#define     AT91C_US_USMODE_ISO7816_1            ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1
-#define     AT91C_US_USMODE_IRDA                 ((unsigned int) 0x8) // (USART) IrDA
-#define     AT91C_US_USMODE_SWHSH                ((unsigned int) 0xC) // (USART) Software Handshaking
-#define AT91C_US_CLKS         ((unsigned int) 0x3 <<  4) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define     AT91C_US_CLKS_CLOCK                ((unsigned int) 0x0 <<  4) // (USART) Clock
-#define     AT91C_US_CLKS_FDIV1                ((unsigned int) 0x1 <<  4) // (USART) fdiv1
-#define     AT91C_US_CLKS_SLOW                 ((unsigned int) 0x2 <<  4) // (USART) slow_clock (ARM)
-#define     AT91C_US_CLKS_EXT                  ((unsigned int) 0x3 <<  4) // (USART) External (SCK)
-#define AT91C_US_CHRL         ((unsigned int) 0x3 <<  6) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define     AT91C_US_CHRL_5_BITS               ((unsigned int) 0x0 <<  6) // (USART) Character Length: 5 bits
-#define     AT91C_US_CHRL_6_BITS               ((unsigned int) 0x1 <<  6) // (USART) Character Length: 6 bits
-#define     AT91C_US_CHRL_7_BITS               ((unsigned int) 0x2 <<  6) // (USART) Character Length: 7 bits
-#define     AT91C_US_CHRL_8_BITS               ((unsigned int) 0x3 <<  6) // (USART) Character Length: 8 bits
-#define AT91C_US_SYNC         ((unsigned int) 0x1 <<  8) // (USART) Synchronous Mode Select
-#define AT91C_US_NBSTOP       ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits
-#define     AT91C_US_NBSTOP_1_BIT                ((unsigned int) 0x0 << 12) // (USART) 1 stop bit
-#define     AT91C_US_NBSTOP_15_BIT               ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
-#define     AT91C_US_NBSTOP_2_BIT                ((unsigned int) 0x2 << 12) // (USART) 2 stop bits
-#define AT91C_US_MSBF         ((unsigned int) 0x1 << 16) // (USART) Bit Order
-#define AT91C_US_MODE9        ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length
-#define AT91C_US_CKLO         ((unsigned int) 0x1 << 18) // (USART) Clock Output Select
-#define AT91C_US_OVER         ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode
-#define AT91C_US_INACK        ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge
-#define AT91C_US_DSNACK       ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK
-#define AT91C_US_MAX_ITER     ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions
-#define AT91C_US_FILTER       ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter
-// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
-#define AT91C_US_RXBRK        ((unsigned int) 0x1 <<  2) // (USART) Break Received/End of Break
-#define AT91C_US_TIMEOUT      ((unsigned int) 0x1 <<  8) // (USART) Receiver Time-out
-#define AT91C_US_ITERATION    ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached
-#define AT91C_US_NACK         ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge
-#define AT91C_US_RIIC         ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag
-#define AT91C_US_DSRIC        ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag
-#define AT91C_US_DCDIC        ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag
-#define AT91C_US_CTSIC        ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag
-// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
-// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
-// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
-#define AT91C_US_RI           ((unsigned int) 0x1 << 20) // (USART) Image of RI Input
-#define AT91C_US_DSR          ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input
-#define AT91C_US_DCD          ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input
-#define AT91C_US_CTS          ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input
+/* -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- */
+#define AT91C_US_STTBRK                  ( ( unsigned int ) 0x1 << 9 )  /* (USART) Start Break */
+#define AT91C_US_STPBRK                  ( ( unsigned int ) 0x1 << 10 ) /* (USART) Stop Break */
+#define AT91C_US_STTTO                   ( ( unsigned int ) 0x1 << 11 ) /* (USART) Start Time-out */
+#define AT91C_US_SENDA                   ( ( unsigned int ) 0x1 << 12 ) /* (USART) Send Address */
+#define AT91C_US_RSTIT                   ( ( unsigned int ) 0x1 << 13 ) /* (USART) Reset Iterations */
+#define AT91C_US_RSTNACK                 ( ( unsigned int ) 0x1 << 14 ) /* (USART) Reset Non Acknowledge */
+#define AT91C_US_RETTO                   ( ( unsigned int ) 0x1 << 15 ) /* (USART) Rearm Time-out */
+#define AT91C_US_DTREN                   ( ( unsigned int ) 0x1 << 16 ) /* (USART) Data Terminal ready Enable */
+#define AT91C_US_DTRDIS                  ( ( unsigned int ) 0x1 << 17 ) /* (USART) Data Terminal ready Disable */
+#define AT91C_US_RTSEN                   ( ( unsigned int ) 0x1 << 18 ) /* (USART) Request to Send enable */
+#define AT91C_US_RTSDIS                  ( ( unsigned int ) 0x1 << 19 ) /* (USART) Request to Send Disable */
+/* -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- */
+#define AT91C_US_USMODE                  ( ( unsigned int ) 0xF << 0 )  /* (USART) Usart mode */
+#define     AT91C_US_USMODE_NORMAL       ( ( unsigned int ) 0x0 )       /* (USART) Normal */
+#define     AT91C_US_USMODE_RS485        ( ( unsigned int ) 0x1 )       /* (USART) RS485 */
+#define     AT91C_US_USMODE_HWHSH        ( ( unsigned int ) 0x2 )       /* (USART) Hardware Handshaking */
+#define     AT91C_US_USMODE_MODEM        ( ( unsigned int ) 0x3 )       /* (USART) Modem */
+#define     AT91C_US_USMODE_ISO7816_0    ( ( unsigned int ) 0x4 )       /* (USART) ISO7816 protocol: T = 0 */
+#define     AT91C_US_USMODE_ISO7816_1    ( ( unsigned int ) 0x6 )       /* (USART) ISO7816 protocol: T = 1 */
+#define     AT91C_US_USMODE_IRDA         ( ( unsigned int ) 0x8 )       /* (USART) IrDA */
+#define     AT91C_US_USMODE_SWHSH        ( ( unsigned int ) 0xC )       /* (USART) Software Handshaking */
+#define AT91C_US_CLKS                    ( ( unsigned int ) 0x3 << 4 )  /* (USART) Clock Selection (Baud Rate generator Input Clock */
+#define     AT91C_US_CLKS_CLOCK          ( ( unsigned int ) 0x0 << 4 )  /* (USART) Clock */
+#define     AT91C_US_CLKS_FDIV1          ( ( unsigned int ) 0x1 << 4 )  /* (USART) fdiv1 */
+#define     AT91C_US_CLKS_SLOW           ( ( unsigned int ) 0x2 << 4 )  /* (USART) slow_clock (ARM) */
+#define     AT91C_US_CLKS_EXT            ( ( unsigned int ) 0x3 << 4 )  /* (USART) External (SCK) */
+#define AT91C_US_CHRL                    ( ( unsigned int ) 0x3 << 6 )  /* (USART) Clock Selection (Baud Rate generator Input Clock */
+#define     AT91C_US_CHRL_5_BITS         ( ( unsigned int ) 0x0 << 6 )  /* (USART) Character Length: 5 bits */
+#define     AT91C_US_CHRL_6_BITS         ( ( unsigned int ) 0x1 << 6 )  /* (USART) Character Length: 6 bits */
+#define     AT91C_US_CHRL_7_BITS         ( ( unsigned int ) 0x2 << 6 )  /* (USART) Character Length: 7 bits */
+#define     AT91C_US_CHRL_8_BITS         ( ( unsigned int ) 0x3 << 6 )  /* (USART) Character Length: 8 bits */
+#define AT91C_US_SYNC                    ( ( unsigned int ) 0x1 << 8 )  /* (USART) Synchronous Mode Select */
+#define AT91C_US_NBSTOP                  ( ( unsigned int ) 0x3 << 12 ) /* (USART) Number of Stop bits */
+#define     AT91C_US_NBSTOP_1_BIT        ( ( unsigned int ) 0x0 << 12 ) /* (USART) 1 stop bit */
+#define     AT91C_US_NBSTOP_15_BIT       ( ( unsigned int ) 0x1 << 12 ) /* (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits */
+#define     AT91C_US_NBSTOP_2_BIT        ( ( unsigned int ) 0x2 << 12 ) /* (USART) 2 stop bits */
+#define AT91C_US_MSBF                    ( ( unsigned int ) 0x1 << 16 ) /* (USART) Bit Order */
+#define AT91C_US_MODE9                   ( ( unsigned int ) 0x1 << 17 ) /* (USART) 9-bit Character length */
+#define AT91C_US_CKLO                    ( ( unsigned int ) 0x1 << 18 ) /* (USART) Clock Output Select */
+#define AT91C_US_OVER                    ( ( unsigned int ) 0x1 << 19 ) /* (USART) Over Sampling Mode */
+#define AT91C_US_INACK                   ( ( unsigned int ) 0x1 << 20 ) /* (USART) Inhibit Non Acknowledge */
+#define AT91C_US_DSNACK                  ( ( unsigned int ) 0x1 << 21 ) /* (USART) Disable Successive NACK */
+#define AT91C_US_MAX_ITER                ( ( unsigned int ) 0x1 << 24 ) /* (USART) Number of Repetitions */
+#define AT91C_US_FILTER                  ( ( unsigned int ) 0x1 << 28 ) /* (USART) Receive Line Filter */
+/* -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- */
+#define AT91C_US_RXBRK                   ( ( unsigned int ) 0x1 << 2 )  /* (USART) Break Received/End of Break */
+#define AT91C_US_TIMEOUT                 ( ( unsigned int ) 0x1 << 8 )  /* (USART) Receiver Time-out */
+#define AT91C_US_ITERATION               ( ( unsigned int ) 0x1 << 10 ) /* (USART) Max number of Repetitions Reached */
+#define AT91C_US_NACK                    ( ( unsigned int ) 0x1 << 13 ) /* (USART) Non Acknowledge */
+#define AT91C_US_RIIC                    ( ( unsigned int ) 0x1 << 16 ) /* (USART) Ring INdicator Input Change Flag */
+#define AT91C_US_DSRIC                   ( ( unsigned int ) 0x1 << 17 ) /* (USART) Data Set Ready Input Change Flag */
+#define AT91C_US_DCDIC                   ( ( unsigned int ) 0x1 << 18 ) /* (USART) Data Carrier Flag */
+#define AT91C_US_CTSIC                   ( ( unsigned int ) 0x1 << 19 ) /* (USART) Clear To Send Input Change Flag */
+/* -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- */
+/* -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- */
+/* -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- */
+#define AT91C_US_RI     ( ( unsigned int ) 0x1 << 20 )   /* (USART) Image of RI Input */
+#define AT91C_US_DSR    ( ( unsigned int ) 0x1 << 21 )   /* (USART) Image of DSR Input */
+#define AT91C_US_DCD    ( ( unsigned int ) 0x1 << 22 )   /* (USART) Image of DCD Input */
+#define AT91C_US_CTS    ( ( unsigned int ) 0x1 << 23 )   /* (USART) Image of CTS Input */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_SSC {
-    AT91_REG     SSC_CR;    // Control Register
-    AT91_REG     SSC_CMR;   // Clock Mode Register
-    AT91_REG     Reserved0[2];  //
-    AT91_REG     SSC_RCMR;  // Receive Clock ModeRegister
-    AT91_REG     SSC_RFMR;  // Receive Frame Mode Register
-    AT91_REG     SSC_TCMR;  // Transmit Clock Mode Register
-    AT91_REG     SSC_TFMR;  // Transmit Frame Mode Register
-    AT91_REG     SSC_RHR;   // Receive Holding Register
-    AT91_REG     SSC_THR;   // Transmit Holding Register
-    AT91_REG     Reserved1[2];  //
-    AT91_REG     SSC_RSHR;  // Receive Sync Holding Register
-    AT91_REG     SSC_TSHR;  // Transmit Sync Holding Register
-    AT91_REG     Reserved2[2];  //
-    AT91_REG     SSC_SR;    // Status Register
-    AT91_REG     SSC_IER;   // Interrupt Enable Register
-    AT91_REG     SSC_IDR;   // Interrupt Disable Register
-    AT91_REG     SSC_IMR;   // Interrupt Mask Register
-    AT91_REG     Reserved3[44];     //
-    AT91_REG     SSC_RPR;   // Receive Pointer Register
-    AT91_REG     SSC_RCR;   // Receive Counter Register
-    AT91_REG     SSC_TPR;   // Transmit Pointer Register
-    AT91_REG     SSC_TCR;   // Transmit Counter Register
-    AT91_REG     SSC_RNPR;  // Receive Next Pointer Register
-    AT91_REG     SSC_RNCR;  // Receive Next Counter Register
-    AT91_REG     SSC_TNPR;  // Transmit Next Pointer Register
-    AT91_REG     SSC_TNCR;  // Transmit Next Counter Register
-    AT91_REG     SSC_PTCR;  // PDC Transfer Control Register
-    AT91_REG     SSC_PTSR;  // PDC Transfer Status Register
-} AT91S_SSC, *AT91PS_SSC;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_SSC
+{
+    AT91_REG SSC_CR;          /* Control Register */
+    AT91_REG SSC_CMR;         /* Clock Mode Register */
+    AT91_REG Reserved0[ 2 ];  /* */
+    AT91_REG SSC_RCMR;        /* Receive Clock ModeRegister */
+    AT91_REG SSC_RFMR;        /* Receive Frame Mode Register */
+    AT91_REG SSC_TCMR;        /* Transmit Clock Mode Register */
+    AT91_REG SSC_TFMR;        /* Transmit Frame Mode Register */
+    AT91_REG SSC_RHR;         /* Receive Holding Register */
+    AT91_REG SSC_THR;         /* Transmit Holding Register */
+    AT91_REG Reserved1[ 2 ];  /* */
+    AT91_REG SSC_RSHR;        /* Receive Sync Holding Register */
+    AT91_REG SSC_TSHR;        /* Transmit Sync Holding Register */
+    AT91_REG Reserved2[ 2 ];  /* */
+    AT91_REG SSC_SR;          /* Status Register */
+    AT91_REG SSC_IER;         /* Interrupt Enable Register */
+    AT91_REG SSC_IDR;         /* Interrupt Disable Register */
+    AT91_REG SSC_IMR;         /* Interrupt Mask Register */
+    AT91_REG Reserved3[ 44 ]; /* */
+    AT91_REG SSC_RPR;         /* Receive Pointer Register */
+    AT91_REG SSC_RCR;         /* Receive Counter Register */
+    AT91_REG SSC_TPR;         /* Transmit Pointer Register */
+    AT91_REG SSC_TCR;         /* Transmit Counter Register */
+    AT91_REG SSC_RNPR;        /* Receive Next Pointer Register */
+    AT91_REG SSC_RNCR;        /* Receive Next Counter Register */
+    AT91_REG SSC_TNPR;        /* Transmit Next Pointer Register */
+    AT91_REG SSC_TNCR;        /* Transmit Next Counter Register */
+    AT91_REG SSC_PTCR;        /* PDC Transfer Control Register */
+    AT91_REG SSC_PTSR;        /* PDC Transfer Status Register */
+} AT91S_SSC, * AT91PS_SSC;
 
-// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
-#define AT91C_SSC_RXEN        ((unsigned int) 0x1 <<  0) // (SSC) Receive Enable
-#define AT91C_SSC_RXDIS       ((unsigned int) 0x1 <<  1) // (SSC) Receive Disable
-#define AT91C_SSC_TXEN        ((unsigned int) 0x1 <<  8) // (SSC) Transmit Enable
-#define AT91C_SSC_TXDIS       ((unsigned int) 0x1 <<  9) // (SSC) Transmit Disable
-#define AT91C_SSC_SWRST       ((unsigned int) 0x1 << 15) // (SSC) Software Reset
-// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
-#define AT91C_SSC_CKS         ((unsigned int) 0x3 <<  0) // (SSC) Receive/Transmit Clock Selection
-#define     AT91C_SSC_CKS_DIV                  ((unsigned int) 0x0) // (SSC) Divided Clock
-#define     AT91C_SSC_CKS_TK                   ((unsigned int) 0x1) // (SSC) TK Clock signal
-#define     AT91C_SSC_CKS_RK                   ((unsigned int) 0x2) // (SSC) RK pin
-#define AT91C_SSC_CKO         ((unsigned int) 0x7 <<  2) // (SSC) Receive/Transmit Clock Output Mode Selection
-#define     AT91C_SSC_CKO_NONE                 ((unsigned int) 0x0 <<  2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
-#define     AT91C_SSC_CKO_CONTINOUS            ((unsigned int) 0x1 <<  2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
-#define     AT91C_SSC_CKO_DATA_TX              ((unsigned int) 0x2 <<  2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
-#define AT91C_SSC_CKI         ((unsigned int) 0x1 <<  5) // (SSC) Receive/Transmit Clock Inversion
-#define AT91C_SSC_START       ((unsigned int) 0xF <<  8) // (SSC) Receive/Transmit Start Selection
-#define     AT91C_SSC_START_CONTINOUS            ((unsigned int) 0x0 <<  8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
-#define     AT91C_SSC_START_TX                   ((unsigned int) 0x1 <<  8) // (SSC) Transmit/Receive start
-#define     AT91C_SSC_START_LOW_RF               ((unsigned int) 0x2 <<  8) // (SSC) Detection of a low level on RF input
-#define     AT91C_SSC_START_HIGH_RF              ((unsigned int) 0x3 <<  8) // (SSC) Detection of a high level on RF input
-#define     AT91C_SSC_START_FALL_RF              ((unsigned int) 0x4 <<  8) // (SSC) Detection of a falling edge on RF input
-#define     AT91C_SSC_START_RISE_RF              ((unsigned int) 0x5 <<  8) // (SSC) Detection of a rising edge on RF input
-#define     AT91C_SSC_START_LEVEL_RF             ((unsigned int) 0x6 <<  8) // (SSC) Detection of any level change on RF input
-#define     AT91C_SSC_START_EDGE_RF              ((unsigned int) 0x7 <<  8) // (SSC) Detection of any edge on RF input
-#define     AT91C_SSC_START_0                    ((unsigned int) 0x8 <<  8) // (SSC) Compare 0
-#define AT91C_SSC_STTDLY      ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay
-#define AT91C_SSC_PERIOD      ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
-// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
-#define AT91C_SSC_DATLEN      ((unsigned int) 0x1F <<  0) // (SSC) Data Length
-#define AT91C_SSC_LOOP        ((unsigned int) 0x1 <<  5) // (SSC) Loop Mode
-#define AT91C_SSC_MSBF        ((unsigned int) 0x1 <<  7) // (SSC) Most Significant Bit First
-#define AT91C_SSC_DATNB       ((unsigned int) 0xF <<  8) // (SSC) Data Number per Frame
-#define AT91C_SSC_FSLEN       ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length
-#define AT91C_SSC_FSOS        ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
-#define     AT91C_SSC_FSOS_NONE                 ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
-#define     AT91C_SSC_FSOS_NEGATIVE             ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
-#define     AT91C_SSC_FSOS_POSITIVE             ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
-#define     AT91C_SSC_FSOS_LOW                  ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
-#define     AT91C_SSC_FSOS_HIGH                 ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
-#define     AT91C_SSC_FSOS_TOGGLE               ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
-#define AT91C_SSC_FSEDGE      ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection
-// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
-// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
-#define AT91C_SSC_DATDEF      ((unsigned int) 0x1 <<  5) // (SSC) Data Default Value
-#define AT91C_SSC_FSDEN       ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable
-// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
-#define AT91C_SSC_TXRDY       ((unsigned int) 0x1 <<  0) // (SSC) Transmit Ready
-#define AT91C_SSC_TXEMPTY     ((unsigned int) 0x1 <<  1) // (SSC) Transmit Empty
-#define AT91C_SSC_ENDTX       ((unsigned int) 0x1 <<  2) // (SSC) End Of Transmission
-#define AT91C_SSC_TXBUFE      ((unsigned int) 0x1 <<  3) // (SSC) Transmit Buffer Empty
-#define AT91C_SSC_RXRDY       ((unsigned int) 0x1 <<  4) // (SSC) Receive Ready
-#define AT91C_SSC_OVRUN       ((unsigned int) 0x1 <<  5) // (SSC) Receive Overrun
-#define AT91C_SSC_ENDRX       ((unsigned int) 0x1 <<  6) // (SSC) End of Reception
-#define AT91C_SSC_RXBUFF      ((unsigned int) 0x1 <<  7) // (SSC) Receive Buffer Full
-#define AT91C_SSC_TXSYN       ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync
-#define AT91C_SSC_RXSYN       ((unsigned int) 0x1 << 11) // (SSC) Receive Sync
-#define AT91C_SSC_TXENA       ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable
-#define AT91C_SSC_RXENA       ((unsigned int) 0x1 << 17) // (SSC) Receive Enable
-// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
-// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
-// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
+/* -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- */
+#define AT91C_SSC_RXEN                    ( ( unsigned int ) 0x1 << 0 )   /* (SSC) Receive Enable */
+#define AT91C_SSC_RXDIS                   ( ( unsigned int ) 0x1 << 1 )   /* (SSC) Receive Disable */
+#define AT91C_SSC_TXEN                    ( ( unsigned int ) 0x1 << 8 )   /* (SSC) Transmit Enable */
+#define AT91C_SSC_TXDIS                   ( ( unsigned int ) 0x1 << 9 )   /* (SSC) Transmit Disable */
+#define AT91C_SSC_SWRST                   ( ( unsigned int ) 0x1 << 15 )  /* (SSC) Software Reset */
+/* -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- */
+#define AT91C_SSC_CKS                     ( ( unsigned int ) 0x3 << 0 )   /* (SSC) Receive/Transmit Clock Selection */
+#define     AT91C_SSC_CKS_DIV             ( ( unsigned int ) 0x0 )        /* (SSC) Divided Clock */
+#define     AT91C_SSC_CKS_TK              ( ( unsigned int ) 0x1 )        /* (SSC) TK Clock signal */
+#define     AT91C_SSC_CKS_RK              ( ( unsigned int ) 0x2 )        /* (SSC) RK pin */
+#define AT91C_SSC_CKO                     ( ( unsigned int ) 0x7 << 2 )   /* (SSC) Receive/Transmit Clock Output Mode Selection */
+#define     AT91C_SSC_CKO_NONE            ( ( unsigned int ) 0x0 << 2 )   /* (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only */
+#define     AT91C_SSC_CKO_CONTINUOUS      ( ( unsigned int ) 0x1 << 2 )   /* (SSC) Continuous Receive/Transmit Clock RK pin: Output */
+#define     AT91C_SSC_CKO_DATA_TX         ( ( unsigned int ) 0x2 << 2 )   /* (SSC) Receive/Transmit Clock only during data transfers RK pin: Output */
+#define AT91C_SSC_CKI                     ( ( unsigned int ) 0x1 << 5 )   /* (SSC) Receive/Transmit Clock Inversion */
+#define AT91C_SSC_START                   ( ( unsigned int ) 0xF << 8 )   /* (SSC) Receive/Transmit Start Selection */
+#define     AT91C_SSC_START_CONTINUOUS    ( ( unsigned int ) 0x0 << 8 )   /* (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */
+#define     AT91C_SSC_START_TX            ( ( unsigned int ) 0x1 << 8 )   /* (SSC) Transmit/Receive start */
+#define     AT91C_SSC_START_LOW_RF        ( ( unsigned int ) 0x2 << 8 )   /* (SSC) Detection of a low level on RF input */
+#define     AT91C_SSC_START_HIGH_RF       ( ( unsigned int ) 0x3 << 8 )   /* (SSC) Detection of a high level on RF input */
+#define     AT91C_SSC_START_FALL_RF       ( ( unsigned int ) 0x4 << 8 )   /* (SSC) Detection of a falling edge on RF input */
+#define     AT91C_SSC_START_RISE_RF       ( ( unsigned int ) 0x5 << 8 )   /* (SSC) Detection of a rising edge on RF input */
+#define     AT91C_SSC_START_LEVEL_RF      ( ( unsigned int ) 0x6 << 8 )   /* (SSC) Detection of any level change on RF input */
+#define     AT91C_SSC_START_EDGE_RF       ( ( unsigned int ) 0x7 << 8 )   /* (SSC) Detection of any edge on RF input */
+#define     AT91C_SSC_START_0             ( ( unsigned int ) 0x8 << 8 )   /* (SSC) Compare 0 */
+#define AT91C_SSC_STTDLY                  ( ( unsigned int ) 0xFF << 16 ) /* (SSC) Receive/Transmit Start Delay */
+#define AT91C_SSC_PERIOD                  ( ( unsigned int ) 0xFF << 24 ) /* (SSC) Receive/Transmit Period Divider Selection */
+/* -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- */
+#define AT91C_SSC_DATLEN                  ( ( unsigned int ) 0x1F << 0 )  /* (SSC) Data Length */
+#define AT91C_SSC_LOOP                    ( ( unsigned int ) 0x1 << 5 )   /* (SSC) Loop Mode */
+#define AT91C_SSC_MSBF                    ( ( unsigned int ) 0x1 << 7 )   /* (SSC) Most Significant Bit First */
+#define AT91C_SSC_DATNB                   ( ( unsigned int ) 0xF << 8 )   /* (SSC) Data Number per Frame */
+#define AT91C_SSC_FSLEN                   ( ( unsigned int ) 0xF << 16 )  /* (SSC) Receive/Transmit Frame Sync length */
+#define AT91C_SSC_FSOS                    ( ( unsigned int ) 0x7 << 20 )  /* (SSC) Receive/Transmit Frame Sync Output Selection */
+#define     AT91C_SSC_FSOS_NONE           ( ( unsigned int ) 0x0 << 20 )  /* (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only */
+#define     AT91C_SSC_FSOS_NEGATIVE       ( ( unsigned int ) 0x1 << 20 )  /* (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse */
+#define     AT91C_SSC_FSOS_POSITIVE       ( ( unsigned int ) 0x2 << 20 )  /* (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse */
+#define     AT91C_SSC_FSOS_LOW            ( ( unsigned int ) 0x3 << 20 )  /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer */
+#define     AT91C_SSC_FSOS_HIGH           ( ( unsigned int ) 0x4 << 20 )  /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer */
+#define     AT91C_SSC_FSOS_TOGGLE         ( ( unsigned int ) 0x5 << 20 )  /* (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer */
+#define AT91C_SSC_FSEDGE                  ( ( unsigned int ) 0x1 << 24 )  /* (SSC) Frame Sync Edge Detection */
+/* -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- */
+/* -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- */
+#define AT91C_SSC_DATDEF                  ( ( unsigned int ) 0x1 << 5 )  /* (SSC) Data Default Value */
+#define AT91C_SSC_FSDEN                   ( ( unsigned int ) 0x1 << 23 ) /* (SSC) Frame Sync Data Enable */
+/* -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- */
+#define AT91C_SSC_TXRDY                   ( ( unsigned int ) 0x1 << 0 )  /* (SSC) Transmit Ready */
+#define AT91C_SSC_TXEMPTY                 ( ( unsigned int ) 0x1 << 1 )  /* (SSC) Transmit Empty */
+#define AT91C_SSC_ENDTX                   ( ( unsigned int ) 0x1 << 2 )  /* (SSC) End Of Transmission */
+#define AT91C_SSC_TXBUFE                  ( ( unsigned int ) 0x1 << 3 )  /* (SSC) Transmit Buffer Empty */
+#define AT91C_SSC_RXRDY                   ( ( unsigned int ) 0x1 << 4 )  /* (SSC) Receive Ready */
+#define AT91C_SSC_OVRUN                   ( ( unsigned int ) 0x1 << 5 )  /* (SSC) Receive Overrun */
+#define AT91C_SSC_ENDRX                   ( ( unsigned int ) 0x1 << 6 )  /* (SSC) End of Reception */
+#define AT91C_SSC_RXBUFF                  ( ( unsigned int ) 0x1 << 7 )  /* (SSC) Receive Buffer Full */
+#define AT91C_SSC_TXSYN                   ( ( unsigned int ) 0x1 << 10 ) /* (SSC) Transmit Sync */
+#define AT91C_SSC_RXSYN                   ( ( unsigned int ) 0x1 << 11 ) /* (SSC) Receive Sync */
+#define AT91C_SSC_TXENA                   ( ( unsigned int ) 0x1 << 16 ) /* (SSC) Transmit Enable */
+#define AT91C_SSC_RXENA                   ( ( unsigned int ) 0x1 << 17 ) /* (SSC) Receive Enable */
+/* -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- */
+/* -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- */
+/* -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Two-wire Interface
-// *****************************************************************************
-typedef struct _AT91S_TWI {
-    AT91_REG     TWI_CR;    // Control Register
-    AT91_REG     TWI_MMR;   // Master Mode Register
-    AT91_REG     Reserved0[1];  //
-    AT91_REG     TWI_IADR;  // Internal Address Register
-    AT91_REG     TWI_CWGR;  // Clock Waveform Generator Register
-    AT91_REG     Reserved1[3];  //
-    AT91_REG     TWI_SR;    // Status Register
-    AT91_REG     TWI_IER;   // Interrupt Enable Register
-    AT91_REG     TWI_IDR;   // Interrupt Disable Register
-    AT91_REG     TWI_IMR;   // Interrupt Mask Register
-    AT91_REG     TWI_RHR;   // Receive Holding Register
-    AT91_REG     TWI_THR;   // Transmit Holding Register
-} AT91S_TWI, *AT91PS_TWI;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Two-wire Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_TWI
+{
+    AT91_REG TWI_CR;         /* Control Register */
+    AT91_REG TWI_MMR;        /* Master Mode Register */
+    AT91_REG Reserved0[ 1 ]; /* */
+    AT91_REG TWI_IADR;       /* Internal Address Register */
+    AT91_REG TWI_CWGR;       /* Clock Waveform Generator Register */
+    AT91_REG Reserved1[ 3 ]; /* */
+    AT91_REG TWI_SR;         /* Status Register */
+    AT91_REG TWI_IER;        /* Interrupt Enable Register */
+    AT91_REG TWI_IDR;        /* Interrupt Disable Register */
+    AT91_REG TWI_IMR;        /* Interrupt Mask Register */
+    AT91_REG TWI_RHR;        /* Receive Holding Register */
+    AT91_REG TWI_THR;        /* Transmit Holding Register */
+} AT91S_TWI, * AT91PS_TWI;
 
-// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
-#define AT91C_TWI_START       ((unsigned int) 0x1 <<  0) // (TWI) Send a START Condition
-#define AT91C_TWI_STOP        ((unsigned int) 0x1 <<  1) // (TWI) Send a STOP Condition
-#define AT91C_TWI_MSEN        ((unsigned int) 0x1 <<  2) // (TWI) TWI Master Transfer Enabled
-#define AT91C_TWI_MSDIS       ((unsigned int) 0x1 <<  3) // (TWI) TWI Master Transfer Disabled
-#define AT91C_TWI_SWRST       ((unsigned int) 0x1 <<  7) // (TWI) Software Reset
-// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
-#define AT91C_TWI_IADRSZ      ((unsigned int) 0x3 <<  8) // (TWI) Internal Device Address Size
-#define     AT91C_TWI_IADRSZ_NO                   ((unsigned int) 0x0 <<  8) // (TWI) No internal device address
-#define     AT91C_TWI_IADRSZ_1_BYTE               ((unsigned int) 0x1 <<  8) // (TWI) One-byte internal device address
-#define     AT91C_TWI_IADRSZ_2_BYTE               ((unsigned int) 0x2 <<  8) // (TWI) Two-byte internal device address
-#define     AT91C_TWI_IADRSZ_3_BYTE               ((unsigned int) 0x3 <<  8) // (TWI) Three-byte internal device address
-#define AT91C_TWI_MREAD       ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction
-#define AT91C_TWI_DADR        ((unsigned int) 0x7F << 16) // (TWI) Device Address
-// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
-#define AT91C_TWI_CLDIV       ((unsigned int) 0xFF <<  0) // (TWI) Clock Low Divider
-#define AT91C_TWI_CHDIV       ((unsigned int) 0xFF <<  8) // (TWI) Clock High Divider
-#define AT91C_TWI_CKDIV       ((unsigned int) 0x7 << 16) // (TWI) Clock Divider
-// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
-#define AT91C_TWI_TXCOMP      ((unsigned int) 0x1 <<  0) // (TWI) Transmission Completed
-#define AT91C_TWI_RXRDY       ((unsigned int) 0x1 <<  1) // (TWI) Receive holding register ReaDY
-#define AT91C_TWI_TXRDY       ((unsigned int) 0x1 <<  2) // (TWI) Transmit holding register ReaDY
-#define AT91C_TWI_OVRE        ((unsigned int) 0x1 <<  6) // (TWI) Overrun Error
-#define AT91C_TWI_UNRE        ((unsigned int) 0x1 <<  7) // (TWI) Underrun Error
-#define AT91C_TWI_NACK        ((unsigned int) 0x1 <<  8) // (TWI) Not Acknowledged
-// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
-// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
-// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
+/* -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- */
+#define AT91C_TWI_START                ( ( unsigned int ) 0x1 << 0 )   /* (TWI) Send a START Condition */
+#define AT91C_TWI_STOP                 ( ( unsigned int ) 0x1 << 1 )   /* (TWI) Send a STOP Condition */
+#define AT91C_TWI_MSEN                 ( ( unsigned int ) 0x1 << 2 )   /* (TWI) TWI Master Transfer Enabled */
+#define AT91C_TWI_MSDIS                ( ( unsigned int ) 0x1 << 3 )   /* (TWI) TWI Master Transfer Disabled */
+#define AT91C_TWI_SWRST                ( ( unsigned int ) 0x1 << 7 )   /* (TWI) Software Reset */
+/* -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- */
+#define AT91C_TWI_IADRSZ               ( ( unsigned int ) 0x3 << 8 )   /* (TWI) Internal Device Address Size */
+#define     AT91C_TWI_IADRSZ_NO        ( ( unsigned int ) 0x0 << 8 )   /* (TWI) No internal device address */
+#define     AT91C_TWI_IADRSZ_1_BYTE    ( ( unsigned int ) 0x1 << 8 )   /* (TWI) One-byte internal device address */
+#define     AT91C_TWI_IADRSZ_2_BYTE    ( ( unsigned int ) 0x2 << 8 )   /* (TWI) Two-byte internal device address */
+#define     AT91C_TWI_IADRSZ_3_BYTE    ( ( unsigned int ) 0x3 << 8 )   /* (TWI) Three-byte internal device address */
+#define AT91C_TWI_MREAD                ( ( unsigned int ) 0x1 << 12 )  /* (TWI) Master Read Direction */
+#define AT91C_TWI_DADR                 ( ( unsigned int ) 0x7F << 16 ) /* (TWI) Device Address */
+/* -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- */
+#define AT91C_TWI_CLDIV                ( ( unsigned int ) 0xFF << 0 )  /* (TWI) Clock Low Divider */
+#define AT91C_TWI_CHDIV                ( ( unsigned int ) 0xFF << 8 )  /* (TWI) Clock High Divider */
+#define AT91C_TWI_CKDIV                ( ( unsigned int ) 0x7 << 16 )  /* (TWI) Clock Divider */
+/* -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- */
+#define AT91C_TWI_TXCOMP               ( ( unsigned int ) 0x1 << 0 )   /* (TWI) Transmission Completed */
+#define AT91C_TWI_RXRDY                ( ( unsigned int ) 0x1 << 1 )   /* (TWI) Receive holding register ReaDY */
+#define AT91C_TWI_TXRDY                ( ( unsigned int ) 0x1 << 2 )   /* (TWI) Transmit holding register ReaDY */
+#define AT91C_TWI_OVRE                 ( ( unsigned int ) 0x1 << 6 )   /* (TWI) Overrun Error */
+#define AT91C_TWI_UNRE                 ( ( unsigned int ) 0x1 << 7 )   /* (TWI) Underrun Error */
+#define AT91C_TWI_NACK                 ( ( unsigned int ) 0x1 << 8 )   /* (TWI) Not Acknowledged */
+/* -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- */
+/* -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- */
+/* -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR PWMC Channel Interface
-// *****************************************************************************
-typedef struct _AT91S_PWMC_CH {
-    AT91_REG     PWMC_CMR;  // Channel Mode Register
-    AT91_REG     PWMC_CDTYR;    // Channel Duty Cycle Register
-    AT91_REG     PWMC_CPRDR;    // Channel Period Register
-    AT91_REG     PWMC_CCNTR;    // Channel Counter Register
-    AT91_REG     PWMC_CUPDR;    // Channel Update Register
-    AT91_REG     PWMC_Reserved[3];  // Reserved
-} AT91S_PWMC_CH, *AT91PS_PWMC_CH;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR PWMC Channel Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_PWMC_CH
+{
+    AT91_REG PWMC_CMR;           /* Channel Mode Register */
+    AT91_REG PWMC_CDTYR;         /* Channel Duty Cycle Register */
+    AT91_REG PWMC_CPRDR;         /* Channel Period Register */
+    AT91_REG PWMC_CCNTR;         /* Channel Counter Register */
+    AT91_REG PWMC_CUPDR;         /* Channel Update Register */
+    AT91_REG PWMC_Reserved[ 3 ]; /* Reserved */
+} AT91S_PWMC_CH, * AT91PS_PWMC_CH;
 
-// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
-#define AT91C_PWMC_CPRE       ((unsigned int) 0xF <<  0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
-#define     AT91C_PWMC_CPRE_MCK                  ((unsigned int) 0x0) // (PWMC_CH)
-#define     AT91C_PWMC_CPRE_MCKA                 ((unsigned int) 0xB) // (PWMC_CH)
-#define     AT91C_PWMC_CPRE_MCKB                 ((unsigned int) 0xC) // (PWMC_CH)
-#define AT91C_PWMC_CALG       ((unsigned int) 0x1 <<  8) // (PWMC_CH) Channel Alignment
-#define AT91C_PWMC_CPOL       ((unsigned int) 0x1 <<  9) // (PWMC_CH) Channel Polarity
-#define AT91C_PWMC_CPD        ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period
-// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
-#define AT91C_PWMC_CDTY       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Duty Cycle
-// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
-#define AT91C_PWMC_CPRD       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Period
-// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
-#define AT91C_PWMC_CCNT       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Counter
-// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
-#define AT91C_PWMC_CUPD       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Update
+/* -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- */
+#define AT91C_PWMC_CPRE             ( ( unsigned int ) 0xF << 0 )  /* (PWMC_CH) Channel Pre-scaler : PWMC_CLKx */
+#define     AT91C_PWMC_CPRE_MCK     ( ( unsigned int ) 0x0 )       /* (PWMC_CH) */
+#define     AT91C_PWMC_CPRE_MCKA    ( ( unsigned int ) 0xB )       /* (PWMC_CH) */
+#define     AT91C_PWMC_CPRE_MCKB    ( ( unsigned int ) 0xC )       /* (PWMC_CH) */
+#define AT91C_PWMC_CALG             ( ( unsigned int ) 0x1 << 8 )  /* (PWMC_CH) Channel Alignment */
+#define AT91C_PWMC_CPOL             ( ( unsigned int ) 0x1 << 9 )  /* (PWMC_CH) Channel Polarity */
+#define AT91C_PWMC_CPD              ( ( unsigned int ) 0x1 << 10 ) /* (PWMC_CH) Channel Update Period */
+/* -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- */
+#define AT91C_PWMC_CDTY             ( ( unsigned int ) 0x0 << 0 )  /* (PWMC_CH) Channel Duty Cycle */
+/* -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- */
+#define AT91C_PWMC_CPRD             ( ( unsigned int ) 0x0 << 0 )  /* (PWMC_CH) Channel Period */
+/* -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- */
+#define AT91C_PWMC_CCNT             ( ( unsigned int ) 0x0 << 0 )  /* (PWMC_CH) Channel Counter */
+/* -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- */
+#define AT91C_PWMC_CUPD             ( ( unsigned int ) 0x0 << 0 )  /* (PWMC_CH) Channel Update */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_PWMC {
-    AT91_REG     PWMC_MR;   // PWMC Mode Register
-    AT91_REG     PWMC_ENA;  // PWMC Enable Register
-    AT91_REG     PWMC_DIS;  // PWMC Disable Register
-    AT91_REG     PWMC_SR;   // PWMC Status Register
-    AT91_REG     PWMC_IER;  // PWMC Interrupt Enable Register
-    AT91_REG     PWMC_IDR;  // PWMC Interrupt Disable Register
-    AT91_REG     PWMC_IMR;  // PWMC Interrupt Mask Register
-    AT91_REG     PWMC_ISR;  // PWMC Interrupt Status Register
-    AT91_REG     Reserved0[55];     //
-    AT91_REG     PWMC_VR;   // PWMC Version Register
-    AT91_REG     Reserved1[64];     //
-    AT91S_PWMC_CH    PWMC_CH[4];    // PWMC Channel
-} AT91S_PWMC, *AT91PS_PWMC;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_PWMC
+{
+    AT91_REG PWMC_MR;           /* PWMC Mode Register */
+    AT91_REG PWMC_ENA;          /* PWMC Enable Register */
+    AT91_REG PWMC_DIS;          /* PWMC Disable Register */
+    AT91_REG PWMC_SR;           /* PWMC Status Register */
+    AT91_REG PWMC_IER;          /* PWMC Interrupt Enable Register */
+    AT91_REG PWMC_IDR;          /* PWMC Interrupt Disable Register */
+    AT91_REG PWMC_IMR;          /* PWMC Interrupt Mask Register */
+    AT91_REG PWMC_ISR;          /* PWMC Interrupt Status Register */
+    AT91_REG Reserved0[ 55 ];   /* */
+    AT91_REG PWMC_VR;           /* PWMC Version Register */
+    AT91_REG Reserved1[ 64 ];   /* */
+    AT91S_PWMC_CH PWMC_CH[ 4 ]; /* PWMC Channel */
+} AT91S_PWMC, * AT91PS_PWMC;
 
-// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
-#define AT91C_PWMC_DIVA       ((unsigned int) 0xFF <<  0) // (PWMC) CLKA divide factor.
-#define AT91C_PWMC_PREA       ((unsigned int) 0xF <<  8) // (PWMC) Divider Input Clock Prescaler A
-#define     AT91C_PWMC_PREA_MCK                  ((unsigned int) 0x0 <<  8) // (PWMC)
-#define AT91C_PWMC_DIVB       ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor.
-#define AT91C_PWMC_PREB       ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B
-#define     AT91C_PWMC_PREB_MCK                  ((unsigned int) 0x0 << 24) // (PWMC)
-// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
-#define AT91C_PWMC_CHID0      ((unsigned int) 0x1 <<  0) // (PWMC) Channel ID 0
-#define AT91C_PWMC_CHID1      ((unsigned int) 0x1 <<  1) // (PWMC) Channel ID 1
-#define AT91C_PWMC_CHID2      ((unsigned int) 0x1 <<  2) // (PWMC) Channel ID 2
-#define AT91C_PWMC_CHID3      ((unsigned int) 0x1 <<  3) // (PWMC) Channel ID 3
-// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
-// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
-// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
-// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
-// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
-// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
+/* -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- */
+#define AT91C_PWMC_DIVA            ( ( unsigned int ) 0xFF << 0 )  /* (PWMC) CLKA divide factor. */
+#define AT91C_PWMC_PREA            ( ( unsigned int ) 0xF << 8 )   /* (PWMC) Divider Input Clock Prescaler A */
+#define     AT91C_PWMC_PREA_MCK    ( ( unsigned int ) 0x0 << 8 )   /* (PWMC) */
+#define AT91C_PWMC_DIVB            ( ( unsigned int ) 0xFF << 16 ) /* (PWMC) CLKB divide factor. */
+#define AT91C_PWMC_PREB            ( ( unsigned int ) 0xF << 24 )  /* (PWMC) Divider Input Clock Prescaler B */
+#define     AT91C_PWMC_PREB_MCK    ( ( unsigned int ) 0x0 << 24 )  /* (PWMC) */
+/* -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- */
+#define AT91C_PWMC_CHID0           ( ( unsigned int ) 0x1 << 0 )   /* (PWMC) Channel ID 0 */
+#define AT91C_PWMC_CHID1           ( ( unsigned int ) 0x1 << 1 )   /* (PWMC) Channel ID 1 */
+#define AT91C_PWMC_CHID2           ( ( unsigned int ) 0x1 << 2 )   /* (PWMC) Channel ID 2 */
+#define AT91C_PWMC_CHID3           ( ( unsigned int ) 0x1 << 3 )   /* (PWMC) Channel ID 3 */
+/* -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- */
+/* -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- */
+/* -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- */
+/* -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- */
+/* -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- */
+/* -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR USB Device Interface
-// *****************************************************************************
-typedef struct _AT91S_UDP {
-    AT91_REG     UDP_NUM;   // Frame Number Register
-    AT91_REG     UDP_GLBSTATE;  // Global State Register
-    AT91_REG     UDP_FADDR;     // Function Address Register
-    AT91_REG     Reserved0[1];  //
-    AT91_REG     UDP_IER;   // Interrupt Enable Register
-    AT91_REG     UDP_IDR;   // Interrupt Disable Register
-    AT91_REG     UDP_IMR;   // Interrupt Mask Register
-    AT91_REG     UDP_ISR;   // Interrupt Status Register
-    AT91_REG     UDP_ICR;   // Interrupt Clear Register
-    AT91_REG     Reserved1[1];  //
-    AT91_REG     UDP_RSTEP;     // Reset Endpoint Register
-    AT91_REG     Reserved2[1];  //
-    AT91_REG     UDP_CSR[6];    // Endpoint Control and Status Register
-    AT91_REG     Reserved3[2];  //
-    AT91_REG     UDP_FDR[6];    // Endpoint FIFO Data Register
-    AT91_REG     Reserved4[3];  //
-    AT91_REG     UDP_TXVC;  // Transceiver Control Register
-} AT91S_UDP, *AT91PS_UDP;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR USB Device Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_UDP
+{
+    AT91_REG UDP_NUM;        /* Frame Number Register */
+    AT91_REG UDP_GLBSTATE;   /* Global State Register */
+    AT91_REG UDP_FADDR;      /* Function Address Register */
+    AT91_REG Reserved0[ 1 ]; /* */
+    AT91_REG UDP_IER;        /* Interrupt Enable Register */
+    AT91_REG UDP_IDR;        /* Interrupt Disable Register */
+    AT91_REG UDP_IMR;        /* Interrupt Mask Register */
+    AT91_REG UDP_ISR;        /* Interrupt Status Register */
+    AT91_REG UDP_ICR;        /* Interrupt Clear Register */
+    AT91_REG Reserved1[ 1 ]; /* */
+    AT91_REG UDP_RSTEP;      /* Reset Endpoint Register */
+    AT91_REG Reserved2[ 1 ]; /* */
+    AT91_REG UDP_CSR[ 6 ];   /* Endpoint Control and Status Register */
+    AT91_REG Reserved3[ 2 ]; /* */
+    AT91_REG UDP_FDR[ 6 ];   /* Endpoint FIFO Data Register */
+    AT91_REG Reserved4[ 3 ]; /* */
+    AT91_REG UDP_TXVC;       /* Transceiver Control Register */
+} AT91S_UDP, * AT91PS_UDP;
 
-// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
-#define AT91C_UDP_FRM_NUM     ((unsigned int) 0x7FF <<  0) // (UDP) Frame Number as Defined in the Packet Field Formats
-#define AT91C_UDP_FRM_ERR     ((unsigned int) 0x1 << 16) // (UDP) Frame Error
-#define AT91C_UDP_FRM_OK      ((unsigned int) 0x1 << 17) // (UDP) Frame OK
-// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
-#define AT91C_UDP_FADDEN      ((unsigned int) 0x1 <<  0) // (UDP) Function Address Enable
-#define AT91C_UDP_CONFG       ((unsigned int) 0x1 <<  1) // (UDP) Configured
-#define AT91C_UDP_ESR         ((unsigned int) 0x1 <<  2) // (UDP) Enable Send Resume
-#define AT91C_UDP_RSMINPR     ((unsigned int) 0x1 <<  3) // (UDP) A Resume Has Been Sent to the Host
-#define AT91C_UDP_RMWUPE      ((unsigned int) 0x1 <<  4) // (UDP) Remote Wake Up Enable
-// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
-#define AT91C_UDP_FADD        ((unsigned int) 0xFF <<  0) // (UDP) Function Address Value
-#define AT91C_UDP_FEN         ((unsigned int) 0x1 <<  8) // (UDP) Function Enable
-// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
-#define AT91C_UDP_EPINT0      ((unsigned int) 0x1 <<  0) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT1      ((unsigned int) 0x1 <<  1) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT2      ((unsigned int) 0x1 <<  2) // (UDP) Endpoint 2 Interrupt
-#define AT91C_UDP_EPINT3      ((unsigned int) 0x1 <<  3) // (UDP) Endpoint 3 Interrupt
-#define AT91C_UDP_EPINT4      ((unsigned int) 0x1 <<  4) // (UDP) Endpoint 4 Interrupt
-#define AT91C_UDP_EPINT5      ((unsigned int) 0x1 <<  5) // (UDP) Endpoint 5 Interrupt
-#define AT91C_UDP_RXSUSP      ((unsigned int) 0x1 <<  8) // (UDP) USB Suspend Interrupt
-#define AT91C_UDP_RXRSM       ((unsigned int) 0x1 <<  9) // (UDP) USB Resume Interrupt
-#define AT91C_UDP_EXTRSM      ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt
-#define AT91C_UDP_SOFINT      ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt
-#define AT91C_UDP_WAKEUP      ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt
-// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
-// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
-// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
-#define AT91C_UDP_ENDBUSRES   ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
-// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
-// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
-#define AT91C_UDP_EP0         ((unsigned int) 0x1 <<  0) // (UDP) Reset Endpoint 0
-#define AT91C_UDP_EP1         ((unsigned int) 0x1 <<  1) // (UDP) Reset Endpoint 1
-#define AT91C_UDP_EP2         ((unsigned int) 0x1 <<  2) // (UDP) Reset Endpoint 2
-#define AT91C_UDP_EP3         ((unsigned int) 0x1 <<  3) // (UDP) Reset Endpoint 3
-#define AT91C_UDP_EP4         ((unsigned int) 0x1 <<  4) // (UDP) Reset Endpoint 4
-#define AT91C_UDP_EP5         ((unsigned int) 0x1 <<  5) // (UDP) Reset Endpoint 5
-// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
-#define AT91C_UDP_TXCOMP      ((unsigned int) 0x1 <<  0) // (UDP) Generates an IN packet with data previously written in the DPR
-#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 <<  1) // (UDP) Receive Data Bank 0
-#define AT91C_UDP_RXSETUP     ((unsigned int) 0x1 <<  2) // (UDP) Sends STALL to the Host (Control endpoints)
-#define AT91C_UDP_ISOERROR    ((unsigned int) 0x1 <<  3) // (UDP) Isochronous error (Isochronous endpoints)
-#define AT91C_UDP_TXPKTRDY    ((unsigned int) 0x1 <<  4) // (UDP) Transmit Packet Ready
-#define AT91C_UDP_FORCESTALL  ((unsigned int) 0x1 <<  5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
-#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 <<  6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
-#define AT91C_UDP_DIR         ((unsigned int) 0x1 <<  7) // (UDP) Transfer Direction
-#define AT91C_UDP_EPTYPE      ((unsigned int) 0x7 <<  8) // (UDP) Endpoint type
-#define     AT91C_UDP_EPTYPE_CTRL                 ((unsigned int) 0x0 <<  8) // (UDP) Control
-#define     AT91C_UDP_EPTYPE_ISO_OUT              ((unsigned int) 0x1 <<  8) // (UDP) Isochronous OUT
-#define     AT91C_UDP_EPTYPE_BULK_OUT             ((unsigned int) 0x2 <<  8) // (UDP) Bulk OUT
-#define     AT91C_UDP_EPTYPE_INT_OUT              ((unsigned int) 0x3 <<  8) // (UDP) Interrupt OUT
-#define     AT91C_UDP_EPTYPE_ISO_IN               ((unsigned int) 0x5 <<  8) // (UDP) Isochronous IN
-#define     AT91C_UDP_EPTYPE_BULK_IN              ((unsigned int) 0x6 <<  8) // (UDP) Bulk IN
-#define     AT91C_UDP_EPTYPE_INT_IN               ((unsigned int) 0x7 <<  8) // (UDP) Interrupt IN
-#define AT91C_UDP_DTGLE       ((unsigned int) 0x1 << 11) // (UDP) Data Toggle
-#define AT91C_UDP_EPEDS       ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable
-#define AT91C_UDP_RXBYTECNT   ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
-// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------
-#define AT91C_UDP_TXVDIS      ((unsigned int) 0x1 <<  8) // (UDP)
-#define AT91C_UDP_PUON        ((unsigned int) 0x1 <<  9) // (UDP) Pull-up ON
+/* -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- */
+#define AT91C_UDP_FRM_NUM    ( ( unsigned int ) 0x7FF << 0 ) /* (UDP) Frame Number as Defined in the Packet Field Formats */
+#define AT91C_UDP_FRM_ERR    ( ( unsigned int ) 0x1 << 16 )  /* (UDP) Frame Error */
+#define AT91C_UDP_FRM_OK     ( ( unsigned int ) 0x1 << 17 )  /* (UDP) Frame OK */
+/* -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- */
+#define AT91C_UDP_FADDEN     ( ( unsigned int ) 0x1 << 0 )   /* (UDP) Function Address Enable */
+#define AT91C_UDP_CONFG      ( ( unsigned int ) 0x1 << 1 )   /* (UDP) Configured */
+#define AT91C_UDP_ESR        ( ( unsigned int ) 0x1 << 2 )   /* (UDP) Enable Send Resume */
+#define AT91C_UDP_RSMINPR    ( ( unsigned int ) 0x1 << 3 )   /* (UDP) A Resume Has Been Sent to the Host */
+#define AT91C_UDP_RMWUPE     ( ( unsigned int ) 0x1 << 4 )   /* (UDP) Remote Wake Up Enable */
+/* -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- */
+#define AT91C_UDP_FADD       ( ( unsigned int ) 0xFF << 0 )  /* (UDP) Function Address Value */
+#define AT91C_UDP_FEN        ( ( unsigned int ) 0x1 << 8 )   /* (UDP) Function Enable */
+/* -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- */
+#define AT91C_UDP_EPINT0     ( ( unsigned int ) 0x1 << 0 )   /* (UDP) Endpoint 0 Interrupt */
+#define AT91C_UDP_EPINT1     ( ( unsigned int ) 0x1 << 1 )   /* (UDP) Endpoint 0 Interrupt */
+#define AT91C_UDP_EPINT2     ( ( unsigned int ) 0x1 << 2 )   /* (UDP) Endpoint 2 Interrupt */
+#define AT91C_UDP_EPINT3     ( ( unsigned int ) 0x1 << 3 )   /* (UDP) Endpoint 3 Interrupt */
+#define AT91C_UDP_EPINT4     ( ( unsigned int ) 0x1 << 4 )   /* (UDP) Endpoint 4 Interrupt */
+#define AT91C_UDP_EPINT5     ( ( unsigned int ) 0x1 << 5 )   /* (UDP) Endpoint 5 Interrupt */
+#define AT91C_UDP_RXSUSP     ( ( unsigned int ) 0x1 << 8 )   /* (UDP) USB Suspend Interrupt */
+#define AT91C_UDP_RXRSM      ( ( unsigned int ) 0x1 << 9 )   /* (UDP) USB Resume Interrupt */
+#define AT91C_UDP_EXTRSM     ( ( unsigned int ) 0x1 << 10 )  /* (UDP) USB External Resume Interrupt */
+#define AT91C_UDP_SOFINT     ( ( unsigned int ) 0x1 << 11 )  /* (UDP) USB Start Of frame Interrupt */
+#define AT91C_UDP_WAKEUP     ( ( unsigned int ) 0x1 << 13 )  /* (UDP) USB Resume Interrupt */
+/* -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- */
+/* -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- */
+/* -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- */
+#define AT91C_UDP_ENDBUSRES              ( ( unsigned int ) 0x1 << 12 ) /* (UDP) USB End Of Bus Reset Interrupt */
+/* -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- */
+/* -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- */
+#define AT91C_UDP_EP0                    ( ( unsigned int ) 0x1 << 0 )    /* (UDP) Reset Endpoint 0 */
+#define AT91C_UDP_EP1                    ( ( unsigned int ) 0x1 << 1 )    /* (UDP) Reset Endpoint 1 */
+#define AT91C_UDP_EP2                    ( ( unsigned int ) 0x1 << 2 )    /* (UDP) Reset Endpoint 2 */
+#define AT91C_UDP_EP3                    ( ( unsigned int ) 0x1 << 3 )    /* (UDP) Reset Endpoint 3 */
+#define AT91C_UDP_EP4                    ( ( unsigned int ) 0x1 << 4 )    /* (UDP) Reset Endpoint 4 */
+#define AT91C_UDP_EP5                    ( ( unsigned int ) 0x1 << 5 )    /* (UDP) Reset Endpoint 5 */
+/* -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- */
+#define AT91C_UDP_TXCOMP                 ( ( unsigned int ) 0x1 << 0 )    /* (UDP) Generates an IN packet with data previously written in the DPR */
+#define AT91C_UDP_RX_DATA_BK0            ( ( unsigned int ) 0x1 << 1 )    /* (UDP) Receive Data Bank 0 */
+#define AT91C_UDP_RXSETUP                ( ( unsigned int ) 0x1 << 2 )    /* (UDP) Sends STALL to the Host (Control endpoints) */
+#define AT91C_UDP_ISOERROR               ( ( unsigned int ) 0x1 << 3 )    /* (UDP) Isochronous error (Isochronous endpoints) */
+#define AT91C_UDP_TXPKTRDY               ( ( unsigned int ) 0x1 << 4 )    /* (UDP) Transmit Packet Ready */
+#define AT91C_UDP_FORCESTALL             ( ( unsigned int ) 0x1 << 5 )    /* (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). */
+#define AT91C_UDP_RX_DATA_BK1            ( ( unsigned int ) 0x1 << 6 )    /* (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). */
+#define AT91C_UDP_DIR                    ( ( unsigned int ) 0x1 << 7 )    /* (UDP) Transfer Direction */
+#define AT91C_UDP_EPTYPE                 ( ( unsigned int ) 0x7 << 8 )    /* (UDP) Endpoint type */
+#define     AT91C_UDP_EPTYPE_CTRL        ( ( unsigned int ) 0x0 << 8 )    /* (UDP) Control */
+#define     AT91C_UDP_EPTYPE_ISO_OUT     ( ( unsigned int ) 0x1 << 8 )    /* (UDP) Isochronous OUT */
+#define     AT91C_UDP_EPTYPE_BULK_OUT    ( ( unsigned int ) 0x2 << 8 )    /* (UDP) Bulk OUT */
+#define     AT91C_UDP_EPTYPE_INT_OUT     ( ( unsigned int ) 0x3 << 8 )    /* (UDP) Interrupt OUT */
+#define     AT91C_UDP_EPTYPE_ISO_IN      ( ( unsigned int ) 0x5 << 8 )    /* (UDP) Isochronous IN */
+#define     AT91C_UDP_EPTYPE_BULK_IN     ( ( unsigned int ) 0x6 << 8 )    /* (UDP) Bulk IN */
+#define     AT91C_UDP_EPTYPE_INT_IN      ( ( unsigned int ) 0x7 << 8 )    /* (UDP) Interrupt IN */
+#define AT91C_UDP_DTGLE                  ( ( unsigned int ) 0x1 << 11 )   /* (UDP) Data Toggle */
+#define AT91C_UDP_EPEDS                  ( ( unsigned int ) 0x1 << 15 )   /* (UDP) Endpoint Enable Disable */
+#define AT91C_UDP_RXBYTECNT              ( ( unsigned int ) 0x7FF << 16 ) /* (UDP) Number Of Bytes Available in the FIFO */
+/* -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- */
+#define AT91C_UDP_TXVDIS                 ( ( unsigned int ) 0x1 << 8 )    /* (UDP) */
+#define AT91C_UDP_PUON                   ( ( unsigned int ) 0x1 << 9 )    /* (UDP) Pull-up ON */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
-// *****************************************************************************
-typedef struct _AT91S_TC {
-    AT91_REG     TC_CCR;    // Channel Control Register
-    AT91_REG     TC_CMR;    // Channel Mode Register (Capture Mode / Waveform Mode)
-    AT91_REG     Reserved0[2];  //
-    AT91_REG     TC_CV;     // Counter Value
-    AT91_REG     TC_RA;     // Register A
-    AT91_REG     TC_RB;     // Register B
-    AT91_REG     TC_RC;     // Register C
-    AT91_REG     TC_SR;     // Status Register
-    AT91_REG     TC_IER;    // Interrupt Enable Register
-    AT91_REG     TC_IDR;    // Interrupt Disable Register
-    AT91_REG     TC_IMR;    // Interrupt Mask Register
-} AT91S_TC, *AT91PS_TC;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_TC
+{
+    AT91_REG TC_CCR;         /* Channel Control Register */
+    AT91_REG TC_CMR;         /* Channel Mode Register (Capture Mode / Waveform Mode) */
+    AT91_REG Reserved0[ 2 ]; /* */
+    AT91_REG TC_CV;          /* Counter Value */
+    AT91_REG TC_RA;          /* Register A */
+    AT91_REG TC_RB;          /* Register B */
+    AT91_REG TC_RC;          /* Register C */
+    AT91_REG TC_SR;          /* Status Register */
+    AT91_REG TC_IER;         /* Interrupt Enable Register */
+    AT91_REG TC_IDR;         /* Interrupt Disable Register */
+    AT91_REG TC_IMR;         /* Interrupt Mask Register */
+} AT91S_TC, * AT91PS_TC;
 
-// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
-#define AT91C_TC_CLKEN        ((unsigned int) 0x1 <<  0) // (TC) Counter Clock Enable Command
-#define AT91C_TC_CLKDIS       ((unsigned int) 0x1 <<  1) // (TC) Counter Clock Disable Command
-#define AT91C_TC_SWTRG        ((unsigned int) 0x1 <<  2) // (TC) Software Trigger Command
-// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
-#define AT91C_TC_CLKS         ((unsigned int) 0x7 <<  0) // (TC) Clock Selection
-#define     AT91C_TC_CLKS_TIMER_DIV1_CLOCK     ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
-#define     AT91C_TC_CLKS_TIMER_DIV2_CLOCK     ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
-#define     AT91C_TC_CLKS_TIMER_DIV3_CLOCK     ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
-#define     AT91C_TC_CLKS_TIMER_DIV4_CLOCK     ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
-#define     AT91C_TC_CLKS_TIMER_DIV5_CLOCK     ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
-#define     AT91C_TC_CLKS_XC0                  ((unsigned int) 0x5) // (TC) Clock selected: XC0
-#define     AT91C_TC_CLKS_XC1                  ((unsigned int) 0x6) // (TC) Clock selected: XC1
-#define     AT91C_TC_CLKS_XC2                  ((unsigned int) 0x7) // (TC) Clock selected: XC2
-#define AT91C_TC_CLKI         ((unsigned int) 0x1 <<  3) // (TC) Clock Invert
-#define AT91C_TC_BURST        ((unsigned int) 0x3 <<  4) // (TC) Burst Signal Selection
-#define     AT91C_TC_BURST_NONE                 ((unsigned int) 0x0 <<  4) // (TC) The clock is not gated by an external signal
-#define     AT91C_TC_BURST_XC0                  ((unsigned int) 0x1 <<  4) // (TC) XC0 is ANDed with the selected clock
-#define     AT91C_TC_BURST_XC1                  ((unsigned int) 0x2 <<  4) // (TC) XC1 is ANDed with the selected clock
-#define     AT91C_TC_BURST_XC2                  ((unsigned int) 0x3 <<  4) // (TC) XC2 is ANDed with the selected clock
-#define AT91C_TC_CPCSTOP      ((unsigned int) 0x1 <<  6) // (TC) Counter Clock Stopped with RC Compare
-#define AT91C_TC_LDBSTOP      ((unsigned int) 0x1 <<  6) // (TC) Counter Clock Stopped with RB Loading
-#define AT91C_TC_CPCDIS       ((unsigned int) 0x1 <<  7) // (TC) Counter Clock Disable with RC Compare
-#define AT91C_TC_LDBDIS       ((unsigned int) 0x1 <<  7) // (TC) Counter Clock Disabled with RB Loading
-#define AT91C_TC_ETRGEDG      ((unsigned int) 0x3 <<  8) // (TC) External Trigger Edge Selection
-#define     AT91C_TC_ETRGEDG_NONE                 ((unsigned int) 0x0 <<  8) // (TC) Edge: None
-#define     AT91C_TC_ETRGEDG_RISING               ((unsigned int) 0x1 <<  8) // (TC) Edge: rising edge
-#define     AT91C_TC_ETRGEDG_FALLING              ((unsigned int) 0x2 <<  8) // (TC) Edge: falling edge
-#define     AT91C_TC_ETRGEDG_BOTH                 ((unsigned int) 0x3 <<  8) // (TC) Edge: each edge
-#define AT91C_TC_EEVTEDG      ((unsigned int) 0x3 <<  8) // (TC) External Event Edge Selection
-#define     AT91C_TC_EEVTEDG_NONE                 ((unsigned int) 0x0 <<  8) // (TC) Edge: None
-#define     AT91C_TC_EEVTEDG_RISING               ((unsigned int) 0x1 <<  8) // (TC) Edge: rising edge
-#define     AT91C_TC_EEVTEDG_FALLING              ((unsigned int) 0x2 <<  8) // (TC) Edge: falling edge
-#define     AT91C_TC_EEVTEDG_BOTH                 ((unsigned int) 0x3 <<  8) // (TC) Edge: each edge
-#define AT91C_TC_EEVT         ((unsigned int) 0x3 << 10) // (TC) External Event  Selection
-#define     AT91C_TC_EEVT_TIOB                 ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
-#define     AT91C_TC_EEVT_XC0                  ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
-#define     AT91C_TC_EEVT_XC1                  ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
-#define     AT91C_TC_EEVT_XC2                  ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
-#define AT91C_TC_ABETRG       ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
-#define AT91C_TC_ENETRG       ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable
-#define AT91C_TC_WAVESEL      ((unsigned int) 0x3 << 13) // (TC) Waveform  Selection
-#define     AT91C_TC_WAVESEL_UP                   ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
-#define     AT91C_TC_WAVESEL_UPDOWN               ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
-#define     AT91C_TC_WAVESEL_UP_AUTO              ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
-#define     AT91C_TC_WAVESEL_UPDOWN_AUTO          ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
-#define AT91C_TC_CPCTRG       ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable
-#define AT91C_TC_WAVE         ((unsigned int) 0x1 << 15) // (TC)
-#define AT91C_TC_ACPA         ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA
-#define     AT91C_TC_ACPA_NONE                 ((unsigned int) 0x0 << 16) // (TC) Effect: none
-#define     AT91C_TC_ACPA_SET                  ((unsigned int) 0x1 << 16) // (TC) Effect: set
-#define     AT91C_TC_ACPA_CLEAR                ((unsigned int) 0x2 << 16) // (TC) Effect: clear
-#define     AT91C_TC_ACPA_TOGGLE               ((unsigned int) 0x3 << 16) // (TC) Effect: toggle
-#define AT91C_TC_LDRA         ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection
-#define     AT91C_TC_LDRA_NONE                 ((unsigned int) 0x0 << 16) // (TC) Edge: None
-#define     AT91C_TC_LDRA_RISING               ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA
-#define     AT91C_TC_LDRA_FALLING              ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA
-#define     AT91C_TC_LDRA_BOTH                 ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_ACPC         ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA
-#define     AT91C_TC_ACPC_NONE                 ((unsigned int) 0x0 << 18) // (TC) Effect: none
-#define     AT91C_TC_ACPC_SET                  ((unsigned int) 0x1 << 18) // (TC) Effect: set
-#define     AT91C_TC_ACPC_CLEAR                ((unsigned int) 0x2 << 18) // (TC) Effect: clear
-#define     AT91C_TC_ACPC_TOGGLE               ((unsigned int) 0x3 << 18) // (TC) Effect: toggle
-#define AT91C_TC_LDRB         ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection
-#define     AT91C_TC_LDRB_NONE                 ((unsigned int) 0x0 << 18) // (TC) Edge: None
-#define     AT91C_TC_LDRB_RISING               ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA
-#define     AT91C_TC_LDRB_FALLING              ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA
-#define     AT91C_TC_LDRB_BOTH                 ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_AEEVT        ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA
-#define     AT91C_TC_AEEVT_NONE                 ((unsigned int) 0x0 << 20) // (TC) Effect: none
-#define     AT91C_TC_AEEVT_SET                  ((unsigned int) 0x1 << 20) // (TC) Effect: set
-#define     AT91C_TC_AEEVT_CLEAR                ((unsigned int) 0x2 << 20) // (TC) Effect: clear
-#define     AT91C_TC_AEEVT_TOGGLE               ((unsigned int) 0x3 << 20) // (TC) Effect: toggle
-#define AT91C_TC_ASWTRG       ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA
-#define     AT91C_TC_ASWTRG_NONE                 ((unsigned int) 0x0 << 22) // (TC) Effect: none
-#define     AT91C_TC_ASWTRG_SET                  ((unsigned int) 0x1 << 22) // (TC) Effect: set
-#define     AT91C_TC_ASWTRG_CLEAR                ((unsigned int) 0x2 << 22) // (TC) Effect: clear
-#define     AT91C_TC_ASWTRG_TOGGLE               ((unsigned int) 0x3 << 22) // (TC) Effect: toggle
-#define AT91C_TC_BCPB         ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB
-#define     AT91C_TC_BCPB_NONE                 ((unsigned int) 0x0 << 24) // (TC) Effect: none
-#define     AT91C_TC_BCPB_SET                  ((unsigned int) 0x1 << 24) // (TC) Effect: set
-#define     AT91C_TC_BCPB_CLEAR                ((unsigned int) 0x2 << 24) // (TC) Effect: clear
-#define     AT91C_TC_BCPB_TOGGLE               ((unsigned int) 0x3 << 24) // (TC) Effect: toggle
-#define AT91C_TC_BCPC         ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB
-#define     AT91C_TC_BCPC_NONE                 ((unsigned int) 0x0 << 26) // (TC) Effect: none
-#define     AT91C_TC_BCPC_SET                  ((unsigned int) 0x1 << 26) // (TC) Effect: set
-#define     AT91C_TC_BCPC_CLEAR                ((unsigned int) 0x2 << 26) // (TC) Effect: clear
-#define     AT91C_TC_BCPC_TOGGLE               ((unsigned int) 0x3 << 26) // (TC) Effect: toggle
-#define AT91C_TC_BEEVT        ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB
-#define     AT91C_TC_BEEVT_NONE                 ((unsigned int) 0x0 << 28) // (TC) Effect: none
-#define     AT91C_TC_BEEVT_SET                  ((unsigned int) 0x1 << 28) // (TC) Effect: set
-#define     AT91C_TC_BEEVT_CLEAR                ((unsigned int) 0x2 << 28) // (TC) Effect: clear
-#define     AT91C_TC_BEEVT_TOGGLE               ((unsigned int) 0x3 << 28) // (TC) Effect: toggle
-#define AT91C_TC_BSWTRG       ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB
-#define     AT91C_TC_BSWTRG_NONE                 ((unsigned int) 0x0 << 30) // (TC) Effect: none
-#define     AT91C_TC_BSWTRG_SET                  ((unsigned int) 0x1 << 30) // (TC) Effect: set
-#define     AT91C_TC_BSWTRG_CLEAR                ((unsigned int) 0x2 << 30) // (TC) Effect: clear
-#define     AT91C_TC_BSWTRG_TOGGLE               ((unsigned int) 0x3 << 30) // (TC) Effect: toggle
-// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
-#define AT91C_TC_COVFS        ((unsigned int) 0x1 <<  0) // (TC) Counter Overflow
-#define AT91C_TC_LOVRS        ((unsigned int) 0x1 <<  1) // (TC) Load Overrun
-#define AT91C_TC_CPAS         ((unsigned int) 0x1 <<  2) // (TC) RA Compare
-#define AT91C_TC_CPBS         ((unsigned int) 0x1 <<  3) // (TC) RB Compare
-#define AT91C_TC_CPCS         ((unsigned int) 0x1 <<  4) // (TC) RC Compare
-#define AT91C_TC_LDRAS        ((unsigned int) 0x1 <<  5) // (TC) RA Loading
-#define AT91C_TC_LDRBS        ((unsigned int) 0x1 <<  6) // (TC) RB Loading
-#define AT91C_TC_ETRGS        ((unsigned int) 0x1 <<  7) // (TC) External Trigger
-#define AT91C_TC_CLKSTA       ((unsigned int) 0x1 << 16) // (TC) Clock Enabling
-#define AT91C_TC_MTIOA        ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror
-#define AT91C_TC_MTIOB        ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror
-// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
-// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
-// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
+/* -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- */
+#define AT91C_TC_CLKEN                        ( ( unsigned int ) 0x1 << 0 )  /* (TC) Counter Clock Enable Command */
+#define AT91C_TC_CLKDIS                       ( ( unsigned int ) 0x1 << 1 )  /* (TC) Counter Clock Disable Command */
+#define AT91C_TC_SWTRG                        ( ( unsigned int ) 0x1 << 2 )  /* (TC) Software Trigger Command */
+/* -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- */
+#define AT91C_TC_CLKS                         ( ( unsigned int ) 0x7 << 0 )  /* (TC) Clock Selection */
+#define     AT91C_TC_CLKS_TIMER_DIV1_CLOCK    ( ( unsigned int ) 0x0 )       /* (TC) Clock selected: TIMER_DIV1_CLOCK */
+#define     AT91C_TC_CLKS_TIMER_DIV2_CLOCK    ( ( unsigned int ) 0x1 )       /* (TC) Clock selected: TIMER_DIV2_CLOCK */
+#define     AT91C_TC_CLKS_TIMER_DIV3_CLOCK    ( ( unsigned int ) 0x2 )       /* (TC) Clock selected: TIMER_DIV3_CLOCK */
+#define     AT91C_TC_CLKS_TIMER_DIV4_CLOCK    ( ( unsigned int ) 0x3 )       /* (TC) Clock selected: TIMER_DIV4_CLOCK */
+#define     AT91C_TC_CLKS_TIMER_DIV5_CLOCK    ( ( unsigned int ) 0x4 )       /* (TC) Clock selected: TIMER_DIV5_CLOCK */
+#define     AT91C_TC_CLKS_XC0                 ( ( unsigned int ) 0x5 )       /* (TC) Clock selected: XC0 */
+#define     AT91C_TC_CLKS_XC1                 ( ( unsigned int ) 0x6 )       /* (TC) Clock selected: XC1 */
+#define     AT91C_TC_CLKS_XC2                 ( ( unsigned int ) 0x7 )       /* (TC) Clock selected: XC2 */
+#define AT91C_TC_CLKI                         ( ( unsigned int ) 0x1 << 3 )  /* (TC) Clock Invert */
+#define AT91C_TC_BURST                        ( ( unsigned int ) 0x3 << 4 )  /* (TC) Burst Signal Selection */
+#define     AT91C_TC_BURST_NONE               ( ( unsigned int ) 0x0 << 4 )  /* (TC) The clock is not gated by an external signal */
+#define     AT91C_TC_BURST_XC0                ( ( unsigned int ) 0x1 << 4 )  /* (TC) XC0 is ANDed with the selected clock */
+#define     AT91C_TC_BURST_XC1                ( ( unsigned int ) 0x2 << 4 )  /* (TC) XC1 is ANDed with the selected clock */
+#define     AT91C_TC_BURST_XC2                ( ( unsigned int ) 0x3 << 4 )  /* (TC) XC2 is ANDed with the selected clock */
+#define AT91C_TC_CPCSTOP                      ( ( unsigned int ) 0x1 << 6 )  /* (TC) Counter Clock Stopped with RC Compare */
+#define AT91C_TC_LDBSTOP                      ( ( unsigned int ) 0x1 << 6 )  /* (TC) Counter Clock Stopped with RB Loading */
+#define AT91C_TC_CPCDIS                       ( ( unsigned int ) 0x1 << 7 )  /* (TC) Counter Clock Disable with RC Compare */
+#define AT91C_TC_LDBDIS                       ( ( unsigned int ) 0x1 << 7 )  /* (TC) Counter Clock Disabled with RB Loading */
+#define AT91C_TC_ETRGEDG                      ( ( unsigned int ) 0x3 << 8 )  /* (TC) External Trigger Edge Selection */
+#define     AT91C_TC_ETRGEDG_NONE             ( ( unsigned int ) 0x0 << 8 )  /* (TC) Edge: None */
+#define     AT91C_TC_ETRGEDG_RISING           ( ( unsigned int ) 0x1 << 8 )  /* (TC) Edge: rising edge */
+#define     AT91C_TC_ETRGEDG_FALLING          ( ( unsigned int ) 0x2 << 8 )  /* (TC) Edge: falling edge */
+#define     AT91C_TC_ETRGEDG_BOTH             ( ( unsigned int ) 0x3 << 8 )  /* (TC) Edge: each edge */
+#define AT91C_TC_EEVTEDG                      ( ( unsigned int ) 0x3 << 8 )  /* (TC) External Event Edge Selection */
+#define     AT91C_TC_EEVTEDG_NONE             ( ( unsigned int ) 0x0 << 8 )  /* (TC) Edge: None */
+#define     AT91C_TC_EEVTEDG_RISING           ( ( unsigned int ) 0x1 << 8 )  /* (TC) Edge: rising edge */
+#define     AT91C_TC_EEVTEDG_FALLING          ( ( unsigned int ) 0x2 << 8 )  /* (TC) Edge: falling edge */
+#define     AT91C_TC_EEVTEDG_BOTH             ( ( unsigned int ) 0x3 << 8 )  /* (TC) Edge: each edge */
+#define AT91C_TC_EEVT                         ( ( unsigned int ) 0x3 << 10 ) /* (TC) External Event  Selection */
+#define     AT91C_TC_EEVT_TIOB                ( ( unsigned int ) 0x0 << 10 ) /* (TC) Signal selected as external event: TIOB TIOB direction: input */
+#define     AT91C_TC_EEVT_XC0                 ( ( unsigned int ) 0x1 << 10 ) /* (TC) Signal selected as external event: XC0 TIOB direction: output */
+#define     AT91C_TC_EEVT_XC1                 ( ( unsigned int ) 0x2 << 10 ) /* (TC) Signal selected as external event: XC1 TIOB direction: output */
+#define     AT91C_TC_EEVT_XC2                 ( ( unsigned int ) 0x3 << 10 ) /* (TC) Signal selected as external event: XC2 TIOB direction: output */
+#define AT91C_TC_ABETRG                       ( ( unsigned int ) 0x1 << 10 ) /* (TC) TIOA or TIOB External Trigger Selection */
+#define AT91C_TC_ENETRG                       ( ( unsigned int ) 0x1 << 12 ) /* (TC) External Event Trigger enable */
+#define AT91C_TC_WAVESEL                      ( ( unsigned int ) 0x3 << 13 ) /* (TC) Waveform  Selection */
+#define     AT91C_TC_WAVESEL_UP               ( ( unsigned int ) 0x0 << 13 ) /* (TC) UP mode without atomatic trigger on RC Compare */
+#define     AT91C_TC_WAVESEL_UPDOWN           ( ( unsigned int ) 0x1 << 13 ) /* (TC) UPDOWN mode without automatic trigger on RC Compare */
+#define     AT91C_TC_WAVESEL_UP_AUTO          ( ( unsigned int ) 0x2 << 13 ) /* (TC) UP mode with automatic trigger on RC Compare */
+#define     AT91C_TC_WAVESEL_UPDOWN_AUTO      ( ( unsigned int ) 0x3 << 13 ) /* (TC) UPDOWN mode with automatic trigger on RC Compare */
+#define AT91C_TC_CPCTRG                       ( ( unsigned int ) 0x1 << 14 ) /* (TC) RC Compare Trigger Enable */
+#define AT91C_TC_WAVE                         ( ( unsigned int ) 0x1 << 15 ) /* (TC) */
+#define AT91C_TC_ACPA                         ( ( unsigned int ) 0x3 << 16 ) /* (TC) RA Compare Effect on TIOA */
+#define     AT91C_TC_ACPA_NONE                ( ( unsigned int ) 0x0 << 16 ) /* (TC) Effect: none */
+#define     AT91C_TC_ACPA_SET                 ( ( unsigned int ) 0x1 << 16 ) /* (TC) Effect: set */
+#define     AT91C_TC_ACPA_CLEAR               ( ( unsigned int ) 0x2 << 16 ) /* (TC) Effect: clear */
+#define     AT91C_TC_ACPA_TOGGLE              ( ( unsigned int ) 0x3 << 16 ) /* (TC) Effect: toggle */
+#define AT91C_TC_LDRA                         ( ( unsigned int ) 0x3 << 16 ) /* (TC) RA Loading Selection */
+#define     AT91C_TC_LDRA_NONE                ( ( unsigned int ) 0x0 << 16 ) /* (TC) Edge: None */
+#define     AT91C_TC_LDRA_RISING              ( ( unsigned int ) 0x1 << 16 ) /* (TC) Edge: rising edge of TIOA */
+#define     AT91C_TC_LDRA_FALLING             ( ( unsigned int ) 0x2 << 16 ) /* (TC) Edge: falling edge of TIOA */
+#define     AT91C_TC_LDRA_BOTH                ( ( unsigned int ) 0x3 << 16 ) /* (TC) Edge: each edge of TIOA */
+#define AT91C_TC_ACPC                         ( ( unsigned int ) 0x3 << 18 ) /* (TC) RC Compare Effect on TIOA */
+#define     AT91C_TC_ACPC_NONE                ( ( unsigned int ) 0x0 << 18 ) /* (TC) Effect: none */
+#define     AT91C_TC_ACPC_SET                 ( ( unsigned int ) 0x1 << 18 ) /* (TC) Effect: set */
+#define     AT91C_TC_ACPC_CLEAR               ( ( unsigned int ) 0x2 << 18 ) /* (TC) Effect: clear */
+#define     AT91C_TC_ACPC_TOGGLE              ( ( unsigned int ) 0x3 << 18 ) /* (TC) Effect: toggle */
+#define AT91C_TC_LDRB                         ( ( unsigned int ) 0x3 << 18 ) /* (TC) RB Loading Selection */
+#define     AT91C_TC_LDRB_NONE                ( ( unsigned int ) 0x0 << 18 ) /* (TC) Edge: None */
+#define     AT91C_TC_LDRB_RISING              ( ( unsigned int ) 0x1 << 18 ) /* (TC) Edge: rising edge of TIOA */
+#define     AT91C_TC_LDRB_FALLING             ( ( unsigned int ) 0x2 << 18 ) /* (TC) Edge: falling edge of TIOA */
+#define     AT91C_TC_LDRB_BOTH                ( ( unsigned int ) 0x3 << 18 ) /* (TC) Edge: each edge of TIOA */
+#define AT91C_TC_AEEVT                        ( ( unsigned int ) 0x3 << 20 ) /* (TC) External Event Effect on TIOA */
+#define     AT91C_TC_AEEVT_NONE               ( ( unsigned int ) 0x0 << 20 ) /* (TC) Effect: none */
+#define     AT91C_TC_AEEVT_SET                ( ( unsigned int ) 0x1 << 20 ) /* (TC) Effect: set */
+#define     AT91C_TC_AEEVT_CLEAR              ( ( unsigned int ) 0x2 << 20 ) /* (TC) Effect: clear */
+#define     AT91C_TC_AEEVT_TOGGLE             ( ( unsigned int ) 0x3 << 20 ) /* (TC) Effect: toggle */
+#define AT91C_TC_ASWTRG                       ( ( unsigned int ) 0x3 << 22 ) /* (TC) Software Trigger Effect on TIOA */
+#define     AT91C_TC_ASWTRG_NONE              ( ( unsigned int ) 0x0 << 22 ) /* (TC) Effect: none */
+#define     AT91C_TC_ASWTRG_SET               ( ( unsigned int ) 0x1 << 22 ) /* (TC) Effect: set */
+#define     AT91C_TC_ASWTRG_CLEAR             ( ( unsigned int ) 0x2 << 22 ) /* (TC) Effect: clear */
+#define     AT91C_TC_ASWTRG_TOGGLE            ( ( unsigned int ) 0x3 << 22 ) /* (TC) Effect: toggle */
+#define AT91C_TC_BCPB                         ( ( unsigned int ) 0x3 << 24 ) /* (TC) RB Compare Effect on TIOB */
+#define     AT91C_TC_BCPB_NONE                ( ( unsigned int ) 0x0 << 24 ) /* (TC) Effect: none */
+#define     AT91C_TC_BCPB_SET                 ( ( unsigned int ) 0x1 << 24 ) /* (TC) Effect: set */
+#define     AT91C_TC_BCPB_CLEAR               ( ( unsigned int ) 0x2 << 24 ) /* (TC) Effect: clear */
+#define     AT91C_TC_BCPB_TOGGLE              ( ( unsigned int ) 0x3 << 24 ) /* (TC) Effect: toggle */
+#define AT91C_TC_BCPC                         ( ( unsigned int ) 0x3 << 26 ) /* (TC) RC Compare Effect on TIOB */
+#define     AT91C_TC_BCPC_NONE                ( ( unsigned int ) 0x0 << 26 ) /* (TC) Effect: none */
+#define     AT91C_TC_BCPC_SET                 ( ( unsigned int ) 0x1 << 26 ) /* (TC) Effect: set */
+#define     AT91C_TC_BCPC_CLEAR               ( ( unsigned int ) 0x2 << 26 ) /* (TC) Effect: clear */
+#define     AT91C_TC_BCPC_TOGGLE              ( ( unsigned int ) 0x3 << 26 ) /* (TC) Effect: toggle */
+#define AT91C_TC_BEEVT                        ( ( unsigned int ) 0x3 << 28 ) /* (TC) External Event Effect on TIOB */
+#define     AT91C_TC_BEEVT_NONE               ( ( unsigned int ) 0x0 << 28 ) /* (TC) Effect: none */
+#define     AT91C_TC_BEEVT_SET                ( ( unsigned int ) 0x1 << 28 ) /* (TC) Effect: set */
+#define     AT91C_TC_BEEVT_CLEAR              ( ( unsigned int ) 0x2 << 28 ) /* (TC) Effect: clear */
+#define     AT91C_TC_BEEVT_TOGGLE             ( ( unsigned int ) 0x3 << 28 ) /* (TC) Effect: toggle */
+#define AT91C_TC_BSWTRG                       ( ( unsigned int ) 0x3 << 30 ) /* (TC) Software Trigger Effect on TIOB */
+#define     AT91C_TC_BSWTRG_NONE              ( ( unsigned int ) 0x0 << 30 ) /* (TC) Effect: none */
+#define     AT91C_TC_BSWTRG_SET               ( ( unsigned int ) 0x1 << 30 ) /* (TC) Effect: set */
+#define     AT91C_TC_BSWTRG_CLEAR             ( ( unsigned int ) 0x2 << 30 ) /* (TC) Effect: clear */
+#define     AT91C_TC_BSWTRG_TOGGLE            ( ( unsigned int ) 0x3 << 30 ) /* (TC) Effect: toggle */
+/* -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- */
+#define AT91C_TC_COVFS                        ( ( unsigned int ) 0x1 << 0 )  /* (TC) Counter Overflow */
+#define AT91C_TC_LOVRS                        ( ( unsigned int ) 0x1 << 1 )  /* (TC) Load Overrun */
+#define AT91C_TC_CPAS                         ( ( unsigned int ) 0x1 << 2 )  /* (TC) RA Compare */
+#define AT91C_TC_CPBS                         ( ( unsigned int ) 0x1 << 3 )  /* (TC) RB Compare */
+#define AT91C_TC_CPCS                         ( ( unsigned int ) 0x1 << 4 )  /* (TC) RC Compare */
+#define AT91C_TC_LDRAS                        ( ( unsigned int ) 0x1 << 5 )  /* (TC) RA Loading */
+#define AT91C_TC_LDRBS                        ( ( unsigned int ) 0x1 << 6 )  /* (TC) RB Loading */
+#define AT91C_TC_ETRGS                        ( ( unsigned int ) 0x1 << 7 )  /* (TC) External Trigger */
+#define AT91C_TC_CLKSTA                       ( ( unsigned int ) 0x1 << 16 ) /* (TC) Clock Enabling */
+#define AT91C_TC_MTIOA                        ( ( unsigned int ) 0x1 << 17 ) /* (TC) TIOA Mirror */
+#define AT91C_TC_MTIOB                        ( ( unsigned int ) 0x1 << 18 ) /* (TC) TIOA Mirror */
+/* -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- */
+/* -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- */
+/* -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Timer Counter Interface
-// *****************************************************************************
-typedef struct _AT91S_TCB {
-    AT91S_TC     TCB_TC0;   // TC Channel 0
-    AT91_REG     Reserved0[4];  //
-    AT91S_TC     TCB_TC1;   // TC Channel 1
-    AT91_REG     Reserved1[4];  //
-    AT91S_TC     TCB_TC2;   // TC Channel 2
-    AT91_REG     Reserved2[4];  //
-    AT91_REG     TCB_BCR;   // TC Block Control Register
-    AT91_REG     TCB_BMR;   // TC Block Mode Register
-} AT91S_TCB, *AT91PS_TCB;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Timer Counter Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_TCB
+{
+    AT91S_TC TCB_TC0;        /* TC Channel 0 */
+    AT91_REG Reserved0[ 4 ]; /* */
+    AT91S_TC TCB_TC1;        /* TC Channel 1 */
+    AT91_REG Reserved1[ 4 ]; /* */
+    AT91S_TC TCB_TC2;        /* TC Channel 2 */
+    AT91_REG Reserved2[ 4 ]; /* */
+    AT91_REG TCB_BCR;        /* TC Block Control Register */
+    AT91_REG TCB_BMR;        /* TC Block Mode Register */
+} AT91S_TCB, * AT91PS_TCB;
 
-// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
-#define AT91C_TCB_SYNC        ((unsigned int) 0x1 <<  0) // (TCB) Synchro Command
-// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
-#define AT91C_TCB_TC0XC0S     ((unsigned int) 0x3 <<  0) // (TCB) External Clock Signal 0 Selection
-#define     AT91C_TCB_TC0XC0S_TCLK0                ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0
-#define     AT91C_TCB_TC0XC0S_NONE                 ((unsigned int) 0x1) // (TCB) None signal connected to XC0
-#define     AT91C_TCB_TC0XC0S_TIOA1                ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0
-#define     AT91C_TCB_TC0XC0S_TIOA2                ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0
-#define AT91C_TCB_TC1XC1S     ((unsigned int) 0x3 <<  2) // (TCB) External Clock Signal 1 Selection
-#define     AT91C_TCB_TC1XC1S_TCLK1                ((unsigned int) 0x0 <<  2) // (TCB) TCLK1 connected to XC1
-#define     AT91C_TCB_TC1XC1S_NONE                 ((unsigned int) 0x1 <<  2) // (TCB) None signal connected to XC1
-#define     AT91C_TCB_TC1XC1S_TIOA0                ((unsigned int) 0x2 <<  2) // (TCB) TIOA0 connected to XC1
-#define     AT91C_TCB_TC1XC1S_TIOA2                ((unsigned int) 0x3 <<  2) // (TCB) TIOA2 connected to XC1
-#define AT91C_TCB_TC2XC2S     ((unsigned int) 0x3 <<  4) // (TCB) External Clock Signal 2 Selection
-#define     AT91C_TCB_TC2XC2S_TCLK2                ((unsigned int) 0x0 <<  4) // (TCB) TCLK2 connected to XC2
-#define     AT91C_TCB_TC2XC2S_NONE                 ((unsigned int) 0x1 <<  4) // (TCB) None signal connected to XC2
-#define     AT91C_TCB_TC2XC2S_TIOA0                ((unsigned int) 0x2 <<  4) // (TCB) TIOA0 connected to XC2
-#define     AT91C_TCB_TC2XC2S_TIOA1                ((unsigned int) 0x3 <<  4) // (TCB) TIOA2 connected to XC2
+/* -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- */
+#define AT91C_TCB_SYNC                 ( ( unsigned int ) 0x1 << 0 ) /* (TCB) Synchro Command */
+/* -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- */
+#define AT91C_TCB_TC0XC0S              ( ( unsigned int ) 0x3 << 0 ) /* (TCB) External Clock Signal 0 Selection */
+#define     AT91C_TCB_TC0XC0S_TCLK0    ( ( unsigned int ) 0x0 )      /* (TCB) TCLK0 connected to XC0 */
+#define     AT91C_TCB_TC0XC0S_NONE     ( ( unsigned int ) 0x1 )      /* (TCB) None signal connected to XC0 */
+#define     AT91C_TCB_TC0XC0S_TIOA1    ( ( unsigned int ) 0x2 )      /* (TCB) TIOA1 connected to XC0 */
+#define     AT91C_TCB_TC0XC0S_TIOA2    ( ( unsigned int ) 0x3 )      /* (TCB) TIOA2 connected to XC0 */
+#define AT91C_TCB_TC1XC1S              ( ( unsigned int ) 0x3 << 2 ) /* (TCB) External Clock Signal 1 Selection */
+#define     AT91C_TCB_TC1XC1S_TCLK1    ( ( unsigned int ) 0x0 << 2 ) /* (TCB) TCLK1 connected to XC1 */
+#define     AT91C_TCB_TC1XC1S_NONE     ( ( unsigned int ) 0x1 << 2 ) /* (TCB) None signal connected to XC1 */
+#define     AT91C_TCB_TC1XC1S_TIOA0    ( ( unsigned int ) 0x2 << 2 ) /* (TCB) TIOA0 connected to XC1 */
+#define     AT91C_TCB_TC1XC1S_TIOA2    ( ( unsigned int ) 0x3 << 2 ) /* (TCB) TIOA2 connected to XC1 */
+#define AT91C_TCB_TC2XC2S              ( ( unsigned int ) 0x3 << 4 ) /* (TCB) External Clock Signal 2 Selection */
+#define     AT91C_TCB_TC2XC2S_TCLK2    ( ( unsigned int ) 0x0 << 4 ) /* (TCB) TCLK2 connected to XC2 */
+#define     AT91C_TCB_TC2XC2S_NONE     ( ( unsigned int ) 0x1 << 4 ) /* (TCB) None signal connected to XC2 */
+#define     AT91C_TCB_TC2XC2S_TIOA0    ( ( unsigned int ) 0x2 << 4 ) /* (TCB) TIOA0 connected to XC2 */
+#define     AT91C_TCB_TC2XC2S_TIOA1    ( ( unsigned int ) 0x3 << 4 ) /* (TCB) TIOA2 connected to XC2 */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Control Area Network MailBox Interface
-// *****************************************************************************
-typedef struct _AT91S_CAN_MB {
-    AT91_REG     CAN_MB_MMR;    // MailBox Mode Register
-    AT91_REG     CAN_MB_MAM;    // MailBox Acceptance Mask Register
-    AT91_REG     CAN_MB_MID;    // MailBox ID Register
-    AT91_REG     CAN_MB_MFID;   // MailBox Family ID Register
-    AT91_REG     CAN_MB_MSR;    // MailBox Status Register
-    AT91_REG     CAN_MB_MDL;    // MailBox Data Low Register
-    AT91_REG     CAN_MB_MDH;    // MailBox Data High Register
-    AT91_REG     CAN_MB_MCR;    // MailBox Control Register
-} AT91S_CAN_MB, *AT91PS_CAN_MB;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Control Area Network MailBox Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_CAN_MB
+{
+    AT91_REG CAN_MB_MMR;  /* MailBox Mode Register */
+    AT91_REG CAN_MB_MAM;  /* MailBox Acceptance Mask Register */
+    AT91_REG CAN_MB_MID;  /* MailBox ID Register */
+    AT91_REG CAN_MB_MFID; /* MailBox Family ID Register */
+    AT91_REG CAN_MB_MSR;  /* MailBox Status Register */
+    AT91_REG CAN_MB_MDL;  /* MailBox Data Low Register */
+    AT91_REG CAN_MB_MDH;  /* MailBox Data High Register */
+    AT91_REG CAN_MB_MCR;  /* MailBox Control Register */
+} AT91S_CAN_MB, * AT91PS_CAN_MB;
 
-// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register --------
-#define AT91C_CAN_MTIMEMARK   ((unsigned int) 0xFFFF <<  0) // (CAN_MB) Mailbox Timemark
-#define AT91C_CAN_PRIOR       ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority
-#define AT91C_CAN_MOT         ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type
-#define     AT91C_CAN_MOT_DIS                  ((unsigned int) 0x0 << 24) // (CAN_MB)
-#define     AT91C_CAN_MOT_RX                   ((unsigned int) 0x1 << 24) // (CAN_MB)
-#define     AT91C_CAN_MOT_RXOVERWRITE          ((unsigned int) 0x2 << 24) // (CAN_MB)
-#define     AT91C_CAN_MOT_TX                   ((unsigned int) 0x3 << 24) // (CAN_MB)
-#define     AT91C_CAN_MOT_CONSUMER             ((unsigned int) 0x4 << 24) // (CAN_MB)
-#define     AT91C_CAN_MOT_PRODUCER             ((unsigned int) 0x5 << 24) // (CAN_MB)
-// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register --------
-#define AT91C_CAN_MIDvB       ((unsigned int) 0x3FFFF <<  0) // (CAN_MB) Complementary bits for identifier in extended mode
-#define AT91C_CAN_MIDvA       ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode
-#define AT91C_CAN_MIDE        ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version
-// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register --------
-// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register --------
-// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register --------
-#define AT91C_CAN_MTIMESTAMP  ((unsigned int) 0xFFFF <<  0) // (CAN_MB) Timer Value
-#define AT91C_CAN_MDLC        ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code
-#define AT91C_CAN_MRTR        ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request
-#define AT91C_CAN_MABT        ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort
-#define AT91C_CAN_MRDY        ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready
-#define AT91C_CAN_MMI         ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored
-// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register --------
-// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register --------
-// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register --------
-#define AT91C_CAN_MACR        ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox
-#define AT91C_CAN_MTCR        ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command
+/* -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- */
+#define AT91C_CAN_MTIMEMARK              ( ( unsigned int ) 0xFFFF << 0 )  /* (CAN_MB) Mailbox Timemark */
+#define AT91C_CAN_PRIOR                  ( ( unsigned int ) 0xF << 16 )    /* (CAN_MB) Mailbox Priority */
+#define AT91C_CAN_MOT                    ( ( unsigned int ) 0x7 << 24 )    /* (CAN_MB) Mailbox Object Type */
+#define     AT91C_CAN_MOT_DIS            ( ( unsigned int ) 0x0 << 24 )    /* (CAN_MB) */
+#define     AT91C_CAN_MOT_RX             ( ( unsigned int ) 0x1 << 24 )    /* (CAN_MB) */
+#define     AT91C_CAN_MOT_RXOVERWRITE    ( ( unsigned int ) 0x2 << 24 )    /* (CAN_MB) */
+#define     AT91C_CAN_MOT_TX             ( ( unsigned int ) 0x3 << 24 )    /* (CAN_MB) */
+#define     AT91C_CAN_MOT_CONSUMER       ( ( unsigned int ) 0x4 << 24 )    /* (CAN_MB) */
+#define     AT91C_CAN_MOT_PRODUCER       ( ( unsigned int ) 0x5 << 24 )    /* (CAN_MB) */
+/* -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- */
+#define AT91C_CAN_MIDvB                  ( ( unsigned int ) 0x3FFFF << 0 ) /* (CAN_MB) Complementary bits for identifier in extended mode */
+#define AT91C_CAN_MIDvA                  ( ( unsigned int ) 0x7FF << 18 )  /* (CAN_MB) Identifier for standard frame mode */
+#define AT91C_CAN_MIDE                   ( ( unsigned int ) 0x1 << 29 )    /* (CAN_MB) Identifier Version */
+/* -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- */
+/* -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- */
+/* -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- */
+#define AT91C_CAN_MTIMESTAMP    ( ( unsigned int ) 0xFFFF << 0 ) /* (CAN_MB) Timer Value */
+#define AT91C_CAN_MDLC          ( ( unsigned int ) 0xF << 16 )   /* (CAN_MB) Mailbox Data Length Code */
+#define AT91C_CAN_MRTR          ( ( unsigned int ) 0x1 << 20 )   /* (CAN_MB) Mailbox Remote Transmission Request */
+#define AT91C_CAN_MABT          ( ( unsigned int ) 0x1 << 22 )   /* (CAN_MB) Mailbox Message Abort */
+#define AT91C_CAN_MRDY          ( ( unsigned int ) 0x1 << 23 )   /* (CAN_MB) Mailbox Ready */
+#define AT91C_CAN_MMI           ( ( unsigned int ) 0x1 << 24 )   /* (CAN_MB) Mailbox Message Ignored */
+/* -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- */
+/* -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- */
+/* -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- */
+#define AT91C_CAN_MACR    ( ( unsigned int ) 0x1 << 22 ) /* (CAN_MB) Abort Request for Mailbox */
+#define AT91C_CAN_MTCR    ( ( unsigned int ) 0x1 << 23 ) /* (CAN_MB) Mailbox Transfer Command */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Control Area Network Interface
-// *****************************************************************************
-typedef struct _AT91S_CAN {
-    AT91_REG     CAN_MR;    // Mode Register
-    AT91_REG     CAN_IER;   // Interrupt Enable Register
-    AT91_REG     CAN_IDR;   // Interrupt Disable Register
-    AT91_REG     CAN_IMR;   // Interrupt Mask Register
-    AT91_REG     CAN_SR;    // Status Register
-    AT91_REG     CAN_BR;    // Baudrate Register
-    AT91_REG     CAN_TIM;   // Timer Register
-    AT91_REG     CAN_TIMESTP;   // Time Stamp Register
-    AT91_REG     CAN_ECR;   // Error Counter Register
-    AT91_REG     CAN_TCR;   // Transfer Command Register
-    AT91_REG     CAN_ACR;   // Abort Command Register
-    AT91_REG     Reserved0[52];     //
-    AT91_REG     CAN_VR;    // Version Register
-    AT91_REG     Reserved1[64];     //
-    AT91S_CAN_MB     CAN_MB0;   // CAN Mailbox 0
-    AT91S_CAN_MB     CAN_MB1;   // CAN Mailbox 1
-    AT91S_CAN_MB     CAN_MB2;   // CAN Mailbox 2
-    AT91S_CAN_MB     CAN_MB3;   // CAN Mailbox 3
-    AT91S_CAN_MB     CAN_MB4;   // CAN Mailbox 4
-    AT91S_CAN_MB     CAN_MB5;   // CAN Mailbox 5
-    AT91S_CAN_MB     CAN_MB6;   // CAN Mailbox 6
-    AT91S_CAN_MB     CAN_MB7;   // CAN Mailbox 7
-    AT91S_CAN_MB     CAN_MB8;   // CAN Mailbox 8
-    AT91S_CAN_MB     CAN_MB9;   // CAN Mailbox 9
-    AT91S_CAN_MB     CAN_MB10;  // CAN Mailbox 10
-    AT91S_CAN_MB     CAN_MB11;  // CAN Mailbox 11
-    AT91S_CAN_MB     CAN_MB12;  // CAN Mailbox 12
-    AT91S_CAN_MB     CAN_MB13;  // CAN Mailbox 13
-    AT91S_CAN_MB     CAN_MB14;  // CAN Mailbox 14
-    AT91S_CAN_MB     CAN_MB15;  // CAN Mailbox 15
-} AT91S_CAN, *AT91PS_CAN;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Control Area Network Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_CAN
+{
+    AT91_REG CAN_MR;          /* Mode Register */
+    AT91_REG CAN_IER;         /* Interrupt Enable Register */
+    AT91_REG CAN_IDR;         /* Interrupt Disable Register */
+    AT91_REG CAN_IMR;         /* Interrupt Mask Register */
+    AT91_REG CAN_SR;          /* Status Register */
+    AT91_REG CAN_BR;          /* Baudrate Register */
+    AT91_REG CAN_TIM;         /* Timer Register */
+    AT91_REG CAN_TIMESTP;     /* Time Stamp Register */
+    AT91_REG CAN_ECR;         /* Error Counter Register */
+    AT91_REG CAN_TCR;         /* Transfer Command Register */
+    AT91_REG CAN_ACR;         /* Abort Command Register */
+    AT91_REG Reserved0[ 52 ]; /* */
+    AT91_REG CAN_VR;          /* Version Register */
+    AT91_REG Reserved1[ 64 ]; /* */
+    AT91S_CAN_MB CAN_MB0;     /* CAN Mailbox 0 */
+    AT91S_CAN_MB CAN_MB1;     /* CAN Mailbox 1 */
+    AT91S_CAN_MB CAN_MB2;     /* CAN Mailbox 2 */
+    AT91S_CAN_MB CAN_MB3;     /* CAN Mailbox 3 */
+    AT91S_CAN_MB CAN_MB4;     /* CAN Mailbox 4 */
+    AT91S_CAN_MB CAN_MB5;     /* CAN Mailbox 5 */
+    AT91S_CAN_MB CAN_MB6;     /* CAN Mailbox 6 */
+    AT91S_CAN_MB CAN_MB7;     /* CAN Mailbox 7 */
+    AT91S_CAN_MB CAN_MB8;     /* CAN Mailbox 8 */
+    AT91S_CAN_MB CAN_MB9;     /* CAN Mailbox 9 */
+    AT91S_CAN_MB CAN_MB10;    /* CAN Mailbox 10 */
+    AT91S_CAN_MB CAN_MB11;    /* CAN Mailbox 11 */
+    AT91S_CAN_MB CAN_MB12;    /* CAN Mailbox 12 */
+    AT91S_CAN_MB CAN_MB13;    /* CAN Mailbox 13 */
+    AT91S_CAN_MB CAN_MB14;    /* CAN Mailbox 14 */
+    AT91S_CAN_MB CAN_MB15;    /* CAN Mailbox 15 */
+} AT91S_CAN, * AT91PS_CAN;
 
-// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register --------
-#define AT91C_CAN_CANEN       ((unsigned int) 0x1 <<  0) // (CAN) CAN Controller Enable
-#define AT91C_CAN_LPM         ((unsigned int) 0x1 <<  1) // (CAN) Disable/Enable Low Power Mode
-#define AT91C_CAN_ABM         ((unsigned int) 0x1 <<  2) // (CAN) Disable/Enable Autobaud/Listen Mode
-#define AT91C_CAN_OVL         ((unsigned int) 0x1 <<  3) // (CAN) Disable/Enable Overload Frame
-#define AT91C_CAN_TEOF        ((unsigned int) 0x1 <<  4) // (CAN) Time Stamp messages at each end of Frame
-#define AT91C_CAN_TTM         ((unsigned int) 0x1 <<  5) // (CAN) Disable/Enable Time Trigger Mode
-#define AT91C_CAN_TIMFRZ      ((unsigned int) 0x1 <<  6) // (CAN) Enable Timer Freeze
-#define AT91C_CAN_DRPT        ((unsigned int) 0x1 <<  7) // (CAN) Disable Repeat
-// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register --------
-#define AT91C_CAN_MB0         ((unsigned int) 0x1 <<  0) // (CAN) Mailbox 0 Flag
-#define AT91C_CAN_MB1         ((unsigned int) 0x1 <<  1) // (CAN) Mailbox 1 Flag
-#define AT91C_CAN_MB2         ((unsigned int) 0x1 <<  2) // (CAN) Mailbox 2 Flag
-#define AT91C_CAN_MB3         ((unsigned int) 0x1 <<  3) // (CAN) Mailbox 3 Flag
-#define AT91C_CAN_MB4         ((unsigned int) 0x1 <<  4) // (CAN) Mailbox 4 Flag
-#define AT91C_CAN_MB5         ((unsigned int) 0x1 <<  5) // (CAN) Mailbox 5 Flag
-#define AT91C_CAN_MB6         ((unsigned int) 0x1 <<  6) // (CAN) Mailbox 6 Flag
-#define AT91C_CAN_MB7         ((unsigned int) 0x1 <<  7) // (CAN) Mailbox 7 Flag
-#define AT91C_CAN_MB8         ((unsigned int) 0x1 <<  8) // (CAN) Mailbox 8 Flag
-#define AT91C_CAN_MB9         ((unsigned int) 0x1 <<  9) // (CAN) Mailbox 9 Flag
-#define AT91C_CAN_MB10        ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag
-#define AT91C_CAN_MB11        ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag
-#define AT91C_CAN_MB12        ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag
-#define AT91C_CAN_MB13        ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag
-#define AT91C_CAN_MB14        ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag
-#define AT91C_CAN_MB15        ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag
-#define AT91C_CAN_ERRA        ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag
-#define AT91C_CAN_WARN        ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag
-#define AT91C_CAN_ERRP        ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag
-#define AT91C_CAN_BOFF        ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag
-#define AT91C_CAN_SLEEP       ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag
-#define AT91C_CAN_WAKEUP      ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag
-#define AT91C_CAN_TOVF        ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag
-#define AT91C_CAN_TSTP        ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag
-#define AT91C_CAN_CERR        ((unsigned int) 0x1 << 24) // (CAN) CRC Error
-#define AT91C_CAN_SERR        ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error
-#define AT91C_CAN_AERR        ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error
-#define AT91C_CAN_FERR        ((unsigned int) 0x1 << 27) // (CAN) Form Error
-#define AT91C_CAN_BERR        ((unsigned int) 0x1 << 28) // (CAN) Bit Error
-// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register --------
-// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register --------
-// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register --------
-#define AT91C_CAN_RBSY        ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy
-#define AT91C_CAN_TBSY        ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy
-#define AT91C_CAN_OVLY        ((unsigned int) 0x1 << 31) // (CAN) Overload Busy
-// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register --------
-#define AT91C_CAN_PHASE2      ((unsigned int) 0x7 <<  0) // (CAN) Phase 2 segment
-#define AT91C_CAN_PHASE1      ((unsigned int) 0x7 <<  4) // (CAN) Phase 1 segment
-#define AT91C_CAN_PROPAG      ((unsigned int) 0x7 <<  8) // (CAN) Programmation time segment
-#define AT91C_CAN_SYNC        ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment
-#define AT91C_CAN_BRP         ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler
-#define AT91C_CAN_SMP         ((unsigned int) 0x1 << 24) // (CAN) Sampling mode
-// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register --------
-#define AT91C_CAN_TIMER       ((unsigned int) 0xFFFF <<  0) // (CAN) Timer field
-// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register --------
-// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register --------
-#define AT91C_CAN_REC         ((unsigned int) 0xFF <<  0) // (CAN) Receive Error Counter
-#define AT91C_CAN_TEC         ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter
-// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register --------
-#define AT91C_CAN_TIMRST      ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field
-// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register --------
+/* -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- */
+#define AT91C_CAN_CANEN     ( ( unsigned int ) 0x1 << 0 )  /* (CAN) CAN Controller Enable */
+#define AT91C_CAN_LPM       ( ( unsigned int ) 0x1 << 1 )  /* (CAN) Disable/Enable Low Power Mode */
+#define AT91C_CAN_ABM       ( ( unsigned int ) 0x1 << 2 )  /* (CAN) Disable/Enable Autobaud/Listen Mode */
+#define AT91C_CAN_OVL       ( ( unsigned int ) 0x1 << 3 )  /* (CAN) Disable/Enable Overload Frame */
+#define AT91C_CAN_TEOF      ( ( unsigned int ) 0x1 << 4 )  /* (CAN) Time Stamp messages at each end of Frame */
+#define AT91C_CAN_TTM       ( ( unsigned int ) 0x1 << 5 )  /* (CAN) Disable/Enable Time Trigger Mode */
+#define AT91C_CAN_TIMFRZ    ( ( unsigned int ) 0x1 << 6 )  /* (CAN) Enable Timer Freeze */
+#define AT91C_CAN_DRPT      ( ( unsigned int ) 0x1 << 7 )  /* (CAN) Disable Repeat */
+/* -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- */
+#define AT91C_CAN_MB0       ( ( unsigned int ) 0x1 << 0 )  /* (CAN) Mailbox 0 Flag */
+#define AT91C_CAN_MB1       ( ( unsigned int ) 0x1 << 1 )  /* (CAN) Mailbox 1 Flag */
+#define AT91C_CAN_MB2       ( ( unsigned int ) 0x1 << 2 )  /* (CAN) Mailbox 2 Flag */
+#define AT91C_CAN_MB3       ( ( unsigned int ) 0x1 << 3 )  /* (CAN) Mailbox 3 Flag */
+#define AT91C_CAN_MB4       ( ( unsigned int ) 0x1 << 4 )  /* (CAN) Mailbox 4 Flag */
+#define AT91C_CAN_MB5       ( ( unsigned int ) 0x1 << 5 )  /* (CAN) Mailbox 5 Flag */
+#define AT91C_CAN_MB6       ( ( unsigned int ) 0x1 << 6 )  /* (CAN) Mailbox 6 Flag */
+#define AT91C_CAN_MB7       ( ( unsigned int ) 0x1 << 7 )  /* (CAN) Mailbox 7 Flag */
+#define AT91C_CAN_MB8       ( ( unsigned int ) 0x1 << 8 )  /* (CAN) Mailbox 8 Flag */
+#define AT91C_CAN_MB9       ( ( unsigned int ) 0x1 << 9 )  /* (CAN) Mailbox 9 Flag */
+#define AT91C_CAN_MB10      ( ( unsigned int ) 0x1 << 10 ) /* (CAN) Mailbox 10 Flag */
+#define AT91C_CAN_MB11      ( ( unsigned int ) 0x1 << 11 ) /* (CAN) Mailbox 11 Flag */
+#define AT91C_CAN_MB12      ( ( unsigned int ) 0x1 << 12 ) /* (CAN) Mailbox 12 Flag */
+#define AT91C_CAN_MB13      ( ( unsigned int ) 0x1 << 13 ) /* (CAN) Mailbox 13 Flag */
+#define AT91C_CAN_MB14      ( ( unsigned int ) 0x1 << 14 ) /* (CAN) Mailbox 14 Flag */
+#define AT91C_CAN_MB15      ( ( unsigned int ) 0x1 << 15 ) /* (CAN) Mailbox 15 Flag */
+#define AT91C_CAN_ERRA      ( ( unsigned int ) 0x1 << 16 ) /* (CAN) Error Active Mode Flag */
+#define AT91C_CAN_WARN      ( ( unsigned int ) 0x1 << 17 ) /* (CAN) Warning Limit Flag */
+#define AT91C_CAN_ERRP      ( ( unsigned int ) 0x1 << 18 ) /* (CAN) Error Passive Mode Flag */
+#define AT91C_CAN_BOFF      ( ( unsigned int ) 0x1 << 19 ) /* (CAN) Bus Off Mode Flag */
+#define AT91C_CAN_SLEEP     ( ( unsigned int ) 0x1 << 20 ) /* (CAN) Sleep Flag */
+#define AT91C_CAN_WAKEUP    ( ( unsigned int ) 0x1 << 21 ) /* (CAN) Wakeup Flag */
+#define AT91C_CAN_TOVF      ( ( unsigned int ) 0x1 << 22 ) /* (CAN) Timer Overflow Flag */
+#define AT91C_CAN_TSTP      ( ( unsigned int ) 0x1 << 23 ) /* (CAN) Timestamp Flag */
+#define AT91C_CAN_CERR      ( ( unsigned int ) 0x1 << 24 ) /* (CAN) CRC Error */
+#define AT91C_CAN_SERR      ( ( unsigned int ) 0x1 << 25 ) /* (CAN) Stuffing Error */
+#define AT91C_CAN_AERR      ( ( unsigned int ) 0x1 << 26 ) /* (CAN) Acknowledgment Error */
+#define AT91C_CAN_FERR      ( ( unsigned int ) 0x1 << 27 ) /* (CAN) Form Error */
+#define AT91C_CAN_BERR      ( ( unsigned int ) 0x1 << 28 ) /* (CAN) Bit Error */
+/* -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- */
+/* -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- */
+/* -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- */
+#define AT91C_CAN_RBSY      ( ( unsigned int ) 0x1 << 29 )   /* (CAN) Receiver Busy */
+#define AT91C_CAN_TBSY      ( ( unsigned int ) 0x1 << 30 )   /* (CAN) Transmitter Busy */
+#define AT91C_CAN_OVLY      ( ( unsigned int ) 0x1 << 31 )   /* (CAN) Overload Busy */
+/* -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- */
+#define AT91C_CAN_PHASE2    ( ( unsigned int ) 0x7 << 0 )    /* (CAN) Phase 2 segment */
+#define AT91C_CAN_PHASE1    ( ( unsigned int ) 0x7 << 4 )    /* (CAN) Phase 1 segment */
+#define AT91C_CAN_PROPAG    ( ( unsigned int ) 0x7 << 8 )    /* (CAN) Programmation time segment */
+#define AT91C_CAN_SYNC      ( ( unsigned int ) 0x3 << 12 )   /* (CAN) Re-synchronization jump width segment */
+#define AT91C_CAN_BRP       ( ( unsigned int ) 0x7F << 16 )  /* (CAN) Baudrate Prescaler */
+#define AT91C_CAN_SMP       ( ( unsigned int ) 0x1 << 24 )   /* (CAN) Sampling mode */
+/* -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- */
+#define AT91C_CAN_TIMER     ( ( unsigned int ) 0xFFFF << 0 ) /* (CAN) Timer field */
+/* -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- */
+/* -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- */
+#define AT91C_CAN_REC       ( ( unsigned int ) 0xFF << 0 )  /* (CAN) Receive Error Counter */
+#define AT91C_CAN_TEC       ( ( unsigned int ) 0xFF << 16 ) /* (CAN) Transmit Error Counter */
+/* -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- */
+#define AT91C_CAN_TIMRST    ( ( unsigned int ) 0x1 << 31 )  /* (CAN) Timer Reset Field */
+/* -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Ethernet MAC 10/100
-// *****************************************************************************
-typedef struct _AT91S_EMAC {
-    AT91_REG     EMAC_NCR;  // Network Control Register
-    AT91_REG     EMAC_NCFGR;    // Network Configuration Register
-    AT91_REG     EMAC_NSR;  // Network Status Register
-    AT91_REG     Reserved0[2];  //
-    AT91_REG     EMAC_TSR;  // Transmit Status Register
-    AT91_REG     EMAC_RBQP;     // Receive Buffer Queue Pointer
-    AT91_REG     EMAC_TBQP;     // Transmit Buffer Queue Pointer
-    AT91_REG     EMAC_RSR;  // Receive Status Register
-    AT91_REG     EMAC_ISR;  // Interrupt Status Register
-    AT91_REG     EMAC_IER;  // Interrupt Enable Register
-    AT91_REG     EMAC_IDR;  // Interrupt Disable Register
-    AT91_REG     EMAC_IMR;  // Interrupt Mask Register
-    AT91_REG     EMAC_MAN;  // PHY Maintenance Register
-    AT91_REG     EMAC_PTR;  // Pause Time Register
-    AT91_REG     EMAC_PFR;  // Pause Frames received Register
-    AT91_REG     EMAC_FTO;  // Frames Transmitted OK Register
-    AT91_REG     EMAC_SCF;  // Single Collision Frame Register
-    AT91_REG     EMAC_MCF;  // Multiple Collision Frame Register
-    AT91_REG     EMAC_FRO;  // Frames Received OK Register
-    AT91_REG     EMAC_FCSE;     // Frame Check Sequence Error Register
-    AT91_REG     EMAC_ALE;  // Alignment Error Register
-    AT91_REG     EMAC_DTF;  // Deferred Transmission Frame Register
-    AT91_REG     EMAC_LCOL;     // Late Collision Register
-    AT91_REG     EMAC_ECOL;     // Excessive Collision Register
-    AT91_REG     EMAC_TUND;     // Transmit Underrun Error Register
-    AT91_REG     EMAC_CSE;  // Carrier Sense Error Register
-    AT91_REG     EMAC_RRE;  // Receive Ressource Error Register
-    AT91_REG     EMAC_ROV;  // Receive Overrun Errors Register
-    AT91_REG     EMAC_RSE;  // Receive Symbol Errors Register
-    AT91_REG     EMAC_ELE;  // Excessive Length Errors Register
-    AT91_REG     EMAC_RJA;  // Receive Jabbers Register
-    AT91_REG     EMAC_USF;  // Undersize Frames Register
-    AT91_REG     EMAC_STE;  // SQE Test Error Register
-    AT91_REG     EMAC_RLE;  // Receive Length Field Mismatch Register
-    AT91_REG     EMAC_TPF;  // Transmitted Pause Frames Register
-    AT91_REG     EMAC_HRB;  // Hash Address Bottom[31:0]
-    AT91_REG     EMAC_HRT;  // Hash Address Top[63:32]
-    AT91_REG     EMAC_SA1L;     // Specific Address 1 Bottom, First 4 bytes
-    AT91_REG     EMAC_SA1H;     // Specific Address 1 Top, Last 2 bytes
-    AT91_REG     EMAC_SA2L;     // Specific Address 2 Bottom, First 4 bytes
-    AT91_REG     EMAC_SA2H;     // Specific Address 2 Top, Last 2 bytes
-    AT91_REG     EMAC_SA3L;     // Specific Address 3 Bottom, First 4 bytes
-    AT91_REG     EMAC_SA3H;     // Specific Address 3 Top, Last 2 bytes
-    AT91_REG     EMAC_SA4L;     // Specific Address 4 Bottom, First 4 bytes
-    AT91_REG     EMAC_SA4H;     // Specific Address 4 Top, Last 2 bytes
-    AT91_REG     EMAC_TID;  // Type ID Checking Register
-    AT91_REG     EMAC_TPQ;  // Transmit Pause Quantum Register
-    AT91_REG     EMAC_USRIO;    // USER Input/Output Register
-    AT91_REG     EMAC_WOL;  // Wake On LAN Register
-    AT91_REG     Reserved1[13];     //
-    AT91_REG     EMAC_REV;  // Revision Register
-} AT91S_EMAC, *AT91PS_EMAC;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Ethernet MAC 10/100 */
+/* ***************************************************************************** */
+typedef struct _AT91S_EMAC
+{
+    AT91_REG EMAC_NCR;        /* Network Control Register */
+    AT91_REG EMAC_NCFGR;      /* Network Configuration Register */
+    AT91_REG EMAC_NSR;        /* Network Status Register */
+    AT91_REG Reserved0[ 2 ];  /* */
+    AT91_REG EMAC_TSR;        /* Transmit Status Register */
+    AT91_REG EMAC_RBQP;       /* Receive Buffer Queue Pointer */
+    AT91_REG EMAC_TBQP;       /* Transmit Buffer Queue Pointer */
+    AT91_REG EMAC_RSR;        /* Receive Status Register */
+    AT91_REG EMAC_ISR;        /* Interrupt Status Register */
+    AT91_REG EMAC_IER;        /* Interrupt Enable Register */
+    AT91_REG EMAC_IDR;        /* Interrupt Disable Register */
+    AT91_REG EMAC_IMR;        /* Interrupt Mask Register */
+    AT91_REG EMAC_MAN;        /* PHY Maintenance Register */
+    AT91_REG EMAC_PTR;        /* Pause Time Register */
+    AT91_REG EMAC_PFR;        /* Pause Frames received Register */
+    AT91_REG EMAC_FTO;        /* Frames Transmitted OK Register */
+    AT91_REG EMAC_SCF;        /* Single Collision Frame Register */
+    AT91_REG EMAC_MCF;        /* Multiple Collision Frame Register */
+    AT91_REG EMAC_FRO;        /* Frames Received OK Register */
+    AT91_REG EMAC_FCSE;       /* Frame Check Sequence Error Register */
+    AT91_REG EMAC_ALE;        /* Alignment Error Register */
+    AT91_REG EMAC_DTF;        /* Deferred Transmission Frame Register */
+    AT91_REG EMAC_LCOL;       /* Late Collision Register */
+    AT91_REG EMAC_ECOL;       /* Excessive Collision Register */
+    AT91_REG EMAC_TUND;       /* Transmit Underrun Error Register */
+    AT91_REG EMAC_CSE;        /* Carrier Sense Error Register */
+    AT91_REG EMAC_RRE;        /* Receive Ressource Error Register */
+    AT91_REG EMAC_ROV;        /* Receive Overrun Errors Register */
+    AT91_REG EMAC_RSE;        /* Receive Symbol Errors Register */
+    AT91_REG EMAC_ELE;        /* Excessive Length Errors Register */
+    AT91_REG EMAC_RJA;        /* Receive Jabbers Register */
+    AT91_REG EMAC_USF;        /* Undersize Frames Register */
+    AT91_REG EMAC_STE;        /* SQE Test Error Register */
+    AT91_REG EMAC_RLE;        /* Receive Length Field Mismatch Register */
+    AT91_REG EMAC_TPF;        /* Transmitted Pause Frames Register */
+    AT91_REG EMAC_HRB;        /* Hash Address Bottom[31:0] */
+    AT91_REG EMAC_HRT;        /* Hash Address Top[63:32] */
+    AT91_REG EMAC_SA1L;       /* Specific Address 1 Bottom, First 4 bytes */
+    AT91_REG EMAC_SA1H;       /* Specific Address 1 Top, Last 2 bytes */
+    AT91_REG EMAC_SA2L;       /* Specific Address 2 Bottom, First 4 bytes */
+    AT91_REG EMAC_SA2H;       /* Specific Address 2 Top, Last 2 bytes */
+    AT91_REG EMAC_SA3L;       /* Specific Address 3 Bottom, First 4 bytes */
+    AT91_REG EMAC_SA3H;       /* Specific Address 3 Top, Last 2 bytes */
+    AT91_REG EMAC_SA4L;       /* Specific Address 4 Bottom, First 4 bytes */
+    AT91_REG EMAC_SA4H;       /* Specific Address 4 Top, Last 2 bytes */
+    AT91_REG EMAC_TID;        /* Type ID Checking Register */
+    AT91_REG EMAC_TPQ;        /* Transmit Pause Quantum Register */
+    AT91_REG EMAC_USRIO;      /* USER Input/Output Register */
+    AT91_REG EMAC_WOL;        /* Wake On LAN Register */
+    AT91_REG Reserved1[ 13 ]; /* */
+    AT91_REG EMAC_REV;        /* Revision Register */
+} AT91S_EMAC, * AT91PS_EMAC;
 
-// -------- EMAC_NCR : (EMAC Offset: 0x0)  --------
-#define AT91C_EMAC_LB         ((unsigned int) 0x1 <<  0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
-#define AT91C_EMAC_LLB        ((unsigned int) 0x1 <<  1) // (EMAC) Loopback local.
-#define AT91C_EMAC_RE         ((unsigned int) 0x1 <<  2) // (EMAC) Receive enable.
-#define AT91C_EMAC_TE         ((unsigned int) 0x1 <<  3) // (EMAC) Transmit enable.
-#define AT91C_EMAC_MPE        ((unsigned int) 0x1 <<  4) // (EMAC) Management port enable.
-#define AT91C_EMAC_CLRSTAT    ((unsigned int) 0x1 <<  5) // (EMAC) Clear statistics registers.
-#define AT91C_EMAC_INCSTAT    ((unsigned int) 0x1 <<  6) // (EMAC) Increment statistics registers.
-#define AT91C_EMAC_WESTAT     ((unsigned int) 0x1 <<  7) // (EMAC) Write enable for statistics registers.
-#define AT91C_EMAC_BP         ((unsigned int) 0x1 <<  8) // (EMAC) Back pressure.
-#define AT91C_EMAC_TSTART     ((unsigned int) 0x1 <<  9) // (EMAC) Start Transmission.
-#define AT91C_EMAC_THALT      ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt.
-#define AT91C_EMAC_TPFR       ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame
-#define AT91C_EMAC_TZQ        ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame
-// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register --------
-#define AT91C_EMAC_SPD        ((unsigned int) 0x1 <<  0) // (EMAC) Speed.
-#define AT91C_EMAC_FD         ((unsigned int) 0x1 <<  1) // (EMAC) Full duplex.
-#define AT91C_EMAC_JFRAME     ((unsigned int) 0x1 <<  3) // (EMAC) Jumbo Frames.
-#define AT91C_EMAC_CAF        ((unsigned int) 0x1 <<  4) // (EMAC) Copy all frames.
-#define AT91C_EMAC_NBC        ((unsigned int) 0x1 <<  5) // (EMAC) No broadcast.
-#define AT91C_EMAC_MTI        ((unsigned int) 0x1 <<  6) // (EMAC) Multicast hash event enable
-#define AT91C_EMAC_UNI        ((unsigned int) 0x1 <<  7) // (EMAC) Unicast hash enable.
-#define AT91C_EMAC_BIG        ((unsigned int) 0x1 <<  8) // (EMAC) Receive 1522 bytes.
-#define AT91C_EMAC_EAE        ((unsigned int) 0x1 <<  9) // (EMAC) External address match enable.
-#define AT91C_EMAC_CLK        ((unsigned int) 0x3 << 10) // (EMAC)
-#define     AT91C_EMAC_CLK_HCLK_8               ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8
-#define     AT91C_EMAC_CLK_HCLK_16              ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16
-#define     AT91C_EMAC_CLK_HCLK_32              ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32
-#define     AT91C_EMAC_CLK_HCLK_64              ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64
-#define AT91C_EMAC_RTY        ((unsigned int) 0x1 << 12) // (EMAC)
-#define AT91C_EMAC_PAE        ((unsigned int) 0x1 << 13) // (EMAC)
-#define AT91C_EMAC_RBOF       ((unsigned int) 0x3 << 14) // (EMAC)
-#define     AT91C_EMAC_RBOF_OFFSET_0             ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer
-#define     AT91C_EMAC_RBOF_OFFSET_1             ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer
-#define     AT91C_EMAC_RBOF_OFFSET_2             ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
-#define     AT91C_EMAC_RBOF_OFFSET_3             ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
-#define AT91C_EMAC_RLCE       ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable
-#define AT91C_EMAC_DRFCS      ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS
-#define AT91C_EMAC_EFRHD      ((unsigned int) 0x1 << 18) // (EMAC)
-#define AT91C_EMAC_IRXFCS     ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS
-// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register --------
-#define AT91C_EMAC_LINKR      ((unsigned int) 0x1 <<  0) // (EMAC)
-#define AT91C_EMAC_MDIO       ((unsigned int) 0x1 <<  1) // (EMAC)
-#define AT91C_EMAC_IDLE       ((unsigned int) 0x1 <<  2) // (EMAC)
-// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register --------
-#define AT91C_EMAC_UBR        ((unsigned int) 0x1 <<  0) // (EMAC)
-#define AT91C_EMAC_COL        ((unsigned int) 0x1 <<  1) // (EMAC)
-#define AT91C_EMAC_RLES       ((unsigned int) 0x1 <<  2) // (EMAC)
-#define AT91C_EMAC_TGO        ((unsigned int) 0x1 <<  3) // (EMAC) Transmit Go
-#define AT91C_EMAC_BEX        ((unsigned int) 0x1 <<  4) // (EMAC) Buffers exhausted mid frame
-#define AT91C_EMAC_COMP       ((unsigned int) 0x1 <<  5) // (EMAC)
-#define AT91C_EMAC_UND        ((unsigned int) 0x1 <<  6) // (EMAC)
-// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register --------
-#define AT91C_EMAC_BNA        ((unsigned int) 0x1 <<  0) // (EMAC)
-#define AT91C_EMAC_REC        ((unsigned int) 0x1 <<  1) // (EMAC)
-#define AT91C_EMAC_OVR        ((unsigned int) 0x1 <<  2) // (EMAC)
-// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register --------
-#define AT91C_EMAC_MFD        ((unsigned int) 0x1 <<  0) // (EMAC)
-#define AT91C_EMAC_RCOMP      ((unsigned int) 0x1 <<  1) // (EMAC)
-#define AT91C_EMAC_RXUBR      ((unsigned int) 0x1 <<  2) // (EMAC)
-#define AT91C_EMAC_TXUBR      ((unsigned int) 0x1 <<  3) // (EMAC)
-#define AT91C_EMAC_TUNDR      ((unsigned int) 0x1 <<  4) // (EMAC)
-#define AT91C_EMAC_RLEX       ((unsigned int) 0x1 <<  5) // (EMAC)
-#define AT91C_EMAC_TXERR      ((unsigned int) 0x1 <<  6) // (EMAC)
-#define AT91C_EMAC_TCOMP      ((unsigned int) 0x1 <<  7) // (EMAC)
-#define AT91C_EMAC_LINK       ((unsigned int) 0x1 <<  9) // (EMAC)
-#define AT91C_EMAC_ROVR       ((unsigned int) 0x1 << 10) // (EMAC)
-#define AT91C_EMAC_HRESP      ((unsigned int) 0x1 << 11) // (EMAC)
-#define AT91C_EMAC_PFRE       ((unsigned int) 0x1 << 12) // (EMAC)
-#define AT91C_EMAC_PTZ        ((unsigned int) 0x1 << 13) // (EMAC)
-// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register --------
-// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register --------
-// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register --------
-// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register --------
-#define AT91C_EMAC_DATA       ((unsigned int) 0xFFFF <<  0) // (EMAC)
-#define AT91C_EMAC_CODE       ((unsigned int) 0x3 << 16) // (EMAC)
-#define AT91C_EMAC_REGA       ((unsigned int) 0x1F << 18) // (EMAC)
-#define AT91C_EMAC_PHYA       ((unsigned int) 0x1F << 23) // (EMAC)
-#define AT91C_EMAC_RW         ((unsigned int) 0x3 << 28) // (EMAC)
-#define AT91C_EMAC_SOF        ((unsigned int) 0x3 << 30) // (EMAC)
-// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register --------
-#define AT91C_EMAC_RMII       ((unsigned int) 0x1 <<  0) // (EMAC) Reduce MII
-// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register --------
-#define AT91C_EMAC_IP         ((unsigned int) 0xFFFF <<  0) // (EMAC) ARP request IP address
-#define AT91C_EMAC_MAG        ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable
-#define AT91C_EMAC_ARP        ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable
-#define AT91C_EMAC_SA1        ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable
-// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register --------
-#define AT91C_EMAC_REVREF     ((unsigned int) 0xFFFF <<  0) // (EMAC)
-#define AT91C_EMAC_PARTREF    ((unsigned int) 0xFFFF << 16) // (EMAC)
+/* -------- EMAC_NCR : (EMAC Offset: 0x0)  -------- */
+#define AT91C_EMAC_LB                   ( ( unsigned int ) 0x1 << 0 )  /* (EMAC) Loopback. Optional. When set, loopback signal is at high level. */
+#define AT91C_EMAC_LLB                  ( ( unsigned int ) 0x1 << 1 )  /* (EMAC) Loopback local. */
+#define AT91C_EMAC_RE                   ( ( unsigned int ) 0x1 << 2 )  /* (EMAC) Receive enable. */
+#define AT91C_EMAC_TE                   ( ( unsigned int ) 0x1 << 3 )  /* (EMAC) Transmit enable. */
+#define AT91C_EMAC_MPE                  ( ( unsigned int ) 0x1 << 4 )  /* (EMAC) Management port enable. */
+#define AT91C_EMAC_CLRSTAT              ( ( unsigned int ) 0x1 << 5 )  /* (EMAC) Clear statistics registers. */
+#define AT91C_EMAC_INCSTAT              ( ( unsigned int ) 0x1 << 6 )  /* (EMAC) Increment statistics registers. */
+#define AT91C_EMAC_WESTAT               ( ( unsigned int ) 0x1 << 7 )  /* (EMAC) Write enable for statistics registers. */
+#define AT91C_EMAC_BP                   ( ( unsigned int ) 0x1 << 8 )  /* (EMAC) Back pressure. */
+#define AT91C_EMAC_TSTART               ( ( unsigned int ) 0x1 << 9 )  /* (EMAC) Start Transmission. */
+#define AT91C_EMAC_THALT                ( ( unsigned int ) 0x1 << 10 ) /* (EMAC) Transmission Halt. */
+#define AT91C_EMAC_TPFR                 ( ( unsigned int ) 0x1 << 11 ) /* (EMAC) Transmit pause frame */
+#define AT91C_EMAC_TZQ                  ( ( unsigned int ) 0x1 << 12 ) /* (EMAC) Transmit zero quantum pause frame */
+/* -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- */
+#define AT91C_EMAC_SPD                  ( ( unsigned int ) 0x1 << 0 )  /* (EMAC) Speed. */
+#define AT91C_EMAC_FD                   ( ( unsigned int ) 0x1 << 1 )  /* (EMAC) Full duplex. */
+#define AT91C_EMAC_JFRAME               ( ( unsigned int ) 0x1 << 3 )  /* (EMAC) Jumbo Frames. */
+#define AT91C_EMAC_CAF                  ( ( unsigned int ) 0x1 << 4 )  /* (EMAC) Copy all frames. */
+#define AT91C_EMAC_NBC                  ( ( unsigned int ) 0x1 << 5 )  /* (EMAC) No broadcast. */
+#define AT91C_EMAC_MTI                  ( ( unsigned int ) 0x1 << 6 )  /* (EMAC) Multicast hash event enable */
+#define AT91C_EMAC_UNI                  ( ( unsigned int ) 0x1 << 7 )  /* (EMAC) Unicast hash enable. */
+#define AT91C_EMAC_BIG                  ( ( unsigned int ) 0x1 << 8 )  /* (EMAC) Receive 1522 bytes. */
+#define AT91C_EMAC_EAE                  ( ( unsigned int ) 0x1 << 9 )  /* (EMAC) External address match enable. */
+#define AT91C_EMAC_CLK                  ( ( unsigned int ) 0x3 << 10 ) /* (EMAC) */
+#define     AT91C_EMAC_CLK_HCLK_8       ( ( unsigned int ) 0x0 << 10 ) /* (EMAC) HCLK divided by 8 */
+#define     AT91C_EMAC_CLK_HCLK_16      ( ( unsigned int ) 0x1 << 10 ) /* (EMAC) HCLK divided by 16 */
+#define     AT91C_EMAC_CLK_HCLK_32      ( ( unsigned int ) 0x2 << 10 ) /* (EMAC) HCLK divided by 32 */
+#define     AT91C_EMAC_CLK_HCLK_64      ( ( unsigned int ) 0x3 << 10 ) /* (EMAC) HCLK divided by 64 */
+#define AT91C_EMAC_RTY                  ( ( unsigned int ) 0x1 << 12 ) /* (EMAC) */
+#define AT91C_EMAC_PAE                  ( ( unsigned int ) 0x1 << 13 ) /* (EMAC) */
+#define AT91C_EMAC_RBOF                 ( ( unsigned int ) 0x3 << 14 ) /* (EMAC) */
+#define     AT91C_EMAC_RBOF_OFFSET_0    ( ( unsigned int ) 0x0 << 14 ) /* (EMAC) no offset from start of receive buffer */
+#define     AT91C_EMAC_RBOF_OFFSET_1    ( ( unsigned int ) 0x1 << 14 ) /* (EMAC) one byte offset from start of receive buffer */
+#define     AT91C_EMAC_RBOF_OFFSET_2    ( ( unsigned int ) 0x2 << 14 ) /* (EMAC) two bytes offset from start of receive buffer */
+#define     AT91C_EMAC_RBOF_OFFSET_3    ( ( unsigned int ) 0x3 << 14 ) /* (EMAC) three bytes offset from start of receive buffer */
+#define AT91C_EMAC_RLCE                 ( ( unsigned int ) 0x1 << 16 ) /* (EMAC) Receive Length field Checking Enable */
+#define AT91C_EMAC_DRFCS                ( ( unsigned int ) 0x1 << 17 ) /* (EMAC) Discard Receive FCS */
+#define AT91C_EMAC_EFRHD                ( ( unsigned int ) 0x1 << 18 ) /* (EMAC) */
+#define AT91C_EMAC_IRXFCS               ( ( unsigned int ) 0x1 << 19 ) /* (EMAC) Ignore RX FCS */
+/* -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- */
+#define AT91C_EMAC_LINKR                ( ( unsigned int ) 0x1 << 0 )  /* (EMAC) */
+#define AT91C_EMAC_MDIO                 ( ( unsigned int ) 0x1 << 1 )  /* (EMAC) */
+#define AT91C_EMAC_IDLE                 ( ( unsigned int ) 0x1 << 2 )  /* (EMAC) */
+/* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- */
+#define AT91C_EMAC_UBR                  ( ( unsigned int ) 0x1 << 0 )  /* (EMAC) */
+#define AT91C_EMAC_COL                  ( ( unsigned int ) 0x1 << 1 )  /* (EMAC) */
+#define AT91C_EMAC_RLES                 ( ( unsigned int ) 0x1 << 2 )  /* (EMAC) */
+#define AT91C_EMAC_TGO                  ( ( unsigned int ) 0x1 << 3 )  /* (EMAC) Transmit Go */
+#define AT91C_EMAC_BEX                  ( ( unsigned int ) 0x1 << 4 )  /* (EMAC) Buffers exhausted mid frame */
+#define AT91C_EMAC_COMP                 ( ( unsigned int ) 0x1 << 5 )  /* (EMAC) */
+#define AT91C_EMAC_UND                  ( ( unsigned int ) 0x1 << 6 )  /* (EMAC) */
+/* -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- */
+#define AT91C_EMAC_BNA                  ( ( unsigned int ) 0x1 << 0 )  /* (EMAC) */
+#define AT91C_EMAC_REC                  ( ( unsigned int ) 0x1 << 1 )  /* (EMAC) */
+#define AT91C_EMAC_OVR                  ( ( unsigned int ) 0x1 << 2 )  /* (EMAC) */
+/* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- */
+#define AT91C_EMAC_MFD                  ( ( unsigned int ) 0x1 << 0 )  /* (EMAC) */
+#define AT91C_EMAC_RCOMP                ( ( unsigned int ) 0x1 << 1 )  /* (EMAC) */
+#define AT91C_EMAC_RXUBR                ( ( unsigned int ) 0x1 << 2 )  /* (EMAC) */
+#define AT91C_EMAC_TXUBR                ( ( unsigned int ) 0x1 << 3 )  /* (EMAC) */
+#define AT91C_EMAC_TUNDR                ( ( unsigned int ) 0x1 << 4 )  /* (EMAC) */
+#define AT91C_EMAC_RLEX                 ( ( unsigned int ) 0x1 << 5 )  /* (EMAC) */
+#define AT91C_EMAC_TXERR                ( ( unsigned int ) 0x1 << 6 )  /* (EMAC) */
+#define AT91C_EMAC_TCOMP                ( ( unsigned int ) 0x1 << 7 )  /* (EMAC) */
+#define AT91C_EMAC_LINK                 ( ( unsigned int ) 0x1 << 9 )  /* (EMAC) */
+#define AT91C_EMAC_ROVR                 ( ( unsigned int ) 0x1 << 10 ) /* (EMAC) */
+#define AT91C_EMAC_HRESP                ( ( unsigned int ) 0x1 << 11 ) /* (EMAC) */
+#define AT91C_EMAC_PFRE                 ( ( unsigned int ) 0x1 << 12 ) /* (EMAC) */
+#define AT91C_EMAC_PTZ                  ( ( unsigned int ) 0x1 << 13 ) /* (EMAC) */
+/* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- */
+/* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- */
+/* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */
+/* -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- */
+#define AT91C_EMAC_DATA       ( ( unsigned int ) 0xFFFF << 0 )  /* (EMAC) */
+#define AT91C_EMAC_CODE       ( ( unsigned int ) 0x3 << 16 )    /* (EMAC) */
+#define AT91C_EMAC_REGA       ( ( unsigned int ) 0x1F << 18 )   /* (EMAC) */
+#define AT91C_EMAC_PHYA       ( ( unsigned int ) 0x1F << 23 )   /* (EMAC) */
+#define AT91C_EMAC_RW         ( ( unsigned int ) 0x3 << 28 )    /* (EMAC) */
+#define AT91C_EMAC_SOF        ( ( unsigned int ) 0x3 << 30 )    /* (EMAC) */
+/* -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- */
+#define AT91C_EMAC_RMII       ( ( unsigned int ) 0x1 << 0 )     /* (EMAC) Reduce MII */
+/* -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- */
+#define AT91C_EMAC_IP         ( ( unsigned int ) 0xFFFF << 0 )  /* (EMAC) ARP request IP address */
+#define AT91C_EMAC_MAG        ( ( unsigned int ) 0x1 << 16 )    /* (EMAC) Magic packet event enable */
+#define AT91C_EMAC_ARP        ( ( unsigned int ) 0x1 << 17 )    /* (EMAC) ARP request event enable */
+#define AT91C_EMAC_SA1        ( ( unsigned int ) 0x1 << 18 )    /* (EMAC) Specific address register 1 event enable */
+/* -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- */
+#define AT91C_EMAC_REVREF     ( ( unsigned int ) 0xFFFF << 0 )  /* (EMAC) */
+#define AT91C_EMAC_PARTREF    ( ( unsigned int ) 0xFFFF << 16 ) /* (EMAC) */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
-// *****************************************************************************
-typedef struct _AT91S_ADC {
-    AT91_REG     ADC_CR;    // ADC Control Register
-    AT91_REG     ADC_MR;    // ADC Mode Register
-    AT91_REG     Reserved0[2];  //
-    AT91_REG     ADC_CHER;  // ADC Channel Enable Register
-    AT91_REG     ADC_CHDR;  // ADC Channel Disable Register
-    AT91_REG     ADC_CHSR;  // ADC Channel Status Register
-    AT91_REG     ADC_SR;    // ADC Status Register
-    AT91_REG     ADC_LCDR;  // ADC Last Converted Data Register
-    AT91_REG     ADC_IER;   // ADC Interrupt Enable Register
-    AT91_REG     ADC_IDR;   // ADC Interrupt Disable Register
-    AT91_REG     ADC_IMR;   // ADC Interrupt Mask Register
-    AT91_REG     ADC_CDR0;  // ADC Channel Data Register 0
-    AT91_REG     ADC_CDR1;  // ADC Channel Data Register 1
-    AT91_REG     ADC_CDR2;  // ADC Channel Data Register 2
-    AT91_REG     ADC_CDR3;  // ADC Channel Data Register 3
-    AT91_REG     ADC_CDR4;  // ADC Channel Data Register 4
-    AT91_REG     ADC_CDR5;  // ADC Channel Data Register 5
-    AT91_REG     ADC_CDR6;  // ADC Channel Data Register 6
-    AT91_REG     ADC_CDR7;  // ADC Channel Data Register 7
-    AT91_REG     Reserved1[44];     //
-    AT91_REG     ADC_RPR;   // Receive Pointer Register
-    AT91_REG     ADC_RCR;   // Receive Counter Register
-    AT91_REG     ADC_TPR;   // Transmit Pointer Register
-    AT91_REG     ADC_TCR;   // Transmit Counter Register
-    AT91_REG     ADC_RNPR;  // Receive Next Pointer Register
-    AT91_REG     ADC_RNCR;  // Receive Next Counter Register
-    AT91_REG     ADC_TNPR;  // Transmit Next Pointer Register
-    AT91_REG     ADC_TNCR;  // Transmit Next Counter Register
-    AT91_REG     ADC_PTCR;  // PDC Transfer Control Register
-    AT91_REG     ADC_PTSR;  // PDC Transfer Status Register
-} AT91S_ADC, *AT91PS_ADC;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor */
+/* ***************************************************************************** */
+typedef struct _AT91S_ADC
+{
+    AT91_REG ADC_CR;          /* ADC Control Register */
+    AT91_REG ADC_MR;          /* ADC Mode Register */
+    AT91_REG Reserved0[ 2 ];  /* */
+    AT91_REG ADC_CHER;        /* ADC Channel Enable Register */
+    AT91_REG ADC_CHDR;        /* ADC Channel Disable Register */
+    AT91_REG ADC_CHSR;        /* ADC Channel Status Register */
+    AT91_REG ADC_SR;          /* ADC Status Register */
+    AT91_REG ADC_LCDR;        /* ADC Last Converted Data Register */
+    AT91_REG ADC_IER;         /* ADC Interrupt Enable Register */
+    AT91_REG ADC_IDR;         /* ADC Interrupt Disable Register */
+    AT91_REG ADC_IMR;         /* ADC Interrupt Mask Register */
+    AT91_REG ADC_CDR0;        /* ADC Channel Data Register 0 */
+    AT91_REG ADC_CDR1;        /* ADC Channel Data Register 1 */
+    AT91_REG ADC_CDR2;        /* ADC Channel Data Register 2 */
+    AT91_REG ADC_CDR3;        /* ADC Channel Data Register 3 */
+    AT91_REG ADC_CDR4;        /* ADC Channel Data Register 4 */
+    AT91_REG ADC_CDR5;        /* ADC Channel Data Register 5 */
+    AT91_REG ADC_CDR6;        /* ADC Channel Data Register 6 */
+    AT91_REG ADC_CDR7;        /* ADC Channel Data Register 7 */
+    AT91_REG Reserved1[ 44 ]; /* */
+    AT91_REG ADC_RPR;         /* Receive Pointer Register */
+    AT91_REG ADC_RCR;         /* Receive Counter Register */
+    AT91_REG ADC_TPR;         /* Transmit Pointer Register */
+    AT91_REG ADC_TCR;         /* Transmit Counter Register */
+    AT91_REG ADC_RNPR;        /* Receive Next Pointer Register */
+    AT91_REG ADC_RNCR;        /* Receive Next Counter Register */
+    AT91_REG ADC_TNPR;        /* Transmit Next Pointer Register */
+    AT91_REG ADC_TNCR;        /* Transmit Next Counter Register */
+    AT91_REG ADC_PTCR;        /* PDC Transfer Control Register */
+    AT91_REG ADC_PTSR;        /* PDC Transfer Status Register */
+} AT91S_ADC, * AT91PS_ADC;
 
-// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
-#define AT91C_ADC_SWRST       ((unsigned int) 0x1 <<  0) // (ADC) Software Reset
-#define AT91C_ADC_START       ((unsigned int) 0x1 <<  1) // (ADC) Start Conversion
-// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
-#define AT91C_ADC_TRGEN       ((unsigned int) 0x1 <<  0) // (ADC) Trigger Enable
-#define     AT91C_ADC_TRGEN_DIS                  ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
-#define     AT91C_ADC_TRGEN_EN                   ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
-#define AT91C_ADC_TRGSEL      ((unsigned int) 0x7 <<  1) // (ADC) Trigger Selection
-#define     AT91C_ADC_TRGSEL_TIOA0                ((unsigned int) 0x0 <<  1) // (ADC) Selected TRGSEL = TIAO0
-#define     AT91C_ADC_TRGSEL_TIOA1                ((unsigned int) 0x1 <<  1) // (ADC) Selected TRGSEL = TIAO1
-#define     AT91C_ADC_TRGSEL_TIOA2                ((unsigned int) 0x2 <<  1) // (ADC) Selected TRGSEL = TIAO2
-#define     AT91C_ADC_TRGSEL_TIOA3                ((unsigned int) 0x3 <<  1) // (ADC) Selected TRGSEL = TIAO3
-#define     AT91C_ADC_TRGSEL_TIOA4                ((unsigned int) 0x4 <<  1) // (ADC) Selected TRGSEL = TIAO4
-#define     AT91C_ADC_TRGSEL_TIOA5                ((unsigned int) 0x5 <<  1) // (ADC) Selected TRGSEL = TIAO5
-#define     AT91C_ADC_TRGSEL_EXT                  ((unsigned int) 0x6 <<  1) // (ADC) Selected TRGSEL = External Trigger
-#define AT91C_ADC_LOWRES      ((unsigned int) 0x1 <<  4) // (ADC) Resolution.
-#define     AT91C_ADC_LOWRES_10_BIT               ((unsigned int) 0x0 <<  4) // (ADC) 10-bit resolution
-#define     AT91C_ADC_LOWRES_8_BIT                ((unsigned int) 0x1 <<  4) // (ADC) 8-bit resolution
-#define AT91C_ADC_SLEEP       ((unsigned int) 0x1 <<  5) // (ADC) Sleep Mode
-#define     AT91C_ADC_SLEEP_NORMAL_MODE          ((unsigned int) 0x0 <<  5) // (ADC) Normal Mode
-#define     AT91C_ADC_SLEEP_MODE                 ((unsigned int) 0x1 <<  5) // (ADC) Sleep Mode
-#define AT91C_ADC_PRESCAL     ((unsigned int) 0x3F <<  8) // (ADC) Prescaler rate selection
-#define AT91C_ADC_STARTUP     ((unsigned int) 0x1F << 16) // (ADC) Startup Time
-#define AT91C_ADC_SHTIM       ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time
-// --------     ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
-#define AT91C_ADC_CH0         ((unsigned int) 0x1 <<  0) // (ADC) Channel 0
-#define AT91C_ADC_CH1         ((unsigned int) 0x1 <<  1) // (ADC) Channel 1
-#define AT91C_ADC_CH2         ((unsigned int) 0x1 <<  2) // (ADC) Channel 2
-#define AT91C_ADC_CH3         ((unsigned int) 0x1 <<  3) // (ADC) Channel 3
-#define AT91C_ADC_CH4         ((unsigned int) 0x1 <<  4) // (ADC) Channel 4
-#define AT91C_ADC_CH5         ((unsigned int) 0x1 <<  5) // (ADC) Channel 5
-#define AT91C_ADC_CH6         ((unsigned int) 0x1 <<  6) // (ADC) Channel 6
-#define AT91C_ADC_CH7         ((unsigned int) 0x1 <<  7) // (ADC) Channel 7
-// --------     ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
-// --------     ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
-// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
-#define AT91C_ADC_EOC0        ((unsigned int) 0x1 <<  0) // (ADC) End of Conversion
-#define AT91C_ADC_EOC1        ((unsigned int) 0x1 <<  1) // (ADC) End of Conversion
-#define AT91C_ADC_EOC2        ((unsigned int) 0x1 <<  2) // (ADC) End of Conversion
-#define AT91C_ADC_EOC3        ((unsigned int) 0x1 <<  3) // (ADC) End of Conversion
-#define AT91C_ADC_EOC4        ((unsigned int) 0x1 <<  4) // (ADC) End of Conversion
-#define AT91C_ADC_EOC5        ((unsigned int) 0x1 <<  5) // (ADC) End of Conversion
-#define AT91C_ADC_EOC6        ((unsigned int) 0x1 <<  6) // (ADC) End of Conversion
-#define AT91C_ADC_EOC7        ((unsigned int) 0x1 <<  7) // (ADC) End of Conversion
-#define AT91C_ADC_OVRE0       ((unsigned int) 0x1 <<  8) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE1       ((unsigned int) 0x1 <<  9) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE2       ((unsigned int) 0x1 << 10) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE3       ((unsigned int) 0x1 << 11) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE4       ((unsigned int) 0x1 << 12) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE5       ((unsigned int) 0x1 << 13) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE6       ((unsigned int) 0x1 << 14) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE7       ((unsigned int) 0x1 << 15) // (ADC) Overrun Error
-#define AT91C_ADC_DRDY        ((unsigned int) 0x1 << 16) // (ADC) Data Ready
-#define AT91C_ADC_GOVRE       ((unsigned int) 0x1 << 17) // (ADC) General Overrun
-#define AT91C_ADC_ENDRX       ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer
-#define AT91C_ADC_RXBUFF      ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt
-// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
-#define AT91C_ADC_LDATA       ((unsigned int) 0x3FF <<  0) // (ADC) Last Data Converted
-// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
-// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
-// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
-// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
-#define AT91C_ADC_DATA        ((unsigned int) 0x3FF <<  0) // (ADC) Converted Data
-// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
-// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
-// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
-// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
-// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
-// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
-// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
+/* -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- */
+#define AT91C_ADC_SWRST                    ( ( unsigned int ) 0x1 << 0 )   /* (ADC) Software Reset */
+#define AT91C_ADC_START                    ( ( unsigned int ) 0x1 << 1 )   /* (ADC) Start Conversion */
+/* -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- */
+#define AT91C_ADC_TRGEN                    ( ( unsigned int ) 0x1 << 0 )   /* (ADC) Trigger Enable */
+#define     AT91C_ADC_TRGEN_DIS            ( ( unsigned int ) 0x0 )        /* (ADC) Hardware triggers are disabled. Starting a conversion is only possible by software */
+#define     AT91C_ADC_TRGEN_EN             ( ( unsigned int ) 0x1 )        /* (ADC) Hardware trigger selected by TRGSEL field is enabled. */
+#define AT91C_ADC_TRGSEL                   ( ( unsigned int ) 0x7 << 1 )   /* (ADC) Trigger Selection */
+#define     AT91C_ADC_TRGSEL_TIOA0         ( ( unsigned int ) 0x0 << 1 )   /* (ADC) Selected TRGSEL = TIAO0 */
+#define     AT91C_ADC_TRGSEL_TIOA1         ( ( unsigned int ) 0x1 << 1 )   /* (ADC) Selected TRGSEL = TIAO1 */
+#define     AT91C_ADC_TRGSEL_TIOA2         ( ( unsigned int ) 0x2 << 1 )   /* (ADC) Selected TRGSEL = TIAO2 */
+#define     AT91C_ADC_TRGSEL_TIOA3         ( ( unsigned int ) 0x3 << 1 )   /* (ADC) Selected TRGSEL = TIAO3 */
+#define     AT91C_ADC_TRGSEL_TIOA4         ( ( unsigned int ) 0x4 << 1 )   /* (ADC) Selected TRGSEL = TIAO4 */
+#define     AT91C_ADC_TRGSEL_TIOA5         ( ( unsigned int ) 0x5 << 1 )   /* (ADC) Selected TRGSEL = TIAO5 */
+#define     AT91C_ADC_TRGSEL_EXT           ( ( unsigned int ) 0x6 << 1 )   /* (ADC) Selected TRGSEL = External Trigger */
+#define AT91C_ADC_LOWRES                   ( ( unsigned int ) 0x1 << 4 )   /* (ADC) Resolution. */
+#define     AT91C_ADC_LOWRES_10_BIT        ( ( unsigned int ) 0x0 << 4 )   /* (ADC) 10-bit resolution */
+#define     AT91C_ADC_LOWRES_8_BIT         ( ( unsigned int ) 0x1 << 4 )   /* (ADC) 8-bit resolution */
+#define AT91C_ADC_SLEEP                    ( ( unsigned int ) 0x1 << 5 )   /* (ADC) Sleep Mode */
+#define     AT91C_ADC_SLEEP_NORMAL_MODE    ( ( unsigned int ) 0x0 << 5 )   /* (ADC) Normal Mode */
+#define     AT91C_ADC_SLEEP_MODE           ( ( unsigned int ) 0x1 << 5 )   /* (ADC) Sleep Mode */
+#define AT91C_ADC_PRESCAL                  ( ( unsigned int ) 0x3F << 8 )  /* (ADC) Prescaler rate selection */
+#define AT91C_ADC_STARTUP                  ( ( unsigned int ) 0x1F << 16 ) /* (ADC) Startup Time */
+#define AT91C_ADC_SHTIM                    ( ( unsigned int ) 0xF << 24 )  /* (ADC) Sample & Hold Time */
+/* --------     ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- */
+#define AT91C_ADC_CH0                      ( ( unsigned int ) 0x1 << 0 )   /* (ADC) Channel 0 */
+#define AT91C_ADC_CH1                      ( ( unsigned int ) 0x1 << 1 )   /* (ADC) Channel 1 */
+#define AT91C_ADC_CH2                      ( ( unsigned int ) 0x1 << 2 )   /* (ADC) Channel 2 */
+#define AT91C_ADC_CH3                      ( ( unsigned int ) 0x1 << 3 )   /* (ADC) Channel 3 */
+#define AT91C_ADC_CH4                      ( ( unsigned int ) 0x1 << 4 )   /* (ADC) Channel 4 */
+#define AT91C_ADC_CH5                      ( ( unsigned int ) 0x1 << 5 )   /* (ADC) Channel 5 */
+#define AT91C_ADC_CH6                      ( ( unsigned int ) 0x1 << 6 )   /* (ADC) Channel 6 */
+#define AT91C_ADC_CH7                      ( ( unsigned int ) 0x1 << 7 )   /* (ADC) Channel 7 */
+/* --------     ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- */
+/* --------     ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- */
+/* -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- */
+#define AT91C_ADC_EOC0      ( ( unsigned int ) 0x1 << 0 )   /* (ADC) End of Conversion */
+#define AT91C_ADC_EOC1      ( ( unsigned int ) 0x1 << 1 )   /* (ADC) End of Conversion */
+#define AT91C_ADC_EOC2      ( ( unsigned int ) 0x1 << 2 )   /* (ADC) End of Conversion */
+#define AT91C_ADC_EOC3      ( ( unsigned int ) 0x1 << 3 )   /* (ADC) End of Conversion */
+#define AT91C_ADC_EOC4      ( ( unsigned int ) 0x1 << 4 )   /* (ADC) End of Conversion */
+#define AT91C_ADC_EOC5      ( ( unsigned int ) 0x1 << 5 )   /* (ADC) End of Conversion */
+#define AT91C_ADC_EOC6      ( ( unsigned int ) 0x1 << 6 )   /* (ADC) End of Conversion */
+#define AT91C_ADC_EOC7      ( ( unsigned int ) 0x1 << 7 )   /* (ADC) End of Conversion */
+#define AT91C_ADC_OVRE0     ( ( unsigned int ) 0x1 << 8 )   /* (ADC) Overrun Error */
+#define AT91C_ADC_OVRE1     ( ( unsigned int ) 0x1 << 9 )   /* (ADC) Overrun Error */
+#define AT91C_ADC_OVRE2     ( ( unsigned int ) 0x1 << 10 )  /* (ADC) Overrun Error */
+#define AT91C_ADC_OVRE3     ( ( unsigned int ) 0x1 << 11 )  /* (ADC) Overrun Error */
+#define AT91C_ADC_OVRE4     ( ( unsigned int ) 0x1 << 12 )  /* (ADC) Overrun Error */
+#define AT91C_ADC_OVRE5     ( ( unsigned int ) 0x1 << 13 )  /* (ADC) Overrun Error */
+#define AT91C_ADC_OVRE6     ( ( unsigned int ) 0x1 << 14 )  /* (ADC) Overrun Error */
+#define AT91C_ADC_OVRE7     ( ( unsigned int ) 0x1 << 15 )  /* (ADC) Overrun Error */
+#define AT91C_ADC_DRDY      ( ( unsigned int ) 0x1 << 16 )  /* (ADC) Data Ready */
+#define AT91C_ADC_GOVRE     ( ( unsigned int ) 0x1 << 17 )  /* (ADC) General Overrun */
+#define AT91C_ADC_ENDRX     ( ( unsigned int ) 0x1 << 18 )  /* (ADC) End of Receiver Transfer */
+#define AT91C_ADC_RXBUFF    ( ( unsigned int ) 0x1 << 19 )  /* (ADC) RXBUFF Interrupt */
+/* -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- */
+#define AT91C_ADC_LDATA     ( ( unsigned int ) 0x3FF << 0 ) /* (ADC) Last Data Converted */
+/* -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- */
+/* -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- */
+/* -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- */
+/* -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- */
+#define AT91C_ADC_DATA    ( ( unsigned int ) 0x3FF << 0 )  /* (ADC) Converted Data */
+/* -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- */
+/* -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- */
+/* -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- */
+/* -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- */
+/* -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- */
+/* -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- */
+/* -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Advanced  Encryption Standard
-// *****************************************************************************
-typedef struct _AT91S_AES {
-    AT91_REG     AES_CR;    // Control Register
-    AT91_REG     AES_MR;    // Mode Register
-    AT91_REG     Reserved0[2];  //
-    AT91_REG     AES_IER;   // Interrupt Enable Register
-    AT91_REG     AES_IDR;   // Interrupt Disable Register
-    AT91_REG     AES_IMR;   // Interrupt Mask Register
-    AT91_REG     AES_ISR;   // Interrupt Status Register
-    AT91_REG     AES_KEYWxR[4];     // Key Word x Register
-    AT91_REG     Reserved1[4];  //
-    AT91_REG     AES_IDATAxR[4];    // Input Data x Register
-    AT91_REG     AES_ODATAxR[4];    // Output Data x Register
-    AT91_REG     AES_IVxR[4];   // Initialization Vector x Register
-    AT91_REG     Reserved2[35];     //
-    AT91_REG     AES_VR;    // AES Version Register
-    AT91_REG     AES_RPR;   // Receive Pointer Register
-    AT91_REG     AES_RCR;   // Receive Counter Register
-    AT91_REG     AES_TPR;   // Transmit Pointer Register
-    AT91_REG     AES_TCR;   // Transmit Counter Register
-    AT91_REG     AES_RNPR;  // Receive Next Pointer Register
-    AT91_REG     AES_RNCR;  // Receive Next Counter Register
-    AT91_REG     AES_TNPR;  // Transmit Next Pointer Register
-    AT91_REG     AES_TNCR;  // Transmit Next Counter Register
-    AT91_REG     AES_PTCR;  // PDC Transfer Control Register
-    AT91_REG     AES_PTSR;  // PDC Transfer Status Register
-} AT91S_AES, *AT91PS_AES;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Advanced  Encryption Standard */
+/* ***************************************************************************** */
+typedef struct _AT91S_AES
+{
+    AT91_REG AES_CR;           /* Control Register */
+    AT91_REG AES_MR;           /* Mode Register */
+    AT91_REG Reserved0[ 2 ];   /* */
+    AT91_REG AES_IER;          /* Interrupt Enable Register */
+    AT91_REG AES_IDR;          /* Interrupt Disable Register */
+    AT91_REG AES_IMR;          /* Interrupt Mask Register */
+    AT91_REG AES_ISR;          /* Interrupt Status Register */
+    AT91_REG AES_KEYWxR[ 4 ];  /* Key Word x Register */
+    AT91_REG Reserved1[ 4 ];   /* */
+    AT91_REG AES_IDATAxR[ 4 ]; /* Input Data x Register */
+    AT91_REG AES_ODATAxR[ 4 ]; /* Output Data x Register */
+    AT91_REG AES_IVxR[ 4 ];    /* Initialization Vector x Register */
+    AT91_REG Reserved2[ 35 ];  /* */
+    AT91_REG AES_VR;           /* AES Version Register */
+    AT91_REG AES_RPR;          /* Receive Pointer Register */
+    AT91_REG AES_RCR;          /* Receive Counter Register */
+    AT91_REG AES_TPR;          /* Transmit Pointer Register */
+    AT91_REG AES_TCR;          /* Transmit Counter Register */
+    AT91_REG AES_RNPR;         /* Receive Next Pointer Register */
+    AT91_REG AES_RNCR;         /* Receive Next Counter Register */
+    AT91_REG AES_TNPR;         /* Transmit Next Pointer Register */
+    AT91_REG AES_TNCR;         /* Transmit Next Counter Register */
+    AT91_REG AES_PTCR;         /* PDC Transfer Control Register */
+    AT91_REG AES_PTSR;         /* PDC Transfer Status Register */
+} AT91S_AES, * AT91PS_AES;
 
-// -------- AES_CR : (AES Offset: 0x0) Control Register --------
-#define AT91C_AES_START       ((unsigned int) 0x1 <<  0) // (AES) Starts Processing
-#define AT91C_AES_SWRST       ((unsigned int) 0x1 <<  8) // (AES) Software Reset
-#define AT91C_AES_LOADSEED    ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading
-// -------- AES_MR : (AES Offset: 0x4) Mode Register --------
-#define AT91C_AES_CIPHER      ((unsigned int) 0x1 <<  0) // (AES) Processing Mode
-#define AT91C_AES_PROCDLY     ((unsigned int) 0xF <<  4) // (AES) Processing Delay
-#define AT91C_AES_SMOD        ((unsigned int) 0x3 <<  8) // (AES) Start Mode
-#define     AT91C_AES_SMOD_MANUAL               ((unsigned int) 0x0 <<  8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.
-#define     AT91C_AES_SMOD_AUTO                 ((unsigned int) 0x1 <<  8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).
-#define     AT91C_AES_SMOD_PDC                  ((unsigned int) 0x2 <<  8) // (AES) PDC Mode (cf datasheet).
-#define AT91C_AES_OPMOD       ((unsigned int) 0x7 << 12) // (AES) Operation Mode
-#define     AT91C_AES_OPMOD_ECB                  ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode.
-#define     AT91C_AES_OPMOD_CBC                  ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode.
-#define     AT91C_AES_OPMOD_OFB                  ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode.
-#define     AT91C_AES_OPMOD_CFB                  ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode.
-#define     AT91C_AES_OPMOD_CTR                  ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode.
-#define AT91C_AES_LOD         ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode
-#define AT91C_AES_CFBS        ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size
-#define     AT91C_AES_CFBS_128_BIT              ((unsigned int) 0x0 << 16) // (AES) 128-bit.
-#define     AT91C_AES_CFBS_64_BIT               ((unsigned int) 0x1 << 16) // (AES) 64-bit.
-#define     AT91C_AES_CFBS_32_BIT               ((unsigned int) 0x2 << 16) // (AES) 32-bit.
-#define     AT91C_AES_CFBS_16_BIT               ((unsigned int) 0x3 << 16) // (AES) 16-bit.
-#define     AT91C_AES_CFBS_8_BIT                ((unsigned int) 0x4 << 16) // (AES) 8-bit.
-#define AT91C_AES_CKEY        ((unsigned int) 0xF << 20) // (AES) Countermeasure Key
-#define AT91C_AES_CTYPE       ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type
-#define     AT91C_AES_CTYPE_TYPE1_EN             ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled.
-#define     AT91C_AES_CTYPE_TYPE2_EN             ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled.
-#define     AT91C_AES_CTYPE_TYPE3_EN             ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled.
-#define     AT91C_AES_CTYPE_TYPE4_EN             ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled.
-#define     AT91C_AES_CTYPE_TYPE5_EN             ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled.
-// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register --------
-#define AT91C_AES_DATRDY      ((unsigned int) 0x1 <<  0) // (AES) DATRDY
-#define AT91C_AES_ENDRX       ((unsigned int) 0x1 <<  1) // (AES) PDC Read Buffer End
-#define AT91C_AES_ENDTX       ((unsigned int) 0x1 <<  2) // (AES) PDC Write Buffer End
-#define AT91C_AES_RXBUFF      ((unsigned int) 0x1 <<  3) // (AES) PDC Read Buffer Full
-#define AT91C_AES_TXBUFE      ((unsigned int) 0x1 <<  4) // (AES) PDC Write Buffer Empty
-#define AT91C_AES_URAD        ((unsigned int) 0x1 <<  8) // (AES) Unspecified Register Access Detection
-// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register --------
-// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register --------
-// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register --------
-#define AT91C_AES_URAT        ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status
-#define     AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode.
-#define     AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing.
-#define     AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing.
-#define     AT91C_AES_URAT_OUT_DAT_READ_SUBKEY  ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation.
-#define     AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation.
-#define     AT91C_AES_URAT_WO_REG_READ          ((unsigned int) 0x5 << 12) // (AES) Write-only register read access.
+/* -------- AES_CR : (AES Offset: 0x0) Control Register -------- */
+#define AT91C_AES_START                 ( ( unsigned int ) 0x1 << 0 )   /* (AES) Starts Processing */
+#define AT91C_AES_SWRST                 ( ( unsigned int ) 0x1 << 8 )   /* (AES) Software Reset */
+#define AT91C_AES_LOADSEED              ( ( unsigned int ) 0x1 << 16 )  /* (AES) Random Number Generator Seed Loading */
+/* -------- AES_MR : (AES Offset: 0x4) Mode Register -------- */
+#define AT91C_AES_CIPHER                ( ( unsigned int ) 0x1 << 0 )   /* (AES) Processing Mode */
+#define AT91C_AES_PROCDLY               ( ( unsigned int ) 0xF << 4 )   /* (AES) Processing Delay */
+#define AT91C_AES_SMOD                  ( ( unsigned int ) 0x3 << 8 )   /* (AES) Start Mode */
+#define     AT91C_AES_SMOD_MANUAL       ( ( unsigned int ) 0x0 << 8 )   /* (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. */
+#define     AT91C_AES_SMOD_AUTO         ( ( unsigned int ) 0x1 << 8 )   /* (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). */
+#define     AT91C_AES_SMOD_PDC          ( ( unsigned int ) 0x2 << 8 )   /* (AES) PDC Mode (cf datasheet). */
+#define AT91C_AES_OPMOD                 ( ( unsigned int ) 0x7 << 12 )  /* (AES) Operation Mode */
+#define     AT91C_AES_OPMOD_ECB         ( ( unsigned int ) 0x0 << 12 )  /* (AES) ECB Electronic CodeBook mode. */
+#define     AT91C_AES_OPMOD_CBC         ( ( unsigned int ) 0x1 << 12 )  /* (AES) CBC Cipher Block Chaining mode. */
+#define     AT91C_AES_OPMOD_OFB         ( ( unsigned int ) 0x2 << 12 )  /* (AES) OFB Output Feedback mode. */
+#define     AT91C_AES_OPMOD_CFB         ( ( unsigned int ) 0x3 << 12 )  /* (AES) CFB Cipher Feedback mode. */
+#define     AT91C_AES_OPMOD_CTR         ( ( unsigned int ) 0x4 << 12 )  /* (AES) CTR Counter mode. */
+#define AT91C_AES_LOD                   ( ( unsigned int ) 0x1 << 15 )  /* (AES) Last Output Data Mode */
+#define AT91C_AES_CFBS                  ( ( unsigned int ) 0x7 << 16 )  /* (AES) Cipher Feedback Data Size */
+#define     AT91C_AES_CFBS_128_BIT      ( ( unsigned int ) 0x0 << 16 )  /* (AES) 128-bit. */
+#define     AT91C_AES_CFBS_64_BIT       ( ( unsigned int ) 0x1 << 16 )  /* (AES) 64-bit. */
+#define     AT91C_AES_CFBS_32_BIT       ( ( unsigned int ) 0x2 << 16 )  /* (AES) 32-bit. */
+#define     AT91C_AES_CFBS_16_BIT       ( ( unsigned int ) 0x3 << 16 )  /* (AES) 16-bit. */
+#define     AT91C_AES_CFBS_8_BIT        ( ( unsigned int ) 0x4 << 16 )  /* (AES) 8-bit. */
+#define AT91C_AES_CKEY                  ( ( unsigned int ) 0xF << 20 )  /* (AES) Countermeasure Key */
+#define AT91C_AES_CTYPE                 ( ( unsigned int ) 0x1F << 24 ) /* (AES) Countermeasure Type */
+#define     AT91C_AES_CTYPE_TYPE1_EN    ( ( unsigned int ) 0x1 << 24 )  /* (AES) Countermeasure type 1 is enabled. */
+#define     AT91C_AES_CTYPE_TYPE2_EN    ( ( unsigned int ) 0x2 << 24 )  /* (AES) Countermeasure type 2 is enabled. */
+#define     AT91C_AES_CTYPE_TYPE3_EN    ( ( unsigned int ) 0x4 << 24 )  /* (AES) Countermeasure type 3 is enabled. */
+#define     AT91C_AES_CTYPE_TYPE4_EN    ( ( unsigned int ) 0x8 << 24 )  /* (AES) Countermeasure type 4 is enabled. */
+#define     AT91C_AES_CTYPE_TYPE5_EN    ( ( unsigned int ) 0x10 << 24 ) /* (AES) Countermeasure type 5 is enabled. */
+/* -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- */
+#define AT91C_AES_DATRDY                ( ( unsigned int ) 0x1 << 0 )   /* (AES) DATRDY */
+#define AT91C_AES_ENDRX                 ( ( unsigned int ) 0x1 << 1 )   /* (AES) PDC Read Buffer End */
+#define AT91C_AES_ENDTX                 ( ( unsigned int ) 0x1 << 2 )   /* (AES) PDC Write Buffer End */
+#define AT91C_AES_RXBUFF                ( ( unsigned int ) 0x1 << 3 )   /* (AES) PDC Read Buffer Full */
+#define AT91C_AES_TXBUFE                ( ( unsigned int ) 0x1 << 4 )   /* (AES) PDC Write Buffer Empty */
+#define AT91C_AES_URAD                  ( ( unsigned int ) 0x1 << 8 )   /* (AES) Unspecified Register Access Detection */
+/* -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- */
+/* -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- */
+/* -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- */
+#define AT91C_AES_URAT                              ( ( unsigned int ) 0x7 << 12 ) /* (AES) Unspecified Register Access Type Status */
+#define     AT91C_AES_URAT_IN_DAT_WRITE_DATPROC     ( ( unsigned int ) 0x0 << 12 ) /* (AES) Input data register written during the data processing in PDC mode. */
+#define     AT91C_AES_URAT_OUT_DAT_READ_DATPROC     ( ( unsigned int ) 0x1 << 12 ) /* (AES) Output data register read during the data processing. */
+#define     AT91C_AES_URAT_MODEREG_WRITE_DATPROC    ( ( unsigned int ) 0x2 << 12 ) /* (AES) Mode register written during the data processing. */
+#define     AT91C_AES_URAT_OUT_DAT_READ_SUBKEY      ( ( unsigned int ) 0x3 << 12 ) /* (AES) Output data register read during the sub-keys generation. */
+#define     AT91C_AES_URAT_MODEREG_WRITE_SUBKEY     ( ( unsigned int ) 0x4 << 12 ) /* (AES) Mode register written during the sub-keys generation. */
+#define     AT91C_AES_URAT_WO_REG_READ              ( ( unsigned int ) 0x5 << 12 ) /* (AES) Write-only register read access. */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Triple Data Encryption Standard
-// *****************************************************************************
-typedef struct _AT91S_TDES {
-    AT91_REG     TDES_CR;   // Control Register
-    AT91_REG     TDES_MR;   // Mode Register
-    AT91_REG     Reserved0[2];  //
-    AT91_REG     TDES_IER;  // Interrupt Enable Register
-    AT91_REG     TDES_IDR;  // Interrupt Disable Register
-    AT91_REG     TDES_IMR;  // Interrupt Mask Register
-    AT91_REG     TDES_ISR;  // Interrupt Status Register
-    AT91_REG     TDES_KEY1WxR[2];   // Key 1 Word x Register
-    AT91_REG     TDES_KEY2WxR[2];   // Key 2 Word x Register
-    AT91_REG     TDES_KEY3WxR[2];   // Key 3 Word x Register
-    AT91_REG     Reserved1[2];  //
-    AT91_REG     TDES_IDATAxR[2];   // Input Data x Register
-    AT91_REG     Reserved2[2];  //
-    AT91_REG     TDES_ODATAxR[2];   // Output Data x Register
-    AT91_REG     Reserved3[2];  //
-    AT91_REG     TDES_IVxR[2];  // Initialization Vector x Register
-    AT91_REG     Reserved4[37];     //
-    AT91_REG     TDES_VR;   // TDES Version Register
-    AT91_REG     TDES_RPR;  // Receive Pointer Register
-    AT91_REG     TDES_RCR;  // Receive Counter Register
-    AT91_REG     TDES_TPR;  // Transmit Pointer Register
-    AT91_REG     TDES_TCR;  // Transmit Counter Register
-    AT91_REG     TDES_RNPR;     // Receive Next Pointer Register
-    AT91_REG     TDES_RNCR;     // Receive Next Counter Register
-    AT91_REG     TDES_TNPR;     // Transmit Next Pointer Register
-    AT91_REG     TDES_TNCR;     // Transmit Next Counter Register
-    AT91_REG     TDES_PTCR;     // PDC Transfer Control Register
-    AT91_REG     TDES_PTSR;     // PDC Transfer Status Register
-} AT91S_TDES, *AT91PS_TDES;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Triple Data Encryption Standard */
+/* ***************************************************************************** */
+typedef struct _AT91S_TDES
+{
+    AT91_REG TDES_CR;           /* Control Register */
+    AT91_REG TDES_MR;           /* Mode Register */
+    AT91_REG Reserved0[ 2 ];    /* */
+    AT91_REG TDES_IER;          /* Interrupt Enable Register */
+    AT91_REG TDES_IDR;          /* Interrupt Disable Register */
+    AT91_REG TDES_IMR;          /* Interrupt Mask Register */
+    AT91_REG TDES_ISR;          /* Interrupt Status Register */
+    AT91_REG TDES_KEY1WxR[ 2 ]; /* Key 1 Word x Register */
+    AT91_REG TDES_KEY2WxR[ 2 ]; /* Key 2 Word x Register */
+    AT91_REG TDES_KEY3WxR[ 2 ]; /* Key 3 Word x Register */
+    AT91_REG Reserved1[ 2 ];    /* */
+    AT91_REG TDES_IDATAxR[ 2 ]; /* Input Data x Register */
+    AT91_REG Reserved2[ 2 ];    /* */
+    AT91_REG TDES_ODATAxR[ 2 ]; /* Output Data x Register */
+    AT91_REG Reserved3[ 2 ];    /* */
+    AT91_REG TDES_IVxR[ 2 ];    /* Initialization Vector x Register */
+    AT91_REG Reserved4[ 37 ];   /* */
+    AT91_REG TDES_VR;           /* TDES Version Register */
+    AT91_REG TDES_RPR;          /* Receive Pointer Register */
+    AT91_REG TDES_RCR;          /* Receive Counter Register */
+    AT91_REG TDES_TPR;          /* Transmit Pointer Register */
+    AT91_REG TDES_TCR;          /* Transmit Counter Register */
+    AT91_REG TDES_RNPR;         /* Receive Next Pointer Register */
+    AT91_REG TDES_RNCR;         /* Receive Next Counter Register */
+    AT91_REG TDES_TNPR;         /* Transmit Next Pointer Register */
+    AT91_REG TDES_TNCR;         /* Transmit Next Counter Register */
+    AT91_REG TDES_PTCR;         /* PDC Transfer Control Register */
+    AT91_REG TDES_PTSR;         /* PDC Transfer Status Register */
+} AT91S_TDES, * AT91PS_TDES;
 
-// -------- TDES_CR : (TDES Offset: 0x0) Control Register --------
-#define AT91C_TDES_START      ((unsigned int) 0x1 <<  0) // (TDES) Starts Processing
-#define AT91C_TDES_SWRST      ((unsigned int) 0x1 <<  8) // (TDES) Software Reset
-// -------- TDES_MR : (TDES Offset: 0x4) Mode Register --------
-#define AT91C_TDES_CIPHER     ((unsigned int) 0x1 <<  0) // (TDES) Processing Mode
-#define AT91C_TDES_TDESMOD    ((unsigned int) 0x1 <<  1) // (TDES) Single or Triple DES Mode
-#define AT91C_TDES_KEYMOD     ((unsigned int) 0x1 <<  4) // (TDES) Key Mode
-#define AT91C_TDES_SMOD       ((unsigned int) 0x3 <<  8) // (TDES) Start Mode
-#define     AT91C_TDES_SMOD_MANUAL               ((unsigned int) 0x0 <<  8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.
-#define     AT91C_TDES_SMOD_AUTO                 ((unsigned int) 0x1 <<  8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).
-#define     AT91C_TDES_SMOD_PDC                  ((unsigned int) 0x2 <<  8) // (TDES) PDC Mode (cf datasheet).
-#define AT91C_TDES_OPMOD      ((unsigned int) 0x3 << 12) // (TDES) Operation Mode
-#define     AT91C_TDES_OPMOD_ECB                  ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode.
-#define     AT91C_TDES_OPMOD_CBC                  ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode.
-#define     AT91C_TDES_OPMOD_OFB                  ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode.
-#define     AT91C_TDES_OPMOD_CFB                  ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode.
-#define AT91C_TDES_LOD        ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode
-#define AT91C_TDES_CFBS       ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size
-#define     AT91C_TDES_CFBS_64_BIT               ((unsigned int) 0x0 << 16) // (TDES) 64-bit.
-#define     AT91C_TDES_CFBS_32_BIT               ((unsigned int) 0x1 << 16) // (TDES) 32-bit.
-#define     AT91C_TDES_CFBS_16_BIT               ((unsigned int) 0x2 << 16) // (TDES) 16-bit.
-#define     AT91C_TDES_CFBS_8_BIT                ((unsigned int) 0x3 << 16) // (TDES) 8-bit.
-// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register --------
-#define AT91C_TDES_DATRDY     ((unsigned int) 0x1 <<  0) // (TDES) DATRDY
-#define AT91C_TDES_ENDRX      ((unsigned int) 0x1 <<  1) // (TDES) PDC Read Buffer End
-#define AT91C_TDES_ENDTX      ((unsigned int) 0x1 <<  2) // (TDES) PDC Write Buffer End
-#define AT91C_TDES_RXBUFF     ((unsigned int) 0x1 <<  3) // (TDES) PDC Read Buffer Full
-#define AT91C_TDES_TXBUFE     ((unsigned int) 0x1 <<  4) // (TDES) PDC Write Buffer Empty
-#define AT91C_TDES_URAD       ((unsigned int) 0x1 <<  8) // (TDES) Unspecified Register Access Detection
-// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register --------
-// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register --------
-// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register --------
-#define AT91C_TDES_URAT       ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status
-#define     AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode.
-#define     AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing.
-#define     AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing.
-#define     AT91C_TDES_URAT_WO_REG_READ          ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access.
+/* -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- */
+#define AT91C_TDES_START              ( ( unsigned int ) 0x1 << 0 )  /* (TDES) Starts Processing */
+#define AT91C_TDES_SWRST              ( ( unsigned int ) 0x1 << 8 )  /* (TDES) Software Reset */
+/* -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- */
+#define AT91C_TDES_CIPHER             ( ( unsigned int ) 0x1 << 0 )  /* (TDES) Processing Mode */
+#define AT91C_TDES_TDESMOD            ( ( unsigned int ) 0x1 << 1 )  /* (TDES) Single or Triple DES Mode */
+#define AT91C_TDES_KEYMOD             ( ( unsigned int ) 0x1 << 4 )  /* (TDES) Key Mode */
+#define AT91C_TDES_SMOD               ( ( unsigned int ) 0x3 << 8 )  /* (TDES) Start Mode */
+#define     AT91C_TDES_SMOD_MANUAL    ( ( unsigned int ) 0x0 << 8 )  /* (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. */
+#define     AT91C_TDES_SMOD_AUTO      ( ( unsigned int ) 0x1 << 8 )  /* (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). */
+#define     AT91C_TDES_SMOD_PDC       ( ( unsigned int ) 0x2 << 8 )  /* (TDES) PDC Mode (cf datasheet). */
+#define AT91C_TDES_OPMOD              ( ( unsigned int ) 0x3 << 12 ) /* (TDES) Operation Mode */
+#define     AT91C_TDES_OPMOD_ECB      ( ( unsigned int ) 0x0 << 12 ) /* (TDES) ECB Electronic CodeBook mode. */
+#define     AT91C_TDES_OPMOD_CBC      ( ( unsigned int ) 0x1 << 12 ) /* (TDES) CBC Cipher Block Chaining mode. */
+#define     AT91C_TDES_OPMOD_OFB      ( ( unsigned int ) 0x2 << 12 ) /* (TDES) OFB Output Feedback mode. */
+#define     AT91C_TDES_OPMOD_CFB      ( ( unsigned int ) 0x3 << 12 ) /* (TDES) CFB Cipher Feedback mode. */
+#define AT91C_TDES_LOD                ( ( unsigned int ) 0x1 << 15 ) /* (TDES) Last Output Data Mode */
+#define AT91C_TDES_CFBS               ( ( unsigned int ) 0x3 << 16 ) /* (TDES) Cipher Feedback Data Size */
+#define     AT91C_TDES_CFBS_64_BIT    ( ( unsigned int ) 0x0 << 16 ) /* (TDES) 64-bit. */
+#define     AT91C_TDES_CFBS_32_BIT    ( ( unsigned int ) 0x1 << 16 ) /* (TDES) 32-bit. */
+#define     AT91C_TDES_CFBS_16_BIT    ( ( unsigned int ) 0x2 << 16 ) /* (TDES) 16-bit. */
+#define     AT91C_TDES_CFBS_8_BIT     ( ( unsigned int ) 0x3 << 16 ) /* (TDES) 8-bit. */
+/* -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- */
+#define AT91C_TDES_DATRDY             ( ( unsigned int ) 0x1 << 0 )  /* (TDES) DATRDY */
+#define AT91C_TDES_ENDRX              ( ( unsigned int ) 0x1 << 1 )  /* (TDES) PDC Read Buffer End */
+#define AT91C_TDES_ENDTX              ( ( unsigned int ) 0x1 << 2 )  /* (TDES) PDC Write Buffer End */
+#define AT91C_TDES_RXBUFF             ( ( unsigned int ) 0x1 << 3 )  /* (TDES) PDC Read Buffer Full */
+#define AT91C_TDES_TXBUFE             ( ( unsigned int ) 0x1 << 4 )  /* (TDES) PDC Write Buffer Empty */
+#define AT91C_TDES_URAD               ( ( unsigned int ) 0x1 << 8 )  /* (TDES) Unspecified Register Access Detection */
+/* -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- */
+/* -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- */
+/* -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- */
+#define AT91C_TDES_URAT                              ( ( unsigned int ) 0x3 << 12 ) /* (TDES) Unspecified Register Access Type Status */
+#define     AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC     ( ( unsigned int ) 0x0 << 12 ) /* (TDES) Input data register written during the data processing in PDC mode. */
+#define     AT91C_TDES_URAT_OUT_DAT_READ_DATPROC     ( ( unsigned int ) 0x1 << 12 ) /* (TDES) Output data register read during the data processing. */
+#define     AT91C_TDES_URAT_MODEREG_WRITE_DATPROC    ( ( unsigned int ) 0x2 << 12 ) /* (TDES) Mode register written during the data processing. */
+#define     AT91C_TDES_URAT_WO_REG_READ              ( ( unsigned int ) 0x3 << 12 ) /* (TDES) Write-only register read access. */
 
-// *****************************************************************************
-//               REGISTER ADDRESS DEFINITION FOR AT91SAM7X128
-// *****************************************************************************
-// ========== Register definition for SYS peripheral ==========
-// ========== Register definition for AIC peripheral ==========
-#define AT91C_AIC_IVR   ((AT91_REG *)   0xFFFFF100) // (AIC) IRQ Vector Register
-#define AT91C_AIC_SMR   ((AT91_REG *)   0xFFFFF000) // (AIC) Source Mode Register
-#define AT91C_AIC_FVR   ((AT91_REG *)   0xFFFFF104) // (AIC) FIQ Vector Register
-#define AT91C_AIC_DCR   ((AT91_REG *)   0xFFFFF138) // (AIC) Debug Control Register (Protect)
-#define AT91C_AIC_EOICR ((AT91_REG *)   0xFFFFF130) // (AIC) End of Interrupt Command Register
-#define AT91C_AIC_SVR   ((AT91_REG *)   0xFFFFF080) // (AIC) Source Vector Register
-#define AT91C_AIC_FFSR  ((AT91_REG *)   0xFFFFF148) // (AIC) Fast Forcing Status Register
-#define AT91C_AIC_ICCR  ((AT91_REG *)   0xFFFFF128) // (AIC) Interrupt Clear Command Register
-#define AT91C_AIC_ISR   ((AT91_REG *)   0xFFFFF108) // (AIC) Interrupt Status Register
-#define AT91C_AIC_IMR   ((AT91_REG *)   0xFFFFF110) // (AIC) Interrupt Mask Register
-#define AT91C_AIC_IPR   ((AT91_REG *)   0xFFFFF10C) // (AIC) Interrupt Pending Register
-#define AT91C_AIC_FFER  ((AT91_REG *)   0xFFFFF140) // (AIC) Fast Forcing Enable Register
-#define AT91C_AIC_IECR  ((AT91_REG *)   0xFFFFF120) // (AIC) Interrupt Enable Command Register
-#define AT91C_AIC_ISCR  ((AT91_REG *)   0xFFFFF12C) // (AIC) Interrupt Set Command Register
-#define AT91C_AIC_FFDR  ((AT91_REG *)   0xFFFFF144) // (AIC) Fast Forcing Disable Register
-#define AT91C_AIC_CISR  ((AT91_REG *)   0xFFFFF114) // (AIC) Core Interrupt Status Register
-#define AT91C_AIC_IDCR  ((AT91_REG *)   0xFFFFF124) // (AIC) Interrupt Disable Command Register
-#define AT91C_AIC_SPU   ((AT91_REG *)   0xFFFFF134) // (AIC) Spurious Vector Register
-// ========== Register definition for PDC_DBGU peripheral ==========
-#define AT91C_DBGU_TCR  ((AT91_REG *)   0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
-#define AT91C_DBGU_RNPR ((AT91_REG *)   0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
-#define AT91C_DBGU_TNPR ((AT91_REG *)   0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
-#define AT91C_DBGU_TPR  ((AT91_REG *)   0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
-#define AT91C_DBGU_RPR  ((AT91_REG *)   0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
-#define AT91C_DBGU_RCR  ((AT91_REG *)   0xFFFFF304) // (PDC_DBGU) Receive Counter Register
-#define AT91C_DBGU_RNCR ((AT91_REG *)   0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
-#define AT91C_DBGU_PTCR ((AT91_REG *)   0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
-#define AT91C_DBGU_PTSR ((AT91_REG *)   0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
-#define AT91C_DBGU_TNCR ((AT91_REG *)   0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
-// ========== Register definition for DBGU peripheral ==========
-#define AT91C_DBGU_EXID ((AT91_REG *)   0xFFFFF244) // (DBGU) Chip ID Extension Register
-#define AT91C_DBGU_BRGR ((AT91_REG *)   0xFFFFF220) // (DBGU) Baud Rate Generator Register
-#define AT91C_DBGU_IDR  ((AT91_REG *)   0xFFFFF20C) // (DBGU) Interrupt Disable Register
-#define AT91C_DBGU_CSR  ((AT91_REG *)   0xFFFFF214) // (DBGU) Channel Status Register
-#define AT91C_DBGU_CIDR ((AT91_REG *)   0xFFFFF240) // (DBGU) Chip ID Register
-#define AT91C_DBGU_MR   ((AT91_REG *)   0xFFFFF204) // (DBGU) Mode Register
-#define AT91C_DBGU_IMR  ((AT91_REG *)   0xFFFFF210) // (DBGU) Interrupt Mask Register
-#define AT91C_DBGU_CR   ((AT91_REG *)   0xFFFFF200) // (DBGU) Control Register
-#define AT91C_DBGU_FNTR ((AT91_REG *)   0xFFFFF248) // (DBGU) Force NTRST Register
-#define AT91C_DBGU_THR  ((AT91_REG *)   0xFFFFF21C) // (DBGU) Transmitter Holding Register
-#define AT91C_DBGU_RHR  ((AT91_REG *)   0xFFFFF218) // (DBGU) Receiver Holding Register
-#define AT91C_DBGU_IER  ((AT91_REG *)   0xFFFFF208) // (DBGU) Interrupt Enable Register
-// ========== Register definition for PIOA peripheral ==========
-#define AT91C_PIOA_ODR  ((AT91_REG *)   0xFFFFF414) // (PIOA) Output Disable Registerr
-#define AT91C_PIOA_SODR ((AT91_REG *)   0xFFFFF430) // (PIOA) Set Output Data Register
-#define AT91C_PIOA_ISR  ((AT91_REG *)   0xFFFFF44C) // (PIOA) Interrupt Status Register
-#define AT91C_PIOA_ABSR ((AT91_REG *)   0xFFFFF478) // (PIOA) AB Select Status Register
-#define AT91C_PIOA_IER  ((AT91_REG *)   0xFFFFF440) // (PIOA) Interrupt Enable Register
-#define AT91C_PIOA_PPUDR ((AT91_REG *)  0xFFFFF460) // (PIOA) Pull-up Disable Register
-#define AT91C_PIOA_IMR  ((AT91_REG *)   0xFFFFF448) // (PIOA) Interrupt Mask Register
-#define AT91C_PIOA_PER  ((AT91_REG *)   0xFFFFF400) // (PIOA) PIO Enable Register
-#define AT91C_PIOA_IFDR ((AT91_REG *)   0xFFFFF424) // (PIOA) Input Filter Disable Register
-#define AT91C_PIOA_OWDR ((AT91_REG *)   0xFFFFF4A4) // (PIOA) Output Write Disable Register
-#define AT91C_PIOA_MDSR ((AT91_REG *)   0xFFFFF458) // (PIOA) Multi-driver Status Register
-#define AT91C_PIOA_IDR  ((AT91_REG *)   0xFFFFF444) // (PIOA) Interrupt Disable Register
-#define AT91C_PIOA_ODSR ((AT91_REG *)   0xFFFFF438) // (PIOA) Output Data Status Register
-#define AT91C_PIOA_PPUSR ((AT91_REG *)  0xFFFFF468) // (PIOA) Pull-up Status Register
-#define AT91C_PIOA_OWSR ((AT91_REG *)   0xFFFFF4A8) // (PIOA) Output Write Status Register
-#define AT91C_PIOA_BSR  ((AT91_REG *)   0xFFFFF474) // (PIOA) Select B Register
-#define AT91C_PIOA_OWER ((AT91_REG *)   0xFFFFF4A0) // (PIOA) Output Write Enable Register
-#define AT91C_PIOA_IFER ((AT91_REG *)   0xFFFFF420) // (PIOA) Input Filter Enable Register
-#define AT91C_PIOA_PDSR ((AT91_REG *)   0xFFFFF43C) // (PIOA) Pin Data Status Register
-#define AT91C_PIOA_PPUER ((AT91_REG *)  0xFFFFF464) // (PIOA) Pull-up Enable Register
-#define AT91C_PIOA_OSR  ((AT91_REG *)   0xFFFFF418) // (PIOA) Output Status Register
-#define AT91C_PIOA_ASR  ((AT91_REG *)   0xFFFFF470) // (PIOA) Select A Register
-#define AT91C_PIOA_MDDR ((AT91_REG *)   0xFFFFF454) // (PIOA) Multi-driver Disable Register
-#define AT91C_PIOA_CODR ((AT91_REG *)   0xFFFFF434) // (PIOA) Clear Output Data Register
-#define AT91C_PIOA_MDER ((AT91_REG *)   0xFFFFF450) // (PIOA) Multi-driver Enable Register
-#define AT91C_PIOA_PDR  ((AT91_REG *)   0xFFFFF404) // (PIOA) PIO Disable Register
-#define AT91C_PIOA_IFSR ((AT91_REG *)   0xFFFFF428) // (PIOA) Input Filter Status Register
-#define AT91C_PIOA_OER  ((AT91_REG *)   0xFFFFF410) // (PIOA) Output Enable Register
-#define AT91C_PIOA_PSR  ((AT91_REG *)   0xFFFFF408) // (PIOA) PIO Status Register
-// ========== Register definition for PIOB peripheral ==========
-#define AT91C_PIOB_OWDR ((AT91_REG *)   0xFFFFF6A4) // (PIOB) Output Write Disable Register
-#define AT91C_PIOB_MDER ((AT91_REG *)   0xFFFFF650) // (PIOB) Multi-driver Enable Register
-#define AT91C_PIOB_PPUSR ((AT91_REG *)  0xFFFFF668) // (PIOB) Pull-up Status Register
-#define AT91C_PIOB_IMR  ((AT91_REG *)   0xFFFFF648) // (PIOB) Interrupt Mask Register
-#define AT91C_PIOB_ASR  ((AT91_REG *)   0xFFFFF670) // (PIOB) Select A Register
-#define AT91C_PIOB_PPUDR ((AT91_REG *)  0xFFFFF660) // (PIOB) Pull-up Disable Register
-#define AT91C_PIOB_PSR  ((AT91_REG *)   0xFFFFF608) // (PIOB) PIO Status Register
-#define AT91C_PIOB_IER  ((AT91_REG *)   0xFFFFF640) // (PIOB) Interrupt Enable Register
-#define AT91C_PIOB_CODR ((AT91_REG *)   0xFFFFF634) // (PIOB) Clear Output Data Register
-#define AT91C_PIOB_OWER ((AT91_REG *)   0xFFFFF6A0) // (PIOB) Output Write Enable Register
-#define AT91C_PIOB_ABSR ((AT91_REG *)   0xFFFFF678) // (PIOB) AB Select Status Register
-#define AT91C_PIOB_IFDR ((AT91_REG *)   0xFFFFF624) // (PIOB) Input Filter Disable Register
-#define AT91C_PIOB_PDSR ((AT91_REG *)   0xFFFFF63C) // (PIOB) Pin Data Status Register
-#define AT91C_PIOB_IDR  ((AT91_REG *)   0xFFFFF644) // (PIOB) Interrupt Disable Register
-#define AT91C_PIOB_OWSR ((AT91_REG *)   0xFFFFF6A8) // (PIOB) Output Write Status Register
-#define AT91C_PIOB_PDR  ((AT91_REG *)   0xFFFFF604) // (PIOB) PIO Disable Register
-#define AT91C_PIOB_ODR  ((AT91_REG *)   0xFFFFF614) // (PIOB) Output Disable Registerr
-#define AT91C_PIOB_IFSR ((AT91_REG *)   0xFFFFF628) // (PIOB) Input Filter Status Register
-#define AT91C_PIOB_PPUER ((AT91_REG *)  0xFFFFF664) // (PIOB) Pull-up Enable Register
-#define AT91C_PIOB_SODR ((AT91_REG *)   0xFFFFF630) // (PIOB) Set Output Data Register
-#define AT91C_PIOB_ISR  ((AT91_REG *)   0xFFFFF64C) // (PIOB) Interrupt Status Register
-#define AT91C_PIOB_ODSR ((AT91_REG *)   0xFFFFF638) // (PIOB) Output Data Status Register
-#define AT91C_PIOB_OSR  ((AT91_REG *)   0xFFFFF618) // (PIOB) Output Status Register
-#define AT91C_PIOB_MDSR ((AT91_REG *)   0xFFFFF658) // (PIOB) Multi-driver Status Register
-#define AT91C_PIOB_IFER ((AT91_REG *)   0xFFFFF620) // (PIOB) Input Filter Enable Register
-#define AT91C_PIOB_BSR  ((AT91_REG *)   0xFFFFF674) // (PIOB) Select B Register
-#define AT91C_PIOB_MDDR ((AT91_REG *)   0xFFFFF654) // (PIOB) Multi-driver Disable Register
-#define AT91C_PIOB_OER  ((AT91_REG *)   0xFFFFF610) // (PIOB) Output Enable Register
-#define AT91C_PIOB_PER  ((AT91_REG *)   0xFFFFF600) // (PIOB) PIO Enable Register
-// ========== Register definition for CKGR peripheral ==========
-#define AT91C_CKGR_MOR  ((AT91_REG *)   0xFFFFFC20) // (CKGR) Main Oscillator Register
-#define AT91C_CKGR_PLLR ((AT91_REG *)   0xFFFFFC2C) // (CKGR) PLL Register
-#define AT91C_CKGR_MCFR ((AT91_REG *)   0xFFFFFC24) // (CKGR) Main Clock  Frequency Register
-// ========== Register definition for PMC peripheral ==========
-#define AT91C_PMC_IDR   ((AT91_REG *)   0xFFFFFC64) // (PMC) Interrupt Disable Register
-#define AT91C_PMC_MOR   ((AT91_REG *)   0xFFFFFC20) // (PMC) Main Oscillator Register
-#define AT91C_PMC_PLLR  ((AT91_REG *)   0xFFFFFC2C) // (PMC) PLL Register
-#define AT91C_PMC_PCER  ((AT91_REG *)   0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
-#define AT91C_PMC_PCKR  ((AT91_REG *)   0xFFFFFC40) // (PMC) Programmable Clock Register
-#define AT91C_PMC_MCKR  ((AT91_REG *)   0xFFFFFC30) // (PMC) Master Clock Register
-#define AT91C_PMC_SCDR  ((AT91_REG *)   0xFFFFFC04) // (PMC) System Clock Disable Register
-#define AT91C_PMC_PCDR  ((AT91_REG *)   0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
-#define AT91C_PMC_SCSR  ((AT91_REG *)   0xFFFFFC08) // (PMC) System Clock Status Register
-#define AT91C_PMC_PCSR  ((AT91_REG *)   0xFFFFFC18) // (PMC) Peripheral Clock Status Register
-#define AT91C_PMC_MCFR  ((AT91_REG *)   0xFFFFFC24) // (PMC) Main Clock  Frequency Register
-#define AT91C_PMC_SCER  ((AT91_REG *)   0xFFFFFC00) // (PMC) System Clock Enable Register
-#define AT91C_PMC_IMR   ((AT91_REG *)   0xFFFFFC6C) // (PMC) Interrupt Mask Register
-#define AT91C_PMC_IER   ((AT91_REG *)   0xFFFFFC60) // (PMC) Interrupt Enable Register
-#define AT91C_PMC_SR    ((AT91_REG *)   0xFFFFFC68) // (PMC) Status Register
-// ========== Register definition for RSTC peripheral ==========
-#define AT91C_RSTC_RCR  ((AT91_REG *)   0xFFFFFD00) // (RSTC) Reset Control Register
-#define AT91C_RSTC_RMR  ((AT91_REG *)   0xFFFFFD08) // (RSTC) Reset Mode Register
-#define AT91C_RSTC_RSR  ((AT91_REG *)   0xFFFFFD04) // (RSTC) Reset Status Register
-// ========== Register definition for RTTC peripheral ==========
-#define AT91C_RTTC_RTSR ((AT91_REG *)   0xFFFFFD2C) // (RTTC) Real-time Status Register
-#define AT91C_RTTC_RTMR ((AT91_REG *)   0xFFFFFD20) // (RTTC) Real-time Mode Register
-#define AT91C_RTTC_RTVR ((AT91_REG *)   0xFFFFFD28) // (RTTC) Real-time Value Register
-#define AT91C_RTTC_RTAR ((AT91_REG *)   0xFFFFFD24) // (RTTC) Real-time Alarm Register
-// ========== Register definition for PITC peripheral ==========
-#define AT91C_PITC_PIVR ((AT91_REG *)   0xFFFFFD38) // (PITC) Period Interval Value Register
-#define AT91C_PITC_PISR ((AT91_REG *)   0xFFFFFD34) // (PITC) Period Interval Status Register
-#define AT91C_PITC_PIIR ((AT91_REG *)   0xFFFFFD3C) // (PITC) Period Interval Image Register
-#define AT91C_PITC_PIMR ((AT91_REG *)   0xFFFFFD30) // (PITC) Period Interval Mode Register
-// ========== Register definition for WDTC peripheral ==========
-#define AT91C_WDTC_WDCR ((AT91_REG *)   0xFFFFFD40) // (WDTC) Watchdog Control Register
-#define AT91C_WDTC_WDSR ((AT91_REG *)   0xFFFFFD48) // (WDTC) Watchdog Status Register
-#define AT91C_WDTC_WDMR ((AT91_REG *)   0xFFFFFD44) // (WDTC) Watchdog Mode Register
-// ========== Register definition for VREG peripheral ==========
-#define AT91C_VREG_MR   ((AT91_REG *)   0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
-// ========== Register definition for MC peripheral ==========
-#define AT91C_MC_ASR    ((AT91_REG *)   0xFFFFFF04) // (MC) MC Abort Status Register
-#define AT91C_MC_RCR    ((AT91_REG *)   0xFFFFFF00) // (MC) MC Remap Control Register
-#define AT91C_MC_FCR    ((AT91_REG *)   0xFFFFFF64) // (MC) MC Flash Command Register
-#define AT91C_MC_AASR   ((AT91_REG *)   0xFFFFFF08) // (MC) MC Abort Address Status Register
-#define AT91C_MC_FSR    ((AT91_REG *)   0xFFFFFF68) // (MC) MC Flash Status Register
-#define AT91C_MC_FMR    ((AT91_REG *)   0xFFFFFF60) // (MC) MC Flash Mode Register
-// ========== Register definition for PDC_SPI1 peripheral ==========
-#define AT91C_SPI1_PTCR ((AT91_REG *)   0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register
-#define AT91C_SPI1_RPR  ((AT91_REG *)   0xFFFE4100) // (PDC_SPI1) Receive Pointer Register
-#define AT91C_SPI1_TNCR ((AT91_REG *)   0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register
-#define AT91C_SPI1_TPR  ((AT91_REG *)   0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register
-#define AT91C_SPI1_TNPR ((AT91_REG *)   0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register
-#define AT91C_SPI1_TCR  ((AT91_REG *)   0xFFFE410C) // (PDC_SPI1) Transmit Counter Register
-#define AT91C_SPI1_RCR  ((AT91_REG *)   0xFFFE4104) // (PDC_SPI1) Receive Counter Register
-#define AT91C_SPI1_RNPR ((AT91_REG *)   0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register
-#define AT91C_SPI1_RNCR ((AT91_REG *)   0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register
-#define AT91C_SPI1_PTSR ((AT91_REG *)   0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register
-// ========== Register definition for SPI1 peripheral ==========
-#define AT91C_SPI1_IMR  ((AT91_REG *)   0xFFFE401C) // (SPI1) Interrupt Mask Register
-#define AT91C_SPI1_IER  ((AT91_REG *)   0xFFFE4014) // (SPI1) Interrupt Enable Register
-#define AT91C_SPI1_MR   ((AT91_REG *)   0xFFFE4004) // (SPI1) Mode Register
-#define AT91C_SPI1_RDR  ((AT91_REG *)   0xFFFE4008) // (SPI1) Receive Data Register
-#define AT91C_SPI1_IDR  ((AT91_REG *)   0xFFFE4018) // (SPI1) Interrupt Disable Register
-#define AT91C_SPI1_SR   ((AT91_REG *)   0xFFFE4010) // (SPI1) Status Register
-#define AT91C_SPI1_TDR  ((AT91_REG *)   0xFFFE400C) // (SPI1) Transmit Data Register
-#define AT91C_SPI1_CR   ((AT91_REG *)   0xFFFE4000) // (SPI1) Control Register
-#define AT91C_SPI1_CSR  ((AT91_REG *)   0xFFFE4030) // (SPI1) Chip Select Register
-// ========== Register definition for PDC_SPI0 peripheral ==========
-#define AT91C_SPI0_PTCR ((AT91_REG *)   0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register
-#define AT91C_SPI0_TPR  ((AT91_REG *)   0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register
-#define AT91C_SPI0_TCR  ((AT91_REG *)   0xFFFE010C) // (PDC_SPI0) Transmit Counter Register
-#define AT91C_SPI0_RCR  ((AT91_REG *)   0xFFFE0104) // (PDC_SPI0) Receive Counter Register
-#define AT91C_SPI0_PTSR ((AT91_REG *)   0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register
-#define AT91C_SPI0_RNPR ((AT91_REG *)   0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register
-#define AT91C_SPI0_RPR  ((AT91_REG *)   0xFFFE0100) // (PDC_SPI0) Receive Pointer Register
-#define AT91C_SPI0_TNCR ((AT91_REG *)   0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register
-#define AT91C_SPI0_RNCR ((AT91_REG *)   0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register
-#define AT91C_SPI0_TNPR ((AT91_REG *)   0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register
-// ========== Register definition for SPI0 peripheral ==========
-#define AT91C_SPI0_IER  ((AT91_REG *)   0xFFFE0014) // (SPI0) Interrupt Enable Register
-#define AT91C_SPI0_SR   ((AT91_REG *)   0xFFFE0010) // (SPI0) Status Register
-#define AT91C_SPI0_IDR  ((AT91_REG *)   0xFFFE0018) // (SPI0) Interrupt Disable Register
-#define AT91C_SPI0_CR   ((AT91_REG *)   0xFFFE0000) // (SPI0) Control Register
-#define AT91C_SPI0_MR   ((AT91_REG *)   0xFFFE0004) // (SPI0) Mode Register
-#define AT91C_SPI0_IMR  ((AT91_REG *)   0xFFFE001C) // (SPI0) Interrupt Mask Register
-#define AT91C_SPI0_TDR  ((AT91_REG *)   0xFFFE000C) // (SPI0) Transmit Data Register
-#define AT91C_SPI0_RDR  ((AT91_REG *)   0xFFFE0008) // (SPI0) Receive Data Register
-#define AT91C_SPI0_CSR  ((AT91_REG *)   0xFFFE0030) // (SPI0) Chip Select Register
-// ========== Register definition for PDC_US1 peripheral ==========
-#define AT91C_US1_RNCR  ((AT91_REG *)   0xFFFC4114) // (PDC_US1) Receive Next Counter Register
-#define AT91C_US1_PTCR  ((AT91_REG *)   0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
-#define AT91C_US1_TCR   ((AT91_REG *)   0xFFFC410C) // (PDC_US1) Transmit Counter Register
-#define AT91C_US1_PTSR  ((AT91_REG *)   0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
-#define AT91C_US1_TNPR  ((AT91_REG *)   0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
-#define AT91C_US1_RCR   ((AT91_REG *)   0xFFFC4104) // (PDC_US1) Receive Counter Register
-#define AT91C_US1_RNPR  ((AT91_REG *)   0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
-#define AT91C_US1_RPR   ((AT91_REG *)   0xFFFC4100) // (PDC_US1) Receive Pointer Register
-#define AT91C_US1_TNCR  ((AT91_REG *)   0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
-#define AT91C_US1_TPR   ((AT91_REG *)   0xFFFC4108) // (PDC_US1) Transmit Pointer Register
-// ========== Register definition for US1 peripheral ==========
-#define AT91C_US1_IF    ((AT91_REG *)   0xFFFC404C) // (US1) IRDA_FILTER Register
-#define AT91C_US1_NER   ((AT91_REG *)   0xFFFC4044) // (US1) Nb Errors Register
-#define AT91C_US1_RTOR  ((AT91_REG *)   0xFFFC4024) // (US1) Receiver Time-out Register
-#define AT91C_US1_CSR   ((AT91_REG *)   0xFFFC4014) // (US1) Channel Status Register
-#define AT91C_US1_IDR   ((AT91_REG *)   0xFFFC400C) // (US1) Interrupt Disable Register
-#define AT91C_US1_IER   ((AT91_REG *)   0xFFFC4008) // (US1) Interrupt Enable Register
-#define AT91C_US1_THR   ((AT91_REG *)   0xFFFC401C) // (US1) Transmitter Holding Register
-#define AT91C_US1_TTGR  ((AT91_REG *)   0xFFFC4028) // (US1) Transmitter Time-guard Register
-#define AT91C_US1_RHR   ((AT91_REG *)   0xFFFC4018) // (US1) Receiver Holding Register
-#define AT91C_US1_BRGR  ((AT91_REG *)   0xFFFC4020) // (US1) Baud Rate Generator Register
-#define AT91C_US1_IMR   ((AT91_REG *)   0xFFFC4010) // (US1) Interrupt Mask Register
-#define AT91C_US1_FIDI  ((AT91_REG *)   0xFFFC4040) // (US1) FI_DI_Ratio Register
-#define AT91C_US1_CR    ((AT91_REG *)   0xFFFC4000) // (US1) Control Register
-#define AT91C_US1_MR    ((AT91_REG *)   0xFFFC4004) // (US1) Mode Register
-// ========== Register definition for PDC_US0 peripheral ==========
-#define AT91C_US0_TNPR  ((AT91_REG *)   0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
-#define AT91C_US0_RNPR  ((AT91_REG *)   0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
-#define AT91C_US0_TCR   ((AT91_REG *)   0xFFFC010C) // (PDC_US0) Transmit Counter Register
-#define AT91C_US0_PTCR  ((AT91_REG *)   0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
-#define AT91C_US0_PTSR  ((AT91_REG *)   0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
-#define AT91C_US0_TNCR  ((AT91_REG *)   0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
-#define AT91C_US0_TPR   ((AT91_REG *)   0xFFFC0108) // (PDC_US0) Transmit Pointer Register
-#define AT91C_US0_RCR   ((AT91_REG *)   0xFFFC0104) // (PDC_US0) Receive Counter Register
-#define AT91C_US0_RPR   ((AT91_REG *)   0xFFFC0100) // (PDC_US0) Receive Pointer Register
-#define AT91C_US0_RNCR  ((AT91_REG *)   0xFFFC0114) // (PDC_US0) Receive Next Counter Register
-// ========== Register definition for US0 peripheral ==========
-#define AT91C_US0_BRGR  ((AT91_REG *)   0xFFFC0020) // (US0) Baud Rate Generator Register
-#define AT91C_US0_NER   ((AT91_REG *)   0xFFFC0044) // (US0) Nb Errors Register
-#define AT91C_US0_CR    ((AT91_REG *)   0xFFFC0000) // (US0) Control Register
-#define AT91C_US0_IMR   ((AT91_REG *)   0xFFFC0010) // (US0) Interrupt Mask Register
-#define AT91C_US0_FIDI  ((AT91_REG *)   0xFFFC0040) // (US0) FI_DI_Ratio Register
-#define AT91C_US0_TTGR  ((AT91_REG *)   0xFFFC0028) // (US0) Transmitter Time-guard Register
-#define AT91C_US0_MR    ((AT91_REG *)   0xFFFC0004) // (US0) Mode Register
-#define AT91C_US0_RTOR  ((AT91_REG *)   0xFFFC0024) // (US0) Receiver Time-out Register
-#define AT91C_US0_CSR   ((AT91_REG *)   0xFFFC0014) // (US0) Channel Status Register
-#define AT91C_US0_RHR   ((AT91_REG *)   0xFFFC0018) // (US0) Receiver Holding Register
-#define AT91C_US0_IDR   ((AT91_REG *)   0xFFFC000C) // (US0) Interrupt Disable Register
-#define AT91C_US0_THR   ((AT91_REG *)   0xFFFC001C) // (US0) Transmitter Holding Register
-#define AT91C_US0_IF    ((AT91_REG *)   0xFFFC004C) // (US0) IRDA_FILTER Register
-#define AT91C_US0_IER   ((AT91_REG *)   0xFFFC0008) // (US0) Interrupt Enable Register
-// ========== Register definition for PDC_SSC peripheral ==========
-#define AT91C_SSC_TNCR  ((AT91_REG *)   0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
-#define AT91C_SSC_RPR   ((AT91_REG *)   0xFFFD4100) // (PDC_SSC) Receive Pointer Register
-#define AT91C_SSC_RNCR  ((AT91_REG *)   0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
-#define AT91C_SSC_TPR   ((AT91_REG *)   0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
-#define AT91C_SSC_PTCR  ((AT91_REG *)   0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
-#define AT91C_SSC_TCR   ((AT91_REG *)   0xFFFD410C) // (PDC_SSC) Transmit Counter Register
-#define AT91C_SSC_RCR   ((AT91_REG *)   0xFFFD4104) // (PDC_SSC) Receive Counter Register
-#define AT91C_SSC_RNPR  ((AT91_REG *)   0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
-#define AT91C_SSC_TNPR  ((AT91_REG *)   0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
-#define AT91C_SSC_PTSR  ((AT91_REG *)   0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
-// ========== Register definition for SSC peripheral ==========
-#define AT91C_SSC_RHR   ((AT91_REG *)   0xFFFD4020) // (SSC) Receive Holding Register
-#define AT91C_SSC_RSHR  ((AT91_REG *)   0xFFFD4030) // (SSC) Receive Sync Holding Register
-#define AT91C_SSC_TFMR  ((AT91_REG *)   0xFFFD401C) // (SSC) Transmit Frame Mode Register
-#define AT91C_SSC_IDR   ((AT91_REG *)   0xFFFD4048) // (SSC) Interrupt Disable Register
-#define AT91C_SSC_THR   ((AT91_REG *)   0xFFFD4024) // (SSC) Transmit Holding Register
-#define AT91C_SSC_RCMR  ((AT91_REG *)   0xFFFD4010) // (SSC) Receive Clock ModeRegister
-#define AT91C_SSC_IER   ((AT91_REG *)   0xFFFD4044) // (SSC) Interrupt Enable Register
-#define AT91C_SSC_TSHR  ((AT91_REG *)   0xFFFD4034) // (SSC) Transmit Sync Holding Register
-#define AT91C_SSC_SR    ((AT91_REG *)   0xFFFD4040) // (SSC) Status Register
-#define AT91C_SSC_CMR   ((AT91_REG *)   0xFFFD4004) // (SSC) Clock Mode Register
-#define AT91C_SSC_TCMR  ((AT91_REG *)   0xFFFD4018) // (SSC) Transmit Clock Mode Register
-#define AT91C_SSC_CR    ((AT91_REG *)   0xFFFD4000) // (SSC) Control Register
-#define AT91C_SSC_IMR   ((AT91_REG *)   0xFFFD404C) // (SSC) Interrupt Mask Register
-#define AT91C_SSC_RFMR  ((AT91_REG *)   0xFFFD4014) // (SSC) Receive Frame Mode Register
-// ========== Register definition for TWI peripheral ==========
-#define AT91C_TWI_IER   ((AT91_REG *)   0xFFFB8024) // (TWI) Interrupt Enable Register
-#define AT91C_TWI_CR    ((AT91_REG *)   0xFFFB8000) // (TWI) Control Register
-#define AT91C_TWI_SR    ((AT91_REG *)   0xFFFB8020) // (TWI) Status Register
-#define AT91C_TWI_IMR   ((AT91_REG *)   0xFFFB802C) // (TWI) Interrupt Mask Register
-#define AT91C_TWI_THR   ((AT91_REG *)   0xFFFB8034) // (TWI) Transmit Holding Register
-#define AT91C_TWI_IDR   ((AT91_REG *)   0xFFFB8028) // (TWI) Interrupt Disable Register
-#define AT91C_TWI_IADR  ((AT91_REG *)   0xFFFB800C) // (TWI) Internal Address Register
-#define AT91C_TWI_MMR   ((AT91_REG *)   0xFFFB8004) // (TWI) Master Mode Register
-#define AT91C_TWI_CWGR  ((AT91_REG *)   0xFFFB8010) // (TWI) Clock Waveform Generator Register
-#define AT91C_TWI_RHR   ((AT91_REG *)   0xFFFB8030) // (TWI) Receive Holding Register
-// ========== Register definition for PWMC_CH3 peripheral ==========
-#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *)  0xFFFCC270) // (PWMC_CH3) Channel Update Register
-#define AT91C_PWMC_CH3_Reserved ((AT91_REG *)   0xFFFCC274) // (PWMC_CH3) Reserved
-#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *)  0xFFFCC268) // (PWMC_CH3) Channel Period Register
-#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *)  0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
-#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *)  0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
-#define AT91C_PWMC_CH3_CMR ((AT91_REG *)    0xFFFCC260) // (PWMC_CH3) Channel Mode Register
-// ========== Register definition for PWMC_CH2 peripheral ==========
-#define AT91C_PWMC_CH2_Reserved ((AT91_REG *)   0xFFFCC254) // (PWMC_CH2) Reserved
-#define AT91C_PWMC_CH2_CMR ((AT91_REG *)    0xFFFCC240) // (PWMC_CH2) Channel Mode Register
-#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *)  0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
-#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *)  0xFFFCC248) // (PWMC_CH2) Channel Period Register
-#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *)  0xFFFCC250) // (PWMC_CH2) Channel Update Register
-#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *)  0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
-// ========== Register definition for PWMC_CH1 peripheral ==========
-#define AT91C_PWMC_CH1_Reserved ((AT91_REG *)   0xFFFCC234) // (PWMC_CH1) Reserved
-#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *)  0xFFFCC230) // (PWMC_CH1) Channel Update Register
-#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *)  0xFFFCC228) // (PWMC_CH1) Channel Period Register
-#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *)  0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
-#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *)  0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
-#define AT91C_PWMC_CH1_CMR ((AT91_REG *)    0xFFFCC220) // (PWMC_CH1) Channel Mode Register
-// ========== Register definition for PWMC_CH0 peripheral ==========
-#define AT91C_PWMC_CH0_Reserved ((AT91_REG *)   0xFFFCC214) // (PWMC_CH0) Reserved
-#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *)  0xFFFCC208) // (PWMC_CH0) Channel Period Register
-#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *)  0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
-#define AT91C_PWMC_CH0_CMR ((AT91_REG *)    0xFFFCC200) // (PWMC_CH0) Channel Mode Register
-#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *)  0xFFFCC210) // (PWMC_CH0) Channel Update Register
-#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *)  0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
-// ========== Register definition for PWMC peripheral ==========
-#define AT91C_PWMC_IDR  ((AT91_REG *)   0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
-#define AT91C_PWMC_DIS  ((AT91_REG *)   0xFFFCC008) // (PWMC) PWMC Disable Register
-#define AT91C_PWMC_IER  ((AT91_REG *)   0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
-#define AT91C_PWMC_VR   ((AT91_REG *)   0xFFFCC0FC) // (PWMC) PWMC Version Register
-#define AT91C_PWMC_ISR  ((AT91_REG *)   0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
-#define AT91C_PWMC_SR   ((AT91_REG *)   0xFFFCC00C) // (PWMC) PWMC Status Register
-#define AT91C_PWMC_IMR  ((AT91_REG *)   0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
-#define AT91C_PWMC_MR   ((AT91_REG *)   0xFFFCC000) // (PWMC) PWMC Mode Register
-#define AT91C_PWMC_ENA  ((AT91_REG *)   0xFFFCC004) // (PWMC) PWMC Enable Register
-// ========== Register definition for UDP peripheral ==========
-#define AT91C_UDP_IMR   ((AT91_REG *)   0xFFFB0018) // (UDP) Interrupt Mask Register
-#define AT91C_UDP_FADDR ((AT91_REG *)   0xFFFB0008) // (UDP) Function Address Register
-#define AT91C_UDP_NUM   ((AT91_REG *)   0xFFFB0000) // (UDP) Frame Number Register
-#define AT91C_UDP_FDR   ((AT91_REG *)   0xFFFB0050) // (UDP) Endpoint FIFO Data Register
-#define AT91C_UDP_ISR   ((AT91_REG *)   0xFFFB001C) // (UDP) Interrupt Status Register
-#define AT91C_UDP_CSR   ((AT91_REG *)   0xFFFB0030) // (UDP) Endpoint Control and Status Register
-#define AT91C_UDP_IDR   ((AT91_REG *)   0xFFFB0014) // (UDP) Interrupt Disable Register
-#define AT91C_UDP_ICR   ((AT91_REG *)   0xFFFB0020) // (UDP) Interrupt Clear Register
-#define AT91C_UDP_RSTEP ((AT91_REG *)   0xFFFB0028) // (UDP) Reset Endpoint Register
-#define AT91C_UDP_TXVC  ((AT91_REG *)   0xFFFB0074) // (UDP) Transceiver Control Register
-#define AT91C_UDP_GLBSTATE ((AT91_REG *)    0xFFFB0004) // (UDP) Global State Register
-#define AT91C_UDP_IER   ((AT91_REG *)   0xFFFB0010) // (UDP) Interrupt Enable Register
-// ========== Register definition for TC0 peripheral ==========
-#define AT91C_TC0_SR    ((AT91_REG *)   0xFFFA0020) // (TC0) Status Register
-#define AT91C_TC0_RC    ((AT91_REG *)   0xFFFA001C) // (TC0) Register C
-#define AT91C_TC0_RB    ((AT91_REG *)   0xFFFA0018) // (TC0) Register B
-#define AT91C_TC0_CCR   ((AT91_REG *)   0xFFFA0000) // (TC0) Channel Control Register
-#define AT91C_TC0_CMR   ((AT91_REG *)   0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC0_IER   ((AT91_REG *)   0xFFFA0024) // (TC0) Interrupt Enable Register
-#define AT91C_TC0_RA    ((AT91_REG *)   0xFFFA0014) // (TC0) Register A
-#define AT91C_TC0_IDR   ((AT91_REG *)   0xFFFA0028) // (TC0) Interrupt Disable Register
-#define AT91C_TC0_CV    ((AT91_REG *)   0xFFFA0010) // (TC0) Counter Value
-#define AT91C_TC0_IMR   ((AT91_REG *)   0xFFFA002C) // (TC0) Interrupt Mask Register
-// ========== Register definition for TC1 peripheral ==========
-#define AT91C_TC1_RB    ((AT91_REG *)   0xFFFA0058) // (TC1) Register B
-#define AT91C_TC1_CCR   ((AT91_REG *)   0xFFFA0040) // (TC1) Channel Control Register
-#define AT91C_TC1_IER   ((AT91_REG *)   0xFFFA0064) // (TC1) Interrupt Enable Register
-#define AT91C_TC1_IDR   ((AT91_REG *)   0xFFFA0068) // (TC1) Interrupt Disable Register
-#define AT91C_TC1_SR    ((AT91_REG *)   0xFFFA0060) // (TC1) Status Register
-#define AT91C_TC1_CMR   ((AT91_REG *)   0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC1_RA    ((AT91_REG *)   0xFFFA0054) // (TC1) Register A
-#define AT91C_TC1_RC    ((AT91_REG *)   0xFFFA005C) // (TC1) Register C
-#define AT91C_TC1_IMR   ((AT91_REG *)   0xFFFA006C) // (TC1) Interrupt Mask Register
-#define AT91C_TC1_CV    ((AT91_REG *)   0xFFFA0050) // (TC1) Counter Value
-// ========== Register definition for TC2 peripheral ==========
-#define AT91C_TC2_CMR   ((AT91_REG *)   0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC2_CCR   ((AT91_REG *)   0xFFFA0080) // (TC2) Channel Control Register
-#define AT91C_TC2_CV    ((AT91_REG *)   0xFFFA0090) // (TC2) Counter Value
-#define AT91C_TC2_RA    ((AT91_REG *)   0xFFFA0094) // (TC2) Register A
-#define AT91C_TC2_RB    ((AT91_REG *)   0xFFFA0098) // (TC2) Register B
-#define AT91C_TC2_IDR   ((AT91_REG *)   0xFFFA00A8) // (TC2) Interrupt Disable Register
-#define AT91C_TC2_IMR   ((AT91_REG *)   0xFFFA00AC) // (TC2) Interrupt Mask Register
-#define AT91C_TC2_RC    ((AT91_REG *)   0xFFFA009C) // (TC2) Register C
-#define AT91C_TC2_IER   ((AT91_REG *)   0xFFFA00A4) // (TC2) Interrupt Enable Register
-#define AT91C_TC2_SR    ((AT91_REG *)   0xFFFA00A0) // (TC2) Status Register
-// ========== Register definition for TCB peripheral ==========
-#define AT91C_TCB_BMR   ((AT91_REG *)   0xFFFA00C4) // (TCB) TC Block Mode Register
-#define AT91C_TCB_BCR   ((AT91_REG *)   0xFFFA00C0) // (TCB) TC Block Control Register
-// ========== Register definition for CAN_MB0 peripheral ==========
-#define AT91C_CAN_MB0_MDL ((AT91_REG *)     0xFFFD0214) // (CAN_MB0) MailBox Data Low Register
-#define AT91C_CAN_MB0_MAM ((AT91_REG *)     0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB0_MCR ((AT91_REG *)     0xFFFD021C) // (CAN_MB0) MailBox Control Register
-#define AT91C_CAN_MB0_MID ((AT91_REG *)     0xFFFD0208) // (CAN_MB0) MailBox ID Register
-#define AT91C_CAN_MB0_MSR ((AT91_REG *)     0xFFFD0210) // (CAN_MB0) MailBox Status Register
-#define AT91C_CAN_MB0_MFID ((AT91_REG *)    0xFFFD020C) // (CAN_MB0) MailBox Family ID Register
-#define AT91C_CAN_MB0_MDH ((AT91_REG *)     0xFFFD0218) // (CAN_MB0) MailBox Data High Register
-#define AT91C_CAN_MB0_MMR ((AT91_REG *)     0xFFFD0200) // (CAN_MB0) MailBox Mode Register
-// ========== Register definition for CAN_MB1 peripheral ==========
-#define AT91C_CAN_MB1_MDL ((AT91_REG *)     0xFFFD0234) // (CAN_MB1) MailBox Data Low Register
-#define AT91C_CAN_MB1_MID ((AT91_REG *)     0xFFFD0228) // (CAN_MB1) MailBox ID Register
-#define AT91C_CAN_MB1_MMR ((AT91_REG *)     0xFFFD0220) // (CAN_MB1) MailBox Mode Register
-#define AT91C_CAN_MB1_MSR ((AT91_REG *)     0xFFFD0230) // (CAN_MB1) MailBox Status Register
-#define AT91C_CAN_MB1_MAM ((AT91_REG *)     0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB1_MDH ((AT91_REG *)     0xFFFD0238) // (CAN_MB1) MailBox Data High Register
-#define AT91C_CAN_MB1_MCR ((AT91_REG *)     0xFFFD023C) // (CAN_MB1) MailBox Control Register
-#define AT91C_CAN_MB1_MFID ((AT91_REG *)    0xFFFD022C) // (CAN_MB1) MailBox Family ID Register
-// ========== Register definition for CAN_MB2 peripheral ==========
-#define AT91C_CAN_MB2_MCR ((AT91_REG *)     0xFFFD025C) // (CAN_MB2) MailBox Control Register
-#define AT91C_CAN_MB2_MDH ((AT91_REG *)     0xFFFD0258) // (CAN_MB2) MailBox Data High Register
-#define AT91C_CAN_MB2_MID ((AT91_REG *)     0xFFFD0248) // (CAN_MB2) MailBox ID Register
-#define AT91C_CAN_MB2_MDL ((AT91_REG *)     0xFFFD0254) // (CAN_MB2) MailBox Data Low Register
-#define AT91C_CAN_MB2_MMR ((AT91_REG *)     0xFFFD0240) // (CAN_MB2) MailBox Mode Register
-#define AT91C_CAN_MB2_MAM ((AT91_REG *)     0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB2_MFID ((AT91_REG *)    0xFFFD024C) // (CAN_MB2) MailBox Family ID Register
-#define AT91C_CAN_MB2_MSR ((AT91_REG *)     0xFFFD0250) // (CAN_MB2) MailBox Status Register
-// ========== Register definition for CAN_MB3 peripheral ==========
-#define AT91C_CAN_MB3_MFID ((AT91_REG *)    0xFFFD026C) // (CAN_MB3) MailBox Family ID Register
-#define AT91C_CAN_MB3_MAM ((AT91_REG *)     0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB3_MID ((AT91_REG *)     0xFFFD0268) // (CAN_MB3) MailBox ID Register
-#define AT91C_CAN_MB3_MCR ((AT91_REG *)     0xFFFD027C) // (CAN_MB3) MailBox Control Register
-#define AT91C_CAN_MB3_MMR ((AT91_REG *)     0xFFFD0260) // (CAN_MB3) MailBox Mode Register
-#define AT91C_CAN_MB3_MSR ((AT91_REG *)     0xFFFD0270) // (CAN_MB3) MailBox Status Register
-#define AT91C_CAN_MB3_MDL ((AT91_REG *)     0xFFFD0274) // (CAN_MB3) MailBox Data Low Register
-#define AT91C_CAN_MB3_MDH ((AT91_REG *)     0xFFFD0278) // (CAN_MB3) MailBox Data High Register
-// ========== Register definition for CAN_MB4 peripheral ==========
-#define AT91C_CAN_MB4_MID ((AT91_REG *)     0xFFFD0288) // (CAN_MB4) MailBox ID Register
-#define AT91C_CAN_MB4_MMR ((AT91_REG *)     0xFFFD0280) // (CAN_MB4) MailBox Mode Register
-#define AT91C_CAN_MB4_MDH ((AT91_REG *)     0xFFFD0298) // (CAN_MB4) MailBox Data High Register
-#define AT91C_CAN_MB4_MFID ((AT91_REG *)    0xFFFD028C) // (CAN_MB4) MailBox Family ID Register
-#define AT91C_CAN_MB4_MSR ((AT91_REG *)     0xFFFD0290) // (CAN_MB4) MailBox Status Register
-#define AT91C_CAN_MB4_MCR ((AT91_REG *)     0xFFFD029C) // (CAN_MB4) MailBox Control Register
-#define AT91C_CAN_MB4_MDL ((AT91_REG *)     0xFFFD0294) // (CAN_MB4) MailBox Data Low Register
-#define AT91C_CAN_MB4_MAM ((AT91_REG *)     0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register
-// ========== Register definition for CAN_MB5 peripheral ==========
-#define AT91C_CAN_MB5_MSR ((AT91_REG *)     0xFFFD02B0) // (CAN_MB5) MailBox Status Register
-#define AT91C_CAN_MB5_MCR ((AT91_REG *)     0xFFFD02BC) // (CAN_MB5) MailBox Control Register
-#define AT91C_CAN_MB5_MFID ((AT91_REG *)    0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register
-#define AT91C_CAN_MB5_MDH ((AT91_REG *)     0xFFFD02B8) // (CAN_MB5) MailBox Data High Register
-#define AT91C_CAN_MB5_MID ((AT91_REG *)     0xFFFD02A8) // (CAN_MB5) MailBox ID Register
-#define AT91C_CAN_MB5_MMR ((AT91_REG *)     0xFFFD02A0) // (CAN_MB5) MailBox Mode Register
-#define AT91C_CAN_MB5_MDL ((AT91_REG *)     0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register
-#define AT91C_CAN_MB5_MAM ((AT91_REG *)     0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register
-// ========== Register definition for CAN_MB6 peripheral ==========
-#define AT91C_CAN_MB6_MFID ((AT91_REG *)    0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register
-#define AT91C_CAN_MB6_MID ((AT91_REG *)     0xFFFD02C8) // (CAN_MB6) MailBox ID Register
-#define AT91C_CAN_MB6_MAM ((AT91_REG *)     0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB6_MSR ((AT91_REG *)     0xFFFD02D0) // (CAN_MB6) MailBox Status Register
-#define AT91C_CAN_MB6_MDL ((AT91_REG *)     0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register
-#define AT91C_CAN_MB6_MCR ((AT91_REG *)     0xFFFD02DC) // (CAN_MB6) MailBox Control Register
-#define AT91C_CAN_MB6_MDH ((AT91_REG *)     0xFFFD02D8) // (CAN_MB6) MailBox Data High Register
-#define AT91C_CAN_MB6_MMR ((AT91_REG *)     0xFFFD02C0) // (CAN_MB6) MailBox Mode Register
-// ========== Register definition for CAN_MB7 peripheral ==========
-#define AT91C_CAN_MB7_MCR ((AT91_REG *)     0xFFFD02FC) // (CAN_MB7) MailBox Control Register
-#define AT91C_CAN_MB7_MDH ((AT91_REG *)     0xFFFD02F8) // (CAN_MB7) MailBox Data High Register
-#define AT91C_CAN_MB7_MFID ((AT91_REG *)    0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register
-#define AT91C_CAN_MB7_MDL ((AT91_REG *)     0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register
-#define AT91C_CAN_MB7_MID ((AT91_REG *)     0xFFFD02E8) // (CAN_MB7) MailBox ID Register
-#define AT91C_CAN_MB7_MMR ((AT91_REG *)     0xFFFD02E0) // (CAN_MB7) MailBox Mode Register
-#define AT91C_CAN_MB7_MAM ((AT91_REG *)     0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB7_MSR ((AT91_REG *)     0xFFFD02F0) // (CAN_MB7) MailBox Status Register
-// ========== Register definition for CAN peripheral ==========
-#define AT91C_CAN_TCR   ((AT91_REG *)   0xFFFD0024) // (CAN) Transfer Command Register
-#define AT91C_CAN_IMR   ((AT91_REG *)   0xFFFD000C) // (CAN) Interrupt Mask Register
-#define AT91C_CAN_IER   ((AT91_REG *)   0xFFFD0004) // (CAN) Interrupt Enable Register
-#define AT91C_CAN_ECR   ((AT91_REG *)   0xFFFD0020) // (CAN) Error Counter Register
-#define AT91C_CAN_TIMESTP ((AT91_REG *)     0xFFFD001C) // (CAN) Time Stamp Register
-#define AT91C_CAN_MR    ((AT91_REG *)   0xFFFD0000) // (CAN) Mode Register
-#define AT91C_CAN_IDR   ((AT91_REG *)   0xFFFD0008) // (CAN) Interrupt Disable Register
-#define AT91C_CAN_ACR   ((AT91_REG *)   0xFFFD0028) // (CAN) Abort Command Register
-#define AT91C_CAN_TIM   ((AT91_REG *)   0xFFFD0018) // (CAN) Timer Register
-#define AT91C_CAN_SR    ((AT91_REG *)   0xFFFD0010) // (CAN) Status Register
-#define AT91C_CAN_BR    ((AT91_REG *)   0xFFFD0014) // (CAN) Baudrate Register
-#define AT91C_CAN_VR    ((AT91_REG *)   0xFFFD00FC) // (CAN) Version Register
-// ========== Register definition for EMAC peripheral ==========
-#define AT91C_EMAC_ISR  ((AT91_REG *)   0xFFFDC024) // (EMAC) Interrupt Status Register
-#define AT91C_EMAC_SA4H ((AT91_REG *)   0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes
-#define AT91C_EMAC_SA1L ((AT91_REG *)   0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes
-#define AT91C_EMAC_ELE  ((AT91_REG *)   0xFFFDC078) // (EMAC) Excessive Length Errors Register
-#define AT91C_EMAC_LCOL ((AT91_REG *)   0xFFFDC05C) // (EMAC) Late Collision Register
-#define AT91C_EMAC_RLE  ((AT91_REG *)   0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register
-#define AT91C_EMAC_WOL  ((AT91_REG *)   0xFFFDC0C4) // (EMAC) Wake On LAN Register
-#define AT91C_EMAC_DTF  ((AT91_REG *)   0xFFFDC058) // (EMAC) Deferred Transmission Frame Register
-#define AT91C_EMAC_TUND ((AT91_REG *)   0xFFFDC064) // (EMAC) Transmit Underrun Error Register
-#define AT91C_EMAC_NCR  ((AT91_REG *)   0xFFFDC000) // (EMAC) Network Control Register
-#define AT91C_EMAC_SA4L ((AT91_REG *)   0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes
-#define AT91C_EMAC_RSR  ((AT91_REG *)   0xFFFDC020) // (EMAC) Receive Status Register
-#define AT91C_EMAC_SA3L ((AT91_REG *)   0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes
-#define AT91C_EMAC_TSR  ((AT91_REG *)   0xFFFDC014) // (EMAC) Transmit Status Register
-#define AT91C_EMAC_IDR  ((AT91_REG *)   0xFFFDC02C) // (EMAC) Interrupt Disable Register
-#define AT91C_EMAC_RSE  ((AT91_REG *)   0xFFFDC074) // (EMAC) Receive Symbol Errors Register
-#define AT91C_EMAC_ECOL ((AT91_REG *)   0xFFFDC060) // (EMAC) Excessive Collision Register
-#define AT91C_EMAC_TID  ((AT91_REG *)   0xFFFDC0B8) // (EMAC) Type ID Checking Register
-#define AT91C_EMAC_HRB  ((AT91_REG *)   0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]
-#define AT91C_EMAC_TBQP ((AT91_REG *)   0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer
-#define AT91C_EMAC_USRIO ((AT91_REG *)  0xFFFDC0C0) // (EMAC) USER Input/Output Register
-#define AT91C_EMAC_PTR  ((AT91_REG *)   0xFFFDC038) // (EMAC) Pause Time Register
-#define AT91C_EMAC_SA2H ((AT91_REG *)   0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes
-#define AT91C_EMAC_ROV  ((AT91_REG *)   0xFFFDC070) // (EMAC) Receive Overrun Errors Register
-#define AT91C_EMAC_ALE  ((AT91_REG *)   0xFFFDC054) // (EMAC) Alignment Error Register
-#define AT91C_EMAC_RJA  ((AT91_REG *)   0xFFFDC07C) // (EMAC) Receive Jabbers Register
-#define AT91C_EMAC_RBQP ((AT91_REG *)   0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer
-#define AT91C_EMAC_TPF  ((AT91_REG *)   0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register
-#define AT91C_EMAC_NCFGR ((AT91_REG *)  0xFFFDC004) // (EMAC) Network Configuration Register
-#define AT91C_EMAC_HRT  ((AT91_REG *)   0xFFFDC094) // (EMAC) Hash Address Top[63:32]
-#define AT91C_EMAC_USF  ((AT91_REG *)   0xFFFDC080) // (EMAC) Undersize Frames Register
-#define AT91C_EMAC_FCSE ((AT91_REG *)   0xFFFDC050) // (EMAC) Frame Check Sequence Error Register
-#define AT91C_EMAC_TPQ  ((AT91_REG *)   0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register
-#define AT91C_EMAC_MAN  ((AT91_REG *)   0xFFFDC034) // (EMAC) PHY Maintenance Register
-#define AT91C_EMAC_FTO  ((AT91_REG *)   0xFFFDC040) // (EMAC) Frames Transmitted OK Register
-#define AT91C_EMAC_REV  ((AT91_REG *)   0xFFFDC0FC) // (EMAC) Revision Register
-#define AT91C_EMAC_IMR  ((AT91_REG *)   0xFFFDC030) // (EMAC) Interrupt Mask Register
-#define AT91C_EMAC_SCF  ((AT91_REG *)   0xFFFDC044) // (EMAC) Single Collision Frame Register
-#define AT91C_EMAC_PFR  ((AT91_REG *)   0xFFFDC03C) // (EMAC) Pause Frames received Register
-#define AT91C_EMAC_MCF  ((AT91_REG *)   0xFFFDC048) // (EMAC) Multiple Collision Frame Register
-#define AT91C_EMAC_NSR  ((AT91_REG *)   0xFFFDC008) // (EMAC) Network Status Register
-#define AT91C_EMAC_SA2L ((AT91_REG *)   0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes
-#define AT91C_EMAC_FRO  ((AT91_REG *)   0xFFFDC04C) // (EMAC) Frames Received OK Register
-#define AT91C_EMAC_IER  ((AT91_REG *)   0xFFFDC028) // (EMAC) Interrupt Enable Register
-#define AT91C_EMAC_SA1H ((AT91_REG *)   0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes
-#define AT91C_EMAC_CSE  ((AT91_REG *)   0xFFFDC068) // (EMAC) Carrier Sense Error Register
-#define AT91C_EMAC_SA3H ((AT91_REG *)   0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes
-#define AT91C_EMAC_RRE  ((AT91_REG *)   0xFFFDC06C) // (EMAC) Receive Ressource Error Register
-#define AT91C_EMAC_STE  ((AT91_REG *)   0xFFFDC084) // (EMAC) SQE Test Error Register
-// ========== Register definition for PDC_ADC peripheral ==========
-#define AT91C_ADC_PTSR  ((AT91_REG *)   0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
-#define AT91C_ADC_PTCR  ((AT91_REG *)   0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
-#define AT91C_ADC_TNPR  ((AT91_REG *)   0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
-#define AT91C_ADC_TNCR  ((AT91_REG *)   0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
-#define AT91C_ADC_RNPR  ((AT91_REG *)   0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
-#define AT91C_ADC_RNCR  ((AT91_REG *)   0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
-#define AT91C_ADC_RPR   ((AT91_REG *)   0xFFFD8100) // (PDC_ADC) Receive Pointer Register
-#define AT91C_ADC_TCR   ((AT91_REG *)   0xFFFD810C) // (PDC_ADC) Transmit Counter Register
-#define AT91C_ADC_TPR   ((AT91_REG *)   0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
-#define AT91C_ADC_RCR   ((AT91_REG *)   0xFFFD8104) // (PDC_ADC) Receive Counter Register
-// ========== Register definition for ADC peripheral ==========
-#define AT91C_ADC_CDR2  ((AT91_REG *)   0xFFFD8038) // (ADC) ADC Channel Data Register 2
-#define AT91C_ADC_CDR3  ((AT91_REG *)   0xFFFD803C) // (ADC) ADC Channel Data Register 3
-#define AT91C_ADC_CDR0  ((AT91_REG *)   0xFFFD8030) // (ADC) ADC Channel Data Register 0
-#define AT91C_ADC_CDR5  ((AT91_REG *)   0xFFFD8044) // (ADC) ADC Channel Data Register 5
-#define AT91C_ADC_CHDR  ((AT91_REG *)   0xFFFD8014) // (ADC) ADC Channel Disable Register
-#define AT91C_ADC_SR    ((AT91_REG *)   0xFFFD801C) // (ADC) ADC Status Register
-#define AT91C_ADC_CDR4  ((AT91_REG *)   0xFFFD8040) // (ADC) ADC Channel Data Register 4
-#define AT91C_ADC_CDR1  ((AT91_REG *)   0xFFFD8034) // (ADC) ADC Channel Data Register 1
-#define AT91C_ADC_LCDR  ((AT91_REG *)   0xFFFD8020) // (ADC) ADC Last Converted Data Register
-#define AT91C_ADC_IDR   ((AT91_REG *)   0xFFFD8028) // (ADC) ADC Interrupt Disable Register
-#define AT91C_ADC_CR    ((AT91_REG *)   0xFFFD8000) // (ADC) ADC Control Register
-#define AT91C_ADC_CDR7  ((AT91_REG *)   0xFFFD804C) // (ADC) ADC Channel Data Register 7
-#define AT91C_ADC_CDR6  ((AT91_REG *)   0xFFFD8048) // (ADC) ADC Channel Data Register 6
-#define AT91C_ADC_IER   ((AT91_REG *)   0xFFFD8024) // (ADC) ADC Interrupt Enable Register
-#define AT91C_ADC_CHER  ((AT91_REG *)   0xFFFD8010) // (ADC) ADC Channel Enable Register
-#define AT91C_ADC_CHSR  ((AT91_REG *)   0xFFFD8018) // (ADC) ADC Channel Status Register
-#define AT91C_ADC_MR    ((AT91_REG *)   0xFFFD8004) // (ADC) ADC Mode Register
-#define AT91C_ADC_IMR   ((AT91_REG *)   0xFFFD802C) // (ADC) ADC Interrupt Mask Register
-// ========== Register definition for PDC_AES peripheral ==========
-#define AT91C_AES_TPR   ((AT91_REG *)   0xFFFA4108) // (PDC_AES) Transmit Pointer Register
-#define AT91C_AES_PTCR  ((AT91_REG *)   0xFFFA4120) // (PDC_AES) PDC Transfer Control Register
-#define AT91C_AES_RNPR  ((AT91_REG *)   0xFFFA4110) // (PDC_AES) Receive Next Pointer Register
-#define AT91C_AES_TNCR  ((AT91_REG *)   0xFFFA411C) // (PDC_AES) Transmit Next Counter Register
-#define AT91C_AES_TCR   ((AT91_REG *)   0xFFFA410C) // (PDC_AES) Transmit Counter Register
-#define AT91C_AES_RCR   ((AT91_REG *)   0xFFFA4104) // (PDC_AES) Receive Counter Register
-#define AT91C_AES_RNCR  ((AT91_REG *)   0xFFFA4114) // (PDC_AES) Receive Next Counter Register
-#define AT91C_AES_TNPR  ((AT91_REG *)   0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register
-#define AT91C_AES_RPR   ((AT91_REG *)   0xFFFA4100) // (PDC_AES) Receive Pointer Register
-#define AT91C_AES_PTSR  ((AT91_REG *)   0xFFFA4124) // (PDC_AES) PDC Transfer Status Register
-// ========== Register definition for AES peripheral ==========
-#define AT91C_AES_IVxR  ((AT91_REG *)   0xFFFA4060) // (AES) Initialization Vector x Register
-#define AT91C_AES_MR    ((AT91_REG *)   0xFFFA4004) // (AES) Mode Register
-#define AT91C_AES_VR    ((AT91_REG *)   0xFFFA40FC) // (AES) AES Version Register
-#define AT91C_AES_ODATAxR ((AT91_REG *)     0xFFFA4050) // (AES) Output Data x Register
-#define AT91C_AES_IDATAxR ((AT91_REG *)     0xFFFA4040) // (AES) Input Data x Register
-#define AT91C_AES_CR    ((AT91_REG *)   0xFFFA4000) // (AES) Control Register
-#define AT91C_AES_IDR   ((AT91_REG *)   0xFFFA4014) // (AES) Interrupt Disable Register
-#define AT91C_AES_IMR   ((AT91_REG *)   0xFFFA4018) // (AES) Interrupt Mask Register
-#define AT91C_AES_IER   ((AT91_REG *)   0xFFFA4010) // (AES) Interrupt Enable Register
-#define AT91C_AES_KEYWxR ((AT91_REG *)  0xFFFA4020) // (AES) Key Word x Register
-#define AT91C_AES_ISR   ((AT91_REG *)   0xFFFA401C) // (AES) Interrupt Status Register
-// ========== Register definition for PDC_TDES peripheral ==========
-#define AT91C_TDES_RNCR ((AT91_REG *)   0xFFFA8114) // (PDC_TDES) Receive Next Counter Register
-#define AT91C_TDES_TCR  ((AT91_REG *)   0xFFFA810C) // (PDC_TDES) Transmit Counter Register
-#define AT91C_TDES_RCR  ((AT91_REG *)   0xFFFA8104) // (PDC_TDES) Receive Counter Register
-#define AT91C_TDES_TNPR ((AT91_REG *)   0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register
-#define AT91C_TDES_RNPR ((AT91_REG *)   0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register
-#define AT91C_TDES_RPR  ((AT91_REG *)   0xFFFA8100) // (PDC_TDES) Receive Pointer Register
-#define AT91C_TDES_TNCR ((AT91_REG *)   0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register
-#define AT91C_TDES_TPR  ((AT91_REG *)   0xFFFA8108) // (PDC_TDES) Transmit Pointer Register
-#define AT91C_TDES_PTSR ((AT91_REG *)   0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register
-#define AT91C_TDES_PTCR ((AT91_REG *)   0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register
-// ========== Register definition for TDES peripheral ==========
-#define AT91C_TDES_KEY2WxR ((AT91_REG *)    0xFFFA8028) // (TDES) Key 2 Word x Register
-#define AT91C_TDES_KEY3WxR ((AT91_REG *)    0xFFFA8030) // (TDES) Key 3 Word x Register
-#define AT91C_TDES_IDR  ((AT91_REG *)   0xFFFA8014) // (TDES) Interrupt Disable Register
-#define AT91C_TDES_VR   ((AT91_REG *)   0xFFFA80FC) // (TDES) TDES Version Register
-#define AT91C_TDES_IVxR ((AT91_REG *)   0xFFFA8060) // (TDES) Initialization Vector x Register
-#define AT91C_TDES_ODATAxR ((AT91_REG *)    0xFFFA8050) // (TDES) Output Data x Register
-#define AT91C_TDES_IMR  ((AT91_REG *)   0xFFFA8018) // (TDES) Interrupt Mask Register
-#define AT91C_TDES_MR   ((AT91_REG *)   0xFFFA8004) // (TDES) Mode Register
-#define AT91C_TDES_CR   ((AT91_REG *)   0xFFFA8000) // (TDES) Control Register
-#define AT91C_TDES_IER  ((AT91_REG *)   0xFFFA8010) // (TDES) Interrupt Enable Register
-#define AT91C_TDES_ISR  ((AT91_REG *)   0xFFFA801C) // (TDES) Interrupt Status Register
-#define AT91C_TDES_IDATAxR ((AT91_REG *)    0xFFFA8040) // (TDES) Input Data x Register
-#define AT91C_TDES_KEY1WxR ((AT91_REG *)    0xFFFA8020) // (TDES) Key 1 Word x Register
+/* ***************************************************************************** */
+/*               REGISTER ADDRESS DEFINITION FOR AT91SAM7X128 */
+/* ***************************************************************************** */
+/* ========== Register definition for SYS peripheral ========== */
+/* ========== Register definition for AIC peripheral ========== */
+#define AT91C_AIC_IVR              ( ( AT91_REG * ) 0xFFFFF100 ) /* (AIC) IRQ Vector Register */
+#define AT91C_AIC_SMR              ( ( AT91_REG * ) 0xFFFFF000 ) /* (AIC) Source Mode Register */
+#define AT91C_AIC_FVR              ( ( AT91_REG * ) 0xFFFFF104 ) /* (AIC) FIQ Vector Register */
+#define AT91C_AIC_DCR              ( ( AT91_REG * ) 0xFFFFF138 ) /* (AIC) Debug Control Register (Protect) */
+#define AT91C_AIC_EOICR            ( ( AT91_REG * ) 0xFFFFF130 ) /* (AIC) End of Interrupt Command Register */
+#define AT91C_AIC_SVR              ( ( AT91_REG * ) 0xFFFFF080 ) /* (AIC) Source Vector Register */
+#define AT91C_AIC_FFSR             ( ( AT91_REG * ) 0xFFFFF148 ) /* (AIC) Fast Forcing Status Register */
+#define AT91C_AIC_ICCR             ( ( AT91_REG * ) 0xFFFFF128 ) /* (AIC) Interrupt Clear Command Register */
+#define AT91C_AIC_ISR              ( ( AT91_REG * ) 0xFFFFF108 ) /* (AIC) Interrupt Status Register */
+#define AT91C_AIC_IMR              ( ( AT91_REG * ) 0xFFFFF110 ) /* (AIC) Interrupt Mask Register */
+#define AT91C_AIC_IPR              ( ( AT91_REG * ) 0xFFFFF10C ) /* (AIC) Interrupt Pending Register */
+#define AT91C_AIC_FFER             ( ( AT91_REG * ) 0xFFFFF140 ) /* (AIC) Fast Forcing Enable Register */
+#define AT91C_AIC_IECR             ( ( AT91_REG * ) 0xFFFFF120 ) /* (AIC) Interrupt Enable Command Register */
+#define AT91C_AIC_ISCR             ( ( AT91_REG * ) 0xFFFFF12C ) /* (AIC) Interrupt Set Command Register */
+#define AT91C_AIC_FFDR             ( ( AT91_REG * ) 0xFFFFF144 ) /* (AIC) Fast Forcing Disable Register */
+#define AT91C_AIC_CISR             ( ( AT91_REG * ) 0xFFFFF114 ) /* (AIC) Core Interrupt Status Register */
+#define AT91C_AIC_IDCR             ( ( AT91_REG * ) 0xFFFFF124 ) /* (AIC) Interrupt Disable Command Register */
+#define AT91C_AIC_SPU              ( ( AT91_REG * ) 0xFFFFF134 ) /* (AIC) Spurious Vector Register */
+/* ========== Register definition for PDC_DBGU peripheral ========== */
+#define AT91C_DBGU_TCR             ( ( AT91_REG * ) 0xFFFFF30C ) /* (PDC_DBGU) Transmit Counter Register */
+#define AT91C_DBGU_RNPR            ( ( AT91_REG * ) 0xFFFFF310 ) /* (PDC_DBGU) Receive Next Pointer Register */
+#define AT91C_DBGU_TNPR            ( ( AT91_REG * ) 0xFFFFF318 ) /* (PDC_DBGU) Transmit Next Pointer Register */
+#define AT91C_DBGU_TPR             ( ( AT91_REG * ) 0xFFFFF308 ) /* (PDC_DBGU) Transmit Pointer Register */
+#define AT91C_DBGU_RPR             ( ( AT91_REG * ) 0xFFFFF300 ) /* (PDC_DBGU) Receive Pointer Register */
+#define AT91C_DBGU_RCR             ( ( AT91_REG * ) 0xFFFFF304 ) /* (PDC_DBGU) Receive Counter Register */
+#define AT91C_DBGU_RNCR            ( ( AT91_REG * ) 0xFFFFF314 ) /* (PDC_DBGU) Receive Next Counter Register */
+#define AT91C_DBGU_PTCR            ( ( AT91_REG * ) 0xFFFFF320 ) /* (PDC_DBGU) PDC Transfer Control Register */
+#define AT91C_DBGU_PTSR            ( ( AT91_REG * ) 0xFFFFF324 ) /* (PDC_DBGU) PDC Transfer Status Register */
+#define AT91C_DBGU_TNCR            ( ( AT91_REG * ) 0xFFFFF31C ) /* (PDC_DBGU) Transmit Next Counter Register */
+/* ========== Register definition for DBGU peripheral ========== */
+#define AT91C_DBGU_EXID            ( ( AT91_REG * ) 0xFFFFF244 ) /* (DBGU) Chip ID Extension Register */
+#define AT91C_DBGU_BRGR            ( ( AT91_REG * ) 0xFFFFF220 ) /* (DBGU) Baud Rate Generator Register */
+#define AT91C_DBGU_IDR             ( ( AT91_REG * ) 0xFFFFF20C ) /* (DBGU) Interrupt Disable Register */
+#define AT91C_DBGU_CSR             ( ( AT91_REG * ) 0xFFFFF214 ) /* (DBGU) Channel Status Register */
+#define AT91C_DBGU_CIDR            ( ( AT91_REG * ) 0xFFFFF240 ) /* (DBGU) Chip ID Register */
+#define AT91C_DBGU_MR              ( ( AT91_REG * ) 0xFFFFF204 ) /* (DBGU) Mode Register */
+#define AT91C_DBGU_IMR             ( ( AT91_REG * ) 0xFFFFF210 ) /* (DBGU) Interrupt Mask Register */
+#define AT91C_DBGU_CR              ( ( AT91_REG * ) 0xFFFFF200 ) /* (DBGU) Control Register */
+#define AT91C_DBGU_FNTR            ( ( AT91_REG * ) 0xFFFFF248 ) /* (DBGU) Force NTRST Register */
+#define AT91C_DBGU_THR             ( ( AT91_REG * ) 0xFFFFF21C ) /* (DBGU) Transmitter Holding Register */
+#define AT91C_DBGU_RHR             ( ( AT91_REG * ) 0xFFFFF218 ) /* (DBGU) Receiver Holding Register */
+#define AT91C_DBGU_IER             ( ( AT91_REG * ) 0xFFFFF208 ) /* (DBGU) Interrupt Enable Register */
+/* ========== Register definition for PIOA peripheral ========== */
+#define AT91C_PIOA_ODR             ( ( AT91_REG * ) 0xFFFFF414 ) /* (PIOA) Output Disable Registerr */
+#define AT91C_PIOA_SODR            ( ( AT91_REG * ) 0xFFFFF430 ) /* (PIOA) Set Output Data Register */
+#define AT91C_PIOA_ISR             ( ( AT91_REG * ) 0xFFFFF44C ) /* (PIOA) Interrupt Status Register */
+#define AT91C_PIOA_ABSR            ( ( AT91_REG * ) 0xFFFFF478 ) /* (PIOA) AB Select Status Register */
+#define AT91C_PIOA_IER             ( ( AT91_REG * ) 0xFFFFF440 ) /* (PIOA) Interrupt Enable Register */
+#define AT91C_PIOA_PPUDR           ( ( AT91_REG * ) 0xFFFFF460 ) /* (PIOA) Pull-up Disable Register */
+#define AT91C_PIOA_IMR             ( ( AT91_REG * ) 0xFFFFF448 ) /* (PIOA) Interrupt Mask Register */
+#define AT91C_PIOA_PER             ( ( AT91_REG * ) 0xFFFFF400 ) /* (PIOA) PIO Enable Register */
+#define AT91C_PIOA_IFDR            ( ( AT91_REG * ) 0xFFFFF424 ) /* (PIOA) Input Filter Disable Register */
+#define AT91C_PIOA_OWDR            ( ( AT91_REG * ) 0xFFFFF4A4 ) /* (PIOA) Output Write Disable Register */
+#define AT91C_PIOA_MDSR            ( ( AT91_REG * ) 0xFFFFF458 ) /* (PIOA) Multi-driver Status Register */
+#define AT91C_PIOA_IDR             ( ( AT91_REG * ) 0xFFFFF444 ) /* (PIOA) Interrupt Disable Register */
+#define AT91C_PIOA_ODSR            ( ( AT91_REG * ) 0xFFFFF438 ) /* (PIOA) Output Data Status Register */
+#define AT91C_PIOA_PPUSR           ( ( AT91_REG * ) 0xFFFFF468 ) /* (PIOA) Pull-up Status Register */
+#define AT91C_PIOA_OWSR            ( ( AT91_REG * ) 0xFFFFF4A8 ) /* (PIOA) Output Write Status Register */
+#define AT91C_PIOA_BSR             ( ( AT91_REG * ) 0xFFFFF474 ) /* (PIOA) Select B Register */
+#define AT91C_PIOA_OWER            ( ( AT91_REG * ) 0xFFFFF4A0 ) /* (PIOA) Output Write Enable Register */
+#define AT91C_PIOA_IFER            ( ( AT91_REG * ) 0xFFFFF420 ) /* (PIOA) Input Filter Enable Register */
+#define AT91C_PIOA_PDSR            ( ( AT91_REG * ) 0xFFFFF43C ) /* (PIOA) Pin Data Status Register */
+#define AT91C_PIOA_PPUER           ( ( AT91_REG * ) 0xFFFFF464 ) /* (PIOA) Pull-up Enable Register */
+#define AT91C_PIOA_OSR             ( ( AT91_REG * ) 0xFFFFF418 ) /* (PIOA) Output Status Register */
+#define AT91C_PIOA_ASR             ( ( AT91_REG * ) 0xFFFFF470 ) /* (PIOA) Select A Register */
+#define AT91C_PIOA_MDDR            ( ( AT91_REG * ) 0xFFFFF454 ) /* (PIOA) Multi-driver Disable Register */
+#define AT91C_PIOA_CODR            ( ( AT91_REG * ) 0xFFFFF434 ) /* (PIOA) Clear Output Data Register */
+#define AT91C_PIOA_MDER            ( ( AT91_REG * ) 0xFFFFF450 ) /* (PIOA) Multi-driver Enable Register */
+#define AT91C_PIOA_PDR             ( ( AT91_REG * ) 0xFFFFF404 ) /* (PIOA) PIO Disable Register */
+#define AT91C_PIOA_IFSR            ( ( AT91_REG * ) 0xFFFFF428 ) /* (PIOA) Input Filter Status Register */
+#define AT91C_PIOA_OER             ( ( AT91_REG * ) 0xFFFFF410 ) /* (PIOA) Output Enable Register */
+#define AT91C_PIOA_PSR             ( ( AT91_REG * ) 0xFFFFF408 ) /* (PIOA) PIO Status Register */
+/* ========== Register definition for PIOB peripheral ========== */
+#define AT91C_PIOB_OWDR            ( ( AT91_REG * ) 0xFFFFF6A4 ) /* (PIOB) Output Write Disable Register */
+#define AT91C_PIOB_MDER            ( ( AT91_REG * ) 0xFFFFF650 ) /* (PIOB) Multi-driver Enable Register */
+#define AT91C_PIOB_PPUSR           ( ( AT91_REG * ) 0xFFFFF668 ) /* (PIOB) Pull-up Status Register */
+#define AT91C_PIOB_IMR             ( ( AT91_REG * ) 0xFFFFF648 ) /* (PIOB) Interrupt Mask Register */
+#define AT91C_PIOB_ASR             ( ( AT91_REG * ) 0xFFFFF670 ) /* (PIOB) Select A Register */
+#define AT91C_PIOB_PPUDR           ( ( AT91_REG * ) 0xFFFFF660 ) /* (PIOB) Pull-up Disable Register */
+#define AT91C_PIOB_PSR             ( ( AT91_REG * ) 0xFFFFF608 ) /* (PIOB) PIO Status Register */
+#define AT91C_PIOB_IER             ( ( AT91_REG * ) 0xFFFFF640 ) /* (PIOB) Interrupt Enable Register */
+#define AT91C_PIOB_CODR            ( ( AT91_REG * ) 0xFFFFF634 ) /* (PIOB) Clear Output Data Register */
+#define AT91C_PIOB_OWER            ( ( AT91_REG * ) 0xFFFFF6A0 ) /* (PIOB) Output Write Enable Register */
+#define AT91C_PIOB_ABSR            ( ( AT91_REG * ) 0xFFFFF678 ) /* (PIOB) AB Select Status Register */
+#define AT91C_PIOB_IFDR            ( ( AT91_REG * ) 0xFFFFF624 ) /* (PIOB) Input Filter Disable Register */
+#define AT91C_PIOB_PDSR            ( ( AT91_REG * ) 0xFFFFF63C ) /* (PIOB) Pin Data Status Register */
+#define AT91C_PIOB_IDR             ( ( AT91_REG * ) 0xFFFFF644 ) /* (PIOB) Interrupt Disable Register */
+#define AT91C_PIOB_OWSR            ( ( AT91_REG * ) 0xFFFFF6A8 ) /* (PIOB) Output Write Status Register */
+#define AT91C_PIOB_PDR             ( ( AT91_REG * ) 0xFFFFF604 ) /* (PIOB) PIO Disable Register */
+#define AT91C_PIOB_ODR             ( ( AT91_REG * ) 0xFFFFF614 ) /* (PIOB) Output Disable Registerr */
+#define AT91C_PIOB_IFSR            ( ( AT91_REG * ) 0xFFFFF628 ) /* (PIOB) Input Filter Status Register */
+#define AT91C_PIOB_PPUER           ( ( AT91_REG * ) 0xFFFFF664 ) /* (PIOB) Pull-up Enable Register */
+#define AT91C_PIOB_SODR            ( ( AT91_REG * ) 0xFFFFF630 ) /* (PIOB) Set Output Data Register */
+#define AT91C_PIOB_ISR             ( ( AT91_REG * ) 0xFFFFF64C ) /* (PIOB) Interrupt Status Register */
+#define AT91C_PIOB_ODSR            ( ( AT91_REG * ) 0xFFFFF638 ) /* (PIOB) Output Data Status Register */
+#define AT91C_PIOB_OSR             ( ( AT91_REG * ) 0xFFFFF618 ) /* (PIOB) Output Status Register */
+#define AT91C_PIOB_MDSR            ( ( AT91_REG * ) 0xFFFFF658 ) /* (PIOB) Multi-driver Status Register */
+#define AT91C_PIOB_IFER            ( ( AT91_REG * ) 0xFFFFF620 ) /* (PIOB) Input Filter Enable Register */
+#define AT91C_PIOB_BSR             ( ( AT91_REG * ) 0xFFFFF674 ) /* (PIOB) Select B Register */
+#define AT91C_PIOB_MDDR            ( ( AT91_REG * ) 0xFFFFF654 ) /* (PIOB) Multi-driver Disable Register */
+#define AT91C_PIOB_OER             ( ( AT91_REG * ) 0xFFFFF610 ) /* (PIOB) Output Enable Register */
+#define AT91C_PIOB_PER             ( ( AT91_REG * ) 0xFFFFF600 ) /* (PIOB) PIO Enable Register */
+/* ========== Register definition for CKGR peripheral ========== */
+#define AT91C_CKGR_MOR             ( ( AT91_REG * ) 0xFFFFFC20 ) /* (CKGR) Main Oscillator Register */
+#define AT91C_CKGR_PLLR            ( ( AT91_REG * ) 0xFFFFFC2C ) /* (CKGR) PLL Register */
+#define AT91C_CKGR_MCFR            ( ( AT91_REG * ) 0xFFFFFC24 ) /* (CKGR) Main Clock  Frequency Register */
+/* ========== Register definition for PMC peripheral ========== */
+#define AT91C_PMC_IDR              ( ( AT91_REG * ) 0xFFFFFC64 ) /* (PMC) Interrupt Disable Register */
+#define AT91C_PMC_MOR              ( ( AT91_REG * ) 0xFFFFFC20 ) /* (PMC) Main Oscillator Register */
+#define AT91C_PMC_PLLR             ( ( AT91_REG * ) 0xFFFFFC2C ) /* (PMC) PLL Register */
+#define AT91C_PMC_PCER             ( ( AT91_REG * ) 0xFFFFFC10 ) /* (PMC) Peripheral Clock Enable Register */
+#define AT91C_PMC_PCKR             ( ( AT91_REG * ) 0xFFFFFC40 ) /* (PMC) Programmable Clock Register */
+#define AT91C_PMC_MCKR             ( ( AT91_REG * ) 0xFFFFFC30 ) /* (PMC) Master Clock Register */
+#define AT91C_PMC_SCDR             ( ( AT91_REG * ) 0xFFFFFC04 ) /* (PMC) System Clock Disable Register */
+#define AT91C_PMC_PCDR             ( ( AT91_REG * ) 0xFFFFFC14 ) /* (PMC) Peripheral Clock Disable Register */
+#define AT91C_PMC_SCSR             ( ( AT91_REG * ) 0xFFFFFC08 ) /* (PMC) System Clock Status Register */
+#define AT91C_PMC_PCSR             ( ( AT91_REG * ) 0xFFFFFC18 ) /* (PMC) Peripheral Clock Status Register */
+#define AT91C_PMC_MCFR             ( ( AT91_REG * ) 0xFFFFFC24 ) /* (PMC) Main Clock  Frequency Register */
+#define AT91C_PMC_SCER             ( ( AT91_REG * ) 0xFFFFFC00 ) /* (PMC) System Clock Enable Register */
+#define AT91C_PMC_IMR              ( ( AT91_REG * ) 0xFFFFFC6C ) /* (PMC) Interrupt Mask Register */
+#define AT91C_PMC_IER              ( ( AT91_REG * ) 0xFFFFFC60 ) /* (PMC) Interrupt Enable Register */
+#define AT91C_PMC_SR               ( ( AT91_REG * ) 0xFFFFFC68 ) /* (PMC) Status Register */
+/* ========== Register definition for RSTC peripheral ========== */
+#define AT91C_RSTC_RCR             ( ( AT91_REG * ) 0xFFFFFD00 ) /* (RSTC) Reset Control Register */
+#define AT91C_RSTC_RMR             ( ( AT91_REG * ) 0xFFFFFD08 ) /* (RSTC) Reset Mode Register */
+#define AT91C_RSTC_RSR             ( ( AT91_REG * ) 0xFFFFFD04 ) /* (RSTC) Reset Status Register */
+/* ========== Register definition for RTTC peripheral ========== */
+#define AT91C_RTTC_RTSR            ( ( AT91_REG * ) 0xFFFFFD2C ) /* (RTTC) Real-time Status Register */
+#define AT91C_RTTC_RTMR            ( ( AT91_REG * ) 0xFFFFFD20 ) /* (RTTC) Real-time Mode Register */
+#define AT91C_RTTC_RTVR            ( ( AT91_REG * ) 0xFFFFFD28 ) /* (RTTC) Real-time Value Register */
+#define AT91C_RTTC_RTAR            ( ( AT91_REG * ) 0xFFFFFD24 ) /* (RTTC) Real-time Alarm Register */
+/* ========== Register definition for PITC peripheral ========== */
+#define AT91C_PITC_PIVR            ( ( AT91_REG * ) 0xFFFFFD38 ) /* (PITC) Period Interval Value Register */
+#define AT91C_PITC_PISR            ( ( AT91_REG * ) 0xFFFFFD34 ) /* (PITC) Period Interval Status Register */
+#define AT91C_PITC_PIIR            ( ( AT91_REG * ) 0xFFFFFD3C ) /* (PITC) Period Interval Image Register */
+#define AT91C_PITC_PIMR            ( ( AT91_REG * ) 0xFFFFFD30 ) /* (PITC) Period Interval Mode Register */
+/* ========== Register definition for WDTC peripheral ========== */
+#define AT91C_WDTC_WDCR            ( ( AT91_REG * ) 0xFFFFFD40 ) /* (WDTC) Watchdog Control Register */
+#define AT91C_WDTC_WDSR            ( ( AT91_REG * ) 0xFFFFFD48 ) /* (WDTC) Watchdog Status Register */
+#define AT91C_WDTC_WDMR            ( ( AT91_REG * ) 0xFFFFFD44 ) /* (WDTC) Watchdog Mode Register */
+/* ========== Register definition for VREG peripheral ========== */
+#define AT91C_VREG_MR              ( ( AT91_REG * ) 0xFFFFFD60 ) /* (VREG) Voltage Regulator Mode Register */
+/* ========== Register definition for MC peripheral ========== */
+#define AT91C_MC_ASR               ( ( AT91_REG * ) 0xFFFFFF04 ) /* (MC) MC Abort Status Register */
+#define AT91C_MC_RCR               ( ( AT91_REG * ) 0xFFFFFF00 ) /* (MC) MC Remap Control Register */
+#define AT91C_MC_FCR               ( ( AT91_REG * ) 0xFFFFFF64 ) /* (MC) MC Flash Command Register */
+#define AT91C_MC_AASR              ( ( AT91_REG * ) 0xFFFFFF08 ) /* (MC) MC Abort Address Status Register */
+#define AT91C_MC_FSR               ( ( AT91_REG * ) 0xFFFFFF68 ) /* (MC) MC Flash Status Register */
+#define AT91C_MC_FMR               ( ( AT91_REG * ) 0xFFFFFF60 ) /* (MC) MC Flash Mode Register */
+/* ========== Register definition for PDC_SPI1 peripheral ========== */
+#define AT91C_SPI1_PTCR            ( ( AT91_REG * ) 0xFFFE4120 ) /* (PDC_SPI1) PDC Transfer Control Register */
+#define AT91C_SPI1_RPR             ( ( AT91_REG * ) 0xFFFE4100 ) /* (PDC_SPI1) Receive Pointer Register */
+#define AT91C_SPI1_TNCR            ( ( AT91_REG * ) 0xFFFE411C ) /* (PDC_SPI1) Transmit Next Counter Register */
+#define AT91C_SPI1_TPR             ( ( AT91_REG * ) 0xFFFE4108 ) /* (PDC_SPI1) Transmit Pointer Register */
+#define AT91C_SPI1_TNPR            ( ( AT91_REG * ) 0xFFFE4118 ) /* (PDC_SPI1) Transmit Next Pointer Register */
+#define AT91C_SPI1_TCR             ( ( AT91_REG * ) 0xFFFE410C ) /* (PDC_SPI1) Transmit Counter Register */
+#define AT91C_SPI1_RCR             ( ( AT91_REG * ) 0xFFFE4104 ) /* (PDC_SPI1) Receive Counter Register */
+#define AT91C_SPI1_RNPR            ( ( AT91_REG * ) 0xFFFE4110 ) /* (PDC_SPI1) Receive Next Pointer Register */
+#define AT91C_SPI1_RNCR            ( ( AT91_REG * ) 0xFFFE4114 ) /* (PDC_SPI1) Receive Next Counter Register */
+#define AT91C_SPI1_PTSR            ( ( AT91_REG * ) 0xFFFE4124 ) /* (PDC_SPI1) PDC Transfer Status Register */
+/* ========== Register definition for SPI1 peripheral ========== */
+#define AT91C_SPI1_IMR             ( ( AT91_REG * ) 0xFFFE401C ) /* (SPI1) Interrupt Mask Register */
+#define AT91C_SPI1_IER             ( ( AT91_REG * ) 0xFFFE4014 ) /* (SPI1) Interrupt Enable Register */
+#define AT91C_SPI1_MR              ( ( AT91_REG * ) 0xFFFE4004 ) /* (SPI1) Mode Register */
+#define AT91C_SPI1_RDR             ( ( AT91_REG * ) 0xFFFE4008 ) /* (SPI1) Receive Data Register */
+#define AT91C_SPI1_IDR             ( ( AT91_REG * ) 0xFFFE4018 ) /* (SPI1) Interrupt Disable Register */
+#define AT91C_SPI1_SR              ( ( AT91_REG * ) 0xFFFE4010 ) /* (SPI1) Status Register */
+#define AT91C_SPI1_TDR             ( ( AT91_REG * ) 0xFFFE400C ) /* (SPI1) Transmit Data Register */
+#define AT91C_SPI1_CR              ( ( AT91_REG * ) 0xFFFE4000 ) /* (SPI1) Control Register */
+#define AT91C_SPI1_CSR             ( ( AT91_REG * ) 0xFFFE4030 ) /* (SPI1) Chip Select Register */
+/* ========== Register definition for PDC_SPI0 peripheral ========== */
+#define AT91C_SPI0_PTCR            ( ( AT91_REG * ) 0xFFFE0120 ) /* (PDC_SPI0) PDC Transfer Control Register */
+#define AT91C_SPI0_TPR             ( ( AT91_REG * ) 0xFFFE0108 ) /* (PDC_SPI0) Transmit Pointer Register */
+#define AT91C_SPI0_TCR             ( ( AT91_REG * ) 0xFFFE010C ) /* (PDC_SPI0) Transmit Counter Register */
+#define AT91C_SPI0_RCR             ( ( AT91_REG * ) 0xFFFE0104 ) /* (PDC_SPI0) Receive Counter Register */
+#define AT91C_SPI0_PTSR            ( ( AT91_REG * ) 0xFFFE0124 ) /* (PDC_SPI0) PDC Transfer Status Register */
+#define AT91C_SPI0_RNPR            ( ( AT91_REG * ) 0xFFFE0110 ) /* (PDC_SPI0) Receive Next Pointer Register */
+#define AT91C_SPI0_RPR             ( ( AT91_REG * ) 0xFFFE0100 ) /* (PDC_SPI0) Receive Pointer Register */
+#define AT91C_SPI0_TNCR            ( ( AT91_REG * ) 0xFFFE011C ) /* (PDC_SPI0) Transmit Next Counter Register */
+#define AT91C_SPI0_RNCR            ( ( AT91_REG * ) 0xFFFE0114 ) /* (PDC_SPI0) Receive Next Counter Register */
+#define AT91C_SPI0_TNPR            ( ( AT91_REG * ) 0xFFFE0118 ) /* (PDC_SPI0) Transmit Next Pointer Register */
+/* ========== Register definition for SPI0 peripheral ========== */
+#define AT91C_SPI0_IER             ( ( AT91_REG * ) 0xFFFE0014 ) /* (SPI0) Interrupt Enable Register */
+#define AT91C_SPI0_SR              ( ( AT91_REG * ) 0xFFFE0010 ) /* (SPI0) Status Register */
+#define AT91C_SPI0_IDR             ( ( AT91_REG * ) 0xFFFE0018 ) /* (SPI0) Interrupt Disable Register */
+#define AT91C_SPI0_CR              ( ( AT91_REG * ) 0xFFFE0000 ) /* (SPI0) Control Register */
+#define AT91C_SPI0_MR              ( ( AT91_REG * ) 0xFFFE0004 ) /* (SPI0) Mode Register */
+#define AT91C_SPI0_IMR             ( ( AT91_REG * ) 0xFFFE001C ) /* (SPI0) Interrupt Mask Register */
+#define AT91C_SPI0_TDR             ( ( AT91_REG * ) 0xFFFE000C ) /* (SPI0) Transmit Data Register */
+#define AT91C_SPI0_RDR             ( ( AT91_REG * ) 0xFFFE0008 ) /* (SPI0) Receive Data Register */
+#define AT91C_SPI0_CSR             ( ( AT91_REG * ) 0xFFFE0030 ) /* (SPI0) Chip Select Register */
+/* ========== Register definition for PDC_US1 peripheral ========== */
+#define AT91C_US1_RNCR             ( ( AT91_REG * ) 0xFFFC4114 ) /* (PDC_US1) Receive Next Counter Register */
+#define AT91C_US1_PTCR             ( ( AT91_REG * ) 0xFFFC4120 ) /* (PDC_US1) PDC Transfer Control Register */
+#define AT91C_US1_TCR              ( ( AT91_REG * ) 0xFFFC410C ) /* (PDC_US1) Transmit Counter Register */
+#define AT91C_US1_PTSR             ( ( AT91_REG * ) 0xFFFC4124 ) /* (PDC_US1) PDC Transfer Status Register */
+#define AT91C_US1_TNPR             ( ( AT91_REG * ) 0xFFFC4118 ) /* (PDC_US1) Transmit Next Pointer Register */
+#define AT91C_US1_RCR              ( ( AT91_REG * ) 0xFFFC4104 ) /* (PDC_US1) Receive Counter Register */
+#define AT91C_US1_RNPR             ( ( AT91_REG * ) 0xFFFC4110 ) /* (PDC_US1) Receive Next Pointer Register */
+#define AT91C_US1_RPR              ( ( AT91_REG * ) 0xFFFC4100 ) /* (PDC_US1) Receive Pointer Register */
+#define AT91C_US1_TNCR             ( ( AT91_REG * ) 0xFFFC411C ) /* (PDC_US1) Transmit Next Counter Register */
+#define AT91C_US1_TPR              ( ( AT91_REG * ) 0xFFFC4108 ) /* (PDC_US1) Transmit Pointer Register */
+/* ========== Register definition for US1 peripheral ========== */
+#define AT91C_US1_IF               ( ( AT91_REG * ) 0xFFFC404C ) /* (US1) IRDA_FILTER Register */
+#define AT91C_US1_NER              ( ( AT91_REG * ) 0xFFFC4044 ) /* (US1) Nb Errors Register */
+#define AT91C_US1_RTOR             ( ( AT91_REG * ) 0xFFFC4024 ) /* (US1) Receiver Time-out Register */
+#define AT91C_US1_CSR              ( ( AT91_REG * ) 0xFFFC4014 ) /* (US1) Channel Status Register */
+#define AT91C_US1_IDR              ( ( AT91_REG * ) 0xFFFC400C ) /* (US1) Interrupt Disable Register */
+#define AT91C_US1_IER              ( ( AT91_REG * ) 0xFFFC4008 ) /* (US1) Interrupt Enable Register */
+#define AT91C_US1_THR              ( ( AT91_REG * ) 0xFFFC401C ) /* (US1) Transmitter Holding Register */
+#define AT91C_US1_TTGR             ( ( AT91_REG * ) 0xFFFC4028 ) /* (US1) Transmitter Time-guard Register */
+#define AT91C_US1_RHR              ( ( AT91_REG * ) 0xFFFC4018 ) /* (US1) Receiver Holding Register */
+#define AT91C_US1_BRGR             ( ( AT91_REG * ) 0xFFFC4020 ) /* (US1) Baud Rate Generator Register */
+#define AT91C_US1_IMR              ( ( AT91_REG * ) 0xFFFC4010 ) /* (US1) Interrupt Mask Register */
+#define AT91C_US1_FIDI             ( ( AT91_REG * ) 0xFFFC4040 ) /* (US1) FI_DI_Ratio Register */
+#define AT91C_US1_CR               ( ( AT91_REG * ) 0xFFFC4000 ) /* (US1) Control Register */
+#define AT91C_US1_MR               ( ( AT91_REG * ) 0xFFFC4004 ) /* (US1) Mode Register */
+/* ========== Register definition for PDC_US0 peripheral ========== */
+#define AT91C_US0_TNPR             ( ( AT91_REG * ) 0xFFFC0118 ) /* (PDC_US0) Transmit Next Pointer Register */
+#define AT91C_US0_RNPR             ( ( AT91_REG * ) 0xFFFC0110 ) /* (PDC_US0) Receive Next Pointer Register */
+#define AT91C_US0_TCR              ( ( AT91_REG * ) 0xFFFC010C ) /* (PDC_US0) Transmit Counter Register */
+#define AT91C_US0_PTCR             ( ( AT91_REG * ) 0xFFFC0120 ) /* (PDC_US0) PDC Transfer Control Register */
+#define AT91C_US0_PTSR             ( ( AT91_REG * ) 0xFFFC0124 ) /* (PDC_US0) PDC Transfer Status Register */
+#define AT91C_US0_TNCR             ( ( AT91_REG * ) 0xFFFC011C ) /* (PDC_US0) Transmit Next Counter Register */
+#define AT91C_US0_TPR              ( ( AT91_REG * ) 0xFFFC0108 ) /* (PDC_US0) Transmit Pointer Register */
+#define AT91C_US0_RCR              ( ( AT91_REG * ) 0xFFFC0104 ) /* (PDC_US0) Receive Counter Register */
+#define AT91C_US0_RPR              ( ( AT91_REG * ) 0xFFFC0100 ) /* (PDC_US0) Receive Pointer Register */
+#define AT91C_US0_RNCR             ( ( AT91_REG * ) 0xFFFC0114 ) /* (PDC_US0) Receive Next Counter Register */
+/* ========== Register definition for US0 peripheral ========== */
+#define AT91C_US0_BRGR             ( ( AT91_REG * ) 0xFFFC0020 ) /* (US0) Baud Rate Generator Register */
+#define AT91C_US0_NER              ( ( AT91_REG * ) 0xFFFC0044 ) /* (US0) Nb Errors Register */
+#define AT91C_US0_CR               ( ( AT91_REG * ) 0xFFFC0000 ) /* (US0) Control Register */
+#define AT91C_US0_IMR              ( ( AT91_REG * ) 0xFFFC0010 ) /* (US0) Interrupt Mask Register */
+#define AT91C_US0_FIDI             ( ( AT91_REG * ) 0xFFFC0040 ) /* (US0) FI_DI_Ratio Register */
+#define AT91C_US0_TTGR             ( ( AT91_REG * ) 0xFFFC0028 ) /* (US0) Transmitter Time-guard Register */
+#define AT91C_US0_MR               ( ( AT91_REG * ) 0xFFFC0004 ) /* (US0) Mode Register */
+#define AT91C_US0_RTOR             ( ( AT91_REG * ) 0xFFFC0024 ) /* (US0) Receiver Time-out Register */
+#define AT91C_US0_CSR              ( ( AT91_REG * ) 0xFFFC0014 ) /* (US0) Channel Status Register */
+#define AT91C_US0_RHR              ( ( AT91_REG * ) 0xFFFC0018 ) /* (US0) Receiver Holding Register */
+#define AT91C_US0_IDR              ( ( AT91_REG * ) 0xFFFC000C ) /* (US0) Interrupt Disable Register */
+#define AT91C_US0_THR              ( ( AT91_REG * ) 0xFFFC001C ) /* (US0) Transmitter Holding Register */
+#define AT91C_US0_IF               ( ( AT91_REG * ) 0xFFFC004C ) /* (US0) IRDA_FILTER Register */
+#define AT91C_US0_IER              ( ( AT91_REG * ) 0xFFFC0008 ) /* (US0) Interrupt Enable Register */
+/* ========== Register definition for PDC_SSC peripheral ========== */
+#define AT91C_SSC_TNCR             ( ( AT91_REG * ) 0xFFFD411C ) /* (PDC_SSC) Transmit Next Counter Register */
+#define AT91C_SSC_RPR              ( ( AT91_REG * ) 0xFFFD4100 ) /* (PDC_SSC) Receive Pointer Register */
+#define AT91C_SSC_RNCR             ( ( AT91_REG * ) 0xFFFD4114 ) /* (PDC_SSC) Receive Next Counter Register */
+#define AT91C_SSC_TPR              ( ( AT91_REG * ) 0xFFFD4108 ) /* (PDC_SSC) Transmit Pointer Register */
+#define AT91C_SSC_PTCR             ( ( AT91_REG * ) 0xFFFD4120 ) /* (PDC_SSC) PDC Transfer Control Register */
+#define AT91C_SSC_TCR              ( ( AT91_REG * ) 0xFFFD410C ) /* (PDC_SSC) Transmit Counter Register */
+#define AT91C_SSC_RCR              ( ( AT91_REG * ) 0xFFFD4104 ) /* (PDC_SSC) Receive Counter Register */
+#define AT91C_SSC_RNPR             ( ( AT91_REG * ) 0xFFFD4110 ) /* (PDC_SSC) Receive Next Pointer Register */
+#define AT91C_SSC_TNPR             ( ( AT91_REG * ) 0xFFFD4118 ) /* (PDC_SSC) Transmit Next Pointer Register */
+#define AT91C_SSC_PTSR             ( ( AT91_REG * ) 0xFFFD4124 ) /* (PDC_SSC) PDC Transfer Status Register */
+/* ========== Register definition for SSC peripheral ========== */
+#define AT91C_SSC_RHR              ( ( AT91_REG * ) 0xFFFD4020 ) /* (SSC) Receive Holding Register */
+#define AT91C_SSC_RSHR             ( ( AT91_REG * ) 0xFFFD4030 ) /* (SSC) Receive Sync Holding Register */
+#define AT91C_SSC_TFMR             ( ( AT91_REG * ) 0xFFFD401C ) /* (SSC) Transmit Frame Mode Register */
+#define AT91C_SSC_IDR              ( ( AT91_REG * ) 0xFFFD4048 ) /* (SSC) Interrupt Disable Register */
+#define AT91C_SSC_THR              ( ( AT91_REG * ) 0xFFFD4024 ) /* (SSC) Transmit Holding Register */
+#define AT91C_SSC_RCMR             ( ( AT91_REG * ) 0xFFFD4010 ) /* (SSC) Receive Clock ModeRegister */
+#define AT91C_SSC_IER              ( ( AT91_REG * ) 0xFFFD4044 ) /* (SSC) Interrupt Enable Register */
+#define AT91C_SSC_TSHR             ( ( AT91_REG * ) 0xFFFD4034 ) /* (SSC) Transmit Sync Holding Register */
+#define AT91C_SSC_SR               ( ( AT91_REG * ) 0xFFFD4040 ) /* (SSC) Status Register */
+#define AT91C_SSC_CMR              ( ( AT91_REG * ) 0xFFFD4004 ) /* (SSC) Clock Mode Register */
+#define AT91C_SSC_TCMR             ( ( AT91_REG * ) 0xFFFD4018 ) /* (SSC) Transmit Clock Mode Register */
+#define AT91C_SSC_CR               ( ( AT91_REG * ) 0xFFFD4000 ) /* (SSC) Control Register */
+#define AT91C_SSC_IMR              ( ( AT91_REG * ) 0xFFFD404C ) /* (SSC) Interrupt Mask Register */
+#define AT91C_SSC_RFMR             ( ( AT91_REG * ) 0xFFFD4014 ) /* (SSC) Receive Frame Mode Register */
+/* ========== Register definition for TWI peripheral ========== */
+#define AT91C_TWI_IER              ( ( AT91_REG * ) 0xFFFB8024 ) /* (TWI) Interrupt Enable Register */
+#define AT91C_TWI_CR               ( ( AT91_REG * ) 0xFFFB8000 ) /* (TWI) Control Register */
+#define AT91C_TWI_SR               ( ( AT91_REG * ) 0xFFFB8020 ) /* (TWI) Status Register */
+#define AT91C_TWI_IMR              ( ( AT91_REG * ) 0xFFFB802C ) /* (TWI) Interrupt Mask Register */
+#define AT91C_TWI_THR              ( ( AT91_REG * ) 0xFFFB8034 ) /* (TWI) Transmit Holding Register */
+#define AT91C_TWI_IDR              ( ( AT91_REG * ) 0xFFFB8028 ) /* (TWI) Interrupt Disable Register */
+#define AT91C_TWI_IADR             ( ( AT91_REG * ) 0xFFFB800C ) /* (TWI) Internal Address Register */
+#define AT91C_TWI_MMR              ( ( AT91_REG * ) 0xFFFB8004 ) /* (TWI) Master Mode Register */
+#define AT91C_TWI_CWGR             ( ( AT91_REG * ) 0xFFFB8010 ) /* (TWI) Clock Waveform Generator Register */
+#define AT91C_TWI_RHR              ( ( AT91_REG * ) 0xFFFB8030 ) /* (TWI) Receive Holding Register */
+/* ========== Register definition for PWMC_CH3 peripheral ========== */
+#define AT91C_PWMC_CH3_CUPDR       ( ( AT91_REG * ) 0xFFFCC270 ) /* (PWMC_CH3) Channel Update Register */
+#define AT91C_PWMC_CH3_Reserved    ( ( AT91_REG * ) 0xFFFCC274 ) /* (PWMC_CH3) Reserved */
+#define AT91C_PWMC_CH3_CPRDR       ( ( AT91_REG * ) 0xFFFCC268 ) /* (PWMC_CH3) Channel Period Register */
+#define AT91C_PWMC_CH3_CDTYR       ( ( AT91_REG * ) 0xFFFCC264 ) /* (PWMC_CH3) Channel Duty Cycle Register */
+#define AT91C_PWMC_CH3_CCNTR       ( ( AT91_REG * ) 0xFFFCC26C ) /* (PWMC_CH3) Channel Counter Register */
+#define AT91C_PWMC_CH3_CMR         ( ( AT91_REG * ) 0xFFFCC260 ) /* (PWMC_CH3) Channel Mode Register */
+/* ========== Register definition for PWMC_CH2 peripheral ========== */
+#define AT91C_PWMC_CH2_Reserved    ( ( AT91_REG * ) 0xFFFCC254 ) /* (PWMC_CH2) Reserved */
+#define AT91C_PWMC_CH2_CMR         ( ( AT91_REG * ) 0xFFFCC240 ) /* (PWMC_CH2) Channel Mode Register */
+#define AT91C_PWMC_CH2_CCNTR       ( ( AT91_REG * ) 0xFFFCC24C ) /* (PWMC_CH2) Channel Counter Register */
+#define AT91C_PWMC_CH2_CPRDR       ( ( AT91_REG * ) 0xFFFCC248 ) /* (PWMC_CH2) Channel Period Register */
+#define AT91C_PWMC_CH2_CUPDR       ( ( AT91_REG * ) 0xFFFCC250 ) /* (PWMC_CH2) Channel Update Register */
+#define AT91C_PWMC_CH2_CDTYR       ( ( AT91_REG * ) 0xFFFCC244 ) /* (PWMC_CH2) Channel Duty Cycle Register */
+/* ========== Register definition for PWMC_CH1 peripheral ========== */
+#define AT91C_PWMC_CH1_Reserved    ( ( AT91_REG * ) 0xFFFCC234 ) /* (PWMC_CH1) Reserved */
+#define AT91C_PWMC_CH1_CUPDR       ( ( AT91_REG * ) 0xFFFCC230 ) /* (PWMC_CH1) Channel Update Register */
+#define AT91C_PWMC_CH1_CPRDR       ( ( AT91_REG * ) 0xFFFCC228 ) /* (PWMC_CH1) Channel Period Register */
+#define AT91C_PWMC_CH1_CCNTR       ( ( AT91_REG * ) 0xFFFCC22C ) /* (PWMC_CH1) Channel Counter Register */
+#define AT91C_PWMC_CH1_CDTYR       ( ( AT91_REG * ) 0xFFFCC224 ) /* (PWMC_CH1) Channel Duty Cycle Register */
+#define AT91C_PWMC_CH1_CMR         ( ( AT91_REG * ) 0xFFFCC220 ) /* (PWMC_CH1) Channel Mode Register */
+/* ========== Register definition for PWMC_CH0 peripheral ========== */
+#define AT91C_PWMC_CH0_Reserved    ( ( AT91_REG * ) 0xFFFCC214 ) /* (PWMC_CH0) Reserved */
+#define AT91C_PWMC_CH0_CPRDR       ( ( AT91_REG * ) 0xFFFCC208 ) /* (PWMC_CH0) Channel Period Register */
+#define AT91C_PWMC_CH0_CDTYR       ( ( AT91_REG * ) 0xFFFCC204 ) /* (PWMC_CH0) Channel Duty Cycle Register */
+#define AT91C_PWMC_CH0_CMR         ( ( AT91_REG * ) 0xFFFCC200 ) /* (PWMC_CH0) Channel Mode Register */
+#define AT91C_PWMC_CH0_CUPDR       ( ( AT91_REG * ) 0xFFFCC210 ) /* (PWMC_CH0) Channel Update Register */
+#define AT91C_PWMC_CH0_CCNTR       ( ( AT91_REG * ) 0xFFFCC20C ) /* (PWMC_CH0) Channel Counter Register */
+/* ========== Register definition for PWMC peripheral ========== */
+#define AT91C_PWMC_IDR             ( ( AT91_REG * ) 0xFFFCC014 ) /* (PWMC) PWMC Interrupt Disable Register */
+#define AT91C_PWMC_DIS             ( ( AT91_REG * ) 0xFFFCC008 ) /* (PWMC) PWMC Disable Register */
+#define AT91C_PWMC_IER             ( ( AT91_REG * ) 0xFFFCC010 ) /* (PWMC) PWMC Interrupt Enable Register */
+#define AT91C_PWMC_VR              ( ( AT91_REG * ) 0xFFFCC0FC ) /* (PWMC) PWMC Version Register */
+#define AT91C_PWMC_ISR             ( ( AT91_REG * ) 0xFFFCC01C ) /* (PWMC) PWMC Interrupt Status Register */
+#define AT91C_PWMC_SR              ( ( AT91_REG * ) 0xFFFCC00C ) /* (PWMC) PWMC Status Register */
+#define AT91C_PWMC_IMR             ( ( AT91_REG * ) 0xFFFCC018 ) /* (PWMC) PWMC Interrupt Mask Register */
+#define AT91C_PWMC_MR              ( ( AT91_REG * ) 0xFFFCC000 ) /* (PWMC) PWMC Mode Register */
+#define AT91C_PWMC_ENA             ( ( AT91_REG * ) 0xFFFCC004 ) /* (PWMC) PWMC Enable Register */
+/* ========== Register definition for UDP peripheral ========== */
+#define AT91C_UDP_IMR              ( ( AT91_REG * ) 0xFFFB0018 ) /* (UDP) Interrupt Mask Register */
+#define AT91C_UDP_FADDR            ( ( AT91_REG * ) 0xFFFB0008 ) /* (UDP) Function Address Register */
+#define AT91C_UDP_NUM              ( ( AT91_REG * ) 0xFFFB0000 ) /* (UDP) Frame Number Register */
+#define AT91C_UDP_FDR              ( ( AT91_REG * ) 0xFFFB0050 ) /* (UDP) Endpoint FIFO Data Register */
+#define AT91C_UDP_ISR              ( ( AT91_REG * ) 0xFFFB001C ) /* (UDP) Interrupt Status Register */
+#define AT91C_UDP_CSR              ( ( AT91_REG * ) 0xFFFB0030 ) /* (UDP) Endpoint Control and Status Register */
+#define AT91C_UDP_IDR              ( ( AT91_REG * ) 0xFFFB0014 ) /* (UDP) Interrupt Disable Register */
+#define AT91C_UDP_ICR              ( ( AT91_REG * ) 0xFFFB0020 ) /* (UDP) Interrupt Clear Register */
+#define AT91C_UDP_RSTEP            ( ( AT91_REG * ) 0xFFFB0028 ) /* (UDP) Reset Endpoint Register */
+#define AT91C_UDP_TXVC             ( ( AT91_REG * ) 0xFFFB0074 ) /* (UDP) Transceiver Control Register */
+#define AT91C_UDP_GLBSTATE         ( ( AT91_REG * ) 0xFFFB0004 ) /* (UDP) Global State Register */
+#define AT91C_UDP_IER              ( ( AT91_REG * ) 0xFFFB0010 ) /* (UDP) Interrupt Enable Register */
+/* ========== Register definition for TC0 peripheral ========== */
+#define AT91C_TC0_SR               ( ( AT91_REG * ) 0xFFFA0020 ) /* (TC0) Status Register */
+#define AT91C_TC0_RC               ( ( AT91_REG * ) 0xFFFA001C ) /* (TC0) Register C */
+#define AT91C_TC0_RB               ( ( AT91_REG * ) 0xFFFA0018 ) /* (TC0) Register B */
+#define AT91C_TC0_CCR              ( ( AT91_REG * ) 0xFFFA0000 ) /* (TC0) Channel Control Register */
+#define AT91C_TC0_CMR              ( ( AT91_REG * ) 0xFFFA0004 ) /* (TC0) Channel Mode Register (Capture Mode / Waveform Mode) */
+#define AT91C_TC0_IER              ( ( AT91_REG * ) 0xFFFA0024 ) /* (TC0) Interrupt Enable Register */
+#define AT91C_TC0_RA               ( ( AT91_REG * ) 0xFFFA0014 ) /* (TC0) Register A */
+#define AT91C_TC0_IDR              ( ( AT91_REG * ) 0xFFFA0028 ) /* (TC0) Interrupt Disable Register */
+#define AT91C_TC0_CV               ( ( AT91_REG * ) 0xFFFA0010 ) /* (TC0) Counter Value */
+#define AT91C_TC0_IMR              ( ( AT91_REG * ) 0xFFFA002C ) /* (TC0) Interrupt Mask Register */
+/* ========== Register definition for TC1 peripheral ========== */
+#define AT91C_TC1_RB               ( ( AT91_REG * ) 0xFFFA0058 ) /* (TC1) Register B */
+#define AT91C_TC1_CCR              ( ( AT91_REG * ) 0xFFFA0040 ) /* (TC1) Channel Control Register */
+#define AT91C_TC1_IER              ( ( AT91_REG * ) 0xFFFA0064 ) /* (TC1) Interrupt Enable Register */
+#define AT91C_TC1_IDR              ( ( AT91_REG * ) 0xFFFA0068 ) /* (TC1) Interrupt Disable Register */
+#define AT91C_TC1_SR               ( ( AT91_REG * ) 0xFFFA0060 ) /* (TC1) Status Register */
+#define AT91C_TC1_CMR              ( ( AT91_REG * ) 0xFFFA0044 ) /* (TC1) Channel Mode Register (Capture Mode / Waveform Mode) */
+#define AT91C_TC1_RA               ( ( AT91_REG * ) 0xFFFA0054 ) /* (TC1) Register A */
+#define AT91C_TC1_RC               ( ( AT91_REG * ) 0xFFFA005C ) /* (TC1) Register C */
+#define AT91C_TC1_IMR              ( ( AT91_REG * ) 0xFFFA006C ) /* (TC1) Interrupt Mask Register */
+#define AT91C_TC1_CV               ( ( AT91_REG * ) 0xFFFA0050 ) /* (TC1) Counter Value */
+/* ========== Register definition for TC2 peripheral ========== */
+#define AT91C_TC2_CMR              ( ( AT91_REG * ) 0xFFFA0084 ) /* (TC2) Channel Mode Register (Capture Mode / Waveform Mode) */
+#define AT91C_TC2_CCR              ( ( AT91_REG * ) 0xFFFA0080 ) /* (TC2) Channel Control Register */
+#define AT91C_TC2_CV               ( ( AT91_REG * ) 0xFFFA0090 ) /* (TC2) Counter Value */
+#define AT91C_TC2_RA               ( ( AT91_REG * ) 0xFFFA0094 ) /* (TC2) Register A */
+#define AT91C_TC2_RB               ( ( AT91_REG * ) 0xFFFA0098 ) /* (TC2) Register B */
+#define AT91C_TC2_IDR              ( ( AT91_REG * ) 0xFFFA00A8 ) /* (TC2) Interrupt Disable Register */
+#define AT91C_TC2_IMR              ( ( AT91_REG * ) 0xFFFA00AC ) /* (TC2) Interrupt Mask Register */
+#define AT91C_TC2_RC               ( ( AT91_REG * ) 0xFFFA009C ) /* (TC2) Register C */
+#define AT91C_TC2_IER              ( ( AT91_REG * ) 0xFFFA00A4 ) /* (TC2) Interrupt Enable Register */
+#define AT91C_TC2_SR               ( ( AT91_REG * ) 0xFFFA00A0 ) /* (TC2) Status Register */
+/* ========== Register definition for TCB peripheral ========== */
+#define AT91C_TCB_BMR              ( ( AT91_REG * ) 0xFFFA00C4 ) /* (TCB) TC Block Mode Register */
+#define AT91C_TCB_BCR              ( ( AT91_REG * ) 0xFFFA00C0 ) /* (TCB) TC Block Control Register */
+/* ========== Register definition for CAN_MB0 peripheral ========== */
+#define AT91C_CAN_MB0_MDL          ( ( AT91_REG * ) 0xFFFD0214 ) /* (CAN_MB0) MailBox Data Low Register */
+#define AT91C_CAN_MB0_MAM          ( ( AT91_REG * ) 0xFFFD0204 ) /* (CAN_MB0) MailBox Acceptance Mask Register */
+#define AT91C_CAN_MB0_MCR          ( ( AT91_REG * ) 0xFFFD021C ) /* (CAN_MB0) MailBox Control Register */
+#define AT91C_CAN_MB0_MID          ( ( AT91_REG * ) 0xFFFD0208 ) /* (CAN_MB0) MailBox ID Register */
+#define AT91C_CAN_MB0_MSR          ( ( AT91_REG * ) 0xFFFD0210 ) /* (CAN_MB0) MailBox Status Register */
+#define AT91C_CAN_MB0_MFID         ( ( AT91_REG * ) 0xFFFD020C ) /* (CAN_MB0) MailBox Family ID Register */
+#define AT91C_CAN_MB0_MDH          ( ( AT91_REG * ) 0xFFFD0218 ) /* (CAN_MB0) MailBox Data High Register */
+#define AT91C_CAN_MB0_MMR          ( ( AT91_REG * ) 0xFFFD0200 ) /* (CAN_MB0) MailBox Mode Register */
+/* ========== Register definition for CAN_MB1 peripheral ========== */
+#define AT91C_CAN_MB1_MDL          ( ( AT91_REG * ) 0xFFFD0234 ) /* (CAN_MB1) MailBox Data Low Register */
+#define AT91C_CAN_MB1_MID          ( ( AT91_REG * ) 0xFFFD0228 ) /* (CAN_MB1) MailBox ID Register */
+#define AT91C_CAN_MB1_MMR          ( ( AT91_REG * ) 0xFFFD0220 ) /* (CAN_MB1) MailBox Mode Register */
+#define AT91C_CAN_MB1_MSR          ( ( AT91_REG * ) 0xFFFD0230 ) /* (CAN_MB1) MailBox Status Register */
+#define AT91C_CAN_MB1_MAM          ( ( AT91_REG * ) 0xFFFD0224 ) /* (CAN_MB1) MailBox Acceptance Mask Register */
+#define AT91C_CAN_MB1_MDH          ( ( AT91_REG * ) 0xFFFD0238 ) /* (CAN_MB1) MailBox Data High Register */
+#define AT91C_CAN_MB1_MCR          ( ( AT91_REG * ) 0xFFFD023C ) /* (CAN_MB1) MailBox Control Register */
+#define AT91C_CAN_MB1_MFID         ( ( AT91_REG * ) 0xFFFD022C ) /* (CAN_MB1) MailBox Family ID Register */
+/* ========== Register definition for CAN_MB2 peripheral ========== */
+#define AT91C_CAN_MB2_MCR          ( ( AT91_REG * ) 0xFFFD025C ) /* (CAN_MB2) MailBox Control Register */
+#define AT91C_CAN_MB2_MDH          ( ( AT91_REG * ) 0xFFFD0258 ) /* (CAN_MB2) MailBox Data High Register */
+#define AT91C_CAN_MB2_MID          ( ( AT91_REG * ) 0xFFFD0248 ) /* (CAN_MB2) MailBox ID Register */
+#define AT91C_CAN_MB2_MDL          ( ( AT91_REG * ) 0xFFFD0254 ) /* (CAN_MB2) MailBox Data Low Register */
+#define AT91C_CAN_MB2_MMR          ( ( AT91_REG * ) 0xFFFD0240 ) /* (CAN_MB2) MailBox Mode Register */
+#define AT91C_CAN_MB2_MAM          ( ( AT91_REG * ) 0xFFFD0244 ) /* (CAN_MB2) MailBox Acceptance Mask Register */
+#define AT91C_CAN_MB2_MFID         ( ( AT91_REG * ) 0xFFFD024C ) /* (CAN_MB2) MailBox Family ID Register */
+#define AT91C_CAN_MB2_MSR          ( ( AT91_REG * ) 0xFFFD0250 ) /* (CAN_MB2) MailBox Status Register */
+/* ========== Register definition for CAN_MB3 peripheral ========== */
+#define AT91C_CAN_MB3_MFID         ( ( AT91_REG * ) 0xFFFD026C ) /* (CAN_MB3) MailBox Family ID Register */
+#define AT91C_CAN_MB3_MAM          ( ( AT91_REG * ) 0xFFFD0264 ) /* (CAN_MB3) MailBox Acceptance Mask Register */
+#define AT91C_CAN_MB3_MID          ( ( AT91_REG * ) 0xFFFD0268 ) /* (CAN_MB3) MailBox ID Register */
+#define AT91C_CAN_MB3_MCR          ( ( AT91_REG * ) 0xFFFD027C ) /* (CAN_MB3) MailBox Control Register */
+#define AT91C_CAN_MB3_MMR          ( ( AT91_REG * ) 0xFFFD0260 ) /* (CAN_MB3) MailBox Mode Register */
+#define AT91C_CAN_MB3_MSR          ( ( AT91_REG * ) 0xFFFD0270 ) /* (CAN_MB3) MailBox Status Register */
+#define AT91C_CAN_MB3_MDL          ( ( AT91_REG * ) 0xFFFD0274 ) /* (CAN_MB3) MailBox Data Low Register */
+#define AT91C_CAN_MB3_MDH          ( ( AT91_REG * ) 0xFFFD0278 ) /* (CAN_MB3) MailBox Data High Register */
+/* ========== Register definition for CAN_MB4 peripheral ========== */
+#define AT91C_CAN_MB4_MID          ( ( AT91_REG * ) 0xFFFD0288 ) /* (CAN_MB4) MailBox ID Register */
+#define AT91C_CAN_MB4_MMR          ( ( AT91_REG * ) 0xFFFD0280 ) /* (CAN_MB4) MailBox Mode Register */
+#define AT91C_CAN_MB4_MDH          ( ( AT91_REG * ) 0xFFFD0298 ) /* (CAN_MB4) MailBox Data High Register */
+#define AT91C_CAN_MB4_MFID         ( ( AT91_REG * ) 0xFFFD028C ) /* (CAN_MB4) MailBox Family ID Register */
+#define AT91C_CAN_MB4_MSR          ( ( AT91_REG * ) 0xFFFD0290 ) /* (CAN_MB4) MailBox Status Register */
+#define AT91C_CAN_MB4_MCR          ( ( AT91_REG * ) 0xFFFD029C ) /* (CAN_MB4) MailBox Control Register */
+#define AT91C_CAN_MB4_MDL          ( ( AT91_REG * ) 0xFFFD0294 ) /* (CAN_MB4) MailBox Data Low Register */
+#define AT91C_CAN_MB4_MAM          ( ( AT91_REG * ) 0xFFFD0284 ) /* (CAN_MB4) MailBox Acceptance Mask Register */
+/* ========== Register definition for CAN_MB5 peripheral ========== */
+#define AT91C_CAN_MB5_MSR          ( ( AT91_REG * ) 0xFFFD02B0 ) /* (CAN_MB5) MailBox Status Register */
+#define AT91C_CAN_MB5_MCR          ( ( AT91_REG * ) 0xFFFD02BC ) /* (CAN_MB5) MailBox Control Register */
+#define AT91C_CAN_MB5_MFID         ( ( AT91_REG * ) 0xFFFD02AC ) /* (CAN_MB5) MailBox Family ID Register */
+#define AT91C_CAN_MB5_MDH          ( ( AT91_REG * ) 0xFFFD02B8 ) /* (CAN_MB5) MailBox Data High Register */
+#define AT91C_CAN_MB5_MID          ( ( AT91_REG * ) 0xFFFD02A8 ) /* (CAN_MB5) MailBox ID Register */
+#define AT91C_CAN_MB5_MMR          ( ( AT91_REG * ) 0xFFFD02A0 ) /* (CAN_MB5) MailBox Mode Register */
+#define AT91C_CAN_MB5_MDL          ( ( AT91_REG * ) 0xFFFD02B4 ) /* (CAN_MB5) MailBox Data Low Register */
+#define AT91C_CAN_MB5_MAM          ( ( AT91_REG * ) 0xFFFD02A4 ) /* (CAN_MB5) MailBox Acceptance Mask Register */
+/* ========== Register definition for CAN_MB6 peripheral ========== */
+#define AT91C_CAN_MB6_MFID         ( ( AT91_REG * ) 0xFFFD02CC ) /* (CAN_MB6) MailBox Family ID Register */
+#define AT91C_CAN_MB6_MID          ( ( AT91_REG * ) 0xFFFD02C8 ) /* (CAN_MB6) MailBox ID Register */
+#define AT91C_CAN_MB6_MAM          ( ( AT91_REG * ) 0xFFFD02C4 ) /* (CAN_MB6) MailBox Acceptance Mask Register */
+#define AT91C_CAN_MB6_MSR          ( ( AT91_REG * ) 0xFFFD02D0 ) /* (CAN_MB6) MailBox Status Register */
+#define AT91C_CAN_MB6_MDL          ( ( AT91_REG * ) 0xFFFD02D4 ) /* (CAN_MB6) MailBox Data Low Register */
+#define AT91C_CAN_MB6_MCR          ( ( AT91_REG * ) 0xFFFD02DC ) /* (CAN_MB6) MailBox Control Register */
+#define AT91C_CAN_MB6_MDH          ( ( AT91_REG * ) 0xFFFD02D8 ) /* (CAN_MB6) MailBox Data High Register */
+#define AT91C_CAN_MB6_MMR          ( ( AT91_REG * ) 0xFFFD02C0 ) /* (CAN_MB6) MailBox Mode Register */
+/* ========== Register definition for CAN_MB7 peripheral ========== */
+#define AT91C_CAN_MB7_MCR          ( ( AT91_REG * ) 0xFFFD02FC ) /* (CAN_MB7) MailBox Control Register */
+#define AT91C_CAN_MB7_MDH          ( ( AT91_REG * ) 0xFFFD02F8 ) /* (CAN_MB7) MailBox Data High Register */
+#define AT91C_CAN_MB7_MFID         ( ( AT91_REG * ) 0xFFFD02EC ) /* (CAN_MB7) MailBox Family ID Register */
+#define AT91C_CAN_MB7_MDL          ( ( AT91_REG * ) 0xFFFD02F4 ) /* (CAN_MB7) MailBox Data Low Register */
+#define AT91C_CAN_MB7_MID          ( ( AT91_REG * ) 0xFFFD02E8 ) /* (CAN_MB7) MailBox ID Register */
+#define AT91C_CAN_MB7_MMR          ( ( AT91_REG * ) 0xFFFD02E0 ) /* (CAN_MB7) MailBox Mode Register */
+#define AT91C_CAN_MB7_MAM          ( ( AT91_REG * ) 0xFFFD02E4 ) /* (CAN_MB7) MailBox Acceptance Mask Register */
+#define AT91C_CAN_MB7_MSR          ( ( AT91_REG * ) 0xFFFD02F0 ) /* (CAN_MB7) MailBox Status Register */
+/* ========== Register definition for CAN peripheral ========== */
+#define AT91C_CAN_TCR              ( ( AT91_REG * ) 0xFFFD0024 ) /* (CAN) Transfer Command Register */
+#define AT91C_CAN_IMR              ( ( AT91_REG * ) 0xFFFD000C ) /* (CAN) Interrupt Mask Register */
+#define AT91C_CAN_IER              ( ( AT91_REG * ) 0xFFFD0004 ) /* (CAN) Interrupt Enable Register */
+#define AT91C_CAN_ECR              ( ( AT91_REG * ) 0xFFFD0020 ) /* (CAN) Error Counter Register */
+#define AT91C_CAN_TIMESTP          ( ( AT91_REG * ) 0xFFFD001C ) /* (CAN) Time Stamp Register */
+#define AT91C_CAN_MR               ( ( AT91_REG * ) 0xFFFD0000 ) /* (CAN) Mode Register */
+#define AT91C_CAN_IDR              ( ( AT91_REG * ) 0xFFFD0008 ) /* (CAN) Interrupt Disable Register */
+#define AT91C_CAN_ACR              ( ( AT91_REG * ) 0xFFFD0028 ) /* (CAN) Abort Command Register */
+#define AT91C_CAN_TIM              ( ( AT91_REG * ) 0xFFFD0018 ) /* (CAN) Timer Register */
+#define AT91C_CAN_SR               ( ( AT91_REG * ) 0xFFFD0010 ) /* (CAN) Status Register */
+#define AT91C_CAN_BR               ( ( AT91_REG * ) 0xFFFD0014 ) /* (CAN) Baudrate Register */
+#define AT91C_CAN_VR               ( ( AT91_REG * ) 0xFFFD00FC ) /* (CAN) Version Register */
+/* ========== Register definition for EMAC peripheral ========== */
+#define AT91C_EMAC_ISR             ( ( AT91_REG * ) 0xFFFDC024 ) /* (EMAC) Interrupt Status Register */
+#define AT91C_EMAC_SA4H            ( ( AT91_REG * ) 0xFFFDC0B4 ) /* (EMAC) Specific Address 4 Top, Last 2 bytes */
+#define AT91C_EMAC_SA1L            ( ( AT91_REG * ) 0xFFFDC098 ) /* (EMAC) Specific Address 1 Bottom, First 4 bytes */
+#define AT91C_EMAC_ELE             ( ( AT91_REG * ) 0xFFFDC078 ) /* (EMAC) Excessive Length Errors Register */
+#define AT91C_EMAC_LCOL            ( ( AT91_REG * ) 0xFFFDC05C ) /* (EMAC) Late Collision Register */
+#define AT91C_EMAC_RLE             ( ( AT91_REG * ) 0xFFFDC088 ) /* (EMAC) Receive Length Field Mismatch Register */
+#define AT91C_EMAC_WOL             ( ( AT91_REG * ) 0xFFFDC0C4 ) /* (EMAC) Wake On LAN Register */
+#define AT91C_EMAC_DTF             ( ( AT91_REG * ) 0xFFFDC058 ) /* (EMAC) Deferred Transmission Frame Register */
+#define AT91C_EMAC_TUND            ( ( AT91_REG * ) 0xFFFDC064 ) /* (EMAC) Transmit Underrun Error Register */
+#define AT91C_EMAC_NCR             ( ( AT91_REG * ) 0xFFFDC000 ) /* (EMAC) Network Control Register */
+#define AT91C_EMAC_SA4L            ( ( AT91_REG * ) 0xFFFDC0B0 ) /* (EMAC) Specific Address 4 Bottom, First 4 bytes */
+#define AT91C_EMAC_RSR             ( ( AT91_REG * ) 0xFFFDC020 ) /* (EMAC) Receive Status Register */
+#define AT91C_EMAC_SA3L            ( ( AT91_REG * ) 0xFFFDC0A8 ) /* (EMAC) Specific Address 3 Bottom, First 4 bytes */
+#define AT91C_EMAC_TSR             ( ( AT91_REG * ) 0xFFFDC014 ) /* (EMAC) Transmit Status Register */
+#define AT91C_EMAC_IDR             ( ( AT91_REG * ) 0xFFFDC02C ) /* (EMAC) Interrupt Disable Register */
+#define AT91C_EMAC_RSE             ( ( AT91_REG * ) 0xFFFDC074 ) /* (EMAC) Receive Symbol Errors Register */
+#define AT91C_EMAC_ECOL            ( ( AT91_REG * ) 0xFFFDC060 ) /* (EMAC) Excessive Collision Register */
+#define AT91C_EMAC_TID             ( ( AT91_REG * ) 0xFFFDC0B8 ) /* (EMAC) Type ID Checking Register */
+#define AT91C_EMAC_HRB             ( ( AT91_REG * ) 0xFFFDC090 ) /* (EMAC) Hash Address Bottom[31:0] */
+#define AT91C_EMAC_TBQP            ( ( AT91_REG * ) 0xFFFDC01C ) /* (EMAC) Transmit Buffer Queue Pointer */
+#define AT91C_EMAC_USRIO           ( ( AT91_REG * ) 0xFFFDC0C0 ) /* (EMAC) USER Input/Output Register */
+#define AT91C_EMAC_PTR             ( ( AT91_REG * ) 0xFFFDC038 ) /* (EMAC) Pause Time Register */
+#define AT91C_EMAC_SA2H            ( ( AT91_REG * ) 0xFFFDC0A4 ) /* (EMAC) Specific Address 2 Top, Last 2 bytes */
+#define AT91C_EMAC_ROV             ( ( AT91_REG * ) 0xFFFDC070 ) /* (EMAC) Receive Overrun Errors Register */
+#define AT91C_EMAC_ALE             ( ( AT91_REG * ) 0xFFFDC054 ) /* (EMAC) Alignment Error Register */
+#define AT91C_EMAC_RJA             ( ( AT91_REG * ) 0xFFFDC07C ) /* (EMAC) Receive Jabbers Register */
+#define AT91C_EMAC_RBQP            ( ( AT91_REG * ) 0xFFFDC018 ) /* (EMAC) Receive Buffer Queue Pointer */
+#define AT91C_EMAC_TPF             ( ( AT91_REG * ) 0xFFFDC08C ) /* (EMAC) Transmitted Pause Frames Register */
+#define AT91C_EMAC_NCFGR           ( ( AT91_REG * ) 0xFFFDC004 ) /* (EMAC) Network Configuration Register */
+#define AT91C_EMAC_HRT             ( ( AT91_REG * ) 0xFFFDC094 ) /* (EMAC) Hash Address Top[63:32] */
+#define AT91C_EMAC_USF             ( ( AT91_REG * ) 0xFFFDC080 ) /* (EMAC) Undersize Frames Register */
+#define AT91C_EMAC_FCSE            ( ( AT91_REG * ) 0xFFFDC050 ) /* (EMAC) Frame Check Sequence Error Register */
+#define AT91C_EMAC_TPQ             ( ( AT91_REG * ) 0xFFFDC0BC ) /* (EMAC) Transmit Pause Quantum Register */
+#define AT91C_EMAC_MAN             ( ( AT91_REG * ) 0xFFFDC034 ) /* (EMAC) PHY Maintenance Register */
+#define AT91C_EMAC_FTO             ( ( AT91_REG * ) 0xFFFDC040 ) /* (EMAC) Frames Transmitted OK Register */
+#define AT91C_EMAC_REV             ( ( AT91_REG * ) 0xFFFDC0FC ) /* (EMAC) Revision Register */
+#define AT91C_EMAC_IMR             ( ( AT91_REG * ) 0xFFFDC030 ) /* (EMAC) Interrupt Mask Register */
+#define AT91C_EMAC_SCF             ( ( AT91_REG * ) 0xFFFDC044 ) /* (EMAC) Single Collision Frame Register */
+#define AT91C_EMAC_PFR             ( ( AT91_REG * ) 0xFFFDC03C ) /* (EMAC) Pause Frames received Register */
+#define AT91C_EMAC_MCF             ( ( AT91_REG * ) 0xFFFDC048 ) /* (EMAC) Multiple Collision Frame Register */
+#define AT91C_EMAC_NSR             ( ( AT91_REG * ) 0xFFFDC008 ) /* (EMAC) Network Status Register */
+#define AT91C_EMAC_SA2L            ( ( AT91_REG * ) 0xFFFDC0A0 ) /* (EMAC) Specific Address 2 Bottom, First 4 bytes */
+#define AT91C_EMAC_FRO             ( ( AT91_REG * ) 0xFFFDC04C ) /* (EMAC) Frames Received OK Register */
+#define AT91C_EMAC_IER             ( ( AT91_REG * ) 0xFFFDC028 ) /* (EMAC) Interrupt Enable Register */
+#define AT91C_EMAC_SA1H            ( ( AT91_REG * ) 0xFFFDC09C ) /* (EMAC) Specific Address 1 Top, Last 2 bytes */
+#define AT91C_EMAC_CSE             ( ( AT91_REG * ) 0xFFFDC068 ) /* (EMAC) Carrier Sense Error Register */
+#define AT91C_EMAC_SA3H            ( ( AT91_REG * ) 0xFFFDC0AC ) /* (EMAC) Specific Address 3 Top, Last 2 bytes */
+#define AT91C_EMAC_RRE             ( ( AT91_REG * ) 0xFFFDC06C ) /* (EMAC) Receive Ressource Error Register */
+#define AT91C_EMAC_STE             ( ( AT91_REG * ) 0xFFFDC084 ) /* (EMAC) SQE Test Error Register */
+/* ========== Register definition for PDC_ADC peripheral ========== */
+#define AT91C_ADC_PTSR             ( ( AT91_REG * ) 0xFFFD8124 ) /* (PDC_ADC) PDC Transfer Status Register */
+#define AT91C_ADC_PTCR             ( ( AT91_REG * ) 0xFFFD8120 ) /* (PDC_ADC) PDC Transfer Control Register */
+#define AT91C_ADC_TNPR             ( ( AT91_REG * ) 0xFFFD8118 ) /* (PDC_ADC) Transmit Next Pointer Register */
+#define AT91C_ADC_TNCR             ( ( AT91_REG * ) 0xFFFD811C ) /* (PDC_ADC) Transmit Next Counter Register */
+#define AT91C_ADC_RNPR             ( ( AT91_REG * ) 0xFFFD8110 ) /* (PDC_ADC) Receive Next Pointer Register */
+#define AT91C_ADC_RNCR             ( ( AT91_REG * ) 0xFFFD8114 ) /* (PDC_ADC) Receive Next Counter Register */
+#define AT91C_ADC_RPR              ( ( AT91_REG * ) 0xFFFD8100 ) /* (PDC_ADC) Receive Pointer Register */
+#define AT91C_ADC_TCR              ( ( AT91_REG * ) 0xFFFD810C ) /* (PDC_ADC) Transmit Counter Register */
+#define AT91C_ADC_TPR              ( ( AT91_REG * ) 0xFFFD8108 ) /* (PDC_ADC) Transmit Pointer Register */
+#define AT91C_ADC_RCR              ( ( AT91_REG * ) 0xFFFD8104 ) /* (PDC_ADC) Receive Counter Register */
+/* ========== Register definition for ADC peripheral ========== */
+#define AT91C_ADC_CDR2             ( ( AT91_REG * ) 0xFFFD8038 ) /* (ADC) ADC Channel Data Register 2 */
+#define AT91C_ADC_CDR3             ( ( AT91_REG * ) 0xFFFD803C ) /* (ADC) ADC Channel Data Register 3 */
+#define AT91C_ADC_CDR0             ( ( AT91_REG * ) 0xFFFD8030 ) /* (ADC) ADC Channel Data Register 0 */
+#define AT91C_ADC_CDR5             ( ( AT91_REG * ) 0xFFFD8044 ) /* (ADC) ADC Channel Data Register 5 */
+#define AT91C_ADC_CHDR             ( ( AT91_REG * ) 0xFFFD8014 ) /* (ADC) ADC Channel Disable Register */
+#define AT91C_ADC_SR               ( ( AT91_REG * ) 0xFFFD801C ) /* (ADC) ADC Status Register */
+#define AT91C_ADC_CDR4             ( ( AT91_REG * ) 0xFFFD8040 ) /* (ADC) ADC Channel Data Register 4 */
+#define AT91C_ADC_CDR1             ( ( AT91_REG * ) 0xFFFD8034 ) /* (ADC) ADC Channel Data Register 1 */
+#define AT91C_ADC_LCDR             ( ( AT91_REG * ) 0xFFFD8020 ) /* (ADC) ADC Last Converted Data Register */
+#define AT91C_ADC_IDR              ( ( AT91_REG * ) 0xFFFD8028 ) /* (ADC) ADC Interrupt Disable Register */
+#define AT91C_ADC_CR               ( ( AT91_REG * ) 0xFFFD8000 ) /* (ADC) ADC Control Register */
+#define AT91C_ADC_CDR7             ( ( AT91_REG * ) 0xFFFD804C ) /* (ADC) ADC Channel Data Register 7 */
+#define AT91C_ADC_CDR6             ( ( AT91_REG * ) 0xFFFD8048 ) /* (ADC) ADC Channel Data Register 6 */
+#define AT91C_ADC_IER              ( ( AT91_REG * ) 0xFFFD8024 ) /* (ADC) ADC Interrupt Enable Register */
+#define AT91C_ADC_CHER             ( ( AT91_REG * ) 0xFFFD8010 ) /* (ADC) ADC Channel Enable Register */
+#define AT91C_ADC_CHSR             ( ( AT91_REG * ) 0xFFFD8018 ) /* (ADC) ADC Channel Status Register */
+#define AT91C_ADC_MR               ( ( AT91_REG * ) 0xFFFD8004 ) /* (ADC) ADC Mode Register */
+#define AT91C_ADC_IMR              ( ( AT91_REG * ) 0xFFFD802C ) /* (ADC) ADC Interrupt Mask Register */
+/* ========== Register definition for PDC_AES peripheral ========== */
+#define AT91C_AES_TPR              ( ( AT91_REG * ) 0xFFFA4108 ) /* (PDC_AES) Transmit Pointer Register */
+#define AT91C_AES_PTCR             ( ( AT91_REG * ) 0xFFFA4120 ) /* (PDC_AES) PDC Transfer Control Register */
+#define AT91C_AES_RNPR             ( ( AT91_REG * ) 0xFFFA4110 ) /* (PDC_AES) Receive Next Pointer Register */
+#define AT91C_AES_TNCR             ( ( AT91_REG * ) 0xFFFA411C ) /* (PDC_AES) Transmit Next Counter Register */
+#define AT91C_AES_TCR              ( ( AT91_REG * ) 0xFFFA410C ) /* (PDC_AES) Transmit Counter Register */
+#define AT91C_AES_RCR              ( ( AT91_REG * ) 0xFFFA4104 ) /* (PDC_AES) Receive Counter Register */
+#define AT91C_AES_RNCR             ( ( AT91_REG * ) 0xFFFA4114 ) /* (PDC_AES) Receive Next Counter Register */
+#define AT91C_AES_TNPR             ( ( AT91_REG * ) 0xFFFA4118 ) /* (PDC_AES) Transmit Next Pointer Register */
+#define AT91C_AES_RPR              ( ( AT91_REG * ) 0xFFFA4100 ) /* (PDC_AES) Receive Pointer Register */
+#define AT91C_AES_PTSR             ( ( AT91_REG * ) 0xFFFA4124 ) /* (PDC_AES) PDC Transfer Status Register */
+/* ========== Register definition for AES peripheral ========== */
+#define AT91C_AES_IVxR             ( ( AT91_REG * ) 0xFFFA4060 ) /* (AES) Initialization Vector x Register */
+#define AT91C_AES_MR               ( ( AT91_REG * ) 0xFFFA4004 ) /* (AES) Mode Register */
+#define AT91C_AES_VR               ( ( AT91_REG * ) 0xFFFA40FC ) /* (AES) AES Version Register */
+#define AT91C_AES_ODATAxR          ( ( AT91_REG * ) 0xFFFA4050 ) /* (AES) Output Data x Register */
+#define AT91C_AES_IDATAxR          ( ( AT91_REG * ) 0xFFFA4040 ) /* (AES) Input Data x Register */
+#define AT91C_AES_CR               ( ( AT91_REG * ) 0xFFFA4000 ) /* (AES) Control Register */
+#define AT91C_AES_IDR              ( ( AT91_REG * ) 0xFFFA4014 ) /* (AES) Interrupt Disable Register */
+#define AT91C_AES_IMR              ( ( AT91_REG * ) 0xFFFA4018 ) /* (AES) Interrupt Mask Register */
+#define AT91C_AES_IER              ( ( AT91_REG * ) 0xFFFA4010 ) /* (AES) Interrupt Enable Register */
+#define AT91C_AES_KEYWxR           ( ( AT91_REG * ) 0xFFFA4020 ) /* (AES) Key Word x Register */
+#define AT91C_AES_ISR              ( ( AT91_REG * ) 0xFFFA401C ) /* (AES) Interrupt Status Register */
+/* ========== Register definition for PDC_TDES peripheral ========== */
+#define AT91C_TDES_RNCR            ( ( AT91_REG * ) 0xFFFA8114 ) /* (PDC_TDES) Receive Next Counter Register */
+#define AT91C_TDES_TCR             ( ( AT91_REG * ) 0xFFFA810C ) /* (PDC_TDES) Transmit Counter Register */
+#define AT91C_TDES_RCR             ( ( AT91_REG * ) 0xFFFA8104 ) /* (PDC_TDES) Receive Counter Register */
+#define AT91C_TDES_TNPR            ( ( AT91_REG * ) 0xFFFA8118 ) /* (PDC_TDES) Transmit Next Pointer Register */
+#define AT91C_TDES_RNPR            ( ( AT91_REG * ) 0xFFFA8110 ) /* (PDC_TDES) Receive Next Pointer Register */
+#define AT91C_TDES_RPR             ( ( AT91_REG * ) 0xFFFA8100 ) /* (PDC_TDES) Receive Pointer Register */
+#define AT91C_TDES_TNCR            ( ( AT91_REG * ) 0xFFFA811C ) /* (PDC_TDES) Transmit Next Counter Register */
+#define AT91C_TDES_TPR             ( ( AT91_REG * ) 0xFFFA8108 ) /* (PDC_TDES) Transmit Pointer Register */
+#define AT91C_TDES_PTSR            ( ( AT91_REG * ) 0xFFFA8124 ) /* (PDC_TDES) PDC Transfer Status Register */
+#define AT91C_TDES_PTCR            ( ( AT91_REG * ) 0xFFFA8120 ) /* (PDC_TDES) PDC Transfer Control Register */
+/* ========== Register definition for TDES peripheral ========== */
+#define AT91C_TDES_KEY2WxR         ( ( AT91_REG * ) 0xFFFA8028 ) /* (TDES) Key 2 Word x Register */
+#define AT91C_TDES_KEY3WxR         ( ( AT91_REG * ) 0xFFFA8030 ) /* (TDES) Key 3 Word x Register */
+#define AT91C_TDES_IDR             ( ( AT91_REG * ) 0xFFFA8014 ) /* (TDES) Interrupt Disable Register */
+#define AT91C_TDES_VR              ( ( AT91_REG * ) 0xFFFA80FC ) /* (TDES) TDES Version Register */
+#define AT91C_TDES_IVxR            ( ( AT91_REG * ) 0xFFFA8060 ) /* (TDES) Initialization Vector x Register */
+#define AT91C_TDES_ODATAxR         ( ( AT91_REG * ) 0xFFFA8050 ) /* (TDES) Output Data x Register */
+#define AT91C_TDES_IMR             ( ( AT91_REG * ) 0xFFFA8018 ) /* (TDES) Interrupt Mask Register */
+#define AT91C_TDES_MR              ( ( AT91_REG * ) 0xFFFA8004 ) /* (TDES) Mode Register */
+#define AT91C_TDES_CR              ( ( AT91_REG * ) 0xFFFA8000 ) /* (TDES) Control Register */
+#define AT91C_TDES_IER             ( ( AT91_REG * ) 0xFFFA8010 ) /* (TDES) Interrupt Enable Register */
+#define AT91C_TDES_ISR             ( ( AT91_REG * ) 0xFFFA801C ) /* (TDES) Interrupt Status Register */
+#define AT91C_TDES_IDATAxR         ( ( AT91_REG * ) 0xFFFA8040 ) /* (TDES) Input Data x Register */
+#define AT91C_TDES_KEY1WxR         ( ( AT91_REG * ) 0xFFFA8020 ) /* (TDES) Key 1 Word x Register */
 
-// *****************************************************************************
-//               PIO DEFINITIONS FOR AT91SAM7X128
-// *****************************************************************************
-#define AT91C_PIO_PA0        ((unsigned int) 1 <<  0) // Pin Controlled by PA0
-#define AT91C_PA0_RXD0     ((unsigned int) AT91C_PIO_PA0) //  USART 0 Receive Data
-#define AT91C_PIO_PA1        ((unsigned int) 1 <<  1) // Pin Controlled by PA1
-#define AT91C_PA1_TXD0     ((unsigned int) AT91C_PIO_PA1) //  USART 0 Transmit Data
-#define AT91C_PIO_PA10       ((unsigned int) 1 << 10) // Pin Controlled by PA10
-#define AT91C_PA10_TWD      ((unsigned int) AT91C_PIO_PA10) //  TWI Two-wire Serial Data
-#define AT91C_PIO_PA11       ((unsigned int) 1 << 11) // Pin Controlled by PA11
-#define AT91C_PA11_TWCK     ((unsigned int) AT91C_PIO_PA11) //  TWI Two-wire Serial Clock
-#define AT91C_PIO_PA12       ((unsigned int) 1 << 12) // Pin Controlled by PA12
-#define AT91C_PA12_NPCS00   ((unsigned int) AT91C_PIO_PA12) //  SPI 0 Peripheral Chip Select 0
-#define AT91C_PIO_PA13       ((unsigned int) 1 << 13) // Pin Controlled by PA13
-#define AT91C_PA13_NPCS01   ((unsigned int) AT91C_PIO_PA13) //  SPI 0 Peripheral Chip Select 1
-#define AT91C_PA13_PCK1     ((unsigned int) AT91C_PIO_PA13) //  PMC Programmable Clock Output 1
-#define AT91C_PIO_PA14       ((unsigned int) 1 << 14) // Pin Controlled by PA14
-#define AT91C_PA14_NPCS02   ((unsigned int) AT91C_PIO_PA14) //  SPI 0 Peripheral Chip Select 2
-#define AT91C_PA14_IRQ1     ((unsigned int) AT91C_PIO_PA14) //  External Interrupt 1
-#define AT91C_PIO_PA15       ((unsigned int) 1 << 15) // Pin Controlled by PA15
-#define AT91C_PA15_NPCS03   ((unsigned int) AT91C_PIO_PA15) //  SPI 0 Peripheral Chip Select 3
-#define AT91C_PA15_TCLK2    ((unsigned int) AT91C_PIO_PA15) //  Timer Counter 2 external clock input
-#define AT91C_PIO_PA16       ((unsigned int) 1 << 16) // Pin Controlled by PA16
-#define AT91C_PA16_MISO0    ((unsigned int) AT91C_PIO_PA16) //  SPI 0 Master In Slave
-#define AT91C_PIO_PA17       ((unsigned int) 1 << 17) // Pin Controlled by PA17
-#define AT91C_PA17_MOSI0    ((unsigned int) AT91C_PIO_PA17) //  SPI 0 Master Out Slave
-#define AT91C_PIO_PA18       ((unsigned int) 1 << 18) // Pin Controlled by PA18
-#define AT91C_PA18_SPCK0    ((unsigned int) AT91C_PIO_PA18) //  SPI 0 Serial Clock
-#define AT91C_PIO_PA19       ((unsigned int) 1 << 19) // Pin Controlled by PA19
-#define AT91C_PA19_CANRX    ((unsigned int) AT91C_PIO_PA19) //  CAN Receive
-#define AT91C_PIO_PA2        ((unsigned int) 1 <<  2) // Pin Controlled by PA2
-#define AT91C_PA2_SCK0     ((unsigned int) AT91C_PIO_PA2) //  USART 0 Serial Clock
-#define AT91C_PA2_NPCS11   ((unsigned int) AT91C_PIO_PA2) //  SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PA20       ((unsigned int) 1 << 20) // Pin Controlled by PA20
-#define AT91C_PA20_CANTX    ((unsigned int) AT91C_PIO_PA20) //  CAN Transmit
-#define AT91C_PIO_PA21       ((unsigned int) 1 << 21) // Pin Controlled by PA21
-#define AT91C_PA21_TF       ((unsigned int) AT91C_PIO_PA21) //  SSC Transmit Frame Sync
-#define AT91C_PA21_NPCS10   ((unsigned int) AT91C_PIO_PA21) //  SPI 1 Peripheral Chip Select 0
-#define AT91C_PIO_PA22       ((unsigned int) 1 << 22) // Pin Controlled by PA22
-#define AT91C_PA22_TK       ((unsigned int) AT91C_PIO_PA22) //  SSC Transmit Clock
-#define AT91C_PA22_SPCK1    ((unsigned int) AT91C_PIO_PA22) //  SPI 1 Serial Clock
-#define AT91C_PIO_PA23       ((unsigned int) 1 << 23) // Pin Controlled by PA23
-#define AT91C_PA23_TD       ((unsigned int) AT91C_PIO_PA23) //  SSC Transmit data
-#define AT91C_PA23_MOSI1    ((unsigned int) AT91C_PIO_PA23) //  SPI 1 Master Out Slave
-#define AT91C_PIO_PA24       ((unsigned int) 1 << 24) // Pin Controlled by PA24
-#define AT91C_PA24_RD       ((unsigned int) AT91C_PIO_PA24) //  SSC Receive Data
-#define AT91C_PA24_MISO1    ((unsigned int) AT91C_PIO_PA24) //  SPI 1 Master In Slave
-#define AT91C_PIO_PA25       ((unsigned int) 1 << 25) // Pin Controlled by PA25
-#define AT91C_PA25_RK       ((unsigned int) AT91C_PIO_PA25) //  SSC Receive Clock
-#define AT91C_PA25_NPCS11   ((unsigned int) AT91C_PIO_PA25) //  SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PA26       ((unsigned int) 1 << 26) // Pin Controlled by PA26
-#define AT91C_PA26_RF       ((unsigned int) AT91C_PIO_PA26) //  SSC Receive Frame Sync
-#define AT91C_PA26_NPCS12   ((unsigned int) AT91C_PIO_PA26) //  SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PA27       ((unsigned int) 1 << 27) // Pin Controlled by PA27
-#define AT91C_PA27_DRXD     ((unsigned int) AT91C_PIO_PA27) //  DBGU Debug Receive Data
-#define AT91C_PA27_PCK3     ((unsigned int) AT91C_PIO_PA27) //  PMC Programmable Clock Output 3
-#define AT91C_PIO_PA28       ((unsigned int) 1 << 28) // Pin Controlled by PA28
-#define AT91C_PA28_DTXD     ((unsigned int) AT91C_PIO_PA28) //  DBGU Debug Transmit Data
-#define AT91C_PIO_PA29       ((unsigned int) 1 << 29) // Pin Controlled by PA29
-#define AT91C_PA29_FIQ      ((unsigned int) AT91C_PIO_PA29) //  AIC Fast Interrupt Input
-#define AT91C_PA29_NPCS13   ((unsigned int) AT91C_PIO_PA29) //  SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PA3        ((unsigned int) 1 <<  3) // Pin Controlled by PA3
-#define AT91C_PA3_RTS0     ((unsigned int) AT91C_PIO_PA3) //  USART 0 Ready To Send
-#define AT91C_PA3_NPCS12   ((unsigned int) AT91C_PIO_PA3) //  SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PA30       ((unsigned int) 1 << 30) // Pin Controlled by PA30
-#define AT91C_PA30_IRQ0     ((unsigned int) AT91C_PIO_PA30) //  External Interrupt 0
-#define AT91C_PA30_PCK2     ((unsigned int) AT91C_PIO_PA30) //  PMC Programmable Clock Output 2
-#define AT91C_PIO_PA4        ((unsigned int) 1 <<  4) // Pin Controlled by PA4
-#define AT91C_PA4_CTS0     ((unsigned int) AT91C_PIO_PA4) //  USART 0 Clear To Send
-#define AT91C_PA4_NPCS13   ((unsigned int) AT91C_PIO_PA4) //  SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PA5        ((unsigned int) 1 <<  5) // Pin Controlled by PA5
-#define AT91C_PA5_RXD1     ((unsigned int) AT91C_PIO_PA5) //  USART 1 Receive Data
-#define AT91C_PIO_PA6        ((unsigned int) 1 <<  6) // Pin Controlled by PA6
-#define AT91C_PA6_TXD1     ((unsigned int) AT91C_PIO_PA6) //  USART 1 Transmit Data
-#define AT91C_PIO_PA7        ((unsigned int) 1 <<  7) // Pin Controlled by PA7
-#define AT91C_PA7_SCK1     ((unsigned int) AT91C_PIO_PA7) //  USART 1 Serial Clock
-#define AT91C_PA7_NPCS01   ((unsigned int) AT91C_PIO_PA7) //  SPI 0 Peripheral Chip Select 1
-#define AT91C_PIO_PA8        ((unsigned int) 1 <<  8) // Pin Controlled by PA8
-#define AT91C_PA8_RTS1     ((unsigned int) AT91C_PIO_PA8) //  USART 1 Ready To Send
-#define AT91C_PA8_NPCS02   ((unsigned int) AT91C_PIO_PA8) //  SPI 0 Peripheral Chip Select 2
-#define AT91C_PIO_PA9        ((unsigned int) 1 <<  9) // Pin Controlled by PA9
-#define AT91C_PA9_CTS1     ((unsigned int) AT91C_PIO_PA9) //  USART 1 Clear To Send
-#define AT91C_PA9_NPCS03   ((unsigned int) AT91C_PIO_PA9) //  SPI 0 Peripheral Chip Select 3
-#define AT91C_PIO_PB0        ((unsigned int) 1 <<  0) // Pin Controlled by PB0
-#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) //  Ethernet MAC Transmit Clock/Reference Clock
-#define AT91C_PB0_PCK0     ((unsigned int) AT91C_PIO_PB0) //  PMC Programmable Clock Output 0
-#define AT91C_PIO_PB1        ((unsigned int) 1 <<  1) // Pin Controlled by PB1
-#define AT91C_PB1_ETXEN    ((unsigned int) AT91C_PIO_PB1) //  Ethernet MAC Transmit Enable
-#define AT91C_PIO_PB10       ((unsigned int) 1 << 10) // Pin Controlled by PB10
-#define AT91C_PB10_ETX2     ((unsigned int) AT91C_PIO_PB10) //  Ethernet MAC Transmit Data 2
-#define AT91C_PB10_NPCS11   ((unsigned int) AT91C_PIO_PB10) //  SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PB11       ((unsigned int) 1 << 11) // Pin Controlled by PB11
-#define AT91C_PB11_ETX3     ((unsigned int) AT91C_PIO_PB11) //  Ethernet MAC Transmit Data 3
-#define AT91C_PB11_NPCS12   ((unsigned int) AT91C_PIO_PB11) //  SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PB12       ((unsigned int) 1 << 12) // Pin Controlled by PB12
-#define AT91C_PB12_ETXER    ((unsigned int) AT91C_PIO_PB12) //  Ethernet MAC Transmikt Coding Error
-#define AT91C_PB12_TCLK0    ((unsigned int) AT91C_PIO_PB12) //  Timer Counter 0 external clock input
-#define AT91C_PIO_PB13       ((unsigned int) 1 << 13) // Pin Controlled by PB13
-#define AT91C_PB13_ERX2     ((unsigned int) AT91C_PIO_PB13) //  Ethernet MAC Receive Data 2
-#define AT91C_PB13_NPCS01   ((unsigned int) AT91C_PIO_PB13) //  SPI 0 Peripheral Chip Select 1
-#define AT91C_PIO_PB14       ((unsigned int) 1 << 14) // Pin Controlled by PB14
-#define AT91C_PB14_ERX3     ((unsigned int) AT91C_PIO_PB14) //  Ethernet MAC Receive Data 3
-#define AT91C_PB14_NPCS02   ((unsigned int) AT91C_PIO_PB14) //  SPI 0 Peripheral Chip Select 2
-#define AT91C_PIO_PB15       ((unsigned int) 1 << 15) // Pin Controlled by PB15
-#define AT91C_PB15_ERXDV    ((unsigned int) AT91C_PIO_PB15) //  Ethernet MAC Receive Data Valid
-#define AT91C_PIO_PB16       ((unsigned int) 1 << 16) // Pin Controlled by PB16
-#define AT91C_PB16_ECOL     ((unsigned int) AT91C_PIO_PB16) //  Ethernet MAC Collision Detected
-#define AT91C_PB16_NPCS13   ((unsigned int) AT91C_PIO_PB16) //  SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PB17       ((unsigned int) 1 << 17) // Pin Controlled by PB17
-#define AT91C_PB17_ERXCK    ((unsigned int) AT91C_PIO_PB17) //  Ethernet MAC Receive Clock
-#define AT91C_PB17_NPCS03   ((unsigned int) AT91C_PIO_PB17) //  SPI 0 Peripheral Chip Select 3
-#define AT91C_PIO_PB18       ((unsigned int) 1 << 18) // Pin Controlled by PB18
-#define AT91C_PB18_EF100    ((unsigned int) AT91C_PIO_PB18) //  Ethernet MAC Force 100 Mbits/sec
-#define AT91C_PB18_ADTRG    ((unsigned int) AT91C_PIO_PB18) //  ADC External Trigger
-#define AT91C_PIO_PB19       ((unsigned int) 1 << 19) // Pin Controlled by PB19
-#define AT91C_PB19_PWM0     ((unsigned int) AT91C_PIO_PB19) //  PWM Channel 0
-#define AT91C_PB19_TCLK1    ((unsigned int) AT91C_PIO_PB19) //  Timer Counter 1 external clock input
-#define AT91C_PIO_PB2        ((unsigned int) 1 <<  2) // Pin Controlled by PB2
-#define AT91C_PB2_ETX0     ((unsigned int) AT91C_PIO_PB2) //  Ethernet MAC Transmit Data 0
-#define AT91C_PIO_PB20       ((unsigned int) 1 << 20) // Pin Controlled by PB20
-#define AT91C_PB20_PWM1     ((unsigned int) AT91C_PIO_PB20) //  PWM Channel 1
-#define AT91C_PB20_PCK0     ((unsigned int) AT91C_PIO_PB20) //  PMC Programmable Clock Output 0
-#define AT91C_PIO_PB21       ((unsigned int) 1 << 21) // Pin Controlled by PB21
-#define AT91C_PB21_PWM2     ((unsigned int) AT91C_PIO_PB21) //  PWM Channel 2
-#define AT91C_PB21_PCK1     ((unsigned int) AT91C_PIO_PB21) //  PMC Programmable Clock Output 1
-#define AT91C_PIO_PB22       ((unsigned int) 1 << 22) // Pin Controlled by PB22
-#define AT91C_PB22_PWM3     ((unsigned int) AT91C_PIO_PB22) //  PWM Channel 3
-#define AT91C_PB22_PCK2     ((unsigned int) AT91C_PIO_PB22) //  PMC Programmable Clock Output 2
-#define AT91C_PIO_PB23       ((unsigned int) 1 << 23) // Pin Controlled by PB23
-#define AT91C_PB23_TIOA0    ((unsigned int) AT91C_PIO_PB23) //  Timer Counter 0 Multipurpose Timer I/O Pin A
-#define AT91C_PB23_DCD1     ((unsigned int) AT91C_PIO_PB23) //  USART 1 Data Carrier Detect
-#define AT91C_PIO_PB24       ((unsigned int) 1 << 24) // Pin Controlled by PB24
-#define AT91C_PB24_TIOB0    ((unsigned int) AT91C_PIO_PB24) //  Timer Counter 0 Multipurpose Timer I/O Pin B
-#define AT91C_PB24_DSR1     ((unsigned int) AT91C_PIO_PB24) //  USART 1 Data Set ready
-#define AT91C_PIO_PB25       ((unsigned int) 1 << 25) // Pin Controlled by PB25
-#define AT91C_PB25_TIOA1    ((unsigned int) AT91C_PIO_PB25) //  Timer Counter 1 Multipurpose Timer I/O Pin A
-#define AT91C_PB25_DTR1     ((unsigned int) AT91C_PIO_PB25) //  USART 1 Data Terminal ready
-#define AT91C_PIO_PB26       ((unsigned int) 1 << 26) // Pin Controlled by PB26
-#define AT91C_PB26_TIOB1    ((unsigned int) AT91C_PIO_PB26) //  Timer Counter 1 Multipurpose Timer I/O Pin B
-#define AT91C_PB26_RI1      ((unsigned int) AT91C_PIO_PB26) //  USART 1 Ring Indicator
-#define AT91C_PIO_PB27       ((unsigned int) 1 << 27) // Pin Controlled by PB27
-#define AT91C_PB27_TIOA2    ((unsigned int) AT91C_PIO_PB27) //  Timer Counter 2 Multipurpose Timer I/O Pin A
-#define AT91C_PB27_PWM0     ((unsigned int) AT91C_PIO_PB27) //  PWM Channel 0
-#define AT91C_PIO_PB28       ((unsigned int) 1 << 28) // Pin Controlled by PB28
-#define AT91C_PB28_TIOB2    ((unsigned int) AT91C_PIO_PB28) //  Timer Counter 2 Multipurpose Timer I/O Pin B
-#define AT91C_PB28_PWM1     ((unsigned int) AT91C_PIO_PB28) //  PWM Channel 1
-#define AT91C_PIO_PB29       ((unsigned int) 1 << 29) // Pin Controlled by PB29
-#define AT91C_PB29_PCK1     ((unsigned int) AT91C_PIO_PB29) //  PMC Programmable Clock Output 1
-#define AT91C_PB29_PWM2     ((unsigned int) AT91C_PIO_PB29) //  PWM Channel 2
-#define AT91C_PIO_PB3        ((unsigned int) 1 <<  3) // Pin Controlled by PB3
-#define AT91C_PB3_ETX1     ((unsigned int) AT91C_PIO_PB3) //  Ethernet MAC Transmit Data 1
-#define AT91C_PIO_PB30       ((unsigned int) 1 << 30) // Pin Controlled by PB30
-#define AT91C_PB30_PCK2     ((unsigned int) AT91C_PIO_PB30) //  PMC Programmable Clock Output 2
-#define AT91C_PB30_PWM3     ((unsigned int) AT91C_PIO_PB30) //  PWM Channel 3
-#define AT91C_PIO_PB4        ((unsigned int) 1 <<  4) // Pin Controlled by PB4
-#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) //  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
-#define AT91C_PIO_PB5        ((unsigned int) 1 <<  5) // Pin Controlled by PB5
-#define AT91C_PB5_ERX0     ((unsigned int) AT91C_PIO_PB5) //  Ethernet MAC Receive Data 0
-#define AT91C_PIO_PB6        ((unsigned int) 1 <<  6) // Pin Controlled by PB6
-#define AT91C_PB6_ERX1     ((unsigned int) AT91C_PIO_PB6) //  Ethernet MAC Receive Data 1
-#define AT91C_PIO_PB7        ((unsigned int) 1 <<  7) // Pin Controlled by PB7
-#define AT91C_PB7_ERXER    ((unsigned int) AT91C_PIO_PB7) //  Ethernet MAC Receive Error
-#define AT91C_PIO_PB8        ((unsigned int) 1 <<  8) // Pin Controlled by PB8
-#define AT91C_PB8_EMDC     ((unsigned int) AT91C_PIO_PB8) //  Ethernet MAC Management Data Clock
-#define AT91C_PIO_PB9        ((unsigned int) 1 <<  9) // Pin Controlled by PB9
-#define AT91C_PB9_EMDIO    ((unsigned int) AT91C_PIO_PB9) //  Ethernet MAC Management Data Input/Output
+/* ***************************************************************************** */
+/*               PIO DEFINITIONS FOR AT91SAM7X128 */
+/* ***************************************************************************** */
+#define AT91C_PIO_PA0             ( ( unsigned int ) 1 << 0 )         /* Pin Controlled by PA0 */
+#define AT91C_PA0_RXD0            ( ( unsigned int ) AT91C_PIO_PA0 )  /*  USART 0 Receive Data */
+#define AT91C_PIO_PA1             ( ( unsigned int ) 1 << 1 )         /* Pin Controlled by PA1 */
+#define AT91C_PA1_TXD0            ( ( unsigned int ) AT91C_PIO_PA1 )  /*  USART 0 Transmit Data */
+#define AT91C_PIO_PA10            ( ( unsigned int ) 1 << 10 )        /* Pin Controlled by PA10 */
+#define AT91C_PA10_TWD            ( ( unsigned int ) AT91C_PIO_PA10 ) /*  TWI Two-wire Serial Data */
+#define AT91C_PIO_PA11            ( ( unsigned int ) 1 << 11 )        /* Pin Controlled by PA11 */
+#define AT91C_PA11_TWCK           ( ( unsigned int ) AT91C_PIO_PA11 ) /*  TWI Two-wire Serial Clock */
+#define AT91C_PIO_PA12            ( ( unsigned int ) 1 << 12 )        /* Pin Controlled by PA12 */
+#define AT91C_PA12_NPCS00         ( ( unsigned int ) AT91C_PIO_PA12 ) /*  SPI 0 Peripheral Chip Select 0 */
+#define AT91C_PIO_PA13            ( ( unsigned int ) 1 << 13 )        /* Pin Controlled by PA13 */
+#define AT91C_PA13_NPCS01         ( ( unsigned int ) AT91C_PIO_PA13 ) /*  SPI 0 Peripheral Chip Select 1 */
+#define AT91C_PA13_PCK1           ( ( unsigned int ) AT91C_PIO_PA13 ) /*  PMC Programmable Clock Output 1 */
+#define AT91C_PIO_PA14            ( ( unsigned int ) 1 << 14 )        /* Pin Controlled by PA14 */
+#define AT91C_PA14_NPCS02         ( ( unsigned int ) AT91C_PIO_PA14 ) /*  SPI 0 Peripheral Chip Select 2 */
+#define AT91C_PA14_IRQ1           ( ( unsigned int ) AT91C_PIO_PA14 ) /*  External Interrupt 1 */
+#define AT91C_PIO_PA15            ( ( unsigned int ) 1 << 15 )        /* Pin Controlled by PA15 */
+#define AT91C_PA15_NPCS03         ( ( unsigned int ) AT91C_PIO_PA15 ) /*  SPI 0 Peripheral Chip Select 3 */
+#define AT91C_PA15_TCLK2          ( ( unsigned int ) AT91C_PIO_PA15 ) /*  Timer Counter 2 external clock input */
+#define AT91C_PIO_PA16            ( ( unsigned int ) 1 << 16 )        /* Pin Controlled by PA16 */
+#define AT91C_PA16_MISO0          ( ( unsigned int ) AT91C_PIO_PA16 ) /*  SPI 0 Master In Slave */
+#define AT91C_PIO_PA17            ( ( unsigned int ) 1 << 17 )        /* Pin Controlled by PA17 */
+#define AT91C_PA17_MOSI0          ( ( unsigned int ) AT91C_PIO_PA17 ) /*  SPI 0 Master Out Slave */
+#define AT91C_PIO_PA18            ( ( unsigned int ) 1 << 18 )        /* Pin Controlled by PA18 */
+#define AT91C_PA18_SPCK0          ( ( unsigned int ) AT91C_PIO_PA18 ) /*  SPI 0 Serial Clock */
+#define AT91C_PIO_PA19            ( ( unsigned int ) 1 << 19 )        /* Pin Controlled by PA19 */
+#define AT91C_PA19_CANRX          ( ( unsigned int ) AT91C_PIO_PA19 ) /*  CAN Receive */
+#define AT91C_PIO_PA2             ( ( unsigned int ) 1 << 2 )         /* Pin Controlled by PA2 */
+#define AT91C_PA2_SCK0            ( ( unsigned int ) AT91C_PIO_PA2 )  /*  USART 0 Serial Clock */
+#define AT91C_PA2_NPCS11          ( ( unsigned int ) AT91C_PIO_PA2 )  /*  SPI 1 Peripheral Chip Select 1 */
+#define AT91C_PIO_PA20            ( ( unsigned int ) 1 << 20 )        /* Pin Controlled by PA20 */
+#define AT91C_PA20_CANTX          ( ( unsigned int ) AT91C_PIO_PA20 ) /*  CAN Transmit */
+#define AT91C_PIO_PA21            ( ( unsigned int ) 1 << 21 )        /* Pin Controlled by PA21 */
+#define AT91C_PA21_TF             ( ( unsigned int ) AT91C_PIO_PA21 ) /*  SSC Transmit Frame Sync */
+#define AT91C_PA21_NPCS10         ( ( unsigned int ) AT91C_PIO_PA21 ) /*  SPI 1 Peripheral Chip Select 0 */
+#define AT91C_PIO_PA22            ( ( unsigned int ) 1 << 22 )        /* Pin Controlled by PA22 */
+#define AT91C_PA22_TK             ( ( unsigned int ) AT91C_PIO_PA22 ) /*  SSC Transmit Clock */
+#define AT91C_PA22_SPCK1          ( ( unsigned int ) AT91C_PIO_PA22 ) /*  SPI 1 Serial Clock */
+#define AT91C_PIO_PA23            ( ( unsigned int ) 1 << 23 )        /* Pin Controlled by PA23 */
+#define AT91C_PA23_TD             ( ( unsigned int ) AT91C_PIO_PA23 ) /*  SSC Transmit data */
+#define AT91C_PA23_MOSI1          ( ( unsigned int ) AT91C_PIO_PA23 ) /*  SPI 1 Master Out Slave */
+#define AT91C_PIO_PA24            ( ( unsigned int ) 1 << 24 )        /* Pin Controlled by PA24 */
+#define AT91C_PA24_RD             ( ( unsigned int ) AT91C_PIO_PA24 ) /*  SSC Receive Data */
+#define AT91C_PA24_MISO1          ( ( unsigned int ) AT91C_PIO_PA24 ) /*  SPI 1 Master In Slave */
+#define AT91C_PIO_PA25            ( ( unsigned int ) 1 << 25 )        /* Pin Controlled by PA25 */
+#define AT91C_PA25_RK             ( ( unsigned int ) AT91C_PIO_PA25 ) /*  SSC Receive Clock */
+#define AT91C_PA25_NPCS11         ( ( unsigned int ) AT91C_PIO_PA25 ) /*  SPI 1 Peripheral Chip Select 1 */
+#define AT91C_PIO_PA26            ( ( unsigned int ) 1 << 26 )        /* Pin Controlled by PA26 */
+#define AT91C_PA26_RF             ( ( unsigned int ) AT91C_PIO_PA26 ) /*  SSC Receive Frame Sync */
+#define AT91C_PA26_NPCS12         ( ( unsigned int ) AT91C_PIO_PA26 ) /*  SPI 1 Peripheral Chip Select 2 */
+#define AT91C_PIO_PA27            ( ( unsigned int ) 1 << 27 )        /* Pin Controlled by PA27 */
+#define AT91C_PA27_DRXD           ( ( unsigned int ) AT91C_PIO_PA27 ) /*  DBGU Debug Receive Data */
+#define AT91C_PA27_PCK3           ( ( unsigned int ) AT91C_PIO_PA27 ) /*  PMC Programmable Clock Output 3 */
+#define AT91C_PIO_PA28            ( ( unsigned int ) 1 << 28 )        /* Pin Controlled by PA28 */
+#define AT91C_PA28_DTXD           ( ( unsigned int ) AT91C_PIO_PA28 ) /*  DBGU Debug Transmit Data */
+#define AT91C_PIO_PA29            ( ( unsigned int ) 1 << 29 )        /* Pin Controlled by PA29 */
+#define AT91C_PA29_FIQ            ( ( unsigned int ) AT91C_PIO_PA29 ) /*  AIC Fast Interrupt Input */
+#define AT91C_PA29_NPCS13         ( ( unsigned int ) AT91C_PIO_PA29 ) /*  SPI 1 Peripheral Chip Select 3 */
+#define AT91C_PIO_PA3             ( ( unsigned int ) 1 << 3 )         /* Pin Controlled by PA3 */
+#define AT91C_PA3_RTS0            ( ( unsigned int ) AT91C_PIO_PA3 )  /*  USART 0 Ready To Send */
+#define AT91C_PA3_NPCS12          ( ( unsigned int ) AT91C_PIO_PA3 )  /*  SPI 1 Peripheral Chip Select 2 */
+#define AT91C_PIO_PA30            ( ( unsigned int ) 1 << 30 )        /* Pin Controlled by PA30 */
+#define AT91C_PA30_IRQ0           ( ( unsigned int ) AT91C_PIO_PA30 ) /*  External Interrupt 0 */
+#define AT91C_PA30_PCK2           ( ( unsigned int ) AT91C_PIO_PA30 ) /*  PMC Programmable Clock Output 2 */
+#define AT91C_PIO_PA4             ( ( unsigned int ) 1 << 4 )         /* Pin Controlled by PA4 */
+#define AT91C_PA4_CTS0            ( ( unsigned int ) AT91C_PIO_PA4 )  /*  USART 0 Clear To Send */
+#define AT91C_PA4_NPCS13          ( ( unsigned int ) AT91C_PIO_PA4 )  /*  SPI 1 Peripheral Chip Select 3 */
+#define AT91C_PIO_PA5             ( ( unsigned int ) 1 << 5 )         /* Pin Controlled by PA5 */
+#define AT91C_PA5_RXD1            ( ( unsigned int ) AT91C_PIO_PA5 )  /*  USART 1 Receive Data */
+#define AT91C_PIO_PA6             ( ( unsigned int ) 1 << 6 )         /* Pin Controlled by PA6 */
+#define AT91C_PA6_TXD1            ( ( unsigned int ) AT91C_PIO_PA6 )  /*  USART 1 Transmit Data */
+#define AT91C_PIO_PA7             ( ( unsigned int ) 1 << 7 )         /* Pin Controlled by PA7 */
+#define AT91C_PA7_SCK1            ( ( unsigned int ) AT91C_PIO_PA7 )  /*  USART 1 Serial Clock */
+#define AT91C_PA7_NPCS01          ( ( unsigned int ) AT91C_PIO_PA7 )  /*  SPI 0 Peripheral Chip Select 1 */
+#define AT91C_PIO_PA8             ( ( unsigned int ) 1 << 8 )         /* Pin Controlled by PA8 */
+#define AT91C_PA8_RTS1            ( ( unsigned int ) AT91C_PIO_PA8 )  /*  USART 1 Ready To Send */
+#define AT91C_PA8_NPCS02          ( ( unsigned int ) AT91C_PIO_PA8 )  /*  SPI 0 Peripheral Chip Select 2 */
+#define AT91C_PIO_PA9             ( ( unsigned int ) 1 << 9 )         /* Pin Controlled by PA9 */
+#define AT91C_PA9_CTS1            ( ( unsigned int ) AT91C_PIO_PA9 )  /*  USART 1 Clear To Send */
+#define AT91C_PA9_NPCS03          ( ( unsigned int ) AT91C_PIO_PA9 )  /*  SPI 0 Peripheral Chip Select 3 */
+#define AT91C_PIO_PB0             ( ( unsigned int ) 1 << 0 )         /* Pin Controlled by PB0 */
+#define AT91C_PB0_ETXCK_EREFCK    ( ( unsigned int ) AT91C_PIO_PB0 )  /*  Ethernet MAC Transmit Clock/Reference Clock */
+#define AT91C_PB0_PCK0            ( ( unsigned int ) AT91C_PIO_PB0 )  /*  PMC Programmable Clock Output 0 */
+#define AT91C_PIO_PB1             ( ( unsigned int ) 1 << 1 )         /* Pin Controlled by PB1 */
+#define AT91C_PB1_ETXEN           ( ( unsigned int ) AT91C_PIO_PB1 )  /*  Ethernet MAC Transmit Enable */
+#define AT91C_PIO_PB10            ( ( unsigned int ) 1 << 10 )        /* Pin Controlled by PB10 */
+#define AT91C_PB10_ETX2           ( ( unsigned int ) AT91C_PIO_PB10 ) /*  Ethernet MAC Transmit Data 2 */
+#define AT91C_PB10_NPCS11         ( ( unsigned int ) AT91C_PIO_PB10 ) /*  SPI 1 Peripheral Chip Select 1 */
+#define AT91C_PIO_PB11            ( ( unsigned int ) 1 << 11 )        /* Pin Controlled by PB11 */
+#define AT91C_PB11_ETX3           ( ( unsigned int ) AT91C_PIO_PB11 ) /*  Ethernet MAC Transmit Data 3 */
+#define AT91C_PB11_NPCS12         ( ( unsigned int ) AT91C_PIO_PB11 ) /*  SPI 1 Peripheral Chip Select 2 */
+#define AT91C_PIO_PB12            ( ( unsigned int ) 1 << 12 )        /* Pin Controlled by PB12 */
+#define AT91C_PB12_ETXER          ( ( unsigned int ) AT91C_PIO_PB12 ) /*  Ethernet MAC Transmit Coding Error */
+#define AT91C_PB12_TCLK0          ( ( unsigned int ) AT91C_PIO_PB12 ) /*  Timer Counter 0 external clock input */
+#define AT91C_PIO_PB13            ( ( unsigned int ) 1 << 13 )        /* Pin Controlled by PB13 */
+#define AT91C_PB13_ERX2           ( ( unsigned int ) AT91C_PIO_PB13 ) /*  Ethernet MAC Receive Data 2 */
+#define AT91C_PB13_NPCS01         ( ( unsigned int ) AT91C_PIO_PB13 ) /*  SPI 0 Peripheral Chip Select 1 */
+#define AT91C_PIO_PB14            ( ( unsigned int ) 1 << 14 )        /* Pin Controlled by PB14 */
+#define AT91C_PB14_ERX3           ( ( unsigned int ) AT91C_PIO_PB14 ) /*  Ethernet MAC Receive Data 3 */
+#define AT91C_PB14_NPCS02         ( ( unsigned int ) AT91C_PIO_PB14 ) /*  SPI 0 Peripheral Chip Select 2 */
+#define AT91C_PIO_PB15            ( ( unsigned int ) 1 << 15 )        /* Pin Controlled by PB15 */
+#define AT91C_PB15_ERXDV          ( ( unsigned int ) AT91C_PIO_PB15 ) /*  Ethernet MAC Receive Data Valid */
+#define AT91C_PIO_PB16            ( ( unsigned int ) 1 << 16 )        /* Pin Controlled by PB16 */
+#define AT91C_PB16_ECOL           ( ( unsigned int ) AT91C_PIO_PB16 ) /*  Ethernet MAC Collision Detected */
+#define AT91C_PB16_NPCS13         ( ( unsigned int ) AT91C_PIO_PB16 ) /*  SPI 1 Peripheral Chip Select 3 */
+#define AT91C_PIO_PB17            ( ( unsigned int ) 1 << 17 )        /* Pin Controlled by PB17 */
+#define AT91C_PB17_ERXCK          ( ( unsigned int ) AT91C_PIO_PB17 ) /*  Ethernet MAC Receive Clock */
+#define AT91C_PB17_NPCS03         ( ( unsigned int ) AT91C_PIO_PB17 ) /*  SPI 0 Peripheral Chip Select 3 */
+#define AT91C_PIO_PB18            ( ( unsigned int ) 1 << 18 )        /* Pin Controlled by PB18 */
+#define AT91C_PB18_EF100          ( ( unsigned int ) AT91C_PIO_PB18 ) /*  Ethernet MAC Force 100 Mbits/sec */
+#define AT91C_PB18_ADTRG          ( ( unsigned int ) AT91C_PIO_PB18 ) /*  ADC External Trigger */
+#define AT91C_PIO_PB19            ( ( unsigned int ) 1 << 19 )        /* Pin Controlled by PB19 */
+#define AT91C_PB19_PWM0           ( ( unsigned int ) AT91C_PIO_PB19 ) /*  PWM Channel 0 */
+#define AT91C_PB19_TCLK1          ( ( unsigned int ) AT91C_PIO_PB19 ) /*  Timer Counter 1 external clock input */
+#define AT91C_PIO_PB2             ( ( unsigned int ) 1 << 2 )         /* Pin Controlled by PB2 */
+#define AT91C_PB2_ETX0            ( ( unsigned int ) AT91C_PIO_PB2 )  /*  Ethernet MAC Transmit Data 0 */
+#define AT91C_PIO_PB20            ( ( unsigned int ) 1 << 20 )        /* Pin Controlled by PB20 */
+#define AT91C_PB20_PWM1           ( ( unsigned int ) AT91C_PIO_PB20 ) /*  PWM Channel 1 */
+#define AT91C_PB20_PCK0           ( ( unsigned int ) AT91C_PIO_PB20 ) /*  PMC Programmable Clock Output 0 */
+#define AT91C_PIO_PB21            ( ( unsigned int ) 1 << 21 )        /* Pin Controlled by PB21 */
+#define AT91C_PB21_PWM2           ( ( unsigned int ) AT91C_PIO_PB21 ) /*  PWM Channel 2 */
+#define AT91C_PB21_PCK1           ( ( unsigned int ) AT91C_PIO_PB21 ) /*  PMC Programmable Clock Output 1 */
+#define AT91C_PIO_PB22            ( ( unsigned int ) 1 << 22 )        /* Pin Controlled by PB22 */
+#define AT91C_PB22_PWM3           ( ( unsigned int ) AT91C_PIO_PB22 ) /*  PWM Channel 3 */
+#define AT91C_PB22_PCK2           ( ( unsigned int ) AT91C_PIO_PB22 ) /*  PMC Programmable Clock Output 2 */
+#define AT91C_PIO_PB23            ( ( unsigned int ) 1 << 23 )        /* Pin Controlled by PB23 */
+#define AT91C_PB23_TIOA0          ( ( unsigned int ) AT91C_PIO_PB23 ) /*  Timer Counter 0 Multipurpose Timer I/O Pin A */
+#define AT91C_PB23_DCD1           ( ( unsigned int ) AT91C_PIO_PB23 ) /*  USART 1 Data Carrier Detect */
+#define AT91C_PIO_PB24            ( ( unsigned int ) 1 << 24 )        /* Pin Controlled by PB24 */
+#define AT91C_PB24_TIOB0          ( ( unsigned int ) AT91C_PIO_PB24 ) /*  Timer Counter 0 Multipurpose Timer I/O Pin B */
+#define AT91C_PB24_DSR1           ( ( unsigned int ) AT91C_PIO_PB24 ) /*  USART 1 Data Set ready */
+#define AT91C_PIO_PB25            ( ( unsigned int ) 1 << 25 )        /* Pin Controlled by PB25 */
+#define AT91C_PB25_TIOA1          ( ( unsigned int ) AT91C_PIO_PB25 ) /*  Timer Counter 1 Multipurpose Timer I/O Pin A */
+#define AT91C_PB25_DTR1           ( ( unsigned int ) AT91C_PIO_PB25 ) /*  USART 1 Data Terminal ready */
+#define AT91C_PIO_PB26            ( ( unsigned int ) 1 << 26 )        /* Pin Controlled by PB26 */
+#define AT91C_PB26_TIOB1          ( ( unsigned int ) AT91C_PIO_PB26 ) /*  Timer Counter 1 Multipurpose Timer I/O Pin B */
+#define AT91C_PB26_RI1            ( ( unsigned int ) AT91C_PIO_PB26 ) /*  USART 1 Ring Indicator */
+#define AT91C_PIO_PB27            ( ( unsigned int ) 1 << 27 )        /* Pin Controlled by PB27 */
+#define AT91C_PB27_TIOA2          ( ( unsigned int ) AT91C_PIO_PB27 ) /*  Timer Counter 2 Multipurpose Timer I/O Pin A */
+#define AT91C_PB27_PWM0           ( ( unsigned int ) AT91C_PIO_PB27 ) /*  PWM Channel 0 */
+#define AT91C_PIO_PB28            ( ( unsigned int ) 1 << 28 )        /* Pin Controlled by PB28 */
+#define AT91C_PB28_TIOB2          ( ( unsigned int ) AT91C_PIO_PB28 ) /*  Timer Counter 2 Multipurpose Timer I/O Pin B */
+#define AT91C_PB28_PWM1           ( ( unsigned int ) AT91C_PIO_PB28 ) /*  PWM Channel 1 */
+#define AT91C_PIO_PB29            ( ( unsigned int ) 1 << 29 )        /* Pin Controlled by PB29 */
+#define AT91C_PB29_PCK1           ( ( unsigned int ) AT91C_PIO_PB29 ) /*  PMC Programmable Clock Output 1 */
+#define AT91C_PB29_PWM2           ( ( unsigned int ) AT91C_PIO_PB29 ) /*  PWM Channel 2 */
+#define AT91C_PIO_PB3             ( ( unsigned int ) 1 << 3 )         /* Pin Controlled by PB3 */
+#define AT91C_PB3_ETX1            ( ( unsigned int ) AT91C_PIO_PB3 )  /*  Ethernet MAC Transmit Data 1 */
+#define AT91C_PIO_PB30            ( ( unsigned int ) 1 << 30 )        /* Pin Controlled by PB30 */
+#define AT91C_PB30_PCK2           ( ( unsigned int ) AT91C_PIO_PB30 ) /*  PMC Programmable Clock Output 2 */
+#define AT91C_PB30_PWM3           ( ( unsigned int ) AT91C_PIO_PB30 ) /*  PWM Channel 3 */
+#define AT91C_PIO_PB4             ( ( unsigned int ) 1 << 4 )         /* Pin Controlled by PB4 */
+#define AT91C_PB4_ECRS_ECRSDV     ( ( unsigned int ) AT91C_PIO_PB4 )  /*  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid */
+#define AT91C_PIO_PB5             ( ( unsigned int ) 1 << 5 )         /* Pin Controlled by PB5 */
+#define AT91C_PB5_ERX0            ( ( unsigned int ) AT91C_PIO_PB5 )  /*  Ethernet MAC Receive Data 0 */
+#define AT91C_PIO_PB6             ( ( unsigned int ) 1 << 6 )         /* Pin Controlled by PB6 */
+#define AT91C_PB6_ERX1            ( ( unsigned int ) AT91C_PIO_PB6 )  /*  Ethernet MAC Receive Data 1 */
+#define AT91C_PIO_PB7             ( ( unsigned int ) 1 << 7 )         /* Pin Controlled by PB7 */
+#define AT91C_PB7_ERXER           ( ( unsigned int ) AT91C_PIO_PB7 )  /*  Ethernet MAC Receive Error */
+#define AT91C_PIO_PB8             ( ( unsigned int ) 1 << 8 )         /* Pin Controlled by PB8 */
+#define AT91C_PB8_EMDC            ( ( unsigned int ) AT91C_PIO_PB8 )  /*  Ethernet MAC Management Data Clock */
+#define AT91C_PIO_PB9             ( ( unsigned int ) 1 << 9 )         /* Pin Controlled by PB9 */
+#define AT91C_PB9_EMDIO           ( ( unsigned int ) AT91C_PIO_PB9 )  /*  Ethernet MAC Management Data Input/Output */
 
-// *****************************************************************************
-//               PERIPHERAL ID DEFINITIONS FOR AT91SAM7X128
-// *****************************************************************************
-#define AT91C_ID_FIQ    ((unsigned int)  0) // Advanced Interrupt Controller (FIQ)
-#define AT91C_ID_SYS    ((unsigned int)  1) // System Peripheral
-#define AT91C_ID_PIOA   ((unsigned int)  2) // Parallel IO Controller A
-#define AT91C_ID_PIOB   ((unsigned int)  3) // Parallel IO Controller B
-#define AT91C_ID_SPI0   ((unsigned int)  4) // Serial Peripheral Interface 0
-#define AT91C_ID_SPI1   ((unsigned int)  5) // Serial Peripheral Interface 1
-#define AT91C_ID_US0    ((unsigned int)  6) // USART 0
-#define AT91C_ID_US1    ((unsigned int)  7) // USART 1
-#define AT91C_ID_SSC    ((unsigned int)  8) // Serial Synchronous Controller
-#define AT91C_ID_TWI    ((unsigned int)  9) // Two-Wire Interface
-#define AT91C_ID_PWMC   ((unsigned int) 10) // PWM Controller
-#define AT91C_ID_UDP    ((unsigned int) 11) // USB Device Port
-#define AT91C_ID_TC0    ((unsigned int) 12) // Timer Counter 0
-#define AT91C_ID_TC1    ((unsigned int) 13) // Timer Counter 1
-#define AT91C_ID_TC2    ((unsigned int) 14) // Timer Counter 2
-#define AT91C_ID_CAN    ((unsigned int) 15) // Control Area Network Controller
-#define AT91C_ID_EMAC   ((unsigned int) 16) // Ethernet MAC
-#define AT91C_ID_ADC    ((unsigned int) 17) // Analog-to-Digital Converter
-#define AT91C_ID_AES    ((unsigned int) 18) // Advanced Encryption Standard 128-bit
-#define AT91C_ID_TDES   ((unsigned int) 19) // Triple Data Encryption Standard
-#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved
-#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved
-#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved
-#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved
-#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved
-#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved
-#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved
-#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved
-#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved
-#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved
-#define AT91C_ID_IRQ0   ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0)
-#define AT91C_ID_IRQ1   ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1)
+/* ***************************************************************************** */
+/*               PERIPHERAL ID DEFINITIONS FOR AT91SAM7X128 */
+/* ***************************************************************************** */
+#define AT91C_ID_FIQ            ( ( unsigned int ) 0 )  /* Advanced Interrupt Controller (FIQ) */
+#define AT91C_ID_SYS            ( ( unsigned int ) 1 )  /* System Peripheral */
+#define AT91C_ID_PIOA           ( ( unsigned int ) 2 )  /* Parallel IO Controller A */
+#define AT91C_ID_PIOB           ( ( unsigned int ) 3 )  /* Parallel IO Controller B */
+#define AT91C_ID_SPI0           ( ( unsigned int ) 4 )  /* Serial Peripheral Interface 0 */
+#define AT91C_ID_SPI1           ( ( unsigned int ) 5 )  /* Serial Peripheral Interface 1 */
+#define AT91C_ID_US0            ( ( unsigned int ) 6 )  /* USART 0 */
+#define AT91C_ID_US1            ( ( unsigned int ) 7 )  /* USART 1 */
+#define AT91C_ID_SSC            ( ( unsigned int ) 8 )  /* Serial Synchronous Controller */
+#define AT91C_ID_TWI            ( ( unsigned int ) 9 )  /* Two-Wire Interface */
+#define AT91C_ID_PWMC           ( ( unsigned int ) 10 ) /* PWM Controller */
+#define AT91C_ID_UDP            ( ( unsigned int ) 11 ) /* USB Device Port */
+#define AT91C_ID_TC0            ( ( unsigned int ) 12 ) /* Timer Counter 0 */
+#define AT91C_ID_TC1            ( ( unsigned int ) 13 ) /* Timer Counter 1 */
+#define AT91C_ID_TC2            ( ( unsigned int ) 14 ) /* Timer Counter 2 */
+#define AT91C_ID_CAN            ( ( unsigned int ) 15 ) /* Control Area Network Controller */
+#define AT91C_ID_EMAC           ( ( unsigned int ) 16 ) /* Ethernet MAC */
+#define AT91C_ID_ADC            ( ( unsigned int ) 17 ) /* Analog-to-Digital Converter */
+#define AT91C_ID_AES            ( ( unsigned int ) 18 ) /* Advanced Encryption Standard 128-bit */
+#define AT91C_ID_TDES           ( ( unsigned int ) 19 ) /* Triple Data Encryption Standard */
+#define AT91C_ID_20_Reserved    ( ( unsigned int ) 20 ) /* Reserved */
+#define AT91C_ID_21_Reserved    ( ( unsigned int ) 21 ) /* Reserved */
+#define AT91C_ID_22_Reserved    ( ( unsigned int ) 22 ) /* Reserved */
+#define AT91C_ID_23_Reserved    ( ( unsigned int ) 23 ) /* Reserved */
+#define AT91C_ID_24_Reserved    ( ( unsigned int ) 24 ) /* Reserved */
+#define AT91C_ID_25_Reserved    ( ( unsigned int ) 25 ) /* Reserved */
+#define AT91C_ID_26_Reserved    ( ( unsigned int ) 26 ) /* Reserved */
+#define AT91C_ID_27_Reserved    ( ( unsigned int ) 27 ) /* Reserved */
+#define AT91C_ID_28_Reserved    ( ( unsigned int ) 28 ) /* Reserved */
+#define AT91C_ID_29_Reserved    ( ( unsigned int ) 29 ) /* Reserved */
+#define AT91C_ID_IRQ0           ( ( unsigned int ) 30 ) /* Advanced Interrupt Controller (IRQ0) */
+#define AT91C_ID_IRQ1           ( ( unsigned int ) 31 ) /* Advanced Interrupt Controller (IRQ1) */
 
-// *****************************************************************************
-//               BASE ADDRESS DEFINITIONS FOR AT91SAM7X128
-// *****************************************************************************
-#define AT91C_BASE_SYS       ((AT91PS_SYS)  0xFFFFF000) // (SYS) Base Address
-#define AT91C_BASE_AIC       ((AT91PS_AIC)  0xFFFFF000) // (AIC) Base Address
-#define AT91C_BASE_PDC_DBGU  ((AT91PS_PDC)  0xFFFFF300) // (PDC_DBGU) Base Address
-#define AT91C_BASE_DBGU      ((AT91PS_DBGU)     0xFFFFF200) // (DBGU) Base Address
-#define AT91C_BASE_PIOA      ((AT91PS_PIO)  0xFFFFF400) // (PIOA) Base Address
-#define AT91C_BASE_PIOB      ((AT91PS_PIO)  0xFFFFF600) // (PIOB) Base Address
-#define AT91C_BASE_CKGR      ((AT91PS_CKGR)     0xFFFFFC20) // (CKGR) Base Address
-#define AT91C_BASE_PMC       ((AT91PS_PMC)  0xFFFFFC00) // (PMC) Base Address
-#define AT91C_BASE_RSTC      ((AT91PS_RSTC)     0xFFFFFD00) // (RSTC) Base Address
-#define AT91C_BASE_RTTC      ((AT91PS_RTTC)     0xFFFFFD20) // (RTTC) Base Address
-#define AT91C_BASE_PITC      ((AT91PS_PITC)     0xFFFFFD30) // (PITC) Base Address
-#define AT91C_BASE_WDTC      ((AT91PS_WDTC)     0xFFFFFD40) // (WDTC) Base Address
-#define AT91C_BASE_VREG      ((AT91PS_VREG)     0xFFFFFD60) // (VREG) Base Address
-#define AT91C_BASE_MC        ((AT91PS_MC)   0xFFFFFF00) // (MC) Base Address
-#define AT91C_BASE_PDC_SPI1  ((AT91PS_PDC)  0xFFFE4100) // (PDC_SPI1) Base Address
-#define AT91C_BASE_SPI1      ((AT91PS_SPI)  0xFFFE4000) // (SPI1) Base Address
-#define AT91C_BASE_PDC_SPI0  ((AT91PS_PDC)  0xFFFE0100) // (PDC_SPI0) Base Address
-#define AT91C_BASE_SPI0      ((AT91PS_SPI)  0xFFFE0000) // (SPI0) Base Address
-#define AT91C_BASE_PDC_US1   ((AT91PS_PDC)  0xFFFC4100) // (PDC_US1) Base Address
-#define AT91C_BASE_US1       ((AT91PS_USART)    0xFFFC4000) // (US1) Base Address
-#define AT91C_BASE_PDC_US0   ((AT91PS_PDC)  0xFFFC0100) // (PDC_US0) Base Address
-#define AT91C_BASE_US0       ((AT91PS_USART)    0xFFFC0000) // (US0) Base Address
-#define AT91C_BASE_PDC_SSC   ((AT91PS_PDC)  0xFFFD4100) // (PDC_SSC) Base Address
-#define AT91C_BASE_SSC       ((AT91PS_SSC)  0xFFFD4000) // (SSC) Base Address
-#define AT91C_BASE_TWI       ((AT91PS_TWI)  0xFFFB8000) // (TWI) Base Address
-#define AT91C_BASE_PWMC_CH3  ((AT91PS_PWMC_CH)  0xFFFCC260) // (PWMC_CH3) Base Address
-#define AT91C_BASE_PWMC_CH2  ((AT91PS_PWMC_CH)  0xFFFCC240) // (PWMC_CH2) Base Address
-#define AT91C_BASE_PWMC_CH1  ((AT91PS_PWMC_CH)  0xFFFCC220) // (PWMC_CH1) Base Address
-#define AT91C_BASE_PWMC_CH0  ((AT91PS_PWMC_CH)  0xFFFCC200) // (PWMC_CH0) Base Address
-#define AT91C_BASE_PWMC      ((AT91PS_PWMC)     0xFFFCC000) // (PWMC) Base Address
-#define AT91C_BASE_UDP       ((AT91PS_UDP)  0xFFFB0000) // (UDP) Base Address
-#define AT91C_BASE_TC0       ((AT91PS_TC)   0xFFFA0000) // (TC0) Base Address
-#define AT91C_BASE_TC1       ((AT91PS_TC)   0xFFFA0040) // (TC1) Base Address
-#define AT91C_BASE_TC2       ((AT91PS_TC)   0xFFFA0080) // (TC2) Base Address
-#define AT91C_BASE_TCB       ((AT91PS_TCB)  0xFFFA0000) // (TCB) Base Address
-#define AT91C_BASE_CAN_MB0   ((AT91PS_CAN_MB)   0xFFFD0200) // (CAN_MB0) Base Address
-#define AT91C_BASE_CAN_MB1   ((AT91PS_CAN_MB)   0xFFFD0220) // (CAN_MB1) Base Address
-#define AT91C_BASE_CAN_MB2   ((AT91PS_CAN_MB)   0xFFFD0240) // (CAN_MB2) Base Address
-#define AT91C_BASE_CAN_MB3   ((AT91PS_CAN_MB)   0xFFFD0260) // (CAN_MB3) Base Address
-#define AT91C_BASE_CAN_MB4   ((AT91PS_CAN_MB)   0xFFFD0280) // (CAN_MB4) Base Address
-#define AT91C_BASE_CAN_MB5   ((AT91PS_CAN_MB)   0xFFFD02A0) // (CAN_MB5) Base Address
-#define AT91C_BASE_CAN_MB6   ((AT91PS_CAN_MB)   0xFFFD02C0) // (CAN_MB6) Base Address
-#define AT91C_BASE_CAN_MB7   ((AT91PS_CAN_MB)   0xFFFD02E0) // (CAN_MB7) Base Address
-#define AT91C_BASE_CAN       ((AT91PS_CAN)  0xFFFD0000) // (CAN) Base Address
-#define AT91C_BASE_EMAC      ((AT91PS_EMAC)     0xFFFDC000) // (EMAC) Base Address
-#define AT91C_BASE_PDC_ADC   ((AT91PS_PDC)  0xFFFD8100) // (PDC_ADC) Base Address
-#define AT91C_BASE_ADC       ((AT91PS_ADC)  0xFFFD8000) // (ADC) Base Address
-#define AT91C_BASE_PDC_AES   ((AT91PS_PDC)  0xFFFA4100) // (PDC_AES) Base Address
-#define AT91C_BASE_AES       ((AT91PS_AES)  0xFFFA4000) // (AES) Base Address
-#define AT91C_BASE_PDC_TDES  ((AT91PS_PDC)  0xFFFA8100) // (PDC_TDES) Base Address
-#define AT91C_BASE_TDES      ((AT91PS_TDES)     0xFFFA8000) // (TDES) Base Address
+/* ***************************************************************************** */
+/*               BASE ADDRESS DEFINITIONS FOR AT91SAM7X128 */
+/* ***************************************************************************** */
+#define AT91C_BASE_SYS         ( ( AT91PS_SYS ) 0xFFFFF000 )     /* (SYS) Base Address */
+#define AT91C_BASE_AIC         ( ( AT91PS_AIC ) 0xFFFFF000 )     /* (AIC) Base Address */
+#define AT91C_BASE_PDC_DBGU    ( ( AT91PS_PDC ) 0xFFFFF300 )     /* (PDC_DBGU) Base Address */
+#define AT91C_BASE_DBGU        ( ( AT91PS_DBGU ) 0xFFFFF200 )    /* (DBGU) Base Address */
+#define AT91C_BASE_PIOA        ( ( AT91PS_PIO ) 0xFFFFF400 )     /* (PIOA) Base Address */
+#define AT91C_BASE_PIOB        ( ( AT91PS_PIO ) 0xFFFFF600 )     /* (PIOB) Base Address */
+#define AT91C_BASE_CKGR        ( ( AT91PS_CKGR ) 0xFFFFFC20 )    /* (CKGR) Base Address */
+#define AT91C_BASE_PMC         ( ( AT91PS_PMC ) 0xFFFFFC00 )     /* (PMC) Base Address */
+#define AT91C_BASE_RSTC        ( ( AT91PS_RSTC ) 0xFFFFFD00 )    /* (RSTC) Base Address */
+#define AT91C_BASE_RTTC        ( ( AT91PS_RTTC ) 0xFFFFFD20 )    /* (RTTC) Base Address */
+#define AT91C_BASE_PITC        ( ( AT91PS_PITC ) 0xFFFFFD30 )    /* (PITC) Base Address */
+#define AT91C_BASE_WDTC        ( ( AT91PS_WDTC ) 0xFFFFFD40 )    /* (WDTC) Base Address */
+#define AT91C_BASE_VREG        ( ( AT91PS_VREG ) 0xFFFFFD60 )    /* (VREG) Base Address */
+#define AT91C_BASE_MC          ( ( AT91PS_MC ) 0xFFFFFF00 )      /* (MC) Base Address */
+#define AT91C_BASE_PDC_SPI1    ( ( AT91PS_PDC ) 0xFFFE4100 )     /* (PDC_SPI1) Base Address */
+#define AT91C_BASE_SPI1        ( ( AT91PS_SPI ) 0xFFFE4000 )     /* (SPI1) Base Address */
+#define AT91C_BASE_PDC_SPI0    ( ( AT91PS_PDC ) 0xFFFE0100 )     /* (PDC_SPI0) Base Address */
+#define AT91C_BASE_SPI0        ( ( AT91PS_SPI ) 0xFFFE0000 )     /* (SPI0) Base Address */
+#define AT91C_BASE_PDC_US1     ( ( AT91PS_PDC ) 0xFFFC4100 )     /* (PDC_US1) Base Address */
+#define AT91C_BASE_US1         ( ( AT91PS_USART ) 0xFFFC4000 )   /* (US1) Base Address */
+#define AT91C_BASE_PDC_US0     ( ( AT91PS_PDC ) 0xFFFC0100 )     /* (PDC_US0) Base Address */
+#define AT91C_BASE_US0         ( ( AT91PS_USART ) 0xFFFC0000 )   /* (US0) Base Address */
+#define AT91C_BASE_PDC_SSC     ( ( AT91PS_PDC ) 0xFFFD4100 )     /* (PDC_SSC) Base Address */
+#define AT91C_BASE_SSC         ( ( AT91PS_SSC ) 0xFFFD4000 )     /* (SSC) Base Address */
+#define AT91C_BASE_TWI         ( ( AT91PS_TWI ) 0xFFFB8000 )     /* (TWI) Base Address */
+#define AT91C_BASE_PWMC_CH3    ( ( AT91PS_PWMC_CH ) 0xFFFCC260 ) /* (PWMC_CH3) Base Address */
+#define AT91C_BASE_PWMC_CH2    ( ( AT91PS_PWMC_CH ) 0xFFFCC240 ) /* (PWMC_CH2) Base Address */
+#define AT91C_BASE_PWMC_CH1    ( ( AT91PS_PWMC_CH ) 0xFFFCC220 ) /* (PWMC_CH1) Base Address */
+#define AT91C_BASE_PWMC_CH0    ( ( AT91PS_PWMC_CH ) 0xFFFCC200 ) /* (PWMC_CH0) Base Address */
+#define AT91C_BASE_PWMC        ( ( AT91PS_PWMC ) 0xFFFCC000 )    /* (PWMC) Base Address */
+#define AT91C_BASE_UDP         ( ( AT91PS_UDP ) 0xFFFB0000 )     /* (UDP) Base Address */
+#define AT91C_BASE_TC0         ( ( AT91PS_TC ) 0xFFFA0000 )      /* (TC0) Base Address */
+#define AT91C_BASE_TC1         ( ( AT91PS_TC ) 0xFFFA0040 )      /* (TC1) Base Address */
+#define AT91C_BASE_TC2         ( ( AT91PS_TC ) 0xFFFA0080 )      /* (TC2) Base Address */
+#define AT91C_BASE_TCB         ( ( AT91PS_TCB ) 0xFFFA0000 )     /* (TCB) Base Address */
+#define AT91C_BASE_CAN_MB0     ( ( AT91PS_CAN_MB ) 0xFFFD0200 )  /* (CAN_MB0) Base Address */
+#define AT91C_BASE_CAN_MB1     ( ( AT91PS_CAN_MB ) 0xFFFD0220 )  /* (CAN_MB1) Base Address */
+#define AT91C_BASE_CAN_MB2     ( ( AT91PS_CAN_MB ) 0xFFFD0240 )  /* (CAN_MB2) Base Address */
+#define AT91C_BASE_CAN_MB3     ( ( AT91PS_CAN_MB ) 0xFFFD0260 )  /* (CAN_MB3) Base Address */
+#define AT91C_BASE_CAN_MB4     ( ( AT91PS_CAN_MB ) 0xFFFD0280 )  /* (CAN_MB4) Base Address */
+#define AT91C_BASE_CAN_MB5     ( ( AT91PS_CAN_MB ) 0xFFFD02A0 )  /* (CAN_MB5) Base Address */
+#define AT91C_BASE_CAN_MB6     ( ( AT91PS_CAN_MB ) 0xFFFD02C0 )  /* (CAN_MB6) Base Address */
+#define AT91C_BASE_CAN_MB7     ( ( AT91PS_CAN_MB ) 0xFFFD02E0 )  /* (CAN_MB7) Base Address */
+#define AT91C_BASE_CAN         ( ( AT91PS_CAN ) 0xFFFD0000 )     /* (CAN) Base Address */
+#define AT91C_BASE_EMAC        ( ( AT91PS_EMAC ) 0xFFFDC000 )    /* (EMAC) Base Address */
+#define AT91C_BASE_PDC_ADC     ( ( AT91PS_PDC ) 0xFFFD8100 )     /* (PDC_ADC) Base Address */
+#define AT91C_BASE_ADC         ( ( AT91PS_ADC ) 0xFFFD8000 )     /* (ADC) Base Address */
+#define AT91C_BASE_PDC_AES     ( ( AT91PS_PDC ) 0xFFFA4100 )     /* (PDC_AES) Base Address */
+#define AT91C_BASE_AES         ( ( AT91PS_AES ) 0xFFFA4000 )     /* (AES) Base Address */
+#define AT91C_BASE_PDC_TDES    ( ( AT91PS_PDC ) 0xFFFA8100 )     /* (PDC_TDES) Base Address */
+#define AT91C_BASE_TDES        ( ( AT91PS_TDES ) 0xFFFA8000 )    /* (TDES) Base Address */
 
-// *****************************************************************************
-//               MEMORY MAPPING DEFINITIONS FOR AT91SAM7X128
-// *****************************************************************************
-#define AT91C_ISRAM  ((char *)  0x00200000) // Internal SRAM base address
-#define AT91C_ISRAM_SIZE     ((unsigned int) 0x00008000) // Internal SRAM size in byte (32 Kbyte)
-#define AT91C_IFLASH     ((char *)  0x00100000) // Internal ROM base address
-#define AT91C_IFLASH_SIZE    ((unsigned int) 0x00020000) // Internal ROM size in byte (128 Kbyte)
+/* ***************************************************************************** */
+/*               MEMORY MAPPING DEFINITIONS FOR AT91SAM7X128 */
+/* ***************************************************************************** */
+#define AT91C_ISRAM          ( ( char * ) 0x00200000 )       /* Internal SRAM base address */
+#define AT91C_ISRAM_SIZE     ( ( unsigned int ) 0x00008000 ) /* Internal SRAM size in byte (32 Kbyte) */
+#define AT91C_IFLASH         ( ( char * ) 0x00100000 )       /* Internal ROM base address */
+#define AT91C_IFLASH_SIZE    ( ( unsigned int ) 0x00020000 ) /* Internal ROM size in byte (128 Kbyte) */
 
-#endif
+#endif /* ifndef AT91SAM7X128_H */
diff --git a/portable/IAR/AtmelSAM7S64/AT91SAM7X128_inc.h b/portable/IAR/AtmelSAM7S64/AT91SAM7X128_inc.h
index e76fdd774..fe701970e 100644
--- a/portable/IAR/AtmelSAM7S64/AT91SAM7X128_inc.h
+++ b/portable/IAR/AtmelSAM7S64/AT91SAM7X128_inc.h
@@ -1,2444 +1,2444 @@
-//  ----------------------------------------------------------------------------
-//          ATMEL Microcontroller Software Support  -  ROUSSET  -
-//  ----------------------------------------------------------------------------
-//  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
-//  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
-//  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
-//  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
-//  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-//  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-//  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-//  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//  ----------------------------------------------------------------------------
-// File Name           : AT91SAM7X128.h
-// Object              : AT91SAM7X128 definitions
-// Generated           : AT91 SW Application Group  05/20/2005 (16:22:23)
-//
-// CVS Reference       : /AT91SAM7X128.pl/1.14/Tue May 10 12:12:05 2005//
-// CVS Reference       : /SYS_SAM7X.pl/1.3/Tue Feb  1 17:01:43 2005//
-// CVS Reference       : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005//
-// CVS Reference       : /PMC_SAM7X.pl/1.4/Tue Feb  8 13:58:10 2005//
-// CVS Reference       : /RSTC_SAM7X.pl/1.1/Tue Feb  1 16:16:26 2005//
-// CVS Reference       : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005//
-// CVS Reference       : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005//
-// CVS Reference       : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//
-// CVS Reference       : /PIO_6057A.pl/1.2/Thu Feb  3 10:18:28 2005//
-// CVS Reference       : /RTTC_6081A.pl/1.2/Tue Nov  9 14:43:58 2004//
-// CVS Reference       : /PITC_6079A.pl/1.2/Tue Nov  9 14:43:56 2004//
-// CVS Reference       : /WDTC_6080A.pl/1.3/Tue Nov  9 14:44:00 2004//
-// CVS Reference       : /VREG_6085B.pl/1.1/Tue Feb  1 16:05:48 2005//
-// CVS Reference       : /PDC_6074C.pl/1.2/Thu Feb  3 08:48:54 2005//
-// CVS Reference       : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//
-// CVS Reference       : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//
-// CVS Reference       : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//
-// CVS Reference       : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//
-// CVS Reference       : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//
-// CVS Reference       : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//
-// CVS Reference       : /CAN_6019B.pl/1.1/Tue Mar  8 12:42:22 2005//
-// CVS Reference       : /EMACB_6119A.pl/1.5/Thu Feb  3 15:52:04 2005//
-// CVS Reference       : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//
-// CVS Reference       : /AES_6149A.pl/1.10/Mon Feb  7 09:44:25 2005//
-// CVS Reference       : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005//
-//  ----------------------------------------------------------------------------
+/*  ---------------------------------------------------------------------------- */
+/*          ATMEL Microcontroller Software Support  -  ROUSSET  - */
+/*  ---------------------------------------------------------------------------- */
+/*  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
+/*  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
+/*  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
+/*  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
+/*  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
+/*  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
+/*  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/*  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
+/*  ---------------------------------------------------------------------------- */
+/* File Name           : AT91SAM7X128.h */
+/* Object              : AT91SAM7X128 definitions */
+/* Generated           : AT91 SW Application Group  05/20/2005 (16:22:23) */
+/* */
+/* CVS Reference       : /AT91SAM7X128.pl/1.14/Tue May 10 12:12:05 2005// */
+/* CVS Reference       : /SYS_SAM7X.pl/1.3/Tue Feb  1 17:01:43 2005// */
+/* CVS Reference       : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// */
+/* CVS Reference       : /PMC_SAM7X.pl/1.4/Tue Feb  8 13:58:10 2005// */
+/* CVS Reference       : /RSTC_SAM7X.pl/1.1/Tue Feb  1 16:16:26 2005// */
+/* CVS Reference       : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// */
+/* CVS Reference       : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// */
+/* CVS Reference       : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// */
+/* CVS Reference       : /PIO_6057A.pl/1.2/Thu Feb  3 10:18:28 2005// */
+/* CVS Reference       : /RTTC_6081A.pl/1.2/Tue Nov  9 14:43:58 2004// */
+/* CVS Reference       : /PITC_6079A.pl/1.2/Tue Nov  9 14:43:56 2004// */
+/* CVS Reference       : /WDTC_6080A.pl/1.3/Tue Nov  9 14:44:00 2004// */
+/* CVS Reference       : /VREG_6085B.pl/1.1/Tue Feb  1 16:05:48 2005// */
+/* CVS Reference       : /PDC_6074C.pl/1.2/Thu Feb  3 08:48:54 2005// */
+/* CVS Reference       : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// */
+/* CVS Reference       : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// */
+/* CVS Reference       : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// */
+/* CVS Reference       : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// */
+/* CVS Reference       : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// */
+/* CVS Reference       : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// */
+/* CVS Reference       : /CAN_6019B.pl/1.1/Tue Mar  8 12:42:22 2005// */
+/* CVS Reference       : /EMACB_6119A.pl/1.5/Thu Feb  3 15:52:04 2005// */
+/* CVS Reference       : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// */
+/* CVS Reference       : /AES_6149A.pl/1.10/Mon Feb  7 09:44:25 2005// */
+/* CVS Reference       : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// */
+/*  ---------------------------------------------------------------------------- */
 
-// Hardware register definition
+/* Hardware register definition */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR System Peripherals
-// *****************************************************************************
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR System Peripherals */
+/* ***************************************************************************** */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
-// *****************************************************************************
-// *** Register offset in AT91S_AIC structure ***
-#define AIC_SMR         ( 0) // Source Mode Register
-#define AIC_SVR         (128) // Source Vector Register
-#define AIC_IVR         (256) // IRQ Vector Register
-#define AIC_FVR         (260) // FIQ Vector Register
-#define AIC_ISR         (264) // Interrupt Status Register
-#define AIC_IPR         (268) // Interrupt Pending Register
-#define AIC_IMR         (272) // Interrupt Mask Register
-#define AIC_CISR        (276) // Core Interrupt Status Register
-#define AIC_IECR        (288) // Interrupt Enable Command Register
-#define AIC_IDCR        (292) // Interrupt Disable Command Register
-#define AIC_ICCR        (296) // Interrupt Clear Command Register
-#define AIC_ISCR        (300) // Interrupt Set Command Register
-#define AIC_EOICR       (304) // End of Interrupt Command Register
-#define AIC_SPU         (308) // Spurious Vector Register
-#define AIC_DCR         (312) // Debug Control Register (Protect)
-#define AIC_FFER        (320) // Fast Forcing Enable Register
-#define AIC_FFDR        (324) // Fast Forcing Disable Register
-#define AIC_FFSR        (328) // Fast Forcing Status Register
-// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
-#define AT91C_AIC_PRIOR           (0x7 <<  0) // (AIC) Priority Level
-#define     AT91C_AIC_PRIOR_LOWEST               (0x0) // (AIC) Lowest priority level
-#define     AT91C_AIC_PRIOR_HIGHEST              (0x7) // (AIC) Highest priority level
-#define AT91C_AIC_SRCTYPE         (0x3 <<  5) // (AIC) Interrupt Source Type
-#define     AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL       (0x0 <<  5) // (AIC) Internal Sources Code Label High-level Sensitive
-#define     AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL        (0x0 <<  5) // (AIC) External Sources Code Label Low-level Sensitive
-#define     AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE    (0x1 <<  5) // (AIC) Internal Sources Code Label Positive Edge triggered
-#define     AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE    (0x1 <<  5) // (AIC) External Sources Code Label Negative Edge triggered
-#define     AT91C_AIC_SRCTYPE_HIGH_LEVEL           (0x2 <<  5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
-#define     AT91C_AIC_SRCTYPE_POSITIVE_EDGE        (0x3 <<  5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
-// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
-#define AT91C_AIC_NFIQ            (0x1 <<  0) // (AIC) NFIQ Status
-#define AT91C_AIC_NIRQ            (0x1 <<  1) // (AIC) NIRQ Status
-// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
-#define AT91C_AIC_DCR_PROT        (0x1 <<  0) // (AIC) Protection Mode
-#define AT91C_AIC_DCR_GMSK        (0x1 <<  1) // (AIC) General Mask
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_AIC structure *** */
+#define AIC_SMR                                    ( 0 )        /* Source Mode Register */
+#define AIC_SVR                                    ( 128 )      /* Source Vector Register */
+#define AIC_IVR                                    ( 256 )      /* IRQ Vector Register */
+#define AIC_FVR                                    ( 260 )      /* FIQ Vector Register */
+#define AIC_ISR                                    ( 264 )      /* Interrupt Status Register */
+#define AIC_IPR                                    ( 268 )      /* Interrupt Pending Register */
+#define AIC_IMR                                    ( 272 )      /* Interrupt Mask Register */
+#define AIC_CISR                                   ( 276 )      /* Core Interrupt Status Register */
+#define AIC_IECR                                   ( 288 )      /* Interrupt Enable Command Register */
+#define AIC_IDCR                                   ( 292 )      /* Interrupt Disable Command Register */
+#define AIC_ICCR                                   ( 296 )      /* Interrupt Clear Command Register */
+#define AIC_ISCR                                   ( 300 )      /* Interrupt Set Command Register */
+#define AIC_EOICR                                  ( 304 )      /* End of Interrupt Command Register */
+#define AIC_SPU                                    ( 308 )      /* Spurious Vector Register */
+#define AIC_DCR                                    ( 312 )      /* Debug Control Register (Protect) */
+#define AIC_FFER                                   ( 320 )      /* Fast Forcing Enable Register */
+#define AIC_FFDR                                   ( 324 )      /* Fast Forcing Disable Register */
+#define AIC_FFSR                                   ( 328 )      /* Fast Forcing Status Register */
+/* -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- */
+#define AT91C_AIC_PRIOR                            ( 0x7 << 0 ) /* (AIC) Priority Level */
+#define     AT91C_AIC_PRIOR_LOWEST                 ( 0x0 )      /* (AIC) Lowest priority level */
+#define     AT91C_AIC_PRIOR_HIGHEST                ( 0x7 )      /* (AIC) Highest priority level */
+#define AT91C_AIC_SRCTYPE                          ( 0x3 << 5 ) /* (AIC) Interrupt Source Type */
+#define     AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL       ( 0x0 << 5 ) /* (AIC) Internal Sources Code Label High-level Sensitive */
+#define     AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL        ( 0x0 << 5 ) /* (AIC) External Sources Code Label Low-level Sensitive */
+#define     AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE    ( 0x1 << 5 ) /* (AIC) Internal Sources Code Label Positive Edge triggered */
+#define     AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE    ( 0x1 << 5 ) /* (AIC) External Sources Code Label Negative Edge triggered */
+#define     AT91C_AIC_SRCTYPE_HIGH_LEVEL           ( 0x2 << 5 ) /* (AIC) Internal Or External Sources Code Label High-level Sensitive */
+#define     AT91C_AIC_SRCTYPE_POSITIVE_EDGE        ( 0x3 << 5 ) /* (AIC) Internal Or External Sources Code Label Positive Edge triggered */
+/* -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- */
+#define AT91C_AIC_NFIQ                             ( 0x1 << 0 ) /* (AIC) NFIQ Status */
+#define AT91C_AIC_NIRQ                             ( 0x1 << 1 ) /* (AIC) NIRQ Status */
+/* -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- */
+#define AT91C_AIC_DCR_PROT                         ( 0x1 << 0 ) /* (AIC) Protection Mode */
+#define AT91C_AIC_DCR_GMSK                         ( 0x1 << 1 ) /* (AIC) General Mask */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller
-// *****************************************************************************
-// *** Register offset in AT91S_PDC structure ***
-#define PDC_RPR         ( 0) // Receive Pointer Register
-#define PDC_RCR         ( 4) // Receive Counter Register
-#define PDC_TPR         ( 8) // Transmit Pointer Register
-#define PDC_TCR         (12) // Transmit Counter Register
-#define PDC_RNPR        (16) // Receive Next Pointer Register
-#define PDC_RNCR        (20) // Receive Next Counter Register
-#define PDC_TNPR        (24) // Transmit Next Pointer Register
-#define PDC_TNCR        (28) // Transmit Next Counter Register
-#define PDC_PTCR        (32) // PDC Transfer Control Register
-#define PDC_PTSR        (36) // PDC Transfer Status Register
-// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
-#define AT91C_PDC_RXTEN           (0x1 <<  0) // (PDC) Receiver Transfer Enable
-#define AT91C_PDC_RXTDIS          (0x1 <<  1) // (PDC) Receiver Transfer Disable
-#define AT91C_PDC_TXTEN           (0x1 <<  8) // (PDC) Transmitter Transfer Enable
-#define AT91C_PDC_TXTDIS          (0x1 <<  9) // (PDC) Transmitter Transfer Disable
-// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_PDC structure *** */
+#define PDC_RPR             ( 0 )        /* Receive Pointer Register */
+#define PDC_RCR             ( 4 )        /* Receive Counter Register */
+#define PDC_TPR             ( 8 )        /* Transmit Pointer Register */
+#define PDC_TCR             ( 12 )       /* Transmit Counter Register */
+#define PDC_RNPR            ( 16 )       /* Receive Next Pointer Register */
+#define PDC_RNCR            ( 20 )       /* Receive Next Counter Register */
+#define PDC_TNPR            ( 24 )       /* Transmit Next Pointer Register */
+#define PDC_TNCR            ( 28 )       /* Transmit Next Counter Register */
+#define PDC_PTCR            ( 32 )       /* PDC Transfer Control Register */
+#define PDC_PTSR            ( 36 )       /* PDC Transfer Status Register */
+/* -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */
+#define AT91C_PDC_RXTEN     ( 0x1 << 0 ) /* (PDC) Receiver Transfer Enable */
+#define AT91C_PDC_RXTDIS    ( 0x1 << 1 ) /* (PDC) Receiver Transfer Disable */
+#define AT91C_PDC_TXTEN     ( 0x1 << 8 ) /* (PDC) Transmitter Transfer Enable */
+#define AT91C_PDC_TXTDIS    ( 0x1 << 9 ) /* (PDC) Transmitter Transfer Disable */
+/* -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Debug Unit
-// *****************************************************************************
-// *** Register offset in AT91S_DBGU structure ***
-#define DBGU_CR         ( 0) // Control Register
-#define DBGU_MR         ( 4) // Mode Register
-#define DBGU_IER        ( 8) // Interrupt Enable Register
-#define DBGU_IDR        (12) // Interrupt Disable Register
-#define DBGU_IMR        (16) // Interrupt Mask Register
-#define DBGU_CSR        (20) // Channel Status Register
-#define DBGU_RHR        (24) // Receiver Holding Register
-#define DBGU_THR        (28) // Transmitter Holding Register
-#define DBGU_BRGR       (32) // Baud Rate Generator Register
-#define DBGU_CIDR       (64) // Chip ID Register
-#define DBGU_EXID       (68) // Chip ID Extension Register
-#define DBGU_FNTR       (72) // Force NTRST Register
-#define DBGU_RPR        (256) // Receive Pointer Register
-#define DBGU_RCR        (260) // Receive Counter Register
-#define DBGU_TPR        (264) // Transmit Pointer Register
-#define DBGU_TCR        (268) // Transmit Counter Register
-#define DBGU_RNPR       (272) // Receive Next Pointer Register
-#define DBGU_RNCR       (276) // Receive Next Counter Register
-#define DBGU_TNPR       (280) // Transmit Next Pointer Register
-#define DBGU_TNCR       (284) // Transmit Next Counter Register
-#define DBGU_PTCR       (288) // PDC Transfer Control Register
-#define DBGU_PTSR       (292) // PDC Transfer Status Register
-// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
-#define AT91C_US_RSTRX            (0x1 <<  2) // (DBGU) Reset Receiver
-#define AT91C_US_RSTTX            (0x1 <<  3) // (DBGU) Reset Transmitter
-#define AT91C_US_RXEN             (0x1 <<  4) // (DBGU) Receiver Enable
-#define AT91C_US_RXDIS            (0x1 <<  5) // (DBGU) Receiver Disable
-#define AT91C_US_TXEN             (0x1 <<  6) // (DBGU) Transmitter Enable
-#define AT91C_US_TXDIS            (0x1 <<  7) // (DBGU) Transmitter Disable
-#define AT91C_US_RSTSTA           (0x1 <<  8) // (DBGU) Reset Status Bits
-// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
-#define AT91C_US_PAR              (0x7 <<  9) // (DBGU) Parity type
-#define     AT91C_US_PAR_EVEN                 (0x0 <<  9) // (DBGU) Even Parity
-#define     AT91C_US_PAR_ODD                  (0x1 <<  9) // (DBGU) Odd Parity
-#define     AT91C_US_PAR_SPACE                (0x2 <<  9) // (DBGU) Parity forced to 0 (Space)
-#define     AT91C_US_PAR_MARK                 (0x3 <<  9) // (DBGU) Parity forced to 1 (Mark)
-#define     AT91C_US_PAR_NONE                 (0x4 <<  9) // (DBGU) No Parity
-#define     AT91C_US_PAR_MULTI_DROP           (0x6 <<  9) // (DBGU) Multi-drop mode
-#define AT91C_US_CHMODE           (0x3 << 14) // (DBGU) Channel Mode
-#define     AT91C_US_CHMODE_NORMAL               (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
-#define     AT91C_US_CHMODE_AUTO                 (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
-#define     AT91C_US_CHMODE_LOCAL                (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
-#define     AT91C_US_CHMODE_REMOTE               (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
-// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
-#define AT91C_US_RXRDY            (0x1 <<  0) // (DBGU) RXRDY Interrupt
-#define AT91C_US_TXRDY            (0x1 <<  1) // (DBGU) TXRDY Interrupt
-#define AT91C_US_ENDRX            (0x1 <<  3) // (DBGU) End of Receive Transfer Interrupt
-#define AT91C_US_ENDTX            (0x1 <<  4) // (DBGU) End of Transmit Interrupt
-#define AT91C_US_OVRE             (0x1 <<  5) // (DBGU) Overrun Interrupt
-#define AT91C_US_FRAME            (0x1 <<  6) // (DBGU) Framing Error Interrupt
-#define AT91C_US_PARE             (0x1 <<  7) // (DBGU) Parity Error Interrupt
-#define AT91C_US_TXEMPTY          (0x1 <<  9) // (DBGU) TXEMPTY Interrupt
-#define AT91C_US_TXBUFE           (0x1 << 11) // (DBGU) TXBUFE Interrupt
-#define AT91C_US_RXBUFF           (0x1 << 12) // (DBGU) RXBUFF Interrupt
-#define AT91C_US_COMM_TX          (0x1 << 30) // (DBGU) COMM_TX Interrupt
-#define AT91C_US_COMM_RX          (0x1 << 31) // (DBGU) COMM_RX Interrupt
-// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
-// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
-// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
-// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
-#define AT91C_US_FORCE_NTRST      (0x1 <<  0) // (DBGU) Force NTRST in JTAG
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Debug Unit */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_DBGU structure *** */
+#define DBGU_CR                        ( 0 )         /* Control Register */
+#define DBGU_MR                        ( 4 )         /* Mode Register */
+#define DBGU_IER                       ( 8 )         /* Interrupt Enable Register */
+#define DBGU_IDR                       ( 12 )        /* Interrupt Disable Register */
+#define DBGU_IMR                       ( 16 )        /* Interrupt Mask Register */
+#define DBGU_CSR                       ( 20 )        /* Channel Status Register */
+#define DBGU_RHR                       ( 24 )        /* Receiver Holding Register */
+#define DBGU_THR                       ( 28 )        /* Transmitter Holding Register */
+#define DBGU_BRGR                      ( 32 )        /* Baud Rate Generator Register */
+#define DBGU_CIDR                      ( 64 )        /* Chip ID Register */
+#define DBGU_EXID                      ( 68 )        /* Chip ID Extension Register */
+#define DBGU_FNTR                      ( 72 )        /* Force NTRST Register */
+#define DBGU_RPR                       ( 256 )       /* Receive Pointer Register */
+#define DBGU_RCR                       ( 260 )       /* Receive Counter Register */
+#define DBGU_TPR                       ( 264 )       /* Transmit Pointer Register */
+#define DBGU_TCR                       ( 268 )       /* Transmit Counter Register */
+#define DBGU_RNPR                      ( 272 )       /* Receive Next Pointer Register */
+#define DBGU_RNCR                      ( 276 )       /* Receive Next Counter Register */
+#define DBGU_TNPR                      ( 280 )       /* Transmit Next Pointer Register */
+#define DBGU_TNCR                      ( 284 )       /* Transmit Next Counter Register */
+#define DBGU_PTCR                      ( 288 )       /* PDC Transfer Control Register */
+#define DBGU_PTSR                      ( 292 )       /* PDC Transfer Status Register */
+/* -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- */
+#define AT91C_US_RSTRX                 ( 0x1 << 2 )  /* (DBGU) Reset Receiver */
+#define AT91C_US_RSTTX                 ( 0x1 << 3 )  /* (DBGU) Reset Transmitter */
+#define AT91C_US_RXEN                  ( 0x1 << 4 )  /* (DBGU) Receiver Enable */
+#define AT91C_US_RXDIS                 ( 0x1 << 5 )  /* (DBGU) Receiver Disable */
+#define AT91C_US_TXEN                  ( 0x1 << 6 )  /* (DBGU) Transmitter Enable */
+#define AT91C_US_TXDIS                 ( 0x1 << 7 )  /* (DBGU) Transmitter Disable */
+#define AT91C_US_RSTSTA                ( 0x1 << 8 )  /* (DBGU) Reset Status Bits */
+/* -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- */
+#define AT91C_US_PAR                   ( 0x7 << 9 )  /* (DBGU) Parity type */
+#define     AT91C_US_PAR_EVEN          ( 0x0 << 9 )  /* (DBGU) Even Parity */
+#define     AT91C_US_PAR_ODD           ( 0x1 << 9 )  /* (DBGU) Odd Parity */
+#define     AT91C_US_PAR_SPACE         ( 0x2 << 9 )  /* (DBGU) Parity forced to 0 (Space) */
+#define     AT91C_US_PAR_MARK          ( 0x3 << 9 )  /* (DBGU) Parity forced to 1 (Mark) */
+#define     AT91C_US_PAR_NONE          ( 0x4 << 9 )  /* (DBGU) No Parity */
+#define     AT91C_US_PAR_MULTI_DROP    ( 0x6 << 9 )  /* (DBGU) Multi-drop mode */
+#define AT91C_US_CHMODE                ( 0x3 << 14 ) /* (DBGU) Channel Mode */
+#define     AT91C_US_CHMODE_NORMAL     ( 0x0 << 14 ) /* (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. */
+#define     AT91C_US_CHMODE_AUTO       ( 0x1 << 14 ) /* (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. */
+#define     AT91C_US_CHMODE_LOCAL      ( 0x2 << 14 ) /* (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. */
+#define     AT91C_US_CHMODE_REMOTE     ( 0x3 << 14 ) /* (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. */
+/* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */
+#define AT91C_US_RXRDY                 ( 0x1 << 0 )  /* (DBGU) RXRDY Interrupt */
+#define AT91C_US_TXRDY                 ( 0x1 << 1 )  /* (DBGU) TXRDY Interrupt */
+#define AT91C_US_ENDRX                 ( 0x1 << 3 )  /* (DBGU) End of Receive Transfer Interrupt */
+#define AT91C_US_ENDTX                 ( 0x1 << 4 )  /* (DBGU) End of Transmit Interrupt */
+#define AT91C_US_OVRE                  ( 0x1 << 5 )  /* (DBGU) Overrun Interrupt */
+#define AT91C_US_FRAME                 ( 0x1 << 6 )  /* (DBGU) Framing Error Interrupt */
+#define AT91C_US_PARE                  ( 0x1 << 7 )  /* (DBGU) Parity Error Interrupt */
+#define AT91C_US_TXEMPTY               ( 0x1 << 9 )  /* (DBGU) TXEMPTY Interrupt */
+#define AT91C_US_TXBUFE                ( 0x1 << 11 ) /* (DBGU) TXBUFE Interrupt */
+#define AT91C_US_RXBUFF                ( 0x1 << 12 ) /* (DBGU) RXBUFF Interrupt */
+#define AT91C_US_COMM_TX               ( 0x1 << 30 ) /* (DBGU) COMM_TX Interrupt */
+#define AT91C_US_COMM_RX               ( 0x1 << 31 ) /* (DBGU) COMM_RX Interrupt */
+/* -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- */
+/* -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- */
+/* -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- */
+/* -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- */
+#define AT91C_US_FORCE_NTRST    ( 0x1 << 0 )  /* (DBGU) Force NTRST in JTAG */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
-// *****************************************************************************
-// *** Register offset in AT91S_PIO structure ***
-#define PIO_PER         ( 0) // PIO Enable Register
-#define PIO_PDR         ( 4) // PIO Disable Register
-#define PIO_PSR         ( 8) // PIO Status Register
-#define PIO_OER         (16) // Output Enable Register
-#define PIO_ODR         (20) // Output Disable Registerr
-#define PIO_OSR         (24) // Output Status Register
-#define PIO_IFER        (32) // Input Filter Enable Register
-#define PIO_IFDR        (36) // Input Filter Disable Register
-#define PIO_IFSR        (40) // Input Filter Status Register
-#define PIO_SODR        (48) // Set Output Data Register
-#define PIO_CODR        (52) // Clear Output Data Register
-#define PIO_ODSR        (56) // Output Data Status Register
-#define PIO_PDSR        (60) // Pin Data Status Register
-#define PIO_IER         (64) // Interrupt Enable Register
-#define PIO_IDR         (68) // Interrupt Disable Register
-#define PIO_IMR         (72) // Interrupt Mask Register
-#define PIO_ISR         (76) // Interrupt Status Register
-#define PIO_MDER        (80) // Multi-driver Enable Register
-#define PIO_MDDR        (84) // Multi-driver Disable Register
-#define PIO_MDSR        (88) // Multi-driver Status Register
-#define PIO_PPUDR       (96) // Pull-up Disable Register
-#define PIO_PPUER       (100) // Pull-up Enable Register
-#define PIO_PPUSR       (104) // Pull-up Status Register
-#define PIO_ASR         (112) // Select A Register
-#define PIO_BSR         (116) // Select B Register
-#define PIO_ABSR        (120) // AB Select Status Register
-#define PIO_OWER        (160) // Output Write Enable Register
-#define PIO_OWDR        (164) // Output Write Disable Register
-#define PIO_OWSR        (168) // Output Write Status Register
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Parallel Input Output Controller */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_PIO structure *** */
+#define PIO_PER      ( 0 )   /* PIO Enable Register */
+#define PIO_PDR      ( 4 )   /* PIO Disable Register */
+#define PIO_PSR      ( 8 )   /* PIO Status Register */
+#define PIO_OER      ( 16 )  /* Output Enable Register */
+#define PIO_ODR      ( 20 )  /* Output Disable Registerr */
+#define PIO_OSR      ( 24 )  /* Output Status Register */
+#define PIO_IFER     ( 32 )  /* Input Filter Enable Register */
+#define PIO_IFDR     ( 36 )  /* Input Filter Disable Register */
+#define PIO_IFSR     ( 40 )  /* Input Filter Status Register */
+#define PIO_SODR     ( 48 )  /* Set Output Data Register */
+#define PIO_CODR     ( 52 )  /* Clear Output Data Register */
+#define PIO_ODSR     ( 56 )  /* Output Data Status Register */
+#define PIO_PDSR     ( 60 )  /* Pin Data Status Register */
+#define PIO_IER      ( 64 )  /* Interrupt Enable Register */
+#define PIO_IDR      ( 68 )  /* Interrupt Disable Register */
+#define PIO_IMR      ( 72 )  /* Interrupt Mask Register */
+#define PIO_ISR      ( 76 )  /* Interrupt Status Register */
+#define PIO_MDER     ( 80 )  /* Multi-driver Enable Register */
+#define PIO_MDDR     ( 84 )  /* Multi-driver Disable Register */
+#define PIO_MDSR     ( 88 )  /* Multi-driver Status Register */
+#define PIO_PPUDR    ( 96 )  /* Pull-up Disable Register */
+#define PIO_PPUER    ( 100 ) /* Pull-up Enable Register */
+#define PIO_PPUSR    ( 104 ) /* Pull-up Status Register */
+#define PIO_ASR      ( 112 ) /* Select A Register */
+#define PIO_BSR      ( 116 ) /* Select B Register */
+#define PIO_ABSR     ( 120 ) /* AB Select Status Register */
+#define PIO_OWER     ( 160 ) /* Output Write Enable Register */
+#define PIO_OWDR     ( 164 ) /* Output Write Disable Register */
+#define PIO_OWSR     ( 168 ) /* Output Write Status Register */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Clock Generator Controler
-// *****************************************************************************
-// *** Register offset in AT91S_CKGR structure ***
-#define CKGR_MOR        ( 0) // Main Oscillator Register
-#define CKGR_MCFR       ( 4) // Main Clock  Frequency Register
-#define CKGR_PLLR       (12) // PLL Register
-// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
-#define AT91C_CKGR_MOSCEN         (0x1 <<  0) // (CKGR) Main Oscillator Enable
-#define AT91C_CKGR_OSCBYPASS      (0x1 <<  1) // (CKGR) Main Oscillator Bypass
-#define AT91C_CKGR_OSCOUNT        (0xFF <<  8) // (CKGR) Main Oscillator Start-up Time
-// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
-#define AT91C_CKGR_MAINF          (0xFFFF <<  0) // (CKGR) Main Clock Frequency
-#define AT91C_CKGR_MAINRDY        (0x1 << 16) // (CKGR) Main Clock Ready
-// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
-#define AT91C_CKGR_DIV            (0xFF <<  0) // (CKGR) Divider Selected
-#define     AT91C_CKGR_DIV_0                    (0x0) // (CKGR) Divider output is 0
-#define     AT91C_CKGR_DIV_BYPASS               (0x1) // (CKGR) Divider is bypassed
-#define AT91C_CKGR_PLLCOUNT       (0x3F <<  8) // (CKGR) PLL Counter
-#define AT91C_CKGR_OUT            (0x3 << 14) // (CKGR) PLL Output Frequency Range
-#define     AT91C_CKGR_OUT_0                    (0x0 << 14) // (CKGR) Please refer to the PLL datasheet
-#define     AT91C_CKGR_OUT_1                    (0x1 << 14) // (CKGR) Please refer to the PLL datasheet
-#define     AT91C_CKGR_OUT_2                    (0x2 << 14) // (CKGR) Please refer to the PLL datasheet
-#define     AT91C_CKGR_OUT_3                    (0x3 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_MUL            (0x7FF << 16) // (CKGR) PLL Multiplier
-#define AT91C_CKGR_USBDIV         (0x3 << 28) // (CKGR) Divider for USB Clocks
-#define     AT91C_CKGR_USBDIV_0                    (0x0 << 28) // (CKGR) Divider output is PLL clock output
-#define     AT91C_CKGR_USBDIV_1                    (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
-#define     AT91C_CKGR_USBDIV_2                    (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Clock Generator Controller */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_CKGR structure *** */
+#define CKGR_MOR                     ( 0 )           /* Main Oscillator Register */
+#define CKGR_MCFR                    ( 4 )           /* Main Clock  Frequency Register */
+#define CKGR_PLLR                    ( 12 )          /* PLL Register */
+/* -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */
+#define AT91C_CKGR_MOSCEN            ( 0x1 << 0 )    /* (CKGR) Main Oscillator Enable */
+#define AT91C_CKGR_OSCBYPASS         ( 0x1 << 1 )    /* (CKGR) Main Oscillator Bypass */
+#define AT91C_CKGR_OSCOUNT           ( 0xFF << 8 )   /* (CKGR) Main Oscillator Start-up Time */
+/* -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- */
+#define AT91C_CKGR_MAINF             ( 0xFFFF << 0 ) /* (CKGR) Main Clock Frequency */
+#define AT91C_CKGR_MAINRDY           ( 0x1 << 16 )   /* (CKGR) Main Clock Ready */
+/* -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- */
+#define AT91C_CKGR_DIV               ( 0xFF << 0 )   /* (CKGR) Divider Selected */
+#define     AT91C_CKGR_DIV_0         ( 0x0 )         /* (CKGR) Divider output is 0 */
+#define     AT91C_CKGR_DIV_BYPASS    ( 0x1 )         /* (CKGR) Divider is bypassed */
+#define AT91C_CKGR_PLLCOUNT          ( 0x3F << 8 )   /* (CKGR) PLL Counter */
+#define AT91C_CKGR_OUT               ( 0x3 << 14 )   /* (CKGR) PLL Output Frequency Range */
+#define     AT91C_CKGR_OUT_0         ( 0x0 << 14 )   /* (CKGR) Please refer to the PLL datasheet */
+#define     AT91C_CKGR_OUT_1         ( 0x1 << 14 )   /* (CKGR) Please refer to the PLL datasheet */
+#define     AT91C_CKGR_OUT_2         ( 0x2 << 14 )   /* (CKGR) Please refer to the PLL datasheet */
+#define     AT91C_CKGR_OUT_3         ( 0x3 << 14 )   /* (CKGR) Please refer to the PLL datasheet */
+#define AT91C_CKGR_MUL               ( 0x7FF << 16 ) /* (CKGR) PLL Multiplier */
+#define AT91C_CKGR_USBDIV            ( 0x3 << 28 )   /* (CKGR) Divider for USB Clocks */
+#define     AT91C_CKGR_USBDIV_0      ( 0x0 << 28 )   /* (CKGR) Divider output is PLL clock output */
+#define     AT91C_CKGR_USBDIV_1      ( 0x1 << 28 )   /* (CKGR) Divider output is PLL clock output divided by 2 */
+#define     AT91C_CKGR_USBDIV_2      ( 0x2 << 28 )   /* (CKGR) Divider output is PLL clock output divided by 4 */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Power Management Controler
-// *****************************************************************************
-// *** Register offset in AT91S_PMC structure ***
-#define PMC_SCER        ( 0) // System Clock Enable Register
-#define PMC_SCDR        ( 4) // System Clock Disable Register
-#define PMC_SCSR        ( 8) // System Clock Status Register
-#define PMC_PCER        (16) // Peripheral Clock Enable Register
-#define PMC_PCDR        (20) // Peripheral Clock Disable Register
-#define PMC_PCSR        (24) // Peripheral Clock Status Register
-#define PMC_MOR         (32) // Main Oscillator Register
-#define PMC_MCFR        (36) // Main Clock  Frequency Register
-#define PMC_PLLR        (44) // PLL Register
-#define PMC_MCKR        (48) // Master Clock Register
-#define PMC_PCKR        (64) // Programmable Clock Register
-#define PMC_IER         (96) // Interrupt Enable Register
-#define PMC_IDR         (100) // Interrupt Disable Register
-#define PMC_SR          (104) // Status Register
-#define PMC_IMR         (108) // Interrupt Mask Register
-// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
-#define AT91C_PMC_PCK             (0x1 <<  0) // (PMC) Processor Clock
-#define AT91C_PMC_UDP             (0x1 <<  7) // (PMC) USB Device Port Clock
-#define AT91C_PMC_PCK0            (0x1 <<  8) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK1            (0x1 <<  9) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK2            (0x1 << 10) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK3            (0x1 << 11) // (PMC) Programmable Clock Output
-// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
-// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
-// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
-// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
-// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
-// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
-#define AT91C_PMC_CSS             (0x3 <<  0) // (PMC) Programmable Clock Selection
-#define     AT91C_PMC_CSS_SLOW_CLK             (0x0) // (PMC) Slow Clock is selected
-#define     AT91C_PMC_CSS_MAIN_CLK             (0x1) // (PMC) Main Clock is selected
-#define     AT91C_PMC_CSS_PLL_CLK              (0x3) // (PMC) Clock from PLL is selected
-#define AT91C_PMC_PRES            (0x7 <<  2) // (PMC) Programmable Clock Prescaler
-#define     AT91C_PMC_PRES_CLK                  (0x0 <<  2) // (PMC) Selected clock
-#define     AT91C_PMC_PRES_CLK_2                (0x1 <<  2) // (PMC) Selected clock divided by 2
-#define     AT91C_PMC_PRES_CLK_4                (0x2 <<  2) // (PMC) Selected clock divided by 4
-#define     AT91C_PMC_PRES_CLK_8                (0x3 <<  2) // (PMC) Selected clock divided by 8
-#define     AT91C_PMC_PRES_CLK_16               (0x4 <<  2) // (PMC) Selected clock divided by 16
-#define     AT91C_PMC_PRES_CLK_32               (0x5 <<  2) // (PMC) Selected clock divided by 32
-#define     AT91C_PMC_PRES_CLK_64               (0x6 <<  2) // (PMC) Selected clock divided by 64
-// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
-// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
-#define AT91C_PMC_MOSCS           (0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask
-#define AT91C_PMC_LOCK            (0x1 <<  2) // (PMC) PLL Status/Enable/Disable/Mask
-#define AT91C_PMC_MCKRDY          (0x1 <<  3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK0RDY         (0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK1RDY         (0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK2RDY         (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK3RDY         (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
-// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
-// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
-// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Power Management Controller */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_PMC structure *** */
+#define PMC_SCER          ( 0 )         /* System Clock Enable Register */
+#define PMC_SCDR          ( 4 )         /* System Clock Disable Register */
+#define PMC_SCSR          ( 8 )         /* System Clock Status Register */
+#define PMC_PCER          ( 16 )        /* Peripheral Clock Enable Register */
+#define PMC_PCDR          ( 20 )        /* Peripheral Clock Disable Register */
+#define PMC_PCSR          ( 24 )        /* Peripheral Clock Status Register */
+#define PMC_MOR           ( 32 )        /* Main Oscillator Register */
+#define PMC_MCFR          ( 36 )        /* Main Clock  Frequency Register */
+#define PMC_PLLR          ( 44 )        /* PLL Register */
+#define PMC_MCKR          ( 48 )        /* Master Clock Register */
+#define PMC_PCKR          ( 64 )        /* Programmable Clock Register */
+#define PMC_IER           ( 96 )        /* Interrupt Enable Register */
+#define PMC_IDR           ( 100 )       /* Interrupt Disable Register */
+#define PMC_SR            ( 104 )       /* Status Register */
+#define PMC_IMR           ( 108 )       /* Interrupt Mask Register */
+/* -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- */
+#define AT91C_PMC_PCK     ( 0x1 << 0 )  /* (PMC) Processor Clock */
+#define AT91C_PMC_UDP     ( 0x1 << 7 )  /* (PMC) USB Device Port Clock */
+#define AT91C_PMC_PCK0    ( 0x1 << 8 )  /* (PMC) Programmable Clock Output */
+#define AT91C_PMC_PCK1    ( 0x1 << 9 )  /* (PMC) Programmable Clock Output */
+#define AT91C_PMC_PCK2    ( 0x1 << 10 ) /* (PMC) Programmable Clock Output */
+#define AT91C_PMC_PCK3    ( 0x1 << 11 ) /* (PMC) Programmable Clock Output */
+/* -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- */
+/* -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- */
+/* -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- */
+/* -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- */
+/* -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- */
+/* -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- */
+#define AT91C_PMC_CSS                 ( 0x3 << 0 ) /* (PMC) Programmable Clock Selection */
+#define     AT91C_PMC_CSS_SLOW_CLK    ( 0x0 )      /* (PMC) Slow Clock is selected */
+#define     AT91C_PMC_CSS_MAIN_CLK    ( 0x1 )      /* (PMC) Main Clock is selected */
+#define     AT91C_PMC_CSS_PLL_CLK     ( 0x3 )      /* (PMC) Clock from PLL is selected */
+#define AT91C_PMC_PRES                ( 0x7 << 2 ) /* (PMC) Programmable Clock Prescaler */
+#define     AT91C_PMC_PRES_CLK        ( 0x0 << 2 ) /* (PMC) Selected clock */
+#define     AT91C_PMC_PRES_CLK_2      ( 0x1 << 2 ) /* (PMC) Selected clock divided by 2 */
+#define     AT91C_PMC_PRES_CLK_4      ( 0x2 << 2 ) /* (PMC) Selected clock divided by 4 */
+#define     AT91C_PMC_PRES_CLK_8      ( 0x3 << 2 ) /* (PMC) Selected clock divided by 8 */
+#define     AT91C_PMC_PRES_CLK_16     ( 0x4 << 2 ) /* (PMC) Selected clock divided by 16 */
+#define     AT91C_PMC_PRES_CLK_32     ( 0x5 << 2 ) /* (PMC) Selected clock divided by 32 */
+#define     AT91C_PMC_PRES_CLK_64     ( 0x6 << 2 ) /* (PMC) Selected clock divided by 64 */
+/* -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- */
+/* -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- */
+#define AT91C_PMC_MOSCS               ( 0x1 << 0 )  /* (PMC) MOSC Status/Enable/Disable/Mask */
+#define AT91C_PMC_LOCK                ( 0x1 << 2 )  /* (PMC) PLL Status/Enable/Disable/Mask */
+#define AT91C_PMC_MCKRDY              ( 0x1 << 3 )  /* (PMC) MCK_RDY Status/Enable/Disable/Mask */
+#define AT91C_PMC_PCK0RDY             ( 0x1 << 8 )  /* (PMC) PCK0_RDY Status/Enable/Disable/Mask */
+#define AT91C_PMC_PCK1RDY             ( 0x1 << 9 )  /* (PMC) PCK1_RDY Status/Enable/Disable/Mask */
+#define AT91C_PMC_PCK2RDY             ( 0x1 << 10 ) /* (PMC) PCK2_RDY Status/Enable/Disable/Mask */
+#define AT91C_PMC_PCK3RDY             ( 0x1 << 11 ) /* (PMC) PCK3_RDY Status/Enable/Disable/Mask */
+/* -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- */
+/* -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- */
+/* -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Reset Controller Interface
-// *****************************************************************************
-// *** Register offset in AT91S_RSTC structure ***
-#define RSTC_RCR        ( 0) // Reset Control Register
-#define RSTC_RSR        ( 4) // Reset Status Register
-#define RSTC_RMR        ( 8) // Reset Mode Register
-// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
-#define AT91C_RSTC_PROCRST        (0x1 <<  0) // (RSTC) Processor Reset
-#define AT91C_RSTC_PERRST         (0x1 <<  2) // (RSTC) Peripheral Reset
-#define AT91C_RSTC_EXTRST         (0x1 <<  3) // (RSTC) External Reset
-#define AT91C_RSTC_KEY            (0xFF << 24) // (RSTC) Password
-// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
-#define AT91C_RSTC_URSTS          (0x1 <<  0) // (RSTC) User Reset Status
-#define AT91C_RSTC_BODSTS         (0x1 <<  1) // (RSTC) Brownout Detection Status
-#define AT91C_RSTC_RSTTYP         (0x7 <<  8) // (RSTC) Reset Type
-#define     AT91C_RSTC_RSTTYP_POWERUP              (0x0 <<  8) // (RSTC) Power-up Reset. VDDCORE rising.
-#define     AT91C_RSTC_RSTTYP_WAKEUP               (0x1 <<  8) // (RSTC) WakeUp Reset. VDDCORE rising.
-#define     AT91C_RSTC_RSTTYP_WATCHDOG             (0x2 <<  8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
-#define     AT91C_RSTC_RSTTYP_SOFTWARE             (0x3 <<  8) // (RSTC) Software Reset. Processor reset required by the software.
-#define     AT91C_RSTC_RSTTYP_USER                 (0x4 <<  8) // (RSTC) User Reset. NRST pin detected low.
-#define     AT91C_RSTC_RSTTYP_BROWNOUT             (0x5 <<  8) // (RSTC) Brownout Reset occured.
-#define AT91C_RSTC_NRSTL          (0x1 << 16) // (RSTC) NRST pin level
-#define AT91C_RSTC_SRCMP          (0x1 << 17) // (RSTC) Software Reset Command in Progress.
-// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
-#define AT91C_RSTC_URSTEN         (0x1 <<  0) // (RSTC) User Reset Enable
-#define AT91C_RSTC_URSTIEN        (0x1 <<  4) // (RSTC) User Reset Interrupt Enable
-#define AT91C_RSTC_ERSTL          (0xF <<  8) // (RSTC) User Reset Enable
-#define AT91C_RSTC_BODIEN         (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Reset Controller Interface */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_RSTC structure *** */
+#define RSTC_RCR                          ( 0 )          /* Reset Control Register */
+#define RSTC_RSR                          ( 4 )          /* Reset Status Register */
+#define RSTC_RMR                          ( 8 )          /* Reset Mode Register */
+/* -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- */
+#define AT91C_RSTC_PROCRST                ( 0x1 << 0 )   /* (RSTC) Processor Reset */
+#define AT91C_RSTC_PERRST                 ( 0x1 << 2 )   /* (RSTC) Peripheral Reset */
+#define AT91C_RSTC_EXTRST                 ( 0x1 << 3 )   /* (RSTC) External Reset */
+#define AT91C_RSTC_KEY                    ( 0xFF << 24 ) /* (RSTC) Password */
+/* -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- */
+#define AT91C_RSTC_URSTS                  ( 0x1 << 0 )   /* (RSTC) User Reset Status */
+#define AT91C_RSTC_BODSTS                 ( 0x1 << 1 )   /* (RSTC) Brownout Detection Status */
+#define AT91C_RSTC_RSTTYP                 ( 0x7 << 8 )   /* (RSTC) Reset Type */
+#define     AT91C_RSTC_RSTTYP_POWERUP     ( 0x0 << 8 )   /* (RSTC) Power-up Reset. VDDCORE rising. */
+#define     AT91C_RSTC_RSTTYP_WAKEUP      ( 0x1 << 8 )   /* (RSTC) WakeUp Reset. VDDCORE rising. */
+#define     AT91C_RSTC_RSTTYP_WATCHDOG    ( 0x2 << 8 )   /* (RSTC) Watchdog Reset. Watchdog overflow occurred. */
+#define     AT91C_RSTC_RSTTYP_SOFTWARE    ( 0x3 << 8 )   /* (RSTC) Software Reset. Processor reset required by the software. */
+#define     AT91C_RSTC_RSTTYP_USER        ( 0x4 << 8 )   /* (RSTC) User Reset. NRST pin detected low. */
+#define     AT91C_RSTC_RSTTYP_BROWNOUT    ( 0x5 << 8 )   /* (RSTC) Brownout Reset occurred. */
+#define AT91C_RSTC_NRSTL                  ( 0x1 << 16 )  /* (RSTC) NRST pin level */
+#define AT91C_RSTC_SRCMP                  ( 0x1 << 17 )  /* (RSTC) Software Reset Command in Progress. */
+/* -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- */
+#define AT91C_RSTC_URSTEN                 ( 0x1 << 0 )   /* (RSTC) User Reset Enable */
+#define AT91C_RSTC_URSTIEN                ( 0x1 << 4 )   /* (RSTC) User Reset Interrupt Enable */
+#define AT91C_RSTC_ERSTL                  ( 0xF << 8 )   /* (RSTC) User Reset Enable */
+#define AT91C_RSTC_BODIEN                 ( 0x1 << 16 )  /* (RSTC) Brownout Detection Interrupt Enable */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
-// *****************************************************************************
-// *** Register offset in AT91S_RTTC structure ***
-#define RTTC_RTMR       ( 0) // Real-time Mode Register
-#define RTTC_RTAR       ( 4) // Real-time Alarm Register
-#define RTTC_RTVR       ( 8) // Real-time Value Register
-#define RTTC_RTSR       (12) // Real-time Status Register
-// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
-#define AT91C_RTTC_RTPRES         (0xFFFF <<  0) // (RTTC) Real-time Timer Prescaler Value
-#define AT91C_RTTC_ALMIEN         (0x1 << 16) // (RTTC) Alarm Interrupt Enable
-#define AT91C_RTTC_RTTINCIEN      (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
-#define AT91C_RTTC_RTTRST         (0x1 << 18) // (RTTC) Real Time Timer Restart
-// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
-#define AT91C_RTTC_ALMV           (0x0 <<  0) // (RTTC) Alarm Value
-// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
-#define AT91C_RTTC_CRTV           (0x0 <<  0) // (RTTC) Current Real-time Value
-// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
-#define AT91C_RTTC_ALMS           (0x1 <<  0) // (RTTC) Real-time Alarm Status
-#define AT91C_RTTC_RTTINC         (0x1 <<  1) // (RTTC) Real-time Timer Increment
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_RTTC structure *** */
+#define RTTC_RTMR               ( 0 )           /* Real-time Mode Register */
+#define RTTC_RTAR               ( 4 )           /* Real-time Alarm Register */
+#define RTTC_RTVR               ( 8 )           /* Real-time Value Register */
+#define RTTC_RTSR               ( 12 )          /* Real-time Status Register */
+/* -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- */
+#define AT91C_RTTC_RTPRES       ( 0xFFFF << 0 ) /* (RTTC) Real-time Timer Prescaler Value */
+#define AT91C_RTTC_ALMIEN       ( 0x1 << 16 )   /* (RTTC) Alarm Interrupt Enable */
+#define AT91C_RTTC_RTTINCIEN    ( 0x1 << 17 )   /* (RTTC) Real Time Timer Increment Interrupt Enable */
+#define AT91C_RTTC_RTTRST       ( 0x1 << 18 )   /* (RTTC) Real Time Timer Restart */
+/* -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- */
+#define AT91C_RTTC_ALMV         ( 0x0 << 0 )    /* (RTTC) Alarm Value */
+/* -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- */
+#define AT91C_RTTC_CRTV         ( 0x0 << 0 )    /* (RTTC) Current Real-time Value */
+/* -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- */
+#define AT91C_RTTC_ALMS         ( 0x1 << 0 )    /* (RTTC) Real-time Alarm Status */
+#define AT91C_RTTC_RTTINC       ( 0x1 << 1 )    /* (RTTC) Real-time Timer Increment */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
-// *****************************************************************************
-// *** Register offset in AT91S_PITC structure ***
-#define PITC_PIMR       ( 0) // Period Interval Mode Register
-#define PITC_PISR       ( 4) // Period Interval Status Register
-#define PITC_PIVR       ( 8) // Period Interval Value Register
-#define PITC_PIIR       (12) // Period Interval Image Register
-// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
-#define AT91C_PITC_PIV            (0xFFFFF <<  0) // (PITC) Periodic Interval Value
-#define AT91C_PITC_PITEN          (0x1 << 24) // (PITC) Periodic Interval Timer Enabled
-#define AT91C_PITC_PITIEN         (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
-// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
-#define AT91C_PITC_PITS           (0x1 <<  0) // (PITC) Periodic Interval Timer Status
-// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
-#define AT91C_PITC_CPIV           (0xFFFFF <<  0) // (PITC) Current Periodic Interval Value
-#define AT91C_PITC_PICNT          (0xFFF << 20) // (PITC) Periodic Interval Counter
-// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_PITC structure *** */
+#define PITC_PIMR            ( 0 )            /* Period Interval Mode Register */
+#define PITC_PISR            ( 4 )            /* Period Interval Status Register */
+#define PITC_PIVR            ( 8 )            /* Period Interval Value Register */
+#define PITC_PIIR            ( 12 )           /* Period Interval Image Register */
+/* -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- */
+#define AT91C_PITC_PIV       ( 0xFFFFF << 0 ) /* (PITC) Periodic Interval Value */
+#define AT91C_PITC_PITEN     ( 0x1 << 24 )    /* (PITC) Periodic Interval Timer Enabled */
+#define AT91C_PITC_PITIEN    ( 0x1 << 25 )    /* (PITC) Periodic Interval Timer Interrupt Enable */
+/* -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- */
+#define AT91C_PITC_PITS      ( 0x1 << 0 )     /* (PITC) Periodic Interval Timer Status */
+/* -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- */
+#define AT91C_PITC_CPIV      ( 0xFFFFF << 0 ) /* (PITC) Current Periodic Interval Value */
+#define AT91C_PITC_PICNT     ( 0xFFF << 20 )  /* (PITC) Periodic Interval Counter */
+/* -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
-// *****************************************************************************
-// *** Register offset in AT91S_WDTC structure ***
-#define WDTC_WDCR       ( 0) // Watchdog Control Register
-#define WDTC_WDMR       ( 4) // Watchdog Mode Register
-#define WDTC_WDSR       ( 8) // Watchdog Status Register
-// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
-#define AT91C_WDTC_WDRSTT         (0x1 <<  0) // (WDTC) Watchdog Restart
-#define AT91C_WDTC_KEY            (0xFF << 24) // (WDTC) Watchdog KEY Password
-// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
-#define AT91C_WDTC_WDV            (0xFFF <<  0) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDFIEN         (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
-#define AT91C_WDTC_WDRSTEN        (0x1 << 13) // (WDTC) Watchdog Reset Enable
-#define AT91C_WDTC_WDRPROC        (0x1 << 14) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDDIS          (0x1 << 15) // (WDTC) Watchdog Disable
-#define AT91C_WDTC_WDD            (0xFFF << 16) // (WDTC) Watchdog Delta Value
-#define AT91C_WDTC_WDDBGHLT       (0x1 << 28) // (WDTC) Watchdog Debug Halt
-#define AT91C_WDTC_WDIDLEHLT      (0x1 << 29) // (WDTC) Watchdog Idle Halt
-// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
-#define AT91C_WDTC_WDUNF          (0x1 <<  0) // (WDTC) Watchdog Underflow
-#define AT91C_WDTC_WDERR          (0x1 <<  1) // (WDTC) Watchdog Error
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_WDTC structure *** */
+#define WDTC_WDCR               ( 0 )           /* Watchdog Control Register */
+#define WDTC_WDMR               ( 4 )           /* Watchdog Mode Register */
+#define WDTC_WDSR               ( 8 )           /* Watchdog Status Register */
+/* -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- */
+#define AT91C_WDTC_WDRSTT       ( 0x1 << 0 )    /* (WDTC) Watchdog Restart */
+#define AT91C_WDTC_KEY          ( 0xFF << 24 )  /* (WDTC) Watchdog KEY Password */
+/* -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- */
+#define AT91C_WDTC_WDV          ( 0xFFF << 0 )  /* (WDTC) Watchdog Timer Restart */
+#define AT91C_WDTC_WDFIEN       ( 0x1 << 12 )   /* (WDTC) Watchdog Fault Interrupt Enable */
+#define AT91C_WDTC_WDRSTEN      ( 0x1 << 13 )   /* (WDTC) Watchdog Reset Enable */
+#define AT91C_WDTC_WDRPROC      ( 0x1 << 14 )   /* (WDTC) Watchdog Timer Restart */
+#define AT91C_WDTC_WDDIS        ( 0x1 << 15 )   /* (WDTC) Watchdog Disable */
+#define AT91C_WDTC_WDD          ( 0xFFF << 16 ) /* (WDTC) Watchdog Delta Value */
+#define AT91C_WDTC_WDDBGHLT     ( 0x1 << 28 )   /* (WDTC) Watchdog Debug Halt */
+#define AT91C_WDTC_WDIDLEHLT    ( 0x1 << 29 )   /* (WDTC) Watchdog Idle Halt */
+/* -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- */
+#define AT91C_WDTC_WDUNF        ( 0x1 << 0 )    /* (WDTC) Watchdog Underflow */
+#define AT91C_WDTC_WDERR        ( 0x1 << 1 )    /* (WDTC) Watchdog Error */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Voltage Regulator Mode Controller Interface
-// *****************************************************************************
-// *** Register offset in AT91S_VREG structure ***
-#define VREG_MR         ( 0) // Voltage Regulator Mode Register
-// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register --------
-#define AT91C_VREG_PSTDBY         (0x1 <<  0) // (VREG) Voltage Regulator Power Standby Mode
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Voltage Regulator Mode Controller Interface */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_VREG structure *** */
+#define VREG_MR              ( 0 )        /* Voltage Regulator Mode Register */
+/* -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- */
+#define AT91C_VREG_PSTDBY    ( 0x1 << 0 ) /* (VREG) Voltage Regulator Power Standby Mode */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Memory Controller Interface
-// *****************************************************************************
-// *** Register offset in AT91S_MC structure ***
-#define MC_RCR          ( 0) // MC Remap Control Register
-#define MC_ASR          ( 4) // MC Abort Status Register
-#define MC_AASR         ( 8) // MC Abort Address Status Register
-#define MC_FMR          (96) // MC Flash Mode Register
-#define MC_FCR          (100) // MC Flash Command Register
-#define MC_FSR          (104) // MC Flash Status Register
-// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
-#define AT91C_MC_RCB              (0x1 <<  0) // (MC) Remap Command Bit
-// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
-#define AT91C_MC_UNDADD           (0x1 <<  0) // (MC) Undefined Addess Abort Status
-#define AT91C_MC_MISADD           (0x1 <<  1) // (MC) Misaligned Addess Abort Status
-#define AT91C_MC_ABTSZ            (0x3 <<  8) // (MC) Abort Size Status
-#define     AT91C_MC_ABTSZ_BYTE                 (0x0 <<  8) // (MC) Byte
-#define     AT91C_MC_ABTSZ_HWORD                (0x1 <<  8) // (MC) Half-word
-#define     AT91C_MC_ABTSZ_WORD                 (0x2 <<  8) // (MC) Word
-#define AT91C_MC_ABTTYP           (0x3 << 10) // (MC) Abort Type Status
-#define     AT91C_MC_ABTTYP_DATAR                (0x0 << 10) // (MC) Data Read
-#define     AT91C_MC_ABTTYP_DATAW                (0x1 << 10) // (MC) Data Write
-#define     AT91C_MC_ABTTYP_FETCH                (0x2 << 10) // (MC) Code Fetch
-#define AT91C_MC_MST0             (0x1 << 16) // (MC) Master 0 Abort Source
-#define AT91C_MC_MST1             (0x1 << 17) // (MC) Master 1 Abort Source
-#define AT91C_MC_SVMST0           (0x1 << 24) // (MC) Saved Master 0 Abort Source
-#define AT91C_MC_SVMST1           (0x1 << 25) // (MC) Saved Master 1 Abort Source
-// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
-#define AT91C_MC_FRDY             (0x1 <<  0) // (MC) Flash Ready
-#define AT91C_MC_LOCKE            (0x1 <<  2) // (MC) Lock Error
-#define AT91C_MC_PROGE            (0x1 <<  3) // (MC) Programming Error
-#define AT91C_MC_NEBP             (0x1 <<  7) // (MC) No Erase Before Programming
-#define AT91C_MC_FWS              (0x3 <<  8) // (MC) Flash Wait State
-#define     AT91C_MC_FWS_0FWS                 (0x0 <<  8) // (MC) 1 cycle for Read, 2 for Write operations
-#define     AT91C_MC_FWS_1FWS                 (0x1 <<  8) // (MC) 2 cycles for Read, 3 for Write operations
-#define     AT91C_MC_FWS_2FWS                 (0x2 <<  8) // (MC) 3 cycles for Read, 4 for Write operations
-#define     AT91C_MC_FWS_3FWS                 (0x3 <<  8) // (MC) 4 cycles for Read, 4 for Write operations
-#define AT91C_MC_FMCN             (0xFF << 16) // (MC) Flash Microsecond Cycle Number
-// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
-#define AT91C_MC_FCMD             (0xF <<  0) // (MC) Flash Command
-#define     AT91C_MC_FCMD_START_PROG           (0x1) // (MC) Starts the programming of th epage specified by PAGEN.
-#define     AT91C_MC_FCMD_LOCK                 (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define     AT91C_MC_FCMD_PROG_AND_LOCK        (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
-#define     AT91C_MC_FCMD_UNLOCK               (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define     AT91C_MC_FCMD_ERASE_ALL            (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
-#define     AT91C_MC_FCMD_SET_GP_NVM           (0xB) // (MC) Set General Purpose NVM bits.
-#define     AT91C_MC_FCMD_CLR_GP_NVM           (0xD) // (MC) Clear General Purpose NVM bits.
-#define     AT91C_MC_FCMD_SET_SECURITY         (0xF) // (MC) Set Security Bit.
-#define AT91C_MC_PAGEN            (0x3FF <<  8) // (MC) Page Number
-#define AT91C_MC_KEY              (0xFF << 24) // (MC) Writing Protect Key
-// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register --------
-#define AT91C_MC_SECURITY         (0x1 <<  4) // (MC) Security Bit Status
-#define AT91C_MC_GPNVM0           (0x1 <<  8) // (MC) Sector 0 Lock Status
-#define AT91C_MC_GPNVM1           (0x1 <<  9) // (MC) Sector 1 Lock Status
-#define AT91C_MC_GPNVM2           (0x1 << 10) // (MC) Sector 2 Lock Status
-#define AT91C_MC_GPNVM3           (0x1 << 11) // (MC) Sector 3 Lock Status
-#define AT91C_MC_GPNVM4           (0x1 << 12) // (MC) Sector 4 Lock Status
-#define AT91C_MC_GPNVM5           (0x1 << 13) // (MC) Sector 5 Lock Status
-#define AT91C_MC_GPNVM6           (0x1 << 14) // (MC) Sector 6 Lock Status
-#define AT91C_MC_GPNVM7           (0x1 << 15) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS0           (0x1 << 16) // (MC) Sector 0 Lock Status
-#define AT91C_MC_LOCKS1           (0x1 << 17) // (MC) Sector 1 Lock Status
-#define AT91C_MC_LOCKS2           (0x1 << 18) // (MC) Sector 2 Lock Status
-#define AT91C_MC_LOCKS3           (0x1 << 19) // (MC) Sector 3 Lock Status
-#define AT91C_MC_LOCKS4           (0x1 << 20) // (MC) Sector 4 Lock Status
-#define AT91C_MC_LOCKS5           (0x1 << 21) // (MC) Sector 5 Lock Status
-#define AT91C_MC_LOCKS6           (0x1 << 22) // (MC) Sector 6 Lock Status
-#define AT91C_MC_LOCKS7           (0x1 << 23) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS8           (0x1 << 24) // (MC) Sector 8 Lock Status
-#define AT91C_MC_LOCKS9           (0x1 << 25) // (MC) Sector 9 Lock Status
-#define AT91C_MC_LOCKS10          (0x1 << 26) // (MC) Sector 10 Lock Status
-#define AT91C_MC_LOCKS11          (0x1 << 27) // (MC) Sector 11 Lock Status
-#define AT91C_MC_LOCKS12          (0x1 << 28) // (MC) Sector 12 Lock Status
-#define AT91C_MC_LOCKS13          (0x1 << 29) // (MC) Sector 13 Lock Status
-#define AT91C_MC_LOCKS14          (0x1 << 30) // (MC) Sector 14 Lock Status
-#define AT91C_MC_LOCKS15          (0x1 << 31) // (MC) Sector 15 Lock Status
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Memory Controller Interface */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_MC structure *** */
+#define MC_RCR                             ( 0 )          /* MC Remap Control Register */
+#define MC_ASR                             ( 4 )          /* MC Abort Status Register */
+#define MC_AASR                            ( 8 )          /* MC Abort Address Status Register */
+#define MC_FMR                             ( 96 )         /* MC Flash Mode Register */
+#define MC_FCR                             ( 100 )        /* MC Flash Command Register */
+#define MC_FSR                             ( 104 )        /* MC Flash Status Register */
+/* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */
+#define AT91C_MC_RCB                       ( 0x1 << 0 )   /* (MC) Remap Command Bit */
+/* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */
+#define AT91C_MC_UNDADD                    ( 0x1 << 0 )   /* (MC) Undefined Addess Abort Status */
+#define AT91C_MC_MISADD                    ( 0x1 << 1 )   /* (MC) Misaligned Addess Abort Status */
+#define AT91C_MC_ABTSZ                     ( 0x3 << 8 )   /* (MC) Abort Size Status */
+#define     AT91C_MC_ABTSZ_BYTE            ( 0x0 << 8 )   /* (MC) Byte */
+#define     AT91C_MC_ABTSZ_HWORD           ( 0x1 << 8 )   /* (MC) Half-word */
+#define     AT91C_MC_ABTSZ_WORD            ( 0x2 << 8 )   /* (MC) Word */
+#define AT91C_MC_ABTTYP                    ( 0x3 << 10 )  /* (MC) Abort Type Status */
+#define     AT91C_MC_ABTTYP_DATAR          ( 0x0 << 10 )  /* (MC) Data Read */
+#define     AT91C_MC_ABTTYP_DATAW          ( 0x1 << 10 )  /* (MC) Data Write */
+#define     AT91C_MC_ABTTYP_FETCH          ( 0x2 << 10 )  /* (MC) Code Fetch */
+#define AT91C_MC_MST0                      ( 0x1 << 16 )  /* (MC) Master 0 Abort Source */
+#define AT91C_MC_MST1                      ( 0x1 << 17 )  /* (MC) Master 1 Abort Source */
+#define AT91C_MC_SVMST0                    ( 0x1 << 24 )  /* (MC) Saved Master 0 Abort Source */
+#define AT91C_MC_SVMST1                    ( 0x1 << 25 )  /* (MC) Saved Master 1 Abort Source */
+/* -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- */
+#define AT91C_MC_FRDY                      ( 0x1 << 0 )   /* (MC) Flash Ready */
+#define AT91C_MC_LOCKE                     ( 0x1 << 2 )   /* (MC) Lock Error */
+#define AT91C_MC_PROGE                     ( 0x1 << 3 )   /* (MC) Programming Error */
+#define AT91C_MC_NEBP                      ( 0x1 << 7 )   /* (MC) No Erase Before Programming */
+#define AT91C_MC_FWS                       ( 0x3 << 8 )   /* (MC) Flash Wait State */
+#define     AT91C_MC_FWS_0FWS              ( 0x0 << 8 )   /* (MC) 1 cycle for Read, 2 for Write operations */
+#define     AT91C_MC_FWS_1FWS              ( 0x1 << 8 )   /* (MC) 2 cycles for Read, 3 for Write operations */
+#define     AT91C_MC_FWS_2FWS              ( 0x2 << 8 )   /* (MC) 3 cycles for Read, 4 for Write operations */
+#define     AT91C_MC_FWS_3FWS              ( 0x3 << 8 )   /* (MC) 4 cycles for Read, 4 for Write operations */
+#define AT91C_MC_FMCN                      ( 0xFF << 16 ) /* (MC) Flash Microsecond Cycle Number */
+/* -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- */
+#define AT91C_MC_FCMD                      ( 0xF << 0 )   /* (MC) Flash Command */
+#define     AT91C_MC_FCMD_START_PROG       ( 0x1 )        /* (MC) Starts the programming of th epage specified by PAGEN. */
+#define     AT91C_MC_FCMD_LOCK             ( 0x2 )        /* (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */
+#define     AT91C_MC_FCMD_PROG_AND_LOCK    ( 0x3 )        /* (MC) The lock sequence automatically happens after the programming sequence is completed. */
+#define     AT91C_MC_FCMD_UNLOCK           ( 0x4 )        /* (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */
+#define     AT91C_MC_FCMD_ERASE_ALL        ( 0x8 )        /* (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. */
+#define     AT91C_MC_FCMD_SET_GP_NVM       ( 0xB )        /* (MC) Set General Purpose NVM bits. */
+#define     AT91C_MC_FCMD_CLR_GP_NVM       ( 0xD )        /* (MC) Clear General Purpose NVM bits. */
+#define     AT91C_MC_FCMD_SET_SECURITY     ( 0xF )        /* (MC) Set Security Bit. */
+#define AT91C_MC_PAGEN                     ( 0x3FF << 8 ) /* (MC) Page Number */
+#define AT91C_MC_KEY                       ( 0xFF << 24 ) /* (MC) Writing Protect Key */
+/* -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- */
+#define AT91C_MC_SECURITY                  ( 0x1 << 4 )   /* (MC) Security Bit Status */
+#define AT91C_MC_GPNVM0                    ( 0x1 << 8 )   /* (MC) Sector 0 Lock Status */
+#define AT91C_MC_GPNVM1                    ( 0x1 << 9 )   /* (MC) Sector 1 Lock Status */
+#define AT91C_MC_GPNVM2                    ( 0x1 << 10 )  /* (MC) Sector 2 Lock Status */
+#define AT91C_MC_GPNVM3                    ( 0x1 << 11 )  /* (MC) Sector 3 Lock Status */
+#define AT91C_MC_GPNVM4                    ( 0x1 << 12 )  /* (MC) Sector 4 Lock Status */
+#define AT91C_MC_GPNVM5                    ( 0x1 << 13 )  /* (MC) Sector 5 Lock Status */
+#define AT91C_MC_GPNVM6                    ( 0x1 << 14 )  /* (MC) Sector 6 Lock Status */
+#define AT91C_MC_GPNVM7                    ( 0x1 << 15 )  /* (MC) Sector 7 Lock Status */
+#define AT91C_MC_LOCKS0                    ( 0x1 << 16 )  /* (MC) Sector 0 Lock Status */
+#define AT91C_MC_LOCKS1                    ( 0x1 << 17 )  /* (MC) Sector 1 Lock Status */
+#define AT91C_MC_LOCKS2                    ( 0x1 << 18 )  /* (MC) Sector 2 Lock Status */
+#define AT91C_MC_LOCKS3                    ( 0x1 << 19 )  /* (MC) Sector 3 Lock Status */
+#define AT91C_MC_LOCKS4                    ( 0x1 << 20 )  /* (MC) Sector 4 Lock Status */
+#define AT91C_MC_LOCKS5                    ( 0x1 << 21 )  /* (MC) Sector 5 Lock Status */
+#define AT91C_MC_LOCKS6                    ( 0x1 << 22 )  /* (MC) Sector 6 Lock Status */
+#define AT91C_MC_LOCKS7                    ( 0x1 << 23 )  /* (MC) Sector 7 Lock Status */
+#define AT91C_MC_LOCKS8                    ( 0x1 << 24 )  /* (MC) Sector 8 Lock Status */
+#define AT91C_MC_LOCKS9                    ( 0x1 << 25 )  /* (MC) Sector 9 Lock Status */
+#define AT91C_MC_LOCKS10                   ( 0x1 << 26 )  /* (MC) Sector 10 Lock Status */
+#define AT91C_MC_LOCKS11                   ( 0x1 << 27 )  /* (MC) Sector 11 Lock Status */
+#define AT91C_MC_LOCKS12                   ( 0x1 << 28 )  /* (MC) Sector 12 Lock Status */
+#define AT91C_MC_LOCKS13                   ( 0x1 << 29 )  /* (MC) Sector 13 Lock Status */
+#define AT91C_MC_LOCKS14                   ( 0x1 << 30 )  /* (MC) Sector 14 Lock Status */
+#define AT91C_MC_LOCKS15                   ( 0x1 << 31 )  /* (MC) Sector 15 Lock Status */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
-// *****************************************************************************
-// *** Register offset in AT91S_SPI structure ***
-#define SPI_CR          ( 0) // Control Register
-#define SPI_MR          ( 4) // Mode Register
-#define SPI_RDR         ( 8) // Receive Data Register
-#define SPI_TDR         (12) // Transmit Data Register
-#define SPI_SR          (16) // Status Register
-#define SPI_IER         (20) // Interrupt Enable Register
-#define SPI_IDR         (24) // Interrupt Disable Register
-#define SPI_IMR         (28) // Interrupt Mask Register
-#define SPI_CSR         (48) // Chip Select Register
-#define SPI_RPR         (256) // Receive Pointer Register
-#define SPI_RCR         (260) // Receive Counter Register
-#define SPI_TPR         (264) // Transmit Pointer Register
-#define SPI_TCR         (268) // Transmit Counter Register
-#define SPI_RNPR        (272) // Receive Next Pointer Register
-#define SPI_RNCR        (276) // Receive Next Counter Register
-#define SPI_TNPR        (280) // Transmit Next Pointer Register
-#define SPI_TNCR        (284) // Transmit Next Counter Register
-#define SPI_PTCR        (288) // PDC Transfer Control Register
-#define SPI_PTSR        (292) // PDC Transfer Status Register
-// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
-#define AT91C_SPI_SPIEN           (0x1 <<  0) // (SPI) SPI Enable
-#define AT91C_SPI_SPIDIS          (0x1 <<  1) // (SPI) SPI Disable
-#define AT91C_SPI_SWRST           (0x1 <<  7) // (SPI) SPI Software reset
-#define AT91C_SPI_LASTXFER        (0x1 << 24) // (SPI) SPI Last Transfer
-// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
-#define AT91C_SPI_MSTR            (0x1 <<  0) // (SPI) Master/Slave Mode
-#define AT91C_SPI_PS              (0x1 <<  1) // (SPI) Peripheral Select
-#define     AT91C_SPI_PS_FIXED                (0x0 <<  1) // (SPI) Fixed Peripheral Select
-#define     AT91C_SPI_PS_VARIABLE             (0x1 <<  1) // (SPI) Variable Peripheral Select
-#define AT91C_SPI_PCSDEC          (0x1 <<  2) // (SPI) Chip Select Decode
-#define AT91C_SPI_FDIV            (0x1 <<  3) // (SPI) Clock Selection
-#define AT91C_SPI_MODFDIS         (0x1 <<  4) // (SPI) Mode Fault Detection
-#define AT91C_SPI_LLB             (0x1 <<  7) // (SPI) Clock Selection
-#define AT91C_SPI_PCS             (0xF << 16) // (SPI) Peripheral Chip Select
-#define AT91C_SPI_DLYBCS          (0xFF << 24) // (SPI) Delay Between Chip Selects
-// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
-#define AT91C_SPI_RD              (0xFFFF <<  0) // (SPI) Receive Data
-#define AT91C_SPI_RPCS            (0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
-#define AT91C_SPI_TD              (0xFFFF <<  0) // (SPI) Transmit Data
-#define AT91C_SPI_TPCS            (0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
-#define AT91C_SPI_RDRF            (0x1 <<  0) // (SPI) Receive Data Register Full
-#define AT91C_SPI_TDRE            (0x1 <<  1) // (SPI) Transmit Data Register Empty
-#define AT91C_SPI_MODF            (0x1 <<  2) // (SPI) Mode Fault Error
-#define AT91C_SPI_OVRES           (0x1 <<  3) // (SPI) Overrun Error Status
-#define AT91C_SPI_ENDRX           (0x1 <<  4) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_ENDTX           (0x1 <<  5) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_RXBUFF          (0x1 <<  6) // (SPI) RXBUFF Interrupt
-#define AT91C_SPI_TXBUFE          (0x1 <<  7) // (SPI) TXBUFE Interrupt
-#define AT91C_SPI_NSSR            (0x1 <<  8) // (SPI) NSSR Interrupt
-#define AT91C_SPI_TXEMPTY         (0x1 <<  9) // (SPI) TXEMPTY Interrupt
-#define AT91C_SPI_SPIENS          (0x1 << 16) // (SPI) Enable Status
-// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
-// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
-// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
-// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
-#define AT91C_SPI_CPOL            (0x1 <<  0) // (SPI) Clock Polarity
-#define AT91C_SPI_NCPHA           (0x1 <<  1) // (SPI) Clock Phase
-#define AT91C_SPI_CSAAT           (0x1 <<  3) // (SPI) Chip Select Active After Transfer
-#define AT91C_SPI_BITS            (0xF <<  4) // (SPI) Bits Per Transfer
-#define     AT91C_SPI_BITS_8                    (0x0 <<  4) // (SPI) 8 Bits Per transfer
-#define     AT91C_SPI_BITS_9                    (0x1 <<  4) // (SPI) 9 Bits Per transfer
-#define     AT91C_SPI_BITS_10                   (0x2 <<  4) // (SPI) 10 Bits Per transfer
-#define     AT91C_SPI_BITS_11                   (0x3 <<  4) // (SPI) 11 Bits Per transfer
-#define     AT91C_SPI_BITS_12                   (0x4 <<  4) // (SPI) 12 Bits Per transfer
-#define     AT91C_SPI_BITS_13                   (0x5 <<  4) // (SPI) 13 Bits Per transfer
-#define     AT91C_SPI_BITS_14                   (0x6 <<  4) // (SPI) 14 Bits Per transfer
-#define     AT91C_SPI_BITS_15                   (0x7 <<  4) // (SPI) 15 Bits Per transfer
-#define     AT91C_SPI_BITS_16                   (0x8 <<  4) // (SPI) 16 Bits Per transfer
-#define AT91C_SPI_SCBR            (0xFF <<  8) // (SPI) Serial Clock Baud Rate
-#define AT91C_SPI_DLYBS           (0xFF << 16) // (SPI) Delay Before SPCK
-#define AT91C_SPI_DLYBCT          (0xFF << 24) // (SPI) Delay Between Consecutive Transfers
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Serial Parallel Interface */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_SPI structure *** */
+#define SPI_CR                       ( 0 )           /* Control Register */
+#define SPI_MR                       ( 4 )           /* Mode Register */
+#define SPI_RDR                      ( 8 )           /* Receive Data Register */
+#define SPI_TDR                      ( 12 )          /* Transmit Data Register */
+#define SPI_SR                       ( 16 )          /* Status Register */
+#define SPI_IER                      ( 20 )          /* Interrupt Enable Register */
+#define SPI_IDR                      ( 24 )          /* Interrupt Disable Register */
+#define SPI_IMR                      ( 28 )          /* Interrupt Mask Register */
+#define SPI_CSR                      ( 48 )          /* Chip Select Register */
+#define SPI_RPR                      ( 256 )         /* Receive Pointer Register */
+#define SPI_RCR                      ( 260 )         /* Receive Counter Register */
+#define SPI_TPR                      ( 264 )         /* Transmit Pointer Register */
+#define SPI_TCR                      ( 268 )         /* Transmit Counter Register */
+#define SPI_RNPR                     ( 272 )         /* Receive Next Pointer Register */
+#define SPI_RNCR                     ( 276 )         /* Receive Next Counter Register */
+#define SPI_TNPR                     ( 280 )         /* Transmit Next Pointer Register */
+#define SPI_TNCR                     ( 284 )         /* Transmit Next Counter Register */
+#define SPI_PTCR                     ( 288 )         /* PDC Transfer Control Register */
+#define SPI_PTSR                     ( 292 )         /* PDC Transfer Status Register */
+/* -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */
+#define AT91C_SPI_SPIEN              ( 0x1 << 0 )    /* (SPI) SPI Enable */
+#define AT91C_SPI_SPIDIS             ( 0x1 << 1 )    /* (SPI) SPI Disable */
+#define AT91C_SPI_SWRST              ( 0x1 << 7 )    /* (SPI) SPI Software reset */
+#define AT91C_SPI_LASTXFER           ( 0x1 << 24 )   /* (SPI) SPI Last Transfer */
+/* -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- */
+#define AT91C_SPI_MSTR               ( 0x1 << 0 )    /* (SPI) Master/Slave Mode */
+#define AT91C_SPI_PS                 ( 0x1 << 1 )    /* (SPI) Peripheral Select */
+#define     AT91C_SPI_PS_FIXED       ( 0x0 << 1 )    /* (SPI) Fixed Peripheral Select */
+#define     AT91C_SPI_PS_VARIABLE    ( 0x1 << 1 )    /* (SPI) Variable Peripheral Select */
+#define AT91C_SPI_PCSDEC             ( 0x1 << 2 )    /* (SPI) Chip Select Decode */
+#define AT91C_SPI_FDIV               ( 0x1 << 3 )    /* (SPI) Clock Selection */
+#define AT91C_SPI_MODFDIS            ( 0x1 << 4 )    /* (SPI) Mode Fault Detection */
+#define AT91C_SPI_LLB                ( 0x1 << 7 )    /* (SPI) Clock Selection */
+#define AT91C_SPI_PCS                ( 0xF << 16 )   /* (SPI) Peripheral Chip Select */
+#define AT91C_SPI_DLYBCS             ( 0xFF << 24 )  /* (SPI) Delay Between Chip Selects */
+/* -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- */
+#define AT91C_SPI_RD                 ( 0xFFFF << 0 ) /* (SPI) Receive Data */
+#define AT91C_SPI_RPCS               ( 0xF << 16 )   /* (SPI) Peripheral Chip Select Status */
+/* -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- */
+#define AT91C_SPI_TD                 ( 0xFFFF << 0 ) /* (SPI) Transmit Data */
+#define AT91C_SPI_TPCS               ( 0xF << 16 )   /* (SPI) Peripheral Chip Select Status */
+/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
+#define AT91C_SPI_RDRF               ( 0x1 << 0 )    /* (SPI) Receive Data Register Full */
+#define AT91C_SPI_TDRE               ( 0x1 << 1 )    /* (SPI) Transmit Data Register Empty */
+#define AT91C_SPI_MODF               ( 0x1 << 2 )    /* (SPI) Mode Fault Error */
+#define AT91C_SPI_OVRES              ( 0x1 << 3 )    /* (SPI) Overrun Error Status */
+#define AT91C_SPI_ENDRX              ( 0x1 << 4 )    /* (SPI) End of Receiver Transfer */
+#define AT91C_SPI_ENDTX              ( 0x1 << 5 )    /* (SPI) End of Receiver Transfer */
+#define AT91C_SPI_RXBUFF             ( 0x1 << 6 )    /* (SPI) RXBUFF Interrupt */
+#define AT91C_SPI_TXBUFE             ( 0x1 << 7 )    /* (SPI) TXBUFE Interrupt */
+#define AT91C_SPI_NSSR               ( 0x1 << 8 )    /* (SPI) NSSR Interrupt */
+#define AT91C_SPI_TXEMPTY            ( 0x1 << 9 )    /* (SPI) TXEMPTY Interrupt */
+#define AT91C_SPI_SPIENS             ( 0x1 << 16 )   /* (SPI) Enable Status */
+/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
+/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
+/* -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */
+/* -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */
+#define AT91C_SPI_CPOL           ( 0x1 << 0 )   /* (SPI) Clock Polarity */
+#define AT91C_SPI_NCPHA          ( 0x1 << 1 )   /* (SPI) Clock Phase */
+#define AT91C_SPI_CSAAT          ( 0x1 << 3 )   /* (SPI) Chip Select Active After Transfer */
+#define AT91C_SPI_BITS           ( 0xF << 4 )   /* (SPI) Bits Per Transfer */
+#define     AT91C_SPI_BITS_8     ( 0x0 << 4 )   /* (SPI) 8 Bits Per transfer */
+#define     AT91C_SPI_BITS_9     ( 0x1 << 4 )   /* (SPI) 9 Bits Per transfer */
+#define     AT91C_SPI_BITS_10    ( 0x2 << 4 )   /* (SPI) 10 Bits Per transfer */
+#define     AT91C_SPI_BITS_11    ( 0x3 << 4 )   /* (SPI) 11 Bits Per transfer */
+#define     AT91C_SPI_BITS_12    ( 0x4 << 4 )   /* (SPI) 12 Bits Per transfer */
+#define     AT91C_SPI_BITS_13    ( 0x5 << 4 )   /* (SPI) 13 Bits Per transfer */
+#define     AT91C_SPI_BITS_14    ( 0x6 << 4 )   /* (SPI) 14 Bits Per transfer */
+#define     AT91C_SPI_BITS_15    ( 0x7 << 4 )   /* (SPI) 15 Bits Per transfer */
+#define     AT91C_SPI_BITS_16    ( 0x8 << 4 )   /* (SPI) 16 Bits Per transfer */
+#define AT91C_SPI_SCBR           ( 0xFF << 8 )  /* (SPI) Serial Clock Baud Rate */
+#define AT91C_SPI_DLYBS          ( 0xFF << 16 ) /* (SPI) Delay Before SPCK */
+#define AT91C_SPI_DLYBCT         ( 0xFF << 24 ) /* (SPI) Delay Between Consecutive Transfers */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Usart
-// *****************************************************************************
-// *** Register offset in AT91S_USART structure ***
-#define US_CR           ( 0) // Control Register
-#define US_MR           ( 4) // Mode Register
-#define US_IER          ( 8) // Interrupt Enable Register
-#define US_IDR          (12) // Interrupt Disable Register
-#define US_IMR          (16) // Interrupt Mask Register
-#define US_CSR          (20) // Channel Status Register
-#define US_RHR          (24) // Receiver Holding Register
-#define US_THR          (28) // Transmitter Holding Register
-#define US_BRGR         (32) // Baud Rate Generator Register
-#define US_RTOR         (36) // Receiver Time-out Register
-#define US_TTGR         (40) // Transmitter Time-guard Register
-#define US_FIDI         (64) // FI_DI_Ratio Register
-#define US_NER          (68) // Nb Errors Register
-#define US_IF           (76) // IRDA_FILTER Register
-#define US_RPR          (256) // Receive Pointer Register
-#define US_RCR          (260) // Receive Counter Register
-#define US_TPR          (264) // Transmit Pointer Register
-#define US_TCR          (268) // Transmit Counter Register
-#define US_RNPR         (272) // Receive Next Pointer Register
-#define US_RNCR         (276) // Receive Next Counter Register
-#define US_TNPR         (280) // Transmit Next Pointer Register
-#define US_TNCR         (284) // Transmit Next Counter Register
-#define US_PTCR         (288) // PDC Transfer Control Register
-#define US_PTSR         (292) // PDC Transfer Status Register
-// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
-#define AT91C_US_STTBRK           (0x1 <<  9) // (USART) Start Break
-#define AT91C_US_STPBRK           (0x1 << 10) // (USART) Stop Break
-#define AT91C_US_STTTO            (0x1 << 11) // (USART) Start Time-out
-#define AT91C_US_SENDA            (0x1 << 12) // (USART) Send Address
-#define AT91C_US_RSTIT            (0x1 << 13) // (USART) Reset Iterations
-#define AT91C_US_RSTNACK          (0x1 << 14) // (USART) Reset Non Acknowledge
-#define AT91C_US_RETTO            (0x1 << 15) // (USART) Rearm Time-out
-#define AT91C_US_DTREN            (0x1 << 16) // (USART) Data Terminal ready Enable
-#define AT91C_US_DTRDIS           (0x1 << 17) // (USART) Data Terminal ready Disable
-#define AT91C_US_RTSEN            (0x1 << 18) // (USART) Request to Send enable
-#define AT91C_US_RTSDIS           (0x1 << 19) // (USART) Request to Send Disable
-// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
-#define AT91C_US_USMODE           (0xF <<  0) // (USART) Usart mode
-#define     AT91C_US_USMODE_NORMAL               (0x0) // (USART) Normal
-#define     AT91C_US_USMODE_RS485                (0x1) // (USART) RS485
-#define     AT91C_US_USMODE_HWHSH                (0x2) // (USART) Hardware Handshaking
-#define     AT91C_US_USMODE_MODEM                (0x3) // (USART) Modem
-#define     AT91C_US_USMODE_ISO7816_0            (0x4) // (USART) ISO7816 protocol: T = 0
-#define     AT91C_US_USMODE_ISO7816_1            (0x6) // (USART) ISO7816 protocol: T = 1
-#define     AT91C_US_USMODE_IRDA                 (0x8) // (USART) IrDA
-#define     AT91C_US_USMODE_SWHSH                (0xC) // (USART) Software Handshaking
-#define AT91C_US_CLKS             (0x3 <<  4) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define     AT91C_US_CLKS_CLOCK                (0x0 <<  4) // (USART) Clock
-#define     AT91C_US_CLKS_FDIV1                (0x1 <<  4) // (USART) fdiv1
-#define     AT91C_US_CLKS_SLOW                 (0x2 <<  4) // (USART) slow_clock (ARM)
-#define     AT91C_US_CLKS_EXT                  (0x3 <<  4) // (USART) External (SCK)
-#define AT91C_US_CHRL             (0x3 <<  6) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define     AT91C_US_CHRL_5_BITS               (0x0 <<  6) // (USART) Character Length: 5 bits
-#define     AT91C_US_CHRL_6_BITS               (0x1 <<  6) // (USART) Character Length: 6 bits
-#define     AT91C_US_CHRL_7_BITS               (0x2 <<  6) // (USART) Character Length: 7 bits
-#define     AT91C_US_CHRL_8_BITS               (0x3 <<  6) // (USART) Character Length: 8 bits
-#define AT91C_US_SYNC             (0x1 <<  8) // (USART) Synchronous Mode Select
-#define AT91C_US_NBSTOP           (0x3 << 12) // (USART) Number of Stop bits
-#define     AT91C_US_NBSTOP_1_BIT                (0x0 << 12) // (USART) 1 stop bit
-#define     AT91C_US_NBSTOP_15_BIT               (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
-#define     AT91C_US_NBSTOP_2_BIT                (0x2 << 12) // (USART) 2 stop bits
-#define AT91C_US_MSBF             (0x1 << 16) // (USART) Bit Order
-#define AT91C_US_MODE9            (0x1 << 17) // (USART) 9-bit Character length
-#define AT91C_US_CKLO             (0x1 << 18) // (USART) Clock Output Select
-#define AT91C_US_OVER             (0x1 << 19) // (USART) Over Sampling Mode
-#define AT91C_US_INACK            (0x1 << 20) // (USART) Inhibit Non Acknowledge
-#define AT91C_US_DSNACK           (0x1 << 21) // (USART) Disable Successive NACK
-#define AT91C_US_MAX_ITER         (0x1 << 24) // (USART) Number of Repetitions
-#define AT91C_US_FILTER           (0x1 << 28) // (USART) Receive Line Filter
-// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
-#define AT91C_US_RXBRK            (0x1 <<  2) // (USART) Break Received/End of Break
-#define AT91C_US_TIMEOUT          (0x1 <<  8) // (USART) Receiver Time-out
-#define AT91C_US_ITERATION        (0x1 << 10) // (USART) Max number of Repetitions Reached
-#define AT91C_US_NACK             (0x1 << 13) // (USART) Non Acknowledge
-#define AT91C_US_RIIC             (0x1 << 16) // (USART) Ring INdicator Input Change Flag
-#define AT91C_US_DSRIC            (0x1 << 17) // (USART) Data Set Ready Input Change Flag
-#define AT91C_US_DCDIC            (0x1 << 18) // (USART) Data Carrier Flag
-#define AT91C_US_CTSIC            (0x1 << 19) // (USART) Clear To Send Input Change Flag
-// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
-// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
-// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
-#define AT91C_US_RI               (0x1 << 20) // (USART) Image of RI Input
-#define AT91C_US_DSR              (0x1 << 21) // (USART) Image of DSR Input
-#define AT91C_US_DCD              (0x1 << 22) // (USART) Image of DCD Input
-#define AT91C_US_CTS              (0x1 << 23) // (USART) Image of CTS Input
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Usart */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_USART structure *** */
+#define US_CR                            ( 0 )         /* Control Register */
+#define US_MR                            ( 4 )         /* Mode Register */
+#define US_IER                           ( 8 )         /* Interrupt Enable Register */
+#define US_IDR                           ( 12 )        /* Interrupt Disable Register */
+#define US_IMR                           ( 16 )        /* Interrupt Mask Register */
+#define US_CSR                           ( 20 )        /* Channel Status Register */
+#define US_RHR                           ( 24 )        /* Receiver Holding Register */
+#define US_THR                           ( 28 )        /* Transmitter Holding Register */
+#define US_BRGR                          ( 32 )        /* Baud Rate Generator Register */
+#define US_RTOR                          ( 36 )        /* Receiver Time-out Register */
+#define US_TTGR                          ( 40 )        /* Transmitter Time-guard Register */
+#define US_FIDI                          ( 64 )        /* FI_DI_Ratio Register */
+#define US_NER                           ( 68 )        /* Nb Errors Register */
+#define US_IF                            ( 76 )        /* IRDA_FILTER Register */
+#define US_RPR                           ( 256 )       /* Receive Pointer Register */
+#define US_RCR                           ( 260 )       /* Receive Counter Register */
+#define US_TPR                           ( 264 )       /* Transmit Pointer Register */
+#define US_TCR                           ( 268 )       /* Transmit Counter Register */
+#define US_RNPR                          ( 272 )       /* Receive Next Pointer Register */
+#define US_RNCR                          ( 276 )       /* Receive Next Counter Register */
+#define US_TNPR                          ( 280 )       /* Transmit Next Pointer Register */
+#define US_TNCR                          ( 284 )       /* Transmit Next Counter Register */
+#define US_PTCR                          ( 288 )       /* PDC Transfer Control Register */
+#define US_PTSR                          ( 292 )       /* PDC Transfer Status Register */
+/* -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- */
+#define AT91C_US_STTBRK                  ( 0x1 << 9 )  /* (USART) Start Break */
+#define AT91C_US_STPBRK                  ( 0x1 << 10 ) /* (USART) Stop Break */
+#define AT91C_US_STTTO                   ( 0x1 << 11 ) /* (USART) Start Time-out */
+#define AT91C_US_SENDA                   ( 0x1 << 12 ) /* (USART) Send Address */
+#define AT91C_US_RSTIT                   ( 0x1 << 13 ) /* (USART) Reset Iterations */
+#define AT91C_US_RSTNACK                 ( 0x1 << 14 ) /* (USART) Reset Non Acknowledge */
+#define AT91C_US_RETTO                   ( 0x1 << 15 ) /* (USART) Rearm Time-out */
+#define AT91C_US_DTREN                   ( 0x1 << 16 ) /* (USART) Data Terminal ready Enable */
+#define AT91C_US_DTRDIS                  ( 0x1 << 17 ) /* (USART) Data Terminal ready Disable */
+#define AT91C_US_RTSEN                   ( 0x1 << 18 ) /* (USART) Request to Send enable */
+#define AT91C_US_RTSDIS                  ( 0x1 << 19 ) /* (USART) Request to Send Disable */
+/* -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- */
+#define AT91C_US_USMODE                  ( 0xF << 0 )  /* (USART) Usart mode */
+#define     AT91C_US_USMODE_NORMAL       ( 0x0 )       /* (USART) Normal */
+#define     AT91C_US_USMODE_RS485        ( 0x1 )       /* (USART) RS485 */
+#define     AT91C_US_USMODE_HWHSH        ( 0x2 )       /* (USART) Hardware Handshaking */
+#define     AT91C_US_USMODE_MODEM        ( 0x3 )       /* (USART) Modem */
+#define     AT91C_US_USMODE_ISO7816_0    ( 0x4 )       /* (USART) ISO7816 protocol: T = 0 */
+#define     AT91C_US_USMODE_ISO7816_1    ( 0x6 )       /* (USART) ISO7816 protocol: T = 1 */
+#define     AT91C_US_USMODE_IRDA         ( 0x8 )       /* (USART) IrDA */
+#define     AT91C_US_USMODE_SWHSH        ( 0xC )       /* (USART) Software Handshaking */
+#define AT91C_US_CLKS                    ( 0x3 << 4 )  /* (USART) Clock Selection (Baud Rate generator Input Clock */
+#define     AT91C_US_CLKS_CLOCK          ( 0x0 << 4 )  /* (USART) Clock */
+#define     AT91C_US_CLKS_FDIV1          ( 0x1 << 4 )  /* (USART) fdiv1 */
+#define     AT91C_US_CLKS_SLOW           ( 0x2 << 4 )  /* (USART) slow_clock (ARM) */
+#define     AT91C_US_CLKS_EXT            ( 0x3 << 4 )  /* (USART) External (SCK) */
+#define AT91C_US_CHRL                    ( 0x3 << 6 )  /* (USART) Clock Selection (Baud Rate generator Input Clock */
+#define     AT91C_US_CHRL_5_BITS         ( 0x0 << 6 )  /* (USART) Character Length: 5 bits */
+#define     AT91C_US_CHRL_6_BITS         ( 0x1 << 6 )  /* (USART) Character Length: 6 bits */
+#define     AT91C_US_CHRL_7_BITS         ( 0x2 << 6 )  /* (USART) Character Length: 7 bits */
+#define     AT91C_US_CHRL_8_BITS         ( 0x3 << 6 )  /* (USART) Character Length: 8 bits */
+#define AT91C_US_SYNC                    ( 0x1 << 8 )  /* (USART) Synchronous Mode Select */
+#define AT91C_US_NBSTOP                  ( 0x3 << 12 ) /* (USART) Number of Stop bits */
+#define     AT91C_US_NBSTOP_1_BIT        ( 0x0 << 12 ) /* (USART) 1 stop bit */
+#define     AT91C_US_NBSTOP_15_BIT       ( 0x1 << 12 ) /* (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits */
+#define     AT91C_US_NBSTOP_2_BIT        ( 0x2 << 12 ) /* (USART) 2 stop bits */
+#define AT91C_US_MSBF                    ( 0x1 << 16 ) /* (USART) Bit Order */
+#define AT91C_US_MODE9                   ( 0x1 << 17 ) /* (USART) 9-bit Character length */
+#define AT91C_US_CKLO                    ( 0x1 << 18 ) /* (USART) Clock Output Select */
+#define AT91C_US_OVER                    ( 0x1 << 19 ) /* (USART) Over Sampling Mode */
+#define AT91C_US_INACK                   ( 0x1 << 20 ) /* (USART) Inhibit Non Acknowledge */
+#define AT91C_US_DSNACK                  ( 0x1 << 21 ) /* (USART) Disable Successive NACK */
+#define AT91C_US_MAX_ITER                ( 0x1 << 24 ) /* (USART) Number of Repetitions */
+#define AT91C_US_FILTER                  ( 0x1 << 28 ) /* (USART) Receive Line Filter */
+/* -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- */
+#define AT91C_US_RXBRK                   ( 0x1 << 2 )  /* (USART) Break Received/End of Break */
+#define AT91C_US_TIMEOUT                 ( 0x1 << 8 )  /* (USART) Receiver Time-out */
+#define AT91C_US_ITERATION               ( 0x1 << 10 ) /* (USART) Max number of Repetitions Reached */
+#define AT91C_US_NACK                    ( 0x1 << 13 ) /* (USART) Non Acknowledge */
+#define AT91C_US_RIIC                    ( 0x1 << 16 ) /* (USART) Ring INdicator Input Change Flag */
+#define AT91C_US_DSRIC                   ( 0x1 << 17 ) /* (USART) Data Set Ready Input Change Flag */
+#define AT91C_US_DCDIC                   ( 0x1 << 18 ) /* (USART) Data Carrier Flag */
+#define AT91C_US_CTSIC                   ( 0x1 << 19 ) /* (USART) Clear To Send Input Change Flag */
+/* -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- */
+/* -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- */
+/* -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- */
+#define AT91C_US_RI     ( 0x1 << 20 )         /* (USART) Image of RI Input */
+#define AT91C_US_DSR    ( 0x1 << 21 )         /* (USART) Image of DSR Input */
+#define AT91C_US_DCD    ( 0x1 << 22 )         /* (USART) Image of DCD Input */
+#define AT91C_US_CTS    ( 0x1 << 23 )         /* (USART) Image of CTS Input */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
-// *****************************************************************************
-// *** Register offset in AT91S_SSC structure ***
-#define SSC_CR          ( 0) // Control Register
-#define SSC_CMR         ( 4) // Clock Mode Register
-#define SSC_RCMR        (16) // Receive Clock ModeRegister
-#define SSC_RFMR        (20) // Receive Frame Mode Register
-#define SSC_TCMR        (24) // Transmit Clock Mode Register
-#define SSC_TFMR        (28) // Transmit Frame Mode Register
-#define SSC_RHR         (32) // Receive Holding Register
-#define SSC_THR         (36) // Transmit Holding Register
-#define SSC_RSHR        (48) // Receive Sync Holding Register
-#define SSC_TSHR        (52) // Transmit Sync Holding Register
-#define SSC_SR          (64) // Status Register
-#define SSC_IER         (68) // Interrupt Enable Register
-#define SSC_IDR         (72) // Interrupt Disable Register
-#define SSC_IMR         (76) // Interrupt Mask Register
-#define SSC_RPR         (256) // Receive Pointer Register
-#define SSC_RCR         (260) // Receive Counter Register
-#define SSC_TPR         (264) // Transmit Pointer Register
-#define SSC_TCR         (268) // Transmit Counter Register
-#define SSC_RNPR        (272) // Receive Next Pointer Register
-#define SSC_RNCR        (276) // Receive Next Counter Register
-#define SSC_TNPR        (280) // Transmit Next Pointer Register
-#define SSC_TNCR        (284) // Transmit Next Counter Register
-#define SSC_PTCR        (288) // PDC Transfer Control Register
-#define SSC_PTSR        (292) // PDC Transfer Status Register
-// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
-#define AT91C_SSC_RXEN            (0x1 <<  0) // (SSC) Receive Enable
-#define AT91C_SSC_RXDIS           (0x1 <<  1) // (SSC) Receive Disable
-#define AT91C_SSC_TXEN            (0x1 <<  8) // (SSC) Transmit Enable
-#define AT91C_SSC_TXDIS           (0x1 <<  9) // (SSC) Transmit Disable
-#define AT91C_SSC_SWRST           (0x1 << 15) // (SSC) Software Reset
-// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
-#define AT91C_SSC_CKS             (0x3 <<  0) // (SSC) Receive/Transmit Clock Selection
-#define     AT91C_SSC_CKS_DIV                  (0x0) // (SSC) Divided Clock
-#define     AT91C_SSC_CKS_TK                   (0x1) // (SSC) TK Clock signal
-#define     AT91C_SSC_CKS_RK                   (0x2) // (SSC) RK pin
-#define AT91C_SSC_CKO             (0x7 <<  2) // (SSC) Receive/Transmit Clock Output Mode Selection
-#define     AT91C_SSC_CKO_NONE                 (0x0 <<  2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
-#define     AT91C_SSC_CKO_CONTINOUS            (0x1 <<  2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
-#define     AT91C_SSC_CKO_DATA_TX              (0x2 <<  2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
-#define AT91C_SSC_CKI             (0x1 <<  5) // (SSC) Receive/Transmit Clock Inversion
-#define AT91C_SSC_START           (0xF <<  8) // (SSC) Receive/Transmit Start Selection
-#define     AT91C_SSC_START_CONTINOUS            (0x0 <<  8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
-#define     AT91C_SSC_START_TX                   (0x1 <<  8) // (SSC) Transmit/Receive start
-#define     AT91C_SSC_START_LOW_RF               (0x2 <<  8) // (SSC) Detection of a low level on RF input
-#define     AT91C_SSC_START_HIGH_RF              (0x3 <<  8) // (SSC) Detection of a high level on RF input
-#define     AT91C_SSC_START_FALL_RF              (0x4 <<  8) // (SSC) Detection of a falling edge on RF input
-#define     AT91C_SSC_START_RISE_RF              (0x5 <<  8) // (SSC) Detection of a rising edge on RF input
-#define     AT91C_SSC_START_LEVEL_RF             (0x6 <<  8) // (SSC) Detection of any level change on RF input
-#define     AT91C_SSC_START_EDGE_RF              (0x7 <<  8) // (SSC) Detection of any edge on RF input
-#define     AT91C_SSC_START_0                    (0x8 <<  8) // (SSC) Compare 0
-#define AT91C_SSC_STTDLY          (0xFF << 16) // (SSC) Receive/Transmit Start Delay
-#define AT91C_SSC_PERIOD          (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
-// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
-#define AT91C_SSC_DATLEN          (0x1F <<  0) // (SSC) Data Length
-#define AT91C_SSC_LOOP            (0x1 <<  5) // (SSC) Loop Mode
-#define AT91C_SSC_MSBF            (0x1 <<  7) // (SSC) Most Significant Bit First
-#define AT91C_SSC_DATNB           (0xF <<  8) // (SSC) Data Number per Frame
-#define AT91C_SSC_FSLEN           (0xF << 16) // (SSC) Receive/Transmit Frame Sync length
-#define AT91C_SSC_FSOS            (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
-#define     AT91C_SSC_FSOS_NONE                 (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
-#define     AT91C_SSC_FSOS_NEGATIVE             (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
-#define     AT91C_SSC_FSOS_POSITIVE             (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
-#define     AT91C_SSC_FSOS_LOW                  (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
-#define     AT91C_SSC_FSOS_HIGH                 (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
-#define     AT91C_SSC_FSOS_TOGGLE               (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
-#define AT91C_SSC_FSEDGE          (0x1 << 24) // (SSC) Frame Sync Edge Detection
-// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
-// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
-#define AT91C_SSC_DATDEF          (0x1 <<  5) // (SSC) Data Default Value
-#define AT91C_SSC_FSDEN           (0x1 << 23) // (SSC) Frame Sync Data Enable
-// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
-#define AT91C_SSC_TXRDY           (0x1 <<  0) // (SSC) Transmit Ready
-#define AT91C_SSC_TXEMPTY         (0x1 <<  1) // (SSC) Transmit Empty
-#define AT91C_SSC_ENDTX           (0x1 <<  2) // (SSC) End Of Transmission
-#define AT91C_SSC_TXBUFE          (0x1 <<  3) // (SSC) Transmit Buffer Empty
-#define AT91C_SSC_RXRDY           (0x1 <<  4) // (SSC) Receive Ready
-#define AT91C_SSC_OVRUN           (0x1 <<  5) // (SSC) Receive Overrun
-#define AT91C_SSC_ENDRX           (0x1 <<  6) // (SSC) End of Reception
-#define AT91C_SSC_RXBUFF          (0x1 <<  7) // (SSC) Receive Buffer Full
-#define AT91C_SSC_TXSYN           (0x1 << 10) // (SSC) Transmit Sync
-#define AT91C_SSC_RXSYN           (0x1 << 11) // (SSC) Receive Sync
-#define AT91C_SSC_TXENA           (0x1 << 16) // (SSC) Transmit Enable
-#define AT91C_SSC_RXENA           (0x1 << 17) // (SSC) Receive Enable
-// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
-// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
-// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_SSC structure *** */
+#define SSC_CR                            ( 0 )          /* Control Register */
+#define SSC_CMR                           ( 4 )          /* Clock Mode Register */
+#define SSC_RCMR                          ( 16 )         /* Receive Clock ModeRegister */
+#define SSC_RFMR                          ( 20 )         /* Receive Frame Mode Register */
+#define SSC_TCMR                          ( 24 )         /* Transmit Clock Mode Register */
+#define SSC_TFMR                          ( 28 )         /* Transmit Frame Mode Register */
+#define SSC_RHR                           ( 32 )         /* Receive Holding Register */
+#define SSC_THR                           ( 36 )         /* Transmit Holding Register */
+#define SSC_RSHR                          ( 48 )         /* Receive Sync Holding Register */
+#define SSC_TSHR                          ( 52 )         /* Transmit Sync Holding Register */
+#define SSC_SR                            ( 64 )         /* Status Register */
+#define SSC_IER                           ( 68 )         /* Interrupt Enable Register */
+#define SSC_IDR                           ( 72 )         /* Interrupt Disable Register */
+#define SSC_IMR                           ( 76 )         /* Interrupt Mask Register */
+#define SSC_RPR                           ( 256 )        /* Receive Pointer Register */
+#define SSC_RCR                           ( 260 )        /* Receive Counter Register */
+#define SSC_TPR                           ( 264 )        /* Transmit Pointer Register */
+#define SSC_TCR                           ( 268 )        /* Transmit Counter Register */
+#define SSC_RNPR                          ( 272 )        /* Receive Next Pointer Register */
+#define SSC_RNCR                          ( 276 )        /* Receive Next Counter Register */
+#define SSC_TNPR                          ( 280 )        /* Transmit Next Pointer Register */
+#define SSC_TNCR                          ( 284 )        /* Transmit Next Counter Register */
+#define SSC_PTCR                          ( 288 )        /* PDC Transfer Control Register */
+#define SSC_PTSR                          ( 292 )        /* PDC Transfer Status Register */
+/* -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- */
+#define AT91C_SSC_RXEN                    ( 0x1 << 0 )   /* (SSC) Receive Enable */
+#define AT91C_SSC_RXDIS                   ( 0x1 << 1 )   /* (SSC) Receive Disable */
+#define AT91C_SSC_TXEN                    ( 0x1 << 8 )   /* (SSC) Transmit Enable */
+#define AT91C_SSC_TXDIS                   ( 0x1 << 9 )   /* (SSC) Transmit Disable */
+#define AT91C_SSC_SWRST                   ( 0x1 << 15 )  /* (SSC) Software Reset */
+/* -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- */
+#define AT91C_SSC_CKS                     ( 0x3 << 0 )   /* (SSC) Receive/Transmit Clock Selection */
+#define     AT91C_SSC_CKS_DIV             ( 0x0 )        /* (SSC) Divided Clock */
+#define     AT91C_SSC_CKS_TK              ( 0x1 )        /* (SSC) TK Clock signal */
+#define     AT91C_SSC_CKS_RK              ( 0x2 )        /* (SSC) RK pin */
+#define AT91C_SSC_CKO                     ( 0x7 << 2 )   /* (SSC) Receive/Transmit Clock Output Mode Selection */
+#define     AT91C_SSC_CKO_NONE            ( 0x0 << 2 )   /* (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only */
+#define     AT91C_SSC_CKO_CONTINUOUS      ( 0x1 << 2 )   /* (SSC) Continuous Receive/Transmit Clock RK pin: Output */
+#define     AT91C_SSC_CKO_DATA_TX         ( 0x2 << 2 )   /* (SSC) Receive/Transmit Clock only during data transfers RK pin: Output */
+#define AT91C_SSC_CKI                     ( 0x1 << 5 )   /* (SSC) Receive/Transmit Clock Inversion */
+#define AT91C_SSC_START                   ( 0xF << 8 )   /* (SSC) Receive/Transmit Start Selection */
+#define     AT91C_SSC_START_CONTINUOUS    ( 0x0 << 8 )   /* (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */
+#define     AT91C_SSC_START_TX            ( 0x1 << 8 )   /* (SSC) Transmit/Receive start */
+#define     AT91C_SSC_START_LOW_RF        ( 0x2 << 8 )   /* (SSC) Detection of a low level on RF input */
+#define     AT91C_SSC_START_HIGH_RF       ( 0x3 << 8 )   /* (SSC) Detection of a high level on RF input */
+#define     AT91C_SSC_START_FALL_RF       ( 0x4 << 8 )   /* (SSC) Detection of a falling edge on RF input */
+#define     AT91C_SSC_START_RISE_RF       ( 0x5 << 8 )   /* (SSC) Detection of a rising edge on RF input */
+#define     AT91C_SSC_START_LEVEL_RF      ( 0x6 << 8 )   /* (SSC) Detection of any level change on RF input */
+#define     AT91C_SSC_START_EDGE_RF       ( 0x7 << 8 )   /* (SSC) Detection of any edge on RF input */
+#define     AT91C_SSC_START_0             ( 0x8 << 8 )   /* (SSC) Compare 0 */
+#define AT91C_SSC_STTDLY                  ( 0xFF << 16 ) /* (SSC) Receive/Transmit Start Delay */
+#define AT91C_SSC_PERIOD                  ( 0xFF << 24 ) /* (SSC) Receive/Transmit Period Divider Selection */
+/* -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- */
+#define AT91C_SSC_DATLEN                  ( 0x1F << 0 )  /* (SSC) Data Length */
+#define AT91C_SSC_LOOP                    ( 0x1 << 5 )   /* (SSC) Loop Mode */
+#define AT91C_SSC_MSBF                    ( 0x1 << 7 )   /* (SSC) Most Significant Bit First */
+#define AT91C_SSC_DATNB                   ( 0xF << 8 )   /* (SSC) Data Number per Frame */
+#define AT91C_SSC_FSLEN                   ( 0xF << 16 )  /* (SSC) Receive/Transmit Frame Sync length */
+#define AT91C_SSC_FSOS                    ( 0x7 << 20 )  /* (SSC) Receive/Transmit Frame Sync Output Selection */
+#define     AT91C_SSC_FSOS_NONE           ( 0x0 << 20 )  /* (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only */
+#define     AT91C_SSC_FSOS_NEGATIVE       ( 0x1 << 20 )  /* (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse */
+#define     AT91C_SSC_FSOS_POSITIVE       ( 0x2 << 20 )  /* (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse */
+#define     AT91C_SSC_FSOS_LOW            ( 0x3 << 20 )  /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer */
+#define     AT91C_SSC_FSOS_HIGH           ( 0x4 << 20 )  /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer */
+#define     AT91C_SSC_FSOS_TOGGLE         ( 0x5 << 20 )  /* (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer */
+#define AT91C_SSC_FSEDGE                  ( 0x1 << 24 )  /* (SSC) Frame Sync Edge Detection */
+/* -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- */
+/* -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- */
+#define AT91C_SSC_DATDEF                  ( 0x1 << 5 )  /* (SSC) Data Default Value */
+#define AT91C_SSC_FSDEN                   ( 0x1 << 23 ) /* (SSC) Frame Sync Data Enable */
+/* -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- */
+#define AT91C_SSC_TXRDY                   ( 0x1 << 0 )  /* (SSC) Transmit Ready */
+#define AT91C_SSC_TXEMPTY                 ( 0x1 << 1 )  /* (SSC) Transmit Empty */
+#define AT91C_SSC_ENDTX                   ( 0x1 << 2 )  /* (SSC) End Of Transmission */
+#define AT91C_SSC_TXBUFE                  ( 0x1 << 3 )  /* (SSC) Transmit Buffer Empty */
+#define AT91C_SSC_RXRDY                   ( 0x1 << 4 )  /* (SSC) Receive Ready */
+#define AT91C_SSC_OVRUN                   ( 0x1 << 5 )  /* (SSC) Receive Overrun */
+#define AT91C_SSC_ENDRX                   ( 0x1 << 6 )  /* (SSC) End of Reception */
+#define AT91C_SSC_RXBUFF                  ( 0x1 << 7 )  /* (SSC) Receive Buffer Full */
+#define AT91C_SSC_TXSYN                   ( 0x1 << 10 ) /* (SSC) Transmit Sync */
+#define AT91C_SSC_RXSYN                   ( 0x1 << 11 ) /* (SSC) Receive Sync */
+#define AT91C_SSC_TXENA                   ( 0x1 << 16 ) /* (SSC) Transmit Enable */
+#define AT91C_SSC_RXENA                   ( 0x1 << 17 ) /* (SSC) Receive Enable */
+/* -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- */
+/* -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- */
+/* -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Two-wire Interface
-// *****************************************************************************
-// *** Register offset in AT91S_TWI structure ***
-#define TWI_CR          ( 0) // Control Register
-#define TWI_MMR         ( 4) // Master Mode Register
-#define TWI_IADR        (12) // Internal Address Register
-#define TWI_CWGR        (16) // Clock Waveform Generator Register
-#define TWI_SR          (32) // Status Register
-#define TWI_IER         (36) // Interrupt Enable Register
-#define TWI_IDR         (40) // Interrupt Disable Register
-#define TWI_IMR         (44) // Interrupt Mask Register
-#define TWI_RHR         (48) // Receive Holding Register
-#define TWI_THR         (52) // Transmit Holding Register
-// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
-#define AT91C_TWI_START           (0x1 <<  0) // (TWI) Send a START Condition
-#define AT91C_TWI_STOP            (0x1 <<  1) // (TWI) Send a STOP Condition
-#define AT91C_TWI_MSEN            (0x1 <<  2) // (TWI) TWI Master Transfer Enabled
-#define AT91C_TWI_MSDIS           (0x1 <<  3) // (TWI) TWI Master Transfer Disabled
-#define AT91C_TWI_SWRST           (0x1 <<  7) // (TWI) Software Reset
-// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
-#define AT91C_TWI_IADRSZ          (0x3 <<  8) // (TWI) Internal Device Address Size
-#define     AT91C_TWI_IADRSZ_NO                   (0x0 <<  8) // (TWI) No internal device address
-#define     AT91C_TWI_IADRSZ_1_BYTE               (0x1 <<  8) // (TWI) One-byte internal device address
-#define     AT91C_TWI_IADRSZ_2_BYTE               (0x2 <<  8) // (TWI) Two-byte internal device address
-#define     AT91C_TWI_IADRSZ_3_BYTE               (0x3 <<  8) // (TWI) Three-byte internal device address
-#define AT91C_TWI_MREAD           (0x1 << 12) // (TWI) Master Read Direction
-#define AT91C_TWI_DADR            (0x7F << 16) // (TWI) Device Address
-// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
-#define AT91C_TWI_CLDIV           (0xFF <<  0) // (TWI) Clock Low Divider
-#define AT91C_TWI_CHDIV           (0xFF <<  8) // (TWI) Clock High Divider
-#define AT91C_TWI_CKDIV           (0x7 << 16) // (TWI) Clock Divider
-// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
-#define AT91C_TWI_TXCOMP          (0x1 <<  0) // (TWI) Transmission Completed
-#define AT91C_TWI_RXRDY           (0x1 <<  1) // (TWI) Receive holding register ReaDY
-#define AT91C_TWI_TXRDY           (0x1 <<  2) // (TWI) Transmit holding register ReaDY
-#define AT91C_TWI_OVRE            (0x1 <<  6) // (TWI) Overrun Error
-#define AT91C_TWI_UNRE            (0x1 <<  7) // (TWI) Underrun Error
-#define AT91C_TWI_NACK            (0x1 <<  8) // (TWI) Not Acknowledged
-// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
-// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
-// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Two-wire Interface */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_TWI structure *** */
+#define TWI_CR                         ( 0 )          /* Control Register */
+#define TWI_MMR                        ( 4 )          /* Master Mode Register */
+#define TWI_IADR                       ( 12 )         /* Internal Address Register */
+#define TWI_CWGR                       ( 16 )         /* Clock Waveform Generator Register */
+#define TWI_SR                         ( 32 )         /* Status Register */
+#define TWI_IER                        ( 36 )         /* Interrupt Enable Register */
+#define TWI_IDR                        ( 40 )         /* Interrupt Disable Register */
+#define TWI_IMR                        ( 44 )         /* Interrupt Mask Register */
+#define TWI_RHR                        ( 48 )         /* Receive Holding Register */
+#define TWI_THR                        ( 52 )         /* Transmit Holding Register */
+/* -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- */
+#define AT91C_TWI_START                ( 0x1 << 0 )   /* (TWI) Send a START Condition */
+#define AT91C_TWI_STOP                 ( 0x1 << 1 )   /* (TWI) Send a STOP Condition */
+#define AT91C_TWI_MSEN                 ( 0x1 << 2 )   /* (TWI) TWI Master Transfer Enabled */
+#define AT91C_TWI_MSDIS                ( 0x1 << 3 )   /* (TWI) TWI Master Transfer Disabled */
+#define AT91C_TWI_SWRST                ( 0x1 << 7 )   /* (TWI) Software Reset */
+/* -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- */
+#define AT91C_TWI_IADRSZ               ( 0x3 << 8 )   /* (TWI) Internal Device Address Size */
+#define     AT91C_TWI_IADRSZ_NO        ( 0x0 << 8 )   /* (TWI) No internal device address */
+#define     AT91C_TWI_IADRSZ_1_BYTE    ( 0x1 << 8 )   /* (TWI) One-byte internal device address */
+#define     AT91C_TWI_IADRSZ_2_BYTE    ( 0x2 << 8 )   /* (TWI) Two-byte internal device address */
+#define     AT91C_TWI_IADRSZ_3_BYTE    ( 0x3 << 8 )   /* (TWI) Three-byte internal device address */
+#define AT91C_TWI_MREAD                ( 0x1 << 12 )  /* (TWI) Master Read Direction */
+#define AT91C_TWI_DADR                 ( 0x7F << 16 ) /* (TWI) Device Address */
+/* -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- */
+#define AT91C_TWI_CLDIV                ( 0xFF << 0 )  /* (TWI) Clock Low Divider */
+#define AT91C_TWI_CHDIV                ( 0xFF << 8 )  /* (TWI) Clock High Divider */
+#define AT91C_TWI_CKDIV                ( 0x7 << 16 )  /* (TWI) Clock Divider */
+/* -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- */
+#define AT91C_TWI_TXCOMP               ( 0x1 << 0 )   /* (TWI) Transmission Completed */
+#define AT91C_TWI_RXRDY                ( 0x1 << 1 )   /* (TWI) Receive holding register ReaDY */
+#define AT91C_TWI_TXRDY                ( 0x1 << 2 )   /* (TWI) Transmit holding register ReaDY */
+#define AT91C_TWI_OVRE                 ( 0x1 << 6 )   /* (TWI) Overrun Error */
+#define AT91C_TWI_UNRE                 ( 0x1 << 7 )   /* (TWI) Underrun Error */
+#define AT91C_TWI_NACK                 ( 0x1 << 8 )   /* (TWI) Not Acknowledged */
+/* -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- */
+/* -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- */
+/* -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR PWMC Channel Interface
-// *****************************************************************************
-// *** Register offset in AT91S_PWMC_CH structure ***
-#define PWMC_CMR        ( 0) // Channel Mode Register
-#define PWMC_CDTYR      ( 4) // Channel Duty Cycle Register
-#define PWMC_CPRDR      ( 8) // Channel Period Register
-#define PWMC_CCNTR      (12) // Channel Counter Register
-#define PWMC_CUPDR      (16) // Channel Update Register
-#define PWMC_Reserved   (20) // Reserved
-// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
-#define AT91C_PWMC_CPRE           (0xF <<  0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
-#define     AT91C_PWMC_CPRE_MCK                  (0x0) // (PWMC_CH)
-#define     AT91C_PWMC_CPRE_MCKA                 (0xB) // (PWMC_CH)
-#define     AT91C_PWMC_CPRE_MCKB                 (0xC) // (PWMC_CH)
-#define AT91C_PWMC_CALG           (0x1 <<  8) // (PWMC_CH) Channel Alignment
-#define AT91C_PWMC_CPOL           (0x1 <<  9) // (PWMC_CH) Channel Polarity
-#define AT91C_PWMC_CPD            (0x1 << 10) // (PWMC_CH) Channel Update Period
-// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
-#define AT91C_PWMC_CDTY           (0x0 <<  0) // (PWMC_CH) Channel Duty Cycle
-// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
-#define AT91C_PWMC_CPRD           (0x0 <<  0) // (PWMC_CH) Channel Period
-// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
-#define AT91C_PWMC_CCNT           (0x0 <<  0) // (PWMC_CH) Channel Counter
-// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
-#define AT91C_PWMC_CUPD           (0x0 <<  0) // (PWMC_CH) Channel Update
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR PWMC Channel Interface */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_PWMC_CH structure *** */
+#define PWMC_CMR                    ( 0 )         /* Channel Mode Register */
+#define PWMC_CDTYR                  ( 4 )         /* Channel Duty Cycle Register */
+#define PWMC_CPRDR                  ( 8 )         /* Channel Period Register */
+#define PWMC_CCNTR                  ( 12 )        /* Channel Counter Register */
+#define PWMC_CUPDR                  ( 16 )        /* Channel Update Register */
+#define PWMC_Reserved               ( 20 )        /* Reserved */
+/* -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- */
+#define AT91C_PWMC_CPRE             ( 0xF << 0 )  /* (PWMC_CH) Channel Pre-scaler : PWMC_CLKx */
+#define     AT91C_PWMC_CPRE_MCK     ( 0x0 )       /* (PWMC_CH) */
+#define     AT91C_PWMC_CPRE_MCKA    ( 0xB )       /* (PWMC_CH) */
+#define     AT91C_PWMC_CPRE_MCKB    ( 0xC )       /* (PWMC_CH) */
+#define AT91C_PWMC_CALG             ( 0x1 << 8 )  /* (PWMC_CH) Channel Alignment */
+#define AT91C_PWMC_CPOL             ( 0x1 << 9 )  /* (PWMC_CH) Channel Polarity */
+#define AT91C_PWMC_CPD              ( 0x1 << 10 ) /* (PWMC_CH) Channel Update Period */
+/* -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- */
+#define AT91C_PWMC_CDTY             ( 0x0 << 0 )  /* (PWMC_CH) Channel Duty Cycle */
+/* -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- */
+#define AT91C_PWMC_CPRD             ( 0x0 << 0 )  /* (PWMC_CH) Channel Period */
+/* -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- */
+#define AT91C_PWMC_CCNT             ( 0x0 << 0 )  /* (PWMC_CH) Channel Counter */
+/* -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- */
+#define AT91C_PWMC_CUPD             ( 0x0 << 0 )  /* (PWMC_CH) Channel Update */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface
-// *****************************************************************************
-// *** Register offset in AT91S_PWMC structure ***
-#define PWMC_MR         ( 0) // PWMC Mode Register
-#define PWMC_ENA        ( 4) // PWMC Enable Register
-#define PWMC_DIS        ( 8) // PWMC Disable Register
-#define PWMC_SR         (12) // PWMC Status Register
-#define PWMC_IER        (16) // PWMC Interrupt Enable Register
-#define PWMC_IDR        (20) // PWMC Interrupt Disable Register
-#define PWMC_IMR        (24) // PWMC Interrupt Mask Register
-#define PWMC_ISR        (28) // PWMC Interrupt Status Register
-#define PWMC_VR         (252) // PWMC Version Register
-#define PWMC_CH         (512) // PWMC Channel
-// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
-#define AT91C_PWMC_DIVA           (0xFF <<  0) // (PWMC) CLKA divide factor.
-#define AT91C_PWMC_PREA           (0xF <<  8) // (PWMC) Divider Input Clock Prescaler A
-#define     AT91C_PWMC_PREA_MCK                  (0x0 <<  8) // (PWMC)
-#define AT91C_PWMC_DIVB           (0xFF << 16) // (PWMC) CLKB divide factor.
-#define AT91C_PWMC_PREB           (0xF << 24) // (PWMC) Divider Input Clock Prescaler B
-#define     AT91C_PWMC_PREB_MCK                  (0x0 << 24) // (PWMC)
-// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
-#define AT91C_PWMC_CHID0          (0x1 <<  0) // (PWMC) Channel ID 0
-#define AT91C_PWMC_CHID1          (0x1 <<  1) // (PWMC) Channel ID 1
-#define AT91C_PWMC_CHID2          (0x1 <<  2) // (PWMC) Channel ID 2
-#define AT91C_PWMC_CHID3          (0x1 <<  3) // (PWMC) Channel ID 3
-// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
-// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
-// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
-// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
-// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
-// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_PWMC structure *** */
+#define PWMC_MR                    ( 0 )          /* PWMC Mode Register */
+#define PWMC_ENA                   ( 4 )          /* PWMC Enable Register */
+#define PWMC_DIS                   ( 8 )          /* PWMC Disable Register */
+#define PWMC_SR                    ( 12 )         /* PWMC Status Register */
+#define PWMC_IER                   ( 16 )         /* PWMC Interrupt Enable Register */
+#define PWMC_IDR                   ( 20 )         /* PWMC Interrupt Disable Register */
+#define PWMC_IMR                   ( 24 )         /* PWMC Interrupt Mask Register */
+#define PWMC_ISR                   ( 28 )         /* PWMC Interrupt Status Register */
+#define PWMC_VR                    ( 252 )        /* PWMC Version Register */
+#define PWMC_CH                    ( 512 )        /* PWMC Channel */
+/* -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- */
+#define AT91C_PWMC_DIVA            ( 0xFF << 0 )  /* (PWMC) CLKA divide factor. */
+#define AT91C_PWMC_PREA            ( 0xF << 8 )   /* (PWMC) Divider Input Clock Prescaler A */
+#define     AT91C_PWMC_PREA_MCK    ( 0x0 << 8 )   /* (PWMC) */
+#define AT91C_PWMC_DIVB            ( 0xFF << 16 ) /* (PWMC) CLKB divide factor. */
+#define AT91C_PWMC_PREB            ( 0xF << 24 )  /* (PWMC) Divider Input Clock Prescaler B */
+#define     AT91C_PWMC_PREB_MCK    ( 0x0 << 24 )  /* (PWMC) */
+/* -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- */
+#define AT91C_PWMC_CHID0           ( 0x1 << 0 )   /* (PWMC) Channel ID 0 */
+#define AT91C_PWMC_CHID1           ( 0x1 << 1 )   /* (PWMC) Channel ID 1 */
+#define AT91C_PWMC_CHID2           ( 0x1 << 2 )   /* (PWMC) Channel ID 2 */
+#define AT91C_PWMC_CHID3           ( 0x1 << 3 )   /* (PWMC) Channel ID 3 */
+/* -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- */
+/* -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- */
+/* -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- */
+/* -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- */
+/* -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- */
+/* -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR USB Device Interface
-// *****************************************************************************
-// *** Register offset in AT91S_UDP structure ***
-#define UDP_NUM         ( 0) // Frame Number Register
-#define UDP_GLBSTATE    ( 4) // Global State Register
-#define UDP_FADDR       ( 8) // Function Address Register
-#define UDP_IER         (16) // Interrupt Enable Register
-#define UDP_IDR         (20) // Interrupt Disable Register
-#define UDP_IMR         (24) // Interrupt Mask Register
-#define UDP_ISR         (28) // Interrupt Status Register
-#define UDP_ICR         (32) // Interrupt Clear Register
-#define UDP_RSTEP       (40) // Reset Endpoint Register
-#define UDP_CSR         (48) // Endpoint Control and Status Register
-#define UDP_FDR         (80) // Endpoint FIFO Data Register
-#define UDP_TXVC        (116) // Transceiver Control Register
-// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
-#define AT91C_UDP_FRM_NUM         (0x7FF <<  0) // (UDP) Frame Number as Defined in the Packet Field Formats
-#define AT91C_UDP_FRM_ERR         (0x1 << 16) // (UDP) Frame Error
-#define AT91C_UDP_FRM_OK          (0x1 << 17) // (UDP) Frame OK
-// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
-#define AT91C_UDP_FADDEN          (0x1 <<  0) // (UDP) Function Address Enable
-#define AT91C_UDP_CONFG           (0x1 <<  1) // (UDP) Configured
-#define AT91C_UDP_ESR             (0x1 <<  2) // (UDP) Enable Send Resume
-#define AT91C_UDP_RSMINPR         (0x1 <<  3) // (UDP) A Resume Has Been Sent to the Host
-#define AT91C_UDP_RMWUPE          (0x1 <<  4) // (UDP) Remote Wake Up Enable
-// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
-#define AT91C_UDP_FADD            (0xFF <<  0) // (UDP) Function Address Value
-#define AT91C_UDP_FEN             (0x1 <<  8) // (UDP) Function Enable
-// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
-#define AT91C_UDP_EPINT0          (0x1 <<  0) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT1          (0x1 <<  1) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT2          (0x1 <<  2) // (UDP) Endpoint 2 Interrupt
-#define AT91C_UDP_EPINT3          (0x1 <<  3) // (UDP) Endpoint 3 Interrupt
-#define AT91C_UDP_EPINT4          (0x1 <<  4) // (UDP) Endpoint 4 Interrupt
-#define AT91C_UDP_EPINT5          (0x1 <<  5) // (UDP) Endpoint 5 Interrupt
-#define AT91C_UDP_RXSUSP          (0x1 <<  8) // (UDP) USB Suspend Interrupt
-#define AT91C_UDP_RXRSM           (0x1 <<  9) // (UDP) USB Resume Interrupt
-#define AT91C_UDP_EXTRSM          (0x1 << 10) // (UDP) USB External Resume Interrupt
-#define AT91C_UDP_SOFINT          (0x1 << 11) // (UDP) USB Start Of frame Interrupt
-#define AT91C_UDP_WAKEUP          (0x1 << 13) // (UDP) USB Resume Interrupt
-// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
-// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
-// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
-#define AT91C_UDP_ENDBUSRES       (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
-// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
-// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
-#define AT91C_UDP_EP0             (0x1 <<  0) // (UDP) Reset Endpoint 0
-#define AT91C_UDP_EP1             (0x1 <<  1) // (UDP) Reset Endpoint 1
-#define AT91C_UDP_EP2             (0x1 <<  2) // (UDP) Reset Endpoint 2
-#define AT91C_UDP_EP3             (0x1 <<  3) // (UDP) Reset Endpoint 3
-#define AT91C_UDP_EP4             (0x1 <<  4) // (UDP) Reset Endpoint 4
-#define AT91C_UDP_EP5             (0x1 <<  5) // (UDP) Reset Endpoint 5
-// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
-#define AT91C_UDP_TXCOMP          (0x1 <<  0) // (UDP) Generates an IN packet with data previously written in the DPR
-#define AT91C_UDP_RX_DATA_BK0     (0x1 <<  1) // (UDP) Receive Data Bank 0
-#define AT91C_UDP_RXSETUP         (0x1 <<  2) // (UDP) Sends STALL to the Host (Control endpoints)
-#define AT91C_UDP_ISOERROR        (0x1 <<  3) // (UDP) Isochronous error (Isochronous endpoints)
-#define AT91C_UDP_TXPKTRDY        (0x1 <<  4) // (UDP) Transmit Packet Ready
-#define AT91C_UDP_FORCESTALL      (0x1 <<  5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
-#define AT91C_UDP_RX_DATA_BK1     (0x1 <<  6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
-#define AT91C_UDP_DIR             (0x1 <<  7) // (UDP) Transfer Direction
-#define AT91C_UDP_EPTYPE          (0x7 <<  8) // (UDP) Endpoint type
-#define     AT91C_UDP_EPTYPE_CTRL                 (0x0 <<  8) // (UDP) Control
-#define     AT91C_UDP_EPTYPE_ISO_OUT              (0x1 <<  8) // (UDP) Isochronous OUT
-#define     AT91C_UDP_EPTYPE_BULK_OUT             (0x2 <<  8) // (UDP) Bulk OUT
-#define     AT91C_UDP_EPTYPE_INT_OUT              (0x3 <<  8) // (UDP) Interrupt OUT
-#define     AT91C_UDP_EPTYPE_ISO_IN               (0x5 <<  8) // (UDP) Isochronous IN
-#define     AT91C_UDP_EPTYPE_BULK_IN              (0x6 <<  8) // (UDP) Bulk IN
-#define     AT91C_UDP_EPTYPE_INT_IN               (0x7 <<  8) // (UDP) Interrupt IN
-#define AT91C_UDP_DTGLE           (0x1 << 11) // (UDP) Data Toggle
-#define AT91C_UDP_EPEDS           (0x1 << 15) // (UDP) Endpoint Enable Disable
-#define AT91C_UDP_RXBYTECNT       (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
-// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------
-#define AT91C_UDP_TXVDIS          (0x1 <<  8) // (UDP)
-#define AT91C_UDP_PUON            (0x1 <<  9) // (UDP) Pull-up ON
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR USB Device Interface */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_UDP structure *** */
+#define UDP_NUM              ( 0 )          /* Frame Number Register */
+#define UDP_GLBSTATE         ( 4 )          /* Global State Register */
+#define UDP_FADDR            ( 8 )          /* Function Address Register */
+#define UDP_IER              ( 16 )         /* Interrupt Enable Register */
+#define UDP_IDR              ( 20 )         /* Interrupt Disable Register */
+#define UDP_IMR              ( 24 )         /* Interrupt Mask Register */
+#define UDP_ISR              ( 28 )         /* Interrupt Status Register */
+#define UDP_ICR              ( 32 )         /* Interrupt Clear Register */
+#define UDP_RSTEP            ( 40 )         /* Reset Endpoint Register */
+#define UDP_CSR              ( 48 )         /* Endpoint Control and Status Register */
+#define UDP_FDR              ( 80 )         /* Endpoint FIFO Data Register */
+#define UDP_TXVC             ( 116 )        /* Transceiver Control Register */
+/* -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- */
+#define AT91C_UDP_FRM_NUM    ( 0x7FF << 0 ) /* (UDP) Frame Number as Defined in the Packet Field Formats */
+#define AT91C_UDP_FRM_ERR    ( 0x1 << 16 )  /* (UDP) Frame Error */
+#define AT91C_UDP_FRM_OK     ( 0x1 << 17 )  /* (UDP) Frame OK */
+/* -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- */
+#define AT91C_UDP_FADDEN     ( 0x1 << 0 )   /* (UDP) Function Address Enable */
+#define AT91C_UDP_CONFG      ( 0x1 << 1 )   /* (UDP) Configured */
+#define AT91C_UDP_ESR        ( 0x1 << 2 )   /* (UDP) Enable Send Resume */
+#define AT91C_UDP_RSMINPR    ( 0x1 << 3 )   /* (UDP) A Resume Has Been Sent to the Host */
+#define AT91C_UDP_RMWUPE     ( 0x1 << 4 )   /* (UDP) Remote Wake Up Enable */
+/* -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- */
+#define AT91C_UDP_FADD       ( 0xFF << 0 )  /* (UDP) Function Address Value */
+#define AT91C_UDP_FEN        ( 0x1 << 8 )   /* (UDP) Function Enable */
+/* -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- */
+#define AT91C_UDP_EPINT0     ( 0x1 << 0 )   /* (UDP) Endpoint 0 Interrupt */
+#define AT91C_UDP_EPINT1     ( 0x1 << 1 )   /* (UDP) Endpoint 0 Interrupt */
+#define AT91C_UDP_EPINT2     ( 0x1 << 2 )   /* (UDP) Endpoint 2 Interrupt */
+#define AT91C_UDP_EPINT3     ( 0x1 << 3 )   /* (UDP) Endpoint 3 Interrupt */
+#define AT91C_UDP_EPINT4     ( 0x1 << 4 )   /* (UDP) Endpoint 4 Interrupt */
+#define AT91C_UDP_EPINT5     ( 0x1 << 5 )   /* (UDP) Endpoint 5 Interrupt */
+#define AT91C_UDP_RXSUSP     ( 0x1 << 8 )   /* (UDP) USB Suspend Interrupt */
+#define AT91C_UDP_RXRSM      ( 0x1 << 9 )   /* (UDP) USB Resume Interrupt */
+#define AT91C_UDP_EXTRSM     ( 0x1 << 10 )  /* (UDP) USB External Resume Interrupt */
+#define AT91C_UDP_SOFINT     ( 0x1 << 11 )  /* (UDP) USB Start Of frame Interrupt */
+#define AT91C_UDP_WAKEUP     ( 0x1 << 13 )  /* (UDP) USB Resume Interrupt */
+/* -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- */
+/* -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- */
+/* -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- */
+#define AT91C_UDP_ENDBUSRES              ( 0x1 << 12 ) /* (UDP) USB End Of Bus Reset Interrupt */
+/* -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- */
+/* -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- */
+#define AT91C_UDP_EP0                    ( 0x1 << 0 )    /* (UDP) Reset Endpoint 0 */
+#define AT91C_UDP_EP1                    ( 0x1 << 1 )    /* (UDP) Reset Endpoint 1 */
+#define AT91C_UDP_EP2                    ( 0x1 << 2 )    /* (UDP) Reset Endpoint 2 */
+#define AT91C_UDP_EP3                    ( 0x1 << 3 )    /* (UDP) Reset Endpoint 3 */
+#define AT91C_UDP_EP4                    ( 0x1 << 4 )    /* (UDP) Reset Endpoint 4 */
+#define AT91C_UDP_EP5                    ( 0x1 << 5 )    /* (UDP) Reset Endpoint 5 */
+/* -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- */
+#define AT91C_UDP_TXCOMP                 ( 0x1 << 0 )    /* (UDP) Generates an IN packet with data previously written in the DPR */
+#define AT91C_UDP_RX_DATA_BK0            ( 0x1 << 1 )    /* (UDP) Receive Data Bank 0 */
+#define AT91C_UDP_RXSETUP                ( 0x1 << 2 )    /* (UDP) Sends STALL to the Host (Control endpoints) */
+#define AT91C_UDP_ISOERROR               ( 0x1 << 3 )    /* (UDP) Isochronous error (Isochronous endpoints) */
+#define AT91C_UDP_TXPKTRDY               ( 0x1 << 4 )    /* (UDP) Transmit Packet Ready */
+#define AT91C_UDP_FORCESTALL             ( 0x1 << 5 )    /* (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). */
+#define AT91C_UDP_RX_DATA_BK1            ( 0x1 << 6 )    /* (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). */
+#define AT91C_UDP_DIR                    ( 0x1 << 7 )    /* (UDP) Transfer Direction */
+#define AT91C_UDP_EPTYPE                 ( 0x7 << 8 )    /* (UDP) Endpoint type */
+#define     AT91C_UDP_EPTYPE_CTRL        ( 0x0 << 8 )    /* (UDP) Control */
+#define     AT91C_UDP_EPTYPE_ISO_OUT     ( 0x1 << 8 )    /* (UDP) Isochronous OUT */
+#define     AT91C_UDP_EPTYPE_BULK_OUT    ( 0x2 << 8 )    /* (UDP) Bulk OUT */
+#define     AT91C_UDP_EPTYPE_INT_OUT     ( 0x3 << 8 )    /* (UDP) Interrupt OUT */
+#define     AT91C_UDP_EPTYPE_ISO_IN      ( 0x5 << 8 )    /* (UDP) Isochronous IN */
+#define     AT91C_UDP_EPTYPE_BULK_IN     ( 0x6 << 8 )    /* (UDP) Bulk IN */
+#define     AT91C_UDP_EPTYPE_INT_IN      ( 0x7 << 8 )    /* (UDP) Interrupt IN */
+#define AT91C_UDP_DTGLE                  ( 0x1 << 11 )   /* (UDP) Data Toggle */
+#define AT91C_UDP_EPEDS                  ( 0x1 << 15 )   /* (UDP) Endpoint Enable Disable */
+#define AT91C_UDP_RXBYTECNT              ( 0x7FF << 16 ) /* (UDP) Number Of Bytes Available in the FIFO */
+/* -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- */
+#define AT91C_UDP_TXVDIS                 ( 0x1 << 8 )    /* (UDP) */
+#define AT91C_UDP_PUON                   ( 0x1 << 9 )    /* (UDP) Pull-up ON */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
-// *****************************************************************************
-// *** Register offset in AT91S_TC structure ***
-#define TC_CCR          ( 0) // Channel Control Register
-#define TC_CMR          ( 4) // Channel Mode Register (Capture Mode / Waveform Mode)
-#define TC_CV           (16) // Counter Value
-#define TC_RA           (20) // Register A
-#define TC_RB           (24) // Register B
-#define TC_RC           (28) // Register C
-#define TC_SR           (32) // Status Register
-#define TC_IER          (36) // Interrupt Enable Register
-#define TC_IDR          (40) // Interrupt Disable Register
-#define TC_IMR          (44) // Interrupt Mask Register
-// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
-#define AT91C_TC_CLKEN            (0x1 <<  0) // (TC) Counter Clock Enable Command
-#define AT91C_TC_CLKDIS           (0x1 <<  1) // (TC) Counter Clock Disable Command
-#define AT91C_TC_SWTRG            (0x1 <<  2) // (TC) Software Trigger Command
-// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
-#define AT91C_TC_CLKS             (0x7 <<  0) // (TC) Clock Selection
-#define     AT91C_TC_CLKS_TIMER_DIV1_CLOCK     (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
-#define     AT91C_TC_CLKS_TIMER_DIV2_CLOCK     (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
-#define     AT91C_TC_CLKS_TIMER_DIV3_CLOCK     (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
-#define     AT91C_TC_CLKS_TIMER_DIV4_CLOCK     (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
-#define     AT91C_TC_CLKS_TIMER_DIV5_CLOCK     (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
-#define     AT91C_TC_CLKS_XC0                  (0x5) // (TC) Clock selected: XC0
-#define     AT91C_TC_CLKS_XC1                  (0x6) // (TC) Clock selected: XC1
-#define     AT91C_TC_CLKS_XC2                  (0x7) // (TC) Clock selected: XC2
-#define AT91C_TC_CLKI             (0x1 <<  3) // (TC) Clock Invert
-#define AT91C_TC_BURST            (0x3 <<  4) // (TC) Burst Signal Selection
-#define     AT91C_TC_BURST_NONE                 (0x0 <<  4) // (TC) The clock is not gated by an external signal
-#define     AT91C_TC_BURST_XC0                  (0x1 <<  4) // (TC) XC0 is ANDed with the selected clock
-#define     AT91C_TC_BURST_XC1                  (0x2 <<  4) // (TC) XC1 is ANDed with the selected clock
-#define     AT91C_TC_BURST_XC2                  (0x3 <<  4) // (TC) XC2 is ANDed with the selected clock
-#define AT91C_TC_CPCSTOP          (0x1 <<  6) // (TC) Counter Clock Stopped with RC Compare
-#define AT91C_TC_LDBSTOP          (0x1 <<  6) // (TC) Counter Clock Stopped with RB Loading
-#define AT91C_TC_CPCDIS           (0x1 <<  7) // (TC) Counter Clock Disable with RC Compare
-#define AT91C_TC_LDBDIS           (0x1 <<  7) // (TC) Counter Clock Disabled with RB Loading
-#define AT91C_TC_ETRGEDG          (0x3 <<  8) // (TC) External Trigger Edge Selection
-#define     AT91C_TC_ETRGEDG_NONE                 (0x0 <<  8) // (TC) Edge: None
-#define     AT91C_TC_ETRGEDG_RISING               (0x1 <<  8) // (TC) Edge: rising edge
-#define     AT91C_TC_ETRGEDG_FALLING              (0x2 <<  8) // (TC) Edge: falling edge
-#define     AT91C_TC_ETRGEDG_BOTH                 (0x3 <<  8) // (TC) Edge: each edge
-#define AT91C_TC_EEVTEDG          (0x3 <<  8) // (TC) External Event Edge Selection
-#define     AT91C_TC_EEVTEDG_NONE                 (0x0 <<  8) // (TC) Edge: None
-#define     AT91C_TC_EEVTEDG_RISING               (0x1 <<  8) // (TC) Edge: rising edge
-#define     AT91C_TC_EEVTEDG_FALLING              (0x2 <<  8) // (TC) Edge: falling edge
-#define     AT91C_TC_EEVTEDG_BOTH                 (0x3 <<  8) // (TC) Edge: each edge
-#define AT91C_TC_EEVT             (0x3 << 10) // (TC) External Event  Selection
-#define     AT91C_TC_EEVT_TIOB                 (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
-#define     AT91C_TC_EEVT_XC0                  (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
-#define     AT91C_TC_EEVT_XC1                  (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
-#define     AT91C_TC_EEVT_XC2                  (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
-#define AT91C_TC_ABETRG           (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
-#define AT91C_TC_ENETRG           (0x1 << 12) // (TC) External Event Trigger enable
-#define AT91C_TC_WAVESEL          (0x3 << 13) // (TC) Waveform  Selection
-#define     AT91C_TC_WAVESEL_UP                   (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
-#define     AT91C_TC_WAVESEL_UPDOWN               (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
-#define     AT91C_TC_WAVESEL_UP_AUTO              (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
-#define     AT91C_TC_WAVESEL_UPDOWN_AUTO          (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
-#define AT91C_TC_CPCTRG           (0x1 << 14) // (TC) RC Compare Trigger Enable
-#define AT91C_TC_WAVE             (0x1 << 15) // (TC)
-#define AT91C_TC_ACPA             (0x3 << 16) // (TC) RA Compare Effect on TIOA
-#define     AT91C_TC_ACPA_NONE                 (0x0 << 16) // (TC) Effect: none
-#define     AT91C_TC_ACPA_SET                  (0x1 << 16) // (TC) Effect: set
-#define     AT91C_TC_ACPA_CLEAR                (0x2 << 16) // (TC) Effect: clear
-#define     AT91C_TC_ACPA_TOGGLE               (0x3 << 16) // (TC) Effect: toggle
-#define AT91C_TC_LDRA             (0x3 << 16) // (TC) RA Loading Selection
-#define     AT91C_TC_LDRA_NONE                 (0x0 << 16) // (TC) Edge: None
-#define     AT91C_TC_LDRA_RISING               (0x1 << 16) // (TC) Edge: rising edge of TIOA
-#define     AT91C_TC_LDRA_FALLING              (0x2 << 16) // (TC) Edge: falling edge of TIOA
-#define     AT91C_TC_LDRA_BOTH                 (0x3 << 16) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_ACPC             (0x3 << 18) // (TC) RC Compare Effect on TIOA
-#define     AT91C_TC_ACPC_NONE                 (0x0 << 18) // (TC) Effect: none
-#define     AT91C_TC_ACPC_SET                  (0x1 << 18) // (TC) Effect: set
-#define     AT91C_TC_ACPC_CLEAR                (0x2 << 18) // (TC) Effect: clear
-#define     AT91C_TC_ACPC_TOGGLE               (0x3 << 18) // (TC) Effect: toggle
-#define AT91C_TC_LDRB             (0x3 << 18) // (TC) RB Loading Selection
-#define     AT91C_TC_LDRB_NONE                 (0x0 << 18) // (TC) Edge: None
-#define     AT91C_TC_LDRB_RISING               (0x1 << 18) // (TC) Edge: rising edge of TIOA
-#define     AT91C_TC_LDRB_FALLING              (0x2 << 18) // (TC) Edge: falling edge of TIOA
-#define     AT91C_TC_LDRB_BOTH                 (0x3 << 18) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_AEEVT            (0x3 << 20) // (TC) External Event Effect on TIOA
-#define     AT91C_TC_AEEVT_NONE                 (0x0 << 20) // (TC) Effect: none
-#define     AT91C_TC_AEEVT_SET                  (0x1 << 20) // (TC) Effect: set
-#define     AT91C_TC_AEEVT_CLEAR                (0x2 << 20) // (TC) Effect: clear
-#define     AT91C_TC_AEEVT_TOGGLE               (0x3 << 20) // (TC) Effect: toggle
-#define AT91C_TC_ASWTRG           (0x3 << 22) // (TC) Software Trigger Effect on TIOA
-#define     AT91C_TC_ASWTRG_NONE                 (0x0 << 22) // (TC) Effect: none
-#define     AT91C_TC_ASWTRG_SET                  (0x1 << 22) // (TC) Effect: set
-#define     AT91C_TC_ASWTRG_CLEAR                (0x2 << 22) // (TC) Effect: clear
-#define     AT91C_TC_ASWTRG_TOGGLE               (0x3 << 22) // (TC) Effect: toggle
-#define AT91C_TC_BCPB             (0x3 << 24) // (TC) RB Compare Effect on TIOB
-#define     AT91C_TC_BCPB_NONE                 (0x0 << 24) // (TC) Effect: none
-#define     AT91C_TC_BCPB_SET                  (0x1 << 24) // (TC) Effect: set
-#define     AT91C_TC_BCPB_CLEAR                (0x2 << 24) // (TC) Effect: clear
-#define     AT91C_TC_BCPB_TOGGLE               (0x3 << 24) // (TC) Effect: toggle
-#define AT91C_TC_BCPC             (0x3 << 26) // (TC) RC Compare Effect on TIOB
-#define     AT91C_TC_BCPC_NONE                 (0x0 << 26) // (TC) Effect: none
-#define     AT91C_TC_BCPC_SET                  (0x1 << 26) // (TC) Effect: set
-#define     AT91C_TC_BCPC_CLEAR                (0x2 << 26) // (TC) Effect: clear
-#define     AT91C_TC_BCPC_TOGGLE               (0x3 << 26) // (TC) Effect: toggle
-#define AT91C_TC_BEEVT            (0x3 << 28) // (TC) External Event Effect on TIOB
-#define     AT91C_TC_BEEVT_NONE                 (0x0 << 28) // (TC) Effect: none
-#define     AT91C_TC_BEEVT_SET                  (0x1 << 28) // (TC) Effect: set
-#define     AT91C_TC_BEEVT_CLEAR                (0x2 << 28) // (TC) Effect: clear
-#define     AT91C_TC_BEEVT_TOGGLE               (0x3 << 28) // (TC) Effect: toggle
-#define AT91C_TC_BSWTRG           (0x3 << 30) // (TC) Software Trigger Effect on TIOB
-#define     AT91C_TC_BSWTRG_NONE                 (0x0 << 30) // (TC) Effect: none
-#define     AT91C_TC_BSWTRG_SET                  (0x1 << 30) // (TC) Effect: set
-#define     AT91C_TC_BSWTRG_CLEAR                (0x2 << 30) // (TC) Effect: clear
-#define     AT91C_TC_BSWTRG_TOGGLE               (0x3 << 30) // (TC) Effect: toggle
-// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
-#define AT91C_TC_COVFS            (0x1 <<  0) // (TC) Counter Overflow
-#define AT91C_TC_LOVRS            (0x1 <<  1) // (TC) Load Overrun
-#define AT91C_TC_CPAS             (0x1 <<  2) // (TC) RA Compare
-#define AT91C_TC_CPBS             (0x1 <<  3) // (TC) RB Compare
-#define AT91C_TC_CPCS             (0x1 <<  4) // (TC) RC Compare
-#define AT91C_TC_LDRAS            (0x1 <<  5) // (TC) RA Loading
-#define AT91C_TC_LDRBS            (0x1 <<  6) // (TC) RB Loading
-#define AT91C_TC_ETRGS            (0x1 <<  7) // (TC) External Trigger
-#define AT91C_TC_CLKSTA           (0x1 << 16) // (TC) Clock Enabling
-#define AT91C_TC_MTIOA            (0x1 << 17) // (TC) TIOA Mirror
-#define AT91C_TC_MTIOB            (0x1 << 18) // (TC) TIOA Mirror
-// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
-// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
-// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_TC structure *** */
+#define TC_CCR                                ( 0 )         /* Channel Control Register */
+#define TC_CMR                                ( 4 )         /* Channel Mode Register (Capture Mode / Waveform Mode) */
+#define TC_CV                                 ( 16 )        /* Counter Value */
+#define TC_RA                                 ( 20 )        /* Register A */
+#define TC_RB                                 ( 24 )        /* Register B */
+#define TC_RC                                 ( 28 )        /* Register C */
+#define TC_SR                                 ( 32 )        /* Status Register */
+#define TC_IER                                ( 36 )        /* Interrupt Enable Register */
+#define TC_IDR                                ( 40 )        /* Interrupt Disable Register */
+#define TC_IMR                                ( 44 )        /* Interrupt Mask Register */
+/* -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- */
+#define AT91C_TC_CLKEN                        ( 0x1 << 0 )  /* (TC) Counter Clock Enable Command */
+#define AT91C_TC_CLKDIS                       ( 0x1 << 1 )  /* (TC) Counter Clock Disable Command */
+#define AT91C_TC_SWTRG                        ( 0x1 << 2 )  /* (TC) Software Trigger Command */
+/* -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- */
+#define AT91C_TC_CLKS                         ( 0x7 << 0 )  /* (TC) Clock Selection */
+#define     AT91C_TC_CLKS_TIMER_DIV1_CLOCK    ( 0x0 )       /* (TC) Clock selected: TIMER_DIV1_CLOCK */
+#define     AT91C_TC_CLKS_TIMER_DIV2_CLOCK    ( 0x1 )       /* (TC) Clock selected: TIMER_DIV2_CLOCK */
+#define     AT91C_TC_CLKS_TIMER_DIV3_CLOCK    ( 0x2 )       /* (TC) Clock selected: TIMER_DIV3_CLOCK */
+#define     AT91C_TC_CLKS_TIMER_DIV4_CLOCK    ( 0x3 )       /* (TC) Clock selected: TIMER_DIV4_CLOCK */
+#define     AT91C_TC_CLKS_TIMER_DIV5_CLOCK    ( 0x4 )       /* (TC) Clock selected: TIMER_DIV5_CLOCK */
+#define     AT91C_TC_CLKS_XC0                 ( 0x5 )       /* (TC) Clock selected: XC0 */
+#define     AT91C_TC_CLKS_XC1                 ( 0x6 )       /* (TC) Clock selected: XC1 */
+#define     AT91C_TC_CLKS_XC2                 ( 0x7 )       /* (TC) Clock selected: XC2 */
+#define AT91C_TC_CLKI                         ( 0x1 << 3 )  /* (TC) Clock Invert */
+#define AT91C_TC_BURST                        ( 0x3 << 4 )  /* (TC) Burst Signal Selection */
+#define     AT91C_TC_BURST_NONE               ( 0x0 << 4 )  /* (TC) The clock is not gated by an external signal */
+#define     AT91C_TC_BURST_XC0                ( 0x1 << 4 )  /* (TC) XC0 is ANDed with the selected clock */
+#define     AT91C_TC_BURST_XC1                ( 0x2 << 4 )  /* (TC) XC1 is ANDed with the selected clock */
+#define     AT91C_TC_BURST_XC2                ( 0x3 << 4 )  /* (TC) XC2 is ANDed with the selected clock */
+#define AT91C_TC_CPCSTOP                      ( 0x1 << 6 )  /* (TC) Counter Clock Stopped with RC Compare */
+#define AT91C_TC_LDBSTOP                      ( 0x1 << 6 )  /* (TC) Counter Clock Stopped with RB Loading */
+#define AT91C_TC_CPCDIS                       ( 0x1 << 7 )  /* (TC) Counter Clock Disable with RC Compare */
+#define AT91C_TC_LDBDIS                       ( 0x1 << 7 )  /* (TC) Counter Clock Disabled with RB Loading */
+#define AT91C_TC_ETRGEDG                      ( 0x3 << 8 )  /* (TC) External Trigger Edge Selection */
+#define     AT91C_TC_ETRGEDG_NONE             ( 0x0 << 8 )  /* (TC) Edge: None */
+#define     AT91C_TC_ETRGEDG_RISING           ( 0x1 << 8 )  /* (TC) Edge: rising edge */
+#define     AT91C_TC_ETRGEDG_FALLING          ( 0x2 << 8 )  /* (TC) Edge: falling edge */
+#define     AT91C_TC_ETRGEDG_BOTH             ( 0x3 << 8 )  /* (TC) Edge: each edge */
+#define AT91C_TC_EEVTEDG                      ( 0x3 << 8 )  /* (TC) External Event Edge Selection */
+#define     AT91C_TC_EEVTEDG_NONE             ( 0x0 << 8 )  /* (TC) Edge: None */
+#define     AT91C_TC_EEVTEDG_RISING           ( 0x1 << 8 )  /* (TC) Edge: rising edge */
+#define     AT91C_TC_EEVTEDG_FALLING          ( 0x2 << 8 )  /* (TC) Edge: falling edge */
+#define     AT91C_TC_EEVTEDG_BOTH             ( 0x3 << 8 )  /* (TC) Edge: each edge */
+#define AT91C_TC_EEVT                         ( 0x3 << 10 ) /* (TC) External Event  Selection */
+#define     AT91C_TC_EEVT_TIOB                ( 0x0 << 10 ) /* (TC) Signal selected as external event: TIOB TIOB direction: input */
+#define     AT91C_TC_EEVT_XC0                 ( 0x1 << 10 ) /* (TC) Signal selected as external event: XC0 TIOB direction: output */
+#define     AT91C_TC_EEVT_XC1                 ( 0x2 << 10 ) /* (TC) Signal selected as external event: XC1 TIOB direction: output */
+#define     AT91C_TC_EEVT_XC2                 ( 0x3 << 10 ) /* (TC) Signal selected as external event: XC2 TIOB direction: output */
+#define AT91C_TC_ABETRG                       ( 0x1 << 10 ) /* (TC) TIOA or TIOB External Trigger Selection */
+#define AT91C_TC_ENETRG                       ( 0x1 << 12 ) /* (TC) External Event Trigger enable */
+#define AT91C_TC_WAVESEL                      ( 0x3 << 13 ) /* (TC) Waveform  Selection */
+#define     AT91C_TC_WAVESEL_UP               ( 0x0 << 13 ) /* (TC) UP mode without atomatic trigger on RC Compare */
+#define     AT91C_TC_WAVESEL_UPDOWN           ( 0x1 << 13 ) /* (TC) UPDOWN mode without automatic trigger on RC Compare */
+#define     AT91C_TC_WAVESEL_UP_AUTO          ( 0x2 << 13 ) /* (TC) UP mode with automatic trigger on RC Compare */
+#define     AT91C_TC_WAVESEL_UPDOWN_AUTO      ( 0x3 << 13 ) /* (TC) UPDOWN mode with automatic trigger on RC Compare */
+#define AT91C_TC_CPCTRG                       ( 0x1 << 14 ) /* (TC) RC Compare Trigger Enable */
+#define AT91C_TC_WAVE                         ( 0x1 << 15 ) /* (TC) */
+#define AT91C_TC_ACPA                         ( 0x3 << 16 ) /* (TC) RA Compare Effect on TIOA */
+#define     AT91C_TC_ACPA_NONE                ( 0x0 << 16 ) /* (TC) Effect: none */
+#define     AT91C_TC_ACPA_SET                 ( 0x1 << 16 ) /* (TC) Effect: set */
+#define     AT91C_TC_ACPA_CLEAR               ( 0x2 << 16 ) /* (TC) Effect: clear */
+#define     AT91C_TC_ACPA_TOGGLE              ( 0x3 << 16 ) /* (TC) Effect: toggle */
+#define AT91C_TC_LDRA                         ( 0x3 << 16 ) /* (TC) RA Loading Selection */
+#define     AT91C_TC_LDRA_NONE                ( 0x0 << 16 ) /* (TC) Edge: None */
+#define     AT91C_TC_LDRA_RISING              ( 0x1 << 16 ) /* (TC) Edge: rising edge of TIOA */
+#define     AT91C_TC_LDRA_FALLING             ( 0x2 << 16 ) /* (TC) Edge: falling edge of TIOA */
+#define     AT91C_TC_LDRA_BOTH                ( 0x3 << 16 ) /* (TC) Edge: each edge of TIOA */
+#define AT91C_TC_ACPC                         ( 0x3 << 18 ) /* (TC) RC Compare Effect on TIOA */
+#define     AT91C_TC_ACPC_NONE                ( 0x0 << 18 ) /* (TC) Effect: none */
+#define     AT91C_TC_ACPC_SET                 ( 0x1 << 18 ) /* (TC) Effect: set */
+#define     AT91C_TC_ACPC_CLEAR               ( 0x2 << 18 ) /* (TC) Effect: clear */
+#define     AT91C_TC_ACPC_TOGGLE              ( 0x3 << 18 ) /* (TC) Effect: toggle */
+#define AT91C_TC_LDRB                         ( 0x3 << 18 ) /* (TC) RB Loading Selection */
+#define     AT91C_TC_LDRB_NONE                ( 0x0 << 18 ) /* (TC) Edge: None */
+#define     AT91C_TC_LDRB_RISING              ( 0x1 << 18 ) /* (TC) Edge: rising edge of TIOA */
+#define     AT91C_TC_LDRB_FALLING             ( 0x2 << 18 ) /* (TC) Edge: falling edge of TIOA */
+#define     AT91C_TC_LDRB_BOTH                ( 0x3 << 18 ) /* (TC) Edge: each edge of TIOA */
+#define AT91C_TC_AEEVT                        ( 0x3 << 20 ) /* (TC) External Event Effect on TIOA */
+#define     AT91C_TC_AEEVT_NONE               ( 0x0 << 20 ) /* (TC) Effect: none */
+#define     AT91C_TC_AEEVT_SET                ( 0x1 << 20 ) /* (TC) Effect: set */
+#define     AT91C_TC_AEEVT_CLEAR              ( 0x2 << 20 ) /* (TC) Effect: clear */
+#define     AT91C_TC_AEEVT_TOGGLE             ( 0x3 << 20 ) /* (TC) Effect: toggle */
+#define AT91C_TC_ASWTRG                       ( 0x3 << 22 ) /* (TC) Software Trigger Effect on TIOA */
+#define     AT91C_TC_ASWTRG_NONE              ( 0x0 << 22 ) /* (TC) Effect: none */
+#define     AT91C_TC_ASWTRG_SET               ( 0x1 << 22 ) /* (TC) Effect: set */
+#define     AT91C_TC_ASWTRG_CLEAR             ( 0x2 << 22 ) /* (TC) Effect: clear */
+#define     AT91C_TC_ASWTRG_TOGGLE            ( 0x3 << 22 ) /* (TC) Effect: toggle */
+#define AT91C_TC_BCPB                         ( 0x3 << 24 ) /* (TC) RB Compare Effect on TIOB */
+#define     AT91C_TC_BCPB_NONE                ( 0x0 << 24 ) /* (TC) Effect: none */
+#define     AT91C_TC_BCPB_SET                 ( 0x1 << 24 ) /* (TC) Effect: set */
+#define     AT91C_TC_BCPB_CLEAR               ( 0x2 << 24 ) /* (TC) Effect: clear */
+#define     AT91C_TC_BCPB_TOGGLE              ( 0x3 << 24 ) /* (TC) Effect: toggle */
+#define AT91C_TC_BCPC                         ( 0x3 << 26 ) /* (TC) RC Compare Effect on TIOB */
+#define     AT91C_TC_BCPC_NONE                ( 0x0 << 26 ) /* (TC) Effect: none */
+#define     AT91C_TC_BCPC_SET                 ( 0x1 << 26 ) /* (TC) Effect: set */
+#define     AT91C_TC_BCPC_CLEAR               ( 0x2 << 26 ) /* (TC) Effect: clear */
+#define     AT91C_TC_BCPC_TOGGLE              ( 0x3 << 26 ) /* (TC) Effect: toggle */
+#define AT91C_TC_BEEVT                        ( 0x3 << 28 ) /* (TC) External Event Effect on TIOB */
+#define     AT91C_TC_BEEVT_NONE               ( 0x0 << 28 ) /* (TC) Effect: none */
+#define     AT91C_TC_BEEVT_SET                ( 0x1 << 28 ) /* (TC) Effect: set */
+#define     AT91C_TC_BEEVT_CLEAR              ( 0x2 << 28 ) /* (TC) Effect: clear */
+#define     AT91C_TC_BEEVT_TOGGLE             ( 0x3 << 28 ) /* (TC) Effect: toggle */
+#define AT91C_TC_BSWTRG                       ( 0x3 << 30 ) /* (TC) Software Trigger Effect on TIOB */
+#define     AT91C_TC_BSWTRG_NONE              ( 0x0 << 30 ) /* (TC) Effect: none */
+#define     AT91C_TC_BSWTRG_SET               ( 0x1 << 30 ) /* (TC) Effect: set */
+#define     AT91C_TC_BSWTRG_CLEAR             ( 0x2 << 30 ) /* (TC) Effect: clear */
+#define     AT91C_TC_BSWTRG_TOGGLE            ( 0x3 << 30 ) /* (TC) Effect: toggle */
+/* -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- */
+#define AT91C_TC_COVFS                        ( 0x1 << 0 )  /* (TC) Counter Overflow */
+#define AT91C_TC_LOVRS                        ( 0x1 << 1 )  /* (TC) Load Overrun */
+#define AT91C_TC_CPAS                         ( 0x1 << 2 )  /* (TC) RA Compare */
+#define AT91C_TC_CPBS                         ( 0x1 << 3 )  /* (TC) RB Compare */
+#define AT91C_TC_CPCS                         ( 0x1 << 4 )  /* (TC) RC Compare */
+#define AT91C_TC_LDRAS                        ( 0x1 << 5 )  /* (TC) RA Loading */
+#define AT91C_TC_LDRBS                        ( 0x1 << 6 )  /* (TC) RB Loading */
+#define AT91C_TC_ETRGS                        ( 0x1 << 7 )  /* (TC) External Trigger */
+#define AT91C_TC_CLKSTA                       ( 0x1 << 16 ) /* (TC) Clock Enabling */
+#define AT91C_TC_MTIOA                        ( 0x1 << 17 ) /* (TC) TIOA Mirror */
+#define AT91C_TC_MTIOB                        ( 0x1 << 18 ) /* (TC) TIOA Mirror */
+/* -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- */
+/* -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- */
+/* -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Timer Counter Interface
-// *****************************************************************************
-// *** Register offset in AT91S_TCB structure ***
-#define TCB_TC0         ( 0) // TC Channel 0
-#define TCB_TC1         (64) // TC Channel 1
-#define TCB_TC2         (128) // TC Channel 2
-#define TCB_BCR         (192) // TC Block Control Register
-#define TCB_BMR         (196) // TC Block Mode Register
-// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
-#define AT91C_TCB_SYNC            (0x1 <<  0) // (TCB) Synchro Command
-// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
-#define AT91C_TCB_TC0XC0S         (0x3 <<  0) // (TCB) External Clock Signal 0 Selection
-#define     AT91C_TCB_TC0XC0S_TCLK0                (0x0) // (TCB) TCLK0 connected to XC0
-#define     AT91C_TCB_TC0XC0S_NONE                 (0x1) // (TCB) None signal connected to XC0
-#define     AT91C_TCB_TC0XC0S_TIOA1                (0x2) // (TCB) TIOA1 connected to XC0
-#define     AT91C_TCB_TC0XC0S_TIOA2                (0x3) // (TCB) TIOA2 connected to XC0
-#define AT91C_TCB_TC1XC1S         (0x3 <<  2) // (TCB) External Clock Signal 1 Selection
-#define     AT91C_TCB_TC1XC1S_TCLK1                (0x0 <<  2) // (TCB) TCLK1 connected to XC1
-#define     AT91C_TCB_TC1XC1S_NONE                 (0x1 <<  2) // (TCB) None signal connected to XC1
-#define     AT91C_TCB_TC1XC1S_TIOA0                (0x2 <<  2) // (TCB) TIOA0 connected to XC1
-#define     AT91C_TCB_TC1XC1S_TIOA2                (0x3 <<  2) // (TCB) TIOA2 connected to XC1
-#define AT91C_TCB_TC2XC2S         (0x3 <<  4) // (TCB) External Clock Signal 2 Selection
-#define     AT91C_TCB_TC2XC2S_TCLK2                (0x0 <<  4) // (TCB) TCLK2 connected to XC2
-#define     AT91C_TCB_TC2XC2S_NONE                 (0x1 <<  4) // (TCB) None signal connected to XC2
-#define     AT91C_TCB_TC2XC2S_TIOA0                (0x2 <<  4) // (TCB) TIOA0 connected to XC2
-#define     AT91C_TCB_TC2XC2S_TIOA1                (0x3 <<  4) // (TCB) TIOA2 connected to XC2
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Timer Counter Interface */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_TCB structure *** */
+#define TCB_TC0                        ( 0 )        /* TC Channel 0 */
+#define TCB_TC1                        ( 64 )       /* TC Channel 1 */
+#define TCB_TC2                        ( 128 )      /* TC Channel 2 */
+#define TCB_BCR                        ( 192 )      /* TC Block Control Register */
+#define TCB_BMR                        ( 196 )      /* TC Block Mode Register */
+/* -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- */
+#define AT91C_TCB_SYNC                 ( 0x1 << 0 ) /* (TCB) Synchro Command */
+/* -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- */
+#define AT91C_TCB_TC0XC0S              ( 0x3 << 0 ) /* (TCB) External Clock Signal 0 Selection */
+#define     AT91C_TCB_TC0XC0S_TCLK0    ( 0x0 )      /* (TCB) TCLK0 connected to XC0 */
+#define     AT91C_TCB_TC0XC0S_NONE     ( 0x1 )      /* (TCB) None signal connected to XC0 */
+#define     AT91C_TCB_TC0XC0S_TIOA1    ( 0x2 )      /* (TCB) TIOA1 connected to XC0 */
+#define     AT91C_TCB_TC0XC0S_TIOA2    ( 0x3 )      /* (TCB) TIOA2 connected to XC0 */
+#define AT91C_TCB_TC1XC1S              ( 0x3 << 2 ) /* (TCB) External Clock Signal 1 Selection */
+#define     AT91C_TCB_TC1XC1S_TCLK1    ( 0x0 << 2 ) /* (TCB) TCLK1 connected to XC1 */
+#define     AT91C_TCB_TC1XC1S_NONE     ( 0x1 << 2 ) /* (TCB) None signal connected to XC1 */
+#define     AT91C_TCB_TC1XC1S_TIOA0    ( 0x2 << 2 ) /* (TCB) TIOA0 connected to XC1 */
+#define     AT91C_TCB_TC1XC1S_TIOA2    ( 0x3 << 2 ) /* (TCB) TIOA2 connected to XC1 */
+#define AT91C_TCB_TC2XC2S              ( 0x3 << 4 ) /* (TCB) External Clock Signal 2 Selection */
+#define     AT91C_TCB_TC2XC2S_TCLK2    ( 0x0 << 4 ) /* (TCB) TCLK2 connected to XC2 */
+#define     AT91C_TCB_TC2XC2S_NONE     ( 0x1 << 4 ) /* (TCB) None signal connected to XC2 */
+#define     AT91C_TCB_TC2XC2S_TIOA0    ( 0x2 << 4 ) /* (TCB) TIOA0 connected to XC2 */
+#define     AT91C_TCB_TC2XC2S_TIOA1    ( 0x3 << 4 ) /* (TCB) TIOA2 connected to XC2 */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Control Area Network MailBox Interface
-// *****************************************************************************
-// *** Register offset in AT91S_CAN_MB structure ***
-#define CAN_MB_MMR      ( 0) // MailBox Mode Register
-#define CAN_MB_MAM      ( 4) // MailBox Acceptance Mask Register
-#define CAN_MB_MID      ( 8) // MailBox ID Register
-#define CAN_MB_MFID     (12) // MailBox Family ID Register
-#define CAN_MB_MSR      (16) // MailBox Status Register
-#define CAN_MB_MDL      (20) // MailBox Data Low Register
-#define CAN_MB_MDH      (24) // MailBox Data High Register
-#define CAN_MB_MCR      (28) // MailBox Control Register
-// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register --------
-#define AT91C_CAN_MTIMEMARK       (0xFFFF <<  0) // (CAN_MB) Mailbox Timemark
-#define AT91C_CAN_PRIOR           (0xF << 16) // (CAN_MB) Mailbox Priority
-#define AT91C_CAN_MOT             (0x7 << 24) // (CAN_MB) Mailbox Object Type
-#define     AT91C_CAN_MOT_DIS                  (0x0 << 24) // (CAN_MB)
-#define     AT91C_CAN_MOT_RX                   (0x1 << 24) // (CAN_MB)
-#define     AT91C_CAN_MOT_RXOVERWRITE          (0x2 << 24) // (CAN_MB)
-#define     AT91C_CAN_MOT_TX                   (0x3 << 24) // (CAN_MB)
-#define     AT91C_CAN_MOT_CONSUMER             (0x4 << 24) // (CAN_MB)
-#define     AT91C_CAN_MOT_PRODUCER             (0x5 << 24) // (CAN_MB)
-// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register --------
-#define AT91C_CAN_MIDvB           (0x3FFFF <<  0) // (CAN_MB) Complementary bits for identifier in extended mode
-#define AT91C_CAN_MIDvA           (0x7FF << 18) // (CAN_MB) Identifier for standard frame mode
-#define AT91C_CAN_MIDE            (0x1 << 29) // (CAN_MB) Identifier Version
-// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register --------
-// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register --------
-// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register --------
-#define AT91C_CAN_MTIMESTAMP      (0xFFFF <<  0) // (CAN_MB) Timer Value
-#define AT91C_CAN_MDLC            (0xF << 16) // (CAN_MB) Mailbox Data Length Code
-#define AT91C_CAN_MRTR            (0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request
-#define AT91C_CAN_MABT            (0x1 << 22) // (CAN_MB) Mailbox Message Abort
-#define AT91C_CAN_MRDY            (0x1 << 23) // (CAN_MB) Mailbox Ready
-#define AT91C_CAN_MMI             (0x1 << 24) // (CAN_MB) Mailbox Message Ignored
-// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register --------
-// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register --------
-// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register --------
-#define AT91C_CAN_MACR            (0x1 << 22) // (CAN_MB) Abort Request for Mailbox
-#define AT91C_CAN_MTCR            (0x1 << 23) // (CAN_MB) Mailbox Transfer Command
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Control Area Network MailBox Interface */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_CAN_MB structure *** */
+#define CAN_MB_MMR                       ( 0 )            /* MailBox Mode Register */
+#define CAN_MB_MAM                       ( 4 )            /* MailBox Acceptance Mask Register */
+#define CAN_MB_MID                       ( 8 )            /* MailBox ID Register */
+#define CAN_MB_MFID                      ( 12 )           /* MailBox Family ID Register */
+#define CAN_MB_MSR                       ( 16 )           /* MailBox Status Register */
+#define CAN_MB_MDL                       ( 20 )           /* MailBox Data Low Register */
+#define CAN_MB_MDH                       ( 24 )           /* MailBox Data High Register */
+#define CAN_MB_MCR                       ( 28 )           /* MailBox Control Register */
+/* -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- */
+#define AT91C_CAN_MTIMEMARK              ( 0xFFFF << 0 )  /* (CAN_MB) Mailbox Timemark */
+#define AT91C_CAN_PRIOR                  ( 0xF << 16 )    /* (CAN_MB) Mailbox Priority */
+#define AT91C_CAN_MOT                    ( 0x7 << 24 )    /* (CAN_MB) Mailbox Object Type */
+#define     AT91C_CAN_MOT_DIS            ( 0x0 << 24 )    /* (CAN_MB) */
+#define     AT91C_CAN_MOT_RX             ( 0x1 << 24 )    /* (CAN_MB) */
+#define     AT91C_CAN_MOT_RXOVERWRITE    ( 0x2 << 24 )    /* (CAN_MB) */
+#define     AT91C_CAN_MOT_TX             ( 0x3 << 24 )    /* (CAN_MB) */
+#define     AT91C_CAN_MOT_CONSUMER       ( 0x4 << 24 )    /* (CAN_MB) */
+#define     AT91C_CAN_MOT_PRODUCER       ( 0x5 << 24 )    /* (CAN_MB) */
+/* -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- */
+#define AT91C_CAN_MIDvB                  ( 0x3FFFF << 0 ) /* (CAN_MB) Complementary bits for identifier in extended mode */
+#define AT91C_CAN_MIDvA                  ( 0x7FF << 18 )  /* (CAN_MB) Identifier for standard frame mode */
+#define AT91C_CAN_MIDE                   ( 0x1 << 29 )    /* (CAN_MB) Identifier Version */
+/* -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- */
+/* -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- */
+/* -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- */
+#define AT91C_CAN_MTIMESTAMP    ( 0xFFFF << 0 ) /* (CAN_MB) Timer Value */
+#define AT91C_CAN_MDLC          ( 0xF << 16 )   /* (CAN_MB) Mailbox Data Length Code */
+#define AT91C_CAN_MRTR          ( 0x1 << 20 )   /* (CAN_MB) Mailbox Remote Transmission Request */
+#define AT91C_CAN_MABT          ( 0x1 << 22 )   /* (CAN_MB) Mailbox Message Abort */
+#define AT91C_CAN_MRDY          ( 0x1 << 23 )   /* (CAN_MB) Mailbox Ready */
+#define AT91C_CAN_MMI           ( 0x1 << 24 )   /* (CAN_MB) Mailbox Message Ignored */
+/* -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- */
+/* -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- */
+/* -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- */
+#define AT91C_CAN_MACR    ( 0x1 << 22 )       /* (CAN_MB) Abort Request for Mailbox */
+#define AT91C_CAN_MTCR    ( 0x1 << 23 )       /* (CAN_MB) Mailbox Transfer Command */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Control Area Network Interface
-// *****************************************************************************
-// *** Register offset in AT91S_CAN structure ***
-#define CAN_MR          ( 0) // Mode Register
-#define CAN_IER         ( 4) // Interrupt Enable Register
-#define CAN_IDR         ( 8) // Interrupt Disable Register
-#define CAN_IMR         (12) // Interrupt Mask Register
-#define CAN_SR          (16) // Status Register
-#define CAN_BR          (20) // Baudrate Register
-#define CAN_TIM         (24) // Timer Register
-#define CAN_TIMESTP     (28) // Time Stamp Register
-#define CAN_ECR         (32) // Error Counter Register
-#define CAN_TCR         (36) // Transfer Command Register
-#define CAN_ACR         (40) // Abort Command Register
-#define CAN_VR          (252) // Version Register
-#define CAN_MB0         (512) // CAN Mailbox 0
-#define CAN_MB1         (544) // CAN Mailbox 1
-#define CAN_MB2         (576) // CAN Mailbox 2
-#define CAN_MB3         (608) // CAN Mailbox 3
-#define CAN_MB4         (640) // CAN Mailbox 4
-#define CAN_MB5         (672) // CAN Mailbox 5
-#define CAN_MB6         (704) // CAN Mailbox 6
-#define CAN_MB7         (736) // CAN Mailbox 7
-#define CAN_MB8         (768) // CAN Mailbox 8
-#define CAN_MB9         (800) // CAN Mailbox 9
-#define CAN_MB10        (832) // CAN Mailbox 10
-#define CAN_MB11        (864) // CAN Mailbox 11
-#define CAN_MB12        (896) // CAN Mailbox 12
-#define CAN_MB13        (928) // CAN Mailbox 13
-#define CAN_MB14        (960) // CAN Mailbox 14
-#define CAN_MB15        (992) // CAN Mailbox 15
-// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register --------
-#define AT91C_CAN_CANEN           (0x1 <<  0) // (CAN) CAN Controller Enable
-#define AT91C_CAN_LPM             (0x1 <<  1) // (CAN) Disable/Enable Low Power Mode
-#define AT91C_CAN_ABM             (0x1 <<  2) // (CAN) Disable/Enable Autobaud/Listen Mode
-#define AT91C_CAN_OVL             (0x1 <<  3) // (CAN) Disable/Enable Overload Frame
-#define AT91C_CAN_TEOF            (0x1 <<  4) // (CAN) Time Stamp messages at each end of Frame
-#define AT91C_CAN_TTM             (0x1 <<  5) // (CAN) Disable/Enable Time Trigger Mode
-#define AT91C_CAN_TIMFRZ          (0x1 <<  6) // (CAN) Enable Timer Freeze
-#define AT91C_CAN_DRPT            (0x1 <<  7) // (CAN) Disable Repeat
-// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register --------
-#define AT91C_CAN_MB0             (0x1 <<  0) // (CAN) Mailbox 0 Flag
-#define AT91C_CAN_MB1             (0x1 <<  1) // (CAN) Mailbox 1 Flag
-#define AT91C_CAN_MB2             (0x1 <<  2) // (CAN) Mailbox 2 Flag
-#define AT91C_CAN_MB3             (0x1 <<  3) // (CAN) Mailbox 3 Flag
-#define AT91C_CAN_MB4             (0x1 <<  4) // (CAN) Mailbox 4 Flag
-#define AT91C_CAN_MB5             (0x1 <<  5) // (CAN) Mailbox 5 Flag
-#define AT91C_CAN_MB6             (0x1 <<  6) // (CAN) Mailbox 6 Flag
-#define AT91C_CAN_MB7             (0x1 <<  7) // (CAN) Mailbox 7 Flag
-#define AT91C_CAN_MB8             (0x1 <<  8) // (CAN) Mailbox 8 Flag
-#define AT91C_CAN_MB9             (0x1 <<  9) // (CAN) Mailbox 9 Flag
-#define AT91C_CAN_MB10            (0x1 << 10) // (CAN) Mailbox 10 Flag
-#define AT91C_CAN_MB11            (0x1 << 11) // (CAN) Mailbox 11 Flag
-#define AT91C_CAN_MB12            (0x1 << 12) // (CAN) Mailbox 12 Flag
-#define AT91C_CAN_MB13            (0x1 << 13) // (CAN) Mailbox 13 Flag
-#define AT91C_CAN_MB14            (0x1 << 14) // (CAN) Mailbox 14 Flag
-#define AT91C_CAN_MB15            (0x1 << 15) // (CAN) Mailbox 15 Flag
-#define AT91C_CAN_ERRA            (0x1 << 16) // (CAN) Error Active Mode Flag
-#define AT91C_CAN_WARN            (0x1 << 17) // (CAN) Warning Limit Flag
-#define AT91C_CAN_ERRP            (0x1 << 18) // (CAN) Error Passive Mode Flag
-#define AT91C_CAN_BOFF            (0x1 << 19) // (CAN) Bus Off Mode Flag
-#define AT91C_CAN_SLEEP           (0x1 << 20) // (CAN) Sleep Flag
-#define AT91C_CAN_WAKEUP          (0x1 << 21) // (CAN) Wakeup Flag
-#define AT91C_CAN_TOVF            (0x1 << 22) // (CAN) Timer Overflow Flag
-#define AT91C_CAN_TSTP            (0x1 << 23) // (CAN) Timestamp Flag
-#define AT91C_CAN_CERR            (0x1 << 24) // (CAN) CRC Error
-#define AT91C_CAN_SERR            (0x1 << 25) // (CAN) Stuffing Error
-#define AT91C_CAN_AERR            (0x1 << 26) // (CAN) Acknowledgment Error
-#define AT91C_CAN_FERR            (0x1 << 27) // (CAN) Form Error
-#define AT91C_CAN_BERR            (0x1 << 28) // (CAN) Bit Error
-// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register --------
-// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register --------
-// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register --------
-#define AT91C_CAN_RBSY            (0x1 << 29) // (CAN) Receiver Busy
-#define AT91C_CAN_TBSY            (0x1 << 30) // (CAN) Transmitter Busy
-#define AT91C_CAN_OVLY            (0x1 << 31) // (CAN) Overload Busy
-// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register --------
-#define AT91C_CAN_PHASE2          (0x7 <<  0) // (CAN) Phase 2 segment
-#define AT91C_CAN_PHASE1          (0x7 <<  4) // (CAN) Phase 1 segment
-#define AT91C_CAN_PROPAG          (0x7 <<  8) // (CAN) Programmation time segment
-#define AT91C_CAN_SYNC            (0x3 << 12) // (CAN) Re-synchronization jump width segment
-#define AT91C_CAN_BRP             (0x7F << 16) // (CAN) Baudrate Prescaler
-#define AT91C_CAN_SMP             (0x1 << 24) // (CAN) Sampling mode
-// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register --------
-#define AT91C_CAN_TIMER           (0xFFFF <<  0) // (CAN) Timer field
-// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register --------
-// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register --------
-#define AT91C_CAN_REC             (0xFF <<  0) // (CAN) Receive Error Counter
-#define AT91C_CAN_TEC             (0xFF << 16) // (CAN) Transmit Error Counter
-// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register --------
-#define AT91C_CAN_TIMRST          (0x1 << 31) // (CAN) Timer Reset Field
-// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register --------
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Control Area Network Interface */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_CAN structure *** */
+#define CAN_MR              ( 0 )         /* Mode Register */
+#define CAN_IER             ( 4 )         /* Interrupt Enable Register */
+#define CAN_IDR             ( 8 )         /* Interrupt Disable Register */
+#define CAN_IMR             ( 12 )        /* Interrupt Mask Register */
+#define CAN_SR              ( 16 )        /* Status Register */
+#define CAN_BR              ( 20 )        /* Baudrate Register */
+#define CAN_TIM             ( 24 )        /* Timer Register */
+#define CAN_TIMESTP         ( 28 )        /* Time Stamp Register */
+#define CAN_ECR             ( 32 )        /* Error Counter Register */
+#define CAN_TCR             ( 36 )        /* Transfer Command Register */
+#define CAN_ACR             ( 40 )        /* Abort Command Register */
+#define CAN_VR              ( 252 )       /* Version Register */
+#define CAN_MB0             ( 512 )       /* CAN Mailbox 0 */
+#define CAN_MB1             ( 544 )       /* CAN Mailbox 1 */
+#define CAN_MB2             ( 576 )       /* CAN Mailbox 2 */
+#define CAN_MB3             ( 608 )       /* CAN Mailbox 3 */
+#define CAN_MB4             ( 640 )       /* CAN Mailbox 4 */
+#define CAN_MB5             ( 672 )       /* CAN Mailbox 5 */
+#define CAN_MB6             ( 704 )       /* CAN Mailbox 6 */
+#define CAN_MB7             ( 736 )       /* CAN Mailbox 7 */
+#define CAN_MB8             ( 768 )       /* CAN Mailbox 8 */
+#define CAN_MB9             ( 800 )       /* CAN Mailbox 9 */
+#define CAN_MB10            ( 832 )       /* CAN Mailbox 10 */
+#define CAN_MB11            ( 864 )       /* CAN Mailbox 11 */
+#define CAN_MB12            ( 896 )       /* CAN Mailbox 12 */
+#define CAN_MB13            ( 928 )       /* CAN Mailbox 13 */
+#define CAN_MB14            ( 960 )       /* CAN Mailbox 14 */
+#define CAN_MB15            ( 992 )       /* CAN Mailbox 15 */
+/* -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- */
+#define AT91C_CAN_CANEN     ( 0x1 << 0 )  /* (CAN) CAN Controller Enable */
+#define AT91C_CAN_LPM       ( 0x1 << 1 )  /* (CAN) Disable/Enable Low Power Mode */
+#define AT91C_CAN_ABM       ( 0x1 << 2 )  /* (CAN) Disable/Enable Autobaud/Listen Mode */
+#define AT91C_CAN_OVL       ( 0x1 << 3 )  /* (CAN) Disable/Enable Overload Frame */
+#define AT91C_CAN_TEOF      ( 0x1 << 4 )  /* (CAN) Time Stamp messages at each end of Frame */
+#define AT91C_CAN_TTM       ( 0x1 << 5 )  /* (CAN) Disable/Enable Time Trigger Mode */
+#define AT91C_CAN_TIMFRZ    ( 0x1 << 6 )  /* (CAN) Enable Timer Freeze */
+#define AT91C_CAN_DRPT      ( 0x1 << 7 )  /* (CAN) Disable Repeat */
+/* -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- */
+#define AT91C_CAN_MB0       ( 0x1 << 0 )  /* (CAN) Mailbox 0 Flag */
+#define AT91C_CAN_MB1       ( 0x1 << 1 )  /* (CAN) Mailbox 1 Flag */
+#define AT91C_CAN_MB2       ( 0x1 << 2 )  /* (CAN) Mailbox 2 Flag */
+#define AT91C_CAN_MB3       ( 0x1 << 3 )  /* (CAN) Mailbox 3 Flag */
+#define AT91C_CAN_MB4       ( 0x1 << 4 )  /* (CAN) Mailbox 4 Flag */
+#define AT91C_CAN_MB5       ( 0x1 << 5 )  /* (CAN) Mailbox 5 Flag */
+#define AT91C_CAN_MB6       ( 0x1 << 6 )  /* (CAN) Mailbox 6 Flag */
+#define AT91C_CAN_MB7       ( 0x1 << 7 )  /* (CAN) Mailbox 7 Flag */
+#define AT91C_CAN_MB8       ( 0x1 << 8 )  /* (CAN) Mailbox 8 Flag */
+#define AT91C_CAN_MB9       ( 0x1 << 9 )  /* (CAN) Mailbox 9 Flag */
+#define AT91C_CAN_MB10      ( 0x1 << 10 ) /* (CAN) Mailbox 10 Flag */
+#define AT91C_CAN_MB11      ( 0x1 << 11 ) /* (CAN) Mailbox 11 Flag */
+#define AT91C_CAN_MB12      ( 0x1 << 12 ) /* (CAN) Mailbox 12 Flag */
+#define AT91C_CAN_MB13      ( 0x1 << 13 ) /* (CAN) Mailbox 13 Flag */
+#define AT91C_CAN_MB14      ( 0x1 << 14 ) /* (CAN) Mailbox 14 Flag */
+#define AT91C_CAN_MB15      ( 0x1 << 15 ) /* (CAN) Mailbox 15 Flag */
+#define AT91C_CAN_ERRA      ( 0x1 << 16 ) /* (CAN) Error Active Mode Flag */
+#define AT91C_CAN_WARN      ( 0x1 << 17 ) /* (CAN) Warning Limit Flag */
+#define AT91C_CAN_ERRP      ( 0x1 << 18 ) /* (CAN) Error Passive Mode Flag */
+#define AT91C_CAN_BOFF      ( 0x1 << 19 ) /* (CAN) Bus Off Mode Flag */
+#define AT91C_CAN_SLEEP     ( 0x1 << 20 ) /* (CAN) Sleep Flag */
+#define AT91C_CAN_WAKEUP    ( 0x1 << 21 ) /* (CAN) Wakeup Flag */
+#define AT91C_CAN_TOVF      ( 0x1 << 22 ) /* (CAN) Timer Overflow Flag */
+#define AT91C_CAN_TSTP      ( 0x1 << 23 ) /* (CAN) Timestamp Flag */
+#define AT91C_CAN_CERR      ( 0x1 << 24 ) /* (CAN) CRC Error */
+#define AT91C_CAN_SERR      ( 0x1 << 25 ) /* (CAN) Stuffing Error */
+#define AT91C_CAN_AERR      ( 0x1 << 26 ) /* (CAN) Acknowledgment Error */
+#define AT91C_CAN_FERR      ( 0x1 << 27 ) /* (CAN) Form Error */
+#define AT91C_CAN_BERR      ( 0x1 << 28 ) /* (CAN) Bit Error */
+/* -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- */
+/* -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- */
+/* -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- */
+#define AT91C_CAN_RBSY      ( 0x1 << 29 )     /* (CAN) Receiver Busy */
+#define AT91C_CAN_TBSY      ( 0x1 << 30 )     /* (CAN) Transmitter Busy */
+#define AT91C_CAN_OVLY      ( 0x1 << 31 )     /* (CAN) Overload Busy */
+/* -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- */
+#define AT91C_CAN_PHASE2    ( 0x7 << 0 )      /* (CAN) Phase 2 segment */
+#define AT91C_CAN_PHASE1    ( 0x7 << 4 )      /* (CAN) Phase 1 segment */
+#define AT91C_CAN_PROPAG    ( 0x7 << 8 )      /* (CAN) Programmation time segment */
+#define AT91C_CAN_SYNC      ( 0x3 << 12 )     /* (CAN) Re-synchronization jump width segment */
+#define AT91C_CAN_BRP       ( 0x7F << 16 )    /* (CAN) Baudrate Prescaler */
+#define AT91C_CAN_SMP       ( 0x1 << 24 )     /* (CAN) Sampling mode */
+/* -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- */
+#define AT91C_CAN_TIMER     ( 0xFFFF << 0 )   /* (CAN) Timer field */
+/* -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- */
+/* -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- */
+#define AT91C_CAN_REC       ( 0xFF << 0 )     /* (CAN) Receive Error Counter */
+#define AT91C_CAN_TEC       ( 0xFF << 16 )    /* (CAN) Transmit Error Counter */
+/* -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- */
+#define AT91C_CAN_TIMRST    ( 0x1 << 31 )     /* (CAN) Timer Reset Field */
+/* -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Ethernet MAC 10/100
-// *****************************************************************************
-// *** Register offset in AT91S_EMAC structure ***
-#define EMAC_NCR        ( 0) // Network Control Register
-#define EMAC_NCFGR      ( 4) // Network Configuration Register
-#define EMAC_NSR        ( 8) // Network Status Register
-#define EMAC_TSR        (20) // Transmit Status Register
-#define EMAC_RBQP       (24) // Receive Buffer Queue Pointer
-#define EMAC_TBQP       (28) // Transmit Buffer Queue Pointer
-#define EMAC_RSR        (32) // Receive Status Register
-#define EMAC_ISR        (36) // Interrupt Status Register
-#define EMAC_IER        (40) // Interrupt Enable Register
-#define EMAC_IDR        (44) // Interrupt Disable Register
-#define EMAC_IMR        (48) // Interrupt Mask Register
-#define EMAC_MAN        (52) // PHY Maintenance Register
-#define EMAC_PTR        (56) // Pause Time Register
-#define EMAC_PFR        (60) // Pause Frames received Register
-#define EMAC_FTO        (64) // Frames Transmitted OK Register
-#define EMAC_SCF        (68) // Single Collision Frame Register
-#define EMAC_MCF        (72) // Multiple Collision Frame Register
-#define EMAC_FRO        (76) // Frames Received OK Register
-#define EMAC_FCSE       (80) // Frame Check Sequence Error Register
-#define EMAC_ALE        (84) // Alignment Error Register
-#define EMAC_DTF        (88) // Deferred Transmission Frame Register
-#define EMAC_LCOL       (92) // Late Collision Register
-#define EMAC_ECOL       (96) // Excessive Collision Register
-#define EMAC_TUND       (100) // Transmit Underrun Error Register
-#define EMAC_CSE        (104) // Carrier Sense Error Register
-#define EMAC_RRE        (108) // Receive Ressource Error Register
-#define EMAC_ROV        (112) // Receive Overrun Errors Register
-#define EMAC_RSE        (116) // Receive Symbol Errors Register
-#define EMAC_ELE        (120) // Excessive Length Errors Register
-#define EMAC_RJA        (124) // Receive Jabbers Register
-#define EMAC_USF        (128) // Undersize Frames Register
-#define EMAC_STE        (132) // SQE Test Error Register
-#define EMAC_RLE        (136) // Receive Length Field Mismatch Register
-#define EMAC_TPF        (140) // Transmitted Pause Frames Register
-#define EMAC_HRB        (144) // Hash Address Bottom[31:0]
-#define EMAC_HRT        (148) // Hash Address Top[63:32]
-#define EMAC_SA1L       (152) // Specific Address 1 Bottom, First 4 bytes
-#define EMAC_SA1H       (156) // Specific Address 1 Top, Last 2 bytes
-#define EMAC_SA2L       (160) // Specific Address 2 Bottom, First 4 bytes
-#define EMAC_SA2H       (164) // Specific Address 2 Top, Last 2 bytes
-#define EMAC_SA3L       (168) // Specific Address 3 Bottom, First 4 bytes
-#define EMAC_SA3H       (172) // Specific Address 3 Top, Last 2 bytes
-#define EMAC_SA4L       (176) // Specific Address 4 Bottom, First 4 bytes
-#define EMAC_SA4H       (180) // Specific Address 4 Top, Last 2 bytes
-#define EMAC_TID        (184) // Type ID Checking Register
-#define EMAC_TPQ        (188) // Transmit Pause Quantum Register
-#define EMAC_USRIO      (192) // USER Input/Output Register
-#define EMAC_WOL        (196) // Wake On LAN Register
-#define EMAC_REV        (252) // Revision Register
-// -------- EMAC_NCR : (EMAC Offset: 0x0)  --------
-#define AT91C_EMAC_LB             (0x1 <<  0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
-#define AT91C_EMAC_LLB            (0x1 <<  1) // (EMAC) Loopback local.
-#define AT91C_EMAC_RE             (0x1 <<  2) // (EMAC) Receive enable.
-#define AT91C_EMAC_TE             (0x1 <<  3) // (EMAC) Transmit enable.
-#define AT91C_EMAC_MPE            (0x1 <<  4) // (EMAC) Management port enable.
-#define AT91C_EMAC_CLRSTAT        (0x1 <<  5) // (EMAC) Clear statistics registers.
-#define AT91C_EMAC_INCSTAT        (0x1 <<  6) // (EMAC) Increment statistics registers.
-#define AT91C_EMAC_WESTAT         (0x1 <<  7) // (EMAC) Write enable for statistics registers.
-#define AT91C_EMAC_BP             (0x1 <<  8) // (EMAC) Back pressure.
-#define AT91C_EMAC_TSTART         (0x1 <<  9) // (EMAC) Start Transmission.
-#define AT91C_EMAC_THALT          (0x1 << 10) // (EMAC) Transmission Halt.
-#define AT91C_EMAC_TPFR           (0x1 << 11) // (EMAC) Transmit pause frame
-#define AT91C_EMAC_TZQ            (0x1 << 12) // (EMAC) Transmit zero quantum pause frame
-// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register --------
-#define AT91C_EMAC_SPD            (0x1 <<  0) // (EMAC) Speed.
-#define AT91C_EMAC_FD             (0x1 <<  1) // (EMAC) Full duplex.
-#define AT91C_EMAC_JFRAME         (0x1 <<  3) // (EMAC) Jumbo Frames.
-#define AT91C_EMAC_CAF            (0x1 <<  4) // (EMAC) Copy all frames.
-#define AT91C_EMAC_NBC            (0x1 <<  5) // (EMAC) No broadcast.
-#define AT91C_EMAC_MTI            (0x1 <<  6) // (EMAC) Multicast hash event enable
-#define AT91C_EMAC_UNI            (0x1 <<  7) // (EMAC) Unicast hash enable.
-#define AT91C_EMAC_BIG            (0x1 <<  8) // (EMAC) Receive 1522 bytes.
-#define AT91C_EMAC_EAE            (0x1 <<  9) // (EMAC) External address match enable.
-#define AT91C_EMAC_CLK            (0x3 << 10) // (EMAC)
-#define     AT91C_EMAC_CLK_HCLK_8               (0x0 << 10) // (EMAC) HCLK divided by 8
-#define     AT91C_EMAC_CLK_HCLK_16              (0x1 << 10) // (EMAC) HCLK divided by 16
-#define     AT91C_EMAC_CLK_HCLK_32              (0x2 << 10) // (EMAC) HCLK divided by 32
-#define     AT91C_EMAC_CLK_HCLK_64              (0x3 << 10) // (EMAC) HCLK divided by 64
-#define AT91C_EMAC_RTY            (0x1 << 12) // (EMAC)
-#define AT91C_EMAC_PAE            (0x1 << 13) // (EMAC)
-#define AT91C_EMAC_RBOF           (0x3 << 14) // (EMAC)
-#define     AT91C_EMAC_RBOF_OFFSET_0             (0x0 << 14) // (EMAC) no offset from start of receive buffer
-#define     AT91C_EMAC_RBOF_OFFSET_1             (0x1 << 14) // (EMAC) one byte offset from start of receive buffer
-#define     AT91C_EMAC_RBOF_OFFSET_2             (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
-#define     AT91C_EMAC_RBOF_OFFSET_3             (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
-#define AT91C_EMAC_RLCE           (0x1 << 16) // (EMAC) Receive Length field Checking Enable
-#define AT91C_EMAC_DRFCS          (0x1 << 17) // (EMAC) Discard Receive FCS
-#define AT91C_EMAC_EFRHD          (0x1 << 18) // (EMAC)
-#define AT91C_EMAC_IRXFCS         (0x1 << 19) // (EMAC) Ignore RX FCS
-// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register --------
-#define AT91C_EMAC_LINKR          (0x1 <<  0) // (EMAC)
-#define AT91C_EMAC_MDIO           (0x1 <<  1) // (EMAC)
-#define AT91C_EMAC_IDLE           (0x1 <<  2) // (EMAC)
-// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register --------
-#define AT91C_EMAC_UBR            (0x1 <<  0) // (EMAC)
-#define AT91C_EMAC_COL            (0x1 <<  1) // (EMAC)
-#define AT91C_EMAC_RLES           (0x1 <<  2) // (EMAC)
-#define AT91C_EMAC_TGO            (0x1 <<  3) // (EMAC) Transmit Go
-#define AT91C_EMAC_BEX            (0x1 <<  4) // (EMAC) Buffers exhausted mid frame
-#define AT91C_EMAC_COMP           (0x1 <<  5) // (EMAC)
-#define AT91C_EMAC_UND            (0x1 <<  6) // (EMAC)
-// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register --------
-#define AT91C_EMAC_BNA            (0x1 <<  0) // (EMAC)
-#define AT91C_EMAC_REC            (0x1 <<  1) // (EMAC)
-#define AT91C_EMAC_OVR            (0x1 <<  2) // (EMAC)
-// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register --------
-#define AT91C_EMAC_MFD            (0x1 <<  0) // (EMAC)
-#define AT91C_EMAC_RCOMP          (0x1 <<  1) // (EMAC)
-#define AT91C_EMAC_RXUBR          (0x1 <<  2) // (EMAC)
-#define AT91C_EMAC_TXUBR          (0x1 <<  3) // (EMAC)
-#define AT91C_EMAC_TUNDR          (0x1 <<  4) // (EMAC)
-#define AT91C_EMAC_RLEX           (0x1 <<  5) // (EMAC)
-#define AT91C_EMAC_TXERR          (0x1 <<  6) // (EMAC)
-#define AT91C_EMAC_TCOMP          (0x1 <<  7) // (EMAC)
-#define AT91C_EMAC_LINK           (0x1 <<  9) // (EMAC)
-#define AT91C_EMAC_ROVR           (0x1 << 10) // (EMAC)
-#define AT91C_EMAC_HRESP          (0x1 << 11) // (EMAC)
-#define AT91C_EMAC_PFRE           (0x1 << 12) // (EMAC)
-#define AT91C_EMAC_PTZ            (0x1 << 13) // (EMAC)
-// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register --------
-// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register --------
-// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register --------
-// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register --------
-#define AT91C_EMAC_DATA           (0xFFFF <<  0) // (EMAC)
-#define AT91C_EMAC_CODE           (0x3 << 16) // (EMAC)
-#define AT91C_EMAC_REGA           (0x1F << 18) // (EMAC)
-#define AT91C_EMAC_PHYA           (0x1F << 23) // (EMAC)
-#define AT91C_EMAC_RW             (0x3 << 28) // (EMAC)
-#define AT91C_EMAC_SOF            (0x3 << 30) // (EMAC)
-// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register --------
-#define AT91C_EMAC_RMII           (0x1 <<  0) // (EMAC) Reduce MII
-// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register --------
-#define AT91C_EMAC_IP             (0xFFFF <<  0) // (EMAC) ARP request IP address
-#define AT91C_EMAC_MAG            (0x1 << 16) // (EMAC) Magic packet event enable
-#define AT91C_EMAC_ARP            (0x1 << 17) // (EMAC) ARP request event enable
-#define AT91C_EMAC_SA1            (0x1 << 18) // (EMAC) Specific address register 1 event enable
-// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register --------
-#define AT91C_EMAC_REVREF         (0xFFFF <<  0) // (EMAC)
-#define AT91C_EMAC_PARTREF        (0xFFFF << 16) // (EMAC)
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Ethernet MAC 10/100 */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_EMAC structure *** */
+#define EMAC_NCR                        ( 0 )         /* Network Control Register */
+#define EMAC_NCFGR                      ( 4 )         /* Network Configuration Register */
+#define EMAC_NSR                        ( 8 )         /* Network Status Register */
+#define EMAC_TSR                        ( 20 )        /* Transmit Status Register */
+#define EMAC_RBQP                       ( 24 )        /* Receive Buffer Queue Pointer */
+#define EMAC_TBQP                       ( 28 )        /* Transmit Buffer Queue Pointer */
+#define EMAC_RSR                        ( 32 )        /* Receive Status Register */
+#define EMAC_ISR                        ( 36 )        /* Interrupt Status Register */
+#define EMAC_IER                        ( 40 )        /* Interrupt Enable Register */
+#define EMAC_IDR                        ( 44 )        /* Interrupt Disable Register */
+#define EMAC_IMR                        ( 48 )        /* Interrupt Mask Register */
+#define EMAC_MAN                        ( 52 )        /* PHY Maintenance Register */
+#define EMAC_PTR                        ( 56 )        /* Pause Time Register */
+#define EMAC_PFR                        ( 60 )        /* Pause Frames received Register */
+#define EMAC_FTO                        ( 64 )        /* Frames Transmitted OK Register */
+#define EMAC_SCF                        ( 68 )        /* Single Collision Frame Register */
+#define EMAC_MCF                        ( 72 )        /* Multiple Collision Frame Register */
+#define EMAC_FRO                        ( 76 )        /* Frames Received OK Register */
+#define EMAC_FCSE                       ( 80 )        /* Frame Check Sequence Error Register */
+#define EMAC_ALE                        ( 84 )        /* Alignment Error Register */
+#define EMAC_DTF                        ( 88 )        /* Deferred Transmission Frame Register */
+#define EMAC_LCOL                       ( 92 )        /* Late Collision Register */
+#define EMAC_ECOL                       ( 96 )        /* Excessive Collision Register */
+#define EMAC_TUND                       ( 100 )       /* Transmit Underrun Error Register */
+#define EMAC_CSE                        ( 104 )       /* Carrier Sense Error Register */
+#define EMAC_RRE                        ( 108 )       /* Receive Ressource Error Register */
+#define EMAC_ROV                        ( 112 )       /* Receive Overrun Errors Register */
+#define EMAC_RSE                        ( 116 )       /* Receive Symbol Errors Register */
+#define EMAC_ELE                        ( 120 )       /* Excessive Length Errors Register */
+#define EMAC_RJA                        ( 124 )       /* Receive Jabbers Register */
+#define EMAC_USF                        ( 128 )       /* Undersize Frames Register */
+#define EMAC_STE                        ( 132 )       /* SQE Test Error Register */
+#define EMAC_RLE                        ( 136 )       /* Receive Length Field Mismatch Register */
+#define EMAC_TPF                        ( 140 )       /* Transmitted Pause Frames Register */
+#define EMAC_HRB                        ( 144 )       /* Hash Address Bottom[31:0] */
+#define EMAC_HRT                        ( 148 )       /* Hash Address Top[63:32] */
+#define EMAC_SA1L                       ( 152 )       /* Specific Address 1 Bottom, First 4 bytes */
+#define EMAC_SA1H                       ( 156 )       /* Specific Address 1 Top, Last 2 bytes */
+#define EMAC_SA2L                       ( 160 )       /* Specific Address 2 Bottom, First 4 bytes */
+#define EMAC_SA2H                       ( 164 )       /* Specific Address 2 Top, Last 2 bytes */
+#define EMAC_SA3L                       ( 168 )       /* Specific Address 3 Bottom, First 4 bytes */
+#define EMAC_SA3H                       ( 172 )       /* Specific Address 3 Top, Last 2 bytes */
+#define EMAC_SA4L                       ( 176 )       /* Specific Address 4 Bottom, First 4 bytes */
+#define EMAC_SA4H                       ( 180 )       /* Specific Address 4 Top, Last 2 bytes */
+#define EMAC_TID                        ( 184 )       /* Type ID Checking Register */
+#define EMAC_TPQ                        ( 188 )       /* Transmit Pause Quantum Register */
+#define EMAC_USRIO                      ( 192 )       /* USER Input/Output Register */
+#define EMAC_WOL                        ( 196 )       /* Wake On LAN Register */
+#define EMAC_REV                        ( 252 )       /* Revision Register */
+/* -------- EMAC_NCR : (EMAC Offset: 0x0)  -------- */
+#define AT91C_EMAC_LB                   ( 0x1 << 0 )  /* (EMAC) Loopback. Optional. When set, loopback signal is at high level. */
+#define AT91C_EMAC_LLB                  ( 0x1 << 1 )  /* (EMAC) Loopback local. */
+#define AT91C_EMAC_RE                   ( 0x1 << 2 )  /* (EMAC) Receive enable. */
+#define AT91C_EMAC_TE                   ( 0x1 << 3 )  /* (EMAC) Transmit enable. */
+#define AT91C_EMAC_MPE                  ( 0x1 << 4 )  /* (EMAC) Management port enable. */
+#define AT91C_EMAC_CLRSTAT              ( 0x1 << 5 )  /* (EMAC) Clear statistics registers. */
+#define AT91C_EMAC_INCSTAT              ( 0x1 << 6 )  /* (EMAC) Increment statistics registers. */
+#define AT91C_EMAC_WESTAT               ( 0x1 << 7 )  /* (EMAC) Write enable for statistics registers. */
+#define AT91C_EMAC_BP                   ( 0x1 << 8 )  /* (EMAC) Back pressure. */
+#define AT91C_EMAC_TSTART               ( 0x1 << 9 )  /* (EMAC) Start Transmission. */
+#define AT91C_EMAC_THALT                ( 0x1 << 10 ) /* (EMAC) Transmission Halt. */
+#define AT91C_EMAC_TPFR                 ( 0x1 << 11 ) /* (EMAC) Transmit pause frame */
+#define AT91C_EMAC_TZQ                  ( 0x1 << 12 ) /* (EMAC) Transmit zero quantum pause frame */
+/* -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- */
+#define AT91C_EMAC_SPD                  ( 0x1 << 0 )  /* (EMAC) Speed. */
+#define AT91C_EMAC_FD                   ( 0x1 << 1 )  /* (EMAC) Full duplex. */
+#define AT91C_EMAC_JFRAME               ( 0x1 << 3 )  /* (EMAC) Jumbo Frames. */
+#define AT91C_EMAC_CAF                  ( 0x1 << 4 )  /* (EMAC) Copy all frames. */
+#define AT91C_EMAC_NBC                  ( 0x1 << 5 )  /* (EMAC) No broadcast. */
+#define AT91C_EMAC_MTI                  ( 0x1 << 6 )  /* (EMAC) Multicast hash event enable */
+#define AT91C_EMAC_UNI                  ( 0x1 << 7 )  /* (EMAC) Unicast hash enable. */
+#define AT91C_EMAC_BIG                  ( 0x1 << 8 )  /* (EMAC) Receive 1522 bytes. */
+#define AT91C_EMAC_EAE                  ( 0x1 << 9 )  /* (EMAC) External address match enable. */
+#define AT91C_EMAC_CLK                  ( 0x3 << 10 ) /* (EMAC) */
+#define     AT91C_EMAC_CLK_HCLK_8       ( 0x0 << 10 ) /* (EMAC) HCLK divided by 8 */
+#define     AT91C_EMAC_CLK_HCLK_16      ( 0x1 << 10 ) /* (EMAC) HCLK divided by 16 */
+#define     AT91C_EMAC_CLK_HCLK_32      ( 0x2 << 10 ) /* (EMAC) HCLK divided by 32 */
+#define     AT91C_EMAC_CLK_HCLK_64      ( 0x3 << 10 ) /* (EMAC) HCLK divided by 64 */
+#define AT91C_EMAC_RTY                  ( 0x1 << 12 ) /* (EMAC) */
+#define AT91C_EMAC_PAE                  ( 0x1 << 13 ) /* (EMAC) */
+#define AT91C_EMAC_RBOF                 ( 0x3 << 14 ) /* (EMAC) */
+#define     AT91C_EMAC_RBOF_OFFSET_0    ( 0x0 << 14 ) /* (EMAC) no offset from start of receive buffer */
+#define     AT91C_EMAC_RBOF_OFFSET_1    ( 0x1 << 14 ) /* (EMAC) one byte offset from start of receive buffer */
+#define     AT91C_EMAC_RBOF_OFFSET_2    ( 0x2 << 14 ) /* (EMAC) two bytes offset from start of receive buffer */
+#define     AT91C_EMAC_RBOF_OFFSET_3    ( 0x3 << 14 ) /* (EMAC) three bytes offset from start of receive buffer */
+#define AT91C_EMAC_RLCE                 ( 0x1 << 16 ) /* (EMAC) Receive Length field Checking Enable */
+#define AT91C_EMAC_DRFCS                ( 0x1 << 17 ) /* (EMAC) Discard Receive FCS */
+#define AT91C_EMAC_EFRHD                ( 0x1 << 18 ) /* (EMAC) */
+#define AT91C_EMAC_IRXFCS               ( 0x1 << 19 ) /* (EMAC) Ignore RX FCS */
+/* -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- */
+#define AT91C_EMAC_LINKR                ( 0x1 << 0 )  /* (EMAC) */
+#define AT91C_EMAC_MDIO                 ( 0x1 << 1 )  /* (EMAC) */
+#define AT91C_EMAC_IDLE                 ( 0x1 << 2 )  /* (EMAC) */
+/* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- */
+#define AT91C_EMAC_UBR                  ( 0x1 << 0 )  /* (EMAC) */
+#define AT91C_EMAC_COL                  ( 0x1 << 1 )  /* (EMAC) */
+#define AT91C_EMAC_RLES                 ( 0x1 << 2 )  /* (EMAC) */
+#define AT91C_EMAC_TGO                  ( 0x1 << 3 )  /* (EMAC) Transmit Go */
+#define AT91C_EMAC_BEX                  ( 0x1 << 4 )  /* (EMAC) Buffers exhausted mid frame */
+#define AT91C_EMAC_COMP                 ( 0x1 << 5 )  /* (EMAC) */
+#define AT91C_EMAC_UND                  ( 0x1 << 6 )  /* (EMAC) */
+/* -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- */
+#define AT91C_EMAC_BNA                  ( 0x1 << 0 )  /* (EMAC) */
+#define AT91C_EMAC_REC                  ( 0x1 << 1 )  /* (EMAC) */
+#define AT91C_EMAC_OVR                  ( 0x1 << 2 )  /* (EMAC) */
+/* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- */
+#define AT91C_EMAC_MFD                  ( 0x1 << 0 )  /* (EMAC) */
+#define AT91C_EMAC_RCOMP                ( 0x1 << 1 )  /* (EMAC) */
+#define AT91C_EMAC_RXUBR                ( 0x1 << 2 )  /* (EMAC) */
+#define AT91C_EMAC_TXUBR                ( 0x1 << 3 )  /* (EMAC) */
+#define AT91C_EMAC_TUNDR                ( 0x1 << 4 )  /* (EMAC) */
+#define AT91C_EMAC_RLEX                 ( 0x1 << 5 )  /* (EMAC) */
+#define AT91C_EMAC_TXERR                ( 0x1 << 6 )  /* (EMAC) */
+#define AT91C_EMAC_TCOMP                ( 0x1 << 7 )  /* (EMAC) */
+#define AT91C_EMAC_LINK                 ( 0x1 << 9 )  /* (EMAC) */
+#define AT91C_EMAC_ROVR                 ( 0x1 << 10 ) /* (EMAC) */
+#define AT91C_EMAC_HRESP                ( 0x1 << 11 ) /* (EMAC) */
+#define AT91C_EMAC_PFRE                 ( 0x1 << 12 ) /* (EMAC) */
+#define AT91C_EMAC_PTZ                  ( 0x1 << 13 ) /* (EMAC) */
+/* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- */
+/* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- */
+/* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */
+/* -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- */
+#define AT91C_EMAC_DATA       ( 0xFFFF << 0 )  /* (EMAC) */
+#define AT91C_EMAC_CODE       ( 0x3 << 16 )    /* (EMAC) */
+#define AT91C_EMAC_REGA       ( 0x1F << 18 )   /* (EMAC) */
+#define AT91C_EMAC_PHYA       ( 0x1F << 23 )   /* (EMAC) */
+#define AT91C_EMAC_RW         ( 0x3 << 28 )    /* (EMAC) */
+#define AT91C_EMAC_SOF        ( 0x3 << 30 )    /* (EMAC) */
+/* -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- */
+#define AT91C_EMAC_RMII       ( 0x1 << 0 )     /* (EMAC) Reduce MII */
+/* -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- */
+#define AT91C_EMAC_IP         ( 0xFFFF << 0 )  /* (EMAC) ARP request IP address */
+#define AT91C_EMAC_MAG        ( 0x1 << 16 )    /* (EMAC) Magic packet event enable */
+#define AT91C_EMAC_ARP        ( 0x1 << 17 )    /* (EMAC) ARP request event enable */
+#define AT91C_EMAC_SA1        ( 0x1 << 18 )    /* (EMAC) Specific address register 1 event enable */
+/* -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- */
+#define AT91C_EMAC_REVREF     ( 0xFFFF << 0 )  /* (EMAC) */
+#define AT91C_EMAC_PARTREF    ( 0xFFFF << 16 ) /* (EMAC) */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
-// *****************************************************************************
-// *** Register offset in AT91S_ADC structure ***
-#define ADC_CR          ( 0) // ADC Control Register
-#define ADC_MR          ( 4) // ADC Mode Register
-#define ADC_CHER        (16) // ADC Channel Enable Register
-#define ADC_CHDR        (20) // ADC Channel Disable Register
-#define ADC_CHSR        (24) // ADC Channel Status Register
-#define ADC_SR          (28) // ADC Status Register
-#define ADC_LCDR        (32) // ADC Last Converted Data Register
-#define ADC_IER         (36) // ADC Interrupt Enable Register
-#define ADC_IDR         (40) // ADC Interrupt Disable Register
-#define ADC_IMR         (44) // ADC Interrupt Mask Register
-#define ADC_CDR0        (48) // ADC Channel Data Register 0
-#define ADC_CDR1        (52) // ADC Channel Data Register 1
-#define ADC_CDR2        (56) // ADC Channel Data Register 2
-#define ADC_CDR3        (60) // ADC Channel Data Register 3
-#define ADC_CDR4        (64) // ADC Channel Data Register 4
-#define ADC_CDR5        (68) // ADC Channel Data Register 5
-#define ADC_CDR6        (72) // ADC Channel Data Register 6
-#define ADC_CDR7        (76) // ADC Channel Data Register 7
-#define ADC_RPR         (256) // Receive Pointer Register
-#define ADC_RCR         (260) // Receive Counter Register
-#define ADC_TPR         (264) // Transmit Pointer Register
-#define ADC_TCR         (268) // Transmit Counter Register
-#define ADC_RNPR        (272) // Receive Next Pointer Register
-#define ADC_RNCR        (276) // Receive Next Counter Register
-#define ADC_TNPR        (280) // Transmit Next Pointer Register
-#define ADC_TNCR        (284) // Transmit Next Counter Register
-#define ADC_PTCR        (288) // PDC Transfer Control Register
-#define ADC_PTSR        (292) // PDC Transfer Status Register
-// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
-#define AT91C_ADC_SWRST           (0x1 <<  0) // (ADC) Software Reset
-#define AT91C_ADC_START           (0x1 <<  1) // (ADC) Start Conversion
-// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
-#define AT91C_ADC_TRGEN           (0x1 <<  0) // (ADC) Trigger Enable
-#define     AT91C_ADC_TRGEN_DIS                  (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
-#define     AT91C_ADC_TRGEN_EN                   (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
-#define AT91C_ADC_TRGSEL          (0x7 <<  1) // (ADC) Trigger Selection
-#define     AT91C_ADC_TRGSEL_TIOA0                (0x0 <<  1) // (ADC) Selected TRGSEL = TIAO0
-#define     AT91C_ADC_TRGSEL_TIOA1                (0x1 <<  1) // (ADC) Selected TRGSEL = TIAO1
-#define     AT91C_ADC_TRGSEL_TIOA2                (0x2 <<  1) // (ADC) Selected TRGSEL = TIAO2
-#define     AT91C_ADC_TRGSEL_TIOA3                (0x3 <<  1) // (ADC) Selected TRGSEL = TIAO3
-#define     AT91C_ADC_TRGSEL_TIOA4                (0x4 <<  1) // (ADC) Selected TRGSEL = TIAO4
-#define     AT91C_ADC_TRGSEL_TIOA5                (0x5 <<  1) // (ADC) Selected TRGSEL = TIAO5
-#define     AT91C_ADC_TRGSEL_EXT                  (0x6 <<  1) // (ADC) Selected TRGSEL = External Trigger
-#define AT91C_ADC_LOWRES          (0x1 <<  4) // (ADC) Resolution.
-#define     AT91C_ADC_LOWRES_10_BIT               (0x0 <<  4) // (ADC) 10-bit resolution
-#define     AT91C_ADC_LOWRES_8_BIT                (0x1 <<  4) // (ADC) 8-bit resolution
-#define AT91C_ADC_SLEEP           (0x1 <<  5) // (ADC) Sleep Mode
-#define     AT91C_ADC_SLEEP_NORMAL_MODE          (0x0 <<  5) // (ADC) Normal Mode
-#define     AT91C_ADC_SLEEP_MODE                 (0x1 <<  5) // (ADC) Sleep Mode
-#define AT91C_ADC_PRESCAL         (0x3F <<  8) // (ADC) Prescaler rate selection
-#define AT91C_ADC_STARTUP         (0x1F << 16) // (ADC) Startup Time
-#define AT91C_ADC_SHTIM           (0xF << 24) // (ADC) Sample & Hold Time
-// --------     ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
-#define AT91C_ADC_CH0             (0x1 <<  0) // (ADC) Channel 0
-#define AT91C_ADC_CH1             (0x1 <<  1) // (ADC) Channel 1
-#define AT91C_ADC_CH2             (0x1 <<  2) // (ADC) Channel 2
-#define AT91C_ADC_CH3             (0x1 <<  3) // (ADC) Channel 3
-#define AT91C_ADC_CH4             (0x1 <<  4) // (ADC) Channel 4
-#define AT91C_ADC_CH5             (0x1 <<  5) // (ADC) Channel 5
-#define AT91C_ADC_CH6             (0x1 <<  6) // (ADC) Channel 6
-#define AT91C_ADC_CH7             (0x1 <<  7) // (ADC) Channel 7
-// --------     ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
-// --------     ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
-// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
-#define AT91C_ADC_EOC0            (0x1 <<  0) // (ADC) End of Conversion
-#define AT91C_ADC_EOC1            (0x1 <<  1) // (ADC) End of Conversion
-#define AT91C_ADC_EOC2            (0x1 <<  2) // (ADC) End of Conversion
-#define AT91C_ADC_EOC3            (0x1 <<  3) // (ADC) End of Conversion
-#define AT91C_ADC_EOC4            (0x1 <<  4) // (ADC) End of Conversion
-#define AT91C_ADC_EOC5            (0x1 <<  5) // (ADC) End of Conversion
-#define AT91C_ADC_EOC6            (0x1 <<  6) // (ADC) End of Conversion
-#define AT91C_ADC_EOC7            (0x1 <<  7) // (ADC) End of Conversion
-#define AT91C_ADC_OVRE0           (0x1 <<  8) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE1           (0x1 <<  9) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE2           (0x1 << 10) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE3           (0x1 << 11) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE4           (0x1 << 12) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE5           (0x1 << 13) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE6           (0x1 << 14) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE7           (0x1 << 15) // (ADC) Overrun Error
-#define AT91C_ADC_DRDY            (0x1 << 16) // (ADC) Data Ready
-#define AT91C_ADC_GOVRE           (0x1 << 17) // (ADC) General Overrun
-#define AT91C_ADC_ENDRX           (0x1 << 18) // (ADC) End of Receiver Transfer
-#define AT91C_ADC_RXBUFF          (0x1 << 19) // (ADC) RXBUFF Interrupt
-// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
-#define AT91C_ADC_LDATA           (0x3FF <<  0) // (ADC) Last Data Converted
-// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
-// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
-// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
-// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
-#define AT91C_ADC_DATA            (0x3FF <<  0) // (ADC) Converted Data
-// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
-// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
-// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
-// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
-// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
-// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
-// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_ADC structure *** */
+#define ADC_CR                             ( 0 )          /* ADC Control Register */
+#define ADC_MR                             ( 4 )          /* ADC Mode Register */
+#define ADC_CHER                           ( 16 )         /* ADC Channel Enable Register */
+#define ADC_CHDR                           ( 20 )         /* ADC Channel Disable Register */
+#define ADC_CHSR                           ( 24 )         /* ADC Channel Status Register */
+#define ADC_SR                             ( 28 )         /* ADC Status Register */
+#define ADC_LCDR                           ( 32 )         /* ADC Last Converted Data Register */
+#define ADC_IER                            ( 36 )         /* ADC Interrupt Enable Register */
+#define ADC_IDR                            ( 40 )         /* ADC Interrupt Disable Register */
+#define ADC_IMR                            ( 44 )         /* ADC Interrupt Mask Register */
+#define ADC_CDR0                           ( 48 )         /* ADC Channel Data Register 0 */
+#define ADC_CDR1                           ( 52 )         /* ADC Channel Data Register 1 */
+#define ADC_CDR2                           ( 56 )         /* ADC Channel Data Register 2 */
+#define ADC_CDR3                           ( 60 )         /* ADC Channel Data Register 3 */
+#define ADC_CDR4                           ( 64 )         /* ADC Channel Data Register 4 */
+#define ADC_CDR5                           ( 68 )         /* ADC Channel Data Register 5 */
+#define ADC_CDR6                           ( 72 )         /* ADC Channel Data Register 6 */
+#define ADC_CDR7                           ( 76 )         /* ADC Channel Data Register 7 */
+#define ADC_RPR                            ( 256 )        /* Receive Pointer Register */
+#define ADC_RCR                            ( 260 )        /* Receive Counter Register */
+#define ADC_TPR                            ( 264 )        /* Transmit Pointer Register */
+#define ADC_TCR                            ( 268 )        /* Transmit Counter Register */
+#define ADC_RNPR                           ( 272 )        /* Receive Next Pointer Register */
+#define ADC_RNCR                           ( 276 )        /* Receive Next Counter Register */
+#define ADC_TNPR                           ( 280 )        /* Transmit Next Pointer Register */
+#define ADC_TNCR                           ( 284 )        /* Transmit Next Counter Register */
+#define ADC_PTCR                           ( 288 )        /* PDC Transfer Control Register */
+#define ADC_PTSR                           ( 292 )        /* PDC Transfer Status Register */
+/* -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- */
+#define AT91C_ADC_SWRST                    ( 0x1 << 0 )   /* (ADC) Software Reset */
+#define AT91C_ADC_START                    ( 0x1 << 1 )   /* (ADC) Start Conversion */
+/* -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- */
+#define AT91C_ADC_TRGEN                    ( 0x1 << 0 )   /* (ADC) Trigger Enable */
+#define     AT91C_ADC_TRGEN_DIS            ( 0x0 )        /* (ADC) Hardware triggers are disabled. Starting a conversion is only possible by software */
+#define     AT91C_ADC_TRGEN_EN             ( 0x1 )        /* (ADC) Hardware trigger selected by TRGSEL field is enabled. */
+#define AT91C_ADC_TRGSEL                   ( 0x7 << 1 )   /* (ADC) Trigger Selection */
+#define     AT91C_ADC_TRGSEL_TIOA0         ( 0x0 << 1 )   /* (ADC) Selected TRGSEL = TIAO0 */
+#define     AT91C_ADC_TRGSEL_TIOA1         ( 0x1 << 1 )   /* (ADC) Selected TRGSEL = TIAO1 */
+#define     AT91C_ADC_TRGSEL_TIOA2         ( 0x2 << 1 )   /* (ADC) Selected TRGSEL = TIAO2 */
+#define     AT91C_ADC_TRGSEL_TIOA3         ( 0x3 << 1 )   /* (ADC) Selected TRGSEL = TIAO3 */
+#define     AT91C_ADC_TRGSEL_TIOA4         ( 0x4 << 1 )   /* (ADC) Selected TRGSEL = TIAO4 */
+#define     AT91C_ADC_TRGSEL_TIOA5         ( 0x5 << 1 )   /* (ADC) Selected TRGSEL = TIAO5 */
+#define     AT91C_ADC_TRGSEL_EXT           ( 0x6 << 1 )   /* (ADC) Selected TRGSEL = External Trigger */
+#define AT91C_ADC_LOWRES                   ( 0x1 << 4 )   /* (ADC) Resolution. */
+#define     AT91C_ADC_LOWRES_10_BIT        ( 0x0 << 4 )   /* (ADC) 10-bit resolution */
+#define     AT91C_ADC_LOWRES_8_BIT         ( 0x1 << 4 )   /* (ADC) 8-bit resolution */
+#define AT91C_ADC_SLEEP                    ( 0x1 << 5 )   /* (ADC) Sleep Mode */
+#define     AT91C_ADC_SLEEP_NORMAL_MODE    ( 0x0 << 5 )   /* (ADC) Normal Mode */
+#define     AT91C_ADC_SLEEP_MODE           ( 0x1 << 5 )   /* (ADC) Sleep Mode */
+#define AT91C_ADC_PRESCAL                  ( 0x3F << 8 )  /* (ADC) Prescaler rate selection */
+#define AT91C_ADC_STARTUP                  ( 0x1F << 16 ) /* (ADC) Startup Time */
+#define AT91C_ADC_SHTIM                    ( 0xF << 24 )  /* (ADC) Sample & Hold Time */
+/* --------     ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- */
+#define AT91C_ADC_CH0                      ( 0x1 << 0 )   /* (ADC) Channel 0 */
+#define AT91C_ADC_CH1                      ( 0x1 << 1 )   /* (ADC) Channel 1 */
+#define AT91C_ADC_CH2                      ( 0x1 << 2 )   /* (ADC) Channel 2 */
+#define AT91C_ADC_CH3                      ( 0x1 << 3 )   /* (ADC) Channel 3 */
+#define AT91C_ADC_CH4                      ( 0x1 << 4 )   /* (ADC) Channel 4 */
+#define AT91C_ADC_CH5                      ( 0x1 << 5 )   /* (ADC) Channel 5 */
+#define AT91C_ADC_CH6                      ( 0x1 << 6 )   /* (ADC) Channel 6 */
+#define AT91C_ADC_CH7                      ( 0x1 << 7 )   /* (ADC) Channel 7 */
+/* --------     ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- */
+/* --------     ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- */
+/* -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- */
+#define AT91C_ADC_EOC0      ( 0x1 << 0 )      /* (ADC) End of Conversion */
+#define AT91C_ADC_EOC1      ( 0x1 << 1 )      /* (ADC) End of Conversion */
+#define AT91C_ADC_EOC2      ( 0x1 << 2 )      /* (ADC) End of Conversion */
+#define AT91C_ADC_EOC3      ( 0x1 << 3 )      /* (ADC) End of Conversion */
+#define AT91C_ADC_EOC4      ( 0x1 << 4 )      /* (ADC) End of Conversion */
+#define AT91C_ADC_EOC5      ( 0x1 << 5 )      /* (ADC) End of Conversion */
+#define AT91C_ADC_EOC6      ( 0x1 << 6 )      /* (ADC) End of Conversion */
+#define AT91C_ADC_EOC7      ( 0x1 << 7 )      /* (ADC) End of Conversion */
+#define AT91C_ADC_OVRE0     ( 0x1 << 8 )      /* (ADC) Overrun Error */
+#define AT91C_ADC_OVRE1     ( 0x1 << 9 )      /* (ADC) Overrun Error */
+#define AT91C_ADC_OVRE2     ( 0x1 << 10 )     /* (ADC) Overrun Error */
+#define AT91C_ADC_OVRE3     ( 0x1 << 11 )     /* (ADC) Overrun Error */
+#define AT91C_ADC_OVRE4     ( 0x1 << 12 )     /* (ADC) Overrun Error */
+#define AT91C_ADC_OVRE5     ( 0x1 << 13 )     /* (ADC) Overrun Error */
+#define AT91C_ADC_OVRE6     ( 0x1 << 14 )     /* (ADC) Overrun Error */
+#define AT91C_ADC_OVRE7     ( 0x1 << 15 )     /* (ADC) Overrun Error */
+#define AT91C_ADC_DRDY      ( 0x1 << 16 )     /* (ADC) Data Ready */
+#define AT91C_ADC_GOVRE     ( 0x1 << 17 )     /* (ADC) General Overrun */
+#define AT91C_ADC_ENDRX     ( 0x1 << 18 )     /* (ADC) End of Receiver Transfer */
+#define AT91C_ADC_RXBUFF    ( 0x1 << 19 )     /* (ADC) RXBUFF Interrupt */
+/* -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- */
+#define AT91C_ADC_LDATA     ( 0x3FF << 0 )    /* (ADC) Last Data Converted */
+/* -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- */
+/* -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- */
+/* -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- */
+/* -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- */
+#define AT91C_ADC_DATA    ( 0x3FF << 0 )        /* (ADC) Converted Data */
+/* -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- */
+/* -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- */
+/* -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- */
+/* -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- */
+/* -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- */
+/* -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- */
+/* -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Advanced  Encryption Standard
-// *****************************************************************************
-// *** Register offset in AT91S_AES structure ***
-#define AES_CR          ( 0) // Control Register
-#define AES_MR          ( 4) // Mode Register
-#define AES_IER         (16) // Interrupt Enable Register
-#define AES_IDR         (20) // Interrupt Disable Register
-#define AES_IMR         (24) // Interrupt Mask Register
-#define AES_ISR         (28) // Interrupt Status Register
-#define AES_KEYWxR      (32) // Key Word x Register
-#define AES_IDATAxR     (64) // Input Data x Register
-#define AES_ODATAxR     (80) // Output Data x Register
-#define AES_IVxR        (96) // Initialization Vector x Register
-#define AES_VR          (252) // AES Version Register
-#define AES_RPR         (256) // Receive Pointer Register
-#define AES_RCR         (260) // Receive Counter Register
-#define AES_TPR         (264) // Transmit Pointer Register
-#define AES_TCR         (268) // Transmit Counter Register
-#define AES_RNPR        (272) // Receive Next Pointer Register
-#define AES_RNCR        (276) // Receive Next Counter Register
-#define AES_TNPR        (280) // Transmit Next Pointer Register
-#define AES_TNCR        (284) // Transmit Next Counter Register
-#define AES_PTCR        (288) // PDC Transfer Control Register
-#define AES_PTSR        (292) // PDC Transfer Status Register
-// -------- AES_CR : (AES Offset: 0x0) Control Register --------
-#define AT91C_AES_START           (0x1 <<  0) // (AES) Starts Processing
-#define AT91C_AES_SWRST           (0x1 <<  8) // (AES) Software Reset
-#define AT91C_AES_LOADSEED        (0x1 << 16) // (AES) Random Number Generator Seed Loading
-// -------- AES_MR : (AES Offset: 0x4) Mode Register --------
-#define AT91C_AES_CIPHER          (0x1 <<  0) // (AES) Processing Mode
-#define AT91C_AES_PROCDLY         (0xF <<  4) // (AES) Processing Delay
-#define AT91C_AES_SMOD            (0x3 <<  8) // (AES) Start Mode
-#define     AT91C_AES_SMOD_MANUAL               (0x0 <<  8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.
-#define     AT91C_AES_SMOD_AUTO                 (0x1 <<  8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).
-#define     AT91C_AES_SMOD_PDC                  (0x2 <<  8) // (AES) PDC Mode (cf datasheet).
-#define AT91C_AES_OPMOD           (0x7 << 12) // (AES) Operation Mode
-#define     AT91C_AES_OPMOD_ECB                  (0x0 << 12) // (AES) ECB Electronic CodeBook mode.
-#define     AT91C_AES_OPMOD_CBC                  (0x1 << 12) // (AES) CBC Cipher Block Chaining mode.
-#define     AT91C_AES_OPMOD_OFB                  (0x2 << 12) // (AES) OFB Output Feedback mode.
-#define     AT91C_AES_OPMOD_CFB                  (0x3 << 12) // (AES) CFB Cipher Feedback mode.
-#define     AT91C_AES_OPMOD_CTR                  (0x4 << 12) // (AES) CTR Counter mode.
-#define AT91C_AES_LOD             (0x1 << 15) // (AES) Last Output Data Mode
-#define AT91C_AES_CFBS            (0x7 << 16) // (AES) Cipher Feedback Data Size
-#define     AT91C_AES_CFBS_128_BIT              (0x0 << 16) // (AES) 128-bit.
-#define     AT91C_AES_CFBS_64_BIT               (0x1 << 16) // (AES) 64-bit.
-#define     AT91C_AES_CFBS_32_BIT               (0x2 << 16) // (AES) 32-bit.
-#define     AT91C_AES_CFBS_16_BIT               (0x3 << 16) // (AES) 16-bit.
-#define     AT91C_AES_CFBS_8_BIT                (0x4 << 16) // (AES) 8-bit.
-#define AT91C_AES_CKEY            (0xF << 20) // (AES) Countermeasure Key
-#define AT91C_AES_CTYPE           (0x1F << 24) // (AES) Countermeasure Type
-#define     AT91C_AES_CTYPE_TYPE1_EN             (0x1 << 24) // (AES) Countermeasure type 1 is enabled.
-#define     AT91C_AES_CTYPE_TYPE2_EN             (0x2 << 24) // (AES) Countermeasure type 2 is enabled.
-#define     AT91C_AES_CTYPE_TYPE3_EN             (0x4 << 24) // (AES) Countermeasure type 3 is enabled.
-#define     AT91C_AES_CTYPE_TYPE4_EN             (0x8 << 24) // (AES) Countermeasure type 4 is enabled.
-#define     AT91C_AES_CTYPE_TYPE5_EN             (0x10 << 24) // (AES) Countermeasure type 5 is enabled.
-// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register --------
-#define AT91C_AES_DATRDY          (0x1 <<  0) // (AES) DATRDY
-#define AT91C_AES_ENDRX           (0x1 <<  1) // (AES) PDC Read Buffer End
-#define AT91C_AES_ENDTX           (0x1 <<  2) // (AES) PDC Write Buffer End
-#define AT91C_AES_RXBUFF          (0x1 <<  3) // (AES) PDC Read Buffer Full
-#define AT91C_AES_TXBUFE          (0x1 <<  4) // (AES) PDC Write Buffer Empty
-#define AT91C_AES_URAD            (0x1 <<  8) // (AES) Unspecified Register Access Detection
-// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register --------
-// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register --------
-// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register --------
-#define AT91C_AES_URAT            (0x7 << 12) // (AES) Unspecified Register Access Type Status
-#define     AT91C_AES_URAT_IN_DAT_WRITE_DATPROC (0x0 << 12) // (AES) Input data register written during the data processing in PDC mode.
-#define     AT91C_AES_URAT_OUT_DAT_READ_DATPROC (0x1 << 12) // (AES) Output data register read during the data processing.
-#define     AT91C_AES_URAT_MODEREG_WRITE_DATPROC (0x2 << 12) // (AES) Mode register written during the data processing.
-#define     AT91C_AES_URAT_OUT_DAT_READ_SUBKEY  (0x3 << 12) // (AES) Output data register read during the sub-keys generation.
-#define     AT91C_AES_URAT_MODEREG_WRITE_SUBKEY (0x4 << 12) // (AES) Mode register written during the sub-keys generation.
-#define     AT91C_AES_URAT_WO_REG_READ          (0x5 << 12) // (AES) Write-only register read access.
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Advanced  Encryption Standard */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_AES structure *** */
+#define AES_CR                          ( 0 )          /* Control Register */
+#define AES_MR                          ( 4 )          /* Mode Register */
+#define AES_IER                         ( 16 )         /* Interrupt Enable Register */
+#define AES_IDR                         ( 20 )         /* Interrupt Disable Register */
+#define AES_IMR                         ( 24 )         /* Interrupt Mask Register */
+#define AES_ISR                         ( 28 )         /* Interrupt Status Register */
+#define AES_KEYWxR                      ( 32 )         /* Key Word x Register */
+#define AES_IDATAxR                     ( 64 )         /* Input Data x Register */
+#define AES_ODATAxR                     ( 80 )         /* Output Data x Register */
+#define AES_IVxR                        ( 96 )         /* Initialization Vector x Register */
+#define AES_VR                          ( 252 )        /* AES Version Register */
+#define AES_RPR                         ( 256 )        /* Receive Pointer Register */
+#define AES_RCR                         ( 260 )        /* Receive Counter Register */
+#define AES_TPR                         ( 264 )        /* Transmit Pointer Register */
+#define AES_TCR                         ( 268 )        /* Transmit Counter Register */
+#define AES_RNPR                        ( 272 )        /* Receive Next Pointer Register */
+#define AES_RNCR                        ( 276 )        /* Receive Next Counter Register */
+#define AES_TNPR                        ( 280 )        /* Transmit Next Pointer Register */
+#define AES_TNCR                        ( 284 )        /* Transmit Next Counter Register */
+#define AES_PTCR                        ( 288 )        /* PDC Transfer Control Register */
+#define AES_PTSR                        ( 292 )        /* PDC Transfer Status Register */
+/* -------- AES_CR : (AES Offset: 0x0) Control Register -------- */
+#define AT91C_AES_START                 ( 0x1 << 0 )   /* (AES) Starts Processing */
+#define AT91C_AES_SWRST                 ( 0x1 << 8 )   /* (AES) Software Reset */
+#define AT91C_AES_LOADSEED              ( 0x1 << 16 )  /* (AES) Random Number Generator Seed Loading */
+/* -------- AES_MR : (AES Offset: 0x4) Mode Register -------- */
+#define AT91C_AES_CIPHER                ( 0x1 << 0 )   /* (AES) Processing Mode */
+#define AT91C_AES_PROCDLY               ( 0xF << 4 )   /* (AES) Processing Delay */
+#define AT91C_AES_SMOD                  ( 0x3 << 8 )   /* (AES) Start Mode */
+#define     AT91C_AES_SMOD_MANUAL       ( 0x0 << 8 )   /* (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. */
+#define     AT91C_AES_SMOD_AUTO         ( 0x1 << 8 )   /* (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). */
+#define     AT91C_AES_SMOD_PDC          ( 0x2 << 8 )   /* (AES) PDC Mode (cf datasheet). */
+#define AT91C_AES_OPMOD                 ( 0x7 << 12 )  /* (AES) Operation Mode */
+#define     AT91C_AES_OPMOD_ECB         ( 0x0 << 12 )  /* (AES) ECB Electronic CodeBook mode. */
+#define     AT91C_AES_OPMOD_CBC         ( 0x1 << 12 )  /* (AES) CBC Cipher Block Chaining mode. */
+#define     AT91C_AES_OPMOD_OFB         ( 0x2 << 12 )  /* (AES) OFB Output Feedback mode. */
+#define     AT91C_AES_OPMOD_CFB         ( 0x3 << 12 )  /* (AES) CFB Cipher Feedback mode. */
+#define     AT91C_AES_OPMOD_CTR         ( 0x4 << 12 )  /* (AES) CTR Counter mode. */
+#define AT91C_AES_LOD                   ( 0x1 << 15 )  /* (AES) Last Output Data Mode */
+#define AT91C_AES_CFBS                  ( 0x7 << 16 )  /* (AES) Cipher Feedback Data Size */
+#define     AT91C_AES_CFBS_128_BIT      ( 0x0 << 16 )  /* (AES) 128-bit. */
+#define     AT91C_AES_CFBS_64_BIT       ( 0x1 << 16 )  /* (AES) 64-bit. */
+#define     AT91C_AES_CFBS_32_BIT       ( 0x2 << 16 )  /* (AES) 32-bit. */
+#define     AT91C_AES_CFBS_16_BIT       ( 0x3 << 16 )  /* (AES) 16-bit. */
+#define     AT91C_AES_CFBS_8_BIT        ( 0x4 << 16 )  /* (AES) 8-bit. */
+#define AT91C_AES_CKEY                  ( 0xF << 20 )  /* (AES) Countermeasure Key */
+#define AT91C_AES_CTYPE                 ( 0x1F << 24 ) /* (AES) Countermeasure Type */
+#define     AT91C_AES_CTYPE_TYPE1_EN    ( 0x1 << 24 )  /* (AES) Countermeasure type 1 is enabled. */
+#define     AT91C_AES_CTYPE_TYPE2_EN    ( 0x2 << 24 )  /* (AES) Countermeasure type 2 is enabled. */
+#define     AT91C_AES_CTYPE_TYPE3_EN    ( 0x4 << 24 )  /* (AES) Countermeasure type 3 is enabled. */
+#define     AT91C_AES_CTYPE_TYPE4_EN    ( 0x8 << 24 )  /* (AES) Countermeasure type 4 is enabled. */
+#define     AT91C_AES_CTYPE_TYPE5_EN    ( 0x10 << 24 ) /* (AES) Countermeasure type 5 is enabled. */
+/* -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- */
+#define AT91C_AES_DATRDY                ( 0x1 << 0 )   /* (AES) DATRDY */
+#define AT91C_AES_ENDRX                 ( 0x1 << 1 )   /* (AES) PDC Read Buffer End */
+#define AT91C_AES_ENDTX                 ( 0x1 << 2 )   /* (AES) PDC Write Buffer End */
+#define AT91C_AES_RXBUFF                ( 0x1 << 3 )   /* (AES) PDC Read Buffer Full */
+#define AT91C_AES_TXBUFE                ( 0x1 << 4 )   /* (AES) PDC Write Buffer Empty */
+#define AT91C_AES_URAD                  ( 0x1 << 8 )   /* (AES) Unspecified Register Access Detection */
+/* -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- */
+/* -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- */
+/* -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- */
+#define AT91C_AES_URAT                              ( 0x7 << 12 ) /* (AES) Unspecified Register Access Type Status */
+#define     AT91C_AES_URAT_IN_DAT_WRITE_DATPROC     ( 0x0 << 12 ) /* (AES) Input data register written during the data processing in PDC mode. */
+#define     AT91C_AES_URAT_OUT_DAT_READ_DATPROC     ( 0x1 << 12 ) /* (AES) Output data register read during the data processing. */
+#define     AT91C_AES_URAT_MODEREG_WRITE_DATPROC    ( 0x2 << 12 ) /* (AES) Mode register written during the data processing. */
+#define     AT91C_AES_URAT_OUT_DAT_READ_SUBKEY      ( 0x3 << 12 ) /* (AES) Output data register read during the sub-keys generation. */
+#define     AT91C_AES_URAT_MODEREG_WRITE_SUBKEY     ( 0x4 << 12 ) /* (AES) Mode register written during the sub-keys generation. */
+#define     AT91C_AES_URAT_WO_REG_READ              ( 0x5 << 12 ) /* (AES) Write-only register read access. */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Triple Data Encryption Standard
-// *****************************************************************************
-// *** Register offset in AT91S_TDES structure ***
-#define TDES_CR         ( 0) // Control Register
-#define TDES_MR         ( 4) // Mode Register
-#define TDES_IER        (16) // Interrupt Enable Register
-#define TDES_IDR        (20) // Interrupt Disable Register
-#define TDES_IMR        (24) // Interrupt Mask Register
-#define TDES_ISR        (28) // Interrupt Status Register
-#define TDES_KEY1WxR    (32) // Key 1 Word x Register
-#define TDES_KEY2WxR    (40) // Key 2 Word x Register
-#define TDES_KEY3WxR    (48) // Key 3 Word x Register
-#define TDES_IDATAxR    (64) // Input Data x Register
-#define TDES_ODATAxR    (80) // Output Data x Register
-#define TDES_IVxR       (96) // Initialization Vector x Register
-#define TDES_VR         (252) // TDES Version Register
-#define TDES_RPR        (256) // Receive Pointer Register
-#define TDES_RCR        (260) // Receive Counter Register
-#define TDES_TPR        (264) // Transmit Pointer Register
-#define TDES_TCR        (268) // Transmit Counter Register
-#define TDES_RNPR       (272) // Receive Next Pointer Register
-#define TDES_RNCR       (276) // Receive Next Counter Register
-#define TDES_TNPR       (280) // Transmit Next Pointer Register
-#define TDES_TNCR       (284) // Transmit Next Counter Register
-#define TDES_PTCR       (288) // PDC Transfer Control Register
-#define TDES_PTSR       (292) // PDC Transfer Status Register
-// -------- TDES_CR : (TDES Offset: 0x0) Control Register --------
-#define AT91C_TDES_START          (0x1 <<  0) // (TDES) Starts Processing
-#define AT91C_TDES_SWRST          (0x1 <<  8) // (TDES) Software Reset
-// -------- TDES_MR : (TDES Offset: 0x4) Mode Register --------
-#define AT91C_TDES_CIPHER         (0x1 <<  0) // (TDES) Processing Mode
-#define AT91C_TDES_TDESMOD        (0x1 <<  1) // (TDES) Single or Triple DES Mode
-#define AT91C_TDES_KEYMOD         (0x1 <<  4) // (TDES) Key Mode
-#define AT91C_TDES_SMOD           (0x3 <<  8) // (TDES) Start Mode
-#define     AT91C_TDES_SMOD_MANUAL               (0x0 <<  8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.
-#define     AT91C_TDES_SMOD_AUTO                 (0x1 <<  8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).
-#define     AT91C_TDES_SMOD_PDC                  (0x2 <<  8) // (TDES) PDC Mode (cf datasheet).
-#define AT91C_TDES_OPMOD          (0x3 << 12) // (TDES) Operation Mode
-#define     AT91C_TDES_OPMOD_ECB                  (0x0 << 12) // (TDES) ECB Electronic CodeBook mode.
-#define     AT91C_TDES_OPMOD_CBC                  (0x1 << 12) // (TDES) CBC Cipher Block Chaining mode.
-#define     AT91C_TDES_OPMOD_OFB                  (0x2 << 12) // (TDES) OFB Output Feedback mode.
-#define     AT91C_TDES_OPMOD_CFB                  (0x3 << 12) // (TDES) CFB Cipher Feedback mode.
-#define AT91C_TDES_LOD            (0x1 << 15) // (TDES) Last Output Data Mode
-#define AT91C_TDES_CFBS           (0x3 << 16) // (TDES) Cipher Feedback Data Size
-#define     AT91C_TDES_CFBS_64_BIT               (0x0 << 16) // (TDES) 64-bit.
-#define     AT91C_TDES_CFBS_32_BIT               (0x1 << 16) // (TDES) 32-bit.
-#define     AT91C_TDES_CFBS_16_BIT               (0x2 << 16) // (TDES) 16-bit.
-#define     AT91C_TDES_CFBS_8_BIT                (0x3 << 16) // (TDES) 8-bit.
-// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register --------
-#define AT91C_TDES_DATRDY         (0x1 <<  0) // (TDES) DATRDY
-#define AT91C_TDES_ENDRX          (0x1 <<  1) // (TDES) PDC Read Buffer End
-#define AT91C_TDES_ENDTX          (0x1 <<  2) // (TDES) PDC Write Buffer End
-#define AT91C_TDES_RXBUFF         (0x1 <<  3) // (TDES) PDC Read Buffer Full
-#define AT91C_TDES_TXBUFE         (0x1 <<  4) // (TDES) PDC Write Buffer Empty
-#define AT91C_TDES_URAD           (0x1 <<  8) // (TDES) Unspecified Register Access Detection
-// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register --------
-// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register --------
-// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register --------
-#define AT91C_TDES_URAT           (0x3 << 12) // (TDES) Unspecified Register Access Type Status
-#define     AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC (0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode.
-#define     AT91C_TDES_URAT_OUT_DAT_READ_DATPROC (0x1 << 12) // (TDES) Output data register read during the data processing.
-#define     AT91C_TDES_URAT_MODEREG_WRITE_DATPROC (0x2 << 12) // (TDES) Mode register written during the data processing.
-#define     AT91C_TDES_URAT_WO_REG_READ          (0x3 << 12) // (TDES) Write-only register read access.
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Triple Data Encryption Standard */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_TDES structure *** */
+#define TDES_CR                       ( 0 )         /* Control Register */
+#define TDES_MR                       ( 4 )         /* Mode Register */
+#define TDES_IER                      ( 16 )        /* Interrupt Enable Register */
+#define TDES_IDR                      ( 20 )        /* Interrupt Disable Register */
+#define TDES_IMR                      ( 24 )        /* Interrupt Mask Register */
+#define TDES_ISR                      ( 28 )        /* Interrupt Status Register */
+#define TDES_KEY1WxR                  ( 32 )        /* Key 1 Word x Register */
+#define TDES_KEY2WxR                  ( 40 )        /* Key 2 Word x Register */
+#define TDES_KEY3WxR                  ( 48 )        /* Key 3 Word x Register */
+#define TDES_IDATAxR                  ( 64 )        /* Input Data x Register */
+#define TDES_ODATAxR                  ( 80 )        /* Output Data x Register */
+#define TDES_IVxR                     ( 96 )        /* Initialization Vector x Register */
+#define TDES_VR                       ( 252 )       /* TDES Version Register */
+#define TDES_RPR                      ( 256 )       /* Receive Pointer Register */
+#define TDES_RCR                      ( 260 )       /* Receive Counter Register */
+#define TDES_TPR                      ( 264 )       /* Transmit Pointer Register */
+#define TDES_TCR                      ( 268 )       /* Transmit Counter Register */
+#define TDES_RNPR                     ( 272 )       /* Receive Next Pointer Register */
+#define TDES_RNCR                     ( 276 )       /* Receive Next Counter Register */
+#define TDES_TNPR                     ( 280 )       /* Transmit Next Pointer Register */
+#define TDES_TNCR                     ( 284 )       /* Transmit Next Counter Register */
+#define TDES_PTCR                     ( 288 )       /* PDC Transfer Control Register */
+#define TDES_PTSR                     ( 292 )       /* PDC Transfer Status Register */
+/* -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- */
+#define AT91C_TDES_START              ( 0x1 << 0 )  /* (TDES) Starts Processing */
+#define AT91C_TDES_SWRST              ( 0x1 << 8 )  /* (TDES) Software Reset */
+/* -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- */
+#define AT91C_TDES_CIPHER             ( 0x1 << 0 )  /* (TDES) Processing Mode */
+#define AT91C_TDES_TDESMOD            ( 0x1 << 1 )  /* (TDES) Single or Triple DES Mode */
+#define AT91C_TDES_KEYMOD             ( 0x1 << 4 )  /* (TDES) Key Mode */
+#define AT91C_TDES_SMOD               ( 0x3 << 8 )  /* (TDES) Start Mode */
+#define     AT91C_TDES_SMOD_MANUAL    ( 0x0 << 8 )  /* (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. */
+#define     AT91C_TDES_SMOD_AUTO      ( 0x1 << 8 )  /* (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). */
+#define     AT91C_TDES_SMOD_PDC       ( 0x2 << 8 )  /* (TDES) PDC Mode (cf datasheet). */
+#define AT91C_TDES_OPMOD              ( 0x3 << 12 ) /* (TDES) Operation Mode */
+#define     AT91C_TDES_OPMOD_ECB      ( 0x0 << 12 ) /* (TDES) ECB Electronic CodeBook mode. */
+#define     AT91C_TDES_OPMOD_CBC      ( 0x1 << 12 ) /* (TDES) CBC Cipher Block Chaining mode. */
+#define     AT91C_TDES_OPMOD_OFB      ( 0x2 << 12 ) /* (TDES) OFB Output Feedback mode. */
+#define     AT91C_TDES_OPMOD_CFB      ( 0x3 << 12 ) /* (TDES) CFB Cipher Feedback mode. */
+#define AT91C_TDES_LOD                ( 0x1 << 15 ) /* (TDES) Last Output Data Mode */
+#define AT91C_TDES_CFBS               ( 0x3 << 16 ) /* (TDES) Cipher Feedback Data Size */
+#define     AT91C_TDES_CFBS_64_BIT    ( 0x0 << 16 ) /* (TDES) 64-bit. */
+#define     AT91C_TDES_CFBS_32_BIT    ( 0x1 << 16 ) /* (TDES) 32-bit. */
+#define     AT91C_TDES_CFBS_16_BIT    ( 0x2 << 16 ) /* (TDES) 16-bit. */
+#define     AT91C_TDES_CFBS_8_BIT     ( 0x3 << 16 ) /* (TDES) 8-bit. */
+/* -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- */
+#define AT91C_TDES_DATRDY             ( 0x1 << 0 )  /* (TDES) DATRDY */
+#define AT91C_TDES_ENDRX              ( 0x1 << 1 )  /* (TDES) PDC Read Buffer End */
+#define AT91C_TDES_ENDTX              ( 0x1 << 2 )  /* (TDES) PDC Write Buffer End */
+#define AT91C_TDES_RXBUFF             ( 0x1 << 3 )  /* (TDES) PDC Read Buffer Full */
+#define AT91C_TDES_TXBUFE             ( 0x1 << 4 )  /* (TDES) PDC Write Buffer Empty */
+#define AT91C_TDES_URAD               ( 0x1 << 8 )  /* (TDES) Unspecified Register Access Detection */
+/* -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- */
+/* -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- */
+/* -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- */
+#define AT91C_TDES_URAT                              ( 0x3 << 12 ) /* (TDES) Unspecified Register Access Type Status */
+#define     AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC     ( 0x0 << 12 ) /* (TDES) Input data register written during the data processing in PDC mode. */
+#define     AT91C_TDES_URAT_OUT_DAT_READ_DATPROC     ( 0x1 << 12 ) /* (TDES) Output data register read during the data processing. */
+#define     AT91C_TDES_URAT_MODEREG_WRITE_DATPROC    ( 0x2 << 12 ) /* (TDES) Mode register written during the data processing. */
+#define     AT91C_TDES_URAT_WO_REG_READ              ( 0x3 << 12 ) /* (TDES) Write-only register read access. */
 
-// *****************************************************************************
-//               REGISTER ADDRESS DEFINITION FOR AT91SAM7X128
-// *****************************************************************************
-// ========== Register definition for SYS peripheral ==========
-// ========== Register definition for AIC peripheral ==========
-#define AT91C_AIC_IVR             (0xFFFFF100) // (AIC) IRQ Vector Register
-#define AT91C_AIC_SMR             (0xFFFFF000) // (AIC) Source Mode Register
-#define AT91C_AIC_FVR             (0xFFFFF104) // (AIC) FIQ Vector Register
-#define AT91C_AIC_DCR             (0xFFFFF138) // (AIC) Debug Control Register (Protect)
-#define AT91C_AIC_EOICR           (0xFFFFF130) // (AIC) End of Interrupt Command Register
-#define AT91C_AIC_SVR             (0xFFFFF080) // (AIC) Source Vector Register
-#define AT91C_AIC_FFSR            (0xFFFFF148) // (AIC) Fast Forcing Status Register
-#define AT91C_AIC_ICCR            (0xFFFFF128) // (AIC) Interrupt Clear Command Register
-#define AT91C_AIC_ISR             (0xFFFFF108) // (AIC) Interrupt Status Register
-#define AT91C_AIC_IMR             (0xFFFFF110) // (AIC) Interrupt Mask Register
-#define AT91C_AIC_IPR             (0xFFFFF10C) // (AIC) Interrupt Pending Register
-#define AT91C_AIC_FFER            (0xFFFFF140) // (AIC) Fast Forcing Enable Register
-#define AT91C_AIC_IECR            (0xFFFFF120) // (AIC) Interrupt Enable Command Register
-#define AT91C_AIC_ISCR            (0xFFFFF12C) // (AIC) Interrupt Set Command Register
-#define AT91C_AIC_FFDR            (0xFFFFF144) // (AIC) Fast Forcing Disable Register
-#define AT91C_AIC_CISR            (0xFFFFF114) // (AIC) Core Interrupt Status Register
-#define AT91C_AIC_IDCR            (0xFFFFF124) // (AIC) Interrupt Disable Command Register
-#define AT91C_AIC_SPU             (0xFFFFF134) // (AIC) Spurious Vector Register
-// ========== Register definition for PDC_DBGU peripheral ==========
-#define AT91C_DBGU_TCR            (0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
-#define AT91C_DBGU_RNPR           (0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
-#define AT91C_DBGU_TNPR           (0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
-#define AT91C_DBGU_TPR            (0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
-#define AT91C_DBGU_RPR            (0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
-#define AT91C_DBGU_RCR            (0xFFFFF304) // (PDC_DBGU) Receive Counter Register
-#define AT91C_DBGU_RNCR           (0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
-#define AT91C_DBGU_PTCR           (0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
-#define AT91C_DBGU_PTSR           (0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
-#define AT91C_DBGU_TNCR           (0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
-// ========== Register definition for DBGU peripheral ==========
-#define AT91C_DBGU_EXID           (0xFFFFF244) // (DBGU) Chip ID Extension Register
-#define AT91C_DBGU_BRGR           (0xFFFFF220) // (DBGU) Baud Rate Generator Register
-#define AT91C_DBGU_IDR            (0xFFFFF20C) // (DBGU) Interrupt Disable Register
-#define AT91C_DBGU_CSR            (0xFFFFF214) // (DBGU) Channel Status Register
-#define AT91C_DBGU_CIDR           (0xFFFFF240) // (DBGU) Chip ID Register
-#define AT91C_DBGU_MR             (0xFFFFF204) // (DBGU) Mode Register
-#define AT91C_DBGU_IMR            (0xFFFFF210) // (DBGU) Interrupt Mask Register
-#define AT91C_DBGU_CR             (0xFFFFF200) // (DBGU) Control Register
-#define AT91C_DBGU_FNTR           (0xFFFFF248) // (DBGU) Force NTRST Register
-#define AT91C_DBGU_THR            (0xFFFFF21C) // (DBGU) Transmitter Holding Register
-#define AT91C_DBGU_RHR            (0xFFFFF218) // (DBGU) Receiver Holding Register
-#define AT91C_DBGU_IER            (0xFFFFF208) // (DBGU) Interrupt Enable Register
-// ========== Register definition for PIOA peripheral ==========
-#define AT91C_PIOA_ODR            (0xFFFFF414) // (PIOA) Output Disable Registerr
-#define AT91C_PIOA_SODR           (0xFFFFF430) // (PIOA) Set Output Data Register
-#define AT91C_PIOA_ISR            (0xFFFFF44C) // (PIOA) Interrupt Status Register
-#define AT91C_PIOA_ABSR           (0xFFFFF478) // (PIOA) AB Select Status Register
-#define AT91C_PIOA_IER            (0xFFFFF440) // (PIOA) Interrupt Enable Register
-#define AT91C_PIOA_PPUDR          (0xFFFFF460) // (PIOA) Pull-up Disable Register
-#define AT91C_PIOA_IMR            (0xFFFFF448) // (PIOA) Interrupt Mask Register
-#define AT91C_PIOA_PER            (0xFFFFF400) // (PIOA) PIO Enable Register
-#define AT91C_PIOA_IFDR           (0xFFFFF424) // (PIOA) Input Filter Disable Register
-#define AT91C_PIOA_OWDR           (0xFFFFF4A4) // (PIOA) Output Write Disable Register
-#define AT91C_PIOA_MDSR           (0xFFFFF458) // (PIOA) Multi-driver Status Register
-#define AT91C_PIOA_IDR            (0xFFFFF444) // (PIOA) Interrupt Disable Register
-#define AT91C_PIOA_ODSR           (0xFFFFF438) // (PIOA) Output Data Status Register
-#define AT91C_PIOA_PPUSR          (0xFFFFF468) // (PIOA) Pull-up Status Register
-#define AT91C_PIOA_OWSR           (0xFFFFF4A8) // (PIOA) Output Write Status Register
-#define AT91C_PIOA_BSR            (0xFFFFF474) // (PIOA) Select B Register
-#define AT91C_PIOA_OWER           (0xFFFFF4A0) // (PIOA) Output Write Enable Register
-#define AT91C_PIOA_IFER           (0xFFFFF420) // (PIOA) Input Filter Enable Register
-#define AT91C_PIOA_PDSR           (0xFFFFF43C) // (PIOA) Pin Data Status Register
-#define AT91C_PIOA_PPUER          (0xFFFFF464) // (PIOA) Pull-up Enable Register
-#define AT91C_PIOA_OSR            (0xFFFFF418) // (PIOA) Output Status Register
-#define AT91C_PIOA_ASR            (0xFFFFF470) // (PIOA) Select A Register
-#define AT91C_PIOA_MDDR           (0xFFFFF454) // (PIOA) Multi-driver Disable Register
-#define AT91C_PIOA_CODR           (0xFFFFF434) // (PIOA) Clear Output Data Register
-#define AT91C_PIOA_MDER           (0xFFFFF450) // (PIOA) Multi-driver Enable Register
-#define AT91C_PIOA_PDR            (0xFFFFF404) // (PIOA) PIO Disable Register
-#define AT91C_PIOA_IFSR           (0xFFFFF428) // (PIOA) Input Filter Status Register
-#define AT91C_PIOA_OER            (0xFFFFF410) // (PIOA) Output Enable Register
-#define AT91C_PIOA_PSR            (0xFFFFF408) // (PIOA) PIO Status Register
-// ========== Register definition for PIOB peripheral ==========
-#define AT91C_PIOB_OWDR           (0xFFFFF6A4) // (PIOB) Output Write Disable Register
-#define AT91C_PIOB_MDER           (0xFFFFF650) // (PIOB) Multi-driver Enable Register
-#define AT91C_PIOB_PPUSR          (0xFFFFF668) // (PIOB) Pull-up Status Register
-#define AT91C_PIOB_IMR            (0xFFFFF648) // (PIOB) Interrupt Mask Register
-#define AT91C_PIOB_ASR            (0xFFFFF670) // (PIOB) Select A Register
-#define AT91C_PIOB_PPUDR          (0xFFFFF660) // (PIOB) Pull-up Disable Register
-#define AT91C_PIOB_PSR            (0xFFFFF608) // (PIOB) PIO Status Register
-#define AT91C_PIOB_IER            (0xFFFFF640) // (PIOB) Interrupt Enable Register
-#define AT91C_PIOB_CODR           (0xFFFFF634) // (PIOB) Clear Output Data Register
-#define AT91C_PIOB_OWER           (0xFFFFF6A0) // (PIOB) Output Write Enable Register
-#define AT91C_PIOB_ABSR           (0xFFFFF678) // (PIOB) AB Select Status Register
-#define AT91C_PIOB_IFDR           (0xFFFFF624) // (PIOB) Input Filter Disable Register
-#define AT91C_PIOB_PDSR           (0xFFFFF63C) // (PIOB) Pin Data Status Register
-#define AT91C_PIOB_IDR            (0xFFFFF644) // (PIOB) Interrupt Disable Register
-#define AT91C_PIOB_OWSR           (0xFFFFF6A8) // (PIOB) Output Write Status Register
-#define AT91C_PIOB_PDR            (0xFFFFF604) // (PIOB) PIO Disable Register
-#define AT91C_PIOB_ODR            (0xFFFFF614) // (PIOB) Output Disable Registerr
-#define AT91C_PIOB_IFSR           (0xFFFFF628) // (PIOB) Input Filter Status Register
-#define AT91C_PIOB_PPUER          (0xFFFFF664) // (PIOB) Pull-up Enable Register
-#define AT91C_PIOB_SODR           (0xFFFFF630) // (PIOB) Set Output Data Register
-#define AT91C_PIOB_ISR            (0xFFFFF64C) // (PIOB) Interrupt Status Register
-#define AT91C_PIOB_ODSR           (0xFFFFF638) // (PIOB) Output Data Status Register
-#define AT91C_PIOB_OSR            (0xFFFFF618) // (PIOB) Output Status Register
-#define AT91C_PIOB_MDSR           (0xFFFFF658) // (PIOB) Multi-driver Status Register
-#define AT91C_PIOB_IFER           (0xFFFFF620) // (PIOB) Input Filter Enable Register
-#define AT91C_PIOB_BSR            (0xFFFFF674) // (PIOB) Select B Register
-#define AT91C_PIOB_MDDR           (0xFFFFF654) // (PIOB) Multi-driver Disable Register
-#define AT91C_PIOB_OER            (0xFFFFF610) // (PIOB) Output Enable Register
-#define AT91C_PIOB_PER            (0xFFFFF600) // (PIOB) PIO Enable Register
-// ========== Register definition for CKGR peripheral ==========
-#define AT91C_CKGR_MOR            (0xFFFFFC20) // (CKGR) Main Oscillator Register
-#define AT91C_CKGR_PLLR           (0xFFFFFC2C) // (CKGR) PLL Register
-#define AT91C_CKGR_MCFR           (0xFFFFFC24) // (CKGR) Main Clock  Frequency Register
-// ========== Register definition for PMC peripheral ==========
-#define AT91C_PMC_IDR             (0xFFFFFC64) // (PMC) Interrupt Disable Register
-#define AT91C_PMC_MOR             (0xFFFFFC20) // (PMC) Main Oscillator Register
-#define AT91C_PMC_PLLR            (0xFFFFFC2C) // (PMC) PLL Register
-#define AT91C_PMC_PCER            (0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
-#define AT91C_PMC_PCKR            (0xFFFFFC40) // (PMC) Programmable Clock Register
-#define AT91C_PMC_MCKR            (0xFFFFFC30) // (PMC) Master Clock Register
-#define AT91C_PMC_SCDR            (0xFFFFFC04) // (PMC) System Clock Disable Register
-#define AT91C_PMC_PCDR            (0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
-#define AT91C_PMC_SCSR            (0xFFFFFC08) // (PMC) System Clock Status Register
-#define AT91C_PMC_PCSR            (0xFFFFFC18) // (PMC) Peripheral Clock Status Register
-#define AT91C_PMC_MCFR            (0xFFFFFC24) // (PMC) Main Clock  Frequency Register
-#define AT91C_PMC_SCER            (0xFFFFFC00) // (PMC) System Clock Enable Register
-#define AT91C_PMC_IMR             (0xFFFFFC6C) // (PMC) Interrupt Mask Register
-#define AT91C_PMC_IER             (0xFFFFFC60) // (PMC) Interrupt Enable Register
-#define AT91C_PMC_SR              (0xFFFFFC68) // (PMC) Status Register
-// ========== Register definition for RSTC peripheral ==========
-#define AT91C_RSTC_RCR            (0xFFFFFD00) // (RSTC) Reset Control Register
-#define AT91C_RSTC_RMR            (0xFFFFFD08) // (RSTC) Reset Mode Register
-#define AT91C_RSTC_RSR            (0xFFFFFD04) // (RSTC) Reset Status Register
-// ========== Register definition for RTTC peripheral ==========
-#define AT91C_RTTC_RTSR           (0xFFFFFD2C) // (RTTC) Real-time Status Register
-#define AT91C_RTTC_RTMR           (0xFFFFFD20) // (RTTC) Real-time Mode Register
-#define AT91C_RTTC_RTVR           (0xFFFFFD28) // (RTTC) Real-time Value Register
-#define AT91C_RTTC_RTAR           (0xFFFFFD24) // (RTTC) Real-time Alarm Register
-// ========== Register definition for PITC peripheral ==========
-#define AT91C_PITC_PIVR           (0xFFFFFD38) // (PITC) Period Interval Value Register
-#define AT91C_PITC_PISR           (0xFFFFFD34) // (PITC) Period Interval Status Register
-#define AT91C_PITC_PIIR           (0xFFFFFD3C) // (PITC) Period Interval Image Register
-#define AT91C_PITC_PIMR           (0xFFFFFD30) // (PITC) Period Interval Mode Register
-// ========== Register definition for WDTC peripheral ==========
-#define AT91C_WDTC_WDCR           (0xFFFFFD40) // (WDTC) Watchdog Control Register
-#define AT91C_WDTC_WDSR           (0xFFFFFD48) // (WDTC) Watchdog Status Register
-#define AT91C_WDTC_WDMR           (0xFFFFFD44) // (WDTC) Watchdog Mode Register
-// ========== Register definition for VREG peripheral ==========
-#define AT91C_VREG_MR             (0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
-// ========== Register definition for MC peripheral ==========
-#define AT91C_MC_ASR              (0xFFFFFF04) // (MC) MC Abort Status Register
-#define AT91C_MC_RCR              (0xFFFFFF00) // (MC) MC Remap Control Register
-#define AT91C_MC_FCR              (0xFFFFFF64) // (MC) MC Flash Command Register
-#define AT91C_MC_AASR             (0xFFFFFF08) // (MC) MC Abort Address Status Register
-#define AT91C_MC_FSR              (0xFFFFFF68) // (MC) MC Flash Status Register
-#define AT91C_MC_FMR              (0xFFFFFF60) // (MC) MC Flash Mode Register
-// ========== Register definition for PDC_SPI1 peripheral ==========
-#define AT91C_SPI1_PTCR           (0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register
-#define AT91C_SPI1_RPR            (0xFFFE4100) // (PDC_SPI1) Receive Pointer Register
-#define AT91C_SPI1_TNCR           (0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register
-#define AT91C_SPI1_TPR            (0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register
-#define AT91C_SPI1_TNPR           (0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register
-#define AT91C_SPI1_TCR            (0xFFFE410C) // (PDC_SPI1) Transmit Counter Register
-#define AT91C_SPI1_RCR            (0xFFFE4104) // (PDC_SPI1) Receive Counter Register
-#define AT91C_SPI1_RNPR           (0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register
-#define AT91C_SPI1_RNCR           (0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register
-#define AT91C_SPI1_PTSR           (0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register
-// ========== Register definition for SPI1 peripheral ==========
-#define AT91C_SPI1_IMR            (0xFFFE401C) // (SPI1) Interrupt Mask Register
-#define AT91C_SPI1_IER            (0xFFFE4014) // (SPI1) Interrupt Enable Register
-#define AT91C_SPI1_MR             (0xFFFE4004) // (SPI1) Mode Register
-#define AT91C_SPI1_RDR            (0xFFFE4008) // (SPI1) Receive Data Register
-#define AT91C_SPI1_IDR            (0xFFFE4018) // (SPI1) Interrupt Disable Register
-#define AT91C_SPI1_SR             (0xFFFE4010) // (SPI1) Status Register
-#define AT91C_SPI1_TDR            (0xFFFE400C) // (SPI1) Transmit Data Register
-#define AT91C_SPI1_CR             (0xFFFE4000) // (SPI1) Control Register
-#define AT91C_SPI1_CSR            (0xFFFE4030) // (SPI1) Chip Select Register
-// ========== Register definition for PDC_SPI0 peripheral ==========
-#define AT91C_SPI0_PTCR           (0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register
-#define AT91C_SPI0_TPR            (0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register
-#define AT91C_SPI0_TCR            (0xFFFE010C) // (PDC_SPI0) Transmit Counter Register
-#define AT91C_SPI0_RCR            (0xFFFE0104) // (PDC_SPI0) Receive Counter Register
-#define AT91C_SPI0_PTSR           (0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register
-#define AT91C_SPI0_RNPR           (0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register
-#define AT91C_SPI0_RPR            (0xFFFE0100) // (PDC_SPI0) Receive Pointer Register
-#define AT91C_SPI0_TNCR           (0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register
-#define AT91C_SPI0_RNCR           (0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register
-#define AT91C_SPI0_TNPR           (0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register
-// ========== Register definition for SPI0 peripheral ==========
-#define AT91C_SPI0_IER            (0xFFFE0014) // (SPI0) Interrupt Enable Register
-#define AT91C_SPI0_SR             (0xFFFE0010) // (SPI0) Status Register
-#define AT91C_SPI0_IDR            (0xFFFE0018) // (SPI0) Interrupt Disable Register
-#define AT91C_SPI0_CR             (0xFFFE0000) // (SPI0) Control Register
-#define AT91C_SPI0_MR             (0xFFFE0004) // (SPI0) Mode Register
-#define AT91C_SPI0_IMR            (0xFFFE001C) // (SPI0) Interrupt Mask Register
-#define AT91C_SPI0_TDR            (0xFFFE000C) // (SPI0) Transmit Data Register
-#define AT91C_SPI0_RDR            (0xFFFE0008) // (SPI0) Receive Data Register
-#define AT91C_SPI0_CSR            (0xFFFE0030) // (SPI0) Chip Select Register
-// ========== Register definition for PDC_US1 peripheral ==========
-#define AT91C_US1_RNCR            (0xFFFC4114) // (PDC_US1) Receive Next Counter Register
-#define AT91C_US1_PTCR            (0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
-#define AT91C_US1_TCR             (0xFFFC410C) // (PDC_US1) Transmit Counter Register
-#define AT91C_US1_PTSR            (0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
-#define AT91C_US1_TNPR            (0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
-#define AT91C_US1_RCR             (0xFFFC4104) // (PDC_US1) Receive Counter Register
-#define AT91C_US1_RNPR            (0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
-#define AT91C_US1_RPR             (0xFFFC4100) // (PDC_US1) Receive Pointer Register
-#define AT91C_US1_TNCR            (0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
-#define AT91C_US1_TPR             (0xFFFC4108) // (PDC_US1) Transmit Pointer Register
-// ========== Register definition for US1 peripheral ==========
-#define AT91C_US1_IF              (0xFFFC404C) // (US1) IRDA_FILTER Register
-#define AT91C_US1_NER             (0xFFFC4044) // (US1) Nb Errors Register
-#define AT91C_US1_RTOR            (0xFFFC4024) // (US1) Receiver Time-out Register
-#define AT91C_US1_CSR             (0xFFFC4014) // (US1) Channel Status Register
-#define AT91C_US1_IDR             (0xFFFC400C) // (US1) Interrupt Disable Register
-#define AT91C_US1_IER             (0xFFFC4008) // (US1) Interrupt Enable Register
-#define AT91C_US1_THR             (0xFFFC401C) // (US1) Transmitter Holding Register
-#define AT91C_US1_TTGR            (0xFFFC4028) // (US1) Transmitter Time-guard Register
-#define AT91C_US1_RHR             (0xFFFC4018) // (US1) Receiver Holding Register
-#define AT91C_US1_BRGR            (0xFFFC4020) // (US1) Baud Rate Generator Register
-#define AT91C_US1_IMR             (0xFFFC4010) // (US1) Interrupt Mask Register
-#define AT91C_US1_FIDI            (0xFFFC4040) // (US1) FI_DI_Ratio Register
-#define AT91C_US1_CR              (0xFFFC4000) // (US1) Control Register
-#define AT91C_US1_MR              (0xFFFC4004) // (US1) Mode Register
-// ========== Register definition for PDC_US0 peripheral ==========
-#define AT91C_US0_TNPR            (0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
-#define AT91C_US0_RNPR            (0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
-#define AT91C_US0_TCR             (0xFFFC010C) // (PDC_US0) Transmit Counter Register
-#define AT91C_US0_PTCR            (0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
-#define AT91C_US0_PTSR            (0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
-#define AT91C_US0_TNCR            (0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
-#define AT91C_US0_TPR             (0xFFFC0108) // (PDC_US0) Transmit Pointer Register
-#define AT91C_US0_RCR             (0xFFFC0104) // (PDC_US0) Receive Counter Register
-#define AT91C_US0_RPR             (0xFFFC0100) // (PDC_US0) Receive Pointer Register
-#define AT91C_US0_RNCR            (0xFFFC0114) // (PDC_US0) Receive Next Counter Register
-// ========== Register definition for US0 peripheral ==========
-#define AT91C_US0_BRGR            (0xFFFC0020) // (US0) Baud Rate Generator Register
-#define AT91C_US0_NER             (0xFFFC0044) // (US0) Nb Errors Register
-#define AT91C_US0_CR              (0xFFFC0000) // (US0) Control Register
-#define AT91C_US0_IMR             (0xFFFC0010) // (US0) Interrupt Mask Register
-#define AT91C_US0_FIDI            (0xFFFC0040) // (US0) FI_DI_Ratio Register
-#define AT91C_US0_TTGR            (0xFFFC0028) // (US0) Transmitter Time-guard Register
-#define AT91C_US0_MR              (0xFFFC0004) // (US0) Mode Register
-#define AT91C_US0_RTOR            (0xFFFC0024) // (US0) Receiver Time-out Register
-#define AT91C_US0_CSR             (0xFFFC0014) // (US0) Channel Status Register
-#define AT91C_US0_RHR             (0xFFFC0018) // (US0) Receiver Holding Register
-#define AT91C_US0_IDR             (0xFFFC000C) // (US0) Interrupt Disable Register
-#define AT91C_US0_THR             (0xFFFC001C) // (US0) Transmitter Holding Register
-#define AT91C_US0_IF              (0xFFFC004C) // (US0) IRDA_FILTER Register
-#define AT91C_US0_IER             (0xFFFC0008) // (US0) Interrupt Enable Register
-// ========== Register definition for PDC_SSC peripheral ==========
-#define AT91C_SSC_TNCR            (0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
-#define AT91C_SSC_RPR             (0xFFFD4100) // (PDC_SSC) Receive Pointer Register
-#define AT91C_SSC_RNCR            (0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
-#define AT91C_SSC_TPR             (0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
-#define AT91C_SSC_PTCR            (0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
-#define AT91C_SSC_TCR             (0xFFFD410C) // (PDC_SSC) Transmit Counter Register
-#define AT91C_SSC_RCR             (0xFFFD4104) // (PDC_SSC) Receive Counter Register
-#define AT91C_SSC_RNPR            (0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
-#define AT91C_SSC_TNPR            (0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
-#define AT91C_SSC_PTSR            (0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
-// ========== Register definition for SSC peripheral ==========
-#define AT91C_SSC_RHR             (0xFFFD4020) // (SSC) Receive Holding Register
-#define AT91C_SSC_RSHR            (0xFFFD4030) // (SSC) Receive Sync Holding Register
-#define AT91C_SSC_TFMR            (0xFFFD401C) // (SSC) Transmit Frame Mode Register
-#define AT91C_SSC_IDR             (0xFFFD4048) // (SSC) Interrupt Disable Register
-#define AT91C_SSC_THR             (0xFFFD4024) // (SSC) Transmit Holding Register
-#define AT91C_SSC_RCMR            (0xFFFD4010) // (SSC) Receive Clock ModeRegister
-#define AT91C_SSC_IER             (0xFFFD4044) // (SSC) Interrupt Enable Register
-#define AT91C_SSC_TSHR            (0xFFFD4034) // (SSC) Transmit Sync Holding Register
-#define AT91C_SSC_SR              (0xFFFD4040) // (SSC) Status Register
-#define AT91C_SSC_CMR             (0xFFFD4004) // (SSC) Clock Mode Register
-#define AT91C_SSC_TCMR            (0xFFFD4018) // (SSC) Transmit Clock Mode Register
-#define AT91C_SSC_CR              (0xFFFD4000) // (SSC) Control Register
-#define AT91C_SSC_IMR             (0xFFFD404C) // (SSC) Interrupt Mask Register
-#define AT91C_SSC_RFMR            (0xFFFD4014) // (SSC) Receive Frame Mode Register
-// ========== Register definition for TWI peripheral ==========
-#define AT91C_TWI_IER             (0xFFFB8024) // (TWI) Interrupt Enable Register
-#define AT91C_TWI_CR              (0xFFFB8000) // (TWI) Control Register
-#define AT91C_TWI_SR              (0xFFFB8020) // (TWI) Status Register
-#define AT91C_TWI_IMR             (0xFFFB802C) // (TWI) Interrupt Mask Register
-#define AT91C_TWI_THR             (0xFFFB8034) // (TWI) Transmit Holding Register
-#define AT91C_TWI_IDR             (0xFFFB8028) // (TWI) Interrupt Disable Register
-#define AT91C_TWI_IADR            (0xFFFB800C) // (TWI) Internal Address Register
-#define AT91C_TWI_MMR             (0xFFFB8004) // (TWI) Master Mode Register
-#define AT91C_TWI_CWGR            (0xFFFB8010) // (TWI) Clock Waveform Generator Register
-#define AT91C_TWI_RHR             (0xFFFB8030) // (TWI) Receive Holding Register
-// ========== Register definition for PWMC_CH3 peripheral ==========
-#define AT91C_PWMC_CH3_CUPDR      (0xFFFCC270) // (PWMC_CH3) Channel Update Register
-#define AT91C_PWMC_CH3_Reserved   (0xFFFCC274) // (PWMC_CH3) Reserved
-#define AT91C_PWMC_CH3_CPRDR      (0xFFFCC268) // (PWMC_CH3) Channel Period Register
-#define AT91C_PWMC_CH3_CDTYR      (0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
-#define AT91C_PWMC_CH3_CCNTR      (0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
-#define AT91C_PWMC_CH3_CMR        (0xFFFCC260) // (PWMC_CH3) Channel Mode Register
-// ========== Register definition for PWMC_CH2 peripheral ==========
-#define AT91C_PWMC_CH2_Reserved   (0xFFFCC254) // (PWMC_CH2) Reserved
-#define AT91C_PWMC_CH2_CMR        (0xFFFCC240) // (PWMC_CH2) Channel Mode Register
-#define AT91C_PWMC_CH2_CCNTR      (0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
-#define AT91C_PWMC_CH2_CPRDR      (0xFFFCC248) // (PWMC_CH2) Channel Period Register
-#define AT91C_PWMC_CH2_CUPDR      (0xFFFCC250) // (PWMC_CH2) Channel Update Register
-#define AT91C_PWMC_CH2_CDTYR      (0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
-// ========== Register definition for PWMC_CH1 peripheral ==========
-#define AT91C_PWMC_CH1_Reserved   (0xFFFCC234) // (PWMC_CH1) Reserved
-#define AT91C_PWMC_CH1_CUPDR      (0xFFFCC230) // (PWMC_CH1) Channel Update Register
-#define AT91C_PWMC_CH1_CPRDR      (0xFFFCC228) // (PWMC_CH1) Channel Period Register
-#define AT91C_PWMC_CH1_CCNTR      (0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
-#define AT91C_PWMC_CH1_CDTYR      (0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
-#define AT91C_PWMC_CH1_CMR        (0xFFFCC220) // (PWMC_CH1) Channel Mode Register
-// ========== Register definition for PWMC_CH0 peripheral ==========
-#define AT91C_PWMC_CH0_Reserved   (0xFFFCC214) // (PWMC_CH0) Reserved
-#define AT91C_PWMC_CH0_CPRDR      (0xFFFCC208) // (PWMC_CH0) Channel Period Register
-#define AT91C_PWMC_CH0_CDTYR      (0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
-#define AT91C_PWMC_CH0_CMR        (0xFFFCC200) // (PWMC_CH0) Channel Mode Register
-#define AT91C_PWMC_CH0_CUPDR      (0xFFFCC210) // (PWMC_CH0) Channel Update Register
-#define AT91C_PWMC_CH0_CCNTR      (0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
-// ========== Register definition for PWMC peripheral ==========
-#define AT91C_PWMC_IDR            (0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
-#define AT91C_PWMC_DIS            (0xFFFCC008) // (PWMC) PWMC Disable Register
-#define AT91C_PWMC_IER            (0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
-#define AT91C_PWMC_VR             (0xFFFCC0FC) // (PWMC) PWMC Version Register
-#define AT91C_PWMC_ISR            (0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
-#define AT91C_PWMC_SR             (0xFFFCC00C) // (PWMC) PWMC Status Register
-#define AT91C_PWMC_IMR            (0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
-#define AT91C_PWMC_MR             (0xFFFCC000) // (PWMC) PWMC Mode Register
-#define AT91C_PWMC_ENA            (0xFFFCC004) // (PWMC) PWMC Enable Register
-// ========== Register definition for UDP peripheral ==========
-#define AT91C_UDP_IMR             (0xFFFB0018) // (UDP) Interrupt Mask Register
-#define AT91C_UDP_FADDR           (0xFFFB0008) // (UDP) Function Address Register
-#define AT91C_UDP_NUM             (0xFFFB0000) // (UDP) Frame Number Register
-#define AT91C_UDP_FDR             (0xFFFB0050) // (UDP) Endpoint FIFO Data Register
-#define AT91C_UDP_ISR             (0xFFFB001C) // (UDP) Interrupt Status Register
-#define AT91C_UDP_CSR             (0xFFFB0030) // (UDP) Endpoint Control and Status Register
-#define AT91C_UDP_IDR             (0xFFFB0014) // (UDP) Interrupt Disable Register
-#define AT91C_UDP_ICR             (0xFFFB0020) // (UDP) Interrupt Clear Register
-#define AT91C_UDP_RSTEP           (0xFFFB0028) // (UDP) Reset Endpoint Register
-#define AT91C_UDP_TXVC            (0xFFFB0074) // (UDP) Transceiver Control Register
-#define AT91C_UDP_GLBSTATE        (0xFFFB0004) // (UDP) Global State Register
-#define AT91C_UDP_IER             (0xFFFB0010) // (UDP) Interrupt Enable Register
-// ========== Register definition for TC0 peripheral ==========
-#define AT91C_TC0_SR              (0xFFFA0020) // (TC0) Status Register
-#define AT91C_TC0_RC              (0xFFFA001C) // (TC0) Register C
-#define AT91C_TC0_RB              (0xFFFA0018) // (TC0) Register B
-#define AT91C_TC0_CCR             (0xFFFA0000) // (TC0) Channel Control Register
-#define AT91C_TC0_CMR             (0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC0_IER             (0xFFFA0024) // (TC0) Interrupt Enable Register
-#define AT91C_TC0_RA              (0xFFFA0014) // (TC0) Register A
-#define AT91C_TC0_IDR             (0xFFFA0028) // (TC0) Interrupt Disable Register
-#define AT91C_TC0_CV              (0xFFFA0010) // (TC0) Counter Value
-#define AT91C_TC0_IMR             (0xFFFA002C) // (TC0) Interrupt Mask Register
-// ========== Register definition for TC1 peripheral ==========
-#define AT91C_TC1_RB              (0xFFFA0058) // (TC1) Register B
-#define AT91C_TC1_CCR             (0xFFFA0040) // (TC1) Channel Control Register
-#define AT91C_TC1_IER             (0xFFFA0064) // (TC1) Interrupt Enable Register
-#define AT91C_TC1_IDR             (0xFFFA0068) // (TC1) Interrupt Disable Register
-#define AT91C_TC1_SR              (0xFFFA0060) // (TC1) Status Register
-#define AT91C_TC1_CMR             (0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC1_RA              (0xFFFA0054) // (TC1) Register A
-#define AT91C_TC1_RC              (0xFFFA005C) // (TC1) Register C
-#define AT91C_TC1_IMR             (0xFFFA006C) // (TC1) Interrupt Mask Register
-#define AT91C_TC1_CV              (0xFFFA0050) // (TC1) Counter Value
-// ========== Register definition for TC2 peripheral ==========
-#define AT91C_TC2_CMR             (0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC2_CCR             (0xFFFA0080) // (TC2) Channel Control Register
-#define AT91C_TC2_CV              (0xFFFA0090) // (TC2) Counter Value
-#define AT91C_TC2_RA              (0xFFFA0094) // (TC2) Register A
-#define AT91C_TC2_RB              (0xFFFA0098) // (TC2) Register B
-#define AT91C_TC2_IDR             (0xFFFA00A8) // (TC2) Interrupt Disable Register
-#define AT91C_TC2_IMR             (0xFFFA00AC) // (TC2) Interrupt Mask Register
-#define AT91C_TC2_RC              (0xFFFA009C) // (TC2) Register C
-#define AT91C_TC2_IER             (0xFFFA00A4) // (TC2) Interrupt Enable Register
-#define AT91C_TC2_SR              (0xFFFA00A0) // (TC2) Status Register
-// ========== Register definition for TCB peripheral ==========
-#define AT91C_TCB_BMR             (0xFFFA00C4) // (TCB) TC Block Mode Register
-#define AT91C_TCB_BCR             (0xFFFA00C0) // (TCB) TC Block Control Register
-// ========== Register definition for CAN_MB0 peripheral ==========
-#define AT91C_CAN_MB0_MDL         (0xFFFD0214) // (CAN_MB0) MailBox Data Low Register
-#define AT91C_CAN_MB0_MAM         (0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB0_MCR         (0xFFFD021C) // (CAN_MB0) MailBox Control Register
-#define AT91C_CAN_MB0_MID         (0xFFFD0208) // (CAN_MB0) MailBox ID Register
-#define AT91C_CAN_MB0_MSR         (0xFFFD0210) // (CAN_MB0) MailBox Status Register
-#define AT91C_CAN_MB0_MFID        (0xFFFD020C) // (CAN_MB0) MailBox Family ID Register
-#define AT91C_CAN_MB0_MDH         (0xFFFD0218) // (CAN_MB0) MailBox Data High Register
-#define AT91C_CAN_MB0_MMR         (0xFFFD0200) // (CAN_MB0) MailBox Mode Register
-// ========== Register definition for CAN_MB1 peripheral ==========
-#define AT91C_CAN_MB1_MDL         (0xFFFD0234) // (CAN_MB1) MailBox Data Low Register
-#define AT91C_CAN_MB1_MID         (0xFFFD0228) // (CAN_MB1) MailBox ID Register
-#define AT91C_CAN_MB1_MMR         (0xFFFD0220) // (CAN_MB1) MailBox Mode Register
-#define AT91C_CAN_MB1_MSR         (0xFFFD0230) // (CAN_MB1) MailBox Status Register
-#define AT91C_CAN_MB1_MAM         (0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB1_MDH         (0xFFFD0238) // (CAN_MB1) MailBox Data High Register
-#define AT91C_CAN_MB1_MCR         (0xFFFD023C) // (CAN_MB1) MailBox Control Register
-#define AT91C_CAN_MB1_MFID        (0xFFFD022C) // (CAN_MB1) MailBox Family ID Register
-// ========== Register definition for CAN_MB2 peripheral ==========
-#define AT91C_CAN_MB2_MCR         (0xFFFD025C) // (CAN_MB2) MailBox Control Register
-#define AT91C_CAN_MB2_MDH         (0xFFFD0258) // (CAN_MB2) MailBox Data High Register
-#define AT91C_CAN_MB2_MID         (0xFFFD0248) // (CAN_MB2) MailBox ID Register
-#define AT91C_CAN_MB2_MDL         (0xFFFD0254) // (CAN_MB2) MailBox Data Low Register
-#define AT91C_CAN_MB2_MMR         (0xFFFD0240) // (CAN_MB2) MailBox Mode Register
-#define AT91C_CAN_MB2_MAM         (0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB2_MFID        (0xFFFD024C) // (CAN_MB2) MailBox Family ID Register
-#define AT91C_CAN_MB2_MSR         (0xFFFD0250) // (CAN_MB2) MailBox Status Register
-// ========== Register definition for CAN_MB3 peripheral ==========
-#define AT91C_CAN_MB3_MFID        (0xFFFD026C) // (CAN_MB3) MailBox Family ID Register
-#define AT91C_CAN_MB3_MAM         (0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB3_MID         (0xFFFD0268) // (CAN_MB3) MailBox ID Register
-#define AT91C_CAN_MB3_MCR         (0xFFFD027C) // (CAN_MB3) MailBox Control Register
-#define AT91C_CAN_MB3_MMR         (0xFFFD0260) // (CAN_MB3) MailBox Mode Register
-#define AT91C_CAN_MB3_MSR         (0xFFFD0270) // (CAN_MB3) MailBox Status Register
-#define AT91C_CAN_MB3_MDL         (0xFFFD0274) // (CAN_MB3) MailBox Data Low Register
-#define AT91C_CAN_MB3_MDH         (0xFFFD0278) // (CAN_MB3) MailBox Data High Register
-// ========== Register definition for CAN_MB4 peripheral ==========
-#define AT91C_CAN_MB4_MID         (0xFFFD0288) // (CAN_MB4) MailBox ID Register
-#define AT91C_CAN_MB4_MMR         (0xFFFD0280) // (CAN_MB4) MailBox Mode Register
-#define AT91C_CAN_MB4_MDH         (0xFFFD0298) // (CAN_MB4) MailBox Data High Register
-#define AT91C_CAN_MB4_MFID        (0xFFFD028C) // (CAN_MB4) MailBox Family ID Register
-#define AT91C_CAN_MB4_MSR         (0xFFFD0290) // (CAN_MB4) MailBox Status Register
-#define AT91C_CAN_MB4_MCR         (0xFFFD029C) // (CAN_MB4) MailBox Control Register
-#define AT91C_CAN_MB4_MDL         (0xFFFD0294) // (CAN_MB4) MailBox Data Low Register
-#define AT91C_CAN_MB4_MAM         (0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register
-// ========== Register definition for CAN_MB5 peripheral ==========
-#define AT91C_CAN_MB5_MSR         (0xFFFD02B0) // (CAN_MB5) MailBox Status Register
-#define AT91C_CAN_MB5_MCR         (0xFFFD02BC) // (CAN_MB5) MailBox Control Register
-#define AT91C_CAN_MB5_MFID        (0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register
-#define AT91C_CAN_MB5_MDH         (0xFFFD02B8) // (CAN_MB5) MailBox Data High Register
-#define AT91C_CAN_MB5_MID         (0xFFFD02A8) // (CAN_MB5) MailBox ID Register
-#define AT91C_CAN_MB5_MMR         (0xFFFD02A0) // (CAN_MB5) MailBox Mode Register
-#define AT91C_CAN_MB5_MDL         (0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register
-#define AT91C_CAN_MB5_MAM         (0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register
-// ========== Register definition for CAN_MB6 peripheral ==========
-#define AT91C_CAN_MB6_MFID        (0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register
-#define AT91C_CAN_MB6_MID         (0xFFFD02C8) // (CAN_MB6) MailBox ID Register
-#define AT91C_CAN_MB6_MAM         (0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB6_MSR         (0xFFFD02D0) // (CAN_MB6) MailBox Status Register
-#define AT91C_CAN_MB6_MDL         (0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register
-#define AT91C_CAN_MB6_MCR         (0xFFFD02DC) // (CAN_MB6) MailBox Control Register
-#define AT91C_CAN_MB6_MDH         (0xFFFD02D8) // (CAN_MB6) MailBox Data High Register
-#define AT91C_CAN_MB6_MMR         (0xFFFD02C0) // (CAN_MB6) MailBox Mode Register
-// ========== Register definition for CAN_MB7 peripheral ==========
-#define AT91C_CAN_MB7_MCR         (0xFFFD02FC) // (CAN_MB7) MailBox Control Register
-#define AT91C_CAN_MB7_MDH         (0xFFFD02F8) // (CAN_MB7) MailBox Data High Register
-#define AT91C_CAN_MB7_MFID        (0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register
-#define AT91C_CAN_MB7_MDL         (0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register
-#define AT91C_CAN_MB7_MID         (0xFFFD02E8) // (CAN_MB7) MailBox ID Register
-#define AT91C_CAN_MB7_MMR         (0xFFFD02E0) // (CAN_MB7) MailBox Mode Register
-#define AT91C_CAN_MB7_MAM         (0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB7_MSR         (0xFFFD02F0) // (CAN_MB7) MailBox Status Register
-// ========== Register definition for CAN peripheral ==========
-#define AT91C_CAN_TCR             (0xFFFD0024) // (CAN) Transfer Command Register
-#define AT91C_CAN_IMR             (0xFFFD000C) // (CAN) Interrupt Mask Register
-#define AT91C_CAN_IER             (0xFFFD0004) // (CAN) Interrupt Enable Register
-#define AT91C_CAN_ECR             (0xFFFD0020) // (CAN) Error Counter Register
-#define AT91C_CAN_TIMESTP         (0xFFFD001C) // (CAN) Time Stamp Register
-#define AT91C_CAN_MR              (0xFFFD0000) // (CAN) Mode Register
-#define AT91C_CAN_IDR             (0xFFFD0008) // (CAN) Interrupt Disable Register
-#define AT91C_CAN_ACR             (0xFFFD0028) // (CAN) Abort Command Register
-#define AT91C_CAN_TIM             (0xFFFD0018) // (CAN) Timer Register
-#define AT91C_CAN_SR              (0xFFFD0010) // (CAN) Status Register
-#define AT91C_CAN_BR              (0xFFFD0014) // (CAN) Baudrate Register
-#define AT91C_CAN_VR              (0xFFFD00FC) // (CAN) Version Register
-// ========== Register definition for EMAC peripheral ==========
-#define AT91C_EMAC_ISR            (0xFFFDC024) // (EMAC) Interrupt Status Register
-#define AT91C_EMAC_SA4H           (0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes
-#define AT91C_EMAC_SA1L           (0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes
-#define AT91C_EMAC_ELE            (0xFFFDC078) // (EMAC) Excessive Length Errors Register
-#define AT91C_EMAC_LCOL           (0xFFFDC05C) // (EMAC) Late Collision Register
-#define AT91C_EMAC_RLE            (0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register
-#define AT91C_EMAC_WOL            (0xFFFDC0C4) // (EMAC) Wake On LAN Register
-#define AT91C_EMAC_DTF            (0xFFFDC058) // (EMAC) Deferred Transmission Frame Register
-#define AT91C_EMAC_TUND           (0xFFFDC064) // (EMAC) Transmit Underrun Error Register
-#define AT91C_EMAC_NCR            (0xFFFDC000) // (EMAC) Network Control Register
-#define AT91C_EMAC_SA4L           (0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes
-#define AT91C_EMAC_RSR            (0xFFFDC020) // (EMAC) Receive Status Register
-#define AT91C_EMAC_SA3L           (0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes
-#define AT91C_EMAC_TSR            (0xFFFDC014) // (EMAC) Transmit Status Register
-#define AT91C_EMAC_IDR            (0xFFFDC02C) // (EMAC) Interrupt Disable Register
-#define AT91C_EMAC_RSE            (0xFFFDC074) // (EMAC) Receive Symbol Errors Register
-#define AT91C_EMAC_ECOL           (0xFFFDC060) // (EMAC) Excessive Collision Register
-#define AT91C_EMAC_TID            (0xFFFDC0B8) // (EMAC) Type ID Checking Register
-#define AT91C_EMAC_HRB            (0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]
-#define AT91C_EMAC_TBQP           (0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer
-#define AT91C_EMAC_USRIO          (0xFFFDC0C0) // (EMAC) USER Input/Output Register
-#define AT91C_EMAC_PTR            (0xFFFDC038) // (EMAC) Pause Time Register
-#define AT91C_EMAC_SA2H           (0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes
-#define AT91C_EMAC_ROV            (0xFFFDC070) // (EMAC) Receive Overrun Errors Register
-#define AT91C_EMAC_ALE            (0xFFFDC054) // (EMAC) Alignment Error Register
-#define AT91C_EMAC_RJA            (0xFFFDC07C) // (EMAC) Receive Jabbers Register
-#define AT91C_EMAC_RBQP           (0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer
-#define AT91C_EMAC_TPF            (0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register
-#define AT91C_EMAC_NCFGR          (0xFFFDC004) // (EMAC) Network Configuration Register
-#define AT91C_EMAC_HRT            (0xFFFDC094) // (EMAC) Hash Address Top[63:32]
-#define AT91C_EMAC_USF            (0xFFFDC080) // (EMAC) Undersize Frames Register
-#define AT91C_EMAC_FCSE           (0xFFFDC050) // (EMAC) Frame Check Sequence Error Register
-#define AT91C_EMAC_TPQ            (0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register
-#define AT91C_EMAC_MAN            (0xFFFDC034) // (EMAC) PHY Maintenance Register
-#define AT91C_EMAC_FTO            (0xFFFDC040) // (EMAC) Frames Transmitted OK Register
-#define AT91C_EMAC_REV            (0xFFFDC0FC) // (EMAC) Revision Register
-#define AT91C_EMAC_IMR            (0xFFFDC030) // (EMAC) Interrupt Mask Register
-#define AT91C_EMAC_SCF            (0xFFFDC044) // (EMAC) Single Collision Frame Register
-#define AT91C_EMAC_PFR            (0xFFFDC03C) // (EMAC) Pause Frames received Register
-#define AT91C_EMAC_MCF            (0xFFFDC048) // (EMAC) Multiple Collision Frame Register
-#define AT91C_EMAC_NSR            (0xFFFDC008) // (EMAC) Network Status Register
-#define AT91C_EMAC_SA2L           (0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes
-#define AT91C_EMAC_FRO            (0xFFFDC04C) // (EMAC) Frames Received OK Register
-#define AT91C_EMAC_IER            (0xFFFDC028) // (EMAC) Interrupt Enable Register
-#define AT91C_EMAC_SA1H           (0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes
-#define AT91C_EMAC_CSE            (0xFFFDC068) // (EMAC) Carrier Sense Error Register
-#define AT91C_EMAC_SA3H           (0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes
-#define AT91C_EMAC_RRE            (0xFFFDC06C) // (EMAC) Receive Ressource Error Register
-#define AT91C_EMAC_STE            (0xFFFDC084) // (EMAC) SQE Test Error Register
-// ========== Register definition for PDC_ADC peripheral ==========
-#define AT91C_ADC_PTSR            (0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
-#define AT91C_ADC_PTCR            (0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
-#define AT91C_ADC_TNPR            (0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
-#define AT91C_ADC_TNCR            (0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
-#define AT91C_ADC_RNPR            (0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
-#define AT91C_ADC_RNCR            (0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
-#define AT91C_ADC_RPR             (0xFFFD8100) // (PDC_ADC) Receive Pointer Register
-#define AT91C_ADC_TCR             (0xFFFD810C) // (PDC_ADC) Transmit Counter Register
-#define AT91C_ADC_TPR             (0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
-#define AT91C_ADC_RCR             (0xFFFD8104) // (PDC_ADC) Receive Counter Register
-// ========== Register definition for ADC peripheral ==========
-#define AT91C_ADC_CDR2            (0xFFFD8038) // (ADC) ADC Channel Data Register 2
-#define AT91C_ADC_CDR3            (0xFFFD803C) // (ADC) ADC Channel Data Register 3
-#define AT91C_ADC_CDR0            (0xFFFD8030) // (ADC) ADC Channel Data Register 0
-#define AT91C_ADC_CDR5            (0xFFFD8044) // (ADC) ADC Channel Data Register 5
-#define AT91C_ADC_CHDR            (0xFFFD8014) // (ADC) ADC Channel Disable Register
-#define AT91C_ADC_SR              (0xFFFD801C) // (ADC) ADC Status Register
-#define AT91C_ADC_CDR4            (0xFFFD8040) // (ADC) ADC Channel Data Register 4
-#define AT91C_ADC_CDR1            (0xFFFD8034) // (ADC) ADC Channel Data Register 1
-#define AT91C_ADC_LCDR            (0xFFFD8020) // (ADC) ADC Last Converted Data Register
-#define AT91C_ADC_IDR             (0xFFFD8028) // (ADC) ADC Interrupt Disable Register
-#define AT91C_ADC_CR              (0xFFFD8000) // (ADC) ADC Control Register
-#define AT91C_ADC_CDR7            (0xFFFD804C) // (ADC) ADC Channel Data Register 7
-#define AT91C_ADC_CDR6            (0xFFFD8048) // (ADC) ADC Channel Data Register 6
-#define AT91C_ADC_IER             (0xFFFD8024) // (ADC) ADC Interrupt Enable Register
-#define AT91C_ADC_CHER            (0xFFFD8010) // (ADC) ADC Channel Enable Register
-#define AT91C_ADC_CHSR            (0xFFFD8018) // (ADC) ADC Channel Status Register
-#define AT91C_ADC_MR              (0xFFFD8004) // (ADC) ADC Mode Register
-#define AT91C_ADC_IMR             (0xFFFD802C) // (ADC) ADC Interrupt Mask Register
-// ========== Register definition for PDC_AES peripheral ==========
-#define AT91C_AES_TPR             (0xFFFA4108) // (PDC_AES) Transmit Pointer Register
-#define AT91C_AES_PTCR            (0xFFFA4120) // (PDC_AES) PDC Transfer Control Register
-#define AT91C_AES_RNPR            (0xFFFA4110) // (PDC_AES) Receive Next Pointer Register
-#define AT91C_AES_TNCR            (0xFFFA411C) // (PDC_AES) Transmit Next Counter Register
-#define AT91C_AES_TCR             (0xFFFA410C) // (PDC_AES) Transmit Counter Register
-#define AT91C_AES_RCR             (0xFFFA4104) // (PDC_AES) Receive Counter Register
-#define AT91C_AES_RNCR            (0xFFFA4114) // (PDC_AES) Receive Next Counter Register
-#define AT91C_AES_TNPR            (0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register
-#define AT91C_AES_RPR             (0xFFFA4100) // (PDC_AES) Receive Pointer Register
-#define AT91C_AES_PTSR            (0xFFFA4124) // (PDC_AES) PDC Transfer Status Register
-// ========== Register definition for AES peripheral ==========
-#define AT91C_AES_IVxR            (0xFFFA4060) // (AES) Initialization Vector x Register
-#define AT91C_AES_MR              (0xFFFA4004) // (AES) Mode Register
-#define AT91C_AES_VR              (0xFFFA40FC) // (AES) AES Version Register
-#define AT91C_AES_ODATAxR         (0xFFFA4050) // (AES) Output Data x Register
-#define AT91C_AES_IDATAxR         (0xFFFA4040) // (AES) Input Data x Register
-#define AT91C_AES_CR              (0xFFFA4000) // (AES) Control Register
-#define AT91C_AES_IDR             (0xFFFA4014) // (AES) Interrupt Disable Register
-#define AT91C_AES_IMR             (0xFFFA4018) // (AES) Interrupt Mask Register
-#define AT91C_AES_IER             (0xFFFA4010) // (AES) Interrupt Enable Register
-#define AT91C_AES_KEYWxR          (0xFFFA4020) // (AES) Key Word x Register
-#define AT91C_AES_ISR             (0xFFFA401C) // (AES) Interrupt Status Register
-// ========== Register definition for PDC_TDES peripheral ==========
-#define AT91C_TDES_RNCR           (0xFFFA8114) // (PDC_TDES) Receive Next Counter Register
-#define AT91C_TDES_TCR            (0xFFFA810C) // (PDC_TDES) Transmit Counter Register
-#define AT91C_TDES_RCR            (0xFFFA8104) // (PDC_TDES) Receive Counter Register
-#define AT91C_TDES_TNPR           (0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register
-#define AT91C_TDES_RNPR           (0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register
-#define AT91C_TDES_RPR            (0xFFFA8100) // (PDC_TDES) Receive Pointer Register
-#define AT91C_TDES_TNCR           (0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register
-#define AT91C_TDES_TPR            (0xFFFA8108) // (PDC_TDES) Transmit Pointer Register
-#define AT91C_TDES_PTSR           (0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register
-#define AT91C_TDES_PTCR           (0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register
-// ========== Register definition for TDES peripheral ==========
-#define AT91C_TDES_KEY2WxR        (0xFFFA8028) // (TDES) Key 2 Word x Register
-#define AT91C_TDES_KEY3WxR        (0xFFFA8030) // (TDES) Key 3 Word x Register
-#define AT91C_TDES_IDR            (0xFFFA8014) // (TDES) Interrupt Disable Register
-#define AT91C_TDES_VR             (0xFFFA80FC) // (TDES) TDES Version Register
-#define AT91C_TDES_IVxR           (0xFFFA8060) // (TDES) Initialization Vector x Register
-#define AT91C_TDES_ODATAxR        (0xFFFA8050) // (TDES) Output Data x Register
-#define AT91C_TDES_IMR            (0xFFFA8018) // (TDES) Interrupt Mask Register
-#define AT91C_TDES_MR             (0xFFFA8004) // (TDES) Mode Register
-#define AT91C_TDES_CR             (0xFFFA8000) // (TDES) Control Register
-#define AT91C_TDES_IER            (0xFFFA8010) // (TDES) Interrupt Enable Register
-#define AT91C_TDES_ISR            (0xFFFA801C) // (TDES) Interrupt Status Register
-#define AT91C_TDES_IDATAxR        (0xFFFA8040) // (TDES) Input Data x Register
-#define AT91C_TDES_KEY1WxR        (0xFFFA8020) // (TDES) Key 1 Word x Register
+/* ***************************************************************************** */
+/*               REGISTER ADDRESS DEFINITION FOR AT91SAM7X128 */
+/* ***************************************************************************** */
+/* ========== Register definition for SYS peripheral ========== */
+/* ========== Register definition for AIC peripheral ========== */
+#define AT91C_AIC_IVR              ( 0xFFFFF100 ) /* (AIC) IRQ Vector Register */
+#define AT91C_AIC_SMR              ( 0xFFFFF000 ) /* (AIC) Source Mode Register */
+#define AT91C_AIC_FVR              ( 0xFFFFF104 ) /* (AIC) FIQ Vector Register */
+#define AT91C_AIC_DCR              ( 0xFFFFF138 ) /* (AIC) Debug Control Register (Protect) */
+#define AT91C_AIC_EOICR            ( 0xFFFFF130 ) /* (AIC) End of Interrupt Command Register */
+#define AT91C_AIC_SVR              ( 0xFFFFF080 ) /* (AIC) Source Vector Register */
+#define AT91C_AIC_FFSR             ( 0xFFFFF148 ) /* (AIC) Fast Forcing Status Register */
+#define AT91C_AIC_ICCR             ( 0xFFFFF128 ) /* (AIC) Interrupt Clear Command Register */
+#define AT91C_AIC_ISR              ( 0xFFFFF108 ) /* (AIC) Interrupt Status Register */
+#define AT91C_AIC_IMR              ( 0xFFFFF110 ) /* (AIC) Interrupt Mask Register */
+#define AT91C_AIC_IPR              ( 0xFFFFF10C ) /* (AIC) Interrupt Pending Register */
+#define AT91C_AIC_FFER             ( 0xFFFFF140 ) /* (AIC) Fast Forcing Enable Register */
+#define AT91C_AIC_IECR             ( 0xFFFFF120 ) /* (AIC) Interrupt Enable Command Register */
+#define AT91C_AIC_ISCR             ( 0xFFFFF12C ) /* (AIC) Interrupt Set Command Register */
+#define AT91C_AIC_FFDR             ( 0xFFFFF144 ) /* (AIC) Fast Forcing Disable Register */
+#define AT91C_AIC_CISR             ( 0xFFFFF114 ) /* (AIC) Core Interrupt Status Register */
+#define AT91C_AIC_IDCR             ( 0xFFFFF124 ) /* (AIC) Interrupt Disable Command Register */
+#define AT91C_AIC_SPU              ( 0xFFFFF134 ) /* (AIC) Spurious Vector Register */
+/* ========== Register definition for PDC_DBGU peripheral ========== */
+#define AT91C_DBGU_TCR             ( 0xFFFFF30C ) /* (PDC_DBGU) Transmit Counter Register */
+#define AT91C_DBGU_RNPR            ( 0xFFFFF310 ) /* (PDC_DBGU) Receive Next Pointer Register */
+#define AT91C_DBGU_TNPR            ( 0xFFFFF318 ) /* (PDC_DBGU) Transmit Next Pointer Register */
+#define AT91C_DBGU_TPR             ( 0xFFFFF308 ) /* (PDC_DBGU) Transmit Pointer Register */
+#define AT91C_DBGU_RPR             ( 0xFFFFF300 ) /* (PDC_DBGU) Receive Pointer Register */
+#define AT91C_DBGU_RCR             ( 0xFFFFF304 ) /* (PDC_DBGU) Receive Counter Register */
+#define AT91C_DBGU_RNCR            ( 0xFFFFF314 ) /* (PDC_DBGU) Receive Next Counter Register */
+#define AT91C_DBGU_PTCR            ( 0xFFFFF320 ) /* (PDC_DBGU) PDC Transfer Control Register */
+#define AT91C_DBGU_PTSR            ( 0xFFFFF324 ) /* (PDC_DBGU) PDC Transfer Status Register */
+#define AT91C_DBGU_TNCR            ( 0xFFFFF31C ) /* (PDC_DBGU) Transmit Next Counter Register */
+/* ========== Register definition for DBGU peripheral ========== */
+#define AT91C_DBGU_EXID            ( 0xFFFFF244 ) /* (DBGU) Chip ID Extension Register */
+#define AT91C_DBGU_BRGR            ( 0xFFFFF220 ) /* (DBGU) Baud Rate Generator Register */
+#define AT91C_DBGU_IDR             ( 0xFFFFF20C ) /* (DBGU) Interrupt Disable Register */
+#define AT91C_DBGU_CSR             ( 0xFFFFF214 ) /* (DBGU) Channel Status Register */
+#define AT91C_DBGU_CIDR            ( 0xFFFFF240 ) /* (DBGU) Chip ID Register */
+#define AT91C_DBGU_MR              ( 0xFFFFF204 ) /* (DBGU) Mode Register */
+#define AT91C_DBGU_IMR             ( 0xFFFFF210 ) /* (DBGU) Interrupt Mask Register */
+#define AT91C_DBGU_CR              ( 0xFFFFF200 ) /* (DBGU) Control Register */
+#define AT91C_DBGU_FNTR            ( 0xFFFFF248 ) /* (DBGU) Force NTRST Register */
+#define AT91C_DBGU_THR             ( 0xFFFFF21C ) /* (DBGU) Transmitter Holding Register */
+#define AT91C_DBGU_RHR             ( 0xFFFFF218 ) /* (DBGU) Receiver Holding Register */
+#define AT91C_DBGU_IER             ( 0xFFFFF208 ) /* (DBGU) Interrupt Enable Register */
+/* ========== Register definition for PIOA peripheral ========== */
+#define AT91C_PIOA_ODR             ( 0xFFFFF414 ) /* (PIOA) Output Disable Registerr */
+#define AT91C_PIOA_SODR            ( 0xFFFFF430 ) /* (PIOA) Set Output Data Register */
+#define AT91C_PIOA_ISR             ( 0xFFFFF44C ) /* (PIOA) Interrupt Status Register */
+#define AT91C_PIOA_ABSR            ( 0xFFFFF478 ) /* (PIOA) AB Select Status Register */
+#define AT91C_PIOA_IER             ( 0xFFFFF440 ) /* (PIOA) Interrupt Enable Register */
+#define AT91C_PIOA_PPUDR           ( 0xFFFFF460 ) /* (PIOA) Pull-up Disable Register */
+#define AT91C_PIOA_IMR             ( 0xFFFFF448 ) /* (PIOA) Interrupt Mask Register */
+#define AT91C_PIOA_PER             ( 0xFFFFF400 ) /* (PIOA) PIO Enable Register */
+#define AT91C_PIOA_IFDR            ( 0xFFFFF424 ) /* (PIOA) Input Filter Disable Register */
+#define AT91C_PIOA_OWDR            ( 0xFFFFF4A4 ) /* (PIOA) Output Write Disable Register */
+#define AT91C_PIOA_MDSR            ( 0xFFFFF458 ) /* (PIOA) Multi-driver Status Register */
+#define AT91C_PIOA_IDR             ( 0xFFFFF444 ) /* (PIOA) Interrupt Disable Register */
+#define AT91C_PIOA_ODSR            ( 0xFFFFF438 ) /* (PIOA) Output Data Status Register */
+#define AT91C_PIOA_PPUSR           ( 0xFFFFF468 ) /* (PIOA) Pull-up Status Register */
+#define AT91C_PIOA_OWSR            ( 0xFFFFF4A8 ) /* (PIOA) Output Write Status Register */
+#define AT91C_PIOA_BSR             ( 0xFFFFF474 ) /* (PIOA) Select B Register */
+#define AT91C_PIOA_OWER            ( 0xFFFFF4A0 ) /* (PIOA) Output Write Enable Register */
+#define AT91C_PIOA_IFER            ( 0xFFFFF420 ) /* (PIOA) Input Filter Enable Register */
+#define AT91C_PIOA_PDSR            ( 0xFFFFF43C ) /* (PIOA) Pin Data Status Register */
+#define AT91C_PIOA_PPUER           ( 0xFFFFF464 ) /* (PIOA) Pull-up Enable Register */
+#define AT91C_PIOA_OSR             ( 0xFFFFF418 ) /* (PIOA) Output Status Register */
+#define AT91C_PIOA_ASR             ( 0xFFFFF470 ) /* (PIOA) Select A Register */
+#define AT91C_PIOA_MDDR            ( 0xFFFFF454 ) /* (PIOA) Multi-driver Disable Register */
+#define AT91C_PIOA_CODR            ( 0xFFFFF434 ) /* (PIOA) Clear Output Data Register */
+#define AT91C_PIOA_MDER            ( 0xFFFFF450 ) /* (PIOA) Multi-driver Enable Register */
+#define AT91C_PIOA_PDR             ( 0xFFFFF404 ) /* (PIOA) PIO Disable Register */
+#define AT91C_PIOA_IFSR            ( 0xFFFFF428 ) /* (PIOA) Input Filter Status Register */
+#define AT91C_PIOA_OER             ( 0xFFFFF410 ) /* (PIOA) Output Enable Register */
+#define AT91C_PIOA_PSR             ( 0xFFFFF408 ) /* (PIOA) PIO Status Register */
+/* ========== Register definition for PIOB peripheral ========== */
+#define AT91C_PIOB_OWDR            ( 0xFFFFF6A4 ) /* (PIOB) Output Write Disable Register */
+#define AT91C_PIOB_MDER            ( 0xFFFFF650 ) /* (PIOB) Multi-driver Enable Register */
+#define AT91C_PIOB_PPUSR           ( 0xFFFFF668 ) /* (PIOB) Pull-up Status Register */
+#define AT91C_PIOB_IMR             ( 0xFFFFF648 ) /* (PIOB) Interrupt Mask Register */
+#define AT91C_PIOB_ASR             ( 0xFFFFF670 ) /* (PIOB) Select A Register */
+#define AT91C_PIOB_PPUDR           ( 0xFFFFF660 ) /* (PIOB) Pull-up Disable Register */
+#define AT91C_PIOB_PSR             ( 0xFFFFF608 ) /* (PIOB) PIO Status Register */
+#define AT91C_PIOB_IER             ( 0xFFFFF640 ) /* (PIOB) Interrupt Enable Register */
+#define AT91C_PIOB_CODR            ( 0xFFFFF634 ) /* (PIOB) Clear Output Data Register */
+#define AT91C_PIOB_OWER            ( 0xFFFFF6A0 ) /* (PIOB) Output Write Enable Register */
+#define AT91C_PIOB_ABSR            ( 0xFFFFF678 ) /* (PIOB) AB Select Status Register */
+#define AT91C_PIOB_IFDR            ( 0xFFFFF624 ) /* (PIOB) Input Filter Disable Register */
+#define AT91C_PIOB_PDSR            ( 0xFFFFF63C ) /* (PIOB) Pin Data Status Register */
+#define AT91C_PIOB_IDR             ( 0xFFFFF644 ) /* (PIOB) Interrupt Disable Register */
+#define AT91C_PIOB_OWSR            ( 0xFFFFF6A8 ) /* (PIOB) Output Write Status Register */
+#define AT91C_PIOB_PDR             ( 0xFFFFF604 ) /* (PIOB) PIO Disable Register */
+#define AT91C_PIOB_ODR             ( 0xFFFFF614 ) /* (PIOB) Output Disable Registerr */
+#define AT91C_PIOB_IFSR            ( 0xFFFFF628 ) /* (PIOB) Input Filter Status Register */
+#define AT91C_PIOB_PPUER           ( 0xFFFFF664 ) /* (PIOB) Pull-up Enable Register */
+#define AT91C_PIOB_SODR            ( 0xFFFFF630 ) /* (PIOB) Set Output Data Register */
+#define AT91C_PIOB_ISR             ( 0xFFFFF64C ) /* (PIOB) Interrupt Status Register */
+#define AT91C_PIOB_ODSR            ( 0xFFFFF638 ) /* (PIOB) Output Data Status Register */
+#define AT91C_PIOB_OSR             ( 0xFFFFF618 ) /* (PIOB) Output Status Register */
+#define AT91C_PIOB_MDSR            ( 0xFFFFF658 ) /* (PIOB) Multi-driver Status Register */
+#define AT91C_PIOB_IFER            ( 0xFFFFF620 ) /* (PIOB) Input Filter Enable Register */
+#define AT91C_PIOB_BSR             ( 0xFFFFF674 ) /* (PIOB) Select B Register */
+#define AT91C_PIOB_MDDR            ( 0xFFFFF654 ) /* (PIOB) Multi-driver Disable Register */
+#define AT91C_PIOB_OER             ( 0xFFFFF610 ) /* (PIOB) Output Enable Register */
+#define AT91C_PIOB_PER             ( 0xFFFFF600 ) /* (PIOB) PIO Enable Register */
+/* ========== Register definition for CKGR peripheral ========== */
+#define AT91C_CKGR_MOR             ( 0xFFFFFC20 ) /* (CKGR) Main Oscillator Register */
+#define AT91C_CKGR_PLLR            ( 0xFFFFFC2C ) /* (CKGR) PLL Register */
+#define AT91C_CKGR_MCFR            ( 0xFFFFFC24 ) /* (CKGR) Main Clock  Frequency Register */
+/* ========== Register definition for PMC peripheral ========== */
+#define AT91C_PMC_IDR              ( 0xFFFFFC64 ) /* (PMC) Interrupt Disable Register */
+#define AT91C_PMC_MOR              ( 0xFFFFFC20 ) /* (PMC) Main Oscillator Register */
+#define AT91C_PMC_PLLR             ( 0xFFFFFC2C ) /* (PMC) PLL Register */
+#define AT91C_PMC_PCER             ( 0xFFFFFC10 ) /* (PMC) Peripheral Clock Enable Register */
+#define AT91C_PMC_PCKR             ( 0xFFFFFC40 ) /* (PMC) Programmable Clock Register */
+#define AT91C_PMC_MCKR             ( 0xFFFFFC30 ) /* (PMC) Master Clock Register */
+#define AT91C_PMC_SCDR             ( 0xFFFFFC04 ) /* (PMC) System Clock Disable Register */
+#define AT91C_PMC_PCDR             ( 0xFFFFFC14 ) /* (PMC) Peripheral Clock Disable Register */
+#define AT91C_PMC_SCSR             ( 0xFFFFFC08 ) /* (PMC) System Clock Status Register */
+#define AT91C_PMC_PCSR             ( 0xFFFFFC18 ) /* (PMC) Peripheral Clock Status Register */
+#define AT91C_PMC_MCFR             ( 0xFFFFFC24 ) /* (PMC) Main Clock  Frequency Register */
+#define AT91C_PMC_SCER             ( 0xFFFFFC00 ) /* (PMC) System Clock Enable Register */
+#define AT91C_PMC_IMR              ( 0xFFFFFC6C ) /* (PMC) Interrupt Mask Register */
+#define AT91C_PMC_IER              ( 0xFFFFFC60 ) /* (PMC) Interrupt Enable Register */
+#define AT91C_PMC_SR               ( 0xFFFFFC68 ) /* (PMC) Status Register */
+/* ========== Register definition for RSTC peripheral ========== */
+#define AT91C_RSTC_RCR             ( 0xFFFFFD00 ) /* (RSTC) Reset Control Register */
+#define AT91C_RSTC_RMR             ( 0xFFFFFD08 ) /* (RSTC) Reset Mode Register */
+#define AT91C_RSTC_RSR             ( 0xFFFFFD04 ) /* (RSTC) Reset Status Register */
+/* ========== Register definition for RTTC peripheral ========== */
+#define AT91C_RTTC_RTSR            ( 0xFFFFFD2C ) /* (RTTC) Real-time Status Register */
+#define AT91C_RTTC_RTMR            ( 0xFFFFFD20 ) /* (RTTC) Real-time Mode Register */
+#define AT91C_RTTC_RTVR            ( 0xFFFFFD28 ) /* (RTTC) Real-time Value Register */
+#define AT91C_RTTC_RTAR            ( 0xFFFFFD24 ) /* (RTTC) Real-time Alarm Register */
+/* ========== Register definition for PITC peripheral ========== */
+#define AT91C_PITC_PIVR            ( 0xFFFFFD38 ) /* (PITC) Period Interval Value Register */
+#define AT91C_PITC_PISR            ( 0xFFFFFD34 ) /* (PITC) Period Interval Status Register */
+#define AT91C_PITC_PIIR            ( 0xFFFFFD3C ) /* (PITC) Period Interval Image Register */
+#define AT91C_PITC_PIMR            ( 0xFFFFFD30 ) /* (PITC) Period Interval Mode Register */
+/* ========== Register definition for WDTC peripheral ========== */
+#define AT91C_WDTC_WDCR            ( 0xFFFFFD40 ) /* (WDTC) Watchdog Control Register */
+#define AT91C_WDTC_WDSR            ( 0xFFFFFD48 ) /* (WDTC) Watchdog Status Register */
+#define AT91C_WDTC_WDMR            ( 0xFFFFFD44 ) /* (WDTC) Watchdog Mode Register */
+/* ========== Register definition for VREG peripheral ========== */
+#define AT91C_VREG_MR              ( 0xFFFFFD60 ) /* (VREG) Voltage Regulator Mode Register */
+/* ========== Register definition for MC peripheral ========== */
+#define AT91C_MC_ASR               ( 0xFFFFFF04 ) /* (MC) MC Abort Status Register */
+#define AT91C_MC_RCR               ( 0xFFFFFF00 ) /* (MC) MC Remap Control Register */
+#define AT91C_MC_FCR               ( 0xFFFFFF64 ) /* (MC) MC Flash Command Register */
+#define AT91C_MC_AASR              ( 0xFFFFFF08 ) /* (MC) MC Abort Address Status Register */
+#define AT91C_MC_FSR               ( 0xFFFFFF68 ) /* (MC) MC Flash Status Register */
+#define AT91C_MC_FMR               ( 0xFFFFFF60 ) /* (MC) MC Flash Mode Register */
+/* ========== Register definition for PDC_SPI1 peripheral ========== */
+#define AT91C_SPI1_PTCR            ( 0xFFFE4120 ) /* (PDC_SPI1) PDC Transfer Control Register */
+#define AT91C_SPI1_RPR             ( 0xFFFE4100 ) /* (PDC_SPI1) Receive Pointer Register */
+#define AT91C_SPI1_TNCR            ( 0xFFFE411C ) /* (PDC_SPI1) Transmit Next Counter Register */
+#define AT91C_SPI1_TPR             ( 0xFFFE4108 ) /* (PDC_SPI1) Transmit Pointer Register */
+#define AT91C_SPI1_TNPR            ( 0xFFFE4118 ) /* (PDC_SPI1) Transmit Next Pointer Register */
+#define AT91C_SPI1_TCR             ( 0xFFFE410C ) /* (PDC_SPI1) Transmit Counter Register */
+#define AT91C_SPI1_RCR             ( 0xFFFE4104 ) /* (PDC_SPI1) Receive Counter Register */
+#define AT91C_SPI1_RNPR            ( 0xFFFE4110 ) /* (PDC_SPI1) Receive Next Pointer Register */
+#define AT91C_SPI1_RNCR            ( 0xFFFE4114 ) /* (PDC_SPI1) Receive Next Counter Register */
+#define AT91C_SPI1_PTSR            ( 0xFFFE4124 ) /* (PDC_SPI1) PDC Transfer Status Register */
+/* ========== Register definition for SPI1 peripheral ========== */
+#define AT91C_SPI1_IMR             ( 0xFFFE401C ) /* (SPI1) Interrupt Mask Register */
+#define AT91C_SPI1_IER             ( 0xFFFE4014 ) /* (SPI1) Interrupt Enable Register */
+#define AT91C_SPI1_MR              ( 0xFFFE4004 ) /* (SPI1) Mode Register */
+#define AT91C_SPI1_RDR             ( 0xFFFE4008 ) /* (SPI1) Receive Data Register */
+#define AT91C_SPI1_IDR             ( 0xFFFE4018 ) /* (SPI1) Interrupt Disable Register */
+#define AT91C_SPI1_SR              ( 0xFFFE4010 ) /* (SPI1) Status Register */
+#define AT91C_SPI1_TDR             ( 0xFFFE400C ) /* (SPI1) Transmit Data Register */
+#define AT91C_SPI1_CR              ( 0xFFFE4000 ) /* (SPI1) Control Register */
+#define AT91C_SPI1_CSR             ( 0xFFFE4030 ) /* (SPI1) Chip Select Register */
+/* ========== Register definition for PDC_SPI0 peripheral ========== */
+#define AT91C_SPI0_PTCR            ( 0xFFFE0120 ) /* (PDC_SPI0) PDC Transfer Control Register */
+#define AT91C_SPI0_TPR             ( 0xFFFE0108 ) /* (PDC_SPI0) Transmit Pointer Register */
+#define AT91C_SPI0_TCR             ( 0xFFFE010C ) /* (PDC_SPI0) Transmit Counter Register */
+#define AT91C_SPI0_RCR             ( 0xFFFE0104 ) /* (PDC_SPI0) Receive Counter Register */
+#define AT91C_SPI0_PTSR            ( 0xFFFE0124 ) /* (PDC_SPI0) PDC Transfer Status Register */
+#define AT91C_SPI0_RNPR            ( 0xFFFE0110 ) /* (PDC_SPI0) Receive Next Pointer Register */
+#define AT91C_SPI0_RPR             ( 0xFFFE0100 ) /* (PDC_SPI0) Receive Pointer Register */
+#define AT91C_SPI0_TNCR            ( 0xFFFE011C ) /* (PDC_SPI0) Transmit Next Counter Register */
+#define AT91C_SPI0_RNCR            ( 0xFFFE0114 ) /* (PDC_SPI0) Receive Next Counter Register */
+#define AT91C_SPI0_TNPR            ( 0xFFFE0118 ) /* (PDC_SPI0) Transmit Next Pointer Register */
+/* ========== Register definition for SPI0 peripheral ========== */
+#define AT91C_SPI0_IER             ( 0xFFFE0014 ) /* (SPI0) Interrupt Enable Register */
+#define AT91C_SPI0_SR              ( 0xFFFE0010 ) /* (SPI0) Status Register */
+#define AT91C_SPI0_IDR             ( 0xFFFE0018 ) /* (SPI0) Interrupt Disable Register */
+#define AT91C_SPI0_CR              ( 0xFFFE0000 ) /* (SPI0) Control Register */
+#define AT91C_SPI0_MR              ( 0xFFFE0004 ) /* (SPI0) Mode Register */
+#define AT91C_SPI0_IMR             ( 0xFFFE001C ) /* (SPI0) Interrupt Mask Register */
+#define AT91C_SPI0_TDR             ( 0xFFFE000C ) /* (SPI0) Transmit Data Register */
+#define AT91C_SPI0_RDR             ( 0xFFFE0008 ) /* (SPI0) Receive Data Register */
+#define AT91C_SPI0_CSR             ( 0xFFFE0030 ) /* (SPI0) Chip Select Register */
+/* ========== Register definition for PDC_US1 peripheral ========== */
+#define AT91C_US1_RNCR             ( 0xFFFC4114 ) /* (PDC_US1) Receive Next Counter Register */
+#define AT91C_US1_PTCR             ( 0xFFFC4120 ) /* (PDC_US1) PDC Transfer Control Register */
+#define AT91C_US1_TCR              ( 0xFFFC410C ) /* (PDC_US1) Transmit Counter Register */
+#define AT91C_US1_PTSR             ( 0xFFFC4124 ) /* (PDC_US1) PDC Transfer Status Register */
+#define AT91C_US1_TNPR             ( 0xFFFC4118 ) /* (PDC_US1) Transmit Next Pointer Register */
+#define AT91C_US1_RCR              ( 0xFFFC4104 ) /* (PDC_US1) Receive Counter Register */
+#define AT91C_US1_RNPR             ( 0xFFFC4110 ) /* (PDC_US1) Receive Next Pointer Register */
+#define AT91C_US1_RPR              ( 0xFFFC4100 ) /* (PDC_US1) Receive Pointer Register */
+#define AT91C_US1_TNCR             ( 0xFFFC411C ) /* (PDC_US1) Transmit Next Counter Register */
+#define AT91C_US1_TPR              ( 0xFFFC4108 ) /* (PDC_US1) Transmit Pointer Register */
+/* ========== Register definition for US1 peripheral ========== */
+#define AT91C_US1_IF               ( 0xFFFC404C ) /* (US1) IRDA_FILTER Register */
+#define AT91C_US1_NER              ( 0xFFFC4044 ) /* (US1) Nb Errors Register */
+#define AT91C_US1_RTOR             ( 0xFFFC4024 ) /* (US1) Receiver Time-out Register */
+#define AT91C_US1_CSR              ( 0xFFFC4014 ) /* (US1) Channel Status Register */
+#define AT91C_US1_IDR              ( 0xFFFC400C ) /* (US1) Interrupt Disable Register */
+#define AT91C_US1_IER              ( 0xFFFC4008 ) /* (US1) Interrupt Enable Register */
+#define AT91C_US1_THR              ( 0xFFFC401C ) /* (US1) Transmitter Holding Register */
+#define AT91C_US1_TTGR             ( 0xFFFC4028 ) /* (US1) Transmitter Time-guard Register */
+#define AT91C_US1_RHR              ( 0xFFFC4018 ) /* (US1) Receiver Holding Register */
+#define AT91C_US1_BRGR             ( 0xFFFC4020 ) /* (US1) Baud Rate Generator Register */
+#define AT91C_US1_IMR              ( 0xFFFC4010 ) /* (US1) Interrupt Mask Register */
+#define AT91C_US1_FIDI             ( 0xFFFC4040 ) /* (US1) FI_DI_Ratio Register */
+#define AT91C_US1_CR               ( 0xFFFC4000 ) /* (US1) Control Register */
+#define AT91C_US1_MR               ( 0xFFFC4004 ) /* (US1) Mode Register */
+/* ========== Register definition for PDC_US0 peripheral ========== */
+#define AT91C_US0_TNPR             ( 0xFFFC0118 ) /* (PDC_US0) Transmit Next Pointer Register */
+#define AT91C_US0_RNPR             ( 0xFFFC0110 ) /* (PDC_US0) Receive Next Pointer Register */
+#define AT91C_US0_TCR              ( 0xFFFC010C ) /* (PDC_US0) Transmit Counter Register */
+#define AT91C_US0_PTCR             ( 0xFFFC0120 ) /* (PDC_US0) PDC Transfer Control Register */
+#define AT91C_US0_PTSR             ( 0xFFFC0124 ) /* (PDC_US0) PDC Transfer Status Register */
+#define AT91C_US0_TNCR             ( 0xFFFC011C ) /* (PDC_US0) Transmit Next Counter Register */
+#define AT91C_US0_TPR              ( 0xFFFC0108 ) /* (PDC_US0) Transmit Pointer Register */
+#define AT91C_US0_RCR              ( 0xFFFC0104 ) /* (PDC_US0) Receive Counter Register */
+#define AT91C_US0_RPR              ( 0xFFFC0100 ) /* (PDC_US0) Receive Pointer Register */
+#define AT91C_US0_RNCR             ( 0xFFFC0114 ) /* (PDC_US0) Receive Next Counter Register */
+/* ========== Register definition for US0 peripheral ========== */
+#define AT91C_US0_BRGR             ( 0xFFFC0020 ) /* (US0) Baud Rate Generator Register */
+#define AT91C_US0_NER              ( 0xFFFC0044 ) /* (US0) Nb Errors Register */
+#define AT91C_US0_CR               ( 0xFFFC0000 ) /* (US0) Control Register */
+#define AT91C_US0_IMR              ( 0xFFFC0010 ) /* (US0) Interrupt Mask Register */
+#define AT91C_US0_FIDI             ( 0xFFFC0040 ) /* (US0) FI_DI_Ratio Register */
+#define AT91C_US0_TTGR             ( 0xFFFC0028 ) /* (US0) Transmitter Time-guard Register */
+#define AT91C_US0_MR               ( 0xFFFC0004 ) /* (US0) Mode Register */
+#define AT91C_US0_RTOR             ( 0xFFFC0024 ) /* (US0) Receiver Time-out Register */
+#define AT91C_US0_CSR              ( 0xFFFC0014 ) /* (US0) Channel Status Register */
+#define AT91C_US0_RHR              ( 0xFFFC0018 ) /* (US0) Receiver Holding Register */
+#define AT91C_US0_IDR              ( 0xFFFC000C ) /* (US0) Interrupt Disable Register */
+#define AT91C_US0_THR              ( 0xFFFC001C ) /* (US0) Transmitter Holding Register */
+#define AT91C_US0_IF               ( 0xFFFC004C ) /* (US0) IRDA_FILTER Register */
+#define AT91C_US0_IER              ( 0xFFFC0008 ) /* (US0) Interrupt Enable Register */
+/* ========== Register definition for PDC_SSC peripheral ========== */
+#define AT91C_SSC_TNCR             ( 0xFFFD411C ) /* (PDC_SSC) Transmit Next Counter Register */
+#define AT91C_SSC_RPR              ( 0xFFFD4100 ) /* (PDC_SSC) Receive Pointer Register */
+#define AT91C_SSC_RNCR             ( 0xFFFD4114 ) /* (PDC_SSC) Receive Next Counter Register */
+#define AT91C_SSC_TPR              ( 0xFFFD4108 ) /* (PDC_SSC) Transmit Pointer Register */
+#define AT91C_SSC_PTCR             ( 0xFFFD4120 ) /* (PDC_SSC) PDC Transfer Control Register */
+#define AT91C_SSC_TCR              ( 0xFFFD410C ) /* (PDC_SSC) Transmit Counter Register */
+#define AT91C_SSC_RCR              ( 0xFFFD4104 ) /* (PDC_SSC) Receive Counter Register */
+#define AT91C_SSC_RNPR             ( 0xFFFD4110 ) /* (PDC_SSC) Receive Next Pointer Register */
+#define AT91C_SSC_TNPR             ( 0xFFFD4118 ) /* (PDC_SSC) Transmit Next Pointer Register */
+#define AT91C_SSC_PTSR             ( 0xFFFD4124 ) /* (PDC_SSC) PDC Transfer Status Register */
+/* ========== Register definition for SSC peripheral ========== */
+#define AT91C_SSC_RHR              ( 0xFFFD4020 ) /* (SSC) Receive Holding Register */
+#define AT91C_SSC_RSHR             ( 0xFFFD4030 ) /* (SSC) Receive Sync Holding Register */
+#define AT91C_SSC_TFMR             ( 0xFFFD401C ) /* (SSC) Transmit Frame Mode Register */
+#define AT91C_SSC_IDR              ( 0xFFFD4048 ) /* (SSC) Interrupt Disable Register */
+#define AT91C_SSC_THR              ( 0xFFFD4024 ) /* (SSC) Transmit Holding Register */
+#define AT91C_SSC_RCMR             ( 0xFFFD4010 ) /* (SSC) Receive Clock ModeRegister */
+#define AT91C_SSC_IER              ( 0xFFFD4044 ) /* (SSC) Interrupt Enable Register */
+#define AT91C_SSC_TSHR             ( 0xFFFD4034 ) /* (SSC) Transmit Sync Holding Register */
+#define AT91C_SSC_SR               ( 0xFFFD4040 ) /* (SSC) Status Register */
+#define AT91C_SSC_CMR              ( 0xFFFD4004 ) /* (SSC) Clock Mode Register */
+#define AT91C_SSC_TCMR             ( 0xFFFD4018 ) /* (SSC) Transmit Clock Mode Register */
+#define AT91C_SSC_CR               ( 0xFFFD4000 ) /* (SSC) Control Register */
+#define AT91C_SSC_IMR              ( 0xFFFD404C ) /* (SSC) Interrupt Mask Register */
+#define AT91C_SSC_RFMR             ( 0xFFFD4014 ) /* (SSC) Receive Frame Mode Register */
+/* ========== Register definition for TWI peripheral ========== */
+#define AT91C_TWI_IER              ( 0xFFFB8024 ) /* (TWI) Interrupt Enable Register */
+#define AT91C_TWI_CR               ( 0xFFFB8000 ) /* (TWI) Control Register */
+#define AT91C_TWI_SR               ( 0xFFFB8020 ) /* (TWI) Status Register */
+#define AT91C_TWI_IMR              ( 0xFFFB802C ) /* (TWI) Interrupt Mask Register */
+#define AT91C_TWI_THR              ( 0xFFFB8034 ) /* (TWI) Transmit Holding Register */
+#define AT91C_TWI_IDR              ( 0xFFFB8028 ) /* (TWI) Interrupt Disable Register */
+#define AT91C_TWI_IADR             ( 0xFFFB800C ) /* (TWI) Internal Address Register */
+#define AT91C_TWI_MMR              ( 0xFFFB8004 ) /* (TWI) Master Mode Register */
+#define AT91C_TWI_CWGR             ( 0xFFFB8010 ) /* (TWI) Clock Waveform Generator Register */
+#define AT91C_TWI_RHR              ( 0xFFFB8030 ) /* (TWI) Receive Holding Register */
+/* ========== Register definition for PWMC_CH3 peripheral ========== */
+#define AT91C_PWMC_CH3_CUPDR       ( 0xFFFCC270 ) /* (PWMC_CH3) Channel Update Register */
+#define AT91C_PWMC_CH3_Reserved    ( 0xFFFCC274 ) /* (PWMC_CH3) Reserved */
+#define AT91C_PWMC_CH3_CPRDR       ( 0xFFFCC268 ) /* (PWMC_CH3) Channel Period Register */
+#define AT91C_PWMC_CH3_CDTYR       ( 0xFFFCC264 ) /* (PWMC_CH3) Channel Duty Cycle Register */
+#define AT91C_PWMC_CH3_CCNTR       ( 0xFFFCC26C ) /* (PWMC_CH3) Channel Counter Register */
+#define AT91C_PWMC_CH3_CMR         ( 0xFFFCC260 ) /* (PWMC_CH3) Channel Mode Register */
+/* ========== Register definition for PWMC_CH2 peripheral ========== */
+#define AT91C_PWMC_CH2_Reserved    ( 0xFFFCC254 ) /* (PWMC_CH2) Reserved */
+#define AT91C_PWMC_CH2_CMR         ( 0xFFFCC240 ) /* (PWMC_CH2) Channel Mode Register */
+#define AT91C_PWMC_CH2_CCNTR       ( 0xFFFCC24C ) /* (PWMC_CH2) Channel Counter Register */
+#define AT91C_PWMC_CH2_CPRDR       ( 0xFFFCC248 ) /* (PWMC_CH2) Channel Period Register */
+#define AT91C_PWMC_CH2_CUPDR       ( 0xFFFCC250 ) /* (PWMC_CH2) Channel Update Register */
+#define AT91C_PWMC_CH2_CDTYR       ( 0xFFFCC244 ) /* (PWMC_CH2) Channel Duty Cycle Register */
+/* ========== Register definition for PWMC_CH1 peripheral ========== */
+#define AT91C_PWMC_CH1_Reserved    ( 0xFFFCC234 ) /* (PWMC_CH1) Reserved */
+#define AT91C_PWMC_CH1_CUPDR       ( 0xFFFCC230 ) /* (PWMC_CH1) Channel Update Register */
+#define AT91C_PWMC_CH1_CPRDR       ( 0xFFFCC228 ) /* (PWMC_CH1) Channel Period Register */
+#define AT91C_PWMC_CH1_CCNTR       ( 0xFFFCC22C ) /* (PWMC_CH1) Channel Counter Register */
+#define AT91C_PWMC_CH1_CDTYR       ( 0xFFFCC224 ) /* (PWMC_CH1) Channel Duty Cycle Register */
+#define AT91C_PWMC_CH1_CMR         ( 0xFFFCC220 ) /* (PWMC_CH1) Channel Mode Register */
+/* ========== Register definition for PWMC_CH0 peripheral ========== */
+#define AT91C_PWMC_CH0_Reserved    ( 0xFFFCC214 ) /* (PWMC_CH0) Reserved */
+#define AT91C_PWMC_CH0_CPRDR       ( 0xFFFCC208 ) /* (PWMC_CH0) Channel Period Register */
+#define AT91C_PWMC_CH0_CDTYR       ( 0xFFFCC204 ) /* (PWMC_CH0) Channel Duty Cycle Register */
+#define AT91C_PWMC_CH0_CMR         ( 0xFFFCC200 ) /* (PWMC_CH0) Channel Mode Register */
+#define AT91C_PWMC_CH0_CUPDR       ( 0xFFFCC210 ) /* (PWMC_CH0) Channel Update Register */
+#define AT91C_PWMC_CH0_CCNTR       ( 0xFFFCC20C ) /* (PWMC_CH0) Channel Counter Register */
+/* ========== Register definition for PWMC peripheral ========== */
+#define AT91C_PWMC_IDR             ( 0xFFFCC014 ) /* (PWMC) PWMC Interrupt Disable Register */
+#define AT91C_PWMC_DIS             ( 0xFFFCC008 ) /* (PWMC) PWMC Disable Register */
+#define AT91C_PWMC_IER             ( 0xFFFCC010 ) /* (PWMC) PWMC Interrupt Enable Register */
+#define AT91C_PWMC_VR              ( 0xFFFCC0FC ) /* (PWMC) PWMC Version Register */
+#define AT91C_PWMC_ISR             ( 0xFFFCC01C ) /* (PWMC) PWMC Interrupt Status Register */
+#define AT91C_PWMC_SR              ( 0xFFFCC00C ) /* (PWMC) PWMC Status Register */
+#define AT91C_PWMC_IMR             ( 0xFFFCC018 ) /* (PWMC) PWMC Interrupt Mask Register */
+#define AT91C_PWMC_MR              ( 0xFFFCC000 ) /* (PWMC) PWMC Mode Register */
+#define AT91C_PWMC_ENA             ( 0xFFFCC004 ) /* (PWMC) PWMC Enable Register */
+/* ========== Register definition for UDP peripheral ========== */
+#define AT91C_UDP_IMR              ( 0xFFFB0018 ) /* (UDP) Interrupt Mask Register */
+#define AT91C_UDP_FADDR            ( 0xFFFB0008 ) /* (UDP) Function Address Register */
+#define AT91C_UDP_NUM              ( 0xFFFB0000 ) /* (UDP) Frame Number Register */
+#define AT91C_UDP_FDR              ( 0xFFFB0050 ) /* (UDP) Endpoint FIFO Data Register */
+#define AT91C_UDP_ISR              ( 0xFFFB001C ) /* (UDP) Interrupt Status Register */
+#define AT91C_UDP_CSR              ( 0xFFFB0030 ) /* (UDP) Endpoint Control and Status Register */
+#define AT91C_UDP_IDR              ( 0xFFFB0014 ) /* (UDP) Interrupt Disable Register */
+#define AT91C_UDP_ICR              ( 0xFFFB0020 ) /* (UDP) Interrupt Clear Register */
+#define AT91C_UDP_RSTEP            ( 0xFFFB0028 ) /* (UDP) Reset Endpoint Register */
+#define AT91C_UDP_TXVC             ( 0xFFFB0074 ) /* (UDP) Transceiver Control Register */
+#define AT91C_UDP_GLBSTATE         ( 0xFFFB0004 ) /* (UDP) Global State Register */
+#define AT91C_UDP_IER              ( 0xFFFB0010 ) /* (UDP) Interrupt Enable Register */
+/* ========== Register definition for TC0 peripheral ========== */
+#define AT91C_TC0_SR               ( 0xFFFA0020 ) /* (TC0) Status Register */
+#define AT91C_TC0_RC               ( 0xFFFA001C ) /* (TC0) Register C */
+#define AT91C_TC0_RB               ( 0xFFFA0018 ) /* (TC0) Register B */
+#define AT91C_TC0_CCR              ( 0xFFFA0000 ) /* (TC0) Channel Control Register */
+#define AT91C_TC0_CMR              ( 0xFFFA0004 ) /* (TC0) Channel Mode Register (Capture Mode / Waveform Mode) */
+#define AT91C_TC0_IER              ( 0xFFFA0024 ) /* (TC0) Interrupt Enable Register */
+#define AT91C_TC0_RA               ( 0xFFFA0014 ) /* (TC0) Register A */
+#define AT91C_TC0_IDR              ( 0xFFFA0028 ) /* (TC0) Interrupt Disable Register */
+#define AT91C_TC0_CV               ( 0xFFFA0010 ) /* (TC0) Counter Value */
+#define AT91C_TC0_IMR              ( 0xFFFA002C ) /* (TC0) Interrupt Mask Register */
+/* ========== Register definition for TC1 peripheral ========== */
+#define AT91C_TC1_RB               ( 0xFFFA0058 ) /* (TC1) Register B */
+#define AT91C_TC1_CCR              ( 0xFFFA0040 ) /* (TC1) Channel Control Register */
+#define AT91C_TC1_IER              ( 0xFFFA0064 ) /* (TC1) Interrupt Enable Register */
+#define AT91C_TC1_IDR              ( 0xFFFA0068 ) /* (TC1) Interrupt Disable Register */
+#define AT91C_TC1_SR               ( 0xFFFA0060 ) /* (TC1) Status Register */
+#define AT91C_TC1_CMR              ( 0xFFFA0044 ) /* (TC1) Channel Mode Register (Capture Mode / Waveform Mode) */
+#define AT91C_TC1_RA               ( 0xFFFA0054 ) /* (TC1) Register A */
+#define AT91C_TC1_RC               ( 0xFFFA005C ) /* (TC1) Register C */
+#define AT91C_TC1_IMR              ( 0xFFFA006C ) /* (TC1) Interrupt Mask Register */
+#define AT91C_TC1_CV               ( 0xFFFA0050 ) /* (TC1) Counter Value */
+/* ========== Register definition for TC2 peripheral ========== */
+#define AT91C_TC2_CMR              ( 0xFFFA0084 ) /* (TC2) Channel Mode Register (Capture Mode / Waveform Mode) */
+#define AT91C_TC2_CCR              ( 0xFFFA0080 ) /* (TC2) Channel Control Register */
+#define AT91C_TC2_CV               ( 0xFFFA0090 ) /* (TC2) Counter Value */
+#define AT91C_TC2_RA               ( 0xFFFA0094 ) /* (TC2) Register A */
+#define AT91C_TC2_RB               ( 0xFFFA0098 ) /* (TC2) Register B */
+#define AT91C_TC2_IDR              ( 0xFFFA00A8 ) /* (TC2) Interrupt Disable Register */
+#define AT91C_TC2_IMR              ( 0xFFFA00AC ) /* (TC2) Interrupt Mask Register */
+#define AT91C_TC2_RC               ( 0xFFFA009C ) /* (TC2) Register C */
+#define AT91C_TC2_IER              ( 0xFFFA00A4 ) /* (TC2) Interrupt Enable Register */
+#define AT91C_TC2_SR               ( 0xFFFA00A0 ) /* (TC2) Status Register */
+/* ========== Register definition for TCB peripheral ========== */
+#define AT91C_TCB_BMR              ( 0xFFFA00C4 ) /* (TCB) TC Block Mode Register */
+#define AT91C_TCB_BCR              ( 0xFFFA00C0 ) /* (TCB) TC Block Control Register */
+/* ========== Register definition for CAN_MB0 peripheral ========== */
+#define AT91C_CAN_MB0_MDL          ( 0xFFFD0214 ) /* (CAN_MB0) MailBox Data Low Register */
+#define AT91C_CAN_MB0_MAM          ( 0xFFFD0204 ) /* (CAN_MB0) MailBox Acceptance Mask Register */
+#define AT91C_CAN_MB0_MCR          ( 0xFFFD021C ) /* (CAN_MB0) MailBox Control Register */
+#define AT91C_CAN_MB0_MID          ( 0xFFFD0208 ) /* (CAN_MB0) MailBox ID Register */
+#define AT91C_CAN_MB0_MSR          ( 0xFFFD0210 ) /* (CAN_MB0) MailBox Status Register */
+#define AT91C_CAN_MB0_MFID         ( 0xFFFD020C ) /* (CAN_MB0) MailBox Family ID Register */
+#define AT91C_CAN_MB0_MDH          ( 0xFFFD0218 ) /* (CAN_MB0) MailBox Data High Register */
+#define AT91C_CAN_MB0_MMR          ( 0xFFFD0200 ) /* (CAN_MB0) MailBox Mode Register */
+/* ========== Register definition for CAN_MB1 peripheral ========== */
+#define AT91C_CAN_MB1_MDL          ( 0xFFFD0234 ) /* (CAN_MB1) MailBox Data Low Register */
+#define AT91C_CAN_MB1_MID          ( 0xFFFD0228 ) /* (CAN_MB1) MailBox ID Register */
+#define AT91C_CAN_MB1_MMR          ( 0xFFFD0220 ) /* (CAN_MB1) MailBox Mode Register */
+#define AT91C_CAN_MB1_MSR          ( 0xFFFD0230 ) /* (CAN_MB1) MailBox Status Register */
+#define AT91C_CAN_MB1_MAM          ( 0xFFFD0224 ) /* (CAN_MB1) MailBox Acceptance Mask Register */
+#define AT91C_CAN_MB1_MDH          ( 0xFFFD0238 ) /* (CAN_MB1) MailBox Data High Register */
+#define AT91C_CAN_MB1_MCR          ( 0xFFFD023C ) /* (CAN_MB1) MailBox Control Register */
+#define AT91C_CAN_MB1_MFID         ( 0xFFFD022C ) /* (CAN_MB1) MailBox Family ID Register */
+/* ========== Register definition for CAN_MB2 peripheral ========== */
+#define AT91C_CAN_MB2_MCR          ( 0xFFFD025C ) /* (CAN_MB2) MailBox Control Register */
+#define AT91C_CAN_MB2_MDH          ( 0xFFFD0258 ) /* (CAN_MB2) MailBox Data High Register */
+#define AT91C_CAN_MB2_MID          ( 0xFFFD0248 ) /* (CAN_MB2) MailBox ID Register */
+#define AT91C_CAN_MB2_MDL          ( 0xFFFD0254 ) /* (CAN_MB2) MailBox Data Low Register */
+#define AT91C_CAN_MB2_MMR          ( 0xFFFD0240 ) /* (CAN_MB2) MailBox Mode Register */
+#define AT91C_CAN_MB2_MAM          ( 0xFFFD0244 ) /* (CAN_MB2) MailBox Acceptance Mask Register */
+#define AT91C_CAN_MB2_MFID         ( 0xFFFD024C ) /* (CAN_MB2) MailBox Family ID Register */
+#define AT91C_CAN_MB2_MSR          ( 0xFFFD0250 ) /* (CAN_MB2) MailBox Status Register */
+/* ========== Register definition for CAN_MB3 peripheral ========== */
+#define AT91C_CAN_MB3_MFID         ( 0xFFFD026C ) /* (CAN_MB3) MailBox Family ID Register */
+#define AT91C_CAN_MB3_MAM          ( 0xFFFD0264 ) /* (CAN_MB3) MailBox Acceptance Mask Register */
+#define AT91C_CAN_MB3_MID          ( 0xFFFD0268 ) /* (CAN_MB3) MailBox ID Register */
+#define AT91C_CAN_MB3_MCR          ( 0xFFFD027C ) /* (CAN_MB3) MailBox Control Register */
+#define AT91C_CAN_MB3_MMR          ( 0xFFFD0260 ) /* (CAN_MB3) MailBox Mode Register */
+#define AT91C_CAN_MB3_MSR          ( 0xFFFD0270 ) /* (CAN_MB3) MailBox Status Register */
+#define AT91C_CAN_MB3_MDL          ( 0xFFFD0274 ) /* (CAN_MB3) MailBox Data Low Register */
+#define AT91C_CAN_MB3_MDH          ( 0xFFFD0278 ) /* (CAN_MB3) MailBox Data High Register */
+/* ========== Register definition for CAN_MB4 peripheral ========== */
+#define AT91C_CAN_MB4_MID          ( 0xFFFD0288 ) /* (CAN_MB4) MailBox ID Register */
+#define AT91C_CAN_MB4_MMR          ( 0xFFFD0280 ) /* (CAN_MB4) MailBox Mode Register */
+#define AT91C_CAN_MB4_MDH          ( 0xFFFD0298 ) /* (CAN_MB4) MailBox Data High Register */
+#define AT91C_CAN_MB4_MFID         ( 0xFFFD028C ) /* (CAN_MB4) MailBox Family ID Register */
+#define AT91C_CAN_MB4_MSR          ( 0xFFFD0290 ) /* (CAN_MB4) MailBox Status Register */
+#define AT91C_CAN_MB4_MCR          ( 0xFFFD029C ) /* (CAN_MB4) MailBox Control Register */
+#define AT91C_CAN_MB4_MDL          ( 0xFFFD0294 ) /* (CAN_MB4) MailBox Data Low Register */
+#define AT91C_CAN_MB4_MAM          ( 0xFFFD0284 ) /* (CAN_MB4) MailBox Acceptance Mask Register */
+/* ========== Register definition for CAN_MB5 peripheral ========== */
+#define AT91C_CAN_MB5_MSR          ( 0xFFFD02B0 ) /* (CAN_MB5) MailBox Status Register */
+#define AT91C_CAN_MB5_MCR          ( 0xFFFD02BC ) /* (CAN_MB5) MailBox Control Register */
+#define AT91C_CAN_MB5_MFID         ( 0xFFFD02AC ) /* (CAN_MB5) MailBox Family ID Register */
+#define AT91C_CAN_MB5_MDH          ( 0xFFFD02B8 ) /* (CAN_MB5) MailBox Data High Register */
+#define AT91C_CAN_MB5_MID          ( 0xFFFD02A8 ) /* (CAN_MB5) MailBox ID Register */
+#define AT91C_CAN_MB5_MMR          ( 0xFFFD02A0 ) /* (CAN_MB5) MailBox Mode Register */
+#define AT91C_CAN_MB5_MDL          ( 0xFFFD02B4 ) /* (CAN_MB5) MailBox Data Low Register */
+#define AT91C_CAN_MB5_MAM          ( 0xFFFD02A4 ) /* (CAN_MB5) MailBox Acceptance Mask Register */
+/* ========== Register definition for CAN_MB6 peripheral ========== */
+#define AT91C_CAN_MB6_MFID         ( 0xFFFD02CC ) /* (CAN_MB6) MailBox Family ID Register */
+#define AT91C_CAN_MB6_MID          ( 0xFFFD02C8 ) /* (CAN_MB6) MailBox ID Register */
+#define AT91C_CAN_MB6_MAM          ( 0xFFFD02C4 ) /* (CAN_MB6) MailBox Acceptance Mask Register */
+#define AT91C_CAN_MB6_MSR          ( 0xFFFD02D0 ) /* (CAN_MB6) MailBox Status Register */
+#define AT91C_CAN_MB6_MDL          ( 0xFFFD02D4 ) /* (CAN_MB6) MailBox Data Low Register */
+#define AT91C_CAN_MB6_MCR          ( 0xFFFD02DC ) /* (CAN_MB6) MailBox Control Register */
+#define AT91C_CAN_MB6_MDH          ( 0xFFFD02D8 ) /* (CAN_MB6) MailBox Data High Register */
+#define AT91C_CAN_MB6_MMR          ( 0xFFFD02C0 ) /* (CAN_MB6) MailBox Mode Register */
+/* ========== Register definition for CAN_MB7 peripheral ========== */
+#define AT91C_CAN_MB7_MCR          ( 0xFFFD02FC ) /* (CAN_MB7) MailBox Control Register */
+#define AT91C_CAN_MB7_MDH          ( 0xFFFD02F8 ) /* (CAN_MB7) MailBox Data High Register */
+#define AT91C_CAN_MB7_MFID         ( 0xFFFD02EC ) /* (CAN_MB7) MailBox Family ID Register */
+#define AT91C_CAN_MB7_MDL          ( 0xFFFD02F4 ) /* (CAN_MB7) MailBox Data Low Register */
+#define AT91C_CAN_MB7_MID          ( 0xFFFD02E8 ) /* (CAN_MB7) MailBox ID Register */
+#define AT91C_CAN_MB7_MMR          ( 0xFFFD02E0 ) /* (CAN_MB7) MailBox Mode Register */
+#define AT91C_CAN_MB7_MAM          ( 0xFFFD02E4 ) /* (CAN_MB7) MailBox Acceptance Mask Register */
+#define AT91C_CAN_MB7_MSR          ( 0xFFFD02F0 ) /* (CAN_MB7) MailBox Status Register */
+/* ========== Register definition for CAN peripheral ========== */
+#define AT91C_CAN_TCR              ( 0xFFFD0024 ) /* (CAN) Transfer Command Register */
+#define AT91C_CAN_IMR              ( 0xFFFD000C ) /* (CAN) Interrupt Mask Register */
+#define AT91C_CAN_IER              ( 0xFFFD0004 ) /* (CAN) Interrupt Enable Register */
+#define AT91C_CAN_ECR              ( 0xFFFD0020 ) /* (CAN) Error Counter Register */
+#define AT91C_CAN_TIMESTP          ( 0xFFFD001C ) /* (CAN) Time Stamp Register */
+#define AT91C_CAN_MR               ( 0xFFFD0000 ) /* (CAN) Mode Register */
+#define AT91C_CAN_IDR              ( 0xFFFD0008 ) /* (CAN) Interrupt Disable Register */
+#define AT91C_CAN_ACR              ( 0xFFFD0028 ) /* (CAN) Abort Command Register */
+#define AT91C_CAN_TIM              ( 0xFFFD0018 ) /* (CAN) Timer Register */
+#define AT91C_CAN_SR               ( 0xFFFD0010 ) /* (CAN) Status Register */
+#define AT91C_CAN_BR               ( 0xFFFD0014 ) /* (CAN) Baudrate Register */
+#define AT91C_CAN_VR               ( 0xFFFD00FC ) /* (CAN) Version Register */
+/* ========== Register definition for EMAC peripheral ========== */
+#define AT91C_EMAC_ISR             ( 0xFFFDC024 ) /* (EMAC) Interrupt Status Register */
+#define AT91C_EMAC_SA4H            ( 0xFFFDC0B4 ) /* (EMAC) Specific Address 4 Top, Last 2 bytes */
+#define AT91C_EMAC_SA1L            ( 0xFFFDC098 ) /* (EMAC) Specific Address 1 Bottom, First 4 bytes */
+#define AT91C_EMAC_ELE             ( 0xFFFDC078 ) /* (EMAC) Excessive Length Errors Register */
+#define AT91C_EMAC_LCOL            ( 0xFFFDC05C ) /* (EMAC) Late Collision Register */
+#define AT91C_EMAC_RLE             ( 0xFFFDC088 ) /* (EMAC) Receive Length Field Mismatch Register */
+#define AT91C_EMAC_WOL             ( 0xFFFDC0C4 ) /* (EMAC) Wake On LAN Register */
+#define AT91C_EMAC_DTF             ( 0xFFFDC058 ) /* (EMAC) Deferred Transmission Frame Register */
+#define AT91C_EMAC_TUND            ( 0xFFFDC064 ) /* (EMAC) Transmit Underrun Error Register */
+#define AT91C_EMAC_NCR             ( 0xFFFDC000 ) /* (EMAC) Network Control Register */
+#define AT91C_EMAC_SA4L            ( 0xFFFDC0B0 ) /* (EMAC) Specific Address 4 Bottom, First 4 bytes */
+#define AT91C_EMAC_RSR             ( 0xFFFDC020 ) /* (EMAC) Receive Status Register */
+#define AT91C_EMAC_SA3L            ( 0xFFFDC0A8 ) /* (EMAC) Specific Address 3 Bottom, First 4 bytes */
+#define AT91C_EMAC_TSR             ( 0xFFFDC014 ) /* (EMAC) Transmit Status Register */
+#define AT91C_EMAC_IDR             ( 0xFFFDC02C ) /* (EMAC) Interrupt Disable Register */
+#define AT91C_EMAC_RSE             ( 0xFFFDC074 ) /* (EMAC) Receive Symbol Errors Register */
+#define AT91C_EMAC_ECOL            ( 0xFFFDC060 ) /* (EMAC) Excessive Collision Register */
+#define AT91C_EMAC_TID             ( 0xFFFDC0B8 ) /* (EMAC) Type ID Checking Register */
+#define AT91C_EMAC_HRB             ( 0xFFFDC090 ) /* (EMAC) Hash Address Bottom[31:0] */
+#define AT91C_EMAC_TBQP            ( 0xFFFDC01C ) /* (EMAC) Transmit Buffer Queue Pointer */
+#define AT91C_EMAC_USRIO           ( 0xFFFDC0C0 ) /* (EMAC) USER Input/Output Register */
+#define AT91C_EMAC_PTR             ( 0xFFFDC038 ) /* (EMAC) Pause Time Register */
+#define AT91C_EMAC_SA2H            ( 0xFFFDC0A4 ) /* (EMAC) Specific Address 2 Top, Last 2 bytes */
+#define AT91C_EMAC_ROV             ( 0xFFFDC070 ) /* (EMAC) Receive Overrun Errors Register */
+#define AT91C_EMAC_ALE             ( 0xFFFDC054 ) /* (EMAC) Alignment Error Register */
+#define AT91C_EMAC_RJA             ( 0xFFFDC07C ) /* (EMAC) Receive Jabbers Register */
+#define AT91C_EMAC_RBQP            ( 0xFFFDC018 ) /* (EMAC) Receive Buffer Queue Pointer */
+#define AT91C_EMAC_TPF             ( 0xFFFDC08C ) /* (EMAC) Transmitted Pause Frames Register */
+#define AT91C_EMAC_NCFGR           ( 0xFFFDC004 ) /* (EMAC) Network Configuration Register */
+#define AT91C_EMAC_HRT             ( 0xFFFDC094 ) /* (EMAC) Hash Address Top[63:32] */
+#define AT91C_EMAC_USF             ( 0xFFFDC080 ) /* (EMAC) Undersize Frames Register */
+#define AT91C_EMAC_FCSE            ( 0xFFFDC050 ) /* (EMAC) Frame Check Sequence Error Register */
+#define AT91C_EMAC_TPQ             ( 0xFFFDC0BC ) /* (EMAC) Transmit Pause Quantum Register */
+#define AT91C_EMAC_MAN             ( 0xFFFDC034 ) /* (EMAC) PHY Maintenance Register */
+#define AT91C_EMAC_FTO             ( 0xFFFDC040 ) /* (EMAC) Frames Transmitted OK Register */
+#define AT91C_EMAC_REV             ( 0xFFFDC0FC ) /* (EMAC) Revision Register */
+#define AT91C_EMAC_IMR             ( 0xFFFDC030 ) /* (EMAC) Interrupt Mask Register */
+#define AT91C_EMAC_SCF             ( 0xFFFDC044 ) /* (EMAC) Single Collision Frame Register */
+#define AT91C_EMAC_PFR             ( 0xFFFDC03C ) /* (EMAC) Pause Frames received Register */
+#define AT91C_EMAC_MCF             ( 0xFFFDC048 ) /* (EMAC) Multiple Collision Frame Register */
+#define AT91C_EMAC_NSR             ( 0xFFFDC008 ) /* (EMAC) Network Status Register */
+#define AT91C_EMAC_SA2L            ( 0xFFFDC0A0 ) /* (EMAC) Specific Address 2 Bottom, First 4 bytes */
+#define AT91C_EMAC_FRO             ( 0xFFFDC04C ) /* (EMAC) Frames Received OK Register */
+#define AT91C_EMAC_IER             ( 0xFFFDC028 ) /* (EMAC) Interrupt Enable Register */
+#define AT91C_EMAC_SA1H            ( 0xFFFDC09C ) /* (EMAC) Specific Address 1 Top, Last 2 bytes */
+#define AT91C_EMAC_CSE             ( 0xFFFDC068 ) /* (EMAC) Carrier Sense Error Register */
+#define AT91C_EMAC_SA3H            ( 0xFFFDC0AC ) /* (EMAC) Specific Address 3 Top, Last 2 bytes */
+#define AT91C_EMAC_RRE             ( 0xFFFDC06C ) /* (EMAC) Receive Ressource Error Register */
+#define AT91C_EMAC_STE             ( 0xFFFDC084 ) /* (EMAC) SQE Test Error Register */
+/* ========== Register definition for PDC_ADC peripheral ========== */
+#define AT91C_ADC_PTSR             ( 0xFFFD8124 ) /* (PDC_ADC) PDC Transfer Status Register */
+#define AT91C_ADC_PTCR             ( 0xFFFD8120 ) /* (PDC_ADC) PDC Transfer Control Register */
+#define AT91C_ADC_TNPR             ( 0xFFFD8118 ) /* (PDC_ADC) Transmit Next Pointer Register */
+#define AT91C_ADC_TNCR             ( 0xFFFD811C ) /* (PDC_ADC) Transmit Next Counter Register */
+#define AT91C_ADC_RNPR             ( 0xFFFD8110 ) /* (PDC_ADC) Receive Next Pointer Register */
+#define AT91C_ADC_RNCR             ( 0xFFFD8114 ) /* (PDC_ADC) Receive Next Counter Register */
+#define AT91C_ADC_RPR              ( 0xFFFD8100 ) /* (PDC_ADC) Receive Pointer Register */
+#define AT91C_ADC_TCR              ( 0xFFFD810C ) /* (PDC_ADC) Transmit Counter Register */
+#define AT91C_ADC_TPR              ( 0xFFFD8108 ) /* (PDC_ADC) Transmit Pointer Register */
+#define AT91C_ADC_RCR              ( 0xFFFD8104 ) /* (PDC_ADC) Receive Counter Register */
+/* ========== Register definition for ADC peripheral ========== */
+#define AT91C_ADC_CDR2             ( 0xFFFD8038 ) /* (ADC) ADC Channel Data Register 2 */
+#define AT91C_ADC_CDR3             ( 0xFFFD803C ) /* (ADC) ADC Channel Data Register 3 */
+#define AT91C_ADC_CDR0             ( 0xFFFD8030 ) /* (ADC) ADC Channel Data Register 0 */
+#define AT91C_ADC_CDR5             ( 0xFFFD8044 ) /* (ADC) ADC Channel Data Register 5 */
+#define AT91C_ADC_CHDR             ( 0xFFFD8014 ) /* (ADC) ADC Channel Disable Register */
+#define AT91C_ADC_SR               ( 0xFFFD801C ) /* (ADC) ADC Status Register */
+#define AT91C_ADC_CDR4             ( 0xFFFD8040 ) /* (ADC) ADC Channel Data Register 4 */
+#define AT91C_ADC_CDR1             ( 0xFFFD8034 ) /* (ADC) ADC Channel Data Register 1 */
+#define AT91C_ADC_LCDR             ( 0xFFFD8020 ) /* (ADC) ADC Last Converted Data Register */
+#define AT91C_ADC_IDR              ( 0xFFFD8028 ) /* (ADC) ADC Interrupt Disable Register */
+#define AT91C_ADC_CR               ( 0xFFFD8000 ) /* (ADC) ADC Control Register */
+#define AT91C_ADC_CDR7             ( 0xFFFD804C ) /* (ADC) ADC Channel Data Register 7 */
+#define AT91C_ADC_CDR6             ( 0xFFFD8048 ) /* (ADC) ADC Channel Data Register 6 */
+#define AT91C_ADC_IER              ( 0xFFFD8024 ) /* (ADC) ADC Interrupt Enable Register */
+#define AT91C_ADC_CHER             ( 0xFFFD8010 ) /* (ADC) ADC Channel Enable Register */
+#define AT91C_ADC_CHSR             ( 0xFFFD8018 ) /* (ADC) ADC Channel Status Register */
+#define AT91C_ADC_MR               ( 0xFFFD8004 ) /* (ADC) ADC Mode Register */
+#define AT91C_ADC_IMR              ( 0xFFFD802C ) /* (ADC) ADC Interrupt Mask Register */
+/* ========== Register definition for PDC_AES peripheral ========== */
+#define AT91C_AES_TPR              ( 0xFFFA4108 ) /* (PDC_AES) Transmit Pointer Register */
+#define AT91C_AES_PTCR             ( 0xFFFA4120 ) /* (PDC_AES) PDC Transfer Control Register */
+#define AT91C_AES_RNPR             ( 0xFFFA4110 ) /* (PDC_AES) Receive Next Pointer Register */
+#define AT91C_AES_TNCR             ( 0xFFFA411C ) /* (PDC_AES) Transmit Next Counter Register */
+#define AT91C_AES_TCR              ( 0xFFFA410C ) /* (PDC_AES) Transmit Counter Register */
+#define AT91C_AES_RCR              ( 0xFFFA4104 ) /* (PDC_AES) Receive Counter Register */
+#define AT91C_AES_RNCR             ( 0xFFFA4114 ) /* (PDC_AES) Receive Next Counter Register */
+#define AT91C_AES_TNPR             ( 0xFFFA4118 ) /* (PDC_AES) Transmit Next Pointer Register */
+#define AT91C_AES_RPR              ( 0xFFFA4100 ) /* (PDC_AES) Receive Pointer Register */
+#define AT91C_AES_PTSR             ( 0xFFFA4124 ) /* (PDC_AES) PDC Transfer Status Register */
+/* ========== Register definition for AES peripheral ========== */
+#define AT91C_AES_IVxR             ( 0xFFFA4060 ) /* (AES) Initialization Vector x Register */
+#define AT91C_AES_MR               ( 0xFFFA4004 ) /* (AES) Mode Register */
+#define AT91C_AES_VR               ( 0xFFFA40FC ) /* (AES) AES Version Register */
+#define AT91C_AES_ODATAxR          ( 0xFFFA4050 ) /* (AES) Output Data x Register */
+#define AT91C_AES_IDATAxR          ( 0xFFFA4040 ) /* (AES) Input Data x Register */
+#define AT91C_AES_CR               ( 0xFFFA4000 ) /* (AES) Control Register */
+#define AT91C_AES_IDR              ( 0xFFFA4014 ) /* (AES) Interrupt Disable Register */
+#define AT91C_AES_IMR              ( 0xFFFA4018 ) /* (AES) Interrupt Mask Register */
+#define AT91C_AES_IER              ( 0xFFFA4010 ) /* (AES) Interrupt Enable Register */
+#define AT91C_AES_KEYWxR           ( 0xFFFA4020 ) /* (AES) Key Word x Register */
+#define AT91C_AES_ISR              ( 0xFFFA401C ) /* (AES) Interrupt Status Register */
+/* ========== Register definition for PDC_TDES peripheral ========== */
+#define AT91C_TDES_RNCR            ( 0xFFFA8114 ) /* (PDC_TDES) Receive Next Counter Register */
+#define AT91C_TDES_TCR             ( 0xFFFA810C ) /* (PDC_TDES) Transmit Counter Register */
+#define AT91C_TDES_RCR             ( 0xFFFA8104 ) /* (PDC_TDES) Receive Counter Register */
+#define AT91C_TDES_TNPR            ( 0xFFFA8118 ) /* (PDC_TDES) Transmit Next Pointer Register */
+#define AT91C_TDES_RNPR            ( 0xFFFA8110 ) /* (PDC_TDES) Receive Next Pointer Register */
+#define AT91C_TDES_RPR             ( 0xFFFA8100 ) /* (PDC_TDES) Receive Pointer Register */
+#define AT91C_TDES_TNCR            ( 0xFFFA811C ) /* (PDC_TDES) Transmit Next Counter Register */
+#define AT91C_TDES_TPR             ( 0xFFFA8108 ) /* (PDC_TDES) Transmit Pointer Register */
+#define AT91C_TDES_PTSR            ( 0xFFFA8124 ) /* (PDC_TDES) PDC Transfer Status Register */
+#define AT91C_TDES_PTCR            ( 0xFFFA8120 ) /* (PDC_TDES) PDC Transfer Control Register */
+/* ========== Register definition for TDES peripheral ========== */
+#define AT91C_TDES_KEY2WxR         ( 0xFFFA8028 ) /* (TDES) Key 2 Word x Register */
+#define AT91C_TDES_KEY3WxR         ( 0xFFFA8030 ) /* (TDES) Key 3 Word x Register */
+#define AT91C_TDES_IDR             ( 0xFFFA8014 ) /* (TDES) Interrupt Disable Register */
+#define AT91C_TDES_VR              ( 0xFFFA80FC ) /* (TDES) TDES Version Register */
+#define AT91C_TDES_IVxR            ( 0xFFFA8060 ) /* (TDES) Initialization Vector x Register */
+#define AT91C_TDES_ODATAxR         ( 0xFFFA8050 ) /* (TDES) Output Data x Register */
+#define AT91C_TDES_IMR             ( 0xFFFA8018 ) /* (TDES) Interrupt Mask Register */
+#define AT91C_TDES_MR              ( 0xFFFA8004 ) /* (TDES) Mode Register */
+#define AT91C_TDES_CR              ( 0xFFFA8000 ) /* (TDES) Control Register */
+#define AT91C_TDES_IER             ( 0xFFFA8010 ) /* (TDES) Interrupt Enable Register */
+#define AT91C_TDES_ISR             ( 0xFFFA801C ) /* (TDES) Interrupt Status Register */
+#define AT91C_TDES_IDATAxR         ( 0xFFFA8040 ) /* (TDES) Input Data x Register */
+#define AT91C_TDES_KEY1WxR         ( 0xFFFA8020 ) /* (TDES) Key 1 Word x Register */
 
-// *****************************************************************************
-//               PIO DEFINITIONS FOR AT91SAM7X128
-// *****************************************************************************
-#define AT91C_PIO_PA0             (1 <<  0) // Pin Controlled by PA0
-#define AT91C_PA0_RXD0            (AT91C_PIO_PA0) //  USART 0 Receive Data
-#define AT91C_PIO_PA1             (1 <<  1) // Pin Controlled by PA1
-#define AT91C_PA1_TXD0            (AT91C_PIO_PA1) //  USART 0 Transmit Data
-#define AT91C_PIO_PA10            (1 << 10) // Pin Controlled by PA10
-#define AT91C_PA10_TWD            (AT91C_PIO_PA10) //  TWI Two-wire Serial Data
-#define AT91C_PIO_PA11            (1 << 11) // Pin Controlled by PA11
-#define AT91C_PA11_TWCK           (AT91C_PIO_PA11) //  TWI Two-wire Serial Clock
-#define AT91C_PIO_PA12            (1 << 12) // Pin Controlled by PA12
-#define AT91C_PA12_NPCS00         (AT91C_PIO_PA12) //  SPI 0 Peripheral Chip Select 0
-#define AT91C_PIO_PA13            (1 << 13) // Pin Controlled by PA13
-#define AT91C_PA13_NPCS01         (AT91C_PIO_PA13) //  SPI 0 Peripheral Chip Select 1
-#define AT91C_PA13_PCK1           (AT91C_PIO_PA13) //  PMC Programmable Clock Output 1
-#define AT91C_PIO_PA14            (1 << 14) // Pin Controlled by PA14
-#define AT91C_PA14_NPCS02         (AT91C_PIO_PA14) //  SPI 0 Peripheral Chip Select 2
-#define AT91C_PA14_IRQ1           (AT91C_PIO_PA14) //  External Interrupt 1
-#define AT91C_PIO_PA15            (1 << 15) // Pin Controlled by PA15
-#define AT91C_PA15_NPCS03         (AT91C_PIO_PA15) //  SPI 0 Peripheral Chip Select 3
-#define AT91C_PA15_TCLK2          (AT91C_PIO_PA15) //  Timer Counter 2 external clock input
-#define AT91C_PIO_PA16            (1 << 16) // Pin Controlled by PA16
-#define AT91C_PA16_MISO0          (AT91C_PIO_PA16) //  SPI 0 Master In Slave
-#define AT91C_PIO_PA17            (1 << 17) // Pin Controlled by PA17
-#define AT91C_PA17_MOSI0          (AT91C_PIO_PA17) //  SPI 0 Master Out Slave
-#define AT91C_PIO_PA18            (1 << 18) // Pin Controlled by PA18
-#define AT91C_PA18_SPCK0          (AT91C_PIO_PA18) //  SPI 0 Serial Clock
-#define AT91C_PIO_PA19            (1 << 19) // Pin Controlled by PA19
-#define AT91C_PA19_CANRX          (AT91C_PIO_PA19) //  CAN Receive
-#define AT91C_PIO_PA2             (1 <<  2) // Pin Controlled by PA2
-#define AT91C_PA2_SCK0            (AT91C_PIO_PA2) //  USART 0 Serial Clock
-#define AT91C_PA2_NPCS11          (AT91C_PIO_PA2) //  SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PA20            (1 << 20) // Pin Controlled by PA20
-#define AT91C_PA20_CANTX          (AT91C_PIO_PA20) //  CAN Transmit
-#define AT91C_PIO_PA21            (1 << 21) // Pin Controlled by PA21
-#define AT91C_PA21_TF             (AT91C_PIO_PA21) //  SSC Transmit Frame Sync
-#define AT91C_PA21_NPCS10         (AT91C_PIO_PA21) //  SPI 1 Peripheral Chip Select 0
-#define AT91C_PIO_PA22            (1 << 22) // Pin Controlled by PA22
-#define AT91C_PA22_TK             (AT91C_PIO_PA22) //  SSC Transmit Clock
-#define AT91C_PA22_SPCK1          (AT91C_PIO_PA22) //  SPI 1 Serial Clock
-#define AT91C_PIO_PA23            (1 << 23) // Pin Controlled by PA23
-#define AT91C_PA23_TD             (AT91C_PIO_PA23) //  SSC Transmit data
-#define AT91C_PA23_MOSI1          (AT91C_PIO_PA23) //  SPI 1 Master Out Slave
-#define AT91C_PIO_PA24            (1 << 24) // Pin Controlled by PA24
-#define AT91C_PA24_RD             (AT91C_PIO_PA24) //  SSC Receive Data
-#define AT91C_PA24_MISO1          (AT91C_PIO_PA24) //  SPI 1 Master In Slave
-#define AT91C_PIO_PA25            (1 << 25) // Pin Controlled by PA25
-#define AT91C_PA25_RK             (AT91C_PIO_PA25) //  SSC Receive Clock
-#define AT91C_PA25_NPCS11         (AT91C_PIO_PA25) //  SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PA26            (1 << 26) // Pin Controlled by PA26
-#define AT91C_PA26_RF             (AT91C_PIO_PA26) //  SSC Receive Frame Sync
-#define AT91C_PA26_NPCS12         (AT91C_PIO_PA26) //  SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PA27            (1 << 27) // Pin Controlled by PA27
-#define AT91C_PA27_DRXD           (AT91C_PIO_PA27) //  DBGU Debug Receive Data
-#define AT91C_PA27_PCK3           (AT91C_PIO_PA27) //  PMC Programmable Clock Output 3
-#define AT91C_PIO_PA28            (1 << 28) // Pin Controlled by PA28
-#define AT91C_PA28_DTXD           (AT91C_PIO_PA28) //  DBGU Debug Transmit Data
-#define AT91C_PIO_PA29            (1 << 29) // Pin Controlled by PA29
-#define AT91C_PA29_FIQ            (AT91C_PIO_PA29) //  AIC Fast Interrupt Input
-#define AT91C_PA29_NPCS13         (AT91C_PIO_PA29) //  SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PA3             (1 <<  3) // Pin Controlled by PA3
-#define AT91C_PA3_RTS0            (AT91C_PIO_PA3) //  USART 0 Ready To Send
-#define AT91C_PA3_NPCS12          (AT91C_PIO_PA3) //  SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PA30            (1 << 30) // Pin Controlled by PA30
-#define AT91C_PA30_IRQ0           (AT91C_PIO_PA30) //  External Interrupt 0
-#define AT91C_PA30_PCK2           (AT91C_PIO_PA30) //  PMC Programmable Clock Output 2
-#define AT91C_PIO_PA4             (1 <<  4) // Pin Controlled by PA4
-#define AT91C_PA4_CTS0            (AT91C_PIO_PA4) //  USART 0 Clear To Send
-#define AT91C_PA4_NPCS13          (AT91C_PIO_PA4) //  SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PA5             (1 <<  5) // Pin Controlled by PA5
-#define AT91C_PA5_RXD1            (AT91C_PIO_PA5) //  USART 1 Receive Data
-#define AT91C_PIO_PA6             (1 <<  6) // Pin Controlled by PA6
-#define AT91C_PA6_TXD1            (AT91C_PIO_PA6) //  USART 1 Transmit Data
-#define AT91C_PIO_PA7             (1 <<  7) // Pin Controlled by PA7
-#define AT91C_PA7_SCK1            (AT91C_PIO_PA7) //  USART 1 Serial Clock
-#define AT91C_PA7_NPCS01          (AT91C_PIO_PA7) //  SPI 0 Peripheral Chip Select 1
-#define AT91C_PIO_PA8             (1 <<  8) // Pin Controlled by PA8
-#define AT91C_PA8_RTS1            (AT91C_PIO_PA8) //  USART 1 Ready To Send
-#define AT91C_PA8_NPCS02          (AT91C_PIO_PA8) //  SPI 0 Peripheral Chip Select 2
-#define AT91C_PIO_PA9             (1 <<  9) // Pin Controlled by PA9
-#define AT91C_PA9_CTS1            (AT91C_PIO_PA9) //  USART 1 Clear To Send
-#define AT91C_PA9_NPCS03          (AT91C_PIO_PA9) //  SPI 0 Peripheral Chip Select 3
-#define AT91C_PIO_PB0             (1 <<  0) // Pin Controlled by PB0
-#define AT91C_PB0_ETXCK_EREFCK    (AT91C_PIO_PB0) //  Ethernet MAC Transmit Clock/Reference Clock
-#define AT91C_PB0_PCK0            (AT91C_PIO_PB0) //  PMC Programmable Clock Output 0
-#define AT91C_PIO_PB1             (1 <<  1) // Pin Controlled by PB1
-#define AT91C_PB1_ETXEN           (AT91C_PIO_PB1) //  Ethernet MAC Transmit Enable
-#define AT91C_PIO_PB10            (1 << 10) // Pin Controlled by PB10
-#define AT91C_PB10_ETX2           (AT91C_PIO_PB10) //  Ethernet MAC Transmit Data 2
-#define AT91C_PB10_NPCS11         (AT91C_PIO_PB10) //  SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PB11            (1 << 11) // Pin Controlled by PB11
-#define AT91C_PB11_ETX3           (AT91C_PIO_PB11) //  Ethernet MAC Transmit Data 3
-#define AT91C_PB11_NPCS12         (AT91C_PIO_PB11) //  SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PB12            (1 << 12) // Pin Controlled by PB12
-#define AT91C_PB12_ETXER          (AT91C_PIO_PB12) //  Ethernet MAC Transmikt Coding Error
-#define AT91C_PB12_TCLK0          (AT91C_PIO_PB12) //  Timer Counter 0 external clock input
-#define AT91C_PIO_PB13            (1 << 13) // Pin Controlled by PB13
-#define AT91C_PB13_ERX2           (AT91C_PIO_PB13) //  Ethernet MAC Receive Data 2
-#define AT91C_PB13_NPCS01         (AT91C_PIO_PB13) //  SPI 0 Peripheral Chip Select 1
-#define AT91C_PIO_PB14            (1 << 14) // Pin Controlled by PB14
-#define AT91C_PB14_ERX3           (AT91C_PIO_PB14) //  Ethernet MAC Receive Data 3
-#define AT91C_PB14_NPCS02         (AT91C_PIO_PB14) //  SPI 0 Peripheral Chip Select 2
-#define AT91C_PIO_PB15            (1 << 15) // Pin Controlled by PB15
-#define AT91C_PB15_ERXDV          (AT91C_PIO_PB15) //  Ethernet MAC Receive Data Valid
-#define AT91C_PIO_PB16            (1 << 16) // Pin Controlled by PB16
-#define AT91C_PB16_ECOL           (AT91C_PIO_PB16) //  Ethernet MAC Collision Detected
-#define AT91C_PB16_NPCS13         (AT91C_PIO_PB16) //  SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PB17            (1 << 17) // Pin Controlled by PB17
-#define AT91C_PB17_ERXCK          (AT91C_PIO_PB17) //  Ethernet MAC Receive Clock
-#define AT91C_PB17_NPCS03         (AT91C_PIO_PB17) //  SPI 0 Peripheral Chip Select 3
-#define AT91C_PIO_PB18            (1 << 18) // Pin Controlled by PB18
-#define AT91C_PB18_EF100          (AT91C_PIO_PB18) //  Ethernet MAC Force 100 Mbits/sec
-#define AT91C_PB18_ADTRG          (AT91C_PIO_PB18) //  ADC External Trigger
-#define AT91C_PIO_PB19            (1 << 19) // Pin Controlled by PB19
-#define AT91C_PB19_PWM0           (AT91C_PIO_PB19) //  PWM Channel 0
-#define AT91C_PB19_TCLK1          (AT91C_PIO_PB19) //  Timer Counter 1 external clock input
-#define AT91C_PIO_PB2             (1 <<  2) // Pin Controlled by PB2
-#define AT91C_PB2_ETX0            (AT91C_PIO_PB2) //  Ethernet MAC Transmit Data 0
-#define AT91C_PIO_PB20            (1 << 20) // Pin Controlled by PB20
-#define AT91C_PB20_PWM1           (AT91C_PIO_PB20) //  PWM Channel 1
-#define AT91C_PB20_PCK0           (AT91C_PIO_PB20) //  PMC Programmable Clock Output 0
-#define AT91C_PIO_PB21            (1 << 21) // Pin Controlled by PB21
-#define AT91C_PB21_PWM2           (AT91C_PIO_PB21) //  PWM Channel 2
-#define AT91C_PB21_PCK1           (AT91C_PIO_PB21) //  PMC Programmable Clock Output 1
-#define AT91C_PIO_PB22            (1 << 22) // Pin Controlled by PB22
-#define AT91C_PB22_PWM3           (AT91C_PIO_PB22) //  PWM Channel 3
-#define AT91C_PB22_PCK2           (AT91C_PIO_PB22) //  PMC Programmable Clock Output 2
-#define AT91C_PIO_PB23            (1 << 23) // Pin Controlled by PB23
-#define AT91C_PB23_TIOA0          (AT91C_PIO_PB23) //  Timer Counter 0 Multipurpose Timer I/O Pin A
-#define AT91C_PB23_DCD1           (AT91C_PIO_PB23) //  USART 1 Data Carrier Detect
-#define AT91C_PIO_PB24            (1 << 24) // Pin Controlled by PB24
-#define AT91C_PB24_TIOB0          (AT91C_PIO_PB24) //  Timer Counter 0 Multipurpose Timer I/O Pin B
-#define AT91C_PB24_DSR1           (AT91C_PIO_PB24) //  USART 1 Data Set ready
-#define AT91C_PIO_PB25            (1 << 25) // Pin Controlled by PB25
-#define AT91C_PB25_TIOA1          (AT91C_PIO_PB25) //  Timer Counter 1 Multipurpose Timer I/O Pin A
-#define AT91C_PB25_DTR1           (AT91C_PIO_PB25) //  USART 1 Data Terminal ready
-#define AT91C_PIO_PB26            (1 << 26) // Pin Controlled by PB26
-#define AT91C_PB26_TIOB1          (AT91C_PIO_PB26) //  Timer Counter 1 Multipurpose Timer I/O Pin B
-#define AT91C_PB26_RI1            (AT91C_PIO_PB26) //  USART 1 Ring Indicator
-#define AT91C_PIO_PB27            (1 << 27) // Pin Controlled by PB27
-#define AT91C_PB27_TIOA2          (AT91C_PIO_PB27) //  Timer Counter 2 Multipurpose Timer I/O Pin A
-#define AT91C_PB27_PWM0           (AT91C_PIO_PB27) //  PWM Channel 0
-#define AT91C_PIO_PB28            (1 << 28) // Pin Controlled by PB28
-#define AT91C_PB28_TIOB2          (AT91C_PIO_PB28) //  Timer Counter 2 Multipurpose Timer I/O Pin B
-#define AT91C_PB28_PWM1           (AT91C_PIO_PB28) //  PWM Channel 1
-#define AT91C_PIO_PB29            (1 << 29) // Pin Controlled by PB29
-#define AT91C_PB29_PCK1           (AT91C_PIO_PB29) //  PMC Programmable Clock Output 1
-#define AT91C_PB29_PWM2           (AT91C_PIO_PB29) //  PWM Channel 2
-#define AT91C_PIO_PB3             (1 <<  3) // Pin Controlled by PB3
-#define AT91C_PB3_ETX1            (AT91C_PIO_PB3) //  Ethernet MAC Transmit Data 1
-#define AT91C_PIO_PB30            (1 << 30) // Pin Controlled by PB30
-#define AT91C_PB30_PCK2           (AT91C_PIO_PB30) //  PMC Programmable Clock Output 2
-#define AT91C_PB30_PWM3           (AT91C_PIO_PB30) //  PWM Channel 3
-#define AT91C_PIO_PB4             (1 <<  4) // Pin Controlled by PB4
-#define AT91C_PB4_ECRS_ECRSDV     (AT91C_PIO_PB4) //  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
-#define AT91C_PIO_PB5             (1 <<  5) // Pin Controlled by PB5
-#define AT91C_PB5_ERX0            (AT91C_PIO_PB5) //  Ethernet MAC Receive Data 0
-#define AT91C_PIO_PB6             (1 <<  6) // Pin Controlled by PB6
-#define AT91C_PB6_ERX1            (AT91C_PIO_PB6) //  Ethernet MAC Receive Data 1
-#define AT91C_PIO_PB7             (1 <<  7) // Pin Controlled by PB7
-#define AT91C_PB7_ERXER           (AT91C_PIO_PB7) //  Ethernet MAC Receive Error
-#define AT91C_PIO_PB8             (1 <<  8) // Pin Controlled by PB8
-#define AT91C_PB8_EMDC            (AT91C_PIO_PB8) //  Ethernet MAC Management Data Clock
-#define AT91C_PIO_PB9             (1 <<  9) // Pin Controlled by PB9
-#define AT91C_PB9_EMDIO           (AT91C_PIO_PB9) //  Ethernet MAC Management Data Input/Output
+/* ***************************************************************************** */
+/*               PIO DEFINITIONS FOR AT91SAM7X128 */
+/* ***************************************************************************** */
+#define AT91C_PIO_PA0             ( 1 << 0 )         /* Pin Controlled by PA0 */
+#define AT91C_PA0_RXD0            ( AT91C_PIO_PA0 )  /*  USART 0 Receive Data */
+#define AT91C_PIO_PA1             ( 1 << 1 )         /* Pin Controlled by PA1 */
+#define AT91C_PA1_TXD0            ( AT91C_PIO_PA1 )  /*  USART 0 Transmit Data */
+#define AT91C_PIO_PA10            ( 1 << 10 )        /* Pin Controlled by PA10 */
+#define AT91C_PA10_TWD            ( AT91C_PIO_PA10 ) /*  TWI Two-wire Serial Data */
+#define AT91C_PIO_PA11            ( 1 << 11 )        /* Pin Controlled by PA11 */
+#define AT91C_PA11_TWCK           ( AT91C_PIO_PA11 ) /*  TWI Two-wire Serial Clock */
+#define AT91C_PIO_PA12            ( 1 << 12 )        /* Pin Controlled by PA12 */
+#define AT91C_PA12_NPCS00         ( AT91C_PIO_PA12 ) /*  SPI 0 Peripheral Chip Select 0 */
+#define AT91C_PIO_PA13            ( 1 << 13 )        /* Pin Controlled by PA13 */
+#define AT91C_PA13_NPCS01         ( AT91C_PIO_PA13 ) /*  SPI 0 Peripheral Chip Select 1 */
+#define AT91C_PA13_PCK1           ( AT91C_PIO_PA13 ) /*  PMC Programmable Clock Output 1 */
+#define AT91C_PIO_PA14            ( 1 << 14 )        /* Pin Controlled by PA14 */
+#define AT91C_PA14_NPCS02         ( AT91C_PIO_PA14 ) /*  SPI 0 Peripheral Chip Select 2 */
+#define AT91C_PA14_IRQ1           ( AT91C_PIO_PA14 ) /*  External Interrupt 1 */
+#define AT91C_PIO_PA15            ( 1 << 15 )        /* Pin Controlled by PA15 */
+#define AT91C_PA15_NPCS03         ( AT91C_PIO_PA15 ) /*  SPI 0 Peripheral Chip Select 3 */
+#define AT91C_PA15_TCLK2          ( AT91C_PIO_PA15 ) /*  Timer Counter 2 external clock input */
+#define AT91C_PIO_PA16            ( 1 << 16 )        /* Pin Controlled by PA16 */
+#define AT91C_PA16_MISO0          ( AT91C_PIO_PA16 ) /*  SPI 0 Master In Slave */
+#define AT91C_PIO_PA17            ( 1 << 17 )        /* Pin Controlled by PA17 */
+#define AT91C_PA17_MOSI0          ( AT91C_PIO_PA17 ) /*  SPI 0 Master Out Slave */
+#define AT91C_PIO_PA18            ( 1 << 18 )        /* Pin Controlled by PA18 */
+#define AT91C_PA18_SPCK0          ( AT91C_PIO_PA18 ) /*  SPI 0 Serial Clock */
+#define AT91C_PIO_PA19            ( 1 << 19 )        /* Pin Controlled by PA19 */
+#define AT91C_PA19_CANRX          ( AT91C_PIO_PA19 ) /*  CAN Receive */
+#define AT91C_PIO_PA2             ( 1 << 2 )         /* Pin Controlled by PA2 */
+#define AT91C_PA2_SCK0            ( AT91C_PIO_PA2 )  /*  USART 0 Serial Clock */
+#define AT91C_PA2_NPCS11          ( AT91C_PIO_PA2 )  /*  SPI 1 Peripheral Chip Select 1 */
+#define AT91C_PIO_PA20            ( 1 << 20 )        /* Pin Controlled by PA20 */
+#define AT91C_PA20_CANTX          ( AT91C_PIO_PA20 ) /*  CAN Transmit */
+#define AT91C_PIO_PA21            ( 1 << 21 )        /* Pin Controlled by PA21 */
+#define AT91C_PA21_TF             ( AT91C_PIO_PA21 ) /*  SSC Transmit Frame Sync */
+#define AT91C_PA21_NPCS10         ( AT91C_PIO_PA21 ) /*  SPI 1 Peripheral Chip Select 0 */
+#define AT91C_PIO_PA22            ( 1 << 22 )        /* Pin Controlled by PA22 */
+#define AT91C_PA22_TK             ( AT91C_PIO_PA22 ) /*  SSC Transmit Clock */
+#define AT91C_PA22_SPCK1          ( AT91C_PIO_PA22 ) /*  SPI 1 Serial Clock */
+#define AT91C_PIO_PA23            ( 1 << 23 )        /* Pin Controlled by PA23 */
+#define AT91C_PA23_TD             ( AT91C_PIO_PA23 ) /*  SSC Transmit data */
+#define AT91C_PA23_MOSI1          ( AT91C_PIO_PA23 ) /*  SPI 1 Master Out Slave */
+#define AT91C_PIO_PA24            ( 1 << 24 )        /* Pin Controlled by PA24 */
+#define AT91C_PA24_RD             ( AT91C_PIO_PA24 ) /*  SSC Receive Data */
+#define AT91C_PA24_MISO1          ( AT91C_PIO_PA24 ) /*  SPI 1 Master In Slave */
+#define AT91C_PIO_PA25            ( 1 << 25 )        /* Pin Controlled by PA25 */
+#define AT91C_PA25_RK             ( AT91C_PIO_PA25 ) /*  SSC Receive Clock */
+#define AT91C_PA25_NPCS11         ( AT91C_PIO_PA25 ) /*  SPI 1 Peripheral Chip Select 1 */
+#define AT91C_PIO_PA26            ( 1 << 26 )        /* Pin Controlled by PA26 */
+#define AT91C_PA26_RF             ( AT91C_PIO_PA26 ) /*  SSC Receive Frame Sync */
+#define AT91C_PA26_NPCS12         ( AT91C_PIO_PA26 ) /*  SPI 1 Peripheral Chip Select 2 */
+#define AT91C_PIO_PA27            ( 1 << 27 )        /* Pin Controlled by PA27 */
+#define AT91C_PA27_DRXD           ( AT91C_PIO_PA27 ) /*  DBGU Debug Receive Data */
+#define AT91C_PA27_PCK3           ( AT91C_PIO_PA27 ) /*  PMC Programmable Clock Output 3 */
+#define AT91C_PIO_PA28            ( 1 << 28 )        /* Pin Controlled by PA28 */
+#define AT91C_PA28_DTXD           ( AT91C_PIO_PA28 ) /*  DBGU Debug Transmit Data */
+#define AT91C_PIO_PA29            ( 1 << 29 )        /* Pin Controlled by PA29 */
+#define AT91C_PA29_FIQ            ( AT91C_PIO_PA29 ) /*  AIC Fast Interrupt Input */
+#define AT91C_PA29_NPCS13         ( AT91C_PIO_PA29 ) /*  SPI 1 Peripheral Chip Select 3 */
+#define AT91C_PIO_PA3             ( 1 << 3 )         /* Pin Controlled by PA3 */
+#define AT91C_PA3_RTS0            ( AT91C_PIO_PA3 )  /*  USART 0 Ready To Send */
+#define AT91C_PA3_NPCS12          ( AT91C_PIO_PA3 )  /*  SPI 1 Peripheral Chip Select 2 */
+#define AT91C_PIO_PA30            ( 1 << 30 )        /* Pin Controlled by PA30 */
+#define AT91C_PA30_IRQ0           ( AT91C_PIO_PA30 ) /*  External Interrupt 0 */
+#define AT91C_PA30_PCK2           ( AT91C_PIO_PA30 ) /*  PMC Programmable Clock Output 2 */
+#define AT91C_PIO_PA4             ( 1 << 4 )         /* Pin Controlled by PA4 */
+#define AT91C_PA4_CTS0            ( AT91C_PIO_PA4 )  /*  USART 0 Clear To Send */
+#define AT91C_PA4_NPCS13          ( AT91C_PIO_PA4 )  /*  SPI 1 Peripheral Chip Select 3 */
+#define AT91C_PIO_PA5             ( 1 << 5 )         /* Pin Controlled by PA5 */
+#define AT91C_PA5_RXD1            ( AT91C_PIO_PA5 )  /*  USART 1 Receive Data */
+#define AT91C_PIO_PA6             ( 1 << 6 )         /* Pin Controlled by PA6 */
+#define AT91C_PA6_TXD1            ( AT91C_PIO_PA6 )  /*  USART 1 Transmit Data */
+#define AT91C_PIO_PA7             ( 1 << 7 )         /* Pin Controlled by PA7 */
+#define AT91C_PA7_SCK1            ( AT91C_PIO_PA7 )  /*  USART 1 Serial Clock */
+#define AT91C_PA7_NPCS01          ( AT91C_PIO_PA7 )  /*  SPI 0 Peripheral Chip Select 1 */
+#define AT91C_PIO_PA8             ( 1 << 8 )         /* Pin Controlled by PA8 */
+#define AT91C_PA8_RTS1            ( AT91C_PIO_PA8 )  /*  USART 1 Ready To Send */
+#define AT91C_PA8_NPCS02          ( AT91C_PIO_PA8 )  /*  SPI 0 Peripheral Chip Select 2 */
+#define AT91C_PIO_PA9             ( 1 << 9 )         /* Pin Controlled by PA9 */
+#define AT91C_PA9_CTS1            ( AT91C_PIO_PA9 )  /*  USART 1 Clear To Send */
+#define AT91C_PA9_NPCS03          ( AT91C_PIO_PA9 )  /*  SPI 0 Peripheral Chip Select 3 */
+#define AT91C_PIO_PB0             ( 1 << 0 )         /* Pin Controlled by PB0 */
+#define AT91C_PB0_ETXCK_EREFCK    ( AT91C_PIO_PB0 )  /*  Ethernet MAC Transmit Clock/Reference Clock */
+#define AT91C_PB0_PCK0            ( AT91C_PIO_PB0 )  /*  PMC Programmable Clock Output 0 */
+#define AT91C_PIO_PB1             ( 1 << 1 )         /* Pin Controlled by PB1 */
+#define AT91C_PB1_ETXEN           ( AT91C_PIO_PB1 )  /*  Ethernet MAC Transmit Enable */
+#define AT91C_PIO_PB10            ( 1 << 10 )        /* Pin Controlled by PB10 */
+#define AT91C_PB10_ETX2           ( AT91C_PIO_PB10 ) /*  Ethernet MAC Transmit Data 2 */
+#define AT91C_PB10_NPCS11         ( AT91C_PIO_PB10 ) /*  SPI 1 Peripheral Chip Select 1 */
+#define AT91C_PIO_PB11            ( 1 << 11 )        /* Pin Controlled by PB11 */
+#define AT91C_PB11_ETX3           ( AT91C_PIO_PB11 ) /*  Ethernet MAC Transmit Data 3 */
+#define AT91C_PB11_NPCS12         ( AT91C_PIO_PB11 ) /*  SPI 1 Peripheral Chip Select 2 */
+#define AT91C_PIO_PB12            ( 1 << 12 )        /* Pin Controlled by PB12 */
+#define AT91C_PB12_ETXER          ( AT91C_PIO_PB12 ) /*  Ethernet MAC Transmit Coding Error */
+#define AT91C_PB12_TCLK0          ( AT91C_PIO_PB12 ) /*  Timer Counter 0 external clock input */
+#define AT91C_PIO_PB13            ( 1 << 13 )        /* Pin Controlled by PB13 */
+#define AT91C_PB13_ERX2           ( AT91C_PIO_PB13 ) /*  Ethernet MAC Receive Data 2 */
+#define AT91C_PB13_NPCS01         ( AT91C_PIO_PB13 ) /*  SPI 0 Peripheral Chip Select 1 */
+#define AT91C_PIO_PB14            ( 1 << 14 )        /* Pin Controlled by PB14 */
+#define AT91C_PB14_ERX3           ( AT91C_PIO_PB14 ) /*  Ethernet MAC Receive Data 3 */
+#define AT91C_PB14_NPCS02         ( AT91C_PIO_PB14 ) /*  SPI 0 Peripheral Chip Select 2 */
+#define AT91C_PIO_PB15            ( 1 << 15 )        /* Pin Controlled by PB15 */
+#define AT91C_PB15_ERXDV          ( AT91C_PIO_PB15 ) /*  Ethernet MAC Receive Data Valid */
+#define AT91C_PIO_PB16            ( 1 << 16 )        /* Pin Controlled by PB16 */
+#define AT91C_PB16_ECOL           ( AT91C_PIO_PB16 ) /*  Ethernet MAC Collision Detected */
+#define AT91C_PB16_NPCS13         ( AT91C_PIO_PB16 ) /*  SPI 1 Peripheral Chip Select 3 */
+#define AT91C_PIO_PB17            ( 1 << 17 )        /* Pin Controlled by PB17 */
+#define AT91C_PB17_ERXCK          ( AT91C_PIO_PB17 ) /*  Ethernet MAC Receive Clock */
+#define AT91C_PB17_NPCS03         ( AT91C_PIO_PB17 ) /*  SPI 0 Peripheral Chip Select 3 */
+#define AT91C_PIO_PB18            ( 1 << 18 )        /* Pin Controlled by PB18 */
+#define AT91C_PB18_EF100          ( AT91C_PIO_PB18 ) /*  Ethernet MAC Force 100 Mbits/sec */
+#define AT91C_PB18_ADTRG          ( AT91C_PIO_PB18 ) /*  ADC External Trigger */
+#define AT91C_PIO_PB19            ( 1 << 19 )        /* Pin Controlled by PB19 */
+#define AT91C_PB19_PWM0           ( AT91C_PIO_PB19 ) /*  PWM Channel 0 */
+#define AT91C_PB19_TCLK1          ( AT91C_PIO_PB19 ) /*  Timer Counter 1 external clock input */
+#define AT91C_PIO_PB2             ( 1 << 2 )         /* Pin Controlled by PB2 */
+#define AT91C_PB2_ETX0            ( AT91C_PIO_PB2 )  /*  Ethernet MAC Transmit Data 0 */
+#define AT91C_PIO_PB20            ( 1 << 20 )        /* Pin Controlled by PB20 */
+#define AT91C_PB20_PWM1           ( AT91C_PIO_PB20 ) /*  PWM Channel 1 */
+#define AT91C_PB20_PCK0           ( AT91C_PIO_PB20 ) /*  PMC Programmable Clock Output 0 */
+#define AT91C_PIO_PB21            ( 1 << 21 )        /* Pin Controlled by PB21 */
+#define AT91C_PB21_PWM2           ( AT91C_PIO_PB21 ) /*  PWM Channel 2 */
+#define AT91C_PB21_PCK1           ( AT91C_PIO_PB21 ) /*  PMC Programmable Clock Output 1 */
+#define AT91C_PIO_PB22            ( 1 << 22 )        /* Pin Controlled by PB22 */
+#define AT91C_PB22_PWM3           ( AT91C_PIO_PB22 ) /*  PWM Channel 3 */
+#define AT91C_PB22_PCK2           ( AT91C_PIO_PB22 ) /*  PMC Programmable Clock Output 2 */
+#define AT91C_PIO_PB23            ( 1 << 23 )        /* Pin Controlled by PB23 */
+#define AT91C_PB23_TIOA0          ( AT91C_PIO_PB23 ) /*  Timer Counter 0 Multipurpose Timer I/O Pin A */
+#define AT91C_PB23_DCD1           ( AT91C_PIO_PB23 ) /*  USART 1 Data Carrier Detect */
+#define AT91C_PIO_PB24            ( 1 << 24 )        /* Pin Controlled by PB24 */
+#define AT91C_PB24_TIOB0          ( AT91C_PIO_PB24 ) /*  Timer Counter 0 Multipurpose Timer I/O Pin B */
+#define AT91C_PB24_DSR1           ( AT91C_PIO_PB24 ) /*  USART 1 Data Set ready */
+#define AT91C_PIO_PB25            ( 1 << 25 )        /* Pin Controlled by PB25 */
+#define AT91C_PB25_TIOA1          ( AT91C_PIO_PB25 ) /*  Timer Counter 1 Multipurpose Timer I/O Pin A */
+#define AT91C_PB25_DTR1           ( AT91C_PIO_PB25 ) /*  USART 1 Data Terminal ready */
+#define AT91C_PIO_PB26            ( 1 << 26 )        /* Pin Controlled by PB26 */
+#define AT91C_PB26_TIOB1          ( AT91C_PIO_PB26 ) /*  Timer Counter 1 Multipurpose Timer I/O Pin B */
+#define AT91C_PB26_RI1            ( AT91C_PIO_PB26 ) /*  USART 1 Ring Indicator */
+#define AT91C_PIO_PB27            ( 1 << 27 )        /* Pin Controlled by PB27 */
+#define AT91C_PB27_TIOA2          ( AT91C_PIO_PB27 ) /*  Timer Counter 2 Multipurpose Timer I/O Pin A */
+#define AT91C_PB27_PWM0           ( AT91C_PIO_PB27 ) /*  PWM Channel 0 */
+#define AT91C_PIO_PB28            ( 1 << 28 )        /* Pin Controlled by PB28 */
+#define AT91C_PB28_TIOB2          ( AT91C_PIO_PB28 ) /*  Timer Counter 2 Multipurpose Timer I/O Pin B */
+#define AT91C_PB28_PWM1           ( AT91C_PIO_PB28 ) /*  PWM Channel 1 */
+#define AT91C_PIO_PB29            ( 1 << 29 )        /* Pin Controlled by PB29 */
+#define AT91C_PB29_PCK1           ( AT91C_PIO_PB29 ) /*  PMC Programmable Clock Output 1 */
+#define AT91C_PB29_PWM2           ( AT91C_PIO_PB29 ) /*  PWM Channel 2 */
+#define AT91C_PIO_PB3             ( 1 << 3 )         /* Pin Controlled by PB3 */
+#define AT91C_PB3_ETX1            ( AT91C_PIO_PB3 )  /*  Ethernet MAC Transmit Data 1 */
+#define AT91C_PIO_PB30            ( 1 << 30 )        /* Pin Controlled by PB30 */
+#define AT91C_PB30_PCK2           ( AT91C_PIO_PB30 ) /*  PMC Programmable Clock Output 2 */
+#define AT91C_PB30_PWM3           ( AT91C_PIO_PB30 ) /*  PWM Channel 3 */
+#define AT91C_PIO_PB4             ( 1 << 4 )         /* Pin Controlled by PB4 */
+#define AT91C_PB4_ECRS_ECRSDV     ( AT91C_PIO_PB4 )  /*  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid */
+#define AT91C_PIO_PB5             ( 1 << 5 )         /* Pin Controlled by PB5 */
+#define AT91C_PB5_ERX0            ( AT91C_PIO_PB5 )  /*  Ethernet MAC Receive Data 0 */
+#define AT91C_PIO_PB6             ( 1 << 6 )         /* Pin Controlled by PB6 */
+#define AT91C_PB6_ERX1            ( AT91C_PIO_PB6 )  /*  Ethernet MAC Receive Data 1 */
+#define AT91C_PIO_PB7             ( 1 << 7 )         /* Pin Controlled by PB7 */
+#define AT91C_PB7_ERXER           ( AT91C_PIO_PB7 )  /*  Ethernet MAC Receive Error */
+#define AT91C_PIO_PB8             ( 1 << 8 )         /* Pin Controlled by PB8 */
+#define AT91C_PB8_EMDC            ( AT91C_PIO_PB8 )  /*  Ethernet MAC Management Data Clock */
+#define AT91C_PIO_PB9             ( 1 << 9 )         /* Pin Controlled by PB9 */
+#define AT91C_PB9_EMDIO           ( AT91C_PIO_PB9 )  /*  Ethernet MAC Management Data Input/Output */
 
-// *****************************************************************************
-//               PERIPHERAL ID DEFINITIONS FOR AT91SAM7X128
-// *****************************************************************************
-#define AT91C_ID_FIQ              ( 0) // Advanced Interrupt Controller (FIQ)
-#define AT91C_ID_SYS              ( 1) // System Peripheral
-#define AT91C_ID_PIOA             ( 2) // Parallel IO Controller A
-#define AT91C_ID_PIOB             ( 3) // Parallel IO Controller B
-#define AT91C_ID_SPI0             ( 4) // Serial Peripheral Interface 0
-#define AT91C_ID_SPI1             ( 5) // Serial Peripheral Interface 1
-#define AT91C_ID_US0              ( 6) // USART 0
-#define AT91C_ID_US1              ( 7) // USART 1
-#define AT91C_ID_SSC              ( 8) // Serial Synchronous Controller
-#define AT91C_ID_TWI              ( 9) // Two-Wire Interface
-#define AT91C_ID_PWMC             (10) // PWM Controller
-#define AT91C_ID_UDP              (11) // USB Device Port
-#define AT91C_ID_TC0              (12) // Timer Counter 0
-#define AT91C_ID_TC1              (13) // Timer Counter 1
-#define AT91C_ID_TC2              (14) // Timer Counter 2
-#define AT91C_ID_CAN              (15) // Control Area Network Controller
-#define AT91C_ID_EMAC             (16) // Ethernet MAC
-#define AT91C_ID_ADC              (17) // Analog-to-Digital Converter
-#define AT91C_ID_AES              (18) // Advanced Encryption Standard 128-bit
-#define AT91C_ID_TDES             (19) // Triple Data Encryption Standard
-#define AT91C_ID_20_Reserved      (20) // Reserved
-#define AT91C_ID_21_Reserved      (21) // Reserved
-#define AT91C_ID_22_Reserved      (22) // Reserved
-#define AT91C_ID_23_Reserved      (23) // Reserved
-#define AT91C_ID_24_Reserved      (24) // Reserved
-#define AT91C_ID_25_Reserved      (25) // Reserved
-#define AT91C_ID_26_Reserved      (26) // Reserved
-#define AT91C_ID_27_Reserved      (27) // Reserved
-#define AT91C_ID_28_Reserved      (28) // Reserved
-#define AT91C_ID_29_Reserved      (29) // Reserved
-#define AT91C_ID_IRQ0             (30) // Advanced Interrupt Controller (IRQ0)
-#define AT91C_ID_IRQ1             (31) // Advanced Interrupt Controller (IRQ1)
+/* ***************************************************************************** */
+/*               PERIPHERAL ID DEFINITIONS FOR AT91SAM7X128 */
+/* ***************************************************************************** */
+#define AT91C_ID_FIQ            ( 0 )  /* Advanced Interrupt Controller (FIQ) */
+#define AT91C_ID_SYS            ( 1 )  /* System Peripheral */
+#define AT91C_ID_PIOA           ( 2 )  /* Parallel IO Controller A */
+#define AT91C_ID_PIOB           ( 3 )  /* Parallel IO Controller B */
+#define AT91C_ID_SPI0           ( 4 )  /* Serial Peripheral Interface 0 */
+#define AT91C_ID_SPI1           ( 5 )  /* Serial Peripheral Interface 1 */
+#define AT91C_ID_US0            ( 6 )  /* USART 0 */
+#define AT91C_ID_US1            ( 7 )  /* USART 1 */
+#define AT91C_ID_SSC            ( 8 )  /* Serial Synchronous Controller */
+#define AT91C_ID_TWI            ( 9 )  /* Two-Wire Interface */
+#define AT91C_ID_PWMC           ( 10 ) /* PWM Controller */
+#define AT91C_ID_UDP            ( 11 ) /* USB Device Port */
+#define AT91C_ID_TC0            ( 12 ) /* Timer Counter 0 */
+#define AT91C_ID_TC1            ( 13 ) /* Timer Counter 1 */
+#define AT91C_ID_TC2            ( 14 ) /* Timer Counter 2 */
+#define AT91C_ID_CAN            ( 15 ) /* Control Area Network Controller */
+#define AT91C_ID_EMAC           ( 16 ) /* Ethernet MAC */
+#define AT91C_ID_ADC            ( 17 ) /* Analog-to-Digital Converter */
+#define AT91C_ID_AES            ( 18 ) /* Advanced Encryption Standard 128-bit */
+#define AT91C_ID_TDES           ( 19 ) /* Triple Data Encryption Standard */
+#define AT91C_ID_20_Reserved    ( 20 ) /* Reserved */
+#define AT91C_ID_21_Reserved    ( 21 ) /* Reserved */
+#define AT91C_ID_22_Reserved    ( 22 ) /* Reserved */
+#define AT91C_ID_23_Reserved    ( 23 ) /* Reserved */
+#define AT91C_ID_24_Reserved    ( 24 ) /* Reserved */
+#define AT91C_ID_25_Reserved    ( 25 ) /* Reserved */
+#define AT91C_ID_26_Reserved    ( 26 ) /* Reserved */
+#define AT91C_ID_27_Reserved    ( 27 ) /* Reserved */
+#define AT91C_ID_28_Reserved    ( 28 ) /* Reserved */
+#define AT91C_ID_29_Reserved    ( 29 ) /* Reserved */
+#define AT91C_ID_IRQ0           ( 30 ) /* Advanced Interrupt Controller (IRQ0) */
+#define AT91C_ID_IRQ1           ( 31 ) /* Advanced Interrupt Controller (IRQ1) */
 
-// *****************************************************************************
-//               BASE ADDRESS DEFINITIONS FOR AT91SAM7X128
-// *****************************************************************************
-#define AT91C_BASE_SYS            (0xFFFFF000) // (SYS) Base Address
-#define AT91C_BASE_AIC            (0xFFFFF000) // (AIC) Base Address
-#define AT91C_BASE_PDC_DBGU       (0xFFFFF300) // (PDC_DBGU) Base Address
-#define AT91C_BASE_DBGU           (0xFFFFF200) // (DBGU) Base Address
-#define AT91C_BASE_PIOA           (0xFFFFF400) // (PIOA) Base Address
-#define AT91C_BASE_PIOB           (0xFFFFF600) // (PIOB) Base Address
-#define AT91C_BASE_CKGR           (0xFFFFFC20) // (CKGR) Base Address
-#define AT91C_BASE_PMC            (0xFFFFFC00) // (PMC) Base Address
-#define AT91C_BASE_RSTC           (0xFFFFFD00) // (RSTC) Base Address
-#define AT91C_BASE_RTTC           (0xFFFFFD20) // (RTTC) Base Address
-#define AT91C_BASE_PITC           (0xFFFFFD30) // (PITC) Base Address
-#define AT91C_BASE_WDTC           (0xFFFFFD40) // (WDTC) Base Address
-#define AT91C_BASE_VREG           (0xFFFFFD60) // (VREG) Base Address
-#define AT91C_BASE_MC             (0xFFFFFF00) // (MC) Base Address
-#define AT91C_BASE_PDC_SPI1       (0xFFFE4100) // (PDC_SPI1) Base Address
-#define AT91C_BASE_SPI1           (0xFFFE4000) // (SPI1) Base Address
-#define AT91C_BASE_PDC_SPI0       (0xFFFE0100) // (PDC_SPI0) Base Address
-#define AT91C_BASE_SPI0           (0xFFFE0000) // (SPI0) Base Address
-#define AT91C_BASE_PDC_US1        (0xFFFC4100) // (PDC_US1) Base Address
-#define AT91C_BASE_US1            (0xFFFC4000) // (US1) Base Address
-#define AT91C_BASE_PDC_US0        (0xFFFC0100) // (PDC_US0) Base Address
-#define AT91C_BASE_US0            (0xFFFC0000) // (US0) Base Address
-#define AT91C_BASE_PDC_SSC        (0xFFFD4100) // (PDC_SSC) Base Address
-#define AT91C_BASE_SSC            (0xFFFD4000) // (SSC) Base Address
-#define AT91C_BASE_TWI            (0xFFFB8000) // (TWI) Base Address
-#define AT91C_BASE_PWMC_CH3       (0xFFFCC260) // (PWMC_CH3) Base Address
-#define AT91C_BASE_PWMC_CH2       (0xFFFCC240) // (PWMC_CH2) Base Address
-#define AT91C_BASE_PWMC_CH1       (0xFFFCC220) // (PWMC_CH1) Base Address
-#define AT91C_BASE_PWMC_CH0       (0xFFFCC200) // (PWMC_CH0) Base Address
-#define AT91C_BASE_PWMC           (0xFFFCC000) // (PWMC) Base Address
-#define AT91C_BASE_UDP            (0xFFFB0000) // (UDP) Base Address
-#define AT91C_BASE_TC0            (0xFFFA0000) // (TC0) Base Address
-#define AT91C_BASE_TC1            (0xFFFA0040) // (TC1) Base Address
-#define AT91C_BASE_TC2            (0xFFFA0080) // (TC2) Base Address
-#define AT91C_BASE_TCB            (0xFFFA0000) // (TCB) Base Address
-#define AT91C_BASE_CAN_MB0        (0xFFFD0200) // (CAN_MB0) Base Address
-#define AT91C_BASE_CAN_MB1        (0xFFFD0220) // (CAN_MB1) Base Address
-#define AT91C_BASE_CAN_MB2        (0xFFFD0240) // (CAN_MB2) Base Address
-#define AT91C_BASE_CAN_MB3        (0xFFFD0260) // (CAN_MB3) Base Address
-#define AT91C_BASE_CAN_MB4        (0xFFFD0280) // (CAN_MB4) Base Address
-#define AT91C_BASE_CAN_MB5        (0xFFFD02A0) // (CAN_MB5) Base Address
-#define AT91C_BASE_CAN_MB6        (0xFFFD02C0) // (CAN_MB6) Base Address
-#define AT91C_BASE_CAN_MB7        (0xFFFD02E0) // (CAN_MB7) Base Address
-#define AT91C_BASE_CAN            (0xFFFD0000) // (CAN) Base Address
-#define AT91C_BASE_EMAC           (0xFFFDC000) // (EMAC) Base Address
-#define AT91C_BASE_PDC_ADC        (0xFFFD8100) // (PDC_ADC) Base Address
-#define AT91C_BASE_ADC            (0xFFFD8000) // (ADC) Base Address
-#define AT91C_BASE_PDC_AES        (0xFFFA4100) // (PDC_AES) Base Address
-#define AT91C_BASE_AES            (0xFFFA4000) // (AES) Base Address
-#define AT91C_BASE_PDC_TDES       (0xFFFA8100) // (PDC_TDES) Base Address
-#define AT91C_BASE_TDES           (0xFFFA8000) // (TDES) Base Address
+/* ***************************************************************************** */
+/*               BASE ADDRESS DEFINITIONS FOR AT91SAM7X128 */
+/* ***************************************************************************** */
+#define AT91C_BASE_SYS         ( 0xFFFFF000 )  /* (SYS) Base Address */
+#define AT91C_BASE_AIC         ( 0xFFFFF000 )  /* (AIC) Base Address */
+#define AT91C_BASE_PDC_DBGU    ( 0xFFFFF300 )  /* (PDC_DBGU) Base Address */
+#define AT91C_BASE_DBGU        ( 0xFFFFF200 )  /* (DBGU) Base Address */
+#define AT91C_BASE_PIOA        ( 0xFFFFF400 )  /* (PIOA) Base Address */
+#define AT91C_BASE_PIOB        ( 0xFFFFF600 )  /* (PIOB) Base Address */
+#define AT91C_BASE_CKGR        ( 0xFFFFFC20 )  /* (CKGR) Base Address */
+#define AT91C_BASE_PMC         ( 0xFFFFFC00 )  /* (PMC) Base Address */
+#define AT91C_BASE_RSTC        ( 0xFFFFFD00 )  /* (RSTC) Base Address */
+#define AT91C_BASE_RTTC        ( 0xFFFFFD20 )  /* (RTTC) Base Address */
+#define AT91C_BASE_PITC        ( 0xFFFFFD30 )  /* (PITC) Base Address */
+#define AT91C_BASE_WDTC        ( 0xFFFFFD40 )  /* (WDTC) Base Address */
+#define AT91C_BASE_VREG        ( 0xFFFFFD60 )  /* (VREG) Base Address */
+#define AT91C_BASE_MC          ( 0xFFFFFF00 )  /* (MC) Base Address */
+#define AT91C_BASE_PDC_SPI1    ( 0xFFFE4100 )  /* (PDC_SPI1) Base Address */
+#define AT91C_BASE_SPI1        ( 0xFFFE4000 )  /* (SPI1) Base Address */
+#define AT91C_BASE_PDC_SPI0    ( 0xFFFE0100 )  /* (PDC_SPI0) Base Address */
+#define AT91C_BASE_SPI0        ( 0xFFFE0000 )  /* (SPI0) Base Address */
+#define AT91C_BASE_PDC_US1     ( 0xFFFC4100 )  /* (PDC_US1) Base Address */
+#define AT91C_BASE_US1         ( 0xFFFC4000 )  /* (US1) Base Address */
+#define AT91C_BASE_PDC_US0     ( 0xFFFC0100 )  /* (PDC_US0) Base Address */
+#define AT91C_BASE_US0         ( 0xFFFC0000 )  /* (US0) Base Address */
+#define AT91C_BASE_PDC_SSC     ( 0xFFFD4100 )  /* (PDC_SSC) Base Address */
+#define AT91C_BASE_SSC         ( 0xFFFD4000 )  /* (SSC) Base Address */
+#define AT91C_BASE_TWI         ( 0xFFFB8000 )  /* (TWI) Base Address */
+#define AT91C_BASE_PWMC_CH3    ( 0xFFFCC260 )  /* (PWMC_CH3) Base Address */
+#define AT91C_BASE_PWMC_CH2    ( 0xFFFCC240 )  /* (PWMC_CH2) Base Address */
+#define AT91C_BASE_PWMC_CH1    ( 0xFFFCC220 )  /* (PWMC_CH1) Base Address */
+#define AT91C_BASE_PWMC_CH0    ( 0xFFFCC200 )  /* (PWMC_CH0) Base Address */
+#define AT91C_BASE_PWMC        ( 0xFFFCC000 )  /* (PWMC) Base Address */
+#define AT91C_BASE_UDP         ( 0xFFFB0000 )  /* (UDP) Base Address */
+#define AT91C_BASE_TC0         ( 0xFFFA0000 )  /* (TC0) Base Address */
+#define AT91C_BASE_TC1         ( 0xFFFA0040 )  /* (TC1) Base Address */
+#define AT91C_BASE_TC2         ( 0xFFFA0080 )  /* (TC2) Base Address */
+#define AT91C_BASE_TCB         ( 0xFFFA0000 )  /* (TCB) Base Address */
+#define AT91C_BASE_CAN_MB0     ( 0xFFFD0200 )  /* (CAN_MB0) Base Address */
+#define AT91C_BASE_CAN_MB1     ( 0xFFFD0220 )  /* (CAN_MB1) Base Address */
+#define AT91C_BASE_CAN_MB2     ( 0xFFFD0240 )  /* (CAN_MB2) Base Address */
+#define AT91C_BASE_CAN_MB3     ( 0xFFFD0260 )  /* (CAN_MB3) Base Address */
+#define AT91C_BASE_CAN_MB4     ( 0xFFFD0280 )  /* (CAN_MB4) Base Address */
+#define AT91C_BASE_CAN_MB5     ( 0xFFFD02A0 )  /* (CAN_MB5) Base Address */
+#define AT91C_BASE_CAN_MB6     ( 0xFFFD02C0 )  /* (CAN_MB6) Base Address */
+#define AT91C_BASE_CAN_MB7     ( 0xFFFD02E0 )  /* (CAN_MB7) Base Address */
+#define AT91C_BASE_CAN         ( 0xFFFD0000 )  /* (CAN) Base Address */
+#define AT91C_BASE_EMAC        ( 0xFFFDC000 )  /* (EMAC) Base Address */
+#define AT91C_BASE_PDC_ADC     ( 0xFFFD8100 )  /* (PDC_ADC) Base Address */
+#define AT91C_BASE_ADC         ( 0xFFFD8000 )  /* (ADC) Base Address */
+#define AT91C_BASE_PDC_AES     ( 0xFFFA4100 )  /* (PDC_AES) Base Address */
+#define AT91C_BASE_AES         ( 0xFFFA4000 )  /* (AES) Base Address */
+#define AT91C_BASE_PDC_TDES    ( 0xFFFA8100 )  /* (PDC_TDES) Base Address */
+#define AT91C_BASE_TDES        ( 0xFFFA8000 )  /* (TDES) Base Address */
 
-// *****************************************************************************
-//               MEMORY MAPPING DEFINITIONS FOR AT91SAM7X128
-// *****************************************************************************
-#define AT91C_ISRAM               (0x00200000) // Internal SRAM base address
-#define AT91C_ISRAM_SIZE             (0x00008000) // Internal SRAM size in byte (32 Kbyte)
-#define AT91C_IFLASH                 (0x00100000) // Internal ROM base address
-#define AT91C_IFLASH_SIZE           (0x00020000) // Internal ROM size in byte (128 Kbyte)
+/* ***************************************************************************** */
+/*               MEMORY MAPPING DEFINITIONS FOR AT91SAM7X128 */
+/* ***************************************************************************** */
+#define AT91C_ISRAM          ( 0x00200000 )    /* Internal SRAM base address */
+#define AT91C_ISRAM_SIZE     ( 0x00008000 )    /* Internal SRAM size in byte (32 Kbyte) */
+#define AT91C_IFLASH         ( 0x00100000 )    /* Internal ROM base address */
+#define AT91C_IFLASH_SIZE    ( 0x00020000 )    /* Internal ROM size in byte (128 Kbyte) */
diff --git a/portable/IAR/AtmelSAM7S64/AT91SAM7X256.h b/portable/IAR/AtmelSAM7S64/AT91SAM7X256.h
index cf952e3c2..98e1babc2 100644
--- a/portable/IAR/AtmelSAM7S64/AT91SAM7X256.h
+++ b/portable/IAR/AtmelSAM7S64/AT91SAM7X256.h
@@ -1,2715 +1,2743 @@
-//  ----------------------------------------------------------------------------
-//          ATMEL Microcontroller Software Support  -  ROUSSET  -
-//  ----------------------------------------------------------------------------
-//  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
-//  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
-//  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
-//  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
-//  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-//  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-//  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-//  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//  ----------------------------------------------------------------------------
-// File Name           : AT91SAM7X256.h
-// Object              : AT91SAM7X256 definitions
-// Generated           : AT91 SW Application Group  05/20/2005 (16:22:29)
-//
-// CVS Reference       : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005//
-// CVS Reference       : /SYS_SAM7X.pl/1.3/Tue Feb  1 17:01:43 2005//
-// CVS Reference       : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005//
-// CVS Reference       : /PMC_SAM7X.pl/1.4/Tue Feb  8 13:58:10 2005//
-// CVS Reference       : /RSTC_SAM7X.pl/1.1/Tue Feb  1 16:16:26 2005//
-// CVS Reference       : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005//
-// CVS Reference       : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005//
-// CVS Reference       : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//
-// CVS Reference       : /PIO_6057A.pl/1.2/Thu Feb  3 10:18:28 2005//
-// CVS Reference       : /RTTC_6081A.pl/1.2/Tue Nov  9 14:43:58 2004//
-// CVS Reference       : /PITC_6079A.pl/1.2/Tue Nov  9 14:43:56 2004//
-// CVS Reference       : /WDTC_6080A.pl/1.3/Tue Nov  9 14:44:00 2004//
-// CVS Reference       : /VREG_6085B.pl/1.1/Tue Feb  1 16:05:48 2005//
-// CVS Reference       : /PDC_6074C.pl/1.2/Thu Feb  3 08:48:54 2005//
-// CVS Reference       : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//
-// CVS Reference       : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//
-// CVS Reference       : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//
-// CVS Reference       : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//
-// CVS Reference       : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//
-// CVS Reference       : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//
-// CVS Reference       : /CAN_6019B.pl/1.1/Tue Mar  8 12:42:22 2005//
-// CVS Reference       : /EMACB_6119A.pl/1.5/Thu Feb  3 15:52:04 2005//
-// CVS Reference       : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//
-// CVS Reference       : /AES_6149A.pl/1.10/Mon Feb  7 09:44:25 2005//
-// CVS Reference       : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005//
-//  ----------------------------------------------------------------------------
+/*  ---------------------------------------------------------------------------- */
+/*          ATMEL Microcontroller Software Support  -  ROUSSET  - */
+/*  ---------------------------------------------------------------------------- */
+/*  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
+/*  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
+/*  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
+/*  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
+/*  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
+/*  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
+/*  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/*  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
+/*  ---------------------------------------------------------------------------- */
+/* File Name           : AT91SAM7X256.h */
+/* Object              : AT91SAM7X256 definitions */
+/* Generated           : AT91 SW Application Group  05/20/2005 (16:22:29) */
+/* */
+/* CVS Reference       : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005// */
+/* CVS Reference       : /SYS_SAM7X.pl/1.3/Tue Feb  1 17:01:43 2005// */
+/* CVS Reference       : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// */
+/* CVS Reference       : /PMC_SAM7X.pl/1.4/Tue Feb  8 13:58:10 2005// */
+/* CVS Reference       : /RSTC_SAM7X.pl/1.1/Tue Feb  1 16:16:26 2005// */
+/* CVS Reference       : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// */
+/* CVS Reference       : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// */
+/* CVS Reference       : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// */
+/* CVS Reference       : /PIO_6057A.pl/1.2/Thu Feb  3 10:18:28 2005// */
+/* CVS Reference       : /RTTC_6081A.pl/1.2/Tue Nov  9 14:43:58 2004// */
+/* CVS Reference       : /PITC_6079A.pl/1.2/Tue Nov  9 14:43:56 2004// */
+/* CVS Reference       : /WDTC_6080A.pl/1.3/Tue Nov  9 14:44:00 2004// */
+/* CVS Reference       : /VREG_6085B.pl/1.1/Tue Feb  1 16:05:48 2005// */
+/* CVS Reference       : /PDC_6074C.pl/1.2/Thu Feb  3 08:48:54 2005// */
+/* CVS Reference       : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// */
+/* CVS Reference       : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// */
+/* CVS Reference       : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// */
+/* CVS Reference       : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// */
+/* CVS Reference       : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// */
+/* CVS Reference       : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// */
+/* CVS Reference       : /CAN_6019B.pl/1.1/Tue Mar  8 12:42:22 2005// */
+/* CVS Reference       : /EMACB_6119A.pl/1.5/Thu Feb  3 15:52:04 2005// */
+/* CVS Reference       : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// */
+/* CVS Reference       : /AES_6149A.pl/1.10/Mon Feb  7 09:44:25 2005// */
+/* CVS Reference       : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// */
+/*  ---------------------------------------------------------------------------- */
 
 #ifndef AT91SAM7X256_H
 #define AT91SAM7X256_H
 
-typedef volatile unsigned int AT91_REG;// Hardware register definition
+typedef volatile unsigned int AT91_REG; /* Hardware register definition */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR System Peripherals
-// *****************************************************************************
-typedef struct _AT91S_SYS {
-    AT91_REG     AIC_SMR[32];   // Source Mode Register
-    AT91_REG     AIC_SVR[32];   // Source Vector Register
-    AT91_REG     AIC_IVR;   // IRQ Vector Register
-    AT91_REG     AIC_FVR;   // FIQ Vector Register
-    AT91_REG     AIC_ISR;   // Interrupt Status Register
-    AT91_REG     AIC_IPR;   // Interrupt Pending Register
-    AT91_REG     AIC_IMR;   // Interrupt Mask Register
-    AT91_REG     AIC_CISR;  // Core Interrupt Status Register
-    AT91_REG     Reserved0[2];  //
-    AT91_REG     AIC_IECR;  // Interrupt Enable Command Register
-    AT91_REG     AIC_IDCR;  // Interrupt Disable Command Register
-    AT91_REG     AIC_ICCR;  // Interrupt Clear Command Register
-    AT91_REG     AIC_ISCR;  // Interrupt Set Command Register
-    AT91_REG     AIC_EOICR;     // End of Interrupt Command Register
-    AT91_REG     AIC_SPU;   // Spurious Vector Register
-    AT91_REG     AIC_DCR;   // Debug Control Register (Protect)
-    AT91_REG     Reserved1[1];  //
-    AT91_REG     AIC_FFER;  // Fast Forcing Enable Register
-    AT91_REG     AIC_FFDR;  // Fast Forcing Disable Register
-    AT91_REG     AIC_FFSR;  // Fast Forcing Status Register
-    AT91_REG     Reserved2[45];     //
-    AT91_REG     DBGU_CR;   // Control Register
-    AT91_REG     DBGU_MR;   // Mode Register
-    AT91_REG     DBGU_IER;  // Interrupt Enable Register
-    AT91_REG     DBGU_IDR;  // Interrupt Disable Register
-    AT91_REG     DBGU_IMR;  // Interrupt Mask Register
-    AT91_REG     DBGU_CSR;  // Channel Status Register
-    AT91_REG     DBGU_RHR;  // Receiver Holding Register
-    AT91_REG     DBGU_THR;  // Transmitter Holding Register
-    AT91_REG     DBGU_BRGR;     // Baud Rate Generator Register
-    AT91_REG     Reserved3[7];  //
-    AT91_REG     DBGU_CIDR;     // Chip ID Register
-    AT91_REG     DBGU_EXID;     // Chip ID Extension Register
-    AT91_REG     DBGU_FNTR;     // Force NTRST Register
-    AT91_REG     Reserved4[45];     //
-    AT91_REG     DBGU_RPR;  // Receive Pointer Register
-    AT91_REG     DBGU_RCR;  // Receive Counter Register
-    AT91_REG     DBGU_TPR;  // Transmit Pointer Register
-    AT91_REG     DBGU_TCR;  // Transmit Counter Register
-    AT91_REG     DBGU_RNPR;     // Receive Next Pointer Register
-    AT91_REG     DBGU_RNCR;     // Receive Next Counter Register
-    AT91_REG     DBGU_TNPR;     // Transmit Next Pointer Register
-    AT91_REG     DBGU_TNCR;     // Transmit Next Counter Register
-    AT91_REG     DBGU_PTCR;     // PDC Transfer Control Register
-    AT91_REG     DBGU_PTSR;     // PDC Transfer Status Register
-    AT91_REG     Reserved5[54];     //
-    AT91_REG     PIOA_PER;  // PIO Enable Register
-    AT91_REG     PIOA_PDR;  // PIO Disable Register
-    AT91_REG     PIOA_PSR;  // PIO Status Register
-    AT91_REG     Reserved6[1];  //
-    AT91_REG     PIOA_OER;  // Output Enable Register
-    AT91_REG     PIOA_ODR;  // Output Disable Registerr
-    AT91_REG     PIOA_OSR;  // Output Status Register
-    AT91_REG     Reserved7[1];  //
-    AT91_REG     PIOA_IFER;     // Input Filter Enable Register
-    AT91_REG     PIOA_IFDR;     // Input Filter Disable Register
-    AT91_REG     PIOA_IFSR;     // Input Filter Status Register
-    AT91_REG     Reserved8[1];  //
-    AT91_REG     PIOA_SODR;     // Set Output Data Register
-    AT91_REG     PIOA_CODR;     // Clear Output Data Register
-    AT91_REG     PIOA_ODSR;     // Output Data Status Register
-    AT91_REG     PIOA_PDSR;     // Pin Data Status Register
-    AT91_REG     PIOA_IER;  // Interrupt Enable Register
-    AT91_REG     PIOA_IDR;  // Interrupt Disable Register
-    AT91_REG     PIOA_IMR;  // Interrupt Mask Register
-    AT91_REG     PIOA_ISR;  // Interrupt Status Register
-    AT91_REG     PIOA_MDER;     // Multi-driver Enable Register
-    AT91_REG     PIOA_MDDR;     // Multi-driver Disable Register
-    AT91_REG     PIOA_MDSR;     // Multi-driver Status Register
-    AT91_REG     Reserved9[1];  //
-    AT91_REG     PIOA_PPUDR;    // Pull-up Disable Register
-    AT91_REG     PIOA_PPUER;    // Pull-up Enable Register
-    AT91_REG     PIOA_PPUSR;    // Pull-up Status Register
-    AT91_REG     Reserved10[1];     //
-    AT91_REG     PIOA_ASR;  // Select A Register
-    AT91_REG     PIOA_BSR;  // Select B Register
-    AT91_REG     PIOA_ABSR;     // AB Select Status Register
-    AT91_REG     Reserved11[9];     //
-    AT91_REG     PIOA_OWER;     // Output Write Enable Register
-    AT91_REG     PIOA_OWDR;     // Output Write Disable Register
-    AT91_REG     PIOA_OWSR;     // Output Write Status Register
-    AT91_REG     Reserved12[85];    //
-    AT91_REG     PIOB_PER;  // PIO Enable Register
-    AT91_REG     PIOB_PDR;  // PIO Disable Register
-    AT91_REG     PIOB_PSR;  // PIO Status Register
-    AT91_REG     Reserved13[1];     //
-    AT91_REG     PIOB_OER;  // Output Enable Register
-    AT91_REG     PIOB_ODR;  // Output Disable Registerr
-    AT91_REG     PIOB_OSR;  // Output Status Register
-    AT91_REG     Reserved14[1];     //
-    AT91_REG     PIOB_IFER;     // Input Filter Enable Register
-    AT91_REG     PIOB_IFDR;     // Input Filter Disable Register
-    AT91_REG     PIOB_IFSR;     // Input Filter Status Register
-    AT91_REG     Reserved15[1];     //
-    AT91_REG     PIOB_SODR;     // Set Output Data Register
-    AT91_REG     PIOB_CODR;     // Clear Output Data Register
-    AT91_REG     PIOB_ODSR;     // Output Data Status Register
-    AT91_REG     PIOB_PDSR;     // Pin Data Status Register
-    AT91_REG     PIOB_IER;  // Interrupt Enable Register
-    AT91_REG     PIOB_IDR;  // Interrupt Disable Register
-    AT91_REG     PIOB_IMR;  // Interrupt Mask Register
-    AT91_REG     PIOB_ISR;  // Interrupt Status Register
-    AT91_REG     PIOB_MDER;     // Multi-driver Enable Register
-    AT91_REG     PIOB_MDDR;     // Multi-driver Disable Register
-    AT91_REG     PIOB_MDSR;     // Multi-driver Status Register
-    AT91_REG     Reserved16[1];     //
-    AT91_REG     PIOB_PPUDR;    // Pull-up Disable Register
-    AT91_REG     PIOB_PPUER;    // Pull-up Enable Register
-    AT91_REG     PIOB_PPUSR;    // Pull-up Status Register
-    AT91_REG     Reserved17[1];     //
-    AT91_REG     PIOB_ASR;  // Select A Register
-    AT91_REG     PIOB_BSR;  // Select B Register
-    AT91_REG     PIOB_ABSR;     // AB Select Status Register
-    AT91_REG     Reserved18[9];     //
-    AT91_REG     PIOB_OWER;     // Output Write Enable Register
-    AT91_REG     PIOB_OWDR;     // Output Write Disable Register
-    AT91_REG     PIOB_OWSR;     // Output Write Status Register
-    AT91_REG     Reserved19[341];   //
-    AT91_REG     PMC_SCER;  // System Clock Enable Register
-    AT91_REG     PMC_SCDR;  // System Clock Disable Register
-    AT91_REG     PMC_SCSR;  // System Clock Status Register
-    AT91_REG     Reserved20[1];     //
-    AT91_REG     PMC_PCER;  // Peripheral Clock Enable Register
-    AT91_REG     PMC_PCDR;  // Peripheral Clock Disable Register
-    AT91_REG     PMC_PCSR;  // Peripheral Clock Status Register
-    AT91_REG     Reserved21[1];     //
-    AT91_REG     PMC_MOR;   // Main Oscillator Register
-    AT91_REG     PMC_MCFR;  // Main Clock  Frequency Register
-    AT91_REG     Reserved22[1];     //
-    AT91_REG     PMC_PLLR;  // PLL Register
-    AT91_REG     PMC_MCKR;  // Master Clock Register
-    AT91_REG     Reserved23[3];     //
-    AT91_REG     PMC_PCKR[4];   // Programmable Clock Register
-    AT91_REG     Reserved24[4];     //
-    AT91_REG     PMC_IER;   // Interrupt Enable Register
-    AT91_REG     PMC_IDR;   // Interrupt Disable Register
-    AT91_REG     PMC_SR;    // Status Register
-    AT91_REG     PMC_IMR;   // Interrupt Mask Register
-    AT91_REG     Reserved25[36];    //
-    AT91_REG     RSTC_RCR;  // Reset Control Register
-    AT91_REG     RSTC_RSR;  // Reset Status Register
-    AT91_REG     RSTC_RMR;  // Reset Mode Register
-    AT91_REG     Reserved26[5];     //
-    AT91_REG     RTTC_RTMR;     // Real-time Mode Register
-    AT91_REG     RTTC_RTAR;     // Real-time Alarm Register
-    AT91_REG     RTTC_RTVR;     // Real-time Value Register
-    AT91_REG     RTTC_RTSR;     // Real-time Status Register
-    AT91_REG     PITC_PIMR;     // Period Interval Mode Register
-    AT91_REG     PITC_PISR;     // Period Interval Status Register
-    AT91_REG     PITC_PIVR;     // Period Interval Value Register
-    AT91_REG     PITC_PIIR;     // Period Interval Image Register
-    AT91_REG     WDTC_WDCR;     // Watchdog Control Register
-    AT91_REG     WDTC_WDMR;     // Watchdog Mode Register
-    AT91_REG     WDTC_WDSR;     // Watchdog Status Register
-    AT91_REG     Reserved27[5];     //
-    AT91_REG     VREG_MR;   // Voltage Regulator Mode Register
-} AT91S_SYS, *AT91PS_SYS;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR System Peripherals */
+/* ***************************************************************************** */
+typedef struct _AT91S_SYS
+{
+    AT91_REG AIC_SMR[ 32 ];     /* Source Mode Register */
+    AT91_REG AIC_SVR[ 32 ];     /* Source Vector Register */
+    AT91_REG AIC_IVR;           /* IRQ Vector Register */
+    AT91_REG AIC_FVR;           /* FIQ Vector Register */
+    AT91_REG AIC_ISR;           /* Interrupt Status Register */
+    AT91_REG AIC_IPR;           /* Interrupt Pending Register */
+    AT91_REG AIC_IMR;           /* Interrupt Mask Register */
+    AT91_REG AIC_CISR;          /* Core Interrupt Status Register */
+    AT91_REG Reserved0[ 2 ];    /* */
+    AT91_REG AIC_IECR;          /* Interrupt Enable Command Register */
+    AT91_REG AIC_IDCR;          /* Interrupt Disable Command Register */
+    AT91_REG AIC_ICCR;          /* Interrupt Clear Command Register */
+    AT91_REG AIC_ISCR;          /* Interrupt Set Command Register */
+    AT91_REG AIC_EOICR;         /* End of Interrupt Command Register */
+    AT91_REG AIC_SPU;           /* Spurious Vector Register */
+    AT91_REG AIC_DCR;           /* Debug Control Register (Protect) */
+    AT91_REG Reserved1[ 1 ];    /* */
+    AT91_REG AIC_FFER;          /* Fast Forcing Enable Register */
+    AT91_REG AIC_FFDR;          /* Fast Forcing Disable Register */
+    AT91_REG AIC_FFSR;          /* Fast Forcing Status Register */
+    AT91_REG Reserved2[ 45 ];   /* */
+    AT91_REG DBGU_CR;           /* Control Register */
+    AT91_REG DBGU_MR;           /* Mode Register */
+    AT91_REG DBGU_IER;          /* Interrupt Enable Register */
+    AT91_REG DBGU_IDR;          /* Interrupt Disable Register */
+    AT91_REG DBGU_IMR;          /* Interrupt Mask Register */
+    AT91_REG DBGU_CSR;          /* Channel Status Register */
+    AT91_REG DBGU_RHR;          /* Receiver Holding Register */
+    AT91_REG DBGU_THR;          /* Transmitter Holding Register */
+    AT91_REG DBGU_BRGR;         /* Baud Rate Generator Register */
+    AT91_REG Reserved3[ 7 ];    /* */
+    AT91_REG DBGU_CIDR;         /* Chip ID Register */
+    AT91_REG DBGU_EXID;         /* Chip ID Extension Register */
+    AT91_REG DBGU_FNTR;         /* Force NTRST Register */
+    AT91_REG Reserved4[ 45 ];   /* */
+    AT91_REG DBGU_RPR;          /* Receive Pointer Register */
+    AT91_REG DBGU_RCR;          /* Receive Counter Register */
+    AT91_REG DBGU_TPR;          /* Transmit Pointer Register */
+    AT91_REG DBGU_TCR;          /* Transmit Counter Register */
+    AT91_REG DBGU_RNPR;         /* Receive Next Pointer Register */
+    AT91_REG DBGU_RNCR;         /* Receive Next Counter Register */
+    AT91_REG DBGU_TNPR;         /* Transmit Next Pointer Register */
+    AT91_REG DBGU_TNCR;         /* Transmit Next Counter Register */
+    AT91_REG DBGU_PTCR;         /* PDC Transfer Control Register */
+    AT91_REG DBGU_PTSR;         /* PDC Transfer Status Register */
+    AT91_REG Reserved5[ 54 ];   /* */
+    AT91_REG PIOA_PER;          /* PIO Enable Register */
+    AT91_REG PIOA_PDR;          /* PIO Disable Register */
+    AT91_REG PIOA_PSR;          /* PIO Status Register */
+    AT91_REG Reserved6[ 1 ];    /* */
+    AT91_REG PIOA_OER;          /* Output Enable Register */
+    AT91_REG PIOA_ODR;          /* Output Disable Registerr */
+    AT91_REG PIOA_OSR;          /* Output Status Register */
+    AT91_REG Reserved7[ 1 ];    /* */
+    AT91_REG PIOA_IFER;         /* Input Filter Enable Register */
+    AT91_REG PIOA_IFDR;         /* Input Filter Disable Register */
+    AT91_REG PIOA_IFSR;         /* Input Filter Status Register */
+    AT91_REG Reserved8[ 1 ];    /* */
+    AT91_REG PIOA_SODR;         /* Set Output Data Register */
+    AT91_REG PIOA_CODR;         /* Clear Output Data Register */
+    AT91_REG PIOA_ODSR;         /* Output Data Status Register */
+    AT91_REG PIOA_PDSR;         /* Pin Data Status Register */
+    AT91_REG PIOA_IER;          /* Interrupt Enable Register */
+    AT91_REG PIOA_IDR;          /* Interrupt Disable Register */
+    AT91_REG PIOA_IMR;          /* Interrupt Mask Register */
+    AT91_REG PIOA_ISR;          /* Interrupt Status Register */
+    AT91_REG PIOA_MDER;         /* Multi-driver Enable Register */
+    AT91_REG PIOA_MDDR;         /* Multi-driver Disable Register */
+    AT91_REG PIOA_MDSR;         /* Multi-driver Status Register */
+    AT91_REG Reserved9[ 1 ];    /* */
+    AT91_REG PIOA_PPUDR;        /* Pull-up Disable Register */
+    AT91_REG PIOA_PPUER;        /* Pull-up Enable Register */
+    AT91_REG PIOA_PPUSR;        /* Pull-up Status Register */
+    AT91_REG Reserved10[ 1 ];   /* */
+    AT91_REG PIOA_ASR;          /* Select A Register */
+    AT91_REG PIOA_BSR;          /* Select B Register */
+    AT91_REG PIOA_ABSR;         /* AB Select Status Register */
+    AT91_REG Reserved11[ 9 ];   /* */
+    AT91_REG PIOA_OWER;         /* Output Write Enable Register */
+    AT91_REG PIOA_OWDR;         /* Output Write Disable Register */
+    AT91_REG PIOA_OWSR;         /* Output Write Status Register */
+    AT91_REG Reserved12[ 85 ];  /* */
+    AT91_REG PIOB_PER;          /* PIO Enable Register */
+    AT91_REG PIOB_PDR;          /* PIO Disable Register */
+    AT91_REG PIOB_PSR;          /* PIO Status Register */
+    AT91_REG Reserved13[ 1 ];   /* */
+    AT91_REG PIOB_OER;          /* Output Enable Register */
+    AT91_REG PIOB_ODR;          /* Output Disable Registerr */
+    AT91_REG PIOB_OSR;          /* Output Status Register */
+    AT91_REG Reserved14[ 1 ];   /* */
+    AT91_REG PIOB_IFER;         /* Input Filter Enable Register */
+    AT91_REG PIOB_IFDR;         /* Input Filter Disable Register */
+    AT91_REG PIOB_IFSR;         /* Input Filter Status Register */
+    AT91_REG Reserved15[ 1 ];   /* */
+    AT91_REG PIOB_SODR;         /* Set Output Data Register */
+    AT91_REG PIOB_CODR;         /* Clear Output Data Register */
+    AT91_REG PIOB_ODSR;         /* Output Data Status Register */
+    AT91_REG PIOB_PDSR;         /* Pin Data Status Register */
+    AT91_REG PIOB_IER;          /* Interrupt Enable Register */
+    AT91_REG PIOB_IDR;          /* Interrupt Disable Register */
+    AT91_REG PIOB_IMR;          /* Interrupt Mask Register */
+    AT91_REG PIOB_ISR;          /* Interrupt Status Register */
+    AT91_REG PIOB_MDER;         /* Multi-driver Enable Register */
+    AT91_REG PIOB_MDDR;         /* Multi-driver Disable Register */
+    AT91_REG PIOB_MDSR;         /* Multi-driver Status Register */
+    AT91_REG Reserved16[ 1 ];   /* */
+    AT91_REG PIOB_PPUDR;        /* Pull-up Disable Register */
+    AT91_REG PIOB_PPUER;        /* Pull-up Enable Register */
+    AT91_REG PIOB_PPUSR;        /* Pull-up Status Register */
+    AT91_REG Reserved17[ 1 ];   /* */
+    AT91_REG PIOB_ASR;          /* Select A Register */
+    AT91_REG PIOB_BSR;          /* Select B Register */
+    AT91_REG PIOB_ABSR;         /* AB Select Status Register */
+    AT91_REG Reserved18[ 9 ];   /* */
+    AT91_REG PIOB_OWER;         /* Output Write Enable Register */
+    AT91_REG PIOB_OWDR;         /* Output Write Disable Register */
+    AT91_REG PIOB_OWSR;         /* Output Write Status Register */
+    AT91_REG Reserved19[ 341 ]; /* */
+    AT91_REG PMC_SCER;          /* System Clock Enable Register */
+    AT91_REG PMC_SCDR;          /* System Clock Disable Register */
+    AT91_REG PMC_SCSR;          /* System Clock Status Register */
+    AT91_REG Reserved20[ 1 ];   /* */
+    AT91_REG PMC_PCER;          /* Peripheral Clock Enable Register */
+    AT91_REG PMC_PCDR;          /* Peripheral Clock Disable Register */
+    AT91_REG PMC_PCSR;          /* Peripheral Clock Status Register */
+    AT91_REG Reserved21[ 1 ];   /* */
+    AT91_REG PMC_MOR;           /* Main Oscillator Register */
+    AT91_REG PMC_MCFR;          /* Main Clock  Frequency Register */
+    AT91_REG Reserved22[ 1 ];   /* */
+    AT91_REG PMC_PLLR;          /* PLL Register */
+    AT91_REG PMC_MCKR;          /* Master Clock Register */
+    AT91_REG Reserved23[ 3 ];   /* */
+    AT91_REG PMC_PCKR[ 4 ];     /* Programmable Clock Register */
+    AT91_REG Reserved24[ 4 ];   /* */
+    AT91_REG PMC_IER;           /* Interrupt Enable Register */
+    AT91_REG PMC_IDR;           /* Interrupt Disable Register */
+    AT91_REG PMC_SR;            /* Status Register */
+    AT91_REG PMC_IMR;           /* Interrupt Mask Register */
+    AT91_REG Reserved25[ 36 ];  /* */
+    AT91_REG RSTC_RCR;          /* Reset Control Register */
+    AT91_REG RSTC_RSR;          /* Reset Status Register */
+    AT91_REG RSTC_RMR;          /* Reset Mode Register */
+    AT91_REG Reserved26[ 5 ];   /* */
+    AT91_REG RTTC_RTMR;         /* Real-time Mode Register */
+    AT91_REG RTTC_RTAR;         /* Real-time Alarm Register */
+    AT91_REG RTTC_RTVR;         /* Real-time Value Register */
+    AT91_REG RTTC_RTSR;         /* Real-time Status Register */
+    AT91_REG PITC_PIMR;         /* Period Interval Mode Register */
+    AT91_REG PITC_PISR;         /* Period Interval Status Register */
+    AT91_REG PITC_PIVR;         /* Period Interval Value Register */
+    AT91_REG PITC_PIIR;         /* Period Interval Image Register */
+    AT91_REG WDTC_WDCR;         /* Watchdog Control Register */
+    AT91_REG WDTC_WDMR;         /* Watchdog Mode Register */
+    AT91_REG WDTC_WDSR;         /* Watchdog Status Register */
+    AT91_REG Reserved27[ 5 ];   /* */
+    AT91_REG VREG_MR;           /* Voltage Regulator Mode Register */
+} AT91S_SYS, * AT91PS_SYS;
 
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
-// *****************************************************************************
-typedef struct _AT91S_AIC {
-    AT91_REG     AIC_SMR[32];   // Source Mode Register
-    AT91_REG     AIC_SVR[32];   // Source Vector Register
-    AT91_REG     AIC_IVR;   // IRQ Vector Register
-    AT91_REG     AIC_FVR;   // FIQ Vector Register
-    AT91_REG     AIC_ISR;   // Interrupt Status Register
-    AT91_REG     AIC_IPR;   // Interrupt Pending Register
-    AT91_REG     AIC_IMR;   // Interrupt Mask Register
-    AT91_REG     AIC_CISR;  // Core Interrupt Status Register
-    AT91_REG     Reserved0[2];  //
-    AT91_REG     AIC_IECR;  // Interrupt Enable Command Register
-    AT91_REG     AIC_IDCR;  // Interrupt Disable Command Register
-    AT91_REG     AIC_ICCR;  // Interrupt Clear Command Register
-    AT91_REG     AIC_ISCR;  // Interrupt Set Command Register
-    AT91_REG     AIC_EOICR;     // End of Interrupt Command Register
-    AT91_REG     AIC_SPU;   // Spurious Vector Register
-    AT91_REG     AIC_DCR;   // Debug Control Register (Protect)
-    AT91_REG     Reserved1[1];  //
-    AT91_REG     AIC_FFER;  // Fast Forcing Enable Register
-    AT91_REG     AIC_FFDR;  // Fast Forcing Disable Register
-    AT91_REG     AIC_FFSR;  // Fast Forcing Status Register
-} AT91S_AIC, *AT91PS_AIC;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller */
+/* ***************************************************************************** */
+typedef struct _AT91S_AIC
+{
+    AT91_REG AIC_SMR[ 32 ];  /* Source Mode Register */
+    AT91_REG AIC_SVR[ 32 ];  /* Source Vector Register */
+    AT91_REG AIC_IVR;        /* IRQ Vector Register */
+    AT91_REG AIC_FVR;        /* FIQ Vector Register */
+    AT91_REG AIC_ISR;        /* Interrupt Status Register */
+    AT91_REG AIC_IPR;        /* Interrupt Pending Register */
+    AT91_REG AIC_IMR;        /* Interrupt Mask Register */
+    AT91_REG AIC_CISR;       /* Core Interrupt Status Register */
+    AT91_REG Reserved0[ 2 ]; /* */
+    AT91_REG AIC_IECR;       /* Interrupt Enable Command Register */
+    AT91_REG AIC_IDCR;       /* Interrupt Disable Command Register */
+    AT91_REG AIC_ICCR;       /* Interrupt Clear Command Register */
+    AT91_REG AIC_ISCR;       /* Interrupt Set Command Register */
+    AT91_REG AIC_EOICR;      /* End of Interrupt Command Register */
+    AT91_REG AIC_SPU;        /* Spurious Vector Register */
+    AT91_REG AIC_DCR;        /* Debug Control Register (Protect) */
+    AT91_REG Reserved1[ 1 ]; /* */
+    AT91_REG AIC_FFER;       /* Fast Forcing Enable Register */
+    AT91_REG AIC_FFDR;       /* Fast Forcing Disable Register */
+    AT91_REG AIC_FFSR;       /* Fast Forcing Status Register */
+} AT91S_AIC, * AT91PS_AIC;
 
-// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
-#define AT91C_AIC_PRIOR       ((unsigned int) 0x7 <<  0) // (AIC) Priority Level
-#define     AT91C_AIC_PRIOR_LOWEST               ((unsigned int) 0x0) // (AIC) Lowest priority level
-#define     AT91C_AIC_PRIOR_HIGHEST              ((unsigned int) 0x7) // (AIC) Highest priority level
-#define AT91C_AIC_SRCTYPE     ((unsigned int) 0x3 <<  5) // (AIC) Interrupt Source Type
-#define     AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL       ((unsigned int) 0x0 <<  5) // (AIC) Internal Sources Code Label High-level Sensitive
-#define     AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL        ((unsigned int) 0x0 <<  5) // (AIC) External Sources Code Label Low-level Sensitive
-#define     AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE    ((unsigned int) 0x1 <<  5) // (AIC) Internal Sources Code Label Positive Edge triggered
-#define     AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE    ((unsigned int) 0x1 <<  5) // (AIC) External Sources Code Label Negative Edge triggered
-#define     AT91C_AIC_SRCTYPE_HIGH_LEVEL           ((unsigned int) 0x2 <<  5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
-#define     AT91C_AIC_SRCTYPE_POSITIVE_EDGE        ((unsigned int) 0x3 <<  5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
-// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
-#define AT91C_AIC_NFIQ        ((unsigned int) 0x1 <<  0) // (AIC) NFIQ Status
-#define AT91C_AIC_NIRQ        ((unsigned int) 0x1 <<  1) // (AIC) NIRQ Status
-// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
-#define AT91C_AIC_DCR_PROT    ((unsigned int) 0x1 <<  0) // (AIC) Protection Mode
-#define AT91C_AIC_DCR_GMSK    ((unsigned int) 0x1 <<  1) // (AIC) General Mask
+/* -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- */
+#define AT91C_AIC_PRIOR                            ( ( unsigned int ) 0x7 << 0 ) /* (AIC) Priority Level */
+#define     AT91C_AIC_PRIOR_LOWEST                 ( ( unsigned int ) 0x0 )      /* (AIC) Lowest priority level */
+#define     AT91C_AIC_PRIOR_HIGHEST                ( ( unsigned int ) 0x7 )      /* (AIC) Highest priority level */
+#define AT91C_AIC_SRCTYPE                          ( ( unsigned int ) 0x3 << 5 ) /* (AIC) Interrupt Source Type */
+#define     AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL       ( ( unsigned int ) 0x0 << 5 ) /* (AIC) Internal Sources Code Label High-level Sensitive */
+#define     AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL        ( ( unsigned int ) 0x0 << 5 ) /* (AIC) External Sources Code Label Low-level Sensitive */
+#define     AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE    ( ( unsigned int ) 0x1 << 5 ) /* (AIC) Internal Sources Code Label Positive Edge triggered */
+#define     AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE    ( ( unsigned int ) 0x1 << 5 ) /* (AIC) External Sources Code Label Negative Edge triggered */
+#define     AT91C_AIC_SRCTYPE_HIGH_LEVEL           ( ( unsigned int ) 0x2 << 5 ) /* (AIC) Internal Or External Sources Code Label High-level Sensitive */
+#define     AT91C_AIC_SRCTYPE_POSITIVE_EDGE        ( ( unsigned int ) 0x3 << 5 ) /* (AIC) Internal Or External Sources Code Label Positive Edge triggered */
+/* -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- */
+#define AT91C_AIC_NFIQ                             ( ( unsigned int ) 0x1 << 0 ) /* (AIC) NFIQ Status */
+#define AT91C_AIC_NIRQ                             ( ( unsigned int ) 0x1 << 1 ) /* (AIC) NIRQ Status */
+/* -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- */
+#define AT91C_AIC_DCR_PROT                         ( ( unsigned int ) 0x1 << 0 ) /* (AIC) Protection Mode */
+#define AT91C_AIC_DCR_GMSK                         ( ( unsigned int ) 0x1 << 1 ) /* (AIC) General Mask */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller
-// *****************************************************************************
-typedef struct _AT91S_PDC {
-    AT91_REG     PDC_RPR;   // Receive Pointer Register
-    AT91_REG     PDC_RCR;   // Receive Counter Register
-    AT91_REG     PDC_TPR;   // Transmit Pointer Register
-    AT91_REG     PDC_TCR;   // Transmit Counter Register
-    AT91_REG     PDC_RNPR;  // Receive Next Pointer Register
-    AT91_REG     PDC_RNCR;  // Receive Next Counter Register
-    AT91_REG     PDC_TNPR;  // Transmit Next Pointer Register
-    AT91_REG     PDC_TNCR;  // Transmit Next Counter Register
-    AT91_REG     PDC_PTCR;  // PDC Transfer Control Register
-    AT91_REG     PDC_PTSR;  // PDC Transfer Status Register
-} AT91S_PDC, *AT91PS_PDC;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller */
+/* ***************************************************************************** */
+typedef struct _AT91S_PDC
+{
+    AT91_REG PDC_RPR;  /* Receive Pointer Register */
+    AT91_REG PDC_RCR;  /* Receive Counter Register */
+    AT91_REG PDC_TPR;  /* Transmit Pointer Register */
+    AT91_REG PDC_TCR;  /* Transmit Counter Register */
+    AT91_REG PDC_RNPR; /* Receive Next Pointer Register */
+    AT91_REG PDC_RNCR; /* Receive Next Counter Register */
+    AT91_REG PDC_TNPR; /* Transmit Next Pointer Register */
+    AT91_REG PDC_TNCR; /* Transmit Next Counter Register */
+    AT91_REG PDC_PTCR; /* PDC Transfer Control Register */
+    AT91_REG PDC_PTSR; /* PDC Transfer Status Register */
+} AT91S_PDC, * AT91PS_PDC;
 
-// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
-#define AT91C_PDC_RXTEN       ((unsigned int) 0x1 <<  0) // (PDC) Receiver Transfer Enable
-#define AT91C_PDC_RXTDIS      ((unsigned int) 0x1 <<  1) // (PDC) Receiver Transfer Disable
-#define AT91C_PDC_TXTEN       ((unsigned int) 0x1 <<  8) // (PDC) Transmitter Transfer Enable
-#define AT91C_PDC_TXTDIS      ((unsigned int) 0x1 <<  9) // (PDC) Transmitter Transfer Disable
-// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
+/* -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */
+#define AT91C_PDC_RXTEN     ( ( unsigned int ) 0x1 << 0 ) /* (PDC) Receiver Transfer Enable */
+#define AT91C_PDC_RXTDIS    ( ( unsigned int ) 0x1 << 1 ) /* (PDC) Receiver Transfer Disable */
+#define AT91C_PDC_TXTEN     ( ( unsigned int ) 0x1 << 8 ) /* (PDC) Transmitter Transfer Enable */
+#define AT91C_PDC_TXTDIS    ( ( unsigned int ) 0x1 << 9 ) /* (PDC) Transmitter Transfer Disable */
+/* -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Debug Unit
-// *****************************************************************************
-typedef struct _AT91S_DBGU {
-    AT91_REG     DBGU_CR;   // Control Register
-    AT91_REG     DBGU_MR;   // Mode Register
-    AT91_REG     DBGU_IER;  // Interrupt Enable Register
-    AT91_REG     DBGU_IDR;  // Interrupt Disable Register
-    AT91_REG     DBGU_IMR;  // Interrupt Mask Register
-    AT91_REG     DBGU_CSR;  // Channel Status Register
-    AT91_REG     DBGU_RHR;  // Receiver Holding Register
-    AT91_REG     DBGU_THR;  // Transmitter Holding Register
-    AT91_REG     DBGU_BRGR;     // Baud Rate Generator Register
-    AT91_REG     Reserved0[7];  //
-    AT91_REG     DBGU_CIDR;     // Chip ID Register
-    AT91_REG     DBGU_EXID;     // Chip ID Extension Register
-    AT91_REG     DBGU_FNTR;     // Force NTRST Register
-    AT91_REG     Reserved1[45];     //
-    AT91_REG     DBGU_RPR;  // Receive Pointer Register
-    AT91_REG     DBGU_RCR;  // Receive Counter Register
-    AT91_REG     DBGU_TPR;  // Transmit Pointer Register
-    AT91_REG     DBGU_TCR;  // Transmit Counter Register
-    AT91_REG     DBGU_RNPR;     // Receive Next Pointer Register
-    AT91_REG     DBGU_RNCR;     // Receive Next Counter Register
-    AT91_REG     DBGU_TNPR;     // Transmit Next Pointer Register
-    AT91_REG     DBGU_TNCR;     // Transmit Next Counter Register
-    AT91_REG     DBGU_PTCR;     // PDC Transfer Control Register
-    AT91_REG     DBGU_PTSR;     // PDC Transfer Status Register
-} AT91S_DBGU, *AT91PS_DBGU;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Debug Unit */
+/* ***************************************************************************** */
+typedef struct _AT91S_DBGU
+{
+    AT91_REG DBGU_CR;         /* Control Register */
+    AT91_REG DBGU_MR;         /* Mode Register */
+    AT91_REG DBGU_IER;        /* Interrupt Enable Register */
+    AT91_REG DBGU_IDR;        /* Interrupt Disable Register */
+    AT91_REG DBGU_IMR;        /* Interrupt Mask Register */
+    AT91_REG DBGU_CSR;        /* Channel Status Register */
+    AT91_REG DBGU_RHR;        /* Receiver Holding Register */
+    AT91_REG DBGU_THR;        /* Transmitter Holding Register */
+    AT91_REG DBGU_BRGR;       /* Baud Rate Generator Register */
+    AT91_REG Reserved0[ 7 ];  /* */
+    AT91_REG DBGU_CIDR;       /* Chip ID Register */
+    AT91_REG DBGU_EXID;       /* Chip ID Extension Register */
+    AT91_REG DBGU_FNTR;       /* Force NTRST Register */
+    AT91_REG Reserved1[ 45 ]; /* */
+    AT91_REG DBGU_RPR;        /* Receive Pointer Register */
+    AT91_REG DBGU_RCR;        /* Receive Counter Register */
+    AT91_REG DBGU_TPR;        /* Transmit Pointer Register */
+    AT91_REG DBGU_TCR;        /* Transmit Counter Register */
+    AT91_REG DBGU_RNPR;       /* Receive Next Pointer Register */
+    AT91_REG DBGU_RNCR;       /* Receive Next Counter Register */
+    AT91_REG DBGU_TNPR;       /* Transmit Next Pointer Register */
+    AT91_REG DBGU_TNCR;       /* Transmit Next Counter Register */
+    AT91_REG DBGU_PTCR;       /* PDC Transfer Control Register */
+    AT91_REG DBGU_PTSR;       /* PDC Transfer Status Register */
+} AT91S_DBGU, * AT91PS_DBGU;
 
-// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
-#define AT91C_US_RSTRX        ((unsigned int) 0x1 <<  2) // (DBGU) Reset Receiver
-#define AT91C_US_RSTTX        ((unsigned int) 0x1 <<  3) // (DBGU) Reset Transmitter
-#define AT91C_US_RXEN         ((unsigned int) 0x1 <<  4) // (DBGU) Receiver Enable
-#define AT91C_US_RXDIS        ((unsigned int) 0x1 <<  5) // (DBGU) Receiver Disable
-#define AT91C_US_TXEN         ((unsigned int) 0x1 <<  6) // (DBGU) Transmitter Enable
-#define AT91C_US_TXDIS        ((unsigned int) 0x1 <<  7) // (DBGU) Transmitter Disable
-#define AT91C_US_RSTSTA       ((unsigned int) 0x1 <<  8) // (DBGU) Reset Status Bits
-// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
-#define AT91C_US_PAR          ((unsigned int) 0x7 <<  9) // (DBGU) Parity type
-#define     AT91C_US_PAR_EVEN                 ((unsigned int) 0x0 <<  9) // (DBGU) Even Parity
-#define     AT91C_US_PAR_ODD                  ((unsigned int) 0x1 <<  9) // (DBGU) Odd Parity
-#define     AT91C_US_PAR_SPACE                ((unsigned int) 0x2 <<  9) // (DBGU) Parity forced to 0 (Space)
-#define     AT91C_US_PAR_MARK                 ((unsigned int) 0x3 <<  9) // (DBGU) Parity forced to 1 (Mark)
-#define     AT91C_US_PAR_NONE                 ((unsigned int) 0x4 <<  9) // (DBGU) No Parity
-#define     AT91C_US_PAR_MULTI_DROP           ((unsigned int) 0x6 <<  9) // (DBGU) Multi-drop mode
-#define AT91C_US_CHMODE       ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode
-#define     AT91C_US_CHMODE_NORMAL               ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
-#define     AT91C_US_CHMODE_AUTO                 ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
-#define     AT91C_US_CHMODE_LOCAL                ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
-#define     AT91C_US_CHMODE_REMOTE               ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
-// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
-#define AT91C_US_RXRDY        ((unsigned int) 0x1 <<  0) // (DBGU) RXRDY Interrupt
-#define AT91C_US_TXRDY        ((unsigned int) 0x1 <<  1) // (DBGU) TXRDY Interrupt
-#define AT91C_US_ENDRX        ((unsigned int) 0x1 <<  3) // (DBGU) End of Receive Transfer Interrupt
-#define AT91C_US_ENDTX        ((unsigned int) 0x1 <<  4) // (DBGU) End of Transmit Interrupt
-#define AT91C_US_OVRE         ((unsigned int) 0x1 <<  5) // (DBGU) Overrun Interrupt
-#define AT91C_US_FRAME        ((unsigned int) 0x1 <<  6) // (DBGU) Framing Error Interrupt
-#define AT91C_US_PARE         ((unsigned int) 0x1 <<  7) // (DBGU) Parity Error Interrupt
-#define AT91C_US_TXEMPTY      ((unsigned int) 0x1 <<  9) // (DBGU) TXEMPTY Interrupt
-#define AT91C_US_TXBUFE       ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt
-#define AT91C_US_RXBUFF       ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt
-#define AT91C_US_COMM_TX      ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt
-#define AT91C_US_COMM_RX      ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt
-// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
-// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
-// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
-// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
-#define AT91C_US_FORCE_NTRST  ((unsigned int) 0x1 <<  0) // (DBGU) Force NTRST in JTAG
+/* -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- */
+#define AT91C_US_RSTRX                 ( ( unsigned int ) 0x1 << 2 )  /* (DBGU) Reset Receiver */
+#define AT91C_US_RSTTX                 ( ( unsigned int ) 0x1 << 3 )  /* (DBGU) Reset Transmitter */
+#define AT91C_US_RXEN                  ( ( unsigned int ) 0x1 << 4 )  /* (DBGU) Receiver Enable */
+#define AT91C_US_RXDIS                 ( ( unsigned int ) 0x1 << 5 )  /* (DBGU) Receiver Disable */
+#define AT91C_US_TXEN                  ( ( unsigned int ) 0x1 << 6 )  /* (DBGU) Transmitter Enable */
+#define AT91C_US_TXDIS                 ( ( unsigned int ) 0x1 << 7 )  /* (DBGU) Transmitter Disable */
+#define AT91C_US_RSTSTA                ( ( unsigned int ) 0x1 << 8 )  /* (DBGU) Reset Status Bits */
+/* -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- */
+#define AT91C_US_PAR                   ( ( unsigned int ) 0x7 << 9 )  /* (DBGU) Parity type */
+#define     AT91C_US_PAR_EVEN          ( ( unsigned int ) 0x0 << 9 )  /* (DBGU) Even Parity */
+#define     AT91C_US_PAR_ODD           ( ( unsigned int ) 0x1 << 9 )  /* (DBGU) Odd Parity */
+#define     AT91C_US_PAR_SPACE         ( ( unsigned int ) 0x2 << 9 )  /* (DBGU) Parity forced to 0 (Space) */
+#define     AT91C_US_PAR_MARK          ( ( unsigned int ) 0x3 << 9 )  /* (DBGU) Parity forced to 1 (Mark) */
+#define     AT91C_US_PAR_NONE          ( ( unsigned int ) 0x4 << 9 )  /* (DBGU) No Parity */
+#define     AT91C_US_PAR_MULTI_DROP    ( ( unsigned int ) 0x6 << 9 )  /* (DBGU) Multi-drop mode */
+#define AT91C_US_CHMODE                ( ( unsigned int ) 0x3 << 14 ) /* (DBGU) Channel Mode */
+#define     AT91C_US_CHMODE_NORMAL     ( ( unsigned int ) 0x0 << 14 ) /* (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. */
+#define     AT91C_US_CHMODE_AUTO       ( ( unsigned int ) 0x1 << 14 ) /* (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. */
+#define     AT91C_US_CHMODE_LOCAL      ( ( unsigned int ) 0x2 << 14 ) /* (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. */
+#define     AT91C_US_CHMODE_REMOTE     ( ( unsigned int ) 0x3 << 14 ) /* (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. */
+/* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */
+#define AT91C_US_RXRDY                 ( ( unsigned int ) 0x1 << 0 )  /* (DBGU) RXRDY Interrupt */
+#define AT91C_US_TXRDY                 ( ( unsigned int ) 0x1 << 1 )  /* (DBGU) TXRDY Interrupt */
+#define AT91C_US_ENDRX                 ( ( unsigned int ) 0x1 << 3 )  /* (DBGU) End of Receive Transfer Interrupt */
+#define AT91C_US_ENDTX                 ( ( unsigned int ) 0x1 << 4 )  /* (DBGU) End of Transmit Interrupt */
+#define AT91C_US_OVRE                  ( ( unsigned int ) 0x1 << 5 )  /* (DBGU) Overrun Interrupt */
+#define AT91C_US_FRAME                 ( ( unsigned int ) 0x1 << 6 )  /* (DBGU) Framing Error Interrupt */
+#define AT91C_US_PARE                  ( ( unsigned int ) 0x1 << 7 )  /* (DBGU) Parity Error Interrupt */
+#define AT91C_US_TXEMPTY               ( ( unsigned int ) 0x1 << 9 )  /* (DBGU) TXEMPTY Interrupt */
+#define AT91C_US_TXBUFE                ( ( unsigned int ) 0x1 << 11 ) /* (DBGU) TXBUFE Interrupt */
+#define AT91C_US_RXBUFF                ( ( unsigned int ) 0x1 << 12 ) /* (DBGU) RXBUFF Interrupt */
+#define AT91C_US_COMM_TX               ( ( unsigned int ) 0x1 << 30 ) /* (DBGU) COMM_TX Interrupt */
+#define AT91C_US_COMM_RX               ( ( unsigned int ) 0x1 << 31 ) /* (DBGU) COMM_RX Interrupt */
+/* -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- */
+/* -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- */
+/* -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- */
+/* -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- */
+#define AT91C_US_FORCE_NTRST    ( ( unsigned int ) 0x1 << 0 ) /* (DBGU) Force NTRST in JTAG */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
-// *****************************************************************************
-typedef struct _AT91S_PIO {
-    AT91_REG     PIO_PER;   // PIO Enable Register
-    AT91_REG     PIO_PDR;   // PIO Disable Register
-    AT91_REG     PIO_PSR;   // PIO Status Register
-    AT91_REG     Reserved0[1];  //
-    AT91_REG     PIO_OER;   // Output Enable Register
-    AT91_REG     PIO_ODR;   // Output Disable Registerr
-    AT91_REG     PIO_OSR;   // Output Status Register
-    AT91_REG     Reserved1[1];  //
-    AT91_REG     PIO_IFER;  // Input Filter Enable Register
-    AT91_REG     PIO_IFDR;  // Input Filter Disable Register
-    AT91_REG     PIO_IFSR;  // Input Filter Status Register
-    AT91_REG     Reserved2[1];  //
-    AT91_REG     PIO_SODR;  // Set Output Data Register
-    AT91_REG     PIO_CODR;  // Clear Output Data Register
-    AT91_REG     PIO_ODSR;  // Output Data Status Register
-    AT91_REG     PIO_PDSR;  // Pin Data Status Register
-    AT91_REG     PIO_IER;   // Interrupt Enable Register
-    AT91_REG     PIO_IDR;   // Interrupt Disable Register
-    AT91_REG     PIO_IMR;   // Interrupt Mask Register
-    AT91_REG     PIO_ISR;   // Interrupt Status Register
-    AT91_REG     PIO_MDER;  // Multi-driver Enable Register
-    AT91_REG     PIO_MDDR;  // Multi-driver Disable Register
-    AT91_REG     PIO_MDSR;  // Multi-driver Status Register
-    AT91_REG     Reserved3[1];  //
-    AT91_REG     PIO_PPUDR;     // Pull-up Disable Register
-    AT91_REG     PIO_PPUER;     // Pull-up Enable Register
-    AT91_REG     PIO_PPUSR;     // Pull-up Status Register
-    AT91_REG     Reserved4[1];  //
-    AT91_REG     PIO_ASR;   // Select A Register
-    AT91_REG     PIO_BSR;   // Select B Register
-    AT91_REG     PIO_ABSR;  // AB Select Status Register
-    AT91_REG     Reserved5[9];  //
-    AT91_REG     PIO_OWER;  // Output Write Enable Register
-    AT91_REG     PIO_OWDR;  // Output Write Disable Register
-    AT91_REG     PIO_OWSR;  // Output Write Status Register
-} AT91S_PIO, *AT91PS_PIO;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Parallel Input Output Controller */
+/* ***************************************************************************** */
+typedef struct _AT91S_PIO
+{
+    AT91_REG PIO_PER;        /* PIO Enable Register */
+    AT91_REG PIO_PDR;        /* PIO Disable Register */
+    AT91_REG PIO_PSR;        /* PIO Status Register */
+    AT91_REG Reserved0[ 1 ]; /* */
+    AT91_REG PIO_OER;        /* Output Enable Register */
+    AT91_REG PIO_ODR;        /* Output Disable Registerr */
+    AT91_REG PIO_OSR;        /* Output Status Register */
+    AT91_REG Reserved1[ 1 ]; /* */
+    AT91_REG PIO_IFER;       /* Input Filter Enable Register */
+    AT91_REG PIO_IFDR;       /* Input Filter Disable Register */
+    AT91_REG PIO_IFSR;       /* Input Filter Status Register */
+    AT91_REG Reserved2[ 1 ]; /* */
+    AT91_REG PIO_SODR;       /* Set Output Data Register */
+    AT91_REG PIO_CODR;       /* Clear Output Data Register */
+    AT91_REG PIO_ODSR;       /* Output Data Status Register */
+    AT91_REG PIO_PDSR;       /* Pin Data Status Register */
+    AT91_REG PIO_IER;        /* Interrupt Enable Register */
+    AT91_REG PIO_IDR;        /* Interrupt Disable Register */
+    AT91_REG PIO_IMR;        /* Interrupt Mask Register */
+    AT91_REG PIO_ISR;        /* Interrupt Status Register */
+    AT91_REG PIO_MDER;       /* Multi-driver Enable Register */
+    AT91_REG PIO_MDDR;       /* Multi-driver Disable Register */
+    AT91_REG PIO_MDSR;       /* Multi-driver Status Register */
+    AT91_REG Reserved3[ 1 ]; /* */
+    AT91_REG PIO_PPUDR;      /* Pull-up Disable Register */
+    AT91_REG PIO_PPUER;      /* Pull-up Enable Register */
+    AT91_REG PIO_PPUSR;      /* Pull-up Status Register */
+    AT91_REG Reserved4[ 1 ]; /* */
+    AT91_REG PIO_ASR;        /* Select A Register */
+    AT91_REG PIO_BSR;        /* Select B Register */
+    AT91_REG PIO_ABSR;       /* AB Select Status Register */
+    AT91_REG Reserved5[ 9 ]; /* */
+    AT91_REG PIO_OWER;       /* Output Write Enable Register */
+    AT91_REG PIO_OWDR;       /* Output Write Disable Register */
+    AT91_REG PIO_OWSR;       /* Output Write Status Register */
+} AT91S_PIO, * AT91PS_PIO;
 
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Clock Generator Controler
-// *****************************************************************************
-typedef struct _AT91S_CKGR {
-    AT91_REG     CKGR_MOR;  // Main Oscillator Register
-    AT91_REG     CKGR_MCFR;     // Main Clock  Frequency Register
-    AT91_REG     Reserved0[1];  //
-    AT91_REG     CKGR_PLLR;     // PLL Register
-} AT91S_CKGR, *AT91PS_CKGR;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Clock Generator Controller */
+/* ***************************************************************************** */
+typedef struct _AT91S_CKGR
+{
+    AT91_REG CKGR_MOR;       /* Main Oscillator Register */
+    AT91_REG CKGR_MCFR;      /* Main Clock  Frequency Register */
+    AT91_REG Reserved0[ 1 ]; /* */
+    AT91_REG CKGR_PLLR;      /* PLL Register */
+} AT91S_CKGR, * AT91PS_CKGR;
 
-// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
-#define AT91C_CKGR_MOSCEN     ((unsigned int) 0x1 <<  0) // (CKGR) Main Oscillator Enable
-#define AT91C_CKGR_OSCBYPASS  ((unsigned int) 0x1 <<  1) // (CKGR) Main Oscillator Bypass
-#define AT91C_CKGR_OSCOUNT    ((unsigned int) 0xFF <<  8) // (CKGR) Main Oscillator Start-up Time
-// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
-#define AT91C_CKGR_MAINF      ((unsigned int) 0xFFFF <<  0) // (CKGR) Main Clock Frequency
-#define AT91C_CKGR_MAINRDY    ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready
-// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
-#define AT91C_CKGR_DIV        ((unsigned int) 0xFF <<  0) // (CKGR) Divider Selected
-#define     AT91C_CKGR_DIV_0                    ((unsigned int) 0x0) // (CKGR) Divider output is 0
-#define     AT91C_CKGR_DIV_BYPASS               ((unsigned int) 0x1) // (CKGR) Divider is bypassed
-#define AT91C_CKGR_PLLCOUNT   ((unsigned int) 0x3F <<  8) // (CKGR) PLL Counter
-#define AT91C_CKGR_OUT        ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range
-#define     AT91C_CKGR_OUT_0                    ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet
-#define     AT91C_CKGR_OUT_1                    ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet
-#define     AT91C_CKGR_OUT_2                    ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet
-#define     AT91C_CKGR_OUT_3                    ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_MUL        ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier
-#define AT91C_CKGR_USBDIV     ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks
-#define     AT91C_CKGR_USBDIV_0                    ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output
-#define     AT91C_CKGR_USBDIV_1                    ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
-#define     AT91C_CKGR_USBDIV_2                    ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
+/* -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */
+#define AT91C_CKGR_MOSCEN            ( ( unsigned int ) 0x1 << 0 )    /* (CKGR) Main Oscillator Enable */
+#define AT91C_CKGR_OSCBYPASS         ( ( unsigned int ) 0x1 << 1 )    /* (CKGR) Main Oscillator Bypass */
+#define AT91C_CKGR_OSCOUNT           ( ( unsigned int ) 0xFF << 8 )   /* (CKGR) Main Oscillator Start-up Time */
+/* -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- */
+#define AT91C_CKGR_MAINF             ( ( unsigned int ) 0xFFFF << 0 ) /* (CKGR) Main Clock Frequency */
+#define AT91C_CKGR_MAINRDY           ( ( unsigned int ) 0x1 << 16 )   /* (CKGR) Main Clock Ready */
+/* -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- */
+#define AT91C_CKGR_DIV               ( ( unsigned int ) 0xFF << 0 )   /* (CKGR) Divider Selected */
+#define     AT91C_CKGR_DIV_0         ( ( unsigned int ) 0x0 )         /* (CKGR) Divider output is 0 */
+#define     AT91C_CKGR_DIV_BYPASS    ( ( unsigned int ) 0x1 )         /* (CKGR) Divider is bypassed */
+#define AT91C_CKGR_PLLCOUNT          ( ( unsigned int ) 0x3F << 8 )   /* (CKGR) PLL Counter */
+#define AT91C_CKGR_OUT               ( ( unsigned int ) 0x3 << 14 )   /* (CKGR) PLL Output Frequency Range */
+#define     AT91C_CKGR_OUT_0         ( ( unsigned int ) 0x0 << 14 )   /* (CKGR) Please refer to the PLL datasheet */
+#define     AT91C_CKGR_OUT_1         ( ( unsigned int ) 0x1 << 14 )   /* (CKGR) Please refer to the PLL datasheet */
+#define     AT91C_CKGR_OUT_2         ( ( unsigned int ) 0x2 << 14 )   /* (CKGR) Please refer to the PLL datasheet */
+#define     AT91C_CKGR_OUT_3         ( ( unsigned int ) 0x3 << 14 )   /* (CKGR) Please refer to the PLL datasheet */
+#define AT91C_CKGR_MUL               ( ( unsigned int ) 0x7FF << 16 ) /* (CKGR) PLL Multiplier */
+#define AT91C_CKGR_USBDIV            ( ( unsigned int ) 0x3 << 28 )   /* (CKGR) Divider for USB Clocks */
+#define     AT91C_CKGR_USBDIV_0      ( ( unsigned int ) 0x0 << 28 )   /* (CKGR) Divider output is PLL clock output */
+#define     AT91C_CKGR_USBDIV_1      ( ( unsigned int ) 0x1 << 28 )   /* (CKGR) Divider output is PLL clock output divided by 2 */
+#define     AT91C_CKGR_USBDIV_2      ( ( unsigned int ) 0x2 << 28 )   /* (CKGR) Divider output is PLL clock output divided by 4 */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Power Management Controler
-// *****************************************************************************
-typedef struct _AT91S_PMC {
-    AT91_REG     PMC_SCER;  // System Clock Enable Register
-    AT91_REG     PMC_SCDR;  // System Clock Disable Register
-    AT91_REG     PMC_SCSR;  // System Clock Status Register
-    AT91_REG     Reserved0[1];  //
-    AT91_REG     PMC_PCER;  // Peripheral Clock Enable Register
-    AT91_REG     PMC_PCDR;  // Peripheral Clock Disable Register
-    AT91_REG     PMC_PCSR;  // Peripheral Clock Status Register
-    AT91_REG     Reserved1[1];  //
-    AT91_REG     PMC_MOR;   // Main Oscillator Register
-    AT91_REG     PMC_MCFR;  // Main Clock  Frequency Register
-    AT91_REG     Reserved2[1];  //
-    AT91_REG     PMC_PLLR;  // PLL Register
-    AT91_REG     PMC_MCKR;  // Master Clock Register
-    AT91_REG     Reserved3[3];  //
-    AT91_REG     PMC_PCKR[4];   // Programmable Clock Register
-    AT91_REG     Reserved4[4];  //
-    AT91_REG     PMC_IER;   // Interrupt Enable Register
-    AT91_REG     PMC_IDR;   // Interrupt Disable Register
-    AT91_REG     PMC_SR;    // Status Register
-    AT91_REG     PMC_IMR;   // Interrupt Mask Register
-} AT91S_PMC, *AT91PS_PMC;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Power Management Controller */
+/* ***************************************************************************** */
+typedef struct _AT91S_PMC
+{
+    AT91_REG PMC_SCER;       /* System Clock Enable Register */
+    AT91_REG PMC_SCDR;       /* System Clock Disable Register */
+    AT91_REG PMC_SCSR;       /* System Clock Status Register */
+    AT91_REG Reserved0[ 1 ]; /* */
+    AT91_REG PMC_PCER;       /* Peripheral Clock Enable Register */
+    AT91_REG PMC_PCDR;       /* Peripheral Clock Disable Register */
+    AT91_REG PMC_PCSR;       /* Peripheral Clock Status Register */
+    AT91_REG Reserved1[ 1 ]; /* */
+    AT91_REG PMC_MOR;        /* Main Oscillator Register */
+    AT91_REG PMC_MCFR;       /* Main Clock  Frequency Register */
+    AT91_REG Reserved2[ 1 ]; /* */
+    AT91_REG PMC_PLLR;       /* PLL Register */
+    AT91_REG PMC_MCKR;       /* Master Clock Register */
+    AT91_REG Reserved3[ 3 ]; /* */
+    AT91_REG PMC_PCKR[ 4 ];  /* Programmable Clock Register */
+    AT91_REG Reserved4[ 4 ]; /* */
+    AT91_REG PMC_IER;        /* Interrupt Enable Register */
+    AT91_REG PMC_IDR;        /* Interrupt Disable Register */
+    AT91_REG PMC_SR;         /* Status Register */
+    AT91_REG PMC_IMR;        /* Interrupt Mask Register */
+} AT91S_PMC, * AT91PS_PMC;
 
-// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
-#define AT91C_PMC_PCK         ((unsigned int) 0x1 <<  0) // (PMC) Processor Clock
-#define AT91C_PMC_UDP         ((unsigned int) 0x1 <<  7) // (PMC) USB Device Port Clock
-#define AT91C_PMC_PCK0        ((unsigned int) 0x1 <<  8) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK1        ((unsigned int) 0x1 <<  9) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK2        ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK3        ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output
-// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
-// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
-// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
-// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
-// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
-// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
-#define AT91C_PMC_CSS         ((unsigned int) 0x3 <<  0) // (PMC) Programmable Clock Selection
-#define     AT91C_PMC_CSS_SLOW_CLK             ((unsigned int) 0x0) // (PMC) Slow Clock is selected
-#define     AT91C_PMC_CSS_MAIN_CLK             ((unsigned int) 0x1) // (PMC) Main Clock is selected
-#define     AT91C_PMC_CSS_PLL_CLK              ((unsigned int) 0x3) // (PMC) Clock from PLL is selected
-#define AT91C_PMC_PRES        ((unsigned int) 0x7 <<  2) // (PMC) Programmable Clock Prescaler
-#define     AT91C_PMC_PRES_CLK                  ((unsigned int) 0x0 <<  2) // (PMC) Selected clock
-#define     AT91C_PMC_PRES_CLK_2                ((unsigned int) 0x1 <<  2) // (PMC) Selected clock divided by 2
-#define     AT91C_PMC_PRES_CLK_4                ((unsigned int) 0x2 <<  2) // (PMC) Selected clock divided by 4
-#define     AT91C_PMC_PRES_CLK_8                ((unsigned int) 0x3 <<  2) // (PMC) Selected clock divided by 8
-#define     AT91C_PMC_PRES_CLK_16               ((unsigned int) 0x4 <<  2) // (PMC) Selected clock divided by 16
-#define     AT91C_PMC_PRES_CLK_32               ((unsigned int) 0x5 <<  2) // (PMC) Selected clock divided by 32
-#define     AT91C_PMC_PRES_CLK_64               ((unsigned int) 0x6 <<  2) // (PMC) Selected clock divided by 64
-// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
-// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
-#define AT91C_PMC_MOSCS       ((unsigned int) 0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask
-#define AT91C_PMC_LOCK        ((unsigned int) 0x1 <<  2) // (PMC) PLL Status/Enable/Disable/Mask
-#define AT91C_PMC_MCKRDY      ((unsigned int) 0x1 <<  3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK0RDY     ((unsigned int) 0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK1RDY     ((unsigned int) 0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK2RDY     ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK3RDY     ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
-// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
-// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
-// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
+/* -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- */
+#define AT91C_PMC_PCK     ( ( unsigned int ) 0x1 << 0 )  /* (PMC) Processor Clock */
+#define AT91C_PMC_UDP     ( ( unsigned int ) 0x1 << 7 )  /* (PMC) USB Device Port Clock */
+#define AT91C_PMC_PCK0    ( ( unsigned int ) 0x1 << 8 )  /* (PMC) Programmable Clock Output */
+#define AT91C_PMC_PCK1    ( ( unsigned int ) 0x1 << 9 )  /* (PMC) Programmable Clock Output */
+#define AT91C_PMC_PCK2    ( ( unsigned int ) 0x1 << 10 ) /* (PMC) Programmable Clock Output */
+#define AT91C_PMC_PCK3    ( ( unsigned int ) 0x1 << 11 ) /* (PMC) Programmable Clock Output */
+/* -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- */
+/* -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- */
+/* -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- */
+/* -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- */
+/* -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- */
+/* -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- */
+#define AT91C_PMC_CSS                 ( ( unsigned int ) 0x3 << 0 ) /* (PMC) Programmable Clock Selection */
+#define     AT91C_PMC_CSS_SLOW_CLK    ( ( unsigned int ) 0x0 )      /* (PMC) Slow Clock is selected */
+#define     AT91C_PMC_CSS_MAIN_CLK    ( ( unsigned int ) 0x1 )      /* (PMC) Main Clock is selected */
+#define     AT91C_PMC_CSS_PLL_CLK     ( ( unsigned int ) 0x3 )      /* (PMC) Clock from PLL is selected */
+#define AT91C_PMC_PRES                ( ( unsigned int ) 0x7 << 2 ) /* (PMC) Programmable Clock Prescaler */
+#define     AT91C_PMC_PRES_CLK        ( ( unsigned int ) 0x0 << 2 ) /* (PMC) Selected clock */
+#define     AT91C_PMC_PRES_CLK_2      ( ( unsigned int ) 0x1 << 2 ) /* (PMC) Selected clock divided by 2 */
+#define     AT91C_PMC_PRES_CLK_4      ( ( unsigned int ) 0x2 << 2 ) /* (PMC) Selected clock divided by 4 */
+#define     AT91C_PMC_PRES_CLK_8      ( ( unsigned int ) 0x3 << 2 ) /* (PMC) Selected clock divided by 8 */
+#define     AT91C_PMC_PRES_CLK_16     ( ( unsigned int ) 0x4 << 2 ) /* (PMC) Selected clock divided by 16 */
+#define     AT91C_PMC_PRES_CLK_32     ( ( unsigned int ) 0x5 << 2 ) /* (PMC) Selected clock divided by 32 */
+#define     AT91C_PMC_PRES_CLK_64     ( ( unsigned int ) 0x6 << 2 ) /* (PMC) Selected clock divided by 64 */
+/* -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- */
+/* -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- */
+#define AT91C_PMC_MOSCS               ( ( unsigned int ) 0x1 << 0 )  /* (PMC) MOSC Status/Enable/Disable/Mask */
+#define AT91C_PMC_LOCK                ( ( unsigned int ) 0x1 << 2 )  /* (PMC) PLL Status/Enable/Disable/Mask */
+#define AT91C_PMC_MCKRDY              ( ( unsigned int ) 0x1 << 3 )  /* (PMC) MCK_RDY Status/Enable/Disable/Mask */
+#define AT91C_PMC_PCK0RDY             ( ( unsigned int ) 0x1 << 8 )  /* (PMC) PCK0_RDY Status/Enable/Disable/Mask */
+#define AT91C_PMC_PCK1RDY             ( ( unsigned int ) 0x1 << 9 )  /* (PMC) PCK1_RDY Status/Enable/Disable/Mask */
+#define AT91C_PMC_PCK2RDY             ( ( unsigned int ) 0x1 << 10 ) /* (PMC) PCK2_RDY Status/Enable/Disable/Mask */
+#define AT91C_PMC_PCK3RDY             ( ( unsigned int ) 0x1 << 11 ) /* (PMC) PCK3_RDY Status/Enable/Disable/Mask */
+/* -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- */
+/* -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- */
+/* -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Reset Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_RSTC {
-    AT91_REG     RSTC_RCR;  // Reset Control Register
-    AT91_REG     RSTC_RSR;  // Reset Status Register
-    AT91_REG     RSTC_RMR;  // Reset Mode Register
-} AT91S_RSTC, *AT91PS_RSTC;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Reset Controller Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_RSTC
+{
+    AT91_REG RSTC_RCR; /* Reset Control Register */
+    AT91_REG RSTC_RSR; /* Reset Status Register */
+    AT91_REG RSTC_RMR; /* Reset Mode Register */
+} AT91S_RSTC, * AT91PS_RSTC;
 
-// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
-#define AT91C_RSTC_PROCRST    ((unsigned int) 0x1 <<  0) // (RSTC) Processor Reset
-#define AT91C_RSTC_PERRST     ((unsigned int) 0x1 <<  2) // (RSTC) Peripheral Reset
-#define AT91C_RSTC_EXTRST     ((unsigned int) 0x1 <<  3) // (RSTC) External Reset
-#define AT91C_RSTC_KEY        ((unsigned int) 0xFF << 24) // (RSTC) Password
-// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
-#define AT91C_RSTC_URSTS      ((unsigned int) 0x1 <<  0) // (RSTC) User Reset Status
-#define AT91C_RSTC_BODSTS     ((unsigned int) 0x1 <<  1) // (RSTC) Brownout Detection Status
-#define AT91C_RSTC_RSTTYP     ((unsigned int) 0x7 <<  8) // (RSTC) Reset Type
-#define     AT91C_RSTC_RSTTYP_POWERUP              ((unsigned int) 0x0 <<  8) // (RSTC) Power-up Reset. VDDCORE rising.
-#define     AT91C_RSTC_RSTTYP_WAKEUP               ((unsigned int) 0x1 <<  8) // (RSTC) WakeUp Reset. VDDCORE rising.
-#define     AT91C_RSTC_RSTTYP_WATCHDOG             ((unsigned int) 0x2 <<  8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
-#define     AT91C_RSTC_RSTTYP_SOFTWARE             ((unsigned int) 0x3 <<  8) // (RSTC) Software Reset. Processor reset required by the software.
-#define     AT91C_RSTC_RSTTYP_USER                 ((unsigned int) 0x4 <<  8) // (RSTC) User Reset. NRST pin detected low.
-#define     AT91C_RSTC_RSTTYP_BROWNOUT             ((unsigned int) 0x5 <<  8) // (RSTC) Brownout Reset occured.
-#define AT91C_RSTC_NRSTL      ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level
-#define AT91C_RSTC_SRCMP      ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress.
-// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
-#define AT91C_RSTC_URSTEN     ((unsigned int) 0x1 <<  0) // (RSTC) User Reset Enable
-#define AT91C_RSTC_URSTIEN    ((unsigned int) 0x1 <<  4) // (RSTC) User Reset Interrupt Enable
-#define AT91C_RSTC_ERSTL      ((unsigned int) 0xF <<  8) // (RSTC) User Reset Enable
-#define AT91C_RSTC_BODIEN     ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
+/* -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- */
+#define AT91C_RSTC_PROCRST                ( ( unsigned int ) 0x1 << 0 )   /* (RSTC) Processor Reset */
+#define AT91C_RSTC_PERRST                 ( ( unsigned int ) 0x1 << 2 )   /* (RSTC) Peripheral Reset */
+#define AT91C_RSTC_EXTRST                 ( ( unsigned int ) 0x1 << 3 )   /* (RSTC) External Reset */
+#define AT91C_RSTC_KEY                    ( ( unsigned int ) 0xFF << 24 ) /* (RSTC) Password */
+/* -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- */
+#define AT91C_RSTC_URSTS                  ( ( unsigned int ) 0x1 << 0 )   /* (RSTC) User Reset Status */
+#define AT91C_RSTC_BODSTS                 ( ( unsigned int ) 0x1 << 1 )   /* (RSTC) Brownout Detection Status */
+#define AT91C_RSTC_RSTTYP                 ( ( unsigned int ) 0x7 << 8 )   /* (RSTC) Reset Type */
+#define     AT91C_RSTC_RSTTYP_POWERUP     ( ( unsigned int ) 0x0 << 8 )   /* (RSTC) Power-up Reset. VDDCORE rising. */
+#define     AT91C_RSTC_RSTTYP_WAKEUP      ( ( unsigned int ) 0x1 << 8 )   /* (RSTC) WakeUp Reset. VDDCORE rising. */
+#define     AT91C_RSTC_RSTTYP_WATCHDOG    ( ( unsigned int ) 0x2 << 8 )   /* (RSTC) Watchdog Reset. Watchdog overflow occurred. */
+#define     AT91C_RSTC_RSTTYP_SOFTWARE    ( ( unsigned int ) 0x3 << 8 )   /* (RSTC) Software Reset. Processor reset required by the software. */
+#define     AT91C_RSTC_RSTTYP_USER        ( ( unsigned int ) 0x4 << 8 )   /* (RSTC) User Reset. NRST pin detected low. */
+#define     AT91C_RSTC_RSTTYP_BROWNOUT    ( ( unsigned int ) 0x5 << 8 )   /* (RSTC) Brownout Reset occurred. */
+#define AT91C_RSTC_NRSTL                  ( ( unsigned int ) 0x1 << 16 )  /* (RSTC) NRST pin level */
+#define AT91C_RSTC_SRCMP                  ( ( unsigned int ) 0x1 << 17 )  /* (RSTC) Software Reset Command in Progress. */
+/* -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- */
+#define AT91C_RSTC_URSTEN                 ( ( unsigned int ) 0x1 << 0 )   /* (RSTC) User Reset Enable */
+#define AT91C_RSTC_URSTIEN                ( ( unsigned int ) 0x1 << 4 )   /* (RSTC) User Reset Interrupt Enable */
+#define AT91C_RSTC_ERSTL                  ( ( unsigned int ) 0xF << 8 )   /* (RSTC) User Reset Enable */
+#define AT91C_RSTC_BODIEN                 ( ( unsigned int ) 0x1 << 16 )  /* (RSTC) Brownout Detection Interrupt Enable */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_RTTC {
-    AT91_REG     RTTC_RTMR;     // Real-time Mode Register
-    AT91_REG     RTTC_RTAR;     // Real-time Alarm Register
-    AT91_REG     RTTC_RTVR;     // Real-time Value Register
-    AT91_REG     RTTC_RTSR;     // Real-time Status Register
-} AT91S_RTTC, *AT91PS_RTTC;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_RTTC
+{
+    AT91_REG RTTC_RTMR; /* Real-time Mode Register */
+    AT91_REG RTTC_RTAR; /* Real-time Alarm Register */
+    AT91_REG RTTC_RTVR; /* Real-time Value Register */
+    AT91_REG RTTC_RTSR; /* Real-time Status Register */
+} AT91S_RTTC, * AT91PS_RTTC;
 
-// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
-#define AT91C_RTTC_RTPRES     ((unsigned int) 0xFFFF <<  0) // (RTTC) Real-time Timer Prescaler Value
-#define AT91C_RTTC_ALMIEN     ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable
-#define AT91C_RTTC_RTTINCIEN  ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
-#define AT91C_RTTC_RTTRST     ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart
-// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
-#define AT91C_RTTC_ALMV       ((unsigned int) 0x0 <<  0) // (RTTC) Alarm Value
-// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
-#define AT91C_RTTC_CRTV       ((unsigned int) 0x0 <<  0) // (RTTC) Current Real-time Value
-// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
-#define AT91C_RTTC_ALMS       ((unsigned int) 0x1 <<  0) // (RTTC) Real-time Alarm Status
-#define AT91C_RTTC_RTTINC     ((unsigned int) 0x1 <<  1) // (RTTC) Real-time Timer Increment
+/* -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- */
+#define AT91C_RTTC_RTPRES       ( ( unsigned int ) 0xFFFF << 0 ) /* (RTTC) Real-time Timer Prescaler Value */
+#define AT91C_RTTC_ALMIEN       ( ( unsigned int ) 0x1 << 16 )   /* (RTTC) Alarm Interrupt Enable */
+#define AT91C_RTTC_RTTINCIEN    ( ( unsigned int ) 0x1 << 17 )   /* (RTTC) Real Time Timer Increment Interrupt Enable */
+#define AT91C_RTTC_RTTRST       ( ( unsigned int ) 0x1 << 18 )   /* (RTTC) Real Time Timer Restart */
+/* -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- */
+#define AT91C_RTTC_ALMV         ( ( unsigned int ) 0x0 << 0 )    /* (RTTC) Alarm Value */
+/* -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- */
+#define AT91C_RTTC_CRTV         ( ( unsigned int ) 0x0 << 0 )    /* (RTTC) Current Real-time Value */
+/* -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- */
+#define AT91C_RTTC_ALMS         ( ( unsigned int ) 0x1 << 0 )    /* (RTTC) Real-time Alarm Status */
+#define AT91C_RTTC_RTTINC       ( ( unsigned int ) 0x1 << 1 )    /* (RTTC) Real-time Timer Increment */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_PITC {
-    AT91_REG     PITC_PIMR;     // Period Interval Mode Register
-    AT91_REG     PITC_PISR;     // Period Interval Status Register
-    AT91_REG     PITC_PIVR;     // Period Interval Value Register
-    AT91_REG     PITC_PIIR;     // Period Interval Image Register
-} AT91S_PITC, *AT91PS_PITC;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_PITC
+{
+    AT91_REG PITC_PIMR; /* Period Interval Mode Register */
+    AT91_REG PITC_PISR; /* Period Interval Status Register */
+    AT91_REG PITC_PIVR; /* Period Interval Value Register */
+    AT91_REG PITC_PIIR; /* Period Interval Image Register */
+} AT91S_PITC, * AT91PS_PITC;
 
-// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
-#define AT91C_PITC_PIV        ((unsigned int) 0xFFFFF <<  0) // (PITC) Periodic Interval Value
-#define AT91C_PITC_PITEN      ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled
-#define AT91C_PITC_PITIEN     ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
-// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
-#define AT91C_PITC_PITS       ((unsigned int) 0x1 <<  0) // (PITC) Periodic Interval Timer Status
-// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
-#define AT91C_PITC_CPIV       ((unsigned int) 0xFFFFF <<  0) // (PITC) Current Periodic Interval Value
-#define AT91C_PITC_PICNT      ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter
-// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
+/* -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- */
+#define AT91C_PITC_PIV       ( ( unsigned int ) 0xFFFFF << 0 ) /* (PITC) Periodic Interval Value */
+#define AT91C_PITC_PITEN     ( ( unsigned int ) 0x1 << 24 )    /* (PITC) Periodic Interval Timer Enabled */
+#define AT91C_PITC_PITIEN    ( ( unsigned int ) 0x1 << 25 )    /* (PITC) Periodic Interval Timer Interrupt Enable */
+/* -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- */
+#define AT91C_PITC_PITS      ( ( unsigned int ) 0x1 << 0 )     /* (PITC) Periodic Interval Timer Status */
+/* -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- */
+#define AT91C_PITC_CPIV      ( ( unsigned int ) 0xFFFFF << 0 ) /* (PITC) Current Periodic Interval Value */
+#define AT91C_PITC_PICNT     ( ( unsigned int ) 0xFFF << 20 )  /* (PITC) Periodic Interval Counter */
+/* -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_WDTC {
-    AT91_REG     WDTC_WDCR;     // Watchdog Control Register
-    AT91_REG     WDTC_WDMR;     // Watchdog Mode Register
-    AT91_REG     WDTC_WDSR;     // Watchdog Status Register
-} AT91S_WDTC, *AT91PS_WDTC;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_WDTC
+{
+    AT91_REG WDTC_WDCR; /* Watchdog Control Register */
+    AT91_REG WDTC_WDMR; /* Watchdog Mode Register */
+    AT91_REG WDTC_WDSR; /* Watchdog Status Register */
+} AT91S_WDTC, * AT91PS_WDTC;
 
-// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
-#define AT91C_WDTC_WDRSTT     ((unsigned int) 0x1 <<  0) // (WDTC) Watchdog Restart
-#define AT91C_WDTC_KEY        ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password
-// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
-#define AT91C_WDTC_WDV        ((unsigned int) 0xFFF <<  0) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDFIEN     ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
-#define AT91C_WDTC_WDRSTEN    ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable
-#define AT91C_WDTC_WDRPROC    ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDDIS      ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable
-#define AT91C_WDTC_WDD        ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value
-#define AT91C_WDTC_WDDBGHLT   ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt
-#define AT91C_WDTC_WDIDLEHLT  ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt
-// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
-#define AT91C_WDTC_WDUNF      ((unsigned int) 0x1 <<  0) // (WDTC) Watchdog Underflow
-#define AT91C_WDTC_WDERR      ((unsigned int) 0x1 <<  1) // (WDTC) Watchdog Error
+/* -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- */
+#define AT91C_WDTC_WDRSTT       ( ( unsigned int ) 0x1 << 0 )    /* (WDTC) Watchdog Restart */
+#define AT91C_WDTC_KEY          ( ( unsigned int ) 0xFF << 24 )  /* (WDTC) Watchdog KEY Password */
+/* -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- */
+#define AT91C_WDTC_WDV          ( ( unsigned int ) 0xFFF << 0 )  /* (WDTC) Watchdog Timer Restart */
+#define AT91C_WDTC_WDFIEN       ( ( unsigned int ) 0x1 << 12 )   /* (WDTC) Watchdog Fault Interrupt Enable */
+#define AT91C_WDTC_WDRSTEN      ( ( unsigned int ) 0x1 << 13 )   /* (WDTC) Watchdog Reset Enable */
+#define AT91C_WDTC_WDRPROC      ( ( unsigned int ) 0x1 << 14 )   /* (WDTC) Watchdog Timer Restart */
+#define AT91C_WDTC_WDDIS        ( ( unsigned int ) 0x1 << 15 )   /* (WDTC) Watchdog Disable */
+#define AT91C_WDTC_WDD          ( ( unsigned int ) 0xFFF << 16 ) /* (WDTC) Watchdog Delta Value */
+#define AT91C_WDTC_WDDBGHLT     ( ( unsigned int ) 0x1 << 28 )   /* (WDTC) Watchdog Debug Halt */
+#define AT91C_WDTC_WDIDLEHLT    ( ( unsigned int ) 0x1 << 29 )   /* (WDTC) Watchdog Idle Halt */
+/* -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- */
+#define AT91C_WDTC_WDUNF        ( ( unsigned int ) 0x1 << 0 )    /* (WDTC) Watchdog Underflow */
+#define AT91C_WDTC_WDERR        ( ( unsigned int ) 0x1 << 1 )    /* (WDTC) Watchdog Error */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Voltage Regulator Mode Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_VREG {
-    AT91_REG     VREG_MR;   // Voltage Regulator Mode Register
-} AT91S_VREG, *AT91PS_VREG;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Voltage Regulator Mode Controller Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_VREG
+{
+    AT91_REG VREG_MR; /* Voltage Regulator Mode Register */
+} AT91S_VREG, * AT91PS_VREG;
 
-// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register --------
-#define AT91C_VREG_PSTDBY     ((unsigned int) 0x1 <<  0) // (VREG) Voltage Regulator Power Standby Mode
+/* -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- */
+#define AT91C_VREG_PSTDBY    ( ( unsigned int ) 0x1 << 0 ) /* (VREG) Voltage Regulator Power Standby Mode */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Memory Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_MC {
-    AT91_REG     MC_RCR;    // MC Remap Control Register
-    AT91_REG     MC_ASR;    // MC Abort Status Register
-    AT91_REG     MC_AASR;   // MC Abort Address Status Register
-    AT91_REG     Reserved0[21];     //
-    AT91_REG     MC_FMR;    // MC Flash Mode Register
-    AT91_REG     MC_FCR;    // MC Flash Command Register
-    AT91_REG     MC_FSR;    // MC Flash Status Register
-} AT91S_MC, *AT91PS_MC;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Memory Controller Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_MC
+{
+    AT91_REG MC_RCR;          /* MC Remap Control Register */
+    AT91_REG MC_ASR;          /* MC Abort Status Register */
+    AT91_REG MC_AASR;         /* MC Abort Address Status Register */
+    AT91_REG Reserved0[ 21 ]; /* */
+    AT91_REG MC_FMR;          /* MC Flash Mode Register */
+    AT91_REG MC_FCR;          /* MC Flash Command Register */
+    AT91_REG MC_FSR;          /* MC Flash Status Register */
+} AT91S_MC, * AT91PS_MC;
 
-// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
-#define AT91C_MC_RCB          ((unsigned int) 0x1 <<  0) // (MC) Remap Command Bit
-// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
-#define AT91C_MC_UNDADD       ((unsigned int) 0x1 <<  0) // (MC) Undefined Addess Abort Status
-#define AT91C_MC_MISADD       ((unsigned int) 0x1 <<  1) // (MC) Misaligned Addess Abort Status
-#define AT91C_MC_ABTSZ        ((unsigned int) 0x3 <<  8) // (MC) Abort Size Status
-#define     AT91C_MC_ABTSZ_BYTE                 ((unsigned int) 0x0 <<  8) // (MC) Byte
-#define     AT91C_MC_ABTSZ_HWORD                ((unsigned int) 0x1 <<  8) // (MC) Half-word
-#define     AT91C_MC_ABTSZ_WORD                 ((unsigned int) 0x2 <<  8) // (MC) Word
-#define AT91C_MC_ABTTYP       ((unsigned int) 0x3 << 10) // (MC) Abort Type Status
-#define     AT91C_MC_ABTTYP_DATAR                ((unsigned int) 0x0 << 10) // (MC) Data Read
-#define     AT91C_MC_ABTTYP_DATAW                ((unsigned int) 0x1 << 10) // (MC) Data Write
-#define     AT91C_MC_ABTTYP_FETCH                ((unsigned int) 0x2 << 10) // (MC) Code Fetch
-#define AT91C_MC_MST0         ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source
-#define AT91C_MC_MST1         ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source
-#define AT91C_MC_SVMST0       ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source
-#define AT91C_MC_SVMST1       ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source
-// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
-#define AT91C_MC_FRDY         ((unsigned int) 0x1 <<  0) // (MC) Flash Ready
-#define AT91C_MC_LOCKE        ((unsigned int) 0x1 <<  2) // (MC) Lock Error
-#define AT91C_MC_PROGE        ((unsigned int) 0x1 <<  3) // (MC) Programming Error
-#define AT91C_MC_NEBP         ((unsigned int) 0x1 <<  7) // (MC) No Erase Before Programming
-#define AT91C_MC_FWS          ((unsigned int) 0x3 <<  8) // (MC) Flash Wait State
-#define     AT91C_MC_FWS_0FWS                 ((unsigned int) 0x0 <<  8) // (MC) 1 cycle for Read, 2 for Write operations
-#define     AT91C_MC_FWS_1FWS                 ((unsigned int) 0x1 <<  8) // (MC) 2 cycles for Read, 3 for Write operations
-#define     AT91C_MC_FWS_2FWS                 ((unsigned int) 0x2 <<  8) // (MC) 3 cycles for Read, 4 for Write operations
-#define     AT91C_MC_FWS_3FWS                 ((unsigned int) 0x3 <<  8) // (MC) 4 cycles for Read, 4 for Write operations
-#define AT91C_MC_FMCN         ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number
-// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
-#define AT91C_MC_FCMD         ((unsigned int) 0xF <<  0) // (MC) Flash Command
-#define     AT91C_MC_FCMD_START_PROG           ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN.
-#define     AT91C_MC_FCMD_LOCK                 ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define     AT91C_MC_FCMD_PROG_AND_LOCK        ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
-#define     AT91C_MC_FCMD_UNLOCK               ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define     AT91C_MC_FCMD_ERASE_ALL            ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
-#define     AT91C_MC_FCMD_SET_GP_NVM           ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits.
-#define     AT91C_MC_FCMD_CLR_GP_NVM           ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits.
-#define     AT91C_MC_FCMD_SET_SECURITY         ((unsigned int) 0xF) // (MC) Set Security Bit.
-#define AT91C_MC_PAGEN        ((unsigned int) 0x3FF <<  8) // (MC) Page Number
-#define AT91C_MC_KEY          ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key
-// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register --------
-#define AT91C_MC_SECURITY     ((unsigned int) 0x1 <<  4) // (MC) Security Bit Status
-#define AT91C_MC_GPNVM0       ((unsigned int) 0x1 <<  8) // (MC) Sector 0 Lock Status
-#define AT91C_MC_GPNVM1       ((unsigned int) 0x1 <<  9) // (MC) Sector 1 Lock Status
-#define AT91C_MC_GPNVM2       ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status
-#define AT91C_MC_GPNVM3       ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status
-#define AT91C_MC_GPNVM4       ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status
-#define AT91C_MC_GPNVM5       ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status
-#define AT91C_MC_GPNVM6       ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status
-#define AT91C_MC_GPNVM7       ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS0       ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status
-#define AT91C_MC_LOCKS1       ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status
-#define AT91C_MC_LOCKS2       ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status
-#define AT91C_MC_LOCKS3       ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status
-#define AT91C_MC_LOCKS4       ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status
-#define AT91C_MC_LOCKS5       ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status
-#define AT91C_MC_LOCKS6       ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status
-#define AT91C_MC_LOCKS7       ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS8       ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status
-#define AT91C_MC_LOCKS9       ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status
-#define AT91C_MC_LOCKS10      ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status
-#define AT91C_MC_LOCKS11      ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status
-#define AT91C_MC_LOCKS12      ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status
-#define AT91C_MC_LOCKS13      ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status
-#define AT91C_MC_LOCKS14      ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status
-#define AT91C_MC_LOCKS15      ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status
+/* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */
+#define AT91C_MC_RCB                       ( ( unsigned int ) 0x1 << 0 )   /* (MC) Remap Command Bit */
+/* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */
+#define AT91C_MC_UNDADD                    ( ( unsigned int ) 0x1 << 0 )   /* (MC) Undefined Addess Abort Status */
+#define AT91C_MC_MISADD                    ( ( unsigned int ) 0x1 << 1 )   /* (MC) Misaligned Addess Abort Status */
+#define AT91C_MC_ABTSZ                     ( ( unsigned int ) 0x3 << 8 )   /* (MC) Abort Size Status */
+#define     AT91C_MC_ABTSZ_BYTE            ( ( unsigned int ) 0x0 << 8 )   /* (MC) Byte */
+#define     AT91C_MC_ABTSZ_HWORD           ( ( unsigned int ) 0x1 << 8 )   /* (MC) Half-word */
+#define     AT91C_MC_ABTSZ_WORD            ( ( unsigned int ) 0x2 << 8 )   /* (MC) Word */
+#define AT91C_MC_ABTTYP                    ( ( unsigned int ) 0x3 << 10 )  /* (MC) Abort Type Status */
+#define     AT91C_MC_ABTTYP_DATAR          ( ( unsigned int ) 0x0 << 10 )  /* (MC) Data Read */
+#define     AT91C_MC_ABTTYP_DATAW          ( ( unsigned int ) 0x1 << 10 )  /* (MC) Data Write */
+#define     AT91C_MC_ABTTYP_FETCH          ( ( unsigned int ) 0x2 << 10 )  /* (MC) Code Fetch */
+#define AT91C_MC_MST0                      ( ( unsigned int ) 0x1 << 16 )  /* (MC) Master 0 Abort Source */
+#define AT91C_MC_MST1                      ( ( unsigned int ) 0x1 << 17 )  /* (MC) Master 1 Abort Source */
+#define AT91C_MC_SVMST0                    ( ( unsigned int ) 0x1 << 24 )  /* (MC) Saved Master 0 Abort Source */
+#define AT91C_MC_SVMST1                    ( ( unsigned int ) 0x1 << 25 )  /* (MC) Saved Master 1 Abort Source */
+/* -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- */
+#define AT91C_MC_FRDY                      ( ( unsigned int ) 0x1 << 0 )   /* (MC) Flash Ready */
+#define AT91C_MC_LOCKE                     ( ( unsigned int ) 0x1 << 2 )   /* (MC) Lock Error */
+#define AT91C_MC_PROGE                     ( ( unsigned int ) 0x1 << 3 )   /* (MC) Programming Error */
+#define AT91C_MC_NEBP                      ( ( unsigned int ) 0x1 << 7 )   /* (MC) No Erase Before Programming */
+#define AT91C_MC_FWS                       ( ( unsigned int ) 0x3 << 8 )   /* (MC) Flash Wait State */
+#define     AT91C_MC_FWS_0FWS              ( ( unsigned int ) 0x0 << 8 )   /* (MC) 1 cycle for Read, 2 for Write operations */
+#define     AT91C_MC_FWS_1FWS              ( ( unsigned int ) 0x1 << 8 )   /* (MC) 2 cycles for Read, 3 for Write operations */
+#define     AT91C_MC_FWS_2FWS              ( ( unsigned int ) 0x2 << 8 )   /* (MC) 3 cycles for Read, 4 for Write operations */
+#define     AT91C_MC_FWS_3FWS              ( ( unsigned int ) 0x3 << 8 )   /* (MC) 4 cycles for Read, 4 for Write operations */
+#define AT91C_MC_FMCN                      ( ( unsigned int ) 0xFF << 16 ) /* (MC) Flash Microsecond Cycle Number */
+/* -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- */
+#define AT91C_MC_FCMD                      ( ( unsigned int ) 0xF << 0 )   /* (MC) Flash Command */
+#define     AT91C_MC_FCMD_START_PROG       ( ( unsigned int ) 0x1 )        /* (MC) Starts the programming of th epage specified by PAGEN. */
+#define     AT91C_MC_FCMD_LOCK             ( ( unsigned int ) 0x2 )        /* (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */
+#define     AT91C_MC_FCMD_PROG_AND_LOCK    ( ( unsigned int ) 0x3 )        /* (MC) The lock sequence automatically happens after the programming sequence is completed. */
+#define     AT91C_MC_FCMD_UNLOCK           ( ( unsigned int ) 0x4 )        /* (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */
+#define     AT91C_MC_FCMD_ERASE_ALL        ( ( unsigned int ) 0x8 )        /* (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. */
+#define     AT91C_MC_FCMD_SET_GP_NVM       ( ( unsigned int ) 0xB )        /* (MC) Set General Purpose NVM bits. */
+#define     AT91C_MC_FCMD_CLR_GP_NVM       ( ( unsigned int ) 0xD )        /* (MC) Clear General Purpose NVM bits. */
+#define     AT91C_MC_FCMD_SET_SECURITY     ( ( unsigned int ) 0xF )        /* (MC) Set Security Bit. */
+#define AT91C_MC_PAGEN                     ( ( unsigned int ) 0x3FF << 8 ) /* (MC) Page Number */
+#define AT91C_MC_KEY                       ( ( unsigned int ) 0xFF << 24 ) /* (MC) Writing Protect Key */
+/* -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- */
+#define AT91C_MC_SECURITY                  ( ( unsigned int ) 0x1 << 4 )   /* (MC) Security Bit Status */
+#define AT91C_MC_GPNVM0                    ( ( unsigned int ) 0x1 << 8 )   /* (MC) Sector 0 Lock Status */
+#define AT91C_MC_GPNVM1                    ( ( unsigned int ) 0x1 << 9 )   /* (MC) Sector 1 Lock Status */
+#define AT91C_MC_GPNVM2                    ( ( unsigned int ) 0x1 << 10 )  /* (MC) Sector 2 Lock Status */
+#define AT91C_MC_GPNVM3                    ( ( unsigned int ) 0x1 << 11 )  /* (MC) Sector 3 Lock Status */
+#define AT91C_MC_GPNVM4                    ( ( unsigned int ) 0x1 << 12 )  /* (MC) Sector 4 Lock Status */
+#define AT91C_MC_GPNVM5                    ( ( unsigned int ) 0x1 << 13 )  /* (MC) Sector 5 Lock Status */
+#define AT91C_MC_GPNVM6                    ( ( unsigned int ) 0x1 << 14 )  /* (MC) Sector 6 Lock Status */
+#define AT91C_MC_GPNVM7                    ( ( unsigned int ) 0x1 << 15 )  /* (MC) Sector 7 Lock Status */
+#define AT91C_MC_LOCKS0                    ( ( unsigned int ) 0x1 << 16 )  /* (MC) Sector 0 Lock Status */
+#define AT91C_MC_LOCKS1                    ( ( unsigned int ) 0x1 << 17 )  /* (MC) Sector 1 Lock Status */
+#define AT91C_MC_LOCKS2                    ( ( unsigned int ) 0x1 << 18 )  /* (MC) Sector 2 Lock Status */
+#define AT91C_MC_LOCKS3                    ( ( unsigned int ) 0x1 << 19 )  /* (MC) Sector 3 Lock Status */
+#define AT91C_MC_LOCKS4                    ( ( unsigned int ) 0x1 << 20 )  /* (MC) Sector 4 Lock Status */
+#define AT91C_MC_LOCKS5                    ( ( unsigned int ) 0x1 << 21 )  /* (MC) Sector 5 Lock Status */
+#define AT91C_MC_LOCKS6                    ( ( unsigned int ) 0x1 << 22 )  /* (MC) Sector 6 Lock Status */
+#define AT91C_MC_LOCKS7                    ( ( unsigned int ) 0x1 << 23 )  /* (MC) Sector 7 Lock Status */
+#define AT91C_MC_LOCKS8                    ( ( unsigned int ) 0x1 << 24 )  /* (MC) Sector 8 Lock Status */
+#define AT91C_MC_LOCKS9                    ( ( unsigned int ) 0x1 << 25 )  /* (MC) Sector 9 Lock Status */
+#define AT91C_MC_LOCKS10                   ( ( unsigned int ) 0x1 << 26 )  /* (MC) Sector 10 Lock Status */
+#define AT91C_MC_LOCKS11                   ( ( unsigned int ) 0x1 << 27 )  /* (MC) Sector 11 Lock Status */
+#define AT91C_MC_LOCKS12                   ( ( unsigned int ) 0x1 << 28 )  /* (MC) Sector 12 Lock Status */
+#define AT91C_MC_LOCKS13                   ( ( unsigned int ) 0x1 << 29 )  /* (MC) Sector 13 Lock Status */
+#define AT91C_MC_LOCKS14                   ( ( unsigned int ) 0x1 << 30 )  /* (MC) Sector 14 Lock Status */
+#define AT91C_MC_LOCKS15                   ( ( unsigned int ) 0x1 << 31 )  /* (MC) Sector 15 Lock Status */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
-// *****************************************************************************
-typedef struct _AT91S_SPI {
-    AT91_REG     SPI_CR;    // Control Register
-    AT91_REG     SPI_MR;    // Mode Register
-    AT91_REG     SPI_RDR;   // Receive Data Register
-    AT91_REG     SPI_TDR;   // Transmit Data Register
-    AT91_REG     SPI_SR;    // Status Register
-    AT91_REG     SPI_IER;   // Interrupt Enable Register
-    AT91_REG     SPI_IDR;   // Interrupt Disable Register
-    AT91_REG     SPI_IMR;   // Interrupt Mask Register
-    AT91_REG     Reserved0[4];  //
-    AT91_REG     SPI_CSR[4];    // Chip Select Register
-    AT91_REG     Reserved1[48];     //
-    AT91_REG     SPI_RPR;   // Receive Pointer Register
-    AT91_REG     SPI_RCR;   // Receive Counter Register
-    AT91_REG     SPI_TPR;   // Transmit Pointer Register
-    AT91_REG     SPI_TCR;   // Transmit Counter Register
-    AT91_REG     SPI_RNPR;  // Receive Next Pointer Register
-    AT91_REG     SPI_RNCR;  // Receive Next Counter Register
-    AT91_REG     SPI_TNPR;  // Transmit Next Pointer Register
-    AT91_REG     SPI_TNCR;  // Transmit Next Counter Register
-    AT91_REG     SPI_PTCR;  // PDC Transfer Control Register
-    AT91_REG     SPI_PTSR;  // PDC Transfer Status Register
-} AT91S_SPI, *AT91PS_SPI;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Serial Parallel Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_SPI
+{
+    AT91_REG SPI_CR;          /* Control Register */
+    AT91_REG SPI_MR;          /* Mode Register */
+    AT91_REG SPI_RDR;         /* Receive Data Register */
+    AT91_REG SPI_TDR;         /* Transmit Data Register */
+    AT91_REG SPI_SR;          /* Status Register */
+    AT91_REG SPI_IER;         /* Interrupt Enable Register */
+    AT91_REG SPI_IDR;         /* Interrupt Disable Register */
+    AT91_REG SPI_IMR;         /* Interrupt Mask Register */
+    AT91_REG Reserved0[ 4 ];  /* */
+    AT91_REG SPI_CSR[ 4 ];    /* Chip Select Register */
+    AT91_REG Reserved1[ 48 ]; /* */
+    AT91_REG SPI_RPR;         /* Receive Pointer Register */
+    AT91_REG SPI_RCR;         /* Receive Counter Register */
+    AT91_REG SPI_TPR;         /* Transmit Pointer Register */
+    AT91_REG SPI_TCR;         /* Transmit Counter Register */
+    AT91_REG SPI_RNPR;        /* Receive Next Pointer Register */
+    AT91_REG SPI_RNCR;        /* Receive Next Counter Register */
+    AT91_REG SPI_TNPR;        /* Transmit Next Pointer Register */
+    AT91_REG SPI_TNCR;        /* Transmit Next Counter Register */
+    AT91_REG SPI_PTCR;        /* PDC Transfer Control Register */
+    AT91_REG SPI_PTSR;        /* PDC Transfer Status Register */
+} AT91S_SPI, * AT91PS_SPI;
 
-// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
-#define AT91C_SPI_SPIEN       ((unsigned int) 0x1 <<  0) // (SPI) SPI Enable
-#define AT91C_SPI_SPIDIS      ((unsigned int) 0x1 <<  1) // (SPI) SPI Disable
-#define AT91C_SPI_SWRST       ((unsigned int) 0x1 <<  7) // (SPI) SPI Software reset
-#define AT91C_SPI_LASTXFER    ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer
-// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
-#define AT91C_SPI_MSTR        ((unsigned int) 0x1 <<  0) // (SPI) Master/Slave Mode
-#define AT91C_SPI_PS          ((unsigned int) 0x1 <<  1) // (SPI) Peripheral Select
-#define     AT91C_SPI_PS_FIXED                ((unsigned int) 0x0 <<  1) // (SPI) Fixed Peripheral Select
-#define     AT91C_SPI_PS_VARIABLE             ((unsigned int) 0x1 <<  1) // (SPI) Variable Peripheral Select
-#define AT91C_SPI_PCSDEC      ((unsigned int) 0x1 <<  2) // (SPI) Chip Select Decode
-#define AT91C_SPI_FDIV        ((unsigned int) 0x1 <<  3) // (SPI) Clock Selection
-#define AT91C_SPI_MODFDIS     ((unsigned int) 0x1 <<  4) // (SPI) Mode Fault Detection
-#define AT91C_SPI_LLB         ((unsigned int) 0x1 <<  7) // (SPI) Clock Selection
-#define AT91C_SPI_PCS         ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select
-#define AT91C_SPI_DLYBCS      ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects
-// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
-#define AT91C_SPI_RD          ((unsigned int) 0xFFFF <<  0) // (SPI) Receive Data
-#define AT91C_SPI_RPCS        ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
-#define AT91C_SPI_TD          ((unsigned int) 0xFFFF <<  0) // (SPI) Transmit Data
-#define AT91C_SPI_TPCS        ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
-#define AT91C_SPI_RDRF        ((unsigned int) 0x1 <<  0) // (SPI) Receive Data Register Full
-#define AT91C_SPI_TDRE        ((unsigned int) 0x1 <<  1) // (SPI) Transmit Data Register Empty
-#define AT91C_SPI_MODF        ((unsigned int) 0x1 <<  2) // (SPI) Mode Fault Error
-#define AT91C_SPI_OVRES       ((unsigned int) 0x1 <<  3) // (SPI) Overrun Error Status
-#define AT91C_SPI_ENDRX       ((unsigned int) 0x1 <<  4) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_ENDTX       ((unsigned int) 0x1 <<  5) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_RXBUFF      ((unsigned int) 0x1 <<  6) // (SPI) RXBUFF Interrupt
-#define AT91C_SPI_TXBUFE      ((unsigned int) 0x1 <<  7) // (SPI) TXBUFE Interrupt
-#define AT91C_SPI_NSSR        ((unsigned int) 0x1 <<  8) // (SPI) NSSR Interrupt
-#define AT91C_SPI_TXEMPTY     ((unsigned int) 0x1 <<  9) // (SPI) TXEMPTY Interrupt
-#define AT91C_SPI_SPIENS      ((unsigned int) 0x1 << 16) // (SPI) Enable Status
-// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
-// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
-// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
-// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
-#define AT91C_SPI_CPOL        ((unsigned int) 0x1 <<  0) // (SPI) Clock Polarity
-#define AT91C_SPI_NCPHA       ((unsigned int) 0x1 <<  1) // (SPI) Clock Phase
-#define AT91C_SPI_CSAAT       ((unsigned int) 0x1 <<  3) // (SPI) Chip Select Active After Transfer
-#define AT91C_SPI_BITS        ((unsigned int) 0xF <<  4) // (SPI) Bits Per Transfer
-#define     AT91C_SPI_BITS_8                    ((unsigned int) 0x0 <<  4) // (SPI) 8 Bits Per transfer
-#define     AT91C_SPI_BITS_9                    ((unsigned int) 0x1 <<  4) // (SPI) 9 Bits Per transfer
-#define     AT91C_SPI_BITS_10                   ((unsigned int) 0x2 <<  4) // (SPI) 10 Bits Per transfer
-#define     AT91C_SPI_BITS_11                   ((unsigned int) 0x3 <<  4) // (SPI) 11 Bits Per transfer
-#define     AT91C_SPI_BITS_12                   ((unsigned int) 0x4 <<  4) // (SPI) 12 Bits Per transfer
-#define     AT91C_SPI_BITS_13                   ((unsigned int) 0x5 <<  4) // (SPI) 13 Bits Per transfer
-#define     AT91C_SPI_BITS_14                   ((unsigned int) 0x6 <<  4) // (SPI) 14 Bits Per transfer
-#define     AT91C_SPI_BITS_15                   ((unsigned int) 0x7 <<  4) // (SPI) 15 Bits Per transfer
-#define     AT91C_SPI_BITS_16                   ((unsigned int) 0x8 <<  4) // (SPI) 16 Bits Per transfer
-#define AT91C_SPI_SCBR        ((unsigned int) 0xFF <<  8) // (SPI) Serial Clock Baud Rate
-#define AT91C_SPI_DLYBS       ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK
-#define AT91C_SPI_DLYBCT      ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers
+/* -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */
+#define AT91C_SPI_SPIEN              ( ( unsigned int ) 0x1 << 0 )    /* (SPI) SPI Enable */
+#define AT91C_SPI_SPIDIS             ( ( unsigned int ) 0x1 << 1 )    /* (SPI) SPI Disable */
+#define AT91C_SPI_SWRST              ( ( unsigned int ) 0x1 << 7 )    /* (SPI) SPI Software reset */
+#define AT91C_SPI_LASTXFER           ( ( unsigned int ) 0x1 << 24 )   /* (SPI) SPI Last Transfer */
+/* -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- */
+#define AT91C_SPI_MSTR               ( ( unsigned int ) 0x1 << 0 )    /* (SPI) Master/Slave Mode */
+#define AT91C_SPI_PS                 ( ( unsigned int ) 0x1 << 1 )    /* (SPI) Peripheral Select */
+#define     AT91C_SPI_PS_FIXED       ( ( unsigned int ) 0x0 << 1 )    /* (SPI) Fixed Peripheral Select */
+#define     AT91C_SPI_PS_VARIABLE    ( ( unsigned int ) 0x1 << 1 )    /* (SPI) Variable Peripheral Select */
+#define AT91C_SPI_PCSDEC             ( ( unsigned int ) 0x1 << 2 )    /* (SPI) Chip Select Decode */
+#define AT91C_SPI_FDIV               ( ( unsigned int ) 0x1 << 3 )    /* (SPI) Clock Selection */
+#define AT91C_SPI_MODFDIS            ( ( unsigned int ) 0x1 << 4 )    /* (SPI) Mode Fault Detection */
+#define AT91C_SPI_LLB                ( ( unsigned int ) 0x1 << 7 )    /* (SPI) Clock Selection */
+#define AT91C_SPI_PCS                ( ( unsigned int ) 0xF << 16 )   /* (SPI) Peripheral Chip Select */
+#define AT91C_SPI_DLYBCS             ( ( unsigned int ) 0xFF << 24 )  /* (SPI) Delay Between Chip Selects */
+/* -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- */
+#define AT91C_SPI_RD                 ( ( unsigned int ) 0xFFFF << 0 ) /* (SPI) Receive Data */
+#define AT91C_SPI_RPCS               ( ( unsigned int ) 0xF << 16 )   /* (SPI) Peripheral Chip Select Status */
+/* -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- */
+#define AT91C_SPI_TD                 ( ( unsigned int ) 0xFFFF << 0 ) /* (SPI) Transmit Data */
+#define AT91C_SPI_TPCS               ( ( unsigned int ) 0xF << 16 )   /* (SPI) Peripheral Chip Select Status */
+/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
+#define AT91C_SPI_RDRF               ( ( unsigned int ) 0x1 << 0 )    /* (SPI) Receive Data Register Full */
+#define AT91C_SPI_TDRE               ( ( unsigned int ) 0x1 << 1 )    /* (SPI) Transmit Data Register Empty */
+#define AT91C_SPI_MODF               ( ( unsigned int ) 0x1 << 2 )    /* (SPI) Mode Fault Error */
+#define AT91C_SPI_OVRES              ( ( unsigned int ) 0x1 << 3 )    /* (SPI) Overrun Error Status */
+#define AT91C_SPI_ENDRX              ( ( unsigned int ) 0x1 << 4 )    /* (SPI) End of Receiver Transfer */
+#define AT91C_SPI_ENDTX              ( ( unsigned int ) 0x1 << 5 )    /* (SPI) End of Receiver Transfer */
+#define AT91C_SPI_RXBUFF             ( ( unsigned int ) 0x1 << 6 )    /* (SPI) RXBUFF Interrupt */
+#define AT91C_SPI_TXBUFE             ( ( unsigned int ) 0x1 << 7 )    /* (SPI) TXBUFE Interrupt */
+#define AT91C_SPI_NSSR               ( ( unsigned int ) 0x1 << 8 )    /* (SPI) NSSR Interrupt */
+#define AT91C_SPI_TXEMPTY            ( ( unsigned int ) 0x1 << 9 )    /* (SPI) TXEMPTY Interrupt */
+#define AT91C_SPI_SPIENS             ( ( unsigned int ) 0x1 << 16 )   /* (SPI) Enable Status */
+/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
+/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
+/* -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */
+/* -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */
+#define AT91C_SPI_CPOL           ( ( unsigned int ) 0x1 << 0 )   /* (SPI) Clock Polarity */
+#define AT91C_SPI_NCPHA          ( ( unsigned int ) 0x1 << 1 )   /* (SPI) Clock Phase */
+#define AT91C_SPI_CSAAT          ( ( unsigned int ) 0x1 << 3 )   /* (SPI) Chip Select Active After Transfer */
+#define AT91C_SPI_BITS           ( ( unsigned int ) 0xF << 4 )   /* (SPI) Bits Per Transfer */
+#define     AT91C_SPI_BITS_8     ( ( unsigned int ) 0x0 << 4 )   /* (SPI) 8 Bits Per transfer */
+#define     AT91C_SPI_BITS_9     ( ( unsigned int ) 0x1 << 4 )   /* (SPI) 9 Bits Per transfer */
+#define     AT91C_SPI_BITS_10    ( ( unsigned int ) 0x2 << 4 )   /* (SPI) 10 Bits Per transfer */
+#define     AT91C_SPI_BITS_11    ( ( unsigned int ) 0x3 << 4 )   /* (SPI) 11 Bits Per transfer */
+#define     AT91C_SPI_BITS_12    ( ( unsigned int ) 0x4 << 4 )   /* (SPI) 12 Bits Per transfer */
+#define     AT91C_SPI_BITS_13    ( ( unsigned int ) 0x5 << 4 )   /* (SPI) 13 Bits Per transfer */
+#define     AT91C_SPI_BITS_14    ( ( unsigned int ) 0x6 << 4 )   /* (SPI) 14 Bits Per transfer */
+#define     AT91C_SPI_BITS_15    ( ( unsigned int ) 0x7 << 4 )   /* (SPI) 15 Bits Per transfer */
+#define     AT91C_SPI_BITS_16    ( ( unsigned int ) 0x8 << 4 )   /* (SPI) 16 Bits Per transfer */
+#define AT91C_SPI_SCBR           ( ( unsigned int ) 0xFF << 8 )  /* (SPI) Serial Clock Baud Rate */
+#define AT91C_SPI_DLYBS          ( ( unsigned int ) 0xFF << 16 ) /* (SPI) Delay Before SPCK */
+#define AT91C_SPI_DLYBCT         ( ( unsigned int ) 0xFF << 24 ) /* (SPI) Delay Between Consecutive Transfers */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Usart
-// *****************************************************************************
-typedef struct _AT91S_USART {
-    AT91_REG     US_CR;     // Control Register
-    AT91_REG     US_MR;     // Mode Register
-    AT91_REG     US_IER;    // Interrupt Enable Register
-    AT91_REG     US_IDR;    // Interrupt Disable Register
-    AT91_REG     US_IMR;    // Interrupt Mask Register
-    AT91_REG     US_CSR;    // Channel Status Register
-    AT91_REG     US_RHR;    // Receiver Holding Register
-    AT91_REG     US_THR;    // Transmitter Holding Register
-    AT91_REG     US_BRGR;   // Baud Rate Generator Register
-    AT91_REG     US_RTOR;   // Receiver Time-out Register
-    AT91_REG     US_TTGR;   // Transmitter Time-guard Register
-    AT91_REG     Reserved0[5];  //
-    AT91_REG     US_FIDI;   // FI_DI_Ratio Register
-    AT91_REG     US_NER;    // Nb Errors Register
-    AT91_REG     Reserved1[1];  //
-    AT91_REG     US_IF;     // IRDA_FILTER Register
-    AT91_REG     Reserved2[44];     //
-    AT91_REG     US_RPR;    // Receive Pointer Register
-    AT91_REG     US_RCR;    // Receive Counter Register
-    AT91_REG     US_TPR;    // Transmit Pointer Register
-    AT91_REG     US_TCR;    // Transmit Counter Register
-    AT91_REG     US_RNPR;   // Receive Next Pointer Register
-    AT91_REG     US_RNCR;   // Receive Next Counter Register
-    AT91_REG     US_TNPR;   // Transmit Next Pointer Register
-    AT91_REG     US_TNCR;   // Transmit Next Counter Register
-    AT91_REG     US_PTCR;   // PDC Transfer Control Register
-    AT91_REG     US_PTSR;   // PDC Transfer Status Register
-} AT91S_USART, *AT91PS_USART;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Usart */
+/* ***************************************************************************** */
+typedef struct _AT91S_USART
+{
+    AT91_REG US_CR;           /* Control Register */
+    AT91_REG US_MR;           /* Mode Register */
+    AT91_REG US_IER;          /* Interrupt Enable Register */
+    AT91_REG US_IDR;          /* Interrupt Disable Register */
+    AT91_REG US_IMR;          /* Interrupt Mask Register */
+    AT91_REG US_CSR;          /* Channel Status Register */
+    AT91_REG US_RHR;          /* Receiver Holding Register */
+    AT91_REG US_THR;          /* Transmitter Holding Register */
+    AT91_REG US_BRGR;         /* Baud Rate Generator Register */
+    AT91_REG US_RTOR;         /* Receiver Time-out Register */
+    AT91_REG US_TTGR;         /* Transmitter Time-guard Register */
+    AT91_REG Reserved0[ 5 ];  /* */
+    AT91_REG US_FIDI;         /* FI_DI_Ratio Register */
+    AT91_REG US_NER;          /* Nb Errors Register */
+    AT91_REG Reserved1[ 1 ];  /* */
+    AT91_REG US_IF;           /* IRDA_FILTER Register */
+    AT91_REG Reserved2[ 44 ]; /* */
+    AT91_REG US_RPR;          /* Receive Pointer Register */
+    AT91_REG US_RCR;          /* Receive Counter Register */
+    AT91_REG US_TPR;          /* Transmit Pointer Register */
+    AT91_REG US_TCR;          /* Transmit Counter Register */
+    AT91_REG US_RNPR;         /* Receive Next Pointer Register */
+    AT91_REG US_RNCR;         /* Receive Next Counter Register */
+    AT91_REG US_TNPR;         /* Transmit Next Pointer Register */
+    AT91_REG US_TNCR;         /* Transmit Next Counter Register */
+    AT91_REG US_PTCR;         /* PDC Transfer Control Register */
+    AT91_REG US_PTSR;         /* PDC Transfer Status Register */
+} AT91S_USART, * AT91PS_USART;
 
-// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
-#define AT91C_US_STTBRK       ((unsigned int) 0x1 <<  9) // (USART) Start Break
-#define AT91C_US_STPBRK       ((unsigned int) 0x1 << 10) // (USART) Stop Break
-#define AT91C_US_STTTO        ((unsigned int) 0x1 << 11) // (USART) Start Time-out
-#define AT91C_US_SENDA        ((unsigned int) 0x1 << 12) // (USART) Send Address
-#define AT91C_US_RSTIT        ((unsigned int) 0x1 << 13) // (USART) Reset Iterations
-#define AT91C_US_RSTNACK      ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge
-#define AT91C_US_RETTO        ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out
-#define AT91C_US_DTREN        ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable
-#define AT91C_US_DTRDIS       ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable
-#define AT91C_US_RTSEN        ((unsigned int) 0x1 << 18) // (USART) Request to Send enable
-#define AT91C_US_RTSDIS       ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable
-// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
-#define AT91C_US_USMODE       ((unsigned int) 0xF <<  0) // (USART) Usart mode
-#define     AT91C_US_USMODE_NORMAL               ((unsigned int) 0x0) // (USART) Normal
-#define     AT91C_US_USMODE_RS485                ((unsigned int) 0x1) // (USART) RS485
-#define     AT91C_US_USMODE_HWHSH                ((unsigned int) 0x2) // (USART) Hardware Handshaking
-#define     AT91C_US_USMODE_MODEM                ((unsigned int) 0x3) // (USART) Modem
-#define     AT91C_US_USMODE_ISO7816_0            ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0
-#define     AT91C_US_USMODE_ISO7816_1            ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1
-#define     AT91C_US_USMODE_IRDA                 ((unsigned int) 0x8) // (USART) IrDA
-#define     AT91C_US_USMODE_SWHSH                ((unsigned int) 0xC) // (USART) Software Handshaking
-#define AT91C_US_CLKS         ((unsigned int) 0x3 <<  4) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define     AT91C_US_CLKS_CLOCK                ((unsigned int) 0x0 <<  4) // (USART) Clock
-#define     AT91C_US_CLKS_FDIV1                ((unsigned int) 0x1 <<  4) // (USART) fdiv1
-#define     AT91C_US_CLKS_SLOW                 ((unsigned int) 0x2 <<  4) // (USART) slow_clock (ARM)
-#define     AT91C_US_CLKS_EXT                  ((unsigned int) 0x3 <<  4) // (USART) External (SCK)
-#define AT91C_US_CHRL         ((unsigned int) 0x3 <<  6) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define     AT91C_US_CHRL_5_BITS               ((unsigned int) 0x0 <<  6) // (USART) Character Length: 5 bits
-#define     AT91C_US_CHRL_6_BITS               ((unsigned int) 0x1 <<  6) // (USART) Character Length: 6 bits
-#define     AT91C_US_CHRL_7_BITS               ((unsigned int) 0x2 <<  6) // (USART) Character Length: 7 bits
-#define     AT91C_US_CHRL_8_BITS               ((unsigned int) 0x3 <<  6) // (USART) Character Length: 8 bits
-#define AT91C_US_SYNC         ((unsigned int) 0x1 <<  8) // (USART) Synchronous Mode Select
-#define AT91C_US_NBSTOP       ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits
-#define     AT91C_US_NBSTOP_1_BIT                ((unsigned int) 0x0 << 12) // (USART) 1 stop bit
-#define     AT91C_US_NBSTOP_15_BIT               ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
-#define     AT91C_US_NBSTOP_2_BIT                ((unsigned int) 0x2 << 12) // (USART) 2 stop bits
-#define AT91C_US_MSBF         ((unsigned int) 0x1 << 16) // (USART) Bit Order
-#define AT91C_US_MODE9        ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length
-#define AT91C_US_CKLO         ((unsigned int) 0x1 << 18) // (USART) Clock Output Select
-#define AT91C_US_OVER         ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode
-#define AT91C_US_INACK        ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge
-#define AT91C_US_DSNACK       ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK
-#define AT91C_US_MAX_ITER     ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions
-#define AT91C_US_FILTER       ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter
-// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
-#define AT91C_US_RXBRK        ((unsigned int) 0x1 <<  2) // (USART) Break Received/End of Break
-#define AT91C_US_TIMEOUT      ((unsigned int) 0x1 <<  8) // (USART) Receiver Time-out
-#define AT91C_US_ITERATION    ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached
-#define AT91C_US_NACK         ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge
-#define AT91C_US_RIIC         ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag
-#define AT91C_US_DSRIC        ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag
-#define AT91C_US_DCDIC        ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag
-#define AT91C_US_CTSIC        ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag
-// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
-// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
-// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
-#define AT91C_US_RI           ((unsigned int) 0x1 << 20) // (USART) Image of RI Input
-#define AT91C_US_DSR          ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input
-#define AT91C_US_DCD          ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input
-#define AT91C_US_CTS          ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input
+/* -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- */
+#define AT91C_US_STTBRK                  ( ( unsigned int ) 0x1 << 9 )  /* (USART) Start Break */
+#define AT91C_US_STPBRK                  ( ( unsigned int ) 0x1 << 10 ) /* (USART) Stop Break */
+#define AT91C_US_STTTO                   ( ( unsigned int ) 0x1 << 11 ) /* (USART) Start Time-out */
+#define AT91C_US_SENDA                   ( ( unsigned int ) 0x1 << 12 ) /* (USART) Send Address */
+#define AT91C_US_RSTIT                   ( ( unsigned int ) 0x1 << 13 ) /* (USART) Reset Iterations */
+#define AT91C_US_RSTNACK                 ( ( unsigned int ) 0x1 << 14 ) /* (USART) Reset Non Acknowledge */
+#define AT91C_US_RETTO                   ( ( unsigned int ) 0x1 << 15 ) /* (USART) Rearm Time-out */
+#define AT91C_US_DTREN                   ( ( unsigned int ) 0x1 << 16 ) /* (USART) Data Terminal ready Enable */
+#define AT91C_US_DTRDIS                  ( ( unsigned int ) 0x1 << 17 ) /* (USART) Data Terminal ready Disable */
+#define AT91C_US_RTSEN                   ( ( unsigned int ) 0x1 << 18 ) /* (USART) Request to Send enable */
+#define AT91C_US_RTSDIS                  ( ( unsigned int ) 0x1 << 19 ) /* (USART) Request to Send Disable */
+/* -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- */
+#define AT91C_US_USMODE                  ( ( unsigned int ) 0xF << 0 )  /* (USART) Usart mode */
+#define     AT91C_US_USMODE_NORMAL       ( ( unsigned int ) 0x0 )       /* (USART) Normal */
+#define     AT91C_US_USMODE_RS485        ( ( unsigned int ) 0x1 )       /* (USART) RS485 */
+#define     AT91C_US_USMODE_HWHSH        ( ( unsigned int ) 0x2 )       /* (USART) Hardware Handshaking */
+#define     AT91C_US_USMODE_MODEM        ( ( unsigned int ) 0x3 )       /* (USART) Modem */
+#define     AT91C_US_USMODE_ISO7816_0    ( ( unsigned int ) 0x4 )       /* (USART) ISO7816 protocol: T = 0 */
+#define     AT91C_US_USMODE_ISO7816_1    ( ( unsigned int ) 0x6 )       /* (USART) ISO7816 protocol: T = 1 */
+#define     AT91C_US_USMODE_IRDA         ( ( unsigned int ) 0x8 )       /* (USART) IrDA */
+#define     AT91C_US_USMODE_SWHSH        ( ( unsigned int ) 0xC )       /* (USART) Software Handshaking */
+#define AT91C_US_CLKS                    ( ( unsigned int ) 0x3 << 4 )  /* (USART) Clock Selection (Baud Rate generator Input Clock */
+#define     AT91C_US_CLKS_CLOCK          ( ( unsigned int ) 0x0 << 4 )  /* (USART) Clock */
+#define     AT91C_US_CLKS_FDIV1          ( ( unsigned int ) 0x1 << 4 )  /* (USART) fdiv1 */
+#define     AT91C_US_CLKS_SLOW           ( ( unsigned int ) 0x2 << 4 )  /* (USART) slow_clock (ARM) */
+#define     AT91C_US_CLKS_EXT            ( ( unsigned int ) 0x3 << 4 )  /* (USART) External (SCK) */
+#define AT91C_US_CHRL                    ( ( unsigned int ) 0x3 << 6 )  /* (USART) Clock Selection (Baud Rate generator Input Clock */
+#define     AT91C_US_CHRL_5_BITS         ( ( unsigned int ) 0x0 << 6 )  /* (USART) Character Length: 5 bits */
+#define     AT91C_US_CHRL_6_BITS         ( ( unsigned int ) 0x1 << 6 )  /* (USART) Character Length: 6 bits */
+#define     AT91C_US_CHRL_7_BITS         ( ( unsigned int ) 0x2 << 6 )  /* (USART) Character Length: 7 bits */
+#define     AT91C_US_CHRL_8_BITS         ( ( unsigned int ) 0x3 << 6 )  /* (USART) Character Length: 8 bits */
+#define AT91C_US_SYNC                    ( ( unsigned int ) 0x1 << 8 )  /* (USART) Synchronous Mode Select */
+#define AT91C_US_NBSTOP                  ( ( unsigned int ) 0x3 << 12 ) /* (USART) Number of Stop bits */
+#define     AT91C_US_NBSTOP_1_BIT        ( ( unsigned int ) 0x0 << 12 ) /* (USART) 1 stop bit */
+#define     AT91C_US_NBSTOP_15_BIT       ( ( unsigned int ) 0x1 << 12 ) /* (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits */
+#define     AT91C_US_NBSTOP_2_BIT        ( ( unsigned int ) 0x2 << 12 ) /* (USART) 2 stop bits */
+#define AT91C_US_MSBF                    ( ( unsigned int ) 0x1 << 16 ) /* (USART) Bit Order */
+#define AT91C_US_MODE9                   ( ( unsigned int ) 0x1 << 17 ) /* (USART) 9-bit Character length */
+#define AT91C_US_CKLO                    ( ( unsigned int ) 0x1 << 18 ) /* (USART) Clock Output Select */
+#define AT91C_US_OVER                    ( ( unsigned int ) 0x1 << 19 ) /* (USART) Over Sampling Mode */
+#define AT91C_US_INACK                   ( ( unsigned int ) 0x1 << 20 ) /* (USART) Inhibit Non Acknowledge */
+#define AT91C_US_DSNACK                  ( ( unsigned int ) 0x1 << 21 ) /* (USART) Disable Successive NACK */
+#define AT91C_US_MAX_ITER                ( ( unsigned int ) 0x1 << 24 ) /* (USART) Number of Repetitions */
+#define AT91C_US_FILTER                  ( ( unsigned int ) 0x1 << 28 ) /* (USART) Receive Line Filter */
+/* -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- */
+#define AT91C_US_RXBRK                   ( ( unsigned int ) 0x1 << 2 )  /* (USART) Break Received/End of Break */
+#define AT91C_US_TIMEOUT                 ( ( unsigned int ) 0x1 << 8 )  /* (USART) Receiver Time-out */
+#define AT91C_US_ITERATION               ( ( unsigned int ) 0x1 << 10 ) /* (USART) Max number of Repetitions Reached */
+#define AT91C_US_NACK                    ( ( unsigned int ) 0x1 << 13 ) /* (USART) Non Acknowledge */
+#define AT91C_US_RIIC                    ( ( unsigned int ) 0x1 << 16 ) /* (USART) Ring INdicator Input Change Flag */
+#define AT91C_US_DSRIC                   ( ( unsigned int ) 0x1 << 17 ) /* (USART) Data Set Ready Input Change Flag */
+#define AT91C_US_DCDIC                   ( ( unsigned int ) 0x1 << 18 ) /* (USART) Data Carrier Flag */
+#define AT91C_US_CTSIC                   ( ( unsigned int ) 0x1 << 19 ) /* (USART) Clear To Send Input Change Flag */
+/* -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- */
+/* -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- */
+/* -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- */
+#define AT91C_US_RI     ( ( unsigned int ) 0x1 << 20 )   /* (USART) Image of RI Input */
+#define AT91C_US_DSR    ( ( unsigned int ) 0x1 << 21 )   /* (USART) Image of DSR Input */
+#define AT91C_US_DCD    ( ( unsigned int ) 0x1 << 22 )   /* (USART) Image of DCD Input */
+#define AT91C_US_CTS    ( ( unsigned int ) 0x1 << 23 )   /* (USART) Image of CTS Input */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_SSC {
-    AT91_REG     SSC_CR;    // Control Register
-    AT91_REG     SSC_CMR;   // Clock Mode Register
-    AT91_REG     Reserved0[2];  //
-    AT91_REG     SSC_RCMR;  // Receive Clock ModeRegister
-    AT91_REG     SSC_RFMR;  // Receive Frame Mode Register
-    AT91_REG     SSC_TCMR;  // Transmit Clock Mode Register
-    AT91_REG     SSC_TFMR;  // Transmit Frame Mode Register
-    AT91_REG     SSC_RHR;   // Receive Holding Register
-    AT91_REG     SSC_THR;   // Transmit Holding Register
-    AT91_REG     Reserved1[2];  //
-    AT91_REG     SSC_RSHR;  // Receive Sync Holding Register
-    AT91_REG     SSC_TSHR;  // Transmit Sync Holding Register
-    AT91_REG     Reserved2[2];  //
-    AT91_REG     SSC_SR;    // Status Register
-    AT91_REG     SSC_IER;   // Interrupt Enable Register
-    AT91_REG     SSC_IDR;   // Interrupt Disable Register
-    AT91_REG     SSC_IMR;   // Interrupt Mask Register
-    AT91_REG     Reserved3[44];     //
-    AT91_REG     SSC_RPR;   // Receive Pointer Register
-    AT91_REG     SSC_RCR;   // Receive Counter Register
-    AT91_REG     SSC_TPR;   // Transmit Pointer Register
-    AT91_REG     SSC_TCR;   // Transmit Counter Register
-    AT91_REG     SSC_RNPR;  // Receive Next Pointer Register
-    AT91_REG     SSC_RNCR;  // Receive Next Counter Register
-    AT91_REG     SSC_TNPR;  // Transmit Next Pointer Register
-    AT91_REG     SSC_TNCR;  // Transmit Next Counter Register
-    AT91_REG     SSC_PTCR;  // PDC Transfer Control Register
-    AT91_REG     SSC_PTSR;  // PDC Transfer Status Register
-} AT91S_SSC, *AT91PS_SSC;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_SSC
+{
+    AT91_REG SSC_CR;          /* Control Register */
+    AT91_REG SSC_CMR;         /* Clock Mode Register */
+    AT91_REG Reserved0[ 2 ];  /* */
+    AT91_REG SSC_RCMR;        /* Receive Clock ModeRegister */
+    AT91_REG SSC_RFMR;        /* Receive Frame Mode Register */
+    AT91_REG SSC_TCMR;        /* Transmit Clock Mode Register */
+    AT91_REG SSC_TFMR;        /* Transmit Frame Mode Register */
+    AT91_REG SSC_RHR;         /* Receive Holding Register */
+    AT91_REG SSC_THR;         /* Transmit Holding Register */
+    AT91_REG Reserved1[ 2 ];  /* */
+    AT91_REG SSC_RSHR;        /* Receive Sync Holding Register */
+    AT91_REG SSC_TSHR;        /* Transmit Sync Holding Register */
+    AT91_REG Reserved2[ 2 ];  /* */
+    AT91_REG SSC_SR;          /* Status Register */
+    AT91_REG SSC_IER;         /* Interrupt Enable Register */
+    AT91_REG SSC_IDR;         /* Interrupt Disable Register */
+    AT91_REG SSC_IMR;         /* Interrupt Mask Register */
+    AT91_REG Reserved3[ 44 ]; /* */
+    AT91_REG SSC_RPR;         /* Receive Pointer Register */
+    AT91_REG SSC_RCR;         /* Receive Counter Register */
+    AT91_REG SSC_TPR;         /* Transmit Pointer Register */
+    AT91_REG SSC_TCR;         /* Transmit Counter Register */
+    AT91_REG SSC_RNPR;        /* Receive Next Pointer Register */
+    AT91_REG SSC_RNCR;        /* Receive Next Counter Register */
+    AT91_REG SSC_TNPR;        /* Transmit Next Pointer Register */
+    AT91_REG SSC_TNCR;        /* Transmit Next Counter Register */
+    AT91_REG SSC_PTCR;        /* PDC Transfer Control Register */
+    AT91_REG SSC_PTSR;        /* PDC Transfer Status Register */
+} AT91S_SSC, * AT91PS_SSC;
 
-// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
-#define AT91C_SSC_RXEN        ((unsigned int) 0x1 <<  0) // (SSC) Receive Enable
-#define AT91C_SSC_RXDIS       ((unsigned int) 0x1 <<  1) // (SSC) Receive Disable
-#define AT91C_SSC_TXEN        ((unsigned int) 0x1 <<  8) // (SSC) Transmit Enable
-#define AT91C_SSC_TXDIS       ((unsigned int) 0x1 <<  9) // (SSC) Transmit Disable
-#define AT91C_SSC_SWRST       ((unsigned int) 0x1 << 15) // (SSC) Software Reset
-// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
-#define AT91C_SSC_CKS         ((unsigned int) 0x3 <<  0) // (SSC) Receive/Transmit Clock Selection
-#define     AT91C_SSC_CKS_DIV                  ((unsigned int) 0x0) // (SSC) Divided Clock
-#define     AT91C_SSC_CKS_TK                   ((unsigned int) 0x1) // (SSC) TK Clock signal
-#define     AT91C_SSC_CKS_RK                   ((unsigned int) 0x2) // (SSC) RK pin
-#define AT91C_SSC_CKO         ((unsigned int) 0x7 <<  2) // (SSC) Receive/Transmit Clock Output Mode Selection
-#define     AT91C_SSC_CKO_NONE                 ((unsigned int) 0x0 <<  2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
-#define     AT91C_SSC_CKO_CONTINOUS            ((unsigned int) 0x1 <<  2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
-#define     AT91C_SSC_CKO_DATA_TX              ((unsigned int) 0x2 <<  2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
-#define AT91C_SSC_CKI         ((unsigned int) 0x1 <<  5) // (SSC) Receive/Transmit Clock Inversion
-#define AT91C_SSC_START       ((unsigned int) 0xF <<  8) // (SSC) Receive/Transmit Start Selection
-#define     AT91C_SSC_START_CONTINOUS            ((unsigned int) 0x0 <<  8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
-#define     AT91C_SSC_START_TX                   ((unsigned int) 0x1 <<  8) // (SSC) Transmit/Receive start
-#define     AT91C_SSC_START_LOW_RF               ((unsigned int) 0x2 <<  8) // (SSC) Detection of a low level on RF input
-#define     AT91C_SSC_START_HIGH_RF              ((unsigned int) 0x3 <<  8) // (SSC) Detection of a high level on RF input
-#define     AT91C_SSC_START_FALL_RF              ((unsigned int) 0x4 <<  8) // (SSC) Detection of a falling edge on RF input
-#define     AT91C_SSC_START_RISE_RF              ((unsigned int) 0x5 <<  8) // (SSC) Detection of a rising edge on RF input
-#define     AT91C_SSC_START_LEVEL_RF             ((unsigned int) 0x6 <<  8) // (SSC) Detection of any level change on RF input
-#define     AT91C_SSC_START_EDGE_RF              ((unsigned int) 0x7 <<  8) // (SSC) Detection of any edge on RF input
-#define     AT91C_SSC_START_0                    ((unsigned int) 0x8 <<  8) // (SSC) Compare 0
-#define AT91C_SSC_STTDLY      ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay
-#define AT91C_SSC_PERIOD      ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
-// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
-#define AT91C_SSC_DATLEN      ((unsigned int) 0x1F <<  0) // (SSC) Data Length
-#define AT91C_SSC_LOOP        ((unsigned int) 0x1 <<  5) // (SSC) Loop Mode
-#define AT91C_SSC_MSBF        ((unsigned int) 0x1 <<  7) // (SSC) Most Significant Bit First
-#define AT91C_SSC_DATNB       ((unsigned int) 0xF <<  8) // (SSC) Data Number per Frame
-#define AT91C_SSC_FSLEN       ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length
-#define AT91C_SSC_FSOS        ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
-#define     AT91C_SSC_FSOS_NONE                 ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
-#define     AT91C_SSC_FSOS_NEGATIVE             ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
-#define     AT91C_SSC_FSOS_POSITIVE             ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
-#define     AT91C_SSC_FSOS_LOW                  ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
-#define     AT91C_SSC_FSOS_HIGH                 ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
-#define     AT91C_SSC_FSOS_TOGGLE               ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
-#define AT91C_SSC_FSEDGE      ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection
-// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
-// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
-#define AT91C_SSC_DATDEF      ((unsigned int) 0x1 <<  5) // (SSC) Data Default Value
-#define AT91C_SSC_FSDEN       ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable
-// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
-#define AT91C_SSC_TXRDY       ((unsigned int) 0x1 <<  0) // (SSC) Transmit Ready
-#define AT91C_SSC_TXEMPTY     ((unsigned int) 0x1 <<  1) // (SSC) Transmit Empty
-#define AT91C_SSC_ENDTX       ((unsigned int) 0x1 <<  2) // (SSC) End Of Transmission
-#define AT91C_SSC_TXBUFE      ((unsigned int) 0x1 <<  3) // (SSC) Transmit Buffer Empty
-#define AT91C_SSC_RXRDY       ((unsigned int) 0x1 <<  4) // (SSC) Receive Ready
-#define AT91C_SSC_OVRUN       ((unsigned int) 0x1 <<  5) // (SSC) Receive Overrun
-#define AT91C_SSC_ENDRX       ((unsigned int) 0x1 <<  6) // (SSC) End of Reception
-#define AT91C_SSC_RXBUFF      ((unsigned int) 0x1 <<  7) // (SSC) Receive Buffer Full
-#define AT91C_SSC_TXSYN       ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync
-#define AT91C_SSC_RXSYN       ((unsigned int) 0x1 << 11) // (SSC) Receive Sync
-#define AT91C_SSC_TXENA       ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable
-#define AT91C_SSC_RXENA       ((unsigned int) 0x1 << 17) // (SSC) Receive Enable
-// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
-// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
-// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
+/* -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- */
+#define AT91C_SSC_RXEN                    ( ( unsigned int ) 0x1 << 0 )   /* (SSC) Receive Enable */
+#define AT91C_SSC_RXDIS                   ( ( unsigned int ) 0x1 << 1 )   /* (SSC) Receive Disable */
+#define AT91C_SSC_TXEN                    ( ( unsigned int ) 0x1 << 8 )   /* (SSC) Transmit Enable */
+#define AT91C_SSC_TXDIS                   ( ( unsigned int ) 0x1 << 9 )   /* (SSC) Transmit Disable */
+#define AT91C_SSC_SWRST                   ( ( unsigned int ) 0x1 << 15 )  /* (SSC) Software Reset */
+/* -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- */
+#define AT91C_SSC_CKS                     ( ( unsigned int ) 0x3 << 0 )   /* (SSC) Receive/Transmit Clock Selection */
+#define     AT91C_SSC_CKS_DIV             ( ( unsigned int ) 0x0 )        /* (SSC) Divided Clock */
+#define     AT91C_SSC_CKS_TK              ( ( unsigned int ) 0x1 )        /* (SSC) TK Clock signal */
+#define     AT91C_SSC_CKS_RK              ( ( unsigned int ) 0x2 )        /* (SSC) RK pin */
+#define AT91C_SSC_CKO                     ( ( unsigned int ) 0x7 << 2 )   /* (SSC) Receive/Transmit Clock Output Mode Selection */
+#define     AT91C_SSC_CKO_NONE            ( ( unsigned int ) 0x0 << 2 )   /* (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only */
+#define     AT91C_SSC_CKO_CONTINUOUS      ( ( unsigned int ) 0x1 << 2 )   /* (SSC) Continuous Receive/Transmit Clock RK pin: Output */
+#define     AT91C_SSC_CKO_DATA_TX         ( ( unsigned int ) 0x2 << 2 )   /* (SSC) Receive/Transmit Clock only during data transfers RK pin: Output */
+#define AT91C_SSC_CKI                     ( ( unsigned int ) 0x1 << 5 )   /* (SSC) Receive/Transmit Clock Inversion */
+#define AT91C_SSC_START                   ( ( unsigned int ) 0xF << 8 )   /* (SSC) Receive/Transmit Start Selection */
+#define     AT91C_SSC_START_CONTINUOUS    ( ( unsigned int ) 0x0 << 8 )   /* (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */
+#define     AT91C_SSC_START_TX            ( ( unsigned int ) 0x1 << 8 )   /* (SSC) Transmit/Receive start */
+#define     AT91C_SSC_START_LOW_RF        ( ( unsigned int ) 0x2 << 8 )   /* (SSC) Detection of a low level on RF input */
+#define     AT91C_SSC_START_HIGH_RF       ( ( unsigned int ) 0x3 << 8 )   /* (SSC) Detection of a high level on RF input */
+#define     AT91C_SSC_START_FALL_RF       ( ( unsigned int ) 0x4 << 8 )   /* (SSC) Detection of a falling edge on RF input */
+#define     AT91C_SSC_START_RISE_RF       ( ( unsigned int ) 0x5 << 8 )   /* (SSC) Detection of a rising edge on RF input */
+#define     AT91C_SSC_START_LEVEL_RF      ( ( unsigned int ) 0x6 << 8 )   /* (SSC) Detection of any level change on RF input */
+#define     AT91C_SSC_START_EDGE_RF       ( ( unsigned int ) 0x7 << 8 )   /* (SSC) Detection of any edge on RF input */
+#define     AT91C_SSC_START_0             ( ( unsigned int ) 0x8 << 8 )   /* (SSC) Compare 0 */
+#define AT91C_SSC_STTDLY                  ( ( unsigned int ) 0xFF << 16 ) /* (SSC) Receive/Transmit Start Delay */
+#define AT91C_SSC_PERIOD                  ( ( unsigned int ) 0xFF << 24 ) /* (SSC) Receive/Transmit Period Divider Selection */
+/* -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- */
+#define AT91C_SSC_DATLEN                  ( ( unsigned int ) 0x1F << 0 )  /* (SSC) Data Length */
+#define AT91C_SSC_LOOP                    ( ( unsigned int ) 0x1 << 5 )   /* (SSC) Loop Mode */
+#define AT91C_SSC_MSBF                    ( ( unsigned int ) 0x1 << 7 )   /* (SSC) Most Significant Bit First */
+#define AT91C_SSC_DATNB                   ( ( unsigned int ) 0xF << 8 )   /* (SSC) Data Number per Frame */
+#define AT91C_SSC_FSLEN                   ( ( unsigned int ) 0xF << 16 )  /* (SSC) Receive/Transmit Frame Sync length */
+#define AT91C_SSC_FSOS                    ( ( unsigned int ) 0x7 << 20 )  /* (SSC) Receive/Transmit Frame Sync Output Selection */
+#define     AT91C_SSC_FSOS_NONE           ( ( unsigned int ) 0x0 << 20 )  /* (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only */
+#define     AT91C_SSC_FSOS_NEGATIVE       ( ( unsigned int ) 0x1 << 20 )  /* (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse */
+#define     AT91C_SSC_FSOS_POSITIVE       ( ( unsigned int ) 0x2 << 20 )  /* (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse */
+#define     AT91C_SSC_FSOS_LOW            ( ( unsigned int ) 0x3 << 20 )  /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer */
+#define     AT91C_SSC_FSOS_HIGH           ( ( unsigned int ) 0x4 << 20 )  /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer */
+#define     AT91C_SSC_FSOS_TOGGLE         ( ( unsigned int ) 0x5 << 20 )  /* (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer */
+#define AT91C_SSC_FSEDGE                  ( ( unsigned int ) 0x1 << 24 )  /* (SSC) Frame Sync Edge Detection */
+/* -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- */
+/* -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- */
+#define AT91C_SSC_DATDEF                  ( ( unsigned int ) 0x1 << 5 )  /* (SSC) Data Default Value */
+#define AT91C_SSC_FSDEN                   ( ( unsigned int ) 0x1 << 23 ) /* (SSC) Frame Sync Data Enable */
+/* -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- */
+#define AT91C_SSC_TXRDY                   ( ( unsigned int ) 0x1 << 0 )  /* (SSC) Transmit Ready */
+#define AT91C_SSC_TXEMPTY                 ( ( unsigned int ) 0x1 << 1 )  /* (SSC) Transmit Empty */
+#define AT91C_SSC_ENDTX                   ( ( unsigned int ) 0x1 << 2 )  /* (SSC) End Of Transmission */
+#define AT91C_SSC_TXBUFE                  ( ( unsigned int ) 0x1 << 3 )  /* (SSC) Transmit Buffer Empty */
+#define AT91C_SSC_RXRDY                   ( ( unsigned int ) 0x1 << 4 )  /* (SSC) Receive Ready */
+#define AT91C_SSC_OVRUN                   ( ( unsigned int ) 0x1 << 5 )  /* (SSC) Receive Overrun */
+#define AT91C_SSC_ENDRX                   ( ( unsigned int ) 0x1 << 6 )  /* (SSC) End of Reception */
+#define AT91C_SSC_RXBUFF                  ( ( unsigned int ) 0x1 << 7 )  /* (SSC) Receive Buffer Full */
+#define AT91C_SSC_TXSYN                   ( ( unsigned int ) 0x1 << 10 ) /* (SSC) Transmit Sync */
+#define AT91C_SSC_RXSYN                   ( ( unsigned int ) 0x1 << 11 ) /* (SSC) Receive Sync */
+#define AT91C_SSC_TXENA                   ( ( unsigned int ) 0x1 << 16 ) /* (SSC) Transmit Enable */
+#define AT91C_SSC_RXENA                   ( ( unsigned int ) 0x1 << 17 ) /* (SSC) Receive Enable */
+/* -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- */
+/* -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- */
+/* -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Two-wire Interface
-// *****************************************************************************
-typedef struct _AT91S_TWI {
-    AT91_REG     TWI_CR;    // Control Register
-    AT91_REG     TWI_MMR;   // Master Mode Register
-    AT91_REG     Reserved0[1];  //
-    AT91_REG     TWI_IADR;  // Internal Address Register
-    AT91_REG     TWI_CWGR;  // Clock Waveform Generator Register
-    AT91_REG     Reserved1[3];  //
-    AT91_REG     TWI_SR;    // Status Register
-    AT91_REG     TWI_IER;   // Interrupt Enable Register
-    AT91_REG     TWI_IDR;   // Interrupt Disable Register
-    AT91_REG     TWI_IMR;   // Interrupt Mask Register
-    AT91_REG     TWI_RHR;   // Receive Holding Register
-    AT91_REG     TWI_THR;   // Transmit Holding Register
-} AT91S_TWI, *AT91PS_TWI;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Two-wire Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_TWI
+{
+    AT91_REG TWI_CR;         /* Control Register */
+    AT91_REG TWI_MMR;        /* Master Mode Register */
+    AT91_REG Reserved0[ 1 ]; /* */
+    AT91_REG TWI_IADR;       /* Internal Address Register */
+    AT91_REG TWI_CWGR;       /* Clock Waveform Generator Register */
+    AT91_REG Reserved1[ 3 ]; /* */
+    AT91_REG TWI_SR;         /* Status Register */
+    AT91_REG TWI_IER;        /* Interrupt Enable Register */
+    AT91_REG TWI_IDR;        /* Interrupt Disable Register */
+    AT91_REG TWI_IMR;        /* Interrupt Mask Register */
+    AT91_REG TWI_RHR;        /* Receive Holding Register */
+    AT91_REG TWI_THR;        /* Transmit Holding Register */
+} AT91S_TWI, * AT91PS_TWI;
 
-// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
-#define AT91C_TWI_START       ((unsigned int) 0x1 <<  0) // (TWI) Send a START Condition
-#define AT91C_TWI_STOP        ((unsigned int) 0x1 <<  1) // (TWI) Send a STOP Condition
-#define AT91C_TWI_MSEN        ((unsigned int) 0x1 <<  2) // (TWI) TWI Master Transfer Enabled
-#define AT91C_TWI_MSDIS       ((unsigned int) 0x1 <<  3) // (TWI) TWI Master Transfer Disabled
-#define AT91C_TWI_SWRST       ((unsigned int) 0x1 <<  7) // (TWI) Software Reset
-// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
-#define AT91C_TWI_IADRSZ      ((unsigned int) 0x3 <<  8) // (TWI) Internal Device Address Size
-#define     AT91C_TWI_IADRSZ_NO                   ((unsigned int) 0x0 <<  8) // (TWI) No internal device address
-#define     AT91C_TWI_IADRSZ_1_BYTE               ((unsigned int) 0x1 <<  8) // (TWI) One-byte internal device address
-#define     AT91C_TWI_IADRSZ_2_BYTE               ((unsigned int) 0x2 <<  8) // (TWI) Two-byte internal device address
-#define     AT91C_TWI_IADRSZ_3_BYTE               ((unsigned int) 0x3 <<  8) // (TWI) Three-byte internal device address
-#define AT91C_TWI_MREAD       ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction
-#define AT91C_TWI_DADR        ((unsigned int) 0x7F << 16) // (TWI) Device Address
-// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
-#define AT91C_TWI_CLDIV       ((unsigned int) 0xFF <<  0) // (TWI) Clock Low Divider
-#define AT91C_TWI_CHDIV       ((unsigned int) 0xFF <<  8) // (TWI) Clock High Divider
-#define AT91C_TWI_CKDIV       ((unsigned int) 0x7 << 16) // (TWI) Clock Divider
-// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
-#define AT91C_TWI_TXCOMP      ((unsigned int) 0x1 <<  0) // (TWI) Transmission Completed
-#define AT91C_TWI_RXRDY       ((unsigned int) 0x1 <<  1) // (TWI) Receive holding register ReaDY
-#define AT91C_TWI_TXRDY       ((unsigned int) 0x1 <<  2) // (TWI) Transmit holding register ReaDY
-#define AT91C_TWI_OVRE        ((unsigned int) 0x1 <<  6) // (TWI) Overrun Error
-#define AT91C_TWI_UNRE        ((unsigned int) 0x1 <<  7) // (TWI) Underrun Error
-#define AT91C_TWI_NACK        ((unsigned int) 0x1 <<  8) // (TWI) Not Acknowledged
-// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
-// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
-// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
+/* -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- */
+#define AT91C_TWI_START                ( ( unsigned int ) 0x1 << 0 )   /* (TWI) Send a START Condition */
+#define AT91C_TWI_STOP                 ( ( unsigned int ) 0x1 << 1 )   /* (TWI) Send a STOP Condition */
+#define AT91C_TWI_MSEN                 ( ( unsigned int ) 0x1 << 2 )   /* (TWI) TWI Master Transfer Enabled */
+#define AT91C_TWI_MSDIS                ( ( unsigned int ) 0x1 << 3 )   /* (TWI) TWI Master Transfer Disabled */
+#define AT91C_TWI_SWRST                ( ( unsigned int ) 0x1 << 7 )   /* (TWI) Software Reset */
+/* -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- */
+#define AT91C_TWI_IADRSZ               ( ( unsigned int ) 0x3 << 8 )   /* (TWI) Internal Device Address Size */
+#define     AT91C_TWI_IADRSZ_NO        ( ( unsigned int ) 0x0 << 8 )   /* (TWI) No internal device address */
+#define     AT91C_TWI_IADRSZ_1_BYTE    ( ( unsigned int ) 0x1 << 8 )   /* (TWI) One-byte internal device address */
+#define     AT91C_TWI_IADRSZ_2_BYTE    ( ( unsigned int ) 0x2 << 8 )   /* (TWI) Two-byte internal device address */
+#define     AT91C_TWI_IADRSZ_3_BYTE    ( ( unsigned int ) 0x3 << 8 )   /* (TWI) Three-byte internal device address */
+#define AT91C_TWI_MREAD                ( ( unsigned int ) 0x1 << 12 )  /* (TWI) Master Read Direction */
+#define AT91C_TWI_DADR                 ( ( unsigned int ) 0x7F << 16 ) /* (TWI) Device Address */
+/* -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- */
+#define AT91C_TWI_CLDIV                ( ( unsigned int ) 0xFF << 0 )  /* (TWI) Clock Low Divider */
+#define AT91C_TWI_CHDIV                ( ( unsigned int ) 0xFF << 8 )  /* (TWI) Clock High Divider */
+#define AT91C_TWI_CKDIV                ( ( unsigned int ) 0x7 << 16 )  /* (TWI) Clock Divider */
+/* -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- */
+#define AT91C_TWI_TXCOMP               ( ( unsigned int ) 0x1 << 0 )   /* (TWI) Transmission Completed */
+#define AT91C_TWI_RXRDY                ( ( unsigned int ) 0x1 << 1 )   /* (TWI) Receive holding register ReaDY */
+#define AT91C_TWI_TXRDY                ( ( unsigned int ) 0x1 << 2 )   /* (TWI) Transmit holding register ReaDY */
+#define AT91C_TWI_OVRE                 ( ( unsigned int ) 0x1 << 6 )   /* (TWI) Overrun Error */
+#define AT91C_TWI_UNRE                 ( ( unsigned int ) 0x1 << 7 )   /* (TWI) Underrun Error */
+#define AT91C_TWI_NACK                 ( ( unsigned int ) 0x1 << 8 )   /* (TWI) Not Acknowledged */
+/* -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- */
+/* -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- */
+/* -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR PWMC Channel Interface
-// *****************************************************************************
-typedef struct _AT91S_PWMC_CH {
-    AT91_REG     PWMC_CMR;  // Channel Mode Register
-    AT91_REG     PWMC_CDTYR;    // Channel Duty Cycle Register
-    AT91_REG     PWMC_CPRDR;    // Channel Period Register
-    AT91_REG     PWMC_CCNTR;    // Channel Counter Register
-    AT91_REG     PWMC_CUPDR;    // Channel Update Register
-    AT91_REG     PWMC_Reserved[3];  // Reserved
-} AT91S_PWMC_CH, *AT91PS_PWMC_CH;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR PWMC Channel Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_PWMC_CH
+{
+    AT91_REG PWMC_CMR;           /* Channel Mode Register */
+    AT91_REG PWMC_CDTYR;         /* Channel Duty Cycle Register */
+    AT91_REG PWMC_CPRDR;         /* Channel Period Register */
+    AT91_REG PWMC_CCNTR;         /* Channel Counter Register */
+    AT91_REG PWMC_CUPDR;         /* Channel Update Register */
+    AT91_REG PWMC_Reserved[ 3 ]; /* Reserved */
+} AT91S_PWMC_CH, * AT91PS_PWMC_CH;
 
-// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
-#define AT91C_PWMC_CPRE       ((unsigned int) 0xF <<  0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
-#define     AT91C_PWMC_CPRE_MCK                  ((unsigned int) 0x0) // (PWMC_CH)
-#define     AT91C_PWMC_CPRE_MCKA                 ((unsigned int) 0xB) // (PWMC_CH)
-#define     AT91C_PWMC_CPRE_MCKB                 ((unsigned int) 0xC) // (PWMC_CH)
-#define AT91C_PWMC_CALG       ((unsigned int) 0x1 <<  8) // (PWMC_CH) Channel Alignment
-#define AT91C_PWMC_CPOL       ((unsigned int) 0x1 <<  9) // (PWMC_CH) Channel Polarity
-#define AT91C_PWMC_CPD        ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period
-// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
-#define AT91C_PWMC_CDTY       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Duty Cycle
-// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
-#define AT91C_PWMC_CPRD       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Period
-// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
-#define AT91C_PWMC_CCNT       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Counter
-// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
-#define AT91C_PWMC_CUPD       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Update
+/* -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- */
+#define AT91C_PWMC_CPRE             ( ( unsigned int ) 0xF << 0 )  /* (PWMC_CH) Channel Pre-scaler : PWMC_CLKx */
+#define     AT91C_PWMC_CPRE_MCK     ( ( unsigned int ) 0x0 )       /* (PWMC_CH) */
+#define     AT91C_PWMC_CPRE_MCKA    ( ( unsigned int ) 0xB )       /* (PWMC_CH) */
+#define     AT91C_PWMC_CPRE_MCKB    ( ( unsigned int ) 0xC )       /* (PWMC_CH) */
+#define AT91C_PWMC_CALG             ( ( unsigned int ) 0x1 << 8 )  /* (PWMC_CH) Channel Alignment */
+#define AT91C_PWMC_CPOL             ( ( unsigned int ) 0x1 << 9 )  /* (PWMC_CH) Channel Polarity */
+#define AT91C_PWMC_CPD              ( ( unsigned int ) 0x1 << 10 ) /* (PWMC_CH) Channel Update Period */
+/* -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- */
+#define AT91C_PWMC_CDTY             ( ( unsigned int ) 0x0 << 0 )  /* (PWMC_CH) Channel Duty Cycle */
+/* -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- */
+#define AT91C_PWMC_CPRD             ( ( unsigned int ) 0x0 << 0 )  /* (PWMC_CH) Channel Period */
+/* -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- */
+#define AT91C_PWMC_CCNT             ( ( unsigned int ) 0x0 << 0 )  /* (PWMC_CH) Channel Counter */
+/* -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- */
+#define AT91C_PWMC_CUPD             ( ( unsigned int ) 0x0 << 0 )  /* (PWMC_CH) Channel Update */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_PWMC {
-    AT91_REG     PWMC_MR;   // PWMC Mode Register
-    AT91_REG     PWMC_ENA;  // PWMC Enable Register
-    AT91_REG     PWMC_DIS;  // PWMC Disable Register
-    AT91_REG     PWMC_SR;   // PWMC Status Register
-    AT91_REG     PWMC_IER;  // PWMC Interrupt Enable Register
-    AT91_REG     PWMC_IDR;  // PWMC Interrupt Disable Register
-    AT91_REG     PWMC_IMR;  // PWMC Interrupt Mask Register
-    AT91_REG     PWMC_ISR;  // PWMC Interrupt Status Register
-    AT91_REG     Reserved0[55];     //
-    AT91_REG     PWMC_VR;   // PWMC Version Register
-    AT91_REG     Reserved1[64];     //
-    AT91S_PWMC_CH    PWMC_CH[4];    // PWMC Channel
-} AT91S_PWMC, *AT91PS_PWMC;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_PWMC
+{
+    AT91_REG PWMC_MR;           /* PWMC Mode Register */
+    AT91_REG PWMC_ENA;          /* PWMC Enable Register */
+    AT91_REG PWMC_DIS;          /* PWMC Disable Register */
+    AT91_REG PWMC_SR;           /* PWMC Status Register */
+    AT91_REG PWMC_IER;          /* PWMC Interrupt Enable Register */
+    AT91_REG PWMC_IDR;          /* PWMC Interrupt Disable Register */
+    AT91_REG PWMC_IMR;          /* PWMC Interrupt Mask Register */
+    AT91_REG PWMC_ISR;          /* PWMC Interrupt Status Register */
+    AT91_REG Reserved0[ 55 ];   /* */
+    AT91_REG PWMC_VR;           /* PWMC Version Register */
+    AT91_REG Reserved1[ 64 ];   /* */
+    AT91S_PWMC_CH PWMC_CH[ 4 ]; /* PWMC Channel */
+} AT91S_PWMC, * AT91PS_PWMC;
 
-// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
-#define AT91C_PWMC_DIVA       ((unsigned int) 0xFF <<  0) // (PWMC) CLKA divide factor.
-#define AT91C_PWMC_PREA       ((unsigned int) 0xF <<  8) // (PWMC) Divider Input Clock Prescaler A
-#define     AT91C_PWMC_PREA_MCK                  ((unsigned int) 0x0 <<  8) // (PWMC)
-#define AT91C_PWMC_DIVB       ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor.
-#define AT91C_PWMC_PREB       ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B
-#define     AT91C_PWMC_PREB_MCK                  ((unsigned int) 0x0 << 24) // (PWMC)
-// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
-#define AT91C_PWMC_CHID0      ((unsigned int) 0x1 <<  0) // (PWMC) Channel ID 0
-#define AT91C_PWMC_CHID1      ((unsigned int) 0x1 <<  1) // (PWMC) Channel ID 1
-#define AT91C_PWMC_CHID2      ((unsigned int) 0x1 <<  2) // (PWMC) Channel ID 2
-#define AT91C_PWMC_CHID3      ((unsigned int) 0x1 <<  3) // (PWMC) Channel ID 3
-// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
-// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
-// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
-// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
-// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
-// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
+/* -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- */
+#define AT91C_PWMC_DIVA            ( ( unsigned int ) 0xFF << 0 )  /* (PWMC) CLKA divide factor. */
+#define AT91C_PWMC_PREA            ( ( unsigned int ) 0xF << 8 )   /* (PWMC) Divider Input Clock Prescaler A */
+#define     AT91C_PWMC_PREA_MCK    ( ( unsigned int ) 0x0 << 8 )   /* (PWMC) */
+#define AT91C_PWMC_DIVB            ( ( unsigned int ) 0xFF << 16 ) /* (PWMC) CLKB divide factor. */
+#define AT91C_PWMC_PREB            ( ( unsigned int ) 0xF << 24 )  /* (PWMC) Divider Input Clock Prescaler B */
+#define     AT91C_PWMC_PREB_MCK    ( ( unsigned int ) 0x0 << 24 )  /* (PWMC) */
+/* -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- */
+#define AT91C_PWMC_CHID0           ( ( unsigned int ) 0x1 << 0 )   /* (PWMC) Channel ID 0 */
+#define AT91C_PWMC_CHID1           ( ( unsigned int ) 0x1 << 1 )   /* (PWMC) Channel ID 1 */
+#define AT91C_PWMC_CHID2           ( ( unsigned int ) 0x1 << 2 )   /* (PWMC) Channel ID 2 */
+#define AT91C_PWMC_CHID3           ( ( unsigned int ) 0x1 << 3 )   /* (PWMC) Channel ID 3 */
+/* -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- */
+/* -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- */
+/* -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- */
+/* -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- */
+/* -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- */
+/* -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR USB Device Interface
-// *****************************************************************************
-typedef struct _AT91S_UDP {
-    AT91_REG     UDP_NUM;   // Frame Number Register
-    AT91_REG     UDP_GLBSTATE;  // Global State Register
-    AT91_REG     UDP_FADDR;     // Function Address Register
-    AT91_REG     Reserved0[1];  //
-    AT91_REG     UDP_IER;   // Interrupt Enable Register
-    AT91_REG     UDP_IDR;   // Interrupt Disable Register
-    AT91_REG     UDP_IMR;   // Interrupt Mask Register
-    AT91_REG     UDP_ISR;   // Interrupt Status Register
-    AT91_REG     UDP_ICR;   // Interrupt Clear Register
-    AT91_REG     Reserved1[1];  //
-    AT91_REG     UDP_RSTEP;     // Reset Endpoint Register
-    AT91_REG     Reserved2[1];  //
-    AT91_REG     UDP_CSR[6];    // Endpoint Control and Status Register
-    AT91_REG     Reserved3[2];  //
-    AT91_REG     UDP_FDR[6];    // Endpoint FIFO Data Register
-    AT91_REG     Reserved4[3];  //
-    AT91_REG     UDP_TXVC;  // Transceiver Control Register
-} AT91S_UDP, *AT91PS_UDP;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR USB Device Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_UDP
+{
+    AT91_REG UDP_NUM;        /* Frame Number Register */
+    AT91_REG UDP_GLBSTATE;   /* Global State Register */
+    AT91_REG UDP_FADDR;      /* Function Address Register */
+    AT91_REG Reserved0[ 1 ]; /* */
+    AT91_REG UDP_IER;        /* Interrupt Enable Register */
+    AT91_REG UDP_IDR;        /* Interrupt Disable Register */
+    AT91_REG UDP_IMR;        /* Interrupt Mask Register */
+    AT91_REG UDP_ISR;        /* Interrupt Status Register */
+    AT91_REG UDP_ICR;        /* Interrupt Clear Register */
+    AT91_REG Reserved1[ 1 ]; /* */
+    AT91_REG UDP_RSTEP;      /* Reset Endpoint Register */
+    AT91_REG Reserved2[ 1 ]; /* */
+    AT91_REG UDP_CSR[ 6 ];   /* Endpoint Control and Status Register */
+    AT91_REG Reserved3[ 2 ]; /* */
+    AT91_REG UDP_FDR[ 6 ];   /* Endpoint FIFO Data Register */
+    AT91_REG Reserved4[ 3 ]; /* */
+    AT91_REG UDP_TXVC;       /* Transceiver Control Register */
+} AT91S_UDP, * AT91PS_UDP;
 
-// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
-#define AT91C_UDP_FRM_NUM     ((unsigned int) 0x7FF <<  0) // (UDP) Frame Number as Defined in the Packet Field Formats
-#define AT91C_UDP_FRM_ERR     ((unsigned int) 0x1 << 16) // (UDP) Frame Error
-#define AT91C_UDP_FRM_OK      ((unsigned int) 0x1 << 17) // (UDP) Frame OK
-// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
-#define AT91C_UDP_FADDEN      ((unsigned int) 0x1 <<  0) // (UDP) Function Address Enable
-#define AT91C_UDP_CONFG       ((unsigned int) 0x1 <<  1) // (UDP) Configured
-#define AT91C_UDP_ESR         ((unsigned int) 0x1 <<  2) // (UDP) Enable Send Resume
-#define AT91C_UDP_RSMINPR     ((unsigned int) 0x1 <<  3) // (UDP) A Resume Has Been Sent to the Host
-#define AT91C_UDP_RMWUPE      ((unsigned int) 0x1 <<  4) // (UDP) Remote Wake Up Enable
-// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
-#define AT91C_UDP_FADD        ((unsigned int) 0xFF <<  0) // (UDP) Function Address Value
-#define AT91C_UDP_FEN         ((unsigned int) 0x1 <<  8) // (UDP) Function Enable
-// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
-#define AT91C_UDP_EPINT0      ((unsigned int) 0x1 <<  0) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT1      ((unsigned int) 0x1 <<  1) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT2      ((unsigned int) 0x1 <<  2) // (UDP) Endpoint 2 Interrupt
-#define AT91C_UDP_EPINT3      ((unsigned int) 0x1 <<  3) // (UDP) Endpoint 3 Interrupt
-#define AT91C_UDP_EPINT4      ((unsigned int) 0x1 <<  4) // (UDP) Endpoint 4 Interrupt
-#define AT91C_UDP_EPINT5      ((unsigned int) 0x1 <<  5) // (UDP) Endpoint 5 Interrupt
-#define AT91C_UDP_RXSUSP      ((unsigned int) 0x1 <<  8) // (UDP) USB Suspend Interrupt
-#define AT91C_UDP_RXRSM       ((unsigned int) 0x1 <<  9) // (UDP) USB Resume Interrupt
-#define AT91C_UDP_EXTRSM      ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt
-#define AT91C_UDP_SOFINT      ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt
-#define AT91C_UDP_WAKEUP      ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt
-// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
-// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
-// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
-#define AT91C_UDP_ENDBUSRES   ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
-// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
-// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
-#define AT91C_UDP_EP0         ((unsigned int) 0x1 <<  0) // (UDP) Reset Endpoint 0
-#define AT91C_UDP_EP1         ((unsigned int) 0x1 <<  1) // (UDP) Reset Endpoint 1
-#define AT91C_UDP_EP2         ((unsigned int) 0x1 <<  2) // (UDP) Reset Endpoint 2
-#define AT91C_UDP_EP3         ((unsigned int) 0x1 <<  3) // (UDP) Reset Endpoint 3
-#define AT91C_UDP_EP4         ((unsigned int) 0x1 <<  4) // (UDP) Reset Endpoint 4
-#define AT91C_UDP_EP5         ((unsigned int) 0x1 <<  5) // (UDP) Reset Endpoint 5
-// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
-#define AT91C_UDP_TXCOMP      ((unsigned int) 0x1 <<  0) // (UDP) Generates an IN packet with data previously written in the DPR
-#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 <<  1) // (UDP) Receive Data Bank 0
-#define AT91C_UDP_RXSETUP     ((unsigned int) 0x1 <<  2) // (UDP) Sends STALL to the Host (Control endpoints)
-#define AT91C_UDP_ISOERROR    ((unsigned int) 0x1 <<  3) // (UDP) Isochronous error (Isochronous endpoints)
-#define AT91C_UDP_TXPKTRDY    ((unsigned int) 0x1 <<  4) // (UDP) Transmit Packet Ready
-#define AT91C_UDP_FORCESTALL  ((unsigned int) 0x1 <<  5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
-#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 <<  6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
-#define AT91C_UDP_DIR         ((unsigned int) 0x1 <<  7) // (UDP) Transfer Direction
-#define AT91C_UDP_EPTYPE      ((unsigned int) 0x7 <<  8) // (UDP) Endpoint type
-#define     AT91C_UDP_EPTYPE_CTRL                 ((unsigned int) 0x0 <<  8) // (UDP) Control
-#define     AT91C_UDP_EPTYPE_ISO_OUT              ((unsigned int) 0x1 <<  8) // (UDP) Isochronous OUT
-#define     AT91C_UDP_EPTYPE_BULK_OUT             ((unsigned int) 0x2 <<  8) // (UDP) Bulk OUT
-#define     AT91C_UDP_EPTYPE_INT_OUT              ((unsigned int) 0x3 <<  8) // (UDP) Interrupt OUT
-#define     AT91C_UDP_EPTYPE_ISO_IN               ((unsigned int) 0x5 <<  8) // (UDP) Isochronous IN
-#define     AT91C_UDP_EPTYPE_BULK_IN              ((unsigned int) 0x6 <<  8) // (UDP) Bulk IN
-#define     AT91C_UDP_EPTYPE_INT_IN               ((unsigned int) 0x7 <<  8) // (UDP) Interrupt IN
-#define AT91C_UDP_DTGLE       ((unsigned int) 0x1 << 11) // (UDP) Data Toggle
-#define AT91C_UDP_EPEDS       ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable
-#define AT91C_UDP_RXBYTECNT   ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
-// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------
-#define AT91C_UDP_TXVDIS      ((unsigned int) 0x1 <<  8) // (UDP)
-#define AT91C_UDP_PUON        ((unsigned int) 0x1 <<  9) // (UDP) Pull-up ON
+/* -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- */
+#define AT91C_UDP_FRM_NUM    ( ( unsigned int ) 0x7FF << 0 ) /* (UDP) Frame Number as Defined in the Packet Field Formats */
+#define AT91C_UDP_FRM_ERR    ( ( unsigned int ) 0x1 << 16 )  /* (UDP) Frame Error */
+#define AT91C_UDP_FRM_OK     ( ( unsigned int ) 0x1 << 17 )  /* (UDP) Frame OK */
+/* -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- */
+#define AT91C_UDP_FADDEN     ( ( unsigned int ) 0x1 << 0 )   /* (UDP) Function Address Enable */
+#define AT91C_UDP_CONFG      ( ( unsigned int ) 0x1 << 1 )   /* (UDP) Configured */
+#define AT91C_UDP_ESR        ( ( unsigned int ) 0x1 << 2 )   /* (UDP) Enable Send Resume */
+#define AT91C_UDP_RSMINPR    ( ( unsigned int ) 0x1 << 3 )   /* (UDP) A Resume Has Been Sent to the Host */
+#define AT91C_UDP_RMWUPE     ( ( unsigned int ) 0x1 << 4 )   /* (UDP) Remote Wake Up Enable */
+/* -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- */
+#define AT91C_UDP_FADD       ( ( unsigned int ) 0xFF << 0 )  /* (UDP) Function Address Value */
+#define AT91C_UDP_FEN        ( ( unsigned int ) 0x1 << 8 )   /* (UDP) Function Enable */
+/* -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- */
+#define AT91C_UDP_EPINT0     ( ( unsigned int ) 0x1 << 0 )   /* (UDP) Endpoint 0 Interrupt */
+#define AT91C_UDP_EPINT1     ( ( unsigned int ) 0x1 << 1 )   /* (UDP) Endpoint 0 Interrupt */
+#define AT91C_UDP_EPINT2     ( ( unsigned int ) 0x1 << 2 )   /* (UDP) Endpoint 2 Interrupt */
+#define AT91C_UDP_EPINT3     ( ( unsigned int ) 0x1 << 3 )   /* (UDP) Endpoint 3 Interrupt */
+#define AT91C_UDP_EPINT4     ( ( unsigned int ) 0x1 << 4 )   /* (UDP) Endpoint 4 Interrupt */
+#define AT91C_UDP_EPINT5     ( ( unsigned int ) 0x1 << 5 )   /* (UDP) Endpoint 5 Interrupt */
+#define AT91C_UDP_RXSUSP     ( ( unsigned int ) 0x1 << 8 )   /* (UDP) USB Suspend Interrupt */
+#define AT91C_UDP_RXRSM      ( ( unsigned int ) 0x1 << 9 )   /* (UDP) USB Resume Interrupt */
+#define AT91C_UDP_EXTRSM     ( ( unsigned int ) 0x1 << 10 )  /* (UDP) USB External Resume Interrupt */
+#define AT91C_UDP_SOFINT     ( ( unsigned int ) 0x1 << 11 )  /* (UDP) USB Start Of frame Interrupt */
+#define AT91C_UDP_WAKEUP     ( ( unsigned int ) 0x1 << 13 )  /* (UDP) USB Resume Interrupt */
+/* -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- */
+/* -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- */
+/* -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- */
+#define AT91C_UDP_ENDBUSRES              ( ( unsigned int ) 0x1 << 12 ) /* (UDP) USB End Of Bus Reset Interrupt */
+/* -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- */
+/* -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- */
+#define AT91C_UDP_EP0                    ( ( unsigned int ) 0x1 << 0 )    /* (UDP) Reset Endpoint 0 */
+#define AT91C_UDP_EP1                    ( ( unsigned int ) 0x1 << 1 )    /* (UDP) Reset Endpoint 1 */
+#define AT91C_UDP_EP2                    ( ( unsigned int ) 0x1 << 2 )    /* (UDP) Reset Endpoint 2 */
+#define AT91C_UDP_EP3                    ( ( unsigned int ) 0x1 << 3 )    /* (UDP) Reset Endpoint 3 */
+#define AT91C_UDP_EP4                    ( ( unsigned int ) 0x1 << 4 )    /* (UDP) Reset Endpoint 4 */
+#define AT91C_UDP_EP5                    ( ( unsigned int ) 0x1 << 5 )    /* (UDP) Reset Endpoint 5 */
+/* -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- */
+#define AT91C_UDP_TXCOMP                 ( ( unsigned int ) 0x1 << 0 )    /* (UDP) Generates an IN packet with data previously written in the DPR */
+#define AT91C_UDP_RX_DATA_BK0            ( ( unsigned int ) 0x1 << 1 )    /* (UDP) Receive Data Bank 0 */
+#define AT91C_UDP_RXSETUP                ( ( unsigned int ) 0x1 << 2 )    /* (UDP) Sends STALL to the Host (Control endpoints) */
+#define AT91C_UDP_ISOERROR               ( ( unsigned int ) 0x1 << 3 )    /* (UDP) Isochronous error (Isochronous endpoints) */
+#define AT91C_UDP_TXPKTRDY               ( ( unsigned int ) 0x1 << 4 )    /* (UDP) Transmit Packet Ready */
+#define AT91C_UDP_FORCESTALL             ( ( unsigned int ) 0x1 << 5 )    /* (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). */
+#define AT91C_UDP_RX_DATA_BK1            ( ( unsigned int ) 0x1 << 6 )    /* (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). */
+#define AT91C_UDP_DIR                    ( ( unsigned int ) 0x1 << 7 )    /* (UDP) Transfer Direction */
+#define AT91C_UDP_EPTYPE                 ( ( unsigned int ) 0x7 << 8 )    /* (UDP) Endpoint type */
+#define     AT91C_UDP_EPTYPE_CTRL        ( ( unsigned int ) 0x0 << 8 )    /* (UDP) Control */
+#define     AT91C_UDP_EPTYPE_ISO_OUT     ( ( unsigned int ) 0x1 << 8 )    /* (UDP) Isochronous OUT */
+#define     AT91C_UDP_EPTYPE_BULK_OUT    ( ( unsigned int ) 0x2 << 8 )    /* (UDP) Bulk OUT */
+#define     AT91C_UDP_EPTYPE_INT_OUT     ( ( unsigned int ) 0x3 << 8 )    /* (UDP) Interrupt OUT */
+#define     AT91C_UDP_EPTYPE_ISO_IN      ( ( unsigned int ) 0x5 << 8 )    /* (UDP) Isochronous IN */
+#define     AT91C_UDP_EPTYPE_BULK_IN     ( ( unsigned int ) 0x6 << 8 )    /* (UDP) Bulk IN */
+#define     AT91C_UDP_EPTYPE_INT_IN      ( ( unsigned int ) 0x7 << 8 )    /* (UDP) Interrupt IN */
+#define AT91C_UDP_DTGLE                  ( ( unsigned int ) 0x1 << 11 )   /* (UDP) Data Toggle */
+#define AT91C_UDP_EPEDS                  ( ( unsigned int ) 0x1 << 15 )   /* (UDP) Endpoint Enable Disable */
+#define AT91C_UDP_RXBYTECNT              ( ( unsigned int ) 0x7FF << 16 ) /* (UDP) Number Of Bytes Available in the FIFO */
+/* -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- */
+#define AT91C_UDP_TXVDIS                 ( ( unsigned int ) 0x1 << 8 )    /* (UDP) */
+#define AT91C_UDP_PUON                   ( ( unsigned int ) 0x1 << 9 )    /* (UDP) Pull-up ON */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
-// *****************************************************************************
-typedef struct _AT91S_TC {
-    AT91_REG     TC_CCR;    // Channel Control Register
-    AT91_REG     TC_CMR;    // Channel Mode Register (Capture Mode / Waveform Mode)
-    AT91_REG     Reserved0[2];  //
-    AT91_REG     TC_CV;     // Counter Value
-    AT91_REG     TC_RA;     // Register A
-    AT91_REG     TC_RB;     // Register B
-    AT91_REG     TC_RC;     // Register C
-    AT91_REG     TC_SR;     // Status Register
-    AT91_REG     TC_IER;    // Interrupt Enable Register
-    AT91_REG     TC_IDR;    // Interrupt Disable Register
-    AT91_REG     TC_IMR;    // Interrupt Mask Register
-} AT91S_TC, *AT91PS_TC;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_TC
+{
+    AT91_REG TC_CCR;         /* Channel Control Register */
+    AT91_REG TC_CMR;         /* Channel Mode Register (Capture Mode / Waveform Mode) */
+    AT91_REG Reserved0[ 2 ]; /* */
+    AT91_REG TC_CV;          /* Counter Value */
+    AT91_REG TC_RA;          /* Register A */
+    AT91_REG TC_RB;          /* Register B */
+    AT91_REG TC_RC;          /* Register C */
+    AT91_REG TC_SR;          /* Status Register */
+    AT91_REG TC_IER;         /* Interrupt Enable Register */
+    AT91_REG TC_IDR;         /* Interrupt Disable Register */
+    AT91_REG TC_IMR;         /* Interrupt Mask Register */
+} AT91S_TC, * AT91PS_TC;
 
-// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
-#define AT91C_TC_CLKEN        ((unsigned int) 0x1 <<  0) // (TC) Counter Clock Enable Command
-#define AT91C_TC_CLKDIS       ((unsigned int) 0x1 <<  1) // (TC) Counter Clock Disable Command
-#define AT91C_TC_SWTRG        ((unsigned int) 0x1 <<  2) // (TC) Software Trigger Command
-// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
-#define AT91C_TC_CLKS         ((unsigned int) 0x7 <<  0) // (TC) Clock Selection
-#define     AT91C_TC_CLKS_TIMER_DIV1_CLOCK     ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
-#define     AT91C_TC_CLKS_TIMER_DIV2_CLOCK     ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
-#define     AT91C_TC_CLKS_TIMER_DIV3_CLOCK     ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
-#define     AT91C_TC_CLKS_TIMER_DIV4_CLOCK     ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
-#define     AT91C_TC_CLKS_TIMER_DIV5_CLOCK     ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
-#define     AT91C_TC_CLKS_XC0                  ((unsigned int) 0x5) // (TC) Clock selected: XC0
-#define     AT91C_TC_CLKS_XC1                  ((unsigned int) 0x6) // (TC) Clock selected: XC1
-#define     AT91C_TC_CLKS_XC2                  ((unsigned int) 0x7) // (TC) Clock selected: XC2
-#define AT91C_TC_CLKI         ((unsigned int) 0x1 <<  3) // (TC) Clock Invert
-#define AT91C_TC_BURST        ((unsigned int) 0x3 <<  4) // (TC) Burst Signal Selection
-#define     AT91C_TC_BURST_NONE                 ((unsigned int) 0x0 <<  4) // (TC) The clock is not gated by an external signal
-#define     AT91C_TC_BURST_XC0                  ((unsigned int) 0x1 <<  4) // (TC) XC0 is ANDed with the selected clock
-#define     AT91C_TC_BURST_XC1                  ((unsigned int) 0x2 <<  4) // (TC) XC1 is ANDed with the selected clock
-#define     AT91C_TC_BURST_XC2                  ((unsigned int) 0x3 <<  4) // (TC) XC2 is ANDed with the selected clock
-#define AT91C_TC_CPCSTOP      ((unsigned int) 0x1 <<  6) // (TC) Counter Clock Stopped with RC Compare
-#define AT91C_TC_LDBSTOP      ((unsigned int) 0x1 <<  6) // (TC) Counter Clock Stopped with RB Loading
-#define AT91C_TC_CPCDIS       ((unsigned int) 0x1 <<  7) // (TC) Counter Clock Disable with RC Compare
-#define AT91C_TC_LDBDIS       ((unsigned int) 0x1 <<  7) // (TC) Counter Clock Disabled with RB Loading
-#define AT91C_TC_ETRGEDG      ((unsigned int) 0x3 <<  8) // (TC) External Trigger Edge Selection
-#define     AT91C_TC_ETRGEDG_NONE                 ((unsigned int) 0x0 <<  8) // (TC) Edge: None
-#define     AT91C_TC_ETRGEDG_RISING               ((unsigned int) 0x1 <<  8) // (TC) Edge: rising edge
-#define     AT91C_TC_ETRGEDG_FALLING              ((unsigned int) 0x2 <<  8) // (TC) Edge: falling edge
-#define     AT91C_TC_ETRGEDG_BOTH                 ((unsigned int) 0x3 <<  8) // (TC) Edge: each edge
-#define AT91C_TC_EEVTEDG      ((unsigned int) 0x3 <<  8) // (TC) External Event Edge Selection
-#define     AT91C_TC_EEVTEDG_NONE                 ((unsigned int) 0x0 <<  8) // (TC) Edge: None
-#define     AT91C_TC_EEVTEDG_RISING               ((unsigned int) 0x1 <<  8) // (TC) Edge: rising edge
-#define     AT91C_TC_EEVTEDG_FALLING              ((unsigned int) 0x2 <<  8) // (TC) Edge: falling edge
-#define     AT91C_TC_EEVTEDG_BOTH                 ((unsigned int) 0x3 <<  8) // (TC) Edge: each edge
-#define AT91C_TC_EEVT         ((unsigned int) 0x3 << 10) // (TC) External Event  Selection
-#define     AT91C_TC_EEVT_TIOB                 ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
-#define     AT91C_TC_EEVT_XC0                  ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
-#define     AT91C_TC_EEVT_XC1                  ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
-#define     AT91C_TC_EEVT_XC2                  ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
-#define AT91C_TC_ABETRG       ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
-#define AT91C_TC_ENETRG       ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable
-#define AT91C_TC_WAVESEL      ((unsigned int) 0x3 << 13) // (TC) Waveform  Selection
-#define     AT91C_TC_WAVESEL_UP                   ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
-#define     AT91C_TC_WAVESEL_UPDOWN               ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
-#define     AT91C_TC_WAVESEL_UP_AUTO              ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
-#define     AT91C_TC_WAVESEL_UPDOWN_AUTO          ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
-#define AT91C_TC_CPCTRG       ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable
-#define AT91C_TC_WAVE         ((unsigned int) 0x1 << 15) // (TC)
-#define AT91C_TC_ACPA         ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA
-#define     AT91C_TC_ACPA_NONE                 ((unsigned int) 0x0 << 16) // (TC) Effect: none
-#define     AT91C_TC_ACPA_SET                  ((unsigned int) 0x1 << 16) // (TC) Effect: set
-#define     AT91C_TC_ACPA_CLEAR                ((unsigned int) 0x2 << 16) // (TC) Effect: clear
-#define     AT91C_TC_ACPA_TOGGLE               ((unsigned int) 0x3 << 16) // (TC) Effect: toggle
-#define AT91C_TC_LDRA         ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection
-#define     AT91C_TC_LDRA_NONE                 ((unsigned int) 0x0 << 16) // (TC) Edge: None
-#define     AT91C_TC_LDRA_RISING               ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA
-#define     AT91C_TC_LDRA_FALLING              ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA
-#define     AT91C_TC_LDRA_BOTH                 ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_ACPC         ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA
-#define     AT91C_TC_ACPC_NONE                 ((unsigned int) 0x0 << 18) // (TC) Effect: none
-#define     AT91C_TC_ACPC_SET                  ((unsigned int) 0x1 << 18) // (TC) Effect: set
-#define     AT91C_TC_ACPC_CLEAR                ((unsigned int) 0x2 << 18) // (TC) Effect: clear
-#define     AT91C_TC_ACPC_TOGGLE               ((unsigned int) 0x3 << 18) // (TC) Effect: toggle
-#define AT91C_TC_LDRB         ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection
-#define     AT91C_TC_LDRB_NONE                 ((unsigned int) 0x0 << 18) // (TC) Edge: None
-#define     AT91C_TC_LDRB_RISING               ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA
-#define     AT91C_TC_LDRB_FALLING              ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA
-#define     AT91C_TC_LDRB_BOTH                 ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_AEEVT        ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA
-#define     AT91C_TC_AEEVT_NONE                 ((unsigned int) 0x0 << 20) // (TC) Effect: none
-#define     AT91C_TC_AEEVT_SET                  ((unsigned int) 0x1 << 20) // (TC) Effect: set
-#define     AT91C_TC_AEEVT_CLEAR                ((unsigned int) 0x2 << 20) // (TC) Effect: clear
-#define     AT91C_TC_AEEVT_TOGGLE               ((unsigned int) 0x3 << 20) // (TC) Effect: toggle
-#define AT91C_TC_ASWTRG       ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA
-#define     AT91C_TC_ASWTRG_NONE                 ((unsigned int) 0x0 << 22) // (TC) Effect: none
-#define     AT91C_TC_ASWTRG_SET                  ((unsigned int) 0x1 << 22) // (TC) Effect: set
-#define     AT91C_TC_ASWTRG_CLEAR                ((unsigned int) 0x2 << 22) // (TC) Effect: clear
-#define     AT91C_TC_ASWTRG_TOGGLE               ((unsigned int) 0x3 << 22) // (TC) Effect: toggle
-#define AT91C_TC_BCPB         ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB
-#define     AT91C_TC_BCPB_NONE                 ((unsigned int) 0x0 << 24) // (TC) Effect: none
-#define     AT91C_TC_BCPB_SET                  ((unsigned int) 0x1 << 24) // (TC) Effect: set
-#define     AT91C_TC_BCPB_CLEAR                ((unsigned int) 0x2 << 24) // (TC) Effect: clear
-#define     AT91C_TC_BCPB_TOGGLE               ((unsigned int) 0x3 << 24) // (TC) Effect: toggle
-#define AT91C_TC_BCPC         ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB
-#define     AT91C_TC_BCPC_NONE                 ((unsigned int) 0x0 << 26) // (TC) Effect: none
-#define     AT91C_TC_BCPC_SET                  ((unsigned int) 0x1 << 26) // (TC) Effect: set
-#define     AT91C_TC_BCPC_CLEAR                ((unsigned int) 0x2 << 26) // (TC) Effect: clear
-#define     AT91C_TC_BCPC_TOGGLE               ((unsigned int) 0x3 << 26) // (TC) Effect: toggle
-#define AT91C_TC_BEEVT        ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB
-#define     AT91C_TC_BEEVT_NONE                 ((unsigned int) 0x0 << 28) // (TC) Effect: none
-#define     AT91C_TC_BEEVT_SET                  ((unsigned int) 0x1 << 28) // (TC) Effect: set
-#define     AT91C_TC_BEEVT_CLEAR                ((unsigned int) 0x2 << 28) // (TC) Effect: clear
-#define     AT91C_TC_BEEVT_TOGGLE               ((unsigned int) 0x3 << 28) // (TC) Effect: toggle
-#define AT91C_TC_BSWTRG       ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB
-#define     AT91C_TC_BSWTRG_NONE                 ((unsigned int) 0x0 << 30) // (TC) Effect: none
-#define     AT91C_TC_BSWTRG_SET                  ((unsigned int) 0x1 << 30) // (TC) Effect: set
-#define     AT91C_TC_BSWTRG_CLEAR                ((unsigned int) 0x2 << 30) // (TC) Effect: clear
-#define     AT91C_TC_BSWTRG_TOGGLE               ((unsigned int) 0x3 << 30) // (TC) Effect: toggle
-// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
-#define AT91C_TC_COVFS        ((unsigned int) 0x1 <<  0) // (TC) Counter Overflow
-#define AT91C_TC_LOVRS        ((unsigned int) 0x1 <<  1) // (TC) Load Overrun
-#define AT91C_TC_CPAS         ((unsigned int) 0x1 <<  2) // (TC) RA Compare
-#define AT91C_TC_CPBS         ((unsigned int) 0x1 <<  3) // (TC) RB Compare
-#define AT91C_TC_CPCS         ((unsigned int) 0x1 <<  4) // (TC) RC Compare
-#define AT91C_TC_LDRAS        ((unsigned int) 0x1 <<  5) // (TC) RA Loading
-#define AT91C_TC_LDRBS        ((unsigned int) 0x1 <<  6) // (TC) RB Loading
-#define AT91C_TC_ETRGS        ((unsigned int) 0x1 <<  7) // (TC) External Trigger
-#define AT91C_TC_CLKSTA       ((unsigned int) 0x1 << 16) // (TC) Clock Enabling
-#define AT91C_TC_MTIOA        ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror
-#define AT91C_TC_MTIOB        ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror
-// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
-// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
-// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
+/* -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- */
+#define AT91C_TC_CLKEN                        ( ( unsigned int ) 0x1 << 0 )  /* (TC) Counter Clock Enable Command */
+#define AT91C_TC_CLKDIS                       ( ( unsigned int ) 0x1 << 1 )  /* (TC) Counter Clock Disable Command */
+#define AT91C_TC_SWTRG                        ( ( unsigned int ) 0x1 << 2 )  /* (TC) Software Trigger Command */
+/* -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- */
+#define AT91C_TC_CLKS                         ( ( unsigned int ) 0x7 << 0 )  /* (TC) Clock Selection */
+#define     AT91C_TC_CLKS_TIMER_DIV1_CLOCK    ( ( unsigned int ) 0x0 )       /* (TC) Clock selected: TIMER_DIV1_CLOCK */
+#define     AT91C_TC_CLKS_TIMER_DIV2_CLOCK    ( ( unsigned int ) 0x1 )       /* (TC) Clock selected: TIMER_DIV2_CLOCK */
+#define     AT91C_TC_CLKS_TIMER_DIV3_CLOCK    ( ( unsigned int ) 0x2 )       /* (TC) Clock selected: TIMER_DIV3_CLOCK */
+#define     AT91C_TC_CLKS_TIMER_DIV4_CLOCK    ( ( unsigned int ) 0x3 )       /* (TC) Clock selected: TIMER_DIV4_CLOCK */
+#define     AT91C_TC_CLKS_TIMER_DIV5_CLOCK    ( ( unsigned int ) 0x4 )       /* (TC) Clock selected: TIMER_DIV5_CLOCK */
+#define     AT91C_TC_CLKS_XC0                 ( ( unsigned int ) 0x5 )       /* (TC) Clock selected: XC0 */
+#define     AT91C_TC_CLKS_XC1                 ( ( unsigned int ) 0x6 )       /* (TC) Clock selected: XC1 */
+#define     AT91C_TC_CLKS_XC2                 ( ( unsigned int ) 0x7 )       /* (TC) Clock selected: XC2 */
+#define AT91C_TC_CLKI                         ( ( unsigned int ) 0x1 << 3 )  /* (TC) Clock Invert */
+#define AT91C_TC_BURST                        ( ( unsigned int ) 0x3 << 4 )  /* (TC) Burst Signal Selection */
+#define     AT91C_TC_BURST_NONE               ( ( unsigned int ) 0x0 << 4 )  /* (TC) The clock is not gated by an external signal */
+#define     AT91C_TC_BURST_XC0                ( ( unsigned int ) 0x1 << 4 )  /* (TC) XC0 is ANDed with the selected clock */
+#define     AT91C_TC_BURST_XC1                ( ( unsigned int ) 0x2 << 4 )  /* (TC) XC1 is ANDed with the selected clock */
+#define     AT91C_TC_BURST_XC2                ( ( unsigned int ) 0x3 << 4 )  /* (TC) XC2 is ANDed with the selected clock */
+#define AT91C_TC_CPCSTOP                      ( ( unsigned int ) 0x1 << 6 )  /* (TC) Counter Clock Stopped with RC Compare */
+#define AT91C_TC_LDBSTOP                      ( ( unsigned int ) 0x1 << 6 )  /* (TC) Counter Clock Stopped with RB Loading */
+#define AT91C_TC_CPCDIS                       ( ( unsigned int ) 0x1 << 7 )  /* (TC) Counter Clock Disable with RC Compare */
+#define AT91C_TC_LDBDIS                       ( ( unsigned int ) 0x1 << 7 )  /* (TC) Counter Clock Disabled with RB Loading */
+#define AT91C_TC_ETRGEDG                      ( ( unsigned int ) 0x3 << 8 )  /* (TC) External Trigger Edge Selection */
+#define     AT91C_TC_ETRGEDG_NONE             ( ( unsigned int ) 0x0 << 8 )  /* (TC) Edge: None */
+#define     AT91C_TC_ETRGEDG_RISING           ( ( unsigned int ) 0x1 << 8 )  /* (TC) Edge: rising edge */
+#define     AT91C_TC_ETRGEDG_FALLING          ( ( unsigned int ) 0x2 << 8 )  /* (TC) Edge: falling edge */
+#define     AT91C_TC_ETRGEDG_BOTH             ( ( unsigned int ) 0x3 << 8 )  /* (TC) Edge: each edge */
+#define AT91C_TC_EEVTEDG                      ( ( unsigned int ) 0x3 << 8 )  /* (TC) External Event Edge Selection */
+#define     AT91C_TC_EEVTEDG_NONE             ( ( unsigned int ) 0x0 << 8 )  /* (TC) Edge: None */
+#define     AT91C_TC_EEVTEDG_RISING           ( ( unsigned int ) 0x1 << 8 )  /* (TC) Edge: rising edge */
+#define     AT91C_TC_EEVTEDG_FALLING          ( ( unsigned int ) 0x2 << 8 )  /* (TC) Edge: falling edge */
+#define     AT91C_TC_EEVTEDG_BOTH             ( ( unsigned int ) 0x3 << 8 )  /* (TC) Edge: each edge */
+#define AT91C_TC_EEVT                         ( ( unsigned int ) 0x3 << 10 ) /* (TC) External Event  Selection */
+#define     AT91C_TC_EEVT_TIOB                ( ( unsigned int ) 0x0 << 10 ) /* (TC) Signal selected as external event: TIOB TIOB direction: input */
+#define     AT91C_TC_EEVT_XC0                 ( ( unsigned int ) 0x1 << 10 ) /* (TC) Signal selected as external event: XC0 TIOB direction: output */
+#define     AT91C_TC_EEVT_XC1                 ( ( unsigned int ) 0x2 << 10 ) /* (TC) Signal selected as external event: XC1 TIOB direction: output */
+#define     AT91C_TC_EEVT_XC2                 ( ( unsigned int ) 0x3 << 10 ) /* (TC) Signal selected as external event: XC2 TIOB direction: output */
+#define AT91C_TC_ABETRG                       ( ( unsigned int ) 0x1 << 10 ) /* (TC) TIOA or TIOB External Trigger Selection */
+#define AT91C_TC_ENETRG                       ( ( unsigned int ) 0x1 << 12 ) /* (TC) External Event Trigger enable */
+#define AT91C_TC_WAVESEL                      ( ( unsigned int ) 0x3 << 13 ) /* (TC) Waveform  Selection */
+#define     AT91C_TC_WAVESEL_UP               ( ( unsigned int ) 0x0 << 13 ) /* (TC) UP mode without atomatic trigger on RC Compare */
+#define     AT91C_TC_WAVESEL_UPDOWN           ( ( unsigned int ) 0x1 << 13 ) /* (TC) UPDOWN mode without automatic trigger on RC Compare */
+#define     AT91C_TC_WAVESEL_UP_AUTO          ( ( unsigned int ) 0x2 << 13 ) /* (TC) UP mode with automatic trigger on RC Compare */
+#define     AT91C_TC_WAVESEL_UPDOWN_AUTO      ( ( unsigned int ) 0x3 << 13 ) /* (TC) UPDOWN mode with automatic trigger on RC Compare */
+#define AT91C_TC_CPCTRG                       ( ( unsigned int ) 0x1 << 14 ) /* (TC) RC Compare Trigger Enable */
+#define AT91C_TC_WAVE                         ( ( unsigned int ) 0x1 << 15 ) /* (TC) */
+#define AT91C_TC_ACPA                         ( ( unsigned int ) 0x3 << 16 ) /* (TC) RA Compare Effect on TIOA */
+#define     AT91C_TC_ACPA_NONE                ( ( unsigned int ) 0x0 << 16 ) /* (TC) Effect: none */
+#define     AT91C_TC_ACPA_SET                 ( ( unsigned int ) 0x1 << 16 ) /* (TC) Effect: set */
+#define     AT91C_TC_ACPA_CLEAR               ( ( unsigned int ) 0x2 << 16 ) /* (TC) Effect: clear */
+#define     AT91C_TC_ACPA_TOGGLE              ( ( unsigned int ) 0x3 << 16 ) /* (TC) Effect: toggle */
+#define AT91C_TC_LDRA                         ( ( unsigned int ) 0x3 << 16 ) /* (TC) RA Loading Selection */
+#define     AT91C_TC_LDRA_NONE                ( ( unsigned int ) 0x0 << 16 ) /* (TC) Edge: None */
+#define     AT91C_TC_LDRA_RISING              ( ( unsigned int ) 0x1 << 16 ) /* (TC) Edge: rising edge of TIOA */
+#define     AT91C_TC_LDRA_FALLING             ( ( unsigned int ) 0x2 << 16 ) /* (TC) Edge: falling edge of TIOA */
+#define     AT91C_TC_LDRA_BOTH                ( ( unsigned int ) 0x3 << 16 ) /* (TC) Edge: each edge of TIOA */
+#define AT91C_TC_ACPC                         ( ( unsigned int ) 0x3 << 18 ) /* (TC) RC Compare Effect on TIOA */
+#define     AT91C_TC_ACPC_NONE                ( ( unsigned int ) 0x0 << 18 ) /* (TC) Effect: none */
+#define     AT91C_TC_ACPC_SET                 ( ( unsigned int ) 0x1 << 18 ) /* (TC) Effect: set */
+#define     AT91C_TC_ACPC_CLEAR               ( ( unsigned int ) 0x2 << 18 ) /* (TC) Effect: clear */
+#define     AT91C_TC_ACPC_TOGGLE              ( ( unsigned int ) 0x3 << 18 ) /* (TC) Effect: toggle */
+#define AT91C_TC_LDRB                         ( ( unsigned int ) 0x3 << 18 ) /* (TC) RB Loading Selection */
+#define     AT91C_TC_LDRB_NONE                ( ( unsigned int ) 0x0 << 18 ) /* (TC) Edge: None */
+#define     AT91C_TC_LDRB_RISING              ( ( unsigned int ) 0x1 << 18 ) /* (TC) Edge: rising edge of TIOA */
+#define     AT91C_TC_LDRB_FALLING             ( ( unsigned int ) 0x2 << 18 ) /* (TC) Edge: falling edge of TIOA */
+#define     AT91C_TC_LDRB_BOTH                ( ( unsigned int ) 0x3 << 18 ) /* (TC) Edge: each edge of TIOA */
+#define AT91C_TC_AEEVT                        ( ( unsigned int ) 0x3 << 20 ) /* (TC) External Event Effect on TIOA */
+#define     AT91C_TC_AEEVT_NONE               ( ( unsigned int ) 0x0 << 20 ) /* (TC) Effect: none */
+#define     AT91C_TC_AEEVT_SET                ( ( unsigned int ) 0x1 << 20 ) /* (TC) Effect: set */
+#define     AT91C_TC_AEEVT_CLEAR              ( ( unsigned int ) 0x2 << 20 ) /* (TC) Effect: clear */
+#define     AT91C_TC_AEEVT_TOGGLE             ( ( unsigned int ) 0x3 << 20 ) /* (TC) Effect: toggle */
+#define AT91C_TC_ASWTRG                       ( ( unsigned int ) 0x3 << 22 ) /* (TC) Software Trigger Effect on TIOA */
+#define     AT91C_TC_ASWTRG_NONE              ( ( unsigned int ) 0x0 << 22 ) /* (TC) Effect: none */
+#define     AT91C_TC_ASWTRG_SET               ( ( unsigned int ) 0x1 << 22 ) /* (TC) Effect: set */
+#define     AT91C_TC_ASWTRG_CLEAR             ( ( unsigned int ) 0x2 << 22 ) /* (TC) Effect: clear */
+#define     AT91C_TC_ASWTRG_TOGGLE            ( ( unsigned int ) 0x3 << 22 ) /* (TC) Effect: toggle */
+#define AT91C_TC_BCPB                         ( ( unsigned int ) 0x3 << 24 ) /* (TC) RB Compare Effect on TIOB */
+#define     AT91C_TC_BCPB_NONE                ( ( unsigned int ) 0x0 << 24 ) /* (TC) Effect: none */
+#define     AT91C_TC_BCPB_SET                 ( ( unsigned int ) 0x1 << 24 ) /* (TC) Effect: set */
+#define     AT91C_TC_BCPB_CLEAR               ( ( unsigned int ) 0x2 << 24 ) /* (TC) Effect: clear */
+#define     AT91C_TC_BCPB_TOGGLE              ( ( unsigned int ) 0x3 << 24 ) /* (TC) Effect: toggle */
+#define AT91C_TC_BCPC                         ( ( unsigned int ) 0x3 << 26 ) /* (TC) RC Compare Effect on TIOB */
+#define     AT91C_TC_BCPC_NONE                ( ( unsigned int ) 0x0 << 26 ) /* (TC) Effect: none */
+#define     AT91C_TC_BCPC_SET                 ( ( unsigned int ) 0x1 << 26 ) /* (TC) Effect: set */
+#define     AT91C_TC_BCPC_CLEAR               ( ( unsigned int ) 0x2 << 26 ) /* (TC) Effect: clear */
+#define     AT91C_TC_BCPC_TOGGLE              ( ( unsigned int ) 0x3 << 26 ) /* (TC) Effect: toggle */
+#define AT91C_TC_BEEVT                        ( ( unsigned int ) 0x3 << 28 ) /* (TC) External Event Effect on TIOB */
+#define     AT91C_TC_BEEVT_NONE               ( ( unsigned int ) 0x0 << 28 ) /* (TC) Effect: none */
+#define     AT91C_TC_BEEVT_SET                ( ( unsigned int ) 0x1 << 28 ) /* (TC) Effect: set */
+#define     AT91C_TC_BEEVT_CLEAR              ( ( unsigned int ) 0x2 << 28 ) /* (TC) Effect: clear */
+#define     AT91C_TC_BEEVT_TOGGLE             ( ( unsigned int ) 0x3 << 28 ) /* (TC) Effect: toggle */
+#define AT91C_TC_BSWTRG                       ( ( unsigned int ) 0x3 << 30 ) /* (TC) Software Trigger Effect on TIOB */
+#define     AT91C_TC_BSWTRG_NONE              ( ( unsigned int ) 0x0 << 30 ) /* (TC) Effect: none */
+#define     AT91C_TC_BSWTRG_SET               ( ( unsigned int ) 0x1 << 30 ) /* (TC) Effect: set */
+#define     AT91C_TC_BSWTRG_CLEAR             ( ( unsigned int ) 0x2 << 30 ) /* (TC) Effect: clear */
+#define     AT91C_TC_BSWTRG_TOGGLE            ( ( unsigned int ) 0x3 << 30 ) /* (TC) Effect: toggle */
+/* -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- */
+#define AT91C_TC_COVFS                        ( ( unsigned int ) 0x1 << 0 )  /* (TC) Counter Overflow */
+#define AT91C_TC_LOVRS                        ( ( unsigned int ) 0x1 << 1 )  /* (TC) Load Overrun */
+#define AT91C_TC_CPAS                         ( ( unsigned int ) 0x1 << 2 )  /* (TC) RA Compare */
+#define AT91C_TC_CPBS                         ( ( unsigned int ) 0x1 << 3 )  /* (TC) RB Compare */
+#define AT91C_TC_CPCS                         ( ( unsigned int ) 0x1 << 4 )  /* (TC) RC Compare */
+#define AT91C_TC_LDRAS                        ( ( unsigned int ) 0x1 << 5 )  /* (TC) RA Loading */
+#define AT91C_TC_LDRBS                        ( ( unsigned int ) 0x1 << 6 )  /* (TC) RB Loading */
+#define AT91C_TC_ETRGS                        ( ( unsigned int ) 0x1 << 7 )  /* (TC) External Trigger */
+#define AT91C_TC_CLKSTA                       ( ( unsigned int ) 0x1 << 16 ) /* (TC) Clock Enabling */
+#define AT91C_TC_MTIOA                        ( ( unsigned int ) 0x1 << 17 ) /* (TC) TIOA Mirror */
+#define AT91C_TC_MTIOB                        ( ( unsigned int ) 0x1 << 18 ) /* (TC) TIOA Mirror */
+/* -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- */
+/* -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- */
+/* -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Timer Counter Interface
-// *****************************************************************************
-typedef struct _AT91S_TCB {
-    AT91S_TC     TCB_TC0;   // TC Channel 0
-    AT91_REG     Reserved0[4];  //
-    AT91S_TC     TCB_TC1;   // TC Channel 1
-    AT91_REG     Reserved1[4];  //
-    AT91S_TC     TCB_TC2;   // TC Channel 2
-    AT91_REG     Reserved2[4];  //
-    AT91_REG     TCB_BCR;   // TC Block Control Register
-    AT91_REG     TCB_BMR;   // TC Block Mode Register
-} AT91S_TCB, *AT91PS_TCB;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Timer Counter Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_TCB
+{
+    AT91S_TC TCB_TC0;        /* TC Channel 0 */
+    AT91_REG Reserved0[ 4 ]; /* */
+    AT91S_TC TCB_TC1;        /* TC Channel 1 */
+    AT91_REG Reserved1[ 4 ]; /* */
+    AT91S_TC TCB_TC2;        /* TC Channel 2 */
+    AT91_REG Reserved2[ 4 ]; /* */
+    AT91_REG TCB_BCR;        /* TC Block Control Register */
+    AT91_REG TCB_BMR;        /* TC Block Mode Register */
+} AT91S_TCB, * AT91PS_TCB;
 
-// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
-#define AT91C_TCB_SYNC        ((unsigned int) 0x1 <<  0) // (TCB) Synchro Command
-// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
-#define AT91C_TCB_TC0XC0S     ((unsigned int) 0x3 <<  0) // (TCB) External Clock Signal 0 Selection
-#define     AT91C_TCB_TC0XC0S_TCLK0                ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0
-#define     AT91C_TCB_TC0XC0S_NONE                 ((unsigned int) 0x1) // (TCB) None signal connected to XC0
-#define     AT91C_TCB_TC0XC0S_TIOA1                ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0
-#define     AT91C_TCB_TC0XC0S_TIOA2                ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0
-#define AT91C_TCB_TC1XC1S     ((unsigned int) 0x3 <<  2) // (TCB) External Clock Signal 1 Selection
-#define     AT91C_TCB_TC1XC1S_TCLK1                ((unsigned int) 0x0 <<  2) // (TCB) TCLK1 connected to XC1
-#define     AT91C_TCB_TC1XC1S_NONE                 ((unsigned int) 0x1 <<  2) // (TCB) None signal connected to XC1
-#define     AT91C_TCB_TC1XC1S_TIOA0                ((unsigned int) 0x2 <<  2) // (TCB) TIOA0 connected to XC1
-#define     AT91C_TCB_TC1XC1S_TIOA2                ((unsigned int) 0x3 <<  2) // (TCB) TIOA2 connected to XC1
-#define AT91C_TCB_TC2XC2S     ((unsigned int) 0x3 <<  4) // (TCB) External Clock Signal 2 Selection
-#define     AT91C_TCB_TC2XC2S_TCLK2                ((unsigned int) 0x0 <<  4) // (TCB) TCLK2 connected to XC2
-#define     AT91C_TCB_TC2XC2S_NONE                 ((unsigned int) 0x1 <<  4) // (TCB) None signal connected to XC2
-#define     AT91C_TCB_TC2XC2S_TIOA0                ((unsigned int) 0x2 <<  4) // (TCB) TIOA0 connected to XC2
-#define     AT91C_TCB_TC2XC2S_TIOA1                ((unsigned int) 0x3 <<  4) // (TCB) TIOA2 connected to XC2
+/* -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- */
+#define AT91C_TCB_SYNC                 ( ( unsigned int ) 0x1 << 0 ) /* (TCB) Synchro Command */
+/* -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- */
+#define AT91C_TCB_TC0XC0S              ( ( unsigned int ) 0x3 << 0 ) /* (TCB) External Clock Signal 0 Selection */
+#define     AT91C_TCB_TC0XC0S_TCLK0    ( ( unsigned int ) 0x0 )      /* (TCB) TCLK0 connected to XC0 */
+#define     AT91C_TCB_TC0XC0S_NONE     ( ( unsigned int ) 0x1 )      /* (TCB) None signal connected to XC0 */
+#define     AT91C_TCB_TC0XC0S_TIOA1    ( ( unsigned int ) 0x2 )      /* (TCB) TIOA1 connected to XC0 */
+#define     AT91C_TCB_TC0XC0S_TIOA2    ( ( unsigned int ) 0x3 )      /* (TCB) TIOA2 connected to XC0 */
+#define AT91C_TCB_TC1XC1S              ( ( unsigned int ) 0x3 << 2 ) /* (TCB) External Clock Signal 1 Selection */
+#define     AT91C_TCB_TC1XC1S_TCLK1    ( ( unsigned int ) 0x0 << 2 ) /* (TCB) TCLK1 connected to XC1 */
+#define     AT91C_TCB_TC1XC1S_NONE     ( ( unsigned int ) 0x1 << 2 ) /* (TCB) None signal connected to XC1 */
+#define     AT91C_TCB_TC1XC1S_TIOA0    ( ( unsigned int ) 0x2 << 2 ) /* (TCB) TIOA0 connected to XC1 */
+#define     AT91C_TCB_TC1XC1S_TIOA2    ( ( unsigned int ) 0x3 << 2 ) /* (TCB) TIOA2 connected to XC1 */
+#define AT91C_TCB_TC2XC2S              ( ( unsigned int ) 0x3 << 4 ) /* (TCB) External Clock Signal 2 Selection */
+#define     AT91C_TCB_TC2XC2S_TCLK2    ( ( unsigned int ) 0x0 << 4 ) /* (TCB) TCLK2 connected to XC2 */
+#define     AT91C_TCB_TC2XC2S_NONE     ( ( unsigned int ) 0x1 << 4 ) /* (TCB) None signal connected to XC2 */
+#define     AT91C_TCB_TC2XC2S_TIOA0    ( ( unsigned int ) 0x2 << 4 ) /* (TCB) TIOA0 connected to XC2 */
+#define     AT91C_TCB_TC2XC2S_TIOA1    ( ( unsigned int ) 0x3 << 4 ) /* (TCB) TIOA2 connected to XC2 */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Control Area Network MailBox Interface
-// *****************************************************************************
-typedef struct _AT91S_CAN_MB {
-    AT91_REG     CAN_MB_MMR;    // MailBox Mode Register
-    AT91_REG     CAN_MB_MAM;    // MailBox Acceptance Mask Register
-    AT91_REG     CAN_MB_MID;    // MailBox ID Register
-    AT91_REG     CAN_MB_MFID;   // MailBox Family ID Register
-    AT91_REG     CAN_MB_MSR;    // MailBox Status Register
-    AT91_REG     CAN_MB_MDL;    // MailBox Data Low Register
-    AT91_REG     CAN_MB_MDH;    // MailBox Data High Register
-    AT91_REG     CAN_MB_MCR;    // MailBox Control Register
-} AT91S_CAN_MB, *AT91PS_CAN_MB;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Control Area Network MailBox Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_CAN_MB
+{
+    AT91_REG CAN_MB_MMR;  /* MailBox Mode Register */
+    AT91_REG CAN_MB_MAM;  /* MailBox Acceptance Mask Register */
+    AT91_REG CAN_MB_MID;  /* MailBox ID Register */
+    AT91_REG CAN_MB_MFID; /* MailBox Family ID Register */
+    AT91_REG CAN_MB_MSR;  /* MailBox Status Register */
+    AT91_REG CAN_MB_MDL;  /* MailBox Data Low Register */
+    AT91_REG CAN_MB_MDH;  /* MailBox Data High Register */
+    AT91_REG CAN_MB_MCR;  /* MailBox Control Register */
+} AT91S_CAN_MB, * AT91PS_CAN_MB;
 
-// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register --------
-#define AT91C_CAN_MTIMEMARK   ((unsigned int) 0xFFFF <<  0) // (CAN_MB) Mailbox Timemark
-#define AT91C_CAN_PRIOR       ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority
-#define AT91C_CAN_MOT         ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type
-#define     AT91C_CAN_MOT_DIS                  ((unsigned int) 0x0 << 24) // (CAN_MB)
-#define     AT91C_CAN_MOT_RX                   ((unsigned int) 0x1 << 24) // (CAN_MB)
-#define     AT91C_CAN_MOT_RXOVERWRITE          ((unsigned int) 0x2 << 24) // (CAN_MB)
-#define     AT91C_CAN_MOT_TX                   ((unsigned int) 0x3 << 24) // (CAN_MB)
-#define     AT91C_CAN_MOT_CONSUMER             ((unsigned int) 0x4 << 24) // (CAN_MB)
-#define     AT91C_CAN_MOT_PRODUCER             ((unsigned int) 0x5 << 24) // (CAN_MB)
-// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register --------
-#define AT91C_CAN_MIDvB       ((unsigned int) 0x3FFFF <<  0) // (CAN_MB) Complementary bits for identifier in extended mode
-#define AT91C_CAN_MIDvA       ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode
-#define AT91C_CAN_MIDE        ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version
-// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register --------
-// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register --------
-// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register --------
-#define AT91C_CAN_MTIMESTAMP  ((unsigned int) 0xFFFF <<  0) // (CAN_MB) Timer Value
-#define AT91C_CAN_MDLC        ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code
-#define AT91C_CAN_MRTR        ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request
-#define AT91C_CAN_MABT        ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort
-#define AT91C_CAN_MRDY        ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready
-#define AT91C_CAN_MMI         ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored
-// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register --------
-// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register --------
-// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register --------
-#define AT91C_CAN_MACR        ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox
-#define AT91C_CAN_MTCR        ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command
+/* -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- */
+#define AT91C_CAN_MTIMEMARK              ( ( unsigned int ) 0xFFFF << 0 )  /* (CAN_MB) Mailbox Timemark */
+#define AT91C_CAN_PRIOR                  ( ( unsigned int ) 0xF << 16 )    /* (CAN_MB) Mailbox Priority */
+#define AT91C_CAN_MOT                    ( ( unsigned int ) 0x7 << 24 )    /* (CAN_MB) Mailbox Object Type */
+#define     AT91C_CAN_MOT_DIS            ( ( unsigned int ) 0x0 << 24 )    /* (CAN_MB) */
+#define     AT91C_CAN_MOT_RX             ( ( unsigned int ) 0x1 << 24 )    /* (CAN_MB) */
+#define     AT91C_CAN_MOT_RXOVERWRITE    ( ( unsigned int ) 0x2 << 24 )    /* (CAN_MB) */
+#define     AT91C_CAN_MOT_TX             ( ( unsigned int ) 0x3 << 24 )    /* (CAN_MB) */
+#define     AT91C_CAN_MOT_CONSUMER       ( ( unsigned int ) 0x4 << 24 )    /* (CAN_MB) */
+#define     AT91C_CAN_MOT_PRODUCER       ( ( unsigned int ) 0x5 << 24 )    /* (CAN_MB) */
+/* -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- */
+#define AT91C_CAN_MIDvB                  ( ( unsigned int ) 0x3FFFF << 0 ) /* (CAN_MB) Complementary bits for identifier in extended mode */
+#define AT91C_CAN_MIDvA                  ( ( unsigned int ) 0x7FF << 18 )  /* (CAN_MB) Identifier for standard frame mode */
+#define AT91C_CAN_MIDE                   ( ( unsigned int ) 0x1 << 29 )    /* (CAN_MB) Identifier Version */
+/* -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- */
+/* -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- */
+/* -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- */
+#define AT91C_CAN_MTIMESTAMP    ( ( unsigned int ) 0xFFFF << 0 ) /* (CAN_MB) Timer Value */
+#define AT91C_CAN_MDLC          ( ( unsigned int ) 0xF << 16 )   /* (CAN_MB) Mailbox Data Length Code */
+#define AT91C_CAN_MRTR          ( ( unsigned int ) 0x1 << 20 )   /* (CAN_MB) Mailbox Remote Transmission Request */
+#define AT91C_CAN_MABT          ( ( unsigned int ) 0x1 << 22 )   /* (CAN_MB) Mailbox Message Abort */
+#define AT91C_CAN_MRDY          ( ( unsigned int ) 0x1 << 23 )   /* (CAN_MB) Mailbox Ready */
+#define AT91C_CAN_MMI           ( ( unsigned int ) 0x1 << 24 )   /* (CAN_MB) Mailbox Message Ignored */
+/* -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- */
+/* -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- */
+/* -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- */
+#define AT91C_CAN_MACR    ( ( unsigned int ) 0x1 << 22 ) /* (CAN_MB) Abort Request for Mailbox */
+#define AT91C_CAN_MTCR    ( ( unsigned int ) 0x1 << 23 ) /* (CAN_MB) Mailbox Transfer Command */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Control Area Network Interface
-// *****************************************************************************
-typedef struct _AT91S_CAN {
-    AT91_REG     CAN_MR;    // Mode Register
-    AT91_REG     CAN_IER;   // Interrupt Enable Register
-    AT91_REG     CAN_IDR;   // Interrupt Disable Register
-    AT91_REG     CAN_IMR;   // Interrupt Mask Register
-    AT91_REG     CAN_SR;    // Status Register
-    AT91_REG     CAN_BR;    // Baudrate Register
-    AT91_REG     CAN_TIM;   // Timer Register
-    AT91_REG     CAN_TIMESTP;   // Time Stamp Register
-    AT91_REG     CAN_ECR;   // Error Counter Register
-    AT91_REG     CAN_TCR;   // Transfer Command Register
-    AT91_REG     CAN_ACR;   // Abort Command Register
-    AT91_REG     Reserved0[52];     //
-    AT91_REG     CAN_VR;    // Version Register
-    AT91_REG     Reserved1[64];     //
-    AT91S_CAN_MB     CAN_MB0;   // CAN Mailbox 0
-    AT91S_CAN_MB     CAN_MB1;   // CAN Mailbox 1
-    AT91S_CAN_MB     CAN_MB2;   // CAN Mailbox 2
-    AT91S_CAN_MB     CAN_MB3;   // CAN Mailbox 3
-    AT91S_CAN_MB     CAN_MB4;   // CAN Mailbox 4
-    AT91S_CAN_MB     CAN_MB5;   // CAN Mailbox 5
-    AT91S_CAN_MB     CAN_MB6;   // CAN Mailbox 6
-    AT91S_CAN_MB     CAN_MB7;   // CAN Mailbox 7
-    AT91S_CAN_MB     CAN_MB8;   // CAN Mailbox 8
-    AT91S_CAN_MB     CAN_MB9;   // CAN Mailbox 9
-    AT91S_CAN_MB     CAN_MB10;  // CAN Mailbox 10
-    AT91S_CAN_MB     CAN_MB11;  // CAN Mailbox 11
-    AT91S_CAN_MB     CAN_MB12;  // CAN Mailbox 12
-    AT91S_CAN_MB     CAN_MB13;  // CAN Mailbox 13
-    AT91S_CAN_MB     CAN_MB14;  // CAN Mailbox 14
-    AT91S_CAN_MB     CAN_MB15;  // CAN Mailbox 15
-} AT91S_CAN, *AT91PS_CAN;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Control Area Network Interface */
+/* ***************************************************************************** */
+typedef struct _AT91S_CAN
+{
+    AT91_REG CAN_MR;          /* Mode Register */
+    AT91_REG CAN_IER;         /* Interrupt Enable Register */
+    AT91_REG CAN_IDR;         /* Interrupt Disable Register */
+    AT91_REG CAN_IMR;         /* Interrupt Mask Register */
+    AT91_REG CAN_SR;          /* Status Register */
+    AT91_REG CAN_BR;          /* Baudrate Register */
+    AT91_REG CAN_TIM;         /* Timer Register */
+    AT91_REG CAN_TIMESTP;     /* Time Stamp Register */
+    AT91_REG CAN_ECR;         /* Error Counter Register */
+    AT91_REG CAN_TCR;         /* Transfer Command Register */
+    AT91_REG CAN_ACR;         /* Abort Command Register */
+    AT91_REG Reserved0[ 52 ]; /* */
+    AT91_REG CAN_VR;          /* Version Register */
+    AT91_REG Reserved1[ 64 ]; /* */
+    AT91S_CAN_MB CAN_MB0;     /* CAN Mailbox 0 */
+    AT91S_CAN_MB CAN_MB1;     /* CAN Mailbox 1 */
+    AT91S_CAN_MB CAN_MB2;     /* CAN Mailbox 2 */
+    AT91S_CAN_MB CAN_MB3;     /* CAN Mailbox 3 */
+    AT91S_CAN_MB CAN_MB4;     /* CAN Mailbox 4 */
+    AT91S_CAN_MB CAN_MB5;     /* CAN Mailbox 5 */
+    AT91S_CAN_MB CAN_MB6;     /* CAN Mailbox 6 */
+    AT91S_CAN_MB CAN_MB7;     /* CAN Mailbox 7 */
+    AT91S_CAN_MB CAN_MB8;     /* CAN Mailbox 8 */
+    AT91S_CAN_MB CAN_MB9;     /* CAN Mailbox 9 */
+    AT91S_CAN_MB CAN_MB10;    /* CAN Mailbox 10 */
+    AT91S_CAN_MB CAN_MB11;    /* CAN Mailbox 11 */
+    AT91S_CAN_MB CAN_MB12;    /* CAN Mailbox 12 */
+    AT91S_CAN_MB CAN_MB13;    /* CAN Mailbox 13 */
+    AT91S_CAN_MB CAN_MB14;    /* CAN Mailbox 14 */
+    AT91S_CAN_MB CAN_MB15;    /* CAN Mailbox 15 */
+} AT91S_CAN, * AT91PS_CAN;
 
-// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register --------
-#define AT91C_CAN_CANEN       ((unsigned int) 0x1 <<  0) // (CAN) CAN Controller Enable
-#define AT91C_CAN_LPM         ((unsigned int) 0x1 <<  1) // (CAN) Disable/Enable Low Power Mode
-#define AT91C_CAN_ABM         ((unsigned int) 0x1 <<  2) // (CAN) Disable/Enable Autobaud/Listen Mode
-#define AT91C_CAN_OVL         ((unsigned int) 0x1 <<  3) // (CAN) Disable/Enable Overload Frame
-#define AT91C_CAN_TEOF        ((unsigned int) 0x1 <<  4) // (CAN) Time Stamp messages at each end of Frame
-#define AT91C_CAN_TTM         ((unsigned int) 0x1 <<  5) // (CAN) Disable/Enable Time Trigger Mode
-#define AT91C_CAN_TIMFRZ      ((unsigned int) 0x1 <<  6) // (CAN) Enable Timer Freeze
-#define AT91C_CAN_DRPT        ((unsigned int) 0x1 <<  7) // (CAN) Disable Repeat
-// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register --------
-#define AT91C_CAN_MB0         ((unsigned int) 0x1 <<  0) // (CAN) Mailbox 0 Flag
-#define AT91C_CAN_MB1         ((unsigned int) 0x1 <<  1) // (CAN) Mailbox 1 Flag
-#define AT91C_CAN_MB2         ((unsigned int) 0x1 <<  2) // (CAN) Mailbox 2 Flag
-#define AT91C_CAN_MB3         ((unsigned int) 0x1 <<  3) // (CAN) Mailbox 3 Flag
-#define AT91C_CAN_MB4         ((unsigned int) 0x1 <<  4) // (CAN) Mailbox 4 Flag
-#define AT91C_CAN_MB5         ((unsigned int) 0x1 <<  5) // (CAN) Mailbox 5 Flag
-#define AT91C_CAN_MB6         ((unsigned int) 0x1 <<  6) // (CAN) Mailbox 6 Flag
-#define AT91C_CAN_MB7         ((unsigned int) 0x1 <<  7) // (CAN) Mailbox 7 Flag
-#define AT91C_CAN_MB8         ((unsigned int) 0x1 <<  8) // (CAN) Mailbox 8 Flag
-#define AT91C_CAN_MB9         ((unsigned int) 0x1 <<  9) // (CAN) Mailbox 9 Flag
-#define AT91C_CAN_MB10        ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag
-#define AT91C_CAN_MB11        ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag
-#define AT91C_CAN_MB12        ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag
-#define AT91C_CAN_MB13        ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag
-#define AT91C_CAN_MB14        ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag
-#define AT91C_CAN_MB15        ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag
-#define AT91C_CAN_ERRA        ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag
-#define AT91C_CAN_WARN        ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag
-#define AT91C_CAN_ERRP        ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag
-#define AT91C_CAN_BOFF        ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag
-#define AT91C_CAN_SLEEP       ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag
-#define AT91C_CAN_WAKEUP      ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag
-#define AT91C_CAN_TOVF        ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag
-#define AT91C_CAN_TSTP        ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag
-#define AT91C_CAN_CERR        ((unsigned int) 0x1 << 24) // (CAN) CRC Error
-#define AT91C_CAN_SERR        ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error
-#define AT91C_CAN_AERR        ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error
-#define AT91C_CAN_FERR        ((unsigned int) 0x1 << 27) // (CAN) Form Error
-#define AT91C_CAN_BERR        ((unsigned int) 0x1 << 28) // (CAN) Bit Error
-// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register --------
-// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register --------
-// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register --------
-#define AT91C_CAN_RBSY        ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy
-#define AT91C_CAN_TBSY        ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy
-#define AT91C_CAN_OVLY        ((unsigned int) 0x1 << 31) // (CAN) Overload Busy
-// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register --------
-#define AT91C_CAN_PHASE2      ((unsigned int) 0x7 <<  0) // (CAN) Phase 2 segment
-#define AT91C_CAN_PHASE1      ((unsigned int) 0x7 <<  4) // (CAN) Phase 1 segment
-#define AT91C_CAN_PROPAG      ((unsigned int) 0x7 <<  8) // (CAN) Programmation time segment
-#define AT91C_CAN_SYNC        ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment
-#define AT91C_CAN_BRP         ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler
-#define AT91C_CAN_SMP         ((unsigned int) 0x1 << 24) // (CAN) Sampling mode
-// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register --------
-#define AT91C_CAN_TIMER       ((unsigned int) 0xFFFF <<  0) // (CAN) Timer field
-// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register --------
-// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register --------
-#define AT91C_CAN_REC         ((unsigned int) 0xFF <<  0) // (CAN) Receive Error Counter
-#define AT91C_CAN_TEC         ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter
-// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register --------
-#define AT91C_CAN_TIMRST      ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field
-// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register --------
+/* -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- */
+#define AT91C_CAN_CANEN     ( ( unsigned int ) 0x1 << 0 )  /* (CAN) CAN Controller Enable */
+#define AT91C_CAN_LPM       ( ( unsigned int ) 0x1 << 1 )  /* (CAN) Disable/Enable Low Power Mode */
+#define AT91C_CAN_ABM       ( ( unsigned int ) 0x1 << 2 )  /* (CAN) Disable/Enable Autobaud/Listen Mode */
+#define AT91C_CAN_OVL       ( ( unsigned int ) 0x1 << 3 )  /* (CAN) Disable/Enable Overload Frame */
+#define AT91C_CAN_TEOF      ( ( unsigned int ) 0x1 << 4 )  /* (CAN) Time Stamp messages at each end of Frame */
+#define AT91C_CAN_TTM       ( ( unsigned int ) 0x1 << 5 )  /* (CAN) Disable/Enable Time Trigger Mode */
+#define AT91C_CAN_TIMFRZ    ( ( unsigned int ) 0x1 << 6 )  /* (CAN) Enable Timer Freeze */
+#define AT91C_CAN_DRPT      ( ( unsigned int ) 0x1 << 7 )  /* (CAN) Disable Repeat */
+/* -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- */
+#define AT91C_CAN_MB0       ( ( unsigned int ) 0x1 << 0 )  /* (CAN) Mailbox 0 Flag */
+#define AT91C_CAN_MB1       ( ( unsigned int ) 0x1 << 1 )  /* (CAN) Mailbox 1 Flag */
+#define AT91C_CAN_MB2       ( ( unsigned int ) 0x1 << 2 )  /* (CAN) Mailbox 2 Flag */
+#define AT91C_CAN_MB3       ( ( unsigned int ) 0x1 << 3 )  /* (CAN) Mailbox 3 Flag */
+#define AT91C_CAN_MB4       ( ( unsigned int ) 0x1 << 4 )  /* (CAN) Mailbox 4 Flag */
+#define AT91C_CAN_MB5       ( ( unsigned int ) 0x1 << 5 )  /* (CAN) Mailbox 5 Flag */
+#define AT91C_CAN_MB6       ( ( unsigned int ) 0x1 << 6 )  /* (CAN) Mailbox 6 Flag */
+#define AT91C_CAN_MB7       ( ( unsigned int ) 0x1 << 7 )  /* (CAN) Mailbox 7 Flag */
+#define AT91C_CAN_MB8       ( ( unsigned int ) 0x1 << 8 )  /* (CAN) Mailbox 8 Flag */
+#define AT91C_CAN_MB9       ( ( unsigned int ) 0x1 << 9 )  /* (CAN) Mailbox 9 Flag */
+#define AT91C_CAN_MB10      ( ( unsigned int ) 0x1 << 10 ) /* (CAN) Mailbox 10 Flag */
+#define AT91C_CAN_MB11      ( ( unsigned int ) 0x1 << 11 ) /* (CAN) Mailbox 11 Flag */
+#define AT91C_CAN_MB12      ( ( unsigned int ) 0x1 << 12 ) /* (CAN) Mailbox 12 Flag */
+#define AT91C_CAN_MB13      ( ( unsigned int ) 0x1 << 13 ) /* (CAN) Mailbox 13 Flag */
+#define AT91C_CAN_MB14      ( ( unsigned int ) 0x1 << 14 ) /* (CAN) Mailbox 14 Flag */
+#define AT91C_CAN_MB15      ( ( unsigned int ) 0x1 << 15 ) /* (CAN) Mailbox 15 Flag */
+#define AT91C_CAN_ERRA      ( ( unsigned int ) 0x1 << 16 ) /* (CAN) Error Active Mode Flag */
+#define AT91C_CAN_WARN      ( ( unsigned int ) 0x1 << 17 ) /* (CAN) Warning Limit Flag */
+#define AT91C_CAN_ERRP      ( ( unsigned int ) 0x1 << 18 ) /* (CAN) Error Passive Mode Flag */
+#define AT91C_CAN_BOFF      ( ( unsigned int ) 0x1 << 19 ) /* (CAN) Bus Off Mode Flag */
+#define AT91C_CAN_SLEEP     ( ( unsigned int ) 0x1 << 20 ) /* (CAN) Sleep Flag */
+#define AT91C_CAN_WAKEUP    ( ( unsigned int ) 0x1 << 21 ) /* (CAN) Wakeup Flag */
+#define AT91C_CAN_TOVF      ( ( unsigned int ) 0x1 << 22 ) /* (CAN) Timer Overflow Flag */
+#define AT91C_CAN_TSTP      ( ( unsigned int ) 0x1 << 23 ) /* (CAN) Timestamp Flag */
+#define AT91C_CAN_CERR      ( ( unsigned int ) 0x1 << 24 ) /* (CAN) CRC Error */
+#define AT91C_CAN_SERR      ( ( unsigned int ) 0x1 << 25 ) /* (CAN) Stuffing Error */
+#define AT91C_CAN_AERR      ( ( unsigned int ) 0x1 << 26 ) /* (CAN) Acknowledgment Error */
+#define AT91C_CAN_FERR      ( ( unsigned int ) 0x1 << 27 ) /* (CAN) Form Error */
+#define AT91C_CAN_BERR      ( ( unsigned int ) 0x1 << 28 ) /* (CAN) Bit Error */
+/* -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- */
+/* -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- */
+/* -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- */
+#define AT91C_CAN_RBSY      ( ( unsigned int ) 0x1 << 29 )   /* (CAN) Receiver Busy */
+#define AT91C_CAN_TBSY      ( ( unsigned int ) 0x1 << 30 )   /* (CAN) Transmitter Busy */
+#define AT91C_CAN_OVLY      ( ( unsigned int ) 0x1 << 31 )   /* (CAN) Overload Busy */
+/* -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- */
+#define AT91C_CAN_PHASE2    ( ( unsigned int ) 0x7 << 0 )    /* (CAN) Phase 2 segment */
+#define AT91C_CAN_PHASE1    ( ( unsigned int ) 0x7 << 4 )    /* (CAN) Phase 1 segment */
+#define AT91C_CAN_PROPAG    ( ( unsigned int ) 0x7 << 8 )    /* (CAN) Programmation time segment */
+#define AT91C_CAN_SYNC      ( ( unsigned int ) 0x3 << 12 )   /* (CAN) Re-synchronization jump width segment */
+#define AT91C_CAN_BRP       ( ( unsigned int ) 0x7F << 16 )  /* (CAN) Baudrate Prescaler */
+#define AT91C_CAN_SMP       ( ( unsigned int ) 0x1 << 24 )   /* (CAN) Sampling mode */
+/* -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- */
+#define AT91C_CAN_TIMER     ( ( unsigned int ) 0xFFFF << 0 ) /* (CAN) Timer field */
+/* -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- */
+/* -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- */
+#define AT91C_CAN_REC       ( ( unsigned int ) 0xFF << 0 )  /* (CAN) Receive Error Counter */
+#define AT91C_CAN_TEC       ( ( unsigned int ) 0xFF << 16 ) /* (CAN) Transmit Error Counter */
+/* -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- */
+#define AT91C_CAN_TIMRST    ( ( unsigned int ) 0x1 << 31 )  /* (CAN) Timer Reset Field */
+/* -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Ethernet MAC 10/100
-// *****************************************************************************
-typedef struct _AT91S_EMAC {
-    AT91_REG     EMAC_NCR;  // Network Control Register
-    AT91_REG     EMAC_NCFGR;    // Network Configuration Register
-    AT91_REG     EMAC_NSR;  // Network Status Register
-    AT91_REG     Reserved0[2];  //
-    AT91_REG     EMAC_TSR;  // Transmit Status Register
-    AT91_REG     EMAC_RBQP;     // Receive Buffer Queue Pointer
-    AT91_REG     EMAC_TBQP;     // Transmit Buffer Queue Pointer
-    AT91_REG     EMAC_RSR;  // Receive Status Register
-    AT91_REG     EMAC_ISR;  // Interrupt Status Register
-    AT91_REG     EMAC_IER;  // Interrupt Enable Register
-    AT91_REG     EMAC_IDR;  // Interrupt Disable Register
-    AT91_REG     EMAC_IMR;  // Interrupt Mask Register
-    AT91_REG     EMAC_MAN;  // PHY Maintenance Register
-    AT91_REG     EMAC_PTR;  // Pause Time Register
-    AT91_REG     EMAC_PFR;  // Pause Frames received Register
-    AT91_REG     EMAC_FTO;  // Frames Transmitted OK Register
-    AT91_REG     EMAC_SCF;  // Single Collision Frame Register
-    AT91_REG     EMAC_MCF;  // Multiple Collision Frame Register
-    AT91_REG     EMAC_FRO;  // Frames Received OK Register
-    AT91_REG     EMAC_FCSE;     // Frame Check Sequence Error Register
-    AT91_REG     EMAC_ALE;  // Alignment Error Register
-    AT91_REG     EMAC_DTF;  // Deferred Transmission Frame Register
-    AT91_REG     EMAC_LCOL;     // Late Collision Register
-    AT91_REG     EMAC_ECOL;     // Excessive Collision Register
-    AT91_REG     EMAC_TUND;     // Transmit Underrun Error Register
-    AT91_REG     EMAC_CSE;  // Carrier Sense Error Register
-    AT91_REG     EMAC_RRE;  // Receive Ressource Error Register
-    AT91_REG     EMAC_ROV;  // Receive Overrun Errors Register
-    AT91_REG     EMAC_RSE;  // Receive Symbol Errors Register
-    AT91_REG     EMAC_ELE;  // Excessive Length Errors Register
-    AT91_REG     EMAC_RJA;  // Receive Jabbers Register
-    AT91_REG     EMAC_USF;  // Undersize Frames Register
-    AT91_REG     EMAC_STE;  // SQE Test Error Register
-    AT91_REG     EMAC_RLE;  // Receive Length Field Mismatch Register
-    AT91_REG     EMAC_TPF;  // Transmitted Pause Frames Register
-    AT91_REG     EMAC_HRB;  // Hash Address Bottom[31:0]
-    AT91_REG     EMAC_HRT;  // Hash Address Top[63:32]
-    AT91_REG     EMAC_SA1L;     // Specific Address 1 Bottom, First 4 bytes
-    AT91_REG     EMAC_SA1H;     // Specific Address 1 Top, Last 2 bytes
-    AT91_REG     EMAC_SA2L;     // Specific Address 2 Bottom, First 4 bytes
-    AT91_REG     EMAC_SA2H;     // Specific Address 2 Top, Last 2 bytes
-    AT91_REG     EMAC_SA3L;     // Specific Address 3 Bottom, First 4 bytes
-    AT91_REG     EMAC_SA3H;     // Specific Address 3 Top, Last 2 bytes
-    AT91_REG     EMAC_SA4L;     // Specific Address 4 Bottom, First 4 bytes
-    AT91_REG     EMAC_SA4H;     // Specific Address 4 Top, Last 2 bytes
-    AT91_REG     EMAC_TID;  // Type ID Checking Register
-    AT91_REG     EMAC_TPQ;  // Transmit Pause Quantum Register
-    AT91_REG     EMAC_USRIO;    // USER Input/Output Register
-    AT91_REG     EMAC_WOL;  // Wake On LAN Register
-    AT91_REG     Reserved1[13];     //
-    AT91_REG     EMAC_REV;  // Revision Register
-} AT91S_EMAC, *AT91PS_EMAC;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Ethernet MAC 10/100 */
+/* ***************************************************************************** */
+typedef struct _AT91S_EMAC
+{
+    AT91_REG EMAC_NCR;        /* Network Control Register */
+    AT91_REG EMAC_NCFGR;      /* Network Configuration Register */
+    AT91_REG EMAC_NSR;        /* Network Status Register */
+    AT91_REG Reserved0[ 2 ];  /* */
+    AT91_REG EMAC_TSR;        /* Transmit Status Register */
+    AT91_REG EMAC_RBQP;       /* Receive Buffer Queue Pointer */
+    AT91_REG EMAC_TBQP;       /* Transmit Buffer Queue Pointer */
+    AT91_REG EMAC_RSR;        /* Receive Status Register */
+    AT91_REG EMAC_ISR;        /* Interrupt Status Register */
+    AT91_REG EMAC_IER;        /* Interrupt Enable Register */
+    AT91_REG EMAC_IDR;        /* Interrupt Disable Register */
+    AT91_REG EMAC_IMR;        /* Interrupt Mask Register */
+    AT91_REG EMAC_MAN;        /* PHY Maintenance Register */
+    AT91_REG EMAC_PTR;        /* Pause Time Register */
+    AT91_REG EMAC_PFR;        /* Pause Frames received Register */
+    AT91_REG EMAC_FTO;        /* Frames Transmitted OK Register */
+    AT91_REG EMAC_SCF;        /* Single Collision Frame Register */
+    AT91_REG EMAC_MCF;        /* Multiple Collision Frame Register */
+    AT91_REG EMAC_FRO;        /* Frames Received OK Register */
+    AT91_REG EMAC_FCSE;       /* Frame Check Sequence Error Register */
+    AT91_REG EMAC_ALE;        /* Alignment Error Register */
+    AT91_REG EMAC_DTF;        /* Deferred Transmission Frame Register */
+    AT91_REG EMAC_LCOL;       /* Late Collision Register */
+    AT91_REG EMAC_ECOL;       /* Excessive Collision Register */
+    AT91_REG EMAC_TUND;       /* Transmit Underrun Error Register */
+    AT91_REG EMAC_CSE;        /* Carrier Sense Error Register */
+    AT91_REG EMAC_RRE;        /* Receive Ressource Error Register */
+    AT91_REG EMAC_ROV;        /* Receive Overrun Errors Register */
+    AT91_REG EMAC_RSE;        /* Receive Symbol Errors Register */
+    AT91_REG EMAC_ELE;        /* Excessive Length Errors Register */
+    AT91_REG EMAC_RJA;        /* Receive Jabbers Register */
+    AT91_REG EMAC_USF;        /* Undersize Frames Register */
+    AT91_REG EMAC_STE;        /* SQE Test Error Register */
+    AT91_REG EMAC_RLE;        /* Receive Length Field Mismatch Register */
+    AT91_REG EMAC_TPF;        /* Transmitted Pause Frames Register */
+    AT91_REG EMAC_HRB;        /* Hash Address Bottom[31:0] */
+    AT91_REG EMAC_HRT;        /* Hash Address Top[63:32] */
+    AT91_REG EMAC_SA1L;       /* Specific Address 1 Bottom, First 4 bytes */
+    AT91_REG EMAC_SA1H;       /* Specific Address 1 Top, Last 2 bytes */
+    AT91_REG EMAC_SA2L;       /* Specific Address 2 Bottom, First 4 bytes */
+    AT91_REG EMAC_SA2H;       /* Specific Address 2 Top, Last 2 bytes */
+    AT91_REG EMAC_SA3L;       /* Specific Address 3 Bottom, First 4 bytes */
+    AT91_REG EMAC_SA3H;       /* Specific Address 3 Top, Last 2 bytes */
+    AT91_REG EMAC_SA4L;       /* Specific Address 4 Bottom, First 4 bytes */
+    AT91_REG EMAC_SA4H;       /* Specific Address 4 Top, Last 2 bytes */
+    AT91_REG EMAC_TID;        /* Type ID Checking Register */
+    AT91_REG EMAC_TPQ;        /* Transmit Pause Quantum Register */
+    AT91_REG EMAC_USRIO;      /* USER Input/Output Register */
+    AT91_REG EMAC_WOL;        /* Wake On LAN Register */
+    AT91_REG Reserved1[ 13 ]; /* */
+    AT91_REG EMAC_REV;        /* Revision Register */
+} AT91S_EMAC, * AT91PS_EMAC;
 
-// -------- EMAC_NCR : (EMAC Offset: 0x0)  --------
-#define AT91C_EMAC_LB         ((unsigned int) 0x1 <<  0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
-#define AT91C_EMAC_LLB        ((unsigned int) 0x1 <<  1) // (EMAC) Loopback local.
-#define AT91C_EMAC_RE         ((unsigned int) 0x1 <<  2) // (EMAC) Receive enable.
-#define AT91C_EMAC_TE         ((unsigned int) 0x1 <<  3) // (EMAC) Transmit enable.
-#define AT91C_EMAC_MPE        ((unsigned int) 0x1 <<  4) // (EMAC) Management port enable.
-#define AT91C_EMAC_CLRSTAT    ((unsigned int) 0x1 <<  5) // (EMAC) Clear statistics registers.
-#define AT91C_EMAC_INCSTAT    ((unsigned int) 0x1 <<  6) // (EMAC) Increment statistics registers.
-#define AT91C_EMAC_WESTAT     ((unsigned int) 0x1 <<  7) // (EMAC) Write enable for statistics registers.
-#define AT91C_EMAC_BP         ((unsigned int) 0x1 <<  8) // (EMAC) Back pressure.
-#define AT91C_EMAC_TSTART     ((unsigned int) 0x1 <<  9) // (EMAC) Start Transmission.
-#define AT91C_EMAC_THALT      ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt.
-#define AT91C_EMAC_TPFR       ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame
-#define AT91C_EMAC_TZQ        ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame
-// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register --------
-#define AT91C_EMAC_SPD        ((unsigned int) 0x1 <<  0) // (EMAC) Speed.
-#define AT91C_EMAC_FD         ((unsigned int) 0x1 <<  1) // (EMAC) Full duplex.
-#define AT91C_EMAC_JFRAME     ((unsigned int) 0x1 <<  3) // (EMAC) Jumbo Frames.
-#define AT91C_EMAC_CAF        ((unsigned int) 0x1 <<  4) // (EMAC) Copy all frames.
-#define AT91C_EMAC_NBC        ((unsigned int) 0x1 <<  5) // (EMAC) No broadcast.
-#define AT91C_EMAC_MTI        ((unsigned int) 0x1 <<  6) // (EMAC) Multicast hash event enable
-#define AT91C_EMAC_UNI        ((unsigned int) 0x1 <<  7) // (EMAC) Unicast hash enable.
-#define AT91C_EMAC_BIG        ((unsigned int) 0x1 <<  8) // (EMAC) Receive 1522 bytes.
-#define AT91C_EMAC_EAE        ((unsigned int) 0x1 <<  9) // (EMAC) External address match enable.
-#define AT91C_EMAC_CLK        ((unsigned int) 0x3 << 10) // (EMAC)
-#define     AT91C_EMAC_CLK_HCLK_8               ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8
-#define     AT91C_EMAC_CLK_HCLK_16              ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16
-#define     AT91C_EMAC_CLK_HCLK_32              ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32
-#define     AT91C_EMAC_CLK_HCLK_64              ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64
-#define AT91C_EMAC_RTY        ((unsigned int) 0x1 << 12) // (EMAC)
-#define AT91C_EMAC_PAE        ((unsigned int) 0x1 << 13) // (EMAC)
-#define AT91C_EMAC_RBOF       ((unsigned int) 0x3 << 14) // (EMAC)
-#define     AT91C_EMAC_RBOF_OFFSET_0             ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer
-#define     AT91C_EMAC_RBOF_OFFSET_1             ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer
-#define     AT91C_EMAC_RBOF_OFFSET_2             ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
-#define     AT91C_EMAC_RBOF_OFFSET_3             ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
-#define AT91C_EMAC_RLCE       ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable
-#define AT91C_EMAC_DRFCS      ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS
-#define AT91C_EMAC_EFRHD      ((unsigned int) 0x1 << 18) // (EMAC)
-#define AT91C_EMAC_IRXFCS     ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS
-// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register --------
-#define AT91C_EMAC_LINKR      ((unsigned int) 0x1 <<  0) // (EMAC)
-#define AT91C_EMAC_MDIO       ((unsigned int) 0x1 <<  1) // (EMAC)
-#define AT91C_EMAC_IDLE       ((unsigned int) 0x1 <<  2) // (EMAC)
-// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register --------
-#define AT91C_EMAC_UBR        ((unsigned int) 0x1 <<  0) // (EMAC)
-#define AT91C_EMAC_COL        ((unsigned int) 0x1 <<  1) // (EMAC)
-#define AT91C_EMAC_RLES       ((unsigned int) 0x1 <<  2) // (EMAC)
-#define AT91C_EMAC_TGO        ((unsigned int) 0x1 <<  3) // (EMAC) Transmit Go
-#define AT91C_EMAC_BEX        ((unsigned int) 0x1 <<  4) // (EMAC) Buffers exhausted mid frame
-#define AT91C_EMAC_COMP       ((unsigned int) 0x1 <<  5) // (EMAC)
-#define AT91C_EMAC_UND        ((unsigned int) 0x1 <<  6) // (EMAC)
-// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register --------
-#define AT91C_EMAC_BNA        ((unsigned int) 0x1 <<  0) // (EMAC)
-#define AT91C_EMAC_REC        ((unsigned int) 0x1 <<  1) // (EMAC)
-#define AT91C_EMAC_OVR        ((unsigned int) 0x1 <<  2) // (EMAC)
-// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register --------
-#define AT91C_EMAC_MFD        ((unsigned int) 0x1 <<  0) // (EMAC)
-#define AT91C_EMAC_RCOMP      ((unsigned int) 0x1 <<  1) // (EMAC)
-#define AT91C_EMAC_RXUBR      ((unsigned int) 0x1 <<  2) // (EMAC)
-#define AT91C_EMAC_TXUBR      ((unsigned int) 0x1 <<  3) // (EMAC)
-#define AT91C_EMAC_TUNDR      ((unsigned int) 0x1 <<  4) // (EMAC)
-#define AT91C_EMAC_RLEX       ((unsigned int) 0x1 <<  5) // (EMAC)
-#define AT91C_EMAC_TXERR      ((unsigned int) 0x1 <<  6) // (EMAC)
-#define AT91C_EMAC_TCOMP      ((unsigned int) 0x1 <<  7) // (EMAC)
-#define AT91C_EMAC_LINK       ((unsigned int) 0x1 <<  9) // (EMAC)
-#define AT91C_EMAC_ROVR       ((unsigned int) 0x1 << 10) // (EMAC)
-#define AT91C_EMAC_HRESP      ((unsigned int) 0x1 << 11) // (EMAC)
-#define AT91C_EMAC_PFRE       ((unsigned int) 0x1 << 12) // (EMAC)
-#define AT91C_EMAC_PTZ        ((unsigned int) 0x1 << 13) // (EMAC)
-// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register --------
-// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register --------
-// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register --------
-// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register --------
-#define AT91C_EMAC_DATA       ((unsigned int) 0xFFFF <<  0) // (EMAC)
-#define AT91C_EMAC_CODE       ((unsigned int) 0x3 << 16) // (EMAC)
-#define AT91C_EMAC_REGA       ((unsigned int) 0x1F << 18) // (EMAC)
-#define AT91C_EMAC_PHYA       ((unsigned int) 0x1F << 23) // (EMAC)
-#define AT91C_EMAC_RW         ((unsigned int) 0x3 << 28) // (EMAC)
-#define AT91C_EMAC_SOF        ((unsigned int) 0x3 << 30) // (EMAC)
-// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register --------
-#define AT91C_EMAC_RMII       ((unsigned int) 0x1 <<  0) // (EMAC) Reduce MII
-// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register --------
-#define AT91C_EMAC_IP         ((unsigned int) 0xFFFF <<  0) // (EMAC) ARP request IP address
-#define AT91C_EMAC_MAG        ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable
-#define AT91C_EMAC_ARP        ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable
-#define AT91C_EMAC_SA1        ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable
-// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register --------
-#define AT91C_EMAC_REVREF     ((unsigned int) 0xFFFF <<  0) // (EMAC)
-#define AT91C_EMAC_PARTREF    ((unsigned int) 0xFFFF << 16) // (EMAC)
+/* -------- EMAC_NCR : (EMAC Offset: 0x0)  -------- */
+#define AT91C_EMAC_LB                   ( ( unsigned int ) 0x1 << 0 )  /* (EMAC) Loopback. Optional. When set, loopback signal is at high level. */
+#define AT91C_EMAC_LLB                  ( ( unsigned int ) 0x1 << 1 )  /* (EMAC) Loopback local. */
+#define AT91C_EMAC_RE                   ( ( unsigned int ) 0x1 << 2 )  /* (EMAC) Receive enable. */
+#define AT91C_EMAC_TE                   ( ( unsigned int ) 0x1 << 3 )  /* (EMAC) Transmit enable. */
+#define AT91C_EMAC_MPE                  ( ( unsigned int ) 0x1 << 4 )  /* (EMAC) Management port enable. */
+#define AT91C_EMAC_CLRSTAT              ( ( unsigned int ) 0x1 << 5 )  /* (EMAC) Clear statistics registers. */
+#define AT91C_EMAC_INCSTAT              ( ( unsigned int ) 0x1 << 6 )  /* (EMAC) Increment statistics registers. */
+#define AT91C_EMAC_WESTAT               ( ( unsigned int ) 0x1 << 7 )  /* (EMAC) Write enable for statistics registers. */
+#define AT91C_EMAC_BP                   ( ( unsigned int ) 0x1 << 8 )  /* (EMAC) Back pressure. */
+#define AT91C_EMAC_TSTART               ( ( unsigned int ) 0x1 << 9 )  /* (EMAC) Start Transmission. */
+#define AT91C_EMAC_THALT                ( ( unsigned int ) 0x1 << 10 ) /* (EMAC) Transmission Halt. */
+#define AT91C_EMAC_TPFR                 ( ( unsigned int ) 0x1 << 11 ) /* (EMAC) Transmit pause frame */
+#define AT91C_EMAC_TZQ                  ( ( unsigned int ) 0x1 << 12 ) /* (EMAC) Transmit zero quantum pause frame */
+/* -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- */
+#define AT91C_EMAC_SPD                  ( ( unsigned int ) 0x1 << 0 )  /* (EMAC) Speed. */
+#define AT91C_EMAC_FD                   ( ( unsigned int ) 0x1 << 1 )  /* (EMAC) Full duplex. */
+#define AT91C_EMAC_JFRAME               ( ( unsigned int ) 0x1 << 3 )  /* (EMAC) Jumbo Frames. */
+#define AT91C_EMAC_CAF                  ( ( unsigned int ) 0x1 << 4 )  /* (EMAC) Copy all frames. */
+#define AT91C_EMAC_NBC                  ( ( unsigned int ) 0x1 << 5 )  /* (EMAC) No broadcast. */
+#define AT91C_EMAC_MTI                  ( ( unsigned int ) 0x1 << 6 )  /* (EMAC) Multicast hash event enable */
+#define AT91C_EMAC_UNI                  ( ( unsigned int ) 0x1 << 7 )  /* (EMAC) Unicast hash enable. */
+#define AT91C_EMAC_BIG                  ( ( unsigned int ) 0x1 << 8 )  /* (EMAC) Receive 1522 bytes. */
+#define AT91C_EMAC_EAE                  ( ( unsigned int ) 0x1 << 9 )  /* (EMAC) External address match enable. */
+#define AT91C_EMAC_CLK                  ( ( unsigned int ) 0x3 << 10 ) /* (EMAC) */
+#define     AT91C_EMAC_CLK_HCLK_8       ( ( unsigned int ) 0x0 << 10 ) /* (EMAC) HCLK divided by 8 */
+#define     AT91C_EMAC_CLK_HCLK_16      ( ( unsigned int ) 0x1 << 10 ) /* (EMAC) HCLK divided by 16 */
+#define     AT91C_EMAC_CLK_HCLK_32      ( ( unsigned int ) 0x2 << 10 ) /* (EMAC) HCLK divided by 32 */
+#define     AT91C_EMAC_CLK_HCLK_64      ( ( unsigned int ) 0x3 << 10 ) /* (EMAC) HCLK divided by 64 */
+#define AT91C_EMAC_RTY                  ( ( unsigned int ) 0x1 << 12 ) /* (EMAC) */
+#define AT91C_EMAC_PAE                  ( ( unsigned int ) 0x1 << 13 ) /* (EMAC) */
+#define AT91C_EMAC_RBOF                 ( ( unsigned int ) 0x3 << 14 ) /* (EMAC) */
+#define     AT91C_EMAC_RBOF_OFFSET_0    ( ( unsigned int ) 0x0 << 14 ) /* (EMAC) no offset from start of receive buffer */
+#define     AT91C_EMAC_RBOF_OFFSET_1    ( ( unsigned int ) 0x1 << 14 ) /* (EMAC) one byte offset from start of receive buffer */
+#define     AT91C_EMAC_RBOF_OFFSET_2    ( ( unsigned int ) 0x2 << 14 ) /* (EMAC) two bytes offset from start of receive buffer */
+#define     AT91C_EMAC_RBOF_OFFSET_3    ( ( unsigned int ) 0x3 << 14 ) /* (EMAC) three bytes offset from start of receive buffer */
+#define AT91C_EMAC_RLCE                 ( ( unsigned int ) 0x1 << 16 ) /* (EMAC) Receive Length field Checking Enable */
+#define AT91C_EMAC_DRFCS                ( ( unsigned int ) 0x1 << 17 ) /* (EMAC) Discard Receive FCS */
+#define AT91C_EMAC_EFRHD                ( ( unsigned int ) 0x1 << 18 ) /* (EMAC) */
+#define AT91C_EMAC_IRXFCS               ( ( unsigned int ) 0x1 << 19 ) /* (EMAC) Ignore RX FCS */
+/* -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- */
+#define AT91C_EMAC_LINKR                ( ( unsigned int ) 0x1 << 0 )  /* (EMAC) */
+#define AT91C_EMAC_MDIO                 ( ( unsigned int ) 0x1 << 1 )  /* (EMAC) */
+#define AT91C_EMAC_IDLE                 ( ( unsigned int ) 0x1 << 2 )  /* (EMAC) */
+/* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- */
+#define AT91C_EMAC_UBR                  ( ( unsigned int ) 0x1 << 0 )  /* (EMAC) */
+#define AT91C_EMAC_COL                  ( ( unsigned int ) 0x1 << 1 )  /* (EMAC) */
+#define AT91C_EMAC_RLES                 ( ( unsigned int ) 0x1 << 2 )  /* (EMAC) */
+#define AT91C_EMAC_TGO                  ( ( unsigned int ) 0x1 << 3 )  /* (EMAC) Transmit Go */
+#define AT91C_EMAC_BEX                  ( ( unsigned int ) 0x1 << 4 )  /* (EMAC) Buffers exhausted mid frame */
+#define AT91C_EMAC_COMP                 ( ( unsigned int ) 0x1 << 5 )  /* (EMAC) */
+#define AT91C_EMAC_UND                  ( ( unsigned int ) 0x1 << 6 )  /* (EMAC) */
+/* -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- */
+#define AT91C_EMAC_BNA                  ( ( unsigned int ) 0x1 << 0 )  /* (EMAC) */
+#define AT91C_EMAC_REC                  ( ( unsigned int ) 0x1 << 1 )  /* (EMAC) */
+#define AT91C_EMAC_OVR                  ( ( unsigned int ) 0x1 << 2 )  /* (EMAC) */
+/* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- */
+#define AT91C_EMAC_MFD                  ( ( unsigned int ) 0x1 << 0 )  /* (EMAC) */
+#define AT91C_EMAC_RCOMP                ( ( unsigned int ) 0x1 << 1 )  /* (EMAC) */
+#define AT91C_EMAC_RXUBR                ( ( unsigned int ) 0x1 << 2 )  /* (EMAC) */
+#define AT91C_EMAC_TXUBR                ( ( unsigned int ) 0x1 << 3 )  /* (EMAC) */
+#define AT91C_EMAC_TUNDR                ( ( unsigned int ) 0x1 << 4 )  /* (EMAC) */
+#define AT91C_EMAC_RLEX                 ( ( unsigned int ) 0x1 << 5 )  /* (EMAC) */
+#define AT91C_EMAC_TXERR                ( ( unsigned int ) 0x1 << 6 )  /* (EMAC) */
+#define AT91C_EMAC_TCOMP                ( ( unsigned int ) 0x1 << 7 )  /* (EMAC) */
+#define AT91C_EMAC_LINK                 ( ( unsigned int ) 0x1 << 9 )  /* (EMAC) */
+#define AT91C_EMAC_ROVR                 ( ( unsigned int ) 0x1 << 10 ) /* (EMAC) */
+#define AT91C_EMAC_HRESP                ( ( unsigned int ) 0x1 << 11 ) /* (EMAC) */
+#define AT91C_EMAC_PFRE                 ( ( unsigned int ) 0x1 << 12 ) /* (EMAC) */
+#define AT91C_EMAC_PTZ                  ( ( unsigned int ) 0x1 << 13 ) /* (EMAC) */
+/* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- */
+/* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- */
+/* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */
+/* -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- */
+#define AT91C_EMAC_DATA       ( ( unsigned int ) 0xFFFF << 0 )  /* (EMAC) */
+#define AT91C_EMAC_CODE       ( ( unsigned int ) 0x3 << 16 )    /* (EMAC) */
+#define AT91C_EMAC_REGA       ( ( unsigned int ) 0x1F << 18 )   /* (EMAC) */
+#define AT91C_EMAC_PHYA       ( ( unsigned int ) 0x1F << 23 )   /* (EMAC) */
+#define AT91C_EMAC_RW         ( ( unsigned int ) 0x3 << 28 )    /* (EMAC) */
+#define AT91C_EMAC_SOF        ( ( unsigned int ) 0x3 << 30 )    /* (EMAC) */
+/* -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- */
+#define AT91C_EMAC_RMII       ( ( unsigned int ) 0x1 << 0 )     /* (EMAC) Reduce MII */
+/* -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- */
+#define AT91C_EMAC_IP         ( ( unsigned int ) 0xFFFF << 0 )  /* (EMAC) ARP request IP address */
+#define AT91C_EMAC_MAG        ( ( unsigned int ) 0x1 << 16 )    /* (EMAC) Magic packet event enable */
+#define AT91C_EMAC_ARP        ( ( unsigned int ) 0x1 << 17 )    /* (EMAC) ARP request event enable */
+#define AT91C_EMAC_SA1        ( ( unsigned int ) 0x1 << 18 )    /* (EMAC) Specific address register 1 event enable */
+/* -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- */
+#define AT91C_EMAC_REVREF     ( ( unsigned int ) 0xFFFF << 0 )  /* (EMAC) */
+#define AT91C_EMAC_PARTREF    ( ( unsigned int ) 0xFFFF << 16 ) /* (EMAC) */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
-// *****************************************************************************
-typedef struct _AT91S_ADC {
-    AT91_REG     ADC_CR;    // ADC Control Register
-    AT91_REG     ADC_MR;    // ADC Mode Register
-    AT91_REG     Reserved0[2];  //
-    AT91_REG     ADC_CHER;  // ADC Channel Enable Register
-    AT91_REG     ADC_CHDR;  // ADC Channel Disable Register
-    AT91_REG     ADC_CHSR;  // ADC Channel Status Register
-    AT91_REG     ADC_SR;    // ADC Status Register
-    AT91_REG     ADC_LCDR;  // ADC Last Converted Data Register
-    AT91_REG     ADC_IER;   // ADC Interrupt Enable Register
-    AT91_REG     ADC_IDR;   // ADC Interrupt Disable Register
-    AT91_REG     ADC_IMR;   // ADC Interrupt Mask Register
-    AT91_REG     ADC_CDR0;  // ADC Channel Data Register 0
-    AT91_REG     ADC_CDR1;  // ADC Channel Data Register 1
-    AT91_REG     ADC_CDR2;  // ADC Channel Data Register 2
-    AT91_REG     ADC_CDR3;  // ADC Channel Data Register 3
-    AT91_REG     ADC_CDR4;  // ADC Channel Data Register 4
-    AT91_REG     ADC_CDR5;  // ADC Channel Data Register 5
-    AT91_REG     ADC_CDR6;  // ADC Channel Data Register 6
-    AT91_REG     ADC_CDR7;  // ADC Channel Data Register 7
-    AT91_REG     Reserved1[44];     //
-    AT91_REG     ADC_RPR;   // Receive Pointer Register
-    AT91_REG     ADC_RCR;   // Receive Counter Register
-    AT91_REG     ADC_TPR;   // Transmit Pointer Register
-    AT91_REG     ADC_TCR;   // Transmit Counter Register
-    AT91_REG     ADC_RNPR;  // Receive Next Pointer Register
-    AT91_REG     ADC_RNCR;  // Receive Next Counter Register
-    AT91_REG     ADC_TNPR;  // Transmit Next Pointer Register
-    AT91_REG     ADC_TNCR;  // Transmit Next Counter Register
-    AT91_REG     ADC_PTCR;  // PDC Transfer Control Register
-    AT91_REG     ADC_PTSR;  // PDC Transfer Status Register
-} AT91S_ADC, *AT91PS_ADC;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor */
+/* ***************************************************************************** */
+typedef struct _AT91S_ADC
+{
+    AT91_REG ADC_CR;          /* ADC Control Register */
+    AT91_REG ADC_MR;          /* ADC Mode Register */
+    AT91_REG Reserved0[ 2 ];  /* */
+    AT91_REG ADC_CHER;        /* ADC Channel Enable Register */
+    AT91_REG ADC_CHDR;        /* ADC Channel Disable Register */
+    AT91_REG ADC_CHSR;        /* ADC Channel Status Register */
+    AT91_REG ADC_SR;          /* ADC Status Register */
+    AT91_REG ADC_LCDR;        /* ADC Last Converted Data Register */
+    AT91_REG ADC_IER;         /* ADC Interrupt Enable Register */
+    AT91_REG ADC_IDR;         /* ADC Interrupt Disable Register */
+    AT91_REG ADC_IMR;         /* ADC Interrupt Mask Register */
+    AT91_REG ADC_CDR0;        /* ADC Channel Data Register 0 */
+    AT91_REG ADC_CDR1;        /* ADC Channel Data Register 1 */
+    AT91_REG ADC_CDR2;        /* ADC Channel Data Register 2 */
+    AT91_REG ADC_CDR3;        /* ADC Channel Data Register 3 */
+    AT91_REG ADC_CDR4;        /* ADC Channel Data Register 4 */
+    AT91_REG ADC_CDR5;        /* ADC Channel Data Register 5 */
+    AT91_REG ADC_CDR6;        /* ADC Channel Data Register 6 */
+    AT91_REG ADC_CDR7;        /* ADC Channel Data Register 7 */
+    AT91_REG Reserved1[ 44 ]; /* */
+    AT91_REG ADC_RPR;         /* Receive Pointer Register */
+    AT91_REG ADC_RCR;         /* Receive Counter Register */
+    AT91_REG ADC_TPR;         /* Transmit Pointer Register */
+    AT91_REG ADC_TCR;         /* Transmit Counter Register */
+    AT91_REG ADC_RNPR;        /* Receive Next Pointer Register */
+    AT91_REG ADC_RNCR;        /* Receive Next Counter Register */
+    AT91_REG ADC_TNPR;        /* Transmit Next Pointer Register */
+    AT91_REG ADC_TNCR;        /* Transmit Next Counter Register */
+    AT91_REG ADC_PTCR;        /* PDC Transfer Control Register */
+    AT91_REG ADC_PTSR;        /* PDC Transfer Status Register */
+} AT91S_ADC, * AT91PS_ADC;
 
-// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
-#define AT91C_ADC_SWRST       ((unsigned int) 0x1 <<  0) // (ADC) Software Reset
-#define AT91C_ADC_START       ((unsigned int) 0x1 <<  1) // (ADC) Start Conversion
-// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
-#define AT91C_ADC_TRGEN       ((unsigned int) 0x1 <<  0) // (ADC) Trigger Enable
-#define     AT91C_ADC_TRGEN_DIS                  ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
-#define     AT91C_ADC_TRGEN_EN                   ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
-#define AT91C_ADC_TRGSEL      ((unsigned int) 0x7 <<  1) // (ADC) Trigger Selection
-#define     AT91C_ADC_TRGSEL_TIOA0                ((unsigned int) 0x0 <<  1) // (ADC) Selected TRGSEL = TIAO0
-#define     AT91C_ADC_TRGSEL_TIOA1                ((unsigned int) 0x1 <<  1) // (ADC) Selected TRGSEL = TIAO1
-#define     AT91C_ADC_TRGSEL_TIOA2                ((unsigned int) 0x2 <<  1) // (ADC) Selected TRGSEL = TIAO2
-#define     AT91C_ADC_TRGSEL_TIOA3                ((unsigned int) 0x3 <<  1) // (ADC) Selected TRGSEL = TIAO3
-#define     AT91C_ADC_TRGSEL_TIOA4                ((unsigned int) 0x4 <<  1) // (ADC) Selected TRGSEL = TIAO4
-#define     AT91C_ADC_TRGSEL_TIOA5                ((unsigned int) 0x5 <<  1) // (ADC) Selected TRGSEL = TIAO5
-#define     AT91C_ADC_TRGSEL_EXT                  ((unsigned int) 0x6 <<  1) // (ADC) Selected TRGSEL = External Trigger
-#define AT91C_ADC_LOWRES      ((unsigned int) 0x1 <<  4) // (ADC) Resolution.
-#define     AT91C_ADC_LOWRES_10_BIT               ((unsigned int) 0x0 <<  4) // (ADC) 10-bit resolution
-#define     AT91C_ADC_LOWRES_8_BIT                ((unsigned int) 0x1 <<  4) // (ADC) 8-bit resolution
-#define AT91C_ADC_SLEEP       ((unsigned int) 0x1 <<  5) // (ADC) Sleep Mode
-#define     AT91C_ADC_SLEEP_NORMAL_MODE          ((unsigned int) 0x0 <<  5) // (ADC) Normal Mode
-#define     AT91C_ADC_SLEEP_MODE                 ((unsigned int) 0x1 <<  5) // (ADC) Sleep Mode
-#define AT91C_ADC_PRESCAL     ((unsigned int) 0x3F <<  8) // (ADC) Prescaler rate selection
-#define AT91C_ADC_STARTUP     ((unsigned int) 0x1F << 16) // (ADC) Startup Time
-#define AT91C_ADC_SHTIM       ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time
-// --------     ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
-#define AT91C_ADC_CH0         ((unsigned int) 0x1 <<  0) // (ADC) Channel 0
-#define AT91C_ADC_CH1         ((unsigned int) 0x1 <<  1) // (ADC) Channel 1
-#define AT91C_ADC_CH2         ((unsigned int) 0x1 <<  2) // (ADC) Channel 2
-#define AT91C_ADC_CH3         ((unsigned int) 0x1 <<  3) // (ADC) Channel 3
-#define AT91C_ADC_CH4         ((unsigned int) 0x1 <<  4) // (ADC) Channel 4
-#define AT91C_ADC_CH5         ((unsigned int) 0x1 <<  5) // (ADC) Channel 5
-#define AT91C_ADC_CH6         ((unsigned int) 0x1 <<  6) // (ADC) Channel 6
-#define AT91C_ADC_CH7         ((unsigned int) 0x1 <<  7) // (ADC) Channel 7
-// --------     ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
-// --------     ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
-// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
-#define AT91C_ADC_EOC0        ((unsigned int) 0x1 <<  0) // (ADC) End of Conversion
-#define AT91C_ADC_EOC1        ((unsigned int) 0x1 <<  1) // (ADC) End of Conversion
-#define AT91C_ADC_EOC2        ((unsigned int) 0x1 <<  2) // (ADC) End of Conversion
-#define AT91C_ADC_EOC3        ((unsigned int) 0x1 <<  3) // (ADC) End of Conversion
-#define AT91C_ADC_EOC4        ((unsigned int) 0x1 <<  4) // (ADC) End of Conversion
-#define AT91C_ADC_EOC5        ((unsigned int) 0x1 <<  5) // (ADC) End of Conversion
-#define AT91C_ADC_EOC6        ((unsigned int) 0x1 <<  6) // (ADC) End of Conversion
-#define AT91C_ADC_EOC7        ((unsigned int) 0x1 <<  7) // (ADC) End of Conversion
-#define AT91C_ADC_OVRE0       ((unsigned int) 0x1 <<  8) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE1       ((unsigned int) 0x1 <<  9) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE2       ((unsigned int) 0x1 << 10) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE3       ((unsigned int) 0x1 << 11) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE4       ((unsigned int) 0x1 << 12) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE5       ((unsigned int) 0x1 << 13) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE6       ((unsigned int) 0x1 << 14) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE7       ((unsigned int) 0x1 << 15) // (ADC) Overrun Error
-#define AT91C_ADC_DRDY        ((unsigned int) 0x1 << 16) // (ADC) Data Ready
-#define AT91C_ADC_GOVRE       ((unsigned int) 0x1 << 17) // (ADC) General Overrun
-#define AT91C_ADC_ENDRX       ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer
-#define AT91C_ADC_RXBUFF      ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt
-// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
-#define AT91C_ADC_LDATA       ((unsigned int) 0x3FF <<  0) // (ADC) Last Data Converted
-// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
-// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
-// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
-// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
-#define AT91C_ADC_DATA        ((unsigned int) 0x3FF <<  0) // (ADC) Converted Data
-// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
-// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
-// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
-// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
-// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
-// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
-// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
+/* -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- */
+#define AT91C_ADC_SWRST                    ( ( unsigned int ) 0x1 << 0 )   /* (ADC) Software Reset */
+#define AT91C_ADC_START                    ( ( unsigned int ) 0x1 << 1 )   /* (ADC) Start Conversion */
+/* -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- */
+#define AT91C_ADC_TRGEN                    ( ( unsigned int ) 0x1 << 0 )   /* (ADC) Trigger Enable */
+#define     AT91C_ADC_TRGEN_DIS            ( ( unsigned int ) 0x0 )        /* (ADC) Hardware triggers are disabled. Starting a conversion is only possible by software */
+#define     AT91C_ADC_TRGEN_EN             ( ( unsigned int ) 0x1 )        /* (ADC) Hardware trigger selected by TRGSEL field is enabled. */
+#define AT91C_ADC_TRGSEL                   ( ( unsigned int ) 0x7 << 1 )   /* (ADC) Trigger Selection */
+#define     AT91C_ADC_TRGSEL_TIOA0         ( ( unsigned int ) 0x0 << 1 )   /* (ADC) Selected TRGSEL = TIAO0 */
+#define     AT91C_ADC_TRGSEL_TIOA1         ( ( unsigned int ) 0x1 << 1 )   /* (ADC) Selected TRGSEL = TIAO1 */
+#define     AT91C_ADC_TRGSEL_TIOA2         ( ( unsigned int ) 0x2 << 1 )   /* (ADC) Selected TRGSEL = TIAO2 */
+#define     AT91C_ADC_TRGSEL_TIOA3         ( ( unsigned int ) 0x3 << 1 )   /* (ADC) Selected TRGSEL = TIAO3 */
+#define     AT91C_ADC_TRGSEL_TIOA4         ( ( unsigned int ) 0x4 << 1 )   /* (ADC) Selected TRGSEL = TIAO4 */
+#define     AT91C_ADC_TRGSEL_TIOA5         ( ( unsigned int ) 0x5 << 1 )   /* (ADC) Selected TRGSEL = TIAO5 */
+#define     AT91C_ADC_TRGSEL_EXT           ( ( unsigned int ) 0x6 << 1 )   /* (ADC) Selected TRGSEL = External Trigger */
+#define AT91C_ADC_LOWRES                   ( ( unsigned int ) 0x1 << 4 )   /* (ADC) Resolution. */
+#define     AT91C_ADC_LOWRES_10_BIT        ( ( unsigned int ) 0x0 << 4 )   /* (ADC) 10-bit resolution */
+#define     AT91C_ADC_LOWRES_8_BIT         ( ( unsigned int ) 0x1 << 4 )   /* (ADC) 8-bit resolution */
+#define AT91C_ADC_SLEEP                    ( ( unsigned int ) 0x1 << 5 )   /* (ADC) Sleep Mode */
+#define     AT91C_ADC_SLEEP_NORMAL_MODE    ( ( unsigned int ) 0x0 << 5 )   /* (ADC) Normal Mode */
+#define     AT91C_ADC_SLEEP_MODE           ( ( unsigned int ) 0x1 << 5 )   /* (ADC) Sleep Mode */
+#define AT91C_ADC_PRESCAL                  ( ( unsigned int ) 0x3F << 8 )  /* (ADC) Prescaler rate selection */
+#define AT91C_ADC_STARTUP                  ( ( unsigned int ) 0x1F << 16 ) /* (ADC) Startup Time */
+#define AT91C_ADC_SHTIM                    ( ( unsigned int ) 0xF << 24 )  /* (ADC) Sample & Hold Time */
+/* --------     ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- */
+#define AT91C_ADC_CH0                      ( ( unsigned int ) 0x1 << 0 )   /* (ADC) Channel 0 */
+#define AT91C_ADC_CH1                      ( ( unsigned int ) 0x1 << 1 )   /* (ADC) Channel 1 */
+#define AT91C_ADC_CH2                      ( ( unsigned int ) 0x1 << 2 )   /* (ADC) Channel 2 */
+#define AT91C_ADC_CH3                      ( ( unsigned int ) 0x1 << 3 )   /* (ADC) Channel 3 */
+#define AT91C_ADC_CH4                      ( ( unsigned int ) 0x1 << 4 )   /* (ADC) Channel 4 */
+#define AT91C_ADC_CH5                      ( ( unsigned int ) 0x1 << 5 )   /* (ADC) Channel 5 */
+#define AT91C_ADC_CH6                      ( ( unsigned int ) 0x1 << 6 )   /* (ADC) Channel 6 */
+#define AT91C_ADC_CH7                      ( ( unsigned int ) 0x1 << 7 )   /* (ADC) Channel 7 */
+/* --------     ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- */
+/* --------     ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- */
+/* -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- */
+#define AT91C_ADC_EOC0      ( ( unsigned int ) 0x1 << 0 )   /* (ADC) End of Conversion */
+#define AT91C_ADC_EOC1      ( ( unsigned int ) 0x1 << 1 )   /* (ADC) End of Conversion */
+#define AT91C_ADC_EOC2      ( ( unsigned int ) 0x1 << 2 )   /* (ADC) End of Conversion */
+#define AT91C_ADC_EOC3      ( ( unsigned int ) 0x1 << 3 )   /* (ADC) End of Conversion */
+#define AT91C_ADC_EOC4      ( ( unsigned int ) 0x1 << 4 )   /* (ADC) End of Conversion */
+#define AT91C_ADC_EOC5      ( ( unsigned int ) 0x1 << 5 )   /* (ADC) End of Conversion */
+#define AT91C_ADC_EOC6      ( ( unsigned int ) 0x1 << 6 )   /* (ADC) End of Conversion */
+#define AT91C_ADC_EOC7      ( ( unsigned int ) 0x1 << 7 )   /* (ADC) End of Conversion */
+#define AT91C_ADC_OVRE0     ( ( unsigned int ) 0x1 << 8 )   /* (ADC) Overrun Error */
+#define AT91C_ADC_OVRE1     ( ( unsigned int ) 0x1 << 9 )   /* (ADC) Overrun Error */
+#define AT91C_ADC_OVRE2     ( ( unsigned int ) 0x1 << 10 )  /* (ADC) Overrun Error */
+#define AT91C_ADC_OVRE3     ( ( unsigned int ) 0x1 << 11 )  /* (ADC) Overrun Error */
+#define AT91C_ADC_OVRE4     ( ( unsigned int ) 0x1 << 12 )  /* (ADC) Overrun Error */
+#define AT91C_ADC_OVRE5     ( ( unsigned int ) 0x1 << 13 )  /* (ADC) Overrun Error */
+#define AT91C_ADC_OVRE6     ( ( unsigned int ) 0x1 << 14 )  /* (ADC) Overrun Error */
+#define AT91C_ADC_OVRE7     ( ( unsigned int ) 0x1 << 15 )  /* (ADC) Overrun Error */
+#define AT91C_ADC_DRDY      ( ( unsigned int ) 0x1 << 16 )  /* (ADC) Data Ready */
+#define AT91C_ADC_GOVRE     ( ( unsigned int ) 0x1 << 17 )  /* (ADC) General Overrun */
+#define AT91C_ADC_ENDRX     ( ( unsigned int ) 0x1 << 18 )  /* (ADC) End of Receiver Transfer */
+#define AT91C_ADC_RXBUFF    ( ( unsigned int ) 0x1 << 19 )  /* (ADC) RXBUFF Interrupt */
+/* -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- */
+#define AT91C_ADC_LDATA     ( ( unsigned int ) 0x3FF << 0 ) /* (ADC) Last Data Converted */
+/* -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- */
+/* -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- */
+/* -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- */
+/* -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- */
+#define AT91C_ADC_DATA    ( ( unsigned int ) 0x3FF << 0 )  /* (ADC) Converted Data */
+/* -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- */
+/* -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- */
+/* -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- */
+/* -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- */
+/* -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- */
+/* -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- */
+/* -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Advanced  Encryption Standard
-// *****************************************************************************
-typedef struct _AT91S_AES {
-    AT91_REG     AES_CR;    // Control Register
-    AT91_REG     AES_MR;    // Mode Register
-    AT91_REG     Reserved0[2];  //
-    AT91_REG     AES_IER;   // Interrupt Enable Register
-    AT91_REG     AES_IDR;   // Interrupt Disable Register
-    AT91_REG     AES_IMR;   // Interrupt Mask Register
-    AT91_REG     AES_ISR;   // Interrupt Status Register
-    AT91_REG     AES_KEYWxR[4];     // Key Word x Register
-    AT91_REG     Reserved1[4];  //
-    AT91_REG     AES_IDATAxR[4];    // Input Data x Register
-    AT91_REG     AES_ODATAxR[4];    // Output Data x Register
-    AT91_REG     AES_IVxR[4];   // Initialization Vector x Register
-    AT91_REG     Reserved2[35];     //
-    AT91_REG     AES_VR;    // AES Version Register
-    AT91_REG     AES_RPR;   // Receive Pointer Register
-    AT91_REG     AES_RCR;   // Receive Counter Register
-    AT91_REG     AES_TPR;   // Transmit Pointer Register
-    AT91_REG     AES_TCR;   // Transmit Counter Register
-    AT91_REG     AES_RNPR;  // Receive Next Pointer Register
-    AT91_REG     AES_RNCR;  // Receive Next Counter Register
-    AT91_REG     AES_TNPR;  // Transmit Next Pointer Register
-    AT91_REG     AES_TNCR;  // Transmit Next Counter Register
-    AT91_REG     AES_PTCR;  // PDC Transfer Control Register
-    AT91_REG     AES_PTSR;  // PDC Transfer Status Register
-} AT91S_AES, *AT91PS_AES;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Advanced  Encryption Standard */
+/* ***************************************************************************** */
+typedef struct _AT91S_AES
+{
+    AT91_REG AES_CR;           /* Control Register */
+    AT91_REG AES_MR;           /* Mode Register */
+    AT91_REG Reserved0[ 2 ];   /* */
+    AT91_REG AES_IER;          /* Interrupt Enable Register */
+    AT91_REG AES_IDR;          /* Interrupt Disable Register */
+    AT91_REG AES_IMR;          /* Interrupt Mask Register */
+    AT91_REG AES_ISR;          /* Interrupt Status Register */
+    AT91_REG AES_KEYWxR[ 4 ];  /* Key Word x Register */
+    AT91_REG Reserved1[ 4 ];   /* */
+    AT91_REG AES_IDATAxR[ 4 ]; /* Input Data x Register */
+    AT91_REG AES_ODATAxR[ 4 ]; /* Output Data x Register */
+    AT91_REG AES_IVxR[ 4 ];    /* Initialization Vector x Register */
+    AT91_REG Reserved2[ 35 ];  /* */
+    AT91_REG AES_VR;           /* AES Version Register */
+    AT91_REG AES_RPR;          /* Receive Pointer Register */
+    AT91_REG AES_RCR;          /* Receive Counter Register */
+    AT91_REG AES_TPR;          /* Transmit Pointer Register */
+    AT91_REG AES_TCR;          /* Transmit Counter Register */
+    AT91_REG AES_RNPR;         /* Receive Next Pointer Register */
+    AT91_REG AES_RNCR;         /* Receive Next Counter Register */
+    AT91_REG AES_TNPR;         /* Transmit Next Pointer Register */
+    AT91_REG AES_TNCR;         /* Transmit Next Counter Register */
+    AT91_REG AES_PTCR;         /* PDC Transfer Control Register */
+    AT91_REG AES_PTSR;         /* PDC Transfer Status Register */
+} AT91S_AES, * AT91PS_AES;
 
-// -------- AES_CR : (AES Offset: 0x0) Control Register --------
-#define AT91C_AES_START       ((unsigned int) 0x1 <<  0) // (AES) Starts Processing
-#define AT91C_AES_SWRST       ((unsigned int) 0x1 <<  8) // (AES) Software Reset
-#define AT91C_AES_LOADSEED    ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading
-// -------- AES_MR : (AES Offset: 0x4) Mode Register --------
-#define AT91C_AES_CIPHER      ((unsigned int) 0x1 <<  0) // (AES) Processing Mode
-#define AT91C_AES_PROCDLY     ((unsigned int) 0xF <<  4) // (AES) Processing Delay
-#define AT91C_AES_SMOD        ((unsigned int) 0x3 <<  8) // (AES) Start Mode
-#define     AT91C_AES_SMOD_MANUAL               ((unsigned int) 0x0 <<  8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.
-#define     AT91C_AES_SMOD_AUTO                 ((unsigned int) 0x1 <<  8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).
-#define     AT91C_AES_SMOD_PDC                  ((unsigned int) 0x2 <<  8) // (AES) PDC Mode (cf datasheet).
-#define AT91C_AES_OPMOD       ((unsigned int) 0x7 << 12) // (AES) Operation Mode
-#define     AT91C_AES_OPMOD_ECB                  ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode.
-#define     AT91C_AES_OPMOD_CBC                  ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode.
-#define     AT91C_AES_OPMOD_OFB                  ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode.
-#define     AT91C_AES_OPMOD_CFB                  ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode.
-#define     AT91C_AES_OPMOD_CTR                  ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode.
-#define AT91C_AES_LOD         ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode
-#define AT91C_AES_CFBS        ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size
-#define     AT91C_AES_CFBS_128_BIT              ((unsigned int) 0x0 << 16) // (AES) 128-bit.
-#define     AT91C_AES_CFBS_64_BIT               ((unsigned int) 0x1 << 16) // (AES) 64-bit.
-#define     AT91C_AES_CFBS_32_BIT               ((unsigned int) 0x2 << 16) // (AES) 32-bit.
-#define     AT91C_AES_CFBS_16_BIT               ((unsigned int) 0x3 << 16) // (AES) 16-bit.
-#define     AT91C_AES_CFBS_8_BIT                ((unsigned int) 0x4 << 16) // (AES) 8-bit.
-#define AT91C_AES_CKEY        ((unsigned int) 0xF << 20) // (AES) Countermeasure Key
-#define AT91C_AES_CTYPE       ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type
-#define     AT91C_AES_CTYPE_TYPE1_EN             ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled.
-#define     AT91C_AES_CTYPE_TYPE2_EN             ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled.
-#define     AT91C_AES_CTYPE_TYPE3_EN             ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled.
-#define     AT91C_AES_CTYPE_TYPE4_EN             ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled.
-#define     AT91C_AES_CTYPE_TYPE5_EN             ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled.
-// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register --------
-#define AT91C_AES_DATRDY      ((unsigned int) 0x1 <<  0) // (AES) DATRDY
-#define AT91C_AES_ENDRX       ((unsigned int) 0x1 <<  1) // (AES) PDC Read Buffer End
-#define AT91C_AES_ENDTX       ((unsigned int) 0x1 <<  2) // (AES) PDC Write Buffer End
-#define AT91C_AES_RXBUFF      ((unsigned int) 0x1 <<  3) // (AES) PDC Read Buffer Full
-#define AT91C_AES_TXBUFE      ((unsigned int) 0x1 <<  4) // (AES) PDC Write Buffer Empty
-#define AT91C_AES_URAD        ((unsigned int) 0x1 <<  8) // (AES) Unspecified Register Access Detection
-// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register --------
-// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register --------
-// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register --------
-#define AT91C_AES_URAT        ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status
-#define     AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode.
-#define     AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing.
-#define     AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing.
-#define     AT91C_AES_URAT_OUT_DAT_READ_SUBKEY  ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation.
-#define     AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation.
-#define     AT91C_AES_URAT_WO_REG_READ          ((unsigned int) 0x5 << 12) // (AES) Write-only register read access.
+/* -------- AES_CR : (AES Offset: 0x0) Control Register -------- */
+#define AT91C_AES_START                 ( ( unsigned int ) 0x1 << 0 )   /* (AES) Starts Processing */
+#define AT91C_AES_SWRST                 ( ( unsigned int ) 0x1 << 8 )   /* (AES) Software Reset */
+#define AT91C_AES_LOADSEED              ( ( unsigned int ) 0x1 << 16 )  /* (AES) Random Number Generator Seed Loading */
+/* -------- AES_MR : (AES Offset: 0x4) Mode Register -------- */
+#define AT91C_AES_CIPHER                ( ( unsigned int ) 0x1 << 0 )   /* (AES) Processing Mode */
+#define AT91C_AES_PROCDLY               ( ( unsigned int ) 0xF << 4 )   /* (AES) Processing Delay */
+#define AT91C_AES_SMOD                  ( ( unsigned int ) 0x3 << 8 )   /* (AES) Start Mode */
+#define     AT91C_AES_SMOD_MANUAL       ( ( unsigned int ) 0x0 << 8 )   /* (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. */
+#define     AT91C_AES_SMOD_AUTO         ( ( unsigned int ) 0x1 << 8 )   /* (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). */
+#define     AT91C_AES_SMOD_PDC          ( ( unsigned int ) 0x2 << 8 )   /* (AES) PDC Mode (cf datasheet). */
+#define AT91C_AES_OPMOD                 ( ( unsigned int ) 0x7 << 12 )  /* (AES) Operation Mode */
+#define     AT91C_AES_OPMOD_ECB         ( ( unsigned int ) 0x0 << 12 )  /* (AES) ECB Electronic CodeBook mode. */
+#define     AT91C_AES_OPMOD_CBC         ( ( unsigned int ) 0x1 << 12 )  /* (AES) CBC Cipher Block Chaining mode. */
+#define     AT91C_AES_OPMOD_OFB         ( ( unsigned int ) 0x2 << 12 )  /* (AES) OFB Output Feedback mode. */
+#define     AT91C_AES_OPMOD_CFB         ( ( unsigned int ) 0x3 << 12 )  /* (AES) CFB Cipher Feedback mode. */
+#define     AT91C_AES_OPMOD_CTR         ( ( unsigned int ) 0x4 << 12 )  /* (AES) CTR Counter mode. */
+#define AT91C_AES_LOD                   ( ( unsigned int ) 0x1 << 15 )  /* (AES) Last Output Data Mode */
+#define AT91C_AES_CFBS                  ( ( unsigned int ) 0x7 << 16 )  /* (AES) Cipher Feedback Data Size */
+#define     AT91C_AES_CFBS_128_BIT      ( ( unsigned int ) 0x0 << 16 )  /* (AES) 128-bit. */
+#define     AT91C_AES_CFBS_64_BIT       ( ( unsigned int ) 0x1 << 16 )  /* (AES) 64-bit. */
+#define     AT91C_AES_CFBS_32_BIT       ( ( unsigned int ) 0x2 << 16 )  /* (AES) 32-bit. */
+#define     AT91C_AES_CFBS_16_BIT       ( ( unsigned int ) 0x3 << 16 )  /* (AES) 16-bit. */
+#define     AT91C_AES_CFBS_8_BIT        ( ( unsigned int ) 0x4 << 16 )  /* (AES) 8-bit. */
+#define AT91C_AES_CKEY                  ( ( unsigned int ) 0xF << 20 )  /* (AES) Countermeasure Key */
+#define AT91C_AES_CTYPE                 ( ( unsigned int ) 0x1F << 24 ) /* (AES) Countermeasure Type */
+#define     AT91C_AES_CTYPE_TYPE1_EN    ( ( unsigned int ) 0x1 << 24 )  /* (AES) Countermeasure type 1 is enabled. */
+#define     AT91C_AES_CTYPE_TYPE2_EN    ( ( unsigned int ) 0x2 << 24 )  /* (AES) Countermeasure type 2 is enabled. */
+#define     AT91C_AES_CTYPE_TYPE3_EN    ( ( unsigned int ) 0x4 << 24 )  /* (AES) Countermeasure type 3 is enabled. */
+#define     AT91C_AES_CTYPE_TYPE4_EN    ( ( unsigned int ) 0x8 << 24 )  /* (AES) Countermeasure type 4 is enabled. */
+#define     AT91C_AES_CTYPE_TYPE5_EN    ( ( unsigned int ) 0x10 << 24 ) /* (AES) Countermeasure type 5 is enabled. */
+/* -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- */
+#define AT91C_AES_DATRDY                ( ( unsigned int ) 0x1 << 0 )   /* (AES) DATRDY */
+#define AT91C_AES_ENDRX                 ( ( unsigned int ) 0x1 << 1 )   /* (AES) PDC Read Buffer End */
+#define AT91C_AES_ENDTX                 ( ( unsigned int ) 0x1 << 2 )   /* (AES) PDC Write Buffer End */
+#define AT91C_AES_RXBUFF                ( ( unsigned int ) 0x1 << 3 )   /* (AES) PDC Read Buffer Full */
+#define AT91C_AES_TXBUFE                ( ( unsigned int ) 0x1 << 4 )   /* (AES) PDC Write Buffer Empty */
+#define AT91C_AES_URAD                  ( ( unsigned int ) 0x1 << 8 )   /* (AES) Unspecified Register Access Detection */
+/* -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- */
+/* -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- */
+/* -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- */
+#define AT91C_AES_URAT                              ( ( unsigned int ) 0x7 << 12 ) /* (AES) Unspecified Register Access Type Status */
+#define     AT91C_AES_URAT_IN_DAT_WRITE_DATPROC     ( ( unsigned int ) 0x0 << 12 ) /* (AES) Input data register written during the data processing in PDC mode. */
+#define     AT91C_AES_URAT_OUT_DAT_READ_DATPROC     ( ( unsigned int ) 0x1 << 12 ) /* (AES) Output data register read during the data processing. */
+#define     AT91C_AES_URAT_MODEREG_WRITE_DATPROC    ( ( unsigned int ) 0x2 << 12 ) /* (AES) Mode register written during the data processing. */
+#define     AT91C_AES_URAT_OUT_DAT_READ_SUBKEY      ( ( unsigned int ) 0x3 << 12 ) /* (AES) Output data register read during the sub-keys generation. */
+#define     AT91C_AES_URAT_MODEREG_WRITE_SUBKEY     ( ( unsigned int ) 0x4 << 12 ) /* (AES) Mode register written during the sub-keys generation. */
+#define     AT91C_AES_URAT_WO_REG_READ              ( ( unsigned int ) 0x5 << 12 ) /* (AES) Write-only register read access. */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Triple Data Encryption Standard
-// *****************************************************************************
-typedef struct _AT91S_TDES {
-    AT91_REG     TDES_CR;   // Control Register
-    AT91_REG     TDES_MR;   // Mode Register
-    AT91_REG     Reserved0[2];  //
-    AT91_REG     TDES_IER;  // Interrupt Enable Register
-    AT91_REG     TDES_IDR;  // Interrupt Disable Register
-    AT91_REG     TDES_IMR;  // Interrupt Mask Register
-    AT91_REG     TDES_ISR;  // Interrupt Status Register
-    AT91_REG     TDES_KEY1WxR[2];   // Key 1 Word x Register
-    AT91_REG     TDES_KEY2WxR[2];   // Key 2 Word x Register
-    AT91_REG     TDES_KEY3WxR[2];   // Key 3 Word x Register
-    AT91_REG     Reserved1[2];  //
-    AT91_REG     TDES_IDATAxR[2];   // Input Data x Register
-    AT91_REG     Reserved2[2];  //
-    AT91_REG     TDES_ODATAxR[2];   // Output Data x Register
-    AT91_REG     Reserved3[2];  //
-    AT91_REG     TDES_IVxR[2];  // Initialization Vector x Register
-    AT91_REG     Reserved4[37];     //
-    AT91_REG     TDES_VR;   // TDES Version Register
-    AT91_REG     TDES_RPR;  // Receive Pointer Register
-    AT91_REG     TDES_RCR;  // Receive Counter Register
-    AT91_REG     TDES_TPR;  // Transmit Pointer Register
-    AT91_REG     TDES_TCR;  // Transmit Counter Register
-    AT91_REG     TDES_RNPR;     // Receive Next Pointer Register
-    AT91_REG     TDES_RNCR;     // Receive Next Counter Register
-    AT91_REG     TDES_TNPR;     // Transmit Next Pointer Register
-    AT91_REG     TDES_TNCR;     // Transmit Next Counter Register
-    AT91_REG     TDES_PTCR;     // PDC Transfer Control Register
-    AT91_REG     TDES_PTSR;     // PDC Transfer Status Register
-} AT91S_TDES, *AT91PS_TDES;
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Triple Data Encryption Standard */
+/* ***************************************************************************** */
+typedef struct _AT91S_TDES
+{
+    AT91_REG TDES_CR;           /* Control Register */
+    AT91_REG TDES_MR;           /* Mode Register */
+    AT91_REG Reserved0[ 2 ];    /* */
+    AT91_REG TDES_IER;          /* Interrupt Enable Register */
+    AT91_REG TDES_IDR;          /* Interrupt Disable Register */
+    AT91_REG TDES_IMR;          /* Interrupt Mask Register */
+    AT91_REG TDES_ISR;          /* Interrupt Status Register */
+    AT91_REG TDES_KEY1WxR[ 2 ]; /* Key 1 Word x Register */
+    AT91_REG TDES_KEY2WxR[ 2 ]; /* Key 2 Word x Register */
+    AT91_REG TDES_KEY3WxR[ 2 ]; /* Key 3 Word x Register */
+    AT91_REG Reserved1[ 2 ];    /* */
+    AT91_REG TDES_IDATAxR[ 2 ]; /* Input Data x Register */
+    AT91_REG Reserved2[ 2 ];    /* */
+    AT91_REG TDES_ODATAxR[ 2 ]; /* Output Data x Register */
+    AT91_REG Reserved3[ 2 ];    /* */
+    AT91_REG TDES_IVxR[ 2 ];    /* Initialization Vector x Register */
+    AT91_REG Reserved4[ 37 ];   /* */
+    AT91_REG TDES_VR;           /* TDES Version Register */
+    AT91_REG TDES_RPR;          /* Receive Pointer Register */
+    AT91_REG TDES_RCR;          /* Receive Counter Register */
+    AT91_REG TDES_TPR;          /* Transmit Pointer Register */
+    AT91_REG TDES_TCR;          /* Transmit Counter Register */
+    AT91_REG TDES_RNPR;         /* Receive Next Pointer Register */
+    AT91_REG TDES_RNCR;         /* Receive Next Counter Register */
+    AT91_REG TDES_TNPR;         /* Transmit Next Pointer Register */
+    AT91_REG TDES_TNCR;         /* Transmit Next Counter Register */
+    AT91_REG TDES_PTCR;         /* PDC Transfer Control Register */
+    AT91_REG TDES_PTSR;         /* PDC Transfer Status Register */
+} AT91S_TDES, * AT91PS_TDES;
 
-// -------- TDES_CR : (TDES Offset: 0x0) Control Register --------
-#define AT91C_TDES_START      ((unsigned int) 0x1 <<  0) // (TDES) Starts Processing
-#define AT91C_TDES_SWRST      ((unsigned int) 0x1 <<  8) // (TDES) Software Reset
-// -------- TDES_MR : (TDES Offset: 0x4) Mode Register --------
-#define AT91C_TDES_CIPHER     ((unsigned int) 0x1 <<  0) // (TDES) Processing Mode
-#define AT91C_TDES_TDESMOD    ((unsigned int) 0x1 <<  1) // (TDES) Single or Triple DES Mode
-#define AT91C_TDES_KEYMOD     ((unsigned int) 0x1 <<  4) // (TDES) Key Mode
-#define AT91C_TDES_SMOD       ((unsigned int) 0x3 <<  8) // (TDES) Start Mode
-#define     AT91C_TDES_SMOD_MANUAL               ((unsigned int) 0x0 <<  8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.
-#define     AT91C_TDES_SMOD_AUTO                 ((unsigned int) 0x1 <<  8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).
-#define     AT91C_TDES_SMOD_PDC                  ((unsigned int) 0x2 <<  8) // (TDES) PDC Mode (cf datasheet).
-#define AT91C_TDES_OPMOD      ((unsigned int) 0x3 << 12) // (TDES) Operation Mode
-#define     AT91C_TDES_OPMOD_ECB                  ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode.
-#define     AT91C_TDES_OPMOD_CBC                  ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode.
-#define     AT91C_TDES_OPMOD_OFB                  ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode.
-#define     AT91C_TDES_OPMOD_CFB                  ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode.
-#define AT91C_TDES_LOD        ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode
-#define AT91C_TDES_CFBS       ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size
-#define     AT91C_TDES_CFBS_64_BIT               ((unsigned int) 0x0 << 16) // (TDES) 64-bit.
-#define     AT91C_TDES_CFBS_32_BIT               ((unsigned int) 0x1 << 16) // (TDES) 32-bit.
-#define     AT91C_TDES_CFBS_16_BIT               ((unsigned int) 0x2 << 16) // (TDES) 16-bit.
-#define     AT91C_TDES_CFBS_8_BIT                ((unsigned int) 0x3 << 16) // (TDES) 8-bit.
-// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register --------
-#define AT91C_TDES_DATRDY     ((unsigned int) 0x1 <<  0) // (TDES) DATRDY
-#define AT91C_TDES_ENDRX      ((unsigned int) 0x1 <<  1) // (TDES) PDC Read Buffer End
-#define AT91C_TDES_ENDTX      ((unsigned int) 0x1 <<  2) // (TDES) PDC Write Buffer End
-#define AT91C_TDES_RXBUFF     ((unsigned int) 0x1 <<  3) // (TDES) PDC Read Buffer Full
-#define AT91C_TDES_TXBUFE     ((unsigned int) 0x1 <<  4) // (TDES) PDC Write Buffer Empty
-#define AT91C_TDES_URAD       ((unsigned int) 0x1 <<  8) // (TDES) Unspecified Register Access Detection
-// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register --------
-// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register --------
-// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register --------
-#define AT91C_TDES_URAT       ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status
-#define     AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode.
-#define     AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing.
-#define     AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing.
-#define     AT91C_TDES_URAT_WO_REG_READ          ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access.
+/* -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- */
+#define AT91C_TDES_START              ( ( unsigned int ) 0x1 << 0 )  /* (TDES) Starts Processing */
+#define AT91C_TDES_SWRST              ( ( unsigned int ) 0x1 << 8 )  /* (TDES) Software Reset */
+/* -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- */
+#define AT91C_TDES_CIPHER             ( ( unsigned int ) 0x1 << 0 )  /* (TDES) Processing Mode */
+#define AT91C_TDES_TDESMOD            ( ( unsigned int ) 0x1 << 1 )  /* (TDES) Single or Triple DES Mode */
+#define AT91C_TDES_KEYMOD             ( ( unsigned int ) 0x1 << 4 )  /* (TDES) Key Mode */
+#define AT91C_TDES_SMOD               ( ( unsigned int ) 0x3 << 8 )  /* (TDES) Start Mode */
+#define     AT91C_TDES_SMOD_MANUAL    ( ( unsigned int ) 0x0 << 8 )  /* (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. */
+#define     AT91C_TDES_SMOD_AUTO      ( ( unsigned int ) 0x1 << 8 )  /* (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). */
+#define     AT91C_TDES_SMOD_PDC       ( ( unsigned int ) 0x2 << 8 )  /* (TDES) PDC Mode (cf datasheet). */
+#define AT91C_TDES_OPMOD              ( ( unsigned int ) 0x3 << 12 ) /* (TDES) Operation Mode */
+#define     AT91C_TDES_OPMOD_ECB      ( ( unsigned int ) 0x0 << 12 ) /* (TDES) ECB Electronic CodeBook mode. */
+#define     AT91C_TDES_OPMOD_CBC      ( ( unsigned int ) 0x1 << 12 ) /* (TDES) CBC Cipher Block Chaining mode. */
+#define     AT91C_TDES_OPMOD_OFB      ( ( unsigned int ) 0x2 << 12 ) /* (TDES) OFB Output Feedback mode. */
+#define     AT91C_TDES_OPMOD_CFB      ( ( unsigned int ) 0x3 << 12 ) /* (TDES) CFB Cipher Feedback mode. */
+#define AT91C_TDES_LOD                ( ( unsigned int ) 0x1 << 15 ) /* (TDES) Last Output Data Mode */
+#define AT91C_TDES_CFBS               ( ( unsigned int ) 0x3 << 16 ) /* (TDES) Cipher Feedback Data Size */
+#define     AT91C_TDES_CFBS_64_BIT    ( ( unsigned int ) 0x0 << 16 ) /* (TDES) 64-bit. */
+#define     AT91C_TDES_CFBS_32_BIT    ( ( unsigned int ) 0x1 << 16 ) /* (TDES) 32-bit. */
+#define     AT91C_TDES_CFBS_16_BIT    ( ( unsigned int ) 0x2 << 16 ) /* (TDES) 16-bit. */
+#define     AT91C_TDES_CFBS_8_BIT     ( ( unsigned int ) 0x3 << 16 ) /* (TDES) 8-bit. */
+/* -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- */
+#define AT91C_TDES_DATRDY             ( ( unsigned int ) 0x1 << 0 )  /* (TDES) DATRDY */
+#define AT91C_TDES_ENDRX              ( ( unsigned int ) 0x1 << 1 )  /* (TDES) PDC Read Buffer End */
+#define AT91C_TDES_ENDTX              ( ( unsigned int ) 0x1 << 2 )  /* (TDES) PDC Write Buffer End */
+#define AT91C_TDES_RXBUFF             ( ( unsigned int ) 0x1 << 3 )  /* (TDES) PDC Read Buffer Full */
+#define AT91C_TDES_TXBUFE             ( ( unsigned int ) 0x1 << 4 )  /* (TDES) PDC Write Buffer Empty */
+#define AT91C_TDES_URAD               ( ( unsigned int ) 0x1 << 8 )  /* (TDES) Unspecified Register Access Detection */
+/* -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- */
+/* -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- */
+/* -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- */
+#define AT91C_TDES_URAT                              ( ( unsigned int ) 0x3 << 12 ) /* (TDES) Unspecified Register Access Type Status */
+#define     AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC     ( ( unsigned int ) 0x0 << 12 ) /* (TDES) Input data register written during the data processing in PDC mode. */
+#define     AT91C_TDES_URAT_OUT_DAT_READ_DATPROC     ( ( unsigned int ) 0x1 << 12 ) /* (TDES) Output data register read during the data processing. */
+#define     AT91C_TDES_URAT_MODEREG_WRITE_DATPROC    ( ( unsigned int ) 0x2 << 12 ) /* (TDES) Mode register written during the data processing. */
+#define     AT91C_TDES_URAT_WO_REG_READ              ( ( unsigned int ) 0x3 << 12 ) /* (TDES) Write-only register read access. */
 
-// *****************************************************************************
-//               REGISTER ADDRESS DEFINITION FOR AT91SAM7X256
-// *****************************************************************************
-// ========== Register definition for SYS peripheral ==========
-// ========== Register definition for AIC peripheral ==========
-#define AT91C_AIC_IVR   ((AT91_REG *)   0xFFFFF100) // (AIC) IRQ Vector Register
-#define AT91C_AIC_SMR   ((AT91_REG *)   0xFFFFF000) // (AIC) Source Mode Register
-#define AT91C_AIC_FVR   ((AT91_REG *)   0xFFFFF104) // (AIC) FIQ Vector Register
-#define AT91C_AIC_DCR   ((AT91_REG *)   0xFFFFF138) // (AIC) Debug Control Register (Protect)
-#define AT91C_AIC_EOICR ((AT91_REG *)   0xFFFFF130) // (AIC) End of Interrupt Command Register
-#define AT91C_AIC_SVR   ((AT91_REG *)   0xFFFFF080) // (AIC) Source Vector Register
-#define AT91C_AIC_FFSR  ((AT91_REG *)   0xFFFFF148) // (AIC) Fast Forcing Status Register
-#define AT91C_AIC_ICCR  ((AT91_REG *)   0xFFFFF128) // (AIC) Interrupt Clear Command Register
-#define AT91C_AIC_ISR   ((AT91_REG *)   0xFFFFF108) // (AIC) Interrupt Status Register
-#define AT91C_AIC_IMR   ((AT91_REG *)   0xFFFFF110) // (AIC) Interrupt Mask Register
-#define AT91C_AIC_IPR   ((AT91_REG *)   0xFFFFF10C) // (AIC) Interrupt Pending Register
-#define AT91C_AIC_FFER  ((AT91_REG *)   0xFFFFF140) // (AIC) Fast Forcing Enable Register
-#define AT91C_AIC_IECR  ((AT91_REG *)   0xFFFFF120) // (AIC) Interrupt Enable Command Register
-#define AT91C_AIC_ISCR  ((AT91_REG *)   0xFFFFF12C) // (AIC) Interrupt Set Command Register
-#define AT91C_AIC_FFDR  ((AT91_REG *)   0xFFFFF144) // (AIC) Fast Forcing Disable Register
-#define AT91C_AIC_CISR  ((AT91_REG *)   0xFFFFF114) // (AIC) Core Interrupt Status Register
-#define AT91C_AIC_IDCR  ((AT91_REG *)   0xFFFFF124) // (AIC) Interrupt Disable Command Register
-#define AT91C_AIC_SPU   ((AT91_REG *)   0xFFFFF134) // (AIC) Spurious Vector Register
-// ========== Register definition for PDC_DBGU peripheral ==========
-#define AT91C_DBGU_TCR  ((AT91_REG *)   0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
-#define AT91C_DBGU_RNPR ((AT91_REG *)   0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
-#define AT91C_DBGU_TNPR ((AT91_REG *)   0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
-#define AT91C_DBGU_TPR  ((AT91_REG *)   0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
-#define AT91C_DBGU_RPR  ((AT91_REG *)   0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
-#define AT91C_DBGU_RCR  ((AT91_REG *)   0xFFFFF304) // (PDC_DBGU) Receive Counter Register
-#define AT91C_DBGU_RNCR ((AT91_REG *)   0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
-#define AT91C_DBGU_PTCR ((AT91_REG *)   0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
-#define AT91C_DBGU_PTSR ((AT91_REG *)   0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
-#define AT91C_DBGU_TNCR ((AT91_REG *)   0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
-// ========== Register definition for DBGU peripheral ==========
-#define AT91C_DBGU_EXID ((AT91_REG *)   0xFFFFF244) // (DBGU) Chip ID Extension Register
-#define AT91C_DBGU_BRGR ((AT91_REG *)   0xFFFFF220) // (DBGU) Baud Rate Generator Register
-#define AT91C_DBGU_IDR  ((AT91_REG *)   0xFFFFF20C) // (DBGU) Interrupt Disable Register
-#define AT91C_DBGU_CSR  ((AT91_REG *)   0xFFFFF214) // (DBGU) Channel Status Register
-#define AT91C_DBGU_CIDR ((AT91_REG *)   0xFFFFF240) // (DBGU) Chip ID Register
-#define AT91C_DBGU_MR   ((AT91_REG *)   0xFFFFF204) // (DBGU) Mode Register
-#define AT91C_DBGU_IMR  ((AT91_REG *)   0xFFFFF210) // (DBGU) Interrupt Mask Register
-#define AT91C_DBGU_CR   ((AT91_REG *)   0xFFFFF200) // (DBGU) Control Register
-#define AT91C_DBGU_FNTR ((AT91_REG *)   0xFFFFF248) // (DBGU) Force NTRST Register
-#define AT91C_DBGU_THR  ((AT91_REG *)   0xFFFFF21C) // (DBGU) Transmitter Holding Register
-#define AT91C_DBGU_RHR  ((AT91_REG *)   0xFFFFF218) // (DBGU) Receiver Holding Register
-#define AT91C_DBGU_IER  ((AT91_REG *)   0xFFFFF208) // (DBGU) Interrupt Enable Register
-// ========== Register definition for PIOA peripheral ==========
-#define AT91C_PIOA_ODR  ((AT91_REG *)   0xFFFFF414) // (PIOA) Output Disable Registerr
-#define AT91C_PIOA_SODR ((AT91_REG *)   0xFFFFF430) // (PIOA) Set Output Data Register
-#define AT91C_PIOA_ISR  ((AT91_REG *)   0xFFFFF44C) // (PIOA) Interrupt Status Register
-#define AT91C_PIOA_ABSR ((AT91_REG *)   0xFFFFF478) // (PIOA) AB Select Status Register
-#define AT91C_PIOA_IER  ((AT91_REG *)   0xFFFFF440) // (PIOA) Interrupt Enable Register
-#define AT91C_PIOA_PPUDR ((AT91_REG *)  0xFFFFF460) // (PIOA) Pull-up Disable Register
-#define AT91C_PIOA_IMR  ((AT91_REG *)   0xFFFFF448) // (PIOA) Interrupt Mask Register
-#define AT91C_PIOA_PER  ((AT91_REG *)   0xFFFFF400) // (PIOA) PIO Enable Register
-#define AT91C_PIOA_IFDR ((AT91_REG *)   0xFFFFF424) // (PIOA) Input Filter Disable Register
-#define AT91C_PIOA_OWDR ((AT91_REG *)   0xFFFFF4A4) // (PIOA) Output Write Disable Register
-#define AT91C_PIOA_MDSR ((AT91_REG *)   0xFFFFF458) // (PIOA) Multi-driver Status Register
-#define AT91C_PIOA_IDR  ((AT91_REG *)   0xFFFFF444) // (PIOA) Interrupt Disable Register
-#define AT91C_PIOA_ODSR ((AT91_REG *)   0xFFFFF438) // (PIOA) Output Data Status Register
-#define AT91C_PIOA_PPUSR ((AT91_REG *)  0xFFFFF468) // (PIOA) Pull-up Status Register
-#define AT91C_PIOA_OWSR ((AT91_REG *)   0xFFFFF4A8) // (PIOA) Output Write Status Register
-#define AT91C_PIOA_BSR  ((AT91_REG *)   0xFFFFF474) // (PIOA) Select B Register
-#define AT91C_PIOA_OWER ((AT91_REG *)   0xFFFFF4A0) // (PIOA) Output Write Enable Register
-#define AT91C_PIOA_IFER ((AT91_REG *)   0xFFFFF420) // (PIOA) Input Filter Enable Register
-#define AT91C_PIOA_PDSR ((AT91_REG *)   0xFFFFF43C) // (PIOA) Pin Data Status Register
-#define AT91C_PIOA_PPUER ((AT91_REG *)  0xFFFFF464) // (PIOA) Pull-up Enable Register
-#define AT91C_PIOA_OSR  ((AT91_REG *)   0xFFFFF418) // (PIOA) Output Status Register
-#define AT91C_PIOA_ASR  ((AT91_REG *)   0xFFFFF470) // (PIOA) Select A Register
-#define AT91C_PIOA_MDDR ((AT91_REG *)   0xFFFFF454) // (PIOA) Multi-driver Disable Register
-#define AT91C_PIOA_CODR ((AT91_REG *)   0xFFFFF434) // (PIOA) Clear Output Data Register
-#define AT91C_PIOA_MDER ((AT91_REG *)   0xFFFFF450) // (PIOA) Multi-driver Enable Register
-#define AT91C_PIOA_PDR  ((AT91_REG *)   0xFFFFF404) // (PIOA) PIO Disable Register
-#define AT91C_PIOA_IFSR ((AT91_REG *)   0xFFFFF428) // (PIOA) Input Filter Status Register
-#define AT91C_PIOA_OER  ((AT91_REG *)   0xFFFFF410) // (PIOA) Output Enable Register
-#define AT91C_PIOA_PSR  ((AT91_REG *)   0xFFFFF408) // (PIOA) PIO Status Register
-// ========== Register definition for PIOB peripheral ==========
-#define AT91C_PIOB_OWDR ((AT91_REG *)   0xFFFFF6A4) // (PIOB) Output Write Disable Register
-#define AT91C_PIOB_MDER ((AT91_REG *)   0xFFFFF650) // (PIOB) Multi-driver Enable Register
-#define AT91C_PIOB_PPUSR ((AT91_REG *)  0xFFFFF668) // (PIOB) Pull-up Status Register
-#define AT91C_PIOB_IMR  ((AT91_REG *)   0xFFFFF648) // (PIOB) Interrupt Mask Register
-#define AT91C_PIOB_ASR  ((AT91_REG *)   0xFFFFF670) // (PIOB) Select A Register
-#define AT91C_PIOB_PPUDR ((AT91_REG *)  0xFFFFF660) // (PIOB) Pull-up Disable Register
-#define AT91C_PIOB_PSR  ((AT91_REG *)   0xFFFFF608) // (PIOB) PIO Status Register
-#define AT91C_PIOB_IER  ((AT91_REG *)   0xFFFFF640) // (PIOB) Interrupt Enable Register
-#define AT91C_PIOB_CODR ((AT91_REG *)   0xFFFFF634) // (PIOB) Clear Output Data Register
-#define AT91C_PIOB_OWER ((AT91_REG *)   0xFFFFF6A0) // (PIOB) Output Write Enable Register
-#define AT91C_PIOB_ABSR ((AT91_REG *)   0xFFFFF678) // (PIOB) AB Select Status Register
-#define AT91C_PIOB_IFDR ((AT91_REG *)   0xFFFFF624) // (PIOB) Input Filter Disable Register
-#define AT91C_PIOB_PDSR ((AT91_REG *)   0xFFFFF63C) // (PIOB) Pin Data Status Register
-#define AT91C_PIOB_IDR  ((AT91_REG *)   0xFFFFF644) // (PIOB) Interrupt Disable Register
-#define AT91C_PIOB_OWSR ((AT91_REG *)   0xFFFFF6A8) // (PIOB) Output Write Status Register
-#define AT91C_PIOB_PDR  ((AT91_REG *)   0xFFFFF604) // (PIOB) PIO Disable Register
-#define AT91C_PIOB_ODR  ((AT91_REG *)   0xFFFFF614) // (PIOB) Output Disable Registerr
-#define AT91C_PIOB_IFSR ((AT91_REG *)   0xFFFFF628) // (PIOB) Input Filter Status Register
-#define AT91C_PIOB_PPUER ((AT91_REG *)  0xFFFFF664) // (PIOB) Pull-up Enable Register
-#define AT91C_PIOB_SODR ((AT91_REG *)   0xFFFFF630) // (PIOB) Set Output Data Register
-#define AT91C_PIOB_ISR  ((AT91_REG *)   0xFFFFF64C) // (PIOB) Interrupt Status Register
-#define AT91C_PIOB_ODSR ((AT91_REG *)   0xFFFFF638) // (PIOB) Output Data Status Register
-#define AT91C_PIOB_OSR  ((AT91_REG *)   0xFFFFF618) // (PIOB) Output Status Register
-#define AT91C_PIOB_MDSR ((AT91_REG *)   0xFFFFF658) // (PIOB) Multi-driver Status Register
-#define AT91C_PIOB_IFER ((AT91_REG *)   0xFFFFF620) // (PIOB) Input Filter Enable Register
-#define AT91C_PIOB_BSR  ((AT91_REG *)   0xFFFFF674) // (PIOB) Select B Register
-#define AT91C_PIOB_MDDR ((AT91_REG *)   0xFFFFF654) // (PIOB) Multi-driver Disable Register
-#define AT91C_PIOB_OER  ((AT91_REG *)   0xFFFFF610) // (PIOB) Output Enable Register
-#define AT91C_PIOB_PER  ((AT91_REG *)   0xFFFFF600) // (PIOB) PIO Enable Register
-// ========== Register definition for CKGR peripheral ==========
-#define AT91C_CKGR_MOR  ((AT91_REG *)   0xFFFFFC20) // (CKGR) Main Oscillator Register
-#define AT91C_CKGR_PLLR ((AT91_REG *)   0xFFFFFC2C) // (CKGR) PLL Register
-#define AT91C_CKGR_MCFR ((AT91_REG *)   0xFFFFFC24) // (CKGR) Main Clock  Frequency Register
-// ========== Register definition for PMC peripheral ==========
-#define AT91C_PMC_IDR   ((AT91_REG *)   0xFFFFFC64) // (PMC) Interrupt Disable Register
-#define AT91C_PMC_MOR   ((AT91_REG *)   0xFFFFFC20) // (PMC) Main Oscillator Register
-#define AT91C_PMC_PLLR  ((AT91_REG *)   0xFFFFFC2C) // (PMC) PLL Register
-#define AT91C_PMC_PCER  ((AT91_REG *)   0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
-#define AT91C_PMC_PCKR  ((AT91_REG *)   0xFFFFFC40) // (PMC) Programmable Clock Register
-#define AT91C_PMC_MCKR  ((AT91_REG *)   0xFFFFFC30) // (PMC) Master Clock Register
-#define AT91C_PMC_SCDR  ((AT91_REG *)   0xFFFFFC04) // (PMC) System Clock Disable Register
-#define AT91C_PMC_PCDR  ((AT91_REG *)   0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
-#define AT91C_PMC_SCSR  ((AT91_REG *)   0xFFFFFC08) // (PMC) System Clock Status Register
-#define AT91C_PMC_PCSR  ((AT91_REG *)   0xFFFFFC18) // (PMC) Peripheral Clock Status Register
-#define AT91C_PMC_MCFR  ((AT91_REG *)   0xFFFFFC24) // (PMC) Main Clock  Frequency Register
-#define AT91C_PMC_SCER  ((AT91_REG *)   0xFFFFFC00) // (PMC) System Clock Enable Register
-#define AT91C_PMC_IMR   ((AT91_REG *)   0xFFFFFC6C) // (PMC) Interrupt Mask Register
-#define AT91C_PMC_IER   ((AT91_REG *)   0xFFFFFC60) // (PMC) Interrupt Enable Register
-#define AT91C_PMC_SR    ((AT91_REG *)   0xFFFFFC68) // (PMC) Status Register
-// ========== Register definition for RSTC peripheral ==========
-#define AT91C_RSTC_RCR  ((AT91_REG *)   0xFFFFFD00) // (RSTC) Reset Control Register
-#define AT91C_RSTC_RMR  ((AT91_REG *)   0xFFFFFD08) // (RSTC) Reset Mode Register
-#define AT91C_RSTC_RSR  ((AT91_REG *)   0xFFFFFD04) // (RSTC) Reset Status Register
-// ========== Register definition for RTTC peripheral ==========
-#define AT91C_RTTC_RTSR ((AT91_REG *)   0xFFFFFD2C) // (RTTC) Real-time Status Register
-#define AT91C_RTTC_RTMR ((AT91_REG *)   0xFFFFFD20) // (RTTC) Real-time Mode Register
-#define AT91C_RTTC_RTVR ((AT91_REG *)   0xFFFFFD28) // (RTTC) Real-time Value Register
-#define AT91C_RTTC_RTAR ((AT91_REG *)   0xFFFFFD24) // (RTTC) Real-time Alarm Register
-// ========== Register definition for PITC peripheral ==========
-#define AT91C_PITC_PIVR ((AT91_REG *)   0xFFFFFD38) // (PITC) Period Interval Value Register
-#define AT91C_PITC_PISR ((AT91_REG *)   0xFFFFFD34) // (PITC) Period Interval Status Register
-#define AT91C_PITC_PIIR ((AT91_REG *)   0xFFFFFD3C) // (PITC) Period Interval Image Register
-#define AT91C_PITC_PIMR ((AT91_REG *)   0xFFFFFD30) // (PITC) Period Interval Mode Register
-// ========== Register definition for WDTC peripheral ==========
-#define AT91C_WDTC_WDCR ((AT91_REG *)   0xFFFFFD40) // (WDTC) Watchdog Control Register
-#define AT91C_WDTC_WDSR ((AT91_REG *)   0xFFFFFD48) // (WDTC) Watchdog Status Register
-#define AT91C_WDTC_WDMR ((AT91_REG *)   0xFFFFFD44) // (WDTC) Watchdog Mode Register
-// ========== Register definition for VREG peripheral ==========
-#define AT91C_VREG_MR   ((AT91_REG *)   0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
-// ========== Register definition for MC peripheral ==========
-#define AT91C_MC_ASR    ((AT91_REG *)   0xFFFFFF04) // (MC) MC Abort Status Register
-#define AT91C_MC_RCR    ((AT91_REG *)   0xFFFFFF00) // (MC) MC Remap Control Register
-#define AT91C_MC_FCR    ((AT91_REG *)   0xFFFFFF64) // (MC) MC Flash Command Register
-#define AT91C_MC_AASR   ((AT91_REG *)   0xFFFFFF08) // (MC) MC Abort Address Status Register
-#define AT91C_MC_FSR    ((AT91_REG *)   0xFFFFFF68) // (MC) MC Flash Status Register
-#define AT91C_MC_FMR    ((AT91_REG *)   0xFFFFFF60) // (MC) MC Flash Mode Register
-// ========== Register definition for PDC_SPI1 peripheral ==========
-#define AT91C_SPI1_PTCR ((AT91_REG *)   0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register
-#define AT91C_SPI1_RPR  ((AT91_REG *)   0xFFFE4100) // (PDC_SPI1) Receive Pointer Register
-#define AT91C_SPI1_TNCR ((AT91_REG *)   0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register
-#define AT91C_SPI1_TPR  ((AT91_REG *)   0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register
-#define AT91C_SPI1_TNPR ((AT91_REG *)   0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register
-#define AT91C_SPI1_TCR  ((AT91_REG *)   0xFFFE410C) // (PDC_SPI1) Transmit Counter Register
-#define AT91C_SPI1_RCR  ((AT91_REG *)   0xFFFE4104) // (PDC_SPI1) Receive Counter Register
-#define AT91C_SPI1_RNPR ((AT91_REG *)   0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register
-#define AT91C_SPI1_RNCR ((AT91_REG *)   0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register
-#define AT91C_SPI1_PTSR ((AT91_REG *)   0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register
-// ========== Register definition for SPI1 peripheral ==========
-#define AT91C_SPI1_IMR  ((AT91_REG *)   0xFFFE401C) // (SPI1) Interrupt Mask Register
-#define AT91C_SPI1_IER  ((AT91_REG *)   0xFFFE4014) // (SPI1) Interrupt Enable Register
-#define AT91C_SPI1_MR   ((AT91_REG *)   0xFFFE4004) // (SPI1) Mode Register
-#define AT91C_SPI1_RDR  ((AT91_REG *)   0xFFFE4008) // (SPI1) Receive Data Register
-#define AT91C_SPI1_IDR  ((AT91_REG *)   0xFFFE4018) // (SPI1) Interrupt Disable Register
-#define AT91C_SPI1_SR   ((AT91_REG *)   0xFFFE4010) // (SPI1) Status Register
-#define AT91C_SPI1_TDR  ((AT91_REG *)   0xFFFE400C) // (SPI1) Transmit Data Register
-#define AT91C_SPI1_CR   ((AT91_REG *)   0xFFFE4000) // (SPI1) Control Register
-#define AT91C_SPI1_CSR  ((AT91_REG *)   0xFFFE4030) // (SPI1) Chip Select Register
-// ========== Register definition for PDC_SPI0 peripheral ==========
-#define AT91C_SPI0_PTCR ((AT91_REG *)   0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register
-#define AT91C_SPI0_TPR  ((AT91_REG *)   0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register
-#define AT91C_SPI0_TCR  ((AT91_REG *)   0xFFFE010C) // (PDC_SPI0) Transmit Counter Register
-#define AT91C_SPI0_RCR  ((AT91_REG *)   0xFFFE0104) // (PDC_SPI0) Receive Counter Register
-#define AT91C_SPI0_PTSR ((AT91_REG *)   0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register
-#define AT91C_SPI0_RNPR ((AT91_REG *)   0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register
-#define AT91C_SPI0_RPR  ((AT91_REG *)   0xFFFE0100) // (PDC_SPI0) Receive Pointer Register
-#define AT91C_SPI0_TNCR ((AT91_REG *)   0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register
-#define AT91C_SPI0_RNCR ((AT91_REG *)   0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register
-#define AT91C_SPI0_TNPR ((AT91_REG *)   0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register
-// ========== Register definition for SPI0 peripheral ==========
-#define AT91C_SPI0_IER  ((AT91_REG *)   0xFFFE0014) // (SPI0) Interrupt Enable Register
-#define AT91C_SPI0_SR   ((AT91_REG *)   0xFFFE0010) // (SPI0) Status Register
-#define AT91C_SPI0_IDR  ((AT91_REG *)   0xFFFE0018) // (SPI0) Interrupt Disable Register
-#define AT91C_SPI0_CR   ((AT91_REG *)   0xFFFE0000) // (SPI0) Control Register
-#define AT91C_SPI0_MR   ((AT91_REG *)   0xFFFE0004) // (SPI0) Mode Register
-#define AT91C_SPI0_IMR  ((AT91_REG *)   0xFFFE001C) // (SPI0) Interrupt Mask Register
-#define AT91C_SPI0_TDR  ((AT91_REG *)   0xFFFE000C) // (SPI0) Transmit Data Register
-#define AT91C_SPI0_RDR  ((AT91_REG *)   0xFFFE0008) // (SPI0) Receive Data Register
-#define AT91C_SPI0_CSR  ((AT91_REG *)   0xFFFE0030) // (SPI0) Chip Select Register
-// ========== Register definition for PDC_US1 peripheral ==========
-#define AT91C_US1_RNCR  ((AT91_REG *)   0xFFFC4114) // (PDC_US1) Receive Next Counter Register
-#define AT91C_US1_PTCR  ((AT91_REG *)   0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
-#define AT91C_US1_TCR   ((AT91_REG *)   0xFFFC410C) // (PDC_US1) Transmit Counter Register
-#define AT91C_US1_PTSR  ((AT91_REG *)   0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
-#define AT91C_US1_TNPR  ((AT91_REG *)   0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
-#define AT91C_US1_RCR   ((AT91_REG *)   0xFFFC4104) // (PDC_US1) Receive Counter Register
-#define AT91C_US1_RNPR  ((AT91_REG *)   0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
-#define AT91C_US1_RPR   ((AT91_REG *)   0xFFFC4100) // (PDC_US1) Receive Pointer Register
-#define AT91C_US1_TNCR  ((AT91_REG *)   0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
-#define AT91C_US1_TPR   ((AT91_REG *)   0xFFFC4108) // (PDC_US1) Transmit Pointer Register
-// ========== Register definition for US1 peripheral ==========
-#define AT91C_US1_IF    ((AT91_REG *)   0xFFFC404C) // (US1) IRDA_FILTER Register
-#define AT91C_US1_NER   ((AT91_REG *)   0xFFFC4044) // (US1) Nb Errors Register
-#define AT91C_US1_RTOR  ((AT91_REG *)   0xFFFC4024) // (US1) Receiver Time-out Register
-#define AT91C_US1_CSR   ((AT91_REG *)   0xFFFC4014) // (US1) Channel Status Register
-#define AT91C_US1_IDR   ((AT91_REG *)   0xFFFC400C) // (US1) Interrupt Disable Register
-#define AT91C_US1_IER   ((AT91_REG *)   0xFFFC4008) // (US1) Interrupt Enable Register
-#define AT91C_US1_THR   ((AT91_REG *)   0xFFFC401C) // (US1) Transmitter Holding Register
-#define AT91C_US1_TTGR  ((AT91_REG *)   0xFFFC4028) // (US1) Transmitter Time-guard Register
-#define AT91C_US1_RHR   ((AT91_REG *)   0xFFFC4018) // (US1) Receiver Holding Register
-#define AT91C_US1_BRGR  ((AT91_REG *)   0xFFFC4020) // (US1) Baud Rate Generator Register
-#define AT91C_US1_IMR   ((AT91_REG *)   0xFFFC4010) // (US1) Interrupt Mask Register
-#define AT91C_US1_FIDI  ((AT91_REG *)   0xFFFC4040) // (US1) FI_DI_Ratio Register
-#define AT91C_US1_CR    ((AT91_REG *)   0xFFFC4000) // (US1) Control Register
-#define AT91C_US1_MR    ((AT91_REG *)   0xFFFC4004) // (US1) Mode Register
-// ========== Register definition for PDC_US0 peripheral ==========
-#define AT91C_US0_TNPR  ((AT91_REG *)   0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
-#define AT91C_US0_RNPR  ((AT91_REG *)   0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
-#define AT91C_US0_TCR   ((AT91_REG *)   0xFFFC010C) // (PDC_US0) Transmit Counter Register
-#define AT91C_US0_PTCR  ((AT91_REG *)   0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
-#define AT91C_US0_PTSR  ((AT91_REG *)   0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
-#define AT91C_US0_TNCR  ((AT91_REG *)   0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
-#define AT91C_US0_TPR   ((AT91_REG *)   0xFFFC0108) // (PDC_US0) Transmit Pointer Register
-#define AT91C_US0_RCR   ((AT91_REG *)   0xFFFC0104) // (PDC_US0) Receive Counter Register
-#define AT91C_US0_RPR   ((AT91_REG *)   0xFFFC0100) // (PDC_US0) Receive Pointer Register
-#define AT91C_US0_RNCR  ((AT91_REG *)   0xFFFC0114) // (PDC_US0) Receive Next Counter Register
-// ========== Register definition for US0 peripheral ==========
-#define AT91C_US0_BRGR  ((AT91_REG *)   0xFFFC0020) // (US0) Baud Rate Generator Register
-#define AT91C_US0_NER   ((AT91_REG *)   0xFFFC0044) // (US0) Nb Errors Register
-#define AT91C_US0_CR    ((AT91_REG *)   0xFFFC0000) // (US0) Control Register
-#define AT91C_US0_IMR   ((AT91_REG *)   0xFFFC0010) // (US0) Interrupt Mask Register
-#define AT91C_US0_FIDI  ((AT91_REG *)   0xFFFC0040) // (US0) FI_DI_Ratio Register
-#define AT91C_US0_TTGR  ((AT91_REG *)   0xFFFC0028) // (US0) Transmitter Time-guard Register
-#define AT91C_US0_MR    ((AT91_REG *)   0xFFFC0004) // (US0) Mode Register
-#define AT91C_US0_RTOR  ((AT91_REG *)   0xFFFC0024) // (US0) Receiver Time-out Register
-#define AT91C_US0_CSR   ((AT91_REG *)   0xFFFC0014) // (US0) Channel Status Register
-#define AT91C_US0_RHR   ((AT91_REG *)   0xFFFC0018) // (US0) Receiver Holding Register
-#define AT91C_US0_IDR   ((AT91_REG *)   0xFFFC000C) // (US0) Interrupt Disable Register
-#define AT91C_US0_THR   ((AT91_REG *)   0xFFFC001C) // (US0) Transmitter Holding Register
-#define AT91C_US0_IF    ((AT91_REG *)   0xFFFC004C) // (US0) IRDA_FILTER Register
-#define AT91C_US0_IER   ((AT91_REG *)   0xFFFC0008) // (US0) Interrupt Enable Register
-// ========== Register definition for PDC_SSC peripheral ==========
-#define AT91C_SSC_TNCR  ((AT91_REG *)   0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
-#define AT91C_SSC_RPR   ((AT91_REG *)   0xFFFD4100) // (PDC_SSC) Receive Pointer Register
-#define AT91C_SSC_RNCR  ((AT91_REG *)   0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
-#define AT91C_SSC_TPR   ((AT91_REG *)   0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
-#define AT91C_SSC_PTCR  ((AT91_REG *)   0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
-#define AT91C_SSC_TCR   ((AT91_REG *)   0xFFFD410C) // (PDC_SSC) Transmit Counter Register
-#define AT91C_SSC_RCR   ((AT91_REG *)   0xFFFD4104) // (PDC_SSC) Receive Counter Register
-#define AT91C_SSC_RNPR  ((AT91_REG *)   0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
-#define AT91C_SSC_TNPR  ((AT91_REG *)   0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
-#define AT91C_SSC_PTSR  ((AT91_REG *)   0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
-// ========== Register definition for SSC peripheral ==========
-#define AT91C_SSC_RHR   ((AT91_REG *)   0xFFFD4020) // (SSC) Receive Holding Register
-#define AT91C_SSC_RSHR  ((AT91_REG *)   0xFFFD4030) // (SSC) Receive Sync Holding Register
-#define AT91C_SSC_TFMR  ((AT91_REG *)   0xFFFD401C) // (SSC) Transmit Frame Mode Register
-#define AT91C_SSC_IDR   ((AT91_REG *)   0xFFFD4048) // (SSC) Interrupt Disable Register
-#define AT91C_SSC_THR   ((AT91_REG *)   0xFFFD4024) // (SSC) Transmit Holding Register
-#define AT91C_SSC_RCMR  ((AT91_REG *)   0xFFFD4010) // (SSC) Receive Clock ModeRegister
-#define AT91C_SSC_IER   ((AT91_REG *)   0xFFFD4044) // (SSC) Interrupt Enable Register
-#define AT91C_SSC_TSHR  ((AT91_REG *)   0xFFFD4034) // (SSC) Transmit Sync Holding Register
-#define AT91C_SSC_SR    ((AT91_REG *)   0xFFFD4040) // (SSC) Status Register
-#define AT91C_SSC_CMR   ((AT91_REG *)   0xFFFD4004) // (SSC) Clock Mode Register
-#define AT91C_SSC_TCMR  ((AT91_REG *)   0xFFFD4018) // (SSC) Transmit Clock Mode Register
-#define AT91C_SSC_CR    ((AT91_REG *)   0xFFFD4000) // (SSC) Control Register
-#define AT91C_SSC_IMR   ((AT91_REG *)   0xFFFD404C) // (SSC) Interrupt Mask Register
-#define AT91C_SSC_RFMR  ((AT91_REG *)   0xFFFD4014) // (SSC) Receive Frame Mode Register
-// ========== Register definition for TWI peripheral ==========
-#define AT91C_TWI_IER   ((AT91_REG *)   0xFFFB8024) // (TWI) Interrupt Enable Register
-#define AT91C_TWI_CR    ((AT91_REG *)   0xFFFB8000) // (TWI) Control Register
-#define AT91C_TWI_SR    ((AT91_REG *)   0xFFFB8020) // (TWI) Status Register
-#define AT91C_TWI_IMR   ((AT91_REG *)   0xFFFB802C) // (TWI) Interrupt Mask Register
-#define AT91C_TWI_THR   ((AT91_REG *)   0xFFFB8034) // (TWI) Transmit Holding Register
-#define AT91C_TWI_IDR   ((AT91_REG *)   0xFFFB8028) // (TWI) Interrupt Disable Register
-#define AT91C_TWI_IADR  ((AT91_REG *)   0xFFFB800C) // (TWI) Internal Address Register
-#define AT91C_TWI_MMR   ((AT91_REG *)   0xFFFB8004) // (TWI) Master Mode Register
-#define AT91C_TWI_CWGR  ((AT91_REG *)   0xFFFB8010) // (TWI) Clock Waveform Generator Register
-#define AT91C_TWI_RHR   ((AT91_REG *)   0xFFFB8030) // (TWI) Receive Holding Register
-// ========== Register definition for PWMC_CH3 peripheral ==========
-#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *)  0xFFFCC270) // (PWMC_CH3) Channel Update Register
-#define AT91C_PWMC_CH3_Reserved ((AT91_REG *)   0xFFFCC274) // (PWMC_CH3) Reserved
-#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *)  0xFFFCC268) // (PWMC_CH3) Channel Period Register
-#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *)  0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
-#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *)  0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
-#define AT91C_PWMC_CH3_CMR ((AT91_REG *)    0xFFFCC260) // (PWMC_CH3) Channel Mode Register
-// ========== Register definition for PWMC_CH2 peripheral ==========
-#define AT91C_PWMC_CH2_Reserved ((AT91_REG *)   0xFFFCC254) // (PWMC_CH2) Reserved
-#define AT91C_PWMC_CH2_CMR ((AT91_REG *)    0xFFFCC240) // (PWMC_CH2) Channel Mode Register
-#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *)  0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
-#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *)  0xFFFCC248) // (PWMC_CH2) Channel Period Register
-#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *)  0xFFFCC250) // (PWMC_CH2) Channel Update Register
-#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *)  0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
-// ========== Register definition for PWMC_CH1 peripheral ==========
-#define AT91C_PWMC_CH1_Reserved ((AT91_REG *)   0xFFFCC234) // (PWMC_CH1) Reserved
-#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *)  0xFFFCC230) // (PWMC_CH1) Channel Update Register
-#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *)  0xFFFCC228) // (PWMC_CH1) Channel Period Register
-#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *)  0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
-#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *)  0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
-#define AT91C_PWMC_CH1_CMR ((AT91_REG *)    0xFFFCC220) // (PWMC_CH1) Channel Mode Register
-// ========== Register definition for PWMC_CH0 peripheral ==========
-#define AT91C_PWMC_CH0_Reserved ((AT91_REG *)   0xFFFCC214) // (PWMC_CH0) Reserved
-#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *)  0xFFFCC208) // (PWMC_CH0) Channel Period Register
-#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *)  0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
-#define AT91C_PWMC_CH0_CMR ((AT91_REG *)    0xFFFCC200) // (PWMC_CH0) Channel Mode Register
-#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *)  0xFFFCC210) // (PWMC_CH0) Channel Update Register
-#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *)  0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
-// ========== Register definition for PWMC peripheral ==========
-#define AT91C_PWMC_IDR  ((AT91_REG *)   0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
-#define AT91C_PWMC_DIS  ((AT91_REG *)   0xFFFCC008) // (PWMC) PWMC Disable Register
-#define AT91C_PWMC_IER  ((AT91_REG *)   0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
-#define AT91C_PWMC_VR   ((AT91_REG *)   0xFFFCC0FC) // (PWMC) PWMC Version Register
-#define AT91C_PWMC_ISR  ((AT91_REG *)   0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
-#define AT91C_PWMC_SR   ((AT91_REG *)   0xFFFCC00C) // (PWMC) PWMC Status Register
-#define AT91C_PWMC_IMR  ((AT91_REG *)   0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
-#define AT91C_PWMC_MR   ((AT91_REG *)   0xFFFCC000) // (PWMC) PWMC Mode Register
-#define AT91C_PWMC_ENA  ((AT91_REG *)   0xFFFCC004) // (PWMC) PWMC Enable Register
-// ========== Register definition for UDP peripheral ==========
-#define AT91C_UDP_IMR   ((AT91_REG *)   0xFFFB0018) // (UDP) Interrupt Mask Register
-#define AT91C_UDP_FADDR ((AT91_REG *)   0xFFFB0008) // (UDP) Function Address Register
-#define AT91C_UDP_NUM   ((AT91_REG *)   0xFFFB0000) // (UDP) Frame Number Register
-#define AT91C_UDP_FDR   ((AT91_REG *)   0xFFFB0050) // (UDP) Endpoint FIFO Data Register
-#define AT91C_UDP_ISR   ((AT91_REG *)   0xFFFB001C) // (UDP) Interrupt Status Register
-#define AT91C_UDP_CSR   ((AT91_REG *)   0xFFFB0030) // (UDP) Endpoint Control and Status Register
-#define AT91C_UDP_IDR   ((AT91_REG *)   0xFFFB0014) // (UDP) Interrupt Disable Register
-#define AT91C_UDP_ICR   ((AT91_REG *)   0xFFFB0020) // (UDP) Interrupt Clear Register
-#define AT91C_UDP_RSTEP ((AT91_REG *)   0xFFFB0028) // (UDP) Reset Endpoint Register
-#define AT91C_UDP_TXVC  ((AT91_REG *)   0xFFFB0074) // (UDP) Transceiver Control Register
-#define AT91C_UDP_GLBSTATE ((AT91_REG *)    0xFFFB0004) // (UDP) Global State Register
-#define AT91C_UDP_IER   ((AT91_REG *)   0xFFFB0010) // (UDP) Interrupt Enable Register
-// ========== Register definition for TC0 peripheral ==========
-#define AT91C_TC0_SR    ((AT91_REG *)   0xFFFA0020) // (TC0) Status Register
-#define AT91C_TC0_RC    ((AT91_REG *)   0xFFFA001C) // (TC0) Register C
-#define AT91C_TC0_RB    ((AT91_REG *)   0xFFFA0018) // (TC0) Register B
-#define AT91C_TC0_CCR   ((AT91_REG *)   0xFFFA0000) // (TC0) Channel Control Register
-#define AT91C_TC0_CMR   ((AT91_REG *)   0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC0_IER   ((AT91_REG *)   0xFFFA0024) // (TC0) Interrupt Enable Register
-#define AT91C_TC0_RA    ((AT91_REG *)   0xFFFA0014) // (TC0) Register A
-#define AT91C_TC0_IDR   ((AT91_REG *)   0xFFFA0028) // (TC0) Interrupt Disable Register
-#define AT91C_TC0_CV    ((AT91_REG *)   0xFFFA0010) // (TC0) Counter Value
-#define AT91C_TC0_IMR   ((AT91_REG *)   0xFFFA002C) // (TC0) Interrupt Mask Register
-// ========== Register definition for TC1 peripheral ==========
-#define AT91C_TC1_RB    ((AT91_REG *)   0xFFFA0058) // (TC1) Register B
-#define AT91C_TC1_CCR   ((AT91_REG *)   0xFFFA0040) // (TC1) Channel Control Register
-#define AT91C_TC1_IER   ((AT91_REG *)   0xFFFA0064) // (TC1) Interrupt Enable Register
-#define AT91C_TC1_IDR   ((AT91_REG *)   0xFFFA0068) // (TC1) Interrupt Disable Register
-#define AT91C_TC1_SR    ((AT91_REG *)   0xFFFA0060) // (TC1) Status Register
-#define AT91C_TC1_CMR   ((AT91_REG *)   0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC1_RA    ((AT91_REG *)   0xFFFA0054) // (TC1) Register A
-#define AT91C_TC1_RC    ((AT91_REG *)   0xFFFA005C) // (TC1) Register C
-#define AT91C_TC1_IMR   ((AT91_REG *)   0xFFFA006C) // (TC1) Interrupt Mask Register
-#define AT91C_TC1_CV    ((AT91_REG *)   0xFFFA0050) // (TC1) Counter Value
-// ========== Register definition for TC2 peripheral ==========
-#define AT91C_TC2_CMR   ((AT91_REG *)   0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC2_CCR   ((AT91_REG *)   0xFFFA0080) // (TC2) Channel Control Register
-#define AT91C_TC2_CV    ((AT91_REG *)   0xFFFA0090) // (TC2) Counter Value
-#define AT91C_TC2_RA    ((AT91_REG *)   0xFFFA0094) // (TC2) Register A
-#define AT91C_TC2_RB    ((AT91_REG *)   0xFFFA0098) // (TC2) Register B
-#define AT91C_TC2_IDR   ((AT91_REG *)   0xFFFA00A8) // (TC2) Interrupt Disable Register
-#define AT91C_TC2_IMR   ((AT91_REG *)   0xFFFA00AC) // (TC2) Interrupt Mask Register
-#define AT91C_TC2_RC    ((AT91_REG *)   0xFFFA009C) // (TC2) Register C
-#define AT91C_TC2_IER   ((AT91_REG *)   0xFFFA00A4) // (TC2) Interrupt Enable Register
-#define AT91C_TC2_SR    ((AT91_REG *)   0xFFFA00A0) // (TC2) Status Register
-// ========== Register definition for TCB peripheral ==========
-#define AT91C_TCB_BMR   ((AT91_REG *)   0xFFFA00C4) // (TCB) TC Block Mode Register
-#define AT91C_TCB_BCR   ((AT91_REG *)   0xFFFA00C0) // (TCB) TC Block Control Register
-// ========== Register definition for CAN_MB0 peripheral ==========
-#define AT91C_CAN_MB0_MDL ((AT91_REG *)     0xFFFD0214) // (CAN_MB0) MailBox Data Low Register
-#define AT91C_CAN_MB0_MAM ((AT91_REG *)     0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB0_MCR ((AT91_REG *)     0xFFFD021C) // (CAN_MB0) MailBox Control Register
-#define AT91C_CAN_MB0_MID ((AT91_REG *)     0xFFFD0208) // (CAN_MB0) MailBox ID Register
-#define AT91C_CAN_MB0_MSR ((AT91_REG *)     0xFFFD0210) // (CAN_MB0) MailBox Status Register
-#define AT91C_CAN_MB0_MFID ((AT91_REG *)    0xFFFD020C) // (CAN_MB0) MailBox Family ID Register
-#define AT91C_CAN_MB0_MDH ((AT91_REG *)     0xFFFD0218) // (CAN_MB0) MailBox Data High Register
-#define AT91C_CAN_MB0_MMR ((AT91_REG *)     0xFFFD0200) // (CAN_MB0) MailBox Mode Register
-// ========== Register definition for CAN_MB1 peripheral ==========
-#define AT91C_CAN_MB1_MDL ((AT91_REG *)     0xFFFD0234) // (CAN_MB1) MailBox Data Low Register
-#define AT91C_CAN_MB1_MID ((AT91_REG *)     0xFFFD0228) // (CAN_MB1) MailBox ID Register
-#define AT91C_CAN_MB1_MMR ((AT91_REG *)     0xFFFD0220) // (CAN_MB1) MailBox Mode Register
-#define AT91C_CAN_MB1_MSR ((AT91_REG *)     0xFFFD0230) // (CAN_MB1) MailBox Status Register
-#define AT91C_CAN_MB1_MAM ((AT91_REG *)     0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB1_MDH ((AT91_REG *)     0xFFFD0238) // (CAN_MB1) MailBox Data High Register
-#define AT91C_CAN_MB1_MCR ((AT91_REG *)     0xFFFD023C) // (CAN_MB1) MailBox Control Register
-#define AT91C_CAN_MB1_MFID ((AT91_REG *)    0xFFFD022C) // (CAN_MB1) MailBox Family ID Register
-// ========== Register definition for CAN_MB2 peripheral ==========
-#define AT91C_CAN_MB2_MCR ((AT91_REG *)     0xFFFD025C) // (CAN_MB2) MailBox Control Register
-#define AT91C_CAN_MB2_MDH ((AT91_REG *)     0xFFFD0258) // (CAN_MB2) MailBox Data High Register
-#define AT91C_CAN_MB2_MID ((AT91_REG *)     0xFFFD0248) // (CAN_MB2) MailBox ID Register
-#define AT91C_CAN_MB2_MDL ((AT91_REG *)     0xFFFD0254) // (CAN_MB2) MailBox Data Low Register
-#define AT91C_CAN_MB2_MMR ((AT91_REG *)     0xFFFD0240) // (CAN_MB2) MailBox Mode Register
-#define AT91C_CAN_MB2_MAM ((AT91_REG *)     0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB2_MFID ((AT91_REG *)    0xFFFD024C) // (CAN_MB2) MailBox Family ID Register
-#define AT91C_CAN_MB2_MSR ((AT91_REG *)     0xFFFD0250) // (CAN_MB2) MailBox Status Register
-// ========== Register definition for CAN_MB3 peripheral ==========
-#define AT91C_CAN_MB3_MFID ((AT91_REG *)    0xFFFD026C) // (CAN_MB3) MailBox Family ID Register
-#define AT91C_CAN_MB3_MAM ((AT91_REG *)     0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB3_MID ((AT91_REG *)     0xFFFD0268) // (CAN_MB3) MailBox ID Register
-#define AT91C_CAN_MB3_MCR ((AT91_REG *)     0xFFFD027C) // (CAN_MB3) MailBox Control Register
-#define AT91C_CAN_MB3_MMR ((AT91_REG *)     0xFFFD0260) // (CAN_MB3) MailBox Mode Register
-#define AT91C_CAN_MB3_MSR ((AT91_REG *)     0xFFFD0270) // (CAN_MB3) MailBox Status Register
-#define AT91C_CAN_MB3_MDL ((AT91_REG *)     0xFFFD0274) // (CAN_MB3) MailBox Data Low Register
-#define AT91C_CAN_MB3_MDH ((AT91_REG *)     0xFFFD0278) // (CAN_MB3) MailBox Data High Register
-// ========== Register definition for CAN_MB4 peripheral ==========
-#define AT91C_CAN_MB4_MID ((AT91_REG *)     0xFFFD0288) // (CAN_MB4) MailBox ID Register
-#define AT91C_CAN_MB4_MMR ((AT91_REG *)     0xFFFD0280) // (CAN_MB4) MailBox Mode Register
-#define AT91C_CAN_MB4_MDH ((AT91_REG *)     0xFFFD0298) // (CAN_MB4) MailBox Data High Register
-#define AT91C_CAN_MB4_MFID ((AT91_REG *)    0xFFFD028C) // (CAN_MB4) MailBox Family ID Register
-#define AT91C_CAN_MB4_MSR ((AT91_REG *)     0xFFFD0290) // (CAN_MB4) MailBox Status Register
-#define AT91C_CAN_MB4_MCR ((AT91_REG *)     0xFFFD029C) // (CAN_MB4) MailBox Control Register
-#define AT91C_CAN_MB4_MDL ((AT91_REG *)     0xFFFD0294) // (CAN_MB4) MailBox Data Low Register
-#define AT91C_CAN_MB4_MAM ((AT91_REG *)     0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register
-// ========== Register definition for CAN_MB5 peripheral ==========
-#define AT91C_CAN_MB5_MSR ((AT91_REG *)     0xFFFD02B0) // (CAN_MB5) MailBox Status Register
-#define AT91C_CAN_MB5_MCR ((AT91_REG *)     0xFFFD02BC) // (CAN_MB5) MailBox Control Register
-#define AT91C_CAN_MB5_MFID ((AT91_REG *)    0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register
-#define AT91C_CAN_MB5_MDH ((AT91_REG *)     0xFFFD02B8) // (CAN_MB5) MailBox Data High Register
-#define AT91C_CAN_MB5_MID ((AT91_REG *)     0xFFFD02A8) // (CAN_MB5) MailBox ID Register
-#define AT91C_CAN_MB5_MMR ((AT91_REG *)     0xFFFD02A0) // (CAN_MB5) MailBox Mode Register
-#define AT91C_CAN_MB5_MDL ((AT91_REG *)     0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register
-#define AT91C_CAN_MB5_MAM ((AT91_REG *)     0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register
-// ========== Register definition for CAN_MB6 peripheral ==========
-#define AT91C_CAN_MB6_MFID ((AT91_REG *)    0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register
-#define AT91C_CAN_MB6_MID ((AT91_REG *)     0xFFFD02C8) // (CAN_MB6) MailBox ID Register
-#define AT91C_CAN_MB6_MAM ((AT91_REG *)     0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB6_MSR ((AT91_REG *)     0xFFFD02D0) // (CAN_MB6) MailBox Status Register
-#define AT91C_CAN_MB6_MDL ((AT91_REG *)     0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register
-#define AT91C_CAN_MB6_MCR ((AT91_REG *)     0xFFFD02DC) // (CAN_MB6) MailBox Control Register
-#define AT91C_CAN_MB6_MDH ((AT91_REG *)     0xFFFD02D8) // (CAN_MB6) MailBox Data High Register
-#define AT91C_CAN_MB6_MMR ((AT91_REG *)     0xFFFD02C0) // (CAN_MB6) MailBox Mode Register
-// ========== Register definition for CAN_MB7 peripheral ==========
-#define AT91C_CAN_MB7_MCR ((AT91_REG *)     0xFFFD02FC) // (CAN_MB7) MailBox Control Register
-#define AT91C_CAN_MB7_MDH ((AT91_REG *)     0xFFFD02F8) // (CAN_MB7) MailBox Data High Register
-#define AT91C_CAN_MB7_MFID ((AT91_REG *)    0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register
-#define AT91C_CAN_MB7_MDL ((AT91_REG *)     0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register
-#define AT91C_CAN_MB7_MID ((AT91_REG *)     0xFFFD02E8) // (CAN_MB7) MailBox ID Register
-#define AT91C_CAN_MB7_MMR ((AT91_REG *)     0xFFFD02E0) // (CAN_MB7) MailBox Mode Register
-#define AT91C_CAN_MB7_MAM ((AT91_REG *)     0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB7_MSR ((AT91_REG *)     0xFFFD02F0) // (CAN_MB7) MailBox Status Register
-// ========== Register definition for CAN peripheral ==========
-#define AT91C_CAN_TCR   ((AT91_REG *)   0xFFFD0024) // (CAN) Transfer Command Register
-#define AT91C_CAN_IMR   ((AT91_REG *)   0xFFFD000C) // (CAN) Interrupt Mask Register
-#define AT91C_CAN_IER   ((AT91_REG *)   0xFFFD0004) // (CAN) Interrupt Enable Register
-#define AT91C_CAN_ECR   ((AT91_REG *)   0xFFFD0020) // (CAN) Error Counter Register
-#define AT91C_CAN_TIMESTP ((AT91_REG *)     0xFFFD001C) // (CAN) Time Stamp Register
-#define AT91C_CAN_MR    ((AT91_REG *)   0xFFFD0000) // (CAN) Mode Register
-#define AT91C_CAN_IDR   ((AT91_REG *)   0xFFFD0008) // (CAN) Interrupt Disable Register
-#define AT91C_CAN_ACR   ((AT91_REG *)   0xFFFD0028) // (CAN) Abort Command Register
-#define AT91C_CAN_TIM   ((AT91_REG *)   0xFFFD0018) // (CAN) Timer Register
-#define AT91C_CAN_SR    ((AT91_REG *)   0xFFFD0010) // (CAN) Status Register
-#define AT91C_CAN_BR    ((AT91_REG *)   0xFFFD0014) // (CAN) Baudrate Register
-#define AT91C_CAN_VR    ((AT91_REG *)   0xFFFD00FC) // (CAN) Version Register
-// ========== Register definition for EMAC peripheral ==========
-#define AT91C_EMAC_ISR  ((AT91_REG *)   0xFFFDC024) // (EMAC) Interrupt Status Register
-#define AT91C_EMAC_SA4H ((AT91_REG *)   0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes
-#define AT91C_EMAC_SA1L ((AT91_REG *)   0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes
-#define AT91C_EMAC_ELE  ((AT91_REG *)   0xFFFDC078) // (EMAC) Excessive Length Errors Register
-#define AT91C_EMAC_LCOL ((AT91_REG *)   0xFFFDC05C) // (EMAC) Late Collision Register
-#define AT91C_EMAC_RLE  ((AT91_REG *)   0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register
-#define AT91C_EMAC_WOL  ((AT91_REG *)   0xFFFDC0C4) // (EMAC) Wake On LAN Register
-#define AT91C_EMAC_DTF  ((AT91_REG *)   0xFFFDC058) // (EMAC) Deferred Transmission Frame Register
-#define AT91C_EMAC_TUND ((AT91_REG *)   0xFFFDC064) // (EMAC) Transmit Underrun Error Register
-#define AT91C_EMAC_NCR  ((AT91_REG *)   0xFFFDC000) // (EMAC) Network Control Register
-#define AT91C_EMAC_SA4L ((AT91_REG *)   0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes
-#define AT91C_EMAC_RSR  ((AT91_REG *)   0xFFFDC020) // (EMAC) Receive Status Register
-#define AT91C_EMAC_SA3L ((AT91_REG *)   0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes
-#define AT91C_EMAC_TSR  ((AT91_REG *)   0xFFFDC014) // (EMAC) Transmit Status Register
-#define AT91C_EMAC_IDR  ((AT91_REG *)   0xFFFDC02C) // (EMAC) Interrupt Disable Register
-#define AT91C_EMAC_RSE  ((AT91_REG *)   0xFFFDC074) // (EMAC) Receive Symbol Errors Register
-#define AT91C_EMAC_ECOL ((AT91_REG *)   0xFFFDC060) // (EMAC) Excessive Collision Register
-#define AT91C_EMAC_TID  ((AT91_REG *)   0xFFFDC0B8) // (EMAC) Type ID Checking Register
-#define AT91C_EMAC_HRB  ((AT91_REG *)   0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]
-#define AT91C_EMAC_TBQP ((AT91_REG *)   0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer
-#define AT91C_EMAC_USRIO ((AT91_REG *)  0xFFFDC0C0) // (EMAC) USER Input/Output Register
-#define AT91C_EMAC_PTR  ((AT91_REG *)   0xFFFDC038) // (EMAC) Pause Time Register
-#define AT91C_EMAC_SA2H ((AT91_REG *)   0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes
-#define AT91C_EMAC_ROV  ((AT91_REG *)   0xFFFDC070) // (EMAC) Receive Overrun Errors Register
-#define AT91C_EMAC_ALE  ((AT91_REG *)   0xFFFDC054) // (EMAC) Alignment Error Register
-#define AT91C_EMAC_RJA  ((AT91_REG *)   0xFFFDC07C) // (EMAC) Receive Jabbers Register
-#define AT91C_EMAC_RBQP ((AT91_REG *)   0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer
-#define AT91C_EMAC_TPF  ((AT91_REG *)   0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register
-#define AT91C_EMAC_NCFGR ((AT91_REG *)  0xFFFDC004) // (EMAC) Network Configuration Register
-#define AT91C_EMAC_HRT  ((AT91_REG *)   0xFFFDC094) // (EMAC) Hash Address Top[63:32]
-#define AT91C_EMAC_USF  ((AT91_REG *)   0xFFFDC080) // (EMAC) Undersize Frames Register
-#define AT91C_EMAC_FCSE ((AT91_REG *)   0xFFFDC050) // (EMAC) Frame Check Sequence Error Register
-#define AT91C_EMAC_TPQ  ((AT91_REG *)   0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register
-#define AT91C_EMAC_MAN  ((AT91_REG *)   0xFFFDC034) // (EMAC) PHY Maintenance Register
-#define AT91C_EMAC_FTO  ((AT91_REG *)   0xFFFDC040) // (EMAC) Frames Transmitted OK Register
-#define AT91C_EMAC_REV  ((AT91_REG *)   0xFFFDC0FC) // (EMAC) Revision Register
-#define AT91C_EMAC_IMR  ((AT91_REG *)   0xFFFDC030) // (EMAC) Interrupt Mask Register
-#define AT91C_EMAC_SCF  ((AT91_REG *)   0xFFFDC044) // (EMAC) Single Collision Frame Register
-#define AT91C_EMAC_PFR  ((AT91_REG *)   0xFFFDC03C) // (EMAC) Pause Frames received Register
-#define AT91C_EMAC_MCF  ((AT91_REG *)   0xFFFDC048) // (EMAC) Multiple Collision Frame Register
-#define AT91C_EMAC_NSR  ((AT91_REG *)   0xFFFDC008) // (EMAC) Network Status Register
-#define AT91C_EMAC_SA2L ((AT91_REG *)   0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes
-#define AT91C_EMAC_FRO  ((AT91_REG *)   0xFFFDC04C) // (EMAC) Frames Received OK Register
-#define AT91C_EMAC_IER  ((AT91_REG *)   0xFFFDC028) // (EMAC) Interrupt Enable Register
-#define AT91C_EMAC_SA1H ((AT91_REG *)   0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes
-#define AT91C_EMAC_CSE  ((AT91_REG *)   0xFFFDC068) // (EMAC) Carrier Sense Error Register
-#define AT91C_EMAC_SA3H ((AT91_REG *)   0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes
-#define AT91C_EMAC_RRE  ((AT91_REG *)   0xFFFDC06C) // (EMAC) Receive Ressource Error Register
-#define AT91C_EMAC_STE  ((AT91_REG *)   0xFFFDC084) // (EMAC) SQE Test Error Register
-// ========== Register definition for PDC_ADC peripheral ==========
-#define AT91C_ADC_PTSR  ((AT91_REG *)   0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
-#define AT91C_ADC_PTCR  ((AT91_REG *)   0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
-#define AT91C_ADC_TNPR  ((AT91_REG *)   0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
-#define AT91C_ADC_TNCR  ((AT91_REG *)   0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
-#define AT91C_ADC_RNPR  ((AT91_REG *)   0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
-#define AT91C_ADC_RNCR  ((AT91_REG *)   0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
-#define AT91C_ADC_RPR   ((AT91_REG *)   0xFFFD8100) // (PDC_ADC) Receive Pointer Register
-#define AT91C_ADC_TCR   ((AT91_REG *)   0xFFFD810C) // (PDC_ADC) Transmit Counter Register
-#define AT91C_ADC_TPR   ((AT91_REG *)   0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
-#define AT91C_ADC_RCR   ((AT91_REG *)   0xFFFD8104) // (PDC_ADC) Receive Counter Register
-// ========== Register definition for ADC peripheral ==========
-#define AT91C_ADC_CDR2  ((AT91_REG *)   0xFFFD8038) // (ADC) ADC Channel Data Register 2
-#define AT91C_ADC_CDR3  ((AT91_REG *)   0xFFFD803C) // (ADC) ADC Channel Data Register 3
-#define AT91C_ADC_CDR0  ((AT91_REG *)   0xFFFD8030) // (ADC) ADC Channel Data Register 0
-#define AT91C_ADC_CDR5  ((AT91_REG *)   0xFFFD8044) // (ADC) ADC Channel Data Register 5
-#define AT91C_ADC_CHDR  ((AT91_REG *)   0xFFFD8014) // (ADC) ADC Channel Disable Register
-#define AT91C_ADC_SR    ((AT91_REG *)   0xFFFD801C) // (ADC) ADC Status Register
-#define AT91C_ADC_CDR4  ((AT91_REG *)   0xFFFD8040) // (ADC) ADC Channel Data Register 4
-#define AT91C_ADC_CDR1  ((AT91_REG *)   0xFFFD8034) // (ADC) ADC Channel Data Register 1
-#define AT91C_ADC_LCDR  ((AT91_REG *)   0xFFFD8020) // (ADC) ADC Last Converted Data Register
-#define AT91C_ADC_IDR   ((AT91_REG *)   0xFFFD8028) // (ADC) ADC Interrupt Disable Register
-#define AT91C_ADC_CR    ((AT91_REG *)   0xFFFD8000) // (ADC) ADC Control Register
-#define AT91C_ADC_CDR7  ((AT91_REG *)   0xFFFD804C) // (ADC) ADC Channel Data Register 7
-#define AT91C_ADC_CDR6  ((AT91_REG *)   0xFFFD8048) // (ADC) ADC Channel Data Register 6
-#define AT91C_ADC_IER   ((AT91_REG *)   0xFFFD8024) // (ADC) ADC Interrupt Enable Register
-#define AT91C_ADC_CHER  ((AT91_REG *)   0xFFFD8010) // (ADC) ADC Channel Enable Register
-#define AT91C_ADC_CHSR  ((AT91_REG *)   0xFFFD8018) // (ADC) ADC Channel Status Register
-#define AT91C_ADC_MR    ((AT91_REG *)   0xFFFD8004) // (ADC) ADC Mode Register
-#define AT91C_ADC_IMR   ((AT91_REG *)   0xFFFD802C) // (ADC) ADC Interrupt Mask Register
-// ========== Register definition for PDC_AES peripheral ==========
-#define AT91C_AES_TPR   ((AT91_REG *)   0xFFFA4108) // (PDC_AES) Transmit Pointer Register
-#define AT91C_AES_PTCR  ((AT91_REG *)   0xFFFA4120) // (PDC_AES) PDC Transfer Control Register
-#define AT91C_AES_RNPR  ((AT91_REG *)   0xFFFA4110) // (PDC_AES) Receive Next Pointer Register
-#define AT91C_AES_TNCR  ((AT91_REG *)   0xFFFA411C) // (PDC_AES) Transmit Next Counter Register
-#define AT91C_AES_TCR   ((AT91_REG *)   0xFFFA410C) // (PDC_AES) Transmit Counter Register
-#define AT91C_AES_RCR   ((AT91_REG *)   0xFFFA4104) // (PDC_AES) Receive Counter Register
-#define AT91C_AES_RNCR  ((AT91_REG *)   0xFFFA4114) // (PDC_AES) Receive Next Counter Register
-#define AT91C_AES_TNPR  ((AT91_REG *)   0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register
-#define AT91C_AES_RPR   ((AT91_REG *)   0xFFFA4100) // (PDC_AES) Receive Pointer Register
-#define AT91C_AES_PTSR  ((AT91_REG *)   0xFFFA4124) // (PDC_AES) PDC Transfer Status Register
-// ========== Register definition for AES peripheral ==========
-#define AT91C_AES_IVxR  ((AT91_REG *)   0xFFFA4060) // (AES) Initialization Vector x Register
-#define AT91C_AES_MR    ((AT91_REG *)   0xFFFA4004) // (AES) Mode Register
-#define AT91C_AES_VR    ((AT91_REG *)   0xFFFA40FC) // (AES) AES Version Register
-#define AT91C_AES_ODATAxR ((AT91_REG *)     0xFFFA4050) // (AES) Output Data x Register
-#define AT91C_AES_IDATAxR ((AT91_REG *)     0xFFFA4040) // (AES) Input Data x Register
-#define AT91C_AES_CR    ((AT91_REG *)   0xFFFA4000) // (AES) Control Register
-#define AT91C_AES_IDR   ((AT91_REG *)   0xFFFA4014) // (AES) Interrupt Disable Register
-#define AT91C_AES_IMR   ((AT91_REG *)   0xFFFA4018) // (AES) Interrupt Mask Register
-#define AT91C_AES_IER   ((AT91_REG *)   0xFFFA4010) // (AES) Interrupt Enable Register
-#define AT91C_AES_KEYWxR ((AT91_REG *)  0xFFFA4020) // (AES) Key Word x Register
-#define AT91C_AES_ISR   ((AT91_REG *)   0xFFFA401C) // (AES) Interrupt Status Register
-// ========== Register definition for PDC_TDES peripheral ==========
-#define AT91C_TDES_RNCR ((AT91_REG *)   0xFFFA8114) // (PDC_TDES) Receive Next Counter Register
-#define AT91C_TDES_TCR  ((AT91_REG *)   0xFFFA810C) // (PDC_TDES) Transmit Counter Register
-#define AT91C_TDES_RCR  ((AT91_REG *)   0xFFFA8104) // (PDC_TDES) Receive Counter Register
-#define AT91C_TDES_TNPR ((AT91_REG *)   0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register
-#define AT91C_TDES_RNPR ((AT91_REG *)   0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register
-#define AT91C_TDES_RPR  ((AT91_REG *)   0xFFFA8100) // (PDC_TDES) Receive Pointer Register
-#define AT91C_TDES_TNCR ((AT91_REG *)   0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register
-#define AT91C_TDES_TPR  ((AT91_REG *)   0xFFFA8108) // (PDC_TDES) Transmit Pointer Register
-#define AT91C_TDES_PTSR ((AT91_REG *)   0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register
-#define AT91C_TDES_PTCR ((AT91_REG *)   0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register
-// ========== Register definition for TDES peripheral ==========
-#define AT91C_TDES_KEY2WxR ((AT91_REG *)    0xFFFA8028) // (TDES) Key 2 Word x Register
-#define AT91C_TDES_KEY3WxR ((AT91_REG *)    0xFFFA8030) // (TDES) Key 3 Word x Register
-#define AT91C_TDES_IDR  ((AT91_REG *)   0xFFFA8014) // (TDES) Interrupt Disable Register
-#define AT91C_TDES_VR   ((AT91_REG *)   0xFFFA80FC) // (TDES) TDES Version Register
-#define AT91C_TDES_IVxR ((AT91_REG *)   0xFFFA8060) // (TDES) Initialization Vector x Register
-#define AT91C_TDES_ODATAxR ((AT91_REG *)    0xFFFA8050) // (TDES) Output Data x Register
-#define AT91C_TDES_IMR  ((AT91_REG *)   0xFFFA8018) // (TDES) Interrupt Mask Register
-#define AT91C_TDES_MR   ((AT91_REG *)   0xFFFA8004) // (TDES) Mode Register
-#define AT91C_TDES_CR   ((AT91_REG *)   0xFFFA8000) // (TDES) Control Register
-#define AT91C_TDES_IER  ((AT91_REG *)   0xFFFA8010) // (TDES) Interrupt Enable Register
-#define AT91C_TDES_ISR  ((AT91_REG *)   0xFFFA801C) // (TDES) Interrupt Status Register
-#define AT91C_TDES_IDATAxR ((AT91_REG *)    0xFFFA8040) // (TDES) Input Data x Register
-#define AT91C_TDES_KEY1WxR ((AT91_REG *)    0xFFFA8020) // (TDES) Key 1 Word x Register
+/* ***************************************************************************** */
+/*               REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 */
+/* ***************************************************************************** */
+/* ========== Register definition for SYS peripheral ========== */
+/* ========== Register definition for AIC peripheral ========== */
+#define AT91C_AIC_IVR              ( ( AT91_REG * ) 0xFFFFF100 ) /* (AIC) IRQ Vector Register */
+#define AT91C_AIC_SMR              ( ( AT91_REG * ) 0xFFFFF000 ) /* (AIC) Source Mode Register */
+#define AT91C_AIC_FVR              ( ( AT91_REG * ) 0xFFFFF104 ) /* (AIC) FIQ Vector Register */
+#define AT91C_AIC_DCR              ( ( AT91_REG * ) 0xFFFFF138 ) /* (AIC) Debug Control Register (Protect) */
+#define AT91C_AIC_EOICR            ( ( AT91_REG * ) 0xFFFFF130 ) /* (AIC) End of Interrupt Command Register */
+#define AT91C_AIC_SVR              ( ( AT91_REG * ) 0xFFFFF080 ) /* (AIC) Source Vector Register */
+#define AT91C_AIC_FFSR             ( ( AT91_REG * ) 0xFFFFF148 ) /* (AIC) Fast Forcing Status Register */
+#define AT91C_AIC_ICCR             ( ( AT91_REG * ) 0xFFFFF128 ) /* (AIC) Interrupt Clear Command Register */
+#define AT91C_AIC_ISR              ( ( AT91_REG * ) 0xFFFFF108 ) /* (AIC) Interrupt Status Register */
+#define AT91C_AIC_IMR              ( ( AT91_REG * ) 0xFFFFF110 ) /* (AIC) Interrupt Mask Register */
+#define AT91C_AIC_IPR              ( ( AT91_REG * ) 0xFFFFF10C ) /* (AIC) Interrupt Pending Register */
+#define AT91C_AIC_FFER             ( ( AT91_REG * ) 0xFFFFF140 ) /* (AIC) Fast Forcing Enable Register */
+#define AT91C_AIC_IECR             ( ( AT91_REG * ) 0xFFFFF120 ) /* (AIC) Interrupt Enable Command Register */
+#define AT91C_AIC_ISCR             ( ( AT91_REG * ) 0xFFFFF12C ) /* (AIC) Interrupt Set Command Register */
+#define AT91C_AIC_FFDR             ( ( AT91_REG * ) 0xFFFFF144 ) /* (AIC) Fast Forcing Disable Register */
+#define AT91C_AIC_CISR             ( ( AT91_REG * ) 0xFFFFF114 ) /* (AIC) Core Interrupt Status Register */
+#define AT91C_AIC_IDCR             ( ( AT91_REG * ) 0xFFFFF124 ) /* (AIC) Interrupt Disable Command Register */
+#define AT91C_AIC_SPU              ( ( AT91_REG * ) 0xFFFFF134 ) /* (AIC) Spurious Vector Register */
+/* ========== Register definition for PDC_DBGU peripheral ========== */
+#define AT91C_DBGU_TCR             ( ( AT91_REG * ) 0xFFFFF30C ) /* (PDC_DBGU) Transmit Counter Register */
+#define AT91C_DBGU_RNPR            ( ( AT91_REG * ) 0xFFFFF310 ) /* (PDC_DBGU) Receive Next Pointer Register */
+#define AT91C_DBGU_TNPR            ( ( AT91_REG * ) 0xFFFFF318 ) /* (PDC_DBGU) Transmit Next Pointer Register */
+#define AT91C_DBGU_TPR             ( ( AT91_REG * ) 0xFFFFF308 ) /* (PDC_DBGU) Transmit Pointer Register */
+#define AT91C_DBGU_RPR             ( ( AT91_REG * ) 0xFFFFF300 ) /* (PDC_DBGU) Receive Pointer Register */
+#define AT91C_DBGU_RCR             ( ( AT91_REG * ) 0xFFFFF304 ) /* (PDC_DBGU) Receive Counter Register */
+#define AT91C_DBGU_RNCR            ( ( AT91_REG * ) 0xFFFFF314 ) /* (PDC_DBGU) Receive Next Counter Register */
+#define AT91C_DBGU_PTCR            ( ( AT91_REG * ) 0xFFFFF320 ) /* (PDC_DBGU) PDC Transfer Control Register */
+#define AT91C_DBGU_PTSR            ( ( AT91_REG * ) 0xFFFFF324 ) /* (PDC_DBGU) PDC Transfer Status Register */
+#define AT91C_DBGU_TNCR            ( ( AT91_REG * ) 0xFFFFF31C ) /* (PDC_DBGU) Transmit Next Counter Register */
+/* ========== Register definition for DBGU peripheral ========== */
+#define AT91C_DBGU_EXID            ( ( AT91_REG * ) 0xFFFFF244 ) /* (DBGU) Chip ID Extension Register */
+#define AT91C_DBGU_BRGR            ( ( AT91_REG * ) 0xFFFFF220 ) /* (DBGU) Baud Rate Generator Register */
+#define AT91C_DBGU_IDR             ( ( AT91_REG * ) 0xFFFFF20C ) /* (DBGU) Interrupt Disable Register */
+#define AT91C_DBGU_CSR             ( ( AT91_REG * ) 0xFFFFF214 ) /* (DBGU) Channel Status Register */
+#define AT91C_DBGU_CIDR            ( ( AT91_REG * ) 0xFFFFF240 ) /* (DBGU) Chip ID Register */
+#define AT91C_DBGU_MR              ( ( AT91_REG * ) 0xFFFFF204 ) /* (DBGU) Mode Register */
+#define AT91C_DBGU_IMR             ( ( AT91_REG * ) 0xFFFFF210 ) /* (DBGU) Interrupt Mask Register */
+#define AT91C_DBGU_CR              ( ( AT91_REG * ) 0xFFFFF200 ) /* (DBGU) Control Register */
+#define AT91C_DBGU_FNTR            ( ( AT91_REG * ) 0xFFFFF248 ) /* (DBGU) Force NTRST Register */
+#define AT91C_DBGU_THR             ( ( AT91_REG * ) 0xFFFFF21C ) /* (DBGU) Transmitter Holding Register */
+#define AT91C_DBGU_RHR             ( ( AT91_REG * ) 0xFFFFF218 ) /* (DBGU) Receiver Holding Register */
+#define AT91C_DBGU_IER             ( ( AT91_REG * ) 0xFFFFF208 ) /* (DBGU) Interrupt Enable Register */
+/* ========== Register definition for PIOA peripheral ========== */
+#define AT91C_PIOA_ODR             ( ( AT91_REG * ) 0xFFFFF414 ) /* (PIOA) Output Disable Registerr */
+#define AT91C_PIOA_SODR            ( ( AT91_REG * ) 0xFFFFF430 ) /* (PIOA) Set Output Data Register */
+#define AT91C_PIOA_ISR             ( ( AT91_REG * ) 0xFFFFF44C ) /* (PIOA) Interrupt Status Register */
+#define AT91C_PIOA_ABSR            ( ( AT91_REG * ) 0xFFFFF478 ) /* (PIOA) AB Select Status Register */
+#define AT91C_PIOA_IER             ( ( AT91_REG * ) 0xFFFFF440 ) /* (PIOA) Interrupt Enable Register */
+#define AT91C_PIOA_PPUDR           ( ( AT91_REG * ) 0xFFFFF460 ) /* (PIOA) Pull-up Disable Register */
+#define AT91C_PIOA_IMR             ( ( AT91_REG * ) 0xFFFFF448 ) /* (PIOA) Interrupt Mask Register */
+#define AT91C_PIOA_PER             ( ( AT91_REG * ) 0xFFFFF400 ) /* (PIOA) PIO Enable Register */
+#define AT91C_PIOA_IFDR            ( ( AT91_REG * ) 0xFFFFF424 ) /* (PIOA) Input Filter Disable Register */
+#define AT91C_PIOA_OWDR            ( ( AT91_REG * ) 0xFFFFF4A4 ) /* (PIOA) Output Write Disable Register */
+#define AT91C_PIOA_MDSR            ( ( AT91_REG * ) 0xFFFFF458 ) /* (PIOA) Multi-driver Status Register */
+#define AT91C_PIOA_IDR             ( ( AT91_REG * ) 0xFFFFF444 ) /* (PIOA) Interrupt Disable Register */
+#define AT91C_PIOA_ODSR            ( ( AT91_REG * ) 0xFFFFF438 ) /* (PIOA) Output Data Status Register */
+#define AT91C_PIOA_PPUSR           ( ( AT91_REG * ) 0xFFFFF468 ) /* (PIOA) Pull-up Status Register */
+#define AT91C_PIOA_OWSR            ( ( AT91_REG * ) 0xFFFFF4A8 ) /* (PIOA) Output Write Status Register */
+#define AT91C_PIOA_BSR             ( ( AT91_REG * ) 0xFFFFF474 ) /* (PIOA) Select B Register */
+#define AT91C_PIOA_OWER            ( ( AT91_REG * ) 0xFFFFF4A0 ) /* (PIOA) Output Write Enable Register */
+#define AT91C_PIOA_IFER            ( ( AT91_REG * ) 0xFFFFF420 ) /* (PIOA) Input Filter Enable Register */
+#define AT91C_PIOA_PDSR            ( ( AT91_REG * ) 0xFFFFF43C ) /* (PIOA) Pin Data Status Register */
+#define AT91C_PIOA_PPUER           ( ( AT91_REG * ) 0xFFFFF464 ) /* (PIOA) Pull-up Enable Register */
+#define AT91C_PIOA_OSR             ( ( AT91_REG * ) 0xFFFFF418 ) /* (PIOA) Output Status Register */
+#define AT91C_PIOA_ASR             ( ( AT91_REG * ) 0xFFFFF470 ) /* (PIOA) Select A Register */
+#define AT91C_PIOA_MDDR            ( ( AT91_REG * ) 0xFFFFF454 ) /* (PIOA) Multi-driver Disable Register */
+#define AT91C_PIOA_CODR            ( ( AT91_REG * ) 0xFFFFF434 ) /* (PIOA) Clear Output Data Register */
+#define AT91C_PIOA_MDER            ( ( AT91_REG * ) 0xFFFFF450 ) /* (PIOA) Multi-driver Enable Register */
+#define AT91C_PIOA_PDR             ( ( AT91_REG * ) 0xFFFFF404 ) /* (PIOA) PIO Disable Register */
+#define AT91C_PIOA_IFSR            ( ( AT91_REG * ) 0xFFFFF428 ) /* (PIOA) Input Filter Status Register */
+#define AT91C_PIOA_OER             ( ( AT91_REG * ) 0xFFFFF410 ) /* (PIOA) Output Enable Register */
+#define AT91C_PIOA_PSR             ( ( AT91_REG * ) 0xFFFFF408 ) /* (PIOA) PIO Status Register */
+/* ========== Register definition for PIOB peripheral ========== */
+#define AT91C_PIOB_OWDR            ( ( AT91_REG * ) 0xFFFFF6A4 ) /* (PIOB) Output Write Disable Register */
+#define AT91C_PIOB_MDER            ( ( AT91_REG * ) 0xFFFFF650 ) /* (PIOB) Multi-driver Enable Register */
+#define AT91C_PIOB_PPUSR           ( ( AT91_REG * ) 0xFFFFF668 ) /* (PIOB) Pull-up Status Register */
+#define AT91C_PIOB_IMR             ( ( AT91_REG * ) 0xFFFFF648 ) /* (PIOB) Interrupt Mask Register */
+#define AT91C_PIOB_ASR             ( ( AT91_REG * ) 0xFFFFF670 ) /* (PIOB) Select A Register */
+#define AT91C_PIOB_PPUDR           ( ( AT91_REG * ) 0xFFFFF660 ) /* (PIOB) Pull-up Disable Register */
+#define AT91C_PIOB_PSR             ( ( AT91_REG * ) 0xFFFFF608 ) /* (PIOB) PIO Status Register */
+#define AT91C_PIOB_IER             ( ( AT91_REG * ) 0xFFFFF640 ) /* (PIOB) Interrupt Enable Register */
+#define AT91C_PIOB_CODR            ( ( AT91_REG * ) 0xFFFFF634 ) /* (PIOB) Clear Output Data Register */
+#define AT91C_PIOB_OWER            ( ( AT91_REG * ) 0xFFFFF6A0 ) /* (PIOB) Output Write Enable Register */
+#define AT91C_PIOB_ABSR            ( ( AT91_REG * ) 0xFFFFF678 ) /* (PIOB) AB Select Status Register */
+#define AT91C_PIOB_IFDR            ( ( AT91_REG * ) 0xFFFFF624 ) /* (PIOB) Input Filter Disable Register */
+#define AT91C_PIOB_PDSR            ( ( AT91_REG * ) 0xFFFFF63C ) /* (PIOB) Pin Data Status Register */
+#define AT91C_PIOB_IDR             ( ( AT91_REG * ) 0xFFFFF644 ) /* (PIOB) Interrupt Disable Register */
+#define AT91C_PIOB_OWSR            ( ( AT91_REG * ) 0xFFFFF6A8 ) /* (PIOB) Output Write Status Register */
+#define AT91C_PIOB_PDR             ( ( AT91_REG * ) 0xFFFFF604 ) /* (PIOB) PIO Disable Register */
+#define AT91C_PIOB_ODR             ( ( AT91_REG * ) 0xFFFFF614 ) /* (PIOB) Output Disable Registerr */
+#define AT91C_PIOB_IFSR            ( ( AT91_REG * ) 0xFFFFF628 ) /* (PIOB) Input Filter Status Register */
+#define AT91C_PIOB_PPUER           ( ( AT91_REG * ) 0xFFFFF664 ) /* (PIOB) Pull-up Enable Register */
+#define AT91C_PIOB_SODR            ( ( AT91_REG * ) 0xFFFFF630 ) /* (PIOB) Set Output Data Register */
+#define AT91C_PIOB_ISR             ( ( AT91_REG * ) 0xFFFFF64C ) /* (PIOB) Interrupt Status Register */
+#define AT91C_PIOB_ODSR            ( ( AT91_REG * ) 0xFFFFF638 ) /* (PIOB) Output Data Status Register */
+#define AT91C_PIOB_OSR             ( ( AT91_REG * ) 0xFFFFF618 ) /* (PIOB) Output Status Register */
+#define AT91C_PIOB_MDSR            ( ( AT91_REG * ) 0xFFFFF658 ) /* (PIOB) Multi-driver Status Register */
+#define AT91C_PIOB_IFER            ( ( AT91_REG * ) 0xFFFFF620 ) /* (PIOB) Input Filter Enable Register */
+#define AT91C_PIOB_BSR             ( ( AT91_REG * ) 0xFFFFF674 ) /* (PIOB) Select B Register */
+#define AT91C_PIOB_MDDR            ( ( AT91_REG * ) 0xFFFFF654 ) /* (PIOB) Multi-driver Disable Register */
+#define AT91C_PIOB_OER             ( ( AT91_REG * ) 0xFFFFF610 ) /* (PIOB) Output Enable Register */
+#define AT91C_PIOB_PER             ( ( AT91_REG * ) 0xFFFFF600 ) /* (PIOB) PIO Enable Register */
+/* ========== Register definition for CKGR peripheral ========== */
+#define AT91C_CKGR_MOR             ( ( AT91_REG * ) 0xFFFFFC20 ) /* (CKGR) Main Oscillator Register */
+#define AT91C_CKGR_PLLR            ( ( AT91_REG * ) 0xFFFFFC2C ) /* (CKGR) PLL Register */
+#define AT91C_CKGR_MCFR            ( ( AT91_REG * ) 0xFFFFFC24 ) /* (CKGR) Main Clock  Frequency Register */
+/* ========== Register definition for PMC peripheral ========== */
+#define AT91C_PMC_IDR              ( ( AT91_REG * ) 0xFFFFFC64 ) /* (PMC) Interrupt Disable Register */
+#define AT91C_PMC_MOR              ( ( AT91_REG * ) 0xFFFFFC20 ) /* (PMC) Main Oscillator Register */
+#define AT91C_PMC_PLLR             ( ( AT91_REG * ) 0xFFFFFC2C ) /* (PMC) PLL Register */
+#define AT91C_PMC_PCER             ( ( AT91_REG * ) 0xFFFFFC10 ) /* (PMC) Peripheral Clock Enable Register */
+#define AT91C_PMC_PCKR             ( ( AT91_REG * ) 0xFFFFFC40 ) /* (PMC) Programmable Clock Register */
+#define AT91C_PMC_MCKR             ( ( AT91_REG * ) 0xFFFFFC30 ) /* (PMC) Master Clock Register */
+#define AT91C_PMC_SCDR             ( ( AT91_REG * ) 0xFFFFFC04 ) /* (PMC) System Clock Disable Register */
+#define AT91C_PMC_PCDR             ( ( AT91_REG * ) 0xFFFFFC14 ) /* (PMC) Peripheral Clock Disable Register */
+#define AT91C_PMC_SCSR             ( ( AT91_REG * ) 0xFFFFFC08 ) /* (PMC) System Clock Status Register */
+#define AT91C_PMC_PCSR             ( ( AT91_REG * ) 0xFFFFFC18 ) /* (PMC) Peripheral Clock Status Register */
+#define AT91C_PMC_MCFR             ( ( AT91_REG * ) 0xFFFFFC24 ) /* (PMC) Main Clock  Frequency Register */
+#define AT91C_PMC_SCER             ( ( AT91_REG * ) 0xFFFFFC00 ) /* (PMC) System Clock Enable Register */
+#define AT91C_PMC_IMR              ( ( AT91_REG * ) 0xFFFFFC6C ) /* (PMC) Interrupt Mask Register */
+#define AT91C_PMC_IER              ( ( AT91_REG * ) 0xFFFFFC60 ) /* (PMC) Interrupt Enable Register */
+#define AT91C_PMC_SR               ( ( AT91_REG * ) 0xFFFFFC68 ) /* (PMC) Status Register */
+/* ========== Register definition for RSTC peripheral ========== */
+#define AT91C_RSTC_RCR             ( ( AT91_REG * ) 0xFFFFFD00 ) /* (RSTC) Reset Control Register */
+#define AT91C_RSTC_RMR             ( ( AT91_REG * ) 0xFFFFFD08 ) /* (RSTC) Reset Mode Register */
+#define AT91C_RSTC_RSR             ( ( AT91_REG * ) 0xFFFFFD04 ) /* (RSTC) Reset Status Register */
+/* ========== Register definition for RTTC peripheral ========== */
+#define AT91C_RTTC_RTSR            ( ( AT91_REG * ) 0xFFFFFD2C ) /* (RTTC) Real-time Status Register */
+#define AT91C_RTTC_RTMR            ( ( AT91_REG * ) 0xFFFFFD20 ) /* (RTTC) Real-time Mode Register */
+#define AT91C_RTTC_RTVR            ( ( AT91_REG * ) 0xFFFFFD28 ) /* (RTTC) Real-time Value Register */
+#define AT91C_RTTC_RTAR            ( ( AT91_REG * ) 0xFFFFFD24 ) /* (RTTC) Real-time Alarm Register */
+/* ========== Register definition for PITC peripheral ========== */
+#define AT91C_PITC_PIVR            ( ( AT91_REG * ) 0xFFFFFD38 ) /* (PITC) Period Interval Value Register */
+#define AT91C_PITC_PISR            ( ( AT91_REG * ) 0xFFFFFD34 ) /* (PITC) Period Interval Status Register */
+#define AT91C_PITC_PIIR            ( ( AT91_REG * ) 0xFFFFFD3C ) /* (PITC) Period Interval Image Register */
+#define AT91C_PITC_PIMR            ( ( AT91_REG * ) 0xFFFFFD30 ) /* (PITC) Period Interval Mode Register */
+/* ========== Register definition for WDTC peripheral ========== */
+#define AT91C_WDTC_WDCR            ( ( AT91_REG * ) 0xFFFFFD40 ) /* (WDTC) Watchdog Control Register */
+#define AT91C_WDTC_WDSR            ( ( AT91_REG * ) 0xFFFFFD48 ) /* (WDTC) Watchdog Status Register */
+#define AT91C_WDTC_WDMR            ( ( AT91_REG * ) 0xFFFFFD44 ) /* (WDTC) Watchdog Mode Register */
+/* ========== Register definition for VREG peripheral ========== */
+#define AT91C_VREG_MR              ( ( AT91_REG * ) 0xFFFFFD60 ) /* (VREG) Voltage Regulator Mode Register */
+/* ========== Register definition for MC peripheral ========== */
+#define AT91C_MC_ASR               ( ( AT91_REG * ) 0xFFFFFF04 ) /* (MC) MC Abort Status Register */
+#define AT91C_MC_RCR               ( ( AT91_REG * ) 0xFFFFFF00 ) /* (MC) MC Remap Control Register */
+#define AT91C_MC_FCR               ( ( AT91_REG * ) 0xFFFFFF64 ) /* (MC) MC Flash Command Register */
+#define AT91C_MC_AASR              ( ( AT91_REG * ) 0xFFFFFF08 ) /* (MC) MC Abort Address Status Register */
+#define AT91C_MC_FSR               ( ( AT91_REG * ) 0xFFFFFF68 ) /* (MC) MC Flash Status Register */
+#define AT91C_MC_FMR               ( ( AT91_REG * ) 0xFFFFFF60 ) /* (MC) MC Flash Mode Register */
+/* ========== Register definition for PDC_SPI1 peripheral ========== */
+#define AT91C_SPI1_PTCR            ( ( AT91_REG * ) 0xFFFE4120 ) /* (PDC_SPI1) PDC Transfer Control Register */
+#define AT91C_SPI1_RPR             ( ( AT91_REG * ) 0xFFFE4100 ) /* (PDC_SPI1) Receive Pointer Register */
+#define AT91C_SPI1_TNCR            ( ( AT91_REG * ) 0xFFFE411C ) /* (PDC_SPI1) Transmit Next Counter Register */
+#define AT91C_SPI1_TPR             ( ( AT91_REG * ) 0xFFFE4108 ) /* (PDC_SPI1) Transmit Pointer Register */
+#define AT91C_SPI1_TNPR            ( ( AT91_REG * ) 0xFFFE4118 ) /* (PDC_SPI1) Transmit Next Pointer Register */
+#define AT91C_SPI1_TCR             ( ( AT91_REG * ) 0xFFFE410C ) /* (PDC_SPI1) Transmit Counter Register */
+#define AT91C_SPI1_RCR             ( ( AT91_REG * ) 0xFFFE4104 ) /* (PDC_SPI1) Receive Counter Register */
+#define AT91C_SPI1_RNPR            ( ( AT91_REG * ) 0xFFFE4110 ) /* (PDC_SPI1) Receive Next Pointer Register */
+#define AT91C_SPI1_RNCR            ( ( AT91_REG * ) 0xFFFE4114 ) /* (PDC_SPI1) Receive Next Counter Register */
+#define AT91C_SPI1_PTSR            ( ( AT91_REG * ) 0xFFFE4124 ) /* (PDC_SPI1) PDC Transfer Status Register */
+/* ========== Register definition for SPI1 peripheral ========== */
+#define AT91C_SPI1_IMR             ( ( AT91_REG * ) 0xFFFE401C ) /* (SPI1) Interrupt Mask Register */
+#define AT91C_SPI1_IER             ( ( AT91_REG * ) 0xFFFE4014 ) /* (SPI1) Interrupt Enable Register */
+#define AT91C_SPI1_MR              ( ( AT91_REG * ) 0xFFFE4004 ) /* (SPI1) Mode Register */
+#define AT91C_SPI1_RDR             ( ( AT91_REG * ) 0xFFFE4008 ) /* (SPI1) Receive Data Register */
+#define AT91C_SPI1_IDR             ( ( AT91_REG * ) 0xFFFE4018 ) /* (SPI1) Interrupt Disable Register */
+#define AT91C_SPI1_SR              ( ( AT91_REG * ) 0xFFFE4010 ) /* (SPI1) Status Register */
+#define AT91C_SPI1_TDR             ( ( AT91_REG * ) 0xFFFE400C ) /* (SPI1) Transmit Data Register */
+#define AT91C_SPI1_CR              ( ( AT91_REG * ) 0xFFFE4000 ) /* (SPI1) Control Register */
+#define AT91C_SPI1_CSR             ( ( AT91_REG * ) 0xFFFE4030 ) /* (SPI1) Chip Select Register */
+/* ========== Register definition for PDC_SPI0 peripheral ========== */
+#define AT91C_SPI0_PTCR            ( ( AT91_REG * ) 0xFFFE0120 ) /* (PDC_SPI0) PDC Transfer Control Register */
+#define AT91C_SPI0_TPR             ( ( AT91_REG * ) 0xFFFE0108 ) /* (PDC_SPI0) Transmit Pointer Register */
+#define AT91C_SPI0_TCR             ( ( AT91_REG * ) 0xFFFE010C ) /* (PDC_SPI0) Transmit Counter Register */
+#define AT91C_SPI0_RCR             ( ( AT91_REG * ) 0xFFFE0104 ) /* (PDC_SPI0) Receive Counter Register */
+#define AT91C_SPI0_PTSR            ( ( AT91_REG * ) 0xFFFE0124 ) /* (PDC_SPI0) PDC Transfer Status Register */
+#define AT91C_SPI0_RNPR            ( ( AT91_REG * ) 0xFFFE0110 ) /* (PDC_SPI0) Receive Next Pointer Register */
+#define AT91C_SPI0_RPR             ( ( AT91_REG * ) 0xFFFE0100 ) /* (PDC_SPI0) Receive Pointer Register */
+#define AT91C_SPI0_TNCR            ( ( AT91_REG * ) 0xFFFE011C ) /* (PDC_SPI0) Transmit Next Counter Register */
+#define AT91C_SPI0_RNCR            ( ( AT91_REG * ) 0xFFFE0114 ) /* (PDC_SPI0) Receive Next Counter Register */
+#define AT91C_SPI0_TNPR            ( ( AT91_REG * ) 0xFFFE0118 ) /* (PDC_SPI0) Transmit Next Pointer Register */
+/* ========== Register definition for SPI0 peripheral ========== */
+#define AT91C_SPI0_IER             ( ( AT91_REG * ) 0xFFFE0014 ) /* (SPI0) Interrupt Enable Register */
+#define AT91C_SPI0_SR              ( ( AT91_REG * ) 0xFFFE0010 ) /* (SPI0) Status Register */
+#define AT91C_SPI0_IDR             ( ( AT91_REG * ) 0xFFFE0018 ) /* (SPI0) Interrupt Disable Register */
+#define AT91C_SPI0_CR              ( ( AT91_REG * ) 0xFFFE0000 ) /* (SPI0) Control Register */
+#define AT91C_SPI0_MR              ( ( AT91_REG * ) 0xFFFE0004 ) /* (SPI0) Mode Register */
+#define AT91C_SPI0_IMR             ( ( AT91_REG * ) 0xFFFE001C ) /* (SPI0) Interrupt Mask Register */
+#define AT91C_SPI0_TDR             ( ( AT91_REG * ) 0xFFFE000C ) /* (SPI0) Transmit Data Register */
+#define AT91C_SPI0_RDR             ( ( AT91_REG * ) 0xFFFE0008 ) /* (SPI0) Receive Data Register */
+#define AT91C_SPI0_CSR             ( ( AT91_REG * ) 0xFFFE0030 ) /* (SPI0) Chip Select Register */
+/* ========== Register definition for PDC_US1 peripheral ========== */
+#define AT91C_US1_RNCR             ( ( AT91_REG * ) 0xFFFC4114 ) /* (PDC_US1) Receive Next Counter Register */
+#define AT91C_US1_PTCR             ( ( AT91_REG * ) 0xFFFC4120 ) /* (PDC_US1) PDC Transfer Control Register */
+#define AT91C_US1_TCR              ( ( AT91_REG * ) 0xFFFC410C ) /* (PDC_US1) Transmit Counter Register */
+#define AT91C_US1_PTSR             ( ( AT91_REG * ) 0xFFFC4124 ) /* (PDC_US1) PDC Transfer Status Register */
+#define AT91C_US1_TNPR             ( ( AT91_REG * ) 0xFFFC4118 ) /* (PDC_US1) Transmit Next Pointer Register */
+#define AT91C_US1_RCR              ( ( AT91_REG * ) 0xFFFC4104 ) /* (PDC_US1) Receive Counter Register */
+#define AT91C_US1_RNPR             ( ( AT91_REG * ) 0xFFFC4110 ) /* (PDC_US1) Receive Next Pointer Register */
+#define AT91C_US1_RPR              ( ( AT91_REG * ) 0xFFFC4100 ) /* (PDC_US1) Receive Pointer Register */
+#define AT91C_US1_TNCR             ( ( AT91_REG * ) 0xFFFC411C ) /* (PDC_US1) Transmit Next Counter Register */
+#define AT91C_US1_TPR              ( ( AT91_REG * ) 0xFFFC4108 ) /* (PDC_US1) Transmit Pointer Register */
+/* ========== Register definition for US1 peripheral ========== */
+#define AT91C_US1_IF               ( ( AT91_REG * ) 0xFFFC404C ) /* (US1) IRDA_FILTER Register */
+#define AT91C_US1_NER              ( ( AT91_REG * ) 0xFFFC4044 ) /* (US1) Nb Errors Register */
+#define AT91C_US1_RTOR             ( ( AT91_REG * ) 0xFFFC4024 ) /* (US1) Receiver Time-out Register */
+#define AT91C_US1_CSR              ( ( AT91_REG * ) 0xFFFC4014 ) /* (US1) Channel Status Register */
+#define AT91C_US1_IDR              ( ( AT91_REG * ) 0xFFFC400C ) /* (US1) Interrupt Disable Register */
+#define AT91C_US1_IER              ( ( AT91_REG * ) 0xFFFC4008 ) /* (US1) Interrupt Enable Register */
+#define AT91C_US1_THR              ( ( AT91_REG * ) 0xFFFC401C ) /* (US1) Transmitter Holding Register */
+#define AT91C_US1_TTGR             ( ( AT91_REG * ) 0xFFFC4028 ) /* (US1) Transmitter Time-guard Register */
+#define AT91C_US1_RHR              ( ( AT91_REG * ) 0xFFFC4018 ) /* (US1) Receiver Holding Register */
+#define AT91C_US1_BRGR             ( ( AT91_REG * ) 0xFFFC4020 ) /* (US1) Baud Rate Generator Register */
+#define AT91C_US1_IMR              ( ( AT91_REG * ) 0xFFFC4010 ) /* (US1) Interrupt Mask Register */
+#define AT91C_US1_FIDI             ( ( AT91_REG * ) 0xFFFC4040 ) /* (US1) FI_DI_Ratio Register */
+#define AT91C_US1_CR               ( ( AT91_REG * ) 0xFFFC4000 ) /* (US1) Control Register */
+#define AT91C_US1_MR               ( ( AT91_REG * ) 0xFFFC4004 ) /* (US1) Mode Register */
+/* ========== Register definition for PDC_US0 peripheral ========== */
+#define AT91C_US0_TNPR             ( ( AT91_REG * ) 0xFFFC0118 ) /* (PDC_US0) Transmit Next Pointer Register */
+#define AT91C_US0_RNPR             ( ( AT91_REG * ) 0xFFFC0110 ) /* (PDC_US0) Receive Next Pointer Register */
+#define AT91C_US0_TCR              ( ( AT91_REG * ) 0xFFFC010C ) /* (PDC_US0) Transmit Counter Register */
+#define AT91C_US0_PTCR             ( ( AT91_REG * ) 0xFFFC0120 ) /* (PDC_US0) PDC Transfer Control Register */
+#define AT91C_US0_PTSR             ( ( AT91_REG * ) 0xFFFC0124 ) /* (PDC_US0) PDC Transfer Status Register */
+#define AT91C_US0_TNCR             ( ( AT91_REG * ) 0xFFFC011C ) /* (PDC_US0) Transmit Next Counter Register */
+#define AT91C_US0_TPR              ( ( AT91_REG * ) 0xFFFC0108 ) /* (PDC_US0) Transmit Pointer Register */
+#define AT91C_US0_RCR              ( ( AT91_REG * ) 0xFFFC0104 ) /* (PDC_US0) Receive Counter Register */
+#define AT91C_US0_RPR              ( ( AT91_REG * ) 0xFFFC0100 ) /* (PDC_US0) Receive Pointer Register */
+#define AT91C_US0_RNCR             ( ( AT91_REG * ) 0xFFFC0114 ) /* (PDC_US0) Receive Next Counter Register */
+/* ========== Register definition for US0 peripheral ========== */
+#define AT91C_US0_BRGR             ( ( AT91_REG * ) 0xFFFC0020 ) /* (US0) Baud Rate Generator Register */
+#define AT91C_US0_NER              ( ( AT91_REG * ) 0xFFFC0044 ) /* (US0) Nb Errors Register */
+#define AT91C_US0_CR               ( ( AT91_REG * ) 0xFFFC0000 ) /* (US0) Control Register */
+#define AT91C_US0_IMR              ( ( AT91_REG * ) 0xFFFC0010 ) /* (US0) Interrupt Mask Register */
+#define AT91C_US0_FIDI             ( ( AT91_REG * ) 0xFFFC0040 ) /* (US0) FI_DI_Ratio Register */
+#define AT91C_US0_TTGR             ( ( AT91_REG * ) 0xFFFC0028 ) /* (US0) Transmitter Time-guard Register */
+#define AT91C_US0_MR               ( ( AT91_REG * ) 0xFFFC0004 ) /* (US0) Mode Register */
+#define AT91C_US0_RTOR             ( ( AT91_REG * ) 0xFFFC0024 ) /* (US0) Receiver Time-out Register */
+#define AT91C_US0_CSR              ( ( AT91_REG * ) 0xFFFC0014 ) /* (US0) Channel Status Register */
+#define AT91C_US0_RHR              ( ( AT91_REG * ) 0xFFFC0018 ) /* (US0) Receiver Holding Register */
+#define AT91C_US0_IDR              ( ( AT91_REG * ) 0xFFFC000C ) /* (US0) Interrupt Disable Register */
+#define AT91C_US0_THR              ( ( AT91_REG * ) 0xFFFC001C ) /* (US0) Transmitter Holding Register */
+#define AT91C_US0_IF               ( ( AT91_REG * ) 0xFFFC004C ) /* (US0) IRDA_FILTER Register */
+#define AT91C_US0_IER              ( ( AT91_REG * ) 0xFFFC0008 ) /* (US0) Interrupt Enable Register */
+/* ========== Register definition for PDC_SSC peripheral ========== */
+#define AT91C_SSC_TNCR             ( ( AT91_REG * ) 0xFFFD411C ) /* (PDC_SSC) Transmit Next Counter Register */
+#define AT91C_SSC_RPR              ( ( AT91_REG * ) 0xFFFD4100 ) /* (PDC_SSC) Receive Pointer Register */
+#define AT91C_SSC_RNCR             ( ( AT91_REG * ) 0xFFFD4114 ) /* (PDC_SSC) Receive Next Counter Register */
+#define AT91C_SSC_TPR              ( ( AT91_REG * ) 0xFFFD4108 ) /* (PDC_SSC) Transmit Pointer Register */
+#define AT91C_SSC_PTCR             ( ( AT91_REG * ) 0xFFFD4120 ) /* (PDC_SSC) PDC Transfer Control Register */
+#define AT91C_SSC_TCR              ( ( AT91_REG * ) 0xFFFD410C ) /* (PDC_SSC) Transmit Counter Register */
+#define AT91C_SSC_RCR              ( ( AT91_REG * ) 0xFFFD4104 ) /* (PDC_SSC) Receive Counter Register */
+#define AT91C_SSC_RNPR             ( ( AT91_REG * ) 0xFFFD4110 ) /* (PDC_SSC) Receive Next Pointer Register */
+#define AT91C_SSC_TNPR             ( ( AT91_REG * ) 0xFFFD4118 ) /* (PDC_SSC) Transmit Next Pointer Register */
+#define AT91C_SSC_PTSR             ( ( AT91_REG * ) 0xFFFD4124 ) /* (PDC_SSC) PDC Transfer Status Register */
+/* ========== Register definition for SSC peripheral ========== */
+#define AT91C_SSC_RHR              ( ( AT91_REG * ) 0xFFFD4020 ) /* (SSC) Receive Holding Register */
+#define AT91C_SSC_RSHR             ( ( AT91_REG * ) 0xFFFD4030 ) /* (SSC) Receive Sync Holding Register */
+#define AT91C_SSC_TFMR             ( ( AT91_REG * ) 0xFFFD401C ) /* (SSC) Transmit Frame Mode Register */
+#define AT91C_SSC_IDR              ( ( AT91_REG * ) 0xFFFD4048 ) /* (SSC) Interrupt Disable Register */
+#define AT91C_SSC_THR              ( ( AT91_REG * ) 0xFFFD4024 ) /* (SSC) Transmit Holding Register */
+#define AT91C_SSC_RCMR             ( ( AT91_REG * ) 0xFFFD4010 ) /* (SSC) Receive Clock ModeRegister */
+#define AT91C_SSC_IER              ( ( AT91_REG * ) 0xFFFD4044 ) /* (SSC) Interrupt Enable Register */
+#define AT91C_SSC_TSHR             ( ( AT91_REG * ) 0xFFFD4034 ) /* (SSC) Transmit Sync Holding Register */
+#define AT91C_SSC_SR               ( ( AT91_REG * ) 0xFFFD4040 ) /* (SSC) Status Register */
+#define AT91C_SSC_CMR              ( ( AT91_REG * ) 0xFFFD4004 ) /* (SSC) Clock Mode Register */
+#define AT91C_SSC_TCMR             ( ( AT91_REG * ) 0xFFFD4018 ) /* (SSC) Transmit Clock Mode Register */
+#define AT91C_SSC_CR               ( ( AT91_REG * ) 0xFFFD4000 ) /* (SSC) Control Register */
+#define AT91C_SSC_IMR              ( ( AT91_REG * ) 0xFFFD404C ) /* (SSC) Interrupt Mask Register */
+#define AT91C_SSC_RFMR             ( ( AT91_REG * ) 0xFFFD4014 ) /* (SSC) Receive Frame Mode Register */
+/* ========== Register definition for TWI peripheral ========== */
+#define AT91C_TWI_IER              ( ( AT91_REG * ) 0xFFFB8024 ) /* (TWI) Interrupt Enable Register */
+#define AT91C_TWI_CR               ( ( AT91_REG * ) 0xFFFB8000 ) /* (TWI) Control Register */
+#define AT91C_TWI_SR               ( ( AT91_REG * ) 0xFFFB8020 ) /* (TWI) Status Register */
+#define AT91C_TWI_IMR              ( ( AT91_REG * ) 0xFFFB802C ) /* (TWI) Interrupt Mask Register */
+#define AT91C_TWI_THR              ( ( AT91_REG * ) 0xFFFB8034 ) /* (TWI) Transmit Holding Register */
+#define AT91C_TWI_IDR              ( ( AT91_REG * ) 0xFFFB8028 ) /* (TWI) Interrupt Disable Register */
+#define AT91C_TWI_IADR             ( ( AT91_REG * ) 0xFFFB800C ) /* (TWI) Internal Address Register */
+#define AT91C_TWI_MMR              ( ( AT91_REG * ) 0xFFFB8004 ) /* (TWI) Master Mode Register */
+#define AT91C_TWI_CWGR             ( ( AT91_REG * ) 0xFFFB8010 ) /* (TWI) Clock Waveform Generator Register */
+#define AT91C_TWI_RHR              ( ( AT91_REG * ) 0xFFFB8030 ) /* (TWI) Receive Holding Register */
+/* ========== Register definition for PWMC_CH3 peripheral ========== */
+#define AT91C_PWMC_CH3_CUPDR       ( ( AT91_REG * ) 0xFFFCC270 ) /* (PWMC_CH3) Channel Update Register */
+#define AT91C_PWMC_CH3_Reserved    ( ( AT91_REG * ) 0xFFFCC274 ) /* (PWMC_CH3) Reserved */
+#define AT91C_PWMC_CH3_CPRDR       ( ( AT91_REG * ) 0xFFFCC268 ) /* (PWMC_CH3) Channel Period Register */
+#define AT91C_PWMC_CH3_CDTYR       ( ( AT91_REG * ) 0xFFFCC264 ) /* (PWMC_CH3) Channel Duty Cycle Register */
+#define AT91C_PWMC_CH3_CCNTR       ( ( AT91_REG * ) 0xFFFCC26C ) /* (PWMC_CH3) Channel Counter Register */
+#define AT91C_PWMC_CH3_CMR         ( ( AT91_REG * ) 0xFFFCC260 ) /* (PWMC_CH3) Channel Mode Register */
+/* ========== Register definition for PWMC_CH2 peripheral ========== */
+#define AT91C_PWMC_CH2_Reserved    ( ( AT91_REG * ) 0xFFFCC254 ) /* (PWMC_CH2) Reserved */
+#define AT91C_PWMC_CH2_CMR         ( ( AT91_REG * ) 0xFFFCC240 ) /* (PWMC_CH2) Channel Mode Register */
+#define AT91C_PWMC_CH2_CCNTR       ( ( AT91_REG * ) 0xFFFCC24C ) /* (PWMC_CH2) Channel Counter Register */
+#define AT91C_PWMC_CH2_CPRDR       ( ( AT91_REG * ) 0xFFFCC248 ) /* (PWMC_CH2) Channel Period Register */
+#define AT91C_PWMC_CH2_CUPDR       ( ( AT91_REG * ) 0xFFFCC250 ) /* (PWMC_CH2) Channel Update Register */
+#define AT91C_PWMC_CH2_CDTYR       ( ( AT91_REG * ) 0xFFFCC244 ) /* (PWMC_CH2) Channel Duty Cycle Register */
+/* ========== Register definition for PWMC_CH1 peripheral ========== */
+#define AT91C_PWMC_CH1_Reserved    ( ( AT91_REG * ) 0xFFFCC234 ) /* (PWMC_CH1) Reserved */
+#define AT91C_PWMC_CH1_CUPDR       ( ( AT91_REG * ) 0xFFFCC230 ) /* (PWMC_CH1) Channel Update Register */
+#define AT91C_PWMC_CH1_CPRDR       ( ( AT91_REG * ) 0xFFFCC228 ) /* (PWMC_CH1) Channel Period Register */
+#define AT91C_PWMC_CH1_CCNTR       ( ( AT91_REG * ) 0xFFFCC22C ) /* (PWMC_CH1) Channel Counter Register */
+#define AT91C_PWMC_CH1_CDTYR       ( ( AT91_REG * ) 0xFFFCC224 ) /* (PWMC_CH1) Channel Duty Cycle Register */
+#define AT91C_PWMC_CH1_CMR         ( ( AT91_REG * ) 0xFFFCC220 ) /* (PWMC_CH1) Channel Mode Register */
+/* ========== Register definition for PWMC_CH0 peripheral ========== */
+#define AT91C_PWMC_CH0_Reserved    ( ( AT91_REG * ) 0xFFFCC214 ) /* (PWMC_CH0) Reserved */
+#define AT91C_PWMC_CH0_CPRDR       ( ( AT91_REG * ) 0xFFFCC208 ) /* (PWMC_CH0) Channel Period Register */
+#define AT91C_PWMC_CH0_CDTYR       ( ( AT91_REG * ) 0xFFFCC204 ) /* (PWMC_CH0) Channel Duty Cycle Register */
+#define AT91C_PWMC_CH0_CMR         ( ( AT91_REG * ) 0xFFFCC200 ) /* (PWMC_CH0) Channel Mode Register */
+#define AT91C_PWMC_CH0_CUPDR       ( ( AT91_REG * ) 0xFFFCC210 ) /* (PWMC_CH0) Channel Update Register */
+#define AT91C_PWMC_CH0_CCNTR       ( ( AT91_REG * ) 0xFFFCC20C ) /* (PWMC_CH0) Channel Counter Register */
+/* ========== Register definition for PWMC peripheral ========== */
+#define AT91C_PWMC_IDR             ( ( AT91_REG * ) 0xFFFCC014 ) /* (PWMC) PWMC Interrupt Disable Register */
+#define AT91C_PWMC_DIS             ( ( AT91_REG * ) 0xFFFCC008 ) /* (PWMC) PWMC Disable Register */
+#define AT91C_PWMC_IER             ( ( AT91_REG * ) 0xFFFCC010 ) /* (PWMC) PWMC Interrupt Enable Register */
+#define AT91C_PWMC_VR              ( ( AT91_REG * ) 0xFFFCC0FC ) /* (PWMC) PWMC Version Register */
+#define AT91C_PWMC_ISR             ( ( AT91_REG * ) 0xFFFCC01C ) /* (PWMC) PWMC Interrupt Status Register */
+#define AT91C_PWMC_SR              ( ( AT91_REG * ) 0xFFFCC00C ) /* (PWMC) PWMC Status Register */
+#define AT91C_PWMC_IMR             ( ( AT91_REG * ) 0xFFFCC018 ) /* (PWMC) PWMC Interrupt Mask Register */
+#define AT91C_PWMC_MR              ( ( AT91_REG * ) 0xFFFCC000 ) /* (PWMC) PWMC Mode Register */
+#define AT91C_PWMC_ENA             ( ( AT91_REG * ) 0xFFFCC004 ) /* (PWMC) PWMC Enable Register */
+/* ========== Register definition for UDP peripheral ========== */
+#define AT91C_UDP_IMR              ( ( AT91_REG * ) 0xFFFB0018 ) /* (UDP) Interrupt Mask Register */
+#define AT91C_UDP_FADDR            ( ( AT91_REG * ) 0xFFFB0008 ) /* (UDP) Function Address Register */
+#define AT91C_UDP_NUM              ( ( AT91_REG * ) 0xFFFB0000 ) /* (UDP) Frame Number Register */
+#define AT91C_UDP_FDR              ( ( AT91_REG * ) 0xFFFB0050 ) /* (UDP) Endpoint FIFO Data Register */
+#define AT91C_UDP_ISR              ( ( AT91_REG * ) 0xFFFB001C ) /* (UDP) Interrupt Status Register */
+#define AT91C_UDP_CSR              ( ( AT91_REG * ) 0xFFFB0030 ) /* (UDP) Endpoint Control and Status Register */
+#define AT91C_UDP_IDR              ( ( AT91_REG * ) 0xFFFB0014 ) /* (UDP) Interrupt Disable Register */
+#define AT91C_UDP_ICR              ( ( AT91_REG * ) 0xFFFB0020 ) /* (UDP) Interrupt Clear Register */
+#define AT91C_UDP_RSTEP            ( ( AT91_REG * ) 0xFFFB0028 ) /* (UDP) Reset Endpoint Register */
+#define AT91C_UDP_TXVC             ( ( AT91_REG * ) 0xFFFB0074 ) /* (UDP) Transceiver Control Register */
+#define AT91C_UDP_GLBSTATE         ( ( AT91_REG * ) 0xFFFB0004 ) /* (UDP) Global State Register */
+#define AT91C_UDP_IER              ( ( AT91_REG * ) 0xFFFB0010 ) /* (UDP) Interrupt Enable Register */
+/* ========== Register definition for TC0 peripheral ========== */
+#define AT91C_TC0_SR               ( ( AT91_REG * ) 0xFFFA0020 ) /* (TC0) Status Register */
+#define AT91C_TC0_RC               ( ( AT91_REG * ) 0xFFFA001C ) /* (TC0) Register C */
+#define AT91C_TC0_RB               ( ( AT91_REG * ) 0xFFFA0018 ) /* (TC0) Register B */
+#define AT91C_TC0_CCR              ( ( AT91_REG * ) 0xFFFA0000 ) /* (TC0) Channel Control Register */
+#define AT91C_TC0_CMR              ( ( AT91_REG * ) 0xFFFA0004 ) /* (TC0) Channel Mode Register (Capture Mode / Waveform Mode) */
+#define AT91C_TC0_IER              ( ( AT91_REG * ) 0xFFFA0024 ) /* (TC0) Interrupt Enable Register */
+#define AT91C_TC0_RA               ( ( AT91_REG * ) 0xFFFA0014 ) /* (TC0) Register A */
+#define AT91C_TC0_IDR              ( ( AT91_REG * ) 0xFFFA0028 ) /* (TC0) Interrupt Disable Register */
+#define AT91C_TC0_CV               ( ( AT91_REG * ) 0xFFFA0010 ) /* (TC0) Counter Value */
+#define AT91C_TC0_IMR              ( ( AT91_REG * ) 0xFFFA002C ) /* (TC0) Interrupt Mask Register */
+/* ========== Register definition for TC1 peripheral ========== */
+#define AT91C_TC1_RB               ( ( AT91_REG * ) 0xFFFA0058 ) /* (TC1) Register B */
+#define AT91C_TC1_CCR              ( ( AT91_REG * ) 0xFFFA0040 ) /* (TC1) Channel Control Register */
+#define AT91C_TC1_IER              ( ( AT91_REG * ) 0xFFFA0064 ) /* (TC1) Interrupt Enable Register */
+#define AT91C_TC1_IDR              ( ( AT91_REG * ) 0xFFFA0068 ) /* (TC1) Interrupt Disable Register */
+#define AT91C_TC1_SR               ( ( AT91_REG * ) 0xFFFA0060 ) /* (TC1) Status Register */
+#define AT91C_TC1_CMR              ( ( AT91_REG * ) 0xFFFA0044 ) /* (TC1) Channel Mode Register (Capture Mode / Waveform Mode) */
+#define AT91C_TC1_RA               ( ( AT91_REG * ) 0xFFFA0054 ) /* (TC1) Register A */
+#define AT91C_TC1_RC               ( ( AT91_REG * ) 0xFFFA005C ) /* (TC1) Register C */
+#define AT91C_TC1_IMR              ( ( AT91_REG * ) 0xFFFA006C ) /* (TC1) Interrupt Mask Register */
+#define AT91C_TC1_CV               ( ( AT91_REG * ) 0xFFFA0050 ) /* (TC1) Counter Value */
+/* ========== Register definition for TC2 peripheral ========== */
+#define AT91C_TC2_CMR              ( ( AT91_REG * ) 0xFFFA0084 ) /* (TC2) Channel Mode Register (Capture Mode / Waveform Mode) */
+#define AT91C_TC2_CCR              ( ( AT91_REG * ) 0xFFFA0080 ) /* (TC2) Channel Control Register */
+#define AT91C_TC2_CV               ( ( AT91_REG * ) 0xFFFA0090 ) /* (TC2) Counter Value */
+#define AT91C_TC2_RA               ( ( AT91_REG * ) 0xFFFA0094 ) /* (TC2) Register A */
+#define AT91C_TC2_RB               ( ( AT91_REG * ) 0xFFFA0098 ) /* (TC2) Register B */
+#define AT91C_TC2_IDR              ( ( AT91_REG * ) 0xFFFA00A8 ) /* (TC2) Interrupt Disable Register */
+#define AT91C_TC2_IMR              ( ( AT91_REG * ) 0xFFFA00AC ) /* (TC2) Interrupt Mask Register */
+#define AT91C_TC2_RC               ( ( AT91_REG * ) 0xFFFA009C ) /* (TC2) Register C */
+#define AT91C_TC2_IER              ( ( AT91_REG * ) 0xFFFA00A4 ) /* (TC2) Interrupt Enable Register */
+#define AT91C_TC2_SR               ( ( AT91_REG * ) 0xFFFA00A0 ) /* (TC2) Status Register */
+/* ========== Register definition for TCB peripheral ========== */
+#define AT91C_TCB_BMR              ( ( AT91_REG * ) 0xFFFA00C4 ) /* (TCB) TC Block Mode Register */
+#define AT91C_TCB_BCR              ( ( AT91_REG * ) 0xFFFA00C0 ) /* (TCB) TC Block Control Register */
+/* ========== Register definition for CAN_MB0 peripheral ========== */
+#define AT91C_CAN_MB0_MDL          ( ( AT91_REG * ) 0xFFFD0214 ) /* (CAN_MB0) MailBox Data Low Register */
+#define AT91C_CAN_MB0_MAM          ( ( AT91_REG * ) 0xFFFD0204 ) /* (CAN_MB0) MailBox Acceptance Mask Register */
+#define AT91C_CAN_MB0_MCR          ( ( AT91_REG * ) 0xFFFD021C ) /* (CAN_MB0) MailBox Control Register */
+#define AT91C_CAN_MB0_MID          ( ( AT91_REG * ) 0xFFFD0208 ) /* (CAN_MB0) MailBox ID Register */
+#define AT91C_CAN_MB0_MSR          ( ( AT91_REG * ) 0xFFFD0210 ) /* (CAN_MB0) MailBox Status Register */
+#define AT91C_CAN_MB0_MFID         ( ( AT91_REG * ) 0xFFFD020C ) /* (CAN_MB0) MailBox Family ID Register */
+#define AT91C_CAN_MB0_MDH          ( ( AT91_REG * ) 0xFFFD0218 ) /* (CAN_MB0) MailBox Data High Register */
+#define AT91C_CAN_MB0_MMR          ( ( AT91_REG * ) 0xFFFD0200 ) /* (CAN_MB0) MailBox Mode Register */
+/* ========== Register definition for CAN_MB1 peripheral ========== */
+#define AT91C_CAN_MB1_MDL          ( ( AT91_REG * ) 0xFFFD0234 ) /* (CAN_MB1) MailBox Data Low Register */
+#define AT91C_CAN_MB1_MID          ( ( AT91_REG * ) 0xFFFD0228 ) /* (CAN_MB1) MailBox ID Register */
+#define AT91C_CAN_MB1_MMR          ( ( AT91_REG * ) 0xFFFD0220 ) /* (CAN_MB1) MailBox Mode Register */
+#define AT91C_CAN_MB1_MSR          ( ( AT91_REG * ) 0xFFFD0230 ) /* (CAN_MB1) MailBox Status Register */
+#define AT91C_CAN_MB1_MAM          ( ( AT91_REG * ) 0xFFFD0224 ) /* (CAN_MB1) MailBox Acceptance Mask Register */
+#define AT91C_CAN_MB1_MDH          ( ( AT91_REG * ) 0xFFFD0238 ) /* (CAN_MB1) MailBox Data High Register */
+#define AT91C_CAN_MB1_MCR          ( ( AT91_REG * ) 0xFFFD023C ) /* (CAN_MB1) MailBox Control Register */
+#define AT91C_CAN_MB1_MFID         ( ( AT91_REG * ) 0xFFFD022C ) /* (CAN_MB1) MailBox Family ID Register */
+/* ========== Register definition for CAN_MB2 peripheral ========== */
+#define AT91C_CAN_MB2_MCR          ( ( AT91_REG * ) 0xFFFD025C ) /* (CAN_MB2) MailBox Control Register */
+#define AT91C_CAN_MB2_MDH          ( ( AT91_REG * ) 0xFFFD0258 ) /* (CAN_MB2) MailBox Data High Register */
+#define AT91C_CAN_MB2_MID          ( ( AT91_REG * ) 0xFFFD0248 ) /* (CAN_MB2) MailBox ID Register */
+#define AT91C_CAN_MB2_MDL          ( ( AT91_REG * ) 0xFFFD0254 ) /* (CAN_MB2) MailBox Data Low Register */
+#define AT91C_CAN_MB2_MMR          ( ( AT91_REG * ) 0xFFFD0240 ) /* (CAN_MB2) MailBox Mode Register */
+#define AT91C_CAN_MB2_MAM          ( ( AT91_REG * ) 0xFFFD0244 ) /* (CAN_MB2) MailBox Acceptance Mask Register */
+#define AT91C_CAN_MB2_MFID         ( ( AT91_REG * ) 0xFFFD024C ) /* (CAN_MB2) MailBox Family ID Register */
+#define AT91C_CAN_MB2_MSR          ( ( AT91_REG * ) 0xFFFD0250 ) /* (CAN_MB2) MailBox Status Register */
+/* ========== Register definition for CAN_MB3 peripheral ========== */
+#define AT91C_CAN_MB3_MFID         ( ( AT91_REG * ) 0xFFFD026C ) /* (CAN_MB3) MailBox Family ID Register */
+#define AT91C_CAN_MB3_MAM          ( ( AT91_REG * ) 0xFFFD0264 ) /* (CAN_MB3) MailBox Acceptance Mask Register */
+#define AT91C_CAN_MB3_MID          ( ( AT91_REG * ) 0xFFFD0268 ) /* (CAN_MB3) MailBox ID Register */
+#define AT91C_CAN_MB3_MCR          ( ( AT91_REG * ) 0xFFFD027C ) /* (CAN_MB3) MailBox Control Register */
+#define AT91C_CAN_MB3_MMR          ( ( AT91_REG * ) 0xFFFD0260 ) /* (CAN_MB3) MailBox Mode Register */
+#define AT91C_CAN_MB3_MSR          ( ( AT91_REG * ) 0xFFFD0270 ) /* (CAN_MB3) MailBox Status Register */
+#define AT91C_CAN_MB3_MDL          ( ( AT91_REG * ) 0xFFFD0274 ) /* (CAN_MB3) MailBox Data Low Register */
+#define AT91C_CAN_MB3_MDH          ( ( AT91_REG * ) 0xFFFD0278 ) /* (CAN_MB3) MailBox Data High Register */
+/* ========== Register definition for CAN_MB4 peripheral ========== */
+#define AT91C_CAN_MB4_MID          ( ( AT91_REG * ) 0xFFFD0288 ) /* (CAN_MB4) MailBox ID Register */
+#define AT91C_CAN_MB4_MMR          ( ( AT91_REG * ) 0xFFFD0280 ) /* (CAN_MB4) MailBox Mode Register */
+#define AT91C_CAN_MB4_MDH          ( ( AT91_REG * ) 0xFFFD0298 ) /* (CAN_MB4) MailBox Data High Register */
+#define AT91C_CAN_MB4_MFID         ( ( AT91_REG * ) 0xFFFD028C ) /* (CAN_MB4) MailBox Family ID Register */
+#define AT91C_CAN_MB4_MSR          ( ( AT91_REG * ) 0xFFFD0290 ) /* (CAN_MB4) MailBox Status Register */
+#define AT91C_CAN_MB4_MCR          ( ( AT91_REG * ) 0xFFFD029C ) /* (CAN_MB4) MailBox Control Register */
+#define AT91C_CAN_MB4_MDL          ( ( AT91_REG * ) 0xFFFD0294 ) /* (CAN_MB4) MailBox Data Low Register */
+#define AT91C_CAN_MB4_MAM          ( ( AT91_REG * ) 0xFFFD0284 ) /* (CAN_MB4) MailBox Acceptance Mask Register */
+/* ========== Register definition for CAN_MB5 peripheral ========== */
+#define AT91C_CAN_MB5_MSR          ( ( AT91_REG * ) 0xFFFD02B0 ) /* (CAN_MB5) MailBox Status Register */
+#define AT91C_CAN_MB5_MCR          ( ( AT91_REG * ) 0xFFFD02BC ) /* (CAN_MB5) MailBox Control Register */
+#define AT91C_CAN_MB5_MFID         ( ( AT91_REG * ) 0xFFFD02AC ) /* (CAN_MB5) MailBox Family ID Register */
+#define AT91C_CAN_MB5_MDH          ( ( AT91_REG * ) 0xFFFD02B8 ) /* (CAN_MB5) MailBox Data High Register */
+#define AT91C_CAN_MB5_MID          ( ( AT91_REG * ) 0xFFFD02A8 ) /* (CAN_MB5) MailBox ID Register */
+#define AT91C_CAN_MB5_MMR          ( ( AT91_REG * ) 0xFFFD02A0 ) /* (CAN_MB5) MailBox Mode Register */
+#define AT91C_CAN_MB5_MDL          ( ( AT91_REG * ) 0xFFFD02B4 ) /* (CAN_MB5) MailBox Data Low Register */
+#define AT91C_CAN_MB5_MAM          ( ( AT91_REG * ) 0xFFFD02A4 ) /* (CAN_MB5) MailBox Acceptance Mask Register */
+/* ========== Register definition for CAN_MB6 peripheral ========== */
+#define AT91C_CAN_MB6_MFID         ( ( AT91_REG * ) 0xFFFD02CC ) /* (CAN_MB6) MailBox Family ID Register */
+#define AT91C_CAN_MB6_MID          ( ( AT91_REG * ) 0xFFFD02C8 ) /* (CAN_MB6) MailBox ID Register */
+#define AT91C_CAN_MB6_MAM          ( ( AT91_REG * ) 0xFFFD02C4 ) /* (CAN_MB6) MailBox Acceptance Mask Register */
+#define AT91C_CAN_MB6_MSR          ( ( AT91_REG * ) 0xFFFD02D0 ) /* (CAN_MB6) MailBox Status Register */
+#define AT91C_CAN_MB6_MDL          ( ( AT91_REG * ) 0xFFFD02D4 ) /* (CAN_MB6) MailBox Data Low Register */
+#define AT91C_CAN_MB6_MCR          ( ( AT91_REG * ) 0xFFFD02DC ) /* (CAN_MB6) MailBox Control Register */
+#define AT91C_CAN_MB6_MDH          ( ( AT91_REG * ) 0xFFFD02D8 ) /* (CAN_MB6) MailBox Data High Register */
+#define AT91C_CAN_MB6_MMR          ( ( AT91_REG * ) 0xFFFD02C0 ) /* (CAN_MB6) MailBox Mode Register */
+/* ========== Register definition for CAN_MB7 peripheral ========== */
+#define AT91C_CAN_MB7_MCR          ( ( AT91_REG * ) 0xFFFD02FC ) /* (CAN_MB7) MailBox Control Register */
+#define AT91C_CAN_MB7_MDH          ( ( AT91_REG * ) 0xFFFD02F8 ) /* (CAN_MB7) MailBox Data High Register */
+#define AT91C_CAN_MB7_MFID         ( ( AT91_REG * ) 0xFFFD02EC ) /* (CAN_MB7) MailBox Family ID Register */
+#define AT91C_CAN_MB7_MDL          ( ( AT91_REG * ) 0xFFFD02F4 ) /* (CAN_MB7) MailBox Data Low Register */
+#define AT91C_CAN_MB7_MID          ( ( AT91_REG * ) 0xFFFD02E8 ) /* (CAN_MB7) MailBox ID Register */
+#define AT91C_CAN_MB7_MMR          ( ( AT91_REG * ) 0xFFFD02E0 ) /* (CAN_MB7) MailBox Mode Register */
+#define AT91C_CAN_MB7_MAM          ( ( AT91_REG * ) 0xFFFD02E4 ) /* (CAN_MB7) MailBox Acceptance Mask Register */
+#define AT91C_CAN_MB7_MSR          ( ( AT91_REG * ) 0xFFFD02F0 ) /* (CAN_MB7) MailBox Status Register */
+/* ========== Register definition for CAN peripheral ========== */
+#define AT91C_CAN_TCR              ( ( AT91_REG * ) 0xFFFD0024 ) /* (CAN) Transfer Command Register */
+#define AT91C_CAN_IMR              ( ( AT91_REG * ) 0xFFFD000C ) /* (CAN) Interrupt Mask Register */
+#define AT91C_CAN_IER              ( ( AT91_REG * ) 0xFFFD0004 ) /* (CAN) Interrupt Enable Register */
+#define AT91C_CAN_ECR              ( ( AT91_REG * ) 0xFFFD0020 ) /* (CAN) Error Counter Register */
+#define AT91C_CAN_TIMESTP          ( ( AT91_REG * ) 0xFFFD001C ) /* (CAN) Time Stamp Register */
+#define AT91C_CAN_MR               ( ( AT91_REG * ) 0xFFFD0000 ) /* (CAN) Mode Register */
+#define AT91C_CAN_IDR              ( ( AT91_REG * ) 0xFFFD0008 ) /* (CAN) Interrupt Disable Register */
+#define AT91C_CAN_ACR              ( ( AT91_REG * ) 0xFFFD0028 ) /* (CAN) Abort Command Register */
+#define AT91C_CAN_TIM              ( ( AT91_REG * ) 0xFFFD0018 ) /* (CAN) Timer Register */
+#define AT91C_CAN_SR               ( ( AT91_REG * ) 0xFFFD0010 ) /* (CAN) Status Register */
+#define AT91C_CAN_BR               ( ( AT91_REG * ) 0xFFFD0014 ) /* (CAN) Baudrate Register */
+#define AT91C_CAN_VR               ( ( AT91_REG * ) 0xFFFD00FC ) /* (CAN) Version Register */
+/* ========== Register definition for EMAC peripheral ========== */
+#define AT91C_EMAC_ISR             ( ( AT91_REG * ) 0xFFFDC024 ) /* (EMAC) Interrupt Status Register */
+#define AT91C_EMAC_SA4H            ( ( AT91_REG * ) 0xFFFDC0B4 ) /* (EMAC) Specific Address 4 Top, Last 2 bytes */
+#define AT91C_EMAC_SA1L            ( ( AT91_REG * ) 0xFFFDC098 ) /* (EMAC) Specific Address 1 Bottom, First 4 bytes */
+#define AT91C_EMAC_ELE             ( ( AT91_REG * ) 0xFFFDC078 ) /* (EMAC) Excessive Length Errors Register */
+#define AT91C_EMAC_LCOL            ( ( AT91_REG * ) 0xFFFDC05C ) /* (EMAC) Late Collision Register */
+#define AT91C_EMAC_RLE             ( ( AT91_REG * ) 0xFFFDC088 ) /* (EMAC) Receive Length Field Mismatch Register */
+#define AT91C_EMAC_WOL             ( ( AT91_REG * ) 0xFFFDC0C4 ) /* (EMAC) Wake On LAN Register */
+#define AT91C_EMAC_DTF             ( ( AT91_REG * ) 0xFFFDC058 ) /* (EMAC) Deferred Transmission Frame Register */
+#define AT91C_EMAC_TUND            ( ( AT91_REG * ) 0xFFFDC064 ) /* (EMAC) Transmit Underrun Error Register */
+#define AT91C_EMAC_NCR             ( ( AT91_REG * ) 0xFFFDC000 ) /* (EMAC) Network Control Register */
+#define AT91C_EMAC_SA4L            ( ( AT91_REG * ) 0xFFFDC0B0 ) /* (EMAC) Specific Address 4 Bottom, First 4 bytes */
+#define AT91C_EMAC_RSR             ( ( AT91_REG * ) 0xFFFDC020 ) /* (EMAC) Receive Status Register */
+#define AT91C_EMAC_SA3L            ( ( AT91_REG * ) 0xFFFDC0A8 ) /* (EMAC) Specific Address 3 Bottom, First 4 bytes */
+#define AT91C_EMAC_TSR             ( ( AT91_REG * ) 0xFFFDC014 ) /* (EMAC) Transmit Status Register */
+#define AT91C_EMAC_IDR             ( ( AT91_REG * ) 0xFFFDC02C ) /* (EMAC) Interrupt Disable Register */
+#define AT91C_EMAC_RSE             ( ( AT91_REG * ) 0xFFFDC074 ) /* (EMAC) Receive Symbol Errors Register */
+#define AT91C_EMAC_ECOL            ( ( AT91_REG * ) 0xFFFDC060 ) /* (EMAC) Excessive Collision Register */
+#define AT91C_EMAC_TID             ( ( AT91_REG * ) 0xFFFDC0B8 ) /* (EMAC) Type ID Checking Register */
+#define AT91C_EMAC_HRB             ( ( AT91_REG * ) 0xFFFDC090 ) /* (EMAC) Hash Address Bottom[31:0] */
+#define AT91C_EMAC_TBQP            ( ( AT91_REG * ) 0xFFFDC01C ) /* (EMAC) Transmit Buffer Queue Pointer */
+#define AT91C_EMAC_USRIO           ( ( AT91_REG * ) 0xFFFDC0C0 ) /* (EMAC) USER Input/Output Register */
+#define AT91C_EMAC_PTR             ( ( AT91_REG * ) 0xFFFDC038 ) /* (EMAC) Pause Time Register */
+#define AT91C_EMAC_SA2H            ( ( AT91_REG * ) 0xFFFDC0A4 ) /* (EMAC) Specific Address 2 Top, Last 2 bytes */
+#define AT91C_EMAC_ROV             ( ( AT91_REG * ) 0xFFFDC070 ) /* (EMAC) Receive Overrun Errors Register */
+#define AT91C_EMAC_ALE             ( ( AT91_REG * ) 0xFFFDC054 ) /* (EMAC) Alignment Error Register */
+#define AT91C_EMAC_RJA             ( ( AT91_REG * ) 0xFFFDC07C ) /* (EMAC) Receive Jabbers Register */
+#define AT91C_EMAC_RBQP            ( ( AT91_REG * ) 0xFFFDC018 ) /* (EMAC) Receive Buffer Queue Pointer */
+#define AT91C_EMAC_TPF             ( ( AT91_REG * ) 0xFFFDC08C ) /* (EMAC) Transmitted Pause Frames Register */
+#define AT91C_EMAC_NCFGR           ( ( AT91_REG * ) 0xFFFDC004 ) /* (EMAC) Network Configuration Register */
+#define AT91C_EMAC_HRT             ( ( AT91_REG * ) 0xFFFDC094 ) /* (EMAC) Hash Address Top[63:32] */
+#define AT91C_EMAC_USF             ( ( AT91_REG * ) 0xFFFDC080 ) /* (EMAC) Undersize Frames Register */
+#define AT91C_EMAC_FCSE            ( ( AT91_REG * ) 0xFFFDC050 ) /* (EMAC) Frame Check Sequence Error Register */
+#define AT91C_EMAC_TPQ             ( ( AT91_REG * ) 0xFFFDC0BC ) /* (EMAC) Transmit Pause Quantum Register */
+#define AT91C_EMAC_MAN             ( ( AT91_REG * ) 0xFFFDC034 ) /* (EMAC) PHY Maintenance Register */
+#define AT91C_EMAC_FTO             ( ( AT91_REG * ) 0xFFFDC040 ) /* (EMAC) Frames Transmitted OK Register */
+#define AT91C_EMAC_REV             ( ( AT91_REG * ) 0xFFFDC0FC ) /* (EMAC) Revision Register */
+#define AT91C_EMAC_IMR             ( ( AT91_REG * ) 0xFFFDC030 ) /* (EMAC) Interrupt Mask Register */
+#define AT91C_EMAC_SCF             ( ( AT91_REG * ) 0xFFFDC044 ) /* (EMAC) Single Collision Frame Register */
+#define AT91C_EMAC_PFR             ( ( AT91_REG * ) 0xFFFDC03C ) /* (EMAC) Pause Frames received Register */
+#define AT91C_EMAC_MCF             ( ( AT91_REG * ) 0xFFFDC048 ) /* (EMAC) Multiple Collision Frame Register */
+#define AT91C_EMAC_NSR             ( ( AT91_REG * ) 0xFFFDC008 ) /* (EMAC) Network Status Register */
+#define AT91C_EMAC_SA2L            ( ( AT91_REG * ) 0xFFFDC0A0 ) /* (EMAC) Specific Address 2 Bottom, First 4 bytes */
+#define AT91C_EMAC_FRO             ( ( AT91_REG * ) 0xFFFDC04C ) /* (EMAC) Frames Received OK Register */
+#define AT91C_EMAC_IER             ( ( AT91_REG * ) 0xFFFDC028 ) /* (EMAC) Interrupt Enable Register */
+#define AT91C_EMAC_SA1H            ( ( AT91_REG * ) 0xFFFDC09C ) /* (EMAC) Specific Address 1 Top, Last 2 bytes */
+#define AT91C_EMAC_CSE             ( ( AT91_REG * ) 0xFFFDC068 ) /* (EMAC) Carrier Sense Error Register */
+#define AT91C_EMAC_SA3H            ( ( AT91_REG * ) 0xFFFDC0AC ) /* (EMAC) Specific Address 3 Top, Last 2 bytes */
+#define AT91C_EMAC_RRE             ( ( AT91_REG * ) 0xFFFDC06C ) /* (EMAC) Receive Ressource Error Register */
+#define AT91C_EMAC_STE             ( ( AT91_REG * ) 0xFFFDC084 ) /* (EMAC) SQE Test Error Register */
+/* ========== Register definition for PDC_ADC peripheral ========== */
+#define AT91C_ADC_PTSR             ( ( AT91_REG * ) 0xFFFD8124 ) /* (PDC_ADC) PDC Transfer Status Register */
+#define AT91C_ADC_PTCR             ( ( AT91_REG * ) 0xFFFD8120 ) /* (PDC_ADC) PDC Transfer Control Register */
+#define AT91C_ADC_TNPR             ( ( AT91_REG * ) 0xFFFD8118 ) /* (PDC_ADC) Transmit Next Pointer Register */
+#define AT91C_ADC_TNCR             ( ( AT91_REG * ) 0xFFFD811C ) /* (PDC_ADC) Transmit Next Counter Register */
+#define AT91C_ADC_RNPR             ( ( AT91_REG * ) 0xFFFD8110 ) /* (PDC_ADC) Receive Next Pointer Register */
+#define AT91C_ADC_RNCR             ( ( AT91_REG * ) 0xFFFD8114 ) /* (PDC_ADC) Receive Next Counter Register */
+#define AT91C_ADC_RPR              ( ( AT91_REG * ) 0xFFFD8100 ) /* (PDC_ADC) Receive Pointer Register */
+#define AT91C_ADC_TCR              ( ( AT91_REG * ) 0xFFFD810C ) /* (PDC_ADC) Transmit Counter Register */
+#define AT91C_ADC_TPR              ( ( AT91_REG * ) 0xFFFD8108 ) /* (PDC_ADC) Transmit Pointer Register */
+#define AT91C_ADC_RCR              ( ( AT91_REG * ) 0xFFFD8104 ) /* (PDC_ADC) Receive Counter Register */
+/* ========== Register definition for ADC peripheral ========== */
+#define AT91C_ADC_CDR2             ( ( AT91_REG * ) 0xFFFD8038 ) /* (ADC) ADC Channel Data Register 2 */
+#define AT91C_ADC_CDR3             ( ( AT91_REG * ) 0xFFFD803C ) /* (ADC) ADC Channel Data Register 3 */
+#define AT91C_ADC_CDR0             ( ( AT91_REG * ) 0xFFFD8030 ) /* (ADC) ADC Channel Data Register 0 */
+#define AT91C_ADC_CDR5             ( ( AT91_REG * ) 0xFFFD8044 ) /* (ADC) ADC Channel Data Register 5 */
+#define AT91C_ADC_CHDR             ( ( AT91_REG * ) 0xFFFD8014 ) /* (ADC) ADC Channel Disable Register */
+#define AT91C_ADC_SR               ( ( AT91_REG * ) 0xFFFD801C ) /* (ADC) ADC Status Register */
+#define AT91C_ADC_CDR4             ( ( AT91_REG * ) 0xFFFD8040 ) /* (ADC) ADC Channel Data Register 4 */
+#define AT91C_ADC_CDR1             ( ( AT91_REG * ) 0xFFFD8034 ) /* (ADC) ADC Channel Data Register 1 */
+#define AT91C_ADC_LCDR             ( ( AT91_REG * ) 0xFFFD8020 ) /* (ADC) ADC Last Converted Data Register */
+#define AT91C_ADC_IDR              ( ( AT91_REG * ) 0xFFFD8028 ) /* (ADC) ADC Interrupt Disable Register */
+#define AT91C_ADC_CR               ( ( AT91_REG * ) 0xFFFD8000 ) /* (ADC) ADC Control Register */
+#define AT91C_ADC_CDR7             ( ( AT91_REG * ) 0xFFFD804C ) /* (ADC) ADC Channel Data Register 7 */
+#define AT91C_ADC_CDR6             ( ( AT91_REG * ) 0xFFFD8048 ) /* (ADC) ADC Channel Data Register 6 */
+#define AT91C_ADC_IER              ( ( AT91_REG * ) 0xFFFD8024 ) /* (ADC) ADC Interrupt Enable Register */
+#define AT91C_ADC_CHER             ( ( AT91_REG * ) 0xFFFD8010 ) /* (ADC) ADC Channel Enable Register */
+#define AT91C_ADC_CHSR             ( ( AT91_REG * ) 0xFFFD8018 ) /* (ADC) ADC Channel Status Register */
+#define AT91C_ADC_MR               ( ( AT91_REG * ) 0xFFFD8004 ) /* (ADC) ADC Mode Register */
+#define AT91C_ADC_IMR              ( ( AT91_REG * ) 0xFFFD802C ) /* (ADC) ADC Interrupt Mask Register */
+/* ========== Register definition for PDC_AES peripheral ========== */
+#define AT91C_AES_TPR              ( ( AT91_REG * ) 0xFFFA4108 ) /* (PDC_AES) Transmit Pointer Register */
+#define AT91C_AES_PTCR             ( ( AT91_REG * ) 0xFFFA4120 ) /* (PDC_AES) PDC Transfer Control Register */
+#define AT91C_AES_RNPR             ( ( AT91_REG * ) 0xFFFA4110 ) /* (PDC_AES) Receive Next Pointer Register */
+#define AT91C_AES_TNCR             ( ( AT91_REG * ) 0xFFFA411C ) /* (PDC_AES) Transmit Next Counter Register */
+#define AT91C_AES_TCR              ( ( AT91_REG * ) 0xFFFA410C ) /* (PDC_AES) Transmit Counter Register */
+#define AT91C_AES_RCR              ( ( AT91_REG * ) 0xFFFA4104 ) /* (PDC_AES) Receive Counter Register */
+#define AT91C_AES_RNCR             ( ( AT91_REG * ) 0xFFFA4114 ) /* (PDC_AES) Receive Next Counter Register */
+#define AT91C_AES_TNPR             ( ( AT91_REG * ) 0xFFFA4118 ) /* (PDC_AES) Transmit Next Pointer Register */
+#define AT91C_AES_RPR              ( ( AT91_REG * ) 0xFFFA4100 ) /* (PDC_AES) Receive Pointer Register */
+#define AT91C_AES_PTSR             ( ( AT91_REG * ) 0xFFFA4124 ) /* (PDC_AES) PDC Transfer Status Register */
+/* ========== Register definition for AES peripheral ========== */
+#define AT91C_AES_IVxR             ( ( AT91_REG * ) 0xFFFA4060 ) /* (AES) Initialization Vector x Register */
+#define AT91C_AES_MR               ( ( AT91_REG * ) 0xFFFA4004 ) /* (AES) Mode Register */
+#define AT91C_AES_VR               ( ( AT91_REG * ) 0xFFFA40FC ) /* (AES) AES Version Register */
+#define AT91C_AES_ODATAxR          ( ( AT91_REG * ) 0xFFFA4050 ) /* (AES) Output Data x Register */
+#define AT91C_AES_IDATAxR          ( ( AT91_REG * ) 0xFFFA4040 ) /* (AES) Input Data x Register */
+#define AT91C_AES_CR               ( ( AT91_REG * ) 0xFFFA4000 ) /* (AES) Control Register */
+#define AT91C_AES_IDR              ( ( AT91_REG * ) 0xFFFA4014 ) /* (AES) Interrupt Disable Register */
+#define AT91C_AES_IMR              ( ( AT91_REG * ) 0xFFFA4018 ) /* (AES) Interrupt Mask Register */
+#define AT91C_AES_IER              ( ( AT91_REG * ) 0xFFFA4010 ) /* (AES) Interrupt Enable Register */
+#define AT91C_AES_KEYWxR           ( ( AT91_REG * ) 0xFFFA4020 ) /* (AES) Key Word x Register */
+#define AT91C_AES_ISR              ( ( AT91_REG * ) 0xFFFA401C ) /* (AES) Interrupt Status Register */
+/* ========== Register definition for PDC_TDES peripheral ========== */
+#define AT91C_TDES_RNCR            ( ( AT91_REG * ) 0xFFFA8114 ) /* (PDC_TDES) Receive Next Counter Register */
+#define AT91C_TDES_TCR             ( ( AT91_REG * ) 0xFFFA810C ) /* (PDC_TDES) Transmit Counter Register */
+#define AT91C_TDES_RCR             ( ( AT91_REG * ) 0xFFFA8104 ) /* (PDC_TDES) Receive Counter Register */
+#define AT91C_TDES_TNPR            ( ( AT91_REG * ) 0xFFFA8118 ) /* (PDC_TDES) Transmit Next Pointer Register */
+#define AT91C_TDES_RNPR            ( ( AT91_REG * ) 0xFFFA8110 ) /* (PDC_TDES) Receive Next Pointer Register */
+#define AT91C_TDES_RPR             ( ( AT91_REG * ) 0xFFFA8100 ) /* (PDC_TDES) Receive Pointer Register */
+#define AT91C_TDES_TNCR            ( ( AT91_REG * ) 0xFFFA811C ) /* (PDC_TDES) Transmit Next Counter Register */
+#define AT91C_TDES_TPR             ( ( AT91_REG * ) 0xFFFA8108 ) /* (PDC_TDES) Transmit Pointer Register */
+#define AT91C_TDES_PTSR            ( ( AT91_REG * ) 0xFFFA8124 ) /* (PDC_TDES) PDC Transfer Status Register */
+#define AT91C_TDES_PTCR            ( ( AT91_REG * ) 0xFFFA8120 ) /* (PDC_TDES) PDC Transfer Control Register */
+/* ========== Register definition for TDES peripheral ========== */
+#define AT91C_TDES_KEY2WxR         ( ( AT91_REG * ) 0xFFFA8028 ) /* (TDES) Key 2 Word x Register */
+#define AT91C_TDES_KEY3WxR         ( ( AT91_REG * ) 0xFFFA8030 ) /* (TDES) Key 3 Word x Register */
+#define AT91C_TDES_IDR             ( ( AT91_REG * ) 0xFFFA8014 ) /* (TDES) Interrupt Disable Register */
+#define AT91C_TDES_VR              ( ( AT91_REG * ) 0xFFFA80FC ) /* (TDES) TDES Version Register */
+#define AT91C_TDES_IVxR            ( ( AT91_REG * ) 0xFFFA8060 ) /* (TDES) Initialization Vector x Register */
+#define AT91C_TDES_ODATAxR         ( ( AT91_REG * ) 0xFFFA8050 ) /* (TDES) Output Data x Register */
+#define AT91C_TDES_IMR             ( ( AT91_REG * ) 0xFFFA8018 ) /* (TDES) Interrupt Mask Register */
+#define AT91C_TDES_MR              ( ( AT91_REG * ) 0xFFFA8004 ) /* (TDES) Mode Register */
+#define AT91C_TDES_CR              ( ( AT91_REG * ) 0xFFFA8000 ) /* (TDES) Control Register */
+#define AT91C_TDES_IER             ( ( AT91_REG * ) 0xFFFA8010 ) /* (TDES) Interrupt Enable Register */
+#define AT91C_TDES_ISR             ( ( AT91_REG * ) 0xFFFA801C ) /* (TDES) Interrupt Status Register */
+#define AT91C_TDES_IDATAxR         ( ( AT91_REG * ) 0xFFFA8040 ) /* (TDES) Input Data x Register */
+#define AT91C_TDES_KEY1WxR         ( ( AT91_REG * ) 0xFFFA8020 ) /* (TDES) Key 1 Word x Register */
 
-// *****************************************************************************
-//               PIO DEFINITIONS FOR AT91SAM7X256
-// *****************************************************************************
-#define AT91C_PIO_PA0        ((unsigned int) 1 <<  0) // Pin Controlled by PA0
-#define AT91C_PA0_RXD0     ((unsigned int) AT91C_PIO_PA0) //  USART 0 Receive Data
-#define AT91C_PIO_PA1        ((unsigned int) 1 <<  1) // Pin Controlled by PA1
-#define AT91C_PA1_TXD0     ((unsigned int) AT91C_PIO_PA1) //  USART 0 Transmit Data
-#define AT91C_PIO_PA10       ((unsigned int) 1 << 10) // Pin Controlled by PA10
-#define AT91C_PA10_TWD      ((unsigned int) AT91C_PIO_PA10) //  TWI Two-wire Serial Data
-#define AT91C_PIO_PA11       ((unsigned int) 1 << 11) // Pin Controlled by PA11
-#define AT91C_PA11_TWCK     ((unsigned int) AT91C_PIO_PA11) //  TWI Two-wire Serial Clock
-#define AT91C_PIO_PA12       ((unsigned int) 1 << 12) // Pin Controlled by PA12
-#define AT91C_PA12_NPCS00   ((unsigned int) AT91C_PIO_PA12) //  SPI 0 Peripheral Chip Select 0
-#define AT91C_PIO_PA13       ((unsigned int) 1 << 13) // Pin Controlled by PA13
-#define AT91C_PA13_NPCS01   ((unsigned int) AT91C_PIO_PA13) //  SPI 0 Peripheral Chip Select 1
-#define AT91C_PA13_PCK1     ((unsigned int) AT91C_PIO_PA13) //  PMC Programmable Clock Output 1
-#define AT91C_PIO_PA14       ((unsigned int) 1 << 14) // Pin Controlled by PA14
-#define AT91C_PA14_NPCS02   ((unsigned int) AT91C_PIO_PA14) //  SPI 0 Peripheral Chip Select 2
-#define AT91C_PA14_IRQ1     ((unsigned int) AT91C_PIO_PA14) //  External Interrupt 1
-#define AT91C_PIO_PA15       ((unsigned int) 1 << 15) // Pin Controlled by PA15
-#define AT91C_PA15_NPCS03   ((unsigned int) AT91C_PIO_PA15) //  SPI 0 Peripheral Chip Select 3
-#define AT91C_PA15_TCLK2    ((unsigned int) AT91C_PIO_PA15) //  Timer Counter 2 external clock input
-#define AT91C_PIO_PA16       ((unsigned int) 1 << 16) // Pin Controlled by PA16
-#define AT91C_PA16_MISO0    ((unsigned int) AT91C_PIO_PA16) //  SPI 0 Master In Slave
-#define AT91C_PIO_PA17       ((unsigned int) 1 << 17) // Pin Controlled by PA17
-#define AT91C_PA17_MOSI0    ((unsigned int) AT91C_PIO_PA17) //  SPI 0 Master Out Slave
-#define AT91C_PIO_PA18       ((unsigned int) 1 << 18) // Pin Controlled by PA18
-#define AT91C_PA18_SPCK0    ((unsigned int) AT91C_PIO_PA18) //  SPI 0 Serial Clock
-#define AT91C_PIO_PA19       ((unsigned int) 1 << 19) // Pin Controlled by PA19
-#define AT91C_PA19_CANRX    ((unsigned int) AT91C_PIO_PA19) //  CAN Receive
-#define AT91C_PIO_PA2        ((unsigned int) 1 <<  2) // Pin Controlled by PA2
-#define AT91C_PA2_SCK0     ((unsigned int) AT91C_PIO_PA2) //  USART 0 Serial Clock
-#define AT91C_PA2_NPCS11   ((unsigned int) AT91C_PIO_PA2) //  SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PA20       ((unsigned int) 1 << 20) // Pin Controlled by PA20
-#define AT91C_PA20_CANTX    ((unsigned int) AT91C_PIO_PA20) //  CAN Transmit
-#define AT91C_PIO_PA21       ((unsigned int) 1 << 21) // Pin Controlled by PA21
-#define AT91C_PA21_TF       ((unsigned int) AT91C_PIO_PA21) //  SSC Transmit Frame Sync
-#define AT91C_PA21_NPCS10   ((unsigned int) AT91C_PIO_PA21) //  SPI 1 Peripheral Chip Select 0
-#define AT91C_PIO_PA22       ((unsigned int) 1 << 22) // Pin Controlled by PA22
-#define AT91C_PA22_TK       ((unsigned int) AT91C_PIO_PA22) //  SSC Transmit Clock
-#define AT91C_PA22_SPCK1    ((unsigned int) AT91C_PIO_PA22) //  SPI 1 Serial Clock
-#define AT91C_PIO_PA23       ((unsigned int) 1 << 23) // Pin Controlled by PA23
-#define AT91C_PA23_TD       ((unsigned int) AT91C_PIO_PA23) //  SSC Transmit data
-#define AT91C_PA23_MOSI1    ((unsigned int) AT91C_PIO_PA23) //  SPI 1 Master Out Slave
-#define AT91C_PIO_PA24       ((unsigned int) 1 << 24) // Pin Controlled by PA24
-#define AT91C_PA24_RD       ((unsigned int) AT91C_PIO_PA24) //  SSC Receive Data
-#define AT91C_PA24_MISO1    ((unsigned int) AT91C_PIO_PA24) //  SPI 1 Master In Slave
-#define AT91C_PIO_PA25       ((unsigned int) 1 << 25) // Pin Controlled by PA25
-#define AT91C_PA25_RK       ((unsigned int) AT91C_PIO_PA25) //  SSC Receive Clock
-#define AT91C_PA25_NPCS11   ((unsigned int) AT91C_PIO_PA25) //  SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PA26       ((unsigned int) 1 << 26) // Pin Controlled by PA26
-#define AT91C_PA26_RF       ((unsigned int) AT91C_PIO_PA26) //  SSC Receive Frame Sync
-#define AT91C_PA26_NPCS12   ((unsigned int) AT91C_PIO_PA26) //  SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PA27       ((unsigned int) 1 << 27) // Pin Controlled by PA27
-#define AT91C_PA27_DRXD     ((unsigned int) AT91C_PIO_PA27) //  DBGU Debug Receive Data
-#define AT91C_PA27_PCK3     ((unsigned int) AT91C_PIO_PA27) //  PMC Programmable Clock Output 3
-#define AT91C_PIO_PA28       ((unsigned int) 1 << 28) // Pin Controlled by PA28
-#define AT91C_PA28_DTXD     ((unsigned int) AT91C_PIO_PA28) //  DBGU Debug Transmit Data
-#define AT91C_PIO_PA29       ((unsigned int) 1 << 29) // Pin Controlled by PA29
-#define AT91C_PA29_FIQ      ((unsigned int) AT91C_PIO_PA29) //  AIC Fast Interrupt Input
-#define AT91C_PA29_NPCS13   ((unsigned int) AT91C_PIO_PA29) //  SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PA3        ((unsigned int) 1 <<  3) // Pin Controlled by PA3
-#define AT91C_PA3_RTS0     ((unsigned int) AT91C_PIO_PA3) //  USART 0 Ready To Send
-#define AT91C_PA3_NPCS12   ((unsigned int) AT91C_PIO_PA3) //  SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PA30       ((unsigned int) 1 << 30) // Pin Controlled by PA30
-#define AT91C_PA30_IRQ0     ((unsigned int) AT91C_PIO_PA30) //  External Interrupt 0
-#define AT91C_PA30_PCK2     ((unsigned int) AT91C_PIO_PA30) //  PMC Programmable Clock Output 2
-#define AT91C_PIO_PA4        ((unsigned int) 1 <<  4) // Pin Controlled by PA4
-#define AT91C_PA4_CTS0     ((unsigned int) AT91C_PIO_PA4) //  USART 0 Clear To Send
-#define AT91C_PA4_NPCS13   ((unsigned int) AT91C_PIO_PA4) //  SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PA5        ((unsigned int) 1 <<  5) // Pin Controlled by PA5
-#define AT91C_PA5_RXD1     ((unsigned int) AT91C_PIO_PA5) //  USART 1 Receive Data
-#define AT91C_PIO_PA6        ((unsigned int) 1 <<  6) // Pin Controlled by PA6
-#define AT91C_PA6_TXD1     ((unsigned int) AT91C_PIO_PA6) //  USART 1 Transmit Data
-#define AT91C_PIO_PA7        ((unsigned int) 1 <<  7) // Pin Controlled by PA7
-#define AT91C_PA7_SCK1     ((unsigned int) AT91C_PIO_PA7) //  USART 1 Serial Clock
-#define AT91C_PA7_NPCS01   ((unsigned int) AT91C_PIO_PA7) //  SPI 0 Peripheral Chip Select 1
-#define AT91C_PIO_PA8        ((unsigned int) 1 <<  8) // Pin Controlled by PA8
-#define AT91C_PA8_RTS1     ((unsigned int) AT91C_PIO_PA8) //  USART 1 Ready To Send
-#define AT91C_PA8_NPCS02   ((unsigned int) AT91C_PIO_PA8) //  SPI 0 Peripheral Chip Select 2
-#define AT91C_PIO_PA9        ((unsigned int) 1 <<  9) // Pin Controlled by PA9
-#define AT91C_PA9_CTS1     ((unsigned int) AT91C_PIO_PA9) //  USART 1 Clear To Send
-#define AT91C_PA9_NPCS03   ((unsigned int) AT91C_PIO_PA9) //  SPI 0 Peripheral Chip Select 3
-#define AT91C_PIO_PB0        ((unsigned int) 1 <<  0) // Pin Controlled by PB0
-#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) //  Ethernet MAC Transmit Clock/Reference Clock
-#define AT91C_PB0_PCK0     ((unsigned int) AT91C_PIO_PB0) //  PMC Programmable Clock Output 0
-#define AT91C_PIO_PB1        ((unsigned int) 1 <<  1) // Pin Controlled by PB1
-#define AT91C_PB1_ETXEN    ((unsigned int) AT91C_PIO_PB1) //  Ethernet MAC Transmit Enable
-#define AT91C_PIO_PB10       ((unsigned int) 1 << 10) // Pin Controlled by PB10
-#define AT91C_PB10_ETX2     ((unsigned int) AT91C_PIO_PB10) //  Ethernet MAC Transmit Data 2
-#define AT91C_PB10_NPCS11   ((unsigned int) AT91C_PIO_PB10) //  SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PB11       ((unsigned int) 1 << 11) // Pin Controlled by PB11
-#define AT91C_PB11_ETX3     ((unsigned int) AT91C_PIO_PB11) //  Ethernet MAC Transmit Data 3
-#define AT91C_PB11_NPCS12   ((unsigned int) AT91C_PIO_PB11) //  SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PB12       ((unsigned int) 1 << 12) // Pin Controlled by PB12
-#define AT91C_PB12_ETXER    ((unsigned int) AT91C_PIO_PB12) //  Ethernet MAC Transmikt Coding Error
-#define AT91C_PB12_TCLK0    ((unsigned int) AT91C_PIO_PB12) //  Timer Counter 0 external clock input
-#define AT91C_PIO_PB13       ((unsigned int) 1 << 13) // Pin Controlled by PB13
-#define AT91C_PB13_ERX2     ((unsigned int) AT91C_PIO_PB13) //  Ethernet MAC Receive Data 2
-#define AT91C_PB13_NPCS01   ((unsigned int) AT91C_PIO_PB13) //  SPI 0 Peripheral Chip Select 1
-#define AT91C_PIO_PB14       ((unsigned int) 1 << 14) // Pin Controlled by PB14
-#define AT91C_PB14_ERX3     ((unsigned int) AT91C_PIO_PB14) //  Ethernet MAC Receive Data 3
-#define AT91C_PB14_NPCS02   ((unsigned int) AT91C_PIO_PB14) //  SPI 0 Peripheral Chip Select 2
-#define AT91C_PIO_PB15       ((unsigned int) 1 << 15) // Pin Controlled by PB15
-#define AT91C_PB15_ERXDV    ((unsigned int) AT91C_PIO_PB15) //  Ethernet MAC Receive Data Valid
-#define AT91C_PIO_PB16       ((unsigned int) 1 << 16) // Pin Controlled by PB16
-#define AT91C_PB16_ECOL     ((unsigned int) AT91C_PIO_PB16) //  Ethernet MAC Collision Detected
-#define AT91C_PB16_NPCS13   ((unsigned int) AT91C_PIO_PB16) //  SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PB17       ((unsigned int) 1 << 17) // Pin Controlled by PB17
-#define AT91C_PB17_ERXCK    ((unsigned int) AT91C_PIO_PB17) //  Ethernet MAC Receive Clock
-#define AT91C_PB17_NPCS03   ((unsigned int) AT91C_PIO_PB17) //  SPI 0 Peripheral Chip Select 3
-#define AT91C_PIO_PB18       ((unsigned int) 1 << 18) // Pin Controlled by PB18
-#define AT91C_PB18_EF100    ((unsigned int) AT91C_PIO_PB18) //  Ethernet MAC Force 100 Mbits/sec
-#define AT91C_PB18_ADTRG    ((unsigned int) AT91C_PIO_PB18) //  ADC External Trigger
-#define AT91C_PIO_PB19       ((unsigned int) 1 << 19) // Pin Controlled by PB19
-#define AT91C_PB19_PWM0     ((unsigned int) AT91C_PIO_PB19) //  PWM Channel 0
-#define AT91C_PB19_TCLK1    ((unsigned int) AT91C_PIO_PB19) //  Timer Counter 1 external clock input
-#define AT91C_PIO_PB2        ((unsigned int) 1 <<  2) // Pin Controlled by PB2
-#define AT91C_PB2_ETX0     ((unsigned int) AT91C_PIO_PB2) //  Ethernet MAC Transmit Data 0
-#define AT91C_PIO_PB20       ((unsigned int) 1 << 20) // Pin Controlled by PB20
-#define AT91C_PB20_PWM1     ((unsigned int) AT91C_PIO_PB20) //  PWM Channel 1
-#define AT91C_PB20_PCK0     ((unsigned int) AT91C_PIO_PB20) //  PMC Programmable Clock Output 0
-#define AT91C_PIO_PB21       ((unsigned int) 1 << 21) // Pin Controlled by PB21
-#define AT91C_PB21_PWM2     ((unsigned int) AT91C_PIO_PB21) //  PWM Channel 2
-#define AT91C_PB21_PCK1     ((unsigned int) AT91C_PIO_PB21) //  PMC Programmable Clock Output 1
-#define AT91C_PIO_PB22       ((unsigned int) 1 << 22) // Pin Controlled by PB22
-#define AT91C_PB22_PWM3     ((unsigned int) AT91C_PIO_PB22) //  PWM Channel 3
-#define AT91C_PB22_PCK2     ((unsigned int) AT91C_PIO_PB22) //  PMC Programmable Clock Output 2
-#define AT91C_PIO_PB23       ((unsigned int) 1 << 23) // Pin Controlled by PB23
-#define AT91C_PB23_TIOA0    ((unsigned int) AT91C_PIO_PB23) //  Timer Counter 0 Multipurpose Timer I/O Pin A
-#define AT91C_PB23_DCD1     ((unsigned int) AT91C_PIO_PB23) //  USART 1 Data Carrier Detect
-#define AT91C_PIO_PB24       ((unsigned int) 1 << 24) // Pin Controlled by PB24
-#define AT91C_PB24_TIOB0    ((unsigned int) AT91C_PIO_PB24) //  Timer Counter 0 Multipurpose Timer I/O Pin B
-#define AT91C_PB24_DSR1     ((unsigned int) AT91C_PIO_PB24) //  USART 1 Data Set ready
-#define AT91C_PIO_PB25       ((unsigned int) 1 << 25) // Pin Controlled by PB25
-#define AT91C_PB25_TIOA1    ((unsigned int) AT91C_PIO_PB25) //  Timer Counter 1 Multipurpose Timer I/O Pin A
-#define AT91C_PB25_DTR1     ((unsigned int) AT91C_PIO_PB25) //  USART 1 Data Terminal ready
-#define AT91C_PIO_PB26       ((unsigned int) 1 << 26) // Pin Controlled by PB26
-#define AT91C_PB26_TIOB1    ((unsigned int) AT91C_PIO_PB26) //  Timer Counter 1 Multipurpose Timer I/O Pin B
-#define AT91C_PB26_RI1      ((unsigned int) AT91C_PIO_PB26) //  USART 1 Ring Indicator
-#define AT91C_PIO_PB27       ((unsigned int) 1 << 27) // Pin Controlled by PB27
-#define AT91C_PB27_TIOA2    ((unsigned int) AT91C_PIO_PB27) //  Timer Counter 2 Multipurpose Timer I/O Pin A
-#define AT91C_PB27_PWM0     ((unsigned int) AT91C_PIO_PB27) //  PWM Channel 0
-#define AT91C_PIO_PB28       ((unsigned int) 1 << 28) // Pin Controlled by PB28
-#define AT91C_PB28_TIOB2    ((unsigned int) AT91C_PIO_PB28) //  Timer Counter 2 Multipurpose Timer I/O Pin B
-#define AT91C_PB28_PWM1     ((unsigned int) AT91C_PIO_PB28) //  PWM Channel 1
-#define AT91C_PIO_PB29       ((unsigned int) 1 << 29) // Pin Controlled by PB29
-#define AT91C_PB29_PCK1     ((unsigned int) AT91C_PIO_PB29) //  PMC Programmable Clock Output 1
-#define AT91C_PB29_PWM2     ((unsigned int) AT91C_PIO_PB29) //  PWM Channel 2
-#define AT91C_PIO_PB3        ((unsigned int) 1 <<  3) // Pin Controlled by PB3
-#define AT91C_PB3_ETX1     ((unsigned int) AT91C_PIO_PB3) //  Ethernet MAC Transmit Data 1
-#define AT91C_PIO_PB30       ((unsigned int) 1 << 30) // Pin Controlled by PB30
-#define AT91C_PB30_PCK2     ((unsigned int) AT91C_PIO_PB30) //  PMC Programmable Clock Output 2
-#define AT91C_PB30_PWM3     ((unsigned int) AT91C_PIO_PB30) //  PWM Channel 3
-#define AT91C_PIO_PB4        ((unsigned int) 1 <<  4) // Pin Controlled by PB4
-#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) //  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
-#define AT91C_PIO_PB5        ((unsigned int) 1 <<  5) // Pin Controlled by PB5
-#define AT91C_PB5_ERX0     ((unsigned int) AT91C_PIO_PB5) //  Ethernet MAC Receive Data 0
-#define AT91C_PIO_PB6        ((unsigned int) 1 <<  6) // Pin Controlled by PB6
-#define AT91C_PB6_ERX1     ((unsigned int) AT91C_PIO_PB6) //  Ethernet MAC Receive Data 1
-#define AT91C_PIO_PB7        ((unsigned int) 1 <<  7) // Pin Controlled by PB7
-#define AT91C_PB7_ERXER    ((unsigned int) AT91C_PIO_PB7) //  Ethernet MAC Receive Error
-#define AT91C_PIO_PB8        ((unsigned int) 1 <<  8) // Pin Controlled by PB8
-#define AT91C_PB8_EMDC     ((unsigned int) AT91C_PIO_PB8) //  Ethernet MAC Management Data Clock
-#define AT91C_PIO_PB9        ((unsigned int) 1 <<  9) // Pin Controlled by PB9
-#define AT91C_PB9_EMDIO    ((unsigned int) AT91C_PIO_PB9) //  Ethernet MAC Management Data Input/Output
+/* ***************************************************************************** */
+/*               PIO DEFINITIONS FOR AT91SAM7X256 */
+/* ***************************************************************************** */
+#define AT91C_PIO_PA0             ( ( unsigned int ) 1 << 0 )         /* Pin Controlled by PA0 */
+#define AT91C_PA0_RXD0            ( ( unsigned int ) AT91C_PIO_PA0 )  /*  USART 0 Receive Data */
+#define AT91C_PIO_PA1             ( ( unsigned int ) 1 << 1 )         /* Pin Controlled by PA1 */
+#define AT91C_PA1_TXD0            ( ( unsigned int ) AT91C_PIO_PA1 )  /*  USART 0 Transmit Data */
+#define AT91C_PIO_PA10            ( ( unsigned int ) 1 << 10 )        /* Pin Controlled by PA10 */
+#define AT91C_PA10_TWD            ( ( unsigned int ) AT91C_PIO_PA10 ) /*  TWI Two-wire Serial Data */
+#define AT91C_PIO_PA11            ( ( unsigned int ) 1 << 11 )        /* Pin Controlled by PA11 */
+#define AT91C_PA11_TWCK           ( ( unsigned int ) AT91C_PIO_PA11 ) /*  TWI Two-wire Serial Clock */
+#define AT91C_PIO_PA12            ( ( unsigned int ) 1 << 12 )        /* Pin Controlled by PA12 */
+#define AT91C_PA12_NPCS00         ( ( unsigned int ) AT91C_PIO_PA12 ) /*  SPI 0 Peripheral Chip Select 0 */
+#define AT91C_PIO_PA13            ( ( unsigned int ) 1 << 13 )        /* Pin Controlled by PA13 */
+#define AT91C_PA13_NPCS01         ( ( unsigned int ) AT91C_PIO_PA13 ) /*  SPI 0 Peripheral Chip Select 1 */
+#define AT91C_PA13_PCK1           ( ( unsigned int ) AT91C_PIO_PA13 ) /*  PMC Programmable Clock Output 1 */
+#define AT91C_PIO_PA14            ( ( unsigned int ) 1 << 14 )        /* Pin Controlled by PA14 */
+#define AT91C_PA14_NPCS02         ( ( unsigned int ) AT91C_PIO_PA14 ) /*  SPI 0 Peripheral Chip Select 2 */
+#define AT91C_PA14_IRQ1           ( ( unsigned int ) AT91C_PIO_PA14 ) /*  External Interrupt 1 */
+#define AT91C_PIO_PA15            ( ( unsigned int ) 1 << 15 )        /* Pin Controlled by PA15 */
+#define AT91C_PA15_NPCS03         ( ( unsigned int ) AT91C_PIO_PA15 ) /*  SPI 0 Peripheral Chip Select 3 */
+#define AT91C_PA15_TCLK2          ( ( unsigned int ) AT91C_PIO_PA15 ) /*  Timer Counter 2 external clock input */
+#define AT91C_PIO_PA16            ( ( unsigned int ) 1 << 16 )        /* Pin Controlled by PA16 */
+#define AT91C_PA16_MISO0          ( ( unsigned int ) AT91C_PIO_PA16 ) /*  SPI 0 Master In Slave */
+#define AT91C_PIO_PA17            ( ( unsigned int ) 1 << 17 )        /* Pin Controlled by PA17 */
+#define AT91C_PA17_MOSI0          ( ( unsigned int ) AT91C_PIO_PA17 ) /*  SPI 0 Master Out Slave */
+#define AT91C_PIO_PA18            ( ( unsigned int ) 1 << 18 )        /* Pin Controlled by PA18 */
+#define AT91C_PA18_SPCK0          ( ( unsigned int ) AT91C_PIO_PA18 ) /*  SPI 0 Serial Clock */
+#define AT91C_PIO_PA19            ( ( unsigned int ) 1 << 19 )        /* Pin Controlled by PA19 */
+#define AT91C_PA19_CANRX          ( ( unsigned int ) AT91C_PIO_PA19 ) /*  CAN Receive */
+#define AT91C_PIO_PA2             ( ( unsigned int ) 1 << 2 )         /* Pin Controlled by PA2 */
+#define AT91C_PA2_SCK0            ( ( unsigned int ) AT91C_PIO_PA2 )  /*  USART 0 Serial Clock */
+#define AT91C_PA2_NPCS11          ( ( unsigned int ) AT91C_PIO_PA2 )  /*  SPI 1 Peripheral Chip Select 1 */
+#define AT91C_PIO_PA20            ( ( unsigned int ) 1 << 20 )        /* Pin Controlled by PA20 */
+#define AT91C_PA20_CANTX          ( ( unsigned int ) AT91C_PIO_PA20 ) /*  CAN Transmit */
+#define AT91C_PIO_PA21            ( ( unsigned int ) 1 << 21 )        /* Pin Controlled by PA21 */
+#define AT91C_PA21_TF             ( ( unsigned int ) AT91C_PIO_PA21 ) /*  SSC Transmit Frame Sync */
+#define AT91C_PA21_NPCS10         ( ( unsigned int ) AT91C_PIO_PA21 ) /*  SPI 1 Peripheral Chip Select 0 */
+#define AT91C_PIO_PA22            ( ( unsigned int ) 1 << 22 )        /* Pin Controlled by PA22 */
+#define AT91C_PA22_TK             ( ( unsigned int ) AT91C_PIO_PA22 ) /*  SSC Transmit Clock */
+#define AT91C_PA22_SPCK1          ( ( unsigned int ) AT91C_PIO_PA22 ) /*  SPI 1 Serial Clock */
+#define AT91C_PIO_PA23            ( ( unsigned int ) 1 << 23 )        /* Pin Controlled by PA23 */
+#define AT91C_PA23_TD             ( ( unsigned int ) AT91C_PIO_PA23 ) /*  SSC Transmit data */
+#define AT91C_PA23_MOSI1          ( ( unsigned int ) AT91C_PIO_PA23 ) /*  SPI 1 Master Out Slave */
+#define AT91C_PIO_PA24            ( ( unsigned int ) 1 << 24 )        /* Pin Controlled by PA24 */
+#define AT91C_PA24_RD             ( ( unsigned int ) AT91C_PIO_PA24 ) /*  SSC Receive Data */
+#define AT91C_PA24_MISO1          ( ( unsigned int ) AT91C_PIO_PA24 ) /*  SPI 1 Master In Slave */
+#define AT91C_PIO_PA25            ( ( unsigned int ) 1 << 25 )        /* Pin Controlled by PA25 */
+#define AT91C_PA25_RK             ( ( unsigned int ) AT91C_PIO_PA25 ) /*  SSC Receive Clock */
+#define AT91C_PA25_NPCS11         ( ( unsigned int ) AT91C_PIO_PA25 ) /*  SPI 1 Peripheral Chip Select 1 */
+#define AT91C_PIO_PA26            ( ( unsigned int ) 1 << 26 )        /* Pin Controlled by PA26 */
+#define AT91C_PA26_RF             ( ( unsigned int ) AT91C_PIO_PA26 ) /*  SSC Receive Frame Sync */
+#define AT91C_PA26_NPCS12         ( ( unsigned int ) AT91C_PIO_PA26 ) /*  SPI 1 Peripheral Chip Select 2 */
+#define AT91C_PIO_PA27            ( ( unsigned int ) 1 << 27 )        /* Pin Controlled by PA27 */
+#define AT91C_PA27_DRXD           ( ( unsigned int ) AT91C_PIO_PA27 ) /*  DBGU Debug Receive Data */
+#define AT91C_PA27_PCK3           ( ( unsigned int ) AT91C_PIO_PA27 ) /*  PMC Programmable Clock Output 3 */
+#define AT91C_PIO_PA28            ( ( unsigned int ) 1 << 28 )        /* Pin Controlled by PA28 */
+#define AT91C_PA28_DTXD           ( ( unsigned int ) AT91C_PIO_PA28 ) /*  DBGU Debug Transmit Data */
+#define AT91C_PIO_PA29            ( ( unsigned int ) 1 << 29 )        /* Pin Controlled by PA29 */
+#define AT91C_PA29_FIQ            ( ( unsigned int ) AT91C_PIO_PA29 ) /*  AIC Fast Interrupt Input */
+#define AT91C_PA29_NPCS13         ( ( unsigned int ) AT91C_PIO_PA29 ) /*  SPI 1 Peripheral Chip Select 3 */
+#define AT91C_PIO_PA3             ( ( unsigned int ) 1 << 3 )         /* Pin Controlled by PA3 */
+#define AT91C_PA3_RTS0            ( ( unsigned int ) AT91C_PIO_PA3 )  /*  USART 0 Ready To Send */
+#define AT91C_PA3_NPCS12          ( ( unsigned int ) AT91C_PIO_PA3 )  /*  SPI 1 Peripheral Chip Select 2 */
+#define AT91C_PIO_PA30            ( ( unsigned int ) 1 << 30 )        /* Pin Controlled by PA30 */
+#define AT91C_PA30_IRQ0           ( ( unsigned int ) AT91C_PIO_PA30 ) /*  External Interrupt 0 */
+#define AT91C_PA30_PCK2           ( ( unsigned int ) AT91C_PIO_PA30 ) /*  PMC Programmable Clock Output 2 */
+#define AT91C_PIO_PA4             ( ( unsigned int ) 1 << 4 )         /* Pin Controlled by PA4 */
+#define AT91C_PA4_CTS0            ( ( unsigned int ) AT91C_PIO_PA4 )  /*  USART 0 Clear To Send */
+#define AT91C_PA4_NPCS13          ( ( unsigned int ) AT91C_PIO_PA4 )  /*  SPI 1 Peripheral Chip Select 3 */
+#define AT91C_PIO_PA5             ( ( unsigned int ) 1 << 5 )         /* Pin Controlled by PA5 */
+#define AT91C_PA5_RXD1            ( ( unsigned int ) AT91C_PIO_PA5 )  /*  USART 1 Receive Data */
+#define AT91C_PIO_PA6             ( ( unsigned int ) 1 << 6 )         /* Pin Controlled by PA6 */
+#define AT91C_PA6_TXD1            ( ( unsigned int ) AT91C_PIO_PA6 )  /*  USART 1 Transmit Data */
+#define AT91C_PIO_PA7             ( ( unsigned int ) 1 << 7 )         /* Pin Controlled by PA7 */
+#define AT91C_PA7_SCK1            ( ( unsigned int ) AT91C_PIO_PA7 )  /*  USART 1 Serial Clock */
+#define AT91C_PA7_NPCS01          ( ( unsigned int ) AT91C_PIO_PA7 )  /*  SPI 0 Peripheral Chip Select 1 */
+#define AT91C_PIO_PA8             ( ( unsigned int ) 1 << 8 )         /* Pin Controlled by PA8 */
+#define AT91C_PA8_RTS1            ( ( unsigned int ) AT91C_PIO_PA8 )  /*  USART 1 Ready To Send */
+#define AT91C_PA8_NPCS02          ( ( unsigned int ) AT91C_PIO_PA8 )  /*  SPI 0 Peripheral Chip Select 2 */
+#define AT91C_PIO_PA9             ( ( unsigned int ) 1 << 9 )         /* Pin Controlled by PA9 */
+#define AT91C_PA9_CTS1            ( ( unsigned int ) AT91C_PIO_PA9 )  /*  USART 1 Clear To Send */
+#define AT91C_PA9_NPCS03          ( ( unsigned int ) AT91C_PIO_PA9 )  /*  SPI 0 Peripheral Chip Select 3 */
+#define AT91C_PIO_PB0             ( ( unsigned int ) 1 << 0 )         /* Pin Controlled by PB0 */
+#define AT91C_PB0_ETXCK_EREFCK    ( ( unsigned int ) AT91C_PIO_PB0 )  /*  Ethernet MAC Transmit Clock/Reference Clock */
+#define AT91C_PB0_PCK0            ( ( unsigned int ) AT91C_PIO_PB0 )  /*  PMC Programmable Clock Output 0 */
+#define AT91C_PIO_PB1             ( ( unsigned int ) 1 << 1 )         /* Pin Controlled by PB1 */
+#define AT91C_PB1_ETXEN           ( ( unsigned int ) AT91C_PIO_PB1 )  /*  Ethernet MAC Transmit Enable */
+#define AT91C_PIO_PB10            ( ( unsigned int ) 1 << 10 )        /* Pin Controlled by PB10 */
+#define AT91C_PB10_ETX2           ( ( unsigned int ) AT91C_PIO_PB10 ) /*  Ethernet MAC Transmit Data 2 */
+#define AT91C_PB10_NPCS11         ( ( unsigned int ) AT91C_PIO_PB10 ) /*  SPI 1 Peripheral Chip Select 1 */
+#define AT91C_PIO_PB11            ( ( unsigned int ) 1 << 11 )        /* Pin Controlled by PB11 */
+#define AT91C_PB11_ETX3           ( ( unsigned int ) AT91C_PIO_PB11 ) /*  Ethernet MAC Transmit Data 3 */
+#define AT91C_PB11_NPCS12         ( ( unsigned int ) AT91C_PIO_PB11 ) /*  SPI 1 Peripheral Chip Select 2 */
+#define AT91C_PIO_PB12            ( ( unsigned int ) 1 << 12 )        /* Pin Controlled by PB12 */
+#define AT91C_PB12_ETXER          ( ( unsigned int ) AT91C_PIO_PB12 ) /*  Ethernet MAC Transmit Coding Error */
+#define AT91C_PB12_TCLK0          ( ( unsigned int ) AT91C_PIO_PB12 ) /*  Timer Counter 0 external clock input */
+#define AT91C_PIO_PB13            ( ( unsigned int ) 1 << 13 )        /* Pin Controlled by PB13 */
+#define AT91C_PB13_ERX2           ( ( unsigned int ) AT91C_PIO_PB13 ) /*  Ethernet MAC Receive Data 2 */
+#define AT91C_PB13_NPCS01         ( ( unsigned int ) AT91C_PIO_PB13 ) /*  SPI 0 Peripheral Chip Select 1 */
+#define AT91C_PIO_PB14            ( ( unsigned int ) 1 << 14 )        /* Pin Controlled by PB14 */
+#define AT91C_PB14_ERX3           ( ( unsigned int ) AT91C_PIO_PB14 ) /*  Ethernet MAC Receive Data 3 */
+#define AT91C_PB14_NPCS02         ( ( unsigned int ) AT91C_PIO_PB14 ) /*  SPI 0 Peripheral Chip Select 2 */
+#define AT91C_PIO_PB15            ( ( unsigned int ) 1 << 15 )        /* Pin Controlled by PB15 */
+#define AT91C_PB15_ERXDV          ( ( unsigned int ) AT91C_PIO_PB15 ) /*  Ethernet MAC Receive Data Valid */
+#define AT91C_PIO_PB16            ( ( unsigned int ) 1 << 16 )        /* Pin Controlled by PB16 */
+#define AT91C_PB16_ECOL           ( ( unsigned int ) AT91C_PIO_PB16 ) /*  Ethernet MAC Collision Detected */
+#define AT91C_PB16_NPCS13         ( ( unsigned int ) AT91C_PIO_PB16 ) /*  SPI 1 Peripheral Chip Select 3 */
+#define AT91C_PIO_PB17            ( ( unsigned int ) 1 << 17 )        /* Pin Controlled by PB17 */
+#define AT91C_PB17_ERXCK          ( ( unsigned int ) AT91C_PIO_PB17 ) /*  Ethernet MAC Receive Clock */
+#define AT91C_PB17_NPCS03         ( ( unsigned int ) AT91C_PIO_PB17 ) /*  SPI 0 Peripheral Chip Select 3 */
+#define AT91C_PIO_PB18            ( ( unsigned int ) 1 << 18 )        /* Pin Controlled by PB18 */
+#define AT91C_PB18_EF100          ( ( unsigned int ) AT91C_PIO_PB18 ) /*  Ethernet MAC Force 100 Mbits/sec */
+#define AT91C_PB18_ADTRG          ( ( unsigned int ) AT91C_PIO_PB18 ) /*  ADC External Trigger */
+#define AT91C_PIO_PB19            ( ( unsigned int ) 1 << 19 )        /* Pin Controlled by PB19 */
+#define AT91C_PB19_PWM0           ( ( unsigned int ) AT91C_PIO_PB19 ) /*  PWM Channel 0 */
+#define AT91C_PB19_TCLK1          ( ( unsigned int ) AT91C_PIO_PB19 ) /*  Timer Counter 1 external clock input */
+#define AT91C_PIO_PB2             ( ( unsigned int ) 1 << 2 )         /* Pin Controlled by PB2 */
+#define AT91C_PB2_ETX0            ( ( unsigned int ) AT91C_PIO_PB2 )  /*  Ethernet MAC Transmit Data 0 */
+#define AT91C_PIO_PB20            ( ( unsigned int ) 1 << 20 )        /* Pin Controlled by PB20 */
+#define AT91C_PB20_PWM1           ( ( unsigned int ) AT91C_PIO_PB20 ) /*  PWM Channel 1 */
+#define AT91C_PB20_PCK0           ( ( unsigned int ) AT91C_PIO_PB20 ) /*  PMC Programmable Clock Output 0 */
+#define AT91C_PIO_PB21            ( ( unsigned int ) 1 << 21 )        /* Pin Controlled by PB21 */
+#define AT91C_PB21_PWM2           ( ( unsigned int ) AT91C_PIO_PB21 ) /*  PWM Channel 2 */
+#define AT91C_PB21_PCK1           ( ( unsigned int ) AT91C_PIO_PB21 ) /*  PMC Programmable Clock Output 1 */
+#define AT91C_PIO_PB22            ( ( unsigned int ) 1 << 22 )        /* Pin Controlled by PB22 */
+#define AT91C_PB22_PWM3           ( ( unsigned int ) AT91C_PIO_PB22 ) /*  PWM Channel 3 */
+#define AT91C_PB22_PCK2           ( ( unsigned int ) AT91C_PIO_PB22 ) /*  PMC Programmable Clock Output 2 */
+#define AT91C_PIO_PB23            ( ( unsigned int ) 1 << 23 )        /* Pin Controlled by PB23 */
+#define AT91C_PB23_TIOA0          ( ( unsigned int ) AT91C_PIO_PB23 ) /*  Timer Counter 0 Multipurpose Timer I/O Pin A */
+#define AT91C_PB23_DCD1           ( ( unsigned int ) AT91C_PIO_PB23 ) /*  USART 1 Data Carrier Detect */
+#define AT91C_PIO_PB24            ( ( unsigned int ) 1 << 24 )        /* Pin Controlled by PB24 */
+#define AT91C_PB24_TIOB0          ( ( unsigned int ) AT91C_PIO_PB24 ) /*  Timer Counter 0 Multipurpose Timer I/O Pin B */
+#define AT91C_PB24_DSR1           ( ( unsigned int ) AT91C_PIO_PB24 ) /*  USART 1 Data Set ready */
+#define AT91C_PIO_PB25            ( ( unsigned int ) 1 << 25 )        /* Pin Controlled by PB25 */
+#define AT91C_PB25_TIOA1          ( ( unsigned int ) AT91C_PIO_PB25 ) /*  Timer Counter 1 Multipurpose Timer I/O Pin A */
+#define AT91C_PB25_DTR1           ( ( unsigned int ) AT91C_PIO_PB25 ) /*  USART 1 Data Terminal ready */
+#define AT91C_PIO_PB26            ( ( unsigned int ) 1 << 26 )        /* Pin Controlled by PB26 */
+#define AT91C_PB26_TIOB1          ( ( unsigned int ) AT91C_PIO_PB26 ) /*  Timer Counter 1 Multipurpose Timer I/O Pin B */
+#define AT91C_PB26_RI1            ( ( unsigned int ) AT91C_PIO_PB26 ) /*  USART 1 Ring Indicator */
+#define AT91C_PIO_PB27            ( ( unsigned int ) 1 << 27 )        /* Pin Controlled by PB27 */
+#define AT91C_PB27_TIOA2          ( ( unsigned int ) AT91C_PIO_PB27 ) /*  Timer Counter 2 Multipurpose Timer I/O Pin A */
+#define AT91C_PB27_PWM0           ( ( unsigned int ) AT91C_PIO_PB27 ) /*  PWM Channel 0 */
+#define AT91C_PIO_PB28            ( ( unsigned int ) 1 << 28 )        /* Pin Controlled by PB28 */
+#define AT91C_PB28_TIOB2          ( ( unsigned int ) AT91C_PIO_PB28 ) /*  Timer Counter 2 Multipurpose Timer I/O Pin B */
+#define AT91C_PB28_PWM1           ( ( unsigned int ) AT91C_PIO_PB28 ) /*  PWM Channel 1 */
+#define AT91C_PIO_PB29            ( ( unsigned int ) 1 << 29 )        /* Pin Controlled by PB29 */
+#define AT91C_PB29_PCK1           ( ( unsigned int ) AT91C_PIO_PB29 ) /*  PMC Programmable Clock Output 1 */
+#define AT91C_PB29_PWM2           ( ( unsigned int ) AT91C_PIO_PB29 ) /*  PWM Channel 2 */
+#define AT91C_PIO_PB3             ( ( unsigned int ) 1 << 3 )         /* Pin Controlled by PB3 */
+#define AT91C_PB3_ETX1            ( ( unsigned int ) AT91C_PIO_PB3 )  /*  Ethernet MAC Transmit Data 1 */
+#define AT91C_PIO_PB30            ( ( unsigned int ) 1 << 30 )        /* Pin Controlled by PB30 */
+#define AT91C_PB30_PCK2           ( ( unsigned int ) AT91C_PIO_PB30 ) /*  PMC Programmable Clock Output 2 */
+#define AT91C_PB30_PWM3           ( ( unsigned int ) AT91C_PIO_PB30 ) /*  PWM Channel 3 */
+#define AT91C_PIO_PB4             ( ( unsigned int ) 1 << 4 )         /* Pin Controlled by PB4 */
+#define AT91C_PB4_ECRS_ECRSDV     ( ( unsigned int ) AT91C_PIO_PB4 )  /*  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid */
+#define AT91C_PIO_PB5             ( ( unsigned int ) 1 << 5 )         /* Pin Controlled by PB5 */
+#define AT91C_PB5_ERX0            ( ( unsigned int ) AT91C_PIO_PB5 )  /*  Ethernet MAC Receive Data 0 */
+#define AT91C_PIO_PB6             ( ( unsigned int ) 1 << 6 )         /* Pin Controlled by PB6 */
+#define AT91C_PB6_ERX1            ( ( unsigned int ) AT91C_PIO_PB6 )  /*  Ethernet MAC Receive Data 1 */
+#define AT91C_PIO_PB7             ( ( unsigned int ) 1 << 7 )         /* Pin Controlled by PB7 */
+#define AT91C_PB7_ERXER           ( ( unsigned int ) AT91C_PIO_PB7 )  /*  Ethernet MAC Receive Error */
+#define AT91C_PIO_PB8             ( ( unsigned int ) 1 << 8 )         /* Pin Controlled by PB8 */
+#define AT91C_PB8_EMDC            ( ( unsigned int ) AT91C_PIO_PB8 )  /*  Ethernet MAC Management Data Clock */
+#define AT91C_PIO_PB9             ( ( unsigned int ) 1 << 9 )         /* Pin Controlled by PB9 */
+#define AT91C_PB9_EMDIO           ( ( unsigned int ) AT91C_PIO_PB9 )  /*  Ethernet MAC Management Data Input/Output */
 
-// *****************************************************************************
-//               PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256
-// *****************************************************************************
-#define AT91C_ID_FIQ    ((unsigned int)  0) // Advanced Interrupt Controller (FIQ)
-#define AT91C_ID_SYS    ((unsigned int)  1) // System Peripheral
-#define AT91C_ID_PIOA   ((unsigned int)  2) // Parallel IO Controller A
-#define AT91C_ID_PIOB   ((unsigned int)  3) // Parallel IO Controller B
-#define AT91C_ID_SPI0   ((unsigned int)  4) // Serial Peripheral Interface 0
-#define AT91C_ID_SPI1   ((unsigned int)  5) // Serial Peripheral Interface 1
-#define AT91C_ID_US0    ((unsigned int)  6) // USART 0
-#define AT91C_ID_US1    ((unsigned int)  7) // USART 1
-#define AT91C_ID_SSC    ((unsigned int)  8) // Serial Synchronous Controller
-#define AT91C_ID_TWI    ((unsigned int)  9) // Two-Wire Interface
-#define AT91C_ID_PWMC   ((unsigned int) 10) // PWM Controller
-#define AT91C_ID_UDP    ((unsigned int) 11) // USB Device Port
-#define AT91C_ID_TC0    ((unsigned int) 12) // Timer Counter 0
-#define AT91C_ID_TC1    ((unsigned int) 13) // Timer Counter 1
-#define AT91C_ID_TC2    ((unsigned int) 14) // Timer Counter 2
-#define AT91C_ID_CAN    ((unsigned int) 15) // Control Area Network Controller
-#define AT91C_ID_EMAC   ((unsigned int) 16) // Ethernet MAC
-#define AT91C_ID_ADC    ((unsigned int) 17) // Analog-to-Digital Converter
-#define AT91C_ID_AES    ((unsigned int) 18) // Advanced Encryption Standard 128-bit
-#define AT91C_ID_TDES   ((unsigned int) 19) // Triple Data Encryption Standard
-#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved
-#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved
-#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved
-#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved
-#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved
-#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved
-#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved
-#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved
-#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved
-#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved
-#define AT91C_ID_IRQ0   ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0)
-#define AT91C_ID_IRQ1   ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1)
+/* ***************************************************************************** */
+/*               PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 */
+/* ***************************************************************************** */
+#define AT91C_ID_FIQ            ( ( unsigned int ) 0 )  /* Advanced Interrupt Controller (FIQ) */
+#define AT91C_ID_SYS            ( ( unsigned int ) 1 )  /* System Peripheral */
+#define AT91C_ID_PIOA           ( ( unsigned int ) 2 )  /* Parallel IO Controller A */
+#define AT91C_ID_PIOB           ( ( unsigned int ) 3 )  /* Parallel IO Controller B */
+#define AT91C_ID_SPI0           ( ( unsigned int ) 4 )  /* Serial Peripheral Interface 0 */
+#define AT91C_ID_SPI1           ( ( unsigned int ) 5 )  /* Serial Peripheral Interface 1 */
+#define AT91C_ID_US0            ( ( unsigned int ) 6 )  /* USART 0 */
+#define AT91C_ID_US1            ( ( unsigned int ) 7 )  /* USART 1 */
+#define AT91C_ID_SSC            ( ( unsigned int ) 8 )  /* Serial Synchronous Controller */
+#define AT91C_ID_TWI            ( ( unsigned int ) 9 )  /* Two-Wire Interface */
+#define AT91C_ID_PWMC           ( ( unsigned int ) 10 ) /* PWM Controller */
+#define AT91C_ID_UDP            ( ( unsigned int ) 11 ) /* USB Device Port */
+#define AT91C_ID_TC0            ( ( unsigned int ) 12 ) /* Timer Counter 0 */
+#define AT91C_ID_TC1            ( ( unsigned int ) 13 ) /* Timer Counter 1 */
+#define AT91C_ID_TC2            ( ( unsigned int ) 14 ) /* Timer Counter 2 */
+#define AT91C_ID_CAN            ( ( unsigned int ) 15 ) /* Control Area Network Controller */
+#define AT91C_ID_EMAC           ( ( unsigned int ) 16 ) /* Ethernet MAC */
+#define AT91C_ID_ADC            ( ( unsigned int ) 17 ) /* Analog-to-Digital Converter */
+#define AT91C_ID_AES            ( ( unsigned int ) 18 ) /* Advanced Encryption Standard 128-bit */
+#define AT91C_ID_TDES           ( ( unsigned int ) 19 ) /* Triple Data Encryption Standard */
+#define AT91C_ID_20_Reserved    ( ( unsigned int ) 20 ) /* Reserved */
+#define AT91C_ID_21_Reserved    ( ( unsigned int ) 21 ) /* Reserved */
+#define AT91C_ID_22_Reserved    ( ( unsigned int ) 22 ) /* Reserved */
+#define AT91C_ID_23_Reserved    ( ( unsigned int ) 23 ) /* Reserved */
+#define AT91C_ID_24_Reserved    ( ( unsigned int ) 24 ) /* Reserved */
+#define AT91C_ID_25_Reserved    ( ( unsigned int ) 25 ) /* Reserved */
+#define AT91C_ID_26_Reserved    ( ( unsigned int ) 26 ) /* Reserved */
+#define AT91C_ID_27_Reserved    ( ( unsigned int ) 27 ) /* Reserved */
+#define AT91C_ID_28_Reserved    ( ( unsigned int ) 28 ) /* Reserved */
+#define AT91C_ID_29_Reserved    ( ( unsigned int ) 29 ) /* Reserved */
+#define AT91C_ID_IRQ0           ( ( unsigned int ) 30 ) /* Advanced Interrupt Controller (IRQ0) */
+#define AT91C_ID_IRQ1           ( ( unsigned int ) 31 ) /* Advanced Interrupt Controller (IRQ1) */
 
-// *****************************************************************************
-//               BASE ADDRESS DEFINITIONS FOR AT91SAM7X256
-// *****************************************************************************
-#define AT91C_BASE_SYS       ((AT91PS_SYS)  0xFFFFF000) // (SYS) Base Address
-#define AT91C_BASE_AIC       ((AT91PS_AIC)  0xFFFFF000) // (AIC) Base Address
-#define AT91C_BASE_PDC_DBGU  ((AT91PS_PDC)  0xFFFFF300) // (PDC_DBGU) Base Address
-#define AT91C_BASE_DBGU      ((AT91PS_DBGU)     0xFFFFF200) // (DBGU) Base Address
-#define AT91C_BASE_PIOA      ((AT91PS_PIO)  0xFFFFF400) // (PIOA) Base Address
-#define AT91C_BASE_PIOB      ((AT91PS_PIO)  0xFFFFF600) // (PIOB) Base Address
-#define AT91C_BASE_CKGR      ((AT91PS_CKGR)     0xFFFFFC20) // (CKGR) Base Address
-#define AT91C_BASE_PMC       ((AT91PS_PMC)  0xFFFFFC00) // (PMC) Base Address
-#define AT91C_BASE_RSTC      ((AT91PS_RSTC)     0xFFFFFD00) // (RSTC) Base Address
-#define AT91C_BASE_RTTC      ((AT91PS_RTTC)     0xFFFFFD20) // (RTTC) Base Address
-#define AT91C_BASE_PITC      ((AT91PS_PITC)     0xFFFFFD30) // (PITC) Base Address
-#define AT91C_BASE_WDTC      ((AT91PS_WDTC)     0xFFFFFD40) // (WDTC) Base Address
-#define AT91C_BASE_VREG      ((AT91PS_VREG)     0xFFFFFD60) // (VREG) Base Address
-#define AT91C_BASE_MC        ((AT91PS_MC)   0xFFFFFF00) // (MC) Base Address
-#define AT91C_BASE_PDC_SPI1  ((AT91PS_PDC)  0xFFFE4100) // (PDC_SPI1) Base Address
-#define AT91C_BASE_SPI1      ((AT91PS_SPI)  0xFFFE4000) // (SPI1) Base Address
-#define AT91C_BASE_PDC_SPI0  ((AT91PS_PDC)  0xFFFE0100) // (PDC_SPI0) Base Address
-#define AT91C_BASE_SPI0      ((AT91PS_SPI)  0xFFFE0000) // (SPI0) Base Address
-#define AT91C_BASE_PDC_US1   ((AT91PS_PDC)  0xFFFC4100) // (PDC_US1) Base Address
-#define AT91C_BASE_US1       ((AT91PS_USART)    0xFFFC4000) // (US1) Base Address
-#define AT91C_BASE_PDC_US0   ((AT91PS_PDC)  0xFFFC0100) // (PDC_US0) Base Address
-#define AT91C_BASE_US0       ((AT91PS_USART)    0xFFFC0000) // (US0) Base Address
-#define AT91C_BASE_PDC_SSC   ((AT91PS_PDC)  0xFFFD4100) // (PDC_SSC) Base Address
-#define AT91C_BASE_SSC       ((AT91PS_SSC)  0xFFFD4000) // (SSC) Base Address
-#define AT91C_BASE_TWI       ((AT91PS_TWI)  0xFFFB8000) // (TWI) Base Address
-#define AT91C_BASE_PWMC_CH3  ((AT91PS_PWMC_CH)  0xFFFCC260) // (PWMC_CH3) Base Address
-#define AT91C_BASE_PWMC_CH2  ((AT91PS_PWMC_CH)  0xFFFCC240) // (PWMC_CH2) Base Address
-#define AT91C_BASE_PWMC_CH1  ((AT91PS_PWMC_CH)  0xFFFCC220) // (PWMC_CH1) Base Address
-#define AT91C_BASE_PWMC_CH0  ((AT91PS_PWMC_CH)  0xFFFCC200) // (PWMC_CH0) Base Address
-#define AT91C_BASE_PWMC      ((AT91PS_PWMC)     0xFFFCC000) // (PWMC) Base Address
-#define AT91C_BASE_UDP       ((AT91PS_UDP)  0xFFFB0000) // (UDP) Base Address
-#define AT91C_BASE_TC0       ((AT91PS_TC)   0xFFFA0000) // (TC0) Base Address
-#define AT91C_BASE_TC1       ((AT91PS_TC)   0xFFFA0040) // (TC1) Base Address
-#define AT91C_BASE_TC2       ((AT91PS_TC)   0xFFFA0080) // (TC2) Base Address
-#define AT91C_BASE_TCB       ((AT91PS_TCB)  0xFFFA0000) // (TCB) Base Address
-#define AT91C_BASE_CAN_MB0   ((AT91PS_CAN_MB)   0xFFFD0200) // (CAN_MB0) Base Address
-#define AT91C_BASE_CAN_MB1   ((AT91PS_CAN_MB)   0xFFFD0220) // (CAN_MB1) Base Address
-#define AT91C_BASE_CAN_MB2   ((AT91PS_CAN_MB)   0xFFFD0240) // (CAN_MB2) Base Address
-#define AT91C_BASE_CAN_MB3   ((AT91PS_CAN_MB)   0xFFFD0260) // (CAN_MB3) Base Address
-#define AT91C_BASE_CAN_MB4   ((AT91PS_CAN_MB)   0xFFFD0280) // (CAN_MB4) Base Address
-#define AT91C_BASE_CAN_MB5   ((AT91PS_CAN_MB)   0xFFFD02A0) // (CAN_MB5) Base Address
-#define AT91C_BASE_CAN_MB6   ((AT91PS_CAN_MB)   0xFFFD02C0) // (CAN_MB6) Base Address
-#define AT91C_BASE_CAN_MB7   ((AT91PS_CAN_MB)   0xFFFD02E0) // (CAN_MB7) Base Address
-#define AT91C_BASE_CAN       ((AT91PS_CAN)  0xFFFD0000) // (CAN) Base Address
-#define AT91C_BASE_EMAC      ((AT91PS_EMAC)     0xFFFDC000) // (EMAC) Base Address
-#define AT91C_BASE_PDC_ADC   ((AT91PS_PDC)  0xFFFD8100) // (PDC_ADC) Base Address
-#define AT91C_BASE_ADC       ((AT91PS_ADC)  0xFFFD8000) // (ADC) Base Address
-#define AT91C_BASE_PDC_AES   ((AT91PS_PDC)  0xFFFA4100) // (PDC_AES) Base Address
-#define AT91C_BASE_AES       ((AT91PS_AES)  0xFFFA4000) // (AES) Base Address
-#define AT91C_BASE_PDC_TDES  ((AT91PS_PDC)  0xFFFA8100) // (PDC_TDES) Base Address
-#define AT91C_BASE_TDES      ((AT91PS_TDES)     0xFFFA8000) // (TDES) Base Address
+/* ***************************************************************************** */
+/*               BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 */
+/* ***************************************************************************** */
+#define AT91C_BASE_SYS         ( ( AT91PS_SYS ) 0xFFFFF000 )     /* (SYS) Base Address */
+#define AT91C_BASE_AIC         ( ( AT91PS_AIC ) 0xFFFFF000 )     /* (AIC) Base Address */
+#define AT91C_BASE_PDC_DBGU    ( ( AT91PS_PDC ) 0xFFFFF300 )     /* (PDC_DBGU) Base Address */
+#define AT91C_BASE_DBGU        ( ( AT91PS_DBGU ) 0xFFFFF200 )    /* (DBGU) Base Address */
+#define AT91C_BASE_PIOA        ( ( AT91PS_PIO ) 0xFFFFF400 )     /* (PIOA) Base Address */
+#define AT91C_BASE_PIOB        ( ( AT91PS_PIO ) 0xFFFFF600 )     /* (PIOB) Base Address */
+#define AT91C_BASE_CKGR        ( ( AT91PS_CKGR ) 0xFFFFFC20 )    /* (CKGR) Base Address */
+#define AT91C_BASE_PMC         ( ( AT91PS_PMC ) 0xFFFFFC00 )     /* (PMC) Base Address */
+#define AT91C_BASE_RSTC        ( ( AT91PS_RSTC ) 0xFFFFFD00 )    /* (RSTC) Base Address */
+#define AT91C_BASE_RTTC        ( ( AT91PS_RTTC ) 0xFFFFFD20 )    /* (RTTC) Base Address */
+#define AT91C_BASE_PITC        ( ( AT91PS_PITC ) 0xFFFFFD30 )    /* (PITC) Base Address */
+#define AT91C_BASE_WDTC        ( ( AT91PS_WDTC ) 0xFFFFFD40 )    /* (WDTC) Base Address */
+#define AT91C_BASE_VREG        ( ( AT91PS_VREG ) 0xFFFFFD60 )    /* (VREG) Base Address */
+#define AT91C_BASE_MC          ( ( AT91PS_MC ) 0xFFFFFF00 )      /* (MC) Base Address */
+#define AT91C_BASE_PDC_SPI1    ( ( AT91PS_PDC ) 0xFFFE4100 )     /* (PDC_SPI1) Base Address */
+#define AT91C_BASE_SPI1        ( ( AT91PS_SPI ) 0xFFFE4000 )     /* (SPI1) Base Address */
+#define AT91C_BASE_PDC_SPI0    ( ( AT91PS_PDC ) 0xFFFE0100 )     /* (PDC_SPI0) Base Address */
+#define AT91C_BASE_SPI0        ( ( AT91PS_SPI ) 0xFFFE0000 )     /* (SPI0) Base Address */
+#define AT91C_BASE_PDC_US1     ( ( AT91PS_PDC ) 0xFFFC4100 )     /* (PDC_US1) Base Address */
+#define AT91C_BASE_US1         ( ( AT91PS_USART ) 0xFFFC4000 )   /* (US1) Base Address */
+#define AT91C_BASE_PDC_US0     ( ( AT91PS_PDC ) 0xFFFC0100 )     /* (PDC_US0) Base Address */
+#define AT91C_BASE_US0         ( ( AT91PS_USART ) 0xFFFC0000 )   /* (US0) Base Address */
+#define AT91C_BASE_PDC_SSC     ( ( AT91PS_PDC ) 0xFFFD4100 )     /* (PDC_SSC) Base Address */
+#define AT91C_BASE_SSC         ( ( AT91PS_SSC ) 0xFFFD4000 )     /* (SSC) Base Address */
+#define AT91C_BASE_TWI         ( ( AT91PS_TWI ) 0xFFFB8000 )     /* (TWI) Base Address */
+#define AT91C_BASE_PWMC_CH3    ( ( AT91PS_PWMC_CH ) 0xFFFCC260 ) /* (PWMC_CH3) Base Address */
+#define AT91C_BASE_PWMC_CH2    ( ( AT91PS_PWMC_CH ) 0xFFFCC240 ) /* (PWMC_CH2) Base Address */
+#define AT91C_BASE_PWMC_CH1    ( ( AT91PS_PWMC_CH ) 0xFFFCC220 ) /* (PWMC_CH1) Base Address */
+#define AT91C_BASE_PWMC_CH0    ( ( AT91PS_PWMC_CH ) 0xFFFCC200 ) /* (PWMC_CH0) Base Address */
+#define AT91C_BASE_PWMC        ( ( AT91PS_PWMC ) 0xFFFCC000 )    /* (PWMC) Base Address */
+#define AT91C_BASE_UDP         ( ( AT91PS_UDP ) 0xFFFB0000 )     /* (UDP) Base Address */
+#define AT91C_BASE_TC0         ( ( AT91PS_TC ) 0xFFFA0000 )      /* (TC0) Base Address */
+#define AT91C_BASE_TC1         ( ( AT91PS_TC ) 0xFFFA0040 )      /* (TC1) Base Address */
+#define AT91C_BASE_TC2         ( ( AT91PS_TC ) 0xFFFA0080 )      /* (TC2) Base Address */
+#define AT91C_BASE_TCB         ( ( AT91PS_TCB ) 0xFFFA0000 )     /* (TCB) Base Address */
+#define AT91C_BASE_CAN_MB0     ( ( AT91PS_CAN_MB ) 0xFFFD0200 )  /* (CAN_MB0) Base Address */
+#define AT91C_BASE_CAN_MB1     ( ( AT91PS_CAN_MB ) 0xFFFD0220 )  /* (CAN_MB1) Base Address */
+#define AT91C_BASE_CAN_MB2     ( ( AT91PS_CAN_MB ) 0xFFFD0240 )  /* (CAN_MB2) Base Address */
+#define AT91C_BASE_CAN_MB3     ( ( AT91PS_CAN_MB ) 0xFFFD0260 )  /* (CAN_MB3) Base Address */
+#define AT91C_BASE_CAN_MB4     ( ( AT91PS_CAN_MB ) 0xFFFD0280 )  /* (CAN_MB4) Base Address */
+#define AT91C_BASE_CAN_MB5     ( ( AT91PS_CAN_MB ) 0xFFFD02A0 )  /* (CAN_MB5) Base Address */
+#define AT91C_BASE_CAN_MB6     ( ( AT91PS_CAN_MB ) 0xFFFD02C0 )  /* (CAN_MB6) Base Address */
+#define AT91C_BASE_CAN_MB7     ( ( AT91PS_CAN_MB ) 0xFFFD02E0 )  /* (CAN_MB7) Base Address */
+#define AT91C_BASE_CAN         ( ( AT91PS_CAN ) 0xFFFD0000 )     /* (CAN) Base Address */
+#define AT91C_BASE_EMAC        ( ( AT91PS_EMAC ) 0xFFFDC000 )    /* (EMAC) Base Address */
+#define AT91C_BASE_PDC_ADC     ( ( AT91PS_PDC ) 0xFFFD8100 )     /* (PDC_ADC) Base Address */
+#define AT91C_BASE_ADC         ( ( AT91PS_ADC ) 0xFFFD8000 )     /* (ADC) Base Address */
+#define AT91C_BASE_PDC_AES     ( ( AT91PS_PDC ) 0xFFFA4100 )     /* (PDC_AES) Base Address */
+#define AT91C_BASE_AES         ( ( AT91PS_AES ) 0xFFFA4000 )     /* (AES) Base Address */
+#define AT91C_BASE_PDC_TDES    ( ( AT91PS_PDC ) 0xFFFA8100 )     /* (PDC_TDES) Base Address */
+#define AT91C_BASE_TDES        ( ( AT91PS_TDES ) 0xFFFA8000 )    /* (TDES) Base Address */
 
-// *****************************************************************************
-//               MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256
-// *****************************************************************************
-#define AT91C_ISRAM  ((char *)  0x00200000) // Internal SRAM base address
-#define AT91C_ISRAM_SIZE     ((unsigned int) 0x00010000) // Internal SRAM size in byte (64 Kbyte)
-#define AT91C_IFLASH     ((char *)  0x00100000) // Internal ROM base address
-#define AT91C_IFLASH_SIZE    ((unsigned int) 0x00040000) // Internal ROM size in byte (256 Kbyte)
+/* ***************************************************************************** */
+/*               MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 */
+/* ***************************************************************************** */
+#define AT91C_ISRAM          ( ( char * ) 0x00200000 )       /* Internal SRAM base address */
+#define AT91C_ISRAM_SIZE     ( ( unsigned int ) 0x00010000 ) /* Internal SRAM size in byte (64 Kbyte) */
+#define AT91C_IFLASH         ( ( char * ) 0x00100000 )       /* Internal ROM base address */
+#define AT91C_IFLASH_SIZE    ( ( unsigned int ) 0x00040000 ) /* Internal ROM size in byte (256 Kbyte) */
 
-#endif
+#endif /* ifndef AT91SAM7X256_H */
diff --git a/portable/IAR/AtmelSAM7S64/AT91SAM7X256_inc.h b/portable/IAR/AtmelSAM7S64/AT91SAM7X256_inc.h
index c85684df6..5c0be5efc 100644
--- a/portable/IAR/AtmelSAM7S64/AT91SAM7X256_inc.h
+++ b/portable/IAR/AtmelSAM7S64/AT91SAM7X256_inc.h
@@ -1,2444 +1,2444 @@
-//  ----------------------------------------------------------------------------
-//          ATMEL Microcontroller Software Support  -  ROUSSET  -
-//  ----------------------------------------------------------------------------
-//  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
-//  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
-//  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
-//  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
-//  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-//  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-//  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-//  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//  ----------------------------------------------------------------------------
-// File Name           : AT91SAM7X256.h
-// Object              : AT91SAM7X256 definitions
-// Generated           : AT91 SW Application Group  05/20/2005 (16:22:29)
-//
-// CVS Reference       : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005//
-// CVS Reference       : /SYS_SAM7X.pl/1.3/Tue Feb  1 17:01:43 2005//
-// CVS Reference       : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005//
-// CVS Reference       : /PMC_SAM7X.pl/1.4/Tue Feb  8 13:58:10 2005//
-// CVS Reference       : /RSTC_SAM7X.pl/1.1/Tue Feb  1 16:16:26 2005//
-// CVS Reference       : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005//
-// CVS Reference       : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005//
-// CVS Reference       : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//
-// CVS Reference       : /PIO_6057A.pl/1.2/Thu Feb  3 10:18:28 2005//
-// CVS Reference       : /RTTC_6081A.pl/1.2/Tue Nov  9 14:43:58 2004//
-// CVS Reference       : /PITC_6079A.pl/1.2/Tue Nov  9 14:43:56 2004//
-// CVS Reference       : /WDTC_6080A.pl/1.3/Tue Nov  9 14:44:00 2004//
-// CVS Reference       : /VREG_6085B.pl/1.1/Tue Feb  1 16:05:48 2005//
-// CVS Reference       : /PDC_6074C.pl/1.2/Thu Feb  3 08:48:54 2005//
-// CVS Reference       : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//
-// CVS Reference       : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//
-// CVS Reference       : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//
-// CVS Reference       : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//
-// CVS Reference       : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//
-// CVS Reference       : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//
-// CVS Reference       : /CAN_6019B.pl/1.1/Tue Mar  8 12:42:22 2005//
-// CVS Reference       : /EMACB_6119A.pl/1.5/Thu Feb  3 15:52:04 2005//
-// CVS Reference       : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//
-// CVS Reference       : /AES_6149A.pl/1.10/Mon Feb  7 09:44:25 2005//
-// CVS Reference       : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005//
-//  ----------------------------------------------------------------------------
+/*  ---------------------------------------------------------------------------- */
+/*          ATMEL Microcontroller Software Support  -  ROUSSET  - */
+/*  ---------------------------------------------------------------------------- */
+/*  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
+/*  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
+/*  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
+/*  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
+/*  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
+/*  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
+/*  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/*  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
+/*  ---------------------------------------------------------------------------- */
+/* File Name           : AT91SAM7X256.h */
+/* Object              : AT91SAM7X256 definitions */
+/* Generated           : AT91 SW Application Group  05/20/2005 (16:22:29) */
+/* */
+/* CVS Reference       : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005// */
+/* CVS Reference       : /SYS_SAM7X.pl/1.3/Tue Feb  1 17:01:43 2005// */
+/* CVS Reference       : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// */
+/* CVS Reference       : /PMC_SAM7X.pl/1.4/Tue Feb  8 13:58:10 2005// */
+/* CVS Reference       : /RSTC_SAM7X.pl/1.1/Tue Feb  1 16:16:26 2005// */
+/* CVS Reference       : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// */
+/* CVS Reference       : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// */
+/* CVS Reference       : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// */
+/* CVS Reference       : /PIO_6057A.pl/1.2/Thu Feb  3 10:18:28 2005// */
+/* CVS Reference       : /RTTC_6081A.pl/1.2/Tue Nov  9 14:43:58 2004// */
+/* CVS Reference       : /PITC_6079A.pl/1.2/Tue Nov  9 14:43:56 2004// */
+/* CVS Reference       : /WDTC_6080A.pl/1.3/Tue Nov  9 14:44:00 2004// */
+/* CVS Reference       : /VREG_6085B.pl/1.1/Tue Feb  1 16:05:48 2005// */
+/* CVS Reference       : /PDC_6074C.pl/1.2/Thu Feb  3 08:48:54 2005// */
+/* CVS Reference       : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// */
+/* CVS Reference       : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// */
+/* CVS Reference       : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// */
+/* CVS Reference       : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// */
+/* CVS Reference       : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// */
+/* CVS Reference       : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// */
+/* CVS Reference       : /CAN_6019B.pl/1.1/Tue Mar  8 12:42:22 2005// */
+/* CVS Reference       : /EMACB_6119A.pl/1.5/Thu Feb  3 15:52:04 2005// */
+/* CVS Reference       : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// */
+/* CVS Reference       : /AES_6149A.pl/1.10/Mon Feb  7 09:44:25 2005// */
+/* CVS Reference       : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// */
+/*  ---------------------------------------------------------------------------- */
 
-// Hardware register definition
+/* Hardware register definition */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR System Peripherals
-// *****************************************************************************
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR System Peripherals */
+/* ***************************************************************************** */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
-// *****************************************************************************
-// *** Register offset in AT91S_AIC structure ***
-#define AIC_SMR         ( 0) // Source Mode Register
-#define AIC_SVR         (128) // Source Vector Register
-#define AIC_IVR         (256) // IRQ Vector Register
-#define AIC_FVR         (260) // FIQ Vector Register
-#define AIC_ISR         (264) // Interrupt Status Register
-#define AIC_IPR         (268) // Interrupt Pending Register
-#define AIC_IMR         (272) // Interrupt Mask Register
-#define AIC_CISR        (276) // Core Interrupt Status Register
-#define AIC_IECR        (288) // Interrupt Enable Command Register
-#define AIC_IDCR        (292) // Interrupt Disable Command Register
-#define AIC_ICCR        (296) // Interrupt Clear Command Register
-#define AIC_ISCR        (300) // Interrupt Set Command Register
-#define AIC_EOICR       (304) // End of Interrupt Command Register
-#define AIC_SPU         (308) // Spurious Vector Register
-#define AIC_DCR         (312) // Debug Control Register (Protect)
-#define AIC_FFER        (320) // Fast Forcing Enable Register
-#define AIC_FFDR        (324) // Fast Forcing Disable Register
-#define AIC_FFSR        (328) // Fast Forcing Status Register
-// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
-#define AT91C_AIC_PRIOR           (0x7 <<  0) // (AIC) Priority Level
-#define     AT91C_AIC_PRIOR_LOWEST               (0x0) // (AIC) Lowest priority level
-#define     AT91C_AIC_PRIOR_HIGHEST              (0x7) // (AIC) Highest priority level
-#define AT91C_AIC_SRCTYPE         (0x3 <<  5) // (AIC) Interrupt Source Type
-#define     AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL       (0x0 <<  5) // (AIC) Internal Sources Code Label High-level Sensitive
-#define     AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL        (0x0 <<  5) // (AIC) External Sources Code Label Low-level Sensitive
-#define     AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE    (0x1 <<  5) // (AIC) Internal Sources Code Label Positive Edge triggered
-#define     AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE    (0x1 <<  5) // (AIC) External Sources Code Label Negative Edge triggered
-#define     AT91C_AIC_SRCTYPE_HIGH_LEVEL           (0x2 <<  5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
-#define     AT91C_AIC_SRCTYPE_POSITIVE_EDGE        (0x3 <<  5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
-// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
-#define AT91C_AIC_NFIQ            (0x1 <<  0) // (AIC) NFIQ Status
-#define AT91C_AIC_NIRQ            (0x1 <<  1) // (AIC) NIRQ Status
-// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
-#define AT91C_AIC_DCR_PROT        (0x1 <<  0) // (AIC) Protection Mode
-#define AT91C_AIC_DCR_GMSK        (0x1 <<  1) // (AIC) General Mask
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_AIC structure *** */
+#define AIC_SMR                                    ( 0 )        /* Source Mode Register */
+#define AIC_SVR                                    ( 128 )      /* Source Vector Register */
+#define AIC_IVR                                    ( 256 )      /* IRQ Vector Register */
+#define AIC_FVR                                    ( 260 )      /* FIQ Vector Register */
+#define AIC_ISR                                    ( 264 )      /* Interrupt Status Register */
+#define AIC_IPR                                    ( 268 )      /* Interrupt Pending Register */
+#define AIC_IMR                                    ( 272 )      /* Interrupt Mask Register */
+#define AIC_CISR                                   ( 276 )      /* Core Interrupt Status Register */
+#define AIC_IECR                                   ( 288 )      /* Interrupt Enable Command Register */
+#define AIC_IDCR                                   ( 292 )      /* Interrupt Disable Command Register */
+#define AIC_ICCR                                   ( 296 )      /* Interrupt Clear Command Register */
+#define AIC_ISCR                                   ( 300 )      /* Interrupt Set Command Register */
+#define AIC_EOICR                                  ( 304 )      /* End of Interrupt Command Register */
+#define AIC_SPU                                    ( 308 )      /* Spurious Vector Register */
+#define AIC_DCR                                    ( 312 )      /* Debug Control Register (Protect) */
+#define AIC_FFER                                   ( 320 )      /* Fast Forcing Enable Register */
+#define AIC_FFDR                                   ( 324 )      /* Fast Forcing Disable Register */
+#define AIC_FFSR                                   ( 328 )      /* Fast Forcing Status Register */
+/* -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- */
+#define AT91C_AIC_PRIOR                            ( 0x7 << 0 ) /* (AIC) Priority Level */
+#define     AT91C_AIC_PRIOR_LOWEST                 ( 0x0 )      /* (AIC) Lowest priority level */
+#define     AT91C_AIC_PRIOR_HIGHEST                ( 0x7 )      /* (AIC) Highest priority level */
+#define AT91C_AIC_SRCTYPE                          ( 0x3 << 5 ) /* (AIC) Interrupt Source Type */
+#define     AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL       ( 0x0 << 5 ) /* (AIC) Internal Sources Code Label High-level Sensitive */
+#define     AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL        ( 0x0 << 5 ) /* (AIC) External Sources Code Label Low-level Sensitive */
+#define     AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE    ( 0x1 << 5 ) /* (AIC) Internal Sources Code Label Positive Edge triggered */
+#define     AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE    ( 0x1 << 5 ) /* (AIC) External Sources Code Label Negative Edge triggered */
+#define     AT91C_AIC_SRCTYPE_HIGH_LEVEL           ( 0x2 << 5 ) /* (AIC) Internal Or External Sources Code Label High-level Sensitive */
+#define     AT91C_AIC_SRCTYPE_POSITIVE_EDGE        ( 0x3 << 5 ) /* (AIC) Internal Or External Sources Code Label Positive Edge triggered */
+/* -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- */
+#define AT91C_AIC_NFIQ                             ( 0x1 << 0 ) /* (AIC) NFIQ Status */
+#define AT91C_AIC_NIRQ                             ( 0x1 << 1 ) /* (AIC) NIRQ Status */
+/* -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- */
+#define AT91C_AIC_DCR_PROT                         ( 0x1 << 0 ) /* (AIC) Protection Mode */
+#define AT91C_AIC_DCR_GMSK                         ( 0x1 << 1 ) /* (AIC) General Mask */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller
-// *****************************************************************************
-// *** Register offset in AT91S_PDC structure ***
-#define PDC_RPR         ( 0) // Receive Pointer Register
-#define PDC_RCR         ( 4) // Receive Counter Register
-#define PDC_TPR         ( 8) // Transmit Pointer Register
-#define PDC_TCR         (12) // Transmit Counter Register
-#define PDC_RNPR        (16) // Receive Next Pointer Register
-#define PDC_RNCR        (20) // Receive Next Counter Register
-#define PDC_TNPR        (24) // Transmit Next Pointer Register
-#define PDC_TNCR        (28) // Transmit Next Counter Register
-#define PDC_PTCR        (32) // PDC Transfer Control Register
-#define PDC_PTSR        (36) // PDC Transfer Status Register
-// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
-#define AT91C_PDC_RXTEN           (0x1 <<  0) // (PDC) Receiver Transfer Enable
-#define AT91C_PDC_RXTDIS          (0x1 <<  1) // (PDC) Receiver Transfer Disable
-#define AT91C_PDC_TXTEN           (0x1 <<  8) // (PDC) Transmitter Transfer Enable
-#define AT91C_PDC_TXTDIS          (0x1 <<  9) // (PDC) Transmitter Transfer Disable
-// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_PDC structure *** */
+#define PDC_RPR             ( 0 )        /* Receive Pointer Register */
+#define PDC_RCR             ( 4 )        /* Receive Counter Register */
+#define PDC_TPR             ( 8 )        /* Transmit Pointer Register */
+#define PDC_TCR             ( 12 )       /* Transmit Counter Register */
+#define PDC_RNPR            ( 16 )       /* Receive Next Pointer Register */
+#define PDC_RNCR            ( 20 )       /* Receive Next Counter Register */
+#define PDC_TNPR            ( 24 )       /* Transmit Next Pointer Register */
+#define PDC_TNCR            ( 28 )       /* Transmit Next Counter Register */
+#define PDC_PTCR            ( 32 )       /* PDC Transfer Control Register */
+#define PDC_PTSR            ( 36 )       /* PDC Transfer Status Register */
+/* -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */
+#define AT91C_PDC_RXTEN     ( 0x1 << 0 ) /* (PDC) Receiver Transfer Enable */
+#define AT91C_PDC_RXTDIS    ( 0x1 << 1 ) /* (PDC) Receiver Transfer Disable */
+#define AT91C_PDC_TXTEN     ( 0x1 << 8 ) /* (PDC) Transmitter Transfer Enable */
+#define AT91C_PDC_TXTDIS    ( 0x1 << 9 ) /* (PDC) Transmitter Transfer Disable */
+/* -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Debug Unit
-// *****************************************************************************
-// *** Register offset in AT91S_DBGU structure ***
-#define DBGU_CR         ( 0) // Control Register
-#define DBGU_MR         ( 4) // Mode Register
-#define DBGU_IER        ( 8) // Interrupt Enable Register
-#define DBGU_IDR        (12) // Interrupt Disable Register
-#define DBGU_IMR        (16) // Interrupt Mask Register
-#define DBGU_CSR        (20) // Channel Status Register
-#define DBGU_RHR        (24) // Receiver Holding Register
-#define DBGU_THR        (28) // Transmitter Holding Register
-#define DBGU_BRGR       (32) // Baud Rate Generator Register
-#define DBGU_CIDR       (64) // Chip ID Register
-#define DBGU_EXID       (68) // Chip ID Extension Register
-#define DBGU_FNTR       (72) // Force NTRST Register
-#define DBGU_RPR        (256) // Receive Pointer Register
-#define DBGU_RCR        (260) // Receive Counter Register
-#define DBGU_TPR        (264) // Transmit Pointer Register
-#define DBGU_TCR        (268) // Transmit Counter Register
-#define DBGU_RNPR       (272) // Receive Next Pointer Register
-#define DBGU_RNCR       (276) // Receive Next Counter Register
-#define DBGU_TNPR       (280) // Transmit Next Pointer Register
-#define DBGU_TNCR       (284) // Transmit Next Counter Register
-#define DBGU_PTCR       (288) // PDC Transfer Control Register
-#define DBGU_PTSR       (292) // PDC Transfer Status Register
-// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
-#define AT91C_US_RSTRX            (0x1 <<  2) // (DBGU) Reset Receiver
-#define AT91C_US_RSTTX            (0x1 <<  3) // (DBGU) Reset Transmitter
-#define AT91C_US_RXEN             (0x1 <<  4) // (DBGU) Receiver Enable
-#define AT91C_US_RXDIS            (0x1 <<  5) // (DBGU) Receiver Disable
-#define AT91C_US_TXEN             (0x1 <<  6) // (DBGU) Transmitter Enable
-#define AT91C_US_TXDIS            (0x1 <<  7) // (DBGU) Transmitter Disable
-#define AT91C_US_RSTSTA           (0x1 <<  8) // (DBGU) Reset Status Bits
-// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
-#define AT91C_US_PAR              (0x7 <<  9) // (DBGU) Parity type
-#define     AT91C_US_PAR_EVEN                 (0x0 <<  9) // (DBGU) Even Parity
-#define     AT91C_US_PAR_ODD                  (0x1 <<  9) // (DBGU) Odd Parity
-#define     AT91C_US_PAR_SPACE                (0x2 <<  9) // (DBGU) Parity forced to 0 (Space)
-#define     AT91C_US_PAR_MARK                 (0x3 <<  9) // (DBGU) Parity forced to 1 (Mark)
-#define     AT91C_US_PAR_NONE                 (0x4 <<  9) // (DBGU) No Parity
-#define     AT91C_US_PAR_MULTI_DROP           (0x6 <<  9) // (DBGU) Multi-drop mode
-#define AT91C_US_CHMODE           (0x3 << 14) // (DBGU) Channel Mode
-#define     AT91C_US_CHMODE_NORMAL               (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
-#define     AT91C_US_CHMODE_AUTO                 (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
-#define     AT91C_US_CHMODE_LOCAL                (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
-#define     AT91C_US_CHMODE_REMOTE               (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
-// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
-#define AT91C_US_RXRDY            (0x1 <<  0) // (DBGU) RXRDY Interrupt
-#define AT91C_US_TXRDY            (0x1 <<  1) // (DBGU) TXRDY Interrupt
-#define AT91C_US_ENDRX            (0x1 <<  3) // (DBGU) End of Receive Transfer Interrupt
-#define AT91C_US_ENDTX            (0x1 <<  4) // (DBGU) End of Transmit Interrupt
-#define AT91C_US_OVRE             (0x1 <<  5) // (DBGU) Overrun Interrupt
-#define AT91C_US_FRAME            (0x1 <<  6) // (DBGU) Framing Error Interrupt
-#define AT91C_US_PARE             (0x1 <<  7) // (DBGU) Parity Error Interrupt
-#define AT91C_US_TXEMPTY          (0x1 <<  9) // (DBGU) TXEMPTY Interrupt
-#define AT91C_US_TXBUFE           (0x1 << 11) // (DBGU) TXBUFE Interrupt
-#define AT91C_US_RXBUFF           (0x1 << 12) // (DBGU) RXBUFF Interrupt
-#define AT91C_US_COMM_TX          (0x1 << 30) // (DBGU) COMM_TX Interrupt
-#define AT91C_US_COMM_RX          (0x1 << 31) // (DBGU) COMM_RX Interrupt
-// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
-// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
-// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
-// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
-#define AT91C_US_FORCE_NTRST      (0x1 <<  0) // (DBGU) Force NTRST in JTAG
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Debug Unit */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_DBGU structure *** */
+#define DBGU_CR                        ( 0 )         /* Control Register */
+#define DBGU_MR                        ( 4 )         /* Mode Register */
+#define DBGU_IER                       ( 8 )         /* Interrupt Enable Register */
+#define DBGU_IDR                       ( 12 )        /* Interrupt Disable Register */
+#define DBGU_IMR                       ( 16 )        /* Interrupt Mask Register */
+#define DBGU_CSR                       ( 20 )        /* Channel Status Register */
+#define DBGU_RHR                       ( 24 )        /* Receiver Holding Register */
+#define DBGU_THR                       ( 28 )        /* Transmitter Holding Register */
+#define DBGU_BRGR                      ( 32 )        /* Baud Rate Generator Register */
+#define DBGU_CIDR                      ( 64 )        /* Chip ID Register */
+#define DBGU_EXID                      ( 68 )        /* Chip ID Extension Register */
+#define DBGU_FNTR                      ( 72 )        /* Force NTRST Register */
+#define DBGU_RPR                       ( 256 )       /* Receive Pointer Register */
+#define DBGU_RCR                       ( 260 )       /* Receive Counter Register */
+#define DBGU_TPR                       ( 264 )       /* Transmit Pointer Register */
+#define DBGU_TCR                       ( 268 )       /* Transmit Counter Register */
+#define DBGU_RNPR                      ( 272 )       /* Receive Next Pointer Register */
+#define DBGU_RNCR                      ( 276 )       /* Receive Next Counter Register */
+#define DBGU_TNPR                      ( 280 )       /* Transmit Next Pointer Register */
+#define DBGU_TNCR                      ( 284 )       /* Transmit Next Counter Register */
+#define DBGU_PTCR                      ( 288 )       /* PDC Transfer Control Register */
+#define DBGU_PTSR                      ( 292 )       /* PDC Transfer Status Register */
+/* -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- */
+#define AT91C_US_RSTRX                 ( 0x1 << 2 )  /* (DBGU) Reset Receiver */
+#define AT91C_US_RSTTX                 ( 0x1 << 3 )  /* (DBGU) Reset Transmitter */
+#define AT91C_US_RXEN                  ( 0x1 << 4 )  /* (DBGU) Receiver Enable */
+#define AT91C_US_RXDIS                 ( 0x1 << 5 )  /* (DBGU) Receiver Disable */
+#define AT91C_US_TXEN                  ( 0x1 << 6 )  /* (DBGU) Transmitter Enable */
+#define AT91C_US_TXDIS                 ( 0x1 << 7 )  /* (DBGU) Transmitter Disable */
+#define AT91C_US_RSTSTA                ( 0x1 << 8 )  /* (DBGU) Reset Status Bits */
+/* -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- */
+#define AT91C_US_PAR                   ( 0x7 << 9 )  /* (DBGU) Parity type */
+#define     AT91C_US_PAR_EVEN          ( 0x0 << 9 )  /* (DBGU) Even Parity */
+#define     AT91C_US_PAR_ODD           ( 0x1 << 9 )  /* (DBGU) Odd Parity */
+#define     AT91C_US_PAR_SPACE         ( 0x2 << 9 )  /* (DBGU) Parity forced to 0 (Space) */
+#define     AT91C_US_PAR_MARK          ( 0x3 << 9 )  /* (DBGU) Parity forced to 1 (Mark) */
+#define     AT91C_US_PAR_NONE          ( 0x4 << 9 )  /* (DBGU) No Parity */
+#define     AT91C_US_PAR_MULTI_DROP    ( 0x6 << 9 )  /* (DBGU) Multi-drop mode */
+#define AT91C_US_CHMODE                ( 0x3 << 14 ) /* (DBGU) Channel Mode */
+#define     AT91C_US_CHMODE_NORMAL     ( 0x0 << 14 ) /* (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. */
+#define     AT91C_US_CHMODE_AUTO       ( 0x1 << 14 ) /* (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. */
+#define     AT91C_US_CHMODE_LOCAL      ( 0x2 << 14 ) /* (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. */
+#define     AT91C_US_CHMODE_REMOTE     ( 0x3 << 14 ) /* (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. */
+/* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */
+#define AT91C_US_RXRDY                 ( 0x1 << 0 )  /* (DBGU) RXRDY Interrupt */
+#define AT91C_US_TXRDY                 ( 0x1 << 1 )  /* (DBGU) TXRDY Interrupt */
+#define AT91C_US_ENDRX                 ( 0x1 << 3 )  /* (DBGU) End of Receive Transfer Interrupt */
+#define AT91C_US_ENDTX                 ( 0x1 << 4 )  /* (DBGU) End of Transmit Interrupt */
+#define AT91C_US_OVRE                  ( 0x1 << 5 )  /* (DBGU) Overrun Interrupt */
+#define AT91C_US_FRAME                 ( 0x1 << 6 )  /* (DBGU) Framing Error Interrupt */
+#define AT91C_US_PARE                  ( 0x1 << 7 )  /* (DBGU) Parity Error Interrupt */
+#define AT91C_US_TXEMPTY               ( 0x1 << 9 )  /* (DBGU) TXEMPTY Interrupt */
+#define AT91C_US_TXBUFE                ( 0x1 << 11 ) /* (DBGU) TXBUFE Interrupt */
+#define AT91C_US_RXBUFF                ( 0x1 << 12 ) /* (DBGU) RXBUFF Interrupt */
+#define AT91C_US_COMM_TX               ( 0x1 << 30 ) /* (DBGU) COMM_TX Interrupt */
+#define AT91C_US_COMM_RX               ( 0x1 << 31 ) /* (DBGU) COMM_RX Interrupt */
+/* -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- */
+/* -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- */
+/* -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- */
+/* -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- */
+#define AT91C_US_FORCE_NTRST    ( 0x1 << 0 )  /* (DBGU) Force NTRST in JTAG */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
-// *****************************************************************************
-// *** Register offset in AT91S_PIO structure ***
-#define PIO_PER         ( 0) // PIO Enable Register
-#define PIO_PDR         ( 4) // PIO Disable Register
-#define PIO_PSR         ( 8) // PIO Status Register
-#define PIO_OER         (16) // Output Enable Register
-#define PIO_ODR         (20) // Output Disable Registerr
-#define PIO_OSR         (24) // Output Status Register
-#define PIO_IFER        (32) // Input Filter Enable Register
-#define PIO_IFDR        (36) // Input Filter Disable Register
-#define PIO_IFSR        (40) // Input Filter Status Register
-#define PIO_SODR        (48) // Set Output Data Register
-#define PIO_CODR        (52) // Clear Output Data Register
-#define PIO_ODSR        (56) // Output Data Status Register
-#define PIO_PDSR        (60) // Pin Data Status Register
-#define PIO_IER         (64) // Interrupt Enable Register
-#define PIO_IDR         (68) // Interrupt Disable Register
-#define PIO_IMR         (72) // Interrupt Mask Register
-#define PIO_ISR         (76) // Interrupt Status Register
-#define PIO_MDER        (80) // Multi-driver Enable Register
-#define PIO_MDDR        (84) // Multi-driver Disable Register
-#define PIO_MDSR        (88) // Multi-driver Status Register
-#define PIO_PPUDR       (96) // Pull-up Disable Register
-#define PIO_PPUER       (100) // Pull-up Enable Register
-#define PIO_PPUSR       (104) // Pull-up Status Register
-#define PIO_ASR         (112) // Select A Register
-#define PIO_BSR         (116) // Select B Register
-#define PIO_ABSR        (120) // AB Select Status Register
-#define PIO_OWER        (160) // Output Write Enable Register
-#define PIO_OWDR        (164) // Output Write Disable Register
-#define PIO_OWSR        (168) // Output Write Status Register
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Parallel Input Output Controller */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_PIO structure *** */
+#define PIO_PER      ( 0 )   /* PIO Enable Register */
+#define PIO_PDR      ( 4 )   /* PIO Disable Register */
+#define PIO_PSR      ( 8 )   /* PIO Status Register */
+#define PIO_OER      ( 16 )  /* Output Enable Register */
+#define PIO_ODR      ( 20 )  /* Output Disable Registerr */
+#define PIO_OSR      ( 24 )  /* Output Status Register */
+#define PIO_IFER     ( 32 )  /* Input Filter Enable Register */
+#define PIO_IFDR     ( 36 )  /* Input Filter Disable Register */
+#define PIO_IFSR     ( 40 )  /* Input Filter Status Register */
+#define PIO_SODR     ( 48 )  /* Set Output Data Register */
+#define PIO_CODR     ( 52 )  /* Clear Output Data Register */
+#define PIO_ODSR     ( 56 )  /* Output Data Status Register */
+#define PIO_PDSR     ( 60 )  /* Pin Data Status Register */
+#define PIO_IER      ( 64 )  /* Interrupt Enable Register */
+#define PIO_IDR      ( 68 )  /* Interrupt Disable Register */
+#define PIO_IMR      ( 72 )  /* Interrupt Mask Register */
+#define PIO_ISR      ( 76 )  /* Interrupt Status Register */
+#define PIO_MDER     ( 80 )  /* Multi-driver Enable Register */
+#define PIO_MDDR     ( 84 )  /* Multi-driver Disable Register */
+#define PIO_MDSR     ( 88 )  /* Multi-driver Status Register */
+#define PIO_PPUDR    ( 96 )  /* Pull-up Disable Register */
+#define PIO_PPUER    ( 100 ) /* Pull-up Enable Register */
+#define PIO_PPUSR    ( 104 ) /* Pull-up Status Register */
+#define PIO_ASR      ( 112 ) /* Select A Register */
+#define PIO_BSR      ( 116 ) /* Select B Register */
+#define PIO_ABSR     ( 120 ) /* AB Select Status Register */
+#define PIO_OWER     ( 160 ) /* Output Write Enable Register */
+#define PIO_OWDR     ( 164 ) /* Output Write Disable Register */
+#define PIO_OWSR     ( 168 ) /* Output Write Status Register */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Clock Generator Controler
-// *****************************************************************************
-// *** Register offset in AT91S_CKGR structure ***
-#define CKGR_MOR        ( 0) // Main Oscillator Register
-#define CKGR_MCFR       ( 4) // Main Clock  Frequency Register
-#define CKGR_PLLR       (12) // PLL Register
-// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
-#define AT91C_CKGR_MOSCEN         (0x1 <<  0) // (CKGR) Main Oscillator Enable
-#define AT91C_CKGR_OSCBYPASS      (0x1 <<  1) // (CKGR) Main Oscillator Bypass
-#define AT91C_CKGR_OSCOUNT        (0xFF <<  8) // (CKGR) Main Oscillator Start-up Time
-// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
-#define AT91C_CKGR_MAINF          (0xFFFF <<  0) // (CKGR) Main Clock Frequency
-#define AT91C_CKGR_MAINRDY        (0x1 << 16) // (CKGR) Main Clock Ready
-// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
-#define AT91C_CKGR_DIV            (0xFF <<  0) // (CKGR) Divider Selected
-#define     AT91C_CKGR_DIV_0                    (0x0) // (CKGR) Divider output is 0
-#define     AT91C_CKGR_DIV_BYPASS               (0x1) // (CKGR) Divider is bypassed
-#define AT91C_CKGR_PLLCOUNT       (0x3F <<  8) // (CKGR) PLL Counter
-#define AT91C_CKGR_OUT            (0x3 << 14) // (CKGR) PLL Output Frequency Range
-#define     AT91C_CKGR_OUT_0                    (0x0 << 14) // (CKGR) Please refer to the PLL datasheet
-#define     AT91C_CKGR_OUT_1                    (0x1 << 14) // (CKGR) Please refer to the PLL datasheet
-#define     AT91C_CKGR_OUT_2                    (0x2 << 14) // (CKGR) Please refer to the PLL datasheet
-#define     AT91C_CKGR_OUT_3                    (0x3 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_MUL            (0x7FF << 16) // (CKGR) PLL Multiplier
-#define AT91C_CKGR_USBDIV         (0x3 << 28) // (CKGR) Divider for USB Clocks
-#define     AT91C_CKGR_USBDIV_0                    (0x0 << 28) // (CKGR) Divider output is PLL clock output
-#define     AT91C_CKGR_USBDIV_1                    (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
-#define     AT91C_CKGR_USBDIV_2                    (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Clock Generator Controller */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_CKGR structure *** */
+#define CKGR_MOR                     ( 0 )           /* Main Oscillator Register */
+#define CKGR_MCFR                    ( 4 )           /* Main Clock  Frequency Register */
+#define CKGR_PLLR                    ( 12 )          /* PLL Register */
+/* -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */
+#define AT91C_CKGR_MOSCEN            ( 0x1 << 0 )    /* (CKGR) Main Oscillator Enable */
+#define AT91C_CKGR_OSCBYPASS         ( 0x1 << 1 )    /* (CKGR) Main Oscillator Bypass */
+#define AT91C_CKGR_OSCOUNT           ( 0xFF << 8 )   /* (CKGR) Main Oscillator Start-up Time */
+/* -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- */
+#define AT91C_CKGR_MAINF             ( 0xFFFF << 0 ) /* (CKGR) Main Clock Frequency */
+#define AT91C_CKGR_MAINRDY           ( 0x1 << 16 )   /* (CKGR) Main Clock Ready */
+/* -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- */
+#define AT91C_CKGR_DIV               ( 0xFF << 0 )   /* (CKGR) Divider Selected */
+#define     AT91C_CKGR_DIV_0         ( 0x0 )         /* (CKGR) Divider output is 0 */
+#define     AT91C_CKGR_DIV_BYPASS    ( 0x1 )         /* (CKGR) Divider is bypassed */
+#define AT91C_CKGR_PLLCOUNT          ( 0x3F << 8 )   /* (CKGR) PLL Counter */
+#define AT91C_CKGR_OUT               ( 0x3 << 14 )   /* (CKGR) PLL Output Frequency Range */
+#define     AT91C_CKGR_OUT_0         ( 0x0 << 14 )   /* (CKGR) Please refer to the PLL datasheet */
+#define     AT91C_CKGR_OUT_1         ( 0x1 << 14 )   /* (CKGR) Please refer to the PLL datasheet */
+#define     AT91C_CKGR_OUT_2         ( 0x2 << 14 )   /* (CKGR) Please refer to the PLL datasheet */
+#define     AT91C_CKGR_OUT_3         ( 0x3 << 14 )   /* (CKGR) Please refer to the PLL datasheet */
+#define AT91C_CKGR_MUL               ( 0x7FF << 16 ) /* (CKGR) PLL Multiplier */
+#define AT91C_CKGR_USBDIV            ( 0x3 << 28 )   /* (CKGR) Divider for USB Clocks */
+#define     AT91C_CKGR_USBDIV_0      ( 0x0 << 28 )   /* (CKGR) Divider output is PLL clock output */
+#define     AT91C_CKGR_USBDIV_1      ( 0x1 << 28 )   /* (CKGR) Divider output is PLL clock output divided by 2 */
+#define     AT91C_CKGR_USBDIV_2      ( 0x2 << 28 )   /* (CKGR) Divider output is PLL clock output divided by 4 */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Power Management Controler
-// *****************************************************************************
-// *** Register offset in AT91S_PMC structure ***
-#define PMC_SCER        ( 0) // System Clock Enable Register
-#define PMC_SCDR        ( 4) // System Clock Disable Register
-#define PMC_SCSR        ( 8) // System Clock Status Register
-#define PMC_PCER        (16) // Peripheral Clock Enable Register
-#define PMC_PCDR        (20) // Peripheral Clock Disable Register
-#define PMC_PCSR        (24) // Peripheral Clock Status Register
-#define PMC_MOR         (32) // Main Oscillator Register
-#define PMC_MCFR        (36) // Main Clock  Frequency Register
-#define PMC_PLLR        (44) // PLL Register
-#define PMC_MCKR        (48) // Master Clock Register
-#define PMC_PCKR        (64) // Programmable Clock Register
-#define PMC_IER         (96) // Interrupt Enable Register
-#define PMC_IDR         (100) // Interrupt Disable Register
-#define PMC_SR          (104) // Status Register
-#define PMC_IMR         (108) // Interrupt Mask Register
-// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
-#define AT91C_PMC_PCK             (0x1 <<  0) // (PMC) Processor Clock
-#define AT91C_PMC_UDP             (0x1 <<  7) // (PMC) USB Device Port Clock
-#define AT91C_PMC_PCK0            (0x1 <<  8) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK1            (0x1 <<  9) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK2            (0x1 << 10) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK3            (0x1 << 11) // (PMC) Programmable Clock Output
-// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
-// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
-// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
-// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
-// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
-// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
-#define AT91C_PMC_CSS             (0x3 <<  0) // (PMC) Programmable Clock Selection
-#define     AT91C_PMC_CSS_SLOW_CLK             (0x0) // (PMC) Slow Clock is selected
-#define     AT91C_PMC_CSS_MAIN_CLK             (0x1) // (PMC) Main Clock is selected
-#define     AT91C_PMC_CSS_PLL_CLK              (0x3) // (PMC) Clock from PLL is selected
-#define AT91C_PMC_PRES            (0x7 <<  2) // (PMC) Programmable Clock Prescaler
-#define     AT91C_PMC_PRES_CLK                  (0x0 <<  2) // (PMC) Selected clock
-#define     AT91C_PMC_PRES_CLK_2                (0x1 <<  2) // (PMC) Selected clock divided by 2
-#define     AT91C_PMC_PRES_CLK_4                (0x2 <<  2) // (PMC) Selected clock divided by 4
-#define     AT91C_PMC_PRES_CLK_8                (0x3 <<  2) // (PMC) Selected clock divided by 8
-#define     AT91C_PMC_PRES_CLK_16               (0x4 <<  2) // (PMC) Selected clock divided by 16
-#define     AT91C_PMC_PRES_CLK_32               (0x5 <<  2) // (PMC) Selected clock divided by 32
-#define     AT91C_PMC_PRES_CLK_64               (0x6 <<  2) // (PMC) Selected clock divided by 64
-// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
-// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
-#define AT91C_PMC_MOSCS           (0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask
-#define AT91C_PMC_LOCK            (0x1 <<  2) // (PMC) PLL Status/Enable/Disable/Mask
-#define AT91C_PMC_MCKRDY          (0x1 <<  3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK0RDY         (0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK1RDY         (0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK2RDY         (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK3RDY         (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
-// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
-// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
-// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Power Management Controller */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_PMC structure *** */
+#define PMC_SCER          ( 0 )         /* System Clock Enable Register */
+#define PMC_SCDR          ( 4 )         /* System Clock Disable Register */
+#define PMC_SCSR          ( 8 )         /* System Clock Status Register */
+#define PMC_PCER          ( 16 )        /* Peripheral Clock Enable Register */
+#define PMC_PCDR          ( 20 )        /* Peripheral Clock Disable Register */
+#define PMC_PCSR          ( 24 )        /* Peripheral Clock Status Register */
+#define PMC_MOR           ( 32 )        /* Main Oscillator Register */
+#define PMC_MCFR          ( 36 )        /* Main Clock  Frequency Register */
+#define PMC_PLLR          ( 44 )        /* PLL Register */
+#define PMC_MCKR          ( 48 )        /* Master Clock Register */
+#define PMC_PCKR          ( 64 )        /* Programmable Clock Register */
+#define PMC_IER           ( 96 )        /* Interrupt Enable Register */
+#define PMC_IDR           ( 100 )       /* Interrupt Disable Register */
+#define PMC_SR            ( 104 )       /* Status Register */
+#define PMC_IMR           ( 108 )       /* Interrupt Mask Register */
+/* -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- */
+#define AT91C_PMC_PCK     ( 0x1 << 0 )  /* (PMC) Processor Clock */
+#define AT91C_PMC_UDP     ( 0x1 << 7 )  /* (PMC) USB Device Port Clock */
+#define AT91C_PMC_PCK0    ( 0x1 << 8 )  /* (PMC) Programmable Clock Output */
+#define AT91C_PMC_PCK1    ( 0x1 << 9 )  /* (PMC) Programmable Clock Output */
+#define AT91C_PMC_PCK2    ( 0x1 << 10 ) /* (PMC) Programmable Clock Output */
+#define AT91C_PMC_PCK3    ( 0x1 << 11 ) /* (PMC) Programmable Clock Output */
+/* -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- */
+/* -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- */
+/* -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- */
+/* -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- */
+/* -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- */
+/* -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- */
+#define AT91C_PMC_CSS                 ( 0x3 << 0 ) /* (PMC) Programmable Clock Selection */
+#define     AT91C_PMC_CSS_SLOW_CLK    ( 0x0 )      /* (PMC) Slow Clock is selected */
+#define     AT91C_PMC_CSS_MAIN_CLK    ( 0x1 )      /* (PMC) Main Clock is selected */
+#define     AT91C_PMC_CSS_PLL_CLK     ( 0x3 )      /* (PMC) Clock from PLL is selected */
+#define AT91C_PMC_PRES                ( 0x7 << 2 ) /* (PMC) Programmable Clock Prescaler */
+#define     AT91C_PMC_PRES_CLK        ( 0x0 << 2 ) /* (PMC) Selected clock */
+#define     AT91C_PMC_PRES_CLK_2      ( 0x1 << 2 ) /* (PMC) Selected clock divided by 2 */
+#define     AT91C_PMC_PRES_CLK_4      ( 0x2 << 2 ) /* (PMC) Selected clock divided by 4 */
+#define     AT91C_PMC_PRES_CLK_8      ( 0x3 << 2 ) /* (PMC) Selected clock divided by 8 */
+#define     AT91C_PMC_PRES_CLK_16     ( 0x4 << 2 ) /* (PMC) Selected clock divided by 16 */
+#define     AT91C_PMC_PRES_CLK_32     ( 0x5 << 2 ) /* (PMC) Selected clock divided by 32 */
+#define     AT91C_PMC_PRES_CLK_64     ( 0x6 << 2 ) /* (PMC) Selected clock divided by 64 */
+/* -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- */
+/* -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- */
+#define AT91C_PMC_MOSCS               ( 0x1 << 0 )  /* (PMC) MOSC Status/Enable/Disable/Mask */
+#define AT91C_PMC_LOCK                ( 0x1 << 2 )  /* (PMC) PLL Status/Enable/Disable/Mask */
+#define AT91C_PMC_MCKRDY              ( 0x1 << 3 )  /* (PMC) MCK_RDY Status/Enable/Disable/Mask */
+#define AT91C_PMC_PCK0RDY             ( 0x1 << 8 )  /* (PMC) PCK0_RDY Status/Enable/Disable/Mask */
+#define AT91C_PMC_PCK1RDY             ( 0x1 << 9 )  /* (PMC) PCK1_RDY Status/Enable/Disable/Mask */
+#define AT91C_PMC_PCK2RDY             ( 0x1 << 10 ) /* (PMC) PCK2_RDY Status/Enable/Disable/Mask */
+#define AT91C_PMC_PCK3RDY             ( 0x1 << 11 ) /* (PMC) PCK3_RDY Status/Enable/Disable/Mask */
+/* -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- */
+/* -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- */
+/* -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Reset Controller Interface
-// *****************************************************************************
-// *** Register offset in AT91S_RSTC structure ***
-#define RSTC_RCR        ( 0) // Reset Control Register
-#define RSTC_RSR        ( 4) // Reset Status Register
-#define RSTC_RMR        ( 8) // Reset Mode Register
-// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
-#define AT91C_RSTC_PROCRST        (0x1 <<  0) // (RSTC) Processor Reset
-#define AT91C_RSTC_PERRST         (0x1 <<  2) // (RSTC) Peripheral Reset
-#define AT91C_RSTC_EXTRST         (0x1 <<  3) // (RSTC) External Reset
-#define AT91C_RSTC_KEY            (0xFF << 24) // (RSTC) Password
-// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
-#define AT91C_RSTC_URSTS          (0x1 <<  0) // (RSTC) User Reset Status
-#define AT91C_RSTC_BODSTS         (0x1 <<  1) // (RSTC) Brownout Detection Status
-#define AT91C_RSTC_RSTTYP         (0x7 <<  8) // (RSTC) Reset Type
-#define     AT91C_RSTC_RSTTYP_POWERUP              (0x0 <<  8) // (RSTC) Power-up Reset. VDDCORE rising.
-#define     AT91C_RSTC_RSTTYP_WAKEUP               (0x1 <<  8) // (RSTC) WakeUp Reset. VDDCORE rising.
-#define     AT91C_RSTC_RSTTYP_WATCHDOG             (0x2 <<  8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
-#define     AT91C_RSTC_RSTTYP_SOFTWARE             (0x3 <<  8) // (RSTC) Software Reset. Processor reset required by the software.
-#define     AT91C_RSTC_RSTTYP_USER                 (0x4 <<  8) // (RSTC) User Reset. NRST pin detected low.
-#define     AT91C_RSTC_RSTTYP_BROWNOUT             (0x5 <<  8) // (RSTC) Brownout Reset occured.
-#define AT91C_RSTC_NRSTL          (0x1 << 16) // (RSTC) NRST pin level
-#define AT91C_RSTC_SRCMP          (0x1 << 17) // (RSTC) Software Reset Command in Progress.
-// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
-#define AT91C_RSTC_URSTEN         (0x1 <<  0) // (RSTC) User Reset Enable
-#define AT91C_RSTC_URSTIEN        (0x1 <<  4) // (RSTC) User Reset Interrupt Enable
-#define AT91C_RSTC_ERSTL          (0xF <<  8) // (RSTC) User Reset Enable
-#define AT91C_RSTC_BODIEN         (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Reset Controller Interface */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_RSTC structure *** */
+#define RSTC_RCR                          ( 0 )          /* Reset Control Register */
+#define RSTC_RSR                          ( 4 )          /* Reset Status Register */
+#define RSTC_RMR                          ( 8 )          /* Reset Mode Register */
+/* -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- */
+#define AT91C_RSTC_PROCRST                ( 0x1 << 0 )   /* (RSTC) Processor Reset */
+#define AT91C_RSTC_PERRST                 ( 0x1 << 2 )   /* (RSTC) Peripheral Reset */
+#define AT91C_RSTC_EXTRST                 ( 0x1 << 3 )   /* (RSTC) External Reset */
+#define AT91C_RSTC_KEY                    ( 0xFF << 24 ) /* (RSTC) Password */
+/* -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- */
+#define AT91C_RSTC_URSTS                  ( 0x1 << 0 )   /* (RSTC) User Reset Status */
+#define AT91C_RSTC_BODSTS                 ( 0x1 << 1 )   /* (RSTC) Brownout Detection Status */
+#define AT91C_RSTC_RSTTYP                 ( 0x7 << 8 )   /* (RSTC) Reset Type */
+#define     AT91C_RSTC_RSTTYP_POWERUP     ( 0x0 << 8 )   /* (RSTC) Power-up Reset. VDDCORE rising. */
+#define     AT91C_RSTC_RSTTYP_WAKEUP      ( 0x1 << 8 )   /* (RSTC) WakeUp Reset. VDDCORE rising. */
+#define     AT91C_RSTC_RSTTYP_WATCHDOG    ( 0x2 << 8 )   /* (RSTC) Watchdog Reset. Watchdog overflow occurred. */
+#define     AT91C_RSTC_RSTTYP_SOFTWARE    ( 0x3 << 8 )   /* (RSTC) Software Reset. Processor reset required by the software. */
+#define     AT91C_RSTC_RSTTYP_USER        ( 0x4 << 8 )   /* (RSTC) User Reset. NRST pin detected low. */
+#define     AT91C_RSTC_RSTTYP_BROWNOUT    ( 0x5 << 8 )   /* (RSTC) Brownout Reset occurred. */
+#define AT91C_RSTC_NRSTL                  ( 0x1 << 16 )  /* (RSTC) NRST pin level */
+#define AT91C_RSTC_SRCMP                  ( 0x1 << 17 )  /* (RSTC) Software Reset Command in Progress. */
+/* -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- */
+#define AT91C_RSTC_URSTEN                 ( 0x1 << 0 )   /* (RSTC) User Reset Enable */
+#define AT91C_RSTC_URSTIEN                ( 0x1 << 4 )   /* (RSTC) User Reset Interrupt Enable */
+#define AT91C_RSTC_ERSTL                  ( 0xF << 8 )   /* (RSTC) User Reset Enable */
+#define AT91C_RSTC_BODIEN                 ( 0x1 << 16 )  /* (RSTC) Brownout Detection Interrupt Enable */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
-// *****************************************************************************
-// *** Register offset in AT91S_RTTC structure ***
-#define RTTC_RTMR       ( 0) // Real-time Mode Register
-#define RTTC_RTAR       ( 4) // Real-time Alarm Register
-#define RTTC_RTVR       ( 8) // Real-time Value Register
-#define RTTC_RTSR       (12) // Real-time Status Register
-// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
-#define AT91C_RTTC_RTPRES         (0xFFFF <<  0) // (RTTC) Real-time Timer Prescaler Value
-#define AT91C_RTTC_ALMIEN         (0x1 << 16) // (RTTC) Alarm Interrupt Enable
-#define AT91C_RTTC_RTTINCIEN      (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
-#define AT91C_RTTC_RTTRST         (0x1 << 18) // (RTTC) Real Time Timer Restart
-// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
-#define AT91C_RTTC_ALMV           (0x0 <<  0) // (RTTC) Alarm Value
-// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
-#define AT91C_RTTC_CRTV           (0x0 <<  0) // (RTTC) Current Real-time Value
-// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
-#define AT91C_RTTC_ALMS           (0x1 <<  0) // (RTTC) Real-time Alarm Status
-#define AT91C_RTTC_RTTINC         (0x1 <<  1) // (RTTC) Real-time Timer Increment
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_RTTC structure *** */
+#define RTTC_RTMR               ( 0 )           /* Real-time Mode Register */
+#define RTTC_RTAR               ( 4 )           /* Real-time Alarm Register */
+#define RTTC_RTVR               ( 8 )           /* Real-time Value Register */
+#define RTTC_RTSR               ( 12 )          /* Real-time Status Register */
+/* -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- */
+#define AT91C_RTTC_RTPRES       ( 0xFFFF << 0 ) /* (RTTC) Real-time Timer Prescaler Value */
+#define AT91C_RTTC_ALMIEN       ( 0x1 << 16 )   /* (RTTC) Alarm Interrupt Enable */
+#define AT91C_RTTC_RTTINCIEN    ( 0x1 << 17 )   /* (RTTC) Real Time Timer Increment Interrupt Enable */
+#define AT91C_RTTC_RTTRST       ( 0x1 << 18 )   /* (RTTC) Real Time Timer Restart */
+/* -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- */
+#define AT91C_RTTC_ALMV         ( 0x0 << 0 )    /* (RTTC) Alarm Value */
+/* -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- */
+#define AT91C_RTTC_CRTV         ( 0x0 << 0 )    /* (RTTC) Current Real-time Value */
+/* -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- */
+#define AT91C_RTTC_ALMS         ( 0x1 << 0 )    /* (RTTC) Real-time Alarm Status */
+#define AT91C_RTTC_RTTINC       ( 0x1 << 1 )    /* (RTTC) Real-time Timer Increment */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
-// *****************************************************************************
-// *** Register offset in AT91S_PITC structure ***
-#define PITC_PIMR       ( 0) // Period Interval Mode Register
-#define PITC_PISR       ( 4) // Period Interval Status Register
-#define PITC_PIVR       ( 8) // Period Interval Value Register
-#define PITC_PIIR       (12) // Period Interval Image Register
-// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
-#define AT91C_PITC_PIV            (0xFFFFF <<  0) // (PITC) Periodic Interval Value
-#define AT91C_PITC_PITEN          (0x1 << 24) // (PITC) Periodic Interval Timer Enabled
-#define AT91C_PITC_PITIEN         (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
-// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
-#define AT91C_PITC_PITS           (0x1 <<  0) // (PITC) Periodic Interval Timer Status
-// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
-#define AT91C_PITC_CPIV           (0xFFFFF <<  0) // (PITC) Current Periodic Interval Value
-#define AT91C_PITC_PICNT          (0xFFF << 20) // (PITC) Periodic Interval Counter
-// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_PITC structure *** */
+#define PITC_PIMR            ( 0 )            /* Period Interval Mode Register */
+#define PITC_PISR            ( 4 )            /* Period Interval Status Register */
+#define PITC_PIVR            ( 8 )            /* Period Interval Value Register */
+#define PITC_PIIR            ( 12 )           /* Period Interval Image Register */
+/* -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- */
+#define AT91C_PITC_PIV       ( 0xFFFFF << 0 ) /* (PITC) Periodic Interval Value */
+#define AT91C_PITC_PITEN     ( 0x1 << 24 )    /* (PITC) Periodic Interval Timer Enabled */
+#define AT91C_PITC_PITIEN    ( 0x1 << 25 )    /* (PITC) Periodic Interval Timer Interrupt Enable */
+/* -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- */
+#define AT91C_PITC_PITS      ( 0x1 << 0 )     /* (PITC) Periodic Interval Timer Status */
+/* -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- */
+#define AT91C_PITC_CPIV      ( 0xFFFFF << 0 ) /* (PITC) Current Periodic Interval Value */
+#define AT91C_PITC_PICNT     ( 0xFFF << 20 )  /* (PITC) Periodic Interval Counter */
+/* -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
-// *****************************************************************************
-// *** Register offset in AT91S_WDTC structure ***
-#define WDTC_WDCR       ( 0) // Watchdog Control Register
-#define WDTC_WDMR       ( 4) // Watchdog Mode Register
-#define WDTC_WDSR       ( 8) // Watchdog Status Register
-// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
-#define AT91C_WDTC_WDRSTT         (0x1 <<  0) // (WDTC) Watchdog Restart
-#define AT91C_WDTC_KEY            (0xFF << 24) // (WDTC) Watchdog KEY Password
-// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
-#define AT91C_WDTC_WDV            (0xFFF <<  0) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDFIEN         (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
-#define AT91C_WDTC_WDRSTEN        (0x1 << 13) // (WDTC) Watchdog Reset Enable
-#define AT91C_WDTC_WDRPROC        (0x1 << 14) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDDIS          (0x1 << 15) // (WDTC) Watchdog Disable
-#define AT91C_WDTC_WDD            (0xFFF << 16) // (WDTC) Watchdog Delta Value
-#define AT91C_WDTC_WDDBGHLT       (0x1 << 28) // (WDTC) Watchdog Debug Halt
-#define AT91C_WDTC_WDIDLEHLT      (0x1 << 29) // (WDTC) Watchdog Idle Halt
-// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
-#define AT91C_WDTC_WDUNF          (0x1 <<  0) // (WDTC) Watchdog Underflow
-#define AT91C_WDTC_WDERR          (0x1 <<  1) // (WDTC) Watchdog Error
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_WDTC structure *** */
+#define WDTC_WDCR               ( 0 )           /* Watchdog Control Register */
+#define WDTC_WDMR               ( 4 )           /* Watchdog Mode Register */
+#define WDTC_WDSR               ( 8 )           /* Watchdog Status Register */
+/* -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- */
+#define AT91C_WDTC_WDRSTT       ( 0x1 << 0 )    /* (WDTC) Watchdog Restart */
+#define AT91C_WDTC_KEY          ( 0xFF << 24 )  /* (WDTC) Watchdog KEY Password */
+/* -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- */
+#define AT91C_WDTC_WDV          ( 0xFFF << 0 )  /* (WDTC) Watchdog Timer Restart */
+#define AT91C_WDTC_WDFIEN       ( 0x1 << 12 )   /* (WDTC) Watchdog Fault Interrupt Enable */
+#define AT91C_WDTC_WDRSTEN      ( 0x1 << 13 )   /* (WDTC) Watchdog Reset Enable */
+#define AT91C_WDTC_WDRPROC      ( 0x1 << 14 )   /* (WDTC) Watchdog Timer Restart */
+#define AT91C_WDTC_WDDIS        ( 0x1 << 15 )   /* (WDTC) Watchdog Disable */
+#define AT91C_WDTC_WDD          ( 0xFFF << 16 ) /* (WDTC) Watchdog Delta Value */
+#define AT91C_WDTC_WDDBGHLT     ( 0x1 << 28 )   /* (WDTC) Watchdog Debug Halt */
+#define AT91C_WDTC_WDIDLEHLT    ( 0x1 << 29 )   /* (WDTC) Watchdog Idle Halt */
+/* -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- */
+#define AT91C_WDTC_WDUNF        ( 0x1 << 0 )    /* (WDTC) Watchdog Underflow */
+#define AT91C_WDTC_WDERR        ( 0x1 << 1 )    /* (WDTC) Watchdog Error */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Voltage Regulator Mode Controller Interface
-// *****************************************************************************
-// *** Register offset in AT91S_VREG structure ***
-#define VREG_MR         ( 0) // Voltage Regulator Mode Register
-// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register --------
-#define AT91C_VREG_PSTDBY         (0x1 <<  0) // (VREG) Voltage Regulator Power Standby Mode
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Voltage Regulator Mode Controller Interface */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_VREG structure *** */
+#define VREG_MR              ( 0 )        /* Voltage Regulator Mode Register */
+/* -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- */
+#define AT91C_VREG_PSTDBY    ( 0x1 << 0 ) /* (VREG) Voltage Regulator Power Standby Mode */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Memory Controller Interface
-// *****************************************************************************
-// *** Register offset in AT91S_MC structure ***
-#define MC_RCR          ( 0) // MC Remap Control Register
-#define MC_ASR          ( 4) // MC Abort Status Register
-#define MC_AASR         ( 8) // MC Abort Address Status Register
-#define MC_FMR          (96) // MC Flash Mode Register
-#define MC_FCR          (100) // MC Flash Command Register
-#define MC_FSR          (104) // MC Flash Status Register
-// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
-#define AT91C_MC_RCB              (0x1 <<  0) // (MC) Remap Command Bit
-// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
-#define AT91C_MC_UNDADD           (0x1 <<  0) // (MC) Undefined Addess Abort Status
-#define AT91C_MC_MISADD           (0x1 <<  1) // (MC) Misaligned Addess Abort Status
-#define AT91C_MC_ABTSZ            (0x3 <<  8) // (MC) Abort Size Status
-#define     AT91C_MC_ABTSZ_BYTE                 (0x0 <<  8) // (MC) Byte
-#define     AT91C_MC_ABTSZ_HWORD                (0x1 <<  8) // (MC) Half-word
-#define     AT91C_MC_ABTSZ_WORD                 (0x2 <<  8) // (MC) Word
-#define AT91C_MC_ABTTYP           (0x3 << 10) // (MC) Abort Type Status
-#define     AT91C_MC_ABTTYP_DATAR                (0x0 << 10) // (MC) Data Read
-#define     AT91C_MC_ABTTYP_DATAW                (0x1 << 10) // (MC) Data Write
-#define     AT91C_MC_ABTTYP_FETCH                (0x2 << 10) // (MC) Code Fetch
-#define AT91C_MC_MST0             (0x1 << 16) // (MC) Master 0 Abort Source
-#define AT91C_MC_MST1             (0x1 << 17) // (MC) Master 1 Abort Source
-#define AT91C_MC_SVMST0           (0x1 << 24) // (MC) Saved Master 0 Abort Source
-#define AT91C_MC_SVMST1           (0x1 << 25) // (MC) Saved Master 1 Abort Source
-// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
-#define AT91C_MC_FRDY             (0x1 <<  0) // (MC) Flash Ready
-#define AT91C_MC_LOCKE            (0x1 <<  2) // (MC) Lock Error
-#define AT91C_MC_PROGE            (0x1 <<  3) // (MC) Programming Error
-#define AT91C_MC_NEBP             (0x1 <<  7) // (MC) No Erase Before Programming
-#define AT91C_MC_FWS              (0x3 <<  8) // (MC) Flash Wait State
-#define     AT91C_MC_FWS_0FWS                 (0x0 <<  8) // (MC) 1 cycle for Read, 2 for Write operations
-#define     AT91C_MC_FWS_1FWS                 (0x1 <<  8) // (MC) 2 cycles for Read, 3 for Write operations
-#define     AT91C_MC_FWS_2FWS                 (0x2 <<  8) // (MC) 3 cycles for Read, 4 for Write operations
-#define     AT91C_MC_FWS_3FWS                 (0x3 <<  8) // (MC) 4 cycles for Read, 4 for Write operations
-#define AT91C_MC_FMCN             (0xFF << 16) // (MC) Flash Microsecond Cycle Number
-// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
-#define AT91C_MC_FCMD             (0xF <<  0) // (MC) Flash Command
-#define     AT91C_MC_FCMD_START_PROG           (0x1) // (MC) Starts the programming of th epage specified by PAGEN.
-#define     AT91C_MC_FCMD_LOCK                 (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define     AT91C_MC_FCMD_PROG_AND_LOCK        (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
-#define     AT91C_MC_FCMD_UNLOCK               (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define     AT91C_MC_FCMD_ERASE_ALL            (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
-#define     AT91C_MC_FCMD_SET_GP_NVM           (0xB) // (MC) Set General Purpose NVM bits.
-#define     AT91C_MC_FCMD_CLR_GP_NVM           (0xD) // (MC) Clear General Purpose NVM bits.
-#define     AT91C_MC_FCMD_SET_SECURITY         (0xF) // (MC) Set Security Bit.
-#define AT91C_MC_PAGEN            (0x3FF <<  8) // (MC) Page Number
-#define AT91C_MC_KEY              (0xFF << 24) // (MC) Writing Protect Key
-// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register --------
-#define AT91C_MC_SECURITY         (0x1 <<  4) // (MC) Security Bit Status
-#define AT91C_MC_GPNVM0           (0x1 <<  8) // (MC) Sector 0 Lock Status
-#define AT91C_MC_GPNVM1           (0x1 <<  9) // (MC) Sector 1 Lock Status
-#define AT91C_MC_GPNVM2           (0x1 << 10) // (MC) Sector 2 Lock Status
-#define AT91C_MC_GPNVM3           (0x1 << 11) // (MC) Sector 3 Lock Status
-#define AT91C_MC_GPNVM4           (0x1 << 12) // (MC) Sector 4 Lock Status
-#define AT91C_MC_GPNVM5           (0x1 << 13) // (MC) Sector 5 Lock Status
-#define AT91C_MC_GPNVM6           (0x1 << 14) // (MC) Sector 6 Lock Status
-#define AT91C_MC_GPNVM7           (0x1 << 15) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS0           (0x1 << 16) // (MC) Sector 0 Lock Status
-#define AT91C_MC_LOCKS1           (0x1 << 17) // (MC) Sector 1 Lock Status
-#define AT91C_MC_LOCKS2           (0x1 << 18) // (MC) Sector 2 Lock Status
-#define AT91C_MC_LOCKS3           (0x1 << 19) // (MC) Sector 3 Lock Status
-#define AT91C_MC_LOCKS4           (0x1 << 20) // (MC) Sector 4 Lock Status
-#define AT91C_MC_LOCKS5           (0x1 << 21) // (MC) Sector 5 Lock Status
-#define AT91C_MC_LOCKS6           (0x1 << 22) // (MC) Sector 6 Lock Status
-#define AT91C_MC_LOCKS7           (0x1 << 23) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS8           (0x1 << 24) // (MC) Sector 8 Lock Status
-#define AT91C_MC_LOCKS9           (0x1 << 25) // (MC) Sector 9 Lock Status
-#define AT91C_MC_LOCKS10          (0x1 << 26) // (MC) Sector 10 Lock Status
-#define AT91C_MC_LOCKS11          (0x1 << 27) // (MC) Sector 11 Lock Status
-#define AT91C_MC_LOCKS12          (0x1 << 28) // (MC) Sector 12 Lock Status
-#define AT91C_MC_LOCKS13          (0x1 << 29) // (MC) Sector 13 Lock Status
-#define AT91C_MC_LOCKS14          (0x1 << 30) // (MC) Sector 14 Lock Status
-#define AT91C_MC_LOCKS15          (0x1 << 31) // (MC) Sector 15 Lock Status
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Memory Controller Interface */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_MC structure *** */
+#define MC_RCR                             ( 0 )          /* MC Remap Control Register */
+#define MC_ASR                             ( 4 )          /* MC Abort Status Register */
+#define MC_AASR                            ( 8 )          /* MC Abort Address Status Register */
+#define MC_FMR                             ( 96 )         /* MC Flash Mode Register */
+#define MC_FCR                             ( 100 )        /* MC Flash Command Register */
+#define MC_FSR                             ( 104 )        /* MC Flash Status Register */
+/* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */
+#define AT91C_MC_RCB                       ( 0x1 << 0 )   /* (MC) Remap Command Bit */
+/* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */
+#define AT91C_MC_UNDADD                    ( 0x1 << 0 )   /* (MC) Undefined Addess Abort Status */
+#define AT91C_MC_MISADD                    ( 0x1 << 1 )   /* (MC) Misaligned Addess Abort Status */
+#define AT91C_MC_ABTSZ                     ( 0x3 << 8 )   /* (MC) Abort Size Status */
+#define     AT91C_MC_ABTSZ_BYTE            ( 0x0 << 8 )   /* (MC) Byte */
+#define     AT91C_MC_ABTSZ_HWORD           ( 0x1 << 8 )   /* (MC) Half-word */
+#define     AT91C_MC_ABTSZ_WORD            ( 0x2 << 8 )   /* (MC) Word */
+#define AT91C_MC_ABTTYP                    ( 0x3 << 10 )  /* (MC) Abort Type Status */
+#define     AT91C_MC_ABTTYP_DATAR          ( 0x0 << 10 )  /* (MC) Data Read */
+#define     AT91C_MC_ABTTYP_DATAW          ( 0x1 << 10 )  /* (MC) Data Write */
+#define     AT91C_MC_ABTTYP_FETCH          ( 0x2 << 10 )  /* (MC) Code Fetch */
+#define AT91C_MC_MST0                      ( 0x1 << 16 )  /* (MC) Master 0 Abort Source */
+#define AT91C_MC_MST1                      ( 0x1 << 17 )  /* (MC) Master 1 Abort Source */
+#define AT91C_MC_SVMST0                    ( 0x1 << 24 )  /* (MC) Saved Master 0 Abort Source */
+#define AT91C_MC_SVMST1                    ( 0x1 << 25 )  /* (MC) Saved Master 1 Abort Source */
+/* -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- */
+#define AT91C_MC_FRDY                      ( 0x1 << 0 )   /* (MC) Flash Ready */
+#define AT91C_MC_LOCKE                     ( 0x1 << 2 )   /* (MC) Lock Error */
+#define AT91C_MC_PROGE                     ( 0x1 << 3 )   /* (MC) Programming Error */
+#define AT91C_MC_NEBP                      ( 0x1 << 7 )   /* (MC) No Erase Before Programming */
+#define AT91C_MC_FWS                       ( 0x3 << 8 )   /* (MC) Flash Wait State */
+#define     AT91C_MC_FWS_0FWS              ( 0x0 << 8 )   /* (MC) 1 cycle for Read, 2 for Write operations */
+#define     AT91C_MC_FWS_1FWS              ( 0x1 << 8 )   /* (MC) 2 cycles for Read, 3 for Write operations */
+#define     AT91C_MC_FWS_2FWS              ( 0x2 << 8 )   /* (MC) 3 cycles for Read, 4 for Write operations */
+#define     AT91C_MC_FWS_3FWS              ( 0x3 << 8 )   /* (MC) 4 cycles for Read, 4 for Write operations */
+#define AT91C_MC_FMCN                      ( 0xFF << 16 ) /* (MC) Flash Microsecond Cycle Number */
+/* -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- */
+#define AT91C_MC_FCMD                      ( 0xF << 0 )   /* (MC) Flash Command */
+#define     AT91C_MC_FCMD_START_PROG       ( 0x1 )        /* (MC) Starts the programming of th epage specified by PAGEN. */
+#define     AT91C_MC_FCMD_LOCK             ( 0x2 )        /* (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */
+#define     AT91C_MC_FCMD_PROG_AND_LOCK    ( 0x3 )        /* (MC) The lock sequence automatically happens after the programming sequence is completed. */
+#define     AT91C_MC_FCMD_UNLOCK           ( 0x4 )        /* (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */
+#define     AT91C_MC_FCMD_ERASE_ALL        ( 0x8 )        /* (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. */
+#define     AT91C_MC_FCMD_SET_GP_NVM       ( 0xB )        /* (MC) Set General Purpose NVM bits. */
+#define     AT91C_MC_FCMD_CLR_GP_NVM       ( 0xD )        /* (MC) Clear General Purpose NVM bits. */
+#define     AT91C_MC_FCMD_SET_SECURITY     ( 0xF )        /* (MC) Set Security Bit. */
+#define AT91C_MC_PAGEN                     ( 0x3FF << 8 ) /* (MC) Page Number */
+#define AT91C_MC_KEY                       ( 0xFF << 24 ) /* (MC) Writing Protect Key */
+/* -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- */
+#define AT91C_MC_SECURITY                  ( 0x1 << 4 )   /* (MC) Security Bit Status */
+#define AT91C_MC_GPNVM0                    ( 0x1 << 8 )   /* (MC) Sector 0 Lock Status */
+#define AT91C_MC_GPNVM1                    ( 0x1 << 9 )   /* (MC) Sector 1 Lock Status */
+#define AT91C_MC_GPNVM2                    ( 0x1 << 10 )  /* (MC) Sector 2 Lock Status */
+#define AT91C_MC_GPNVM3                    ( 0x1 << 11 )  /* (MC) Sector 3 Lock Status */
+#define AT91C_MC_GPNVM4                    ( 0x1 << 12 )  /* (MC) Sector 4 Lock Status */
+#define AT91C_MC_GPNVM5                    ( 0x1 << 13 )  /* (MC) Sector 5 Lock Status */
+#define AT91C_MC_GPNVM6                    ( 0x1 << 14 )  /* (MC) Sector 6 Lock Status */
+#define AT91C_MC_GPNVM7                    ( 0x1 << 15 )  /* (MC) Sector 7 Lock Status */
+#define AT91C_MC_LOCKS0                    ( 0x1 << 16 )  /* (MC) Sector 0 Lock Status */
+#define AT91C_MC_LOCKS1                    ( 0x1 << 17 )  /* (MC) Sector 1 Lock Status */
+#define AT91C_MC_LOCKS2                    ( 0x1 << 18 )  /* (MC) Sector 2 Lock Status */
+#define AT91C_MC_LOCKS3                    ( 0x1 << 19 )  /* (MC) Sector 3 Lock Status */
+#define AT91C_MC_LOCKS4                    ( 0x1 << 20 )  /* (MC) Sector 4 Lock Status */
+#define AT91C_MC_LOCKS5                    ( 0x1 << 21 )  /* (MC) Sector 5 Lock Status */
+#define AT91C_MC_LOCKS6                    ( 0x1 << 22 )  /* (MC) Sector 6 Lock Status */
+#define AT91C_MC_LOCKS7                    ( 0x1 << 23 )  /* (MC) Sector 7 Lock Status */
+#define AT91C_MC_LOCKS8                    ( 0x1 << 24 )  /* (MC) Sector 8 Lock Status */
+#define AT91C_MC_LOCKS9                    ( 0x1 << 25 )  /* (MC) Sector 9 Lock Status */
+#define AT91C_MC_LOCKS10                   ( 0x1 << 26 )  /* (MC) Sector 10 Lock Status */
+#define AT91C_MC_LOCKS11                   ( 0x1 << 27 )  /* (MC) Sector 11 Lock Status */
+#define AT91C_MC_LOCKS12                   ( 0x1 << 28 )  /* (MC) Sector 12 Lock Status */
+#define AT91C_MC_LOCKS13                   ( 0x1 << 29 )  /* (MC) Sector 13 Lock Status */
+#define AT91C_MC_LOCKS14                   ( 0x1 << 30 )  /* (MC) Sector 14 Lock Status */
+#define AT91C_MC_LOCKS15                   ( 0x1 << 31 )  /* (MC) Sector 15 Lock Status */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
-// *****************************************************************************
-// *** Register offset in AT91S_SPI structure ***
-#define SPI_CR          ( 0) // Control Register
-#define SPI_MR          ( 4) // Mode Register
-#define SPI_RDR         ( 8) // Receive Data Register
-#define SPI_TDR         (12) // Transmit Data Register
-#define SPI_SR          (16) // Status Register
-#define SPI_IER         (20) // Interrupt Enable Register
-#define SPI_IDR         (24) // Interrupt Disable Register
-#define SPI_IMR         (28) // Interrupt Mask Register
-#define SPI_CSR         (48) // Chip Select Register
-#define SPI_RPR         (256) // Receive Pointer Register
-#define SPI_RCR         (260) // Receive Counter Register
-#define SPI_TPR         (264) // Transmit Pointer Register
-#define SPI_TCR         (268) // Transmit Counter Register
-#define SPI_RNPR        (272) // Receive Next Pointer Register
-#define SPI_RNCR        (276) // Receive Next Counter Register
-#define SPI_TNPR        (280) // Transmit Next Pointer Register
-#define SPI_TNCR        (284) // Transmit Next Counter Register
-#define SPI_PTCR        (288) // PDC Transfer Control Register
-#define SPI_PTSR        (292) // PDC Transfer Status Register
-// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
-#define AT91C_SPI_SPIEN           (0x1 <<  0) // (SPI) SPI Enable
-#define AT91C_SPI_SPIDIS          (0x1 <<  1) // (SPI) SPI Disable
-#define AT91C_SPI_SWRST           (0x1 <<  7) // (SPI) SPI Software reset
-#define AT91C_SPI_LASTXFER        (0x1 << 24) // (SPI) SPI Last Transfer
-// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
-#define AT91C_SPI_MSTR            (0x1 <<  0) // (SPI) Master/Slave Mode
-#define AT91C_SPI_PS              (0x1 <<  1) // (SPI) Peripheral Select
-#define     AT91C_SPI_PS_FIXED                (0x0 <<  1) // (SPI) Fixed Peripheral Select
-#define     AT91C_SPI_PS_VARIABLE             (0x1 <<  1) // (SPI) Variable Peripheral Select
-#define AT91C_SPI_PCSDEC          (0x1 <<  2) // (SPI) Chip Select Decode
-#define AT91C_SPI_FDIV            (0x1 <<  3) // (SPI) Clock Selection
-#define AT91C_SPI_MODFDIS         (0x1 <<  4) // (SPI) Mode Fault Detection
-#define AT91C_SPI_LLB             (0x1 <<  7) // (SPI) Clock Selection
-#define AT91C_SPI_PCS             (0xF << 16) // (SPI) Peripheral Chip Select
-#define AT91C_SPI_DLYBCS          (0xFF << 24) // (SPI) Delay Between Chip Selects
-// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
-#define AT91C_SPI_RD              (0xFFFF <<  0) // (SPI) Receive Data
-#define AT91C_SPI_RPCS            (0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
-#define AT91C_SPI_TD              (0xFFFF <<  0) // (SPI) Transmit Data
-#define AT91C_SPI_TPCS            (0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
-#define AT91C_SPI_RDRF            (0x1 <<  0) // (SPI) Receive Data Register Full
-#define AT91C_SPI_TDRE            (0x1 <<  1) // (SPI) Transmit Data Register Empty
-#define AT91C_SPI_MODF            (0x1 <<  2) // (SPI) Mode Fault Error
-#define AT91C_SPI_OVRES           (0x1 <<  3) // (SPI) Overrun Error Status
-#define AT91C_SPI_ENDRX           (0x1 <<  4) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_ENDTX           (0x1 <<  5) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_RXBUFF          (0x1 <<  6) // (SPI) RXBUFF Interrupt
-#define AT91C_SPI_TXBUFE          (0x1 <<  7) // (SPI) TXBUFE Interrupt
-#define AT91C_SPI_NSSR            (0x1 <<  8) // (SPI) NSSR Interrupt
-#define AT91C_SPI_TXEMPTY         (0x1 <<  9) // (SPI) TXEMPTY Interrupt
-#define AT91C_SPI_SPIENS          (0x1 << 16) // (SPI) Enable Status
-// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
-// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
-// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
-// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
-#define AT91C_SPI_CPOL            (0x1 <<  0) // (SPI) Clock Polarity
-#define AT91C_SPI_NCPHA           (0x1 <<  1) // (SPI) Clock Phase
-#define AT91C_SPI_CSAAT           (0x1 <<  3) // (SPI) Chip Select Active After Transfer
-#define AT91C_SPI_BITS            (0xF <<  4) // (SPI) Bits Per Transfer
-#define     AT91C_SPI_BITS_8                    (0x0 <<  4) // (SPI) 8 Bits Per transfer
-#define     AT91C_SPI_BITS_9                    (0x1 <<  4) // (SPI) 9 Bits Per transfer
-#define     AT91C_SPI_BITS_10                   (0x2 <<  4) // (SPI) 10 Bits Per transfer
-#define     AT91C_SPI_BITS_11                   (0x3 <<  4) // (SPI) 11 Bits Per transfer
-#define     AT91C_SPI_BITS_12                   (0x4 <<  4) // (SPI) 12 Bits Per transfer
-#define     AT91C_SPI_BITS_13                   (0x5 <<  4) // (SPI) 13 Bits Per transfer
-#define     AT91C_SPI_BITS_14                   (0x6 <<  4) // (SPI) 14 Bits Per transfer
-#define     AT91C_SPI_BITS_15                   (0x7 <<  4) // (SPI) 15 Bits Per transfer
-#define     AT91C_SPI_BITS_16                   (0x8 <<  4) // (SPI) 16 Bits Per transfer
-#define AT91C_SPI_SCBR            (0xFF <<  8) // (SPI) Serial Clock Baud Rate
-#define AT91C_SPI_DLYBS           (0xFF << 16) // (SPI) Delay Before SPCK
-#define AT91C_SPI_DLYBCT          (0xFF << 24) // (SPI) Delay Between Consecutive Transfers
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Serial Parallel Interface */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_SPI structure *** */
+#define SPI_CR                       ( 0 )           /* Control Register */
+#define SPI_MR                       ( 4 )           /* Mode Register */
+#define SPI_RDR                      ( 8 )           /* Receive Data Register */
+#define SPI_TDR                      ( 12 )          /* Transmit Data Register */
+#define SPI_SR                       ( 16 )          /* Status Register */
+#define SPI_IER                      ( 20 )          /* Interrupt Enable Register */
+#define SPI_IDR                      ( 24 )          /* Interrupt Disable Register */
+#define SPI_IMR                      ( 28 )          /* Interrupt Mask Register */
+#define SPI_CSR                      ( 48 )          /* Chip Select Register */
+#define SPI_RPR                      ( 256 )         /* Receive Pointer Register */
+#define SPI_RCR                      ( 260 )         /* Receive Counter Register */
+#define SPI_TPR                      ( 264 )         /* Transmit Pointer Register */
+#define SPI_TCR                      ( 268 )         /* Transmit Counter Register */
+#define SPI_RNPR                     ( 272 )         /* Receive Next Pointer Register */
+#define SPI_RNCR                     ( 276 )         /* Receive Next Counter Register */
+#define SPI_TNPR                     ( 280 )         /* Transmit Next Pointer Register */
+#define SPI_TNCR                     ( 284 )         /* Transmit Next Counter Register */
+#define SPI_PTCR                     ( 288 )         /* PDC Transfer Control Register */
+#define SPI_PTSR                     ( 292 )         /* PDC Transfer Status Register */
+/* -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */
+#define AT91C_SPI_SPIEN              ( 0x1 << 0 )    /* (SPI) SPI Enable */
+#define AT91C_SPI_SPIDIS             ( 0x1 << 1 )    /* (SPI) SPI Disable */
+#define AT91C_SPI_SWRST              ( 0x1 << 7 )    /* (SPI) SPI Software reset */
+#define AT91C_SPI_LASTXFER           ( 0x1 << 24 )   /* (SPI) SPI Last Transfer */
+/* -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- */
+#define AT91C_SPI_MSTR               ( 0x1 << 0 )    /* (SPI) Master/Slave Mode */
+#define AT91C_SPI_PS                 ( 0x1 << 1 )    /* (SPI) Peripheral Select */
+#define     AT91C_SPI_PS_FIXED       ( 0x0 << 1 )    /* (SPI) Fixed Peripheral Select */
+#define     AT91C_SPI_PS_VARIABLE    ( 0x1 << 1 )    /* (SPI) Variable Peripheral Select */
+#define AT91C_SPI_PCSDEC             ( 0x1 << 2 )    /* (SPI) Chip Select Decode */
+#define AT91C_SPI_FDIV               ( 0x1 << 3 )    /* (SPI) Clock Selection */
+#define AT91C_SPI_MODFDIS            ( 0x1 << 4 )    /* (SPI) Mode Fault Detection */
+#define AT91C_SPI_LLB                ( 0x1 << 7 )    /* (SPI) Clock Selection */
+#define AT91C_SPI_PCS                ( 0xF << 16 )   /* (SPI) Peripheral Chip Select */
+#define AT91C_SPI_DLYBCS             ( 0xFF << 24 )  /* (SPI) Delay Between Chip Selects */
+/* -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- */
+#define AT91C_SPI_RD                 ( 0xFFFF << 0 ) /* (SPI) Receive Data */
+#define AT91C_SPI_RPCS               ( 0xF << 16 )   /* (SPI) Peripheral Chip Select Status */
+/* -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- */
+#define AT91C_SPI_TD                 ( 0xFFFF << 0 ) /* (SPI) Transmit Data */
+#define AT91C_SPI_TPCS               ( 0xF << 16 )   /* (SPI) Peripheral Chip Select Status */
+/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
+#define AT91C_SPI_RDRF               ( 0x1 << 0 )    /* (SPI) Receive Data Register Full */
+#define AT91C_SPI_TDRE               ( 0x1 << 1 )    /* (SPI) Transmit Data Register Empty */
+#define AT91C_SPI_MODF               ( 0x1 << 2 )    /* (SPI) Mode Fault Error */
+#define AT91C_SPI_OVRES              ( 0x1 << 3 )    /* (SPI) Overrun Error Status */
+#define AT91C_SPI_ENDRX              ( 0x1 << 4 )    /* (SPI) End of Receiver Transfer */
+#define AT91C_SPI_ENDTX              ( 0x1 << 5 )    /* (SPI) End of Receiver Transfer */
+#define AT91C_SPI_RXBUFF             ( 0x1 << 6 )    /* (SPI) RXBUFF Interrupt */
+#define AT91C_SPI_TXBUFE             ( 0x1 << 7 )    /* (SPI) TXBUFE Interrupt */
+#define AT91C_SPI_NSSR               ( 0x1 << 8 )    /* (SPI) NSSR Interrupt */
+#define AT91C_SPI_TXEMPTY            ( 0x1 << 9 )    /* (SPI) TXEMPTY Interrupt */
+#define AT91C_SPI_SPIENS             ( 0x1 << 16 )   /* (SPI) Enable Status */
+/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
+/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
+/* -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */
+/* -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */
+#define AT91C_SPI_CPOL           ( 0x1 << 0 )   /* (SPI) Clock Polarity */
+#define AT91C_SPI_NCPHA          ( 0x1 << 1 )   /* (SPI) Clock Phase */
+#define AT91C_SPI_CSAAT          ( 0x1 << 3 )   /* (SPI) Chip Select Active After Transfer */
+#define AT91C_SPI_BITS           ( 0xF << 4 )   /* (SPI) Bits Per Transfer */
+#define     AT91C_SPI_BITS_8     ( 0x0 << 4 )   /* (SPI) 8 Bits Per transfer */
+#define     AT91C_SPI_BITS_9     ( 0x1 << 4 )   /* (SPI) 9 Bits Per transfer */
+#define     AT91C_SPI_BITS_10    ( 0x2 << 4 )   /* (SPI) 10 Bits Per transfer */
+#define     AT91C_SPI_BITS_11    ( 0x3 << 4 )   /* (SPI) 11 Bits Per transfer */
+#define     AT91C_SPI_BITS_12    ( 0x4 << 4 )   /* (SPI) 12 Bits Per transfer */
+#define     AT91C_SPI_BITS_13    ( 0x5 << 4 )   /* (SPI) 13 Bits Per transfer */
+#define     AT91C_SPI_BITS_14    ( 0x6 << 4 )   /* (SPI) 14 Bits Per transfer */
+#define     AT91C_SPI_BITS_15    ( 0x7 << 4 )   /* (SPI) 15 Bits Per transfer */
+#define     AT91C_SPI_BITS_16    ( 0x8 << 4 )   /* (SPI) 16 Bits Per transfer */
+#define AT91C_SPI_SCBR           ( 0xFF << 8 )  /* (SPI) Serial Clock Baud Rate */
+#define AT91C_SPI_DLYBS          ( 0xFF << 16 ) /* (SPI) Delay Before SPCK */
+#define AT91C_SPI_DLYBCT         ( 0xFF << 24 ) /* (SPI) Delay Between Consecutive Transfers */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Usart
-// *****************************************************************************
-// *** Register offset in AT91S_USART structure ***
-#define US_CR           ( 0) // Control Register
-#define US_MR           ( 4) // Mode Register
-#define US_IER          ( 8) // Interrupt Enable Register
-#define US_IDR          (12) // Interrupt Disable Register
-#define US_IMR          (16) // Interrupt Mask Register
-#define US_CSR          (20) // Channel Status Register
-#define US_RHR          (24) // Receiver Holding Register
-#define US_THR          (28) // Transmitter Holding Register
-#define US_BRGR         (32) // Baud Rate Generator Register
-#define US_RTOR         (36) // Receiver Time-out Register
-#define US_TTGR         (40) // Transmitter Time-guard Register
-#define US_FIDI         (64) // FI_DI_Ratio Register
-#define US_NER          (68) // Nb Errors Register
-#define US_IF           (76) // IRDA_FILTER Register
-#define US_RPR          (256) // Receive Pointer Register
-#define US_RCR          (260) // Receive Counter Register
-#define US_TPR          (264) // Transmit Pointer Register
-#define US_TCR          (268) // Transmit Counter Register
-#define US_RNPR         (272) // Receive Next Pointer Register
-#define US_RNCR         (276) // Receive Next Counter Register
-#define US_TNPR         (280) // Transmit Next Pointer Register
-#define US_TNCR         (284) // Transmit Next Counter Register
-#define US_PTCR         (288) // PDC Transfer Control Register
-#define US_PTSR         (292) // PDC Transfer Status Register
-// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
-#define AT91C_US_STTBRK           (0x1 <<  9) // (USART) Start Break
-#define AT91C_US_STPBRK           (0x1 << 10) // (USART) Stop Break
-#define AT91C_US_STTTO            (0x1 << 11) // (USART) Start Time-out
-#define AT91C_US_SENDA            (0x1 << 12) // (USART) Send Address
-#define AT91C_US_RSTIT            (0x1 << 13) // (USART) Reset Iterations
-#define AT91C_US_RSTNACK          (0x1 << 14) // (USART) Reset Non Acknowledge
-#define AT91C_US_RETTO            (0x1 << 15) // (USART) Rearm Time-out
-#define AT91C_US_DTREN            (0x1 << 16) // (USART) Data Terminal ready Enable
-#define AT91C_US_DTRDIS           (0x1 << 17) // (USART) Data Terminal ready Disable
-#define AT91C_US_RTSEN            (0x1 << 18) // (USART) Request to Send enable
-#define AT91C_US_RTSDIS           (0x1 << 19) // (USART) Request to Send Disable
-// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
-#define AT91C_US_USMODE           (0xF <<  0) // (USART) Usart mode
-#define     AT91C_US_USMODE_NORMAL               (0x0) // (USART) Normal
-#define     AT91C_US_USMODE_RS485                (0x1) // (USART) RS485
-#define     AT91C_US_USMODE_HWHSH                (0x2) // (USART) Hardware Handshaking
-#define     AT91C_US_USMODE_MODEM                (0x3) // (USART) Modem
-#define     AT91C_US_USMODE_ISO7816_0            (0x4) // (USART) ISO7816 protocol: T = 0
-#define     AT91C_US_USMODE_ISO7816_1            (0x6) // (USART) ISO7816 protocol: T = 1
-#define     AT91C_US_USMODE_IRDA                 (0x8) // (USART) IrDA
-#define     AT91C_US_USMODE_SWHSH                (0xC) // (USART) Software Handshaking
-#define AT91C_US_CLKS             (0x3 <<  4) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define     AT91C_US_CLKS_CLOCK                (0x0 <<  4) // (USART) Clock
-#define     AT91C_US_CLKS_FDIV1                (0x1 <<  4) // (USART) fdiv1
-#define     AT91C_US_CLKS_SLOW                 (0x2 <<  4) // (USART) slow_clock (ARM)
-#define     AT91C_US_CLKS_EXT                  (0x3 <<  4) // (USART) External (SCK)
-#define AT91C_US_CHRL             (0x3 <<  6) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define     AT91C_US_CHRL_5_BITS               (0x0 <<  6) // (USART) Character Length: 5 bits
-#define     AT91C_US_CHRL_6_BITS               (0x1 <<  6) // (USART) Character Length: 6 bits
-#define     AT91C_US_CHRL_7_BITS               (0x2 <<  6) // (USART) Character Length: 7 bits
-#define     AT91C_US_CHRL_8_BITS               (0x3 <<  6) // (USART) Character Length: 8 bits
-#define AT91C_US_SYNC             (0x1 <<  8) // (USART) Synchronous Mode Select
-#define AT91C_US_NBSTOP           (0x3 << 12) // (USART) Number of Stop bits
-#define     AT91C_US_NBSTOP_1_BIT                (0x0 << 12) // (USART) 1 stop bit
-#define     AT91C_US_NBSTOP_15_BIT               (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
-#define     AT91C_US_NBSTOP_2_BIT                (0x2 << 12) // (USART) 2 stop bits
-#define AT91C_US_MSBF             (0x1 << 16) // (USART) Bit Order
-#define AT91C_US_MODE9            (0x1 << 17) // (USART) 9-bit Character length
-#define AT91C_US_CKLO             (0x1 << 18) // (USART) Clock Output Select
-#define AT91C_US_OVER             (0x1 << 19) // (USART) Over Sampling Mode
-#define AT91C_US_INACK            (0x1 << 20) // (USART) Inhibit Non Acknowledge
-#define AT91C_US_DSNACK           (0x1 << 21) // (USART) Disable Successive NACK
-#define AT91C_US_MAX_ITER         (0x1 << 24) // (USART) Number of Repetitions
-#define AT91C_US_FILTER           (0x1 << 28) // (USART) Receive Line Filter
-// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
-#define AT91C_US_RXBRK            (0x1 <<  2) // (USART) Break Received/End of Break
-#define AT91C_US_TIMEOUT          (0x1 <<  8) // (USART) Receiver Time-out
-#define AT91C_US_ITERATION        (0x1 << 10) // (USART) Max number of Repetitions Reached
-#define AT91C_US_NACK             (0x1 << 13) // (USART) Non Acknowledge
-#define AT91C_US_RIIC             (0x1 << 16) // (USART) Ring INdicator Input Change Flag
-#define AT91C_US_DSRIC            (0x1 << 17) // (USART) Data Set Ready Input Change Flag
-#define AT91C_US_DCDIC            (0x1 << 18) // (USART) Data Carrier Flag
-#define AT91C_US_CTSIC            (0x1 << 19) // (USART) Clear To Send Input Change Flag
-// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
-// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
-// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
-#define AT91C_US_RI               (0x1 << 20) // (USART) Image of RI Input
-#define AT91C_US_DSR              (0x1 << 21) // (USART) Image of DSR Input
-#define AT91C_US_DCD              (0x1 << 22) // (USART) Image of DCD Input
-#define AT91C_US_CTS              (0x1 << 23) // (USART) Image of CTS Input
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Usart */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_USART structure *** */
+#define US_CR                            ( 0 )         /* Control Register */
+#define US_MR                            ( 4 )         /* Mode Register */
+#define US_IER                           ( 8 )         /* Interrupt Enable Register */
+#define US_IDR                           ( 12 )        /* Interrupt Disable Register */
+#define US_IMR                           ( 16 )        /* Interrupt Mask Register */
+#define US_CSR                           ( 20 )        /* Channel Status Register */
+#define US_RHR                           ( 24 )        /* Receiver Holding Register */
+#define US_THR                           ( 28 )        /* Transmitter Holding Register */
+#define US_BRGR                          ( 32 )        /* Baud Rate Generator Register */
+#define US_RTOR                          ( 36 )        /* Receiver Time-out Register */
+#define US_TTGR                          ( 40 )        /* Transmitter Time-guard Register */
+#define US_FIDI                          ( 64 )        /* FI_DI_Ratio Register */
+#define US_NER                           ( 68 )        /* Nb Errors Register */
+#define US_IF                            ( 76 )        /* IRDA_FILTER Register */
+#define US_RPR                           ( 256 )       /* Receive Pointer Register */
+#define US_RCR                           ( 260 )       /* Receive Counter Register */
+#define US_TPR                           ( 264 )       /* Transmit Pointer Register */
+#define US_TCR                           ( 268 )       /* Transmit Counter Register */
+#define US_RNPR                          ( 272 )       /* Receive Next Pointer Register */
+#define US_RNCR                          ( 276 )       /* Receive Next Counter Register */
+#define US_TNPR                          ( 280 )       /* Transmit Next Pointer Register */
+#define US_TNCR                          ( 284 )       /* Transmit Next Counter Register */
+#define US_PTCR                          ( 288 )       /* PDC Transfer Control Register */
+#define US_PTSR                          ( 292 )       /* PDC Transfer Status Register */
+/* -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- */
+#define AT91C_US_STTBRK                  ( 0x1 << 9 )  /* (USART) Start Break */
+#define AT91C_US_STPBRK                  ( 0x1 << 10 ) /* (USART) Stop Break */
+#define AT91C_US_STTTO                   ( 0x1 << 11 ) /* (USART) Start Time-out */
+#define AT91C_US_SENDA                   ( 0x1 << 12 ) /* (USART) Send Address */
+#define AT91C_US_RSTIT                   ( 0x1 << 13 ) /* (USART) Reset Iterations */
+#define AT91C_US_RSTNACK                 ( 0x1 << 14 ) /* (USART) Reset Non Acknowledge */
+#define AT91C_US_RETTO                   ( 0x1 << 15 ) /* (USART) Rearm Time-out */
+#define AT91C_US_DTREN                   ( 0x1 << 16 ) /* (USART) Data Terminal ready Enable */
+#define AT91C_US_DTRDIS                  ( 0x1 << 17 ) /* (USART) Data Terminal ready Disable */
+#define AT91C_US_RTSEN                   ( 0x1 << 18 ) /* (USART) Request to Send enable */
+#define AT91C_US_RTSDIS                  ( 0x1 << 19 ) /* (USART) Request to Send Disable */
+/* -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- */
+#define AT91C_US_USMODE                  ( 0xF << 0 )  /* (USART) Usart mode */
+#define     AT91C_US_USMODE_NORMAL       ( 0x0 )       /* (USART) Normal */
+#define     AT91C_US_USMODE_RS485        ( 0x1 )       /* (USART) RS485 */
+#define     AT91C_US_USMODE_HWHSH        ( 0x2 )       /* (USART) Hardware Handshaking */
+#define     AT91C_US_USMODE_MODEM        ( 0x3 )       /* (USART) Modem */
+#define     AT91C_US_USMODE_ISO7816_0    ( 0x4 )       /* (USART) ISO7816 protocol: T = 0 */
+#define     AT91C_US_USMODE_ISO7816_1    ( 0x6 )       /* (USART) ISO7816 protocol: T = 1 */
+#define     AT91C_US_USMODE_IRDA         ( 0x8 )       /* (USART) IrDA */
+#define     AT91C_US_USMODE_SWHSH        ( 0xC )       /* (USART) Software Handshaking */
+#define AT91C_US_CLKS                    ( 0x3 << 4 )  /* (USART) Clock Selection (Baud Rate generator Input Clock */
+#define     AT91C_US_CLKS_CLOCK          ( 0x0 << 4 )  /* (USART) Clock */
+#define     AT91C_US_CLKS_FDIV1          ( 0x1 << 4 )  /* (USART) fdiv1 */
+#define     AT91C_US_CLKS_SLOW           ( 0x2 << 4 )  /* (USART) slow_clock (ARM) */
+#define     AT91C_US_CLKS_EXT            ( 0x3 << 4 )  /* (USART) External (SCK) */
+#define AT91C_US_CHRL                    ( 0x3 << 6 )  /* (USART) Clock Selection (Baud Rate generator Input Clock */
+#define     AT91C_US_CHRL_5_BITS         ( 0x0 << 6 )  /* (USART) Character Length: 5 bits */
+#define     AT91C_US_CHRL_6_BITS         ( 0x1 << 6 )  /* (USART) Character Length: 6 bits */
+#define     AT91C_US_CHRL_7_BITS         ( 0x2 << 6 )  /* (USART) Character Length: 7 bits */
+#define     AT91C_US_CHRL_8_BITS         ( 0x3 << 6 )  /* (USART) Character Length: 8 bits */
+#define AT91C_US_SYNC                    ( 0x1 << 8 )  /* (USART) Synchronous Mode Select */
+#define AT91C_US_NBSTOP                  ( 0x3 << 12 ) /* (USART) Number of Stop bits */
+#define     AT91C_US_NBSTOP_1_BIT        ( 0x0 << 12 ) /* (USART) 1 stop bit */
+#define     AT91C_US_NBSTOP_15_BIT       ( 0x1 << 12 ) /* (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits */
+#define     AT91C_US_NBSTOP_2_BIT        ( 0x2 << 12 ) /* (USART) 2 stop bits */
+#define AT91C_US_MSBF                    ( 0x1 << 16 ) /* (USART) Bit Order */
+#define AT91C_US_MODE9                   ( 0x1 << 17 ) /* (USART) 9-bit Character length */
+#define AT91C_US_CKLO                    ( 0x1 << 18 ) /* (USART) Clock Output Select */
+#define AT91C_US_OVER                    ( 0x1 << 19 ) /* (USART) Over Sampling Mode */
+#define AT91C_US_INACK                   ( 0x1 << 20 ) /* (USART) Inhibit Non Acknowledge */
+#define AT91C_US_DSNACK                  ( 0x1 << 21 ) /* (USART) Disable Successive NACK */
+#define AT91C_US_MAX_ITER                ( 0x1 << 24 ) /* (USART) Number of Repetitions */
+#define AT91C_US_FILTER                  ( 0x1 << 28 ) /* (USART) Receive Line Filter */
+/* -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- */
+#define AT91C_US_RXBRK                   ( 0x1 << 2 )  /* (USART) Break Received/End of Break */
+#define AT91C_US_TIMEOUT                 ( 0x1 << 8 )  /* (USART) Receiver Time-out */
+#define AT91C_US_ITERATION               ( 0x1 << 10 ) /* (USART) Max number of Repetitions Reached */
+#define AT91C_US_NACK                    ( 0x1 << 13 ) /* (USART) Non Acknowledge */
+#define AT91C_US_RIIC                    ( 0x1 << 16 ) /* (USART) Ring INdicator Input Change Flag */
+#define AT91C_US_DSRIC                   ( 0x1 << 17 ) /* (USART) Data Set Ready Input Change Flag */
+#define AT91C_US_DCDIC                   ( 0x1 << 18 ) /* (USART) Data Carrier Flag */
+#define AT91C_US_CTSIC                   ( 0x1 << 19 ) /* (USART) Clear To Send Input Change Flag */
+/* -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- */
+/* -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- */
+/* -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- */
+#define AT91C_US_RI     ( 0x1 << 20 )         /* (USART) Image of RI Input */
+#define AT91C_US_DSR    ( 0x1 << 21 )         /* (USART) Image of DSR Input */
+#define AT91C_US_DCD    ( 0x1 << 22 )         /* (USART) Image of DCD Input */
+#define AT91C_US_CTS    ( 0x1 << 23 )         /* (USART) Image of CTS Input */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
-// *****************************************************************************
-// *** Register offset in AT91S_SSC structure ***
-#define SSC_CR          ( 0) // Control Register
-#define SSC_CMR         ( 4) // Clock Mode Register
-#define SSC_RCMR        (16) // Receive Clock ModeRegister
-#define SSC_RFMR        (20) // Receive Frame Mode Register
-#define SSC_TCMR        (24) // Transmit Clock Mode Register
-#define SSC_TFMR        (28) // Transmit Frame Mode Register
-#define SSC_RHR         (32) // Receive Holding Register
-#define SSC_THR         (36) // Transmit Holding Register
-#define SSC_RSHR        (48) // Receive Sync Holding Register
-#define SSC_TSHR        (52) // Transmit Sync Holding Register
-#define SSC_SR          (64) // Status Register
-#define SSC_IER         (68) // Interrupt Enable Register
-#define SSC_IDR         (72) // Interrupt Disable Register
-#define SSC_IMR         (76) // Interrupt Mask Register
-#define SSC_RPR         (256) // Receive Pointer Register
-#define SSC_RCR         (260) // Receive Counter Register
-#define SSC_TPR         (264) // Transmit Pointer Register
-#define SSC_TCR         (268) // Transmit Counter Register
-#define SSC_RNPR        (272) // Receive Next Pointer Register
-#define SSC_RNCR        (276) // Receive Next Counter Register
-#define SSC_TNPR        (280) // Transmit Next Pointer Register
-#define SSC_TNCR        (284) // Transmit Next Counter Register
-#define SSC_PTCR        (288) // PDC Transfer Control Register
-#define SSC_PTSR        (292) // PDC Transfer Status Register
-// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
-#define AT91C_SSC_RXEN            (0x1 <<  0) // (SSC) Receive Enable
-#define AT91C_SSC_RXDIS           (0x1 <<  1) // (SSC) Receive Disable
-#define AT91C_SSC_TXEN            (0x1 <<  8) // (SSC) Transmit Enable
-#define AT91C_SSC_TXDIS           (0x1 <<  9) // (SSC) Transmit Disable
-#define AT91C_SSC_SWRST           (0x1 << 15) // (SSC) Software Reset
-// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
-#define AT91C_SSC_CKS             (0x3 <<  0) // (SSC) Receive/Transmit Clock Selection
-#define     AT91C_SSC_CKS_DIV                  (0x0) // (SSC) Divided Clock
-#define     AT91C_SSC_CKS_TK                   (0x1) // (SSC) TK Clock signal
-#define     AT91C_SSC_CKS_RK                   (0x2) // (SSC) RK pin
-#define AT91C_SSC_CKO             (0x7 <<  2) // (SSC) Receive/Transmit Clock Output Mode Selection
-#define     AT91C_SSC_CKO_NONE                 (0x0 <<  2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
-#define     AT91C_SSC_CKO_CONTINOUS            (0x1 <<  2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
-#define     AT91C_SSC_CKO_DATA_TX              (0x2 <<  2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
-#define AT91C_SSC_CKI             (0x1 <<  5) // (SSC) Receive/Transmit Clock Inversion
-#define AT91C_SSC_START           (0xF <<  8) // (SSC) Receive/Transmit Start Selection
-#define     AT91C_SSC_START_CONTINOUS            (0x0 <<  8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
-#define     AT91C_SSC_START_TX                   (0x1 <<  8) // (SSC) Transmit/Receive start
-#define     AT91C_SSC_START_LOW_RF               (0x2 <<  8) // (SSC) Detection of a low level on RF input
-#define     AT91C_SSC_START_HIGH_RF              (0x3 <<  8) // (SSC) Detection of a high level on RF input
-#define     AT91C_SSC_START_FALL_RF              (0x4 <<  8) // (SSC) Detection of a falling edge on RF input
-#define     AT91C_SSC_START_RISE_RF              (0x5 <<  8) // (SSC) Detection of a rising edge on RF input
-#define     AT91C_SSC_START_LEVEL_RF             (0x6 <<  8) // (SSC) Detection of any level change on RF input
-#define     AT91C_SSC_START_EDGE_RF              (0x7 <<  8) // (SSC) Detection of any edge on RF input
-#define     AT91C_SSC_START_0                    (0x8 <<  8) // (SSC) Compare 0
-#define AT91C_SSC_STTDLY          (0xFF << 16) // (SSC) Receive/Transmit Start Delay
-#define AT91C_SSC_PERIOD          (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
-// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
-#define AT91C_SSC_DATLEN          (0x1F <<  0) // (SSC) Data Length
-#define AT91C_SSC_LOOP            (0x1 <<  5) // (SSC) Loop Mode
-#define AT91C_SSC_MSBF            (0x1 <<  7) // (SSC) Most Significant Bit First
-#define AT91C_SSC_DATNB           (0xF <<  8) // (SSC) Data Number per Frame
-#define AT91C_SSC_FSLEN           (0xF << 16) // (SSC) Receive/Transmit Frame Sync length
-#define AT91C_SSC_FSOS            (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
-#define     AT91C_SSC_FSOS_NONE                 (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
-#define     AT91C_SSC_FSOS_NEGATIVE             (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
-#define     AT91C_SSC_FSOS_POSITIVE             (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
-#define     AT91C_SSC_FSOS_LOW                  (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
-#define     AT91C_SSC_FSOS_HIGH                 (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
-#define     AT91C_SSC_FSOS_TOGGLE               (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
-#define AT91C_SSC_FSEDGE          (0x1 << 24) // (SSC) Frame Sync Edge Detection
-// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
-// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
-#define AT91C_SSC_DATDEF          (0x1 <<  5) // (SSC) Data Default Value
-#define AT91C_SSC_FSDEN           (0x1 << 23) // (SSC) Frame Sync Data Enable
-// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
-#define AT91C_SSC_TXRDY           (0x1 <<  0) // (SSC) Transmit Ready
-#define AT91C_SSC_TXEMPTY         (0x1 <<  1) // (SSC) Transmit Empty
-#define AT91C_SSC_ENDTX           (0x1 <<  2) // (SSC) End Of Transmission
-#define AT91C_SSC_TXBUFE          (0x1 <<  3) // (SSC) Transmit Buffer Empty
-#define AT91C_SSC_RXRDY           (0x1 <<  4) // (SSC) Receive Ready
-#define AT91C_SSC_OVRUN           (0x1 <<  5) // (SSC) Receive Overrun
-#define AT91C_SSC_ENDRX           (0x1 <<  6) // (SSC) End of Reception
-#define AT91C_SSC_RXBUFF          (0x1 <<  7) // (SSC) Receive Buffer Full
-#define AT91C_SSC_TXSYN           (0x1 << 10) // (SSC) Transmit Sync
-#define AT91C_SSC_RXSYN           (0x1 << 11) // (SSC) Receive Sync
-#define AT91C_SSC_TXENA           (0x1 << 16) // (SSC) Transmit Enable
-#define AT91C_SSC_RXENA           (0x1 << 17) // (SSC) Receive Enable
-// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
-// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
-// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_SSC structure *** */
+#define SSC_CR                            ( 0 )          /* Control Register */
+#define SSC_CMR                           ( 4 )          /* Clock Mode Register */
+#define SSC_RCMR                          ( 16 )         /* Receive Clock ModeRegister */
+#define SSC_RFMR                          ( 20 )         /* Receive Frame Mode Register */
+#define SSC_TCMR                          ( 24 )         /* Transmit Clock Mode Register */
+#define SSC_TFMR                          ( 28 )         /* Transmit Frame Mode Register */
+#define SSC_RHR                           ( 32 )         /* Receive Holding Register */
+#define SSC_THR                           ( 36 )         /* Transmit Holding Register */
+#define SSC_RSHR                          ( 48 )         /* Receive Sync Holding Register */
+#define SSC_TSHR                          ( 52 )         /* Transmit Sync Holding Register */
+#define SSC_SR                            ( 64 )         /* Status Register */
+#define SSC_IER                           ( 68 )         /* Interrupt Enable Register */
+#define SSC_IDR                           ( 72 )         /* Interrupt Disable Register */
+#define SSC_IMR                           ( 76 )         /* Interrupt Mask Register */
+#define SSC_RPR                           ( 256 )        /* Receive Pointer Register */
+#define SSC_RCR                           ( 260 )        /* Receive Counter Register */
+#define SSC_TPR                           ( 264 )        /* Transmit Pointer Register */
+#define SSC_TCR                           ( 268 )        /* Transmit Counter Register */
+#define SSC_RNPR                          ( 272 )        /* Receive Next Pointer Register */
+#define SSC_RNCR                          ( 276 )        /* Receive Next Counter Register */
+#define SSC_TNPR                          ( 280 )        /* Transmit Next Pointer Register */
+#define SSC_TNCR                          ( 284 )        /* Transmit Next Counter Register */
+#define SSC_PTCR                          ( 288 )        /* PDC Transfer Control Register */
+#define SSC_PTSR                          ( 292 )        /* PDC Transfer Status Register */
+/* -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- */
+#define AT91C_SSC_RXEN                    ( 0x1 << 0 )   /* (SSC) Receive Enable */
+#define AT91C_SSC_RXDIS                   ( 0x1 << 1 )   /* (SSC) Receive Disable */
+#define AT91C_SSC_TXEN                    ( 0x1 << 8 )   /* (SSC) Transmit Enable */
+#define AT91C_SSC_TXDIS                   ( 0x1 << 9 )   /* (SSC) Transmit Disable */
+#define AT91C_SSC_SWRST                   ( 0x1 << 15 )  /* (SSC) Software Reset */
+/* -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- */
+#define AT91C_SSC_CKS                     ( 0x3 << 0 )   /* (SSC) Receive/Transmit Clock Selection */
+#define     AT91C_SSC_CKS_DIV             ( 0x0 )        /* (SSC) Divided Clock */
+#define     AT91C_SSC_CKS_TK              ( 0x1 )        /* (SSC) TK Clock signal */
+#define     AT91C_SSC_CKS_RK              ( 0x2 )        /* (SSC) RK pin */
+#define AT91C_SSC_CKO                     ( 0x7 << 2 )   /* (SSC) Receive/Transmit Clock Output Mode Selection */
+#define     AT91C_SSC_CKO_NONE            ( 0x0 << 2 )   /* (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only */
+#define     AT91C_SSC_CKO_CONTINUOUS      ( 0x1 << 2 )   /* (SSC) Continuous Receive/Transmit Clock RK pin: Output */
+#define     AT91C_SSC_CKO_DATA_TX         ( 0x2 << 2 )   /* (SSC) Receive/Transmit Clock only during data transfers RK pin: Output */
+#define AT91C_SSC_CKI                     ( 0x1 << 5 )   /* (SSC) Receive/Transmit Clock Inversion */
+#define AT91C_SSC_START                   ( 0xF << 8 )   /* (SSC) Receive/Transmit Start Selection */
+#define     AT91C_SSC_START_CONTINUOUS    ( 0x0 << 8 )   /* (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */
+#define     AT91C_SSC_START_TX            ( 0x1 << 8 )   /* (SSC) Transmit/Receive start */
+#define     AT91C_SSC_START_LOW_RF        ( 0x2 << 8 )   /* (SSC) Detection of a low level on RF input */
+#define     AT91C_SSC_START_HIGH_RF       ( 0x3 << 8 )   /* (SSC) Detection of a high level on RF input */
+#define     AT91C_SSC_START_FALL_RF       ( 0x4 << 8 )   /* (SSC) Detection of a falling edge on RF input */
+#define     AT91C_SSC_START_RISE_RF       ( 0x5 << 8 )   /* (SSC) Detection of a rising edge on RF input */
+#define     AT91C_SSC_START_LEVEL_RF      ( 0x6 << 8 )   /* (SSC) Detection of any level change on RF input */
+#define     AT91C_SSC_START_EDGE_RF       ( 0x7 << 8 )   /* (SSC) Detection of any edge on RF input */
+#define     AT91C_SSC_START_0             ( 0x8 << 8 )   /* (SSC) Compare 0 */
+#define AT91C_SSC_STTDLY                  ( 0xFF << 16 ) /* (SSC) Receive/Transmit Start Delay */
+#define AT91C_SSC_PERIOD                  ( 0xFF << 24 ) /* (SSC) Receive/Transmit Period Divider Selection */
+/* -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- */
+#define AT91C_SSC_DATLEN                  ( 0x1F << 0 )  /* (SSC) Data Length */
+#define AT91C_SSC_LOOP                    ( 0x1 << 5 )   /* (SSC) Loop Mode */
+#define AT91C_SSC_MSBF                    ( 0x1 << 7 )   /* (SSC) Most Significant Bit First */
+#define AT91C_SSC_DATNB                   ( 0xF << 8 )   /* (SSC) Data Number per Frame */
+#define AT91C_SSC_FSLEN                   ( 0xF << 16 )  /* (SSC) Receive/Transmit Frame Sync length */
+#define AT91C_SSC_FSOS                    ( 0x7 << 20 )  /* (SSC) Receive/Transmit Frame Sync Output Selection */
+#define     AT91C_SSC_FSOS_NONE           ( 0x0 << 20 )  /* (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only */
+#define     AT91C_SSC_FSOS_NEGATIVE       ( 0x1 << 20 )  /* (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse */
+#define     AT91C_SSC_FSOS_POSITIVE       ( 0x2 << 20 )  /* (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse */
+#define     AT91C_SSC_FSOS_LOW            ( 0x3 << 20 )  /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer */
+#define     AT91C_SSC_FSOS_HIGH           ( 0x4 << 20 )  /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer */
+#define     AT91C_SSC_FSOS_TOGGLE         ( 0x5 << 20 )  /* (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer */
+#define AT91C_SSC_FSEDGE                  ( 0x1 << 24 )  /* (SSC) Frame Sync Edge Detection */
+/* -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- */
+/* -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- */
+#define AT91C_SSC_DATDEF                  ( 0x1 << 5 )  /* (SSC) Data Default Value */
+#define AT91C_SSC_FSDEN                   ( 0x1 << 23 ) /* (SSC) Frame Sync Data Enable */
+/* -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- */
+#define AT91C_SSC_TXRDY                   ( 0x1 << 0 )  /* (SSC) Transmit Ready */
+#define AT91C_SSC_TXEMPTY                 ( 0x1 << 1 )  /* (SSC) Transmit Empty */
+#define AT91C_SSC_ENDTX                   ( 0x1 << 2 )  /* (SSC) End Of Transmission */
+#define AT91C_SSC_TXBUFE                  ( 0x1 << 3 )  /* (SSC) Transmit Buffer Empty */
+#define AT91C_SSC_RXRDY                   ( 0x1 << 4 )  /* (SSC) Receive Ready */
+#define AT91C_SSC_OVRUN                   ( 0x1 << 5 )  /* (SSC) Receive Overrun */
+#define AT91C_SSC_ENDRX                   ( 0x1 << 6 )  /* (SSC) End of Reception */
+#define AT91C_SSC_RXBUFF                  ( 0x1 << 7 )  /* (SSC) Receive Buffer Full */
+#define AT91C_SSC_TXSYN                   ( 0x1 << 10 ) /* (SSC) Transmit Sync */
+#define AT91C_SSC_RXSYN                   ( 0x1 << 11 ) /* (SSC) Receive Sync */
+#define AT91C_SSC_TXENA                   ( 0x1 << 16 ) /* (SSC) Transmit Enable */
+#define AT91C_SSC_RXENA                   ( 0x1 << 17 ) /* (SSC) Receive Enable */
+/* -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- */
+/* -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- */
+/* -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Two-wire Interface
-// *****************************************************************************
-// *** Register offset in AT91S_TWI structure ***
-#define TWI_CR          ( 0) // Control Register
-#define TWI_MMR         ( 4) // Master Mode Register
-#define TWI_IADR        (12) // Internal Address Register
-#define TWI_CWGR        (16) // Clock Waveform Generator Register
-#define TWI_SR          (32) // Status Register
-#define TWI_IER         (36) // Interrupt Enable Register
-#define TWI_IDR         (40) // Interrupt Disable Register
-#define TWI_IMR         (44) // Interrupt Mask Register
-#define TWI_RHR         (48) // Receive Holding Register
-#define TWI_THR         (52) // Transmit Holding Register
-// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
-#define AT91C_TWI_START           (0x1 <<  0) // (TWI) Send a START Condition
-#define AT91C_TWI_STOP            (0x1 <<  1) // (TWI) Send a STOP Condition
-#define AT91C_TWI_MSEN            (0x1 <<  2) // (TWI) TWI Master Transfer Enabled
-#define AT91C_TWI_MSDIS           (0x1 <<  3) // (TWI) TWI Master Transfer Disabled
-#define AT91C_TWI_SWRST           (0x1 <<  7) // (TWI) Software Reset
-// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
-#define AT91C_TWI_IADRSZ          (0x3 <<  8) // (TWI) Internal Device Address Size
-#define     AT91C_TWI_IADRSZ_NO                   (0x0 <<  8) // (TWI) No internal device address
-#define     AT91C_TWI_IADRSZ_1_BYTE               (0x1 <<  8) // (TWI) One-byte internal device address
-#define     AT91C_TWI_IADRSZ_2_BYTE               (0x2 <<  8) // (TWI) Two-byte internal device address
-#define     AT91C_TWI_IADRSZ_3_BYTE               (0x3 <<  8) // (TWI) Three-byte internal device address
-#define AT91C_TWI_MREAD           (0x1 << 12) // (TWI) Master Read Direction
-#define AT91C_TWI_DADR            (0x7F << 16) // (TWI) Device Address
-// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
-#define AT91C_TWI_CLDIV           (0xFF <<  0) // (TWI) Clock Low Divider
-#define AT91C_TWI_CHDIV           (0xFF <<  8) // (TWI) Clock High Divider
-#define AT91C_TWI_CKDIV           (0x7 << 16) // (TWI) Clock Divider
-// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
-#define AT91C_TWI_TXCOMP          (0x1 <<  0) // (TWI) Transmission Completed
-#define AT91C_TWI_RXRDY           (0x1 <<  1) // (TWI) Receive holding register ReaDY
-#define AT91C_TWI_TXRDY           (0x1 <<  2) // (TWI) Transmit holding register ReaDY
-#define AT91C_TWI_OVRE            (0x1 <<  6) // (TWI) Overrun Error
-#define AT91C_TWI_UNRE            (0x1 <<  7) // (TWI) Underrun Error
-#define AT91C_TWI_NACK            (0x1 <<  8) // (TWI) Not Acknowledged
-// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
-// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
-// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Two-wire Interface */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_TWI structure *** */
+#define TWI_CR                         ( 0 )          /* Control Register */
+#define TWI_MMR                        ( 4 )          /* Master Mode Register */
+#define TWI_IADR                       ( 12 )         /* Internal Address Register */
+#define TWI_CWGR                       ( 16 )         /* Clock Waveform Generator Register */
+#define TWI_SR                         ( 32 )         /* Status Register */
+#define TWI_IER                        ( 36 )         /* Interrupt Enable Register */
+#define TWI_IDR                        ( 40 )         /* Interrupt Disable Register */
+#define TWI_IMR                        ( 44 )         /* Interrupt Mask Register */
+#define TWI_RHR                        ( 48 )         /* Receive Holding Register */
+#define TWI_THR                        ( 52 )         /* Transmit Holding Register */
+/* -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- */
+#define AT91C_TWI_START                ( 0x1 << 0 )   /* (TWI) Send a START Condition */
+#define AT91C_TWI_STOP                 ( 0x1 << 1 )   /* (TWI) Send a STOP Condition */
+#define AT91C_TWI_MSEN                 ( 0x1 << 2 )   /* (TWI) TWI Master Transfer Enabled */
+#define AT91C_TWI_MSDIS                ( 0x1 << 3 )   /* (TWI) TWI Master Transfer Disabled */
+#define AT91C_TWI_SWRST                ( 0x1 << 7 )   /* (TWI) Software Reset */
+/* -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- */
+#define AT91C_TWI_IADRSZ               ( 0x3 << 8 )   /* (TWI) Internal Device Address Size */
+#define     AT91C_TWI_IADRSZ_NO        ( 0x0 << 8 )   /* (TWI) No internal device address */
+#define     AT91C_TWI_IADRSZ_1_BYTE    ( 0x1 << 8 )   /* (TWI) One-byte internal device address */
+#define     AT91C_TWI_IADRSZ_2_BYTE    ( 0x2 << 8 )   /* (TWI) Two-byte internal device address */
+#define     AT91C_TWI_IADRSZ_3_BYTE    ( 0x3 << 8 )   /* (TWI) Three-byte internal device address */
+#define AT91C_TWI_MREAD                ( 0x1 << 12 )  /* (TWI) Master Read Direction */
+#define AT91C_TWI_DADR                 ( 0x7F << 16 ) /* (TWI) Device Address */
+/* -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- */
+#define AT91C_TWI_CLDIV                ( 0xFF << 0 )  /* (TWI) Clock Low Divider */
+#define AT91C_TWI_CHDIV                ( 0xFF << 8 )  /* (TWI) Clock High Divider */
+#define AT91C_TWI_CKDIV                ( 0x7 << 16 )  /* (TWI) Clock Divider */
+/* -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- */
+#define AT91C_TWI_TXCOMP               ( 0x1 << 0 )   /* (TWI) Transmission Completed */
+#define AT91C_TWI_RXRDY                ( 0x1 << 1 )   /* (TWI) Receive holding register ReaDY */
+#define AT91C_TWI_TXRDY                ( 0x1 << 2 )   /* (TWI) Transmit holding register ReaDY */
+#define AT91C_TWI_OVRE                 ( 0x1 << 6 )   /* (TWI) Overrun Error */
+#define AT91C_TWI_UNRE                 ( 0x1 << 7 )   /* (TWI) Underrun Error */
+#define AT91C_TWI_NACK                 ( 0x1 << 8 )   /* (TWI) Not Acknowledged */
+/* -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- */
+/* -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- */
+/* -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR PWMC Channel Interface
-// *****************************************************************************
-// *** Register offset in AT91S_PWMC_CH structure ***
-#define PWMC_CMR        ( 0) // Channel Mode Register
-#define PWMC_CDTYR      ( 4) // Channel Duty Cycle Register
-#define PWMC_CPRDR      ( 8) // Channel Period Register
-#define PWMC_CCNTR      (12) // Channel Counter Register
-#define PWMC_CUPDR      (16) // Channel Update Register
-#define PWMC_Reserved   (20) // Reserved
-// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
-#define AT91C_PWMC_CPRE           (0xF <<  0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
-#define     AT91C_PWMC_CPRE_MCK                  (0x0) // (PWMC_CH)
-#define     AT91C_PWMC_CPRE_MCKA                 (0xB) // (PWMC_CH)
-#define     AT91C_PWMC_CPRE_MCKB                 (0xC) // (PWMC_CH)
-#define AT91C_PWMC_CALG           (0x1 <<  8) // (PWMC_CH) Channel Alignment
-#define AT91C_PWMC_CPOL           (0x1 <<  9) // (PWMC_CH) Channel Polarity
-#define AT91C_PWMC_CPD            (0x1 << 10) // (PWMC_CH) Channel Update Period
-// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
-#define AT91C_PWMC_CDTY           (0x0 <<  0) // (PWMC_CH) Channel Duty Cycle
-// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
-#define AT91C_PWMC_CPRD           (0x0 <<  0) // (PWMC_CH) Channel Period
-// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
-#define AT91C_PWMC_CCNT           (0x0 <<  0) // (PWMC_CH) Channel Counter
-// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
-#define AT91C_PWMC_CUPD           (0x0 <<  0) // (PWMC_CH) Channel Update
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR PWMC Channel Interface */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_PWMC_CH structure *** */
+#define PWMC_CMR                    ( 0 )         /* Channel Mode Register */
+#define PWMC_CDTYR                  ( 4 )         /* Channel Duty Cycle Register */
+#define PWMC_CPRDR                  ( 8 )         /* Channel Period Register */
+#define PWMC_CCNTR                  ( 12 )        /* Channel Counter Register */
+#define PWMC_CUPDR                  ( 16 )        /* Channel Update Register */
+#define PWMC_Reserved               ( 20 )        /* Reserved */
+/* -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- */
+#define AT91C_PWMC_CPRE             ( 0xF << 0 )  /* (PWMC_CH) Channel Pre-scaler : PWMC_CLKx */
+#define     AT91C_PWMC_CPRE_MCK     ( 0x0 )       /* (PWMC_CH) */
+#define     AT91C_PWMC_CPRE_MCKA    ( 0xB )       /* (PWMC_CH) */
+#define     AT91C_PWMC_CPRE_MCKB    ( 0xC )       /* (PWMC_CH) */
+#define AT91C_PWMC_CALG             ( 0x1 << 8 )  /* (PWMC_CH) Channel Alignment */
+#define AT91C_PWMC_CPOL             ( 0x1 << 9 )  /* (PWMC_CH) Channel Polarity */
+#define AT91C_PWMC_CPD              ( 0x1 << 10 ) /* (PWMC_CH) Channel Update Period */
+/* -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- */
+#define AT91C_PWMC_CDTY             ( 0x0 << 0 )  /* (PWMC_CH) Channel Duty Cycle */
+/* -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- */
+#define AT91C_PWMC_CPRD             ( 0x0 << 0 )  /* (PWMC_CH) Channel Period */
+/* -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- */
+#define AT91C_PWMC_CCNT             ( 0x0 << 0 )  /* (PWMC_CH) Channel Counter */
+/* -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- */
+#define AT91C_PWMC_CUPD             ( 0x0 << 0 )  /* (PWMC_CH) Channel Update */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface
-// *****************************************************************************
-// *** Register offset in AT91S_PWMC structure ***
-#define PWMC_MR         ( 0) // PWMC Mode Register
-#define PWMC_ENA        ( 4) // PWMC Enable Register
-#define PWMC_DIS        ( 8) // PWMC Disable Register
-#define PWMC_SR         (12) // PWMC Status Register
-#define PWMC_IER        (16) // PWMC Interrupt Enable Register
-#define PWMC_IDR        (20) // PWMC Interrupt Disable Register
-#define PWMC_IMR        (24) // PWMC Interrupt Mask Register
-#define PWMC_ISR        (28) // PWMC Interrupt Status Register
-#define PWMC_VR         (252) // PWMC Version Register
-#define PWMC_CH         (512) // PWMC Channel
-// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
-#define AT91C_PWMC_DIVA           (0xFF <<  0) // (PWMC) CLKA divide factor.
-#define AT91C_PWMC_PREA           (0xF <<  8) // (PWMC) Divider Input Clock Prescaler A
-#define     AT91C_PWMC_PREA_MCK                  (0x0 <<  8) // (PWMC)
-#define AT91C_PWMC_DIVB           (0xFF << 16) // (PWMC) CLKB divide factor.
-#define AT91C_PWMC_PREB           (0xF << 24) // (PWMC) Divider Input Clock Prescaler B
-#define     AT91C_PWMC_PREB_MCK                  (0x0 << 24) // (PWMC)
-// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
-#define AT91C_PWMC_CHID0          (0x1 <<  0) // (PWMC) Channel ID 0
-#define AT91C_PWMC_CHID1          (0x1 <<  1) // (PWMC) Channel ID 1
-#define AT91C_PWMC_CHID2          (0x1 <<  2) // (PWMC) Channel ID 2
-#define AT91C_PWMC_CHID3          (0x1 <<  3) // (PWMC) Channel ID 3
-// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
-// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
-// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
-// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
-// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
-// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_PWMC structure *** */
+#define PWMC_MR                    ( 0 )          /* PWMC Mode Register */
+#define PWMC_ENA                   ( 4 )          /* PWMC Enable Register */
+#define PWMC_DIS                   ( 8 )          /* PWMC Disable Register */
+#define PWMC_SR                    ( 12 )         /* PWMC Status Register */
+#define PWMC_IER                   ( 16 )         /* PWMC Interrupt Enable Register */
+#define PWMC_IDR                   ( 20 )         /* PWMC Interrupt Disable Register */
+#define PWMC_IMR                   ( 24 )         /* PWMC Interrupt Mask Register */
+#define PWMC_ISR                   ( 28 )         /* PWMC Interrupt Status Register */
+#define PWMC_VR                    ( 252 )        /* PWMC Version Register */
+#define PWMC_CH                    ( 512 )        /* PWMC Channel */
+/* -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- */
+#define AT91C_PWMC_DIVA            ( 0xFF << 0 )  /* (PWMC) CLKA divide factor. */
+#define AT91C_PWMC_PREA            ( 0xF << 8 )   /* (PWMC) Divider Input Clock Prescaler A */
+#define     AT91C_PWMC_PREA_MCK    ( 0x0 << 8 )   /* (PWMC) */
+#define AT91C_PWMC_DIVB            ( 0xFF << 16 ) /* (PWMC) CLKB divide factor. */
+#define AT91C_PWMC_PREB            ( 0xF << 24 )  /* (PWMC) Divider Input Clock Prescaler B */
+#define     AT91C_PWMC_PREB_MCK    ( 0x0 << 24 )  /* (PWMC) */
+/* -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- */
+#define AT91C_PWMC_CHID0           ( 0x1 << 0 )   /* (PWMC) Channel ID 0 */
+#define AT91C_PWMC_CHID1           ( 0x1 << 1 )   /* (PWMC) Channel ID 1 */
+#define AT91C_PWMC_CHID2           ( 0x1 << 2 )   /* (PWMC) Channel ID 2 */
+#define AT91C_PWMC_CHID3           ( 0x1 << 3 )   /* (PWMC) Channel ID 3 */
+/* -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- */
+/* -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- */
+/* -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- */
+/* -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- */
+/* -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- */
+/* -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR USB Device Interface
-// *****************************************************************************
-// *** Register offset in AT91S_UDP structure ***
-#define UDP_NUM         ( 0) // Frame Number Register
-#define UDP_GLBSTATE    ( 4) // Global State Register
-#define UDP_FADDR       ( 8) // Function Address Register
-#define UDP_IER         (16) // Interrupt Enable Register
-#define UDP_IDR         (20) // Interrupt Disable Register
-#define UDP_IMR         (24) // Interrupt Mask Register
-#define UDP_ISR         (28) // Interrupt Status Register
-#define UDP_ICR         (32) // Interrupt Clear Register
-#define UDP_RSTEP       (40) // Reset Endpoint Register
-#define UDP_CSR         (48) // Endpoint Control and Status Register
-#define UDP_FDR         (80) // Endpoint FIFO Data Register
-#define UDP_TXVC        (116) // Transceiver Control Register
-// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
-#define AT91C_UDP_FRM_NUM         (0x7FF <<  0) // (UDP) Frame Number as Defined in the Packet Field Formats
-#define AT91C_UDP_FRM_ERR         (0x1 << 16) // (UDP) Frame Error
-#define AT91C_UDP_FRM_OK          (0x1 << 17) // (UDP) Frame OK
-// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
-#define AT91C_UDP_FADDEN          (0x1 <<  0) // (UDP) Function Address Enable
-#define AT91C_UDP_CONFG           (0x1 <<  1) // (UDP) Configured
-#define AT91C_UDP_ESR             (0x1 <<  2) // (UDP) Enable Send Resume
-#define AT91C_UDP_RSMINPR         (0x1 <<  3) // (UDP) A Resume Has Been Sent to the Host
-#define AT91C_UDP_RMWUPE          (0x1 <<  4) // (UDP) Remote Wake Up Enable
-// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
-#define AT91C_UDP_FADD            (0xFF <<  0) // (UDP) Function Address Value
-#define AT91C_UDP_FEN             (0x1 <<  8) // (UDP) Function Enable
-// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
-#define AT91C_UDP_EPINT0          (0x1 <<  0) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT1          (0x1 <<  1) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT2          (0x1 <<  2) // (UDP) Endpoint 2 Interrupt
-#define AT91C_UDP_EPINT3          (0x1 <<  3) // (UDP) Endpoint 3 Interrupt
-#define AT91C_UDP_EPINT4          (0x1 <<  4) // (UDP) Endpoint 4 Interrupt
-#define AT91C_UDP_EPINT5          (0x1 <<  5) // (UDP) Endpoint 5 Interrupt
-#define AT91C_UDP_RXSUSP          (0x1 <<  8) // (UDP) USB Suspend Interrupt
-#define AT91C_UDP_RXRSM           (0x1 <<  9) // (UDP) USB Resume Interrupt
-#define AT91C_UDP_EXTRSM          (0x1 << 10) // (UDP) USB External Resume Interrupt
-#define AT91C_UDP_SOFINT          (0x1 << 11) // (UDP) USB Start Of frame Interrupt
-#define AT91C_UDP_WAKEUP          (0x1 << 13) // (UDP) USB Resume Interrupt
-// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
-// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
-// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
-#define AT91C_UDP_ENDBUSRES       (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
-// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
-// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
-#define AT91C_UDP_EP0             (0x1 <<  0) // (UDP) Reset Endpoint 0
-#define AT91C_UDP_EP1             (0x1 <<  1) // (UDP) Reset Endpoint 1
-#define AT91C_UDP_EP2             (0x1 <<  2) // (UDP) Reset Endpoint 2
-#define AT91C_UDP_EP3             (0x1 <<  3) // (UDP) Reset Endpoint 3
-#define AT91C_UDP_EP4             (0x1 <<  4) // (UDP) Reset Endpoint 4
-#define AT91C_UDP_EP5             (0x1 <<  5) // (UDP) Reset Endpoint 5
-// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
-#define AT91C_UDP_TXCOMP          (0x1 <<  0) // (UDP) Generates an IN packet with data previously written in the DPR
-#define AT91C_UDP_RX_DATA_BK0     (0x1 <<  1) // (UDP) Receive Data Bank 0
-#define AT91C_UDP_RXSETUP         (0x1 <<  2) // (UDP) Sends STALL to the Host (Control endpoints)
-#define AT91C_UDP_ISOERROR        (0x1 <<  3) // (UDP) Isochronous error (Isochronous endpoints)
-#define AT91C_UDP_TXPKTRDY        (0x1 <<  4) // (UDP) Transmit Packet Ready
-#define AT91C_UDP_FORCESTALL      (0x1 <<  5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
-#define AT91C_UDP_RX_DATA_BK1     (0x1 <<  6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
-#define AT91C_UDP_DIR             (0x1 <<  7) // (UDP) Transfer Direction
-#define AT91C_UDP_EPTYPE          (0x7 <<  8) // (UDP) Endpoint type
-#define     AT91C_UDP_EPTYPE_CTRL                 (0x0 <<  8) // (UDP) Control
-#define     AT91C_UDP_EPTYPE_ISO_OUT              (0x1 <<  8) // (UDP) Isochronous OUT
-#define     AT91C_UDP_EPTYPE_BULK_OUT             (0x2 <<  8) // (UDP) Bulk OUT
-#define     AT91C_UDP_EPTYPE_INT_OUT              (0x3 <<  8) // (UDP) Interrupt OUT
-#define     AT91C_UDP_EPTYPE_ISO_IN               (0x5 <<  8) // (UDP) Isochronous IN
-#define     AT91C_UDP_EPTYPE_BULK_IN              (0x6 <<  8) // (UDP) Bulk IN
-#define     AT91C_UDP_EPTYPE_INT_IN               (0x7 <<  8) // (UDP) Interrupt IN
-#define AT91C_UDP_DTGLE           (0x1 << 11) // (UDP) Data Toggle
-#define AT91C_UDP_EPEDS           (0x1 << 15) // (UDP) Endpoint Enable Disable
-#define AT91C_UDP_RXBYTECNT       (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
-// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------
-#define AT91C_UDP_TXVDIS          (0x1 <<  8) // (UDP)
-#define AT91C_UDP_PUON            (0x1 <<  9) // (UDP) Pull-up ON
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR USB Device Interface */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_UDP structure *** */
+#define UDP_NUM              ( 0 )          /* Frame Number Register */
+#define UDP_GLBSTATE         ( 4 )          /* Global State Register */
+#define UDP_FADDR            ( 8 )          /* Function Address Register */
+#define UDP_IER              ( 16 )         /* Interrupt Enable Register */
+#define UDP_IDR              ( 20 )         /* Interrupt Disable Register */
+#define UDP_IMR              ( 24 )         /* Interrupt Mask Register */
+#define UDP_ISR              ( 28 )         /* Interrupt Status Register */
+#define UDP_ICR              ( 32 )         /* Interrupt Clear Register */
+#define UDP_RSTEP            ( 40 )         /* Reset Endpoint Register */
+#define UDP_CSR              ( 48 )         /* Endpoint Control and Status Register */
+#define UDP_FDR              ( 80 )         /* Endpoint FIFO Data Register */
+#define UDP_TXVC             ( 116 )        /* Transceiver Control Register */
+/* -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- */
+#define AT91C_UDP_FRM_NUM    ( 0x7FF << 0 ) /* (UDP) Frame Number as Defined in the Packet Field Formats */
+#define AT91C_UDP_FRM_ERR    ( 0x1 << 16 )  /* (UDP) Frame Error */
+#define AT91C_UDP_FRM_OK     ( 0x1 << 17 )  /* (UDP) Frame OK */
+/* -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- */
+#define AT91C_UDP_FADDEN     ( 0x1 << 0 )   /* (UDP) Function Address Enable */
+#define AT91C_UDP_CONFG      ( 0x1 << 1 )   /* (UDP) Configured */
+#define AT91C_UDP_ESR        ( 0x1 << 2 )   /* (UDP) Enable Send Resume */
+#define AT91C_UDP_RSMINPR    ( 0x1 << 3 )   /* (UDP) A Resume Has Been Sent to the Host */
+#define AT91C_UDP_RMWUPE     ( 0x1 << 4 )   /* (UDP) Remote Wake Up Enable */
+/* -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- */
+#define AT91C_UDP_FADD       ( 0xFF << 0 )  /* (UDP) Function Address Value */
+#define AT91C_UDP_FEN        ( 0x1 << 8 )   /* (UDP) Function Enable */
+/* -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- */
+#define AT91C_UDP_EPINT0     ( 0x1 << 0 )   /* (UDP) Endpoint 0 Interrupt */
+#define AT91C_UDP_EPINT1     ( 0x1 << 1 )   /* (UDP) Endpoint 0 Interrupt */
+#define AT91C_UDP_EPINT2     ( 0x1 << 2 )   /* (UDP) Endpoint 2 Interrupt */
+#define AT91C_UDP_EPINT3     ( 0x1 << 3 )   /* (UDP) Endpoint 3 Interrupt */
+#define AT91C_UDP_EPINT4     ( 0x1 << 4 )   /* (UDP) Endpoint 4 Interrupt */
+#define AT91C_UDP_EPINT5     ( 0x1 << 5 )   /* (UDP) Endpoint 5 Interrupt */
+#define AT91C_UDP_RXSUSP     ( 0x1 << 8 )   /* (UDP) USB Suspend Interrupt */
+#define AT91C_UDP_RXRSM      ( 0x1 << 9 )   /* (UDP) USB Resume Interrupt */
+#define AT91C_UDP_EXTRSM     ( 0x1 << 10 )  /* (UDP) USB External Resume Interrupt */
+#define AT91C_UDP_SOFINT     ( 0x1 << 11 )  /* (UDP) USB Start Of frame Interrupt */
+#define AT91C_UDP_WAKEUP     ( 0x1 << 13 )  /* (UDP) USB Resume Interrupt */
+/* -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- */
+/* -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- */
+/* -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- */
+#define AT91C_UDP_ENDBUSRES              ( 0x1 << 12 ) /* (UDP) USB End Of Bus Reset Interrupt */
+/* -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- */
+/* -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- */
+#define AT91C_UDP_EP0                    ( 0x1 << 0 )    /* (UDP) Reset Endpoint 0 */
+#define AT91C_UDP_EP1                    ( 0x1 << 1 )    /* (UDP) Reset Endpoint 1 */
+#define AT91C_UDP_EP2                    ( 0x1 << 2 )    /* (UDP) Reset Endpoint 2 */
+#define AT91C_UDP_EP3                    ( 0x1 << 3 )    /* (UDP) Reset Endpoint 3 */
+#define AT91C_UDP_EP4                    ( 0x1 << 4 )    /* (UDP) Reset Endpoint 4 */
+#define AT91C_UDP_EP5                    ( 0x1 << 5 )    /* (UDP) Reset Endpoint 5 */
+/* -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- */
+#define AT91C_UDP_TXCOMP                 ( 0x1 << 0 )    /* (UDP) Generates an IN packet with data previously written in the DPR */
+#define AT91C_UDP_RX_DATA_BK0            ( 0x1 << 1 )    /* (UDP) Receive Data Bank 0 */
+#define AT91C_UDP_RXSETUP                ( 0x1 << 2 )    /* (UDP) Sends STALL to the Host (Control endpoints) */
+#define AT91C_UDP_ISOERROR               ( 0x1 << 3 )    /* (UDP) Isochronous error (Isochronous endpoints) */
+#define AT91C_UDP_TXPKTRDY               ( 0x1 << 4 )    /* (UDP) Transmit Packet Ready */
+#define AT91C_UDP_FORCESTALL             ( 0x1 << 5 )    /* (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). */
+#define AT91C_UDP_RX_DATA_BK1            ( 0x1 << 6 )    /* (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). */
+#define AT91C_UDP_DIR                    ( 0x1 << 7 )    /* (UDP) Transfer Direction */
+#define AT91C_UDP_EPTYPE                 ( 0x7 << 8 )    /* (UDP) Endpoint type */
+#define     AT91C_UDP_EPTYPE_CTRL        ( 0x0 << 8 )    /* (UDP) Control */
+#define     AT91C_UDP_EPTYPE_ISO_OUT     ( 0x1 << 8 )    /* (UDP) Isochronous OUT */
+#define     AT91C_UDP_EPTYPE_BULK_OUT    ( 0x2 << 8 )    /* (UDP) Bulk OUT */
+#define     AT91C_UDP_EPTYPE_INT_OUT     ( 0x3 << 8 )    /* (UDP) Interrupt OUT */
+#define     AT91C_UDP_EPTYPE_ISO_IN      ( 0x5 << 8 )    /* (UDP) Isochronous IN */
+#define     AT91C_UDP_EPTYPE_BULK_IN     ( 0x6 << 8 )    /* (UDP) Bulk IN */
+#define     AT91C_UDP_EPTYPE_INT_IN      ( 0x7 << 8 )    /* (UDP) Interrupt IN */
+#define AT91C_UDP_DTGLE                  ( 0x1 << 11 )   /* (UDP) Data Toggle */
+#define AT91C_UDP_EPEDS                  ( 0x1 << 15 )   /* (UDP) Endpoint Enable Disable */
+#define AT91C_UDP_RXBYTECNT              ( 0x7FF << 16 ) /* (UDP) Number Of Bytes Available in the FIFO */
+/* -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- */
+#define AT91C_UDP_TXVDIS                 ( 0x1 << 8 )    /* (UDP) */
+#define AT91C_UDP_PUON                   ( 0x1 << 9 )    /* (UDP) Pull-up ON */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
-// *****************************************************************************
-// *** Register offset in AT91S_TC structure ***
-#define TC_CCR          ( 0) // Channel Control Register
-#define TC_CMR          ( 4) // Channel Mode Register (Capture Mode / Waveform Mode)
-#define TC_CV           (16) // Counter Value
-#define TC_RA           (20) // Register A
-#define TC_RB           (24) // Register B
-#define TC_RC           (28) // Register C
-#define TC_SR           (32) // Status Register
-#define TC_IER          (36) // Interrupt Enable Register
-#define TC_IDR          (40) // Interrupt Disable Register
-#define TC_IMR          (44) // Interrupt Mask Register
-// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
-#define AT91C_TC_CLKEN            (0x1 <<  0) // (TC) Counter Clock Enable Command
-#define AT91C_TC_CLKDIS           (0x1 <<  1) // (TC) Counter Clock Disable Command
-#define AT91C_TC_SWTRG            (0x1 <<  2) // (TC) Software Trigger Command
-// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
-#define AT91C_TC_CLKS             (0x7 <<  0) // (TC) Clock Selection
-#define     AT91C_TC_CLKS_TIMER_DIV1_CLOCK     (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
-#define     AT91C_TC_CLKS_TIMER_DIV2_CLOCK     (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
-#define     AT91C_TC_CLKS_TIMER_DIV3_CLOCK     (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
-#define     AT91C_TC_CLKS_TIMER_DIV4_CLOCK     (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
-#define     AT91C_TC_CLKS_TIMER_DIV5_CLOCK     (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
-#define     AT91C_TC_CLKS_XC0                  (0x5) // (TC) Clock selected: XC0
-#define     AT91C_TC_CLKS_XC1                  (0x6) // (TC) Clock selected: XC1
-#define     AT91C_TC_CLKS_XC2                  (0x7) // (TC) Clock selected: XC2
-#define AT91C_TC_CLKI             (0x1 <<  3) // (TC) Clock Invert
-#define AT91C_TC_BURST            (0x3 <<  4) // (TC) Burst Signal Selection
-#define     AT91C_TC_BURST_NONE                 (0x0 <<  4) // (TC) The clock is not gated by an external signal
-#define     AT91C_TC_BURST_XC0                  (0x1 <<  4) // (TC) XC0 is ANDed with the selected clock
-#define     AT91C_TC_BURST_XC1                  (0x2 <<  4) // (TC) XC1 is ANDed with the selected clock
-#define     AT91C_TC_BURST_XC2                  (0x3 <<  4) // (TC) XC2 is ANDed with the selected clock
-#define AT91C_TC_CPCSTOP          (0x1 <<  6) // (TC) Counter Clock Stopped with RC Compare
-#define AT91C_TC_LDBSTOP          (0x1 <<  6) // (TC) Counter Clock Stopped with RB Loading
-#define AT91C_TC_CPCDIS           (0x1 <<  7) // (TC) Counter Clock Disable with RC Compare
-#define AT91C_TC_LDBDIS           (0x1 <<  7) // (TC) Counter Clock Disabled with RB Loading
-#define AT91C_TC_ETRGEDG          (0x3 <<  8) // (TC) External Trigger Edge Selection
-#define     AT91C_TC_ETRGEDG_NONE                 (0x0 <<  8) // (TC) Edge: None
-#define     AT91C_TC_ETRGEDG_RISING               (0x1 <<  8) // (TC) Edge: rising edge
-#define     AT91C_TC_ETRGEDG_FALLING              (0x2 <<  8) // (TC) Edge: falling edge
-#define     AT91C_TC_ETRGEDG_BOTH                 (0x3 <<  8) // (TC) Edge: each edge
-#define AT91C_TC_EEVTEDG          (0x3 <<  8) // (TC) External Event Edge Selection
-#define     AT91C_TC_EEVTEDG_NONE                 (0x0 <<  8) // (TC) Edge: None
-#define     AT91C_TC_EEVTEDG_RISING               (0x1 <<  8) // (TC) Edge: rising edge
-#define     AT91C_TC_EEVTEDG_FALLING              (0x2 <<  8) // (TC) Edge: falling edge
-#define     AT91C_TC_EEVTEDG_BOTH                 (0x3 <<  8) // (TC) Edge: each edge
-#define AT91C_TC_EEVT             (0x3 << 10) // (TC) External Event  Selection
-#define     AT91C_TC_EEVT_TIOB                 (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
-#define     AT91C_TC_EEVT_XC0                  (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
-#define     AT91C_TC_EEVT_XC1                  (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
-#define     AT91C_TC_EEVT_XC2                  (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
-#define AT91C_TC_ABETRG           (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
-#define AT91C_TC_ENETRG           (0x1 << 12) // (TC) External Event Trigger enable
-#define AT91C_TC_WAVESEL          (0x3 << 13) // (TC) Waveform  Selection
-#define     AT91C_TC_WAVESEL_UP                   (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
-#define     AT91C_TC_WAVESEL_UPDOWN               (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
-#define     AT91C_TC_WAVESEL_UP_AUTO              (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
-#define     AT91C_TC_WAVESEL_UPDOWN_AUTO          (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
-#define AT91C_TC_CPCTRG           (0x1 << 14) // (TC) RC Compare Trigger Enable
-#define AT91C_TC_WAVE             (0x1 << 15) // (TC)
-#define AT91C_TC_ACPA             (0x3 << 16) // (TC) RA Compare Effect on TIOA
-#define     AT91C_TC_ACPA_NONE                 (0x0 << 16) // (TC) Effect: none
-#define     AT91C_TC_ACPA_SET                  (0x1 << 16) // (TC) Effect: set
-#define     AT91C_TC_ACPA_CLEAR                (0x2 << 16) // (TC) Effect: clear
-#define     AT91C_TC_ACPA_TOGGLE               (0x3 << 16) // (TC) Effect: toggle
-#define AT91C_TC_LDRA             (0x3 << 16) // (TC) RA Loading Selection
-#define     AT91C_TC_LDRA_NONE                 (0x0 << 16) // (TC) Edge: None
-#define     AT91C_TC_LDRA_RISING               (0x1 << 16) // (TC) Edge: rising edge of TIOA
-#define     AT91C_TC_LDRA_FALLING              (0x2 << 16) // (TC) Edge: falling edge of TIOA
-#define     AT91C_TC_LDRA_BOTH                 (0x3 << 16) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_ACPC             (0x3 << 18) // (TC) RC Compare Effect on TIOA
-#define     AT91C_TC_ACPC_NONE                 (0x0 << 18) // (TC) Effect: none
-#define     AT91C_TC_ACPC_SET                  (0x1 << 18) // (TC) Effect: set
-#define     AT91C_TC_ACPC_CLEAR                (0x2 << 18) // (TC) Effect: clear
-#define     AT91C_TC_ACPC_TOGGLE               (0x3 << 18) // (TC) Effect: toggle
-#define AT91C_TC_LDRB             (0x3 << 18) // (TC) RB Loading Selection
-#define     AT91C_TC_LDRB_NONE                 (0x0 << 18) // (TC) Edge: None
-#define     AT91C_TC_LDRB_RISING               (0x1 << 18) // (TC) Edge: rising edge of TIOA
-#define     AT91C_TC_LDRB_FALLING              (0x2 << 18) // (TC) Edge: falling edge of TIOA
-#define     AT91C_TC_LDRB_BOTH                 (0x3 << 18) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_AEEVT            (0x3 << 20) // (TC) External Event Effect on TIOA
-#define     AT91C_TC_AEEVT_NONE                 (0x0 << 20) // (TC) Effect: none
-#define     AT91C_TC_AEEVT_SET                  (0x1 << 20) // (TC) Effect: set
-#define     AT91C_TC_AEEVT_CLEAR                (0x2 << 20) // (TC) Effect: clear
-#define     AT91C_TC_AEEVT_TOGGLE               (0x3 << 20) // (TC) Effect: toggle
-#define AT91C_TC_ASWTRG           (0x3 << 22) // (TC) Software Trigger Effect on TIOA
-#define     AT91C_TC_ASWTRG_NONE                 (0x0 << 22) // (TC) Effect: none
-#define     AT91C_TC_ASWTRG_SET                  (0x1 << 22) // (TC) Effect: set
-#define     AT91C_TC_ASWTRG_CLEAR                (0x2 << 22) // (TC) Effect: clear
-#define     AT91C_TC_ASWTRG_TOGGLE               (0x3 << 22) // (TC) Effect: toggle
-#define AT91C_TC_BCPB             (0x3 << 24) // (TC) RB Compare Effect on TIOB
-#define     AT91C_TC_BCPB_NONE                 (0x0 << 24) // (TC) Effect: none
-#define     AT91C_TC_BCPB_SET                  (0x1 << 24) // (TC) Effect: set
-#define     AT91C_TC_BCPB_CLEAR                (0x2 << 24) // (TC) Effect: clear
-#define     AT91C_TC_BCPB_TOGGLE               (0x3 << 24) // (TC) Effect: toggle
-#define AT91C_TC_BCPC             (0x3 << 26) // (TC) RC Compare Effect on TIOB
-#define     AT91C_TC_BCPC_NONE                 (0x0 << 26) // (TC) Effect: none
-#define     AT91C_TC_BCPC_SET                  (0x1 << 26) // (TC) Effect: set
-#define     AT91C_TC_BCPC_CLEAR                (0x2 << 26) // (TC) Effect: clear
-#define     AT91C_TC_BCPC_TOGGLE               (0x3 << 26) // (TC) Effect: toggle
-#define AT91C_TC_BEEVT            (0x3 << 28) // (TC) External Event Effect on TIOB
-#define     AT91C_TC_BEEVT_NONE                 (0x0 << 28) // (TC) Effect: none
-#define     AT91C_TC_BEEVT_SET                  (0x1 << 28) // (TC) Effect: set
-#define     AT91C_TC_BEEVT_CLEAR                (0x2 << 28) // (TC) Effect: clear
-#define     AT91C_TC_BEEVT_TOGGLE               (0x3 << 28) // (TC) Effect: toggle
-#define AT91C_TC_BSWTRG           (0x3 << 30) // (TC) Software Trigger Effect on TIOB
-#define     AT91C_TC_BSWTRG_NONE                 (0x0 << 30) // (TC) Effect: none
-#define     AT91C_TC_BSWTRG_SET                  (0x1 << 30) // (TC) Effect: set
-#define     AT91C_TC_BSWTRG_CLEAR                (0x2 << 30) // (TC) Effect: clear
-#define     AT91C_TC_BSWTRG_TOGGLE               (0x3 << 30) // (TC) Effect: toggle
-// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
-#define AT91C_TC_COVFS            (0x1 <<  0) // (TC) Counter Overflow
-#define AT91C_TC_LOVRS            (0x1 <<  1) // (TC) Load Overrun
-#define AT91C_TC_CPAS             (0x1 <<  2) // (TC) RA Compare
-#define AT91C_TC_CPBS             (0x1 <<  3) // (TC) RB Compare
-#define AT91C_TC_CPCS             (0x1 <<  4) // (TC) RC Compare
-#define AT91C_TC_LDRAS            (0x1 <<  5) // (TC) RA Loading
-#define AT91C_TC_LDRBS            (0x1 <<  6) // (TC) RB Loading
-#define AT91C_TC_ETRGS            (0x1 <<  7) // (TC) External Trigger
-#define AT91C_TC_CLKSTA           (0x1 << 16) // (TC) Clock Enabling
-#define AT91C_TC_MTIOA            (0x1 << 17) // (TC) TIOA Mirror
-#define AT91C_TC_MTIOB            (0x1 << 18) // (TC) TIOA Mirror
-// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
-// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
-// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_TC structure *** */
+#define TC_CCR                                ( 0 )         /* Channel Control Register */
+#define TC_CMR                                ( 4 )         /* Channel Mode Register (Capture Mode / Waveform Mode) */
+#define TC_CV                                 ( 16 )        /* Counter Value */
+#define TC_RA                                 ( 20 )        /* Register A */
+#define TC_RB                                 ( 24 )        /* Register B */
+#define TC_RC                                 ( 28 )        /* Register C */
+#define TC_SR                                 ( 32 )        /* Status Register */
+#define TC_IER                                ( 36 )        /* Interrupt Enable Register */
+#define TC_IDR                                ( 40 )        /* Interrupt Disable Register */
+#define TC_IMR                                ( 44 )        /* Interrupt Mask Register */
+/* -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- */
+#define AT91C_TC_CLKEN                        ( 0x1 << 0 )  /* (TC) Counter Clock Enable Command */
+#define AT91C_TC_CLKDIS                       ( 0x1 << 1 )  /* (TC) Counter Clock Disable Command */
+#define AT91C_TC_SWTRG                        ( 0x1 << 2 )  /* (TC) Software Trigger Command */
+/* -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- */
+#define AT91C_TC_CLKS                         ( 0x7 << 0 )  /* (TC) Clock Selection */
+#define     AT91C_TC_CLKS_TIMER_DIV1_CLOCK    ( 0x0 )       /* (TC) Clock selected: TIMER_DIV1_CLOCK */
+#define     AT91C_TC_CLKS_TIMER_DIV2_CLOCK    ( 0x1 )       /* (TC) Clock selected: TIMER_DIV2_CLOCK */
+#define     AT91C_TC_CLKS_TIMER_DIV3_CLOCK    ( 0x2 )       /* (TC) Clock selected: TIMER_DIV3_CLOCK */
+#define     AT91C_TC_CLKS_TIMER_DIV4_CLOCK    ( 0x3 )       /* (TC) Clock selected: TIMER_DIV4_CLOCK */
+#define     AT91C_TC_CLKS_TIMER_DIV5_CLOCK    ( 0x4 )       /* (TC) Clock selected: TIMER_DIV5_CLOCK */
+#define     AT91C_TC_CLKS_XC0                 ( 0x5 )       /* (TC) Clock selected: XC0 */
+#define     AT91C_TC_CLKS_XC1                 ( 0x6 )       /* (TC) Clock selected: XC1 */
+#define     AT91C_TC_CLKS_XC2                 ( 0x7 )       /* (TC) Clock selected: XC2 */
+#define AT91C_TC_CLKI                         ( 0x1 << 3 )  /* (TC) Clock Invert */
+#define AT91C_TC_BURST                        ( 0x3 << 4 )  /* (TC) Burst Signal Selection */
+#define     AT91C_TC_BURST_NONE               ( 0x0 << 4 )  /* (TC) The clock is not gated by an external signal */
+#define     AT91C_TC_BURST_XC0                ( 0x1 << 4 )  /* (TC) XC0 is ANDed with the selected clock */
+#define     AT91C_TC_BURST_XC1                ( 0x2 << 4 )  /* (TC) XC1 is ANDed with the selected clock */
+#define     AT91C_TC_BURST_XC2                ( 0x3 << 4 )  /* (TC) XC2 is ANDed with the selected clock */
+#define AT91C_TC_CPCSTOP                      ( 0x1 << 6 )  /* (TC) Counter Clock Stopped with RC Compare */
+#define AT91C_TC_LDBSTOP                      ( 0x1 << 6 )  /* (TC) Counter Clock Stopped with RB Loading */
+#define AT91C_TC_CPCDIS                       ( 0x1 << 7 )  /* (TC) Counter Clock Disable with RC Compare */
+#define AT91C_TC_LDBDIS                       ( 0x1 << 7 )  /* (TC) Counter Clock Disabled with RB Loading */
+#define AT91C_TC_ETRGEDG                      ( 0x3 << 8 )  /* (TC) External Trigger Edge Selection */
+#define     AT91C_TC_ETRGEDG_NONE             ( 0x0 << 8 )  /* (TC) Edge: None */
+#define     AT91C_TC_ETRGEDG_RISING           ( 0x1 << 8 )  /* (TC) Edge: rising edge */
+#define     AT91C_TC_ETRGEDG_FALLING          ( 0x2 << 8 )  /* (TC) Edge: falling edge */
+#define     AT91C_TC_ETRGEDG_BOTH             ( 0x3 << 8 )  /* (TC) Edge: each edge */
+#define AT91C_TC_EEVTEDG                      ( 0x3 << 8 )  /* (TC) External Event Edge Selection */
+#define     AT91C_TC_EEVTEDG_NONE             ( 0x0 << 8 )  /* (TC) Edge: None */
+#define     AT91C_TC_EEVTEDG_RISING           ( 0x1 << 8 )  /* (TC) Edge: rising edge */
+#define     AT91C_TC_EEVTEDG_FALLING          ( 0x2 << 8 )  /* (TC) Edge: falling edge */
+#define     AT91C_TC_EEVTEDG_BOTH             ( 0x3 << 8 )  /* (TC) Edge: each edge */
+#define AT91C_TC_EEVT                         ( 0x3 << 10 ) /* (TC) External Event  Selection */
+#define     AT91C_TC_EEVT_TIOB                ( 0x0 << 10 ) /* (TC) Signal selected as external event: TIOB TIOB direction: input */
+#define     AT91C_TC_EEVT_XC0                 ( 0x1 << 10 ) /* (TC) Signal selected as external event: XC0 TIOB direction: output */
+#define     AT91C_TC_EEVT_XC1                 ( 0x2 << 10 ) /* (TC) Signal selected as external event: XC1 TIOB direction: output */
+#define     AT91C_TC_EEVT_XC2                 ( 0x3 << 10 ) /* (TC) Signal selected as external event: XC2 TIOB direction: output */
+#define AT91C_TC_ABETRG                       ( 0x1 << 10 ) /* (TC) TIOA or TIOB External Trigger Selection */
+#define AT91C_TC_ENETRG                       ( 0x1 << 12 ) /* (TC) External Event Trigger enable */
+#define AT91C_TC_WAVESEL                      ( 0x3 << 13 ) /* (TC) Waveform  Selection */
+#define     AT91C_TC_WAVESEL_UP               ( 0x0 << 13 ) /* (TC) UP mode without atomatic trigger on RC Compare */
+#define     AT91C_TC_WAVESEL_UPDOWN           ( 0x1 << 13 ) /* (TC) UPDOWN mode without automatic trigger on RC Compare */
+#define     AT91C_TC_WAVESEL_UP_AUTO          ( 0x2 << 13 ) /* (TC) UP mode with automatic trigger on RC Compare */
+#define     AT91C_TC_WAVESEL_UPDOWN_AUTO      ( 0x3 << 13 ) /* (TC) UPDOWN mode with automatic trigger on RC Compare */
+#define AT91C_TC_CPCTRG                       ( 0x1 << 14 ) /* (TC) RC Compare Trigger Enable */
+#define AT91C_TC_WAVE                         ( 0x1 << 15 ) /* (TC) */
+#define AT91C_TC_ACPA                         ( 0x3 << 16 ) /* (TC) RA Compare Effect on TIOA */
+#define     AT91C_TC_ACPA_NONE                ( 0x0 << 16 ) /* (TC) Effect: none */
+#define     AT91C_TC_ACPA_SET                 ( 0x1 << 16 ) /* (TC) Effect: set */
+#define     AT91C_TC_ACPA_CLEAR               ( 0x2 << 16 ) /* (TC) Effect: clear */
+#define     AT91C_TC_ACPA_TOGGLE              ( 0x3 << 16 ) /* (TC) Effect: toggle */
+#define AT91C_TC_LDRA                         ( 0x3 << 16 ) /* (TC) RA Loading Selection */
+#define     AT91C_TC_LDRA_NONE                ( 0x0 << 16 ) /* (TC) Edge: None */
+#define     AT91C_TC_LDRA_RISING              ( 0x1 << 16 ) /* (TC) Edge: rising edge of TIOA */
+#define     AT91C_TC_LDRA_FALLING             ( 0x2 << 16 ) /* (TC) Edge: falling edge of TIOA */
+#define     AT91C_TC_LDRA_BOTH                ( 0x3 << 16 ) /* (TC) Edge: each edge of TIOA */
+#define AT91C_TC_ACPC                         ( 0x3 << 18 ) /* (TC) RC Compare Effect on TIOA */
+#define     AT91C_TC_ACPC_NONE                ( 0x0 << 18 ) /* (TC) Effect: none */
+#define     AT91C_TC_ACPC_SET                 ( 0x1 << 18 ) /* (TC) Effect: set */
+#define     AT91C_TC_ACPC_CLEAR               ( 0x2 << 18 ) /* (TC) Effect: clear */
+#define     AT91C_TC_ACPC_TOGGLE              ( 0x3 << 18 ) /* (TC) Effect: toggle */
+#define AT91C_TC_LDRB                         ( 0x3 << 18 ) /* (TC) RB Loading Selection */
+#define     AT91C_TC_LDRB_NONE                ( 0x0 << 18 ) /* (TC) Edge: None */
+#define     AT91C_TC_LDRB_RISING              ( 0x1 << 18 ) /* (TC) Edge: rising edge of TIOA */
+#define     AT91C_TC_LDRB_FALLING             ( 0x2 << 18 ) /* (TC) Edge: falling edge of TIOA */
+#define     AT91C_TC_LDRB_BOTH                ( 0x3 << 18 ) /* (TC) Edge: each edge of TIOA */
+#define AT91C_TC_AEEVT                        ( 0x3 << 20 ) /* (TC) External Event Effect on TIOA */
+#define     AT91C_TC_AEEVT_NONE               ( 0x0 << 20 ) /* (TC) Effect: none */
+#define     AT91C_TC_AEEVT_SET                ( 0x1 << 20 ) /* (TC) Effect: set */
+#define     AT91C_TC_AEEVT_CLEAR              ( 0x2 << 20 ) /* (TC) Effect: clear */
+#define     AT91C_TC_AEEVT_TOGGLE             ( 0x3 << 20 ) /* (TC) Effect: toggle */
+#define AT91C_TC_ASWTRG                       ( 0x3 << 22 ) /* (TC) Software Trigger Effect on TIOA */
+#define     AT91C_TC_ASWTRG_NONE              ( 0x0 << 22 ) /* (TC) Effect: none */
+#define     AT91C_TC_ASWTRG_SET               ( 0x1 << 22 ) /* (TC) Effect: set */
+#define     AT91C_TC_ASWTRG_CLEAR             ( 0x2 << 22 ) /* (TC) Effect: clear */
+#define     AT91C_TC_ASWTRG_TOGGLE            ( 0x3 << 22 ) /* (TC) Effect: toggle */
+#define AT91C_TC_BCPB                         ( 0x3 << 24 ) /* (TC) RB Compare Effect on TIOB */
+#define     AT91C_TC_BCPB_NONE                ( 0x0 << 24 ) /* (TC) Effect: none */
+#define     AT91C_TC_BCPB_SET                 ( 0x1 << 24 ) /* (TC) Effect: set */
+#define     AT91C_TC_BCPB_CLEAR               ( 0x2 << 24 ) /* (TC) Effect: clear */
+#define     AT91C_TC_BCPB_TOGGLE              ( 0x3 << 24 ) /* (TC) Effect: toggle */
+#define AT91C_TC_BCPC                         ( 0x3 << 26 ) /* (TC) RC Compare Effect on TIOB */
+#define     AT91C_TC_BCPC_NONE                ( 0x0 << 26 ) /* (TC) Effect: none */
+#define     AT91C_TC_BCPC_SET                 ( 0x1 << 26 ) /* (TC) Effect: set */
+#define     AT91C_TC_BCPC_CLEAR               ( 0x2 << 26 ) /* (TC) Effect: clear */
+#define     AT91C_TC_BCPC_TOGGLE              ( 0x3 << 26 ) /* (TC) Effect: toggle */
+#define AT91C_TC_BEEVT                        ( 0x3 << 28 ) /* (TC) External Event Effect on TIOB */
+#define     AT91C_TC_BEEVT_NONE               ( 0x0 << 28 ) /* (TC) Effect: none */
+#define     AT91C_TC_BEEVT_SET                ( 0x1 << 28 ) /* (TC) Effect: set */
+#define     AT91C_TC_BEEVT_CLEAR              ( 0x2 << 28 ) /* (TC) Effect: clear */
+#define     AT91C_TC_BEEVT_TOGGLE             ( 0x3 << 28 ) /* (TC) Effect: toggle */
+#define AT91C_TC_BSWTRG                       ( 0x3 << 30 ) /* (TC) Software Trigger Effect on TIOB */
+#define     AT91C_TC_BSWTRG_NONE              ( 0x0 << 30 ) /* (TC) Effect: none */
+#define     AT91C_TC_BSWTRG_SET               ( 0x1 << 30 ) /* (TC) Effect: set */
+#define     AT91C_TC_BSWTRG_CLEAR             ( 0x2 << 30 ) /* (TC) Effect: clear */
+#define     AT91C_TC_BSWTRG_TOGGLE            ( 0x3 << 30 ) /* (TC) Effect: toggle */
+/* -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- */
+#define AT91C_TC_COVFS                        ( 0x1 << 0 )  /* (TC) Counter Overflow */
+#define AT91C_TC_LOVRS                        ( 0x1 << 1 )  /* (TC) Load Overrun */
+#define AT91C_TC_CPAS                         ( 0x1 << 2 )  /* (TC) RA Compare */
+#define AT91C_TC_CPBS                         ( 0x1 << 3 )  /* (TC) RB Compare */
+#define AT91C_TC_CPCS                         ( 0x1 << 4 )  /* (TC) RC Compare */
+#define AT91C_TC_LDRAS                        ( 0x1 << 5 )  /* (TC) RA Loading */
+#define AT91C_TC_LDRBS                        ( 0x1 << 6 )  /* (TC) RB Loading */
+#define AT91C_TC_ETRGS                        ( 0x1 << 7 )  /* (TC) External Trigger */
+#define AT91C_TC_CLKSTA                       ( 0x1 << 16 ) /* (TC) Clock Enabling */
+#define AT91C_TC_MTIOA                        ( 0x1 << 17 ) /* (TC) TIOA Mirror */
+#define AT91C_TC_MTIOB                        ( 0x1 << 18 ) /* (TC) TIOA Mirror */
+/* -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- */
+/* -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- */
+/* -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Timer Counter Interface
-// *****************************************************************************
-// *** Register offset in AT91S_TCB structure ***
-#define TCB_TC0         ( 0) // TC Channel 0
-#define TCB_TC1         (64) // TC Channel 1
-#define TCB_TC2         (128) // TC Channel 2
-#define TCB_BCR         (192) // TC Block Control Register
-#define TCB_BMR         (196) // TC Block Mode Register
-// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
-#define AT91C_TCB_SYNC            (0x1 <<  0) // (TCB) Synchro Command
-// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
-#define AT91C_TCB_TC0XC0S         (0x3 <<  0) // (TCB) External Clock Signal 0 Selection
-#define     AT91C_TCB_TC0XC0S_TCLK0                (0x0) // (TCB) TCLK0 connected to XC0
-#define     AT91C_TCB_TC0XC0S_NONE                 (0x1) // (TCB) None signal connected to XC0
-#define     AT91C_TCB_TC0XC0S_TIOA1                (0x2) // (TCB) TIOA1 connected to XC0
-#define     AT91C_TCB_TC0XC0S_TIOA2                (0x3) // (TCB) TIOA2 connected to XC0
-#define AT91C_TCB_TC1XC1S         (0x3 <<  2) // (TCB) External Clock Signal 1 Selection
-#define     AT91C_TCB_TC1XC1S_TCLK1                (0x0 <<  2) // (TCB) TCLK1 connected to XC1
-#define     AT91C_TCB_TC1XC1S_NONE                 (0x1 <<  2) // (TCB) None signal connected to XC1
-#define     AT91C_TCB_TC1XC1S_TIOA0                (0x2 <<  2) // (TCB) TIOA0 connected to XC1
-#define     AT91C_TCB_TC1XC1S_TIOA2                (0x3 <<  2) // (TCB) TIOA2 connected to XC1
-#define AT91C_TCB_TC2XC2S         (0x3 <<  4) // (TCB) External Clock Signal 2 Selection
-#define     AT91C_TCB_TC2XC2S_TCLK2                (0x0 <<  4) // (TCB) TCLK2 connected to XC2
-#define     AT91C_TCB_TC2XC2S_NONE                 (0x1 <<  4) // (TCB) None signal connected to XC2
-#define     AT91C_TCB_TC2XC2S_TIOA0                (0x2 <<  4) // (TCB) TIOA0 connected to XC2
-#define     AT91C_TCB_TC2XC2S_TIOA1                (0x3 <<  4) // (TCB) TIOA2 connected to XC2
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Timer Counter Interface */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_TCB structure *** */
+#define TCB_TC0                        ( 0 )        /* TC Channel 0 */
+#define TCB_TC1                        ( 64 )       /* TC Channel 1 */
+#define TCB_TC2                        ( 128 )      /* TC Channel 2 */
+#define TCB_BCR                        ( 192 )      /* TC Block Control Register */
+#define TCB_BMR                        ( 196 )      /* TC Block Mode Register */
+/* -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- */
+#define AT91C_TCB_SYNC                 ( 0x1 << 0 ) /* (TCB) Synchro Command */
+/* -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- */
+#define AT91C_TCB_TC0XC0S              ( 0x3 << 0 ) /* (TCB) External Clock Signal 0 Selection */
+#define     AT91C_TCB_TC0XC0S_TCLK0    ( 0x0 )      /* (TCB) TCLK0 connected to XC0 */
+#define     AT91C_TCB_TC0XC0S_NONE     ( 0x1 )      /* (TCB) None signal connected to XC0 */
+#define     AT91C_TCB_TC0XC0S_TIOA1    ( 0x2 )      /* (TCB) TIOA1 connected to XC0 */
+#define     AT91C_TCB_TC0XC0S_TIOA2    ( 0x3 )      /* (TCB) TIOA2 connected to XC0 */
+#define AT91C_TCB_TC1XC1S              ( 0x3 << 2 ) /* (TCB) External Clock Signal 1 Selection */
+#define     AT91C_TCB_TC1XC1S_TCLK1    ( 0x0 << 2 ) /* (TCB) TCLK1 connected to XC1 */
+#define     AT91C_TCB_TC1XC1S_NONE     ( 0x1 << 2 ) /* (TCB) None signal connected to XC1 */
+#define     AT91C_TCB_TC1XC1S_TIOA0    ( 0x2 << 2 ) /* (TCB) TIOA0 connected to XC1 */
+#define     AT91C_TCB_TC1XC1S_TIOA2    ( 0x3 << 2 ) /* (TCB) TIOA2 connected to XC1 */
+#define AT91C_TCB_TC2XC2S              ( 0x3 << 4 ) /* (TCB) External Clock Signal 2 Selection */
+#define     AT91C_TCB_TC2XC2S_TCLK2    ( 0x0 << 4 ) /* (TCB) TCLK2 connected to XC2 */
+#define     AT91C_TCB_TC2XC2S_NONE     ( 0x1 << 4 ) /* (TCB) None signal connected to XC2 */
+#define     AT91C_TCB_TC2XC2S_TIOA0    ( 0x2 << 4 ) /* (TCB) TIOA0 connected to XC2 */
+#define     AT91C_TCB_TC2XC2S_TIOA1    ( 0x3 << 4 ) /* (TCB) TIOA2 connected to XC2 */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Control Area Network MailBox Interface
-// *****************************************************************************
-// *** Register offset in AT91S_CAN_MB structure ***
-#define CAN_MB_MMR      ( 0) // MailBox Mode Register
-#define CAN_MB_MAM      ( 4) // MailBox Acceptance Mask Register
-#define CAN_MB_MID      ( 8) // MailBox ID Register
-#define CAN_MB_MFID     (12) // MailBox Family ID Register
-#define CAN_MB_MSR      (16) // MailBox Status Register
-#define CAN_MB_MDL      (20) // MailBox Data Low Register
-#define CAN_MB_MDH      (24) // MailBox Data High Register
-#define CAN_MB_MCR      (28) // MailBox Control Register
-// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register --------
-#define AT91C_CAN_MTIMEMARK       (0xFFFF <<  0) // (CAN_MB) Mailbox Timemark
-#define AT91C_CAN_PRIOR           (0xF << 16) // (CAN_MB) Mailbox Priority
-#define AT91C_CAN_MOT             (0x7 << 24) // (CAN_MB) Mailbox Object Type
-#define     AT91C_CAN_MOT_DIS                  (0x0 << 24) // (CAN_MB)
-#define     AT91C_CAN_MOT_RX                   (0x1 << 24) // (CAN_MB)
-#define     AT91C_CAN_MOT_RXOVERWRITE          (0x2 << 24) // (CAN_MB)
-#define     AT91C_CAN_MOT_TX                   (0x3 << 24) // (CAN_MB)
-#define     AT91C_CAN_MOT_CONSUMER             (0x4 << 24) // (CAN_MB)
-#define     AT91C_CAN_MOT_PRODUCER             (0x5 << 24) // (CAN_MB)
-// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register --------
-#define AT91C_CAN_MIDvB           (0x3FFFF <<  0) // (CAN_MB) Complementary bits for identifier in extended mode
-#define AT91C_CAN_MIDvA           (0x7FF << 18) // (CAN_MB) Identifier for standard frame mode
-#define AT91C_CAN_MIDE            (0x1 << 29) // (CAN_MB) Identifier Version
-// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register --------
-// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register --------
-// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register --------
-#define AT91C_CAN_MTIMESTAMP      (0xFFFF <<  0) // (CAN_MB) Timer Value
-#define AT91C_CAN_MDLC            (0xF << 16) // (CAN_MB) Mailbox Data Length Code
-#define AT91C_CAN_MRTR            (0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request
-#define AT91C_CAN_MABT            (0x1 << 22) // (CAN_MB) Mailbox Message Abort
-#define AT91C_CAN_MRDY            (0x1 << 23) // (CAN_MB) Mailbox Ready
-#define AT91C_CAN_MMI             (0x1 << 24) // (CAN_MB) Mailbox Message Ignored
-// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register --------
-// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register --------
-// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register --------
-#define AT91C_CAN_MACR            (0x1 << 22) // (CAN_MB) Abort Request for Mailbox
-#define AT91C_CAN_MTCR            (0x1 << 23) // (CAN_MB) Mailbox Transfer Command
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Control Area Network MailBox Interface */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_CAN_MB structure *** */
+#define CAN_MB_MMR                       ( 0 )            /* MailBox Mode Register */
+#define CAN_MB_MAM                       ( 4 )            /* MailBox Acceptance Mask Register */
+#define CAN_MB_MID                       ( 8 )            /* MailBox ID Register */
+#define CAN_MB_MFID                      ( 12 )           /* MailBox Family ID Register */
+#define CAN_MB_MSR                       ( 16 )           /* MailBox Status Register */
+#define CAN_MB_MDL                       ( 20 )           /* MailBox Data Low Register */
+#define CAN_MB_MDH                       ( 24 )           /* MailBox Data High Register */
+#define CAN_MB_MCR                       ( 28 )           /* MailBox Control Register */
+/* -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- */
+#define AT91C_CAN_MTIMEMARK              ( 0xFFFF << 0 )  /* (CAN_MB) Mailbox Timemark */
+#define AT91C_CAN_PRIOR                  ( 0xF << 16 )    /* (CAN_MB) Mailbox Priority */
+#define AT91C_CAN_MOT                    ( 0x7 << 24 )    /* (CAN_MB) Mailbox Object Type */
+#define     AT91C_CAN_MOT_DIS            ( 0x0 << 24 )    /* (CAN_MB) */
+#define     AT91C_CAN_MOT_RX             ( 0x1 << 24 )    /* (CAN_MB) */
+#define     AT91C_CAN_MOT_RXOVERWRITE    ( 0x2 << 24 )    /* (CAN_MB) */
+#define     AT91C_CAN_MOT_TX             ( 0x3 << 24 )    /* (CAN_MB) */
+#define     AT91C_CAN_MOT_CONSUMER       ( 0x4 << 24 )    /* (CAN_MB) */
+#define     AT91C_CAN_MOT_PRODUCER       ( 0x5 << 24 )    /* (CAN_MB) */
+/* -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- */
+#define AT91C_CAN_MIDvB                  ( 0x3FFFF << 0 ) /* (CAN_MB) Complementary bits for identifier in extended mode */
+#define AT91C_CAN_MIDvA                  ( 0x7FF << 18 )  /* (CAN_MB) Identifier for standard frame mode */
+#define AT91C_CAN_MIDE                   ( 0x1 << 29 )    /* (CAN_MB) Identifier Version */
+/* -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- */
+/* -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- */
+/* -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- */
+#define AT91C_CAN_MTIMESTAMP    ( 0xFFFF << 0 ) /* (CAN_MB) Timer Value */
+#define AT91C_CAN_MDLC          ( 0xF << 16 )   /* (CAN_MB) Mailbox Data Length Code */
+#define AT91C_CAN_MRTR          ( 0x1 << 20 )   /* (CAN_MB) Mailbox Remote Transmission Request */
+#define AT91C_CAN_MABT          ( 0x1 << 22 )   /* (CAN_MB) Mailbox Message Abort */
+#define AT91C_CAN_MRDY          ( 0x1 << 23 )   /* (CAN_MB) Mailbox Ready */
+#define AT91C_CAN_MMI           ( 0x1 << 24 )   /* (CAN_MB) Mailbox Message Ignored */
+/* -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- */
+/* -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- */
+/* -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- */
+#define AT91C_CAN_MACR    ( 0x1 << 22 )       /* (CAN_MB) Abort Request for Mailbox */
+#define AT91C_CAN_MTCR    ( 0x1 << 23 )       /* (CAN_MB) Mailbox Transfer Command */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Control Area Network Interface
-// *****************************************************************************
-// *** Register offset in AT91S_CAN structure ***
-#define CAN_MR          ( 0) // Mode Register
-#define CAN_IER         ( 4) // Interrupt Enable Register
-#define CAN_IDR         ( 8) // Interrupt Disable Register
-#define CAN_IMR         (12) // Interrupt Mask Register
-#define CAN_SR          (16) // Status Register
-#define CAN_BR          (20) // Baudrate Register
-#define CAN_TIM         (24) // Timer Register
-#define CAN_TIMESTP     (28) // Time Stamp Register
-#define CAN_ECR         (32) // Error Counter Register
-#define CAN_TCR         (36) // Transfer Command Register
-#define CAN_ACR         (40) // Abort Command Register
-#define CAN_VR          (252) // Version Register
-#define CAN_MB0         (512) // CAN Mailbox 0
-#define CAN_MB1         (544) // CAN Mailbox 1
-#define CAN_MB2         (576) // CAN Mailbox 2
-#define CAN_MB3         (608) // CAN Mailbox 3
-#define CAN_MB4         (640) // CAN Mailbox 4
-#define CAN_MB5         (672) // CAN Mailbox 5
-#define CAN_MB6         (704) // CAN Mailbox 6
-#define CAN_MB7         (736) // CAN Mailbox 7
-#define CAN_MB8         (768) // CAN Mailbox 8
-#define CAN_MB9         (800) // CAN Mailbox 9
-#define CAN_MB10        (832) // CAN Mailbox 10
-#define CAN_MB11        (864) // CAN Mailbox 11
-#define CAN_MB12        (896) // CAN Mailbox 12
-#define CAN_MB13        (928) // CAN Mailbox 13
-#define CAN_MB14        (960) // CAN Mailbox 14
-#define CAN_MB15        (992) // CAN Mailbox 15
-// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register --------
-#define AT91C_CAN_CANEN           (0x1 <<  0) // (CAN) CAN Controller Enable
-#define AT91C_CAN_LPM             (0x1 <<  1) // (CAN) Disable/Enable Low Power Mode
-#define AT91C_CAN_ABM             (0x1 <<  2) // (CAN) Disable/Enable Autobaud/Listen Mode
-#define AT91C_CAN_OVL             (0x1 <<  3) // (CAN) Disable/Enable Overload Frame
-#define AT91C_CAN_TEOF            (0x1 <<  4) // (CAN) Time Stamp messages at each end of Frame
-#define AT91C_CAN_TTM             (0x1 <<  5) // (CAN) Disable/Enable Time Trigger Mode
-#define AT91C_CAN_TIMFRZ          (0x1 <<  6) // (CAN) Enable Timer Freeze
-#define AT91C_CAN_DRPT            (0x1 <<  7) // (CAN) Disable Repeat
-// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register --------
-#define AT91C_CAN_MB0             (0x1 <<  0) // (CAN) Mailbox 0 Flag
-#define AT91C_CAN_MB1             (0x1 <<  1) // (CAN) Mailbox 1 Flag
-#define AT91C_CAN_MB2             (0x1 <<  2) // (CAN) Mailbox 2 Flag
-#define AT91C_CAN_MB3             (0x1 <<  3) // (CAN) Mailbox 3 Flag
-#define AT91C_CAN_MB4             (0x1 <<  4) // (CAN) Mailbox 4 Flag
-#define AT91C_CAN_MB5             (0x1 <<  5) // (CAN) Mailbox 5 Flag
-#define AT91C_CAN_MB6             (0x1 <<  6) // (CAN) Mailbox 6 Flag
-#define AT91C_CAN_MB7             (0x1 <<  7) // (CAN) Mailbox 7 Flag
-#define AT91C_CAN_MB8             (0x1 <<  8) // (CAN) Mailbox 8 Flag
-#define AT91C_CAN_MB9             (0x1 <<  9) // (CAN) Mailbox 9 Flag
-#define AT91C_CAN_MB10            (0x1 << 10) // (CAN) Mailbox 10 Flag
-#define AT91C_CAN_MB11            (0x1 << 11) // (CAN) Mailbox 11 Flag
-#define AT91C_CAN_MB12            (0x1 << 12) // (CAN) Mailbox 12 Flag
-#define AT91C_CAN_MB13            (0x1 << 13) // (CAN) Mailbox 13 Flag
-#define AT91C_CAN_MB14            (0x1 << 14) // (CAN) Mailbox 14 Flag
-#define AT91C_CAN_MB15            (0x1 << 15) // (CAN) Mailbox 15 Flag
-#define AT91C_CAN_ERRA            (0x1 << 16) // (CAN) Error Active Mode Flag
-#define AT91C_CAN_WARN            (0x1 << 17) // (CAN) Warning Limit Flag
-#define AT91C_CAN_ERRP            (0x1 << 18) // (CAN) Error Passive Mode Flag
-#define AT91C_CAN_BOFF            (0x1 << 19) // (CAN) Bus Off Mode Flag
-#define AT91C_CAN_SLEEP           (0x1 << 20) // (CAN) Sleep Flag
-#define AT91C_CAN_WAKEUP          (0x1 << 21) // (CAN) Wakeup Flag
-#define AT91C_CAN_TOVF            (0x1 << 22) // (CAN) Timer Overflow Flag
-#define AT91C_CAN_TSTP            (0x1 << 23) // (CAN) Timestamp Flag
-#define AT91C_CAN_CERR            (0x1 << 24) // (CAN) CRC Error
-#define AT91C_CAN_SERR            (0x1 << 25) // (CAN) Stuffing Error
-#define AT91C_CAN_AERR            (0x1 << 26) // (CAN) Acknowledgment Error
-#define AT91C_CAN_FERR            (0x1 << 27) // (CAN) Form Error
-#define AT91C_CAN_BERR            (0x1 << 28) // (CAN) Bit Error
-// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register --------
-// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register --------
-// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register --------
-#define AT91C_CAN_RBSY            (0x1 << 29) // (CAN) Receiver Busy
-#define AT91C_CAN_TBSY            (0x1 << 30) // (CAN) Transmitter Busy
-#define AT91C_CAN_OVLY            (0x1 << 31) // (CAN) Overload Busy
-// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register --------
-#define AT91C_CAN_PHASE2          (0x7 <<  0) // (CAN) Phase 2 segment
-#define AT91C_CAN_PHASE1          (0x7 <<  4) // (CAN) Phase 1 segment
-#define AT91C_CAN_PROPAG          (0x7 <<  8) // (CAN) Programmation time segment
-#define AT91C_CAN_SYNC            (0x3 << 12) // (CAN) Re-synchronization jump width segment
-#define AT91C_CAN_BRP             (0x7F << 16) // (CAN) Baudrate Prescaler
-#define AT91C_CAN_SMP             (0x1 << 24) // (CAN) Sampling mode
-// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register --------
-#define AT91C_CAN_TIMER           (0xFFFF <<  0) // (CAN) Timer field
-// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register --------
-// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register --------
-#define AT91C_CAN_REC             (0xFF <<  0) // (CAN) Receive Error Counter
-#define AT91C_CAN_TEC             (0xFF << 16) // (CAN) Transmit Error Counter
-// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register --------
-#define AT91C_CAN_TIMRST          (0x1 << 31) // (CAN) Timer Reset Field
-// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register --------
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Control Area Network Interface */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_CAN structure *** */
+#define CAN_MR              ( 0 )         /* Mode Register */
+#define CAN_IER             ( 4 )         /* Interrupt Enable Register */
+#define CAN_IDR             ( 8 )         /* Interrupt Disable Register */
+#define CAN_IMR             ( 12 )        /* Interrupt Mask Register */
+#define CAN_SR              ( 16 )        /* Status Register */
+#define CAN_BR              ( 20 )        /* Baudrate Register */
+#define CAN_TIM             ( 24 )        /* Timer Register */
+#define CAN_TIMESTP         ( 28 )        /* Time Stamp Register */
+#define CAN_ECR             ( 32 )        /* Error Counter Register */
+#define CAN_TCR             ( 36 )        /* Transfer Command Register */
+#define CAN_ACR             ( 40 )        /* Abort Command Register */
+#define CAN_VR              ( 252 )       /* Version Register */
+#define CAN_MB0             ( 512 )       /* CAN Mailbox 0 */
+#define CAN_MB1             ( 544 )       /* CAN Mailbox 1 */
+#define CAN_MB2             ( 576 )       /* CAN Mailbox 2 */
+#define CAN_MB3             ( 608 )       /* CAN Mailbox 3 */
+#define CAN_MB4             ( 640 )       /* CAN Mailbox 4 */
+#define CAN_MB5             ( 672 )       /* CAN Mailbox 5 */
+#define CAN_MB6             ( 704 )       /* CAN Mailbox 6 */
+#define CAN_MB7             ( 736 )       /* CAN Mailbox 7 */
+#define CAN_MB8             ( 768 )       /* CAN Mailbox 8 */
+#define CAN_MB9             ( 800 )       /* CAN Mailbox 9 */
+#define CAN_MB10            ( 832 )       /* CAN Mailbox 10 */
+#define CAN_MB11            ( 864 )       /* CAN Mailbox 11 */
+#define CAN_MB12            ( 896 )       /* CAN Mailbox 12 */
+#define CAN_MB13            ( 928 )       /* CAN Mailbox 13 */
+#define CAN_MB14            ( 960 )       /* CAN Mailbox 14 */
+#define CAN_MB15            ( 992 )       /* CAN Mailbox 15 */
+/* -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- */
+#define AT91C_CAN_CANEN     ( 0x1 << 0 )  /* (CAN) CAN Controller Enable */
+#define AT91C_CAN_LPM       ( 0x1 << 1 )  /* (CAN) Disable/Enable Low Power Mode */
+#define AT91C_CAN_ABM       ( 0x1 << 2 )  /* (CAN) Disable/Enable Autobaud/Listen Mode */
+#define AT91C_CAN_OVL       ( 0x1 << 3 )  /* (CAN) Disable/Enable Overload Frame */
+#define AT91C_CAN_TEOF      ( 0x1 << 4 )  /* (CAN) Time Stamp messages at each end of Frame */
+#define AT91C_CAN_TTM       ( 0x1 << 5 )  /* (CAN) Disable/Enable Time Trigger Mode */
+#define AT91C_CAN_TIMFRZ    ( 0x1 << 6 )  /* (CAN) Enable Timer Freeze */
+#define AT91C_CAN_DRPT      ( 0x1 << 7 )  /* (CAN) Disable Repeat */
+/* -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- */
+#define AT91C_CAN_MB0       ( 0x1 << 0 )  /* (CAN) Mailbox 0 Flag */
+#define AT91C_CAN_MB1       ( 0x1 << 1 )  /* (CAN) Mailbox 1 Flag */
+#define AT91C_CAN_MB2       ( 0x1 << 2 )  /* (CAN) Mailbox 2 Flag */
+#define AT91C_CAN_MB3       ( 0x1 << 3 )  /* (CAN) Mailbox 3 Flag */
+#define AT91C_CAN_MB4       ( 0x1 << 4 )  /* (CAN) Mailbox 4 Flag */
+#define AT91C_CAN_MB5       ( 0x1 << 5 )  /* (CAN) Mailbox 5 Flag */
+#define AT91C_CAN_MB6       ( 0x1 << 6 )  /* (CAN) Mailbox 6 Flag */
+#define AT91C_CAN_MB7       ( 0x1 << 7 )  /* (CAN) Mailbox 7 Flag */
+#define AT91C_CAN_MB8       ( 0x1 << 8 )  /* (CAN) Mailbox 8 Flag */
+#define AT91C_CAN_MB9       ( 0x1 << 9 )  /* (CAN) Mailbox 9 Flag */
+#define AT91C_CAN_MB10      ( 0x1 << 10 ) /* (CAN) Mailbox 10 Flag */
+#define AT91C_CAN_MB11      ( 0x1 << 11 ) /* (CAN) Mailbox 11 Flag */
+#define AT91C_CAN_MB12      ( 0x1 << 12 ) /* (CAN) Mailbox 12 Flag */
+#define AT91C_CAN_MB13      ( 0x1 << 13 ) /* (CAN) Mailbox 13 Flag */
+#define AT91C_CAN_MB14      ( 0x1 << 14 ) /* (CAN) Mailbox 14 Flag */
+#define AT91C_CAN_MB15      ( 0x1 << 15 ) /* (CAN) Mailbox 15 Flag */
+#define AT91C_CAN_ERRA      ( 0x1 << 16 ) /* (CAN) Error Active Mode Flag */
+#define AT91C_CAN_WARN      ( 0x1 << 17 ) /* (CAN) Warning Limit Flag */
+#define AT91C_CAN_ERRP      ( 0x1 << 18 ) /* (CAN) Error Passive Mode Flag */
+#define AT91C_CAN_BOFF      ( 0x1 << 19 ) /* (CAN) Bus Off Mode Flag */
+#define AT91C_CAN_SLEEP     ( 0x1 << 20 ) /* (CAN) Sleep Flag */
+#define AT91C_CAN_WAKEUP    ( 0x1 << 21 ) /* (CAN) Wakeup Flag */
+#define AT91C_CAN_TOVF      ( 0x1 << 22 ) /* (CAN) Timer Overflow Flag */
+#define AT91C_CAN_TSTP      ( 0x1 << 23 ) /* (CAN) Timestamp Flag */
+#define AT91C_CAN_CERR      ( 0x1 << 24 ) /* (CAN) CRC Error */
+#define AT91C_CAN_SERR      ( 0x1 << 25 ) /* (CAN) Stuffing Error */
+#define AT91C_CAN_AERR      ( 0x1 << 26 ) /* (CAN) Acknowledgment Error */
+#define AT91C_CAN_FERR      ( 0x1 << 27 ) /* (CAN) Form Error */
+#define AT91C_CAN_BERR      ( 0x1 << 28 ) /* (CAN) Bit Error */
+/* -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- */
+/* -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- */
+/* -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- */
+#define AT91C_CAN_RBSY      ( 0x1 << 29 )     /* (CAN) Receiver Busy */
+#define AT91C_CAN_TBSY      ( 0x1 << 30 )     /* (CAN) Transmitter Busy */
+#define AT91C_CAN_OVLY      ( 0x1 << 31 )     /* (CAN) Overload Busy */
+/* -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- */
+#define AT91C_CAN_PHASE2    ( 0x7 << 0 )      /* (CAN) Phase 2 segment */
+#define AT91C_CAN_PHASE1    ( 0x7 << 4 )      /* (CAN) Phase 1 segment */
+#define AT91C_CAN_PROPAG    ( 0x7 << 8 )      /* (CAN) Programmation time segment */
+#define AT91C_CAN_SYNC      ( 0x3 << 12 )     /* (CAN) Re-synchronization jump width segment */
+#define AT91C_CAN_BRP       ( 0x7F << 16 )    /* (CAN) Baudrate Prescaler */
+#define AT91C_CAN_SMP       ( 0x1 << 24 )     /* (CAN) Sampling mode */
+/* -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- */
+#define AT91C_CAN_TIMER     ( 0xFFFF << 0 )   /* (CAN) Timer field */
+/* -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- */
+/* -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- */
+#define AT91C_CAN_REC       ( 0xFF << 0 )     /* (CAN) Receive Error Counter */
+#define AT91C_CAN_TEC       ( 0xFF << 16 )    /* (CAN) Transmit Error Counter */
+/* -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- */
+#define AT91C_CAN_TIMRST    ( 0x1 << 31 )     /* (CAN) Timer Reset Field */
+/* -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Ethernet MAC 10/100
-// *****************************************************************************
-// *** Register offset in AT91S_EMAC structure ***
-#define EMAC_NCR        ( 0) // Network Control Register
-#define EMAC_NCFGR      ( 4) // Network Configuration Register
-#define EMAC_NSR        ( 8) // Network Status Register
-#define EMAC_TSR        (20) // Transmit Status Register
-#define EMAC_RBQP       (24) // Receive Buffer Queue Pointer
-#define EMAC_TBQP       (28) // Transmit Buffer Queue Pointer
-#define EMAC_RSR        (32) // Receive Status Register
-#define EMAC_ISR        (36) // Interrupt Status Register
-#define EMAC_IER        (40) // Interrupt Enable Register
-#define EMAC_IDR        (44) // Interrupt Disable Register
-#define EMAC_IMR        (48) // Interrupt Mask Register
-#define EMAC_MAN        (52) // PHY Maintenance Register
-#define EMAC_PTR        (56) // Pause Time Register
-#define EMAC_PFR        (60) // Pause Frames received Register
-#define EMAC_FTO        (64) // Frames Transmitted OK Register
-#define EMAC_SCF        (68) // Single Collision Frame Register
-#define EMAC_MCF        (72) // Multiple Collision Frame Register
-#define EMAC_FRO        (76) // Frames Received OK Register
-#define EMAC_FCSE       (80) // Frame Check Sequence Error Register
-#define EMAC_ALE        (84) // Alignment Error Register
-#define EMAC_DTF        (88) // Deferred Transmission Frame Register
-#define EMAC_LCOL       (92) // Late Collision Register
-#define EMAC_ECOL       (96) // Excessive Collision Register
-#define EMAC_TUND       (100) // Transmit Underrun Error Register
-#define EMAC_CSE        (104) // Carrier Sense Error Register
-#define EMAC_RRE        (108) // Receive Ressource Error Register
-#define EMAC_ROV        (112) // Receive Overrun Errors Register
-#define EMAC_RSE        (116) // Receive Symbol Errors Register
-#define EMAC_ELE        (120) // Excessive Length Errors Register
-#define EMAC_RJA        (124) // Receive Jabbers Register
-#define EMAC_USF        (128) // Undersize Frames Register
-#define EMAC_STE        (132) // SQE Test Error Register
-#define EMAC_RLE        (136) // Receive Length Field Mismatch Register
-#define EMAC_TPF        (140) // Transmitted Pause Frames Register
-#define EMAC_HRB        (144) // Hash Address Bottom[31:0]
-#define EMAC_HRT        (148) // Hash Address Top[63:32]
-#define EMAC_SA1L       (152) // Specific Address 1 Bottom, First 4 bytes
-#define EMAC_SA1H       (156) // Specific Address 1 Top, Last 2 bytes
-#define EMAC_SA2L       (160) // Specific Address 2 Bottom, First 4 bytes
-#define EMAC_SA2H       (164) // Specific Address 2 Top, Last 2 bytes
-#define EMAC_SA3L       (168) // Specific Address 3 Bottom, First 4 bytes
-#define EMAC_SA3H       (172) // Specific Address 3 Top, Last 2 bytes
-#define EMAC_SA4L       (176) // Specific Address 4 Bottom, First 4 bytes
-#define EMAC_SA4H       (180) // Specific Address 4 Top, Last 2 bytes
-#define EMAC_TID        (184) // Type ID Checking Register
-#define EMAC_TPQ        (188) // Transmit Pause Quantum Register
-#define EMAC_USRIO      (192) // USER Input/Output Register
-#define EMAC_WOL        (196) // Wake On LAN Register
-#define EMAC_REV        (252) // Revision Register
-// -------- EMAC_NCR : (EMAC Offset: 0x0)  --------
-#define AT91C_EMAC_LB             (0x1 <<  0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
-#define AT91C_EMAC_LLB            (0x1 <<  1) // (EMAC) Loopback local.
-#define AT91C_EMAC_RE             (0x1 <<  2) // (EMAC) Receive enable.
-#define AT91C_EMAC_TE             (0x1 <<  3) // (EMAC) Transmit enable.
-#define AT91C_EMAC_MPE            (0x1 <<  4) // (EMAC) Management port enable.
-#define AT91C_EMAC_CLRSTAT        (0x1 <<  5) // (EMAC) Clear statistics registers.
-#define AT91C_EMAC_INCSTAT        (0x1 <<  6) // (EMAC) Increment statistics registers.
-#define AT91C_EMAC_WESTAT         (0x1 <<  7) // (EMAC) Write enable for statistics registers.
-#define AT91C_EMAC_BP             (0x1 <<  8) // (EMAC) Back pressure.
-#define AT91C_EMAC_TSTART         (0x1 <<  9) // (EMAC) Start Transmission.
-#define AT91C_EMAC_THALT          (0x1 << 10) // (EMAC) Transmission Halt.
-#define AT91C_EMAC_TPFR           (0x1 << 11) // (EMAC) Transmit pause frame
-#define AT91C_EMAC_TZQ            (0x1 << 12) // (EMAC) Transmit zero quantum pause frame
-// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register --------
-#define AT91C_EMAC_SPD            (0x1 <<  0) // (EMAC) Speed.
-#define AT91C_EMAC_FD             (0x1 <<  1) // (EMAC) Full duplex.
-#define AT91C_EMAC_JFRAME         (0x1 <<  3) // (EMAC) Jumbo Frames.
-#define AT91C_EMAC_CAF            (0x1 <<  4) // (EMAC) Copy all frames.
-#define AT91C_EMAC_NBC            (0x1 <<  5) // (EMAC) No broadcast.
-#define AT91C_EMAC_MTI            (0x1 <<  6) // (EMAC) Multicast hash event enable
-#define AT91C_EMAC_UNI            (0x1 <<  7) // (EMAC) Unicast hash enable.
-#define AT91C_EMAC_BIG            (0x1 <<  8) // (EMAC) Receive 1522 bytes.
-#define AT91C_EMAC_EAE            (0x1 <<  9) // (EMAC) External address match enable.
-#define AT91C_EMAC_CLK            (0x3 << 10) // (EMAC)
-#define     AT91C_EMAC_CLK_HCLK_8               (0x0 << 10) // (EMAC) HCLK divided by 8
-#define     AT91C_EMAC_CLK_HCLK_16              (0x1 << 10) // (EMAC) HCLK divided by 16
-#define     AT91C_EMAC_CLK_HCLK_32              (0x2 << 10) // (EMAC) HCLK divided by 32
-#define     AT91C_EMAC_CLK_HCLK_64              (0x3 << 10) // (EMAC) HCLK divided by 64
-#define AT91C_EMAC_RTY            (0x1 << 12) // (EMAC)
-#define AT91C_EMAC_PAE            (0x1 << 13) // (EMAC)
-#define AT91C_EMAC_RBOF           (0x3 << 14) // (EMAC)
-#define     AT91C_EMAC_RBOF_OFFSET_0             (0x0 << 14) // (EMAC) no offset from start of receive buffer
-#define     AT91C_EMAC_RBOF_OFFSET_1             (0x1 << 14) // (EMAC) one byte offset from start of receive buffer
-#define     AT91C_EMAC_RBOF_OFFSET_2             (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
-#define     AT91C_EMAC_RBOF_OFFSET_3             (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
-#define AT91C_EMAC_RLCE           (0x1 << 16) // (EMAC) Receive Length field Checking Enable
-#define AT91C_EMAC_DRFCS          (0x1 << 17) // (EMAC) Discard Receive FCS
-#define AT91C_EMAC_EFRHD          (0x1 << 18) // (EMAC)
-#define AT91C_EMAC_IRXFCS         (0x1 << 19) // (EMAC) Ignore RX FCS
-// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register --------
-#define AT91C_EMAC_LINKR          (0x1 <<  0) // (EMAC)
-#define AT91C_EMAC_MDIO           (0x1 <<  1) // (EMAC)
-#define AT91C_EMAC_IDLE           (0x1 <<  2) // (EMAC)
-// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register --------
-#define AT91C_EMAC_UBR            (0x1 <<  0) // (EMAC)
-#define AT91C_EMAC_COL            (0x1 <<  1) // (EMAC)
-#define AT91C_EMAC_RLES           (0x1 <<  2) // (EMAC)
-#define AT91C_EMAC_TGO            (0x1 <<  3) // (EMAC) Transmit Go
-#define AT91C_EMAC_BEX            (0x1 <<  4) // (EMAC) Buffers exhausted mid frame
-#define AT91C_EMAC_COMP           (0x1 <<  5) // (EMAC)
-#define AT91C_EMAC_UND            (0x1 <<  6) // (EMAC)
-// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register --------
-#define AT91C_EMAC_BNA            (0x1 <<  0) // (EMAC)
-#define AT91C_EMAC_REC            (0x1 <<  1) // (EMAC)
-#define AT91C_EMAC_OVR            (0x1 <<  2) // (EMAC)
-// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register --------
-#define AT91C_EMAC_MFD            (0x1 <<  0) // (EMAC)
-#define AT91C_EMAC_RCOMP          (0x1 <<  1) // (EMAC)
-#define AT91C_EMAC_RXUBR          (0x1 <<  2) // (EMAC)
-#define AT91C_EMAC_TXUBR          (0x1 <<  3) // (EMAC)
-#define AT91C_EMAC_TUNDR          (0x1 <<  4) // (EMAC)
-#define AT91C_EMAC_RLEX           (0x1 <<  5) // (EMAC)
-#define AT91C_EMAC_TXERR          (0x1 <<  6) // (EMAC)
-#define AT91C_EMAC_TCOMP          (0x1 <<  7) // (EMAC)
-#define AT91C_EMAC_LINK           (0x1 <<  9) // (EMAC)
-#define AT91C_EMAC_ROVR           (0x1 << 10) // (EMAC)
-#define AT91C_EMAC_HRESP          (0x1 << 11) // (EMAC)
-#define AT91C_EMAC_PFRE           (0x1 << 12) // (EMAC)
-#define AT91C_EMAC_PTZ            (0x1 << 13) // (EMAC)
-// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register --------
-// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register --------
-// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register --------
-// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register --------
-#define AT91C_EMAC_DATA           (0xFFFF <<  0) // (EMAC)
-#define AT91C_EMAC_CODE           (0x3 << 16) // (EMAC)
-#define AT91C_EMAC_REGA           (0x1F << 18) // (EMAC)
-#define AT91C_EMAC_PHYA           (0x1F << 23) // (EMAC)
-#define AT91C_EMAC_RW             (0x3 << 28) // (EMAC)
-#define AT91C_EMAC_SOF            (0x3 << 30) // (EMAC)
-// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register --------
-#define AT91C_EMAC_RMII           (0x1 <<  0) // (EMAC) Reduce MII
-// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register --------
-#define AT91C_EMAC_IP             (0xFFFF <<  0) // (EMAC) ARP request IP address
-#define AT91C_EMAC_MAG            (0x1 << 16) // (EMAC) Magic packet event enable
-#define AT91C_EMAC_ARP            (0x1 << 17) // (EMAC) ARP request event enable
-#define AT91C_EMAC_SA1            (0x1 << 18) // (EMAC) Specific address register 1 event enable
-// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register --------
-#define AT91C_EMAC_REVREF         (0xFFFF <<  0) // (EMAC)
-#define AT91C_EMAC_PARTREF        (0xFFFF << 16) // (EMAC)
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Ethernet MAC 10/100 */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_EMAC structure *** */
+#define EMAC_NCR                        ( 0 )         /* Network Control Register */
+#define EMAC_NCFGR                      ( 4 )         /* Network Configuration Register */
+#define EMAC_NSR                        ( 8 )         /* Network Status Register */
+#define EMAC_TSR                        ( 20 )        /* Transmit Status Register */
+#define EMAC_RBQP                       ( 24 )        /* Receive Buffer Queue Pointer */
+#define EMAC_TBQP                       ( 28 )        /* Transmit Buffer Queue Pointer */
+#define EMAC_RSR                        ( 32 )        /* Receive Status Register */
+#define EMAC_ISR                        ( 36 )        /* Interrupt Status Register */
+#define EMAC_IER                        ( 40 )        /* Interrupt Enable Register */
+#define EMAC_IDR                        ( 44 )        /* Interrupt Disable Register */
+#define EMAC_IMR                        ( 48 )        /* Interrupt Mask Register */
+#define EMAC_MAN                        ( 52 )        /* PHY Maintenance Register */
+#define EMAC_PTR                        ( 56 )        /* Pause Time Register */
+#define EMAC_PFR                        ( 60 )        /* Pause Frames received Register */
+#define EMAC_FTO                        ( 64 )        /* Frames Transmitted OK Register */
+#define EMAC_SCF                        ( 68 )        /* Single Collision Frame Register */
+#define EMAC_MCF                        ( 72 )        /* Multiple Collision Frame Register */
+#define EMAC_FRO                        ( 76 )        /* Frames Received OK Register */
+#define EMAC_FCSE                       ( 80 )        /* Frame Check Sequence Error Register */
+#define EMAC_ALE                        ( 84 )        /* Alignment Error Register */
+#define EMAC_DTF                        ( 88 )        /* Deferred Transmission Frame Register */
+#define EMAC_LCOL                       ( 92 )        /* Late Collision Register */
+#define EMAC_ECOL                       ( 96 )        /* Excessive Collision Register */
+#define EMAC_TUND                       ( 100 )       /* Transmit Underrun Error Register */
+#define EMAC_CSE                        ( 104 )       /* Carrier Sense Error Register */
+#define EMAC_RRE                        ( 108 )       /* Receive Ressource Error Register */
+#define EMAC_ROV                        ( 112 )       /* Receive Overrun Errors Register */
+#define EMAC_RSE                        ( 116 )       /* Receive Symbol Errors Register */
+#define EMAC_ELE                        ( 120 )       /* Excessive Length Errors Register */
+#define EMAC_RJA                        ( 124 )       /* Receive Jabbers Register */
+#define EMAC_USF                        ( 128 )       /* Undersize Frames Register */
+#define EMAC_STE                        ( 132 )       /* SQE Test Error Register */
+#define EMAC_RLE                        ( 136 )       /* Receive Length Field Mismatch Register */
+#define EMAC_TPF                        ( 140 )       /* Transmitted Pause Frames Register */
+#define EMAC_HRB                        ( 144 )       /* Hash Address Bottom[31:0] */
+#define EMAC_HRT                        ( 148 )       /* Hash Address Top[63:32] */
+#define EMAC_SA1L                       ( 152 )       /* Specific Address 1 Bottom, First 4 bytes */
+#define EMAC_SA1H                       ( 156 )       /* Specific Address 1 Top, Last 2 bytes */
+#define EMAC_SA2L                       ( 160 )       /* Specific Address 2 Bottom, First 4 bytes */
+#define EMAC_SA2H                       ( 164 )       /* Specific Address 2 Top, Last 2 bytes */
+#define EMAC_SA3L                       ( 168 )       /* Specific Address 3 Bottom, First 4 bytes */
+#define EMAC_SA3H                       ( 172 )       /* Specific Address 3 Top, Last 2 bytes */
+#define EMAC_SA4L                       ( 176 )       /* Specific Address 4 Bottom, First 4 bytes */
+#define EMAC_SA4H                       ( 180 )       /* Specific Address 4 Top, Last 2 bytes */
+#define EMAC_TID                        ( 184 )       /* Type ID Checking Register */
+#define EMAC_TPQ                        ( 188 )       /* Transmit Pause Quantum Register */
+#define EMAC_USRIO                      ( 192 )       /* USER Input/Output Register */
+#define EMAC_WOL                        ( 196 )       /* Wake On LAN Register */
+#define EMAC_REV                        ( 252 )       /* Revision Register */
+/* -------- EMAC_NCR : (EMAC Offset: 0x0)  -------- */
+#define AT91C_EMAC_LB                   ( 0x1 << 0 )  /* (EMAC) Loopback. Optional. When set, loopback signal is at high level. */
+#define AT91C_EMAC_LLB                  ( 0x1 << 1 )  /* (EMAC) Loopback local. */
+#define AT91C_EMAC_RE                   ( 0x1 << 2 )  /* (EMAC) Receive enable. */
+#define AT91C_EMAC_TE                   ( 0x1 << 3 )  /* (EMAC) Transmit enable. */
+#define AT91C_EMAC_MPE                  ( 0x1 << 4 )  /* (EMAC) Management port enable. */
+#define AT91C_EMAC_CLRSTAT              ( 0x1 << 5 )  /* (EMAC) Clear statistics registers. */
+#define AT91C_EMAC_INCSTAT              ( 0x1 << 6 )  /* (EMAC) Increment statistics registers. */
+#define AT91C_EMAC_WESTAT               ( 0x1 << 7 )  /* (EMAC) Write enable for statistics registers. */
+#define AT91C_EMAC_BP                   ( 0x1 << 8 )  /* (EMAC) Back pressure. */
+#define AT91C_EMAC_TSTART               ( 0x1 << 9 )  /* (EMAC) Start Transmission. */
+#define AT91C_EMAC_THALT                ( 0x1 << 10 ) /* (EMAC) Transmission Halt. */
+#define AT91C_EMAC_TPFR                 ( 0x1 << 11 ) /* (EMAC) Transmit pause frame */
+#define AT91C_EMAC_TZQ                  ( 0x1 << 12 ) /* (EMAC) Transmit zero quantum pause frame */
+/* -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- */
+#define AT91C_EMAC_SPD                  ( 0x1 << 0 )  /* (EMAC) Speed. */
+#define AT91C_EMAC_FD                   ( 0x1 << 1 )  /* (EMAC) Full duplex. */
+#define AT91C_EMAC_JFRAME               ( 0x1 << 3 )  /* (EMAC) Jumbo Frames. */
+#define AT91C_EMAC_CAF                  ( 0x1 << 4 )  /* (EMAC) Copy all frames. */
+#define AT91C_EMAC_NBC                  ( 0x1 << 5 )  /* (EMAC) No broadcast. */
+#define AT91C_EMAC_MTI                  ( 0x1 << 6 )  /* (EMAC) Multicast hash event enable */
+#define AT91C_EMAC_UNI                  ( 0x1 << 7 )  /* (EMAC) Unicast hash enable. */
+#define AT91C_EMAC_BIG                  ( 0x1 << 8 )  /* (EMAC) Receive 1522 bytes. */
+#define AT91C_EMAC_EAE                  ( 0x1 << 9 )  /* (EMAC) External address match enable. */
+#define AT91C_EMAC_CLK                  ( 0x3 << 10 ) /* (EMAC) */
+#define     AT91C_EMAC_CLK_HCLK_8       ( 0x0 << 10 ) /* (EMAC) HCLK divided by 8 */
+#define     AT91C_EMAC_CLK_HCLK_16      ( 0x1 << 10 ) /* (EMAC) HCLK divided by 16 */
+#define     AT91C_EMAC_CLK_HCLK_32      ( 0x2 << 10 ) /* (EMAC) HCLK divided by 32 */
+#define     AT91C_EMAC_CLK_HCLK_64      ( 0x3 << 10 ) /* (EMAC) HCLK divided by 64 */
+#define AT91C_EMAC_RTY                  ( 0x1 << 12 ) /* (EMAC) */
+#define AT91C_EMAC_PAE                  ( 0x1 << 13 ) /* (EMAC) */
+#define AT91C_EMAC_RBOF                 ( 0x3 << 14 ) /* (EMAC) */
+#define     AT91C_EMAC_RBOF_OFFSET_0    ( 0x0 << 14 ) /* (EMAC) no offset from start of receive buffer */
+#define     AT91C_EMAC_RBOF_OFFSET_1    ( 0x1 << 14 ) /* (EMAC) one byte offset from start of receive buffer */
+#define     AT91C_EMAC_RBOF_OFFSET_2    ( 0x2 << 14 ) /* (EMAC) two bytes offset from start of receive buffer */
+#define     AT91C_EMAC_RBOF_OFFSET_3    ( 0x3 << 14 ) /* (EMAC) three bytes offset from start of receive buffer */
+#define AT91C_EMAC_RLCE                 ( 0x1 << 16 ) /* (EMAC) Receive Length field Checking Enable */
+#define AT91C_EMAC_DRFCS                ( 0x1 << 17 ) /* (EMAC) Discard Receive FCS */
+#define AT91C_EMAC_EFRHD                ( 0x1 << 18 ) /* (EMAC) */
+#define AT91C_EMAC_IRXFCS               ( 0x1 << 19 ) /* (EMAC) Ignore RX FCS */
+/* -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- */
+#define AT91C_EMAC_LINKR                ( 0x1 << 0 )  /* (EMAC) */
+#define AT91C_EMAC_MDIO                 ( 0x1 << 1 )  /* (EMAC) */
+#define AT91C_EMAC_IDLE                 ( 0x1 << 2 )  /* (EMAC) */
+/* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- */
+#define AT91C_EMAC_UBR                  ( 0x1 << 0 )  /* (EMAC) */
+#define AT91C_EMAC_COL                  ( 0x1 << 1 )  /* (EMAC) */
+#define AT91C_EMAC_RLES                 ( 0x1 << 2 )  /* (EMAC) */
+#define AT91C_EMAC_TGO                  ( 0x1 << 3 )  /* (EMAC) Transmit Go */
+#define AT91C_EMAC_BEX                  ( 0x1 << 4 )  /* (EMAC) Buffers exhausted mid frame */
+#define AT91C_EMAC_COMP                 ( 0x1 << 5 )  /* (EMAC) */
+#define AT91C_EMAC_UND                  ( 0x1 << 6 )  /* (EMAC) */
+/* -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- */
+#define AT91C_EMAC_BNA                  ( 0x1 << 0 )  /* (EMAC) */
+#define AT91C_EMAC_REC                  ( 0x1 << 1 )  /* (EMAC) */
+#define AT91C_EMAC_OVR                  ( 0x1 << 2 )  /* (EMAC) */
+/* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- */
+#define AT91C_EMAC_MFD                  ( 0x1 << 0 )  /* (EMAC) */
+#define AT91C_EMAC_RCOMP                ( 0x1 << 1 )  /* (EMAC) */
+#define AT91C_EMAC_RXUBR                ( 0x1 << 2 )  /* (EMAC) */
+#define AT91C_EMAC_TXUBR                ( 0x1 << 3 )  /* (EMAC) */
+#define AT91C_EMAC_TUNDR                ( 0x1 << 4 )  /* (EMAC) */
+#define AT91C_EMAC_RLEX                 ( 0x1 << 5 )  /* (EMAC) */
+#define AT91C_EMAC_TXERR                ( 0x1 << 6 )  /* (EMAC) */
+#define AT91C_EMAC_TCOMP                ( 0x1 << 7 )  /* (EMAC) */
+#define AT91C_EMAC_LINK                 ( 0x1 << 9 )  /* (EMAC) */
+#define AT91C_EMAC_ROVR                 ( 0x1 << 10 ) /* (EMAC) */
+#define AT91C_EMAC_HRESP                ( 0x1 << 11 ) /* (EMAC) */
+#define AT91C_EMAC_PFRE                 ( 0x1 << 12 ) /* (EMAC) */
+#define AT91C_EMAC_PTZ                  ( 0x1 << 13 ) /* (EMAC) */
+/* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- */
+/* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- */
+/* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */
+/* -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- */
+#define AT91C_EMAC_DATA       ( 0xFFFF << 0 )  /* (EMAC) */
+#define AT91C_EMAC_CODE       ( 0x3 << 16 )    /* (EMAC) */
+#define AT91C_EMAC_REGA       ( 0x1F << 18 )   /* (EMAC) */
+#define AT91C_EMAC_PHYA       ( 0x1F << 23 )   /* (EMAC) */
+#define AT91C_EMAC_RW         ( 0x3 << 28 )    /* (EMAC) */
+#define AT91C_EMAC_SOF        ( 0x3 << 30 )    /* (EMAC) */
+/* -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- */
+#define AT91C_EMAC_RMII       ( 0x1 << 0 )     /* (EMAC) Reduce MII */
+/* -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- */
+#define AT91C_EMAC_IP         ( 0xFFFF << 0 )  /* (EMAC) ARP request IP address */
+#define AT91C_EMAC_MAG        ( 0x1 << 16 )    /* (EMAC) Magic packet event enable */
+#define AT91C_EMAC_ARP        ( 0x1 << 17 )    /* (EMAC) ARP request event enable */
+#define AT91C_EMAC_SA1        ( 0x1 << 18 )    /* (EMAC) Specific address register 1 event enable */
+/* -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- */
+#define AT91C_EMAC_REVREF     ( 0xFFFF << 0 )  /* (EMAC) */
+#define AT91C_EMAC_PARTREF    ( 0xFFFF << 16 ) /* (EMAC) */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
-// *****************************************************************************
-// *** Register offset in AT91S_ADC structure ***
-#define ADC_CR          ( 0) // ADC Control Register
-#define ADC_MR          ( 4) // ADC Mode Register
-#define ADC_CHER        (16) // ADC Channel Enable Register
-#define ADC_CHDR        (20) // ADC Channel Disable Register
-#define ADC_CHSR        (24) // ADC Channel Status Register
-#define ADC_SR          (28) // ADC Status Register
-#define ADC_LCDR        (32) // ADC Last Converted Data Register
-#define ADC_IER         (36) // ADC Interrupt Enable Register
-#define ADC_IDR         (40) // ADC Interrupt Disable Register
-#define ADC_IMR         (44) // ADC Interrupt Mask Register
-#define ADC_CDR0        (48) // ADC Channel Data Register 0
-#define ADC_CDR1        (52) // ADC Channel Data Register 1
-#define ADC_CDR2        (56) // ADC Channel Data Register 2
-#define ADC_CDR3        (60) // ADC Channel Data Register 3
-#define ADC_CDR4        (64) // ADC Channel Data Register 4
-#define ADC_CDR5        (68) // ADC Channel Data Register 5
-#define ADC_CDR6        (72) // ADC Channel Data Register 6
-#define ADC_CDR7        (76) // ADC Channel Data Register 7
-#define ADC_RPR         (256) // Receive Pointer Register
-#define ADC_RCR         (260) // Receive Counter Register
-#define ADC_TPR         (264) // Transmit Pointer Register
-#define ADC_TCR         (268) // Transmit Counter Register
-#define ADC_RNPR        (272) // Receive Next Pointer Register
-#define ADC_RNCR        (276) // Receive Next Counter Register
-#define ADC_TNPR        (280) // Transmit Next Pointer Register
-#define ADC_TNCR        (284) // Transmit Next Counter Register
-#define ADC_PTCR        (288) // PDC Transfer Control Register
-#define ADC_PTSR        (292) // PDC Transfer Status Register
-// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
-#define AT91C_ADC_SWRST           (0x1 <<  0) // (ADC) Software Reset
-#define AT91C_ADC_START           (0x1 <<  1) // (ADC) Start Conversion
-// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
-#define AT91C_ADC_TRGEN           (0x1 <<  0) // (ADC) Trigger Enable
-#define     AT91C_ADC_TRGEN_DIS                  (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
-#define     AT91C_ADC_TRGEN_EN                   (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
-#define AT91C_ADC_TRGSEL          (0x7 <<  1) // (ADC) Trigger Selection
-#define     AT91C_ADC_TRGSEL_TIOA0                (0x0 <<  1) // (ADC) Selected TRGSEL = TIAO0
-#define     AT91C_ADC_TRGSEL_TIOA1                (0x1 <<  1) // (ADC) Selected TRGSEL = TIAO1
-#define     AT91C_ADC_TRGSEL_TIOA2                (0x2 <<  1) // (ADC) Selected TRGSEL = TIAO2
-#define     AT91C_ADC_TRGSEL_TIOA3                (0x3 <<  1) // (ADC) Selected TRGSEL = TIAO3
-#define     AT91C_ADC_TRGSEL_TIOA4                (0x4 <<  1) // (ADC) Selected TRGSEL = TIAO4
-#define     AT91C_ADC_TRGSEL_TIOA5                (0x5 <<  1) // (ADC) Selected TRGSEL = TIAO5
-#define     AT91C_ADC_TRGSEL_EXT                  (0x6 <<  1) // (ADC) Selected TRGSEL = External Trigger
-#define AT91C_ADC_LOWRES          (0x1 <<  4) // (ADC) Resolution.
-#define     AT91C_ADC_LOWRES_10_BIT               (0x0 <<  4) // (ADC) 10-bit resolution
-#define     AT91C_ADC_LOWRES_8_BIT                (0x1 <<  4) // (ADC) 8-bit resolution
-#define AT91C_ADC_SLEEP           (0x1 <<  5) // (ADC) Sleep Mode
-#define     AT91C_ADC_SLEEP_NORMAL_MODE          (0x0 <<  5) // (ADC) Normal Mode
-#define     AT91C_ADC_SLEEP_MODE                 (0x1 <<  5) // (ADC) Sleep Mode
-#define AT91C_ADC_PRESCAL         (0x3F <<  8) // (ADC) Prescaler rate selection
-#define AT91C_ADC_STARTUP         (0x1F << 16) // (ADC) Startup Time
-#define AT91C_ADC_SHTIM           (0xF << 24) // (ADC) Sample & Hold Time
-// --------     ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
-#define AT91C_ADC_CH0             (0x1 <<  0) // (ADC) Channel 0
-#define AT91C_ADC_CH1             (0x1 <<  1) // (ADC) Channel 1
-#define AT91C_ADC_CH2             (0x1 <<  2) // (ADC) Channel 2
-#define AT91C_ADC_CH3             (0x1 <<  3) // (ADC) Channel 3
-#define AT91C_ADC_CH4             (0x1 <<  4) // (ADC) Channel 4
-#define AT91C_ADC_CH5             (0x1 <<  5) // (ADC) Channel 5
-#define AT91C_ADC_CH6             (0x1 <<  6) // (ADC) Channel 6
-#define AT91C_ADC_CH7             (0x1 <<  7) // (ADC) Channel 7
-// --------     ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
-// --------     ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
-// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
-#define AT91C_ADC_EOC0            (0x1 <<  0) // (ADC) End of Conversion
-#define AT91C_ADC_EOC1            (0x1 <<  1) // (ADC) End of Conversion
-#define AT91C_ADC_EOC2            (0x1 <<  2) // (ADC) End of Conversion
-#define AT91C_ADC_EOC3            (0x1 <<  3) // (ADC) End of Conversion
-#define AT91C_ADC_EOC4            (0x1 <<  4) // (ADC) End of Conversion
-#define AT91C_ADC_EOC5            (0x1 <<  5) // (ADC) End of Conversion
-#define AT91C_ADC_EOC6            (0x1 <<  6) // (ADC) End of Conversion
-#define AT91C_ADC_EOC7            (0x1 <<  7) // (ADC) End of Conversion
-#define AT91C_ADC_OVRE0           (0x1 <<  8) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE1           (0x1 <<  9) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE2           (0x1 << 10) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE3           (0x1 << 11) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE4           (0x1 << 12) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE5           (0x1 << 13) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE6           (0x1 << 14) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE7           (0x1 << 15) // (ADC) Overrun Error
-#define AT91C_ADC_DRDY            (0x1 << 16) // (ADC) Data Ready
-#define AT91C_ADC_GOVRE           (0x1 << 17) // (ADC) General Overrun
-#define AT91C_ADC_ENDRX           (0x1 << 18) // (ADC) End of Receiver Transfer
-#define AT91C_ADC_RXBUFF          (0x1 << 19) // (ADC) RXBUFF Interrupt
-// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
-#define AT91C_ADC_LDATA           (0x3FF <<  0) // (ADC) Last Data Converted
-// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
-// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
-// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
-// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
-#define AT91C_ADC_DATA            (0x3FF <<  0) // (ADC) Converted Data
-// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
-// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
-// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
-// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
-// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
-// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
-// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_ADC structure *** */
+#define ADC_CR                             ( 0 )          /* ADC Control Register */
+#define ADC_MR                             ( 4 )          /* ADC Mode Register */
+#define ADC_CHER                           ( 16 )         /* ADC Channel Enable Register */
+#define ADC_CHDR                           ( 20 )         /* ADC Channel Disable Register */
+#define ADC_CHSR                           ( 24 )         /* ADC Channel Status Register */
+#define ADC_SR                             ( 28 )         /* ADC Status Register */
+#define ADC_LCDR                           ( 32 )         /* ADC Last Converted Data Register */
+#define ADC_IER                            ( 36 )         /* ADC Interrupt Enable Register */
+#define ADC_IDR                            ( 40 )         /* ADC Interrupt Disable Register */
+#define ADC_IMR                            ( 44 )         /* ADC Interrupt Mask Register */
+#define ADC_CDR0                           ( 48 )         /* ADC Channel Data Register 0 */
+#define ADC_CDR1                           ( 52 )         /* ADC Channel Data Register 1 */
+#define ADC_CDR2                           ( 56 )         /* ADC Channel Data Register 2 */
+#define ADC_CDR3                           ( 60 )         /* ADC Channel Data Register 3 */
+#define ADC_CDR4                           ( 64 )         /* ADC Channel Data Register 4 */
+#define ADC_CDR5                           ( 68 )         /* ADC Channel Data Register 5 */
+#define ADC_CDR6                           ( 72 )         /* ADC Channel Data Register 6 */
+#define ADC_CDR7                           ( 76 )         /* ADC Channel Data Register 7 */
+#define ADC_RPR                            ( 256 )        /* Receive Pointer Register */
+#define ADC_RCR                            ( 260 )        /* Receive Counter Register */
+#define ADC_TPR                            ( 264 )        /* Transmit Pointer Register */
+#define ADC_TCR                            ( 268 )        /* Transmit Counter Register */
+#define ADC_RNPR                           ( 272 )        /* Receive Next Pointer Register */
+#define ADC_RNCR                           ( 276 )        /* Receive Next Counter Register */
+#define ADC_TNPR                           ( 280 )        /* Transmit Next Pointer Register */
+#define ADC_TNCR                           ( 284 )        /* Transmit Next Counter Register */
+#define ADC_PTCR                           ( 288 )        /* PDC Transfer Control Register */
+#define ADC_PTSR                           ( 292 )        /* PDC Transfer Status Register */
+/* -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- */
+#define AT91C_ADC_SWRST                    ( 0x1 << 0 )   /* (ADC) Software Reset */
+#define AT91C_ADC_START                    ( 0x1 << 1 )   /* (ADC) Start Conversion */
+/* -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- */
+#define AT91C_ADC_TRGEN                    ( 0x1 << 0 )   /* (ADC) Trigger Enable */
+#define     AT91C_ADC_TRGEN_DIS            ( 0x0 )        /* (ADC) Hardware triggers are disabled. Starting a conversion is only possible by software */
+#define     AT91C_ADC_TRGEN_EN             ( 0x1 )        /* (ADC) Hardware trigger selected by TRGSEL field is enabled. */
+#define AT91C_ADC_TRGSEL                   ( 0x7 << 1 )   /* (ADC) Trigger Selection */
+#define     AT91C_ADC_TRGSEL_TIOA0         ( 0x0 << 1 )   /* (ADC) Selected TRGSEL = TIAO0 */
+#define     AT91C_ADC_TRGSEL_TIOA1         ( 0x1 << 1 )   /* (ADC) Selected TRGSEL = TIAO1 */
+#define     AT91C_ADC_TRGSEL_TIOA2         ( 0x2 << 1 )   /* (ADC) Selected TRGSEL = TIAO2 */
+#define     AT91C_ADC_TRGSEL_TIOA3         ( 0x3 << 1 )   /* (ADC) Selected TRGSEL = TIAO3 */
+#define     AT91C_ADC_TRGSEL_TIOA4         ( 0x4 << 1 )   /* (ADC) Selected TRGSEL = TIAO4 */
+#define     AT91C_ADC_TRGSEL_TIOA5         ( 0x5 << 1 )   /* (ADC) Selected TRGSEL = TIAO5 */
+#define     AT91C_ADC_TRGSEL_EXT           ( 0x6 << 1 )   /* (ADC) Selected TRGSEL = External Trigger */
+#define AT91C_ADC_LOWRES                   ( 0x1 << 4 )   /* (ADC) Resolution. */
+#define     AT91C_ADC_LOWRES_10_BIT        ( 0x0 << 4 )   /* (ADC) 10-bit resolution */
+#define     AT91C_ADC_LOWRES_8_BIT         ( 0x1 << 4 )   /* (ADC) 8-bit resolution */
+#define AT91C_ADC_SLEEP                    ( 0x1 << 5 )   /* (ADC) Sleep Mode */
+#define     AT91C_ADC_SLEEP_NORMAL_MODE    ( 0x0 << 5 )   /* (ADC) Normal Mode */
+#define     AT91C_ADC_SLEEP_MODE           ( 0x1 << 5 )   /* (ADC) Sleep Mode */
+#define AT91C_ADC_PRESCAL                  ( 0x3F << 8 )  /* (ADC) Prescaler rate selection */
+#define AT91C_ADC_STARTUP                  ( 0x1F << 16 ) /* (ADC) Startup Time */
+#define AT91C_ADC_SHTIM                    ( 0xF << 24 )  /* (ADC) Sample & Hold Time */
+/* --------     ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- */
+#define AT91C_ADC_CH0                      ( 0x1 << 0 )   /* (ADC) Channel 0 */
+#define AT91C_ADC_CH1                      ( 0x1 << 1 )   /* (ADC) Channel 1 */
+#define AT91C_ADC_CH2                      ( 0x1 << 2 )   /* (ADC) Channel 2 */
+#define AT91C_ADC_CH3                      ( 0x1 << 3 )   /* (ADC) Channel 3 */
+#define AT91C_ADC_CH4                      ( 0x1 << 4 )   /* (ADC) Channel 4 */
+#define AT91C_ADC_CH5                      ( 0x1 << 5 )   /* (ADC) Channel 5 */
+#define AT91C_ADC_CH6                      ( 0x1 << 6 )   /* (ADC) Channel 6 */
+#define AT91C_ADC_CH7                      ( 0x1 << 7 )   /* (ADC) Channel 7 */
+/* --------     ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- */
+/* --------     ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- */
+/* -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- */
+#define AT91C_ADC_EOC0      ( 0x1 << 0 )      /* (ADC) End of Conversion */
+#define AT91C_ADC_EOC1      ( 0x1 << 1 )      /* (ADC) End of Conversion */
+#define AT91C_ADC_EOC2      ( 0x1 << 2 )      /* (ADC) End of Conversion */
+#define AT91C_ADC_EOC3      ( 0x1 << 3 )      /* (ADC) End of Conversion */
+#define AT91C_ADC_EOC4      ( 0x1 << 4 )      /* (ADC) End of Conversion */
+#define AT91C_ADC_EOC5      ( 0x1 << 5 )      /* (ADC) End of Conversion */
+#define AT91C_ADC_EOC6      ( 0x1 << 6 )      /* (ADC) End of Conversion */
+#define AT91C_ADC_EOC7      ( 0x1 << 7 )      /* (ADC) End of Conversion */
+#define AT91C_ADC_OVRE0     ( 0x1 << 8 )      /* (ADC) Overrun Error */
+#define AT91C_ADC_OVRE1     ( 0x1 << 9 )      /* (ADC) Overrun Error */
+#define AT91C_ADC_OVRE2     ( 0x1 << 10 )     /* (ADC) Overrun Error */
+#define AT91C_ADC_OVRE3     ( 0x1 << 11 )     /* (ADC) Overrun Error */
+#define AT91C_ADC_OVRE4     ( 0x1 << 12 )     /* (ADC) Overrun Error */
+#define AT91C_ADC_OVRE5     ( 0x1 << 13 )     /* (ADC) Overrun Error */
+#define AT91C_ADC_OVRE6     ( 0x1 << 14 )     /* (ADC) Overrun Error */
+#define AT91C_ADC_OVRE7     ( 0x1 << 15 )     /* (ADC) Overrun Error */
+#define AT91C_ADC_DRDY      ( 0x1 << 16 )     /* (ADC) Data Ready */
+#define AT91C_ADC_GOVRE     ( 0x1 << 17 )     /* (ADC) General Overrun */
+#define AT91C_ADC_ENDRX     ( 0x1 << 18 )     /* (ADC) End of Receiver Transfer */
+#define AT91C_ADC_RXBUFF    ( 0x1 << 19 )     /* (ADC) RXBUFF Interrupt */
+/* -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- */
+#define AT91C_ADC_LDATA     ( 0x3FF << 0 )    /* (ADC) Last Data Converted */
+/* -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- */
+/* -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- */
+/* -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- */
+/* -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- */
+#define AT91C_ADC_DATA    ( 0x3FF << 0 )        /* (ADC) Converted Data */
+/* -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- */
+/* -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- */
+/* -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- */
+/* -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- */
+/* -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- */
+/* -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- */
+/* -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Advanced  Encryption Standard
-// *****************************************************************************
-// *** Register offset in AT91S_AES structure ***
-#define AES_CR          ( 0) // Control Register
-#define AES_MR          ( 4) // Mode Register
-#define AES_IER         (16) // Interrupt Enable Register
-#define AES_IDR         (20) // Interrupt Disable Register
-#define AES_IMR         (24) // Interrupt Mask Register
-#define AES_ISR         (28) // Interrupt Status Register
-#define AES_KEYWxR      (32) // Key Word x Register
-#define AES_IDATAxR     (64) // Input Data x Register
-#define AES_ODATAxR     (80) // Output Data x Register
-#define AES_IVxR        (96) // Initialization Vector x Register
-#define AES_VR          (252) // AES Version Register
-#define AES_RPR         (256) // Receive Pointer Register
-#define AES_RCR         (260) // Receive Counter Register
-#define AES_TPR         (264) // Transmit Pointer Register
-#define AES_TCR         (268) // Transmit Counter Register
-#define AES_RNPR        (272) // Receive Next Pointer Register
-#define AES_RNCR        (276) // Receive Next Counter Register
-#define AES_TNPR        (280) // Transmit Next Pointer Register
-#define AES_TNCR        (284) // Transmit Next Counter Register
-#define AES_PTCR        (288) // PDC Transfer Control Register
-#define AES_PTSR        (292) // PDC Transfer Status Register
-// -------- AES_CR : (AES Offset: 0x0) Control Register --------
-#define AT91C_AES_START           (0x1 <<  0) // (AES) Starts Processing
-#define AT91C_AES_SWRST           (0x1 <<  8) // (AES) Software Reset
-#define AT91C_AES_LOADSEED        (0x1 << 16) // (AES) Random Number Generator Seed Loading
-// -------- AES_MR : (AES Offset: 0x4) Mode Register --------
-#define AT91C_AES_CIPHER          (0x1 <<  0) // (AES) Processing Mode
-#define AT91C_AES_PROCDLY         (0xF <<  4) // (AES) Processing Delay
-#define AT91C_AES_SMOD            (0x3 <<  8) // (AES) Start Mode
-#define     AT91C_AES_SMOD_MANUAL               (0x0 <<  8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.
-#define     AT91C_AES_SMOD_AUTO                 (0x1 <<  8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).
-#define     AT91C_AES_SMOD_PDC                  (0x2 <<  8) // (AES) PDC Mode (cf datasheet).
-#define AT91C_AES_OPMOD           (0x7 << 12) // (AES) Operation Mode
-#define     AT91C_AES_OPMOD_ECB                  (0x0 << 12) // (AES) ECB Electronic CodeBook mode.
-#define     AT91C_AES_OPMOD_CBC                  (0x1 << 12) // (AES) CBC Cipher Block Chaining mode.
-#define     AT91C_AES_OPMOD_OFB                  (0x2 << 12) // (AES) OFB Output Feedback mode.
-#define     AT91C_AES_OPMOD_CFB                  (0x3 << 12) // (AES) CFB Cipher Feedback mode.
-#define     AT91C_AES_OPMOD_CTR                  (0x4 << 12) // (AES) CTR Counter mode.
-#define AT91C_AES_LOD             (0x1 << 15) // (AES) Last Output Data Mode
-#define AT91C_AES_CFBS            (0x7 << 16) // (AES) Cipher Feedback Data Size
-#define     AT91C_AES_CFBS_128_BIT              (0x0 << 16) // (AES) 128-bit.
-#define     AT91C_AES_CFBS_64_BIT               (0x1 << 16) // (AES) 64-bit.
-#define     AT91C_AES_CFBS_32_BIT               (0x2 << 16) // (AES) 32-bit.
-#define     AT91C_AES_CFBS_16_BIT               (0x3 << 16) // (AES) 16-bit.
-#define     AT91C_AES_CFBS_8_BIT                (0x4 << 16) // (AES) 8-bit.
-#define AT91C_AES_CKEY            (0xF << 20) // (AES) Countermeasure Key
-#define AT91C_AES_CTYPE           (0x1F << 24) // (AES) Countermeasure Type
-#define     AT91C_AES_CTYPE_TYPE1_EN             (0x1 << 24) // (AES) Countermeasure type 1 is enabled.
-#define     AT91C_AES_CTYPE_TYPE2_EN             (0x2 << 24) // (AES) Countermeasure type 2 is enabled.
-#define     AT91C_AES_CTYPE_TYPE3_EN             (0x4 << 24) // (AES) Countermeasure type 3 is enabled.
-#define     AT91C_AES_CTYPE_TYPE4_EN             (0x8 << 24) // (AES) Countermeasure type 4 is enabled.
-#define     AT91C_AES_CTYPE_TYPE5_EN             (0x10 << 24) // (AES) Countermeasure type 5 is enabled.
-// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register --------
-#define AT91C_AES_DATRDY          (0x1 <<  0) // (AES) DATRDY
-#define AT91C_AES_ENDRX           (0x1 <<  1) // (AES) PDC Read Buffer End
-#define AT91C_AES_ENDTX           (0x1 <<  2) // (AES) PDC Write Buffer End
-#define AT91C_AES_RXBUFF          (0x1 <<  3) // (AES) PDC Read Buffer Full
-#define AT91C_AES_TXBUFE          (0x1 <<  4) // (AES) PDC Write Buffer Empty
-#define AT91C_AES_URAD            (0x1 <<  8) // (AES) Unspecified Register Access Detection
-// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register --------
-// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register --------
-// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register --------
-#define AT91C_AES_URAT            (0x7 << 12) // (AES) Unspecified Register Access Type Status
-#define     AT91C_AES_URAT_IN_DAT_WRITE_DATPROC (0x0 << 12) // (AES) Input data register written during the data processing in PDC mode.
-#define     AT91C_AES_URAT_OUT_DAT_READ_DATPROC (0x1 << 12) // (AES) Output data register read during the data processing.
-#define     AT91C_AES_URAT_MODEREG_WRITE_DATPROC (0x2 << 12) // (AES) Mode register written during the data processing.
-#define     AT91C_AES_URAT_OUT_DAT_READ_SUBKEY  (0x3 << 12) // (AES) Output data register read during the sub-keys generation.
-#define     AT91C_AES_URAT_MODEREG_WRITE_SUBKEY (0x4 << 12) // (AES) Mode register written during the sub-keys generation.
-#define     AT91C_AES_URAT_WO_REG_READ          (0x5 << 12) // (AES) Write-only register read access.
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Advanced  Encryption Standard */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_AES structure *** */
+#define AES_CR                          ( 0 )          /* Control Register */
+#define AES_MR                          ( 4 )          /* Mode Register */
+#define AES_IER                         ( 16 )         /* Interrupt Enable Register */
+#define AES_IDR                         ( 20 )         /* Interrupt Disable Register */
+#define AES_IMR                         ( 24 )         /* Interrupt Mask Register */
+#define AES_ISR                         ( 28 )         /* Interrupt Status Register */
+#define AES_KEYWxR                      ( 32 )         /* Key Word x Register */
+#define AES_IDATAxR                     ( 64 )         /* Input Data x Register */
+#define AES_ODATAxR                     ( 80 )         /* Output Data x Register */
+#define AES_IVxR                        ( 96 )         /* Initialization Vector x Register */
+#define AES_VR                          ( 252 )        /* AES Version Register */
+#define AES_RPR                         ( 256 )        /* Receive Pointer Register */
+#define AES_RCR                         ( 260 )        /* Receive Counter Register */
+#define AES_TPR                         ( 264 )        /* Transmit Pointer Register */
+#define AES_TCR                         ( 268 )        /* Transmit Counter Register */
+#define AES_RNPR                        ( 272 )        /* Receive Next Pointer Register */
+#define AES_RNCR                        ( 276 )        /* Receive Next Counter Register */
+#define AES_TNPR                        ( 280 )        /* Transmit Next Pointer Register */
+#define AES_TNCR                        ( 284 )        /* Transmit Next Counter Register */
+#define AES_PTCR                        ( 288 )        /* PDC Transfer Control Register */
+#define AES_PTSR                        ( 292 )        /* PDC Transfer Status Register */
+/* -------- AES_CR : (AES Offset: 0x0) Control Register -------- */
+#define AT91C_AES_START                 ( 0x1 << 0 )   /* (AES) Starts Processing */
+#define AT91C_AES_SWRST                 ( 0x1 << 8 )   /* (AES) Software Reset */
+#define AT91C_AES_LOADSEED              ( 0x1 << 16 )  /* (AES) Random Number Generator Seed Loading */
+/* -------- AES_MR : (AES Offset: 0x4) Mode Register -------- */
+#define AT91C_AES_CIPHER                ( 0x1 << 0 )   /* (AES) Processing Mode */
+#define AT91C_AES_PROCDLY               ( 0xF << 4 )   /* (AES) Processing Delay */
+#define AT91C_AES_SMOD                  ( 0x3 << 8 )   /* (AES) Start Mode */
+#define     AT91C_AES_SMOD_MANUAL       ( 0x0 << 8 )   /* (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. */
+#define     AT91C_AES_SMOD_AUTO         ( 0x1 << 8 )   /* (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). */
+#define     AT91C_AES_SMOD_PDC          ( 0x2 << 8 )   /* (AES) PDC Mode (cf datasheet). */
+#define AT91C_AES_OPMOD                 ( 0x7 << 12 )  /* (AES) Operation Mode */
+#define     AT91C_AES_OPMOD_ECB         ( 0x0 << 12 )  /* (AES) ECB Electronic CodeBook mode. */
+#define     AT91C_AES_OPMOD_CBC         ( 0x1 << 12 )  /* (AES) CBC Cipher Block Chaining mode. */
+#define     AT91C_AES_OPMOD_OFB         ( 0x2 << 12 )  /* (AES) OFB Output Feedback mode. */
+#define     AT91C_AES_OPMOD_CFB         ( 0x3 << 12 )  /* (AES) CFB Cipher Feedback mode. */
+#define     AT91C_AES_OPMOD_CTR         ( 0x4 << 12 )  /* (AES) CTR Counter mode. */
+#define AT91C_AES_LOD                   ( 0x1 << 15 )  /* (AES) Last Output Data Mode */
+#define AT91C_AES_CFBS                  ( 0x7 << 16 )  /* (AES) Cipher Feedback Data Size */
+#define     AT91C_AES_CFBS_128_BIT      ( 0x0 << 16 )  /* (AES) 128-bit. */
+#define     AT91C_AES_CFBS_64_BIT       ( 0x1 << 16 )  /* (AES) 64-bit. */
+#define     AT91C_AES_CFBS_32_BIT       ( 0x2 << 16 )  /* (AES) 32-bit. */
+#define     AT91C_AES_CFBS_16_BIT       ( 0x3 << 16 )  /* (AES) 16-bit. */
+#define     AT91C_AES_CFBS_8_BIT        ( 0x4 << 16 )  /* (AES) 8-bit. */
+#define AT91C_AES_CKEY                  ( 0xF << 20 )  /* (AES) Countermeasure Key */
+#define AT91C_AES_CTYPE                 ( 0x1F << 24 ) /* (AES) Countermeasure Type */
+#define     AT91C_AES_CTYPE_TYPE1_EN    ( 0x1 << 24 )  /* (AES) Countermeasure type 1 is enabled. */
+#define     AT91C_AES_CTYPE_TYPE2_EN    ( 0x2 << 24 )  /* (AES) Countermeasure type 2 is enabled. */
+#define     AT91C_AES_CTYPE_TYPE3_EN    ( 0x4 << 24 )  /* (AES) Countermeasure type 3 is enabled. */
+#define     AT91C_AES_CTYPE_TYPE4_EN    ( 0x8 << 24 )  /* (AES) Countermeasure type 4 is enabled. */
+#define     AT91C_AES_CTYPE_TYPE5_EN    ( 0x10 << 24 ) /* (AES) Countermeasure type 5 is enabled. */
+/* -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- */
+#define AT91C_AES_DATRDY                ( 0x1 << 0 )   /* (AES) DATRDY */
+#define AT91C_AES_ENDRX                 ( 0x1 << 1 )   /* (AES) PDC Read Buffer End */
+#define AT91C_AES_ENDTX                 ( 0x1 << 2 )   /* (AES) PDC Write Buffer End */
+#define AT91C_AES_RXBUFF                ( 0x1 << 3 )   /* (AES) PDC Read Buffer Full */
+#define AT91C_AES_TXBUFE                ( 0x1 << 4 )   /* (AES) PDC Write Buffer Empty */
+#define AT91C_AES_URAD                  ( 0x1 << 8 )   /* (AES) Unspecified Register Access Detection */
+/* -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- */
+/* -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- */
+/* -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- */
+#define AT91C_AES_URAT                              ( 0x7 << 12 ) /* (AES) Unspecified Register Access Type Status */
+#define     AT91C_AES_URAT_IN_DAT_WRITE_DATPROC     ( 0x0 << 12 ) /* (AES) Input data register written during the data processing in PDC mode. */
+#define     AT91C_AES_URAT_OUT_DAT_READ_DATPROC     ( 0x1 << 12 ) /* (AES) Output data register read during the data processing. */
+#define     AT91C_AES_URAT_MODEREG_WRITE_DATPROC    ( 0x2 << 12 ) /* (AES) Mode register written during the data processing. */
+#define     AT91C_AES_URAT_OUT_DAT_READ_SUBKEY      ( 0x3 << 12 ) /* (AES) Output data register read during the sub-keys generation. */
+#define     AT91C_AES_URAT_MODEREG_WRITE_SUBKEY     ( 0x4 << 12 ) /* (AES) Mode register written during the sub-keys generation. */
+#define     AT91C_AES_URAT_WO_REG_READ              ( 0x5 << 12 ) /* (AES) Write-only register read access. */
 
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Triple Data Encryption Standard
-// *****************************************************************************
-// *** Register offset in AT91S_TDES structure ***
-#define TDES_CR         ( 0) // Control Register
-#define TDES_MR         ( 4) // Mode Register
-#define TDES_IER        (16) // Interrupt Enable Register
-#define TDES_IDR        (20) // Interrupt Disable Register
-#define TDES_IMR        (24) // Interrupt Mask Register
-#define TDES_ISR        (28) // Interrupt Status Register
-#define TDES_KEY1WxR    (32) // Key 1 Word x Register
-#define TDES_KEY2WxR    (40) // Key 2 Word x Register
-#define TDES_KEY3WxR    (48) // Key 3 Word x Register
-#define TDES_IDATAxR    (64) // Input Data x Register
-#define TDES_ODATAxR    (80) // Output Data x Register
-#define TDES_IVxR       (96) // Initialization Vector x Register
-#define TDES_VR         (252) // TDES Version Register
-#define TDES_RPR        (256) // Receive Pointer Register
-#define TDES_RCR        (260) // Receive Counter Register
-#define TDES_TPR        (264) // Transmit Pointer Register
-#define TDES_TCR        (268) // Transmit Counter Register
-#define TDES_RNPR       (272) // Receive Next Pointer Register
-#define TDES_RNCR       (276) // Receive Next Counter Register
-#define TDES_TNPR       (280) // Transmit Next Pointer Register
-#define TDES_TNCR       (284) // Transmit Next Counter Register
-#define TDES_PTCR       (288) // PDC Transfer Control Register
-#define TDES_PTSR       (292) // PDC Transfer Status Register
-// -------- TDES_CR : (TDES Offset: 0x0) Control Register --------
-#define AT91C_TDES_START          (0x1 <<  0) // (TDES) Starts Processing
-#define AT91C_TDES_SWRST          (0x1 <<  8) // (TDES) Software Reset
-// -------- TDES_MR : (TDES Offset: 0x4) Mode Register --------
-#define AT91C_TDES_CIPHER         (0x1 <<  0) // (TDES) Processing Mode
-#define AT91C_TDES_TDESMOD        (0x1 <<  1) // (TDES) Single or Triple DES Mode
-#define AT91C_TDES_KEYMOD         (0x1 <<  4) // (TDES) Key Mode
-#define AT91C_TDES_SMOD           (0x3 <<  8) // (TDES) Start Mode
-#define     AT91C_TDES_SMOD_MANUAL               (0x0 <<  8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.
-#define     AT91C_TDES_SMOD_AUTO                 (0x1 <<  8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).
-#define     AT91C_TDES_SMOD_PDC                  (0x2 <<  8) // (TDES) PDC Mode (cf datasheet).
-#define AT91C_TDES_OPMOD          (0x3 << 12) // (TDES) Operation Mode
-#define     AT91C_TDES_OPMOD_ECB                  (0x0 << 12) // (TDES) ECB Electronic CodeBook mode.
-#define     AT91C_TDES_OPMOD_CBC                  (0x1 << 12) // (TDES) CBC Cipher Block Chaining mode.
-#define     AT91C_TDES_OPMOD_OFB                  (0x2 << 12) // (TDES) OFB Output Feedback mode.
-#define     AT91C_TDES_OPMOD_CFB                  (0x3 << 12) // (TDES) CFB Cipher Feedback mode.
-#define AT91C_TDES_LOD            (0x1 << 15) // (TDES) Last Output Data Mode
-#define AT91C_TDES_CFBS           (0x3 << 16) // (TDES) Cipher Feedback Data Size
-#define     AT91C_TDES_CFBS_64_BIT               (0x0 << 16) // (TDES) 64-bit.
-#define     AT91C_TDES_CFBS_32_BIT               (0x1 << 16) // (TDES) 32-bit.
-#define     AT91C_TDES_CFBS_16_BIT               (0x2 << 16) // (TDES) 16-bit.
-#define     AT91C_TDES_CFBS_8_BIT                (0x3 << 16) // (TDES) 8-bit.
-// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register --------
-#define AT91C_TDES_DATRDY         (0x1 <<  0) // (TDES) DATRDY
-#define AT91C_TDES_ENDRX          (0x1 <<  1) // (TDES) PDC Read Buffer End
-#define AT91C_TDES_ENDTX          (0x1 <<  2) // (TDES) PDC Write Buffer End
-#define AT91C_TDES_RXBUFF         (0x1 <<  3) // (TDES) PDC Read Buffer Full
-#define AT91C_TDES_TXBUFE         (0x1 <<  4) // (TDES) PDC Write Buffer Empty
-#define AT91C_TDES_URAD           (0x1 <<  8) // (TDES) Unspecified Register Access Detection
-// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register --------
-// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register --------
-// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register --------
-#define AT91C_TDES_URAT           (0x3 << 12) // (TDES) Unspecified Register Access Type Status
-#define     AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC (0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode.
-#define     AT91C_TDES_URAT_OUT_DAT_READ_DATPROC (0x1 << 12) // (TDES) Output data register read during the data processing.
-#define     AT91C_TDES_URAT_MODEREG_WRITE_DATPROC (0x2 << 12) // (TDES) Mode register written during the data processing.
-#define     AT91C_TDES_URAT_WO_REG_READ          (0x3 << 12) // (TDES) Write-only register read access.
+/* ***************************************************************************** */
+/*              SOFTWARE API DEFINITION  FOR Triple Data Encryption Standard */
+/* ***************************************************************************** */
+/* *** Register offset in AT91S_TDES structure *** */
+#define TDES_CR                       ( 0 )         /* Control Register */
+#define TDES_MR                       ( 4 )         /* Mode Register */
+#define TDES_IER                      ( 16 )        /* Interrupt Enable Register */
+#define TDES_IDR                      ( 20 )        /* Interrupt Disable Register */
+#define TDES_IMR                      ( 24 )        /* Interrupt Mask Register */
+#define TDES_ISR                      ( 28 )        /* Interrupt Status Register */
+#define TDES_KEY1WxR                  ( 32 )        /* Key 1 Word x Register */
+#define TDES_KEY2WxR                  ( 40 )        /* Key 2 Word x Register */
+#define TDES_KEY3WxR                  ( 48 )        /* Key 3 Word x Register */
+#define TDES_IDATAxR                  ( 64 )        /* Input Data x Register */
+#define TDES_ODATAxR                  ( 80 )        /* Output Data x Register */
+#define TDES_IVxR                     ( 96 )        /* Initialization Vector x Register */
+#define TDES_VR                       ( 252 )       /* TDES Version Register */
+#define TDES_RPR                      ( 256 )       /* Receive Pointer Register */
+#define TDES_RCR                      ( 260 )       /* Receive Counter Register */
+#define TDES_TPR                      ( 264 )       /* Transmit Pointer Register */
+#define TDES_TCR                      ( 268 )       /* Transmit Counter Register */
+#define TDES_RNPR                     ( 272 )       /* Receive Next Pointer Register */
+#define TDES_RNCR                     ( 276 )       /* Receive Next Counter Register */
+#define TDES_TNPR                     ( 280 )       /* Transmit Next Pointer Register */
+#define TDES_TNCR                     ( 284 )       /* Transmit Next Counter Register */
+#define TDES_PTCR                     ( 288 )       /* PDC Transfer Control Register */
+#define TDES_PTSR                     ( 292 )       /* PDC Transfer Status Register */
+/* -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- */
+#define AT91C_TDES_START              ( 0x1 << 0 )  /* (TDES) Starts Processing */
+#define AT91C_TDES_SWRST              ( 0x1 << 8 )  /* (TDES) Software Reset */
+/* -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- */
+#define AT91C_TDES_CIPHER             ( 0x1 << 0 )  /* (TDES) Processing Mode */
+#define AT91C_TDES_TDESMOD            ( 0x1 << 1 )  /* (TDES) Single or Triple DES Mode */
+#define AT91C_TDES_KEYMOD             ( 0x1 << 4 )  /* (TDES) Key Mode */
+#define AT91C_TDES_SMOD               ( 0x3 << 8 )  /* (TDES) Start Mode */
+#define     AT91C_TDES_SMOD_MANUAL    ( 0x0 << 8 )  /* (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. */
+#define     AT91C_TDES_SMOD_AUTO      ( 0x1 << 8 )  /* (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). */
+#define     AT91C_TDES_SMOD_PDC       ( 0x2 << 8 )  /* (TDES) PDC Mode (cf datasheet). */
+#define AT91C_TDES_OPMOD              ( 0x3 << 12 ) /* (TDES) Operation Mode */
+#define     AT91C_TDES_OPMOD_ECB      ( 0x0 << 12 ) /* (TDES) ECB Electronic CodeBook mode. */
+#define     AT91C_TDES_OPMOD_CBC      ( 0x1 << 12 ) /* (TDES) CBC Cipher Block Chaining mode. */
+#define     AT91C_TDES_OPMOD_OFB      ( 0x2 << 12 ) /* (TDES) OFB Output Feedback mode. */
+#define     AT91C_TDES_OPMOD_CFB      ( 0x3 << 12 ) /* (TDES) CFB Cipher Feedback mode. */
+#define AT91C_TDES_LOD                ( 0x1 << 15 ) /* (TDES) Last Output Data Mode */
+#define AT91C_TDES_CFBS               ( 0x3 << 16 ) /* (TDES) Cipher Feedback Data Size */
+#define     AT91C_TDES_CFBS_64_BIT    ( 0x0 << 16 ) /* (TDES) 64-bit. */
+#define     AT91C_TDES_CFBS_32_BIT    ( 0x1 << 16 ) /* (TDES) 32-bit. */
+#define     AT91C_TDES_CFBS_16_BIT    ( 0x2 << 16 ) /* (TDES) 16-bit. */
+#define     AT91C_TDES_CFBS_8_BIT     ( 0x3 << 16 ) /* (TDES) 8-bit. */
+/* -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- */
+#define AT91C_TDES_DATRDY             ( 0x1 << 0 )  /* (TDES) DATRDY */
+#define AT91C_TDES_ENDRX              ( 0x1 << 1 )  /* (TDES) PDC Read Buffer End */
+#define AT91C_TDES_ENDTX              ( 0x1 << 2 )  /* (TDES) PDC Write Buffer End */
+#define AT91C_TDES_RXBUFF             ( 0x1 << 3 )  /* (TDES) PDC Read Buffer Full */
+#define AT91C_TDES_TXBUFE             ( 0x1 << 4 )  /* (TDES) PDC Write Buffer Empty */
+#define AT91C_TDES_URAD               ( 0x1 << 8 )  /* (TDES) Unspecified Register Access Detection */
+/* -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- */
+/* -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- */
+/* -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- */
+#define AT91C_TDES_URAT                              ( 0x3 << 12 ) /* (TDES) Unspecified Register Access Type Status */
+#define     AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC     ( 0x0 << 12 ) /* (TDES) Input data register written during the data processing in PDC mode. */
+#define     AT91C_TDES_URAT_OUT_DAT_READ_DATPROC     ( 0x1 << 12 ) /* (TDES) Output data register read during the data processing. */
+#define     AT91C_TDES_URAT_MODEREG_WRITE_DATPROC    ( 0x2 << 12 ) /* (TDES) Mode register written during the data processing. */
+#define     AT91C_TDES_URAT_WO_REG_READ              ( 0x3 << 12 ) /* (TDES) Write-only register read access. */
 
-// *****************************************************************************
-//               REGISTER ADDRESS DEFINITION FOR AT91SAM7X256
-// *****************************************************************************
-// ========== Register definition for SYS peripheral ==========
-// ========== Register definition for AIC peripheral ==========
-#define AT91C_AIC_IVR             (0xFFFFF100) // (AIC) IRQ Vector Register
-#define AT91C_AIC_SMR             (0xFFFFF000) // (AIC) Source Mode Register
-#define AT91C_AIC_FVR             (0xFFFFF104) // (AIC) FIQ Vector Register
-#define AT91C_AIC_DCR             (0xFFFFF138) // (AIC) Debug Control Register (Protect)
-#define AT91C_AIC_EOICR           (0xFFFFF130) // (AIC) End of Interrupt Command Register
-#define AT91C_AIC_SVR             (0xFFFFF080) // (AIC) Source Vector Register
-#define AT91C_AIC_FFSR            (0xFFFFF148) // (AIC) Fast Forcing Status Register
-#define AT91C_AIC_ICCR            (0xFFFFF128) // (AIC) Interrupt Clear Command Register
-#define AT91C_AIC_ISR             (0xFFFFF108) // (AIC) Interrupt Status Register
-#define AT91C_AIC_IMR             (0xFFFFF110) // (AIC) Interrupt Mask Register
-#define AT91C_AIC_IPR             (0xFFFFF10C) // (AIC) Interrupt Pending Register
-#define AT91C_AIC_FFER            (0xFFFFF140) // (AIC) Fast Forcing Enable Register
-#define AT91C_AIC_IECR            (0xFFFFF120) // (AIC) Interrupt Enable Command Register
-#define AT91C_AIC_ISCR            (0xFFFFF12C) // (AIC) Interrupt Set Command Register
-#define AT91C_AIC_FFDR            (0xFFFFF144) // (AIC) Fast Forcing Disable Register
-#define AT91C_AIC_CISR            (0xFFFFF114) // (AIC) Core Interrupt Status Register
-#define AT91C_AIC_IDCR            (0xFFFFF124) // (AIC) Interrupt Disable Command Register
-#define AT91C_AIC_SPU             (0xFFFFF134) // (AIC) Spurious Vector Register
-// ========== Register definition for PDC_DBGU peripheral ==========
-#define AT91C_DBGU_TCR            (0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
-#define AT91C_DBGU_RNPR           (0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
-#define AT91C_DBGU_TNPR           (0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
-#define AT91C_DBGU_TPR            (0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
-#define AT91C_DBGU_RPR            (0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
-#define AT91C_DBGU_RCR            (0xFFFFF304) // (PDC_DBGU) Receive Counter Register
-#define AT91C_DBGU_RNCR           (0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
-#define AT91C_DBGU_PTCR           (0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
-#define AT91C_DBGU_PTSR           (0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
-#define AT91C_DBGU_TNCR           (0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
-// ========== Register definition for DBGU peripheral ==========
-#define AT91C_DBGU_EXID           (0xFFFFF244) // (DBGU) Chip ID Extension Register
-#define AT91C_DBGU_BRGR           (0xFFFFF220) // (DBGU) Baud Rate Generator Register
-#define AT91C_DBGU_IDR            (0xFFFFF20C) // (DBGU) Interrupt Disable Register
-#define AT91C_DBGU_CSR            (0xFFFFF214) // (DBGU) Channel Status Register
-#define AT91C_DBGU_CIDR           (0xFFFFF240) // (DBGU) Chip ID Register
-#define AT91C_DBGU_MR             (0xFFFFF204) // (DBGU) Mode Register
-#define AT91C_DBGU_IMR            (0xFFFFF210) // (DBGU) Interrupt Mask Register
-#define AT91C_DBGU_CR             (0xFFFFF200) // (DBGU) Control Register
-#define AT91C_DBGU_FNTR           (0xFFFFF248) // (DBGU) Force NTRST Register
-#define AT91C_DBGU_THR            (0xFFFFF21C) // (DBGU) Transmitter Holding Register
-#define AT91C_DBGU_RHR            (0xFFFFF218) // (DBGU) Receiver Holding Register
-#define AT91C_DBGU_IER            (0xFFFFF208) // (DBGU) Interrupt Enable Register
-// ========== Register definition for PIOA peripheral ==========
-#define AT91C_PIOA_ODR            (0xFFFFF414) // (PIOA) Output Disable Registerr
-#define AT91C_PIOA_SODR           (0xFFFFF430) // (PIOA) Set Output Data Register
-#define AT91C_PIOA_ISR            (0xFFFFF44C) // (PIOA) Interrupt Status Register
-#define AT91C_PIOA_ABSR           (0xFFFFF478) // (PIOA) AB Select Status Register
-#define AT91C_PIOA_IER            (0xFFFFF440) // (PIOA) Interrupt Enable Register
-#define AT91C_PIOA_PPUDR          (0xFFFFF460) // (PIOA) Pull-up Disable Register
-#define AT91C_PIOA_IMR            (0xFFFFF448) // (PIOA) Interrupt Mask Register
-#define AT91C_PIOA_PER            (0xFFFFF400) // (PIOA) PIO Enable Register
-#define AT91C_PIOA_IFDR           (0xFFFFF424) // (PIOA) Input Filter Disable Register
-#define AT91C_PIOA_OWDR           (0xFFFFF4A4) // (PIOA) Output Write Disable Register
-#define AT91C_PIOA_MDSR           (0xFFFFF458) // (PIOA) Multi-driver Status Register
-#define AT91C_PIOA_IDR            (0xFFFFF444) // (PIOA) Interrupt Disable Register
-#define AT91C_PIOA_ODSR           (0xFFFFF438) // (PIOA) Output Data Status Register
-#define AT91C_PIOA_PPUSR          (0xFFFFF468) // (PIOA) Pull-up Status Register
-#define AT91C_PIOA_OWSR           (0xFFFFF4A8) // (PIOA) Output Write Status Register
-#define AT91C_PIOA_BSR            (0xFFFFF474) // (PIOA) Select B Register
-#define AT91C_PIOA_OWER           (0xFFFFF4A0) // (PIOA) Output Write Enable Register
-#define AT91C_PIOA_IFER           (0xFFFFF420) // (PIOA) Input Filter Enable Register
-#define AT91C_PIOA_PDSR           (0xFFFFF43C) // (PIOA) Pin Data Status Register
-#define AT91C_PIOA_PPUER          (0xFFFFF464) // (PIOA) Pull-up Enable Register
-#define AT91C_PIOA_OSR            (0xFFFFF418) // (PIOA) Output Status Register
-#define AT91C_PIOA_ASR            (0xFFFFF470) // (PIOA) Select A Register
-#define AT91C_PIOA_MDDR           (0xFFFFF454) // (PIOA) Multi-driver Disable Register
-#define AT91C_PIOA_CODR           (0xFFFFF434) // (PIOA) Clear Output Data Register
-#define AT91C_PIOA_MDER           (0xFFFFF450) // (PIOA) Multi-driver Enable Register
-#define AT91C_PIOA_PDR            (0xFFFFF404) // (PIOA) PIO Disable Register
-#define AT91C_PIOA_IFSR           (0xFFFFF428) // (PIOA) Input Filter Status Register
-#define AT91C_PIOA_OER            (0xFFFFF410) // (PIOA) Output Enable Register
-#define AT91C_PIOA_PSR            (0xFFFFF408) // (PIOA) PIO Status Register
-// ========== Register definition for PIOB peripheral ==========
-#define AT91C_PIOB_OWDR           (0xFFFFF6A4) // (PIOB) Output Write Disable Register
-#define AT91C_PIOB_MDER           (0xFFFFF650) // (PIOB) Multi-driver Enable Register
-#define AT91C_PIOB_PPUSR          (0xFFFFF668) // (PIOB) Pull-up Status Register
-#define AT91C_PIOB_IMR            (0xFFFFF648) // (PIOB) Interrupt Mask Register
-#define AT91C_PIOB_ASR            (0xFFFFF670) // (PIOB) Select A Register
-#define AT91C_PIOB_PPUDR          (0xFFFFF660) // (PIOB) Pull-up Disable Register
-#define AT91C_PIOB_PSR            (0xFFFFF608) // (PIOB) PIO Status Register
-#define AT91C_PIOB_IER            (0xFFFFF640) // (PIOB) Interrupt Enable Register
-#define AT91C_PIOB_CODR           (0xFFFFF634) // (PIOB) Clear Output Data Register
-#define AT91C_PIOB_OWER           (0xFFFFF6A0) // (PIOB) Output Write Enable Register
-#define AT91C_PIOB_ABSR           (0xFFFFF678) // (PIOB) AB Select Status Register
-#define AT91C_PIOB_IFDR           (0xFFFFF624) // (PIOB) Input Filter Disable Register
-#define AT91C_PIOB_PDSR           (0xFFFFF63C) // (PIOB) Pin Data Status Register
-#define AT91C_PIOB_IDR            (0xFFFFF644) // (PIOB) Interrupt Disable Register
-#define AT91C_PIOB_OWSR           (0xFFFFF6A8) // (PIOB) Output Write Status Register
-#define AT91C_PIOB_PDR            (0xFFFFF604) // (PIOB) PIO Disable Register
-#define AT91C_PIOB_ODR            (0xFFFFF614) // (PIOB) Output Disable Registerr
-#define AT91C_PIOB_IFSR           (0xFFFFF628) // (PIOB) Input Filter Status Register
-#define AT91C_PIOB_PPUER          (0xFFFFF664) // (PIOB) Pull-up Enable Register
-#define AT91C_PIOB_SODR           (0xFFFFF630) // (PIOB) Set Output Data Register
-#define AT91C_PIOB_ISR            (0xFFFFF64C) // (PIOB) Interrupt Status Register
-#define AT91C_PIOB_ODSR           (0xFFFFF638) // (PIOB) Output Data Status Register
-#define AT91C_PIOB_OSR            (0xFFFFF618) // (PIOB) Output Status Register
-#define AT91C_PIOB_MDSR           (0xFFFFF658) // (PIOB) Multi-driver Status Register
-#define AT91C_PIOB_IFER           (0xFFFFF620) // (PIOB) Input Filter Enable Register
-#define AT91C_PIOB_BSR            (0xFFFFF674) // (PIOB) Select B Register
-#define AT91C_PIOB_MDDR           (0xFFFFF654) // (PIOB) Multi-driver Disable Register
-#define AT91C_PIOB_OER            (0xFFFFF610) // (PIOB) Output Enable Register
-#define AT91C_PIOB_PER            (0xFFFFF600) // (PIOB) PIO Enable Register
-// ========== Register definition for CKGR peripheral ==========
-#define AT91C_CKGR_MOR            (0xFFFFFC20) // (CKGR) Main Oscillator Register
-#define AT91C_CKGR_PLLR           (0xFFFFFC2C) // (CKGR) PLL Register
-#define AT91C_CKGR_MCFR           (0xFFFFFC24) // (CKGR) Main Clock  Frequency Register
-// ========== Register definition for PMC peripheral ==========
-#define AT91C_PMC_IDR             (0xFFFFFC64) // (PMC) Interrupt Disable Register
-#define AT91C_PMC_MOR             (0xFFFFFC20) // (PMC) Main Oscillator Register
-#define AT91C_PMC_PLLR            (0xFFFFFC2C) // (PMC) PLL Register
-#define AT91C_PMC_PCER            (0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
-#define AT91C_PMC_PCKR            (0xFFFFFC40) // (PMC) Programmable Clock Register
-#define AT91C_PMC_MCKR            (0xFFFFFC30) // (PMC) Master Clock Register
-#define AT91C_PMC_SCDR            (0xFFFFFC04) // (PMC) System Clock Disable Register
-#define AT91C_PMC_PCDR            (0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
-#define AT91C_PMC_SCSR            (0xFFFFFC08) // (PMC) System Clock Status Register
-#define AT91C_PMC_PCSR            (0xFFFFFC18) // (PMC) Peripheral Clock Status Register
-#define AT91C_PMC_MCFR            (0xFFFFFC24) // (PMC) Main Clock  Frequency Register
-#define AT91C_PMC_SCER            (0xFFFFFC00) // (PMC) System Clock Enable Register
-#define AT91C_PMC_IMR             (0xFFFFFC6C) // (PMC) Interrupt Mask Register
-#define AT91C_PMC_IER             (0xFFFFFC60) // (PMC) Interrupt Enable Register
-#define AT91C_PMC_SR              (0xFFFFFC68) // (PMC) Status Register
-// ========== Register definition for RSTC peripheral ==========
-#define AT91C_RSTC_RCR            (0xFFFFFD00) // (RSTC) Reset Control Register
-#define AT91C_RSTC_RMR            (0xFFFFFD08) // (RSTC) Reset Mode Register
-#define AT91C_RSTC_RSR            (0xFFFFFD04) // (RSTC) Reset Status Register
-// ========== Register definition for RTTC peripheral ==========
-#define AT91C_RTTC_RTSR           (0xFFFFFD2C) // (RTTC) Real-time Status Register
-#define AT91C_RTTC_RTMR           (0xFFFFFD20) // (RTTC) Real-time Mode Register
-#define AT91C_RTTC_RTVR           (0xFFFFFD28) // (RTTC) Real-time Value Register
-#define AT91C_RTTC_RTAR           (0xFFFFFD24) // (RTTC) Real-time Alarm Register
-// ========== Register definition for PITC peripheral ==========
-#define AT91C_PITC_PIVR           (0xFFFFFD38) // (PITC) Period Interval Value Register
-#define AT91C_PITC_PISR           (0xFFFFFD34) // (PITC) Period Interval Status Register
-#define AT91C_PITC_PIIR           (0xFFFFFD3C) // (PITC) Period Interval Image Register
-#define AT91C_PITC_PIMR           (0xFFFFFD30) // (PITC) Period Interval Mode Register
-// ========== Register definition for WDTC peripheral ==========
-#define AT91C_WDTC_WDCR           (0xFFFFFD40) // (WDTC) Watchdog Control Register
-#define AT91C_WDTC_WDSR           (0xFFFFFD48) // (WDTC) Watchdog Status Register
-#define AT91C_WDTC_WDMR           (0xFFFFFD44) // (WDTC) Watchdog Mode Register
-// ========== Register definition for VREG peripheral ==========
-#define AT91C_VREG_MR             (0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
-// ========== Register definition for MC peripheral ==========
-#define AT91C_MC_ASR              (0xFFFFFF04) // (MC) MC Abort Status Register
-#define AT91C_MC_RCR              (0xFFFFFF00) // (MC) MC Remap Control Register
-#define AT91C_MC_FCR              (0xFFFFFF64) // (MC) MC Flash Command Register
-#define AT91C_MC_AASR             (0xFFFFFF08) // (MC) MC Abort Address Status Register
-#define AT91C_MC_FSR              (0xFFFFFF68) // (MC) MC Flash Status Register
-#define AT91C_MC_FMR              (0xFFFFFF60) // (MC) MC Flash Mode Register
-// ========== Register definition for PDC_SPI1 peripheral ==========
-#define AT91C_SPI1_PTCR           (0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register
-#define AT91C_SPI1_RPR            (0xFFFE4100) // (PDC_SPI1) Receive Pointer Register
-#define AT91C_SPI1_TNCR           (0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register
-#define AT91C_SPI1_TPR            (0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register
-#define AT91C_SPI1_TNPR           (0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register
-#define AT91C_SPI1_TCR            (0xFFFE410C) // (PDC_SPI1) Transmit Counter Register
-#define AT91C_SPI1_RCR            (0xFFFE4104) // (PDC_SPI1) Receive Counter Register
-#define AT91C_SPI1_RNPR           (0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register
-#define AT91C_SPI1_RNCR           (0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register
-#define AT91C_SPI1_PTSR           (0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register
-// ========== Register definition for SPI1 peripheral ==========
-#define AT91C_SPI1_IMR            (0xFFFE401C) // (SPI1) Interrupt Mask Register
-#define AT91C_SPI1_IER            (0xFFFE4014) // (SPI1) Interrupt Enable Register
-#define AT91C_SPI1_MR             (0xFFFE4004) // (SPI1) Mode Register
-#define AT91C_SPI1_RDR            (0xFFFE4008) // (SPI1) Receive Data Register
-#define AT91C_SPI1_IDR            (0xFFFE4018) // (SPI1) Interrupt Disable Register
-#define AT91C_SPI1_SR             (0xFFFE4010) // (SPI1) Status Register
-#define AT91C_SPI1_TDR            (0xFFFE400C) // (SPI1) Transmit Data Register
-#define AT91C_SPI1_CR             (0xFFFE4000) // (SPI1) Control Register
-#define AT91C_SPI1_CSR            (0xFFFE4030) // (SPI1) Chip Select Register
-// ========== Register definition for PDC_SPI0 peripheral ==========
-#define AT91C_SPI0_PTCR           (0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register
-#define AT91C_SPI0_TPR            (0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register
-#define AT91C_SPI0_TCR            (0xFFFE010C) // (PDC_SPI0) Transmit Counter Register
-#define AT91C_SPI0_RCR            (0xFFFE0104) // (PDC_SPI0) Receive Counter Register
-#define AT91C_SPI0_PTSR           (0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register
-#define AT91C_SPI0_RNPR           (0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register
-#define AT91C_SPI0_RPR            (0xFFFE0100) // (PDC_SPI0) Receive Pointer Register
-#define AT91C_SPI0_TNCR           (0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register
-#define AT91C_SPI0_RNCR           (0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register
-#define AT91C_SPI0_TNPR           (0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register
-// ========== Register definition for SPI0 peripheral ==========
-#define AT91C_SPI0_IER            (0xFFFE0014) // (SPI0) Interrupt Enable Register
-#define AT91C_SPI0_SR             (0xFFFE0010) // (SPI0) Status Register
-#define AT91C_SPI0_IDR            (0xFFFE0018) // (SPI0) Interrupt Disable Register
-#define AT91C_SPI0_CR             (0xFFFE0000) // (SPI0) Control Register
-#define AT91C_SPI0_MR             (0xFFFE0004) // (SPI0) Mode Register
-#define AT91C_SPI0_IMR            (0xFFFE001C) // (SPI0) Interrupt Mask Register
-#define AT91C_SPI0_TDR            (0xFFFE000C) // (SPI0) Transmit Data Register
-#define AT91C_SPI0_RDR            (0xFFFE0008) // (SPI0) Receive Data Register
-#define AT91C_SPI0_CSR            (0xFFFE0030) // (SPI0) Chip Select Register
-// ========== Register definition for PDC_US1 peripheral ==========
-#define AT91C_US1_RNCR            (0xFFFC4114) // (PDC_US1) Receive Next Counter Register
-#define AT91C_US1_PTCR            (0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
-#define AT91C_US1_TCR             (0xFFFC410C) // (PDC_US1) Transmit Counter Register
-#define AT91C_US1_PTSR            (0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
-#define AT91C_US1_TNPR            (0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
-#define AT91C_US1_RCR             (0xFFFC4104) // (PDC_US1) Receive Counter Register
-#define AT91C_US1_RNPR            (0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
-#define AT91C_US1_RPR             (0xFFFC4100) // (PDC_US1) Receive Pointer Register
-#define AT91C_US1_TNCR            (0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
-#define AT91C_US1_TPR             (0xFFFC4108) // (PDC_US1) Transmit Pointer Register
-// ========== Register definition for US1 peripheral ==========
-#define AT91C_US1_IF              (0xFFFC404C) // (US1) IRDA_FILTER Register
-#define AT91C_US1_NER             (0xFFFC4044) // (US1) Nb Errors Register
-#define AT91C_US1_RTOR            (0xFFFC4024) // (US1) Receiver Time-out Register
-#define AT91C_US1_CSR             (0xFFFC4014) // (US1) Channel Status Register
-#define AT91C_US1_IDR             (0xFFFC400C) // (US1) Interrupt Disable Register
-#define AT91C_US1_IER             (0xFFFC4008) // (US1) Interrupt Enable Register
-#define AT91C_US1_THR             (0xFFFC401C) // (US1) Transmitter Holding Register
-#define AT91C_US1_TTGR            (0xFFFC4028) // (US1) Transmitter Time-guard Register
-#define AT91C_US1_RHR             (0xFFFC4018) // (US1) Receiver Holding Register
-#define AT91C_US1_BRGR            (0xFFFC4020) // (US1) Baud Rate Generator Register
-#define AT91C_US1_IMR             (0xFFFC4010) // (US1) Interrupt Mask Register
-#define AT91C_US1_FIDI            (0xFFFC4040) // (US1) FI_DI_Ratio Register
-#define AT91C_US1_CR              (0xFFFC4000) // (US1) Control Register
-#define AT91C_US1_MR              (0xFFFC4004) // (US1) Mode Register
-// ========== Register definition for PDC_US0 peripheral ==========
-#define AT91C_US0_TNPR            (0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
-#define AT91C_US0_RNPR            (0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
-#define AT91C_US0_TCR             (0xFFFC010C) // (PDC_US0) Transmit Counter Register
-#define AT91C_US0_PTCR            (0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
-#define AT91C_US0_PTSR            (0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
-#define AT91C_US0_TNCR            (0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
-#define AT91C_US0_TPR             (0xFFFC0108) // (PDC_US0) Transmit Pointer Register
-#define AT91C_US0_RCR             (0xFFFC0104) // (PDC_US0) Receive Counter Register
-#define AT91C_US0_RPR             (0xFFFC0100) // (PDC_US0) Receive Pointer Register
-#define AT91C_US0_RNCR            (0xFFFC0114) // (PDC_US0) Receive Next Counter Register
-// ========== Register definition for US0 peripheral ==========
-#define AT91C_US0_BRGR            (0xFFFC0020) // (US0) Baud Rate Generator Register
-#define AT91C_US0_NER             (0xFFFC0044) // (US0) Nb Errors Register
-#define AT91C_US0_CR              (0xFFFC0000) // (US0) Control Register
-#define AT91C_US0_IMR             (0xFFFC0010) // (US0) Interrupt Mask Register
-#define AT91C_US0_FIDI            (0xFFFC0040) // (US0) FI_DI_Ratio Register
-#define AT91C_US0_TTGR            (0xFFFC0028) // (US0) Transmitter Time-guard Register
-#define AT91C_US0_MR              (0xFFFC0004) // (US0) Mode Register
-#define AT91C_US0_RTOR            (0xFFFC0024) // (US0) Receiver Time-out Register
-#define AT91C_US0_CSR             (0xFFFC0014) // (US0) Channel Status Register
-#define AT91C_US0_RHR             (0xFFFC0018) // (US0) Receiver Holding Register
-#define AT91C_US0_IDR             (0xFFFC000C) // (US0) Interrupt Disable Register
-#define AT91C_US0_THR             (0xFFFC001C) // (US0) Transmitter Holding Register
-#define AT91C_US0_IF              (0xFFFC004C) // (US0) IRDA_FILTER Register
-#define AT91C_US0_IER             (0xFFFC0008) // (US0) Interrupt Enable Register
-// ========== Register definition for PDC_SSC peripheral ==========
-#define AT91C_SSC_TNCR            (0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
-#define AT91C_SSC_RPR             (0xFFFD4100) // (PDC_SSC) Receive Pointer Register
-#define AT91C_SSC_RNCR            (0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
-#define AT91C_SSC_TPR             (0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
-#define AT91C_SSC_PTCR            (0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
-#define AT91C_SSC_TCR             (0xFFFD410C) // (PDC_SSC) Transmit Counter Register
-#define AT91C_SSC_RCR             (0xFFFD4104) // (PDC_SSC) Receive Counter Register
-#define AT91C_SSC_RNPR            (0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
-#define AT91C_SSC_TNPR            (0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
-#define AT91C_SSC_PTSR            (0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
-// ========== Register definition for SSC peripheral ==========
-#define AT91C_SSC_RHR             (0xFFFD4020) // (SSC) Receive Holding Register
-#define AT91C_SSC_RSHR            (0xFFFD4030) // (SSC) Receive Sync Holding Register
-#define AT91C_SSC_TFMR            (0xFFFD401C) // (SSC) Transmit Frame Mode Register
-#define AT91C_SSC_IDR             (0xFFFD4048) // (SSC) Interrupt Disable Register
-#define AT91C_SSC_THR             (0xFFFD4024) // (SSC) Transmit Holding Register
-#define AT91C_SSC_RCMR            (0xFFFD4010) // (SSC) Receive Clock ModeRegister
-#define AT91C_SSC_IER             (0xFFFD4044) // (SSC) Interrupt Enable Register
-#define AT91C_SSC_TSHR            (0xFFFD4034) // (SSC) Transmit Sync Holding Register
-#define AT91C_SSC_SR              (0xFFFD4040) // (SSC) Status Register
-#define AT91C_SSC_CMR             (0xFFFD4004) // (SSC) Clock Mode Register
-#define AT91C_SSC_TCMR            (0xFFFD4018) // (SSC) Transmit Clock Mode Register
-#define AT91C_SSC_CR              (0xFFFD4000) // (SSC) Control Register
-#define AT91C_SSC_IMR             (0xFFFD404C) // (SSC) Interrupt Mask Register
-#define AT91C_SSC_RFMR            (0xFFFD4014) // (SSC) Receive Frame Mode Register
-// ========== Register definition for TWI peripheral ==========
-#define AT91C_TWI_IER             (0xFFFB8024) // (TWI) Interrupt Enable Register
-#define AT91C_TWI_CR              (0xFFFB8000) // (TWI) Control Register
-#define AT91C_TWI_SR              (0xFFFB8020) // (TWI) Status Register
-#define AT91C_TWI_IMR             (0xFFFB802C) // (TWI) Interrupt Mask Register
-#define AT91C_TWI_THR             (0xFFFB8034) // (TWI) Transmit Holding Register
-#define AT91C_TWI_IDR             (0xFFFB8028) // (TWI) Interrupt Disable Register
-#define AT91C_TWI_IADR            (0xFFFB800C) // (TWI) Internal Address Register
-#define AT91C_TWI_MMR             (0xFFFB8004) // (TWI) Master Mode Register
-#define AT91C_TWI_CWGR            (0xFFFB8010) // (TWI) Clock Waveform Generator Register
-#define AT91C_TWI_RHR             (0xFFFB8030) // (TWI) Receive Holding Register
-// ========== Register definition for PWMC_CH3 peripheral ==========
-#define AT91C_PWMC_CH3_CUPDR      (0xFFFCC270) // (PWMC_CH3) Channel Update Register
-#define AT91C_PWMC_CH3_Reserved   (0xFFFCC274) // (PWMC_CH3) Reserved
-#define AT91C_PWMC_CH3_CPRDR      (0xFFFCC268) // (PWMC_CH3) Channel Period Register
-#define AT91C_PWMC_CH3_CDTYR      (0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
-#define AT91C_PWMC_CH3_CCNTR      (0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
-#define AT91C_PWMC_CH3_CMR        (0xFFFCC260) // (PWMC_CH3) Channel Mode Register
-// ========== Register definition for PWMC_CH2 peripheral ==========
-#define AT91C_PWMC_CH2_Reserved   (0xFFFCC254) // (PWMC_CH2) Reserved
-#define AT91C_PWMC_CH2_CMR        (0xFFFCC240) // (PWMC_CH2) Channel Mode Register
-#define AT91C_PWMC_CH2_CCNTR      (0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
-#define AT91C_PWMC_CH2_CPRDR      (0xFFFCC248) // (PWMC_CH2) Channel Period Register
-#define AT91C_PWMC_CH2_CUPDR      (0xFFFCC250) // (PWMC_CH2) Channel Update Register
-#define AT91C_PWMC_CH2_CDTYR      (0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
-// ========== Register definition for PWMC_CH1 peripheral ==========
-#define AT91C_PWMC_CH1_Reserved   (0xFFFCC234) // (PWMC_CH1) Reserved
-#define AT91C_PWMC_CH1_CUPDR      (0xFFFCC230) // (PWMC_CH1) Channel Update Register
-#define AT91C_PWMC_CH1_CPRDR      (0xFFFCC228) // (PWMC_CH1) Channel Period Register
-#define AT91C_PWMC_CH1_CCNTR      (0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
-#define AT91C_PWMC_CH1_CDTYR      (0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
-#define AT91C_PWMC_CH1_CMR        (0xFFFCC220) // (PWMC_CH1) Channel Mode Register
-// ========== Register definition for PWMC_CH0 peripheral ==========
-#define AT91C_PWMC_CH0_Reserved   (0xFFFCC214) // (PWMC_CH0) Reserved
-#define AT91C_PWMC_CH0_CPRDR      (0xFFFCC208) // (PWMC_CH0) Channel Period Register
-#define AT91C_PWMC_CH0_CDTYR      (0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
-#define AT91C_PWMC_CH0_CMR        (0xFFFCC200) // (PWMC_CH0) Channel Mode Register
-#define AT91C_PWMC_CH0_CUPDR      (0xFFFCC210) // (PWMC_CH0) Channel Update Register
-#define AT91C_PWMC_CH0_CCNTR      (0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
-// ========== Register definition for PWMC peripheral ==========
-#define AT91C_PWMC_IDR            (0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
-#define AT91C_PWMC_DIS            (0xFFFCC008) // (PWMC) PWMC Disable Register
-#define AT91C_PWMC_IER            (0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
-#define AT91C_PWMC_VR             (0xFFFCC0FC) // (PWMC) PWMC Version Register
-#define AT91C_PWMC_ISR            (0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
-#define AT91C_PWMC_SR             (0xFFFCC00C) // (PWMC) PWMC Status Register
-#define AT91C_PWMC_IMR            (0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
-#define AT91C_PWMC_MR             (0xFFFCC000) // (PWMC) PWMC Mode Register
-#define AT91C_PWMC_ENA            (0xFFFCC004) // (PWMC) PWMC Enable Register
-// ========== Register definition for UDP peripheral ==========
-#define AT91C_UDP_IMR             (0xFFFB0018) // (UDP) Interrupt Mask Register
-#define AT91C_UDP_FADDR           (0xFFFB0008) // (UDP) Function Address Register
-#define AT91C_UDP_NUM             (0xFFFB0000) // (UDP) Frame Number Register
-#define AT91C_UDP_FDR             (0xFFFB0050) // (UDP) Endpoint FIFO Data Register
-#define AT91C_UDP_ISR             (0xFFFB001C) // (UDP) Interrupt Status Register
-#define AT91C_UDP_CSR             (0xFFFB0030) // (UDP) Endpoint Control and Status Register
-#define AT91C_UDP_IDR             (0xFFFB0014) // (UDP) Interrupt Disable Register
-#define AT91C_UDP_ICR             (0xFFFB0020) // (UDP) Interrupt Clear Register
-#define AT91C_UDP_RSTEP           (0xFFFB0028) // (UDP) Reset Endpoint Register
-#define AT91C_UDP_TXVC            (0xFFFB0074) // (UDP) Transceiver Control Register
-#define AT91C_UDP_GLBSTATE        (0xFFFB0004) // (UDP) Global State Register
-#define AT91C_UDP_IER             (0xFFFB0010) // (UDP) Interrupt Enable Register
-// ========== Register definition for TC0 peripheral ==========
-#define AT91C_TC0_SR              (0xFFFA0020) // (TC0) Status Register
-#define AT91C_TC0_RC              (0xFFFA001C) // (TC0) Register C
-#define AT91C_TC0_RB              (0xFFFA0018) // (TC0) Register B
-#define AT91C_TC0_CCR             (0xFFFA0000) // (TC0) Channel Control Register
-#define AT91C_TC0_CMR             (0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC0_IER             (0xFFFA0024) // (TC0) Interrupt Enable Register
-#define AT91C_TC0_RA              (0xFFFA0014) // (TC0) Register A
-#define AT91C_TC0_IDR             (0xFFFA0028) // (TC0) Interrupt Disable Register
-#define AT91C_TC0_CV              (0xFFFA0010) // (TC0) Counter Value
-#define AT91C_TC0_IMR             (0xFFFA002C) // (TC0) Interrupt Mask Register
-// ========== Register definition for TC1 peripheral ==========
-#define AT91C_TC1_RB              (0xFFFA0058) // (TC1) Register B
-#define AT91C_TC1_CCR             (0xFFFA0040) // (TC1) Channel Control Register
-#define AT91C_TC1_IER             (0xFFFA0064) // (TC1) Interrupt Enable Register
-#define AT91C_TC1_IDR             (0xFFFA0068) // (TC1) Interrupt Disable Register
-#define AT91C_TC1_SR              (0xFFFA0060) // (TC1) Status Register
-#define AT91C_TC1_CMR             (0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC1_RA              (0xFFFA0054) // (TC1) Register A
-#define AT91C_TC1_RC              (0xFFFA005C) // (TC1) Register C
-#define AT91C_TC1_IMR             (0xFFFA006C) // (TC1) Interrupt Mask Register
-#define AT91C_TC1_CV              (0xFFFA0050) // (TC1) Counter Value
-// ========== Register definition for TC2 peripheral ==========
-#define AT91C_TC2_CMR             (0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC2_CCR             (0xFFFA0080) // (TC2) Channel Control Register
-#define AT91C_TC2_CV              (0xFFFA0090) // (TC2) Counter Value
-#define AT91C_TC2_RA              (0xFFFA0094) // (TC2) Register A
-#define AT91C_TC2_RB              (0xFFFA0098) // (TC2) Register B
-#define AT91C_TC2_IDR             (0xFFFA00A8) // (TC2) Interrupt Disable Register
-#define AT91C_TC2_IMR             (0xFFFA00AC) // (TC2) Interrupt Mask Register
-#define AT91C_TC2_RC              (0xFFFA009C) // (TC2) Register C
-#define AT91C_TC2_IER             (0xFFFA00A4) // (TC2) Interrupt Enable Register
-#define AT91C_TC2_SR              (0xFFFA00A0) // (TC2) Status Register
-// ========== Register definition for TCB peripheral ==========
-#define AT91C_TCB_BMR             (0xFFFA00C4) // (TCB) TC Block Mode Register
-#define AT91C_TCB_BCR             (0xFFFA00C0) // (TCB) TC Block Control Register
-// ========== Register definition for CAN_MB0 peripheral ==========
-#define AT91C_CAN_MB0_MDL         (0xFFFD0214) // (CAN_MB0) MailBox Data Low Register
-#define AT91C_CAN_MB0_MAM         (0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB0_MCR         (0xFFFD021C) // (CAN_MB0) MailBox Control Register
-#define AT91C_CAN_MB0_MID         (0xFFFD0208) // (CAN_MB0) MailBox ID Register
-#define AT91C_CAN_MB0_MSR         (0xFFFD0210) // (CAN_MB0) MailBox Status Register
-#define AT91C_CAN_MB0_MFID        (0xFFFD020C) // (CAN_MB0) MailBox Family ID Register
-#define AT91C_CAN_MB0_MDH         (0xFFFD0218) // (CAN_MB0) MailBox Data High Register
-#define AT91C_CAN_MB0_MMR         (0xFFFD0200) // (CAN_MB0) MailBox Mode Register
-// ========== Register definition for CAN_MB1 peripheral ==========
-#define AT91C_CAN_MB1_MDL         (0xFFFD0234) // (CAN_MB1) MailBox Data Low Register
-#define AT91C_CAN_MB1_MID         (0xFFFD0228) // (CAN_MB1) MailBox ID Register
-#define AT91C_CAN_MB1_MMR         (0xFFFD0220) // (CAN_MB1) MailBox Mode Register
-#define AT91C_CAN_MB1_MSR         (0xFFFD0230) // (CAN_MB1) MailBox Status Register
-#define AT91C_CAN_MB1_MAM         (0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB1_MDH         (0xFFFD0238) // (CAN_MB1) MailBox Data High Register
-#define AT91C_CAN_MB1_MCR         (0xFFFD023C) // (CAN_MB1) MailBox Control Register
-#define AT91C_CAN_MB1_MFID        (0xFFFD022C) // (CAN_MB1) MailBox Family ID Register
-// ========== Register definition for CAN_MB2 peripheral ==========
-#define AT91C_CAN_MB2_MCR         (0xFFFD025C) // (CAN_MB2) MailBox Control Register
-#define AT91C_CAN_MB2_MDH         (0xFFFD0258) // (CAN_MB2) MailBox Data High Register
-#define AT91C_CAN_MB2_MID         (0xFFFD0248) // (CAN_MB2) MailBox ID Register
-#define AT91C_CAN_MB2_MDL         (0xFFFD0254) // (CAN_MB2) MailBox Data Low Register
-#define AT91C_CAN_MB2_MMR         (0xFFFD0240) // (CAN_MB2) MailBox Mode Register
-#define AT91C_CAN_MB2_MAM         (0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB2_MFID        (0xFFFD024C) // (CAN_MB2) MailBox Family ID Register
-#define AT91C_CAN_MB2_MSR         (0xFFFD0250) // (CAN_MB2) MailBox Status Register
-// ========== Register definition for CAN_MB3 peripheral ==========
-#define AT91C_CAN_MB3_MFID        (0xFFFD026C) // (CAN_MB3) MailBox Family ID Register
-#define AT91C_CAN_MB3_MAM         (0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB3_MID         (0xFFFD0268) // (CAN_MB3) MailBox ID Register
-#define AT91C_CAN_MB3_MCR         (0xFFFD027C) // (CAN_MB3) MailBox Control Register
-#define AT91C_CAN_MB3_MMR         (0xFFFD0260) // (CAN_MB3) MailBox Mode Register
-#define AT91C_CAN_MB3_MSR         (0xFFFD0270) // (CAN_MB3) MailBox Status Register
-#define AT91C_CAN_MB3_MDL         (0xFFFD0274) // (CAN_MB3) MailBox Data Low Register
-#define AT91C_CAN_MB3_MDH         (0xFFFD0278) // (CAN_MB3) MailBox Data High Register
-// ========== Register definition for CAN_MB4 peripheral ==========
-#define AT91C_CAN_MB4_MID         (0xFFFD0288) // (CAN_MB4) MailBox ID Register
-#define AT91C_CAN_MB4_MMR         (0xFFFD0280) // (CAN_MB4) MailBox Mode Register
-#define AT91C_CAN_MB4_MDH         (0xFFFD0298) // (CAN_MB4) MailBox Data High Register
-#define AT91C_CAN_MB4_MFID        (0xFFFD028C) // (CAN_MB4) MailBox Family ID Register
-#define AT91C_CAN_MB4_MSR         (0xFFFD0290) // (CAN_MB4) MailBox Status Register
-#define AT91C_CAN_MB4_MCR         (0xFFFD029C) // (CAN_MB4) MailBox Control Register
-#define AT91C_CAN_MB4_MDL         (0xFFFD0294) // (CAN_MB4) MailBox Data Low Register
-#define AT91C_CAN_MB4_MAM         (0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register
-// ========== Register definition for CAN_MB5 peripheral ==========
-#define AT91C_CAN_MB5_MSR         (0xFFFD02B0) // (CAN_MB5) MailBox Status Register
-#define AT91C_CAN_MB5_MCR         (0xFFFD02BC) // (CAN_MB5) MailBox Control Register
-#define AT91C_CAN_MB5_MFID        (0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register
-#define AT91C_CAN_MB5_MDH         (0xFFFD02B8) // (CAN_MB5) MailBox Data High Register
-#define AT91C_CAN_MB5_MID         (0xFFFD02A8) // (CAN_MB5) MailBox ID Register
-#define AT91C_CAN_MB5_MMR         (0xFFFD02A0) // (CAN_MB5) MailBox Mode Register
-#define AT91C_CAN_MB5_MDL         (0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register
-#define AT91C_CAN_MB5_MAM         (0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register
-// ========== Register definition for CAN_MB6 peripheral ==========
-#define AT91C_CAN_MB6_MFID        (0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register
-#define AT91C_CAN_MB6_MID         (0xFFFD02C8) // (CAN_MB6) MailBox ID Register
-#define AT91C_CAN_MB6_MAM         (0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB6_MSR         (0xFFFD02D0) // (CAN_MB6) MailBox Status Register
-#define AT91C_CAN_MB6_MDL         (0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register
-#define AT91C_CAN_MB6_MCR         (0xFFFD02DC) // (CAN_MB6) MailBox Control Register
-#define AT91C_CAN_MB6_MDH         (0xFFFD02D8) // (CAN_MB6) MailBox Data High Register
-#define AT91C_CAN_MB6_MMR         (0xFFFD02C0) // (CAN_MB6) MailBox Mode Register
-// ========== Register definition for CAN_MB7 peripheral ==========
-#define AT91C_CAN_MB7_MCR         (0xFFFD02FC) // (CAN_MB7) MailBox Control Register
-#define AT91C_CAN_MB7_MDH         (0xFFFD02F8) // (CAN_MB7) MailBox Data High Register
-#define AT91C_CAN_MB7_MFID        (0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register
-#define AT91C_CAN_MB7_MDL         (0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register
-#define AT91C_CAN_MB7_MID         (0xFFFD02E8) // (CAN_MB7) MailBox ID Register
-#define AT91C_CAN_MB7_MMR         (0xFFFD02E0) // (CAN_MB7) MailBox Mode Register
-#define AT91C_CAN_MB7_MAM         (0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB7_MSR         (0xFFFD02F0) // (CAN_MB7) MailBox Status Register
-// ========== Register definition for CAN peripheral ==========
-#define AT91C_CAN_TCR             (0xFFFD0024) // (CAN) Transfer Command Register
-#define AT91C_CAN_IMR             (0xFFFD000C) // (CAN) Interrupt Mask Register
-#define AT91C_CAN_IER             (0xFFFD0004) // (CAN) Interrupt Enable Register
-#define AT91C_CAN_ECR             (0xFFFD0020) // (CAN) Error Counter Register
-#define AT91C_CAN_TIMESTP         (0xFFFD001C) // (CAN) Time Stamp Register
-#define AT91C_CAN_MR              (0xFFFD0000) // (CAN) Mode Register
-#define AT91C_CAN_IDR             (0xFFFD0008) // (CAN) Interrupt Disable Register
-#define AT91C_CAN_ACR             (0xFFFD0028) // (CAN) Abort Command Register
-#define AT91C_CAN_TIM             (0xFFFD0018) // (CAN) Timer Register
-#define AT91C_CAN_SR              (0xFFFD0010) // (CAN) Status Register
-#define AT91C_CAN_BR              (0xFFFD0014) // (CAN) Baudrate Register
-#define AT91C_CAN_VR              (0xFFFD00FC) // (CAN) Version Register
-// ========== Register definition for EMAC peripheral ==========
-#define AT91C_EMAC_ISR            (0xFFFDC024) // (EMAC) Interrupt Status Register
-#define AT91C_EMAC_SA4H           (0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes
-#define AT91C_EMAC_SA1L           (0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes
-#define AT91C_EMAC_ELE            (0xFFFDC078) // (EMAC) Excessive Length Errors Register
-#define AT91C_EMAC_LCOL           (0xFFFDC05C) // (EMAC) Late Collision Register
-#define AT91C_EMAC_RLE            (0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register
-#define AT91C_EMAC_WOL            (0xFFFDC0C4) // (EMAC) Wake On LAN Register
-#define AT91C_EMAC_DTF            (0xFFFDC058) // (EMAC) Deferred Transmission Frame Register
-#define AT91C_EMAC_TUND           (0xFFFDC064) // (EMAC) Transmit Underrun Error Register
-#define AT91C_EMAC_NCR            (0xFFFDC000) // (EMAC) Network Control Register
-#define AT91C_EMAC_SA4L           (0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes
-#define AT91C_EMAC_RSR            (0xFFFDC020) // (EMAC) Receive Status Register
-#define AT91C_EMAC_SA3L           (0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes
-#define AT91C_EMAC_TSR            (0xFFFDC014) // (EMAC) Transmit Status Register
-#define AT91C_EMAC_IDR            (0xFFFDC02C) // (EMAC) Interrupt Disable Register
-#define AT91C_EMAC_RSE            (0xFFFDC074) // (EMAC) Receive Symbol Errors Register
-#define AT91C_EMAC_ECOL           (0xFFFDC060) // (EMAC) Excessive Collision Register
-#define AT91C_EMAC_TID            (0xFFFDC0B8) // (EMAC) Type ID Checking Register
-#define AT91C_EMAC_HRB            (0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]
-#define AT91C_EMAC_TBQP           (0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer
-#define AT91C_EMAC_USRIO          (0xFFFDC0C0) // (EMAC) USER Input/Output Register
-#define AT91C_EMAC_PTR            (0xFFFDC038) // (EMAC) Pause Time Register
-#define AT91C_EMAC_SA2H           (0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes
-#define AT91C_EMAC_ROV            (0xFFFDC070) // (EMAC) Receive Overrun Errors Register
-#define AT91C_EMAC_ALE            (0xFFFDC054) // (EMAC) Alignment Error Register
-#define AT91C_EMAC_RJA            (0xFFFDC07C) // (EMAC) Receive Jabbers Register
-#define AT91C_EMAC_RBQP           (0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer
-#define AT91C_EMAC_TPF            (0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register
-#define AT91C_EMAC_NCFGR          (0xFFFDC004) // (EMAC) Network Configuration Register
-#define AT91C_EMAC_HRT            (0xFFFDC094) // (EMAC) Hash Address Top[63:32]
-#define AT91C_EMAC_USF            (0xFFFDC080) // (EMAC) Undersize Frames Register
-#define AT91C_EMAC_FCSE           (0xFFFDC050) // (EMAC) Frame Check Sequence Error Register
-#define AT91C_EMAC_TPQ            (0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register
-#define AT91C_EMAC_MAN            (0xFFFDC034) // (EMAC) PHY Maintenance Register
-#define AT91C_EMAC_FTO            (0xFFFDC040) // (EMAC) Frames Transmitted OK Register
-#define AT91C_EMAC_REV            (0xFFFDC0FC) // (EMAC) Revision Register
-#define AT91C_EMAC_IMR            (0xFFFDC030) // (EMAC) Interrupt Mask Register
-#define AT91C_EMAC_SCF            (0xFFFDC044) // (EMAC) Single Collision Frame Register
-#define AT91C_EMAC_PFR            (0xFFFDC03C) // (EMAC) Pause Frames received Register
-#define AT91C_EMAC_MCF            (0xFFFDC048) // (EMAC) Multiple Collision Frame Register
-#define AT91C_EMAC_NSR            (0xFFFDC008) // (EMAC) Network Status Register
-#define AT91C_EMAC_SA2L           (0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes
-#define AT91C_EMAC_FRO            (0xFFFDC04C) // (EMAC) Frames Received OK Register
-#define AT91C_EMAC_IER            (0xFFFDC028) // (EMAC) Interrupt Enable Register
-#define AT91C_EMAC_SA1H           (0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes
-#define AT91C_EMAC_CSE            (0xFFFDC068) // (EMAC) Carrier Sense Error Register
-#define AT91C_EMAC_SA3H           (0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes
-#define AT91C_EMAC_RRE            (0xFFFDC06C) // (EMAC) Receive Ressource Error Register
-#define AT91C_EMAC_STE            (0xFFFDC084) // (EMAC) SQE Test Error Register
-// ========== Register definition for PDC_ADC peripheral ==========
-#define AT91C_ADC_PTSR            (0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
-#define AT91C_ADC_PTCR            (0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
-#define AT91C_ADC_TNPR            (0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
-#define AT91C_ADC_TNCR            (0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
-#define AT91C_ADC_RNPR            (0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
-#define AT91C_ADC_RNCR            (0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
-#define AT91C_ADC_RPR             (0xFFFD8100) // (PDC_ADC) Receive Pointer Register
-#define AT91C_ADC_TCR             (0xFFFD810C) // (PDC_ADC) Transmit Counter Register
-#define AT91C_ADC_TPR             (0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
-#define AT91C_ADC_RCR             (0xFFFD8104) // (PDC_ADC) Receive Counter Register
-// ========== Register definition for ADC peripheral ==========
-#define AT91C_ADC_CDR2            (0xFFFD8038) // (ADC) ADC Channel Data Register 2
-#define AT91C_ADC_CDR3            (0xFFFD803C) // (ADC) ADC Channel Data Register 3
-#define AT91C_ADC_CDR0            (0xFFFD8030) // (ADC) ADC Channel Data Register 0
-#define AT91C_ADC_CDR5            (0xFFFD8044) // (ADC) ADC Channel Data Register 5
-#define AT91C_ADC_CHDR            (0xFFFD8014) // (ADC) ADC Channel Disable Register
-#define AT91C_ADC_SR              (0xFFFD801C) // (ADC) ADC Status Register
-#define AT91C_ADC_CDR4            (0xFFFD8040) // (ADC) ADC Channel Data Register 4
-#define AT91C_ADC_CDR1            (0xFFFD8034) // (ADC) ADC Channel Data Register 1
-#define AT91C_ADC_LCDR            (0xFFFD8020) // (ADC) ADC Last Converted Data Register
-#define AT91C_ADC_IDR             (0xFFFD8028) // (ADC) ADC Interrupt Disable Register
-#define AT91C_ADC_CR              (0xFFFD8000) // (ADC) ADC Control Register
-#define AT91C_ADC_CDR7            (0xFFFD804C) // (ADC) ADC Channel Data Register 7
-#define AT91C_ADC_CDR6            (0xFFFD8048) // (ADC) ADC Channel Data Register 6
-#define AT91C_ADC_IER             (0xFFFD8024) // (ADC) ADC Interrupt Enable Register
-#define AT91C_ADC_CHER            (0xFFFD8010) // (ADC) ADC Channel Enable Register
-#define AT91C_ADC_CHSR            (0xFFFD8018) // (ADC) ADC Channel Status Register
-#define AT91C_ADC_MR              (0xFFFD8004) // (ADC) ADC Mode Register
-#define AT91C_ADC_IMR             (0xFFFD802C) // (ADC) ADC Interrupt Mask Register
-// ========== Register definition for PDC_AES peripheral ==========
-#define AT91C_AES_TPR             (0xFFFA4108) // (PDC_AES) Transmit Pointer Register
-#define AT91C_AES_PTCR            (0xFFFA4120) // (PDC_AES) PDC Transfer Control Register
-#define AT91C_AES_RNPR            (0xFFFA4110) // (PDC_AES) Receive Next Pointer Register
-#define AT91C_AES_TNCR            (0xFFFA411C) // (PDC_AES) Transmit Next Counter Register
-#define AT91C_AES_TCR             (0xFFFA410C) // (PDC_AES) Transmit Counter Register
-#define AT91C_AES_RCR             (0xFFFA4104) // (PDC_AES) Receive Counter Register
-#define AT91C_AES_RNCR            (0xFFFA4114) // (PDC_AES) Receive Next Counter Register
-#define AT91C_AES_TNPR            (0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register
-#define AT91C_AES_RPR             (0xFFFA4100) // (PDC_AES) Receive Pointer Register
-#define AT91C_AES_PTSR            (0xFFFA4124) // (PDC_AES) PDC Transfer Status Register
-// ========== Register definition for AES peripheral ==========
-#define AT91C_AES_IVxR            (0xFFFA4060) // (AES) Initialization Vector x Register
-#define AT91C_AES_MR              (0xFFFA4004) // (AES) Mode Register
-#define AT91C_AES_VR              (0xFFFA40FC) // (AES) AES Version Register
-#define AT91C_AES_ODATAxR         (0xFFFA4050) // (AES) Output Data x Register
-#define AT91C_AES_IDATAxR         (0xFFFA4040) // (AES) Input Data x Register
-#define AT91C_AES_CR              (0xFFFA4000) // (AES) Control Register
-#define AT91C_AES_IDR             (0xFFFA4014) // (AES) Interrupt Disable Register
-#define AT91C_AES_IMR             (0xFFFA4018) // (AES) Interrupt Mask Register
-#define AT91C_AES_IER             (0xFFFA4010) // (AES) Interrupt Enable Register
-#define AT91C_AES_KEYWxR          (0xFFFA4020) // (AES) Key Word x Register
-#define AT91C_AES_ISR             (0xFFFA401C) // (AES) Interrupt Status Register
-// ========== Register definition for PDC_TDES peripheral ==========
-#define AT91C_TDES_RNCR           (0xFFFA8114) // (PDC_TDES) Receive Next Counter Register
-#define AT91C_TDES_TCR            (0xFFFA810C) // (PDC_TDES) Transmit Counter Register
-#define AT91C_TDES_RCR            (0xFFFA8104) // (PDC_TDES) Receive Counter Register
-#define AT91C_TDES_TNPR           (0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register
-#define AT91C_TDES_RNPR           (0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register
-#define AT91C_TDES_RPR            (0xFFFA8100) // (PDC_TDES) Receive Pointer Register
-#define AT91C_TDES_TNCR           (0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register
-#define AT91C_TDES_TPR            (0xFFFA8108) // (PDC_TDES) Transmit Pointer Register
-#define AT91C_TDES_PTSR           (0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register
-#define AT91C_TDES_PTCR           (0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register
-// ========== Register definition for TDES peripheral ==========
-#define AT91C_TDES_KEY2WxR        (0xFFFA8028) // (TDES) Key 2 Word x Register
-#define AT91C_TDES_KEY3WxR        (0xFFFA8030) // (TDES) Key 3 Word x Register
-#define AT91C_TDES_IDR            (0xFFFA8014) // (TDES) Interrupt Disable Register
-#define AT91C_TDES_VR             (0xFFFA80FC) // (TDES) TDES Version Register
-#define AT91C_TDES_IVxR           (0xFFFA8060) // (TDES) Initialization Vector x Register
-#define AT91C_TDES_ODATAxR        (0xFFFA8050) // (TDES) Output Data x Register
-#define AT91C_TDES_IMR            (0xFFFA8018) // (TDES) Interrupt Mask Register
-#define AT91C_TDES_MR             (0xFFFA8004) // (TDES) Mode Register
-#define AT91C_TDES_CR             (0xFFFA8000) // (TDES) Control Register
-#define AT91C_TDES_IER            (0xFFFA8010) // (TDES) Interrupt Enable Register
-#define AT91C_TDES_ISR            (0xFFFA801C) // (TDES) Interrupt Status Register
-#define AT91C_TDES_IDATAxR        (0xFFFA8040) // (TDES) Input Data x Register
-#define AT91C_TDES_KEY1WxR        (0xFFFA8020) // (TDES) Key 1 Word x Register
+/* ***************************************************************************** */
+/*               REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 */
+/* ***************************************************************************** */
+/* ========== Register definition for SYS peripheral ========== */
+/* ========== Register definition for AIC peripheral ========== */
+#define AT91C_AIC_IVR              ( 0xFFFFF100 ) /* (AIC) IRQ Vector Register */
+#define AT91C_AIC_SMR              ( 0xFFFFF000 ) /* (AIC) Source Mode Register */
+#define AT91C_AIC_FVR              ( 0xFFFFF104 ) /* (AIC) FIQ Vector Register */
+#define AT91C_AIC_DCR              ( 0xFFFFF138 ) /* (AIC) Debug Control Register (Protect) */
+#define AT91C_AIC_EOICR            ( 0xFFFFF130 ) /* (AIC) End of Interrupt Command Register */
+#define AT91C_AIC_SVR              ( 0xFFFFF080 ) /* (AIC) Source Vector Register */
+#define AT91C_AIC_FFSR             ( 0xFFFFF148 ) /* (AIC) Fast Forcing Status Register */
+#define AT91C_AIC_ICCR             ( 0xFFFFF128 ) /* (AIC) Interrupt Clear Command Register */
+#define AT91C_AIC_ISR              ( 0xFFFFF108 ) /* (AIC) Interrupt Status Register */
+#define AT91C_AIC_IMR              ( 0xFFFFF110 ) /* (AIC) Interrupt Mask Register */
+#define AT91C_AIC_IPR              ( 0xFFFFF10C ) /* (AIC) Interrupt Pending Register */
+#define AT91C_AIC_FFER             ( 0xFFFFF140 ) /* (AIC) Fast Forcing Enable Register */
+#define AT91C_AIC_IECR             ( 0xFFFFF120 ) /* (AIC) Interrupt Enable Command Register */
+#define AT91C_AIC_ISCR             ( 0xFFFFF12C ) /* (AIC) Interrupt Set Command Register */
+#define AT91C_AIC_FFDR             ( 0xFFFFF144 ) /* (AIC) Fast Forcing Disable Register */
+#define AT91C_AIC_CISR             ( 0xFFFFF114 ) /* (AIC) Core Interrupt Status Register */
+#define AT91C_AIC_IDCR             ( 0xFFFFF124 ) /* (AIC) Interrupt Disable Command Register */
+#define AT91C_AIC_SPU              ( 0xFFFFF134 ) /* (AIC) Spurious Vector Register */
+/* ========== Register definition for PDC_DBGU peripheral ========== */
+#define AT91C_DBGU_TCR             ( 0xFFFFF30C ) /* (PDC_DBGU) Transmit Counter Register */
+#define AT91C_DBGU_RNPR            ( 0xFFFFF310 ) /* (PDC_DBGU) Receive Next Pointer Register */
+#define AT91C_DBGU_TNPR            ( 0xFFFFF318 ) /* (PDC_DBGU) Transmit Next Pointer Register */
+#define AT91C_DBGU_TPR             ( 0xFFFFF308 ) /* (PDC_DBGU) Transmit Pointer Register */
+#define AT91C_DBGU_RPR             ( 0xFFFFF300 ) /* (PDC_DBGU) Receive Pointer Register */
+#define AT91C_DBGU_RCR             ( 0xFFFFF304 ) /* (PDC_DBGU) Receive Counter Register */
+#define AT91C_DBGU_RNCR            ( 0xFFFFF314 ) /* (PDC_DBGU) Receive Next Counter Register */
+#define AT91C_DBGU_PTCR            ( 0xFFFFF320 ) /* (PDC_DBGU) PDC Transfer Control Register */
+#define AT91C_DBGU_PTSR            ( 0xFFFFF324 ) /* (PDC_DBGU) PDC Transfer Status Register */
+#define AT91C_DBGU_TNCR            ( 0xFFFFF31C ) /* (PDC_DBGU) Transmit Next Counter Register */
+/* ========== Register definition for DBGU peripheral ========== */
+#define AT91C_DBGU_EXID            ( 0xFFFFF244 ) /* (DBGU) Chip ID Extension Register */
+#define AT91C_DBGU_BRGR            ( 0xFFFFF220 ) /* (DBGU) Baud Rate Generator Register */
+#define AT91C_DBGU_IDR             ( 0xFFFFF20C ) /* (DBGU) Interrupt Disable Register */
+#define AT91C_DBGU_CSR             ( 0xFFFFF214 ) /* (DBGU) Channel Status Register */
+#define AT91C_DBGU_CIDR            ( 0xFFFFF240 ) /* (DBGU) Chip ID Register */
+#define AT91C_DBGU_MR              ( 0xFFFFF204 ) /* (DBGU) Mode Register */
+#define AT91C_DBGU_IMR             ( 0xFFFFF210 ) /* (DBGU) Interrupt Mask Register */
+#define AT91C_DBGU_CR              ( 0xFFFFF200 ) /* (DBGU) Control Register */
+#define AT91C_DBGU_FNTR            ( 0xFFFFF248 ) /* (DBGU) Force NTRST Register */
+#define AT91C_DBGU_THR             ( 0xFFFFF21C ) /* (DBGU) Transmitter Holding Register */
+#define AT91C_DBGU_RHR             ( 0xFFFFF218 ) /* (DBGU) Receiver Holding Register */
+#define AT91C_DBGU_IER             ( 0xFFFFF208 ) /* (DBGU) Interrupt Enable Register */
+/* ========== Register definition for PIOA peripheral ========== */
+#define AT91C_PIOA_ODR             ( 0xFFFFF414 ) /* (PIOA) Output Disable Registerr */
+#define AT91C_PIOA_SODR            ( 0xFFFFF430 ) /* (PIOA) Set Output Data Register */
+#define AT91C_PIOA_ISR             ( 0xFFFFF44C ) /* (PIOA) Interrupt Status Register */
+#define AT91C_PIOA_ABSR            ( 0xFFFFF478 ) /* (PIOA) AB Select Status Register */
+#define AT91C_PIOA_IER             ( 0xFFFFF440 ) /* (PIOA) Interrupt Enable Register */
+#define AT91C_PIOA_PPUDR           ( 0xFFFFF460 ) /* (PIOA) Pull-up Disable Register */
+#define AT91C_PIOA_IMR             ( 0xFFFFF448 ) /* (PIOA) Interrupt Mask Register */
+#define AT91C_PIOA_PER             ( 0xFFFFF400 ) /* (PIOA) PIO Enable Register */
+#define AT91C_PIOA_IFDR            ( 0xFFFFF424 ) /* (PIOA) Input Filter Disable Register */
+#define AT91C_PIOA_OWDR            ( 0xFFFFF4A4 ) /* (PIOA) Output Write Disable Register */
+#define AT91C_PIOA_MDSR            ( 0xFFFFF458 ) /* (PIOA) Multi-driver Status Register */
+#define AT91C_PIOA_IDR             ( 0xFFFFF444 ) /* (PIOA) Interrupt Disable Register */
+#define AT91C_PIOA_ODSR            ( 0xFFFFF438 ) /* (PIOA) Output Data Status Register */
+#define AT91C_PIOA_PPUSR           ( 0xFFFFF468 ) /* (PIOA) Pull-up Status Register */
+#define AT91C_PIOA_OWSR            ( 0xFFFFF4A8 ) /* (PIOA) Output Write Status Register */
+#define AT91C_PIOA_BSR             ( 0xFFFFF474 ) /* (PIOA) Select B Register */
+#define AT91C_PIOA_OWER            ( 0xFFFFF4A0 ) /* (PIOA) Output Write Enable Register */
+#define AT91C_PIOA_IFER            ( 0xFFFFF420 ) /* (PIOA) Input Filter Enable Register */
+#define AT91C_PIOA_PDSR            ( 0xFFFFF43C ) /* (PIOA) Pin Data Status Register */
+#define AT91C_PIOA_PPUER           ( 0xFFFFF464 ) /* (PIOA) Pull-up Enable Register */
+#define AT91C_PIOA_OSR             ( 0xFFFFF418 ) /* (PIOA) Output Status Register */
+#define AT91C_PIOA_ASR             ( 0xFFFFF470 ) /* (PIOA) Select A Register */
+#define AT91C_PIOA_MDDR            ( 0xFFFFF454 ) /* (PIOA) Multi-driver Disable Register */
+#define AT91C_PIOA_CODR            ( 0xFFFFF434 ) /* (PIOA) Clear Output Data Register */
+#define AT91C_PIOA_MDER            ( 0xFFFFF450 ) /* (PIOA) Multi-driver Enable Register */
+#define AT91C_PIOA_PDR             ( 0xFFFFF404 ) /* (PIOA) PIO Disable Register */
+#define AT91C_PIOA_IFSR            ( 0xFFFFF428 ) /* (PIOA) Input Filter Status Register */
+#define AT91C_PIOA_OER             ( 0xFFFFF410 ) /* (PIOA) Output Enable Register */
+#define AT91C_PIOA_PSR             ( 0xFFFFF408 ) /* (PIOA) PIO Status Register */
+/* ========== Register definition for PIOB peripheral ========== */
+#define AT91C_PIOB_OWDR            ( 0xFFFFF6A4 ) /* (PIOB) Output Write Disable Register */
+#define AT91C_PIOB_MDER            ( 0xFFFFF650 ) /* (PIOB) Multi-driver Enable Register */
+#define AT91C_PIOB_PPUSR           ( 0xFFFFF668 ) /* (PIOB) Pull-up Status Register */
+#define AT91C_PIOB_IMR             ( 0xFFFFF648 ) /* (PIOB) Interrupt Mask Register */
+#define AT91C_PIOB_ASR             ( 0xFFFFF670 ) /* (PIOB) Select A Register */
+#define AT91C_PIOB_PPUDR           ( 0xFFFFF660 ) /* (PIOB) Pull-up Disable Register */
+#define AT91C_PIOB_PSR             ( 0xFFFFF608 ) /* (PIOB) PIO Status Register */
+#define AT91C_PIOB_IER             ( 0xFFFFF640 ) /* (PIOB) Interrupt Enable Register */
+#define AT91C_PIOB_CODR            ( 0xFFFFF634 ) /* (PIOB) Clear Output Data Register */
+#define AT91C_PIOB_OWER            ( 0xFFFFF6A0 ) /* (PIOB) Output Write Enable Register */
+#define AT91C_PIOB_ABSR            ( 0xFFFFF678 ) /* (PIOB) AB Select Status Register */
+#define AT91C_PIOB_IFDR            ( 0xFFFFF624 ) /* (PIOB) Input Filter Disable Register */
+#define AT91C_PIOB_PDSR            ( 0xFFFFF63C ) /* (PIOB) Pin Data Status Register */
+#define AT91C_PIOB_IDR             ( 0xFFFFF644 ) /* (PIOB) Interrupt Disable Register */
+#define AT91C_PIOB_OWSR            ( 0xFFFFF6A8 ) /* (PIOB) Output Write Status Register */
+#define AT91C_PIOB_PDR             ( 0xFFFFF604 ) /* (PIOB) PIO Disable Register */
+#define AT91C_PIOB_ODR             ( 0xFFFFF614 ) /* (PIOB) Output Disable Registerr */
+#define AT91C_PIOB_IFSR            ( 0xFFFFF628 ) /* (PIOB) Input Filter Status Register */
+#define AT91C_PIOB_PPUER           ( 0xFFFFF664 ) /* (PIOB) Pull-up Enable Register */
+#define AT91C_PIOB_SODR            ( 0xFFFFF630 ) /* (PIOB) Set Output Data Register */
+#define AT91C_PIOB_ISR             ( 0xFFFFF64C ) /* (PIOB) Interrupt Status Register */
+#define AT91C_PIOB_ODSR            ( 0xFFFFF638 ) /* (PIOB) Output Data Status Register */
+#define AT91C_PIOB_OSR             ( 0xFFFFF618 ) /* (PIOB) Output Status Register */
+#define AT91C_PIOB_MDSR            ( 0xFFFFF658 ) /* (PIOB) Multi-driver Status Register */
+#define AT91C_PIOB_IFER            ( 0xFFFFF620 ) /* (PIOB) Input Filter Enable Register */
+#define AT91C_PIOB_BSR             ( 0xFFFFF674 ) /* (PIOB) Select B Register */
+#define AT91C_PIOB_MDDR            ( 0xFFFFF654 ) /* (PIOB) Multi-driver Disable Register */
+#define AT91C_PIOB_OER             ( 0xFFFFF610 ) /* (PIOB) Output Enable Register */
+#define AT91C_PIOB_PER             ( 0xFFFFF600 ) /* (PIOB) PIO Enable Register */
+/* ========== Register definition for CKGR peripheral ========== */
+#define AT91C_CKGR_MOR             ( 0xFFFFFC20 ) /* (CKGR) Main Oscillator Register */
+#define AT91C_CKGR_PLLR            ( 0xFFFFFC2C ) /* (CKGR) PLL Register */
+#define AT91C_CKGR_MCFR            ( 0xFFFFFC24 ) /* (CKGR) Main Clock  Frequency Register */
+/* ========== Register definition for PMC peripheral ========== */
+#define AT91C_PMC_IDR              ( 0xFFFFFC64 ) /* (PMC) Interrupt Disable Register */
+#define AT91C_PMC_MOR              ( 0xFFFFFC20 ) /* (PMC) Main Oscillator Register */
+#define AT91C_PMC_PLLR             ( 0xFFFFFC2C ) /* (PMC) PLL Register */
+#define AT91C_PMC_PCER             ( 0xFFFFFC10 ) /* (PMC) Peripheral Clock Enable Register */
+#define AT91C_PMC_PCKR             ( 0xFFFFFC40 ) /* (PMC) Programmable Clock Register */
+#define AT91C_PMC_MCKR             ( 0xFFFFFC30 ) /* (PMC) Master Clock Register */
+#define AT91C_PMC_SCDR             ( 0xFFFFFC04 ) /* (PMC) System Clock Disable Register */
+#define AT91C_PMC_PCDR             ( 0xFFFFFC14 ) /* (PMC) Peripheral Clock Disable Register */
+#define AT91C_PMC_SCSR             ( 0xFFFFFC08 ) /* (PMC) System Clock Status Register */
+#define AT91C_PMC_PCSR             ( 0xFFFFFC18 ) /* (PMC) Peripheral Clock Status Register */
+#define AT91C_PMC_MCFR             ( 0xFFFFFC24 ) /* (PMC) Main Clock  Frequency Register */
+#define AT91C_PMC_SCER             ( 0xFFFFFC00 ) /* (PMC) System Clock Enable Register */
+#define AT91C_PMC_IMR              ( 0xFFFFFC6C ) /* (PMC) Interrupt Mask Register */
+#define AT91C_PMC_IER              ( 0xFFFFFC60 ) /* (PMC) Interrupt Enable Register */
+#define AT91C_PMC_SR               ( 0xFFFFFC68 ) /* (PMC) Status Register */
+/* ========== Register definition for RSTC peripheral ========== */
+#define AT91C_RSTC_RCR             ( 0xFFFFFD00 ) /* (RSTC) Reset Control Register */
+#define AT91C_RSTC_RMR             ( 0xFFFFFD08 ) /* (RSTC) Reset Mode Register */
+#define AT91C_RSTC_RSR             ( 0xFFFFFD04 ) /* (RSTC) Reset Status Register */
+/* ========== Register definition for RTTC peripheral ========== */
+#define AT91C_RTTC_RTSR            ( 0xFFFFFD2C ) /* (RTTC) Real-time Status Register */
+#define AT91C_RTTC_RTMR            ( 0xFFFFFD20 ) /* (RTTC) Real-time Mode Register */
+#define AT91C_RTTC_RTVR            ( 0xFFFFFD28 ) /* (RTTC) Real-time Value Register */
+#define AT91C_RTTC_RTAR            ( 0xFFFFFD24 ) /* (RTTC) Real-time Alarm Register */
+/* ========== Register definition for PITC peripheral ========== */
+#define AT91C_PITC_PIVR            ( 0xFFFFFD38 ) /* (PITC) Period Interval Value Register */
+#define AT91C_PITC_PISR            ( 0xFFFFFD34 ) /* (PITC) Period Interval Status Register */
+#define AT91C_PITC_PIIR            ( 0xFFFFFD3C ) /* (PITC) Period Interval Image Register */
+#define AT91C_PITC_PIMR            ( 0xFFFFFD30 ) /* (PITC) Period Interval Mode Register */
+/* ========== Register definition for WDTC peripheral ========== */
+#define AT91C_WDTC_WDCR            ( 0xFFFFFD40 ) /* (WDTC) Watchdog Control Register */
+#define AT91C_WDTC_WDSR            ( 0xFFFFFD48 ) /* (WDTC) Watchdog Status Register */
+#define AT91C_WDTC_WDMR            ( 0xFFFFFD44 ) /* (WDTC) Watchdog Mode Register */
+/* ========== Register definition for VREG peripheral ========== */
+#define AT91C_VREG_MR              ( 0xFFFFFD60 ) /* (VREG) Voltage Regulator Mode Register */
+/* ========== Register definition for MC peripheral ========== */
+#define AT91C_MC_ASR               ( 0xFFFFFF04 ) /* (MC) MC Abort Status Register */
+#define AT91C_MC_RCR               ( 0xFFFFFF00 ) /* (MC) MC Remap Control Register */
+#define AT91C_MC_FCR               ( 0xFFFFFF64 ) /* (MC) MC Flash Command Register */
+#define AT91C_MC_AASR              ( 0xFFFFFF08 ) /* (MC) MC Abort Address Status Register */
+#define AT91C_MC_FSR               ( 0xFFFFFF68 ) /* (MC) MC Flash Status Register */
+#define AT91C_MC_FMR               ( 0xFFFFFF60 ) /* (MC) MC Flash Mode Register */
+/* ========== Register definition for PDC_SPI1 peripheral ========== */
+#define AT91C_SPI1_PTCR            ( 0xFFFE4120 ) /* (PDC_SPI1) PDC Transfer Control Register */
+#define AT91C_SPI1_RPR             ( 0xFFFE4100 ) /* (PDC_SPI1) Receive Pointer Register */
+#define AT91C_SPI1_TNCR            ( 0xFFFE411C ) /* (PDC_SPI1) Transmit Next Counter Register */
+#define AT91C_SPI1_TPR             ( 0xFFFE4108 ) /* (PDC_SPI1) Transmit Pointer Register */
+#define AT91C_SPI1_TNPR            ( 0xFFFE4118 ) /* (PDC_SPI1) Transmit Next Pointer Register */
+#define AT91C_SPI1_TCR             ( 0xFFFE410C ) /* (PDC_SPI1) Transmit Counter Register */
+#define AT91C_SPI1_RCR             ( 0xFFFE4104 ) /* (PDC_SPI1) Receive Counter Register */
+#define AT91C_SPI1_RNPR            ( 0xFFFE4110 ) /* (PDC_SPI1) Receive Next Pointer Register */
+#define AT91C_SPI1_RNCR            ( 0xFFFE4114 ) /* (PDC_SPI1) Receive Next Counter Register */
+#define AT91C_SPI1_PTSR            ( 0xFFFE4124 ) /* (PDC_SPI1) PDC Transfer Status Register */
+/* ========== Register definition for SPI1 peripheral ========== */
+#define AT91C_SPI1_IMR             ( 0xFFFE401C ) /* (SPI1) Interrupt Mask Register */
+#define AT91C_SPI1_IER             ( 0xFFFE4014 ) /* (SPI1) Interrupt Enable Register */
+#define AT91C_SPI1_MR              ( 0xFFFE4004 ) /* (SPI1) Mode Register */
+#define AT91C_SPI1_RDR             ( 0xFFFE4008 ) /* (SPI1) Receive Data Register */
+#define AT91C_SPI1_IDR             ( 0xFFFE4018 ) /* (SPI1) Interrupt Disable Register */
+#define AT91C_SPI1_SR              ( 0xFFFE4010 ) /* (SPI1) Status Register */
+#define AT91C_SPI1_TDR             ( 0xFFFE400C ) /* (SPI1) Transmit Data Register */
+#define AT91C_SPI1_CR              ( 0xFFFE4000 ) /* (SPI1) Control Register */
+#define AT91C_SPI1_CSR             ( 0xFFFE4030 ) /* (SPI1) Chip Select Register */
+/* ========== Register definition for PDC_SPI0 peripheral ========== */
+#define AT91C_SPI0_PTCR            ( 0xFFFE0120 ) /* (PDC_SPI0) PDC Transfer Control Register */
+#define AT91C_SPI0_TPR             ( 0xFFFE0108 ) /* (PDC_SPI0) Transmit Pointer Register */
+#define AT91C_SPI0_TCR             ( 0xFFFE010C ) /* (PDC_SPI0) Transmit Counter Register */
+#define AT91C_SPI0_RCR             ( 0xFFFE0104 ) /* (PDC_SPI0) Receive Counter Register */
+#define AT91C_SPI0_PTSR            ( 0xFFFE0124 ) /* (PDC_SPI0) PDC Transfer Status Register */
+#define AT91C_SPI0_RNPR            ( 0xFFFE0110 ) /* (PDC_SPI0) Receive Next Pointer Register */
+#define AT91C_SPI0_RPR             ( 0xFFFE0100 ) /* (PDC_SPI0) Receive Pointer Register */
+#define AT91C_SPI0_TNCR            ( 0xFFFE011C ) /* (PDC_SPI0) Transmit Next Counter Register */
+#define AT91C_SPI0_RNCR            ( 0xFFFE0114 ) /* (PDC_SPI0) Receive Next Counter Register */
+#define AT91C_SPI0_TNPR            ( 0xFFFE0118 ) /* (PDC_SPI0) Transmit Next Pointer Register */
+/* ========== Register definition for SPI0 peripheral ========== */
+#define AT91C_SPI0_IER             ( 0xFFFE0014 ) /* (SPI0) Interrupt Enable Register */
+#define AT91C_SPI0_SR              ( 0xFFFE0010 ) /* (SPI0) Status Register */
+#define AT91C_SPI0_IDR             ( 0xFFFE0018 ) /* (SPI0) Interrupt Disable Register */
+#define AT91C_SPI0_CR              ( 0xFFFE0000 ) /* (SPI0) Control Register */
+#define AT91C_SPI0_MR              ( 0xFFFE0004 ) /* (SPI0) Mode Register */
+#define AT91C_SPI0_IMR             ( 0xFFFE001C ) /* (SPI0) Interrupt Mask Register */
+#define AT91C_SPI0_TDR             ( 0xFFFE000C ) /* (SPI0) Transmit Data Register */
+#define AT91C_SPI0_RDR             ( 0xFFFE0008 ) /* (SPI0) Receive Data Register */
+#define AT91C_SPI0_CSR             ( 0xFFFE0030 ) /* (SPI0) Chip Select Register */
+/* ========== Register definition for PDC_US1 peripheral ========== */
+#define AT91C_US1_RNCR             ( 0xFFFC4114 ) /* (PDC_US1) Receive Next Counter Register */
+#define AT91C_US1_PTCR             ( 0xFFFC4120 ) /* (PDC_US1) PDC Transfer Control Register */
+#define AT91C_US1_TCR              ( 0xFFFC410C ) /* (PDC_US1) Transmit Counter Register */
+#define AT91C_US1_PTSR             ( 0xFFFC4124 ) /* (PDC_US1) PDC Transfer Status Register */
+#define AT91C_US1_TNPR             ( 0xFFFC4118 ) /* (PDC_US1) Transmit Next Pointer Register */
+#define AT91C_US1_RCR              ( 0xFFFC4104 ) /* (PDC_US1) Receive Counter Register */
+#define AT91C_US1_RNPR             ( 0xFFFC4110 ) /* (PDC_US1) Receive Next Pointer Register */
+#define AT91C_US1_RPR              ( 0xFFFC4100 ) /* (PDC_US1) Receive Pointer Register */
+#define AT91C_US1_TNCR             ( 0xFFFC411C ) /* (PDC_US1) Transmit Next Counter Register */
+#define AT91C_US1_TPR              ( 0xFFFC4108 ) /* (PDC_US1) Transmit Pointer Register */
+/* ========== Register definition for US1 peripheral ========== */
+#define AT91C_US1_IF               ( 0xFFFC404C ) /* (US1) IRDA_FILTER Register */
+#define AT91C_US1_NER              ( 0xFFFC4044 ) /* (US1) Nb Errors Register */
+#define AT91C_US1_RTOR             ( 0xFFFC4024 ) /* (US1) Receiver Time-out Register */
+#define AT91C_US1_CSR              ( 0xFFFC4014 ) /* (US1) Channel Status Register */
+#define AT91C_US1_IDR              ( 0xFFFC400C ) /* (US1) Interrupt Disable Register */
+#define AT91C_US1_IER              ( 0xFFFC4008 ) /* (US1) Interrupt Enable Register */
+#define AT91C_US1_THR              ( 0xFFFC401C ) /* (US1) Transmitter Holding Register */
+#define AT91C_US1_TTGR             ( 0xFFFC4028 ) /* (US1) Transmitter Time-guard Register */
+#define AT91C_US1_RHR              ( 0xFFFC4018 ) /* (US1) Receiver Holding Register */
+#define AT91C_US1_BRGR             ( 0xFFFC4020 ) /* (US1) Baud Rate Generator Register */
+#define AT91C_US1_IMR              ( 0xFFFC4010 ) /* (US1) Interrupt Mask Register */
+#define AT91C_US1_FIDI             ( 0xFFFC4040 ) /* (US1) FI_DI_Ratio Register */
+#define AT91C_US1_CR               ( 0xFFFC4000 ) /* (US1) Control Register */
+#define AT91C_US1_MR               ( 0xFFFC4004 ) /* (US1) Mode Register */
+/* ========== Register definition for PDC_US0 peripheral ========== */
+#define AT91C_US0_TNPR             ( 0xFFFC0118 ) /* (PDC_US0) Transmit Next Pointer Register */
+#define AT91C_US0_RNPR             ( 0xFFFC0110 ) /* (PDC_US0) Receive Next Pointer Register */
+#define AT91C_US0_TCR              ( 0xFFFC010C ) /* (PDC_US0) Transmit Counter Register */
+#define AT91C_US0_PTCR             ( 0xFFFC0120 ) /* (PDC_US0) PDC Transfer Control Register */
+#define AT91C_US0_PTSR             ( 0xFFFC0124 ) /* (PDC_US0) PDC Transfer Status Register */
+#define AT91C_US0_TNCR             ( 0xFFFC011C ) /* (PDC_US0) Transmit Next Counter Register */
+#define AT91C_US0_TPR              ( 0xFFFC0108 ) /* (PDC_US0) Transmit Pointer Register */
+#define AT91C_US0_RCR              ( 0xFFFC0104 ) /* (PDC_US0) Receive Counter Register */
+#define AT91C_US0_RPR              ( 0xFFFC0100 ) /* (PDC_US0) Receive Pointer Register */
+#define AT91C_US0_RNCR             ( 0xFFFC0114 ) /* (PDC_US0) Receive Next Counter Register */
+/* ========== Register definition for US0 peripheral ========== */
+#define AT91C_US0_BRGR             ( 0xFFFC0020 ) /* (US0) Baud Rate Generator Register */
+#define AT91C_US0_NER              ( 0xFFFC0044 ) /* (US0) Nb Errors Register */
+#define AT91C_US0_CR               ( 0xFFFC0000 ) /* (US0) Control Register */
+#define AT91C_US0_IMR              ( 0xFFFC0010 ) /* (US0) Interrupt Mask Register */
+#define AT91C_US0_FIDI             ( 0xFFFC0040 ) /* (US0) FI_DI_Ratio Register */
+#define AT91C_US0_TTGR             ( 0xFFFC0028 ) /* (US0) Transmitter Time-guard Register */
+#define AT91C_US0_MR               ( 0xFFFC0004 ) /* (US0) Mode Register */
+#define AT91C_US0_RTOR             ( 0xFFFC0024 ) /* (US0) Receiver Time-out Register */
+#define AT91C_US0_CSR              ( 0xFFFC0014 ) /* (US0) Channel Status Register */
+#define AT91C_US0_RHR              ( 0xFFFC0018 ) /* (US0) Receiver Holding Register */
+#define AT91C_US0_IDR              ( 0xFFFC000C ) /* (US0) Interrupt Disable Register */
+#define AT91C_US0_THR              ( 0xFFFC001C ) /* (US0) Transmitter Holding Register */
+#define AT91C_US0_IF               ( 0xFFFC004C ) /* (US0) IRDA_FILTER Register */
+#define AT91C_US0_IER              ( 0xFFFC0008 ) /* (US0) Interrupt Enable Register */
+/* ========== Register definition for PDC_SSC peripheral ========== */
+#define AT91C_SSC_TNCR             ( 0xFFFD411C ) /* (PDC_SSC) Transmit Next Counter Register */
+#define AT91C_SSC_RPR              ( 0xFFFD4100 ) /* (PDC_SSC) Receive Pointer Register */
+#define AT91C_SSC_RNCR             ( 0xFFFD4114 ) /* (PDC_SSC) Receive Next Counter Register */
+#define AT91C_SSC_TPR              ( 0xFFFD4108 ) /* (PDC_SSC) Transmit Pointer Register */
+#define AT91C_SSC_PTCR             ( 0xFFFD4120 ) /* (PDC_SSC) PDC Transfer Control Register */
+#define AT91C_SSC_TCR              ( 0xFFFD410C ) /* (PDC_SSC) Transmit Counter Register */
+#define AT91C_SSC_RCR              ( 0xFFFD4104 ) /* (PDC_SSC) Receive Counter Register */
+#define AT91C_SSC_RNPR             ( 0xFFFD4110 ) /* (PDC_SSC) Receive Next Pointer Register */
+#define AT91C_SSC_TNPR             ( 0xFFFD4118 ) /* (PDC_SSC) Transmit Next Pointer Register */
+#define AT91C_SSC_PTSR             ( 0xFFFD4124 ) /* (PDC_SSC) PDC Transfer Status Register */
+/* ========== Register definition for SSC peripheral ========== */
+#define AT91C_SSC_RHR              ( 0xFFFD4020 ) /* (SSC) Receive Holding Register */
+#define AT91C_SSC_RSHR             ( 0xFFFD4030 ) /* (SSC) Receive Sync Holding Register */
+#define AT91C_SSC_TFMR             ( 0xFFFD401C ) /* (SSC) Transmit Frame Mode Register */
+#define AT91C_SSC_IDR              ( 0xFFFD4048 ) /* (SSC) Interrupt Disable Register */
+#define AT91C_SSC_THR              ( 0xFFFD4024 ) /* (SSC) Transmit Holding Register */
+#define AT91C_SSC_RCMR             ( 0xFFFD4010 ) /* (SSC) Receive Clock ModeRegister */
+#define AT91C_SSC_IER              ( 0xFFFD4044 ) /* (SSC) Interrupt Enable Register */
+#define AT91C_SSC_TSHR             ( 0xFFFD4034 ) /* (SSC) Transmit Sync Holding Register */
+#define AT91C_SSC_SR               ( 0xFFFD4040 ) /* (SSC) Status Register */
+#define AT91C_SSC_CMR              ( 0xFFFD4004 ) /* (SSC) Clock Mode Register */
+#define AT91C_SSC_TCMR             ( 0xFFFD4018 ) /* (SSC) Transmit Clock Mode Register */
+#define AT91C_SSC_CR               ( 0xFFFD4000 ) /* (SSC) Control Register */
+#define AT91C_SSC_IMR              ( 0xFFFD404C ) /* (SSC) Interrupt Mask Register */
+#define AT91C_SSC_RFMR             ( 0xFFFD4014 ) /* (SSC) Receive Frame Mode Register */
+/* ========== Register definition for TWI peripheral ========== */
+#define AT91C_TWI_IER              ( 0xFFFB8024 ) /* (TWI) Interrupt Enable Register */
+#define AT91C_TWI_CR               ( 0xFFFB8000 ) /* (TWI) Control Register */
+#define AT91C_TWI_SR               ( 0xFFFB8020 ) /* (TWI) Status Register */
+#define AT91C_TWI_IMR              ( 0xFFFB802C ) /* (TWI) Interrupt Mask Register */
+#define AT91C_TWI_THR              ( 0xFFFB8034 ) /* (TWI) Transmit Holding Register */
+#define AT91C_TWI_IDR              ( 0xFFFB8028 ) /* (TWI) Interrupt Disable Register */
+#define AT91C_TWI_IADR             ( 0xFFFB800C ) /* (TWI) Internal Address Register */
+#define AT91C_TWI_MMR              ( 0xFFFB8004 ) /* (TWI) Master Mode Register */
+#define AT91C_TWI_CWGR             ( 0xFFFB8010 ) /* (TWI) Clock Waveform Generator Register */
+#define AT91C_TWI_RHR              ( 0xFFFB8030 ) /* (TWI) Receive Holding Register */
+/* ========== Register definition for PWMC_CH3 peripheral ========== */
+#define AT91C_PWMC_CH3_CUPDR       ( 0xFFFCC270 ) /* (PWMC_CH3) Channel Update Register */
+#define AT91C_PWMC_CH3_Reserved    ( 0xFFFCC274 ) /* (PWMC_CH3) Reserved */
+#define AT91C_PWMC_CH3_CPRDR       ( 0xFFFCC268 ) /* (PWMC_CH3) Channel Period Register */
+#define AT91C_PWMC_CH3_CDTYR       ( 0xFFFCC264 ) /* (PWMC_CH3) Channel Duty Cycle Register */
+#define AT91C_PWMC_CH3_CCNTR       ( 0xFFFCC26C ) /* (PWMC_CH3) Channel Counter Register */
+#define AT91C_PWMC_CH3_CMR         ( 0xFFFCC260 ) /* (PWMC_CH3) Channel Mode Register */
+/* ========== Register definition for PWMC_CH2 peripheral ========== */
+#define AT91C_PWMC_CH2_Reserved    ( 0xFFFCC254 ) /* (PWMC_CH2) Reserved */
+#define AT91C_PWMC_CH2_CMR         ( 0xFFFCC240 ) /* (PWMC_CH2) Channel Mode Register */
+#define AT91C_PWMC_CH2_CCNTR       ( 0xFFFCC24C ) /* (PWMC_CH2) Channel Counter Register */
+#define AT91C_PWMC_CH2_CPRDR       ( 0xFFFCC248 ) /* (PWMC_CH2) Channel Period Register */
+#define AT91C_PWMC_CH2_CUPDR       ( 0xFFFCC250 ) /* (PWMC_CH2) Channel Update Register */
+#define AT91C_PWMC_CH2_CDTYR       ( 0xFFFCC244 ) /* (PWMC_CH2) Channel Duty Cycle Register */
+/* ========== Register definition for PWMC_CH1 peripheral ========== */
+#define AT91C_PWMC_CH1_Reserved    ( 0xFFFCC234 ) /* (PWMC_CH1) Reserved */
+#define AT91C_PWMC_CH1_CUPDR       ( 0xFFFCC230 ) /* (PWMC_CH1) Channel Update Register */
+#define AT91C_PWMC_CH1_CPRDR       ( 0xFFFCC228 ) /* (PWMC_CH1) Channel Period Register */
+#define AT91C_PWMC_CH1_CCNTR       ( 0xFFFCC22C ) /* (PWMC_CH1) Channel Counter Register */
+#define AT91C_PWMC_CH1_CDTYR       ( 0xFFFCC224 ) /* (PWMC_CH1) Channel Duty Cycle Register */
+#define AT91C_PWMC_CH1_CMR         ( 0xFFFCC220 ) /* (PWMC_CH1) Channel Mode Register */
+/* ========== Register definition for PWMC_CH0 peripheral ========== */
+#define AT91C_PWMC_CH0_Reserved    ( 0xFFFCC214 ) /* (PWMC_CH0) Reserved */
+#define AT91C_PWMC_CH0_CPRDR       ( 0xFFFCC208 ) /* (PWMC_CH0) Channel Period Register */
+#define AT91C_PWMC_CH0_CDTYR       ( 0xFFFCC204 ) /* (PWMC_CH0) Channel Duty Cycle Register */
+#define AT91C_PWMC_CH0_CMR         ( 0xFFFCC200 ) /* (PWMC_CH0) Channel Mode Register */
+#define AT91C_PWMC_CH0_CUPDR       ( 0xFFFCC210 ) /* (PWMC_CH0) Channel Update Register */
+#define AT91C_PWMC_CH0_CCNTR       ( 0xFFFCC20C ) /* (PWMC_CH0) Channel Counter Register */
+/* ========== Register definition for PWMC peripheral ========== */
+#define AT91C_PWMC_IDR             ( 0xFFFCC014 ) /* (PWMC) PWMC Interrupt Disable Register */
+#define AT91C_PWMC_DIS             ( 0xFFFCC008 ) /* (PWMC) PWMC Disable Register */
+#define AT91C_PWMC_IER             ( 0xFFFCC010 ) /* (PWMC) PWMC Interrupt Enable Register */
+#define AT91C_PWMC_VR              ( 0xFFFCC0FC ) /* (PWMC) PWMC Version Register */
+#define AT91C_PWMC_ISR             ( 0xFFFCC01C ) /* (PWMC) PWMC Interrupt Status Register */
+#define AT91C_PWMC_SR              ( 0xFFFCC00C ) /* (PWMC) PWMC Status Register */
+#define AT91C_PWMC_IMR             ( 0xFFFCC018 ) /* (PWMC) PWMC Interrupt Mask Register */
+#define AT91C_PWMC_MR              ( 0xFFFCC000 ) /* (PWMC) PWMC Mode Register */
+#define AT91C_PWMC_ENA             ( 0xFFFCC004 ) /* (PWMC) PWMC Enable Register */
+/* ========== Register definition for UDP peripheral ========== */
+#define AT91C_UDP_IMR              ( 0xFFFB0018 ) /* (UDP) Interrupt Mask Register */
+#define AT91C_UDP_FADDR            ( 0xFFFB0008 ) /* (UDP) Function Address Register */
+#define AT91C_UDP_NUM              ( 0xFFFB0000 ) /* (UDP) Frame Number Register */
+#define AT91C_UDP_FDR              ( 0xFFFB0050 ) /* (UDP) Endpoint FIFO Data Register */
+#define AT91C_UDP_ISR              ( 0xFFFB001C ) /* (UDP) Interrupt Status Register */
+#define AT91C_UDP_CSR              ( 0xFFFB0030 ) /* (UDP) Endpoint Control and Status Register */
+#define AT91C_UDP_IDR              ( 0xFFFB0014 ) /* (UDP) Interrupt Disable Register */
+#define AT91C_UDP_ICR              ( 0xFFFB0020 ) /* (UDP) Interrupt Clear Register */
+#define AT91C_UDP_RSTEP            ( 0xFFFB0028 ) /* (UDP) Reset Endpoint Register */
+#define AT91C_UDP_TXVC             ( 0xFFFB0074 ) /* (UDP) Transceiver Control Register */
+#define AT91C_UDP_GLBSTATE         ( 0xFFFB0004 ) /* (UDP) Global State Register */
+#define AT91C_UDP_IER              ( 0xFFFB0010 ) /* (UDP) Interrupt Enable Register */
+/* ========== Register definition for TC0 peripheral ========== */
+#define AT91C_TC0_SR               ( 0xFFFA0020 ) /* (TC0) Status Register */
+#define AT91C_TC0_RC               ( 0xFFFA001C ) /* (TC0) Register C */
+#define AT91C_TC0_RB               ( 0xFFFA0018 ) /* (TC0) Register B */
+#define AT91C_TC0_CCR              ( 0xFFFA0000 ) /* (TC0) Channel Control Register */
+#define AT91C_TC0_CMR              ( 0xFFFA0004 ) /* (TC0) Channel Mode Register (Capture Mode / Waveform Mode) */
+#define AT91C_TC0_IER              ( 0xFFFA0024 ) /* (TC0) Interrupt Enable Register */
+#define AT91C_TC0_RA               ( 0xFFFA0014 ) /* (TC0) Register A */
+#define AT91C_TC0_IDR              ( 0xFFFA0028 ) /* (TC0) Interrupt Disable Register */
+#define AT91C_TC0_CV               ( 0xFFFA0010 ) /* (TC0) Counter Value */
+#define AT91C_TC0_IMR              ( 0xFFFA002C ) /* (TC0) Interrupt Mask Register */
+/* ========== Register definition for TC1 peripheral ========== */
+#define AT91C_TC1_RB               ( 0xFFFA0058 ) /* (TC1) Register B */
+#define AT91C_TC1_CCR              ( 0xFFFA0040 ) /* (TC1) Channel Control Register */
+#define AT91C_TC1_IER              ( 0xFFFA0064 ) /* (TC1) Interrupt Enable Register */
+#define AT91C_TC1_IDR              ( 0xFFFA0068 ) /* (TC1) Interrupt Disable Register */
+#define AT91C_TC1_SR               ( 0xFFFA0060 ) /* (TC1) Status Register */
+#define AT91C_TC1_CMR              ( 0xFFFA0044 ) /* (TC1) Channel Mode Register (Capture Mode / Waveform Mode) */
+#define AT91C_TC1_RA               ( 0xFFFA0054 ) /* (TC1) Register A */
+#define AT91C_TC1_RC               ( 0xFFFA005C ) /* (TC1) Register C */
+#define AT91C_TC1_IMR              ( 0xFFFA006C ) /* (TC1) Interrupt Mask Register */
+#define AT91C_TC1_CV               ( 0xFFFA0050 ) /* (TC1) Counter Value */
+/* ========== Register definition for TC2 peripheral ========== */
+#define AT91C_TC2_CMR              ( 0xFFFA0084 ) /* (TC2) Channel Mode Register (Capture Mode / Waveform Mode) */
+#define AT91C_TC2_CCR              ( 0xFFFA0080 ) /* (TC2) Channel Control Register */
+#define AT91C_TC2_CV               ( 0xFFFA0090 ) /* (TC2) Counter Value */
+#define AT91C_TC2_RA               ( 0xFFFA0094 ) /* (TC2) Register A */
+#define AT91C_TC2_RB               ( 0xFFFA0098 ) /* (TC2) Register B */
+#define AT91C_TC2_IDR              ( 0xFFFA00A8 ) /* (TC2) Interrupt Disable Register */
+#define AT91C_TC2_IMR              ( 0xFFFA00AC ) /* (TC2) Interrupt Mask Register */
+#define AT91C_TC2_RC               ( 0xFFFA009C ) /* (TC2) Register C */
+#define AT91C_TC2_IER              ( 0xFFFA00A4 ) /* (TC2) Interrupt Enable Register */
+#define AT91C_TC2_SR               ( 0xFFFA00A0 ) /* (TC2) Status Register */
+/* ========== Register definition for TCB peripheral ========== */
+#define AT91C_TCB_BMR              ( 0xFFFA00C4 ) /* (TCB) TC Block Mode Register */
+#define AT91C_TCB_BCR              ( 0xFFFA00C0 ) /* (TCB) TC Block Control Register */
+/* ========== Register definition for CAN_MB0 peripheral ========== */
+#define AT91C_CAN_MB0_MDL          ( 0xFFFD0214 ) /* (CAN_MB0) MailBox Data Low Register */
+#define AT91C_CAN_MB0_MAM          ( 0xFFFD0204 ) /* (CAN_MB0) MailBox Acceptance Mask Register */
+#define AT91C_CAN_MB0_MCR          ( 0xFFFD021C ) /* (CAN_MB0) MailBox Control Register */
+#define AT91C_CAN_MB0_MID          ( 0xFFFD0208 ) /* (CAN_MB0) MailBox ID Register */
+#define AT91C_CAN_MB0_MSR          ( 0xFFFD0210 ) /* (CAN_MB0) MailBox Status Register */
+#define AT91C_CAN_MB0_MFID         ( 0xFFFD020C ) /* (CAN_MB0) MailBox Family ID Register */
+#define AT91C_CAN_MB0_MDH          ( 0xFFFD0218 ) /* (CAN_MB0) MailBox Data High Register */
+#define AT91C_CAN_MB0_MMR          ( 0xFFFD0200 ) /* (CAN_MB0) MailBox Mode Register */
+/* ========== Register definition for CAN_MB1 peripheral ========== */
+#define AT91C_CAN_MB1_MDL          ( 0xFFFD0234 ) /* (CAN_MB1) MailBox Data Low Register */
+#define AT91C_CAN_MB1_MID          ( 0xFFFD0228 ) /* (CAN_MB1) MailBox ID Register */
+#define AT91C_CAN_MB1_MMR          ( 0xFFFD0220 ) /* (CAN_MB1) MailBox Mode Register */
+#define AT91C_CAN_MB1_MSR          ( 0xFFFD0230 ) /* (CAN_MB1) MailBox Status Register */
+#define AT91C_CAN_MB1_MAM          ( 0xFFFD0224 ) /* (CAN_MB1) MailBox Acceptance Mask Register */
+#define AT91C_CAN_MB1_MDH          ( 0xFFFD0238 ) /* (CAN_MB1) MailBox Data High Register */
+#define AT91C_CAN_MB1_MCR          ( 0xFFFD023C ) /* (CAN_MB1) MailBox Control Register */
+#define AT91C_CAN_MB1_MFID         ( 0xFFFD022C ) /* (CAN_MB1) MailBox Family ID Register */
+/* ========== Register definition for CAN_MB2 peripheral ========== */
+#define AT91C_CAN_MB2_MCR          ( 0xFFFD025C ) /* (CAN_MB2) MailBox Control Register */
+#define AT91C_CAN_MB2_MDH          ( 0xFFFD0258 ) /* (CAN_MB2) MailBox Data High Register */
+#define AT91C_CAN_MB2_MID          ( 0xFFFD0248 ) /* (CAN_MB2) MailBox ID Register */
+#define AT91C_CAN_MB2_MDL          ( 0xFFFD0254 ) /* (CAN_MB2) MailBox Data Low Register */
+#define AT91C_CAN_MB2_MMR          ( 0xFFFD0240 ) /* (CAN_MB2) MailBox Mode Register */
+#define AT91C_CAN_MB2_MAM          ( 0xFFFD0244 ) /* (CAN_MB2) MailBox Acceptance Mask Register */
+#define AT91C_CAN_MB2_MFID         ( 0xFFFD024C ) /* (CAN_MB2) MailBox Family ID Register */
+#define AT91C_CAN_MB2_MSR          ( 0xFFFD0250 ) /* (CAN_MB2) MailBox Status Register */
+/* ========== Register definition for CAN_MB3 peripheral ========== */
+#define AT91C_CAN_MB3_MFID         ( 0xFFFD026C ) /* (CAN_MB3) MailBox Family ID Register */
+#define AT91C_CAN_MB3_MAM          ( 0xFFFD0264 ) /* (CAN_MB3) MailBox Acceptance Mask Register */
+#define AT91C_CAN_MB3_MID          ( 0xFFFD0268 ) /* (CAN_MB3) MailBox ID Register */
+#define AT91C_CAN_MB3_MCR          ( 0xFFFD027C ) /* (CAN_MB3) MailBox Control Register */
+#define AT91C_CAN_MB3_MMR          ( 0xFFFD0260 ) /* (CAN_MB3) MailBox Mode Register */
+#define AT91C_CAN_MB3_MSR          ( 0xFFFD0270 ) /* (CAN_MB3) MailBox Status Register */
+#define AT91C_CAN_MB3_MDL          ( 0xFFFD0274 ) /* (CAN_MB3) MailBox Data Low Register */
+#define AT91C_CAN_MB3_MDH          ( 0xFFFD0278 ) /* (CAN_MB3) MailBox Data High Register */
+/* ========== Register definition for CAN_MB4 peripheral ========== */
+#define AT91C_CAN_MB4_MID          ( 0xFFFD0288 ) /* (CAN_MB4) MailBox ID Register */
+#define AT91C_CAN_MB4_MMR          ( 0xFFFD0280 ) /* (CAN_MB4) MailBox Mode Register */
+#define AT91C_CAN_MB4_MDH          ( 0xFFFD0298 ) /* (CAN_MB4) MailBox Data High Register */
+#define AT91C_CAN_MB4_MFID         ( 0xFFFD028C ) /* (CAN_MB4) MailBox Family ID Register */
+#define AT91C_CAN_MB4_MSR          ( 0xFFFD0290 ) /* (CAN_MB4) MailBox Status Register */
+#define AT91C_CAN_MB4_MCR          ( 0xFFFD029C ) /* (CAN_MB4) MailBox Control Register */
+#define AT91C_CAN_MB4_MDL          ( 0xFFFD0294 ) /* (CAN_MB4) MailBox Data Low Register */
+#define AT91C_CAN_MB4_MAM          ( 0xFFFD0284 ) /* (CAN_MB4) MailBox Acceptance Mask Register */
+/* ========== Register definition for CAN_MB5 peripheral ========== */
+#define AT91C_CAN_MB5_MSR          ( 0xFFFD02B0 ) /* (CAN_MB5) MailBox Status Register */
+#define AT91C_CAN_MB5_MCR          ( 0xFFFD02BC ) /* (CAN_MB5) MailBox Control Register */
+#define AT91C_CAN_MB5_MFID         ( 0xFFFD02AC ) /* (CAN_MB5) MailBox Family ID Register */
+#define AT91C_CAN_MB5_MDH          ( 0xFFFD02B8 ) /* (CAN_MB5) MailBox Data High Register */
+#define AT91C_CAN_MB5_MID          ( 0xFFFD02A8 ) /* (CAN_MB5) MailBox ID Register */
+#define AT91C_CAN_MB5_MMR          ( 0xFFFD02A0 ) /* (CAN_MB5) MailBox Mode Register */
+#define AT91C_CAN_MB5_MDL          ( 0xFFFD02B4 ) /* (CAN_MB5) MailBox Data Low Register */
+#define AT91C_CAN_MB5_MAM          ( 0xFFFD02A4 ) /* (CAN_MB5) MailBox Acceptance Mask Register */
+/* ========== Register definition for CAN_MB6 peripheral ========== */
+#define AT91C_CAN_MB6_MFID         ( 0xFFFD02CC ) /* (CAN_MB6) MailBox Family ID Register */
+#define AT91C_CAN_MB6_MID          ( 0xFFFD02C8 ) /* (CAN_MB6) MailBox ID Register */
+#define AT91C_CAN_MB6_MAM          ( 0xFFFD02C4 ) /* (CAN_MB6) MailBox Acceptance Mask Register */
+#define AT91C_CAN_MB6_MSR          ( 0xFFFD02D0 ) /* (CAN_MB6) MailBox Status Register */
+#define AT91C_CAN_MB6_MDL          ( 0xFFFD02D4 ) /* (CAN_MB6) MailBox Data Low Register */
+#define AT91C_CAN_MB6_MCR          ( 0xFFFD02DC ) /* (CAN_MB6) MailBox Control Register */
+#define AT91C_CAN_MB6_MDH          ( 0xFFFD02D8 ) /* (CAN_MB6) MailBox Data High Register */
+#define AT91C_CAN_MB6_MMR          ( 0xFFFD02C0 ) /* (CAN_MB6) MailBox Mode Register */
+/* ========== Register definition for CAN_MB7 peripheral ========== */
+#define AT91C_CAN_MB7_MCR          ( 0xFFFD02FC ) /* (CAN_MB7) MailBox Control Register */
+#define AT91C_CAN_MB7_MDH          ( 0xFFFD02F8 ) /* (CAN_MB7) MailBox Data High Register */
+#define AT91C_CAN_MB7_MFID         ( 0xFFFD02EC ) /* (CAN_MB7) MailBox Family ID Register */
+#define AT91C_CAN_MB7_MDL          ( 0xFFFD02F4 ) /* (CAN_MB7) MailBox Data Low Register */
+#define AT91C_CAN_MB7_MID          ( 0xFFFD02E8 ) /* (CAN_MB7) MailBox ID Register */
+#define AT91C_CAN_MB7_MMR          ( 0xFFFD02E0 ) /* (CAN_MB7) MailBox Mode Register */
+#define AT91C_CAN_MB7_MAM          ( 0xFFFD02E4 ) /* (CAN_MB7) MailBox Acceptance Mask Register */
+#define AT91C_CAN_MB7_MSR          ( 0xFFFD02F0 ) /* (CAN_MB7) MailBox Status Register */
+/* ========== Register definition for CAN peripheral ========== */
+#define AT91C_CAN_TCR              ( 0xFFFD0024 ) /* (CAN) Transfer Command Register */
+#define AT91C_CAN_IMR              ( 0xFFFD000C ) /* (CAN) Interrupt Mask Register */
+#define AT91C_CAN_IER              ( 0xFFFD0004 ) /* (CAN) Interrupt Enable Register */
+#define AT91C_CAN_ECR              ( 0xFFFD0020 ) /* (CAN) Error Counter Register */
+#define AT91C_CAN_TIMESTP          ( 0xFFFD001C ) /* (CAN) Time Stamp Register */
+#define AT91C_CAN_MR               ( 0xFFFD0000 ) /* (CAN) Mode Register */
+#define AT91C_CAN_IDR              ( 0xFFFD0008 ) /* (CAN) Interrupt Disable Register */
+#define AT91C_CAN_ACR              ( 0xFFFD0028 ) /* (CAN) Abort Command Register */
+#define AT91C_CAN_TIM              ( 0xFFFD0018 ) /* (CAN) Timer Register */
+#define AT91C_CAN_SR               ( 0xFFFD0010 ) /* (CAN) Status Register */
+#define AT91C_CAN_BR               ( 0xFFFD0014 ) /* (CAN) Baudrate Register */
+#define AT91C_CAN_VR               ( 0xFFFD00FC ) /* (CAN) Version Register */
+/* ========== Register definition for EMAC peripheral ========== */
+#define AT91C_EMAC_ISR             ( 0xFFFDC024 ) /* (EMAC) Interrupt Status Register */
+#define AT91C_EMAC_SA4H            ( 0xFFFDC0B4 ) /* (EMAC) Specific Address 4 Top, Last 2 bytes */
+#define AT91C_EMAC_SA1L            ( 0xFFFDC098 ) /* (EMAC) Specific Address 1 Bottom, First 4 bytes */
+#define AT91C_EMAC_ELE             ( 0xFFFDC078 ) /* (EMAC) Excessive Length Errors Register */
+#define AT91C_EMAC_LCOL            ( 0xFFFDC05C ) /* (EMAC) Late Collision Register */
+#define AT91C_EMAC_RLE             ( 0xFFFDC088 ) /* (EMAC) Receive Length Field Mismatch Register */
+#define AT91C_EMAC_WOL             ( 0xFFFDC0C4 ) /* (EMAC) Wake On LAN Register */
+#define AT91C_EMAC_DTF             ( 0xFFFDC058 ) /* (EMAC) Deferred Transmission Frame Register */
+#define AT91C_EMAC_TUND            ( 0xFFFDC064 ) /* (EMAC) Transmit Underrun Error Register */
+#define AT91C_EMAC_NCR             ( 0xFFFDC000 ) /* (EMAC) Network Control Register */
+#define AT91C_EMAC_SA4L            ( 0xFFFDC0B0 ) /* (EMAC) Specific Address 4 Bottom, First 4 bytes */
+#define AT91C_EMAC_RSR             ( 0xFFFDC020 ) /* (EMAC) Receive Status Register */
+#define AT91C_EMAC_SA3L            ( 0xFFFDC0A8 ) /* (EMAC) Specific Address 3 Bottom, First 4 bytes */
+#define AT91C_EMAC_TSR             ( 0xFFFDC014 ) /* (EMAC) Transmit Status Register */
+#define AT91C_EMAC_IDR             ( 0xFFFDC02C ) /* (EMAC) Interrupt Disable Register */
+#define AT91C_EMAC_RSE             ( 0xFFFDC074 ) /* (EMAC) Receive Symbol Errors Register */
+#define AT91C_EMAC_ECOL            ( 0xFFFDC060 ) /* (EMAC) Excessive Collision Register */
+#define AT91C_EMAC_TID             ( 0xFFFDC0B8 ) /* (EMAC) Type ID Checking Register */
+#define AT91C_EMAC_HRB             ( 0xFFFDC090 ) /* (EMAC) Hash Address Bottom[31:0] */
+#define AT91C_EMAC_TBQP            ( 0xFFFDC01C ) /* (EMAC) Transmit Buffer Queue Pointer */
+#define AT91C_EMAC_USRIO           ( 0xFFFDC0C0 ) /* (EMAC) USER Input/Output Register */
+#define AT91C_EMAC_PTR             ( 0xFFFDC038 ) /* (EMAC) Pause Time Register */
+#define AT91C_EMAC_SA2H            ( 0xFFFDC0A4 ) /* (EMAC) Specific Address 2 Top, Last 2 bytes */
+#define AT91C_EMAC_ROV             ( 0xFFFDC070 ) /* (EMAC) Receive Overrun Errors Register */
+#define AT91C_EMAC_ALE             ( 0xFFFDC054 ) /* (EMAC) Alignment Error Register */
+#define AT91C_EMAC_RJA             ( 0xFFFDC07C ) /* (EMAC) Receive Jabbers Register */
+#define AT91C_EMAC_RBQP            ( 0xFFFDC018 ) /* (EMAC) Receive Buffer Queue Pointer */
+#define AT91C_EMAC_TPF             ( 0xFFFDC08C ) /* (EMAC) Transmitted Pause Frames Register */
+#define AT91C_EMAC_NCFGR           ( 0xFFFDC004 ) /* (EMAC) Network Configuration Register */
+#define AT91C_EMAC_HRT             ( 0xFFFDC094 ) /* (EMAC) Hash Address Top[63:32] */
+#define AT91C_EMAC_USF             ( 0xFFFDC080 ) /* (EMAC) Undersize Frames Register */
+#define AT91C_EMAC_FCSE            ( 0xFFFDC050 ) /* (EMAC) Frame Check Sequence Error Register */
+#define AT91C_EMAC_TPQ             ( 0xFFFDC0BC ) /* (EMAC) Transmit Pause Quantum Register */
+#define AT91C_EMAC_MAN             ( 0xFFFDC034 ) /* (EMAC) PHY Maintenance Register */
+#define AT91C_EMAC_FTO             ( 0xFFFDC040 ) /* (EMAC) Frames Transmitted OK Register */
+#define AT91C_EMAC_REV             ( 0xFFFDC0FC ) /* (EMAC) Revision Register */
+#define AT91C_EMAC_IMR             ( 0xFFFDC030 ) /* (EMAC) Interrupt Mask Register */
+#define AT91C_EMAC_SCF             ( 0xFFFDC044 ) /* (EMAC) Single Collision Frame Register */
+#define AT91C_EMAC_PFR             ( 0xFFFDC03C ) /* (EMAC) Pause Frames received Register */
+#define AT91C_EMAC_MCF             ( 0xFFFDC048 ) /* (EMAC) Multiple Collision Frame Register */
+#define AT91C_EMAC_NSR             ( 0xFFFDC008 ) /* (EMAC) Network Status Register */
+#define AT91C_EMAC_SA2L            ( 0xFFFDC0A0 ) /* (EMAC) Specific Address 2 Bottom, First 4 bytes */
+#define AT91C_EMAC_FRO             ( 0xFFFDC04C ) /* (EMAC) Frames Received OK Register */
+#define AT91C_EMAC_IER             ( 0xFFFDC028 ) /* (EMAC) Interrupt Enable Register */
+#define AT91C_EMAC_SA1H            ( 0xFFFDC09C ) /* (EMAC) Specific Address 1 Top, Last 2 bytes */
+#define AT91C_EMAC_CSE             ( 0xFFFDC068 ) /* (EMAC) Carrier Sense Error Register */
+#define AT91C_EMAC_SA3H            ( 0xFFFDC0AC ) /* (EMAC) Specific Address 3 Top, Last 2 bytes */
+#define AT91C_EMAC_RRE             ( 0xFFFDC06C ) /* (EMAC) Receive Ressource Error Register */
+#define AT91C_EMAC_STE             ( 0xFFFDC084 ) /* (EMAC) SQE Test Error Register */
+/* ========== Register definition for PDC_ADC peripheral ========== */
+#define AT91C_ADC_PTSR             ( 0xFFFD8124 ) /* (PDC_ADC) PDC Transfer Status Register */
+#define AT91C_ADC_PTCR             ( 0xFFFD8120 ) /* (PDC_ADC) PDC Transfer Control Register */
+#define AT91C_ADC_TNPR             ( 0xFFFD8118 ) /* (PDC_ADC) Transmit Next Pointer Register */
+#define AT91C_ADC_TNCR             ( 0xFFFD811C ) /* (PDC_ADC) Transmit Next Counter Register */
+#define AT91C_ADC_RNPR             ( 0xFFFD8110 ) /* (PDC_ADC) Receive Next Pointer Register */
+#define AT91C_ADC_RNCR             ( 0xFFFD8114 ) /* (PDC_ADC) Receive Next Counter Register */
+#define AT91C_ADC_RPR              ( 0xFFFD8100 ) /* (PDC_ADC) Receive Pointer Register */
+#define AT91C_ADC_TCR              ( 0xFFFD810C ) /* (PDC_ADC) Transmit Counter Register */
+#define AT91C_ADC_TPR              ( 0xFFFD8108 ) /* (PDC_ADC) Transmit Pointer Register */
+#define AT91C_ADC_RCR              ( 0xFFFD8104 ) /* (PDC_ADC) Receive Counter Register */
+/* ========== Register definition for ADC peripheral ========== */
+#define AT91C_ADC_CDR2             ( 0xFFFD8038 ) /* (ADC) ADC Channel Data Register 2 */
+#define AT91C_ADC_CDR3             ( 0xFFFD803C ) /* (ADC) ADC Channel Data Register 3 */
+#define AT91C_ADC_CDR0             ( 0xFFFD8030 ) /* (ADC) ADC Channel Data Register 0 */
+#define AT91C_ADC_CDR5             ( 0xFFFD8044 ) /* (ADC) ADC Channel Data Register 5 */
+#define AT91C_ADC_CHDR             ( 0xFFFD8014 ) /* (ADC) ADC Channel Disable Register */
+#define AT91C_ADC_SR               ( 0xFFFD801C ) /* (ADC) ADC Status Register */
+#define AT91C_ADC_CDR4             ( 0xFFFD8040 ) /* (ADC) ADC Channel Data Register 4 */
+#define AT91C_ADC_CDR1             ( 0xFFFD8034 ) /* (ADC) ADC Channel Data Register 1 */
+#define AT91C_ADC_LCDR             ( 0xFFFD8020 ) /* (ADC) ADC Last Converted Data Register */
+#define AT91C_ADC_IDR              ( 0xFFFD8028 ) /* (ADC) ADC Interrupt Disable Register */
+#define AT91C_ADC_CR               ( 0xFFFD8000 ) /* (ADC) ADC Control Register */
+#define AT91C_ADC_CDR7             ( 0xFFFD804C ) /* (ADC) ADC Channel Data Register 7 */
+#define AT91C_ADC_CDR6             ( 0xFFFD8048 ) /* (ADC) ADC Channel Data Register 6 */
+#define AT91C_ADC_IER              ( 0xFFFD8024 ) /* (ADC) ADC Interrupt Enable Register */
+#define AT91C_ADC_CHER             ( 0xFFFD8010 ) /* (ADC) ADC Channel Enable Register */
+#define AT91C_ADC_CHSR             ( 0xFFFD8018 ) /* (ADC) ADC Channel Status Register */
+#define AT91C_ADC_MR               ( 0xFFFD8004 ) /* (ADC) ADC Mode Register */
+#define AT91C_ADC_IMR              ( 0xFFFD802C ) /* (ADC) ADC Interrupt Mask Register */
+/* ========== Register definition for PDC_AES peripheral ========== */
+#define AT91C_AES_TPR              ( 0xFFFA4108 ) /* (PDC_AES) Transmit Pointer Register */
+#define AT91C_AES_PTCR             ( 0xFFFA4120 ) /* (PDC_AES) PDC Transfer Control Register */
+#define AT91C_AES_RNPR             ( 0xFFFA4110 ) /* (PDC_AES) Receive Next Pointer Register */
+#define AT91C_AES_TNCR             ( 0xFFFA411C ) /* (PDC_AES) Transmit Next Counter Register */
+#define AT91C_AES_TCR              ( 0xFFFA410C ) /* (PDC_AES) Transmit Counter Register */
+#define AT91C_AES_RCR              ( 0xFFFA4104 ) /* (PDC_AES) Receive Counter Register */
+#define AT91C_AES_RNCR             ( 0xFFFA4114 ) /* (PDC_AES) Receive Next Counter Register */
+#define AT91C_AES_TNPR             ( 0xFFFA4118 ) /* (PDC_AES) Transmit Next Pointer Register */
+#define AT91C_AES_RPR              ( 0xFFFA4100 ) /* (PDC_AES) Receive Pointer Register */
+#define AT91C_AES_PTSR             ( 0xFFFA4124 ) /* (PDC_AES) PDC Transfer Status Register */
+/* ========== Register definition for AES peripheral ========== */
+#define AT91C_AES_IVxR             ( 0xFFFA4060 ) /* (AES) Initialization Vector x Register */
+#define AT91C_AES_MR               ( 0xFFFA4004 ) /* (AES) Mode Register */
+#define AT91C_AES_VR               ( 0xFFFA40FC ) /* (AES) AES Version Register */
+#define AT91C_AES_ODATAxR          ( 0xFFFA4050 ) /* (AES) Output Data x Register */
+#define AT91C_AES_IDATAxR          ( 0xFFFA4040 ) /* (AES) Input Data x Register */
+#define AT91C_AES_CR               ( 0xFFFA4000 ) /* (AES) Control Register */
+#define AT91C_AES_IDR              ( 0xFFFA4014 ) /* (AES) Interrupt Disable Register */
+#define AT91C_AES_IMR              ( 0xFFFA4018 ) /* (AES) Interrupt Mask Register */
+#define AT91C_AES_IER              ( 0xFFFA4010 ) /* (AES) Interrupt Enable Register */
+#define AT91C_AES_KEYWxR           ( 0xFFFA4020 ) /* (AES) Key Word x Register */
+#define AT91C_AES_ISR              ( 0xFFFA401C ) /* (AES) Interrupt Status Register */
+/* ========== Register definition for PDC_TDES peripheral ========== */
+#define AT91C_TDES_RNCR            ( 0xFFFA8114 ) /* (PDC_TDES) Receive Next Counter Register */
+#define AT91C_TDES_TCR             ( 0xFFFA810C ) /* (PDC_TDES) Transmit Counter Register */
+#define AT91C_TDES_RCR             ( 0xFFFA8104 ) /* (PDC_TDES) Receive Counter Register */
+#define AT91C_TDES_TNPR            ( 0xFFFA8118 ) /* (PDC_TDES) Transmit Next Pointer Register */
+#define AT91C_TDES_RNPR            ( 0xFFFA8110 ) /* (PDC_TDES) Receive Next Pointer Register */
+#define AT91C_TDES_RPR             ( 0xFFFA8100 ) /* (PDC_TDES) Receive Pointer Register */
+#define AT91C_TDES_TNCR            ( 0xFFFA811C ) /* (PDC_TDES) Transmit Next Counter Register */
+#define AT91C_TDES_TPR             ( 0xFFFA8108 ) /* (PDC_TDES) Transmit Pointer Register */
+#define AT91C_TDES_PTSR            ( 0xFFFA8124 ) /* (PDC_TDES) PDC Transfer Status Register */
+#define AT91C_TDES_PTCR            ( 0xFFFA8120 ) /* (PDC_TDES) PDC Transfer Control Register */
+/* ========== Register definition for TDES peripheral ========== */
+#define AT91C_TDES_KEY2WxR         ( 0xFFFA8028 ) /* (TDES) Key 2 Word x Register */
+#define AT91C_TDES_KEY3WxR         ( 0xFFFA8030 ) /* (TDES) Key 3 Word x Register */
+#define AT91C_TDES_IDR             ( 0xFFFA8014 ) /* (TDES) Interrupt Disable Register */
+#define AT91C_TDES_VR              ( 0xFFFA80FC ) /* (TDES) TDES Version Register */
+#define AT91C_TDES_IVxR            ( 0xFFFA8060 ) /* (TDES) Initialization Vector x Register */
+#define AT91C_TDES_ODATAxR         ( 0xFFFA8050 ) /* (TDES) Output Data x Register */
+#define AT91C_TDES_IMR             ( 0xFFFA8018 ) /* (TDES) Interrupt Mask Register */
+#define AT91C_TDES_MR              ( 0xFFFA8004 ) /* (TDES) Mode Register */
+#define AT91C_TDES_CR              ( 0xFFFA8000 ) /* (TDES) Control Register */
+#define AT91C_TDES_IER             ( 0xFFFA8010 ) /* (TDES) Interrupt Enable Register */
+#define AT91C_TDES_ISR             ( 0xFFFA801C ) /* (TDES) Interrupt Status Register */
+#define AT91C_TDES_IDATAxR         ( 0xFFFA8040 ) /* (TDES) Input Data x Register */
+#define AT91C_TDES_KEY1WxR         ( 0xFFFA8020 ) /* (TDES) Key 1 Word x Register */
 
-// *****************************************************************************
-//               PIO DEFINITIONS FOR AT91SAM7X256
-// *****************************************************************************
-#define AT91C_PIO_PA0             (1 <<  0) // Pin Controlled by PA0
-#define AT91C_PA0_RXD0            (AT91C_PIO_PA0) //  USART 0 Receive Data
-#define AT91C_PIO_PA1             (1 <<  1) // Pin Controlled by PA1
-#define AT91C_PA1_TXD0            (AT91C_PIO_PA1) //  USART 0 Transmit Data
-#define AT91C_PIO_PA10            (1 << 10) // Pin Controlled by PA10
-#define AT91C_PA10_TWD            (AT91C_PIO_PA10) //  TWI Two-wire Serial Data
-#define AT91C_PIO_PA11            (1 << 11) // Pin Controlled by PA11
-#define AT91C_PA11_TWCK           (AT91C_PIO_PA11) //  TWI Two-wire Serial Clock
-#define AT91C_PIO_PA12            (1 << 12) // Pin Controlled by PA12
-#define AT91C_PA12_NPCS00         (AT91C_PIO_PA12) //  SPI 0 Peripheral Chip Select 0
-#define AT91C_PIO_PA13            (1 << 13) // Pin Controlled by PA13
-#define AT91C_PA13_NPCS01         (AT91C_PIO_PA13) //  SPI 0 Peripheral Chip Select 1
-#define AT91C_PA13_PCK1           (AT91C_PIO_PA13) //  PMC Programmable Clock Output 1
-#define AT91C_PIO_PA14            (1 << 14) // Pin Controlled by PA14
-#define AT91C_PA14_NPCS02         (AT91C_PIO_PA14) //  SPI 0 Peripheral Chip Select 2
-#define AT91C_PA14_IRQ1           (AT91C_PIO_PA14) //  External Interrupt 1
-#define AT91C_PIO_PA15            (1 << 15) // Pin Controlled by PA15
-#define AT91C_PA15_NPCS03         (AT91C_PIO_PA15) //  SPI 0 Peripheral Chip Select 3
-#define AT91C_PA15_TCLK2          (AT91C_PIO_PA15) //  Timer Counter 2 external clock input
-#define AT91C_PIO_PA16            (1 << 16) // Pin Controlled by PA16
-#define AT91C_PA16_MISO0          (AT91C_PIO_PA16) //  SPI 0 Master In Slave
-#define AT91C_PIO_PA17            (1 << 17) // Pin Controlled by PA17
-#define AT91C_PA17_MOSI0          (AT91C_PIO_PA17) //  SPI 0 Master Out Slave
-#define AT91C_PIO_PA18            (1 << 18) // Pin Controlled by PA18
-#define AT91C_PA18_SPCK0          (AT91C_PIO_PA18) //  SPI 0 Serial Clock
-#define AT91C_PIO_PA19            (1 << 19) // Pin Controlled by PA19
-#define AT91C_PA19_CANRX          (AT91C_PIO_PA19) //  CAN Receive
-#define AT91C_PIO_PA2             (1 <<  2) // Pin Controlled by PA2
-#define AT91C_PA2_SCK0            (AT91C_PIO_PA2) //  USART 0 Serial Clock
-#define AT91C_PA2_NPCS11          (AT91C_PIO_PA2) //  SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PA20            (1 << 20) // Pin Controlled by PA20
-#define AT91C_PA20_CANTX          (AT91C_PIO_PA20) //  CAN Transmit
-#define AT91C_PIO_PA21            (1 << 21) // Pin Controlled by PA21
-#define AT91C_PA21_TF             (AT91C_PIO_PA21) //  SSC Transmit Frame Sync
-#define AT91C_PA21_NPCS10         (AT91C_PIO_PA21) //  SPI 1 Peripheral Chip Select 0
-#define AT91C_PIO_PA22            (1 << 22) // Pin Controlled by PA22
-#define AT91C_PA22_TK             (AT91C_PIO_PA22) //  SSC Transmit Clock
-#define AT91C_PA22_SPCK1          (AT91C_PIO_PA22) //  SPI 1 Serial Clock
-#define AT91C_PIO_PA23            (1 << 23) // Pin Controlled by PA23
-#define AT91C_PA23_TD             (AT91C_PIO_PA23) //  SSC Transmit data
-#define AT91C_PA23_MOSI1          (AT91C_PIO_PA23) //  SPI 1 Master Out Slave
-#define AT91C_PIO_PA24            (1 << 24) // Pin Controlled by PA24
-#define AT91C_PA24_RD             (AT91C_PIO_PA24) //  SSC Receive Data
-#define AT91C_PA24_MISO1          (AT91C_PIO_PA24) //  SPI 1 Master In Slave
-#define AT91C_PIO_PA25            (1 << 25) // Pin Controlled by PA25
-#define AT91C_PA25_RK             (AT91C_PIO_PA25) //  SSC Receive Clock
-#define AT91C_PA25_NPCS11         (AT91C_PIO_PA25) //  SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PA26            (1 << 26) // Pin Controlled by PA26
-#define AT91C_PA26_RF             (AT91C_PIO_PA26) //  SSC Receive Frame Sync
-#define AT91C_PA26_NPCS12         (AT91C_PIO_PA26) //  SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PA27            (1 << 27) // Pin Controlled by PA27
-#define AT91C_PA27_DRXD           (AT91C_PIO_PA27) //  DBGU Debug Receive Data
-#define AT91C_PA27_PCK3           (AT91C_PIO_PA27) //  PMC Programmable Clock Output 3
-#define AT91C_PIO_PA28            (1 << 28) // Pin Controlled by PA28
-#define AT91C_PA28_DTXD           (AT91C_PIO_PA28) //  DBGU Debug Transmit Data
-#define AT91C_PIO_PA29            (1 << 29) // Pin Controlled by PA29
-#define AT91C_PA29_FIQ            (AT91C_PIO_PA29) //  AIC Fast Interrupt Input
-#define AT91C_PA29_NPCS13         (AT91C_PIO_PA29) //  SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PA3             (1 <<  3) // Pin Controlled by PA3
-#define AT91C_PA3_RTS0            (AT91C_PIO_PA3) //  USART 0 Ready To Send
-#define AT91C_PA3_NPCS12          (AT91C_PIO_PA3) //  SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PA30            (1 << 30) // Pin Controlled by PA30
-#define AT91C_PA30_IRQ0           (AT91C_PIO_PA30) //  External Interrupt 0
-#define AT91C_PA30_PCK2           (AT91C_PIO_PA30) //  PMC Programmable Clock Output 2
-#define AT91C_PIO_PA4             (1 <<  4) // Pin Controlled by PA4
-#define AT91C_PA4_CTS0            (AT91C_PIO_PA4) //  USART 0 Clear To Send
-#define AT91C_PA4_NPCS13          (AT91C_PIO_PA4) //  SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PA5             (1 <<  5) // Pin Controlled by PA5
-#define AT91C_PA5_RXD1            (AT91C_PIO_PA5) //  USART 1 Receive Data
-#define AT91C_PIO_PA6             (1 <<  6) // Pin Controlled by PA6
-#define AT91C_PA6_TXD1            (AT91C_PIO_PA6) //  USART 1 Transmit Data
-#define AT91C_PIO_PA7             (1 <<  7) // Pin Controlled by PA7
-#define AT91C_PA7_SCK1            (AT91C_PIO_PA7) //  USART 1 Serial Clock
-#define AT91C_PA7_NPCS01          (AT91C_PIO_PA7) //  SPI 0 Peripheral Chip Select 1
-#define AT91C_PIO_PA8             (1 <<  8) // Pin Controlled by PA8
-#define AT91C_PA8_RTS1            (AT91C_PIO_PA8) //  USART 1 Ready To Send
-#define AT91C_PA8_NPCS02          (AT91C_PIO_PA8) //  SPI 0 Peripheral Chip Select 2
-#define AT91C_PIO_PA9             (1 <<  9) // Pin Controlled by PA9
-#define AT91C_PA9_CTS1            (AT91C_PIO_PA9) //  USART 1 Clear To Send
-#define AT91C_PA9_NPCS03          (AT91C_PIO_PA9) //  SPI 0 Peripheral Chip Select 3
-#define AT91C_PIO_PB0             (1 <<  0) // Pin Controlled by PB0
-#define AT91C_PB0_ETXCK_EREFCK    (AT91C_PIO_PB0) //  Ethernet MAC Transmit Clock/Reference Clock
-#define AT91C_PB0_PCK0            (AT91C_PIO_PB0) //  PMC Programmable Clock Output 0
-#define AT91C_PIO_PB1             (1 <<  1) // Pin Controlled by PB1
-#define AT91C_PB1_ETXEN           (AT91C_PIO_PB1) //  Ethernet MAC Transmit Enable
-#define AT91C_PIO_PB10            (1 << 10) // Pin Controlled by PB10
-#define AT91C_PB10_ETX2           (AT91C_PIO_PB10) //  Ethernet MAC Transmit Data 2
-#define AT91C_PB10_NPCS11         (AT91C_PIO_PB10) //  SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PB11            (1 << 11) // Pin Controlled by PB11
-#define AT91C_PB11_ETX3           (AT91C_PIO_PB11) //  Ethernet MAC Transmit Data 3
-#define AT91C_PB11_NPCS12         (AT91C_PIO_PB11) //  SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PB12            (1 << 12) // Pin Controlled by PB12
-#define AT91C_PB12_ETXER          (AT91C_PIO_PB12) //  Ethernet MAC Transmikt Coding Error
-#define AT91C_PB12_TCLK0          (AT91C_PIO_PB12) //  Timer Counter 0 external clock input
-#define AT91C_PIO_PB13            (1 << 13) // Pin Controlled by PB13
-#define AT91C_PB13_ERX2           (AT91C_PIO_PB13) //  Ethernet MAC Receive Data 2
-#define AT91C_PB13_NPCS01         (AT91C_PIO_PB13) //  SPI 0 Peripheral Chip Select 1
-#define AT91C_PIO_PB14            (1 << 14) // Pin Controlled by PB14
-#define AT91C_PB14_ERX3           (AT91C_PIO_PB14) //  Ethernet MAC Receive Data 3
-#define AT91C_PB14_NPCS02         (AT91C_PIO_PB14) //  SPI 0 Peripheral Chip Select 2
-#define AT91C_PIO_PB15            (1 << 15) // Pin Controlled by PB15
-#define AT91C_PB15_ERXDV          (AT91C_PIO_PB15) //  Ethernet MAC Receive Data Valid
-#define AT91C_PIO_PB16            (1 << 16) // Pin Controlled by PB16
-#define AT91C_PB16_ECOL           (AT91C_PIO_PB16) //  Ethernet MAC Collision Detected
-#define AT91C_PB16_NPCS13         (AT91C_PIO_PB16) //  SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PB17            (1 << 17) // Pin Controlled by PB17
-#define AT91C_PB17_ERXCK          (AT91C_PIO_PB17) //  Ethernet MAC Receive Clock
-#define AT91C_PB17_NPCS03         (AT91C_PIO_PB17) //  SPI 0 Peripheral Chip Select 3
-#define AT91C_PIO_PB18            (1 << 18) // Pin Controlled by PB18
-#define AT91C_PB18_EF100          (AT91C_PIO_PB18) //  Ethernet MAC Force 100 Mbits/sec
-#define AT91C_PB18_ADTRG          (AT91C_PIO_PB18) //  ADC External Trigger
-#define AT91C_PIO_PB19            (1 << 19) // Pin Controlled by PB19
-#define AT91C_PB19_PWM0           (AT91C_PIO_PB19) //  PWM Channel 0
-#define AT91C_PB19_TCLK1          (AT91C_PIO_PB19) //  Timer Counter 1 external clock input
-#define AT91C_PIO_PB2             (1 <<  2) // Pin Controlled by PB2
-#define AT91C_PB2_ETX0            (AT91C_PIO_PB2) //  Ethernet MAC Transmit Data 0
-#define AT91C_PIO_PB20            (1 << 20) // Pin Controlled by PB20
-#define AT91C_PB20_PWM1           (AT91C_PIO_PB20) //  PWM Channel 1
-#define AT91C_PB20_PCK0           (AT91C_PIO_PB20) //  PMC Programmable Clock Output 0
-#define AT91C_PIO_PB21            (1 << 21) // Pin Controlled by PB21
-#define AT91C_PB21_PWM2           (AT91C_PIO_PB21) //  PWM Channel 2
-#define AT91C_PB21_PCK1           (AT91C_PIO_PB21) //  PMC Programmable Clock Output 1
-#define AT91C_PIO_PB22            (1 << 22) // Pin Controlled by PB22
-#define AT91C_PB22_PWM3           (AT91C_PIO_PB22) //  PWM Channel 3
-#define AT91C_PB22_PCK2           (AT91C_PIO_PB22) //  PMC Programmable Clock Output 2
-#define AT91C_PIO_PB23            (1 << 23) // Pin Controlled by PB23
-#define AT91C_PB23_TIOA0          (AT91C_PIO_PB23) //  Timer Counter 0 Multipurpose Timer I/O Pin A
-#define AT91C_PB23_DCD1           (AT91C_PIO_PB23) //  USART 1 Data Carrier Detect
-#define AT91C_PIO_PB24            (1 << 24) // Pin Controlled by PB24
-#define AT91C_PB24_TIOB0          (AT91C_PIO_PB24) //  Timer Counter 0 Multipurpose Timer I/O Pin B
-#define AT91C_PB24_DSR1           (AT91C_PIO_PB24) //  USART 1 Data Set ready
-#define AT91C_PIO_PB25            (1 << 25) // Pin Controlled by PB25
-#define AT91C_PB25_TIOA1          (AT91C_PIO_PB25) //  Timer Counter 1 Multipurpose Timer I/O Pin A
-#define AT91C_PB25_DTR1           (AT91C_PIO_PB25) //  USART 1 Data Terminal ready
-#define AT91C_PIO_PB26            (1 << 26) // Pin Controlled by PB26
-#define AT91C_PB26_TIOB1          (AT91C_PIO_PB26) //  Timer Counter 1 Multipurpose Timer I/O Pin B
-#define AT91C_PB26_RI1            (AT91C_PIO_PB26) //  USART 1 Ring Indicator
-#define AT91C_PIO_PB27            (1 << 27) // Pin Controlled by PB27
-#define AT91C_PB27_TIOA2          (AT91C_PIO_PB27) //  Timer Counter 2 Multipurpose Timer I/O Pin A
-#define AT91C_PB27_PWM0           (AT91C_PIO_PB27) //  PWM Channel 0
-#define AT91C_PIO_PB28            (1 << 28) // Pin Controlled by PB28
-#define AT91C_PB28_TIOB2          (AT91C_PIO_PB28) //  Timer Counter 2 Multipurpose Timer I/O Pin B
-#define AT91C_PB28_PWM1           (AT91C_PIO_PB28) //  PWM Channel 1
-#define AT91C_PIO_PB29            (1 << 29) // Pin Controlled by PB29
-#define AT91C_PB29_PCK1           (AT91C_PIO_PB29) //  PMC Programmable Clock Output 1
-#define AT91C_PB29_PWM2           (AT91C_PIO_PB29) //  PWM Channel 2
-#define AT91C_PIO_PB3             (1 <<  3) // Pin Controlled by PB3
-#define AT91C_PB3_ETX1            (AT91C_PIO_PB3) //  Ethernet MAC Transmit Data 1
-#define AT91C_PIO_PB30            (1 << 30) // Pin Controlled by PB30
-#define AT91C_PB30_PCK2           (AT91C_PIO_PB30) //  PMC Programmable Clock Output 2
-#define AT91C_PB30_PWM3           (AT91C_PIO_PB30) //  PWM Channel 3
-#define AT91C_PIO_PB4             (1 <<  4) // Pin Controlled by PB4
-#define AT91C_PB4_ECRS_ECRSDV     (AT91C_PIO_PB4) //  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
-#define AT91C_PIO_PB5             (1 <<  5) // Pin Controlled by PB5
-#define AT91C_PB5_ERX0            (AT91C_PIO_PB5) //  Ethernet MAC Receive Data 0
-#define AT91C_PIO_PB6             (1 <<  6) // Pin Controlled by PB6
-#define AT91C_PB6_ERX1            (AT91C_PIO_PB6) //  Ethernet MAC Receive Data 1
-#define AT91C_PIO_PB7             (1 <<  7) // Pin Controlled by PB7
-#define AT91C_PB7_ERXER           (AT91C_PIO_PB7) //  Ethernet MAC Receive Error
-#define AT91C_PIO_PB8             (1 <<  8) // Pin Controlled by PB8
-#define AT91C_PB8_EMDC            (AT91C_PIO_PB8) //  Ethernet MAC Management Data Clock
-#define AT91C_PIO_PB9             (1 <<  9) // Pin Controlled by PB9
-#define AT91C_PB9_EMDIO           (AT91C_PIO_PB9) //  Ethernet MAC Management Data Input/Output
+/* ***************************************************************************** */
+/*               PIO DEFINITIONS FOR AT91SAM7X256 */
+/* ***************************************************************************** */
+#define AT91C_PIO_PA0             ( 1 << 0 )         /* Pin Controlled by PA0 */
+#define AT91C_PA0_RXD0            ( AT91C_PIO_PA0 )  /*  USART 0 Receive Data */
+#define AT91C_PIO_PA1             ( 1 << 1 )         /* Pin Controlled by PA1 */
+#define AT91C_PA1_TXD0            ( AT91C_PIO_PA1 )  /*  USART 0 Transmit Data */
+#define AT91C_PIO_PA10            ( 1 << 10 )        /* Pin Controlled by PA10 */
+#define AT91C_PA10_TWD            ( AT91C_PIO_PA10 ) /*  TWI Two-wire Serial Data */
+#define AT91C_PIO_PA11            ( 1 << 11 )        /* Pin Controlled by PA11 */
+#define AT91C_PA11_TWCK           ( AT91C_PIO_PA11 ) /*  TWI Two-wire Serial Clock */
+#define AT91C_PIO_PA12            ( 1 << 12 )        /* Pin Controlled by PA12 */
+#define AT91C_PA12_NPCS00         ( AT91C_PIO_PA12 ) /*  SPI 0 Peripheral Chip Select 0 */
+#define AT91C_PIO_PA13            ( 1 << 13 )        /* Pin Controlled by PA13 */
+#define AT91C_PA13_NPCS01         ( AT91C_PIO_PA13 ) /*  SPI 0 Peripheral Chip Select 1 */
+#define AT91C_PA13_PCK1           ( AT91C_PIO_PA13 ) /*  PMC Programmable Clock Output 1 */
+#define AT91C_PIO_PA14            ( 1 << 14 )        /* Pin Controlled by PA14 */
+#define AT91C_PA14_NPCS02         ( AT91C_PIO_PA14 ) /*  SPI 0 Peripheral Chip Select 2 */
+#define AT91C_PA14_IRQ1           ( AT91C_PIO_PA14 ) /*  External Interrupt 1 */
+#define AT91C_PIO_PA15            ( 1 << 15 )        /* Pin Controlled by PA15 */
+#define AT91C_PA15_NPCS03         ( AT91C_PIO_PA15 ) /*  SPI 0 Peripheral Chip Select 3 */
+#define AT91C_PA15_TCLK2          ( AT91C_PIO_PA15 ) /*  Timer Counter 2 external clock input */
+#define AT91C_PIO_PA16            ( 1 << 16 )        /* Pin Controlled by PA16 */
+#define AT91C_PA16_MISO0          ( AT91C_PIO_PA16 ) /*  SPI 0 Master In Slave */
+#define AT91C_PIO_PA17            ( 1 << 17 )        /* Pin Controlled by PA17 */
+#define AT91C_PA17_MOSI0          ( AT91C_PIO_PA17 ) /*  SPI 0 Master Out Slave */
+#define AT91C_PIO_PA18            ( 1 << 18 )        /* Pin Controlled by PA18 */
+#define AT91C_PA18_SPCK0          ( AT91C_PIO_PA18 ) /*  SPI 0 Serial Clock */
+#define AT91C_PIO_PA19            ( 1 << 19 )        /* Pin Controlled by PA19 */
+#define AT91C_PA19_CANRX          ( AT91C_PIO_PA19 ) /*  CAN Receive */
+#define AT91C_PIO_PA2             ( 1 << 2 )         /* Pin Controlled by PA2 */
+#define AT91C_PA2_SCK0            ( AT91C_PIO_PA2 )  /*  USART 0 Serial Clock */
+#define AT91C_PA2_NPCS11          ( AT91C_PIO_PA2 )  /*  SPI 1 Peripheral Chip Select 1 */
+#define AT91C_PIO_PA20            ( 1 << 20 )        /* Pin Controlled by PA20 */
+#define AT91C_PA20_CANTX          ( AT91C_PIO_PA20 ) /*  CAN Transmit */
+#define AT91C_PIO_PA21            ( 1 << 21 )        /* Pin Controlled by PA21 */
+#define AT91C_PA21_TF             ( AT91C_PIO_PA21 ) /*  SSC Transmit Frame Sync */
+#define AT91C_PA21_NPCS10         ( AT91C_PIO_PA21 ) /*  SPI 1 Peripheral Chip Select 0 */
+#define AT91C_PIO_PA22            ( 1 << 22 )        /* Pin Controlled by PA22 */
+#define AT91C_PA22_TK             ( AT91C_PIO_PA22 ) /*  SSC Transmit Clock */
+#define AT91C_PA22_SPCK1          ( AT91C_PIO_PA22 ) /*  SPI 1 Serial Clock */
+#define AT91C_PIO_PA23            ( 1 << 23 )        /* Pin Controlled by PA23 */
+#define AT91C_PA23_TD             ( AT91C_PIO_PA23 ) /*  SSC Transmit data */
+#define AT91C_PA23_MOSI1          ( AT91C_PIO_PA23 ) /*  SPI 1 Master Out Slave */
+#define AT91C_PIO_PA24            ( 1 << 24 )        /* Pin Controlled by PA24 */
+#define AT91C_PA24_RD             ( AT91C_PIO_PA24 ) /*  SSC Receive Data */
+#define AT91C_PA24_MISO1          ( AT91C_PIO_PA24 ) /*  SPI 1 Master In Slave */
+#define AT91C_PIO_PA25            ( 1 << 25 )        /* Pin Controlled by PA25 */
+#define AT91C_PA25_RK             ( AT91C_PIO_PA25 ) /*  SSC Receive Clock */
+#define AT91C_PA25_NPCS11         ( AT91C_PIO_PA25 ) /*  SPI 1 Peripheral Chip Select 1 */
+#define AT91C_PIO_PA26            ( 1 << 26 )        /* Pin Controlled by PA26 */
+#define AT91C_PA26_RF             ( AT91C_PIO_PA26 ) /*  SSC Receive Frame Sync */
+#define AT91C_PA26_NPCS12         ( AT91C_PIO_PA26 ) /*  SPI 1 Peripheral Chip Select 2 */
+#define AT91C_PIO_PA27            ( 1 << 27 )        /* Pin Controlled by PA27 */
+#define AT91C_PA27_DRXD           ( AT91C_PIO_PA27 ) /*  DBGU Debug Receive Data */
+#define AT91C_PA27_PCK3           ( AT91C_PIO_PA27 ) /*  PMC Programmable Clock Output 3 */
+#define AT91C_PIO_PA28            ( 1 << 28 )        /* Pin Controlled by PA28 */
+#define AT91C_PA28_DTXD           ( AT91C_PIO_PA28 ) /*  DBGU Debug Transmit Data */
+#define AT91C_PIO_PA29            ( 1 << 29 )        /* Pin Controlled by PA29 */
+#define AT91C_PA29_FIQ            ( AT91C_PIO_PA29 ) /*  AIC Fast Interrupt Input */
+#define AT91C_PA29_NPCS13         ( AT91C_PIO_PA29 ) /*  SPI 1 Peripheral Chip Select 3 */
+#define AT91C_PIO_PA3             ( 1 << 3 )         /* Pin Controlled by PA3 */
+#define AT91C_PA3_RTS0            ( AT91C_PIO_PA3 )  /*  USART 0 Ready To Send */
+#define AT91C_PA3_NPCS12          ( AT91C_PIO_PA3 )  /*  SPI 1 Peripheral Chip Select 2 */
+#define AT91C_PIO_PA30            ( 1 << 30 )        /* Pin Controlled by PA30 */
+#define AT91C_PA30_IRQ0           ( AT91C_PIO_PA30 ) /*  External Interrupt 0 */
+#define AT91C_PA30_PCK2           ( AT91C_PIO_PA30 ) /*  PMC Programmable Clock Output 2 */
+#define AT91C_PIO_PA4             ( 1 << 4 )         /* Pin Controlled by PA4 */
+#define AT91C_PA4_CTS0            ( AT91C_PIO_PA4 )  /*  USART 0 Clear To Send */
+#define AT91C_PA4_NPCS13          ( AT91C_PIO_PA4 )  /*  SPI 1 Peripheral Chip Select 3 */
+#define AT91C_PIO_PA5             ( 1 << 5 )         /* Pin Controlled by PA5 */
+#define AT91C_PA5_RXD1            ( AT91C_PIO_PA5 )  /*  USART 1 Receive Data */
+#define AT91C_PIO_PA6             ( 1 << 6 )         /* Pin Controlled by PA6 */
+#define AT91C_PA6_TXD1            ( AT91C_PIO_PA6 )  /*  USART 1 Transmit Data */
+#define AT91C_PIO_PA7             ( 1 << 7 )         /* Pin Controlled by PA7 */
+#define AT91C_PA7_SCK1            ( AT91C_PIO_PA7 )  /*  USART 1 Serial Clock */
+#define AT91C_PA7_NPCS01          ( AT91C_PIO_PA7 )  /*  SPI 0 Peripheral Chip Select 1 */
+#define AT91C_PIO_PA8             ( 1 << 8 )         /* Pin Controlled by PA8 */
+#define AT91C_PA8_RTS1            ( AT91C_PIO_PA8 )  /*  USART 1 Ready To Send */
+#define AT91C_PA8_NPCS02          ( AT91C_PIO_PA8 )  /*  SPI 0 Peripheral Chip Select 2 */
+#define AT91C_PIO_PA9             ( 1 << 9 )         /* Pin Controlled by PA9 */
+#define AT91C_PA9_CTS1            ( AT91C_PIO_PA9 )  /*  USART 1 Clear To Send */
+#define AT91C_PA9_NPCS03          ( AT91C_PIO_PA9 )  /*  SPI 0 Peripheral Chip Select 3 */
+#define AT91C_PIO_PB0             ( 1 << 0 )         /* Pin Controlled by PB0 */
+#define AT91C_PB0_ETXCK_EREFCK    ( AT91C_PIO_PB0 )  /*  Ethernet MAC Transmit Clock/Reference Clock */
+#define AT91C_PB0_PCK0            ( AT91C_PIO_PB0 )  /*  PMC Programmable Clock Output 0 */
+#define AT91C_PIO_PB1             ( 1 << 1 )         /* Pin Controlled by PB1 */
+#define AT91C_PB1_ETXEN           ( AT91C_PIO_PB1 )  /*  Ethernet MAC Transmit Enable */
+#define AT91C_PIO_PB10            ( 1 << 10 )        /* Pin Controlled by PB10 */
+#define AT91C_PB10_ETX2           ( AT91C_PIO_PB10 ) /*  Ethernet MAC Transmit Data 2 */
+#define AT91C_PB10_NPCS11         ( AT91C_PIO_PB10 ) /*  SPI 1 Peripheral Chip Select 1 */
+#define AT91C_PIO_PB11            ( 1 << 11 )        /* Pin Controlled by PB11 */
+#define AT91C_PB11_ETX3           ( AT91C_PIO_PB11 ) /*  Ethernet MAC Transmit Data 3 */
+#define AT91C_PB11_NPCS12         ( AT91C_PIO_PB11 ) /*  SPI 1 Peripheral Chip Select 2 */
+#define AT91C_PIO_PB12            ( 1 << 12 )        /* Pin Controlled by PB12 */
+#define AT91C_PB12_ETXER          ( AT91C_PIO_PB12 ) /*  Ethernet MAC Transmit Coding Error */
+#define AT91C_PB12_TCLK0          ( AT91C_PIO_PB12 ) /*  Timer Counter 0 external clock input */
+#define AT91C_PIO_PB13            ( 1 << 13 )        /* Pin Controlled by PB13 */
+#define AT91C_PB13_ERX2           ( AT91C_PIO_PB13 ) /*  Ethernet MAC Receive Data 2 */
+#define AT91C_PB13_NPCS01         ( AT91C_PIO_PB13 ) /*  SPI 0 Peripheral Chip Select 1 */
+#define AT91C_PIO_PB14            ( 1 << 14 )        /* Pin Controlled by PB14 */
+#define AT91C_PB14_ERX3           ( AT91C_PIO_PB14 ) /*  Ethernet MAC Receive Data 3 */
+#define AT91C_PB14_NPCS02         ( AT91C_PIO_PB14 ) /*  SPI 0 Peripheral Chip Select 2 */
+#define AT91C_PIO_PB15            ( 1 << 15 )        /* Pin Controlled by PB15 */
+#define AT91C_PB15_ERXDV          ( AT91C_PIO_PB15 ) /*  Ethernet MAC Receive Data Valid */
+#define AT91C_PIO_PB16            ( 1 << 16 )        /* Pin Controlled by PB16 */
+#define AT91C_PB16_ECOL           ( AT91C_PIO_PB16 ) /*  Ethernet MAC Collision Detected */
+#define AT91C_PB16_NPCS13         ( AT91C_PIO_PB16 ) /*  SPI 1 Peripheral Chip Select 3 */
+#define AT91C_PIO_PB17            ( 1 << 17 )        /* Pin Controlled by PB17 */
+#define AT91C_PB17_ERXCK          ( AT91C_PIO_PB17 ) /*  Ethernet MAC Receive Clock */
+#define AT91C_PB17_NPCS03         ( AT91C_PIO_PB17 ) /*  SPI 0 Peripheral Chip Select 3 */
+#define AT91C_PIO_PB18            ( 1 << 18 )        /* Pin Controlled by PB18 */
+#define AT91C_PB18_EF100          ( AT91C_PIO_PB18 ) /*  Ethernet MAC Force 100 Mbits/sec */
+#define AT91C_PB18_ADTRG          ( AT91C_PIO_PB18 ) /*  ADC External Trigger */
+#define AT91C_PIO_PB19            ( 1 << 19 )        /* Pin Controlled by PB19 */
+#define AT91C_PB19_PWM0           ( AT91C_PIO_PB19 ) /*  PWM Channel 0 */
+#define AT91C_PB19_TCLK1          ( AT91C_PIO_PB19 ) /*  Timer Counter 1 external clock input */
+#define AT91C_PIO_PB2             ( 1 << 2 )         /* Pin Controlled by PB2 */
+#define AT91C_PB2_ETX0            ( AT91C_PIO_PB2 )  /*  Ethernet MAC Transmit Data 0 */
+#define AT91C_PIO_PB20            ( 1 << 20 )        /* Pin Controlled by PB20 */
+#define AT91C_PB20_PWM1           ( AT91C_PIO_PB20 ) /*  PWM Channel 1 */
+#define AT91C_PB20_PCK0           ( AT91C_PIO_PB20 ) /*  PMC Programmable Clock Output 0 */
+#define AT91C_PIO_PB21            ( 1 << 21 )        /* Pin Controlled by PB21 */
+#define AT91C_PB21_PWM2           ( AT91C_PIO_PB21 ) /*  PWM Channel 2 */
+#define AT91C_PB21_PCK1           ( AT91C_PIO_PB21 ) /*  PMC Programmable Clock Output 1 */
+#define AT91C_PIO_PB22            ( 1 << 22 )        /* Pin Controlled by PB22 */
+#define AT91C_PB22_PWM3           ( AT91C_PIO_PB22 ) /*  PWM Channel 3 */
+#define AT91C_PB22_PCK2           ( AT91C_PIO_PB22 ) /*  PMC Programmable Clock Output 2 */
+#define AT91C_PIO_PB23            ( 1 << 23 )        /* Pin Controlled by PB23 */
+#define AT91C_PB23_TIOA0          ( AT91C_PIO_PB23 ) /*  Timer Counter 0 Multipurpose Timer I/O Pin A */
+#define AT91C_PB23_DCD1           ( AT91C_PIO_PB23 ) /*  USART 1 Data Carrier Detect */
+#define AT91C_PIO_PB24            ( 1 << 24 )        /* Pin Controlled by PB24 */
+#define AT91C_PB24_TIOB0          ( AT91C_PIO_PB24 ) /*  Timer Counter 0 Multipurpose Timer I/O Pin B */
+#define AT91C_PB24_DSR1           ( AT91C_PIO_PB24 ) /*  USART 1 Data Set ready */
+#define AT91C_PIO_PB25            ( 1 << 25 )        /* Pin Controlled by PB25 */
+#define AT91C_PB25_TIOA1          ( AT91C_PIO_PB25 ) /*  Timer Counter 1 Multipurpose Timer I/O Pin A */
+#define AT91C_PB25_DTR1           ( AT91C_PIO_PB25 ) /*  USART 1 Data Terminal ready */
+#define AT91C_PIO_PB26            ( 1 << 26 )        /* Pin Controlled by PB26 */
+#define AT91C_PB26_TIOB1          ( AT91C_PIO_PB26 ) /*  Timer Counter 1 Multipurpose Timer I/O Pin B */
+#define AT91C_PB26_RI1            ( AT91C_PIO_PB26 ) /*  USART 1 Ring Indicator */
+#define AT91C_PIO_PB27            ( 1 << 27 )        /* Pin Controlled by PB27 */
+#define AT91C_PB27_TIOA2          ( AT91C_PIO_PB27 ) /*  Timer Counter 2 Multipurpose Timer I/O Pin A */
+#define AT91C_PB27_PWM0           ( AT91C_PIO_PB27 ) /*  PWM Channel 0 */
+#define AT91C_PIO_PB28            ( 1 << 28 )        /* Pin Controlled by PB28 */
+#define AT91C_PB28_TIOB2          ( AT91C_PIO_PB28 ) /*  Timer Counter 2 Multipurpose Timer I/O Pin B */
+#define AT91C_PB28_PWM1           ( AT91C_PIO_PB28 ) /*  PWM Channel 1 */
+#define AT91C_PIO_PB29            ( 1 << 29 )        /* Pin Controlled by PB29 */
+#define AT91C_PB29_PCK1           ( AT91C_PIO_PB29 ) /*  PMC Programmable Clock Output 1 */
+#define AT91C_PB29_PWM2           ( AT91C_PIO_PB29 ) /*  PWM Channel 2 */
+#define AT91C_PIO_PB3             ( 1 << 3 )         /* Pin Controlled by PB3 */
+#define AT91C_PB3_ETX1            ( AT91C_PIO_PB3 )  /*  Ethernet MAC Transmit Data 1 */
+#define AT91C_PIO_PB30            ( 1 << 30 )        /* Pin Controlled by PB30 */
+#define AT91C_PB30_PCK2           ( AT91C_PIO_PB30 ) /*  PMC Programmable Clock Output 2 */
+#define AT91C_PB30_PWM3           ( AT91C_PIO_PB30 ) /*  PWM Channel 3 */
+#define AT91C_PIO_PB4             ( 1 << 4 )         /* Pin Controlled by PB4 */
+#define AT91C_PB4_ECRS_ECRSDV     ( AT91C_PIO_PB4 )  /*  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid */
+#define AT91C_PIO_PB5             ( 1 << 5 )         /* Pin Controlled by PB5 */
+#define AT91C_PB5_ERX0            ( AT91C_PIO_PB5 )  /*  Ethernet MAC Receive Data 0 */
+#define AT91C_PIO_PB6             ( 1 << 6 )         /* Pin Controlled by PB6 */
+#define AT91C_PB6_ERX1            ( AT91C_PIO_PB6 )  /*  Ethernet MAC Receive Data 1 */
+#define AT91C_PIO_PB7             ( 1 << 7 )         /* Pin Controlled by PB7 */
+#define AT91C_PB7_ERXER           ( AT91C_PIO_PB7 )  /*  Ethernet MAC Receive Error */
+#define AT91C_PIO_PB8             ( 1 << 8 )         /* Pin Controlled by PB8 */
+#define AT91C_PB8_EMDC            ( AT91C_PIO_PB8 )  /*  Ethernet MAC Management Data Clock */
+#define AT91C_PIO_PB9             ( 1 << 9 )         /* Pin Controlled by PB9 */
+#define AT91C_PB9_EMDIO           ( AT91C_PIO_PB9 )  /*  Ethernet MAC Management Data Input/Output */
 
-// *****************************************************************************
-//               PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256
-// *****************************************************************************
-#define AT91C_ID_FIQ              ( 0) // Advanced Interrupt Controller (FIQ)
-#define AT91C_ID_SYS              ( 1) // System Peripheral
-#define AT91C_ID_PIOA             ( 2) // Parallel IO Controller A
-#define AT91C_ID_PIOB             ( 3) // Parallel IO Controller B
-#define AT91C_ID_SPI0             ( 4) // Serial Peripheral Interface 0
-#define AT91C_ID_SPI1             ( 5) // Serial Peripheral Interface 1
-#define AT91C_ID_US0              ( 6) // USART 0
-#define AT91C_ID_US1              ( 7) // USART 1
-#define AT91C_ID_SSC              ( 8) // Serial Synchronous Controller
-#define AT91C_ID_TWI              ( 9) // Two-Wire Interface
-#define AT91C_ID_PWMC             (10) // PWM Controller
-#define AT91C_ID_UDP              (11) // USB Device Port
-#define AT91C_ID_TC0              (12) // Timer Counter 0
-#define AT91C_ID_TC1              (13) // Timer Counter 1
-#define AT91C_ID_TC2              (14) // Timer Counter 2
-#define AT91C_ID_CAN              (15) // Control Area Network Controller
-#define AT91C_ID_EMAC             (16) // Ethernet MAC
-#define AT91C_ID_ADC              (17) // Analog-to-Digital Converter
-#define AT91C_ID_AES              (18) // Advanced Encryption Standard 128-bit
-#define AT91C_ID_TDES             (19) // Triple Data Encryption Standard
-#define AT91C_ID_20_Reserved      (20) // Reserved
-#define AT91C_ID_21_Reserved      (21) // Reserved
-#define AT91C_ID_22_Reserved      (22) // Reserved
-#define AT91C_ID_23_Reserved      (23) // Reserved
-#define AT91C_ID_24_Reserved      (24) // Reserved
-#define AT91C_ID_25_Reserved      (25) // Reserved
-#define AT91C_ID_26_Reserved      (26) // Reserved
-#define AT91C_ID_27_Reserved      (27) // Reserved
-#define AT91C_ID_28_Reserved      (28) // Reserved
-#define AT91C_ID_29_Reserved      (29) // Reserved
-#define AT91C_ID_IRQ0             (30) // Advanced Interrupt Controller (IRQ0)
-#define AT91C_ID_IRQ1             (31) // Advanced Interrupt Controller (IRQ1)
+/* ***************************************************************************** */
+/*               PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 */
+/* ***************************************************************************** */
+#define AT91C_ID_FIQ            ( 0 )  /* Advanced Interrupt Controller (FIQ) */
+#define AT91C_ID_SYS            ( 1 )  /* System Peripheral */
+#define AT91C_ID_PIOA           ( 2 )  /* Parallel IO Controller A */
+#define AT91C_ID_PIOB           ( 3 )  /* Parallel IO Controller B */
+#define AT91C_ID_SPI0           ( 4 )  /* Serial Peripheral Interface 0 */
+#define AT91C_ID_SPI1           ( 5 )  /* Serial Peripheral Interface 1 */
+#define AT91C_ID_US0            ( 6 )  /* USART 0 */
+#define AT91C_ID_US1            ( 7 )  /* USART 1 */
+#define AT91C_ID_SSC            ( 8 )  /* Serial Synchronous Controller */
+#define AT91C_ID_TWI            ( 9 )  /* Two-Wire Interface */
+#define AT91C_ID_PWMC           ( 10 ) /* PWM Controller */
+#define AT91C_ID_UDP            ( 11 ) /* USB Device Port */
+#define AT91C_ID_TC0            ( 12 ) /* Timer Counter 0 */
+#define AT91C_ID_TC1            ( 13 ) /* Timer Counter 1 */
+#define AT91C_ID_TC2            ( 14 ) /* Timer Counter 2 */
+#define AT91C_ID_CAN            ( 15 ) /* Control Area Network Controller */
+#define AT91C_ID_EMAC           ( 16 ) /* Ethernet MAC */
+#define AT91C_ID_ADC            ( 17 ) /* Analog-to-Digital Converter */
+#define AT91C_ID_AES            ( 18 ) /* Advanced Encryption Standard 128-bit */
+#define AT91C_ID_TDES           ( 19 ) /* Triple Data Encryption Standard */
+#define AT91C_ID_20_Reserved    ( 20 ) /* Reserved */
+#define AT91C_ID_21_Reserved    ( 21 ) /* Reserved */
+#define AT91C_ID_22_Reserved    ( 22 ) /* Reserved */
+#define AT91C_ID_23_Reserved    ( 23 ) /* Reserved */
+#define AT91C_ID_24_Reserved    ( 24 ) /* Reserved */
+#define AT91C_ID_25_Reserved    ( 25 ) /* Reserved */
+#define AT91C_ID_26_Reserved    ( 26 ) /* Reserved */
+#define AT91C_ID_27_Reserved    ( 27 ) /* Reserved */
+#define AT91C_ID_28_Reserved    ( 28 ) /* Reserved */
+#define AT91C_ID_29_Reserved    ( 29 ) /* Reserved */
+#define AT91C_ID_IRQ0           ( 30 ) /* Advanced Interrupt Controller (IRQ0) */
+#define AT91C_ID_IRQ1           ( 31 ) /* Advanced Interrupt Controller (IRQ1) */
 
-// *****************************************************************************
-//               BASE ADDRESS DEFINITIONS FOR AT91SAM7X256
-// *****************************************************************************
-#define AT91C_BASE_SYS            (0xFFFFF000) // (SYS) Base Address
-#define AT91C_BASE_AIC            (0xFFFFF000) // (AIC) Base Address
-#define AT91C_BASE_PDC_DBGU       (0xFFFFF300) // (PDC_DBGU) Base Address
-#define AT91C_BASE_DBGU           (0xFFFFF200) // (DBGU) Base Address
-#define AT91C_BASE_PIOA           (0xFFFFF400) // (PIOA) Base Address
-#define AT91C_BASE_PIOB           (0xFFFFF600) // (PIOB) Base Address
-#define AT91C_BASE_CKGR           (0xFFFFFC20) // (CKGR) Base Address
-#define AT91C_BASE_PMC            (0xFFFFFC00) // (PMC) Base Address
-#define AT91C_BASE_RSTC           (0xFFFFFD00) // (RSTC) Base Address
-#define AT91C_BASE_RTTC           (0xFFFFFD20) // (RTTC) Base Address
-#define AT91C_BASE_PITC           (0xFFFFFD30) // (PITC) Base Address
-#define AT91C_BASE_WDTC           (0xFFFFFD40) // (WDTC) Base Address
-#define AT91C_BASE_VREG           (0xFFFFFD60) // (VREG) Base Address
-#define AT91C_BASE_MC             (0xFFFFFF00) // (MC) Base Address
-#define AT91C_BASE_PDC_SPI1       (0xFFFE4100) // (PDC_SPI1) Base Address
-#define AT91C_BASE_SPI1           (0xFFFE4000) // (SPI1) Base Address
-#define AT91C_BASE_PDC_SPI0       (0xFFFE0100) // (PDC_SPI0) Base Address
-#define AT91C_BASE_SPI0           (0xFFFE0000) // (SPI0) Base Address
-#define AT91C_BASE_PDC_US1        (0xFFFC4100) // (PDC_US1) Base Address
-#define AT91C_BASE_US1            (0xFFFC4000) // (US1) Base Address
-#define AT91C_BASE_PDC_US0        (0xFFFC0100) // (PDC_US0) Base Address
-#define AT91C_BASE_US0            (0xFFFC0000) // (US0) Base Address
-#define AT91C_BASE_PDC_SSC        (0xFFFD4100) // (PDC_SSC) Base Address
-#define AT91C_BASE_SSC            (0xFFFD4000) // (SSC) Base Address
-#define AT91C_BASE_TWI            (0xFFFB8000) // (TWI) Base Address
-#define AT91C_BASE_PWMC_CH3       (0xFFFCC260) // (PWMC_CH3) Base Address
-#define AT91C_BASE_PWMC_CH2       (0xFFFCC240) // (PWMC_CH2) Base Address
-#define AT91C_BASE_PWMC_CH1       (0xFFFCC220) // (PWMC_CH1) Base Address
-#define AT91C_BASE_PWMC_CH0       (0xFFFCC200) // (PWMC_CH0) Base Address
-#define AT91C_BASE_PWMC           (0xFFFCC000) // (PWMC) Base Address
-#define AT91C_BASE_UDP            (0xFFFB0000) // (UDP) Base Address
-#define AT91C_BASE_TC0            (0xFFFA0000) // (TC0) Base Address
-#define AT91C_BASE_TC1            (0xFFFA0040) // (TC1) Base Address
-#define AT91C_BASE_TC2            (0xFFFA0080) // (TC2) Base Address
-#define AT91C_BASE_TCB            (0xFFFA0000) // (TCB) Base Address
-#define AT91C_BASE_CAN_MB0        (0xFFFD0200) // (CAN_MB0) Base Address
-#define AT91C_BASE_CAN_MB1        (0xFFFD0220) // (CAN_MB1) Base Address
-#define AT91C_BASE_CAN_MB2        (0xFFFD0240) // (CAN_MB2) Base Address
-#define AT91C_BASE_CAN_MB3        (0xFFFD0260) // (CAN_MB3) Base Address
-#define AT91C_BASE_CAN_MB4        (0xFFFD0280) // (CAN_MB4) Base Address
-#define AT91C_BASE_CAN_MB5        (0xFFFD02A0) // (CAN_MB5) Base Address
-#define AT91C_BASE_CAN_MB6        (0xFFFD02C0) // (CAN_MB6) Base Address
-#define AT91C_BASE_CAN_MB7        (0xFFFD02E0) // (CAN_MB7) Base Address
-#define AT91C_BASE_CAN            (0xFFFD0000) // (CAN) Base Address
-#define AT91C_BASE_EMAC           (0xFFFDC000) // (EMAC) Base Address
-#define AT91C_BASE_PDC_ADC        (0xFFFD8100) // (PDC_ADC) Base Address
-#define AT91C_BASE_ADC            (0xFFFD8000) // (ADC) Base Address
-#define AT91C_BASE_PDC_AES        (0xFFFA4100) // (PDC_AES) Base Address
-#define AT91C_BASE_AES            (0xFFFA4000) // (AES) Base Address
-#define AT91C_BASE_PDC_TDES       (0xFFFA8100) // (PDC_TDES) Base Address
-#define AT91C_BASE_TDES           (0xFFFA8000) // (TDES) Base Address
+/* ***************************************************************************** */
+/*               BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 */
+/* ***************************************************************************** */
+#define AT91C_BASE_SYS         ( 0xFFFFF000 )  /* (SYS) Base Address */
+#define AT91C_BASE_AIC         ( 0xFFFFF000 )  /* (AIC) Base Address */
+#define AT91C_BASE_PDC_DBGU    ( 0xFFFFF300 )  /* (PDC_DBGU) Base Address */
+#define AT91C_BASE_DBGU        ( 0xFFFFF200 )  /* (DBGU) Base Address */
+#define AT91C_BASE_PIOA        ( 0xFFFFF400 )  /* (PIOA) Base Address */
+#define AT91C_BASE_PIOB        ( 0xFFFFF600 )  /* (PIOB) Base Address */
+#define AT91C_BASE_CKGR        ( 0xFFFFFC20 )  /* (CKGR) Base Address */
+#define AT91C_BASE_PMC         ( 0xFFFFFC00 )  /* (PMC) Base Address */
+#define AT91C_BASE_RSTC        ( 0xFFFFFD00 )  /* (RSTC) Base Address */
+#define AT91C_BASE_RTTC        ( 0xFFFFFD20 )  /* (RTTC) Base Address */
+#define AT91C_BASE_PITC        ( 0xFFFFFD30 )  /* (PITC) Base Address */
+#define AT91C_BASE_WDTC        ( 0xFFFFFD40 )  /* (WDTC) Base Address */
+#define AT91C_BASE_VREG        ( 0xFFFFFD60 )  /* (VREG) Base Address */
+#define AT91C_BASE_MC          ( 0xFFFFFF00 )  /* (MC) Base Address */
+#define AT91C_BASE_PDC_SPI1    ( 0xFFFE4100 )  /* (PDC_SPI1) Base Address */
+#define AT91C_BASE_SPI1        ( 0xFFFE4000 )  /* (SPI1) Base Address */
+#define AT91C_BASE_PDC_SPI0    ( 0xFFFE0100 )  /* (PDC_SPI0) Base Address */
+#define AT91C_BASE_SPI0        ( 0xFFFE0000 )  /* (SPI0) Base Address */
+#define AT91C_BASE_PDC_US1     ( 0xFFFC4100 )  /* (PDC_US1) Base Address */
+#define AT91C_BASE_US1         ( 0xFFFC4000 )  /* (US1) Base Address */
+#define AT91C_BASE_PDC_US0     ( 0xFFFC0100 )  /* (PDC_US0) Base Address */
+#define AT91C_BASE_US0         ( 0xFFFC0000 )  /* (US0) Base Address */
+#define AT91C_BASE_PDC_SSC     ( 0xFFFD4100 )  /* (PDC_SSC) Base Address */
+#define AT91C_BASE_SSC         ( 0xFFFD4000 )  /* (SSC) Base Address */
+#define AT91C_BASE_TWI         ( 0xFFFB8000 )  /* (TWI) Base Address */
+#define AT91C_BASE_PWMC_CH3    ( 0xFFFCC260 )  /* (PWMC_CH3) Base Address */
+#define AT91C_BASE_PWMC_CH2    ( 0xFFFCC240 )  /* (PWMC_CH2) Base Address */
+#define AT91C_BASE_PWMC_CH1    ( 0xFFFCC220 )  /* (PWMC_CH1) Base Address */
+#define AT91C_BASE_PWMC_CH0    ( 0xFFFCC200 )  /* (PWMC_CH0) Base Address */
+#define AT91C_BASE_PWMC        ( 0xFFFCC000 )  /* (PWMC) Base Address */
+#define AT91C_BASE_UDP         ( 0xFFFB0000 )  /* (UDP) Base Address */
+#define AT91C_BASE_TC0         ( 0xFFFA0000 )  /* (TC0) Base Address */
+#define AT91C_BASE_TC1         ( 0xFFFA0040 )  /* (TC1) Base Address */
+#define AT91C_BASE_TC2         ( 0xFFFA0080 )  /* (TC2) Base Address */
+#define AT91C_BASE_TCB         ( 0xFFFA0000 )  /* (TCB) Base Address */
+#define AT91C_BASE_CAN_MB0     ( 0xFFFD0200 )  /* (CAN_MB0) Base Address */
+#define AT91C_BASE_CAN_MB1     ( 0xFFFD0220 )  /* (CAN_MB1) Base Address */
+#define AT91C_BASE_CAN_MB2     ( 0xFFFD0240 )  /* (CAN_MB2) Base Address */
+#define AT91C_BASE_CAN_MB3     ( 0xFFFD0260 )  /* (CAN_MB3) Base Address */
+#define AT91C_BASE_CAN_MB4     ( 0xFFFD0280 )  /* (CAN_MB4) Base Address */
+#define AT91C_BASE_CAN_MB5     ( 0xFFFD02A0 )  /* (CAN_MB5) Base Address */
+#define AT91C_BASE_CAN_MB6     ( 0xFFFD02C0 )  /* (CAN_MB6) Base Address */
+#define AT91C_BASE_CAN_MB7     ( 0xFFFD02E0 )  /* (CAN_MB7) Base Address */
+#define AT91C_BASE_CAN         ( 0xFFFD0000 )  /* (CAN) Base Address */
+#define AT91C_BASE_EMAC        ( 0xFFFDC000 )  /* (EMAC) Base Address */
+#define AT91C_BASE_PDC_ADC     ( 0xFFFD8100 )  /* (PDC_ADC) Base Address */
+#define AT91C_BASE_ADC         ( 0xFFFD8000 )  /* (ADC) Base Address */
+#define AT91C_BASE_PDC_AES     ( 0xFFFA4100 )  /* (PDC_AES) Base Address */
+#define AT91C_BASE_AES         ( 0xFFFA4000 )  /* (AES) Base Address */
+#define AT91C_BASE_PDC_TDES    ( 0xFFFA8100 )  /* (PDC_TDES) Base Address */
+#define AT91C_BASE_TDES        ( 0xFFFA8000 )  /* (TDES) Base Address */
 
-// *****************************************************************************
-//               MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256
-// *****************************************************************************
-#define AT91C_ISRAM               (0x00200000) // Internal SRAM base address
-#define AT91C_ISRAM_SIZE             (0x00010000) // Internal SRAM size in byte (64 Kbyte)
-#define AT91C_IFLASH                 (0x00100000) // Internal ROM base address
-#define AT91C_IFLASH_SIZE           (0x00040000) // Internal ROM size in byte (256 Kbyte)
+/* ***************************************************************************** */
+/*               MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 */
+/* ***************************************************************************** */
+#define AT91C_ISRAM          ( 0x00200000 )    /* Internal SRAM base address */
+#define AT91C_ISRAM_SIZE     ( 0x00010000 )    /* Internal SRAM size in byte (64 Kbyte) */
+#define AT91C_IFLASH         ( 0x00100000 )    /* Internal ROM base address */
+#define AT91C_IFLASH_SIZE    ( 0x00040000 )    /* Internal ROM size in byte (256 Kbyte) */
diff --git a/portable/IAR/AtmelSAM7S64/ISR_Support.h b/portable/IAR/AtmelSAM7S64/ISR_Support.h
index 4651c2d13..d63e908b9 100644
--- a/portable/IAR/AtmelSAM7S64/ISR_Support.h
+++ b/portable/IAR/AtmelSAM7S64/ISR_Support.h
@@ -1,105 +1,151 @@
-;/*
-; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
-; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
-; *
-; * SPDX-License-Identifier: MIT
-; *
-; * Permission is hereby granted, free of charge, to any person obtaining a copy of
-; * this software and associated documentation files (the "Software"), to deal in
-; * the Software without restriction, including without limitation the rights to
-; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
-; * the Software, and to permit persons to whom the Software is furnished to do so,
-; * subject to the following conditions:
-; *
-; * The above copyright notice and this permission notice shall be included in all
-; * copies or substantial portions of the Software.
-; *
-; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-; *
-; * https://www.FreeRTOS.org
-; * https://github.com/FreeRTOS
-; *
-; */
+; /*
+   * ; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+   * ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+   * ; *
+   * ; * SPDX-License-Identifier: MIT
+   * ; *
+   * ; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+   * ; * this software and associated documentation files (the "Software"), to deal in
+   * ; * the Software without restriction, including without limitation the rights to
+   * ; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+   * ; * the Software, and to permit persons to whom the Software is furnished to do so,
+   * ; * subject to the following conditions:
+   * ; *
+   * ; * The above copyright notice and this permission notice shall be included in all
+   * ; * copies or substantial portions of the Software.
+   * ; *
+   * ; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+   * ; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+   * ; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+   * ; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+   * ; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+   * ; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+   * ; *
+   * ; * https://www.FreeRTOS.org
+   * ; * https://github.com/FreeRTOS
+   * ; *
+   * ; */
 
-    EXTERN pxCurrentTCB
-    EXTERN ulCriticalNesting
+EXTERN pxCurrentTCB
+EXTERN ulCriticalNesting
 
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Context save and restore macro definitions
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;
+Context save and restore macro definitions
+;
 
 portSAVE_CONTEXT MACRO
 
-    ; Push R0 as we are going to use the register.
-    STMDB   SP!, {R0}
+;
+Push R0 as we are going to use the register.
+   STMDB SP !, {
+    R0
+}
 
-    ; Set R0 to point to the task stack pointer.
-    STMDB   SP, {SP}^
-    NOP
-    SUB     SP, SP, #4
-    LDMIA   SP!, {R0}
+Set R0 to point to the task stack pointer.
+   STMDB SP, {
+    SP
+}
+^
+NOP
+SUB SP, SP, # 4
+LDMIA SP !, {
+    R0
+}
 
-    ; Push the return address onto the stack.
-    STMDB   R0!, {LR}
+;
+Push the return address onto the stack.
+          STMDB R0 !, {
+           LR
+       }
 
-    ; Now we have saved LR we can use it instead of R0.
-    MOV     LR, R0
+       Now we have saved LR we can use it instead of R0.
+          MOV LR, R0
 
-    ; Pop R0 so we can save it onto the system mode stack.
-    LDMIA   SP!, {R0}
+;
 
-    ; Push all the system mode registers onto the task stack.
-    STMDB   LR, {R0-LR}^
-    NOP
-    SUB     LR, LR, #60
+Pop R0 so we can save it onto the system mode stack.
+   LDMIA SP !, {
+    R0
+}
 
-    ; Push the SPSR onto the task stack.
-    MRS     R0, SPSR
-    STMDB   LR!, {R0}
+Push all the system mode registers onto the task stack.
+   STMDB LR, {
+    R0 - LR
+}
+^
+NOP
+SUB LR, LR, # 60
 
-    LDR     R0, =ulCriticalNesting
-    LDR     R0, [R0]
-    STMDB   LR!, {R0}
+;
+Push the SPSR onto the task stack.
+   MRS R0, SPSR
+STMDB LR !, {
+    R0
+}
 
-    ; Store the new top of stack for the task.
-    LDR     R1, =pxCurrentTCB
-    LDR     R0, [R1]
-    STR     LR, [R0]
+LDR R0, = ulCriticalNesting
+          LDR R0, [ R0 ]
+STMDB LR !, {
+    R0
+}
 
-    ENDM
+Store the new top of stack
+
+for the task.
+   LDR R1, = pxCurrentTCB
+             LDR R0, [ R1 ]
+STR LR, [ R0 ]
+
+ENDM
 
 
 portRESTORE_CONTEXT MACRO
 
-    ; Set the LR to the task stack.
-    LDR     R1, =pxCurrentTCB
-    LDR     R0, [R1]
-    LDR     LR, [R0]
+;
+Set the LR to the task stack.
+   LDR R1, = pxCurrentTCB
+             LDR R0, [ R1 ]
+LDR LR, [ R0 ]
 
-    ; The critical nesting depth is the first item on the stack.
-    ; Load it into the ulCriticalNesting variable.
-    LDR     R0, =ulCriticalNesting
-    LDMFD   LR!, {R1}
-    STR     R1, [R0]
+;
+The critical nesting depth is the first item on the stack.
+   ;
+Load it into the ulCriticalNesting variable.
+   LDR R0, = ulCriticalNesting
+             LDMFD LR !, {
+    R1
+}
 
-    ; Get the SPSR from the stack.
-    LDMFD   LR!, {R0}
-    MSR     SPSR_cxsf, R0
+STR R1, [ R0 ]
 
-    ; Restore all system mode registers for the task.
-    LDMFD   LR, {R0-R14}^
-    NOP
+;
+Get the SPSR from the stack.
+   LDMFD LR !, {
+    R0
+}
+MSR SPSR_cxsf, R0
 
-    ; Restore the return address.
-    LDR     LR, [LR, #+60]
+;
+Restore all system mode registers
 
-    ; And return - correcting the offset in the LR to obtain the
-    ; correct address.
-    SUBS    PC, LR, #4
+for the task.
+   LDMFD LR, {
+    R0 - R14
+}
 
-    ENDM
+^
+NOP
+
+;
+Restore the return address.
+          LDR LR, [ LR, # + 60 ]
+
+;
+
+And return -correcting the offset in the LR to obtain the
+;
+
+correct address.
+   SUBS PC, LR, # 4
+
+ENDM
diff --git a/portable/IAR/AtmelSAM7S64/lib_AT91SAM7S64.h b/portable/IAR/AtmelSAM7S64/lib_AT91SAM7S64.h
index 144dc73c2..a392be1a7 100644
--- a/portable/IAR/AtmelSAM7S64/lib_AT91SAM7S64.h
+++ b/portable/IAR/AtmelSAM7S64/lib_AT91SAM7S64.h
@@ -1,3265 +1,3113 @@
-//*----------------------------------------------------------------------------
-//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
-//*----------------------------------------------------------------------------
-//* The software is delivered "AS IS" without warranty or condition of any
-//* kind, either express, implied or statutory. This includes without
-//* limitation any warranty or condition with respect to merchantability or
-//* fitness for any particular purpose, or against the infringements of
-//* intellectual property rights of others.
-//*----------------------------------------------------------------------------
-//* File Name           : lib_AT91SAM7S64.h
-//* Object              : AT91SAM7S64 inlined functions
-//* Generated           : AT91 SW Application Group  07/16/2004 (07:43:09)
-//*
-//* CVS Reference       : /lib_MC_SAM.h/1.3/Thu Mar 25 15:19:14 2004//
-//* CVS Reference       : /lib_pdc_1363d.h/1.2/Wed Feb 19 09:25:22 2003//
-//* CVS Reference       : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003//
-//* CVS Reference       : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003//
-//* CVS Reference       : /lib_spi2.h/1.1/Mon Aug 25 13:23:52 2003//
-//* CVS Reference       : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//
-//* CVS Reference       : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//
-//* CVS Reference       : /lib_pmc_SAM.h/1.6/Tue Apr 27 13:53:52 2004//
-//* CVS Reference       : /lib_adc.h/1.6/Fri Oct 17 08:12:38 2003//
-//* CVS Reference       : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003//
-//* CVS Reference       : /lib_twi.h/1.2/Fri Jan 31 12:19:38 2003//
-//* CVS Reference       : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002//
-//* CVS Reference       : /lib_udp.h/1.3/Fri Jan 31 12:19:48 2003//
-//* CVS Reference       : /lib_aic.h/1.3/Fri Jul 12 07:46:12 2002//
-//*----------------------------------------------------------------------------
+/**---------------------------------------------------------------------------- */
+/**         ATMEL Microcontroller Software Support  -  ROUSSET  - */
+/**---------------------------------------------------------------------------- */
+/** The software is delivered "AS IS" without warranty or condition of any */
+/** kind, either express, implied or statutory. This includes without */
+/** limitation any warranty or condition with respect to merchantability or */
+/** fitness for any particular purpose, or against the infringements of */
+/** intellectual property rights of others. */
+/**---------------------------------------------------------------------------- */
+/** File Name           : lib_AT91SAM7S64.h */
+/** Object              : AT91SAM7S64 inlined functions */
+/** Generated           : AT91 SW Application Group  07/16/2004 (07:43:09) */
+/** */
+/** CVS Reference       : /lib_MC_SAM.h/1.3/Thu Mar 25 15:19:14 2004// */
+/** CVS Reference       : /lib_pdc_1363d.h/1.2/Wed Feb 19 09:25:22 2003// */
+/** CVS Reference       : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003// */
+/** CVS Reference       : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// */
+/** CVS Reference       : /lib_spi2.h/1.1/Mon Aug 25 13:23:52 2003// */
+/** CVS Reference       : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// */
+/** CVS Reference       : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// */
+/** CVS Reference       : /lib_pmc_SAM.h/1.6/Tue Apr 27 13:53:52 2004// */
+/** CVS Reference       : /lib_adc.h/1.6/Fri Oct 17 08:12:38 2003// */
+/** CVS Reference       : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// */
+/** CVS Reference       : /lib_twi.h/1.2/Fri Jan 31 12:19:38 2003// */
+/** CVS Reference       : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002// */
+/** CVS Reference       : /lib_udp.h/1.3/Fri Jan 31 12:19:48 2003// */
+/** CVS Reference       : /lib_aic.h/1.3/Fri Jul 12 07:46:12 2002// */
+/**---------------------------------------------------------------------------- */
 
 #ifndef lib_AT91SAM7S64_H
 #define lib_AT91SAM7S64_H
 
 /* *****************************************************************************
-                SOFTWARE API FOR MC
-   ***************************************************************************** */
+*               SOFTWARE API FOR MC
+***************************************************************************** */
 
-#define AT91C_MC_CORRECT_KEY  ((unsigned int) 0x5A << 24) // (MC) Correct Protect Key
+#define AT91C_MC_CORRECT_KEY    ( ( unsigned int ) 0x5A << 24 ) /* (MC) Correct Protect Key */
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MC_Remap
-//* \brief Make Remap
-//*----------------------------------------------------------------------------
-__inline void AT91F_MC_Remap (void)     //
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_MC_Remap */
+/** \brief Make Remap */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_MC_Remap( void ) /* */
 {
-    AT91PS_MC pMC = (AT91PS_MC) AT91C_BASE_MC;
+    AT91PS_MC pMC = ( AT91PS_MC ) AT91C_BASE_MC;
 
     pMC->MC_RCR = AT91C_MC_RCB;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MC_EFC_CfgModeReg
-//* \brief Configure the EFC Mode Register of the MC controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_MC_EFC_CfgModeReg (
-    AT91PS_MC pMC, // pointer to a MC controller
-    unsigned int mode)        // mode register
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_MC_EFC_CfgModeReg */
+/** \brief Configure the EFC Mode Register of the MC controller */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_MC_EFC_CfgModeReg( AT91PS_MC pMC,      /* pointer to a MC controller */
+                                       unsigned int mode ) /* mode register */
 {
-    // Write to the FMR register
+    /* Write to the FMR register */
     pMC->MC_FMR = mode;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MC_EFC_GetModeReg
-//* \brief Return MC EFC Mode Regsiter
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_MC_EFC_GetModeReg(
-    AT91PS_MC pMC) // pointer to a MC controller
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_MC_EFC_GetModeReg */
+/** \brief Return MC EFC Mode Regsiter */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_MC_EFC_GetModeReg( AT91PS_MC pMC ) /* pointer to a MC controller */
 {
     return pMC->MC_FMR;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MC_EFC_ComputeFMCN
-//* \brief Return MC EFC Mode Regsiter
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_MC_EFC_ComputeFMCN(
-    int master_clock) // master clock in Hz
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_MC_EFC_ComputeFMCN */
+/** \brief Return MC EFC Mode Regsiter */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_MC_EFC_ComputeFMCN( int master_clock ) /* master clock in Hz */
 {
-    return (master_clock/1000000 +2);
+    return( master_clock / 1000000 + 2 );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MC_EFC_PerformCmd
-//* \brief Perform EFC Command
-//*----------------------------------------------------------------------------
-__inline void AT91F_MC_EFC_PerformCmd (
-    AT91PS_MC pMC, // pointer to a MC controller
-    unsigned int transfer_cmd)
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_MC_EFC_PerformCmd */
+/** \brief Perform EFC Command */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_MC_EFC_PerformCmd( AT91PS_MC pMC, /* pointer to a MC controller */
+                                       unsigned int transfer_cmd )
 {
     pMC->MC_FCR = transfer_cmd;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MC_EFC_GetStatus
-//* \brief Return MC EFC Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_MC_EFC_GetStatus(
-    AT91PS_MC pMC) // pointer to a MC controller
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_MC_EFC_GetStatus */
+/** \brief Return MC EFC Status */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_MC_EFC_GetStatus( AT91PS_MC pMC ) /* pointer to a MC controller */
 {
     return pMC->MC_FSR;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MC_EFC_IsInterruptMasked
-//* \brief Test if EFC MC Interrupt is Masked
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_MC_EFC_IsInterruptMasked(
-        AT91PS_MC pMC,   // \arg  pointer to a MC controller
-        unsigned int flag) // \arg  flag to be tested
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_MC_EFC_IsInterruptMasked */
+/** \brief Test if EFC MC Interrupt is Masked */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_MC_EFC_IsInterruptMasked( AT91PS_MC pMC,      /* \arg  pointer to a MC controller */
+                                                      unsigned int flag ) /* \arg  flag to be tested */
 {
-    return (AT91F_MC_EFC_GetModeReg(pMC) & flag);
+    return( AT91F_MC_EFC_GetModeReg( pMC ) & flag );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MC_EFC_IsInterruptSet
-//* \brief Test if EFC MC Interrupt is Set
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_MC_EFC_IsInterruptSet(
-        AT91PS_MC pMC,   // \arg  pointer to a MC controller
-        unsigned int flag) // \arg  flag to be tested
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_MC_EFC_IsInterruptSet */
+/** \brief Test if EFC MC Interrupt is Set */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_MC_EFC_IsInterruptSet( AT91PS_MC pMC,      /* \arg  pointer to a MC controller */
+                                                   unsigned int flag ) /* \arg  flag to be tested */
 {
-    return (AT91F_MC_EFC_GetStatus(pMC) & flag);
+    return( AT91F_MC_EFC_GetStatus( pMC ) & flag );
 }
 
 /* *****************************************************************************
-                SOFTWARE API FOR PDC
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_SetNextRx
-//* \brief Set the next receive transfer descriptor
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_SetNextRx (
-    AT91PS_PDC pPDC,     // \arg pointer to a PDC controller
-    char *address,       // \arg address to the next bloc to be received
-    unsigned int bytes)  // \arg number of bytes to be received
+*               SOFTWARE API FOR PDC
+***************************************************************************** */
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_SetNextRx */
+/** \brief Set the next receive transfer descriptor */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_PDC_SetNextRx( AT91PS_PDC pPDC,     /* \arg pointer to a PDC controller */
+                                   char * address,      /* \arg address to the next bloc to be received */
+                                   unsigned int bytes ) /* \arg number of bytes to be received */
 {
-    pPDC->PDC_RNPR = (unsigned int) address;
+    pPDC->PDC_RNPR = ( unsigned int ) address;
     pPDC->PDC_RNCR = bytes;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_SetNextTx
-//* \brief Set the next transmit transfer descriptor
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_SetNextTx (
-    AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
-    char *address,         // \arg address to the next bloc to be transmitted
-    unsigned int bytes)    // \arg number of bytes to be transmitted
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_SetNextTx */
+/** \brief Set the next transmit transfer descriptor */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_PDC_SetNextTx( AT91PS_PDC pPDC,     /* \arg pointer to a PDC controller */
+                                   char * address,      /* \arg address to the next bloc to be transmitted */
+                                   unsigned int bytes ) /* \arg number of bytes to be transmitted */
 {
-    pPDC->PDC_TNPR = (unsigned int) address;
+    pPDC->PDC_TNPR = ( unsigned int ) address;
     pPDC->PDC_TNCR = bytes;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_SetRx
-//* \brief Set the receive transfer descriptor
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_SetRx (
-    AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
-    char *address,         // \arg address to the next bloc to be received
-    unsigned int bytes)    // \arg number of bytes to be received
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_SetRx */
+/** \brief Set the receive transfer descriptor */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_PDC_SetRx( AT91PS_PDC pPDC,     /* \arg pointer to a PDC controller */
+                               char * address,      /* \arg address to the next bloc to be received */
+                               unsigned int bytes ) /* \arg number of bytes to be received */
 {
-    pPDC->PDC_RPR = (unsigned int) address;
+    pPDC->PDC_RPR = ( unsigned int ) address;
     pPDC->PDC_RCR = bytes;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_SetTx
-//* \brief Set the transmit transfer descriptor
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_SetTx (
-    AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
-    char *address,         // \arg address to the next bloc to be transmitted
-    unsigned int bytes)    // \arg number of bytes to be transmitted
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_SetTx */
+/** \brief Set the transmit transfer descriptor */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_PDC_SetTx( AT91PS_PDC pPDC,     /* \arg pointer to a PDC controller */
+                               char * address,      /* \arg address to the next bloc to be transmitted */
+                               unsigned int bytes ) /* \arg number of bytes to be transmitted */
 {
-    pPDC->PDC_TPR = (unsigned int) address;
+    pPDC->PDC_TPR = ( unsigned int ) address;
     pPDC->PDC_TCR = bytes;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_EnableTx
-//* \brief Enable transmit
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_EnableTx (
-    AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_EnableTx */
+/** \brief Enable transmit */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_PDC_EnableTx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
 {
     pPDC->PDC_PTCR = AT91C_PDC_TXTEN;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_EnableRx
-//* \brief Enable receive
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_EnableRx (
-    AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_EnableRx */
+/** \brief Enable receive */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_PDC_EnableRx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
 {
     pPDC->PDC_PTCR = AT91C_PDC_RXTEN;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_DisableTx
-//* \brief Disable transmit
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_DisableTx (
-    AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_DisableTx */
+/** \brief Disable transmit */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_PDC_DisableTx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
 {
     pPDC->PDC_PTCR = AT91C_PDC_TXTDIS;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_DisableRx
-//* \brief Disable receive
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_DisableRx (
-    AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_DisableRx */
+/** \brief Disable receive */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_PDC_DisableRx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
 {
     pPDC->PDC_PTCR = AT91C_PDC_RXTDIS;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_IsTxEmpty
-//* \brief Test if the current transfer descriptor has been sent
-//*----------------------------------------------------------------------------
-__inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete
-    AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_IsTxEmpty */
+/** \brief Test if the current transfer descriptor has been sent */
+/**---------------------------------------------------------------------------- */
+__inline int AT91F_PDC_IsTxEmpty( /* \return return 1 if transfer is complete */
+    AT91PS_PDC pPDC )             /* \arg pointer to a PDC controller */
 {
-    return !(pPDC->PDC_TCR);
+    return !( pPDC->PDC_TCR );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_IsNextTxEmpty
-//* \brief Test if the next transfer descriptor has been moved to the current td
-//*----------------------------------------------------------------------------
-__inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete
-    AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_IsNextTxEmpty */
+/** \brief Test if the next transfer descriptor has been moved to the current td */
+/**---------------------------------------------------------------------------- */
+__inline int AT91F_PDC_IsNextTxEmpty( /* \return return 1 if transfer is complete */
+    AT91PS_PDC pPDC )                 /* \arg pointer to a PDC controller */
 {
-    return !(pPDC->PDC_TNCR);
+    return !( pPDC->PDC_TNCR );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_IsRxEmpty
-//* \brief Test if the current transfer descriptor has been filled
-//*----------------------------------------------------------------------------
-__inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete
-    AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_IsRxEmpty */
+/** \brief Test if the current transfer descriptor has been filled */
+/**---------------------------------------------------------------------------- */
+__inline int AT91F_PDC_IsRxEmpty( /* \return return 1 if transfer is complete */
+    AT91PS_PDC pPDC )             /* \arg pointer to a PDC controller */
 {
-    return !(pPDC->PDC_RCR);
+    return !( pPDC->PDC_RCR );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_IsNextRxEmpty
-//* \brief Test if the next transfer descriptor has been moved to the current td
-//*----------------------------------------------------------------------------
-__inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete
-    AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_IsNextRxEmpty */
+/** \brief Test if the next transfer descriptor has been moved to the current td */
+/**---------------------------------------------------------------------------- */
+__inline int AT91F_PDC_IsNextRxEmpty( /* \return return 1 if transfer is complete */
+    AT91PS_PDC pPDC )                 /* \arg pointer to a PDC controller */
 {
-    return !(pPDC->PDC_RNCR);
+    return !( pPDC->PDC_RNCR );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_Open
-//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_Open (
-    AT91PS_PDC pPDC)       // \arg pointer to a PDC controller
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_Open */
+/** \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_PDC_Open( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
 {
-    //* Disable the RX and TX PDC transfer requests
-    AT91F_PDC_DisableRx(pPDC);
-    AT91F_PDC_DisableTx(pPDC);
+    /** Disable the RX and TX PDC transfer requests */
+    AT91F_PDC_DisableRx( pPDC );
+    AT91F_PDC_DisableTx( pPDC );
 
-    //* Reset all Counter register Next buffer first
-    AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);
-    AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);
-    AT91F_PDC_SetTx(pPDC, (char *) 0, 0);
-    AT91F_PDC_SetRx(pPDC, (char *) 0, 0);
+    /** Reset all Counter register Next buffer first */
+    AT91F_PDC_SetNextTx( pPDC, ( char * ) 0, 0 );
+    AT91F_PDC_SetNextRx( pPDC, ( char * ) 0, 0 );
+    AT91F_PDC_SetTx( pPDC, ( char * ) 0, 0 );
+    AT91F_PDC_SetRx( pPDC, ( char * ) 0, 0 );
 
-    //* Enable the RX and TX PDC transfer requests
-    AT91F_PDC_EnableRx(pPDC);
-    AT91F_PDC_EnableTx(pPDC);
+    /** Enable the RX and TX PDC transfer requests */
+    AT91F_PDC_EnableRx( pPDC );
+    AT91F_PDC_EnableTx( pPDC );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_Close
-//* \brief Close PDC: disable TX and RX reset transfer descriptors
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_Close (
-    AT91PS_PDC pPDC)       // \arg pointer to a PDC controller
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_Close */
+/** \brief Close PDC: disable TX and RX reset transfer descriptors */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_PDC_Close( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
 {
-    //* Disable the RX and TX PDC transfer requests
-    AT91F_PDC_DisableRx(pPDC);
-    AT91F_PDC_DisableTx(pPDC);
-
-    //* Reset all Counter register Next buffer first
-    AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);
-    AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);
-    AT91F_PDC_SetTx(pPDC, (char *) 0, 0);
-    AT91F_PDC_SetRx(pPDC, (char *) 0, 0);
+    /** Disable the RX and TX PDC transfer requests */
+    AT91F_PDC_DisableRx( pPDC );
+    AT91F_PDC_DisableTx( pPDC );
 
+    /** Reset all Counter register Next buffer first */
+    AT91F_PDC_SetNextTx( pPDC, ( char * ) 0, 0 );
+    AT91F_PDC_SetNextRx( pPDC, ( char * ) 0, 0 );
+    AT91F_PDC_SetTx( pPDC, ( char * ) 0, 0 );
+    AT91F_PDC_SetRx( pPDC, ( char * ) 0, 0 );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_SendFrame
-//* \brief Close PDC: disable TX and RX reset transfer descriptors
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PDC_SendFrame(
-    AT91PS_PDC pPDC,
-    char *pBuffer,
-    unsigned int szBuffer,
-    char *pNextBuffer,
-    unsigned int szNextBuffer )
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_SendFrame */
+/** \brief Close PDC: disable TX and RX reset transfer descriptors */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_PDC_SendFrame( AT91PS_PDC pPDC,
+                                           char * pBuffer,
+                                           unsigned int szBuffer,
+                                           char * pNextBuffer,
+                                           unsigned int szNextBuffer )
 {
-    if (AT91F_PDC_IsTxEmpty(pPDC)) {
-        //* Buffer and next buffer can be initialized
-        AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer);
-        AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer);
+    if( AT91F_PDC_IsTxEmpty( pPDC ) )
+    {
+        /** Buffer and next buffer can be initialized */
+        AT91F_PDC_SetTx( pPDC, pBuffer, szBuffer );
+        AT91F_PDC_SetNextTx( pPDC, pNextBuffer, szNextBuffer );
         return 2;
     }
-    else if (AT91F_PDC_IsNextTxEmpty(pPDC)) {
-        //* Only one buffer can be initialized
-        AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer);
+    else if( AT91F_PDC_IsNextTxEmpty( pPDC ) )
+    {
+        /** Only one buffer can be initialized */
+        AT91F_PDC_SetNextTx( pPDC, pBuffer, szBuffer );
         return 1;
     }
-    else {
-        //* All buffer are in use...
+    else
+    {
+        /** All buffer are in use... */
         return 0;
     }
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_ReceiveFrame
-//* \brief Close PDC: disable TX and RX reset transfer descriptors
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PDC_ReceiveFrame (
-    AT91PS_PDC pPDC,
-    char *pBuffer,
-    unsigned int szBuffer,
-    char *pNextBuffer,
-    unsigned int szNextBuffer )
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_ReceiveFrame */
+/** \brief Close PDC: disable TX and RX reset transfer descriptors */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_PDC_ReceiveFrame( AT91PS_PDC pPDC,
+                                              char * pBuffer,
+                                              unsigned int szBuffer,
+                                              char * pNextBuffer,
+                                              unsigned int szNextBuffer )
 {
-    if (AT91F_PDC_IsRxEmpty(pPDC)) {
-        //* Buffer and next buffer can be initialized
-        AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer);
-        AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer);
+    if( AT91F_PDC_IsRxEmpty( pPDC ) )
+    {
+        /** Buffer and next buffer can be initialized */
+        AT91F_PDC_SetRx( pPDC, pBuffer, szBuffer );
+        AT91F_PDC_SetNextRx( pPDC, pNextBuffer, szNextBuffer );
         return 2;
     }
-    else if (AT91F_PDC_IsNextRxEmpty(pPDC)) {
-        //* Only one buffer can be initialized
-        AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer);
+    else if( AT91F_PDC_IsNextRxEmpty( pPDC ) )
+    {
+        /** Only one buffer can be initialized */
+        AT91F_PDC_SetNextRx( pPDC, pBuffer, szBuffer );
         return 1;
     }
-    else {
-        //* All buffer are in use...
+    else
+    {
+        /** All buffer are in use... */
         return 0;
     }
 }
+
 /* *****************************************************************************
-                SOFTWARE API FOR DBGU
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_DBGU_InterruptEnable
-//* \brief Enable DBGU Interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_DBGU_InterruptEnable(
-        AT91PS_DBGU pDbgu,   // \arg  pointer to a DBGU controller
-        unsigned int flag) // \arg  dbgu interrupt to be enabled
+*               SOFTWARE API FOR DBGU
+***************************************************************************** */
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_DBGU_InterruptEnable */
+/** \brief Enable DBGU Interrupt */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_DBGU_InterruptEnable( AT91PS_DBGU pDbgu,  /* \arg  pointer to a DBGU controller */
+                                          unsigned int flag ) /* \arg  dbgu interrupt to be enabled */
 {
-        pDbgu->DBGU_IER = flag;
+    pDbgu->DBGU_IER = flag;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_DBGU_InterruptDisable
-//* \brief Disable DBGU Interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_DBGU_InterruptDisable(
-        AT91PS_DBGU pDbgu,   // \arg  pointer to a DBGU controller
-        unsigned int flag) // \arg  dbgu interrupt to be disabled
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_DBGU_InterruptDisable */
+/** \brief Disable DBGU Interrupt */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_DBGU_InterruptDisable( AT91PS_DBGU pDbgu,  /* \arg  pointer to a DBGU controller */
+                                           unsigned int flag ) /* \arg  dbgu interrupt to be disabled */
 {
-        pDbgu->DBGU_IDR = flag;
+    pDbgu->DBGU_IDR = flag;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_DBGU_GetInterruptMaskStatus
-//* \brief Return DBGU Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status
-        AT91PS_DBGU pDbgu) // \arg  pointer to a DBGU controller
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_DBGU_GetInterruptMaskStatus */
+/** \brief Return DBGU Interrupt Mask Status */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( /* \return DBGU Interrupt Mask Status */
+    AT91PS_DBGU pDbgu )                                  /* \arg  pointer to a DBGU controller */
 {
-        return pDbgu->DBGU_IMR;
+    return pDbgu->DBGU_IMR;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_DBGU_IsInterruptMasked
-//* \brief Test if DBGU Interrupt is Masked
-//*----------------------------------------------------------------------------
-__inline int AT91F_DBGU_IsInterruptMasked(
-        AT91PS_DBGU pDbgu,   // \arg  pointer to a DBGU controller
-        unsigned int flag) // \arg  flag to be tested
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_DBGU_IsInterruptMasked */
+/** \brief Test if DBGU Interrupt is Masked */
+/**---------------------------------------------------------------------------- */
+__inline int AT91F_DBGU_IsInterruptMasked( AT91PS_DBGU pDbgu,  /* \arg  pointer to a DBGU controller */
+                                           unsigned int flag ) /* \arg  flag to be tested */
 {
-        return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag);
+    return( AT91F_DBGU_GetInterruptMaskStatus( pDbgu ) & flag );
 }
 
 /* *****************************************************************************
-                SOFTWARE API FOR SSC
-   ***************************************************************************** */
-//* Define the standard I2S mode configuration
+*               SOFTWARE API FOR SSC
+***************************************************************************** */
+/** Define the standard I2S mode configuration */
 
-//* Configuration to set in the SSC Transmit Clock Mode Register
-//* Parameters :  nb_bit_by_slot : 8, 16 or 32 bits
-//*               nb_slot_by_frame : number of channels
-#define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\
-                                       AT91C_SSC_CKS_DIV   +\
-                                       AT91C_SSC_CKO_CONTINOUS      +\
-                                       AT91C_SSC_CKG_NONE    +\
-                                       AT91C_SSC_START_FALL_RF +\
-                                       AT91C_SSC_STTOUT  +\
-                                       ((1<<16) & AT91C_SSC_STTDLY) +\
-                                       ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24))
+/** Configuration to set in the SSC Transmit Clock Mode Register */
+/** Parameters :  nb_bit_by_slot : 8, 16 or 32 bits */
+/**               nb_slot_by_frame : number of channels */
+#define AT91C_I2S_ASY_MASTER_TX_SETTING( nb_bit_by_slot, nb_slot_by_frame ) \
+    ( +                                                                     \
+      AT91C_SSC_CKS_DIV +                                                   \
+      AT91C_SSC_CKO_CONTINUOUS +                                            \
+      AT91C_SSC_CKG_NONE +                                                  \
+      AT91C_SSC_START_FALL_RF +                                             \
+      AT91C_SSC_STTOUT +                                                    \
+      ( ( 1 << 16 ) & AT91C_SSC_STTDLY ) +                                  \
+      ( ( ( ( nb_bit_by_slot * nb_slot_by_frame ) / 2 ) - 1 ) << 24 ) )
 
 
-//* Configuration to set in the SSC Transmit Frame Mode Register
-//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits
-//*              nb_slot_by_frame : number of channels
-#define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\
-                                    (nb_bit_by_slot-1)  +\
-                                    AT91C_SSC_MSBF   +\
-                                    (((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB)  +\
-                                    (((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\
-                                    AT91C_SSC_FSOS_NEGATIVE)
+/** Configuration to set in the SSC Transmit Frame Mode Register */
+/** Parameters : nb_bit_by_slot : 8, 16 or 32 bits */
+/**              nb_slot_by_frame : number of channels */
+#define AT91C_I2S_ASY_TX_FRAME_SETTING( nb_bit_by_slot, nb_slot_by_frame ) \
+    ( +                                                                    \
+      ( nb_bit_by_slot - 1 ) +                                             \
+      AT91C_SSC_MSBF +                                                     \
+      ( ( ( nb_slot_by_frame - 1 ) << 8 ) & AT91C_SSC_DATNB ) +            \
+      ( ( ( nb_bit_by_slot - 1 ) << 16 ) & AT91C_SSC_FSLEN ) +             \
+      AT91C_SSC_FSOS_NEGATIVE )
 
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_SetBaudrate
-//* \brief Set the baudrate according to the CPU clock
-//*----------------------------------------------------------------------------
-__inline void AT91F_SSC_SetBaudrate (
-        AT91PS_SSC pSSC,        // \arg pointer to a SSC controller
-        unsigned int mainClock, // \arg peripheral clock
-        unsigned int speed)     // \arg SSC baudrate
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_SSC_SetBaudrate */
+/** \brief Set the baudrate according to the CPU clock */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_SSC_SetBaudrate( AT91PS_SSC pSSC,        /* \arg pointer to a SSC controller */
+                                     unsigned int mainClock, /* \arg peripheral clock */
+                                     unsigned int speed )    /* \arg SSC baudrate */
 {
-        unsigned int baud_value;
-        //* Define the baud rate divisor register
-        if (speed == 0)
-           baud_value = 0;
+    unsigned int baud_value;
+
+    /** Define the baud rate divisor register */
+    if( speed == 0 )
+    {
+        baud_value = 0;
+    }
+    else
+    {
+        baud_value = ( unsigned int ) ( mainClock * 10 ) / ( 2 * speed );
+
+        if( ( baud_value % 10 ) >= 5 )
+        {
+            baud_value = ( baud_value / 10 ) + 1;
+        }
         else
         {
-           baud_value = (unsigned int) (mainClock * 10)/(2*speed);
-           if ((baud_value % 10) >= 5)
-                  baud_value = (baud_value / 10) + 1;
-           else
-                  baud_value /= 10;
+            baud_value /= 10;
         }
+    }
 
-        pSSC->SSC_CMR = baud_value;
+    pSSC->SSC_CMR = baud_value;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_Configure
-//* \brief Configure SSC
-//*----------------------------------------------------------------------------
-__inline void AT91F_SSC_Configure (
-             AT91PS_SSC pSSC,          // \arg pointer to a SSC controller
-             unsigned int syst_clock,  // \arg System Clock Frequency
-             unsigned int baud_rate,   // \arg Expected Baud Rate Frequency
-             unsigned int clock_rx,    // \arg Receiver Clock Parameters
-             unsigned int mode_rx,     // \arg mode Register to be programmed
-             unsigned int clock_tx,    // \arg Transmitter Clock Parameters
-             unsigned int mode_tx)     // \arg mode Register to be programmed
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_SSC_Configure */
+/** \brief Configure SSC */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_SSC_Configure( AT91PS_SSC pSSC,         /* \arg pointer to a SSC controller */
+                                   unsigned int syst_clock, /* \arg System Clock Frequency */
+                                   unsigned int baud_rate,  /* \arg Expected Baud Rate Frequency */
+                                   unsigned int clock_rx,   /* \arg Receiver Clock Parameters */
+                                   unsigned int mode_rx,    /* \arg mode Register to be programmed */
+                                   unsigned int clock_tx,   /* \arg Transmitter Clock Parameters */
+                                   unsigned int mode_tx )   /* \arg mode Register to be programmed */
 {
-    //* Disable interrupts
-    pSSC->SSC_IDR = (unsigned int) -1;
+    /** Disable interrupts */
+    pSSC->SSC_IDR = ( unsigned int ) -1;
 
-    //* Reset receiver and transmitter
-    pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS ;
+    /** Reset receiver and transmitter */
+    pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS;
 
-    //* Define the Clock Mode Register
-    AT91F_SSC_SetBaudrate(pSSC, syst_clock, baud_rate);
+    /** Define the Clock Mode Register */
+    AT91F_SSC_SetBaudrate( pSSC, syst_clock, baud_rate );
 
-     //* Write the Receive Clock Mode Register
-    pSSC->SSC_RCMR =  clock_rx;
+    /** Write the Receive Clock Mode Register */
+    pSSC->SSC_RCMR = clock_rx;
 
-     //* Write the Transmit Clock Mode Register
-    pSSC->SSC_TCMR =  clock_tx;
+    /** Write the Transmit Clock Mode Register */
+    pSSC->SSC_TCMR = clock_tx;
 
-     //* Write the Receive Frame Mode Register
-    pSSC->SSC_RFMR =  mode_rx;
-
-     //* Write the Transmit Frame Mode Register
-    pSSC->SSC_TFMR =  mode_tx;
-
-    //* Clear Transmit and Receive Counters
-    AT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR));
+    /** Write the Receive Frame Mode Register */
+    pSSC->SSC_RFMR = mode_rx;
 
+    /** Write the Transmit Frame Mode Register */
+    pSSC->SSC_TFMR = mode_tx;
 
+    /** Clear Transmit and Receive Counters */
+    AT91F_PDC_Open( ( AT91PS_PDC ) &( pSSC->SSC_RPR ) );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_EnableRx
-//* \brief Enable receiving datas
-//*----------------------------------------------------------------------------
-__inline void AT91F_SSC_EnableRx (
-    AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_SSC_EnableRx */
+/** \brief Enable receiving data */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_SSC_EnableRx( AT91PS_SSC pSSC ) /* \arg pointer to a SSC controller */
 {
-    //* Enable receiver
+    /** Enable receiver */
     pSSC->SSC_CR = AT91C_SSC_RXEN;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_DisableRx
-//* \brief Disable receiving datas
-//*----------------------------------------------------------------------------
-__inline void AT91F_SSC_DisableRx (
-    AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_SSC_DisableRx */
+/** \brief Disable receiving data */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_SSC_DisableRx( AT91PS_SSC pSSC ) /* \arg pointer to a SSC controller */
 {
-    //* Disable receiver
+    /** Disable receiver */
     pSSC->SSC_CR = AT91C_SSC_RXDIS;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_EnableTx
-//* \brief Enable sending datas
-//*----------------------------------------------------------------------------
-__inline void AT91F_SSC_EnableTx (
-    AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_SSC_EnableTx */
+/** \brief Enable sending data */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_SSC_EnableTx( AT91PS_SSC pSSC ) /* \arg pointer to a SSC controller */
 {
-    //* Enable  transmitter
+    /** Enable  transmitter */
     pSSC->SSC_CR = AT91C_SSC_TXEN;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_DisableTx
-//* \brief Disable sending datas
-//*----------------------------------------------------------------------------
-__inline void AT91F_SSC_DisableTx (
-    AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_SSC_DisableTx */
+/** \brief Disable sending data */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_SSC_DisableTx( AT91PS_SSC pSSC ) /* \arg pointer to a SSC controller */
 {
-    //* Disable  transmitter
+    /** Disable  transmitter */
     pSSC->SSC_CR = AT91C_SSC_TXDIS;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_EnableIt
-//* \brief Enable SSC IT
-//*----------------------------------------------------------------------------
-__inline void AT91F_SSC_EnableIt (
-    AT91PS_SSC pSSC, // \arg pointer to a SSC controller
-    unsigned int flag)   // \arg IT to be enabled
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_SSC_EnableIt */
+/** \brief Enable SSC IT */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_SSC_EnableIt( AT91PS_SSC pSSC,    /* \arg pointer to a SSC controller */
+                                  unsigned int flag ) /* \arg IT to be enabled */
 {
-    //* Write to the IER register
+    /** Write to the IER register */
     pSSC->SSC_IER = flag;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_DisableIt
-//* \brief Disable SSC IT
-//*----------------------------------------------------------------------------
-__inline void AT91F_SSC_DisableIt (
-    AT91PS_SSC pSSC, // \arg pointer to a SSC controller
-    unsigned int flag)   // \arg IT to be disabled
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_SSC_DisableIt */
+/** \brief Disable SSC IT */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_SSC_DisableIt( AT91PS_SSC pSSC,    /* \arg pointer to a SSC controller */
+                                   unsigned int flag ) /* \arg IT to be disabled */
 {
-    //* Write to the IDR register
+    /** Write to the IDR register */
     pSSC->SSC_IDR = flag;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_ReceiveFrame
-//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_SSC_ReceiveFrame (
-    AT91PS_SSC pSSC,
-    char *pBuffer,
-    unsigned int szBuffer,
-    char *pNextBuffer,
-    unsigned int szNextBuffer )
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_SSC_ReceiveFrame */
+/** \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_SSC_ReceiveFrame( AT91PS_SSC pSSC,
+                                              char * pBuffer,
+                                              unsigned int szBuffer,
+                                              char * pNextBuffer,
+                                              unsigned int szNextBuffer )
 {
     return AT91F_PDC_ReceiveFrame(
-        (AT91PS_PDC) &(pSSC->SSC_RPR),
+        ( AT91PS_PDC ) &( pSSC->SSC_RPR ),
         pBuffer,
         szBuffer,
         pNextBuffer,
-        szNextBuffer);
+        szNextBuffer );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_SendFrame
-//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_SSC_SendFrame(
-    AT91PS_SSC pSSC,
-    char *pBuffer,
-    unsigned int szBuffer,
-    char *pNextBuffer,
-    unsigned int szNextBuffer )
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_SSC_SendFrame */
+/** \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_SSC_SendFrame( AT91PS_SSC pSSC,
+                                           char * pBuffer,
+                                           unsigned int szBuffer,
+                                           char * pNextBuffer,
+                                           unsigned int szNextBuffer )
 {
     return AT91F_PDC_SendFrame(
-        (AT91PS_PDC) &(pSSC->SSC_RPR),
+        ( AT91PS_PDC ) &( pSSC->SSC_RPR ),
         pBuffer,
         szBuffer,
         pNextBuffer,
-        szNextBuffer);
+        szNextBuffer );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_GetInterruptMaskStatus
-//* \brief Return SSC Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_SSC_GetInterruptMaskStatus( // \return SSC Interrupt Mask Status
-        AT91PS_SSC pSsc) // \arg  pointer to a SSC controller
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_SSC_GetInterruptMaskStatus */
+/** \brief Return SSC Interrupt Mask Status */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_SSC_GetInterruptMaskStatus( /* \return SSC Interrupt Mask Status */
+    AT91PS_SSC pSsc )                                   /* \arg  pointer to a SSC controller */
 {
-        return pSsc->SSC_IMR;
+    return pSsc->SSC_IMR;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_IsInterruptMasked
-//* \brief Test if SSC Interrupt is Masked
-//*----------------------------------------------------------------------------
-__inline int AT91F_SSC_IsInterruptMasked(
-        AT91PS_SSC pSsc,   // \arg  pointer to a SSC controller
-        unsigned int flag) // \arg  flag to be tested
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_SSC_IsInterruptMasked */
+/** \brief Test if SSC Interrupt is Masked */
+/**---------------------------------------------------------------------------- */
+__inline int AT91F_SSC_IsInterruptMasked( AT91PS_SSC pSsc,    /* \arg  pointer to a SSC controller */
+                                          unsigned int flag ) /* \arg  flag to be tested */
 {
-        return (AT91F_SSC_GetInterruptMaskStatus(pSsc) & flag);
+    return( AT91F_SSC_GetInterruptMaskStatus( pSsc ) & flag );
 }
 
 /* *****************************************************************************
-                SOFTWARE API FOR SPI
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_Open
-//* \brief Open a SPI Port
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_SPI_Open (
-        const unsigned int null)  // \arg
+*               SOFTWARE API FOR SPI
+***************************************************************************** */
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_SPI_Open */
+/** \brief Open a SPI Port */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_SPI_Open( const unsigned int null ) /* \arg */
 {
-        /* NOT DEFINED AT THIS MOMENT */
-        return ( 0 );
+    /* NOT DEFINED AT THIS MOMENT */
+    return( 0 );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_CfgCs
-//* \brief Configure SPI chip select register
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_CfgCs (
-    AT91PS_SPI pSPI,     // pointer to a SPI controller
-    int cs,     // SPI cs number (0 to 3)
-    int val)   //  chip select register
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_SPI_CfgCs */
+/** \brief Configure SPI chip select register */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_SPI_CfgCs( AT91PS_SPI pSPI, /* pointer to a SPI controller */
+                               int cs,          /* SPI cs number (0 to 3) */
+                               int val )        /*  chip select register */
 {
-    //* Write to the CSR register
-    *(pSPI->SPI_CSR + cs) = val;
+    /** Write to the CSR register */
+    *( pSPI->SPI_CSR + cs ) = val;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_EnableIt
-//* \brief Enable SPI interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_EnableIt (
-    AT91PS_SPI pSPI,     // pointer to a SPI controller
-    unsigned int flag)   // IT to be enabled
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_SPI_EnableIt */
+/** \brief Enable SPI interrupt */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_SPI_EnableIt( AT91PS_SPI pSPI,    /* pointer to a SPI controller */
+                                  unsigned int flag ) /* IT to be enabled */
 {
-    //* Write to the IER register
+    /** Write to the IER register */
     pSPI->SPI_IER = flag;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_DisableIt
-//* \brief Disable SPI interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_DisableIt (
-    AT91PS_SPI pSPI, // pointer to a SPI controller
-    unsigned int flag) // IT to be disabled
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_SPI_DisableIt */
+/** \brief Disable SPI interrupt */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_SPI_DisableIt( AT91PS_SPI pSPI,    /* pointer to a SPI controller */
+                                   unsigned int flag ) /* IT to be disabled */
 {
-    //* Write to the IDR register
+    /** Write to the IDR register */
     pSPI->SPI_IDR = flag;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_Reset
-//* \brief Reset the SPI controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_Reset (
-    AT91PS_SPI pSPI // pointer to a SPI controller
-    )
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_SPI_Reset */
+/** \brief Reset the SPI controller */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_SPI_Reset( AT91PS_SPI pSPI /* pointer to a SPI controller */
+                               )
 {
-    //* Write to the CR register
+    /** Write to the CR register */
     pSPI->SPI_CR = AT91C_SPI_SWRST;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_Enable
-//* \brief Enable the SPI controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_Enable (
-    AT91PS_SPI pSPI // pointer to a SPI controller
-    )
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_SPI_Enable */
+/** \brief Enable the SPI controller */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_SPI_Enable( AT91PS_SPI pSPI /* pointer to a SPI controller */
+                                )
 {
-    //* Write to the CR register
+    /** Write to the CR register */
     pSPI->SPI_CR = AT91C_SPI_SPIEN;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_Disable
-//* \brief Disable the SPI controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_Disable (
-    AT91PS_SPI pSPI // pointer to a SPI controller
-    )
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_SPI_Disable */
+/** \brief Disable the SPI controller */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_SPI_Disable( AT91PS_SPI pSPI /* pointer to a SPI controller */
+                                 )
 {
-    //* Write to the CR register
+    /** Write to the CR register */
     pSPI->SPI_CR = AT91C_SPI_SPIDIS;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_CfgMode
-//* \brief Enable the SPI controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_CfgMode (
-    AT91PS_SPI pSPI, // pointer to a SPI controller
-    int mode)        // mode register
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_SPI_CfgMode */
+/** \brief Enable the SPI controller */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_SPI_CfgMode( AT91PS_SPI pSPI, /* pointer to a SPI controller */
+                                 int mode )       /* mode register */
 {
-    //* Write to the MR register
+    /** Write to the MR register */
     pSPI->SPI_MR = mode;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_CfgPCS
-//* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_CfgPCS (
-    AT91PS_SPI pSPI, // pointer to a SPI controller
-    char PCS_Device) // PCS of the Device
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_SPI_CfgPCS */
+/** \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_SPI_CfgPCS( AT91PS_SPI pSPI,  /* pointer to a SPI controller */
+                                char PCS_Device ) /* PCS of the Device */
 {
-    //* Write to the MR register
+    /** Write to the MR register */
     pSPI->SPI_MR &= 0xFFF0FFFF;
-    pSPI->SPI_MR |= ( (PCS_Device<<16) & AT91C_SPI_PCS );
+    pSPI->SPI_MR |= ( ( PCS_Device << 16 ) & AT91C_SPI_PCS );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_ReceiveFrame
-//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_SPI_ReceiveFrame (
-    AT91PS_SPI pSPI,
-    char *pBuffer,
-    unsigned int szBuffer,
-    char *pNextBuffer,
-    unsigned int szNextBuffer )
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_SPI_ReceiveFrame */
+/** \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_SPI_ReceiveFrame( AT91PS_SPI pSPI,
+                                              char * pBuffer,
+                                              unsigned int szBuffer,
+                                              char * pNextBuffer,
+                                              unsigned int szNextBuffer )
 {
     return AT91F_PDC_ReceiveFrame(
-        (AT91PS_PDC) &(pSPI->SPI_RPR),
+        ( AT91PS_PDC ) &( pSPI->SPI_RPR ),
         pBuffer,
         szBuffer,
         pNextBuffer,
-        szNextBuffer);
+        szNextBuffer );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_SendFrame
-//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_SPI_SendFrame(
-    AT91PS_SPI pSPI,
-    char *pBuffer,
-    unsigned int szBuffer,
-    char *pNextBuffer,
-    unsigned int szNextBuffer )
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_SPI_SendFrame */
+/** \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is bSPIy */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_SPI_SendFrame( AT91PS_SPI pSPI,
+                                           char * pBuffer,
+                                           unsigned int szBuffer,
+                                           char * pNextBuffer,
+                                           unsigned int szNextBuffer )
 {
     return AT91F_PDC_SendFrame(
-        (AT91PS_PDC) &(pSPI->SPI_RPR),
+        ( AT91PS_PDC ) &( pSPI->SPI_RPR ),
         pBuffer,
         szBuffer,
         pNextBuffer,
-        szNextBuffer);
+        szNextBuffer );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_Close
-//* \brief Close SPI: disable IT disable transfert, close PDC
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_Close (
-    AT91PS_SPI pSPI)     // \arg pointer to a SPI controller
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_SPI_Close */
+/** \brief Close SPI: disable IT disable transfert, close PDC */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_SPI_Close( AT91PS_SPI pSPI ) /* \arg pointer to a SPI controller */
 {
-    //* Reset all the Chip Select register
-    pSPI->SPI_CSR[0] = 0 ;
-    pSPI->SPI_CSR[1] = 0 ;
-    pSPI->SPI_CSR[2] = 0 ;
-    pSPI->SPI_CSR[3] = 0 ;
+    /** Reset all the Chip Select register */
+    pSPI->SPI_CSR[ 0 ] = 0;
+    pSPI->SPI_CSR[ 1 ] = 0;
+    pSPI->SPI_CSR[ 2 ] = 0;
+    pSPI->SPI_CSR[ 3 ] = 0;
 
-    //* Reset the SPI mode
-    pSPI->SPI_MR = 0  ;
+    /** Reset the SPI mode */
+    pSPI->SPI_MR = 0;
 
-    //* Disable all interrupts
-    pSPI->SPI_IDR = 0xFFFFFFFF ;
+    /** Disable all interrupts */
+    pSPI->SPI_IDR = 0xFFFFFFFF;
 
-    //* Abort the Peripheral Data Transfers
-    AT91F_PDC_Close((AT91PS_PDC) &(pSPI->SPI_RPR));
+    /** Abort the Peripheral Data Transfers */
+    AT91F_PDC_Close( ( AT91PS_PDC ) &( pSPI->SPI_RPR ) );
 
-    //* Disable receiver and transmitter and stop any activity immediately
+    /** Disable receiver and transmitter and stop any activity immediately */
     pSPI->SPI_CR = AT91C_SPI_SPIDIS;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_PutChar
-//* \brief Send a character,does not check if ready to send
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_PutChar (
-    AT91PS_SPI pSPI,
-    unsigned int character,
-             unsigned int cs_number )
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_SPI_PutChar */
+/** \brief Send a character,does not check if ready to send */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_SPI_PutChar( AT91PS_SPI pSPI,
+                                 unsigned int character,
+                                 unsigned int cs_number )
 {
     unsigned int value_for_cs;
-    value_for_cs = (~(1 << cs_number)) & 0xF;  //Place a zero among a 4 ONEs number
-    pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16);
+
+    value_for_cs = ( ~( 1 << cs_number ) ) & 0xF; /*Place a zero among a 4 ONEs number */
+    pSPI->SPI_TDR = ( character & 0xFFFF ) | ( value_for_cs << 16 );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_GetChar
-//* \brief Receive a character,does not check if a character is available
-//*----------------------------------------------------------------------------
-__inline int AT91F_SPI_GetChar (
-    const AT91PS_SPI pSPI)
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_SPI_GetChar */
+/** \brief Receive a character,does not check if a character is available */
+/**---------------------------------------------------------------------------- */
+__inline int AT91F_SPI_GetChar( const AT91PS_SPI pSPI )
 {
-    return((pSPI->SPI_RDR) & 0xFFFF);
+    return( ( pSPI->SPI_RDR ) & 0xFFFF );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_GetInterruptMaskStatus
-//* \brief Return SPI Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_SPI_GetInterruptMaskStatus( // \return SPI Interrupt Mask Status
-        AT91PS_SPI pSpi) // \arg  pointer to a SPI controller
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_SPI_GetInterruptMaskStatus */
+/** \brief Return SPI Interrupt Mask Status */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_SPI_GetInterruptMaskStatus( /* \return SPI Interrupt Mask Status */
+    AT91PS_SPI pSpi )                                   /* \arg  pointer to a SPI controller */
 {
-        return pSpi->SPI_IMR;
+    return pSpi->SPI_IMR;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_IsInterruptMasked
-//* \brief Test if SPI Interrupt is Masked
-//*----------------------------------------------------------------------------
-__inline int AT91F_SPI_IsInterruptMasked(
-        AT91PS_SPI pSpi,   // \arg  pointer to a SPI controller
-        unsigned int flag) // \arg  flag to be tested
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_SPI_IsInterruptMasked */
+/** \brief Test if SPI Interrupt is Masked */
+/**---------------------------------------------------------------------------- */
+__inline int AT91F_SPI_IsInterruptMasked( AT91PS_SPI pSpi,    /* \arg  pointer to a SPI controller */
+                                          unsigned int flag ) /* \arg  flag to be tested */
 {
-        return (AT91F_SPI_GetInterruptMaskStatus(pSpi) & flag);
+    return( AT91F_SPI_GetInterruptMaskStatus( pSpi ) & flag );
 }
 
 /* *****************************************************************************
-                SOFTWARE API FOR PWMC
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWM_GetStatus
-//* \brief Return PWM Interrupt Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PWMC_GetStatus( // \return PWM Interrupt Status
-    AT91PS_PWMC pPWM) // pointer to a PWM controller
+*               SOFTWARE API FOR PWMC
+***************************************************************************** */
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PWM_GetStatus */
+/** \brief Return PWM Interrupt Status */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_PWMC_GetStatus( /* \return PWM Interrupt Status */
+    AT91PS_PWMC pPWM )                      /* pointer to a PWM controller */
 {
     return pPWM->PWMC_SR;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWM_InterruptEnable
-//* \brief Enable PWM Interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_InterruptEnable(
-        AT91PS_PWMC pPwm,   // \arg  pointer to a PWM controller
-        unsigned int flag) // \arg  PWM interrupt to be enabled
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PWM_InterruptEnable */
+/** \brief Enable PWM Interrupt */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_PWMC_InterruptEnable( AT91PS_PWMC pPwm,   /* \arg  pointer to a PWM controller */
+                                          unsigned int flag ) /* \arg  PWM interrupt to be enabled */
 {
-        pPwm->PWMC_IER = flag;
+    pPwm->PWMC_IER = flag;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWM_InterruptDisable
-//* \brief Disable PWM Interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_InterruptDisable(
-        AT91PS_PWMC pPwm,   // \arg  pointer to a PWM controller
-        unsigned int flag) // \arg  PWM interrupt to be disabled
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PWM_InterruptDisable */
+/** \brief Disable PWM Interrupt */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_PWMC_InterruptDisable( AT91PS_PWMC pPwm,   /* \arg  pointer to a PWM controller */
+                                           unsigned int flag ) /* \arg  PWM interrupt to be disabled */
 {
-        pPwm->PWMC_IDR = flag;
+    pPwm->PWMC_IDR = flag;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWM_GetInterruptMaskStatus
-//* \brief Return PWM Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PWMC_GetInterruptMaskStatus( // \return PWM Interrupt Mask Status
-        AT91PS_PWMC pPwm) // \arg  pointer to a PWM controller
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PWM_GetInterruptMaskStatus */
+/** \brief Return PWM Interrupt Mask Status */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_PWMC_GetInterruptMaskStatus( /* \return PWM Interrupt Mask Status */
+    AT91PS_PWMC pPwm )                                   /* \arg  pointer to a PWM controller */
 {
-        return pPwm->PWMC_IMR;
+    return pPwm->PWMC_IMR;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWM_IsInterruptMasked
-//* \brief Test if PWM Interrupt is Masked
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PWMC_IsInterruptMasked(
-        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
-        unsigned int flag) // \arg  flag to be tested
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PWM_IsInterruptMasked */
+/** \brief Test if PWM Interrupt is Masked */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_PWMC_IsInterruptMasked( AT91PS_PWMC pPWM,   /* \arg  pointer to a PWM controller */
+                                                    unsigned int flag ) /* \arg  flag to be tested */
 {
-    return (AT91F_PWMC_GetInterruptMaskStatus(pPWM) & flag);
+    return( AT91F_PWMC_GetInterruptMaskStatus( pPWM ) & flag );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWM_IsStatusSet
-//* \brief Test if PWM Interrupt is Set
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PWMC_IsStatusSet(
-        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
-        unsigned int flag) // \arg  flag to be tested
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PWM_IsStatusSet */
+/** \brief Test if PWM Interrupt is Set */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_PWMC_IsStatusSet( AT91PS_PWMC pPWM,   /* \arg  pointer to a PWM controller */
+                                              unsigned int flag ) /* \arg  flag to be tested */
 {
-    return (AT91F_PWMC_GetStatus(pPWM) & flag);
+    return( AT91F_PWMC_GetStatus( pPWM ) & flag );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWM_CfgChannel
-//* \brief Test if PWM Interrupt is Set
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_CfgChannel(
-        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
-        unsigned int channelId, // \arg PWM channel ID
-        unsigned int mode, // \arg  PWM mode
-        unsigned int period, // \arg PWM period
-        unsigned int duty) // \arg PWM duty cycle
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PWM_CfgChannel */
+/** \brief Test if PWM Interrupt is Set */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_PWMC_CfgChannel( AT91PS_PWMC pPWM,       /* \arg  pointer to a PWM controller */
+                                     unsigned int channelId, /* \arg PWM channel ID */
+                                     unsigned int mode,      /* \arg  PWM mode */
+                                     unsigned int period,    /* \arg PWM period */
+                                     unsigned int duty )     /* \arg PWM duty cycle */
 {
-    pPWM->PWMC_CH[channelId].PWMC_CMR = mode;
-    pPWM->PWMC_CH[channelId].PWMC_CDTYR = duty;
-    pPWM->PWMC_CH[channelId].PWMC_CPRDR = period;
+    pPWM->PWMC_CH[ channelId ].PWMC_CMR = mode;
+    pPWM->PWMC_CH[ channelId ].PWMC_CDTYR = duty;
+    pPWM->PWMC_CH[ channelId ].PWMC_CPRDR = period;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWM_StartChannel
-//* \brief Enable channel
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_StartChannel(
-        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
-        unsigned int flag) // \arg  Channels IDs to be enabled
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PWM_StartChannel */
+/** \brief Enable channel */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_PWMC_StartChannel( AT91PS_PWMC pPWM,   /* \arg  pointer to a PWM controller */
+                                       unsigned int flag ) /* \arg  Channels IDs to be enabled */
 {
     pPWM->PWMC_ENA = flag;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWM_StopChannel
-//* \brief Disable channel
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_StopChannel(
-        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
-        unsigned int flag) // \arg  Channels IDs to be enabled
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PWM_StopChannel */
+/** \brief Disable channel */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_PWMC_StopChannel( AT91PS_PWMC pPWM,   /* \arg  pointer to a PWM controller */
+                                      unsigned int flag ) /* \arg  Channels IDs to be enabled */
 {
     pPWM->PWMC_DIS = flag;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWM_UpdateChannel
-//* \brief Update Period or Duty Cycle
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_UpdateChannel(
-        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
-        unsigned int channelId, // \arg PWM channel ID
-        unsigned int update) // \arg  Channels IDs to be enabled
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PWM_UpdateChannel */
+/** \brief Update Period or Duty Cycle */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_PWMC_UpdateChannel( AT91PS_PWMC pPWM,       /* \arg  pointer to a PWM controller */
+                                        unsigned int channelId, /* \arg PWM channel ID */
+                                        unsigned int update )   /* \arg  Channels IDs to be enabled */
 {
-    pPWM->PWMC_CH[channelId].PWMC_CUPDR = update;
+    pPWM->PWMC_CH[ channelId ].PWMC_CUPDR = update;
 }
 
 /* *****************************************************************************
-                SOFTWARE API FOR TC
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TC_InterruptEnable
-//* \brief Enable TC Interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_TC_InterruptEnable(
-        AT91PS_TC pTc,   // \arg  pointer to a TC controller
-        unsigned int flag) // \arg  TC interrupt to be enabled
+*               SOFTWARE API FOR TC
+***************************************************************************** */
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_TC_InterruptEnable */
+/** \brief Enable TC Interrupt */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_TC_InterruptEnable( AT91PS_TC pTc,      /* \arg  pointer to a TC controller */
+                                        unsigned int flag ) /* \arg  TC interrupt to be enabled */
 {
-        pTc->TC_IER = flag;
+    pTc->TC_IER = flag;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TC_InterruptDisable
-//* \brief Disable TC Interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_TC_InterruptDisable(
-        AT91PS_TC pTc,   // \arg  pointer to a TC controller
-        unsigned int flag) // \arg  TC interrupt to be disabled
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_TC_InterruptDisable */
+/** \brief Disable TC Interrupt */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_TC_InterruptDisable( AT91PS_TC pTc,      /* \arg  pointer to a TC controller */
+                                         unsigned int flag ) /* \arg  TC interrupt to be disabled */
 {
-        pTc->TC_IDR = flag;
+    pTc->TC_IDR = flag;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TC_GetInterruptMaskStatus
-//* \brief Return TC Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_TC_GetInterruptMaskStatus( // \return TC Interrupt Mask Status
-        AT91PS_TC pTc) // \arg  pointer to a TC controller
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_TC_GetInterruptMaskStatus */
+/** \brief Return TC Interrupt Mask Status */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_TC_GetInterruptMaskStatus( /* \return TC Interrupt Mask Status */
+    AT91PS_TC pTc )                                    /* \arg  pointer to a TC controller */
 {
-        return pTc->TC_IMR;
+    return pTc->TC_IMR;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TC_IsInterruptMasked
-//* \brief Test if TC Interrupt is Masked
-//*----------------------------------------------------------------------------
-__inline int AT91F_TC_IsInterruptMasked(
-        AT91PS_TC pTc,   // \arg  pointer to a TC controller
-        unsigned int flag) // \arg  flag to be tested
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_TC_IsInterruptMasked */
+/** \brief Test if TC Interrupt is Masked */
+/**---------------------------------------------------------------------------- */
+__inline int AT91F_TC_IsInterruptMasked( AT91PS_TC pTc,      /* \arg  pointer to a TC controller */
+                                         unsigned int flag ) /* \arg  flag to be tested */
 {
-        return (AT91F_TC_GetInterruptMaskStatus(pTc) & flag);
+    return( AT91F_TC_GetInterruptMaskStatus( pTc ) & flag );
 }
 
 /* *****************************************************************************
-                SOFTWARE API FOR PMC
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_CfgSysClkEnableReg
-//* \brief Configure the System Clock Enable Register of the PMC controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_CfgSysClkEnableReg (
-    AT91PS_PMC pPMC, // \arg pointer to PMC controller
-    unsigned int mode)
+*               SOFTWARE API FOR PMC
+***************************************************************************** */
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_CfgSysClkEnableReg */
+/** \brief Configure the System Clock Enable Register of the PMC controller */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_PMC_CfgSysClkEnableReg( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */
+                                            unsigned int mode )
 {
-    //* Write to the SCER register
+    /** Write to the SCER register */
     pPMC->PMC_SCER = mode;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_CfgSysClkDisableReg
-//* \brief Configure the System Clock Disable Register of the PMC controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_CfgSysClkDisableReg (
-    AT91PS_PMC pPMC, // \arg pointer to PMC controller
-    unsigned int mode)
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_CfgSysClkDisableReg */
+/** \brief Configure the System Clock Disable Register of the PMC controller */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_PMC_CfgSysClkDisableReg( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */
+                                             unsigned int mode )
 {
-    //* Write to the SCDR register
+    /** Write to the SCDR register */
     pPMC->PMC_SCDR = mode;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_GetSysClkStatusReg
-//* \brief Return the System Clock Status Register of the PMC controller
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_GetSysClkStatusReg (
-    AT91PS_PMC pPMC // pointer to a CAN controller
-    )
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_GetSysClkStatusReg */
+/** \brief Return the System Clock Status Register of the PMC controller */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_PMC_GetSysClkStatusReg( AT91PS_PMC pPMC /* pointer to a CAN controller */
+                                                    )
 {
     return pPMC->PMC_SCSR;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_EnablePeriphClock
-//* \brief Enable peripheral clock
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_EnablePeriphClock (
-    AT91PS_PMC pPMC, // \arg pointer to PMC controller
-    unsigned int periphIds)  // \arg IDs of peripherals to enable
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_EnablePeriphClock */
+/** \brief Enable peripheral clock */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_PMC_EnablePeriphClock( AT91PS_PMC pPMC,         /* \arg pointer to PMC controller */
+                                           unsigned int periphIds ) /* \arg IDs of peripherals to enable */
 {
     pPMC->PMC_PCER = periphIds;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_DisablePeriphClock
-//* \brief Disable peripheral clock
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_DisablePeriphClock (
-    AT91PS_PMC pPMC, // \arg pointer to PMC controller
-    unsigned int periphIds)  // \arg IDs of peripherals to enable
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_DisablePeriphClock */
+/** \brief Disable peripheral clock */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_PMC_DisablePeriphClock( AT91PS_PMC pPMC,         /* \arg pointer to PMC controller */
+                                            unsigned int periphIds ) /* \arg IDs of peripherals to enable */
 {
     pPMC->PMC_PCDR = periphIds;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_GetPeriphClock
-//* \brief Get peripheral clock status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_GetPeriphClock (
-    AT91PS_PMC pPMC) // \arg pointer to PMC controller
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_GetPeriphClock */
+/** \brief Get peripheral clock status */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_PMC_GetPeriphClock( AT91PS_PMC pPMC ) /* \arg pointer to PMC controller */
 {
     return pPMC->PMC_PCSR;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CKGR_CfgMainOscillatorReg
-//* \brief Cfg the main oscillator
-//*----------------------------------------------------------------------------
-__inline void AT91F_CKGR_CfgMainOscillatorReg (
-    AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
-    unsigned int mode)
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_CKGR_CfgMainOscillatorReg */
+/** \brief Cfg the main oscillator */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_CKGR_CfgMainOscillatorReg( AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */
+                                               unsigned int mode )
 {
     pCKGR->CKGR_MOR = mode;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CKGR_GetMainOscillatorReg
-//* \brief Cfg the main oscillator
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CKGR_GetMainOscillatorReg (
-    AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_CKGR_GetMainOscillatorReg */
+/** \brief Cfg the main oscillator */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_CKGR_GetMainOscillatorReg( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */
 {
     return pCKGR->CKGR_MOR;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CKGR_EnableMainOscillator
-//* \brief Enable the main oscillator
-//*----------------------------------------------------------------------------
-__inline void AT91F_CKGR_EnableMainOscillator(
-    AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_CKGR_EnableMainOscillator */
+/** \brief Enable the main oscillator */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_CKGR_EnableMainOscillator( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */
 {
     pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CKGR_DisableMainOscillator
-//* \brief Disable the main oscillator
-//*----------------------------------------------------------------------------
-__inline void AT91F_CKGR_DisableMainOscillator (
-    AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_CKGR_DisableMainOscillator */
+/** \brief Disable the main oscillator */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_CKGR_DisableMainOscillator( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */
 {
     pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CKGR_CfgMainOscStartUpTime
-//* \brief Cfg MOR Register according to the main osc startup time
-//*----------------------------------------------------------------------------
-__inline void AT91F_CKGR_CfgMainOscStartUpTime (
-    AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
-    unsigned int startup_time,  // \arg main osc startup time in microsecond (us)
-    unsigned int slowClock)  // \arg slowClock in Hz
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_CKGR_CfgMainOscStartUpTime */
+/** \brief Cfg MOR Register according to the main osc startup time */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_CKGR_CfgMainOscStartUpTime( AT91PS_CKGR pCKGR,         /* \arg pointer to CKGR controller */
+                                                unsigned int startup_time, /* \arg main osc startup time in microsecond (us) */
+                                                unsigned int slowClock )   /* \arg slowClock in Hz */
 {
     pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT;
-    pCKGR->CKGR_MOR |= ((slowClock * startup_time)/(8*1000000)) << 8;
+    pCKGR->CKGR_MOR |= ( ( slowClock * startup_time ) / ( 8 * 1000000 ) ) << 8;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CKGR_GetMainClockFreqReg
-//* \brief Cfg the main oscillator
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CKGR_GetMainClockFreqReg (
-    AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_CKGR_GetMainClockFreqReg */
+/** \brief Cfg the main oscillator */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_CKGR_GetMainClockFreqReg( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */
 {
     return pCKGR->CKGR_MCFR;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CKGR_GetMainClock
-//* \brief Return Main clock in Hz
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CKGR_GetMainClock (
-    AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
-    unsigned int slowClock)  // \arg slowClock in Hz
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_CKGR_GetMainClock */
+/** \brief Return Main clock in Hz */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_CKGR_GetMainClock( AT91PS_CKGR pCKGR,       /* \arg pointer to CKGR controller */
+                                               unsigned int slowClock ) /* \arg slowClock in Hz */
 {
-    return ((pCKGR->CKGR_MCFR  & AT91C_CKGR_MAINF) * slowClock) >> 4;
+    return ( ( pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF ) * slowClock ) >> 4;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_CfgMCKReg
-//* \brief Cfg Master Clock Register
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_CfgMCKReg (
-    AT91PS_PMC pPMC, // \arg pointer to PMC controller
-    unsigned int mode)
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_CfgMCKReg */
+/** \brief Cfg Master Clock Register */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_PMC_CfgMCKReg( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */
+                                   unsigned int mode )
 {
     pPMC->PMC_MCKR = mode;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_GetMCKReg
-//* \brief Return Master Clock Register
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_GetMCKReg(
-    AT91PS_PMC pPMC) // \arg pointer to PMC controller
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_GetMCKReg */
+/** \brief Return Master Clock Register */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_PMC_GetMCKReg( AT91PS_PMC pPMC ) /* \arg pointer to PMC controller */
 {
     return pPMC->PMC_MCKR;
 }
 
-//*------------------------------------------------------------------------------
-//* \fn    AT91F_PMC_GetMasterClock
-//* \brief Return master clock in Hz which correponds to processor clock for ARM7
-//*------------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_GetMasterClock (
-    AT91PS_PMC pPMC, // \arg pointer to PMC controller
-    AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
-    unsigned int slowClock)  // \arg slowClock in Hz
+/**------------------------------------------------------------------------------ */
+/** \fn    AT91F_PMC_GetMasterClock */
+/** \brief Return master clock in Hz which corresponds to processor clock for ARM7 */
+/**------------------------------------------------------------------------------ */
+__inline unsigned int AT91F_PMC_GetMasterClock( AT91PS_PMC pPMC,         /* \arg pointer to PMC controller */
+                                                AT91PS_CKGR pCKGR,       /* \arg pointer to CKGR controller */
+                                                unsigned int slowClock ) /* \arg slowClock in Hz */
 {
     unsigned int reg = pPMC->PMC_MCKR;
-    unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2));
+    unsigned int prescaler = ( 1 << ( ( reg & AT91C_PMC_PRES ) >> 2 ) );
     unsigned int pllDivider, pllMultiplier;
 
-    switch (reg & AT91C_PMC_CSS) {
-        case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected
+    switch( reg & AT91C_PMC_CSS )
+    {
+        case AT91C_PMC_CSS_SLOW_CLK: /* Slow clock selected */
             return slowClock / prescaler;
-        case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected
-            return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler;
-        case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected
+
+        case AT91C_PMC_CSS_MAIN_CLK: /* Main clock is selected */
+            return AT91F_CKGR_GetMainClock( pCKGR, slowClock ) / prescaler;
+
+        case AT91C_PMC_CSS_PLL_CLK: /* PLLB clock is selected */
             reg = pCKGR->CKGR_PLLR;
-            pllDivider    = (reg  & AT91C_CKGR_DIV);
-            pllMultiplier = ((reg  & AT91C_CKGR_MUL) >> 16) + 1;
-            return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler;
+            pllDivider = ( reg & AT91C_CKGR_DIV );
+            pllMultiplier = ( ( reg & AT91C_CKGR_MUL ) >> 16 ) + 1;
+            return AT91F_CKGR_GetMainClock( pCKGR, slowClock ) / pllDivider * pllMultiplier / prescaler;
     }
+
     return 0;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_EnablePCK
-//* \brief Enable peripheral clock
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_EnablePCK (
-    AT91PS_PMC pPMC, // \arg pointer to PMC controller
-    unsigned int pck,  // \arg Peripheral clock identifier 0 .. 7
-    unsigned int mode)
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_EnablePCK */
+/** \brief Enable peripheral clock */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_PMC_EnablePCK( AT91PS_PMC pPMC,  /* \arg pointer to PMC controller */
+                                   unsigned int pck, /* \arg Peripheral clock identifier 0 .. 7 */
+                                   unsigned int mode )
 {
-    pPMC->PMC_PCKR[pck] = mode;
-    pPMC->PMC_SCER = (1 << pck) << 8;
+    pPMC->PMC_PCKR[ pck ] = mode;
+    pPMC->PMC_SCER = ( 1 << pck ) << 8;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_DisablePCK
-//* \brief Enable peripheral clock
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_DisablePCK (
-    AT91PS_PMC pPMC, // \arg pointer to PMC controller
-    unsigned int pck)  // \arg Peripheral clock identifier 0 .. 7
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_DisablePCK */
+/** \brief Enable peripheral clock */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_PMC_DisablePCK( AT91PS_PMC pPMC,   /* \arg pointer to PMC controller */
+                                    unsigned int pck ) /* \arg Peripheral clock identifier 0 .. 7 */
 {
-    pPMC->PMC_SCDR = (1 << pck) << 8;
+    pPMC->PMC_SCDR = ( 1 << pck ) << 8;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_EnableIt
-//* \brief Enable PMC interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_EnableIt (
-    AT91PS_PMC pPMC,     // pointer to a PMC controller
-    unsigned int flag)   // IT to be enabled
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_EnableIt */
+/** \brief Enable PMC interrupt */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_PMC_EnableIt( AT91PS_PMC pPMC,    /* pointer to a PMC controller */
+                                  unsigned int flag ) /* IT to be enabled */
 {
-    //* Write to the IER register
+    /** Write to the IER register */
     pPMC->PMC_IER = flag;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_DisableIt
-//* \brief Disable PMC interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_DisableIt (
-    AT91PS_PMC pPMC, // pointer to a PMC controller
-    unsigned int flag) // IT to be disabled
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_DisableIt */
+/** \brief Disable PMC interrupt */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_PMC_DisableIt( AT91PS_PMC pPMC,    /* pointer to a PMC controller */
+                                   unsigned int flag ) /* IT to be disabled */
 {
-    //* Write to the IDR register
+    /** Write to the IDR register */
     pPMC->PMC_IDR = flag;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_GetStatus
-//* \brief Return PMC Interrupt Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_GetStatus( // \return PMC Interrupt Status
-    AT91PS_PMC pPMC) // pointer to a PMC controller
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_GetStatus */
+/** \brief Return PMC Interrupt Status */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_PMC_GetStatus( /* \return PMC Interrupt Status */
+    AT91PS_PMC pPMC )                      /* pointer to a PMC controller */
 {
     return pPMC->PMC_SR;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_GetInterruptMaskStatus
-//* \brief Return PMC Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status
-    AT91PS_PMC pPMC) // pointer to a PMC controller
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_GetInterruptMaskStatus */
+/** \brief Return PMC Interrupt Mask Status */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_PMC_GetInterruptMaskStatus( /* \return PMC Interrupt Mask Status */
+    AT91PS_PMC pPMC )                                   /* pointer to a PMC controller */
 {
     return pPMC->PMC_IMR;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_IsInterruptMasked
-//* \brief Test if PMC Interrupt is Masked
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_IsInterruptMasked(
-        AT91PS_PMC pPMC,   // \arg  pointer to a PMC controller
-        unsigned int flag) // \arg  flag to be tested
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_IsInterruptMasked */
+/** \brief Test if PMC Interrupt is Masked */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_PMC_IsInterruptMasked( AT91PS_PMC pPMC,    /* \arg  pointer to a PMC controller */
+                                                   unsigned int flag ) /* \arg  flag to be tested */
 {
-    return (AT91F_PMC_GetInterruptMaskStatus(pPMC) & flag);
+    return( AT91F_PMC_GetInterruptMaskStatus( pPMC ) & flag );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_IsStatusSet
-//* \brief Test if PMC Status is Set
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_IsStatusSet(
-        AT91PS_PMC pPMC,   // \arg  pointer to a PMC controller
-        unsigned int flag) // \arg  flag to be tested
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_IsStatusSet */
+/** \brief Test if PMC Status is Set */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_PMC_IsStatusSet( AT91PS_PMC pPMC,    /* \arg  pointer to a PMC controller */
+                                             unsigned int flag ) /* \arg  flag to be tested */
 {
-    return (AT91F_PMC_GetStatus(pPMC) & flag);
-}/* *****************************************************************************
-                SOFTWARE API FOR ADC
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_EnableIt
-//* \brief Enable ADC interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_ADC_EnableIt (
-    AT91PS_ADC pADC,     // pointer to a ADC controller
-    unsigned int flag)   // IT to be enabled
+    return( AT91F_PMC_GetStatus( pPMC ) & flag );
+} /* *****************************************************************************
+  *              SOFTWARE API FOR ADC
+  ***************************************************************************** */
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_ADC_EnableIt */
+/** \brief Enable ADC interrupt */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_ADC_EnableIt( AT91PS_ADC pADC,    /* pointer to a ADC controller */
+                                  unsigned int flag ) /* IT to be enabled */
 {
-    //* Write to the IER register
+    /** Write to the IER register */
     pADC->ADC_IER = flag;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_DisableIt
-//* \brief Disable ADC interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_ADC_DisableIt (
-    AT91PS_ADC pADC, // pointer to a ADC controller
-    unsigned int flag) // IT to be disabled
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_ADC_DisableIt */
+/** \brief Disable ADC interrupt */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_ADC_DisableIt( AT91PS_ADC pADC,    /* pointer to a ADC controller */
+                                   unsigned int flag ) /* IT to be disabled */
 {
-    //* Write to the IDR register
+    /** Write to the IDR register */
     pADC->ADC_IDR = flag;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetStatus
-//* \brief Return ADC Interrupt Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetStatus( // \return ADC Interrupt Status
-    AT91PS_ADC pADC) // pointer to a ADC controller
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_ADC_GetStatus */
+/** \brief Return ADC Interrupt Status */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_ADC_GetStatus( /* \return ADC Interrupt Status */
+    AT91PS_ADC pADC )                      /* pointer to a ADC controller */
 {
     return pADC->ADC_SR;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetInterruptMaskStatus
-//* \brief Return ADC Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetInterruptMaskStatus( // \return ADC Interrupt Mask Status
-    AT91PS_ADC pADC) // pointer to a ADC controller
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_ADC_GetInterruptMaskStatus */
+/** \brief Return ADC Interrupt Mask Status */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_ADC_GetInterruptMaskStatus( /* \return ADC Interrupt Mask Status */
+    AT91PS_ADC pADC )                                   /* pointer to a ADC controller */
 {
     return pADC->ADC_IMR;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_IsInterruptMasked
-//* \brief Test if ADC Interrupt is Masked
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_IsInterruptMasked(
-        AT91PS_ADC pADC,   // \arg  pointer to a ADC controller
-        unsigned int flag) // \arg  flag to be tested
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_ADC_IsInterruptMasked */
+/** \brief Test if ADC Interrupt is Masked */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_ADC_IsInterruptMasked( AT91PS_ADC pADC,    /* \arg  pointer to a ADC controller */
+                                                   unsigned int flag ) /* \arg  flag to be tested */
 {
-    return (AT91F_ADC_GetInterruptMaskStatus(pADC) & flag);
+    return( AT91F_ADC_GetInterruptMaskStatus( pADC ) & flag );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_IsStatusSet
-//* \brief Test if ADC Status is Set
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_IsStatusSet(
-        AT91PS_ADC pADC,   // \arg  pointer to a ADC controller
-        unsigned int flag) // \arg  flag to be tested
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_ADC_IsStatusSet */
+/** \brief Test if ADC Status is Set */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_ADC_IsStatusSet( AT91PS_ADC pADC,    /* \arg  pointer to a ADC controller */
+                                             unsigned int flag ) /* \arg  flag to be tested */
 {
-    return (AT91F_ADC_GetStatus(pADC) & flag);
+    return( AT91F_ADC_GetStatus( pADC ) & flag );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_CfgModeReg
-//* \brief Configure the Mode Register of the ADC controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_ADC_CfgModeReg (
-    AT91PS_ADC pADC, // pointer to a ADC controller
-    unsigned int mode)        // mode register
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_ADC_CfgModeReg */
+/** \brief Configure the Mode Register of the ADC controller */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_ADC_CfgModeReg( AT91PS_ADC pADC,    /* pointer to a ADC controller */
+                                    unsigned int mode ) /* mode register */
 {
-    //* Write to the MR register
+    /** Write to the MR register */
     pADC->ADC_MR = mode;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetModeReg
-//* \brief Return the Mode Register of the ADC controller value
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetModeReg (
-    AT91PS_ADC pADC // pointer to a ADC controller
-    )
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_ADC_GetModeReg */
+/** \brief Return the Mode Register of the ADC controller value */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_ADC_GetModeReg( AT91PS_ADC pADC /* pointer to a ADC controller */
+                                            )
 {
     return pADC->ADC_MR;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_CfgTimings
-//* \brief Configure the different necessary timings of the ADC controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_ADC_CfgTimings (
-    AT91PS_ADC pADC, // pointer to a ADC controller
-    unsigned int mck_clock, // in MHz
-    unsigned int adc_clock, // in MHz
-    unsigned int startup_time, // in us
-    unsigned int sample_and_hold_time)  // in ns
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_ADC_CfgTimings */
+/** \brief Configure the different necessary timings of the ADC controller */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_ADC_CfgTimings( AT91PS_ADC pADC,                    /* pointer to a ADC controller */
+                                    unsigned int mck_clock,             /* in MHz */
+                                    unsigned int adc_clock,             /* in MHz */
+                                    unsigned int startup_time,          /* in us */
+                                    unsigned int sample_and_hold_time ) /* in ns */
 {
-    unsigned int prescal,startup,shtim;
+    unsigned int prescal, startup, shtim;
 
-    prescal = mck_clock/(2*adc_clock) - 1;
-    startup = adc_clock*startup_time/8 - 1;
-    shtim = adc_clock*sample_and_hold_time/1000 - 1;
+    prescal = mck_clock / ( 2 * adc_clock ) - 1;
+    startup = adc_clock * startup_time / 8 - 1;
+    shtim = adc_clock * sample_and_hold_time / 1000 - 1;
 
-    //* Write to the MR register
-    pADC->ADC_MR = ( (prescal<<8) & AT91C_ADC_PRESCAL) | ( (startup<<16) & AT91C_ADC_STARTUP) | ( (shtim<<24) & AT91C_ADC_SHTIM);
+    /** Write to the MR register */
+    pADC->ADC_MR = ( ( prescal << 8 ) & AT91C_ADC_PRESCAL ) | ( ( startup << 16 ) & AT91C_ADC_STARTUP ) | ( ( shtim << 24 ) & AT91C_ADC_SHTIM );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_EnableChannel
-//* \brief Return ADC Timer Register Value
-//*----------------------------------------------------------------------------
-__inline void AT91F_ADC_EnableChannel (
-    AT91PS_ADC pADC, // pointer to a ADC controller
-    unsigned int channel)        // mode register
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_ADC_EnableChannel */
+/** \brief Return ADC Timer Register Value */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_ADC_EnableChannel( AT91PS_ADC pADC,       /* pointer to a ADC controller */
+                                       unsigned int channel ) /* mode register */
 {
-    //* Write to the CHER register
+    /** Write to the CHER register */
     pADC->ADC_CHER = channel;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_DisableChannel
-//* \brief Return ADC Timer Register Value
-//*----------------------------------------------------------------------------
-__inline void AT91F_ADC_DisableChannel (
-    AT91PS_ADC pADC, // pointer to a ADC controller
-    unsigned int channel)        // mode register
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_ADC_DisableChannel */
+/** \brief Return ADC Timer Register Value */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_ADC_DisableChannel( AT91PS_ADC pADC,       /* pointer to a ADC controller */
+                                        unsigned int channel ) /* mode register */
 {
-    //* Write to the CHDR register
+    /** Write to the CHDR register */
     pADC->ADC_CHDR = channel;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetChannelStatus
-//* \brief Return ADC Timer Register Value
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetChannelStatus (
-    AT91PS_ADC pADC // pointer to a ADC controller
-    )
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_ADC_GetChannelStatus */
+/** \brief Return ADC Timer Register Value */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_ADC_GetChannelStatus( AT91PS_ADC pADC /* pointer to a ADC controller */
+                                                  )
 {
     return pADC->ADC_CHSR;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_StartConversion
-//* \brief Software request for a analog to digital conversion
-//*----------------------------------------------------------------------------
-__inline void AT91F_ADC_StartConversion (
-    AT91PS_ADC pADC // pointer to a ADC controller
-    )
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_ADC_StartConversion */
+/** \brief Software request for a analog to digital conversion */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_ADC_StartConversion( AT91PS_ADC pADC /* pointer to a ADC controller */
+                                         )
 {
     pADC->ADC_CR = AT91C_ADC_START;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_SoftReset
-//* \brief Software reset
-//*----------------------------------------------------------------------------
-__inline void AT91F_ADC_SoftReset (
-    AT91PS_ADC pADC // pointer to a ADC controller
-    )
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_ADC_SoftReset */
+/** \brief Software reset */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_ADC_SoftReset( AT91PS_ADC pADC /* pointer to a ADC controller */
+                                   )
 {
     pADC->ADC_CR = AT91C_ADC_SWRST;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetLastConvertedData
-//* \brief Return the Last Converted Data
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetLastConvertedData (
-    AT91PS_ADC pADC // pointer to a ADC controller
-    )
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_ADC_GetLastConvertedData */
+/** \brief Return the Last Converted Data */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_ADC_GetLastConvertedData( AT91PS_ADC pADC /* pointer to a ADC controller */
+                                                      )
 {
     return pADC->ADC_LCDR;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetConvertedDataCH0
-//* \brief Return the Channel 0 Converted Data
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetConvertedDataCH0 (
-    AT91PS_ADC pADC // pointer to a ADC controller
-    )
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_ADC_GetConvertedDataCH0 */
+/** \brief Return the Channel 0 Converted Data */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_ADC_GetConvertedDataCH0( AT91PS_ADC pADC /* pointer to a ADC controller */
+                                                     )
 {
     return pADC->ADC_CDR0;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetConvertedDataCH1
-//* \brief Return the Channel 1 Converted Data
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetConvertedDataCH1 (
-    AT91PS_ADC pADC // pointer to a ADC controller
-    )
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_ADC_GetConvertedDataCH1 */
+/** \brief Return the Channel 1 Converted Data */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_ADC_GetConvertedDataCH1( AT91PS_ADC pADC /* pointer to a ADC controller */
+                                                     )
 {
     return pADC->ADC_CDR1;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetConvertedDataCH2
-//* \brief Return the Channel 2 Converted Data
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetConvertedDataCH2 (
-    AT91PS_ADC pADC // pointer to a ADC controller
-    )
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_ADC_GetConvertedDataCH2 */
+/** \brief Return the Channel 2 Converted Data */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_ADC_GetConvertedDataCH2( AT91PS_ADC pADC /* pointer to a ADC controller */
+                                                     )
 {
     return pADC->ADC_CDR2;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetConvertedDataCH3
-//* \brief Return the Channel 3 Converted Data
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetConvertedDataCH3 (
-    AT91PS_ADC pADC // pointer to a ADC controller
-    )
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_ADC_GetConvertedDataCH3 */
+/** \brief Return the Channel 3 Converted Data */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_ADC_GetConvertedDataCH3( AT91PS_ADC pADC /* pointer to a ADC controller */
+                                                     )
 {
     return pADC->ADC_CDR3;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetConvertedDataCH4
-//* \brief Return the Channel 4 Converted Data
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetConvertedDataCH4 (
-    AT91PS_ADC pADC // pointer to a ADC controller
-    )
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_ADC_GetConvertedDataCH4 */
+/** \brief Return the Channel 4 Converted Data */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_ADC_GetConvertedDataCH4( AT91PS_ADC pADC /* pointer to a ADC controller */
+                                                     )
 {
     return pADC->ADC_CDR4;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetConvertedDataCH5
-//* \brief Return the Channel 5 Converted Data
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetConvertedDataCH5 (
-    AT91PS_ADC pADC // pointer to a ADC controller
-    )
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_ADC_GetConvertedDataCH5 */
+/** \brief Return the Channel 5 Converted Data */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_ADC_GetConvertedDataCH5( AT91PS_ADC pADC /* pointer to a ADC controller */
+                                                     )
 {
     return pADC->ADC_CDR5;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetConvertedDataCH6
-//* \brief Return the Channel 6 Converted Data
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetConvertedDataCH6 (
-    AT91PS_ADC pADC // pointer to a ADC controller
-    )
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_ADC_GetConvertedDataCH6 */
+/** \brief Return the Channel 6 Converted Data */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_ADC_GetConvertedDataCH6( AT91PS_ADC pADC /* pointer to a ADC controller */
+                                                     )
 {
     return pADC->ADC_CDR6;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetConvertedDataCH7
-//* \brief Return the Channel 7 Converted Data
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetConvertedDataCH7 (
-    AT91PS_ADC pADC // pointer to a ADC controller
-    )
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_ADC_GetConvertedDataCH7 */
+/** \brief Return the Channel 7 Converted Data */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_ADC_GetConvertedDataCH7( AT91PS_ADC pADC /* pointer to a ADC controller */
+                                                     )
 {
     return pADC->ADC_CDR7;
 }
 
 /* *****************************************************************************
-                SOFTWARE API FOR PIO
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgPeriph
-//* \brief Enable pins to be drived by peripheral
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgPeriph(
-    AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-    unsigned int periphAEnable,  // \arg PERIPH A to enable
-    unsigned int periphBEnable)  // \arg PERIPH B to enable
+*               SOFTWARE API FOR PIO
+***************************************************************************** */
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_CfgPeriph */
+/** \brief Enable pins to be derived by peripheral */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_PIO_CfgPeriph( AT91PS_PIO pPio,             /* \arg pointer to a PIO controller */
+                                   unsigned int periphAEnable,  /* \arg PERIPH A to enable */
+                                   unsigned int periphBEnable ) /* \arg PERIPH B to enable */
 
 {
     pPio->PIO_ASR = periphAEnable;
     pPio->PIO_BSR = periphBEnable;
-    pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode
+    pPio->PIO_PDR = ( periphAEnable | periphBEnable ); /* Set in Periph mode */
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgOutput
-//* \brief Enable PIO in output mode
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgOutput(
-    AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-    unsigned int pioEnable)      // \arg PIO to be enabled
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_CfgOutput */
+/** \brief Enable PIO in output mode */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_PIO_CfgOutput( AT91PS_PIO pPio,         /* \arg pointer to a PIO controller */
+                                   unsigned int pioEnable ) /* \arg PIO to be enabled */
 {
-    pPio->PIO_PER = pioEnable; // Set in PIO mode
-    pPio->PIO_OER = pioEnable; // Configure in Output
+    pPio->PIO_PER = pioEnable;                              /* Set in PIO mode */
+    pPio->PIO_OER = pioEnable;                              /* Configure in Output */
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgInput
-//* \brief Enable PIO in input mode
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgInput(
-    AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-    unsigned int inputEnable)      // \arg PIO to be enabled
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_CfgInput */
+/** \brief Enable PIO in input mode */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_PIO_CfgInput( AT91PS_PIO pPio,           /* \arg pointer to a PIO controller */
+                                  unsigned int inputEnable ) /* \arg PIO to be enabled */
 {
-    // Disable output
-    pPio->PIO_ODR  = inputEnable;
-    pPio->PIO_PER  = inputEnable;
+    /* Disable output */
+    pPio->PIO_ODR = inputEnable;
+    pPio->PIO_PER = inputEnable;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgOpendrain
-//* \brief Configure PIO in open drain
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgOpendrain(
-    AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-    unsigned int multiDrvEnable) // \arg pio to be configured in open drain
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_CfgOpendrain */
+/** \brief Configure PIO in open drain */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_PIO_CfgOpendrain( AT91PS_PIO pPio,              /* \arg pointer to a PIO controller */
+                                      unsigned int multiDrvEnable ) /* \arg pio to be configured in open drain */
 {
-    // Configure the multi-drive option
+    /* Configure the multi-drive option */
     pPio->PIO_MDDR = ~multiDrvEnable;
     pPio->PIO_MDER = multiDrvEnable;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgPullup
-//* \brief Enable pullup on PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgPullup(
-    AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-    unsigned int pullupEnable)   // \arg enable pullup on PIO
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_CfgPullup */
+/** \brief Enable pullup on PIO */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_PIO_CfgPullup( AT91PS_PIO pPio,            /* \arg pointer to a PIO controller */
+                                   unsigned int pullupEnable ) /* \arg enable pullup on PIO */
 {
-        // Connect or not Pullup
+    /* Connect or not Pullup */
     pPio->PIO_PPUDR = ~pullupEnable;
     pPio->PIO_PPUER = pullupEnable;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgDirectDrive
-//* \brief Enable direct drive on PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgDirectDrive(
-    AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-    unsigned int directDrive)    // \arg PIO to be configured with direct drive
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_CfgDirectDrive */
+/** \brief Enable direct drive on PIO */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_PIO_CfgDirectDrive( AT91PS_PIO pPio,           /* \arg pointer to a PIO controller */
+                                        unsigned int directDrive ) /* \arg PIO to be configured with direct drive */
 
 {
-    // Configure the Direct Drive
-    pPio->PIO_OWDR  = ~directDrive;
-    pPio->PIO_OWER  = directDrive;
+    /* Configure the Direct Drive */
+    pPio->PIO_OWDR = ~directDrive;
+    pPio->PIO_OWER = directDrive;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgInputFilter
-//* \brief Enable input filter on input PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgInputFilter(
-    AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-    unsigned int inputFilter)    // \arg PIO to be configured with input filter
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_CfgInputFilter */
+/** \brief Enable input filter on input PIO */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_PIO_CfgInputFilter( AT91PS_PIO pPio,           /* \arg pointer to a PIO controller */
+                                        unsigned int inputFilter ) /* \arg PIO to be configured with input filter */
 
 {
-    // Configure the Direct Drive
-    pPio->PIO_IFDR  = ~inputFilter;
-    pPio->PIO_IFER  = inputFilter;
+    /* Configure the Direct Drive */
+    pPio->PIO_IFDR = ~inputFilter;
+    pPio->PIO_IFER = inputFilter;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetInput
-//* \brief Return PIO input value
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetInput( // \return PIO input
-    AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_GetInput */
+/** \brief Return PIO input value */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_PIO_GetInput( /* \return PIO input */
+    AT91PS_PIO pPio )                     /* \arg  pointer to a PIO controller */
 {
     return pPio->PIO_PDSR;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsInputSet
-//* \brief Test if PIO is input flag is active
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsInputSet(
-    AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-    unsigned int flag) // \arg  flag to be tested
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_IsInputSet */
+/** \brief Test if PIO is input flag is active */
+/**---------------------------------------------------------------------------- */
+__inline int AT91F_PIO_IsInputSet( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                   unsigned int flag ) /* \arg  flag to be tested */
 {
-    return (AT91F_PIO_GetInput(pPio) & flag);
+    return( AT91F_PIO_GetInput( pPio ) & flag );
 }
 
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_SetOutput
-//* \brief Set to 1 output PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_SetOutput(
-    AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-    unsigned int flag) // \arg  output to be set
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_SetOutput */
+/** \brief Set to 1 output PIO */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_PIO_SetOutput( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                   unsigned int flag ) /* \arg  output to be set */
 {
     pPio->PIO_SODR = flag;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_ClearOutput
-//* \brief Set to 0 output PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_ClearOutput(
-    AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-    unsigned int flag) // \arg  output to be cleared
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_ClearOutput */
+/** \brief Set to 0 output PIO */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_PIO_ClearOutput( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                     unsigned int flag ) /* \arg  output to be cleared */
 {
     pPio->PIO_CODR = flag;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_ForceOutput
-//* \brief Force output when Direct drive option is enabled
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_ForceOutput(
-    AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-    unsigned int flag) // \arg  output to be forced
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_ForceOutput */
+/** \brief Force output when Direct drive option is enabled */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_PIO_ForceOutput( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                     unsigned int flag ) /* \arg  output to be forced */
 {
     pPio->PIO_ODSR = flag;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_Enable
-//* \brief Enable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_Enable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio to be enabled
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_Enable */
+/** \brief Enable PIO */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_PIO_Enable( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                unsigned int flag ) /* \arg  pio to be enabled */
 {
-        pPio->PIO_PER = flag;
+    pPio->PIO_PER = flag;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_Disable
-//* \brief Disable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_Disable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio to be disabled
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_Disable */
+/** \brief Disable PIO */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_PIO_Disable( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                 unsigned int flag ) /* \arg  pio to be disabled */
 {
-        pPio->PIO_PDR = flag;
+    pPio->PIO_PDR = flag;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetStatus
-//* \brief Return PIO Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_GetStatus */
+/** \brief Return PIO Status */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_PIO_GetStatus( /* \return PIO Status */
+    AT91PS_PIO pPio )                      /* \arg  pointer to a PIO controller */
 {
-        return pPio->PIO_PSR;
+    return pPio->PIO_PSR;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsSet
-//* \brief Test if PIO is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_IsSet */
+/** \brief Test if PIO is Set */
+/**---------------------------------------------------------------------------- */
+__inline int AT91F_PIO_IsSet( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                              unsigned int flag ) /* \arg  flag to be tested */
 {
-        return (AT91F_PIO_GetStatus(pPio) & flag);
+    return( AT91F_PIO_GetStatus( pPio ) & flag );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_OutputEnable
-//* \brief Output Enable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_OutputEnable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio output to be enabled
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_OutputEnable */
+/** \brief Output Enable PIO */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_PIO_OutputEnable( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                      unsigned int flag ) /* \arg  pio output to be enabled */
 {
-        pPio->PIO_OER = flag;
+    pPio->PIO_OER = flag;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_OutputDisable
-//* \brief Output Enable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_OutputDisable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio output to be disabled
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_OutputDisable */
+/** \brief Output Enable PIO */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_PIO_OutputDisable( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                       unsigned int flag ) /* \arg  pio output to be disabled */
 {
-        pPio->PIO_ODR = flag;
+    pPio->PIO_ODR = flag;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetOutputStatus
-//* \brief Return PIO Output Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_GetOutputStatus */
+/** \brief Return PIO Output Status */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_PIO_GetOutputStatus( /* \return PIO Output Status */
+    AT91PS_PIO pPio )                            /* \arg  pointer to a PIO controller */
 {
-        return pPio->PIO_OSR;
+    return pPio->PIO_OSR;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsOuputSet
-//* \brief Test if PIO Output is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsOutputSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_IsOuputSet */
+/** \brief Test if PIO Output is Set */
+/**---------------------------------------------------------------------------- */
+__inline int AT91F_PIO_IsOutputSet( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                    unsigned int flag ) /* \arg  flag to be tested */
 {
-        return (AT91F_PIO_GetOutputStatus(pPio) & flag);
+    return( AT91F_PIO_GetOutputStatus( pPio ) & flag );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_InputFilterEnable
-//* \brief Input Filter Enable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_InputFilterEnable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio input filter to be enabled
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_InputFilterEnable */
+/** \brief Input Filter Enable PIO */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_PIO_InputFilterEnable( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                           unsigned int flag ) /* \arg  pio input filter to be enabled */
 {
-        pPio->PIO_IFER = flag;
+    pPio->PIO_IFER = flag;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_InputFilterDisable
-//* \brief Input Filter Disable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_InputFilterDisable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio input filter to be disabled
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_InputFilterDisable */
+/** \brief Input Filter Disable PIO */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_PIO_InputFilterDisable( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                            unsigned int flag ) /* \arg  pio input filter to be disabled */
 {
-        pPio->PIO_IFDR = flag;
+    pPio->PIO_IFDR = flag;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetInputFilterStatus
-//* \brief Return PIO Input Filter Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_GetInputFilterStatus */
+/** \brief Return PIO Input Filter Status */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_PIO_GetInputFilterStatus( /* \return PIO Input Filter Status */
+    AT91PS_PIO pPio )                                 /* \arg  pointer to a PIO controller */
 {
-        return pPio->PIO_IFSR;
+    return pPio->PIO_IFSR;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsInputFilterSet
-//* \brief Test if PIO Input filter is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsInputFilterSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_IsInputFilterSet */
+/** \brief Test if PIO Input filter is Set */
+/**---------------------------------------------------------------------------- */
+__inline int AT91F_PIO_IsInputFilterSet( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                         unsigned int flag ) /* \arg  flag to be tested */
 {
-        return (AT91F_PIO_GetInputFilterStatus(pPio) & flag);
+    return( AT91F_PIO_GetInputFilterStatus( pPio ) & flag );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetOutputDataStatus
-//* \brief Return PIO Output Data Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status
-    AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_GetOutputDataStatus */
+/** \brief Return PIO Output Data Status */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_PIO_GetOutputDataStatus( /* \return PIO Output Data Status */
+    AT91PS_PIO pPio )                                /* \arg  pointer to a PIO controller */
 {
-        return pPio->PIO_ODSR;
+    return pPio->PIO_ODSR;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_InterruptEnable
-//* \brief Enable PIO Interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_InterruptEnable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio interrupt to be enabled
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_InterruptEnable */
+/** \brief Enable PIO Interrupt */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_PIO_InterruptEnable( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                         unsigned int flag ) /* \arg  pio interrupt to be enabled */
 {
-        pPio->PIO_IER = flag;
+    pPio->PIO_IER = flag;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_InterruptDisable
-//* \brief Disable PIO Interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_InterruptDisable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio interrupt to be disabled
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_InterruptDisable */
+/** \brief Disable PIO Interrupt */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_PIO_InterruptDisable( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                          unsigned int flag ) /* \arg  pio interrupt to be disabled */
 {
-        pPio->PIO_IDR = flag;
+    pPio->PIO_IDR = flag;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetInterruptMaskStatus
-//* \brief Return PIO Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_GetInterruptMaskStatus */
+/** \brief Return PIO Interrupt Mask Status */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_PIO_GetInterruptMaskStatus( /* \return PIO Interrupt Mask Status */
+    AT91PS_PIO pPio )                                   /* \arg  pointer to a PIO controller */
 {
-        return pPio->PIO_IMR;
+    return pPio->PIO_IMR;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetInterruptStatus
-//* \brief Return PIO Interrupt Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_GetInterruptStatus */
+/** \brief Return PIO Interrupt Status */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_PIO_GetInterruptStatus( /* \return PIO Interrupt Status */
+    AT91PS_PIO pPio )                               /* \arg  pointer to a PIO controller */
 {
-        return pPio->PIO_ISR;
+    return pPio->PIO_ISR;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsInterruptMasked
-//* \brief Test if PIO Interrupt is Masked
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsInterruptMasked(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_IsInterruptMasked */
+/** \brief Test if PIO Interrupt is Masked */
+/**---------------------------------------------------------------------------- */
+__inline int AT91F_PIO_IsInterruptMasked( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                          unsigned int flag ) /* \arg  flag to be tested */
 {
-        return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag);
+    return( AT91F_PIO_GetInterruptMaskStatus( pPio ) & flag );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsInterruptSet
-//* \brief Test if PIO Interrupt is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsInterruptSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_IsInterruptSet */
+/** \brief Test if PIO Interrupt is Set */
+/**---------------------------------------------------------------------------- */
+__inline int AT91F_PIO_IsInterruptSet( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                       unsigned int flag ) /* \arg  flag to be tested */
 {
-        return (AT91F_PIO_GetInterruptStatus(pPio) & flag);
+    return( AT91F_PIO_GetInterruptStatus( pPio ) & flag );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_MultiDriverEnable
-//* \brief Multi Driver Enable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_MultiDriverEnable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio to be enabled
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_MultiDriverEnable */
+/** \brief Multi Driver Enable PIO */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_PIO_MultiDriverEnable( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                           unsigned int flag ) /* \arg  pio to be enabled */
 {
-        pPio->PIO_MDER = flag;
+    pPio->PIO_MDER = flag;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_MultiDriverDisable
-//* \brief Multi Driver Disable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_MultiDriverDisable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio to be disabled
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_MultiDriverDisable */
+/** \brief Multi Driver Disable PIO */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_PIO_MultiDriverDisable( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                            unsigned int flag ) /* \arg  pio to be disabled */
 {
-        pPio->PIO_MDDR = flag;
+    pPio->PIO_MDDR = flag;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetMultiDriverStatus
-//* \brief Return PIO Multi Driver Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_GetMultiDriverStatus */
+/** \brief Return PIO Multi Driver Status */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_PIO_GetMultiDriverStatus( /* \return PIO Multi Driver Status */
+    AT91PS_PIO pPio )                                 /* \arg  pointer to a PIO controller */
 {
-        return pPio->PIO_MDSR;
+    return pPio->PIO_MDSR;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsMultiDriverSet
-//* \brief Test if PIO MultiDriver is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsMultiDriverSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_IsMultiDriverSet */
+/** \brief Test if PIO MultiDriver is Set */
+/**---------------------------------------------------------------------------- */
+__inline int AT91F_PIO_IsMultiDriverSet( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                         unsigned int flag ) /* \arg  flag to be tested */
 {
-        return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag);
+    return( AT91F_PIO_GetMultiDriverStatus( pPio ) & flag );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_A_RegisterSelection
-//* \brief PIO A Register Selection
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_A_RegisterSelection(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio A register selection
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_A_RegisterSelection */
+/** \brief PIO A Register Selection */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_PIO_A_RegisterSelection( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                             unsigned int flag ) /* \arg  pio A register selection */
 {
-        pPio->PIO_ASR = flag;
+    pPio->PIO_ASR = flag;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_B_RegisterSelection
-//* \brief PIO B Register Selection
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_B_RegisterSelection(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio B register selection
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_B_RegisterSelection */
+/** \brief PIO B Register Selection */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_PIO_B_RegisterSelection( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                             unsigned int flag ) /* \arg  pio B register selection */
 {
-        pPio->PIO_BSR = flag;
+    pPio->PIO_BSR = flag;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_Get_AB_RegisterStatus
-//* \brief Return PIO Interrupt Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_Get_AB_RegisterStatus */
+/** \brief Return PIO Interrupt Status */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( /* \return PIO AB Register Status */
+    AT91PS_PIO pPio )                                  /* \arg  pointer to a PIO controller */
 {
-        return pPio->PIO_ABSR;
+    return pPio->PIO_ABSR;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsAB_RegisterSet
-//* \brief Test if PIO AB Register is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsAB_RegisterSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_IsAB_RegisterSet */
+/** \brief Test if PIO AB Register is Set */
+/**---------------------------------------------------------------------------- */
+__inline int AT91F_PIO_IsAB_RegisterSet( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                         unsigned int flag ) /* \arg  flag to be tested */
 {
-        return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag);
+    return( AT91F_PIO_Get_AB_RegisterStatus( pPio ) & flag );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_OutputWriteEnable
-//* \brief Output Write Enable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_OutputWriteEnable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio output write to be enabled
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_OutputWriteEnable */
+/** \brief Output Write Enable PIO */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_PIO_OutputWriteEnable( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                           unsigned int flag ) /* \arg  pio output write to be enabled */
 {
-        pPio->PIO_OWER = flag;
+    pPio->PIO_OWER = flag;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_OutputWriteDisable
-//* \brief Output Write Disable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_OutputWriteDisable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio output write to be disabled
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_OutputWriteDisable */
+/** \brief Output Write Disable PIO */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_PIO_OutputWriteDisable( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                            unsigned int flag ) /* \arg  pio output write to be disabled */
 {
-        pPio->PIO_OWDR = flag;
+    pPio->PIO_OWDR = flag;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetOutputWriteStatus
-//* \brief Return PIO Output Write Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_GetOutputWriteStatus */
+/** \brief Return PIO Output Write Status */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_PIO_GetOutputWriteStatus( /* \return PIO Output Write Status */
+    AT91PS_PIO pPio )                                 /* \arg  pointer to a PIO controller */
 {
-        return pPio->PIO_OWSR;
+    return pPio->PIO_OWSR;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsOutputWriteSet
-//* \brief Test if PIO OutputWrite is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsOutputWriteSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_IsOutputWriteSet */
+/** \brief Test if PIO OutputWrite is Set */
+/**---------------------------------------------------------------------------- */
+__inline int AT91F_PIO_IsOutputWriteSet( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                         unsigned int flag ) /* \arg  flag to be tested */
 {
-        return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag);
+    return( AT91F_PIO_GetOutputWriteStatus( pPio ) & flag );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetCfgPullup
-//* \brief Return PIO Configuration Pullup
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_GetCfgPullup */
+/** \brief Return PIO Configuration Pullup */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_PIO_GetCfgPullup( /* \return PIO Configuration Pullup */
+    AT91PS_PIO pPio )                         /* \arg  pointer to a PIO controller */
 {
-        return pPio->PIO_PPUSR;
+    return pPio->PIO_PPUSR;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsOutputDataStatusSet
-//* \brief Test if PIO Output Data Status is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsOutputDataStatusSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_IsOutputDataStatusSet */
+/** \brief Test if PIO Output Data Status is Set */
+/**---------------------------------------------------------------------------- */
+__inline int AT91F_PIO_IsOutputDataStatusSet( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                              unsigned int flag ) /* \arg  flag to be tested */
 {
-        return (AT91F_PIO_GetOutputDataStatus(pPio) & flag);
+    return( AT91F_PIO_GetOutputDataStatus( pPio ) & flag );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsCfgPullupStatusSet
-//* \brief Test if PIO Configuration Pullup Status is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsCfgPullupStatusSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_IsCfgPullupStatusSet */
+/** \brief Test if PIO Configuration Pullup Status is Set */
+/**---------------------------------------------------------------------------- */
+__inline int AT91F_PIO_IsCfgPullupStatusSet( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                             unsigned int flag ) /* \arg  flag to be tested */
 {
-        return (~AT91F_PIO_GetCfgPullup(pPio) & flag);
+    return( ~AT91F_PIO_GetCfgPullup( pPio ) & flag );
 }
 
 /* *****************************************************************************
-                SOFTWARE API FOR TWI
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TWI_EnableIt
-//* \brief Enable TWI IT
-//*----------------------------------------------------------------------------
-__inline void AT91F_TWI_EnableIt (
-    AT91PS_TWI pTWI, // \arg pointer to a TWI controller
-    unsigned int flag)   // \arg IT to be enabled
+*               SOFTWARE API FOR TWI
+***************************************************************************** */
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_TWI_EnableIt */
+/** \brief Enable TWI IT */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_TWI_EnableIt( AT91PS_TWI pTWI,    /* \arg pointer to a TWI controller */
+                                  unsigned int flag ) /* \arg IT to be enabled */
 {
-    //* Write to the IER register
+    /** Write to the IER register */
     pTWI->TWI_IER = flag;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TWI_DisableIt
-//* \brief Disable TWI IT
-//*----------------------------------------------------------------------------
-__inline void AT91F_TWI_DisableIt (
-    AT91PS_TWI pTWI, // \arg pointer to a TWI controller
-    unsigned int flag)   // \arg IT to be disabled
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_TWI_DisableIt */
+/** \brief Disable TWI IT */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_TWI_DisableIt( AT91PS_TWI pTWI,    /* \arg pointer to a TWI controller */
+                                   unsigned int flag ) /* \arg IT to be disabled */
 {
-    //* Write to the IDR register
+    /** Write to the IDR register */
     pTWI->TWI_IDR = flag;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TWI_Configure
-//* \brief Configure TWI in master mode
-//*----------------------------------------------------------------------------
-__inline void AT91F_TWI_Configure ( AT91PS_TWI pTWI )          // \arg pointer to a TWI controller
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_TWI_Configure */
+/** \brief Configure TWI in master mode */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_TWI_Configure( AT91PS_TWI pTWI ) /* \arg pointer to a TWI controller */
 {
-    //* Disable interrupts
-    pTWI->TWI_IDR = (unsigned int) -1;
+    /** Disable interrupts */
+    pTWI->TWI_IDR = ( unsigned int ) -1;
 
-    //* Reset peripheral
+    /** Reset peripheral */
     pTWI->TWI_CR = AT91C_TWI_SWRST;
 
-    //* Set Master mode
+    /** Set Master mode */
     pTWI->TWI_CR = AT91C_TWI_MSEN | AT91C_TWI_SVDIS;
-
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TWI_GetInterruptMaskStatus
-//* \brief Return TWI Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_TWI_GetInterruptMaskStatus( // \return TWI Interrupt Mask Status
-        AT91PS_TWI pTwi) // \arg  pointer to a TWI controller
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_TWI_GetInterruptMaskStatus */
+/** \brief Return TWI Interrupt Mask Status */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_TWI_GetInterruptMaskStatus( /* \return TWI Interrupt Mask Status */
+    AT91PS_TWI pTwi )                                   /* \arg  pointer to a TWI controller */
 {
-        return pTwi->TWI_IMR;
+    return pTwi->TWI_IMR;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TWI_IsInterruptMasked
-//* \brief Test if TWI Interrupt is Masked
-//*----------------------------------------------------------------------------
-__inline int AT91F_TWI_IsInterruptMasked(
-        AT91PS_TWI pTwi,   // \arg  pointer to a TWI controller
-        unsigned int flag) // \arg  flag to be tested
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_TWI_IsInterruptMasked */
+/** \brief Test if TWI Interrupt is Masked */
+/**---------------------------------------------------------------------------- */
+__inline int AT91F_TWI_IsInterruptMasked( AT91PS_TWI pTwi,    /* \arg  pointer to a TWI controller */
+                                          unsigned int flag ) /* \arg  flag to be tested */
 {
-        return (AT91F_TWI_GetInterruptMaskStatus(pTwi) & flag);
+    return( AT91F_TWI_GetInterruptMaskStatus( pTwi ) & flag );
 }
 
 /* *****************************************************************************
-                SOFTWARE API FOR USART
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_Baudrate
-//* \brief Calculate the baudrate
-//* Standard Asynchronous Mode : 8 bits , 1 stop , no parity
-#define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \
-                        AT91C_US_NBSTOP_1_BIT + \
-                        AT91C_US_PAR_NONE + \
-                        AT91C_US_CHRL_8_BITS + \
-                        AT91C_US_CLKS_CLOCK )
+*               SOFTWARE API FOR USART
+***************************************************************************** */
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_US_Baudrate */
+/** \brief Calculate the baudrate */
+/** Standard Asynchronous Mode : 8 bits , 1 stop , no parity */
+#define AT91C_US_ASYNC_MODE    \
+    ( AT91C_US_USMODE_NORMAL + \
+      AT91C_US_NBSTOP_1_BIT +  \
+      AT91C_US_PAR_NONE +      \
+      AT91C_US_CHRL_8_BITS +   \
+      AT91C_US_CLKS_CLOCK )
 
-//* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity
-#define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \
-                            AT91C_US_NBSTOP_1_BIT + \
-                            AT91C_US_PAR_NONE + \
-                            AT91C_US_CHRL_8_BITS + \
-                            AT91C_US_CLKS_EXT )
+/** Standard External Asynchronous Mode : 8 bits , 1 stop , no parity */
+#define AT91C_US_ASYNC_SCK_MODE \
+    ( AT91C_US_USMODE_NORMAL +  \
+      AT91C_US_NBSTOP_1_BIT +   \
+      AT91C_US_PAR_NONE +       \
+      AT91C_US_CHRL_8_BITS +    \
+      AT91C_US_CLKS_EXT )
 
-//* Standard Synchronous Mode : 8 bits , 1 stop , no parity
-#define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \
-                       AT91C_US_USMODE_NORMAL + \
-                       AT91C_US_NBSTOP_1_BIT + \
-                       AT91C_US_PAR_NONE + \
-                       AT91C_US_CHRL_8_BITS + \
-                       AT91C_US_CLKS_CLOCK )
+/** Standard Synchronous Mode : 8 bits , 1 stop , no parity */
+#define AT91C_US_SYNC_MODE     \
+    ( AT91C_US_SYNC +          \
+      AT91C_US_USMODE_NORMAL + \
+      AT91C_US_NBSTOP_1_BIT +  \
+      AT91C_US_PAR_NONE +      \
+      AT91C_US_CHRL_8_BITS +   \
+      AT91C_US_CLKS_CLOCK )
 
-//* SCK used Label
-#define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT)
+/** SCK used Label */
+#define AT91C_US_SCK_USED    ( AT91C_US_CKLO | AT91C_US_CLKS_EXT )
 
-//* Standard ISO T=0 Mode : 8 bits , 1 stop , parity
-#define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \
-                             AT91C_US_CLKS_CLOCK +\
-                             AT91C_US_NBSTOP_1_BIT + \
-                             AT91C_US_PAR_EVEN + \
-                             AT91C_US_CHRL_8_BITS + \
-                             AT91C_US_CKLO +\
-                             AT91C_US_OVER)
+/** Standard ISO T=0 Mode : 8 bits , 1 stop , parity */
+#define AT91C_US_ISO_READER_MODE  \
+    ( AT91C_US_USMODE_ISO7816_0 + \
+      AT91C_US_CLKS_CLOCK +       \
+      AT91C_US_NBSTOP_1_BIT +     \
+      AT91C_US_PAR_EVEN +         \
+      AT91C_US_CHRL_8_BITS +      \
+      AT91C_US_CKLO +             \
+      AT91C_US_OVER )
 
-//* Standard IRDA mode
-#define AT91C_US_ASYNC_IRDA_MODE (  AT91C_US_USMODE_IRDA + \
-                            AT91C_US_NBSTOP_1_BIT + \
-                            AT91C_US_PAR_NONE + \
-                            AT91C_US_CHRL_8_BITS + \
-                            AT91C_US_CLKS_CLOCK )
+/** Standard IRDA mode */
+#define AT91C_US_ASYNC_IRDA_MODE \
+    ( AT91C_US_USMODE_IRDA +     \
+      AT91C_US_NBSTOP_1_BIT +    \
+      AT91C_US_PAR_NONE +        \
+      AT91C_US_CHRL_8_BITS +     \
+      AT91C_US_CLKS_CLOCK )
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_Baudrate
-//* \brief Caluculate baud_value according to the main clock and the baud rate
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_US_Baudrate (
-    const unsigned int main_clock, // \arg peripheral clock
-    const unsigned int baud_rate)  // \arg UART baudrate
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_US_Baudrate */
+/** \brief Calculate baud_value according to the main clock and the baud rate */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_US_Baudrate( const unsigned int main_clock, /* \arg peripheral clock */
+                                         const unsigned int baud_rate ) /* \arg UART baudrate */
 {
-    unsigned int baud_value = ((main_clock*10)/(baud_rate * 16));
-    if ((baud_value % 10) >= 5)
-        baud_value = (baud_value / 10) + 1;
+    unsigned int baud_value = ( ( main_clock * 10 ) / ( baud_rate * 16 ) );
+
+    if( ( baud_value % 10 ) >= 5 )
+    {
+        baud_value = ( baud_value / 10 ) + 1;
+    }
     else
+    {
         baud_value /= 10;
+    }
+
     return baud_value;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_SetBaudrate
-//* \brief Set the baudrate according to the CPU clock
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_SetBaudrate (
-    AT91PS_USART pUSART,    // \arg pointer to a USART controller
-    unsigned int mainClock, // \arg peripheral clock
-    unsigned int speed)     // \arg UART baudrate
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_US_SetBaudrate */
+/** \brief Set the baudrate according to the CPU clock */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_US_SetBaudrate( AT91PS_USART pUSART,    /* \arg pointer to a USART controller */
+                                    unsigned int mainClock, /* \arg peripheral clock */
+                                    unsigned int speed )    /* \arg UART baudrate */
 {
-    //* Define the baud rate divisor register
-    pUSART->US_BRGR = AT91F_US_Baudrate(mainClock, speed);
+    /** Define the baud rate divisor register */
+    pUSART->US_BRGR = AT91F_US_Baudrate( mainClock, speed );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_SetTimeguard
-//* \brief Set USART timeguard
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_SetTimeguard (
-    AT91PS_USART pUSART,    // \arg pointer to a USART controller
-    unsigned int timeguard) // \arg timeguard value
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_US_SetTimeguard */
+/** \brief Set USART timeguard */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_US_SetTimeguard( AT91PS_USART pUSART,     /* \arg pointer to a USART controller */
+                                     unsigned int timeguard ) /* \arg timeguard value */
 {
-    //* Write the Timeguard Register
-    pUSART->US_TTGR = timeguard ;
+    /** Write the Timeguard Register */
+    pUSART->US_TTGR = timeguard;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_EnableIt
-//* \brief Enable USART IT
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_EnableIt (
-    AT91PS_USART pUSART, // \arg pointer to a USART controller
-    unsigned int flag)   // \arg IT to be enabled
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_US_EnableIt */
+/** \brief Enable USART IT */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_US_EnableIt( AT91PS_USART pUSART, /* \arg pointer to a USART controller */
+                                 unsigned int flag )  /* \arg IT to be enabled */
 {
-    //* Write to the IER register
+    /** Write to the IER register */
     pUSART->US_IER = flag;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_DisableIt
-//* \brief Disable USART IT
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_DisableIt (
-    AT91PS_USART pUSART, // \arg pointer to a USART controller
-    unsigned int flag)   // \arg IT to be disabled
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_US_DisableIt */
+/** \brief Disable USART IT */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_US_DisableIt( AT91PS_USART pUSART, /* \arg pointer to a USART controller */
+                                  unsigned int flag )  /* \arg IT to be disabled */
 {
-    //* Write to the IER register
+    /** Write to the IER register */
     pUSART->US_IDR = flag;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_Configure
-//* \brief Configure USART
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_Configure (
-    AT91PS_USART pUSART,     // \arg pointer to a USART controller
-    unsigned int mainClock,  // \arg peripheral clock
-    unsigned int mode ,      // \arg mode Register to be programmed
-    unsigned int baudRate ,  // \arg baudrate to be programmed
-    unsigned int timeguard ) // \arg timeguard to be programmed
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_US_Configure */
+/** \brief Configure USART */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_US_Configure( AT91PS_USART pUSART,     /* \arg pointer to a USART controller */
+                                  unsigned int mainClock,  /* \arg peripheral clock */
+                                  unsigned int mode,       /* \arg mode Register to be programmed */
+                                  unsigned int baudRate,   /* \arg baudrate to be programmed */
+                                  unsigned int timeguard ) /* \arg timeguard to be programmed */
 {
-    //* Disable interrupts
-    pUSART->US_IDR = (unsigned int) -1;
+    /** Disable interrupts */
+    pUSART->US_IDR = ( unsigned int ) -1;
 
-    //* Reset receiver and transmitter
-    pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS ;
+    /** Reset receiver and transmitter */
+    pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS;
 
-    //* Define the baud rate divisor register
-    AT91F_US_SetBaudrate(pUSART, mainClock, baudRate);
+    /** Define the baud rate divisor register */
+    AT91F_US_SetBaudrate( pUSART, mainClock, baudRate );
 
-    //* Write the Timeguard Register
-    AT91F_US_SetTimeguard(pUSART, timeguard);
+    /** Write the Timeguard Register */
+    AT91F_US_SetTimeguard( pUSART, timeguard );
 
-    //* Clear Transmit and Receive Counters
-    AT91F_PDC_Open((AT91PS_PDC) &(pUSART->US_RPR));
-
-    //* Define the USART mode
-    pUSART->US_MR = mode  ;
+    /** Clear Transmit and Receive Counters */
+    AT91F_PDC_Open( ( AT91PS_PDC ) &( pUSART->US_RPR ) );
 
+    /** Define the USART mode */
+    pUSART->US_MR = mode;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_EnableRx
-//* \brief Enable receiving characters
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_EnableRx (
-    AT91PS_USART pUSART)     // \arg pointer to a USART controller
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_US_EnableRx */
+/** \brief Enable receiving characters */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_US_EnableRx( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */
 {
-    //* Enable receiver
+    /** Enable receiver */
     pUSART->US_CR = AT91C_US_RXEN;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_EnableTx
-//* \brief Enable sending characters
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_EnableTx (
-    AT91PS_USART pUSART)     // \arg pointer to a USART controller
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_US_EnableTx */
+/** \brief Enable sending characters */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_US_EnableTx( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */
 {
-    //* Enable  transmitter
+    /** Enable  transmitter */
     pUSART->US_CR = AT91C_US_TXEN;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_ResetRx
-//* \brief Reset Receiver and re-enable it
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_ResetRx (
-    AT91PS_USART pUSART)     // \arg pointer to a USART controller
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_US_ResetRx */
+/** \brief Reset Receiver and re-enable it */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_US_ResetRx( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */
 {
-    //* Reset receiver
+    /** Reset receiver */
     pUSART->US_CR = AT91C_US_RSTRX;
-    //* Re-Enable receiver
+    /** Re-Enable receiver */
     pUSART->US_CR = AT91C_US_RXEN;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_ResetTx
-//* \brief Reset Transmitter and re-enable it
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_ResetTx (
-    AT91PS_USART pUSART)     // \arg pointer to a USART controller
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_US_ResetTx */
+/** \brief Reset Transmitter and re-enable it */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_US_ResetTx( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */
 {
-    //* Reset transmitter
+    /** Reset transmitter */
     pUSART->US_CR = AT91C_US_RSTTX;
-    //* Enable transmitter
+    /** Enable transmitter */
     pUSART->US_CR = AT91C_US_TXEN;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_DisableRx
-//* \brief Disable Receiver
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_DisableRx (
-    AT91PS_USART pUSART)     // \arg pointer to a USART controller
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_US_DisableRx */
+/** \brief Disable Receiver */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_US_DisableRx( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */
 {
-    //* Disable receiver
+    /** Disable receiver */
     pUSART->US_CR = AT91C_US_RXDIS;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_DisableTx
-//* \brief Disable Transmitter
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_DisableTx (
-    AT91PS_USART pUSART)     // \arg pointer to a USART controller
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_US_DisableTx */
+/** \brief Disable Transmitter */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_US_DisableTx( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */
 {
-    //* Disable transmitter
+    /** Disable transmitter */
     pUSART->US_CR = AT91C_US_TXDIS;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_Close
-//* \brief Close USART: disable IT disable receiver and transmitter, close PDC
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_Close (
-    AT91PS_USART pUSART)     // \arg pointer to a USART controller
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_US_Close */
+/** \brief Close USART: disable IT disable receiver and transmitter, close PDC */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_US_Close( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */
 {
-    //* Reset the baud rate divisor register
-    pUSART->US_BRGR = 0 ;
+    /** Reset the baud rate divisor register */
+    pUSART->US_BRGR = 0;
 
-    //* Reset the USART mode
-    pUSART->US_MR = 0  ;
+    /** Reset the USART mode */
+    pUSART->US_MR = 0;
 
-    //* Reset the Timeguard Register
+    /** Reset the Timeguard Register */
     pUSART->US_TTGR = 0;
 
-    //* Disable all interrupts
-    pUSART->US_IDR = 0xFFFFFFFF ;
+    /** Disable all interrupts */
+    pUSART->US_IDR = 0xFFFFFFFF;
 
-    //* Abort the Peripheral Data Transfers
-    AT91F_PDC_Close((AT91PS_PDC) &(pUSART->US_RPR));
+    /** Abort the Peripheral Data Transfers */
+    AT91F_PDC_Close( ( AT91PS_PDC ) &( pUSART->US_RPR ) );
 
-    //* Disable receiver and transmitter and stop any activity immediately
-    pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX ;
+    /** Disable receiver and transmitter and stop any activity immediately */
+    pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_TxReady
-//* \brief Return 1 if a character can be written in US_THR
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_US_TxReady (
-    AT91PS_USART pUSART )     // \arg pointer to a USART controller
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_US_TxReady */
+/** \brief Return 1 if a character can be written in US_THR */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_US_TxReady( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */
 {
-    return (pUSART->US_CSR & AT91C_US_TXRDY);
+    return( pUSART->US_CSR & AT91C_US_TXRDY );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_RxReady
-//* \brief Return 1 if a character can be read in US_RHR
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_US_RxReady (
-    AT91PS_USART pUSART )     // \arg pointer to a USART controller
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_US_RxReady */
+/** \brief Return 1 if a character can be read in US_RHR */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_US_RxReady( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */
 {
-    return (pUSART->US_CSR & AT91C_US_RXRDY);
+    return( pUSART->US_CSR & AT91C_US_RXRDY );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_Error
-//* \brief Return the error flag
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_US_Error (
-    AT91PS_USART pUSART )     // \arg pointer to a USART controller
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_US_Error */
+/** \brief Return the error flag */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_US_Error( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */
 {
-    return (pUSART->US_CSR &
-        (AT91C_US_OVRE |  // Overrun error
-         AT91C_US_FRAME | // Framing error
-         AT91C_US_PARE));  // Parity error
+    return( pUSART->US_CSR &
+            ( AT91C_US_OVRE |    /* Overrun error */
+              AT91C_US_FRAME |   /* Framing error */
+              AT91C_US_PARE ) ); /* Parity error */
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_PutChar
-//* \brief Send a character,does not check if ready to send
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_PutChar (
-    AT91PS_USART pUSART,
-    int character )
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_US_PutChar */
+/** \brief Send a character,does not check if ready to send */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_US_PutChar( AT91PS_USART pUSART,
+                                int character )
 {
-    pUSART->US_THR = (character & 0x1FF);
+    pUSART->US_THR = ( character & 0x1FF );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_GetChar
-//* \brief Receive a character,does not check if a character is available
-//*----------------------------------------------------------------------------
-__inline int AT91F_US_GetChar (
-    const AT91PS_USART pUSART)
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_US_GetChar */
+/** \brief Receive a character,does not check if a character is available */
+/**---------------------------------------------------------------------------- */
+__inline int AT91F_US_GetChar( const AT91PS_USART pUSART )
 {
-    return((pUSART->US_RHR) & 0x1FF);
+    return( ( pUSART->US_RHR ) & 0x1FF );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_SendFrame
-//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_US_SendFrame(
-    AT91PS_USART pUSART,
-    char *pBuffer,
-    unsigned int szBuffer,
-    char *pNextBuffer,
-    unsigned int szNextBuffer )
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_US_SendFrame */
+/** \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_US_SendFrame( AT91PS_USART pUSART,
+                                          char * pBuffer,
+                                          unsigned int szBuffer,
+                                          char * pNextBuffer,
+                                          unsigned int szNextBuffer )
 {
     return AT91F_PDC_SendFrame(
-        (AT91PS_PDC) &(pUSART->US_RPR),
+        ( AT91PS_PDC ) &( pUSART->US_RPR ),
         pBuffer,
         szBuffer,
         pNextBuffer,
-        szNextBuffer);
+        szNextBuffer );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_ReceiveFrame
-//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_US_ReceiveFrame (
-    AT91PS_USART pUSART,
-    char *pBuffer,
-    unsigned int szBuffer,
-    char *pNextBuffer,
-    unsigned int szNextBuffer )
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_US_ReceiveFrame */
+/** \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_US_ReceiveFrame( AT91PS_USART pUSART,
+                                             char * pBuffer,
+                                             unsigned int szBuffer,
+                                             char * pNextBuffer,
+                                             unsigned int szNextBuffer )
 {
     return AT91F_PDC_ReceiveFrame(
-        (AT91PS_PDC) &(pUSART->US_RPR),
+        ( AT91PS_PDC ) &( pUSART->US_RPR ),
         pBuffer,
         szBuffer,
         pNextBuffer,
-        szNextBuffer);
+        szNextBuffer );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_SetIrdaFilter
-//* \brief Set the value of IrDa filter tregister
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_SetIrdaFilter (
-    AT91PS_USART pUSART,
-    unsigned char value
-)
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_US_SetIrdaFilter */
+/** \brief Set the value of IrDa filter register */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_US_SetIrdaFilter( AT91PS_USART pUSART,
+                                      unsigned char value )
 {
     pUSART->US_IF = value;
 }
 
 /* *****************************************************************************
-                SOFTWARE API FOR UDP
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_EnableIt
-//* \brief Enable UDP IT
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_EnableIt (
-    AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
-    unsigned int flag)   // \arg IT to be enabled
+*               SOFTWARE API FOR UDP
+***************************************************************************** */
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_UDP_EnableIt */
+/** \brief Enable UDP IT */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_UDP_EnableIt( AT91PS_UDP pUDP,    /* \arg pointer to a UDP controller */
+                                  unsigned int flag ) /* \arg IT to be enabled */
 {
-    //* Write to the IER register
+    /** Write to the IER register */
     pUDP->UDP_IER = flag;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_DisableIt
-//* \brief Disable UDP IT
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_DisableIt (
-    AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
-    unsigned int flag)   // \arg IT to be disabled
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_UDP_DisableIt */
+/** \brief Disable UDP IT */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_UDP_DisableIt( AT91PS_UDP pUDP,    /* \arg pointer to a UDP controller */
+                                   unsigned int flag ) /* \arg IT to be disabled */
 {
-    //* Write to the IDR register
+    /** Write to the IDR register */
     pUDP->UDP_IDR = flag;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_SetAddress
-//* \brief Set UDP functional address
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_SetAddress (
-    AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
-    unsigned char address)   // \arg new UDP address
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_UDP_SetAddress */
+/** \brief Set UDP functional address */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_UDP_SetAddress( AT91PS_UDP pUDP,        /* \arg pointer to a UDP controller */
+                                    unsigned char address ) /* \arg new UDP address */
 {
-    pUDP->UDP_FADDR = (AT91C_UDP_FEN | address);
+    pUDP->UDP_FADDR = ( AT91C_UDP_FEN | address );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_EnableEp
-//* \brief Enable Endpoint
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_EnableEp (
-    AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
-    unsigned int flag)   // \arg endpoints to be enabled
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_UDP_EnableEp */
+/** \brief Enable Endpoint */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_UDP_EnableEp( AT91PS_UDP pUDP,    /* \arg pointer to a UDP controller */
+                                  unsigned int flag ) /* \arg endpoints to be enabled */
 {
-    pUDP->UDP_GLBSTATE  |= flag;
+    pUDP->UDP_GLBSTATE |= flag;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_DisableEp
-//* \brief Enable Endpoint
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_DisableEp (
-    AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
-    unsigned int flag)   // \arg endpoints to be enabled
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_UDP_DisableEp */
+/** \brief Enable Endpoint */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_UDP_DisableEp( AT91PS_UDP pUDP,    /* \arg pointer to a UDP controller */
+                                   unsigned int flag ) /* \arg endpoints to be enabled */
 {
-    pUDP->UDP_GLBSTATE  &= ~(flag);
+    pUDP->UDP_GLBSTATE &= ~( flag );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_SetState
-//* \brief Set UDP Device state
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_SetState (
-    AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
-    unsigned int flag)   // \arg new UDP address
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_UDP_SetState */
+/** \brief Set UDP Device state */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_UDP_SetState( AT91PS_UDP pUDP,    /* \arg pointer to a UDP controller */
+                                  unsigned int flag ) /* \arg new UDP address */
 {
-    pUDP->UDP_GLBSTATE  &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG);
-    pUDP->UDP_GLBSTATE  |= flag;
+    pUDP->UDP_GLBSTATE &= ~( AT91C_UDP_FADDEN | AT91C_UDP_CONFG );
+    pUDP->UDP_GLBSTATE |= flag;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_GetState
-//* \brief return UDP Device state
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_UDP_GetState ( // \return the UDP device state
-    AT91PS_UDP pUDP)     // \arg pointer to a UDP controller
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_UDP_GetState */
+/** \brief return UDP Device state */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_UDP_GetState( /* \return the UDP device state */
+    AT91PS_UDP pUDP )                     /* \arg pointer to a UDP controller */
 {
-    return (pUDP->UDP_GLBSTATE  & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG));
+    return( pUDP->UDP_GLBSTATE & ( AT91C_UDP_FADDEN | AT91C_UDP_CONFG ) );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_ResetEp
-//* \brief Reset UDP endpoint
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_ResetEp ( // \return the UDP device state
-    AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
-    unsigned int flag)   // \arg Endpoints to be reset
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_UDP_ResetEp */
+/** \brief Reset UDP endpoint */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_UDP_ResetEp( /* \return the UDP device state */
+    AT91PS_UDP pUDP,             /* \arg pointer to a UDP controller */
+    unsigned int flag )          /* \arg Endpoints to be reset */
 {
     pUDP->UDP_RSTEP = flag;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_EpStall
-//* \brief Endpoint will STALL requests
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_EpStall(
-    AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
-    unsigned char endpoint)   // \arg endpoint number
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_UDP_EpStall */
+/** \brief Endpoint will STALL requests */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_UDP_EpStall( AT91PS_UDP pUDP,         /* \arg pointer to a UDP controller */
+                                 unsigned char endpoint ) /* \arg endpoint number */
 {
-    pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL;
+    pUDP->UDP_CSR[ endpoint ] |= AT91C_UDP_FORCESTALL;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_EpWrite
-//* \brief Write value in the DPR
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_EpWrite(
-    AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
-    unsigned char endpoint,  // \arg endpoint number
-    unsigned char value)     // \arg value to be written in the DPR
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_UDP_EpWrite */
+/** \brief Write value in the DPR */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_UDP_EpWrite( AT91PS_UDP pUDP,        /* \arg pointer to a UDP controller */
+                                 unsigned char endpoint, /* \arg endpoint number */
+                                 unsigned char value )   /* \arg value to be written in the DPR */
 {
-    pUDP->UDP_FDR[endpoint] = value;
+    pUDP->UDP_FDR[ endpoint ] = value;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_EpRead
-//* \brief Return value from the DPR
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_UDP_EpRead(
-    AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
-    unsigned char endpoint)  // \arg endpoint number
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_UDP_EpRead */
+/** \brief Return value from the DPR */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_UDP_EpRead( AT91PS_UDP pUDP,         /* \arg pointer to a UDP controller */
+                                        unsigned char endpoint ) /* \arg endpoint number */
 {
-    return pUDP->UDP_FDR[endpoint];
+    return pUDP->UDP_FDR[ endpoint ];
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_EpEndOfWr
-//* \brief Notify the UDP that values in DPR are ready to be sent
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_EpEndOfWr(
-    AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
-    unsigned char endpoint)  // \arg endpoint number
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_UDP_EpEndOfWr */
+/** \brief Notify the UDP that values in DPR are ready to be sent */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_UDP_EpEndOfWr( AT91PS_UDP pUDP,         /* \arg pointer to a UDP controller */
+                                   unsigned char endpoint ) /* \arg endpoint number */
 {
-    pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY;
+    pUDP->UDP_CSR[ endpoint ] |= AT91C_UDP_TXPKTRDY;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_EpClear
-//* \brief Clear flag in the endpoint CSR register
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_EpClear(
-    AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
-    unsigned char endpoint,  // \arg endpoint number
-    unsigned int flag)       // \arg flag to be cleared
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_UDP_EpClear */
+/** \brief Clear flag in the endpoint CSR register */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_UDP_EpClear( AT91PS_UDP pUDP,        /* \arg pointer to a UDP controller */
+                                 unsigned char endpoint, /* \arg endpoint number */
+                                 unsigned int flag )     /* \arg flag to be cleared */
 {
-    pUDP->UDP_CSR[endpoint] &= ~(flag);
+    pUDP->UDP_CSR[ endpoint ] &= ~( flag );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_EpSet
-//* \brief Set flag in the endpoint CSR register
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_EpSet(
-    AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
-    unsigned char endpoint,  // \arg endpoint number
-    unsigned int flag)       // \arg flag to be cleared
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_UDP_EpSet */
+/** \brief Set flag in the endpoint CSR register */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_UDP_EpSet( AT91PS_UDP pUDP,        /* \arg pointer to a UDP controller */
+                               unsigned char endpoint, /* \arg endpoint number */
+                               unsigned int flag )     /* \arg flag to be cleared */
 {
-    pUDP->UDP_CSR[endpoint] |= flag;
+    pUDP->UDP_CSR[ endpoint ] |= flag;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_EpStatus
-//* \brief Return the endpoint CSR register
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_UDP_EpStatus(
-    AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
-    unsigned char endpoint)  // \arg endpoint number
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_UDP_EpStatus */
+/** \brief Return the endpoint CSR register */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_UDP_EpStatus( AT91PS_UDP pUDP,         /* \arg pointer to a UDP controller */
+                                          unsigned char endpoint ) /* \arg endpoint number */
 {
-    return pUDP->UDP_CSR[endpoint];
+    return pUDP->UDP_CSR[ endpoint ];
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_GetInterruptMaskStatus
-//* \brief Return UDP Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_UDP_GetInterruptMaskStatus( // \return UDP Interrupt Mask Status
-        AT91PS_UDP pUdp) // \arg  pointer to a UDP controller
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_UDP_GetInterruptMaskStatus */
+/** \brief Return UDP Interrupt Mask Status */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_UDP_GetInterruptMaskStatus( /* \return UDP Interrupt Mask Status */
+    AT91PS_UDP pUdp )                                   /* \arg  pointer to a UDP controller */
 {
-        return pUdp->UDP_IMR;
+    return pUdp->UDP_IMR;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_IsInterruptMasked
-//* \brief Test if UDP Interrupt is Masked
-//*----------------------------------------------------------------------------
-__inline int AT91F_UDP_IsInterruptMasked(
-        AT91PS_UDP pUdp,   // \arg  pointer to a UDP controller
-        unsigned int flag) // \arg  flag to be tested
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_UDP_IsInterruptMasked */
+/** \brief Test if UDP Interrupt is Masked */
+/**---------------------------------------------------------------------------- */
+__inline int AT91F_UDP_IsInterruptMasked( AT91PS_UDP pUdp,    /* \arg  pointer to a UDP controller */
+                                          unsigned int flag ) /* \arg  flag to be tested */
 {
-        return (AT91F_UDP_GetInterruptMaskStatus(pUdp) & flag);
+    return( AT91F_UDP_GetInterruptMaskStatus( pUdp ) & flag );
 }
 
 /* *****************************************************************************
-                SOFTWARE API FOR AIC
-   ***************************************************************************** */
-#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20]
+*               SOFTWARE API FOR AIC
+***************************************************************************** */
+#define AT91C_AIC_BRANCH_OPCODE    ( ( void ( * )() ) 0xE51FFF20 ) /* ldr, pc, [pc, #-&F20] */
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_ConfigureIt
-//* \brief Interrupt Handler Initialization
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_AIC_ConfigureIt (
-    AT91PS_AIC pAic,  // \arg pointer to the AIC registers
-    unsigned int irq_id,     // \arg interrupt number to initialize
-    unsigned int priority,   // \arg priority to give to the interrupt
-    unsigned int src_type,   // \arg activation and sense of activation
-    void (*newHandler) (void) ) // \arg address of the interrupt handler
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_AIC_ConfigureIt */
+/** \brief Interrupt Handler Initialization */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_AIC_ConfigureIt( AT91PS_AIC pAic,                /* \arg pointer to the AIC registers */
+                                             unsigned int irq_id,            /* \arg interrupt number to initialize */
+                                             unsigned int priority,          /* \arg priority to give to the interrupt */
+                                             unsigned int src_type,          /* \arg activation and sense of activation */
+                                             void ( * newHandler )( void ) ) /* \arg address of the interrupt handler */
 {
     unsigned int oldHandler;
-    unsigned int mask ;
+    unsigned int mask;
 
-    oldHandler = pAic->AIC_SVR[irq_id];
+    oldHandler = pAic->AIC_SVR[ irq_id ];
 
-    mask = 0x1 << irq_id ;
-    //* Disable the interrupt on the interrupt controller
-    pAic->AIC_IDCR = mask ;
-    //* Save the interrupt handler routine pointer and the interrupt priority
-    pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ;
-    //* Store the Source Mode Register
-    pAic->AIC_SMR[irq_id] = src_type | priority  ;
-    //* Clear the interrupt on the interrupt controller
-    pAic->AIC_ICCR = mask ;
+    mask = 0x1 << irq_id;
+    /** Disable the interrupt on the interrupt controller */
+    pAic->AIC_IDCR = mask;
+    /** Save the interrupt handler routine pointer and the interrupt priority */
+    pAic->AIC_SVR[ irq_id ] = ( unsigned int ) newHandler;
+    /** Store the Source Mode Register */
+    pAic->AIC_SMR[ irq_id ] = src_type | priority;
+    /** Clear the interrupt on the interrupt controller */
+    pAic->AIC_ICCR = mask;
 
     return oldHandler;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_EnableIt
-//* \brief Enable corresponding IT number
-//*----------------------------------------------------------------------------
-__inline void AT91F_AIC_EnableIt (
-    AT91PS_AIC pAic,      // \arg pointer to the AIC registers
-    unsigned int irq_id ) // \arg interrupt number to initialize
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_AIC_EnableIt */
+/** \brief Enable corresponding IT number */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_AIC_EnableIt( AT91PS_AIC pAic,      /* \arg pointer to the AIC registers */
+                                  unsigned int irq_id ) /* \arg interrupt number to initialize */
 {
-    //* Enable the interrupt on the interrupt controller
-    pAic->AIC_IECR = 0x1 << irq_id ;
+    /** Enable the interrupt on the interrupt controller */
+    pAic->AIC_IECR = 0x1 << irq_id;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_DisableIt
-//* \brief Disable corresponding IT number
-//*----------------------------------------------------------------------------
-__inline void AT91F_AIC_DisableIt (
-    AT91PS_AIC pAic,      // \arg pointer to the AIC registers
-    unsigned int irq_id ) // \arg interrupt number to initialize
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_AIC_DisableIt */
+/** \brief Disable corresponding IT number */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_AIC_DisableIt( AT91PS_AIC pAic,      /* \arg pointer to the AIC registers */
+                                   unsigned int irq_id ) /* \arg interrupt number to initialize */
 {
     unsigned int mask = 0x1 << irq_id;
-    //* Disable the interrupt on the interrupt controller
-    pAic->AIC_IDCR = mask ;
-    //* Clear the interrupt on the Interrupt Controller ( if one is pending )
-    pAic->AIC_ICCR = mask ;
+
+    /** Disable the interrupt on the interrupt controller */
+    pAic->AIC_IDCR = mask;
+    /** Clear the interrupt on the Interrupt Controller ( if one is pending ) */
+    pAic->AIC_ICCR = mask;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_ClearIt
-//* \brief Clear corresponding IT number
-//*----------------------------------------------------------------------------
-__inline void AT91F_AIC_ClearIt (
-    AT91PS_AIC pAic,     // \arg pointer to the AIC registers
-    unsigned int irq_id) // \arg interrupt number to initialize
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_AIC_ClearIt */
+/** \brief Clear corresponding IT number */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_AIC_ClearIt( AT91PS_AIC pAic,      /* \arg pointer to the AIC registers */
+                                 unsigned int irq_id ) /* \arg interrupt number to initialize */
 {
-    //* Clear the interrupt on the Interrupt Controller ( if one is pending )
-    pAic->AIC_ICCR = (0x1 << irq_id);
+    /** Clear the interrupt on the Interrupt Controller ( if one is pending ) */
+    pAic->AIC_ICCR = ( 0x1 << irq_id );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_AcknowledgeIt
-//* \brief Acknowledge corresponding IT number
-//*----------------------------------------------------------------------------
-__inline void AT91F_AIC_AcknowledgeIt (
-    AT91PS_AIC pAic)     // \arg pointer to the AIC registers
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_AIC_AcknowledgeIt */
+/** \brief Acknowledge corresponding IT number */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_AIC_AcknowledgeIt( AT91PS_AIC pAic ) /* \arg pointer to the AIC registers */
 {
     pAic->AIC_EOICR = pAic->AIC_EOICR;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_SetExceptionVector
-//* \brief Configure vector handler
-//*----------------------------------------------------------------------------
-__inline unsigned int  AT91F_AIC_SetExceptionVector (
-    unsigned int *pVector, // \arg pointer to the AIC registers
-    void (*Handler) () )   // \arg Interrupt Handler
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_AIC_SetExceptionVector */
+/** \brief Configure vector handler */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_AIC_SetExceptionVector( unsigned int * pVector, /* \arg pointer to the AIC registers */
+                                                    void ( * Handler )() )  /* \arg Interrupt Handler */
 {
     unsigned int oldVector = *pVector;
 
-    if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE)
-        *pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE;
+    if( ( unsigned int ) Handler == ( unsigned int ) AT91C_AIC_BRANCH_OPCODE )
+    {
+        *pVector = ( unsigned int ) AT91C_AIC_BRANCH_OPCODE;
+    }
     else
-        *pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000;
+    {
+        *pVector = ( ( ( ( ( unsigned int ) Handler ) - ( ( unsigned int ) pVector ) - 0x8 ) >> 2 ) & 0x00FFFFFF ) | 0xEA000000;
+    }
 
     return oldVector;
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_Trig
-//* \brief Trig an IT
-//*----------------------------------------------------------------------------
-__inline void  AT91F_AIC_Trig (
-    AT91PS_AIC pAic,     // \arg pointer to the AIC registers
-    unsigned int irq_id) // \arg interrupt number
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_AIC_Trig */
+/** \brief Trig an IT */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_AIC_Trig( AT91PS_AIC pAic,      /* \arg pointer to the AIC registers */
+                              unsigned int irq_id ) /* \arg interrupt number */
 {
-    pAic->AIC_ISCR = (0x1 << irq_id) ;
+    pAic->AIC_ISCR = ( 0x1 << irq_id );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_IsActive
-//* \brief Test if an IT is active
-//*----------------------------------------------------------------------------
-__inline unsigned int  AT91F_AIC_IsActive (
-    AT91PS_AIC pAic,     // \arg pointer to the AIC registers
-    unsigned int irq_id) // \arg Interrupt Number
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_AIC_IsActive */
+/** \brief Test if an IT is active */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_AIC_IsActive( AT91PS_AIC pAic,      /* \arg pointer to the AIC registers */
+                                          unsigned int irq_id ) /* \arg Interrupt Number */
 {
-    return (pAic->AIC_ISR & (0x1 << irq_id));
+    return( pAic->AIC_ISR & ( 0x1 << irq_id ) );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_IsPending
-//* \brief Test if an IT is pending
-//*----------------------------------------------------------------------------
-__inline unsigned int  AT91F_AIC_IsPending (
-    AT91PS_AIC pAic,     // \arg pointer to the AIC registers
-    unsigned int irq_id) // \arg Interrupt Number
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_AIC_IsPending */
+/** \brief Test if an IT is pending */
+/**---------------------------------------------------------------------------- */
+__inline unsigned int AT91F_AIC_IsPending( AT91PS_AIC pAic,      /* \arg pointer to the AIC registers */
+                                           unsigned int irq_id ) /* \arg Interrupt Number */
 {
-    return (pAic->AIC_IPR & (0x1 << irq_id));
+    return( pAic->AIC_IPR & ( 0x1 << irq_id ) );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_Open
-//* \brief Set exception vectors and AIC registers to default values
-//*----------------------------------------------------------------------------
-__inline void AT91F_AIC_Open(
-    AT91PS_AIC pAic,        // \arg pointer to the AIC registers
-    void (*IrqHandler) (),  // \arg Default IRQ vector exception
-    void (*FiqHandler) (),  // \arg Default FIQ vector exception
-    void (*DefaultHandler)  (), // \arg Default Handler set in ISR
-    void (*SpuriousHandler) (), // \arg Default Spurious Handler
-    unsigned int protectMode)   // \arg Debug Control Register
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_AIC_Open */
+/** \brief Set exception vectors and AIC registers to default values */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_AIC_Open( AT91PS_AIC pAic,              /* \arg pointer to the AIC registers */
+                              void ( * IrqHandler )(),      /* \arg Default IRQ vector exception */
+                              void ( * FiqHandler )(),      /* \arg Default FIQ vector exception */
+                              void ( * DefaultHandler )(),  /* \arg Default Handler set in ISR */
+                              void ( * SpuriousHandler )(), /* \arg Default Spurious Handler */
+                              unsigned int protectMode )    /* \arg Debug Control Register */
 {
     int i;
 
-    // Disable all interrupts and set IVR to the default handler
-    for (i = 0; i < 32; ++i) {
-        AT91F_AIC_DisableIt(pAic, i);
-        AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE, DefaultHandler);
+    /* Disable all interrupts and set IVR to the default handler */
+    for( i = 0; i < 32; ++i )
+    {
+        AT91F_AIC_DisableIt( pAic, i );
+        AT91F_AIC_ConfigureIt( pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE, DefaultHandler );
     }
 
-    // Set the IRQ exception vector
-    AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler);
-    // Set the Fast Interrupt exception vector
-    AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler);
+    /* Set the IRQ exception vector */
+    AT91F_AIC_SetExceptionVector( ( unsigned int * ) 0x18, IrqHandler );
+    /* Set the Fast Interrupt exception vector */
+    AT91F_AIC_SetExceptionVector( ( unsigned int * ) 0x1C, FiqHandler );
 
-    pAic->AIC_SPU = (unsigned int) SpuriousHandler;
+    pAic->AIC_SPU = ( unsigned int ) SpuriousHandler;
     pAic->AIC_DCR = protectMode;
 }
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  MC
-//*----------------------------------------------------------------------------
-__inline void AT91F_MC_CfgPMC (void)
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_MC_CfgPMC */
+/** \brief Enable Peripheral clock in PMC for  MC */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_MC_CfgPMC( void )
 {
     AT91F_PMC_EnablePeriphClock(
-        AT91C_BASE_PMC, // PIO controller base address
-        ((unsigned int) 1 << AT91C_ID_SYS));
+        AT91C_BASE_PMC, /* PIO controller base address */
+        ( ( unsigned int ) 1 << AT91C_ID_SYS ) );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_DBGU_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  DBGU
-//*----------------------------------------------------------------------------
-__inline void AT91F_DBGU_CfgPMC (void)
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_DBGU_CfgPMC */
+/** \brief Enable Peripheral clock in PMC for  DBGU */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_DBGU_CfgPMC( void )
 {
     AT91F_PMC_EnablePeriphClock(
-        AT91C_BASE_PMC, // PIO controller base address
-        ((unsigned int) 1 << AT91C_ID_SYS));
+        AT91C_BASE_PMC, /* PIO controller base address */
+        ( ( unsigned int ) 1 << AT91C_ID_SYS ) );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_DBGU_CfgPIO
-//* \brief Configure PIO controllers to drive DBGU signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_DBGU_CfgPIO (void)
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_DBGU_CfgPIO */
+/** \brief Configure PIO controllers to drive DBGU signals */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_DBGU_CfgPIO( void )
 {
-    // Configure PIO controllers to periph mode
+    /* Configure PIO controllers to periph mode */
     AT91F_PIO_CfgPeriph(
-        AT91C_BASE_PIOA, // PIO controller base address
-        ((unsigned int) AT91C_PA10_DTXD    ) |
-        ((unsigned int) AT91C_PA9_DRXD    ), // Peripheral A
-        0); // Peripheral B
+        AT91C_BASE_PIOA,                     /* PIO controller base address */
+        ( ( unsigned int ) AT91C_PA10_DTXD ) |
+        ( ( unsigned int ) AT91C_PA9_DRXD ), /* Peripheral A */
+        0 );                                 /* Peripheral B */
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWMC_CH3_CfgPIO
-//* \brief Configure PIO controllers to drive PWMC_CH3 signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_CH3_CfgPIO (void)
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PWMC_CH3_CfgPIO */
+/** \brief Configure PIO controllers to drive PWMC_CH3 signals */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_PWMC_CH3_CfgPIO( void )
 {
-    // Configure PIO controllers to periph mode
+    /* Configure PIO controllers to periph mode */
     AT91F_PIO_CfgPeriph(
-        AT91C_BASE_PIOA, // PIO controller base address
-        0, // Peripheral A
-        ((unsigned int) AT91C_PA14_PWM3    ) |
-        ((unsigned int) AT91C_PA7_PWM3    )); // Peripheral B
+        AT91C_BASE_PIOA,                       /* PIO controller base address */
+        0,                                     /* Peripheral A */
+        ( ( unsigned int ) AT91C_PA14_PWM3 ) |
+        ( ( unsigned int ) AT91C_PA7_PWM3 ) ); /* Peripheral B */
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWMC_CH2_CfgPIO
-//* \brief Configure PIO controllers to drive PWMC_CH2 signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_CH2_CfgPIO (void)
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PWMC_CH2_CfgPIO */
+/** \brief Configure PIO controllers to drive PWMC_CH2 signals */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_PWMC_CH2_CfgPIO( void )
 {
-    // Configure PIO controllers to periph mode
+    /* Configure PIO controllers to periph mode */
     AT91F_PIO_CfgPeriph(
-        AT91C_BASE_PIOA, // PIO controller base address
-        ((unsigned int) AT91C_PA2_PWM2    ), // Peripheral A
-        ((unsigned int) AT91C_PA25_PWM2    ) |
-        ((unsigned int) AT91C_PA13_PWM2    )); // Peripheral B
+        AT91C_BASE_PIOA,                        /* PIO controller base address */
+        ( ( unsigned int ) AT91C_PA2_PWM2 ),    /* Peripheral A */
+        ( ( unsigned int ) AT91C_PA25_PWM2 ) |
+        ( ( unsigned int ) AT91C_PA13_PWM2 ) ); /* Peripheral B */
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWMC_CH1_CfgPIO
-//* \brief Configure PIO controllers to drive PWMC_CH1 signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_CH1_CfgPIO (void)
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PWMC_CH1_CfgPIO */
+/** \brief Configure PIO controllers to drive PWMC_CH1 signals */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_PWMC_CH1_CfgPIO( void )
 {
-    // Configure PIO controllers to periph mode
+    /* Configure PIO controllers to periph mode */
     AT91F_PIO_CfgPeriph(
-        AT91C_BASE_PIOA, // PIO controller base address
-        ((unsigned int) AT91C_PA1_PWM1    ), // Peripheral A
-        ((unsigned int) AT91C_PA24_PWM1    ) |
-        ((unsigned int) AT91C_PA12_PWM1    )); // Peripheral B
+        AT91C_BASE_PIOA,                        /* PIO controller base address */
+        ( ( unsigned int ) AT91C_PA1_PWM1 ),    /* Peripheral A */
+        ( ( unsigned int ) AT91C_PA24_PWM1 ) |
+        ( ( unsigned int ) AT91C_PA12_PWM1 ) ); /* Peripheral B */
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWMC_CH0_CfgPIO
-//* \brief Configure PIO controllers to drive PWMC_CH0 signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_CH0_CfgPIO (void)
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PWMC_CH0_CfgPIO */
+/** \brief Configure PIO controllers to drive PWMC_CH0 signals */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_PWMC_CH0_CfgPIO( void )
 {
-    // Configure PIO controllers to periph mode
+    /* Configure PIO controllers to periph mode */
     AT91F_PIO_CfgPeriph(
-        AT91C_BASE_PIOA, // PIO controller base address
-        ((unsigned int) AT91C_PA0_PWM0    ), // Peripheral A
-        ((unsigned int) AT91C_PA23_PWM0    ) |
-        ((unsigned int) AT91C_PA11_PWM0    )); // Peripheral B
+        AT91C_BASE_PIOA,                        /* PIO controller base address */
+        ( ( unsigned int ) AT91C_PA0_PWM0 ),    /* Peripheral A */
+        ( ( unsigned int ) AT91C_PA23_PWM0 ) |
+        ( ( unsigned int ) AT91C_PA11_PWM0 ) ); /* Peripheral B */
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  SSC
-//*----------------------------------------------------------------------------
-__inline void AT91F_SSC_CfgPMC (void)
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_SSC_CfgPMC */
+/** \brief Enable Peripheral clock in PMC for  SSC */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_SSC_CfgPMC( void )
 {
     AT91F_PMC_EnablePeriphClock(
-        AT91C_BASE_PMC, // PIO controller base address
-        ((unsigned int) 1 << AT91C_ID_SSC));
+        AT91C_BASE_PMC, /* PIO controller base address */
+        ( ( unsigned int ) 1 << AT91C_ID_SSC ) );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_CfgPIO
-//* \brief Configure PIO controllers to drive SSC signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_SSC_CfgPIO (void)
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_SSC_CfgPIO */
+/** \brief Configure PIO controllers to drive SSC signals */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_SSC_CfgPIO( void )
 {
-    // Configure PIO controllers to periph mode
+    /* Configure PIO controllers to periph mode */
     AT91F_PIO_CfgPeriph(
-        AT91C_BASE_PIOA, // PIO controller base address
-        ((unsigned int) AT91C_PA17_TD      ) |
-        ((unsigned int) AT91C_PA15_TF      ) |
-        ((unsigned int) AT91C_PA19_RK      ) |
-        ((unsigned int) AT91C_PA18_RD      ) |
-        ((unsigned int) AT91C_PA20_RF      ) |
-        ((unsigned int) AT91C_PA16_TK      ), // Peripheral A
-        0); // Peripheral B
+        AT91C_BASE_PIOA, /* PIO controller base address */
+        ( ( unsigned int ) AT91C_PA17_TD ) |
+        ( ( unsigned int ) AT91C_PA15_TF ) |
+        ( ( unsigned int ) AT91C_PA19_RK ) |
+        ( ( unsigned int ) AT91C_PA18_RD ) |
+        ( ( unsigned int ) AT91C_PA20_RF ) |
+        ( ( unsigned int ) AT91C_PA16_TK ), /* Peripheral A */
+        0 );                                /* Peripheral B */
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  SPI
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_CfgPMC (void)
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_SPI_CfgPMC */
+/** \brief Enable Peripheral clock in PMC for  SPI */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_SPI_CfgPMC( void )
 {
     AT91F_PMC_EnablePeriphClock(
-        AT91C_BASE_PMC, // PIO controller base address
-        ((unsigned int) 1 << AT91C_ID_SPI));
+        AT91C_BASE_PMC, /* PIO controller base address */
+        ( ( unsigned int ) 1 << AT91C_ID_SPI ) );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_CfgPIO
-//* \brief Configure PIO controllers to drive SPI signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_CfgPIO (void)
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_SPI_CfgPIO */
+/** \brief Configure PIO controllers to drive SPI signals */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_SPI_CfgPIO( void )
 {
-    // Configure PIO controllers to periph mode
+    /* Configure PIO controllers to periph mode */
     AT91F_PIO_CfgPeriph(
-        AT91C_BASE_PIOA, // PIO controller base address
-        ((unsigned int) AT91C_PA11_NPCS0   ) |
-        ((unsigned int) AT91C_PA13_MOSI    ) |
-        ((unsigned int) AT91C_PA31_NPCS1   ) |
-        ((unsigned int) AT91C_PA12_MISO    ) |
-        ((unsigned int) AT91C_PA14_SPCK    ), // Peripheral A
-        ((unsigned int) AT91C_PA9_NPCS1   ) |
-        ((unsigned int) AT91C_PA30_NPCS2   ) |
-        ((unsigned int) AT91C_PA10_NPCS2   ) |
-        ((unsigned int) AT91C_PA22_NPCS3   ) |
-        ((unsigned int) AT91C_PA3_NPCS3   ) |
-        ((unsigned int) AT91C_PA5_NPCS3   )); // Peripheral B
+        AT91C_BASE_PIOA, /* PIO controller base address */
+        ( ( unsigned int ) AT91C_PA11_NPCS0 ) |
+        ( ( unsigned int ) AT91C_PA13_MOSI ) |
+        ( ( unsigned int ) AT91C_PA31_NPCS1 ) |
+        ( ( unsigned int ) AT91C_PA12_MISO ) |
+        ( ( unsigned int ) AT91C_PA14_SPCK ), /* Peripheral A */
+        ( ( unsigned int ) AT91C_PA9_NPCS1 ) |
+        ( ( unsigned int ) AT91C_PA30_NPCS2 ) |
+        ( ( unsigned int ) AT91C_PA10_NPCS2 ) |
+        ( ( unsigned int ) AT91C_PA22_NPCS3 ) |
+        ( ( unsigned int ) AT91C_PA3_NPCS3 ) |
+        ( ( unsigned int ) AT91C_PA5_NPCS3 ) ); /* Peripheral B */
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWMC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  PWMC
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_CfgPMC (void)
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PWMC_CfgPMC */
+/** \brief Enable Peripheral clock in PMC for  PWMC */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_PWMC_CfgPMC( void )
 {
     AT91F_PMC_EnablePeriphClock(
-        AT91C_BASE_PMC, // PIO controller base address
-        ((unsigned int) 1 << AT91C_ID_PWMC));
+        AT91C_BASE_PMC, /* PIO controller base address */
+        ( ( unsigned int ) 1 << AT91C_ID_PWMC ) );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TC2_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  TC2
-//*----------------------------------------------------------------------------
-__inline void AT91F_TC2_CfgPMC (void)
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_TC2_CfgPMC */
+/** \brief Enable Peripheral clock in PMC for  TC2 */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_TC2_CfgPMC( void )
 {
     AT91F_PMC_EnablePeriphClock(
-        AT91C_BASE_PMC, // PIO controller base address
-        ((unsigned int) 1 << AT91C_ID_TC2));
+        AT91C_BASE_PMC, /* PIO controller base address */
+        ( ( unsigned int ) 1 << AT91C_ID_TC2 ) );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TC2_CfgPIO
-//* \brief Configure PIO controllers to drive TC2 signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_TC2_CfgPIO (void)
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_TC2_CfgPIO */
+/** \brief Configure PIO controllers to drive TC2 signals */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_TC2_CfgPIO( void )
 {
-    // Configure PIO controllers to periph mode
+    /* Configure PIO controllers to periph mode */
     AT91F_PIO_CfgPeriph(
-        AT91C_BASE_PIOA, // PIO controller base address
-        0, // Peripheral A
-        ((unsigned int) AT91C_PA26_TIOA2   ) |
-        ((unsigned int) AT91C_PA27_TIOB2   ) |
-        ((unsigned int) AT91C_PA29_TCLK2   )); // Peripheral B
+        AT91C_BASE_PIOA, /* PIO controller base address */
+        0,               /* Peripheral A */
+        ( ( unsigned int ) AT91C_PA26_TIOA2 ) |
+        ( ( unsigned int ) AT91C_PA27_TIOB2 ) |
+        ( ( unsigned int ) AT91C_PA29_TCLK2 ) ); /* Peripheral B */
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TC1_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  TC1
-//*----------------------------------------------------------------------------
-__inline void AT91F_TC1_CfgPMC (void)
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_TC1_CfgPMC */
+/** \brief Enable Peripheral clock in PMC for  TC1 */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_TC1_CfgPMC( void )
 {
     AT91F_PMC_EnablePeriphClock(
-        AT91C_BASE_PMC, // PIO controller base address
-        ((unsigned int) 1 << AT91C_ID_TC1));
+        AT91C_BASE_PMC, /* PIO controller base address */
+        ( ( unsigned int ) 1 << AT91C_ID_TC1 ) );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TC1_CfgPIO
-//* \brief Configure PIO controllers to drive TC1 signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_TC1_CfgPIO (void)
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_TC1_CfgPIO */
+/** \brief Configure PIO controllers to drive TC1 signals */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_TC1_CfgPIO( void )
 {
-    // Configure PIO controllers to periph mode
+    /* Configure PIO controllers to periph mode */
     AT91F_PIO_CfgPeriph(
-        AT91C_BASE_PIOA, // PIO controller base address
-        0, // Peripheral A
-        ((unsigned int) AT91C_PA15_TIOA1   ) |
-        ((unsigned int) AT91C_PA16_TIOB1   ) |
-        ((unsigned int) AT91C_PA28_TCLK1   )); // Peripheral B
+        AT91C_BASE_PIOA, /* PIO controller base address */
+        0,               /* Peripheral A */
+        ( ( unsigned int ) AT91C_PA15_TIOA1 ) |
+        ( ( unsigned int ) AT91C_PA16_TIOB1 ) |
+        ( ( unsigned int ) AT91C_PA28_TCLK1 ) ); /* Peripheral B */
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TC0_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  TC0
-//*----------------------------------------------------------------------------
-__inline void AT91F_TC0_CfgPMC (void)
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_TC0_CfgPMC */
+/** \brief Enable Peripheral clock in PMC for  TC0 */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_TC0_CfgPMC( void )
 {
     AT91F_PMC_EnablePeriphClock(
-        AT91C_BASE_PMC, // PIO controller base address
-        ((unsigned int) 1 << AT91C_ID_TC0));
+        AT91C_BASE_PMC, /* PIO controller base address */
+        ( ( unsigned int ) 1 << AT91C_ID_TC0 ) );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TC0_CfgPIO
-//* \brief Configure PIO controllers to drive TC0 signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_TC0_CfgPIO (void)
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_TC0_CfgPIO */
+/** \brief Configure PIO controllers to drive TC0 signals */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_TC0_CfgPIO( void )
 {
-    // Configure PIO controllers to periph mode
+    /* Configure PIO controllers to periph mode */
     AT91F_PIO_CfgPeriph(
-        AT91C_BASE_PIOA, // PIO controller base address
-        0, // Peripheral A
-        ((unsigned int) AT91C_PA0_TIOA0   ) |
-        ((unsigned int) AT91C_PA1_TIOB0   ) |
-        ((unsigned int) AT91C_PA4_TCLK0   )); // Peripheral B
+        AT91C_BASE_PIOA, /* PIO controller base address */
+        0,               /* Peripheral A */
+        ( ( unsigned int ) AT91C_PA0_TIOA0 ) |
+        ( ( unsigned int ) AT91C_PA1_TIOB0 ) |
+        ( ( unsigned int ) AT91C_PA4_TCLK0 ) ); /* Peripheral B */
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  PMC
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_CfgPMC (void)
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_CfgPMC */
+/** \brief Enable Peripheral clock in PMC for  PMC */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_PMC_CfgPMC( void )
 {
     AT91F_PMC_EnablePeriphClock(
-        AT91C_BASE_PMC, // PIO controller base address
-        ((unsigned int) 1 << AT91C_ID_SYS));
+        AT91C_BASE_PMC, /* PIO controller base address */
+        ( ( unsigned int ) 1 << AT91C_ID_SYS ) );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_CfgPIO
-//* \brief Configure PIO controllers to drive PMC signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_CfgPIO (void)
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_CfgPIO */
+/** \brief Configure PIO controllers to drive PMC signals */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_PMC_CfgPIO( void )
 {
-    // Configure PIO controllers to periph mode
+    /* Configure PIO controllers to periph mode */
     AT91F_PIO_CfgPeriph(
-        AT91C_BASE_PIOA, // PIO controller base address
-        0, // Peripheral A
-        ((unsigned int) AT91C_PA17_PCK1    ) |
-        ((unsigned int) AT91C_PA21_PCK1    ) |
-        ((unsigned int) AT91C_PA31_PCK2    ) |
-        ((unsigned int) AT91C_PA18_PCK2    ) |
-        ((unsigned int) AT91C_PA6_PCK0    )); // Peripheral B
+        AT91C_BASE_PIOA, /* PIO controller base address */
+        0,               /* Peripheral A */
+        ( ( unsigned int ) AT91C_PA17_PCK1 ) |
+        ( ( unsigned int ) AT91C_PA21_PCK1 ) |
+        ( ( unsigned int ) AT91C_PA31_PCK2 ) |
+        ( ( unsigned int ) AT91C_PA18_PCK2 ) |
+        ( ( unsigned int ) AT91C_PA6_PCK0 ) ); /* Peripheral B */
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  ADC
-//*----------------------------------------------------------------------------
-__inline void AT91F_ADC_CfgPMC (void)
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_ADC_CfgPMC */
+/** \brief Enable Peripheral clock in PMC for  ADC */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_ADC_CfgPMC( void )
 {
     AT91F_PMC_EnablePeriphClock(
-        AT91C_BASE_PMC, // PIO controller base address
-        ((unsigned int) 1 << AT91C_ID_ADC));
+        AT91C_BASE_PMC, /* PIO controller base address */
+        ( ( unsigned int ) 1 << AT91C_ID_ADC ) );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_CfgPIO
-//* \brief Configure PIO controllers to drive ADC signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_ADC_CfgPIO (void)
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_ADC_CfgPIO */
+/** \brief Configure PIO controllers to drive ADC signals */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_ADC_CfgPIO( void )
 {
-    // Configure PIO controllers to periph mode
+    /* Configure PIO controllers to periph mode */
     AT91F_PIO_CfgPeriph(
-        AT91C_BASE_PIOA, // PIO controller base address
-        0, // Peripheral A
-        ((unsigned int) AT91C_PA8_ADTRG   )); // Peripheral B
+        AT91C_BASE_PIOA,                        /* PIO controller base address */
+        0,                                      /* Peripheral A */
+        ( ( unsigned int ) AT91C_PA8_ADTRG ) ); /* Peripheral B */
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIOA_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  PIOA
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIOA_CfgPMC (void)
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIOA_CfgPMC */
+/** \brief Enable Peripheral clock in PMC for  PIOA */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_PIOA_CfgPMC( void )
 {
     AT91F_PMC_EnablePeriphClock(
-        AT91C_BASE_PMC, // PIO controller base address
-        ((unsigned int) 1 << AT91C_ID_PIOA));
+        AT91C_BASE_PMC, /* PIO controller base address */
+        ( ( unsigned int ) 1 << AT91C_ID_PIOA ) );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TWI_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  TWI
-//*----------------------------------------------------------------------------
-__inline void AT91F_TWI_CfgPMC (void)
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_TWI_CfgPMC */
+/** \brief Enable Peripheral clock in PMC for  TWI */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_TWI_CfgPMC( void )
 {
     AT91F_PMC_EnablePeriphClock(
-        AT91C_BASE_PMC, // PIO controller base address
-        ((unsigned int) 1 << AT91C_ID_TWI));
+        AT91C_BASE_PMC, /* PIO controller base address */
+        ( ( unsigned int ) 1 << AT91C_ID_TWI ) );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TWI_CfgPIO
-//* \brief Configure PIO controllers to drive TWI signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_TWI_CfgPIO (void)
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_TWI_CfgPIO */
+/** \brief Configure PIO controllers to drive TWI signals */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_TWI_CfgPIO( void )
 {
-    // Configure PIO controllers to periph mode
+    /* Configure PIO controllers to periph mode */
     AT91F_PIO_CfgPeriph(
-        AT91C_BASE_PIOA, // PIO controller base address
-        ((unsigned int) AT91C_PA3_TWD     ) |
-        ((unsigned int) AT91C_PA4_TWCK    ), // Peripheral A
-        0); // Peripheral B
+        AT91C_BASE_PIOA,                     /* PIO controller base address */
+        ( ( unsigned int ) AT91C_PA3_TWD ) |
+        ( ( unsigned int ) AT91C_PA4_TWCK ), /* Peripheral A */
+        0 );                                 /* Peripheral B */
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US1_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  US1
-//*----------------------------------------------------------------------------
-__inline void AT91F_US1_CfgPMC (void)
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_US1_CfgPMC */
+/** \brief Enable Peripheral clock in PMC for  US1 */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_US1_CfgPMC( void )
 {
     AT91F_PMC_EnablePeriphClock(
-        AT91C_BASE_PMC, // PIO controller base address
-        ((unsigned int) 1 << AT91C_ID_US1));
+        AT91C_BASE_PMC, /* PIO controller base address */
+        ( ( unsigned int ) 1 << AT91C_ID_US1 ) );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US1_CfgPIO
-//* \brief Configure PIO controllers to drive US1 signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_US1_CfgPIO (void)
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_US1_CfgPIO */
+/** \brief Configure PIO controllers to drive US1 signals */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_US1_CfgPIO( void )
 {
-    // Configure PIO controllers to periph mode
+    /* Configure PIO controllers to periph mode */
     AT91F_PIO_CfgPeriph(
-        AT91C_BASE_PIOA, // PIO controller base address
-        ((unsigned int) AT91C_PA21_RXD1    ) |
-        ((unsigned int) AT91C_PA27_DTR1    ) |
-        ((unsigned int) AT91C_PA26_DCD1    ) |
-        ((unsigned int) AT91C_PA22_TXD1    ) |
-        ((unsigned int) AT91C_PA24_RTS1    ) |
-        ((unsigned int) AT91C_PA23_SCK1    ) |
-        ((unsigned int) AT91C_PA28_DSR1    ) |
-        ((unsigned int) AT91C_PA29_RI1     ) |
-        ((unsigned int) AT91C_PA25_CTS1    ), // Peripheral A
-        0); // Peripheral B
+        AT91C_BASE_PIOA, /* PIO controller base address */
+        ( ( unsigned int ) AT91C_PA21_RXD1 ) |
+        ( ( unsigned int ) AT91C_PA27_DTR1 ) |
+        ( ( unsigned int ) AT91C_PA26_DCD1 ) |
+        ( ( unsigned int ) AT91C_PA22_TXD1 ) |
+        ( ( unsigned int ) AT91C_PA24_RTS1 ) |
+        ( ( unsigned int ) AT91C_PA23_SCK1 ) |
+        ( ( unsigned int ) AT91C_PA28_DSR1 ) |
+        ( ( unsigned int ) AT91C_PA29_RI1 ) |
+        ( ( unsigned int ) AT91C_PA25_CTS1 ), /* Peripheral A */
+        0 );                                  /* Peripheral B */
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US0_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  US0
-//*----------------------------------------------------------------------------
-__inline void AT91F_US0_CfgPMC (void)
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_US0_CfgPMC */
+/** \brief Enable Peripheral clock in PMC for  US0 */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_US0_CfgPMC( void )
 {
     AT91F_PMC_EnablePeriphClock(
-        AT91C_BASE_PMC, // PIO controller base address
-        ((unsigned int) 1 << AT91C_ID_US0));
+        AT91C_BASE_PMC, /* PIO controller base address */
+        ( ( unsigned int ) 1 << AT91C_ID_US0 ) );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US0_CfgPIO
-//* \brief Configure PIO controllers to drive US0 signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_US0_CfgPIO (void)
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_US0_CfgPIO */
+/** \brief Configure PIO controllers to drive US0 signals */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_US0_CfgPIO( void )
 {
-    // Configure PIO controllers to periph mode
+    /* Configure PIO controllers to periph mode */
     AT91F_PIO_CfgPeriph(
-        AT91C_BASE_PIOA, // PIO controller base address
-        ((unsigned int) AT91C_PA5_RXD0    ) |
-        ((unsigned int) AT91C_PA6_TXD0    ) |
-        ((unsigned int) AT91C_PA7_RTS0    ) |
-        ((unsigned int) AT91C_PA8_CTS0    ), // Peripheral A
-        ((unsigned int) AT91C_PA2_SCK0    )); // Peripheral B
+        AT91C_BASE_PIOA, /* PIO controller base address */
+        ( ( unsigned int ) AT91C_PA5_RXD0 ) |
+        ( ( unsigned int ) AT91C_PA6_TXD0 ) |
+        ( ( unsigned int ) AT91C_PA7_RTS0 ) |
+        ( ( unsigned int ) AT91C_PA8_CTS0 ),   /* Peripheral A */
+        ( ( unsigned int ) AT91C_PA2_SCK0 ) ); /* Peripheral B */
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  UDP
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_CfgPMC (void)
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_UDP_CfgPMC */
+/** \brief Enable Peripheral clock in PMC for  UDP */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_UDP_CfgPMC( void )
 {
     AT91F_PMC_EnablePeriphClock(
-        AT91C_BASE_PMC, // PIO controller base address
-        ((unsigned int) 1 << AT91C_ID_UDP));
+        AT91C_BASE_PMC, /* PIO controller base address */
+        ( ( unsigned int ) 1 << AT91C_ID_UDP ) );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  AIC
-//*----------------------------------------------------------------------------
-__inline void AT91F_AIC_CfgPMC (void)
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_AIC_CfgPMC */
+/** \brief Enable Peripheral clock in PMC for  AIC */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_AIC_CfgPMC( void )
 {
     AT91F_PMC_EnablePeriphClock(
-        AT91C_BASE_PMC, // PIO controller base address
-        ((unsigned int) 1 << AT91C_ID_IRQ0) |
-        ((unsigned int) 1 << AT91C_ID_FIQ) |
-        ((unsigned int) 1 << AT91C_ID_IRQ1));
+        AT91C_BASE_PMC, /* PIO controller base address */
+        ( ( unsigned int ) 1 << AT91C_ID_IRQ0 ) |
+        ( ( unsigned int ) 1 << AT91C_ID_FIQ ) |
+        ( ( unsigned int ) 1 << AT91C_ID_IRQ1 ) );
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_CfgPIO
-//* \brief Configure PIO controllers to drive AIC signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_AIC_CfgPIO (void)
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_AIC_CfgPIO */
+/** \brief Configure PIO controllers to drive AIC signals */
+/**---------------------------------------------------------------------------- */
+__inline void AT91F_AIC_CfgPIO( void )
 {
-    // Configure PIO controllers to periph mode
+    /* Configure PIO controllers to periph mode */
     AT91F_PIO_CfgPeriph(
-        AT91C_BASE_PIOA, // PIO controller base address
-        ((unsigned int) AT91C_PA30_IRQ1    ), // Peripheral A
-        ((unsigned int) AT91C_PA20_IRQ0    ) |
-        ((unsigned int) AT91C_PA19_FIQ     )); // Peripheral B
+        AT91C_BASE_PIOA,                       /* PIO controller base address */
+        ( ( unsigned int ) AT91C_PA30_IRQ1 ),  /* Peripheral A */
+        ( ( unsigned int ) AT91C_PA20_IRQ0 ) |
+        ( ( unsigned int ) AT91C_PA19_FIQ ) ); /* Peripheral B */
 }
 
 #endif // lib_AT91SAM7S64_H
diff --git a/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X128.h b/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X128.h
index 26afc9411..61fbb1f79 100644
--- a/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X128.h
+++ b/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X128.h
@@ -1,1469 +1,1396 @@
-//* ----------------------------------------------------------------------------
-//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
-//* ----------------------------------------------------------------------------
-//* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
-//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
-//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
-//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
-//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//* ----------------------------------------------------------------------------
-//* File Name           : lib_AT91SAM7X128.h
-//* Object              : AT91SAM7X128 inlined functions
-//* Generated           : AT91 SW Application Group  05/20/2005 (16:22:23)
-//*
-//* CVS Reference       : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003//
-//* CVS Reference       : /lib_pmc_SAM7X.h/1.1/Tue Feb  1 08:32:10 2005//
-//* CVS Reference       : /lib_VREG_6085B.h/1.1/Tue Feb  1 16:20:47 2005//
-//* CVS Reference       : /lib_rstc_6098A.h/1.1/Wed Oct  6 10:39:20 2004//
-//* CVS Reference       : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003//
-//* CVS Reference       : /lib_wdtc_6080A.h/1.1/Wed Oct  6 10:38:30 2004//
-//* CVS Reference       : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002//
-//* CVS Reference       : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003//
-//* CVS Reference       : /lib_pitc_6079A.h/1.2/Tue Nov  9 14:43:56 2004//
-//* CVS Reference       : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005//
-//* CVS Reference       : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005//
-//* CVS Reference       : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004//
-//* CVS Reference       : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003//
-//* CVS Reference       : /lib_rttc_6081A.h/1.1/Wed Oct  6 10:39:38 2004//
-//* CVS Reference       : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005//
-//* CVS Reference       : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005//
-//* CVS Reference       : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//
-//* CVS Reference       : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004//
-//* CVS Reference       : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003//
-//* CVS Reference       : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003//
-//* CVS Reference       : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//
-//* CVS Reference       : /lib_pdc.h/1.2/Tue Jul  2 13:29:40 2002//
-//* ----------------------------------------------------------------------------
+/** ---------------------------------------------------------------------------- */
+/**         ATMEL Microcontroller Software Support  -  ROUSSET  - */
+/** ---------------------------------------------------------------------------- */
+/** DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
+/** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/** MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
+/** DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
+/** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/** LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
+/** OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
+/** LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
+/** NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/** EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
+/** ---------------------------------------------------------------------------- */
+/** File Name           : lib_AT91SAM7X128.h */
+/** Object              : AT91SAM7X128 inlined functions */
+/** Generated           : AT91 SW Application Group  05/20/2005 (16:22:23) */
+/** */
+/** CVS Reference       : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003// */
+/** CVS Reference       : /lib_pmc_SAM7X.h/1.1/Tue Feb  1 08:32:10 2005// */
+/** CVS Reference       : /lib_VREG_6085B.h/1.1/Tue Feb  1 16:20:47 2005// */
+/** CVS Reference       : /lib_rstc_6098A.h/1.1/Wed Oct  6 10:39:20 2004// */
+/** CVS Reference       : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// */
+/** CVS Reference       : /lib_wdtc_6080A.h/1.1/Wed Oct  6 10:38:30 2004// */
+/** CVS Reference       : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002// */
+/** CVS Reference       : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003// */
+/** CVS Reference       : /lib_pitc_6079A.h/1.2/Tue Nov  9 14:43:56 2004// */
+/** CVS Reference       : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005// */
+/** CVS Reference       : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005// */
+/** CVS Reference       : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004// */
+/** CVS Reference       : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003// */
+/** CVS Reference       : /lib_rttc_6081A.h/1.1/Wed Oct  6 10:39:38 2004// */
+/** CVS Reference       : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005// */
+/** CVS Reference       : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005// */
+/** CVS Reference       : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// */
+/** CVS Reference       : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004// */
+/** CVS Reference       : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// */
+/** CVS Reference       : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003// */
+/** CVS Reference       : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// */
+/** CVS Reference       : /lib_pdc.h/1.2/Tue Jul  2 13:29:40 2002// */
+/** ---------------------------------------------------------------------------- */
 
 #ifndef lib_AT91SAM7X128_H
-#define lib_AT91SAM7X128_H
+    #define lib_AT91SAM7X128_H
 
 /* *****************************************************************************
-                SOFTWARE API FOR AIC
-   ***************************************************************************** */
-#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20]
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_ConfigureIt
-//* \brief Interrupt Handler Initialization
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_AIC_ConfigureIt (
-    AT91PS_AIC pAic,  // \arg pointer to the AIC registers
-    unsigned int irq_id,     // \arg interrupt number to initialize
-    unsigned int priority,   // \arg priority to give to the interrupt
-    unsigned int src_type,   // \arg activation and sense of activation
-    void (*newHandler) (void) ) // \arg address of the interrupt handler
-{
-    unsigned int oldHandler;
-    unsigned int mask ;
-
-    oldHandler = pAic->AIC_SVR[irq_id];
-
-    mask = 0x1 << irq_id ;
-    //* Disable the interrupt on the interrupt controller
-    pAic->AIC_IDCR = mask ;
-    //* Save the interrupt handler routine pointer and the interrupt priority
-    pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ;
-    //* Store the Source Mode Register
-    pAic->AIC_SMR[irq_id] = src_type | priority  ;
-    //* Clear the interrupt on the interrupt controller
-    pAic->AIC_ICCR = mask ;
-
-    return oldHandler;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_EnableIt
-//* \brief Enable corresponding IT number
-//*----------------------------------------------------------------------------
-__inline void AT91F_AIC_EnableIt (
-    AT91PS_AIC pAic,      // \arg pointer to the AIC registers
-    unsigned int irq_id ) // \arg interrupt number to initialize
-{
-    //* Enable the interrupt on the interrupt controller
-    pAic->AIC_IECR = 0x1 << irq_id ;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_DisableIt
-//* \brief Disable corresponding IT number
-//*----------------------------------------------------------------------------
-__inline void AT91F_AIC_DisableIt (
-    AT91PS_AIC pAic,      // \arg pointer to the AIC registers
-    unsigned int irq_id ) // \arg interrupt number to initialize
-{
-    unsigned int mask = 0x1 << irq_id;
-    //* Disable the interrupt on the interrupt controller
-    pAic->AIC_IDCR = mask ;
-    //* Clear the interrupt on the Interrupt Controller ( if one is pending )
-    pAic->AIC_ICCR = mask ;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_ClearIt
-//* \brief Clear corresponding IT number
-//*----------------------------------------------------------------------------
-__inline void AT91F_AIC_ClearIt (
-    AT91PS_AIC pAic,     // \arg pointer to the AIC registers
-    unsigned int irq_id) // \arg interrupt number to initialize
-{
-    //* Clear the interrupt on the Interrupt Controller ( if one is pending )
-    pAic->AIC_ICCR = (0x1 << irq_id);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_AcknowledgeIt
-//* \brief Acknowledge corresponding IT number
-//*----------------------------------------------------------------------------
-__inline void AT91F_AIC_AcknowledgeIt (
-    AT91PS_AIC pAic)     // \arg pointer to the AIC registers
-{
-    pAic->AIC_EOICR = pAic->AIC_EOICR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_SetExceptionVector
-//* \brief Configure vector handler
-//*----------------------------------------------------------------------------
-__inline unsigned int  AT91F_AIC_SetExceptionVector (
-    unsigned int *pVector, // \arg pointer to the AIC registers
-    void (*Handler) () )   // \arg Interrupt Handler
-{
-    unsigned int oldVector = *pVector;
-
-    if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE)
-        *pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE;
-    else
-        *pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000;
-
-    return oldVector;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_Trig
-//* \brief Trig an IT
-//*----------------------------------------------------------------------------
-__inline void  AT91F_AIC_Trig (
-    AT91PS_AIC pAic,     // \arg pointer to the AIC registers
-    unsigned int irq_id) // \arg interrupt number
-{
-    pAic->AIC_ISCR = (0x1 << irq_id) ;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_IsActive
-//* \brief Test if an IT is active
-//*----------------------------------------------------------------------------
-__inline unsigned int  AT91F_AIC_IsActive (
-    AT91PS_AIC pAic,     // \arg pointer to the AIC registers
-    unsigned int irq_id) // \arg Interrupt Number
-{
-    return (pAic->AIC_ISR & (0x1 << irq_id));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_IsPending
-//* \brief Test if an IT is pending
-//*----------------------------------------------------------------------------
-__inline unsigned int  AT91F_AIC_IsPending (
-    AT91PS_AIC pAic,     // \arg pointer to the AIC registers
-    unsigned int irq_id) // \arg Interrupt Number
-{
-    return (pAic->AIC_IPR & (0x1 << irq_id));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_Open
-//* \brief Set exception vectors and AIC registers to default values
-//*----------------------------------------------------------------------------
-__inline void AT91F_AIC_Open(
-    AT91PS_AIC pAic,        // \arg pointer to the AIC registers
-    void (*IrqHandler) (),  // \arg Default IRQ vector exception
-    void (*FiqHandler) (),  // \arg Default FIQ vector exception
-    void (*DefaultHandler)  (), // \arg Default Handler set in ISR
-    void (*SpuriousHandler) (), // \arg Default Spurious Handler
-    unsigned int protectMode)   // \arg Debug Control Register
-{
-    int i;
-
-    // Disable all interrupts and set IVR to the default handler
-    for (i = 0; i < 32; ++i) {
-        AT91F_AIC_DisableIt(pAic, i);
-        AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_HIGH_LEVEL, DefaultHandler);
-    }
-
-    // Set the IRQ exception vector
-    AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler);
-    // Set the Fast Interrupt exception vector
-    AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler);
-
-    pAic->AIC_SPU = (unsigned int) SpuriousHandler;
-    pAic->AIC_DCR = protectMode;
-}
-/* *****************************************************************************
-                SOFTWARE API FOR PDC
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_SetNextRx
-//* \brief Set the next receive transfer descriptor
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_SetNextRx (
-    AT91PS_PDC pPDC,     // \arg pointer to a PDC controller
-    char *address,       // \arg address to the next bloc to be received
-    unsigned int bytes)  // \arg number of bytes to be received
-{
-    pPDC->PDC_RNPR = (unsigned int) address;
-    pPDC->PDC_RNCR = bytes;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_SetNextTx
-//* \brief Set the next transmit transfer descriptor
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_SetNextTx (
-    AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
-    char *address,         // \arg address to the next bloc to be transmitted
-    unsigned int bytes)    // \arg number of bytes to be transmitted
-{
-    pPDC->PDC_TNPR = (unsigned int) address;
-    pPDC->PDC_TNCR = bytes;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_SetRx
-//* \brief Set the receive transfer descriptor
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_SetRx (
-    AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
-    char *address,         // \arg address to the next bloc to be received
-    unsigned int bytes)    // \arg number of bytes to be received
-{
-    pPDC->PDC_RPR = (unsigned int) address;
-    pPDC->PDC_RCR = bytes;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_SetTx
-//* \brief Set the transmit transfer descriptor
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_SetTx (
-    AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
-    char *address,         // \arg address to the next bloc to be transmitted
-    unsigned int bytes)    // \arg number of bytes to be transmitted
-{
-    pPDC->PDC_TPR = (unsigned int) address;
-    pPDC->PDC_TCR = bytes;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_EnableTx
-//* \brief Enable transmit
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_EnableTx (
-    AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-    pPDC->PDC_PTCR = AT91C_PDC_TXTEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_EnableRx
-//* \brief Enable receive
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_EnableRx (
-    AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-    pPDC->PDC_PTCR = AT91C_PDC_RXTEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_DisableTx
-//* \brief Disable transmit
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_DisableTx (
-    AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-    pPDC->PDC_PTCR = AT91C_PDC_TXTDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_DisableRx
-//* \brief Disable receive
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_DisableRx (
-    AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-    pPDC->PDC_PTCR = AT91C_PDC_RXTDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_IsTxEmpty
-//* \brief Test if the current transfer descriptor has been sent
-//*----------------------------------------------------------------------------
-__inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete
-    AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-    return !(pPDC->PDC_TCR);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_IsNextTxEmpty
-//* \brief Test if the next transfer descriptor has been moved to the current td
-//*----------------------------------------------------------------------------
-__inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete
-    AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-    return !(pPDC->PDC_TNCR);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_IsRxEmpty
-//* \brief Test if the current transfer descriptor has been filled
-//*----------------------------------------------------------------------------
-__inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete
-    AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-    return !(pPDC->PDC_RCR);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_IsNextRxEmpty
-//* \brief Test if the next transfer descriptor has been moved to the current td
-//*----------------------------------------------------------------------------
-__inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete
-    AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-    return !(pPDC->PDC_RNCR);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_Open
-//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_Open (
-    AT91PS_PDC pPDC)       // \arg pointer to a PDC controller
-{
-    //* Disable the RX and TX PDC transfer requests
-    AT91F_PDC_DisableRx(pPDC);
-    AT91F_PDC_DisableTx(pPDC);
-
-    //* Reset all Counter register Next buffer first
-    AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);
-    AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);
-    AT91F_PDC_SetTx(pPDC, (char *) 0, 0);
-    AT91F_PDC_SetRx(pPDC, (char *) 0, 0);
-
-    //* Enable the RX and TX PDC transfer requests
-    AT91F_PDC_EnableRx(pPDC);
-    AT91F_PDC_EnableTx(pPDC);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_Close
-//* \brief Close PDC: disable TX and RX reset transfer descriptors
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_Close (
-    AT91PS_PDC pPDC)       // \arg pointer to a PDC controller
-{
-    //* Disable the RX and TX PDC transfer requests
-    AT91F_PDC_DisableRx(pPDC);
-    AT91F_PDC_DisableTx(pPDC);
-
-    //* Reset all Counter register Next buffer first
-    AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);
-    AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);
-    AT91F_PDC_SetTx(pPDC, (char *) 0, 0);
-    AT91F_PDC_SetRx(pPDC, (char *) 0, 0);
-
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_SendFrame
-//* \brief Close PDC: disable TX and RX reset transfer descriptors
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PDC_SendFrame(
-    AT91PS_PDC pPDC,
-    char *pBuffer,
-    unsigned int szBuffer,
-    char *pNextBuffer,
-    unsigned int szNextBuffer )
-{
-    if (AT91F_PDC_IsTxEmpty(pPDC)) {
-        //* Buffer and next buffer can be initialized
-        AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer);
-        AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer);
-        return 2;
-    }
-    else if (AT91F_PDC_IsNextTxEmpty(pPDC)) {
-        //* Only one buffer can be initialized
-        AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer);
-        return 1;
-    }
-    else {
-        //* All buffer are in use...
-        return 0;
-    }
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_ReceiveFrame
-//* \brief Close PDC: disable TX and RX reset transfer descriptors
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PDC_ReceiveFrame (
-    AT91PS_PDC pPDC,
-    char *pBuffer,
-    unsigned int szBuffer,
-    char *pNextBuffer,
-    unsigned int szNextBuffer )
-{
-    if (AT91F_PDC_IsRxEmpty(pPDC)) {
-        //* Buffer and next buffer can be initialized
-        AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer);
-        AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer);
-        return 2;
-    }
-    else if (AT91F_PDC_IsNextRxEmpty(pPDC)) {
-        //* Only one buffer can be initialized
-        AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer);
-        return 1;
-    }
-    else {
-        //* All buffer are in use...
-        return 0;
-    }
-}
-/* *****************************************************************************
-                SOFTWARE API FOR DBGU
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_DBGU_InterruptEnable
-//* \brief Enable DBGU Interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_DBGU_InterruptEnable(
-        AT91PS_DBGU pDbgu,   // \arg  pointer to a DBGU controller
-        unsigned int flag) // \arg  dbgu interrupt to be enabled
-{
-        pDbgu->DBGU_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_DBGU_InterruptDisable
-//* \brief Disable DBGU Interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_DBGU_InterruptDisable(
-        AT91PS_DBGU pDbgu,   // \arg  pointer to a DBGU controller
-        unsigned int flag) // \arg  dbgu interrupt to be disabled
-{
-        pDbgu->DBGU_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_DBGU_GetInterruptMaskStatus
-//* \brief Return DBGU Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status
-        AT91PS_DBGU pDbgu) // \arg  pointer to a DBGU controller
-{
-        return pDbgu->DBGU_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_DBGU_IsInterruptMasked
-//* \brief Test if DBGU Interrupt is Masked
-//*----------------------------------------------------------------------------
-__inline int AT91F_DBGU_IsInterruptMasked(
-        AT91PS_DBGU pDbgu,   // \arg  pointer to a DBGU controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag);
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR PIO
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgPeriph
-//* \brief Enable pins to be drived by peripheral
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgPeriph(
-    AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-    unsigned int periphAEnable,  // \arg PERIPH A to enable
-    unsigned int periphBEnable)  // \arg PERIPH B to enable
-
-{
-    pPio->PIO_ASR = periphAEnable;
-    pPio->PIO_BSR = periphBEnable;
-    pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgOutput
-//* \brief Enable PIO in output mode
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgOutput(
-    AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-    unsigned int pioEnable)      // \arg PIO to be enabled
-{
-    pPio->PIO_PER = pioEnable; // Set in PIO mode
-    pPio->PIO_OER = pioEnable; // Configure in Output
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgInput
-//* \brief Enable PIO in input mode
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgInput(
-    AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-    unsigned int inputEnable)      // \arg PIO to be enabled
-{
-    // Disable output
-    pPio->PIO_ODR  = inputEnable;
-    pPio->PIO_PER  = inputEnable;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgOpendrain
-//* \brief Configure PIO in open drain
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgOpendrain(
-    AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-    unsigned int multiDrvEnable) // \arg pio to be configured in open drain
-{
-    // Configure the multi-drive option
-    pPio->PIO_MDDR = ~multiDrvEnable;
-    pPio->PIO_MDER = multiDrvEnable;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgPullup
-//* \brief Enable pullup on PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgPullup(
-    AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-    unsigned int pullupEnable)   // \arg enable pullup on PIO
-{
-        // Connect or not Pullup
-    pPio->PIO_PPUDR = ~pullupEnable;
-    pPio->PIO_PPUER = pullupEnable;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgDirectDrive
-//* \brief Enable direct drive on PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgDirectDrive(
-    AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-    unsigned int directDrive)    // \arg PIO to be configured with direct drive
-
-{
-    // Configure the Direct Drive
-    pPio->PIO_OWDR  = ~directDrive;
-    pPio->PIO_OWER  = directDrive;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgInputFilter
-//* \brief Enable input filter on input PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgInputFilter(
-    AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-    unsigned int inputFilter)    // \arg PIO to be configured with input filter
-
-{
-    // Configure the Direct Drive
-    pPio->PIO_IFDR  = ~inputFilter;
-    pPio->PIO_IFER  = inputFilter;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetInput
-//* \brief Return PIO input value
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetInput( // \return PIO input
-    AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-    return pPio->PIO_PDSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsInputSet
-//* \brief Test if PIO is input flag is active
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsInputSet(
-    AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-    unsigned int flag) // \arg  flag to be tested
-{
-    return (AT91F_PIO_GetInput(pPio) & flag);
-}
-
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_SetOutput
-//* \brief Set to 1 output PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_SetOutput(
-    AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-    unsigned int flag) // \arg  output to be set
-{
-    pPio->PIO_SODR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_ClearOutput
-//* \brief Set to 0 output PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_ClearOutput(
-    AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-    unsigned int flag) // \arg  output to be cleared
-{
-    pPio->PIO_CODR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_ForceOutput
-//* \brief Force output when Direct drive option is enabled
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_ForceOutput(
-    AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-    unsigned int flag) // \arg  output to be forced
-{
-    pPio->PIO_ODSR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_Enable
-//* \brief Enable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_Enable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio to be enabled
-{
-        pPio->PIO_PER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_Disable
-//* \brief Disable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_Disable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio to be disabled
-{
-        pPio->PIO_PDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetStatus
-//* \brief Return PIO Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_PSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsSet
-//* \brief Test if PIO is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_OutputEnable
-//* \brief Output Enable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_OutputEnable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio output to be enabled
-{
-        pPio->PIO_OER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_OutputDisable
-//* \brief Output Enable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_OutputDisable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio output to be disabled
-{
-        pPio->PIO_ODR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetOutputStatus
-//* \brief Return PIO Output Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_OSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsOuputSet
-//* \brief Test if PIO Output is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsOutputSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetOutputStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_InputFilterEnable
-//* \brief Input Filter Enable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_InputFilterEnable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio input filter to be enabled
-{
-        pPio->PIO_IFER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_InputFilterDisable
-//* \brief Input Filter Disable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_InputFilterDisable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio input filter to be disabled
-{
-        pPio->PIO_IFDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetInputFilterStatus
-//* \brief Return PIO Input Filter Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_IFSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsInputFilterSet
-//* \brief Test if PIO Input filter is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsInputFilterSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetInputFilterStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetOutputDataStatus
-//* \brief Return PIO Output Data Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status
-    AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_ODSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_InterruptEnable
-//* \brief Enable PIO Interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_InterruptEnable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio interrupt to be enabled
-{
-        pPio->PIO_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_InterruptDisable
-//* \brief Disable PIO Interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_InterruptDisable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio interrupt to be disabled
-{
-        pPio->PIO_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetInterruptMaskStatus
-//* \brief Return PIO Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetInterruptStatus
-//* \brief Return PIO Interrupt Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_ISR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsInterruptMasked
-//* \brief Test if PIO Interrupt is Masked
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsInterruptMasked(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsInterruptSet
-//* \brief Test if PIO Interrupt is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsInterruptSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetInterruptStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_MultiDriverEnable
-//* \brief Multi Driver Enable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_MultiDriverEnable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio to be enabled
-{
-        pPio->PIO_MDER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_MultiDriverDisable
-//* \brief Multi Driver Disable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_MultiDriverDisable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio to be disabled
-{
-        pPio->PIO_MDDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetMultiDriverStatus
-//* \brief Return PIO Multi Driver Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_MDSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsMultiDriverSet
-//* \brief Test if PIO MultiDriver is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsMultiDriverSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_A_RegisterSelection
-//* \brief PIO A Register Selection
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_A_RegisterSelection(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio A register selection
-{
-        pPio->PIO_ASR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_B_RegisterSelection
-//* \brief PIO B Register Selection
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_B_RegisterSelection(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio B register selection
-{
-        pPio->PIO_BSR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_Get_AB_RegisterStatus
-//* \brief Return PIO Interrupt Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_ABSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsAB_RegisterSet
-//* \brief Test if PIO AB Register is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsAB_RegisterSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_OutputWriteEnable
-//* \brief Output Write Enable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_OutputWriteEnable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio output write to be enabled
-{
-        pPio->PIO_OWER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_OutputWriteDisable
-//* \brief Output Write Disable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_OutputWriteDisable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio output write to be disabled
-{
-        pPio->PIO_OWDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetOutputWriteStatus
-//* \brief Return PIO Output Write Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_OWSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsOutputWriteSet
-//* \brief Test if PIO OutputWrite is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsOutputWriteSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetCfgPullup
-//* \brief Return PIO Configuration Pullup
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_PPUSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsOutputDataStatusSet
-//* \brief Test if PIO Output Data Status is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsOutputDataStatusSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetOutputDataStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsCfgPullupStatusSet
-//* \brief Test if PIO Configuration Pullup Status is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsCfgPullupStatusSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (~AT91F_PIO_GetCfgPullup(pPio) & flag);
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR PMC
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_CfgSysClkEnableReg
-//* \brief Configure the System Clock Enable Register of the PMC controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_CfgSysClkEnableReg (
-    AT91PS_PMC pPMC, // \arg pointer to PMC controller
-    unsigned int mode)
-{
-    //* Write to the SCER register
-    pPMC->PMC_SCER = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_CfgSysClkDisableReg
-//* \brief Configure the System Clock Disable Register of the PMC controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_CfgSysClkDisableReg (
-    AT91PS_PMC pPMC, // \arg pointer to PMC controller
-    unsigned int mode)
-{
-    //* Write to the SCDR register
-    pPMC->PMC_SCDR = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_GetSysClkStatusReg
-//* \brief Return the System Clock Status Register of the PMC controller
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_GetSysClkStatusReg (
-    AT91PS_PMC pPMC // pointer to a CAN controller
-    )
-{
-    return pPMC->PMC_SCSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_EnablePeriphClock
-//* \brief Enable peripheral clock
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_EnablePeriphClock (
-    AT91PS_PMC pPMC, // \arg pointer to PMC controller
-    unsigned int periphIds)  // \arg IDs of peripherals to enable
-{
-    pPMC->PMC_PCER = periphIds;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_DisablePeriphClock
-//* \brief Disable peripheral clock
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_DisablePeriphClock (
-    AT91PS_PMC pPMC, // \arg pointer to PMC controller
-    unsigned int periphIds)  // \arg IDs of peripherals to enable
-{
-    pPMC->PMC_PCDR = periphIds;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_GetPeriphClock
-//* \brief Get peripheral clock status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_GetPeriphClock (
-    AT91PS_PMC pPMC) // \arg pointer to PMC controller
-{
-    return pPMC->PMC_PCSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CKGR_CfgMainOscillatorReg
-//* \brief Cfg the main oscillator
-//*----------------------------------------------------------------------------
-__inline void AT91F_CKGR_CfgMainOscillatorReg (
-    AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
-    unsigned int mode)
-{
-    pCKGR->CKGR_MOR = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CKGR_GetMainOscillatorReg
-//* \brief Cfg the main oscillator
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CKGR_GetMainOscillatorReg (
-    AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
-{
-    return pCKGR->CKGR_MOR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CKGR_EnableMainOscillator
-//* \brief Enable the main oscillator
-//*----------------------------------------------------------------------------
-__inline void AT91F_CKGR_EnableMainOscillator(
-    AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
-{
-    pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CKGR_DisableMainOscillator
-//* \brief Disable the main oscillator
-//*----------------------------------------------------------------------------
-__inline void AT91F_CKGR_DisableMainOscillator (
-    AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
-{
-    pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CKGR_CfgMainOscStartUpTime
-//* \brief Cfg MOR Register according to the main osc startup time
-//*----------------------------------------------------------------------------
-__inline void AT91F_CKGR_CfgMainOscStartUpTime (
-    AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
-    unsigned int startup_time,  // \arg main osc startup time in microsecond (us)
-    unsigned int slowClock)  // \arg slowClock in Hz
-{
-    pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT;
-    pCKGR->CKGR_MOR |= ((slowClock * startup_time)/(8*1000000)) << 8;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CKGR_GetMainClockFreqReg
-//* \brief Cfg the main oscillator
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CKGR_GetMainClockFreqReg (
-    AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
-{
-    return pCKGR->CKGR_MCFR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CKGR_GetMainClock
-//* \brief Return Main clock in Hz
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CKGR_GetMainClock (
-    AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
-    unsigned int slowClock)  // \arg slowClock in Hz
-{
-    return ((pCKGR->CKGR_MCFR  & AT91C_CKGR_MAINF) * slowClock) >> 4;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_CfgMCKReg
-//* \brief Cfg Master Clock Register
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_CfgMCKReg (
-    AT91PS_PMC pPMC, // \arg pointer to PMC controller
-    unsigned int mode)
-{
-    pPMC->PMC_MCKR = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_GetMCKReg
-//* \brief Return Master Clock Register
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_GetMCKReg(
-    AT91PS_PMC pPMC) // \arg pointer to PMC controller
-{
-    return pPMC->PMC_MCKR;
-}
-
-//*------------------------------------------------------------------------------
-//* \fn    AT91F_PMC_GetMasterClock
-//* \brief Return master clock in Hz which correponds to processor clock for ARM7
-//*------------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_GetMasterClock (
-    AT91PS_PMC pPMC, // \arg pointer to PMC controller
-    AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
-    unsigned int slowClock)  // \arg slowClock in Hz
-{
-    unsigned int reg = pPMC->PMC_MCKR;
-    unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2));
-    unsigned int pllDivider, pllMultiplier;
-
-    switch (reg & AT91C_PMC_CSS) {
-        case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected
-            return slowClock / prescaler;
-        case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected
-            return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler;
-        case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected
-            reg = pCKGR->CKGR_PLLR;
-            pllDivider    = (reg  & AT91C_CKGR_DIV);
-            pllMultiplier = ((reg  & AT91C_CKGR_MUL) >> 16) + 1;
-            return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler;
-    }
-    return 0;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_EnablePCK
-//* \brief Enable peripheral clock
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_EnablePCK (
-    AT91PS_PMC pPMC, // \arg pointer to PMC controller
-    unsigned int pck,  // \arg Peripheral clock identifier 0 .. 7
-    unsigned int mode)
-{
-    pPMC->PMC_PCKR[pck] = mode;
-    pPMC->PMC_SCER = (1 << pck) << 8;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_DisablePCK
-//* \brief Enable peripheral clock
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_DisablePCK (
-    AT91PS_PMC pPMC, // \arg pointer to PMC controller
-    unsigned int pck)  // \arg Peripheral clock identifier 0 .. 7
-{
-    pPMC->PMC_SCDR = (1 << pck) << 8;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_EnableIt
-//* \brief Enable PMC interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_EnableIt (
-    AT91PS_PMC pPMC,     // pointer to a PMC controller
-    unsigned int flag)   // IT to be enabled
-{
-    //* Write to the IER register
-    pPMC->PMC_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_DisableIt
-//* \brief Disable PMC interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_DisableIt (
-    AT91PS_PMC pPMC, // pointer to a PMC controller
-    unsigned int flag) // IT to be disabled
-{
-    //* Write to the IDR register
-    pPMC->PMC_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_GetStatus
-//* \brief Return PMC Interrupt Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_GetStatus( // \return PMC Interrupt Status
-    AT91PS_PMC pPMC) // pointer to a PMC controller
-{
-    return pPMC->PMC_SR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_GetInterruptMaskStatus
-//* \brief Return PMC Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status
-    AT91PS_PMC pPMC) // pointer to a PMC controller
-{
-    return pPMC->PMC_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_IsInterruptMasked
-//* \brief Test if PMC Interrupt is Masked
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_IsInterruptMasked(
-        AT91PS_PMC pPMC,   // \arg  pointer to a PMC controller
-        unsigned int flag) // \arg  flag to be tested
-{
-    return (AT91F_PMC_GetInterruptMaskStatus(pPMC) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_IsStatusSet
-//* \brief Test if PMC Status is Set
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_IsStatusSet(
-        AT91PS_PMC pPMC,   // \arg  pointer to a PMC controller
-        unsigned int flag) // \arg  flag to be tested
-{
-    return (AT91F_PMC_GetStatus(pPMC) & flag);
-}/* *****************************************************************************
-                SOFTWARE API FOR RSTC
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_RSTSoftReset
-//* \brief Start Software Reset
-//*----------------------------------------------------------------------------
-__inline void AT91F_RSTSoftReset(
-        AT91PS_RSTC pRSTC,
-        unsigned int reset)
-{
-    pRSTC->RSTC_RCR = (0xA5000000 | reset);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_RSTSetMode
-//* \brief Set Reset Mode
-//*----------------------------------------------------------------------------
-__inline void AT91F_RSTSetMode(
-        AT91PS_RSTC pRSTC,
-        unsigned int mode)
-{
-    pRSTC->RSTC_RMR = (0xA5000000 | mode);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_RSTGetMode
-//* \brief Get Reset Mode
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_RSTGetMode(
-        AT91PS_RSTC pRSTC)
-{
-    return (pRSTC->RSTC_RMR);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_RSTGetStatus
-//* \brief Get Reset Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_RSTGetStatus(
-        AT91PS_RSTC pRSTC)
-{
-    return (pRSTC->RSTC_RSR);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_RSTIsSoftRstActive
-//* \brief Return !=0 if software reset is still not completed
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_RSTIsSoftRstActive(
-        AT91PS_RSTC pRSTC)
-{
-    return ((pRSTC->RSTC_RSR) & AT91C_RSTC_SRCMP);
-}
-/* *****************************************************************************
-                SOFTWARE API FOR RTTC
-   ***************************************************************************** */
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_SetRTT_TimeBase()
-//* \brief  Set the RTT prescaler according to the TimeBase in ms
-//*--------------------------------------------------------------------------------------
-__inline unsigned int AT91F_RTTSetTimeBase(
-        AT91PS_RTTC pRTTC,
-        unsigned int ms)
-{
-    if (ms > 2000)
-        return 1;   // AT91C_TIME_OUT_OF_RANGE
-    pRTTC->RTTC_RTMR &= ~0xFFFF;
-    pRTTC->RTTC_RTMR |= (((ms << 15) /1000) & 0xFFFF);
-    return 0;
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_RTTSetPrescaler()
-//* \brief  Set the new prescaler value
-//*--------------------------------------------------------------------------------------
-__inline unsigned int AT91F_RTTSetPrescaler(
-        AT91PS_RTTC pRTTC,
-        unsigned int rtpres)
-{
-    pRTTC->RTTC_RTMR &= ~0xFFFF;
-    pRTTC->RTTC_RTMR |= (rtpres & 0xFFFF);
-    return (pRTTC->RTTC_RTMR);
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_RTTRestart()
-//* \brief  Restart the RTT prescaler
-//*--------------------------------------------------------------------------------------
-__inline void AT91F_RTTRestart(
-        AT91PS_RTTC pRTTC)
-{
-    pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTRST;
-}
-
-
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_RTT_SetAlarmINT()
-//* \brief  Enable RTT Alarm Interrupt
-//*--------------------------------------------------------------------------------------
-__inline void AT91F_RTTSetAlarmINT(
-        AT91PS_RTTC pRTTC)
-{
-    pRTTC->RTTC_RTMR |= AT91C_RTTC_ALMIEN;
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_RTT_ClearAlarmINT()
-//* \brief  Disable RTT Alarm Interrupt
-//*--------------------------------------------------------------------------------------
-__inline void AT91F_RTTClearAlarmINT(
-        AT91PS_RTTC pRTTC)
-{
-    pRTTC->RTTC_RTMR &= ~AT91C_RTTC_ALMIEN;
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_RTT_SetRttIncINT()
-//* \brief  Enable RTT INC Interrupt
-//*--------------------------------------------------------------------------------------
-__inline void AT91F_RTTSetRttIncINT(
-        AT91PS_RTTC pRTTC)
-{
-    pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTINCIEN;
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_RTT_ClearRttIncINT()
-//* \brief  Disable RTT INC Interrupt
-//*--------------------------------------------------------------------------------------
-__inline void AT91F_RTTClearRttIncINT(
-        AT91PS_RTTC pRTTC)
-{
-    pRTTC->RTTC_RTMR &= ~AT91C_RTTC_RTTINCIEN;
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_RTT_SetAlarmValue()
-//* \brief  Set RTT Alarm Value
-//*--------------------------------------------------------------------------------------
-__inline void AT91F_RTTSetAlarmValue(
-        AT91PS_RTTC pRTTC, unsigned int alarm)
-{
-    pRTTC->RTTC_RTAR = alarm;
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_RTT_GetAlarmValue()
-//* \brief  Get RTT Alarm Value
-//*--------------------------------------------------------------------------------------
-__inline unsigned int AT91F_RTTGetAlarmValue(
-        AT91PS_RTTC pRTTC)
-{
-    return(pRTTC->RTTC_RTAR);
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_RTTGetStatus()
-//* \brief  Read the RTT status
-//*--------------------------------------------------------------------------------------
-__inline unsigned int AT91F_RTTGetStatus(
-        AT91PS_RTTC pRTTC)
-{
-    return(pRTTC->RTTC_RTSR);
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_RTT_ReadValue()
-//* \brief  Read the RTT value
-//*--------------------------------------------------------------------------------------
-__inline unsigned int AT91F_RTTReadValue(
-        AT91PS_RTTC pRTTC)
-{
-        register volatile unsigned int val1,val2;
-    do
+*               SOFTWARE API FOR AIC
+***************************************************************************** */
+    #define AT91C_AIC_BRANCH_OPCODE    ( ( void ( * )() ) 0xE51FFF20 ) /* ldr, pc, [pc, #-&F20] */
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_AIC_ConfigureIt */
+/** \brief Interrupt Handler Initialization */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_AIC_ConfigureIt( AT91PS_AIC pAic,                /* \arg pointer to the AIC registers */
+                                                 unsigned int irq_id,            /* \arg interrupt number to initialize */
+                                                 unsigned int priority,          /* \arg priority to give to the interrupt */
+                                                 unsigned int src_type,          /* \arg activation and sense of activation */
+                                                 void ( * newHandler )( void ) ) /* \arg address of the interrupt handler */
     {
-        val1 = pRTTC->RTTC_RTVR;
-        val2 = pRTTC->RTTC_RTVR;
+        unsigned int oldHandler;
+        unsigned int mask;
+
+        oldHandler = pAic->AIC_SVR[ irq_id ];
+
+        mask = 0x1 << irq_id;
+        /** Disable the interrupt on the interrupt controller */
+        pAic->AIC_IDCR = mask;
+        /** Save the interrupt handler routine pointer and the interrupt priority */
+        pAic->AIC_SVR[ irq_id ] = ( unsigned int ) newHandler;
+        /** Store the Source Mode Register */
+        pAic->AIC_SMR[ irq_id ] = src_type | priority;
+        /** Clear the interrupt on the interrupt controller */
+        pAic->AIC_ICCR = mask;
+
+        return oldHandler;
     }
-    while(val1 != val2);
-    return(val1);
-}
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_AIC_EnableIt */
+/** \brief Enable corresponding IT number */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_AIC_EnableIt( AT91PS_AIC pAic,      /* \arg pointer to the AIC registers */
+                                      unsigned int irq_id ) /* \arg interrupt number to initialize */
+    {
+        /** Enable the interrupt on the interrupt controller */
+        pAic->AIC_IECR = 0x1 << irq_id;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_AIC_DisableIt */
+/** \brief Disable corresponding IT number */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_AIC_DisableIt( AT91PS_AIC pAic,      /* \arg pointer to the AIC registers */
+                                       unsigned int irq_id ) /* \arg interrupt number to initialize */
+    {
+        unsigned int mask = 0x1 << irq_id;
+
+        /** Disable the interrupt on the interrupt controller */
+        pAic->AIC_IDCR = mask;
+        /** Clear the interrupt on the Interrupt Controller ( if one is pending ) */
+        pAic->AIC_ICCR = mask;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_AIC_ClearIt */
+/** \brief Clear corresponding IT number */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_AIC_ClearIt( AT91PS_AIC pAic,      /* \arg pointer to the AIC registers */
+                                     unsigned int irq_id ) /* \arg interrupt number to initialize */
+    {
+        /** Clear the interrupt on the Interrupt Controller ( if one is pending ) */
+        pAic->AIC_ICCR = ( 0x1 << irq_id );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_AIC_AcknowledgeIt */
+/** \brief Acknowledge corresponding IT number */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_AIC_AcknowledgeIt( AT91PS_AIC pAic ) /* \arg pointer to the AIC registers */
+    {
+        pAic->AIC_EOICR = pAic->AIC_EOICR;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_AIC_SetExceptionVector */
+/** \brief Configure vector handler */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_AIC_SetExceptionVector( unsigned int * pVector, /* \arg pointer to the AIC registers */
+                                                        void ( * Handler )() )  /* \arg Interrupt Handler */
+    {
+        unsigned int oldVector = *pVector;
+
+        if( ( unsigned int ) Handler == ( unsigned int ) AT91C_AIC_BRANCH_OPCODE )
+        {
+            *pVector = ( unsigned int ) AT91C_AIC_BRANCH_OPCODE;
+        }
+        else
+        {
+            *pVector = ( ( ( ( ( unsigned int ) Handler ) - ( ( unsigned int ) pVector ) - 0x8 ) >> 2 ) & 0x00FFFFFF ) | 0xEA000000;
+        }
+
+        return oldVector;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_AIC_Trig */
+/** \brief Trig an IT */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_AIC_Trig( AT91PS_AIC pAic,      /* \arg pointer to the AIC registers */
+                                  unsigned int irq_id ) /* \arg interrupt number */
+    {
+        pAic->AIC_ISCR = ( 0x1 << irq_id );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_AIC_IsActive */
+/** \brief Test if an IT is active */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_AIC_IsActive( AT91PS_AIC pAic,      /* \arg pointer to the AIC registers */
+                                              unsigned int irq_id ) /* \arg Interrupt Number */
+    {
+        return( pAic->AIC_ISR & ( 0x1 << irq_id ) );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_AIC_IsPending */
+/** \brief Test if an IT is pending */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_AIC_IsPending( AT91PS_AIC pAic,      /* \arg pointer to the AIC registers */
+                                               unsigned int irq_id ) /* \arg Interrupt Number */
+    {
+        return( pAic->AIC_IPR & ( 0x1 << irq_id ) );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_AIC_Open */
+/** \brief Set exception vectors and AIC registers to default values */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_AIC_Open( AT91PS_AIC pAic,              /* \arg pointer to the AIC registers */
+                                  void ( * IrqHandler )(),      /* \arg Default IRQ vector exception */
+                                  void ( * FiqHandler )(),      /* \arg Default FIQ vector exception */
+                                  void ( * DefaultHandler )(),  /* \arg Default Handler set in ISR */
+                                  void ( * SpuriousHandler )(), /* \arg Default Spurious Handler */
+                                  unsigned int protectMode )    /* \arg Debug Control Register */
+    {
+        int i;
+
+        /* Disable all interrupts and set IVR to the default handler */
+        for( i = 0; i < 32; ++i )
+        {
+            AT91F_AIC_DisableIt( pAic, i );
+            AT91F_AIC_ConfigureIt( pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_HIGH_LEVEL, DefaultHandler );
+        }
+
+        /* Set the IRQ exception vector */
+        AT91F_AIC_SetExceptionVector( ( unsigned int * ) 0x18, IrqHandler );
+        /* Set the Fast Interrupt exception vector */
+        AT91F_AIC_SetExceptionVector( ( unsigned int * ) 0x1C, FiqHandler );
+
+        pAic->AIC_SPU = ( unsigned int ) SpuriousHandler;
+        pAic->AIC_DCR = protectMode;
+    }
+
 /* *****************************************************************************
-                SOFTWARE API FOR PITC
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PITInit
-//* \brief System timer init : period in
\ No newline at end of file
+*               SOFTWARE API FOR PDC
+***************************************************************************** */
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_SetNextRx */
+/** \brief Set the next receive transfer descriptor */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PDC_SetNextRx( AT91PS_PDC pPDC,     /* \arg pointer to a PDC controller */
+                                       char * address,      /* \arg address to the next bloc to be received */
+                                       unsigned int bytes ) /* \arg number of bytes to be received */
+    {
+        pPDC->PDC_RNPR = ( unsigned int ) address;
+        pPDC->PDC_RNCR = bytes;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_SetNextTx */
+/** \brief Set the next transmit transfer descriptor */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PDC_SetNextTx( AT91PS_PDC pPDC,     /* \arg pointer to a PDC controller */
+                                       char * address,      /* \arg address to the next bloc to be transmitted */
+                                       unsigned int bytes ) /* \arg number of bytes to be transmitted */
+    {
+        pPDC->PDC_TNPR = ( unsigned int ) address;
+        pPDC->PDC_TNCR = bytes;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_SetRx */
+/** \brief Set the receive transfer descriptor */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PDC_SetRx( AT91PS_PDC pPDC,     /* \arg pointer to a PDC controller */
+                                   char * address,      /* \arg address to the next bloc to be received */
+                                   unsigned int bytes ) /* \arg number of bytes to be received */
+    {
+        pPDC->PDC_RPR = ( unsigned int ) address;
+        pPDC->PDC_RCR = bytes;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_SetTx */
+/** \brief Set the transmit transfer descriptor */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PDC_SetTx( AT91PS_PDC pPDC,     /* \arg pointer to a PDC controller */
+                                   char * address,      /* \arg address to the next bloc to be transmitted */
+                                   unsigned int bytes ) /* \arg number of bytes to be transmitted */
+    {
+        pPDC->PDC_TPR = ( unsigned int ) address;
+        pPDC->PDC_TCR = bytes;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_EnableTx */
+/** \brief Enable transmit */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PDC_EnableTx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
+    {
+        pPDC->PDC_PTCR = AT91C_PDC_TXTEN;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_EnableRx */
+/** \brief Enable receive */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PDC_EnableRx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
+    {
+        pPDC->PDC_PTCR = AT91C_PDC_RXTEN;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_DisableTx */
+/** \brief Disable transmit */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PDC_DisableTx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
+    {
+        pPDC->PDC_PTCR = AT91C_PDC_TXTDIS;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_DisableRx */
+/** \brief Disable receive */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PDC_DisableRx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
+    {
+        pPDC->PDC_PTCR = AT91C_PDC_RXTDIS;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_IsTxEmpty */
+/** \brief Test if the current transfer descriptor has been sent */
+/**---------------------------------------------------------------------------- */
+    __inline int AT91F_PDC_IsTxEmpty( /* \return return 1 if transfer is complete */
+        AT91PS_PDC pPDC )             /* \arg pointer to a PDC controller */
+    {
+        return !( pPDC->PDC_TCR );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_IsNextTxEmpty */
+/** \brief Test if the next transfer descriptor has been moved to the current td */
+/**---------------------------------------------------------------------------- */
+    __inline int AT91F_PDC_IsNextTxEmpty( /* \return return 1 if transfer is complete */
+        AT91PS_PDC pPDC )                 /* \arg pointer to a PDC controller */
+    {
+        return !( pPDC->PDC_TNCR );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_IsRxEmpty */
+/** \brief Test if the current transfer descriptor has been filled */
+/**---------------------------------------------------------------------------- */
+    __inline int AT91F_PDC_IsRxEmpty( /* \return return 1 if transfer is complete */
+        AT91PS_PDC pPDC )             /* \arg pointer to a PDC controller */
+    {
+        return !( pPDC->PDC_RCR );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_IsNextRxEmpty */
+/** \brief Test if the next transfer descriptor has been moved to the current td */
+/**---------------------------------------------------------------------------- */
+    __inline int AT91F_PDC_IsNextRxEmpty( /* \return return 1 if transfer is complete */
+        AT91PS_PDC pPDC )                 /* \arg pointer to a PDC controller */
+    {
+        return !( pPDC->PDC_RNCR );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_Open */
+/** \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PDC_Open( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
+    {
+        /** Disable the RX and TX PDC transfer requests */
+        AT91F_PDC_DisableRx( pPDC );
+        AT91F_PDC_DisableTx( pPDC );
+
+        /** Reset all Counter register Next buffer first */
+        AT91F_PDC_SetNextTx( pPDC, ( char * ) 0, 0 );
+        AT91F_PDC_SetNextRx( pPDC, ( char * ) 0, 0 );
+        AT91F_PDC_SetTx( pPDC, ( char * ) 0, 0 );
+        AT91F_PDC_SetRx( pPDC, ( char * ) 0, 0 );
+
+        /** Enable the RX and TX PDC transfer requests */
+        AT91F_PDC_EnableRx( pPDC );
+        AT91F_PDC_EnableTx( pPDC );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_Close */
+/** \brief Close PDC: disable TX and RX reset transfer descriptors */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PDC_Close( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
+    {
+        /** Disable the RX and TX PDC transfer requests */
+        AT91F_PDC_DisableRx( pPDC );
+        AT91F_PDC_DisableTx( pPDC );
+
+        /** Reset all Counter register Next buffer first */
+        AT91F_PDC_SetNextTx( pPDC, ( char * ) 0, 0 );
+        AT91F_PDC_SetNextRx( pPDC, ( char * ) 0, 0 );
+        AT91F_PDC_SetTx( pPDC, ( char * ) 0, 0 );
+        AT91F_PDC_SetRx( pPDC, ( char * ) 0, 0 );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_SendFrame */
+/** \brief Close PDC: disable TX and RX reset transfer descriptors */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_PDC_SendFrame( AT91PS_PDC pPDC,
+                                               char * pBuffer,
+                                               unsigned int szBuffer,
+                                               char * pNextBuffer,
+                                               unsigned int szNextBuffer )
+    {
+        if( AT91F_PDC_IsTxEmpty( pPDC ) )
+        {
+            /** Buffer and next buffer can be initialized */
+            AT91F_PDC_SetTx( pPDC, pBuffer, szBuffer );
+            AT91F_PDC_SetNextTx( pPDC, pNextBuffer, szNextBuffer );
+            return 2;
+        }
+        else if( AT91F_PDC_IsNextTxEmpty( pPDC ) )
+        {
+            /** Only one buffer can be initialized */
+            AT91F_PDC_SetNextTx( pPDC, pBuffer, szBuffer );
+            return 1;
+        }
+        else
+        {
+            /** All buffer are in use... */
+            return 0;
+        }
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_ReceiveFrame */
+/** \brief Close PDC: disable TX and RX reset transfer descriptors */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_PDC_ReceiveFrame( AT91PS_PDC pPDC,
+                                                  char * pBuffer,
+                                                  unsigned int szBuffer,
+                                                  char * pNextBuffer,
+                                                  unsigned int szNextBuffer )
+    {
+        if( AT91F_PDC_IsRxEmpty( pPDC ) )
+        {
+            /** Buffer and next buffer can be initialized */
+            AT91F_PDC_SetRx( pPDC, pBuffer, szBuffer );
+            AT91F_PDC_SetNextRx( pPDC, pNextBuffer, szNextBuffer );
+            return 2;
+        }
+        else if( AT91F_PDC_IsNextRxEmpty( pPDC ) )
+        {
+            /** Only one buffer can be initialized */
+            AT91F_PDC_SetNextRx( pPDC, pBuffer, szBuffer );
+            return 1;
+        }
+        else
+        {
+            /** All buffer are in use... */
+            return 0;
+        }
+    }
+
+/* *****************************************************************************
+*               SOFTWARE API FOR DBGU
+***************************************************************************** */
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_DBGU_InterruptEnable */
+/** \brief Enable DBGU Interrupt */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_DBGU_InterruptEnable( AT91PS_DBGU pDbgu,  /* \arg  pointer to a DBGU controller */
+                                              unsigned int flag ) /* \arg  dbgu interrupt to be enabled */
+    {
+        pDbgu->DBGU_IER = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_DBGU_InterruptDisable */
+/** \brief Disable DBGU Interrupt */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_DBGU_InterruptDisable( AT91PS_DBGU pDbgu,  /* \arg  pointer to a DBGU controller */
+                                               unsigned int flag ) /* \arg  dbgu interrupt to be disabled */
+    {
+        pDbgu->DBGU_IDR = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_DBGU_GetInterruptMaskStatus */
+/** \brief Return DBGU Interrupt Mask Status */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( /* \return DBGU Interrupt Mask Status */
+        AT91PS_DBGU pDbgu )                                  /* \arg  pointer to a DBGU controller */
+    {
+        return pDbgu->DBGU_IMR;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_DBGU_IsInterruptMasked */
+/** \brief Test if DBGU Interrupt is Masked */
+/**---------------------------------------------------------------------------- */
+    __inline int AT91F_DBGU_IsInterruptMasked( AT91PS_DBGU pDbgu,  /* \arg  pointer to a DBGU controller */
+                                               unsigned int flag ) /* \arg  flag to be tested */
+    {
+        return( AT91F_DBGU_GetInterruptMaskStatus( pDbgu ) & flag );
+    }
+
+/* *****************************************************************************
+*               SOFTWARE API FOR PIO
+***************************************************************************** */
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_CfgPeriph */
+/** \brief Enable pins to be derived by peripheral */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_CfgPeriph( AT91PS_PIO pPio,             /* \arg pointer to a PIO controller */
+                                       unsigned int periphAEnable,  /* \arg PERIPH A to enable */
+                                       unsigned int periphBEnable ) /* \arg PERIPH B to enable */
+
+    {
+        pPio->PIO_ASR = periphAEnable;
+        pPio->PIO_BSR = periphBEnable;
+        pPio->PIO_PDR = ( periphAEnable | periphBEnable ); /* Set in Periph mode */
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_CfgOutput */
+/** \brief Enable PIO in output mode */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_CfgOutput( AT91PS_PIO pPio,         /* \arg pointer to a PIO controller */
+                                       unsigned int pioEnable ) /* \arg PIO to be enabled */
+    {
+        pPio->PIO_PER = pioEnable;                              /* Set in PIO mode */
+        pPio->PIO_OER = pioEnable;                              /* Configure in Output */
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_CfgInput */
+/** \brief Enable PIO in input mode */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_CfgInput( AT91PS_PIO pPio,           /* \arg pointer to a PIO controller */
+                                      unsigned int inputEnable ) /* \arg PIO to be enabled */
+    {
+        /* Disable output */
+        pPio->PIO_ODR = inputEnable;
+        pPio->PIO_PER = inputEnable;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_CfgOpendrain */
+/** \brief Configure PIO in open drain */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_CfgOpendrain( AT91PS_PIO pPio,              /* \arg pointer to a PIO controller */
+                                          unsigned int multiDrvEnable ) /* \arg pio to be configured in open drain */
+    {
+        /* Configure the multi-drive option */
+        pPio->PIO_MDDR = ~multiDrvEnable;
+        pPio->PIO_MDER = multiDrvEnable;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_CfgPullup */
+/** \brief Enable pullup on PIO */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_CfgPullup( AT91PS_PIO pPio,            /* \arg pointer to a PIO controller */
+                                       unsigned int pullupEnable ) /* \arg enable pullup on PIO */
+    {
+        /* Connect or not Pullup */
+        pPio->PIO_PPUDR = ~pullupEnable;
+        pPio->PIO_PPUER = pullupEnable;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_CfgDirectDrive */
+/** \brief Enable direct drive on PIO */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_CfgDirectDrive( AT91PS_PIO pPio,           /* \arg pointer to a PIO controller */
+                                            unsigned int directDrive ) /* \arg PIO to be configured with direct drive */
+
+    {
+        /* Configure the Direct Drive */
+        pPio->PIO_OWDR = ~directDrive;
+        pPio->PIO_OWER = directDrive;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_CfgInputFilter */
+/** \brief Enable input filter on input PIO */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_CfgInputFilter( AT91PS_PIO pPio,           /* \arg pointer to a PIO controller */
+                                            unsigned int inputFilter ) /* \arg PIO to be configured with input filter */
+
+    {
+        /* Configure the Direct Drive */
+        pPio->PIO_IFDR = ~inputFilter;
+        pPio->PIO_IFER = inputFilter;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_GetInput */
+/** \brief Return PIO input value */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_PIO_GetInput( /* \return PIO input */
+        AT91PS_PIO pPio )                     /* \arg  pointer to a PIO controller */
+    {
+        return pPio->PIO_PDSR;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_IsInputSet */
+/** \brief Test if PIO is input flag is active */
+/**---------------------------------------------------------------------------- */
+    __inline int AT91F_PIO_IsInputSet( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                       unsigned int flag ) /* \arg  flag to be tested */
+    {
+        return( AT91F_PIO_GetInput( pPio ) & flag );
+    }
+
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_SetOutput */
+/** \brief Set to 1 output PIO */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_SetOutput( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                       unsigned int flag ) /* \arg  output to be set */
+    {
+        pPio->PIO_SODR = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_ClearOutput */
+/** \brief Set to 0 output PIO */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_ClearOutput( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                         unsigned int flag ) /* \arg  output to be cleared */
+    {
+        pPio->PIO_CODR = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_ForceOutput */
+/** \brief Force output when Direct drive option is enabled */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_ForceOutput( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                         unsigned int flag ) /* \arg  output to be forced */
+    {
+        pPio->PIO_ODSR = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_Enable */
+/** \brief Enable PIO */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_Enable( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                    unsigned int flag ) /* \arg  pio to be enabled */
+    {
+        pPio->PIO_PER = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_Disable */
+/** \brief Disable PIO */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_Disable( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                     unsigned int flag ) /* \arg  pio to be disabled */
+    {
+        pPio->PIO_PDR = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_GetStatus */
+/** \brief Return PIO Status */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_PIO_GetStatus( /* \return PIO Status */
+        AT91PS_PIO pPio )                      /* \arg  pointer to a PIO controller */
+    {
+        return pPio->PIO_PSR;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_IsSet */
+/** \brief Test if PIO is Set */
+/**---------------------------------------------------------------------------- */
+    __inline int AT91F_PIO_IsSet( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                  unsigned int flag ) /* \arg  flag to be tested */
+    {
+        return( AT91F_PIO_GetStatus( pPio ) & flag );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_OutputEnable */
+/** \brief Output Enable PIO */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_OutputEnable( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                          unsigned int flag ) /* \arg  pio output to be enabled */
+    {
+        pPio->PIO_OER = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_OutputDisable */
+/** \brief Output Enable PIO */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_OutputDisable( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                           unsigned int flag ) /* \arg  pio output to be disabled */
+    {
+        pPio->PIO_ODR = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_GetOutputStatus */
+/** \brief Return PIO Output Status */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_PIO_GetOutputStatus( /* \return PIO Output Status */
+        AT91PS_PIO pPio )                            /* \arg  pointer to a PIO controller */
+    {
+        return pPio->PIO_OSR;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_IsOuputSet */
+/** \brief Test if PIO Output is Set */
+/**---------------------------------------------------------------------------- */
+    __inline int AT91F_PIO_IsOutputSet( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                        unsigned int flag ) /* \arg  flag to be tested */
+    {
+        return( AT91F_PIO_GetOutputStatus( pPio ) & flag );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_InputFilterEnable */
+/** \brief Input Filter Enable PIO */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_InputFilterEnable( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                               unsigned int flag ) /* \arg  pio input filter to be enabled */
+    {
+        pPio->PIO_IFER = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_InputFilterDisable */
+/** \brief Input Filter Disable PIO */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_InputFilterDisable( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                                unsigned int flag ) /* \arg  pio input filter to be disabled */
+    {
+        pPio->PIO_IFDR = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_GetInputFilterStatus */
+/** \brief Return PIO Input Filter Status */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_PIO_GetInputFilterStatus( /* \return PIO Input Filter Status */
+        AT91PS_PIO pPio )                                 /* \arg  pointer to a PIO controller */
+    {
+        return pPio->PIO_IFSR;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_IsInputFilterSet */
+/** \brief Test if PIO Input filter is Set */
+/**---------------------------------------------------------------------------- */
+    __inline int AT91F_PIO_IsInputFilterSet( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                             unsigned int flag ) /* \arg  flag to be tested */
+    {
+        return( AT91F_PIO_GetInputFilterStatus( pPio ) & flag );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_GetOutputDataStatus */
+/** \brief Return PIO Output Data Status */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_PIO_GetOutputDataStatus( /* \return PIO Output Data Status */
+        AT91PS_PIO pPio )                                /* \arg  pointer to a PIO controller */
+    {
+        return pPio->PIO_ODSR;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_InterruptEnable */
+/** \brief Enable PIO Interrupt */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_InterruptEnable( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                             unsigned int flag ) /* \arg  pio interrupt to be enabled */
+    {
+        pPio->PIO_IER = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_InterruptDisable */
+/** \brief Disable PIO Interrupt */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_InterruptDisable( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                              unsigned int flag ) /* \arg  pio interrupt to be disabled */
+    {
+        pPio->PIO_IDR = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_GetInterruptMaskStatus */
+/** \brief Return PIO Interrupt Mask Status */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_PIO_GetInterruptMaskStatus( /* \return PIO Interrupt Mask Status */
+        AT91PS_PIO pPio )                                   /* \arg  pointer to a PIO controller */
+    {
+        return pPio->PIO_IMR;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_GetInterruptStatus */
+/** \brief Return PIO Interrupt Status */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_PIO_GetInterruptStatus( /* \return PIO Interrupt Status */
+        AT91PS_PIO pPio )                               /* \arg  pointer to a PIO controller */
+    {
+        return pPio->PIO_ISR;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_IsInterruptMasked */
+/** \brief Test if PIO Interrupt is Masked */
+/**---------------------------------------------------------------------------- */
+    __inline int AT91F_PIO_IsInterruptMasked( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                              unsigned int flag ) /* \arg  flag to be tested */
+    {
+        return( AT91F_PIO_GetInterruptMaskStatus( pPio ) & flag );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_IsInterruptSet */
+/** \brief Test if PIO Interrupt is Set */
+/**---------------------------------------------------------------------------- */
+    __inline int AT91F_PIO_IsInterruptSet( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                           unsigned int flag ) /* \arg  flag to be tested */
+    {
+        return( AT91F_PIO_GetInterruptStatus( pPio ) & flag );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_MultiDriverEnable */
+/** \brief Multi Driver Enable PIO */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_MultiDriverEnable( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                               unsigned int flag ) /* \arg  pio to be enabled */
+    {
+        pPio->PIO_MDER = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_MultiDriverDisable */
+/** \brief Multi Driver Disable PIO */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_MultiDriverDisable( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                                unsigned int flag ) /* \arg  pio to be disabled */
+    {
+        pPio->PIO_MDDR = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_GetMultiDriverStatus */
+/** \brief Return PIO Multi Driver Status */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_PIO_GetMultiDriverStatus( /* \return PIO Multi Driver Status */
+        AT91PS_PIO pPio )                                 /* \arg  pointer to a PIO controller */
+    {
+        return pPio->PIO_MDSR;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_IsMultiDriverSet */
+/** \brief Test if PIO MultiDriver is Set */
+/**---------------------------------------------------------------------------- */
+    __inline int AT91F_PIO_IsMultiDriverSet( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                             unsigned int flag ) /* \arg  flag to be tested */
+    {
+        return( AT91F_PIO_GetMultiDriverStatus( pPio ) & flag );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_A_RegisterSelection */
+/** \brief PIO A Register Selection */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_A_RegisterSelection( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                                 unsigned int flag ) /* \arg  pio A register selection */
+    {
+        pPio->PIO_ASR = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_B_RegisterSelection */
+/** \brief PIO B Register Selection */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_B_RegisterSelection( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                                 unsigned int flag ) /* \arg  pio B register selection */
+    {
+        pPio->PIO_BSR = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_Get_AB_RegisterStatus */
+/** \brief Return PIO Interrupt Status */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( /* \return PIO AB Register Status */
+        AT91PS_PIO pPio )                                  /* \arg  pointer to a PIO controller */
+    {
+        return pPio->PIO_ABSR;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_IsAB_RegisterSet */
+/** \brief Test if PIO AB Register is Set */
+/**---------------------------------------------------------------------------- */
+    __inline int AT91F_PIO_IsAB_RegisterSet( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                             unsigned int flag ) /* \arg  flag to be tested */
+    {
+        return( AT91F_PIO_Get_AB_RegisterStatus( pPio ) & flag );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_OutputWriteEnable */
+/** \brief Output Write Enable PIO */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_OutputWriteEnable( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                               unsigned int flag ) /* \arg  pio output write to be enabled */
+    {
+        pPio->PIO_OWER = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_OutputWriteDisable */
+/** \brief Output Write Disable PIO */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_OutputWriteDisable( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                                unsigned int flag ) /* \arg  pio output write to be disabled */
+    {
+        pPio->PIO_OWDR = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_GetOutputWriteStatus */
+/** \brief Return PIO Output Write Status */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_PIO_GetOutputWriteStatus( /* \return PIO Output Write Status */
+        AT91PS_PIO pPio )                                 /* \arg  pointer to a PIO controller */
+    {
+        return pPio->PIO_OWSR;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_IsOutputWriteSet */
+/** \brief Test if PIO OutputWrite is Set */
+/**---------------------------------------------------------------------------- */
+    __inline int AT91F_PIO_IsOutputWriteSet( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                             unsigned int flag ) /* \arg  flag to be tested */
+    {
+        return( AT91F_PIO_GetOutputWriteStatus( pPio ) & flag );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_GetCfgPullup */
+/** \brief Return PIO Configuration Pullup */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_PIO_GetCfgPullup( /* \return PIO Configuration Pullup */
+        AT91PS_PIO pPio )                         /* \arg  pointer to a PIO controller */
+    {
+        return pPio->PIO_PPUSR;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_IsOutputDataStatusSet */
+/** \brief Test if PIO Output Data Status is Set */
+/**---------------------------------------------------------------------------- */
+    __inline int AT91F_PIO_IsOutputDataStatusSet( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                                  unsigned int flag ) /* \arg  flag to be tested */
+    {
+        return( AT91F_PIO_GetOutputDataStatus( pPio ) & flag );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_IsCfgPullupStatusSet */
+/** \brief Test if PIO Configuration Pullup Status is Set */
+/**---------------------------------------------------------------------------- */
+    __inline int AT91F_PIO_IsCfgPullupStatusSet( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                                 unsigned int flag ) /* \arg  flag to be tested */
+    {
+        return( ~AT91F_PIO_GetCfgPullup( pPio ) & flag );
+    }
+
+/* *****************************************************************************
+*               SOFTWARE API FOR PMC
+***************************************************************************** */
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_CfgSysClkEnableReg */
+/** \brief Configure the System Clock Enable Register of the PMC controller */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PMC_CfgSysClkEnableReg( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */
+                                                unsigned int mode )
+    {
+        /** Write to the SCER register */
+        pPMC->PMC_SCER = mode;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_CfgSysClkDisableReg */
+/** \brief Configure the System Clock Disable Register of the PMC controller */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PMC_CfgSysClkDisableReg( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */
+                                                 unsigned int mode )
+    {
+        /** Write to the SCDR register */
+        pPMC->PMC_SCDR = mode;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_GetSysClkStatusReg */
+/** \brief Return the System Clock Status Register of the PMC controller */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_PMC_GetSysClkStatusReg( AT91PS_PMC pPMC /* pointer to a CAN controller */
+                                                        )
+    {
+        return pPMC->PMC_SCSR;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_EnablePeriphClock */
+/** \brief Enable peripheral clock */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PMC_EnablePeriphClock( AT91PS_PMC pPMC,         /* \arg pointer to PMC controller */
+                                               unsigned int periphIds ) /* \arg IDs of peripherals to enable */
+    {
+        pPMC->PMC_PCER = periphIds;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_DisablePeriphClock */
+/** \brief Disable peripheral clock */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PMC_DisablePeriphClock( AT91PS_PMC pPMC,         /* \arg pointer to PMC controller */
+                                                unsigned int periphIds ) /* \arg IDs of peripherals to enable */
+    {
+        pPMC->PMC_PCDR = periphIds;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_GetPeriphClock */
+/** \brief Get peripheral clock status */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_PMC_GetPeriphClock( AT91PS_PMC pPMC ) /* \arg pointer to PMC controller */
+    {
+        return pPMC->PMC_PCSR;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_CKGR_CfgMainOscillatorReg */
+/** \brief Cfg the main oscillator */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_CKGR_CfgMainOscillatorReg( AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */
+                                                   unsigned int mode )
+    {
+        pCKGR->CKGR_MOR = mode;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_CKGR_GetMainOscillatorReg */
+/** \brief Cfg the main oscillator */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_CKGR_GetMainOscillatorReg( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */
+    {
+        return pCKGR->CKGR_MOR;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_CKGR_EnableMainOscillator */
+/** \brief Enable the main oscillator */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_CKGR_EnableMainOscillator( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */
+    {
+        pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_CKGR_DisableMainOscillator */
+/** \brief Disable the main oscillator */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_CKGR_DisableMainOscillator( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */
+    {
+        pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_CKGR_CfgMainOscStartUpTime */
+/** \brief Cfg MOR Register according to the main osc startup time */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_CKGR_CfgMainOscStartUpTime( AT91PS_CKGR pCKGR,         /* \arg pointer to CKGR controller */
+                                                    unsigned int startup_time, /* \arg main osc startup time in microsecond (us) */
+                                                    unsigned int slowClock )   /* \arg slowClock in Hz */
+    {
+        pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT;
+        pCKGR->CKGR_MOR |= ( ( slowClock * startup_time ) / ( 8 * 1000000 ) ) << 8;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_CKGR_GetMainClockFreqReg */
+/** \brief Cfg the main oscillator */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_CKGR_GetMainClockFreqReg( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */
+    {
+        return pCKGR->CKGR_MCFR;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_CKGR_GetMainClock */
+/** \brief Return Main clock in Hz */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_CKGR_GetMainClock( AT91PS_CKGR pCKGR,       /* \arg pointer to CKGR controller */
+                                                   unsigned int slowClock ) /* \arg slowClock in Hz */
+    {
+        return ( ( pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF ) * slowClock ) >> 4;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_CfgMCKReg */
+/** \brief Cfg Master Clock Register */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PMC_CfgMCKReg( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */
+                                       unsigned int mode )
+    {
+        pPMC->PMC_MCKR = mode;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_GetMCKReg */
+/** \brief Return Master Clock Register */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_PMC_GetMCKReg( AT91PS_PMC pPMC ) /* \arg pointer to PMC controller */
+    {
+        return pPMC->PMC_MCKR;
+    }
+
+/**------------------------------------------------------------------------------ */
+/** \fn    AT91F_PMC_GetMasterClock */
+/** \brief Return master clock in Hz which corresponds to processor clock for ARM7 */
+/**------------------------------------------------------------------------------ */
+    __inline unsigned int AT91F_PMC_GetMasterClock( AT91PS_PMC pPMC,         /* \arg pointer to PMC controller */
+                                                    AT91PS_CKGR pCKGR,       /* \arg pointer to CKGR controller */
+                                                    unsigned int slowClock ) /* \arg slowClock in Hz */
+    {
+        unsigned int reg = pPMC->PMC_MCKR;
+        unsigned int prescaler = ( 1 << ( ( reg & AT91C_PMC_PRES ) >> 2 ) );
+        unsigned int pllDivider, pllMultiplier;
+
+        switch( reg & AT91C_PMC_CSS )
+        {
+            case AT91C_PMC_CSS_SLOW_CLK: /* Slow clock selected */
+                return slowClock / prescaler;
+
+            case AT91C_PMC_CSS_MAIN_CLK: /* Main clock is selected */
+                return AT91F_CKGR_GetMainClock( pCKGR, slowClock ) / prescaler;
+
+            case AT91C_PMC_CSS_PLL_CLK: /* PLLB clock is selected */
+                reg = pCKGR->CKGR_PLLR;
+                pllDivider = ( reg & AT91C_CKGR_DIV );
+                pllMultiplier = ( ( reg & AT91C_CKGR_MUL ) >> 16 ) + 1;
+                return AT91F_CKGR_GetMainClock( pCKGR, slowClock ) / pllDivider * pllMultiplier / prescaler;
+        }
+
+        return 0;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_EnablePCK */
+/** \brief Enable peripheral clock */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PMC_EnablePCK( AT91PS_PMC pPMC,  /* \arg pointer to PMC controller */
+                                       unsigned int pck, /* \arg Peripheral clock identifier 0 .. 7 */
+                                       unsigned int mode )
+    {
+        pPMC->PMC_PCKR[ pck ] = mode;
+        pPMC->PMC_SCER = ( 1 << pck ) << 8;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_DisablePCK */
+/** \brief Enable peripheral clock */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PMC_DisablePCK( AT91PS_PMC pPMC,   /* \arg pointer to PMC controller */
+                                        unsigned int pck ) /* \arg Peripheral clock identifier 0 .. 7 */
+    {
+        pPMC->PMC_SCDR = ( 1 << pck ) << 8;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_EnableIt */
+/** \brief Enable PMC interrupt */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PMC_EnableIt( AT91PS_PMC pPMC,    /* pointer to a PMC controller */
+                                      unsigned int flag ) /* IT to be enabled */
+    {
+        /** Write to the IER register */
+        pPMC->PMC_IER = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_DisableIt */
+/** \brief Disable PMC interrupt */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PMC_DisableIt( AT91PS_PMC pPMC,    /* pointer to a PMC controller */
+                                       unsigned int flag ) /* IT to be disabled */
+    {
+        /** Write to the IDR register */
+        pPMC->PMC_IDR = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_GetStatus */
+/** \brief Return PMC Interrupt Status */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_PMC_GetStatus( /* \return PMC Interrupt Status */
+        AT91PS_PMC pPMC )                      /* pointer to a PMC controller */
+    {
+        return pPMC->PMC_SR;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_GetInterruptMaskStatus */
+/** \brief Return PMC Interrupt Mask Status */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_PMC_GetInterruptMaskStatus( /* \return PMC Interrupt Mask Status */
+        AT91PS_PMC pPMC )                                   /* pointer to a PMC controller */
+    {
+        return pPMC->PMC_IMR;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_IsInterruptMasked */
+/** \brief Test if PMC Interrupt is Masked */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_PMC_IsInterruptMasked( AT91PS_PMC pPMC,    /* \arg  pointer to a PMC controller */
+                                                       unsigned int flag ) /* \arg  flag to be tested */
+    {
+        return( AT91F_PMC_GetInterruptMaskStatus( pPMC ) & flag );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_IsStatusSet */
+/** \brief Test if PMC Status is Set */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_PMC_IsStatusSet( AT91PS_PMC pPMC,    /* \arg  pointer to a PMC controller */
+                                                 unsigned int flag ) /* \arg  flag to be tested */
+    {
+        return( AT91F_PMC_GetStatus( pPMC ) & flag );
+    } /* *****************************************************************************
+      *              SOFTWARE API FOR RSTC
+      ***************************************************************************** */
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_RSTSoftReset */
+/** \brief Start Software Reset */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_RSTSoftReset( AT91PS_RSTC pRSTC,
+                                      unsigned int reset )
+    {
+        pRSTC->RSTC_RCR = ( 0xA5000000 | reset );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_RSTSetMode */
+/** \brief Set Reset Mode */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_RSTSetMode( AT91PS_RSTC pRSTC,
+                                    unsigned int mode )
+    {
+        pRSTC->RSTC_RMR = ( 0xA5000000 | mode );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_RSTGetMode */
+/** \brief Get Reset Mode */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_RSTGetMode( AT91PS_RSTC pRSTC )
+    {
+        return( pRSTC->RSTC_RMR );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_RSTGetStatus */
+/** \brief Get Reset Status */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_RSTGetStatus( AT91PS_RSTC pRSTC )
+    {
+        return( pRSTC->RSTC_RSR );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_RSTIsSoftRstActive */
+/** \brief Return !=0 if software reset is still not completed */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_RSTIsSoftRstActive( AT91PS_RSTC pRSTC )
+    {
+        return( ( pRSTC->RSTC_RSR ) & AT91C_RSTC_SRCMP );
+    }
+
+/* *****************************************************************************
+*               SOFTWARE API FOR RTTC
+***************************************************************************** */
+/**-------------------------------------------------------------------------------------- */
+/** \fn     AT91F_SetRTT_TimeBase() */
+/** \brief  Set the RTT prescaler according to the TimeBase in ms */
+/**-------------------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_RTTSetTimeBase( AT91PS_RTTC pRTTC,
+                                                unsigned int ms )
+    {
+        if( ms > 2000 )
+        {
+            return 1; /* AT91C_TIME_OUT_OF_RANGE */
+        }
+
+        pRTTC->RTTC_RTMR &= ~0xFFFF;
+        pRTTC->RTTC_RTMR |= ( ( ( ms << 15 ) / 1000 ) & 0xFFFF );
+        return 0;
+    }
+
+/**-------------------------------------------------------------------------------------- */
+/** \fn     AT91F_RTTSetPrescaler() */
+/** \brief  Set the new prescaler value */
+/**-------------------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_RTTSetPrescaler( AT91PS_RTTC pRTTC,
+                                                 unsigned int rtpres )
+    {
+        pRTTC->RTTC_RTMR &= ~0xFFFF;
+        pRTTC->RTTC_RTMR |= ( rtpres & 0xFFFF );
+        return( pRTTC->RTTC_RTMR );
+    }
+
+/**-------------------------------------------------------------------------------------- */
+/** \fn     AT91F_RTTRestart() */
+/** \brief  Restart the RTT prescaler */
+/**-------------------------------------------------------------------------------------- */
+    __inline void AT91F_RTTRestart( AT91PS_RTTC pRTTC )
+    {
+        pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTRST;
+    }
+
+
+/**-------------------------------------------------------------------------------------- */
+/** \fn     AT91F_RTT_SetAlarmINT() */
+/** \brief  Enable RTT Alarm Interrupt */
+/**-------------------------------------------------------------------------------------- */
+    __inline void AT91F_RTTSetAlarmINT( AT91PS_RTTC pRTTC )
+    {
+        pRTTC->RTTC_RTMR |= AT91C_RTTC_ALMIEN;
+    }
+
+/**-------------------------------------------------------------------------------------- */
+/** \fn     AT91F_RTT_ClearAlarmINT() */
+/** \brief  Disable RTT Alarm Interrupt */
+/**-------------------------------------------------------------------------------------- */
+    __inline void AT91F_RTTClearAlarmINT( AT91PS_RTTC pRTTC )
+    {
+        pRTTC->RTTC_RTMR &= ~AT91C_RTTC_ALMIEN;
+    }
+
+/**-------------------------------------------------------------------------------------- */
+/** \fn     AT91F_RTT_SetRttIncINT() */
+/** \brief  Enable RTT INC Interrupt */
+/**-------------------------------------------------------------------------------------- */
+    __inline void AT91F_RTTSetRttIncINT( AT91PS_RTTC pRTTC )
+    {
+        pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTINCIEN;
+    }
+
+/**-------------------------------------------------------------------------------------- */
+/** \fn     AT91F_RTT_ClearRttIncINT() */
+/** \brief  Disable RTT INC Interrupt */
+/**-------------------------------------------------------------------------------------- */
+    __inline void AT91F_RTTClearRttIncINT( AT91PS_RTTC pRTTC )
+    {
+        pRTTC->RTTC_RTMR &= ~AT91C_RTTC_RTTINCIEN;
+    }
+
+/**-------------------------------------------------------------------------------------- */
+/** \fn     AT91F_RTT_SetAlarmValue() */
+/** \brief  Set RTT Alarm Value */
+/**-------------------------------------------------------------------------------------- */
+    __inline void AT91F_RTTSetAlarmValue( AT91PS_RTTC pRTTC,
+                                          unsigned int alarm )
+    {
+        pRTTC->RTTC_RTAR = alarm;
+    }
+
+/**-------------------------------------------------------------------------------------- */
+/** \fn     AT91F_RTT_GetAlarmValue() */
+/** \brief  Get RTT Alarm Value */
+/**-------------------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_RTTGetAlarmValue( AT91PS_RTTC pRTTC )
+    {
+        return( pRTTC->RTTC_RTAR );
+    }
+
+/**-------------------------------------------------------------------------------------- */
+/** \fn     AT91F_RTTGetStatus() */
+/** \brief  Read the RTT status */
+/**-------------------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_RTTGetStatus( AT91PS_RTTC pRTTC )
+    {
+        return( pRTTC->RTTC_RTSR );
+    }
+
+/**-------------------------------------------------------------------------------------- */
+/** \fn     AT91F_RTT_ReadValue() */
+/** \brief  Read the RTT value */
+/**-------------------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_RTTReadValue( AT91PS_RTTC pRTTC )
+    {
+        register volatile unsigned int val1, val2;
+
+        do
+        {
+            val1 = pRTTC->RTTC_RTVR;
+            val2 = pRTTC->RTTC_RTVR;
+        }
+        while( val1 != val2 );
+
+        return( val1 );
+    }
+
+/* *****************************************************************************
+*               SOFTWARE API FOR PITC
+***************************************************************************** */
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PITInit */
+/** \brief System timer init : period in */
diff --git a/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X256.h b/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X256.h
index 556e0ca16..0d9a70884 100644
--- a/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X256.h
+++ b/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X256.h
@@ -1,1469 +1,1396 @@
-//* ----------------------------------------------------------------------------
-//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
-//* ----------------------------------------------------------------------------
-//* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
-//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
-//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
-//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
-//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//* ----------------------------------------------------------------------------
-//* File Name           : lib_AT91SAM7X256.h
-//* Object              : AT91SAM7X256 inlined functions
-//* Generated           : AT91 SW Application Group  05/20/2005 (16:22:29)
-//*
-//* CVS Reference       : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003//
-//* CVS Reference       : /lib_pmc_SAM7X.h/1.1/Tue Feb  1 08:32:10 2005//
-//* CVS Reference       : /lib_VREG_6085B.h/1.1/Tue Feb  1 16:20:47 2005//
-//* CVS Reference       : /lib_rstc_6098A.h/1.1/Wed Oct  6 10:39:20 2004//
-//* CVS Reference       : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003//
-//* CVS Reference       : /lib_wdtc_6080A.h/1.1/Wed Oct  6 10:38:30 2004//
-//* CVS Reference       : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002//
-//* CVS Reference       : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003//
-//* CVS Reference       : /lib_pitc_6079A.h/1.2/Tue Nov  9 14:43:56 2004//
-//* CVS Reference       : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005//
-//* CVS Reference       : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005//
-//* CVS Reference       : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004//
-//* CVS Reference       : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003//
-//* CVS Reference       : /lib_rttc_6081A.h/1.1/Wed Oct  6 10:39:38 2004//
-//* CVS Reference       : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005//
-//* CVS Reference       : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005//
-//* CVS Reference       : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//
-//* CVS Reference       : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004//
-//* CVS Reference       : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003//
-//* CVS Reference       : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003//
-//* CVS Reference       : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//
-//* CVS Reference       : /lib_pdc.h/1.2/Tue Jul  2 13:29:40 2002//
-//* ----------------------------------------------------------------------------
+/** ---------------------------------------------------------------------------- */
+/**         ATMEL Microcontroller Software Support  -  ROUSSET  - */
+/** ---------------------------------------------------------------------------- */
+/** DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
+/** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/** MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
+/** DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
+/** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/** LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
+/** OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
+/** LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
+/** NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/** EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
+/** ---------------------------------------------------------------------------- */
+/** File Name           : lib_AT91SAM7X256.h */
+/** Object              : AT91SAM7X256 inlined functions */
+/** Generated           : AT91 SW Application Group  05/20/2005 (16:22:29) */
+/** */
+/** CVS Reference       : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003// */
+/** CVS Reference       : /lib_pmc_SAM7X.h/1.1/Tue Feb  1 08:32:10 2005// */
+/** CVS Reference       : /lib_VREG_6085B.h/1.1/Tue Feb  1 16:20:47 2005// */
+/** CVS Reference       : /lib_rstc_6098A.h/1.1/Wed Oct  6 10:39:20 2004// */
+/** CVS Reference       : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// */
+/** CVS Reference       : /lib_wdtc_6080A.h/1.1/Wed Oct  6 10:38:30 2004// */
+/** CVS Reference       : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002// */
+/** CVS Reference       : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003// */
+/** CVS Reference       : /lib_pitc_6079A.h/1.2/Tue Nov  9 14:43:56 2004// */
+/** CVS Reference       : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005// */
+/** CVS Reference       : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005// */
+/** CVS Reference       : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004// */
+/** CVS Reference       : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003// */
+/** CVS Reference       : /lib_rttc_6081A.h/1.1/Wed Oct  6 10:39:38 2004// */
+/** CVS Reference       : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005// */
+/** CVS Reference       : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005// */
+/** CVS Reference       : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// */
+/** CVS Reference       : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004// */
+/** CVS Reference       : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// */
+/** CVS Reference       : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003// */
+/** CVS Reference       : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// */
+/** CVS Reference       : /lib_pdc.h/1.2/Tue Jul  2 13:29:40 2002// */
+/** ---------------------------------------------------------------------------- */
 
 #ifndef lib_AT91SAM7X256_H
-#define lib_AT91SAM7X256_H
+    #define lib_AT91SAM7X256_H
 
 /* *****************************************************************************
-                SOFTWARE API FOR AIC
-   ***************************************************************************** */
-#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20]
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_ConfigureIt
-//* \brief Interrupt Handler Initialization
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_AIC_ConfigureIt (
-    AT91PS_AIC pAic,  // \arg pointer to the AIC registers
-    unsigned int irq_id,     // \arg interrupt number to initialize
-    unsigned int priority,   // \arg priority to give to the interrupt
-    unsigned int src_type,   // \arg activation and sense of activation
-    void (*newHandler) (void) ) // \arg address of the interrupt handler
-{
-    unsigned int oldHandler;
-    unsigned int mask ;
-
-    oldHandler = pAic->AIC_SVR[irq_id];
-
-    mask = 0x1 << irq_id ;
-    //* Disable the interrupt on the interrupt controller
-    pAic->AIC_IDCR = mask ;
-    //* Save the interrupt handler routine pointer and the interrupt priority
-    pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ;
-    //* Store the Source Mode Register
-    pAic->AIC_SMR[irq_id] = src_type | priority  ;
-    //* Clear the interrupt on the interrupt controller
-    pAic->AIC_ICCR = mask ;
-
-    return oldHandler;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_EnableIt
-//* \brief Enable corresponding IT number
-//*----------------------------------------------------------------------------
-__inline void AT91F_AIC_EnableIt (
-    AT91PS_AIC pAic,      // \arg pointer to the AIC registers
-    unsigned int irq_id ) // \arg interrupt number to initialize
-{
-    //* Enable the interrupt on the interrupt controller
-    pAic->AIC_IECR = 0x1 << irq_id ;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_DisableIt
-//* \brief Disable corresponding IT number
-//*----------------------------------------------------------------------------
-__inline void AT91F_AIC_DisableIt (
-    AT91PS_AIC pAic,      // \arg pointer to the AIC registers
-    unsigned int irq_id ) // \arg interrupt number to initialize
-{
-    unsigned int mask = 0x1 << irq_id;
-    //* Disable the interrupt on the interrupt controller
-    pAic->AIC_IDCR = mask ;
-    //* Clear the interrupt on the Interrupt Controller ( if one is pending )
-    pAic->AIC_ICCR = mask ;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_ClearIt
-//* \brief Clear corresponding IT number
-//*----------------------------------------------------------------------------
-__inline void AT91F_AIC_ClearIt (
-    AT91PS_AIC pAic,     // \arg pointer to the AIC registers
-    unsigned int irq_id) // \arg interrupt number to initialize
-{
-    //* Clear the interrupt on the Interrupt Controller ( if one is pending )
-    pAic->AIC_ICCR = (0x1 << irq_id);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_AcknowledgeIt
-//* \brief Acknowledge corresponding IT number
-//*----------------------------------------------------------------------------
-__inline void AT91F_AIC_AcknowledgeIt (
-    AT91PS_AIC pAic)     // \arg pointer to the AIC registers
-{
-    pAic->AIC_EOICR = pAic->AIC_EOICR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_SetExceptionVector
-//* \brief Configure vector handler
-//*----------------------------------------------------------------------------
-__inline unsigned int  AT91F_AIC_SetExceptionVector (
-    unsigned int *pVector, // \arg pointer to the AIC registers
-    void (*Handler) () )   // \arg Interrupt Handler
-{
-    unsigned int oldVector = *pVector;
-
-    if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE)
-        *pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE;
-    else
-        *pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000;
-
-    return oldVector;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_Trig
-//* \brief Trig an IT
-//*----------------------------------------------------------------------------
-__inline void  AT91F_AIC_Trig (
-    AT91PS_AIC pAic,     // \arg pointer to the AIC registers
-    unsigned int irq_id) // \arg interrupt number
-{
-    pAic->AIC_ISCR = (0x1 << irq_id) ;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_IsActive
-//* \brief Test if an IT is active
-//*----------------------------------------------------------------------------
-__inline unsigned int  AT91F_AIC_IsActive (
-    AT91PS_AIC pAic,     // \arg pointer to the AIC registers
-    unsigned int irq_id) // \arg Interrupt Number
-{
-    return (pAic->AIC_ISR & (0x1 << irq_id));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_IsPending
-//* \brief Test if an IT is pending
-//*----------------------------------------------------------------------------
-__inline unsigned int  AT91F_AIC_IsPending (
-    AT91PS_AIC pAic,     // \arg pointer to the AIC registers
-    unsigned int irq_id) // \arg Interrupt Number
-{
-    return (pAic->AIC_IPR & (0x1 << irq_id));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_Open
-//* \brief Set exception vectors and AIC registers to default values
-//*----------------------------------------------------------------------------
-__inline void AT91F_AIC_Open(
-    AT91PS_AIC pAic,        // \arg pointer to the AIC registers
-    void (*IrqHandler) (),  // \arg Default IRQ vector exception
-    void (*FiqHandler) (),  // \arg Default FIQ vector exception
-    void (*DefaultHandler)  (), // \arg Default Handler set in ISR
-    void (*SpuriousHandler) (), // \arg Default Spurious Handler
-    unsigned int protectMode)   // \arg Debug Control Register
-{
-    int i;
-
-    // Disable all interrupts and set IVR to the default handler
-    for (i = 0; i < 32; ++i) {
-        AT91F_AIC_DisableIt(pAic, i);
-        AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_HIGH_LEVEL, DefaultHandler);
-    }
-
-    // Set the IRQ exception vector
-    AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler);
-    // Set the Fast Interrupt exception vector
-    AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler);
-
-    pAic->AIC_SPU = (unsigned int) SpuriousHandler;
-    pAic->AIC_DCR = protectMode;
-}
-/* *****************************************************************************
-                SOFTWARE API FOR PDC
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_SetNextRx
-//* \brief Set the next receive transfer descriptor
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_SetNextRx (
-    AT91PS_PDC pPDC,     // \arg pointer to a PDC controller
-    char *address,       // \arg address to the next bloc to be received
-    unsigned int bytes)  // \arg number of bytes to be received
-{
-    pPDC->PDC_RNPR = (unsigned int) address;
-    pPDC->PDC_RNCR = bytes;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_SetNextTx
-//* \brief Set the next transmit transfer descriptor
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_SetNextTx (
-    AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
-    char *address,         // \arg address to the next bloc to be transmitted
-    unsigned int bytes)    // \arg number of bytes to be transmitted
-{
-    pPDC->PDC_TNPR = (unsigned int) address;
-    pPDC->PDC_TNCR = bytes;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_SetRx
-//* \brief Set the receive transfer descriptor
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_SetRx (
-    AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
-    char *address,         // \arg address to the next bloc to be received
-    unsigned int bytes)    // \arg number of bytes to be received
-{
-    pPDC->PDC_RPR = (unsigned int) address;
-    pPDC->PDC_RCR = bytes;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_SetTx
-//* \brief Set the transmit transfer descriptor
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_SetTx (
-    AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
-    char *address,         // \arg address to the next bloc to be transmitted
-    unsigned int bytes)    // \arg number of bytes to be transmitted
-{
-    pPDC->PDC_TPR = (unsigned int) address;
-    pPDC->PDC_TCR = bytes;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_EnableTx
-//* \brief Enable transmit
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_EnableTx (
-    AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-    pPDC->PDC_PTCR = AT91C_PDC_TXTEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_EnableRx
-//* \brief Enable receive
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_EnableRx (
-    AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-    pPDC->PDC_PTCR = AT91C_PDC_RXTEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_DisableTx
-//* \brief Disable transmit
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_DisableTx (
-    AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-    pPDC->PDC_PTCR = AT91C_PDC_TXTDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_DisableRx
-//* \brief Disable receive
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_DisableRx (
-    AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-    pPDC->PDC_PTCR = AT91C_PDC_RXTDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_IsTxEmpty
-//* \brief Test if the current transfer descriptor has been sent
-//*----------------------------------------------------------------------------
-__inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete
-    AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-    return !(pPDC->PDC_TCR);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_IsNextTxEmpty
-//* \brief Test if the next transfer descriptor has been moved to the current td
-//*----------------------------------------------------------------------------
-__inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete
-    AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-    return !(pPDC->PDC_TNCR);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_IsRxEmpty
-//* \brief Test if the current transfer descriptor has been filled
-//*----------------------------------------------------------------------------
-__inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete
-    AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-    return !(pPDC->PDC_RCR);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_IsNextRxEmpty
-//* \brief Test if the next transfer descriptor has been moved to the current td
-//*----------------------------------------------------------------------------
-__inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete
-    AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-    return !(pPDC->PDC_RNCR);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_Open
-//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_Open (
-    AT91PS_PDC pPDC)       // \arg pointer to a PDC controller
-{
-    //* Disable the RX and TX PDC transfer requests
-    AT91F_PDC_DisableRx(pPDC);
-    AT91F_PDC_DisableTx(pPDC);
-
-    //* Reset all Counter register Next buffer first
-    AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);
-    AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);
-    AT91F_PDC_SetTx(pPDC, (char *) 0, 0);
-    AT91F_PDC_SetRx(pPDC, (char *) 0, 0);
-
-    //* Enable the RX and TX PDC transfer requests
-    AT91F_PDC_EnableRx(pPDC);
-    AT91F_PDC_EnableTx(pPDC);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_Close
-//* \brief Close PDC: disable TX and RX reset transfer descriptors
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_Close (
-    AT91PS_PDC pPDC)       // \arg pointer to a PDC controller
-{
-    //* Disable the RX and TX PDC transfer requests
-    AT91F_PDC_DisableRx(pPDC);
-    AT91F_PDC_DisableTx(pPDC);
-
-    //* Reset all Counter register Next buffer first
-    AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);
-    AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);
-    AT91F_PDC_SetTx(pPDC, (char *) 0, 0);
-    AT91F_PDC_SetRx(pPDC, (char *) 0, 0);
-
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_SendFrame
-//* \brief Close PDC: disable TX and RX reset transfer descriptors
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PDC_SendFrame(
-    AT91PS_PDC pPDC,
-    char *pBuffer,
-    unsigned int szBuffer,
-    char *pNextBuffer,
-    unsigned int szNextBuffer )
-{
-    if (AT91F_PDC_IsTxEmpty(pPDC)) {
-        //* Buffer and next buffer can be initialized
-        AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer);
-        AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer);
-        return 2;
-    }
-    else if (AT91F_PDC_IsNextTxEmpty(pPDC)) {
-        //* Only one buffer can be initialized
-        AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer);
-        return 1;
-    }
-    else {
-        //* All buffer are in use...
-        return 0;
-    }
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_ReceiveFrame
-//* \brief Close PDC: disable TX and RX reset transfer descriptors
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PDC_ReceiveFrame (
-    AT91PS_PDC pPDC,
-    char *pBuffer,
-    unsigned int szBuffer,
-    char *pNextBuffer,
-    unsigned int szNextBuffer )
-{
-    if (AT91F_PDC_IsRxEmpty(pPDC)) {
-        //* Buffer and next buffer can be initialized
-        AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer);
-        AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer);
-        return 2;
-    }
-    else if (AT91F_PDC_IsNextRxEmpty(pPDC)) {
-        //* Only one buffer can be initialized
-        AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer);
-        return 1;
-    }
-    else {
-        //* All buffer are in use...
-        return 0;
-    }
-}
-/* *****************************************************************************
-                SOFTWARE API FOR DBGU
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_DBGU_InterruptEnable
-//* \brief Enable DBGU Interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_DBGU_InterruptEnable(
-        AT91PS_DBGU pDbgu,   // \arg  pointer to a DBGU controller
-        unsigned int flag) // \arg  dbgu interrupt to be enabled
-{
-        pDbgu->DBGU_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_DBGU_InterruptDisable
-//* \brief Disable DBGU Interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_DBGU_InterruptDisable(
-        AT91PS_DBGU pDbgu,   // \arg  pointer to a DBGU controller
-        unsigned int flag) // \arg  dbgu interrupt to be disabled
-{
-        pDbgu->DBGU_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_DBGU_GetInterruptMaskStatus
-//* \brief Return DBGU Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status
-        AT91PS_DBGU pDbgu) // \arg  pointer to a DBGU controller
-{
-        return pDbgu->DBGU_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_DBGU_IsInterruptMasked
-//* \brief Test if DBGU Interrupt is Masked
-//*----------------------------------------------------------------------------
-__inline int AT91F_DBGU_IsInterruptMasked(
-        AT91PS_DBGU pDbgu,   // \arg  pointer to a DBGU controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag);
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR PIO
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgPeriph
-//* \brief Enable pins to be drived by peripheral
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgPeriph(
-    AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-    unsigned int periphAEnable,  // \arg PERIPH A to enable
-    unsigned int periphBEnable)  // \arg PERIPH B to enable
-
-{
-    pPio->PIO_ASR = periphAEnable;
-    pPio->PIO_BSR = periphBEnable;
-    pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgOutput
-//* \brief Enable PIO in output mode
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgOutput(
-    AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-    unsigned int pioEnable)      // \arg PIO to be enabled
-{
-    pPio->PIO_PER = pioEnable; // Set in PIO mode
-    pPio->PIO_OER = pioEnable; // Configure in Output
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgInput
-//* \brief Enable PIO in input mode
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgInput(
-    AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-    unsigned int inputEnable)      // \arg PIO to be enabled
-{
-    // Disable output
-    pPio->PIO_ODR  = inputEnable;
-    pPio->PIO_PER  = inputEnable;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgOpendrain
-//* \brief Configure PIO in open drain
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgOpendrain(
-    AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-    unsigned int multiDrvEnable) // \arg pio to be configured in open drain
-{
-    // Configure the multi-drive option
-    pPio->PIO_MDDR = ~multiDrvEnable;
-    pPio->PIO_MDER = multiDrvEnable;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgPullup
-//* \brief Enable pullup on PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgPullup(
-    AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-    unsigned int pullupEnable)   // \arg enable pullup on PIO
-{
-        // Connect or not Pullup
-    pPio->PIO_PPUDR = ~pullupEnable;
-    pPio->PIO_PPUER = pullupEnable;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgDirectDrive
-//* \brief Enable direct drive on PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgDirectDrive(
-    AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-    unsigned int directDrive)    // \arg PIO to be configured with direct drive
-
-{
-    // Configure the Direct Drive
-    pPio->PIO_OWDR  = ~directDrive;
-    pPio->PIO_OWER  = directDrive;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgInputFilter
-//* \brief Enable input filter on input PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgInputFilter(
-    AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-    unsigned int inputFilter)    // \arg PIO to be configured with input filter
-
-{
-    // Configure the Direct Drive
-    pPio->PIO_IFDR  = ~inputFilter;
-    pPio->PIO_IFER  = inputFilter;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetInput
-//* \brief Return PIO input value
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetInput( // \return PIO input
-    AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-    return pPio->PIO_PDSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsInputSet
-//* \brief Test if PIO is input flag is active
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsInputSet(
-    AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-    unsigned int flag) // \arg  flag to be tested
-{
-    return (AT91F_PIO_GetInput(pPio) & flag);
-}
-
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_SetOutput
-//* \brief Set to 1 output PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_SetOutput(
-    AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-    unsigned int flag) // \arg  output to be set
-{
-    pPio->PIO_SODR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_ClearOutput
-//* \brief Set to 0 output PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_ClearOutput(
-    AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-    unsigned int flag) // \arg  output to be cleared
-{
-    pPio->PIO_CODR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_ForceOutput
-//* \brief Force output when Direct drive option is enabled
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_ForceOutput(
-    AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-    unsigned int flag) // \arg  output to be forced
-{
-    pPio->PIO_ODSR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_Enable
-//* \brief Enable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_Enable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio to be enabled
-{
-        pPio->PIO_PER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_Disable
-//* \brief Disable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_Disable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio to be disabled
-{
-        pPio->PIO_PDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetStatus
-//* \brief Return PIO Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_PSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsSet
-//* \brief Test if PIO is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_OutputEnable
-//* \brief Output Enable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_OutputEnable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio output to be enabled
-{
-        pPio->PIO_OER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_OutputDisable
-//* \brief Output Enable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_OutputDisable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio output to be disabled
-{
-        pPio->PIO_ODR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetOutputStatus
-//* \brief Return PIO Output Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_OSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsOuputSet
-//* \brief Test if PIO Output is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsOutputSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetOutputStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_InputFilterEnable
-//* \brief Input Filter Enable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_InputFilterEnable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio input filter to be enabled
-{
-        pPio->PIO_IFER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_InputFilterDisable
-//* \brief Input Filter Disable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_InputFilterDisable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio input filter to be disabled
-{
-        pPio->PIO_IFDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetInputFilterStatus
-//* \brief Return PIO Input Filter Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_IFSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsInputFilterSet
-//* \brief Test if PIO Input filter is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsInputFilterSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetInputFilterStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetOutputDataStatus
-//* \brief Return PIO Output Data Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status
-    AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_ODSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_InterruptEnable
-//* \brief Enable PIO Interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_InterruptEnable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio interrupt to be enabled
-{
-        pPio->PIO_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_InterruptDisable
-//* \brief Disable PIO Interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_InterruptDisable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio interrupt to be disabled
-{
-        pPio->PIO_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetInterruptMaskStatus
-//* \brief Return PIO Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetInterruptStatus
-//* \brief Return PIO Interrupt Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_ISR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsInterruptMasked
-//* \brief Test if PIO Interrupt is Masked
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsInterruptMasked(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsInterruptSet
-//* \brief Test if PIO Interrupt is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsInterruptSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetInterruptStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_MultiDriverEnable
-//* \brief Multi Driver Enable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_MultiDriverEnable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio to be enabled
-{
-        pPio->PIO_MDER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_MultiDriverDisable
-//* \brief Multi Driver Disable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_MultiDriverDisable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio to be disabled
-{
-        pPio->PIO_MDDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetMultiDriverStatus
-//* \brief Return PIO Multi Driver Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_MDSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsMultiDriverSet
-//* \brief Test if PIO MultiDriver is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsMultiDriverSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_A_RegisterSelection
-//* \brief PIO A Register Selection
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_A_RegisterSelection(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio A register selection
-{
-        pPio->PIO_ASR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_B_RegisterSelection
-//* \brief PIO B Register Selection
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_B_RegisterSelection(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio B register selection
-{
-        pPio->PIO_BSR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_Get_AB_RegisterStatus
-//* \brief Return PIO Interrupt Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_ABSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsAB_RegisterSet
-//* \brief Test if PIO AB Register is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsAB_RegisterSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_OutputWriteEnable
-//* \brief Output Write Enable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_OutputWriteEnable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio output write to be enabled
-{
-        pPio->PIO_OWER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_OutputWriteDisable
-//* \brief Output Write Disable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_OutputWriteDisable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio output write to be disabled
-{
-        pPio->PIO_OWDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetOutputWriteStatus
-//* \brief Return PIO Output Write Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_OWSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsOutputWriteSet
-//* \brief Test if PIO OutputWrite is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsOutputWriteSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetCfgPullup
-//* \brief Return PIO Configuration Pullup
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_PPUSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsOutputDataStatusSet
-//* \brief Test if PIO Output Data Status is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsOutputDataStatusSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetOutputDataStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsCfgPullupStatusSet
-//* \brief Test if PIO Configuration Pullup Status is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsCfgPullupStatusSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (~AT91F_PIO_GetCfgPullup(pPio) & flag);
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR PMC
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_CfgSysClkEnableReg
-//* \brief Configure the System Clock Enable Register of the PMC controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_CfgSysClkEnableReg (
-    AT91PS_PMC pPMC, // \arg pointer to PMC controller
-    unsigned int mode)
-{
-    //* Write to the SCER register
-    pPMC->PMC_SCER = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_CfgSysClkDisableReg
-//* \brief Configure the System Clock Disable Register of the PMC controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_CfgSysClkDisableReg (
-    AT91PS_PMC pPMC, // \arg pointer to PMC controller
-    unsigned int mode)
-{
-    //* Write to the SCDR register
-    pPMC->PMC_SCDR = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_GetSysClkStatusReg
-//* \brief Return the System Clock Status Register of the PMC controller
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_GetSysClkStatusReg (
-    AT91PS_PMC pPMC // pointer to a CAN controller
-    )
-{
-    return pPMC->PMC_SCSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_EnablePeriphClock
-//* \brief Enable peripheral clock
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_EnablePeriphClock (
-    AT91PS_PMC pPMC, // \arg pointer to PMC controller
-    unsigned int periphIds)  // \arg IDs of peripherals to enable
-{
-    pPMC->PMC_PCER = periphIds;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_DisablePeriphClock
-//* \brief Disable peripheral clock
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_DisablePeriphClock (
-    AT91PS_PMC pPMC, // \arg pointer to PMC controller
-    unsigned int periphIds)  // \arg IDs of peripherals to enable
-{
-    pPMC->PMC_PCDR = periphIds;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_GetPeriphClock
-//* \brief Get peripheral clock status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_GetPeriphClock (
-    AT91PS_PMC pPMC) // \arg pointer to PMC controller
-{
-    return pPMC->PMC_PCSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CKGR_CfgMainOscillatorReg
-//* \brief Cfg the main oscillator
-//*----------------------------------------------------------------------------
-__inline void AT91F_CKGR_CfgMainOscillatorReg (
-    AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
-    unsigned int mode)
-{
-    pCKGR->CKGR_MOR = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CKGR_GetMainOscillatorReg
-//* \brief Cfg the main oscillator
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CKGR_GetMainOscillatorReg (
-    AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
-{
-    return pCKGR->CKGR_MOR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CKGR_EnableMainOscillator
-//* \brief Enable the main oscillator
-//*----------------------------------------------------------------------------
-__inline void AT91F_CKGR_EnableMainOscillator(
-    AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
-{
-    pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CKGR_DisableMainOscillator
-//* \brief Disable the main oscillator
-//*----------------------------------------------------------------------------
-__inline void AT91F_CKGR_DisableMainOscillator (
-    AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
-{
-    pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CKGR_CfgMainOscStartUpTime
-//* \brief Cfg MOR Register according to the main osc startup time
-//*----------------------------------------------------------------------------
-__inline void AT91F_CKGR_CfgMainOscStartUpTime (
-    AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
-    unsigned int startup_time,  // \arg main osc startup time in microsecond (us)
-    unsigned int slowClock)  // \arg slowClock in Hz
-{
-    pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT;
-    pCKGR->CKGR_MOR |= ((slowClock * startup_time)/(8*1000000)) << 8;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CKGR_GetMainClockFreqReg
-//* \brief Cfg the main oscillator
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CKGR_GetMainClockFreqReg (
-    AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
-{
-    return pCKGR->CKGR_MCFR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CKGR_GetMainClock
-//* \brief Return Main clock in Hz
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CKGR_GetMainClock (
-    AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
-    unsigned int slowClock)  // \arg slowClock in Hz
-{
-    return ((pCKGR->CKGR_MCFR  & AT91C_CKGR_MAINF) * slowClock) >> 4;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_CfgMCKReg
-//* \brief Cfg Master Clock Register
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_CfgMCKReg (
-    AT91PS_PMC pPMC, // \arg pointer to PMC controller
-    unsigned int mode)
-{
-    pPMC->PMC_MCKR = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_GetMCKReg
-//* \brief Return Master Clock Register
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_GetMCKReg(
-    AT91PS_PMC pPMC) // \arg pointer to PMC controller
-{
-    return pPMC->PMC_MCKR;
-}
-
-//*------------------------------------------------------------------------------
-//* \fn    AT91F_PMC_GetMasterClock
-//* \brief Return master clock in Hz which correponds to processor clock for ARM7
-//*------------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_GetMasterClock (
-    AT91PS_PMC pPMC, // \arg pointer to PMC controller
-    AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
-    unsigned int slowClock)  // \arg slowClock in Hz
-{
-    unsigned int reg = pPMC->PMC_MCKR;
-    unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2));
-    unsigned int pllDivider, pllMultiplier;
-
-    switch (reg & AT91C_PMC_CSS) {
-        case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected
-            return slowClock / prescaler;
-        case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected
-            return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler;
-        case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected
-            reg = pCKGR->CKGR_PLLR;
-            pllDivider    = (reg  & AT91C_CKGR_DIV);
-            pllMultiplier = ((reg  & AT91C_CKGR_MUL) >> 16) + 1;
-            return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler;
-    }
-    return 0;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_EnablePCK
-//* \brief Enable peripheral clock
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_EnablePCK (
-    AT91PS_PMC pPMC, // \arg pointer to PMC controller
-    unsigned int pck,  // \arg Peripheral clock identifier 0 .. 7
-    unsigned int mode)
-{
-    pPMC->PMC_PCKR[pck] = mode;
-    pPMC->PMC_SCER = (1 << pck) << 8;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_DisablePCK
-//* \brief Enable peripheral clock
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_DisablePCK (
-    AT91PS_PMC pPMC, // \arg pointer to PMC controller
-    unsigned int pck)  // \arg Peripheral clock identifier 0 .. 7
-{
-    pPMC->PMC_SCDR = (1 << pck) << 8;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_EnableIt
-//* \brief Enable PMC interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_EnableIt (
-    AT91PS_PMC pPMC,     // pointer to a PMC controller
-    unsigned int flag)   // IT to be enabled
-{
-    //* Write to the IER register
-    pPMC->PMC_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_DisableIt
-//* \brief Disable PMC interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_DisableIt (
-    AT91PS_PMC pPMC, // pointer to a PMC controller
-    unsigned int flag) // IT to be disabled
-{
-    //* Write to the IDR register
-    pPMC->PMC_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_GetStatus
-//* \brief Return PMC Interrupt Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_GetStatus( // \return PMC Interrupt Status
-    AT91PS_PMC pPMC) // pointer to a PMC controller
-{
-    return pPMC->PMC_SR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_GetInterruptMaskStatus
-//* \brief Return PMC Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status
-    AT91PS_PMC pPMC) // pointer to a PMC controller
-{
-    return pPMC->PMC_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_IsInterruptMasked
-//* \brief Test if PMC Interrupt is Masked
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_IsInterruptMasked(
-        AT91PS_PMC pPMC,   // \arg  pointer to a PMC controller
-        unsigned int flag) // \arg  flag to be tested
-{
-    return (AT91F_PMC_GetInterruptMaskStatus(pPMC) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_IsStatusSet
-//* \brief Test if PMC Status is Set
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_IsStatusSet(
-        AT91PS_PMC pPMC,   // \arg  pointer to a PMC controller
-        unsigned int flag) // \arg  flag to be tested
-{
-    return (AT91F_PMC_GetStatus(pPMC) & flag);
-}/* *****************************************************************************
-                SOFTWARE API FOR RSTC
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_RSTSoftReset
-//* \brief Start Software Reset
-//*----------------------------------------------------------------------------
-__inline void AT91F_RSTSoftReset(
-        AT91PS_RSTC pRSTC,
-        unsigned int reset)
-{
-    pRSTC->RSTC_RCR = (0xA5000000 | reset);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_RSTSetMode
-//* \brief Set Reset Mode
-//*----------------------------------------------------------------------------
-__inline void AT91F_RSTSetMode(
-        AT91PS_RSTC pRSTC,
-        unsigned int mode)
-{
-    pRSTC->RSTC_RMR = (0xA5000000 | mode);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_RSTGetMode
-//* \brief Get Reset Mode
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_RSTGetMode(
-        AT91PS_RSTC pRSTC)
-{
-    return (pRSTC->RSTC_RMR);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_RSTGetStatus
-//* \brief Get Reset Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_RSTGetStatus(
-        AT91PS_RSTC pRSTC)
-{
-    return (pRSTC->RSTC_RSR);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_RSTIsSoftRstActive
-//* \brief Return !=0 if software reset is still not completed
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_RSTIsSoftRstActive(
-        AT91PS_RSTC pRSTC)
-{
-    return ((pRSTC->RSTC_RSR) & AT91C_RSTC_SRCMP);
-}
-/* *****************************************************************************
-                SOFTWARE API FOR RTTC
-   ***************************************************************************** */
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_SetRTT_TimeBase()
-//* \brief  Set the RTT prescaler according to the TimeBase in ms
-//*--------------------------------------------------------------------------------------
-__inline unsigned int AT91F_RTTSetTimeBase(
-        AT91PS_RTTC pRTTC,
-        unsigned int ms)
-{
-    if (ms > 2000)
-        return 1;   // AT91C_TIME_OUT_OF_RANGE
-    pRTTC->RTTC_RTMR &= ~0xFFFF;
-    pRTTC->RTTC_RTMR |= (((ms << 15) /1000) & 0xFFFF);
-    return 0;
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_RTTSetPrescaler()
-//* \brief  Set the new prescaler value
-//*--------------------------------------------------------------------------------------
-__inline unsigned int AT91F_RTTSetPrescaler(
-        AT91PS_RTTC pRTTC,
-        unsigned int rtpres)
-{
-    pRTTC->RTTC_RTMR &= ~0xFFFF;
-    pRTTC->RTTC_RTMR |= (rtpres & 0xFFFF);
-    return (pRTTC->RTTC_RTMR);
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_RTTRestart()
-//* \brief  Restart the RTT prescaler
-//*--------------------------------------------------------------------------------------
-__inline void AT91F_RTTRestart(
-        AT91PS_RTTC pRTTC)
-{
-    pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTRST;
-}
-
-
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_RTT_SetAlarmINT()
-//* \brief  Enable RTT Alarm Interrupt
-//*--------------------------------------------------------------------------------------
-__inline void AT91F_RTTSetAlarmINT(
-        AT91PS_RTTC pRTTC)
-{
-    pRTTC->RTTC_RTMR |= AT91C_RTTC_ALMIEN;
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_RTT_ClearAlarmINT()
-//* \brief  Disable RTT Alarm Interrupt
-//*--------------------------------------------------------------------------------------
-__inline void AT91F_RTTClearAlarmINT(
-        AT91PS_RTTC pRTTC)
-{
-    pRTTC->RTTC_RTMR &= ~AT91C_RTTC_ALMIEN;
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_RTT_SetRttIncINT()
-//* \brief  Enable RTT INC Interrupt
-//*--------------------------------------------------------------------------------------
-__inline void AT91F_RTTSetRttIncINT(
-        AT91PS_RTTC pRTTC)
-{
-    pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTINCIEN;
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_RTT_ClearRttIncINT()
-//* \brief  Disable RTT INC Interrupt
-//*--------------------------------------------------------------------------------------
-__inline void AT91F_RTTClearRttIncINT(
-        AT91PS_RTTC pRTTC)
-{
-    pRTTC->RTTC_RTMR &= ~AT91C_RTTC_RTTINCIEN;
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_RTT_SetAlarmValue()
-//* \brief  Set RTT Alarm Value
-//*--------------------------------------------------------------------------------------
-__inline void AT91F_RTTSetAlarmValue(
-        AT91PS_RTTC pRTTC, unsigned int alarm)
-{
-    pRTTC->RTTC_RTAR = alarm;
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_RTT_GetAlarmValue()
-//* \brief  Get RTT Alarm Value
-//*--------------------------------------------------------------------------------------
-__inline unsigned int AT91F_RTTGetAlarmValue(
-        AT91PS_RTTC pRTTC)
-{
-    return(pRTTC->RTTC_RTAR);
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_RTTGetStatus()
-//* \brief  Read the RTT status
-//*--------------------------------------------------------------------------------------
-__inline unsigned int AT91F_RTTGetStatus(
-        AT91PS_RTTC pRTTC)
-{
-    return(pRTTC->RTTC_RTSR);
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_RTT_ReadValue()
-//* \brief  Read the RTT value
-//*--------------------------------------------------------------------------------------
-__inline unsigned int AT91F_RTTReadValue(
-        AT91PS_RTTC pRTTC)
-{
-        register volatile unsigned int val1,val2;
-    do
+*               SOFTWARE API FOR AIC
+***************************************************************************** */
+    #define AT91C_AIC_BRANCH_OPCODE    ( ( void ( * )() ) 0xE51FFF20 ) /* ldr, pc, [pc, #-&F20] */
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_AIC_ConfigureIt */
+/** \brief Interrupt Handler Initialization */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_AIC_ConfigureIt( AT91PS_AIC pAic,                /* \arg pointer to the AIC registers */
+                                                 unsigned int irq_id,            /* \arg interrupt number to initialize */
+                                                 unsigned int priority,          /* \arg priority to give to the interrupt */
+                                                 unsigned int src_type,          /* \arg activation and sense of activation */
+                                                 void ( * newHandler )( void ) ) /* \arg address of the interrupt handler */
     {
-        val1 = pRTTC->RTTC_RTVR;
-        val2 = pRTTC->RTTC_RTVR;
+        unsigned int oldHandler;
+        unsigned int mask;
+
+        oldHandler = pAic->AIC_SVR[ irq_id ];
+
+        mask = 0x1 << irq_id;
+        /** Disable the interrupt on the interrupt controller */
+        pAic->AIC_IDCR = mask;
+        /** Save the interrupt handler routine pointer and the interrupt priority */
+        pAic->AIC_SVR[ irq_id ] = ( unsigned int ) newHandler;
+        /** Store the Source Mode Register */
+        pAic->AIC_SMR[ irq_id ] = src_type | priority;
+        /** Clear the interrupt on the interrupt controller */
+        pAic->AIC_ICCR = mask;
+
+        return oldHandler;
     }
-    while(val1 != val2);
-    return(val1);
-}
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_AIC_EnableIt */
+/** \brief Enable corresponding IT number */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_AIC_EnableIt( AT91PS_AIC pAic,      /* \arg pointer to the AIC registers */
+                                      unsigned int irq_id ) /* \arg interrupt number to initialize */
+    {
+        /** Enable the interrupt on the interrupt controller */
+        pAic->AIC_IECR = 0x1 << irq_id;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_AIC_DisableIt */
+/** \brief Disable corresponding IT number */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_AIC_DisableIt( AT91PS_AIC pAic,      /* \arg pointer to the AIC registers */
+                                       unsigned int irq_id ) /* \arg interrupt number to initialize */
+    {
+        unsigned int mask = 0x1 << irq_id;
+
+        /** Disable the interrupt on the interrupt controller */
+        pAic->AIC_IDCR = mask;
+        /** Clear the interrupt on the Interrupt Controller ( if one is pending ) */
+        pAic->AIC_ICCR = mask;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_AIC_ClearIt */
+/** \brief Clear corresponding IT number */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_AIC_ClearIt( AT91PS_AIC pAic,      /* \arg pointer to the AIC registers */
+                                     unsigned int irq_id ) /* \arg interrupt number to initialize */
+    {
+        /** Clear the interrupt on the Interrupt Controller ( if one is pending ) */
+        pAic->AIC_ICCR = ( 0x1 << irq_id );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_AIC_AcknowledgeIt */
+/** \brief Acknowledge corresponding IT number */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_AIC_AcknowledgeIt( AT91PS_AIC pAic ) /* \arg pointer to the AIC registers */
+    {
+        pAic->AIC_EOICR = pAic->AIC_EOICR;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_AIC_SetExceptionVector */
+/** \brief Configure vector handler */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_AIC_SetExceptionVector( unsigned int * pVector, /* \arg pointer to the AIC registers */
+                                                        void ( * Handler )() )  /* \arg Interrupt Handler */
+    {
+        unsigned int oldVector = *pVector;
+
+        if( ( unsigned int ) Handler == ( unsigned int ) AT91C_AIC_BRANCH_OPCODE )
+        {
+            *pVector = ( unsigned int ) AT91C_AIC_BRANCH_OPCODE;
+        }
+        else
+        {
+            *pVector = ( ( ( ( ( unsigned int ) Handler ) - ( ( unsigned int ) pVector ) - 0x8 ) >> 2 ) & 0x00FFFFFF ) | 0xEA000000;
+        }
+
+        return oldVector;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_AIC_Trig */
+/** \brief Trig an IT */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_AIC_Trig( AT91PS_AIC pAic,      /* \arg pointer to the AIC registers */
+                                  unsigned int irq_id ) /* \arg interrupt number */
+    {
+        pAic->AIC_ISCR = ( 0x1 << irq_id );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_AIC_IsActive */
+/** \brief Test if an IT is active */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_AIC_IsActive( AT91PS_AIC pAic,      /* \arg pointer to the AIC registers */
+                                              unsigned int irq_id ) /* \arg Interrupt Number */
+    {
+        return( pAic->AIC_ISR & ( 0x1 << irq_id ) );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_AIC_IsPending */
+/** \brief Test if an IT is pending */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_AIC_IsPending( AT91PS_AIC pAic,      /* \arg pointer to the AIC registers */
+                                               unsigned int irq_id ) /* \arg Interrupt Number */
+    {
+        return( pAic->AIC_IPR & ( 0x1 << irq_id ) );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_AIC_Open */
+/** \brief Set exception vectors and AIC registers to default values */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_AIC_Open( AT91PS_AIC pAic,              /* \arg pointer to the AIC registers */
+                                  void ( * IrqHandler )(),      /* \arg Default IRQ vector exception */
+                                  void ( * FiqHandler )(),      /* \arg Default FIQ vector exception */
+                                  void ( * DefaultHandler )(),  /* \arg Default Handler set in ISR */
+                                  void ( * SpuriousHandler )(), /* \arg Default Spurious Handler */
+                                  unsigned int protectMode )    /* \arg Debug Control Register */
+    {
+        int i;
+
+        /* Disable all interrupts and set IVR to the default handler */
+        for( i = 0; i < 32; ++i )
+        {
+            AT91F_AIC_DisableIt( pAic, i );
+            AT91F_AIC_ConfigureIt( pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_HIGH_LEVEL, DefaultHandler );
+        }
+
+        /* Set the IRQ exception vector */
+        AT91F_AIC_SetExceptionVector( ( unsigned int * ) 0x18, IrqHandler );
+        /* Set the Fast Interrupt exception vector */
+        AT91F_AIC_SetExceptionVector( ( unsigned int * ) 0x1C, FiqHandler );
+
+        pAic->AIC_SPU = ( unsigned int ) SpuriousHandler;
+        pAic->AIC_DCR = protectMode;
+    }
+
 /* *****************************************************************************
-                SOFTWARE API FOR PITC
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PITInit
-//* \brief System timer init : period in
\ No newline at end of file
+*               SOFTWARE API FOR PDC
+***************************************************************************** */
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_SetNextRx */
+/** \brief Set the next receive transfer descriptor */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PDC_SetNextRx( AT91PS_PDC pPDC,     /* \arg pointer to a PDC controller */
+                                       char * address,      /* \arg address to the next bloc to be received */
+                                       unsigned int bytes ) /* \arg number of bytes to be received */
+    {
+        pPDC->PDC_RNPR = ( unsigned int ) address;
+        pPDC->PDC_RNCR = bytes;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_SetNextTx */
+/** \brief Set the next transmit transfer descriptor */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PDC_SetNextTx( AT91PS_PDC pPDC,     /* \arg pointer to a PDC controller */
+                                       char * address,      /* \arg address to the next bloc to be transmitted */
+                                       unsigned int bytes ) /* \arg number of bytes to be transmitted */
+    {
+        pPDC->PDC_TNPR = ( unsigned int ) address;
+        pPDC->PDC_TNCR = bytes;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_SetRx */
+/** \brief Set the receive transfer descriptor */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PDC_SetRx( AT91PS_PDC pPDC,     /* \arg pointer to a PDC controller */
+                                   char * address,      /* \arg address to the next bloc to be received */
+                                   unsigned int bytes ) /* \arg number of bytes to be received */
+    {
+        pPDC->PDC_RPR = ( unsigned int ) address;
+        pPDC->PDC_RCR = bytes;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_SetTx */
+/** \brief Set the transmit transfer descriptor */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PDC_SetTx( AT91PS_PDC pPDC,     /* \arg pointer to a PDC controller */
+                                   char * address,      /* \arg address to the next bloc to be transmitted */
+                                   unsigned int bytes ) /* \arg number of bytes to be transmitted */
+    {
+        pPDC->PDC_TPR = ( unsigned int ) address;
+        pPDC->PDC_TCR = bytes;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_EnableTx */
+/** \brief Enable transmit */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PDC_EnableTx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
+    {
+        pPDC->PDC_PTCR = AT91C_PDC_TXTEN;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_EnableRx */
+/** \brief Enable receive */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PDC_EnableRx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
+    {
+        pPDC->PDC_PTCR = AT91C_PDC_RXTEN;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_DisableTx */
+/** \brief Disable transmit */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PDC_DisableTx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
+    {
+        pPDC->PDC_PTCR = AT91C_PDC_TXTDIS;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_DisableRx */
+/** \brief Disable receive */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PDC_DisableRx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
+    {
+        pPDC->PDC_PTCR = AT91C_PDC_RXTDIS;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_IsTxEmpty */
+/** \brief Test if the current transfer descriptor has been sent */
+/**---------------------------------------------------------------------------- */
+    __inline int AT91F_PDC_IsTxEmpty( /* \return return 1 if transfer is complete */
+        AT91PS_PDC pPDC )             /* \arg pointer to a PDC controller */
+    {
+        return !( pPDC->PDC_TCR );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_IsNextTxEmpty */
+/** \brief Test if the next transfer descriptor has been moved to the current td */
+/**---------------------------------------------------------------------------- */
+    __inline int AT91F_PDC_IsNextTxEmpty( /* \return return 1 if transfer is complete */
+        AT91PS_PDC pPDC )                 /* \arg pointer to a PDC controller */
+    {
+        return !( pPDC->PDC_TNCR );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_IsRxEmpty */
+/** \brief Test if the current transfer descriptor has been filled */
+/**---------------------------------------------------------------------------- */
+    __inline int AT91F_PDC_IsRxEmpty( /* \return return 1 if transfer is complete */
+        AT91PS_PDC pPDC )             /* \arg pointer to a PDC controller */
+    {
+        return !( pPDC->PDC_RCR );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_IsNextRxEmpty */
+/** \brief Test if the next transfer descriptor has been moved to the current td */
+/**---------------------------------------------------------------------------- */
+    __inline int AT91F_PDC_IsNextRxEmpty( /* \return return 1 if transfer is complete */
+        AT91PS_PDC pPDC )                 /* \arg pointer to a PDC controller */
+    {
+        return !( pPDC->PDC_RNCR );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_Open */
+/** \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PDC_Open( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
+    {
+        /** Disable the RX and TX PDC transfer requests */
+        AT91F_PDC_DisableRx( pPDC );
+        AT91F_PDC_DisableTx( pPDC );
+
+        /** Reset all Counter register Next buffer first */
+        AT91F_PDC_SetNextTx( pPDC, ( char * ) 0, 0 );
+        AT91F_PDC_SetNextRx( pPDC, ( char * ) 0, 0 );
+        AT91F_PDC_SetTx( pPDC, ( char * ) 0, 0 );
+        AT91F_PDC_SetRx( pPDC, ( char * ) 0, 0 );
+
+        /** Enable the RX and TX PDC transfer requests */
+        AT91F_PDC_EnableRx( pPDC );
+        AT91F_PDC_EnableTx( pPDC );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_Close */
+/** \brief Close PDC: disable TX and RX reset transfer descriptors */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PDC_Close( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
+    {
+        /** Disable the RX and TX PDC transfer requests */
+        AT91F_PDC_DisableRx( pPDC );
+        AT91F_PDC_DisableTx( pPDC );
+
+        /** Reset all Counter register Next buffer first */
+        AT91F_PDC_SetNextTx( pPDC, ( char * ) 0, 0 );
+        AT91F_PDC_SetNextRx( pPDC, ( char * ) 0, 0 );
+        AT91F_PDC_SetTx( pPDC, ( char * ) 0, 0 );
+        AT91F_PDC_SetRx( pPDC, ( char * ) 0, 0 );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_SendFrame */
+/** \brief Close PDC: disable TX and RX reset transfer descriptors */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_PDC_SendFrame( AT91PS_PDC pPDC,
+                                               char * pBuffer,
+                                               unsigned int szBuffer,
+                                               char * pNextBuffer,
+                                               unsigned int szNextBuffer )
+    {
+        if( AT91F_PDC_IsTxEmpty( pPDC ) )
+        {
+            /** Buffer and next buffer can be initialized */
+            AT91F_PDC_SetTx( pPDC, pBuffer, szBuffer );
+            AT91F_PDC_SetNextTx( pPDC, pNextBuffer, szNextBuffer );
+            return 2;
+        }
+        else if( AT91F_PDC_IsNextTxEmpty( pPDC ) )
+        {
+            /** Only one buffer can be initialized */
+            AT91F_PDC_SetNextTx( pPDC, pBuffer, szBuffer );
+            return 1;
+        }
+        else
+        {
+            /** All buffer are in use... */
+            return 0;
+        }
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PDC_ReceiveFrame */
+/** \brief Close PDC: disable TX and RX reset transfer descriptors */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_PDC_ReceiveFrame( AT91PS_PDC pPDC,
+                                                  char * pBuffer,
+                                                  unsigned int szBuffer,
+                                                  char * pNextBuffer,
+                                                  unsigned int szNextBuffer )
+    {
+        if( AT91F_PDC_IsRxEmpty( pPDC ) )
+        {
+            /** Buffer and next buffer can be initialized */
+            AT91F_PDC_SetRx( pPDC, pBuffer, szBuffer );
+            AT91F_PDC_SetNextRx( pPDC, pNextBuffer, szNextBuffer );
+            return 2;
+        }
+        else if( AT91F_PDC_IsNextRxEmpty( pPDC ) )
+        {
+            /** Only one buffer can be initialized */
+            AT91F_PDC_SetNextRx( pPDC, pBuffer, szBuffer );
+            return 1;
+        }
+        else
+        {
+            /** All buffer are in use... */
+            return 0;
+        }
+    }
+
+/* *****************************************************************************
+*               SOFTWARE API FOR DBGU
+***************************************************************************** */
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_DBGU_InterruptEnable */
+/** \brief Enable DBGU Interrupt */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_DBGU_InterruptEnable( AT91PS_DBGU pDbgu,  /* \arg  pointer to a DBGU controller */
+                                              unsigned int flag ) /* \arg  dbgu interrupt to be enabled */
+    {
+        pDbgu->DBGU_IER = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_DBGU_InterruptDisable */
+/** \brief Disable DBGU Interrupt */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_DBGU_InterruptDisable( AT91PS_DBGU pDbgu,  /* \arg  pointer to a DBGU controller */
+                                               unsigned int flag ) /* \arg  dbgu interrupt to be disabled */
+    {
+        pDbgu->DBGU_IDR = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_DBGU_GetInterruptMaskStatus */
+/** \brief Return DBGU Interrupt Mask Status */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( /* \return DBGU Interrupt Mask Status */
+        AT91PS_DBGU pDbgu )                                  /* \arg  pointer to a DBGU controller */
+    {
+        return pDbgu->DBGU_IMR;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_DBGU_IsInterruptMasked */
+/** \brief Test if DBGU Interrupt is Masked */
+/**---------------------------------------------------------------------------- */
+    __inline int AT91F_DBGU_IsInterruptMasked( AT91PS_DBGU pDbgu,  /* \arg  pointer to a DBGU controller */
+                                               unsigned int flag ) /* \arg  flag to be tested */
+    {
+        return( AT91F_DBGU_GetInterruptMaskStatus( pDbgu ) & flag );
+    }
+
+/* *****************************************************************************
+*               SOFTWARE API FOR PIO
+***************************************************************************** */
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_CfgPeriph */
+/** \brief Enable pins to be derived by peripheral */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_CfgPeriph( AT91PS_PIO pPio,             /* \arg pointer to a PIO controller */
+                                       unsigned int periphAEnable,  /* \arg PERIPH A to enable */
+                                       unsigned int periphBEnable ) /* \arg PERIPH B to enable */
+
+    {
+        pPio->PIO_ASR = periphAEnable;
+        pPio->PIO_BSR = periphBEnable;
+        pPio->PIO_PDR = ( periphAEnable | periphBEnable ); /* Set in Periph mode */
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_CfgOutput */
+/** \brief Enable PIO in output mode */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_CfgOutput( AT91PS_PIO pPio,         /* \arg pointer to a PIO controller */
+                                       unsigned int pioEnable ) /* \arg PIO to be enabled */
+    {
+        pPio->PIO_PER = pioEnable;                              /* Set in PIO mode */
+        pPio->PIO_OER = pioEnable;                              /* Configure in Output */
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_CfgInput */
+/** \brief Enable PIO in input mode */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_CfgInput( AT91PS_PIO pPio,           /* \arg pointer to a PIO controller */
+                                      unsigned int inputEnable ) /* \arg PIO to be enabled */
+    {
+        /* Disable output */
+        pPio->PIO_ODR = inputEnable;
+        pPio->PIO_PER = inputEnable;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_CfgOpendrain */
+/** \brief Configure PIO in open drain */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_CfgOpendrain( AT91PS_PIO pPio,              /* \arg pointer to a PIO controller */
+                                          unsigned int multiDrvEnable ) /* \arg pio to be configured in open drain */
+    {
+        /* Configure the multi-drive option */
+        pPio->PIO_MDDR = ~multiDrvEnable;
+        pPio->PIO_MDER = multiDrvEnable;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_CfgPullup */
+/** \brief Enable pullup on PIO */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_CfgPullup( AT91PS_PIO pPio,            /* \arg pointer to a PIO controller */
+                                       unsigned int pullupEnable ) /* \arg enable pullup on PIO */
+    {
+        /* Connect or not Pullup */
+        pPio->PIO_PPUDR = ~pullupEnable;
+        pPio->PIO_PPUER = pullupEnable;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_CfgDirectDrive */
+/** \brief Enable direct drive on PIO */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_CfgDirectDrive( AT91PS_PIO pPio,           /* \arg pointer to a PIO controller */
+                                            unsigned int directDrive ) /* \arg PIO to be configured with direct drive */
+
+    {
+        /* Configure the Direct Drive */
+        pPio->PIO_OWDR = ~directDrive;
+        pPio->PIO_OWER = directDrive;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_CfgInputFilter */
+/** \brief Enable input filter on input PIO */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_CfgInputFilter( AT91PS_PIO pPio,           /* \arg pointer to a PIO controller */
+                                            unsigned int inputFilter ) /* \arg PIO to be configured with input filter */
+
+    {
+        /* Configure the Direct Drive */
+        pPio->PIO_IFDR = ~inputFilter;
+        pPio->PIO_IFER = inputFilter;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_GetInput */
+/** \brief Return PIO input value */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_PIO_GetInput( /* \return PIO input */
+        AT91PS_PIO pPio )                     /* \arg  pointer to a PIO controller */
+    {
+        return pPio->PIO_PDSR;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_IsInputSet */
+/** \brief Test if PIO is input flag is active */
+/**---------------------------------------------------------------------------- */
+    __inline int AT91F_PIO_IsInputSet( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                       unsigned int flag ) /* \arg  flag to be tested */
+    {
+        return( AT91F_PIO_GetInput( pPio ) & flag );
+    }
+
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_SetOutput */
+/** \brief Set to 1 output PIO */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_SetOutput( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                       unsigned int flag ) /* \arg  output to be set */
+    {
+        pPio->PIO_SODR = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_ClearOutput */
+/** \brief Set to 0 output PIO */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_ClearOutput( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                         unsigned int flag ) /* \arg  output to be cleared */
+    {
+        pPio->PIO_CODR = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_ForceOutput */
+/** \brief Force output when Direct drive option is enabled */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_ForceOutput( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                         unsigned int flag ) /* \arg  output to be forced */
+    {
+        pPio->PIO_ODSR = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_Enable */
+/** \brief Enable PIO */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_Enable( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                    unsigned int flag ) /* \arg  pio to be enabled */
+    {
+        pPio->PIO_PER = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_Disable */
+/** \brief Disable PIO */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_Disable( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                     unsigned int flag ) /* \arg  pio to be disabled */
+    {
+        pPio->PIO_PDR = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_GetStatus */
+/** \brief Return PIO Status */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_PIO_GetStatus( /* \return PIO Status */
+        AT91PS_PIO pPio )                      /* \arg  pointer to a PIO controller */
+    {
+        return pPio->PIO_PSR;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_IsSet */
+/** \brief Test if PIO is Set */
+/**---------------------------------------------------------------------------- */
+    __inline int AT91F_PIO_IsSet( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                  unsigned int flag ) /* \arg  flag to be tested */
+    {
+        return( AT91F_PIO_GetStatus( pPio ) & flag );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_OutputEnable */
+/** \brief Output Enable PIO */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_OutputEnable( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                          unsigned int flag ) /* \arg  pio output to be enabled */
+    {
+        pPio->PIO_OER = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_OutputDisable */
+/** \brief Output Enable PIO */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_OutputDisable( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                           unsigned int flag ) /* \arg  pio output to be disabled */
+    {
+        pPio->PIO_ODR = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_GetOutputStatus */
+/** \brief Return PIO Output Status */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_PIO_GetOutputStatus( /* \return PIO Output Status */
+        AT91PS_PIO pPio )                            /* \arg  pointer to a PIO controller */
+    {
+        return pPio->PIO_OSR;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_IsOuputSet */
+/** \brief Test if PIO Output is Set */
+/**---------------------------------------------------------------------------- */
+    __inline int AT91F_PIO_IsOutputSet( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                        unsigned int flag ) /* \arg  flag to be tested */
+    {
+        return( AT91F_PIO_GetOutputStatus( pPio ) & flag );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_InputFilterEnable */
+/** \brief Input Filter Enable PIO */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_InputFilterEnable( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                               unsigned int flag ) /* \arg  pio input filter to be enabled */
+    {
+        pPio->PIO_IFER = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_InputFilterDisable */
+/** \brief Input Filter Disable PIO */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_InputFilterDisable( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                                unsigned int flag ) /* \arg  pio input filter to be disabled */
+    {
+        pPio->PIO_IFDR = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_GetInputFilterStatus */
+/** \brief Return PIO Input Filter Status */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_PIO_GetInputFilterStatus( /* \return PIO Input Filter Status */
+        AT91PS_PIO pPio )                                 /* \arg  pointer to a PIO controller */
+    {
+        return pPio->PIO_IFSR;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_IsInputFilterSet */
+/** \brief Test if PIO Input filter is Set */
+/**---------------------------------------------------------------------------- */
+    __inline int AT91F_PIO_IsInputFilterSet( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                             unsigned int flag ) /* \arg  flag to be tested */
+    {
+        return( AT91F_PIO_GetInputFilterStatus( pPio ) & flag );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_GetOutputDataStatus */
+/** \brief Return PIO Output Data Status */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_PIO_GetOutputDataStatus( /* \return PIO Output Data Status */
+        AT91PS_PIO pPio )                                /* \arg  pointer to a PIO controller */
+    {
+        return pPio->PIO_ODSR;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_InterruptEnable */
+/** \brief Enable PIO Interrupt */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_InterruptEnable( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                             unsigned int flag ) /* \arg  pio interrupt to be enabled */
+    {
+        pPio->PIO_IER = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_InterruptDisable */
+/** \brief Disable PIO Interrupt */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_InterruptDisable( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                              unsigned int flag ) /* \arg  pio interrupt to be disabled */
+    {
+        pPio->PIO_IDR = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_GetInterruptMaskStatus */
+/** \brief Return PIO Interrupt Mask Status */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_PIO_GetInterruptMaskStatus( /* \return PIO Interrupt Mask Status */
+        AT91PS_PIO pPio )                                   /* \arg  pointer to a PIO controller */
+    {
+        return pPio->PIO_IMR;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_GetInterruptStatus */
+/** \brief Return PIO Interrupt Status */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_PIO_GetInterruptStatus( /* \return PIO Interrupt Status */
+        AT91PS_PIO pPio )                               /* \arg  pointer to a PIO controller */
+    {
+        return pPio->PIO_ISR;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_IsInterruptMasked */
+/** \brief Test if PIO Interrupt is Masked */
+/**---------------------------------------------------------------------------- */
+    __inline int AT91F_PIO_IsInterruptMasked( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                              unsigned int flag ) /* \arg  flag to be tested */
+    {
+        return( AT91F_PIO_GetInterruptMaskStatus( pPio ) & flag );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_IsInterruptSet */
+/** \brief Test if PIO Interrupt is Set */
+/**---------------------------------------------------------------------------- */
+    __inline int AT91F_PIO_IsInterruptSet( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                           unsigned int flag ) /* \arg  flag to be tested */
+    {
+        return( AT91F_PIO_GetInterruptStatus( pPio ) & flag );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_MultiDriverEnable */
+/** \brief Multi Driver Enable PIO */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_MultiDriverEnable( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                               unsigned int flag ) /* \arg  pio to be enabled */
+    {
+        pPio->PIO_MDER = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_MultiDriverDisable */
+/** \brief Multi Driver Disable PIO */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_MultiDriverDisable( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                                unsigned int flag ) /* \arg  pio to be disabled */
+    {
+        pPio->PIO_MDDR = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_GetMultiDriverStatus */
+/** \brief Return PIO Multi Driver Status */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_PIO_GetMultiDriverStatus( /* \return PIO Multi Driver Status */
+        AT91PS_PIO pPio )                                 /* \arg  pointer to a PIO controller */
+    {
+        return pPio->PIO_MDSR;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_IsMultiDriverSet */
+/** \brief Test if PIO MultiDriver is Set */
+/**---------------------------------------------------------------------------- */
+    __inline int AT91F_PIO_IsMultiDriverSet( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                             unsigned int flag ) /* \arg  flag to be tested */
+    {
+        return( AT91F_PIO_GetMultiDriverStatus( pPio ) & flag );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_A_RegisterSelection */
+/** \brief PIO A Register Selection */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_A_RegisterSelection( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                                 unsigned int flag ) /* \arg  pio A register selection */
+    {
+        pPio->PIO_ASR = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_B_RegisterSelection */
+/** \brief PIO B Register Selection */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_B_RegisterSelection( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                                 unsigned int flag ) /* \arg  pio B register selection */
+    {
+        pPio->PIO_BSR = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_Get_AB_RegisterStatus */
+/** \brief Return PIO Interrupt Status */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( /* \return PIO AB Register Status */
+        AT91PS_PIO pPio )                                  /* \arg  pointer to a PIO controller */
+    {
+        return pPio->PIO_ABSR;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_IsAB_RegisterSet */
+/** \brief Test if PIO AB Register is Set */
+/**---------------------------------------------------------------------------- */
+    __inline int AT91F_PIO_IsAB_RegisterSet( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                             unsigned int flag ) /* \arg  flag to be tested */
+    {
+        return( AT91F_PIO_Get_AB_RegisterStatus( pPio ) & flag );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_OutputWriteEnable */
+/** \brief Output Write Enable PIO */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_OutputWriteEnable( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                               unsigned int flag ) /* \arg  pio output write to be enabled */
+    {
+        pPio->PIO_OWER = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_OutputWriteDisable */
+/** \brief Output Write Disable PIO */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PIO_OutputWriteDisable( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                                unsigned int flag ) /* \arg  pio output write to be disabled */
+    {
+        pPio->PIO_OWDR = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_GetOutputWriteStatus */
+/** \brief Return PIO Output Write Status */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_PIO_GetOutputWriteStatus( /* \return PIO Output Write Status */
+        AT91PS_PIO pPio )                                 /* \arg  pointer to a PIO controller */
+    {
+        return pPio->PIO_OWSR;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_IsOutputWriteSet */
+/** \brief Test if PIO OutputWrite is Set */
+/**---------------------------------------------------------------------------- */
+    __inline int AT91F_PIO_IsOutputWriteSet( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                             unsigned int flag ) /* \arg  flag to be tested */
+    {
+        return( AT91F_PIO_GetOutputWriteStatus( pPio ) & flag );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_GetCfgPullup */
+/** \brief Return PIO Configuration Pullup */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_PIO_GetCfgPullup( /* \return PIO Configuration Pullup */
+        AT91PS_PIO pPio )                         /* \arg  pointer to a PIO controller */
+    {
+        return pPio->PIO_PPUSR;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_IsOutputDataStatusSet */
+/** \brief Test if PIO Output Data Status is Set */
+/**---------------------------------------------------------------------------- */
+    __inline int AT91F_PIO_IsOutputDataStatusSet( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                                  unsigned int flag ) /* \arg  flag to be tested */
+    {
+        return( AT91F_PIO_GetOutputDataStatus( pPio ) & flag );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PIO_IsCfgPullupStatusSet */
+/** \brief Test if PIO Configuration Pullup Status is Set */
+/**---------------------------------------------------------------------------- */
+    __inline int AT91F_PIO_IsCfgPullupStatusSet( AT91PS_PIO pPio,    /* \arg  pointer to a PIO controller */
+                                                 unsigned int flag ) /* \arg  flag to be tested */
+    {
+        return( ~AT91F_PIO_GetCfgPullup( pPio ) & flag );
+    }
+
+/* *****************************************************************************
+*               SOFTWARE API FOR PMC
+***************************************************************************** */
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_CfgSysClkEnableReg */
+/** \brief Configure the System Clock Enable Register of the PMC controller */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PMC_CfgSysClkEnableReg( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */
+                                                unsigned int mode )
+    {
+        /** Write to the SCER register */
+        pPMC->PMC_SCER = mode;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_CfgSysClkDisableReg */
+/** \brief Configure the System Clock Disable Register of the PMC controller */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PMC_CfgSysClkDisableReg( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */
+                                                 unsigned int mode )
+    {
+        /** Write to the SCDR register */
+        pPMC->PMC_SCDR = mode;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_GetSysClkStatusReg */
+/** \brief Return the System Clock Status Register of the PMC controller */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_PMC_GetSysClkStatusReg( AT91PS_PMC pPMC /* pointer to a CAN controller */
+                                                        )
+    {
+        return pPMC->PMC_SCSR;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_EnablePeriphClock */
+/** \brief Enable peripheral clock */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PMC_EnablePeriphClock( AT91PS_PMC pPMC,         /* \arg pointer to PMC controller */
+                                               unsigned int periphIds ) /* \arg IDs of peripherals to enable */
+    {
+        pPMC->PMC_PCER = periphIds;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_DisablePeriphClock */
+/** \brief Disable peripheral clock */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PMC_DisablePeriphClock( AT91PS_PMC pPMC,         /* \arg pointer to PMC controller */
+                                                unsigned int periphIds ) /* \arg IDs of peripherals to enable */
+    {
+        pPMC->PMC_PCDR = periphIds;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_GetPeriphClock */
+/** \brief Get peripheral clock status */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_PMC_GetPeriphClock( AT91PS_PMC pPMC ) /* \arg pointer to PMC controller */
+    {
+        return pPMC->PMC_PCSR;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_CKGR_CfgMainOscillatorReg */
+/** \brief Cfg the main oscillator */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_CKGR_CfgMainOscillatorReg( AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */
+                                                   unsigned int mode )
+    {
+        pCKGR->CKGR_MOR = mode;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_CKGR_GetMainOscillatorReg */
+/** \brief Cfg the main oscillator */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_CKGR_GetMainOscillatorReg( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */
+    {
+        return pCKGR->CKGR_MOR;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_CKGR_EnableMainOscillator */
+/** \brief Enable the main oscillator */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_CKGR_EnableMainOscillator( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */
+    {
+        pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_CKGR_DisableMainOscillator */
+/** \brief Disable the main oscillator */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_CKGR_DisableMainOscillator( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */
+    {
+        pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_CKGR_CfgMainOscStartUpTime */
+/** \brief Cfg MOR Register according to the main osc startup time */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_CKGR_CfgMainOscStartUpTime( AT91PS_CKGR pCKGR,         /* \arg pointer to CKGR controller */
+                                                    unsigned int startup_time, /* \arg main osc startup time in microsecond (us) */
+                                                    unsigned int slowClock )   /* \arg slowClock in Hz */
+    {
+        pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT;
+        pCKGR->CKGR_MOR |= ( ( slowClock * startup_time ) / ( 8 * 1000000 ) ) << 8;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_CKGR_GetMainClockFreqReg */
+/** \brief Cfg the main oscillator */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_CKGR_GetMainClockFreqReg( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */
+    {
+        return pCKGR->CKGR_MCFR;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_CKGR_GetMainClock */
+/** \brief Return Main clock in Hz */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_CKGR_GetMainClock( AT91PS_CKGR pCKGR,       /* \arg pointer to CKGR controller */
+                                                   unsigned int slowClock ) /* \arg slowClock in Hz */
+    {
+        return ( ( pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF ) * slowClock ) >> 4;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_CfgMCKReg */
+/** \brief Cfg Master Clock Register */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PMC_CfgMCKReg( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */
+                                       unsigned int mode )
+    {
+        pPMC->PMC_MCKR = mode;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_GetMCKReg */
+/** \brief Return Master Clock Register */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_PMC_GetMCKReg( AT91PS_PMC pPMC ) /* \arg pointer to PMC controller */
+    {
+        return pPMC->PMC_MCKR;
+    }
+
+/**------------------------------------------------------------------------------ */
+/** \fn    AT91F_PMC_GetMasterClock */
+/** \brief Return master clock in Hz which corresponds to processor clock for ARM7 */
+/**------------------------------------------------------------------------------ */
+    __inline unsigned int AT91F_PMC_GetMasterClock( AT91PS_PMC pPMC,         /* \arg pointer to PMC controller */
+                                                    AT91PS_CKGR pCKGR,       /* \arg pointer to CKGR controller */
+                                                    unsigned int slowClock ) /* \arg slowClock in Hz */
+    {
+        unsigned int reg = pPMC->PMC_MCKR;
+        unsigned int prescaler = ( 1 << ( ( reg & AT91C_PMC_PRES ) >> 2 ) );
+        unsigned int pllDivider, pllMultiplier;
+
+        switch( reg & AT91C_PMC_CSS )
+        {
+            case AT91C_PMC_CSS_SLOW_CLK: /* Slow clock selected */
+                return slowClock / prescaler;
+
+            case AT91C_PMC_CSS_MAIN_CLK: /* Main clock is selected */
+                return AT91F_CKGR_GetMainClock( pCKGR, slowClock ) / prescaler;
+
+            case AT91C_PMC_CSS_PLL_CLK: /* PLLB clock is selected */
+                reg = pCKGR->CKGR_PLLR;
+                pllDivider = ( reg & AT91C_CKGR_DIV );
+                pllMultiplier = ( ( reg & AT91C_CKGR_MUL ) >> 16 ) + 1;
+                return AT91F_CKGR_GetMainClock( pCKGR, slowClock ) / pllDivider * pllMultiplier / prescaler;
+        }
+
+        return 0;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_EnablePCK */
+/** \brief Enable peripheral clock */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PMC_EnablePCK( AT91PS_PMC pPMC,  /* \arg pointer to PMC controller */
+                                       unsigned int pck, /* \arg Peripheral clock identifier 0 .. 7 */
+                                       unsigned int mode )
+    {
+        pPMC->PMC_PCKR[ pck ] = mode;
+        pPMC->PMC_SCER = ( 1 << pck ) << 8;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_DisablePCK */
+/** \brief Enable peripheral clock */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PMC_DisablePCK( AT91PS_PMC pPMC,   /* \arg pointer to PMC controller */
+                                        unsigned int pck ) /* \arg Peripheral clock identifier 0 .. 7 */
+    {
+        pPMC->PMC_SCDR = ( 1 << pck ) << 8;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_EnableIt */
+/** \brief Enable PMC interrupt */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PMC_EnableIt( AT91PS_PMC pPMC,    /* pointer to a PMC controller */
+                                      unsigned int flag ) /* IT to be enabled */
+    {
+        /** Write to the IER register */
+        pPMC->PMC_IER = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_DisableIt */
+/** \brief Disable PMC interrupt */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_PMC_DisableIt( AT91PS_PMC pPMC,    /* pointer to a PMC controller */
+                                       unsigned int flag ) /* IT to be disabled */
+    {
+        /** Write to the IDR register */
+        pPMC->PMC_IDR = flag;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_GetStatus */
+/** \brief Return PMC Interrupt Status */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_PMC_GetStatus( /* \return PMC Interrupt Status */
+        AT91PS_PMC pPMC )                      /* pointer to a PMC controller */
+    {
+        return pPMC->PMC_SR;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_GetInterruptMaskStatus */
+/** \brief Return PMC Interrupt Mask Status */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_PMC_GetInterruptMaskStatus( /* \return PMC Interrupt Mask Status */
+        AT91PS_PMC pPMC )                                   /* pointer to a PMC controller */
+    {
+        return pPMC->PMC_IMR;
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_IsInterruptMasked */
+/** \brief Test if PMC Interrupt is Masked */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_PMC_IsInterruptMasked( AT91PS_PMC pPMC,    /* \arg  pointer to a PMC controller */
+                                                       unsigned int flag ) /* \arg  flag to be tested */
+    {
+        return( AT91F_PMC_GetInterruptMaskStatus( pPMC ) & flag );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PMC_IsStatusSet */
+/** \brief Test if PMC Status is Set */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_PMC_IsStatusSet( AT91PS_PMC pPMC,    /* \arg  pointer to a PMC controller */
+                                                 unsigned int flag ) /* \arg  flag to be tested */
+    {
+        return( AT91F_PMC_GetStatus( pPMC ) & flag );
+    } /* *****************************************************************************
+      *              SOFTWARE API FOR RSTC
+      ***************************************************************************** */
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_RSTSoftReset */
+/** \brief Start Software Reset */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_RSTSoftReset( AT91PS_RSTC pRSTC,
+                                      unsigned int reset )
+    {
+        pRSTC->RSTC_RCR = ( 0xA5000000 | reset );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_RSTSetMode */
+/** \brief Set Reset Mode */
+/**---------------------------------------------------------------------------- */
+    __inline void AT91F_RSTSetMode( AT91PS_RSTC pRSTC,
+                                    unsigned int mode )
+    {
+        pRSTC->RSTC_RMR = ( 0xA5000000 | mode );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_RSTGetMode */
+/** \brief Get Reset Mode */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_RSTGetMode( AT91PS_RSTC pRSTC )
+    {
+        return( pRSTC->RSTC_RMR );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_RSTGetStatus */
+/** \brief Get Reset Status */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_RSTGetStatus( AT91PS_RSTC pRSTC )
+    {
+        return( pRSTC->RSTC_RSR );
+    }
+
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_RSTIsSoftRstActive */
+/** \brief Return !=0 if software reset is still not completed */
+/**---------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_RSTIsSoftRstActive( AT91PS_RSTC pRSTC )
+    {
+        return( ( pRSTC->RSTC_RSR ) & AT91C_RSTC_SRCMP );
+    }
+
+/* *****************************************************************************
+*               SOFTWARE API FOR RTTC
+***************************************************************************** */
+/**-------------------------------------------------------------------------------------- */
+/** \fn     AT91F_SetRTT_TimeBase() */
+/** \brief  Set the RTT prescaler according to the TimeBase in ms */
+/**-------------------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_RTTSetTimeBase( AT91PS_RTTC pRTTC,
+                                                unsigned int ms )
+    {
+        if( ms > 2000 )
+        {
+            return 1; /* AT91C_TIME_OUT_OF_RANGE */
+        }
+
+        pRTTC->RTTC_RTMR &= ~0xFFFF;
+        pRTTC->RTTC_RTMR |= ( ( ( ms << 15 ) / 1000 ) & 0xFFFF );
+        return 0;
+    }
+
+/**-------------------------------------------------------------------------------------- */
+/** \fn     AT91F_RTTSetPrescaler() */
+/** \brief  Set the new prescaler value */
+/**-------------------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_RTTSetPrescaler( AT91PS_RTTC pRTTC,
+                                                 unsigned int rtpres )
+    {
+        pRTTC->RTTC_RTMR &= ~0xFFFF;
+        pRTTC->RTTC_RTMR |= ( rtpres & 0xFFFF );
+        return( pRTTC->RTTC_RTMR );
+    }
+
+/**-------------------------------------------------------------------------------------- */
+/** \fn     AT91F_RTTRestart() */
+/** \brief  Restart the RTT prescaler */
+/**-------------------------------------------------------------------------------------- */
+    __inline void AT91F_RTTRestart( AT91PS_RTTC pRTTC )
+    {
+        pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTRST;
+    }
+
+
+/**-------------------------------------------------------------------------------------- */
+/** \fn     AT91F_RTT_SetAlarmINT() */
+/** \brief  Enable RTT Alarm Interrupt */
+/**-------------------------------------------------------------------------------------- */
+    __inline void AT91F_RTTSetAlarmINT( AT91PS_RTTC pRTTC )
+    {
+        pRTTC->RTTC_RTMR |= AT91C_RTTC_ALMIEN;
+    }
+
+/**-------------------------------------------------------------------------------------- */
+/** \fn     AT91F_RTT_ClearAlarmINT() */
+/** \brief  Disable RTT Alarm Interrupt */
+/**-------------------------------------------------------------------------------------- */
+    __inline void AT91F_RTTClearAlarmINT( AT91PS_RTTC pRTTC )
+    {
+        pRTTC->RTTC_RTMR &= ~AT91C_RTTC_ALMIEN;
+    }
+
+/**-------------------------------------------------------------------------------------- */
+/** \fn     AT91F_RTT_SetRttIncINT() */
+/** \brief  Enable RTT INC Interrupt */
+/**-------------------------------------------------------------------------------------- */
+    __inline void AT91F_RTTSetRttIncINT( AT91PS_RTTC pRTTC )
+    {
+        pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTINCIEN;
+    }
+
+/**-------------------------------------------------------------------------------------- */
+/** \fn     AT91F_RTT_ClearRttIncINT() */
+/** \brief  Disable RTT INC Interrupt */
+/**-------------------------------------------------------------------------------------- */
+    __inline void AT91F_RTTClearRttIncINT( AT91PS_RTTC pRTTC )
+    {
+        pRTTC->RTTC_RTMR &= ~AT91C_RTTC_RTTINCIEN;
+    }
+
+/**-------------------------------------------------------------------------------------- */
+/** \fn     AT91F_RTT_SetAlarmValue() */
+/** \brief  Set RTT Alarm Value */
+/**-------------------------------------------------------------------------------------- */
+    __inline void AT91F_RTTSetAlarmValue( AT91PS_RTTC pRTTC,
+                                          unsigned int alarm )
+    {
+        pRTTC->RTTC_RTAR = alarm;
+    }
+
+/**-------------------------------------------------------------------------------------- */
+/** \fn     AT91F_RTT_GetAlarmValue() */
+/** \brief  Get RTT Alarm Value */
+/**-------------------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_RTTGetAlarmValue( AT91PS_RTTC pRTTC )
+    {
+        return( pRTTC->RTTC_RTAR );
+    }
+
+/**-------------------------------------------------------------------------------------- */
+/** \fn     AT91F_RTTGetStatus() */
+/** \brief  Read the RTT status */
+/**-------------------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_RTTGetStatus( AT91PS_RTTC pRTTC )
+    {
+        return( pRTTC->RTTC_RTSR );
+    }
+
+/**-------------------------------------------------------------------------------------- */
+/** \fn     AT91F_RTT_ReadValue() */
+/** \brief  Read the RTT value */
+/**-------------------------------------------------------------------------------------- */
+    __inline unsigned int AT91F_RTTReadValue( AT91PS_RTTC pRTTC )
+    {
+        register volatile unsigned int val1, val2;
+
+        do
+        {
+            val1 = pRTTC->RTTC_RTVR;
+            val2 = pRTTC->RTTC_RTVR;
+        }
+        while( val1 != val2 );
+
+        return( val1 );
+    }
+
+/* *****************************************************************************
+*               SOFTWARE API FOR PITC
+***************************************************************************** */
+/**---------------------------------------------------------------------------- */
+/** \fn    AT91F_PITInit */
+/** \brief System timer init : period in */
diff --git a/portable/IAR/AtmelSAM7S64/port.c b/portable/IAR/AtmelSAM7S64/port.c
index 324897023..ba72aa804 100644
--- a/portable/IAR/AtmelSAM7S64/port.c
+++ b/portable/IAR/AtmelSAM7S64/port.c
@@ -27,8 +27,8 @@
  */
 
 /*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the Atmel ARM7 port.
- *----------------------------------------------------------*/
+* Implementation of functions defined in portable.h for the Atmel ARM7 port.
+*----------------------------------------------------------*/
 
 
 /* Standard includes. */
@@ -39,29 +39,29 @@
 #include "task.h"
 
 /* Constants required to setup the initial stack. */
-#define portINITIAL_SPSR                ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
-#define portTHUMB_MODE_BIT              ( ( StackType_t ) 0x20 )
-#define portINSTRUCTION_SIZE            ( ( StackType_t ) 4 )
+#define portINITIAL_SPSR           ( ( StackType_t ) 0x1f )      /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT         ( ( StackType_t ) 0x20 )
+#define portINSTRUCTION_SIZE       ( ( StackType_t ) 4 )
 
 /* Constants required to setup the PIT. */
-#define portPIT_CLOCK_DIVISOR           ( ( uint32_t ) 16 )
-#define portPIT_COUNTER_VALUE           ( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) * portTICK_PERIOD_MS )
+#define portPIT_CLOCK_DIVISOR      ( ( uint32_t ) 16 )
+#define portPIT_COUNTER_VALUE      ( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) * portTICK_PERIOD_MS )
 
 /* Constants required to handle critical sections. */
-#define portNO_CRITICAL_NESTING         ( ( uint32_t ) 0 )
+#define portNO_CRITICAL_NESTING    ( ( uint32_t ) 0 )
 
 
-#define portINT_LEVEL_SENSITIVE  0
-#define portPIT_ENABLE          ( ( uint16_t ) 0x1 << 24 )
-#define portPIT_INT_ENABLE      ( ( uint16_t ) 0x1 << 25 )
+#define portINT_LEVEL_SENSITIVE    0
+#define portPIT_ENABLE             ( ( uint16_t ) 0x1 << 24 )
+#define portPIT_INT_ENABLE         ( ( uint16_t ) 0x1 << 25 )
 /*-----------------------------------------------------------*/
 
 /* Setup the PIT to generate the tick interrupts. */
 static void prvSetupTimerInterrupt( void );
 
 /* ulCriticalNesting will get set to zero when the first task starts.  It
-cannot be initialised to 0 as this will cause interrupts to be enabled
-during the kernel initialisation process. */
+ * cannot be initialised to 0 as this will cause interrupts to be enabled
+ * during the kernel initialisation process. */
 uint32_t ulCriticalNesting = ( uint32_t ) 9999;
 
 /*-----------------------------------------------------------*/
@@ -72,56 +72,58 @@ uint32_t ulCriticalNesting = ( uint32_t ) 9999;
  *
  * See header file for description.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
-StackType_t *pxOriginalTOS;
+    StackType_t * pxOriginalTOS;
 
     pxOriginalTOS = pxTopOfStack;
 
     /* To ensure asserts in tasks.c don't fail, although in this case the assert
-    is not really required. */
+     * is not really required. */
     pxTopOfStack--;
 
     /* Setup the initial stack of the task.  The stack is set exactly as
-    expected by the portRESTORE_CONTEXT() macro. */
+     * expected by the portRESTORE_CONTEXT() macro. */
 
     /* First on the stack is the return address - which in this case is the
-    start of the task.  The offset is added to make the return address appear
-    as it would within an IRQ ISR. */
+     * start of the task.  The offset is added to make the return address appear
+     * as it would within an IRQ ISR. */
     *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
     pxTopOfStack--;
 
-    *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */
+    *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa;    /* R14 */
     pxTopOfStack--;
     *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
+    *pxTopOfStack = ( StackType_t ) 0x12121212;    /* R12 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
+    *pxTopOfStack = ( StackType_t ) 0x11111111;    /* R11 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
+    *pxTopOfStack = ( StackType_t ) 0x10101010;    /* R10 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
+    *pxTopOfStack = ( StackType_t ) 0x09090909;    /* R9 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
+    *pxTopOfStack = ( StackType_t ) 0x08080808;    /* R8 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
+    *pxTopOfStack = ( StackType_t ) 0x07070707;    /* R7 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
+    *pxTopOfStack = ( StackType_t ) 0x06060606;    /* R6 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
+    *pxTopOfStack = ( StackType_t ) 0x05050505;    /* R5 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
+    *pxTopOfStack = ( StackType_t ) 0x04040404;    /* R4 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
+    *pxTopOfStack = ( StackType_t ) 0x03030303;    /* R3 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
+    *pxTopOfStack = ( StackType_t ) 0x02020202;    /* R2 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
+    *pxTopOfStack = ( StackType_t ) 0x01010101;    /* R1 */
     pxTopOfStack--;
 
     /* When the task starts is will expect to find the function parameter in
-    R0. */
+     * R0. */
     *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
     pxTopOfStack--;
 
@@ -137,8 +139,8 @@ StackType_t *pxOriginalTOS;
     pxTopOfStack--;
 
     /* Interrupt flags cannot always be stored on the stack and will
-    instead be stored in a variable, which is then saved as part of the
-    tasks context. */
+     * instead be stored in a variable, which is then saved as part of the
+     * tasks context. */
     *pxTopOfStack = portNO_CRITICAL_NESTING;
 
     return pxTopOfStack;
@@ -147,10 +149,10 @@ StackType_t *pxOriginalTOS;
 
 BaseType_t xPortStartScheduler( void )
 {
-extern void vPortStartFirstTask( void );
+    extern void vPortStartFirstTask( void );
 
     /* Start the timer that generates the tick ISR.  Interrupts are disabled
-    here already. */
+     * here already. */
     prvSetupTimerInterrupt();
 
     /* Start the first task. */
@@ -164,22 +166,22 @@ extern void vPortStartFirstTask( void );
 void vPortEndScheduler( void )
 {
     /* It is unlikely that the ARM port will require this function as there
-    is nothing to return to.  */
+     * is nothing to return to.  */
 }
 /*-----------------------------------------------------------*/
 
 #if configUSE_PREEMPTION == 0
 
-    /* The cooperative scheduler requires a normal IRQ service routine to
-    simply increment the system tick. */
+/* The cooperative scheduler requires a normal IRQ service routine to
+ * simply increment the system tick. */
     static __arm __irq void vPortNonPreemptiveTick( void );
     static __arm __irq void vPortNonPreemptiveTick( void )
     {
         uint32_t ulDummy;
 
         /* Increment the tick count - which may wake some tasks but as the
-        preemptive scheduler is not being used any woken task is not given
-        processor time no matter what its priority. */
+         * preemptive scheduler is not being used any woken task is not given
+         * processor time no matter what its priority. */
         xTaskIncrementTick();
 
         /* Clear the PIT interrupt. */
@@ -189,37 +191,33 @@ void vPortEndScheduler( void )
         AT91C_BASE_AIC->AIC_EOICR = ulDummy;
     }
 
-#else
+#else /* if configUSE_PREEMPTION == 0 */
 
-    /* Currently the IAR port requires the preemptive tick function to be
-    defined in an asm file. */
+/* Currently the IAR port requires the preemptive tick function to be
+ * defined in an asm file. */
 
-#endif
+#endif /* if configUSE_PREEMPTION == 0 */
 
 /*-----------------------------------------------------------*/
 
 static void prvSetupTimerInterrupt( void )
 {
-AT91PS_PITC pxPIT = AT91C_BASE_PITC;
+    AT91PS_PITC pxPIT = AT91C_BASE_PITC;
 
     /* Setup the AIC for PIT interrupts.  The interrupt routine chosen depends
-    on whether the preemptive or cooperative scheduler is being used. */
+     * on whether the preemptive or cooperative scheduler is being used. */
     #if configUSE_PREEMPTION == 0
-
-        AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vPortNonPreemptiveTick );
-
+        AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void ( * )( void ) )vPortNonPreemptiveTick );
     #else
-
-        extern void ( vPortPreemptiveTick )( void );
-        AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vPortPreemptiveTick );
-
+        extern void( vPortPreemptiveTick )( void );
+        AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void ( * )( void ) )vPortPreemptiveTick );
     #endif
 
     /* Configure the PIT period. */
     pxPIT->PITC_PIMR = portPIT_ENABLE | portPIT_INT_ENABLE | portPIT_COUNTER_VALUE;
 
     /* Enable the interrupt.  Global interrupts are disabled at this point so
-    this is safe. */
+     * this is safe. */
     AT91F_AIC_EnableIt( AT91C_BASE_AIC, AT91C_ID_SYS );
 }
 /*-----------------------------------------------------------*/
@@ -229,9 +227,9 @@ void vPortEnterCritical( void )
     /* Disable interrupts first! */
     __disable_interrupt();
 
-    /* Now interrupts are disabled ulCriticalNesting can be accessed
-    directly.  Increment ulCriticalNesting to keep a count of how many times
-    portENTER_CRITICAL() has been called. */
+    /* Now that interrupts are disabled, ulCriticalNesting can be accessed
+     * directly.  Increment ulCriticalNesting to keep a count of how many times
+     * portENTER_CRITICAL() has been called. */
     ulCriticalNesting++;
 }
 /*-----------------------------------------------------------*/
@@ -244,7 +242,7 @@ void vPortExitCritical( void )
         ulCriticalNesting--;
 
         /* If the nesting level has reached zero then interrupts should be
-        re-enabled. */
+         * re-enabled. */
         if( ulCriticalNesting == portNO_CRITICAL_NESTING )
         {
             __enable_interrupt();
diff --git a/portable/IAR/AtmelSAM7S64/portmacro.h b/portable/IAR/AtmelSAM7S64/portmacro.h
index 9bcf8a670..dbea59237 100644
--- a/portable/IAR/AtmelSAM7S64/portmacro.h
+++ b/portable/IAR/AtmelSAM7S64/portmacro.h
@@ -47,35 +47,35 @@
  */
 
 /* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint32_t
-#define portBASE_TYPE   long
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY ( TickType_t )    ( 0xFFFFFFFFUL )
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) ( 0xFFFFFFFFUL )
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portSTACK_GROWTH            ( -1 )
-#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT          8
-#define portYIELD()                 asm ( "SWI 0" )
-#define portNOP()                   asm ( "NOP" )
+#define portSTACK_GROWTH      ( -1 )
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT    8
+#define portYIELD()    asm ( "SWI 0" )
+#define portNOP()      asm ( "NOP" )
 /*-----------------------------------------------------------*/
 
 /* Critical section handling. */
@@ -91,21 +91,21 @@ __arm __interwork void vPortExitCritical( void );
 /*-----------------------------------------------------------*/
 
 /* Task utilities. */
-#define portEND_SWITCHING_ISR( xSwitchRequired )    \
-{                                                   \
-extern void vTaskSwitchContext( void );             \
-                                                    \
-    if( xSwitchRequired )                           \
-    {                                               \
-        vTaskSwitchContext();                       \
-    }                                               \
-}
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+    {                                            \
+        extern void vTaskSwitchContext( void );  \
+                                                 \
+        if( xSwitchRequired )                    \
+        {                                        \
+            vTaskSwitchContext();                \
+        }                                        \
+    }
 /*-----------------------------------------------------------*/
 
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/IAR/AtmelSAM9XE/ISR_Support.h b/portable/IAR/AtmelSAM9XE/ISR_Support.h
index 44414ecf8..e22768d7d 100644
--- a/portable/IAR/AtmelSAM9XE/ISR_Support.h
+++ b/portable/IAR/AtmelSAM9XE/ISR_Support.h
@@ -1,104 +1,150 @@
-;/*
-; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
-; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
-; *
-; * SPDX-License-Identifier: MIT
-; *
-; * Permission is hereby granted, free of charge, to any person obtaining a copy of
-; * this software and associated documentation files (the "Software"), to deal in
-; * the Software without restriction, including without limitation the rights to
-; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
-; * the Software, and to permit persons to whom the Software is furnished to do so,
-; * subject to the following conditions:
-; *
-; * The above copyright notice and this permission notice shall be included in all
-; * copies or substantial portions of the Software.
-; *
-; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-; *
-; * https://www.FreeRTOS.org
-; * https://github.com/FreeRTOS
-; *
-; */
-    EXTERN pxCurrentTCB
-    EXTERN ulCriticalNesting
+; /*
+   * ; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+   * ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+   * ; *
+   * ; * SPDX-License-Identifier: MIT
+   * ; *
+   * ; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+   * ; * this software and associated documentation files (the "Software"), to deal in
+   * ; * the Software without restriction, including without limitation the rights to
+   * ; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+   * ; * the Software, and to permit persons to whom the Software is furnished to do so,
+   * ; * subject to the following conditions:
+   * ; *
+   * ; * The above copyright notice and this permission notice shall be included in all
+   * ; * copies or substantial portions of the Software.
+   * ; *
+   * ; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+   * ; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+   * ; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+   * ; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+   * ; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+   * ; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+   * ; *
+   * ; * https://www.FreeRTOS.org
+   * ; * https://github.com/FreeRTOS
+   * ; *
+   * ; */
+EXTERN pxCurrentTCB
+EXTERN ulCriticalNesting
 
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Context save and restore macro definitions
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;
+Context save and restore macro definitions
+;
 
 portSAVE_CONTEXT MACRO
 
-    ; Push R0 as we are going to use the register.
-    STMDB   SP!, {R0}
+;
+Push R0 as we are going to use the register.
+   STMDB SP !, {
+    R0
+}
 
-    ; Set R0 to point to the task stack pointer.
-    STMDB   SP, {SP}^
-    NOP
-    SUB     SP, SP, #4
-    LDMIA   SP!, {R0}
+Set R0 to point to the task stack pointer.
+   STMDB SP, {
+    SP
+}
+^
+NOP
+SUB SP, SP, # 4
+LDMIA SP !, {
+    R0
+}
 
-    ; Push the return address onto the stack.
-    STMDB   R0!, {LR}
+;
+Push the return address onto the stack.
+          STMDB R0 !, {
+           LR
+       }
 
-    ; Now we have saved LR we can use it instead of R0.
-    MOV     LR, R0
+       Now we have saved LR we can use it instead of R0.
+          MOV LR, R0
 
-    ; Pop R0 so we can save it onto the system mode stack.
-    LDMIA   SP!, {R0}
+;
 
-    ; Push all the system mode registers onto the task stack.
-    STMDB   LR, {R0-LR}^
-    NOP
-    SUB     LR, LR, #60
+Pop R0 so we can save it onto the system mode stack.
+   LDMIA SP !, {
+    R0
+}
 
-    ; Push the SPSR onto the task stack.
-    MRS     R0, SPSR
-    STMDB   LR!, {R0}
+Push all the system mode registers onto the task stack.
+   STMDB LR, {
+    R0 - LR
+}
+^
+NOP
+SUB LR, LR, # 60
 
-    LDR     R0, =ulCriticalNesting
-    LDR     R0, [R0]
-    STMDB   LR!, {R0}
+;
+Push the SPSR onto the task stack.
+   MRS R0, SPSR
+STMDB LR !, {
+    R0
+}
 
-    ; Store the new top of stack for the task.
-    LDR     R1, =pxCurrentTCB
-    LDR     R0, [R1]
-    STR     LR, [R0]
+LDR R0, = ulCriticalNesting
+          LDR R0, [ R0 ]
+STMDB LR !, {
+    R0
+}
 
-    ENDM
+Store the new top of stack
+
+for the task.
+   LDR R1, = pxCurrentTCB
+             LDR R0, [ R1 ]
+STR LR, [ R0 ]
+
+ENDM
 
 
 portRESTORE_CONTEXT MACRO
 
-    ; Set the LR to the task stack.
-    LDR     R1, =pxCurrentTCB
-    LDR     R0, [R1]
-    LDR     LR, [R0]
+;
+Set the LR to the task stack.
+   LDR R1, = pxCurrentTCB
+             LDR R0, [ R1 ]
+LDR LR, [ R0 ]
 
-    ; The critical nesting depth is the first item on the stack.
-    ; Load it into the ulCriticalNesting variable.
-    LDR     R0, =ulCriticalNesting
-    LDMFD   LR!, {R1}
-    STR     R1, [R0]
+;
+The critical nesting depth is the first item on the stack.
+   ;
+Load it into the ulCriticalNesting variable.
+   LDR R0, = ulCriticalNesting
+             LDMFD LR !, {
+    R1
+}
 
-    ; Get the SPSR from the stack.
-    LDMFD   LR!, {R0}
-    MSR     SPSR_cxsf, R0
+STR R1, [ R0 ]
 
-    ; Restore all system mode registers for the task.
-    LDMFD   LR, {R0-R14}^
-    NOP
+;
+Get the SPSR from the stack.
+   LDMFD LR !, {
+    R0
+}
+MSR SPSR_cxsf, R0
 
-    ; Restore the return address.
-    LDR     LR, [LR, #+60]
+;
+Restore all system mode registers
 
-    ; And return - correcting the offset in the LR to obtain the
-    ; correct address.
-    SUBS    PC, LR, #4
+for the task.
+   LDMFD LR, {
+    R0 - R14
+}
 
-    ENDM
+^
+NOP
+
+;
+Restore the return address.
+          LDR LR, [ LR, # + 60 ]
+
+;
+
+And return -correcting the offset in the LR to obtain the
+;
+
+correct address.
+   SUBS PC, LR, # 4
+
+ENDM
diff --git a/portable/IAR/AtmelSAM9XE/port.c b/portable/IAR/AtmelSAM9XE/port.c
index cb4b7bed6..20c59b71f 100644
--- a/portable/IAR/AtmelSAM9XE/port.c
+++ b/portable/IAR/AtmelSAM9XE/port.c
@@ -27,8 +27,8 @@
  */
 
 /*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the Atmel ARM7 port.
- *----------------------------------------------------------*/
+* Implementation of functions defined in portable.h for the Atmel ARM7 port.
+*----------------------------------------------------------*/
 
 
 /* Standard includes. */
@@ -51,21 +51,21 @@
 /*-----------------------------------------------------------*/
 
 /* Constants required to setup the initial stack. */
-#define portINITIAL_SPSR                ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
-#define portTHUMB_MODE_BIT              ( ( StackType_t ) 0x20 )
-#define portINSTRUCTION_SIZE            ( ( StackType_t ) 4 )
+#define portINITIAL_SPSR           ( ( StackType_t ) 0x1f )      /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT         ( ( StackType_t ) 0x20 )
+#define portINSTRUCTION_SIZE       ( ( StackType_t ) 4 )
 
 /* Constants required to setup the PIT. */
-#define port1MHz_IN_Hz                  ( 1000000ul )
-#define port1SECOND_IN_uS               ( 1000000.0 )
+#define port1MHz_IN_Hz             ( 1000000ul )
+#define port1SECOND_IN_uS          ( 1000000.0 )
 
 /* Constants required to handle critical sections. */
-#define portNO_CRITICAL_NESTING         ( ( uint32_t ) 0 )
+#define portNO_CRITICAL_NESTING    ( ( uint32_t ) 0 )
 
 
-#define portINT_LEVEL_SENSITIVE  0
-#define portPIT_ENABLE          ( ( uint16_t ) 0x1 << 24 )
-#define portPIT_INT_ENABLE      ( ( uint16_t ) 0x1 << 25 )
+#define portINT_LEVEL_SENSITIVE    0
+#define portPIT_ENABLE             ( ( uint16_t ) 0x1 << 24 )
+#define portPIT_INT_ENABLE         ( ( uint16_t ) 0x1 << 25 )
 /*-----------------------------------------------------------*/
 
 /* Setup the PIT to generate the tick interrupts. */
@@ -75,8 +75,8 @@ static void prvSetupTimerInterrupt( void );
 static void vPortTickISR( void );
 
 /* ulCriticalNesting will get set to zero when the first task starts.  It
-cannot be initialised to 0 as this will cause interrupts to be enabled
-during the kernel initialisation process. */
+ * cannot be initialised to 0 as this will cause interrupts to be enabled
+ * during the kernel initialisation process. */
 uint32_t ulCriticalNesting = ( uint32_t ) 9999;
 
 /*-----------------------------------------------------------*/
@@ -87,56 +87,58 @@ uint32_t ulCriticalNesting = ( uint32_t ) 9999;
  *
  * See header file for description.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
-StackType_t *pxOriginalTOS;
+    StackType_t * pxOriginalTOS;
 
     pxOriginalTOS = pxTopOfStack;
 
     /* To ensure asserts in tasks.c don't fail, although in this case the assert
-    is not really required. */
+     * is not really required. */
     pxTopOfStack--;
 
     /* Setup the initial stack of the task.  The stack is set exactly as
-    expected by the portRESTORE_CONTEXT() macro. */
+     * expected by the portRESTORE_CONTEXT() macro. */
 
     /* First on the stack is the return address - which in this case is the
-    start of the task.  The offset is added to make the return address appear
-    as it would within an IRQ ISR. */
+     * start of the task.  The offset is added to make the return address appear
+     * as it would within an IRQ ISR. */
     *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
     pxTopOfStack--;
 
-    *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */
+    *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa;    /* R14 */
     pxTopOfStack--;
     *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
+    *pxTopOfStack = ( StackType_t ) 0x12121212;    /* R12 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
+    *pxTopOfStack = ( StackType_t ) 0x11111111;    /* R11 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
+    *pxTopOfStack = ( StackType_t ) 0x10101010;    /* R10 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
+    *pxTopOfStack = ( StackType_t ) 0x09090909;    /* R9 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
+    *pxTopOfStack = ( StackType_t ) 0x08080808;    /* R8 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
+    *pxTopOfStack = ( StackType_t ) 0x07070707;    /* R7 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
+    *pxTopOfStack = ( StackType_t ) 0x06060606;    /* R6 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
+    *pxTopOfStack = ( StackType_t ) 0x05050505;    /* R5 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
+    *pxTopOfStack = ( StackType_t ) 0x04040404;    /* R4 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
+    *pxTopOfStack = ( StackType_t ) 0x03030303;    /* R3 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
+    *pxTopOfStack = ( StackType_t ) 0x02020202;    /* R2 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
+    *pxTopOfStack = ( StackType_t ) 0x01010101;    /* R1 */
     pxTopOfStack--;
 
     /* When the task starts is will expect to find the function parameter in
-    R0. */
+     * R0. */
     *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
     pxTopOfStack--;
 
@@ -153,8 +155,8 @@ StackType_t *pxOriginalTOS;
     pxTopOfStack--;
 
     /* Interrupt flags cannot always be stored on the stack and will
-    instead be stored in a variable, which is then saved as part of the
-    tasks context. */
+     * instead be stored in a variable, which is then saved as part of the
+     * tasks context. */
     *pxTopOfStack = portNO_CRITICAL_NESTING;
 
     return pxTopOfStack;
@@ -163,10 +165,10 @@ StackType_t *pxOriginalTOS;
 
 BaseType_t xPortStartScheduler( void )
 {
-extern void vPortStartFirstTask( void );
+    extern void vPortStartFirstTask( void );
 
     /* Start the timer that generates the tick ISR.  Interrupts are disabled
-    here already. */
+     * here already. */
     prvSetupTimerInterrupt();
 
     /* Start the first task. */
@@ -180,17 +182,17 @@ extern void vPortStartFirstTask( void );
 void vPortEndScheduler( void )
 {
     /* It is unlikely that the ARM port will require this function as there
-    is nothing to return to.  */
+     * is nothing to return to.  */
 }
 /*-----------------------------------------------------------*/
 
 static __arm void vPortTickISR( void )
 {
-volatile uint32_t ulDummy;
+    volatile uint32_t ulDummy;
 
     /* Increment the tick count - which may wake some tasks but as the
-    preemptive scheduler is not being used any woken task is not given
-    processor time no matter what its priority. */
+     * preemptive scheduler is not being used any woken task is not given
+     * processor time no matter what its priority. */
     if( xTaskIncrementTick() != pdFALSE )
     {
         vTaskSwitchContext();
@@ -208,7 +210,7 @@ volatile uint32_t ulDummy;
 
 static void prvSetupTimerInterrupt( void )
 {
-const uint32_t ulPeriodIn_uS = ( 1.0 / ( double ) configTICK_RATE_HZ ) * port1SECOND_IN_uS;
+    const uint32_t ulPeriodIn_uS = ( 1.0 / ( double ) configTICK_RATE_HZ ) * port1SECOND_IN_uS;
 
     /* Setup the PIT for the required frequency. */
     PIT_Init( ulPeriodIn_uS, BOARD_MCK / port1MHz_IN_Hz );
@@ -226,9 +228,9 @@ void vPortEnterCritical( void )
     /* Disable interrupts first! */
     __disable_irq();
 
-    /* Now interrupts are disabled ulCriticalNesting can be accessed
-    directly.  Increment ulCriticalNesting to keep a count of how many times
-    portENTER_CRITICAL() has been called. */
+    /* Now that interrupts are disabled, ulCriticalNesting can be accessed
+     * directly.  Increment ulCriticalNesting to keep a count of how many times
+     * portENTER_CRITICAL() has been called. */
     ulCriticalNesting++;
 }
 /*-----------------------------------------------------------*/
@@ -241,7 +243,7 @@ void vPortExitCritical( void )
         ulCriticalNesting--;
 
         /* If the nesting level has reached zero then interrupts should be
-        re-enabled. */
+         * re-enabled. */
         if( ulCriticalNesting == portNO_CRITICAL_NESTING )
         {
             __enable_irq();
diff --git a/portable/IAR/AtmelSAM9XE/portmacro.h b/portable/IAR/AtmelSAM9XE/portmacro.h
index fdc7c2ba6..54af3f1d6 100644
--- a/portable/IAR/AtmelSAM9XE/portmacro.h
+++ b/portable/IAR/AtmelSAM9XE/portmacro.h
@@ -49,36 +49,36 @@
  */
 
 /* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint32_t
-#define portBASE_TYPE   long
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY ( TickType_t )    ( 0xFFFFFFFFUL )
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) ( 0xFFFFFFFFUL )
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portSTACK_GROWTH            ( -1 )
-#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT          8
-#define portYIELD()                 asm ( "SWI 0" )
-#define portNOP()                   asm ( "NOP" )
+#define portSTACK_GROWTH      ( -1 )
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT    8
+#define portYIELD()    asm ( "SWI 0" )
+#define portNOP()      asm ( "NOP" )
 /*-----------------------------------------------------------*/
 
 /* Critical section handling. */
@@ -94,21 +94,21 @@ __arm __interwork void vPortExitCritical( void );
 /*-----------------------------------------------------------*/
 
 /* Task utilities. */
-#define portEND_SWITCHING_ISR( xSwitchRequired )    \
-{                                                   \
-extern void vTaskSwitchContext( void );             \
-                                                    \
-    if( xSwitchRequired )                           \
-    {                                               \
-        vTaskSwitchContext();                       \
-    }                                               \
-}
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+    {                                            \
+        extern void vTaskSwitchContext( void );  \
+                                                 \
+        if( xSwitchRequired )                    \
+        {                                        \
+            vTaskSwitchContext();                \
+        }                                        \
+    }
 /*-----------------------------------------------------------*/
 
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/IAR/LPC2000/ISR_Support.h b/portable/IAR/LPC2000/ISR_Support.h
index 4651c2d13..d63e908b9 100644
--- a/portable/IAR/LPC2000/ISR_Support.h
+++ b/portable/IAR/LPC2000/ISR_Support.h
@@ -1,105 +1,151 @@
-;/*
-; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
-; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
-; *
-; * SPDX-License-Identifier: MIT
-; *
-; * Permission is hereby granted, free of charge, to any person obtaining a copy of
-; * this software and associated documentation files (the "Software"), to deal in
-; * the Software without restriction, including without limitation the rights to
-; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
-; * the Software, and to permit persons to whom the Software is furnished to do so,
-; * subject to the following conditions:
-; *
-; * The above copyright notice and this permission notice shall be included in all
-; * copies or substantial portions of the Software.
-; *
-; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-; *
-; * https://www.FreeRTOS.org
-; * https://github.com/FreeRTOS
-; *
-; */
+; /*
+   * ; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+   * ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+   * ; *
+   * ; * SPDX-License-Identifier: MIT
+   * ; *
+   * ; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+   * ; * this software and associated documentation files (the "Software"), to deal in
+   * ; * the Software without restriction, including without limitation the rights to
+   * ; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+   * ; * the Software, and to permit persons to whom the Software is furnished to do so,
+   * ; * subject to the following conditions:
+   * ; *
+   * ; * The above copyright notice and this permission notice shall be included in all
+   * ; * copies or substantial portions of the Software.
+   * ; *
+   * ; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+   * ; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+   * ; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+   * ; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+   * ; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+   * ; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+   * ; *
+   * ; * https://www.FreeRTOS.org
+   * ; * https://github.com/FreeRTOS
+   * ; *
+   * ; */
 
-    EXTERN pxCurrentTCB
-    EXTERN ulCriticalNesting
+EXTERN pxCurrentTCB
+EXTERN ulCriticalNesting
 
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Context save and restore macro definitions
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;
+Context save and restore macro definitions
+;
 
 portSAVE_CONTEXT MACRO
 
-    ; Push R0 as we are going to use the register.
-    STMDB   SP!, {R0}
+;
+Push R0 as we are going to use the register.
+   STMDB SP !, {
+    R0
+}
 
-    ; Set R0 to point to the task stack pointer.
-    STMDB   SP, {SP}^
-    NOP
-    SUB     SP, SP, #4
-    LDMIA   SP!, {R0}
+Set R0 to point to the task stack pointer.
+   STMDB SP, {
+    SP
+}
+^
+NOP
+SUB SP, SP, # 4
+LDMIA SP !, {
+    R0
+}
 
-    ; Push the return address onto the stack.
-    STMDB   R0!, {LR}
+;
+Push the return address onto the stack.
+          STMDB R0 !, {
+           LR
+       }
 
-    ; Now we have saved LR we can use it instead of R0.
-    MOV     LR, R0
+       Now we have saved LR we can use it instead of R0.
+          MOV LR, R0
 
-    ; Pop R0 so we can save it onto the system mode stack.
-    LDMIA   SP!, {R0}
+;
 
-    ; Push all the system mode registers onto the task stack.
-    STMDB   LR, {R0-LR}^
-    NOP
-    SUB     LR, LR, #60
+Pop R0 so we can save it onto the system mode stack.
+   LDMIA SP !, {
+    R0
+}
 
-    ; Push the SPSR onto the task stack.
-    MRS     R0, SPSR
-    STMDB   LR!, {R0}
+Push all the system mode registers onto the task stack.
+   STMDB LR, {
+    R0 - LR
+}
+^
+NOP
+SUB LR, LR, # 60
 
-    LDR     R0, =ulCriticalNesting
-    LDR     R0, [R0]
-    STMDB   LR!, {R0}
+;
+Push the SPSR onto the task stack.
+   MRS R0, SPSR
+STMDB LR !, {
+    R0
+}
 
-    ; Store the new top of stack for the task.
-    LDR     R1, =pxCurrentTCB
-    LDR     R0, [R1]
-    STR     LR, [R0]
+LDR R0, = ulCriticalNesting
+          LDR R0, [ R0 ]
+STMDB LR !, {
+    R0
+}
 
-    ENDM
+Store the new top of stack
+
+for the task.
+   LDR R1, = pxCurrentTCB
+             LDR R0, [ R1 ]
+STR LR, [ R0 ]
+
+ENDM
 
 
 portRESTORE_CONTEXT MACRO
 
-    ; Set the LR to the task stack.
-    LDR     R1, =pxCurrentTCB
-    LDR     R0, [R1]
-    LDR     LR, [R0]
+;
+Set the LR to the task stack.
+   LDR R1, = pxCurrentTCB
+             LDR R0, [ R1 ]
+LDR LR, [ R0 ]
 
-    ; The critical nesting depth is the first item on the stack.
-    ; Load it into the ulCriticalNesting variable.
-    LDR     R0, =ulCriticalNesting
-    LDMFD   LR!, {R1}
-    STR     R1, [R0]
+;
+The critical nesting depth is the first item on the stack.
+   ;
+Load it into the ulCriticalNesting variable.
+   LDR R0, = ulCriticalNesting
+             LDMFD LR !, {
+    R1
+}
 
-    ; Get the SPSR from the stack.
-    LDMFD   LR!, {R0}
-    MSR     SPSR_cxsf, R0
+STR R1, [ R0 ]
 
-    ; Restore all system mode registers for the task.
-    LDMFD   LR, {R0-R14}^
-    NOP
+;
+Get the SPSR from the stack.
+   LDMFD LR !, {
+    R0
+}
+MSR SPSR_cxsf, R0
 
-    ; Restore the return address.
-    LDR     LR, [LR, #+60]
+;
+Restore all system mode registers
 
-    ; And return - correcting the offset in the LR to obtain the
-    ; correct address.
-    SUBS    PC, LR, #4
+for the task.
+   LDMFD LR, {
+    R0 - R14
+}
 
-    ENDM
+^
+NOP
+
+;
+Restore the return address.
+          LDR LR, [ LR, # + 60 ]
+
+;
+
+And return -correcting the offset in the LR to obtain the
+;
+
+correct address.
+   SUBS PC, LR, # 4
+
+ENDM
diff --git a/portable/IAR/LPC2000/port.c b/portable/IAR/LPC2000/port.c
index 3758c5dcf..a8cf766ab 100644
--- a/portable/IAR/LPC2000/port.c
+++ b/portable/IAR/LPC2000/port.c
@@ -27,16 +27,16 @@
  */
 
 /*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the Philips ARM7 port.
- *----------------------------------------------------------*/
+* Implementation of functions defined in portable.h for the Philips ARM7 port.
+*----------------------------------------------------------*/
 
 /*
-    Changes from V3.2.2
-
-    + Bug fix - The prescale value for the timer setup is now written to T0PR
-      instead of T0PC.  This bug would have had no effect unless a prescale
-      value was actually used.
-*/
+ *  Changes from V3.2.2
+ *
+ + Bug fix - The prescale value for the timer setup is now written to T0PR
+ +    instead of T0PC.  This bug would have had no effect unless a prescale
+ +    value was actually used.
+ */
 
 /* Standard includes. */
 #include <stdlib.h>
@@ -47,36 +47,36 @@
 #include "task.h"
 
 /* Constants required to setup the tick ISR. */
-#define portENABLE_TIMER            ( ( uint8_t ) 0x01 )
-#define portPRESCALE_VALUE          0x00
-#define portINTERRUPT_ON_MATCH      ( ( uint32_t ) 0x01 )
-#define portRESET_COUNT_ON_MATCH    ( ( uint32_t ) 0x02 )
+#define portENABLE_TIMER             ( ( uint8_t ) 0x01 )
+#define portPRESCALE_VALUE           0x00
+#define portINTERRUPT_ON_MATCH       ( ( uint32_t ) 0x01 )
+#define portRESET_COUNT_ON_MATCH     ( ( uint32_t ) 0x02 )
 
 /* Constants required to setup the initial stack. */
-#define portINITIAL_SPSR                ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
-#define portTHUMB_MODE_BIT              ( ( StackType_t ) 0x20 )
-#define portINSTRUCTION_SIZE            ( ( StackType_t ) 4 )
+#define portINITIAL_SPSR             ( ( StackType_t ) 0x1f )    /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT           ( ( StackType_t ) 0x20 )
+#define portINSTRUCTION_SIZE         ( ( StackType_t ) 4 )
 
 /* Constants required to setup the PIT. */
-#define portPIT_CLOCK_DIVISOR           ( ( uint32_t ) 16 )
-#define portPIT_COUNTER_VALUE           ( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) * portTICK_PERIOD_MS )
+#define portPIT_CLOCK_DIVISOR        ( ( uint32_t ) 16 )
+#define portPIT_COUNTER_VALUE        ( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) * portTICK_PERIOD_MS )
 
 /* Constants required to handle interrupts. */
-#define portTIMER_MATCH_ISR_BIT     ( ( uint8_t ) 0x01 )
-#define portCLEAR_VIC_INTERRUPT     ( ( uint32_t ) 0 )
+#define portTIMER_MATCH_ISR_BIT      ( ( uint8_t ) 0x01 )
+#define portCLEAR_VIC_INTERRUPT      ( ( uint32_t ) 0 )
 
 /* Constants required to handle critical sections. */
-#define portNO_CRITICAL_NESTING         ( ( uint32_t ) 0 )
+#define portNO_CRITICAL_NESTING      ( ( uint32_t ) 0 )
 
 
-#define portINT_LEVEL_SENSITIVE  0
-#define portPIT_ENABLE          ( ( uint16_t ) 0x1 << 24 )
-#define portPIT_INT_ENABLE      ( ( uint16_t ) 0x1 << 25 )
+#define portINT_LEVEL_SENSITIVE      0
+#define portPIT_ENABLE               ( ( uint16_t ) 0x1 << 24 )
+#define portPIT_INT_ENABLE           ( ( uint16_t ) 0x1 << 25 )
 
 /* Constants required to setup the VIC for the tick ISR. */
-#define portTIMER_VIC_CHANNEL       ( ( uint32_t ) 0x0004 )
-#define portTIMER_VIC_CHANNEL_BIT   ( ( uint32_t ) 0x0010 )
-#define portTIMER_VIC_ENABLE        ( ( uint32_t ) 0x0020 )
+#define portTIMER_VIC_CHANNEL        ( ( uint32_t ) 0x0004 )
+#define portTIMER_VIC_CHANNEL_BIT    ( ( uint32_t ) 0x0010 )
+#define portTIMER_VIC_ENABLE         ( ( uint32_t ) 0x0020 )
 
 /*-----------------------------------------------------------*/
 
@@ -84,8 +84,8 @@
 static void prvSetupTimerInterrupt( void );
 
 /* ulCriticalNesting will get set to zero when the first task starts.  It
-cannot be initialised to 0 as this will cause interrupts to be enabled
-during the kernel initialisation process. */
+ * cannot be initialised to 0 as this will cause interrupts to be enabled
+ * during the kernel initialisation process. */
 uint32_t ulCriticalNesting = ( uint32_t ) 9999;
 
 /*-----------------------------------------------------------*/
@@ -96,52 +96,54 @@ uint32_t ulCriticalNesting = ( uint32_t ) 9999;
  *
  * See header file for description.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
-StackType_t *pxOriginalTOS;
+    StackType_t * pxOriginalTOS;
 
     pxOriginalTOS = pxTopOfStack;
 
     /* Setup the initial stack of the task.  The stack is set exactly as
-    expected by the portRESTORE_CONTEXT() macro. */
+     * expected by the portRESTORE_CONTEXT() macro. */
 
     /* First on the stack is the return address - which in this case is the
-    start of the task.  The offset is added to make the return address appear
-    as it would within an IRQ ISR. */
+     * start of the task.  The offset is added to make the return address appear
+     * as it would within an IRQ ISR. */
     *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
     pxTopOfStack--;
 
-    *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */
+    *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa;    /* R14 */
     pxTopOfStack--;
     *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
+    *pxTopOfStack = ( StackType_t ) 0x12121212;    /* R12 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
+    *pxTopOfStack = ( StackType_t ) 0x11111111;    /* R11 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
+    *pxTopOfStack = ( StackType_t ) 0x10101010;    /* R10 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
+    *pxTopOfStack = ( StackType_t ) 0x09090909;    /* R9 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
+    *pxTopOfStack = ( StackType_t ) 0x08080808;    /* R8 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
+    *pxTopOfStack = ( StackType_t ) 0x07070707;    /* R7 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
+    *pxTopOfStack = ( StackType_t ) 0x06060606;    /* R6 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
+    *pxTopOfStack = ( StackType_t ) 0x05050505;    /* R5 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
+    *pxTopOfStack = ( StackType_t ) 0x04040404;    /* R4 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
+    *pxTopOfStack = ( StackType_t ) 0x03030303;    /* R3 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
+    *pxTopOfStack = ( StackType_t ) 0x02020202;    /* R2 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
+    *pxTopOfStack = ( StackType_t ) 0x01010101;    /* R1 */
     pxTopOfStack--;
 
     /* When the task starts is will expect to find the function parameter in
-    R0. */
+     * R0. */
     *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
     pxTopOfStack--;
 
@@ -157,8 +159,8 @@ StackType_t *pxOriginalTOS;
     pxTopOfStack--;
 
     /* Interrupt flags cannot always be stored on the stack and will
-    instead be stored in a variable, which is then saved as part of the
-    tasks context. */
+     * instead be stored in a variable, which is then saved as part of the
+     * tasks context. */
     *pxTopOfStack = portNO_CRITICAL_NESTING;
 
     return pxTopOfStack;
@@ -167,10 +169,10 @@ StackType_t *pxOriginalTOS;
 
 BaseType_t xPortStartScheduler( void )
 {
-extern void vPortStartFirstTask( void );
+    extern void vPortStartFirstTask( void );
 
     /* Start the timer that generates the tick ISR.  Interrupts are disabled
-    here already. */
+     * here already. */
     prvSetupTimerInterrupt();
 
     /* Start the first task. */
@@ -184,20 +186,20 @@ extern void vPortStartFirstTask( void );
 void vPortEndScheduler( void )
 {
     /* It is unlikely that the ARM port will require this function as there
-    is nothing to return to.  */
+     * is nothing to return to.  */
 }
 /*-----------------------------------------------------------*/
 
 #if configUSE_PREEMPTION == 0
 
-    /* The cooperative scheduler requires a normal IRQ service routine to
-    simply increment the system tick. */
+/* The cooperative scheduler requires a normal IRQ service routine to
+ * simply increment the system tick. */
     static __arm __irq void vPortNonPreemptiveTick( void );
     static __arm __irq void vPortNonPreemptiveTick( void )
     {
         /* Increment the tick count - which may wake some tasks but as the
-        preemptive scheduler is not being used any woken task is not given
-        processor time no matter what its priority. */
+         * preemptive scheduler is not being used any woken task is not given
+         * processor time no matter what its priority. */
         xTaskIncrementTick();
 
         /* Ready for the next interrupt. */
@@ -205,10 +207,10 @@ void vPortEndScheduler( void )
         VICVectAddr = portCLEAR_VIC_INTERRUPT;
     }
 
-#else
+#else /* if configUSE_PREEMPTION == 0 */
 
-    /* This function is called from an asm wrapper, so does not require the __irq
-    keyword. */
+/* This function is called from an asm wrapper, so does not require the __irq
+ * keyword. */
     void vPortPreemptiveTick( void );
     void vPortPreemptiveTick( void )
     {
@@ -216,8 +218,8 @@ void vPortEndScheduler( void )
         if( xTaskIncrementTick() != pdFALSE )
         {
             /* The new tick value might unblock a task.  Ensure the highest task that
-            is ready to execute is the task that will execute when the tick ISR
-            exits. */
+             * is ready to execute is the task that will execute when the tick ISR
+             * exits. */
             vTaskSwitchContext();
         }
 
@@ -226,23 +228,23 @@ void vPortEndScheduler( void )
         VICVectAddr = portCLEAR_VIC_INTERRUPT;
     }
 
-#endif
+#endif /* if configUSE_PREEMPTION == 0 */
 
 /*-----------------------------------------------------------*/
 
 static void prvSetupTimerInterrupt( void )
 {
-uint32_t ulCompareMatch;
+    uint32_t ulCompareMatch;
 
     /* A 1ms tick does not require the use of the timer prescale.  This is
-    defaulted to zero but can be used if necessary. */
+     * defaulted to zero but can be used if necessary. */
     T0PR = portPRESCALE_VALUE;
 
     /* Calculate the match value required for our wanted tick rate. */
     ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
 
     /* Protect against divide by zero.  Using an if() statement still results
-    in a warning - hence the #if. */
+     * in a warning - hence the #if. */
     #if portPRESCALE_VALUE != 0
     {
         ulCompareMatch /= ( portPRESCALE_VALUE + 1 );
@@ -259,25 +261,25 @@ uint32_t ulCompareMatch;
     VICIntEnable |= portTIMER_VIC_CHANNEL_BIT;
 
     /* The ISR installed depends on whether the preemptive or cooperative
-    scheduler is being used. */
+     * scheduler is being used. */
     #if configUSE_PREEMPTION == 1
     {
-        extern void ( vPortPreemptiveTickEntry )( void );
+        extern void( vPortPreemptiveTickEntry )( void );
 
         VICVectAddr0 = ( uint32_t ) vPortPreemptiveTickEntry;
     }
     #else
     {
-        extern void ( vNonPreemptiveTick )( void );
+        extern void( vNonPreemptiveTick )( void );
 
         VICVectAddr0 = ( int32_t ) vPortNonPreemptiveTick;
     }
-    #endif
+    #endif /* if configUSE_PREEMPTION == 1 */
 
     VICVectCntl0 = portTIMER_VIC_CHANNEL | portTIMER_VIC_ENABLE;
 
     /* Start the timer - interrupts are disabled when this function is called
-    so it is okay to do this here. */
+     * so it is okay to do this here. */
     T0TCR = portENABLE_TIMER;
 }
 /*-----------------------------------------------------------*/
@@ -287,9 +289,9 @@ void vPortEnterCritical( void )
     /* Disable interrupts first! */
     __disable_interrupt();
 
-    /* Now interrupts are disabled ulCriticalNesting can be accessed
-    directly.  Increment ulCriticalNesting to keep a count of how many times
-    portENTER_CRITICAL() has been called. */
+    /* Now that interrupts are disabled, ulCriticalNesting can be accessed
+     * directly.  Increment ulCriticalNesting to keep a count of how many times
+     * portENTER_CRITICAL() has been called. */
     ulCriticalNesting++;
 }
 /*-----------------------------------------------------------*/
@@ -302,7 +304,7 @@ void vPortExitCritical( void )
         ulCriticalNesting--;
 
         /* If the nesting level has reached zero then interrupts should be
-        re-enabled. */
+         * re-enabled. */
         if( ulCriticalNesting == portNO_CRITICAL_NESTING )
         {
             __enable_interrupt();
diff --git a/portable/IAR/LPC2000/portmacro.h b/portable/IAR/LPC2000/portmacro.h
index 2929ecba5..28b8d7e77 100644
--- a/portable/IAR/LPC2000/portmacro.h
+++ b/portable/IAR/LPC2000/portmacro.h
@@ -49,36 +49,36 @@
  */
 
 /* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint32_t
-#define portBASE_TYPE   long
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY ( TickType_t )    ( 0xFFFFFFFFUL )
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) ( 0xFFFFFFFFUL )
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portSTACK_GROWTH            ( -1 )
-#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT          8
-#define portYIELD()                 asm ( "SWI 0" )
-#define portNOP()                   asm ( "NOP" )
+#define portSTACK_GROWTH      ( -1 )
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT    8
+#define portYIELD()    asm ( "SWI 0" )
+#define portNOP()      asm ( "NOP" )
 /*-----------------------------------------------------------*/
 
 /* Critical section handling. */
@@ -94,20 +94,20 @@ __arm __interwork void vPortExitCritical( void );
 /*-----------------------------------------------------------*/
 
 /* Task utilities. */
-#define portEND_SWITCHING_ISR( xSwitchRequired )    \
-{                                                   \
-extern void vTaskSwitchContext( void );             \
-                                                    \
-    if( xSwitchRequired )                           \
-    {                                               \
-        vTaskSwitchContext();                       \
-    }                                               \
-}
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+    {                                            \
+        extern void vTaskSwitchContext( void );  \
+                                                 \
+        if( xSwitchRequired )                    \
+        {                                        \
+            vTaskSwitchContext();                \
+        }                                        \
+    }
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/IAR/MSP430/port.c b/portable/IAR/MSP430/port.c
index 4375634d7..845943c7f 100644
--- a/portable/IAR/MSP430/port.c
+++ b/portable/IAR/MSP430/port.c
@@ -31,28 +31,28 @@
 #include "task.h"
 
 /*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the MSP430 port.
- *----------------------------------------------------------*/
+* Implementation of functions defined in portable.h for the MSP430 port.
+*----------------------------------------------------------*/
 
 /* Constants required for hardware setup.  The tick ISR runs off the ACLK,
-not the MCLK. */
+ * not the MCLK. */
 #define portACLK_FREQUENCY_HZ           ( ( TickType_t ) 32768 )
 #define portINITIAL_CRITICAL_NESTING    ( ( uint16_t ) 10 )
 #define portFLAGS_INT_ENABLED           ( ( StackType_t ) 0x08 )
 
 /* We require the address of the pxCurrentTCB variable, but don't want to know
-any details of its type. */
+ * any details of its type. */
 typedef void TCB_t;
 extern volatile TCB_t * volatile pxCurrentTCB;
 
 /* Each task maintains a count of the critical section nesting depth.  Each
-time a critical section is entered the count is incremented.  Each time a
-critical section is exited the count is decremented - with interrupts only
-being re-enabled if the count is zero.
-
-usCriticalNesting will get set to zero when the scheduler starts, but must
-not be initialised to zero as this will cause problems during the startup
-sequence. */
+ * time a critical section is entered the count is incremented.  Each time a
+ * critical section is exited the count is decremented - with interrupts only
+ * being re-enabled if the count is zero.
+ *
+ * usCriticalNesting will get set to zero when the scheduler starts, but must
+ * not be initialised to zero as this will cause problems during the startup
+ * sequence. */
 volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;
 /*-----------------------------------------------------------*/
 
@@ -70,24 +70,26 @@ void vPortSetupTimerInterrupt( void );
  *
  * See the header file portable.h.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
     /*
-        Place a few bytes of known values on the bottom of the stack.
-        This is just useful for debugging and can be included if required.
-
-        *pxTopOfStack = ( StackType_t ) 0x1111;
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x2222;
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x3333;
-        pxTopOfStack--;
-    */
+     *  Place a few bytes of known values on the bottom of the stack.
+     *  This is just useful for debugging and can be included if required.
+     *
+     * pxTopOfStack = ( StackType_t ) 0x1111;
+     *  pxTopOfStack--;
+     * pxTopOfStack = ( StackType_t ) 0x2222;
+     *  pxTopOfStack--;
+     * pxTopOfStack = ( StackType_t ) 0x3333;
+     *  pxTopOfStack--;
+     */
 
     /* The msp430 automatically pushes the PC then SR onto the stack before
-    executing an ISR.  We want the stack to look just as if this has happened
-    so place a pointer to the start of the task on the stack first - followed
-    by the flags we want the task to use when it starts up. */
+     * executing an ISR.  We want the stack to look just as if this has happened
+     * so place a pointer to the start of the task on the stack first - followed
+     * by the flags we want the task to use when it starts up. */
     *pxTopOfStack = ( StackType_t ) pxCode;
     pxTopOfStack--;
     *pxTopOfStack = portFLAGS_INT_ENABLED;
@@ -112,7 +114,7 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
     pxTopOfStack--;
 
     /* When the task starts is will expect to find the function parameter in
-    R15. */
+     * R15. */
     *pxTopOfStack = ( StackType_t ) pvParameters;
     pxTopOfStack--;
 
@@ -124,12 +126,12 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
     pxTopOfStack--;
 
     /* A variable is used to keep track of the critical section nesting.
-    This variable has to be stored as part of the task context and is
-    initially set to zero. */
+     * This variable has to be stored as part of the task context and is
+     * initially set to zero. */
     *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;
 
     /* Return a pointer to the top of the stack we have generated so this can
-    be stored in the task control block for the task. */
+     * be stored in the task control block for the task. */
     return pxTopOfStack;
 }
 /*-----------------------------------------------------------*/
@@ -137,7 +139,7 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
 void vPortEndScheduler( void )
 {
     /* It is unlikely that the MSP430 port will get stopped.  If required simply
-    disable the tick interrupt here. */
+     * disable the tick interrupt here. */
 }
 /*-----------------------------------------------------------*/
 
@@ -169,6 +171,3 @@ void vPortSetupTimerInterrupt( void )
     TACTL |= MC_1;
 }
 /*-----------------------------------------------------------*/
-
-
-
diff --git a/portable/IAR/MSP430/portasm.h b/portable/IAR/MSP430/portasm.h
index 5a8fa0a52..a9d49b7ff 100644
--- a/portable/IAR/MSP430/portasm.h
+++ b/portable/IAR/MSP430/portasm.h
@@ -31,54 +31,54 @@
 
 portSAVE_CONTEXT macro
 
-        IMPORT pxCurrentTCB
-        IMPORT usCriticalNesting
+IMPORT pxCurrentTCB
+IMPORT usCriticalNesting
 
-        /* Save the remaining registers. */
-        push    r4
-        push    r5
-        push    r6
-        push    r7
-        push    r8
-        push    r9
-        push    r10
-        push    r11
-        push    r12
-        push    r13
-        push    r14
-        push    r15
-        mov.w   &usCriticalNesting, r14
-        push    r14
-        mov.w   &pxCurrentTCB, r12
-        mov.w   r1, 0(r12)
-        endm
+/* Save the remaining registers. */
+push r4
+push r5
+push r6
+push r7
+push r8
+push r9
+push r10
+push r11
+push r12
+push r13
+push r14
+push r15
+mov.w &usCriticalNesting, r14
+push r14
+       mov.w &pxCurrentTCB, r12
+       mov.w r1, 0 ( r12 )
+endm
 /*-----------------------------------------------------------*/
 
 portRESTORE_CONTEXT macro
-        mov.w   &pxCurrentTCB, r12
-        mov.w   @r12, r1
-        pop     r15
-        mov.w   r15, &usCriticalNesting
-        pop     r15
-        pop     r14
-        pop     r13
-        pop     r12
-        pop     r11
-        pop     r10
-        pop     r9
-        pop     r8
-        pop     r7
-        pop     r6
-        pop     r5
-        pop     r4
+mov.w & pxCurrentTCB, r12
+mov.w @r12, r1
+pop r15
+mov.w r15, &usCriticalNesting
+pop r15
+pop r14
+pop r13
+pop r12
+pop r11
+pop r10
+pop r9
+pop r8
+pop r7
+pop r6
+pop r5
+pop r4
 
-        /* The last thing on the stack will be the status register.
-        Ensure the power down bits are clear ready for the next
-        time this power down register is popped from the stack. */
-        bic.w   #0xf0,0(SP)
+/* The last thing on the stack will be the status register.
+ * Ensure the power down bits are clear ready for the next
+ * time this power down register is popped from the stack. */
+bic.w   # 0xf0, 0 ( SP )
 
-        reti
-        endm
+reti
+endm
 /*-----------------------------------------------------------*/
 
-#endif
+#endif /* ifndef PORTASM_H */
diff --git a/portable/IAR/MSP430/portmacro.h b/portable/IAR/MSP430/portmacro.h
index 6dcec2f03..51b8aad1e 100644
--- a/portable/IAR/MSP430/portmacro.h
+++ b/portable/IAR/MSP430/portmacro.h
@@ -40,25 +40,25 @@
  */
 
 /* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       int
-#define portSTACK_TYPE  uint16_t
-#define portBASE_TYPE   short
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         int
+#define portSTACK_TYPE    uint16_t
+#define portBASE_TYPE     short
 
-typedef portSTACK_TYPE StackType_t;
-typedef short BaseType_t;
-typedef unsigned short UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef short            BaseType_t;
+typedef unsigned short   UBaseType_t;
 
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY ( TickType_t )    ( 0xFFFFFFFFUL )
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) ( 0xFFFFFFFFUL )
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
@@ -71,37 +71,37 @@ typedef unsigned short UBaseType_t;
 /*-----------------------------------------------------------*/
 
 /* Critical section control macros. */
-#define portNO_CRITICAL_SECTION_NESTING     ( ( uint16_t ) 0 )
+#define portNO_CRITICAL_SECTION_NESTING    ( ( uint16_t ) 0 )
 
-#define portENTER_CRITICAL()                                                    \
-{                                                                               \
-extern volatile uint16_t usCriticalNesting;                         \
-                                                                                \
-    portDISABLE_INTERRUPTS();                                                   \
-                                                                                \
-    /* Now interrupts are disabled usCriticalNesting can be accessed */         \
-    /* directly.  Increment ulCriticalNesting to keep a count of how many */    \
-    /* times portENTER_CRITICAL() has been called. */                           \
-    usCriticalNesting++;                                                        \
-}
+#define portENTER_CRITICAL()                                                     \
+    {                                                                            \
+        extern volatile uint16_t usCriticalNesting;                              \
+                                                                                 \
+        portDISABLE_INTERRUPTS();                                                \
+                                                                                 \
+        /* Now interrupts are disabled usCriticalNesting can be accessed */      \
+        /* directly.  Increment ulCriticalNesting to keep a count of how many */ \
+        /* times portENTER_CRITICAL() has been called. */                        \
+        usCriticalNesting++;                                                     \
+    }
 
-#define portEXIT_CRITICAL()                                                     \
-{                                                                               \
-extern volatile uint16_t usCriticalNesting;                         \
-                                                                                \
-    if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING )                   \
-    {                                                                           \
-        /* Decrement the nesting count as we are leaving a critical section. */ \
-        usCriticalNesting--;                                                    \
-                                                                                \
-        /* If the nesting level has reached zero then interrupts should be */   \
-        /* re-enabled. */                                                       \
-        if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING )              \
-        {                                                                       \
-            portENABLE_INTERRUPTS();                                            \
-        }                                                                       \
-    }                                                                           \
-}
+#define portEXIT_CRITICAL()                                                         \
+    {                                                                               \
+        extern volatile uint16_t usCriticalNesting;                                 \
+                                                                                    \
+        if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING )                   \
+        {                                                                           \
+            /* Decrement the nesting count as we are leaving a critical section. */ \
+            usCriticalNesting--;                                                    \
+                                                                                    \
+            /* If the nesting level has reached zero then interrupts should be */   \
+            /* re-enabled. */                                                       \
+            if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING )              \
+            {                                                                       \
+                portENABLE_INTERRUPTS();                                            \
+            }                                                                       \
+        }                                                                           \
+    }
 /*-----------------------------------------------------------*/
 
 /* Task utilities. */
@@ -110,25 +110,25 @@ extern volatile uint16_t usCriticalNesting;                         \
  * Manual context switch called by portYIELD or taskYIELD.
  */
 extern void vPortYield( void );
-#define portYIELD() vPortYield()
+#define portYIELD()    vPortYield()
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portBYTE_ALIGNMENT          2
-#define portSTACK_GROWTH            ( -1 )
-#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT       2
+#define portSTACK_GROWTH         ( -1 )
+#define portTICK_PERIOD_MS       ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
 #define portNOP()
-#define portPOINTER_SIZE_TYPE       uint16_t
+#define portPOINTER_SIZE_TYPE    uint16_t
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
 #if configINTERRUPT_EXAMPLE_METHOD == 2
 
-extern void vTaskSwitchContext( void );
-#define portYIELD_FROM_ISR( x ) do { if( x ) vTaskSwitchContext(); } while( 0 )
+    extern void vTaskSwitchContext( void );
+    #define portYIELD_FROM_ISR( x )    do { if( x ) vTaskSwitchContext( ); } while( 0 )
 
 #endif
 
diff --git a/portable/IAR/MSP430X/data_model.h b/portable/IAR/MSP430X/data_model.h
index 060135603..97931f3b5 100644
--- a/portable/IAR/MSP430X/data_model.h
+++ b/portable/IAR/MSP430X/data_model.h
@@ -30,30 +30,30 @@
 #define DATA_MODEL_H
 
 #if __DATA_MODEL__ == __DATA_MODEL_SMALL__
-    #define pushm_x pushm.w
-    #define popm_x popm.w
-    #define push_x push.w
-    #define pop_x pop.w
-    #define mov_x mov.w
-    #define cmp_x cmp.w
+    #define pushm_x    pushm.w
+    #define popm_x     popm.w
+    #define push_x     push.w
+    #define pop_x      pop.w
+    #define mov_x      mov.w
+    #define cmp_x      cmp.w
 #endif
 
 #if __DATA_MODEL__ == __DATA_MODEL_MEDIUM__
-    #define pushm_x pushm.a
-    #define popm_x popm.a
-    #define push_x pushx.a
-    #define pop_x popx.a
-    #define mov_x mov.w
-    #define cmp_x cmp.w
+    #define pushm_x    pushm.a
+    #define popm_x     popm.a
+    #define push_x     pushx.a
+    #define pop_x      popx.a
+    #define mov_x      mov.w
+    #define cmp_x      cmp.w
 #endif
 
 #if __DATA_MODEL__ == __DATA_MODEL_LARGE__
-    #define pushm_x pushm.a
-    #define popm_x popm.a
-    #define push_x pushx.a
-    #define pop_x popx.a
-    #define mov_x movx.a
-    #define cmp_x cmpx.a
+    #define pushm_x    pushm.a
+    #define popm_x     popm.a
+    #define push_x     pushx.a
+    #define pop_x      popx.a
+    #define mov_x      movx.a
+    #define cmp_x      cmpx.a
 #endif
 
 #ifndef pushm_x
diff --git a/portable/IAR/MSP430X/port.c b/portable/IAR/MSP430X/port.c
index ea35d9ac7..920f0796f 100644
--- a/portable/IAR/MSP430X/port.c
+++ b/portable/IAR/MSP430X/port.c
@@ -31,28 +31,28 @@
 #include "task.h"
 
 /*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the MSP430X port.
- *----------------------------------------------------------*/
+* Implementation of functions defined in portable.h for the MSP430X port.
+*----------------------------------------------------------*/
 
 /* Constants required for hardware setup.  The tick ISR runs off the ACLK,
-not the MCLK. */
+ * not the MCLK. */
 #define portACLK_FREQUENCY_HZ           ( ( TickType_t ) 32768 )
 #define portINITIAL_CRITICAL_NESTING    ( ( uint16_t ) 10 )
 #define portFLAGS_INT_ENABLED           ( ( StackType_t ) 0x08 )
 
 /* We require the address of the pxCurrentTCB variable, but don't want to know
-any details of its type. */
+ * any details of its type. */
 typedef void TCB_t;
 extern volatile TCB_t * volatile pxCurrentTCB;
 
 /* Each task maintains a count of the critical section nesting depth.  Each
-time a critical section is entered the count is incremented.  Each time a
-critical section is exited the count is decremented - with interrupts only
-being re-enabled if the count is zero.
-
-usCriticalNesting will get set to zero when the scheduler starts, but must
-not be initialised to zero as this will cause problems during the startup
-sequence. */
+ * time a critical section is entered the count is incremented.  Each time a
+ * critical section is exited the count is decremented - with interrupts only
+ * being re-enabled if the count is zero.
+ *
+ * usCriticalNesting will get set to zero when the scheduler starts, but must
+ * not be initialised to zero as this will cause problems during the startup
+ * sequence. */
 volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;
 /*-----------------------------------------------------------*/
 
@@ -70,26 +70,28 @@ void vPortSetupTimerInterrupt( void );
  *
  * See the header file portable.h.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
-uint16_t *pusTopOfStack;
-uint32_t *pulTopOfStack;
+    uint16_t * pusTopOfStack;
+    uint32_t * pulTopOfStack;
 
     /*
-        Place a few bytes of known values on the bottom of the stack.
-        This is just useful for debugging and can be included if required.
-
-        *pxTopOfStack = ( StackType_t ) 0x1111;
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x2222;
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x3333;
-    */
+     *  Place a few bytes of known values on the bottom of the stack.
+     *  This is just useful for debugging and can be included if required.
+     *
+     * pxTopOfStack = ( StackType_t ) 0x1111;
+     *  pxTopOfStack--;
+     * pxTopOfStack = ( StackType_t ) 0x2222;
+     *  pxTopOfStack--;
+     * pxTopOfStack = ( StackType_t ) 0x3333;
+     */
 
     /* StackType_t is either 16 bits or 32 bits depending on the data model.
-    Some stacked items do not change size depending on the data model so have
-    to be explicitly cast to the correct size so this function will work
-    whichever data model is being used. */
+     * Some stacked items do not change size depending on the data model so have
+     * to be explicitly cast to the correct size so this function will work
+     * whichever data model is being used. */
     if( sizeof( StackType_t ) == sizeof( uint16_t ) )
     {
         /* Make room for a 20 bit value stored as a 32 bit value. */
@@ -101,6 +103,7 @@ uint32_t *pulTopOfStack;
     {
         pulTopOfStack = ( uint32_t * ) pxTopOfStack;
     }
+
     *pulTopOfStack = ( uint32_t ) pxCode;
 
     pusTopOfStack = ( uint16_t * ) pulTopOfStack;
@@ -137,20 +140,20 @@ uint32_t *pulTopOfStack;
         pxTopOfStack--;
         *pxTopOfStack = ( StackType_t ) 0x4444;
         pxTopOfStack--;
-    #else
+    #else /* ifdef PRELOAD_REGISTER_VALUES */
         pxTopOfStack -= 3;
         *pxTopOfStack = ( StackType_t ) pvParameters;
         pxTopOfStack -= 9;
-    #endif
+    #endif /* ifdef PRELOAD_REGISTER_VALUES */
 
 
     /* A variable is used to keep track of the critical section nesting.
-    This variable has to be stored as part of the task context and is
-    initially set to zero. */
+     * This variable has to be stored as part of the task context and is
+     * initially set to zero. */
     *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;
 
     /* Return a pointer to the top of the stack we have generated so this can
-    be stored in the task control block for the task. */
+     * be stored in the task control block for the task. */
     return pxTopOfStack;
 }
 /*-----------------------------------------------------------*/
@@ -158,7 +161,7 @@ uint32_t *pulTopOfStack;
 void vPortEndScheduler( void )
 {
     /* It is unlikely that the MSP430 port will get stopped.  If required simply
-    disable the tick interrupt here. */
+     * disable the tick interrupt here. */
 }
 /*-----------------------------------------------------------*/
 
@@ -174,10 +177,8 @@ void vPortSetupTimerInterrupt( void )
 #pragma vector=configTICK_VECTOR
 __interrupt __raw void vTickISREntry( void )
 {
-extern void vPortTickISR( void );
+    extern void vPortTickISR( void );
 
     __bic_SR_register_on_exit( SCG1 + SCG0 + OSCOFF + CPUOFF );
     vPortTickISR();
 }
-
-
diff --git a/portable/IAR/MSP430X/portmacro.h b/portable/IAR/MSP430X/portmacro.h
index 72456cf11..bac91e8a4 100644
--- a/portable/IAR/MSP430X/portmacro.h
+++ b/portable/IAR/MSP430X/portmacro.h
@@ -43,31 +43,31 @@
 #include "msp430.h"
 
 /* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       int
-#define portBASE_TYPE   short
+#define portCHAR         char
+#define portFLOAT        float
+#define portDOUBLE       double
+#define portLONG         long
+#define portSHORT        int
+#define portBASE_TYPE    short
 
 /* The stack type changes depending on the data model. */
-#if( __DATA_MODEL__ == __DATA_MODEL_SMALL__ )
-    #define portSTACK_TYPE uint16_t
-    #define portPOINTER_SIZE_TYPE uint16_t
+#if ( __DATA_MODEL__ == __DATA_MODEL_SMALL__ )
+    #define portSTACK_TYPE           uint16_t
+    #define portPOINTER_SIZE_TYPE    uint16_t
 #else
-    #define portSTACK_TYPE uint32_t
+    #define portSTACK_TYPE           uint32_t
 #endif
 
-typedef portSTACK_TYPE StackType_t;
-typedef short BaseType_t;
-typedef unsigned short UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef short            BaseType_t;
+typedef unsigned short   UBaseType_t;
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY ( TickType_t )    ( 0xFFFFFFFFUL )
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) ( 0xFFFFFFFFUL )
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
@@ -80,37 +80,37 @@ typedef unsigned short UBaseType_t;
 /*-----------------------------------------------------------*/
 
 /* Critical section control macros. */
-#define portNO_CRITICAL_SECTION_NESTING     ( ( uint16_t ) 0 )
+#define portNO_CRITICAL_SECTION_NESTING    ( ( uint16_t ) 0 )
 
-#define portENTER_CRITICAL()                                                    \
-{                                                                               \
-extern volatile uint16_t usCriticalNesting;                                     \
-                                                                                \
-    portDISABLE_INTERRUPTS();                                                   \
-                                                                                \
-    /* Now interrupts are disabled usCriticalNesting can be accessed */         \
-    /* directly.  Increment ulCriticalNesting to keep a count of how many */    \
-    /* times portENTER_CRITICAL() has been called. */                           \
-    usCriticalNesting++;                                                        \
-}
+#define portENTER_CRITICAL()                                                     \
+    {                                                                            \
+        extern volatile uint16_t usCriticalNesting;                              \
+                                                                                 \
+        portDISABLE_INTERRUPTS();                                                \
+                                                                                 \
+        /* Now interrupts are disabled usCriticalNesting can be accessed */      \
+        /* directly.  Increment ulCriticalNesting to keep a count of how many */ \
+        /* times portENTER_CRITICAL() has been called. */                        \
+        usCriticalNesting++;                                                     \
+    }
 
-#define portEXIT_CRITICAL()                                                     \
-{                                                                               \
-extern volatile uint16_t usCriticalNesting;                                     \
-                                                                                \
-    if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING )                   \
-    {                                                                           \
-        /* Decrement the nesting count as we are leaving a critical section. */ \
-        usCriticalNesting--;                                                    \
-                                                                                \
-        /* If the nesting level has reached zero then interrupts should be */   \
-        /* re-enabled. */                                                       \
-        if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING )              \
-        {                                                                       \
-            portENABLE_INTERRUPTS();                                            \
-        }                                                                       \
-    }                                                                           \
-}
+#define portEXIT_CRITICAL()                                                         \
+    {                                                                               \
+        extern volatile uint16_t usCriticalNesting;                                 \
+                                                                                    \
+        if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING )                   \
+        {                                                                           \
+            /* Decrement the nesting count as we are leaving a critical section. */ \
+            usCriticalNesting--;                                                    \
+                                                                                    \
+            /* If the nesting level has reached zero then interrupts should be */   \
+            /* re-enabled. */                                                       \
+            if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING )              \
+            {                                                                       \
+                portENABLE_INTERRUPTS();                                            \
+            }                                                                       \
+        }                                                                           \
+    }
 /*-----------------------------------------------------------*/
 
 /* Task utilities. */
@@ -119,26 +119,26 @@ extern volatile uint16_t usCriticalNesting;
  * Manual context switch called by portYIELD or taskYIELD.
  */
 extern void vPortYield( void );
-#define portYIELD() vPortYield()
+#define portYIELD()    vPortYield()
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portBYTE_ALIGNMENT          2
-#define portSTACK_GROWTH            ( -1 )
-#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portNOP()                   __no_operation()
+#define portBYTE_ALIGNMENT    2
+#define portSTACK_GROWTH      ( -1 )
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()    __no_operation()
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
-#define portYIELD_FROM_ISR( x ) do { if( x ) vPortYield(); } while( 0 )
+#define portYIELD_FROM_ISR( x )                               do { if( x ) vPortYield( ); } while( 0 )
 
 void vApplicationSetupTimerInterrupt( void );
 
 /* sizeof( int ) != sizeof( long ) so a full printf() library is required if
-run time stats information is to be displayed. */
+ * run time stats information is to be displayed. */
 #define portLU_PRINTF_SPECIFIER_REQUIRED
 
 #endif /* PORTMACRO_H */
diff --git a/portable/IAR/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h b/portable/IAR/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h
index 326183148..01100f0a9 100644
--- a/portable/IAR/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h
+++ b/portable/IAR/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h
@@ -54,16 +54,16 @@
 #ifndef __FREERTOS_RISC_V_EXTENSIONS_H__
 #define __FREERTOS_RISC_V_EXTENSIONS_H__
 
-#define portasmHAS_SIFIVE_CLINT 1
-#define portasmHAS_MTIME 1
-#define portasmADDITIONAL_CONTEXT_SIZE 0 /* Must be even number on 32-bit cores. */
+#define portasmHAS_SIFIVE_CLINT           1
+#define portasmHAS_MTIME                  1
+#define portasmADDITIONAL_CONTEXT_SIZE    0 /* Must be even number on 32-bit cores. */
 
 portasmSAVE_ADDITIONAL_REGISTERS MACRO
-    /* No additional registers to save, so this macro does nothing. */
-    ENDM
+/* No additional registers to save, so this macro does nothing. */
+ENDM
 
 portasmRESTORE_ADDITIONAL_REGISTERS MACRO
-    /* No additional registers to restore, so this macro does nothing. */
+/* No additional registers to restore, so this macro does nothing. */
     ENDM
 
 #endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */
diff --git a/portable/IAR/RISC-V/port.c b/portable/IAR/RISC-V/port.c
index 984b8338a..ce0cbdf2f 100644
--- a/portable/IAR/RISC-V/port.c
+++ b/portable/IAR/RISC-V/port.c
@@ -39,15 +39,15 @@
 #include "string.h"
 
 #ifdef configCLINT_BASE_ADDRESS
-    #warning The configCLINT_BASE_ADDRESS constant has been deprecated.  configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS are currently being derived from the (possibly 0) configCLINT_BASE_ADDRESS setting.  Please update to define configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS dirctly in place of configCLINT_BASE_ADDRESS.  See https: /*www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html */
+    #warning "The configCLINT_BASE_ADDRESS constant has been deprecated.  configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS are currently being derived from the (possibly 0) configCLINT_BASE_ADDRESS setting.  Please update to define configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS directly in place of configCLINT_BASE_ADDRESS.  See www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html"
 #endif
 
 #ifndef configMTIME_BASE_ADDRESS
-    #warning configMTIME_BASE_ADDRESS must be defined in FreeRTOSConfig.h.  If the target chip includes a memory-mapped mtime register then set configMTIME_BASE_ADDRESS to the mapped address.  Otherwise set configMTIME_BASE_ADDRESS to 0.  See https: /*www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html */
+    #warning "configMTIME_BASE_ADDRESS must be defined in FreeRTOSConfig.h.  If the target chip includes a memory-mapped mtime register then set configMTIME_BASE_ADDRESS to the mapped address.  Otherwise set configMTIME_BASE_ADDRESS to 0.  See www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html"
 #endif
 
 #ifndef configMTIMECMP_BASE_ADDRESS
-    #warning configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h.  If the target chip includes a memory-mapped mtimecmp register then set configMTIMECMP_BASE_ADDRESS to the mapped address.  Otherwise set configMTIMECMP_BASE_ADDRESS to 0.  See https: /*www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html */
+    #warning "configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h.  If the target chip includes a memory-mapped mtimecmp register then set configMTIMECMP_BASE_ADDRESS to the mapped address.  Otherwise set configMTIMECMP_BASE_ADDRESS to 0.  See www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html"
 #endif
 
 /* Let the user override the pre-loading of the initial LR with the address of
@@ -70,7 +70,7 @@
 static __attribute__( ( aligned( 16 ) ) ) StackType_t xISRStack[ configISR_STACK_SIZE_WORDS ] = { 0 };
 const StackType_t xISRStackTop = ( StackType_t ) &( xISRStack[ configISR_STACK_SIZE_WORDS & ~portBYTE_ALIGNMENT_MASK ] );
 
-/* Don't use 0xa5 as the stack fill bytes as that is used by the kernerl for
+/* Don't use 0xa5 as the stack fill bytes as that is used by the kernel for
  * the task stacks, and so will legitimately appear in many positions within
  * the ISR stack. */
     #define portISR_STACK_FILL_BYTE    0xee
@@ -114,7 +114,7 @@ size_t xTaskReturnAddress = ( size_t ) portTASK_RETURN_ADDRESS;
  * the stack overflow hook function (because the stack overflow hook is specific
  * to a task stack, not the ISR stack). */
 #if defined( configISR_STACK_SIZE_WORDS ) && ( configCHECK_FOR_STACK_OVERFLOW > 2 )
-    #warning This path not tested, or even compiled yet.
+    #warning "This path not tested, or even compiled yet."
 
     static const uint8_t ucExpectedStackBytes[] =
     {
@@ -126,7 +126,7 @@ size_t xTaskReturnAddress = ( size_t ) portTASK_RETURN_ADDRESS;
     }; \
 
     #define portCHECK_ISR_STACK()    configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
-#else  /* if defined( configISR_STACK_SIZE_WORDS ) && ( configCHECK_FOR_STACK_OVERFLOW > 2 ) */
+#else /* if defined( configISR_STACK_SIZE_WORDS ) && ( configCHECK_FOR_STACK_OVERFLOW > 2 ) */
     /* Define the function away. */
     #define portCHECK_ISR_STACK()
 #endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
@@ -167,7 +167,7 @@ static void prvTaskExitError( void )
         volatile uint32_t * const pulTimeLow = ( uint32_t * ) ( configMTIME_BASE_ADDRESS );
         volatile uint32_t ulHartId;
 
-        __asm volatile ( "csrr %0, 0xf14" : "=r" ( ulHartId ) ); /* 0xf14 is hartid. */
+        __asm volatile ( "csrr %0, 0xf14" : "=r" ( ulHartId ) ); /* 0xf14 is HART ID. */
 
         pullMachineTimerCompareRegister = ( volatile uint64_t * ) ( ullMachineTimerCompareRegisterBase + ( ulHartId * sizeof( uint64_t ) ) );
 
diff --git a/portable/IAR/RISC-V/portContext.h b/portable/IAR/RISC-V/portContext.h
index b8f895849..35bca7fe5 100644
--- a/portable/IAR/RISC-V/portContext.h
+++ b/portable/IAR/RISC-V/portContext.h
@@ -30,13 +30,13 @@
 #define PORTCONTEXT_H
 
 #if __riscv_xlen == 64
-    #define portWORD_SIZE 8
-    #define store_x sd
-    #define load_x ld
+    #define portWORD_SIZE    8
+    #define store_x          sd
+    #define load_x           ld
 #elif __riscv_xlen == 32
-    #define store_x sw
-    #define load_x lw
-    #define portWORD_SIZE 4
+    #define store_x          sw
+    #define load_x           lw
+    #define portWORD_SIZE    4
 #else
     #error Assembler did not define __riscv_xlen
 #endif
@@ -49,36 +49,36 @@
  * specific version of freertos_risc_v_chip_specific_extensions.h.  See the
  * notes at the top of portASM.S file. */
 #ifdef __riscv_32e
-    #define portCONTEXT_SIZE ( 15 * portWORD_SIZE )
-    #define portCRITICAL_NESTING_OFFSET 13
-    #define portMSTATUS_OFFSET  14
+    #define portCONTEXT_SIZE               ( 15 * portWORD_SIZE )
+    #define portCRITICAL_NESTING_OFFSET    13
+    #define portMSTATUS_OFFSET             14
 #else
-    #define portCONTEXT_SIZE ( 31 * portWORD_SIZE )
-    #define portCRITICAL_NESTING_OFFSET 29
-    #define portMSTATUS_OFFSET  30
+    #define portCONTEXT_SIZE               ( 31 * portWORD_SIZE )
+    #define portCRITICAL_NESTING_OFFSET    29
+    #define portMSTATUS_OFFSET             30
 #endif
 
-  EXTERN pxCurrentTCB
-  EXTERN xISRStackTop
-  EXTERN xCriticalNesting
-  EXTERN pxCriticalNesting
+EXTERN pxCurrentTCB
+EXTERN xISRStackTop
+EXTERN xCriticalNesting
+EXTERN pxCriticalNesting
 
 /*-----------------------------------------------------------*/
 
 portcontextSAVE_CONTEXT_INTERNAL MACRO
-    addi sp, sp, -portCONTEXT_SIZE
-    store_x x1, 1 * portWORD_SIZE( sp )
-    store_x x5, 2 * portWORD_SIZE( sp )
-    store_x x6, 3 * portWORD_SIZE( sp )
-    store_x x7, 4 * portWORD_SIZE( sp )
-    store_x x8, 5 * portWORD_SIZE( sp )
-    store_x x9, 6 * portWORD_SIZE( sp )
-    store_x x10, 7 * portWORD_SIZE( sp )
-    store_x x11, 8 * portWORD_SIZE( sp )
-    store_x x12, 9 * portWORD_SIZE( sp )
-    store_x x13, 10 * portWORD_SIZE( sp )
-    store_x x14, 11 * portWORD_SIZE( sp )
-    store_x x15, 12 * portWORD_SIZE( sp )
+addi sp, sp, -portCONTEXT_SIZE
+store_x x1, 1 * portWORD_SIZE( sp )
+store_x x5, 2 * portWORD_SIZE( sp )
+store_x x6, 3 * portWORD_SIZE( sp )
+store_x x7, 4 * portWORD_SIZE( sp )
+store_x x8, 5 * portWORD_SIZE( sp )
+store_x x9, 6 * portWORD_SIZE( sp )
+store_x x10, 7 * portWORD_SIZE( sp )
+store_x x11, 8 * portWORD_SIZE( sp )
+store_x x12, 9 * portWORD_SIZE( sp )
+store_x x13, 10 * portWORD_SIZE( sp )
+store_x x14, 11 * portWORD_SIZE( sp )
+store_x x15, 12 * portWORD_SIZE( sp )
 #ifndef __riscv_32e
     store_x x16, 13 * portWORD_SIZE( sp )
     store_x x17, 14 * portWORD_SIZE( sp )
@@ -96,94 +96,94 @@ portcontextSAVE_CONTEXT_INTERNAL MACRO
     store_x x29, 26 * portWORD_SIZE( sp )
     store_x x30, 27 * portWORD_SIZE( sp )
     store_x x31, 28 * portWORD_SIZE( sp )
-#endif
+#endif /* ifndef __riscv_32e */
 
-    load_x  t0, xCriticalNesting         /* Load the value of xCriticalNesting into t0. */
-    store_x t0, portCRITICAL_NESTING_OFFSET * portWORD_SIZE( sp ) /* Store the critical nesting value to the stack. */
+load_x t0, xCriticalNesting                                   /* Load the value of xCriticalNesting into t0. */
+store_x t0, portCRITICAL_NESTING_OFFSET * portWORD_SIZE( sp ) /* Store the critical nesting value to the stack. */
 
-    csrr t0, mstatus                     /* Required for MPIE bit. */
-    store_x t0, portMSTATUS_OFFSET * portWORD_SIZE( sp )
+csrr t0, mstatus                                              /* Required for MPIE bit. */
+store_x t0, portMSTATUS_OFFSET * portWORD_SIZE( sp )
 
-    portasmSAVE_ADDITIONAL_REGISTERS     /* Defined in freertos_risc_v_chip_specific_extensions.h to save any registers unique to the RISC-V implementation. */
+portasmSAVE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to save any registers unique to the RISC-V implementation. */
 
-    load_x  t0, pxCurrentTCB             /* Load pxCurrentTCB. */
-    store_x  sp, 0( t0 )                 /* Write sp to first TCB member. */
+load_x t0, pxCurrentTCB          /* Load pxCurrentTCB. */
+store_x sp, 0 ( t0 )             /* Write sp to first TCB member. */
 
-    ENDM
+ENDM
 /*-----------------------------------------------------------*/
 
 portcontextSAVE_EXCEPTION_CONTEXT MACRO
-    portcontextSAVE_CONTEXT_INTERNAL
-    csrr a0, mcause
-    csrr a1, mepc
-    addi a1, a1, 4                      /* Synchronous so update exception return address to the instruction after the instruction that generated the exception. */
-    store_x a1, 0( sp )                 /* Save updated exception return address. */
-    load_x sp, xISRStackTop             /* Switch to ISR stack. */
-    ENDM
+portcontextSAVE_CONTEXT_INTERNAL
+csrr a0, mcause
+csrr a1, mepc
+addi a1, a1, 4          /* Synchronous so update exception return address to the instruction after the instruction that generated the exception. */
+store_x a1, 0 ( sp )    /* Save updated exception return address. */
+load_x sp, xISRStackTop /* Switch to ISR stack. */
+ENDM
 /*-----------------------------------------------------------*/
 
 portcontextSAVE_INTERRUPT_CONTEXT MACRO
-    portcontextSAVE_CONTEXT_INTERNAL
-    csrr a0, mcause
-    csrr a1, mepc
-    store_x a1, 0( sp )                 /* Asynchronous interrupt so save unmodified exception return address. */
-    load_x sp, xISRStackTop             /* Switch to ISR stack. */
-    ENDM
+portcontextSAVE_CONTEXT_INTERNAL
+csrr a0, mcause
+csrr a1, mepc
+store_x a1, 0 ( sp )    /* Asynchronous interrupt so save unmodified exception return address. */
+load_x sp, xISRStackTop /* Switch to ISR stack. */
+ENDM
 /*-----------------------------------------------------------*/
 
 portcontextRESTORE_CONTEXT MACRO
-    load_x  t1, pxCurrentTCB                /* Load pxCurrentTCB. */
-    load_x  sp, 0( t1 )                     /* Read sp from first TCB member. */
+load_x t1, pxCurrentTCB /* Load pxCurrentTCB. */
+load_x sp, 0 ( t1 )     /* Read sp from first TCB member. */
 
-    /* Load mepc with the address of the instruction in the task to run next. */
-    load_x t0, 0( sp )
-    csrw mepc, t0
+/* Load mepc with the address of the instruction in the task to run next. */
+load_x t0, 0 ( sp )
+csrw mepc, t0
 
-    /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
-    portasmRESTORE_ADDITIONAL_REGISTERS
+/* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
+portasmRESTORE_ADDITIONAL_REGISTERS
 
-    /* Load mstatus with the interrupt enable bits used by the task. */
-    load_x  t0, portMSTATUS_OFFSET * portWORD_SIZE( sp )
-    csrw mstatus, t0                        /* Required for MPIE bit. */
+/* Load mstatus with the interrupt enable bits used by the task. */
+load_x t0, portMSTATUS_OFFSET * portWORD_SIZE( sp )
+csrw mstatus, t0                                             /* Required for MPIE bit. */
 
-    load_x  t0, portCRITICAL_NESTING_OFFSET * portWORD_SIZE( sp )    /* Obtain xCriticalNesting value for this task from task's stack. */
-    load_x  t1, pxCriticalNesting           /* Load the address of xCriticalNesting into t1. */
-    store_x t0, 0( t1 )                     /* Restore the critical nesting value for this task. */
+load_x t0, portCRITICAL_NESTING_OFFSET * portWORD_SIZE( sp ) /* Obtain xCriticalNesting value for this task from task's stack. */
+load_x t1, pxCriticalNesting                                 /* Load the address of xCriticalNesting into t1. */
+store_x t0, 0 ( t1 )                                         /* Restore the critical nesting value for this task. */
 
-    load_x  x1, 1 * portWORD_SIZE( sp )
-    load_x  x5, 2 * portWORD_SIZE( sp )
-    load_x  x6, 3 * portWORD_SIZE( sp )
-    load_x  x7, 4 * portWORD_SIZE( sp )
-    load_x  x8, 5 * portWORD_SIZE( sp )
-    load_x  x9, 6 * portWORD_SIZE( sp )
-    load_x  x10, 7 * portWORD_SIZE( sp )
-    load_x  x11, 8 * portWORD_SIZE( sp )
-    load_x  x12, 9 * portWORD_SIZE( sp )
-    load_x  x13, 10 * portWORD_SIZE( sp )
-    load_x  x14, 11 * portWORD_SIZE( sp )
-    load_x  x15, 12 * portWORD_SIZE( sp )
+load_x x1, 1 * portWORD_SIZE( sp )
+load_x x5, 2 * portWORD_SIZE( sp )
+load_x x6, 3 * portWORD_SIZE( sp )
+load_x x7, 4 * portWORD_SIZE( sp )
+load_x x8, 5 * portWORD_SIZE( sp )
+load_x x9, 6 * portWORD_SIZE( sp )
+load_x x10, 7 * portWORD_SIZE( sp )
+load_x x11, 8 * portWORD_SIZE( sp )
+load_x x12, 9 * portWORD_SIZE( sp )
+load_x x13, 10 * portWORD_SIZE( sp )
+load_x x14, 11 * portWORD_SIZE( sp )
+load_x x15, 12 * portWORD_SIZE( sp )
 #ifndef __riscv_32e
-    load_x  x16, 13 * portWORD_SIZE( sp )
-    load_x  x17, 14 * portWORD_SIZE( sp )
-    load_x  x18, 15 * portWORD_SIZE( sp )
-    load_x  x19, 16 * portWORD_SIZE( sp )
-    load_x  x20, 17 * portWORD_SIZE( sp )
-    load_x  x21, 18 * portWORD_SIZE( sp )
-    load_x  x22, 19 * portWORD_SIZE( sp )
-    load_x  x23, 20 * portWORD_SIZE( sp )
-    load_x  x24, 21 * portWORD_SIZE( sp )
-    load_x  x25, 22 * portWORD_SIZE( sp )
-    load_x  x26, 23 * portWORD_SIZE( sp )
-    load_x  x27, 24 * portWORD_SIZE( sp )
-    load_x  x28, 25 * portWORD_SIZE( sp )
-    load_x  x29, 26 * portWORD_SIZE( sp )
-    load_x  x30, 27 * portWORD_SIZE( sp )
-    load_x  x31, 28 * portWORD_SIZE( sp )
-#endif
-    addi sp, sp, portCONTEXT_SIZE
+    load_x x16, 13 * portWORD_SIZE( sp )
+    load_x x17, 14 * portWORD_SIZE( sp )
+    load_x x18, 15 * portWORD_SIZE( sp )
+    load_x x19, 16 * portWORD_SIZE( sp )
+    load_x x20, 17 * portWORD_SIZE( sp )
+    load_x x21, 18 * portWORD_SIZE( sp )
+    load_x x22, 19 * portWORD_SIZE( sp )
+    load_x x23, 20 * portWORD_SIZE( sp )
+    load_x x24, 21 * portWORD_SIZE( sp )
+    load_x x25, 22 * portWORD_SIZE( sp )
+    load_x x26, 23 * portWORD_SIZE( sp )
+    load_x x27, 24 * portWORD_SIZE( sp )
+    load_x x28, 25 * portWORD_SIZE( sp )
+    load_x x29, 26 * portWORD_SIZE( sp )
+    load_x x30, 27 * portWORD_SIZE( sp )
+    load_x x31, 28 * portWORD_SIZE( sp )
+#endif /* ifndef __riscv_32e */
+addi sp, sp, portCONTEXT_SIZE
 
-    mret
-    ENDM
+mret
+ENDM
 /*-----------------------------------------------------------*/
 
 #endif /* PORTCONTEXT_H */
diff --git a/portable/IAR/RISC-V/portmacro.h b/portable/IAR/RISC-V/portmacro.h
index 5dddb454c..f9431a6de 100644
--- a/portable/IAR/RISC-V/portmacro.h
+++ b/portable/IAR/RISC-V/portmacro.h
@@ -50,85 +50,85 @@
 
 /* Type definitions. */
 #if __riscv_xlen == 64
-    #define portSTACK_TYPE          uint64_t
-    #define portBASE_TYPE           int64_t
-    #define portUBASE_TYPE          uint64_t
-    #define portMAX_DELAY           ( TickType_t ) 0xffffffffffffffffUL
-    #define portPOINTER_SIZE_TYPE   uint64_t
+    #define portSTACK_TYPE           uint64_t
+    #define portBASE_TYPE            int64_t
+    #define portUBASE_TYPE           uint64_t
+    #define portMAX_DELAY            ( TickType_t ) 0xffffffffffffffffUL
+    #define portPOINTER_SIZE_TYPE    uint64_t
 #elif __riscv_xlen == 32
-    #define portSTACK_TYPE          uint32_t
-    #define portBASE_TYPE           int32_t
-    #define portUBASE_TYPE          uint32_t
-    #define portMAX_DELAY           ( TickType_t ) 0xffffffffUL
-#else
-    #error Assembler did not define __riscv_xlen
-#endif
+    #define portSTACK_TYPE           uint32_t
+    #define portBASE_TYPE            int32_t
+    #define portUBASE_TYPE           uint32_t
+    #define portMAX_DELAY            ( TickType_t ) 0xffffffffUL
+#else /* if __riscv_xlen == 64 */
+    #error "Assembler did not define __riscv_xlen"
+#endif /* if __riscv_xlen == 64 */
 
-typedef portSTACK_TYPE StackType_t;
-typedef portBASE_TYPE BaseType_t;
-typedef portUBASE_TYPE UBaseType_t;
-typedef portUBASE_TYPE TickType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef portBASE_TYPE    BaseType_t;
+typedef portUBASE_TYPE   UBaseType_t;
+typedef portUBASE_TYPE   TickType_t;
 
 /* Legacy type definitions. */
-#define portCHAR            char
-#define portFLOAT           float
-#define portDOUBLE          double
-#define portLONG            long
-#define portSHORT           short
+#define portCHAR                   char
+#define portFLOAT                  float
+#define portDOUBLE                 double
+#define portLONG                   long
+#define portSHORT                  short
 
 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
  * not need to be guarded with a critical section. */
-#define portTICK_TYPE_IS_ATOMIC 1
+#define portTICK_TYPE_IS_ATOMIC    1
 /*-----------------------------------------------------------*/
 
 /* Architecture specifics. */
-#define portSTACK_GROWTH            ( -1 )
-#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portSTACK_GROWTH          ( -1 )
+#define portTICK_PERIOD_MS        ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
 #ifdef __riscv_32e
-    #define portBYTE_ALIGNMENT          8   /* RV32E uses RISC-V EABI with reduced stack alignment requirements. */
+    #define portBYTE_ALIGNMENT    8         /* RV32E uses RISC-V EABI with reduced stack alignment requirements. */
 #else
-    #define portBYTE_ALIGNMENT          16
+    #define portBYTE_ALIGNMENT    16
 #endif
 /*-----------------------------------------------------------*/
 
 /* Scheduler utilities. */
 extern void vTaskSwitchContext( void );
-#define portYIELD() __asm volatile( "ecall" );
-#define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) vTaskSwitchContext(); } while( 0 )
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portYIELD()                                 __asm volatile ( "ecall" );
+#define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired ) vTaskSwitchContext( ); } while( 0 )
+#define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
 /* Critical section management. */
-#define portCRITICAL_NESTING_IN_TCB                             0
+#define portCRITICAL_NESTING_IN_TCB    0
 
-#define portSET_INTERRUPT_MASK_FROM_ISR()                       0
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue
+#define portSET_INTERRUPT_MASK_FROM_ISR()                          0
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue )    ( void ) uxSavedStatusValue
 
-#define portDISABLE_INTERRUPTS()	__disable_interrupt()
-#define portENABLE_INTERRUPTS()		__enable_interrupt()
+#define portDISABLE_INTERRUPTS()                                   __disable_interrupt()
+#define portENABLE_INTERRUPTS()                                    __enable_interrupt()
 
 extern size_t xCriticalNesting;
-#define portENTER_CRITICAL()            \
-{                                       \
-    portDISABLE_INTERRUPTS();           \
-    xCriticalNesting++;                 \
-}
+#define portENTER_CRITICAL()      \
+    {                             \
+        portDISABLE_INTERRUPTS(); \
+        xCriticalNesting++;       \
+    }
 
-#define portEXIT_CRITICAL()             \
-{                                       \
-    xCriticalNesting--;                 \
-    if( xCriticalNesting == 0 )         \
-    {                                   \
-        portENABLE_INTERRUPTS();        \
-    }                                   \
-}
+#define portEXIT_CRITICAL()          \
+    {                                \
+        xCriticalNesting--;          \
+        if( xCriticalNesting == 0 )  \
+        {                            \
+            portENABLE_INTERRUPTS(); \
+        }                            \
+    }
 
 /*-----------------------------------------------------------*/
 
 /* Architecture specific optimisations. */
-#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
 
-	#error configUSE_PORT_OPTIMISED_TASK_SELECTION cannot yet be used in the IAR RISC-V port, the CLZ instruction needs to be emulated.
+    #error "configUSE_PORT_OPTIMISED_TASK_SELECTION cannot yet be used in the IAR RISC-V port, the CLZ instruction needs to be emulated."
 
 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 
@@ -138,19 +138,19 @@ extern size_t xCriticalNesting;
 /* Task function macros as described on the FreeRTOS.org WEB site. These are
  * not necessary for to use this port.  They are defined so the common demo
  * files (which build with all the ports) will build. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
 /*-----------------------------------------------------------*/
 
-#define portNOP()    __asm volatile( " nop " )
-#define portINLINE   __inline
+#define portNOP()    __asm volatile ( " nop " )
+#define portINLINE              __inline
 
 #ifndef portFORCE_INLINE
-    #define portFORCE_INLINE inline __attribute__(( always_inline))
+    #define portFORCE_INLINE    inline __attribute__( ( always_inline ) )
 #endif
 
-#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+#define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
 /*-----------------------------------------------------------*/
 
 /* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
@@ -163,20 +163,22 @@ extern size_t xCriticalNesting;
  * backward compatibility derive the newer definitions from the old if the old
  * definition is found. */
 #if defined( configCLINT_BASE_ADDRESS ) && !defined( configMTIME_BASE_ADDRESS ) && ( configCLINT_BASE_ADDRESS == 0 )
-    /* Legacy case where configCLINT_BASE_ADDRESS was defined as 0 to indicate
-     * there was no CLINT.  Equivalent now is to set the MTIME and MTIMECMP
-     * addresses to 0. */
-    #define configMTIME_BASE_ADDRESS     ( 0 )
-    #define configMTIMECMP_BASE_ADDRESS ( 0 )
+
+/* Legacy case where configCLINT_BASE_ADDRESS was defined as 0 to indicate
+ * there was no CLINT.  Equivalent now is to set the MTIME and MTIMECMP
+ * addresses to 0. */
+    #define configMTIME_BASE_ADDRESS       ( 0 )
+    #define configMTIMECMP_BASE_ADDRESS    ( 0 )
 #elif defined( configCLINT_BASE_ADDRESS ) && !defined( configMTIME_BASE_ADDRESS )
-    /* Legacy case where configCLINT_BASE_ADDRESS was set to the base address of
-     * the CLINT.  Equivalent now is to derive the MTIME and MTIMECMP addresses
-     * from the CLINT address. */
-    #define configMTIME_BASE_ADDRESS     ( ( configCLINT_BASE_ADDRESS ) + 0xBFF8UL )
-    #define configMTIMECMP_BASE_ADDRESS ( ( configCLINT_BASE_ADDRESS ) + 0x4000UL )
+
+/* Legacy case where configCLINT_BASE_ADDRESS was set to the base address of
+ * the CLINT.  Equivalent now is to derive the MTIME and MTIMECMP addresses
+ * from the CLINT address. */
+    #define configMTIME_BASE_ADDRESS       ( ( configCLINT_BASE_ADDRESS ) + 0xBFF8UL )
+    #define configMTIMECMP_BASE_ADDRESS    ( ( configCLINT_BASE_ADDRESS ) + 0x4000UL )
 #elif !defined( configMTIME_BASE_ADDRESS ) || !defined( configMTIMECMP_BASE_ADDRESS )
-    #error configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h.  Set them to zero if there is no MTIME (machine time) clock.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
-#endif
+    #error "configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h.  Set them to zero if there is no MTIME (machine time) clock.  See www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html"
+#endif /* if defined( configCLINT_BASE_ADDRESS ) && !defined( configMTIME_BASE_ADDRESS ) && ( configCLINT_BASE_ADDRESS == 0 ) */
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/IAR/RL78/port.c b/portable/IAR/RL78/port.c
index 2f9a08cb8..55baa43e7 100644
--- a/portable/IAR/RL78/port.c
+++ b/portable/IAR/RL78/port.c
@@ -31,8 +31,8 @@
 #include "task.h"
 
 /* The critical nesting value is initialised to a non zero value to ensure
-interrupts don't accidentally become enabled before the scheduler is started. */
-#define portINITIAL_CRITICAL_NESTING  ( ( uint16_t ) 10 )
+ * interrupts don't accidentally become enabled before the scheduler is started. */
+#define portINITIAL_CRITICAL_NESTING    ( ( uint16_t ) 10 )
 
 /* Initial PSW value allocated to a newly created task.
  *   1100011000000000
@@ -45,21 +45,21 @@ interrupts don't accidentally become enabled before the scheduler is started. */
  *   |--------------------- Zero Flag set
  *   ---------------------- Global Interrupt Flag set (enabled)
  */
-#define portPSW    ( 0xc6UL )
+#define portPSW                         ( 0xc6UL )
 
 /* The address of the pxCurrentTCB variable, but don't know or need to know its
-type. */
+ * type. */
 typedef void TCB_t;
 extern volatile TCB_t * volatile pxCurrentTCB;
 
 /* Each task maintains a count of the critical section nesting depth.  Each time
-a critical section is entered the count is incremented.  Each time a critical
-section is exited the count is decremented - with interrupts only being
-re-enabled if the count is zero.
-
-usCriticalNesting will get set to zero when the scheduler starts, but must
-not be initialised to zero as that could cause problems during the startup
-sequence. */
+ * a critical section is entered the count is incremented.  Each time a critical
+ * section is exited the count is decremented - with interrupts only being
+ * re-enabled if the count is zero.
+ *
+ * usCriticalNesting will get set to zero when the scheduler starts, but must
+ * not be initialised to zero as that could cause problems during the startup
+ * sequence. */
 volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;
 
 /*-----------------------------------------------------------*/
@@ -88,35 +88,37 @@ static void prvTaskExitError( void );
  *
  * See the header file portable.h.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
-uint32_t *pulLocal;
+    uint32_t * pulLocal;
 
     /* With large code and large data sizeof( StackType_t ) == 2, and
-    sizeof( StackType_t * ) == 4.  With small code and small data
-    sizeof( StackType_t ) == 2 and sizeof( StackType_t * ) == 2. */
+    * sizeof( StackType_t * ) == 4.  With small code and small data
+    * sizeof( StackType_t ) == 2 and sizeof( StackType_t * ) == 2. */
 
     #if __DATA_MODEL__ == __DATA_MODEL_FAR__
     {
         /* Far pointer parameters are passed using the A:DE registers (24-bit).
-        Although they are stored in memory as a 32-bit value.  Hence decrement
-        the stack pointer, so 2 bytes are left for the contents of A, before
-        storing the pvParameters value. */
+         * Although they are stored in memory as a 32-bit value.  Hence decrement
+         * the stack pointer, so 2 bytes are left for the contents of A, before
+         * storing the pvParameters value. */
         pxTopOfStack--;
-        pulLocal =  ( uint32_t * ) pxTopOfStack;
+        pulLocal = ( uint32_t * ) pxTopOfStack;
         *pulLocal = ( uint32_t ) pvParameters;
         pxTopOfStack--;
 
         /* The return address is a 32-bit value. So decrement the stack pointer
-        in order to make extra room needed to store the correct value.  See the
-        comments above the prvTaskExitError() prototype at the top of this file. */
+         * in order to make extra room needed to store the correct value.  See the
+         * comments above the prvTaskExitError() prototype at the top of this file. */
         pxTopOfStack--;
         pulLocal = ( uint32_t * ) pxTopOfStack;
         *pulLocal = ( uint32_t ) prvTaskExitError;
         pxTopOfStack--;
 
         /* The task function start address combined with the PSW is also stored
-        as a 32-bit value. So leave a space for the second two bytes. */
+         * as a 32-bit value. So leave a space for the second two bytes. */
         pxTopOfStack--;
         pulLocal = ( uint32_t * ) pxTopOfStack;
         *pulLocal = ( ( ( uint32_t ) pxCode ) | ( portPSW << 24UL ) );
@@ -126,18 +128,18 @@ uint32_t *pulLocal;
         *pxTopOfStack = ( StackType_t ) 0x1111;
         pxTopOfStack--;
     }
-    #else
+    #else /* if __DATA_MODEL__ == __DATA_MODEL_FAR__ */
     {
         /* The return address, leaving space for the first two bytes of the
-        32-bit value.  See the comments above the prvTaskExitError() prototype
-        at the top of this file. */
+         * 32-bit value.  See the comments above the prvTaskExitError() prototype
+         * at the top of this file. */
         pxTopOfStack--;
         pulLocal = ( uint32_t * ) pxTopOfStack;
         *pulLocal = ( uint32_t ) prvTaskExitError;
         pxTopOfStack--;
 
         /* Task function.  Again as it is written as a 32-bit value a space is
-        left on the stack for the second two bytes. */
+         * left on the stack for the second two bytes. */
         pxTopOfStack--;
 
         /* Task function start address combined with the PSW. */
@@ -149,7 +151,7 @@ uint32_t *pulLocal;
         *pxTopOfStack = ( StackType_t ) pvParameters;
         pxTopOfStack--;
     }
-    #endif
+    #endif /* if __DATA_MODEL__ == __DATA_MODEL_FAR__ */
 
     /* An initial value for the HL register. */
     *pxTopOfStack = ( StackType_t ) 0x2222;
@@ -166,11 +168,11 @@ uint32_t *pulLocal;
     pxTopOfStack--;
 
     /* Finally the critical section nesting count is set to zero when the task
-    first starts. */
+     * first starts. */
     *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;
 
     /* Return a pointer to the top of the stack that has been generated so
-    it can be stored in the task control block for the task. */
+     * it can be stored in the task control block for the task. */
     return pxTopOfStack;
 }
 /*-----------------------------------------------------------*/
@@ -178,21 +180,24 @@ uint32_t *pulLocal;
 static void prvTaskExitError( void )
 {
     /* A function that implements a task must not exit or attempt to return to
-    its caller as there is nothing to return to.  If a task wants to exit it
-    should instead call vTaskDelete( NULL ).
-
-    Artificially force an assert() to be triggered if configASSERT() is
-    defined, then stop here so application writers can catch the error. */
+     * its caller as there is nothing to return to.  If a task wants to exit it
+     * should instead call vTaskDelete( NULL ).
+     *
+     * Artificially force an assert() to be triggered if configASSERT() is
+     * defined, then stop here so application writers can catch the error. */
     configASSERT( usCriticalNesting == ~0U );
     portDISABLE_INTERRUPTS();
-    for( ;; );
+
+    for( ; ; )
+    {
+    }
 }
 /*-----------------------------------------------------------*/
 
 BaseType_t xPortStartScheduler( void )
 {
     /* Setup the hardware to generate the tick. Interrupts are disabled when
-     this function is called. */
+     * this function is called. */
     vApplicationSetupTimerInterrupt();
 
     /* Restore the context of the first task that is going to run. */
diff --git a/portable/IAR/RL78/portmacro.h b/portable/IAR/RL78/portmacro.h
index 1cfe85fa6..4bf61e88f 100644
--- a/portable/IAR/RL78/portmacro.h
+++ b/portable/IAR/RL78/portmacro.h
@@ -47,101 +47,101 @@
  *-----------------------------------------------------------
  */
 
-#if __DATA_MODEL__ == __DATA_MODEL_FAR__ && __CODE_MODEL__ == __CODE_MODEL_NEAR__
-    #warning This port has not been tested with your selected memory model combination. If a far data model is required it is recommended to also use a far code model.
-#endif
+    #if __DATA_MODEL__ == __DATA_MODEL_FAR__ && __CODE_MODEL__ == __CODE_MODEL_NEAR__
+        #warning This port has not been tested with your selected memory model combination. If a far data model is required it is recommended to also use a far code model.
+    #endif
 
-#if __DATA_MODEL__ == __DATA_MODEL_NEAR__ && __CODE_MODEL__ == __CODE_MODEL_FAR__
-    #warning This port has not been tested with your selected memory model combination. If a far code model is required it is recommended to also use a far data model.
-#endif
+    #if __DATA_MODEL__ == __DATA_MODEL_NEAR__ && __CODE_MODEL__ == __CODE_MODEL_FAR__
+        #warning This port has not been tested with your selected memory model combination. If a far code model is required it is recommended to also use a far data model.
+    #endif
 
 /* Type definitions. */
 
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint16_t
-#define portBASE_TYPE   short
+    #define portCHAR          char
+    #define portFLOAT         float
+    #define portDOUBLE        double
+    #define portLONG          long
+    #define portSHORT         short
+    #define portSTACK_TYPE    uint16_t
+    #define portBASE_TYPE     short
 
-typedef portSTACK_TYPE StackType_t;
-typedef short BaseType_t;
-typedef unsigned short UBaseType_t;
+    typedef portSTACK_TYPE   StackType_t;
+    typedef short            BaseType_t;
+    typedef unsigned short   UBaseType_t;
 
 
-#if __DATA_MODEL__ == __DATA_MODEL_FAR__
-    #define portPOINTER_SIZE_TYPE uint32_t
-#else
-    #define portPOINTER_SIZE_TYPE uint16_t
-#endif
+    #if __DATA_MODEL__ == __DATA_MODEL_FAR__
+        #define portPOINTER_SIZE_TYPE    uint32_t
+    #else
+        #define portPOINTER_SIZE_TYPE    uint16_t
+    #endif
 
 
-#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef unsigned int TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
-#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY ( TickType_t )    ( 0xFFFFFFFFUL )
-#else
-    #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
-#endif
+    #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+        typedef unsigned int   TickType_t;
+        #define portMAX_DELAY    ( TickType_t ) 0xffff
+    #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+        typedef uint32_t       TickType_t;
+        #define portMAX_DELAY    ( TickType_t ) ( 0xFFFFFFFFUL )
+    #else
+        #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+    #endif
 /*-----------------------------------------------------------*/
 
 /* Interrupt control macros. */
-#define portDISABLE_INTERRUPTS()    __asm ( "DI" )
-#define portENABLE_INTERRUPTS()     __asm ( "EI" )
+    #define portDISABLE_INTERRUPTS()    __asm( "DI" )
+    #define portENABLE_INTERRUPTS()     __asm( "EI" )
 /*-----------------------------------------------------------*/
 
 /* Critical section control macros. */
-#define portNO_CRITICAL_SECTION_NESTING        ( ( uint16_t ) 0 )
+    #define portNO_CRITICAL_SECTION_NESTING    ( ( uint16_t ) 0 )
 
-#define portENTER_CRITICAL()                                                   \
-{                                                                              \
-extern volatile uint16_t usCriticalNesting;                                    \
-                                                                               \
-    portDISABLE_INTERRUPTS();                                                  \
-                                                                               \
-    /* Now interrupts are disabled ulCriticalNesting can be accessed */        \
-    /* directly.  Increment ulCriticalNesting to keep a count of how many */   \
-    /* times portENTER_CRITICAL() has been called. */                          \
-    usCriticalNesting++;                                                       \
-}
+    #define portENTER_CRITICAL()                                                  \
+    {                                                                             \
+        extern volatile uint16_t usCriticalNesting;                               \
+                                                                                  \
+        portDISABLE_INTERRUPTS();                                                 \
+                                                                                  \
+        /* Now that interrupts are disabled, ulCriticalNesting can be accessed */ \
+        /* directly.  Increment ulCriticalNesting to keep a count of how many */  \
+        /* times portENTER_CRITICAL() has been called. */                         \
+        usCriticalNesting++;                                                      \
+    }
 
-#define portEXIT_CRITICAL()                                                    \
-{                                                                              \
-extern volatile uint16_t usCriticalNesting;                                    \
-                                                                               \
-    if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING )                  \
-    {                                                                          \
-        /* Decrement the nesting count when leaving a critical section. */     \
-        usCriticalNesting--;                                                   \
-                                                                               \
-        /* If the nesting level has reached zero then interrupts should be */  \
-        /* re-enabled. */                                                      \
-        if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING )             \
-        {                                                                      \
-            portENABLE_INTERRUPTS();                                           \
-        }                                                                      \
-    }                                                                          \
-}
+    #define portEXIT_CRITICAL()                                                   \
+    {                                                                             \
+        extern volatile uint16_t usCriticalNesting;                               \
+                                                                                  \
+        if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING )                 \
+        {                                                                         \
+            /* Decrement the nesting count when leaving a critical section. */    \
+            usCriticalNesting--;                                                  \
+                                                                                  \
+            /* If the nesting level has reached zero then interrupts should be */ \
+            /* re-enabled. */                                                     \
+            if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING )            \
+            {                                                                     \
+                portENABLE_INTERRUPTS();                                          \
+            }                                                                     \
+        }                                                                         \
+    }
 /*-----------------------------------------------------------*/
 
 /* Task utilities. */
-#define portNOP()      __asm( "NOP" )
-#define portYIELD()    __asm( "BRK" )
-#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) do { if( xHigherPriorityTaskWoken ) vTaskSwitchContext(); } while( 0 )
+    #define portNOP()                                         __asm( "NOP" )
+    #define portYIELD()                                       __asm( "BRK" )
+    #define portYIELD_FROM_ISR( xHigherPriorityTaskWoken )    do { if( xHigherPriorityTaskWoken ) vTaskSwitchContext( ); } while( 0 )
 /*-----------------------------------------------------------*/
 
-/* Hardwware specifics. */
-#define portBYTE_ALIGNMENT   2
-#define portSTACK_GROWTH     ( -1 )
-#define portTICK_PERIOD_MS   ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+/* Hardware specifics. */
+    #define portBYTE_ALIGNMENT    2
+    #define portSTACK_GROWTH      ( -1 )
+    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
@@ -151,83 +151,83 @@ extern volatile uint16_t usCriticalNesting;                                    \
 
 #endif /* __IAR_SYSTEMS_ICC__ */
 
-;//-----------------------------------------------------------------------------
-;// The macros below are processed for asm sources which include portmacro.h.
-;//-----------------------------------------------------------------------------
+; /*----------------------------------------------------------------------------- */
+  /* The macros below are processed for asm sources which include portmacro.h. */
+  /*----------------------------------------------------------------------------- */
 #ifdef __IAR_SYSTEMS_ASM__
 
-;/* Functions and variables used by this file. */
-;//-----------------------------------------------------------------------------
+    ; /* Functions and variables used by this file. */
+      /*----------------------------------------------------------------------------- */
     EXTERN _pxCurrentTCB
     EXTERN _usCriticalNesting
 
-;/* Macro used to declutter calls, depends on the selected code model. */
-;//-----------------------------------------------------------------------------
-#if __CODE_MODEL__ == __CODE_MODEL_FAR__
-    #define RCALL(X)    CALL    F:X
-#else
-    #define RCALL(X)    CALL    X
-#endif
+    ; /* Macro used to declutter calls, depends on the selected code model. */
+      /*----------------------------------------------------------------------------- */
+    #if __CODE_MODEL__ == __CODE_MODEL_FAR__
+        #define RCALL( X )    CALL F: X
+    #else
+        #define RCALL( X )    CALL X
+    #endif
 
 
-;/*-----------------------------------------------------------------------------
-; * portSAVE_CONTEXT MACRO
-; * Saves the context of the general purpose registers, CS and ES (only in __far
-; * memory mode) registers the _usCriticalNesting value and the Stack Pointer
-; * of the active Task onto the task stack.
-; *---------------------------------------------------------------------------*/
-portSAVE_CONTEXT MACRO
-    PUSH      AX                       ; // Save AX Register to stack.
-    PUSH      HL
-#if  __CODE_MODEL__  == __CODE_MODEL_FAR__
-    MOV       A, CS                    ; // Save CS register.
-    XCH       A, X
-    MOV       A, ES                    ; // Save ES register.
-    PUSH      AX
-#else
-    MOV       A, CS                    ; // Save CS register.
-    PUSH      AX
-#endif
-    PUSH      DE                       ; // Save the remaining general purpose registers.
-    PUSH      BC
-    MOVW      AX, _usCriticalNesting   ; // Save the _usCriticalNesting value.
-    PUSH      AX
-    MOVW      AX, _pxCurrentTCB        ; // Save the Task stack pointer.
-    MOVW      HL, AX
-    MOVW      AX, SP
-    MOVW      [HL], AX
+    ;        /*-----------------------------------------------------------------------------
+              * ; * portSAVE_CONTEXT MACRO
+              * ; * Saves the context of the general purpose registers, CS and ES (only in __far
+              * ; * memory mode) registers the _usCriticalNesting value and the Stack Pointer
+              * ; * of the active Task onto the task stack.
+              * ; *---------------------------------------------------------------------------*/
+    portSAVE_CONTEXT MACRO
+    PUSH AX; /* Save AX Register to stack. */
+    PUSH HL
+    #if  __CODE_MODEL__ == __CODE_MODEL_FAR__
+        MOV A, CS; /* Save CS register. */
+        XCH A, X
+        MOV A, ES; /* Save ES register. */
+        PUSH AX
+    #else
+        MOV A, CS; /* Save CS register. */
+        PUSH AX
+    #endif
+    PUSH DE;                     /* Save the remaining general purpose registers. */
+    PUSH BC
+    MOVW AX, _usCriticalNesting; /* Save the _usCriticalNesting value. */
+    PUSH AX
+    MOVW AX, _pxCurrentTCB;      /* Save the Task stack pointer. */
+    MOVW HL, AX
+    MOVW AX, SP
+         MOVW[ HL ], AX
+         ENDM
+    ; /*----------------------------------------------------------------------------- */
+
+
+/*-----------------------------------------------------------------------------
+ * ; * portRESTORE_CONTEXT MACRO
+ * ; * Restores the task Stack Pointer then use this to restore _usCriticalNesting,
+ * ; * general purpose registers and the CS and ES (only in __far memory mode)
+ * ; * of the selected task from the task stack.
+ * ; *---------------------------------------------------------------------------*/
+    portRESTORE_CONTEXT MACRO
+    MOVW AX, _pxCurrentTCB; /* Restore the Task stack pointer. */
+    MOVW HL, AX
+    MOVW AX, [ HL ]
+    MOVW SP, AX
+    POP AX; /* Restore _usCriticalNesting value. */
+    MOVW _usCriticalNesting, AX
+    POP BC; /* Restore the necessary general purpose registers. */
+    POP DE
+    #if __CODE_MODEL__ == __CODE_MODEL_FAR__
+        POP AX;   /* Restore the ES register. */
+        MOV ES, A
+        XCH A, X; /* Restore the CS register. */
+        MOV CS, A
+    #else
+        POP AX
+        MOV CS, A; /* Restore CS register. */
+    #endif
+    POP HL;        /* Restore general purpose register HL. */
+    POP AX;        /* Restore AX. */
     ENDM
-;//-----------------------------------------------------------------------------
-
-
-;/*-----------------------------------------------------------------------------
-; * portRESTORE_CONTEXT MACRO
-; * Restores the task Stack Pointer then use this to restore _usCriticalNesting,
-; * general purpose registers and the CS and ES (only in __far memory mode)
-; * of the selected task from the task stack.
-; *---------------------------------------------------------------------------*/
-portRESTORE_CONTEXT MACRO
-    MOVW    AX, _pxCurrentTCB          ; // Restore the Task stack pointer.
-    MOVW    HL, AX
-    MOVW    AX, [HL]
-    MOVW    SP, AX
-    POP     AX                         ; // Restore _usCriticalNesting value.
-    MOVW    _usCriticalNesting, AX
-    POP     BC                         ; // Restore the necessary general purpose registers.
-    POP     DE
-#if __CODE_MODEL__  == __CODE_MODEL_FAR__
-    POP     AX                         ; // Restore the ES register.
-    MOV     ES, A
-    XCH     A, X                       ; // Restore the CS register.
-    MOV     CS, A
-#else
-    POP     AX
-    MOV     CS, A                      ; // Restore CS register.
-#endif
-    POP     HL                         ; // Restore general purpose register HL.
-    POP     AX                         ; // Restore AX.
-    ENDM
-;//-----------------------------------------------------------------------------
+    ;              /*----------------------------------------------------------------------------- */
 
 #endif /* __IAR_SYSTEMS_ASM__ */
 
diff --git a/portable/IAR/RX100/port.c b/portable/IAR/RX100/port.c
index db9bdceb4..27e5d4b75 100644
--- a/portable/IAR/RX100/port.c
+++ b/portable/IAR/RX100/port.c
@@ -27,8 +27,8 @@
  */
 
 /*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the SH2A port.
- *----------------------------------------------------------*/
+* Implementation of functions defined in portable.h for the SH2A port.
+*----------------------------------------------------------*/
 
 /* Standard C includes. */
 #include "limits.h"
@@ -46,29 +46,29 @@
 /*-----------------------------------------------------------*/
 
 /* Tasks should start with interrupts enabled and in Supervisor mode, therefore
-PSW is set with U and I set, and PM and IPL clear. */
-#define portINITIAL_PSW     ( ( StackType_t ) 0x00030000 )
+ * PSW is set with U and I set, and PM and IPL clear. */
+#define portINITIAL_PSW    ( ( StackType_t ) 0x00030000 )
 
 /* The peripheral clock is divided by this value before being supplying the
-CMT. */
+ * CMT. */
 #if ( configUSE_TICKLESS_IDLE == 0 )
     /* If tickless idle is not used then the divisor can be fixed. */
-    #define portCLOCK_DIVISOR   8UL
+    #define portCLOCK_DIVISOR    8UL
 #elif ( configPERIPHERAL_CLOCK_HZ >= 12000000 )
-    #define portCLOCK_DIVISOR   512UL
+    #define portCLOCK_DIVISOR    512UL
 #elif ( configPERIPHERAL_CLOCK_HZ >= 6000000 )
-    #define portCLOCK_DIVISOR   128UL
+    #define portCLOCK_DIVISOR    128UL
 #elif ( configPERIPHERAL_CLOCK_HZ >= 1000000 )
-    #define portCLOCK_DIVISOR   32UL
+    #define portCLOCK_DIVISOR    32UL
 #else
-    #define portCLOCK_DIVISOR   8UL
+    #define portCLOCK_DIVISOR    8UL
 #endif
 
 
 /* Keys required to lock and unlock access to certain system registers
-respectively. */
-#define portUNLOCK_KEY      0xA50B
-#define portLOCK_KEY        0xA500
+ * respectively. */
+#define portUNLOCK_KEY    0xA50B
+#define portLOCK_KEY      0xA500
 
 /*-----------------------------------------------------------*/
 
@@ -92,9 +92,10 @@ __interrupt static void prvTickISR( void );
  */
 static void prvSetupTimerInterrupt( void );
 #ifndef configSETUP_TICK_INTERRUPT
-    /* The user has not provided their own tick interrupt configuration so use
-    the definition in this file (which uses the interval timer). */
-    #define configSETUP_TICK_INTERRUPT() prvSetupTimerInterrupt()
+
+/* The user has not provided their own tick interrupt configuration so use
+ * the definition in this file (which uses the interval timer). */
+    #define configSETUP_TICK_INTERRUPT()    prvSetupTimerInterrupt()
 #endif /* configSETUP_TICK_INTERRUPT */
 
 /*
@@ -108,7 +109,7 @@ static void prvSetupTimerInterrupt( void );
 
 /*-----------------------------------------------------------*/
 
-extern void *pxCurrentTCB;
+extern void * pxCurrentTCB;
 
 /*-----------------------------------------------------------*/
 
@@ -117,33 +118,35 @@ static const uint32_t ulMatchValueForOneTick = ( ( configPERIPHERAL_CLOCK_HZ / p
 
 #if configUSE_TICKLESS_IDLE == 1
 
-    /* Holds the maximum number of ticks that can be suppressed - which is
-    basically how far into the future an interrupt can be generated. Set
-    during initialisation.  This is the maximum possible value that the
-    compare match register can hold divided by ulMatchValueForOneTick. */
+/* Holds the maximum number of ticks that can be suppressed - which is
+ * basically how far into the future an interrupt can be generated. Set
+ * during initialisation.  This is the maximum possible value that the
+ * compare match register can hold divided by ulMatchValueForOneTick. */
     static const TickType_t xMaximumPossibleSuppressedTicks = USHRT_MAX / ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
 
-    /* Flag set from the tick interrupt to allow the sleep processing to know if
-    sleep mode was exited because of a tick interrupt, or an interrupt
-    generated by something else. */
+/* Flag set from the tick interrupt to allow the sleep processing to know if
+ * sleep mode was exited because of a tick interrupt, or an interrupt
+ * generated by something else. */
     static volatile uint32_t ulTickFlag = pdFALSE;
 
-    /* The CMT counter is stopped temporarily each time it is re-programmed.
-    The following constant offsets the CMT counter match value by the number of
-    CMT counts that would typically be missed while the counter was stopped to
-    compensate for the lost time.  The large difference between the divided CMT
-    clock and the CPU clock means it is likely ulStoppedTimerCompensation will
-    equal zero - and be optimised away. */
+/* The CMT counter is stopped temporarily each time it is re-programmed.
+ * The following constant offsets the CMT counter match value by the number of
+ * CMT counts that would typically be missed while the counter was stopped to
+ * compensate for the lost time.  The large difference between the divided CMT
+ * clock and the CPU clock means it is likely ulStoppedTimerCompensation will
+ * equal zero - and be optimised away. */
     static const uint32_t ulStoppedTimerCompensation = 100UL / ( configCPU_CLOCK_HZ / ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) );
 
-#endif
+#endif /* if configUSE_TICKLESS_IDLE == 1 */
 
 /*-----------------------------------------------------------*/
 
 /*
  * See header file for description.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
     /* Offset to end up on 8 byte boundary. */
     pxTopOfStack--;
@@ -158,8 +161,8 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
     *pxTopOfStack = ( StackType_t ) pxCode;
 
     /* When debugging it can be useful if every register is set to a known
-    value.  Otherwise code space can be saved by just setting the registers
-    that need to be set. */
+     * value.  Otherwise code space can be saved by just setting the registers
+     * that need to be set. */
     #ifdef USE_FULL_REGISTER_INITIALISATION
     {
         pxTopOfStack--;
@@ -192,19 +195,19 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
         *pxTopOfStack = 0x22222222;
         pxTopOfStack--;
     }
-    #else
+    #else /* ifdef USE_FULL_REGISTER_INITIALISATION */
     {
         /* Leave space for the registers that will get popped from the stack
-        when the task first starts executing. */
+         * when the task first starts executing. */
         pxTopOfStack -= 15;
     }
-    #endif
+    #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */
 
     *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
     pxTopOfStack--;
-    *pxTopOfStack = 0x12345678; /* Accumulator. */
+    *pxTopOfStack = 0x12345678;                   /* Accumulator. */
     pxTopOfStack--;
-    *pxTopOfStack = 0x87654321; /* Accumulator. */
+    *pxTopOfStack = 0x87654321;                   /* Accumulator. */
 
     return pxTopOfStack;
 }
@@ -216,10 +219,10 @@ BaseType_t xPortStartScheduler( void )
     if( pxCurrentTCB != NULL )
     {
         /* Call an application function to set up the timer that will generate
-        the tick interrupt.  This way the application can decide which
-        peripheral to use.  If tickless mode is used then the default
-        implementation defined in this file (which uses CMT0) should not be
-        overridden. */
+         * the tick interrupt.  This way the application can decide which
+         * peripheral to use.  If tickless mode is used then the default
+         * implementation defined in this file (which uses CMT0) should not be
+         * overridden. */
         configSETUP_TICK_INTERRUPT();
 
         /* Enable the software interrupt. */
@@ -236,11 +239,11 @@ BaseType_t xPortStartScheduler( void )
     }
 
     /* Execution should not reach here as the tasks are now running!
-    prvSetupTimerInterrupt() is called here to prevent the compiler outputting
-    a warning about a statically declared function not being referenced in the
-    case that the application writer has provided their own tick interrupt
-    configuration routine (and defined configSETUP_TICK_INTERRUPT() such that
-    their own routine will be called in place of prvSetupTimerInterrupt()). */
+     * prvSetupTimerInterrupt() is called here to prevent the compiler outputting
+     * a warning about a statically declared function not being referenced in the
+     * case that the application writer has provided their own tick interrupt
+     * configuration routine (and defined configSETUP_TICK_INTERRUPT() such that
+     * their own routine will be called in place of prvSetupTimerInterrupt()). */
     prvSetupTimerInterrupt();
 
     /* Should not get here. */
@@ -255,7 +258,7 @@ __interrupt static void prvTickISR( void )
     __enable_interrupt();
 
     /* Increment the tick, and perform any processing the new tick value
-    necessitates. */
+     * necessitates. */
     __set_interrupt_level( configMAX_SYSCALL_INTERRUPT_PRIORITY );
     {
         if( xTaskIncrementTick() != pdFALSE )
@@ -271,7 +274,7 @@ __interrupt static void prvTickISR( void )
         ulTickFlag = pdTRUE;
 
         /* If this is the first tick since exiting tickless mode then the CMT
-        compare match value needs resetting. */
+         * compare match value needs resetting. */
         CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;
     }
     #endif
@@ -281,7 +284,7 @@ __interrupt static void prvTickISR( void )
 void vPortEndScheduler( void )
 {
     /* Not implemented in ports where there is nothing to return to.
-    Artificially force an assert. */
+     * Artificially force an assert. */
     configASSERT( pxCurrentTCB == NULL );
 }
 /*-----------------------------------------------------------*/
@@ -320,11 +323,11 @@ static void prvSetupTimerInterrupt( void )
     {
         CMT0.CMCR.BIT.CKS = 0;
     }
-    #else
+    #else /* if portCLOCK_DIVISOR == 512 */
     {
         #error Invalid portCLOCK_DIVISOR setting
     }
-    #endif
+    #endif /* if portCLOCK_DIVISOR == 512 */
 
 
     /* Enable the interrupt... */
@@ -346,8 +349,8 @@ static void prvSetupTimerInterrupt( void )
         configPRE_SLEEP_PROCESSING( xExpectedIdleTime );
 
         /* xExpectedIdleTime being set to 0 by configPRE_SLEEP_PROCESSING()
-        means the application defined code has already executed the WAIT
-        instruction. */
+         * means the application defined code has already executed the WAIT
+         * instruction. */
         if( xExpectedIdleTime > 0 )
         {
             __wait_for_interrupt();
@@ -364,8 +367,8 @@ static void prvSetupTimerInterrupt( void )
 
     void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
     {
-    uint32_t ulMatchValue, ulCompleteTickPeriods, ulCurrentCount;
-    eSleepModeStatus eSleepAction;
+        uint32_t ulMatchValue, ulCompleteTickPeriods, ulCurrentCount;
+        eSleepModeStatus eSleepAction;
 
         /* THIS FUNCTION IS CALLED WITH THE SCHEDULER SUSPENDED. */
 
@@ -376,38 +379,41 @@ static void prvSetupTimerInterrupt( void )
         }
 
         /* Calculate the reload value required to wait xExpectedIdleTime tick
-        periods. */
+         * periods. */
         ulMatchValue = ulMatchValueForOneTick * xExpectedIdleTime;
+
         if( ulMatchValue > ulStoppedTimerCompensation )
         {
             /* Compensate for the fact that the CMT is going to be stopped
-            momentarily. */
+             * momentarily. */
             ulMatchValue -= ulStoppedTimerCompensation;
         }
 
         /* Stop the CMT momentarily.  The time the CMT is stopped for is
-        accounted for as best it can be, but using the tickless mode will
-        inevitably result in some tiny drift of the time maintained by the
-        kernel with respect to calendar time. */
+         * accounted for as best it can be, but using the tickless mode will
+         * inevitably result in some tiny drift of the time maintained by the
+         * kernel with respect to calendar time. */
         CMT.CMSTR0.BIT.STR0 = 0;
+
         while( CMT.CMSTR0.BIT.STR0 == 1 )
         {
             /* Nothing to do here. */
         }
 
         /* Critical section using the global interrupt bit as the i bit is
-        automatically reset by the WAIT instruction. */
+         * automatically reset by the WAIT instruction. */
         __disable_interrupt();
 
         /* The tick flag is set to false before sleeping.  If it is true when
-        sleep mode is exited then sleep mode was probably exited because the
-        tick was suppressed for the entire xExpectedIdleTime period. */
+         * sleep mode is exited then sleep mode was probably exited because the
+         * tick was suppressed for the entire xExpectedIdleTime period. */
         ulTickFlag = pdFALSE;
 
         /* If a context switch is pending then abandon the low power entry as
-        the context switch might have been pended by an external interrupt that
-        requires processing. */
+         * the context switch might have been pended by an external interrupt that
+         * requires processing. */
         eSleepAction = eTaskConfirmSleepModeStatus();
+
         if( eSleepAction == eAbortSleep )
         {
             /* Restart tick. */
@@ -426,7 +432,7 @@ static void prvSetupTimerInterrupt( void )
             SYSTEM.PRCR.WORD = portLOCK_KEY;
 
             /* Sleep until something happens.  Calling prvSleep() will
-            automatically reset the i bit in the PSW. */
+             * automatically reset the i bit in the PSW. */
             prvSleep( xExpectedIdleTime );
 
             /* Restart the CMT. */
@@ -446,7 +452,7 @@ static void prvSetupTimerInterrupt( void )
             SYSTEM.PRCR.WORD = portLOCK_KEY;
 
             /* Adjust the match value to take into account that the current
-            time slice is already partially complete. */
+             * time slice is already partially complete. */
             ulMatchValue -= ( uint32_t ) CMT0.CMCNT;
             CMT0.CMCOR = ( uint16_t ) ulMatchValue;
 
@@ -455,14 +461,15 @@ static void prvSetupTimerInterrupt( void )
             CMT.CMSTR0.BIT.STR0 = 1;
 
             /* Sleep until something happens.  Calling prvSleep() will
-            automatically reset the i bit in the PSW. */
+             * automatically reset the i bit in the PSW. */
             prvSleep( xExpectedIdleTime );
 
             /* Stop CMT.  Again, the time the SysTick is stopped for is
-            accounted for as best it can be, but using the tickless mode will
-            inevitably result in some tiny drift of the time maintained by the
-            kernel with respect to calendar time. */
+             * accounted for as best it can be, but using the tickless mode will
+             * inevitably result in some tiny drift of the time maintained by the
+             * kernel with respect to calendar time. */
             CMT.CMSTR0.BIT.STR0 = 0;
+
             while( CMT.CMSTR0.BIT.STR0 == 1 )
             {
                 /* Nothing to do here. */
@@ -473,42 +480,42 @@ static void prvSetupTimerInterrupt( void )
             if( ulTickFlag != pdFALSE )
             {
                 /* The tick interrupt has already executed, although because
-                this function is called with the scheduler suspended the actual
-                tick processing will not occur until after this function has
-                exited.  Reset the match value with whatever remains of this
-                tick period. */
+                 * this function is called with the scheduler suspended the actual
+                 * tick processing will not occur until after this function has
+                 * exited.  Reset the match value with whatever remains of this
+                 * tick period. */
                 ulMatchValue = ulMatchValueForOneTick - ulCurrentCount;
                 CMT0.CMCOR = ( uint16_t ) ulMatchValue;
 
                 /* The tick interrupt handler will already have pended the tick
-                processing in the kernel.  As the pending tick will be
-                processed as soon as this function exits, the tick value
-                maintained by the tick is stepped forward by one less than the
-                time spent sleeping.  The actual stepping of the tick appears
-                later in this function. */
+                 * processing in the kernel.  As the pending tick will be
+                 * processed as soon as this function exits, the tick value
+                 * maintained by the tick is stepped forward by one less than the
+                 * time spent sleeping.  The actual stepping of the tick appears
+                 * later in this function. */
                 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
             }
             else
             {
                 /* Something other than the tick interrupt ended the sleep.
-                How many complete tick periods passed while the processor was
-                sleeping? */
+                 * How many complete tick periods passed while the processor was
+                 * sleeping? */
                 ulCompleteTickPeriods = ulCurrentCount / ulMatchValueForOneTick;
 
                 /* The match value is set to whatever fraction of a single tick
-                period remains. */
+                 * period remains. */
                 ulMatchValue = ulCurrentCount - ( ulCompleteTickPeriods * ulMatchValueForOneTick );
                 CMT0.CMCOR = ( uint16_t ) ulMatchValue;
             }
 
             /* Restart the CMT so it runs up to the match value.  The match value
-            will get set to the value required to generate exactly one tick period
-            the next time the CMT interrupt executes. */
+             * will get set to the value required to generate exactly one tick period
+             * the next time the CMT interrupt executes. */
             CMT0.CMCNT = 0;
             CMT.CMSTR0.BIT.STR0 = 1;
 
             /* Wind the tick forward by the number of tick periods that the CPU
-            remained in a low power state. */
+             * remained in a low power state. */
             vTaskStepTick( ulCompleteTickPeriods );
         }
     }
diff --git a/portable/IAR/RX100/portmacro.h b/portable/IAR/RX100/portmacro.h
index e53c43e4c..2ea18f97a 100644
--- a/portable/IAR/RX100/portmacro.h
+++ b/portable/IAR/RX100/portmacro.h
@@ -52,40 +52,40 @@
  */
 
 /* Type definitions - these are a bit legacy and not really used now, other than
-portSTACK_TYPE and portBASE_TYPE. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint32_t
-#define portBASE_TYPE   long
+ * portSTACK_TYPE and portBASE_TYPE. */
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-    not need to be guarded with a critical section. */
-    #define portTICK_TYPE_IS_ATOMIC 1
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+    #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portBYTE_ALIGNMENT          8   /* Could make four, according to manual. */
-#define portSTACK_GROWTH            -1
-#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portNOP()                   __no_operation()
+#define portBYTE_ALIGNMENT    8         /* Could make four, according to manual. */
+#define portSTACK_GROWTH      -1
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()    __no_operation()
 
 #define portYIELD()                     \
     __asm volatile                      \
@@ -96,55 +96,55 @@ typedef unsigned long UBaseType_t;
         ::: "R15"                       \
     )
 
-#define portYIELD_FROM_ISR( x ) do { if( ( x ) != pdFALSE ) { portYIELD(); } } while( 0 )
+#define portYIELD_FROM_ISR( x )                           do { if( ( x ) != pdFALSE ) { portYIELD(); } } while( 0 )
 
 /* These macros should not be called directly, but through the
-taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
-performed if configASSERT() is defined to ensure an assertion handler does not
-inadvertently attempt to lower the IPL when the call to assert was triggered
-because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
-when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
-functions are those that end in FromISR.  FreeRTOS maintains a separate
-interrupt API to ensure API function and interrupt entry is as fast and as
-simple as possible. */
-#define portENABLE_INTERRUPTS()     __set_interrupt_level( ( uint8_t ) 0 )
+ * taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
+ * performed if configASSERT() is defined to ensure an assertion handler does not
+ * inadvertently attempt to lower the IPL when the call to assert was triggered
+ * because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
+ * when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
+ * functions are those that end in FromISR.  FreeRTOS maintains a separate
+ * interrupt API to ensure API function and interrupt entry is as fast and as
+ * simple as possible. */
+#define portENABLE_INTERRUPTS()                           __set_interrupt_level( ( uint8_t ) 0 )
 #ifdef configASSERT
-    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( __get_interrupt_level() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
-    #define portDISABLE_INTERRUPTS()    if( __get_interrupt_level() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    configASSERT( ( __get_interrupt_level() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+    #define portDISABLE_INTERRUPTS()                      if( __get_interrupt_level() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
 #else
-    #define portDISABLE_INTERRUPTS()    __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+    #define portDISABLE_INTERRUPTS()                      __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
 #endif
 
 /* Critical nesting counts are stored in the TCB. */
-#define portCRITICAL_NESTING_IN_TCB ( 1 )
+#define portCRITICAL_NESTING_IN_TCB    ( 1 )
 
 /* The critical nesting functions defined within tasks.c. */
 extern void vTaskEnterCritical( void );
 extern void vTaskExitCritical( void );
-#define portENTER_CRITICAL()    vTaskEnterCritical()
-#define portEXIT_CRITICAL()     vTaskExitCritical()
+#define portENTER_CRITICAL()                                           vTaskEnterCritical()
+#define portEXIT_CRITICAL()                                            vTaskExitCritical()
 
 /* As this port allows interrupt nesting... */
-#define portSET_INTERRUPT_MASK_FROM_ISR() __get_interrupt_level(); portDISABLE_INTERRUPTS()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) __set_interrupt_level( ( uint8_t ) ( uxSavedInterruptStatus ) )
+#define portSET_INTERRUPT_MASK_FROM_ISR()                              __get_interrupt_level(); portDISABLE_INTERRUPTS()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus )    __set_interrupt_level( ( uint8_t ) ( uxSavedInterruptStatus ) )
 
 /* Tickless idle/low power functionality. */
 #if configUSE_TICKLESS_IDLE == 1
     #ifndef portSUPPRESS_TICKS_AND_SLEEP
         extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
-        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
     #endif
 #endif
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
 /* Prevent warnings of undefined behaviour: the order of volatile accesses is
-undefined - all warnings have been manually checked and are not an issue, and
-the warnings cannot be prevent by code changes without undesirable effects. */
+ * undefined - all warnings have been manually checked and are not an issue, and
+ * the warnings cannot be prevent by code changes without undesirable effects. */
 #pragma diag_suppress=Pa082
 
 /* *INDENT-OFF* */
diff --git a/portable/IAR/RX600/port.c b/portable/IAR/RX600/port.c
index 547f7fb4d..f59725bbd 100644
--- a/portable/IAR/RX600/port.c
+++ b/portable/IAR/RX600/port.c
@@ -27,8 +27,8 @@
  */
 
 /*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the SH2A port.
- *----------------------------------------------------------*/
+* Implementation of functions defined in portable.h for the SH2A port.
+*----------------------------------------------------------*/
 
 /* Scheduler includes. */
 #include "FreeRTOS.h"
@@ -43,8 +43,8 @@
 /*-----------------------------------------------------------*/
 
 /* Tasks should start with interrupts enabled and in Supervisor mode, therefore
-PSW is set with U and I set, and PM and IPL clear. */
-#define portINITIAL_PSW  ( ( StackType_t ) 0x00030000 )
+ * PSW is set with U and I set, and PM and IPL clear. */
+#define portINITIAL_PSW     ( ( StackType_t ) 0x00030000 )
 #define portINITIAL_FPSW    ( ( StackType_t ) 0x00000100 )
 
 /*-----------------------------------------------------------*/
@@ -63,14 +63,16 @@ __interrupt void vTickISR( void );
 
 /*-----------------------------------------------------------*/
 
-extern void *pxCurrentTCB;
+extern void * pxCurrentTCB;
 
 /*-----------------------------------------------------------*/
 
 /*
  * See header file for description.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
     /* R0 is not included as it is the stack pointer. */
 
@@ -81,8 +83,8 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
     *pxTopOfStack = ( StackType_t ) pxCode;
 
     /* When debugging it can be useful if every register is set to a known
-    value.  Otherwise code space can be saved by just setting the registers
-    that need to be set. */
+     * value.  Otherwise code space can be saved by just setting the registers
+     * that need to be set. */
     #ifdef USE_FULL_REGISTER_INITIALISATION
     {
         pxTopOfStack--;
@@ -115,11 +117,11 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
         *pxTopOfStack = 0x22222222;
         pxTopOfStack--;
     }
-    #else
+    #else /* ifdef USE_FULL_REGISTER_INITIALISATION */
     {
         pxTopOfStack -= 15;
     }
-    #endif
+    #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */
 
     *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
     pxTopOfStack--;
@@ -135,14 +137,14 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
 
 BaseType_t xPortStartScheduler( void )
 {
-extern void vApplicationSetupTimerInterrupt( void );
+    extern void vApplicationSetupTimerInterrupt( void );
 
     /* Use pxCurrentTCB just so it does not get optimised away. */
     if( pxCurrentTCB != NULL )
     {
         /* Call an application function to set up the timer that will generate the
-        tick interrupt.  This way the application can decide which peripheral to
-        use.  A demo application is provided to show a suitable example. */
+         * tick interrupt.  This way the application can decide which peripheral to
+         * use.  A demo application is provided to show a suitable example. */
         vApplicationSetupTimerInterrupt();
 
         /* Enable the software interrupt. */
@@ -170,7 +172,7 @@ __interrupt void vTickISR( void )
     __enable_interrupt();
 
     /* Increment the tick, and perform any processing the new tick value
-    necessitates. */
+     * necessitates. */
     __set_interrupt_level( configMAX_SYSCALL_INTERRUPT_PRIORITY );
     {
         if( xTaskIncrementTick() != pdFALSE )
@@ -185,7 +187,7 @@ __interrupt void vTickISR( void )
 void vPortEndScheduler( void )
 {
     /* Not implemented in ports where there is nothing to return to.
-    Artificially force an assert. */
+     * Artificially force an assert. */
     configASSERT( pxCurrentTCB == NULL );
 }
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/RX600/portmacro.h b/portable/IAR/RX600/portmacro.h
index 1b1bec3fc..0a3659c92 100644
--- a/portable/IAR/RX600/portmacro.h
+++ b/portable/IAR/RX600/portmacro.h
@@ -49,92 +49,92 @@
  */
 
 /* Type definitions - these are a bit legacy and not really used now, other than
-portSTACK_TYPE and portBASE_TYPE. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint32_t
-#define portBASE_TYPE   long
+ * portSTACK_TYPE and portBASE_TYPE. */
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-    not need to be guarded with a critical section. */
-    #define portTICK_TYPE_IS_ATOMIC 1
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+    #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portBYTE_ALIGNMENT          8   /* Could make four, according to manual. */
-#define portSTACK_GROWTH            -1
-#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portNOP()                   __no_operation()
+#define portBYTE_ALIGNMENT    8         /* Could make four, according to manual. */
+#define portSTACK_GROWTH      -1
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()    __no_operation()
 
 /* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;"
-where portITU_SWINTR is the location of the software interrupt register
-(0x000872E0).  Don't rely on the assembler to select a register, so instead
-save and restore clobbered registers manually. */
-#define portYIELD()                         \
-    __asm volatile                          \
-    (                                       \
-        "PUSH.L R10                 \n"     \
-        "MOV.L  #0x872E0, R10       \n"     \
-        "MOV.B  #0x1, [R10]         \n"     \
-        "MOV.L  [R10], R10          \n"     \
-        "POP    R10                 \n"     \
+ * where portITU_SWINTR is the location of the software interrupt register
+ * (0x000872E0).  Don't rely on the assembler to select a register, so instead
+ * save and restore clobbered registers manually. */
+#define portYIELD()                     \
+    __asm volatile                      \
+    (                                   \
+        "PUSH.L R10                 \n" \
+        "MOV.L  #0x872E0, R10       \n" \
+        "MOV.B  #0x1, [R10]         \n" \
+        "MOV.L  [R10], R10          \n" \
+        "POP    R10                 \n" \
     )
 
-#define portYIELD_FROM_ISR( x ) do { if( ( x ) != pdFALSE ) portYIELD(); } while( 0 )
+#define portYIELD_FROM_ISR( x )                           do { if( ( x ) != pdFALSE ) portYIELD( ); } while( 0 )
 
 /* These macros should not be called directly, but through the
-taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
-performed if configASSERT() is defined to ensure an assertion handler does not
-inadvertently attempt to lower the IPL when the call to assert was triggered
-because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
-when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
-functions are those that end in FromISR.  FreeRTOS maintains a separate
-interrupt API to ensure API function and interrupt entry is as fast and as
-simple as possible. */
-#define portENABLE_INTERRUPTS()     __set_interrupt_level( ( uint8_t ) 0 )
+ * taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
+ * performed if configASSERT() is defined to ensure an assertion handler does not
+ * inadvertently attempt to lower the IPL when the call to assert was triggered
+ * because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
+ * when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
+ * functions are those that end in FromISR.  FreeRTOS maintains a separate
+ * interrupt API to ensure API function and interrupt entry is as fast and as
+ * simple as possible. */
+#define portENABLE_INTERRUPTS()                           __set_interrupt_level( ( uint8_t ) 0 )
 #ifdef configASSERT
-    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( __get_interrupt_level() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
-    #define portDISABLE_INTERRUPTS()    if( __get_interrupt_level() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    configASSERT( ( __get_interrupt_level() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+    #define portDISABLE_INTERRUPTS()                      if( __get_interrupt_level() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
 #else
-    #define portDISABLE_INTERRUPTS()    __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+    #define portDISABLE_INTERRUPTS()                      __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
 #endif
 
 /* Critical nesting counts are stored in the TCB. */
-#define portCRITICAL_NESTING_IN_TCB ( 1 )
+#define portCRITICAL_NESTING_IN_TCB    ( 1 )
 
 /* The critical nesting functions defined within tasks.c. */
 extern void vTaskEnterCritical( void );
 extern void vTaskExitCritical( void );
-#define portENTER_CRITICAL()    vTaskEnterCritical()
-#define portEXIT_CRITICAL()     vTaskExitCritical()
+#define portENTER_CRITICAL()                                           vTaskEnterCritical()
+#define portEXIT_CRITICAL()                                            vTaskExitCritical()
 
 /* As this port allows interrupt nesting... */
-#define portSET_INTERRUPT_MASK_FROM_ISR() __get_interrupt_level(); portDISABLE_INTERRUPTS()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) __set_interrupt_level( ( uint8_t ) ( uxSavedInterruptStatus ) )
+#define portSET_INTERRUPT_MASK_FROM_ISR()                              __get_interrupt_level(); portDISABLE_INTERRUPTS()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus )    __set_interrupt_level( ( uint8_t ) ( uxSavedInterruptStatus ) )
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/IAR/RX700v3_DPFPU/port.c b/portable/IAR/RX700v3_DPFPU/port.c
index a77efa725..2a902f28e 100644
--- a/portable/IAR/RX700v3_DPFPU/port.c
+++ b/portable/IAR/RX700v3_DPFPU/port.c
@@ -54,22 +54,22 @@
 
 /* Tasks should start with interrupts enabled and in Supervisor mode, therefore
  * PSW is set with U and I set, and PM and IPL clear. */
-#define portINITIAL_PSW     ( ( StackType_t ) 0x00030000 )
-#define portINITIAL_FPSW    ( ( StackType_t ) 0x00000100 )
-#define portINITIAL_DPSW    ( ( StackType_t ) 0x00000100 )
-#define portINITIAL_DCMR    ( ( StackType_t ) 0x00000000 )
-#define portINITIAL_DECNT   ( ( StackType_t ) 0x00000001 )
+#define portINITIAL_PSW                  ( ( StackType_t ) 0x00030000 )
+#define portINITIAL_FPSW                 ( ( StackType_t ) 0x00000100 )
+#define portINITIAL_DPSW                 ( ( StackType_t ) 0x00000100 )
+#define portINITIAL_DCMR                 ( ( StackType_t ) 0x00000000 )
+#define portINITIAL_DECNT                ( ( StackType_t ) 0x00000001 )
 
 /* Tasks are not created with a DPFPU context, but can be given a DPFPU context
  * after they have been created.  A variable is stored as part of the tasks context
  * that holds portNO_DPFPU_CONTEXT if the task does not have a DPFPU context, or
  * any other value if the task does have a DPFPU context. */
-#define portNO_DPFPU_CONTEXT    ( ( StackType_t ) 0 )
-#define portHAS_DPFPU_CONTEXT   ( ( StackType_t ) 1 )
+#define portNO_DPFPU_CONTEXT             ( ( StackType_t ) 0 )
+#define portHAS_DPFPU_CONTEXT            ( ( StackType_t ) 1 )
 
 /* The space on the stack required to hold the DPFPU data registers.  This is 16
  * 64-bit registers. */
-#define portDPFPU_DATA_REGISTER_WORDS   ( 16 * 2 )
+#define portDPFPU_DATA_REGISTER_WORDS    ( 16 * 2 )
 
 /*-----------------------------------------------------------*/
 
@@ -128,41 +128,41 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
      * value.  Otherwise code space can be saved by just setting the registers
      * that need to be set. */
     #ifdef USE_FULL_REGISTER_INITIALISATION
-        {
-            pxTopOfStack--;
-            *pxTopOfStack = 0xffffffff; /* r15. */
-            pxTopOfStack--;
-            *pxTopOfStack = 0xeeeeeeee;
-            pxTopOfStack--;
-            *pxTopOfStack = 0xdddddddd;
-            pxTopOfStack--;
-            *pxTopOfStack = 0xcccccccc;
-            pxTopOfStack--;
-            *pxTopOfStack = 0xbbbbbbbb;
-            pxTopOfStack--;
-            *pxTopOfStack = 0xaaaaaaaa;
-            pxTopOfStack--;
-            *pxTopOfStack = 0x99999999;
-            pxTopOfStack--;
-            *pxTopOfStack = 0x88888888;
-            pxTopOfStack--;
-            *pxTopOfStack = 0x77777777;
-            pxTopOfStack--;
-            *pxTopOfStack = 0x66666666;
-            pxTopOfStack--;
-            *pxTopOfStack = 0x55555555;
-            pxTopOfStack--;
-            *pxTopOfStack = 0x44444444;
-            pxTopOfStack--;
-            *pxTopOfStack = 0x33333333;
-            pxTopOfStack--;
-            *pxTopOfStack = 0x22222222;
-            pxTopOfStack--;
-        }
+    {
+        pxTopOfStack--;
+        *pxTopOfStack = 0xffffffff; /* r15. */
+        pxTopOfStack--;
+        *pxTopOfStack = 0xeeeeeeee;
+        pxTopOfStack--;
+        *pxTopOfStack = 0xdddddddd;
+        pxTopOfStack--;
+        *pxTopOfStack = 0xcccccccc;
+        pxTopOfStack--;
+        *pxTopOfStack = 0xbbbbbbbb;
+        pxTopOfStack--;
+        *pxTopOfStack = 0xaaaaaaaa;
+        pxTopOfStack--;
+        *pxTopOfStack = 0x99999999;
+        pxTopOfStack--;
+        *pxTopOfStack = 0x88888888;
+        pxTopOfStack--;
+        *pxTopOfStack = 0x77777777;
+        pxTopOfStack--;
+        *pxTopOfStack = 0x66666666;
+        pxTopOfStack--;
+        *pxTopOfStack = 0x55555555;
+        pxTopOfStack--;
+        *pxTopOfStack = 0x44444444;
+        pxTopOfStack--;
+        *pxTopOfStack = 0x33333333;
+        pxTopOfStack--;
+        *pxTopOfStack = 0x22222222;
+        pxTopOfStack--;
+    }
     #else /* ifdef USE_FULL_REGISTER_INITIALISATION */
-        {
-            pxTopOfStack -= 15;
-        }
+    {
+        pxTopOfStack -= 15;
+    }
     #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */
 
     *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
@@ -182,73 +182,73 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
     *pxTopOfStack = 0x66666666; /* Accumulator 0. */
 
     #if ( configUSE_TASK_DPFPU_SUPPORT == 1 )
-        {
-            /* The task will start without a DPFPU context.  A task that
-             * uses the DPFPU hardware must call vPortTaskUsesDPFPU() before
-             * executing any floating point instructions. */
-            pxTopOfStack--;
-            *pxTopOfStack = portNO_DPFPU_CONTEXT;
-        }
+    {
+        /* The task will start without a DPFPU context.  A task that
+         * uses the DPFPU hardware must call vPortTaskUsesDPFPU() before
+         * executing any floating point instructions. */
+        pxTopOfStack--;
+        *pxTopOfStack = portNO_DPFPU_CONTEXT;
+    }
     #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 )
+    {
+        /* The task will start with a DPFPU context.  Leave enough
+         * space for the registers - and ensure they are initialised if desired. */
+        #ifdef USE_FULL_REGISTER_INITIALISATION
         {
-            /* The task will start with a DPFPU context.  Leave enough
-             * space for the registers - and ensure they are initialised if desired. */
-            #ifdef USE_FULL_REGISTER_INITIALISATION
-                {
-                    pxTopOfStack -= 2;
-                    *(double *)pxTopOfStack = 1515.1515; /* DR15. */
-                    pxTopOfStack -= 2;
-                    *(double *)pxTopOfStack = 1414.1414; /* DR14. */
-                    pxTopOfStack -= 2;
-                    *(double *)pxTopOfStack = 1313.1313; /* DR13. */
-                    pxTopOfStack -= 2;
-                    *(double *)pxTopOfStack = 1212.1212; /* DR12. */
-                    pxTopOfStack -= 2;
-                    *(double *)pxTopOfStack = 1111.1111; /* DR11. */
-                    pxTopOfStack -= 2;
-                    *(double *)pxTopOfStack = 1010.1010; /* DR10. */
-                    pxTopOfStack -= 2;
-                    *(double *)pxTopOfStack =  909.0909; /* DR9. */
-                    pxTopOfStack -= 2;
-                    *(double *)pxTopOfStack =  808.0808; /* DR8. */
-                    pxTopOfStack -= 2;
-                    *(double *)pxTopOfStack =  707.0707; /* DR7. */
-                    pxTopOfStack -= 2;
-                    *(double *)pxTopOfStack =  606.0606; /* DR6. */
-                    pxTopOfStack -= 2;
-                    *(double *)pxTopOfStack =  505.0505; /* DR5. */
-                    pxTopOfStack -= 2;
-                    *(double *)pxTopOfStack =  404.0404; /* DR4. */
-                    pxTopOfStack -= 2;
-                    *(double *)pxTopOfStack =  303.0303; /* DR3. */
-                    pxTopOfStack -= 2;
-                    *(double *)pxTopOfStack =  202.0202; /* DR2. */
-                    pxTopOfStack -= 2;
-                    *(double *)pxTopOfStack =  101.0101; /* DR1. */
-                    pxTopOfStack -= 2;
-                    *(double *)pxTopOfStack = 9876.54321;/* DR0. */
-                }
-            #else /* ifdef USE_FULL_REGISTER_INITIALISATION */
-                {
-                    pxTopOfStack -= portDPFPU_DATA_REGISTER_WORDS;
-                    memset( pxTopOfStack, 0x00, portDPFPU_DATA_REGISTER_WORDS * sizeof( StackType_t ) );
-                }
-            #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */
-            pxTopOfStack--;
-            *pxTopOfStack = portINITIAL_DECNT; /* DECNT. */
-            pxTopOfStack--;
-            *pxTopOfStack = portINITIAL_DCMR;  /* DCMR. */
-            pxTopOfStack--;
-            *pxTopOfStack = portINITIAL_DPSW;  /* DPSW. */
+            pxTopOfStack -= 2;
+            *( double * ) pxTopOfStack = 1515.1515;  /* DR15. */
+            pxTopOfStack -= 2;
+            *( double * ) pxTopOfStack = 1414.1414;  /* DR14. */
+            pxTopOfStack -= 2;
+            *( double * ) pxTopOfStack = 1313.1313;  /* DR13. */
+            pxTopOfStack -= 2;
+            *( double * ) pxTopOfStack = 1212.1212;  /* DR12. */
+            pxTopOfStack -= 2;
+            *( double * ) pxTopOfStack = 1111.1111;  /* DR11. */
+            pxTopOfStack -= 2;
+            *( double * ) pxTopOfStack = 1010.1010;  /* DR10. */
+            pxTopOfStack -= 2;
+            *( double * ) pxTopOfStack = 909.0909;   /* DR9. */
+            pxTopOfStack -= 2;
+            *( double * ) pxTopOfStack = 808.0808;   /* DR8. */
+            pxTopOfStack -= 2;
+            *( double * ) pxTopOfStack = 707.0707;   /* DR7. */
+            pxTopOfStack -= 2;
+            *( double * ) pxTopOfStack = 606.0606;   /* DR6. */
+            pxTopOfStack -= 2;
+            *( double * ) pxTopOfStack = 505.0505;   /* DR5. */
+            pxTopOfStack -= 2;
+            *( double * ) pxTopOfStack = 404.0404;   /* DR4. */
+            pxTopOfStack -= 2;
+            *( double * ) pxTopOfStack = 303.0303;   /* DR3. */
+            pxTopOfStack -= 2;
+            *( double * ) pxTopOfStack = 202.0202;   /* DR2. */
+            pxTopOfStack -= 2;
+            *( double * ) pxTopOfStack = 101.0101;   /* DR1. */
+            pxTopOfStack -= 2;
+            *( double * ) pxTopOfStack = 9876.54321; /* DR0. */
         }
+        #else /* ifdef USE_FULL_REGISTER_INITIALISATION */
+        {
+            pxTopOfStack -= portDPFPU_DATA_REGISTER_WORDS;
+            memset( pxTopOfStack, 0x00, portDPFPU_DATA_REGISTER_WORDS * sizeof( StackType_t ) );
+        }
+        #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */
+        pxTopOfStack--;
+        *pxTopOfStack = portINITIAL_DECNT; /* DECNT. */
+        pxTopOfStack--;
+        *pxTopOfStack = portINITIAL_DCMR;  /* DCMR. */
+        pxTopOfStack--;
+        *pxTopOfStack = portINITIAL_DPSW;  /* DPSW. */
+    }
     #elif ( configUSE_TASK_DPFPU_SUPPORT == 0 )
-        {
-            /* Omit DPFPU support. */
-        }
+    {
+        /* Omit DPFPU support. */
+    }
     #else /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */
-        {
-            #error Invalid configUSE_TASK_DPFPU_SUPPORT setting - configUSE_TASK_DPFPU_SUPPORT must be set to 0, 1, 2, or left undefined.
-        }
+    {
+        #error Invalid configUSE_TASK_DPFPU_SUPPORT setting - configUSE_TASK_DPFPU_SUPPORT must be set to 0, 1, 2, or left undefined.
+    }
     #endif /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */
 
     return pxTopOfStack;
@@ -316,14 +316,14 @@ static void prvStartFirstTask( void )
         /* When starting the scheduler there is nothing that needs moving to the
          * interrupt stack because the function is not called from an interrupt.
          * Just ensure the current stack is the user stack. */
-        "SETPSW     U                       \n"\
+        "SETPSW     U                       \n" \
 
 
         /* Obtain the location of the stack associated with which ever task
          * pxCurrentTCB is currently pointing to. */
-        "MOV.L      #_pxCurrentTCB, R15     \n"\
-        "MOV.L      [R15], R15              \n"\
-        "MOV.L      [R15], R0               \n"\
+        "MOV.L      #_pxCurrentTCB, R15     \n" \
+        "MOV.L      [R15], R15              \n" \
+        "MOV.L      [R15], R0               \n" \
 
 
         /* Restore the registers from the stack of the task pointed to by
@@ -333,53 +333,52 @@ static void prvStartFirstTask( void )
 
             /* The restored ulPortTaskHasDPFPUContext is to be zero here.
              * So, it is never necessary to restore the DPFPU context here. */
-            "POP        R15                                 \n"\
-            "MOV.L      #_ulPortTaskHasDPFPUContext, R14    \n"\
-            "MOV.L      R15, [R14]                          \n"\
+            "POP        R15                                 \n" \
+            "MOV.L      #_ulPortTaskHasDPFPUContext, R14    \n" \
+            "MOV.L      R15, [R14]                          \n" \
 
         #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 )
-
             /* Restore the DPFPU context. */
-            "DPOPM.L    DPSW-DECNT              \n"\
-            "DPOPM.D    DR0-DR15                \n"\
+            "DPOPM.L    DPSW-DECNT              \n" \
+            "DPOPM.D    DR0-DR15                \n" \
 
         #endif /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */
 
-        "POP        R15                     \n"\
+        "POP        R15                     \n" \
 
         /* Accumulator low 32 bits. */
-        "MVTACLO    R15, A0                 \n"\
-        "POP        R15                     \n"\
+        "MVTACLO    R15, A0                 \n" \
+        "POP        R15                     \n" \
 
         /* Accumulator high 32 bits. */
-        "MVTACHI    R15, A0                 \n"\
-        "POP        R15                     \n"\
+        "MVTACHI    R15, A0                 \n" \
+        "POP        R15                     \n" \
 
         /* Accumulator guard. */
-        "MVTACGU    R15, A0                 \n"\
-        "POP        R15                     \n"\
+        "MVTACGU    R15, A0                 \n" \
+        "POP        R15                     \n" \
 
         /* Accumulator low 32 bits. */
-        "MVTACLO    R15, A1                 \n"\
-        "POP        R15                     \n"\
+        "MVTACLO    R15, A1                 \n" \
+        "POP        R15                     \n" \
 
         /* Accumulator high 32 bits. */
-        "MVTACHI    R15, A1                 \n"\
-        "POP        R15                     \n"\
+        "MVTACHI    R15, A1                 \n" \
+        "POP        R15                     \n" \
 
         /* Accumulator guard. */
-        "MVTACGU    R15, A1                 \n"\
-        "POP        R15                     \n"\
+        "MVTACGU    R15, A1                 \n" \
+        "POP        R15                     \n" \
 
         /* Floating point status word. */
-        "MVTC       R15, FPSW               \n"\
+        "MVTC       R15, FPSW               \n" \
 
         /* R1 to R15 - R0 is not included as it is the SP. */
-        "POPM       R1-R15                  \n"\
+        "POPM       R1-R15                  \n" \
 
         /* This pops the remaining registers. */
-        "RTE                                \n"\
-        "NOP                                \n"\
+        "RTE                                \n" \
+        "NOP                                \n" \
         "NOP                                \n"
     );
 }
@@ -391,100 +390,99 @@ __interrupt void vSoftwareInterruptISR( void )
     __asm volatile
     (
         /* Re-enable interrupts. */
-        "SETPSW     I                           \n"\
+        "SETPSW     I                           \n" \
 
 
         /* Move the data that was automatically pushed onto the interrupt stack when
          * the interrupt occurred from the interrupt stack to the user stack.
          *
          * R15 is saved before it is clobbered. */
-        "PUSH.L     R15                         \n"\
+        "PUSH.L     R15                         \n" \
 
         /* Read the user stack pointer. */
-        "MVFC       USP, R15                    \n"\
+        "MVFC       USP, R15                    \n" \
 
         /* Move the address down to the data being moved. */
-        "SUB        #12, R15                    \n"\
-        "MVTC       R15, USP                    \n"\
+        "SUB        #12, R15                    \n" \
+        "MVTC       R15, USP                    \n" \
 
         /* Copy the data across, R15, then PC, then PSW. */
-        "MOV.L      [ R0 ], [ R15 ]             \n"\
-        "MOV.L      4[ R0 ], 4[ R15 ]           \n"\
-        "MOV.L      8[ R0 ], 8[ R15 ]           \n"\
+        "MOV.L      [ R0 ], [ R15 ]             \n" \
+        "MOV.L      4[ R0 ], 4[ R15 ]           \n" \
+        "MOV.L      8[ R0 ], 8[ R15 ]           \n" \
 
         /* Move the interrupt stack pointer to its new correct position. */
-        "ADD        #12, R0                     \n"\
+        "ADD        #12, R0                     \n" \
 
         /* All the rest of the registers are saved directly to the user stack. */
-        "SETPSW     U                           \n"\
+        "SETPSW     U                           \n" \
 
         /* Save the rest of the general registers (R15 has been saved already). */
-        "PUSHM      R1-R14                      \n"\
+        "PUSHM      R1-R14                      \n" \
 
         /* Save the FPSW and accumulators. */
-        "MVFC       FPSW, R15                   \n"\
-        "PUSH.L     R15                         \n"\
-        "MVFACGU    #0, A1, R15                 \n"\
-        "PUSH.L     R15                         \n"\
-        "MVFACHI    #0, A1, R15                 \n"\
-        "PUSH.L     R15                         \n"\
+        "MVFC       FPSW, R15                   \n"                       \
+        "PUSH.L     R15                         \n"                       \
+        "MVFACGU    #0, A1, R15                 \n"                       \
+        "PUSH.L     R15                         \n"                       \
+        "MVFACHI    #0, A1, R15                 \n"                       \
+        "PUSH.L     R15                         \n"                       \
         "MVFACLO    #0, A1, R15                 \n" /* Low order word. */ \
-        "PUSH.L     R15                         \n"\
-        "MVFACGU    #0, A0, R15                 \n"\
-        "PUSH.L     R15                         \n"\
-        "MVFACHI    #0, A0, R15                 \n"\
-        "PUSH.L     R15                         \n"\
+        "PUSH.L     R15                         \n"                       \
+        "MVFACGU    #0, A0, R15                 \n"                       \
+        "PUSH.L     R15                         \n"                       \
+        "MVFACHI    #0, A0, R15                 \n"                       \
+        "PUSH.L     R15                         \n"                       \
         "MVFACLO    #0, A0, R15                 \n" /* Low order word. */ \
-        "PUSH.L     R15                         \n"\
+        "PUSH.L     R15                         \n"                       \
 
         #if ( configUSE_TASK_DPFPU_SUPPORT == 1 )
 
             /* Does the task have a DPFPU context that needs saving?  If
              * ulPortTaskHasDPFPUContext is 0 then no. */
-            "MOV.L      #_ulPortTaskHasDPFPUContext, R15    \n"\
-            "MOV.L      [R15], R15                          \n"\
-            "CMP        #0, R15                             \n"\
+            "MOV.L      #_ulPortTaskHasDPFPUContext, R15    \n" \
+            "MOV.L      [R15], R15                          \n" \
+            "CMP        #0, R15                             \n" \
 
             /* Save the DPFPU context, if any. */
-            "BEQ.B      __lab1                      \n"\
-            "DPUSHM.D   DR0-DR15                    \n"\
-            "DPUSHM.L   DPSW-DECNT                  \n"\
-            "__lab1:                                \n"\
+            "BEQ.B      __lab1                      \n" \
+            "DPUSHM.D   DR0-DR15                    \n" \
+            "DPUSHM.L   DPSW-DECNT                  \n" \
+            "__lab1:                                \n" \
 
             /* Save ulPortTaskHasDPFPUContext itself. */
-            "PUSH.L     R15                         \n"\
+            "PUSH.L     R15                         \n" \
 
         #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 )
-
             /* Save the DPFPU context, always. */
-            "DPUSHM.D   DR0-DR15                    \n"\
-            "DPUSHM.L   DPSW-DECNT                  \n"\
+            "DPUSHM.D   DR0-DR15                    \n" \
+            "DPUSHM.L   DPSW-DECNT                  \n" \
 
         #endif /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */
 
 
         /* Save the stack pointer to the TCB. */
-        "MOV.L      #_pxCurrentTCB, R15         \n"\
-        "MOV.L      [ R15 ], R15                \n"\
-        "MOV.L      R0, [ R15 ]                 \n"\
+        "MOV.L      #_pxCurrentTCB, R15         \n" \
+        "MOV.L      [ R15 ], R15                \n" \
+        "MOV.L      R0, [ R15 ]                 \n" \
 
 
         /* Ensure the interrupt mask is set to the syscall priority while the kernel
          * structures are being accessed. */
-        "MVTIPL     %0                          \n"\
+        "MVTIPL     %0                          \n" \
 
         /* Select the next task to run. */
-        "BSR.A      _vTaskSwitchContext         \n"\
+        "BSR.A      _vTaskSwitchContext         \n" \
 
         /* Reset the interrupt mask as no more data structure access is required. */
-        "MVTIPL     %1                          \n"\
+        "MVTIPL     %1                          \n" \
 
 
         /* Load the stack pointer of the task that is now selected as the Running
          * state task from its TCB. */
-        "MOV.L      #_pxCurrentTCB,R15          \n"\
-        "MOV.L      [ R15 ], R15                \n"\
-        "MOV.L      [ R15 ], R0                 \n"\
+        "MOV.L      #_pxCurrentTCB,R15          \n" \
+        "MOV.L      [ R15 ], R15                \n" \
+        "MOV.L      [ R15 ], R0                 \n" \
 
 
         /* Restore the context of the new task.  The PSW (Program Status Word) and
@@ -494,56 +492,55 @@ __interrupt void vSoftwareInterruptISR( void )
 
             /* Is there a DPFPU context to restore?  If the restored
              * ulPortTaskHasDPFPUContext is zero then no. */
-            "POP        R15                                 \n"\
-            "MOV.L      #_ulPortTaskHasDPFPUContext, R14    \n"\
-            "MOV.L      R15, [R14]                          \n"\
-            "CMP        #0, R15                             \n"\
+            "POP        R15                                 \n" \
+            "MOV.L      #_ulPortTaskHasDPFPUContext, R14    \n" \
+            "MOV.L      R15, [R14]                          \n" \
+            "CMP        #0, R15                             \n" \
 
             /* Restore the DPFPU context, if any. */
-            "BEQ.B      __lab2                      \n"\
-            "DPOPM.L    DPSW-DECNT                  \n"\
-            "DPOPM.D    DR0-DR15                    \n"\
-            "__lab2:                                \n"\
+            "BEQ.B      __lab2                      \n" \
+            "DPOPM.L    DPSW-DECNT                  \n" \
+            "DPOPM.D    DR0-DR15                    \n" \
+            "__lab2:                                \n" \
 
         #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 )
-
             /* Restore the DPFPU context, always. */
-            "DPOPM.L    DPSW-DECNT                  \n"\
-            "DPOPM.D    DR0-DR15                    \n"\
+            "DPOPM.L    DPSW-DECNT                  \n" \
+            "DPOPM.D    DR0-DR15                    \n" \
 
         #endif /* if( configUSE_TASK_DPFPU_SUPPORT == 1 ) */
 
-        "POP        R15                         \n"\
+        "POP        R15                         \n" \
 
         /* Accumulator low 32 bits. */
-        "MVTACLO    R15, A0                     \n"\
-        "POP        R15                         \n"\
+        "MVTACLO    R15, A0                     \n" \
+        "POP        R15                         \n" \
 
         /* Accumulator high 32 bits. */
-        "MVTACHI    R15, A0                     \n"\
-        "POP        R15                         \n"\
+        "MVTACHI    R15, A0                     \n" \
+        "POP        R15                         \n" \
 
         /* Accumulator guard. */
-        "MVTACGU    R15, A0                     \n"\
-        "POP        R15                         \n"\
+        "MVTACGU    R15, A0                     \n" \
+        "POP        R15                         \n" \
 
         /* Accumulator low 32 bits. */
-        "MVTACLO    R15, A1                     \n"\
-        "POP        R15                         \n"\
+        "MVTACLO    R15, A1                     \n" \
+        "POP        R15                         \n" \
 
         /* Accumulator high 32 bits. */
-        "MVTACHI    R15, A1                     \n"\
-        "POP        R15                         \n"\
+        "MVTACHI    R15, A1                     \n" \
+        "POP        R15                         \n" \
 
         /* Accumulator guard. */
-        "MVTACGU    R15, A1                     \n"\
-        "POP        R15                         \n"\
-        "MVTC       R15, FPSW                   \n"\
-        "POPM       R1-R15                      \n"\
-        "RTE                                    \n"\
-        "NOP                                    \n"\
+        "MVTACGU    R15, A1                     \n" \
+        "POP        R15                         \n" \
+        "MVTC       R15, FPSW                   \n" \
+        "POPM       R1-R15                      \n" \
+        "RTE                                    \n" \
+        "NOP                                    \n" \
         "NOP                                      "
-        portCDT_NO_PARSE( :: ) "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ), "i" ( configKERNEL_INTERRUPT_PRIORITY )
+        portCDT_NO_PARSE( ::) "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ), "i" ( configKERNEL_INTERRUPT_PRIORITY )
     );
 }
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/RX700v3_DPFPU/portmacro.h b/portable/IAR/RX700v3_DPFPU/portmacro.h
index f8fde2790..2819f62e5 100644
--- a/portable/IAR/RX700v3_DPFPU/portmacro.h
+++ b/portable/IAR/RX700v3_DPFPU/portmacro.h
@@ -28,10 +28,10 @@
 
 
 #ifndef PORTMACRO_H
-    #define PORTMACRO_H
+#define PORTMACRO_H
 
 /* Hardware specifics. */
-    #include <intrinsics.h>
+#include <intrinsics.h>
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
@@ -51,9 +51,9 @@
 
 /* When the FIT configurator or the Smart Configurator is used, platform.h has to be
  * used. */
-    #ifndef configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H
-        #define configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H 0
-    #endif
+#ifndef configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H
+    #define configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H    0
+#endif
 
 /* If configUSE_TASK_DPFPU_SUPPORT is set to 1 (or undefined) then each task will
  * be created without a DPFPU context, and a task must call vTaskUsesDPFPU() before
@@ -61,77 +61,77 @@
  * tasks are created with a DPFPU context by default, and calling vTaskUsesDPFPU() has
  * no effect.  If configUSE_TASK_DPFPU_SUPPORT is set to 0 then tasks never take care
  * of any DPFPU context (even if DPFPU registers are used). */
-    #ifndef configUSE_TASK_DPFPU_SUPPORT
-        #define configUSE_TASK_DPFPU_SUPPORT 1
-    #endif
+#ifndef configUSE_TASK_DPFPU_SUPPORT
+    #define configUSE_TASK_DPFPU_SUPPORT    1
+#endif
 
 /*-----------------------------------------------------------*/
 
 /* Type definitions - these are a bit legacy and not really used now, other than
  * portSTACK_TYPE and portBASE_TYPE. */
-    #define portCHAR          char
-    #define portFLOAT         float
-    #define portDOUBLE        double
-    #define portLONG          long
-    #define portSHORT         short
-    #define portSTACK_TYPE    uint32_t
-    #define portBASE_TYPE     long
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-    typedef portSTACK_TYPE   StackType_t;
-    typedef long             BaseType_t;
-    typedef unsigned long    UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
-    #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-        typedef uint16_t     TickType_t;
-        #define portMAX_DELAY              ( TickType_t ) 0xffff
-    #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-        typedef uint32_t     TickType_t;
-        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
  * not need to be guarded with a critical section. */
-        #define portTICK_TYPE_IS_ATOMIC    1
-    #else
-        #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
-    #endif
+    #define portTICK_TYPE_IS_ATOMIC    1
+#else
+    #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+#endif
 
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-    #define portBYTE_ALIGNMENT    8     /* Could make four, according to manual. */
-    #define portSTACK_GROWTH      -1
-    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-    #define portNOP()    __no_operation()
+#define portBYTE_ALIGNMENT    8         /* Could make four, according to manual. */
+#define portSTACK_GROWTH      -1
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()    __no_operation()
 
 /* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;"
  * where portITU_SWINTR is the location of the software interrupt register
  * (0x000872E0).  Don't rely on the assembler to select a register, so instead
  * save and restore clobbered registers manually. */
-    #define portYIELD()           \
-    __asm volatile                \
-    (                             \
-        "PUSH.L R10                 \n"\
-        "MOV.L  #0x872E0, R10       \n"\
-        "MOV.B  #0x1, [R10]         \n"\
-        "CMP    [R10].UB, R10       \n"\
-        "POP    R10                 \n"\
-        portCDT_NO_PARSE( ::: ) "cc"\
+#define portYIELD()                     \
+    __asm volatile                      \
+    (                                   \
+        "PUSH.L R10                 \n" \
+        "MOV.L  #0x872E0, R10       \n" \
+        "MOV.B  #0x1, [R10]         \n" \
+        "CMP    [R10].UB, R10       \n" \
+        "POP    R10                 \n" \
+        portCDT_NO_PARSE( ::: ) "cc"    \
     )
 
-    #define portYIELD_FROM_ISR( x )                           do { if( ( x ) != pdFALSE ) portYIELD(); } while( 0 )
+#define portYIELD_FROM_ISR( x )    do { if( ( x ) != pdFALSE ) portYIELD( ); } while( 0 )
 
 /* Workaround to reduce errors/warnings caused by e2 studio CDT's INDEXER and CODAN. */
-    #ifdef __CDT_PARSER__
+#ifdef __CDT_PARSER__
     #ifndef __asm
-    #define __asm asm
+        #define __asm    asm
     #endif
     #ifndef __attribute__
-    #define __attribute__( ... )
+        #define __attribute__( ... )
     #endif
     #define portCDT_NO_PARSE( token )
-    #else
-    #define portCDT_NO_PARSE( token ) token
-    #endif
+#else
+    #define portCDT_NO_PARSE( token )    token
+#endif
 
 /* These macros should not be called directly, but through the
  * taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
@@ -142,32 +142,32 @@
  * functions are those that end in FromISR.  FreeRTOS maintains a separate
  * interrupt API to ensure API function and interrupt entry is as fast and as
  * simple as possible. */
-    #define portENABLE_INTERRUPTS()                           __set_interrupt_level( ( uint8_t ) 0 )
-    #ifdef configASSERT
-        #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    configASSERT( ( __get_interrupt_level() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
-        #define portDISABLE_INTERRUPTS()                      if( __get_interrupt_level() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
-    #else
-        #define portDISABLE_INTERRUPTS()                      __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
-    #endif
+#define portENABLE_INTERRUPTS()                           __set_interrupt_level( ( uint8_t ) 0 )
+#ifdef configASSERT
+    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    configASSERT( ( __get_interrupt_level() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+    #define portDISABLE_INTERRUPTS()                      if( __get_interrupt_level() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#else
+    #define portDISABLE_INTERRUPTS()                      __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#endif
 
 /* Critical nesting counts are stored in the TCB. */
-    #define portCRITICAL_NESTING_IN_TCB    ( 1 )
+#define portCRITICAL_NESTING_IN_TCB    ( 1 )
 
 /* The critical nesting functions defined within tasks.c. */
-    extern void vTaskEnterCritical( void );
-    extern void vTaskExitCritical( void );
-    #define portENTER_CRITICAL()    vTaskEnterCritical()
-    #define portEXIT_CRITICAL()     vTaskExitCritical()
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+#define portENTER_CRITICAL()                                           vTaskEnterCritical()
+#define portEXIT_CRITICAL()                                            vTaskExitCritical()
 
 /* As this port allows interrupt nesting... */
-    #define portSET_INTERRUPT_MASK_FROM_ISR()                              __get_interrupt_level(); portDISABLE_INTERRUPTS()
-    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus )    __set_interrupt_level( ( uint8_t ) ( uxSavedInterruptStatus ) )
+#define portSET_INTERRUPT_MASK_FROM_ISR()                              __get_interrupt_level(); portDISABLE_INTERRUPTS()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus )    __set_interrupt_level( ( uint8_t ) ( uxSavedInterruptStatus ) )
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
-    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
 /*-----------------------------------------------------------*/
 
@@ -176,22 +176,23 @@
  * themselves a DPFPU context before using any DPFPU instructions.  If
  * configUSE_TASK_DPFPU_SUPPORT is set to 2 then all tasks will have a DPFPU context
  * by default. */
-    #if( configUSE_TASK_DPFPU_SUPPORT == 1 )
-        void vPortTaskUsesDPFPU( void );
-    #else
+#if ( configUSE_TASK_DPFPU_SUPPORT == 1 )
+    void vPortTaskUsesDPFPU( void );
+#else
+
 /* Each task has a DPFPU context already, so define this function away to
  * nothing to prevent it being called accidentally. */
-        #define vPortTaskUsesDPFPU()
-    #endif
-    #define portTASK_USES_DPFPU() vPortTaskUsesDPFPU()
+    #define vPortTaskUsesDPFPU()
+#endif
+#define portTASK_USES_DPFPU()             vPortTaskUsesDPFPU()
 
 /* Definition to allow compatibility with existing FreeRTOS Demo using flop.c. */
-    #define portTASK_USES_FLOATING_POINT() vPortTaskUsesDPFPU()
+#define portTASK_USES_FLOATING_POINT()    vPortTaskUsesDPFPU()
 
 /* Prevent warnings of undefined behaviour: the order of volatile accesses is
  * undefined - all warnings have been manually checked and are not an issue, and
  * the warnings cannot be prevent by code changes without undesirable effects. */
-    #pragma diag_suppress=Pa082
+#pragma diag_suppress=Pa082
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/IAR/RXv2/port.c b/portable/IAR/RXv2/port.c
index f791f44dc..2c87ba5af 100644
--- a/portable/IAR/RXv2/port.c
+++ b/portable/IAR/RXv2/port.c
@@ -27,8 +27,8 @@
  */
 
 /*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the SH2A port.
- *----------------------------------------------------------*/
+* Implementation of functions defined in portable.h for the SH2A port.
+*----------------------------------------------------------*/
 
 /* Scheduler includes. */
 #include "FreeRTOS.h"
@@ -43,8 +43,8 @@
 /*-----------------------------------------------------------*/
 
 /* Tasks should start with interrupts enabled and in Supervisor mode, therefore
-PSW is set with U and I set, and PM and IPL clear. */
-#define portINITIAL_PSW  ( ( StackType_t ) 0x00030000 )
+ * PSW is set with U and I set, and PM and IPL clear. */
+#define portINITIAL_PSW     ( ( StackType_t ) 0x00030000 )
 #define portINITIAL_FPSW    ( ( StackType_t ) 0x00000100 )
 
 /*-----------------------------------------------------------*/
@@ -63,14 +63,16 @@ __interrupt void vTickISR( void );
 
 /*-----------------------------------------------------------*/
 
-extern void *pxCurrentTCB;
+extern void * pxCurrentTCB;
 
 /*-----------------------------------------------------------*/
 
 /*
  * See header file for description.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
     /* R0 is not included as it is the stack pointer. */
 
@@ -81,8 +83,8 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
     *pxTopOfStack = ( StackType_t ) pxCode;
 
     /* When debugging it can be useful if every register is set to a known
-    value.  Otherwise code space can be saved by just setting the registers
-    that need to be set. */
+     * value.  Otherwise code space can be saved by just setting the registers
+     * that need to be set. */
     #ifdef USE_FULL_REGISTER_INITIALISATION
     {
         pxTopOfStack--;
@@ -115,11 +117,11 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
         *pxTopOfStack = 0x22222222;
         pxTopOfStack--;
     }
-    #else
+    #else /* ifdef USE_FULL_REGISTER_INITIALISATION */
     {
         pxTopOfStack -= 15;
     }
-    #endif
+    #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */
 
     *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
     pxTopOfStack--;
@@ -143,14 +145,14 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
 
 BaseType_t xPortStartScheduler( void )
 {
-extern void vApplicationSetupTimerInterrupt( void );
+    extern void vApplicationSetupTimerInterrupt( void );
 
     /* Use pxCurrentTCB just so it does not get optimised away. */
     if( pxCurrentTCB != NULL )
     {
         /* Call an application function to set up the timer that will generate the
-        tick interrupt.  This way the application can decide which peripheral to
-        use.  A demo application is provided to show a suitable example. */
+         * tick interrupt.  This way the application can decide which peripheral to
+         * use.  A demo application is provided to show a suitable example. */
         vApplicationSetupTimerInterrupt();
 
         /* Enable the software interrupt. */
@@ -178,7 +180,7 @@ __interrupt void vTickISR( void )
     __enable_interrupt();
 
     /* Increment the tick, and perform any processing the new tick value
-    necessitates. */
+     * necessitates. */
     __set_interrupt_level( configMAX_SYSCALL_INTERRUPT_PRIORITY );
     {
         if( xTaskIncrementTick() != pdFALSE )
@@ -193,7 +195,7 @@ __interrupt void vTickISR( void )
 void vPortEndScheduler( void )
 {
     /* Not implemented in ports where there is nothing to return to.
-    Artificially force an assert. */
+     * Artificially force an assert. */
     configASSERT( pxCurrentTCB == NULL );
 }
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/RXv2/portmacro.h b/portable/IAR/RXv2/portmacro.h
index 3f8448448..512a6e594 100644
--- a/portable/IAR/RXv2/portmacro.h
+++ b/portable/IAR/RXv2/portmacro.h
@@ -49,96 +49,96 @@
  */
 
 /* Type definitions - these are a bit legacy and not really used now, other than
-portSTACK_TYPE and portBASE_TYPE. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint32_t
-#define portBASE_TYPE   long
+ * portSTACK_TYPE and portBASE_TYPE. */
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-    not need to be guarded with a critical section. */
-    #define portTICK_TYPE_IS_ATOMIC 1
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+    #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portBYTE_ALIGNMENT          8   /* Could make four, according to manual. */
-#define portSTACK_GROWTH            -1
-#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portNOP()                   __no_operation()
+#define portBYTE_ALIGNMENT    8         /* Could make four, according to manual. */
+#define portSTACK_GROWTH      -1
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()    __no_operation()
 
 /* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;"
-where portITU_SWINTR is the location of the software interrupt register
-(0x000872E0).  Don't rely on the assembler to select a register, so instead
-save and restore clobbered registers manually. */
-#define portYIELD()                         \
-    __asm volatile                          \
-    (                                       \
-        "PUSH.L R10                 \n"     \
-        "MOV.L  #0x872E0, R10       \n"     \
-        "MOV.B  #0x1, [R10]         \n"     \
-        "MOV.L  [R10], R10          \n"     \
-        "POP    R10                 \n"     \
+ * where portITU_SWINTR is the location of the software interrupt register
+ * (0x000872E0).  Don't rely on the assembler to select a register, so instead
+ * save and restore clobbered registers manually. */
+#define portYIELD()                     \
+    __asm volatile                      \
+    (                                   \
+        "PUSH.L R10                 \n" \
+        "MOV.L  #0x872E0, R10       \n" \
+        "MOV.B  #0x1, [R10]         \n" \
+        "MOV.L  [R10], R10          \n" \
+        "POP    R10                 \n" \
     )
 
-#define portYIELD_FROM_ISR( x ) do { if( ( x ) != pdFALSE ) portYIELD(); } while( 0 )
+#define portYIELD_FROM_ISR( x )                           do { if( ( x ) != pdFALSE ) portYIELD( ); } while( 0 )
 
 /* These macros should not be called directly, but through the
-taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
-performed if configASSERT() is defined to ensure an assertion handler does not
-inadvertently attempt to lower the IPL when the call to assert was triggered
-because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
-when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
-functions are those that end in FromISR.  FreeRTOS maintains a separate
-interrupt API to ensure API function and interrupt entry is as fast and as
-simple as possible. */
-#define portENABLE_INTERRUPTS()     __set_interrupt_level( ( uint8_t ) 0 )
+ * taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
+ * performed if configASSERT() is defined to ensure an assertion handler does not
+ * inadvertently attempt to lower the IPL when the call to assert was triggered
+ * because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
+ * when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
+ * functions are those that end in FromISR.  FreeRTOS maintains a separate
+ * interrupt API to ensure API function and interrupt entry is as fast and as
+ * simple as possible. */
+#define portENABLE_INTERRUPTS()                           __set_interrupt_level( ( uint8_t ) 0 )
 #ifdef configASSERT
-    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( __get_interrupt_level() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
-    #define portDISABLE_INTERRUPTS()    if( __get_interrupt_level() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    configASSERT( ( __get_interrupt_level() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+    #define portDISABLE_INTERRUPTS()                      if( __get_interrupt_level() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
 #else
-    #define portDISABLE_INTERRUPTS()    __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+    #define portDISABLE_INTERRUPTS()                      __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
 #endif
 
 /* Critical nesting counts are stored in the TCB. */
-#define portCRITICAL_NESTING_IN_TCB ( 1 )
+#define portCRITICAL_NESTING_IN_TCB    ( 1 )
 
 /* The critical nesting functions defined within tasks.c. */
 extern void vTaskEnterCritical( void );
 extern void vTaskExitCritical( void );
-#define portENTER_CRITICAL()    vTaskEnterCritical()
-#define portEXIT_CRITICAL()     vTaskExitCritical()
+#define portENTER_CRITICAL()                                           vTaskEnterCritical()
+#define portEXIT_CRITICAL()                                            vTaskExitCritical()
 
 /* As this port allows interrupt nesting... */
-#define portSET_INTERRUPT_MASK_FROM_ISR() __get_interrupt_level(); portDISABLE_INTERRUPTS()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) __set_interrupt_level( ( uint8_t ) ( uxSavedInterruptStatus ) )
+#define portSET_INTERRUPT_MASK_FROM_ISR()                              __get_interrupt_level(); portDISABLE_INTERRUPTS()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus )    __set_interrupt_level( ( uint8_t ) ( uxSavedInterruptStatus ) )
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
 /* Prevent warnings of undefined behaviour: the order of volatile accesses is
-undefined - all warnings have been manually checked and are not an issue, and
-the warnings cannot be prevent by code changes without undesirable effects. */
+ * undefined - all warnings have been manually checked and are not an issue, and
+ * the warnings cannot be prevent by code changes without undesirable effects. */
 #pragma diag_suppress=Pa082
 
 /* *INDENT-OFF* */
diff --git a/portable/IAR/STR71x/ISR_Support.h b/portable/IAR/STR71x/ISR_Support.h
index 4651c2d13..d63e908b9 100644
--- a/portable/IAR/STR71x/ISR_Support.h
+++ b/portable/IAR/STR71x/ISR_Support.h
@@ -1,105 +1,151 @@
-;/*
-; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
-; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
-; *
-; * SPDX-License-Identifier: MIT
-; *
-; * Permission is hereby granted, free of charge, to any person obtaining a copy of
-; * this software and associated documentation files (the "Software"), to deal in
-; * the Software without restriction, including without limitation the rights to
-; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
-; * the Software, and to permit persons to whom the Software is furnished to do so,
-; * subject to the following conditions:
-; *
-; * The above copyright notice and this permission notice shall be included in all
-; * copies or substantial portions of the Software.
-; *
-; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-; *
-; * https://www.FreeRTOS.org
-; * https://github.com/FreeRTOS
-; *
-; */
+; /*
+   * ; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+   * ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+   * ; *
+   * ; * SPDX-License-Identifier: MIT
+   * ; *
+   * ; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+   * ; * this software and associated documentation files (the "Software"), to deal in
+   * ; * the Software without restriction, including without limitation the rights to
+   * ; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+   * ; * the Software, and to permit persons to whom the Software is furnished to do so,
+   * ; * subject to the following conditions:
+   * ; *
+   * ; * The above copyright notice and this permission notice shall be included in all
+   * ; * copies or substantial portions of the Software.
+   * ; *
+   * ; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+   * ; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+   * ; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+   * ; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+   * ; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+   * ; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+   * ; *
+   * ; * https://www.FreeRTOS.org
+   * ; * https://github.com/FreeRTOS
+   * ; *
+   * ; */
 
-    EXTERN pxCurrentTCB
-    EXTERN ulCriticalNesting
+EXTERN pxCurrentTCB
+EXTERN ulCriticalNesting
 
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Context save and restore macro definitions
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;
+Context save and restore macro definitions
+;
 
 portSAVE_CONTEXT MACRO
 
-    ; Push R0 as we are going to use the register.
-    STMDB   SP!, {R0}
+;
+Push R0 as we are going to use the register.
+   STMDB SP !, {
+    R0
+}
 
-    ; Set R0 to point to the task stack pointer.
-    STMDB   SP, {SP}^
-    NOP
-    SUB     SP, SP, #4
-    LDMIA   SP!, {R0}
+Set R0 to point to the task stack pointer.
+   STMDB SP, {
+    SP
+}
+^
+NOP
+SUB SP, SP, # 4
+LDMIA SP !, {
+    R0
+}
 
-    ; Push the return address onto the stack.
-    STMDB   R0!, {LR}
+;
+Push the return address onto the stack.
+          STMDB R0 !, {
+           LR
+       }
 
-    ; Now we have saved LR we can use it instead of R0.
-    MOV     LR, R0
+       Now we have saved LR we can use it instead of R0.
+          MOV LR, R0
 
-    ; Pop R0 so we can save it onto the system mode stack.
-    LDMIA   SP!, {R0}
+;
 
-    ; Push all the system mode registers onto the task stack.
-    STMDB   LR, {R0-LR}^
-    NOP
-    SUB     LR, LR, #60
+Pop R0 so we can save it onto the system mode stack.
+   LDMIA SP !, {
+    R0
+}
 
-    ; Push the SPSR onto the task stack.
-    MRS     R0, SPSR
-    STMDB   LR!, {R0}
+Push all the system mode registers onto the task stack.
+   STMDB LR, {
+    R0 - LR
+}
+^
+NOP
+SUB LR, LR, # 60
 
-    LDR     R0, =ulCriticalNesting
-    LDR     R0, [R0]
-    STMDB   LR!, {R0}
+;
+Push the SPSR onto the task stack.
+   MRS R0, SPSR
+STMDB LR !, {
+    R0
+}
 
-    ; Store the new top of stack for the task.
-    LDR     R1, =pxCurrentTCB
-    LDR     R0, [R1]
-    STR     LR, [R0]
+LDR R0, = ulCriticalNesting
+          LDR R0, [ R0 ]
+STMDB LR !, {
+    R0
+}
 
-    ENDM
+Store the new top of stack
+
+for the task.
+   LDR R1, = pxCurrentTCB
+             LDR R0, [ R1 ]
+STR LR, [ R0 ]
+
+ENDM
 
 
 portRESTORE_CONTEXT MACRO
 
-    ; Set the LR to the task stack.
-    LDR     R1, =pxCurrentTCB
-    LDR     R0, [R1]
-    LDR     LR, [R0]
+;
+Set the LR to the task stack.
+   LDR R1, = pxCurrentTCB
+             LDR R0, [ R1 ]
+LDR LR, [ R0 ]
 
-    ; The critical nesting depth is the first item on the stack.
-    ; Load it into the ulCriticalNesting variable.
-    LDR     R0, =ulCriticalNesting
-    LDMFD   LR!, {R1}
-    STR     R1, [R0]
+;
+The critical nesting depth is the first item on the stack.
+   ;
+Load it into the ulCriticalNesting variable.
+   LDR R0, = ulCriticalNesting
+             LDMFD LR !, {
+    R1
+}
 
-    ; Get the SPSR from the stack.
-    LDMFD   LR!, {R0}
-    MSR     SPSR_cxsf, R0
+STR R1, [ R0 ]
 
-    ; Restore all system mode registers for the task.
-    LDMFD   LR, {R0-R14}^
-    NOP
+;
+Get the SPSR from the stack.
+   LDMFD LR !, {
+    R0
+}
+MSR SPSR_cxsf, R0
 
-    ; Restore the return address.
-    LDR     LR, [LR, #+60]
+;
+Restore all system mode registers
 
-    ; And return - correcting the offset in the LR to obtain the
-    ; correct address.
-    SUBS    PC, LR, #4
+for the task.
+   LDMFD LR, {
+    R0 - R14
+}
 
-    ENDM
+^
+NOP
+
+;
+Restore the return address.
+          LDR LR, [ LR, # + 60 ]
+
+;
+
+And return -correcting the offset in the LR to obtain the
+;
+
+correct address.
+   SUBS PC, LR, # 4
+
+ENDM
diff --git a/portable/IAR/STR71x/port.c b/portable/IAR/STR71x/port.c
index a7530e807..bed6278c8 100644
--- a/portable/IAR/STR71x/port.c
+++ b/portable/IAR/STR71x/port.c
@@ -27,9 +27,9 @@
  */
 
 /*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the ST STR71x ARM7
- * port.
- *----------------------------------------------------------*/
+* Implementation of functions defined in portable.h for the ST STR71x ARM7
+* port.
+*----------------------------------------------------------*/
 
 /* Library includes. */
 #include "wdg.h"
@@ -43,14 +43,14 @@
 #include "task.h"
 
 /* Constants required to setup the initial stack. */
-#define portINITIAL_SPSR                ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
-#define portTHUMB_MODE_BIT              ( ( StackType_t ) 0x20 )
-#define portINSTRUCTION_SIZE            ( ( StackType_t ) 4 )
+#define portINITIAL_SPSR           ( ( StackType_t ) 0x1f )      /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT         ( ( StackType_t ) 0x20 )
+#define portINSTRUCTION_SIZE       ( ( StackType_t ) 4 )
 
 /* Constants required to handle critical sections. */
-#define portNO_CRITICAL_NESTING         ( ( uint32_t ) 0 )
+#define portNO_CRITICAL_NESTING    ( ( uint32_t ) 0 )
 
-#define portMICROS_PER_SECOND 1000000
+#define portMICROS_PER_SECOND      1000000
 
 /*-----------------------------------------------------------*/
 
@@ -58,13 +58,13 @@
 static void prvSetupTimerInterrupt( void );
 
 /* ulCriticalNesting will get set to zero when the first task starts.  It
-cannot be initialised to 0 as this will cause interrupts to be enabled
-during the kernel initialisation process. */
+ * cannot be initialised to 0 as this will cause interrupts to be enabled
+ * during the kernel initialisation process. */
 uint32_t ulCriticalNesting = ( uint32_t ) 9999;
 
 /* Tick interrupt routines for cooperative and preemptive operation
-respectively.  The preemptive version is not defined as __irq as it is called
-from an asm wrapper function. */
+ * respectively.  The preemptive version is not defined as __irq as it is called
+ * from an asm wrapper function. */
 __arm __irq void vPortNonPreemptiveTick( void );
 void vPortPreemptiveTick( void );
 
@@ -76,56 +76,58 @@ void vPortPreemptiveTick( void );
  *
  * See header file for description.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
-StackType_t *pxOriginalTOS;
+    StackType_t * pxOriginalTOS;
 
     pxOriginalTOS = pxTopOfStack;
 
     /* To ensure asserts in tasks.c don't fail, although in this case the assert
-    is not really required. */
+     * is not really required. */
     pxTopOfStack--;
 
     /* Setup the initial stack of the task.  The stack is set exactly as
-    expected by the portRESTORE_CONTEXT() macro. */
+     * expected by the portRESTORE_CONTEXT() macro. */
 
     /* First on the stack is the return address - which in this case is the
-    start of the task.  The offset is added to make the return address appear
-    as it would within an IRQ ISR. */
+     * start of the task.  The offset is added to make the return address appear
+     * as it would within an IRQ ISR. */
     *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
     pxTopOfStack--;
 
-    *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */
+    *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa;    /* R14 */
     pxTopOfStack--;
     *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
+    *pxTopOfStack = ( StackType_t ) 0x12121212;    /* R12 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
+    *pxTopOfStack = ( StackType_t ) 0x11111111;    /* R11 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
+    *pxTopOfStack = ( StackType_t ) 0x10101010;    /* R10 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
+    *pxTopOfStack = ( StackType_t ) 0x09090909;    /* R9 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
+    *pxTopOfStack = ( StackType_t ) 0x08080808;    /* R8 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
+    *pxTopOfStack = ( StackType_t ) 0x07070707;    /* R7 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
+    *pxTopOfStack = ( StackType_t ) 0x06060606;    /* R6 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
+    *pxTopOfStack = ( StackType_t ) 0x05050505;    /* R5 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
+    *pxTopOfStack = ( StackType_t ) 0x04040404;    /* R4 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
+    *pxTopOfStack = ( StackType_t ) 0x03030303;    /* R3 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
+    *pxTopOfStack = ( StackType_t ) 0x02020202;    /* R2 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
+    *pxTopOfStack = ( StackType_t ) 0x01010101;    /* R1 */
     pxTopOfStack--;
 
     /* When the task starts is will expect to find the function parameter in
-    R0. */
+     * R0. */
     *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
     pxTopOfStack--;
 
@@ -141,8 +143,8 @@ StackType_t *pxOriginalTOS;
     pxTopOfStack--;
 
     /* Interrupt flags cannot always be stored on the stack and will
-    instead be stored in a variable, which is then saved as part of the
-    tasks context. */
+     * instead be stored in a variable, which is then saved as part of the
+     * tasks context. */
     *pxTopOfStack = portNO_CRITICAL_NESTING;
 
     return pxTopOfStack;
@@ -151,10 +153,10 @@ StackType_t *pxOriginalTOS;
 
 BaseType_t xPortStartScheduler( void )
 {
-extern void vPortStartFirstTask( void );
+    extern void vPortStartFirstTask( void );
 
     /* Start the timer that generates the tick ISR.  Interrupts are disabled
-    here already. */
+     * here already. */
     prvSetupTimerInterrupt();
 
     /* Start the first task. */
@@ -168,17 +170,17 @@ extern void vPortStartFirstTask( void );
 void vPortEndScheduler( void )
 {
     /* It is unlikely that the ARM port will require this function as there
-    is nothing to return to.  */
+     * is nothing to return to.  */
 }
 /*-----------------------------------------------------------*/
 
 /* The cooperative scheduler requires a normal IRQ service routine to
-simply increment the system tick. */
+ * simply increment the system tick. */
 __arm __irq void vPortNonPreemptiveTick( void )
 {
     /* Increment the tick count - which may wake some tasks but as the
-    preemptive scheduler is not being used any woken task is not given
-    processor time no matter what its priority. */
+     * preemptive scheduler is not being used any woken task is not given
+     * processor time no matter what its priority. */
     xTaskIncrementTick();
 
     /* Clear the interrupt in the watchdog and EIC. */
@@ -188,7 +190,7 @@ __arm __irq void vPortNonPreemptiveTick( void )
 /*-----------------------------------------------------------*/
 
 /* This function is called from an asm wrapper, so does not require the __irq
-keyword. */
+ * keyword. */
 void vPortPreemptiveTick( void )
 {
     /* Increment the tick counter. */
@@ -218,7 +220,7 @@ static void prvSetupTimerInterrupt( void )
     WDG_ECITConfig( ENABLE );
 
     /* Start the timer - interrupts are actually disabled at this point so
-    it is safe to do this here. */
+     * it is safe to do this here. */
     WDG_CntOnOffConfig( ENABLE );
 }
 /*-----------------------------------------------------------*/
@@ -228,9 +230,9 @@ __arm __interwork void vPortEnterCritical( void )
     /* Disable interrupts first! */
     __disable_interrupt();
 
-    /* Now interrupts are disabled ulCriticalNesting can be accessed
-    directly.  Increment ulCriticalNesting to keep a count of how many times
-    portENTER_CRITICAL() has been called. */
+    /* Now that interrupts are disabled, ulCriticalNesting can be accessed
+     * directly.  Increment ulCriticalNesting to keep a count of how many times
+     * portENTER_CRITICAL() has been called. */
     ulCriticalNesting++;
 }
 /*-----------------------------------------------------------*/
@@ -243,7 +245,7 @@ __arm __interwork void vPortExitCritical( void )
         ulCriticalNesting--;
 
         /* If the nesting level has reached zero then interrupts should be
-        re-enabled. */
+         * re-enabled. */
         if( ulCriticalNesting == portNO_CRITICAL_NESTING )
         {
             __enable_interrupt();
diff --git a/portable/IAR/STR71x/portmacro.h b/portable/IAR/STR71x/portmacro.h
index 1fbadff3e..7fa132cd9 100644
--- a/portable/IAR/STR71x/portmacro.h
+++ b/portable/IAR/STR71x/portmacro.h
@@ -50,24 +50,24 @@
 
 
 /* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint32_t
-#define portBASE_TYPE   long
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
-#elif ( configTICK_TYPE_WIDTH_IN_BITS  == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t             TickType_t;
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+    typedef uint32_t     TickType_t;
     #define portMAX_DELAY    ( TickType_t ) 0xffffffffUL
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -75,11 +75,11 @@ typedef unsigned long UBaseType_t;
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portSTACK_GROWTH            ( -1 )
-#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT          8
-#define portYIELD()                 asm ( "SWI 0" )
-#define portNOP()                   asm ( "NOP" )
+#define portSTACK_GROWTH      ( -1 )
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT    8
+#define portYIELD()    asm ( "SWI 0" )
+#define portNOP()      asm ( "NOP" )
 /*-----------------------------------------------------------*/
 
 /* Critical section handling. */
@@ -95,27 +95,27 @@ __arm __interwork void vPortExitCritical( void );
 /*-----------------------------------------------------------*/
 
 /* Task utilities. */
-#define portEND_SWITCHING_ISR( xSwitchRequired )    \
-{                                                   \
-extern void vTaskSwitchContext( void );             \
-                                                    \
-    if( xSwitchRequired )                           \
-    {                                               \
-        vTaskSwitchContext();                       \
-    }                                               \
-}
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+    {                                            \
+        extern void vTaskSwitchContext( void );  \
+                                                 \
+        if( xSwitchRequired )                    \
+        {                                        \
+            vTaskSwitchContext();                \
+        }                                        \
+    }
 /*-----------------------------------------------------------*/
 
 /* EIC utilities. */
-#define portEIC_CICR_ADDR       *( ( uint32_t * ) 0xFFFFF804 )
-#define portEIC_IPR_ADDR        *( ( uint32_t * ) 0xFFFFF840 )
-#define portCLEAR_EIC()         portEIC_IPR_ADDR = 0x01 << portEIC_CICR_ADDR
+#define portEIC_CICR_ADDR    *( ( uint32_t * ) 0xFFFFF804 )
+#define portEIC_IPR_ADDR     *( ( uint32_t * ) 0xFFFFF840 )
+#define portCLEAR_EIC()    portEIC_IPR_ADDR = 0x01 << portEIC_CICR_ADDR
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/IAR/STR75x/ISR_Support.h b/portable/IAR/STR75x/ISR_Support.h
index 4651c2d13..d63e908b9 100644
--- a/portable/IAR/STR75x/ISR_Support.h
+++ b/portable/IAR/STR75x/ISR_Support.h
@@ -1,105 +1,151 @@
-;/*
-; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
-; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
-; *
-; * SPDX-License-Identifier: MIT
-; *
-; * Permission is hereby granted, free of charge, to any person obtaining a copy of
-; * this software and associated documentation files (the "Software"), to deal in
-; * the Software without restriction, including without limitation the rights to
-; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
-; * the Software, and to permit persons to whom the Software is furnished to do so,
-; * subject to the following conditions:
-; *
-; * The above copyright notice and this permission notice shall be included in all
-; * copies or substantial portions of the Software.
-; *
-; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-; *
-; * https://www.FreeRTOS.org
-; * https://github.com/FreeRTOS
-; *
-; */
+; /*
+   * ; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+   * ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+   * ; *
+   * ; * SPDX-License-Identifier: MIT
+   * ; *
+   * ; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+   * ; * this software and associated documentation files (the "Software"), to deal in
+   * ; * the Software without restriction, including without limitation the rights to
+   * ; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+   * ; * the Software, and to permit persons to whom the Software is furnished to do so,
+   * ; * subject to the following conditions:
+   * ; *
+   * ; * The above copyright notice and this permission notice shall be included in all
+   * ; * copies or substantial portions of the Software.
+   * ; *
+   * ; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+   * ; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+   * ; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+   * ; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+   * ; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+   * ; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+   * ; *
+   * ; * https://www.FreeRTOS.org
+   * ; * https://github.com/FreeRTOS
+   * ; *
+   * ; */
 
-    EXTERN pxCurrentTCB
-    EXTERN ulCriticalNesting
+EXTERN pxCurrentTCB
+EXTERN ulCriticalNesting
 
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Context save and restore macro definitions
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;
+Context save and restore macro definitions
+;
 
 portSAVE_CONTEXT MACRO
 
-    ; Push R0 as we are going to use the register.
-    STMDB   SP!, {R0}
+;
+Push R0 as we are going to use the register.
+   STMDB SP !, {
+    R0
+}
 
-    ; Set R0 to point to the task stack pointer.
-    STMDB   SP, {SP}^
-    NOP
-    SUB     SP, SP, #4
-    LDMIA   SP!, {R0}
+Set R0 to point to the task stack pointer.
+   STMDB SP, {
+    SP
+}
+^
+NOP
+SUB SP, SP, # 4
+LDMIA SP !, {
+    R0
+}
 
-    ; Push the return address onto the stack.
-    STMDB   R0!, {LR}
+;
+Push the return address onto the stack.
+          STMDB R0 !, {
+           LR
+       }
 
-    ; Now we have saved LR we can use it instead of R0.
-    MOV     LR, R0
+       Now we have saved LR we can use it instead of R0.
+          MOV LR, R0
 
-    ; Pop R0 so we can save it onto the system mode stack.
-    LDMIA   SP!, {R0}
+;
 
-    ; Push all the system mode registers onto the task stack.
-    STMDB   LR, {R0-LR}^
-    NOP
-    SUB     LR, LR, #60
+Pop R0 so we can save it onto the system mode stack.
+   LDMIA SP !, {
+    R0
+}
 
-    ; Push the SPSR onto the task stack.
-    MRS     R0, SPSR
-    STMDB   LR!, {R0}
+Push all the system mode registers onto the task stack.
+   STMDB LR, {
+    R0 - LR
+}
+^
+NOP
+SUB LR, LR, # 60
 
-    LDR     R0, =ulCriticalNesting
-    LDR     R0, [R0]
-    STMDB   LR!, {R0}
+;
+Push the SPSR onto the task stack.
+   MRS R0, SPSR
+STMDB LR !, {
+    R0
+}
 
-    ; Store the new top of stack for the task.
-    LDR     R1, =pxCurrentTCB
-    LDR     R0, [R1]
-    STR     LR, [R0]
+LDR R0, = ulCriticalNesting
+          LDR R0, [ R0 ]
+STMDB LR !, {
+    R0
+}
 
-    ENDM
+Store the new top of stack
+
+for the task.
+   LDR R1, = pxCurrentTCB
+             LDR R0, [ R1 ]
+STR LR, [ R0 ]
+
+ENDM
 
 
 portRESTORE_CONTEXT MACRO
 
-    ; Set the LR to the task stack.
-    LDR     R1, =pxCurrentTCB
-    LDR     R0, [R1]
-    LDR     LR, [R0]
+;
+Set the LR to the task stack.
+   LDR R1, = pxCurrentTCB
+             LDR R0, [ R1 ]
+LDR LR, [ R0 ]
 
-    ; The critical nesting depth is the first item on the stack.
-    ; Load it into the ulCriticalNesting variable.
-    LDR     R0, =ulCriticalNesting
-    LDMFD   LR!, {R1}
-    STR     R1, [R0]
+;
+The critical nesting depth is the first item on the stack.
+   ;
+Load it into the ulCriticalNesting variable.
+   LDR R0, = ulCriticalNesting
+             LDMFD LR !, {
+    R1
+}
 
-    ; Get the SPSR from the stack.
-    LDMFD   LR!, {R0}
-    MSR     SPSR_cxsf, R0
+STR R1, [ R0 ]
 
-    ; Restore all system mode registers for the task.
-    LDMFD   LR, {R0-R14}^
-    NOP
+;
+Get the SPSR from the stack.
+   LDMFD LR !, {
+    R0
+}
+MSR SPSR_cxsf, R0
 
-    ; Restore the return address.
-    LDR     LR, [LR, #+60]
+;
+Restore all system mode registers
 
-    ; And return - correcting the offset in the LR to obtain the
-    ; correct address.
-    SUBS    PC, LR, #4
+for the task.
+   LDMFD LR, {
+    R0 - R14
+}
 
-    ENDM
+^
+NOP
+
+;
+Restore the return address.
+          LDR LR, [ LR, # + 60 ]
+
+;
+
+And return -correcting the offset in the LR to obtain the
+;
+
+correct address.
+   SUBS PC, LR, # 4
+
+ENDM
diff --git a/portable/IAR/STR75x/port.c b/portable/IAR/STR75x/port.c
index 4286a328b..756ba06f3 100644
--- a/portable/IAR/STR75x/port.c
+++ b/portable/IAR/STR75x/port.c
@@ -27,9 +27,9 @@
  */
 
 /*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the ST STR75x ARM7
- * port.
- *----------------------------------------------------------*/
+* Implementation of functions defined in portable.h for the ST STR75x ARM7
+* port.
+*----------------------------------------------------------*/
 
 /* Library includes. */
 #include "75x_tb.h"
@@ -40,14 +40,14 @@
 #include "task.h"
 
 /* Constants required to setup the initial stack. */
-#define portINITIAL_SPSR                ( ( StackType_t ) 0x3f ) /* System mode, THUMB mode, interrupts enabled. */
-#define portINSTRUCTION_SIZE            ( ( StackType_t ) 4 )
+#define portINITIAL_SPSR           ( ( StackType_t ) 0x3f )      /* System mode, THUMB mode, interrupts enabled. */
+#define portINSTRUCTION_SIZE       ( ( StackType_t ) 4 )
 
 /* Constants required to handle critical sections. */
-#define portNO_CRITICAL_NESTING         ( ( uint32_t ) 0 )
+#define portNO_CRITICAL_NESTING    ( ( uint32_t ) 0 )
 
 /* Prescale used on the timer clock when calculating the tick period. */
-#define portPRESCALE 20
+#define portPRESCALE               20
 
 
 /*-----------------------------------------------------------*/
@@ -56,8 +56,8 @@
 static void prvSetupTimerInterrupt( void );
 
 /* ulCriticalNesting will get set to zero when the first task starts.  It
-cannot be initialised to 0 as this will cause interrupts to be enabled
-during the kernel initialisation process. */
+ * cannot be initialised to 0 as this will cause interrupts to be enabled
+ * during the kernel initialisation process. */
 uint32_t ulCriticalNesting = ( uint32_t ) 9999;
 
 /* Tick interrupt routines for preemptive operation. */
@@ -71,56 +71,58 @@ __arm void vPortPreemptiveTick( void );
  *
  * See header file for description.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
-StackType_t *pxOriginalTOS;
+    StackType_t * pxOriginalTOS;
 
     pxOriginalTOS = pxTopOfStack;
 
     /* To ensure asserts in tasks.c don't fail, although in this case the assert
-    is not really required. */
+     * is not really required. */
     pxTopOfStack--;
 
     /* Setup the initial stack of the task.  The stack is set exactly as
-    expected by the portRESTORE_CONTEXT() macro. */
+     * expected by the portRESTORE_CONTEXT() macro. */
 
     /* First on the stack is the return address - which in this case is the
-    start of the task.  The offset is added to make the return address appear
-    as it would within an IRQ ISR. */
+     * start of the task.  The offset is added to make the return address appear
+     * as it would within an IRQ ISR. */
     *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
     pxTopOfStack--;
 
-    *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */
+    *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa;    /* R14 */
     pxTopOfStack--;
     *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
+    *pxTopOfStack = ( StackType_t ) 0x12121212;    /* R12 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
+    *pxTopOfStack = ( StackType_t ) 0x11111111;    /* R11 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
+    *pxTopOfStack = ( StackType_t ) 0x10101010;    /* R10 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
+    *pxTopOfStack = ( StackType_t ) 0x09090909;    /* R9 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
+    *pxTopOfStack = ( StackType_t ) 0x08080808;    /* R8 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
+    *pxTopOfStack = ( StackType_t ) 0x07070707;    /* R7 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
+    *pxTopOfStack = ( StackType_t ) 0x06060606;    /* R6 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
+    *pxTopOfStack = ( StackType_t ) 0x05050505;    /* R5 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
+    *pxTopOfStack = ( StackType_t ) 0x04040404;    /* R4 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
+    *pxTopOfStack = ( StackType_t ) 0x03030303;    /* R3 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
+    *pxTopOfStack = ( StackType_t ) 0x02020202;    /* R2 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
+    *pxTopOfStack = ( StackType_t ) 0x01010101;    /* R1 */
     pxTopOfStack--;
 
     /* When the task starts is will expect to find the function parameter in
-    R0. */
+     * R0. */
     *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
     pxTopOfStack--;
 
@@ -129,8 +131,8 @@ StackType_t *pxOriginalTOS;
     pxTopOfStack--;
 
     /* Interrupt flags cannot always be stored on the stack and will
-    instead be stored in a variable, which is then saved as part of the
-    tasks context. */
+     * instead be stored in a variable, which is then saved as part of the
+     * tasks context. */
     *pxTopOfStack = portNO_CRITICAL_NESTING;
 
     return pxTopOfStack;
@@ -139,10 +141,10 @@ StackType_t *pxOriginalTOS;
 
 BaseType_t xPortStartScheduler( void )
 {
-extern void vPortStartFirstTask( void );
+    extern void vPortStartFirstTask( void );
 
     /* Start the timer that generates the tick ISR.  Interrupts are disabled
-    here already. */
+     * here already. */
     prvSetupTimerInterrupt();
 
     /* Start the first task. */
@@ -156,7 +158,7 @@ extern void vPortStartFirstTask( void );
 void vPortEndScheduler( void )
 {
     /* It is unlikely that the ARM port will require this function as there
-    is nothing to return to.  */
+     * is nothing to return to.  */
 }
 /*-----------------------------------------------------------*/
 
@@ -175,30 +177,30 @@ __arm void vPortPreemptiveTick( void )
 
 static void prvSetupTimerInterrupt( void )
 {
-EIC_IRQInitTypeDef  EIC_IRQInitStructure;
-TB_InitTypeDef      TB_InitStructure;
+    EIC_IRQInitTypeDef EIC_IRQInitStructure;
+    TB_InitTypeDef TB_InitStructure;
 
     /* Setup the EIC for the TB. */
     EIC_IRQInitStructure.EIC_IRQChannelCmd = ENABLE;
     EIC_IRQInitStructure.EIC_IRQChannel = TB_IRQChannel;
     EIC_IRQInitStructure.EIC_IRQChannelPriority = 1;
-    EIC_IRQInit(&EIC_IRQInitStructure);
+    EIC_IRQInit( &EIC_IRQInitStructure );
 
     /* Setup the TB for the generation of the tick interrupt. */
     TB_InitStructure.TB_Mode = TB_Mode_Timing;
     TB_InitStructure.TB_CounterMode = TB_CounterMode_Down;
     TB_InitStructure.TB_Prescaler = portPRESCALE - 1;
     TB_InitStructure.TB_AutoReload = ( ( configCPU_CLOCK_HZ / portPRESCALE ) / configTICK_RATE_HZ );
-    TB_Init(&TB_InitStructure);
+    TB_Init( &TB_InitStructure );
 
     /* Enable TB Update interrupt */
-    TB_ITConfig(TB_IT_Update, ENABLE);
+    TB_ITConfig( TB_IT_Update, ENABLE );
 
     /* Clear TB Update interrupt pending bit */
-    TB_ClearITPendingBit(TB_IT_Update);
+    TB_ClearITPendingBit( TB_IT_Update );
 
     /* Enable TB */
-    TB_Cmd(ENABLE);
+    TB_Cmd( ENABLE );
 }
 /*-----------------------------------------------------------*/
 
@@ -207,9 +209,9 @@ __arm __interwork void vPortEnterCritical( void )
     /* Disable interrupts first! */
     __disable_interrupt();
 
-    /* Now interrupts are disabled ulCriticalNesting can be accessed
-    directly.  Increment ulCriticalNesting to keep a count of how many times
-    portENTER_CRITICAL() has been called. */
+    /* Now that interrupts are disabled, ulCriticalNesting can be accessed
+     * directly.  Increment ulCriticalNesting to keep a count of how many times
+     * portENTER_CRITICAL() has been called. */
     ulCriticalNesting++;
 }
 /*-----------------------------------------------------------*/
@@ -222,7 +224,7 @@ __arm __interwork void vPortExitCritical( void )
         ulCriticalNesting--;
 
         /* If the nesting level has reached zero then interrupts should be
-        re-enabled. */
+         * re-enabled. */
         if( ulCriticalNesting == portNO_CRITICAL_NESTING )
         {
             __enable_interrupt();
diff --git a/portable/IAR/STR75x/portmacro.h b/portable/IAR/STR75x/portmacro.h
index 94a7b72ed..edbddd4d3 100644
--- a/portable/IAR/STR75x/portmacro.h
+++ b/portable/IAR/STR75x/portmacro.h
@@ -49,24 +49,24 @@
 /* *INDENT-ON* */
 
 /* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint32_t
-#define portBASE_TYPE   long
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
-#elif ( configTICK_TYPE_WIDTH_IN_BITS  == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t             TickType_t;
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+    typedef uint32_t     TickType_t;
     #define portMAX_DELAY    ( TickType_t ) 0xffffffffUL
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -74,11 +74,11 @@ typedef unsigned long UBaseType_t;
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portSTACK_GROWTH            ( -1 )
-#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT          8
-#define portYIELD()                 asm ( "SWI 0" )
-#define portNOP()                   asm ( "NOP" )
+#define portSTACK_GROWTH      ( -1 )
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT    8
+#define portYIELD()    asm ( "SWI 0" )
+#define portNOP()      asm ( "NOP" )
 /*-----------------------------------------------------------*/
 
 /* Critical section handling. */
@@ -92,21 +92,21 @@ __arm __interwork void vPortExitCritical( void );
 /*-----------------------------------------------------------*/
 
 /* Task utilities. */
-#define portEND_SWITCHING_ISR( xSwitchRequired )    \
-{                                                   \
-extern void vTaskSwitchContext( void );             \
-                                                    \
-    if( xSwitchRequired )                           \
-    {                                               \
-        vTaskSwitchContext();                       \
-    }                                               \
-}
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+    {                                            \
+        extern void vTaskSwitchContext( void );  \
+                                                 \
+        if( xSwitchRequired )                    \
+        {                                        \
+            vTaskSwitchContext();                \
+        }                                        \
+    }
 /*-----------------------------------------------------------*/
 
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/IAR/STR91x/ISR_Support.h b/portable/IAR/STR91x/ISR_Support.h
index 5142c7c56..c206a495b 100644
--- a/portable/IAR/STR91x/ISR_Support.h
+++ b/portable/IAR/STR91x/ISR_Support.h
@@ -26,80 +26,126 @@
  *
  */
 
-    EXTERN pxCurrentTCB
-    EXTERN ulCriticalNesting
+EXTERN pxCurrentTCB
+EXTERN ulCriticalNesting
 
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Context save and restore macro definitions
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;
+Context save and restore macro definitions
+;
 
 portSAVE_CONTEXT MACRO
 
-    ; Push R0 as we are going to use the register.
-    STMDB   SP!, {R0}
+;
+Push R0 as we are going to use the register.
+   STMDB SP !, {
+    R0
+}
 
-    ; Set R0 to point to the task stack pointer.
-    STMDB   SP, {SP}^
-    NOP
-    SUB     SP, SP, #4
-    LDMIA   SP!, {R0}
+Set R0 to point to the task stack pointer.
+   STMDB SP, {
+    SP
+}
+^
+NOP
+SUB SP, SP, # 4
+LDMIA SP !, {
+    R0
+}
 
-    ; Push the return address onto the stack.
-    STMDB   R0!, {LR}
+;
+Push the return address onto the stack.
+          STMDB R0 !, {
+           LR
+       }
 
-    ; Now we have saved LR we can use it instead of R0.
-    MOV     LR, R0
+       Now we have saved LR we can use it instead of R0.
+          MOV LR, R0
 
-    ; Pop R0 so we can save it onto the system mode stack.
-    LDMIA   SP!, {R0}
+;
 
-    ; Push all the system mode registers onto the task stack.
-    STMDB   LR, {R0-LR}^
-    NOP
-    SUB     LR, LR, #60
+Pop R0 so we can save it onto the system mode stack.
+   LDMIA SP !, {
+    R0
+}
 
-    ; Push the SPSR onto the task stack.
-    MRS     R0, SPSR
-    STMDB   LR!, {R0}
+Push all the system mode registers onto the task stack.
+   STMDB LR, {
+    R0 - LR
+}
+^
+NOP
+SUB LR, LR, # 60
 
-    LDR     R0, =ulCriticalNesting
-    LDR     R0, [R0]
-    STMDB   LR!, {R0}
+;
+Push the SPSR onto the task stack.
+   MRS R0, SPSR
+STMDB LR !, {
+    R0
+}
 
-    ; Store the new top of stack for the task.
-    LDR     R1, =pxCurrentTCB
-    LDR     R0, [R1]
-    STR     LR, [R0]
+LDR R0, = ulCriticalNesting
+          LDR R0, [ R0 ]
+STMDB LR !, {
+    R0
+}
 
-    ENDM
+Store the new top of stack
+
+for the task.
+   LDR R1, = pxCurrentTCB
+             LDR R0, [ R1 ]
+STR LR, [ R0 ]
+
+ENDM
 
 
 portRESTORE_CONTEXT MACRO
 
-    ; Set the LR to the task stack.
-    LDR     R1, =pxCurrentTCB
-    LDR     R0, [R1]
-    LDR     LR, [R0]
+;
+Set the LR to the task stack.
+   LDR R1, = pxCurrentTCB
+             LDR R0, [ R1 ]
+LDR LR, [ R0 ]
 
-    ; The critical nesting depth is the first item on the stack.
-    ; Load it into the ulCriticalNesting variable.
-    LDR     R0, =ulCriticalNesting
-    LDMFD   LR!, {R1}
-    STR     R1, [R0]
+;
+The critical nesting depth is the first item on the stack.
+   ;
+Load it into the ulCriticalNesting variable.
+   LDR R0, = ulCriticalNesting
+             LDMFD LR !, {
+    R1
+}
 
-    ; Get the SPSR from the stack.
-    LDMFD   LR!, {R0}
-    MSR     SPSR_cxsf, R0
+STR R1, [ R0 ]
 
-    ; Restore all system mode registers for the task.
-    LDMFD   LR, {R0-R14}^
-    NOP
+;
+Get the SPSR from the stack.
+   LDMFD LR !, {
+    R0
+}
+MSR SPSR_cxsf, R0
 
-    ; Restore the return address.
-    LDR     LR, [LR, #+60]
+;
+Restore all system mode registers
 
-    ; And return - correcting the offset in the LR to obtain the
-    ; correct address.
-    SUBS    PC, LR, #4
+for the task.
+   LDMFD LR, {
+    R0 - R14
+}
 
-    ENDM
+^
+NOP
+
+;
+Restore the return address.
+          LDR LR, [ LR, # + 60 ]
+
+;
+
+And return -correcting the offset in the LR to obtain the
+;
+
+correct address.
+   SUBS PC, LR, # 4
+
+ENDM
diff --git a/portable/IAR/STR91x/port.c b/portable/IAR/STR91x/port.c
index 8a089e243..8dd208016 100644
--- a/portable/IAR/STR91x/port.c
+++ b/portable/IAR/STR91x/port.c
@@ -27,9 +27,9 @@
  */
 
 /*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the ST STR91x ARM9
- * port.
- *----------------------------------------------------------*/
+* Implementation of functions defined in portable.h for the ST STR91x ARM9
+* port.
+*----------------------------------------------------------*/
 
 /* Library includes. */
 #include "91x_lib.h"
@@ -48,18 +48,18 @@
 
 /* Constants required to setup the initial stack. */
 #ifndef _RUN_TASK_IN_ARM_MODE_
-    #define portINITIAL_SPSR            ( ( StackType_t ) 0x3f ) /* System mode, THUMB mode, interrupts enabled. */
+    #define portINITIAL_SPSR       ( ( StackType_t ) 0x3f )      /* System mode, THUMB mode, interrupts enabled. */
 #else
-    #define portINITIAL_SPSR            ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+    #define portINITIAL_SPSR       ( ( StackType_t ) 0x1f )      /* System mode, ARM mode, interrupts enabled. */
 #endif
 
-#define portINSTRUCTION_SIZE            ( ( StackType_t ) 4 )
+#define portINSTRUCTION_SIZE       ( ( StackType_t ) 4 )
 
 /* Constants required to handle critical sections. */
-#define portNO_CRITICAL_NESTING         ( ( uint32_t ) 0 )
+#define portNO_CRITICAL_NESTING    ( ( uint32_t ) 0 )
 
 #ifndef abs
-    #define abs(x) ((x)>0 ? (x) : -(x))
+    #define abs( x )    ( ( x ) > 0 ? ( x ) : -( x ) )
 #endif
 
 /**
@@ -74,14 +74,14 @@
  * }
  *
  */
-#define TOGGLE_LED(port,pin)                                    \
-    if ( ((((port)->DR[(pin)<<2])) & (pin)) != Bit_RESET )      \
-    {                                                           \
-        (port)->DR[(pin) <<2] = 0x00;                           \
-    }                                                           \
-    else                                                        \
-    {                                                           \
-        (port)->DR[(pin) <<2] = (pin);                          \
+#define TOGGLE_LED( port, pin )                                           \
+    if( ( ( ( ( port )->DR[ ( pin ) << 2 ] ) ) & ( pin ) ) != Bit_RESET ) \
+    {                                                                     \
+        ( port )->DR[ ( pin ) << 2 ] = 0x00;                              \
+    }                                                                     \
+    else                                                                  \
+    {                                                                     \
+        ( port )->DR[ ( pin ) << 2 ] = ( pin );                           \
     }
 
 
@@ -91,13 +91,13 @@
 static void prvSetupTimerInterrupt( void );
 
 /* ulCriticalNesting will get set to zero when the first task starts.  It
-cannot be initialised to 0 as this will cause interrupts to be enabled
-during the kernel initialisation process. */
+ * cannot be initialised to 0 as this will cause interrupts to be enabled
+ * during the kernel initialisation process. */
 uint32_t ulCriticalNesting = ( uint32_t ) 9999;
 
 /* Tick interrupt routines for cooperative and preemptive operation
-respectively.  The preemptive version is not defined as __irq as it is called
-from an asm wrapper function. */
+ * respectively.  The preemptive version is not defined as __irq as it is called
+ * from an asm wrapper function. */
 void WDG_IRQHandler( void );
 
 /* VIC interrupt default handler. */
@@ -116,56 +116,58 @@ static void prvDefaultHandler( void );
  *
  * See header file for description.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
-    StackType_t *pxOriginalTOS;
+    StackType_t * pxOriginalTOS;
 
     pxOriginalTOS = pxTopOfStack;
 
     /* To ensure asserts in tasks.c don't fail, although in this case the assert
-    is not really required. */
+     * is not really required. */
     pxTopOfStack--;
 
     /* Setup the initial stack of the task.  The stack is set exactly as
-    expected by the portRESTORE_CONTEXT() macro. */
+     * expected by the portRESTORE_CONTEXT() macro. */
 
     /* First on the stack is the return address - which in this case is the
-    start of the task.  The offset is added to make the return address appear
-    as it would within an IRQ ISR. */
+     * start of the task.  The offset is added to make the return address appear
+     * as it would within an IRQ ISR. */
     *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
     pxTopOfStack--;
 
-    *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */
+    *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa;    /* R14 */
     pxTopOfStack--;
     *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
+    *pxTopOfStack = ( StackType_t ) 0x12121212;    /* R12 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
+    *pxTopOfStack = ( StackType_t ) 0x11111111;    /* R11 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
+    *pxTopOfStack = ( StackType_t ) 0x10101010;    /* R10 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
+    *pxTopOfStack = ( StackType_t ) 0x09090909;    /* R9 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
+    *pxTopOfStack = ( StackType_t ) 0x08080808;    /* R8 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
+    *pxTopOfStack = ( StackType_t ) 0x07070707;    /* R7 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
+    *pxTopOfStack = ( StackType_t ) 0x06060606;    /* R6 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
+    *pxTopOfStack = ( StackType_t ) 0x05050505;    /* R5 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
+    *pxTopOfStack = ( StackType_t ) 0x04040404;    /* R4 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
+    *pxTopOfStack = ( StackType_t ) 0x03030303;    /* R3 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
+    *pxTopOfStack = ( StackType_t ) 0x02020202;    /* R2 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
+    *pxTopOfStack = ( StackType_t ) 0x01010101;    /* R1 */
     pxTopOfStack--;
 
     /* When the task starts is will expect to find the function parameter in
-    R0. */
+     * R0. */
     *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
     pxTopOfStack--;
 
@@ -174,8 +176,8 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
     pxTopOfStack--;
 
     /* Interrupt flags cannot always be stored on the stack and will
-    instead be stored in a variable, which is then saved as part of the
-    tasks context. */
+     * instead be stored in a variable, which is then saved as part of the
+     * tasks context. */
     *pxTopOfStack = portNO_CRITICAL_NESTING;
 
     return pxTopOfStack;
@@ -184,10 +186,10 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
 
 BaseType_t xPortStartScheduler( void )
 {
-extern void vPortStartFirstTask( void );
+    extern void vPortStartFirstTask( void );
 
     /* Start the timer that generates the tick ISR.  Interrupts are disabled
-    here already. */
+     * here already. */
     prvSetupTimerInterrupt();
 
     /* Start the first task. */
@@ -201,41 +203,49 @@ extern void vPortStartFirstTask( void );
 void vPortEndScheduler( void )
 {
     /* It is unlikely that the ARM port will require this function as there
-    is nothing to return to.  */
+     * is nothing to return to.  */
 }
 /*-----------------------------------------------------------*/
 
 /* This function is called from an asm wrapper, so does not require the __irq
-keyword. */
+ * keyword. */
 #if configUSE_WATCHDOG_TICK == 1
 
-    static void prvFindFactors(u32 n, u16 *a, u32 *b)
+    static void prvFindFactors( u32 n,
+                                u16 * a,
+                                u32 * b )
     {
         /* This function is copied from the ST STR7 library and is
-        copyright STMicroelectronics.  Reproduced with permission. */
+         * copyright STMicroelectronics.  Reproduced with permission. */
 
         u32 b0;
         u16 a0;
-        int32_t err, err_min=n;
+        int32_t err, err_min = n;
 
-        *a = a0 = ((n-1)/65536ul) + 1;
+        *a = a0 = ( ( n - 1 ) / 65536ul ) + 1;
         *b = b0 = n / *a;
 
-        for (; *a <= 256; (*a)++)
+        for( ; *a <= 256; ( *a )++ )
         {
             *b = n / *a;
-            err = (int32_t)*a * (int32_t)*b - (int32_t)n;
-            if (abs(err) > (*a / 2))
+            err = ( int32_t ) *a * ( int32_t ) *b - ( int32_t ) n;
+
+            if( abs( err ) > ( *a / 2 ) )
             {
-                (*b)++;
-                err = (int32_t)*a * (int32_t)*b - (int32_t)n;
+                ( *b )++;
+                err = ( int32_t ) *a * ( int32_t ) *b - ( int32_t ) n;
             }
-            if (abs(err) < abs(err_min))
+
+            if( abs( err ) < abs( err_min ) )
             {
                 err_min = err;
                 a0 = *a;
                 b0 = *b;
-                if (err == 0) break;
+
+                if( err == 0 )
+                {
+                    break;
+                }
             }
         }
 
@@ -246,21 +256,21 @@ keyword. */
 
     static void prvSetupTimerInterrupt( void )
     {
-    WDG_InitTypeDef xWdg;
-    uint16_t a;
-    uint32_t n = configCPU_PERIPH_HZ / configTICK_RATE_HZ, b;
+        WDG_InitTypeDef xWdg;
+        uint16_t a;
+        uint32_t n = configCPU_PERIPH_HZ / configTICK_RATE_HZ, b;
 
         /* Configure the watchdog as a free running timer that generates a
-        periodic interrupt. */
+         * periodic interrupt. */
 
         SCU_APBPeriphClockConfig( __WDG, ENABLE );
         WDG_DeInit();
-        WDG_StructInit(&xWdg);
+        WDG_StructInit( &xWdg );
         prvFindFactors( n, &a, &b );
         xWdg.WDG_Prescaler = a - 1;
         xWdg.WDG_Preload = b - 1;
         WDG_Init( &xWdg );
-        WDG_ITConfig(ENABLE);
+        WDG_ITConfig( ENABLE );
 
         /* Configure the VIC for the WDG interrupt. */
         VIC_Config( WDG_ITLine, VIC_IRQ, 10 );
@@ -270,7 +280,7 @@ keyword. */
         VIC0->DVAR = ( uint32_t ) prvDefaultHandler;
         VIC1->DVAR = ( uint32_t ) prvDefaultHandler;
 
-        WDG_Cmd(ENABLE);
+        WDG_Cmd( ENABLE );
     }
     /*-----------------------------------------------------------*/
 
@@ -289,36 +299,44 @@ keyword. */
         }
     }
 
-#else
+#else /* if configUSE_WATCHDOG_TICK == 1 */
 
-    static void prvFindFactors(u32 n, u8 *a, u16 *b)
+    static void prvFindFactors( u32 n,
+                                u8 * a,
+                                u16 * b )
     {
         /* This function is copied from the ST STR7 library and is
-        copyright STMicroelectronics.  Reproduced with permission. */
+         * copyright STMicroelectronics.  Reproduced with permission. */
 
         u16 b0;
         u8 a0;
-        int32_t err, err_min=n;
+        int32_t err, err_min = n;
 
 
-        *a = a0 = ((n-1)/256) + 1;
+        *a = a0 = ( ( n - 1 ) / 256 ) + 1;
         *b = b0 = n / *a;
 
-        for (; *a <= 256; (*a)++)
+        for( ; *a <= 256; ( *a )++ )
         {
             *b = n / *a;
-            err = (int32_t)*a * (int32_t)*b - (int32_t)n;
-            if (abs(err) > (*a / 2))
+            err = ( int32_t ) *a * ( int32_t ) *b - ( int32_t ) n;
+
+            if( abs( err ) > ( *a / 2 ) )
             {
-                (*b)++;
-                err = (int32_t)*a * (int32_t)*b - (int32_t)n;
+                ( *b )++;
+                err = ( int32_t ) *a * ( int32_t ) *b - ( int32_t ) n;
             }
-            if (abs(err) < abs(err_min))
+
+            if( abs( err ) < abs( err_min ) )
             {
                 err_min = err;
                 a0 = *a;
                 b0 = *b;
-                if (err == 0) break;
+
+                if( err == 0 )
+                {
+                    break;
+                }
             }
         }
 
@@ -336,20 +354,20 @@ keyword. */
         TIM_InitTypeDef timer;
 
         SCU_APBPeriphClockConfig( __TIM23, ENABLE );
-        TIM_DeInit(TIM2);
-        TIM_StructInit(&timer);
+        TIM_DeInit( TIM2 );
+        TIM_StructInit( &timer );
         prvFindFactors( n, &a, &b );
 
-        timer.TIM_Mode           = TIM_OCM_CHANNEL_1;
-        timer.TIM_OC1_Modes      = TIM_TIMING;
-        timer.TIM_Clock_Source   = TIM_CLK_APB;
-        timer.TIM_Clock_Edge     = TIM_CLK_EDGE_RISING;
-        timer.TIM_Prescaler      = a-1;
-        timer.TIM_Pulse_Level_1  = TIM_HIGH;
-        timer.TIM_Pulse_Length_1 = s_nPulseLength  = b-1;
+        timer.TIM_Mode = TIM_OCM_CHANNEL_1;
+        timer.TIM_OC1_Modes = TIM_TIMING;
+        timer.TIM_Clock_Source = TIM_CLK_APB;
+        timer.TIM_Clock_Edge = TIM_CLK_EDGE_RISING;
+        timer.TIM_Prescaler = a - 1;
+        timer.TIM_Pulse_Level_1 = TIM_HIGH;
+        timer.TIM_Pulse_Length_1 = s_nPulseLength = b - 1;
 
-        TIM_Init (TIM2, &timer);
-        TIM_ITConfig(TIM2, TIM_IT_OC1, ENABLE);
+        TIM_Init( TIM2, &timer );
+        TIM_ITConfig( TIM2, TIM_IT_OC1, ENABLE );
         /* Configure the VIC for the WDG interrupt. */
         VIC_Config( TIM2_ITLine, VIC_IRQ, 10 );
         VIC_ITCmd( TIM2_ITLine, ENABLE );
@@ -358,14 +376,14 @@ keyword. */
         VIC0->DVAR = ( uint32_t ) prvDefaultHandler;
         VIC1->DVAR = ( uint32_t ) prvDefaultHandler;
 
-        TIM_CounterCmd(TIM2, TIM_CLEAR);
-        TIM_CounterCmd(TIM2, TIM_START);
+        TIM_CounterCmd( TIM2, TIM_CLEAR );
+        TIM_CounterCmd( TIM2, TIM_START );
     }
     /*-----------------------------------------------------------*/
 
     void TIM2_IRQHandler( void )
     {
-        /* Reset the timer counter to avioid overflow. */
+        /* Reset the timer counter to avoid overflow. */
         TIM2->OC1R += s_nPulseLength;
 
         /* Increment the tick counter. */
@@ -388,9 +406,9 @@ __arm __interwork void vPortEnterCritical( void )
     /* Disable interrupts first! */
     portDISABLE_INTERRUPTS();
 
-    /* Now interrupts are disabled ulCriticalNesting can be accessed
-    directly.  Increment ulCriticalNesting to keep a count of how many times
-    portENTER_CRITICAL() has been called. */
+    /* Now that interrupts are disabled, ulCriticalNesting can be accessed
+     * directly.  Increment ulCriticalNesting to keep a count of how many times
+     * portENTER_CRITICAL() has been called. */
     ulCriticalNesting++;
 }
 /*-----------------------------------------------------------*/
@@ -403,7 +421,7 @@ __arm __interwork void vPortExitCritical( void )
         ulCriticalNesting--;
 
         /* If the nesting level has reached zero then interrupts should be
-        re-enabled. */
+         * re-enabled. */
         if( ulCriticalNesting == portNO_CRITICAL_NESTING )
         {
             portENABLE_INTERRUPTS();
diff --git a/portable/IAR/STR91x/portmacro.h b/portable/IAR/STR91x/portmacro.h
index b5429b57d..fc4506d32 100644
--- a/portable/IAR/STR91x/portmacro.h
+++ b/portable/IAR/STR91x/portmacro.h
@@ -49,24 +49,24 @@
 /* *INDENT-ON* */
 
 /* Type definitions. */
-#define portCHAR            char
-#define portFLOAT           float
-#define portDOUBLE          double
-#define portLONG            long
-#define portSHORT           short
-#define portSTACK_TYPE      uint32_t
-#define portBASE_TYPE       long
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
-#elif ( configTICK_TYPE_WIDTH_IN_BITS  == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t             TickType_t;
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+    typedef uint32_t     TickType_t;
     #define portMAX_DELAY    ( TickType_t ) 0xffffffffUL
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -74,11 +74,11 @@ typedef unsigned long UBaseType_t;
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portSTACK_GROWTH            ( -1 )
-#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT          8
-#define portYIELD()                 asm ( "SWI 0" )
-#define portNOP()                   asm ( "NOP" )
+#define portSTACK_GROWTH      ( -1 )
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT    8
+#define portYIELD()    asm ( "SWI 0" )
+#define portNOP()      asm ( "NOP" )
 /*-----------------------------------------------------------*/
 
 /* Critical section handling. */
@@ -94,21 +94,21 @@ __arm __interwork void vPortExitCritical( void );
 /*-----------------------------------------------------------*/
 
 /* Task utilities. */
-#define portEND_SWITCHING_ISR( xSwitchRequired )    \
-{                                                   \
-extern void vTaskSwitchContext( void );             \
-                                                    \
-    if( xSwitchRequired )                           \
-    {                                               \
-        vTaskSwitchContext();                       \
-    }                                               \
-}
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+    {                                            \
+        extern void vTaskSwitchContext( void );  \
+                                                 \
+        if( xSwitchRequired )                    \
+        {                                        \
+            vTaskSwitchContext();                \
+        }                                        \
+    }
 /*-----------------------------------------------------------*/
 
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/IAR/V850ES/ISR_Support.h b/portable/IAR/V850ES/ISR_Support.h
index 28c569152..3f04591f4 100644
--- a/portable/IAR/V850ES/ISR_Support.h
+++ b/portable/IAR/V850ES/ISR_Support.h
@@ -26,125 +26,150 @@
  *
  */
 
-    EXTERN pxCurrentTCB
-    EXTERN usCriticalNesting
+EXTERN pxCurrentTCB
+EXTERN usCriticalNesting
 
 #include "FreeRTOSConfig.h"
 
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Context save and restore macro definitions
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;
+Context save and restore macro definitions
+;
 
 portSAVE_CONTEXT MACRO
 
-    add     -0x0C,sp            ; prepare stack to save necessary values
-    st.w    lp,8[sp]            ; store LP to stack
-    stsr    0,r31
-    st.w    lp,4[sp]            ; store EIPC to stack
-    stsr    1,lp
-    st.w    lp,0[sp]            ; store EIPSW to stack
-#if configDATA_MODE == 1                                        ; Using the Tiny data model
-    prepare {r20,r21,r22,r23,r24,r25,r26,r27,r28,r29,r30},76,sp ; save general purpose registers
-    sst.w   r19,72[ep]
-    sst.w   r18,68[ep]
-    sst.w   r17,64[ep]
-    sst.w   r16,60[ep]
-    sst.w   r15,56[ep]
-    sst.w   r14,52[ep]
-    sst.w   r13,48[ep]
-    sst.w   r12,44[ep]
-    sst.w   r11,40[ep]
-    sst.w   r10,36[ep]
-    sst.w   r9,32[ep]
-    sst.w   r8,28[ep]
-    sst.w   r7,24[ep]
-    sst.w   r6,20[ep]
-    sst.w   r5,16[ep]
-    sst.w   r4,12[ep]
-#else                                                           ; Using the Small/Large data model
-    prepare {r20,r21,r22,r23,r24,r26,r27,r28,r29,r30},72,sp     ; save general purpose registers
-    sst.w   r19,68[ep]
-    sst.w   r18,64[ep]
-    sst.w   r17,60[ep]
-    sst.w   r16,56[ep]
-    sst.w   r15,52[ep]
-    sst.w   r14,48[ep]
-    sst.w   r13,44[ep]
-    sst.w   r12,40[ep]
-    sst.w   r11,36[ep]
-    sst.w   r10,32[ep]
-    sst.w   r9,28[ep]
-    sst.w   r8,24[ep]
-    sst.w   r7,20[ep]
-    sst.w   r6,16[ep]
-    sst.w   r5,12[ep]
+    add - 0x0C, sp;
+prepare stack to save necessary values
+st.w lp, 8[ sp ];
+store LP to stack
+    stsr    0, r31
+    st.w lp, 4[ sp ];
+store EIPC to stack
+    stsr    1, lp
+    st.w lp, 0[ sp ];
+store EIPSW to stack
+#if configDATA_MODE == 1; Using the Tiny data model
+prepare {
+    r20, r21, r22, r23, r24, r25, r26, r27, r28, r29, r30
+}, 76, sp;
+save general purpose registers
+sst.w r19, 72[ ep ]
+sst.w r18, 68[ ep ]
+sst.w r17, 64[ ep ]
+sst.w r16, 60[ ep ]
+sst.w r15, 56[ ep ]
+sst.w r14, 52[ ep ]
+sst.w r13, 48[ ep ]
+sst.w r12, 44[ ep ]
+sst.w r11, 40[ ep ]
+sst.w r10, 36[ ep ]
+sst.w r9, 32[ ep ]
+sst.w r8, 28[ ep ]
+sst.w r7, 24[ ep ]
+sst.w r6, 20[ ep ]
+sst.w r5, 16[ ep ]
+sst.w r4, 12[ ep ]
+#else; Using the Small / Large data model
+prepare {
+    r20, r21, r22, r23, r24, r26, r27, r28, r29, r30
+}, 72, sp;
+save general purpose registers
+sst.w r19, 68[ ep ]
+sst.w r18, 64[ ep ]
+sst.w r17, 60[ ep ]
+sst.w r16, 56[ ep ]
+sst.w r15, 52[ ep ]
+sst.w r14, 48[ ep ]
+sst.w r13, 44[ ep ]
+sst.w r12, 40[ ep ]
+sst.w r11, 36[ ep ]
+sst.w r10, 32[ ep ]
+sst.w r9, 28[ ep ]
+sst.w r8, 24[ ep ]
+sst.w r7, 20[ ep ]
+sst.w r6, 16[ ep ]
+sst.w r5, 12[ ep ]
 #endif /* configDATA_MODE */
-    sst.w   r2,8[ep]
-    sst.w   r1,4[ep]
-    MOVHI   hi1(usCriticalNesting),r0,r1    ; save usCriticalNesting value to stack
-    ld.w    lw1(usCriticalNesting)[r1],r2
-    sst.w   r2,0[ep]
-    MOVHI   hi1(pxCurrentTCB),r0,r1         ; save SP to top of current TCB
-    ld.w    lw1(pxCurrentTCB)[r1],r2
-    st.w    sp,0[r2]
-    ENDM
+sst.w r2, 8[ ep ]
+sst.w r1, 4[ ep ]
+MOVHI hi1( usCriticalNesting ), r0, r1;
+save usCriticalNesting value to stack
+ld.w lw1( usCriticalNesting )[ r1 ], r2
+sst.w r2, 0[ ep ]
+MOVHI hi1( pxCurrentTCB ), r0, r1;
+save SP to top of current TCB
+ld.w lw1( pxCurrentTCB )[ r1 ], r2
+st.w sp, 0[ r2 ]
+ENDM
 
 
 portRESTORE_CONTEXT MACRO
 
-    MOVHI   hi1(pxCurrentTCB),r0,r1         ; get Stackpointer address
-    ld.w    lw1(pxCurrentTCB)[r1],sp
-    MOV     sp,r1
-    ld.w    0[r1],sp                        ; load stackpointer
-    MOV     sp,ep                           ; set stack pointer to element pointer
-    sld.w   0[ep],r1                        ; load usCriticalNesting value from stack
-    MOVHI   hi1(usCriticalNesting),r0,r2
-    st.w    r1,lw1(usCriticalNesting)[r2]
-    sld.w   4[ep],r1                        ; restore general purpose registers
-    sld.w   8[ep],r2
-#if configDATA_MODE == 1                    ; Using Tiny data model
-    sld.w   12[ep],r4
-    sld.w   16[ep],r5
-    sld.w   20[ep],r6
-    sld.w   24[ep],r7
-    sld.w   28[ep],r8
-    sld.w   32[ep],r9
-    sld.w   36[ep],r10
-    sld.w   40[ep],r11
-    sld.w   44[ep],r12
-    sld.w   48[ep],r13
-    sld.w   52[ep],r14
-    sld.w   56[ep],r15
-    sld.w   60[ep],r16
-    sld.w   64[ep],r17
-    sld.w   68[ep],r18
-    sld.w   72[ep],r19
-    dispose 76,{r20,r21,r22,r23,r24,r25,r26,r27,r28,r29,r30}
-#else                                       ; Using Small/Large data model
-    sld.w   12[ep],r5
-    sld.w   16[ep],r6
-    sld.w   20[ep],r7
-    sld.w   24[ep],r8
-    sld.w   28[ep],r9
-    sld.w   32[ep],r10
-    sld.w   36[ep],r11
-    sld.w   40[ep],r12
-    sld.w   44[ep],r13
-    sld.w   48[ep],r14
-    sld.w   52[ep],r15
-    sld.w   56[ep],r16
-    sld.w   60[ep],r17
-    sld.w   64[ep],r18
-    sld.w   68[ep],r19
-    dispose 72,{r20,r21,r22,r23,r24,r26,r27,r28,r29,r30}
+MOVHI hi1( pxCurrentTCB ), r0, r1;
+get Stackpointer address
+ld.w lw1( pxCurrentTCB )[ r1 ], sp
+MOV sp, r1
+ld.w    0[ r1 ], sp;
+load stackpointer
+MOV sp, ep;
+set stack pointer to element pointer
+sld.w   0[ ep ], r1;
+load usCriticalNesting value from stack
+MOVHI hi1( usCriticalNesting ), r0, r2
+st.w r1, lw1( usCriticalNesting )[ r2 ]
+sld.w   4[ ep ], r1;
+restore general purpose registers
+sld.w   8[ ep ], r2
+#if configDATA_MODE == 1; Using Tiny data model
+    sld.w   12[ ep ], r4
+    sld.w   16[ ep ], r5
+    sld.w   20[ ep ], r6
+    sld.w   24[ ep ], r7
+    sld.w   28[ ep ], r8
+    sld.w   32[ ep ], r9
+    sld.w   36[ ep ], r10
+    sld.w   40[ ep ], r11
+    sld.w   44[ ep ], r12
+    sld.w   48[ ep ], r13
+    sld.w   52[ ep ], r14
+    sld.w   56[ ep ], r15
+    sld.w   60[ ep ], r16
+    sld.w   64[ ep ], r17
+    sld.w   68[ ep ], r18
+    sld.w   72[ ep ], r19
+    dispose 76, {
+        r20, r21, r22, r23, r24, r25, r26, r27, r28, r29, r30
+    }
+#else; Using Small / Large data model
+    sld.w   12[ ep ], r5
+    sld.w   16[ ep ], r6
+    sld.w   20[ ep ], r7
+    sld.w   24[ ep ], r8
+    sld.w   28[ ep ], r9
+    sld.w   32[ ep ], r10
+    sld.w   36[ ep ], r11
+    sld.w   40[ ep ], r12
+    sld.w   44[ ep ], r13
+    sld.w   48[ ep ], r14
+    sld.w   52[ ep ], r15
+    sld.w   56[ ep ], r16
+    sld.w   60[ ep ], r17
+    sld.w   64[ ep ], r18
+    sld.w   68[ ep ], r19
+    dispose 72, {
+        r20, r21, r22, r23, r24, r26, r27, r28, r29, r30
+    }
 #endif /* configDATA_MODE */
-    ld.w    0[sp],lp                        ; restore EIPSW from stack
-    ldsr    lp,1
-    ld.w    4[sp],lp                        ; restore EIPC from stack
-    ldsr    lp,0
-    ld.w    8[sp],lp                        ; restore LP from stack
-    add     0x0C,sp                         ; set SP to right position
+ld.w    0[ sp ], lp;
+restore EIPSW from stack
+ldsr lp, 1
+ld.w    4[ sp ], lp;
+restore EIPC from stack
+ldsr lp, 0
+ld.w    8[ sp ], lp;
+restore LP from stack
+    add     0x0C, sp;
+set SP to right position
 
-    RETI
+RETI
 
-    ENDM
+ENDM
diff --git a/portable/IAR/V850ES/port.c b/portable/IAR/V850ES/port.c
index 10e5c4598..17c17b66a 100644
--- a/portable/IAR/V850ES/port.c
+++ b/portable/IAR/V850ES/port.c
@@ -34,14 +34,14 @@
 #include "task.h"
 
 /* Critical nesting should be initialised to a non zero value so interrupts don't
-accidentally get enabled before the scheduler is started. */
-#define portINITIAL_CRITICAL_NESTING  (( StackType_t ) 10)
+ * accidentally get enabled before the scheduler is started. */
+#define portINITIAL_CRITICAL_NESTING    ( ( StackType_t ) 10 )
 
 /* The PSW value assigned to tasks when they start to run for the first time. */
-#define portPSW       (( StackType_t ) 0x00000000)
+#define portPSW                         ( ( StackType_t ) 0x00000000 )
 
 /* We require the address of the pxCurrentTCB variable, but don't want to know
-any details of its type. */
+ * any details of its type. */
 typedef void TCB_t;
 extern volatile TCB_t * volatile pxCurrentTCB;
 
@@ -53,75 +53,77 @@ volatile StackType_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;
 static void prvSetupTimerInterrupt( void );
 
 /*-----------------------------------------------------------*/
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
-    *pxTopOfStack = ( StackType_t ) pxCode;          /* Task function start address */
+    *pxTopOfStack = ( StackType_t ) pxCode;     /* Task function start address */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) pxCode;          /* Task function start address */
+    *pxTopOfStack = ( StackType_t ) pxCode;     /* Task function start address */
     pxTopOfStack--;
-    *pxTopOfStack = portPSW;                            /* Initial PSW value */
+    *pxTopOfStack = portPSW;                    /* Initial PSW value */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x20202020;      /* Initial Value of R20 */
+    *pxTopOfStack = ( StackType_t ) 0x20202020; /* Initial Value of R20 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x21212121;      /* Initial Value of R21 */
+    *pxTopOfStack = ( StackType_t ) 0x21212121; /* Initial Value of R21 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x22222222;      /* Initial Value of R22 */
+    *pxTopOfStack = ( StackType_t ) 0x22222222; /* Initial Value of R22 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x23232323;      /* Initial Value of R23 */
+    *pxTopOfStack = ( StackType_t ) 0x23232323; /* Initial Value of R23 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x24242424;      /* Initial Value of R24 */
+    *pxTopOfStack = ( StackType_t ) 0x24242424; /* Initial Value of R24 */
     pxTopOfStack--;
-#if (__DATA_MODEL__ == 0) || (__DATA_MODEL__ == 1)
-    *pxTopOfStack = ( StackType_t ) 0x25252525;      /* Initial Value of R25 */
+    #if ( __DATA_MODEL__ == 0 ) || ( __DATA_MODEL__ == 1 )
+        *pxTopOfStack = ( StackType_t ) 0x25252525; /* Initial Value of R25 */
+        pxTopOfStack--;
+    #endif /* configDATA_MODE */
+    *pxTopOfStack = ( StackType_t ) 0x26262626; /* Initial Value of R26 */
     pxTopOfStack--;
-#endif /* configDATA_MODE */
-    *pxTopOfStack = ( StackType_t ) 0x26262626;      /* Initial Value of R26 */
+    *pxTopOfStack = ( StackType_t ) 0x27272727; /* Initial Value of R27 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x27272727;      /* Initial Value of R27 */
+    *pxTopOfStack = ( StackType_t ) 0x28282828; /* Initial Value of R28 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x28282828;      /* Initial Value of R28 */
+    *pxTopOfStack = ( StackType_t ) 0x29292929; /* Initial Value of R29 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x29292929;      /* Initial Value of R29 */
+    *pxTopOfStack = ( StackType_t ) 0x30303030; /* Initial Value of R30 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x30303030;      /* Initial Value of R30 */
+    *pxTopOfStack = ( StackType_t ) 0x19191919; /* Initial Value of R19 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x19191919;      /* Initial Value of R19 */
+    *pxTopOfStack = ( StackType_t ) 0x18181818; /* Initial Value of R18 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x18181818;      /* Initial Value of R18 */
+    *pxTopOfStack = ( StackType_t ) 0x17171717; /* Initial Value of R17 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x17171717;      /* Initial Value of R17 */
+    *pxTopOfStack = ( StackType_t ) 0x16161616; /* Initial Value of R16 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x16161616;      /* Initial Value of R16 */
+    *pxTopOfStack = ( StackType_t ) 0x15151515; /* Initial Value of R15 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x15151515;      /* Initial Value of R15 */
+    *pxTopOfStack = ( StackType_t ) 0x14141414; /* Initial Value of R14 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x14141414;      /* Initial Value of R14 */
+    *pxTopOfStack = ( StackType_t ) 0x13131313; /* Initial Value of R13 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x13131313;      /* Initial Value of R13 */
+    *pxTopOfStack = ( StackType_t ) 0x12121212; /* Initial Value of R12 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x12121212;      /* Initial Value of R12 */
+    *pxTopOfStack = ( StackType_t ) 0x11111111; /* Initial Value of R11 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x11111111;      /* Initial Value of R11 */
+    *pxTopOfStack = ( StackType_t ) 0x10101010; /* Initial Value of R10 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x10101010;      /* Initial Value of R10 */
+    *pxTopOfStack = ( StackType_t ) 0x99999999; /* Initial Value of R09 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x99999999;      /* Initial Value of R09 */
+    *pxTopOfStack = ( StackType_t ) 0x88888888; /* Initial Value of R08 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x88888888;      /* Initial Value of R08 */
+    *pxTopOfStack = ( StackType_t ) 0x77777777; /* Initial Value of R07 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x77777777;      /* Initial Value of R07 */
+    *pxTopOfStack = ( StackType_t ) 0x66666666; /* Initial Value of R06 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x66666666;      /* Initial Value of R06 */
+    *pxTopOfStack = ( StackType_t ) 0x55555555; /* Initial Value of R05 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x55555555;      /* Initial Value of R05 */
+    #if __DATA_MODEL__ == 0 || __DATA_MODEL__ == 1
+        *pxTopOfStack = ( StackType_t ) 0x44444444; /* Initial Value of R04 */
+        pxTopOfStack--;
+    #endif /* configDATA_MODE */
+    *pxTopOfStack = ( StackType_t ) 0x22222222;   /* Initial Value of R02 */
     pxTopOfStack--;
-#if __DATA_MODEL__ == 0 || __DATA_MODEL__ == 1
-    *pxTopOfStack = ( StackType_t ) 0x44444444;      /* Initial Value of R04 */
-    pxTopOfStack--;
-#endif /* configDATA_MODE */
-    *pxTopOfStack = ( StackType_t ) 0x22222222;      /* Initial Value of R02 */
-    pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) pvParameters;    /* R1 is expected to hold the function parameter*/
+    *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 is expected to hold the function parameter*/
     pxTopOfStack--;
     *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;
 
@@ -136,7 +138,7 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
 BaseType_t xPortStartScheduler( void )
 {
     /* Setup the hardware to generate the tick.  Interrupts are disabled when
-    this function is called. */
+     * this function is called. */
     prvSetupTimerInterrupt();
 
     /* Restore the context of the first task that is going to run. */
@@ -150,7 +152,7 @@ BaseType_t xPortStartScheduler( void )
 void vPortEndScheduler( void )
 {
     /* It is unlikely that the V850ES/Fx3 port will get stopped.  If required simply
-    disable the tick interrupt here. */
+     * disable the tick interrupt here. */
 }
 /*-----------------------------------------------------------*/
 
@@ -159,24 +161,24 @@ void vPortEndScheduler( void )
  */
 static void prvSetupTimerInterrupt( void )
 {
-    TM0CE     = 0;  /* TMM0 operation disable */
-    TM0EQMK0  = 1;  /* INTTM0EQ0 interrupt disable */
-    TM0EQIF0  = 0;  /* clear INTTM0EQ0 interrupt flag */
+    TM0CE = 0;    /* TMM0 operation disable */
+    TM0EQMK0 = 1; /* INTTM0EQ0 interrupt disable */
+    TM0EQIF0 = 0; /* clear INTTM0EQ0 interrupt flag */
 
     #ifdef __IAR_V850ES_Fx3__
     {
-        TM0CMP0   = (((configCPU_CLOCK_HZ / configTICK_RATE_HZ) / 2)-1);    /* divided by 2 because peripherals only run at CPU_CLOCK/2 */
+        TM0CMP0 = ( ( ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) / 2 ) - 1 ); /* divided by 2 because peripherals only run at CPU_CLOCK/2 */
     }
     #else
     {
-        TM0CMP0   = (configCPU_CLOCK_HZ / configTICK_RATE_HZ);
+        TM0CMP0 = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ );
     }
     #endif
 
     TM0EQIC0 &= 0xF8;
-    TM0CTL0   = 0x00;
-    TM0EQIF0 =  0;  /* clear INTTM0EQ0 interrupt flag */
-    TM0EQMK0 =  0;  /* INTTM0EQ0 interrupt enable */
-    TM0CE =     1;  /* TMM0 operation enable */
+    TM0CTL0 = 0x00;
+    TM0EQIF0 = 0; /* clear INTTM0EQ0 interrupt flag */
+    TM0EQMK0 = 0; /* INTTM0EQ0 interrupt enable */
+    TM0CE = 1;    /* TMM0 operation enable */
 }
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/V850ES/portmacro.h b/portable/IAR/V850ES/portmacro.h
index cfae9ae7c..fa9f87eff 100644
--- a/portable/IAR/V850ES/portmacro.h
+++ b/portable/IAR/V850ES/portmacro.h
@@ -46,24 +46,24 @@
  */
 
 /* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  unsigned int
-#define portBASE_TYPE   int
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    unsigned int
+#define portBASE_TYPE     int
 
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
 
 #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
-#elif ( configTICK_TYPE_WIDTH_IN_BITS  == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t             TickType_t;
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+    typedef uint32_t     TickType_t;
     #define portMAX_DELAY    ( TickType_t ) 0xffffffffUL
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -71,42 +71,42 @@ typedef unsigned long UBaseType_t;
 /*-----------------------------------------------------------*/
 
 /* Interrupt control macros. */
-#define portDISABLE_INTERRUPTS() __asm ( "DI" )
-#define portENABLE_INTERRUPTS()  __asm ( "EI" )
+#define portDISABLE_INTERRUPTS()    __asm( "DI" )
+#define portENABLE_INTERRUPTS()     __asm( "EI" )
 /*-----------------------------------------------------------*/
 
 /* Critical section control macros. */
-#define portNO_CRITICAL_SECTION_NESTING     ( ( UBaseType_t ) 0 )
+#define portNO_CRITICAL_SECTION_NESTING    ( ( UBaseType_t ) 0 )
 
-#define portENTER_CRITICAL()                                                        \
-{                                                                                   \
-extern volatile /*uint16_t*/ portSTACK_TYPE usCriticalNesting;                      \
-                                                                                    \
-    portDISABLE_INTERRUPTS();                                                       \
-                                                                                    \
-    /* Now interrupts are disabled ulCriticalNesting can be accessed */             \
-    /* directly.  Increment ulCriticalNesting to keep a count of how many */        \
-    /* times portENTER_CRITICAL() has been called. */                               \
-    usCriticalNesting++;                                                            \
-}
+#define portENTER_CRITICAL()                                                      \
+    {                                                                             \
+        extern volatile /*uint16_t*/ portSTACK_TYPE usCriticalNesting;            \
+                                                                                  \
+        portDISABLE_INTERRUPTS();                                                 \
+                                                                                  \
+        /* Now that interrupts are disabled, ulCriticalNesting can be accessed */ \
+        /* directly.  Increment ulCriticalNesting to keep a count of how many */  \
+        /* times portENTER_CRITICAL() has been called. */                         \
+        usCriticalNesting++;                                                      \
+    }
 
 #define portEXIT_CRITICAL()                                                         \
-{                                                                                   \
-extern volatile /*uint16_t*/ portSTACK_TYPE usCriticalNesting;                      \
-                                                                                    \
-    if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING )                       \
     {                                                                               \
-        /* Decrement the nesting count as we are leaving a critical section. */     \
-        usCriticalNesting--;                                                        \
+        extern volatile /*uint16_t*/ portSTACK_TYPE usCriticalNesting;              \
                                                                                     \
-        /* If the nesting level has reached zero then interrupts should be */       \
-        /* re-enabled. */                                                           \
-        if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING )                  \
+        if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING )                   \
         {                                                                           \
-            portENABLE_INTERRUPTS();                                                \
+            /* Decrement the nesting count as we are leaving a critical section. */ \
+            usCriticalNesting--;                                                    \
+                                                                                    \
+            /* If the nesting level has reached zero then interrupts should be */   \
+            /* re-enabled. */                                                       \
+            if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING )              \
+            {                                                                       \
+                portENABLE_INTERRUPTS();                                            \
+            }                                                                       \
         }                                                                           \
-    }                                                                               \
-}
+    }
 /*-----------------------------------------------------------*/
 
 /* Task utilities. */
@@ -114,22 +114,22 @@ extern void vPortYield( void );
 extern void vPortStart( void );
 extern void portSAVE_CONTEXT( void );
 extern void portRESTORE_CONTEXT( void );
-#define portYIELD() __asm ( "trap 0" )
-#define portNOP()   __asm ( "NOP" )
+#define portYIELD()                                       __asm( "trap 0" )
+#define portNOP()                                         __asm( "NOP" )
 extern void vTaskSwitchContext( void );
-#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) do { if( xHigherPriorityTaskWoken ) vTaskSwitchContext(); } while( 0 )
+#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken )    do { if( xHigherPriorityTaskWoken ) vTaskSwitchContext( ); } while( 0 )
 
 /*-----------------------------------------------------------*/
 
-/* Hardwware specifics. */
-#define portBYTE_ALIGNMENT  4
-#define portSTACK_GROWTH    ( -1 )
-#define portTICK_PERIOD_MS  ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT    4
+#define portSTACK_GROWTH      ( -1 )
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
 
 /* *INDENT-OFF* */
diff --git a/portable/MPLAB/PIC18F/port.c b/portable/MPLAB/PIC18F/port.c
index 1a1827e42..471a6955e 100644
--- a/portable/MPLAB/PIC18F/port.c
+++ b/portable/MPLAB/PIC18F/port.c
@@ -27,33 +27,33 @@
  */
 
 /*
-Changes between V1.2.4 and V1.2.5
-
-    + Introduced portGLOBAL_INTERRUPT_FLAG definition to test the global
-      interrupt flag setting.  Using the two bits defined within
-      portINITAL_INTERRUPT_STATE was causing the w register to get clobbered
-      before the test was performed.
-
-Changes from V1.2.5
-
-    + Set the interrupt vector address to 0x08.  Previously it was at the
-      incorrect address for compatibility mode of 0x18.
-
-Changes from V2.1.1
-
-    + PCLATU and PCLATH are now saved as part of the context.  This allows
-      function pointers to be used within tasks.  Thanks to Javier Espeche
-      for the enhancement.
-
-Changes from V2.3.1
-
-    + TABLAT is now saved as part of the task context.
-
-Changes from V3.2.0
-
-    + TBLPTRU is now initialised to zero as the MPLAB compiler expects this
-      value and does not write to the register.
-*/
+ * Changes between V1.2.4 and V1.2.5
+ *
+ + Introduced portGLOBAL_INTERRUPT_FLAG definition to test the global
+ +    interrupt flag setting.  Using the two bits defined within
+ +    portINITAL_INTERRUPT_STATE was causing the w register to get clobbered
+ +    before the test was performed.
+ +
+ + Changes from V1.2.5
+ +
+ + Set the interrupt vector address to 0x08.  Previously it was at the
+ +    incorrect address for compatibility mode of 0x18.
+ +
+ + Changes from V2.1.1
+ +
+ + PCLATU and PCLATH are now saved as part of the context.  This allows
+ +    function pointers to be used within tasks.  Thanks to Javier Espeche
+ +    for the enhancement.
+ +
+ + Changes from V2.3.1
+ +
+ + TABLAT is now saved as part of the task context.
+ +
+ + Changes from V3.2.0
+ +
+ + TBLPTRU is now initialised to zero as the MPLAB compiler expects this
+ +    value and does not write to the register.
+ */
 
 /* Scheduler include files. */
 #include "FreeRTOS.h"
@@ -63,37 +63,37 @@ Changes from V3.2.0
 #include "timers.h"
 
 /*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the PIC port.
- *----------------------------------------------------------*/
+* Implementation of functions defined in portable.h for the PIC port.
+*----------------------------------------------------------*/
 
 /* Hardware setup for tick. */
-#define portTIMER_FOSC_SCALE            ( ( uint32_t ) 4 )
+#define portTIMER_FOSC_SCALE                ( ( uint32_t ) 4 )
 
 /* Initial interrupt enable state for newly created tasks.  This value is
-copied into INTCON when a task switches in for the first time. */
+ * copied into INTCON when a task switches in for the first time. */
 #define portINITAL_INTERRUPT_STATE          0xc0
 
 /* Just the bit within INTCON for the global interrupt flag. */
 #define portGLOBAL_INTERRUPT_FLAG           0x80
 
 /* Constant used for context switch macro when we require the interrupt
-enable state to be unchanged when the interrupted task is switched back in. */
+ * enable state to be unchanged when the interrupted task is switched back in. */
 #define portINTERRUPTS_UNCHANGED            0x00
 
 /* Some memory areas get saved as part of the task context.  These memory
-area's get used by the compiler for temporary storage, especially when
-performing mathematical operations, or when using 32bit data types.  This
-constant defines the size of memory area which must be saved. */
+ * area's get used by the compiler for temporary storage, especially when
+ * performing mathematical operations, or when using 32bit data types.  This
+ * constant defines the size of memory area which must be saved. */
 #define portCOMPILER_MANAGED_MEMORY_SIZE    ( ( uint8_t ) 0x13 )
 
 /* We require the address of the pxCurrentTCB variable, but don't want to know
-any details of its type. */
+ * any details of its type. */
 typedef void TCB_t;
 extern volatile TCB_t * volatile pxCurrentTCB;
 
 /* IO port constants. */
-#define portBIT_SET     ( ( uint8_t ) 1 )
-#define portBIT_CLEAR   ( ( uint8_t ) 0 )
+#define portBIT_SET      ( ( uint8_t ) 1 )
+#define portBIT_CLEAR    ( ( uint8_t ) 0 )
 
 /*
  * The serial port ISR's are defined in serial.c, but are called from portable
@@ -136,7 +136,7 @@ static void prvLowInterrupt( void );
  *
  * The compiler uses some locations at the bottom of the memory for temporary
  * storage during math and other computations.  This is especially true if
- * 32bit data types are utilised (as they are by the scheduler).  The .tmpdata
+ * 32bit data types are used (as they are by the scheduler).  The .tmpdata
  * and MATH_DATA sections have to be stored in there entirety as part of a task
  * context.  This macro stores from data address 0x00 to
  * portCOMPILER_MANAGED_MEMORY_SIZE.  This is sufficient for the demo
@@ -144,212 +144,214 @@ static void prvLowInterrupt( void );
  * this is sufficient for your needs.  It is not clear whether this size is
  * fixed for all compilations or has the potential to be program specific.
  */
-#define portSAVE_CONTEXT( ucForcedInterruptFlags )                              \
-{                                                                               \
-    _asm                                                                        \
+#define portSAVE_CONTEXT( ucForcedInterruptFlags ) \
+    {                                              \
+        _asm                                       \
         /* Save the status and WREG registers first, as these will get modified \
-        by the operations below. */                                             \
-        MOVFF   WREG, PREINC1                                                   \
-        MOVFF   STATUS, PREINC1                                                 \
-        /* Save the INTCON register with the appropriate bits forced if         \
-        necessary - as described above. */                                      \
-        MOVFF   INTCON, WREG                                                    \
-        IORLW   ucForcedInterruptFlags                                          \
-        MOVFF   WREG, PREINC1                                                   \
-    _endasm                                                                     \
-                                                                                \
-    portDISABLE_INTERRUPTS();                                                   \
-                                                                                \
-    _asm                                                                        \
-        /* Store the necessary registers to the stack. */                       \
-        MOVFF   BSR, PREINC1                                                    \
-        MOVFF   FSR2L, PREINC1                                                  \
-        MOVFF   FSR2H, PREINC1                                                  \
-        MOVFF   FSR0L, PREINC1                                                  \
-        MOVFF   FSR0H, PREINC1                                                  \
-        MOVFF   TABLAT, PREINC1                                                 \
-        MOVFF   TBLPTRU, PREINC1                                                \
-        MOVFF   TBLPTRH, PREINC1                                                \
-        MOVFF   TBLPTRL, PREINC1                                                \
-        MOVFF   PRODH, PREINC1                                                  \
-        MOVFF   PRODL, PREINC1                                                  \
-        MOVFF   PCLATU, PREINC1                                                 \
-        MOVFF   PCLATH, PREINC1                                                 \
-        /* Store the .tempdata and MATH_DATA areas as described above. */       \
-        CLRF    FSR0L, 0                                                        \
-        CLRF    FSR0H, 0                                                        \
-        MOVFF   POSTINC0, PREINC1                                               \
-        MOVFF   POSTINC0, PREINC1                                               \
-        MOVFF   POSTINC0, PREINC1                                               \
-        MOVFF   POSTINC0, PREINC1                                               \
-        MOVFF   POSTINC0, PREINC1                                               \
-        MOVFF   POSTINC0, PREINC1                                               \
-        MOVFF   POSTINC0, PREINC1                                               \
-        MOVFF   POSTINC0, PREINC1                                               \
-        MOVFF   POSTINC0, PREINC1                                               \
-        MOVFF   POSTINC0, PREINC1                                               \
-        MOVFF   POSTINC0, PREINC1                                               \
-        MOVFF   POSTINC0, PREINC1                                               \
-        MOVFF   POSTINC0, PREINC1                                               \
-        MOVFF   POSTINC0, PREINC1                                               \
-        MOVFF   POSTINC0, PREINC1                                               \
-        MOVFF   POSTINC0, PREINC1                                               \
-        MOVFF   POSTINC0, PREINC1                                               \
-        MOVFF   POSTINC0, PREINC1                                               \
-        MOVFF   POSTINC0, PREINC1                                               \
-        MOVFF   INDF0, PREINC1                                                  \
-        MOVFF   FSR0L, PREINC1                                                  \
-        MOVFF   FSR0H, PREINC1                                                  \
-        /* Store the hardware stack pointer in a temp register before we        \
-        modify it. */                                                           \
-        MOVFF   STKPTR, FSR0L                                                   \
-    _endasm                                                                     \
-                                                                                \
-        /* Store each address from the hardware stack. */                       \
-        while( STKPTR > ( uint8_t ) 0 )                             \
-        {                                                                       \
-            _asm                                                                \
-                MOVFF   TOSL, PREINC1                                           \
-                MOVFF   TOSH, PREINC1                                           \
-                MOVFF   TOSU, PREINC1                                           \
-                POP                                                             \
-            _endasm                                                             \
-        }                                                                       \
-                                                                                \
-    _asm                                                                        \
-        /* Store the number of addresses on the hardware stack (from the        \
-        temporary register). */                                                 \
-        MOVFF   FSR0L, PREINC1                                                  \
-        MOVF    PREINC1, 1, 0                                                   \
-    _endasm                                                                     \
-                                                                                \
-    /* Save the new top of the software stack in the TCB. */                    \
-    _asm                                                                        \
-        MOVFF   pxCurrentTCB, FSR0L                                             \
-        MOVFF   pxCurrentTCB + 1, FSR0H                                         \
-        MOVFF   FSR1L, POSTINC0                                                 \
-        MOVFF   FSR1H, POSTINC0                                                 \
-    _endasm                                                                     \
-}
+         * by the operations below. */ \
+        MOVFF WREG, PREINC1            \
+        MOVFF STATUS, PREINC1          \
+        /* Save the INTCON register with the appropriate bits forced if \
+         * necessary - as described above. */                             \
+        MOVFF INTCON, WREG                                                \
+        IORLW ucForcedInterruptFlags                                      \
+        MOVFF WREG, PREINC1                                               \
+        _endasm                                                           \
+                                                                          \
+        portDISABLE_INTERRUPTS();                                         \
+                                                                          \
+        _asm                                                              \
+        /* Store the necessary registers to the stack. */                 \
+        MOVFF BSR, PREINC1                                                \
+        MOVFF FSR2L, PREINC1                                              \
+        MOVFF FSR2H, PREINC1                                              \
+        MOVFF FSR0L, PREINC1                                              \
+        MOVFF FSR0H, PREINC1                                              \
+        MOVFF TABLAT, PREINC1                                             \
+        MOVFF TBLPTRU, PREINC1                                            \
+        MOVFF TBLPTRH, PREINC1                                            \
+        MOVFF TBLPTRL, PREINC1                                            \
+        MOVFF PRODH, PREINC1                                              \
+        MOVFF PRODL, PREINC1                                              \
+        MOVFF PCLATU, PREINC1                                             \
+        MOVFF PCLATH, PREINC1                                             \
+        /* Store the .tempdata and MATH_DATA areas as described above. */ \
+        CLRF FSR0L, 0                                                     \
+        CLRF FSR0H, 0                                                     \
+        MOVFF POSTINC0, PREINC1                                           \
+        MOVFF POSTINC0, PREINC1                                           \
+        MOVFF POSTINC0, PREINC1                                           \
+        MOVFF POSTINC0, PREINC1                                           \
+        MOVFF POSTINC0, PREINC1                                           \
+        MOVFF POSTINC0, PREINC1                                           \
+        MOVFF POSTINC0, PREINC1                                           \
+        MOVFF POSTINC0, PREINC1                                           \
+        MOVFF POSTINC0, PREINC1                                           \
+        MOVFF POSTINC0, PREINC1                                           \
+        MOVFF POSTINC0, PREINC1                                           \
+        MOVFF POSTINC0, PREINC1                                           \
+        MOVFF POSTINC0, PREINC1                                           \
+        MOVFF POSTINC0, PREINC1                                           \
+        MOVFF POSTINC0, PREINC1                                           \
+        MOVFF POSTINC0, PREINC1                                           \
+        MOVFF POSTINC0, PREINC1                                           \
+        MOVFF POSTINC0, PREINC1                                           \
+        MOVFF POSTINC0, PREINC1                                           \
+        MOVFF INDF0, PREINC1                                              \
+        MOVFF FSR0L, PREINC1                                              \
+        MOVFF FSR0H, PREINC1                                              \
+        /* Store the hardware stack pointer in a temp register before we \
+         * modify it. */                                  \
+        MOVFF STKPTR, FSR0L                               \
+        _endasm                                           \
+                                                          \
+        /* Store each address from the hardware stack. */ \
+        while( STKPTR > ( uint8_t ) 0 )                   \
+        {                                                 \
+            _asm                                          \
+            MOVFF TOSL, PREINC1                           \
+            MOVFF TOSH, PREINC1                           \
+            MOVFF TOSU, PREINC1                           \
+            POP                                           \
+            _endasm                                       \
+        }                                                 \
+                                                          \
+        _asm                                              \
+        /* Store the number of addresses on the hardware stack (from the \
+         * temporary register). */                               \
+        MOVFF FSR0L, PREINC1                                     \
+        MOVF PREINC1, 1, 0                                       \
+        _endasm                                                  \
+                                                                 \
+        /* Save the new top of the software stack in the TCB. */ \
+        _asm                                                     \
+        MOVFF pxCurrentTCB, FSR0L                                \
+        MOVFF pxCurrentTCB + 1, FSR0H                            \
+        MOVFF FSR1L, POSTINC0                                    \
+        MOVFF FSR1H, POSTINC0                                    \
+        _endasm                                                  \
+    }
 /*-----------------------------------------------------------*/
 
 /*
  * This is the reverse of portSAVE_CONTEXT.  See portSAVE_CONTEXT for more
  * details.
  */
-#define portRESTORE_CONTEXT()                                                   \
-{                                                                               \
-    _asm                                                                        \
-        /* Set FSR0 to point to pxCurrentTCB->pxTopOfStack. */                  \
-        MOVFF   pxCurrentTCB, FSR0L                                             \
-        MOVFF   pxCurrentTCB + 1, FSR0H                                         \
-                                                                                \
-        /* De-reference FSR0 to set the address it holds into FSR1.             \
-        (i.e. *( pxCurrentTCB->pxTopOfStack ) ). */                             \
-        MOVFF   POSTINC0, FSR1L                                                 \
-        MOVFF   POSTINC0, FSR1H                                                 \
-                                                                                \
-        /* How many return addresses are there on the hardware stack?  Discard  \
-        the first byte as we are pointing to the next free space. */            \
-        MOVFF   POSTDEC1, FSR0L                                                 \
-        MOVFF   POSTDEC1, FSR0L                                                 \
-    _endasm                                                                     \
-                                                                                \
-    /* Fill the hardware stack from our software stack. */                      \
-    STKPTR = 0;                                                                 \
-                                                                                \
-    while( STKPTR < FSR0L )                                                     \
-    {                                                                           \
-        _asm                                                                    \
-            PUSH                                                                \
-            MOVF    POSTDEC1, 0, 0                                              \
-            MOVWF   TOSU, 0                                                     \
-            MOVF    POSTDEC1, 0, 0                                              \
-            MOVWF   TOSH, 0                                                     \
-            MOVF    POSTDEC1, 0, 0                                              \
-            MOVWF   TOSL, 0                                                     \
-        _endasm                                                                 \
-    }                                                                           \
-                                                                                \
-    _asm                                                                        \
-        /* Restore the .tmpdata and MATH_DATA memory. */                        \
-        MOVFF   POSTDEC1, FSR0H                                                 \
-        MOVFF   POSTDEC1, FSR0L                                                 \
-        MOVFF   POSTDEC1, POSTDEC0                                              \
-        MOVFF   POSTDEC1, POSTDEC0                                              \
-        MOVFF   POSTDEC1, POSTDEC0                                              \
-        MOVFF   POSTDEC1, POSTDEC0                                              \
-        MOVFF   POSTDEC1, POSTDEC0                                              \
-        MOVFF   POSTDEC1, POSTDEC0                                              \
-        MOVFF   POSTDEC1, POSTDEC0                                              \
-        MOVFF   POSTDEC1, POSTDEC0                                              \
-        MOVFF   POSTDEC1, POSTDEC0                                              \
-        MOVFF   POSTDEC1, POSTDEC0                                              \
-        MOVFF   POSTDEC1, POSTDEC0                                              \
-        MOVFF   POSTDEC1, POSTDEC0                                              \
-        MOVFF   POSTDEC1, POSTDEC0                                              \
-        MOVFF   POSTDEC1, POSTDEC0                                              \
-        MOVFF   POSTDEC1, POSTDEC0                                              \
-        MOVFF   POSTDEC1, POSTDEC0                                              \
-        MOVFF   POSTDEC1, POSTDEC0                                              \
-        MOVFF   POSTDEC1, POSTDEC0                                              \
-        MOVFF   POSTDEC1, POSTDEC0                                              \
-        MOVFF   POSTDEC1, INDF0                                                 \
-        /* Restore the other registers forming the tasks context. */            \
-        MOVFF   POSTDEC1, PCLATH                                                \
-        MOVFF   POSTDEC1, PCLATU                                                \
-        MOVFF   POSTDEC1, PRODL                                                 \
-        MOVFF   POSTDEC1, PRODH                                                 \
-        MOVFF   POSTDEC1, TBLPTRL                                               \
-        MOVFF   POSTDEC1, TBLPTRH                                               \
-        MOVFF   POSTDEC1, TBLPTRU                                               \
-        MOVFF   POSTDEC1, TABLAT                                                \
-        MOVFF   POSTDEC1, FSR0H                                                 \
-        MOVFF   POSTDEC1, FSR0L                                                 \
-        MOVFF   POSTDEC1, FSR2H                                                 \
-        MOVFF   POSTDEC1, FSR2L                                                 \
-        MOVFF   POSTDEC1, BSR                                                   \
-        /* The next byte is the INTCON register.  Read this into WREG as some   \
-        manipulation is required. */                                            \
-        MOVFF   POSTDEC1, WREG                                                  \
-    _endasm                                                                     \
-                                                                                \
-    /* From the INTCON register, only the interrupt enable bits form part       \
-    of the tasks context.  It is perfectly legitimate for another task to       \
-    have modified any other bits.  We therefore only restore the top two bits.  \
-    */                                                                          \
-    if( WREG & portGLOBAL_INTERRUPT_FLAG )                                      \
-    {                                                                           \
-        _asm                                                                    \
-            MOVFF   POSTDEC1, STATUS                                            \
-            MOVFF   POSTDEC1, WREG                                              \
-            /* Return enabling interrupts. */                                   \
-            RETFIE  0                                                           \
-        _endasm                                                                 \
-    }                                                                           \
-    else                                                                        \
-    {                                                                           \
-        _asm                                                                    \
-            MOVFF   POSTDEC1, STATUS                                            \
-            MOVFF   POSTDEC1, WREG                                              \
-            /* Return without effecting interrupts.  The context may have       \
-            been saved from a critical region. */                               \
-            RETURN  0                                                           \
-        _endasm                                                                 \
-    }                                                                           \
-}
+#define portRESTORE_CONTEXT()                                  \
+    {                                                          \
+        _asm                                                   \
+        /* Set FSR0 to point to pxCurrentTCB->pxTopOfStack. */ \
+        MOVFF pxCurrentTCB, FSR0L                              \
+        MOVFF pxCurrentTCB + 1, FSR0H                          \
+                                                               \
+        /* De-reference FSR0 to set the address it holds into FSR1. \
+         * (i.e. *( pxCurrentTCB->pxTopOfStack ) ). */ \
+        MOVFF POSTINC0, FSR1L                          \
+        MOVFF POSTINC0, FSR1H                          \
+                                                       \
+        /* How many return addresses are there on the hardware stack?  Discard \
+         * the first byte as we are pointing to the next free space. */ \
+        MOVFF POSTDEC1, FSR0L                                           \
+        MOVFF POSTDEC1, FSR0L                                           \
+        _endasm                                                         \
+                                                                        \
+        /* Fill the hardware stack from our software stack. */          \
+        STKPTR = 0;                                                     \
+                                                                        \
+        while( STKPTR < FSR0L )                                         \
+        {                                                               \
+            _asm                                                        \
+            PUSH                                                        \
+            MOVF POSTDEC1, 0, 0                                         \
+            MOVWF TOSU, 0                                               \
+            MOVF POSTDEC1, 0, 0                                         \
+            MOVWF TOSH, 0                                               \
+            MOVF POSTDEC1, 0, 0                                         \
+            MOVWF TOSL, 0                                               \
+            _endasm                                                     \
+        }                                                               \
+                                                                        \
+        _asm                                                            \
+        /* Restore the .tmpdata and MATH_DATA memory. */                \
+        MOVFF POSTDEC1, FSR0H                                           \
+        MOVFF POSTDEC1, FSR0L                                           \
+        MOVFF POSTDEC1, POSTDEC0                                        \
+        MOVFF POSTDEC1, POSTDEC0                                        \
+        MOVFF POSTDEC1, POSTDEC0                                        \
+        MOVFF POSTDEC1, POSTDEC0                                        \
+        MOVFF POSTDEC1, POSTDEC0                                        \
+        MOVFF POSTDEC1, POSTDEC0                                        \
+        MOVFF POSTDEC1, POSTDEC0                                        \
+        MOVFF POSTDEC1, POSTDEC0                                        \
+        MOVFF POSTDEC1, POSTDEC0                                        \
+        MOVFF POSTDEC1, POSTDEC0                                        \
+        MOVFF POSTDEC1, POSTDEC0                                        \
+        MOVFF POSTDEC1, POSTDEC0                                        \
+        MOVFF POSTDEC1, POSTDEC0                                        \
+        MOVFF POSTDEC1, POSTDEC0                                        \
+        MOVFF POSTDEC1, POSTDEC0                                        \
+        MOVFF POSTDEC1, POSTDEC0                                        \
+        MOVFF POSTDEC1, POSTDEC0                                        \
+        MOVFF POSTDEC1, POSTDEC0                                        \
+        MOVFF POSTDEC1, POSTDEC0                                        \
+        MOVFF POSTDEC1, INDF0                                           \
+        /* Restore the other registers forming the tasks context. */    \
+        MOVFF POSTDEC1, PCLATH                                          \
+        MOVFF POSTDEC1, PCLATU                                          \
+        MOVFF POSTDEC1, PRODL                                           \
+        MOVFF POSTDEC1, PRODH                                           \
+        MOVFF POSTDEC1, TBLPTRL                                         \
+        MOVFF POSTDEC1, TBLPTRH                                         \
+        MOVFF POSTDEC1, TBLPTRU                                         \
+        MOVFF POSTDEC1, TABLAT                                          \
+        MOVFF POSTDEC1, FSR0H                                           \
+        MOVFF POSTDEC1, FSR0L                                           \
+        MOVFF POSTDEC1, FSR2H                                           \
+        MOVFF POSTDEC1, FSR2L                                           \
+        MOVFF POSTDEC1, BSR                                             \
+        /* The next byte is the INTCON register.  Read this into WREG as some \
+         * manipulation is required. */ \
+        MOVFF POSTDEC1, WREG            \
+        _endasm                         \
+                                        \
+        /* From the INTCON register, only the interrupt enable bits form part \
+         * of the tasks context.  It is perfectly legitimate for another task to \
+         * have modified any other bits.  We therefore only restore the top two bits. \
+         */                                   \
+        if( WREG &portGLOBAL_INTERRUPT_FLAG ) \
+        {                                     \
+            _asm                              \
+            MOVFF POSTDEC1, STATUS            \
+            MOVFF POSTDEC1, WREG              \
+            /* Return enabling interrupts. */ \
+            RETFIE 0                          \
+            _endasm                           \
+        }                                     \
+        else                                  \
+        {                                     \
+            _asm                              \
+            MOVFF POSTDEC1, STATUS            \
+            MOVFF POSTDEC1, WREG              \
+            /* Return without effecting interrupts.  The context may have \
+             * been saved from a critical region. */ \
+            RETURN 0                                 \
+            _endasm                                  \
+        }                                            \
+    }
 /*-----------------------------------------------------------*/
 
 /*
  * See header file for description.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
-uint32_t ulAddress;
-uint8_t ucBlock;
+    uint32_t ulAddress;
+    uint8_t ucBlock;
 
     /* Place a few bytes of known values on the bottom of the stack.
-    This is just useful for debugging. */
+     * This is just useful for debugging. */
 
     *pxTopOfStack = 0x11;
     pxTopOfStack++;
@@ -360,10 +362,10 @@ uint8_t ucBlock;
 
 
     /* Simulate how the stack would look after a call to vPortYield() generated
-    by the compiler.
-
-    First store the function parameters.  This is where the task will expect to
-    find them when it starts running. */
+     * by the compiler.
+     *
+     * First store the function parameters.  This is where the task will expect to
+     * find them when it starts running. */
     ulAddress = ( uint32_t ) pvParameters;
     *pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
     pxTopOfStack++;
@@ -373,9 +375,9 @@ uint8_t ucBlock;
     pxTopOfStack++;
 
     /* Next we just leave a space.  When a context is saved the stack pointer
-    is incremented before it is used so as not to corrupt whatever the stack
-    pointer is actually pointing to.  This is especially necessary during
-    function epilogue code generated by the compiler. */
+     * is incremented before it is used so as not to corrupt whatever the stack
+     * pointer is actually pointing to.  This is especially necessary during
+     * function epilogue code generated by the compiler. */
     *pxTopOfStack = 0x44;
     pxTopOfStack++;
 
@@ -445,7 +447,7 @@ uint8_t ucBlock;
     pxTopOfStack++;
 
     /* The only function return address so far is the address of the
-    task. */
+     * task. */
     ulAddress = ( uint32_t ) pxCode;
 
     /* TOS low. */
@@ -463,7 +465,7 @@ uint8_t ucBlock;
     pxTopOfStack++;
 
     /* Store the number of return addresses on the hardware stack - so far only
-    the address of the task entry point. */
+     * the address of the task entry point. */
     *pxTopOfStack = ( StackType_t ) 1;
     pxTopOfStack++;
 
@@ -490,8 +492,8 @@ BaseType_t xPortStartScheduler( void )
 void vPortEndScheduler( void )
 {
     /* It is unlikely that the scheduler for the PIC port will get stopped
-    once running.  If required disable the tick interrupt here, then return
-    to xPortStartScheduler(). */
+     * once running.  If required disable the tick interrupt here, then return
+     * to xPortStartScheduler(). */
 }
 /*-----------------------------------------------------------*/
 
@@ -503,7 +505,7 @@ void vPortEndScheduler( void )
 void vPortYield( void )
 {
     /* This can get called with interrupts either enabled or disabled.  We
-    will save the INTCON register with the interrupt enable bits unmodified. */
+     * will save the INTCON register with the interrupt enable bits unmodified. */
     portSAVE_CONTEXT( portINTERRUPTS_UNCHANGED );
 
     /* Switch to the highest priority task that is ready to run. */
@@ -524,7 +526,7 @@ static void prvLowInterrupt( void )
     if( PIR1bits.CCP1IF )
     {
         _asm
-            goto prvTickISR
+        goto prvTickISR
         _endasm
     }
 
@@ -532,7 +534,7 @@ static void prvLowInterrupt( void )
     if( PIR1bits.RCIF )
     {
         _asm
-            goto vSerialRxISR
+        goto vSerialRxISR
         _endasm
     }
 
@@ -542,7 +544,7 @@ static void prvLowInterrupt( void )
         if( PIE1bits.TXIE )
         {
             _asm
-                goto vSerialTxISR
+            goto vSerialTxISR
             _endasm
         }
     }
@@ -560,7 +562,7 @@ static void prvLowInterrupt( void )
 static void prvTickISR( void )
 {
     /* Interrupts must have been enabled for the ISR to fire, so we have to
-    save the context with interrupts enabled. */
+     * save the context with interrupts enabled. */
     portSAVE_CONTEXT( portGLOBAL_INTERRUPT_FLAG );
     PIR1bits.CCP1IF = 0;
 
@@ -580,16 +582,16 @@ static void prvTickISR( void )
  */
 static void prvSetupTimerInterrupt( void )
 {
-const uint32_t ulConstCompareValue = ( ( configCPU_CLOCK_HZ / portTIMER_FOSC_SCALE ) / configTICK_RATE_HZ );
-uint32_t ulCompareValue;
-uint8_t ucByte;
+    const uint32_t ulConstCompareValue = ( ( configCPU_CLOCK_HZ / portTIMER_FOSC_SCALE ) / configTICK_RATE_HZ );
+    uint32_t ulCompareValue;
+    uint8_t ucByte;
 
     /* Interrupts are disabled when this function is called.
-
-    Setup CCP1 to provide the tick interrupt using a compare match on timer
-    1.
-
-    Clear the time count then setup timer. */
+     *
+     * Setup CCP1 to provide the tick interrupt using a compare match on timer
+     * 1.
+     *
+     * Clear the time count then setup timer. */
     TMR1H = ( uint8_t ) 0x00;
     TMR1L = ( uint8_t ) 0x00;
 
@@ -606,10 +608,10 @@ uint8_t ucByte;
     PIE1bits.CCP1IE = portBIT_SET;      /*< Interrupt enable. */
 
     /* We are only going to use the global interrupt bit, so set the peripheral
-    bit to true. */
+     * bit to true. */
     INTCONbits.GIEL = portBIT_SET;
 
     /* Provided library function for setting up the timer that will produce the
-    tick. */
+     * tick. */
     OpenTimer1( T1_16BIT_RW & T1_SOURCE_INT & T1_PS_1_1 & T1_CCP1_T3_CCP2 );
 }
diff --git a/portable/MPLAB/PIC18F/portmacro.h b/portable/MPLAB/PIC18F/portmacro.h
index 6fef1afe2..11f21cfc9 100644
--- a/portable/MPLAB/PIC18F/portmacro.h
+++ b/portable/MPLAB/PIC18F/portmacro.h
@@ -40,23 +40,23 @@
  */
 
 /* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       int
-#define portSTACK_TYPE  uint8_t
-#define portBASE_TYPE   char
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         int
+#define portSTACK_TYPE    uint8_t
+#define portBASE_TYPE     char
 
-typedef portSTACK_TYPE StackType_t;
-typedef signed char BaseType_t;
-typedef unsigned char UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef signed char      BaseType_t;
+typedef unsigned char    UBaseType_t;
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
-#elif ( configTICK_TYPE_WIDTH_IN_BITS  == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t             TickType_t;
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+    typedef uint32_t     TickType_t;
     #define portMAX_DELAY    ( TickType_t ) 0xffffffffUL
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -64,10 +64,10 @@ typedef unsigned char UBaseType_t;
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portBYTE_ALIGNMENT          1
-#define portGLOBAL_INT_ENABLE_BIT   0x80
-#define portSTACK_GROWTH            1
-#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT           1
+#define portGLOBAL_INT_ENABLE_BIT    0x80
+#define portSTACK_GROWTH             1
+#define portTICK_PERIOD_MS           ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
 /*-----------------------------------------------------------*/
 
 /* Critical section management. */
@@ -75,30 +75,32 @@ typedef unsigned char UBaseType_t;
 #define portENABLE_INTERRUPTS()     INTCONbits.GIEH = 1;
 
 /* Push the INTCON register onto the stack, then disable interrupts. */
-#define portENTER_CRITICAL()        POSTINC1 = INTCON;              \
-                                    INTCONbits.GIEH = 0;
+#define portENTER_CRITICAL() \
+    POSTINC1 = INTCON;       \
+    INTCONbits.GIEH = 0;
 
 /* Retrieve the INTCON register from the stack, and enable interrupts
-if they were saved as being enabled.  Don't modify any other bits
-within the INTCON register as these may have lagitimately have been
-modified within the critical region. */
-#define portEXIT_CRITICAL()         _asm                                    \
-                                        MOVF    POSTDEC1, 1, 0              \
-                                    _endasm                                 \
-                                    if( INDF1 & portGLOBAL_INT_ENABLE_BIT ) \
-                                    {                                       \
-                                        portENABLE_INTERRUPTS();            \
-                                    }
+ * if they were saved as being enabled.  Don't modify any other bits
+ * within the INTCON register as these may have legitimately have been
+ * modified within the critical region. */
+#define portEXIT_CRITICAL()                 \
+    _asm                                    \
+    MOVF POSTDEC1, 1, 0                     \
+    _endasm                                 \
+    if( INDF1 & portGLOBAL_INT_ENABLE_BIT ) \
+    {                                       \
+        portENABLE_INTERRUPTS();            \
+    }
 /*-----------------------------------------------------------*/
 
 /* Task utilities. */
 extern void vPortYield( void );
-#define portYIELD()             vPortYield()
+#define portYIELD()    vPortYield()
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 /*-----------------------------------------------------------*/
 
 /* Required by the kernel aware debugger. */
@@ -107,8 +109,9 @@ extern void vPortYield( void );
 #endif
 
 
-#define portNOP()               _asm    \
-                                    NOP \
-                                _endasm
+#define portNOP() \
+    _asm          \
+    NOP           \
+    _endasm
 
 #endif /* PORTMACRO_H */
diff --git a/portable/MPLAB/PIC24_dsPIC/port.c b/portable/MPLAB/PIC24_dsPIC/port.c
index 6f23fe8a2..dfbce1128 100644
--- a/portable/MPLAB/PIC24_dsPIC/port.c
+++ b/portable/MPLAB/PIC24_dsPIC/port.c
@@ -27,38 +27,38 @@
  */
 
 /*
-    Changes from V4.2.1
-
-    + Introduced the configKERNEL_INTERRUPT_PRIORITY definition.
-*/
+ *  Changes from V4.2.1
+ *
+ + Introduced the configKERNEL_INTERRUPT_PRIORITY definition.
+ */
 
 /*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the PIC24 port.
- *----------------------------------------------------------*/
+* Implementation of functions defined in portable.h for the PIC24 port.
+*----------------------------------------------------------*/
 
 /* Scheduler include files. */
 #include "FreeRTOS.h"
 #include "task.h"
 
 /* Hardware specifics. */
-#define portBIT_SET 1
-#define portTIMER_PRESCALE 8
-#define portINITIAL_SR  0
+#define portBIT_SET           1
+#define portTIMER_PRESCALE    8
+#define portINITIAL_SR        0
 
 /* Defined for backward compatability with project created prior to
-FreeRTOS.org V4.3.0. */
+ * FreeRTOS.org V4.3.0. */
 #ifndef configKERNEL_INTERRUPT_PRIORITY
-    #define configKERNEL_INTERRUPT_PRIORITY 1
+    #define configKERNEL_INTERRUPT_PRIORITY    1
 #endif
 
 /* Use _T1Interrupt as the interrupt handler name if the application writer has
-not provided their own. */
+ * not provided their own. */
 #ifndef configTICK_INTERRUPT_HANDLER
-    #define configTICK_INTERRUPT_HANDLER _T1Interrupt
+    #define configTICK_INTERRUPT_HANDLER    _T1Interrupt
 #endif /* configTICK_INTERRUPT_HANDLER */
 
 /* The program counter is only 23 bits. */
-#define portUNUSED_PR_BITS  0x7f
+#define portUNUSED_PR_BITS    0x7f
 
 /* Records the nesting depth of calls to portENTER_CRITICAL(). */
 UBaseType_t uxCriticalNesting = 0xef;
@@ -67,89 +67,89 @@ UBaseType_t uxCriticalNesting = 0xef;
     #error If configKERNEL_INTERRUPT_PRIORITY is not 1 then the #32 in the following macros needs changing to equal the portINTERRUPT_BITS value, which is ( configKERNEL_INTERRUPT_PRIORITY << 5 )
 #endif
 
-#if defined( __PIC24E__ ) || defined ( __PIC24F__ ) || defined( __PIC24FK__ ) || defined( __PIC24H__ )
+#if defined( __PIC24E__ ) || defined( __PIC24F__ ) || defined( __PIC24FK__ ) || defined( __PIC24H__ )
 
     #ifdef __HAS_EDS__
-        #define portRESTORE_CONTEXT()                                                                                       \
-                    asm volatile(   "MOV    _pxCurrentTCB, W0       \n" /* Restore the stack pointer for the task. */       \
-                            "MOV    [W0], W15               \n"                                                             \
-                            "POP    W0                      \n" /* Restore the critical nesting counter for the task. */    \
-                            "MOV    W0, _uxCriticalNesting  \n"                                                             \
-                            "POP    DSWPAG                  \n"                                                             \
-                            "POP    DSRPAG                  \n"                                                             \
-                            "POP    CORCON                  \n"                                                             \
-                            "POP    TBLPAG                  \n"                                                             \
-                            "POP    RCOUNT                  \n" /* Restore the registers from the stack. */                 \
-                            "POP    W14                     \n"                                                             \
-                            "POP.D  W12                     \n"                                                             \
-                            "POP.D  W10                     \n"                                                             \
-                            "POP.D  W8                      \n"                                                             \
-                            "POP.D  W6                      \n"                                                             \
-                            "POP.D  W4                      \n"                                                             \
-                            "POP.D  W2                      \n"                                                             \
-                            "POP.D  W0                      \n"                                                             \
-                            "POP    SR                        " );
+        #define portRESTORE_CONTEXT()                                                                           \
+    asm volatile ( "MOV    _pxCurrentTCB, W0       \n" /* Restore the stack pointer for the task. */            \
+                   "MOV    [W0], W15               \n"                                                          \
+                   "POP    W0                      \n" /* Restore the critical nesting counter for the task. */ \
+                   "MOV    W0, _uxCriticalNesting  \n"                                                          \
+                   "POP    DSWPAG                  \n"                                                          \
+                   "POP    DSRPAG                  \n"                                                          \
+                   "POP    CORCON                  \n"                                                          \
+                   "POP    TBLPAG                  \n"                                                          \
+                   "POP    RCOUNT                  \n" /* Restore the registers from the stack. */              \
+                   "POP    W14                     \n"                                                          \
+                   "POP.D  W12                     \n"                                                          \
+                   "POP.D  W10                     \n"                                                          \
+                   "POP.D  W8                      \n"                                                          \
+                   "POP.D  W6                      \n"                                                          \
+                   "POP.D  W4                      \n"                                                          \
+                   "POP.D  W2                      \n"                                                          \
+                   "POP.D  W0                      \n"                                                          \
+                   "POP    SR                        " );
     #else /* __HAS_EDS__ */
-        #define portRESTORE_CONTEXT()                                                                                       \
-            asm volatile(   "MOV    _pxCurrentTCB, W0       \n" /* Restore the stack pointer for the task. */               \
-                            "MOV    [W0], W15               \n"                                                             \
-                            "POP    W0                      \n" /* Restore the critical nesting counter for the task. */    \
-                            "MOV    W0, _uxCriticalNesting  \n"                                                             \
-                            "POP    PSVPAG                  \n"                                                             \
-                            "POP    CORCON                  \n"                                                             \
-                            "POP    TBLPAG                  \n"                                                             \
-                            "POP    RCOUNT                  \n" /* Restore the registers from the stack. */                 \
-                            "POP    W14                     \n"                                                             \
-                            "POP.D  W12                     \n"                                                             \
-                            "POP.D  W10                     \n"                                                             \
-                            "POP.D  W8                      \n"                                                             \
-                            "POP.D  W6                      \n"                                                             \
-                            "POP.D  W4                      \n"                                                             \
-                            "POP.D  W2                      \n"                                                             \
-                            "POP.D  W0                      \n"                                                             \
-                            "POP    SR                        " );
-        #endif /* __HAS_EDS__ */
+        #define portRESTORE_CONTEXT()                                                                           \
+    asm volatile ( "MOV    _pxCurrentTCB, W0       \n" /* Restore the stack pointer for the task. */            \
+                   "MOV    [W0], W15               \n"                                                          \
+                   "POP    W0                      \n" /* Restore the critical nesting counter for the task. */ \
+                   "MOV    W0, _uxCriticalNesting  \n"                                                          \
+                   "POP    PSVPAG                  \n"                                                          \
+                   "POP    CORCON                  \n"                                                          \
+                   "POP    TBLPAG                  \n"                                                          \
+                   "POP    RCOUNT                  \n" /* Restore the registers from the stack. */              \
+                   "POP    W14                     \n"                                                          \
+                   "POP.D  W12                     \n"                                                          \
+                   "POP.D  W10                     \n"                                                          \
+                   "POP.D  W8                      \n"                                                          \
+                   "POP.D  W6                      \n"                                                          \
+                   "POP.D  W4                      \n"                                                          \
+                   "POP.D  W2                      \n"                                                          \
+                   "POP.D  W0                      \n"                                                          \
+                   "POP    SR                        " );
+    #endif /* __HAS_EDS__ */
 #endif /* defined( __PIC24E__ ) || defined ( __PIC24F__ ) || defined( __PIC24FK__ ) || defined( __PIC24H__ ) */
 
 #if defined( __dsPIC30F__ ) || defined( __dsPIC33F__ )
 
-    #define portRESTORE_CONTEXT()                                                                                       \
-        asm volatile(   "MOV    _pxCurrentTCB, W0       \n" /* Restore the stack pointer for the task. */               \
-                        "MOV    [W0], W15               \n"                                                             \
-                        "POP    W0                      \n" /* Restore the critical nesting counter for the task. */    \
-                        "MOV    W0, _uxCriticalNesting  \n"                                                             \
-                        "POP    PSVPAG                  \n"                                                             \
-                        "POP    CORCON                  \n"                                                             \
-                        "POP    DOENDH                  \n"                                                             \
-                        "POP    DOENDL                  \n"                                                             \
-                        "POP    DOSTARTH                \n"                                                             \
-                        "POP    DOSTARTL                \n"                                                             \
-                        "POP    DCOUNT                  \n"                                                             \
-                        "POP    ACCBU                   \n"                                                             \
-                        "POP    ACCBH                   \n"                                                             \
-                        "POP    ACCBL                   \n"                                                             \
-                        "POP    ACCAU                   \n"                                                             \
-                        "POP    ACCAH                   \n"                                                             \
-                        "POP    ACCAL                   \n"                                                             \
-                        "POP    TBLPAG                  \n"                                                             \
-                        "POP    RCOUNT                  \n" /* Restore the registers from the stack. */                 \
-                        "POP    W14                     \n"                                                             \
-                        "POP.D  W12                     \n"                                                             \
-                        "POP.D  W10                     \n"                                                             \
-                        "POP.D  W8                      \n"                                                             \
-                        "POP.D  W6                      \n"                                                             \
-                        "POP.D  W4                      \n"                                                             \
-                        "POP.D  W2                      \n"                                                             \
-                        "POP.D  W0                      \n"                                                             \
-                        "POP    SR                        " );
+    #define portRESTORE_CONTEXT()                                                                               \
+    asm volatile ( "MOV    _pxCurrentTCB, W0       \n" /* Restore the stack pointer for the task. */            \
+                   "MOV    [W0], W15               \n"                                                          \
+                   "POP    W0                      \n" /* Restore the critical nesting counter for the task. */ \
+                   "MOV    W0, _uxCriticalNesting  \n"                                                          \
+                   "POP    PSVPAG                  \n"                                                          \
+                   "POP    CORCON                  \n"                                                          \
+                   "POP    DOENDH                  \n"                                                          \
+                   "POP    DOENDL                  \n"                                                          \
+                   "POP    DOSTARTH                \n"                                                          \
+                   "POP    DOSTARTL                \n"                                                          \
+                   "POP    DCOUNT                  \n"                                                          \
+                   "POP    ACCBU                   \n"                                                          \
+                   "POP    ACCBH                   \n"                                                          \
+                   "POP    ACCBL                   \n"                                                          \
+                   "POP    ACCAU                   \n"                                                          \
+                   "POP    ACCAH                   \n"                                                          \
+                   "POP    ACCAL                   \n"                                                          \
+                   "POP    TBLPAG                  \n"                                                          \
+                   "POP    RCOUNT                  \n" /* Restore the registers from the stack. */              \
+                   "POP    W14                     \n"                                                          \
+                   "POP.D  W12                     \n"                                                          \
+                   "POP.D  W10                     \n"                                                          \
+                   "POP.D  W8                      \n"                                                          \
+                   "POP.D  W6                      \n"                                                          \
+                   "POP.D  W4                      \n"                                                          \
+                   "POP.D  W2                      \n"                                                          \
+                   "POP.D  W0                      \n"                                                          \
+                   "POP    SR                        " );
 
 #endif /* defined( __dsPIC30F__ ) || defined( __dsPIC33F__ ) */
 
 #ifndef portRESTORE_CONTEXT
     #error Unrecognised device selected
 
-    /* Note:  dsPIC parts with EDS are not supported as there is no easy way to
-    recover the hardware stacked copies for DOCOUNT, DOHIGH, DOLOW. */
+/* Note:  dsPIC parts with EDS are not supported as there is no easy way to
+ * recover the hardware stacked copies for DOCOUNT, DOHIGH, DOLOW. */
 #endif
 
 /*
@@ -160,56 +160,58 @@ void vApplicationSetupTickTimerInterrupt( void );
 /*
  * See header file for description.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
-uint16_t usCode;
-UBaseType_t i;
+    uint16_t usCode;
+    UBaseType_t i;
 
-const StackType_t xInitialStack[] =
-{
-    0x1111, /* W1 */
-    0x2222, /* W2 */
-    0x3333, /* W3 */
-    0x4444, /* W4 */
-    0x5555, /* W5 */
-    0x6666, /* W6 */
-    0x7777, /* W7 */
-    0x8888, /* W8 */
-    0x9999, /* W9 */
-    0xaaaa, /* W10 */
-    0xbbbb, /* W11 */
-    0xcccc, /* W12 */
-    0xdddd, /* W13 */
-    0xeeee, /* W14 */
-    0xcdce, /* RCOUNT */
-    0xabac, /* TBLPAG */
+    const StackType_t xInitialStack[] =
+    {
+        0x1111, /* W1 */
+        0x2222, /* W2 */
+        0x3333, /* W3 */
+        0x4444, /* W4 */
+        0x5555, /* W5 */
+        0x6666, /* W6 */
+        0x7777, /* W7 */
+        0x8888, /* W8 */
+        0x9999, /* W9 */
+        0xaaaa, /* W10 */
+        0xbbbb, /* W11 */
+        0xcccc, /* W12 */
+        0xdddd, /* W13 */
+        0xeeee, /* W14 */
+        0xcdce, /* RCOUNT */
+        0xabac, /* TBLPAG */
 
-    /* dsPIC specific registers. */
-    #if defined( __dsPIC30F__ ) || defined( __dsPIC33F__ )
-        0x0202, /* ACCAL */
-        0x0303, /* ACCAH */
-        0x0404, /* ACCAU */
-        0x0505, /* ACCBL */
-        0x0606, /* ACCBH */
-        0x0707, /* ACCBU */
-        0x0808, /* DCOUNT */
-        0x090a, /* DOSTARTL */
-        0x1010, /* DOSTARTH */
-        0x1110, /* DOENDL */
-        0x1212, /* DOENDH */
-    #endif
-};
+        /* dsPIC specific registers. */
+        #if defined( __dsPIC30F__ ) || defined( __dsPIC33F__ )
+            0x0202, /* ACCAL */
+            0x0303, /* ACCAH */
+            0x0404, /* ACCAU */
+            0x0505, /* ACCBL */
+            0x0606, /* ACCBH */
+            0x0707, /* ACCBU */
+            0x0808, /* DCOUNT */
+            0x090a, /* DOSTARTL */
+            0x1010, /* DOSTARTH */
+            0x1110, /* DOENDL */
+            0x1212, /* DOENDH */
+        #endif /* if defined( __dsPIC30F__ ) || defined( __dsPIC33F__ ) */
+    };
 
     /* Setup the stack as if a yield had occurred.
-
-    Save the low bytes of the program counter. */
+     *
+     * Save the low bytes of the program counter. */
     usCode = ( uint16_t ) pxCode;
     *pxTopOfStack = ( StackType_t ) usCode;
     pxTopOfStack++;
 
     /* Save the high byte of the program counter.  This will always be zero
-    here as it is passed in a 16bit pointer.  If the address is greater than
-    16 bits then the pointer will point to a jump table. */
+     * here as it is passed in a 16bit pointer.  If the address is greater than
+     * 16 bits then the pointer will point to a jump table. */
     *pxTopOfStack = ( StackType_t ) 0;
     pxTopOfStack++;
 
@@ -230,7 +232,7 @@ const StackType_t xInitialStack[] =
     *pxTopOfStack = CORCON;
     pxTopOfStack++;
 
-    #if defined(__HAS_EDS__)
+    #if defined( __HAS_EDS__ )
         *pxTopOfStack = DSRPAG;
         pxTopOfStack++;
         *pxTopOfStack = DSWPAG;
@@ -267,7 +269,7 @@ BaseType_t xPortStartScheduler( void )
 void vPortEndScheduler( void )
 {
     /* Not implemented in ports where there is nothing to return to.
-    Artificially force an assert. */
+     * Artificially force an assert. */
     configASSERT( uxCriticalNesting == 1000UL );
 }
 /*-----------------------------------------------------------*/
@@ -275,9 +277,9 @@ void vPortEndScheduler( void )
 /*
  * Setup a timer for a regular tick.
  */
-__attribute__(( weak )) void vApplicationSetupTickTimerInterrupt( void )
+__attribute__( ( weak ) ) void vApplicationSetupTickTimerInterrupt( void )
 {
-const uint32_t ulCompareMatch = ( ( configCPU_CLOCK_HZ / portTIMER_PRESCALE ) / configTICK_RATE_HZ ) - 1;
+    const uint32_t ulCompareMatch = ( ( configCPU_CLOCK_HZ / portTIMER_PRESCALE ) / configTICK_RATE_HZ ) - 1;
 
     /* Prescale of 8. */
     T1CON = 0;
@@ -314,6 +316,7 @@ void vPortExitCritical( void )
 {
     configASSERT( uxCriticalNesting );
     uxCriticalNesting--;
+
     if( uxCriticalNesting == 0 )
     {
         portENABLE_INTERRUPTS();
@@ -321,7 +324,7 @@ void vPortExitCritical( void )
 }
 /*-----------------------------------------------------------*/
 
-void __attribute__((__interrupt__, auto_psv)) configTICK_INTERRUPT_HANDLER( void )
+void __attribute__( ( __interrupt__, auto_psv ) ) configTICK_INTERRUPT_HANDLER( void )
 {
     /* Clear the timer interrupt. */
     IFS0bits.T1IF = 0;
diff --git a/portable/MPLAB/PIC24_dsPIC/portmacro.h b/portable/MPLAB/PIC24_dsPIC/portmacro.h
index 0cc26f206..7590d7c74 100644
--- a/portable/MPLAB/PIC24_dsPIC/portmacro.h
+++ b/portable/MPLAB/PIC24_dsPIC/portmacro.h
@@ -46,61 +46,63 @@
  */
 
 /* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint16_t
-#define portBASE_TYPE   short
-#define portPOINTER_SIZE_TYPE size_t
-#define SIZE_MAX    ( ( size_t ) -1 )
+#define portCHAR                 char
+#define portFLOAT                float
+#define portDOUBLE               double
+#define portLONG                 long
+#define portSHORT                short
+#define portSTACK_TYPE           uint16_t
+#define portBASE_TYPE            short
+#define portPOINTER_SIZE_TYPE    size_t
+#define SIZE_MAX                 ( ( size_t ) -1 )
 
-typedef portSTACK_TYPE StackType_t;
-typedef short BaseType_t;
-typedef unsigned short UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef short            BaseType_t;
+typedef unsigned short   UBaseType_t;
+
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffff
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
 /* 16-bit tick type on a 16-bit architecture, so reads of the tick count do
  * not need to be guarded with a critical section. */
-    #define portTICK_TYPE_IS_ATOMIC 1
-#elif ( configTICK_TYPE_WIDTH_IN_BITS  == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t             TickType_t;
-    #define portMAX_DELAY    ( TickType_t ) 0xffffffffUL
+    #define portTICK_TYPE_IS_ATOMIC    1
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+    typedef uint32_t TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portBYTE_ALIGNMENT          2
-#define portSTACK_GROWTH            1
-#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT    2
+#define portSTACK_GROWTH      1
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
 /*-----------------------------------------------------------*/
 
 /* Critical section management. */
 #define portDISABLE_INTERRUPTS()    SET_CPU_IPL( configKERNEL_INTERRUPT_PRIORITY ); __asm volatile ( "NOP" )
 #define portENABLE_INTERRUPTS()     SET_CPU_IPL( 0 )
 
-/* Note that exiting a critical sectino will set the IPL bits to 0, nomatter
-what their value was prior to entering the critical section. */
+/* Note that exiting a critical section will set the IPL bits to 0, no
+ *  matter what their value was prior to entering the critical section. */
 extern void vPortEnterCritical( void );
 extern void vPortExitCritical( void );
-#define portENTER_CRITICAL()        vPortEnterCritical()
-#define portEXIT_CRITICAL()         vPortExitCritical()
+#define portENTER_CRITICAL()    vPortEnterCritical()
+#define portEXIT_CRITICAL()     vPortExitCritical()
 /*-----------------------------------------------------------*/
 
 /* Task utilities. */
 extern void vPortYield( void );
-#define portYIELD()             asm volatile ( "CALL _vPortYield            \n"     \
-                                                "NOP                      " );
+#define portYIELD()                                 \
+    asm volatile ( "CALL _vPortYield            \n" \
+                   "NOP                      " );
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 /*-----------------------------------------------------------*/
 
 /* Required by the kernel aware debugger. */
@@ -108,7 +110,7 @@ extern void vPortYield( void );
     #define portREMOVE_STATIC_QUALIFIER
 #endif
 
-#define portNOP()               asm volatile ( "NOP" )
+#define portNOP()    asm volatile ( "NOP" )
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/MPLAB/PIC32MEC14xx/ISR_Support.h b/portable/MPLAB/PIC32MEC14xx/ISR_Support.h
index d2fa5bb4d..eda3e13e7 100644
--- a/portable/MPLAB/PIC32MEC14xx/ISR_Support.h
+++ b/portable/MPLAB/PIC32MEC14xx/ISR_Support.h
@@ -28,187 +28,187 @@
 
 #include "FreeRTOSConfig.h"
 
-#define portCONTEXT_SIZE 132
-#define portEPC_STACK_LOCATION 124
-#define portSTATUS_STACK_LOCATION 128
+#define portCONTEXT_SIZE             132
+#define portEPC_STACK_LOCATION       124
+#define portSTATUS_STACK_LOCATION    128
 
 #ifdef __LANGUAGE_ASSEMBLY__
 
 /******************************************************************/
-.macro  portSAVE_CONTEXT
+    .macro portSAVE_CONTEXT
 
-    /* Make room for the context. First save the current status so it can be
-    manipulated, and the cause and EPC registers so their original values are
-    captured. */
-    mfc0    k0, _CP0_CAUSE
-    addiu   sp, sp, -portCONTEXT_SIZE
-    mfc0    k1, _CP0_STATUS
+/* Make room for the context. First save the current status so it can be
+ * manipulated, and the cause and EPC registers so their original values are
+ * captured. */
+    mfc0 k0, _CP0_CAUSE
+    addiu sp, sp, -portCONTEXT_SIZE
+    mfc0 k1, _CP0_STATUS
 
-    /* Also save s6 and s5 so they can be used.  Any nesting interrupts should
-    maintain the values of these registers across the ISR. */
-    sw      s6, 44(sp)
-    sw      s5, 40(sp)
-    sw      k1, portSTATUS_STACK_LOCATION(sp)
+/* Also save s6 and s5 so they can be used.  Any nesting interrupts should
+ * maintain the values of these registers across the ISR. */
+    sw s6, 44 ( sp )
+    sw s5, 40 ( sp )
+    sw k1, portSTATUS_STACK_LOCATION( sp )
 
-    /* Prepare to enable interrupts above the current priority.
-    k0 = k0 >> 10. Moves RIPL[17:10] to [7:0] */
-    srl     k0, k0, 0xa
+/* Prepare to enable interrupts above the current priority.
+ * k0 = k0 >> 10. Moves RIPL[17:10] to [7:0] */
+    srl k0, k0, 0xa
 
-    /* Insert bit field. 7 bits k0[6:0] to k1[16:10] */
-    ins     k1, k0, 10, 7
+/* Insert bit field. 7 bits k0[6:0] to k1[16:10] */
+    ins k1, k0, 10, 7
 
-    /* Sets CP0.Status.IPL = CP0.Cause.RIPL
-    Copy the MSB of the IPL, but it would be an error if it was set anyway. */
-    srl     k0, k0, 0x7
+/* Sets CP0.Status.IPL = CP0.Cause.RIPL
+ * Copy the MSB of the IPL, but it would be an error if it was set anyway. */
+    srl k0, k0, 0x7
 
-    /* MSB of IPL is bit[18] of CP0.Status */
-    ins     k1, k0, 18, 1
+/* MSB of IPL is bit[18] of CP0.Status */
+    ins k1, k0, 18, 1
 
-    /* CP0.Status[5:1] = 0 b[5]=Rsvd, b[4]=UM,
-       b[3]=Rsvd, b[2]=ERL, b[1]=EXL
-       Setting EXL=0 allows higher priority interrupts
-       to preempt this handler */
-    ins     k1, zero, 1, 4
+/* CP0.Status[5:1] = 0 b[5]=Rsvd, b[4]=UM,
+ * b[3]=Rsvd, b[2]=ERL, b[1]=EXL
+ * Setting EXL=0 allows higher priority interrupts
+ * to preempt this handler */
+    ins k1, zero, 1, 4
 
 
-    /* s5 is used as the frame pointer. */
-    add     s5, zero, sp
+/* s5 is used as the frame pointer. */
+    add s5, zero, sp
 
-    /* Check the nesting count value. */
-    la      k0, uxInterruptNesting
-    lw      s6, (k0)
+/* Check the nesting count value. */
+    la k0, uxInterruptNesting
+    lw s6, ( k0 )
 
-    /* If the nesting count is 0 then swap to the the system stack, otherwise
-    the system stack is already being used. */
-    bne     s6, zero, 1f
+/* If the nesting count is 0 then swap to the the system stack, otherwise
+ * the system stack is already being used. */
+    bne s6, zero, 1f
     nop
 
-    /* Swap to the system stack. */
-    la      sp, xISRStackTop
-    lw      sp, (sp)
+/* Swap to the system stack. */
+    la sp, xISRStackTop
+    lw sp, ( sp )
 
-    /* Increment and save the nesting count. */
-1:  addiu   s6, s6, 1
-    sw      s6, 0(k0)
+/* Increment and save the nesting count. */
+    1 :  addiu s6, s6, 1
+    sw s6, 0 ( k0 )
 
-    /* s6 holds the EPC value, this is saved after interrupts are re-enabled. */
-    mfc0    s6, _CP0_EPC
+/* s6 holds the EPC value, this is saved after interrupts are re-enabled. */
+    mfc0 s6, _CP0_EPC
 
-    /* Re-enable interrupts. */
-    mtc0    k1, _CP0_STATUS
+/* Re-enable interrupts. */
+    mtc0 k1, _CP0_STATUS
 
-    /* Save the context into the space just created.  s6 is saved again
-    here as it now contains the EPC value.  No other s registers need be
-    saved. */
-    sw      ra, 120(s5) /* Return address (RA=R31) */
-    sw      s8, 116(s5) /* Frame Pointer (FP=R30) */
-    sw      t9, 112(s5)
-    sw      t8, 108(s5)
-    sw      t7, 104(s5)
-    sw      t6, 100(s5)
-    sw      t5, 96(s5)
-    sw      t4, 92(s5)
-    sw      t3, 88(s5)
-    sw      t2, 84(s5)
-    sw      t1, 80(s5)
-    sw      t0, 76(s5)
-    sw      a3, 72(s5)
-    sw      a2, 68(s5)
-    sw      a1, 64(s5)
-    sw      a0, 60(s5)
-    sw      v1, 56(s5)
-    sw      v0, 52(s5)
-    sw      s6, portEPC_STACK_LOCATION(s5)
-    sw      $1, 16(s5)
+/* Save the context into the space just created.  s6 is saved again
+ * here as it now contains the EPC value.  No other s registers need be
+ * saved. */
+    sw ra, 120 ( s5 ) /* Return address (RA=R31) */
+    sw s8, 116 ( s5 ) /* Frame Pointer (FP=R30) */
+    sw t9, 112 ( s5 )
+    sw t8, 108 ( s5 )
+    sw t7, 104 ( s5 )
+    sw t6, 100 ( s5 )
+    sw t5, 96 ( s5 )
+    sw t4, 92 ( s5 )
+    sw t3, 88 ( s5 )
+    sw t2, 84 ( s5 )
+    sw t1, 80 ( s5 )
+    sw t0, 76 ( s5 )
+    sw a3, 72 ( s5 )
+    sw a2, 68 ( s5 )
+    sw a1, 64 ( s5 )
+    sw a0, 60 ( s5 )
+    sw v1, 56 ( s5 )
+    sw v0, 52 ( s5 )
+    sw s6, portEPC_STACK_LOCATION( s5 )
+    sw $1, 16 ( s5 )
 
-    /* MEC14xx does not have DSP, removed 7 words */
-    mfhi    s6
-    sw      s6, 12(s5)
-    mflo    s6
-    sw      s6, 8(s5)
+/* MEC14xx does not have DSP, removed 7 words */
+    mfhi s6
+    sw s6, 12 ( s5 )
+    mflo s6
+    sw s6, 8 ( s5 )
 
-    /* Update the task stack pointer value if nesting is zero. */
-    la      s6, uxInterruptNesting
-    lw      s6, (s6)
-    addiu   s6, s6, -1
-    bne     s6, zero, 1f
+/* Update the task stack pointer value if nesting is zero. */
+    la s6, uxInterruptNesting
+    lw s6, ( s6 )
+    addiu s6, s6, -1
+    bne s6, zero, 1f
     nop
 
-    /* Save the stack pointer. */
-    la      s6, uxSavedTaskStackPointer
-    sw      s5, (s6)
-1:
+/* Save the stack pointer. */
+    la s6, uxSavedTaskStackPointer
+    sw s5, ( s6 )
+    1 :
     .endm
 
 /******************************************************************/
-.macro  portRESTORE_CONTEXT
+       .macro portRESTORE_CONTEXT
 
-    /* Restore the stack pointer from the TCB.  This is only done if the
-    nesting count is 1. */
-    la      s6, uxInterruptNesting
-    lw      s6, (s6)
-    addiu   s6, s6, -1
-    bne     s6, zero, 1f
+/* Restore the stack pointer from the TCB.  This is only done if the
+ * nesting count is 1. */
+    la s6, uxInterruptNesting
+    lw s6, ( s6 )
+    addiu s6, s6, -1
+    bne s6, zero, 1f
     nop
-    la      s6, uxSavedTaskStackPointer
-    lw      s5, (s6)
+    la s6, uxSavedTaskStackPointer
+    lw s5, ( s6 )
 
-    /* Restore the context.
-    MCHP MEC14xx does not include DSP */
-1:
-    lw      s6, 8(s5)
-    mtlo    s6
-    lw      s6, 12(s5)
-    mthi    s6
-    lw      $1, 16(s5)
+/* Restore the context.
+ * MCHP MEC14xx does not include DSP */
+    1 :
+    lw s6, 8 ( s5 )
+    mtlo s6
+    lw s6, 12 ( s5 )
+    mthi s6
+    lw $1, 16 ( s5 )
 
-    /* s6 is loaded as it was used as a scratch register and therefore saved
-    as part of the interrupt context. */
-    lw      s6, 44(s5)
-    lw      v0, 52(s5)
-    lw      v1, 56(s5)
-    lw      a0, 60(s5)
-    lw      a1, 64(s5)
-    lw      a2, 68(s5)
-    lw      a3, 72(s5)
-    lw      t0, 76(s5)
-    lw      t1, 80(s5)
-    lw      t2, 84(s5)
-    lw      t3, 88(s5)
-    lw      t4, 92(s5)
-    lw      t5, 96(s5)
-    lw      t6, 100(s5)
-    lw      t7, 104(s5)
-    lw      t8, 108(s5)
-    lw      t9, 112(s5)
-    lw      s8, 116(s5)
-    lw      ra, 120(s5)
+/* s6 is loaded as it was used as a scratch register and therefore saved
+ * as part of the interrupt context. */
+    lw s6, 44 ( s5 )
+    lw v0, 52 ( s5 )
+    lw v1, 56 ( s5 )
+    lw a0, 60 ( s5 )
+    lw a1, 64 ( s5 )
+    lw a2, 68 ( s5 )
+    lw a3, 72 ( s5 )
+    lw t0, 76 ( s5 )
+    lw t1, 80 ( s5 )
+    lw t2, 84 ( s5 )
+    lw t3, 88 ( s5 )
+    lw t4, 92 ( s5 )
+    lw t5, 96 ( s5 )
+    lw t6, 100 ( s5 )
+    lw t7, 104 ( s5 )
+    lw t8, 108 ( s5 )
+    lw t9, 112 ( s5 )
+    lw s8, 116 ( s5 )
+    lw ra, 120 ( s5 )
 
-    /* Protect access to the k registers, and others. */
+/* Protect access to the k registers, and others. */
     di
     ehb
 
-    /* Decrement the nesting count. */
-    la      k0, uxInterruptNesting
-    lw      k1, (k0)
-    addiu   k1, k1, -1
-    sw      k1, 0(k0)
+/* Decrement the nesting count. */
+    la k0, uxInterruptNesting
+    lw k1, ( k0 )
+    addiu k1, k1, -1
+    sw k1, 0 ( k0 )
 
-    lw      k0, portSTATUS_STACK_LOCATION(s5)
-    lw      k1, portEPC_STACK_LOCATION(s5)
+    lw k0, portSTATUS_STACK_LOCATION( s5 )
+    lw k1, portEPC_STACK_LOCATION( s5 )
 
-    /* Leave the stack in its original state.  First load sp from s5, then
-    restore s5 from the stack. */
-    add     sp, zero, s5
-    lw      s5, 40(sp)
-    addiu   sp, sp, portCONTEXT_SIZE
+/* Leave the stack in its original state.  First load sp from s5, then
+ * restore s5 from the stack. */
+    add sp, zero, s5
+    lw s5, 40 ( sp )
+    addiu sp, sp, portCONTEXT_SIZE
 
-    mtc0    k0, _CP0_STATUS
-    mtc0    k1, _CP0_EPC
+    mtc0 k0, _CP0_STATUS
+    mtc0 k1, _CP0_EPC
     ehb
     eret
     nop
 
-    .endm
+       .endm
 
 #endif /* #ifdef __LANGUAGE_ASSEMBLY__ */
diff --git a/portable/MPLAB/PIC32MEC14xx/port.c b/portable/MPLAB/PIC32MEC14xx/port.c
index ebe9bdb7c..5eb6e567b 100644
--- a/portable/MPLAB/PIC32MEC14xx/port.c
+++ b/portable/MPLAB/PIC32MEC14xx/port.c
@@ -27,8 +27,8 @@
  */
 
 /*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the PIC32MEC14xx  port.
- *----------------------------------------------------------*/
+* Implementation of functions defined in portable.h for the PIC32MEC14xx  port.
+*----------------------------------------------------------*/
 
 /* Scheduler include files. */
 #include "FreeRTOS.h"
@@ -38,57 +38,57 @@
 #include <xc.h>
 #include <cp0defs.h>
 
-#if !defined(__MEC__)
+#if !defined( __MEC__ )
     #error This port is designed to work with XC32 on MEC14xx.  Please update your C compiler version or settings.
 #endif
 
-#if( ( configMAX_SYSCALL_INTERRUPT_PRIORITY >= 0x7 ) || ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 ) )
+#if ( ( configMAX_SYSCALL_INTERRUPT_PRIORITY >= 0x7 ) || ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 ) )
     #error configMAX_SYSCALL_INTERRUPT_PRIORITY must be less than 7 and greater than 0
 #endif
 
 /* Bits within various registers. */
-#define portIE_BIT                  ( 0x00000001 )
-#define portEXL_BIT                 ( 0x00000002 )
+#define portIE_BIT                         ( 0x00000001 )
+#define portEXL_BIT                        ( 0x00000002 )
 
 /* The EXL bit is set to ensure interrupts do not occur while the context of
-the first task is being restored.  MEC14xx does not have DSP HW. */
-#define portINITIAL_SR              ( portIE_BIT | portEXL_BIT )
+ * the first task is being restored.  MEC14xx does not have DSP HW. */
+#define portINITIAL_SR                     ( portIE_BIT | portEXL_BIT )
 
 /* MEC14xx RTOS Timer MMCR's. */
-#define portMMCR_RTMR_PRELOAD   *((volatile uint32_t *)(0xA0007404ul))
-#define portMMCR_RTMR_CONTROL   *((volatile uint32_t *)(0xA0007408ul))
+#define portMMCR_RTMR_PRELOAD              *( ( volatile uint32_t * ) ( 0xA0007404ul ) )
+#define portMMCR_RTMR_CONTROL              *( ( volatile uint32_t * ) ( 0xA0007408ul ) )
 
 /* MEC14xx JTVIC external interrupt controller is mapped to M14K closely-coupled
-peripheral space. */
-#define portGIRQ23_RTOS_TIMER_BITPOS    ( 4 )
-#define portGIRQ23_RTOS_TIMER_MASK      ( 1ul << ( portGIRQ23_RTOS_TIMER_BITPOS ) )
-#define portMMCR_JTVIC_GIRQ23_SRC       *((volatile uint32_t *)(0xBFFFC0F0ul))
-#define portMMCR_JTVIC_GIRQ23_SETEN     *((volatile uint32_t *)(0xBFFFC0F4ul))
-#define portMMCR_JTVIC_GIRQ23_PRIA      *((volatile uint32_t *)(0xBFFFC3F0ul))
+ * peripheral space. */
+#define portGIRQ23_RTOS_TIMER_BITPOS       ( 4 )
+#define portGIRQ23_RTOS_TIMER_MASK         ( 1ul << ( portGIRQ23_RTOS_TIMER_BITPOS ) )
+#define portMMCR_JTVIC_GIRQ23_SRC          *( ( volatile uint32_t * ) ( 0xBFFFC0F0ul ) )
+#define portMMCR_JTVIC_GIRQ23_SETEN        *( ( volatile uint32_t * ) ( 0xBFFFC0F4ul ) )
+#define portMMCR_JTVIC_GIRQ23_PRIA         *( ( volatile uint32_t * ) ( 0xBFFFC3F0ul ) )
 
 /* MIPS Software Interrupts are routed through JTVIC GIRQ24 */
-#define portGIRQ24_M14K_SOFTIRQ0_BITPOS ( 1 )
-#define portGIRQ24_M14K_SOFTIRQ0_MASK   ( 1ul << ( portGIRQ24_M14K_SOFTIRQ0_BITPOS ) )
-#define portMMCR_JTVIC_GIRQ24_SRC       *((volatile uint32_t *)(0xBFFFC100ul))
-#define portMMCR_JTVIC_GIRQ24_SETEN     *((volatile uint32_t *)(0xBFFFC104ul))
-#define portMMCR_JTVIC_GIRQ24_PRIA      *((volatile uint32_t *)(0xBFFFC400ul))
+#define portGIRQ24_M14K_SOFTIRQ0_BITPOS    ( 1 )
+#define portGIRQ24_M14K_SOFTIRQ0_MASK      ( 1ul << ( portGIRQ24_M14K_SOFTIRQ0_BITPOS ) )
+#define portMMCR_JTVIC_GIRQ24_SRC          *( ( volatile uint32_t * ) ( 0xBFFFC100ul ) )
+#define portMMCR_JTVIC_GIRQ24_SETEN        *( ( volatile uint32_t * ) ( 0xBFFFC104ul ) )
+#define portMMCR_JTVIC_GIRQ24_PRIA         *( ( volatile uint32_t * ) ( 0xBFFFC400ul ) )
 
 /*
-By default port.c generates its tick interrupt from the RTOS timer.  The user
-can override this behaviour by:
-    1: Providing their own implementation of vApplicationSetupTickTimerInterrupt(),
-       which is the function that configures the timer.  The function is defined
-       as a weak symbol in this file so if the same function name is used in the
-       application code then the version in the application code will be linked
-       into the application in preference to the version defined in this file.
-    2: Provide a vector implementation in port_asm.S that overrides the default
-       behaviour for the specified interrupt vector.
-    3: Specify the correct bit to clear the interrupt during the timer interrupt
-       handler.
-*/
+ * By default port.c generates its tick interrupt from the RTOS timer.  The user
+ * can override this behaviour by:
+ *  1: Providing their own implementation of vApplicationSetupTickTimerInterrupt(),
+ *     which is the function that configures the timer.  The function is defined
+ *     as a weak symbol in this file so if the same function name is used in the
+ *     application code then the version in the application code will be linked
+ *     into the application in preference to the version defined in this file.
+ *  2: Provide a vector implementation in port_asm.S that overrides the default
+ *     behaviour for the specified interrupt vector.
+ *  3: Specify the correct bit to clear the interrupt during the timer interrupt
+ *     handler.
+ */
 #ifndef configTICK_INTERRUPT_VECTOR
-    #define configTICK_INTERRUPT_VECTOR girq23_b4
-    #define configCLEAR_TICK_TIMER_INTERRUPT() portMMCR_JTVIC_GIRQ23_SRC = portGIRQ23_RTOS_TIMER_MASK
+    #define configTICK_INTERRUPT_VECTOR    girq23_b4
+    #define configCLEAR_TICK_TIMER_INTERRUPT()    portMMCR_JTVIC_GIRQ23_SRC = portGIRQ23_RTOS_TIMER_MASK
 #else
     #ifndef configCLEAR_TICK_TIMER_INTERRUPT
         #error If configTICK_INTERRUPT_VECTOR is defined in application code then configCLEAR_TICK_TIMER_INTERRUPT must also be defined in application code.
@@ -96,34 +96,36 @@ can override this behaviour by:
 #endif
 
 /* Let the user override the pre-loading of the initial RA with the address of
-prvTaskExitError() in case it messes up unwinding of the stack in the debugger -
-in which case configTASK_RETURN_ADDRESS can be defined as 0 (NULL). */
+ * prvTaskExitError() in case it messes up unwinding of the stack in the debugger -
+ * in which case configTASK_RETURN_ADDRESS can be defined as 0 (NULL). */
 #ifdef configTASK_RETURN_ADDRESS
-    #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
+    #define portTASK_RETURN_ADDRESS    configTASK_RETURN_ADDRESS
 #else
-    #define portTASK_RETURN_ADDRESS prvTaskExitError
+    #define portTASK_RETURN_ADDRESS    prvTaskExitError
 #endif
 
 /* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task
-stack checking.  A problem in the ISR stack will trigger an assert, not call the
-stack overflow hook function (because the stack overflow hook is specific to a
-task stack, not the ISR stack). */
-#if( configCHECK_FOR_STACK_OVERFLOW > 2 )
+ * stack checking.  A problem in the ISR stack will trigger an assert, not call the
+ * stack overflow hook function (because the stack overflow hook is specific to a
+ * task stack, not the ISR stack). */
+#if ( configCHECK_FOR_STACK_OVERFLOW > 2 )
 
-    /* Don't use 0xa5 as the stack fill bytes as that is used by the kernel for
-    the task stacks, and so will legitimately appear in many positions within
-    the ISR stack. */
-    #define portISR_STACK_FILL_BYTE 0xee
+/* Don't use 0xa5 as the stack fill bytes as that is used by the kernel for
+ * the task stacks, and so will legitimately appear in many positions within
+ * the ISR stack. */
+    #define portISR_STACK_FILL_BYTE    0xee
 
-    static const uint8_t ucExpectedStackBytes[] = {
-                            portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,     \
-                            portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,     \
-                            portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,     \
-                            portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,     \
-                            portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE };   \
+    static const uint8_t ucExpectedStackBytes[] =
+    {
+        portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
+        portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
+        portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
+        portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
+        portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE
+    }; \
 
-    #define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
-#else
+    #define portCHECK_ISR_STACK()    configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
+#else /* if ( configCHECK_FOR_STACK_OVERFLOW > 2 ) */
     /* Define the function away. */
     #define portCHECK_ISR_STACK()
 #endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
@@ -139,7 +141,7 @@ static void prvTaskExitError( void );
 /*-----------------------------------------------------------*/
 
 /* Records the interrupt nesting depth.  This is initialised to one as it is
-decremented to 0 when the first task starts. */
+ * decremented to 0 when the first task starts. */
 volatile UBaseType_t uxInterruptNesting = 0x01;
 
 /* Stores the task stack pointer when a switch is made to use the system stack. */
@@ -149,7 +151,7 @@ UBaseType_t uxSavedTaskStackPointer = 0;
 StackType_t xISRStack[ configISR_STACK_SIZE ] = { 0 };
 
 /* The top of stack value ensures there is enough space to store 6 registers on
-the callers stack, as some functions seem to want to do this. */
+ * the callers stack, as some functions seem to want to do this. */
 const StackType_t * const xISRStackTop = &( xISRStack[ configISR_STACK_SIZE - 7 ] );
 
 /*-----------------------------------------------------------*/
@@ -157,30 +159,32 @@ const StackType_t * const xISRStackTop = &( xISRStack[ configISR_STACK_SIZE - 7
 /*
  * See header file for description.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
     /* Ensure byte alignment is maintained when leaving this function. */
     pxTopOfStack--;
 
-    *pxTopOfStack = (StackType_t) 0xDEADBEEF;
+    *pxTopOfStack = ( StackType_t ) 0xDEADBEEF;
     pxTopOfStack--;
 
-    *pxTopOfStack = (StackType_t) 0x12345678;   /* Word to which the stack pointer will be left pointing after context restore. */
+    *pxTopOfStack = ( StackType_t ) 0x12345678; /* Word to which the stack pointer will be left pointing after context restore. */
     pxTopOfStack--;
 
-    *pxTopOfStack = (StackType_t) ulPortGetCP0Cause();
+    *pxTopOfStack = ( StackType_t ) ulPortGetCP0Cause();
     pxTopOfStack--;
 
-    *pxTopOfStack = (StackType_t) portINITIAL_SR;   /* CP0_STATUS */
+    *pxTopOfStack = ( StackType_t ) portINITIAL_SR; /* CP0_STATUS */
     pxTopOfStack--;
 
-    *pxTopOfStack = (StackType_t) pxCode;       /* CP0_EPC */
+    *pxTopOfStack = ( StackType_t ) pxCode; /* CP0_EPC */
     pxTopOfStack--;
 
-    *pxTopOfStack = (StackType_t) portTASK_RETURN_ADDRESS;  /* ra */
+    *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* ra */
     pxTopOfStack -= 15;
 
-    *pxTopOfStack = (StackType_t) pvParameters; /* Parameters to pass in. */
+    *pxTopOfStack = ( StackType_t ) pvParameters; /* Parameters to pass in. */
     pxTopOfStack -= 15;
 
     return pxTopOfStack;
@@ -189,9 +193,10 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
 
 static __inline uint32_t prvDisableInterrupt( void )
 {
-uint32_t prev_state;
+    uint32_t prev_state;
+
+    __asm volatile ( "di %0; ehb" : "=r" ( prev_state )::"memory" );
 
-    __asm volatile( "di %0; ehb" : "=r" ( prev_state ) :: "memory" );
     return prev_state;
 }
 /*-----------------------------------------------------------*/
@@ -199,14 +204,17 @@ uint32_t prev_state;
 static void prvTaskExitError( void )
 {
     /* A function that implements a task must not exit or attempt to return to
-    its caller as there is nothing to return to.  If a task wants to exit it
-    should instead call vTaskDelete( NULL ).
-
-    Artificially force an assert() to be triggered if configASSERT() is
-    defined, then stop here so application writers can catch the error. */
+     * its caller as there is nothing to return to.  If a task wants to exit it
+     * should instead call vTaskDelete( NULL ).
+     *
+     * Artificially force an assert() to be triggered if configASSERT() is
+     * defined, then stop here so application writers can catch the error. */
     configASSERT( uxSavedTaskStackPointer == 0UL );
     portDISABLE_INTERRUPTS();
-    for( ;; );
+
+    for( ; ; )
+    {
+    }
 }
 /*-----------------------------------------------------------*/
 
@@ -218,10 +226,10 @@ static void prvTaskExitError( void )
  * ensure the RTOS provided tick interrupt handler is installed on the correct
  * vector number.
  */
-__attribute__(( weak )) void vApplicationSetupTickTimerInterrupt( void )
+__attribute__( ( weak ) ) void vApplicationSetupTickTimerInterrupt( void )
 {
 /* MEC14xx RTOS Timer whose input clock is 32KHz. */
-const uint32_t ulPreload = ( 32768ul / ( configTICK_RATE_HZ ) );
+    const uint32_t ulPreload = ( 32768ul / ( configTICK_RATE_HZ ) );
 
     configASSERT( ulPreload != 0UL );
 
@@ -240,18 +248,18 @@ const uint32_t ulPreload = ( 32768ul / ( configTICK_RATE_HZ ) );
 }
 /*-----------------------------------------------------------*/
 
-void vPortEndScheduler(void)
+void vPortEndScheduler( void )
 {
     /* Not implemented in ports where there is nothing to return to.
-    Artificially force an assert. */
+     * Artificially force an assert. */
     configASSERT( uxInterruptNesting == 1000UL );
 }
 /*-----------------------------------------------------------*/
 
 BaseType_t xPortStartScheduler( void )
 {
-extern void vPortStartFirstTask( void );
-extern void *pxCurrentTCB;
+    extern void vPortStartFirstTask( void );
+    extern void * pxCurrentTCB;
 
     #if ( configCHECK_FOR_STACK_OVERFLOW > 2 )
     {
@@ -261,29 +269,29 @@ extern void *pxCurrentTCB;
     #endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
 
     /* Clear the software interrupt flag. */
-    portMMCR_JTVIC_GIRQ24_SRC = (portGIRQ24_M14K_SOFTIRQ0_MASK);
+    portMMCR_JTVIC_GIRQ24_SRC = ( portGIRQ24_M14K_SOFTIRQ0_MASK );
 
     /* Set software timer priority.  Each GIRQn has one nibble containing its
-    priority */
-    portMMCR_JTVIC_GIRQ24_PRIA &= ~(0xF0ul);
+     * priority */
+    portMMCR_JTVIC_GIRQ24_PRIA &= ~( 0xF0ul );
     portMMCR_JTVIC_GIRQ24_PRIA |= ( portIPL_TO_CODE( configKERNEL_INTERRUPT_PRIORITY ) << 4 );
 
     /* Enable software interrupt. */
     portMMCR_JTVIC_GIRQ24_SETEN = ( portGIRQ24_M14K_SOFTIRQ0_MASK );
 
     /* Setup the timer to generate the tick.  Interrupts will have been disabled
-    by the time we get here. */
+     * by the time we get here. */
     vApplicationSetupTickTimerInterrupt();
 
     /* Start the highest priority task that has been created so far.  Its stack
-    location is loaded into uxSavedTaskStackPointer. */
+     * location is loaded into uxSavedTaskStackPointer. */
     uxSavedTaskStackPointer = *( UBaseType_t * ) pxCurrentTCB;
     vPortStartFirstTask();
 
     /* Should never get here as the tasks will now be executing!  Call the task
-    exit error function to prevent compiler warnings about a static function
-    not being called in the case that the application writer overrides this
-    functionality by defining configTASK_RETURN_ADDRESS. */
+     * exit error function to prevent compiler warnings about a static function
+     * not being called in the case that the application writer overrides this
+     * functionality by defining configTASK_RETURN_ADDRESS. */
     prvTaskExitError();
 
     return pdFALSE;
@@ -292,8 +300,8 @@ extern void *pxCurrentTCB;
 
 void vPortIncrementTick( void )
 {
-UBaseType_t uxSavedStatus;
-uint32_t ulCause;
+    UBaseType_t uxSavedStatus;
+    uint32_t ulCause;
 
     uxSavedStatus = uxPortSetInterruptMaskFromISR();
     {
@@ -317,17 +325,17 @@ uint32_t ulCause;
 
 UBaseType_t uxPortSetInterruptMaskFromISR( void )
 {
-UBaseType_t uxSavedStatusRegister;
+    UBaseType_t uxSavedStatusRegister;
 
     prvDisableInterrupt();
     uxSavedStatusRegister = ulPortGetCP0Status() | 0x01;
 
     /* This clears the IPL bits, then sets them to
-    configMAX_SYSCALL_INTERRUPT_PRIORITY.  This function should not be called
-    from an interrupt that has a priority above
-    configMAX_SYSCALL_INTERRUPT_PRIORITY so, when used correctly, the action
-    can only result in the IPL being unchanged or raised, and therefore never
-    lowered. */
+     * configMAX_SYSCALL_INTERRUPT_PRIORITY.  This function should not be called
+     * from an interrupt that has a priority above
+     * configMAX_SYSCALL_INTERRUPT_PRIORITY so, when used correctly, the action
+     * can only result in the IPL being unchanged or raised, and therefore never
+     * lowered. */
     vPortSetCP0Status( ( ( uxSavedStatusRegister & ( ~portALL_IPL_BITS ) ) ) | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) );
 
     return uxSavedStatusRegister;
diff --git a/portable/MPLAB/PIC32MEC14xx/portmacro.h b/portable/MPLAB/PIC32MEC14xx/portmacro.h
index 9e00a1c05..e20d7b68e 100644
--- a/portable/MPLAB/PIC32MEC14xx/portmacro.h
+++ b/portable/MPLAB/PIC32MEC14xx/portmacro.h
@@ -46,23 +46,23 @@
  */
 
 /* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint32_t
-#define portBASE_TYPE   long
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
-#elif ( configTICK_TYPE_WIDTH_IN_BITS  == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t             TickType_t;
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+    typedef uint32_t     TickType_t;
     #define portMAX_DELAY    ( TickType_t ) 0xffffffffUL
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -70,15 +70,16 @@ typedef unsigned long UBaseType_t;
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portBYTE_ALIGNMENT  8
-#define portSTACK_GROWTH    -1
-#define portTICK_PERIOD_MS  ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT    8
+#define portSTACK_GROWTH      -1
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
 /*-----------------------------------------------------------*/
 
 /* Critical section management. */
 #define portIPL_SHIFT       ( 10UL )
+
 /* Don't straddle the CEE bit.  Interrupts calling FreeRTOS functions should
-never have higher IPL bits set anyway. */
+ * never have higher IPL bits set anyway. */
 #define portALL_IPL_BITS    ( 0x7FUL << portIPL_SHIFT )
 #define portSW0_BIT         ( 0x01 << 8 )
 
@@ -90,38 +91,38 @@ never have higher IPL bits set anyway. */
 
 static inline uint32_t ulPortGetCP0Status( void )
 {
-uint32_t rv;
+    uint32_t rv;
 
-    __asm volatile(
-            "\n\t"
-            "mfc0 %0,$12,0      \n\t"
-            : "=r" ( rv ) :: );
+    __asm volatile (
+        "\n\t"
+        "mfc0 %0,$12,0      \n\t"
+        : "=r" ( rv )::);
 
     return rv;
 }
 /*-----------------------------------------------------------*/
 
-static inline void vPortSetCP0Status( uint32_t new_status)
+static inline void vPortSetCP0Status( uint32_t new_status )
 {
     ( void ) new_status;
 
-    __asm__ __volatile__(
-            "\n\t"
-            "mtc0 %0,$12,0      \n\t"
-            "ehb                \n\t"
-            :
-            :"r" ( new_status ) : );
+    __asm__ __volatile__ (
+        "\n\t"
+        "mtc0 %0,$12,0      \n\t"
+        "ehb                \n\t"
+        :
+        : "r" ( new_status ) : );
 }
 /*-----------------------------------------------------------*/
 
 static inline uint32_t ulPortGetCP0Cause( void )
 {
-uint32_t rv;
+    uint32_t rv;
 
-    __asm volatile(
-            "\n\t"
-            "mfc0 %0,$13,0      \n\t"
-            : "=r" ( rv ) :: );
+    __asm volatile (
+        "\n\t"
+        "mfc0 %0,$13,0      \n\t"
+        : "=r" ( rv )::);
 
     return rv;
 }
@@ -131,86 +132,86 @@ static inline void vPortSetCP0Cause( uint32_t new_cause )
 {
     ( void ) new_cause;
 
-    __asm__ __volatile__(
-            "\n\t"
-            "mtc0 %0,$13,0      \n\t"
-            "ehb                \n\t"
-            :
-            :"r" ( new_cause ) : );
+    __asm__ __volatile__ (
+        "\n\t"
+        "mtc0 %0,$13,0      \n\t"
+        "ehb                \n\t"
+        :
+        : "r" ( new_cause ) : );
 }
 /*-----------------------------------------------------------*/
 
 /* This clears the IPL bits, then sets them to
-configMAX_SYSCALL_INTERRUPT_PRIORITY.  An extra check is performed if
-configASSERT() is defined to ensure an assertion handler does not inadvertently
-attempt to lower the IPL when the call to assert was triggered because the IPL
-value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY when an ISR
-safe FreeRTOS API function was executed.  ISR safe FreeRTOS API functions are
-those that end in FromISR.  FreeRTOS maintains a separate interrupt API to
-ensure API function and interrupt entry is as fast and as simple as possible. */
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.  An extra check is performed if
+ * configASSERT() is defined to ensure an assertion handler does not inadvertently
+ * attempt to lower the IPL when the call to assert was triggered because the IPL
+ * value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY when an ISR
+ * safe FreeRTOS API function was executed.  ISR safe FreeRTOS API functions are
+ * those that end in FromISR.  FreeRTOS maintains a separate interrupt API to
+ * ensure API function and interrupt entry is as fast and as simple as possible. */
 #ifdef configASSERT
-    #define portDISABLE_INTERRUPTS()                                                                            \
-    {                                                                                                           \
-    uint32_t ulStatus;                                                                                          \
-        /* Mask interrupts at and below the kernel interrupt priority. */                                       \
-        ulStatus = ulPortGetCP0Status();                                                                        \
-        /* Is the current IPL below configMAX_SYSCALL_INTERRUPT_PRIORITY? */                                    \
-        if( ( ( ulStatus & portALL_IPL_BITS ) >> portIPL_SHIFT ) < configMAX_SYSCALL_INTERRUPT_PRIORITY )       \
-        {                                                                                                       \
-            ulStatus &= ~portALL_IPL_BITS;                                                                      \
-            vPortSetCP0Status( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) );      \
-        }                                                                                                       \
+    #define portDISABLE_INTERRUPTS()                                                                       \
+    {                                                                                                      \
+        uint32_t ulStatus;                                                                                 \
+        /* Mask interrupts at and below the kernel interrupt priority. */                                  \
+        ulStatus = ulPortGetCP0Status();                                                                   \
+        /* Is the current IPL below configMAX_SYSCALL_INTERRUPT_PRIORITY? */                               \
+        if( ( ( ulStatus & portALL_IPL_BITS ) >> portIPL_SHIFT ) < configMAX_SYSCALL_INTERRUPT_PRIORITY )  \
+        {                                                                                                  \
+            ulStatus &= ~portALL_IPL_BITS;                                                                 \
+            vPortSetCP0Status( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
+        }                                                                                                  \
     }
 #else /* configASSERT */
-    #define portDISABLE_INTERRUPTS()                                                                            \
-    {                                                                                                           \
-    uint32_t ulStatus;                                                                                          \
-        /* Mask interrupts at and below the kernel interrupt priority. */                                       \
-        ulStatus = ulPortGetCP0Status();                                                                        \
-        ulStatus &= ~portALL_IPL_BITS;                                                                          \
-        vPortSetCP0Status( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) );          \
+    #define portDISABLE_INTERRUPTS()                                                                   \
+    {                                                                                                  \
+        uint32_t ulStatus;                                                                             \
+        /* Mask interrupts at and below the kernel interrupt priority. */                              \
+        ulStatus = ulPortGetCP0Status();                                                               \
+        ulStatus &= ~portALL_IPL_BITS;                                                                 \
+        vPortSetCP0Status( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
     }
 #endif /* configASSERT */
 
-#define portENABLE_INTERRUPTS()             \
-{                                           \
-uint32_t ulStatus;                          \
-    /* Unmask all interrupts. */            \
-    ulStatus = ulPortGetCP0Status();        \
-    ulStatus &= ~portALL_IPL_BITS;          \
-    vPortSetCP0Status( ulStatus );          \
-}
+#define portENABLE_INTERRUPTS()          \
+    {                                    \
+        uint32_t ulStatus;               \
+        /* Unmask all interrupts. */     \
+        ulStatus = ulPortGetCP0Status(); \
+        ulStatus &= ~portALL_IPL_BITS;   \
+        vPortSetCP0Status( ulStatus );   \
+    }
 
 
 extern void vTaskEnterCritical( void );
 extern void vTaskExitCritical( void );
-#define portCRITICAL_NESTING_IN_TCB 1
-#define portENTER_CRITICAL()        vTaskEnterCritical()
-#define portEXIT_CRITICAL()         vTaskExitCritical()
+#define portCRITICAL_NESTING_IN_TCB    1
+#define portENTER_CRITICAL()    vTaskEnterCritical()
+#define portEXIT_CRITICAL()     vTaskExitCritical()
 
 extern UBaseType_t uxPortSetInterruptMaskFromISR();
 extern void vPortClearInterruptMaskFromISR( UBaseType_t );
-#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMaskFromISR()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) vPortClearInterruptMaskFromISR( uxSavedStatusRegister )
+#define portSET_INTERRUPT_MASK_FROM_ISR()                             uxPortSetInterruptMaskFromISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister )    vPortClearInterruptMaskFromISR( uxSavedStatusRegister )
 
 #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-    #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+    #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
 #endif
 
 #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
 
-    /* Check the configuration. */
-    #if( configMAX_PRIORITIES > 32 )
+/* Check the configuration. */
+    #if ( configMAX_PRIORITIES > 32 )
         #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
     #endif
 
-    /* Store/clear the ready priorities in a bit map. */
-    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+/* Store/clear the ready priorities in a bit map. */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 
-    /*-----------------------------------------------------------*/
+/*-----------------------------------------------------------*/
 
-    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - _clz( ( uxReadyPriorities ) ) )
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31 - _clz( ( uxReadyPriorities ) ) )
 
 #endif /* taskRECORD_READY_PRIORITY */
 
@@ -218,28 +219,28 @@ extern void vPortClearInterruptMaskFromISR( UBaseType_t );
 
 /* Task utilities. */
 
-#define portYIELD()                         \
-{                                           \
-uint32_t ulCause;                           \
-    /* Trigger software interrupt. */       \
-    ulCause = ulPortGetCP0Cause();          \
-    ulCause |= portSW0_BIT;                 \
-    vPortSetCP0Cause( ulCause );            \
-}
+#define portYIELD()                       \
+    {                                     \
+        uint32_t ulCause;                 \
+        /* Trigger software interrupt. */ \
+        ulCause = ulPortGetCP0Cause();    \
+        ulCause |= portSW0_BIT;           \
+        vPortSetCP0Cause( ulCause );      \
+    }
 
 extern volatile UBaseType_t uxInterruptNesting;
-#define portASSERT_IF_IN_ISR() configASSERT( uxInterruptNesting == 0 )
+#define portASSERT_IF_IN_ISR()    configASSERT( uxInterruptNesting == 0 )
 
-#define portNOP() __asm volatile ( "nop" )
+#define portNOP()                 __asm volatile ( "nop" )
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn))
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters ) __attribute__( ( noreturn ) )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 /*-----------------------------------------------------------*/
 
-#define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired ) { portYIELD(); } } while( 0 )
+#define portEND_SWITCHING_ISR( xSwitchRequired )              do { if( xSwitchRequired ) { portYIELD(); } } while( 0 )
 
 /* Required by the kernel aware debugger. */
 #ifdef __DEBUG
diff --git a/portable/MPLAB/PIC32MX/ISR_Support.h b/portable/MPLAB/PIC32MX/ISR_Support.h
index d594c7cc7..38c8d6a35 100644
--- a/portable/MPLAB/PIC32MX/ISR_Support.h
+++ b/portable/MPLAB/PIC32MX/ISR_Support.h
@@ -28,164 +28,165 @@
 
 #include "FreeRTOSConfig.h"
 
-#define portCONTEXT_SIZE 132
-#define portEPC_STACK_LOCATION  124
-#define portSTATUS_STACK_LOCATION 128
+#define portCONTEXT_SIZE             132
+#define portEPC_STACK_LOCATION       124
+#define portSTATUS_STACK_LOCATION    128
 
 /******************************************************************/
-.macro  portSAVE_CONTEXT
+.macro portSAVE_CONTEXT
 
-    /* Make room for the context. First save the current status so it can be
-    manipulated, and the cause and EPC registers so their original values are
-    captured. */
-    mfc0        k0, _CP0_CAUSE
-    addiu       sp, sp, -portCONTEXT_SIZE
-    mfc0        k1, _CP0_STATUS
+/* Make room for the context. First save the current status so it can be
+ * manipulated, and the cause and EPC registers so their original values are
+ * captured. */
+mfc0 k0, _CP0_CAUSE
+addiu sp, sp, -portCONTEXT_SIZE
+mfc0 k1, _CP0_STATUS
 
-    /* Also save s6 and s5 so they can be used.  Any nesting interrupts should
-    maintain the values of these registers across the ISR. */
-    sw          s6, 44(sp)
-    sw          s5, 40(sp)
-    sw          k1, portSTATUS_STACK_LOCATION(sp)
+/* Also save s6 and s5 so they can be used.  Any nesting interrupts should
+ * maintain the values of these registers across the ISR. */
+sw s6, 44 ( sp )
+sw s5, 40 ( sp )
+sw k1, portSTATUS_STACK_LOCATION( sp )
 
-    /* Prepare to enable interrupts above the current priority. */
-    srl         k0, k0, 0xa
-    ins         k1, k0, 10, 6
-    ins         k1, zero, 1, 4
+/* Prepare to enable interrupts above the current priority. */
+srl k0, k0, 0xa
+ins k1, k0, 10, 6
+ins k1, zero, 1, 4
 
-    /* s5 is used as the frame pointer. */
-    add         s5, zero, sp
+/* s5 is used as the frame pointer. */
+add s5, zero, sp
 
-    /* Check the nesting count value. */
-    la          k0, uxInterruptNesting
-    lw          s6, (k0)
+/* Check the nesting count value. */
+la k0, uxInterruptNesting
+lw s6, ( k0 )
 
-    /* If the nesting count is 0 then swap to the the system stack, otherwise
-    the system stack is already being used. */
-    bne         s6, zero, 1f
-    nop
+/* If the nesting count is 0 then swap to the the system stack, otherwise
+ * the system stack is already being used. */
+bne s6, zero, 1f
+nop
 
-    /* Swap to the system stack. */
-    la          sp, xISRStackTop
-    lw          sp, (sp)
+/* Swap to the system stack. */
+la sp, xISRStackTop
+lw sp, ( sp )
 
-    /* Increment and save the nesting count. */
-1:  addiu       s6, s6, 1
-    sw          s6, 0(k0)
+/* Increment and save the nesting count. */
+1 :  addiu s6, s6, 1
+sw s6, 0 ( k0 )
 
-    /* s6 holds the EPC value, this is saved after interrupts are re-enabled. */
-    mfc0        s6, _CP0_EPC
+/* s6 holds the EPC value, this is saved after interrupts are re-enabled. */
+mfc0 s6, _CP0_EPC
 
-    /* Re-enable interrupts. */
-    mtc0        k1, _CP0_STATUS
+/* Re-enable interrupts. */
+mtc0 k1, _CP0_STATUS
 
-    /* Save the context into the space just created.  s6 is saved again
-    here as it now contains the EPC value.  No other s registers need be
-    saved. */
-    sw          ra, 120(s5)
-    sw          s8, 116(s5)
-    sw          t9, 112(s5)
-    sw          t8, 108(s5)
-    sw          t7, 104(s5)
-    sw          t6, 100(s5)
-    sw          t5, 96(s5)
-    sw          t4, 92(s5)
-    sw          t3, 88(s5)
-    sw          t2, 84(s5)
-    sw          t1, 80(s5)
-    sw          t0, 76(s5)
-    sw          a3, 72(s5)
-    sw          a2, 68(s5)
-    sw          a1, 64(s5)
-    sw          a0, 60(s5)
-    sw          v1, 56(s5)
-    sw          v0, 52(s5)
-    sw          s6, portEPC_STACK_LOCATION(s5)
-    sw          $1, 16(s5)
+/* Save the context into the space just created.  s6 is saved again
+ * here as it now contains the EPC value.  No other s registers need be
+ * saved. */
+sw ra, 120 ( s5 )
+sw s8, 116 ( s5 )
+sw t9, 112 ( s5 )
+sw t8, 108 ( s5 )
+sw t7, 104 ( s5 )
+sw t6, 100 ( s5 )
+sw t5, 96 ( s5 )
+sw t4, 92 ( s5 )
+sw t3, 88 ( s5 )
+sw t2, 84 ( s5 )
+sw t1, 80 ( s5 )
+sw t0, 76 ( s5 )
+sw a3, 72 ( s5 )
+sw a2, 68 ( s5 )
+sw a1, 64 ( s5 )
+sw a0, 60 ( s5 )
+sw v1, 56 ( s5 )
+sw v0, 52 ( s5 )
+sw s6, portEPC_STACK_LOCATION( s5 )
+sw $1, 16 ( s5 )
 
-    /* s6 is used as a scratch register. */
-    mfhi        s6
-    sw          s6, 12(s5)
-    mflo        s6
-    sw          s6, 8(s5)
+/* s6 is used as a scratch register. */
+mfhi s6
+sw s6, 12 ( s5 )
+mflo s6
+sw s6, 8 ( s5 )
 
-    /* Update the task stack pointer value if nesting is zero. */
-    la          s6, uxInterruptNesting
-    lw          s6, (s6)
-    addiu       s6, s6, -1
-    bne         s6, zero, 1f
-    nop
+/* Update the task stack pointer value if nesting is zero. */
+la s6, uxInterruptNesting
+lw s6, ( s6 )
+addiu s6, s6, -1
+bne s6, zero, 1f
+nop
 
-    /* Save the stack pointer. */
-    la          s6, uxSavedTaskStackPointer
-    sw          s5, (s6)
-1:
-    .endm
+/* Save the stack pointer. */
+la s6, uxSavedTaskStackPointer
+sw s5, ( s6 )
+1 :
+.endm
 
 /******************************************************************/
-.macro  portRESTORE_CONTEXT
+   .macro portRESTORE_CONTEXT
 
-    /* Restore the stack pointer from the TCB.  This is only done if the
-    nesting count is 1. */
-    la          s6, uxInterruptNesting
-    lw          s6, (s6)
-    addiu       s6, s6, -1
-    bne         s6, zero, 1f
-    nop
-    la          s6, uxSavedTaskStackPointer
-    lw          s5, (s6)
+/* Restore the stack pointer from the TCB.  This is only done if the
+ * nesting count is 1. */
+la s6, uxInterruptNesting
+lw s6, ( s6 )
+addiu s6, s6, -1
+bne s6, zero, 1f
+nop
+la s6, uxSavedTaskStackPointer
+lw s5, ( s6 )
 
-    /* Restore the context. */
-1:  lw          s6, 8(s5)
-    mtlo        s6
-    lw          s6, 12(s5)
-    mthi        s6
-    lw          $1, 16(s5)
-    /* s6 is loaded as it was used as a scratch register and therefore saved
-    as part of the interrupt context. */
-    lw          s6, 44(s5)
-    lw          v0, 52(s5)
-    lw          v1, 56(s5)
-    lw          a0, 60(s5)
-    lw          a1, 64(s5)
-    lw          a2, 68(s5)
-    lw          a3, 72(s5)
-    lw          t0, 76(s5)
-    lw          t1, 80(s5)
-    lw          t2, 84(s5)
-    lw          t3, 88(s5)
-    lw          t4, 92(s5)
-    lw          t5, 96(s5)
-    lw          t6, 100(s5)
-    lw          t7, 104(s5)
-    lw          t8, 108(s5)
-    lw          t9, 112(s5)
-    lw          s8, 116(s5)
-    lw          ra, 120(s5)
+/* Restore the context. */
+1 :  lw s6, 8 ( s5 )
+mtlo s6
+lw s6, 12 ( s5 )
+mthi s6
+lw $1, 16 ( s5 )
 
-    /* Protect access to the k registers, and others. */
-    di
-    ehb
+/* s6 is loaded as it was used as a scratch register and therefore saved
+ * as part of the interrupt context. */
+lw s6, 44 ( s5 )
+lw v0, 52 ( s5 )
+lw v1, 56 ( s5 )
+lw a0, 60 ( s5 )
+lw a1, 64 ( s5 )
+lw a2, 68 ( s5 )
+lw a3, 72 ( s5 )
+lw t0, 76 ( s5 )
+lw t1, 80 ( s5 )
+lw t2, 84 ( s5 )
+lw t3, 88 ( s5 )
+lw t4, 92 ( s5 )
+lw t5, 96 ( s5 )
+lw t6, 100 ( s5 )
+lw t7, 104 ( s5 )
+lw t8, 108 ( s5 )
+lw t9, 112 ( s5 )
+lw s8, 116 ( s5 )
+lw ra, 120 ( s5 )
 
-    /* Decrement the nesting count. */
-    la          k0, uxInterruptNesting
-    lw          k1, (k0)
-    addiu       k1, k1, -1
-    sw          k1, 0(k0)
+/* Protect access to the k registers, and others. */
+di
+ehb
 
-    lw          k0, portSTATUS_STACK_LOCATION(s5)
-    lw          k1, portEPC_STACK_LOCATION(s5)
+/* Decrement the nesting count. */
+la k0, uxInterruptNesting
+lw k1, ( k0 )
+addiu k1, k1, -1
+sw k1, 0 ( k0 )
 
-    /* Leave the stack in its original state.  First load sp from s5, then
-    restore s5 from the stack. */
-    add         sp, zero, s5
-    lw          s5, 40(sp)
-    addiu       sp, sp, portCONTEXT_SIZE
+lw k0, portSTATUS_STACK_LOCATION( s5 )
+lw k1, portEPC_STACK_LOCATION( s5 )
 
-    mtc0        k0, _CP0_STATUS
-    mtc0        k1, _CP0_EPC
-    ehb
-    eret
-    nop
+/* Leave the stack in its original state.  First load sp from s5, then
+ * restore s5 from the stack. */
+add sp, zero, s5
+lw s5, 40 ( sp )
+addiu sp, sp, portCONTEXT_SIZE
 
-    .endm
+mtc0 k0, _CP0_STATUS
+mtc0 k1, _CP0_EPC
+ehb
+eret
+nop
+
+   .endm
diff --git a/portable/MPLAB/PIC32MX/port.c b/portable/MPLAB/PIC32MX/port.c
index 97c3ceba3..6c71f7257 100644
--- a/portable/MPLAB/PIC32MX/port.c
+++ b/portable/MPLAB/PIC32MX/port.c
@@ -27,8 +27,8 @@
  */
 
 /*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the PIC32MX port.
-  *----------------------------------------------------------*/
+* Implementation of functions defined in portable.h for the PIC32MX port.
+*----------------------------------------------------------*/
 
 #ifndef __XC
     #error This port is designed to work with XC32.  Please update your C compiler version.
@@ -39,41 +39,41 @@
 #include "task.h"
 
 /* Hardware specifics. */
-#define portTIMER_PRESCALE  8
-#define portPRESCALE_BITS   1
+#define portTIMER_PRESCALE    8
+#define portPRESCALE_BITS     1
 
 /* Bits within various registers. */
-#define portIE_BIT                      ( 0x00000001 )
-#define portEXL_BIT                     ( 0x00000002 )
+#define portIE_BIT            ( 0x00000001 )
+#define portEXL_BIT           ( 0x00000002 )
 
 /* Bits within the CAUSE register. */
-#define portCORE_SW_0                   ( 0x00000100 )
-#define portCORE_SW_1                   ( 0x00000200 )
+#define portCORE_SW_0         ( 0x00000100 )
+#define portCORE_SW_1         ( 0x00000200 )
 
 /* The EXL bit is set to ensure interrupts do not occur while the context of
-the first task is being restored. */
-#define portINITIAL_SR                  ( portIE_BIT | portEXL_BIT )
+ * the first task is being restored. */
+#define portINITIAL_SR        ( portIE_BIT | portEXL_BIT )
 
 /*
-By default port.c generates its tick interrupt from TIMER1.  The user can
-override this behaviour by:
-    1: Providing their own implementation of vApplicationSetupTickTimerInterrupt(),
-       which is the function that configures the timer.  The function is defined
-       as a weak symbol in this file so if the same function name is used in the
-       application code then the version in the application code will be linked
-       into the application in preference to the version defined in this file.
-    2: Define configTICK_INTERRUPT_VECTOR to the vector number of the timer used
-       to generate the tick interrupt.  For example, when timer 1 is used then
-       configTICK_INTERRUPT_VECTOR is set to _TIMER_1_VECTOR.
-       configTICK_INTERRUPT_VECTOR should be defined in FreeRTOSConfig.h.
-    3: Define configCLEAR_TICK_TIMER_INTERRUPT() to clear the interrupt in the
-       timer used to generate the tick interrupt.  For example, when timer 1 is
-       used configCLEAR_TICK_TIMER_INTERRUPT() is defined to
-       IFS0CLR = _IFS0_T1IF_MASK.
-*/
+ * By default port.c generates its tick interrupt from TIMER1.  The user can
+ * override this behaviour by:
+ *  1: Providing their own implementation of vApplicationSetupTickTimerInterrupt(),
+ *     which is the function that configures the timer.  The function is defined
+ *     as a weak symbol in this file so if the same function name is used in the
+ *     application code then the version in the application code will be linked
+ *     into the application in preference to the version defined in this file.
+ *  2: Define configTICK_INTERRUPT_VECTOR to the vector number of the timer used
+ *     to generate the tick interrupt.  For example, when timer 1 is used then
+ *     configTICK_INTERRUPT_VECTOR is set to _TIMER_1_VECTOR.
+ *     configTICK_INTERRUPT_VECTOR should be defined in FreeRTOSConfig.h.
+ *  3: Define configCLEAR_TICK_TIMER_INTERRUPT() to clear the interrupt in the
+ *     timer used to generate the tick interrupt.  For example, when timer 1 is
+ *     used configCLEAR_TICK_TIMER_INTERRUPT() is defined to
+ *     IFS0CLR = _IFS0_T1IF_MASK.
+ */
 #ifndef configTICK_INTERRUPT_VECTOR
-    #define configTICK_INTERRUPT_VECTOR _TIMER_1_VECTOR
-    #define configCLEAR_TICK_TIMER_INTERRUPT() IFS0CLR = _IFS0_T1IF_MASK
+    #define configTICK_INTERRUPT_VECTOR    _TIMER_1_VECTOR
+    #define configCLEAR_TICK_TIMER_INTERRUPT()    IFS0CLR = _IFS0_T1IF_MASK
 #else
     #ifndef configCLEAR_TICK_TIMER_INTERRUPT
         #error If configTICK_INTERRUPT_VECTOR is defined in application code then configCLEAR_TICK_TIMER_INTERRUPT must also be defined in application code.
@@ -81,34 +81,36 @@ override this behaviour by:
 #endif
 
 /* Let the user override the pre-loading of the initial RA with the address of
-prvTaskExitError() in case it messes up unwinding of the stack in the
-debugger - in which case configTASK_RETURN_ADDRESS can be defined as 0 (NULL). */
+ * prvTaskExitError() in case it messes up unwinding of the stack in the
+ * debugger - in which case configTASK_RETURN_ADDRESS can be defined as 0 (NULL). */
 #ifdef configTASK_RETURN_ADDRESS
-    #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
+    #define portTASK_RETURN_ADDRESS    configTASK_RETURN_ADDRESS
 #else
-    #define portTASK_RETURN_ADDRESS prvTaskExitError
+    #define portTASK_RETURN_ADDRESS    prvTaskExitError
 #endif
 
 /* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task
-stack checking.  A problem in the ISR stack will trigger an assert, not call the
-stack overflow hook function (because the stack overflow hook is specific to a
-task stack, not the ISR stack). */
-#if( configCHECK_FOR_STACK_OVERFLOW > 2 )
+ * stack checking.  A problem in the ISR stack will trigger an assert, not call the
+ * stack overflow hook function (because the stack overflow hook is specific to a
+ * task stack, not the ISR stack). */
+#if ( configCHECK_FOR_STACK_OVERFLOW > 2 )
 
-    /* Don't use 0xa5 as the stack fill bytes as that is used by the kernerl for
-    the task stacks, and so will legitimately appear in many positions within
-    the ISR stack. */
-    #define portISR_STACK_FILL_BYTE 0xee
+/* Don't use 0xa5 as the stack fill bytes as that is used by the kernel for
+ * the task stacks, and so will legitimately appear in many positions within
+ * the ISR stack. */
+    #define portISR_STACK_FILL_BYTE    0xee
 
-    static const uint8_t ucExpectedStackBytes[] = {
-                                    portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,     \
-                                    portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,     \
-                                    portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,     \
-                                    portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,     \
-                                    portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE };   \
+    static const uint8_t ucExpectedStackBytes[] =
+    {
+        portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
+        portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
+        portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
+        portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
+        portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE
+    }; \
 
-    #define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
-#else
+    #define portCHECK_ISR_STACK()    configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
+#else /* if ( configCHECK_FOR_STACK_OVERFLOW > 2 ) */
     /* Define the function away. */
     #define portCHECK_ISR_STACK()
 #endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
@@ -122,7 +124,7 @@ task stack, not the ISR stack). */
  * following line of code has no effect.  The interrupt priority is set by the
  * call to ConfigIntTimer1() in vApplicationSetupTickTimerInterrupt().
  */
-extern void __attribute__( (interrupt(IPL1AUTO), vector( configTICK_INTERRUPT_VECTOR ))) vPortTickInterruptHandler( void );
+extern void __attribute__( ( interrupt( IPL1AUTO ), vector( configTICK_INTERRUPT_VECTOR ) ) ) vPortTickInterruptHandler( void );
 
 /*
  * The software interrupt handler that performs the yield.  Note that, because
@@ -130,7 +132,7 @@ extern void __attribute__( (interrupt(IPL1AUTO), vector( configTICK_INTERRUPT_VE
  * code has no effect.  The interrupt priority is set by the call to
  * mConfigIntCoreSW0() in xPortStartScheduler().
  */
-void __attribute__( (interrupt(IPL1AUTO), vector(_CORE_SOFTWARE_0_VECTOR))) vPortYieldISR( void );
+void __attribute__( ( interrupt( IPL1AUTO ), vector( _CORE_SOFTWARE_0_VECTOR ) ) ) vPortYieldISR( void );
 
 /*
  * Used to catch tasks that attempt to return from their implementing function.
@@ -140,17 +142,17 @@ static void prvTaskExitError( void );
 /*-----------------------------------------------------------*/
 
 /* Records the interrupt nesting depth.  This is initialised to one as it is
-decremented to 0 when the first task starts. */
+ * decremented to 0 when the first task starts. */
 volatile UBaseType_t uxInterruptNesting = 0x01;
 
 /* Stores the task stack pointer when a switch is made to use the system stack. */
 UBaseType_t uxSavedTaskStackPointer = 0;
 
 /* The stack used by interrupt service routines that cause a context switch. */
-__attribute__ ((aligned(8))) StackType_t xISRStack[ configISR_STACK_SIZE ] = { 0 };
+__attribute__( ( aligned( 8 ) ) ) StackType_t xISRStack[ configISR_STACK_SIZE ] = { 0 };
 
 /* The top of stack value ensures there is enough space to store 6 registers on
-the callers stack, as some functions seem to want to do this. */
+ * the callers stack, as some functions seem to want to do this. */
 const StackType_t * const xISRStackTop = &( xISRStack[ ( configISR_STACK_SIZE & ~portBYTE_ALIGNMENT_MASK ) - 8 ] );
 
 /*-----------------------------------------------------------*/
@@ -158,32 +160,34 @@ const StackType_t * const xISRStackTop = &( xISRStack[ ( configISR_STACK_SIZE &
 /*
  * See header file for description.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
     /* Ensure 8 byte alignment is maintained when the context is popped from
      * stack. The size of the context is 33 words (132 bytes). */
     pxTopOfStack--;
     pxTopOfStack--;
 
-    *pxTopOfStack = (StackType_t) 0xDEADBEEF;
+    *pxTopOfStack = ( StackType_t ) 0xDEADBEEF;
     pxTopOfStack--;
 
-    *pxTopOfStack = (StackType_t) 0x12345678;   /* Word to which the stack pointer will be left pointing after context restore. */
+    *pxTopOfStack = ( StackType_t ) 0x12345678; /* Word to which the stack pointer will be left pointing after context restore. */
     pxTopOfStack--;
 
-    *pxTopOfStack = (StackType_t) _CP0_GET_CAUSE();
+    *pxTopOfStack = ( StackType_t ) _CP0_GET_CAUSE();
     pxTopOfStack--;
 
-    *pxTopOfStack = (StackType_t) portINITIAL_SR;/* CP0_STATUS */
+    *pxTopOfStack = ( StackType_t ) portINITIAL_SR; /* CP0_STATUS */
     pxTopOfStack--;
 
-    *pxTopOfStack = (StackType_t) pxCode;       /* CP0_EPC */
+    *pxTopOfStack = ( StackType_t ) pxCode; /* CP0_EPC */
     pxTopOfStack--;
 
-    *pxTopOfStack = (StackType_t) portTASK_RETURN_ADDRESS;  /* ra */
+    *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* ra */
     pxTopOfStack -= 15;
 
-    *pxTopOfStack = (StackType_t) pvParameters; /* Parameters to pass in. */
+    *pxTopOfStack = ( StackType_t ) pvParameters; /* Parameters to pass in. */
     pxTopOfStack -= 15;
 
     return pxTopOfStack;
@@ -193,14 +197,17 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
 static void prvTaskExitError( void )
 {
     /* A function that implements a task must not exit or attempt to return to
-    its caller as there is nothing to return to.  If a task wants to exit it
-    should instead call vTaskDelete( NULL ).
-
-    Artificially force an assert() to be triggered if configASSERT() is
-    defined, then stop here so application writers can catch the error. */
+     * its caller as there is nothing to return to.  If a task wants to exit it
+     * should instead call vTaskDelete( NULL ).
+     *
+     * Artificially force an assert() to be triggered if configASSERT() is
+     * defined, then stop here so application writers can catch the error. */
     configASSERT( uxSavedTaskStackPointer == 0UL );
     portDISABLE_INTERRUPTS();
-    for( ;; );
+
+    for( ; ; )
+    {
+    }
 }
 /*-----------------------------------------------------------*/
 
@@ -213,9 +220,9 @@ static void prvTaskExitError( void )
  * vector number.  When Timer 1 is used the vector number is defined as
  * _TIMER_1_VECTOR.
  */
-__attribute__(( weak )) void vApplicationSetupTickTimerInterrupt( void )
+__attribute__( ( weak ) ) void vApplicationSetupTickTimerInterrupt( void )
 {
-const uint32_t ulCompareMatch = ( (configPERIPHERAL_CLOCK_HZ / portTIMER_PRESCALE) / configTICK_RATE_HZ ) - 1;
+    const uint32_t ulCompareMatch = ( ( configPERIPHERAL_CLOCK_HZ / portTIMER_PRESCALE ) / configTICK_RATE_HZ ) - 1;
 
     T1CON = 0x0000;
     T1CONbits.TCKPS = portPRESCALE_BITS;
@@ -233,18 +240,18 @@ const uint32_t ulCompareMatch = ( (configPERIPHERAL_CLOCK_HZ / portTIMER_PRESCAL
 }
 /*-----------------------------------------------------------*/
 
-void vPortEndScheduler(void)
+void vPortEndScheduler( void )
 {
     /* Not implemented in ports where there is nothing to return to.
-    Artificially force an assert. */
+     * Artificially force an assert. */
     configASSERT( uxInterruptNesting == 1000UL );
 }
 /*-----------------------------------------------------------*/
 
 BaseType_t xPortStartScheduler( void )
 {
-extern void vPortStartFirstTask( void );
-extern void *pxCurrentTCB;
+    extern void vPortStartFirstTask( void );
+    extern void * pxCurrentTCB;
 
     #if ( configCHECK_FOR_STACK_OVERFLOW > 2 )
     {
@@ -265,18 +272,18 @@ extern void *pxCurrentTCB;
     IEC0SET = 1 << _IEC0_CS0IE_POSITION;
 
     /* Setup the timer to generate the tick.  Interrupts will have been
-    disabled by the time we get here. */
+     * disabled by the time we get here. */
     vApplicationSetupTickTimerInterrupt();
 
     /* Kick off the highest priority task that has been created so far.
-    Its stack location is loaded into uxSavedTaskStackPointer. */
+     * Its stack location is loaded into uxSavedTaskStackPointer. */
     uxSavedTaskStackPointer = *( UBaseType_t * ) pxCurrentTCB;
     vPortStartFirstTask();
 
     /* Should never get here as the tasks will now be executing!  Call the task
-    exit error function to prevent compiler warnings about a static function
-    not being called in the case that the application writer overrides this
-    functionality by defining configTASK_RETURN_ADDRESS. */
+     * exit error function to prevent compiler warnings about a static function
+     * not being called in the case that the application writer overrides this
+     * functionality by defining configTASK_RETURN_ADDRESS. */
     prvTaskExitError();
 
     return pdFALSE;
@@ -285,7 +292,7 @@ extern void *pxCurrentTCB;
 
 void vPortIncrementTick( void )
 {
-UBaseType_t uxSavedStatus;
+    UBaseType_t uxSavedStatus;
 
     uxSavedStatus = uxPortSetInterruptMaskFromISR();
     {
@@ -307,16 +314,17 @@ UBaseType_t uxSavedStatus;
 
 UBaseType_t uxPortSetInterruptMaskFromISR( void )
 {
-UBaseType_t uxSavedStatusRegister;
+    UBaseType_t uxSavedStatusRegister;
 
     __builtin_disable_interrupts();
     uxSavedStatusRegister = _CP0_GET_STATUS() | 0x01;
+
     /* This clears the IPL bits, then sets them to
-    configMAX_SYSCALL_INTERRUPT_PRIORITY.  This function should not be called
-    from an interrupt that has a priority above
-    configMAX_SYSCALL_INTERRUPT_PRIORITY so, when used correctly, the action
-    can only result in the IPL being unchanged or raised, and therefore never
-    lowered. */
+     * configMAX_SYSCALL_INTERRUPT_PRIORITY.  This function should not be called
+     * from an interrupt that has a priority above
+     * configMAX_SYSCALL_INTERRUPT_PRIORITY so, when used correctly, the action
+     * can only result in the IPL being unchanged or raised, and therefore never
+     * lowered. */
     _CP0_SET_STATUS( ( ( uxSavedStatusRegister & ( ~portALL_IPL_BITS ) ) ) | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) );
 
     return uxSavedStatusRegister;
diff --git a/portable/MPLAB/PIC32MX/portmacro.h b/portable/MPLAB/PIC32MX/portmacro.h
index e0bf8dbd1..535104d20 100644
--- a/portable/MPLAB/PIC32MX/portmacro.h
+++ b/portable/MPLAB/PIC32MX/portmacro.h
@@ -49,119 +49,119 @@
  */
 
 /* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint32_t
-#define portBASE_TYPE   long
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-    not need to be guarded with a critical section. */
-    #define portTICK_TYPE_IS_ATOMIC 1
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+    #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portBYTE_ALIGNMENT          8
-#define portSTACK_GROWTH            -1
-#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT    8
+#define portSTACK_GROWTH      -1
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
 /*-----------------------------------------------------------*/
 
 /* Critical section management. */
-#define portIPL_SHIFT               ( 10UL )
-#define portALL_IPL_BITS            ( 0x3fUL << portIPL_SHIFT )
-#define portSW0_BIT                 ( 0x01 << 8 )
+#define portIPL_SHIFT       ( 10UL )
+#define portALL_IPL_BITS    ( 0x3fUL << portIPL_SHIFT )
+#define portSW0_BIT         ( 0x01 << 8 )
 
 /* This clears the IPL bits, then sets them to
-configMAX_SYSCALL_INTERRUPT_PRIORITY.  An extra check is performed if
-configASSERT() is defined to ensure an assertion handler does not inadvertently
-attempt to lower the IPL when the call to assert was triggered because the IPL
-value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY when an ISR
-safe FreeRTOS API function was executed.  ISR safe FreeRTOS API functions are
-those that end in FromISR.  FreeRTOS maintains a separate interrupt API to
-ensure API function and interrupt entry is as fast and as simple as possible. */
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.  An extra check is performed if
+ * configASSERT() is defined to ensure an assertion handler does not inadvertently
+ * attempt to lower the IPL when the call to assert was triggered because the IPL
+ * value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY when an ISR
+ * safe FreeRTOS API function was executed.  ISR safe FreeRTOS API functions are
+ * those that end in FromISR.  FreeRTOS maintains a separate interrupt API to
+ * ensure API function and interrupt entry is as fast and as simple as possible. */
 #ifdef configASSERT
-    #define portDISABLE_INTERRUPTS()                                            \
-    {                                                                           \
-    uint32_t ulStatus;                                                      \
-                                                                                \
-        /* Mask interrupts at and below the kernel interrupt priority. */       \
-        ulStatus = _CP0_GET_STATUS();                                           \
-                                                                                \
-        /* Is the current IPL below configMAX_SYSCALL_INTERRUPT_PRIORITY? */    \
+    #define portDISABLE_INTERRUPTS()                                                                      \
+    {                                                                                                     \
+        uint32_t ulStatus;                                                                                \
+                                                                                                          \
+        /* Mask interrupts at and below the kernel interrupt priority. */                                 \
+        ulStatus = _CP0_GET_STATUS();                                                                     \
+                                                                                                          \
+        /* Is the current IPL below configMAX_SYSCALL_INTERRUPT_PRIORITY? */                              \
         if( ( ( ulStatus & portALL_IPL_BITS ) >> portIPL_SHIFT ) < configMAX_SYSCALL_INTERRUPT_PRIORITY ) \
-        {                                                                       \
-            ulStatus &= ~portALL_IPL_BITS;                                      \
-            _CP0_SET_STATUS( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
-        }                                                                       \
+        {                                                                                                 \
+            ulStatus &= ~portALL_IPL_BITS;                                                                \
+            _CP0_SET_STATUS( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) );  \
+        }                                                                                                 \
     }
 #else /* configASSERT */
-    #define portDISABLE_INTERRUPTS()                                        \
-    {                                                                       \
-    uint32_t ulStatus;                                                  \
-                                                                            \
-        /* Mask interrupts at and below the kernel interrupt priority. */   \
-        ulStatus = _CP0_GET_STATUS();                                       \
-        ulStatus &= ~portALL_IPL_BITS;                                      \
+    #define portDISABLE_INTERRUPTS()                                                                 \
+    {                                                                                                \
+        uint32_t ulStatus;                                                                           \
+                                                                                                     \
+        /* Mask interrupts at and below the kernel interrupt priority. */                            \
+        ulStatus = _CP0_GET_STATUS();                                                                \
+        ulStatus &= ~portALL_IPL_BITS;                                                               \
         _CP0_SET_STATUS( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
     }
 #endif /* configASSERT */
 
-#define portENABLE_INTERRUPTS()                                         \
-{                                                                       \
-uint32_t ulStatus;                                                  \
-                                                                        \
-    /* Unmask all interrupts. */                                        \
-    ulStatus = _CP0_GET_STATUS();                                       \
-    ulStatus &= ~portALL_IPL_BITS;                                      \
-    _CP0_SET_STATUS( ulStatus );                                        \
-}
+#define portENABLE_INTERRUPTS()        \
+    {                                  \
+        uint32_t ulStatus;             \
+                                       \
+        /* Unmask all interrupts. */   \
+        ulStatus = _CP0_GET_STATUS();  \
+        ulStatus &= ~portALL_IPL_BITS; \
+        _CP0_SET_STATUS( ulStatus );   \
+    }
 
 
 extern void vTaskEnterCritical( void );
 extern void vTaskExitCritical( void );
-#define portCRITICAL_NESTING_IN_TCB 1
-#define portENTER_CRITICAL()        vTaskEnterCritical()
-#define portEXIT_CRITICAL()         vTaskExitCritical()
+#define portCRITICAL_NESTING_IN_TCB    1
+#define portENTER_CRITICAL()    vTaskEnterCritical()
+#define portEXIT_CRITICAL()     vTaskExitCritical()
 
 extern UBaseType_t uxPortSetInterruptMaskFromISR();
 extern void vPortClearInterruptMaskFromISR( UBaseType_t );
-#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMaskFromISR()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) vPortClearInterruptMaskFromISR( uxSavedStatusRegister )
+#define portSET_INTERRUPT_MASK_FROM_ISR()                             uxPortSetInterruptMaskFromISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister )    vPortClearInterruptMaskFromISR( uxSavedStatusRegister )
 
 #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-    #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+    #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
 #endif
 
 #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
 
-    /* Check the configuration. */
-    #if( configMAX_PRIORITIES > 32 )
+/* Check the configuration. */
+    #if ( configMAX_PRIORITIES > 32 )
         #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
     #endif
 
-    /* Store/clear the ready priorities in a bit map. */
-    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+/* Store/clear the ready priorities in a bit map. */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 
-    /*-----------------------------------------------------------*/
+/*-----------------------------------------------------------*/
 
-    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - _clz( ( uxReadyPriorities ) ) )
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - _clz( ( uxReadyPriorities ) ) )
 
 #endif /* taskRECORD_READY_PRIORITY */
 
@@ -169,29 +169,29 @@ extern void vPortClearInterruptMaskFromISR( UBaseType_t );
 
 /* Task utilities. */
 
-#define portYIELD()                             \
-{                                               \
-uint32_t ulCause;                           \
-                                                \
-    /* Trigger software interrupt. */           \
-    ulCause = _CP0_GET_CAUSE();                 \
-    ulCause |= portSW0_BIT;                     \
-    _CP0_SET_CAUSE( ulCause );                  \
-}
+#define portYIELD()                       \
+    {                                     \
+        uint32_t ulCause;                 \
+                                          \
+        /* Trigger software interrupt. */ \
+        ulCause = _CP0_GET_CAUSE();       \
+        ulCause |= portSW0_BIT;           \
+        _CP0_SET_CAUSE( ulCause );        \
+    }
 
 extern volatile UBaseType_t uxInterruptNesting;
-#define portASSERT_IF_IN_ISR() configASSERT( uxInterruptNesting == 0 )
+#define portASSERT_IF_IN_ISR()    configASSERT( uxInterruptNesting == 0 )
 
-#define portNOP()   __asm volatile ( "nop" )
+#define portNOP()                 __asm volatile ( "nop" )
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn))
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters ) __attribute__( ( noreturn ) )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 /*-----------------------------------------------------------*/
 
-#define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired ) { portYIELD(); } } while( 0 )
+#define portEND_SWITCHING_ISR( xSwitchRequired )              do { if( xSwitchRequired ) { portYIELD(); } } while( 0 )
 
 /* Required by the kernel aware debugger. */
 #ifdef __DEBUG
diff --git a/portable/MPLAB/PIC32MZ/ISR_Support.h b/portable/MPLAB/PIC32MZ/ISR_Support.h
index a9ddee0f4..459ee2e3f 100644
--- a/portable/MPLAB/PIC32MZ/ISR_Support.h
+++ b/portable/MPLAB/PIC32MZ/ISR_Support.h
@@ -28,405 +28,406 @@
 
 #include "FreeRTOSConfig.h"
 
-#define portCONTEXT_SIZE                160
-#define portEPC_STACK_LOCATION          152
-#define portSTATUS_STACK_LOCATION       156
-#define portFPCSR_STACK_LOCATION        0
-#define portTASK_HAS_FPU_STACK_LOCATION     0
-#define portFPU_CONTEXT_SIZE            264
+#define portCONTEXT_SIZE                   160
+#define portEPC_STACK_LOCATION             152
+#define portSTATUS_STACK_LOCATION          156
+#define portFPCSR_STACK_LOCATION           0
+#define portTASK_HAS_FPU_STACK_LOCATION    0
+#define portFPU_CONTEXT_SIZE               264
 
 /******************************************************************/
-.macro  portSAVE_FPU_REGS    offset, base
-    /* Macro to assist with saving just the FPU registers to the
-     * specified address and base offset,
-     * offset is a constant, base is the base pointer register  */
+.macro portSAVE_FPU_REGS offset, base
 
-    sdc1        $f31, \offset + 248(\base)
-    sdc1        $f30, \offset + 240(\base)
-    sdc1        $f29, \offset + 232(\base)
-    sdc1        $f28, \offset + 224(\base)
-    sdc1        $f27, \offset + 216(\base)
-    sdc1        $f26, \offset + 208(\base)
-    sdc1        $f25, \offset + 200(\base)
-    sdc1        $f24, \offset + 192(\base)
-    sdc1        $f23, \offset + 184(\base)
-    sdc1        $f22, \offset + 176(\base)
-    sdc1        $f21, \offset + 168(\base)
-    sdc1        $f20, \offset + 160(\base)
-    sdc1        $f19, \offset + 152(\base)
-    sdc1        $f18, \offset + 144(\base)
-    sdc1        $f17, \offset + 136(\base)
-    sdc1        $f16, \offset + 128(\base)
-    sdc1        $f15, \offset + 120(\base)
-    sdc1        $f14, \offset + 112(\base)
-    sdc1        $f13, \offset + 104(\base)
-    sdc1        $f12, \offset + 96(\base)
-    sdc1        $f11, \offset + 88(\base)
-    sdc1        $f10, \offset + 80(\base)
-    sdc1        $f9, \offset + 72(\base)
-    sdc1        $f8, \offset + 64(\base)
-    sdc1        $f7, \offset + 56(\base)
-    sdc1        $f6, \offset + 48(\base)
-    sdc1        $f5, \offset + 40(\base)
-    sdc1        $f4, \offset + 32(\base)
-    sdc1        $f3, \offset + 24(\base)
-    sdc1        $f2, \offset + 16(\base)
-    sdc1        $f1, \offset + 8(\base)
-    sdc1        $f0, \offset + 0(\base)
+/* Macro to assist with saving just the FPU registers to the
+ * specified address and base offset,
+ * offset is a constant, base is the base pointer register  */
 
-    .endm
+sdc1 $f31, \ offset + 248 ( \ base )
+sdc1 $f30, \ offset + 240 ( \ base )
+sdc1 $f29, \ offset + 232 ( \ base )
+sdc1 $f28, \ offset + 224 ( \ base )
+sdc1 $f27, \ offset + 216 ( \ base )
+sdc1 $f26, \ offset + 208 ( \ base )
+sdc1 $f25, \ offset + 200 ( \ base )
+sdc1 $f24, \ offset + 192 ( \ base )
+sdc1 $f23, \ offset + 184 ( \ base )
+sdc1 $f22, \ offset + 176 ( \ base )
+sdc1 $f21, \ offset + 168 ( \ base )
+sdc1 $f20, \ offset + 160 ( \ base )
+sdc1 $f19, \ offset + 152 ( \ base )
+sdc1 $f18, \ offset + 144 ( \ base )
+sdc1 $f17, \ offset + 136 ( \ base )
+sdc1 $f16, \ offset + 128 ( \ base )
+sdc1 $f15, \ offset + 120 ( \ base )
+sdc1 $f14, \ offset + 112 ( \ base )
+sdc1 $f13, \ offset + 104 ( \ base )
+sdc1 $f12, \ offset + 96 ( \ base )
+sdc1 $f11, \ offset + 88 ( \ base )
+sdc1 $f10, \ offset + 80 ( \ base )
+sdc1 $f9, \ offset + 72 ( \ base )
+sdc1 $f8, \ offset + 64 ( \ base )
+sdc1 $f7, \ offset + 56 ( \ base )
+sdc1 $f6, \ offset + 48 ( \ base )
+sdc1 $f5, \ offset + 40 ( \ base )
+sdc1 $f4, \ offset + 32 ( \ base )
+sdc1 $f3, \ offset + 24 ( \ base )
+sdc1 $f2, \ offset + 16 ( \ base )
+sdc1 $f1, \ offset + 8 ( \ base )
+sdc1 $f0, \ offset + 0 ( \ base )
+
+   .endm
 
 /******************************************************************/
-.macro  portLOAD_FPU_REGS    offset, base
-    /* Macro to assist with loading just the FPU registers from the
-     * specified address and base offset, offset is a constant,
-     * base is the base pointer register  */
+   .macro portLOAD_FPU_REGS offset, base
 
-    ldc1        $f0, \offset + 0(\base)
-    ldc1        $f1, \offset + 8(\base)
-    ldc1        $f2, \offset + 16(\base)
-    ldc1        $f3, \offset + 24(\base)
-    ldc1        $f4, \offset + 32(\base)
-    ldc1        $f5, \offset + 40(\base)
-    ldc1        $f6, \offset + 48(\base)
-    ldc1        $f7, \offset + 56(\base)
-    ldc1        $f8, \offset + 64(\base)
-    ldc1        $f9, \offset + 72(\base)
-    ldc1        $f10, \offset + 80(\base)
-    ldc1        $f11, \offset + 88(\base)
-    ldc1        $f12, \offset + 96(\base)
-    ldc1        $f13, \offset + 104(\base)
-    ldc1        $f14, \offset + 112(\base)
-    ldc1        $f15, \offset + 120(\base)
-    ldc1        $f16, \offset + 128(\base)
-    ldc1        $f17, \offset + 136(\base)
-    ldc1        $f18, \offset + 144(\base)
-    ldc1        $f19, \offset + 152(\base)
-    ldc1        $f20, \offset + 160(\base)
-    ldc1        $f21, \offset + 168(\base)
-    ldc1        $f22, \offset + 176(\base)
-    ldc1        $f23, \offset + 184(\base)
-    ldc1        $f24, \offset + 192(\base)
-    ldc1        $f25, \offset + 200(\base)
-    ldc1        $f26, \offset + 208(\base)
-    ldc1        $f27, \offset + 216(\base)
-    ldc1        $f28, \offset + 224(\base)
-    ldc1        $f29, \offset + 232(\base)
-    ldc1        $f30, \offset + 240(\base)
-    ldc1        $f31, \offset + 248(\base)
+/* Macro to assist with loading just the FPU registers from the
+ * specified address and base offset, offset is a constant,
+ * base is the base pointer register  */
 
-    .endm
+ldc1 $f0, \ offset + 0 ( \ base )
+ldc1 $f1, \ offset + 8 ( \ base )
+ldc1 $f2, \ offset + 16 ( \ base )
+ldc1 $f3, \ offset + 24 ( \ base )
+ldc1 $f4, \ offset + 32 ( \ base )
+ldc1 $f5, \ offset + 40 ( \ base )
+ldc1 $f6, \ offset + 48 ( \ base )
+ldc1 $f7, \ offset + 56 ( \ base )
+ldc1 $f8, \ offset + 64 ( \ base )
+ldc1 $f9, \ offset + 72 ( \ base )
+ldc1 $f10, \ offset + 80 ( \ base )
+ldc1 $f11, \ offset + 88 ( \ base )
+ldc1 $f12, \ offset + 96 ( \ base )
+ldc1 $f13, \ offset + 104 ( \ base )
+ldc1 $f14, \ offset + 112 ( \ base )
+ldc1 $f15, \ offset + 120 ( \ base )
+ldc1 $f16, \ offset + 128 ( \ base )
+ldc1 $f17, \ offset + 136 ( \ base )
+ldc1 $f18, \ offset + 144 ( \ base )
+ldc1 $f19, \ offset + 152 ( \ base )
+ldc1 $f20, \ offset + 160 ( \ base )
+ldc1 $f21, \ offset + 168 ( \ base )
+ldc1 $f22, \ offset + 176 ( \ base )
+ldc1 $f23, \ offset + 184 ( \ base )
+ldc1 $f24, \ offset + 192 ( \ base )
+ldc1 $f25, \ offset + 200 ( \ base )
+ldc1 $f26, \ offset + 208 ( \ base )
+ldc1 $f27, \ offset + 216 ( \ base )
+ldc1 $f28, \ offset + 224 ( \ base )
+ldc1 $f29, \ offset + 232 ( \ base )
+ldc1 $f30, \ offset + 240 ( \ base )
+ldc1 $f31, \ offset + 248 ( \ base )
+
+   .endm
 
 /******************************************************************/
-.macro  portSAVE_CONTEXT
+   .macro portSAVE_CONTEXT
 
-    /* Make room for the context. First save the current status so it can be
-    manipulated, and the cause and EPC registers so their original values are
-    captured. */
-    mfc0        k0, _CP0_CAUSE
-    addiu       sp, sp, -portCONTEXT_SIZE
+/* Make room for the context. First save the current status so it can be
+ * manipulated, and the cause and EPC registers so their original values are
+ * captured. */
+mfc0 k0, _CP0_CAUSE
+addiu sp, sp, -portCONTEXT_SIZE
 
-    #if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
-        /* Test if we are already using the system stack. Only tasks may use the
-        FPU so if we are already in a nested interrupt then the FPU context does
-        not require saving. */
-        la          k1, uxInterruptNesting
-        lw          k1, 0(k1)
-        bne         k1, zero, 2f
-        nop
+#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
 
-        /* Test if the current task needs the FPU context saving. */
-        la          k1, ulTaskHasFPUContext
-        lw          k1, 0(k1)
-        beq         k1, zero, 1f
-        nop
-
-        /* Adjust the stack to account for the additional FPU context.*/
-        addiu       sp, sp, -portFPU_CONTEXT_SIZE
-
-    1:
-        /* Save the ulTaskHasFPUContext flag. */
-        sw          k1, portTASK_HAS_FPU_STACK_LOCATION(sp)
-
-    2:
-    #endif
-
-    mfc0        k1, _CP0_STATUS
-
-    /* Also save s7, s6 and s5 so they can be used.  Any nesting interrupts
-    should maintain the values of these registers across the ISR. */
-    sw          s7, 48(sp)
-    sw          s6, 44(sp)
-    sw          s5, 40(sp)
-    sw          k1, portSTATUS_STACK_LOCATION(sp)
-
-    /* Prepare to enable interrupts above the current priority. */
-    srl         k0, k0, 0xa
-    ins         k1, k0, 10, 7
-    srl         k0, k0, 0x7 /* This copies the MSB of the IPL, but it would be an error if it was set anyway. */
-    ins         k1, k0, 18, 1
-    ins         k1, zero, 1, 4
-
-    /* s5 is used as the frame pointer. */
-    add         s5, zero, sp
-
-    /* Check the nesting count value. */
-    la          k0, uxInterruptNesting
-    lw          s6, (k0)
-
-    /* If the nesting count is 0 then swap to the the system stack, otherwise
-    the system stack is already being used. */
-    bne         s6, zero, 1f
+/* Test if we are already using the system stack. Only tasks may use the
+ * FPU so if we are already in a nested interrupt then the FPU context does
+ * not require saving. */
+    la k1, uxInterruptNesting
+    lw k1, 0 ( k1 )
+    bne k1, zero, 2f
     nop
 
-    /* Swap to the system stack. */
-    la          sp, xISRStackTop
-    lw          sp, (sp)
-
-    /* Increment and save the nesting count. */
-1:  addiu       s6, s6, 1
-    sw          s6, 0(k0)
-
-    /* s6 holds the EPC value, this is saved after interrupts are re-enabled. */
-    mfc0        s6, _CP0_EPC
-
-    /* Re-enable interrupts. */
-    mtc0        k1, _CP0_STATUS
-
-    /* Save the context into the space just created.  s6 is saved again
-    here as it now contains the EPC value.  No other s registers need be
-    saved. */
-    sw          ra, 120(s5)
-    sw          s8, 116(s5)
-    sw          t9, 112(s5)
-    sw          t8, 108(s5)
-    sw          t7, 104(s5)
-    sw          t6, 100(s5)
-    sw          t5, 96(s5)
-    sw          t4, 92(s5)
-    sw          t3, 88(s5)
-    sw          t2, 84(s5)
-    sw          t1, 80(s5)
-    sw          t0, 76(s5)
-    sw          a3, 72(s5)
-    sw          a2, 68(s5)
-    sw          a1, 64(s5)
-    sw          a0, 60(s5)
-    sw          v1, 56(s5)
-    sw          v0, 52(s5)
-    sw          s6, portEPC_STACK_LOCATION(s5)
-    sw          $1, 16(s5)
-
-    /* Save the AC0, AC1, AC2, AC3 registers from the DSP.  s6 is used as a
-    scratch register. */
-    mfhi        s6, $ac1
-    sw          s6, 128(s5)
-    mflo        s6, $ac1
-    sw          s6, 124(s5)
-
-    mfhi        s6, $ac2
-    sw          s6, 136(s5)
-    mflo        s6, $ac2
-    sw          s6, 132(s5)
-
-    mfhi        s6, $ac3
-    sw          s6, 144(s5)
-    mflo        s6, $ac3
-    sw          s6, 140(s5)
-
-    /* Save the DSP Control register */
-    rddsp       s6
-    sw          s6, 148(s5)
-
-    /* ac0 is done separately to match the MX port. */
-    mfhi        s6, $ac0
-    sw          s6, 12(s5)
-    mflo        s6, $ac0
-    sw          s6, 8(s5)
-
-    /* Save the FPU context if the nesting count was zero. */
-    #if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
-        la          s6, uxInterruptNesting
-        lw          s6, 0(s6)
-        addiu       s6, s6, -1
-        bne         s6, zero, 1f
-        nop
-
-        /* Test if the current task needs the FPU context saving. */
-        lw          s6, portTASK_HAS_FPU_STACK_LOCATION(s5)
-        beq         s6, zero, 1f
-        nop
-
-        /* Save the FPU registers. */
-        portSAVE_FPU_REGS ( portCONTEXT_SIZE + 8 ), s5
-
-        /* Save the FPU status register */
-        cfc1        s6, $f31
-        sw          s6, (portCONTEXT_SIZE + portFPCSR_STACK_LOCATION)(s5)
-
-        1:
-    #endif
-
-    /* Update the task stack pointer value if nesting is zero. */
-    la          s6, uxInterruptNesting
-    lw          s6, (s6)
-    addiu       s6, s6, -1
-    bne         s6, zero, 1f
+/* Test if the current task needs the FPU context saving. */
+    la k1, ulTaskHasFPUContext
+    lw k1, 0 ( k1 )
+    beq k1, zero, 1f
     nop
 
-    /* Save the stack pointer. */
-    la          s6, uxSavedTaskStackPointer
-    sw          s5, (s6)
-1:
-    .endm
+/* Adjust the stack to account for the additional FPU context.*/
+    addiu sp, sp, -portFPU_CONTEXT_SIZE
+
+    1 :
+    /* Save the ulTaskHasFPUContext flag. */
+    sw k1, portTASK_HAS_FPU_STACK_LOCATION( sp )
+
+    2 :
+#endif /* if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) */
+
+mfc0 k1, _CP0_STATUS
+
+/* Also save s7, s6 and s5 so they can be used.  Any nesting interrupts
+ * should maintain the values of these registers across the ISR. */
+sw s7, 48 ( sp )
+sw s6, 44 ( sp )
+sw s5, 40 ( sp )
+sw k1, portSTATUS_STACK_LOCATION( sp )
+
+/* Prepare to enable interrupts above the current priority. */
+srl k0, k0, 0xa
+ins k1, k0, 10, 7
+srl k0, k0, 0x7 /* This copies the MSB of the IPL, but it would be an error if it was set anyway. */
+ins k1, k0, 18, 1
+ins k1, zero, 1, 4
+
+/* s5 is used as the frame pointer. */
+add s5, zero, sp
+
+/* Check the nesting count value. */
+la k0, uxInterruptNesting
+lw s6, ( k0 )
+
+/* If the nesting count is 0 then swap to the the system stack, otherwise
+ * the system stack is already being used. */
+bne s6, zero, 1f
+nop
+
+/* Swap to the system stack. */
+la sp, xISRStackTop
+lw sp, ( sp )
+
+/* Increment and save the nesting count. */
+1 :  addiu s6, s6, 1
+sw s6, 0 ( k0 )
+
+/* s6 holds the EPC value, this is saved after interrupts are re-enabled. */
+mfc0 s6, _CP0_EPC
+
+/* Re-enable interrupts. */
+mtc0 k1, _CP0_STATUS
+
+/* Save the context into the space just created.  s6 is saved again
+ * here as it now contains the EPC value.  No other s registers need be
+ * saved. */
+sw ra, 120 ( s5 )
+sw s8, 116 ( s5 )
+sw t9, 112 ( s5 )
+sw t8, 108 ( s5 )
+sw t7, 104 ( s5 )
+sw t6, 100 ( s5 )
+sw t5, 96 ( s5 )
+sw t4, 92 ( s5 )
+sw t3, 88 ( s5 )
+sw t2, 84 ( s5 )
+sw t1, 80 ( s5 )
+sw t0, 76 ( s5 )
+sw a3, 72 ( s5 )
+sw a2, 68 ( s5 )
+sw a1, 64 ( s5 )
+sw a0, 60 ( s5 )
+sw v1, 56 ( s5 )
+sw v0, 52 ( s5 )
+sw s6, portEPC_STACK_LOCATION( s5 )
+sw $1, 16 ( s5 )
+
+/* Save the AC0, AC1, AC2, AC3 registers from the DSP.  s6 is used as a
+ * scratch register. */
+mfhi s6, $ac1
+sw s6, 128 ( s5 )
+mflo s6, $ac1
+sw s6, 124 ( s5 )
+
+mfhi s6, $ac2
+sw s6, 136 ( s5 )
+mflo s6, $ac2
+sw s6, 132 ( s5 )
+
+mfhi s6, $ac3
+sw s6, 144 ( s5 )
+mflo s6, $ac3
+sw s6, 140 ( s5 )
+
+/* Save the DSP Control register */
+rddsp s6
+sw s6, 148 ( s5 )
+
+/* ac0 is done separately to match the MX port. */
+mfhi s6, $ac0
+sw s6, 12 ( s5 )
+mflo s6, $ac0
+sw s6, 8 ( s5 )
+
+/* Save the FPU context if the nesting count was zero. */
+#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
+    la s6, uxInterruptNesting
+    lw s6, 0 ( s6 )
+    addiu s6, s6, -1
+    bne s6, zero, 1f
+    nop
+
+/* Test if the current task needs the FPU context saving. */
+    lw s6, portTASK_HAS_FPU_STACK_LOCATION( s5 )
+    beq s6, zero, 1f
+    nop
+    /* Save the FPU registers. */
+    portSAVE_FPU_REGS( portCONTEXT_SIZE + 8 ), s5
+
+/* Save the FPU status register */
+    cfc1 s6, $f31
+    sw s6, ( portCONTEXT_SIZE + portFPCSR_STACK_LOCATION )( s5 )
+
+    1 :
+#endif /* if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) */
+
+/* Update the task stack pointer value if nesting is zero. */
+la s6, uxInterruptNesting
+lw s6, ( s6 )
+addiu s6, s6, -1
+bne s6, zero, 1f
+nop
+
+/* Save the stack pointer. */
+la s6, uxSavedTaskStackPointer
+sw s5, ( s6 )
+1 :
+.endm
 
 /******************************************************************/
-.macro  portRESTORE_CONTEXT
+   .macro portRESTORE_CONTEXT
 
-    /* Restore the stack pointer from the TCB.  This is only done if the
-    nesting count is 1. */
-    la          s6, uxInterruptNesting
-    lw          s6, (s6)
-    addiu       s6, s6, -1
-    bne         s6, zero, 1f
+/* Restore the stack pointer from the TCB.  This is only done if the
+ * nesting count is 1. */
+la s6, uxInterruptNesting
+lw s6, ( s6 )
+addiu s6, s6, -1
+bne s6, zero, 1f
+nop
+la s6, uxSavedTaskStackPointer
+lw s5, ( s6 )
+
+#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
+    /* Restore the FPU context if required. */
+    lw s6, portTASK_HAS_FPU_STACK_LOCATION( s5 )
+    beq s6, zero, 1f
     nop
-    la          s6, uxSavedTaskStackPointer
-    lw          s5, (s6)
+    /* Restore the FPU registers. */
+    portLOAD_FPU_REGS( portCONTEXT_SIZE + 8 ), s5
 
-    #if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
-        /* Restore the FPU context if required. */
-        lw          s6, portTASK_HAS_FPU_STACK_LOCATION(s5)
-        beq         s6, zero, 1f
-        nop
+/* Restore the FPU status register. */
+    lw s6, ( portCONTEXT_SIZE + portFPCSR_STACK_LOCATION )( s5 )
+    ctc1 s6, $f31
+#endif /* if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) */
 
-        /* Restore the FPU registers. */
-        portLOAD_FPU_REGS   ( portCONTEXT_SIZE + 8 ), s5
+1 :
 
-        /* Restore the FPU status register. */
-        lw          s6, ( portCONTEXT_SIZE + portFPCSR_STACK_LOCATION )(s5)
-        ctc1        s6, $f31
-    #endif
+/* Restore the context. */
+lw s6, 128 ( s5 )
+mthi s6, $ac1
+lw s6, 124 ( s5 )
+mtlo s6, $ac1
 
-1:
+lw s6, 136 ( s5 )
+mthi s6, $ac2
+lw s6, 132 ( s5 )
+mtlo s6, $ac2
 
-    /* Restore the context. */
-    lw          s6, 128(s5)
-    mthi        s6, $ac1
-    lw          s6, 124(s5)
-    mtlo        s6, $ac1
+lw s6, 144 ( s5 )
+mthi s6, $ac3
+lw s6, 140 ( s5 )
+mtlo s6, $ac3
 
-    lw          s6, 136(s5)
-    mthi        s6, $ac2
-    lw          s6, 132(s5)
-    mtlo        s6, $ac2
+/* Restore DSPControl. */
+lw s6, 148 ( s5 )
+wrdsp s6
 
-    lw          s6, 144(s5)
-    mthi        s6, $ac3
-    lw          s6, 140(s5)
-    mtlo        s6, $ac3
+lw s6, 8 ( s5 )
+mtlo s6, $ac0
+lw s6, 12 ( s5 )
+mthi s6, $ac0
+lw $1, 16 ( s5 )
 
-    /* Restore DSPControl. */
-    lw          s6, 148(s5)
-    wrdsp       s6
+/* s6 is loaded as it was used as a scratch register and therefore saved
+ * as part of the interrupt context. */
+lw s7, 48 ( s5 )
+lw s6, 44 ( s5 )
+lw v0, 52 ( s5 )
+lw v1, 56 ( s5 )
+lw a0, 60 ( s5 )
+lw a1, 64 ( s5 )
+lw a2, 68 ( s5 )
+lw a3, 72 ( s5 )
+lw t0, 76 ( s5 )
+lw t1, 80 ( s5 )
+lw t2, 84 ( s5 )
+lw t3, 88 ( s5 )
+lw t4, 92 ( s5 )
+lw t5, 96 ( s5 )
+lw t6, 100 ( s5 )
+lw t7, 104 ( s5 )
+lw t8, 108 ( s5 )
+lw t9, 112 ( s5 )
+lw s8, 116 ( s5 )
+lw ra, 120 ( s5 )
 
-    lw          s6, 8(s5)
-    mtlo        s6, $ac0
-    lw          s6, 12(s5)
-    mthi        s6, $ac0
-    lw          $1, 16(s5)
+/* Protect access to the k registers, and others. */
+di
+ehb
 
-    /* s6 is loaded as it was used as a scratch register and therefore saved
-    as part of the interrupt context. */
-    lw          s7, 48(s5)
-    lw          s6, 44(s5)
-    lw          v0, 52(s5)
-    lw          v1, 56(s5)
-    lw          a0, 60(s5)
-    lw          a1, 64(s5)
-    lw          a2, 68(s5)
-    lw          a3, 72(s5)
-    lw          t0, 76(s5)
-    lw          t1, 80(s5)
-    lw          t2, 84(s5)
-    lw          t3, 88(s5)
-    lw          t4, 92(s5)
-    lw          t5, 96(s5)
-    lw          t6, 100(s5)
-    lw          t7, 104(s5)
-    lw          t8, 108(s5)
-    lw          t9, 112(s5)
-    lw          s8, 116(s5)
-    lw          ra, 120(s5)
+/* Decrement the nesting count. */
+la k0, uxInterruptNesting
+lw k1, ( k0 )
+addiu k1, k1, -1
+sw k1, 0 ( k0 )
 
-    /* Protect access to the k registers, and others. */
-    di
-    ehb
-
-    /* Decrement the nesting count. */
-    la          k0, uxInterruptNesting
-    lw          k1, (k0)
-    addiu       k1, k1, -1
-    sw          k1, 0(k0)
-
-    #if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
-        /* If the nesting count is now zero then the FPU context may be restored. */
-        bne         k1, zero, 1f
-        nop
-
-        /* Restore the value of ulTaskHasFPUContext */
-        la          k0, ulTaskHasFPUContext
-        lw          k1, 0(s5)
-        sw          k1, 0(k0)
-
-        /* If the task does not have an FPU context then adjust the stack normally. */
-        beq         k1, zero, 1f
-        nop
-
-        /* Restore the STATUS and EPC registers */
-        lw          k0, portSTATUS_STACK_LOCATION(s5)
-        lw          k1, portEPC_STACK_LOCATION(s5)
-
-        /* Leave the stack in its original state.  First load sp from s5, then
-        restore s5 from the stack. */
-        add         sp, zero, s5
-        lw          s5, 40(sp)
-
-        /* Adjust the stack pointer to remove the FPU context */
-        addiu       sp, sp, portFPU_CONTEXT_SIZE
-        beq         zero, zero, 2f
-        nop
-
-        1:  /* Restore the STATUS and EPC registers */
-        lw          k0, portSTATUS_STACK_LOCATION(s5)
-        lw          k1, portEPC_STACK_LOCATION(s5)
-
-        /* Leave the stack in its original state.  First load sp from s5, then
-        restore s5 from the stack. */
-        add         sp, zero, s5
-        lw          s5, 40(sp)
-
-        2:  /* Adjust the stack pointer */
-        addiu       sp, sp, portCONTEXT_SIZE
-
-    #else
-
-        /* Restore the frame when there is no hardware FP support. */
-        lw          k0, portSTATUS_STACK_LOCATION(s5)
-        lw          k1, portEPC_STACK_LOCATION(s5)
-
-        /* Leave the stack in its original state.  First load sp from s5, then
-        restore s5 from the stack. */
-        add         sp, zero, s5
-        lw          s5, 40(sp)
-
-        addiu       sp, sp, portCONTEXT_SIZE
-
-    #endif // ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
-
-    mtc0        k0, _CP0_STATUS
-    mtc0        k1, _CP0_EPC
-    ehb
-    eret
+#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
+    /* If the nesting count is now zero then the FPU context may be restored. */
+    bne k1, zero, 1f
     nop
 
-    .endm
+/* Restore the value of ulTaskHasFPUContext */
+    la k0, ulTaskHasFPUContext
+    lw k1, 0 ( s5 )
+    sw k1, 0 ( k0 )
+
+/* If the task does not have an FPU context then adjust the stack normally. */
+    beq k1, zero, 1f
+    nop
+
+/* Restore the STATUS and EPC registers */
+    lw k0, portSTATUS_STACK_LOCATION( s5 )
+    lw k1, portEPC_STACK_LOCATION( s5 )
+
+/* Leave the stack in its original state.  First load sp from s5, then
+ * restore s5 from the stack. */
+    add sp, zero, s5
+    lw s5, 40 ( sp )
+
+/* Adjust the stack pointer to remove the FPU context */
+    addiu sp, sp, portFPU_CONTEXT_SIZE
+    beq zero, zero, 2f
+    nop
+
+    1 : /* Restore the STATUS and EPC registers */
+    lw k0, portSTATUS_STACK_LOCATION( s5 )
+    lw k1, portEPC_STACK_LOCATION( s5 )
+
+/* Leave the stack in its original state.  First load sp from s5, then
+ * restore s5 from the stack. */
+    add sp, zero, s5
+    lw s5, 40 ( sp )
+
+    2 : /* Adjust the stack pointer */
+    addiu sp, sp, portCONTEXT_SIZE
+
+#else /* if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) */
+
+/* Restore the frame when there is no hardware FP support. */
+    lw k0, portSTATUS_STACK_LOCATION( s5 )
+    lw k1, portEPC_STACK_LOCATION( s5 )
+
+/* Leave the stack in its original state.  First load sp from s5, then
+ * restore s5 from the stack. */
+    add sp, zero, s5
+    lw s5, 40 ( sp )
+
+    addiu sp, sp, portCONTEXT_SIZE
+
+#endif // ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
+
+mtc0 k0, _CP0_STATUS
+mtc0 k1, _CP0_EPC
+ehb
+eret
+nop
+
+   .endm
diff --git a/portable/MPLAB/PIC32MZ/port.c b/portable/MPLAB/PIC32MZ/port.c
index cc711f858..dafbf1d94 100644
--- a/portable/MPLAB/PIC32MZ/port.c
+++ b/portable/MPLAB/PIC32MZ/port.c
@@ -27,8 +27,8 @@
  */
 
 /*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the PIC32MZ port.
-  *----------------------------------------------------------*/
+* Implementation of functions defined in portable.h for the PIC32MZ port.
+*----------------------------------------------------------*/
 
 /* Microchip specific headers. */
 #include <xc.h>
@@ -40,62 +40,62 @@
 #include "FreeRTOS.h"
 #include "task.h"
 
-#if !defined(__PIC32MZ__)
+#if !defined( __PIC32MZ__ )
     #error This port is designed to work with XC32 on PIC32MZ MCUs.  Please update your C compiler version or settings.
 #endif
 
-#if( ( configMAX_SYSCALL_INTERRUPT_PRIORITY >= 0x7 ) || ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 ) )
+#if ( ( configMAX_SYSCALL_INTERRUPT_PRIORITY >= 0x7 ) || ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 ) )
     #error configMAX_SYSCALL_INTERRUPT_PRIORITY must be less than 7 and greater than 0
 #endif
 
 /* Hardware specifics. */
-#define portTIMER_PRESCALE  8
-#define portPRESCALE_BITS   1
+#define portTIMER_PRESCALE    8
+#define portPRESCALE_BITS     1
 
 /* Bits within various registers. */
-#define portIE_BIT                  ( 0x00000001 )
-#define portEXL_BIT                 ( 0x00000002 )
-#define portMX_BIT                  ( 0x01000000 ) /* Allow access to DSP instructions. */
-#define portCU1_BIT                 ( 0x20000000 ) /* enable CP1 for parts with hardware. */
-#define portFR_BIT                  ( 0x04000000 ) /* Enable 64 bit floating point registers. */
+#define portIE_BIT            ( 0x00000001 )
+#define portEXL_BIT           ( 0x00000002 )
+#define portMX_BIT            ( 0x01000000 )       /* Allow access to DSP instructions. */
+#define portCU1_BIT           ( 0x20000000 )       /* enable CP1 for parts with hardware. */
+#define portFR_BIT            ( 0x04000000 )       /* Enable 64 bit floating point registers. */
 
 /* Bits within the CAUSE register. */
-#define portCORE_SW_0               ( 0x00000100 )
-#define portCORE_SW_1               ( 0x00000200 )
+#define portCORE_SW_0         ( 0x00000100 )
+#define portCORE_SW_1         ( 0x00000200 )
 
 /* The EXL bit is set to ensure interrupts do not occur while the context of
-the first task is being restored. */
+ * the first task is being restored. */
 #if ( __mips_hard_float == 1 )
-    #define portINITIAL_SR          ( portIE_BIT | portEXL_BIT | portMX_BIT | portFR_BIT | portCU1_BIT )
+    #define portINITIAL_SR    ( portIE_BIT | portEXL_BIT | portMX_BIT | portFR_BIT | portCU1_BIT )
 #else
-    #define portINITIAL_SR          ( portIE_BIT | portEXL_BIT | portMX_BIT )
+    #define portINITIAL_SR    ( portIE_BIT | portEXL_BIT | portMX_BIT )
 #endif
 
 /* The initial value to store into the FPU status and control register. This is
- only used on parts that support a hardware FPU. */
-#define portINITIAL_FPSCR           (0x1000000) /* High perf on denormal ops */
+ * only used on parts that support a hardware FPU. */
+#define portINITIAL_FPSCR    ( 0x1000000 )      /* High perf on denormal ops */
 
 
 /*
-By default port.c generates its tick interrupt from TIMER1.  The user can
-override this behaviour by:
-    1: Providing their own implementation of vApplicationSetupTickTimerInterrupt(),
-       which is the function that configures the timer.  The function is defined
-       as a weak symbol in this file so if the same function name is used in the
-       application code then the version in the application code will be linked
-       into the application in preference to the version defined in this file.
-    2: Define configTICK_INTERRUPT_VECTOR to the vector number of the timer used
-       to generate the tick interrupt.  For example, when timer 1 is used then
-       configTICK_INTERRUPT_VECTOR is set to _TIMER_1_VECTOR.
-       configTICK_INTERRUPT_VECTOR should be defined in FreeRTOSConfig.h.
-    3: Define configCLEAR_TICK_TIMER_INTERRUPT() to clear the interrupt in the
-       timer used to generate the tick interrupt.  For example, when timer 1 is
-       used configCLEAR_TICK_TIMER_INTERRUPT() is defined to
-       IFS0CLR = _IFS0_T1IF_MASK.
-*/
+ * By default port.c generates its tick interrupt from TIMER1.  The user can
+ * override this behaviour by:
+ *  1: Providing their own implementation of vApplicationSetupTickTimerInterrupt(),
+ *     which is the function that configures the timer.  The function is defined
+ *     as a weak symbol in this file so if the same function name is used in the
+ *     application code then the version in the application code will be linked
+ *     into the application in preference to the version defined in this file.
+ *  2: Define configTICK_INTERRUPT_VECTOR to the vector number of the timer used
+ *     to generate the tick interrupt.  For example, when timer 1 is used then
+ *     configTICK_INTERRUPT_VECTOR is set to _TIMER_1_VECTOR.
+ *     configTICK_INTERRUPT_VECTOR should be defined in FreeRTOSConfig.h.
+ *  3: Define configCLEAR_TICK_TIMER_INTERRUPT() to clear the interrupt in the
+ *     timer used to generate the tick interrupt.  For example, when timer 1 is
+ *     used configCLEAR_TICK_TIMER_INTERRUPT() is defined to
+ *     IFS0CLR = _IFS0_T1IF_MASK.
+ */
 #ifndef configTICK_INTERRUPT_VECTOR
-    #define configTICK_INTERRUPT_VECTOR _TIMER_1_VECTOR
-    #define configCLEAR_TICK_TIMER_INTERRUPT() IFS0CLR = _IFS0_T1IF_MASK
+    #define configTICK_INTERRUPT_VECTOR    _TIMER_1_VECTOR
+    #define configCLEAR_TICK_TIMER_INTERRUPT()    IFS0CLR = _IFS0_T1IF_MASK
 #else
     #ifndef configCLEAR_TICK_TIMER_INTERRUPT
         #error If configTICK_INTERRUPT_VECTOR is defined in application code then configCLEAR_TICK_TIMER_INTERRUPT must also be defined in application code.
@@ -103,34 +103,36 @@ override this behaviour by:
 #endif
 
 /* Let the user override the pre-loading of the initial RA with the address of
-prvTaskExitError() in case it messes up unwinding of the stack in the
-debugger - in which case configTASK_RETURN_ADDRESS can be defined as 0 (NULL). */
+ * prvTaskExitError() in case it messes up unwinding of the stack in the
+ * debugger - in which case configTASK_RETURN_ADDRESS can be defined as 0 (NULL). */
 #ifdef configTASK_RETURN_ADDRESS
-    #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
+    #define portTASK_RETURN_ADDRESS    configTASK_RETURN_ADDRESS
 #else
-    #define portTASK_RETURN_ADDRESS prvTaskExitError
+    #define portTASK_RETURN_ADDRESS    prvTaskExitError
 #endif
 
 /* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task
-stack checking.  A problem in the ISR stack will trigger an assert, not call the
-stack overflow hook function (because the stack overflow hook is specific to a
-task stack, not the ISR stack). */
-#if( configCHECK_FOR_STACK_OVERFLOW > 2 )
+ * stack checking.  A problem in the ISR stack will trigger an assert, not call the
+ * stack overflow hook function (because the stack overflow hook is specific to a
+ * task stack, not the ISR stack). */
+#if ( configCHECK_FOR_STACK_OVERFLOW > 2 )
 
-    /* Don't use 0xa5 as the stack fill bytes as that is used by the kernerl for
-    the task stacks, and so will legitimately appear in many positions within
-    the ISR stack. */
-    #define portISR_STACK_FILL_BYTE 0xee
+/* Don't use 0xa5 as the stack fill bytes as that is used by the kernel for
+ * the task stacks, and so will legitimately appear in many positions within
+ * the ISR stack. */
+    #define portISR_STACK_FILL_BYTE    0xee
 
-    static const uint8_t ucExpectedStackBytes[] = {
-                                    portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,     \
-                                    portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,     \
-                                    portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,     \
-                                    portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,     \
-                                    portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE };   \
+    static const uint8_t ucExpectedStackBytes[] =
+    {
+        portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
+        portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
+        portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
+        portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
+        portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE
+    }; \
 
-    #define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
-#else
+    #define portCHECK_ISR_STACK()    configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
+#else /* if ( configCHECK_FOR_STACK_OVERFLOW > 2 ) */
     /* Define the function away. */
     #define portCHECK_ISR_STACK()
 #endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
@@ -145,23 +147,23 @@ static void prvTaskExitError( void );
 /*-----------------------------------------------------------*/
 
 /* Records the interrupt nesting depth.  This is initialised to one as it is
-decremented to 0 when the first task starts. */
+ * decremented to 0 when the first task starts. */
 volatile UBaseType_t uxInterruptNesting = 0x01;
 
 /* Stores the task stack pointer when a switch is made to use the system stack. */
 UBaseType_t uxSavedTaskStackPointer = 0;
 
 /* The stack used by interrupt service routines that cause a context switch. */
-__attribute__ ((aligned(8))) StackType_t xISRStack[ configISR_STACK_SIZE ] = { 0 };
+__attribute__( ( aligned( 8 ) ) ) StackType_t xISRStack[ configISR_STACK_SIZE ] = { 0 };
 
 /* The top of stack value ensures there is enough space to store 6 registers on
-the callers stack, as some functions seem to want to do this.  8 byte alignment
-is required to allow double word floating point stack pushes generated by the
-compiler. */
+ * the callers stack, as some functions seem to want to do this.  8 byte alignment
+ * is required to allow double word floating point stack pushes generated by the
+ * compiler. */
 const StackType_t * const xISRStackTop = &( xISRStack[ ( configISR_STACK_SIZE & ~portBYTE_ALIGNMENT_MASK ) - 8 ] );
 
 /* Saved as part of the task context. Set to pdFALSE if the task does not
- require an FPU context. */
+ * require an FPU context. */
 #if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
     uint32_t ulTaskHasFPUContext = 0;
 #endif
@@ -171,37 +173,39 @@ const StackType_t * const xISRStackTop = &( xISRStack[ ( configISR_STACK_SIZE &
 /*
  * See header file for description.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
     /* Ensure 8 byte alignment is maintained when leaving this function. */
     pxTopOfStack--;
     pxTopOfStack--;
 
-    *pxTopOfStack = (StackType_t) 0xDEADBEEF;
+    *pxTopOfStack = ( StackType_t ) 0xDEADBEEF;
     pxTopOfStack--;
 
-    *pxTopOfStack = (StackType_t) 0x12345678;   /* Word to which the stack pointer will be left pointing after context restore. */
+    *pxTopOfStack = ( StackType_t ) 0x12345678; /* Word to which the stack pointer will be left pointing after context restore. */
     pxTopOfStack--;
 
-    *pxTopOfStack = (StackType_t) _CP0_GET_CAUSE();
+    *pxTopOfStack = ( StackType_t ) _CP0_GET_CAUSE();
     pxTopOfStack--;
 
-    *pxTopOfStack = (StackType_t) portINITIAL_SR;/* CP0_STATUS */
+    *pxTopOfStack = ( StackType_t ) portINITIAL_SR; /* CP0_STATUS */
     pxTopOfStack--;
 
-    *pxTopOfStack = (StackType_t) pxCode;       /* CP0_EPC */
+    *pxTopOfStack = ( StackType_t ) pxCode; /* CP0_EPC */
     pxTopOfStack--;
 
-    *pxTopOfStack = (StackType_t) 0x00000000;   /* DSPControl */
-    pxTopOfStack -= 7;                          /* Includes space for AC1 - AC3. */
+    *pxTopOfStack = ( StackType_t ) 0x00000000;              /* DSPControl */
+    pxTopOfStack -= 7;                                       /* Includes space for AC1 - AC3. */
 
-    *pxTopOfStack = (StackType_t) portTASK_RETURN_ADDRESS;  /* ra */
+    *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* ra */
     pxTopOfStack -= 15;
 
-    *pxTopOfStack = (StackType_t) pvParameters; /* Parameters to pass in. */
+    *pxTopOfStack = ( StackType_t ) pvParameters; /* Parameters to pass in. */
     pxTopOfStack -= 15;
 
-    *pxTopOfStack = (StackType_t) pdFALSE; /*by default disable FPU context save on parts with FPU */
+    *pxTopOfStack = ( StackType_t ) pdFALSE; /*by default disable FPU context save on parts with FPU */
 
     return pxTopOfStack;
 }
@@ -210,14 +214,17 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
 static void prvTaskExitError( void )
 {
     /* A function that implements a task must not exit or attempt to return to
-    its caller as there is nothing to return to.  If a task wants to exit it
-    should instead call vTaskDelete( NULL ).
-
-    Artificially force an assert() to be triggered if configASSERT() is
-    defined, then stop here so application writers can catch the error. */
+     * its caller as there is nothing to return to.  If a task wants to exit it
+     * should instead call vTaskDelete( NULL ).
+     *
+     * Artificially force an assert() to be triggered if configASSERT() is
+     * defined, then stop here so application writers can catch the error. */
     configASSERT( uxSavedTaskStackPointer == 0UL );
     portDISABLE_INTERRUPTS();
-    for( ;; );
+
+    for( ; ; )
+    {
+    }
 }
 /*-----------------------------------------------------------*/
 
@@ -230,9 +237,9 @@ static void prvTaskExitError( void )
  * vector number.  When Timer 1 is used the vector number is defined as
  * _TIMER_1_VECTOR.
  */
-__attribute__(( weak )) void vApplicationSetupTickTimerInterrupt( void )
+__attribute__( ( weak ) ) void vApplicationSetupTickTimerInterrupt( void )
 {
-const uint32_t ulCompareMatch = ( (configPERIPHERAL_CLOCK_HZ / portTIMER_PRESCALE) / configTICK_RATE_HZ ) - 1UL;
+    const uint32_t ulCompareMatch = ( ( configPERIPHERAL_CLOCK_HZ / portTIMER_PRESCALE ) / configTICK_RATE_HZ ) - 1UL;
 
     T1CON = 0x0000;
     T1CONbits.TCKPS = portPRESCALE_BITS;
@@ -250,18 +257,18 @@ const uint32_t ulCompareMatch = ( (configPERIPHERAL_CLOCK_HZ / portTIMER_PRESCAL
 }
 /*-----------------------------------------------------------*/
 
-void vPortEndScheduler(void)
+void vPortEndScheduler( void )
 {
     /* Not implemented in ports where there is nothing to return to.
-    Artificially force an assert. */
+     * Artificially force an assert. */
     configASSERT( uxInterruptNesting == 1000UL );
 }
 /*-----------------------------------------------------------*/
 
 BaseType_t xPortStartScheduler( void )
 {
-extern void vPortStartFirstTask( void );
-extern void *pxCurrentTCB;
+    extern void vPortStartFirstTask( void );
+    extern void * pxCurrentTCB;
 
     #if ( configCHECK_FOR_STACK_OVERFLOW > 2 )
     {
@@ -282,18 +289,18 @@ extern void *pxCurrentTCB;
     IEC0SET = 1 << _IEC0_CS0IE_POSITION;
 
     /* Setup the timer to generate the tick.  Interrupts will have been
-    disabled by the time we get here. */
+     * disabled by the time we get here. */
     vApplicationSetupTickTimerInterrupt();
 
     /* Kick off the highest priority task that has been created so far.
-    Its stack location is loaded into uxSavedTaskStackPointer. */
+     * Its stack location is loaded into uxSavedTaskStackPointer. */
     uxSavedTaskStackPointer = *( UBaseType_t * ) pxCurrentTCB;
     vPortStartFirstTask();
 
     /* Should never get here as the tasks will now be executing!  Call the task
-    exit error function to prevent compiler warnings about a static function
-    not being called in the case that the application writer overrides this
-    functionality by defining configTASK_RETURN_ADDRESS. */
+     * exit error function to prevent compiler warnings about a static function
+     * not being called in the case that the application writer overrides this
+     * functionality by defining configTASK_RETURN_ADDRESS. */
     prvTaskExitError();
 
     return pdFALSE;
@@ -302,7 +309,7 @@ extern void *pxCurrentTCB;
 
 void vPortIncrementTick( void )
 {
-UBaseType_t uxSavedStatus;
+    UBaseType_t uxSavedStatus;
 
     uxSavedStatus = uxPortSetInterruptMaskFromISR();
     {
@@ -324,16 +331,17 @@ UBaseType_t uxSavedStatus;
 
 UBaseType_t uxPortSetInterruptMaskFromISR( void )
 {
-UBaseType_t uxSavedStatusRegister;
+    UBaseType_t uxSavedStatusRegister;
 
     __builtin_disable_interrupts();
     uxSavedStatusRegister = _CP0_GET_STATUS() | 0x01;
+
     /* This clears the IPL bits, then sets them to
-    configMAX_SYSCALL_INTERRUPT_PRIORITY.  This function should not be called
-    from an interrupt that has a priority above
-    configMAX_SYSCALL_INTERRUPT_PRIORITY so, when used correctly, the action
-    can only result in the IPL being unchanged or raised, and therefore never
-    lowered. */
+     * configMAX_SYSCALL_INTERRUPT_PRIORITY.  This function should not be called
+     * from an interrupt that has a priority above
+     * configMAX_SYSCALL_INTERRUPT_PRIORITY so, when used correctly, the action
+     * can only result in the IPL being unchanged or raised, and therefore never
+     * lowered. */
     _CP0_SET_STATUS( ( ( uxSavedStatusRegister & ( ~portALL_IPL_BITS ) ) ) | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) );
 
     return uxSavedStatusRegister;
@@ -348,17 +356,17 @@ void vPortClearInterruptMaskFromISR( UBaseType_t uxSavedStatusRegister )
 
 #if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
 
-    void vPortTaskUsesFPU(void)
+    void vPortTaskUsesFPU( void )
     {
-    extern void vPortInitialiseFPSCR( uint32_t uxFPSCRInit );
+        extern void vPortInitialiseFPSCR( uint32_t uxFPSCRInit );
 
         portENTER_CRITICAL();
 
         /* Initialise the floating point status register. */
-        vPortInitialiseFPSCR(portINITIAL_FPSCR);
+        vPortInitialiseFPSCR( portINITIAL_FPSCR );
 
         /* A task is registering the fact that it needs a FPU context. Set the
-        FPU flag (saved as part of the task context). */
+         * FPU flag (saved as part of the task context). */
         ulTaskHasFPUContext = pdTRUE;
 
         portEXIT_CRITICAL();
diff --git a/portable/MPLAB/PIC32MZ/portmacro.h b/portable/MPLAB/PIC32MZ/portmacro.h
index 371bcab6f..63b69b436 100644
--- a/portable/MPLAB/PIC32MZ/portmacro.h
+++ b/portable/MPLAB/PIC32MZ/portmacro.h
@@ -49,102 +49,103 @@
  */
 
 /* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint32_t
-#define portBASE_TYPE   long
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-    not need to be guarded with a critical section. */
-    #define portTICK_TYPE_IS_ATOMIC 1
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+    #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portBYTE_ALIGNMENT          8
-#define portSTACK_GROWTH            -1
-#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT    8
+#define portSTACK_GROWTH      -1
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
 /*-----------------------------------------------------------*/
 
 /* Critical section management. */
-#define portIPL_SHIFT               ( 10UL )
+#define portIPL_SHIFT       ( 10UL )
+
 /* Don't straddle the CEE bit.  Interrupts calling FreeRTOS functions should
-never have higher IPL bits set anyway. */
-#define portALL_IPL_BITS            ( 0x7FUL << portIPL_SHIFT )
-#define portSW0_BIT                 ( 0x01 << 8 )
+ * never have higher IPL bits set anyway. */
+#define portALL_IPL_BITS    ( 0x7FUL << portIPL_SHIFT )
+#define portSW0_BIT         ( 0x01 << 8 )
 
 /* This clears the IPL bits, then sets them to
-configMAX_SYSCALL_INTERRUPT_PRIORITY.  An extra check is performed if
-configASSERT() is defined to ensure an assertion handler does not inadvertently
-attempt to lower the IPL when the call to assert was triggered because the IPL
-value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY when an ISR
-safe FreeRTOS API function was executed.  ISR safe FreeRTOS API functions are
-those that end in FromISR.  FreeRTOS maintains a separate interrupt API to
-ensure API function and interrupt entry is as fast and as simple as possible. */
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.  An extra check is performed if
+ * configASSERT() is defined to ensure an assertion handler does not inadvertently
+ * attempt to lower the IPL when the call to assert was triggered because the IPL
+ * value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY when an ISR
+ * safe FreeRTOS API function was executed.  ISR safe FreeRTOS API functions are
+ * those that end in FromISR.  FreeRTOS maintains a separate interrupt API to
+ * ensure API function and interrupt entry is as fast and as simple as possible. */
 #ifdef configASSERT
-    #define portDISABLE_INTERRUPTS()                                            \
-    {                                                                           \
-    uint32_t ulStatus;                                                          \
-                                                                                \
-        /* Mask interrupts at and below the kernel interrupt priority. */       \
-        ulStatus = _CP0_GET_STATUS();                                           \
-                                                                                \
-        /* Is the current IPL below configMAX_SYSCALL_INTERRUPT_PRIORITY? */    \
+    #define portDISABLE_INTERRUPTS()                                                                      \
+    {                                                                                                     \
+        uint32_t ulStatus;                                                                                \
+                                                                                                          \
+        /* Mask interrupts at and below the kernel interrupt priority. */                                 \
+        ulStatus = _CP0_GET_STATUS();                                                                     \
+                                                                                                          \
+        /* Is the current IPL below configMAX_SYSCALL_INTERRUPT_PRIORITY? */                              \
         if( ( ( ulStatus & portALL_IPL_BITS ) >> portIPL_SHIFT ) < configMAX_SYSCALL_INTERRUPT_PRIORITY ) \
-        {                                                                       \
-            ulStatus &= ~portALL_IPL_BITS;                                      \
-            _CP0_SET_STATUS( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
-        }                                                                       \
+        {                                                                                                 \
+            ulStatus &= ~portALL_IPL_BITS;                                                                \
+            _CP0_SET_STATUS( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) );  \
+        }                                                                                                 \
     }
 #else /* configASSERT */
-    #define portDISABLE_INTERRUPTS()                                        \
-    {                                                                       \
-    uint32_t ulStatus;                                                      \
-                                                                            \
-        /* Mask interrupts at and below the kernel interrupt priority. */   \
-        ulStatus = _CP0_GET_STATUS();                                       \
-        ulStatus &= ~portALL_IPL_BITS;                                      \
+    #define portDISABLE_INTERRUPTS()                                                                 \
+    {                                                                                                \
+        uint32_t ulStatus;                                                                           \
+                                                                                                     \
+        /* Mask interrupts at and below the kernel interrupt priority. */                            \
+        ulStatus = _CP0_GET_STATUS();                                                                \
+        ulStatus &= ~portALL_IPL_BITS;                                                               \
         _CP0_SET_STATUS( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
     }
 #endif /* configASSERT */
 
-#define portENABLE_INTERRUPTS()                                         \
-{                                                                       \
-uint32_t ulStatus;                                                      \
-                                                                        \
-    /* Unmask all interrupts. */                                        \
-    ulStatus = _CP0_GET_STATUS();                                       \
-    ulStatus &= ~portALL_IPL_BITS;                                      \
-    _CP0_SET_STATUS( ulStatus );                                        \
-}
+#define portENABLE_INTERRUPTS()        \
+    {                                  \
+        uint32_t ulStatus;             \
+                                       \
+        /* Unmask all interrupts. */   \
+        ulStatus = _CP0_GET_STATUS();  \
+        ulStatus &= ~portALL_IPL_BITS; \
+        _CP0_SET_STATUS( ulStatus );   \
+    }
 
 
 extern void vTaskEnterCritical( void );
 extern void vTaskExitCritical( void );
-#define portCRITICAL_NESTING_IN_TCB 1
-#define portENTER_CRITICAL()        vTaskEnterCritical()
-#define portEXIT_CRITICAL()         vTaskExitCritical()
+#define portCRITICAL_NESTING_IN_TCB    1
+#define portENTER_CRITICAL()    vTaskEnterCritical()
+#define portEXIT_CRITICAL()     vTaskExitCritical()
 
 extern UBaseType_t uxPortSetInterruptMaskFromISR();
 extern void vPortClearInterruptMaskFromISR( UBaseType_t );
-#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMaskFromISR()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) vPortClearInterruptMaskFromISR( uxSavedStatusRegister )
+#define portSET_INTERRUPT_MASK_FROM_ISR()                             uxPortSetInterruptMaskFromISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister )    vPortClearInterruptMaskFromISR( uxSavedStatusRegister )
 
 #if ( __mips_hard_float == 0 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
     #error configUSE_TASK_FPU_SUPPORT can only be set to 1 when the part supports a hardware FPU module.
@@ -152,27 +153,27 @@ extern void vPortClearInterruptMaskFromISR( UBaseType_t );
 
 #if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
     void vPortTaskUsesFPU( void );
-    #define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
+    #define portTASK_USES_FLOATING_POINT()    vPortTaskUsesFPU()
 #endif
 
 #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-    #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+    #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
 #endif
 
 #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
 
-    /* Check the configuration. */
-    #if( configMAX_PRIORITIES > 32 )
+/* Check the configuration. */
+    #if ( configMAX_PRIORITIES > 32 )
         #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
     #endif
 
-    /* Store/clear the ready priorities in a bit map. */
-    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+/* Store/clear the ready priorities in a bit map. */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 
-    /*-----------------------------------------------------------*/
+/*-----------------------------------------------------------*/
 
-    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - _clz( ( uxReadyPriorities ) ) )
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - _clz( ( uxReadyPriorities ) ) )
 
 #endif /* taskRECORD_READY_PRIORITY */
 
@@ -180,29 +181,29 @@ extern void vPortClearInterruptMaskFromISR( UBaseType_t );
 
 /* Task utilities. */
 
-#define portYIELD()                             \
-{                                               \
-uint32_t ulCause;                               \
-                                                \
-    /* Trigger software interrupt. */           \
-    ulCause = _CP0_GET_CAUSE();                 \
-    ulCause |= portSW0_BIT;                     \
-    _CP0_SET_CAUSE( ulCause );                  \
-}
+#define portYIELD()                       \
+    {                                     \
+        uint32_t ulCause;                 \
+                                          \
+        /* Trigger software interrupt. */ \
+        ulCause = _CP0_GET_CAUSE();       \
+        ulCause |= portSW0_BIT;           \
+        _CP0_SET_CAUSE( ulCause );        \
+    }
 
 extern volatile UBaseType_t uxInterruptNesting;
-#define portASSERT_IF_IN_ISR() configASSERT( uxInterruptNesting == 0 )
+#define portASSERT_IF_IN_ISR()    configASSERT( uxInterruptNesting == 0 )
 
-#define portNOP()   __asm volatile ( "nop" )
+#define portNOP()                 __asm volatile ( "nop" )
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn))
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters ) __attribute__( ( noreturn ) )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 /*-----------------------------------------------------------*/
 
-#define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired ) { portYIELD(); } } while( 0 )
+#define portEND_SWITCHING_ISR( xSwitchRequired )              do { if( xSwitchRequired ) { portYIELD(); } } while( 0 )
 
 /* Required by the kernel aware debugger. */
 #ifdef __DEBUG
diff --git a/portable/MSVC-MingW/port.c b/portable/MSVC-MingW/port.c
index c85cfc193..0a0fba6a3 100644
--- a/portable/MSVC-MingW/port.c
+++ b/portable/MSVC-MingW/port.c
@@ -39,14 +39,14 @@
     #pragma comment(lib, "winmm.lib")
 #endif
 
-#define portMAX_INTERRUPTS              ( ( uint32_t ) sizeof( uint32_t ) * 8UL ) /* The number of bits in an uint32_t. */
-#define portNO_CRITICAL_NESTING         ( ( uint32_t ) 0 )
+#define portMAX_INTERRUPTS                          ( ( uint32_t ) sizeof( uint32_t ) * 8UL ) /* The number of bits in an uint32_t. */
+#define portNO_CRITICAL_NESTING                     ( ( uint32_t ) 0 )
 
 /* The priorities at which the various components of the simulation execute. */
-#define portDELETE_SELF_THREAD_PRIORITY          THREAD_PRIORITY_TIME_CRITICAL /* Must be highest. */
-#define portSIMULATED_INTERRUPTS_THREAD_PRIORITY THREAD_PRIORITY_TIME_CRITICAL
-#define portSIMULATED_TIMER_THREAD_PRIORITY      THREAD_PRIORITY_HIGHEST
-#define portTASK_THREAD_PRIORITY                 THREAD_PRIORITY_ABOVE_NORMAL
+#define portDELETE_SELF_THREAD_PRIORITY             THREAD_PRIORITY_TIME_CRITICAL /* Must be highest. */
+#define portSIMULATED_INTERRUPTS_THREAD_PRIORITY    THREAD_PRIORITY_TIME_CRITICAL
+#define portSIMULATED_TIMER_THREAD_PRIORITY         THREAD_PRIORITY_HIGHEST
+#define portTASK_THREAD_PRIORITY                    THREAD_PRIORITY_ABOVE_NORMAL
 
 /*
  * Created as a high priority thread, this function uses a timer to simulate
@@ -87,47 +87,47 @@ static BOOL WINAPI prvEndProcess( DWORD dwCtrlType );
 /*-----------------------------------------------------------*/
 
 /* The WIN32 simulator runs each task in a thread.  The context switching is
-managed by the threads, so the task stack does not have to be managed directly,
-although the task stack is still used to hold an xThreadState structure this is
-the only thing it will ever hold.  The structure indirectly maps the task handle
-to a thread handle. */
+ * managed by the threads, so the task stack does not have to be managed directly,
+ * although the task stack is still used to hold an xThreadState structure this is
+ * the only thing it will ever hold.  The structure indirectly maps the task handle
+ * to a thread handle. */
 typedef struct
 {
     /* Handle of the thread that executes the task. */
-    void *pvThread;
+    void * pvThread;
 
     /* Event used to make sure the thread does not execute past a yield point
-    between the call to SuspendThread() to suspend the thread and the
-    asynchronous SuspendThread() operation actually being performed. */
-    void *pvYieldEvent;
+     * between the call to SuspendThread() to suspend the thread and the
+     * asynchronous SuspendThread() operation actually being performed. */
+    void * pvYieldEvent;
 } ThreadState_t;
 
 /* Simulated interrupts waiting to be processed.  This is a bit mask where each
-bit represents one interrupt, so a maximum of 32 interrupts can be simulated. */
+ * bit represents one interrupt, so a maximum of 32 interrupts can be simulated. */
 static volatile uint32_t ulPendingInterrupts = 0UL;
 
 /* An event used to inform the simulated interrupt processing thread (a high
-priority thread that simulated interrupt processing) that an interrupt is
-pending. */
-static void *pvInterruptEvent = NULL;
+ * priority thread that simulated interrupt processing) that an interrupt is
+ * pending. */
+static void * pvInterruptEvent = NULL;
 
 /* Mutex used to protect all the simulated interrupt variables that are accessed
-by multiple threads. */
-static void *pvInterruptEventMutex = NULL;
+ * by multiple threads. */
+static void * pvInterruptEventMutex = NULL;
 
 /* The critical nesting count for the currently executing task.  This is
-initialised to a non-zero value so interrupts do not become enabled during
-the initialisation phase.  As each task has its own critical nesting value
-ulCriticalNesting will get set to zero when the first task runs.  This
-initialisation is probably not critical in this simulated environment as the
-simulated interrupt handlers do not get created until the FreeRTOS scheduler is
-started anyway. */
+ * initialised to a non-zero value so interrupts do not become enabled during
+ * the initialisation phase.  As each task has its own critical nesting value
+ * ulCriticalNesting will get set to zero when the first task runs.  This
+ * initialisation is probably not critical in this simulated environment as the
+ * simulated interrupt handlers do not get created until the FreeRTOS scheduler is
+ * started anyway. */
 static volatile uint32_t ulCriticalNesting = 9999UL;
 
 /* Handlers for all the simulated software interrupts.  The first two positions
-are used for the Yield and Tick interrupts so are handled slightly differently,
-all the other interrupts can be user defined. */
-static uint32_t (*ulIsrHandler[ portMAX_INTERRUPTS ])( void ) = { 0 };
+ * are used for the Yield and Tick interrupts so are handled slightly differently,
+ * all the other interrupts can be user defined. */
+static uint32_t (* ulIsrHandler[ portMAX_INTERRUPTS ])( void ) = { 0 };
 
 /* Pointer to the TCB of the currently executing task. */
 extern void * volatile pxCurrentTCB;
@@ -139,8 +139,8 @@ static BaseType_t xPortRunning = pdFALSE;
 
 static DWORD WINAPI prvSimulatedPeripheralTimer( LPVOID lpParameter )
 {
-TickType_t xMinimumWindowsBlockTime;
-TIMECAPS xTimeCaps;
+    TickType_t xMinimumWindowsBlockTime;
+    TIMECAPS xTimeCaps;
 
     /* Set the timer resolution to the maximum possible. */
     if( timeGetDevCaps( &xTimeCaps, sizeof( xTimeCaps ) ) == MMSYSERR_NOERROR )
@@ -149,7 +149,7 @@ TIMECAPS xTimeCaps;
         timeBeginPeriod( xTimeCaps.wPeriodMin );
 
         /* Register an exit handler so the timeBeginPeriod() function can be
-        matched with a timeEndPeriod() when the application exits. */
+         * matched with a timeEndPeriod() when the application exits. */
         SetConsoleCtrlHandler( prvEndProcess, TRUE );
     }
     else
@@ -163,11 +163,11 @@ TIMECAPS xTimeCaps;
     while( xPortRunning == pdTRUE )
     {
         /* Wait until the timer expires and we can access the simulated interrupt
-        variables.  *NOTE* this is not a 'real time' way of generating tick
-        events as the next wake time should be relative to the previous wake
-        time, not the time that Sleep() is called.  It is done this way to
-        prevent overruns in this very non real time simulated/emulated
-        environment. */
+         * variables.  *NOTE* this is not a 'real time' way of generating tick
+         * events as the next wake time should be relative to the previous wake
+         * time, not the time that Sleep() is called.  It is done this way to
+         * prevent overruns in this very non real time simulated/emulated
+         * environment. */
         if( portTICK_PERIOD_MS < xMinimumWindowsBlockTime )
         {
             Sleep( xMinimumWindowsBlockTime );
@@ -182,40 +182,39 @@ TIMECAPS xTimeCaps;
             configASSERT( xPortRunning );
 
             /* Can't proceed if in a critical section as pvInterruptEventMutex won't
-            be available. */
+             * be available. */
             WaitForSingleObject( pvInterruptEventMutex, INFINITE );
 
             /* The timer has expired, generate the simulated tick event. */
             ulPendingInterrupts |= ( 1 << portINTERRUPT_TICK );
 
             /* The interrupt is now pending - notify the simulated interrupt
-            handler thread.  Must be outside of a critical section to get here so
-            the handler thread can execute immediately pvInterruptEventMutex is
-            released. */
+             * handler thread.  Must be outside of a critical section to get here so
+             * the handler thread can execute immediately pvInterruptEventMutex is
+             * released. */
             configASSERT( ulCriticalNesting == 0UL );
             SetEvent( pvInterruptEvent );
 
             /* Give back the mutex so the simulated interrupt handler unblocks
-            and can access the interrupt handler variables. */
+             * and can access the interrupt handler variables. */
             ReleaseMutex( pvInterruptEventMutex );
         }
     }
 
-
     return 0;
 }
 /*-----------------------------------------------------------*/
 
 static BOOL WINAPI prvEndProcess( DWORD dwCtrlType )
 {
-TIMECAPS xTimeCaps;
+    TIMECAPS xTimeCaps;
 
     ( void ) dwCtrlType;
 
     if( timeGetDevCaps( &xTimeCaps, sizeof( xTimeCaps ) ) == MMSYSERR_NOERROR )
     {
         /* Match the call to timeBeginPeriod( xTimeCaps.wPeriodMin ) made when
-        the process started with a timeEndPeriod() as the process exits. */
+         * the process started with a timeEndPeriod() as the process exits. */
         timeEndPeriod( xTimeCaps.wPeriodMin );
     }
 
@@ -223,27 +222,29 @@ TIMECAPS xTimeCaps;
 }
 /*-----------------------------------------------------------*/
 
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
-ThreadState_t *pxThreadState = NULL;
-int8_t *pcTopOfStack = ( int8_t * ) pxTopOfStack;
-const SIZE_T xStackSize = 1024; /* Set the size to a small number which will get rounded up to the minimum possible. */
+    ThreadState_t * pxThreadState = NULL;
+    int8_t * pcTopOfStack = ( int8_t * ) pxTopOfStack;
+    const SIZE_T xStackSize = 1024; /* Set the size to a small number which will get rounded up to the minimum possible. */
 
     /* In this simulated case a stack is not initialised, but instead a thread
-    is created that will execute the task being created.  The thread handles
-    the context switching itself.  The ThreadState_t object is placed onto
-    the stack that was created for the task - so the stack buffer is still
-    used, just not in the conventional way.  It will not be used for anything
-    other than holding this structure. */
+     * is created that will execute the task being created.  The thread handles
+     * the context switching itself.  The ThreadState_t object is placed onto
+     * the stack that was created for the task - so the stack buffer is still
+     * used, just not in the conventional way.  It will not be used for anything
+     * other than holding this structure. */
     pxThreadState = ( ThreadState_t * ) ( pcTopOfStack - sizeof( ThreadState_t ) );
 
     /* Create the event used to prevent the thread from executing past its yield
-    point if the SuspendThread() call that suspends the thread does not take
-    effect immediately (it is an asynchronous call). */
-    pxThreadState->pvYieldEvent = CreateEvent(  NULL,  /* Default security attributes. */
-                                                FALSE, /* Auto reset. */
-                                                FALSE, /* Start not signalled. */
-                                                NULL );/* No name. */
+     * point if the SuspendThread() call that suspends the thread does not take
+     * effect immediately (it is an asynchronous call). */
+    pxThreadState->pvYieldEvent = CreateEvent( NULL,   /* Default security attributes. */
+                                               FALSE,  /* Auto reset. */
+                                               FALSE,  /* Start not signalled. */
+                                               NULL ); /* No name. */
 
     /* Create the thread itself. */
     pxThreadState->pvThread = CreateThread( NULL, xStackSize, ( LPTHREAD_START_ROUTINE ) pxCode, pvParameters, CREATE_SUSPENDED | STACK_SIZE_PARAM_IS_A_RESERVATION, NULL );
@@ -258,15 +259,16 @@ const SIZE_T xStackSize = 1024; /* Set the size to a small number which will get
 
 BaseType_t xPortStartScheduler( void )
 {
-void *pvHandle = NULL;
-int32_t lSuccess;
-ThreadState_t *pxThreadState = NULL;
-SYSTEM_INFO xSystemInfo;
+    void * pvHandle = NULL;
+    int32_t lSuccess;
+    ThreadState_t * pxThreadState = NULL;
+    SYSTEM_INFO xSystemInfo;
 
     /* This port runs windows threads with extremely high priority.  All the
-    threads execute on the same core - to prevent locking up the host only start
-    if the host has multiple cores. */
+     * threads execute on the same core - to prevent locking up the host only start
+     * if the host has multiple cores. */
     GetSystemInfo( &xSystemInfo );
+
     if( xSystemInfo.dwNumberOfProcessors <= 1 )
     {
         printf( "This version of the FreeRTOS Windows port can only be used on multi-core hosts.\r\n" );
@@ -277,7 +279,7 @@ SYSTEM_INFO xSystemInfo;
         lSuccess = pdPASS;
 
         /* The highest priority class is used to [try to] prevent other Windows
-        activity interfering with FreeRTOS timing too much. */
+         * activity interfering with FreeRTOS timing too much. */
         if( SetPriorityClass( GetCurrentProcess(), REALTIME_PRIORITY_CLASS ) == 0 )
         {
             printf( "SetPriorityClass() failed\r\n" );
@@ -288,7 +290,7 @@ SYSTEM_INFO xSystemInfo;
         vPortSetInterruptHandler( portINTERRUPT_TICK, prvProcessTickInterrupt );
 
         /* Create the events and mutexes that are used to synchronise all the
-        threads. */
+         * threads. */
         pvInterruptEventMutex = CreateMutex( NULL, FALSE, NULL );
         pvInterruptEvent = CreateEvent( NULL, FALSE, FALSE, NULL );
 
@@ -298,9 +300,10 @@ SYSTEM_INFO xSystemInfo;
         }
 
         /* Set the priority of this thread such that it is above the priority of
-        the threads that run tasks.  This higher priority is required to ensure
-        simulated interrupts take priority over tasks. */
+         * the threads that run tasks.  This higher priority is required to ensure
+         * simulated interrupts take priority over tasks. */
         pvHandle = GetCurrentThread();
+
         if( pvHandle == NULL )
         {
             lSuccess = pdFAIL;
@@ -313,6 +316,7 @@ SYSTEM_INFO xSystemInfo;
         {
             lSuccess = pdFAIL;
         }
+
         SetThreadPriorityBoost( pvHandle, TRUE );
         SetThreadAffinityMask( pvHandle, 0x01 );
     }
@@ -320,10 +324,11 @@ SYSTEM_INFO xSystemInfo;
     if( lSuccess == pdPASS )
     {
         /* Start the thread that simulates the timer peripheral to generate
-        tick interrupts.  The priority is set below that of the simulated
-        interrupt handler so the interrupt event mutex is used for the
-        handshake / overrun protection. */
+         * tick interrupts.  The priority is set below that of the simulated
+         * interrupt handler so the interrupt event mutex is used for the
+         * handshake / overrun protection. */
         pvHandle = CreateThread( NULL, 0, prvSimulatedPeripheralTimer, NULL, CREATE_SUSPENDED, NULL );
+
         if( pvHandle != NULL )
         {
             SetThreadPriority( pvHandle, portSIMULATED_TIMER_THREAD_PRIORITY );
@@ -333,7 +338,7 @@ SYSTEM_INFO xSystemInfo;
         }
 
         /* Start the highest priority task by obtaining its associated thread
-        state structure, in which is stored the thread handle. */
+         * state structure, in which is stored the thread handle. */
         pxThreadState = ( ThreadState_t * ) *( ( size_t * ) pxCurrentTCB );
         ulCriticalNesting = portNO_CRITICAL_NESTING;
 
@@ -344,12 +349,12 @@ SYSTEM_INFO xSystemInfo;
         xPortRunning = pdTRUE;
 
         /* Handle all simulated interrupts - including yield requests and
-        simulated ticks. */
+         * simulated ticks. */
         prvProcessSimulatedInterrupts();
     }
 
     /* Would not expect to return from prvProcessSimulatedInterrupts(), so should
-    not get here. */
+     * not get here. */
     return 0;
 }
 /*-----------------------------------------------------------*/
@@ -363,7 +368,7 @@ static uint32_t prvProcessYieldInterrupt( void )
 
 static uint32_t prvProcessTickInterrupt( void )
 {
-uint32_t ulSwitchRequired;
+    uint32_t ulSwitchRequired;
 
     /* Process the tick itself. */
     configASSERT( xPortRunning );
@@ -375,21 +380,21 @@ uint32_t ulSwitchRequired;
 
 static void prvProcessSimulatedInterrupts( void )
 {
-uint32_t ulSwitchRequired, i;
-ThreadState_t *pxThreadState;
-void *pvObjectList[ 2 ];
-CONTEXT xContext;
-DWORD xWinApiResult;
-const DWORD xTimeoutMilliseconds = 1000;
+    uint32_t ulSwitchRequired, i;
+    ThreadState_t * pxThreadState;
+    void * pvObjectList[ 2 ];
+    CONTEXT xContext;
+    DWORD xWinApiResult;
+    const DWORD xTimeoutMilliseconds = 1000;
 
     /* Going to block on the mutex that ensured exclusive access to the simulated
-    interrupt objects, and the event that signals that a simulated interrupt
-    should be processed. */
+     * interrupt objects, and the event that signals that a simulated interrupt
+     * should be processed. */
     pvObjectList[ 0 ] = pvInterruptEventMutex;
     pvObjectList[ 1 ] = pvInterruptEvent;
 
     /* Create a pending tick to ensure the first task is started as soon as
-    this thread pends. */
+     * this thread pends. */
     ulPendingInterrupts |= ( 1 << portINTERRUPT_TICK );
     SetEvent( pvInterruptEvent );
 
@@ -404,18 +409,18 @@ const DWORD xTimeoutMilliseconds = 1000;
         if( xWinApiResult != WAIT_TIMEOUT )
         {
             /* Cannot be in a critical section to get here.  Tasks that exit a
-            critical section will block on a yield mutex to wait for an interrupt to
-            process if an interrupt was set pending while the task was inside the
-            critical section.  xInsideInterrupt prevents interrupts that contain
-            critical sections from doing the same. */
+             * critical section will block on a yield mutex to wait for an interrupt to
+             * process if an interrupt was set pending while the task was inside the
+             * critical section.  xInsideInterrupt prevents interrupts that contain
+             * critical sections from doing the same. */
             xInsideInterrupt = pdTRUE;
 
             /* Used to indicate whether the simulated interrupt processing has
-            necessitated a context switch to another task/thread. */
+             * necessitated a context switch to another task/thread. */
             ulSwitchRequired = pdFALSE;
 
             /* For each interrupt we are interested in processing, each of which is
-            represented by a bit in the 32bit ulPendingInterrupts variable. */
+             * represented by a bit in the 32bit ulPendingInterrupts variable. */
             for( i = 0; i < portMAX_INTERRUPTS; i++ )
             {
                 /* Is the simulated interrupt pending? */
@@ -425,7 +430,7 @@ const DWORD xTimeoutMilliseconds = 1000;
                     if( ulIsrHandler[ i ] != NULL )
                     {
                         /* Run the actual handler.  Handlers return pdTRUE if they
-                        necessitate a context switch. */
+                         * necessitate a context switch. */
                         if( ulIsrHandler[ i ]() != pdFALSE )
                         {
                             /* A bit mask is used purely to help debugging. */
@@ -440,7 +445,7 @@ const DWORD xTimeoutMilliseconds = 1000;
 
             if( ulSwitchRequired != pdFALSE )
             {
-                void *pvOldCurrentTCB;
+                void * pvOldCurrentTCB;
 
                 pvOldCurrentTCB = pxCurrentTCB;
 
@@ -448,51 +453,51 @@ const DWORD xTimeoutMilliseconds = 1000;
                 vTaskSwitchContext();
 
                 /* If the task selected to enter the running state is not the task
-                that is already in the running state. */
+                 * that is already in the running state. */
                 if( pvOldCurrentTCB != pxCurrentTCB )
                 {
                     /* Suspend the old thread.  In the cases where the (simulated)
-                    interrupt is asynchronous (tick event swapping a task out rather
-                    than a task blocking or yielding) it doesn't matter if the
-                    'suspend' operation doesn't take effect immediately - if it
-                    doesn't it would just be like the interrupt occurring slightly
-                    later.  In cases where the yield was caused by a task blocking
-                    or yielding then the task will block on a yield event after the
-                    yield operation in case the 'suspend' operation doesn't take
-                    effect immediately.  */
-                    pxThreadState = ( ThreadState_t *) *( ( size_t * ) pvOldCurrentTCB );
+                     * interrupt is asynchronous (tick event swapping a task out rather
+                     * than a task blocking or yielding) it doesn't matter if the
+                     * 'suspend' operation doesn't take effect immediately - if it
+                     * doesn't it would just be like the interrupt occurring slightly
+                     * later.  In cases where the yield was caused by a task blocking
+                     * or yielding then the task will block on a yield event after the
+                     * yield operation in case the 'suspend' operation doesn't take
+                     * effect immediately.  */
+                    pxThreadState = ( ThreadState_t * ) *( ( size_t * ) pvOldCurrentTCB );
                     SuspendThread( pxThreadState->pvThread );
 
                     /* Ensure the thread is actually suspended by performing a
-                    synchronous operation that can only complete when the thread is
-                    actually suspended.  The below code asks for dummy register
-                    data.  Experimentation shows that these two lines don't appear
-                    to do anything now, but according to
-                    https://devblogs.microsoft.com/oldnewthing/20150205-00/?p=44743
-                    they do - so as they do not harm (slight run-time hit). */
+                     *  synchronous operation that can only complete when the thread is
+                     *  actually suspended.  The below code asks for dummy register
+                     *  data.  Experimentation shows that these two lines don't appear
+                     *  to do anything now, but according to
+                     *  https://devblogs.microsoft.com/oldnewthing/20150205-00/?p=44743
+                     *  they do - so as they do not harm (slight run-time hit). */
                     xContext.ContextFlags = CONTEXT_INTEGER;
                     ( void ) GetThreadContext( pxThreadState->pvThread, &xContext );
 
                     /* Obtain the state of the task now selected to enter the
-                    Running state. */
-                    pxThreadState = ( ThreadState_t * ) ( *( size_t *) pxCurrentTCB );
+                     * Running state. */
+                    pxThreadState = ( ThreadState_t * ) ( *( size_t * ) pxCurrentTCB );
 
                     /* pxThreadState->pvThread can be NULL if the task deleted
-                    itself - but a deleted task should never be resumed here. */
+                     * itself - but a deleted task should never be resumed here. */
                     configASSERT( pxThreadState->pvThread != NULL );
                     ResumeThread( pxThreadState->pvThread );
                 }
             }
 
             /* If the thread that is about to be resumed stopped running
-            because it yielded then it will wait on an event when it resumed
-            (to ensure it does not continue running after the call to
-            SuspendThread() above as SuspendThread() is asynchronous).
-            Signal the event to ensure the thread can proceed now it is
-            valid for it to do so.  Signaling the event is benign in the case that
-            the task was switched out asynchronously by an interrupt as the event
-            is reset before the task blocks on it. */
-            pxThreadState = ( ThreadState_t * ) ( *( size_t *) pxCurrentTCB );
+             * because it yielded then it will wait on an event when it resumed
+             * (to ensure it does not continue running after the call to
+             * SuspendThread() above as SuspendThread() is asynchronous).
+             * Signal the event to ensure the thread can proceed now it is
+             * valid for it to do so.  Signaling the event is benign in the case that
+             * the task was switched out asynchronously by an interrupt as the event
+             * is reset before the task blocks on it. */
+            pxThreadState = ( ThreadState_t * ) ( *( size_t * ) pxCurrentTCB );
             SetEvent( pxThreadState->pvYieldEvent );
             ReleaseMutex( pvInterruptEventMutex );
         }
@@ -500,29 +505,29 @@ const DWORD xTimeoutMilliseconds = 1000;
 }
 /*-----------------------------------------------------------*/
 
-void vPortDeleteThread( void *pvTaskToDelete )
+void vPortDeleteThread( void * pvTaskToDelete )
 {
-ThreadState_t *pxThreadState;
-uint32_t ulErrorCode;
+    ThreadState_t * pxThreadState;
+    uint32_t ulErrorCode;
 
     /* Remove compiler warnings if configASSERT() is not defined. */
     ( void ) ulErrorCode;
 
     /* Find the handle of the thread being deleted. */
-    pxThreadState = ( ThreadState_t * ) ( *( size_t *) pvTaskToDelete );
+    pxThreadState = ( ThreadState_t * ) ( *( size_t * ) pvTaskToDelete );
 
     /* Check that the thread is still valid, it might have been closed by
-    vPortCloseRunningThread() - which will be the case if the task associated
-    with the thread originally deleted itself rather than being deleted by a
-    different task. */
+     * vPortCloseRunningThread() - which will be the case if the task associated
+     * with the thread originally deleted itself rather than being deleted by a
+     * different task. */
     if( pxThreadState->pvThread != NULL )
     {
         WaitForSingleObject( pvInterruptEventMutex, INFINITE );
 
         /* !!! This is not a nice way to terminate a thread, and will eventually
-        result in resources being depleted if tasks frequently delete other
-        tasks (rather than deleting themselves) as the task stacks will not be
-        freed. */
+         * result in resources being depleted if tasks frequently delete other
+         * tasks (rather than deleting themselves) as the task stacks will not be
+         * freed. */
         ulErrorCode = TerminateThread( pxThreadState->pvThread, 0 );
         configASSERT( ulErrorCode );
 
@@ -534,31 +539,32 @@ uint32_t ulErrorCode;
 }
 /*-----------------------------------------------------------*/
 
-void vPortCloseRunningThread( void *pvTaskToDelete, volatile BaseType_t *pxPendYield )
+void vPortCloseRunningThread( void * pvTaskToDelete,
+                              volatile BaseType_t * pxPendYield )
 {
-ThreadState_t *pxThreadState;
-void *pvThread;
-uint32_t ulErrorCode;
+    ThreadState_t * pxThreadState;
+    void * pvThread;
+    uint32_t ulErrorCode;
 
     /* Remove compiler warnings if configASSERT() is not defined. */
     ( void ) ulErrorCode;
 
     /* Find the handle of the thread being deleted. */
-    pxThreadState = ( ThreadState_t * ) ( *( size_t *) pvTaskToDelete );
+    pxThreadState = ( ThreadState_t * ) ( *( size_t * ) pvTaskToDelete );
     pvThread = pxThreadState->pvThread;
 
     /* Raise the Windows priority of the thread to ensure the FreeRTOS scheduler
-    does not run and swap it out before it is closed.  If that were to happen
-    the thread would never run again and effectively be a thread handle and
-    memory leak. */
+     * does not run and swap it out before it is closed.  If that were to happen
+     * the thread would never run again and effectively be a thread handle and
+     * memory leak. */
     SetThreadPriority( pvThread, portDELETE_SELF_THREAD_PRIORITY );
 
     /* This function will not return, therefore a yield is set as pending to
-    ensure a context switch occurs away from this thread on the next tick. */
+     * ensure a context switch occurs away from this thread on the next tick. */
     *pxPendYield = pdTRUE;
 
     /* Mark the thread associated with this task as invalid so
-    vPortDeleteThread() does not try to terminate it. */
+     * vPortDeleteThread() does not try to terminate it. */
     pxThreadState->pvThread = NULL;
 
     /* Close the thread. */
@@ -566,7 +572,7 @@ uint32_t ulErrorCode;
     configASSERT( ulErrorCode );
 
     /* This is called from a critical section, which must be exited before the
-    thread stops. */
+     * thread stops. */
     taskEXIT_CRITICAL();
     CloseHandle( pxThreadState->pvYieldEvent );
     ExitThread( 0 );
@@ -581,7 +587,7 @@ void vPortEndScheduler( void )
 
 void vPortGenerateSimulatedInterrupt( uint32_t ulInterruptNumber )
 {
-ThreadState_t *pxThreadState = ( ThreadState_t *) *( ( size_t * ) pxCurrentTCB );
+    ThreadState_t * pxThreadState = ( ThreadState_t * ) *( ( size_t * ) pxCurrentTCB );
 
     configASSERT( xPortRunning );
 
@@ -591,34 +597,36 @@ ThreadState_t *pxThreadState = ( ThreadState_t *) *( ( size_t * ) pxCurrentTCB )
         ulPendingInterrupts |= ( 1 << ulInterruptNumber );
 
         /* The simulated interrupt is now held pending, but don't actually
-        process it yet if this call is within a critical section.  It is
-        possible for this to be in a critical section as calls to wait for
-        mutexes are accumulative.  If in a critical section then the event
-        will get set when the critical section nesting count is wound back
-        down to zero. */
+         * process it yet if this call is within a critical section.  It is
+         * possible for this to be in a critical section as calls to wait for
+         * mutexes are accumulative.  If in a critical section then the event
+         * will get set when the critical section nesting count is wound back
+         * down to zero. */
         if( ulCriticalNesting == portNO_CRITICAL_NESTING )
         {
             SetEvent( pvInterruptEvent );
 
             /* Going to wait for an event - make sure the event is not already
-            signaled. */
+             * signaled. */
             ResetEvent( pxThreadState->pvYieldEvent );
         }
 
         ReleaseMutex( pvInterruptEventMutex );
+
         if( ulCriticalNesting == portNO_CRITICAL_NESTING )
         {
             /* An interrupt was pended so ensure to block to allow it to
-            execute.  In most cases the (simulated) interrupt will have
-            executed before the next line is reached - so this is just to make
-            sure. */
+             * execute.  In most cases the (simulated) interrupt will have
+             * executed before the next line is reached - so this is just to make
+             * sure. */
             WaitForSingleObject( pxThreadState->pvYieldEvent, INFINITE );
         }
     }
 }
 /*-----------------------------------------------------------*/
 
-void vPortSetInterruptHandler( uint32_t ulInterruptNumber, uint32_t (*pvHandler)( void ) )
+void vPortSetInterruptHandler( uint32_t ulInterruptNumber,
+                               uint32_t ( * pvHandler )( void ) )
 {
     if( ulInterruptNumber < portMAX_INTERRUPTS )
     {
@@ -641,7 +649,7 @@ void vPortEnterCritical( void )
     if( xPortRunning == pdTRUE )
     {
         /* The interrupt event mutex is held for the entire critical section,
-        effectively disabling (simulated) interrupts. */
+         * effectively disabling (simulated) interrupts. */
         WaitForSingleObject( pvInterruptEventMutex, INFINITE );
     }
 
@@ -651,10 +659,10 @@ void vPortEnterCritical( void )
 
 void vPortExitCritical( void )
 {
-int32_t lMutexNeedsReleasing;
+    int32_t lMutexNeedsReleasing;
 
     /* The interrupt event mutex should already be held by this thread as it was
-    obtained on entry to the critical section. */
+     * obtained on entry to the critical section. */
     lMutexNeedsReleasing = pdTRUE;
 
     if( ulCriticalNesting > portNO_CRITICAL_NESTING )
@@ -662,33 +670,34 @@ int32_t lMutexNeedsReleasing;
         ulCriticalNesting--;
 
         /* Don't need to wait for any pending interrupts to execute if the
-        critical section was exited from inside an interrupt. */
+         * critical section was exited from inside an interrupt. */
         if( ( ulCriticalNesting == portNO_CRITICAL_NESTING ) && ( xInsideInterrupt == pdFALSE ) )
         {
             /* Were any interrupts set to pending while interrupts were
-            (simulated) disabled? */
+             * (simulated) disabled? */
             if( ulPendingInterrupts != 0UL )
             {
-                ThreadState_t *pxThreadState = ( ThreadState_t *) *( ( size_t * ) pxCurrentTCB );
+                ThreadState_t * pxThreadState = ( ThreadState_t * ) *( ( size_t * ) pxCurrentTCB );
 
                 configASSERT( xPortRunning );
 
                 /* The interrupt won't actually executed until
-                pvInterruptEventMutex is released as it waits on both
-                pvInterruptEventMutex and pvInterruptEvent.
-                pvInterruptEvent is only set when the simulated
-                interrupt is pended if the interrupt is pended
-                from outside a critical section - hence it is set
-                here. */
+                 * pvInterruptEventMutex is released as it waits on both
+                 * pvInterruptEventMutex and pvInterruptEvent.
+                 * pvInterruptEvent is only set when the simulated
+                 * interrupt is pended if the interrupt is pended
+                 * from outside a critical section - hence it is set
+                 * here. */
                 SetEvent( pvInterruptEvent );
+
                 /* The calling task is going to wait for an event to ensure the
-                interrupt that is pending executes immediately after the
-                critical section is exited - so make sure the event is not
-                already signaled. */
+                 * interrupt that is pending executes immediately after the
+                 * critical section is exited - so make sure the event is not
+                 * already signaled. */
                 ResetEvent( pxThreadState->pvYieldEvent );
 
                 /* Mutex will be released now so the (simulated) interrupt can
-                execute, so does not require releasing on function exit. */
+                 * execute, so does not require releasing on function exit. */
                 lMutexNeedsReleasing = pdFALSE;
                 ReleaseMutex( pvInterruptEventMutex );
                 WaitForSingleObject( pxThreadState->pvYieldEvent, INFINITE );
diff --git a/portable/MSVC-MingW/portmacro.h b/portable/MSVC-MingW/portmacro.h
index 652792317..d15300772 100644
--- a/portable/MSVC-MingW/portmacro.h
+++ b/portable/MSVC-MingW/portmacro.h
@@ -33,107 +33,109 @@
 #include <winbase.h>
 
 /******************************************************************************
-    Defines
+*   Defines
 ******************************************************************************/
 /* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  size_t
-#define portPOINTER_SIZE_TYPE size_t
+#define portCHAR                 char
+#define portFLOAT                float
+#define portDOUBLE               double
+#define portLONG                 long
+#define portSHORT                short
+#define portSTACK_TYPE           size_t
+#define portPOINTER_SIZE_TYPE    size_t
 
-typedef portSTACK_TYPE StackType_t;
+typedef portSTACK_TYPE           StackType_t;
 
-#if defined( __x86_64__) || defined( _M_X64 )
-    #define portBASE_TYPE   long long
-    typedef long long BaseType_t;
-    typedef unsigned long long UBaseType_t;
+#if defined( __x86_64__ ) || defined( _M_X64 )
+    #define portBASE_TYPE    long long
+    typedef long long            BaseType_t;
+    typedef unsigned long long   UBaseType_t;
 #else
-    #define portBASE_TYPE   long
-    typedef long BaseType_t;
-    typedef unsigned long UBaseType_t;
+    #define portBASE_TYPE    long
+    typedef long                 BaseType_t;
+    typedef unsigned long        UBaseType_t;
 #endif
 
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t             TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+    typedef uint32_t             TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-    /* 32/64-bit tick type on a 32/64-bit architecture, so reads of the tick
-    count do not need to be guarded with a critical section. */
-    #define portTICK_TYPE_IS_ATOMIC 1
+/* 32/64-bit tick type on a 32/64-bit architecture, so reads of the tick
+ * count do not need to be guarded with a critical section. */
+    #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
 
 /* Hardware specifics. */
-#define portSTACK_GROWTH            ( -1 )
-#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portINLINE __inline
+#define portSTACK_GROWTH          ( -1 )
+#define portTICK_PERIOD_MS        ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portINLINE                __inline
 
-#if defined( __x86_64__) || defined( _M_X64 )
-    #define portBYTE_ALIGNMENT      8
+#if defined( __x86_64__ ) || defined( _M_X64 )
+    #define portBYTE_ALIGNMENT    8
 #else
-    #define portBYTE_ALIGNMENT      4
+    #define portBYTE_ALIGNMENT    4
 #endif
 
-#define portYIELD()                 vPortGenerateSimulatedInterrupt( portINTERRUPT_YIELD )
+#define portYIELD()    vPortGenerateSimulatedInterrupt( portINTERRUPT_YIELD )
 
 
 extern volatile BaseType_t xInsideInterrupt;
-#define portSOFTWARE_BARRIER() while( xInsideInterrupt != pdFALSE )
+#define portSOFTWARE_BARRIER()    while( xInsideInterrupt != pdFALSE )
 
 
 /* Simulated interrupts return pdFALSE if no context switch should be performed,
-or a non-zero number if a context switch should be performed. */
-#define portYIELD_FROM_ISR( x ) ( void ) x
-#define portEND_SWITCHING_ISR( x ) portYIELD_FROM_ISR( ( x ) )
+ * or a non-zero number if a context switch should be performed. */
+#define portYIELD_FROM_ISR( x )       ( void ) x
+#define portEND_SWITCHING_ISR( x )    portYIELD_FROM_ISR( ( x ) )
 
-void vPortCloseRunningThread( void *pvTaskToDelete, volatile BaseType_t *pxPendYield );
-void vPortDeleteThread( void *pvThreadToDelete );
-#define portCLEAN_UP_TCB( pxTCB )   vPortDeleteThread( pxTCB )
-#define portPRE_TASK_DELETE_HOOK( pvTaskToDelete, pxPendYield ) vPortCloseRunningThread( ( pvTaskToDelete ), ( pxPendYield ) )
-#define portDISABLE_INTERRUPTS() vPortEnterCritical()
-#define portENABLE_INTERRUPTS() vPortExitCritical()
+void vPortCloseRunningThread( void * pvTaskToDelete,
+                              volatile BaseType_t * pxPendYield );
+void vPortDeleteThread( void * pvThreadToDelete );
+#define portCLEAN_UP_TCB( pxTCB )                                  vPortDeleteThread( pxTCB )
+#define portPRE_TASK_DELETE_HOOK( pvTaskToDelete, pxPendYield )    vPortCloseRunningThread( ( pvTaskToDelete ), ( pxPendYield ) )
+#define portDISABLE_INTERRUPTS()                                   vPortEnterCritical()
+#define portENABLE_INTERRUPTS()                                    vPortExitCritical()
 
 /* Critical section handling. */
 void vPortEnterCritical( void );
 void vPortExitCritical( void );
 
-#define portENTER_CRITICAL()        vPortEnterCritical()
-#define portEXIT_CRITICAL()         vPortExitCritical()
+#define portENTER_CRITICAL()    vPortEnterCritical()
+#define portEXIT_CRITICAL()     vPortExitCritical()
 
 #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-    #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+    #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
 #endif
 
 #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
 
-    /* Check the configuration. */
-    #if( configMAX_PRIORITIES > 32 )
+/* Check the configuration. */
+    #if ( configMAX_PRIORITIES > 32 )
         #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
     #endif
 
-    /* Store/clear the ready priorities in a bit map. */
-    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+/* Store/clear the ready priorities in a bit map. */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 
 
-    /*-----------------------------------------------------------*/
+/*-----------------------------------------------------------*/
 
     #ifdef __GNUC__
-        #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    \
-            __asm volatile( "bsr %1, %0\n\t"                                    \
-                            :"=r"(uxTopPriority) : "rm"(uxReadyPriorities) : "cc" )
+        #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) \
+    __asm volatile ( "bsr %1, %0\n\t"                                        \
+                     : "=r" ( uxTopPriority ) : "rm" ( uxReadyPriorities ) : "cc" )
     #else
-        /* BitScanReverse returns the bit position of the most significant '1'
-        in the word. */
-        #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) _BitScanReverse( ( DWORD * ) &( uxTopPriority ), ( uxReadyPriorities ) )
+
+/* BitScanReverse returns the bit position of the most significant '1'
+ * in the word. */
+        #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    _BitScanReverse( ( DWORD * ) &( uxTopPriority ), ( uxReadyPriorities ) )
     #endif /* __GNUC__ */
 
 #endif /* taskRECORD_READY_PRIORITY */
@@ -144,17 +146,17 @@ void vPortExitCritical( void );
 
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
-#define portINTERRUPT_YIELD             ( 0UL )
-#define portINTERRUPT_TICK              ( 1UL )
+#define portINTERRUPT_YIELD    ( 0UL )
+#define portINTERRUPT_TICK     ( 1UL )
 
 /*
  * Raise a simulated interrupt represented by the bit mask in ulInterruptMask.
  * Each bit can be used to represent an individual interrupt - with the first
  * two bits being used for the Yield and Tick interrupts respectively.
-*/
+ */
 void vPortGenerateSimulatedInterrupt( uint32_t ulInterruptNumber );
 
 /*
@@ -166,6 +168,7 @@ void vPortGenerateSimulatedInterrupt( uint32_t ulInterruptNumber );
  * Interrupt handler functions must return a non-zero value if executing the
  * handler resulted in a task switch being required.
  */
-void vPortSetInterruptHandler( uint32_t ulInterruptNumber, uint32_t (*pvHandler)( void ) );
+void vPortSetInterruptHandler( uint32_t ulInterruptNumber,
+                               uint32_t ( * pvHandler )( void ) );
 
-#endif
+#endif /* ifndef PORTMACRO_H */
diff --git a/portable/MemMang/heap_5.c b/portable/MemMang/heap_5.c
index 5ced44e65..127b28f5e 100644
--- a/portable/MemMang/heap_5.c
+++ b/portable/MemMang/heap_5.c
@@ -28,7 +28,7 @@
 
 /*
  * A sample implementation of pvPortMalloc() that allows the heap to be defined
- * across multiple non-contigous blocks and combines (coalescences) adjacent
+ * across multiple non-contiguous blocks and combines (coalescences) adjacent
  * memory blocks as they are freed.
  *
  * See heap_1.c, heap_2.c, heap_3.c and heap_4.c for alternative
diff --git a/portable/MikroC/ARM_CM4F/port.c b/portable/MikroC/ARM_CM4F/port.c
old mode 100755
new mode 100644
index 91c924a05..a1c3f4e61
--- a/portable/MikroC/ARM_CM4F/port.c
+++ b/portable/MikroC/ARM_CM4F/port.c
@@ -345,22 +345,22 @@ BaseType_t xPortStartScheduler( void )
         if( ulImplementedPrioBits == 8 )
         {
             /* When the hardware implements 8 priority bits, there is no way for
-            * the software to configure PRIGROUP to not have sub-priorities. As
-            * a result, the least significant bit is always used for sub-priority
-            * and there are 128 preemption priorities and 2 sub-priorities.
-            *
-            * This may cause some confusion in some cases - for example, if
-            * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
-            * priority interrupts will be masked in Critical Sections as those
-            * are at the same preemption priority. This may appear confusing as
-            * 4 is higher (numerically lower) priority than
-            * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
-            * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
-            * to 4, this confusion does not happen and the behaviour remains the same.
-            *
-            * The following assert ensures that the sub-priority bit in the
-            * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
-            * confusion. */
+             * the software to configure PRIGROUP to not have sub-priorities. As
+             * a result, the least significant bit is always used for sub-priority
+             * and there are 128 preemption priorities and 2 sub-priorities.
+             *
+             * This may cause some confusion in some cases - for example, if
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
+             * priority interrupts will be masked in Critical Sections as those
+             * are at the same preemption priority. This may appear confusing as
+             * 4 is higher (numerically lower) priority than
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
+             * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
+             * to 4, this confusion does not happen and the behaviour remains the same.
+             *
+             * The following assert ensures that the sub-priority bit in the
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
+             * confusion. */
             configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
             ulMaxPRIGROUPValue = 0;
         }
diff --git a/portable/MikroC/ARM_CM4F/portmacro.h b/portable/MikroC/ARM_CM4F/portmacro.h
index b67a0a9d6..c7b4aae0f 100644
--- a/portable/MikroC/ARM_CM4F/portmacro.h
+++ b/portable/MikroC/ARM_CM4F/portmacro.h
@@ -27,7 +27,7 @@
  */
 
 #ifndef PORTMACRO_H
-    #define PORTMACRO_H
+#define PORTMACRO_H
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
@@ -48,143 +48,147 @@
 /* The compiler needs to be told functions that are only referenced by pointer
  * are to be included in the build.  NOTE:  Omitting these lines will result in a
  * run-time crash, not a linker error! */
-    #pragma funcall vTaskStartScheduler prvIdleTask
-    #pragma funcall xTimerCreateTimerTask prvTimerTask
+#pragma funcall vTaskStartScheduler prvIdleTask
+#pragma funcall xTimerCreateTimerTask prvTimerTask
 
 /* Type definitions. */
-    #define portCHAR          char
-    #define portFLOAT         float
-    #define portDOUBLE        double
-    #define portLONG          long
-    #define portSHORT         short
-    #define portSTACK_TYPE    uint32_t
-    #define portBASE_TYPE     long
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-    typedef portSTACK_TYPE   StackType_t;
-    typedef long             BaseType_t;
-    typedef unsigned long    UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
-    #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-        typedef uint16_t     TickType_t;
-        #define portMAX_DELAY              ( TickType_t ) 0xffff
-    #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-        typedef uint32_t     TickType_t;
-        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
  * not need to be guarded with a critical section. */
-        #define portTICK_TYPE_IS_ATOMIC    1
-    #else
-        #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
-    #endif
+    #define portTICK_TYPE_IS_ATOMIC    1
+#else
+    #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+#endif
 /*-----------------------------------------------------------*/
 
 /* Architecture specifics. */
-    #define portSTACK_GROWTH      ( -1 )
-    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-    #define portBYTE_ALIGNMENT    8
+#define portSTACK_GROWTH      ( -1 )
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT    8
 /*-----------------------------------------------------------*/
 
 /* Scheduler utilities. */
-    #define portYIELD()                                 \
+#define portYIELD()                                     \
     {                                                   \
         /* Set a PendSV to request a context switch. */ \
         portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
                                                         \
         /* Barriers are normally not required but do ensure the code is completely \
          * within the specified behaviour for the architecture. */ \
-        __asm{ dsb };                                              \
-        __asm{ isb };                                              \
+        __asm { dsb };                                             \
+        __asm { isb };                                             \
     }
 
-    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
-    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-    #define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 )
-    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+#define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired != pdFALSE ) portYIELD( ); } while( 0 )
+#define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
 /* Critical section management. */
-    extern void vPortEnterCritical( void );
-    extern void vPortExitCritical( void );
-    #define portDISABLE_INTERRUPTS()                  CPU_REG_SET( CPU_BASEPRI, configMAX_SYSCALL_INTERRUPT_PRIORITY ); __asm{ dsb }; __asm{ isb }
-    #define portENABLE_INTERRUPTS()                   CPU_REG_SET( CPU_BASEPRI, 0 );
-    #define portENTER_CRITICAL()                      vPortEnterCritical()
-    #define portEXIT_CRITICAL()                       vPortExitCritical()
-    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulPortRaiseBASEPRI()
-    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    CPU_REG_SET( CPU_BASEPRI, x ); /* Barrier instructions not used as this is only used to lower the basepri. */
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+#define portDISABLE_INTERRUPTS()                  CPU_REG_SET( CPU_BASEPRI, configMAX_SYSCALL_INTERRUPT_PRIORITY ); __asm { dsb }; __asm { isb }
+#define portENABLE_INTERRUPTS()                   CPU_REG_SET( CPU_BASEPRI, 0 );
+#define portENTER_CRITICAL()                      vPortEnterCritical()
+#define portEXIT_CRITICAL()                       vPortExitCritical()
+#define portSET_INTERRUPT_MASK_FROM_ISR()         ulPortRaiseBASEPRI()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    CPU_REG_SET( CPU_BASEPRI, x );     /* Barrier instructions not used as this is only used to lower the basepri. */
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site.  These are
  * not necessary for to use this port.  They are defined so the common demo files
  * (which build with all the ports) will build. */
-    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
-    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 /*-----------------------------------------------------------*/
 
 /* Tickless idle/low power functionality. */
-    #ifndef portSUPPRESS_TICKS_AND_SLEEP
-        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
-        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
-    #endif
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+    extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+    #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
 /*-----------------------------------------------------------*/
 
 /* Architecture specific optimisations. */
-    #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
-    #endif
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+    #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
+#endif
 
-    #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
 
 /* Generic helper function. */
-        __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
-        {
-            uint8_t ucReturn;
+    __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
+    {
+        uint8_t ucReturn;
 
-            __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) );
+        __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) );
 
-            return ucReturn;
-        }
+        return ucReturn;
+    }
 
 /* Check the configuration. */
-        #if ( configMAX_PRIORITIES > 32 )
-            #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
-        #endif
-
-/* Store/clear the ready priorities in a bit map. */
-        #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-        #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-
-/*-----------------------------------------------------------*/
-
-        #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
-
-    #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-
-/*-----------------------------------------------------------*/
-
-    #ifdef configASSERT
-        void vPortValidateInterruptPriority( void );
-        #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
+    #if ( configMAX_PRIORITIES > 32 )
+        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
     #endif
 
-/* portNOP() is not required by this port. */
-    #define portNOP()
-
-    BaseType_t xPortIsInsideInterrupt( void );
+/* Store/clear the ready priorities in a bit map. */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 
 /*-----------------------------------------------------------*/
 
-    static inline uint32_t ulPortRaiseBASEPRI( void )
-    {
-        uint32_t ulOriginalBASEPRI;
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
 
-        ulOriginalBASEPRI = CPU_REG_GET( CPU_BASEPRI );
-        CPU_REG_SET( CPU_BASEPRI, configMAX_SYSCALL_INTERRUPT_PRIORITY );
-        __asm{ dsb };
-        __asm{ isb };
-        return ulOriginalBASEPRI;
-    }
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/*-----------------------------------------------------------*/
+
+#ifdef configASSERT
+    void vPortValidateInterruptPriority( void );
+    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
+#endif
+
+/* portNOP() is not required by this port. */
+#define portNOP()
+
+BaseType_t xPortIsInsideInterrupt( void );
+
+/*-----------------------------------------------------------*/
+
+static inline uint32_t ulPortRaiseBASEPRI( void )
+{
+    uint32_t ulOriginalBASEPRI;
+
+    ulOriginalBASEPRI = CPU_REG_GET( CPU_BASEPRI );
+    CPU_REG_SET( CPU_BASEPRI, configMAX_SYSCALL_INTERRUPT_PRIORITY );
+    __asm {
+        dsb
+    };
+    __asm {
+        isb
+    };
+    return ulOriginalBASEPRI;
+}
 /*-----------------------------------------------------------*/
 
 /* *INDENT-OFF* */
diff --git a/portable/Paradigm/Tern_EE/large_untested/port.c b/portable/Paradigm/Tern_EE/large_untested/port.c
index 4ecffe01a..fdb275f2b 100644
--- a/portable/Paradigm/Tern_EE/large_untested/port.c
+++ b/portable/Paradigm/Tern_EE/large_untested/port.c
@@ -28,9 +28,9 @@
 
 
 /*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the Tern EE 186
- * port.
- *----------------------------------------------------------*/
+* Implementation of functions defined in portable.h for the Tern EE 186
+* port.
+*----------------------------------------------------------*/
 
 /* Library includes. */
 #include <embedded.h>
@@ -42,27 +42,29 @@
 #include "portasm.h"
 
 /* The timer increments every four clocks, hence the divide by 4. */
-#define portTIMER_COMPARE ( uint16_t ) ( ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) / ( uint32_t ) 4 )
+#define portTIMER_COMPARE                 ( uint16_t ) ( ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) / ( uint32_t ) 4 )
 
 /* From the RDC data sheet. */
-#define portENABLE_TIMER_AND_INTERRUPT ( uint16_t ) 0xe001
+#define portENABLE_TIMER_AND_INTERRUPT    ( uint16_t ) 0xe001
 
 /* Interrupt control. */
-#define portEIO_REGISTER 0xff22
-#define portCLEAR_INTERRUPT 0x0008
+#define portEIO_REGISTER                  0xff22
+#define portCLEAR_INTERRUPT               0x0008
 
 /* Setup the hardware to generate the required tick frequency. */
 static void prvSetupTimerInterrupt( void );
 
 /* The ISR used depends on whether the preemptive or cooperative scheduler
-is being used. */
-#if( configUSE_PREEMPTION == 1 )
-    /* Tick service routine used by the scheduler when preemptive scheduling is
-    being used. */
+ * is being used. */
+#if ( configUSE_PREEMPTION == 1 )
+
+/* Tick service routine used by the scheduler when preemptive scheduling is
+ * being used. */
     static void __interrupt __far prvPreemptiveTick( void );
 #else
-    /* Tick service routine used by the scheduler when cooperative scheduling is
-    being used. */
+
+/* Tick service routine used by the scheduler when cooperative scheduling is
+ * being used. */
     static void __interrupt __far prvNonPreemptiveTick( void );
 #endif
 
@@ -70,18 +72,20 @@ is being used. */
 static void __interrupt __far prvYieldProcessor( void );
 
 /* The timer initialisation functions leave interrupts enabled,
-which is not what we want.  This ISR is installed temporarily in case
-the timer fires before we get a change to disable interrupts again. */
+ * which is not what we want.  This ISR is installed temporarily in case
+ * the timer fires before we get a change to disable interrupts again. */
 static void __interrupt __far prvDummyISR( void );
 
 /*-----------------------------------------------------------*/
 /* See header file for description. */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
-StackType_t DS_Reg = 0;
+    StackType_t DS_Reg = 0;
 
     /* Place a few bytes of known values on the bottom of the stack.
-    This is just useful for debugging. */
+     * This is just useful for debugging. */
 
     *pxTopOfStack = 0x1111;
     pxTopOfStack--;
@@ -91,8 +95,8 @@ StackType_t DS_Reg = 0;
     pxTopOfStack--;
 
     /* We are going to start the scheduler using a return from interrupt
-    instruction to load the program counter, so first there would be the
-    function call with parameters preamble. */
+     * instruction to load the program counter, so first there would be the
+     * function call with parameters preamble. */
 
     *pxTopOfStack = FP_SEG( pvParameters );
     pxTopOfStack--;
@@ -112,8 +116,8 @@ StackType_t DS_Reg = 0;
     pxTopOfStack--;
 
     /* The remaining registers would be pushed on the stack by our context
-    switch function.  These are loaded with values simply to make debugging
-    easier. */
+     * switch function.  These are loaded with values simply to make debugging
+     * easier. */
     *pxTopOfStack = ( StackType_t ) 0xAAAA; /* AX */
     pxTopOfStack--;
     *pxTopOfStack = ( StackType_t ) 0xBBBB; /* BX */
@@ -126,9 +130,11 @@ StackType_t DS_Reg = 0;
     pxTopOfStack--;
 
     /* We need the true data segment. */
-    __asm{  MOV DS_Reg, DS };
+    __asm {
+        MOV DS_Reg, DS
+    };
 
-    *pxTopOfStack = DS_Reg;                     /* DS */
+    *pxTopOfStack = DS_Reg;                 /* DS */
     pxTopOfStack--;
     *pxTopOfStack = ( StackType_t ) 0x0123; /* SI */
     pxTopOfStack--;
@@ -145,7 +151,7 @@ BaseType_t xPortStartScheduler( void )
     /* This is called with interrupts already disabled. */
 
     /* Put our manual switch (yield) function on a known
-    vector. */
+     * vector. */
     setvect( portSWITCH_INT_NUMBER, prvYieldProcessor );
 
     /* Setup the tick interrupt. */
@@ -162,15 +168,15 @@ BaseType_t xPortStartScheduler( void )
 static void __interrupt __far prvDummyISR( void )
 {
     /* The timer initialisation functions leave interrupts enabled,
-    which is not what we want.  This ISR is installed temporarily in case
-    the timer fires before we get a change to disable interrupts again. */
+     * which is not what we want.  This ISR is installed temporarily in case
+     * the timer fires before we get a change to disable interrupts again. */
     outport( portEIO_REGISTER, portCLEAR_INTERRUPT );
 }
 /*-----------------------------------------------------------*/
 
 /* The ISR used depends on whether the preemptive or cooperative scheduler
-is being used. */
-#if( configUSE_PREEMPTION == 1 )
+ * is being used. */
+#if ( configUSE_PREEMPTION == 1 )
     static void __interrupt __far prvPreemptiveTick( void )
     {
         /* Get the scheduler to update the task states following the tick. */
@@ -183,17 +189,17 @@ is being used. */
         /* Reset interrupt. */
         outport( portEIO_REGISTER, portCLEAR_INTERRUPT );
     }
-#else
+#else /* if ( configUSE_PREEMPTION == 1 ) */
     static void __interrupt __far prvNonPreemptiveTick( void )
     {
         /* Same as preemptive tick, but the cooperative scheduler is being used
-        so we don't have to switch in the context of the next task. */
+         * so we don't have to switch in the context of the next task. */
         xTaskIncrementTick();
 
         /* Reset interrupt. */
         outport( portEIO_REGISTER, portCLEAR_INTERRUPT );
     }
-#endif
+#endif /* if ( configUSE_PREEMPTION == 1 ) */
 /*-----------------------------------------------------------*/
 
 static void __interrupt __far prvYieldProcessor( void )
@@ -211,23 +217,25 @@ void vPortEndScheduler( void )
 
 static void prvSetupTimerInterrupt( void )
 {
-const uint16_t usTimerACompare = portTIMER_COMPARE, usTimerAMode = portENABLE_TIMER_AND_INTERRUPT;
-const uint16_t usT2_IRQ = 0x13;
+    const uint16_t usTimerACompare = portTIMER_COMPARE, usTimerAMode = portENABLE_TIMER_AND_INTERRUPT;
+    const uint16_t usT2_IRQ = 0x13;
 
     /* Configure the timer, the dummy handler is used here as the init
-    function leaves interrupts enabled. */
+     * function leaves interrupts enabled. */
     t2_init( usTimerAMode, usTimerACompare, prvDummyISR );
 
     /* Disable interrupts again before installing the real handlers. */
     portDISABLE_INTERRUPTS();
 
-    #if( configUSE_PREEMPTION == 1 )
+    #if ( configUSE_PREEMPTION == 1 )
+
         /* Tick service routine used by the scheduler when preemptive scheduling is
-        being used. */
+         * being used. */
         setvect( usT2_IRQ, prvPreemptiveTick );
     #else
+
         /* Tick service routine used by the scheduler when cooperative scheduling is
-        being used. */
+         * being used. */
         setvect( usT2_IRQ, prvNonPreemptiveTick );
     #endif
 }
diff --git a/portable/Paradigm/Tern_EE/large_untested/portasm.h b/portable/Paradigm/Tern_EE/large_untested/portasm.h
index c3c7456a3..e0321a8b0 100644
--- a/portable/Paradigm/Tern_EE/large_untested/portasm.h
+++ b/portable/Paradigm/Tern_EE/large_untested/portasm.h
@@ -44,32 +44,32 @@ void portSWITCH_CONTEXT( void );
  */
 void portFIRST_CONTEXT( void );
 
-#define portSWITCH_CONTEXT()                                         \
-                        asm { mov   ax, seg pxCurrentTCB        } \
-                            asm { mov   ds, ax                      }  \
-                            asm { les   bx, pxCurrentTCB            }   /* Save the stack pointer into the TCB. */    \
-                            asm { mov   es:0x2[ bx ], ss            }   \
-                            asm { mov   es:[ bx ], sp               }   \
-                            asm { call  far ptr vTaskSwitchContext  }   /* Perform the switch. */   \
-                            asm { mov   ax, seg pxCurrentTCB        }   /* Restore the stack pointer from the TCB. */  \
-                            asm { mov   ds, ax                      }   \
-                            asm { les   bx, dword ptr pxCurrentTCB  }   \
-                            asm { mov   ss, es:[ bx + 2 ]           }      \
-                            asm { mov   sp, es:[ bx ]               }
+#define portSWITCH_CONTEXT()                                                              \
+    asm { mov ax, seg pxCurrentTCB }                                                      \
+    asm { mov ds, ax }                                                                    \
+    asm { les bx, pxCurrentTCB } /* Save the stack pointer into the TCB. */               \
+    asm { mov es : 0x2[ bx ], ss }                                                        \
+    asm { mov es:[ bx ], sp }                                                                      \
+    asm { call far ptr vTaskSwitchContext } /* Perform the switch. */                     \
+    asm { mov ax, seg pxCurrentTCB }        /* Restore the stack pointer from the TCB. */ \
+    asm { mov ds, ax }                                                                    \
+    asm { les bx, dword ptr pxCurrentTCB }                                                \
+    asm { mov ss, es:[ bx + 2 ] }                                                                      \
+    asm { mov sp, es:[ bx ] }
 
-#define portFIRST_CONTEXT()                                             \
-                            asm { mov   ax, seg pxCurrentTCB        }   \
-                            asm { mov   ds, ax                      }   \
-                            asm { les   bx, dword ptr pxCurrentTCB  }   \
-                            asm { mov   ss, es:[ bx + 2 ]           }   \
-                            asm { mov   sp, es:[ bx ]               }   \
-                            asm { pop   bp                          }   \
-                            asm { pop   di                          }   \
-                            asm { pop   si                          }   \
-                            asm { pop   ds                          }   \
-                            asm { pop   es                          }   \
-                            asm { pop   dx                          }   \
-                            asm { pop   cx                          }   \
-                            asm { pop   bx                          }   \
-                            asm { pop   ax                          }   \
-                            asm { iret                              }
+#define portFIRST_CONTEXT()                \
+    asm { mov ax, seg pxCurrentTCB }       \
+    asm { mov ds, ax }                     \
+    asm { les bx, dword ptr pxCurrentTCB } \
+    asm { mov ss, es:[ bx + 2 ] }                       \
+    asm { mov sp, es:[ bx ] }                           \
+    asm { pop bp }                         \
+    asm { pop di }                         \
+    asm { pop si }                         \
+    asm { pop ds }                         \
+    asm { pop es }                         \
+    asm { pop dx }                         \
+    asm { pop cx }                         \
+    asm { pop bx }                         \
+    asm { pop ax }                         \
+    asm { iret }
diff --git a/portable/Paradigm/Tern_EE/large_untested/portmacro.h b/portable/Paradigm/Tern_EE/large_untested/portmacro.h
index 292c9e260..2027213a1 100644
--- a/portable/Paradigm/Tern_EE/large_untested/portmacro.h
+++ b/portable/Paradigm/Tern_EE/large_untested/portmacro.h
@@ -46,24 +46,24 @@
  */
 
 /* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      long
-#define portLONG        long
-#define portSHORT       int
-#define portSTACK_TYPE  uint16_t
-#define portBASE_TYPE   short
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        long
+#define portLONG          long
+#define portSHORT         int
+#define portSTACK_TYPE    uint16_t
+#define portBASE_TYPE     short
 
-typedef portSTACK_TYPE StackType_t;
-typedef short BaseType_t;
-typedef unsigned short UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef short            BaseType_t;
+typedef unsigned short   UBaseType_t;
 
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
-#elif ( configTICK_TYPE_WIDTH_IN_BITS  == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t             TickType_t;
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+    typedef uint32_t     TickType_t;
     #define portMAX_DELAY    ( TickType_t ) 0xffffffffUL
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -71,36 +71,37 @@ typedef unsigned short UBaseType_t;
 /*-----------------------------------------------------------*/
 
 /* Critical section handling. */
-#define portENTER_CRITICAL()            __asm{ pushf }  \
-                                        __asm{ cli   }  \
+#define portENTER_CRITICAL() \
+    __asm { pushf }          \
+    __asm { cli }            \
 
-#define portEXIT_CRITICAL()             __asm{ popf }
+#define portEXIT_CRITICAL()         __asm { popf }
 
-#define portDISABLE_INTERRUPTS()        __asm{ cli }
+#define portDISABLE_INTERRUPTS()    __asm { cli }
 
-#define portENABLE_INTERRUPTS()         __asm{ sti }
+#define portENABLE_INTERRUPTS()     __asm { sti }
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portNOP()                       __asm{ nop }
-#define portSTACK_GROWTH                ( -1 )
-#define portSWITCH_INT_NUMBER           0x80
-#define portYIELD()                     __asm{ int portSWITCH_INT_NUMBER }
-#define portTICK_PERIOD_MS              ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT              2
-#define portINITIAL_SW                  ( ( portSTACK_TYPE ) 0x0202 )   /* Start the tasks with interrupts enabled. */
+#define portNOP()      __asm { nop }
+#define portSTACK_GROWTH         ( -1 )
+#define portSWITCH_INT_NUMBER    0x80
+#define portYIELD()    __asm { int portSWITCH_INT_NUMBER }
+#define portTICK_PERIOD_MS       ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT       2
+#define portINITIAL_SW           ( ( portSTACK_TYPE ) 0x0202 )          /* Start the tasks with interrupts enabled. */
 /*-----------------------------------------------------------*/
 
 /* Compiler specifics. */
-#define portINPUT_BYTE( xAddr )             inp( xAddr )
-#define portOUTPUT_BYTE( xAddr, ucValue )   outp( xAddr, ucValue )
-#define portINPUT_WORD( xAddr )             inpw( xAddr )
-#define portOUTPUT_WORD( xAddr, usValue )   outpw( xAddr, usValue )
+#define portINPUT_BYTE( xAddr )              inp( xAddr )
+#define portOUTPUT_BYTE( xAddr, ucValue )    outp( xAddr, ucValue )
+#define portINPUT_WORD( xAddr )              inpw( xAddr )
+#define portOUTPUT_WORD( xAddr, usValue )    outpw( xAddr, usValue )
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters )
-#define portTASK_FUNCTION( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters )
+#define portTASK_FUNCTION_PROTO( vTaskFunction, vParameters )    void vTaskFunction( void * pvParameters )
+#define portTASK_FUNCTION( vTaskFunction, vParameters )          void vTaskFunction( void * pvParameters )
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/Paradigm/Tern_EE/small/port.c b/portable/Paradigm/Tern_EE/small/port.c
index 2a1c0d962..6d27ba991 100644
--- a/portable/Paradigm/Tern_EE/small/port.c
+++ b/portable/Paradigm/Tern_EE/small/port.c
@@ -28,9 +28,9 @@
 
 
 /*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the Tern EE 186
- * port.
- *----------------------------------------------------------*/
+* Implementation of functions defined in portable.h for the Tern EE 186
+* port.
+*----------------------------------------------------------*/
 
 /* Library includes. */
 #include <embedded.h>
@@ -42,29 +42,31 @@
 #include "portasm.h"
 
 /* The timer increments every four clocks, hence the divide by 4. */
-#define portPRESCALE_VALUE ( 16 )
-#define portTIMER_COMPARE ( configCPU_CLOCK_HZ  / ( configTICK_RATE_HZ * 4UL ) )
+#define portPRESCALE_VALUE                ( 16 )
+#define portTIMER_COMPARE                 ( configCPU_CLOCK_HZ / ( configTICK_RATE_HZ * 4UL ) )
 
 /* From the RDC data sheet. */
-#define portENABLE_TIMER_AND_INTERRUPT  ( uint16_t ) 0xe00b
-#define portENABLE_TIMER                ( uint16_t ) 0xC001
+#define portENABLE_TIMER_AND_INTERRUPT    ( uint16_t ) 0xe00b
+#define portENABLE_TIMER                  ( uint16_t ) 0xC001
 
 /* Interrupt control. */
-#define portEIO_REGISTER 0xff22
-#define portCLEAR_INTERRUPT 0x0008
+#define portEIO_REGISTER                  0xff22
+#define portCLEAR_INTERRUPT               0x0008
 
 /* Setup the hardware to generate the required tick frequency. */
 static void prvSetupTimerInterrupt( void );
 
 /* The ISR used depends on whether the preemptive or cooperative scheduler
-is being used. */
-#if( configUSE_PREEMPTION == 1 )
-    /* Tick service routine used by the scheduler when preemptive scheduling is
-    being used. */
+ * is being used. */
+#if ( configUSE_PREEMPTION == 1 )
+
+/* Tick service routine used by the scheduler when preemptive scheduling is
+ * being used. */
     static void __interrupt __far prvPreemptiveTick( void );
 #else
-    /* Tick service routine used by the scheduler when cooperative scheduling is
-    being used. */
+
+/* Tick service routine used by the scheduler when cooperative scheduling is
+ * being used. */
     static void __interrupt __far prvNonPreemptiveTick( void );
 #endif
 
@@ -73,15 +75,19 @@ static void __interrupt __far prvYieldProcessor( void );
 
 /*-----------------------------------------------------------*/
 /* See header file for description. */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
-StackType_t DS_Reg = 0;
+    StackType_t DS_Reg = 0;
 
     /* We need the true data segment. */
-    __asm{  MOV DS_Reg, DS };
+    __asm {
+        MOV DS_Reg, DS
+    };
 
     /* Place a few bytes of known values on the bottom of the stack.
-    This is just useful for debugging. */
+     * This is just useful for debugging. */
 
     *pxTopOfStack = 0x1111;
     pxTopOfStack--;
@@ -91,8 +97,8 @@ StackType_t DS_Reg = 0;
     pxTopOfStack--;
 
     /* We are going to start the scheduler using a return from interrupt
-    instruction to load the program counter, so first there would be the
-    function call with parameters preamble. */
+     * instruction to load the program counter, so first there would be the
+     * function call with parameters preamble. */
 
     *pxTopOfStack = FP_OFF( pvParameters );
     pxTopOfStack--;
@@ -108,8 +114,8 @@ StackType_t DS_Reg = 0;
     pxTopOfStack--;
 
     /* The remaining registers would be pushed on the stack by our context
-    switch function.  These are loaded with values simply to make debugging
-    easier. */
+     * switch function.  These are loaded with values simply to make debugging
+     * easier. */
     *pxTopOfStack = ( StackType_t ) 0xAAAA; /* AX */
     pxTopOfStack--;
     *pxTopOfStack = ( StackType_t ) 0xBBBB; /* BX */
@@ -121,7 +127,7 @@ StackType_t DS_Reg = 0;
     *pxTopOfStack = ( StackType_t ) 0xEEEE; /* ES */
     pxTopOfStack--;
 
-    *pxTopOfStack = DS_Reg;                     /* DS */
+    *pxTopOfStack = DS_Reg;                 /* DS */
     pxTopOfStack--;
     *pxTopOfStack = ( StackType_t ) 0x0123; /* SI */
     pxTopOfStack--;
@@ -138,7 +144,7 @@ BaseType_t xPortStartScheduler( void )
     /* This is called with interrupts already disabled. */
 
     /* Put our manual switch (yield) function on a known
-    vector. */
+     * vector. */
     setvect( portSWITCH_INT_NUMBER, prvYieldProcessor );
 
     /* Setup the tick interrupt. */
@@ -153,8 +159,8 @@ BaseType_t xPortStartScheduler( void )
 /*-----------------------------------------------------------*/
 
 /* The ISR used depends on whether the preemptive or cooperative scheduler
-is being used. */
-#if( configUSE_PREEMPTION == 1 )
+ * is being used. */
+#if ( configUSE_PREEMPTION == 1 )
     static void __interrupt __far prvPreemptiveTick( void )
     {
         /* Get the scheduler to update the task states following the tick. */
@@ -167,17 +173,17 @@ is being used. */
         /* Reset interrupt. */
         outport( portEIO_REGISTER, portCLEAR_INTERRUPT );
     }
-#else
+#else /* if ( configUSE_PREEMPTION == 1 ) */
     static void __interrupt __far prvNonPreemptiveTick( void )
     {
         /* Same as preemptive tick, but the cooperative scheduler is being used
-        so we don't have to switch in the context of the next task. */
+         * so we don't have to switch in the context of the next task. */
         xTaskIncrementTick();
 
         /* Reset interrupt. */
         outport( portEIO_REGISTER, portCLEAR_INTERRUPT );
     }
-#endif
+#endif /* if ( configUSE_PREEMPTION == 1 ) */
 /*-----------------------------------------------------------*/
 
 static void __interrupt __far prvYieldProcessor( void )
@@ -195,19 +201,21 @@ void vPortEndScheduler( void )
 
 static void prvSetupTimerInterrupt( void )
 {
-const uint32_t ulCompareValue = portTIMER_COMPARE;
-uint16_t usTimerCompare;
+    const uint32_t ulCompareValue = portTIMER_COMPARE;
+    uint16_t usTimerCompare;
 
     usTimerCompare = ( uint16_t ) ( ulCompareValue >> 4 );
     t2_init( portENABLE_TIMER, portPRESCALE_VALUE, NULL );
 
-    #if( configUSE_PREEMPTION == 1 )
+    #if ( configUSE_PREEMPTION == 1 )
+
         /* Tick service routine used by the scheduler when preemptive scheduling is
-        being used. */
+         * being used. */
         t1_init( portENABLE_TIMER_AND_INTERRUPT, usTimerCompare, usTimerCompare, prvPreemptiveTick );
     #else
+
         /* Tick service routine used by the scheduler when cooperative scheduling is
-        being used. */
+         * being used. */
         t1_init( portENABLE_TIMER_AND_INTERRUPT, usTimerCompare, usTimerCompare, prvNonPreemptiveTick );
     #endif
 }
diff --git a/portable/Paradigm/Tern_EE/small/portasm.h b/portable/Paradigm/Tern_EE/small/portasm.h
index 930da20b0..2acba2443 100644
--- a/portable/Paradigm/Tern_EE/small/portasm.h
+++ b/portable/Paradigm/Tern_EE/small/portasm.h
@@ -47,26 +47,26 @@ void portEND_SWITCHING_ISR( void );
  */
 void portFIRST_CONTEXT( void );
 
-#define portEND_SWITCHING_ISR()                                         \
-                            asm { mov   bx, [pxCurrentTCB]          }   \
-                            asm { mov   word ptr [bx], sp           }   \
-                            asm { call  far ptr vTaskSwitchContext  }   \
-                            asm { mov   bx, [pxCurrentTCB]          }   \
-                            asm { mov   sp, [bx]                    }
+#define portEND_SWITCHING_ISR()             \
+    asm { mov bx, [ pxCurrentTCB ] }        \
+    asm { mov word ptr[ bx ], sp }          \
+    asm { call far ptr vTaskSwitchContext } \
+    asm { mov bx, [ pxCurrentTCB ] }        \
+    asm { mov sp, [ bx ] }
 
-#define portFIRST_CONTEXT()                                         \
-                            asm { mov   bx, [pxCurrentTCB]          }   \
-                            asm { mov   sp, [bx]                    }   \
-                            asm { pop   bp                          }   \
-                            asm { pop   di                          }   \
-                            asm { pop   si                          }   \
-                            asm { pop   ds                          }   \
-                            asm { pop   es                          }   \
-                            asm { pop   dx                          }   \
-                            asm { pop   cx                          }   \
-                            asm { pop   bx                          }   \
-                            asm { pop   ax                          }   \
-                            asm { iret                              }
+#define portFIRST_CONTEXT()          \
+    asm { mov bx, [ pxCurrentTCB ] } \
+    asm { mov sp, [ bx ] }           \
+    asm { pop bp }                   \
+    asm { pop di }                   \
+    asm { pop si }                   \
+    asm { pop ds }                   \
+    asm { pop es }                   \
+    asm { pop dx }                   \
+    asm { pop cx }                   \
+    asm { pop bx }                   \
+    asm { pop ax }                   \
+    asm { iret }
 
 
-#endif
+#endif /* ifndef PORT_ASM_H */
diff --git a/portable/Paradigm/Tern_EE/small/portmacro.h b/portable/Paradigm/Tern_EE/small/portmacro.h
index ff0b34b20..393e6faa5 100644
--- a/portable/Paradigm/Tern_EE/small/portmacro.h
+++ b/portable/Paradigm/Tern_EE/small/portmacro.h
@@ -46,26 +46,26 @@
  */
 
 /* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      long
-#define portLONG        long
-#define portSHORT       int
-#define portSTACK_TYPE  uint16_t
-#define portBASE_TYPE   short
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        long
+#define portLONG          long
+#define portSHORT         int
+#define portSTACK_TYPE    uint16_t
+#define portBASE_TYPE     short
 
-typedef portSTACK_TYPE StackType_t;
-typedef short BaseType_t;
-typedef unsigned short UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef short            BaseType_t;
+typedef unsigned short   UBaseType_t;
 
 
-typedef void ( __interrupt __far *pxISR )();
+typedef void ( __interrupt __far * pxISR )();
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
-#elif ( configTICK_TYPE_WIDTH_IN_BITS  == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t             TickType_t;
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t   TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+    typedef uint32_t   TickType_t;
     #define portMAX_DELAY    ( TickType_t ) 0xffffffffUL
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -73,36 +73,37 @@ typedef void ( __interrupt __far *pxISR )();
 /*-----------------------------------------------------------*/
 
 /* Critical section handling. */
-#define portENTER_CRITICAL()            __asm{ pushf }  \
-                                        __asm{ cli   }  \
+#define portENTER_CRITICAL() \
+    __asm { pushf }          \
+    __asm { cli }            \
 
-#define portEXIT_CRITICAL()             __asm{ popf }
+#define portEXIT_CRITICAL()         __asm { popf }
 
-#define portDISABLE_INTERRUPTS()        __asm{ cli }
+#define portDISABLE_INTERRUPTS()    __asm { cli }
 
-#define portENABLE_INTERRUPTS()         __asm{ sti }
+#define portENABLE_INTERRUPTS()     __asm { sti }
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portNOP()                       __asm{ nop }
-#define portSTACK_GROWTH                ( -1 )
-#define portSWITCH_INT_NUMBER           0x80
-#define portYIELD()                     __asm{ int portSWITCH_INT_NUMBER }
-#define portTICK_PERIOD_MS              ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT              2
-#define portINITIAL_SW                  ( ( portSTACK_TYPE ) 0x0202 )   /* Start the tasks with interrupts enabled. */
+#define portNOP()      __asm { nop }
+#define portSTACK_GROWTH         ( -1 )
+#define portSWITCH_INT_NUMBER    0x80
+#define portYIELD()    __asm { int portSWITCH_INT_NUMBER }
+#define portTICK_PERIOD_MS       ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT       2
+#define portINITIAL_SW           ( ( portSTACK_TYPE ) 0x0202 )          /* Start the tasks with interrupts enabled. */
 /*-----------------------------------------------------------*/
 
 /* Compiler specifics. */
-#define portINPUT_BYTE( xAddr )             inp( xAddr )
-#define portOUTPUT_BYTE( xAddr, ucValue )   outp( xAddr, ucValue )
-#define portINPUT_WORD( xAddr )             inpw( xAddr )
-#define portOUTPUT_WORD( xAddr, usValue )   outpw( xAddr, usValue )
+#define portINPUT_BYTE( xAddr )              inp( xAddr )
+#define portOUTPUT_BYTE( xAddr, ucValue )    outp( xAddr, ucValue )
+#define portINPUT_WORD( xAddr )              inpw( xAddr )
+#define portOUTPUT_WORD( xAddr, usValue )    outpw( xAddr, usValue )
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters )
-#define portTASK_FUNCTION( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters )
+#define portTASK_FUNCTION_PROTO( vTaskFunction, vParameters )    void vTaskFunction( void * pvParameters )
+#define portTASK_FUNCTION( vTaskFunction, vParameters )          void vTaskFunction( void * pvParameters )
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/RVDS/ARM7_LPC21xx/port.c b/portable/RVDS/ARM7_LPC21xx/port.c
index a060c045f..2d890e19d 100644
--- a/portable/RVDS/ARM7_LPC21xx/port.c
+++ b/portable/RVDS/ARM7_LPC21xx/port.c
@@ -35,35 +35,35 @@
 #include "task.h"
 
 /* Constants required to setup the initial task context. */
-#define portINITIAL_SPSR                ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
-#define portTHUMB_MODE_BIT              ( ( StackType_t ) 0x20 )
-#define portINSTRUCTION_SIZE            ( ( StackType_t ) 4 )
-#define portNO_CRITICAL_SECTION_NESTING ( ( StackType_t ) 0 )
+#define portINITIAL_SPSR                   ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT                 ( ( StackType_t ) 0x20 )
+#define portINSTRUCTION_SIZE               ( ( StackType_t ) 4 )
+#define portNO_CRITICAL_SECTION_NESTING    ( ( StackType_t ) 0 )
 
 /* Constants required to setup the tick ISR. */
-#define portENABLE_TIMER            ( ( uint8_t ) 0x01 )
-#define portPRESCALE_VALUE          0x00
-#define portINTERRUPT_ON_MATCH      ( ( uint32_t ) 0x01 )
-#define portRESET_COUNT_ON_MATCH    ( ( uint32_t ) 0x02 )
+#define portENABLE_TIMER                   ( ( uint8_t ) 0x01 )
+#define portPRESCALE_VALUE                 0x00
+#define portINTERRUPT_ON_MATCH             ( ( uint32_t ) 0x01 )
+#define portRESET_COUNT_ON_MATCH           ( ( uint32_t ) 0x02 )
 
 /* Constants required to setup the VIC for the tick ISR. */
-#define portTIMER_VIC_CHANNEL       ( ( uint32_t ) 0x0004 )
-#define portTIMER_VIC_CHANNEL_BIT   ( ( uint32_t ) 0x0010 )
-#define portTIMER_VIC_ENABLE        ( ( uint32_t ) 0x0020 )
+#define portTIMER_VIC_CHANNEL              ( ( uint32_t ) 0x0004 )
+#define portTIMER_VIC_CHANNEL_BIT          ( ( uint32_t ) 0x0010 )
+#define portTIMER_VIC_ENABLE               ( ( uint32_t ) 0x0020 )
 
 /* Constants required to handle interrupts. */
-#define portTIMER_MATCH_ISR_BIT     ( ( uint8_t ) 0x01 )
-#define portCLEAR_VIC_INTERRUPT     ( ( uint32_t ) 0 )
+#define portTIMER_MATCH_ISR_BIT            ( ( uint8_t ) 0x01 )
+#define portCLEAR_VIC_INTERRUPT            ( ( uint32_t ) 0 )
 
 /*-----------------------------------------------------------*/
 
 /* The code generated by the Keil compiler does not maintain separate
-stack and frame pointers. The portENTER_CRITICAL macro cannot therefore
-use the stack as per other ports.  Instead a variable is used to keep
-track of the critical section nesting.  This variable has to be stored
-as part of the task context and must be initialised to a non zero value. */
+ * stack and frame pointers. The portENTER_CRITICAL macro cannot therefore
+ * use the stack as per other ports.  Instead a variable is used to keep
+ * track of the critical section nesting.  This variable has to be stored
+ * as part of the task context and must be initialised to a non zero value. */
 
-#define portNO_CRITICAL_NESTING     ( ( uint32_t ) 0 )
+#define portNO_CRITICAL_NESTING    ( ( uint32_t ) 0 )
 volatile uint32_t ulCriticalNesting = 9999UL;
 
 /*-----------------------------------------------------------*/
@@ -82,60 +82,62 @@ extern __asm void vPortStartFirstTask( void );
 /*
  * See header file for description.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
-StackType_t *pxOriginalTOS;
+    StackType_t * pxOriginalTOS;
 
     /* Setup the initial stack of the task.  The stack is set exactly as
-    expected by the portRESTORE_CONTEXT() macro.
-
-    Remember where the top of the (simulated) stack is before we place
-    anything on it. */
+     * expected by the portRESTORE_CONTEXT() macro.
+     *
+     * Remember where the top of the (simulated) stack is before we place
+     * anything on it. */
     pxOriginalTOS = pxTopOfStack;
 
     /* To ensure asserts in tasks.c don't fail, although in this case the assert
-    is not really required. */
+     * is not really required. */
     pxTopOfStack--;
 
     /* First on the stack is the return address - which in this case is the
-    start of the task.  The offset is added to make the return address appear
-    as it would within an IRQ ISR. */
+     * start of the task.  The offset is added to make the return address appear
+     * as it would within an IRQ ISR. */
     *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
     pxTopOfStack--;
 
-    *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */
+    *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa;    /* R14 */
     pxTopOfStack--;
     *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
+    *pxTopOfStack = ( StackType_t ) 0x12121212;    /* R12 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
+    *pxTopOfStack = ( StackType_t ) 0x11111111;    /* R11 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
+    *pxTopOfStack = ( StackType_t ) 0x10101010;    /* R10 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
+    *pxTopOfStack = ( StackType_t ) 0x09090909;    /* R9 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
+    *pxTopOfStack = ( StackType_t ) 0x08080808;    /* R8 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
+    *pxTopOfStack = ( StackType_t ) 0x07070707;    /* R7 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
+    *pxTopOfStack = ( StackType_t ) 0x06060606;    /* R6 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
+    *pxTopOfStack = ( StackType_t ) 0x05050505;    /* R5 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
+    *pxTopOfStack = ( StackType_t ) 0x04040404;    /* R4 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
+    *pxTopOfStack = ( StackType_t ) 0x03030303;    /* R3 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
+    *pxTopOfStack = ( StackType_t ) 0x02020202;    /* R2 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
+    *pxTopOfStack = ( StackType_t ) 0x01010101;    /* R1 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+    *pxTopOfStack = ( StackType_t ) pvParameters;  /* R0 */
     pxTopOfStack--;
 
     /* The last thing onto the stack is the status register, which is set for
-    system mode, with interrupts enabled. */
+     * system mode, with interrupts enabled. */
     *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
 
     if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00UL )
@@ -147,10 +149,10 @@ StackType_t *pxOriginalTOS;
     pxTopOfStack--;
 
     /* The code generated by the Keil compiler does not maintain separate
-    stack and frame pointers. The portENTER_CRITICAL macro cannot therefore
-    use the stack as per other ports.  Instead a variable is used to keep
-    track of the critical section nesting.  This variable has to be stored
-    as part of the task context and is initially set to zero. */
+     * stack and frame pointers. The portENTER_CRITICAL macro cannot therefore
+     * use the stack as per other ports.  Instead a variable is used to keep
+     * track of the critical section nesting.  This variable has to be stored
+     * as part of the task context and is initially set to zero. */
     *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
 
     return pxTopOfStack;
@@ -163,7 +165,7 @@ BaseType_t xPortStartScheduler( void )
     prvSetupTimerInterrupt();
 
     /* Start the first task.  This is done from portISR.c as ARM mode must be
-    used. */
+     * used. */
     vPortStartFirstTask();
 
     /* Should not get here! */
@@ -174,56 +176,56 @@ BaseType_t xPortStartScheduler( void )
 void vPortEndScheduler( void )
 {
     /* It is unlikely that the ARM port will require this function as there
-    is nothing to return to.  If this is required - stop the tick ISR then
-    return back to main. */
+     * is nothing to return to.  If this is required - stop the tick ISR then
+     * return back to main. */
 }
 /*-----------------------------------------------------------*/
 
 #if configUSE_PREEMPTION == 0
 
-    /*
-     * The cooperative scheduler requires a normal IRQ service routine to
-     * simply increment the system tick.
-     */
+/*
+ * The cooperative scheduler requires a normal IRQ service routine to
+ * simply increment the system tick.
+ */
     void vNonPreemptiveTick( void ) __irq;
     void vNonPreemptiveTick( void ) __irq
     {
         /* Increment the tick count - this may make a delaying task ready
-        to run - but a context switch is not performed. */
+         * to run - but a context switch is not performed. */
         xTaskIncrementTick();
 
-        T0IR = portTIMER_MATCH_ISR_BIT;             /* Clear the timer event */
-        VICVectAddr = portCLEAR_VIC_INTERRUPT;      /* Acknowledge the Interrupt */
+        T0IR = portTIMER_MATCH_ISR_BIT;        /* Clear the timer event */
+        VICVectAddr = portCLEAR_VIC_INTERRUPT; /* Acknowledge the Interrupt */
     }
 
- #else
+#else /* if configUSE_PREEMPTION == 0 */
 
-    /*
-     **************************************************************************
-     * The preemptive scheduler ISR is written in assembler and can be found
-     * in the portASM.s file. This will only get used if portUSE_PREEMPTION
-     * is set to 1 in portmacro.h
-     **************************************************************************
-     */
+/*
+ **************************************************************************
+ * The preemptive scheduler ISR is written in assembler and can be found
+ * in the portASM.s file. This will only get used if portUSE_PREEMPTION
+ * is set to 1 in portmacro.h
+ **************************************************************************
+ */
 
-      void vPreemptiveTick( void );
+    void vPreemptiveTick( void );
 
-#endif
+#endif /* if configUSE_PREEMPTION == 0 */
 /*-----------------------------------------------------------*/
 
 static void prvSetupTimerInterrupt( void )
 {
-uint32_t ulCompareMatch;
+    uint32_t ulCompareMatch;
 
     /* A 1ms tick does not require the use of the timer prescale.  This is
-    defaulted to zero but can be used if necessary. */
+     * defaulted to zero but can be used if necessary. */
     T0PR = portPRESCALE_VALUE;
 
     /* Calculate the match value required for our wanted tick rate. */
     ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
 
     /* Protect against divide by zero.  Using an if() statement still results
-    in a warning - hence the #if. */
+     * in a warning - hence the #if. */
     #if portPRESCALE_VALUE != 0
     {
         ulCompareMatch /= ( portPRESCALE_VALUE + 1 );
@@ -240,7 +242,7 @@ uint32_t ulCompareMatch;
     VICIntEnable |= portTIMER_VIC_CHANNEL_BIT;
 
     /* The ISR installed depends on whether the preemptive or cooperative
-    scheduler is being used. */
+     * scheduler is being used. */
     #if configUSE_PREEMPTION == 1
     {
         VICVectAddr0 = ( uint32_t ) vPreemptiveTick;
@@ -254,7 +256,7 @@ uint32_t ulCompareMatch;
     VICVectCntl0 = portTIMER_VIC_CHANNEL | portTIMER_VIC_ENABLE;
 
     /* Start the timer - interrupts are disabled when this function is called
-    so it is okay to do this here. */
+     * so it is okay to do this here. */
     T0TCR = portENABLE_TIMER;
 }
 /*-----------------------------------------------------------*/
@@ -264,9 +266,9 @@ void vPortEnterCritical( void )
     /* Disable interrupts as per portDISABLE_INTERRUPTS();                          */
     __disable_irq();
 
-    /* Now interrupts are disabled ulCriticalNesting can be accessed
-    directly.  Increment ulCriticalNesting to keep a count of how many times
-    portENTER_CRITICAL() has been called. */
+    /* Now that interrupts are disabled, ulCriticalNesting can be accessed
+     * directly.  Increment ulCriticalNesting to keep a count of how many times
+     * portENTER_CRITICAL() has been called. */
     ulCriticalNesting++;
 }
 /*-----------------------------------------------------------*/
@@ -279,7 +281,7 @@ void vPortExitCritical( void )
         ulCriticalNesting--;
 
         /* If the nesting level has reached zero then interrupts should be
-        re-enabled. */
+         * re-enabled. */
         if( ulCriticalNesting == portNO_CRITICAL_NESTING )
         {
             /* Enable interrupts as per portEXIT_CRITICAL(). */
diff --git a/portable/RVDS/ARM7_LPC21xx/portmacro.h b/portable/RVDS/ARM7_LPC21xx/portmacro.h
index 95043eb8d..be0628b77 100644
--- a/portable/RVDS/ARM7_LPC21xx/portmacro.h
+++ b/portable/RVDS/ARM7_LPC21xx/portmacro.h
@@ -47,24 +47,24 @@
  */
 
 /* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint32_t
-#define portBASE_TYPE   long
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
-#elif ( configTICK_TYPE_WIDTH_IN_BITS  == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t             TickType_t;
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+    typedef uint32_t     TickType_t;
     #define portMAX_DELAY    ( TickType_t ) 0xffffffffUL
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -72,34 +72,34 @@ typedef unsigned long UBaseType_t;
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portSTACK_GROWTH            ( -1 )
-#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT          8
+#define portSTACK_GROWTH      ( -1 )
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT    8
 /*-----------------------------------------------------------*/
 
 /* Task utilities. */
 
 /*-----------------------------------------------------------
- * ISR entry and exit macros.  These are only required if a task switch
- * is required from an ISR.
- *----------------------------------------------------------*/
+* ISR entry and exit macros.  These are only required if a task switch
+* is required from an ISR.
+*----------------------------------------------------------*/
 
 /* If a switch is required then we just need to call */
 /* vTaskSwitchContext() as the context has already been */
 /* saved. */
 
-#define portEXIT_SWITCHING_ISR(SwitchRequired)               \
-{                                                            \
-extern void vTaskSwitchContext(void);                        \
-                                                             \
-        if(SwitchRequired)                                   \
-        {                                                    \
-            vTaskSwitchContext();                            \
-        }                                                    \
-}                                                            \
+#define portEXIT_SWITCHING_ISR( SwitchRequired ) \
+    {                                            \
+        extern void vTaskSwitchContext( void );  \
+                                                 \
+        if( SwitchRequired )                     \
+        {                                        \
+            vTaskSwitchContext();                \
+        }                                        \
+    }                                            \
 
 extern void vPortYield( void );
-#define portYIELD() vPortYield()
+#define portYIELD()    vPortYield()
 
 
 /* Critical section management. */
@@ -117,31 +117,31 @@ extern void vPortYield( void );
 
 
 /*-----------------------------------------------------------
- * Critical section control
- *
- * The code generated by the Keil compiler does not maintain separate
- * stack and frame pointers. The portENTER_CRITICAL macro cannot therefore
- * use the stack as per other ports.  Instead a variable is used to keep
- * track of the critical section nesting.  This necessitates the use of a
- * function in place of the macro.
- *----------------------------------------------------------*/
+* Critical section control
+*
+* The code generated by the Keil compiler does not maintain separate
+* stack and frame pointers. The portENTER_CRITICAL macro cannot therefore
+* use the stack as per other ports.  Instead a variable is used to keep
+* track of the critical section nesting.  This necessitates the use of a
+* function in place of the macro.
+*----------------------------------------------------------*/
 
 extern void vPortEnterCritical( void );
 extern void vPortExitCritical( void );
 
-#define portENTER_CRITICAL()        vPortEnterCritical();
-#define portEXIT_CRITICAL()         vPortExitCritical();
+#define portENTER_CRITICAL()    vPortEnterCritical();
+#define portEXIT_CRITICAL()     vPortExitCritical();
 /*-----------------------------------------------------------*/
 
 /* Compiler specifics. */
 #define inline
 #define register
-#define portNOP()   __asm{ NOP }
+#define portNOP()    __asm { NOP }
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )  void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )    void vFunction( void *pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/RVDS/ARM_CA9/port.c b/portable/RVDS/ARM_CA9/port.c
index 661e44500..d3870b8ed 100644
--- a/portable/RVDS/ARM_CA9/port.c
+++ b/portable/RVDS/ARM_CA9/port.c
@@ -34,43 +34,43 @@
 #include "task.h"
 
 #ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS
-    #error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+    #error "configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined.  See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
 #endif
 
 #ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET
-    #error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+    #error "configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined.  See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
 #endif
 
 #ifndef configUNIQUE_INTERRUPT_PRIORITIES
-    #error configUNIQUE_INTERRUPT_PRIORITIES must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+    #error "configUNIQUE_INTERRUPT_PRIORITIES must be defined.  See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
 #endif
 
 #ifndef configSETUP_TICK_INTERRUPT
-    #error configSETUP_TICK_INTERRUPT() must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+    #error "configSETUP_TICK_INTERRUPT() must be defined.  See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
 #endif /* configSETUP_TICK_INTERRUPT */
 
 #ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
-    #error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+    #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be defined.  See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
 #endif
 
 #if configMAX_API_CALL_INTERRUPT_PRIORITY == 0
-    #error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0
+    #error "configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0"
 #endif
 
 #if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES
-    #error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority
+    #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority"
 #endif
 
 #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
     /* Check the configuration. */
-    #if( configMAX_PRIORITIES > 32 )
-        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+    #if ( configMAX_PRIORITIES > 32 )
+        #error "configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice."
     #endif
 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 
 /* In case security extensions are implemented. */
 #if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
-    #error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
+    #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )"
 #endif
 
 #ifndef configCLEAR_TICK_INTERRUPT
@@ -78,80 +78,80 @@
 #endif
 
 /* The number of bits to shift for an interrupt priority is dependent on the
-number of bits implemented by the interrupt controller. */
+ * number of bits implemented by the interrupt controller. */
 #if configUNIQUE_INTERRUPT_PRIORITIES == 16
-    #define portPRIORITY_SHIFT 4
-    #define portMAX_BINARY_POINT_VALUE  3
+    #define portPRIORITY_SHIFT            4
+    #define portMAX_BINARY_POINT_VALUE    3
 #elif configUNIQUE_INTERRUPT_PRIORITIES == 32
-    #define portPRIORITY_SHIFT 3
-    #define portMAX_BINARY_POINT_VALUE  2
+    #define portPRIORITY_SHIFT            3
+    #define portMAX_BINARY_POINT_VALUE    2
 #elif configUNIQUE_INTERRUPT_PRIORITIES == 64
-    #define portPRIORITY_SHIFT 2
-    #define portMAX_BINARY_POINT_VALUE  1
+    #define portPRIORITY_SHIFT            2
+    #define portMAX_BINARY_POINT_VALUE    1
 #elif configUNIQUE_INTERRUPT_PRIORITIES == 128
-    #define portPRIORITY_SHIFT 1
-    #define portMAX_BINARY_POINT_VALUE  0
+    #define portPRIORITY_SHIFT            1
+    #define portMAX_BINARY_POINT_VALUE    0
 #elif configUNIQUE_INTERRUPT_PRIORITIES == 256
-    #define portPRIORITY_SHIFT 0
-    #define portMAX_BINARY_POINT_VALUE  0
-#else
-    #error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting.  configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware
-#endif
+    #define portPRIORITY_SHIFT            0
+    #define portMAX_BINARY_POINT_VALUE    0
+#else /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */
+    #error "Invalid configUNIQUE_INTERRUPT_PRIORITIES setting.  configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware"
+#endif /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */
 
 /* A critical section is exited when the critical section nesting count reaches
-this value. */
-#define portNO_CRITICAL_NESTING         ( ( uint32_t ) 0 )
+ * this value. */
+#define portNO_CRITICAL_NESTING                              ( ( uint32_t ) 0 )
 
 /* In all GICs 255 can be written to the priority mask register to unmask all
-(but the lowest) interrupt priority. */
-#define portUNMASK_VALUE                ( 0xFFUL )
+ * (but the lowest) interrupt priority. */
+#define portUNMASK_VALUE                                     ( 0xFFUL )
 
 /* Tasks are not created with a floating point context, but can be given a
-floating point context after they have been created.  A variable is stored as
-part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
-does not have an FPU context, or any other value if the task does have an FPU
-context. */
-#define portNO_FLOATING_POINT_CONTEXT   ( ( StackType_t ) 0 )
+ * floating point context after they have been created.  A variable is stored as
+ * part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
+ * does not have an FPU context, or any other value if the task does have an FPU
+ * context. */
+#define portNO_FLOATING_POINT_CONTEXT                        ( ( StackType_t ) 0 )
 
 /* Interrupt controller access addresses. */
-#define portICCPMR_PRIORITY_MASK_OFFSET         ( 0x04 )
-#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ( 0x0C )
-#define portICCEOIR_END_OF_INTERRUPT_OFFSET     ( 0x10 )
-#define portICCBPR_BINARY_POINT_OFFSET          ( 0x08 )
-#define portICCRPR_RUNNING_PRIORITY_OFFSET      ( 0x14 )
-#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS      ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )
-#define portICCPMR_PRIORITY_MASK_REGISTER                   ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )
-#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS   ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )
-#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS       ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )
-#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS           ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )
-#define portICCBPR_BINARY_POINT_REGISTER                    ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
-#define portICCRPR_RUNNING_PRIORITY_REGISTER                ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )
+#define portICCPMR_PRIORITY_MASK_OFFSET                      ( 0x04 )
+#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET              ( 0x0C )
+#define portICCEOIR_END_OF_INTERRUPT_OFFSET                  ( 0x10 )
+#define portICCBPR_BINARY_POINT_OFFSET                       ( 0x08 )
+#define portICCRPR_RUNNING_PRIORITY_OFFSET                   ( 0x14 )
+#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS       ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )
+#define portICCPMR_PRIORITY_MASK_REGISTER                    ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )
+#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS    ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )
+#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS        ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )
+#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS            ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )
+#define portICCBPR_BINARY_POINT_REGISTER                     ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
+#define portICCRPR_RUNNING_PRIORITY_REGISTER                 ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )
 
 /* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary
-point is zero. */
-#define portBINARY_POINT_BITS           ( ( uint8_t ) 0x03 )
+ * point is zero. */
+#define portBINARY_POINT_BITS                                ( ( uint8_t ) 0x03 )
 
 /* Constants required to setup the initial task context. */
-#define portINITIAL_SPSR                ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
-#define portTHUMB_MODE_BIT              ( ( StackType_t ) 0x20 )
-#define portTHUMB_MODE_ADDRESS          ( 0x01UL )
+#define portINITIAL_SPSR                                     ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT                                   ( ( StackType_t ) 0x20 )
+#define portTHUMB_MODE_ADDRESS                               ( 0x01UL )
 
 /* Masks all bits in the APSR other than the mode bits. */
-#define portAPSR_MODE_BITS_MASK         ( 0x1F )
+#define portAPSR_MODE_BITS_MASK                              ( 0x1F )
 
 /* The value of the mode bits in the APSR when the CPU is executing in user
-mode. */
-#define portAPSR_USER_MODE              ( 0x10 )
+ * mode. */
+#define portAPSR_USER_MODE                                   ( 0x10 )
 
 /* Macro to unmask all interrupt priorities. */
-#define portCLEAR_INTERRUPT_MASK()                                          \
-{                                                                           \
-    __disable_irq();                                                        \
-    portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE;                   \
-    __asm(  "DSB        \n"                                                 \
-            "ISB        \n" );                                              \
-    __enable_irq();                                                         \
-}
+#define portCLEAR_INTERRUPT_MASK()                            \
+    {                                                         \
+        __disable_irq();                                      \
+        portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \
+        __asm( "DSB        \n"                                \
+               "ISB        \n" );                             \
+        __enable_irq();                                       \
+    }
 
 /*-----------------------------------------------------------*/
 
@@ -169,29 +169,29 @@ static void prvTaskExitError( void );
 /*-----------------------------------------------------------*/
 
 /* A variable is used to keep track of the critical section nesting.  This
-variable has to be stored as part of the task context and must be initialised to
-a non zero value to ensure interrupts don't inadvertently become unmasked before
-the scheduler starts.  As it is stored as part of the task context it will
-automatically be set to 0 when the first task is started. */
+ * variable has to be stored as part of the task context and must be initialised to
+ * a non zero value to ensure interrupts don't inadvertently become unmasked before
+ * the scheduler starts.  As it is stored as part of the task context it will
+ * automatically be set to 0 when the first task is started. */
 volatile uint32_t ulCriticalNesting = 9999UL;
 
 /* Used to pass constants into the ASM code.  The address at which variables are
-placed is the constant value so indirect loads in the asm code are not
-required. */
+ * placed is the constant value so indirect loads in the asm code are not
+ * required. */
 uint32_t ulICCIAR __attribute__( ( at( portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ) ) );
 uint32_t ulICCEOIR __attribute__( ( at( portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ) ) );
 uint32_t ulICCPMR __attribute__( ( at( portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ) ) );
 uint32_t ulAsmAPIPriorityMask __attribute__( ( at( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) ) );
 
 /* Saved as part of the task context.  If ulPortTaskHasFPUContext is non-zero then
-a floating point context must be saved and restored for the task. */
+ * a floating point context must be saved and restored for the task. */
 uint32_t ulPortTaskHasFPUContext = pdFALSE;
 
 /* Set to 1 to pend a context switch from an ISR. */
 uint32_t ulPortYieldRequired = pdFALSE;
 
 /* Counts the interrupt nesting depth.  A context switch is only performed if
-if the nesting depth is 0. */
+ * if the nesting depth is 0. */
 uint32_t ulPortInterruptNesting = 0UL;
 
 /*-----------------------------------------------------------*/
@@ -199,14 +199,16 @@ uint32_t ulPortInterruptNesting = 0UL;
 /*
  * See header file for description.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
     /* Setup the initial stack of the task.  The stack is set exactly as
-    expected by the portRESTORE_CONTEXT() macro.
-
-    The fist real value on the stack is the status register, which is set for
-    system mode, with interrupts enabled.  A few NULLs are added first to ensure
-    GDB does not try decoding a non-existent return address. */
+     * expected by the portRESTORE_CONTEXT() macro.
+     *
+     * The fist real value on the stack is the status register, which is set for
+     * system mode, with interrupts enabled.  A few NULLs are added first to ensure
+     * GDB does not try decoding a non-existent return address. */
     *pxTopOfStack = NULL;
     pxTopOfStack--;
     *pxTopOfStack = NULL;
@@ -228,43 +230,43 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
     pxTopOfStack--;
 
     /* Next all the registers other than the stack pointer. */
-    *pxTopOfStack = ( StackType_t ) prvTaskExitError;   /* R14 */
+    *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* R14 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
+    *pxTopOfStack = ( StackType_t ) 0x12121212;       /* R12 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
+    *pxTopOfStack = ( StackType_t ) 0x11111111;       /* R11 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
+    *pxTopOfStack = ( StackType_t ) 0x10101010;       /* R10 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
+    *pxTopOfStack = ( StackType_t ) 0x09090909;       /* R9 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
+    *pxTopOfStack = ( StackType_t ) 0x08080808;       /* R8 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
+    *pxTopOfStack = ( StackType_t ) 0x07070707;       /* R7 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
+    *pxTopOfStack = ( StackType_t ) 0x06060606;       /* R6 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
+    *pxTopOfStack = ( StackType_t ) 0x05050505;       /* R5 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
+    *pxTopOfStack = ( StackType_t ) 0x04040404;       /* R4 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
+    *pxTopOfStack = ( StackType_t ) 0x03030303;       /* R3 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
+    *pxTopOfStack = ( StackType_t ) 0x02020202;       /* R2 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
+    *pxTopOfStack = ( StackType_t ) 0x01010101;       /* R1 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+    *pxTopOfStack = ( StackType_t ) pvParameters;     /* R0 */
     pxTopOfStack--;
 
     /* The task will start with a critical nesting count of 0 as interrupts are
-    enabled. */
+     * enabled. */
     *pxTopOfStack = portNO_CRITICAL_NESTING;
     pxTopOfStack--;
 
     /* The task will start without a floating point context.  A task that uses
-    the floating point hardware must call vPortTaskUsesFPU() before executing
-    any floating point instructions. */
+     * the floating point hardware must call vPortTaskUsesFPU() before executing
+     * any floating point instructions. */
     *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
 
     return pxTopOfStack;
@@ -274,23 +276,26 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
 static void prvTaskExitError( void )
 {
     /* A function that implements a task must not exit or attempt to return to
-    its caller as there is nothing to return to.  If a task wants to exit it
-    should instead call vTaskDelete( NULL ).
-
-    Artificially force an assert() to be triggered if configASSERT() is
-    defined, then stop here so application writers can catch the error. */
+     * its caller as there is nothing to return to.  If a task wants to exit it
+     * should instead call vTaskDelete( NULL ).
+     *
+     * Artificially force an assert() to be triggered if configASSERT() is
+     * defined, then stop here so application writers can catch the error. */
     configASSERT( ulPortInterruptNesting == ~0UL );
     portDISABLE_INTERRUPTS();
-    for( ;; );
+
+    for( ; ; )
+    {
+    }
 }
 /*-----------------------------------------------------------*/
 
 BaseType_t xPortStartScheduler( void )
 {
-uint32_t ulAPSR;
+    uint32_t ulAPSR;
 
     /* Only continue if the CPU is not in User mode.  The CPU must be in a
-    Privileged mode for the scheduler to start. */
+     * Privileged mode for the scheduler to start. */
     __asm( "MRS ulAPSR, APSR" );
     ulAPSR &= portAPSR_MODE_BITS_MASK;
     configASSERT( ulAPSR != portAPSR_USER_MODE );
@@ -298,8 +303,8 @@ uint32_t ulAPSR;
     if( ulAPSR != portAPSR_USER_MODE )
     {
         /* Only continue if the binary point value is set to its lowest possible
-        setting.  See the comments in vPortValidateInterruptPriority() below for
-        more information. */
+         * setting.  See the comments in vPortValidateInterruptPriority() below for
+         * more information. */
         configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
 
         if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )
@@ -313,8 +318,8 @@ uint32_t ulAPSR;
     }
 
     /* Will only get here if vTaskStartScheduler() was called with the CPU in
-    a non-privileged mode or the binary point register was not set to its lowest
-    possible value. */
+     * a non-privileged mode or the binary point register was not set to its lowest
+     * possible value. */
     return 0;
 }
 /*-----------------------------------------------------------*/
@@ -322,7 +327,7 @@ uint32_t ulAPSR;
 void vPortEndScheduler( void )
 {
     /* Not implemented in ports where there is nothing to return to.
-    Artificially force an assert. */
+     * Artificially force an assert. */
     configASSERT( ulCriticalNesting == 1000UL );
 }
 /*-----------------------------------------------------------*/
@@ -332,16 +337,16 @@ void vPortEnterCritical( void )
     /* Disable interrupts as per portDISABLE_INTERRUPTS();  */
     ulPortSetInterruptMask();
 
-    /* Now interrupts are disabled ulCriticalNesting can be accessed
-    directly.  Increment ulCriticalNesting to keep a count of how many times
-    portENTER_CRITICAL() has been called. */
+    /* Now that interrupts are disabled, ulCriticalNesting can be accessed
+     * directly.  Increment ulCriticalNesting to keep a count of how many times
+     * portENTER_CRITICAL() has been called. */
     ulCriticalNesting++;
 
     /* This is not the interrupt safe version of the enter critical function so
-    assert() if it is being called from an interrupt context.  Only API
-    functions that end in "FromISR" can be used in an interrupt.  Only assert if
-    the critical nesting count is 1 to protect against recursive calls if the
-    assert function also uses a critical section. */
+     * assert() if it is being called from an interrupt context.  Only API
+     * functions that end in "FromISR" can be used in an interrupt.  Only assert if
+     * the critical nesting count is 1 to protect against recursive calls if the
+     * assert function also uses a critical section. */
     if( ulCriticalNesting == 1 )
     {
         configASSERT( ulPortInterruptNesting == 0 );
@@ -354,15 +359,15 @@ void vPortExitCritical( void )
     if( ulCriticalNesting > portNO_CRITICAL_NESTING )
     {
         /* Decrement the nesting count as the critical section is being
-        exited. */
+         * exited. */
         ulCriticalNesting--;
 
         /* If the nesting level has reached zero then all interrupt
-        priorities must be re-enabled. */
+         * priorities must be re-enabled. */
         if( ulCriticalNesting == portNO_CRITICAL_NESTING )
         {
             /* Critical nesting has reached zero so all interrupt priorities
-            should be unmasked. */
+             * should be unmasked. */
             portCLEAR_INTERRUPT_MASK();
         }
     }
@@ -372,12 +377,12 @@ void vPortExitCritical( void )
 void FreeRTOS_Tick_Handler( void )
 {
     /* Set interrupt mask before altering scheduler structures.   The tick
-    handler runs at the lowest priority, so interrupts cannot already be masked,
-    so there is no need to save and restore the current mask value. */
+     * handler runs at the lowest priority, so interrupts cannot already be masked,
+     * so there is no need to save and restore the current mask value. */
     __disable_irq();
     portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
-    __asm(  "DSB        \n"
-            "ISB        \n" );
+    __asm( "DSB        \n"
+           "ISB        \n" );
     __enable_irq();
 
     /* Increment the RTOS tick. */
@@ -394,10 +399,10 @@ void FreeRTOS_Tick_Handler( void )
 
 void vPortTaskUsesFPU( void )
 {
-uint32_t ulInitialFPSCR = 0;
+    uint32_t ulInitialFPSCR = 0;
 
     /* A task is registering the fact that it needs an FPU context.  Set the
-    FPU flag (which is saved as part of the task context). */
+     * FPU flag (which is saved as part of the task context). */
     ulPortTaskHasFPUContext = pdTRUE;
 
     /* Initialise the floating point status register. */
@@ -416,9 +421,10 @@ void vPortClearInterruptMask( uint32_t ulNewMaskValue )
 
 uint32_t ulPortSetInterruptMask( void )
 {
-uint32_t ulReturn;
+    uint32_t ulReturn;
 
     __disable_irq();
+
     if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
     {
         /* Interrupts were already masked. */
@@ -428,49 +434,50 @@ uint32_t ulReturn;
     {
         ulReturn = pdFALSE;
         portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
-        __asm(  "DSB        \n"
-                "ISB        \n" );
+        __asm( "DSB        \n"
+               "ISB        \n" );
     }
+
     __enable_irq();
 
     return ulReturn;
 }
 /*-----------------------------------------------------------*/
 
-#if( configASSERT_DEFINED == 1 )
+#if ( configASSERT_DEFINED == 1 )
 
     void vPortValidateInterruptPriority( void )
     {
         /* The following assertion will fail if a service routine (ISR) for
-        an interrupt that has been assigned a priority above
-        configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
-        function.  ISR safe FreeRTOS API functions must *only* be called
-        from interrupts that have been assigned a priority at or below
-        configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
-        Numerically low interrupt priority numbers represent logically high
-        interrupt priorities, therefore the priority of the interrupt must
-        be set to a value equal to or numerically *higher* than
-        configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
-        FreeRTOS maintains separate thread and ISR API functions to ensure
-        interrupt entry is as fast and simple as possible.
-
-        The following links provide detailed information:
-        https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
-        https://www.FreeRTOS.org/FAQHelp.html */
+         * an interrupt that has been assigned a priority above
+         * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+         * function.  ISR safe FreeRTOS API functions must *only* be called
+         * from interrupts that have been assigned a priority at or below
+         * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+         *
+         * Numerically low interrupt priority numbers represent logically high
+         * interrupt priorities, therefore the priority of the interrupt must
+         * be set to a value equal to or numerically *higher* than
+         * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+         *
+         * FreeRTOS maintains separate thread and ISR API functions to ensure
+         * interrupt entry is as fast and simple as possible.
+         *
+         * The following links provide detailed information:
+         * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+         * https://www.FreeRTOS.org/FAQHelp.html */
         configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
 
         /* Priority grouping:  The interrupt controller (GIC) allows the bits
-        that define each interrupt's priority to be split between bits that
-        define the interrupt's pre-emption priority bits and bits that define
-        the interrupt's sub-priority.  For simplicity all bits must be defined
-        to be pre-emption priority bits.  The following assertion will fail if
-        this is not the case (if some bits represent a sub-priority).
-
-        The priority grouping is configured by the GIC's binary point register
-        (ICCBPR).  Writting 0 to ICCBPR will ensure it is set to its lowest
-        possible value (which may be above 0). */
+         * that define each interrupt's priority to be split between bits that
+         * define the interrupt's pre-emption priority bits and bits that define
+         * the interrupt's sub-priority.  For simplicity all bits must be defined
+         * to be pre-emption priority bits.  The following assertion will fail if
+         * this is not the case (if some bits represent a sub-priority).
+         *
+         * The priority grouping is configured by the GIC's binary point register
+         * (ICCBPR).  Writting 0 to ICCBPR will ensure it is set to its lowest
+         * possible value (which may be above 0). */
         configASSERT( portICCBPR_BINARY_POINT_REGISTER <= portMAX_BINARY_POINT_VALUE );
     }
 
diff --git a/portable/RVDS/ARM_CA9/portmacro.h b/portable/RVDS/ARM_CA9/portmacro.h
index 1351dae9f..fbe3472da 100644
--- a/portable/RVDS/ARM_CA9/portmacro.h
+++ b/portable/RVDS/ARM_CA9/portmacro.h
@@ -46,61 +46,61 @@
  */
 
 /* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint32_t
-#define portBASE_TYPE   long
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-    not need to be guarded with a critical section. */
-    #define portTICK_TYPE_IS_ATOMIC 1
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+    #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portSTACK_GROWTH            ( -1 )
-#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT          8
+#define portSTACK_GROWTH      ( -1 )
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT    8
 
 /*-----------------------------------------------------------*/
 
 /* Task utilities. */
 
 /* Called at the end of an ISR that can cause a context switch. */
-#define portEND_SWITCHING_ISR( xSwitchRequired )\
-{                                               \
-extern uint32_t ulPortYieldRequired;            \
-                                                \
-    if( xSwitchRequired != pdFALSE )            \
-    {                                           \
-        ulPortYieldRequired = pdTRUE;           \
-    }                                           \
-}
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+    {                                            \
+        extern uint32_t ulPortYieldRequired;     \
+                                                 \
+        if( xSwitchRequired != pdFALSE )         \
+        {                                        \
+            ulPortYieldRequired = pdTRUE;        \
+        }                                        \
+    }
 
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
-#define portYIELD() __asm( "SWI 0" );
+#define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
+#define portYIELD()                __asm( "SWI 0" );
 
 
 /*-----------------------------------------------------------
- * Critical section control
- *----------------------------------------------------------*/
+* Critical section control
+*----------------------------------------------------------*/
 
 extern void vPortEnterCritical( void );
 extern void vPortExitCritical( void );
@@ -108,57 +108,57 @@ extern uint32_t ulPortSetInterruptMask( void );
 extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
 
 /* These macros do not globally disable/enable interrupts.  They do mask off
-interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
-#define portENTER_CRITICAL()        vPortEnterCritical();
-#define portEXIT_CRITICAL()         vPortExitCritical();
-#define portDISABLE_INTERRUPTS()    ulPortSetInterruptMask()
-#define portENABLE_INTERRUPTS()     vPortClearInterruptMask( 0 )
-#define portSET_INTERRUPT_MASK_FROM_ISR()       ulPortSetInterruptMask()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)    vPortClearInterruptMask(x)
+ * interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
+#define portENTER_CRITICAL()                      vPortEnterCritical();
+#define portEXIT_CRITICAL()                       vPortExitCritical();
+#define portDISABLE_INTERRUPTS()                  ulPortSetInterruptMask()
+#define portENABLE_INTERRUPTS()                   vPortClearInterruptMask( 0 )
+#define portSET_INTERRUPT_MASK_FROM_ISR()         ulPortSetInterruptMask()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vPortClearInterruptMask( x )
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site.  These are
-not required for this port but included in case common demo code that uses these
-macros is used. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )  void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )    void vFunction( void *pvParameters )
+ * not required for this port but included in case common demo code that uses these
+ * macros is used. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
 /* Prototype of the FreeRTOS tick handler.  This must be installed as the
-handler for whichever peripheral is used to generate the RTOS tick. */
+ * handler for whichever peripheral is used to generate the RTOS tick. */
 void FreeRTOS_Tick_Handler( void );
 
 /* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
-before any floating point instructions are executed. */
+ * before any floating point instructions are executed. */
 void vPortTaskUsesFPU( void );
-#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
+#define portTASK_USES_FLOATING_POINT()    vPortTaskUsesFPU()
 
-#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
-#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
+#define portLOWEST_INTERRUPT_PRIORITY           ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
+#define portLOWEST_USABLE_INTERRUPT_PRIORITY    ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
 
 /* Architecture specific optimisations. */
 #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-    #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+    #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
 #endif
 
 #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
 
-    /* Store/clear the ready priorities in a bit map. */
-    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+/* Store/clear the ready priorities in a bit map. */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 
-    /*-----------------------------------------------------------*/
+/*-----------------------------------------------------------*/
 
-    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __clz( uxReadyPriorities ) )
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31 - __clz( uxReadyPriorities ) )
 
 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 
 #ifdef configASSERT
     void vPortValidateInterruptPriority( void );
-    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()  vPortValidateInterruptPriority()
+    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
 #endif
 
-#define portNOP() __nop()
+#define portNOP()                                         __nop()
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/RVDS/ARM_CM0/portmacro.h b/portable/RVDS/ARM_CM0/portmacro.h
index 4a1ea8a7b..134ee23b8 100644
--- a/portable/RVDS/ARM_CM0/portmacro.h
+++ b/portable/RVDS/ARM_CM0/portmacro.h
@@ -86,9 +86,9 @@ extern void vPortYield( void );
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
 #define portYIELD()                vPortYield()
-#define portEND_SWITCHING_ISR( xSwitchRequired )                                     \
-        do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
-        while( 0 )
+#define portEND_SWITCHING_ISR( xSwitchRequired )                                 \
+    do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
+    while( 0 )
 #define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/RVDS/ARM_CM3/port.c b/portable/RVDS/ARM_CM3/port.c
old mode 100755
new mode 100644
index 91038fd69..ab9fb9f6b
--- a/portable/RVDS/ARM_CM3/port.c
+++ b/portable/RVDS/ARM_CM3/port.c
@@ -310,22 +310,22 @@ BaseType_t xPortStartScheduler( void )
         if( ulImplementedPrioBits == 8 )
         {
             /* When the hardware implements 8 priority bits, there is no way for
-            * the software to configure PRIGROUP to not have sub-priorities. As
-            * a result, the least significant bit is always used for sub-priority
-            * and there are 128 preemption priorities and 2 sub-priorities.
-            *
-            * This may cause some confusion in some cases - for example, if
-            * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
-            * priority interrupts will be masked in Critical Sections as those
-            * are at the same preemption priority. This may appear confusing as
-            * 4 is higher (numerically lower) priority than
-            * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
-            * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
-            * to 4, this confusion does not happen and the behaviour remains the same.
-            *
-            * The following assert ensures that the sub-priority bit in the
-            * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
-            * confusion. */
+             * the software to configure PRIGROUP to not have sub-priorities. As
+             * a result, the least significant bit is always used for sub-priority
+             * and there are 128 preemption priorities and 2 sub-priorities.
+             *
+             * This may cause some confusion in some cases - for example, if
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
+             * priority interrupts will be masked in Critical Sections as those
+             * are at the same preemption priority. This may appear confusing as
+             * 4 is higher (numerically lower) priority than
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
+             * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
+             * to 4, this confusion does not happen and the behaviour remains the same.
+             *
+             * The following assert ensures that the sub-priority bit in the
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
+             * confusion. */
             configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
             ulMaxPRIGROUPValue = 0;
         }
diff --git a/portable/RVDS/ARM_CM3/portmacro.h b/portable/RVDS/ARM_CM3/portmacro.h
index c23a6b3fd..56f59a6e9 100644
--- a/portable/RVDS/ARM_CM3/portmacro.h
+++ b/portable/RVDS/ARM_CM3/portmacro.h
@@ -47,45 +47,45 @@
  */
 
 /* Type definitions. */
-    #define portCHAR          char
-    #define portFLOAT         float
-    #define portDOUBLE        double
-    #define portLONG          long
-    #define portSHORT         short
-    #define portSTACK_TYPE    uint32_t
-    #define portBASE_TYPE     long
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-    typedef portSTACK_TYPE   StackType_t;
-    typedef long             BaseType_t;
-    typedef unsigned long    UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
-    #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-        typedef uint16_t     TickType_t;
-        #define portMAX_DELAY              ( TickType_t ) 0xffff
-    #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-        typedef uint32_t     TickType_t;
-        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
  * not need to be guarded with a critical section. */
-        #define portTICK_TYPE_IS_ATOMIC    1
-    #else
-        #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
-    #endif
+    #define portTICK_TYPE_IS_ATOMIC    1
+#else
+    #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+#endif
 /*-----------------------------------------------------------*/
 
 /* Architecture specifics. */
-    #define portSTACK_GROWTH          ( -1 )
-    #define portTICK_PERIOD_MS        ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-    #define portBYTE_ALIGNMENT        8
+#define portSTACK_GROWTH          ( -1 )
+#define portTICK_PERIOD_MS        ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT        8
 
 /* Constants used with memory barrier intrinsics. */
-    #define portSY_FULL_READ_WRITE    ( 15 )
+#define portSY_FULL_READ_WRITE    ( 15 )
 
 /*-----------------------------------------------------------*/
 
 /* Scheduler utilities. */
-    #define portYIELD()                                 \
+#define portYIELD()                                     \
     {                                                   \
         /* Set a PendSV to request a context switch. */ \
         portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
@@ -97,167 +97,167 @@
     }
 /*-----------------------------------------------------------*/
 
-    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
-    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-    #define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 )
-    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+#define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired != pdFALSE ) portYIELD( ); } while( 0 )
+#define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
 /* Critical section management. */
-    extern void vPortEnterCritical( void );
-    extern void vPortExitCritical( void );
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
 
-    #define portDISABLE_INTERRUPTS()                  vPortRaiseBASEPRI()
-    #define portENABLE_INTERRUPTS()                   vPortSetBASEPRI( 0 )
-    #define portENTER_CRITICAL()                      vPortEnterCritical()
-    #define portEXIT_CRITICAL()                       vPortExitCritical()
-    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulPortRaiseBASEPRI()
-    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vPortSetBASEPRI( x )
+#define portDISABLE_INTERRUPTS()                  vPortRaiseBASEPRI()
+#define portENABLE_INTERRUPTS()                   vPortSetBASEPRI( 0 )
+#define portENTER_CRITICAL()                      vPortEnterCritical()
+#define portEXIT_CRITICAL()                       vPortExitCritical()
+#define portSET_INTERRUPT_MASK_FROM_ISR()         ulPortRaiseBASEPRI()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vPortSetBASEPRI( x )
 
 /*-----------------------------------------------------------*/
 
 /* Tickless idle/low power functionality. */
-    #ifndef portSUPPRESS_TICKS_AND_SLEEP
-        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
-        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
-    #endif
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+    extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+    #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
 /*-----------------------------------------------------------*/
 
 /* Port specific optimisations. */
-    #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
-    #endif
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+    #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
+#endif
 
-    #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
 
 /* Check the configuration. */
-        #if ( configMAX_PRIORITIES > 32 )
-            #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
-        #endif
+    #if ( configMAX_PRIORITIES > 32 )
+        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+    #endif
 
 /* Store/clear the ready priorities in a bit map. */
-        #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-        #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 
 /*-----------------------------------------------------------*/
 
-        #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ( uint32_t ) __clz( ( uxReadyPriorities ) ) )
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ( uint32_t ) __clz( ( uxReadyPriorities ) ) )
 
-    #endif /* taskRECORD_READY_PRIORITY */
+#endif /* taskRECORD_READY_PRIORITY */
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site.  These are
  * not necessary for to use this port.  They are defined so the common demo files
  * (which build with all the ports) will build. */
-    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
-    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 /*-----------------------------------------------------------*/
 
-    #ifdef configASSERT
-        void vPortValidateInterruptPriority( void );
-        #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
-    #endif
+#ifdef configASSERT
+    void vPortValidateInterruptPriority( void );
+    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
+#endif
 
 /* portNOP() is not required by this port. */
-    #define portNOP()
+#define portNOP()
 
-    #define portINLINE              __inline
+#define portINLINE              __inline
 
-    #ifndef portFORCE_INLINE
-        #define portFORCE_INLINE    __forceinline
-    #endif
+#ifndef portFORCE_INLINE
+    #define portFORCE_INLINE    __forceinline
+#endif
 
 /*-----------------------------------------------------------*/
 
-    static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI )
+static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI )
+{
+    __asm
     {
-        __asm
-        {
-            /* Barrier instructions are not used as this function is only used to
-             * lower the BASEPRI value. */
+        /* Barrier instructions are not used as this function is only used to
+         * lower the BASEPRI value. */
 /* *INDENT-OFF* */
             msr basepri, ulBASEPRI
 /* *INDENT-ON* */
-        }
     }
+}
 /*-----------------------------------------------------------*/
 
-    static portFORCE_INLINE void vPortRaiseBASEPRI( void )
-    {
-        uint32_t ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
+static portFORCE_INLINE void vPortRaiseBASEPRI( void )
+{
+    uint32_t ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
 
-        __asm
-        {
-            /* Set BASEPRI to the max syscall priority to effect a critical
-             * section. */
+    __asm
+    {
+        /* Set BASEPRI to the max syscall priority to effect a critical
+         * section. */
 /* *INDENT-OFF* */
             msr basepri, ulNewBASEPRI
             dsb
             isb
 /* *INDENT-ON* */
-        }
     }
+}
 /*-----------------------------------------------------------*/
 
-    static portFORCE_INLINE void vPortClearBASEPRIFromISR( void )
+static portFORCE_INLINE void vPortClearBASEPRIFromISR( void )
+{
+    __asm
     {
-        __asm
-        {
-            /* Set BASEPRI to 0 so no interrupts are masked.  This function is only
-             * used to lower the mask in an interrupt, so memory barriers are not
-             * used. */
+        /* Set BASEPRI to 0 so no interrupts are masked.  This function is only
+         * used to lower the mask in an interrupt, so memory barriers are not
+         * used. */
 /* *INDENT-OFF* */
             msr basepri, # 0
 /* *INDENT-ON* */
-        }
     }
+}
 /*-----------------------------------------------------------*/
 
-    static portFORCE_INLINE uint32_t ulPortRaiseBASEPRI( void )
-    {
-        uint32_t ulReturn, ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
+static portFORCE_INLINE uint32_t ulPortRaiseBASEPRI( void )
+{
+    uint32_t ulReturn, ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
 
-        __asm
-        {
-            /* Set BASEPRI to the max syscall priority to effect a critical
-             * section. */
+    __asm
+    {
+        /* Set BASEPRI to the max syscall priority to effect a critical
+         * section. */
 /* *INDENT-OFF* */
             mrs ulReturn, basepri
             msr basepri, ulNewBASEPRI
             dsb
             isb
 /* *INDENT-ON* */
-        }
-
-        return ulReturn;
     }
+
+    return ulReturn;
+}
 /*-----------------------------------------------------------*/
 
-    static portFORCE_INLINE BaseType_t xPortIsInsideInterrupt( void )
-    {
-        uint32_t ulCurrentInterrupt;
-        BaseType_t xReturn;
+static portFORCE_INLINE BaseType_t xPortIsInsideInterrupt( void )
+{
+    uint32_t ulCurrentInterrupt;
+    BaseType_t xReturn;
 
-        /* Obtain the number of the currently executing interrupt. */
-        __asm
-        {
+    /* Obtain the number of the currently executing interrupt. */
+    __asm
+    {
 /* *INDENT-OFF* */
             mrs ulCurrentInterrupt, ipsr
 /* *INDENT-ON* */
-        }
-
-        if( ulCurrentInterrupt == 0 )
-        {
-            xReturn = pdFALSE;
-        }
-        else
-        {
-            xReturn = pdTRUE;
-        }
-
-        return xReturn;
     }
 
+    if( ulCurrentInterrupt == 0 )
+    {
+        xReturn = pdFALSE;
+    }
+    else
+    {
+        xReturn = pdTRUE;
+    }
+
+    return xReturn;
+}
+
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/RVDS/ARM_CM4F/port.c b/portable/RVDS/ARM_CM4F/port.c
old mode 100755
new mode 100644
index 3c2040596..6794feb3f
--- a/portable/RVDS/ARM_CM4F/port.c
+++ b/portable/RVDS/ARM_CM4F/port.c
@@ -376,22 +376,22 @@ BaseType_t xPortStartScheduler( void )
         if( ulImplementedPrioBits == 8 )
         {
             /* When the hardware implements 8 priority bits, there is no way for
-            * the software to configure PRIGROUP to not have sub-priorities. As
-            * a result, the least significant bit is always used for sub-priority
-            * and there are 128 preemption priorities and 2 sub-priorities.
-            *
-            * This may cause some confusion in some cases - for example, if
-            * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
-            * priority interrupts will be masked in Critical Sections as those
-            * are at the same preemption priority. This may appear confusing as
-            * 4 is higher (numerically lower) priority than
-            * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
-            * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
-            * to 4, this confusion does not happen and the behaviour remains the same.
-            *
-            * The following assert ensures that the sub-priority bit in the
-            * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
-            * confusion. */
+             * the software to configure PRIGROUP to not have sub-priorities. As
+             * a result, the least significant bit is always used for sub-priority
+             * and there are 128 preemption priorities and 2 sub-priorities.
+             *
+             * This may cause some confusion in some cases - for example, if
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
+             * priority interrupts will be masked in Critical Sections as those
+             * are at the same preemption priority. This may appear confusing as
+             * 4 is higher (numerically lower) priority than
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
+             * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
+             * to 4, this confusion does not happen and the behaviour remains the same.
+             *
+             * The following assert ensures that the sub-priority bit in the
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
+             * confusion. */
             configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
             ulMaxPRIGROUPValue = 0;
         }
diff --git a/portable/RVDS/ARM_CM4F/portmacro.h b/portable/RVDS/ARM_CM4F/portmacro.h
index de92c8d4b..645926822 100644
--- a/portable/RVDS/ARM_CM4F/portmacro.h
+++ b/portable/RVDS/ARM_CM4F/portmacro.h
@@ -47,45 +47,45 @@
  */
 
 /* Type definitions. */
-    #define portCHAR          char
-    #define portFLOAT         float
-    #define portDOUBLE        double
-    #define portLONG          long
-    #define portSHORT         short
-    #define portSTACK_TYPE    uint32_t
-    #define portBASE_TYPE     long
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-    typedef portSTACK_TYPE   StackType_t;
-    typedef long             BaseType_t;
-    typedef unsigned long    UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
-    #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-        typedef uint16_t     TickType_t;
-        #define portMAX_DELAY              ( TickType_t ) 0xffff
-    #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-        typedef uint32_t     TickType_t;
-        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
  * not need to be guarded with a critical section. */
-        #define portTICK_TYPE_IS_ATOMIC    1
-    #else
-        #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
-    #endif
+    #define portTICK_TYPE_IS_ATOMIC    1
+#else
+    #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+#endif
 /*-----------------------------------------------------------*/
 
 /* Architecture specifics. */
-    #define portSTACK_GROWTH          ( -1 )
-    #define portTICK_PERIOD_MS        ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-    #define portBYTE_ALIGNMENT        8
+#define portSTACK_GROWTH          ( -1 )
+#define portTICK_PERIOD_MS        ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT        8
 
 /* Constants used with memory barrier intrinsics. */
-    #define portSY_FULL_READ_WRITE    ( 15 )
+#define portSY_FULL_READ_WRITE    ( 15 )
 
 /*-----------------------------------------------------------*/
 
 /* Scheduler utilities. */
-    #define portYIELD()                                 \
+#define portYIELD()                                     \
     {                                                   \
         /* Set a PendSV to request a context switch. */ \
         portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
@@ -97,167 +97,167 @@
     }
 /*-----------------------------------------------------------*/
 
-    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
-    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-    #define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 )
-    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+#define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired != pdFALSE ) portYIELD( ); } while( 0 )
+#define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
 /* Critical section management. */
-    extern void vPortEnterCritical( void );
-    extern void vPortExitCritical( void );
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
 
-    #define portDISABLE_INTERRUPTS()                  vPortRaiseBASEPRI()
-    #define portENABLE_INTERRUPTS()                   vPortSetBASEPRI( 0 )
-    #define portENTER_CRITICAL()                      vPortEnterCritical()
-    #define portEXIT_CRITICAL()                       vPortExitCritical()
-    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulPortRaiseBASEPRI()
-    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vPortSetBASEPRI( x )
+#define portDISABLE_INTERRUPTS()                  vPortRaiseBASEPRI()
+#define portENABLE_INTERRUPTS()                   vPortSetBASEPRI( 0 )
+#define portENTER_CRITICAL()                      vPortEnterCritical()
+#define portEXIT_CRITICAL()                       vPortExitCritical()
+#define portSET_INTERRUPT_MASK_FROM_ISR()         ulPortRaiseBASEPRI()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vPortSetBASEPRI( x )
 
 /*-----------------------------------------------------------*/
 
 /* Tickless idle/low power functionality. */
-    #ifndef portSUPPRESS_TICKS_AND_SLEEP
-        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
-        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
-    #endif
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+    extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+    #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
 /*-----------------------------------------------------------*/
 
 /* Port specific optimisations. */
-    #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
-    #endif
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+    #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
+#endif
 
-    #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
 
 /* Check the configuration. */
-        #if ( configMAX_PRIORITIES > 32 )
-            #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
-        #endif
+    #if ( configMAX_PRIORITIES > 32 )
+        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+    #endif
 
 /* Store/clear the ready priorities in a bit map. */
-        #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-        #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 
 /*-----------------------------------------------------------*/
 
-        #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ( uint32_t ) __clz( ( uxReadyPriorities ) ) )
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ( uint32_t ) __clz( ( uxReadyPriorities ) ) )
 
-    #endif /* taskRECORD_READY_PRIORITY */
+#endif /* taskRECORD_READY_PRIORITY */
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site.  These are
  * not necessary for to use this port.  They are defined so the common demo files
  * (which build with all the ports) will build. */
-    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
-    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 /*-----------------------------------------------------------*/
 
-    #ifdef configASSERT
-        void vPortValidateInterruptPriority( void );
-        #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
-    #endif
+#ifdef configASSERT
+    void vPortValidateInterruptPriority( void );
+    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
+#endif
 
 /* portNOP() is not required by this port. */
-    #define portNOP()
+#define portNOP()
 
-    #define portINLINE              __inline
+#define portINLINE              __inline
 
-    #ifndef portFORCE_INLINE
-        #define portFORCE_INLINE    __forceinline
-    #endif
+#ifndef portFORCE_INLINE
+    #define portFORCE_INLINE    __forceinline
+#endif
 
 /*-----------------------------------------------------------*/
 
-    static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI )
+static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI )
+{
+    __asm
     {
-        __asm
-        {
-            /* Barrier instructions are not used as this function is only used to
-             * lower the BASEPRI value. */
+        /* Barrier instructions are not used as this function is only used to
+         * lower the BASEPRI value. */
 /* *INDENT-OFF* */
             msr basepri, ulBASEPRI
 /* *INDENT-ON* */
-        }
     }
+}
 /*-----------------------------------------------------------*/
 
-    static portFORCE_INLINE void vPortRaiseBASEPRI( void )
-    {
-        uint32_t ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
+static portFORCE_INLINE void vPortRaiseBASEPRI( void )
+{
+    uint32_t ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
 
-        __asm
-        {
-            /* Set BASEPRI to the max syscall priority to effect a critical
-             * section. */
+    __asm
+    {
+        /* Set BASEPRI to the max syscall priority to effect a critical
+         * section. */
 /* *INDENT-OFF* */
             msr basepri, ulNewBASEPRI
             dsb
             isb
 /* *INDENT-ON* */
-        }
     }
+}
 /*-----------------------------------------------------------*/
 
-    static portFORCE_INLINE void vPortClearBASEPRIFromISR( void )
+static portFORCE_INLINE void vPortClearBASEPRIFromISR( void )
+{
+    __asm
     {
-        __asm
-        {
-            /* Set BASEPRI to 0 so no interrupts are masked.  This function is only
-             * used to lower the mask in an interrupt, so memory barriers are not
-             * used. */
+        /* Set BASEPRI to 0 so no interrupts are masked.  This function is only
+         * used to lower the mask in an interrupt, so memory barriers are not
+         * used. */
 /* *INDENT-OFF* */
             msr basepri, # 0
 /* *INDENT-ON* */
-        }
     }
+}
 /*-----------------------------------------------------------*/
 
-    static portFORCE_INLINE uint32_t ulPortRaiseBASEPRI( void )
-    {
-        uint32_t ulReturn, ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
+static portFORCE_INLINE uint32_t ulPortRaiseBASEPRI( void )
+{
+    uint32_t ulReturn, ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
 
-        __asm
-        {
-            /* Set BASEPRI to the max syscall priority to effect a critical
-             * section. */
+    __asm
+    {
+        /* Set BASEPRI to the max syscall priority to effect a critical
+         * section. */
 /* *INDENT-OFF* */
             mrs ulReturn, basepri
             msr basepri, ulNewBASEPRI
             dsb
             isb
 /* *INDENT-ON* */
-        }
-
-        return ulReturn;
     }
+
+    return ulReturn;
+}
 /*-----------------------------------------------------------*/
 
-    static portFORCE_INLINE BaseType_t xPortIsInsideInterrupt( void )
-    {
-        uint32_t ulCurrentInterrupt;
-        BaseType_t xReturn;
+static portFORCE_INLINE BaseType_t xPortIsInsideInterrupt( void )
+{
+    uint32_t ulCurrentInterrupt;
+    BaseType_t xReturn;
 
-        /* Obtain the number of the currently executing interrupt. */
-        __asm
-        {
+    /* Obtain the number of the currently executing interrupt. */
+    __asm
+    {
 /* *INDENT-OFF* */
             mrs ulCurrentInterrupt, ipsr
 /* *INDENT-ON* */
-        }
-
-        if( ulCurrentInterrupt == 0 )
-        {
-            xReturn = pdFALSE;
-        }
-        else
-        {
-            xReturn = pdTRUE;
-        }
-
-        return xReturn;
     }
 
+    if( ulCurrentInterrupt == 0 )
+    {
+        xReturn = pdFALSE;
+    }
+    else
+    {
+        xReturn = pdTRUE;
+    }
+
+    return xReturn;
+}
+
 /* *INDENT-OFF* */
 #ifdef __cplusplus
     }
diff --git a/portable/RVDS/ARM_CM4_MPU/mpu_wrappers_v2_asm.c b/portable/RVDS/ARM_CM4_MPU/mpu_wrappers_v2_asm.c
index e9d0d34a0..931a9ffd4 100644
--- a/portable/RVDS/ARM_CM4_MPU/mpu_wrappers_v2_asm.c
+++ b/portable/RVDS/ARM_CM4_MPU/mpu_wrappers_v2_asm.c
@@ -44,1924 +44,2344 @@
 
 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
 
-#if ( INCLUDE_xTaskDelayUntil == 1 )
+    #if ( INCLUDE_xTaskDelayUntil == 1 )
 
-BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
-                                const TickType_t xTimeIncrement ) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
+                                        const TickType_t xTimeIncrement ) FREERTOS_SYSTEM_CALL;
 
-__asm BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
-                                      const TickType_t xTimeIncrement ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_xTaskDelayUntilImpl
+        __asm BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
+                                              const TickType_t xTimeIncrement ) /* FREERTOS_SYSTEM_CALL */
+        {
+            PRESERVE8
+            extern MPU_xTaskDelayUntilImpl
 
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_xTaskDelayUntil_Unpriv
-MPU_xTaskDelayUntil_Priv
-        pop {r0}
-        b MPU_xTaskDelayUntilImpl
-MPU_xTaskDelayUntil_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskDelayUntilImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-}
+                push {
+                r0
+            }
+            mrs r0, control
+            tst r0, # 1
+            bne MPU_xTaskDelayUntil_Unpriv
+            MPU_xTaskDelayUntil_Priv
+                pop {
+                r0
+            }
+            b MPU_xTaskDelayUntilImpl
+            MPU_xTaskDelayUntil_Unpriv
+                pop {
+                r0
+            }
+            svc # portSVC_SYSTEM_CALL_ENTER
+            bl MPU_xTaskDelayUntilImpl
+            svc # portSVC_SYSTEM_CALL_EXIT
+            bx lr
+        }
 
-#endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */
+    #endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_xTaskAbortDelay == 1 )
+    #if ( INCLUDE_xTaskAbortDelay == 1 )
 
-BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
 
-__asm BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_xTaskAbortDelayImpl
+        __asm BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
+        {
+            PRESERVE8
+            extern MPU_xTaskAbortDelayImpl
 
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_xTaskAbortDelay_Unpriv
-MPU_xTaskAbortDelay_Priv
-        pop {r0}
-        b MPU_xTaskAbortDelayImpl
-MPU_xTaskAbortDelay_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskAbortDelayImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-}
+                push {
+                r0
+            }
+            mrs r0, control
+            tst r0, # 1
+            bne MPU_xTaskAbortDelay_Unpriv
+            MPU_xTaskAbortDelay_Priv
+                pop {
+                r0
+            }
+            b MPU_xTaskAbortDelayImpl
+            MPU_xTaskAbortDelay_Unpriv
+                pop {
+                r0
+            }
+            svc # portSVC_SYSTEM_CALL_ENTER
+            bl MPU_xTaskAbortDelayImpl
+            svc # portSVC_SYSTEM_CALL_EXIT
+            bx lr
+        }
 
-#endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */
+    #endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_vTaskDelay == 1 )
+    #if ( INCLUDE_vTaskDelay == 1 )
 
-void MPU_vTaskDelay( const TickType_t xTicksToDelay ) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskDelay( const TickType_t xTicksToDelay ) FREERTOS_SYSTEM_CALL;
 
-__asm void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_vTaskDelayImpl
+        __asm void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* FREERTOS_SYSTEM_CALL */
+        {
+            PRESERVE8
+            extern MPU_vTaskDelayImpl
 
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_vTaskDelay_Unpriv
-MPU_vTaskDelay_Priv
-        pop {r0}
-        b MPU_vTaskDelayImpl
-MPU_vTaskDelay_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskDelayImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-}
+                push {
+                r0
+            }
+            mrs r0, control
+            tst r0, # 1
+            bne MPU_vTaskDelay_Unpriv
+            MPU_vTaskDelay_Priv
+                pop {
+                r0
+            }
+            b MPU_vTaskDelayImpl
+            MPU_vTaskDelay_Unpriv
+                pop {
+                r0
+            }
+            svc # portSVC_SYSTEM_CALL_ENTER
+            bl MPU_vTaskDelayImpl
+            svc # portSVC_SYSTEM_CALL_EXIT
+            bx lr
+        }
 
-#endif /* if ( INCLUDE_vTaskDelay == 1 ) */
+    #endif /* if ( INCLUDE_vTaskDelay == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_uxTaskPriorityGet == 1 )
+    #if ( INCLUDE_uxTaskPriorityGet == 1 )
 
-UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+        UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
 
-__asm UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_uxTaskPriorityGetImpl
+        __asm UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
+        {
+            PRESERVE8
+            extern MPU_uxTaskPriorityGetImpl
 
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_uxTaskPriorityGet_Unpriv
-MPU_uxTaskPriorityGet_Priv
-        pop {r0}
-        b MPU_uxTaskPriorityGetImpl
-MPU_uxTaskPriorityGet_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskPriorityGetImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-}
+                push {
+                r0
+            }
+            mrs r0, control
+            tst r0, # 1
+            bne MPU_uxTaskPriorityGet_Unpriv
+            MPU_uxTaskPriorityGet_Priv
+                pop {
+                r0
+            }
+            b MPU_uxTaskPriorityGetImpl
+            MPU_uxTaskPriorityGet_Unpriv
+                pop {
+                r0
+            }
+            svc # portSVC_SYSTEM_CALL_ENTER
+            bl MPU_uxTaskPriorityGetImpl
+            svc # portSVC_SYSTEM_CALL_EXIT
+            bx lr
+        }
 
-#endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */
+    #endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_eTaskGetState == 1 )
+    #if ( INCLUDE_eTaskGetState == 1 )
 
-eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+        eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
 
-__asm eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_eTaskGetStateImpl
+        __asm eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
+        {
+            PRESERVE8
+            extern MPU_eTaskGetStateImpl
 
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_eTaskGetState_Unpriv
-MPU_eTaskGetState_Priv
-        pop {r0}
-        b MPU_eTaskGetStateImpl
-MPU_eTaskGetState_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_eTaskGetStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-}
+                push {
+                r0
+            }
+            mrs r0, control
+            tst r0, # 1
+            bne MPU_eTaskGetState_Unpriv
+            MPU_eTaskGetState_Priv
+                pop {
+                r0
+            }
+            b MPU_eTaskGetStateImpl
+            MPU_eTaskGetState_Unpriv
+                pop {
+                r0
+            }
+            svc # portSVC_SYSTEM_CALL_ENTER
+            bl MPU_eTaskGetStateImpl
+            svc # portSVC_SYSTEM_CALL_EXIT
+            bx lr
+        }
 
-#endif /* if ( INCLUDE_eTaskGetState == 1 ) */
+    #endif /* if ( INCLUDE_eTaskGetState == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-void MPU_vTaskGetInfo( TaskHandle_t xTask,
-                       TaskStatus_t * pxTaskStatus,
-                       BaseType_t xGetFreeStackSpace,
-                       eTaskState eState ) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskGetInfo( TaskHandle_t xTask,
+                               TaskStatus_t * pxTaskStatus,
+                               BaseType_t xGetFreeStackSpace,
+                               eTaskState eState ) FREERTOS_SYSTEM_CALL;
 
-__asm void MPU_vTaskGetInfo( TaskHandle_t xTask,
-                             TaskStatus_t * pxTaskStatus,
-                             BaseType_t xGetFreeStackSpace,
-                             eTaskState eState ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_vTaskGetInfoImpl
+        __asm void MPU_vTaskGetInfo( TaskHandle_t xTask,
+                                     TaskStatus_t * pxTaskStatus,
+                                     BaseType_t xGetFreeStackSpace,
+                                     eTaskState eState ) /* FREERTOS_SYSTEM_CALL */
+        {
+            PRESERVE8
+            extern MPU_vTaskGetInfoImpl
 
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_vTaskGetInfo_Unpriv
-MPU_vTaskGetInfo_Priv
-        pop {r0}
-        b MPU_vTaskGetInfoImpl
-MPU_vTaskGetInfo_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskGetInfoImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-}
+                push {
+                r0
+            }
+            mrs r0, control
+            tst r0, # 1
+            bne MPU_vTaskGetInfo_Unpriv
+            MPU_vTaskGetInfo_Priv
+                pop {
+                r0
+            }
+            b MPU_vTaskGetInfoImpl
+            MPU_vTaskGetInfo_Unpriv
+                pop {
+                r0
+            }
+            svc # portSVC_SYSTEM_CALL_ENTER
+            bl MPU_vTaskGetInfoImpl
+            svc # portSVC_SYSTEM_CALL_EXIT
+            bx lr
+        }
 
-#endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
+    #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
+    #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
 
-TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) FREERTOS_SYSTEM_CALL;
+        TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) FREERTOS_SYSTEM_CALL;
 
-__asm TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_xTaskGetIdleTaskHandleImpl
+        __asm TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* FREERTOS_SYSTEM_CALL */
+        {
+            PRESERVE8
+            extern MPU_xTaskGetIdleTaskHandleImpl
 
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_xTaskGetIdleTaskHandle_Unpriv
-MPU_xTaskGetIdleTaskHandle_Priv
-        pop {r0}
-        b MPU_xTaskGetIdleTaskHandleImpl
-MPU_xTaskGetIdleTaskHandle_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetIdleTaskHandleImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-}
+                push {
+                r0
+            }
+            mrs r0, control
+            tst r0, # 1
+            bne MPU_xTaskGetIdleTaskHandle_Unpriv
+            MPU_xTaskGetIdleTaskHandle_Priv
+                pop {
+                r0
+            }
+            b MPU_xTaskGetIdleTaskHandleImpl
+            MPU_xTaskGetIdleTaskHandle_Unpriv
+                pop {
+                r0
+            }
+            svc # portSVC_SYSTEM_CALL_ENTER
+            bl MPU_xTaskGetIdleTaskHandleImpl
+            svc # portSVC_SYSTEM_CALL_EXIT
+            bx lr
+        }
 
-#endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */
+    #endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_vTaskSuspend == 1 )
+    #if ( INCLUDE_vTaskSuspend == 1 )
 
-void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) FREERTOS_SYSTEM_CALL;
 
-__asm void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_vTaskSuspendImpl
+        __asm void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* FREERTOS_SYSTEM_CALL */
+        {
+            PRESERVE8
+            extern MPU_vTaskSuspendImpl
 
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_vTaskSuspend_Unpriv
-MPU_vTaskSuspend_Priv
-        pop {r0}
-        b MPU_vTaskSuspendImpl
-MPU_vTaskSuspend_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSuspendImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-}
+                push {
+                r0
+            }
+            mrs r0, control
+            tst r0, # 1
+            bne MPU_vTaskSuspend_Unpriv
+            MPU_vTaskSuspend_Priv
+                pop {
+                r0
+            }
+            b MPU_vTaskSuspendImpl
+            MPU_vTaskSuspend_Unpriv
+                pop {
+                r0
+            }
+            svc # portSVC_SYSTEM_CALL_ENTER
+            bl MPU_vTaskSuspendImpl
+            svc # portSVC_SYSTEM_CALL_EXIT
+            bx lr
+        }
 
-#endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
+    #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_vTaskSuspend == 1 )
+    #if ( INCLUDE_vTaskSuspend == 1 )
 
-void MPU_vTaskResume( TaskHandle_t xTaskToResume ) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskResume( TaskHandle_t xTaskToResume ) FREERTOS_SYSTEM_CALL;
 
-__asm void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_vTaskResumeImpl
+        __asm void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* FREERTOS_SYSTEM_CALL */
+        {
+            PRESERVE8
+            extern MPU_vTaskResumeImpl
 
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_vTaskResume_Unpriv
-MPU_vTaskResume_Priv
-        pop {r0}
-        b MPU_vTaskResumeImpl
-MPU_vTaskResume_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskResumeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-}
+                push {
+                r0
+            }
+            mrs r0, control
+            tst r0, # 1
+            bne MPU_vTaskResume_Unpriv
+            MPU_vTaskResume_Priv
+                pop {
+                r0
+            }
+            b MPU_vTaskResumeImpl
+            MPU_vTaskResume_Unpriv
+                pop {
+                r0
+            }
+            svc # portSVC_SYSTEM_CALL_ENTER
+            bl MPU_vTaskResumeImpl
+            svc # portSVC_SYSTEM_CALL_EXIT
+            bx lr
+        }
 
-#endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
+    #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
 /*-----------------------------------------------------------*/
 
-TickType_t MPU_xTaskGetTickCount( void ) FREERTOS_SYSTEM_CALL;
+    TickType_t MPU_xTaskGetTickCount( void ) FREERTOS_SYSTEM_CALL;
 
-__asm TickType_t MPU_xTaskGetTickCount( void ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_xTaskGetTickCountImpl
+    __asm TickType_t MPU_xTaskGetTickCount( void ) /* FREERTOS_SYSTEM_CALL */
+    {
+        PRESERVE8
+        extern MPU_xTaskGetTickCountImpl
 
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_xTaskGetTickCount_Unpriv
-MPU_xTaskGetTickCount_Priv
-        pop {r0}
+            push {
+            r0
+        }
+        mrs r0, control
+        tst r0, # 1
+        bne MPU_xTaskGetTickCount_Unpriv
+        MPU_xTaskGetTickCount_Priv
+            pop {
+            r0
+        }
         b MPU_xTaskGetTickCountImpl
-MPU_xTaskGetTickCount_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
+        MPU_xTaskGetTickCount_Unpriv
+            pop {
+            r0
+        }
+        svc # portSVC_SYSTEM_CALL_ENTER
         bl MPU_xTaskGetTickCountImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
+        svc # portSVC_SYSTEM_CALL_EXIT
         bx lr
-}
+    }
 /*-----------------------------------------------------------*/
 
-UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) FREERTOS_SYSTEM_CALL;
+    UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) FREERTOS_SYSTEM_CALL;
 
-__asm UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_uxTaskGetNumberOfTasksImpl
+    __asm UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* FREERTOS_SYSTEM_CALL */
+    {
+        PRESERVE8
+        extern MPU_uxTaskGetNumberOfTasksImpl
 
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_uxTaskGetNumberOfTasks_Unpriv
-MPU_uxTaskGetNumberOfTasks_Priv
-        pop {r0}
+            push {
+            r0
+        }
+        mrs r0, control
+        tst r0, # 1
+        bne MPU_uxTaskGetNumberOfTasks_Unpriv
+        MPU_uxTaskGetNumberOfTasks_Priv
+            pop {
+            r0
+        }
         b MPU_uxTaskGetNumberOfTasksImpl
-MPU_uxTaskGetNumberOfTasks_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
+        MPU_uxTaskGetNumberOfTasks_Unpriv
+            pop {
+            r0
+        }
+        svc # portSVC_SYSTEM_CALL_ENTER
         bl MPU_uxTaskGetNumberOfTasksImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
+        svc # portSVC_SYSTEM_CALL_EXIT
         bx lr
-}
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configGENERATE_RUN_TIME_STATS == 1 )
+    #if ( configGENERATE_RUN_TIME_STATS == 1 )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
 
-__asm configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_ulTaskGetRunTimeCounterImpl
+        __asm configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
+        {
+            PRESERVE8
+            extern MPU_ulTaskGetRunTimeCounterImpl
 
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_ulTaskGetRunTimeCounter_Unpriv
-MPU_ulTaskGetRunTimeCounter_Priv
-        pop {r0}
-        b MPU_ulTaskGetRunTimeCounterImpl
-MPU_ulTaskGetRunTimeCounter_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetRunTimeCounterImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-}
+                push {
+                r0
+            }
+            mrs r0, control
+            tst r0, # 1
+            bne MPU_ulTaskGetRunTimeCounter_Unpriv
+            MPU_ulTaskGetRunTimeCounter_Priv
+                pop {
+                r0
+            }
+            b MPU_ulTaskGetRunTimeCounterImpl
+            MPU_ulTaskGetRunTimeCounter_Unpriv
+                pop {
+                r0
+            }
+            svc # portSVC_SYSTEM_CALL_ENTER
+            bl MPU_ulTaskGetRunTimeCounterImpl
+            svc # portSVC_SYSTEM_CALL_EXIT
+            bx lr
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configGENERATE_RUN_TIME_STATS == 1 )
+    #if ( configGENERATE_RUN_TIME_STATS == 1 )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
 
-__asm configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_ulTaskGetRunTimePercentImpl
+        __asm configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
+        {
+            PRESERVE8
+            extern MPU_ulTaskGetRunTimePercentImpl
 
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_ulTaskGetRunTimePercent_Unpriv
-MPU_ulTaskGetRunTimePercent_Priv
-        pop {r0}
-        b MPU_ulTaskGetRunTimePercentImpl
-MPU_ulTaskGetRunTimePercent_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetRunTimePercentImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-}
+                push {
+                r0
+            }
+            mrs r0, control
+            tst r0, # 1
+            bne MPU_ulTaskGetRunTimePercent_Unpriv
+            MPU_ulTaskGetRunTimePercent_Priv
+                pop {
+                r0
+            }
+            b MPU_ulTaskGetRunTimePercentImpl
+            MPU_ulTaskGetRunTimePercent_Unpriv
+                pop {
+                r0
+            }
+            svc # portSVC_SYSTEM_CALL_ENTER
+            bl MPU_ulTaskGetRunTimePercentImpl
+            svc # portSVC_SYSTEM_CALL_EXIT
+            bx lr
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+    #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) FREERTOS_SYSTEM_CALL;
 
-__asm configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_ulTaskGetIdleRunTimePercentImpl
+        __asm configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* FREERTOS_SYSTEM_CALL */
+        {
+            PRESERVE8
+            extern MPU_ulTaskGetIdleRunTimePercentImpl
 
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_ulTaskGetIdleRunTimePercent_Unpriv
-MPU_ulTaskGetIdleRunTimePercent_Priv
-        pop {r0}
-        b MPU_ulTaskGetIdleRunTimePercentImpl
-MPU_ulTaskGetIdleRunTimePercent_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetIdleRunTimePercentImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-}
+                push {
+                r0
+            }
+            mrs r0, control
+            tst r0, # 1
+            bne MPU_ulTaskGetIdleRunTimePercent_Unpriv
+            MPU_ulTaskGetIdleRunTimePercent_Priv
+                pop {
+                r0
+            }
+            b MPU_ulTaskGetIdleRunTimePercentImpl
+            MPU_ulTaskGetIdleRunTimePercent_Unpriv
+                pop {
+                r0
+            }
+            svc # portSVC_SYSTEM_CALL_ENTER
+            bl MPU_ulTaskGetIdleRunTimePercentImpl
+            svc # portSVC_SYSTEM_CALL_EXIT
+            bx lr
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+    #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
 
-configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) FREERTOS_SYSTEM_CALL;
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) FREERTOS_SYSTEM_CALL;
 
-__asm configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_ulTaskGetIdleRunTimeCounterImpl
+        __asm configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* FREERTOS_SYSTEM_CALL */
+        {
+            PRESERVE8
+            extern MPU_ulTaskGetIdleRunTimeCounterImpl
 
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv
-MPU_ulTaskGetIdleRunTimeCounter_Priv
-        pop {r0}
-        b MPU_ulTaskGetIdleRunTimeCounterImpl
-MPU_ulTaskGetIdleRunTimeCounter_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetIdleRunTimeCounterImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-}
+                push {
+                r0
+            }
+            mrs r0, control
+            tst r0, # 1
+            bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv
+            MPU_ulTaskGetIdleRunTimeCounter_Priv
+                pop {
+                r0
+            }
+            b MPU_ulTaskGetIdleRunTimeCounterImpl
+            MPU_ulTaskGetIdleRunTimeCounter_Unpriv
+                pop {
+                r0
+            }
+            svc # portSVC_SYSTEM_CALL_ENTER
+            bl MPU_ulTaskGetIdleRunTimeCounterImpl
+            svc # portSVC_SYSTEM_CALL_EXIT
+            bx lr
+        }
 
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+    #if ( configUSE_APPLICATION_TASK_TAG == 1 )
 
-void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
-                                     TaskHookFunction_t pxHookFunction ) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
+                                             TaskHookFunction_t pxHookFunction ) FREERTOS_SYSTEM_CALL;
 
-__asm void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
-                                           TaskHookFunction_t pxHookFunction ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_vTaskSetApplicationTaskTagImpl
+        __asm void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
+                                                   TaskHookFunction_t pxHookFunction ) /* FREERTOS_SYSTEM_CALL */
+        {
+            PRESERVE8
+            extern MPU_vTaskSetApplicationTaskTagImpl
 
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_vTaskSetApplicationTaskTag_Unpriv
-MPU_vTaskSetApplicationTaskTag_Priv
-        pop {r0}
-        b MPU_vTaskSetApplicationTaskTagImpl
-MPU_vTaskSetApplicationTaskTag_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSetApplicationTaskTagImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-}
+                push {
+                r0
+            }
+            mrs r0, control
+            tst r0, # 1
+            bne MPU_vTaskSetApplicationTaskTag_Unpriv
+            MPU_vTaskSetApplicationTaskTag_Priv
+                pop {
+                r0
+            }
+            b MPU_vTaskSetApplicationTaskTagImpl
+            MPU_vTaskSetApplicationTaskTag_Unpriv
+                pop {
+                r0
+            }
+            svc # portSVC_SYSTEM_CALL_ENTER
+            bl MPU_vTaskSetApplicationTaskTagImpl
+            svc # portSVC_SYSTEM_CALL_EXIT
+            bx lr
+        }
 
-#endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
+    #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+    #if ( configUSE_APPLICATION_TASK_TAG == 1 )
 
-TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+        TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
 
-__asm TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_xTaskGetApplicationTaskTagImpl
+        __asm TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
+        {
+            PRESERVE8
+            extern MPU_xTaskGetApplicationTaskTagImpl
 
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_xTaskGetApplicationTaskTag_Unpriv
-MPU_xTaskGetApplicationTaskTag_Priv
-        pop {r0}
-        b MPU_xTaskGetApplicationTaskTagImpl
-MPU_xTaskGetApplicationTaskTag_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetApplicationTaskTagImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-}
+                push {
+                r0
+            }
+            mrs r0, control
+            tst r0, # 1
+            bne MPU_xTaskGetApplicationTaskTag_Unpriv
+            MPU_xTaskGetApplicationTaskTag_Priv
+                pop {
+                r0
+            }
+            b MPU_xTaskGetApplicationTaskTagImpl
+            MPU_xTaskGetApplicationTaskTag_Unpriv
+                pop {
+                r0
+            }
+            svc # portSVC_SYSTEM_CALL_ENTER
+            bl MPU_xTaskGetApplicationTaskTagImpl
+            svc # portSVC_SYSTEM_CALL_EXIT
+            bx lr
+        }
 
-#endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
+    #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+    #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
 
-void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
-                                            BaseType_t xIndex,
-                                            void * pvValue ) FREERTOS_SYSTEM_CALL;
+        void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
+                                                    BaseType_t xIndex,
+                                                    void * pvValue ) FREERTOS_SYSTEM_CALL;
 
-__asm void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
-                                                  BaseType_t xIndex,
-                                                  void * pvValue ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_vTaskSetThreadLocalStoragePointerImpl
+        __asm void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
+                                                          BaseType_t xIndex,
+                                                          void * pvValue ) /* FREERTOS_SYSTEM_CALL */
+        {
+            PRESERVE8
+            extern MPU_vTaskSetThreadLocalStoragePointerImpl
 
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv
-MPU_vTaskSetThreadLocalStoragePointer_Priv
-        pop {r0}
-        b MPU_vTaskSetThreadLocalStoragePointerImpl
-MPU_vTaskSetThreadLocalStoragePointer_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSetThreadLocalStoragePointerImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-}
+                push {
+                r0
+            }
+            mrs r0, control
+            tst r0, # 1
+            bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv
+            MPU_vTaskSetThreadLocalStoragePointer_Priv
+                pop {
+                r0
+            }
+            b MPU_vTaskSetThreadLocalStoragePointerImpl
+            MPU_vTaskSetThreadLocalStoragePointer_Unpriv
+                pop {
+                r0
+            }
+            svc # portSVC_SYSTEM_CALL_ENTER
+            bl MPU_vTaskSetThreadLocalStoragePointerImpl
+            svc # portSVC_SYSTEM_CALL_EXIT
+            bx lr
+        }
 
-#endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
+    #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+    #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
 
-void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
-                                               BaseType_t xIndex ) FREERTOS_SYSTEM_CALL;
+        void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
+                                                       BaseType_t xIndex ) FREERTOS_SYSTEM_CALL;
 
-__asm void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
-                                                     BaseType_t xIndex ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_pvTaskGetThreadLocalStoragePointerImpl
+        __asm void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
+                                                             BaseType_t xIndex ) /* FREERTOS_SYSTEM_CALL */
+        {
+            PRESERVE8
+            extern MPU_pvTaskGetThreadLocalStoragePointerImpl
 
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv
-MPU_pvTaskGetThreadLocalStoragePointer_Priv
-        pop {r0}
-        b MPU_pvTaskGetThreadLocalStoragePointerImpl
-MPU_pvTaskGetThreadLocalStoragePointer_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pvTaskGetThreadLocalStoragePointerImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-}
+                push {
+                r0
+            }
+            mrs r0, control
+            tst r0, # 1
+            bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv
+            MPU_pvTaskGetThreadLocalStoragePointer_Priv
+                pop {
+                r0
+            }
+            b MPU_pvTaskGetThreadLocalStoragePointerImpl
+            MPU_pvTaskGetThreadLocalStoragePointer_Unpriv
+                pop {
+                r0
+            }
+            svc # portSVC_SYSTEM_CALL_ENTER
+            bl MPU_pvTaskGetThreadLocalStoragePointerImpl
+            svc # portSVC_SYSTEM_CALL_EXIT
+            bx lr
+        }
 
-#endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
+    #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
-                                      const UBaseType_t uxArraySize,
-                                      configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) FREERTOS_SYSTEM_CALL;
+        UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
+                                              const UBaseType_t uxArraySize,
+                                              configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) FREERTOS_SYSTEM_CALL;
 
-__asm UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
-                                            const UBaseType_t uxArraySize,
-                                            configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_uxTaskGetSystemStateImpl
+        __asm UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
+                                                    const UBaseType_t uxArraySize,
+                                                    configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* FREERTOS_SYSTEM_CALL */
+        {
+            PRESERVE8
+            extern MPU_uxTaskGetSystemStateImpl
 
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_uxTaskGetSystemState_Unpriv
-MPU_uxTaskGetSystemState_Priv
-        pop {r0}
-        b MPU_uxTaskGetSystemStateImpl
-MPU_uxTaskGetSystemState_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetSystemStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-}
+                push {
+                r0
+            }
+            mrs r0, control
+            tst r0, # 1
+            bne MPU_uxTaskGetSystemState_Unpriv
+            MPU_uxTaskGetSystemState_Priv
+                pop {
+                r0
+            }
+            b MPU_uxTaskGetSystemStateImpl
+            MPU_uxTaskGetSystemState_Unpriv
+                pop {
+                r0
+            }
+            svc # portSVC_SYSTEM_CALL_ENTER
+            bl MPU_uxTaskGetSystemStateImpl
+            svc # portSVC_SYSTEM_CALL_EXIT
+            bx lr
+        }
 
-#endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
+    #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
+    #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
 
-UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+        UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
 
-__asm UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_uxTaskGetStackHighWaterMarkImpl
+        __asm UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
+        {
+            PRESERVE8
+            extern MPU_uxTaskGetStackHighWaterMarkImpl
 
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_uxTaskGetStackHighWaterMark_Unpriv
-MPU_uxTaskGetStackHighWaterMark_Priv
-        pop {r0}
-        b MPU_uxTaskGetStackHighWaterMarkImpl
-MPU_uxTaskGetStackHighWaterMark_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetStackHighWaterMarkImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-}
+                push {
+                r0
+            }
+            mrs r0, control
+            tst r0, # 1
+            bne MPU_uxTaskGetStackHighWaterMark_Unpriv
+            MPU_uxTaskGetStackHighWaterMark_Priv
+                pop {
+                r0
+            }
+            b MPU_uxTaskGetStackHighWaterMarkImpl
+            MPU_uxTaskGetStackHighWaterMark_Unpriv
+                pop {
+                r0
+            }
+            svc # portSVC_SYSTEM_CALL_ENTER
+            bl MPU_uxTaskGetStackHighWaterMarkImpl
+            svc # portSVC_SYSTEM_CALL_EXIT
+            bx lr
+        }
 
-#endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */
+    #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
+    #if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
 
-configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+        configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
 
-__asm configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_uxTaskGetStackHighWaterMark2Impl
+        __asm configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
+        {
+            PRESERVE8
+            extern MPU_uxTaskGetStackHighWaterMark2Impl
 
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_uxTaskGetStackHighWaterMark2_Unpriv
-MPU_uxTaskGetStackHighWaterMark2_Priv
-        pop {r0}
-        b MPU_uxTaskGetStackHighWaterMark2Impl
-MPU_uxTaskGetStackHighWaterMark2_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetStackHighWaterMark2Impl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-}
+                push {
+                r0
+            }
+            mrs r0, control
+            tst r0, # 1
+            bne MPU_uxTaskGetStackHighWaterMark2_Unpriv
+            MPU_uxTaskGetStackHighWaterMark2_Priv
+                pop {
+                r0
+            }
+            b MPU_uxTaskGetStackHighWaterMark2Impl
+            MPU_uxTaskGetStackHighWaterMark2_Unpriv
+                pop {
+                r0
+            }
+            svc # portSVC_SYSTEM_CALL_ENTER
+            bl MPU_uxTaskGetStackHighWaterMark2Impl
+            svc # portSVC_SYSTEM_CALL_EXIT
+            bx lr
+        }
 
-#endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */
+    #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
+    #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
 
-TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) FREERTOS_SYSTEM_CALL;
+        TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) FREERTOS_SYSTEM_CALL;
 
-__asm TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_xTaskGetCurrentTaskHandleImpl
+        __asm TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* FREERTOS_SYSTEM_CALL */
+        {
+            PRESERVE8
+            extern MPU_xTaskGetCurrentTaskHandleImpl
 
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_xTaskGetCurrentTaskHandle_Unpriv
-MPU_xTaskGetCurrentTaskHandle_Priv
-        pop {r0}
-        b MPU_xTaskGetCurrentTaskHandleImpl
-MPU_xTaskGetCurrentTaskHandle_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetCurrentTaskHandleImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-}
+                push {
+                r0
+            }
+            mrs r0, control
+            tst r0, # 1
+            bne MPU_xTaskGetCurrentTaskHandle_Unpriv
+            MPU_xTaskGetCurrentTaskHandle_Priv
+                pop {
+                r0
+            }
+            b MPU_xTaskGetCurrentTaskHandleImpl
+            MPU_xTaskGetCurrentTaskHandle_Unpriv
+                pop {
+                r0
+            }
+            svc # portSVC_SYSTEM_CALL_ENTER
+            bl MPU_xTaskGetCurrentTaskHandleImpl
+            svc # portSVC_SYSTEM_CALL_EXIT
+            bx lr
+        }
 
-#endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
+    #endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( INCLUDE_xTaskGetSchedulerState == 1 )
+    #if ( INCLUDE_xTaskGetSchedulerState == 1 )
 
-BaseType_t MPU_xTaskGetSchedulerState( void ) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGetSchedulerState( void ) FREERTOS_SYSTEM_CALL;
 
-__asm BaseType_t MPU_xTaskGetSchedulerState( void ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_xTaskGetSchedulerStateImpl
+        __asm BaseType_t MPU_xTaskGetSchedulerState( void ) /* FREERTOS_SYSTEM_CALL */
+        {
+            PRESERVE8
+            extern MPU_xTaskGetSchedulerStateImpl
 
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_xTaskGetSchedulerState_Unpriv
-MPU_xTaskGetSchedulerState_Priv
-        pop {r0}
-        b MPU_xTaskGetSchedulerStateImpl
-MPU_xTaskGetSchedulerState_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetSchedulerStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-}
+                push {
+                r0
+            }
+            mrs r0, control
+            tst r0, # 1
+            bne MPU_xTaskGetSchedulerState_Unpriv
+            MPU_xTaskGetSchedulerState_Priv
+                pop {
+                r0
+            }
+            b MPU_xTaskGetSchedulerStateImpl
+            MPU_xTaskGetSchedulerState_Unpriv
+                pop {
+                r0
+            }
+            svc # portSVC_SYSTEM_CALL_ENTER
+            bl MPU_xTaskGetSchedulerStateImpl
+            svc # portSVC_SYSTEM_CALL_EXIT
+            bx lr
+        }
 
-#endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */
+    #endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */
 /*-----------------------------------------------------------*/
 
-void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) FREERTOS_SYSTEM_CALL;
+    void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) FREERTOS_SYSTEM_CALL;
 
-__asm void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_vTaskSetTimeOutStateImpl
+    __asm void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* FREERTOS_SYSTEM_CALL */
+    {
+        PRESERVE8
+        extern MPU_vTaskSetTimeOutStateImpl
 
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_vTaskSetTimeOutState_Unpriv
-MPU_vTaskSetTimeOutState_Priv
-        pop {r0}
+            push {
+            r0
+        }
+        mrs r0, control
+        tst r0, # 1
+        bne MPU_vTaskSetTimeOutState_Unpriv
+        MPU_vTaskSetTimeOutState_Priv
+            pop {
+            r0
+        }
         b MPU_vTaskSetTimeOutStateImpl
-MPU_vTaskSetTimeOutState_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
+        MPU_vTaskSetTimeOutState_Unpriv
+            pop {
+            r0
+        }
+        svc # portSVC_SYSTEM_CALL_ENTER
         bl MPU_vTaskSetTimeOutStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
+        svc # portSVC_SYSTEM_CALL_EXIT
         bx lr
-}
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
-                                     TickType_t * const pxTicksToWait ) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
+                                         TickType_t * const pxTicksToWait ) FREERTOS_SYSTEM_CALL;
 
-__asm BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
-                                     TickType_t * const pxTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_xTaskCheckForTimeOutImpl
+    __asm BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
+                                               TickType_t * const pxTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+    {
+        PRESERVE8
+        extern MPU_xTaskCheckForTimeOutImpl
 
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_xTaskCheckForTimeOut_Unpriv
-MPU_xTaskCheckForTimeOut_Priv
-        pop {r0}
+            push {
+            r0
+        }
+        mrs r0, control
+        tst r0, # 1
+        bne MPU_xTaskCheckForTimeOut_Unpriv
+        MPU_xTaskCheckForTimeOut_Priv
+            pop {
+            r0
+        }
         b MPU_xTaskCheckForTimeOutImpl
-MPU_xTaskCheckForTimeOut_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
+        MPU_xTaskCheckForTimeOut_Unpriv
+            pop {
+            r0
+        }
+        svc # portSVC_SYSTEM_CALL_ENTER
         bl MPU_xTaskCheckForTimeOutImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
+        svc # portSVC_SYSTEM_CALL_EXIT
         bx lr
-}
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                   UBaseType_t uxIndexToNotify,
-                                   uint32_t ulValue,
-                                   eNotifyAction eAction,
-                                   uint32_t * pulPreviousNotificationValue ) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
+                                           UBaseType_t uxIndexToNotify,
+                                           uint32_t ulValue,
+                                           eNotifyAction eAction,
+                                           uint32_t * pulPreviousNotificationValue ) FREERTOS_SYSTEM_CALL;
 
-__asm BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                         UBaseType_t uxIndexToNotify,
-                                         uint32_t ulValue,
-                                         eNotifyAction eAction,
-                                         uint32_t * pulPreviousNotificationValue ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_xTaskGenericNotifyImpl
+        __asm BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
+                                                 UBaseType_t uxIndexToNotify,
+                                                 uint32_t ulValue,
+                                                 eNotifyAction eAction,
+                                                 uint32_t * pulPreviousNotificationValue ) /* FREERTOS_SYSTEM_CALL */
+        {
+            PRESERVE8
+            extern MPU_xTaskGenericNotifyImpl
 
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_xTaskGenericNotify_Unpriv
-MPU_xTaskGenericNotify_Priv
-        pop {r0}
-        b MPU_xTaskGenericNotifyImpl
-MPU_xTaskGenericNotify_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTaskGenericNotifyImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-}
+                push {
+                r0
+            }
+            mrs r0, control
+            tst r0, # 1
+            bne MPU_xTaskGenericNotify_Unpriv
+            MPU_xTaskGenericNotify_Priv
+                pop {
+                r0
+            }
+            b MPU_xTaskGenericNotifyImpl
+            MPU_xTaskGenericNotify_Unpriv
+                pop {
+                r0
+            }
+            svc # portSVC_SYSTEM_CALL_ENTER_1
+            bl MPU_xTaskGenericNotifyImpl
+            svc # portSVC_SYSTEM_CALL_EXIT
+            bx lr
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                       uint32_t ulBitsToClearOnEntry,
-                                       uint32_t ulBitsToClearOnExit,
-                                       uint32_t * pulNotificationValue,
-                                       TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
+                                               uint32_t ulBitsToClearOnEntry,
+                                               uint32_t ulBitsToClearOnExit,
+                                               uint32_t * pulNotificationValue,
+                                               TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
 
-__asm BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                             uint32_t ulBitsToClearOnEntry,
-                                             uint32_t ulBitsToClearOnExit,
-                                             uint32_t * pulNotificationValue,
-                                             TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_xTaskGenericNotifyWaitImpl
+        __asm BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
+                                                     uint32_t ulBitsToClearOnEntry,
+                                                     uint32_t ulBitsToClearOnExit,
+                                                     uint32_t * pulNotificationValue,
+                                                     TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+        {
+            PRESERVE8
+            extern MPU_xTaskGenericNotifyWaitImpl
 
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_xTaskGenericNotifyWait_Unpriv
-MPU_xTaskGenericNotifyWait_Priv
-        pop {r0}
-        b MPU_xTaskGenericNotifyWaitImpl
-MPU_xTaskGenericNotifyWait_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTaskGenericNotifyWaitImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-}
+                push {
+                r0
+            }
+            mrs r0, control
+            tst r0, # 1
+            bne MPU_xTaskGenericNotifyWait_Unpriv
+            MPU_xTaskGenericNotifyWait_Priv
+                pop {
+                r0
+            }
+            b MPU_xTaskGenericNotifyWaitImpl
+            MPU_xTaskGenericNotifyWait_Unpriv
+                pop {
+                r0
+            }
+            svc # portSVC_SYSTEM_CALL_ENTER_1
+            bl MPU_xTaskGenericNotifyWaitImpl
+            svc # portSVC_SYSTEM_CALL_EXIT
+            bx lr
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
-                                      BaseType_t xClearCountOnExit,
-                                      TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+        uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
+                                              BaseType_t xClearCountOnExit,
+                                              TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
 
-__asm uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
-                                            BaseType_t xClearCountOnExit,
-                                            TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_ulTaskGenericNotifyTakeImpl
+        __asm uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
+                                                    BaseType_t xClearCountOnExit,
+                                                    TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+        {
+            PRESERVE8
+            extern MPU_ulTaskGenericNotifyTakeImpl
 
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_ulTaskGenericNotifyTake_Unpriv
-MPU_ulTaskGenericNotifyTake_Priv
-        pop {r0}
-        b MPU_ulTaskGenericNotifyTakeImpl
-MPU_ulTaskGenericNotifyTake_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGenericNotifyTakeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-}
+                push {
+                r0
+            }
+            mrs r0, control
+            tst r0, # 1
+            bne MPU_ulTaskGenericNotifyTake_Unpriv
+            MPU_ulTaskGenericNotifyTake_Priv
+                pop {
+                r0
+            }
+            b MPU_ulTaskGenericNotifyTakeImpl
+            MPU_ulTaskGenericNotifyTake_Unpriv
+                pop {
+                r0
+            }
+            svc # portSVC_SYSTEM_CALL_ENTER
+            bl MPU_ulTaskGenericNotifyTakeImpl
+            svc # portSVC_SYSTEM_CALL_EXIT
+            bx lr
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
-                                             UBaseType_t uxIndexToClear ) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
+                                                     UBaseType_t uxIndexToClear ) FREERTOS_SYSTEM_CALL;
 
-__asm BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
-                                                   UBaseType_t uxIndexToClear ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_xTaskGenericNotifyStateClearImpl
+        __asm BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
+                                                           UBaseType_t uxIndexToClear ) /* FREERTOS_SYSTEM_CALL */
+        {
+            PRESERVE8
+            extern MPU_xTaskGenericNotifyStateClearImpl
 
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_xTaskGenericNotifyStateClear_Unpriv
-MPU_xTaskGenericNotifyStateClear_Priv
-        pop {r0}
-        b MPU_xTaskGenericNotifyStateClearImpl
-MPU_xTaskGenericNotifyStateClear_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGenericNotifyStateClearImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-}
+                push {
+                r0
+            }
+            mrs r0, control
+            tst r0, # 1
+            bne MPU_xTaskGenericNotifyStateClear_Unpriv
+            MPU_xTaskGenericNotifyStateClear_Priv
+                pop {
+                r0
+            }
+            b MPU_xTaskGenericNotifyStateClearImpl
+            MPU_xTaskGenericNotifyStateClear_Unpriv
+                pop {
+                r0
+            }
+            svc # portSVC_SYSTEM_CALL_ENTER
+            bl MPU_xTaskGenericNotifyStateClearImpl
+            svc # portSVC_SYSTEM_CALL_EXIT
+            bx lr
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
-                                            UBaseType_t uxIndexToClear,
-                                            uint32_t ulBitsToClear ) FREERTOS_SYSTEM_CALL;
+        uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
+                                                    UBaseType_t uxIndexToClear,
+                                                    uint32_t ulBitsToClear ) FREERTOS_SYSTEM_CALL;
 
-__asm uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
-                                                  UBaseType_t uxIndexToClear,
-                                                  uint32_t ulBitsToClear ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_ulTaskGenericNotifyValueClearImpl
+        __asm uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
+                                                          UBaseType_t uxIndexToClear,
+                                                          uint32_t ulBitsToClear ) /* FREERTOS_SYSTEM_CALL */
+        {
+            PRESERVE8
+            extern MPU_ulTaskGenericNotifyValueClearImpl
 
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_ulTaskGenericNotifyValueClear_Unpriv
-MPU_ulTaskGenericNotifyValueClear_Priv
-        pop {r0}
-        b MPU_ulTaskGenericNotifyValueClearImpl
-MPU_ulTaskGenericNotifyValueClear_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGenericNotifyValueClearImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-}
+                push {
+                r0
+            }
+            mrs r0, control
+            tst r0, # 1
+            bne MPU_ulTaskGenericNotifyValueClear_Unpriv
+            MPU_ulTaskGenericNotifyValueClear_Priv
+                pop {
+                r0
+            }
+            b MPU_ulTaskGenericNotifyValueClearImpl
+            MPU_ulTaskGenericNotifyValueClear_Unpriv
+                pop {
+                r0
+            }
+            svc # portSVC_SYSTEM_CALL_ENTER
+            bl MPU_ulTaskGenericNotifyValueClearImpl
+            svc # portSVC_SYSTEM_CALL_EXIT
+            bx lr
+        }
 
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
-                                  const void * const pvItemToQueue,
-                                  TickType_t xTicksToWait,
-                                  const BaseType_t xCopyPosition ) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
+                                      const void * const pvItemToQueue,
+                                      TickType_t xTicksToWait,
+                                      const BaseType_t xCopyPosition ) FREERTOS_SYSTEM_CALL;
 
-__asm BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
-                                        const void * const pvItemToQueue,
-                                        TickType_t xTicksToWait,
-                                        const BaseType_t xCopyPosition ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_xQueueGenericSendImpl
+    __asm BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
+                                            const void * const pvItemToQueue,
+                                            TickType_t xTicksToWait,
+                                            const BaseType_t xCopyPosition ) /* FREERTOS_SYSTEM_CALL */
+    {
+        PRESERVE8
+        extern MPU_xQueueGenericSendImpl
 
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_xQueueGenericSend_Unpriv
-MPU_xQueueGenericSend_Priv
-        pop {r0}
+            push {
+            r0
+        }
+        mrs r0, control
+        tst r0, # 1
+        bne MPU_xQueueGenericSend_Unpriv
+        MPU_xQueueGenericSend_Priv
+            pop {
+            r0
+        }
         b MPU_xQueueGenericSendImpl
-MPU_xQueueGenericSend_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
+        MPU_xQueueGenericSend_Unpriv
+            pop {
+            r0
+        }
+        svc # portSVC_SYSTEM_CALL_ENTER
         bl MPU_xQueueGenericSendImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
+        svc # portSVC_SYSTEM_CALL_EXIT
         bx lr
-}
+    }
 /*-----------------------------------------------------------*/
 
-UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+    UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
 
-__asm UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_uxQueueMessagesWaitingImpl
+    __asm UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */
+    {
+        PRESERVE8
+        extern MPU_uxQueueMessagesWaitingImpl
 
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_uxQueueMessagesWaiting_Unpriv
-MPU_uxQueueMessagesWaiting_Priv
-        pop {r0}
+            push {
+            r0
+        }
+        mrs r0, control
+        tst r0, # 1
+        bne MPU_uxQueueMessagesWaiting_Unpriv
+        MPU_uxQueueMessagesWaiting_Priv
+            pop {
+            r0
+        }
         b MPU_uxQueueMessagesWaitingImpl
-MPU_uxQueueMessagesWaiting_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
+        MPU_uxQueueMessagesWaiting_Unpriv
+            pop {
+            r0
+        }
+        svc # portSVC_SYSTEM_CALL_ENTER
         bl MPU_uxQueueMessagesWaitingImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
+        svc # portSVC_SYSTEM_CALL_EXIT
         bx lr
-}
+    }
 /*-----------------------------------------------------------*/
 
-UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+    UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
 
-__asm UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_uxQueueSpacesAvailableImpl
+    __asm UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */
+    {
+        PRESERVE8
+        extern MPU_uxQueueSpacesAvailableImpl
 
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_uxQueueSpacesAvailable_Unpriv
-MPU_uxQueueSpacesAvailable_Priv
-        pop {r0}
+            push {
+            r0
+        }
+        mrs r0, control
+        tst r0, # 1
+        bne MPU_uxQueueSpacesAvailable_Unpriv
+        MPU_uxQueueSpacesAvailable_Priv
+            pop {
+            r0
+        }
         b MPU_uxQueueSpacesAvailableImpl
-MPU_uxQueueSpacesAvailable_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
+        MPU_uxQueueSpacesAvailable_Unpriv
+            pop {
+            r0
+        }
+        svc # portSVC_SYSTEM_CALL_ENTER
         bl MPU_uxQueueSpacesAvailableImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
+        svc # portSVC_SYSTEM_CALL_EXIT
         bx lr
-}
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
-                              void * const pvBuffer,
-                              TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
+                                  void * const pvBuffer,
+                                  TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
 
-__asm BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
-                                    void * const pvBuffer,
-                                    TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_xQueueReceiveImpl
+    __asm BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
+                                        void * const pvBuffer,
+                                        TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+    {
+        PRESERVE8
+        extern MPU_xQueueReceiveImpl
 
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_xQueueReceive_Unpriv
-MPU_xQueueReceive_Priv
-        pop {r0}
+            push {
+            r0
+        }
+        mrs r0, control
+        tst r0, # 1
+        bne MPU_xQueueReceive_Unpriv
+        MPU_xQueueReceive_Priv
+            pop {
+            r0
+        }
         b MPU_xQueueReceiveImpl
-MPU_xQueueReceive_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
+        MPU_xQueueReceive_Unpriv
+            pop {
+            r0
+        }
+        svc # portSVC_SYSTEM_CALL_ENTER
         bl MPU_xQueueReceiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
+        svc # portSVC_SYSTEM_CALL_EXIT
         bx lr
-}
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
-                           void * const pvBuffer,
-                           TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
+                               void * const pvBuffer,
+                               TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
 
-__asm BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
-                                 void * const pvBuffer,
-                                 TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_xQueuePeekImpl
+    __asm BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
+                                     void * const pvBuffer,
+                                     TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+    {
+        PRESERVE8
+        extern MPU_xQueuePeekImpl
 
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_xQueuePeek_Unpriv
-MPU_xQueuePeek_Priv
-        pop {r0}
+            push {
+            r0
+        }
+        mrs r0, control
+        tst r0, # 1
+        bne MPU_xQueuePeek_Unpriv
+        MPU_xQueuePeek_Priv
+            pop {
+            r0
+        }
         b MPU_xQueuePeekImpl
-MPU_xQueuePeek_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
+        MPU_xQueuePeek_Unpriv
+            pop {
+            r0
+        }
+        svc # portSVC_SYSTEM_CALL_ENTER
         bl MPU_xQueuePeekImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
+        svc # portSVC_SYSTEM_CALL_EXIT
         bx lr
-}
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
-                                    TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
+                                        TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
 
-__asm BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
-                                          TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_xQueueSemaphoreTakeImpl
+    __asm BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
+                                              TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+    {
+        PRESERVE8
+        extern MPU_xQueueSemaphoreTakeImpl
 
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_xQueueSemaphoreTake_Unpriv
-MPU_xQueueSemaphoreTake_Priv
-        pop {r0}
+            push {
+            r0
+        }
+        mrs r0, control
+        tst r0, # 1
+        bne MPU_xQueueSemaphoreTake_Unpriv
+        MPU_xQueueSemaphoreTake_Priv
+            pop {
+            r0
+        }
         b MPU_xQueueSemaphoreTakeImpl
-MPU_xQueueSemaphoreTake_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
+        MPU_xQueueSemaphoreTake_Unpriv
+            pop {
+            r0
+        }
+        svc # portSVC_SYSTEM_CALL_ENTER
         bl MPU_xQueueSemaphoreTakeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
+        svc # portSVC_SYSTEM_CALL_EXIT
         bx lr
-}
+    }
 /*-----------------------------------------------------------*/
 
-#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+    #if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
 
-TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) FREERTOS_SYSTEM_CALL;
+        TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) FREERTOS_SYSTEM_CALL;
 
-__asm TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_xQueueGetMutexHolderImpl
+        __asm TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* FREERTOS_SYSTEM_CALL */
+        {
+            PRESERVE8
+            extern MPU_xQueueGetMutexHolderImpl
 
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_xQueueGetMutexHolder_Unpriv
-MPU_xQueueGetMutexHolder_Priv
-        pop {r0}
-        b MPU_xQueueGetMutexHolderImpl
-MPU_xQueueGetMutexHolder_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueGetMutexHolderImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-}
+                push {
+                r0
+            }
+            mrs r0, control
+            tst r0, # 1
+            bne MPU_xQueueGetMutexHolder_Unpriv
+            MPU_xQueueGetMutexHolder_Priv
+                pop {
+                r0
+            }
+            b MPU_xQueueGetMutexHolderImpl
+            MPU_xQueueGetMutexHolder_Unpriv
+                pop {
+                r0
+            }
+            svc # portSVC_SYSTEM_CALL_ENTER
+            bl MPU_xQueueGetMutexHolderImpl
+            svc # portSVC_SYSTEM_CALL_EXIT
+            bx lr
+        }
 
-#endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */
+    #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+    #if ( configUSE_RECURSIVE_MUTEXES == 1 )
 
-BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+        BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+                                                 TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+
+        __asm BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+                                                       TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+        {
+            PRESERVE8
+            extern MPU_xQueueTakeMutexRecursiveImpl
+
+                push {
+                r0
+            }
+            mrs r0, control
+            tst r0, # 1
+            bne MPU_xQueueTakeMutexRecursive_Unpriv
+            MPU_xQueueTakeMutexRecursive_Priv
+                pop {
+                r0
+            }
+            b MPU_xQueueTakeMutexRecursiveImpl
+            MPU_xQueueTakeMutexRecursive_Unpriv
+                pop {
+                r0
+            }
+            svc # portSVC_SYSTEM_CALL_ENTER
+            bl MPU_xQueueTakeMutexRecursiveImpl
+            svc # portSVC_SYSTEM_CALL_EXIT
+            bx lr
+        }
+
+    #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_RECURSIVE_MUTEXES == 1 )
+
+        BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) FREERTOS_SYSTEM_CALL;
+
+        __asm BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* FREERTOS_SYSTEM_CALL */
+        {
+            PRESERVE8
+            extern MPU_xQueueGiveMutexRecursiveImpl
+
+                push {
+                r0
+            }
+            mrs r0, control
+            tst r0, # 1
+            bne MPU_xQueueGiveMutexRecursive_Unpriv
+            MPU_xQueueGiveMutexRecursive_Priv
+                pop {
+                r0
+            }
+            b MPU_xQueueGiveMutexRecursiveImpl
+            MPU_xQueueGiveMutexRecursive_Unpriv
+                pop {
+                r0
+            }
+            svc # portSVC_SYSTEM_CALL_ENTER
+            bl MPU_xQueueGiveMutexRecursiveImpl
+            svc # portSVC_SYSTEM_CALL_EXIT
+            bx lr
+        }
+
+    #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_QUEUE_SETS == 1 )
+
+        QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
+                                                        const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+
+        __asm QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
+                                                              const TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+        {
+            PRESERVE8
+            extern MPU_xQueueSelectFromSetImpl
+
+                push {
+                r0
+            }
+            mrs r0, control
+            tst r0, # 1
+            bne MPU_xQueueSelectFromSet_Unpriv
+            MPU_xQueueSelectFromSet_Priv
+                pop {
+                r0
+            }
+            b MPU_xQueueSelectFromSetImpl
+            MPU_xQueueSelectFromSet_Unpriv
+                pop {
+                r0
+            }
+            svc # portSVC_SYSTEM_CALL_ENTER
+            bl MPU_xQueueSelectFromSetImpl
+            svc # portSVC_SYSTEM_CALL_EXIT
+            bx lr
+        }
+
+    #endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_QUEUE_SETS == 1 )
+
+        BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                                       QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL;
+
+        __asm BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                                             QueueSetHandle_t xQueueSet ) /* FREERTOS_SYSTEM_CALL */
+        {
+            PRESERVE8
+            extern MPU_xQueueAddToSetImpl
+
+                push {
+                r0
+            }
+            mrs r0, control
+            tst r0, # 1
+            bne MPU_xQueueAddToSet_Unpriv
+            MPU_xQueueAddToSet_Priv
+                pop {
+                r0
+            }
+            b MPU_xQueueAddToSetImpl
+            MPU_xQueueAddToSet_Unpriv
+                pop {
+                r0
+            }
+            svc # portSVC_SYSTEM_CALL_ENTER
+            bl MPU_xQueueAddToSetImpl
+            svc # portSVC_SYSTEM_CALL_EXIT
+            bx lr
+        }
+
+    #endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+        void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
+                                      const char * pcName ) FREERTOS_SYSTEM_CALL;
+
+        __asm void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
+                                            const char * pcName ) /* FREERTOS_SYSTEM_CALL */
+        {
+            PRESERVE8
+            extern MPU_vQueueAddToRegistryImpl
+
+                push {
+                r0
+            }
+            mrs r0, control
+            tst r0, # 1
+            bne MPU_vQueueAddToRegistry_Unpriv
+            MPU_vQueueAddToRegistry_Priv
+                pop {
+                r0
+            }
+            b MPU_vQueueAddToRegistryImpl
+            MPU_vQueueAddToRegistry_Unpriv
+                pop {
+                r0
+            }
+            svc # portSVC_SYSTEM_CALL_ENTER
+            bl MPU_vQueueAddToRegistryImpl
+            svc # portSVC_SYSTEM_CALL_EXIT
+            bx lr
+        }
+
+    #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+        void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+
+        __asm void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */
+        {
+            PRESERVE8
+            extern MPU_vQueueUnregisterQueueImpl
+
+                push {
+                r0
+            }
+            mrs r0, control
+            tst r0, # 1
+            bne MPU_vQueueUnregisterQueue_Unpriv
+            MPU_vQueueUnregisterQueue_Priv
+                pop {
+                r0
+            }
+            b MPU_vQueueUnregisterQueueImpl
+            MPU_vQueueUnregisterQueue_Unpriv
+                pop {
+                r0
+            }
+            svc # portSVC_SYSTEM_CALL_ENTER
+            bl MPU_vQueueUnregisterQueueImpl
+            svc # portSVC_SYSTEM_CALL_EXIT
+            bx lr
+        }
+
+    #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+        const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+
+        __asm const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */
+        {
+            PRESERVE8
+            extern MPU_pcQueueGetNameImpl
+
+                push {
+                r0
+            }
+            mrs r0, control
+            tst r0, # 1
+            bne MPU_pcQueueGetName_Unpriv
+            MPU_pcQueueGetName_Priv
+                pop {
+                r0
+            }
+            b MPU_pcQueueGetNameImpl
+            MPU_pcQueueGetName_Unpriv
+                pop {
+                r0
+            }
+            svc # portSVC_SYSTEM_CALL_ENTER
+            bl MPU_pcQueueGetNameImpl
+            svc # portSVC_SYSTEM_CALL_EXIT
+            bx lr
+        }
+
+    #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+
+        __asm void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
+        {
+            PRESERVE8
+            extern MPU_pvTimerGetTimerIDImpl
+
+                push {
+                r0
+            }
+            mrs r0, control
+            tst r0, # 1
+            bne MPU_pvTimerGetTimerID_Unpriv
+            MPU_pvTimerGetTimerID_Priv
+                pop {
+                r0
+            }
+            b MPU_pvTimerGetTimerIDImpl
+            MPU_pvTimerGetTimerID_Unpriv
+                pop {
+                r0
+            }
+            svc # portSVC_SYSTEM_CALL_ENTER
+            bl MPU_pvTimerGetTimerIDImpl
+            svc # portSVC_SYSTEM_CALL_EXIT
+            bx lr
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
+                                   void * pvNewID ) FREERTOS_SYSTEM_CALL;
+
+        __asm void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
+                                         void * pvNewID ) /* FREERTOS_SYSTEM_CALL */
+        {
+            PRESERVE8
+            extern MPU_vTimerSetTimerIDImpl
+
+                push {
+                r0
+            }
+            mrs r0, control
+            tst r0, # 1
+            bne MPU_vTimerSetTimerID_Unpriv
+            MPU_vTimerSetTimerID_Priv
+                pop {
+                r0
+            }
+            b MPU_vTimerSetTimerIDImpl
+            MPU_vTimerSetTimerID_Unpriv
+                pop {
+                r0
+            }
+            svc # portSVC_SYSTEM_CALL_ENTER
+            bl MPU_vTimerSetTimerIDImpl
+            svc # portSVC_SYSTEM_CALL_EXIT
+            bx lr
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+
+        __asm BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
+        {
+            PRESERVE8
+            extern MPU_xTimerIsTimerActiveImpl
+
+                push {
+                r0
+            }
+            mrs r0, control
+            tst r0, # 1
+            bne MPU_xTimerIsTimerActive_Unpriv
+            MPU_xTimerIsTimerActive_Priv
+                pop {
+                r0
+            }
+            b MPU_xTimerIsTimerActiveImpl
+            MPU_xTimerIsTimerActive_Unpriv
+                pop {
+                r0
+            }
+            svc # portSVC_SYSTEM_CALL_ENTER
+            bl MPU_xTimerIsTimerActiveImpl
+            svc # portSVC_SYSTEM_CALL_EXIT
+            bx lr
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) FREERTOS_SYSTEM_CALL;
+
+        __asm TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* FREERTOS_SYSTEM_CALL */
+        {
+            PRESERVE8
+            extern MPU_xTimerGetTimerDaemonTaskHandleImpl
+
+                push {
+                r0
+            }
+            mrs r0, control
+            tst r0, # 1
+            bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv
+            MPU_xTimerGetTimerDaemonTaskHandle_Priv
+                pop {
+                r0
+            }
+            b MPU_xTimerGetTimerDaemonTaskHandleImpl
+            MPU_xTimerGetTimerDaemonTaskHandle_Unpriv
+                pop {
+                r0
+            }
+            svc # portSVC_SYSTEM_CALL_ENTER
+            bl MPU_xTimerGetTimerDaemonTaskHandleImpl
+            svc # portSVC_SYSTEM_CALL_EXIT
+            bx lr
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                                     const BaseType_t xCommandID,
+                                                     const TickType_t xOptionalValue,
+                                                     BaseType_t * const pxHigherPriorityTaskWoken,
+                                                     const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+
+        __asm BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                                           const BaseType_t xCommandID,
+                                                           const TickType_t xOptionalValue,
+                                                           BaseType_t * const pxHigherPriorityTaskWoken,
+                                                           const TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+        {
+            PRESERVE8
+            extern MPU_xTimerGenericCommandFromTaskImpl
+
+                push {
+                r0
+            }
+            mrs r0, control
+            tst r0, # 1
+            bne MPU_xTimerGenericCommandFromTask_Unpriv
+            MPU_xTimerGenericCommandFromTask_Priv
+                pop {
+                r0
+            }
+            b MPU_xTimerGenericCommandFromTaskImpl
+            MPU_xTimerGenericCommandFromTask_Unpriv
+                pop {
+                r0
+            }
+            svc # portSVC_SYSTEM_CALL_ENTER_1
+            bl MPU_xTimerGenericCommandFromTaskImpl
+            svc # portSVC_SYSTEM_CALL_EXIT
+            bx lr
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+
+        __asm const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
+        {
+            PRESERVE8
+            extern MPU_pcTimerGetNameImpl
+
+                push {
+                r0
+            }
+            mrs r0, control
+            tst r0, # 1
+            bne MPU_pcTimerGetName_Unpriv
+            MPU_pcTimerGetName_Priv
+                pop {
+                r0
+            }
+            b MPU_pcTimerGetNameImpl
+            MPU_pcTimerGetName_Unpriv
+                pop {
+                r0
+            }
+            svc # portSVC_SYSTEM_CALL_ENTER
+            bl MPU_pcTimerGetNameImpl
+            svc # portSVC_SYSTEM_CALL_EXIT
+            bx lr
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
+                                      const BaseType_t uxAutoReload ) FREERTOS_SYSTEM_CALL;
+
+        __asm void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
+                                            const BaseType_t uxAutoReload ) /* FREERTOS_SYSTEM_CALL */
+        {
+            PRESERVE8
+            extern MPU_vTimerSetReloadModeImpl
+
+                push {
+                r0
+            }
+            mrs r0, control
+            tst r0, # 1
+            bne MPU_vTimerSetReloadMode_Unpriv
+            MPU_vTimerSetReloadMode_Priv
+                pop {
+                r0
+            }
+            b MPU_vTimerSetReloadModeImpl
+            MPU_vTimerSetReloadMode_Unpriv
+                pop {
+                r0
+            }
+            svc # portSVC_SYSTEM_CALL_ENTER
+            bl MPU_vTimerSetReloadModeImpl
+            svc # portSVC_SYSTEM_CALL_EXIT
+            bx lr
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+
+        __asm BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
+        {
+            PRESERVE8
+            extern MPU_xTimerGetReloadModeImpl
+
+                push {
+                r0
+            }
+            mrs r0, control
+            tst r0, # 1
+            bne MPU_xTimerGetReloadMode_Unpriv
+            MPU_xTimerGetReloadMode_Priv
+                pop {
+                r0
+            }
+            b MPU_xTimerGetReloadModeImpl
+            MPU_xTimerGetReloadMode_Unpriv
+                pop {
+                r0
+            }
+            svc # portSVC_SYSTEM_CALL_ENTER
+            bl MPU_xTimerGetReloadModeImpl
+            svc # portSVC_SYSTEM_CALL_EXIT
+            bx lr
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+
+        __asm UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
+        {
+            PRESERVE8
+            extern MPU_uxTimerGetReloadModeImpl
+
+                push {
+                r0
+            }
+            mrs r0, control
+            tst r0, # 1
+            bne MPU_uxTimerGetReloadMode_Unpriv
+            MPU_uxTimerGetReloadMode_Priv
+                pop {
+                r0
+            }
+            b MPU_uxTimerGetReloadModeImpl
+            MPU_uxTimerGetReloadMode_Unpriv
+                pop {
+                r0
+            }
+            svc # portSVC_SYSTEM_CALL_ENTER
+            bl MPU_uxTimerGetReloadModeImpl
+            svc # portSVC_SYSTEM_CALL_EXIT
+            bx lr
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+
+        __asm TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
+        {
+            PRESERVE8
+            extern MPU_xTimerGetPeriodImpl
+
+                push {
+                r0
+            }
+            mrs r0, control
+            tst r0, # 1
+            bne MPU_xTimerGetPeriod_Unpriv
+            MPU_xTimerGetPeriod_Priv
+                pop {
+                r0
+            }
+            b MPU_xTimerGetPeriodImpl
+            MPU_xTimerGetPeriod_Unpriv
+                pop {
+                r0
+            }
+            svc # portSVC_SYSTEM_CALL_ENTER
+            bl MPU_xTimerGetPeriodImpl
+            svc # portSVC_SYSTEM_CALL_EXIT
+            bx lr
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+
+        __asm TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
+        {
+            PRESERVE8
+            extern MPU_xTimerGetExpiryTimeImpl
+
+                push {
+                r0
+            }
+            mrs r0, control
+            tst r0, # 1
+            bne MPU_xTimerGetExpiryTime_Unpriv
+            MPU_xTimerGetExpiryTime_Priv
+                pop {
+                r0
+            }
+            b MPU_xTimerGetExpiryTimeImpl
+            MPU_xTimerGetExpiryTime_Unpriv
+                pop {
+                r0
+            }
+            svc # portSVC_SYSTEM_CALL_ENTER
+            bl MPU_xTimerGetExpiryTimeImpl
+            svc # portSVC_SYSTEM_CALL_EXIT
+            bx lr
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         const BaseType_t xClearOnExit,
+                                         const BaseType_t xWaitForAllBits,
                                          TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
 
-__asm BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+    __asm EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+                                               const EventBits_t uxBitsToWaitFor,
+                                               const BaseType_t xClearOnExit,
+                                               const BaseType_t xWaitForAllBits,
                                                TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_xQueueTakeMutexRecursiveImpl
+    {
+        PRESERVE8
+        extern MPU_xEventGroupWaitBitsImpl
 
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_xQueueTakeMutexRecursive_Unpriv
-MPU_xQueueTakeMutexRecursive_Priv
-        pop {r0}
-        b MPU_xQueueTakeMutexRecursiveImpl
-MPU_xQueueTakeMutexRecursive_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueTakeMutexRecursiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
+            push {
+            r0
+        }
+        mrs r0, control
+        tst r0, # 1
+        bne MPU_xEventGroupWaitBits_Unpriv
+        MPU_xEventGroupWaitBits_Priv
+            pop {
+            r0
+        }
+        b MPU_xEventGroupWaitBitsImpl
+        MPU_xEventGroupWaitBits_Unpriv
+            pop {
+            r0
+        }
+        svc # portSVC_SYSTEM_CALL_ENTER_1
+        bl MPU_xEventGroupWaitBitsImpl
+        svc # portSVC_SYSTEM_CALL_EXIT
         bx lr
-}
-
-#endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                          const EventBits_t uxBitsToClear ) FREERTOS_SYSTEM_CALL;
 
-BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) FREERTOS_SYSTEM_CALL;
+    __asm EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                                const EventBits_t uxBitsToClear ) /* FREERTOS_SYSTEM_CALL */
+    {
+        PRESERVE8
+        extern MPU_xEventGroupClearBitsImpl
 
-__asm BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_xQueueGiveMutexRecursiveImpl
-
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_xQueueGiveMutexRecursive_Unpriv
-MPU_xQueueGiveMutexRecursive_Priv
-        pop {r0}
-        b MPU_xQueueGiveMutexRecursiveImpl
-MPU_xQueueGiveMutexRecursive_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueGiveMutexRecursiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
+            push {
+            r0
+        }
+        mrs r0, control
+        tst r0, # 1
+        bne MPU_xEventGroupClearBits_Unpriv
+        MPU_xEventGroupClearBits_Priv
+            pop {
+            r0
+        }
+        b MPU_xEventGroupClearBitsImpl
+        MPU_xEventGroupClearBits_Unpriv
+            pop {
+            r0
+        }
+        svc # portSVC_SYSTEM_CALL_ENTER
+        bl MPU_xEventGroupClearBitsImpl
+        svc # portSVC_SYSTEM_CALL_EXIT
         bx lr
-}
-
-#endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_QUEUE_SETS == 1 )
+    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                        const EventBits_t uxBitsToSet ) FREERTOS_SYSTEM_CALL;
 
-QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
-                                                const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+    __asm EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                              const EventBits_t uxBitsToSet ) /* FREERTOS_SYSTEM_CALL */
+    {
+        PRESERVE8
+        extern MPU_xEventGroupSetBitsImpl
 
-__asm QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
-                                                      const TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_xQueueSelectFromSetImpl
-
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_xQueueSelectFromSet_Unpriv
-MPU_xQueueSelectFromSet_Priv
-        pop {r0}
-        b MPU_xQueueSelectFromSetImpl
-MPU_xQueueSelectFromSet_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueSelectFromSetImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
+            push {
+            r0
+        }
+        mrs r0, control
+        tst r0, # 1
+        bne MPU_xEventGroupSetBits_Unpriv
+        MPU_xEventGroupSetBits_Priv
+            pop {
+            r0
+        }
+        b MPU_xEventGroupSetBitsImpl
+        MPU_xEventGroupSetBits_Unpriv
+            pop {
+            r0
+        }
+        svc # portSVC_SYSTEM_CALL_ENTER
+        bl MPU_xEventGroupSetBitsImpl
+        svc # portSVC_SYSTEM_CALL_EXIT
         bx lr
-}
-
-#endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_QUEUE_SETS == 1 )
-
-BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
-                               QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL;
-
-__asm BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
-                                     QueueSetHandle_t xQueueSet ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_xQueueAddToSetImpl
-
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_xQueueAddToSet_Unpriv
-MPU_xQueueAddToSet_Priv
-        pop {r0}
-        b MPU_xQueueAddToSetImpl
-MPU_xQueueAddToSet_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueAddToSetImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-}
-
-#endif /* if ( configUSE_QUEUE_SETS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
-                              const char * pcName ) FREERTOS_SYSTEM_CALL;
-
-__asm void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
-                                    const char * pcName ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_vQueueAddToRegistryImpl
-
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_vQueueAddToRegistry_Unpriv
-MPU_vQueueAddToRegistry_Priv
-        pop {r0}
-        b MPU_vQueueAddToRegistryImpl
-MPU_vQueueAddToRegistry_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vQueueAddToRegistryImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-}
-
-#endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
-
-__asm void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_vQueueUnregisterQueueImpl
-
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_vQueueUnregisterQueue_Unpriv
-MPU_vQueueUnregisterQueue_Priv
-        pop {r0}
-        b MPU_vQueueUnregisterQueueImpl
-MPU_vQueueUnregisterQueue_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vQueueUnregisterQueueImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-}
-
-#endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
-
-__asm const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_pcQueueGetNameImpl
-
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_pcQueueGetName_Unpriv
-MPU_pcQueueGetName_Priv
-        pop {r0}
-        b MPU_pcQueueGetNameImpl
-MPU_pcQueueGetName_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pcQueueGetNameImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-}
-
-#endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
-
-__asm void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_pvTimerGetTimerIDImpl
-
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_pvTimerGetTimerID_Unpriv
-MPU_pvTimerGetTimerID_Priv
-        pop {r0}
-        b MPU_pvTimerGetTimerIDImpl
-MPU_pvTimerGetTimerID_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pvTimerGetTimerIDImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
-                           void * pvNewID ) FREERTOS_SYSTEM_CALL;
-
-__asm void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
-                                 void * pvNewID ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_vTimerSetTimerIDImpl
-
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_vTimerSetTimerID_Unpriv
-MPU_vTimerSetTimerID_Priv
-        pop {r0}
-        b MPU_vTimerSetTimerIDImpl
-MPU_vTimerSetTimerID_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTimerSetTimerIDImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
-
-__asm BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_xTimerIsTimerActiveImpl
-
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_xTimerIsTimerActive_Unpriv
-MPU_xTimerIsTimerActive_Priv
-        pop {r0}
-        b MPU_xTimerIsTimerActiveImpl
-MPU_xTimerIsTimerActive_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerIsTimerActiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) FREERTOS_SYSTEM_CALL;
-
-__asm TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_xTimerGetTimerDaemonTaskHandleImpl
-
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv
-MPU_xTimerGetTimerDaemonTaskHandle_Priv
-        pop {r0}
-        b MPU_xTimerGetTimerDaemonTaskHandleImpl
-MPU_xTimerGetTimerDaemonTaskHandle_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetTimerDaemonTaskHandleImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                             const BaseType_t xCommandID,
-                                             const TickType_t xOptionalValue,
-                                             BaseType_t * const pxHigherPriorityTaskWoken,
-                                             const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-
-__asm BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                                   const BaseType_t xCommandID,
-                                                   const TickType_t xOptionalValue,
-                                                   BaseType_t * const pxHigherPriorityTaskWoken,
-                                                   const TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_xTimerGenericCommandFromTaskImpl
-
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_xTimerGenericCommandFromTask_Unpriv
-MPU_xTimerGenericCommandFromTask_Priv
-        pop {r0}
-        b MPU_xTimerGenericCommandFromTaskImpl
-MPU_xTimerGenericCommandFromTask_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTimerGenericCommandFromTaskImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
-
-__asm const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_pcTimerGetNameImpl
-
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_pcTimerGetName_Unpriv
-MPU_pcTimerGetName_Priv
-        pop {r0}
-        b MPU_pcTimerGetNameImpl
-MPU_pcTimerGetName_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pcTimerGetNameImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                              const BaseType_t uxAutoReload ) FREERTOS_SYSTEM_CALL;
-
-__asm void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                                    const BaseType_t uxAutoReload ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_vTimerSetReloadModeImpl
-
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_vTimerSetReloadMode_Unpriv
-MPU_vTimerSetReloadMode_Priv
-        pop {r0}
-        b MPU_vTimerSetReloadModeImpl
-MPU_vTimerSetReloadMode_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTimerSetReloadModeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
-
-__asm BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_xTimerGetReloadModeImpl
-
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_xTimerGetReloadMode_Unpriv
-MPU_xTimerGetReloadMode_Priv
-        pop {r0}
-        b MPU_xTimerGetReloadModeImpl
-MPU_xTimerGetReloadMode_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetReloadModeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
-
-__asm UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_uxTimerGetReloadModeImpl
-
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_uxTimerGetReloadMode_Unpriv
-MPU_uxTimerGetReloadMode_Priv
-        pop {r0}
-        b MPU_uxTimerGetReloadModeImpl
-MPU_uxTimerGetReloadMode_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTimerGetReloadModeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
-
-__asm TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_xTimerGetPeriodImpl
-
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_xTimerGetPeriod_Unpriv
-MPU_xTimerGetPeriod_Priv
-        pop {r0}
-        b MPU_xTimerGetPeriodImpl
-MPU_xTimerGetPeriod_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetPeriodImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
-
-__asm TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_xTimerGetExpiryTimeImpl
-
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_xTimerGetExpiryTime_Unpriv
-MPU_xTimerGetExpiryTime_Priv
-        pop {r0}
-        b MPU_xTimerGetExpiryTimeImpl
-MPU_xTimerGetExpiryTime_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetExpiryTimeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-}
-
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                     const EventBits_t uxBitsToSet,
                                      const EventBits_t uxBitsToWaitFor,
-                                     const BaseType_t xClearOnExit,
-                                     const BaseType_t xWaitForAllBits,
                                      TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
 
-__asm EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+    __asm EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                           const EventBits_t uxBitsToSet,
                                            const EventBits_t uxBitsToWaitFor,
-                                           const BaseType_t xClearOnExit,
-                                           const BaseType_t xWaitForAllBits,
                                            TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_xEventGroupWaitBitsImpl
+    {
+        PRESERVE8
+        extern MPU_xEventGroupSyncImpl
 
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_xEventGroupWaitBits_Unpriv
-MPU_xEventGroupWaitBits_Priv
-        pop {r0}
-        b MPU_xEventGroupWaitBitsImpl
-MPU_xEventGroupWaitBits_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xEventGroupWaitBitsImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-}
-/*-----------------------------------------------------------*/
-
-EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                      const EventBits_t uxBitsToClear ) FREERTOS_SYSTEM_CALL;
-
-__asm EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                            const EventBits_t uxBitsToClear ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_xEventGroupClearBitsImpl
-
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_xEventGroupClearBits_Unpriv
-MPU_xEventGroupClearBits_Priv
-        pop {r0}
-        b MPU_xEventGroupClearBitsImpl
-MPU_xEventGroupClearBits_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xEventGroupClearBitsImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-}
-/*-----------------------------------------------------------*/
-
-EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                    const EventBits_t uxBitsToSet ) FREERTOS_SYSTEM_CALL;
-
-__asm EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                          const EventBits_t uxBitsToSet ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_xEventGroupSetBitsImpl
-
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_xEventGroupSetBits_Unpriv
-MPU_xEventGroupSetBits_Priv
-        pop {r0}
-        b MPU_xEventGroupSetBitsImpl
-MPU_xEventGroupSetBits_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xEventGroupSetBitsImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-}
-/*-----------------------------------------------------------*/
-
-EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                 const EventBits_t uxBitsToSet,
-                                 const EventBits_t uxBitsToWaitFor,
-                                 TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-
-__asm EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                       const EventBits_t uxBitsToSet,
-                                       const EventBits_t uxBitsToWaitFor,
-                                       TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_xEventGroupSyncImpl
-
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_xEventGroupSync_Unpriv
-MPU_xEventGroupSync_Priv
-        pop {r0}
+            push {
+            r0
+        }
+        mrs r0, control
+        tst r0, # 1
+        bne MPU_xEventGroupSync_Unpriv
+        MPU_xEventGroupSync_Priv
+            pop {
+            r0
+        }
         b MPU_xEventGroupSyncImpl
-MPU_xEventGroupSync_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
+        MPU_xEventGroupSync_Unpriv
+            pop {
+            r0
+        }
+        svc # portSVC_SYSTEM_CALL_ENTER
         bl MPU_xEventGroupSyncImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
+        svc # portSVC_SYSTEM_CALL_EXIT
         bx lr
-}
+    }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) FREERTOS_SYSTEM_CALL;
+        UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) FREERTOS_SYSTEM_CALL;
 
-__asm UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_uxEventGroupGetNumberImpl
+        __asm UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* FREERTOS_SYSTEM_CALL */
+        {
+            PRESERVE8
+            extern MPU_uxEventGroupGetNumberImpl
 
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_uxEventGroupGetNumber_Unpriv
-MPU_uxEventGroupGetNumber_Priv
-        pop {r0}
-        b MPU_uxEventGroupGetNumberImpl
-MPU_uxEventGroupGetNumber_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxEventGroupGetNumberImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-}
+                push {
+                r0
+            }
+            mrs r0, control
+            tst r0, # 1
+            bne MPU_uxEventGroupGetNumber_Unpriv
+            MPU_uxEventGroupGetNumber_Priv
+                pop {
+                r0
+            }
+            b MPU_uxEventGroupGetNumberImpl
+            MPU_uxEventGroupGetNumber_Unpriv
+                pop {
+                r0
+            }
+            svc # portSVC_SYSTEM_CALL_ENTER
+            bl MPU_uxEventGroupGetNumberImpl
+            svc # portSVC_SYSTEM_CALL_EXIT
+            bx lr
+        }
 
-#endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
-void MPU_vEventGroupSetNumber( void * xEventGroup,
-                               UBaseType_t uxEventGroupNumber ) FREERTOS_SYSTEM_CALL;
+        void MPU_vEventGroupSetNumber( void * xEventGroup,
+                                       UBaseType_t uxEventGroupNumber ) FREERTOS_SYSTEM_CALL;
 
-__asm void MPU_vEventGroupSetNumber( void * xEventGroup,
-                                     UBaseType_t uxEventGroupNumber ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_vEventGroupSetNumberImpl
+        __asm void MPU_vEventGroupSetNumber( void * xEventGroup,
+                                             UBaseType_t uxEventGroupNumber ) /* FREERTOS_SYSTEM_CALL */
+        {
+            PRESERVE8
+            extern MPU_vEventGroupSetNumberImpl
 
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_vEventGroupSetNumber_Unpriv
-MPU_vEventGroupSetNumber_Priv
-        pop {r0}
-        b MPU_vEventGroupSetNumberImpl
-MPU_vEventGroupSetNumber_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vEventGroupSetNumberImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
-}
+                push {
+                r0
+            }
+            mrs r0, control
+            tst r0, # 1
+            bne MPU_vEventGroupSetNumber_Unpriv
+            MPU_vEventGroupSetNumber_Priv
+                pop {
+                r0
+            }
+            b MPU_vEventGroupSetNumberImpl
+            MPU_vEventGroupSetNumber_Unpriv
+                pop {
+                r0
+            }
+            svc # portSVC_SYSTEM_CALL_ENTER
+            bl MPU_vEventGroupSetNumberImpl
+            svc # portSVC_SYSTEM_CALL_EXIT
+            bx lr
+        }
 
-#endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
 /*-----------------------------------------------------------*/
 
-size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                              const void * pvTxData,
-                              size_t xDataLengthBytes,
-                              TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                  const void * pvTxData,
+                                  size_t xDataLengthBytes,
+                                  TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
 
-__asm size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                                    const void * pvTxData,
-                                    size_t xDataLengthBytes,
-                                    TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_xStreamBufferSendImpl
+    __asm size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                        const void * pvTxData,
+                                        size_t xDataLengthBytes,
+                                        TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+    {
+        PRESERVE8
+        extern MPU_xStreamBufferSendImpl
 
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_xStreamBufferSend_Unpriv
-MPU_xStreamBufferSend_Priv
-        pop {r0}
+            push {
+            r0
+        }
+        mrs r0, control
+        tst r0, # 1
+        bne MPU_xStreamBufferSend_Unpriv
+        MPU_xStreamBufferSend_Priv
+            pop {
+            r0
+        }
         b MPU_xStreamBufferSendImpl
-MPU_xStreamBufferSend_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
+        MPU_xStreamBufferSend_Unpriv
+            pop {
+            r0
+        }
+        svc # portSVC_SYSTEM_CALL_ENTER
         bl MPU_xStreamBufferSendImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
+        svc # portSVC_SYSTEM_CALL_EXIT
         bx lr
-}
+    }
 /*-----------------------------------------------------------*/
 
-size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                 void * pvRxData,
-                                 size_t xBufferLengthBytes,
-                                 TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                     void * pvRxData,
+                                     size_t xBufferLengthBytes,
+                                     TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
 
-__asm size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                       void * pvRxData,
-                                       size_t xBufferLengthBytes,
-                                       TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_xStreamBufferReceiveImpl
+    __asm size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                           void * pvRxData,
+                                           size_t xBufferLengthBytes,
+                                           TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+    {
+        PRESERVE8
+        extern MPU_xStreamBufferReceiveImpl
 
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_xStreamBufferReceive_Unpriv
-MPU_xStreamBufferReceive_Priv
-        pop {r0}
+            push {
+            r0
+        }
+        mrs r0, control
+        tst r0, # 1
+        bne MPU_xStreamBufferReceive_Unpriv
+        MPU_xStreamBufferReceive_Priv
+            pop {
+            r0
+        }
         b MPU_xStreamBufferReceiveImpl
-MPU_xStreamBufferReceive_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
+        MPU_xStreamBufferReceive_Unpriv
+            pop {
+            r0
+        }
+        svc # portSVC_SYSTEM_CALL_ENTER
         bl MPU_xStreamBufferReceiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
+        svc # portSVC_SYSTEM_CALL_EXIT
         bx lr
-}
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
 
-__asm BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_xStreamBufferIsFullImpl
+    __asm BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
+    {
+        PRESERVE8
+        extern MPU_xStreamBufferIsFullImpl
 
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_xStreamBufferIsFull_Unpriv
-MPU_xStreamBufferIsFull_Priv
-        pop {r0}
+            push {
+            r0
+        }
+        mrs r0, control
+        tst r0, # 1
+        bne MPU_xStreamBufferIsFull_Unpriv
+        MPU_xStreamBufferIsFull_Priv
+            pop {
+            r0
+        }
         b MPU_xStreamBufferIsFullImpl
-MPU_xStreamBufferIsFull_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
+        MPU_xStreamBufferIsFull_Unpriv
+            pop {
+            r0
+        }
+        svc # portSVC_SYSTEM_CALL_ENTER
         bl MPU_xStreamBufferIsFullImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
+        svc # portSVC_SYSTEM_CALL_EXIT
         bx lr
-}
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
 
-__asm BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_xStreamBufferIsEmptyImpl
+    __asm BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
+    {
+        PRESERVE8
+        extern MPU_xStreamBufferIsEmptyImpl
 
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_xStreamBufferIsEmpty_Unpriv
-MPU_xStreamBufferIsEmpty_Priv
-        pop {r0}
+            push {
+            r0
+        }
+        mrs r0, control
+        tst r0, # 1
+        bne MPU_xStreamBufferIsEmpty_Unpriv
+        MPU_xStreamBufferIsEmpty_Priv
+            pop {
+            r0
+        }
         b MPU_xStreamBufferIsEmptyImpl
-MPU_xStreamBufferIsEmpty_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
+        MPU_xStreamBufferIsEmpty_Unpriv
+            pop {
+            r0
+        }
+        svc # portSVC_SYSTEM_CALL_ENTER
         bl MPU_xStreamBufferIsEmptyImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
+        svc # portSVC_SYSTEM_CALL_EXIT
         bx lr
-}
+    }
 /*-----------------------------------------------------------*/
 
-size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
 
-__asm size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_xStreamBufferSpacesAvailableImpl
+    __asm size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
+    {
+        PRESERVE8
+        extern MPU_xStreamBufferSpacesAvailableImpl
 
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_xStreamBufferSpacesAvailable_Unpriv
-MPU_xStreamBufferSpacesAvailable_Priv
-        pop {r0}
+            push {
+            r0
+        }
+        mrs r0, control
+        tst r0, # 1
+        bne MPU_xStreamBufferSpacesAvailable_Unpriv
+        MPU_xStreamBufferSpacesAvailable_Priv
+            pop {
+            r0
+        }
         b MPU_xStreamBufferSpacesAvailableImpl
-MPU_xStreamBufferSpacesAvailable_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
+        MPU_xStreamBufferSpacesAvailable_Unpriv
+            pop {
+            r0
+        }
+        svc # portSVC_SYSTEM_CALL_ENTER
         bl MPU_xStreamBufferSpacesAvailableImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
+        svc # portSVC_SYSTEM_CALL_EXIT
         bx lr
-}
+    }
 /*-----------------------------------------------------------*/
 
-size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
 
-__asm size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_xStreamBufferBytesAvailableImpl
+    __asm size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
+    {
+        PRESERVE8
+        extern MPU_xStreamBufferBytesAvailableImpl
 
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_xStreamBufferBytesAvailable_Unpriv
-MPU_xStreamBufferBytesAvailable_Priv
-        pop {r0}
+            push {
+            r0
+        }
+        mrs r0, control
+        tst r0, # 1
+        bne MPU_xStreamBufferBytesAvailable_Unpriv
+        MPU_xStreamBufferBytesAvailable_Priv
+            pop {
+            r0
+        }
         b MPU_xStreamBufferBytesAvailableImpl
-MPU_xStreamBufferBytesAvailable_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
+        MPU_xStreamBufferBytesAvailable_Unpriv
+            pop {
+            r0
+        }
+        svc # portSVC_SYSTEM_CALL_ENTER
         bl MPU_xStreamBufferBytesAvailableImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
+        svc # portSVC_SYSTEM_CALL_EXIT
         bx lr
-}
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                             size_t xTriggerLevel ) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                 size_t xTriggerLevel ) FREERTOS_SYSTEM_CALL;
 
-__asm BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                                   size_t xTriggerLevel ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_xStreamBufferSetTriggerLevelImpl
+    __asm BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                       size_t xTriggerLevel ) /* FREERTOS_SYSTEM_CALL */
+    {
+        PRESERVE8
+        extern MPU_xStreamBufferSetTriggerLevelImpl
 
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_xStreamBufferSetTriggerLevel_Unpriv
-MPU_xStreamBufferSetTriggerLevel_Priv
-        pop {r0}
+            push {
+            r0
+        }
+        mrs r0, control
+        tst r0, # 1
+        bne MPU_xStreamBufferSetTriggerLevel_Unpriv
+        MPU_xStreamBufferSetTriggerLevel_Priv
+            pop {
+            r0
+        }
         b MPU_xStreamBufferSetTriggerLevelImpl
-MPU_xStreamBufferSetTriggerLevel_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
+        MPU_xStreamBufferSetTriggerLevel_Unpriv
+            pop {
+            r0
+        }
+        svc # portSVC_SYSTEM_CALL_ENTER
         bl MPU_xStreamBufferSetTriggerLevelImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
+        svc # portSVC_SYSTEM_CALL_EXIT
         bx lr
-}
+    }
 /*-----------------------------------------------------------*/
 
-size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
 
-__asm size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
-{
-    PRESERVE8
-    extern MPU_xStreamBufferNextMessageLengthBytesImpl
+    __asm size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
+    {
+        PRESERVE8
+        extern MPU_xStreamBufferNextMessageLengthBytesImpl
 
-    push {r0}
-    mrs r0, control
-    tst r0, #1
-    bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv
-MPU_xStreamBufferNextMessageLengthBytes_Priv
-        pop {r0}
+            push {
+            r0
+        }
+        mrs r0, control
+        tst r0, # 1
+        bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv
+        MPU_xStreamBufferNextMessageLengthBytes_Priv
+            pop {
+            r0
+        }
         b MPU_xStreamBufferNextMessageLengthBytesImpl
-MPU_xStreamBufferNextMessageLengthBytes_Unpriv
-        pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
+        MPU_xStreamBufferNextMessageLengthBytes_Unpriv
+            pop {
+            r0
+        }
+        svc # portSVC_SYSTEM_CALL_ENTER
         bl MPU_xStreamBufferNextMessageLengthBytesImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
+        svc # portSVC_SYSTEM_CALL_EXIT
         bx lr
-}
+    }
 /*-----------------------------------------------------------*/
 
 #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
diff --git a/portable/RVDS/ARM_CM4_MPU/port.c b/portable/RVDS/ARM_CM4_MPU/port.c
old mode 100755
new mode 100644
index 7bcf6bc88..be087d823
--- a/portable/RVDS/ARM_CM4_MPU/port.c
+++ b/portable/RVDS/ARM_CM4_MPU/port.c
@@ -244,44 +244,47 @@ static void prvTriggerLazyStacking( void ) PRIVILEGED_FUNCTION;
 
 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
 
-    /**
-     * @brief Sets up the system call stack so that upon returning from
-     * SVC, the system call stack is used.
-     *
-     * It is used for the system calls with up to 4 parameters.
-     *
-     * @param pulTaskStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the system call stack so that upon returning from
+ * SVC, the system call stack is used.
+ *
+ * It is used for the system calls with up to 4 parameters.
+ *
+ * @param pulTaskStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallEnter( uint32_t * pulTaskStack,
+                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
 
-    /**
-     * @brief Sets up the system call stack so that upon returning from
-     * SVC, the system call stack is used.
-     *
-     * It is used for the system calls with 5 parameters.
-     *
-     * @param pulTaskStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the system call stack so that upon returning from
+ * SVC, the system call stack is used.
+ *
+ * It is used for the system calls with 5 parameters.
+ *
+ * @param pulTaskStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallEnter_1( uint32_t * pulTaskStack,
+                             uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
 
-    /**
-     * @brief Sets up the task stack so that upon returning from
-     * SVC, the task stack is used again.
-     *
-     * @param pulSystemCallStack The current SP when the SVC was raised.
-     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
-     */
-    void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Sets up the task stack so that upon returning from
+ * SVC, the task stack is used again.
+ *
+ * @param pulSystemCallStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+    void vSystemCallExit( uint32_t * pulSystemCallStack,
+                          uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
@@ -312,25 +315,26 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
         xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
         xMPUSettings->ulContext[ 0 ] = portINITIAL_CONTROL_IF_UNPRIVILEGED;
     }
-    xMPUSettings->ulContext[ 1 ] = 0x04040404; /* r4. */
-    xMPUSettings->ulContext[ 2 ] = 0x05050505; /* r5. */
-    xMPUSettings->ulContext[ 3 ] = 0x06060606; /* r6. */
-    xMPUSettings->ulContext[ 4 ] = 0x07070707; /* r7. */
-    xMPUSettings->ulContext[ 5 ] = 0x08080808; /* r8. */
-    xMPUSettings->ulContext[ 6 ] = 0x09090909; /* r9. */
-    xMPUSettings->ulContext[ 7 ] = 0x10101010; /* r10. */
-    xMPUSettings->ulContext[ 8 ] = 0x11111111; /* r11. */
-    xMPUSettings->ulContext[ 9 ] = portINITIAL_EXC_RETURN; /* EXC_RETURN. */
 
-    xMPUSettings->ulContext[ 10 ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
-    xMPUSettings->ulContext[ 11 ] = ( uint32_t ) pvParameters; /* r0. */
-    xMPUSettings->ulContext[ 12 ] = 0x01010101; /* r1. */
-    xMPUSettings->ulContext[ 13 ] = 0x02020202; /* r2. */
-    xMPUSettings->ulContext[ 14 ] = 0x03030303; /* r3. */
-    xMPUSettings->ulContext[ 15 ] = 0x12121212; /* r12. */
-    xMPUSettings->ulContext[ 16 ] = 0; /* LR. */
+    xMPUSettings->ulContext[ 1 ] = 0x04040404;                                        /* r4. */
+    xMPUSettings->ulContext[ 2 ] = 0x05050505;                                        /* r5. */
+    xMPUSettings->ulContext[ 3 ] = 0x06060606;                                        /* r6. */
+    xMPUSettings->ulContext[ 4 ] = 0x07070707;                                        /* r7. */
+    xMPUSettings->ulContext[ 5 ] = 0x08080808;                                        /* r8. */
+    xMPUSettings->ulContext[ 6 ] = 0x09090909;                                        /* r9. */
+    xMPUSettings->ulContext[ 7 ] = 0x10101010;                                        /* r10. */
+    xMPUSettings->ulContext[ 8 ] = 0x11111111;                                        /* r11. */
+    xMPUSettings->ulContext[ 9 ] = portINITIAL_EXC_RETURN;                            /* EXC_RETURN. */
+
+    xMPUSettings->ulContext[ 10 ] = ( uint32_t ) ( pxTopOfStack - 8 );                /* PSP with the hardware saved stack. */
+    xMPUSettings->ulContext[ 11 ] = ( uint32_t ) pvParameters;                        /* r0. */
+    xMPUSettings->ulContext[ 12 ] = 0x01010101;                                       /* r1. */
+    xMPUSettings->ulContext[ 13 ] = 0x02020202;                                       /* r2. */
+    xMPUSettings->ulContext[ 14 ] = 0x03030303;                                       /* r3. */
+    xMPUSettings->ulContext[ 15 ] = 0x12121212;                                       /* r12. */
+    xMPUSettings->ulContext[ 16 ] = 0;                                                /* LR. */
     xMPUSettings->ulContext[ 17 ] = ( ( uint32_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC. */
-    xMPUSettings->ulContext[ 18 ] = portINITIAL_XPSR; /* xPSR. */
+    xMPUSettings->ulContext[ 18 ] = portINITIAL_XPSR;                                 /* xPSR. */
 
     #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
     {
@@ -412,7 +416,7 @@ void vSVCHandler_C( uint32_t * pulParam )
                         /* *INDENT-ON* */
                     }
                     break;
-            #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
+                    #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
 
                 default: /* Unknown SVC call. */
                     break;
@@ -434,261 +438,266 @@ __asm void prvTriggerLazyStacking( void ) /* PRIVILEGED_FUNCTION */
 
 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
 
-void vSystemCallEnter( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulSystemCallStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i, r1;
-    extern uint32_t __syscalls_flash_start__;
-    extern uint32_t __syscalls_flash_end__;
-
-    ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallEnter( uint32_t * pulTaskStack,
+                           uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulSystemCallStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i, r1;
+        extern uint32_t __syscalls_flash_start__;
+        extern uint32_t __syscalls_flash_end__;
 
-        /* This is not NULL only for the duration of the system call. */
-        configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
 
-        if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            /* Extended frame i.e. FPU in use. */
-            ulStackFrameSize = 26;
-            prvTriggerLazyStacking();
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+
+            /* This is not NULL only for the duration of the system call. */
+            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+
+            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            {
+                /* Extended frame i.e. FPU in use. */
+                ulStackFrameSize = 26;
+                prvTriggerLazyStacking();
+            }
+            else
+            {
+                /* Standard frame i.e. FPU not in use. */
+                ulStackFrameSize = 8;
+            }
+
+            /* Make space on the system call stack for the stack frame. */
+            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulSystemCallStack[ i ] = pulTaskStack[ i ];
+            }
+
+            /* Use the pulSystemCallStack in thread mode. */
+            __asm
+            {
+                msr psp, pulSystemCallStack
+            };
+
+            /* Raise the privilege for the duration of the system call. */
+            __asm
+            {
+                mrs r1, control /* Obtain current control value. */
+                bic r1, # 1     /* Clear nPRIV bit. */
+                msr control, r1 /* Write back new control value. */
+            };
+
+            /* Remember the location where we should copy the stack frame when we exit from
+             * the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+
+            /* Store the value of the Link Register before the SVC was raised. We need to
+             * restore it when we exit from the system call. */
+            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+
+            /* Record if the hardware used padding to force the stack pointer
+             * to be double word aligned. */
+            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
+            {
+                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
+            }
+            else
+            {
+                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
+            }
+
+            /* We ensure in pxPortInitialiseStack that the system call stack is
+             * double word aligned and therefore, there is no need of padding.
+             * Clear the bit[9] of stacked xPSR. */
+            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
         }
-        else
-        {
-            /* Standard frame i.e. FPU not in use. */
-            ulStackFrameSize = 8;
-        }
-
-        /* Make space on the system call stack for the stack frame. */
-        pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulSystemCallStack[ i ] = pulTaskStack[ i ];
-        }
-
-        /* Use the pulSystemCallStack in thread mode. */
-        __asm
-        {
-            msr psp, pulSystemCallStack
-        };
-
-        /* Raise the privilege for the duration of the system call. */
-        __asm
-        {
-            mrs r1, control /* Obtain current control value. */
-            bic r1, #1      /* Clear nPRIV bit. */
-            msr control, r1 /* Write back new control value. */
-        };
-
-        /* Remember the location where we should copy the stack frame when we exit from
-         * the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-        /* Store the value of the Link Register before the SVC was raised. We need to
-         * restore it when we exit from the system call. */
-        pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-
-        /* Record if the hardware used padding to force the stack pointer
-         * to be double word aligned. */
-        if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-        {
-            pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-        }
-        else
-        {
-            pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-        }
-
-        /* We ensure in pxPortInitialiseStack that the system call stack is
-         * double word aligned and therefore, there is no need of padding.
-         * Clear the bit[9] of stacked xPSR. */
-        pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
     }
-}
 
 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
 
-void vSystemCallEnter_1( uint32_t * pulTaskStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulSystemCallStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i, r1;
-    extern uint32_t __syscalls_flash_start__;
-    extern uint32_t __syscalls_flash_end__;
-
-    ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallEnter_1( uint32_t * pulTaskStack,
+                             uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulSystemCallStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i, r1;
+        extern uint32_t __syscalls_flash_start__;
+        extern uint32_t __syscalls_flash_end__;
 
-        /* This is not NULL only for the duration of the system call. */
-        configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
 
-        if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            /* Extended frame i.e. FPU in use. */
-            ulStackFrameSize = 26;
-            prvTriggerLazyStacking();
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+
+            /* This is not NULL only for the duration of the system call. */
+            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
+
+            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            {
+                /* Extended frame i.e. FPU in use. */
+                ulStackFrameSize = 26;
+                prvTriggerLazyStacking();
+            }
+            else
+            {
+                /* Standard frame i.e. FPU not in use. */
+                ulStackFrameSize = 8;
+            }
+
+            /* Make space on the system call stack for the stack frame and
+             * the parameter passed on the stack. We only need to copy one
+             * parameter but we still reserve 2 spaces to keep the stack
+             * double word aligned. */
+            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulSystemCallStack[ i ] = pulTaskStack[ i ];
+            }
+
+            /* Copy the parameter which is passed the stack. */
+            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
+            {
+                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
+
+                /* Record if the hardware used padding to force the stack pointer
+                 * to be double word aligned. */
+                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
+            }
+            else
+            {
+                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
+
+                /* Record if the hardware used padding to force the stack pointer
+                 * to be double word aligned. */
+                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
+            }
+
+            /* Use the pulSystemCallStack in thread mode. */
+            __asm
+            {
+                msr psp, pulSystemCallStack
+            };
+
+            /* Raise the privilege for the duration of the system call. */
+            __asm
+            {
+                mrs r1, control /* Obtain current control value. */
+                bic r1, # 1     /* Clear nPRIV bit. */
+                msr control, r1 /* Write back new control value. */
+            };
+
+            /* Remember the location where we should copy the stack frame when we exit from
+             * the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+
+            /* Store the value of the Link Register before the SVC was raised. We need to
+             * restore it when we exit from the system call. */
+            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+
+            /* We ensure in pxPortInitialiseStack that the system call stack is
+             * double word aligned and therefore, there is no need of padding.
+             * Clear the bit[9] of stacked xPSR. */
+            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
         }
-        else
-        {
-            /* Standard frame i.e. FPU not in use. */
-            ulStackFrameSize = 8;
-        }
-
-        /* Make space on the system call stack for the stack frame and
-         * the parameter passed on the stack. We only need to copy one
-         * parameter but we still reserve 2 spaces to keep the stack
-         * double word aligned. */
-        pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulSystemCallStack[ i ] = pulTaskStack[ i ];
-        }
-
-        /* Copy the parameter which is passed the stack. */
-        if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-        {
-            pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
-            /* Record if the hardware used padding to force the stack pointer
-             * to be double word aligned. */
-            pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-        }
-        else
-        {
-            pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
-            /* Record if the hardware used padding to force the stack pointer
-             * to be double word aligned. */
-            pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-        }
-
-        /* Use the pulSystemCallStack in thread mode. */
-        __asm
-        {
-            msr psp, pulSystemCallStack
-        };
-
-        /* Raise the privilege for the duration of the system call. */
-        __asm
-        {
-            mrs r1, control /* Obtain current control value. */
-            bic r1, #1      /* Clear nPRIV bit. */
-            msr control, r1 /* Write back new control value. */
-        };
-
-        /* Remember the location where we should copy the stack frame when we exit from
-         * the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-        /* Store the value of the Link Register before the SVC was raised. We need to
-         * restore it when we exit from the system call. */
-        pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-
-        /* We ensure in pxPortInitialiseStack that the system call stack is
-         * double word aligned and therefore, there is no need of padding.
-         * Clear the bit[9] of stacked xPSR. */
-        pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
     }
-}
 
 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
 
-void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
-{
-    extern TaskHandle_t pxCurrentTCB;
-    xMPU_SETTINGS * pxMpuSettings;
-    uint32_t * pulTaskStack;
-    uint32_t ulStackFrameSize, ulSystemCallLocation, i, r1;
-    extern uint32_t __syscalls_flash_start__;
-    extern uint32_t __syscalls_flash_end__;
-
-    ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
-
-    /* If the request did not come from the system call section, do nothing. */
-    if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-        ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+    void vSystemCallExit( uint32_t * pulSystemCallStack,
+                          uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
     {
-        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-        pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulTaskStack;
+        uint32_t ulStackFrameSize, ulSystemCallLocation, i, r1;
+        extern uint32_t __syscalls_flash_start__;
+        extern uint32_t __syscalls_flash_end__;
 
-        if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+        ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
+
+        /* If the request did not come from the system call section, do nothing. */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
         {
-            /* Extended frame i.e. FPU in use. */
-            ulStackFrameSize = 26;
-            prvTriggerLazyStacking();
+            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+            pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
+
+            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
+            {
+                /* Extended frame i.e. FPU in use. */
+                ulStackFrameSize = 26;
+                prvTriggerLazyStacking();
+            }
+            else
+            {
+                /* Standard frame i.e. FPU not in use. */
+                ulStackFrameSize = 8;
+            }
+
+            /* Make space on the task stack for the stack frame. */
+            pulTaskStack = pulTaskStack - ulStackFrameSize;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulTaskStack[ i ] = pulSystemCallStack[ i ];
+            }
+
+            /* Use the pulTaskStack in thread mode. */
+            __asm
+            {
+                msr psp, pulTaskStack
+            };
+
+            /* Drop the privilege before returning to the thread mode. */
+            __asm
+            {
+                mrs r1, control /* Obtain current control value. */
+                orr r1, # 1     /* Set nPRIV bit. */
+                msr control, r1 /* Write back new control value. */
+            };
+
+            /* Restore the stacked link register to what it was at the time of
+             * system call entry. */
+            pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+
+            /* If the hardware used padding to force the stack pointer
+             * to be double word aligned, set the stacked xPSR bit[9],
+             * otherwise clear it. */
+            if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG )
+            {
+                pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK;
+            }
+            else
+            {
+                pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
+            }
+
+            /* This is not NULL only for the duration of the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
         }
-        else
-        {
-            /* Standard frame i.e. FPU not in use. */
-            ulStackFrameSize = 8;
-        }
-
-        /* Make space on the task stack for the stack frame. */
-        pulTaskStack = pulTaskStack - ulStackFrameSize;
-
-        /* Copy the stack frame. */
-        for( i = 0; i < ulStackFrameSize; i++ )
-        {
-            pulTaskStack[ i ] = pulSystemCallStack[ i ];
-        }
-
-        /* Use the pulTaskStack in thread mode. */
-        __asm
-        {
-            msr psp, pulTaskStack
-        };
-
-        /* Drop the privilege before returning to the thread mode. */
-        __asm
-        {
-            mrs r1, control /* Obtain current control value. */
-            orr r1, #1      /* Set nPRIV bit. */
-            msr control, r1 /* Write back new control value. */
-        };
-
-        /* Restore the stacked link register to what it was at the time of
-         * system call entry. */
-        pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
-
-        /* If the hardware used padding to force the stack pointer
-         * to be double word aligned, set the stacked xPSR bit[9],
-         * otherwise clear it. */
-        if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG )
-        {
-            pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK;
-        }
-        else
-        {
-            pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-        }
-
-        /* This is not NULL only for the duration of the system call. */
-        pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
     }
-}
 
 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
@@ -709,12 +718,12 @@ BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */
 
 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
 
-__asm void vPortSVCHandler( void )
-{
-    extern vSVCHandler_C
-    extern vSystemCallEnter
-    extern vSystemCallEnter_1
-    extern vSystemCallExit
+    __asm void vPortSVCHandler( void )
+    {
+        extern vSVCHandler_C
+        extern vSystemCallEnter
+        extern vSystemCallEnter_1
+        extern vSystemCallExit
 
 /* *INDENT-OFF* */
     PRESERVE8
@@ -746,13 +755,13 @@ syscall_exit
         mov r1, lr
         b vSystemCallExit
 /* *INDENT-ON* */
-}
+    }
 
 #else /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
-__asm void vPortSVCHandler( void )
-{
-    extern vSVCHandler_C
+    __asm void vPortSVCHandler( void )
+    {
+        extern vSVCHandler_C
 
 /* *INDENT-OFF* */
         PRESERVE8
@@ -769,7 +778,7 @@ __asm void vPortSVCHandler( void )
 
     b vSVCHandler_C
 /* *INDENT-ON* */
-}
+    }
 
 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
@@ -902,22 +911,22 @@ BaseType_t xPortStartScheduler( void )
         if( ulImplementedPrioBits == 8 )
         {
             /* When the hardware implements 8 priority bits, there is no way for
-            * the software to configure PRIGROUP to not have sub-priorities. As
-            * a result, the least significant bit is always used for sub-priority
-            * and there are 128 preemption priorities and 2 sub-priorities.
-            *
-            * This may cause some confusion in some cases - for example, if
-            * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
-            * priority interrupts will be masked in Critical Sections as those
-            * are at the same preemption priority. This may appear confusing as
-            * 4 is higher (numerically lower) priority than
-            * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
-            * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
-            * to 4, this confusion does not happen and the behaviour remains the same.
-            *
-            * The following assert ensures that the sub-priority bit in the
-            * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
-            * confusion. */
+             * the software to configure PRIGROUP to not have sub-priorities. As
+             * a result, the least significant bit is always used for sub-priority
+             * and there are 128 preemption priorities and 2 sub-priorities.
+             *
+             * This may cause some confusion in some cases - for example, if
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
+             * priority interrupts will be masked in Critical Sections as those
+             * are at the same preemption priority. This may appear confusing as
+             * 4 is higher (numerically lower) priority than
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
+             * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
+             * to 4, this confusion does not happen and the behaviour remains the same.
+             *
+             * The following assert ensures that the sub-priority bit in the
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
+             * confusion. */
             configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
             ulMaxPRIGROUPValue = 0;
         }
@@ -1024,7 +1033,7 @@ void vPortEnterCritical( void )
             portDISABLE_INTERRUPTS();
             uxCriticalNesting++;
         }
-    #else  /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */
+    #else /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */
         portDISABLE_INTERRUPTS();
         uxCriticalNesting++;
     #endif /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */
@@ -1062,7 +1071,7 @@ void vPortExitCritical( void )
                 portENABLE_INTERRUPTS();
             }
         }
-    #else  /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */
+    #else /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */
         configASSERT( uxCriticalNesting );
         uxCriticalNesting--;
 
@@ -1385,10 +1394,10 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
             ( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |
             ( portMPU_REGION_ENABLE );
 
-          xMPUSettings->xRegionSettings[ 0 ].ulRegionStartAddress = ( uint32_t ) __SRAM_segment_start__;
-          xMPUSettings->xRegionSettings[ 0 ].ulRegionEndAddress = ( uint32_t ) __SRAM_segment_end__;
-          xMPUSettings->xRegionSettings[ 0 ].ulRegionPermissions = ( tskMPU_READ_PERMISSION |
-                                                                     tskMPU_WRITE_PERMISSION );
+        xMPUSettings->xRegionSettings[ 0 ].ulRegionStartAddress = ( uint32_t ) __SRAM_segment_start__;
+        xMPUSettings->xRegionSettings[ 0 ].ulRegionEndAddress = ( uint32_t ) __SRAM_segment_end__;
+        xMPUSettings->xRegionSettings[ 0 ].ulRegionPermissions = ( tskMPU_READ_PERMISSION |
+                                                                   tskMPU_WRITE_PERMISSION );
 
         /* Invalidate user configurable regions. */
         for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
@@ -1450,11 +1459,13 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
                 xMPUSettings->xRegionSettings[ ul ].ulRegionStartAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress;
                 xMPUSettings->xRegionSettings[ ul ].ulRegionEndAddress = ( uint32_t ) ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1UL );
                 xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = 0UL;
+
                 if( ( ( xRegions[ lIndex ].ulParameters & portMPU_REGION_READ_ONLY ) == portMPU_REGION_READ_ONLY ) ||
-                    ( ( xRegions[lIndex].ulParameters & portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ) == portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ) )
+                    ( ( xRegions[ lIndex ].ulParameters & portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ) == portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ) )
                 {
                     xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = tskMPU_READ_PERMISSION;
                 }
+
                 if( ( xRegions[ lIndex ].ulParameters & portMPU_REGION_READ_WRITE ) == portMPU_REGION_READ_WRITE )
                 {
                     xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = ( tskMPU_READ_PERMISSION | tskMPU_WRITE_PERMISSION );
diff --git a/portable/RVDS/ARM_CM4_MPU/portmacro.h b/portable/RVDS/ARM_CM4_MPU/portmacro.h
index 20941571a..e67086a7f 100644
--- a/portable/RVDS/ARM_CM4_MPU/portmacro.h
+++ b/portable/RVDS/ARM_CM4_MPU/portmacro.h
@@ -62,7 +62,7 @@ typedef unsigned long    UBaseType_t;
 #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
     typedef uint16_t     TickType_t;
     #define portMAX_DELAY              ( TickType_t ) 0xffff
-#elif ( configTICK_TYPE_WIDTH_IN_BITS  == TICK_TYPE_WIDTH_32_BITS )
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
     typedef uint32_t     TickType_t;
     #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
@@ -70,13 +70,13 @@ typedef unsigned long    UBaseType_t;
  * not need to be guarded with a critical section. */
     #define portTICK_TYPE_IS_ATOMIC    1
 #else
-    #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+    #error "configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width."
 #endif
 
 /* Errata 837070 workaround must be enabled on Cortex-M7 r0p0
  * and r0p1 cores. */
 #ifndef configENABLE_ERRATA_837070_WORKAROUND
-    #define configENABLE_ERRATA_837070_WORKAROUND 0
+    #define configENABLE_ERRATA_837070_WORKAROUND    0
 #endif
 /*-----------------------------------------------------------*/
 
@@ -208,7 +208,7 @@ typedef struct MPU_REGION_SETTINGS
 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
 
     #ifndef configSYSTEM_CALL_STACK_SIZE
-        #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
+        #error "configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2."
     #endif
 
     typedef struct SYSTEM_CALL_STACK_INFO
@@ -221,11 +221,11 @@ typedef struct MPU_REGION_SETTINGS
 
 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
-#define MAX_CONTEXT_SIZE 52
+#define MAX_CONTEXT_SIZE                    52
 
 /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
-#define portSTACK_FRAME_HAS_PADDING_FLAG     ( 1UL << 0UL )
-#define portTASK_IS_PRIVILEGED_FLAG          ( 1UL << 1UL )
+#define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
+#define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
 typedef struct MPU_SETTINGS
 {
@@ -250,16 +250,16 @@ typedef struct MPU_SETTINGS
 /*-----------------------------------------------------------*/
 
 /* SVC numbers for various services. */
-#define portSVC_START_SCHEDULER     0
-#define portSVC_YIELD               1
-#define portSVC_RAISE_PRIVILEGE     2
-#define portSVC_SYSTEM_CALL_ENTER   3   /* System calls with upto 4 parameters. */
-#define portSVC_SYSTEM_CALL_ENTER_1 4   /* System calls with 5 parameters. */
-#define portSVC_SYSTEM_CALL_EXIT    5
+#define portSVC_START_SCHEDULER        0
+#define portSVC_YIELD                  1
+#define portSVC_RAISE_PRIVILEGE        2
+#define portSVC_SYSTEM_CALL_ENTER      3 /* System calls with upto 4 parameters. */
+#define portSVC_SYSTEM_CALL_ENTER_1    4 /* System calls with 5 parameters. */
+#define portSVC_SYSTEM_CALL_EXIT       5
 
 /* Scheduler utilities. */
 
-#define portYIELD()    __asm{ SVC portSVC_YIELD }
+#define portYIELD()    __asm { SVC portSVC_YIELD }
 #define portYIELD_WITHIN_API()                          \
     {                                                   \
         /* Set a PendSV to request a context switch. */ \
@@ -274,8 +274,10 @@ typedef struct MPU_SETTINGS
 
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )
-#define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+#define portEND_SWITCHING_ISR( xSwitchRequired )                                 \
+    do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
+    while( 0 )
+#define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
 /* Critical section management. */
@@ -300,7 +302,7 @@ extern void vPortExitCritical( void );
 
 /* Check the configuration. */
     #if ( configMAX_PRIORITIES > 32 )
-        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+        #error "configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice."
     #endif
 
 /* Store/clear the ready priorities in a bit map. */
@@ -365,7 +367,7 @@ extern BaseType_t xPortIsTaskPrivileged( void );
  *
  * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
  */
-#define portIS_TASK_PRIVILEGED()      xPortIsTaskPrivileged()
+#define portIS_TASK_PRIVILEGED()    xPortIsTaskPrivileged()
 /*-----------------------------------------------------------*/
 
 static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI )
@@ -469,7 +471,7 @@ static portFORCE_INLINE BaseType_t xPortIsInsideInterrupt( void )
 /*-----------------------------------------------------------*/
 
 #ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY
-    #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. https://www.FreeRTOS.org/FreeRTOS-V10.3.x.html"
+    #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. www.FreeRTOS.org/FreeRTOS-V10.3.x.html"
     #define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY    0
 #endif
 /*-----------------------------------------------------------*/
diff --git a/portable/RVDS/ARM_CM7/r0p1/port.c b/portable/RVDS/ARM_CM7/r0p1/port.c
old mode 100755
new mode 100644
index 8414acc99..a7dddc4eb
--- a/portable/RVDS/ARM_CM7/r0p1/port.c
+++ b/portable/RVDS/ARM_CM7/r0p1/port.c
@@ -360,22 +360,22 @@ BaseType_t xPortStartScheduler( void )
         if( ulImplementedPrioBits == 8 )
         {
             /* When the hardware implements 8 priority bits, there is no way for
-            * the software to configure PRIGROUP to not have sub-priorities. As
-            * a result, the least significant bit is always used for sub-priority
-            * and there are 128 preemption priorities and 2 sub-priorities.
-            *
-            * This may cause some confusion in some cases - for example, if
-            * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
-            * priority interrupts will be masked in Critical Sections as those
-            * are at the same preemption priority. This may appear confusing as
-            * 4 is higher (numerically lower) priority than
-            * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
-            * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
-            * to 4, this confusion does not happen and the behaviour remains the same.
-            *
-            * The following assert ensures that the sub-priority bit in the
-            * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
-            * confusion. */
+             * the software to configure PRIGROUP to not have sub-priorities. As
+             * a result, the least significant bit is always used for sub-priority
+             * and there are 128 preemption priorities and 2 sub-priorities.
+             *
+             * This may cause some confusion in some cases - for example, if
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
+             * priority interrupts will be masked in Critical Sections as those
+             * are at the same preemption priority. This may appear confusing as
+             * 4 is higher (numerically lower) priority than
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
+             * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
+             * to 4, this confusion does not happen and the behaviour remains the same.
+             *
+             * The following assert ensures that the sub-priority bit in the
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
+             * confusion. */
             configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
             ulMaxPRIGROUPValue = 0;
         }
diff --git a/portable/RVDS/ARM_CM7/r0p1/portmacro.h b/portable/RVDS/ARM_CM7/r0p1/portmacro.h
index a8fa6630e..efc1a1a43 100644
--- a/portable/RVDS/ARM_CM7/r0p1/portmacro.h
+++ b/portable/RVDS/ARM_CM7/r0p1/portmacro.h
@@ -47,45 +47,45 @@
  */
 
 /* Type definitions. */
-    #define portCHAR          char
-    #define portFLOAT         float
-    #define portDOUBLE        double
-    #define portLONG          long
-    #define portSHORT         short
-    #define portSTACK_TYPE    uint32_t
-    #define portBASE_TYPE     long
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-    typedef portSTACK_TYPE   StackType_t;
-    typedef long             BaseType_t;
-    typedef unsigned long    UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
-    #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-        typedef uint16_t     TickType_t;
-        #define portMAX_DELAY              ( TickType_t ) 0xffff
-    #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-        typedef uint32_t     TickType_t;
-        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
  * not need to be guarded with a critical section. */
-        #define portTICK_TYPE_IS_ATOMIC    1
-    #else
-        #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
-    #endif
+    #define portTICK_TYPE_IS_ATOMIC    1
+#else
+    #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+#endif
 /*-----------------------------------------------------------*/
 
 /* Architecture specifics. */
-    #define portSTACK_GROWTH          ( -1 )
-    #define portTICK_PERIOD_MS        ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-    #define portBYTE_ALIGNMENT        8
+#define portSTACK_GROWTH          ( -1 )
+#define portTICK_PERIOD_MS        ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT        8
 
 /* Constants used with memory barrier intrinsics. */
-    #define portSY_FULL_READ_WRITE    ( 15 )
+#define portSY_FULL_READ_WRITE    ( 15 )
 
 /*-----------------------------------------------------------*/
 
 /* Scheduler utilities. */
-    #define portYIELD()                                 \
+#define portYIELD()                                     \
     {                                                   \
         /* Set a PendSV to request a context switch. */ \
         portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
@@ -97,99 +97,99 @@
     }
 /*-----------------------------------------------------------*/
 
-    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
-    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-    #define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 )
-    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+#define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired != pdFALSE ) portYIELD( ); } while( 0 )
+#define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
 /* Critical section management. */
-    extern void vPortEnterCritical( void );
-    extern void vPortExitCritical( void );
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
 
-    #define portDISABLE_INTERRUPTS()                  vPortRaiseBASEPRI()
-    #define portENABLE_INTERRUPTS()                   vPortSetBASEPRI( 0 )
-    #define portENTER_CRITICAL()                      vPortEnterCritical()
-    #define portEXIT_CRITICAL()                       vPortExitCritical()
-    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulPortRaiseBASEPRI()
-    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vPortSetBASEPRI( x )
+#define portDISABLE_INTERRUPTS()                  vPortRaiseBASEPRI()
+#define portENABLE_INTERRUPTS()                   vPortSetBASEPRI( 0 )
+#define portENTER_CRITICAL()                      vPortEnterCritical()
+#define portEXIT_CRITICAL()                       vPortExitCritical()
+#define portSET_INTERRUPT_MASK_FROM_ISR()         ulPortRaiseBASEPRI()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vPortSetBASEPRI( x )
 
 /*-----------------------------------------------------------*/
 
 /* Tickless idle/low power functionality. */
-    #ifndef portSUPPRESS_TICKS_AND_SLEEP
-        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
-        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
-    #endif
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+    extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+    #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
 /*-----------------------------------------------------------*/
 
 /* Port specific optimisations. */
-    #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
-    #endif
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+    #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
+#endif
 
-    #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
 
 /* Check the configuration. */
-        #if ( configMAX_PRIORITIES > 32 )
-            #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
-        #endif
+    #if ( configMAX_PRIORITIES > 32 )
+        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+    #endif
 
 /* Store/clear the ready priorities in a bit map. */
-        #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-        #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 
 /*-----------------------------------------------------------*/
 
-        #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ( uint32_t ) __clz( ( uxReadyPriorities ) ) )
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ( uint32_t ) __clz( ( uxReadyPriorities ) ) )
 
-    #endif /* taskRECORD_READY_PRIORITY */
+#endif /* taskRECORD_READY_PRIORITY */
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site.  These are
  * not necessary for to use this port.  They are defined so the common demo files
  * (which build with all the ports) will build. */
-    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
-    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 /*-----------------------------------------------------------*/
 
-    #ifdef configASSERT
-        void vPortValidateInterruptPriority( void );
-        #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
-    #endif
+#ifdef configASSERT
+    void vPortValidateInterruptPriority( void );
+    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
+#endif
 
 /* portNOP() is not required by this port. */
-    #define portNOP()
+#define portNOP()
 
-    #define portINLINE              __inline
+#define portINLINE              __inline
 
-    #ifndef portFORCE_INLINE
-        #define portFORCE_INLINE    __forceinline
-    #endif
+#ifndef portFORCE_INLINE
+    #define portFORCE_INLINE    __forceinline
+#endif
 
 /*-----------------------------------------------------------*/
 
-    static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI )
+static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI )
+{
+    __asm
     {
-        __asm
-        {
-            /* Barrier instructions are not used as this function is only used to
-             * lower the BASEPRI value. */
+        /* Barrier instructions are not used as this function is only used to
+         * lower the BASEPRI value. */
 /* *INDENT-OFF* */
             msr basepri, ulBASEPRI
 /* *INDENT-ON* */
-        }
     }
+}
 /*-----------------------------------------------------------*/
 
-    static portFORCE_INLINE void vPortRaiseBASEPRI( void )
-    {
-        uint32_t ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
+static portFORCE_INLINE void vPortRaiseBASEPRI( void )
+{
+    uint32_t ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
 
-        __asm
-        {
-            /* Set BASEPRI to the max syscall priority to effect a critical
-             * section. */
+    __asm
+    {
+        /* Set BASEPRI to the max syscall priority to effect a critical
+         * section. */
 /* *INDENT-OFF* */
             cpsid i
             msr basepri, ulNewBASEPRI
@@ -197,32 +197,32 @@
             isb
             cpsie i
 /* *INDENT-ON* */
-        }
     }
+}
 /*-----------------------------------------------------------*/
 
-    static portFORCE_INLINE void vPortClearBASEPRIFromISR( void )
+static portFORCE_INLINE void vPortClearBASEPRIFromISR( void )
+{
+    __asm
     {
-        __asm
-        {
-            /* Set BASEPRI to 0 so no interrupts are masked.  This function is only
-             * used to lower the mask in an interrupt, so memory barriers are not
-             * used. */
+        /* Set BASEPRI to 0 so no interrupts are masked.  This function is only
+         * used to lower the mask in an interrupt, so memory barriers are not
+         * used. */
 /* *INDENT-OFF* */
             msr basepri, # 0
 /* *INDENT-ON* */
-        }
     }
+}
 /*-----------------------------------------------------------*/
 
-    static portFORCE_INLINE uint32_t ulPortRaiseBASEPRI( void )
-    {
-        uint32_t ulReturn, ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
+static portFORCE_INLINE uint32_t ulPortRaiseBASEPRI( void )
+{
+    uint32_t ulReturn, ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
 
-        __asm
-        {
-            /* Set BASEPRI to the max syscall priority to effect a critical
-             * section. */
+    __asm
+    {
+        /* Set BASEPRI to the max syscall priority to effect a critical
+         * section. */
 /* *INDENT-OFF* */
             mrs ulReturn, basepri
             cpsid i
@@ -231,37 +231,37 @@
             isb
             cpsie i
 /* *INDENT-ON* */
-        }
-
-        return ulReturn;
     }
+
+    return ulReturn;
+}
 /*-----------------------------------------------------------*/
 
-    static portFORCE_INLINE BaseType_t xPortIsInsideInterrupt( void )
-    {
-        uint32_t ulCurrentInterrupt;
-        BaseType_t xReturn;
+static portFORCE_INLINE BaseType_t xPortIsInsideInterrupt( void )
+{
+    uint32_t ulCurrentInterrupt;
+    BaseType_t xReturn;
 
-        /* Obtain the number of the currently executing interrupt. */
-        __asm
-        {
+    /* Obtain the number of the currently executing interrupt. */
+    __asm
+    {
 /* *INDENT-OFF* */
             mrs ulCurrentInterrupt, ipsr
 /* *INDENT-ON* */
-        }
-
-        if( ulCurrentInterrupt == 0 )
-        {
-            xReturn = pdFALSE;
-        }
-        else
-        {
-            xReturn = pdTRUE;
-        }
-
-        return xReturn;
     }
 
+    if( ulCurrentInterrupt == 0 )
+    {
+        xReturn = pdFALSE;
+    }
+    else
+    {
+        xReturn = pdTRUE;
+    }
+
+    return xReturn;
+}
+
 /* *INDENT-OFF* */
 #ifdef __cplusplus
     }
diff --git a/portable/Renesas/RX100/port.c b/portable/Renesas/RX100/port.c
index 9e8db4f04..1c5a98930 100644
--- a/portable/Renesas/RX100/port.c
+++ b/portable/Renesas/RX100/port.c
@@ -27,8 +27,8 @@
  */
 
 /*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the RX100 port.
- *----------------------------------------------------------*/
+* Implementation of functions defined in portable.h for the RX100 port.
+*----------------------------------------------------------*/
 
 /* Standard C includes. */
 #include "limits.h"
@@ -46,35 +46,35 @@
 /*-----------------------------------------------------------*/
 
 /* Tasks should start with interrupts enabled and in Supervisor mode, therefore
-PSW is set with U and I set, and PM and IPL clear. */
-#define portINITIAL_PSW     ( ( StackType_t ) 0x00030000 )
+ * PSW is set with U and I set, and PM and IPL clear. */
+#define portINITIAL_PSW    ( ( StackType_t ) 0x00030000 )
 
 /* The peripheral clock is divided by this value before being supplying the
-CMT. */
+ * CMT. */
 #if ( configUSE_TICKLESS_IDLE == 0 )
     /* If tickless idle is not used then the divisor can be fixed. */
-    #define portCLOCK_DIVISOR   8UL
+    #define portCLOCK_DIVISOR    8UL
 #elif ( configPERIPHERAL_CLOCK_HZ >= 12000000 )
-    #define portCLOCK_DIVISOR   512UL
+    #define portCLOCK_DIVISOR    512UL
 #elif ( configPERIPHERAL_CLOCK_HZ >= 6000000 )
-    #define portCLOCK_DIVISOR   128UL
+    #define portCLOCK_DIVISOR    128UL
 #elif ( configPERIPHERAL_CLOCK_HZ >= 1000000 )
-    #define portCLOCK_DIVISOR   32UL
+    #define portCLOCK_DIVISOR    32UL
 #else
-    #define portCLOCK_DIVISOR   8UL
+    #define portCLOCK_DIVISOR    8UL
 #endif
 
 
 /* Keys required to lock and unlock access to certain system registers
-respectively. */
-#define portUNLOCK_KEY      0xA50B
-#define portLOCK_KEY        0xA500
+ * respectively. */
+#define portUNLOCK_KEY    0xA50B
+#define portLOCK_KEY      0xA500
 
 /*-----------------------------------------------------------*/
 
 /* The following lines are to ensure vSoftwareInterruptEntry can be referenced,
- and therefore installed in the vector table, when the FreeRTOS code is built
-as a library. */
+ * and therefore installed in the vector table, when the FreeRTOS code is built
+ * as a library. */
 extern BaseType_t vSoftwareInterruptEntry;
 const BaseType_t * p_vSoftwareInterruptEntry = &vSoftwareInterruptEntry;
 
@@ -109,9 +109,10 @@ void vSoftwareInterruptISR( void );
  */
 static void prvSetupTimerInterrupt( void );
 #ifndef configSETUP_TICK_INTERRUPT
-    /* The user has not provided their own tick interrupt configuration so use
-    the definition in this file (which uses the interval timer). */
-    #define configSETUP_TICK_INTERRUPT() prvSetupTimerInterrupt()
+
+/* The user has not provided their own tick interrupt configuration so use
+ * the definition in this file (which uses the interval timer). */
+    #define configSETUP_TICK_INTERRUPT()    prvSetupTimerInterrupt()
 #endif /* configSETUP_TICK_INTERRUPT */
 
 /*
@@ -126,7 +127,7 @@ static void prvSetupTimerInterrupt( void );
 /*-----------------------------------------------------------*/
 
 /* These is accessed by the inline assembler functions. */
-extern void *pxCurrentTCB;
+extern void * pxCurrentTCB;
 extern void vTaskSwitchContext( void );
 
 /*-----------------------------------------------------------*/
@@ -136,33 +137,35 @@ static const uint32_t ulMatchValueForOneTick = ( ( configPERIPHERAL_CLOCK_HZ / p
 
 #if configUSE_TICKLESS_IDLE == 1
 
-    /* Holds the maximum number of ticks that can be suppressed - which is
-    basically how far into the future an interrupt can be generated. Set
-    during initialisation.  This is the maximum possible value that the
-    compare match register can hold divided by ulMatchValueForOneTick. */
+/* Holds the maximum number of ticks that can be suppressed - which is
+ * basically how far into the future an interrupt can be generated. Set
+ * during initialisation.  This is the maximum possible value that the
+ * compare match register can hold divided by ulMatchValueForOneTick. */
     static const TickType_t xMaximumPossibleSuppressedTicks = USHRT_MAX / ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
 
-    /* Flag set from the tick interrupt to allow the sleep processing to know if
-    sleep mode was exited because of a tick interrupt, or an interrupt
-    generated by something else. */
+/* Flag set from the tick interrupt to allow the sleep processing to know if
+ * sleep mode was exited because of a tick interrupt, or an interrupt
+ * generated by something else. */
     static volatile uint32_t ulTickFlag = pdFALSE;
 
-    /* The CMT counter is stopped temporarily each time it is re-programmed.
-    The following constant offsets the CMT counter match value by the number of
-    CMT counts that would typically be missed while the counter was stopped to
-    compensate for the lost time.  The large difference between the divided CMT
-    clock and the CPU clock means it is likely ulStoppedTimerCompensation will
-    equal zero - and be optimised away. */
+/* The CMT counter is stopped temporarily each time it is re-programmed.
+ * The following constant offsets the CMT counter match value by the number of
+ * CMT counts that would typically be missed while the counter was stopped to
+ * compensate for the lost time.  The large difference between the divided CMT
+ * clock and the CPU clock means it is likely ulStoppedTimerCompensation will
+ * equal zero - and be optimised away. */
     static const uint32_t ulStoppedTimerCompensation = 100UL / ( configCPU_CLOCK_HZ / ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) );
 
-#endif
+#endif /* if configUSE_TICKLESS_IDLE == 1 */
 
 /*-----------------------------------------------------------*/
 
 /*
  * See header file for description.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
     /* Offset to end up on 8 byte boundary. */
     pxTopOfStack--;
@@ -177,8 +180,8 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
     *pxTopOfStack = ( StackType_t ) pxCode;
 
     /* When debugging it can be useful if every register is set to a known
-    value.  Otherwise code space can be saved by just setting the registers
-    that need to be set. */
+     * value.  Otherwise code space can be saved by just setting the registers
+     * that need to be set. */
     #ifdef USE_FULL_REGISTER_INITIALISATION
     {
         pxTopOfStack--;
@@ -211,19 +214,19 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
         *pxTopOfStack = 0x22222222;
         pxTopOfStack--;
     }
-    #else
+    #else /* ifdef USE_FULL_REGISTER_INITIALISATION */
     {
         /* Leave space for the registers that will get popped from the stack
-        when the task first starts executing. */
+         * when the task first starts executing. */
         pxTopOfStack -= 15;
     }
-    #endif
+    #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */
 
     *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
     pxTopOfStack--;
-    *pxTopOfStack = 0x12345678; /* Accumulator. */
+    *pxTopOfStack = 0x12345678;                   /* Accumulator. */
     pxTopOfStack--;
-    *pxTopOfStack = 0x87654321; /* Accumulator. */
+    *pxTopOfStack = 0x87654321;                   /* Accumulator. */
 
     return pxTopOfStack;
 }
@@ -235,10 +238,10 @@ BaseType_t xPortStartScheduler( void )
     if( pxCurrentTCB != NULL )
     {
         /* Call an application function to set up the timer that will generate
-        the tick interrupt.  This way the application can decide which
-        peripheral to use.  If tickless mode is used then the default
-        implementation defined in this file (which uses CMT0) should not be
-        overridden. */
+         * the tick interrupt.  This way the application can decide which
+         * peripheral to use.  If tickless mode is used then the default
+         * implementation defined in this file (which uses CMT0) should not be
+         * overridden. */
         configSETUP_TICK_INTERRUPT();
 
         /* Enable the software interrupt. */
@@ -255,11 +258,11 @@ BaseType_t xPortStartScheduler( void )
     }
 
     /* Execution should not reach here as the tasks are now running!
-    prvSetupTimerInterrupt() is called here to prevent the compiler outputting
-    a warning about a statically declared function not being referenced in the
-    case that the application writer has provided their own tick interrupt
-    configuration routine (and defined configSETUP_TICK_INTERRUPT() such that
-    their own routine will be called in place of prvSetupTimerInterrupt()). */
+     * prvSetupTimerInterrupt() is called here to prevent the compiler outputting
+     * a warning about a statically declared function not being referenced in the
+     * case that the application writer has provided their own tick interrupt
+     * configuration routine (and defined configSETUP_TICK_INTERRUPT() such that
+     * their own routine will be called in place of prvSetupTimerInterrupt()). */
     prvSetupTimerInterrupt();
 
     /* Just to make sure the function is not optimised away. */
@@ -274,26 +277,26 @@ BaseType_t xPortStartScheduler( void )
 static void prvStartFirstTask( void )
 {
     /* When starting the scheduler there is nothing that needs moving to the
-    interrupt stack because the function is not called from an interrupt.
-    Just ensure the current stack is the user stack. */
-    SETPSW  U
+     * interrupt stack because the function is not called from an interrupt.
+     * Just ensure the current stack is the user stack. */
+    SETPSW U
 
     /* Obtain the location of the stack associated with which ever task
-    pxCurrentTCB is currently pointing to. */
-    MOV.L   #_pxCurrentTCB, R15
-    MOV.L   [R15], R15
-    MOV.L   [R15], R0
+     * pxCurrentTCB is currently pointing to. */
+    MOV.L   # _pxCurrentTCB, R15
+        MOV.L[ R15 ], R15
+        MOV.L[ R15 ], R0
 
     /* Restore the registers from the stack of the task pointed to by
-    pxCurrentTCB. */
-    POP     R15
-    MVTACLO R15         /* Accumulator low 32 bits. */
-    POP     R15
-    MVTACHI R15         /* Accumulator high 32 bits. */
-    POPM    R1-R15      /* R1 to R15 - R0 is not included as it is the SP. */
-    RTE                 /* This pops the remaining registers. */
-    NOP
+     * pxCurrentTCB. */
+    POP R15
+    MVTACLO R15   /* Accumulator low 32 bits. */
+    POP R15
+    MVTACHI R15   /* Accumulator high 32 bits. */
+    POPM R1 - R15 /* R1 to R15 - R0 is not included as it is the SP. */
+    RTE           /* This pops the remaining registers. */
     NOP
+        NOP
 }
 /*-----------------------------------------------------------*/
 
@@ -301,7 +304,7 @@ static void prvStartFirstTask( void )
 void prvTickISR( void )
 {
     /* Increment the tick, and perform any processing the new tick value
-    necessitates. */
+     * necessitates. */
     set_ipl( configMAX_SYSCALL_INTERRUPT_PRIORITY );
     {
         if( xTaskIncrementTick() != pdFALSE )
@@ -309,6 +312,7 @@ void prvTickISR( void )
             taskYIELD();
         }
     }
+
     set_ipl( configKERNEL_INTERRUPT_PRIORITY );
 
     #if configUSE_TICKLESS_IDLE == 1
@@ -317,7 +321,7 @@ void prvTickISR( void )
         ulTickFlag = pdTRUE;
 
         /* If this is the first tick since exiting tickless mode then the CMT
-        compare match value needs resetting. */
+         * compare match value needs resetting. */
         CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;
     }
     #endif
@@ -334,81 +338,87 @@ void vSoftwareInterruptISR( void )
 static void prvYieldHandler( void )
 {
     /* Re-enable interrupts. */
-    SETPSW  I
+    SETPSW I
 
     /* Move the data that was automatically pushed onto the interrupt stack
-    when the interrupt occurred from the interrupt stack to the user stack.
-
-    R15 is saved before it is clobbered. */
-    PUSH.L  R15
+     * when the interrupt occurred from the interrupt stack to the user stack.
+     *
+     * R15 is saved before it is clobbered. */
+    PUSH.L R15
 
     /* Read the user stack pointer. */
-    MVFC    USP, R15
+    MVFC USP, R15
 
     /* Move the address down to the data being moved. */
-    SUB     #12, R15
-    MVTC    R15, USP
+         SUB     # 12, R15
+    MVTC R15, USP
 
     /* Copy the data across. */
-    MOV.L   [ R0 ], [ R15 ] ; R15
-    MOV.L   4[ R0 ], 4[ R15 ]  ; PC
-    MOV.L   8[ R0 ], 8[ R15 ]  ; PSW
+         MOV.L[ R0 ], [ R15 ];
+    R15
+
+    MOV.L   4[ R0 ], 4[ R15 ];
+    PC
+    MOV.L   8[ R0 ], 8[ R15 ];
+    PSW
 
     /* Move the interrupt stack pointer to its new correct position. */
-    ADD #12, R0
+        ADD # 12, R0
 
     /* All the rest of the registers are saved directly to the user stack. */
-    SETPSW  U
+    SETPSW U
 
     /* Save the rest of the general registers (R15 has been saved already). */
-    PUSHM   R1-R14
+    PUSHM R1 - R14
 
     /* Save the accumulator. */
     MVFACHI R15
-    PUSH.L  R15
-    MVFACMI R15 ; Middle order word.
-    SHLL    #16, R15 ; Shifted left as it is restored to the low order word.
-    PUSH.L  R15
+        PUSH.L R15
+    MVFACMI R15;
+    Middle order word.
+       SHLL    # 16, R15;
+    Shifted left as it is restored to the low order word.
+       PUSH.L R15
 
     /* Save the stack pointer to the TCB. */
-    MOV.L   #_pxCurrentTCB, R15
-    MOV.L   [ R15 ], R15
-    MOV.L   R0, [ R15 ]
+    MOV.L   # _pxCurrentTCB, R15
+        MOV.L[ R15 ], R15
+        MOV.L R0, [ R15 ]
 
     /* Ensure the interrupt mask is set to the syscall priority while the
-    kernel structures are being accessed. */
-    MVTIPL  #configMAX_SYSCALL_INTERRUPT_PRIORITY
+     * kernel structures are being accessed. */
+    MVTIPL  # configMAX_SYSCALL_INTERRUPT_PRIORITY
 
     /* Select the next task to run. */
-    BSR.A   _vTaskSwitchContext
+    BSR.A _vTaskSwitchContext
 
     /* Reset the interrupt mask as no more data structure access is
-    required. */
-    MVTIPL  #configKERNEL_INTERRUPT_PRIORITY
+     * required. */
+    MVTIPL  # configKERNEL_INTERRUPT_PRIORITY
 
     /* Load the stack pointer of the task that is now selected as the Running
-    state task from its TCB. */
-    MOV.L   #_pxCurrentTCB,R15
-    MOV.L   [ R15 ], R15
-    MOV.L   [ R15 ], R0
+     * state task from its TCB. */
+    MOV.L   # _pxCurrentTCB, R15
+        MOV.L[ R15 ], R15
+        MOV.L[ R15 ], R0
 
     /* Restore the context of the new task.  The PSW (Program Status Word) and
-    PC will be popped by the RTE instruction. */
-    POP     R15
+     * PC will be popped by the RTE instruction. */
+    POP R15
     MVTACLO R15
-    POP     R15
+    POP R15
     MVTACHI R15
-    POPM    R1-R15
+    POPM R1 - R15
     RTE
     NOP
-    NOP
+        NOP
 }
 /*-----------------------------------------------------------*/
 
 void vPortEndScheduler( void )
 {
     /* Not implemented in ports where there is nothing to return to.
-    Artificially force an assert. */
+     * Artificially force an assert. */
     configASSERT( pxCurrentTCB == NULL );
 
     /* The following line is just to prevent the symbol getting optimised away. */
@@ -450,11 +460,11 @@ static void prvSetupTimerInterrupt( void )
     {
         CMT0.CMCR.BIT.CKS = 0;
     }
-    #else
+    #else /* if portCLOCK_DIVISOR == 512 */
     {
         #error Invalid portCLOCK_DIVISOR setting
     }
-    #endif
+    #endif /* if portCLOCK_DIVISOR == 512 */
 
 
     /* Enable the interrupt... */
@@ -476,8 +486,8 @@ static void prvSetupTimerInterrupt( void )
         configPRE_SLEEP_PROCESSING( xExpectedIdleTime );
 
         /* xExpectedIdleTime being set to 0 by configPRE_SLEEP_PROCESSING()
-        means the application defined code has already executed the WAIT
-        instruction. */
+         * means the application defined code has already executed the WAIT
+         * instruction. */
         if( xExpectedIdleTime > 0 )
         {
             wait();
@@ -494,8 +504,8 @@ static void prvSetupTimerInterrupt( void )
 
     void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
     {
-    uint32_t ulMatchValue, ulCompleteTickPeriods, ulCurrentCount;
-    eSleepModeStatus eSleepAction;
+        uint32_t ulMatchValue, ulCompleteTickPeriods, ulCurrentCount;
+        eSleepModeStatus eSleepAction;
 
         /* THIS FUNCTION IS CALLED WITH THE SCHEDULER SUSPENDED. */
 
@@ -506,38 +516,41 @@ static void prvSetupTimerInterrupt( void )
         }
 
         /* Calculate the reload value required to wait xExpectedIdleTime tick
-        periods. */
+         * periods. */
         ulMatchValue = ulMatchValueForOneTick * xExpectedIdleTime;
+
         if( ulMatchValue > ulStoppedTimerCompensation )
         {
             /* Compensate for the fact that the CMT is going to be stopped
-            momentarily. */
+             * momentarily. */
             ulMatchValue -= ulStoppedTimerCompensation;
         }
 
         /* Stop the CMT momentarily.  The time the CMT is stopped for is
-        accounted for as best it can be, but using the tickless mode will
-        inevitably result in some tiny drift of the time maintained by the
-        kernel with respect to calendar time. */
+         * accounted for as best it can be, but using the tickless mode will
+         * inevitably result in some tiny drift of the time maintained by the
+         * kernel with respect to calendar time. */
         CMT.CMSTR0.BIT.STR0 = 0;
+
         while( CMT.CMSTR0.BIT.STR0 == 1 )
         {
             /* Nothing to do here. */
         }
 
         /* Critical section using the global interrupt bit as the i bit is
-        automatically reset by the WAIT instruction. */
+         * automatically reset by the WAIT instruction. */
         clrpsw_i();
 
         /* The tick flag is set to false before sleeping.  If it is true when
-        sleep mode is exited then sleep mode was probably exited because the
-        tick was suppressed for the entire xExpectedIdleTime period. */
+         * sleep mode is exited then sleep mode was probably exited because the
+         * tick was suppressed for the entire xExpectedIdleTime period. */
         ulTickFlag = pdFALSE;
 
         /* If a context switch is pending then abandon the low power entry as
-        the context switch might have been pended by an external interrupt that
-        requires processing. */
+         * the context switch might have been pended by an external interrupt that
+         * requires processing. */
         eSleepAction = eTaskConfirmSleepModeStatus();
+
         if( eSleepAction == eAbortSleep )
         {
             /* Restart tick. */
@@ -556,7 +569,7 @@ static void prvSetupTimerInterrupt( void )
             SYSTEM.PRCR.WORD = portLOCK_KEY;
 
             /* Sleep until something happens.  Calling prvSleep() will
-            automatically reset the i bit in the PSW. */
+             * automatically reset the i bit in the PSW. */
             prvSleep( xExpectedIdleTime );
 
             /* Restart the CMT. */
@@ -576,7 +589,7 @@ static void prvSetupTimerInterrupt( void )
             SYSTEM.PRCR.WORD = portLOCK_KEY;
 
             /* Adjust the match value to take into account that the current
-            time slice is already partially complete. */
+             * time slice is already partially complete. */
             ulMatchValue -= ( uint32_t ) CMT0.CMCNT;
             CMT0.CMCOR = ( uint16_t ) ulMatchValue;
 
@@ -585,14 +598,15 @@ static void prvSetupTimerInterrupt( void )
             CMT.CMSTR0.BIT.STR0 = 1;
 
             /* Sleep until something happens.  Calling prvSleep() will
-            automatically reset the i bit in the PSW. */
+             * automatically reset the i bit in the PSW. */
             prvSleep( xExpectedIdleTime );
 
             /* Stop CMT.  Again, the time the SysTick is stopped for is
-            accounted for as best it can be, but using the tickless mode will
-            inevitably result in some tiny drift of the time maintained by the
-            kernel with respect to calendar time. */
+             * accounted for as best it can be, but using the tickless mode will
+             * inevitably result in some tiny drift of the time maintained by the
+             * kernel with respect to calendar time. */
             CMT.CMSTR0.BIT.STR0 = 0;
+
             while( CMT.CMSTR0.BIT.STR0 == 1 )
             {
                 /* Nothing to do here. */
@@ -603,42 +617,42 @@ static void prvSetupTimerInterrupt( void )
             if( ulTickFlag != pdFALSE )
             {
                 /* The tick interrupt has already executed, although because
-                this function is called with the scheduler suspended the actual
-                tick processing will not occur until after this function has
-                exited.  Reset the match value with whatever remains of this
-                tick period. */
+                 * this function is called with the scheduler suspended the actual
+                 * tick processing will not occur until after this function has
+                 * exited.  Reset the match value with whatever remains of this
+                 * tick period. */
                 ulMatchValue = ulMatchValueForOneTick - ulCurrentCount;
                 CMT0.CMCOR = ( uint16_t ) ulMatchValue;
 
                 /* The tick interrupt handler will already have pended the tick
-                processing in the kernel.  As the pending tick will be
-                processed as soon as this function exits, the tick value
-                maintained by the tick is stepped forward by one less than the
-                time spent sleeping.  The actual stepping of the tick appears
-                later in this function. */
+                 * processing in the kernel.  As the pending tick will be
+                 * processed as soon as this function exits, the tick value
+                 * maintained by the tick is stepped forward by one less than the
+                 * time spent sleeping.  The actual stepping of the tick appears
+                 * later in this function. */
                 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
             }
             else
             {
                 /* Something other than the tick interrupt ended the sleep.
-                How many complete tick periods passed while the processor was
-                sleeping? */
+                 * How many complete tick periods passed while the processor was
+                 * sleeping? */
                 ulCompleteTickPeriods = ulCurrentCount / ulMatchValueForOneTick;
 
                 /* The match value is set to whatever fraction of a single tick
-                period remains. */
+                 * period remains. */
                 ulMatchValue = ulCurrentCount - ( ulCompleteTickPeriods * ulMatchValueForOneTick );
                 CMT0.CMCOR = ( uint16_t ) ulMatchValue;
             }
 
             /* Restart the CMT so it runs up to the match value.  The match value
-            will get set to the value required to generate exactly one tick period
-            the next time the CMT interrupt executes. */
+             * will get set to the value required to generate exactly one tick period
+             * the next time the CMT interrupt executes. */
             CMT0.CMCNT = 0;
             CMT.CMSTR0.BIT.STR0 = 1;
 
             /* Wind the tick forward by the number of tick periods that the CPU
-            remained in a low power state. */
+             * remained in a low power state. */
             vTaskStepTick( ulCompleteTickPeriods );
         }
     }
diff --git a/portable/Renesas/RX100/portmacro.h b/portable/Renesas/RX100/portmacro.h
index b82fdca24..d6a758bb7 100644
--- a/portable/Renesas/RX100/portmacro.h
+++ b/portable/Renesas/RX100/portmacro.h
@@ -50,87 +50,87 @@
  */
 
 /* Type definitions - these are a bit legacy and not really used now, other
-than portSTACK_TYPE and portBASE_TYPE. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint32_t
-#define portBASE_TYPE   long
+ * than portSTACK_TYPE and portBASE_TYPE. */
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-    not need to be guarded with a critical section. */
-    #define portTICK_TYPE_IS_ATOMIC 1
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+    #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portBYTE_ALIGNMENT              8   /* Could make four, according to manual. */
-#define portSTACK_GROWTH                -1
-#define portTICK_PERIOD_MS              ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portNOP()                       nop()
+#define portBYTE_ALIGNMENT    8             /* Could make four, according to manual. */
+#define portSTACK_GROWTH      -1
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()    nop()
 
 #pragma inline_asm vPortYield
 static void vPortYield( void )
 {
     /* Save clobbered register - may not actually be necessary if inline asm
-    functions are considered to use the same rules as function calls by the
-    compiler. */
+     * functions are considered to use the same rules as function calls by the
+     * compiler. */
     PUSH.L R5
     /* Set ITU SWINTR. */
-    MOV.L #872E0H, R5
-    MOV.B #1, [R5]
+    MOV.L # 872E0H, R5
+        MOV.B # 1, [ R5 ]
     /* Read back to ensure the value is taken before proceeding. */
-    MOV.L [R5], R5
+    MOV.L[ R5 ], R5
     /* Restore clobbered register to its previous value. */
     POP R5
 }
-#define portYIELD() vPortYield()
-#define portYIELD_FROM_ISR( x ) do { if( x != pdFALSE ) { portYIELD(); } } while( 0 )
+#define portYIELD()                                       vPortYield()
+#define portYIELD_FROM_ISR( x )                           do { if( x != pdFALSE ) { portYIELD(); } } while( 0 )
 
 /* These macros should not be called directly, but through the
-taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
-performed if configASSERT() is defined to ensure an assertion handler does not
-inadvertently attempt to lower the IPL when the call to assert was triggered
-because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
-when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
-functions are those that end in FromISR.  FreeRTOS maintains a separate
-interrupt API to ensure API function and interrupt entry is as fast and as
-simple as possible. */
-#define portENABLE_INTERRUPTS()     set_ipl( ( long ) 0 )
+ * taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
+ * performed if configASSERT() is defined to ensure an assertion handler does not
+ * inadvertently attempt to lower the IPL when the call to assert was triggered
+ * because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
+ * when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
+ * functions are those that end in FromISR.  FreeRTOS maintains a separate
+ * interrupt API to ensure API function and interrupt entry is as fast and as
+ * simple as possible. */
+#define portENABLE_INTERRUPTS()                           set_ipl( ( long ) 0 )
 #ifdef configASSERT
-    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( get_ipl() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
-    #define portDISABLE_INTERRUPTS()    if( get_ipl() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    configASSERT( ( get_ipl() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+    #define portDISABLE_INTERRUPTS()                      if( get_ipl() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
 #else
-    #define portDISABLE_INTERRUPTS()    set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+    #define portDISABLE_INTERRUPTS()                      set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
 #endif
 
 /* Critical nesting counts are stored in the TCB. */
-#define portCRITICAL_NESTING_IN_TCB ( 1 )
+#define portCRITICAL_NESTING_IN_TCB    ( 1 )
 
 /* The critical nesting functions defined within tasks.c. */
 extern void vTaskEnterCritical( void );
 extern void vTaskExitCritical( void );
-#define portENTER_CRITICAL()    vTaskEnterCritical()
-#define portEXIT_CRITICAL()     vTaskExitCritical()
+#define portENTER_CRITICAL()                                           vTaskEnterCritical()
+#define portEXIT_CRITICAL()                                            vTaskExitCritical()
 
 /* As this port allows interrupt nesting... */
-#define portSET_INTERRUPT_MASK_FROM_ISR() ( UBaseType_t ) get_ipl(); set_ipl( ( signed long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) set_ipl( ( signed long ) uxSavedInterruptStatus )
+#define portSET_INTERRUPT_MASK_FROM_ISR()                              ( UBaseType_t ) get_ipl(); set_ipl( ( signed long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus )    set_ipl( ( signed long ) uxSavedInterruptStatus )
 
 /*-----------------------------------------------------------*/
 
@@ -138,15 +138,15 @@ extern void vTaskExitCritical( void );
 #if configUSE_TICKLESS_IDLE == 1
     #ifndef portSUPPRESS_TICKS_AND_SLEEP
         extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
-        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
     #endif
 #endif
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/Renesas/RX200/port.c b/portable/Renesas/RX200/port.c
index d60ac8fff..13d035434 100644
--- a/portable/Renesas/RX200/port.c
+++ b/portable/Renesas/RX200/port.c
@@ -27,8 +27,8 @@
  */
 
 /*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the RX200 port.
- *----------------------------------------------------------*/
+* Implementation of functions defined in portable.h for the RX200 port.
+*----------------------------------------------------------*/
 
 /* Scheduler includes. */
 #include "FreeRTOS.h"
@@ -43,14 +43,14 @@
 /*-----------------------------------------------------------*/
 
 /* Tasks should start with interrupts enabled and in Supervisor mode, therefore
-PSW is set with U and I set, and PM and IPL clear. */
-#define portINITIAL_PSW     ( ( StackType_t ) 0x00030000 )
+ * PSW is set with U and I set, and PM and IPL clear. */
+#define portINITIAL_PSW    ( ( StackType_t ) 0x00030000 )
 
 /*-----------------------------------------------------------*/
 
 /* The following lines are to ensure vSoftwareInterruptEntry can be referenced,
- and therefore installed in the vector table, when the FreeRTOS code is built
-as a library. */
+ * and therefore installed in the vector table, when the FreeRTOS code is built
+ * as a library. */
 extern BaseType_t vSoftwareInterruptEntry;
 const BaseType_t * p_vSoftwareInterruptEntry = &vSoftwareInterruptEntry;
 
@@ -80,8 +80,8 @@ void vSoftwareInterruptISR( void );
 /*-----------------------------------------------------------*/
 
 /* This is accessed by the inline assembler functions so is file scope for
-convenience. */
-extern void *pxCurrentTCB;
+ * convenience. */
+extern void * pxCurrentTCB;
 extern void vTaskSwitchContext( void );
 
 /*-----------------------------------------------------------*/
@@ -89,7 +89,9 @@ extern void vTaskSwitchContext( void );
 /*
  * See header file for description.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
     /* Offset to end up on 8 byte boundary. */
     pxTopOfStack--;
@@ -104,8 +106,8 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
     *pxTopOfStack = ( StackType_t ) pxCode;
 
     /* When debugging it can be useful if every register is set to a known
-    value.  Otherwise code space can be saved by just setting the registers
-    that need to be set. */
+     * value.  Otherwise code space can be saved by just setting the registers
+     * that need to be set. */
     #ifdef USE_FULL_REGISTER_INITIALISATION
     {
         pxTopOfStack--;
@@ -138,17 +140,17 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
         *pxTopOfStack = 0x22222222;
         pxTopOfStack--;
     }
-    #else
+    #else /* ifdef USE_FULL_REGISTER_INITIALISATION */
     {
         pxTopOfStack -= 15;
     }
-    #endif
+    #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */
 
     *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
     pxTopOfStack--;
-    *pxTopOfStack = 0x12345678; /* Accumulator. */
+    *pxTopOfStack = 0x12345678;                   /* Accumulator. */
     pxTopOfStack--;
-    *pxTopOfStack = 0x87654321; /* Accumulator. */
+    *pxTopOfStack = 0x87654321;                   /* Accumulator. */
 
     return pxTopOfStack;
 }
@@ -156,14 +158,14 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
 
 BaseType_t xPortStartScheduler( void )
 {
-extern void vApplicationSetupTimerInterrupt( void );
+    extern void vApplicationSetupTimerInterrupt( void );
 
     /* Use pxCurrentTCB just so it does not get optimised away. */
     if( pxCurrentTCB != NULL )
     {
         /* Call an application function to set up the timer that will generate the
-        tick interrupt.  This way the application can decide which peripheral to
-        use.  A demo application is provided to show a suitable example. */
+         * tick interrupt.  This way the application can decide which peripheral to
+         * use.  A demo application is provided to show a suitable example. */
         vApplicationSetupTimerInterrupt();
 
         /* Enable the software interrupt. */
@@ -191,26 +193,26 @@ extern void vApplicationSetupTimerInterrupt( void );
 static void prvStartFirstTask( void )
 {
     /* When starting the scheduler there is nothing that needs moving to the
-    interrupt stack because the function is not called from an interrupt.
-    Just ensure the current stack is the user stack. */
-    SETPSW  U
+     * interrupt stack because the function is not called from an interrupt.
+     * Just ensure the current stack is the user stack. */
+    SETPSW U
 
     /* Obtain the location of the stack associated with which ever task
-    pxCurrentTCB is currently pointing to. */
-    MOV.L   #_pxCurrentTCB, R15
-    MOV.L   [R15], R15
-    MOV.L   [R15], R0
+     * pxCurrentTCB is currently pointing to. */
+    MOV.L   # _pxCurrentTCB, R15
+        MOV.L[ R15 ], R15
+        MOV.L[ R15 ], R0
 
     /* Restore the registers from the stack of the task pointed to by
-    pxCurrentTCB. */
-    POP     R15
-    MVTACLO R15         /* Accumulator low 32 bits. */
-    POP     R15
-    MVTACHI R15         /* Accumulator high 32 bits. */
-    POPM    R1-R15      /* R1 to R15 - R0 is not included as it is the SP. */
-    RTE                 /* This pops the remaining registers. */
-    NOP
+     * pxCurrentTCB. */
+    POP R15
+    MVTACLO R15   /* Accumulator low 32 bits. */
+    POP R15
+    MVTACHI R15   /* Accumulator high 32 bits. */
+    POPM R1 - R15 /* R1 to R15 - R0 is not included as it is the SP. */
+    RTE           /* This pops the remaining registers. */
     NOP
+        NOP
 }
 /*-----------------------------------------------------------*/
 
@@ -218,7 +220,7 @@ static void prvStartFirstTask( void )
 void vTickISR( void )
 {
     /* Increment the tick, and perform any processing the new tick value
-    necessitates. */
+     * necessitates. */
     set_ipl( configMAX_SYSCALL_INTERRUPT_PRIORITY );
     {
         if( xTaskIncrementTick() != pdFALSE )
@@ -226,6 +228,7 @@ void vTickISR( void )
             taskYIELD();
         }
     }
+
     set_ipl( configKERNEL_INTERRUPT_PRIORITY );
 }
 /*-----------------------------------------------------------*/
@@ -240,80 +243,86 @@ void vSoftwareInterruptISR( void )
 static void prvYieldHandler( void )
 {
     /* Re-enable interrupts. */
-    SETPSW  I
+    SETPSW I
 
     /* Move the data that was automatically pushed onto the interrupt stack when
-    the interrupt occurred from the interrupt stack to the user stack.
-
-    R15 is saved before it is clobbered. */
-    PUSH.L  R15
+     * the interrupt occurred from the interrupt stack to the user stack.
+     *
+     * R15 is saved before it is clobbered. */
+    PUSH.L R15
 
     /* Read the user stack pointer. */
-    MVFC    USP, R15
+    MVFC USP, R15
 
     /* Move the address down to the data being moved. */
-    SUB     #12, R15
-    MVTC    R15, USP
+         SUB     # 12, R15
+    MVTC R15, USP
 
     /* Copy the data across. */
-    MOV.L   [ R0 ], [ R15 ] ; R15
-    MOV.L   4[ R0 ], 4[ R15 ]  ; PC
-    MOV.L   8[ R0 ], 8[ R15 ]  ; PSW
+         MOV.L[ R0 ], [ R15 ];
+    R15
+
+    MOV.L   4[ R0 ], 4[ R15 ];
+    PC
+    MOV.L   8[ R0 ], 8[ R15 ];
+    PSW
 
     /* Move the interrupt stack pointer to its new correct position. */
-    ADD #12, R0
+        ADD # 12, R0
 
     /* All the rest of the registers are saved directly to the user stack. */
-    SETPSW  U
+    SETPSW U
 
     /* Save the rest of the general registers (R15 has been saved already). */
-    PUSHM   R1-R14
+    PUSHM R1 - R14
 
     /* Save the accumulator. */
     MVFACHI R15
-    PUSH.L  R15
-    MVFACMI R15 ; Middle order word.
-    SHLL    #16, R15 ; Shifted left as it is restored to the low order word.
-    PUSH.L  R15
+        PUSH.L R15
+    MVFACMI R15;
+    Middle order word.
+       SHLL    # 16, R15;
+    Shifted left as it is restored to the low order word.
+       PUSH.L R15
 
     /* Save the stack pointer to the TCB. */
-    MOV.L   #_pxCurrentTCB, R15
-    MOV.L   [ R15 ], R15
-    MOV.L   R0, [ R15 ]
+    MOV.L   # _pxCurrentTCB, R15
+        MOV.L[ R15 ], R15
+        MOV.L R0, [ R15 ]
 
     /* Ensure the interrupt mask is set to the syscall priority while the kernel
-    structures are being accessed. */
-    MVTIPL  #configMAX_SYSCALL_INTERRUPT_PRIORITY
+     * structures are being accessed. */
+    MVTIPL  # configMAX_SYSCALL_INTERRUPT_PRIORITY
 
     /* Select the next task to run. */
-    BSR.A   _vTaskSwitchContext
+    BSR.A _vTaskSwitchContext
 
     /* Reset the interrupt mask as no more data structure access is required. */
-    MVTIPL  #configKERNEL_INTERRUPT_PRIORITY
+    MVTIPL  # configKERNEL_INTERRUPT_PRIORITY
 
     /* Load the stack pointer of the task that is now selected as the Running
-    state task from its TCB. */
-    MOV.L   #_pxCurrentTCB,R15
-    MOV.L   [ R15 ], R15
-    MOV.L   [ R15 ], R0
+     * state task from its TCB. */
+    MOV.L   # _pxCurrentTCB, R15
+        MOV.L[ R15 ], R15
+        MOV.L[ R15 ], R0
 
     /* Restore the context of the new task.  The PSW (Program Status Word) and
-    PC will be popped by the RTE instruction. */
-    POP     R15
+     * PC will be popped by the RTE instruction. */
+    POP R15
     MVTACLO R15
-    POP     R15
+    POP R15
     MVTACHI R15
-    POPM    R1-R15
+    POPM R1 - R15
     RTE
     NOP
-    NOP
+        NOP
 }
 /*-----------------------------------------------------------*/
 
 void vPortEndScheduler( void )
 {
     /* Not implemented in ports where there is nothing to return to.
-    Artificially force an assert. */
+     * Artificially force an assert. */
     configASSERT( pxCurrentTCB == NULL );
 
     /* The following line is just to prevent the symbol getting optimised away. */
diff --git a/portable/Renesas/RX200/portmacro.h b/portable/Renesas/RX200/portmacro.h
index 55278dacb..c768be9ec 100644
--- a/portable/Renesas/RX200/portmacro.h
+++ b/portable/Renesas/RX200/portmacro.h
@@ -50,93 +50,93 @@
  */
 
 /* Type definitions - these are a bit legacy and not really used now, other than
-portSTACK_TYPE and portBASE_TYPE. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint32_t
-#define portBASE_TYPE   long
+ * portSTACK_TYPE and portBASE_TYPE. */
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-    not need to be guarded with a critical section. */
-    #define portTICK_TYPE_IS_ATOMIC 1
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+    #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portBYTE_ALIGNMENT              8   /* Could make four, according to manual. */
-#define portSTACK_GROWTH                -1
-#define portTICK_PERIOD_MS              ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portNOP()                       nop()
+#define portBYTE_ALIGNMENT    8             /* Could make four, according to manual. */
+#define portSTACK_GROWTH      -1
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()    nop()
 
 #pragma inline_asm vPortYield
 static void vPortYield( void )
 {
     /* Save clobbered register - may not actually be necessary if inline asm
-    functions are considered to use the same rules as function calls by the
-    compiler. */
+     * functions are considered to use the same rules as function calls by the
+     * compiler. */
     PUSH.L R5
     /* Set ITU SWINTR. */
-    MOV.L #553696, R5
-    MOV.B #1, [R5]
+    MOV.L # 553696, R5
+        MOV.B # 1, [ R5 ]
     /* Read back to ensure the value is taken before proceeding. */
-    MOV.L [R5], R5
+    MOV.L[ R5 ], R5
     /* Restore clobbered register to its previous value. */
     POP R5
 }
-#define portYIELD() vPortYield()
-#define portYIELD_FROM_ISR( x ) do { if( x != pdFALSE ) portYIELD(); } while( 0 )
+#define portYIELD()                                       vPortYield()
+#define portYIELD_FROM_ISR( x )                           do { if( x != pdFALSE ) portYIELD( ); } while( 0 )
 
 /* These macros should not be called directly, but through the
-taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
-performed if configASSERT() is defined to ensure an assertion handler does not
-inadvertently attempt to lower the IPL when the call to assert was triggered
-because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
-when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
-functions are those that end in FromISR.  FreeRTOS maintains a separate
-interrupt API to ensure API function and interrupt entry is as fast and as
-simple as possible. */
-#define portENABLE_INTERRUPTS()     set_ipl( ( long ) 0 )
+ * taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
+ * performed if configASSERT() is defined to ensure an assertion handler does not
+ * inadvertently attempt to lower the IPL when the call to assert was triggered
+ * because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
+ * when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
+ * functions are those that end in FromISR.  FreeRTOS maintains a separate
+ * interrupt API to ensure API function and interrupt entry is as fast and as
+ * simple as possible. */
+#define portENABLE_INTERRUPTS()                           set_ipl( ( long ) 0 )
 #ifdef configASSERT
-    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( get_ipl() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
-    #define portDISABLE_INTERRUPTS()    if( get_ipl() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    configASSERT( ( get_ipl() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+    #define portDISABLE_INTERRUPTS()                      if( get_ipl() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
 #else
-    #define portDISABLE_INTERRUPTS()    set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+    #define portDISABLE_INTERRUPTS()                      set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
 #endif
 
 /* Critical nesting counts are stored in the TCB. */
-#define portCRITICAL_NESTING_IN_TCB ( 1 )
+#define portCRITICAL_NESTING_IN_TCB    ( 1 )
 
 /* The critical nesting functions defined within tasks.c. */
 extern void vTaskEnterCritical( void );
 extern void vTaskExitCritical( void );
-#define portENTER_CRITICAL()    vTaskEnterCritical()
-#define portEXIT_CRITICAL()     vTaskExitCritical()
+#define portENTER_CRITICAL()                                           vTaskEnterCritical()
+#define portEXIT_CRITICAL()                                            vTaskExitCritical()
 
 /* As this port allows interrupt nesting... */
-#define portSET_INTERRUPT_MASK_FROM_ISR() get_ipl(); set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) set_ipl( ( long ) uxSavedInterruptStatus )
+#define portSET_INTERRUPT_MASK_FROM_ISR()                              get_ipl(); set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus )    set_ipl( ( long ) uxSavedInterruptStatus )
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/Renesas/RX600/port.c b/portable/Renesas/RX600/port.c
index 5438f5764..5fca0d72d 100644
--- a/portable/Renesas/RX600/port.c
+++ b/portable/Renesas/RX600/port.c
@@ -27,8 +27,8 @@
  */
 
 /*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the RX600 port.
- *----------------------------------------------------------*/
+* Implementation of functions defined in portable.h for the RX600 port.
+*----------------------------------------------------------*/
 
 /* Scheduler includes. */
 #include "FreeRTOS.h"
@@ -43,15 +43,15 @@
 /*-----------------------------------------------------------*/
 
 /* Tasks should start with interrupts enabled and in Supervisor mode, therefore
-PSW is set with U and I set, and PM and IPL clear. */
+ * PSW is set with U and I set, and PM and IPL clear. */
 #define portINITIAL_PSW     ( ( StackType_t ) 0x00030000 )
 #define portINITIAL_FPSW    ( ( StackType_t ) 0x00000100 )
 
 /*-----------------------------------------------------------*/
 
 /* The following lines are to ensure vSoftwareInterruptEntry can be referenced,
- and therefore installed in the vector table, when the FreeRTOS code is built
-as a library. */
+ * and therefore installed in the vector table, when the FreeRTOS code is built
+ * as a library. */
 extern BaseType_t vSoftwareInterruptEntry;
 const BaseType_t * p_vSoftwareInterruptEntry = &vSoftwareInterruptEntry;
 
@@ -81,8 +81,8 @@ void vSoftwareInterruptISR( void );
 /*-----------------------------------------------------------*/
 
 /* This is accessed by the inline assembler functions so is file scope for
-convenience. */
-extern void *pxCurrentTCB;
+ * convenience. */
+extern void * pxCurrentTCB;
 extern void vTaskSwitchContext( void );
 
 /*-----------------------------------------------------------*/
@@ -90,7 +90,9 @@ extern void vTaskSwitchContext( void );
 /*
  * See header file for description.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
     /* R0 is not included as it is the stack pointer. */
 
@@ -101,8 +103,8 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
     *pxTopOfStack = ( StackType_t ) pxCode;
 
     /* When debugging it can be useful if every register is set to a known
-    value.  Otherwise code space can be saved by just setting the registers
-    that need to be set. */
+     * value.  Otherwise code space can be saved by just setting the registers
+     * that need to be set. */
     #ifdef USE_FULL_REGISTER_INITIALISATION
     {
         pxTopOfStack--;
@@ -135,11 +137,11 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
         *pxTopOfStack = 0x22222222;
         pxTopOfStack--;
     }
-    #else
+    #else /* ifdef USE_FULL_REGISTER_INITIALISATION */
     {
         pxTopOfStack -= 15;
     }
-    #endif
+    #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */
 
     *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
     pxTopOfStack--;
@@ -155,14 +157,14 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
 
 BaseType_t xPortStartScheduler( void )
 {
-extern void vApplicationSetupTimerInterrupt( void );
+    extern void vApplicationSetupTimerInterrupt( void );
 
     /* Use pxCurrentTCB just so it does not get optimised away. */
     if( pxCurrentTCB != NULL )
     {
         /* Call an application function to set up the timer that will generate the
-        tick interrupt.  This way the application can decide which peripheral to
-        use.  A demo application is provided to show a suitable example. */
+         * tick interrupt.  This way the application can decide which peripheral to
+         * use.  A demo application is provided to show a suitable example. */
         vApplicationSetupTimerInterrupt();
 
         /* Enable the software interrupt. */
@@ -190,28 +192,28 @@ extern void vApplicationSetupTimerInterrupt( void );
 static void prvStartFirstTask( void )
 {
     /* When starting the scheduler there is nothing that needs moving to the
-    interrupt stack because the function is not called from an interrupt.
-    Just ensure the current stack is the user stack. */
-    SETPSW  U
+     * interrupt stack because the function is not called from an interrupt.
+     * Just ensure the current stack is the user stack. */
+    SETPSW U
 
     /* Obtain the location of the stack associated with which ever task
-    pxCurrentTCB is currently pointing to. */
-    MOV.L   #_pxCurrentTCB, R15
-    MOV.L   [R15], R15
-    MOV.L   [R15], R0
+     * pxCurrentTCB is currently pointing to. */
+    MOV.L   # _pxCurrentTCB, R15
+        MOV.L[ R15 ], R15
+        MOV.L[ R15 ], R0
 
     /* Restore the registers from the stack of the task pointed to by
-    pxCurrentTCB. */
-    POP     R15
-    MVTACLO R15         /* Accumulator low 32 bits. */
-    POP     R15
-    MVTACHI R15         /* Accumulator high 32 bits. */
-    POP     R15
-    MVTC    R15,FPSW    /* Floating point status word. */
-    POPM    R1-R15      /* R1 to R15 - R0 is not included as it is the SP. */
-    RTE                 /* This pops the remaining registers. */
-    NOP
+     * pxCurrentTCB. */
+    POP R15
+    MVTACLO R15    /* Accumulator low 32 bits. */
+    POP R15
+    MVTACHI R15    /* Accumulator high 32 bits. */
+    POP R15
+    MVTC R15, FPSW /* Floating point status word. */
+    POPM R1 - R15  /* R1 to R15 - R0 is not included as it is the SP. */
+    RTE            /* This pops the remaining registers. */
     NOP
+        NOP
 }
 /*-----------------------------------------------------------*/
 
@@ -219,7 +221,7 @@ static void prvStartFirstTask( void )
 void vTickISR( void )
 {
     /* Increment the tick, and perform any processing the new tick value
-    necessitates. */
+     * necessitates. */
     set_ipl( configMAX_SYSCALL_INTERRUPT_PRIORITY );
     {
         if( xTaskIncrementTick() != pdFALSE )
@@ -227,6 +229,7 @@ void vTickISR( void )
             taskYIELD();
         }
     }
+
     set_ipl( configKERNEL_INTERRUPT_PRIORITY );
 }
 /*-----------------------------------------------------------*/
@@ -241,84 +244,90 @@ void vSoftwareInterruptISR( void )
 static void prvYieldHandler( void )
 {
     /* Re-enable interrupts. */
-    SETPSW  I
+    SETPSW I
 
     /* Move the data that was automatically pushed onto the interrupt stack when
-    the interrupt occurred from the interrupt stack to the user stack.
-
-    R15 is saved before it is clobbered. */
-    PUSH.L  R15
+     * the interrupt occurred from the interrupt stack to the user stack.
+     *
+     * R15 is saved before it is clobbered. */
+    PUSH.L R15
 
     /* Read the user stack pointer. */
-    MVFC    USP, R15
+    MVFC USP, R15
 
     /* Move the address down to the data being moved. */
-    SUB     #12, R15
-    MVTC    R15, USP
+         SUB     # 12, R15
+    MVTC R15, USP
 
     /* Copy the data across. */
-    MOV.L   [ R0 ], [ R15 ] ; R15
-    MOV.L   4[ R0 ], 4[ R15 ]  ; PC
-    MOV.L   8[ R0 ], 8[ R15 ]  ; PSW
+         MOV.L[ R0 ], [ R15 ];
+    R15
+
+    MOV.L   4[ R0 ], 4[ R15 ];
+    PC
+    MOV.L   8[ R0 ], 8[ R15 ];
+    PSW
 
     /* Move the interrupt stack pointer to its new correct position. */
-    ADD #12, R0
+        ADD # 12, R0
 
     /* All the rest of the registers are saved directly to the user stack. */
-    SETPSW  U
+    SETPSW U
 
     /* Save the rest of the general registers (R15 has been saved already). */
-    PUSHM   R1-R14
+    PUSHM R1 - R14
 
     /* Save the FPSW and accumulator. */
-    MVFC    FPSW, R15
-    PUSH.L  R15
+    MVFC FPSW, R15
+        PUSH.L R15
     MVFACHI R15
-    PUSH.L  R15
-    MVFACMI R15 ; Middle order word.
-    SHLL    #16, R15 ; Shifted left as it is restored to the low order word.
-    PUSH.L  R15
+        PUSH.L R15
+    MVFACMI R15;
+    Middle order word.
+       SHLL    # 16, R15;
+    Shifted left as it is restored to the low order word.
+       PUSH.L R15
 
     /* Save the stack pointer to the TCB. */
-    MOV.L   #_pxCurrentTCB, R15
-    MOV.L   [ R15 ], R15
-    MOV.L   R0, [ R15 ]
+    MOV.L   # _pxCurrentTCB, R15
+        MOV.L[ R15 ], R15
+        MOV.L R0, [ R15 ]
 
     /* Ensure the interrupt mask is set to the syscall priority while the kernel
-    structures are being accessed. */
-    MVTIPL  #configMAX_SYSCALL_INTERRUPT_PRIORITY
+     * structures are being accessed. */
+    MVTIPL  # configMAX_SYSCALL_INTERRUPT_PRIORITY
 
     /* Select the next task to run. */
-    BSR.A   _vTaskSwitchContext
+    BSR.A _vTaskSwitchContext
 
     /* Reset the interrupt mask as no more data structure access is required. */
-    MVTIPL  #configKERNEL_INTERRUPT_PRIORITY
+    MVTIPL  # configKERNEL_INTERRUPT_PRIORITY
 
     /* Load the stack pointer of the task that is now selected as the Running
-    state task from its TCB. */
-    MOV.L   #_pxCurrentTCB,R15
-    MOV.L   [ R15 ], R15
-    MOV.L   [ R15 ], R0
+     * state task from its TCB. */
+    MOV.L   # _pxCurrentTCB, R15
+        MOV.L[ R15 ], R15
+        MOV.L[ R15 ], R0
 
     /* Restore the context of the new task.  The PSW (Program Status Word) and
-    PC will be popped by the RTE instruction. */
-    POP     R15
+     * PC will be popped by the RTE instruction. */
+    POP R15
     MVTACLO R15
-    POP     R15
+    POP R15
     MVTACHI R15
-    POP     R15
-    MVTC    R15,FPSW
-    POPM    R1-R15
+    POP R15
+    MVTC R15, FPSW
+    POPM R1 - R15
     RTE
     NOP
-    NOP
+        NOP
 }
 /*-----------------------------------------------------------*/
 
 void vPortEndScheduler( void )
 {
     /* Not implemented in ports where there is nothing to return to.
-    Artificially force an assert. */
+     * Artificially force an assert. */
     configASSERT( pxCurrentTCB == NULL );
 
     /* The following line is just to prevent the symbol getting optimised away. */
diff --git a/portable/Renesas/RX600/portmacro.h b/portable/Renesas/RX600/portmacro.h
index 60106ae13..9e5ed59db 100644
--- a/portable/Renesas/RX600/portmacro.h
+++ b/portable/Renesas/RX600/portmacro.h
@@ -50,94 +50,94 @@
  */
 
 /* Type definitions - these are a bit legacy and not really used now, other than
-portSTACK_TYPE and portBASE_TYPE. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint32_t
-#define portBASE_TYPE   long
+ * portSTACK_TYPE and portBASE_TYPE. */
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-    not need to be guarded with a critical section. */
-    #define portTICK_TYPE_IS_ATOMIC 1
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+    #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portBYTE_ALIGNMENT              8   /* Could make four, according to manual. */
-#define portSTACK_GROWTH                -1
-#define portTICK_PERIOD_MS              ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portNOP()                       nop()
+#define portBYTE_ALIGNMENT    8             /* Could make four, according to manual. */
+#define portSTACK_GROWTH      -1
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()    nop()
 
 
 #pragma inline_asm vPortYield
 static void vPortYield( void )
 {
     /* Save clobbered register - may not actually be necessary if inline asm
-    functions are considered to use the same rules as function calls by the
-    compiler. */
+     * functions are considered to use the same rules as function calls by the
+     * compiler. */
     PUSH.L R5
     /* Set ITU SWINTR. */
-    MOV.L #553696, R5
-    MOV.B #1, [R5]
+    MOV.L # 553696, R5
+        MOV.B # 1, [ R5 ]
     /* Read back to ensure the value is taken before proceeding. */
-    MOV.L [R5], R5
+    MOV.L[ R5 ], R5
     /* Restore clobbered register to its previous value. */
     POP R5
 }
-#define portYIELD() vPortYield()
-#define portYIELD_FROM_ISR( x ) do { if( x != pdFALSE ) portYIELD(); } while( 0 )
+#define portYIELD()                                       vPortYield()
+#define portYIELD_FROM_ISR( x )                           do { if( x != pdFALSE ) portYIELD( ); } while( 0 )
 
 /* These macros should not be called directly, but through the
-taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
-performed if configASSERT() is defined to ensure an assertion handler does not
-inadvertently attempt to lower the IPL when the call to assert was triggered
-because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
-when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
-functions are those that end in FromISR.  FreeRTOS maintains a separate
-interrupt API to ensure API function and interrupt entry is as fast and as
-simple as possible. */
-#define portENABLE_INTERRUPTS()     set_ipl( ( long ) 0 )
+ * taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
+ * performed if configASSERT() is defined to ensure an assertion handler does not
+ * inadvertently attempt to lower the IPL when the call to assert was triggered
+ * because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
+ * when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
+ * functions are those that end in FromISR.  FreeRTOS maintains a separate
+ * interrupt API to ensure API function and interrupt entry is as fast and as
+ * simple as possible. */
+#define portENABLE_INTERRUPTS()                           set_ipl( ( long ) 0 )
 #ifdef configASSERT
-    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( get_ipl() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
-    #define portDISABLE_INTERRUPTS()    if( get_ipl() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    configASSERT( ( get_ipl() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+    #define portDISABLE_INTERRUPTS()                      if( get_ipl() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
 #else
-    #define portDISABLE_INTERRUPTS()    set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+    #define portDISABLE_INTERRUPTS()                      set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
 #endif
 
 /* Critical nesting counts are stored in the TCB. */
-#define portCRITICAL_NESTING_IN_TCB ( 1 )
+#define portCRITICAL_NESTING_IN_TCB    ( 1 )
 
 /* The critical nesting functions defined within tasks.c. */
 extern void vTaskEnterCritical( void );
 extern void vTaskExitCritical( void );
-#define portENTER_CRITICAL()    vTaskEnterCritical()
-#define portEXIT_CRITICAL()     vTaskExitCritical()
+#define portENTER_CRITICAL()                                           vTaskEnterCritical()
+#define portEXIT_CRITICAL()                                            vTaskExitCritical()
 
 /* As this port allows interrupt nesting... */
-#define portSET_INTERRUPT_MASK_FROM_ISR() get_ipl(); set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) set_ipl( ( long ) uxSavedInterruptStatus )
+#define portSET_INTERRUPT_MASK_FROM_ISR()                              get_ipl(); set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus )    set_ipl( ( long ) uxSavedInterruptStatus )
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/Renesas/RX600v2/port.c b/portable/Renesas/RX600v2/port.c
index ee7da87e6..39136f882 100644
--- a/portable/Renesas/RX600v2/port.c
+++ b/portable/Renesas/RX600v2/port.c
@@ -27,8 +27,8 @@
  */
 
 /*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the RX600 port.
- *----------------------------------------------------------*/
+* Implementation of functions defined in portable.h for the RX600 port.
+*----------------------------------------------------------*/
 
 /* Scheduler includes. */
 #include "FreeRTOS.h"
@@ -47,15 +47,15 @@
 /*-----------------------------------------------------------*/
 
 /* Tasks should start with interrupts enabled and in Supervisor mode, therefore
-PSW is set with U and I set, and PM and IPL clear. */
+ * PSW is set with U and I set, and PM and IPL clear. */
 #define portINITIAL_PSW     ( ( StackType_t ) 0x00030000 )
 #define portINITIAL_FPSW    ( ( StackType_t ) 0x00000100 )
 
 /*-----------------------------------------------------------*/
 
 /* The following lines are to ensure vSoftwareInterruptEntry can be referenced,
- and therefore installed in the vector table, when the FreeRTOS code is built
-as a library. */
+ * and therefore installed in the vector table, when the FreeRTOS code is built
+ * as a library. */
 extern BaseType_t vSoftwareInterruptEntry;
 const BaseType_t * p_vSoftwareInterruptEntry = &vSoftwareInterruptEntry;
 
@@ -85,8 +85,8 @@ void vSoftwareInterruptISR( void );
 /*-----------------------------------------------------------*/
 
 /* This is accessed by the inline assembler functions so is file scope for
-convenience. */
-extern void *pxCurrentTCB;
+ * convenience. */
+extern void * pxCurrentTCB;
 extern void vTaskSwitchContext( void );
 
 /*-----------------------------------------------------------*/
@@ -94,7 +94,9 @@ extern void vTaskSwitchContext( void );
 /*
  * See header file for description.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
     /* R0 is not included as it is the stack pointer. */
 
@@ -105,8 +107,8 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
     *pxTopOfStack = ( StackType_t ) pxCode;
 
     /* When debugging it can be useful if every register is set to a known
-    value.  Otherwise code space can be saved by just setting the registers
-    that need to be set. */
+     * value.  Otherwise code space can be saved by just setting the registers
+     * that need to be set. */
     #ifdef USE_FULL_REGISTER_INITIALISATION
     {
         pxTopOfStack--;
@@ -139,11 +141,11 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
         *pxTopOfStack = 0x22222222;
         pxTopOfStack--;
     }
-    #else
+    #else /* ifdef USE_FULL_REGISTER_INITIALISATION */
     {
         pxTopOfStack -= 15;
     }
-    #endif
+    #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */
 
     *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
     pxTopOfStack--;
@@ -167,14 +169,14 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
 
 BaseType_t xPortStartScheduler( void )
 {
-extern void vApplicationSetupTimerInterrupt( void );
+    extern void vApplicationSetupTimerInterrupt( void );
 
     /* Use pxCurrentTCB just so it does not get optimised away. */
     if( pxCurrentTCB != NULL )
     {
         /* Call an application function to set up the timer that will generate the
-        tick interrupt.  This way the application can decide which peripheral to
-        use.  A demo application is provided to show a suitable example. */
+         * tick interrupt.  This way the application can decide which peripheral to
+         * use.  A demo application is provided to show a suitable example. */
         vApplicationSetupTimerInterrupt();
 
         /* Enable the software interrupt. */
@@ -202,36 +204,36 @@ extern void vApplicationSetupTimerInterrupt( void );
 static void prvStartFirstTask( void )
 {
     /* When starting the scheduler there is nothing that needs moving to the
-    interrupt stack because the function is not called from an interrupt.
-    Just ensure the current stack is the user stack. */
-    SETPSW  U
+     * interrupt stack because the function is not called from an interrupt.
+     * Just ensure the current stack is the user stack. */
+    SETPSW U
 
     /* Obtain the location of the stack associated with which ever task
-    pxCurrentTCB is currently pointing to. */
-    MOV.L   #_pxCurrentTCB, R15
-    MOV.L   [R15], R15
-    MOV.L   [R15], R0
+     * pxCurrentTCB is currently pointing to. */
+    MOV.L   # _pxCurrentTCB, R15
+        MOV.L[ R15 ], R15
+        MOV.L[ R15 ], R0
 
     /* Restore the registers from the stack of the task pointed to by
-    pxCurrentTCB. */
-    POP     R15
-    MVTACLO R15, A0     /* Accumulator low 32 bits. */
-    POP     R15
-    MVTACHI R15, A0     /* Accumulator high 32 bits. */
-    POP     R15
-    MVTACGU R15, A0     /* Accumulator guard. */
-    POP     R15
-    MVTACLO R15, A1     /* Accumulator low 32 bits. */
-    POP     R15
-    MVTACHI R15, A1     /* Accumulator high 32 bits. */
-    POP     R15
-    MVTACGU R15, A1     /* Accumulator guard. */
-    POP     R15
-    MVTC    R15,FPSW    /* Floating point status word. */
-    POPM    R1-R15      /* R1 to R15 - R0 is not included as it is the SP. */
-    RTE                 /* This pops the remaining registers. */
-    NOP
+     * pxCurrentTCB. */
+    POP R15
+    MVTACLO R15, A0 /* Accumulator low 32 bits. */
+    POP R15
+    MVTACHI R15, A0 /* Accumulator high 32 bits. */
+    POP R15
+    MVTACGU R15, A0 /* Accumulator guard. */
+    POP R15
+    MVTACLO R15, A1 /* Accumulator low 32 bits. */
+    POP R15
+    MVTACHI R15, A1 /* Accumulator high 32 bits. */
+    POP R15
+    MVTACGU R15, A1 /* Accumulator guard. */
+    POP R15
+    MVTC R15, FPSW  /* Floating point status word. */
+    POPM R1 - R15   /* R1 to R15 - R0 is not included as it is the SP. */
+    RTE             /* This pops the remaining registers. */
     NOP
+        NOP
 }
 /*-----------------------------------------------------------*/
 
@@ -239,7 +241,7 @@ static void prvStartFirstTask( void )
 void vTickISR( void )
 {
     /* Increment the tick, and perform any processing the new tick value
-    necessitates. */
+     * necessitates. */
     set_ipl( configMAX_SYSCALL_INTERRUPT_PRIORITY );
     {
         if( xTaskIncrementTick() != pdFALSE )
@@ -247,6 +249,7 @@ void vTickISR( void )
             taskYIELD();
         }
     }
+
     set_ipl( configKERNEL_INTERRUPT_PRIORITY );
 }
 /*-----------------------------------------------------------*/
@@ -261,99 +264,105 @@ void vSoftwareInterruptISR( void )
 static void prvYieldHandler( void )
 {
     /* Re-enable interrupts. */
-    SETPSW  I
+    SETPSW I
 
     /* Move the data that was automatically pushed onto the interrupt stack when
-    the interrupt occurred from the interrupt stack to the user stack.
-
-    R15 is saved before it is clobbered. */
-    PUSH.L  R15
+     * the interrupt occurred from the interrupt stack to the user stack.
+     *
+     * R15 is saved before it is clobbered. */
+    PUSH.L R15
 
     /* Read the user stack pointer. */
-    MVFC    USP, R15
+    MVFC USP, R15
 
     /* Move the address down to the data being moved. */
-    SUB     #12, R15
-    MVTC    R15, USP
+         SUB     # 12, R15
+    MVTC R15, USP
 
     /* Copy the data across. */
-    MOV.L   [ R0 ], [ R15 ] ; R15
-    MOV.L   4[ R0 ], 4[ R15 ]  ; PC
-    MOV.L   8[ R0 ], 8[ R15 ]  ; PSW
+         MOV.L[ R0 ], [ R15 ];
+    R15
+
+    MOV.L   4[ R0 ], 4[ R15 ];
+    PC
+    MOV.L   8[ R0 ], 8[ R15 ];
+    PSW
 
     /* Move the interrupt stack pointer to its new correct position. */
-    ADD #12, R0
+        ADD # 12, R0
 
     /* All the rest of the registers are saved directly to the user stack. */
-    SETPSW  U
+    SETPSW U
 
     /* Save the rest of the general registers (R15 has been saved already). */
-    PUSHM   R1-R14
+    PUSHM R1 - R14
 
     /* Save the FPSW and accumulators. */
-    MVFC    FPSW, R15
-    PUSH.L  R15
-    MVFACGU #0, A1, R15
-    PUSH.L  R15
-    MVFACHI #0, A1, R15
-    PUSH.L  R15
-    MVFACLO #0, A1, R15 ; Low order word.
-    PUSH.L  R15
-    MVFACGU #0, A0, R15
-    PUSH.L  R15
-    MVFACHI #0, A0, R15
-    PUSH.L  R15
-    MVFACLO #0, A0, R15 ; Low order word.
-    PUSH.L  R15
+    MVFC FPSW, R15
+        PUSH.L R15
+        MVFACGU # 0, A1, R15
+        PUSH.L R15
+        MVFACHI # 0, A1, R15
+        PUSH.L R15
+        MVFACLO # 0, A1, R15;
+    Low order word.
+       PUSH.L R15
+        MVFACGU # 0, A0, R15
+        PUSH.L R15
+        MVFACHI # 0, A0, R15
+        PUSH.L R15
+        MVFACLO # 0, A0, R15;
+    Low order word.
+       PUSH.L R15
 
     /* Save the stack pointer to the TCB. */
-    MOV.L   #_pxCurrentTCB, R15
-    MOV.L   [ R15 ], R15
-    MOV.L   R0, [ R15 ]
+    MOV.L   # _pxCurrentTCB, R15
+        MOV.L[ R15 ], R15
+        MOV.L R0, [ R15 ]
 
     /* Ensure the interrupt mask is set to the syscall priority while the kernel
-    structures are being accessed. */
-    MVTIPL  #configMAX_SYSCALL_INTERRUPT_PRIORITY
+     * structures are being accessed. */
+    MVTIPL  # configMAX_SYSCALL_INTERRUPT_PRIORITY
 
     /* Select the next task to run. */
-    BSR.A   _vTaskSwitchContext
+    BSR.A _vTaskSwitchContext
 
     /* Reset the interrupt mask as no more data structure access is required. */
-    MVTIPL  #configKERNEL_INTERRUPT_PRIORITY
+    MVTIPL  # configKERNEL_INTERRUPT_PRIORITY
 
     /* Load the stack pointer of the task that is now selected as the Running
-    state task from its TCB. */
-    MOV.L   #_pxCurrentTCB,R15
-    MOV.L   [ R15 ], R15
-    MOV.L   [ R15 ], R0
+     * state task from its TCB. */
+    MOV.L   # _pxCurrentTCB, R15
+        MOV.L[ R15 ], R15
+        MOV.L[ R15 ], R0
 
     /* Restore the context of the new task.  The PSW (Program Status Word) and
-    PC will be popped by the RTE instruction. */
-    POP     R15
-    MVTACLO R15, A0     /* Accumulator low 32 bits. */
-    POP     R15
-    MVTACHI R15, A0     /* Accumulator high 32 bits. */
-    POP     R15
-    MVTACGU R15, A0     /* Accumulator guard. */
-    POP     R15
-    MVTACLO R15, A1     /* Accumulator low 32 bits. */
-    POP     R15
-    MVTACHI R15, A1     /* Accumulator high 32 bits. */
-    POP     R15
-    MVTACGU R15, A1     /* Accumulator guard. */
-    POP     R15
-    MVTC    R15,FPSW
-    POPM    R1-R15
+     * PC will be popped by the RTE instruction. */
+    POP R15
+    MVTACLO R15, A0 /* Accumulator low 32 bits. */
+    POP R15
+    MVTACHI R15, A0 /* Accumulator high 32 bits. */
+    POP R15
+    MVTACGU R15, A0 /* Accumulator guard. */
+    POP R15
+    MVTACLO R15, A1 /* Accumulator low 32 bits. */
+    POP R15
+    MVTACHI R15, A1 /* Accumulator high 32 bits. */
+    POP R15
+    MVTACGU R15, A1 /* Accumulator guard. */
+    POP R15
+    MVTC R15, FPSW
+    POPM R1 - R15
     RTE
     NOP
-    NOP
+        NOP
 }
 /*-----------------------------------------------------------*/
 
 void vPortEndScheduler( void )
 {
     /* Not implemented in ports where there is nothing to return to.
-    Artificially force an assert. */
+     * Artificially force an assert. */
     configASSERT( pxCurrentTCB == NULL );
 
     /* The following line is just to prevent the symbol getting optimised away. */
diff --git a/portable/Renesas/RX600v2/portmacro.h b/portable/Renesas/RX600v2/portmacro.h
index 6efba647d..a35beaaca 100644
--- a/portable/Renesas/RX600v2/portmacro.h
+++ b/portable/Renesas/RX600v2/portmacro.h
@@ -50,94 +50,94 @@
  */
 
 /* Type definitions - these are a bit legacy and not really used now, other than
-portSTACK_TYPE and portBASE_TYPE. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint32_t
-#define portBASE_TYPE   long
+ * portSTACK_TYPE and portBASE_TYPE. */
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-    not need to be guarded with a critical section. */
-    #define portTICK_TYPE_IS_ATOMIC 1
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+    #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portBYTE_ALIGNMENT              8   /* Could make four, according to manual. */
-#define portSTACK_GROWTH                -1
-#define portTICK_PERIOD_MS              ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portNOP()                       nop()
+#define portBYTE_ALIGNMENT    8             /* Could make four, according to manual. */
+#define portSTACK_GROWTH      -1
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()    nop()
 
 
 #pragma inline_asm vPortYield
 static void vPortYield( void )
 {
     /* Save clobbered register - may not actually be necessary if inline asm
-    functions are considered to use the same rules as function calls by the
-    compiler. */
+     * functions are considered to use the same rules as function calls by the
+     * compiler. */
     PUSH.L R5
     /* Set ITU SWINTR. */
-    MOV.L #553696, R5
-    MOV.B #1, [R5]
+    MOV.L # 553696, R5
+        MOV.B # 1, [ R5 ]
     /* Read back to ensure the value is taken before proceeding. */
-    MOV.L [R5], R5
+    MOV.L[ R5 ], R5
     /* Restore clobbered register to its previous value. */
     POP R5
 }
-#define portYIELD() vPortYield()
-#define portYIELD_FROM_ISR( x ) do { if( x != pdFALSE ) portYIELD(); } while( 0 )
+#define portYIELD()                                       vPortYield()
+#define portYIELD_FROM_ISR( x )                           do { if( x != pdFALSE ) portYIELD( ); } while( 0 )
 
 /* These macros should not be called directly, but through the
-taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
-performed if configASSERT() is defined to ensure an assertion handler does not
-inadvertently attempt to lower the IPL when the call to assert was triggered
-because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
-when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
-functions are those that end in FromISR.  FreeRTOS maintains a separate
-interrupt API to ensure API function and interrupt entry is as fast and as
-simple as possible. */
-#define portENABLE_INTERRUPTS()     set_ipl( ( long ) 0 )
+ * taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
+ * performed if configASSERT() is defined to ensure an assertion handler does not
+ * inadvertently attempt to lower the IPL when the call to assert was triggered
+ * because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
+ * when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
+ * functions are those that end in FromISR.  FreeRTOS maintains a separate
+ * interrupt API to ensure API function and interrupt entry is as fast and as
+ * simple as possible. */
+#define portENABLE_INTERRUPTS()                           set_ipl( ( long ) 0 )
 #ifdef configASSERT
-    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( get_ipl() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
-    #define portDISABLE_INTERRUPTS()    if( get_ipl() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    configASSERT( ( get_ipl() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+    #define portDISABLE_INTERRUPTS()                      if( get_ipl() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
 #else
-    #define portDISABLE_INTERRUPTS()    set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+    #define portDISABLE_INTERRUPTS()                      set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
 #endif
 
 /* Critical nesting counts are stored in the TCB. */
-#define portCRITICAL_NESTING_IN_TCB ( 1 )
+#define portCRITICAL_NESTING_IN_TCB    ( 1 )
 
 /* The critical nesting functions defined within tasks.c. */
 extern void vTaskEnterCritical( void );
 extern void vTaskExitCritical( void );
-#define portENTER_CRITICAL()    vTaskEnterCritical()
-#define portEXIT_CRITICAL()     vTaskExitCritical()
+#define portENTER_CRITICAL()                                           vTaskEnterCritical()
+#define portEXIT_CRITICAL()                                            vTaskExitCritical()
 
 /* As this port allows interrupt nesting... */
-#define portSET_INTERRUPT_MASK_FROM_ISR() ( UBaseType_t ) get_ipl(); set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) set_ipl( ( long ) uxSavedInterruptStatus )
+#define portSET_INTERRUPT_MASK_FROM_ISR()                              ( UBaseType_t ) get_ipl(); set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus )    set_ipl( ( long ) uxSavedInterruptStatus )
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/Renesas/RX700v3_DPFPU/port.c b/portable/Renesas/RX700v3_DPFPU/port.c
index 26cb9f020..99f14c7aa 100644
--- a/portable/Renesas/RX700v3_DPFPU/port.c
+++ b/portable/Renesas/RX700v3_DPFPU/port.c
@@ -54,22 +54,22 @@
 
 /* Tasks should start with interrupts enabled and in Supervisor mode, therefore
  * PSW is set with U and I set, and PM and IPL clear. */
-#define portINITIAL_PSW     ( ( StackType_t ) 0x00030000 )
-#define portINITIAL_FPSW    ( ( StackType_t ) 0x00000100 )
-#define portINITIAL_DPSW    ( ( StackType_t ) 0x00000100 )
-#define portINITIAL_DCMR    ( ( StackType_t ) 0x00000000 )
-#define portINITIAL_DECNT   ( ( StackType_t ) 0x00000001 )
+#define portINITIAL_PSW                  ( ( StackType_t ) 0x00030000 )
+#define portINITIAL_FPSW                 ( ( StackType_t ) 0x00000100 )
+#define portINITIAL_DPSW                 ( ( StackType_t ) 0x00000100 )
+#define portINITIAL_DCMR                 ( ( StackType_t ) 0x00000000 )
+#define portINITIAL_DECNT                ( ( StackType_t ) 0x00000001 )
 
 /* Tasks are not created with a DPFPU context, but can be given a DPFPU context
  * after they have been created.  A variable is stored as part of the tasks context
  * that holds portNO_DPFPU_CONTEXT if the task does not have a DPFPU context, or
  * any other value if the task does have a DPFPU context. */
-#define portNO_DPFPU_CONTEXT    ( ( StackType_t ) 0 )
-#define portHAS_DPFPU_CONTEXT   ( ( StackType_t ) 1 )
+#define portNO_DPFPU_CONTEXT             ( ( StackType_t ) 0 )
+#define portHAS_DPFPU_CONTEXT            ( ( StackType_t ) 1 )
 
 /* The space on the stack required to hold the DPFPU data registers.  This is 16
  * 64-bit registers. */
-#define portDPFPU_DATA_REGISTER_WORDS   ( 16 * 2 )
+#define portDPFPU_DATA_REGISTER_WORDS    ( 16 * 2 )
 
 /*-----------------------------------------------------------*/
 
@@ -144,41 +144,41 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
      * value.  Otherwise code space can be saved by just setting the registers
      * that need to be set. */
     #ifdef USE_FULL_REGISTER_INITIALISATION
-        {
-            pxTopOfStack--;
-            *pxTopOfStack = 0xffffffff; /* r15. */
-            pxTopOfStack--;
-            *pxTopOfStack = 0xeeeeeeee;
-            pxTopOfStack--;
-            *pxTopOfStack = 0xdddddddd;
-            pxTopOfStack--;
-            *pxTopOfStack = 0xcccccccc;
-            pxTopOfStack--;
-            *pxTopOfStack = 0xbbbbbbbb;
-            pxTopOfStack--;
-            *pxTopOfStack = 0xaaaaaaaa;
-            pxTopOfStack--;
-            *pxTopOfStack = 0x99999999;
-            pxTopOfStack--;
-            *pxTopOfStack = 0x88888888;
-            pxTopOfStack--;
-            *pxTopOfStack = 0x77777777;
-            pxTopOfStack--;
-            *pxTopOfStack = 0x66666666;
-            pxTopOfStack--;
-            *pxTopOfStack = 0x55555555;
-            pxTopOfStack--;
-            *pxTopOfStack = 0x44444444;
-            pxTopOfStack--;
-            *pxTopOfStack = 0x33333333;
-            pxTopOfStack--;
-            *pxTopOfStack = 0x22222222;
-            pxTopOfStack--;
-        }
+    {
+        pxTopOfStack--;
+        *pxTopOfStack = 0xffffffff; /* r15. */
+        pxTopOfStack--;
+        *pxTopOfStack = 0xeeeeeeee;
+        pxTopOfStack--;
+        *pxTopOfStack = 0xdddddddd;
+        pxTopOfStack--;
+        *pxTopOfStack = 0xcccccccc;
+        pxTopOfStack--;
+        *pxTopOfStack = 0xbbbbbbbb;
+        pxTopOfStack--;
+        *pxTopOfStack = 0xaaaaaaaa;
+        pxTopOfStack--;
+        *pxTopOfStack = 0x99999999;
+        pxTopOfStack--;
+        *pxTopOfStack = 0x88888888;
+        pxTopOfStack--;
+        *pxTopOfStack = 0x77777777;
+        pxTopOfStack--;
+        *pxTopOfStack = 0x66666666;
+        pxTopOfStack--;
+        *pxTopOfStack = 0x55555555;
+        pxTopOfStack--;
+        *pxTopOfStack = 0x44444444;
+        pxTopOfStack--;
+        *pxTopOfStack = 0x33333333;
+        pxTopOfStack--;
+        *pxTopOfStack = 0x22222222;
+        pxTopOfStack--;
+    }
     #else /* ifdef USE_FULL_REGISTER_INITIALISATION */
-        {
-            pxTopOfStack -= 15;
-        }
+    {
+        pxTopOfStack -= 15;
+    }
     #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */
 
     *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
@@ -198,73 +198,73 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
     *pxTopOfStack = 0x66666666; /* Accumulator 0. */
 
     #if ( configUSE_TASK_DPFPU_SUPPORT == 1 )
-        {
-            /* The task will start without a DPFPU context.  A task that
-             * uses the DPFPU hardware must call vPortTaskUsesDPFPU() before
-             * executing any floating point instructions. */
-            pxTopOfStack--;
-            *pxTopOfStack = portNO_DPFPU_CONTEXT;
-        }
+    {
+        /* The task will start without a DPFPU context.  A task that
+         * uses the DPFPU hardware must call vPortTaskUsesDPFPU() before
+         * executing any floating point instructions. */
+        pxTopOfStack--;
+        *pxTopOfStack = portNO_DPFPU_CONTEXT;
+    }
     #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 )
+    {
+        /* The task will start with a DPFPU context.  Leave enough
+         * space for the registers - and ensure they are initialised if desired. */
+        #ifdef USE_FULL_REGISTER_INITIALISATION
         {
-            /* The task will start with a DPFPU context.  Leave enough
-             * space for the registers - and ensure they are initialised if desired. */
-            #ifdef USE_FULL_REGISTER_INITIALISATION
-                {
-                    pxTopOfStack -= 2;
-                    *(double *)pxTopOfStack = 1515.1515; /* DR15. */
-                    pxTopOfStack -= 2;
-                    *(double *)pxTopOfStack = 1414.1414; /* DR14. */
-                    pxTopOfStack -= 2;
-                    *(double *)pxTopOfStack = 1313.1313; /* DR13. */
-                    pxTopOfStack -= 2;
-                    *(double *)pxTopOfStack = 1212.1212; /* DR12. */
-                    pxTopOfStack -= 2;
-                    *(double *)pxTopOfStack = 1111.1111; /* DR11. */
-                    pxTopOfStack -= 2;
-                    *(double *)pxTopOfStack = 1010.1010; /* DR10. */
-                    pxTopOfStack -= 2;
-                    *(double *)pxTopOfStack =  909.0909; /* DR9. */
-                    pxTopOfStack -= 2;
-                    *(double *)pxTopOfStack =  808.0808; /* DR8. */
-                    pxTopOfStack -= 2;
-                    *(double *)pxTopOfStack =  707.0707; /* DR7. */
-                    pxTopOfStack -= 2;
-                    *(double *)pxTopOfStack =  606.0606; /* DR6. */
-                    pxTopOfStack -= 2;
-                    *(double *)pxTopOfStack =  505.0505; /* DR5. */
-                    pxTopOfStack -= 2;
-                    *(double *)pxTopOfStack =  404.0404; /* DR4. */
-                    pxTopOfStack -= 2;
-                    *(double *)pxTopOfStack =  303.0303; /* DR3. */
-                    pxTopOfStack -= 2;
-                    *(double *)pxTopOfStack =  202.0202; /* DR2. */
-                    pxTopOfStack -= 2;
-                    *(double *)pxTopOfStack =  101.0101; /* DR1. */
-                    pxTopOfStack -= 2;
-                    *(double *)pxTopOfStack = 9876.54321;/* DR0. */
-                }
-            #else /* ifdef USE_FULL_REGISTER_INITIALISATION */
-                {
-                    pxTopOfStack -= portDPFPU_DATA_REGISTER_WORDS;
-                    memset( pxTopOfStack, 0x00, portDPFPU_DATA_REGISTER_WORDS * sizeof( StackType_t ) );
-                }
-            #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */
-            pxTopOfStack--;
-            *pxTopOfStack = portINITIAL_DECNT; /* DECNT. */
-            pxTopOfStack--;
-            *pxTopOfStack = portINITIAL_DCMR;  /* DCMR. */
-            pxTopOfStack--;
-            *pxTopOfStack = portINITIAL_DPSW;  /* DPSW. */
+            pxTopOfStack -= 2;
+            *( double * ) pxTopOfStack = 1515.1515;  /* DR15. */
+            pxTopOfStack -= 2;
+            *( double * ) pxTopOfStack = 1414.1414;  /* DR14. */
+            pxTopOfStack -= 2;
+            *( double * ) pxTopOfStack = 1313.1313;  /* DR13. */
+            pxTopOfStack -= 2;
+            *( double * ) pxTopOfStack = 1212.1212;  /* DR12. */
+            pxTopOfStack -= 2;
+            *( double * ) pxTopOfStack = 1111.1111;  /* DR11. */
+            pxTopOfStack -= 2;
+            *( double * ) pxTopOfStack = 1010.1010;  /* DR10. */
+            pxTopOfStack -= 2;
+            *( double * ) pxTopOfStack = 909.0909;   /* DR9. */
+            pxTopOfStack -= 2;
+            *( double * ) pxTopOfStack = 808.0808;   /* DR8. */
+            pxTopOfStack -= 2;
+            *( double * ) pxTopOfStack = 707.0707;   /* DR7. */
+            pxTopOfStack -= 2;
+            *( double * ) pxTopOfStack = 606.0606;   /* DR6. */
+            pxTopOfStack -= 2;
+            *( double * ) pxTopOfStack = 505.0505;   /* DR5. */
+            pxTopOfStack -= 2;
+            *( double * ) pxTopOfStack = 404.0404;   /* DR4. */
+            pxTopOfStack -= 2;
+            *( double * ) pxTopOfStack = 303.0303;   /* DR3. */
+            pxTopOfStack -= 2;
+            *( double * ) pxTopOfStack = 202.0202;   /* DR2. */
+            pxTopOfStack -= 2;
+            *( double * ) pxTopOfStack = 101.0101;   /* DR1. */
+            pxTopOfStack -= 2;
+            *( double * ) pxTopOfStack = 9876.54321; /* DR0. */
         }
+        #else /* ifdef USE_FULL_REGISTER_INITIALISATION */
+        {
+            pxTopOfStack -= portDPFPU_DATA_REGISTER_WORDS;
+            memset( pxTopOfStack, 0x00, portDPFPU_DATA_REGISTER_WORDS * sizeof( StackType_t ) );
+        }
+        #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */
+        pxTopOfStack--;
+        *pxTopOfStack = portINITIAL_DECNT; /* DECNT. */
+        pxTopOfStack--;
+        *pxTopOfStack = portINITIAL_DCMR;  /* DCMR. */
+        pxTopOfStack--;
+        *pxTopOfStack = portINITIAL_DPSW;  /* DPSW. */
+    }
     #elif ( configUSE_TASK_DPFPU_SUPPORT == 0 )
-        {
-            /* Omit DPFPU support. */
-        }
+    {
+        /* Omit DPFPU support. */
+    }
     #else /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */
-        {
-            #error Invalid configUSE_TASK_DPFPU_SUPPORT setting - configUSE_TASK_DPFPU_SUPPORT must be set to 0, 1, 2, or left undefined.
-        }
+    {
+        #error Invalid configUSE_TASK_DPFPU_SUPPORT setting - configUSE_TASK_DPFPU_SUPPORT must be set to 0, 1, 2, or left undefined.
+    }
     #endif /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */
 
     return pxTopOfStack;
@@ -330,78 +330,74 @@ void vPortEndScheduler( void )
 #pragma inline_asm prvStartFirstTask
 static void prvStartFirstTask( void )
 {
-#ifndef __CDT_PARSER__
+    #ifndef __CDT_PARSER__
 
-    /* When starting the scheduler there is nothing that needs moving to the
-     * interrupt stack because the function is not called from an interrupt.
-     * Just ensure the current stack is the user stack. */
-    SETPSW U
+        /* When starting the scheduler there is nothing that needs moving to the
+         * interrupt stack because the function is not called from an interrupt.
+         * Just ensure the current stack is the user stack. */
+        SETPSW U
 
 
-    /* Obtain the location of the stack associated with which ever task
-     * pxCurrentTCB is currently pointing to. */
-    MOV.L # _pxCurrentTCB, R15
-    MOV.L [ R15 ], R15
-    MOV.L [ R15 ], R0
+        /* Obtain the location of the stack associated with which ever task
+         * pxCurrentTCB is currently pointing to. */
+        MOV.L # _pxCurrentTCB, R15
+            MOV.L[ R15 ], R15
+            MOV.L[ R15 ], R0
 
 
-    /* Restore the registers from the stack of the task pointed to by
-     * pxCurrentTCB. */
+        /* Restore the registers from the stack of the task pointed to by
+         * pxCurrentTCB. */
 
-    #if ( configUSE_TASK_DPFPU_SUPPORT == 1 )
+        #if ( configUSE_TASK_DPFPU_SUPPORT == 1 )
+
+            /* The restored ulPortTaskHasDPFPUContext is to be zero here.
+             * So, it is never necessary to restore the DPFPU context here. */
+            POP R15
+            MOV.L # _ulPortTaskHasDPFPUContext, R14
+            MOV.L R15, [ R14 ]
+        #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 )
+            /* Restore the DPFPU context. */
+            DPOPM.L DPSW - DECNT
+            DPOPM.D DR0 - DR15
+        #endif /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */
 
-        /* The restored ulPortTaskHasDPFPUContext is to be zero here.
-         * So, it is never necessary to restore the DPFPU context here. */
         POP R15
-        MOV.L # _ulPortTaskHasDPFPUContext, R14
-        MOV.L R15, [ R14 ]
 
-    #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 )
+        /* Accumulator low 32 bits. */
+        MVTACLO R15, A0
+        POP R15
 
-        /* Restore the DPFPU context. */
-        DPOPM.L DPSW-DECNT
-        DPOPM.D DR0-DR15
+        /* Accumulator high 32 bits. */
+        MVTACHI R15, A0
+        POP R15
 
-    #endif /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */
+        /* Accumulator guard. */
+        MVTACGU R15, A0
+        POP R15
 
-    POP R15
+        /* Accumulator low 32 bits. */
+        MVTACLO R15, A1
+        POP R15
 
-    /* Accumulator low 32 bits. */
-    MVTACLO R15, A0
-    POP R15
+        /* Accumulator high 32 bits. */
+        MVTACHI R15, A1
+        POP R15
 
-    /* Accumulator high 32 bits. */
-    MVTACHI R15, A0
-    POP R15
+        /* Accumulator guard. */
+        MVTACGU R15, A1
+        POP R15
 
-    /* Accumulator guard. */
-    MVTACGU R15, A0
-    POP R15
+        /* Floating point status word. */
+        MVTC R15, FPSW
 
-    /* Accumulator low 32 bits. */
-    MVTACLO R15, A1
-    POP R15
+        /* R1 to R15 - R0 is not included as it is the SP. */
+        POPM R1 - R15
 
-    /* Accumulator high 32 bits. */
-    MVTACHI R15, A1
-    POP R15
-
-    /* Accumulator guard. */
-    MVTACGU R15, A1
-    POP R15
-
-    /* Floating point status word. */
-    MVTC R15, FPSW
-
-    /* R1 to R15 - R0 is not included as it is the SP. */
-    POPM R1-R15
-
-    /* This pops the remaining registers. */
-    RTE
-    NOP
-    NOP
-
-#endif /* ifndef __CDT_PARSER__ */
+        /* This pops the remaining registers. */
+        RTE
+        NOP
+            NOP
+    #endif /* ifndef __CDT_PARSER__ */
 }
 /*-----------------------------------------------------------*/
 
@@ -414,163 +410,155 @@ void vSoftwareInterruptISR( void )
 #pragma inline_asm prvYieldHandler
 static void prvYieldHandler( void )
 {
-#ifndef __CDT_PARSER__
-
-    /* Re-enable interrupts. */
-    SETPSW I
+    #ifndef __CDT_PARSER__
+        /* Re-enable interrupts. */
+        SETPSW I
 
 
-    /* Move the data that was automatically pushed onto the interrupt stack when
-     * the interrupt occurred from the interrupt stack to the user stack.
-     *
-     * R15 is saved before it is clobbered. */
-    PUSH.L R15
-
-    /* Read the user stack pointer. */
-    MVFC USP, R15
-
-    /* Move the address down to the data being moved. */
-    SUB # 12, R15
-    MVTC R15, USP
-
-    /* Copy the data across, R15, then PC, then PSW. */
-    MOV.L [ R0 ], [ R15 ]
-    MOV.L 4[ R0 ], 4[ R15 ]
-    MOV.L 8[ R0 ], 8[ R15 ]
-
-    /* Move the interrupt stack pointer to its new correct position. */
-    ADD # 12, R0
-
-    /* All the rest of the registers are saved directly to the user stack. */
-    SETPSW U
-
-    /* Save the rest of the general registers (R15 has been saved already). */
-    PUSHM R1-R14
-
-    /* Save the FPSW and accumulators. */
-    MVFC FPSW, R15
-    PUSH.L R15
-    MVFACGU # 0, A1, R15
-    PUSH.L R15
-    MVFACHI # 0, A1, R15
-    PUSH.L R15
-    MVFACLO # 0, A1, R15 /* Low order word. */
-    PUSH.L R15
-    MVFACGU # 0, A0, R15
-    PUSH.L R15
-    MVFACHI # 0, A0, R15
-    PUSH.L R15
-    MVFACLO # 0, A0, R15 /* Low order word. */
-    PUSH.L R15
-
-    #if ( configUSE_TASK_DPFPU_SUPPORT == 1 )
-
-        /* Does the task have a DPFPU context that needs saving?  If
-         * ulPortTaskHasDPFPUContext is 0 then no. */
-        MOV.L # _ulPortTaskHasDPFPUContext, R15
-        MOV.L [ R15 ], R15
-        CMP # 0, R15
-
-        /* Save the DPFPU context, if any. */
-        BEQ.B ?+
-        DPUSHM.D DR0-DR15
-        DPUSHM.L DPSW-DECNT
-        ?:
-
-        /* Save ulPortTaskHasDPFPUContext itself. */
+        /* Move the data that was automatically pushed onto the interrupt stack when
+         * the interrupt occurred from the interrupt stack to the user stack.
+         *
+         * R15 is saved before it is clobbered. */
         PUSH.L R15
 
-    #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 )
+        /* Read the user stack pointer. */
+        MVFC USP, R15
 
-        /* Save the DPFPU context, always. */
-        DPUSHM.D DR0-DR15
-        DPUSHM.L DPSW-DECNT
+        /* Move the address down to the data being moved. */
+             SUB # 12, R15
+        MVTC R15, USP
 
-    #endif /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */
+        /* Copy the data across, R15, then PC, then PSW. */
+             MOV.L[ R0 ], [ R15 ]
+        MOV.L 4[ R0 ], 4[ R15 ]
+        MOV.L 8[ R0 ], 8[ R15 ]
+
+        /* Move the interrupt stack pointer to its new correct position. */
+        ADD # 12, R0
+
+        /* All the rest of the registers are saved directly to the user stack. */
+        SETPSW U
+
+        /* Save the rest of the general registers (R15 has been saved already). */
+        PUSHM R1 - R14
+
+        /* Save the FPSW and accumulators. */
+        MVFC FPSW, R15
+             PUSH.L R15
+             MVFACGU # 0, A1, R15
+             PUSH.L R15
+             MVFACHI # 0, A1, R15
+             PUSH.L R15
+             MVFACLO # 0, A1, R15 /* Low order word. */
+             PUSH.L R15
+             MVFACGU # 0, A0, R15
+             PUSH.L R15
+             MVFACHI # 0, A0, R15
+             PUSH.L R15
+             MVFACLO # 0, A0, R15 /* Low order word. */
+             PUSH.L R15
+
+        #if ( configUSE_TASK_DPFPU_SUPPORT == 1 )
+
+            /* Does the task have a DPFPU context that needs saving?  If
+             * ulPortTaskHasDPFPUContext is 0 then no. */
+            MOV.L # _ulPortTaskHasDPFPUContext, R15
+             MOV.L[ R15 ], R15
+             CMP # 0, R15
+
+            /* Save the DPFPU context, if any. */
+             BEQ.B ? +
+            DPUSHM.D DR0 - DR15
+             DPUSHM.L DPSW - DECNT
+            ? :
+
+            /* Save ulPortTaskHasDPFPUContext itself. */
+            PUSH.L R15
+        #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 )
+            /* Save the DPFPU context, always. */
+            DPUSHM.D DR0 - DR15
+             DPUSHM.L DPSW - DECNT
+        #endif /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */
 
 
-    /* Save the stack pointer to the TCB. */
-    MOV.L # _pxCurrentTCB, R15
-    MOV.L [ R15 ], R15
-    MOV.L R0, [ R15 ]
+        /* Save the stack pointer to the TCB. */
+        MOV.L # _pxCurrentTCB, R15
+             MOV.L[ R15 ], R15
+             MOV.L R0, [ R15 ]
 
 
-    /* Ensure the interrupt mask is set to the syscall priority while the kernel
-     * structures are being accessed. */
-    MVTIPL # configMAX_SYSCALL_INTERRUPT_PRIORITY
+        /* Ensure the interrupt mask is set to the syscall priority while the kernel
+         * structures are being accessed. */
+        MVTIPL # configMAX_SYSCALL_INTERRUPT_PRIORITY
 
-    /* Select the next task to run. */
-    BSR.A _vTaskSwitchContext
+        /* Select the next task to run. */
+        BSR.A _vTaskSwitchContext
 
-    /* Reset the interrupt mask as no more data structure access is required. */
-    MVTIPL # configKERNEL_INTERRUPT_PRIORITY
+        /* Reset the interrupt mask as no more data structure access is required. */
+        MVTIPL # configKERNEL_INTERRUPT_PRIORITY
 
 
-    /* Load the stack pointer of the task that is now selected as the Running
-     * state task from its TCB. */
-    MOV.L # _pxCurrentTCB, R15
-    MOV.L [ R15 ], R15
-    MOV.L [ R15 ], R0
+        /* Load the stack pointer of the task that is now selected as the Running
+         * state task from its TCB. */
+        MOV.L # _pxCurrentTCB, R15
+             MOV.L[ R15 ], R15
+             MOV.L[ R15 ], R0
 
 
-    /* Restore the context of the new task.  The PSW (Program Status Word) and
-     * PC will be popped by the RTE instruction. */
+        /* Restore the context of the new task.  The PSW (Program Status Word) and
+         * PC will be popped by the RTE instruction. */
 
-    #if ( configUSE_TASK_DPFPU_SUPPORT == 1 )
+        #if ( configUSE_TASK_DPFPU_SUPPORT == 1 )
+
+            /* Is there a DPFPU context to restore?  If the restored
+             * ulPortTaskHasDPFPUContext is zero then no. */
+            POP R15
+             MOV.L # _ulPortTaskHasDPFPUContext, R14
+             MOV.L R15, [ R14 ]
+            CMP # 0, R15
+
+            /* Restore the DPFPU context, if any. */
+             BEQ.B ? +
+            DPOPM.L DPSW - DECNT
+             DPOPM.D DR0 - DR15
+            ? :
+        #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 )
+            /* Restore the DPFPU context, always. */
+            DPOPM.L DPSW - DECNT
+             DPOPM.D DR0 - DR15
+        #endif /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */
 
-        /* Is there a DPFPU context to restore?  If the restored
-         * ulPortTaskHasDPFPUContext is zero then no. */
         POP R15
-        MOV.L # _ulPortTaskHasDPFPUContext, R14
-        MOV.L R15, [ R14 ]
-        CMP # 0, R15
 
-        /* Restore the DPFPU context, if any. */
-        BEQ.B ?+
-        DPOPM.L DPSW-DECNT
-        DPOPM.D DR0-DR15
-        ?:
+        /* Accumulator low 32 bits. */
+        MVTACLO R15, A0
+        POP R15
 
-    #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 )
+        /* Accumulator high 32 bits. */
+        MVTACHI R15, A0
+        POP R15
 
-        /* Restore the DPFPU context, always. */
-        DPOPM.L DPSW-DECNT
-        DPOPM.D DR0-DR15
+        /* Accumulator guard. */
+        MVTACGU R15, A0
+        POP R15
 
-    #endif /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */
+        /* Accumulator low 32 bits. */
+        MVTACLO R15, A1
+        POP R15
 
-    POP R15
+        /* Accumulator high 32 bits. */
+        MVTACHI R15, A1
+        POP R15
 
-    /* Accumulator low 32 bits. */
-    MVTACLO R15, A0
-    POP R15
-
-    /* Accumulator high 32 bits. */
-    MVTACHI R15, A0
-    POP R15
-
-    /* Accumulator guard. */
-    MVTACGU R15, A0
-    POP R15
-
-    /* Accumulator low 32 bits. */
-    MVTACLO R15, A1
-    POP R15
-
-    /* Accumulator high 32 bits. */
-    MVTACHI R15, A1
-    POP R15
-
-    /* Accumulator guard. */
-    MVTACGU R15, A1
-    POP R15
-    MVTC R15, FPSW
-    POPM R1-R15
-    RTE
-    NOP
-    NOP
-
-#endif /* ifndef __CDT_PARSER__ */
+        /* Accumulator guard. */
+        MVTACGU R15, A1
+        POP R15
+        MVTC R15, FPSW
+        POPM R1 - R15
+        RTE
+        NOP
+             NOP
+    #endif /* ifndef __CDT_PARSER__ */
 }
 /*-----------------------------------------------------------*/
 
diff --git a/portable/Renesas/RX700v3_DPFPU/portmacro.h b/portable/Renesas/RX700v3_DPFPU/portmacro.h
index fef13556e..050d82432 100644
--- a/portable/Renesas/RX700v3_DPFPU/portmacro.h
+++ b/portable/Renesas/RX700v3_DPFPU/portmacro.h
@@ -28,7 +28,7 @@
 
 
 #ifndef PORTMACRO_H
-    #define PORTMACRO_H
+#define PORTMACRO_H
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
@@ -37,7 +37,7 @@
 /* *INDENT-ON* */
 
 /* Hardware specifics. */
-    #include <machine.h>
+#include <machine.h>
 
 /*-----------------------------------------------------------
  * Port specific definitions.
@@ -51,9 +51,9 @@
 
 /* When the FIT configurator or the Smart Configurator is used, platform.h has to be
  * used. */
-    #ifndef configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H
-        #define configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H 0
-    #endif
+#ifndef configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H
+    #define configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H    0
+#endif
 
 /* If configUSE_TASK_DPFPU_SUPPORT is set to 1 (or undefined) then each task will
  * be created without a DPFPU context, and a task must call vTaskUsesDPFPU() before
@@ -61,72 +61,73 @@
  * tasks are created with a DPFPU context by default, and calling vTaskUsesDPFPU() has
  * no effect.  If configUSE_TASK_DPFPU_SUPPORT is set to 0 then tasks never take care
  * of any DPFPU context (even if DPFPU registers are used). */
-    #ifndef configUSE_TASK_DPFPU_SUPPORT
-        #define configUSE_TASK_DPFPU_SUPPORT 1
-    #endif
+#ifndef configUSE_TASK_DPFPU_SUPPORT
+    #define configUSE_TASK_DPFPU_SUPPORT    1
+#endif
 
 /*-----------------------------------------------------------*/
 
 /* Type definitions - these are a bit legacy and not really used now, other than
  * portSTACK_TYPE and portBASE_TYPE. */
-    #define portCHAR          char
-    #define portFLOAT         float
-    #define portDOUBLE        double
-    #define portLONG          long
-    #define portSHORT         short
-    #define portSTACK_TYPE    uint32_t
-    #define portBASE_TYPE     long
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-    typedef portSTACK_TYPE   StackType_t;
-    typedef long             BaseType_t;
-    typedef unsigned long    UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
-    #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-        typedef uint16_t     TickType_t;
-        #define portMAX_DELAY              ( TickType_t ) 0xffff
-    #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-        typedef uint32_t     TickType_t;
-        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
  * not need to be guarded with a critical section. */
-        #define portTICK_TYPE_IS_ATOMIC    1
-    #else
-        #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
-    #endif
+    #define portTICK_TYPE_IS_ATOMIC    1
+#else
+    #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+#endif
 
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-    #define portBYTE_ALIGNMENT    8     /* Could make four, according to manual. */
-    #define portSTACK_GROWTH      -1
-    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-    #define portNOP()    nop()
+#define portBYTE_ALIGNMENT    8         /* Could make four, according to manual. */
+#define portSTACK_GROWTH      -1
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()    nop()
 
 /* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;"
  * where portITU_SWINTR is the location of the software interrupt register
  * (0x000872E0).  Don't rely on the assembler to select a register, so instead
  * save and restore clobbered registers manually. */
-    #pragma inline_asm vPortYield
-    static void vPortYield( void )
-    {
+#pragma inline_asm vPortYield
+static void vPortYield( void )
+{
     #ifndef __CDT_PARSER__
+
         /* Save clobbered register - may not actually be necessary if inline asm
          * functions are considered to use the same rules as function calls by the
          * compiler. */
         PUSH.L R5
         /* Set ITU SWINTR. */
-        MOV.L # 000872E0H, R5
-        MOV.B # 1, [ R5 ]
+        MOV.L # 000 872E0H, R5
+            MOV.B # 1, [ R5 ]
         /* Read back to ensure the value is taken before proceeding. */
-        CMP [ R5 ].UB, R5
+        CMP[ R5 ].UB, R5
         /* Restore clobbered register to its previous value. */
         POP R5
-    #endif
-    }
+    #endif /* ifndef __CDT_PARSER__ */
+}
 
-    #define portYIELD()                                       vPortYield()
-    #define portYIELD_FROM_ISR( x )                           do { if( ( x ) != pdFALSE ) portYIELD(); } while( 0 )
+#define portYIELD()                                       vPortYield()
+#define portYIELD_FROM_ISR( x )                           do { if( ( x ) != pdFALSE ) portYIELD( ); } while( 0 )
 
 /* These macros should not be called directly, but through the
  * taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
@@ -137,32 +138,32 @@
  * functions are those that end in FromISR.  FreeRTOS maintains a separate
  * interrupt API to ensure API function and interrupt entry is as fast and as
  * simple as possible. */
-    #define portENABLE_INTERRUPTS()                           set_ipl( ( long ) 0 )
-    #ifdef configASSERT
-        #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    configASSERT( ( get_ipl() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
-        #define portDISABLE_INTERRUPTS()                      if( get_ipl() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
-    #else
-        #define portDISABLE_INTERRUPTS()                      set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
-    #endif
+#define portENABLE_INTERRUPTS()                           set_ipl( ( long ) 0 )
+#ifdef configASSERT
+    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    configASSERT( ( get_ipl() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+    #define portDISABLE_INTERRUPTS()                      if( get_ipl() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#else
+    #define portDISABLE_INTERRUPTS()                      set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#endif
 
 /* Critical nesting counts are stored in the TCB. */
-    #define portCRITICAL_NESTING_IN_TCB    ( 1 )
+#define portCRITICAL_NESTING_IN_TCB    ( 1 )
 
 /* The critical nesting functions defined within tasks.c. */
-    extern void vTaskEnterCritical( void );
-    extern void vTaskExitCritical( void );
-    #define portENTER_CRITICAL()    vTaskEnterCritical()
-    #define portEXIT_CRITICAL()     vTaskExitCritical()
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+#define portENTER_CRITICAL()                                           vTaskEnterCritical()
+#define portEXIT_CRITICAL()                                            vTaskExitCritical()
 
 /* As this port allows interrupt nesting... */
-    #define portSET_INTERRUPT_MASK_FROM_ISR()                              ( UBaseType_t ) get_ipl(); set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
-    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus )    set_ipl( ( long ) uxSavedInterruptStatus )
+#define portSET_INTERRUPT_MASK_FROM_ISR()                              ( UBaseType_t ) get_ipl(); set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus )    set_ipl( ( long ) uxSavedInterruptStatus )
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
-    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
 /*-----------------------------------------------------------*/
 
@@ -171,17 +172,18 @@
  * themselves a DPFPU context before using any DPFPU instructions.  If
  * configUSE_TASK_DPFPU_SUPPORT is set to 2 then all tasks will have a DPFPU context
  * by default. */
-    #if( configUSE_TASK_DPFPU_SUPPORT == 1 )
-        void vPortTaskUsesDPFPU( void );
-    #else
+#if ( configUSE_TASK_DPFPU_SUPPORT == 1 )
+    void vPortTaskUsesDPFPU( void );
+#else
+
 /* Each task has a DPFPU context already, so define this function away to
  * nothing to prevent it being called accidentally. */
-        #define vPortTaskUsesDPFPU()
-    #endif
-    #define portTASK_USES_DPFPU() vPortTaskUsesDPFPU()
+    #define vPortTaskUsesDPFPU()
+#endif
+#define portTASK_USES_DPFPU()             vPortTaskUsesDPFPU()
 
 /* Definition to allow compatibility with existing FreeRTOS Demo using flop.c. */
-    #define portTASK_USES_FLOATING_POINT() vPortTaskUsesDPFPU()
+#define portTASK_USES_FLOATING_POINT()    vPortTaskUsesDPFPU()
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/Renesas/SH2A_FPU/port.c b/portable/Renesas/SH2A_FPU/port.c
index 82c06fa5a..b5e97e9b1 100644
--- a/portable/Renesas/SH2A_FPU/port.c
+++ b/portable/Renesas/SH2A_FPU/port.c
@@ -27,8 +27,8 @@
  */
 
 /*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the SH2A port.
- *----------------------------------------------------------*/
+* Implementation of functions defined in portable.h for the SH2A port.
+*----------------------------------------------------------*/
 
 /* Scheduler includes. */
 #include "FreeRTOS.h"
@@ -40,17 +40,17 @@
 /*-----------------------------------------------------------*/
 
 /* The SR assigned to a newly created task.  The only important thing in this
-value is for all interrupts to be enabled. */
-#define portINITIAL_SR              ( 0UL )
+ * value is for all interrupts to be enabled. */
+#define portINITIAL_SR                 ( 0UL )
 
 /* Dimensions the array into which the floating point context is saved.
-Allocate enough space for FPR0 to FPR15, FPUL and FPSCR, each of which is 4
-bytes big.  If this number is changed then the 72 in portasm.src also needs
-changing. */
-#define portFLOP_REGISTERS_TO_STORE ( 18 )
-#define portFLOP_STORAGE_SIZE       ( portFLOP_REGISTERS_TO_STORE * 4 )
+ * Allocate enough space for FPR0 to FPR15, FPUL and FPSCR, each of which is 4
+ * bytes big.  If this number is changed then the 72 in portasm.src also needs
+ * changing. */
+#define portFLOP_REGISTERS_TO_STORE    ( 18 )
+#define portFLOP_STORAGE_SIZE          ( portFLOP_REGISTERS_TO_STORE * 4 )
 
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
+#if ( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
     #error configSUPPORT_DYNAMIC_ALLOCATION must be 1 to use this port.
 #endif
 
@@ -76,7 +76,9 @@ extern uint32_t ulPortGetGBR( void );
 /*
  * See header file for description.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
     /* Mark the end of the stack - used for debugging only and can be removed. */
     *pxTopOfStack = 0x11111111UL;
@@ -170,9 +172,9 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
     *pxTopOfStack = ulPortGetGBR();
 
     /* GBR = global base register.
-       VBR = vector base register.
-       TBR = jump table base register.
-       R15 is the stack pointer. */
+    * VBR = vector base register.
+    * TBR = jump table base register.
+    * R15 is the stack pointer. */
 
     return pxTopOfStack;
 }
@@ -180,18 +182,18 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
 
 BaseType_t xPortStartScheduler( void )
 {
-extern void vApplicationSetupTimerInterrupt( void );
+    extern void vApplicationSetupTimerInterrupt( void );
 
     /* Call an application function to set up the timer that will generate the
-    tick interrupt.  This way the application can decide which peripheral to
-    use.  A demo application is provided to show a suitable example. */
+     * tick interrupt.  This way the application can decide which peripheral to
+     * use.  A demo application is provided to show a suitable example. */
     vApplicationSetupTimerInterrupt();
 
     /* Start the first task.  This will only restore the standard registers and
-    not the flop registers.  This does not really matter though because the only
-    flop register that is initialised to a particular value is fpscr, and it is
-    only initialised to the current value, which will still be the current value
-    when the first task starts executing. */
+     * not the flop registers.  This does not really matter though because the only
+     * flop register that is initialised to a particular value is fpscr, and it is
+     * only initialised to the current value, which will still be the current value
+     * when the first task starts executing. */
     trapa( portSTART_SCHEDULER_TRAP_NO );
 
     /* Should not get here. */
@@ -207,37 +209,37 @@ void vPortEndScheduler( void )
 
 void vPortYield( void )
 {
-int32_t lInterruptMask;
+    int32_t lInterruptMask;
 
     /* Ensure the yield trap runs at the same priority as the other interrupts
-    that can cause a context switch. */
+     * that can cause a context switch. */
     lInterruptMask = get_imask();
 
     /* taskYIELD() can only be called from a task, not an interrupt, so the
-    current interrupt mask can only be 0 or portKERNEL_INTERRUPT_PRIORITY and
-    the mask can be set without risk of accidentally lowering the mask value. */
+     * current interrupt mask can only be 0 or portKERNEL_INTERRUPT_PRIORITY and
+     * the mask can be set without risk of accidentally lowering the mask value. */
     set_imask( portKERNEL_INTERRUPT_PRIORITY );
 
     trapa( portYIELD_TRAP_NO );
 
     /* Restore the interrupt mask to whatever it was previously (when the
-    function was entered). */
+     * function was entered). */
     set_imask( ( int ) lInterruptMask );
 }
 /*-----------------------------------------------------------*/
 
 BaseType_t xPortUsesFloatingPoint( TaskHandle_t xTask )
 {
-uint32_t *pulFlopBuffer;
-BaseType_t xReturn;
-extern void * volatile pxCurrentTCB;
+    uint32_t * pulFlopBuffer;
+    BaseType_t xReturn;
+    extern void * volatile pxCurrentTCB;
 
     /* This function tells the kernel that the task referenced by xTask is
-    going to use the floating point registers and therefore requires the
-    floating point registers saved as part of its context. */
+     * going to use the floating point registers and therefore requires the
+     * floating point registers saved as part of its context. */
 
     /* Passing NULL as xTask is used to indicate that the calling task is the
-    subject task - so pxCurrentTCB is the task handle. */
+     * subject task - so pxCurrentTCB is the task handle. */
     if( xTask == NULL )
     {
         xTask = ( TaskHandle_t ) pxCurrentTCB;
@@ -252,11 +254,11 @@ extern void * volatile pxCurrentTCB;
         memset( ( void * ) pulFlopBuffer, 0x00, portFLOP_STORAGE_SIZE );
 
         /* The first thing to get saved in the buffer is the FPSCR value -
-        initialise this to the current FPSCR value. */
+         * initialise this to the current FPSCR value. */
         *pulFlopBuffer = get_fpscr();
 
         /* Use the task tag to point to the flop buffer.  Pass pointer to just
-        above the buffer because the flop save routine uses a pre-decrement. */
+         * above the buffer because the flop save routine uses a pre-decrement. */
         vTaskSetApplicationTaskTag( xTask, ( void * ) ( pulFlopBuffer + portFLOP_REGISTERS_TO_STORE ) );
         xReturn = pdPASS;
     }
diff --git a/portable/Renesas/SH2A_FPU/portmacro.h b/portable/Renesas/SH2A_FPU/portmacro.h
index 0ff2e323a..e4143e608 100644
--- a/portable/Renesas/SH2A_FPU/portmacro.h
+++ b/portable/Renesas/SH2A_FPU/portmacro.h
@@ -49,68 +49,68 @@
  */
 
 /* Type definitions - these are a bit legacy and not really used now, other than
-portSTACK_TYPE and portBASE_TYPE. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint32_t
-#define portBASE_TYPE   long
+ * portSTACK_TYPE and portBASE_TYPE. */
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-    not need to be guarded with a critical section. */
-    #define portTICK_TYPE_IS_ATOMIC 1
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+    #define portTICK_TYPE_IS_ATOMIC    1
 #endif
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portBYTE_ALIGNMENT              8
-#define portSTACK_GROWTH                -1
-#define portTICK_PERIOD_MS              ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portNOP()                       nop()
-#define portSTART_SCHEDULER_TRAP_NO     ( 32 )
-#define portYIELD_TRAP_NO               ( 33 )
-#define portKERNEL_INTERRUPT_PRIORITY   ( 1 )
+#define portBYTE_ALIGNMENT               8
+#define portSTACK_GROWTH                 -1
+#define portTICK_PERIOD_MS               ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()    nop()
+#define portSTART_SCHEDULER_TRAP_NO      ( 32 )
+#define portYIELD_TRAP_NO                ( 33 )
+#define portKERNEL_INTERRUPT_PRIORITY    ( 1 )
 
 void vPortYield( void );
-#define portYIELD()                     vPortYield()
+#define portYIELD()                vPortYield()
 
 extern void vTaskSwitchContext( void );
-#define portYIELD_FROM_ISR( x )         do { if( x != pdFALSE ) vTaskSwitchContext(); } while( 0 )
+#define portYIELD_FROM_ISR( x )    do { if( x != pdFALSE ) vTaskSwitchContext( ); } while( 0 )
 
 /*
  * This function tells the kernel that the task referenced by xTask is going to
  * use the floating point registers and therefore requires the floating point
  * registers saved as part of its context.
  */
-BaseType_t xPortUsesFloatingPoint( void* xTask );
+BaseType_t xPortUsesFloatingPoint( void * xTask );
 
 /*
  * The flop save and restore functions are defined in portasm.src and called by
  * the trace "task switched in" and "trace task switched out" macros.
  */
-void vPortSaveFlopRegisters( void *pulBuffer );
-void vPortRestoreFlopRegisters( void *pulBuffer );
+void vPortSaveFlopRegisters( void * pulBuffer );
+void vPortRestoreFlopRegisters( void * pulBuffer );
 
 /*
  * pxTaskTag is used to point to the buffer into which the floating point
  * context should be saved.  If pxTaskTag is NULL then the task does not use
  * a floating point context.
  */
-#define traceTASK_SWITCHED_OUT() do { if( pxCurrentTCB->pxTaskTag != NULL ) vPortSaveFlopRegisters( pxCurrentTCB->pxTaskTag ); } while( 0 )
-#define traceTASK_SWITCHED_IN() do { if( pxCurrentTCB->pxTaskTag != NULL ) vPortRestoreFlopRegisters( pxCurrentTCB->pxTaskTag ); } while( 0 )
+#define traceTASK_SWITCHED_OUT()    do { if( pxCurrentTCB->pxTaskTag != NULL ) vPortSaveFlopRegisters( pxCurrentTCB->pxTaskTag ); } while( 0 )
+#define traceTASK_SWITCHED_IN()     do { if( pxCurrentTCB->pxTaskTag != NULL ) vPortRestoreFlopRegisters( pxCurrentTCB->pxTaskTag ); } while( 0 )
 
 /*
  * These macros should be called directly, but through the taskENTER_CRITICAL()
@@ -120,7 +120,7 @@ void vPortRestoreFlopRegisters( void *pulBuffer );
 #define portDISABLE_INTERRUPTS()    set_imask( portKERNEL_INTERRUPT_PRIORITY )
 
 /* Critical nesting counts are stored in the TCB. */
-#define portCRITICAL_NESTING_IN_TCB ( 1 )
+#define portCRITICAL_NESTING_IN_TCB    ( 1 )
 
 /* The critical nesting functions defined within tasks.c. */
 extern void vTaskEnterCritical( void );
@@ -131,8 +131,8 @@ extern void vTaskExitCritical( void );
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/Rowley/MSP430F449/port.c b/portable/Rowley/MSP430F449/port.c
index 992e3e763..b2628aaf7 100644
--- a/portable/Rowley/MSP430F449/port.c
+++ b/portable/Rowley/MSP430F449/port.c
@@ -31,28 +31,28 @@
 #include "task.h"
 
 /*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the MSP430 port.
- *----------------------------------------------------------*/
+* Implementation of functions defined in portable.h for the MSP430 port.
+*----------------------------------------------------------*/
 
 /* Constants required for hardware setup.  The tick ISR runs off the ACLK,
-not the MCLK. */
+ * not the MCLK. */
 #define portACLK_FREQUENCY_HZ           ( ( TickType_t ) 32768 )
 #define portINITIAL_CRITICAL_NESTING    ( ( uint16_t ) 10 )
 #define portFLAGS_INT_ENABLED           ( ( StackType_t ) 0x08 )
 
 /* We require the address of the pxCurrentTCB variable, but don't want to know
-any details of its type. */
+ * any details of its type. */
 typedef void TCB_t;
 extern volatile TCB_t * volatile pxCurrentTCB;
 
 /* Each task maintains a count of the critical section nesting depth.  Each
-time a critical section is entered the count is incremented.  Each time a
-critical section is exited the count is decremented - with interrupts only
-being re-enabled if the count is zero.
-
-usCriticalNesting will get set to zero when the scheduler starts, but must
-not be initialised to zero as this will cause problems during the startup
-sequence. */
+ * time a critical section is entered the count is incremented.  Each time a
+ * critical section is exited the count is decremented - with interrupts only
+ * being re-enabled if the count is zero.
+ *
+ * usCriticalNesting will get set to zero when the scheduler starts, but must
+ * not be initialised to zero as this will cause problems during the startup
+ * sequence. */
 volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;
 /*-----------------------------------------------------------*/
 
@@ -70,24 +70,26 @@ void prvSetupTimerInterrupt( void );
  *
  * See the header file portable.h.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
     /*
-        Place a few bytes of known values on the bottom of the stack.
-        This is just useful for debugging and can be included if required.
-
-        *pxTopOfStack = ( StackType_t ) 0x1111;
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x2222;
-        pxTopOfStack--;
-        *pxTopOfStack = ( StackType_t ) 0x3333;
-        pxTopOfStack--;
-    */
+     *  Place a few bytes of known values on the bottom of the stack.
+     *  This is just useful for debugging and can be included if required.
+     *
+     * pxTopOfStack = ( StackType_t ) 0x1111;
+     *  pxTopOfStack--;
+     * pxTopOfStack = ( StackType_t ) 0x2222;
+     *  pxTopOfStack--;
+     * pxTopOfStack = ( StackType_t ) 0x3333;
+     *  pxTopOfStack--;
+     */
 
     /* The msp430 automatically pushes the PC then SR onto the stack before
-    executing an ISR.  We want the stack to look just as if this has happened
-    so place a pointer to the start of the task on the stack first - followed
-    by the flags we want the task to use when it starts up. */
+     * executing an ISR.  We want the stack to look just as if this has happened
+     * so place a pointer to the start of the task on the stack first - followed
+     * by the flags we want the task to use when it starts up. */
     *pxTopOfStack = ( StackType_t ) pxCode;
     pxTopOfStack--;
     *pxTopOfStack = portFLAGS_INT_ENABLED;
@@ -118,17 +120,17 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
     pxTopOfStack--;
 
     /* When the task starts is will expect to find the function parameter in
-    R15. */
+     * R15. */
     *pxTopOfStack = ( StackType_t ) pvParameters;
     pxTopOfStack--;
 
     /* A variable is used to keep track of the critical section nesting.
-    This variable has to be stored as part of the task context and is
-    initially set to zero. */
+     * This variable has to be stored as part of the task context and is
+     * initially set to zero. */
     *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;
 
     /* Return a pointer to the top of the stack we have generated so this can
-    be stored in the task control block for the task. */
+     * be stored in the task control block for the task. */
     return pxTopOfStack;
 }
 /*-----------------------------------------------------------*/
@@ -136,7 +138,7 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
 void vPortEndScheduler( void )
 {
     /* It is unlikely that the MSP430 port will get stopped.  If required simply
-    disable the tick interrupt here. */
+     * disable the tick interrupt here. */
 }
 /*-----------------------------------------------------------*/
 
@@ -168,6 +170,3 @@ void prvSetupTimerInterrupt( void )
     TACTL |= MC_1;
 }
 /*-----------------------------------------------------------*/
-
-
-
diff --git a/portable/Rowley/MSP430F449/portasm.h b/portable/Rowley/MSP430F449/portasm.h
index 96c27cdac..45ffd0e08 100644
--- a/portable/Rowley/MSP430F449/portasm.h
+++ b/portable/Rowley/MSP430F449/portasm.h
@@ -30,51 +30,51 @@
 #define PORT_ASM_H
 
 portSAVE_CONTEXT macro
-                /* Save the remaining registers. */
-        push    r4
-        push    r5
-        push    r6
-        push    r7
-        push    r8
-        push    r9
-        push    r10
-        push    r11
-        push    r12
-        push    r13
-        push    r14
-        push    r15
-        mov.w   &_usCriticalNesting, r14
-        push    r14
-        mov.w   &_pxCurrentTCB, r12
-        mov.w   r1, @r12
-        endm
+/* Save the remaining registers. */
+push r4
+push r5
+push r6
+push r7
+push r8
+push r9
+push r10
+push r11
+push r12
+push r13
+push r14
+push r15
+mov.w &_usCriticalNesting, r14
+push r14
+       mov.w &_pxCurrentTCB, r12
+       mov.w r1, @r12
+endm
 /*-----------------------------------------------------------*/
 
 portRESTORE_CONTEXT macro
-        mov.w   &_pxCurrentTCB, r12
-        mov.w   @r12, r1
-        pop     r15
-        mov.w   r15, &_usCriticalNesting
-        pop     r15
-        pop     r14
-        pop     r13
-        pop     r12
-        pop     r11
-        pop     r10
-        pop     r9
-        pop     r8
-        pop     r7
-        pop     r6
-        pop     r5
-        pop     r4
+       mov.w &_pxCurrentTCB, r12
+       mov.w @r12, r1
+pop r15
+       mov.w r15, &_usCriticalNesting
+pop r15
+pop r14
+pop r13
+pop r12
+pop r11
+pop r10
+pop r9
+pop r8
+pop r7
+pop r6
+pop r5
+pop r4
 
-        /* The last thing on the stack will be the status register.
-                Ensure the power down bits are clear ready for the next
-                time this power down register is popped from the stack. */
-        bic.w   #0xf0,0(SP)
+/* The last thing on the stack will be the status register.
+ *      Ensure the power down bits are clear ready for the next
+ *      time this power down register is popped from the stack. */
+       bic.w   # 0xf0, 0 ( SP )
 
-        reti
-        endm
+reti
+endm
 /*-----------------------------------------------------------*/
 
-#endif
+#endif /* ifndef PORT_ASM_H */
diff --git a/portable/Rowley/MSP430F449/portmacro.h b/portable/Rowley/MSP430F449/portmacro.h
index 7137a6e09..80da469c8 100644
--- a/portable/Rowley/MSP430F449/portmacro.h
+++ b/portable/Rowley/MSP430F449/portmacro.h
@@ -40,24 +40,24 @@
  */
 
 /* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       int
-#define portSTACK_TYPE  uint16_t
-#define portBASE_TYPE   short
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         int
+#define portSTACK_TYPE    uint16_t
+#define portBASE_TYPE     short
 
-typedef portSTACK_TYPE StackType_t;
-typedef short BaseType_t;
-typedef unsigned short UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef short            BaseType_t;
+typedef unsigned short   UBaseType_t;
 
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
-#elif ( configTICK_TYPE_WIDTH_IN_BITS  == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t             TickType_t;
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+    typedef uint32_t     TickType_t;
     #define portMAX_DELAY    ( TickType_t ) 0xffffffffUL
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -71,37 +71,37 @@ typedef unsigned short UBaseType_t;
 /*-----------------------------------------------------------*/
 
 /* Critical section control macros. */
-#define portNO_CRITICAL_SECTION_NESTING     ( ( uint16_t ) 0 )
+#define portNO_CRITICAL_SECTION_NESTING    ( ( uint16_t ) 0 )
 
-#define portENTER_CRITICAL()                                                    \
-{                                                                               \
-extern volatile uint16_t usCriticalNesting;                         \
-                                                                                \
-    portDISABLE_INTERRUPTS();                                                   \
-                                                                                \
-    /* Now interrupts are disabled usCriticalNesting can be accessed */         \
-    /* directly.  Increment ulCriticalNesting to keep a count of how many */    \
-    /* times portENTER_CRITICAL() has been called. */                           \
-    usCriticalNesting++;                                                        \
-}
+#define portENTER_CRITICAL()                                                     \
+    {                                                                            \
+        extern volatile uint16_t usCriticalNesting;                              \
+                                                                                 \
+        portDISABLE_INTERRUPTS();                                                \
+                                                                                 \
+        /* Now interrupts are disabled usCriticalNesting can be accessed */      \
+        /* directly.  Increment ulCriticalNesting to keep a count of how many */ \
+        /* times portENTER_CRITICAL() has been called. */                        \
+        usCriticalNesting++;                                                     \
+    }
 
-#define portEXIT_CRITICAL()                                                     \
-{                                                                               \
-extern volatile uint16_t usCriticalNesting;                         \
-                                                                                \
-    if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING )                   \
-    {                                                                           \
-        /* Decrement the nesting count as we are leaving a critical section. */ \
-        usCriticalNesting--;                                                    \
-                                                                                \
-        /* If the nesting level has reached zero then interrupts should be */   \
-        /* re-enabled. */                                                       \
-        if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING )              \
-        {                                                                       \
-            portENABLE_INTERRUPTS();                                            \
-        }                                                                       \
-    }                                                                           \
-}
+#define portEXIT_CRITICAL()                                                         \
+    {                                                                               \
+        extern volatile uint16_t usCriticalNesting;                                 \
+                                                                                    \
+        if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING )                   \
+        {                                                                           \
+            /* Decrement the nesting count as we are leaving a critical section. */ \
+            usCriticalNesting--;                                                    \
+                                                                                    \
+            /* If the nesting level has reached zero then interrupts should be */   \
+            /* re-enabled. */                                                       \
+            if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING )              \
+            {                                                                       \
+                portENABLE_INTERRUPTS();                                            \
+            }                                                                       \
+        }                                                                           \
+    }
 /*-----------------------------------------------------------*/
 
 /* Task utilities. */
@@ -110,24 +110,24 @@ extern volatile uint16_t usCriticalNesting;                         \
  * Manual context switch called by portYIELD or taskYIELD.
  */
 extern void vPortYield( void );
-#define portYIELD() vPortYield()
+#define portYIELD()    vPortYield()
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portBYTE_ALIGNMENT          2
-#define portSTACK_GROWTH            ( -1 )
-#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT    2
+#define portSTACK_GROWTH      ( -1 )
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
 #define portNOP()
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) __toplevel
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters ) __toplevel
 
 #if configINTERRUPT_EXAMPLE_METHOD == 2
 
-extern void vTaskSwitchContext( void );
-#define portYIELD_FROM_ISR( x ) do { if( x ) vTaskSwitchContext(); } while( 0 )
+    extern void vTaskSwitchContext( void );
+    #define portYIELD_FROM_ISR( x )    do { if( x ) vTaskSwitchContext( ); } while( 0 )
 
 #endif
 
diff --git a/portable/SDCC/Cygnal/port.c b/portable/SDCC/Cygnal/port.c
index 8bf739eb7..61a7f8f24 100644
--- a/portable/SDCC/Cygnal/port.c
+++ b/portable/SDCC/Cygnal/port.c
@@ -27,8 +27,8 @@
  */
 
 /*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the Cygnal port.
- *----------------------------------------------------------*/
+* Implementation of functions defined in portable.h for the Cygnal port.
+*----------------------------------------------------------*/
 
 /* Standard includes. */
 #include <string.h>
@@ -38,34 +38,34 @@
 #include "task.h"
 
 /* Constants required to setup timer 2 to produce the RTOS tick. */
-#define portCLOCK_DIVISOR                               ( ( uint32_t ) 12 )
-#define portMAX_TIMER_VALUE                             ( ( uint32_t ) 0xffff )
-#define portENABLE_TIMER                                ( ( uint8_t ) 0x04 )
-#define portTIMER_2_INTERRUPT_ENABLE                    ( ( uint8_t ) 0x20 )
+#define portCLOCK_DIVISOR               ( ( uint32_t ) 12 )
+#define portMAX_TIMER_VALUE             ( ( uint32_t ) 0xffff )
+#define portENABLE_TIMER                ( ( uint8_t ) 0x04 )
+#define portTIMER_2_INTERRUPT_ENABLE    ( ( uint8_t ) 0x20 )
 
 /* The value used in the IE register when a task first starts. */
-#define portGLOBAL_INTERRUPT_BIT                        ( ( StackType_t ) 0x80 )
+#define portGLOBAL_INTERRUPT_BIT        ( ( StackType_t ) 0x80 )
 
 /* The value used in the PSW register when a task first starts. */
-#define portINITIAL_PSW                                 ( ( StackType_t ) 0x00 )
+#define portINITIAL_PSW                 ( ( StackType_t ) 0x00 )
 
 /* Macro to clear the timer 2 interrupt flag. */
-#define portCLEAR_INTERRUPT_FLAG()                      TMR2CN &= ~0x80;
+#define portCLEAR_INTERRUPT_FLAG()    TMR2CN &= ~0x80;
 
 /* Used during a context switch to store the size of the stack being copied
-to or from XRAM. */
+ * to or from XRAM. */
 data static uint8_t ucStackBytes;
 
 /* Used during a context switch to point to the next byte in XRAM from/to which
-a RAM byte is to be copied. */
+ * a RAM byte is to be copied. */
 xdata static StackType_t * data pxXRAMStack;
 
 /* Used during a context switch to point to the next byte in RAM from/to which
-an XRAM byte is to be copied. */
+ * an XRAM byte is to be copied. */
 data static StackType_t * data pxRAMStack;
 
 /* We require the address of the pxCurrentTCB variable, but don't want to know
-any details of its type. */
+ * any details of its type. */
 typedef void TCB_t;
 extern volatile TCB_t * volatile pxCurrentTCB;
 
@@ -76,223 +76,226 @@ extern volatile TCB_t * volatile pxCurrentTCB;
 static void prvSetupTimerInterrupt( void );
 
 /*-----------------------------------------------------------*/
+
 /*
  * Macro that copies the current stack from internal RAM to XRAM.  This is
  * required as the 8051 only contains enough internal RAM for a single stack,
  * but we have a stack for every task.
  */
-#define portCOPY_STACK_TO_XRAM()                                                            \
-{                                                                                           \
-        /* pxCurrentTCB points to a TCB which itself points to the location into            \
-        which the first stack byte should be copied. Set pxXRAMStack to point               \
-        to the location into which the first stack byte is to be copied. */                 \
-        pxXRAMStack = ( xdata StackType_t * ) *( ( xdata StackType_t ** ) pxCurrentTCB );   \
-                                                                                            \
-        /* Set pxRAMStack to point to the first byte to be coped from the stack. */         \
-        pxRAMStack = ( data StackType_t * data ) configSTACK_START;                         \
-                                                                                            \
-        /* Calculate the size of the stack we are about to copy from the current            \
-        stack pointer value. */                                                             \
-        ucStackBytes = SP - ( configSTACK_START - 1 );                                      \
-                                                                                            \
-        /* Before starting to copy the stack, store the calculated stack size so            \
-        the stack can be restored when the task is resumed. */                              \
-        *pxXRAMStack = ucStackBytes;                                                        \
-                                                                                            \
-        /* Copy each stack byte in turn.  pxXRAMStack is incremented first as we            \
-        have already stored the stack size into XRAM. */                                    \
-        while( ucStackBytes )                                                               \
-        {                                                                                   \
-                pxXRAMStack++;                                                              \
-                *pxXRAMStack = *pxRAMStack;                                                 \
-                pxRAMStack++;                                                               \
-                ucStackBytes--;                                                             \
-        }                                                                                   \
-}
+#define portCOPY_STACK_TO_XRAM() \
+    {                            \
+        /* pxCurrentTCB points to a TCB which itself points to the location into \
+         * which the first stack byte should be copied. Set pxXRAMStack to point \
+         * to the location into which the first stack byte is to be copied. */            \
+        pxXRAMStack = ( xdata StackType_t * ) *( ( xdata StackType_t ** ) pxCurrentTCB ); \
+                                                                                          \
+        /* Set pxRAMStack to point to the first byte to be coped from the stack. */       \
+        pxRAMStack = ( data StackType_t * data ) configSTACK_START;                       \
+                                                                                          \
+        /* Calculate the size of the stack we are about to copy from the current \
+         * stack pointer value. */                     \
+        ucStackBytes = SP - ( configSTACK_START - 1 ); \
+                                                       \
+        /* Before starting to copy the stack, store the calculated stack size so \
+         * the stack can be restored when the task is resumed. */ \
+        * pxXRAMStack = ucStackBytes;                             \
+                                                                  \
+        /* Copy each stack byte in turn.  pxXRAMStack is incremented first as we \
+         * have already stored the stack size into XRAM. */ \
+        while( ucStackBytes )                               \
+        {                                                   \
+            pxXRAMStack ++;                                 \
+            * pxXRAMStack = * pxRAMStack;                   \
+            pxRAMStack ++;                                  \
+            ucStackBytes --;                                \
+        }                                                   \
+    }
 /*-----------------------------------------------------------*/
 
 /*
  * Macro that copies the stack of the task being resumed from XRAM into
  * internal RAM.
  */
-#define portCOPY_XRAM_TO_STACK()                                                            \
-{                                                                                           \
-        /* Setup the pointers as per portCOPY_STACK_TO_XRAM(), but this time to             \
-        copy the data back out of XRAM and into the stack. */                               \
-        pxXRAMStack = ( xdata StackType_t * ) *( ( xdata StackType_t ** ) pxCurrentTCB );   \
-        pxRAMStack = ( data StackType_t * data ) ( configSTACK_START - 1 );                 \
-                                                                                            \
-        /* The first value stored in XRAM was the size of the stack - i.e. the              \
-        number of bytes we need to copy back. */                                            \
-        ucStackBytes = pxXRAMStack[ 0 ];                                                    \
-                                                                                            \
-        /* Copy the required number of bytes back into the stack. */                        \
-        do                                                                                  \
-        {                                                                                   \
-                pxXRAMStack++;                                                              \
-                pxRAMStack++;                                                               \
-                *pxRAMStack = *pxXRAMStack;                                                 \
-                ucStackBytes--;                                                             \
-        } while( ucStackBytes );                                                            \
-                                                                                            \
-        /* Restore the stack pointer ready to use the restored stack. */                    \
-        SP = ( uint8_t ) pxRAMStack;                                                        \
-}
+#define portCOPY_XRAM_TO_STACK() \
+    {                            \
+        /* Setup the pointers as per portCOPY_STACK_TO_XRAM(), but this time to \
+         * copy the data back out of XRAM and into the stack. */                          \
+        pxXRAMStack = ( xdata StackType_t * ) *( ( xdata StackType_t ** ) pxCurrentTCB ); \
+        pxRAMStack = ( data StackType_t * data )( configSTACK_START - 1 );                \
+                                                                                          \
+        /* The first value stored in XRAM was the size of the stack - i.e. the \
+         * number of bytes we need to copy back. */                      \
+        ucStackBytes = pxXRAMStack[ 0 ];                                 \
+                                                                         \
+        /* Copy the required number of bytes back into the stack. */     \
+        do                                                               \
+        {                                                                \
+            pxXRAMStack ++;                                              \
+            pxRAMStack ++;                                               \
+            * pxRAMStack = * pxXRAMStack;                                \
+            ucStackBytes --;                                             \
+        } while( ucStackBytes );                                         \
+                                                                         \
+        /* Restore the stack pointer ready to use the restored stack. */ \
+        SP = ( uint8_t ) pxRAMStack;                                     \
+    }
 /*-----------------------------------------------------------*/
 
 /*
  * Macro to push the current execution context onto the stack, before the stack
  * is moved to XRAM.
  */
-#define portSAVE_CONTEXT()                                                                  \
-{                                                                                           \
-        _asm                                                                                \
-                /* Push ACC first, as when restoring the context it must be restored        \
-                last (it is used to set the IE register). */                                \
-                push        ACC                                                             \
-                /* Store the IE register then disable interrupts. */                        \
-                push        IE                                                              \
-                clr                _EA                                                      \
-                push        DPL                                                             \
-                push        DPH                                                             \
-                push        b                                                               \
-                push        ar2                                                             \
-                push        ar3                                                             \
-                push        ar4                                                             \
-                push        ar5                                                             \
-                push        ar6                                                             \
-                push        ar7                                                             \
-                push        ar0                                                             \
-                push        ar1                                                             \
-                push        PSW                                                             \
-        _endasm;                                                                            \
-                PSW = 0;                                                                    \
-        _asm                                                                                \
-                push        _bp                                                             \
-        _endasm;                                                                            \
-}
+#define portSAVE_CONTEXT() \
+    {                      \
+        _asm               \
+        /* Push ACC first, as when restoring the context it must be restored \
+         * last (it is used to set the IE register). */      \
+        push ACC                                             \
+        /* Store the IE register then disable interrupts. */ \
+        push IE                                              \
+        clr _EA                                              \
+        push DPL                                             \
+        push DPH                                             \
+        push b                                               \
+        push ar2                                             \
+        push ar3                                             \
+        push ar4                                             \
+        push ar5                                             \
+        push ar6                                             \
+        push ar7                                             \
+        push ar0                                             \
+        push ar1                                             \
+        push PSW                                             \
+        _endasm;                                             \
+        PSW = 0;                                             \
+        _asm                                                 \
+        push _bp                                             \
+        _endasm;                                             \
+    }
 /*-----------------------------------------------------------*/
 
 /*
  * Macro that restores the execution context from the stack.  The execution
  * context was saved into the stack before the stack was copied into XRAM.
  */
-#define portRESTORE_CONTEXT()                                                               \
-{                                                                                           \
-        _asm                                                                                \
-                pop                _bp                                                      \
-                pop                PSW                                                      \
-                pop                ar1                                                      \
-                pop                ar0                                                      \
-                pop                ar7                                                      \
-                pop                ar6                                                      \
-                pop                ar5                                                      \
-                pop                ar4                                                      \
-                pop                ar3                                                      \
-                pop                ar2                                                      \
-                pop                b                                                        \
-                pop                DPH                                                      \
-                pop                DPL                                                      \
-                /* The next byte of the stack is the IE register.  Only the global          \
-                enable bit forms part of the task context.  Pop off the IE then set         \
-                the global enable bit to match that of the stored IE register. */           \
-                pop                ACC                                                      \
-                JB                ACC.7,0098$                                               \
-                CLR                IE.7                                                     \
-                LJMP        0099$                                                           \
-        0098$:                                                                              \
-                SETB        IE.7                                                            \
-        0099$:                                                                              \
-                /* Finally pop off the ACC, which was the first register saved. */          \
-                pop                ACC                                                      \
-                reti                                                                        \
-        _endasm;                                                                            \
-}
+#define portRESTORE_CONTEXT() \
+    {                         \
+        _asm                  \
+        pop _bp               \
+        pop PSW               \
+        pop ar1               \
+        pop ar0               \
+        pop ar7               \
+        pop ar6               \
+        pop ar5               \
+        pop ar4               \
+        pop ar3               \
+        pop ar2               \
+        pop b                 \
+        pop DPH               \
+        pop DPL               \
+        /* The next byte of the stack is the IE register.  Only the global \
+         * enable bit forms part of the task context.  Pop off the IE then set \
+         * the global enable bit to match that of the stored IE register. */ \
+        pop ACC                                                              \
+        JB ACC .7, 00 98$                                                    \
+        CLR IE .7                                                            \
+        LJMP 00 99$                                                          \
+        00 98$ :                                                             \
+        SETB IE .7                                                           \
+        00 99$ :                                                             \
+        /* Finally pop off the ACC, which was the first register saved. */   \
+        pop ACC                                                              \
+        reti                                                                 \
+        _endasm;                                                             \
+    }
 /*-----------------------------------------------------------*/
 
 /*
  * See header file for description.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
-uint32_t ulAddress;
-StackType_t *pxStartOfStack;
+    uint32_t ulAddress;
+    StackType_t * pxStartOfStack;
 
-        /* Leave space to write the size of the stack as the first byte. */
-        pxStartOfStack = pxTopOfStack;
-        pxTopOfStack++;
+    /* Leave space to write the size of the stack as the first byte. */
+    pxStartOfStack = pxTopOfStack;
+    pxTopOfStack++;
 
-        /* Place a few bytes of known values on the bottom of the stack.
-        This is just useful for debugging and can be uncommented if required.
-        *pxTopOfStack = 0x11;
-        pxTopOfStack++;
-        *pxTopOfStack = 0x22;
-        pxTopOfStack++;
-        *pxTopOfStack = 0x33;
-        pxTopOfStack++;
-        */
+    /* Place a few bytes of known values on the bottom of the stack.
+     * This is just useful for debugging and can be uncommented if required.
+     * pxTopOfStack = 0x11;
+     * pxTopOfStack++;
+     * pxTopOfStack = 0x22;
+     * pxTopOfStack++;
+     * pxTopOfStack = 0x33;
+     * pxTopOfStack++;
+     */
 
-        /* Simulate how the stack would look after a call to the scheduler tick
-        ISR.
+    /* Simulate how the stack would look after a call to the scheduler tick
+     * ISR.
+     *
+     * The return address that would have been pushed by the MCU. */
+    ulAddress = ( uint32_t ) pxCode;
+    *pxTopOfStack = ( StackType_t ) ulAddress;
+    ulAddress >>= 8;
+    pxTopOfStack++;
+    *pxTopOfStack = ( StackType_t ) ( ulAddress );
+    pxTopOfStack++;
 
-        The return address that would have been pushed by the MCU. */
-        ulAddress = ( uint32_t ) pxCode;
-        *pxTopOfStack = ( StackType_t ) ulAddress;
-        ulAddress >>= 8;
-        pxTopOfStack++;
-        *pxTopOfStack = ( StackType_t ) ( ulAddress );
-        pxTopOfStack++;
+    /* Next all the registers will have been pushed by portSAVE_CONTEXT(). */
+    *pxTopOfStack = 0xaa; /* acc */
+    pxTopOfStack++;
 
-        /* Next all the registers will have been pushed by portSAVE_CONTEXT(). */
-        *pxTopOfStack = 0xaa;        /* acc */
-        pxTopOfStack++;
+    /* We want tasks to start with interrupts enabled. */
+    *pxTopOfStack = portGLOBAL_INTERRUPT_BIT;
+    pxTopOfStack++;
 
-        /* We want tasks to start with interrupts enabled. */
-        *pxTopOfStack = portGLOBAL_INTERRUPT_BIT;
-        pxTopOfStack++;
+    /* The function parameters will be passed in the DPTR and B register as
+     * a three byte generic pointer is used. */
+    ulAddress = ( uint32_t ) pvParameters;
+    *pxTopOfStack = ( StackType_t ) ulAddress; /* DPL */
+    ulAddress >>= 8;
+    *pxTopOfStack++;
+    *pxTopOfStack = ( StackType_t ) ulAddress; /* DPH */
+    ulAddress >>= 8;
+    pxTopOfStack++;
+    *pxTopOfStack = ( StackType_t ) ulAddress; /* b */
+    pxTopOfStack++;
 
-        /* The function parameters will be passed in the DPTR and B register as
-        a three byte generic pointer is used. */
-        ulAddress = ( uint32_t ) pvParameters;
-        *pxTopOfStack = ( StackType_t ) ulAddress;        /* DPL */
-        ulAddress >>= 8;
-        *pxTopOfStack++;
-        *pxTopOfStack = ( StackType_t ) ulAddress;        /* DPH */
-        ulAddress >>= 8;
-        pxTopOfStack++;
-        *pxTopOfStack = ( StackType_t ) ulAddress;        /* b */
-        pxTopOfStack++;
+    /* The remaining registers are straight forward. */
+    *pxTopOfStack = 0x02; /* R2 */
+    pxTopOfStack++;
+    *pxTopOfStack = 0x03; /* R3 */
+    pxTopOfStack++;
+    *pxTopOfStack = 0x04; /* R4 */
+    pxTopOfStack++;
+    *pxTopOfStack = 0x05; /* R5 */
+    pxTopOfStack++;
+    *pxTopOfStack = 0x06; /* R6 */
+    pxTopOfStack++;
+    *pxTopOfStack = 0x07; /* R7 */
+    pxTopOfStack++;
+    *pxTopOfStack = 0x00; /* R0 */
+    pxTopOfStack++;
+    *pxTopOfStack = 0x01; /* R1 */
+    pxTopOfStack++;
+    *pxTopOfStack = 0x00; /* PSW */
+    pxTopOfStack++;
+    *pxTopOfStack = 0xbb; /* BP */
 
-        /* The remaining registers are straight forward. */
-        *pxTopOfStack = 0x02;        /* R2 */
-        pxTopOfStack++;
-        *pxTopOfStack = 0x03;        /* R3 */
-        pxTopOfStack++;
-        *pxTopOfStack = 0x04;        /* R4 */
-        pxTopOfStack++;
-        *pxTopOfStack = 0x05;        /* R5 */
-        pxTopOfStack++;
-        *pxTopOfStack = 0x06;        /* R6 */
-        pxTopOfStack++;
-        *pxTopOfStack = 0x07;        /* R7 */
-        pxTopOfStack++;
-        *pxTopOfStack = 0x00;        /* R0 */
-        pxTopOfStack++;
-        *pxTopOfStack = 0x01;        /* R1 */
-        pxTopOfStack++;
-        *pxTopOfStack = 0x00;        /* PSW */
-        pxTopOfStack++;
-        *pxTopOfStack = 0xbb;        /* BP */
+    /* Dont increment the stack size here as we don't want to include
+     * the stack size byte as part of the stack size count.
+     *
+     * Finally we place the stack size at the beginning. */
+    *pxStartOfStack = ( StackType_t ) ( pxTopOfStack - pxStartOfStack );
 
-        /* Dont increment the stack size here as we don't want to include
-        the stack size byte as part of the stack size count.
-
-        Finally we place the stack size at the beginning. */
-        *pxStartOfStack = ( StackType_t ) ( pxTopOfStack - pxStartOfStack );
-
-        /* Unlike most ports, we return the start of the stack as this is where the
-        size of the stack is stored. */
-        return pxStartOfStack;
+    /* Unlike most ports, we return the start of the stack as this is where the
+     * size of the stack is stored. */
+    return pxStartOfStack;
 }
 /*-----------------------------------------------------------*/
 
@@ -301,26 +304,26 @@ StackType_t *pxStartOfStack;
  */
 BaseType_t xPortStartScheduler( void )
 {
-        /* Setup timer 2 to generate the RTOS tick. */
-        prvSetupTimerInterrupt();
+    /* Setup timer 2 to generate the RTOS tick. */
+    prvSetupTimerInterrupt();
 
-        /* Make sure we start with the expected SFR page.  This line should not
-        really be required. */
-        SFRPAGE = 0;
+    /* Make sure we start with the expected SFR page.  This line should not
+     * really be required. */
+    SFRPAGE = 0;
 
-        /* Copy the stack for the first task to execute from XRAM into the stack,
-        restore the task context from the new stack, then start running the task. */
-        portCOPY_XRAM_TO_STACK();
-        portRESTORE_CONTEXT();
+    /* Copy the stack for the first task to execute from XRAM into the stack,
+     * restore the task context from the new stack, then start running the task. */
+    portCOPY_XRAM_TO_STACK();
+    portRESTORE_CONTEXT();
 
-        /* Should never get here! */
-        return pdTRUE;
+    /* Should never get here! */
+    return pdTRUE;
 }
 /*-----------------------------------------------------------*/
 
 void vPortEndScheduler( void )
 {
-        /* Not implemented for this port. */
+    /* Not implemented for this port. */
 }
 /*-----------------------------------------------------------*/
 
@@ -330,92 +333,92 @@ void vPortEndScheduler( void )
  */
 void vPortYield( void ) _naked
 {
-        /* Save the execution context onto the stack, then copy the entire stack
-        to XRAM.  This is necessary as the internal RAM is only large enough to
-        hold one stack, and we want one per task.
+    /* Save the execution context onto the stack, then copy the entire stack
+     * to XRAM.  This is necessary as the internal RAM is only large enough to
+     * hold one stack, and we want one per task.
+     *
+     * PERFORMANCE COULD BE IMPROVED BY ONLY COPYING TO XRAM IF A TASK SWITCH
+     * IS REQUIRED. */
+    portSAVE_CONTEXT();
+    portCOPY_STACK_TO_XRAM();
 
-        PERFORMANCE COULD BE IMPROVED BY ONLY COPYING TO XRAM IF A TASK SWITCH
-        IS REQUIRED. */
-        portSAVE_CONTEXT();
-        portCOPY_STACK_TO_XRAM();
+    /* Call the standard scheduler context switch function. */
+    vTaskSwitchContext();
 
-        /* Call the standard scheduler context switch function. */
-        vTaskSwitchContext();
-
-        /* Copy the stack of the task about to execute from XRAM into RAM and
-        restore it's context ready to run on exiting. */
-        portCOPY_XRAM_TO_STACK();
-        portRESTORE_CONTEXT();
+    /* Copy the stack of the task about to execute from XRAM into RAM and
+     * restore it's context ready to run on exiting. */
+    portCOPY_XRAM_TO_STACK();
+    portRESTORE_CONTEXT();
 }
 /*-----------------------------------------------------------*/
 
 #if configUSE_PREEMPTION == 1
-        void vTimer2ISR( void ) interrupt 5 _naked
+    void vTimer2ISR( void ) interrupt 5 _naked
+    {
+        /* Preemptive context switch function triggered by the timer 2 ISR.
+         * This does the same as vPortYield() (see above) with the addition
+         * of incrementing the RTOS tick count. */
+
+        portSAVE_CONTEXT();
+        portCOPY_STACK_TO_XRAM();
+
+        if( xTaskIncrementTick() != pdFALSE )
         {
-                /* Preemptive context switch function triggered by the timer 2 ISR.
-                This does the same as vPortYield() (see above) with the addition
-                of incrementing the RTOS tick count. */
-
-                portSAVE_CONTEXT();
-                portCOPY_STACK_TO_XRAM();
-
-                if( xTaskIncrementTick() != pdFALSE )
-                {
-                        vTaskSwitchContext();
-                }
-
-                portCLEAR_INTERRUPT_FLAG();
-                portCOPY_XRAM_TO_STACK();
-                portRESTORE_CONTEXT();
+            vTaskSwitchContext();
         }
-#else
-        void vTimer2ISR( void ) interrupt 5
-        {
-                /* When using the cooperative scheduler the timer 2 ISR is only
-                required to increment the RTOS tick count. */
 
-                xTaskIncrementTick();
-                portCLEAR_INTERRUPT_FLAG();
-        }
-#endif
+        portCLEAR_INTERRUPT_FLAG();
+        portCOPY_XRAM_TO_STACK();
+        portRESTORE_CONTEXT();
+    }
+#else /* if configUSE_PREEMPTION == 1 */
+    void vTimer2ISR( void ) interrupt 5
+    {
+        /* When using the cooperative scheduler the timer 2 ISR is only
+         * required to increment the RTOS tick count. */
+
+        xTaskIncrementTick();
+        portCLEAR_INTERRUPT_FLAG();
+    }
+#endif /* if configUSE_PREEMPTION == 1 */
 /*-----------------------------------------------------------*/
 
 static void prvSetupTimerInterrupt( void )
 {
-uint8_t ucOriginalSFRPage;
+    uint8_t ucOriginalSFRPage;
 
 /* Constants calculated to give the required timer capture values. */
-const uint32_t ulTicksPerSecond = configCPU_CLOCK_HZ / portCLOCK_DIVISOR;
-const uint32_t ulCaptureTime = ulTicksPerSecond / configTICK_RATE_HZ;
-const uint32_t ulCaptureValue = portMAX_TIMER_VALUE - ulCaptureTime;
-const uint8_t ucLowCaptureByte = ( uint8_t ) ( ulCaptureValue & ( uint32_t ) 0xff );
-const uint8_t ucHighCaptureByte = ( uint8_t ) ( ulCaptureValue >> ( uint32_t ) 8 );
+    const uint32_t ulTicksPerSecond = configCPU_CLOCK_HZ / portCLOCK_DIVISOR;
+    const uint32_t ulCaptureTime = ulTicksPerSecond / configTICK_RATE_HZ;
+    const uint32_t ulCaptureValue = portMAX_TIMER_VALUE - ulCaptureTime;
+    const uint8_t ucLowCaptureByte = ( uint8_t ) ( ulCaptureValue & ( uint32_t ) 0xff );
+    const uint8_t ucHighCaptureByte = ( uint8_t ) ( ulCaptureValue >> ( uint32_t ) 8 );
 
-        /* NOTE:  This uses a timer only present on 8052 architecture. */
+    /* NOTE:  This uses a timer only present on 8052 architecture. */
 
-        /* Remember the current SFR page so we can restore it at the end of the
-        function. */
-        ucOriginalSFRPage = SFRPAGE;
-        SFRPAGE = 0;
+    /* Remember the current SFR page so we can restore it at the end of the
+     * function. */
+    ucOriginalSFRPage = SFRPAGE;
+    SFRPAGE = 0;
 
-        /* TMR2CF can be left in its default state. */
-        TMR2CF = ( uint8_t ) 0;
+    /* TMR2CF can be left in its default state. */
+    TMR2CF = ( uint8_t ) 0;
 
-        /* Setup the overflow reload value. */
-        RCAP2L = ucLowCaptureByte;
-        RCAP2H = ucHighCaptureByte;
+    /* Setup the overflow reload value. */
+    RCAP2L = ucLowCaptureByte;
+    RCAP2H = ucHighCaptureByte;
 
-        /* The initial load is performed manually. */
-        TMR2L = ucLowCaptureByte;
-        TMR2H = ucHighCaptureByte;
+    /* The initial load is performed manually. */
+    TMR2L = ucLowCaptureByte;
+    TMR2H = ucHighCaptureByte;
 
-        /* Enable the timer 2 interrupts. */
-        IE |= portTIMER_2_INTERRUPT_ENABLE;
+    /* Enable the timer 2 interrupts. */
+    IE |= portTIMER_2_INTERRUPT_ENABLE;
 
-        /* Interrupts are disabled when this is called so the timer can be started
-        here. */
-        TMR2CN = portENABLE_TIMER;
+    /* Interrupts are disabled when this is called so the timer can be started
+     * here. */
+    TMR2CN = portENABLE_TIMER;
 
-        /* Restore the original SFR page. */
-        SFRPAGE = ucOriginalSFRPage;
+    /* Restore the original SFR page. */
+    SFRPAGE = ucOriginalSFRPage;
 }
diff --git a/portable/SDCC/Cygnal/portmacro.h b/portable/SDCC/Cygnal/portmacro.h
index 04186381f..7cfbc8cc9 100644
--- a/portable/SDCC/Cygnal/portmacro.h
+++ b/portable/SDCC/Cygnal/portmacro.h
@@ -49,23 +49,23 @@ void vSerialISR( void ) interrupt 4;
  */
 
 /* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      float
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint8_t
-#define portBASE_TYPE   char
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        float
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint8_t
+#define portBASE_TYPE     char
 
-typedef portSTACK_TYPE StackType_t;
-typedef signed char BaseType_t;
-typedef unsigned char UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef signed char      BaseType_t;
+typedef unsigned char    UBaseType_t;
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
-#elif ( configTICK_TYPE_WIDTH_IN_BITS  == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t             TickType_t;
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+    typedef uint32_t     TickType_t;
     #define portMAX_DELAY    ( TickType_t ) 0xffffffffUL
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -73,44 +73,47 @@ typedef unsigned char UBaseType_t;
 /*-----------------------------------------------------------*/
 
 /* Critical section management. */
-#define portENTER_CRITICAL()        _asm        \
-                                    push    ACC \
-                                    push    IE  \
-                                    _endasm;    \
-                                    EA = 0;
+#define portENTER_CRITICAL() \
+    _asm                     \
+    push ACC                 \
+    push IE                  \
+    _endasm;                 \
+    EA = 0;
 
-#define portEXIT_CRITICAL()         _asm            \
-                                    pop     ACC     \
-                                    _endasm;        \
-                                    ACC &= 0x80;    \
-                                    IE |= ACC;      \
-                                    _asm            \
-                                    pop     ACC     \
-                                    _endasm;
+#define portEXIT_CRITICAL() \
+    _asm                    \
+    pop ACC                 \
+    _endasm;                \
+    ACC &= 0x80;            \
+    IE |= ACC;              \
+    _asm                    \
+    pop ACC                 \
+        _endasm;
 
 #define portDISABLE_INTERRUPTS()    EA = 0;
 #define portENABLE_INTERRUPTS()     EA = 1;
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portBYTE_ALIGNMENT          1
-#define portSTACK_GROWTH            ( 1 )
-#define portTICK_PERIOD_MS          ( ( uint32_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT    1
+#define portSTACK_GROWTH      ( 1 )
+#define portTICK_PERIOD_MS    ( ( uint32_t ) 1000 / configTICK_RATE_HZ )
 /*-----------------------------------------------------------*/
 
 /* Task utilities. */
 void vPortYield( void ) _naked;
-#define portYIELD() vPortYield();
+#define portYIELD()    vPortYield();
 /*-----------------------------------------------------------*/
 
-#define portNOP()               _asm    \
-                                    nop \
-                                _endasm;
+#define portNOP() \
+    _asm          \
+    nop           \
+    _endasm;
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
 #endif /* PORTMACRO_H */
diff --git a/portable/Softune/MB91460/__STD_LIB_sbrk.c b/portable/Softune/MB91460/__STD_LIB_sbrk.c
index 87dfc54f7..0be354fec 100644
--- a/portable/Softune/MB91460/__STD_LIB_sbrk.c
+++ b/portable/Softune/MB91460/__STD_LIB_sbrk.c
@@ -30,26 +30,29 @@
 /* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */
 /* ELIGIBILITY FOR ANY PURPOSES.                                             */
 /*                 (C) Fujitsu Microelectronics Europe GmbH                  */
-/*---------------------------------------------------------------------------
-  __STD_LIB_sbrk.C
-  - Used by heap_3.c for memory accocation and deletion.
 
-/*---------------------------------------------------------------------------*/
+/*---------------------------------------------------------------------------
+ * __STD_LIB_sbrk.C
+ * - Used by heap_3.c for memory allocation and deletion.
+ *
+ * /*---------------------------------------------------------------------------*/
 
 #include "FreeRTOSConfig.h"
 #include <stdlib.h>
 
-    static  long         brk_siz  =  0;
-    typedef int          _heep_t;
-    #define ROUNDUP(s)   (((s)+sizeof(_heep_t)-1)&~(sizeof(_heep_t)-1))
-    static  _heep_t      _heep[ROUNDUP(configTOTAL_HEAP_SIZE)/sizeof(_heep_t)];
-    #define              _heep_size      ROUNDUP(configTOTAL_HEAP_SIZE)
+static long brk_siz = 0;
+typedef int _heep_t;
+#define ROUNDUP( s )    ( ( ( s ) + sizeof( _heep_t ) - 1 ) & ~( sizeof( _heep_t ) - 1 ) )
+static _heep_t _heep[ ROUNDUP( configTOTAL_HEAP_SIZE ) / sizeof( _heep_t ) ];
+#define              _heep_size    ROUNDUP( configTOTAL_HEAP_SIZE )
 
-    extern  char  *sbrk(int  size)
+extern char * sbrk( int size )
+{
+    if( ( brk_siz + size > _heep_size ) || ( brk_siz + size < 0 ) )
     {
-       if  (brk_siz  +  size  >  _heep_size  ||  brk_siz  +  size  <  0)
-
-          return((char*)-1);
-       brk_siz  +=  size;
-       return(  (char*)_heep  +  brk_siz  -  size);
+        return( ( char * ) -1 );
     }
+
+    brk_siz += size;
+    return( ( char * ) _heep + brk_siz - size );
+}
diff --git a/portable/Softune/MB91460/port.c b/portable/Softune/MB91460/port.c
index 08e197b06..b8248f2b3 100644
--- a/portable/Softune/MB91460/port.c
+++ b/portable/Softune/MB91460/port.c
@@ -33,7 +33,7 @@
 /*-----------------------------------------------------------*/
 
 /* We require the address of the pxCurrentTCB variable, but don't want to know
-any details of its type. */
+ * any details of its type. */
 typedef void TCB_t;
 extern volatile TCB_t * volatile pxCurrentTCB;
 
@@ -106,10 +106,12 @@ static void prvSetupTimerInterrupt( void );
  *
  * See the header file portable.h.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
     /* Place a few bytes of known values on the bottom of the stack.
-    This is just useful for debugging. */
+     * This is just useful for debugging. */
 
     *pxTopOfStack = 0x11111111;
     pxTopOfStack--;
@@ -119,9 +121,9 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
     pxTopOfStack--;
 
     /* This is a redundant push to the stack, it may be required if
-    in some implementations of the compiler the parameter to the task
-    is passed on to the stack rather than in R4 register. */
-    *pxTopOfStack = (StackType_t)(pvParameters);
+     * in some implementations of the compiler the parameter to the task
+     * is passed on to the stack rather than in R4 register. */
+    *pxTopOfStack = ( StackType_t ) ( pvParameters );
     pxTopOfStack--;
 
     *pxTopOfStack = ( StackType_t ) 0x00000000; /* RP */
@@ -134,36 +136,36 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
     pxTopOfStack--;
 
     /* In the current implementation of the compiler the first
-    parameter to the task (or function) is passed via R4 parameter
-    to the task, hence the pvParameters pointer is copied into the R4
-    register. See compiler manual section 4.6.2 for more information. */
-    *pxTopOfStack = ( StackType_t ) (pvParameters); /* R4 */
+     * parameter to the task (or function) is passed via R4 parameter
+     * to the task, hence the pvParameters pointer is copied into the R4
+     * register. See compiler manual section 4.6.2 for more information. */
+    *pxTopOfStack = ( StackType_t ) ( pvParameters ); /* R4 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x00003333; /* R3 */
+    *pxTopOfStack = ( StackType_t ) 0x00003333;       /* R3 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x00002222; /* R2 */
+    *pxTopOfStack = ( StackType_t ) 0x00002222;       /* R2 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x00001111; /* R1 */
+    *pxTopOfStack = ( StackType_t ) 0x00001111;       /* R1 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x00000001; /* R0 */
+    *pxTopOfStack = ( StackType_t ) 0x00000001;       /* R0 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x0000EEEE; /* R14 */
+    *pxTopOfStack = ( StackType_t ) 0x0000EEEE;       /* R14 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x0000DDDD; /* R13 */
+    *pxTopOfStack = ( StackType_t ) 0x0000DDDD;       /* R13 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x0000CCCC; /* R12 */
+    *pxTopOfStack = ( StackType_t ) 0x0000CCCC;       /* R12 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x0000BBBB; /* R11 */
+    *pxTopOfStack = ( StackType_t ) 0x0000BBBB;       /* R11 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x0000AAAA; /* R10 */
+    *pxTopOfStack = ( StackType_t ) 0x0000AAAA;       /* R10 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x00009999; /* R9 */
+    *pxTopOfStack = ( StackType_t ) 0x00009999;       /* R9 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x00008888; /* R8 */
+    *pxTopOfStack = ( StackType_t ) 0x00008888;       /* R8 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x11110000; /* MDH */
+    *pxTopOfStack = ( StackType_t ) 0x11110000;       /* MDH */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x22220000; /* MDL */
+    *pxTopOfStack = ( StackType_t ) 0x22220000;       /* MDL */
     pxTopOfStack--;
 
     /* The start of the task code. */
@@ -188,8 +190,8 @@ BaseType_t xPortStartScheduler( void )
     #pragma endasm
 
     /* Simulate a function call end as generated by the compiler.  We will now
-    jump to the start of the task the context of which we have just restored. */
-    __asm(" reti ");
+     * jump to the start of the task the context of which we have just restored. */
+    __asm( " reti " );
 
     /* Should not get here. */
     return pdFAIL;
@@ -199,39 +201,39 @@ BaseType_t xPortStartScheduler( void )
 void vPortEndScheduler( void )
 {
     /* Not implemented - unlikely to ever be required as there is nothing to
-    return to. */
+     * return to. */
 }
 /*-----------------------------------------------------------*/
 
 static void prvSetupTimerInterrupt( void )
 {
 /* The peripheral clock divided by 32 is used by the timer. */
-const uint16_t usReloadValue = ( uint16_t ) ( ( ( configPER_CLOCK_HZ / configTICK_RATE_HZ ) / 32UL ) - 1UL );
+    const uint16_t usReloadValue = ( uint16_t ) ( ( ( configPER_CLOCK_HZ / configTICK_RATE_HZ ) / 32UL ) - 1UL );
 
     /* Setup RLT0 to generate a tick interrupt. */
 
-    TMCSR0_CNTE = 0;        /* Count Disable */
-    TMCSR0_CSL = 0x2;       /* CLKP/32 */
-    TMCSR0_MOD = 0;         /* Software trigger */
-    TMCSR0_RELD = 1;        /* Reload */
+    TMCSR0_CNTE = 0;  /* Count Disable */
+    TMCSR0_CSL = 0x2; /* CLKP/32 */
+    TMCSR0_MOD = 0;   /* Software trigger */
+    TMCSR0_RELD = 1;  /* Reload */
 
-    TMCSR0_UF = 0;          /* Clear underflow flag */
+    TMCSR0_UF = 0;    /* Clear underflow flag */
     TMRLR0 = usReloadValue;
-    TMCSR0_INTE = 1;        /* Interrupt Enable */
-    TMCSR0_CNTE = 1;        /* Count Enable */
-    TMCSR0_TRG = 1;         /* Trigger */
+    TMCSR0_INTE = 1;  /* Interrupt Enable */
+    TMCSR0_CNTE = 1;  /* Count Enable */
+    TMCSR0_TRG = 1;   /* Trigger */
 
-    PORTEN = 0x3;           /* Port Enable */
+    PORTEN = 0x3;     /* Port Enable */
 }
 /*-----------------------------------------------------------*/
 
 #if configUSE_PREEMPTION == 1
 
-    /*
-     * Tick ISR for preemptive scheduler. The tick count is incremented
-     * after the context is saved. Then the context is switched if required,
-     * and last the context of the task which is to be resumed is restored.
-     */
+/*
+ * Tick ISR for preemptive scheduler. The tick count is incremented
+ * after the context is saved. Then the context is switched if required,
+ * and last the context of the task which is to be resumed is restored.
+ */
 
     #pragma asm
 
@@ -257,13 +259,13 @@ const uint16_t usReloadValue = ( uint16_t ) ( ( ( configPER_CLOCK_HZ / configTIC
 
     #pragma endasm
 
-#else
+#else /* if configUSE_PREEMPTION == 1 */
 
-    /*
-     * Tick ISR for the cooperative scheduler.  All this does is increment the
-     * tick count.  We don't need to switch context, this can only be done by
-     * manual calls to taskYIELD();
-     */
+/*
+ * Tick ISR for the cooperative scheduler.  All this does is increment the
+ * tick count.  We don't need to switch context, this can only be done by
+ * manual calls to taskYIELD();
+ */
     __interrupt void ReloadTimer0_IRQHandler( void )
     {
         /* Clear RLT0 interrupt flag */
@@ -271,7 +273,7 @@ const uint16_t usReloadValue = ( uint16_t ) ( ( ( configPER_CLOCK_HZ / configTIC
         xTaskIncrementTick();
     }
 
-#endif
+#endif /* if configUSE_PREEMPTION == 1 */
 
 /*
  * Manual context switch. We can use a __nosavereg attribute  as the context
diff --git a/portable/Softune/MB91460/portmacro.h b/portable/Softune/MB91460/portmacro.h
index 9ae6959c4..a80760b88 100644
--- a/portable/Softune/MB91460/portmacro.h
+++ b/portable/Softune/MB91460/portmacro.h
@@ -46,24 +46,24 @@
  */
 
 /* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint32_t
-#define portBASE_TYPE   long
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
-#elif ( configTICK_TYPE_WIDTH_IN_BITS  == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t             TickType_t;
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+    typedef uint32_t     TickType_t;
     #define portMAX_DELAY    ( TickType_t ) 0xffffffffUL
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -74,38 +74,38 @@ typedef unsigned long UBaseType_t;
 #if configKERNEL_INTERRUPT_PRIORITY != 30
     #error configKERNEL_INTERRUPT_PRIORITY (set in FreeRTOSConfig.h) must match the ILM value set in the following line - 30 (1Eh) being the default.
 #endif
-#define portDISABLE_INTERRUPTS() __asm(" STILM #1Eh ")
-#define portENABLE_INTERRUPTS() __asm(" STILM #1Fh ")
+#define portDISABLE_INTERRUPTS()    __asm( " STILM #1Eh " )
+#define portENABLE_INTERRUPTS()     __asm( " STILM #1Fh " )
 
-#define portENTER_CRITICAL()    \
-    __asm(" ST PS,@-R15 ");     \
-    __asm(" ANDCCR #0xef ");    \
+#define portENTER_CRITICAL()   \
+    __asm( " ST PS,@-R15 " );  \
+    __asm( " ANDCCR #0xef " ); \
 
 
-#define portEXIT_CRITICAL()     \
-    __asm(" LD @R15+,PS ");     \
+#define portEXIT_CRITICAL()   \
+    __asm( " LD @R15+,PS " ); \
 
 /*-----------------------------------------------------------*/
 
 /* Architecture specifics. */
-#define portSTACK_GROWTH            ( -1 )
-#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT          4
-#define portNOP()                   __asm( " nop " );
+#define portSTACK_GROWTH      ( -1 )
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT    4
+#define portNOP()    __asm( " nop " );
 /*-----------------------------------------------------------*/
 
 /* portYIELD() uses a SW interrupt */
-#define portYIELD()                 __asm( " INT #40H " );
+#define portYIELD()             __asm( " INT #40H " );
 
 /* portYIELD_FROM_ISR() uses delayed interrupt */
-#define portYIELD_FROM_ISR()            DICR_DLYI = 1
+#define portYIELD_FROM_ISR()    DICR_DLYI = 1
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
-#define portMINIMAL_STACK_SIZE configMINIMAL_STACK_SIZE
+#define portMINIMAL_STACK_SIZE    configMINIMAL_STACK_SIZE
 
 
 #endif /* PORTMACRO_H */
diff --git a/portable/Softune/MB96340/__STD_LIB_sbrk.c b/portable/Softune/MB96340/__STD_LIB_sbrk.c
index 87dfc54f7..0be354fec 100644
--- a/portable/Softune/MB96340/__STD_LIB_sbrk.c
+++ b/portable/Softune/MB96340/__STD_LIB_sbrk.c
@@ -30,26 +30,29 @@
 /* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */
 /* ELIGIBILITY FOR ANY PURPOSES.                                             */
 /*                 (C) Fujitsu Microelectronics Europe GmbH                  */
-/*---------------------------------------------------------------------------
-  __STD_LIB_sbrk.C
-  - Used by heap_3.c for memory accocation and deletion.
 
-/*---------------------------------------------------------------------------*/
+/*---------------------------------------------------------------------------
+ * __STD_LIB_sbrk.C
+ * - Used by heap_3.c for memory allocation and deletion.
+ *
+ * /*---------------------------------------------------------------------------*/
 
 #include "FreeRTOSConfig.h"
 #include <stdlib.h>
 
-    static  long         brk_siz  =  0;
-    typedef int          _heep_t;
-    #define ROUNDUP(s)   (((s)+sizeof(_heep_t)-1)&~(sizeof(_heep_t)-1))
-    static  _heep_t      _heep[ROUNDUP(configTOTAL_HEAP_SIZE)/sizeof(_heep_t)];
-    #define              _heep_size      ROUNDUP(configTOTAL_HEAP_SIZE)
+static long brk_siz = 0;
+typedef int _heep_t;
+#define ROUNDUP( s )    ( ( ( s ) + sizeof( _heep_t ) - 1 ) & ~( sizeof( _heep_t ) - 1 ) )
+static _heep_t _heep[ ROUNDUP( configTOTAL_HEAP_SIZE ) / sizeof( _heep_t ) ];
+#define              _heep_size    ROUNDUP( configTOTAL_HEAP_SIZE )
 
-    extern  char  *sbrk(int  size)
+extern char * sbrk( int size )
+{
+    if( ( brk_siz + size > _heep_size ) || ( brk_siz + size < 0 ) )
     {
-       if  (brk_siz  +  size  >  _heep_size  ||  brk_siz  +  size  <  0)
-
-          return((char*)-1);
-       brk_siz  +=  size;
-       return(  (char*)_heep  +  brk_siz  -  size);
+        return( ( char * ) -1 );
     }
+
+    brk_siz += size;
+    return( ( char * ) _heep + brk_siz - size );
+}
diff --git a/portable/Softune/MB96340/port.c b/portable/Softune/MB96340/port.c
index 23aede59a..21d2cc14d 100644
--- a/portable/Softune/MB96340/port.c
+++ b/portable/Softune/MB96340/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -30,8 +30,8 @@
 #include "task.h"
 
 /*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the 16FX port.
- *----------------------------------------------------------*/
+* Implementation of functions defined in portable.h for the 16FX port.
+*----------------------------------------------------------*/
 
 /*
  * Get current value of DPR and ADB registers
@@ -44,7 +44,7 @@ StackType_t xGet_DPR_ADB_bank( void );
 StackType_t xGet_DTB_PCB_bank( void );
 
 /*
- * Sets up the periodic ISR used for the RTOS tick.  This uses RLT0, but
+ * Sets up the periodic ISR used for the RTOS tick. This uses RLT0, but
  * can be done using any given RLT.
  */
 static void prvSetupRLT0Interrupt( void );
@@ -61,164 +61,164 @@ extern volatile TCB_t * volatile pxCurrentTCB;
 /*-----------------------------------------------------------*/
 
 /*
- * Macro to save a task context to the task stack. This macro  copies the
- * saved context (AH:AL, DPR:ADB, DTB:PCB , PC and PS) from  the   system
- * stack to task stack pointed by user stack pointer ( USP  for SMALL and
- * MEDIUM memory model amd USB:USP for COMPACT  and LARGE memory model ),
- * then  it pushes the general purpose registers RW0-RW7  on  to the task
- * stack. Finally the  resultant  stack  pointer  value is saved into the
- * task  control  block  so  it  can  be retrieved the next time the task
+ * Macro to save a task context to the task stack. This macro copies the
+ * saved context (AH:AL, DPR:ADB, DTB:PCB , PC and PS) from the system
+ * stack to task stack pointed by user stack pointer ( USP for SMALL and
+ * MEDIUM memory model amd USB:USP for COMPACT and LARGE memory model ),
+ * then it pushes the general purpose registers RW0-RW7 on to the task
+ * stack. Finally the resultant stack pointer value is saved into the
+ * task control block so it can be retrieved the next time the task
  * executes.
  */
-#if( ( configMEMMODEL == portSMALL ) || ( configMEMMODEL == portMEDIUM ) )
+#if ( ( configMEMMODEL == portSMALL ) || ( configMEMMODEL == portMEDIUM ) )
 
-    #define portSAVE_CONTEXT()                                          \
-            {   __asm(" POPW  A ");                                     \
-                __asm(" AND  CCR,#H'DF ");                              \
-                __asm(" PUSHW  A ");                                    \
-                __asm(" OR   CCR,#H'20 ");                              \
-                __asm(" POPW  A ");                                     \
-                __asm(" AND  CCR,#H'DF ");                              \
-                __asm(" PUSHW  A ");                                    \
-                __asm(" OR   CCR,#H'20 ");                              \
-                __asm(" POPW  A ");                                     \
-                __asm(" AND  CCR,#H'DF ");                              \
-                __asm(" PUSHW  A ");                                    \
-                __asm(" OR   CCR,#H'20 ");                              \
-                __asm(" POPW  A ");                                     \
-                __asm(" AND  CCR,#H'DF ");                              \
-                __asm(" PUSHW  A ");                                    \
-                __asm(" OR   CCR,#H'20 ");                              \
-                __asm(" POPW  A ");                                     \
-                __asm(" AND  CCR,#H'DF ");                              \
-                __asm(" PUSHW  A ");                                    \
-                __asm(" OR   CCR,#H'20 ");                              \
-                __asm(" POPW  A ");                                     \
-                __asm(" AND  CCR,#H'DF ");                              \
-                __asm(" PUSHW  A ");                                    \
-                __asm(" PUSHW (RW0,RW1,RW2,RW3,RW4,RW5,RW6,RW7) ");     \
-                __asm(" MOVW A, _pxCurrentTCB ");                       \
-                __asm(" MOVW A, SP ");                                  \
-                __asm(" SWAPW ");                                       \
-                __asm(" MOVW @AL, AH ");                                \
-                __asm(" OR   CCR,#H'20 ");                              \
-            }
+    #define portSAVE_CONTEXT()                              \
+    { __asm( " POPW  A " );                                 \
+      __asm( " AND  CCR,#H'DF " );                          \
+      __asm( " PUSHW  A " );                                \
+      __asm( " OR   CCR,#H'20 " );                          \
+      __asm( " POPW  A " );                                 \
+      __asm( " AND  CCR,#H'DF " );                          \
+      __asm( " PUSHW  A " );                                \
+      __asm( " OR   CCR,#H'20 " );                          \
+      __asm( " POPW  A " );                                 \
+      __asm( " AND  CCR,#H'DF " );                          \
+      __asm( " PUSHW  A " );                                \
+      __asm( " OR   CCR,#H'20 " );                          \
+      __asm( " POPW  A " );                                 \
+      __asm( " AND  CCR,#H'DF " );                          \
+      __asm( " PUSHW  A " );                                \
+      __asm( " OR   CCR,#H'20 " );                          \
+      __asm( " POPW  A " );                                 \
+      __asm( " AND  CCR,#H'DF " );                          \
+      __asm( " PUSHW  A " );                                \
+      __asm( " OR   CCR,#H'20 " );                          \
+      __asm( " POPW  A " );                                 \
+      __asm( " AND  CCR,#H'DF " );                          \
+      __asm( " PUSHW  A " );                                \
+      __asm( " PUSHW (RW0,RW1,RW2,RW3,RW4,RW5,RW6,RW7) " ); \
+      __asm( " MOVW A, _pxCurrentTCB " );                   \
+      __asm( " MOVW A, SP " );                              \
+      __asm( " SWAPW " );                                   \
+      __asm( " MOVW @AL, AH " );                            \
+      __asm( " OR   CCR,#H'20 " );                          \
+    }
 
 /*
- * Macro to restore a task context from the task stack.  This is effecti-
- * vely the reverse of SAVE_CONTEXT(). First the stack pointer  value
- * (USP for SMALL and MEDIUM memory model amd  USB:USP  for  COMPACT  and
- * LARGE memory model ) is loaded from the task  control block.  Next the
- * value of all the general purpose registers RW0-RW7 is retrieved. Fina-
- * lly it copies of the context ( AH:AL,  DPR:ADB, DTB:PCB, PC and PS) of
- * the task to be executed upon RETI from user stack to system stack.
+ * Macro to restore a task context from the task stack. This is
+ * effectively the reverse of SAVE_CONTEXT(). First the stack pointer
+ * value (USP for SMALL and MEDIUM memory model amd USB:USP for COMPACT
+ * and LARGE memory model ) is loaded from the task control block. Next the
+ * value of all the general purpose registers RW0-RW7 is retrieved.
+ * Finally it copies of the context ( AH:AL, DPR:ADB, DTB:PCB, PC and PS)
+ * of the task to be executed upon RETI from user stack to system stack.
  */
 
-    #define portRESTORE_CONTEXT()                                       \
-            {   __asm(" MOVW A, _pxCurrentTCB ");                       \
-                __asm(" MOVW A, @A ");                                  \
-                __asm(" AND  CCR,#H'DF ");                              \
-                __asm(" MOVW SP, A ");                                  \
-                __asm(" POPW (RW0,RW1,RW2,RW3,RW4,RW5,RW6,RW7) ");      \
-                __asm(" POPW  A ");                                     \
-                __asm(" OR   CCR,#H'20 ");                              \
-                __asm(" PUSHW  A ");                                    \
-                __asm(" AND  CCR,#H'DF ");                              \
-                __asm(" POPW  A ");                                     \
-                __asm(" OR   CCR,#H'20 ");                              \
-                __asm(" PUSHW  A ");                                    \
-                __asm(" AND  CCR,#H'DF ");                              \
-                __asm(" POPW  A ");                                     \
-                __asm(" OR   CCR,#H'20 ");                              \
-                __asm(" PUSHW  A ");                                    \
-                __asm(" AND  CCR,#H'DF ");                              \
-                __asm(" POPW  A ");                                     \
-                __asm(" OR   CCR,#H'20 ");                              \
-                __asm(" PUSHW  A ");                                    \
-                __asm(" AND  CCR,#H'DF ");                              \
-                __asm(" POPW  A ");                                     \
-                __asm(" OR   CCR,#H'20 ");                              \
-                __asm(" PUSHW  A ");                                    \
-                __asm(" AND  CCR,#H'DF ");                              \
-                __asm(" POPW  A ");                                     \
-                __asm(" OR   CCR,#H'20 ");                              \
-                __asm(" PUSHW  A ");                                    \
-            }
+    #define portRESTORE_CONTEXT()                          \
+    { __asm( " MOVW A, _pxCurrentTCB " );                  \
+      __asm( " MOVW A, @A " );                             \
+      __asm( " AND  CCR,#H'DF " );                         \
+      __asm( " MOVW SP, A " );                             \
+      __asm( " POPW (RW0,RW1,RW2,RW3,RW4,RW5,RW6,RW7) " ); \
+      __asm( " POPW  A " );                                \
+      __asm( " OR   CCR,#H'20 " );                         \
+      __asm( " PUSHW  A " );                               \
+      __asm( " AND  CCR,#H'DF " );                         \
+      __asm( " POPW  A " );                                \
+      __asm( " OR   CCR,#H'20 " );                         \
+      __asm( " PUSHW  A " );                               \
+      __asm( " AND  CCR,#H'DF " );                         \
+      __asm( " POPW  A " );                                \
+      __asm( " OR   CCR,#H'20 " );                         \
+      __asm( " PUSHW  A " );                               \
+      __asm( " AND  CCR,#H'DF " );                         \
+      __asm( " POPW  A " );                                \
+      __asm( " OR   CCR,#H'20 " );                         \
+      __asm( " PUSHW  A " );                               \
+      __asm( " AND  CCR,#H'DF " );                         \
+      __asm( " POPW  A " );                                \
+      __asm( " OR   CCR,#H'20 " );                         \
+      __asm( " PUSHW  A " );                               \
+      __asm( " AND  CCR,#H'DF " );                         \
+      __asm( " POPW  A " );                                \
+      __asm( " OR   CCR,#H'20 " );                         \
+      __asm( " PUSHW  A " );                               \
+    }
 
-#elif( ( configMEMMODEL == portCOMPACT ) || ( configMEMMODEL == portLARGE ) )
+#elif ( ( configMEMMODEL == portCOMPACT ) || ( configMEMMODEL == portLARGE ) )
 
-    #define portSAVE_CONTEXT()                                          \
-            {   __asm(" POPW  A ");                                     \
-                __asm(" AND  CCR,#H'DF ");                              \
-                __asm(" PUSHW  A ");                                    \
-                __asm(" OR   CCR,#H'20 ");                              \
-                __asm(" POPW  A ");                                     \
-                __asm(" AND  CCR,#H'DF ");                              \
-                __asm(" PUSHW  A ");                                    \
-                __asm(" OR   CCR,#H'20 ");                              \
-                __asm(" POPW  A ");                                     \
-                __asm(" AND  CCR,#H'DF ");                              \
-                __asm(" PUSHW  A ");                                    \
-                __asm(" OR   CCR,#H'20 ");                              \
-                __asm(" POPW  A ");                                     \
-                __asm(" AND  CCR,#H'DF ");                              \
-                __asm(" PUSHW  A ");                                    \
-                __asm(" OR   CCR,#H'20 ");                              \
-                __asm(" POPW  A ");                                     \
-                __asm(" AND  CCR,#H'DF ");                              \
-                __asm(" PUSHW  A ");                                    \
-                __asm(" OR   CCR,#H'20 ");                              \
-                __asm(" POPW  A ");                                     \
-                __asm(" AND  CCR,#H'DF ");                              \
-                __asm(" PUSHW  A ");                                    \
-                __asm(" PUSHW (RW0,RW1,RW2,RW3,RW4,RW5,RW6,RW7) ");     \
-                __asm(" MOVL A, _pxCurrentTCB ");                       \
-                __asm(" MOVL RL2, A ");                                 \
-                __asm(" MOVW A, SP ");                                  \
-                __asm(" MOVW @RL2+0, A ");                              \
-                __asm(" MOV A, USB ");                                  \
-                __asm(" MOV @RL2+2, A ");                               \
-            }
+    #define portSAVE_CONTEXT()                              \
+    { __asm( " POPW  A " );                                 \
+      __asm( " AND  CCR,#H'DF " );                          \
+      __asm( " PUSHW  A " );                                \
+      __asm( " OR   CCR,#H'20 " );                          \
+      __asm( " POPW  A " );                                 \
+      __asm( " AND  CCR,#H'DF " );                          \
+      __asm( " PUSHW  A " );                                \
+      __asm( " OR   CCR,#H'20 " );                          \
+      __asm( " POPW  A " );                                 \
+      __asm( " AND  CCR,#H'DF " );                          \
+      __asm( " PUSHW  A " );                                \
+      __asm( " OR   CCR,#H'20 " );                          \
+      __asm( " POPW  A " );                                 \
+      __asm( " AND  CCR,#H'DF " );                          \
+      __asm( " PUSHW  A " );                                \
+      __asm( " OR   CCR,#H'20 " );                          \
+      __asm( " POPW  A " );                                 \
+      __asm( " AND  CCR,#H'DF " );                          \
+      __asm( " PUSHW  A " );                                \
+      __asm( " OR   CCR,#H'20 " );                          \
+      __asm( " POPW  A " );                                 \
+      __asm( " AND  CCR,#H'DF " );                          \
+      __asm( " PUSHW  A " );                                \
+      __asm( " PUSHW (RW0,RW1,RW2,RW3,RW4,RW5,RW6,RW7) " ); \
+      __asm( " MOVL A, _pxCurrentTCB " );                   \
+      __asm( " MOVL RL2, A " );                             \
+      __asm( " MOVW A, SP " );                              \
+      __asm( " MOVW @RL2+0, A " );                          \
+      __asm( " MOV A, USB " );                              \
+      __asm( " MOV @RL2+2, A " );                           \
+    }
 
-    #define portRESTORE_CONTEXT()                                       \
-            {   __asm(" MOVL A, _pxCurrentTCB ");                       \
-                __asm(" MOVL RL2, A ");                                 \
-                __asm(" MOVW A, @RL2+0 ");                              \
-                __asm(" AND  CCR,#H'DF ");                              \
-                __asm(" MOVW SP, A ");                                  \
-                __asm(" MOV A, @RL2+2 ");                               \
-                __asm(" MOV USB, A ");                                  \
-                __asm(" POPW (RW0,RW1,RW2,RW3,RW4,RW5,RW6,RW7) ");      \
-                __asm(" POPW  A ");                                     \
-                __asm(" OR   CCR,#H'20 ");                              \
-                __asm(" PUSHW  A ");                                    \
-                __asm(" AND  CCR,#H'DF ");                              \
-                __asm(" POPW  A ");                                     \
-                __asm(" OR   CCR,#H'20 ");                              \
-                __asm(" PUSHW  A ");                                    \
-                __asm(" AND  CCR,#H'DF ");                              \
-                __asm(" POPW  A ");                                     \
-                __asm(" OR   CCR,#H'20 ");                              \
-                __asm(" PUSHW  A ");                                    \
-                __asm(" AND  CCR,#H'DF ");                              \
-                __asm(" POPW  A ");                                     \
-                __asm(" OR   CCR,#H'20 ");                              \
-                __asm(" PUSHW  A ");                                    \
-                __asm(" AND  CCR,#H'DF ");                              \
-                __asm(" POPW  A ");                                     \
-                __asm(" OR   CCR,#H'20 ");                              \
-                __asm(" PUSHW  A ");                                    \
-                __asm(" AND  CCR,#H'DF ");                              \
-                __asm(" POPW  A ");                                     \
-                __asm(" OR   CCR,#H'20 ");                              \
-                __asm(" PUSHW  A ");                                    \
-            }
-#endif
+    #define portRESTORE_CONTEXT()                          \
+    { __asm( " MOVL A, _pxCurrentTCB " );                  \
+      __asm( " MOVL RL2, A " );                            \
+      __asm( " MOVW A, @RL2+0 " );                         \
+      __asm( " AND  CCR,#H'DF " );                         \
+      __asm( " MOVW SP, A " );                             \
+      __asm( " MOV A, @RL2+2 " );                          \
+      __asm( " MOV USB, A " );                             \
+      __asm( " POPW (RW0,RW1,RW2,RW3,RW4,RW5,RW6,RW7) " ); \
+      __asm( " POPW  A " );                                \
+      __asm( " OR   CCR,#H'20 " );                         \
+      __asm( " PUSHW  A " );                               \
+      __asm( " AND  CCR,#H'DF " );                         \
+      __asm( " POPW  A " );                                \
+      __asm( " OR   CCR,#H'20 " );                         \
+      __asm( " PUSHW  A " );                               \
+      __asm( " AND  CCR,#H'DF " );                         \
+      __asm( " POPW  A " );                                \
+      __asm( " OR   CCR,#H'20 " );                         \
+      __asm( " PUSHW  A " );                               \
+      __asm( " AND  CCR,#H'DF " );                         \
+      __asm( " POPW  A " );                                \
+      __asm( " OR   CCR,#H'20 " );                         \
+      __asm( " PUSHW  A " );                               \
+      __asm( " AND  CCR,#H'DF " );                         \
+      __asm( " POPW  A " );                                \
+      __asm( " OR   CCR,#H'20 " );                         \
+      __asm( " PUSHW  A " );                               \
+      __asm( " AND  CCR,#H'DF " );                         \
+      __asm( " POPW  A " );                                \
+      __asm( " OR   CCR,#H'20 " );                         \
+      __asm( " PUSHW  A " );                               \
+    }
+#endif /* if ( ( configMEMMODEL == portSMALL ) || ( configMEMMODEL == portMEDIUM ) ) */
 
 /*-----------------------------------------------------------*/
 
 /*
- * Functions for obtaining the current value  of  DPR:ADB, DTB:PCB bank registers
+ * Functions for obtaining the current value of DPR:ADB, DTB:PCB bank registers
  */
 
 #pragma asm
@@ -261,10 +261,12 @@ _xGet_DTB_PCB_bank:
  *
  * See the header file portable.h.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
     /* Place a few bytes of known values on the bottom of the stack.
-    This is just useful for debugging. */
+     * This is just useful for debugging. */
     *pxTopOfStack = 0x1111;
     pxTopOfStack--;
     *pxTopOfStack = 0x2222;
@@ -272,12 +274,12 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
     *pxTopOfStack = 0x3333;
     pxTopOfStack--;
 
-    /* Once the task is called the task  would  push  the  pointer to the
-    parameter onto the stack. Hence here the pointer would be copied to the stack
-    first.  When using the COMPACT or LARGE memory model the pointer would be 24
-    bits, and when using the SMALL or MEDIUM memory model the pointer would be 16
-    bits. */
-    #if( ( configMEMMODEL == portCOMPACT ) || ( configMEMMODEL == portLARGE ) )
+    /* Once the task is called the task would push the pointer to the
+     * parameter onto the stack. Hence here the pointer would be copied to the stack
+     * first. When using the COMPACT or LARGE memory model the pointer would be 24
+     * bits, and when using the SMALL or MEDIUM memory model the pointer would be 16
+     * bits. */
+    #if ( ( configMEMMODEL == portCOMPACT ) || ( configMEMMODEL == portLARGE ) )
     {
         *pxTopOfStack = ( StackType_t ) ( ( uint32_t ) ( pvParameters ) >> 16 );
         pxTopOfStack--;
@@ -288,9 +290,9 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
     pxTopOfStack--;
 
     /* This is redundant push to the stack. This is required in order to introduce
-    an offset so that the task accesses a parameter correctly that is passed on to
-    the task stack. */
-    #if( ( configMEMMODEL == portMEDIUM ) || ( configMEMMODEL == portLARGE ) )
+     * an offset so that the task accesses a parameter correctly that is passed on to
+     * the task stack. */
+    #if ( ( configMEMMODEL == portMEDIUM ) || ( configMEMMODEL == portLARGE ) )
     {
         *pxTopOfStack = ( xGet_DTB_PCB_bank() & 0xff00 ) | ( ( ( int32_t ) ( pxCode ) >> 16 ) & 0xff );
         pxTopOfStack--;
@@ -298,7 +300,7 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
     #endif
 
     /* This is redundant push to the stack. This is required in order to introduce
-    an offset so the task correctly accesses the parameter passed on the task stack. */
+     * an offset so the task correctly accesses the parameter passed on the task stack. */
     *pxTopOfStack = ( StackType_t ) ( pxCode );
     pxTopOfStack--;
 
@@ -319,15 +321,15 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
     #endif
 
     /* DTB | PCB, in case of MEDIUM and LARGE memory models, PCB would be used
-    along with PC to indicate the start address of the function. */
-    #if( ( configMEMMODEL == portMEDIUM ) || ( configMEMMODEL == portLARGE ) )
+     * along with PC to indicate the start address of the function. */
+    #if ( ( configMEMMODEL == portMEDIUM ) || ( configMEMMODEL == portLARGE ) )
     {
         *pxTopOfStack = ( xGet_DTB_PCB_bank() & 0xff00 ) | ( ( ( int32_t ) ( pxCode ) >> 16 ) & 0xff );
         pxTopOfStack--;
     }
     #endif
 
-    /* DPR | ADB  */
+    /* DPR | ADB */
     *pxTopOfStack = xGet_DPR_ADB_bank();
     pxTopOfStack--;
 
@@ -363,7 +365,7 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
 static void prvSetupRLT0Interrupt( void )
 {
 /* The peripheral clock divided by 16 is used by the timer. */
-const uint16_t usReloadValue = ( uint16_t ) ( ( ( configCLKP1_CLOCK_HZ / configTICK_RATE_HZ ) / 16UL ) - 1UL );
+    const uint16_t usReloadValue = ( uint16_t ) ( ( ( configCLKP1_CLOCK_HZ / configTICK_RATE_HZ ) / 16UL ) - 1UL );
 
     /* set reload value = 34999+1, TICK Interrupt after 10 ms @ 56MHz of CLKP1 */
     TMRLR0 = usReloadValue;
@@ -381,9 +383,9 @@ BaseType_t xPortStartScheduler( void )
     /* Restore the context of the first task that is going to run. */
     portRESTORE_CONTEXT();
 
-    /* Simulate a function call end as generated by the compiler.  We will now
-    jump to the start of the task the context of which we have just restored. */
-    __asm(" reti ");
+    /* Simulate a function call end as generated by the compiler. We will now
+     * jump to the start of the task the context of which we have just restored. */
+    __asm( " reti " );
 
 
     /* Should not get here. */
@@ -394,7 +396,7 @@ BaseType_t xPortStartScheduler( void )
 void vPortEndScheduler( void )
 {
     /* Not implemented - unlikely to ever be required as there is nothing to
-    return to. */
+     * return to. */
 }
 
 /*-----------------------------------------------------------*/
@@ -406,12 +408,12 @@ void vPortEndScheduler( void )
 
 #if configUSE_PREEMPTION == 1
 
-    /*
-     * Tick ISR for preemptive scheduler.  We can use a __nosavereg attribute
-     * as the context is to be saved by the portSAVE_CONTEXT() macro, not the
-     * compiler generated code.  The tick count is incremented after the context
-     * is saved.
-     */
+/*
+ * Tick ISR for preemptive scheduler. We can use a __nosavereg attribute
+ * as the context is to be saved by the portSAVE_CONTEXT() macro, not the
+ * compiler generated code. The tick count is incremented after the context
+ * is saved.
+ */
     __nosavereg __interrupt void prvRLT0_TICKISR( void )
     {
         /* Disable interrupts so that portSAVE_CONTEXT() is not interrupted */
@@ -427,7 +429,7 @@ void vPortEndScheduler( void )
         TMCSR0_UF = 0;
 
         /* Increment the tick count then switch to the highest priority task
-        that is ready to run. */
+         * that is ready to run. */
         if( xTaskIncrementTick() != pdFALSE )
         {
             vTaskSwitchContext();
@@ -443,13 +445,13 @@ void vPortEndScheduler( void )
         __EI();
     }
 
-#else
+#else /* if configUSE_PREEMPTION == 1 */
 
-    /*
-     * Tick ISR for the cooperative scheduler.  All this does is increment the
-     * tick count.  We don't need to switch context, this can only be done by
-     * manual calls to taskYIELD();
-     */
+/*
+ * Tick ISR for the cooperative scheduler. All this does is increment the
+ * tick count. We don't need to switch context, this can only be done by
+ * manual calls to taskYIELD();
+ */
     __interrupt void prvRLT0_TICKISR( void )
     {
         /* Clear RLT0 interrupt flag */
@@ -458,12 +460,12 @@ void vPortEndScheduler( void )
         xTaskIncrementTick();
     }
 
-#endif
+#endif /* if configUSE_PREEMPTION == 1 */
 
 /*-----------------------------------------------------------*/
 
 /*
- * Manual context switch. We can use a __nosavereg attribute  as the context
+ * Manual context switch. We can use a __nosavereg attribute as the context
  * is to be saved by the portSAVE_CONTEXT() macro, not the compiler generated
  * code.
  */
@@ -492,7 +494,7 @@ __nosavereg __interrupt void vPortYieldDelayed( void )
     __EI();
 
     /* Clear delayed interrupt flag */
-    __asm (" CLRB  03A4H:0 ");
+    __asm( " CLRB  03A4H:0 " );
 
     /* Switch to the highest priority task that is ready to run. */
     vTaskSwitchContext();
diff --git a/portable/Softune/MB96340/portmacro.h b/portable/Softune/MB96340/portmacro.h
index 827874fde..7f36aad59 100644
--- a/portable/Softune/MB96340/portmacro.h
+++ b/portable/Softune/MB96340/portmacro.h
@@ -34,11 +34,11 @@
 #include <stddef.h>
 
 /* Constants denoting the available memory models.  These are used within
-FreeRTOSConfig.h to set the configMEMMODEL value. */
-#define portSMALL     0
-#define portMEDIUM    1
-#define portCOMPACT   2
-#define portLARGE     3
+ * FreeRTOSConfig.h to set the configMEMMODEL value. */
+#define portSMALL      0
+#define portMEDIUM     1
+#define portCOMPACT    2
+#define portLARGE      3
 
 
 /*-----------------------------------------------------------
@@ -52,24 +52,24 @@ FreeRTOSConfig.h to set the configMEMMODEL value. */
  */
 
 /* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint16_t
-#define portBASE_TYPE   short
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint16_t
+#define portBASE_TYPE     short
 
-typedef portSTACK_TYPE StackType_t;
-typedef short BaseType_t;
-typedef unsigned short UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef short            BaseType_t;
+typedef unsigned short   UBaseType_t;
 
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
-#elif ( configTICK_TYPE_WIDTH_IN_BITS  == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t             TickType_t;
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+    typedef uint32_t     TickType_t;
     #define portMAX_DELAY    ( TickType_t ) 0xffffffffUL
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -80,39 +80,39 @@ typedef unsigned short UBaseType_t;
 #if configKERNEL_INTERRUPT_PRIORITY != 6
     #error configKERNEL_INTERRUPT_PRIORITY (set in FreeRTOSConfig.h) must match the ILM value set in the following line - #06H being the default.
 #endif
-#define portDISABLE_INTERRUPTS()    __asm(" MOV ILM, #06h ")
-#define portENABLE_INTERRUPTS()     __asm(" MOV ILM, #07h ")
+#define portDISABLE_INTERRUPTS()    __asm( " MOV ILM, #06h " )
+#define portENABLE_INTERRUPTS()     __asm( " MOV ILM, #07h " )
 
-#define portENTER_CRITICAL()                                \
-        {   __asm(" PUSHW PS ");                            \
-            portDISABLE_INTERRUPTS();                       \
-        }
+#define portENTER_CRITICAL()    \
+    { __asm( " PUSHW PS " );    \
+      portDISABLE_INTERRUPTS(); \
+    }
 
-#define portEXIT_CRITICAL()                                 \
-        {   __asm(" POPW PS ");                             \
-        }
+#define portEXIT_CRITICAL() \
+    { __asm( " POPW PS " ); \
+    }
 
 /*-----------------------------------------------------------*/
 
 /* Architecture specifics. */
-#define portSTACK_GROWTH            ( -1 )
-#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT          2
-#define portNOP()                   __asm( " NOP " );
+#define portSTACK_GROWTH      ( -1 )
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT    2
+#define portNOP()    __asm( " NOP " );
 /*-----------------------------------------------------------*/
 
 /* portYIELD() uses SW interrupt */
-#define portYIELD()                 __asm( " INT #122 " );
+#define portYIELD()             __asm( " INT #122 " );
 
 /* portYIELD_FROM_ISR() uses delayed interrupt */
-#define portYIELD_FROM_ISR()         __asm( " SETB  03A4H:0 " );
+#define portYIELD_FROM_ISR()    __asm( " SETB  03A4H:0 " );
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
-#define portMINIMAL_STACK_SIZE configMINIMAL_STACK_SIZE
+#define portMINIMAL_STACK_SIZE    configMINIMAL_STACK_SIZE
 
 
 #endif /* PORTMACRO_H */
diff --git a/portable/Tasking/ARM_CM4F/port.c b/portable/Tasking/ARM_CM4F/port.c
old mode 100755
new mode 100644
index 4ba5da739..55237166b
--- a/portable/Tasking/ARM_CM4F/port.c
+++ b/portable/Tasking/ARM_CM4F/port.c
@@ -35,26 +35,26 @@
 #include "task.h"
 
 /* Constants required to manipulate the NVIC. */
-#define portNVIC_SYSTICK_CTRL       ( ( volatile uint32_t * ) 0xe000e010 )
-#define portNVIC_SYSTICK_LOAD       ( ( volatile uint32_t * ) 0xe000e014 )
-#define portNVIC_SHPR3_REG          ( ( volatile uint32_t * ) 0xe000ed20 )
-#define portNVIC_SYSTICK_CLK        0x00000004
-#define portNVIC_SYSTICK_INT        0x00000002
-#define portNVIC_SYSTICK_ENABLE     0x00000001
-#define portMIN_INTERRUPT_PRIORITY  ( 255UL )
-#define portNVIC_PENDSV_PRI         ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
-#define portNVIC_SYSTICK_PRI        ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
+#define portNVIC_SYSTICK_CTRL         ( ( volatile uint32_t * ) 0xe000e010 )
+#define portNVIC_SYSTICK_LOAD         ( ( volatile uint32_t * ) 0xe000e014 )
+#define portNVIC_SHPR3_REG            ( ( volatile uint32_t * ) 0xe000ed20 )
+#define portNVIC_SYSTICK_CLK          0x00000004
+#define portNVIC_SYSTICK_INT          0x00000002
+#define portNVIC_SYSTICK_ENABLE       0x00000001
+#define portMIN_INTERRUPT_PRIORITY    ( 255UL )
+#define portNVIC_PENDSV_PRI           ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI          ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
 
 /* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
-#define portVECTACTIVE_MASK         ( 0xFFUL )
+#define portVECTACTIVE_MASK           ( 0xFFUL )
 
 /* Constants required to manipulate the VFP. */
-#define portFPCCR                   ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
-#define portASPEN_AND_LSPEN_BITS    ( 0x3UL << 30UL )
+#define portFPCCR                     ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
+#define portASPEN_AND_LSPEN_BITS      ( 0x3UL << 30UL )
 
 /* Constants required to set up the initial stack. */
-#define portINITIAL_XPSR            ( 0x01000000 )
-#define portINITIAL_EXC_RETURN      ( 0xfffffffd )
+#define portINITIAL_XPSR              ( 0x01000000 )
+#define portINITIAL_EXC_RETURN        ( 0xfffffffd )
 
 /* Let the user override the pre-loading of the initial LR with the address of
  * prvTaskExitError() in case it messes up unwinding of the stack in the
@@ -266,4 +266,4 @@ void prvSetupTimerInterrupt( void )
     /* Configure SysTick to interrupt at the requested rate. */
     *( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
     *( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
-}
\ No newline at end of file
+}
diff --git a/portable/Tasking/ARM_CM4F/portmacro.h b/portable/Tasking/ARM_CM4F/portmacro.h
index 1c3588b86..1f159e4b8 100644
--- a/portable/Tasking/ARM_CM4F/portmacro.h
+++ b/portable/Tasking/ARM_CM4F/portmacro.h
@@ -28,7 +28,7 @@
 
 
 #ifndef PORTMACRO_H
-    #define PORTMACRO_H
+#define PORTMACRO_H
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
@@ -47,49 +47,49 @@
  */
 
 /* Type definitions. */
-    #define portCHAR          char
-    #define portFLOAT         float
-    #define portDOUBLE        double
-    #define portLONG          long
-    #define portSHORT         short
-    #define portSTACK_TYPE    uint32_t
-    #define portBASE_TYPE     long
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-    typedef portSTACK_TYPE   StackType_t;
-    typedef long             BaseType_t;
-    typedef unsigned long    UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
 
-    #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-        typedef uint16_t     TickType_t;
-        #define portMAX_DELAY              ( TickType_t ) 0xffff
-    #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-        typedef uint32_t     TickType_t;
-        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
  * not need to be guarded with a critical section. */
-        #define portTICK_TYPE_IS_ATOMIC    1
-    #else
-        #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
-    #endif
+    #define portTICK_TYPE_IS_ATOMIC    1
+#else
+    #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+#endif
 /*-----------------------------------------------------------*/
 
 /* Architecture specifics. */
-    #define portSTACK_GROWTH      ( -1 )
-    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-    #define portBYTE_ALIGNMENT    8
+#define portSTACK_GROWTH      ( -1 )
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT    8
 /*-----------------------------------------------------------*/
 
 
 /* Scheduler utilities. */
-    extern void vPortYield( void );
-    #define portNVIC_INT_CTRL     ( ( volatile uint32_t * ) 0xe000ed04 )
-    #define portNVIC_PENDSVSET    0x10000000
-    #define portYIELD()                                 vPortYield()
+extern void vPortYield( void );
+#define portNVIC_INT_CTRL     ( ( volatile uint32_t * ) 0xe000ed04 )
+#define portNVIC_PENDSVSET    0x10000000
+#define portYIELD()                                 vPortYield()
 
-    #define portEND_SWITCHING_ISR( xSwitchRequired )    if( xSwitchRequired ) *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET
-    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+#define portEND_SWITCHING_ISR( xSwitchRequired )    if( xSwitchRequired ) *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET
+#define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
 
@@ -99,36 +99,36 @@
  * Set basepri to portMAX_SYSCALL_INTERRUPT_PRIORITY without effecting other
  * registers.  r0 is clobbered.
  */
-    #define portSET_INTERRUPT_MASK()      __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#define portSET_INTERRUPT_MASK()      __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY )
 
 /*
  * Set basepri back to 0 without effective other registers.
  * r0 is clobbered.  FAQ:  Setting BASEPRI to 0 is not a bug.  Please see
  * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing.
  */
-    #define portCLEAR_INTERRUPT_MASK()    __set_BASEPRI( 0 )
+#define portCLEAR_INTERRUPT_MASK()    __set_BASEPRI( 0 )
 
-    extern uint32_t ulPortSetInterruptMask( void );
-    extern void vPortClearInterruptMask( uint32_t ulNewMask );
-    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulPortSetInterruptMask()
-    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vPortClearInterruptMask( x )
+extern uint32_t ulPortSetInterruptMask( void );
+extern void vPortClearInterruptMask( uint32_t ulNewMask );
+#define portSET_INTERRUPT_MASK_FROM_ISR()         ulPortSetInterruptMask()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vPortClearInterruptMask( x )
 
 
-    extern void vPortEnterCritical( void );
-    extern void vPortExitCritical( void );
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
 
-    #define portDISABLE_INTERRUPTS()    portSET_INTERRUPT_MASK()
-    #define portENABLE_INTERRUPTS()     portCLEAR_INTERRUPT_MASK()
-    #define portENTER_CRITICAL()        vPortEnterCritical()
-    #define portEXIT_CRITICAL()         vPortExitCritical()
+#define portDISABLE_INTERRUPTS()    portSET_INTERRUPT_MASK()
+#define portENABLE_INTERRUPTS()     portCLEAR_INTERRUPT_MASK()
+#define portENTER_CRITICAL()        vPortEnterCritical()
+#define portEXIT_CRITICAL()         vPortExitCritical()
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
-    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
-    #define portNOP()
+#define portNOP()
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/ThirdParty/CDK/T-HEAD_CK802/port.c b/portable/ThirdParty/CDK/T-HEAD_CK802/port.c
index 964ddd96c..900bae8b7 100644
--- a/portable/ThirdParty/CDK/T-HEAD_CK802/port.c
+++ b/portable/ThirdParty/CDK/T-HEAD_CK802/port.c
@@ -26,39 +26,41 @@
 #include "FreeRTOS.h"
 #include "task.h"
 
-extern void vPortStartTask(void);
+extern void vPortStartTask( void );
 
 /* Used to keep track of the number of nested calls to taskENTER_CRITICAL().  This
-will be set to 0 prior to the first task being started. */
+ * will be set to 0 prior to the first task being started. */
 portLONG ulCriticalNesting = 0x9999UL;
 
 /* Used to record one tack want to swtich task after enter critical area, we need know it
  * and implement task switch after exit critical area */
 portLONG pendsvflag = 0;
 
-StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
-    StackType_t *stk  = NULL;
+    StackType_t * stk = NULL;
 
     stk = pxTopOfStack;
 
-    *(--stk)  = (uint32_t)pxCode;            /* Entry Point                                         */
-    *(--stk)  = (uint32_t)0xE0000140L;       /* PSR                                                 */
-    *(--stk)  = (uint32_t)0xFFFFFFFEL;       /* R15 (LR) (init value will cause fault if ever used) */
-    *(--stk)  = (uint32_t)0x13131313L;       /* R13                                                 */
-    *(--stk)  = (uint32_t)0x12121212L;       /* R12                                                 */
-    *(--stk)  = (uint32_t)0x11111111L;       /* R11                                                 */
-    *(--stk)  = (uint32_t)0x10101010L;       /* R10                                                 */
-    *(--stk)  = (uint32_t)0x09090909L;       /* R9                                                  */
-    *(--stk)  = (uint32_t)0x08080808L;       /* R8                                                  */
-    *(--stk)  = (uint32_t)0x07070707L;       /* R7                                                  */
-    *(--stk)  = (uint32_t)0x06060606L;       /* R6                                                  */
-    *(--stk)  = (uint32_t)0x05050505L;       /* R5                                                  */
-    *(--stk)  = (uint32_t)0x04040404L;       /* R4                                                  */
-    *(--stk)  = (uint32_t)0x03030303L;       /* R3                                                  */
-    *(--stk)  = (uint32_t)0x02020202L;       /* R2                                                  */
-    *(--stk)  = (uint32_t)0x01010101L;       /* R1                                                  */
-    *(--stk)  = (uint32_t)pvParameters;      /* R0 : argument                                       */
+    *( --stk ) = ( uint32_t ) pxCode;       /* Entry Point                                         */
+    *( --stk ) = ( uint32_t ) 0xE0000140L;  /* PSR                                                 */
+    *( --stk ) = ( uint32_t ) 0xFFFFFFFEL;  /* R15 (LR) (init value will cause fault if ever used) */
+    *( --stk ) = ( uint32_t ) 0x13131313L;  /* R13                                                 */
+    *( --stk ) = ( uint32_t ) 0x12121212L;  /* R12                                                 */
+    *( --stk ) = ( uint32_t ) 0x11111111L;  /* R11                                                 */
+    *( --stk ) = ( uint32_t ) 0x10101010L;  /* R10                                                 */
+    *( --stk ) = ( uint32_t ) 0x09090909L;  /* R9                                                  */
+    *( --stk ) = ( uint32_t ) 0x08080808L;  /* R8                                                  */
+    *( --stk ) = ( uint32_t ) 0x07070707L;  /* R7                                                  */
+    *( --stk ) = ( uint32_t ) 0x06060606L;  /* R6                                                  */
+    *( --stk ) = ( uint32_t ) 0x05050505L;  /* R5                                                  */
+    *( --stk ) = ( uint32_t ) 0x04040404L;  /* R4                                                  */
+    *( --stk ) = ( uint32_t ) 0x03030303L;  /* R3                                                  */
+    *( --stk ) = ( uint32_t ) 0x02020202L;  /* R2                                                  */
+    *( --stk ) = ( uint32_t ) 0x01010101L;  /* R1                                                  */
+    *( --stk ) = ( uint32_t ) pvParameters; /* R0 : argument                                       */
 
     return stk;
 }
@@ -81,21 +83,25 @@ void vPortEndScheduler( void )
 void vPortEnterCritical( void )
 {
     portDISABLE_INTERRUPTS();
-    ulCriticalNesting ++;
+    ulCriticalNesting++;
 }
 
 void vPortExitCritical( void )
 {
-    if (ulCriticalNesting == 0) {
-        while(1);
+    if( ulCriticalNesting == 0 )
+    {
+        while( 1 )
+        {
+        }
     }
 
-    ulCriticalNesting --;
-    if (ulCriticalNesting == 0)
+    ulCriticalNesting--;
+
+    if( ulCriticalNesting == 0 )
     {
         portENABLE_INTERRUPTS();
 
-        if (pendsvflag)
+        if( pendsvflag )
         {
             pendsvflag = 0;
             portYIELD();
@@ -104,30 +110,30 @@ void vPortExitCritical( void )
 }
 
 #if configUSE_PREEMPTION == 0
-void xPortSysTickHandler( void )
-{
-    portLONG ulDummy;
+    void xPortSysTickHandler( void )
+    {
+        portLONG ulDummy;
 
-    ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
-    xTaskIncrementTick();
-    portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
-}
+        ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
+        xTaskIncrementTick();
+        portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
+    }
 
 #else
-void xPortSysTickHandler( void )
-{
-    portLONG ulDummy;
-
-    ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
+    void xPortSysTickHandler( void )
     {
-        if (xTaskIncrementTick() != pdFALSE)
+        portLONG ulDummy;
+
+        ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
         {
-            portYIELD_FROM_ISR(pdTRUE);
+            if( xTaskIncrementTick() != pdFALSE )
+            {
+                portYIELD_FROM_ISR( pdTRUE );
+            }
         }
+        portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
     }
-    portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
-}
-#endif
+#endif /* if configUSE_PREEMPTION == 0 */
 
 void vPortYieldHandler( void )
 {
@@ -140,12 +146,17 @@ void vPortYieldHandler( void )
     portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask );
 }
 
-__attribute__((weak)) void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed portCHAR *pcTaskName )
+__attribute__( ( weak ) ) void vApplicationStackOverflowHook( xTaskHandle * pxTask,
+                                                              signed portCHAR * pcTaskName )
 {
-    for(;;);
+    for( ; ; )
+    {
+    }
 }
 
-__attribute__((weak)) void vApplicationMallocFailedHook( void )
+__attribute__( ( weak ) ) void vApplicationMallocFailedHook( void )
 {
-    for(;;);
+    for( ; ; )
+    {
+    }
 }
diff --git a/portable/ThirdParty/CDK/T-HEAD_CK802/portmacro.h b/portable/ThirdParty/CDK/T-HEAD_CK802/portmacro.h
index 2c6979faf..d91f5251e 100644
--- a/portable/ThirdParty/CDK/T-HEAD_CK802/portmacro.h
+++ b/portable/ThirdParty/CDK/T-HEAD_CK802/portmacro.h
@@ -29,7 +29,7 @@
 #include <stdint.h>
 #include <csi_core.h>
 
-extern void vPortYield(void);
+extern void vPortYield( void );
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
@@ -50,24 +50,24 @@ extern void vPortYield(void);
  */
 
 /* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint32_t
-#define portBASE_TYPE   long
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-typedef void (*portvectorfunc)(void);
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
+typedef void (* portvectorfunc)( void );
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t  TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
-#elif ( configTICK_TYPE_WIDTH_IN_BITS  == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t             TickType_t;
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+    typedef uint32_t     TickType_t;
     #define portMAX_DELAY    ( TickType_t ) 0xffffffffUL
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -75,10 +75,10 @@ typedef void (*portvectorfunc)(void);
 
 
 /* Hardware specifics. */
-#define portBYTE_ALIGNMENT          8
-#define portSTACK_GROWTH            -1
-#define portMS_PERIOD_TICK          10
-#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT    8
+#define portSTACK_GROWTH      -1
+#define portMS_PERIOD_TICK    10
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
 
 
 static inline void vPortEnableInterrupt( void )
@@ -91,69 +91,72 @@ static inline void vPortDisableInterrupt( void )
     __disable_irq();
 }
 
-static inline portLONG GetCurrentPSR (void)
+static inline portLONG GetCurrentPSR( void )
 {
     return __get_PSR();
 }
 
-static inline portLONG SaveLocalPSR (void)
+static inline portLONG SaveLocalPSR( void )
 {
     portLONG flags = __get_PSR();
+
     __disable_irq();
     return flags;
 }
 
-static inline void RestoreLocalPSR (portLONG newMask)
+static inline void RestoreLocalPSR( portLONG newMask )
 {
-    __asm__ __volatile__(
-    "mtcr   %0, psr \n"
-    :
-    :"r" (newMask)
-    :"memory"
-    );
+    __asm__ __volatile__ (
+        "mtcr   %0, psr \n"
+        :
+        : "r" ( newMask )
+        : "memory"
+        );
 }
 
 extern void vPortEnterCritical( void );
 extern void vPortExitCritical( void );
-extern __attribute__((naked)) void cpu_yeild(void);
+extern __attribute__( ( naked ) ) void cpu_yeild( void );
 
-#define portDISABLE_INTERRUPTS()                vPortDisableInterrupt()
-#define portENABLE_INTERRUPTS()                 vPortEnableInterrupt()
-#define portENTER_CRITICAL()                    vPortEnterCritical()
-#define portEXIT_CRITICAL()                     vPortExitCritical()
-#define portSET_INTERRUPT_MASK_FROM_ISR()       SaveLocalPSR()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(a)    RestoreLocalPSR(a)
+#define portDISABLE_INTERRUPTS()                  vPortDisableInterrupt()
+#define portENABLE_INTERRUPTS()                   vPortEnableInterrupt()
+#define portENTER_CRITICAL()                      vPortEnterCritical()
+#define portEXIT_CRITICAL()                       vPortExitCritical()
+#define portSET_INTERRUPT_MASK_FROM_ISR()         SaveLocalPSR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( a )    RestoreLocalPSR( a )
 
-#define portNOP()                   asm("nop")
+#define portNOP()                                 asm ( "nop" )
 
 extern portLONG ulCriticalNesting;
 extern portLONG pendsvflag;
 
-#define portYIELD()                 if (ulCriticalNesting == 0) \
-                                    {   \
-                                        vPortYield();   \
-                                    }   \
-                                    else \
-                                    {   \
-                                        pendsvflag = 1; \
-                                    }   \
-                                    portNOP();portNOP()
+#define portYIELD()              \
+    if( ulCriticalNesting == 0 ) \
+    {                            \
+        vPortYield();            \
+    }                            \
+    else                         \
+    {                            \
+        pendsvflag = 1;          \
+    }                            \
+    portNOP(); portNOP()
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn))
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters ) __attribute__( ( noreturn ) )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 /*-----------------------------------------------------------*/
 
-#define portEND_SWITCHING_ISR( xSwitchRequired )    do {    \
-                                                            if( xSwitchRequired != pdFALSE )    \
-                                                            {   \
-                                                                portYIELD();    \
-                                                            }   \
-                                                    }while(0)
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+    do {                                         \
+        if( xSwitchRequired != pdFALSE )         \
+        {                                        \
+            portYIELD();                         \
+        }                                        \
+    } while( 0 )
 
-#define portYIELD_FROM_ISR( a )     vTaskSwitchContext()
+#define portYIELD_FROM_ISR( a )    vTaskSwitchContext()
 
 
 
diff --git a/portable/ThirdParty/GCC/ARC_EM_HS/portmacro.h b/portable/ThirdParty/GCC/ARC_EM_HS/portmacro.h
index 49b15b099..e5004146b 100644
--- a/portable/ThirdParty/GCC/ARC_EM_HS/portmacro.h
+++ b/portable/ThirdParty/GCC/ARC_EM_HS/portmacro.h
@@ -78,15 +78,15 @@
     #define false    0          /* false */
 #endif /* false */
 
-typedef portSTACK_TYPE     StackType_t;
-typedef long               BaseType_t;
-typedef unsigned long      UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
 #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t       TickType_t;
-    #define portMAX_DELAY          ( TickType_t ) 0xffff
-#elif ( configTICK_TYPE_WIDTH_IN_BITS  == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t             TickType_t;
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+    typedef uint32_t     TickType_t;
     #define portMAX_DELAY    ( TickType_t ) 0xffffffffUL
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
diff --git a/portable/ThirdParty/GCC/ARC_v1/port.c b/portable/ThirdParty/GCC/ARC_v1/port.c
index 4dbdc7e60..728cd6fac 100644
--- a/portable/ThirdParty/GCC/ARC_v1/port.c
+++ b/portable/ThirdParty/GCC/ARC_v1/port.c
@@ -212,7 +212,7 @@ void vPortEndTask( void )
         volatile StackType_t * pxTopOfStack; /*< Points to the location of the last item placed on the tasks stack.  THIS MUST BE THE FIRST MEMBER OF THE TCB STRUCT. */
 
         #if ( portUSING_MPU_WRAPPERS == 1 )
-            xMPU_SETTINGS xMPUSettings;     /*< The MPU settings are defined as part of the port layer.  THIS MUST BE THE SECOND MEMBER OF THE TCB STRUCT. */
+            xMPU_SETTINGS xMPUSettings; /*< The MPU settings are defined as part of the port layer.  THIS MUST BE THE SECOND MEMBER OF THE TCB STRUCT. */
         #endif
 
         ListItem_t xStateListItem;                  /*< The list that the state list item of a task is reference from denotes the state of that task (Ready, Blocked, Suspended ). */
@@ -222,20 +222,20 @@ void vPortEndTask( void )
         char pcTaskName[ configMAX_TASK_NAME_LEN ]; /*< Descriptive name given to the task when created.  Facilitates debugging only. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
 
         #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) )
-            StackType_t * pxEndOfStack;     /*< Points to the highest valid address for the stack. */
+            StackType_t * pxEndOfStack; /*< Points to the highest valid address for the stack. */
         #endif
 
         #if ( portCRITICAL_NESTING_IN_TCB == 1 )
-            UBaseType_t uxCriticalNesting;  /*< Holds the critical section nesting depth for ports that do not maintain their own count in the port layer. */
+            UBaseType_t uxCriticalNesting; /*< Holds the critical section nesting depth for ports that do not maintain their own count in the port layer. */
         #endif
 
         #if ( configUSE_TRACE_FACILITY == 1 )
-            UBaseType_t uxTCBNumber;        /*< Stores a number that increments each time a TCB is created.  It allows debuggers to determine when a task has been deleted and then recreated. */
-            UBaseType_t uxTaskNumber;       /*< Stores a number specifically for use by third party trace code. */
+            UBaseType_t uxTCBNumber;  /*< Stores a number that increments each time a TCB is created.  It allows debuggers to determine when a task has been deleted and then recreated. */
+            UBaseType_t uxTaskNumber; /*< Stores a number specifically for use by third party trace code. */
         #endif
 
         #if ( configUSE_MUTEXES == 1 )
-            UBaseType_t uxBasePriority;     /*< The priority last assigned to the task - used by the priority inheritance mechanism. */
+            UBaseType_t uxBasePriority; /*< The priority last assigned to the task - used by the priority inheritance mechanism. */
             UBaseType_t uxMutexesHeld;
         #endif
 
@@ -248,7 +248,7 @@ void vPortEndTask( void )
         #endif
 
         #if ( configGENERATE_RUN_TIME_STATS == 1 )
-            uint32_t ulRunTimeCounter;      /*< Stores the amount of time the task has spent in the Running state. */
+            uint32_t ulRunTimeCounter; /*< Stores the amount of time the task has spent in the Running state. */
         #endif
 
         #if ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 )
diff --git a/portable/ThirdParty/GCC/ARC_v1/portmacro.h b/portable/ThirdParty/GCC/ARC_v1/portmacro.h
index 137cbc05d..cc67ad613 100644
--- a/portable/ThirdParty/GCC/ARC_v1/portmacro.h
+++ b/portable/ThirdParty/GCC/ARC_v1/portmacro.h
@@ -27,8 +27,8 @@
  */
 
 #ifndef PORTMACRO_H
-    #define PORTMACRO_H
-    #include "embARC.h"
+#define PORTMACRO_H
+#include "embARC.h"
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
@@ -37,9 +37,9 @@
 /* *INDENT-ON* */
 
 /* record stack high address for stack check */
-    #ifndef configRECORD_STACK_HIGH_ADDRESS
-        #define configRECORD_STACK_HIGH_ADDRESS    1
-    #endif
+#ifndef configRECORD_STACK_HIGH_ADDRESS
+    #define configRECORD_STACK_HIGH_ADDRESS    1
+#endif
 
 /*-----------------------------------------------------------
  * Port specific definitions.
@@ -52,78 +52,78 @@
  */
 
 /* Type definitions. */
-    #define portCHAR          char
-    #define portFLOAT         float
-    #define portDOUBLE        double
-    #define portLONG          long
-    #define portSHORT         short
-    #define portSTACK_TYPE    unsigned int
-    #define portBASE_TYPE     portLONG
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    unsigned int
+#define portBASE_TYPE     portLONG
 
-    #ifndef Asm
-        #define Asm           __asm__ volatile
-    #endif
+#ifndef Asm
+    #define Asm           __asm__ volatile
+#endif
 
 /*
  *  normal constants
  */
-    #ifndef NULL
-        #define NULL    0       /* invalid pointer */
-    #endif /* NULL */
+#ifndef NULL
+    #define NULL    0           /* invalid pointer */
+#endif /* NULL */
 
-    #ifndef true
-        #define true    1       /* true */
-    #endif /* true */
+#ifndef true
+    #define true    1           /* true */
+#endif /* true */
 
-    #ifndef false
-        #define false    0      /* false */
-    #endif /* false */
+#ifndef false
+    #define false    0          /* false */
+#endif /* false */
 
-    typedef portSTACK_TYPE     StackType_t;
-    typedef long               BaseType_t;
-    typedef unsigned long      UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
-    #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-        typedef uint16_t       TickType_t;
-        #define portMAX_DELAY          ( TickType_t ) 0xffff
-    #elif ( configTICK_TYPE_WIDTH_IN_BITS  == TICK_TYPE_WIDTH_32_BITS )
-        typedef uint32_t             TickType_t;
-        #define portMAX_DELAY    ( TickType_t ) 0xffffffffUL
-    #else
-        #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
-    #endif
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffffffffUL
+#else
+    #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+#endif
 
-    #define portNO_CRITICAL_NESTING    ( ( uint32_t ) 0 )
-    #define portSTACK_GROWTH           ( -1 )
-    #define portTICK_PERIOD_MS         ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-    #define portBYTE_ALIGNMENT         8
-    #define portNOP()               Asm( "nop_s" );
-    #define IPM_ENABLE_ALL             1
+#define portNO_CRITICAL_NESTING    ( ( uint32_t ) 0 )
+#define portSTACK_GROWTH           ( -1 )
+#define portTICK_PERIOD_MS         ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT         8
+#define portNOP()               Asm( "nop_s" );
+#define IPM_ENABLE_ALL             1
 
-    #define portYIELD_FROM_ISR()    vPortYieldFromIsr()
-    #define portYIELD()             vPortYield()
+#define portYIELD_FROM_ISR()    vPortYieldFromIsr()
+#define portYIELD()             vPortYield()
 
 /* Critical section management. */
-    #define portDISABLE_INTERRUPTS() \
-    {                                \
-        arc_lock();                  \
-    }                                \
+#define portDISABLE_INTERRUPTS() \
+    {                            \
+        arc_lock();              \
+    }                            \
 
-    #define portENABLE_INTERRUPTS() \
-    {                               \
-        arc_unlock();               \
-    }                               \
+#define portENABLE_INTERRUPTS() \
+    {                           \
+        arc_unlock();           \
+    }                           \
 
-    extern volatile unsigned int ulCriticalNesting;
+extern volatile unsigned int ulCriticalNesting;
 
-    #define portENTER_CRITICAL() \
+#define portENTER_CRITICAL()     \
     {                            \
         portDISABLE_INTERRUPTS() \
         ulCriticalNesting++;     \
     }
 
 
-    #define portEXIT_CRITICAL()                                \
+#define portEXIT_CRITICAL()                                    \
     {                                                          \
         if( ulCriticalNesting > portNO_CRITICAL_NESTING )      \
         {                                                      \
@@ -136,14 +136,14 @@
     }
 
 
-    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
-    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
-    #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS()              do {} while( 0 ) /* we use the timer */
-    #define portALT_GET_RUN_TIME_COUNTER_VALUE( dest )            ( dest = xTickCount )
+#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS()              do {} while( 0 )     /* we use the timer */
+#define portALT_GET_RUN_TIME_COUNTER_VALUE( dest )            ( dest = xTickCount )
 
-    void vPortYield( void );
-    void vPortYieldFromIsr( void );
+void vPortYield( void );
+void vPortYieldFromIsr( void );
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/ThirdParty/GCC/ARM_TFM/README.md b/portable/ThirdParty/GCC/ARM_TFM/README.md
index 310d21b9c..b1d49fd71 100644
--- a/portable/ThirdParty/GCC/ARM_TFM/README.md
+++ b/portable/ThirdParty/GCC/ARM_TFM/README.md
@@ -32,7 +32,7 @@ See the [link](https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/) to
 
 ### Build TF-M
 
-Please refer to this [link](https://tf-m-user-guide.trustedfirmware.org/docs/technical_references/instructions/tfm_build_instruction.html) to build the secure side.
+Please refer to this [link](https://developer.nordicsemi.com/nRF_Connect_SDK/doc/latest/tfm/building/tfm_build_instruction.html) to build the secure side.
 _**Note:** ```TFM_NS_MANAGE_NSID``` must be configured as "OFF" when building TF-M_.
 
 ## Build the Non-Secure Side
diff --git a/portable/ThirdParty/GCC/ARM_TFM/os_wrapper_freertos.c b/portable/ThirdParty/GCC/ARM_TFM/os_wrapper_freertos.c
index 4c634ddfa..8eb453930 100644
--- a/portable/ThirdParty/GCC/ARM_TFM/os_wrapper_freertos.c
+++ b/portable/ThirdParty/GCC/ARM_TFM/os_wrapper_freertos.c
@@ -34,58 +34,72 @@
 #include "semphr.h"
 #include "mpu_wrappers.h"
 
-#if( configSUPPORT_STATIC_ALLOCATION == 1 )
-    /*
-     * In the static allocation, the RAM is required to hold the semaphore's
-     * state.
-     */
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+/*
+ * In the static allocation, the RAM is required to hold the semaphore's
+ * state.
+ */
     StaticSemaphore_t xSecureMutexBuffer;
 #endif
 
 void * os_wrapper_mutex_create( void )
 {
-SemaphoreHandle_t xMutexHandle = NULL;
+    SemaphoreHandle_t xMutexHandle = NULL;
 
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-    xMutexHandle = xSemaphoreCreateMutex();
-#elif( configSUPPORT_STATIC_ALLOCATION == 1 )
-    xMutexHandle = xSemaphoreCreateMutexStatic( &xSecureMutexBuffer );
-#endif
+    #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+        xMutexHandle = xSemaphoreCreateMutex();
+    #elif ( configSUPPORT_STATIC_ALLOCATION == 1 )
+        xMutexHandle = xSemaphoreCreateMutexStatic( &xSecureMutexBuffer );
+    #endif
     return ( void * ) xMutexHandle;
 }
 /*-----------------------------------------------------------*/
 
-uint32_t os_wrapper_mutex_acquire( void * handle, uint32_t timeout )
+uint32_t os_wrapper_mutex_acquire( void * handle,
+                                   uint32_t timeout )
 {
-BaseType_t xRet;
+    BaseType_t xRet;
 
-    if( ! handle )
+    if( !handle )
+    {
         return OS_WRAPPER_ERROR;
+    }
 
     xRet = xSemaphoreTake( ( SemaphoreHandle_t ) handle,
                            ( timeout == OS_WRAPPER_WAIT_FOREVER ) ?
                            portMAX_DELAY : ( TickType_t ) timeout );
 
     if( xRet != pdPASS )
+    {
         return OS_WRAPPER_ERROR;
+    }
     else
+    {
         return OS_WRAPPER_SUCCESS;
+    }
 }
 /*-----------------------------------------------------------*/
 
 uint32_t os_wrapper_mutex_release( void * handle )
 {
-BaseType_t xRet;
+    BaseType_t xRet;
 
     if( !handle )
+    {
         return OS_WRAPPER_ERROR;
+    }
 
     xRet = xSemaphoreGive( ( SemaphoreHandle_t ) handle );
 
     if( xRet != pdPASS )
+    {
         return OS_WRAPPER_ERROR;
+    }
     else
+    {
         return OS_WRAPPER_SUCCESS;
+    }
 }
 /*-----------------------------------------------------------*/
 
diff --git a/portable/ThirdParty/GCC/ATmega/port.c b/portable/ThirdParty/GCC/ATmega/port.c
index b8f9546d7..fa71552b3 100644
--- a/portable/ThirdParty/GCC/ATmega/port.c
+++ b/portable/ThirdParty/GCC/ATmega/port.c
@@ -37,167 +37,168 @@
 #include "task.h"
 
 /*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the AVR port.
- *----------------------------------------------------------*/
+* Implementation of functions defined in portable.h for the AVR port.
+*----------------------------------------------------------*/
 
 /* Start tasks with interrupts enabled. */
-#define portFLAGS_INT_ENABLED           ( (StackType_t) 0x80 )
+#define portFLAGS_INT_ENABLED    ( ( StackType_t ) 0x80 )
 
-#if defined( portUSE_WDTO)
+#if defined( portUSE_WDTO )
     #warning "Watchdog Timer used for scheduler."
-    #define portSCHEDULER_ISR           WDT_vect
+    #define portSCHEDULER_ISR    WDT_vect
 
 #elif defined( portUSE_TIMER0 )
 /* Hardware constants for Timer0. */
     #warning "Timer0 used for scheduler."
-    #define portSCHEDULER_ISR           TIMER0_COMPA_vect
-    #define portCLEAR_COUNTER_ON_MATCH  ( (uint8_t) _BV(WGM01) )
-    #define portPRESCALE_1024           ( (uint8_t) (_BV(CS02)|_BV(CS00)) )
-    #define portCLOCK_PRESCALER         ( (uint32_t) 1024 )
-    #define portCOMPARE_MATCH_A_INTERRUPT_ENABLE    ( (uint8_t) _BV(OCIE0A) )
-    #define portOCRL                    OCR0A
-    #define portTCCRa                   TCCR0A
-    #define portTCCRb                   TCCR0B
-    #define portTIMSK                   TIMSK0
-    #define portTIFR                    TIFR0
+    #define portSCHEDULER_ISR                       TIMER0_COMPA_vect
+    #define portCLEAR_COUNTER_ON_MATCH              ( ( uint8_t ) _BV( WGM01 ) )
+    #define portPRESCALE_1024                       ( ( uint8_t ) ( _BV( CS02 ) | _BV( CS00 ) ) )
+    #define portCLOCK_PRESCALER                     ( ( uint32_t ) 1024 )
+    #define portCOMPARE_MATCH_A_INTERRUPT_ENABLE    ( ( uint8_t ) _BV( OCIE0A ) )
+    #define portOCRL                                OCR0A
+    #define portTCCRa                               TCCR0A
+    #define portTCCRb                               TCCR0B
+    #define portTIMSK                               TIMSK0
+    #define portTIFR                                TIFR0
 
-#else
+#else /* if defined( portUSE_WDTO ) */
     #error "No Timer defined for scheduler"
-#endif
+#endif /* if defined( portUSE_WDTO ) */
 
 /*-----------------------------------------------------------*/
 
 /* We require the address of the pxCurrentTCB variable, but don't want to know
-any details of its type. */
+ * any details of its type. */
 typedef void TCB_t;
 extern volatile TCB_t * volatile pxCurrentTCB;
 
 /*-----------------------------------------------------------*/
 
 /**
-    Enable the watchdog timer, configuring it for expire after
-    (value) timeout (which is a combination of the WDP0
-    through WDP3 bits).
+ *  Enable the watchdog timer, configuring it for expire after
+ *  (value) timeout (which is a combination of the WDP0
+ *  through WDP3 bits).
+ *
+ *  This function is derived from <avr/wdt.h> but enables only
+ *  the interrupt bit (WDIE), rather than the reset bit (WDE).
+ *
+ *  Can't find it documented but the WDT, once enabled,
+ *  rolls over and fires a new interrupt each time.
+ *
+ *  See also the symbolic constants WDTO_15MS et al.
+ *
+ *  Updated to match avr-libc 2.0.0
+ */
 
-    This function is derived from <avr/wdt.h> but enables only
-    the interrupt bit (WDIE), rather than the reset bit (WDE).
+#if defined( portUSE_WDTO )
 
-    Can't find it documented but the WDT, once enabled,
-    rolls over and fires a new interrupt each time.
-
-    See also the symbolic constants WDTO_15MS et al.
-
-    Updated to match avr-libc 2.0.0
-*/
-
-#if defined( portUSE_WDTO)
-
-static __inline__
-__attribute__ ((__always_inline__))
-void wdt_interrupt_enable (const uint8_t value)
-{
-    if (_SFR_IO_REG_P (_WD_CONTROL_REG))
+    static __inline__
+    __attribute__( ( __always_inline__ ) )
+    void wdt_interrupt_enable( const uint8_t value )
     {
-        __asm__ __volatile__ (
+        if( _SFR_IO_REG_P( _WD_CONTROL_REG ) )
+        {
+            __asm__ __volatile__ (
                 "in __tmp_reg__,__SREG__"   "\n\t"
-                "cli"                       "\n\t"
-                "wdr"                       "\n\t"
-                "out %0, %1"                "\n\t"
-                "out __SREG__,__tmp_reg__"  "\n\t"
-                "out %0, %2"                "\n\t"
+                                            "cli"                       "\n\t"
+                                                                        "wdr"                       "\n\t"
+                                                                                                    "out %0, %1"                "\n\t"
+                                                                                                                                "out __SREG__,__tmp_reg__"  "\n\t"
+                                                                                                                                                            "out %0, %2"                "\n\t"
                 : /* no outputs */
-                : "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)),
-                "r" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))),
-                "r" ((uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) |
-                        _BV(WDIF) | _BV(WDIE) | (value & 0x07)) )
+                : "I" ( _SFR_IO_ADDR( _WD_CONTROL_REG ) ),
+                "r" ( ( uint8_t ) ( _BV( _WD_CHANGE_BIT ) | _BV( WDE ) ) ),
+                "r" ( ( uint8_t ) ( ( value & 0x08 ? _WD_PS3_MASK : 0x00 ) |
+                                    _BV( WDIF ) | _BV( WDIE ) | ( value & 0x07 ) ) )
                 : "r0"
-        );
-    }
-    else
-    {
-        __asm__ __volatile__ (
+                );
+        }
+        else
+        {
+            __asm__ __volatile__ (
                 "in __tmp_reg__,__SREG__"   "\n\t"
-                "cli"                       "\n\t"
-                "wdr"                       "\n\t"
-                "sts %0, %1"                "\n\t"
-                "out __SREG__,__tmp_reg__"  "\n\t"
-                "sts %0, %2"                "\n\t"
+                                            "cli"                       "\n\t"
+                                                                        "wdr"                       "\n\t"
+                                                                                                    "sts %0, %1"                "\n\t"
+                                                                                                                                "out __SREG__,__tmp_reg__"  "\n\t"
+                                                                                                                                                            "sts %0, %2"                "\n\t"
                 : /* no outputs */
-                : "n" (_SFR_MEM_ADDR(_WD_CONTROL_REG)),
-                "r" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))),
-                "r" ((uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) |
-                        _BV(WDIF) | _BV(WDIE) | (value & 0x07)) )
+                : "n" ( _SFR_MEM_ADDR( _WD_CONTROL_REG ) ),
+                "r" ( ( uint8_t ) ( _BV( _WD_CHANGE_BIT ) | _BV( WDE ) ) ),
+                "r" ( ( uint8_t ) ( ( value & 0x08 ? _WD_PS3_MASK : 0x00 ) |
+                                    _BV( WDIF ) | _BV( WDIE ) | ( value & 0x07 ) ) )
                 : "r0"
-        );
+                );
+        }
     }
-}
-#endif
+#endif /* if defined( portUSE_WDTO ) */
 
 /*-----------------------------------------------------------*/
+
 /**
-    Enable the watchdog timer, configuring it for expire after
-    (value) timeout (which is a combination of the WDP0
-    through WDP3 bits).
+ *  Enable the watchdog timer, configuring it for expire after
+ *  (value) timeout (which is a combination of the WDP0
+ *  through WDP3 bits).
+ *
+ *  This function is derived from <avr/wdt.h> but enables both
+ *  the reset bit (WDE), and the interrupt bit (WDIE).
+ *
+ *  This will ensure that if the interrupt is not serviced
+ *  before the second timeout, the AVR will reset.
+ *
+ *  Servicing the interrupt automatically clears it,
+ *  and ensures the AVR does not reset.
+ *
+ *  Can't find it documented but the WDT, once enabled,
+ *  rolls over and fires a new interrupt each time.
+ *
+ *  See also the symbolic constants WDTO_15MS et al.
+ *
+ *  Updated to match avr-libc 2.0.0
+ */
 
-    This function is derived from <avr/wdt.h> but enables both
-    the reset bit (WDE), and the interrupt bit (WDIE).
+#if defined( portUSE_WDTO )
 
-    This will ensure that if the interrupt is not serviced
-    before the second timeout, the AVR will reset.
-
-    Servicing the interrupt automatically clears it,
-    and ensures the AVR does not reset.
-
-    Can't find it documented but the WDT, once enabled,
-    rolls over and fires a new interrupt each time.
-
-    See also the symbolic constants WDTO_15MS et al.
-
-    Updated to match avr-libc 2.0.0
-*/
-
-#if defined( portUSE_WDTO)
-
-static __inline__
-__attribute__ ((__always_inline__))
-void wdt_interrupt_reset_enable (const uint8_t value)
-{
-    if (_SFR_IO_REG_P (_WD_CONTROL_REG))
+    static __inline__
+    __attribute__( ( __always_inline__ ) )
+    void wdt_interrupt_reset_enable( const uint8_t value )
     {
-        __asm__ __volatile__ (
+        if( _SFR_IO_REG_P( _WD_CONTROL_REG ) )
+        {
+            __asm__ __volatile__ (
                 "in __tmp_reg__,__SREG__"   "\n\t"
-                "cli"                       "\n\t"
-                "wdr"                       "\n\t"
-                "out %0, %1"                "\n\t"
-                "out __SREG__,__tmp_reg__"  "\n\t"
-                "out %0, %2"                "\n\t"
+                                            "cli"                       "\n\t"
+                                                                        "wdr"                       "\n\t"
+                                                                                                    "out %0, %1"                "\n\t"
+                                                                                                                                "out __SREG__,__tmp_reg__"  "\n\t"
+                                                                                                                                                            "out %0, %2"                "\n\t"
                 : /* no outputs */
-                : "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)),
-                "r" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))),
-                "r" ((uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) |
-                        _BV(WDIF) | _BV(WDIE) | _BV(WDE) | (value & 0x07)) )
+                : "I" ( _SFR_IO_ADDR( _WD_CONTROL_REG ) ),
+                "r" ( ( uint8_t ) ( _BV( _WD_CHANGE_BIT ) | _BV( WDE ) ) ),
+                "r" ( ( uint8_t ) ( ( value & 0x08 ? _WD_PS3_MASK : 0x00 ) |
+                                    _BV( WDIF ) | _BV( WDIE ) | _BV( WDE ) | ( value & 0x07 ) ) )
                 : "r0"
-        );
-    }
-    else
-    {
-        __asm__ __volatile__ (
+                );
+        }
+        else
+        {
+            __asm__ __volatile__ (
                 "in __tmp_reg__,__SREG__"   "\n\t"
-                "cli"                       "\n\t"
-                "wdr"                       "\n\t"
-                "sts %0, %1"                "\n\t"
-                "out __SREG__,__tmp_reg__"  "\n\t"
-                "sts %0, %2"                "\n\t"
+                                            "cli"                       "\n\t"
+                                                                        "wdr"                       "\n\t"
+                                                                                                    "sts %0, %1"                "\n\t"
+                                                                                                                                "out __SREG__,__tmp_reg__"  "\n\t"
+                                                                                                                                                            "sts %0, %2"                "\n\t"
                 : /* no outputs */
-                : "n" (_SFR_MEM_ADDR(_WD_CONTROL_REG)),
-                "r" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))),
-                "r" ((uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) |
-                        _BV(WDIF) | _BV(WDIE) | _BV(WDE) | (value & 0x07)) )
+                : "n" ( _SFR_MEM_ADDR( _WD_CONTROL_REG ) ),
+                "r" ( ( uint8_t ) ( _BV( _WD_CHANGE_BIT ) | _BV( WDE ) ) ),
+                "r" ( ( uint8_t ) ( ( value & 0x08 ? _WD_PS3_MASK : 0x00 ) |
+                                    _BV( WDIF ) | _BV( WDIE ) | _BV( WDE ) | ( value & 0x07 ) ) )
                 : "r0"
-        );
+                );
+        }
     }
-}
-#endif
+#endif /* if defined( portUSE_WDTO ) */
 
 /*-----------------------------------------------------------*/
 
@@ -226,295 +227,295 @@ void wdt_interrupt_reset_enable (const uint8_t value)
  * The interrupts will have been disabled during the call to portSAVE_CONTEXT()
  * so we need not worry about reading/writing to the stack pointer.
  */
-#if defined(__AVR_3_BYTE_PC__) && defined(__AVR_HAVE_RAMPZ__)
+#if defined( __AVR_3_BYTE_PC__ ) && defined( __AVR_HAVE_RAMPZ__ )
 /* 3-Byte PC Save  with RAMPZ */
-#define portSAVE_CONTEXT()                                                              \
-        __asm__ __volatile__ (  "push   __tmp_reg__                             \n\t"   \
-                                "in     __tmp_reg__, __SREG__                   \n\t"   \
-                                "cli                                            \n\t"   \
-                                "push   __tmp_reg__                             \n\t"   \
-                                "in     __tmp_reg__, 0x3B                       \n\t"   \
-                                "push   __tmp_reg__                             \n\t"   \
-                                "in     __tmp_reg__, 0x3C                       \n\t"   \
-                                "push   __tmp_reg__                             \n\t"   \
-                                "push   __zero_reg__                            \n\t"   \
-                                "clr    __zero_reg__                            \n\t"   \
-                                "push   r2                                      \n\t"   \
-                                "push   r3                                      \n\t"   \
-                                "push   r4                                      \n\t"   \
-                                "push   r5                                      \n\t"   \
-                                "push   r6                                      \n\t"   \
-                                "push   r7                                      \n\t"   \
-                                "push   r8                                      \n\t"   \
-                                "push   r9                                      \n\t"   \
-                                "push   r10                                     \n\t"   \
-                                "push   r11                                     \n\t"   \
-                                "push   r12                                     \n\t"   \
-                                "push   r13                                     \n\t"   \
-                                "push   r14                                     \n\t"   \
-                                "push   r15                                     \n\t"   \
-                                "push   r16                                     \n\t"   \
-                                "push   r17                                     \n\t"   \
-                                "push   r18                                     \n\t"   \
-                                "push   r19                                     \n\t"   \
-                                "push   r20                                     \n\t"   \
-                                "push   r21                                     \n\t"   \
-                                "push   r22                                     \n\t"   \
-                                "push   r23                                     \n\t"   \
-                                "push   r24                                     \n\t"   \
-                                "push   r25                                     \n\t"   \
-                                "push   r26                                     \n\t"   \
-                                "push   r27                                     \n\t"   \
-                                "push   r28                                     \n\t"   \
-                                "push   r29                                     \n\t"   \
-                                "push   r30                                     \n\t"   \
-                                "push   r31                                     \n\t"   \
-                                "lds    r26, pxCurrentTCB                       \n\t"   \
-                                "lds    r27, pxCurrentTCB + 1                   \n\t"   \
-                                "in     __tmp_reg__, __SP_L__                   \n\t"   \
-                                "st     x+, __tmp_reg__                         \n\t"   \
-                                "in     __tmp_reg__, __SP_H__                   \n\t"   \
-                                "st     x+, __tmp_reg__                         \n\t"   \
-                             );
-#elif defined(__AVR_HAVE_RAMPZ__)
+    #define portSAVE_CONTEXT()                                                   \
+    __asm__ __volatile__ ( "push   __tmp_reg__                             \n\t" \
+                           "in     __tmp_reg__, __SREG__                   \n\t" \
+                           "cli                                            \n\t" \
+                           "push   __tmp_reg__                             \n\t" \
+                           "in     __tmp_reg__, 0x3B                       \n\t" \
+                           "push   __tmp_reg__                             \n\t" \
+                           "in     __tmp_reg__, 0x3C                       \n\t" \
+                           "push   __tmp_reg__                             \n\t" \
+                           "push   __zero_reg__                            \n\t" \
+                           "clr    __zero_reg__                            \n\t" \
+                           "push   r2                                      \n\t" \
+                           "push   r3                                      \n\t" \
+                           "push   r4                                      \n\t" \
+                           "push   r5                                      \n\t" \
+                           "push   r6                                      \n\t" \
+                           "push   r7                                      \n\t" \
+                           "push   r8                                      \n\t" \
+                           "push   r9                                      \n\t" \
+                           "push   r10                                     \n\t" \
+                           "push   r11                                     \n\t" \
+                           "push   r12                                     \n\t" \
+                           "push   r13                                     \n\t" \
+                           "push   r14                                     \n\t" \
+                           "push   r15                                     \n\t" \
+                           "push   r16                                     \n\t" \
+                           "push   r17                                     \n\t" \
+                           "push   r18                                     \n\t" \
+                           "push   r19                                     \n\t" \
+                           "push   r20                                     \n\t" \
+                           "push   r21                                     \n\t" \
+                           "push   r22                                     \n\t" \
+                           "push   r23                                     \n\t" \
+                           "push   r24                                     \n\t" \
+                           "push   r25                                     \n\t" \
+                           "push   r26                                     \n\t" \
+                           "push   r27                                     \n\t" \
+                           "push   r28                                     \n\t" \
+                           "push   r29                                     \n\t" \
+                           "push   r30                                     \n\t" \
+                           "push   r31                                     \n\t" \
+                           "lds    r26, pxCurrentTCB                       \n\t" \
+                           "lds    r27, pxCurrentTCB + 1                   \n\t" \
+                           "in     __tmp_reg__, __SP_L__                   \n\t" \
+                           "st     x+, __tmp_reg__                         \n\t" \
+                           "in     __tmp_reg__, __SP_H__                   \n\t" \
+                           "st     x+, __tmp_reg__                         \n\t" \
+                           );
+#elif defined( __AVR_HAVE_RAMPZ__ )
 /* 2-Byte PC Save  with RAMPZ */
-#define portSAVE_CONTEXT()                                                              \
-        __asm__ __volatile__ (  "push   __tmp_reg__                             \n\t"   \
-                                "in     __tmp_reg__, __SREG__                   \n\t"   \
-                                "cli                                            \n\t"   \
-                                "push   __tmp_reg__                             \n\t"   \
-                                "in     __tmp_reg__, 0x3B                       \n\t"   \
-                                "push   __tmp_reg__                             \n\t"   \
-                                "push   __zero_reg__                            \n\t"   \
-                                "clr    __zero_reg__                            \n\t"   \
-                                "push   r2                                      \n\t"   \
-                                "push   r3                                      \n\t"   \
-                                "push   r4                                      \n\t"   \
-                                "push   r5                                      \n\t"   \
-                                "push   r6                                      \n\t"   \
-                                "push   r7                                      \n\t"   \
-                                "push   r8                                      \n\t"   \
-                                "push   r9                                      \n\t"   \
-                                "push   r10                                     \n\t"   \
-                                "push   r11                                     \n\t"   \
-                                "push   r12                                     \n\t"   \
-                                "push   r13                                     \n\t"   \
-                                "push   r14                                     \n\t"   \
-                                "push   r15                                     \n\t"   \
-                                "push   r16                                     \n\t"   \
-                                "push   r17                                     \n\t"   \
-                                "push   r18                                     \n\t"   \
-                                "push   r19                                     \n\t"   \
-                                "push   r20                                     \n\t"   \
-                                "push   r21                                     \n\t"   \
-                                "push   r22                                     \n\t"   \
-                                "push   r23                                     \n\t"   \
-                                "push   r24                                     \n\t"   \
-                                "push   r25                                     \n\t"   \
-                                "push   r26                                     \n\t"   \
-                                "push   r27                                     \n\t"   \
-                                "push   r28                                     \n\t"   \
-                                "push   r29                                     \n\t"   \
-                                "push   r30                                     \n\t"   \
-                                "push   r31                                     \n\t"   \
-                                "lds    r26, pxCurrentTCB                       \n\t"   \
-                                "lds    r27, pxCurrentTCB + 1                   \n\t"   \
-                                "in     __tmp_reg__, __SP_L__                   \n\t"   \
-                                "st     x+, __tmp_reg__                         \n\t"   \
-                                "in     __tmp_reg__, __SP_H__                   \n\t"   \
-                                "st     x+, __tmp_reg__                         \n\t"   \
-                             );
-#else
+    #define portSAVE_CONTEXT()                                                   \
+    __asm__ __volatile__ ( "push   __tmp_reg__                             \n\t" \
+                           "in     __tmp_reg__, __SREG__                   \n\t" \
+                           "cli                                            \n\t" \
+                           "push   __tmp_reg__                             \n\t" \
+                           "in     __tmp_reg__, 0x3B                       \n\t" \
+                           "push   __tmp_reg__                             \n\t" \
+                           "push   __zero_reg__                            \n\t" \
+                           "clr    __zero_reg__                            \n\t" \
+                           "push   r2                                      \n\t" \
+                           "push   r3                                      \n\t" \
+                           "push   r4                                      \n\t" \
+                           "push   r5                                      \n\t" \
+                           "push   r6                                      \n\t" \
+                           "push   r7                                      \n\t" \
+                           "push   r8                                      \n\t" \
+                           "push   r9                                      \n\t" \
+                           "push   r10                                     \n\t" \
+                           "push   r11                                     \n\t" \
+                           "push   r12                                     \n\t" \
+                           "push   r13                                     \n\t" \
+                           "push   r14                                     \n\t" \
+                           "push   r15                                     \n\t" \
+                           "push   r16                                     \n\t" \
+                           "push   r17                                     \n\t" \
+                           "push   r18                                     \n\t" \
+                           "push   r19                                     \n\t" \
+                           "push   r20                                     \n\t" \
+                           "push   r21                                     \n\t" \
+                           "push   r22                                     \n\t" \
+                           "push   r23                                     \n\t" \
+                           "push   r24                                     \n\t" \
+                           "push   r25                                     \n\t" \
+                           "push   r26                                     \n\t" \
+                           "push   r27                                     \n\t" \
+                           "push   r28                                     \n\t" \
+                           "push   r29                                     \n\t" \
+                           "push   r30                                     \n\t" \
+                           "push   r31                                     \n\t" \
+                           "lds    r26, pxCurrentTCB                       \n\t" \
+                           "lds    r27, pxCurrentTCB + 1                   \n\t" \
+                           "in     __tmp_reg__, __SP_L__                   \n\t" \
+                           "st     x+, __tmp_reg__                         \n\t" \
+                           "in     __tmp_reg__, __SP_H__                   \n\t" \
+                           "st     x+, __tmp_reg__                         \n\t" \
+                           );
+#else /* if defined( __AVR_3_BYTE_PC__ ) && defined( __AVR_HAVE_RAMPZ__ ) */
 /* 2-Byte PC Save */
-#define portSAVE_CONTEXT()                                                              \
-        __asm__ __volatile__ (  "push   __tmp_reg__                             \n\t"   \
-                                "in     __tmp_reg__, __SREG__                   \n\t"   \
-                                "cli                                            \n\t"   \
-                                "push   __tmp_reg__                             \n\t"   \
-                                "push   __zero_reg__                            \n\t"   \
-                                "clr    __zero_reg__                            \n\t"   \
-                                "push   r2                                      \n\t"   \
-                                "push   r3                                      \n\t"   \
-                                "push   r4                                      \n\t"   \
-                                "push   r5                                      \n\t"   \
-                                "push   r6                                      \n\t"   \
-                                "push   r7                                      \n\t"   \
-                                "push   r8                                      \n\t"   \
-                                "push   r9                                      \n\t"   \
-                                "push   r10                                     \n\t"   \
-                                "push   r11                                     \n\t"   \
-                                "push   r12                                     \n\t"   \
-                                "push   r13                                     \n\t"   \
-                                "push   r14                                     \n\t"   \
-                                "push   r15                                     \n\t"   \
-                                "push   r16                                     \n\t"   \
-                                "push   r17                                     \n\t"   \
-                                "push   r18                                     \n\t"   \
-                                "push   r19                                     \n\t"   \
-                                "push   r20                                     \n\t"   \
-                                "push   r21                                     \n\t"   \
-                                "push   r22                                     \n\t"   \
-                                "push   r23                                     \n\t"   \
-                                "push   r24                                     \n\t"   \
-                                "push   r25                                     \n\t"   \
-                                "push   r26                                     \n\t"   \
-                                "push   r27                                     \n\t"   \
-                                "push   r28                                     \n\t"   \
-                                "push   r29                                     \n\t"   \
-                                "push   r30                                     \n\t"   \
-                                "push   r31                                     \n\t"   \
-                                "lds    r26, pxCurrentTCB                       \n\t"   \
-                                "lds    r27, pxCurrentTCB + 1                   \n\t"   \
-                                "in     __tmp_reg__, __SP_L__                   \n\t"   \
-                                "st     x+, __tmp_reg__                         \n\t"   \
-                                "in     __tmp_reg__, __SP_H__                   \n\t"   \
-                                "st     x+, __tmp_reg__                         \n\t"   \
-                             );
-#endif
+    #define portSAVE_CONTEXT()                                                   \
+    __asm__ __volatile__ ( "push   __tmp_reg__                             \n\t" \
+                           "in     __tmp_reg__, __SREG__                   \n\t" \
+                           "cli                                            \n\t" \
+                           "push   __tmp_reg__                             \n\t" \
+                           "push   __zero_reg__                            \n\t" \
+                           "clr    __zero_reg__                            \n\t" \
+                           "push   r2                                      \n\t" \
+                           "push   r3                                      \n\t" \
+                           "push   r4                                      \n\t" \
+                           "push   r5                                      \n\t" \
+                           "push   r6                                      \n\t" \
+                           "push   r7                                      \n\t" \
+                           "push   r8                                      \n\t" \
+                           "push   r9                                      \n\t" \
+                           "push   r10                                     \n\t" \
+                           "push   r11                                     \n\t" \
+                           "push   r12                                     \n\t" \
+                           "push   r13                                     \n\t" \
+                           "push   r14                                     \n\t" \
+                           "push   r15                                     \n\t" \
+                           "push   r16                                     \n\t" \
+                           "push   r17                                     \n\t" \
+                           "push   r18                                     \n\t" \
+                           "push   r19                                     \n\t" \
+                           "push   r20                                     \n\t" \
+                           "push   r21                                     \n\t" \
+                           "push   r22                                     \n\t" \
+                           "push   r23                                     \n\t" \
+                           "push   r24                                     \n\t" \
+                           "push   r25                                     \n\t" \
+                           "push   r26                                     \n\t" \
+                           "push   r27                                     \n\t" \
+                           "push   r28                                     \n\t" \
+                           "push   r29                                     \n\t" \
+                           "push   r30                                     \n\t" \
+                           "push   r31                                     \n\t" \
+                           "lds    r26, pxCurrentTCB                       \n\t" \
+                           "lds    r27, pxCurrentTCB + 1                   \n\t" \
+                           "in     __tmp_reg__, __SP_L__                   \n\t" \
+                           "st     x+, __tmp_reg__                         \n\t" \
+                           "in     __tmp_reg__, __SP_H__                   \n\t" \
+                           "st     x+, __tmp_reg__                         \n\t" \
+                           );
+#endif /* if defined( __AVR_3_BYTE_PC__ ) && defined( __AVR_HAVE_RAMPZ__ ) */
 
 /*
  * Opposite to portSAVE_CONTEXT().  Interrupts will have been disabled during
  * the context save so we can write to the stack pointer.
  */
-#if defined(__AVR_3_BYTE_PC__) && defined(__AVR_HAVE_RAMPZ__)
+#if defined( __AVR_3_BYTE_PC__ ) && defined( __AVR_HAVE_RAMPZ__ )
 /* 3-Byte PC Restore with RAMPZ */
-#define portRESTORE_CONTEXT()                                                           \
-        __asm__ __volatile__ (  "lds    r26, pxCurrentTCB                       \n\t"   \
-                                "lds    r27, pxCurrentTCB + 1                   \n\t"   \
-                                "ld     r28, x+                                 \n\t"   \
-                                "out    __SP_L__, r28                           \n\t"   \
-                                "ld     r29, x+                                 \n\t"   \
-                                "out    __SP_H__, r29                           \n\t"   \
-                                "pop    r31                                     \n\t"   \
-                                "pop    r30                                     \n\t"   \
-                                "pop    r29                                     \n\t"   \
-                                "pop    r28                                     \n\t"   \
-                                "pop    r27                                     \n\t"   \
-                                "pop    r26                                     \n\t"   \
-                                "pop    r25                                     \n\t"   \
-                                "pop    r24                                     \n\t"   \
-                                "pop    r23                                     \n\t"   \
-                                "pop    r22                                     \n\t"   \
-                                "pop    r21                                     \n\t"   \
-                                "pop    r20                                     \n\t"   \
-                                "pop    r19                                     \n\t"   \
-                                "pop    r18                                     \n\t"   \
-                                "pop    r17                                     \n\t"   \
-                                "pop    r16                                     \n\t"   \
-                                "pop    r15                                     \n\t"   \
-                                "pop    r14                                     \n\t"   \
-                                "pop    r13                                     \n\t"   \
-                                "pop    r12                                     \n\t"   \
-                                "pop    r11                                     \n\t"   \
-                                "pop    r10                                     \n\t"   \
-                                "pop    r9                                      \n\t"   \
-                                "pop    r8                                      \n\t"   \
-                                "pop    r7                                      \n\t"   \
-                                "pop    r6                                      \n\t"   \
-                                "pop    r5                                      \n\t"   \
-                                "pop    r4                                      \n\t"   \
-                                "pop    r3                                      \n\t"   \
-                                "pop    r2                                      \n\t"   \
-                                "pop    __zero_reg__                            \n\t"   \
-                                "pop    __tmp_reg__                             \n\t"   \
-                                "out    0x3C, __tmp_reg__                       \n\t"   \
-                                "pop    __tmp_reg__                             \n\t"   \
-                                "out    0x3B, __tmp_reg__                       \n\t"   \
-                                "pop    __tmp_reg__                             \n\t"   \
-                                "out    __SREG__, __tmp_reg__                   \n\t"   \
-                                "pop    __tmp_reg__                             \n\t"   \
-                             );
-#elif defined(__AVR_HAVE_RAMPZ__)
+    #define portRESTORE_CONTEXT()                                                \
+    __asm__ __volatile__ ( "lds    r26, pxCurrentTCB                       \n\t" \
+                           "lds    r27, pxCurrentTCB + 1                   \n\t" \
+                           "ld     r28, x+                                 \n\t" \
+                           "out    __SP_L__, r28                           \n\t" \
+                           "ld     r29, x+                                 \n\t" \
+                           "out    __SP_H__, r29                           \n\t" \
+                           "pop    r31                                     \n\t" \
+                           "pop    r30                                     \n\t" \
+                           "pop    r29                                     \n\t" \
+                           "pop    r28                                     \n\t" \
+                           "pop    r27                                     \n\t" \
+                           "pop    r26                                     \n\t" \
+                           "pop    r25                                     \n\t" \
+                           "pop    r24                                     \n\t" \
+                           "pop    r23                                     \n\t" \
+                           "pop    r22                                     \n\t" \
+                           "pop    r21                                     \n\t" \
+                           "pop    r20                                     \n\t" \
+                           "pop    r19                                     \n\t" \
+                           "pop    r18                                     \n\t" \
+                           "pop    r17                                     \n\t" \
+                           "pop    r16                                     \n\t" \
+                           "pop    r15                                     \n\t" \
+                           "pop    r14                                     \n\t" \
+                           "pop    r13                                     \n\t" \
+                           "pop    r12                                     \n\t" \
+                           "pop    r11                                     \n\t" \
+                           "pop    r10                                     \n\t" \
+                           "pop    r9                                      \n\t" \
+                           "pop    r8                                      \n\t" \
+                           "pop    r7                                      \n\t" \
+                           "pop    r6                                      \n\t" \
+                           "pop    r5                                      \n\t" \
+                           "pop    r4                                      \n\t" \
+                           "pop    r3                                      \n\t" \
+                           "pop    r2                                      \n\t" \
+                           "pop    __zero_reg__                            \n\t" \
+                           "pop    __tmp_reg__                             \n\t" \
+                           "out    0x3C, __tmp_reg__                       \n\t" \
+                           "pop    __tmp_reg__                             \n\t" \
+                           "out    0x3B, __tmp_reg__                       \n\t" \
+                           "pop    __tmp_reg__                             \n\t" \
+                           "out    __SREG__, __tmp_reg__                   \n\t" \
+                           "pop    __tmp_reg__                             \n\t" \
+                           );
+#elif defined( __AVR_HAVE_RAMPZ__ )
 /* 2-Byte PC Restore with RAMPZ */
-#define portRESTORE_CONTEXT()                                                           \
-        __asm__ __volatile__ (  "lds    r26, pxCurrentTCB                       \n\t"   \
-                                "lds    r27, pxCurrentTCB + 1                   \n\t"   \
-                                "ld     r28, x+                                 \n\t"   \
-                                "out    __SP_L__, r28                           \n\t"   \
-                                "ld     r29, x+                                 \n\t"   \
-                                "out    __SP_H__, r29                           \n\t"   \
-                                "pop    r31                                     \n\t"   \
-                                "pop    r30                                     \n\t"   \
-                                "pop    r29                                     \n\t"   \
-                                "pop    r28                                     \n\t"   \
-                                "pop    r27                                     \n\t"   \
-                                "pop    r26                                     \n\t"   \
-                                "pop    r25                                     \n\t"   \
-                                "pop    r24                                     \n\t"   \
-                                "pop    r23                                     \n\t"   \
-                                "pop    r22                                     \n\t"   \
-                                "pop    r21                                     \n\t"   \
-                                "pop    r20                                     \n\t"   \
-                                "pop    r19                                     \n\t"   \
-                                "pop    r18                                     \n\t"   \
-                                "pop    r17                                     \n\t"   \
-                                "pop    r16                                     \n\t"   \
-                                "pop    r15                                     \n\t"   \
-                                "pop    r14                                     \n\t"   \
-                                "pop    r13                                     \n\t"   \
-                                "pop    r12                                     \n\t"   \
-                                "pop    r11                                     \n\t"   \
-                                "pop    r10                                     \n\t"   \
-                                "pop    r9                                      \n\t"   \
-                                "pop    r8                                      \n\t"   \
-                                "pop    r7                                      \n\t"   \
-                                "pop    r6                                      \n\t"   \
-                                "pop    r5                                      \n\t"   \
-                                "pop    r4                                      \n\t"   \
-                                "pop    r3                                      \n\t"   \
-                                "pop    r2                                      \n\t"   \
-                                "pop    __zero_reg__                            \n\t"   \
-                                "pop    __tmp_reg__                             \n\t"   \
-                                "out    0x3B, __tmp_reg__                       \n\t"   \
-                                "pop    __tmp_reg__                             \n\t"   \
-                                "out    __SREG__, __tmp_reg__                   \n\t"   \
-                                "pop    __tmp_reg__                             \n\t"   \
-                             );
-#else
+    #define portRESTORE_CONTEXT()                                                \
+    __asm__ __volatile__ ( "lds    r26, pxCurrentTCB                       \n\t" \
+                           "lds    r27, pxCurrentTCB + 1                   \n\t" \
+                           "ld     r28, x+                                 \n\t" \
+                           "out    __SP_L__, r28                           \n\t" \
+                           "ld     r29, x+                                 \n\t" \
+                           "out    __SP_H__, r29                           \n\t" \
+                           "pop    r31                                     \n\t" \
+                           "pop    r30                                     \n\t" \
+                           "pop    r29                                     \n\t" \
+                           "pop    r28                                     \n\t" \
+                           "pop    r27                                     \n\t" \
+                           "pop    r26                                     \n\t" \
+                           "pop    r25                                     \n\t" \
+                           "pop    r24                                     \n\t" \
+                           "pop    r23                                     \n\t" \
+                           "pop    r22                                     \n\t" \
+                           "pop    r21                                     \n\t" \
+                           "pop    r20                                     \n\t" \
+                           "pop    r19                                     \n\t" \
+                           "pop    r18                                     \n\t" \
+                           "pop    r17                                     \n\t" \
+                           "pop    r16                                     \n\t" \
+                           "pop    r15                                     \n\t" \
+                           "pop    r14                                     \n\t" \
+                           "pop    r13                                     \n\t" \
+                           "pop    r12                                     \n\t" \
+                           "pop    r11                                     \n\t" \
+                           "pop    r10                                     \n\t" \
+                           "pop    r9                                      \n\t" \
+                           "pop    r8                                      \n\t" \
+                           "pop    r7                                      \n\t" \
+                           "pop    r6                                      \n\t" \
+                           "pop    r5                                      \n\t" \
+                           "pop    r4                                      \n\t" \
+                           "pop    r3                                      \n\t" \
+                           "pop    r2                                      \n\t" \
+                           "pop    __zero_reg__                            \n\t" \
+                           "pop    __tmp_reg__                             \n\t" \
+                           "out    0x3B, __tmp_reg__                       \n\t" \
+                           "pop    __tmp_reg__                             \n\t" \
+                           "out    __SREG__, __tmp_reg__                   \n\t" \
+                           "pop    __tmp_reg__                             \n\t" \
+                           );
+#else /* if defined( __AVR_3_BYTE_PC__ ) && defined( __AVR_HAVE_RAMPZ__ ) */
 /* 2-Byte PC Restore */
-#define portRESTORE_CONTEXT()                                                           \
-        __asm__ __volatile__ (  "lds    r26, pxCurrentTCB                       \n\t"   \
-                                "lds    r27, pxCurrentTCB + 1                   \n\t"   \
-                                "ld     r28, x+                                 \n\t"   \
-                                "out    __SP_L__, r28                           \n\t"   \
-                                "ld     r29, x+                                 \n\t"   \
-                                "out    __SP_H__, r29                           \n\t"   \
-                                "pop    r31                                     \n\t"   \
-                                "pop    r30                                     \n\t"   \
-                                "pop    r29                                     \n\t"   \
-                                "pop    r28                                     \n\t"   \
-                                "pop    r27                                     \n\t"   \
-                                "pop    r26                                     \n\t"   \
-                                "pop    r25                                     \n\t"   \
-                                "pop    r24                                     \n\t"   \
-                                "pop    r23                                     \n\t"   \
-                                "pop    r22                                     \n\t"   \
-                                "pop    r21                                     \n\t"   \
-                                "pop    r20                                     \n\t"   \
-                                "pop    r19                                     \n\t"   \
-                                "pop    r18                                     \n\t"   \
-                                "pop    r17                                     \n\t"   \
-                                "pop    r16                                     \n\t"   \
-                                "pop    r15                                     \n\t"   \
-                                "pop    r14                                     \n\t"   \
-                                "pop    r13                                     \n\t"   \
-                                "pop    r12                                     \n\t"   \
-                                "pop    r11                                     \n\t"   \
-                                "pop    r10                                     \n\t"   \
-                                "pop    r9                                      \n\t"   \
-                                "pop    r8                                      \n\t"   \
-                                "pop    r7                                      \n\t"   \
-                                "pop    r6                                      \n\t"   \
-                                "pop    r5                                      \n\t"   \
-                                "pop    r4                                      \n\t"   \
-                                "pop    r3                                      \n\t"   \
-                                "pop    r2                                      \n\t"   \
-                                "pop    __zero_reg__                            \n\t"   \
-                                "pop    __tmp_reg__                             \n\t"   \
-                                "out    __SREG__, __tmp_reg__                   \n\t"   \
-                                "pop    __tmp_reg__                             \n\t"   \
-                             );
-#endif
+    #define portRESTORE_CONTEXT()                                                \
+    __asm__ __volatile__ ( "lds    r26, pxCurrentTCB                       \n\t" \
+                           "lds    r27, pxCurrentTCB + 1                   \n\t" \
+                           "ld     r28, x+                                 \n\t" \
+                           "out    __SP_L__, r28                           \n\t" \
+                           "ld     r29, x+                                 \n\t" \
+                           "out    __SP_H__, r29                           \n\t" \
+                           "pop    r31                                     \n\t" \
+                           "pop    r30                                     \n\t" \
+                           "pop    r29                                     \n\t" \
+                           "pop    r28                                     \n\t" \
+                           "pop    r27                                     \n\t" \
+                           "pop    r26                                     \n\t" \
+                           "pop    r25                                     \n\t" \
+                           "pop    r24                                     \n\t" \
+                           "pop    r23                                     \n\t" \
+                           "pop    r22                                     \n\t" \
+                           "pop    r21                                     \n\t" \
+                           "pop    r20                                     \n\t" \
+                           "pop    r19                                     \n\t" \
+                           "pop    r18                                     \n\t" \
+                           "pop    r17                                     \n\t" \
+                           "pop    r16                                     \n\t" \
+                           "pop    r15                                     \n\t" \
+                           "pop    r14                                     \n\t" \
+                           "pop    r13                                     \n\t" \
+                           "pop    r12                                     \n\t" \
+                           "pop    r11                                     \n\t" \
+                           "pop    r10                                     \n\t" \
+                           "pop    r9                                      \n\t" \
+                           "pop    r8                                      \n\t" \
+                           "pop    r7                                      \n\t" \
+                           "pop    r6                                      \n\t" \
+                           "pop    r5                                      \n\t" \
+                           "pop    r4                                      \n\t" \
+                           "pop    r3                                      \n\t" \
+                           "pop    r2                                      \n\t" \
+                           "pop    __zero_reg__                            \n\t" \
+                           "pop    __tmp_reg__                             \n\t" \
+                           "out    __SREG__, __tmp_reg__                   \n\t" \
+                           "pop    __tmp_reg__                             \n\t" \
+                           );
+#endif /* if defined( __AVR_3_BYTE_PC__ ) && defined( __AVR_HAVE_RAMPZ__ ) */
 /*-----------------------------------------------------------*/
 
 /*
@@ -526,14 +527,17 @@ static void prvSetupTimerInterrupt( void );
 /*
  * See header file for description.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
-uint16_t usAddress;
+    uint16_t usAddress;
+
     /* Simulate how the stack would look after a call to vPortYield() generated by
-    the compiler. */
+     * the compiler. */
 
     /* The start of the task code will be popped off the stack last, so place
-    it on first. */
+     * it on first. */
     usAddress = ( uint16_t ) pxCode;
     *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
     pxTopOfStack--;
@@ -542,48 +546,51 @@ uint16_t usAddress;
     *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
     pxTopOfStack--;
 
-#if defined(__AVR_3_BYTE_PC__)
-    /* The AVR ATmega2560/ATmega2561 have 256KBytes of program memory and a 17-bit
-     * program counter. When a code address is stored on the stack, it takes 3 bytes
-     * instead of 2 for the other ATmega* chips.
-     *
-     * Store 0 as the top byte since we force all task routines to the bottom 128K
-     * of flash. We do this by using the .lowtext label in the linker script.
-     *
-     * In order to do this properly, we would need to get a full 3-byte pointer to
-     * pxCode. That requires a change to GCC. Not likely to happen any time soon.
-     */
-    *pxTopOfStack = 0;
-    pxTopOfStack--;
-#endif
+    #if defined( __AVR_3_BYTE_PC__ )
+
+        /* The AVR ATmega2560/ATmega2561 have 256KBytes of program memory and a 17-bit
+         * program counter. When a code address is stored on the stack, it takes 3 bytes
+         * instead of 2 for the other ATmega* chips.
+         *
+         * Store 0 as the top byte since we force all task routines to the bottom 128K
+         * of flash. We do this by using the .lowtext label in the linker script.
+         *
+         * In order to do this properly, we would need to get a full 3-byte pointer to
+         * pxCode. That requires a change to GCC. Not likely to happen any time soon.
+         */
+        *pxTopOfStack = 0;
+        pxTopOfStack--;
+    #endif
 
     /* Next simulate the stack as if after a call to portSAVE_CONTEXT().
-    portSAVE_CONTEXT places the flags on the stack immediately after r0
-    to ensure the interrupts get disabled as soon as possible, and so ensuring
-    the stack use is minimal should a context switch interrupt occur. */
-    *pxTopOfStack = ( StackType_t ) 0x00;    /* R0 */
+     *  portSAVE_CONTEXT places the flags on the stack immediately after r0
+     *  to ensure the interrupts get disabled as soon as possible, and so ensuring
+     *  the stack use is minimal should a context switch interrupt occur. */
+    *pxTopOfStack = ( StackType_t ) 0x00; /* R0 */
     pxTopOfStack--;
     *pxTopOfStack = portFLAGS_INT_ENABLED;
     pxTopOfStack--;
 
-#if defined(__AVR_3_BYTE_PC__)
-    /* If we have an ATmega256x, we are also saving the EIND register.
-     * We should default to 0.
-     */
-    *pxTopOfStack = ( StackType_t ) 0x00;    /* EIND */
-    pxTopOfStack--;
-#endif
+    #if defined( __AVR_3_BYTE_PC__ )
 
-#if defined(__AVR_HAVE_RAMPZ__)
-    /* We are saving the RAMPZ register.
-     * We should default to 0.
-     */
-    *pxTopOfStack = ( StackType_t ) 0x00;    /* RAMPZ */
-    pxTopOfStack--;
-#endif
+        /* If we have an ATmega256x, we are also saving the EIND register.
+         * We should default to 0.
+         */
+        *pxTopOfStack = ( StackType_t ) 0x00; /* EIND */
+        pxTopOfStack--;
+    #endif
+
+    #if defined( __AVR_HAVE_RAMPZ__ )
+
+        /* We are saving the RAMPZ register.
+         * We should default to 0.
+         */
+        *pxTopOfStack = ( StackType_t ) 0x00; /* RAMPZ */
+        pxTopOfStack--;
+    #endif
 
     /* Now the remaining registers. The compiler expects R1 to be 0. */
-    *pxTopOfStack = ( StackType_t ) 0x00;    /* R1 */
+    *pxTopOfStack = ( StackType_t ) 0x00; /* R1 */
 
     /* Leave R2 - R23 untouched */
     pxTopOfStack -= 23;
@@ -612,7 +619,7 @@ BaseType_t xPortStartScheduler( void )
     portRESTORE_CONTEXT();
 
     /* Simulate a function call end as generated by the compiler. We will now
-    jump to the start of the task the context of which we have just restored. */
+     * jump to the start of the task the context of which we have just restored. */
     __asm__ __volatile__ ( "ret" );
 
     /* Should not get here. */
@@ -630,7 +637,7 @@ void vPortEndScheduler( void )
  * Manual context switch. The first thing we do is save the registers so we
  * can use a naked attribute.
  */
-void vPortYield( void ) __attribute__ ( ( hot, flatten, naked ) );
+void vPortYield( void ) __attribute__( ( hot, flatten, naked ) );
 void vPortYield( void )
 {
     portSAVE_CONTEXT();
@@ -645,8 +652,8 @@ void vPortYield( void )
  * Manual context switch callable from ISRs. The first thing we do is save
  * the registers so we can use a naked attribute.
  */
-void vPortYieldFromISR(void) __attribute__ ( ( hot, flatten, naked ) );
-void vPortYieldFromISR(void)
+void vPortYieldFromISR( void ) __attribute__( ( hot, flatten, naked ) );
+void vPortYieldFromISR( void )
 {
     portSAVE_CONTEXT();
     vTaskSwitchContext();
@@ -662,105 +669,111 @@ void vPortYieldFromISR(void)
  * difference from vPortYield() is the tick count is incremented as the
  * call comes from the tick ISR.
  */
-void vPortYieldFromTick( void ) __attribute__ ( ( hot, flatten, naked ) );
+void vPortYieldFromTick( void ) __attribute__( ( hot, flatten, naked ) );
 void vPortYieldFromTick( void )
 {
     portSAVE_CONTEXT();
+
     if( xTaskIncrementTick() != pdFALSE )
     {
         vTaskSwitchContext();
     }
+
     portRESTORE_CONTEXT();
 
     __asm__ __volatile__ ( "ret" );
 }
 /*-----------------------------------------------------------*/
 
-#if defined(portUSE_WDTO)
+#if defined( portUSE_WDTO )
+
 /*
  * Setup WDT to generate a tick interrupt.
  */
-void prvSetupTimerInterrupt( void )
-{
-    /* reset watchdog */
-    wdt_reset();
+    void prvSetupTimerInterrupt( void )
+    {
+        /* reset watchdog */
+        wdt_reset();
 
-    /* set up WDT Interrupt (rather than the WDT Reset). */
-    wdt_interrupt_enable( portUSE_WDTO );
-}
+        /* set up WDT Interrupt (rather than the WDT Reset). */
+        wdt_interrupt_enable( portUSE_WDTO );
+    }
+
+#elif defined( portUSE_TIMER0 )
 
-#elif defined (portUSE_TIMER0)
 /*
  * Setup Timer0 compare match A to generate a tick interrupt.
  */
-static void prvSetupTimerInterrupt( void )
-{
-uint32_t ulCompareMatch;
-uint8_t ucLowByte;
+    static void prvSetupTimerInterrupt( void )
+    {
+        uint32_t ulCompareMatch;
+        uint8_t ucLowByte;
 
-    /* Using 8bit Timer0 to generate the tick. Correct fuses must be
-    selected for the configCPU_CLOCK_HZ clock.*/
+        /* Using 8bit Timer0 to generate the tick. Correct fuses must be
+         * selected for the configCPU_CLOCK_HZ clock.*/
 
-    ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
+        ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
 
-    /* We only have 8 bits so have to scale 1024 to get our required tick rate. */
-    ulCompareMatch /= portCLOCK_PRESCALER;
+        /* We only have 8 bits so have to scale 1024 to get our required tick rate. */
+        ulCompareMatch /= portCLOCK_PRESCALER;
 
-    /* Adjust for correct value. */
-    ulCompareMatch -= ( uint32_t ) 1;
+        /* Adjust for correct value. */
+        ulCompareMatch -= ( uint32_t ) 1;
 
-    /* Setup compare match value for compare match A. Interrupts are disabled
-    before this is called so we need not worry here. */
-    ucLowByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff );
-    portOCRL = ucLowByte;
+        /* Setup compare match value for compare match A. Interrupts are disabled
+         * before this is called so we need not worry here. */
+        ucLowByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff );
+        portOCRL = ucLowByte;
 
-    /* Setup clock source and compare match behaviour. */
-    portTCCRa = portCLEAR_COUNTER_ON_MATCH;
-    portTCCRb = portPRESCALE_1024;
+        /* Setup clock source and compare match behaviour. */
+        portTCCRa = portCLEAR_COUNTER_ON_MATCH;
+        portTCCRb = portPRESCALE_1024;
 
 
-    /* Enable the interrupt - this is okay as interrupt are currently globally disabled. */
-    ucLowByte = portTIMSK;
-    ucLowByte |= portCOMPARE_MATCH_A_INTERRUPT_ENABLE;
-    portTIMSK = ucLowByte;
-}
+        /* Enable the interrupt - this is okay as interrupt are currently globally disabled. */
+        ucLowByte = portTIMSK;
+        ucLowByte |= portCOMPARE_MATCH_A_INTERRUPT_ENABLE;
+        portTIMSK = ucLowByte;
+    }
 
-#endif
+#endif /* if defined( portUSE_WDTO ) */
 
 /*-----------------------------------------------------------*/
 
 #if configUSE_PREEMPTION == 1
 
-    /*
-     * Tick ISR for preemptive scheduler. We can use a naked attribute as
-     * the context is saved at the start of vPortYieldFromTick(). The tick
-     * count is incremented after the context is saved.
-     *
-     * use ISR_NOBLOCK where there is an important timer running, that should preempt the scheduler.
-     *
-     */
-    ISR(portSCHEDULER_ISR, ISR_NAKED) __attribute__ ((hot, flatten));
+/*
+ * Tick ISR for preemptive scheduler. We can use a naked attribute as
+ * the context is saved at the start of vPortYieldFromTick(). The tick
+ * count is incremented after the context is saved.
+ *
+ * use ISR_NOBLOCK where there is an important timer running, that should preempt the scheduler.
+ *
+ */
+    ISR( portSCHEDULER_ISR, ISR_NAKED ) __attribute__( ( hot, flatten ) );
+
 /*  ISR(portSCHEDULER_ISR, ISR_NAKED ISR_NOBLOCK) __attribute__ ((hot, flatten));
  */
-    ISR(portSCHEDULER_ISR)
+    ISR( portSCHEDULER_ISR )
     {
         vPortYieldFromTick();
         __asm__ __volatile__ ( "reti" );
     }
-#else
+#else /* if configUSE_PREEMPTION == 1 */
+
+/*
+ * Tick ISR for the cooperative scheduler. All this does is increment the
+ * tick count. We don't need to switch context, this can only be done by
+ * manual calls to taskYIELD();
+ *
+ * use ISR_NOBLOCK where there is an important timer running, that should preempt the scheduler.
+ */
+    ISR( portSCHEDULER_ISR ) __attribute__( ( hot, flatten ) );
 
-    /*
-     * Tick ISR for the cooperative scheduler. All this does is increment the
-     * tick count. We don't need to switch context, this can only be done by
-     * manual calls to taskYIELD();
-     *
-     * use ISR_NOBLOCK where there is an important timer running, that should preempt the scheduler.
-     */
-    ISR(portSCHEDULER_ISR) __attribute__ ((hot, flatten));
 /*  ISR(portSCHEDULER_ISR, ISR_NOBLOCK) __attribute__ ((hot, flatten));
  */
-    ISR(portSCHEDULER_ISR)
+    ISR( portSCHEDULER_ISR )
     {
         xTaskIncrementTick();
     }
-#endif
+#endif /* if configUSE_PREEMPTION == 1 */
diff --git a/portable/ThirdParty/GCC/ATmega/portmacro.h b/portable/ThirdParty/GCC/ATmega/portmacro.h
index e48ddb219..7f8205497 100644
--- a/portable/ThirdParty/GCC/ATmega/portmacro.h
+++ b/portable/ThirdParty/GCC/ATmega/portmacro.h
@@ -24,7 +24,7 @@
  * https://www.FreeRTOS.org
  * https://github.com/FreeRTOS
  *
-*/
+ */
 
 #ifndef PORTMACRO_H
 #define PORTMACRO_H
@@ -48,23 +48,23 @@
 #include <avr/wdt.h>
 
 /* Type definitions. */
-#define portCHAR                    char
-#define portFLOAT                   float
-#define portDOUBLE                  double
-#define portLONG                    long
-#define portSHORT                   int
+#define portCHAR                 char
+#define portFLOAT                float
+#define portDOUBLE               double
+#define portLONG                 long
+#define portSHORT                int
 
 #define portPOINTER_SIZE_TYPE    uint16_t
 
-typedef uint8_t                     StackType_t;
-typedef int8_t                      BaseType_t;
-typedef uint8_t                     UBaseType_t;
+typedef uint8_t        StackType_t;
+typedef int8_t         BaseType_t;
+typedef uint8_t        UBaseType_t;
 
 #if configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS
-    typedef uint16_t                TickType_t;
-    #define portMAX_DELAY           ( TickType_t ) 0xffff
-#elif ( configTICK_TYPE_WIDTH_IN_BITS  == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t             TickType_t;
+    typedef uint16_t   TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+    typedef uint32_t   TickType_t;
     #define portMAX_DELAY    ( TickType_t ) 0xffffffffUL
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -73,23 +73,25 @@ typedef uint8_t                     UBaseType_t;
 
 /* Critical section management. */
 
-#define portENTER_CRITICAL()        __asm__ __volatile__ (                          \
-                                        "in __tmp_reg__, __SREG__"        "\n\t"    \
-                                        "cli"                             "\n\t"    \
-                                        "push __tmp_reg__"                "\n\t"    \
-                                        ::: "memory"                                \
-                                        )
+#define portENTER_CRITICAL()                                                                                         \
+    __asm__ __volatile__ (                                                                                           \
+        "in __tmp_reg__, __SREG__"        "\n\t"                                                                     \
+                                          "cli"                             "\n\t"                                   \
+                                                                            "push __tmp_reg__"                "\n\t" \
+        ::: "memory"                                                                                                 \
+        )
 
 
-#define portEXIT_CRITICAL()         __asm__ __volatile__ (                          \
-                                        "pop __tmp_reg__"                 "\n\t"    \
-                                        "out __SREG__, __tmp_reg__"       "\n\t"    \
-                                        ::: "memory"                                \
-                                        )
+#define portEXIT_CRITICAL()                                                        \
+    __asm__ __volatile__ (                                                         \
+        "pop __tmp_reg__"                 "\n\t"                                   \
+                                          "out __SREG__, __tmp_reg__"       "\n\t" \
+        ::: "memory"                                                               \
+        )
 
 
-#define portDISABLE_INTERRUPTS()    __asm__ __volatile__ ( "cli" ::: "memory")
-#define portENABLE_INTERRUPTS()     __asm__ __volatile__ ( "sei" ::: "memory")
+#define portDISABLE_INTERRUPTS()    __asm__ __volatile__ ( "cli" ::: "memory" )
+#define portENABLE_INTERRUPTS()     __asm__ __volatile__ ( "sei" ::: "memory" )
 /*-----------------------------------------------------------*/
 
 /* Architecture specifics. */
@@ -98,27 +100,27 @@ typedef uint8_t                     UBaseType_t;
  * Prefer to use the enhanced Watchdog Timer, but also Timer0 is ok.
  */
 
-#if defined(WDIE) && defined(WDIF)              /* If Enhanced WDT with interrupt capability is available */
+#if defined( WDIE ) && defined( WDIF ) /* If Enhanced WDT with interrupt capability is available */
 
-#define portUSE_WDTO                WDTO_15MS   /* use the Watchdog Timer for xTaskIncrementTick */
+    #define portUSE_WDTO    WDTO_15MS  /* use the Watchdog Timer for xTaskIncrementTick */
 
 /* Watchdog period options:         WDTO_15MS
-                                    WDTO_30MS
-                                    WDTO_60MS
-                                    WDTO_120MS
-                                    WDTO_250MS
-                                    WDTO_500MS
-                                    WDTO_1S
-                                    WDTO_2S
-*/
+ *                                  WDTO_30MS
+ *                                  WDTO_60MS
+ *                                  WDTO_120MS
+ *                                  WDTO_250MS
+ *                                  WDTO_500MS
+ *                                  WDTO_1S
+ *                                  WDTO_2S
+ */
 
 #else
 
-#define portUSE_TIMER0                          /* use the 8-bit Timer0 for xTaskIncrementTick */
+    #define portUSE_TIMER0    /* use the 8-bit Timer0 for xTaskIncrementTick */
 
 #endif
 
-#define portSTACK_GROWTH            ( -1 )
+#define portSTACK_GROWTH    ( -1 )
 
 /* Timing for the scheduler.
  * Watchdog Timer is 128kHz nominal,
@@ -126,35 +128,35 @@ typedef uint8_t                     UBaseType_t;
  * from data sheet.
  */
 #if defined( portUSE_WDTO )
-#define portTICK_PERIOD_MS          ( (TickType_t) _BV( portUSE_WDTO + 4 ) )
+    #define portTICK_PERIOD_MS    ( ( TickType_t ) _BV( portUSE_WDTO + 4 ) )
 #else
-#define portTICK_PERIOD_MS          ( (TickType_t) 1000 / configTICK_RATE_HZ )
+    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
 #endif
 
-#define portBYTE_ALIGNMENT          1
-#define portNOP()                   __asm__ __volatile__ ( "nop" );
+#define portBYTE_ALIGNMENT        1
+#define portNOP()    __asm__ __volatile__ ( "nop" );
 /*-----------------------------------------------------------*/
 
 /* Kernel utilities. */
-extern void vPortYield( void )      __attribute__ ( ( naked ) );
-#define portYIELD()                 vPortYield()
+extern void vPortYield( void )      __attribute__( ( naked ) );
+#define portYIELD()             vPortYield()
 
-extern void vPortYieldFromISR( void )   __attribute__ ( ( naked ) );
-#define portYIELD_FROM_ISR()            vPortYieldFromISR()
+extern void vPortYieldFromISR( void )   __attribute__( ( naked ) );
+#define portYIELD_FROM_ISR()    vPortYieldFromISR()
 /*-----------------------------------------------------------*/
 
-#if defined(__AVR_3_BYTE_PC__)
+#if defined( __AVR_3_BYTE_PC__ )
 /* Task function macros as described on the FreeRTOS.org WEB site. */
 
 /* Add .lowtext tag from the avr linker script avr6.x for ATmega2560 and ATmega2561
  * to make sure functions are loaded in low memory.
  */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__ ((section (".lowtext")))
+    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters ) __attribute__( ( section( ".lowtext" ) ) )
 #else
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
 #endif
 
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )              void vFunction( void * pvParameters )
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/ThirdParty/GCC/Posix/port.c b/portable/ThirdParty/GCC/Posix/port.c
index a8cb25734..8ec819397 100644
--- a/portable/ThirdParty/GCC/Posix/port.c
+++ b/portable/ThirdParty/GCC/Posix/port.c
@@ -119,10 +119,10 @@ static void prvPortYieldFromISR( void );
 /*-----------------------------------------------------------*/
 
 static void prvFatalError( const char * pcCall,
-                           int iErrno ) __attribute__ ((__noreturn__));
+                           int iErrno ) __attribute__( ( __noreturn__ ) );
 
 void prvFatalError( const char * pcCall,
-                           int iErrno )
+                    int iErrno )
 {
     fprintf( stderr, "%s: %s\n", pcCall, strerror( iErrno ) );
     abort();
@@ -148,11 +148,11 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
      */
     thread = ( Thread_t * ) ( pxTopOfStack + 1 ) - 1;
     pxTopOfStack = ( StackType_t * ) thread - 1;
-    ulStackSize = ( size_t )( pxTopOfStack + 1 - pxEndOfStack ) * sizeof( *pxTopOfStack );
+    ulStackSize = ( size_t ) ( pxTopOfStack + 1 - pxEndOfStack ) * sizeof( *pxTopOfStack );
 
     #ifdef __APPLE__
-        pxEndOfStack = mach_vm_round_page ( pxEndOfStack );
-        ulStackSize = mach_vm_trunc_page ( ulStackSize );
+        pxEndOfStack = mach_vm_round_page( pxEndOfStack );
+        ulStackSize = mach_vm_trunc_page( ulStackSize );
     #endif
 
     thread->pxCode = pxCode;
@@ -161,6 +161,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
 
     pthread_attr_init( &xThreadAttributes );
     iRet = pthread_attr_setstack( &xThreadAttributes, pxEndOfStack, ulStackSize );
+
     if( iRet != 0 )
     {
         fprintf( stderr, "[WARN] pthread_attr_setstack failed with return value: %d. Default stack will be used.\n", iRet );
@@ -336,7 +337,7 @@ UBaseType_t xPortSetInterruptMask( void )
 {
     /* Interrupts are always disabled inside ISRs (signals
      * handlers). */
-    return ( UBaseType_t )0;
+    return ( UBaseType_t ) 0;
 }
 /*-----------------------------------------------------------*/
 
@@ -352,7 +353,7 @@ static uint64_t prvGetTimeNs( void )
 
     clock_gettime( CLOCK_MONOTONIC, &t );
 
-    return ( uint64_t )t.tv_sec * ( uint64_t )1000000000UL + ( uint64_t )t.tv_nsec;
+    return ( uint64_t ) t.tv_sec * ( uint64_t ) 1000000000UL + ( uint64_t ) t.tv_nsec;
 }
 
 static uint64_t prvStartTimeNs;
diff --git a/portable/ThirdParty/GCC/Posix/portmacro.h b/portable/ThirdParty/GCC/Posix/portmacro.h
index 5e57a050a..6d141f145 100644
--- a/portable/ThirdParty/GCC/Posix/portmacro.h
+++ b/portable/ThirdParty/GCC/Posix/portmacro.h
@@ -50,71 +50,72 @@
  */
 
 /* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  unsigned long
-#define portBASE_TYPE   long
-#define portPOINTER_SIZE_TYPE intptr_t
+#define portCHAR                 char
+#define portFLOAT                float
+#define portDOUBLE               double
+#define portLONG                 long
+#define portSHORT                short
+#define portSTACK_TYPE           unsigned long
+#define portBASE_TYPE            long
+#define portPOINTER_SIZE_TYPE    intptr_t
 
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
 
-typedef unsigned long TickType_t;
-#define portMAX_DELAY ( TickType_t ) ULONG_MAX
+typedef unsigned long    TickType_t;
+#define portMAX_DELAY              ( TickType_t ) ULONG_MAX
 
-#define portTICK_TYPE_IS_ATOMIC 1
+#define portTICK_TYPE_IS_ATOMIC    1
 
 /*-----------------------------------------------------------*/
 
 /* Architecture specifics. */
-#define portSTACK_GROWTH            ( -1 )
-#define portHAS_STACK_OVERFLOW_CHECKING ( 1 )
-#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portTICK_RATE_MICROSECONDS  ( ( TickType_t ) 1000000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT          8
+#define portSTACK_GROWTH                   ( -1 )
+#define portHAS_STACK_OVERFLOW_CHECKING    ( 1 )
+#define portTICK_PERIOD_MS                 ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portTICK_RATE_MICROSECONDS         ( ( TickType_t ) 1000000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT                 8
 /*-----------------------------------------------------------*/
 
 /* Scheduler utilities. */
 extern void vPortYield( void );
 
-#define portYIELD() vPortYield()
+#define portYIELD()                                 vPortYield()
 
-#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) vPortYield()
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portEND_SWITCHING_ISR( xSwitchRequired )    if( xSwitchRequired != pdFALSE ) vPortYield( )
+#define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
 /* Critical section management. */
 extern void vPortDisableInterrupts( void );
 extern void vPortEnableInterrupts( void );
-#define portSET_INTERRUPT_MASK()        ( vPortDisableInterrupts() )
-#define portCLEAR_INTERRUPT_MASK()      ( vPortEnableInterrupts() )
+#define portSET_INTERRUPT_MASK()      ( vPortDisableInterrupts() )
+#define portCLEAR_INTERRUPT_MASK()    ( vPortEnableInterrupts() )
 
 extern UBaseType_t xPortSetInterruptMask( void );
 extern void vPortClearInterruptMask( UBaseType_t xMask );
 
 extern void vPortEnterCritical( void );
 extern void vPortExitCritical( void );
-#define portSET_INTERRUPT_MASK_FROM_ISR()       xPortSetInterruptMask()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)    vPortClearInterruptMask(x)
-#define portDISABLE_INTERRUPTS()                portSET_INTERRUPT_MASK()
-#define portENABLE_INTERRUPTS()                 portCLEAR_INTERRUPT_MASK()
-#define portENTER_CRITICAL()                    vPortEnterCritical()
-#define portEXIT_CRITICAL()                     vPortExitCritical()
+#define portSET_INTERRUPT_MASK_FROM_ISR()         xPortSetInterruptMask()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vPortClearInterruptMask( x )
+#define portDISABLE_INTERRUPTS()                  portSET_INTERRUPT_MASK()
+#define portENABLE_INTERRUPTS()                   portCLEAR_INTERRUPT_MASK()
+#define portENTER_CRITICAL()                      vPortEnterCritical()
+#define portEXIT_CRITICAL()                       vPortExitCritical()
 
 /*-----------------------------------------------------------*/
 
-extern void vPortThreadDying( void *pxTaskToDelete, volatile BaseType_t *pxPendYield );
-extern void vPortCancelThread( void *pxTaskToDelete );
-#define portPRE_TASK_DELETE_HOOK( pvTaskToDelete, pxPendYield ) vPortThreadDying( ( pvTaskToDelete ), ( pxPendYield ) )
-#define portCLEAN_UP_TCB( pxTCB )   vPortCancelThread( pxTCB )
+extern void vPortThreadDying( void * pxTaskToDelete,
+                              volatile BaseType_t * pxPendYield );
+extern void vPortCancelThread( void * pxTaskToDelete );
+#define portPRE_TASK_DELETE_HOOK( pvTaskToDelete, pxPendYield )    vPortThreadDying( ( pvTaskToDelete ), ( pxPendYield ) )
+#define portCLEAN_UP_TCB( pxTCB )                                  vPortCancelThread( pxTCB )
 /*-----------------------------------------------------------*/
 
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__( ( noreturn ) )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )         void vFunction( void * pvParameters ) __attribute__( ( noreturn ) )
+#define portTASK_FUNCTION( vFunction, pvParameters )               void vFunction( void * pvParameters )
 /*-----------------------------------------------------------*/
 
 /*
@@ -125,11 +126,11 @@ extern void vPortCancelThread( void *pxTaskToDelete );
  * Thus, only a compilier barrier is needed to prevent the compiler
  * reordering.
  */
-#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+#define portMEMORY_BARRIER()                        __asm volatile ( "" ::: "memory" )
 
 extern uint32_t ulPortGetRunTime( void );
-#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() /* no-op */
-#define portGET_RUN_TIME_COUNTER_VALUE()         ulPortGetRunTime()
+#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS()    /* no-op */
+#define portGET_RUN_TIME_COUNTER_VALUE()            ulPortGetRunTime()
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/ThirdParty/GCC/Posix/utils/wait_for_event.c b/portable/ThirdParty/GCC/Posix/utils/wait_for_event.c
index 144eba6c8..ead6cdb07 100644
--- a/portable/ThirdParty/GCC/Posix/utils/wait_for_event.c
+++ b/portable/ThirdParty/GCC/Posix/utils/wait_for_event.c
@@ -77,10 +77,10 @@ bool event_wait_timed( struct event * ev,
 
     clock_gettime( CLOCK_REALTIME, &ts );
     ts.tv_sec += ms / 1000;
-    ts.tv_nsec += ((ms % 1000) * 1000000);
+    ts.tv_nsec += ( ( ms % 1000 ) * 1000000 );
     pthread_mutex_lock( &ev->mutex );
 
-    while( (ev->event_triggered == false) && (ret == 0) )
+    while( ( ev->event_triggered == false ) && ( ret == 0 ) )
     {
         ret = pthread_cond_timedwait( &ev->cond, &ev->mutex, &ts );
 
diff --git a/portable/ThirdParty/GCC/RP2040/README.md b/portable/ThirdParty/GCC/RP2040/README.md
index 7c4dbe23a..bd521d53f 100644
--- a/portable/ThirdParty/GCC/RP2040/README.md
+++ b/portable/ThirdParty/GCC/RP2040/README.md
@@ -11,23 +11,23 @@ more efficient to use the non SMP version in the main FreeRTOS-Kernel branch in
 
 ## Using this port
 
-You can copy [FreeRTOS-Kernel-import.cmake](FreeRTOS-Kernel-import.cmake) into your project, and
+You can copy [FreeRTOS_Kernel_import.cmake](FreeRTOS_Kernel_import.cmake) into your project, and
 add the following in your `CMakeLists.txt`:
 
 ```cmake
 include(FreeRTOS_Kernel_import.cmake)
 ```
 
-This will locate the FreeRTOS kernel if it is a direct sub-module of your project, or if you provide the 
+This will locate the FreeRTOS kernel if it is a direct sub-module of your project, or if you provide the
 `FREERTOS_KERNEL_PATH` variable in your environment or via `-DFREERTOS_KERNEL_PATH=/path/to/FreeRTOS-Kernel` on the CMake command line.
 
-**NOTE:** If you are using version 1.3.1 or older of the Raspberry Pi Pico SDK then this line must appear before the 
-`pico_sdk_init()` and will cause FreeRTOS to be included/required in all RP2040 targets in your project. After this SDK 
-version, you can include the FreeRTOS-Kernel support later in your CMake build (possibly in a subdirectory) and the 
+**NOTE:** If you are using version 1.3.1 or older of the Raspberry Pi Pico SDK then this line must appear before the
+`pico_sdk_init()` and will cause FreeRTOS to be included/required in all RP2040 targets in your project. After this SDK
+version, you can include the FreeRTOS-Kernel support later in your CMake build (possibly in a subdirectory) and the
 FreeRTOS-Kernel support will only apply to those targets which explicitly include FreeRTOS support.
 
-As an alternative to the `import` statement above, you can just add this directory directly via thw following (with 
-the same placement restrictions related to the Raspberry Pi Pico SDK version above): 
+As an alternative to the `import` statement above, you can just add this directory directly via thw following (with
+the same placement restrictions related to the Raspberry Pi Pico SDK version above):
 
 ```cmake
 add_subdirectory(path/to/this/directory FreeRTOS-Kernel)
diff --git a/portable/ThirdParty/GCC/RP2040/idle_task_static_memory.c b/portable/ThirdParty/GCC/RP2040/idle_task_static_memory.c
index 4d4b0ea1b..aaeec1881 100644
--- a/portable/ThirdParty/GCC/RP2040/idle_task_static_memory.c
+++ b/portable/ThirdParty/GCC/RP2040/idle_task_static_memory.c
@@ -28,25 +28,25 @@
 
 #include "FreeRTOS.h"
 
-void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer,
-                                    StackType_t **ppxIdleTaskStackBuffer,
-                                    uint32_t *pulIdleTaskStackSize )
+void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer,
+                                    StackType_t ** ppxIdleTaskStackBuffer,
+                                    uint32_t * pulIdleTaskStackSize )
 {
     /* If the buffers to be provided to the Idle task are declared inside this
-    function then they must be declared static - otherwise they will be allocated on
-    the stack and so not exists after this function exits. */
+     * function then they must be declared static - otherwise they will be allocated on
+     * the stack and so not exists after this function exits. */
     static StaticTask_t xIdleTaskTCB;
     static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ];
 
     /* Pass out a pointer to the StaticTask_t structure in which the Idle task's
-    state will be stored. */
+     * state will be stored. */
     *ppxIdleTaskTCBBuffer = &xIdleTaskTCB;
 
     /* Pass out the array that will be used as the Idle task's stack. */
     *ppxIdleTaskStackBuffer = uxIdleTaskStack;
 
     /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer.
-    Note that, as the array is necessarily of type StackType_t,
-    configMINIMAL_STACK_SIZE is specified in words, not bytes. */
+     * Note that, as the array is necessarily of type StackType_t,
+     * configMINIMAL_STACK_SIZE is specified in words, not bytes. */
     *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;
 }
diff --git a/portable/ThirdParty/GCC/RP2040/include/freertos_sdk_config.h b/portable/ThirdParty/GCC/RP2040/include/freertos_sdk_config.h
index 8bf5d0b1d..bf9fdca5e 100644
--- a/portable/ThirdParty/GCC/RP2040/include/freertos_sdk_config.h
+++ b/portable/ThirdParty/GCC/RP2040/include/freertos_sdk_config.h
@@ -33,41 +33,45 @@
     #include "FreeRTOSConfig.h"
     #include "rp2040_config.h"
     #ifndef PICO_USE_MALLOC_MUTEX
-        // malloc needs to be made thread safe
-        #define PICO_USE_MALLOC_MUTEX 1
+        /* malloc needs to be made thread safe */
+        #define PICO_USE_MALLOC_MUTEX    1
     #endif /* PICO_USE_MALLOC_MUTEX */
     #if ( configSUPPORT_PICO_SYNC_INTEROP == 1 )
-        // increase the amount of time it may reasonably take to wake us up
+        /* increase the amount of time it may reasonably take to wake us up */
         #ifndef PICO_TIME_SLEEP_OVERHEAD_ADJUST_US
-        #define PICO_TIME_SLEEP_OVERHEAD_ADJUST_US 150
+            #define PICO_TIME_SLEEP_OVERHEAD_ADJUST_US    150
         #endif
 
-        #define lock_owner_id_t uint32_t
-        extern uint32_t ulPortLockGetCurrentOwnerId(void);
-        #define lock_get_caller_owner_id() ulPortLockGetCurrentOwnerId()
-        #define LOCK_INVALID_OWNER_ID ((uint32_t)-1)
+        #define lock_owner_id_t                           uint32_t
+        extern uint32_t ulPortLockGetCurrentOwnerId( void );
+        #define lock_get_caller_owner_id()    ulPortLockGetCurrentOwnerId()
+        #define LOCK_INVALID_OWNER_ID                     ( ( uint32_t ) -1 )
 
         struct lock_core;
         #ifndef lock_internal_spin_unlock_with_wait
-        extern void vPortLockInternalSpinUnlockWithWait( struct lock_core *pxLock, uint32_t ulSave);
-        #define lock_internal_spin_unlock_with_wait(lock, save) vPortLockInternalSpinUnlockWithWait(lock, save)
+            extern void vPortLockInternalSpinUnlockWithWait( struct lock_core * pxLock,
+                                                             uint32_t ulSave );
+            #define lock_internal_spin_unlock_with_wait( lock, save )    vPortLockInternalSpinUnlockWithWait( lock, save )
         #endif
 
         #ifndef lock_internal_spin_unlock_with_notify
-        extern void vPortLockInternalSpinUnlockWithNotify( struct lock_core *pxLock, uint32_t save);
-        #define lock_internal_spin_unlock_with_notify(lock, save) vPortLockInternalSpinUnlockWithNotify(lock, save);
+            extern void vPortLockInternalSpinUnlockWithNotify( struct lock_core * pxLock,
+                                                               uint32_t save );
+            #define lock_internal_spin_unlock_with_notify( lock, save )    vPortLockInternalSpinUnlockWithNotify( lock, save );
         #endif
 
         #ifndef lock_internal_spin_unlock_with_best_effort_wait_or_timeout
-        extern bool xPortLockInternalSpinUnlockWithBestEffortWaitOrTimeout( struct lock_core *pxLock, uint32_t ulSave, absolute_time_t uxUntil);
-        #define lock_internal_spin_unlock_with_best_effort_wait_or_timeout(lock, save, until) \
-            xPortLockInternalSpinUnlockWithBestEffortWaitOrTimeout(lock, save, until)
+            extern bool xPortLockInternalSpinUnlockWithBestEffortWaitOrTimeout( struct lock_core * pxLock,
+                                                                                uint32_t ulSave,
+                                                                                absolute_time_t uxUntil );
+            #define lock_internal_spin_unlock_with_best_effort_wait_or_timeout( lock, save, until ) \
+    xPortLockInternalSpinUnlockWithBestEffortWaitOrTimeout( lock, save, until )
         #endif
     #endif /* configSUPPORT_PICO_SYNC_INTEROP */
 
     #if ( configSUPPORT_PICO_TIME_INTEROP == 1 )
-        extern void xPortSyncInternalYieldUntilBefore(absolute_time_t t);
-        #define sync_internal_yield_until_before(t) xPortSyncInternalYieldUntilBefore(t)
+        extern void xPortSyncInternalYieldUntilBefore( absolute_time_t t );
+        #define sync_internal_yield_until_before( t )    xPortSyncInternalYieldUntilBefore( t )
     #endif /* configSUPPORT_PICO_TIME_INTEROP */
 #endif /* __ASSEMBLER__ */
-#endif
+#endif /* ifndef FREERTOS_SDK_CONFIG_H */
diff --git a/portable/ThirdParty/GCC/RP2040/include/portmacro.h b/portable/ThirdParty/GCC/RP2040/include/portmacro.h
index 7880a9903..e1c483458 100644
--- a/portable/ThirdParty/GCC/RP2040/include/portmacro.h
+++ b/portable/ThirdParty/GCC/RP2040/include/portmacro.h
@@ -28,7 +28,7 @@
  */
 
 #ifndef PORTMACRO_H
-    #define PORTMACRO_H
+#define PORTMACRO_H
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
@@ -36,8 +36,8 @@
 #endif
 /* *INDENT-ON* */
 
-    #include "pico.h"
-    #include "hardware/sync.h"
+#include "pico.h"
+#include "hardware/sync.h"
 
 /*-----------------------------------------------------------
  * Port specific definitions.
@@ -50,210 +50,225 @@
  */
 
 /* Type definitions. */
-    #define portCHAR          char
-    #define portFLOAT         float
-    #define portDOUBLE        double
-    #define portLONG          long
-    #define portSHORT         short
-    #define portSTACK_TYPE    uint32_t
-    #define portBASE_TYPE     long
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
 
-    typedef portSTACK_TYPE    StackType_t;
-    typedef int32_t           BaseType_t;
-    typedef uint32_t          UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef int32_t          BaseType_t;
+typedef uint32_t         UBaseType_t;
 
-    #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-        typedef uint16_t     TickType_t;
-        #define portMAX_DELAY              ( TickType_t ) 0xffff
-    #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-        typedef uint32_t     TickType_t;
-        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
  * not need to be guarded with a critical section. */
-        #define portTICK_TYPE_IS_ATOMIC    1
-    #else
-        #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
-    #endif
+    #define portTICK_TYPE_IS_ATOMIC    1
+#else
+    #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+#endif
 /*-----------------------------------------------------------*/
 
 /* Architecture specifics. */
-    #define portSTACK_GROWTH      ( -1 )
-    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-    #define portBYTE_ALIGNMENT    8
-    #define portDONT_DISCARD      __attribute__( ( used ) )
-    /* We have to use PICO_DIVIDER_DISABLE_INTERRUPTS as the source of truth rathern than our config,
-     * as our FreeRTOSConfig.h header cannot be included by ASM code - which is what this affects in the SDK */
-    #define portUSE_DIVIDER_SAVE_RESTORE !PICO_DIVIDER_DISABLE_INTERRUPTS
-    #if portUSE_DIVIDER_SAVE_RESTORE
-    #define portSTACK_LIMIT_PADDING 4
-    #endif
+#define portSTACK_GROWTH                ( -1 )
+#define portTICK_PERIOD_MS              ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT              8
+#define portDONT_DISCARD                __attribute__( ( used ) )
+
+/* We have to use PICO_DIVIDER_DISABLE_INTERRUPTS as the source of truth rathern than our config,
+ * as our FreeRTOSConfig.h header cannot be included by ASM code - which is what this affects in the SDK */
+#define portUSE_DIVIDER_SAVE_RESTORE    !PICO_DIVIDER_DISABLE_INTERRUPTS
+#if portUSE_DIVIDER_SAVE_RESTORE
+    #define portSTACK_LIMIT_PADDING     4
+#endif
 
 /*-----------------------------------------------------------*/
 
 
 /* Scheduler utilities. */
-    extern void vPortYield( void );
-    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
-    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-    #define portYIELD()                                 vPortYield()
-    #define portEND_SWITCHING_ISR( xSwitchRequired )    if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
-    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+extern void vPortYield( void );
+#define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
+#define portYIELD()                                 vPortYield()
+#define portEND_SWITCHING_ISR( xSwitchRequired )    if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+#define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
 
 /*-----------------------------------------------------------*/
 
 /* Exception handlers */
-    #if (configUSE_DYNAMIC_EXCEPTION_HANDLERS == 0)
-        /* We only need to override the SDK's weak functions if we want to replace them at compile time */
-        #define vPortSVCHandler isr_svcall
-        #define xPortPendSVHandler isr_pendsv
-        #define xPortSysTickHandler isr_systick
-    #endif
+#if ( configUSE_DYNAMIC_EXCEPTION_HANDLERS == 0 )
+    /* We only need to override the SDK's weak functions if we want to replace them at compile time */
+    #define vPortSVCHandler        isr_svcall
+    #define xPortPendSVHandler     isr_pendsv
+    #define xPortSysTickHandler    isr_systick
+#endif
 
 /*-----------------------------------------------------------*/
 
 /* Multi-core */
-    #define portMAX_CORE_COUNT            2
+#define portMAX_CORE_COUNT    2
 
-    /* Check validity of number of cores specified in config */
-    #if ( configNUMBER_OF_CORES < 1 || portMAX_CORE_COUNT < configNUMBER_OF_CORES )
-        #error "Invalid number of cores specified in config!"
-    #endif
+/* Check validity of number of cores specified in config */
+#if ( configNUMBER_OF_CORES < 1 || portMAX_CORE_COUNT < configNUMBER_OF_CORES )
+    #error "Invalid number of cores specified in config!"
+#endif
 
-    #if ( configTICK_CORE < 0 || configTICK_CORE > configNUMBER_OF_CORES )
-        #error "Invalid tick core specified in config!"
-    #endif
-    /* FreeRTOS core id is always zero based, so always 0 if we're running on only one core */
-    #if configNUMBER_OF_CORES == portMAX_CORE_COUNT
-        #define portGET_CORE_ID() get_core_num()
-    #else
-        #define portGET_CORE_ID() 0
-    #endif
+#if ( configTICK_CORE < 0 || configTICK_CORE > configNUMBER_OF_CORES )
+    #error "Invalid tick core specified in config!"
+#endif
+/* FreeRTOS core id is always zero based, so always 0 if we're running on only one core */
+#if configNUMBER_OF_CORES == portMAX_CORE_COUNT
+    #define portGET_CORE_ID()    get_core_num()
+#else
+    #define portGET_CORE_ID()    0
+#endif
 
-    #define portCHECK_IF_IN_ISR() ({ \
-        uint32_t ulIPSR;                                                  \
-       __asm volatile ("mrs %0, IPSR" : "=r" (ulIPSR)::);             \
-       ((uint8_t)ulIPSR)>0;})
+#define portCHECK_IF_IN_ISR()                                 \
+    ( {                                                       \
+        uint32_t ulIPSR;                                      \
+        __asm volatile ( "mrs %0, IPSR" : "=r" ( ulIPSR )::); \
+        ( ( uint8_t ) ulIPSR ) > 0; } )
 
-    void vYieldCore(int xCoreID);
-    #define portYIELD_CORE(a) vYieldCore(a)
-    #define portRESTORE_INTERRUPTS(ulState) __asm volatile ("msr PRIMASK,%0"::"r" (ulState) : )
+void vYieldCore( int xCoreID );
+#define portYIELD_CORE( a )                  vYieldCore( a )
+#define portRESTORE_INTERRUPTS( ulState )    __asm volatile ( "msr PRIMASK,%0" ::"r" ( ulState ) : )
 
 /*-----------------------------------------------------------*/
 
 /* Critical nesting count management. */
-    extern UBaseType_t uxCriticalNestings[ configNUMBER_OF_CORES ];
-    #define portGET_CRITICAL_NESTING_COUNT()        ( uxCriticalNestings[ portGET_CORE_ID() ] )
-    #define portSET_CRITICAL_NESTING_COUNT( x )     ( uxCriticalNestings[ portGET_CORE_ID() ] = ( x ) )
-    #define portINCREMENT_CRITICAL_NESTING_COUNT()  ( uxCriticalNestings[ portGET_CORE_ID() ]++ )
-    #define portDECREMENT_CRITICAL_NESTING_COUNT()  ( uxCriticalNestings[ portGET_CORE_ID() ]-- )
+extern UBaseType_t uxCriticalNestings[ configNUMBER_OF_CORES ];
+#define portGET_CRITICAL_NESTING_COUNT()          ( uxCriticalNestings[ portGET_CORE_ID() ] )
+#define portSET_CRITICAL_NESTING_COUNT( x )       ( uxCriticalNestings[ portGET_CORE_ID() ] = ( x ) )
+#define portINCREMENT_CRITICAL_NESTING_COUNT()    ( uxCriticalNestings[ portGET_CORE_ID() ]++ )
+#define portDECREMENT_CRITICAL_NESTING_COUNT()    ( uxCriticalNestings[ portGET_CORE_ID() ]-- )
 
 /*-----------------------------------------------------------*/
 
 /* Critical section management. */
 
-    #define portSET_INTERRUPT_MASK()                     ({               \
-       uint32_t ulState;                                                  \
-       __asm volatile ("mrs %0, PRIMASK" : "=r" (ulState)::);             \
-       __asm volatile ( " cpsid i " ::: "memory" );                       \
-       ulState;})
+#define portSET_INTERRUPT_MASK()                                  \
+    ( {                                                           \
+        uint32_t ulState;                                         \
+        __asm volatile ( "mrs %0, PRIMASK" : "=r" ( ulState )::); \
+        __asm volatile ( " cpsid i " ::: "memory" );              \
+        ulState; } )
 
-    #define portCLEAR_INTERRUPT_MASK(ulState) __asm volatile ("msr PRIMASK,%0"::"r" (ulState) : )
+#define portCLEAR_INTERRUPT_MASK( ulState )    __asm volatile ( "msr PRIMASK,%0" ::"r" ( ulState ) : )
 
-    extern uint32_t ulSetInterruptMaskFromISR( void ) __attribute__( ( naked ) );
-    extern void vClearInterruptMaskFromISR( uint32_t ulMask )  __attribute__( ( naked ) );
-    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulSetInterruptMaskFromISR()
-    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vClearInterruptMaskFromISR( x )
+extern uint32_t ulSetInterruptMaskFromISR( void ) __attribute__( ( naked ) );
+extern void vClearInterruptMaskFromISR( uint32_t ulMask )  __attribute__( ( naked ) );
+#define portSET_INTERRUPT_MASK_FROM_ISR()         ulSetInterruptMaskFromISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vClearInterruptMaskFromISR( x )
 
-    #define portDISABLE_INTERRUPTS()                  __asm volatile ( " cpsid i " ::: "memory" )
+#define portDISABLE_INTERRUPTS()                  __asm volatile ( " cpsid i " ::: "memory" )
 
-    extern void vPortEnableInterrupts();
-    #define portENABLE_INTERRUPTS()                   vPortEnableInterrupts()
+extern void vPortEnableInterrupts();
+#define portENABLE_INTERRUPTS()                   vPortEnableInterrupts()
 
-    #if ( configNUMBER_OF_CORES == 1 )
-        extern void vPortEnterCritical( void );
-        extern void vPortExitCritical( void );
-        #define portENTER_CRITICAL()                      vPortEnterCritical()
-        #define portEXIT_CRITICAL()                       vPortExitCritical()
-    #else
-        extern void vTaskEnterCritical( void );
-        extern void vTaskExitCritical( void );
-        extern UBaseType_t vTaskEnterCriticalFromISR( void );
-        extern void vTaskExitCriticalFromISR( UBaseType_t uxSavedInterruptStatus );
-        #define portENTER_CRITICAL()                      vTaskEnterCritical()
-        #define portEXIT_CRITICAL()                       vTaskExitCritical()
-        #define portENTER_CRITICAL_FROM_ISR()             vTaskEnterCriticalFromISR()
-        #define portEXIT_CRITICAL_FROM_ISR( x )           vTaskExitCriticalFromISR( x )
-    #endif
+#if ( configNUMBER_OF_CORES == 1 )
+    extern void vPortEnterCritical( void );
+    extern void vPortExitCritical( void );
+    #define portENTER_CRITICAL()    vPortEnterCritical()
+    #define portEXIT_CRITICAL()     vPortExitCritical()
+#else
+    extern void vTaskEnterCritical( void );
+    extern void vTaskExitCritical( void );
+    extern UBaseType_t vTaskEnterCriticalFromISR( void );
+    extern void vTaskExitCriticalFromISR( UBaseType_t uxSavedInterruptStatus );
+    #define portENTER_CRITICAL()               vTaskEnterCritical()
+    #define portEXIT_CRITICAL()                vTaskExitCritical()
+    #define portENTER_CRITICAL_FROM_ISR()      vTaskEnterCriticalFromISR()
+    #define portEXIT_CRITICAL_FROM_ISR( x )    vTaskExitCriticalFromISR( x )
+#endif /* if ( configNUMBER_OF_CORES == 1 ) */
 
-	#define portRTOS_SPINLOCK_COUNT 2
+#define portRTOS_SPINLOCK_COUNT    2
 
-    /* Note this is a single method with uxAcquire parameter since we have
-     * static vars, the method is always called with a compile time constant for
-     * uxAcquire, and the compiler should dothe right thing! */
-    static inline void vPortRecursiveLock(uint32_t ulLockNum, spin_lock_t *pxSpinLock, BaseType_t uxAcquire) {
-        static uint8_t ucOwnedByCore[ portMAX_CORE_COUNT ];
-        static uint8_t ucRecursionCountByLock[ portRTOS_SPINLOCK_COUNT ];
-        configASSERT( ulLockNum < portRTOS_SPINLOCK_COUNT );
-        uint32_t ulCoreNum = get_core_num();
-        uint32_t ulLockBit = 1u << ulLockNum;
-        configASSERT(ulLockBit < 256u );
-        if( uxAcquire )
+/* Note this is a single method with uxAcquire parameter since we have
+ * static vars, the method is always called with a compile time constant for
+ * uxAcquire, and the compiler should dothe right thing! */
+static inline void vPortRecursiveLock( uint32_t ulLockNum,
+                                       spin_lock_t * pxSpinLock,
+                                       BaseType_t uxAcquire )
+{
+    static uint8_t ucOwnedByCore[ portMAX_CORE_COUNT ];
+    static uint8_t ucRecursionCountByLock[ portRTOS_SPINLOCK_COUNT ];
+
+    configASSERT( ulLockNum < portRTOS_SPINLOCK_COUNT );
+    uint32_t ulCoreNum = get_core_num();
+    uint32_t ulLockBit = 1u << ulLockNum;
+    configASSERT( ulLockBit < 256u );
+
+    if( uxAcquire )
+    {
+        if( __builtin_expect( !*pxSpinLock, 0 ) )
         {
-            if( __builtin_expect( !*pxSpinLock, 0 ) )
+            if( ucOwnedByCore[ ulCoreNum ] & ulLockBit )
             {
-                if( ucOwnedByCore[ulCoreNum] & ulLockBit )
-                {
-                    configASSERT(ucRecursionCountByLock[ulLockNum] != 255u );
-                    ucRecursionCountByLock[ulLockNum]++;
-                    return;
-                }
-                while ( __builtin_expect( !*pxSpinLock, 0 ) );
+                configASSERT( ucRecursionCountByLock[ ulLockNum ] != 255u );
+                ucRecursionCountByLock[ ulLockNum ]++;
+                return;
             }
-            __mem_fence_acquire();
-            configASSERT(ucRecursionCountByLock[ulLockNum] == 0 );
-            ucRecursionCountByLock[ulLockNum] = 1;
-            ucOwnedByCore[ulCoreNum] |= ulLockBit;
-        } else {
-            configASSERT((ucOwnedByCore[ulCoreNum] & ulLockBit) != 0 );
-            configASSERT(ucRecursionCountByLock[ulLockNum] != 0 );
-            if( !--ucRecursionCountByLock[ulLockNum] )
+
+            while( __builtin_expect( !*pxSpinLock, 0 ) )
             {
-                ucOwnedByCore[ulCoreNum] &= ~ulLockBit;
-                __mem_fence_release();
-                *pxSpinLock = 1;
             }
         }
-    }
 
-    #if ( configNUMBER_OF_CORES == 1 )
-        #define portGET_ISR_LOCK()
-        #define portRELEASE_ISR_LOCK()
-        #define portGET_TASK_LOCK()
-        #define portRELEASE_TASK_LOCK()
-    #else
-        #define portGET_ISR_LOCK()      vPortRecursiveLock(0, spin_lock_instance(configSMP_SPINLOCK_0), pdTRUE)
-        #define portRELEASE_ISR_LOCK()  vPortRecursiveLock(0, spin_lock_instance(configSMP_SPINLOCK_0), pdFALSE)
-        #define portGET_TASK_LOCK()     vPortRecursiveLock(1, spin_lock_instance(configSMP_SPINLOCK_1), pdTRUE)
-        #define portRELEASE_TASK_LOCK() vPortRecursiveLock(1, spin_lock_instance(configSMP_SPINLOCK_1), pdFALSE)
-    #endif
+        __mem_fence_acquire();
+        configASSERT( ucRecursionCountByLock[ ulLockNum ] == 0 );
+        ucRecursionCountByLock[ ulLockNum ] = 1;
+        ucOwnedByCore[ ulCoreNum ] |= ulLockBit;
+    }
+    else
+    {
+        configASSERT( ( ucOwnedByCore[ ulCoreNum ] & ulLockBit ) != 0 );
+        configASSERT( ucRecursionCountByLock[ ulLockNum ] != 0 );
+
+        if( !--ucRecursionCountByLock[ ulLockNum ] )
+        {
+            ucOwnedByCore[ ulCoreNum ] &= ~ulLockBit;
+            __mem_fence_release();
+            *pxSpinLock = 1;
+        }
+    }
+}
+
+#if ( configNUMBER_OF_CORES == 1 )
+    #define portGET_ISR_LOCK()
+    #define portRELEASE_ISR_LOCK()
+    #define portGET_TASK_LOCK()
+    #define portRELEASE_TASK_LOCK()
+#else
+    #define portGET_ISR_LOCK()         vPortRecursiveLock( 0, spin_lock_instance( configSMP_SPINLOCK_0 ), pdTRUE )
+    #define portRELEASE_ISR_LOCK()     vPortRecursiveLock( 0, spin_lock_instance( configSMP_SPINLOCK_0 ), pdFALSE )
+    #define portGET_TASK_LOCK()        vPortRecursiveLock( 1, spin_lock_instance( configSMP_SPINLOCK_1 ), pdTRUE )
+    #define portRELEASE_TASK_LOCK()    vPortRecursiveLock( 1, spin_lock_instance( configSMP_SPINLOCK_1 ), pdFALSE )
+#endif
 
 /*-----------------------------------------------------------*/
 
 /* Tickless idle/low power functionality. */
-    #ifndef portSUPPRESS_TICKS_AND_SLEEP
-        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
-        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
-    #endif
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+    extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+    #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
-    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
-    #define portNOP()
+#define portNOP()
 
-    #define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
+#define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/ThirdParty/GCC/RP2040/include/rp2040_config.h b/portable/ThirdParty/GCC/RP2040/include/rp2040_config.h
index 35c6f2463..a0f65c761 100644
--- a/portable/ThirdParty/GCC/RP2040/include/rp2040_config.h
+++ b/portable/ThirdParty/GCC/RP2040/include/rp2040_config.h
@@ -40,9 +40,9 @@
  */
 #ifndef configUSE_DYNAMIC_EXCEPTION_HANDLERS
     #if defined( PICO_NO_RAM_VECTOR_TABLE ) && ( PICO_NO_RAM_VECTOR_TABLE == 1 )
-        #define configUSE_DYNAMIC_EXCEPTION_HANDLERS 0
+        #define configUSE_DYNAMIC_EXCEPTION_HANDLERS    0
     #else
-        #define configUSE_DYNAMIC_EXCEPTION_HANDLERS 1
+        #define configUSE_DYNAMIC_EXCEPTION_HANDLERS    1
     #endif
 #endif
 
@@ -51,7 +51,7 @@
  */
 #ifndef configSUPPORT_PICO_SYNC_INTEROP
     #if LIB_PICO_SYNC
-        #define configSUPPORT_PICO_SYNC_INTEROP 1
+        #define configSUPPORT_PICO_SYNC_INTEROP    1
     #endif
 #endif
 
@@ -61,15 +61,16 @@
  */
 #ifndef configSUPPORT_PICO_TIME_INTEROP
     #if LIB_PICO_TIME
-        #define configSUPPORT_PICO_TIME_INTEROP 1
+        #define configSUPPORT_PICO_TIME_INTEROP    1
     #endif
 #endif
 
 #if ( configNUMBER_OF_CORES > 1 )
-    /* configTICK_CORE indicates which core should handle the SysTick
-     * interrupts */
+
+/* configTICK_CORE indicates which core should handle the SysTick
+ * interrupts */
     #ifndef configTICK_CORE
-        #define configTICK_CORE 0
+        #define configTICK_CORE    0
     #endif
 #endif
 
@@ -77,11 +78,11 @@
  * the spin lock numbers to be used are defined statically and defaulted here
  * to the values nominally set aside for RTOS by the SDK */
 #ifndef configSMP_SPINLOCK_0
-    #define configSMP_SPINLOCK_0 PICO_SPINLOCK_ID_OS1
+    #define configSMP_SPINLOCK_0    PICO_SPINLOCK_ID_OS1
 #endif
 
 #ifndef configSMP_SPINLOCK_1
-    #define configSMP_SPINLOCK_1 PICO_SPINLOCK_ID_OS2
+    #define configSMP_SPINLOCK_1    PICO_SPINLOCK_ID_OS2
 #endif
 
 /* *INDENT-OFF* */
@@ -90,4 +91,4 @@
 #endif
 /* *INDENT-ON* */
 
-#endif
+#endif /* ifndef RP2040_CONFIG_H */
diff --git a/portable/ThirdParty/GCC/RP2040/port.c b/portable/ThirdParty/GCC/RP2040/port.c
index bf0dcf4aa..aef32afba 100644
--- a/portable/ThirdParty/GCC/RP2040/port.c
+++ b/portable/ThirdParty/GCC/RP2040/port.c
@@ -28,8 +28,8 @@
  */
 
 /*----------------------------------------------------------------------
-* Implementation of functions defined in portable.h for the RP2040 port.
-*----------------------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the RP2040 port.
+ *----------------------------------------------------------------------*/
 
 #include "FreeRTOS.h"
 #include "task.h"
@@ -42,12 +42,12 @@
  * the non SMP FreeRTOS_Kernel is not linked with pico_multicore itself). We
  * use this flag to determine if we need multi-core functionality.
  */
-#if ( LIB_PICO_MULTICORE == 1)
+#if ( LIB_PICO_MULTICORE == 1 )
     #include "pico/multicore.h"
 #endif /* LIB_PICO_MULTICORE */
 
 /* TODO : consider to remove this macro. */
-#define portRUNNING_ON_BOTH_CORES ( configNUMBER_OF_CORES == portMAX_CORE_COUNT )
+#define portRUNNING_ON_BOTH_CORES             ( configNUMBER_OF_CORES == portMAX_CORE_COUNT )
 
 /* Constants required to manipulate the NVIC. */
 #define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )
@@ -118,7 +118,7 @@ static void prvTaskExitError( void );
 #if ( configNUMBER_OF_CORES == 1 )
     static UBaseType_t uxCriticalNesting;
 #else /* #if ( configNUMBER_OF_CORES == 1 ) */
-    UBaseType_t uxCriticalNestings[ configNUMBER_OF_CORES ] = { 0 };
+UBaseType_t uxCriticalNestings[ configNUMBER_OF_CORES ] = { 0 };
 #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
 
 /*-----------------------------------------------------------*/
@@ -129,7 +129,7 @@ static void prvTaskExitError( void );
     #include "event_groups.h"
     #if configSUPPORT_STATIC_ALLOCATION
         static StaticEventGroup_t xStaticEventGroup;
-        #define pEventGroup (&xStaticEventGroup)
+        #define pEventGroup    ( &xStaticEventGroup )
     #endif /* configSUPPORT_STATIC_ALLOCATION */
     static EventGroupHandle_t xEventGroup;
     #if ( portRUNNING_ON_BOTH_CORES == 0 )
@@ -166,15 +166,15 @@ static void prvTaskExitError( void );
 
 /*-----------------------------------------------------------*/
 
-#define INVALID_PRIMARY_CORE_NUM 0xffu
+#define INVALID_PRIMARY_CORE_NUM    0xffu
 /* The primary core number (the own which has the SysTick handler) */
 static uint8_t ucPrimaryCoreNum = INVALID_PRIMARY_CORE_NUM;
 
 /* Note: portIS_FREE_RTOS_CORE() also returns false until the scheduler is started */
 #if ( portRUNNING_ON_BOTH_CORES == 1 )
-    #define portIS_FREE_RTOS_CORE() (ucPrimaryCoreNum != INVALID_PRIMARY_CORE_NUM)
+    #define portIS_FREE_RTOS_CORE()    ( ucPrimaryCoreNum != INVALID_PRIMARY_CORE_NUM )
 #else
-    #define portIS_FREE_RTOS_CORE() (ucPrimaryCoreNum == get_core_num())
+    #define portIS_FREE_RTOS_CORE()    ( ucPrimaryCoreNum == get_core_num() )
 #endif
 
 /*
@@ -218,70 +218,70 @@ void vPortSVCHandler( void )
 
 void vPortStartFirstTask( void )
 {
-#if ( configNUMBER_OF_CORES == 1 )
-    __asm volatile (
-        "   .syntax unified             \n"
-        "   ldr  r2, pxCurrentTCBConst1 \n"/* Obtain location of pxCurrentTCB. */
-        "   ldr  r3, [r2]               \n"
-        "   ldr  r0, [r3]               \n"/* The first item in pxCurrentTCB is the task top of stack. */
-        "   adds r0, #32                \n"/* Discard everything up to r0. */
-        "   msr  psp, r0                \n"/* This is now the new top of stack to use in the task. */
-        "   movs r0, #2                 \n"/* Switch to the psp stack. */
-        "   msr  CONTROL, r0            \n"
-        "   isb                         \n"
-        "   pop  {r0-r5}                \n"/* Pop the registers that are saved automatically. */
-        "   mov  lr, r5                 \n"/* lr is now in r5. */
-        "   pop  {r3}                   \n"/* Return address is now in r3. */
-        "   pop  {r2}                   \n"/* Pop and discard XPSR. */
-        "   cpsie i                     \n"/* The first task has its context and interrupts can be enabled. */
-        "   bx   r3                     \n"/* Finally, jump to the user defined task code. */
-	"   .align 4                       \n"
-	"pxCurrentTCBConst1: .word pxCurrentTCB\n"
-    );
-#else
-    __asm volatile (
-        "    .syntax unified                    \n"
-        #if configRESET_STACK_POINTER
-            "   ldr  r0, =0xE000ED08            \n" /* Use the NVIC offset register to locate the stack. */
-            "   ldr r0, [r0]                    \n"
-            "   ldr r0, [r0]                    \n"
-            "   msr msp, r0                     \n" /* Set the msp back to the start of the stack. */
-        #endif /* configRESET_STACK_POINTER */
-        #if portRUNNING_ON_BOTH_CORES
-            "   adr r1, ulAsmLocals             \n"/* Get the location of the current TCB for the current core. */
-            "   ldmia r1!, {r2, r3}             \n"
-            "   ldr r2, [r2]                    \n"/* r2 = Core number */
-            "   lsls r2, #2                     \n"
-            "   ldr r3, [r3, r2]                \n"/* r3 = pxCurrentTCBs[get_core_num()] */
-        #else
-            "   ldr r3, =pxCurrentTCBs          \n"
-            "   ldr r3, [r3]                    \n" /* r3 = pxCurrentTCBs[0] */
-        #endif /* portRUNNING_ON_BOTH_CORES */
-        "    ldr  r0, [r3]                       \n"/* The first item in pxCurrentTCB is the task top of stack. */
-        "    adds r0, #32                        \n"/* Discard everything up to r0. */
-        "    msr  psp, r0                        \n"/* This is now the new top of stack to use in the task. */
-        "    movs r0, #2                         \n"/* Switch to the psp stack. */
-        "    msr  CONTROL, r0                    \n"
-        "    isb                                 \n"
-        "    pop  {r0-r5}                        \n"/* Pop the registers that are saved automatically. */
-        "    mov  lr, r5                         \n"/* lr is now in r5. */
-        "    pop  {r3}                           \n"/* Return address is now in r3. */
-        "    pop  {r2}                           \n"/* Pop and discard XPSR. */
-        "    cpsie i                             \n"/* The first task has its context and interrupts can be enabled. */
-        "    bx   r3                             \n"/* Finally, jump to the user defined task code. */
-        #if portRUNNING_ON_BOTH_CORES
-            "                                   \n"
-            "     .align 4                      \n"
-            "ulAsmLocals:                       \n"
-            "    .word 0xD0000000               \n"/* SIO */
-            "    .word pxCurrentTCBs            \n"
-        #endif /* portRUNNING_ON_BOTH_CORES */
-    );
-#endif
+    #if ( configNUMBER_OF_CORES == 1 )
+        __asm volatile (
+            "   .syntax unified             \n"
+            "   ldr  r2, pxCurrentTCBConst1 \n" /* Obtain location of pxCurrentTCB. */
+            "   ldr  r3, [r2]               \n"
+            "   ldr  r0, [r3]               \n" /* The first item in pxCurrentTCB is the task top of stack. */
+            "   adds r0, #32                \n" /* Discard everything up to r0. */
+            "   msr  psp, r0                \n" /* This is now the new top of stack to use in the task. */
+            "   movs r0, #2                 \n" /* Switch to the psp stack. */
+            "   msr  CONTROL, r0            \n"
+            "   isb                         \n"
+            "   pop  {r0-r5}                \n" /* Pop the registers that are saved automatically. */
+            "   mov  lr, r5                 \n" /* lr is now in r5. */
+            "   pop  {r3}                   \n" /* Return address is now in r3. */
+            "   pop  {r2}                   \n" /* Pop and discard XPSR. */
+            "   cpsie i                     \n" /* The first task has its context and interrupts can be enabled. */
+            "   bx   r3                     \n" /* Finally, jump to the user defined task code. */
+            "   .align 4                       \n"
+            "pxCurrentTCBConst1: .word pxCurrentTCB\n"
+            );
+    #else /* if ( configNUMBER_OF_CORES == 1 ) */
+        __asm volatile (
+            "    .syntax unified                    \n"
+            #if configRESET_STACK_POINTER
+                "   ldr  r0, =0xE000ED08            \n" /* Use the NVIC offset register to locate the stack. */
+                "   ldr r0, [r0]                    \n"
+                "   ldr r0, [r0]                    \n"
+                "   msr msp, r0                     \n" /* Set the msp back to the start of the stack. */
+            #endif /* configRESET_STACK_POINTER */
+            #if portRUNNING_ON_BOTH_CORES
+                "   adr r1, ulAsmLocals             \n" /* Get the location of the current TCB for the current core. */
+                "   ldmia r1!, {r2, r3}             \n"
+                "   ldr r2, [r2]                    \n" /* r2 = Core number */
+                "   lsls r2, #2                     \n"
+                "   ldr r3, [r3, r2]                \n" /* r3 = pxCurrentTCBs[get_core_num()] */
+            #else
+                "   ldr r3, =pxCurrentTCBs          \n"
+                "   ldr r3, [r3]                    \n"  /* r3 = pxCurrentTCBs[0] */
+            #endif /* portRUNNING_ON_BOTH_CORES */
+            "    ldr  r0, [r3]                       \n" /* The first item in pxCurrentTCB is the task top of stack. */
+            "    adds r0, #32                        \n" /* Discard everything up to r0. */
+            "    msr  psp, r0                        \n" /* This is now the new top of stack to use in the task. */
+            "    movs r0, #2                         \n" /* Switch to the psp stack. */
+            "    msr  CONTROL, r0                    \n"
+            "    isb                                 \n"
+            "    pop  {r0-r5}                        \n" /* Pop the registers that are saved automatically. */
+            "    mov  lr, r5                         \n" /* lr is now in r5. */
+            "    pop  {r3}                           \n" /* Return address is now in r3. */
+            "    pop  {r2}                           \n" /* Pop and discard XPSR. */
+            "    cpsie i                             \n" /* The first task has its context and interrupts can be enabled. */
+            "    bx   r3                             \n" /* Finally, jump to the user defined task code. */
+            #if portRUNNING_ON_BOTH_CORES
+                "                                   \n"
+                "     .align 4                      \n"
+                "ulAsmLocals:                       \n"
+                "    .word 0xD0000000               \n" /* SIO */
+                "    .word pxCurrentTCBs            \n"
+            #endif /* portRUNNING_ON_BOTH_CORES */
+            );
+    #endif /* if ( configNUMBER_OF_CORES == 1 ) */
 }
 /*-----------------------------------------------------------*/
 
-#if ( LIB_PICO_MULTICORE == 1 ) && ( configSUPPORT_PICO_SYNC_INTEROP == 1)
+#if ( LIB_PICO_MULTICORE == 1 ) && ( configSUPPORT_PICO_SYNC_INTEROP == 1 )
     static void prvFIFOInterruptHandler()
     {
         /* We must remove the contents (which we don't care about)
@@ -303,15 +303,16 @@ void vPortStartFirstTask( void )
             portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
         #endif /* portRUNNING_ON_BOTH_CORES */
     }
-#endif
+#endif /* if ( LIB_PICO_MULTICORE == 1 ) && ( configSUPPORT_PICO_SYNC_INTEROP == 1 ) */
 
 #if ( configNUMBER_OF_CORES > 1 )
-    /*
-     * See header file for description.
-     */
+
+/*
+ * See header file for description.
+ */
     static BaseType_t xPortStartSchedulerOnCore()
     {
-        if( ucPrimaryCoreNum == get_core_num())
+        if( ucPrimaryCoreNum == get_core_num() )
         {
             /* Start the timer that generates the tick ISR.  Interrupts are disabled
              * here already. */
@@ -363,9 +364,9 @@ void vPortStartFirstTask( void )
         }
     #endif
 
-    /*
-     * See header file for description.
-     */
+/*
+ * See header file for description.
+ */
     BaseType_t xPortStartScheduler( void )
     {
         configASSERT( ucPrimaryCoreNum == INVALID_PRIMARY_CORE_NUM );
@@ -376,7 +377,7 @@ void vPortStartFirstTask( void )
 
         #if portRUNNING_ON_BOTH_CORES
             ucPrimaryCoreNum = configTICK_CORE;
-            configASSERT( get_core_num() == 0) ; // we must be started on core 0
+            configASSERT( get_core_num() == 0 ); /* we must be started on core 0 */
             multicore_launch_core1( prvDisableInterruptsAndPortStartSchedulerOnCore );
         #else
             ucPrimaryCoreNum = get_core_num();
@@ -387,17 +388,18 @@ void vPortStartFirstTask( void )
         return 0;
     }
 
-#else
-    /*
-     * See header file for description.
-     */
+#else /* if ( configNUMBER_OF_CORES > 1 ) */
+
+/*
+ * See header file for description.
+ */
     BaseType_t xPortStartScheduler( void )
     {
         /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
         portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
         portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
 
-        #if (configUSE_DYNAMIC_EXCEPTION_HANDLERS == 1)
+        #if ( configUSE_DYNAMIC_EXCEPTION_HANDLERS == 1 )
             exception_set_exclusive_handler( PENDSV_EXCEPTION, xPortPendSVHandler );
             exception_set_exclusive_handler( SYSTICK_EXCEPTION, xPortSysTickHandler );
             exception_set_exclusive_handler( SVCALL_EXCEPTION, vPortSVCHandler );
@@ -411,8 +413,8 @@ void vPortStartFirstTask( void )
         uxCriticalNesting = 0;
 
         ucPrimaryCoreNum = get_core_num();
-        #if (LIB_PICO_MULTICORE == 1)
-            #if ( configSUPPORT_PICO_SYNC_INTEROP == 1)
+        #if ( LIB_PICO_MULTICORE == 1 )
+            #if ( configSUPPORT_PICO_SYNC_INTEROP == 1 )
                 multicore_fifo_clear_irq();
                 multicore_fifo_drain();
                 uint32_t irq_num = 15 + get_core_num();
@@ -437,7 +439,7 @@ void vPortStartFirstTask( void )
         /* Should not get here! */
         return 0;
     }
-#endif
+#endif /* if ( configNUMBER_OF_CORES > 1 ) */
 
 /*-----------------------------------------------------------*/
 
@@ -451,6 +453,7 @@ void vPortEndScheduler( void )
 void vPortYield( void )
 {
     #if ( configSUPPORT_PICO_SYNC_INTEROP == 1 )
+
         /* We are not in an ISR, and pxYieldSpinLock is always dealt with and
          * cleared when interrupts are re-enabled, so should be NULL */
         configASSERT( pxYieldSpinLock[ portGET_CORE_ID() ] == NULL );
@@ -483,6 +486,7 @@ void vPortYield( void )
     {
         configASSERT( uxCriticalNesting );
         uxCriticalNesting--;
+
         if( uxCriticalNesting == 0 )
         {
             portENABLE_INTERRUPTS();
@@ -494,11 +498,12 @@ void vPortEnableInterrupts( void )
 {
     #if ( configSUPPORT_PICO_SYNC_INTEROP == 1 )
         int xCoreID = ( int ) portGET_CORE_ID();
-        if( pxYieldSpinLock[xCoreID] )
+
+        if( pxYieldSpinLock[ xCoreID ] )
         {
-            spin_lock_t* const pxTmpLock = pxYieldSpinLock[xCoreID];
-            pxYieldSpinLock[xCoreID] = NULL;
-            spin_unlock( pxTmpLock, ulYieldSpinLockSaveValue[xCoreID] );
+            spin_lock_t * const pxTmpLock = pxYieldSpinLock[ xCoreID ];
+            pxYieldSpinLock[ xCoreID ] = NULL;
+            spin_unlock( pxTmpLock, ulYieldSpinLockSaveValue[ xCoreID ] );
         }
     #endif
     __asm volatile ( " cpsie i " ::: "memory" );
@@ -537,8 +542,9 @@ void vYieldCore( int xCoreID )
     configASSERT( xCoreID != ( int ) portGET_CORE_ID() );
 
     #if portRUNNING_ON_BOTH_CORES
+
         /* Non blocking, will cause interrupt on other core if the queue isn't already full,
-        in which case an IRQ must be pending */
+         * in which case an IRQ must be pending */
         sio_hw->fifo_wr = 0;
     #endif
 }
@@ -548,179 +554,185 @@ void vYieldCore( int xCoreID )
 void xPortPendSVHandler( void )
 {
     /* This is a naked function. */
-#if ( configNUMBER_OF_CORES == 1 )
-    __asm volatile
-    (
-        "   .syntax unified                     \n"
-        "   mrs r0, psp                         \n"
-        "                                       \n"
-        "   ldr r3, pxCurrentTCBConst2          \n"/* Get the location of the current TCB. */
-        "   ldr r2, [r3]                        \n"
-        "                                       \n"
-        "   subs r0, r0, #32                    \n"/* Make space for the remaining low registers. */
-        "   str r0, [r2]                        \n"/* Save the new top of stack. */
-        "   stmia r0!, {r4-r7}                  \n"/* Store the low registers that are not saved automatically. */
-        "   mov r4, r8                          \n"/* Store the high registers. */
-        "   mov r5, r9                          \n"
-        "   mov r6, r10                         \n"
-        "   mov r7, r11                         \n"
-        "   stmia r0!, {r4-r7}                  \n"
-        #if portUSE_DIVIDER_SAVE_RESTORE
-            "   movs r2, #0xd                   \n"/* Store the divider state. */
-            "   lsls r2, #28                    \n"
-            /* We expect that the divider is ready at this point (which is
-             * necessary to safely save/restore), because:
-             * a) if we have not been interrupted since we entered this method,
-             *    then >8 cycles have clearly passed, so the divider is done
-             * b) if we were interrupted in the interim, then any "safe" - i.e.
-             *    does the right thing in an IRQ - use of the divider should
-             *    have waited for any in-process divide to complete, saved and
-             *    then fully restored the result, thus the result is ready in
-             *    that case too. */
-            "   ldr r4, [r2, #0x60]             \n"/* SIO_DIV_UDIVIDEND_OFFSET */
-            "   ldr r5, [r2, #0x64]             \n"/* SIO_DIV_UDIVISOR_OFFSET */
-            "   ldr r6, [r2, #0x74]             \n"/* SIO_DIV_REMAINDER_OFFSET */
-            "   ldr r7, [r2, #0x70]             \n"/* SIO_DIV_QUOTIENT_OFFSET */
-            /* We actually save the divider state in the 4 words below
-             * our recorded stack pointer, so as not to disrupt the stack
-             * frame expected by debuggers - this is addressed by
-             * portEXTRA_STACK_SIZE */
-            "   subs r0, r0, #48                \n"
-            "   stmia r0!, {r4-r7}              \n"
-        #endif /* portUSE_DIVIDER_SAVE_RESTORE */
-        "   push {r3, r14}                      \n"
-        "   cpsid i                             \n"
-        "   bl vTaskSwitchContext               \n"
-        "   cpsie i                             \n"
-        "   pop {r2, r3}                        \n"/* lr goes in r3. r2 now holds tcb pointer. */
-        "                                       \n"
-        "   ldr r1, [r2]                        \n"
-        "   ldr r0, [r1]                        \n"/* The first item in pxCurrentTCB is the task top of stack. */
-        "   adds r0, r0, #16                    \n"/* Move to the high registers. */
-        "   ldmia r0!, {r4-r7}                  \n"/* Pop the high registers. */
-        "   mov r8, r4                          \n"
-        "   mov r9, r5                          \n"
-        "   mov r10, r6                         \n"
-        "   mov r11, r7                         \n"
-        "                                       \n"
-        "   msr psp, r0                         \n"/* Remember the new top of stack for the task. */
-        "                                       \n"
-        #if portUSE_DIVIDER_SAVE_RESTORE
-        "   movs r2, #0xd                       \n"/* Pop the divider state. */
-        "   lsls r2, #28                        \n"
-        "   subs r0, r0, #48                    \n"/* Go back for the divider state */
-        "   ldmia r0!, {r4-r7}                  \n"/* Pop the divider state. */
-        /* Note always restore via SIO_DIV_UDIVI*, because we will overwrite the
-         * results stopping the calculation anyway, however the sign of results
-         * is adjusted by the h/w at read time based on whether the last started
-         * division was signed and the inputs' signs differed */
-        "   str r4, [r2, #0x60]                 \n"/* SIO_DIV_UDIVIDEND_OFFSET */
-        "   str r5, [r2, #0x64]                 \n"/* SIO_DIV_UDIVISOR_OFFSET */
-        "   str r6, [r2, #0x74]                 \n"/* SIO_DIV_REMAINDER_OFFSET */
-        "   str r7, [r2, #0x70]                 \n"/* SIO_DIV_QUOTIENT_OFFSET */
-        #else
-        "   subs r0, r0, #32                    \n"/* Go back for the low registers that are not automatically restored. */
-        #endif /* portUSE_DIVIDER_SAVE_RESTORE */
-        "   ldmia r0!, {r4-r7}                  \n"/* Pop low registers.  */
-        "                                       \n"
-        "   bx r3                               \n"
-	"   .align 4                            \n"
-	"pxCurrentTCBConst2: .word pxCurrentTCB \n"
-    );
-#else
-    __asm volatile
-    (
-        "   .syntax unified                     \n"
-        "   mrs r1, psp                         \n"
-        "                                       \n"
-        "   adr    r0, ulAsmLocals2             \n"/* Get the location of the current TCB for the current core. */
-        "   ldmia r0!, {r2, r3}                 \n"
-        #if portRUNNING_ON_BOTH_CORES
-            "   ldr r0, [r2]                    \n"/* r0 = Core number */
-            "   lsls r0, r0, #2                 \n"
-            "   adds r3, r0                     \n"/* r3 = &pxCurrentTCBs[get_core_num()] */
-        #else
-            "                                   \n"/* r3 = &pxCurrentTCBs[0] */
-        #endif /* portRUNNING_ON_BOTH_CORES */
-        "   ldr    r0, [r3]                     \n"/* r0 = pxCurrentTCB */
-        "                                       \n"
-        "   subs r1, r1, #32                    \n"/* Make space for the remaining low registers. */
-        "   str r1, [r0]                        \n"/* Save the new top of stack. */
-        "   stmia r1!, {r4-r7}                  \n"/* Store the low registers that are not saved automatically. */
-        "   mov r4, r8                          \n"/* Store the high registers. */
-        "   mov r5, r9                          \n"
-        "   mov r6, r10                         \n"
-        "   mov r7, r11                         \n"
-        "   stmia r1!, {r4-r7}                  \n"
-        #if portUSE_DIVIDER_SAVE_RESTORE
-            /* We expect that the divider is ready at this point (which is
-             * necessary to safely save/restore), because:
-             * a) if we have not been interrupted since we entered this method,
-             *    then >8 cycles have clearly passed, so the divider is done
-             * b) if we were interrupted in the interim, then any "safe" - i.e.
-             *    does the right thing in an IRQ - use of the divider should
-             *    have waited for any in-process divide to complete, saved and
-             *    then fully restored the result, thus the result is ready in
-             *    that case too. */
-            "   ldr r4, [r2, #0x60]             \n"/* SIO_DIV_UDIVIDEND_OFFSET */
-            "   ldr r5, [r2, #0x64]             \n"/* SIO_DIV_UDIVISOR_OFFSET */
-            "   ldr r6, [r2, #0x74]             \n"/* SIO_DIV_REMAINDER_OFFSET */
-            "   ldr r7, [r2, #0x70]             \n"/* SIO_DIV_QUOTIENT_OFFSET */
-            /* We actually save the divider state in the 4 words below
-             * our recorded stack pointer, so as not to disrupt the stack
-             * frame expected by debuggers - this is addressed by
-             * portEXTRA_STACK_SIZE */
-            "   subs r1, r1, #48                \n"
-            "   stmia r1!, {r4-r7}              \n"
-        #endif /* portUSE_DIVIDER_SAVE_RESTORE */
-        #if portRUNNING_ON_BOTH_CORES
-            "   ldr r0, [r2]                    \n"/* r0 = Core number */
-        #else
-            "   movs r0, #0                     \n"
-        #endif /* portRUNNING_ON_BOTH_CORES */
-        "   push {r3, r14}                      \n"
-        "   cpsid i                             \n"
-        "   bl vTaskSwitchContext               \n"
-        "   cpsie i                             \n"
-        "   pop {r2, r3}                        \n"/* lr goes in r3. r2 now holds tcb pointer. */
-        "                                       \n"
-        "   ldr r1, [r2]                        \n"
-        "   ldr r0, [r1]                        \n"/* The first item in pxCurrentTCB is the task top of stack. */
-        "   adds r0, r0, #16                    \n"/* Move to the high registers. */
-        "   ldmia r0!, {r4-r7}                  \n"/* Pop the high registers. */
-        "    mov r8, r4                         \n"
-        "    mov r9, r5                         \n"
-        "    mov r10, r6                        \n"
-        "    mov r11, r7                        \n"
-        "                                       \n"
-        "   msr psp, r0                         \n"/* Remember the new top of stack for the task. */
-        "                                       \n"
-        #if portUSE_DIVIDER_SAVE_RESTORE
-        "   movs r2, #0xd                       \n"/* Pop the divider state. */
-        "   lsls r2, #28                        \n"
-        "   subs r0, r0, #48                    \n"/* Go back for the divider state */
-        "   ldmia r0!, {r4-r7}                  \n"/* Pop the divider state. */
-        /* Note always restore via SIO_DIV_UDIVI*, because we will overwrite the
-         * results stopping the calculation anyway, however the sign of results
-         * is adjusted by the h/w at read time based on whether the last started
-         * division was signed and the inputs' signs differed */
-        "   str r4, [r2, #0x60]                \n"/* SIO_DIV_UDIVIDEND_OFFSET */
-        "   str r5, [r2, #0x64]                \n"/* SIO_DIV_UDIVISOR_OFFSET */
-        "   str r6, [r2, #0x74]                \n"/* SIO_DIV_REMAINDER_OFFSET */
-        "   str r7, [r2, #0x70]                \n"/* SIO_DIV_QUOTIENT_OFFSET */
-        #else
-        "   subs r0, r0, #32                   \n"/* Go back for the low registers that are not automatically restored. */
-        #endif /* portUSE_DIVIDER_SAVE_RESTORE */
-        "   ldmia r0!, {r4-r7}                 \n"/* Pop low registers.  */
-        "                                      \n"
-        "   bx r3                              \n"
-        "                                      \n"
-        "   .align 4                           \n"
-        "ulAsmLocals2:                         \n"
-        "   .word 0xD0000000                   \n"/* SIO */
-        "   .word pxCurrentTCBs                \n"
-    );
-#endif
+    #if ( configNUMBER_OF_CORES == 1 )
+        __asm volatile
+        (
+            "   .syntax unified                     \n"
+            "   mrs r0, psp                         \n"
+            "                                       \n"
+            "   ldr r3, pxCurrentTCBConst2          \n" /* Get the location of the current TCB. */
+            "   ldr r2, [r3]                        \n"
+            "                                       \n"
+            "   subs r0, r0, #32                    \n" /* Make space for the remaining low registers. */
+            "   str r0, [r2]                        \n" /* Save the new top of stack. */
+            "   stmia r0!, {r4-r7}                  \n" /* Store the low registers that are not saved automatically. */
+            "   mov r4, r8                          \n" /* Store the high registers. */
+            "   mov r5, r9                          \n"
+            "   mov r6, r10                         \n"
+            "   mov r7, r11                         \n"
+            "   stmia r0!, {r4-r7}                  \n"
+            #if portUSE_DIVIDER_SAVE_RESTORE
+                "   movs r2, #0xd                   \n" /* Store the divider state. */
+                "   lsls r2, #28                    \n"
+
+                /* We expect that the divider is ready at this point (which is
+                 * necessary to safely save/restore), because:
+                 * a) if we have not been interrupted since we entered this method,
+                 *    then >8 cycles have clearly passed, so the divider is done
+                 * b) if we were interrupted in the interim, then any "safe" - i.e.
+                 *    does the right thing in an IRQ - use of the divider should
+                 *    have waited for any in-process divide to complete, saved and
+                 *    then fully restored the result, thus the result is ready in
+                 *    that case too. */
+                "   ldr r4, [r2, #0x60]             \n" /* SIO_DIV_UDIVIDEND_OFFSET */
+                "   ldr r5, [r2, #0x64]             \n" /* SIO_DIV_UDIVISOR_OFFSET */
+                "   ldr r6, [r2, #0x74]             \n" /* SIO_DIV_REMAINDER_OFFSET */
+                "   ldr r7, [r2, #0x70]             \n" /* SIO_DIV_QUOTIENT_OFFSET */
+
+                /* We actually save the divider state in the 4 words below
+                 * our recorded stack pointer, so as not to disrupt the stack
+                 * frame expected by debuggers - this is addressed by
+                 * portEXTRA_STACK_SIZE */
+                "   subs r0, r0, #48                \n"
+                "   stmia r0!, {r4-r7}              \n"
+            #endif /* portUSE_DIVIDER_SAVE_RESTORE */
+            "   push {r3, r14}                      \n"
+            "   cpsid i                             \n"
+            "   bl vTaskSwitchContext               \n"
+            "   cpsie i                             \n"
+            "   pop {r2, r3}                        \n" /* lr goes in r3. r2 now holds tcb pointer. */
+            "                                       \n"
+            "   ldr r1, [r2]                        \n"
+            "   ldr r0, [r1]                        \n" /* The first item in pxCurrentTCB is the task top of stack. */
+            "   adds r0, r0, #16                    \n" /* Move to the high registers. */
+            "   ldmia r0!, {r4-r7}                  \n" /* Pop the high registers. */
+            "   mov r8, r4                          \n"
+            "   mov r9, r5                          \n"
+            "   mov r10, r6                         \n"
+            "   mov r11, r7                         \n"
+            "                                       \n"
+            "   msr psp, r0                         \n" /* Remember the new top of stack for the task. */
+            "                                       \n"
+            #if portUSE_DIVIDER_SAVE_RESTORE
+                "   movs r2, #0xd                       \n" /* Pop the divider state. */
+                "   lsls r2, #28                        \n"
+                "   subs r0, r0, #48                    \n" /* Go back for the divider state */
+                "   ldmia r0!, {r4-r7}                  \n" /* Pop the divider state. */
+
+                /* Note always restore via SIO_DIV_UDIVI*, because we will overwrite the
+                 * results stopping the calculation anyway, however the sign of results
+                 * is adjusted by the h/w at read time based on whether the last started
+                 * division was signed and the inputs' signs differed */
+                "   str r4, [r2, #0x60]                 \n" /* SIO_DIV_UDIVIDEND_OFFSET */
+                "   str r5, [r2, #0x64]                 \n" /* SIO_DIV_UDIVISOR_OFFSET */
+                "   str r6, [r2, #0x74]                 \n" /* SIO_DIV_REMAINDER_OFFSET */
+                "   str r7, [r2, #0x70]                 \n" /* SIO_DIV_QUOTIENT_OFFSET */
+            #else /* if portUSE_DIVIDER_SAVE_RESTORE */
+                "   subs r0, r0, #32                    \n" /* Go back for the low registers that are not automatically restored. */
+            #endif /* portUSE_DIVIDER_SAVE_RESTORE */
+            "   ldmia r0!, {r4-r7}                  \n"     /* Pop low registers.  */
+            "                                       \n"
+            "   bx r3                               \n"
+            "   .align 4                            \n"
+            "pxCurrentTCBConst2: .word pxCurrentTCB \n"
+        );
+    #else /* if ( configNUMBER_OF_CORES == 1 ) */
+        __asm volatile
+        (
+            "   .syntax unified                     \n"
+            "   mrs r1, psp                         \n"
+            "                                       \n"
+            "   adr    r0, ulAsmLocals2             \n" /* Get the location of the current TCB for the current core. */
+            "   ldmia r0!, {r2, r3}                 \n"
+            #if portRUNNING_ON_BOTH_CORES
+                "   ldr r0, [r2]                    \n" /* r0 = Core number */
+                "   lsls r0, r0, #2                 \n"
+                "   adds r3, r0                     \n" /* r3 = &pxCurrentTCBs[get_core_num()] */
+            #else
+                "                                   \n" /* r3 = &pxCurrentTCBs[0] */
+            #endif /* portRUNNING_ON_BOTH_CORES */
+            "   ldr    r0, [r3]                     \n" /* r0 = pxCurrentTCB */
+            "                                       \n"
+            "   subs r1, r1, #32                    \n" /* Make space for the remaining low registers. */
+            "   str r1, [r0]                        \n" /* Save the new top of stack. */
+            "   stmia r1!, {r4-r7}                  \n" /* Store the low registers that are not saved automatically. */
+            "   mov r4, r8                          \n" /* Store the high registers. */
+            "   mov r5, r9                          \n"
+            "   mov r6, r10                         \n"
+            "   mov r7, r11                         \n"
+            "   stmia r1!, {r4-r7}                  \n"
+            #if portUSE_DIVIDER_SAVE_RESTORE
+
+                /* We expect that the divider is ready at this point (which is
+                 * necessary to safely save/restore), because:
+                 * a) if we have not been interrupted since we entered this method,
+                 *    then >8 cycles have clearly passed, so the divider is done
+                 * b) if we were interrupted in the interim, then any "safe" - i.e.
+                 *    does the right thing in an IRQ - use of the divider should
+                 *    have waited for any in-process divide to complete, saved and
+                 *    then fully restored the result, thus the result is ready in
+                 *    that case too. */
+                "   ldr r4, [r2, #0x60]             \n" /* SIO_DIV_UDIVIDEND_OFFSET */
+                "   ldr r5, [r2, #0x64]             \n" /* SIO_DIV_UDIVISOR_OFFSET */
+                "   ldr r6, [r2, #0x74]             \n" /* SIO_DIV_REMAINDER_OFFSET */
+                "   ldr r7, [r2, #0x70]             \n" /* SIO_DIV_QUOTIENT_OFFSET */
+
+                /* We actually save the divider state in the 4 words below
+                 * our recorded stack pointer, so as not to disrupt the stack
+                 * frame expected by debuggers - this is addressed by
+                 * portEXTRA_STACK_SIZE */
+                "   subs r1, r1, #48                \n"
+                "   stmia r1!, {r4-r7}              \n"
+            #endif /* portUSE_DIVIDER_SAVE_RESTORE */
+            #if portRUNNING_ON_BOTH_CORES
+                "   ldr r0, [r2]                    \n" /* r0 = Core number */
+            #else
+                "   movs r0, #0                     \n"
+            #endif /* portRUNNING_ON_BOTH_CORES */
+            "   push {r3, r14}                      \n"
+            "   cpsid i                             \n"
+            "   bl vTaskSwitchContext               \n"
+            "   cpsie i                             \n"
+            "   pop {r2, r3}                        \n" /* lr goes in r3. r2 now holds tcb pointer. */
+            "                                       \n"
+            "   ldr r1, [r2]                        \n"
+            "   ldr r0, [r1]                        \n" /* The first item in pxCurrentTCB is the task top of stack. */
+            "   adds r0, r0, #16                    \n" /* Move to the high registers. */
+            "   ldmia r0!, {r4-r7}                  \n" /* Pop the high registers. */
+            "    mov r8, r4                         \n"
+            "    mov r9, r5                         \n"
+            "    mov r10, r6                        \n"
+            "    mov r11, r7                        \n"
+            "                                       \n"
+            "   msr psp, r0                         \n" /* Remember the new top of stack for the task. */
+            "                                       \n"
+            #if portUSE_DIVIDER_SAVE_RESTORE
+                "   movs r2, #0xd                       \n" /* Pop the divider state. */
+                "   lsls r2, #28                        \n"
+                "   subs r0, r0, #48                    \n" /* Go back for the divider state */
+                "   ldmia r0!, {r4-r7}                  \n" /* Pop the divider state. */
+
+                /* Note always restore via SIO_DIV_UDIVI*, because we will overwrite the
+                 * results stopping the calculation anyway, however the sign of results
+                 * is adjusted by the h/w at read time based on whether the last started
+                 * division was signed and the inputs' signs differed */
+                "   str r4, [r2, #0x60]                \n" /* SIO_DIV_UDIVIDEND_OFFSET */
+                "   str r5, [r2, #0x64]                \n" /* SIO_DIV_UDIVISOR_OFFSET */
+                "   str r6, [r2, #0x74]                \n" /* SIO_DIV_REMAINDER_OFFSET */
+                "   str r7, [r2, #0x70]                \n" /* SIO_DIV_QUOTIENT_OFFSET */
+            #else /* if portUSE_DIVIDER_SAVE_RESTORE */
+                "   subs r0, r0, #32                   \n" /* Go back for the low registers that are not automatically restored. */
+            #endif /* portUSE_DIVIDER_SAVE_RESTORE */
+            "   ldmia r0!, {r4-r7}                 \n"     /* Pop low registers.  */
+            "                                      \n"
+            "   bx r3                              \n"
+            "                                      \n"
+            "   .align 4                           \n"
+            "ulAsmLocals2:                         \n"
+            "   .word 0xD0000000                   \n" /* SIO */
+            "   .word pxCurrentTCBs                \n"
+        );
+    #endif /* if ( configNUMBER_OF_CORES == 1 ) */
 }
 /*-----------------------------------------------------------*/
 
@@ -749,11 +761,11 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
 {
     /* Calculate the constants required to configure the tick interrupt. */
     #if ( configUSE_TICKLESS_IDLE == 1 )
-        {
-            ulTimerCountsForOneTick = ( clock_get_hz(clk_sys) / configTICK_RATE_HZ );
-            xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
-            ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR;
-        }
+    {
+        ulTimerCountsForOneTick = ( clock_get_hz( clk_sys ) / configTICK_RATE_HZ );
+        xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+        ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR;
+    }
     #endif /* configUSE_TICKLESS_IDLE */
 
     /* Stop and reset the SysTick. */
@@ -938,32 +950,38 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
 #if ( configSUPPORT_PICO_SYNC_INTEROP == 1 ) || ( configSUPPORT_PICO_TIME_INTEROP == 1 )
     static TickType_t prvGetTicksToWaitBefore( absolute_time_t t )
     {
-        int64_t xDelay = absolute_time_diff_us(get_absolute_time(), t);
+        int64_t xDelay = absolute_time_diff_us( get_absolute_time(), t );
         const uint32_t ulTickPeriod = 1000000 / configTICK_RATE_HZ;
+
         xDelay -= ulTickPeriod;
+
         if( xDelay >= ulTickPeriod )
         {
             return xDelay / ulTickPeriod;
         }
+
         return 0;
     }
-#endif
+#endif /* if ( configSUPPORT_PICO_SYNC_INTEROP == 1 ) || ( configSUPPORT_PICO_TIME_INTEROP == 1 ) */
 
 #if ( configSUPPORT_PICO_SYNC_INTEROP == 1 )
     uint32_t ulPortLockGetCurrentOwnerId()
     {
-        if( portIS_FREE_RTOS_CORE())
+        if( portIS_FREE_RTOS_CORE() )
         {
             uint32_t exception = __get_current_exception();
+
             if( !exception )
             {
                 return ( uintptr_t ) xTaskGetCurrentTaskHandle();
             }
+
             /* Note: since ROM as at 0x00000000, these can't be confused with
              * valid task handles (pointers) in RAM */
             /* We make all exception handler/core combinations distinct owners */
             return get_core_num() + exception * 2;
         }
+
         /* Note: since ROM as at 0x00000000, this can't be confused with
          * valid task handles (pointers) in RAM */
         return get_core_num();
@@ -972,10 +990,11 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
     static inline EventBits_t prvGetEventGroupBit( spin_lock_t * spinLock )
     {
         uint32_t ulBit;
+
         #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-            ulBit = 1u << (spin_lock_get_num(spinLock) & 0x7u);
+            ulBit = 1u << ( spin_lock_get_num( spinLock ) & 0x7u );
         #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-            ulBit = 1u << spin_lock_get_num(spinLock);
+            ulBit = 1u << spin_lock_get_num( spinLock );
             /* reduce to range 0-24 */
             ulBit |= ulBit << 8u;
             ulBit >>= 8u;
@@ -986,45 +1005,52 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
     static inline EventBits_t prvGetAllEventGroupBits()
     {
         #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-            return (EventBits_t) 0xffu;
+            return ( EventBits_t ) 0xffu;
         #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
             return ( EventBits_t ) 0xffffffu;
         #endif /* configTICK_TYPE_WIDTH_IN_BITS */
     }
 
-    void vPortLockInternalSpinUnlockWithWait( struct lock_core * pxLock, uint32_t ulSave )
+    void vPortLockInternalSpinUnlockWithWait( struct lock_core * pxLock,
+                                              uint32_t ulSave )
     {
         configASSERT( !portCHECK_IF_IN_ISR() );
-        // note no need to check LIB_PICO_MULTICORE, as this is always returns true if that is not defined
+
+        /* note no need to check LIB_PICO_MULTICORE, as this is always returns true if that is not defined */
         if( !portIS_FREE_RTOS_CORE() )
         {
-            spin_unlock(pxLock->spin_lock, ulSave );
+            spin_unlock( pxLock->spin_lock, ulSave );
             __wfe();
         }
         else
         {
             configASSERT( pxYieldSpinLock[ portGET_CORE_ID() ] == NULL );
 
-            // we want to hold the lock until the event bits have been set; since interrupts are currently disabled
-            // by the spinlock, we can defer until portENABLE_INTERRUPTS is called which is always called when
-            // the scheduler is unlocked during this call
-            configASSERT(pxLock->spin_lock);
+            /* we want to hold the lock until the event bits have been set; since interrupts are currently disabled */
+            /* by the spinlock, we can defer until portENABLE_INTERRUPTS is called which is always called when */
+            /* the scheduler is unlocked during this call */
+            configASSERT( pxLock->spin_lock );
             int xCoreID = ( int ) portGET_CORE_ID();
-            pxYieldSpinLock[xCoreID] = pxLock->spin_lock;
-            ulYieldSpinLockSaveValue[xCoreID] = ulSave;
-            xEventGroupWaitBits( xEventGroup, prvGetEventGroupBit(pxLock->spin_lock),
-                                 pdTRUE, pdFALSE, portMAX_DELAY);
+            pxYieldSpinLock[ xCoreID ] = pxLock->spin_lock;
+            ulYieldSpinLockSaveValue[ xCoreID ] = ulSave;
+            xEventGroupWaitBits( xEventGroup, prvGetEventGroupBit( pxLock->spin_lock ),
+                                 pdTRUE, pdFALSE, portMAX_DELAY );
         }
     }
 
-    void vPortLockInternalSpinUnlockWithNotify( struct lock_core *pxLock, uint32_t ulSave ) {
-        EventBits_t uxBits = prvGetEventGroupBit(pxLock->spin_lock );
-        if (portIS_FREE_RTOS_CORE()) {
+    void vPortLockInternalSpinUnlockWithNotify( struct lock_core * pxLock,
+                                                uint32_t ulSave )
+    {
+        EventBits_t uxBits = prvGetEventGroupBit( pxLock->spin_lock );
+
+        if( portIS_FREE_RTOS_CORE() )
+        {
             #if LIB_PICO_MULTICORE
                 /* signal an event in case a regular core is waiting */
                 __sev();
             #endif
-            spin_unlock(pxLock->spin_lock, ulSave );
+            spin_unlock( pxLock->spin_lock, ulSave );
+
             if( !portCHECK_IF_IN_ISR() )
             {
                 xEventGroupSetBits( xEventGroup, uxBits );
@@ -1040,34 +1066,39 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
         {
             __sev();
             #if ( portRUNNING_ON_BOTH_CORES == 0 )
+
                 /* We could sent the bits across the FIFO which would have required us to block here if the FIFO was full,
                  * or we could have just set all bits on the other side, however it seems reasonable instead to take
                  * the hit of another spin lock to protect an accurate bit set. */
                 if( pxCrossCoreSpinLock != pxLock->spin_lock )
                 {
-                    spin_lock_unsafe_blocking(pxCrossCoreSpinLock);
+                    spin_lock_unsafe_blocking( pxCrossCoreSpinLock );
                     uxCrossCoreEventBits |= uxBits;
-                    spin_unlock_unsafe(pxCrossCoreSpinLock);
+                    spin_unlock_unsafe( pxCrossCoreSpinLock );
                 }
                 else
                 {
                     uxCrossCoreEventBits |= uxBits;
                 }
+
                 /* This causes fifo irq on the other (FreeRTOS) core which will do the set the event bits */
                 sio_hw->fifo_wr = 0;
             #endif /* portRUNNING_ON_BOTH_CORES == 0 */
-            spin_unlock(pxLock->spin_lock, ulSave);
+            spin_unlock( pxLock->spin_lock, ulSave );
         }
     }
 
-    bool xPortLockInternalSpinUnlockWithBestEffortWaitOrTimeout( struct lock_core * pxLock, uint32_t ulSave, absolute_time_t uxUntil )
+    bool xPortLockInternalSpinUnlockWithBestEffortWaitOrTimeout( struct lock_core * pxLock,
+                                                                 uint32_t ulSave,
+                                                                 absolute_time_t uxUntil )
     {
         configASSERT( !portCHECK_IF_IN_ISR() );
-        // note no need to check LIB_PICO_MULTICORE, as this is always returns true if that is not defined
+
+        /* note no need to check LIB_PICO_MULTICORE, as this is always returns true if that is not defined */
         if( !portIS_FREE_RTOS_CORE() )
         {
-            spin_unlock(pxLock->spin_lock, ulSave);
-            return best_effort_wfe_or_timeout(uxUntil);
+            spin_unlock( pxLock->spin_lock, ulSave );
+            return best_effort_wfe_or_timeout( uxUntil );
         }
         else
         {
@@ -1075,24 +1106,26 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
             configASSERT( pxYieldSpinLock[ portGET_CORE_ID() ] == NULL );
 
             TickType_t uxTicksToWait = prvGetTicksToWaitBefore( uxUntil );
+
             if( uxTicksToWait )
             {
                 /* We want to hold the lock until the event bits have been set; since interrupts are currently disabled
                  * by the spinlock, we can defer until portENABLE_INTERRUPTS is called which is always called when
                  * the scheduler is unlocked during this call */
-                configASSERT(pxLock->spin_lock);
+                configASSERT( pxLock->spin_lock );
                 int xCoreID = ( int ) portGET_CORE_ID();
-                pxYieldSpinLock[xCoreID] = pxLock->spin_lock;
-                ulYieldSpinLockSaveValue[xCoreID] = ulSave;
+                pxYieldSpinLock[ xCoreID ] = pxLock->spin_lock;
+                ulYieldSpinLockSaveValue[ xCoreID ] = ulSave;
                 xEventGroupWaitBits( xEventGroup,
-                                     prvGetEventGroupBit(pxLock->spin_lock), pdTRUE,
+                                     prvGetEventGroupBit( pxLock->spin_lock ), pdTRUE,
                                      pdFALSE, uxTicksToWait );
             }
             else
             {
                 spin_unlock( pxLock->spin_lock, ulSave );
             }
-            if ( time_reached( uxUntil ) )
+
+            if( time_reached( uxUntil ) )
             {
                 return true;
             }
@@ -1106,9 +1139,9 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
         }
     }
 
-    #if ( configSUPPORT_PICO_SYNC_INTEROP == 1)
+    #if ( configSUPPORT_PICO_SYNC_INTEROP == 1 )
         /* runs before main */
-        static void __attribute__((constructor)) prvRuntimeInitializer( void )
+        static void __attribute__( ( constructor ) ) prvRuntimeInitializer( void )
         {
             /* This must be done even before the scheduler is started, as the spin lock
              * is used by the overrides of the SDK wait/notify primitives */
@@ -1119,8 +1152,9 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
             /* The event group is not used prior to scheduler init, but is initialized
              * here to since it logically belongs with the spin lock */
             #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
-                xEventGroup = xEventGroupCreateStatic(&xStaticEventGroup);
+                xEventGroup = xEventGroupCreateStatic( &xStaticEventGroup );
             #else
+
                 /* Note that it is slightly dubious calling this here before the scheduler is initialized,
                  * however the only thing it touches is the allocator which then calls vPortEnterCritical
                  * and vPortExitCritical, and allocating here saves us checking the one time initialized variable in
@@ -1128,16 +1162,17 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
                 xEventGroup = xEventGroupCreate();
             #endif /* configSUPPORT_STATIC_ALLOCATION */
         }
-    #endif
+    #endif /* if ( configSUPPORT_PICO_SYNC_INTEROP == 1 ) */
 #endif /* configSUPPORT_PICO_SYNC_INTEROP */
 
 #if ( configSUPPORT_PICO_TIME_INTEROP == 1 )
     void xPortSyncInternalYieldUntilBefore( absolute_time_t t )
     {
-        TickType_t uxTicksToWait = prvGetTicksToWaitBefore(t);
+        TickType_t uxTicksToWait = prvGetTicksToWaitBefore( t );
+
         if( uxTicksToWait )
         {
-            vTaskDelay(uxTicksToWait);
+            vTaskDelay( uxTicksToWait );
         }
     }
 #endif /* configSUPPORT_PICO_TIME_INTEROP */
diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/include/FreeRTOSConfig_arch.h b/portable/ThirdParty/GCC/Xtensa_ESP32/include/FreeRTOSConfig_arch.h
index eebfcde84..111c99f1a 100644
--- a/portable/ThirdParty/GCC/Xtensa_ESP32/include/FreeRTOSConfig_arch.h
+++ b/portable/ThirdParty/GCC/Xtensa_ESP32/include/FreeRTOSConfig_arch.h
@@ -5,6 +5,7 @@
  *
  * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD
  */
+
 /*
  * FreeRTOS Kernel V10.4.3
  * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
@@ -39,29 +40,30 @@
 #include "sdkconfig.h"
 
 /* enable use of optimized task selection by the scheduler */
-#if defined (CONFIG_FREERTOS_OPTIMIZED_SCHEDULER) && !defined(configUSE_PORT_OPTIMISED_TASK_SELECTION)
-#define configUSE_PORT_OPTIMISED_TASK_SELECTION         1
+#if defined( CONFIG_FREERTOS_OPTIMIZED_SCHEDULER ) && !defined( configUSE_PORT_OPTIMISED_TASK_SELECTION )
+    #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
 #endif
 
-#define XT_USE_THREAD_SAFE_CLIB                         0
+#define XT_USE_THREAD_SAFE_CLIB                        0
 #undef XT_USE_SWPRI
 
 #if CONFIG_FREERTOS_CORETIMER_0
-#define XT_TIMER_INDEX                                  0
+    #define XT_TIMER_INDEX    0
 #elif CONFIG_FREERTOS_CORETIMER_1
-#define XT_TIMER_INDEX                                  1
+    #define XT_TIMER_INDEX    1
 #endif
 
 #ifndef __ASSEMBLER__
+
 /**
  * This function is defined to provide a deprecation warning whenever
  * XT_CLOCK_FREQ macro is used.
  * Update the code to use esp_clk_cpu_freq function instead.
  * @return current CPU clock frequency, in Hz
  */
-int xt_clock_freq(void) __attribute__((deprecated));
+    int xt_clock_freq( void ) __attribute__( ( deprecated ) );
 
-#define XT_CLOCK_FREQ   (xt_clock_freq())
+    #define XT_CLOCK_FREQ    ( xt_clock_freq() )
 
 #endif // __ASSEMBLER__
 
@@ -70,47 +72,50 @@ int xt_clock_freq(void) __attribute__((deprecated));
 
 /* configASSERT behaviour */
 #ifndef __ASSEMBLER__
-#include <assert.h>
-#include "esp_rom_sys.h"
-#if CONFIG_IDF_TARGET_ESP32
-#include "esp32/rom/ets_sys.h"  // will be removed in idf v5.0
-#elif CONFIG_IDF_TARGET_ESP32S2
-#include "esp32s2/rom/ets_sys.h"
-#elif CONFIG_IDF_TARGET_ESP32S3
-#include "esp32s3/rom/ets_sys.h"
-#endif
+    #include <assert.h>
+    #include "esp_rom_sys.h"
+    #if CONFIG_IDF_TARGET_ESP32
+        #include "esp32/rom/ets_sys.h" /* will be removed in idf v5.0 */
+    #elif CONFIG_IDF_TARGET_ESP32S2
+        #include "esp32s2/rom/ets_sys.h"
+    #elif CONFIG_IDF_TARGET_ESP32S3
+        #include "esp32s3/rom/ets_sys.h"
+    #endif
 #endif // __ASSEMBLER__
 
-// If CONFIG_FREERTOS_ASSERT_DISABLE is set then configASSERT is defined empty later in FreeRTOS.h and the macro
-// configASSERT_DEFINED remains unset (meaning some warnings are avoided)
+/* If CONFIG_FREERTOS_ASSERT_DISABLE is set then configASSERT is defined empty later in FreeRTOS.h and the macro */
+/* configASSERT_DEFINED remains unset (meaning some warnings are avoided) */
 #ifdef configASSERT
-#undef configASSERT
-#if defined(CONFIG_FREERTOS_ASSERT_FAIL_PRINT_CONTINUE)
-#define configASSERT(a) if (unlikely(!(a))) {                           \
-        esp_rom_printf("%s:%d (%s)- assert failed!\n", __FILE__, __LINE__,  \
-                   __FUNCTION__);                                           \
+    #undef configASSERT
+    #if defined( CONFIG_FREERTOS_ASSERT_FAIL_PRINT_CONTINUE )
+        #define configASSERT( a )                                           \
+    if( unlikely( !( a ) ) ) {                                              \
+        esp_rom_printf( "%s:%d (%s)- assert failed!\n", __FILE__, __LINE__, \
+                        __FUNCTION__ );                                     \
     }
-#elif defined(CONFIG_FREERTOS_ASSERT_FAIL_ABORT)
-#define configASSERT(a) assert(a)
-#endif
-#endif
+    #elif defined( CONFIG_FREERTOS_ASSERT_FAIL_ABORT )
+        #define configASSERT( a )    assert( a )
+    #endif
+#endif /* ifdef configASSERT */
 
 #if CONFIG_FREERTOS_ASSERT_ON_UNTESTED_FUNCTION
-#define UNTESTED_FUNCTION() { esp_rom_printf("Untested FreeRTOS function %s\r\n", __FUNCTION__); configASSERT(false); } while(0)
+    #define UNTESTED_FUNCTION()                                                                     \
+    { esp_rom_printf( "Untested FreeRTOS function %s\r\n", __FUNCTION__ ); configASSERT( false ); } \
+    while( 0 )
 #else
-#define UNTESTED_FUNCTION()
+    #define UNTESTED_FUNCTION()
 #endif
 
-#define configXT_BOARD                                  1   /* Board mode */
-#define configXT_SIMULATOR                              0
+#define configXT_BOARD                          1           /* Board mode */
+#define configXT_SIMULATOR                      0
 
 /* The maximum interrupt priority from which FreeRTOS.org API functions can
-   be called.  Only API functions that end in ...FromISR() can be used within
-   interrupts. */
+ * be called.  Only API functions that end in ...FromISR() can be used within
+ * interrupts. */
 #define configMAX_SYSCALL_INTERRUPT_PRIORITY    XCHAL_EXCM_LEVEL
 
 /* Stack alignment, architecture specifc. Must be a power of two. */
-#define configSTACK_ALIGNMENT                           16
+#define configSTACK_ALIGNMENT                   16
 
 
 /* The Xtensa port uses a separate interrupt stack. Adjust the stack size
@@ -119,16 +124,16 @@ int xt_clock_freq(void) __attribute__((deprecated));
  * the stack for the 2nd CPU will be calculated using configISR_STACK_SIZE.
  */
 #ifndef configISR_STACK_SIZE
-#define configISR_STACK_SIZE                            ((CONFIG_FREERTOS_ISR_STACKSIZE + configSTACK_ALIGNMENT - 1) & (~(configSTACK_ALIGNMENT - 1)))
+    #define configISR_STACK_SIZE    ( ( CONFIG_FREERTOS_ISR_STACKSIZE + configSTACK_ALIGNMENT - 1 ) & ( ~( configSTACK_ALIGNMENT - 1 ) ) )
 #endif
 
 #ifndef __ASSEMBLER__
-#if CONFIG_APPTRACE_SV_ENABLE
-extern uint32_t port_switch_flag[];
-#define os_task_switch_is_pended(_cpu_) (port_switch_flag[_cpu_])
-#else
-#define os_task_switch_is_pended(_cpu_) (false)
-#endif
+    #if CONFIG_APPTRACE_SV_ENABLE
+        extern uint32_t port_switch_flag[];
+        #define os_task_switch_is_pended( _cpu_ )    ( port_switch_flag[ _cpu_ ] )
+    #else
+        #define os_task_switch_is_pended( _cpu_ )    ( false )
+    #endif
 #endif
 
 #endif // FREERTOS_CONFIG_XTENSA_H
diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/include/port_systick.h b/portable/ThirdParty/GCC/Xtensa_ESP32/include/port_systick.h
index 738b5a180..22f18ba52 100644
--- a/portable/ThirdParty/GCC/Xtensa_ESP32/include/port_systick.h
+++ b/portable/ThirdParty/GCC/Xtensa_ESP32/include/port_systick.h
@@ -15,7 +15,7 @@
 /**
  * @brief Set up the SysTick interrupt
  */
-void vPortSetupTimer(void);
+void vPortSetupTimer( void );
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/include/portbenchmark.h b/portable/ThirdParty/GCC/Xtensa_ESP32/include/portbenchmark.h
index 4f14dc478..ad5c881d1 100644
--- a/portable/ThirdParty/GCC/Xtensa_ESP32/include/portbenchmark.h
+++ b/portable/ThirdParty/GCC/Xtensa_ESP32/include/portbenchmark.h
@@ -5,6 +5,7 @@
  *
  * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD
  */
+
 /*
  * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
  *
diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/include/portmacro.h b/portable/ThirdParty/GCC/Xtensa_ESP32/include/portmacro.h
index e87d560cf..c5981eaa5 100644
--- a/portable/ThirdParty/GCC/Xtensa_ESP32/include/portmacro.h
+++ b/portable/ThirdParty/GCC/Xtensa_ESP32/include/portmacro.h
@@ -6,6 +6,7 @@
  *
  * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD
  */
+
 /*
  * FreeRTOS Kernel V10.4.3
  * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
@@ -75,23 +76,23 @@
     #include <xtensa/config/system.h> /* required for XSHAL_CLIB */
     #include <xtensa/xtruntime.h>
     #include "soc/spinlock.h"
-    #include "esp_timer.h"            /* required for FreeRTOS run time stats */
+    #include "esp_timer.h" /* required for FreeRTOS run time stats */
     #include "esp_system.h"
     #include "esp_idf_version.h"
     #include "esp_heap_caps.h"
 
-    /* TODO: Resolve build warnings generated due to this header inclusion */
+/* TODO: Resolve build warnings generated due to this header inclusion */
     #include "hal/cpu_hal.h"
 
-    /* TODO: These includes are not directly used in this file. They are kept into to prevent a breaking change. Remove these. */
+/* TODO: These includes are not directly used in this file. They are kept into to prevent a breaking change. Remove these. */
     #include <limits.h>
     #include <xtensa/xtensa_api.h>
 
     #include "soc/cpu.h"
     #include "soc/soc_memory_layout.h"
-#if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0))
-    #include "soc/compare_set.h"
-#endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */
+    #if ( ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL( 4, 2, 0 ) )
+        #include "soc/compare_set.h"
+    #endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */
 
 /*#include "xtensa_context.h" */
 
@@ -122,7 +123,7 @@
     #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
         typedef uint16_t             TickType_t;
         #define portMAX_DELAY    ( TickType_t ) 0xffff
-    #elif ( configTICK_TYPE_WIDTH_IN_BITS  == TICK_TYPE_WIDTH_32_BITS )
+    #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
         typedef uint32_t             TickType_t;
         #define portMAX_DELAY    ( TickType_t ) 0xffffffffUL
     #else
@@ -137,14 +138,14 @@
     #include "esp_attr.h"
 
 /* "mux" data structure (spinlock) */
-    typedef spinlock_t                          portMUX_TYPE;               /**< Spinlock type used by FreeRTOS critical sections */
-    #define portMUX_INITIALIZER_UNLOCKED        SPINLOCK_INITIALIZER        /**< Spinlock initializer */
-    #define portMUX_FREE_VAL                    SPINLOCK_FREE               /**< Spinlock is free. [refactor-todo] check if this is still required */
-    #define portMUX_NO_TIMEOUT                  SPINLOCK_WAIT_FOREVER       /**< When passed for 'timeout_cycles', spin forever if necessary. [refactor-todo] check if this is still required */
-    #define portMUX_TRY_LOCK                    SPINLOCK_NO_WAIT            /**< Try to acquire the spinlock a single time only. [refactor-todo] check if this is still required */
-    #define portMUX_INITIALIZE(mux)             spinlock_initialize(mux)    /*< Initialize a spinlock to its unlocked state */
+    typedef spinlock_t portMUX_TYPE;                                /**< Spinlock type used by FreeRTOS critical sections */
+    #define portMUX_INITIALIZER_UNLOCKED    SPINLOCK_INITIALIZER    /**< Spinlock initializer */
+    #define portMUX_FREE_VAL                SPINLOCK_FREE           /**< Spinlock is free. [refactor-todo] check if this is still required */
+    #define portMUX_NO_TIMEOUT              SPINLOCK_WAIT_FOREVER   /**< When passed for 'timeout_cycles', spin forever if necessary. [refactor-todo] check if this is still required */
+    #define portMUX_TRY_LOCK                SPINLOCK_NO_WAIT        /**< Try to acquire the spinlock a single time only. [refactor-todo] check if this is still required */
+    #define portMUX_INITIALIZE( mux )    spinlock_initialize( mux ) /*< Initialize a spinlock to its unlocked state */
 
-    #define portCRITICAL_NESTING_IN_TCB    1
+    #define portCRITICAL_NESTING_IN_TCB     1
 
 /*
  * Modifications to portENTER_CRITICAL.
@@ -223,8 +224,8 @@
         }                                 \
     } while( 0 )
 
-    #define portASSERT_IF_IN_ISR()  vPortAssertIfInISR()
-    void vPortAssertIfInISR(void);
+    #define portASSERT_IF_IN_ISR()    vPortAssertIfInISR()
+    void vPortAssertIfInISR( void );
 
 /* Critical section management. NW-TODO: replace XTOS_SET_INTLEVEL with more efficient version, if any? */
 /* These cannot be nested. They should be used with a lot of care and cannot be called from interrupt level. */
@@ -239,6 +240,7 @@
     static inline UBaseType_t __attribute__( ( always_inline ) ) xPortSetInterruptMaskFromISR( void )
     {
         UBaseType_t prev_int_level = XTOS_SET_INTLEVEL( XCHAL_EXCM_LEVEL );
+
         portbenchmarkINTERRUPT_DISABLE();
         return prev_int_level;
     }
@@ -255,11 +257,11 @@
 
 /*Because the ROM routines don't necessarily handle a stack in external RAM correctly, we force */
 /*the stack memory to always be internal. */
-    #define portTcbMemoryCaps (MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT)
-    #define portStackMemoryCaps (MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT)
+    #define portTcbMemoryCaps      ( MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT )
+    #define portStackMemoryCaps    ( MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT )
 
-    #define pvPortMallocTcbMem(size) heap_caps_malloc(size, portTcbMemoryCaps)
-    #define pvPortMallocStackMem(size)  heap_caps_malloc(size, portStackMemoryCaps)
+    #define pvPortMallocTcbMem( size )        heap_caps_malloc( size, portTcbMemoryCaps )
+    #define pvPortMallocStackMem( size )      heap_caps_malloc( size, portStackMemoryCaps )
 
 /*xTaskCreateStatic uses these functions to check incoming memory. */
     #define portVALID_TCB_MEM( ptr )          ( esp_ptr_internal( ptr ) && esp_ptr_byte_accessible( ptr ) )
@@ -278,18 +280,18 @@
  * *bitwise inverse* of the old mem if the mem wasn't written. This doesn't seem to happen on the
  * ESP32 (portMUX assertions would fail).
  */
-        static inline void uxPortCompareSet( volatile uint32_t * addr,
-                                             uint32_t compare,
-                                             uint32_t * set )
-        {
-            #if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0))
+    static inline void uxPortCompareSet( volatile uint32_t * addr,
+                                         uint32_t compare,
+                                         uint32_t * set )
+    {
+        #if ( ESP_IDF_VERSION < ESP_IDF_VERSION_VAL( 4, 2, 0 ) )
             __asm__ __volatile__ (
                 "WSR       %2,SCOMPARE1 \n"
                 "S32C1I     %0, %1, 0   \n"
                 : "=r" ( *set )
                 : "r" ( addr ), "r" ( compare ), "0" ( *set )
                 );
-            #else
+        #else
             #if ( XCHAL_HAVE_S32C1I > 0 )
                 __asm__ __volatile__ (
                     "WSR        %2,SCOMPARE1 \n"
@@ -316,21 +318,23 @@
 
                 *set = old_value;
             #endif /* if ( XCHAL_HAVE_S32C1I > 0 ) */
-            #endif /* #if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0)) */
-        }
+        #endif /* #if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0)) */
+    }
 
-        #if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0))
+    #if ( ESP_IDF_VERSION < ESP_IDF_VERSION_VAL( 4, 2, 0 ) )
         void uxPortCompareSetExtram( volatile uint32_t * addr,
                                      uint32_t compare,
                                      uint32_t * set );
-        #else
-        static inline void uxPortCompareSetExtram(volatile uint32_t *addr, uint32_t compare, uint32_t *set)
+    #else
+        static inline void uxPortCompareSetExtram( volatile uint32_t * addr,
+                                                   uint32_t compare,
+                                                   uint32_t * set )
         {
-        #if defined(CONFIG_SPIRAM)
-            compare_and_set_extram(addr, compare, set);
-        #endif
+            #if defined( CONFIG_SPIRAM )
+                compare_and_set_extram( addr, compare, set );
+            #endif
         }
-        #endif
+    #endif /* if ( ESP_IDF_VERSION < ESP_IDF_VERSION_VAL( 4, 2, 0 ) ) */
 
 /*-----------------------------------------------------------*/
 
@@ -348,15 +352,17 @@
 
     #ifdef CONFIG_FREERTOS_RUN_TIME_STATS_USING_ESP_TIMER
 /* Coarse resolution time (us) */
-        #define portALT_GET_RUN_TIME_COUNTER_VALUE( x )     do { x = ( uint32_t )esp_timer_get_time(); } while( 0 )
+        #define portALT_GET_RUN_TIME_COUNTER_VALUE( x )    do { x = ( uint32_t ) esp_timer_get_time(); } while( 0 )
     #endif
 
 
 
 /* Kernel utilities. */
     void vPortYield( void );
-    void vPortEvaluateYieldFromISR( int argc, ... );
+    void vPortEvaluateYieldFromISR( int argc,
+                                    ... );
     void _frxt_setup_switch( void );
+
 /* Macro to count number of arguments of a __VA_ARGS__ used to support portYIELD_FROM_ISR with,
  * or without arguments. The macro counts only 0 or 1 arguments.
  *
@@ -366,26 +372,26 @@
  * This allows users to compile their code with standard C++20 enabled instead of the GNU extension.
  * Below C++20, we haven't found any good alternative to using ##__VA_ARGS__.
  */
-    #if defined( __cplusplus ) && ( __cplusplus >  201703L )
-    #define portGET_ARGUMENT_COUNT(...) portGET_ARGUMENT_COUNT_INNER( 0 __VA_OPT__(,) __VA_ARGS__, 1 , 0 )
+    #if defined( __cplusplus ) && ( __cplusplus > 201703L )
+        #define portGET_ARGUMENT_COUNT( ... )                        portGET_ARGUMENT_COUNT_INNER( 0 __VA_OPT__(, ) __VA_ARGS__, 1, 0 )
     #else
-    #define portGET_ARGUMENT_COUNT(...) portGET_ARGUMENT_COUNT_INNER( 0, ##__VA_ARGS__, 1, 0 )
+        #define portGET_ARGUMENT_COUNT( ... )                        portGET_ARGUMENT_COUNT_INNER( 0, ## __VA_ARGS__, 1, 0 )
     #endif
-    #define portGET_ARGUMENT_COUNT_INNER( zero, one, count, ... ) count
+    #define portGET_ARGUMENT_COUNT_INNER( zero, one, count, ... )    count
 
     _Static_assert( portGET_ARGUMENT_COUNT() == 0, "portGET_ARGUMENT_COUNT() result does not match for 0 arguments" );
     _Static_assert( portGET_ARGUMENT_COUNT( 1 ) == 1, "portGET_ARGUMENT_COUNT() result does not match for 1 argument" );
 
-    #define portYIELD() vPortYield()
+    #define portYIELD()    vPortYield()
 
 /* The macro below could be used when passing a single argument, or without any argument,
  * it was developed to support both usages of portYIELD inside of an ISR. Any other usage form
  * might result in undesired behaviour
  */
-    #if defined( __cplusplus ) && ( __cplusplus >  201703L )
-    #define portYIELD_FROM_ISR(...) vPortEvaluateYieldFromISR( portGET_ARGUMENT_COUNT( __VA_ARGS__ ) __VA_OPT__( , ) __VA_ARGS__ )
+    #if defined( __cplusplus ) && ( __cplusplus > 201703L )
+        #define portYIELD_FROM_ISR( ... )    vPortEvaluateYieldFromISR( portGET_ARGUMENT_COUNT( __VA_ARGS__ ) __VA_OPT__(, ) __VA_ARGS__ )
     #else
-    #define portYIELD_FROM_ISR(...) vPortEvaluateYieldFromISR( portGET_ARGUMENT_COUNT( __VA_ARGS__ ), ##__VA_ARGS__ )
+        #define portYIELD_FROM_ISR( ... )    vPortEvaluateYieldFromISR( portGET_ARGUMENT_COUNT( __VA_ARGS__ ), ## __VA_ARGS__ )
     #endif
 
     static inline BaseType_t xPortGetCoreID();
@@ -436,31 +442,31 @@
 
     void _xt_coproc_release( volatile void * coproc_sa_base );
 
-    /*-----------------------------------------------------------*/
+/*-----------------------------------------------------------*/
 
-    #if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0))
-    /* Architecture specific optimisations. */
+    #if ( ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL( 4, 2, 0 ) )
+        /* Architecture specific optimisations. */
 
-    #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+        #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
 
-    /* Check the configuration. */
-    #if( configMAX_PRIORITIES > 32 )
-        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
-    #endif
+/* Check the configuration. */
+            #if ( configMAX_PRIORITIES > 32 )
+                #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
+            #endif
 
-    /* Store/clear the ready priorities in a bit map. */
-    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+/* Store/clear the ready priorities in a bit map. */
+            #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+            #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 
-    /*-----------------------------------------------------------*/
+/*-----------------------------------------------------------*/
 
-    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __builtin_clz( ( uxReadyPriorities ) ) )
+            #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31 - __builtin_clz( ( uxReadyPriorities ) ) )
 
-    #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+        #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 
     #endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */
 
-    /*-----------------------------------------------------------*/
+/*-----------------------------------------------------------*/
 
 /*
  * Map to the memory management routines required for the port.
@@ -474,7 +480,8 @@
     #define xPortGetFreeHeapSize               esp_get_free_heap_size
     #define xPortGetMinimumEverFreeHeapSize    esp_get_minimum_free_heap_size
 
-#if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0))
+    #if ( ESP_IDF_VERSION < ESP_IDF_VERSION_VAL( 4, 2, 0 ) )
+
 /*
  * Send an interrupt to another core in order to make the task running
  * on it yield for a higher-priority task.
@@ -482,7 +489,7 @@
 
         void vPortYieldOtherCore( BaseType_t coreid ) PRIVILEGED_FUNCTION;
 
-#endif /* ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0) */
+    #endif /* ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0) */
 
 /*
  * Callback to set a watchpoint on the end of the stack. Called every context switch to change the stack
@@ -522,27 +529,27 @@
 /* Multi-core: get current core ID */
     static inline BaseType_t IRAM_ATTR xPortGetCoreID()
     {
-        return ( uint32_t )cpu_hal_get_core_id();
+        return ( uint32_t ) cpu_hal_get_core_id();
     }
 
 /* Get tick rate per second */
     uint32_t xPortGetTickRateHz( void );
 
-    static inline bool IRAM_ATTR xPortCanYield(void)
+    static inline bool IRAM_ATTR xPortCanYield( void )
     {
         uint32_t ps_reg = 0;
 
-        //Get the current value of PS (processor status) register
-        RSR(PS, ps_reg);
+        /*Get the current value of PS (processor status) register */
+        RSR( PS, ps_reg );
 
         /*
-        * intlevel = (ps_reg & 0xf);
-        * excm  = (ps_reg >> 4) & 0x1;
-        * CINTLEVEL is max(excm * EXCMLEVEL, INTLEVEL), where EXCMLEVEL is 3.
-        * However, just return true, only intlevel is zero.
-        */
+         * intlevel = (ps_reg & 0xf);
+         * excm  = (ps_reg >> 4) & 0x1;
+         * CINTLEVEL is max(excm * EXCMLEVEL, INTLEVEL), where EXCMLEVEL is 3.
+         * However, just return true, only intlevel is zero.
+         */
 
-        return ((ps_reg & PS_INTLEVEL_MASK) == 0);
+        return( ( ps_reg & PS_INTLEVEL_MASK ) == 0 );
     }
 
 /* porttrace */
diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/include/xt_asm_utils.h b/portable/ThirdParty/GCC/Xtensa_ESP32/include/xt_asm_utils.h
index ba31b9c26..9660e49a9 100644
--- a/portable/ThirdParty/GCC/Xtensa_ESP32/include/xt_asm_utils.h
+++ b/portable/ThirdParty/GCC/Xtensa_ESP32/include/xt_asm_utils.h
@@ -8,7 +8,7 @@
 
 /* File adapted to use on IDF FreeRTOS component, extracted
  * originally from zephyr RTOS code base:
- * https://github.com/zephyrproject-rtos/zephyr/blob/dafd348/arch/xtensa/include/xtensa-asm2-s.h
+ * https://github.com/zephyrproject-rtos/zephyr/blob/dafd3485bf67880e667b6e9a758b0b64fb688d63/arch/xtensa/include/xtensa-asm2-s.h
  */
 
 #ifndef __XT_ASM_UTILS_H
@@ -67,9 +67,9 @@
     rotw 3
     and a4, a4, a4
     rotw 2
-#else
-#error Unrecognized XCHAL_NUM_AREGS
-#endif
-.endm
+#else /* if XCHAL_NUM_AREGS == 64 */
+    #error Unrecognized XCHAL_NUM_AREGS
+#endif /* if XCHAL_NUM_AREGS == 64 */
+   .endm
 
-#endif
+#endif /* ifndef __XT_ASM_UTILS_H */
diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_api.h b/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_api.h
index 511a9da3d..a9069d798 100644
--- a/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_api.h
+++ b/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_api.h
@@ -5,6 +5,7 @@
  *
  * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD
  */
+
 /*
  * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
  *
diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_config.h b/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_config.h
index 78ef67da8..635e8647a 100644
--- a/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_config.h
+++ b/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_config.h
@@ -5,6 +5,7 @@
  *
  * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD
  */
+
 /*
  * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
  *
@@ -40,7 +41,7 @@
 *******************************************************************************/
 
 #ifndef XTENSA_CONFIG_H
-    #define XTENSA_CONFIG_H
+#define XTENSA_CONFIG_H
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
@@ -48,11 +49,11 @@
 #endif
 /* *INDENT-ON* */
 
-    #include <xtensa/hal.h>
-    #include <xtensa/config/core.h>
-    #include <xtensa/config/system.h> /* required for XSHAL_CLIB */
+#include <xtensa/hal.h>
+#include <xtensa/config/core.h>
+#include <xtensa/config/system.h> /* required for XSHAL_CLIB */
 
-    #include "xtensa_context.h"
+#include "xtensa_context.h"
 
 
 /*-----------------------------------------------------------------------------
@@ -105,27 +106,27 @@
  *  -----------------------------------------------------------------------------*/
 
 /* Extra space required for interrupt/exception hooks. */
-    #ifdef XT_INTEXC_HOOKS
-        #ifdef __XTENSA_CALL0_ABI__
-            #define STK_INTEXC_EXTRA     0x200
-        #else
-            #define STK_INTEXC_EXTRA     0x180
-        #endif
+#ifdef XT_INTEXC_HOOKS
+    #ifdef __XTENSA_CALL0_ABI__
+        #define STK_INTEXC_EXTRA     0x200
     #else
-        #define STK_INTEXC_EXTRA         0
+        #define STK_INTEXC_EXTRA     0x180
     #endif
+#else
+    #define STK_INTEXC_EXTRA         0
+#endif
 
-    #define XT_CLIB_CONTEXT_AREA_SIZE    0
+#define XT_CLIB_CONTEXT_AREA_SIZE    0
 
 /*------------------------------------------------------------------------------
  *  Extra size -- interrupt frame plus coprocessor save area plus hook space.
  *  NOTE: Make sure XT_INTEXC_HOOKS is undefined unless you really need the hooks.
  *  ------------------------------------------------------------------------------*/
-    #ifdef __XTENSA_CALL0_ABI__
-        #define XT_XTRA_SIZE    ( XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x10 + XT_CP_SIZE )
-    #else
-        #define XT_XTRA_SIZE    ( XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x20 + XT_CP_SIZE )
-    #endif
+#ifdef __XTENSA_CALL0_ABI__
+    #define XT_XTRA_SIZE    ( XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x10 + XT_CP_SIZE )
+#else
+    #define XT_XTRA_SIZE    ( XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x20 + XT_CP_SIZE )
+#endif
 
 /*------------------------------------------------------------------------------
  *  Space allocated for user code -- function calls and local variables.
@@ -135,18 +136,18 @@
  *  NOTE: The windowed ABI requires more stack, since space has to be reserved
  *  for spilling register windows.
  *  ------------------------------------------------------------------------------*/
-    #ifdef __XTENSA_CALL0_ABI__
-        #define XT_USER_SIZE    0x200
-    #else
-        #define XT_USER_SIZE    0x400
-    #endif
+#ifdef __XTENSA_CALL0_ABI__
+    #define XT_USER_SIZE    0x200
+#else
+    #define XT_USER_SIZE    0x400
+#endif
 
 /* Minimum recommended stack size. */
-    #define XT_STACK_MIN_SIZE      ( ( XT_XTRA_SIZE + XT_USER_SIZE ) / sizeof( unsigned char ) )
+#define XT_STACK_MIN_SIZE      ( ( XT_XTRA_SIZE + XT_USER_SIZE ) / sizeof( unsigned char ) )
 
 /* OS overhead with and without C library thread context. */
-    #define XT_STACK_EXTRA         ( XT_XTRA_SIZE )
-    #define XT_STACK_EXTRA_CLIB    ( XT_XTRA_SIZE + XT_CLIB_CONTEXT_AREA_SIZE )
+#define XT_STACK_EXTRA         ( XT_XTRA_SIZE )
+#define XT_STACK_EXTRA_CLIB    ( XT_XTRA_SIZE + XT_CLIB_CONTEXT_AREA_SIZE )
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_context.h b/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_context.h
index fc24748c4..56e6bf5c7 100644
--- a/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_context.h
+++ b/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_context.h
@@ -5,6 +5,7 @@
  *
  * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD
  */
+
 /*
  * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
  *
diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_rtos.h b/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_rtos.h
index 1f0c063b1..767e95052 100644
--- a/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_rtos.h
+++ b/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_rtos.h
@@ -5,6 +5,7 @@
  *
  * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD
  */
+
 /*
  * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
  *
@@ -60,6 +61,7 @@
 #include    <xtensa/corebits.h>
 #include    <xtensa/config/system.h>
 #include    "sdkconfig.h"
+
 /*
  * Include any RTOS specific definitions that are needed by this header.
  */
@@ -155,9 +157,9 @@
  */
 /* void XT_RTOS_TIMER_INT(void) */
 #ifdef CONFIG_FREERTOS_SYSTICK_USES_CCOUNT
-#define XT_RTOS_TIMER_INT   _frxt_timer_int
+    #define XT_RTOS_TIMER_INT    _frxt_timer_int
 #endif
-#define XT_TICK_PER_SEC      configTICK_RATE_HZ
+#define XT_TICK_PER_SEC          configTICK_RATE_HZ
 
 /*
  * Return in a15 the base address of the co-processor state save area for the
diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_timer.h b/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_timer.h
index 635ce1ffd..d046feac5 100644
--- a/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_timer.h
+++ b/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_timer.h
@@ -5,6 +5,7 @@
  *
  * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD
  */
+
 /*
  * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
  *
diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/port.c b/portable/ThirdParty/GCC/Xtensa_ESP32/port.c
index 4852cffa7..49139d71d 100644
--- a/portable/ThirdParty/GCC/Xtensa_ESP32/port.c
+++ b/portable/ThirdParty/GCC/Xtensa_ESP32/port.c
@@ -6,6 +6,7 @@
  *
  * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD
  */
+
 /*
  * FreeRTOS Kernel V10.4.3
  * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
@@ -33,6 +34,7 @@
  *
  * 1 tab == 4 spaces!
  */
+
 /*
  * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
  *
@@ -63,22 +65,22 @@
 #include "xtensa_rtos.h"
 #include "esp_idf_version.h"
 
-#if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0))
-#include "rom/ets_sys.h"
-#include "esp_panic.h"
-#include "esp_crosscore_int.h"
+#if ( ESP_IDF_VERSION < ESP_IDF_VERSION_VAL( 4, 2, 0 ) )
+    #include "rom/ets_sys.h"
+    #include "esp_panic.h"
+    #include "esp_crosscore_int.h"
 #else
-#if CONFIG_IDF_TARGET_ESP32S3
-    #include "esp32s3/rom/ets_sys.h"
-#elif CONFIG_IDF_TARGET_ESP32S2
-    #include "esp32s2/rom/ets_sys.h"
-#elif CONFIG_IDF_TARGET_ESP32
-    #include "esp32/rom/ets_sys.h"
-#endif
-#include "esp_private/panic_reason.h"
-#include "esp_debug_helpers.h"
-#include "esp_private/crosscore_int.h"
-#include "esp_log.h"
+    #if CONFIG_IDF_TARGET_ESP32S3
+        #include "esp32s3/rom/ets_sys.h"
+    #elif CONFIG_IDF_TARGET_ESP32S2
+        #include "esp32s2/rom/ets_sys.h"
+    #elif CONFIG_IDF_TARGET_ESP32
+        #include "esp32/rom/ets_sys.h"
+    #endif
+    #include "esp_private/panic_reason.h"
+    #include "esp_debug_helpers.h"
+    #include "esp_private/crosscore_int.h"
+    #include "esp_log.h"
 #endif /* ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0) */
 #include "soc/cpu.h"
 
@@ -94,12 +96,12 @@
 /* Defined in xtensa_context.S */
 extern void _xt_coproc_init( void );
 
-_Static_assert(tskNO_AFFINITY == CONFIG_FREERTOS_NO_AFFINITY, "incorrect tskNO_AFFINITY value");
+_Static_assert( tskNO_AFFINITY == CONFIG_FREERTOS_NO_AFFINITY, "incorrect tskNO_AFFINITY value" );
 
 /*-----------------------------------------------------------*/
 
-extern volatile int port_xSchedulerRunning[portNUM_PROCESSORS];
-unsigned port_interruptNesting[ portNUM_PROCESSORS ] = { 0 };  /* Interrupt nesting level. Increased/decreased in portasm.c, _frxt_int_enter/_frxt_int_exit */
+extern volatile int port_xSchedulerRunning[ portNUM_PROCESSORS ];
+unsigned port_interruptNesting[ portNUM_PROCESSORS ] = { 0 }; /* Interrupt nesting level. Increased/decreased in portasm.c, _frxt_int_enter/_frxt_int_exit */
 
 /*-----------------------------------------------------------*/
 
@@ -153,15 +155,15 @@ void _xt_user_exit( void );
     thread_local_sz = ALIGNUP( 0x10, thread_local_sz );
 
     /* Initialize task's stack so that we have the following structure at the top:
-
-        ----LOW ADDRESSES ----------------------------------------HIGH ADDRESSES----------
-         task stack | interrupt stack frame | thread local vars | co-processor save area |
-        ----------------------------------------------------------------------------------
-                    |                                                                    |
-                    SP                                                             pxTopOfStack
-
-        All parts are aligned to 16 byte boundary.
-    */
+     *
+     *  ----LOW ADDRESSES ----------------------------------------HIGH ADDRESSES----------
+     *   task stack | interrupt stack frame | thread local vars | co-processor save area |
+     *  ----------------------------------------------------------------------------------
+     |                                                                    |
+     |              SP                                                             pxTopOfStack
+     |
+     |  All parts are aligned to 16 byte boundary.
+     */
 
     /* Create interrupt stack frame aligned to 16 byte boundary */
     sp = ( StackType_t * ) ( ( ( UBaseType_t ) pxTopOfStack - XT_CP_SIZE - thread_local_sz - XT_STK_FRMSZ ) & ~0xf );
@@ -309,7 +311,7 @@ void vPortYieldOtherCore( BaseType_t coreid )
                                     uint32_t usStackDepth )
     {
         #if XCHAL_CP_NUM > 0
-            xMPUSettings->coproc_area = ( StackType_t * ) ( ( uint32_t ) ( pxBottomOfStack + usStackDepth - 1 ));
+            xMPUSettings->coproc_area = ( StackType_t * ) ( ( uint32_t ) ( pxBottomOfStack + usStackDepth - 1 ) );
             xMPUSettings->coproc_area = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) xMPUSettings->coproc_area ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) );
             xMPUSettings->coproc_area = ( StackType_t * ) ( ( ( uint32_t ) xMPUSettings->coproc_area - XT_CP_SIZE ) & ~0xf );
 
@@ -351,27 +353,29 @@ BaseType_t IRAM_ATTR xPortInterruptedFromISRContext()
     return( port_interruptNesting[ xPortGetCoreID() ] != 0 );
 }
 
-void IRAM_ATTR vPortEvaluateYieldFromISR( int argc, ... )
+void IRAM_ATTR vPortEvaluateYieldFromISR( int argc,
+                                          ... )
 {
     BaseType_t xYield;
     va_list ap;
+
     va_start( ap, argc );
 
     if( argc )
     {
-        xYield = ( BaseType_t )va_arg( ap, int );
+        xYield = ( BaseType_t ) va_arg( ap, int );
         va_end( ap );
     }
     else
     {
-        //it is a empty parameter vPortYieldFromISR macro call:
+        /*it is a empty parameter vPortYieldFromISR macro call: */
         va_end( ap );
         traceISR_EXIT_TO_SCHEDULER();
         _frxt_setup_switch();
         return;
     }
 
-    //Yield exists, so need evaluate it first then switch:
+    /*Yield exists, so need evaluate it first then switch: */
     if( xYield == pdTRUE )
     {
         traceISR_EXIT_TO_SCHEDULER();
@@ -477,8 +481,8 @@ void vPortCPUInitializeMutex( portMUX_TYPE * mux )
     }
 #endif /* ifdef CONFIG_FREERTOS_PORTMUX_DEBUG */
 
-#define STACK_WATCH_AREA_SIZE ( 32 )
-#define STACK_WATCH_POINT_NUMBER ( SOC_CPU_WATCHPOINTS_NUM - 1 )
+#define STACK_WATCH_AREA_SIZE       ( 32 )
+#define STACK_WATCH_POINT_NUMBER    ( SOC_CPU_WATCHPOINTS_NUM - 1 )
 
 void vPortSetStackWatchpoint( void * pxStackStart )
 {
@@ -491,48 +495,48 @@ void vPortSetStackWatchpoint( void * pxStackStart )
     int addr = ( int ) pxStackStart;
 
     addr = ( addr + 31 ) & ( ~31 );
-    esp_cpu_set_watchpoint( STACK_WATCH_POINT_NUMBER, (char*)addr, 32, ESP_WATCHPOINT_STORE );
+    esp_cpu_set_watchpoint( STACK_WATCH_POINT_NUMBER, ( char * ) addr, 32, ESP_WATCHPOINT_STORE );
 }
 
-#if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0))
+#if ( ESP_IDF_VERSION < ESP_IDF_VERSION_VAL( 4, 2, 0 ) )
 
-#if defined( CONFIG_SPIRAM_SUPPORT )
+    #if defined( CONFIG_SPIRAM_SUPPORT )
 
 /*
  * Compare & set (S32C1) does not work in external RAM. Instead, this routine uses a mux (in internal memory) to fake it.
  */
-    static portMUX_TYPE extram_mux = portMUX_INITIALIZER_UNLOCKED;
+        static portMUX_TYPE extram_mux = portMUX_INITIALIZER_UNLOCKED;
 
-    void uxPortCompareSetExtram( volatile uint32_t * addr,
-                                 uint32_t compare,
-                                 uint32_t * set )
-    {
-        uint32_t prev;
-
-        uint32_t oldlevel = portSET_INTERRUPT_MASK_FROM_ISR();
-
-        #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
-            vPortCPUAcquireMutexIntsDisabled( &extram_mux, portMUX_NO_TIMEOUT, __FUNCTION__, __LINE__ );
-        #else
-            vPortCPUAcquireMutexIntsDisabled( &extram_mux, portMUX_NO_TIMEOUT );
-        #endif
-        prev = *addr;
-
-        if( prev == compare )
+        void uxPortCompareSetExtram( volatile uint32_t * addr,
+                                     uint32_t compare,
+                                     uint32_t * set )
         {
-            *addr = *set;
+            uint32_t prev;
+
+            uint32_t oldlevel = portSET_INTERRUPT_MASK_FROM_ISR();
+
+            #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
+                vPortCPUAcquireMutexIntsDisabled( &extram_mux, portMUX_NO_TIMEOUT, __FUNCTION__, __LINE__ );
+            #else
+                vPortCPUAcquireMutexIntsDisabled( &extram_mux, portMUX_NO_TIMEOUT );
+            #endif
+            prev = *addr;
+
+            if( prev == compare )
+            {
+                *addr = *set;
+            }
+
+            *set = prev;
+            #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
+                vPortCPUReleaseMutexIntsDisabled( &extram_mux, __FUNCTION__, __LINE__ );
+            #else
+                vPortCPUReleaseMutexIntsDisabled( &extram_mux );
+            #endif
+
+            portCLEAR_INTERRUPT_MASK_FROM_ISR( oldlevel );
         }
-
-        *set = prev;
-        #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
-            vPortCPUReleaseMutexIntsDisabled( &extram_mux, __FUNCTION__, __LINE__ );
-        #else
-            vPortCPUReleaseMutexIntsDisabled( &extram_mux );
-        #endif
-
-        portCLEAR_INTERRUPT_MASK_FROM_ISR(oldlevel);
-    }
-#endif //defined(CONFIG_SPIRAM_SUPPORT)
+    #endif //defined(CONFIG_SPIRAM_SUPPORT)
 
 #endif /* ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0) */
 
@@ -542,27 +546,27 @@ uint32_t xPortGetTickRateHz( void )
     return ( uint32_t ) configTICK_RATE_HZ;
 }
 
-// For now, running FreeRTOS on one core and a bare metal on the other (or other OSes)
-// is not supported. For now CONFIG_FREERTOS_UNICORE and CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
-// should mirror each other's values.
-//
-// And since this should be true, we can just check for CONFIG_FREERTOS_UNICORE.
+/* For now, running FreeRTOS on one core and a bare metal on the other (or other OSes) */
+/* is not supported. For now CONFIG_FREERTOS_UNICORE and CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE */
+/* should mirror each other's values. */
+/* */
+/* And since this should be true, we can just check for CONFIG_FREERTOS_UNICORE. */
 #if CONFIG_FREERTOS_UNICORE != CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
     #error "FreeRTOS and system configuration mismatch regarding the use of multiple cores."
 #endif
 
-extern void esp_startup_start_app_common(void);
+extern void esp_startup_start_app_common( void );
 
-void esp_startup_start_app(void)
+void esp_startup_start_app( void )
 {
-#if !CONFIG_ESP_INT_WDT
-#if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
-    assert(!soc_has_cache_lock_bug() && "ESP32 Rev 3 + Dual Core + PSRAM requires INT WDT enabled in project config!");
-#endif
-#endif
+    #if !CONFIG_ESP_INT_WDT
+        #if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
+            assert( !soc_has_cache_lock_bug() && "ESP32 Rev 3 + Dual Core + PSRAM requires INT WDT enabled in project config!" );
+        #endif
+    #endif
 
     esp_startup_start_app_common();
 
-    ESP_LOGI("cpu_start", "Starting scheduler on PRO CPU.");
+    ESP_LOGI( "cpu_start", "Starting scheduler on PRO CPU." );
     vTaskStartScheduler();
 }
diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/port_common.c b/portable/ThirdParty/GCC/Xtensa_ESP32/port_common.c
index 11f119bcd..cd8193a89 100644
--- a/portable/ThirdParty/GCC/Xtensa_ESP32/port_common.c
+++ b/portable/ThirdParty/GCC/Xtensa_ESP32/port_common.c
@@ -14,7 +14,7 @@
 #include "esp_task_wdt.h"
 #include "esp_task.h"
 #include "esp_private/crosscore_int.h"
-#include "esp_private/startup_internal.h"    /* Required by g_spiram_ok. [refactor-todo] for g_spiram_ok */
+#include "esp_private/startup_internal.h" /* Required by g_spiram_ok. [refactor-todo] for g_spiram_ok */
 #include "esp_log.h"
 #include "soc/soc_memory_types.h"
 #include "soc/dport_access.h"
@@ -22,17 +22,17 @@
 #include "esp_freertos_hooks.h"
 
 #if CONFIG_IDF_TARGET_ESP32
-#include "esp32/spiram.h"
+    #include "esp32/spiram.h"
 #elif CONFIG_IDF_TARGET_ESP32S2
-#include "esp32s2/spiram.h"
+    #include "esp32s2/spiram.h"
 #elif CONFIG_IDF_TARGET_ESP32S3
-#include "esp32s3/spiram.h"
+    #include "esp32s3/spiram.h"
 #elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
-// SPIRAM is not supported on ESP32-C3
+/* SPIRAM is not supported on ESP32-C3 */
 #endif
 
 #if CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL
-static const char* TAG = "cpu_start";
+    static const char * TAG = "cpu_start";
 #endif
 
 /* Architecture-agnostic parts of the FreeRTOS ESP-IDF port layer can go here.
@@ -41,119 +41,127 @@ static const char* TAG = "cpu_start";
  * which will then call esp_startup_start_app_common()
  */
 
-// Duplicate of inaccessible xSchedulerRunning; needed at startup to avoid counting nesting
-volatile unsigned port_xSchedulerRunning[portNUM_PROCESSORS] = {0};
+/* Duplicate of inaccessible xSchedulerRunning; needed at startup to avoid counting nesting */
+volatile unsigned port_xSchedulerRunning[ portNUM_PROCESSORS ] = { 0 };
 
-// For now, running FreeRTOS on one core and a bare metal on the other (or other OSes)
-// is not supported. For now CONFIG_FREERTOS_UNICORE and CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
-// should mirror each other's values.
-//
-// And since this should be true, we can just check for CONFIG_FREERTOS_UNICORE.
+/* For now, running FreeRTOS on one core and a bare metal on the other (or other OSes) */
+/* is not supported. For now CONFIG_FREERTOS_UNICORE and CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE */
+/* should mirror each other's values. */
+/* */
+/* And since this should be true, we can just check for CONFIG_FREERTOS_UNICORE. */
 #if CONFIG_FREERTOS_UNICORE != CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
     #error "FreeRTOS and system configuration mismatch regarding the use of multiple cores."
 #endif
 
-static void main_task(void* args);
+static void main_task( void * args );
 
 #ifdef CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
-void esp_gdbstub_init(void);
+    void esp_gdbstub_init( void );
 #endif // CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
 
-extern void app_main(void);
+extern void app_main( void );
 
-void esp_startup_start_app_common(void)
+void esp_startup_start_app_common( void )
 {
-#if CONFIG_ESP_INT_WDT
-    esp_int_wdt_init();
-    //Initialize the interrupt watch dog for CPU0.
-    esp_int_wdt_cpu_init();
-#endif
+    #if CONFIG_ESP_INT_WDT
+        esp_int_wdt_init();
+        /*Initialize the interrupt watch dog for CPU0. */
+        esp_int_wdt_cpu_init();
+    #endif
 
     esp_crosscore_int_init();
 
-#ifdef CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
-    esp_gdbstub_init();
-#endif // CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
+    #ifdef CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
+        esp_gdbstub_init();
+    #endif // CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
 
-    portBASE_TYPE res = xTaskCreatePinnedToCore(&main_task, "main",
-                                                ESP_TASK_MAIN_STACK, NULL,
-                                                ESP_TASK_MAIN_PRIO, NULL, ESP_TASK_MAIN_CORE);
-    assert(res == pdTRUE);
-    (void)res;
+    portBASE_TYPE res = xTaskCreatePinnedToCore( &main_task, "main",
+                                                 ESP_TASK_MAIN_STACK, NULL,
+                                                 ESP_TASK_MAIN_PRIO, NULL, ESP_TASK_MAIN_CORE );
+    assert( res == pdTRUE );
+    ( void ) res;
 }
 
 #if !CONFIG_FREERTOS_UNICORE
-static volatile bool s_other_cpu_startup_done = false;
-static bool other_cpu_startup_idle_hook_cb(void)
-{
-    s_other_cpu_startup_done = true;
-    return true;
-}
-#endif
-
-static void main_task(void* args)
-{
-#if !CONFIG_FREERTOS_UNICORE
-    // Wait for FreeRTOS initialization to finish on other core, before replacing its startup stack
-    esp_register_freertos_idle_hook_for_cpu(other_cpu_startup_idle_hook_cb, !xPortGetCoreID());
-    while (!s_other_cpu_startup_done) {
-        ;
+    static volatile bool s_other_cpu_startup_done = false;
+    static bool other_cpu_startup_idle_hook_cb( void )
+    {
+        s_other_cpu_startup_done = true;
+        return true;
     }
-    esp_deregister_freertos_idle_hook_for_cpu(other_cpu_startup_idle_hook_cb, !xPortGetCoreID());
 #endif
 
-    // [refactor-todo] check if there is a way to move the following block to esp_system startup
+static void main_task( void * args )
+{
+    #if !CONFIG_FREERTOS_UNICORE
+        /* Wait for FreeRTOS initialization to finish on other core, before replacing its startup stack */
+        esp_register_freertos_idle_hook_for_cpu( other_cpu_startup_idle_hook_cb, !xPortGetCoreID() );
+
+        while( !s_other_cpu_startup_done )
+        {
+        }
+        esp_deregister_freertos_idle_hook_for_cpu( other_cpu_startup_idle_hook_cb, !xPortGetCoreID() );
+    #endif
+
+    /* [refactor-todo] check if there is a way to move the following block to esp_system startup */
     heap_caps_enable_nonos_stack_heaps();
 
-    // Now we have startup stack RAM available for heap, enable any DMA pool memory
-#if CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL
-    if (g_spiram_ok) {
-        esp_err_t r = esp_spiram_reserve_dma_pool(CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL);
-        if (r != ESP_OK) {
-            ESP_EARLY_LOGE(TAG, "Could not reserve internal/DMA pool (error 0x%x)", r);
-            abort();
+    /* Now we have startup stack RAM available for heap, enable any DMA pool memory */
+    #if CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL
+        if( g_spiram_ok )
+        {
+            esp_err_t r = esp_spiram_reserve_dma_pool( CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL );
+
+            if( r != ESP_OK )
+            {
+                ESP_EARLY_LOGE( TAG, "Could not reserve internal/DMA pool (error 0x%x)", r );
+                abort();
+            }
         }
-    }
-#endif
+    #endif /* if CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL */
 
-    //Initialize task wdt if configured to do so
-#ifdef CONFIG_ESP_TASK_WDT_PANIC
-    ESP_ERROR_CHECK(esp_task_wdt_init(CONFIG_ESP_TASK_WDT_TIMEOUT_S, true));
-#elif CONFIG_ESP_TASK_WDT
-    ESP_ERROR_CHECK(esp_task_wdt_init(CONFIG_ESP_TASK_WDT_TIMEOUT_S, false));
-#endif
+    /*Initialize task wdt if configured to do so */
+    #ifdef CONFIG_ESP_TASK_WDT_PANIC
+        ESP_ERROR_CHECK( esp_task_wdt_init( CONFIG_ESP_TASK_WDT_TIMEOUT_S, true ) );
+    #elif CONFIG_ESP_TASK_WDT
+        ESP_ERROR_CHECK( esp_task_wdt_init( CONFIG_ESP_TASK_WDT_TIMEOUT_S, false ) );
+    #endif
 
-    //Add IDLE 0 to task wdt
-#ifdef CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0
-    TaskHandle_t idle_0 = xTaskGetIdleTaskHandleForCPU(0);
-    if(idle_0 != NULL){
-        ESP_ERROR_CHECK(esp_task_wdt_add(idle_0));
-    }
-#endif
-    //Add IDLE 1 to task wdt
-#ifdef CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1
-    TaskHandle_t idle_1 = xTaskGetIdleTaskHandleForCPU(1);
-    if(idle_1 != NULL){
-        ESP_ERROR_CHECK(esp_task_wdt_add(idle_1));
-    }
-#endif
+    /*Add IDLE 0 to task wdt */
+    #ifdef CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0
+        TaskHandle_t idle_0 = xTaskGetIdleTaskHandleForCPU( 0 );
+
+        if( idle_0 != NULL )
+        {
+            ESP_ERROR_CHECK( esp_task_wdt_add( idle_0 ) );
+        }
+    #endif
+    /*Add IDLE 1 to task wdt */
+    #ifdef CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1
+        TaskHandle_t idle_1 = xTaskGetIdleTaskHandleForCPU( 1 );
+
+        if( idle_1 != NULL )
+        {
+            ESP_ERROR_CHECK( esp_task_wdt_add( idle_1 ) );
+        }
+    #endif
 
     app_main();
-    vTaskDelete(NULL);
+    vTaskDelete( NULL );
 }
 
-// -------------------- Heap Related -----------------------
+/* -------------------- Heap Related ----------------------- */
 
-bool xPortCheckValidTCBMem(const void *ptr)
+bool xPortCheckValidTCBMem( const void * ptr )
 {
-    return esp_ptr_internal(ptr) && esp_ptr_byte_accessible(ptr);
+    return esp_ptr_internal( ptr ) && esp_ptr_byte_accessible( ptr );
 }
 
-bool xPortcheckValidStackMem(const void *ptr)
+bool xPortcheckValidStackMem( const void * ptr )
 {
-#ifdef CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
-    return esp_ptr_byte_accessible(ptr);
-#else
-    return esp_ptr_internal(ptr) && esp_ptr_byte_accessible(ptr);
-#endif
+    #ifdef CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
+        return esp_ptr_byte_accessible( ptr );
+    #else
+        return esp_ptr_internal( ptr ) && esp_ptr_byte_accessible( ptr );
+    #endif
 }
diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/port_systick.c b/portable/ThirdParty/GCC/Xtensa_ESP32/port_systick.c
index a9f437c61..69d8e9a03 100644
--- a/portable/ThirdParty/GCC/Xtensa_ESP32/port_systick.c
+++ b/portable/ThirdParty/GCC/Xtensa_ESP32/port_systick.c
@@ -14,51 +14,51 @@
 #include "esp_log.h"
 #include "sdkconfig.h"
 #ifdef CONFIG_FREERTOS_SYSTICK_USES_SYSTIMER
-#include "soc/periph_defs.h"
-#include "soc/system_reg.h"
-#include "hal/systimer_hal.h"
-#include "hal/systimer_ll.h"
+    #include "soc/periph_defs.h"
+    #include "soc/system_reg.h"
+    #include "hal/systimer_hal.h"
+    #include "hal/systimer_ll.h"
 #endif
 
 #ifdef CONFIG_PM_TRACE
-#include "esp_private/pm_trace.h"
+    #include "esp_private/pm_trace.h"
 #endif //CONFIG_PM_TRACE
 
-BaseType_t xPortSysTickHandler(void);
+BaseType_t xPortSysTickHandler( void );
 
 #ifdef CONFIG_FREERTOS_SYSTICK_USES_CCOUNT
-extern void _frxt_tick_timer_init(void);
-extern void _xt_tick_divisor_init(void);
+    extern void _frxt_tick_timer_init( void );
+    extern void _xt_tick_divisor_init( void );
 
-#ifdef CONFIG_FREERTOS_CORETIMER_0
-    #define SYSTICK_INTR_ID (ETS_INTERNAL_TIMER0_INTR_SOURCE+ETS_INTERNAL_INTR_SOURCE_OFF)
-#endif
-#ifdef CONFIG_FREERTOS_CORETIMER_1
-    #define SYSTICK_INTR_ID (ETS_INTERNAL_TIMER1_INTR_SOURCE+ETS_INTERNAL_INTR_SOURCE_OFF)
-#endif
+    #ifdef CONFIG_FREERTOS_CORETIMER_0
+        #define SYSTICK_INTR_ID    ( ETS_INTERNAL_TIMER0_INTR_SOURCE + ETS_INTERNAL_INTR_SOURCE_OFF )
+    #endif
+    #ifdef CONFIG_FREERTOS_CORETIMER_1
+        #define SYSTICK_INTR_ID    ( ETS_INTERNAL_TIMER1_INTR_SOURCE + ETS_INTERNAL_INTR_SOURCE_OFF )
+    #endif
 
 /**
  * @brief Initialize CCONT timer to generate the tick interrupt
  *
  */
-void vPortSetupTimer(void)
-{
-    /* Init the tick divisor value */
-    _xt_tick_divisor_init();
+    void vPortSetupTimer( void )
+    {
+        /* Init the tick divisor value */
+        _xt_tick_divisor_init();
 
-    _frxt_tick_timer_init();
-}
+        _frxt_tick_timer_init();
+    }
 
 
 #elif CONFIG_FREERTOS_SYSTICK_USES_SYSTIMER
 
-_Static_assert(SOC_CPU_CORES_NUM <= SOC_SYSTIMER_ALARM_NUM - 1, "the number of cores must match the number of core alarms in SYSTIMER");
+    _Static_assert( SOC_CPU_CORES_NUM <= SOC_SYSTIMER_ALARM_NUM - 1, "the number of cores must match the number of core alarms in SYSTIMER" );
 
-void SysTickIsrHandler(void *arg);
+    void SysTickIsrHandler( void * arg );
 
-static uint32_t s_handled_systicks[portNUM_PROCESSORS] = { 0 };
+    static uint32_t s_handled_systicks[ portNUM_PROCESSORS ] = { 0 };
 
-#define SYSTICK_INTR_ID (ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE)
+    #define SYSTICK_INTR_ID    ( ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE )
 
 /**
  * @brief Set up the systimer peripheral to generate the tick interrupt
@@ -67,50 +67,58 @@ static uint32_t s_handled_systicks[portNUM_PROCESSORS] = { 0 };
  * It is done at the same time so SysTicks for both CPUs occur at the same time or very close.
  * Shifts a time of triggering interrupts for core 0 and core 1.
  */
-void vPortSetupTimer(void)
-{
-    unsigned cpuid = xPortGetCoreID();
-#ifdef CONFIG_FREERTOS_CORETIMER_SYSTIMER_LVL3
-    const unsigned level = ESP_INTR_FLAG_LEVEL3;
-#else
-    const unsigned level = ESP_INTR_FLAG_LEVEL1;
-#endif
-    /* Systimer HAL layer object */
-    static systimer_hal_context_t systimer_hal;
-    /* set system timer interrupt vector */
-    ESP_ERROR_CHECK(esp_intr_alloc(ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE + cpuid, ESP_INTR_FLAG_IRAM | level, SysTickIsrHandler, &systimer_hal, NULL));
+    void vPortSetupTimer( void )
+    {
+        unsigned cpuid = xPortGetCoreID();
 
-    if (cpuid == 0) {
-        systimer_hal_init(&systimer_hal);
-        systimer_ll_set_counter_value(systimer_hal.dev, SYSTIMER_LL_COUNTER_OS_TICK, 0);
-        systimer_ll_apply_counter_value(systimer_hal.dev, SYSTIMER_LL_COUNTER_OS_TICK);
+        #ifdef CONFIG_FREERTOS_CORETIMER_SYSTIMER_LVL3
+            const unsigned level = ESP_INTR_FLAG_LEVEL3;
+        #else
+            const unsigned level = ESP_INTR_FLAG_LEVEL1;
+        #endif
+        /* Systimer HAL layer object */
+        static systimer_hal_context_t systimer_hal;
+        /* set system timer interrupt vector */
+        ESP_ERROR_CHECK( esp_intr_alloc( ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE + cpuid, ESP_INTR_FLAG_IRAM | level, SysTickIsrHandler, &systimer_hal, NULL ) );
 
-        for (cpuid = 0; cpuid < SOC_CPU_CORES_NUM; cpuid++) {
-            systimer_hal_counter_can_stall_by_cpu(&systimer_hal, SYSTIMER_LL_COUNTER_OS_TICK, cpuid, false);
-        }
+        if( cpuid == 0 )
+        {
+            systimer_hal_init( &systimer_hal );
+            systimer_ll_set_counter_value( systimer_hal.dev, SYSTIMER_LL_COUNTER_OS_TICK, 0 );
+            systimer_ll_apply_counter_value( systimer_hal.dev, SYSTIMER_LL_COUNTER_OS_TICK );
 
-        for (cpuid = 0; cpuid < portNUM_PROCESSORS; ++cpuid) {
-            uint32_t alarm_id = SYSTIMER_LL_ALARM_OS_TICK_CORE0 + cpuid;
+            for( cpuid = 0; cpuid < SOC_CPU_CORES_NUM; cpuid++ )
+            {
+                systimer_hal_counter_can_stall_by_cpu( &systimer_hal, SYSTIMER_LL_COUNTER_OS_TICK, cpuid, false );
+            }
 
-            /* configure the timer */
-            systimer_hal_connect_alarm_counter(&systimer_hal, alarm_id, SYSTIMER_LL_COUNTER_OS_TICK);
-            systimer_hal_set_alarm_period(&systimer_hal, alarm_id, 1000000UL / CONFIG_FREERTOS_HZ);
-            systimer_hal_select_alarm_mode(&systimer_hal, alarm_id, SYSTIMER_ALARM_MODE_PERIOD);
-            systimer_hal_counter_can_stall_by_cpu(&systimer_hal, SYSTIMER_LL_COUNTER_OS_TICK, cpuid, true);
-            if (cpuid == 0) {
-                systimer_hal_enable_alarm_int(&systimer_hal, alarm_id);
-                systimer_hal_enable_counter(&systimer_hal, SYSTIMER_LL_COUNTER_OS_TICK);
-#ifndef CONFIG_FREERTOS_UNICORE
-                // SysTick of core 0 and core 1 are shifted by half of period
-                systimer_hal_counter_value_advance(&systimer_hal, SYSTIMER_LL_COUNTER_OS_TICK, 1000000UL / CONFIG_FREERTOS_HZ / 2);
-#endif
+            for( cpuid = 0; cpuid < portNUM_PROCESSORS; ++cpuid )
+            {
+                uint32_t alarm_id = SYSTIMER_LL_ALARM_OS_TICK_CORE0 + cpuid;
+
+                /* configure the timer */
+                systimer_hal_connect_alarm_counter( &systimer_hal, alarm_id, SYSTIMER_LL_COUNTER_OS_TICK );
+                systimer_hal_set_alarm_period( &systimer_hal, alarm_id, 1000000UL / CONFIG_FREERTOS_HZ );
+                systimer_hal_select_alarm_mode( &systimer_hal, alarm_id, SYSTIMER_ALARM_MODE_PERIOD );
+                systimer_hal_counter_can_stall_by_cpu( &systimer_hal, SYSTIMER_LL_COUNTER_OS_TICK, cpuid, true );
+
+                if( cpuid == 0 )
+                {
+                    systimer_hal_enable_alarm_int( &systimer_hal, alarm_id );
+                    systimer_hal_enable_counter( &systimer_hal, SYSTIMER_LL_COUNTER_OS_TICK );
+                    #ifndef CONFIG_FREERTOS_UNICORE
+                        /* SysTick of core 0 and core 1 are shifted by half of period */
+                        systimer_hal_counter_value_advance( &systimer_hal, SYSTIMER_LL_COUNTER_OS_TICK, 1000000UL / CONFIG_FREERTOS_HZ / 2 );
+                    #endif
+                }
             }
         }
-    } else {
-        uint32_t alarm_id = SYSTIMER_LL_ALARM_OS_TICK_CORE0 + cpuid;
-        systimer_hal_enable_alarm_int(&systimer_hal, alarm_id);
+        else
+        {
+            uint32_t alarm_id = SYSTIMER_LL_ALARM_OS_TICK_CORE0 + cpuid;
+            systimer_hal_enable_alarm_int( &systimer_hal, alarm_id );
+        }
     }
-}
 
 /**
  * @brief Systimer interrupt handler.
@@ -118,37 +126,46 @@ void vPortSetupTimer(void)
  * The Systimer interrupt for SysTick works in periodic mode no need to calc the next alarm.
  * If a timer interrupt is ever serviced more than one tick late, it is necessary to process multiple ticks.
  */
-IRAM_ATTR void SysTickIsrHandler(void *arg)
-{
-    uint32_t cpuid = xPortGetCoreID();
-    systimer_hal_context_t *systimer_hal = (systimer_hal_context_t *)arg;
-#ifdef CONFIG_PM_TRACE
-    ESP_PM_TRACE_ENTER(TICK, cpuid);
-#endif
+    IRAM_ATTR void SysTickIsrHandler( void * arg )
+    {
+        uint32_t cpuid = xPortGetCoreID();
+        systimer_hal_context_t * systimer_hal = ( systimer_hal_context_t * ) arg;
 
-    uint32_t alarm_id = SYSTIMER_LL_ALARM_OS_TICK_CORE0 + cpuid;
-    do {
-        systimer_ll_clear_alarm_int(systimer_hal->dev, alarm_id);
+        #ifdef CONFIG_PM_TRACE
+            ESP_PM_TRACE_ENTER( TICK, cpuid );
+        #endif
 
-        uint32_t diff = systimer_hal_get_counter_value(systimer_hal, SYSTIMER_LL_COUNTER_OS_TICK) / systimer_ll_get_alarm_period(systimer_hal->dev, alarm_id) - s_handled_systicks[cpuid];
-        if (diff > 0) {
-            if (s_handled_systicks[cpuid] == 0) {
-                s_handled_systicks[cpuid] = diff;
-                diff = 1;
-            } else {
-                s_handled_systicks[cpuid] += diff;
+        uint32_t alarm_id = SYSTIMER_LL_ALARM_OS_TICK_CORE0 + cpuid;
+
+        do
+        {
+            systimer_ll_clear_alarm_int( systimer_hal->dev, alarm_id );
+
+            uint32_t diff = systimer_hal_get_counter_value( systimer_hal, SYSTIMER_LL_COUNTER_OS_TICK ) / systimer_ll_get_alarm_period( systimer_hal->dev, alarm_id ) - s_handled_systicks[ cpuid ];
+
+            if( diff > 0 )
+            {
+                if( s_handled_systicks[ cpuid ] == 0 )
+                {
+                    s_handled_systicks[ cpuid ] = diff;
+                    diff = 1;
+                }
+                else
+                {
+                    s_handled_systicks[ cpuid ] += diff;
+                }
+
+                do
+                {
+                    xPortSysTickHandler();
+                } while( --diff );
             }
+        } while( systimer_ll_is_alarm_int_fired( systimer_hal->dev, alarm_id ) );
 
-            do {
-                xPortSysTickHandler();
-            } while (--diff);
-        }
-    } while (systimer_ll_is_alarm_int_fired(systimer_hal->dev, alarm_id));
-
-#ifdef CONFIG_PM_TRACE
-    ESP_PM_TRACE_EXIT(TICK, cpuid);
-#endif
-}
+        #ifdef CONFIG_PM_TRACE
+            ESP_PM_TRACE_EXIT( TICK, cpuid );
+        #endif
+    }
 
 #endif // CONFIG_FREERTOS_SYSTICK_USES_CCOUNT
 
@@ -160,15 +177,20 @@ IRAM_ATTR void SysTickIsrHandler(void *arg)
  *  - SysTickIsrHandler for xtensa with CONFIG_FREERTOS_SYSTICK_USES_SYSTIMER
  *  - SysTickIsrHandler for riscv
  */
-BaseType_t xPortSysTickHandler(void)
+BaseType_t xPortSysTickHandler( void )
 {
     portbenchmarkIntLatency();
-    traceISR_ENTER(SYSTICK_INTR_ID);
+    traceISR_ENTER( SYSTICK_INTR_ID );
     BaseType_t ret = xTaskIncrementTick();
-    if(ret != pdFALSE) {
+
+    if( ret != pdFALSE )
+    {
         portYIELD_FROM_ISR();
-    } else {
+    }
+    else
+    {
         traceISR_EXIT();
     }
+
     return ret;
 }
diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/portmux_impl.h b/portable/ThirdParty/GCC/Xtensa_ESP32/portmux_impl.h
index 98d924f40..b9a4fa508 100644
--- a/portable/ThirdParty/GCC/Xtensa_ESP32/portmux_impl.h
+++ b/portable/ThirdParty/GCC/Xtensa_ESP32/portmux_impl.h
@@ -31,10 +31,10 @@
 #include "portable.h"
 
 /* XOR one core ID with this value to get the other core ID */
-#if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0))
-#define CORE_ID_XOR_SWAP    ( CORE_ID_PRO ^ CORE_ID_APP )
+#if ( ESP_IDF_VERSION < ESP_IDF_VERSION_VAL( 4, 2, 0 ) )
+    #define CORE_ID_XOR_SWAP           ( CORE_ID_PRO ^ CORE_ID_APP )
 #else
-#define CORE_ID_REGVAL_XOR_SWAP (CORE_ID_REGVAL_PRO ^ CORE_ID_REGVAL_APP)
+    #define CORE_ID_REGVAL_XOR_SWAP    ( CORE_ID_REGVAL_PRO ^ CORE_ID_REGVAL_APP )
 #endif
 
 
diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/portmux_impl.inc.h b/portable/ThirdParty/GCC/Xtensa_ESP32/portmux_impl.inc.h
index 9d7c826ec..37ca2fd0b 100644
--- a/portable/ThirdParty/GCC/Xtensa_ESP32/portmux_impl.inc.h
+++ b/portable/ThirdParty/GCC/Xtensa_ESP32/portmux_impl.inc.h
@@ -53,16 +53,16 @@ static inline bool __attribute__( ( always_inline ) )
             #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
                 uint32_t owner = mux->owner;
 
-                #if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0))
-                if( ( owner != portMUX_FREE_VAL ) && ( owner != CORE_ID_PRO ) && ( owner != CORE_ID_APP ) )
+                #if ( ESP_IDF_VERSION < ESP_IDF_VERSION_VAL( 4, 2, 0 ) )
+                    if( ( owner != portMUX_FREE_VAL ) && ( owner != CORE_ID_PRO ) && ( owner != CORE_ID_APP ) )
                 #else
-                if (owner != portMUX_FREE_VAL && owner != CORE_ID_REGVAL_PRO && owner != CORE_ID_REGVAL_APP)
+                    if( ( owner != portMUX_FREE_VAL ) && ( owner != CORE_ID_REGVAL_PRO ) && ( owner != CORE_ID_REGVAL_APP ) )
                 #endif
                 {
                     ets_printf( "ERROR: vPortCPUAcquireMutex: mux %p is uninitialized (0x%X)! Called from %s line %d.\n", mux, owner, fnName, line );
                     mux->owner = portMUX_FREE_VAL;
                 }
-            #endif
+            #endif /* ifdef CONFIG_FREERTOS_PORTMUX_DEBUG */
 
             /* Spin until we own the core */
 
@@ -71,10 +71,10 @@ static inline bool __attribute__( ( always_inline ) )
             /* Note: coreID is the full 32 bit core ID (CORE_ID_PRO/CORE_ID_APP),
              * not the 0/1 value returned by xPortGetCoreID()
              */
-            #if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0))
-            otherCoreID = CORE_ID_XOR_SWAP ^ coreID;
+            #if ( ESP_IDF_VERSION < ESP_IDF_VERSION_VAL( 4, 2, 0 ) )
+                otherCoreID = CORE_ID_XOR_SWAP ^ coreID;
             #else
-            otherCoreID = CORE_ID_REGVAL_XOR_SWAP ^ coreID;
+                otherCoreID = CORE_ID_REGVAL_XOR_SWAP ^ coreID;
             #endif
 
             do
@@ -154,10 +154,10 @@ static inline bool __attribute__( ( always_inline ) )
                     mux->lastLockedLine = line;
                     uint32_t owner = mux->owner;
 
-                    #if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0))
-                    if( ( owner != portMUX_FREE_VAL ) && ( owner != CORE_ID_PRO ) && ( owner != CORE_ID_APP ) )
+                    #if ( ESP_IDF_VERSION < ESP_IDF_VERSION_VAL( 4, 2, 0 ) )
+                        if( ( owner != portMUX_FREE_VAL ) && ( owner != CORE_ID_PRO ) && ( owner != CORE_ID_APP ) )
                     #else
-                    if (owner != portMUX_FREE_VAL && owner != CORE_ID_REGVAL_PRO && owner != CORE_ID_REGVAL_APP)
+                        if( ( owner != portMUX_FREE_VAL ) && ( owner != CORE_ID_REGVAL_PRO ) && ( owner != CORE_ID_REGVAL_APP ) )
                     #endif
                     {
                         ets_printf( "ERROR: vPortCPUReleaseMutex: mux %p is invalid (0x%x)!\n", mux, mux->owner );
diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_init.c b/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_init.c
index e7275c623..fbdd95fc5 100644
--- a/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_init.c
+++ b/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_init.c
@@ -5,6 +5,7 @@
  *
  * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD
  */
+
 /*
  * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
  *
@@ -39,37 +40,37 @@
 
 
 #ifdef XT_BOARD
-#include "xtensa/xtbsp.h"
+    #include "xtensa/xtbsp.h"
 #endif
 
 #include "xtensa_rtos.h"
 #include "sdkconfig.h"
 #include "esp_idf_version.h"
-#if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0))
-#include    "esp_clk.h"
+#if ( ESP_IDF_VERSION < ESP_IDF_VERSION_VAL( 4, 2, 0 ) )
+    #include    "esp_clk.h"
 #else
-#if CONFIG_IDF_TARGET_ESP32
-#include "esp32/clk.h"
-#elif CONFIG_IDF_TARGET_ESP32S2
-#include "esp32s2/clk.h"
-#elif CONFIG_IDF_TARGET_ESP32S3
-#include "esp32s3/clk.h"
-#endif
+    #if CONFIG_IDF_TARGET_ESP32
+        #include "esp32/clk.h"
+    #elif CONFIG_IDF_TARGET_ESP32S2
+        #include "esp32s2/clk.h"
+    #elif CONFIG_IDF_TARGET_ESP32S3
+        #include "esp32s3/clk.h"
+    #endif
 #endif /* ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0) */
 
 #ifdef XT_RTOS_TIMER_INT
 
-unsigned _xt_tick_divisor = 0;  /* cached number of cycles per tick */
+    unsigned _xt_tick_divisor = 0; /* cached number of cycles per tick */
 
-void _xt_tick_divisor_init(void)
-{
-    _xt_tick_divisor = esp_clk_cpu_freq() / XT_TICK_PER_SEC;
-}
+    void _xt_tick_divisor_init( void )
+    {
+        _xt_tick_divisor = esp_clk_cpu_freq() / XT_TICK_PER_SEC;
+    }
 
 /* Deprecated, to be removed */
-int xt_clock_freq(void)
-{
-    return esp_clk_cpu_freq();
-}
+    int xt_clock_freq( void )
+    {
+        return esp_clk_cpu_freq();
+    }
 
 #endif /* XT_RTOS_TIMER_INT */
diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_overlay_os_hook.c b/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_overlay_os_hook.c
index 618083dc9..4146f5d64 100644
--- a/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_overlay_os_hook.c
+++ b/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_overlay_os_hook.c
@@ -5,6 +5,7 @@
  *
  * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD
  */
+
 /*
  * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
  *
diff --git a/portable/ThirdParty/XCC/Xtensa/port.c b/portable/ThirdParty/XCC/Xtensa/port.c
index 805a78401..a95784167 100644
--- a/portable/ThirdParty/XCC/Xtensa/port.c
+++ b/portable/ThirdParty/XCC/Xtensa/port.c
@@ -37,34 +37,39 @@
 
 
 /* Defined in portasm.h */
-extern void _frxt_tick_timer_init(void);
+extern void _frxt_tick_timer_init( void );
 
 /* Defined in xtensa_context.S */
-extern void _xt_coproc_init(void);
+extern void _xt_coproc_init( void );
 
 
 /*-----------------------------------------------------------*/
 
 /* We require the address of the pxCurrentTCB variable, but don't want to know
-any details of its type. */
+ * any details of its type. */
 typedef void TCB_t;
 extern volatile TCB_t * volatile pxCurrentTCB;
 
-unsigned port_xSchedulerRunning = 0; // Duplicate of inaccessible xSchedulerRunning; needed at startup to avoid counting nesting
-unsigned port_interruptNesting = 0;  // Interrupt nesting level
+unsigned port_xSchedulerRunning = 0; /* Duplicate of inaccessible xSchedulerRunning; needed at startup to avoid counting nesting */
+unsigned port_interruptNesting = 0;  /* Interrupt nesting level */
 
 /*-----------------------------------------------------------*/
 
-// User exception dispatcher when exiting
-void _xt_user_exit(void);
+/* User exception dispatcher when exiting */
+void _xt_user_exit( void );
 
 /*
  * Stack initialization
  */
 #if portUSING_MPU_WRAPPERS
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged )
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters,
+                                         BaseType_t xRunPrivileged )
 #else
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters )
 #endif
 {
     StackType_t * sp;
@@ -129,18 +134,18 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
 void vPortEndScheduler( void )
 {
     /* It is unlikely that the Xtensa port will get stopped.  If required simply
-    disable the tick interrupt here. */
+     * disable the tick interrupt here. */
 }
 
 /*-----------------------------------------------------------*/
 
 BaseType_t xPortStartScheduler( void )
 {
-    // Interrupts are disabled at this point and stack contains PS with enabled interrupts when task context is restored
+    /* Interrupts are disabled at this point and stack contains PS with enabled interrupts when task context is restored */
 
     #if XCHAL_CP_NUM > 0
-    /* Initialize co-processor management for tasks. Leave CPENABLE alone. */
-    _xt_coproc_init();
+        /* Initialize co-processor management for tasks. Leave CPENABLE alone. */
+        _xt_coproc_init();
     #endif
 
     /* Init the tick divisor value */
@@ -150,14 +155,14 @@ BaseType_t xPortStartScheduler( void )
     _frxt_tick_timer_init();
 
     #if XT_USE_THREAD_SAFE_CLIB
-    // Init C library
-    vPortClibInit();
+        /* Init C library */
+        vPortClibInit();
     #endif
 
     port_xSchedulerRunning = 1;
 
-    // Cannot be directly called from C; never returns
-    __asm__ volatile ("call0    _frxt_dispatch\n");
+    /* Cannot be directly called from C; never returns */
+    __asm__ volatile ( "call0    _frxt_dispatch\n" );
 
     /* Should not get here. */
     return pdTRUE;
@@ -190,19 +195,19 @@ BaseType_t xPortSysTickHandler( void )
  * Used to set coprocessor area in stack. Current hack is to reuse MPU pointer for coprocessor area.
  */
 #if portUSING_MPU_WRAPPERS
-void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
-                                const struct xMEMORY_REGION * const xRegions,
-                                StackType_t * pxBottomOfStack,
-                                uint32_t ulStackDepth )
-{
-    #if XCHAL_CP_NUM > 0
-        xMPUSettings->coproc_area = ( StackType_t * ) ( ( uint32_t ) ( pxBottomOfStack + ulStackDepth - 1 ));
-        xMPUSettings->coproc_area = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) xMPUSettings->coproc_area ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) );
-        xMPUSettings->coproc_area = ( StackType_t * ) ( ( ( uint32_t ) xMPUSettings->coproc_area - XT_CP_SIZE ) & ~0xf );
+    void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
+                                    const struct xMEMORY_REGION * const xRegions,
+                                    StackType_t * pxBottomOfStack,
+                                    uint32_t ulStackDepth )
+    {
+        #if XCHAL_CP_NUM > 0
+            xMPUSettings->coproc_area = ( StackType_t * ) ( ( uint32_t ) ( pxBottomOfStack + ulStackDepth - 1 ) );
+            xMPUSettings->coproc_area = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) xMPUSettings->coproc_area ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) );
+            xMPUSettings->coproc_area = ( StackType_t * ) ( ( ( uint32_t ) xMPUSettings->coproc_area - XT_CP_SIZE ) & ~0xf );
 
-        /* NOTE: we cannot initialize the coprocessor save area here because FreeRTOS is going to
-         * clear the stack area after we return. This is done in pxPortInitialiseStack().
-         */
-    #endif
-}
+            /* NOTE: we cannot initialize the coprocessor save area here because FreeRTOS is going to
+             * clear the stack area after we return. This is done in pxPortInitialiseStack().
+             */
+        #endif
+    }
 #endif /* if portUSING_MPU_WRAPPERS */
diff --git a/portable/ThirdParty/XCC/Xtensa/portbenchmark.h b/portable/ThirdParty/XCC/Xtensa/portbenchmark.h
index 7778dd1a5..deb1cd0d6 100644
--- a/portable/ThirdParty/XCC/Xtensa/portbenchmark.h
+++ b/portable/ThirdParty/XCC/Xtensa/portbenchmark.h
@@ -42,7 +42,7 @@
 #endif
 
 #define portbenchmarkINTERRUPT_DISABLE()
-#define portbenchmarkINTERRUPT_RESTORE(newstate)
+#define portbenchmarkINTERRUPT_RESTORE( newstate )
 #define portbenchmarkIntLatency()
 #define portbenchmarkIntWait()
 #define portbenchmarkReset()
diff --git a/portable/ThirdParty/XCC/Xtensa/portclib.c b/portable/ThirdParty/XCC/Xtensa/portclib.c
index 3c87d6741..bb415fbbe 100644
--- a/portable/ThirdParty/XCC/Xtensa/portclib.c
+++ b/portable/ThirdParty/XCC/Xtensa/portclib.c
@@ -31,200 +31,204 @@
 
 #if XT_USE_THREAD_SAFE_CLIB
 
-#if XSHAL_CLIB == XTHAL_CLIB_XCLIB
+    #if XSHAL_CLIB == XTHAL_CLIB_XCLIB
 
-#include <errno.h>
-#include <sys/reent.h>
+        #include <errno.h>
+        #include <sys/reent.h>
 
-#include "semphr.h"
+        #include "semphr.h"
 
-typedef SemaphoreHandle_t       _Rmtx;
+        typedef SemaphoreHandle_t _Rmtx;
 
-//-----------------------------------------------------------------------------
-//  Override this and set to nonzero to enable locking.
-//-----------------------------------------------------------------------------
-int32_t _xclib_use_mt = 1;
+/*----------------------------------------------------------------------------- */
+/*  Override this and set to nonzero to enable locking. */
+/*----------------------------------------------------------------------------- */
+        int32_t _xclib_use_mt = 1;
 
 
-//-----------------------------------------------------------------------------
-//  Init lock.
-//-----------------------------------------------------------------------------
-void
-_Mtxinit(_Rmtx * mtx)
-{
-    *mtx = xSemaphoreCreateRecursiveMutex();
-}
+/*----------------------------------------------------------------------------- */
+/*  Init lock. */
+/*----------------------------------------------------------------------------- */
+        void _Mtxinit( _Rmtx * mtx )
+        {
+            *mtx = xSemaphoreCreateRecursiveMutex();
+        }
 
-//-----------------------------------------------------------------------------
-//  Destroy lock.
-//-----------------------------------------------------------------------------
-void
-_Mtxdst(_Rmtx * mtx)
-{
-    if ((mtx != NULL) && (*mtx != NULL)) {
-        vSemaphoreDelete(*mtx);
-    }
-}
+/*----------------------------------------------------------------------------- */
+/*  Destroy lock. */
+/*----------------------------------------------------------------------------- */
+        void _Mtxdst( _Rmtx * mtx )
+        {
+            if( ( mtx != NULL ) && ( *mtx != NULL ) )
+            {
+                vSemaphoreDelete( *mtx );
+            }
+        }
 
-//-----------------------------------------------------------------------------
-//  Lock.
-//-----------------------------------------------------------------------------
-void
-_Mtxlock(_Rmtx * mtx)
-{
-    if ((mtx != NULL) && (*mtx != NULL)) {
-        xSemaphoreTakeRecursive(*mtx, portMAX_DELAY);
-    }
-}
+/*----------------------------------------------------------------------------- */
+/*  Lock. */
+/*----------------------------------------------------------------------------- */
+        void _Mtxlock( _Rmtx * mtx )
+        {
+            if( ( mtx != NULL ) && ( *mtx != NULL ) )
+            {
+                xSemaphoreTakeRecursive( *mtx, portMAX_DELAY );
+            }
+        }
 
-//-----------------------------------------------------------------------------
-//  Unlock.
-//-----------------------------------------------------------------------------
-void
-_Mtxunlock(_Rmtx * mtx)
-{
-    if ((mtx != NULL) && (*mtx != NULL)) {
-        xSemaphoreGiveRecursive(*mtx);
-    }
-}
+/*----------------------------------------------------------------------------- */
+/*  Unlock. */
+/*----------------------------------------------------------------------------- */
+        void _Mtxunlock( _Rmtx * mtx )
+        {
+            if( ( mtx != NULL ) && ( *mtx != NULL ) )
+            {
+                xSemaphoreGiveRecursive( *mtx );
+            }
+        }
 
-//-----------------------------------------------------------------------------
-//  Called by malloc() to allocate blocks of memory from the heap.
-//-----------------------------------------------------------------------------
-void *
-_sbrk_r (struct _reent * reent, int32_t incr)
-{
-    extern char _end;
-    extern char _heap_sentry;
-    static char * _heap_sentry_ptr = &_heap_sentry;
-    static char * heap_ptr;
-    char * base;
+/*----------------------------------------------------------------------------- */
+/*  Called by malloc() to allocate blocks of memory from the heap. */
+/*----------------------------------------------------------------------------- */
+        void * _sbrk_r( struct _reent * reent,
+                        int32_t incr )
+        {
+            extern char _end;
+            extern char _heap_sentry;
+            static char * _heap_sentry_ptr = &_heap_sentry;
+            static char * heap_ptr;
+            char * base;
 
-    if (!heap_ptr)
-        heap_ptr = (char *) &_end;
+            if( !heap_ptr )
+            {
+                heap_ptr = ( char * ) &_end;
+            }
 
-    base = heap_ptr;
-    if (heap_ptr + incr >= _heap_sentry_ptr) {
-        reent->_errno = ENOMEM;
-        return (char *) -1;
-    }
+            base = heap_ptr;
 
-    heap_ptr += incr;
-    return base;
-}
+            if( heap_ptr + incr >= _heap_sentry_ptr )
+            {
+                reent->_errno = ENOMEM;
+                return ( char * ) -1;
+            }
 
-//-----------------------------------------------------------------------------
-//  Global initialization for C library.
-//-----------------------------------------------------------------------------
-void
-vPortClibInit(void)
-{
-}
+            heap_ptr += incr;
+            return base;
+        }
 
-//-----------------------------------------------------------------------------
-//  Per-thread cleanup stub provided for linking, does nothing.
-//-----------------------------------------------------------------------------
-void
-_reclaim_reent(void * ptr)
-{
-}
+/*----------------------------------------------------------------------------- */
+/*  Global initialization for C library. */
+/*----------------------------------------------------------------------------- */
+        void vPortClibInit( void )
+        {
+        }
 
-#endif /* XSHAL_CLIB == XTHAL_CLIB_XCLIB */
+/*----------------------------------------------------------------------------- */
+/*  Per-thread cleanup stub provided for linking, does nothing. */
+/*----------------------------------------------------------------------------- */
+        void _reclaim_reent( void * ptr )
+        {
+        }
 
-#if XSHAL_CLIB == XTHAL_CLIB_NEWLIB
+    #endif /* XSHAL_CLIB == XTHAL_CLIB_XCLIB */
 
-#include <errno.h>
-#include <malloc.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
+    #if XSHAL_CLIB == XTHAL_CLIB_NEWLIB
 
-#include "semphr.h"
+        #include <errno.h>
+        #include <malloc.h>
+        #include <stdio.h>
+        #include <stdlib.h>
+        #include <string.h>
 
-static SemaphoreHandle_t xClibMutex;
-static uint32_t  ulClibInitDone = 0;
+        #include "semphr.h"
 
-//-----------------------------------------------------------------------------
-//  Get C library lock.
-//-----------------------------------------------------------------------------
-void
-__malloc_lock(struct _reent * ptr)
-{
-    if (!ulClibInitDone)
-        return;
+        static SemaphoreHandle_t xClibMutex;
+        static uint32_t ulClibInitDone = 0;
 
-    xSemaphoreTakeRecursive(xClibMutex, portMAX_DELAY);
-}
+/*----------------------------------------------------------------------------- */
+/*  Get C library lock. */
+/*----------------------------------------------------------------------------- */
+        void __malloc_lock( struct _reent * ptr )
+        {
+            if( !ulClibInitDone )
+            {
+                return;
+            }
 
-//-----------------------------------------------------------------------------
-//  Release C library lock.
-//-----------------------------------------------------------------------------
-void
-__malloc_unlock(struct _reent * ptr)
-{
-    if (!ulClibInitDone)
-        return;
+            xSemaphoreTakeRecursive( xClibMutex, portMAX_DELAY );
+        }
 
-    xSemaphoreGiveRecursive(xClibMutex);
-}
+/*----------------------------------------------------------------------------- */
+/*  Release C library lock. */
+/*----------------------------------------------------------------------------- */
+        void __malloc_unlock( struct _reent * ptr )
+        {
+            if( !ulClibInitDone )
+            {
+                return;
+            }
 
-//-----------------------------------------------------------------------------
-//  Lock for environment. Since we have only one global lock we can just call
-//  the malloc() lock function.
-//-----------------------------------------------------------------------------
-void
-__env_lock(struct _reent * ptr)
-{
-    __malloc_lock(ptr);
-}
+            xSemaphoreGiveRecursive( xClibMutex );
+        }
+
+/*----------------------------------------------------------------------------- */
+/*  Lock for environment. Since we have only one global lock we can just call */
+/*  the malloc() lock function. */
+/*----------------------------------------------------------------------------- */
+        void __env_lock( struct _reent * ptr )
+        {
+            __malloc_lock( ptr );
+        }
 
 
-//-----------------------------------------------------------------------------
-//  Unlock environment.
-//-----------------------------------------------------------------------------
-void
-__env_unlock(struct _reent * ptr)
-{
-    __malloc_unlock(ptr);
-}
+/*----------------------------------------------------------------------------- */
+/*  Unlock environment. */
+/*----------------------------------------------------------------------------- */
+        void __env_unlock( struct _reent * ptr )
+        {
+            __malloc_unlock( ptr );
+        }
 
-//-----------------------------------------------------------------------------
-//  Called by malloc() to allocate blocks of memory from the heap.
-//-----------------------------------------------------------------------------
-void *
-_sbrk_r (struct _reent * reent, int32_t incr)
-{
-    extern char _end;
-    extern char _heap_sentry;
-    static char * _heap_sentry_ptr = &_heap_sentry;
-    static char * heap_ptr;
-    char * base;
+/*----------------------------------------------------------------------------- */
+/*  Called by malloc() to allocate blocks of memory from the heap. */
+/*----------------------------------------------------------------------------- */
+        void * _sbrk_r( struct _reent * reent,
+                        int32_t incr )
+        {
+            extern char _end;
+            extern char _heap_sentry;
+            static char * _heap_sentry_ptr = &_heap_sentry;
+            static char * heap_ptr;
+            char * base;
 
-    if (!heap_ptr)
-        heap_ptr = (char *) &_end;
+            if( !heap_ptr )
+            {
+                heap_ptr = ( char * ) &_end;
+            }
 
-    base = heap_ptr;
-    if (heap_ptr + incr >= _heap_sentry_ptr) {
-        reent->_errno = ENOMEM;
-        return (char *) -1;
-    }
+            base = heap_ptr;
 
-    heap_ptr += incr;
-    return base;
-}
+            if( heap_ptr + incr >= _heap_sentry_ptr )
+            {
+                reent->_errno = ENOMEM;
+                return ( char * ) -1;
+            }
 
-//-----------------------------------------------------------------------------
-//  Global initialization for C library.
-//-----------------------------------------------------------------------------
-void
-vPortClibInit(void)
-{
-    configASSERT(!ulClibInitDone);
+            heap_ptr += incr;
+            return base;
+        }
 
-    xClibMutex = xSemaphoreCreateRecursiveMutex();
-    ulClibInitDone  = 1;
-}
+/*----------------------------------------------------------------------------- */
+/*  Global initialization for C library. */
+/*----------------------------------------------------------------------------- */
+        void vPortClibInit( void )
+        {
+            configASSERT( !ulClibInitDone );
 
-#endif /* XSHAL_CLIB == XTHAL_CLIB_NEWLIB */
+            xClibMutex = xSemaphoreCreateRecursiveMutex();
+            ulClibInitDone = 1;
+        }
+
+    #endif /* XSHAL_CLIB == XTHAL_CLIB_NEWLIB */
 
 #endif /* XT_USE_THREAD_SAFE_CLIB */
diff --git a/portable/ThirdParty/XCC/Xtensa/portmacro.h b/portable/ThirdParty/XCC/Xtensa/portmacro.h
index f84e4335e..21d3e5384 100644
--- a/portable/ThirdParty/XCC/Xtensa/portmacro.h
+++ b/portable/ThirdParty/XCC/Xtensa/portmacro.h
@@ -38,15 +38,15 @@
 
 #ifndef __ASSEMBLER__
 
-#include <stdint.h>
+    #include <stdint.h>
 
-#include <xtensa/tie/xt_core.h>
-#include <xtensa/hal.h>
-#include <xtensa/config/core.h>
-#include <xtensa/config/system.h>   /* required for XSHAL_CLIB */
-#include <xtensa/xtruntime.h>
+    #include <xtensa/tie/xt_core.h>
+    #include <xtensa/hal.h>
+    #include <xtensa/config/core.h>
+    #include <xtensa/config/system.h> /* required for XSHAL_CLIB */
+    #include <xtensa/xtruntime.h>
 
-//#include "xtensa_context.h"
+/*#include "xtensa_context.h" */
 
 /*-----------------------------------------------------------
  * Port specific definitions.
@@ -60,149 +60,159 @@
 
 /* Type definitions. */
 
-#define portCHAR        int8_t
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        int32_t
-#define portSHORT       int16_t
-#define portSTACK_TYPE  uint32_t
-#define portBASE_TYPE   int
+    #define portCHAR          int8_t
+    #define portFLOAT         float
+    #define portDOUBLE        double
+    #define portLONG          int32_t
+    #define portSHORT         int16_t
+    #define portSTACK_TYPE    uint32_t
+    #define portBASE_TYPE     int
 
-typedef portSTACK_TYPE          StackType_t;
-typedef portBASE_TYPE           BaseType_t;
-typedef unsigned portBASE_TYPE  UBaseType_t;
+    typedef portSTACK_TYPE           StackType_t;
+    typedef portBASE_TYPE            BaseType_t;
+    typedef unsigned portBASE_TYPE   UBaseType_t;
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
-#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#else
-    #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
-#endif
+    #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+        typedef uint16_t             TickType_t;
+        #define portMAX_DELAY    ( TickType_t ) 0xffff
+    #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+        typedef uint32_t             TickType_t;
+        #define portMAX_DELAY    ( TickType_t ) 0xffffffffUL
+    #else
+        #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+    #endif
 /*-----------------------------------------------------------*/
 
-// portbenchmark
-#include "portbenchmark.h"
+/* portbenchmark */
+    #include "portbenchmark.h"
 
 /* Critical section management. NW-TODO: replace XTOS_SET_INTLEVEL with more efficient version, if any? */
-// These cannot be nested. They should be used with a lot of care and cannot be called from interrupt level.
-#define portDISABLE_INTERRUPTS()      do { XTOS_SET_INTLEVEL(XCHAL_EXCM_LEVEL); portbenchmarkINTERRUPT_DISABLE(); } while (0)
-#define portENABLE_INTERRUPTS()       do { portbenchmarkINTERRUPT_RESTORE(0); XTOS_SET_INTLEVEL(0); } while (0)
+/* These cannot be nested. They should be used with a lot of care and cannot be called from interrupt level. */
+    #define portDISABLE_INTERRUPTS()    do { XTOS_SET_INTLEVEL( XCHAL_EXCM_LEVEL ); portbenchmarkINTERRUPT_DISABLE(); } while( 0 )
+    #define portENABLE_INTERRUPTS()     do { portbenchmarkINTERRUPT_RESTORE( 0 ); XTOS_SET_INTLEVEL( 0 ); } while( 0 )
 
-// These can be nested
-#define portCRITICAL_NESTING_IN_TCB 1  // For now, let FreeRTOS' (tasks.c) manage critical nesting
-void vTaskEnterCritical(void);
-void vTaskExitCritical(void);
-#define portENTER_CRITICAL()        vTaskEnterCritical()
-#define portEXIT_CRITICAL()         vTaskExitCritical()
+/* These can be nested */
+    #define portCRITICAL_NESTING_IN_TCB    1 /* For now, let FreeRTOS' (tasks.c) manage critical nesting */
+    void vTaskEnterCritical( void );
+    void vTaskExitCritical( void );
+    #define portENTER_CRITICAL()    vTaskEnterCritical()
+    #define portEXIT_CRITICAL()     vTaskExitCritical()
 
-// Cleaner and preferred solution allows nested interrupts disabling and restoring via local registers or stack.
-// They can be called from interrupts too.
-static inline unsigned portENTER_CRITICAL_NESTED() { unsigned state = XTOS_SET_INTLEVEL(XCHAL_EXCM_LEVEL); portbenchmarkINTERRUPT_DISABLE(); return state; }
-#define portEXIT_CRITICAL_NESTED(state)   do { portbenchmarkINTERRUPT_RESTORE(state); XTOS_RESTORE_JUST_INTLEVEL(state); } while (0)
+/* Cleaner and preferred solution allows nested interrupts disabling and restoring via local registers or stack. */
+/* They can be called from interrupts too. */
+    static inline unsigned portENTER_CRITICAL_NESTED()
+    {
+        unsigned state = XTOS_SET_INTLEVEL( XCHAL_EXCM_LEVEL );
 
-// These FreeRTOS versions are similar to the nested versions above
-#define portSET_INTERRUPT_MASK_FROM_ISR()            portENTER_CRITICAL_NESTED()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(state)     portEXIT_CRITICAL_NESTED(state)
+        portbenchmarkINTERRUPT_DISABLE();
+        return state;
+    }
+    #define portEXIT_CRITICAL_NESTED( state )             do { portbenchmarkINTERRUPT_RESTORE( state ); XTOS_RESTORE_JUST_INTLEVEL( state ); } while( 0 )
+
+/* These FreeRTOS versions are similar to the nested versions above */
+    #define portSET_INTERRUPT_MASK_FROM_ISR()             portENTER_CRITICAL_NESTED()
+    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( state )    portEXIT_CRITICAL_NESTED( state )
 
 /*-----------------------------------------------------------*/
 
 /* Architecture specifics. */
-#define portSTACK_GROWTH            ( -1 )
-#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT          4
-#define portNOP()                   XT_NOP()
+    #define portSTACK_GROWTH      ( -1 )
+    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+    #define portBYTE_ALIGNMENT    4
+    #define portNOP()    XT_NOP()
 /*-----------------------------------------------------------*/
 
 /* Fine resolution time */
-#define portGET_RUN_TIME_COUNTER_VALUE()  xthal_get_ccount()
+    #define portGET_RUN_TIME_COUNTER_VALUE()    xthal_get_ccount()
 
 /* Kernel utilities. */
-void vPortYield( void );
-void _frxt_setup_switch( void );
-#define portYIELD()       vPortYield()
-#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken )  \
-    if ( ( xHigherPriorityTaskWoken ) != 0 ) {  \
-        _frxt_setup_switch();           \
+    void vPortYield( void );
+    void _frxt_setup_switch( void );
+    #define portYIELD()    vPortYield()
+    #define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) \
+    if( ( xHigherPriorityTaskWoken ) != 0 ) {              \
+        _frxt_setup_switch();                              \
     }
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
-// When coprocessors are defined, we to maintain a pointer to coprocessors area.
-// We currently use a hack: redefine field xMPU_SETTINGS in TCB block as a structure that can hold:
-// MPU wrappers, coprocessor area pointer, trace code structure, and more if needed.
-// The field is normally used for memory protection. FreeRTOS should create another general purpose field.
-typedef struct {
-    #if XCHAL_CP_NUM > 0
-    volatile StackType_t* coproc_area; // Pointer to coprocessor save area; MUST BE FIRST
-    #endif
-
-    #if portUSING_MPU_WRAPPERS
-    // Define here mpu_settings, which is port dependent
-    int mpu_setting; // Just a dummy example here; MPU not ported to Xtensa yet
+/* When coprocessors are defined, we to maintain a pointer to coprocessors area. */
+/* We currently use a hack: redefine field xMPU_SETTINGS in TCB block as a structure that can hold: */
+/* MPU wrappers, coprocessor area pointer, trace code structure, and more if needed. */
+/* The field is normally used for memory protection. FreeRTOS should create another general purpose field. */
+    typedef struct
+    {
+        #if XCHAL_CP_NUM > 0
+            volatile StackType_t * coproc_area; /* Pointer to coprocessor save area; MUST BE FIRST */
+        #endif
+
+        #if portUSING_MPU_WRAPPERS
+            /* Define here mpu_settings, which is port dependent */
+            int mpu_setting; /* Just a dummy example here; MPU not ported to Xtensa yet */
+        #endif
+
+        #if configUSE_TRACE_FACILITY_2
+            struct
+            {
+                /* Cf. porttraceStamp() */
+                int taskstamp;      /* Stamp from inside task to see where we are */
+                int taskstampcount; /* A counter usually incremented when we restart the task's loop */
+            } porttrace;
+        #endif
+    } xMPU_SETTINGS;
+
+/* Main hack to use MPU_wrappers even when no MPU is defined (warning: mpu_setting should not be accessed; otherwise move this above xMPU_SETTINGS) */
+    #if ( XCHAL_CP_NUM > 0 || configUSE_TRACE_FACILITY_2 ) && !portUSING_MPU_WRAPPERS /* If MPU wrappers not used, we still need to allocate coproc area */
+        #undef portUSING_MPU_WRAPPERS
+        #define portUSING_MPU_WRAPPERS    1                                           /* Enable it to allocate coproc area */
+        #define MPU_WRAPPERS_H                                                        /* Override mpu_wrapper.h to disable unwanted code */
+        #define PRIVILEGED_FUNCTION
+        #define PRIVILEGED_DATA
     #endif
 
+/* porttrace */
     #if configUSE_TRACE_FACILITY_2
-    struct {
-        // Cf. porttraceStamp()
-        int taskstamp;        /* Stamp from inside task to see where we are */
-        int taskstampcount;   /* A counter usually incremented when we restart the task's loop */
-    } porttrace;
+        #include "porttrace.h"
     #endif
-} xMPU_SETTINGS;
 
-// Main hack to use MPU_wrappers even when no MPU is defined (warning: mpu_setting should not be accessed; otherwise move this above xMPU_SETTINGS)
-#if (XCHAL_CP_NUM > 0 || configUSE_TRACE_FACILITY_2) && !portUSING_MPU_WRAPPERS   // If MPU wrappers not used, we still need to allocate coproc area
-    #undef portUSING_MPU_WRAPPERS
-    #define portUSING_MPU_WRAPPERS 1   // Enable it to allocate coproc area
-    #define MPU_WRAPPERS_H             // Override mpu_wrapper.h to disable unwanted code
-    #define PRIVILEGED_FUNCTION
-    #define PRIVILEGED_DATA
-#endif
-
-// porttrace
-#if configUSE_TRACE_FACILITY_2
-#include "porttrace.h"
-#endif
-
-// configASSERT_2 if requested
-#if configASSERT_2
-#include <stdio.h>
-void exit(int);
-#define configASSERT( x )   if (!(x)) { porttracePrint(-1); printf("\nAssertion failed in %s:%d\n", __FILE__, __LINE__); exit(-1); }
-#endif
+/* configASSERT_2 if requested */
+    #if configASSERT_2
+        #include <stdio.h>
+        void exit( int );
+        #define configASSERT( x )    if( !( x ) ) { porttracePrint( -1 ); printf( "\nAssertion failed in %s:%d\n", __FILE__, __LINE__ ); exit( -1 ); }
+    #endif
 
 
 /* C library support -- only XCLIB and NEWLIB are supported. */
 
 /* To enable thread-safe C library support, XT_USE_THREAD_SAFE_CLIB must be
-   defined to be > 0 somewhere above or on the command line. */
+ * defined to be > 0 somewhere above or on the command line. */
 
-#if (XT_USE_THREAD_SAFE_CLIB > 0u) && (XSHAL_CLIB == XTHAL_CLIB_XCLIB)
-extern void vPortClibInit(void);
-#endif // XCLIB support
+    #if ( XT_USE_THREAD_SAFE_CLIB > 0u ) && ( XSHAL_CLIB == XTHAL_CLIB_XCLIB )
+        extern void vPortClibInit( void );
+    #endif // XCLIB support
 
-#if (XT_USE_THREAD_SAFE_CLIB > 0u) && (XSHAL_CLIB == XTHAL_CLIB_NEWLIB)
-extern void vPortClibInit(void);
+    #if ( XT_USE_THREAD_SAFE_CLIB > 0u ) && ( XSHAL_CLIB == XTHAL_CLIB_NEWLIB )
+        extern void vPortClibInit( void );
 
-// This C library cleanup is not currently done by FreeRTOS when deleting a task
-#include <stdio.h>
-#define portCLEAN_UP_TCB(pxTCB)   vPortCleanUpTcbClib(&((pxTCB)->xNewLib_reent))
-static inline void vPortCleanUpTcbClib(struct _reent *ptr)
-{
-    FILE * fp = &(ptr->__sf[0]);
-    int i;
-    for (i = 0; i < 3; ++i, ++fp) {
-        fp->_close = NULL;
-    }
-}
-#endif // NEWLIB support
+/* This C library cleanup is not currently done by FreeRTOS when deleting a task */
+        #include <stdio.h>
+        #define portCLEAN_UP_TCB( pxTCB )    vPortCleanUpTcbClib( &( ( pxTCB )->xNewLib_reent ) )
+        static inline void vPortCleanUpTcbClib( struct _reent * ptr )
+        {
+            FILE * fp = &( ptr->__sf[ 0 ] );
+            int i;
+
+            for( i = 0; i < 3; ++i, ++fp )
+            {
+                fp->_close = NULL;
+            }
+        }
+    #endif // NEWLIB support
 
 #endif // __ASSEMBLER__
 
diff --git a/portable/ThirdParty/XCC/Xtensa/porttrace.h b/portable/ThirdParty/XCC/Xtensa/porttrace.h
index 9909ec3af..7a2ad1d53 100644
--- a/portable/ThirdParty/XCC/Xtensa/porttrace.h
+++ b/portable/ThirdParty/XCC/Xtensa/porttrace.h
@@ -1,4 +1,4 @@
- /*
+/*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
@@ -43,7 +43,7 @@
     #error "You need to download the FreeRTOS_trace patch that overwrites this file"
 #endif
 
-#define porttracePrint(nelements)
-#define porttraceStamp(stamp, count_incr)
+#define porttracePrint( nelements )
+#define porttraceStamp( stamp, count_incr )
 
 #endif /* PORTTRACE_H */
diff --git a/portable/ThirdParty/XCC/Xtensa/xtensa_api.h b/portable/ThirdParty/XCC/Xtensa/xtensa_api.h
index 703449f2b..bf2834f09 100644
--- a/portable/ThirdParty/XCC/Xtensa/xtensa_api.h
+++ b/portable/ThirdParty/XCC/Xtensa/xtensa_api.h
@@ -1,4 +1,4 @@
- /*
+/*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
@@ -40,87 +40,90 @@
 
 
 /* Typedef for C-callable interrupt handler function */
-typedef void (*xt_handler)(void *);
+typedef void (* xt_handler)( void * );
 
 /* Typedef for C-callable exception handler function */
-typedef void (*xt_exc_handler)(XtExcFrame *);
+typedef void (* xt_exc_handler)( XtExcFrame * );
 
 
 /*
--------------------------------------------------------------------------------
-  Call this function to set a handler for the specified exception.
-
-    n        - Exception number (type)
-    f        - Handler function address, NULL to uninstall handler.
-
-  The handler will be passed a pointer to the exception frame, which is created
-  on the stack of the thread that caused the exception.
-
-  If the handler returns, the thread context will be restored and the faulting
-  instruction will be retried. Any values in the exception frame that are
-  modified by the handler will be restored as part of the context. For details
-  of the exception frame structure see xtensa_context.h.
--------------------------------------------------------------------------------
-*/
-extern xt_exc_handler xt_set_exception_handler(int n, xt_exc_handler f);
+ * -------------------------------------------------------------------------------
+ * Call this function to set a handler for the specified exception.
+ *
+ *  n        - Exception number (type)
+ *  f        - Handler function address, NULL to uninstall handler.
+ *
+ * The handler will be passed a pointer to the exception frame, which is created
+ * on the stack of the thread that caused the exception.
+ *
+ * If the handler returns, the thread context will be restored and the faulting
+ * instruction will be retried. Any values in the exception frame that are
+ * modified by the handler will be restored as part of the context. For details
+ * of the exception frame structure see xtensa_context.h.
+ * -------------------------------------------------------------------------------
+ */
+extern xt_exc_handler xt_set_exception_handler( int n,
+                                                xt_exc_handler f );
 
 
 /*
--------------------------------------------------------------------------------
-  Call this function to set a handler for the specified interrupt.
-
-    n        - Interrupt number.
-    f        - Handler function address, NULL to uninstall handler.
-    arg      - Argument to be passed to handler.
--------------------------------------------------------------------------------
-*/
-extern xt_handler xt_set_interrupt_handler(int n, xt_handler f, void * arg);
+ * -------------------------------------------------------------------------------
+ * Call this function to set a handler for the specified interrupt.
+ *
+ *  n        - Interrupt number.
+ *  f        - Handler function address, NULL to uninstall handler.
+ *  arg      - Argument to be passed to handler.
+ * -------------------------------------------------------------------------------
+ */
+extern xt_handler xt_set_interrupt_handler( int n,
+                                            xt_handler f,
+                                            void * arg );
 
 
 /*
--------------------------------------------------------------------------------
-  Call this function to enable the specified interrupts.
-
-    mask     - Bit mask of interrupts to be enabled.
-
-  Returns the previous state of the interrupt enables.
--------------------------------------------------------------------------------
-*/
-extern unsigned int xt_ints_on(unsigned int mask);
+ * -------------------------------------------------------------------------------
+ * Call this function to enable the specified interrupts.
+ *
+ *  mask     - Bit mask of interrupts to be enabled.
+ *
+ * Returns the previous state of the interrupt enables.
+ * -------------------------------------------------------------------------------
+ */
+extern unsigned int xt_ints_on( unsigned int mask );
 
 
 /*
--------------------------------------------------------------------------------
-  Call this function to disable the specified interrupts.
-
-    mask     - Bit mask of interrupts to be disabled.
-
-  Returns the previous state of the interrupt enables.
--------------------------------------------------------------------------------
-*/
-extern unsigned int xt_ints_off(unsigned int mask);
+ * -------------------------------------------------------------------------------
+ * Call this function to disable the specified interrupts.
+ *
+ *  mask     - Bit mask of interrupts to be disabled.
+ *
+ * Returns the previous state of the interrupt enables.
+ * -------------------------------------------------------------------------------
+ */
+extern unsigned int xt_ints_off( unsigned int mask );
 
 
 /*
--------------------------------------------------------------------------------
-  Call this function to set the specified (s/w) interrupt.
--------------------------------------------------------------------------------
-*/
-static inline void xt_set_intset(unsigned int arg)
+ * -------------------------------------------------------------------------------
+ * Call this function to set the specified (s/w) interrupt.
+ * -------------------------------------------------------------------------------
+ */
+static inline void xt_set_intset( unsigned int arg )
 {
-    xthal_set_intset(arg);
+    xthal_set_intset( arg );
 }
 
 
 /*
--------------------------------------------------------------------------------
-  Call this function to clear the specified (s/w or edge-triggered)
-  interrupt.
--------------------------------------------------------------------------------
-*/
-static inline void xt_set_intclear(unsigned int arg)
+ * -------------------------------------------------------------------------------
+ * Call this function to clear the specified (s/w or edge-triggered)
+ * interrupt.
+ * -------------------------------------------------------------------------------
+ */
+static inline void xt_set_intclear( unsigned int arg )
 {
-    xthal_set_intclear(arg);
+    xthal_set_intclear( arg );
 }
 
 
diff --git a/portable/ThirdParty/XCC/Xtensa/xtensa_config.h b/portable/ThirdParty/XCC/Xtensa/xtensa_config.h
index a5efcda58..cf80f8190 100644
--- a/portable/ThirdParty/XCC/Xtensa/xtensa_config.h
+++ b/portable/ThirdParty/XCC/Xtensa/xtensa_config.h
@@ -1,4 +1,4 @@
- /*
+/*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
@@ -47,139 +47,139 @@
 
 #include <xtensa/hal.h>
 #include <xtensa/config/core.h>
-#include <xtensa/config/system.h>   /* required for XSHAL_CLIB */
+#include <xtensa/config/system.h> /* required for XSHAL_CLIB */
 
 #include "xtensa_context.h"
 
 
 /*-----------------------------------------------------------------------------
-*                                 STACK REQUIREMENTS
-*
-* This section defines the minimum stack size, and the extra space required to
-* be allocated for saving coprocessor state and/or C library state information
-* (if thread safety is enabled for the C library). The sizes are in bytes.
-*
-* Stack sizes for individual tasks should be derived from these minima based on
-* the maximum call depth of the task and the maximum level of interrupt nesting.
-* A minimum stack size is defined by XT_STACK_MIN_SIZE. This minimum is based
-* on the requirement for a task that calls nothing else but can be interrupted.
-* This assumes that interrupt handlers do not call more than a few levels deep.
-* If this is not true, i.e. one or more interrupt handlers make deep calls then
-* the minimum must be increased.
-*
-* If the Xtensa processor configuration includes coprocessors, then space is
-* allocated to save the coprocessor state on the stack.
-*
-* If thread safety is enabled for the C runtime library, (XT_USE_THREAD_SAFE_CLIB
-* is defined) then space is allocated to save the C library context in the TCB.
-*
-* Allocating insufficient stack space is a common source of hard-to-find errors.
-* During development, it is best to enable the FreeRTOS stack checking features.
-*
-* Usage:
-*
-* XT_USE_THREAD_SAFE_CLIB -- Define this to a nonzero value to enable thread-safe
-*                            use of the C library. This will require extra stack
-*                            space to be allocated for tasks that use the C library
-*                            reentrant functions. See below for more information.
-*
-* NOTE: The Xtensa toolchain supports multiple C libraries and not all of them
-* support thread safety. Check your core configuration to see which C library
-* was chosen for your system.
-*
-* XT_STACK_MIN_SIZE       -- The minimum stack size for any task. It is recommended
-*                            that you do not use a stack smaller than this for any
-*                            task. In case you want to use stacks smaller than this
-*                            size, you must verify that the smaller size(s) will work
-*                            under all operating conditions.
-*
-* XT_STACK_EXTRA          -- The amount of extra stack space to allocate for a task
-*                            that does not make C library reentrant calls. Add this
-*                            to the amount of stack space required by the task itself.
-*
-* XT_STACK_EXTRA_CLIB     -- The amount of space to allocate for C library state.
-*
------------------------------------------------------------------------------*/
+ *                                 STACK REQUIREMENTS
+ *
+ * This section defines the minimum stack size, and the extra space required to
+ * be allocated for saving coprocessor state and/or C library state information
+ * (if thread safety is enabled for the C library). The sizes are in bytes.
+ *
+ * Stack sizes for individual tasks should be derived from these minima based on
+ * the maximum call depth of the task and the maximum level of interrupt nesting.
+ * A minimum stack size is defined by XT_STACK_MIN_SIZE. This minimum is based
+ * on the requirement for a task that calls nothing else but can be interrupted.
+ * This assumes that interrupt handlers do not call more than a few levels deep.
+ * If this is not true, i.e. one or more interrupt handlers make deep calls then
+ * the minimum must be increased.
+ *
+ * If the Xtensa processor configuration includes coprocessors, then space is
+ * allocated to save the coprocessor state on the stack.
+ *
+ * If thread safety is enabled for the C runtime library, (XT_USE_THREAD_SAFE_CLIB
+ * is defined) then space is allocated to save the C library context in the TCB.
+ *
+ * Allocating insufficient stack space is a common source of hard-to-find errors.
+ * During development, it is best to enable the FreeRTOS stack checking features.
+ *
+ * Usage:
+ *
+ * XT_USE_THREAD_SAFE_CLIB -- Define this to a nonzero value to enable thread-safe
+ *                            use of the C library. This will require extra stack
+ *                            space to be allocated for tasks that use the C library
+ *                            reentrant functions. See below for more information.
+ *
+ * NOTE: The Xtensa toolchain supports multiple C libraries and not all of them
+ * support thread safety. Check your core configuration to see which C library
+ * was chosen for your system.
+ *
+ * XT_STACK_MIN_SIZE       -- The minimum stack size for any task. It is recommended
+ *                            that you do not use a stack smaller than this for any
+ *                            task. In case you want to use stacks smaller than this
+ *                            size, you must verify that the smaller size(s) will work
+ *                            under all operating conditions.
+ *
+ * XT_STACK_EXTRA          -- The amount of extra stack space to allocate for a task
+ *                            that does not make C library reentrant calls. Add this
+ *                            to the amount of stack space required by the task itself.
+ *
+ * XT_STACK_EXTRA_CLIB     -- The amount of space to allocate for C library state.
+ *
+ *  -----------------------------------------------------------------------------*/
 
 /* Extra space required for interrupt/exception hooks. */
 #ifdef XT_INTEXC_HOOKS
-  #ifdef __XTENSA_CALL0_ABI__
-    #define STK_INTEXC_EXTRA        0x200
-  #else
-    #define STK_INTEXC_EXTRA        0x180
-  #endif
+    #ifdef __XTENSA_CALL0_ABI__
+        #define STK_INTEXC_EXTRA    0x200
+    #else
+        #define STK_INTEXC_EXTRA    0x180
+    #endif
 #else
-  #define STK_INTEXC_EXTRA          0
+    #define STK_INTEXC_EXTRA        0
 #endif
 
 /* Check C library thread safety support and compute size of C library save area.
-   For the supported libraries, we enable thread safety by default, and this can
-   be overridden from the compiler/make command line. */
-#if (XSHAL_CLIB == XTHAL_CLIB_NEWLIB) || (XSHAL_CLIB == XTHAL_CLIB_XCLIB)
-  #ifndef XT_USE_THREAD_SAFE_CLIB
-    #define XT_USE_THREAD_SAFE_CLIB         1
-  #endif
+ * For the supported libraries, we enable thread safety by default, and this can
+ * be overridden from the compiler/make command line. */
+#if ( XSHAL_CLIB == XTHAL_CLIB_NEWLIB ) || ( XSHAL_CLIB == XTHAL_CLIB_XCLIB )
+    #ifndef XT_USE_THREAD_SAFE_CLIB
+        #define XT_USE_THREAD_SAFE_CLIB    1
+    #endif
 #else
-  #define XT_USE_THREAD_SAFE_CLIB           0
+    #define XT_USE_THREAD_SAFE_CLIB        0
 #endif
 
 #if XT_USE_THREAD_SAFE_CLIB > 0u
-  #if XSHAL_CLIB == XTHAL_CLIB_XCLIB
-    #define XT_HAVE_THREAD_SAFE_CLIB        1
-    #if !defined __ASSEMBLER__
-      #include <sys/reent.h>
-      #define XT_CLIB_CONTEXT_AREA_SIZE     ((sizeof(struct _reent) + 15) + (-16))
-      #define XT_CLIB_GLOBAL_PTR            _reent_ptr
-      #define _REENT_INIT_PTR               _init_reent
-      #define _impure_ptr                   _reent_ptr
+    #if XSHAL_CLIB == XTHAL_CLIB_XCLIB
+        #define XT_HAVE_THREAD_SAFE_CLIB         1
+        #if !defined __ASSEMBLER__
+            #include <sys/reent.h>
+            #define XT_CLIB_CONTEXT_AREA_SIZE    ( ( sizeof( struct _reent ) + 15 ) + ( -16 ) )
+            #define XT_CLIB_GLOBAL_PTR           _reent_ptr
+            #define _REENT_INIT_PTR              _init_reent
+            #define _impure_ptr                  _reent_ptr
 
-      void _reclaim_reent(void * ptr);
-    #endif
-  #elif XSHAL_CLIB == XTHAL_CLIB_NEWLIB
-    #define XT_HAVE_THREAD_SAFE_CLIB        1
-    #if !defined __ASSEMBLER__
-      #include <sys/reent.h>
-      #define XT_CLIB_CONTEXT_AREA_SIZE     ((sizeof(struct _reent) + 15) + (-16))
-      #define XT_CLIB_GLOBAL_PTR            _impure_ptr
-    #endif
-  #else
-    #define XT_HAVE_THREAD_SAFE_CLIB        0
-    #error The selected C runtime library is not thread safe.
-  #endif
+            void _reclaim_reent( void * ptr );
+        #endif
+    #elif XSHAL_CLIB == XTHAL_CLIB_NEWLIB
+        #define XT_HAVE_THREAD_SAFE_CLIB         1
+        #if !defined __ASSEMBLER__
+            #include <sys/reent.h>
+            #define XT_CLIB_CONTEXT_AREA_SIZE    ( ( sizeof( struct _reent ) + 15 ) + ( -16 ) )
+            #define XT_CLIB_GLOBAL_PTR           _impure_ptr
+        #endif
+    #else /* if XSHAL_CLIB == XTHAL_CLIB_XCLIB */
+        #define XT_HAVE_THREAD_SAFE_CLIB         0
+        #error The selected C runtime library is not thread safe.
+    #endif /* if XSHAL_CLIB == XTHAL_CLIB_XCLIB */
+#else /* if XT_USE_THREAD_SAFE_CLIB > 0u */
+    #define XT_CLIB_CONTEXT_AREA_SIZE    0
+#endif /* if XT_USE_THREAD_SAFE_CLIB > 0u */
+
+/*------------------------------------------------------------------------------
+ *  Extra size -- interrupt frame plus coprocessor save area plus hook space.
+ *  NOTE: Make sure XT_INTEXC_HOOKS is undefined unless you really need the hooks.
+ *  ------------------------------------------------------------------------------*/
+#ifdef __XTENSA_CALL0_ABI__
+    #define XT_XTRA_SIZE    ( XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x10 + XT_CP_SIZE )
 #else
-  #define XT_CLIB_CONTEXT_AREA_SIZE         0
+    #define XT_XTRA_SIZE    ( XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x20 + XT_CP_SIZE )
 #endif
 
 /*------------------------------------------------------------------------------
-  Extra size -- interrupt frame plus coprocessor save area plus hook space.
-  NOTE: Make sure XT_INTEXC_HOOKS is undefined unless you really need the hooks.
-------------------------------------------------------------------------------*/
+ *  Space allocated for user code -- function calls and local variables.
+ *  NOTE: This number can be adjusted to suit your needs. You must verify that the
+ *  amount of space you reserve is adequate for the worst-case conditions in your
+ *  application.
+ *  NOTE: The windowed ABI requires more stack, since space has to be reserved
+ *  for spilling register windows.
+ *  ------------------------------------------------------------------------------*/
 #ifdef __XTENSA_CALL0_ABI__
-  #define XT_XTRA_SIZE            (XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x10 + XT_CP_SIZE)
+    #define XT_USER_SIZE    0x200
 #else
-  #define XT_XTRA_SIZE            (XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x20 + XT_CP_SIZE)
-#endif
-
-/*------------------------------------------------------------------------------
-  Space allocated for user code -- function calls and local variables.
-  NOTE: This number can be adjusted to suit your needs. You must verify that the
-  amount of space you reserve is adequate for the worst-case conditions in your
-  application.
-  NOTE: The windowed ABI requires more stack, since space has to be reserved
-  for spilling register windows.
-------------------------------------------------------------------------------*/
-#ifdef __XTENSA_CALL0_ABI__
-  #define XT_USER_SIZE            0x200
-#else
-  #define XT_USER_SIZE            0x400
+    #define XT_USER_SIZE    0x400
 #endif
 
 /* Minimum recommended stack size. */
-#define XT_STACK_MIN_SIZE         ((XT_XTRA_SIZE + XT_USER_SIZE) / sizeof(unsigned char))
+#define XT_STACK_MIN_SIZE      ( ( XT_XTRA_SIZE + XT_USER_SIZE ) / sizeof( unsigned char ) )
 
 /* OS overhead with and without C library thread context. */
-#define XT_STACK_EXTRA              (XT_XTRA_SIZE)
-#define XT_STACK_EXTRA_CLIB         (XT_XTRA_SIZE + XT_CLIB_CONTEXT_AREA_SIZE)
+#define XT_STACK_EXTRA         ( XT_XTRA_SIZE )
+#define XT_STACK_EXTRA_CLIB    ( XT_XTRA_SIZE + XT_CLIB_CONTEXT_AREA_SIZE )
 
 
 /* *INDENT-OFF* */
diff --git a/portable/ThirdParty/XCC/Xtensa/xtensa_context.h b/portable/ThirdParty/XCC/Xtensa/xtensa_context.h
index 579c62ea2..5d243d3c0 100644
--- a/portable/ThirdParty/XCC/Xtensa/xtensa_context.h
+++ b/portable/ThirdParty/XCC/Xtensa/xtensa_context.h
@@ -1,4 +1,4 @@
- /*
+/*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
@@ -44,7 +44,7 @@
 #define XTENSA_CONTEXT_H
 
 #ifdef __ASSEMBLER__
-#include    <xtensa/coreasm.h>
+    #include    <xtensa/coreasm.h>
 #endif
 
 #include    <xtensa/config/tie.h>
@@ -53,303 +53,307 @@
 
 
 /* Align a value up to nearest n-byte boundary, where n is a power of 2. */
-#define ALIGNUP(n, val) (((val) + (n)-1) & -(n))
+#define ALIGNUP( n, val )    ( ( ( val ) + ( n ) - 1 ) & -( n ) )
 
 
 /*
--------------------------------------------------------------------------------
-  Macros that help define structures for both C and assembler.
--------------------------------------------------------------------------------
-*/
-#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__)
+ * -------------------------------------------------------------------------------
+ * Macros that help define structures for both C and assembler.
+ * -------------------------------------------------------------------------------
+ */
+#if defined( _ASMLANGUAGE ) || defined( __ASSEMBLER__ )
 
-#define STRUCT_BEGIN            .pushsection .text; .struct 0
-#define STRUCT_FIELD(ctype,size,asname,name)    asname: .space  size
-#define STRUCT_AFIELD(ctype,size,asname,name,n) asname: .space  (size)*(n)
-#define STRUCT_END(sname)       sname##Size:; .popsection
+    #define STRUCT_BEGIN    .pushsection.text; .struct 0
+    #define STRUCT_FIELD( ctype, size, asname, name )        asname :.space size
+    #define STRUCT_AFIELD( ctype, size, asname, name, n )    asname :.space( size ) *( n )
+    #define STRUCT_END( sname )                              sname ## Size:; .popsection
 
 #else
 
-#define STRUCT_BEGIN            typedef struct {
-#define STRUCT_FIELD(ctype,size,asname,name)    ctype   name;
-#define STRUCT_AFIELD(ctype,size,asname,name,n) ctype   name[n];
-#define STRUCT_END(sname)       } sname;
+    #define STRUCT_BEGIN    typedef struct {
+    #define STRUCT_FIELD( ctype, size, asname, name )        ctype name;
+    #define STRUCT_AFIELD( ctype, size, asname, name, n )    ctype name[ n ];
+    #define STRUCT_END( sname ) \
+}                               \
+    sname;
 
 #endif //_ASMLANGUAGE || __ASSEMBLER__
 
 
 /*
--------------------------------------------------------------------------------
-  INTERRUPT/EXCEPTION STACK FRAME FOR A THREAD OR NESTED INTERRUPT
+ * -------------------------------------------------------------------------------
+ * INTERRUPT/EXCEPTION STACK FRAME FOR A THREAD OR NESTED INTERRUPT
+ *
+ * A stack frame of this structure is allocated for any interrupt or exception.
+ * It goes on the current stack. If the RTOS has a system stack for handling
+ * interrupts, every thread stack must allow space for just one interrupt stack
+ * frame, then nested interrupt stack frames go on the system stack.
+ *
+ * The frame includes basic registers (explicit) and "extra" registers introduced
+ * by user TIE or the use of the MAC16 option in the user's Xtensa config.
+ * The frame size is minimized by omitting regs not applicable to user's config.
+ *
+ * For Windowed ABI, this stack frame includes the interruptee's base save area,
+ * another base save area to manage gcc nested functions, and a little temporary
+ * space to help manage the spilling of the register windows.
+ * -------------------------------------------------------------------------------
+ */
 
-  A stack frame of this structure is allocated for any interrupt or exception.
-  It goes on the current stack. If the RTOS has a system stack for handling
-  interrupts, every thread stack must allow space for just one interrupt stack
-  frame, then nested interrupt stack frames go on the system stack.
-
-  The frame includes basic registers (explicit) and "extra" registers introduced
-  by user TIE or the use of the MAC16 option in the user's Xtensa config.
-  The frame size is minimized by omitting regs not applicable to user's config.
-
-  For Windowed ABI, this stack frame includes the interruptee's base save area,
-  another base save area to manage gcc nested functions, and a little temporary
-  space to help manage the spilling of the register windows.
--------------------------------------------------------------------------------
-*/
-
-STRUCT_BEGIN
-STRUCT_FIELD (long, 4, XT_STK_EXIT,     exit) /* exit point for dispatch */
-STRUCT_FIELD (long, 4, XT_STK_PC,       pc)   /* return PC */
-STRUCT_FIELD (long, 4, XT_STK_PS,       ps)   /* return PS */
-STRUCT_FIELD (long, 4, XT_STK_A0,       a0)
-STRUCT_FIELD (long, 4, XT_STK_A1,       a1)   /* stack pointer before interrupt */
-STRUCT_FIELD (long, 4, XT_STK_A2,       a2)
-STRUCT_FIELD (long, 4, XT_STK_A3,       a3)
-STRUCT_FIELD (long, 4, XT_STK_A4,       a4)
-STRUCT_FIELD (long, 4, XT_STK_A5,       a5)
-STRUCT_FIELD (long, 4, XT_STK_A6,       a6)
-STRUCT_FIELD (long, 4, XT_STK_A7,       a7)
-STRUCT_FIELD (long, 4, XT_STK_A8,       a8)
-STRUCT_FIELD (long, 4, XT_STK_A9,       a9)
-STRUCT_FIELD (long, 4, XT_STK_A10,      a10)
-STRUCT_FIELD (long, 4, XT_STK_A11,      a11)
-STRUCT_FIELD (long, 4, XT_STK_A12,      a12)
-STRUCT_FIELD (long, 4, XT_STK_A13,      a13)
-STRUCT_FIELD (long, 4, XT_STK_A14,      a14)
-STRUCT_FIELD (long, 4, XT_STK_A15,      a15)
-STRUCT_FIELD (long, 4, XT_STK_SAR,      sar)
-STRUCT_FIELD (long, 4, XT_STK_EXCCAUSE, exccause)
-STRUCT_FIELD (long, 4, XT_STK_EXCVADDR, excvaddr)
+STRUCT_BEGIN STRUCT_FIELD( long,
+                           4,
+                           XT_STK_EXIT,
+                           exit )      /* exit point for dispatch */
+STRUCT_FIELD( long, 4, XT_STK_PC, pc ) /* return PC */
+STRUCT_FIELD( long, 4, XT_STK_PS, ps ) /* return PS */
+STRUCT_FIELD( long, 4, XT_STK_A0, a0 )
+STRUCT_FIELD( long, 4, XT_STK_A1, a1 ) /* stack pointer before interrupt */
+STRUCT_FIELD( long, 4, XT_STK_A2, a2 )
+STRUCT_FIELD( long, 4, XT_STK_A3, a3 )
+STRUCT_FIELD( long, 4, XT_STK_A4, a4 )
+STRUCT_FIELD( long, 4, XT_STK_A5, a5 )
+STRUCT_FIELD( long, 4, XT_STK_A6, a6 )
+STRUCT_FIELD( long, 4, XT_STK_A7, a7 )
+STRUCT_FIELD( long, 4, XT_STK_A8, a8 )
+STRUCT_FIELD( long, 4, XT_STK_A9, a9 )
+STRUCT_FIELD( long, 4, XT_STK_A10, a10 )
+STRUCT_FIELD( long, 4, XT_STK_A11, a11 )
+STRUCT_FIELD( long, 4, XT_STK_A12, a12 )
+STRUCT_FIELD( long, 4, XT_STK_A13, a13 )
+STRUCT_FIELD( long, 4, XT_STK_A14, a14 )
+STRUCT_FIELD( long, 4, XT_STK_A15, a15 )
+STRUCT_FIELD( long, 4, XT_STK_SAR, sar )
+STRUCT_FIELD( long, 4, XT_STK_EXCCAUSE, exccause )
+STRUCT_FIELD( long, 4, XT_STK_EXCVADDR, excvaddr )
 #if XCHAL_HAVE_LOOPS
-STRUCT_FIELD (long, 4, XT_STK_LBEG,   lbeg)
-STRUCT_FIELD (long, 4, XT_STK_LEND,   lend)
-STRUCT_FIELD (long, 4, XT_STK_LCOUNT, lcount)
+    STRUCT_FIELD( long, 4, XT_STK_LBEG, lbeg )
+    STRUCT_FIELD( long, 4, XT_STK_LEND, lend )
+    STRUCT_FIELD( long, 4, XT_STK_LCOUNT, lcount )
 #endif
 #ifndef __XTENSA_CALL0_ABI__
 /* Temporary space for saving stuff during window spill */
-STRUCT_FIELD (long, 4, XT_STK_TMP0,   tmp0)
-STRUCT_FIELD (long, 4, XT_STK_TMP1,   tmp1)
-STRUCT_FIELD (long, 4, XT_STK_TMP2,   tmp2)
+    STRUCT_FIELD( long, 4, XT_STK_TMP0, tmp0 )
+    STRUCT_FIELD( long, 4, XT_STK_TMP1, tmp1 )
+    STRUCT_FIELD( long, 4, XT_STK_TMP2, tmp2 )
 #endif
 #ifdef XT_USE_SWPRI
 /* Storage for virtual priority mask */
-STRUCT_FIELD (long, 4, XT_STK_VPRI,   vpri)
+    STRUCT_FIELD( long, 4, XT_STK_VPRI, vpri )
 #endif
 #ifdef XT_USE_OVLY
 /* Storage for overlay state */
-STRUCT_FIELD (long, 4, XT_STK_OVLY,   ovly)
+    STRUCT_FIELD( long, 4, XT_STK_OVLY, ovly )
 #endif
-STRUCT_END(XtExcFrame)
+STRUCT_END( XtExcFrame )
 
-#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__)
-#define XT_STK_NEXT1      XtExcFrameSize
+#if defined( _ASMLANGUAGE ) || defined( __ASSEMBLER__ )
+#define XT_STK_NEXT1    XtExcFrameSize
 #else
-#define XT_STK_NEXT1      sizeof(XtExcFrame)
+#define XT_STK_NEXT1    sizeof( XtExcFrame )
 #endif
 
 /* Allocate extra storage if needed */
 #if XCHAL_EXTRA_SA_SIZE != 0
 
-#if XCHAL_EXTRA_SA_ALIGN <= 16
-#define XT_STK_EXTRA            ALIGNUP(XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1)
-#else
+    #if XCHAL_EXTRA_SA_ALIGN <= 16
+#define XT_STK_EXTRA    ALIGNUP( XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1 )
+    #else
 /* If need more alignment than stack, add space for dynamic alignment */
-#define XT_STK_EXTRA            (ALIGNUP(XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1) + XCHAL_EXTRA_SA_ALIGN)
-#endif
-#define XT_STK_NEXT2            (XT_STK_EXTRA + XCHAL_EXTRA_SA_SIZE)
+#define XT_STK_EXTRA    ( ALIGNUP( XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1 ) + XCHAL_EXTRA_SA_ALIGN )
+    #endif
+#define XT_STK_NEXT2    ( XT_STK_EXTRA + XCHAL_EXTRA_SA_SIZE )
 
 #else
 
-#define XT_STK_NEXT2            XT_STK_NEXT1
+#define XT_STK_NEXT2    XT_STK_NEXT1
 
-#endif
+#endif /* if XCHAL_EXTRA_SA_SIZE != 0 */
 
 /*
--------------------------------------------------------------------------------
-  This is the frame size. Add space for 4 registers (interruptee's base save
-  area) and some space for gcc nested functions if any.
--------------------------------------------------------------------------------
-*/
-#define XT_STK_FRMSZ            (ALIGNUP(0x10, XT_STK_NEXT2) + 0x20)
+ * -------------------------------------------------------------------------------
+ * This is the frame size. Add space for 4 registers (interruptee's base save
+ * area) and some space for gcc nested functions if any.
+ * -------------------------------------------------------------------------------
+ */
+#define XT_STK_FRMSZ    ( ALIGNUP( 0x10, XT_STK_NEXT2 ) + 0x20 )
 
 
 /*
--------------------------------------------------------------------------------
-  SOLICITED STACK FRAME FOR A THREAD
-
-  A stack frame of this structure is allocated whenever a thread enters the
-  RTOS kernel intentionally (and synchronously) to submit to thread scheduling.
-  It goes on the current thread's stack.
-
-  The solicited frame only includes registers that are required to be preserved
-  by the callee according to the compiler's ABI conventions, some space to save
-  the return address for returning to the caller, and the caller's PS register.
-
-  For Windowed ABI, this stack frame includes the caller's base save area.
-
-  Note on XT_SOL_EXIT field:
-      It is necessary to distinguish a solicited from an interrupt stack frame.
-      This field corresponds to XT_STK_EXIT in the interrupt stack frame and is
-      always at the same offset (0). It can be written with a code (usually 0)
-      to distinguish a solicted frame from an interrupt frame. An RTOS port may
-      opt to ignore this field if it has another way of distinguishing frames.
--------------------------------------------------------------------------------
-*/
+ * -------------------------------------------------------------------------------
+ * SOLICITED STACK FRAME FOR A THREAD
+ *
+ * A stack frame of this structure is allocated whenever a thread enters the
+ * RTOS kernel intentionally (and synchronously) to submit to thread scheduling.
+ * It goes on the current thread's stack.
+ *
+ * The solicited frame only includes registers that are required to be preserved
+ * by the callee according to the compiler's ABI conventions, some space to save
+ * the return address for returning to the caller, and the caller's PS register.
+ *
+ * For Windowed ABI, this stack frame includes the caller's base save area.
+ *
+ * Note on XT_SOL_EXIT field:
+ *    It is necessary to distinguish a solicited from an interrupt stack frame.
+ *    This field corresponds to XT_STK_EXIT in the interrupt stack frame and is
+ *    always at the same offset (0). It can be written with a code (usually 0)
+ *    to distinguish a solicted frame from an interrupt frame. An RTOS port may
+ *    opt to ignore this field if it has another way of distinguishing frames.
+ * -------------------------------------------------------------------------------
+ */
 
 STRUCT_BEGIN
 #ifdef __XTENSA_CALL0_ABI__
-STRUCT_FIELD (long, 4, XT_SOL_EXIT, exit)
-STRUCT_FIELD (long, 4, XT_SOL_PC,   pc)
-STRUCT_FIELD (long, 4, XT_SOL_PS,   ps)
-STRUCT_FIELD (long, 4, XT_SOL_NEXT, next)
-STRUCT_FIELD (long, 4, XT_SOL_A12,  a12)    /* should be on 16-byte alignment */
-STRUCT_FIELD (long, 4, XT_SOL_A13,  a13)
-STRUCT_FIELD (long, 4, XT_SOL_A14,  a14)
-STRUCT_FIELD (long, 4, XT_SOL_A15,  a15)
+    STRUCT_FIELD( long, 4, XT_SOL_EXIT, exit )
+    STRUCT_FIELD( long, 4, XT_SOL_PC, pc )
+    STRUCT_FIELD( long, 4, XT_SOL_PS, ps )
+    STRUCT_FIELD( long, 4, XT_SOL_NEXT, next )
+    STRUCT_FIELD( long, 4, XT_SOL_A12, a12 ) /* should be on 16-byte alignment */
+    STRUCT_FIELD( long, 4, XT_SOL_A13, a13 )
+    STRUCT_FIELD( long, 4, XT_SOL_A14, a14 )
+    STRUCT_FIELD( long, 4, XT_SOL_A15, a15 )
 #else
-STRUCT_FIELD (long, 4, XT_SOL_EXIT, exit)
-STRUCT_FIELD (long, 4, XT_SOL_PC,   pc)
-STRUCT_FIELD (long, 4, XT_SOL_PS,   ps)
-STRUCT_FIELD (long, 4, XT_SOL_NEXT, next)
-STRUCT_FIELD (long, 4, XT_SOL_A0,   a0)    /* should be on 16-byte alignment */
-STRUCT_FIELD (long, 4, XT_SOL_A1,   a1)
-STRUCT_FIELD (long, 4, XT_SOL_A2,   a2)
-STRUCT_FIELD (long, 4, XT_SOL_A3,   a3)
-#endif
-STRUCT_END(XtSolFrame)
+    STRUCT_FIELD( long, 4, XT_SOL_EXIT, exit )
+    STRUCT_FIELD( long, 4, XT_SOL_PC, pc )
+    STRUCT_FIELD( long, 4, XT_SOL_PS, ps )
+    STRUCT_FIELD( long, 4, XT_SOL_NEXT, next )
+    STRUCT_FIELD( long, 4, XT_SOL_A0, a0 ) /* should be on 16-byte alignment */
+    STRUCT_FIELD( long, 4, XT_SOL_A1, a1 )
+    STRUCT_FIELD( long, 4, XT_SOL_A2, a2 )
+    STRUCT_FIELD( long, 4, XT_SOL_A3, a3 )
+#endif /* ifdef __XTENSA_CALL0_ABI__ */
+STRUCT_END( XtSolFrame )
 
 /* Size of solicited stack frame */
-#define XT_SOL_FRMSZ            ALIGNUP(0x10, XtSolFrameSize)
+#define XT_SOL_FRMSZ    ALIGNUP( 0x10, XtSolFrameSize )
 
 
 /*
--------------------------------------------------------------------------------
-  CO-PROCESSOR STATE SAVE AREA FOR A THREAD
-
-  The RTOS must provide an area per thread to save the state of co-processors
-  when that thread does not have control. Co-processors are context-switched
-  lazily (on demand) only when a new thread uses a co-processor instruction,
-  otherwise a thread retains ownership of the co-processor even when it loses
-  control of the processor. An Xtensa co-processor exception is triggered when
-  any co-processor instruction is executed by a thread that is not the owner,
-  and the context switch of that co-processor is then peformed by the handler.
-  Ownership represents which thread's state is currently in the co-processor.
-
-  Co-processors may not be used by interrupt or exception handlers. If an
-  co-processor instruction is executed by an interrupt or exception handler,
-  the co-processor exception handler will trigger a kernel panic and freeze.
-  This restriction is introduced to reduce the overhead of saving and restoring
-  co-processor state (which can be quite large) and in particular remove that
-  overhead from interrupt handlers.
-
-  The co-processor state save area may be in any convenient per-thread location
-  such as in the thread control block or above the thread stack area. It need
-  not be in the interrupt stack frame since interrupts don't use co-processors.
-
-  Along with the save area for each co-processor, two bitmasks with flags per
-  co-processor (laid out as in the CPENABLE reg) help manage context-switching
-  co-processors as efficiently as possible:
-
-  XT_CPENABLE
-    The contents of a non-running thread's CPENABLE register.
-    It represents the co-processors owned (and whose state is still needed)
-    by the thread. When a thread is preempted, its CPENABLE is saved here.
-    When a thread solicits a context-swtich, its CPENABLE is cleared - the
-    compiler has saved the (caller-saved) co-proc state if it needs to.
-    When a non-running thread loses ownership of a CP, its bit is cleared.
-    When a thread runs, it's XT_CPENABLE is loaded into the CPENABLE reg.
-    Avoids co-processor exceptions when no change of ownership is needed.
-
-  XT_CPSTORED
-    A bitmask with the same layout as CPENABLE, a bit per co-processor.
-    Indicates whether the state of each co-processor is saved in the state
-    save area. When a thread enters the kernel, only the state of co-procs
-    still enabled in CPENABLE is saved. When the co-processor exception
-    handler assigns ownership of a co-processor to a thread, it restores
-    the saved state only if this bit is set, and clears this bit.
-
-  XT_CP_CS_ST
-    A bitmask with the same layout as CPENABLE, a bit per co-processor.
-    Indicates whether callee-saved state is saved in the state save area.
-    Callee-saved state is saved by itself on a solicited context switch,
-    and restored when needed by the coprocessor exception handler.
-    Unsolicited switches will cause the entire coprocessor to be saved
-    when necessary.
-
-  XT_CP_ASA
-    Pointer to the aligned save area.  Allows it to be aligned more than
-    the overall save area (which might only be stack-aligned or TCB-aligned).
-    Especially relevant for Xtensa cores configured with a very large data
-    path that requires alignment greater than 16 bytes (ABI stack alignment).
--------------------------------------------------------------------------------
-*/
+ * -------------------------------------------------------------------------------
+ * CO-PROCESSOR STATE SAVE AREA FOR A THREAD
+ *
+ * The RTOS must provide an area per thread to save the state of co-processors
+ * when that thread does not have control. Co-processors are context-switched
+ * lazily (on demand) only when a new thread uses a co-processor instruction,
+ * otherwise a thread retains ownership of the co-processor even when it loses
+ * control of the processor. An Xtensa co-processor exception is triggered when
+ * any co-processor instruction is executed by a thread that is not the owner,
+ * and the context switch of that co-processor is then peformed by the handler.
+ * Ownership represents which thread's state is currently in the co-processor.
+ *
+ * Co-processors may not be used by interrupt or exception handlers. If an
+ * co-processor instruction is executed by an interrupt or exception handler,
+ * the co-processor exception handler will trigger a kernel panic and freeze.
+ * This restriction is introduced to reduce the overhead of saving and restoring
+ * co-processor state (which can be quite large) and in particular remove that
+ * overhead from interrupt handlers.
+ *
+ * The co-processor state save area may be in any convenient per-thread location
+ * such as in the thread control block or above the thread stack area. It need
+ * not be in the interrupt stack frame since interrupts don't use co-processors.
+ *
+ * Along with the save area for each co-processor, two bitmasks with flags per
+ * co-processor (laid out as in the CPENABLE reg) help manage context-switching
+ * co-processors as efficiently as possible:
+ *
+ * XT_CPENABLE
+ *  The contents of a non-running thread's CPENABLE register.
+ *  It represents the co-processors owned (and whose state is still needed)
+ *  by the thread. When a thread is preempted, its CPENABLE is saved here.
+ *  When a thread solicits a context-swtich, its CPENABLE is cleared - the
+ *  compiler has saved the (caller-saved) co-proc state if it needs to.
+ *  When a non-running thread loses ownership of a CP, its bit is cleared.
+ *  When a thread runs, it's XT_CPENABLE is loaded into the CPENABLE reg.
+ *  Avoids co-processor exceptions when no change of ownership is needed.
+ *
+ * XT_CPSTORED
+ *  A bitmask with the same layout as CPENABLE, a bit per co-processor.
+ *  Indicates whether the state of each co-processor is saved in the state
+ *  save area. When a thread enters the kernel, only the state of co-procs
+ *  still enabled in CPENABLE is saved. When the co-processor exception
+ *  handler assigns ownership of a co-processor to a thread, it restores
+ *  the saved state only if this bit is set, and clears this bit.
+ *
+ * XT_CP_CS_ST
+ *  A bitmask with the same layout as CPENABLE, a bit per co-processor.
+ *  Indicates whether callee-saved state is saved in the state save area.
+ *  Callee-saved state is saved by itself on a solicited context switch,
+ *  and restored when needed by the coprocessor exception handler.
+ *  Unsolicited switches will cause the entire coprocessor to be saved
+ *  when necessary.
+ *
+ * XT_CP_ASA
+ *  Pointer to the aligned save area.  Allows it to be aligned more than
+ *  the overall save area (which might only be stack-aligned or TCB-aligned).
+ *  Especially relevant for Xtensa cores configured with a very large data
+ *  path that requires alignment greater than 16 bytes (ABI stack alignment).
+ * -------------------------------------------------------------------------------
+ */
 
 #if XCHAL_CP_NUM > 0
 
 /*  Offsets of each coprocessor save area within the 'aligned save area':  */
-#define XT_CP0_SA   0
-#define XT_CP1_SA   ALIGNUP(XCHAL_CP1_SA_ALIGN, XT_CP0_SA + XCHAL_CP0_SA_SIZE)
-#define XT_CP2_SA   ALIGNUP(XCHAL_CP2_SA_ALIGN, XT_CP1_SA + XCHAL_CP1_SA_SIZE)
-#define XT_CP3_SA   ALIGNUP(XCHAL_CP3_SA_ALIGN, XT_CP2_SA + XCHAL_CP2_SA_SIZE)
-#define XT_CP4_SA   ALIGNUP(XCHAL_CP4_SA_ALIGN, XT_CP3_SA + XCHAL_CP3_SA_SIZE)
-#define XT_CP5_SA   ALIGNUP(XCHAL_CP5_SA_ALIGN, XT_CP4_SA + XCHAL_CP4_SA_SIZE)
-#define XT_CP6_SA   ALIGNUP(XCHAL_CP6_SA_ALIGN, XT_CP5_SA + XCHAL_CP5_SA_SIZE)
-#define XT_CP7_SA   ALIGNUP(XCHAL_CP7_SA_ALIGN, XT_CP6_SA + XCHAL_CP6_SA_SIZE)
-#define XT_CP_SA_SIZE   ALIGNUP(16, XT_CP7_SA + XCHAL_CP7_SA_SIZE)
+#define XT_CP0_SA        0
+#define XT_CP1_SA        ALIGNUP( XCHAL_CP1_SA_ALIGN, XT_CP0_SA + XCHAL_CP0_SA_SIZE )
+#define XT_CP2_SA        ALIGNUP( XCHAL_CP2_SA_ALIGN, XT_CP1_SA + XCHAL_CP1_SA_SIZE )
+#define XT_CP3_SA        ALIGNUP( XCHAL_CP3_SA_ALIGN, XT_CP2_SA + XCHAL_CP2_SA_SIZE )
+#define XT_CP4_SA        ALIGNUP( XCHAL_CP4_SA_ALIGN, XT_CP3_SA + XCHAL_CP3_SA_SIZE )
+#define XT_CP5_SA        ALIGNUP( XCHAL_CP5_SA_ALIGN, XT_CP4_SA + XCHAL_CP4_SA_SIZE )
+#define XT_CP6_SA        ALIGNUP( XCHAL_CP6_SA_ALIGN, XT_CP5_SA + XCHAL_CP5_SA_SIZE )
+#define XT_CP7_SA        ALIGNUP( XCHAL_CP7_SA_ALIGN, XT_CP6_SA + XCHAL_CP6_SA_SIZE )
+#define XT_CP_SA_SIZE    ALIGNUP( 16, XT_CP7_SA + XCHAL_CP7_SA_SIZE )
 
 /*  Offsets within the overall save area:  */
-#define XT_CPENABLE 0   /* (2 bytes) coprocessors active for this thread */
-#define XT_CPSTORED 2   /* (2 bytes) coprocessors saved for this thread */
-#define XT_CP_CS_ST 4   /* (2 bytes) coprocessor callee-saved regs stored for this thread */
-#define XT_CP_ASA   8   /* (4 bytes) ptr to aligned save area */
+#define XT_CPENABLE      0 /* (2 bytes) coprocessors active for this thread */
+#define XT_CPSTORED      2 /* (2 bytes) coprocessors saved for this thread */
+#define XT_CP_CS_ST      4 /* (2 bytes) coprocessor callee-saved regs stored for this thread */
+#define XT_CP_ASA        8 /* (4 bytes) ptr to aligned save area */
 /*  Overall size allows for dynamic alignment:  */
-#define XT_CP_SIZE  (12 + XT_CP_SA_SIZE + XCHAL_TOTAL_SA_ALIGN)
-#else
-#define XT_CP_SIZE  0
-#endif
+#define XT_CP_SIZE       ( 12 + XT_CP_SA_SIZE + XCHAL_TOTAL_SA_ALIGN )
+#else /* if XCHAL_CP_NUM > 0 */
+#define XT_CP_SIZE       0
+#endif /* if XCHAL_CP_NUM > 0 */
 
 
 /*
--------------------------------------------------------------------------------
-  MACROS TO HANDLE ABI SPECIFICS OF FUNCTION ENTRY AND RETURN
-
-  Convenient where the frame size requirements are the same for both ABIs.
-    ENTRY(sz), RET(sz) are for framed functions (have locals or make calls).
-    ENTRY0,    RET0    are for frameless functions (no locals, no calls).
-
-  where size = size of stack frame in bytes (must be >0 and aligned to 16).
-  For framed functions the frame is created and the return address saved at
-  base of frame (Call0 ABI) or as determined by hardware (Windowed ABI).
-  For frameless functions, there is no frame and return address remains in a0.
-  Note: Because CPP macros expand to a single line, macros requiring multi-line
-  expansions are implemented as assembler macros.
--------------------------------------------------------------------------------
-*/
+ * -------------------------------------------------------------------------------
+ * MACROS TO HANDLE ABI SPECIFICS OF FUNCTION ENTRY AND RETURN
+ *
+ * Convenient where the frame size requirements are the same for both ABIs.
+ *  ENTRY(sz), RET(sz) are for framed functions (have locals or make calls).
+ *  ENTRY0,    RET0    are for frameless functions (no locals, no calls).
+ *
+ * where size = size of stack frame in bytes (must be >0 and aligned to 16).
+ * For framed functions the frame is created and the return address saved at
+ * base of frame (Call0 ABI) or as determined by hardware (Windowed ABI).
+ * For frameless functions, there is no frame and return address remains in a0.
+ * Note: Because CPP macros expand to a single line, macros requiring multi-line
+ * expansions are implemented as assembler macros.
+ * -------------------------------------------------------------------------------
+ */
 
 #ifdef __ASSEMBLER__
-#ifdef __XTENSA_CALL0_ABI__
-  /* Call0 */
-  #define ENTRY(sz)     entry1  sz
-    .macro  entry1 size=0x10
-    addi    sp, sp, -\size
-    s32i    a0, sp, 0
-    .endm
-  #define ENTRY0
-  #define RET(sz)       ret1    sz
-    .macro  ret1 size=0x10
-    l32i    a0, sp, 0
-    addi    sp, sp, \size
-    ret
-    .endm
-  #define RET0          ret
-#else
-  /* Windowed */
-  #define ENTRY(sz)     entry   sp, sz
-  #define ENTRY0        entry   sp, 0x10
-  #define RET(sz)       retw
-  #define RET0          retw
-#endif
-#endif
+    #ifdef __XTENSA_CALL0_ABI__
+        /* Call0 */
+#define ENTRY( sz )    entry1 sz
+           .macro entry1 size = 0x10
+                                addi sp, sp, -\ size
+        s32i a0, sp, 0
+           .endm
+#define ENTRY0
+#define RET( sz )    ret1 sz
+           .macro ret1 size = 0x10
+                              l32i a0, sp, 0
+        addi sp, sp, \ size
+        ret
+           .endm
+#define RET0    ret
+    #else /* ifdef __XTENSA_CALL0_ABI__ */
+        /* Windowed */
+#define ENTRY( sz )    entry sp, sz
+#define ENTRY0    entry sp, 0x10
+#define RET( sz )      retw
+#define RET0      retw
+    #endif /* ifdef __XTENSA_CALL0_ABI__ */
+#endif /* ifdef __ASSEMBLER__ */
 
 
 #endif /* XTENSA_CONTEXT_H */
diff --git a/portable/ThirdParty/XCC/Xtensa/xtensa_init.c b/portable/ThirdParty/XCC/Xtensa/xtensa_init.c
index c18520350..7ee6f3d63 100644
--- a/portable/ThirdParty/XCC/Xtensa/xtensa_init.c
+++ b/portable/ThirdParty/XCC/Xtensa/xtensa_init.c
@@ -1,4 +1,4 @@
- /*
+/*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
@@ -36,35 +36,31 @@
 
 
 #ifdef XT_BOARD
-#include    <xtensa/xtbsp.h>
+    #include    <xtensa/xtbsp.h>
 #endif
 
 #include    "xtensa_rtos.h"
 
 #ifdef XT_RTOS_TIMER_INT
 
-unsigned _xt_tick_divisor = 0;  /* cached number of cycles per tick */
+    unsigned _xt_tick_divisor = 0; /* cached number of cycles per tick */
 
 /*
-Compute and initialize at run-time the tick divisor (the number of
-processor clock cycles in an RTOS tick, used to set the tick timer).
-Called when the processor clock frequency is not known at compile-time.
-*/
-void _xt_tick_divisor_init(void)
-{
-#ifdef XT_CLOCK_FREQ
-
-    _xt_tick_divisor = (XT_CLOCK_FREQ / XT_TICK_PER_SEC);
-
-#else
-
-    #ifdef XT_BOARD
-    _xt_tick_divisor = xtbsp_clock_freq_hz() / XT_TICK_PER_SEC;
-    #else
-    #error "No way to obtain processor clock frequency"
-    #endif  /* XT_BOARD */
-
-#endif /* XT_CLOCK_FREQ */
-}
+ * Compute and initialize at run-time the tick divisor (the number of
+ * processor clock cycles in an RTOS tick, used to set the tick timer).
+ * Called when the processor clock frequency is not known at compile-time.
+ */
+    void _xt_tick_divisor_init( void )
+    {
+        #ifdef XT_CLOCK_FREQ
+            _xt_tick_divisor = ( XT_CLOCK_FREQ / XT_TICK_PER_SEC );
+        #else
+            #ifdef XT_BOARD
+                _xt_tick_divisor = xtbsp_clock_freq_hz() / XT_TICK_PER_SEC;
+            #else
+            #error "No way to obtain processor clock frequency"
+            #endif /* XT_BOARD */
+        #endif /* XT_CLOCK_FREQ */
+    }
 
 #endif /* XT_RTOS_TIMER_INT */
diff --git a/portable/ThirdParty/XCC/Xtensa/xtensa_intr.c b/portable/ThirdParty/XCC/Xtensa/xtensa_intr.c
index 88ed191e3..87bf63cb4 100644
--- a/portable/ThirdParty/XCC/Xtensa/xtensa_intr.c
+++ b/portable/ThirdParty/XCC/Xtensa/xtensa_intr.c
@@ -1,4 +1,4 @@
- /*
+/*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
@@ -43,95 +43,110 @@
 
 /* Handler table is in xtensa_intr_asm.S */
 
-extern xt_exc_handler _xt_exception_table[XCHAL_EXCCAUSE_NUM];
+    extern xt_exc_handler _xt_exception_table[ XCHAL_EXCCAUSE_NUM ];
 
 
 /*
-  Default handler for unhandled exceptions.
-*/
-void xt_unhandled_exception(XtExcFrame *frame)
-{
-    exit(-1);
-}
+ * Default handler for unhandled exceptions.
+ */
+    void xt_unhandled_exception( XtExcFrame * frame )
+    {
+        exit( -1 );
+    }
 
 
 /*
-  This function registers a handler for the specified exception.
-  The function returns the address of the previous handler.
-  On error, it returns 0.
-*/
-xt_exc_handler xt_set_exception_handler(int n, xt_exc_handler f)
-{
-    xt_exc_handler old;
+ * This function registers a handler for the specified exception.
+ * The function returns the address of the previous handler.
+ * On error, it returns 0.
+ */
+    xt_exc_handler xt_set_exception_handler( int n,
+                                             xt_exc_handler f )
+    {
+        xt_exc_handler old;
 
-    if( n < 0 || n >= XCHAL_EXCCAUSE_NUM )
-        return 0;       /* invalid exception number */
+        if( ( n < 0 ) || ( n >= XCHAL_EXCCAUSE_NUM ) )
+        {
+            return 0; /* invalid exception number */
+        }
 
-    old = _xt_exception_table[n];
+        old = _xt_exception_table[ n ];
 
-    if (f) {
-        _xt_exception_table[n] = f;
-    }
-    else {
-        _xt_exception_table[n] = &xt_unhandled_exception;
+        if( f )
+        {
+            _xt_exception_table[ n ] = f;
+        }
+        else
+        {
+            _xt_exception_table[ n ] = &xt_unhandled_exception;
+        }
+
+        return( ( old == &xt_unhandled_exception ) ? 0 : old );
     }
 
-    return ((old == &xt_unhandled_exception) ? 0 : old);
-}
-
-#endif
+#endif /* if XCHAL_HAVE_EXCEPTIONS */
 
 #if XCHAL_HAVE_INTERRUPTS
 
 /* Handler table is in xtensa_intr_asm.S */
 
-typedef struct xt_handler_table_entry {
-    void * handler;
-    void * arg;
-} xt_handler_table_entry;
+    typedef struct xt_handler_table_entry
+    {
+        void * handler;
+        void * arg;
+    } xt_handler_table_entry;
 
-extern xt_handler_table_entry _xt_interrupt_table[XCHAL_NUM_INTERRUPTS];
+    extern xt_handler_table_entry _xt_interrupt_table[ XCHAL_NUM_INTERRUPTS ];
 
 
 /*
-  Default handler for unhandled interrupts.
-*/
-void xt_unhandled_interrupt(void * arg)
-{
-    exit(-1);
-}
+ * Default handler for unhandled interrupts.
+ */
+    void xt_unhandled_interrupt( void * arg )
+    {
+        exit( -1 );
+    }
 
 
 /*
-  This function registers a handler for the specified interrupt. The "arg"
-  parameter specifies the argument to be passed to the handler when it is
-  invoked. The function returns the address of the previous handler.
-  On error, it returns 0.
-*/
-xt_handler xt_set_interrupt_handler(int n, xt_handler f, void * arg)
-{
-    xt_handler_table_entry * entry;
-    xt_handler               old;
+ * This function registers a handler for the specified interrupt. The "arg"
+ * parameter specifies the argument to be passed to the handler when it is
+ * invoked. The function returns the address of the previous handler.
+ * On error, it returns 0.
+ */
+    xt_handler xt_set_interrupt_handler( int n,
+                                         xt_handler f,
+                                         void * arg )
+    {
+        xt_handler_table_entry * entry;
+        xt_handler old;
 
-    if( n < 0 || n >= XCHAL_NUM_INTERRUPTS )
-        return 0;       /* invalid interrupt number */
-    if( Xthal_intlevel[n] > XCHAL_EXCM_LEVEL )
-        return 0;       /* priority level too high to safely handle in C */
+        if( ( n < 0 ) || ( n >= XCHAL_NUM_INTERRUPTS ) )
+        {
+            return 0; /* invalid interrupt number */
+        }
 
-    entry = _xt_interrupt_table + n;
-    old   = entry->handler;
+        if( Xthal_intlevel[ n ] > XCHAL_EXCM_LEVEL )
+        {
+            return 0; /* priority level too high to safely handle in C */
+        }
 
-    if (f) {
-        entry->handler = f;
-        entry->arg     = arg;
+        entry = _xt_interrupt_table + n;
+        old = entry->handler;
+
+        if( f )
+        {
+            entry->handler = f;
+            entry->arg = arg;
+        }
+        else
+        {
+            entry->handler = &xt_unhandled_interrupt;
+            entry->arg = ( void * ) n;
+        }
+
+        return( ( old == &xt_unhandled_interrupt ) ? 0 : old );
     }
-    else {
-        entry->handler = &xt_unhandled_interrupt;
-        entry->arg     = (void*)n;
-    }
-
-    return ((old == &xt_unhandled_interrupt) ? 0 : old);
-}
 
 
 #endif /* XCHAL_HAVE_INTERRUPTS */
diff --git a/portable/ThirdParty/XCC/Xtensa/xtensa_overlay_os_hook.c b/portable/ThirdParty/XCC/Xtensa/xtensa_overlay_os_hook.c
index 2a8506a01..fcbc57386 100644
--- a/portable/ThirdParty/XCC/Xtensa/xtensa_overlay_os_hook.c
+++ b/portable/ThirdParty/XCC/Xtensa/xtensa_overlay_os_hook.c
@@ -1,4 +1,4 @@
- /*
+/*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
@@ -39,7 +39,7 @@
 /* Mutex object that controls access to the overlay. Currently only one
  * overlay region is supported so one mutex suffices.
  */
-static SemaphoreHandle_t xt_overlay_mutex;
+    static SemaphoreHandle_t xt_overlay_mutex;
 
 
 /* This function should be overridden to provide OS specific init such
@@ -47,30 +47,30 @@ static SemaphoreHandle_t xt_overlay_mutex;
  * Typically this mutex would be set up with priority inheritance. See
  * overlay manager documentation for more details.
  */
-void xt_overlay_init_os(void)
-{
-    /* Create the mutex for overlay access. Priority inheritance is
-     * required.
-     */
-    xt_overlay_mutex = xSemaphoreCreateMutex();
-}
+    void xt_overlay_init_os( void )
+    {
+        /* Create the mutex for overlay access. Priority inheritance is
+         * required.
+         */
+        xt_overlay_mutex = xSemaphoreCreateMutex();
+    }
 
 
 /* This function locks access to shared overlay resources, typically
  * by acquiring a mutex.
  */
-void xt_overlay_lock(void)
-{
-    xSemaphoreTake(xt_overlay_mutex, 0);
-}
+    void xt_overlay_lock( void )
+    {
+        xSemaphoreTake( xt_overlay_mutex, 0 );
+    }
 
 
 /* This function releases access to shared overlay resources, typically
  * by unlocking a mutex.
  */
-void xt_overlay_unlock(void)
-{
-    xSemaphoreGive(xt_overlay_mutex);
-}
+    void xt_overlay_unlock( void )
+    {
+        xSemaphoreGive( xt_overlay_mutex );
+    }
 
-#endif
+#endif /* if configUSE_MUTEX */
diff --git a/portable/ThirdParty/XCC/Xtensa/xtensa_rtos.h b/portable/ThirdParty/XCC/Xtensa/xtensa_rtos.h
index 2c917c832..54f4d0b7e 100644
--- a/portable/ThirdParty/XCC/Xtensa/xtensa_rtos.h
+++ b/portable/ThirdParty/XCC/Xtensa/xtensa_rtos.h
@@ -1,4 +1,4 @@
- /*
+/*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
@@ -49,9 +49,9 @@
 #define XTENSA_RTOS_H
 
 #ifdef __ASSEMBLER__
-#include    <xtensa/coreasm.h>
+    #include    <xtensa/coreasm.h>
 #else
-#include    <xtensa/config/core.h>
+    #include    <xtensa/config/core.h>
 #endif
 
 #include    <xtensa/corebits.h>
@@ -59,180 +59,180 @@
 #include    <xtensa/simcall.h>
 
 /*
-Include any RTOS specific definitions that are needed by this header.
-*/
+ * Include any RTOS specific definitions that are needed by this header.
+ */
 #include    <FreeRTOSConfig.h>
 
 /*
-Convert FreeRTOSConfig definitions to XTENSA definitions.
-However these can still be overridden from the command line.
-*/
+ * Convert FreeRTOSConfig definitions to XTENSA definitions.
+ * However these can still be overridden from the command line.
+ */
 
 #ifndef XT_SIMULATOR
-  #if configXT_SIMULATOR
-    #define XT_SIMULATOR             1  /* Simulator mode */
-  #endif
+    #if configXT_SIMULATOR
+        #define XT_SIMULATOR    1       /* Simulator mode */
+    #endif
 #endif
 
 #ifndef XT_BOARD
-  #if configXT_BOARD
-    #define XT_BOARD                 1  /* Board mode */
-  #endif
+    #if configXT_BOARD
+        #define XT_BOARD    1           /* Board mode */
+    #endif
 #endif
 
 #ifndef XT_TIMER_INDEX
-  #if defined configXT_TIMER_INDEX
-    #define XT_TIMER_INDEX           configXT_TIMER_INDEX  /* Index of hardware timer to be used */
-  #endif
+    #if defined configXT_TIMER_INDEX
+        #define XT_TIMER_INDEX    configXT_TIMER_INDEX     /* Index of hardware timer to be used */
+    #endif
 #endif
 
 #ifndef XT_INTEXC_HOOKS
-  #if configXT_INTEXC_HOOKS
-    #define XT_INTEXC_HOOKS          1  /* Enables exception hooks */
-  #endif
+    #if configXT_INTEXC_HOOKS
+        #define XT_INTEXC_HOOKS    1    /* Enables exception hooks */
+    #endif
 #endif
 
-#if (!XT_SIMULATOR) && (!XT_BOARD)
-  #error Either XT_SIMULATOR or XT_BOARD must be defined.
+#if ( !XT_SIMULATOR ) && ( !XT_BOARD )
+    #error Either XT_SIMULATOR or XT_BOARD must be defined.
 #endif
 
 
 /*
-Name of RTOS (for messages).
-*/
+ * Name of RTOS (for messages).
+ */
 #define XT_RTOS_NAME    FreeRTOS
 
 /*
-Check some Xtensa configuration requirements and report error if not met.
-Error messages can be customize to the RTOS port.
-*/
+ * Check some Xtensa configuration requirements and report error if not met.
+ * Error messages can be customize to the RTOS port.
+ */
 
 #if !XCHAL_HAVE_XEA2
-#error "FreeRTOS/Xtensa requires XEA2 (exception architecture 2)."
+    #error "FreeRTOS/Xtensa requires XEA2 (exception architecture 2)."
 #endif
 
 
 /*******************************************************************************
-
-RTOS CALLOUT MACROS MAPPED TO RTOS PORT-SPECIFIC FUNCTIONS.
-
-Define callout macros used in generic Xtensa code to interact with the RTOS.
-The macros are simply the function names for use in calls from assembler code.
-Some of these functions may call back to generic functions in xtensa_context.h .
-
+*
+*  RTOS CALLOUT MACROS MAPPED TO RTOS PORT-SPECIFIC FUNCTIONS.
+*
+*  Define callout macros used in generic Xtensa code to interact with the RTOS.
+*  The macros are simply the function names for use in calls from assembler code.
+*  Some of these functions may call back to generic functions in xtensa_context.h .
+*
 *******************************************************************************/
 
 /*
-Inform RTOS of entry into an interrupt handler that will affect it.
-Allows RTOS to manage switch to any system stack and count nesting level.
-Called after minimal context has been saved, with interrupts disabled.
-RTOS port can call0 _xt_context_save to save the rest of the context.
-May only be called from assembly code by the 'call0' instruction.
-*/
-// void XT_RTOS_INT_ENTER(void)
-#define XT_RTOS_INT_ENTER   _frxt_int_enter
+ * Inform RTOS of entry into an interrupt handler that will affect it.
+ * Allows RTOS to manage switch to any system stack and count nesting level.
+ * Called after minimal context has been saved, with interrupts disabled.
+ * RTOS port can call0 _xt_context_save to save the rest of the context.
+ * May only be called from assembly code by the 'call0' instruction.
+ */
+/* void XT_RTOS_INT_ENTER(void) */
+#define XT_RTOS_INT_ENTER    _frxt_int_enter
 
 /*
-Inform RTOS of completion of an interrupt handler, and give control to
-RTOS to perform thread/task scheduling, switch back from any system stack
-and restore the context, and return to the exit dispatcher saved in the
-stack frame at XT_STK_EXIT. RTOS port can call0 _xt_context_restore
-to save the context saved in XT_RTOS_INT_ENTER via _xt_context_save,
-leaving only a minimal part of the context to be restored by the exit
-dispatcher. This function does not return to the place it was called from.
-May only be called from assembly code by the 'call0' instruction.
-*/
-// void XT_RTOS_INT_EXIT(void)
+ * Inform RTOS of completion of an interrupt handler, and give control to
+ * RTOS to perform thread/task scheduling, switch back from any system stack
+ * and restore the context, and return to the exit dispatcher saved in the
+ * stack frame at XT_STK_EXIT. RTOS port can call0 _xt_context_restore
+ * to save the context saved in XT_RTOS_INT_ENTER via _xt_context_save,
+ * leaving only a minimal part of the context to be restored by the exit
+ * dispatcher. This function does not return to the place it was called from.
+ * May only be called from assembly code by the 'call0' instruction.
+ */
+/* void XT_RTOS_INT_EXIT(void) */
 #define XT_RTOS_INT_EXIT    _frxt_int_exit
 
 /*
-Inform RTOS of the occurrence of a tick timer interrupt.
-If RTOS has no tick timer, leave XT_RTOS_TIMER_INT undefined.
-May be coded in or called from C or assembly, per ABI conventions.
-RTOS may optionally define XT_TICK_PER_SEC in its own way (eg. macro).
-*/
-// void XT_RTOS_TIMER_INT(void)
-#define XT_RTOS_TIMER_INT   _frxt_timer_int
-#define XT_TICK_PER_SEC     configTICK_RATE_HZ
+ * Inform RTOS of the occurrence of a tick timer interrupt.
+ * If RTOS has no tick timer, leave XT_RTOS_TIMER_INT undefined.
+ * May be coded in or called from C or assembly, per ABI conventions.
+ * RTOS may optionally define XT_TICK_PER_SEC in its own way (eg. macro).
+ */
+/* void XT_RTOS_TIMER_INT(void) */
+#define XT_RTOS_TIMER_INT    _frxt_timer_int
+#define XT_TICK_PER_SEC      configTICK_RATE_HZ
 
 /*
-Return in a15 the base address of the co-processor state save area for the
-thread that triggered a co-processor exception, or 0 if no thread was running.
-The state save area is structured as defined in xtensa_context.h and has size
-XT_CP_SIZE. Co-processor instructions should only be used in thread code, never
-in interrupt handlers or the RTOS kernel. May only be called from assembly code
-and by the 'call0' instruction. A result of 0 indicates an unrecoverable error.
-The implementation may use only a2-4, a15 (all other regs must be preserved).
-*/
-// void* XT_RTOS_CP_STATE(void)
+ * Return in a15 the base address of the co-processor state save area for the
+ * thread that triggered a co-processor exception, or 0 if no thread was running.
+ * The state save area is structured as defined in xtensa_context.h and has size
+ * XT_CP_SIZE. Co-processor instructions should only be used in thread code, never
+ * in interrupt handlers or the RTOS kernel. May only be called from assembly code
+ * and by the 'call0' instruction. A result of 0 indicates an unrecoverable error.
+ * The implementation may use only a2-4, a15 (all other regs must be preserved).
+ */
+/* void* XT_RTOS_CP_STATE(void) */
 #define XT_RTOS_CP_STATE    _frxt_task_coproc_state
 
 
 /*******************************************************************************
-
-HOOKS TO DYNAMICALLY INSTALL INTERRUPT AND EXCEPTION HANDLERS PER LEVEL.
-
-This Xtensa RTOS port provides hooks for dynamically installing exception
-and interrupt handlers to facilitate automated testing where each test
-case can install its own handler for user exceptions and each interrupt
-priority (level). This consists of an array of function pointers indexed
-by interrupt priority, with index 0 being the user exception handler hook.
-Each entry in the array is initially 0, and may be replaced by a function
-pointer of type XT_INTEXC_HOOK. A handler may be uninstalled by installing 0.
-
-The handler for low and medium priority obeys ABI conventions so may be coded
-in C. For the exception handler, the cause is the contents of the EXCCAUSE
-reg, and the result is -1 if handled, else the cause (still needs handling).
-For interrupt handlers, the cause is a mask of pending enabled interrupts at
-that level, and the result is the same mask with the bits for the handled
-interrupts cleared (those not cleared still need handling). This allows a test
-case to either pre-handle or override the default handling for the exception
-or interrupt level (see xtensa_vectors.S).
-
-High priority handlers (including NMI) must be coded in assembly, are always
-called by 'call0' regardless of ABI, must preserve all registers except a0,
-and must not use or modify the interrupted stack. The hook argument 'cause'
-is not passed and the result is ignored, so as not to burden the caller with
-saving and restoring a2 (it assumes only one interrupt per level - see the
-discussion in high priority interrupts in xtensa_vectors.S). The handler
-therefore should be coded to prototype 'void h(void)' even though it plugs
-into an array of handlers of prototype 'unsigned h(unsigned)'.
-
-To enable interrupt/exception hooks, compile the RTOS with '-DXT_INTEXC_HOOKS'.
-
+*
+*  HOOKS TO DYNAMICALLY INSTALL INTERRUPT AND EXCEPTION HANDLERS PER LEVEL.
+*
+*  This Xtensa RTOS port provides hooks for dynamically installing exception
+*  and interrupt handlers to facilitate automated testing where each test
+*  case can install its own handler for user exceptions and each interrupt
+*  priority (level). This consists of an array of function pointers indexed
+*  by interrupt priority, with index 0 being the user exception handler hook.
+*  Each entry in the array is initially 0, and may be replaced by a function
+*  pointer of type XT_INTEXC_HOOK. A handler may be uninstalled by installing 0.
+*
+*  The handler for low and medium priority obeys ABI conventions so may be coded
+*  in C. For the exception handler, the cause is the contents of the EXCCAUSE
+*  reg, and the result is -1 if handled, else the cause (still needs handling).
+*  For interrupt handlers, the cause is a mask of pending enabled interrupts at
+*  that level, and the result is the same mask with the bits for the handled
+*  interrupts cleared (those not cleared still need handling). This allows a test
+*  case to either pre-handle or override the default handling for the exception
+*  or interrupt level (see xtensa_vectors.S).
+*
+*  High priority handlers (including NMI) must be coded in assembly, are always
+*  called by 'call0' regardless of ABI, must preserve all registers except a0,
+*  and must not use or modify the interrupted stack. The hook argument 'cause'
+*  is not passed and the result is ignored, so as not to burden the caller with
+*  saving and restoring a2 (it assumes only one interrupt per level - see the
+*  discussion in high priority interrupts in xtensa_vectors.S). The handler
+*  therefore should be coded to prototype 'void h(void)' even though it plugs
+*  into an array of handlers of prototype 'unsigned h(unsigned)'.
+*
+*  To enable interrupt/exception hooks, compile the RTOS with '-DXT_INTEXC_HOOKS'.
+*
 *******************************************************************************/
 
-#define XT_INTEXC_HOOK_NUM  (1 + XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI)
+#define XT_INTEXC_HOOK_NUM    ( 1 + XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI )
 
 #ifndef __ASSEMBLER__
-typedef unsigned (*XT_INTEXC_HOOK)(unsigned cause);
-extern  volatile XT_INTEXC_HOOK _xt_intexc_hooks[XT_INTEXC_HOOK_NUM];
+    typedef unsigned (* XT_INTEXC_HOOK)( unsigned cause );
+    extern volatile XT_INTEXC_HOOK _xt_intexc_hooks[ XT_INTEXC_HOOK_NUM ];
 #endif
 
 
 /*******************************************************************************
-
-CONVENIENCE INCLUSIONS.
-
-Ensures RTOS specific files need only include this one Xtensa-generic header.
-These headers are included last so they can use the RTOS definitions above.
-
+*
+*  CONVENIENCE INCLUSIONS.
+*
+*  Ensures RTOS specific files need only include this one Xtensa-generic header.
+*  These headers are included last so they can use the RTOS definitions above.
+*
 *******************************************************************************/
 
 #include    "xtensa_context.h"
 
 #ifdef XT_RTOS_TIMER_INT
-#include    "xtensa_timer.h"
+    #include    "xtensa_timer.h"
 #endif
 
 
 /*******************************************************************************
-
-Xtensa Port Version.
-
+*
+*  Xtensa Port Version.
+*
 *******************************************************************************/
 
-#define XTENSA_PORT_VERSION             1.7
-#define XTENSA_PORT_VERSION_STRING      "1.7"
+#define XTENSA_PORT_VERSION           1.7
+#define XTENSA_PORT_VERSION_STRING    "1.7"
 
 #endif /* XTENSA_RTOS_H */
diff --git a/portable/ThirdParty/XCC/Xtensa/xtensa_timer.h b/portable/ThirdParty/XCC/Xtensa/xtensa_timer.h
index cefac70f2..ecaf3f4e9 100644
--- a/portable/ThirdParty/XCC/Xtensa/xtensa_timer.h
+++ b/portable/ThirdParty/XCC/Xtensa/xtensa_timer.h
@@ -1,4 +1,4 @@
- /*
+/*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
@@ -47,118 +47,118 @@
 #define XTENSA_TIMER_H
 
 #ifdef __ASSEMBLER__
-#include    <xtensa/coreasm.h>
+    #include    <xtensa/coreasm.h>
 #endif
 
 #include    <xtensa/corebits.h>
 #include    <xtensa/config/system.h>
 
-#include    "xtensa_rtos.h"     /* in case this wasn't included directly */
+#include    "xtensa_rtos.h" /* in case this wasn't included directly */
 
 #include    <FreeRTOSConfig.h>
 
 /*
-Select timer to use for periodic tick, and determine its interrupt number
-and priority. User may specify a timer by defining XT_TIMER_INDEX with -D,
-in which case its validity is checked (it must exist in this core and must
-not be on a high priority interrupt - an error will be reported in invalid).
-Otherwise select the first low or medium priority interrupt timer available.
-*/
+ * Select timer to use for periodic tick, and determine its interrupt number
+ * and priority. User may specify a timer by defining XT_TIMER_INDEX with -D,
+ * in which case its validity is checked (it must exist in this core and must
+ * not be on a high priority interrupt - an error will be reported in invalid).
+ * Otherwise select the first low or medium priority interrupt timer available.
+ */
 #if XCHAL_NUM_TIMERS == 0
 
-  #error "This Xtensa configuration is unsupported, it has no timers."
+    #error "This Xtensa configuration is unsupported, it has no timers."
 
 #else
 
-#ifndef XT_TIMER_INDEX
-  #if XCHAL_TIMER3_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
-    #if XCHAL_INT_LEVEL(XCHAL_TIMER3_INTERRUPT) <= XCHAL_EXCM_LEVEL
-      #undef  XT_TIMER_INDEX
-      #define XT_TIMER_INDEX    3
+    #ifndef XT_TIMER_INDEX
+        #if XCHAL_TIMER3_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
+            #if XCHAL_INT_LEVEL( XCHAL_TIMER3_INTERRUPT ) <= XCHAL_EXCM_LEVEL
+                #undef  XT_TIMER_INDEX
+                #define XT_TIMER_INDEX    3
+            #endif
+        #endif
+        #if XCHAL_TIMER2_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
+            #if XCHAL_INT_LEVEL( XCHAL_TIMER2_INTERRUPT ) <= XCHAL_EXCM_LEVEL
+                #undef  XT_TIMER_INDEX
+                #define XT_TIMER_INDEX    2
+            #endif
+        #endif
+        #if XCHAL_TIMER1_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
+            #if XCHAL_INT_LEVEL( XCHAL_TIMER1_INTERRUPT ) <= XCHAL_EXCM_LEVEL
+                #undef  XT_TIMER_INDEX
+                #define XT_TIMER_INDEX    1
+            #endif
+        #endif
+        #if XCHAL_TIMER0_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
+            #if XCHAL_INT_LEVEL( XCHAL_TIMER0_INTERRUPT ) <= XCHAL_EXCM_LEVEL
+                #undef  XT_TIMER_INDEX
+                #define XT_TIMER_INDEX    0
+            #endif
+        #endif
+    #endif /* ifndef XT_TIMER_INDEX */
+    #ifndef XT_TIMER_INDEX
+        #error "There is no suitable timer in this Xtensa configuration."
     #endif
-  #endif
-  #if XCHAL_TIMER2_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
-    #if XCHAL_INT_LEVEL(XCHAL_TIMER2_INTERRUPT) <= XCHAL_EXCM_LEVEL
-      #undef  XT_TIMER_INDEX
-      #define XT_TIMER_INDEX    2
-    #endif
-  #endif
-  #if XCHAL_TIMER1_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
-    #if XCHAL_INT_LEVEL(XCHAL_TIMER1_INTERRUPT) <= XCHAL_EXCM_LEVEL
-      #undef  XT_TIMER_INDEX
-      #define XT_TIMER_INDEX    1
-    #endif
-  #endif
-  #if XCHAL_TIMER0_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
-    #if XCHAL_INT_LEVEL(XCHAL_TIMER0_INTERRUPT) <= XCHAL_EXCM_LEVEL
-      #undef  XT_TIMER_INDEX
-      #define XT_TIMER_INDEX    0
-    #endif
-  #endif
-#endif
-#ifndef XT_TIMER_INDEX
-  #error "There is no suitable timer in this Xtensa configuration."
-#endif
 
-#define XT_CCOMPARE             (CCOMPARE + XT_TIMER_INDEX)
-#define XT_TIMER_INTNUM         XCHAL_TIMER_INTERRUPT(XT_TIMER_INDEX)
-#define XT_TIMER_INTPRI         XCHAL_INT_LEVEL(XT_TIMER_INTNUM)
-#define XT_TIMER_INTEN          (1 << XT_TIMER_INTNUM)
+    #define XT_CCOMPARE        ( CCOMPARE + XT_TIMER_INDEX )
+    #define XT_TIMER_INTNUM    XCHAL_TIMER_INTERRUPT( XT_TIMER_INDEX )
+    #define XT_TIMER_INTPRI    XCHAL_INT_LEVEL( XT_TIMER_INTNUM )
+    #define XT_TIMER_INTEN     ( 1 << XT_TIMER_INTNUM )
 
-#if XT_TIMER_INTNUM == XTHAL_TIMER_UNCONFIGURED
-  #error "The timer selected by XT_TIMER_INDEX does not exist in this core."
-#elif XT_TIMER_INTPRI > XCHAL_EXCM_LEVEL
-  #error "The timer interrupt cannot be high priority (use medium or low)."
-#endif
+    #if XT_TIMER_INTNUM == XTHAL_TIMER_UNCONFIGURED
+        #error "The timer selected by XT_TIMER_INDEX does not exist in this core."
+    #elif XT_TIMER_INTPRI > XCHAL_EXCM_LEVEL
+        #error "The timer interrupt cannot be high priority (use medium or low)."
+    #endif
 
 #endif /* XCHAL_NUM_TIMERS */
 
 /*
-Set processor clock frequency, used to determine clock divisor for timer tick.
-User should BE SURE TO ADJUST THIS for the Xtensa platform being used.
-If using a supported board via the board-independent API defined in xtbsp.h,
-this may be left undefined and frequency and tick divisor will be computed
-and cached during run-time initialization.
-
-NOTE ON SIMULATOR:
-Under the Xtensa instruction set simulator, the frequency can only be estimated
-because it depends on the speed of the host and the version of the simulator.
-Also because it runs much slower than hardware, it is not possible to achieve
-real-time performance for most applications under the simulator. A frequency
-too low does not allow enough time between timer interrupts, starving threads.
-To obtain a more convenient but non-real-time tick duration on the simulator,
-compile with xt-xcc option "-DXT_SIMULATOR".
-Adjust this frequency to taste (it's not real-time anyway!).
-*/
-#if defined(XT_SIMULATOR) && !defined(XT_CLOCK_FREQ)
-#define XT_CLOCK_FREQ       configCPU_CLOCK_HZ
+ * Set processor clock frequency, used to determine clock divisor for timer tick.
+ * User should BE SURE TO ADJUST THIS for the Xtensa platform being used.
+ * If using a supported board via the board-independent API defined in xtbsp.h,
+ * this may be left undefined and frequency and tick divisor will be computed
+ * and cached during run-time initialization.
+ *
+ * NOTE ON SIMULATOR:
+ * Under the Xtensa instruction set simulator, the frequency can only be estimated
+ * because it depends on the speed of the host and the version of the simulator.
+ * Also because it runs much slower than hardware, it is not possible to achieve
+ * real-time performance for most applications under the simulator. A frequency
+ * too low does not allow enough time between timer interrupts, starving threads.
+ * To obtain a more convenient but non-real-time tick duration on the simulator,
+ * compile with xt-xcc option "-DXT_SIMULATOR".
+ * Adjust this frequency to taste (it's not real-time anyway!).
+ */
+#if defined( XT_SIMULATOR ) && !defined( XT_CLOCK_FREQ )
+    #define XT_CLOCK_FREQ    configCPU_CLOCK_HZ
 #endif
 
-#if !defined(XT_CLOCK_FREQ) && !defined(XT_BOARD)
-  #error "XT_CLOCK_FREQ must be defined for the target platform."
+#if !defined( XT_CLOCK_FREQ ) && !defined( XT_BOARD )
+    #error "XT_CLOCK_FREQ must be defined for the target platform."
 #endif
 
 /*
-Default number of timer "ticks" per second (default 100 for 10ms tick).
-RTOS may define this in its own way (if applicable) in xtensa_rtos.h.
-User may redefine this to an optimal value for the application, either by
-editing this here or in xtensa_rtos.h, or compiling with xt-xcc option
-"-DXT_TICK_PER_SEC=<value>" where <value> is a suitable number.
-*/
+ * Default number of timer "ticks" per second (default 100 for 10ms tick).
+ * RTOS may define this in its own way (if applicable) in xtensa_rtos.h.
+ * User may redefine this to an optimal value for the application, either by
+ * editing this here or in xtensa_rtos.h, or compiling with xt-xcc option
+ * "-DXT_TICK_PER_SEC=<value>" where <value> is a suitable number.
+ */
 #ifndef XT_TICK_PER_SEC
-#define XT_TICK_PER_SEC    configTICK_RATE_HZ        /* 10 ms tick = 100 ticks per second */
+    #define XT_TICK_PER_SEC    configTICK_RATE_HZ    /* 10 ms tick = 100 ticks per second */
 #endif
 
 /*
-Derivation of clock divisor for timer tick and interrupt (one per tick).
-*/
+ * Derivation of clock divisor for timer tick and interrupt (one per tick).
+ */
 #ifdef XT_CLOCK_FREQ
-#define XT_TICK_DIVISOR     (XT_CLOCK_FREQ / XT_TICK_PER_SEC)
+    #define XT_TICK_DIVISOR    ( XT_CLOCK_FREQ / XT_TICK_PER_SEC )
 #endif
 
 #ifndef __ASSEMBLER__
-extern unsigned _xt_tick_divisor;
-extern void     _xt_tick_divisor_init(void);
+    extern unsigned _xt_tick_divisor;
+    extern void _xt_tick_divisor_init( void );
 #endif
 
-#endif  /* XTENSA_TIMER_H */
+#endif /* XTENSA_TIMER_H */
diff --git a/portable/ThirdParty/xClang/XCOREAI/port.c b/portable/ThirdParty/xClang/XCOREAI/port.c
index 0d7307383..ba4598b6b 100644
--- a/portable/ThirdParty/xClang/XCOREAI/port.c
+++ b/portable/ThirdParty/xClang/XCOREAI/port.c
@@ -1,4 +1,4 @@
-// Copyright (c) 2019, XMOS Ltd, All rights reserved
+/* Copyright (c) 2019, XMOS Ltd, All rights reserved */
 
 /* Scheduler includes. */
 #include "FreeRTOS.h"
@@ -16,139 +16,144 @@ uint32_t ulPortYieldRequired[ portMAX_CORE_COUNT ] = { pdFALSE };
 
 void vIntercoreInterruptISR( void )
 {
-	int xCoreID;
+    int xCoreID;
 
-//	debug_printf( "In KCALL: %u\n", ulData );
-	xCoreID = rtos_core_id_get();
-	ulPortYieldRequired[ xCoreID ] = pdTRUE;
+/*	debug_printf( "In KCALL: %u\n", ulData ); */
+    xCoreID = rtos_core_id_get();
+    ulPortYieldRequired[ xCoreID ] = pdTRUE;
 }
 /*-----------------------------------------------------------*/
 
 DEFINE_RTOS_INTERRUPT_CALLBACK( pxKernelTimerISR, pvData )
 {
-	uint32_t ulLastTrigger;
-	uint32_t ulNow;
-	int xCoreID;
+    uint32_t ulLastTrigger;
+    uint32_t ulNow;
+    int xCoreID;
     UBaseType_t uxSavedInterruptStatus;
 
-	xCoreID = 0;
+    xCoreID = 0;
 
-	configASSERT( xCoreID == rtos_core_id_get() );
+    configASSERT( xCoreID == rtos_core_id_get() );
 
-	/* Need the next interrupt to be scheduled relative to
-	 * the current trigger time, rather than the current
-	 * time. */
-	ulLastTrigger = hwtimer_get_trigger_time( xKernelTimer );
+    /* Need the next interrupt to be scheduled relative to
+     * the current trigger time, rather than the current
+     * time. */
+    ulLastTrigger = hwtimer_get_trigger_time( xKernelTimer );
 
-	/* Check to see if the ISR is late. If it is, we don't
-	 * want to schedule the next interrupt to be in the past. */
-	ulNow = hwtimer_get_time( xKernelTimer );
-	if( ulNow - ulLastTrigger >= configCPU_CLOCK_HZ / configTICK_RATE_HZ )
-	{
-		ulLastTrigger = ulNow;
-	}
+    /* Check to see if the ISR is late. If it is, we don't
+     * want to schedule the next interrupt to be in the past. */
+    ulNow = hwtimer_get_time( xKernelTimer );
 
-	ulLastTrigger += configCPU_CLOCK_HZ / configTICK_RATE_HZ;
-	hwtimer_change_trigger_time( xKernelTimer, ulLastTrigger );
+    if( ulNow - ulLastTrigger >= configCPU_CLOCK_HZ / configTICK_RATE_HZ )
+    {
+        ulLastTrigger = ulNow;
+    }
 
-#if configUPDATE_RTOS_TIME_FROM_TICK_ISR == 1
-	rtos_time_increment( RTOS_TICK_PERIOD( configTICK_RATE_HZ ) );
-#endif
+    ulLastTrigger += configCPU_CLOCK_HZ / configTICK_RATE_HZ;
+    hwtimer_change_trigger_time( xKernelTimer, ulLastTrigger );
+
+    #if configUPDATE_RTOS_TIME_FROM_TICK_ISR == 1
+        rtos_time_increment( RTOS_TICK_PERIOD( configTICK_RATE_HZ ) );
+    #endif
 
     uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
-	if( xTaskIncrementTick() != pdFALSE )
-	{
-		ulPortYieldRequired[ xCoreID ] = pdTRUE;
-	}
+
+    if( xTaskIncrementTick() != pdFALSE )
+    {
+        ulPortYieldRequired[ xCoreID ] = pdTRUE;
+    }
+
     taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
 }
 /*-----------------------------------------------------------*/
 
 void vPortYieldOtherCore( int xOtherCoreID )
 {
-	int xCoreID;
+    int xCoreID;
 
-	/*
-	 * This function must be called from within a critical section.
-	 */
+    /*
+     * This function must be called from within a critical section.
+     */
 
-	xCoreID = rtos_core_id_get();
+    xCoreID = rtos_core_id_get();
 
-//	debug_printf("%d->%d\n", xCoreID, xOtherCoreID);
+/*	debug_printf("%d->%d\n", xCoreID, xOtherCoreID); */
 
-//	debug_printf("Yield core %d from %d\n", xOtherCoreID, xCoreID );
+/*	debug_printf("Yield core %d from %d\n", xOtherCoreID, xCoreID ); */
 
-	rtos_irq( xOtherCoreID, xCoreID );
+    rtos_irq( xOtherCoreID, xCoreID );
 }
 /*-----------------------------------------------------------*/
 
 static int prvCoreInit( void )
 {
-	int xCoreID;
+    int xCoreID;
 
-	xCoreID = rtos_core_register();
-	debug_printf( "Logical Core %d initializing as FreeRTOS Core %d\n", get_logical_core_id(), xCoreID );
+    xCoreID = rtos_core_register();
+    debug_printf( "Logical Core %d initializing as FreeRTOS Core %d\n", get_logical_core_id(), xCoreID );
 
-	asm volatile (
-			"ldap r11, kexcept\n\t"
-			"set kep, r11\n\t"
-			:
-			:
-			: "r11"
-	);
+    asm volatile (
+        "ldap r11, kexcept\n\t"
+        "set kep, r11\n\t"
+        :
+        :
+        : "r11"
+        );
 
-	rtos_irq_enable( configNUMBER_OF_CORES );
+    rtos_irq_enable( configNUMBER_OF_CORES );
 
-	/*
-	 * All threads wait here until all have enabled IRQs
-	 */
-	while( rtos_irq_ready() == pdFALSE );
+    /*
+     * All threads wait here until all have enabled IRQs
+     */
+    while( rtos_irq_ready() == pdFALSE )
+    {
+    }
 
-	if( xCoreID == 0 )
-	{
-		uint32_t ulNow;
-		ulNow = hwtimer_get_time( xKernelTimer );
-//		debug_printf( "The time is now (%u)\n", ulNow );
+    if( xCoreID == 0 )
+    {
+        uint32_t ulNow;
+        ulNow = hwtimer_get_time( xKernelTimer );
+/*		debug_printf( "The time is now (%u)\n", ulNow ); */
 
-		ulNow += configCPU_CLOCK_HZ / configTICK_RATE_HZ;
+        ulNow += configCPU_CLOCK_HZ / configTICK_RATE_HZ;
 
-		triggerable_setup_interrupt_callback( xKernelTimer, NULL, RTOS_INTERRUPT_CALLBACK( pxKernelTimerISR ) );
-		hwtimer_set_trigger_time( xKernelTimer, ulNow );
-		triggerable_enable_trigger( xKernelTimer );
-	}
+        triggerable_setup_interrupt_callback( xKernelTimer, NULL, RTOS_INTERRUPT_CALLBACK( pxKernelTimerISR ) );
+        hwtimer_set_trigger_time( xKernelTimer, ulNow );
+        triggerable_enable_trigger( xKernelTimer );
+    }
 
-	return xCoreID;
+    return xCoreID;
 }
 /*-----------------------------------------------------------*/
 
 DEFINE_RTOS_KERNEL_ENTRY( void, vPortStartSchedulerOnCore, void )
 {
-	int xCoreID;
+    int xCoreID;
 
-	xCoreID = prvCoreInit();
+    xCoreID = prvCoreInit();
 
-	#if( configUSE_CORE_INIT_HOOK == 1 )
-	{
-		extern void vApplicationCoreInitHook( BaseType_t xCoreID );
+    #if ( configUSE_CORE_INIT_HOOK == 1 )
+    {
+        extern void vApplicationCoreInitHook( BaseType_t xCoreID );
 
-		vApplicationCoreInitHook( xCoreID );
-	}
-	#endif
+        vApplicationCoreInitHook( xCoreID );
+    }
+    #endif
 
-	debug_printf( "FreeRTOS Core %d initialized\n", xCoreID );
+    debug_printf( "FreeRTOS Core %d initialized\n", xCoreID );
 
-	/*
-	 * Restore the context of the first thread
-	 * to run and jump into it.
-	 */
-	asm volatile (
-			"mov r6, %0\n\t" /* R6 must be the FreeRTOS core ID*/
-			"ldaw r5, dp[pxCurrentTCBs]\n\t" /* R5 must be the TCB list which is indexed by R6 */
-			"bu _freertos_restore_ctx\n\t"
-			: /* no outputs */
-			: "r"(xCoreID)
-			: "r5", "r6"
-	);
+    /*
+     * Restore the context of the first thread
+     * to run and jump into it.
+     */
+    asm volatile (
+        "mov r6, %0\n\t"                 /* R6 must be the FreeRTOS core ID*/
+        "ldaw r5, dp[pxCurrentTCBs]\n\t" /* R5 must be the TCB list which is indexed by R6 */
+        "bu _freertos_restore_ctx\n\t"
+        :                                /* no outputs */
+        : "r" ( xCoreID )
+        : "r5", "r6"
+        );
 }
 /*-----------------------------------------------------------*/
 
@@ -159,70 +164,73 @@ DEFINE_RTOS_KERNEL_ENTRY( void, vPortStartSchedulerOnCore, void )
 /*
  * See header file for description.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
-	//debug_printf( "Top of stack was %p for task %p\n", pxTopOfStack, pxCode );
-	/*
-	 * Grow the thread's stack by portTHREAD_CONTEXT_STACK_GROWTH
-	 * so we can push the context onto it.
-	 */
-	pxTopOfStack -= portTHREAD_CONTEXT_STACK_GROWTH;
+    /*debug_printf( "Top of stack was %p for task %p\n", pxTopOfStack, pxCode ); */
 
-	uint32_t dp;
-	uint32_t cp;
+    /*
+     * Grow the thread's stack by portTHREAD_CONTEXT_STACK_GROWTH
+     * so we can push the context onto it.
+     */
+    pxTopOfStack -= portTHREAD_CONTEXT_STACK_GROWTH;
 
-	/*
-	 * We need to get the current CP and DP pointers.
-	 */
-	asm volatile (
-			"ldaw r11, cp[0]\n\t" /* get CP into R11 */
-			"mov %0, r11\n\t" /* get R11 (CP) into cp */
-			"ldaw r11, dp[0]\n\t" /* get DP into R11 */
-			"mov %1, r11\n\t" /* get R11 (DP) into dp */
-			: "=r"(cp), "=r"(dp) /* output 0 is cp, output 1 is dp */
-			: /* there are no inputs */
-			: "r11" /* R11 gets clobbered */
-	);
+    uint32_t dp;
+    uint32_t cp;
 
-	/*
-	 * Push the thread context onto the stack.
-	 * Saved PC will point to the new thread's
-	 * entry pointer.
-	 * Interrupts will default to enabled.
-	 * KEDI is also set to enable dual issue mode
-	 * upon kernel entry.
-	 */
-	pxTopOfStack[ 1 ] = ( StackType_t ) pxCode;       /* SP[1]  := SPC */
+    /*
+     * We need to get the current CP and DP pointers.
+     */
+    asm volatile (
+        "ldaw r11, cp[0]\n\t"      /* get CP into R11 */
+        "mov %0, r11\n\t"          /* get R11 (CP) into cp */
+        "ldaw r11, dp[0]\n\t"      /* get DP into R11 */
+        "mov %1, r11\n\t"          /* get R11 (DP) into dp */
+        : "=r" ( cp ), "=r" ( dp ) /* output 0 is cp, output 1 is dp */
+        :                          /* there are no inputs */
+        : "r11"                    /* R11 gets clobbered */
+        );
+
+    /*
+     * Push the thread context onto the stack.
+     * Saved PC will point to the new thread's
+     * entry pointer.
+     * Interrupts will default to enabled.
+     * KEDI is also set to enable dual issue mode
+     * upon kernel entry.
+     */
+    pxTopOfStack[ 1 ] = ( StackType_t ) pxCode;       /* SP[1]  := SPC */
     pxTopOfStack[ 2 ] = XS1_SR_IEBLE_MASK
-                      | XS1_SR_KEDI_MASK;             /* SP[2]  := SSR */
-	pxTopOfStack[ 3 ] = 0x00000000;                   /* SP[3]  := SED */
-	pxTopOfStack[ 4 ] = 0x00000000;                   /* SP[4]  := ET */
-	pxTopOfStack[ 5 ] = dp;                           /* SP[5]  := DP */
-	pxTopOfStack[ 6 ] = cp;                           /* SP[6]  := CP */
-	pxTopOfStack[ 7 ] = 0x00000000;                   /* SP[7]  := LR */
-	pxTopOfStack[ 8 ] = ( StackType_t ) pvParameters; /* SP[8]  := R0 */
-	pxTopOfStack[ 9 ] = 0x01010101;                   /* SP[9]  := R1 */
-	pxTopOfStack[ 10 ] = 0x02020202;                  /* SP[10] := R2 */
-	pxTopOfStack[ 11 ] = 0x03030303;                  /* SP[11] := R3 */
-	pxTopOfStack[ 12 ] = 0x04040404;                  /* SP[12] := R4 */
-	pxTopOfStack[ 13 ] = 0x05050505;                  /* SP[13] := R5 */
-	pxTopOfStack[ 14 ] = 0x06060606;                  /* SP[14] := R6 */
-	pxTopOfStack[ 15 ] = 0x07070707;                  /* SP[15] := R7 */
-	pxTopOfStack[ 16 ] = 0x08080808;                  /* SP[16] := R8 */
-	pxTopOfStack[ 17 ] = 0x09090909;                  /* SP[17] := R9 */
-	pxTopOfStack[ 18 ] = 0x10101010;                  /* SP[18] := R10 */
-	pxTopOfStack[ 19 ] = 0x11111111;                  /* SP[19] := R11 */
-	pxTopOfStack[ 20 ] = 0x00000000;                  /* SP[20] := vH and vSR */
-	memset(&pxTopOfStack[21], 0, 32);                 /* SP[21 - 28] := vR   */
-	memset(&pxTopOfStack[29], 1, 32);                 /* SP[29 - 36] := vD   */
-	memset(&pxTopOfStack[37], 2, 32);                 /* SP[37 - 44] := vC   */
+                        | XS1_SR_KEDI_MASK;           /* SP[2]  := SSR */
+    pxTopOfStack[ 3 ] = 0x00000000;                   /* SP[3]  := SED */
+    pxTopOfStack[ 4 ] = 0x00000000;                   /* SP[4]  := ET */
+    pxTopOfStack[ 5 ] = dp;                           /* SP[5]  := DP */
+    pxTopOfStack[ 6 ] = cp;                           /* SP[6]  := CP */
+    pxTopOfStack[ 7 ] = 0x00000000;                   /* SP[7]  := LR */
+    pxTopOfStack[ 8 ] = ( StackType_t ) pvParameters; /* SP[8]  := R0 */
+    pxTopOfStack[ 9 ] = 0x01010101;                   /* SP[9]  := R1 */
+    pxTopOfStack[ 10 ] = 0x02020202;                  /* SP[10] := R2 */
+    pxTopOfStack[ 11 ] = 0x03030303;                  /* SP[11] := R3 */
+    pxTopOfStack[ 12 ] = 0x04040404;                  /* SP[12] := R4 */
+    pxTopOfStack[ 13 ] = 0x05050505;                  /* SP[13] := R5 */
+    pxTopOfStack[ 14 ] = 0x06060606;                  /* SP[14] := R6 */
+    pxTopOfStack[ 15 ] = 0x07070707;                  /* SP[15] := R7 */
+    pxTopOfStack[ 16 ] = 0x08080808;                  /* SP[16] := R8 */
+    pxTopOfStack[ 17 ] = 0x09090909;                  /* SP[17] := R9 */
+    pxTopOfStack[ 18 ] = 0x10101010;                  /* SP[18] := R10 */
+    pxTopOfStack[ 19 ] = 0x11111111;                  /* SP[19] := R11 */
+    pxTopOfStack[ 20 ] = 0x00000000;                  /* SP[20] := vH and vSR */
+    memset( &pxTopOfStack[ 21 ], 0, 32 );             /* SP[21 - 28] := vR   */
+    memset( &pxTopOfStack[ 29 ], 1, 32 );             /* SP[29 - 36] := vD   */
+    memset( &pxTopOfStack[ 37 ], 2, 32 );             /* SP[37 - 44] := vC   */
 
-	//debug_printf( "Top of stack is now %p for task %p\n", pxTopOfStack, pxCode );
+    /*debug_printf( "Top of stack is now %p for task %p\n", pxTopOfStack, pxCode ); */
 
-	/*
-	 * Returns the new top of the stack
-	 */
-	return pxTopOfStack;
+    /*
+     * Returns the new top of the stack
+     */
+    return pxTopOfStack;
 }
 /*-----------------------------------------------------------*/
 
@@ -233,22 +241,22 @@ void vPortStartSMPScheduler( void );
  */
 BaseType_t xPortStartScheduler( void )
 {
-	if( ( configNUMBER_OF_CORES > portMAX_CORE_COUNT ) || ( configNUMBER_OF_CORES <= 0 ) )
-	{
-		return pdFAIL;
-	}
+    if( ( configNUMBER_OF_CORES > portMAX_CORE_COUNT ) || ( configNUMBER_OF_CORES <= 0 ) )
+    {
+        return pdFAIL;
+    }
 
-	rtos_locks_initialize();
-	xKernelTimer = hwtimer_alloc();
+    rtos_locks_initialize();
+    xKernelTimer = hwtimer_alloc();
 
-	vPortStartSMPScheduler();
+    vPortStartSMPScheduler();
 
-	return pdPASS;
+    return pdPASS;
 }
 /*-----------------------------------------------------------*/
 
 void vPortEndScheduler( void )
 {
-	/* Do not implement. */
+    /* Do not implement. */
 }
 /*-----------------------------------------------------------*/
diff --git a/portable/ThirdParty/xClang/XCOREAI/portmacro.h b/portable/ThirdParty/xClang/XCOREAI/portmacro.h
index 36907b258..06f2b75dc 100644
--- a/portable/ThirdParty/xClang/XCOREAI/portmacro.h
+++ b/portable/ThirdParty/xClang/XCOREAI/portmacro.h
@@ -1,63 +1,63 @@
-// Copyright (c) 2020, XMOS Ltd, All rights reserved
+/* Copyright (c) 2020, XMOS Ltd, All rights reserved */
 
 #ifndef PORTMACRO_H
-#define PORTMACRO_H
+    #define PORTMACRO_H
 
-#ifndef __ASSEMBLER__
+    #ifndef __ASSEMBLER__
 
 /* Inclusion of xc1.h will result in clock being defined as a type.
  * By default, FreeRTOS will require standard time.h, where clock is a function.
  */
-#ifndef USE_XCORE_CLOCK_TYPE
-#define _clock_defined
-#endif
+        #ifndef USE_XCORE_CLOCK_TYPE
+            #define _clock_defined
+        #endif
 
-#include <xs1.h>
-#include "rtos_support.h"
+        #include <xs1.h>
+        #include "rtos_support.h"
 
-#ifdef __cplusplus
-extern "C" {
-#endif
+        #ifdef __cplusplus
+        extern "C" {
+        #endif
 
 /* Type definitions. */
-#define portSTACK_TYPE	uint32_t
-typedef portSTACK_TYPE StackType_t;
-typedef double portDOUBLE;
-typedef int32_t BaseType_t;
-typedef uint32_t UBaseType_t;
+        #define portSTACK_TYPE    uint32_t
+        typedef portSTACK_TYPE   StackType_t;
+        typedef double           portDOUBLE;
+        typedef int32_t          BaseType_t;
+        typedef uint32_t         UBaseType_t;
 
-#define portBASE_TYPE   BaseType_t
+        #define portBASE_TYPE    BaseType_t
 
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+        #if ( configUSE_16_BIT_TICKS == 1 )
+            typedef uint16_t     TickType_t;
+            #define portMAX_DELAY              ( TickType_t ) 0xffff
+        #else
+            typedef uint32_t     TickType_t;
+            #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC 1
-#endif
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+            #define portTICK_TYPE_IS_ATOMIC    1
+        #endif
 /*-----------------------------------------------------------*/
 
-#endif /* __ASSEMBLER__ */
+    #endif /* __ASSEMBLER__ */
 
 /* Architecture specifics. These can be used by assembly files as well. */
-#define portSTACK_GROWTH			  ( -1 )
-#define portTICK_PERIOD_MS			  ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT			  8
-#define portCRITICAL_NESTING_IN_TCB   1
-#define portMAX_CORE_COUNT            8
-#ifndef configNUMBER_OF_CORES
-#define configNUMBER_OF_CORES         1
-#endif
+    #define portSTACK_GROWTH               ( -1 )
+    #define portTICK_PERIOD_MS             ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+    #define portBYTE_ALIGNMENT             8
+    #define portCRITICAL_NESTING_IN_TCB    1
+    #define portMAX_CORE_COUNT             8
+    #ifndef configNUMBER_OF_CORES
+        #define configNUMBER_OF_CORES      1
+    #endif
 
 /* This may be set to zero in the config file if the rtos_time
-functions are not needed or if it is incremented elsewhere. */
-#ifndef configUPDATE_RTOS_TIME_FROM_TICK_ISR
-#define configUPDATE_RTOS_TIME_FROM_TICK_ISR 1
-#endif
+ *  functions are not needed or if it is incremented elsewhere. */
+    #ifndef configUPDATE_RTOS_TIME_FROM_TICK_ISR
+        #define configUPDATE_RTOS_TIME_FROM_TICK_ISR    1
+    #endif
 
 /*
  * When entering an ISR we need to grow the stack by one more word than
@@ -66,150 +66,149 @@ functions are not needed or if it is incremented elsewhere. */
  * it is OK to store words at SP[0]. Therefore the ISR must leave SP[0] alone
  * even though it is normally not necessary to do so.
  */
-#define portTHREAD_CONTEXT_STACK_GROWTH RTOS_SUPPORT_INTERRUPT_STACK_GROWTH
+    #define portTHREAD_CONTEXT_STACK_GROWTH    RTOS_SUPPORT_INTERRUPT_STACK_GROWTH
 
-#ifndef __ASSEMBLER__
+    #ifndef __ASSEMBLER__
 
 /* Check validity of number of cores specified in config */
-#if ( configNUMBER_OF_CORES < 1 || portMAX_CORE_COUNT < configNUMBER_OF_CORES )
-#error "Invalid number of cores specified in config!"
-#endif
+        #if ( configNUMBER_OF_CORES < 1 || portMAX_CORE_COUNT < configNUMBER_OF_CORES )
+            #error "Invalid number of cores specified in config!"
+        #endif
 
-#define portMEMORY_BARRIER() RTOS_MEMORY_BARRIER()
-#define portTASK_STACK_DEPTH(pxTaskCode) RTOS_THREAD_STACK_SIZE(pxTaskCode)
+        #define portMEMORY_BARRIER()                  RTOS_MEMORY_BARRIER()
+        #define portTASK_STACK_DEPTH( pxTaskCode )    RTOS_THREAD_STACK_SIZE( pxTaskCode )
 /*-----------------------------------------------------------*/
 
 /* Scheduler utilities. */
-#define portYIELD() 	asm volatile( "KCALLI_lu6 0" ::: "memory" )
+        #define portYIELD()    asm volatile ( "KCALLI_lu6 0" ::: "memory" )
 
-#define portEND_SWITCHING_ISR( xSwitchRequired ) \
-do \
-{ \
-	if( xSwitchRequired != pdFALSE ) \
-	{ \
-		extern uint32_t ulPortYieldRequired[ portMAX_CORE_COUNT ]; \
-	    ulPortYieldRequired[ portGET_CORE_ID() ] = pdTRUE; \
-	} \
-} while( 0 )
+        #define portEND_SWITCHING_ISR( xSwitchRequired )               \
+    do                                                                 \
+    {                                                                  \
+        if( xSwitchRequired != pdFALSE )                               \
+        {                                                              \
+            extern uint32_t ulPortYieldRequired[ portMAX_CORE_COUNT ]; \
+            ulPortYieldRequired[ portGET_CORE_ID() ] = pdTRUE;         \
+        }                                                              \
+    } while( 0 )
 
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+        #define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
 /* SMP utilities. */
-#define portGET_CORE_ID() rtos_core_id_get()
+        #define portGET_CORE_ID()      rtos_core_id_get()
 
-void vPortYieldOtherCore( int xOtherCoreID );
-#define portYIELD_CORE( x ) vPortYieldOtherCore( x )
+        void vPortYieldOtherCore( int xOtherCoreID );
+        #define portYIELD_CORE( x )    vPortYieldOtherCore( x )
 /*-----------------------------------------------------------*/
 
 /* Architecture specific optimisations. */
-#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
-#endif
+        #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+            #define configUSE_PORT_OPTIMISED_TASK_SELECTION    0
+        #endif
 
-#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+        #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
 
-    /* Store/clear the ready priorities in a bit map. */
-    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+/* Store/clear the ready priorities in a bit map. */
+            #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+            #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 
-    /*-----------------------------------------------------------*/
+/*-----------------------------------------------------------*/
 
-    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __builtin_clz( uxReadyPriorities ) )
+            #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ( uint32_t ) __builtin_clz( uxReadyPriorities ) )
 
-#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+        #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 /*-----------------------------------------------------------*/
 
 /* Critical section management. */
 
-#define portGET_INTERRUPT_STATE() rtos_interrupt_mask_get()
+        #define portGET_INTERRUPT_STATE()                 rtos_interrupt_mask_get()
 
 /*
  * This differs from the standard portDISABLE_INTERRUPTS()
  * in that it also returns what the interrupt state was
  * before it disabling interrupts.
  */
-#define portDISABLE_INTERRUPTS() rtos_interrupt_mask_all()
+        #define portDISABLE_INTERRUPTS()                  rtos_interrupt_mask_all()
 
-#define portENABLE_INTERRUPTS() rtos_interrupt_unmask_all()
+        #define portENABLE_INTERRUPTS()                   rtos_interrupt_unmask_all()
 
 /*
  * Port set interrupt mask and clear interrupt mask.
  */
-#define portSET_INTERRUPT_MASK()                rtos_interrupt_mask_all()
-#define portCLEAR_INTERRUPT_MASK( ulState )     rtos_interrupt_mask_set( ulState )
+        #define portSET_INTERRUPT_MASK()                  rtos_interrupt_mask_all()
+        #define portCLEAR_INTERRUPT_MASK( ulState )       rtos_interrupt_mask_set( ulState )
 
-#define portSET_INTERRUPT_MASK_FROM_ISR()       ( 0 )
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)    ( (void) x )
+        #define portSET_INTERRUPT_MASK_FROM_ISR()         ( 0 )
+        #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    ( ( void ) x )
 
 /*
  * Will enable interrupts if ulState is non-zero.
  */
-#define portRESTORE_INTERRUPTS(ulState) rtos_interrupt_mask_set(ulState)
+        #define portRESTORE_INTERRUPTS( ulState )         rtos_interrupt_mask_set( ulState )
 
 /*
  * Returns non-zero if currently running in an
  * ISR or otherwise in kernel mode.
  */
-#define portCHECK_IF_IN_ISR() rtos_isr_running()
+        #define portCHECK_IF_IN_ISR()                     rtos_isr_running()
 
-#define portASSERT_IF_IN_ISR() configASSERT( portCHECK_IF_IN_ISR() == 0 )
+        #define portASSERT_IF_IN_ISR()                    configASSERT( portCHECK_IF_IN_ISR() == 0 )
 
-#define portGET_ISR_LOCK()      rtos_lock_acquire(0)
-#define portRELEASE_ISR_LOCK()  rtos_lock_release(0)
-#define portGET_TASK_LOCK()     rtos_lock_acquire(1)
-#define portRELEASE_TASK_LOCK() rtos_lock_release(1)
+        #define portGET_ISR_LOCK()                        rtos_lock_acquire( 0 )
+        #define portRELEASE_ISR_LOCK()                    rtos_lock_release( 0 )
+        #define portGET_TASK_LOCK()                       rtos_lock_acquire( 1 )
+        #define portRELEASE_TASK_LOCK()                   rtos_lock_release( 1 )
 
-void vTaskEnterCritical(void);
-void vTaskExitCritical(void);
-#define portENTER_CRITICAL()                   vTaskEnterCritical()
-#define portEXIT_CRITICAL()                    vTaskExitCritical()
+        void vTaskEnterCritical( void );
+        void vTaskExitCritical( void );
+        #define portENTER_CRITICAL()    vTaskEnterCritical()
+        #define portEXIT_CRITICAL()     vTaskExitCritical()
 
-extern UBaseType_t vTaskEnterCriticalFromISR( void );
-extern void vTaskExitCriticalFromISR( UBaseType_t uxSavedInterruptStatus );
-#define portENTER_CRITICAL_FROM_ISR             vTaskEnterCriticalFromISR
-#define portEXIT_CRITICAL_FROM_ISR              vTaskExitCriticalFromISR
+        extern UBaseType_t vTaskEnterCriticalFromISR( void );
+        extern void vTaskExitCriticalFromISR( UBaseType_t uxSavedInterruptStatus );
+        #define portENTER_CRITICAL_FROM_ISR    vTaskEnterCriticalFromISR
+        #define portEXIT_CRITICAL_FROM_ISR     vTaskExitCriticalFromISR
 
 /*-----------------------------------------------------------*/
 
 /* Runtime stats support */
-#if ( configGENERATE_RUN_TIME_STATS == 1 )
-int xscope_gettime( void );
-#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() 	/* nothing needed here */
-#define portGET_RUN_TIME_COUNTER_VALUE()			xscope_gettime()
-#endif
+        #if ( configGENERATE_RUN_TIME_STATS == 1 )
+            int xscope_gettime( void );
+            #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS()    /* nothing needed here */
+            #define portGET_RUN_TIME_COUNTER_VALUE()            xscope_gettime()
+        #endif
 /*-----------------------------------------------------------*/
 
 /* Maps sprintf and snprintf to the lite version in lib_rtos_support */
-#if ( configUSE_DEBUG_SPRINTF == 1 )
-#define sprintf(...) rtos_sprintf(__VA_ARGS__)
-#define snprintf(...) rtos_snprintf(__VA_ARGS__)
-#endif
+        #if ( configUSE_DEBUG_SPRINTF == 1 )
+            #define sprintf( ... )     rtos_sprintf( __VA_ARGS__ )
+            #define snprintf( ... )    rtos_snprintf( __VA_ARGS__ )
+        #endif
 
 /* Attribute for the pxCallbackFunction member of the Timer_t struct.
-Required by xcc to calculate stack usage. */
-#define portTIMER_CALLBACK_ATTRIBUTE __attribute__((fptrgroup("timerCallbackGroup")))
+ * Required by xcc to calculate stack usage. */
+        #define portTIMER_CALLBACK_ATTRIBUTE    __attribute__( ( fptrgroup( "timerCallbackGroup" ) ) )
 
 /* Timer callback function macros. For xcc this ensures they get added to the timer callback
-group so that stack usage for certain functions in timers.c can be calculated. */
-#define portTIMER_CALLBACK_FUNCTION_PROTO( vFunction, xTimer ) void vFunction( TimerHandle_t xTimer )
-#define portTIMER_CALLBACK_FUNCTION( vFunction, xTimer ) portTIMER_CALLBACK_ATTRIBUTE void vFunction( TimerHandle_t xTimer )
+ * group so that stack usage for certain functions in timers.c can be calculated. */
+        #define portTIMER_CALLBACK_FUNCTION_PROTO( vFunction, xTimer )    void vFunction( TimerHandle_t xTimer )
+        #define portTIMER_CALLBACK_FUNCTION( vFunction, xTimer )          portTIMER_CALLBACK_ATTRIBUTE void vFunction( TimerHandle_t xTimer )
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site.  These are
-not necessary for to use this port.  They are defined so the common demo files
-(which build with all the ports) will build. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+ * not necessary for to use this port.  They are defined so the common demo files
+ * (which build with all the ports) will build. */
+        #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+        #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 /*-----------------------------------------------------------*/
 
 
-#ifdef __cplusplus
+        #ifdef __cplusplus
 }
-#endif
+        #endif
 
-#endif /* __ASSEMBLER__ */
+    #endif /* __ASSEMBLER__ */
 
 #endif /* PORTMACRO_H */
-
diff --git a/portable/ThirdParty/xClang/XCOREAI/rtos_support_rtos_config.h b/portable/ThirdParty/xClang/XCOREAI/rtos_support_rtos_config.h
index 8b8d1054d..3e4140903 100644
--- a/portable/ThirdParty/xClang/XCOREAI/rtos_support_rtos_config.h
+++ b/portable/ThirdParty/xClang/XCOREAI/rtos_support_rtos_config.h
@@ -1,4 +1,4 @@
-// Copyright (c) 2020, XMOS Ltd, All rights reserved
+/* Copyright (c) 2020, XMOS Ltd, All rights reserved */
 
 #ifndef RTOS_SUPPORT_RTOS_CONFIG_H_
 #define RTOS_SUPPORT_RTOS_CONFIG_H_
@@ -6,7 +6,7 @@
 /**
  * Lets the application know that the RTOS in use is FreeRTOS.
  */
-#define RTOS_FREERTOS 1
+#define RTOS_FREERTOS                              1
 
 /**
  * The number of words to extend the stack by when entering an ISR.
@@ -17,28 +17,29 @@
  * it is OK to store words at SP[0]. Therefore the ISR must leave SP[0] alone
  * even though it is normally not necessary to do so.
  */
-#define RTOS_SUPPORT_INTERRUPT_STACK_GROWTH ( 44 + 1 )
+#define RTOS_SUPPORT_INTERRUPT_STACK_GROWTH        ( 44 + 1 )
 
 /**
  * The word offset into the stack where R1 is to be stored after it
  * is extended when saving a thread's context.
  */
-#define RTOS_SUPPORT_INTERRUPT_R1_STACK_OFFSET 9
+#define RTOS_SUPPORT_INTERRUPT_R1_STACK_OFFSET     9
 
 /**
  * The word offset into the stack where R11 is to be stored after it
  * is extended when saving a thread's context.
  */
-#define RTOS_SUPPORT_INTERRUPT_R11_STACK_OFFSET 19
+#define RTOS_SUPPORT_INTERRUPT_R11_STACK_OFFSET    19
 
 /**
  * The RTOS provided handler that should run when a
  * core receives an intercore interrupt request.
  */
-#define RTOS_INTERCORE_INTERRUPT_ISR() do { \
-	void vIntercoreInterruptISR( void ); \
-	vIntercoreInterruptISR(); \
-} while ( 0 )
+#define RTOS_INTERCORE_INTERRUPT_ISR()       \
+    do {                                     \
+        void vIntercoreInterruptISR( void ); \
+        vIntercoreInterruptISR();            \
+    } while( 0 )
 
 /**
  * The number of hardware locks that the RTOS
@@ -48,48 +49,47 @@
  * Note that the IRQ routines require a lock and
  * will share the first one with the RTOS.
  */
-#define RTOS_LOCK_COUNT 2
+#define RTOS_LOCK_COUNT            2
 
 /**
  * Remaps all calls to debug_printf() to rtos_printf().
  * When this is on, files should not include both rtos_support.h
  * and debug_print.h.
  */
-#define RTOS_DEBUG_PRINTF_REMAP 1
+#define RTOS_DEBUG_PRINTF_REMAP    1
 
 
 #ifdef configENABLE_DEBUG_PRINTF
-	#if configENABLE_DEBUG_PRINTF
+    #if configENABLE_DEBUG_PRINTF
 
-		/* ensure that debug_printf is enabled */
-		#ifdef DEBUG_PRINT_ENABLE
-			#undef DEBUG_PRINT_ENABLE
-		#endif
-		#define DEBUG_PRINT_ENABLE 1
+/* ensure that debug_printf is enabled */
+        #ifdef DEBUG_PRINT_ENABLE
+            #undef DEBUG_PRINT_ENABLE
+        #endif
+        #define DEBUG_PRINT_ENABLE                        1
 
-		#ifndef configTASKS_DEBUG
-			#define configTASKS_DEBUG 0
-		#endif
-		#if configTASKS_DEBUG == 1
-			#define DEBUG_PRINT_ENABLE_FREERTOS_TASKS 1
-		#else
-			#define DEBUG_PRINT_DISABLE_FREERTOS_TASKS 1
-		#endif
+        #ifndef configTASKS_DEBUG
+            #define configTASKS_DEBUG                     0
+        #endif
+        #if configTASKS_DEBUG == 1
+            #define DEBUG_PRINT_ENABLE_FREERTOS_TASKS     1
+        #else
+            #define DEBUG_PRINT_DISABLE_FREERTOS_TASKS    1
+        #endif
 
-	#else /* configENABLE_DEBUG_PRINTF */
+    #else /* configENABLE_DEBUG_PRINTF */
 
-		/* ensure that debug_printf is disabled */
-		#ifdef DEBUG_UNIT
-			#undef DEBUG_UNIT
-		#endif
-		#ifdef DEBUG_PRINT_ENABLE
-			#undef DEBUG_PRINT_ENABLE
-		#endif
+/* ensure that debug_printf is disabled */
+        #ifdef DEBUG_UNIT
+            #undef DEBUG_UNIT
+        #endif
+        #ifdef DEBUG_PRINT_ENABLE
+            #undef DEBUG_PRINT_ENABLE
+        #endif
 
-		#define DEBUG_PRINT_ENABLE 0
+        #define DEBUG_PRINT_ENABLE    0
 
-	#endif /* configENABLE_DEBUG_PRINTF */
-#endif
+    #endif /* configENABLE_DEBUG_PRINTF */
+#endif /* ifdef configENABLE_DEBUG_PRINTF */
 
 #endif /* RTOS_SUPPORT_RTOS_CONFIG_H_ */
-
diff --git a/portable/WizC/PIC18/Drivers/Tick/Tick.c b/portable/WizC/PIC18/Drivers/Tick/Tick.c
index 5dfa080b6..16d7bc12a 100644
--- a/portable/WizC/PIC18/Drivers/Tick/Tick.c
+++ b/portable/WizC/PIC18/Drivers/Tick/Tick.c
@@ -27,22 +27,22 @@
  */
 
 /*
-Changes from V3.0.0
-    + ISRcode is pulled inline and portTICKisr() is therefore
-      deleted from this file.
-
-    + Prescaler logic for Timer1 added to allow for a wider
-      range of TickRates.
-
-Changes from V3.0.1
-*/
+ * Changes from V3.0.0
+ + ISRcode is pulled inline and portTICKisr() is therefore
+ +    deleted from this file.
+ +
+ + Prescaler logic for Timer1 added to allow for a wider
+ +    range of TickRates.
+ +
+ + Changes from V3.0.1
+ */
 
 #include <FreeRTOS.h>
 #include <task.h>
 
 /* IO port constants. */
-#define portBIT_SET     (1)
-#define portBIT_CLEAR   (0)
+#define portBIT_SET                    ( 1 )
+#define portBIT_CLEAR                  ( 0 )
 
 /*
  * Hardware setup for the tick.
@@ -50,27 +50,27 @@ Changes from V3.0.1
  * and requested tickrate, a prescaled value with a matching
  * prescaler are determined.
  */
-#define portTIMER_COMPARE_BASE          ((APROCFREQ/4)/configTICK_RATE_HZ)
+#define portTIMER_COMPARE_BASE         ( ( APROCFREQ / 4 ) / configTICK_RATE_HZ )
 
-#if portTIMER_COMPARE_BASE   < 0x10000
-    #define portTIMER_COMPARE_VALUE     (portTIMER_COMPARE_BASE)
-    #define portTIMER_COMPARE_PS1       (portBIT_CLEAR)
-    #define portTIMER_COMPARE_PS0       (portBIT_CLEAR)
+#if portTIMER_COMPARE_BASE < 0x10000
+    #define portTIMER_COMPARE_VALUE    ( portTIMER_COMPARE_BASE )
+    #define portTIMER_COMPARE_PS1      ( portBIT_CLEAR )
+    #define portTIMER_COMPARE_PS0      ( portBIT_CLEAR )
 #elif portTIMER_COMPARE_BASE < 0x20000
-    #define portTIMER_COMPARE_VALUE     (portTIMER_COMPARE_BASE / 2)
-    #define portTIMER_COMPARE_PS1       (portBIT_CLEAR)
-    #define portTIMER_COMPARE_PS0       (portBIT_SET)
+    #define portTIMER_COMPARE_VALUE    ( portTIMER_COMPARE_BASE / 2 )
+    #define portTIMER_COMPARE_PS1      ( portBIT_CLEAR )
+    #define portTIMER_COMPARE_PS0      ( portBIT_SET )
 #elif portTIMER_COMPARE_BASE < 0x40000
-    #define portTIMER_COMPARE_VALUE     (portTIMER_COMPARE_BASE / 4)
-    #define portTIMER_COMPARE_PS1       (portBIT_SET)
-    #define portTIMER_COMPARE_PS0       (portBIT_CLEAR)
+    #define portTIMER_COMPARE_VALUE    ( portTIMER_COMPARE_BASE / 4 )
+    #define portTIMER_COMPARE_PS1      ( portBIT_SET )
+    #define portTIMER_COMPARE_PS0      ( portBIT_CLEAR )
 #elif portTIMER_COMPARE_BASE < 0x80000
-    #define portTIMER_COMPARE_VALUE     (portTIMER_COMPARE_BASE / 8)
-    #define portTIMER_COMPARE_PS1       (portBIT_SET)
-    #define portTIMER_COMPARE_PS0       (portBIT_SET)
-#else
+    #define portTIMER_COMPARE_VALUE    ( portTIMER_COMPARE_BASE / 8 )
+    #define portTIMER_COMPARE_PS1      ( portBIT_SET )
+    #define portTIMER_COMPARE_PS0      ( portBIT_SET )
+#else /* if portTIMER_COMPARE_BASE < 0x10000 */
     #error "TickRate out of range"
-#endif
+#endif /* if portTIMER_COMPARE_BASE < 0x10000 */
 
 /*-----------------------------------------------------------*/
 
@@ -92,27 +92,27 @@ void portSetupTick( void )
      * Set the compare match value.
      */
     CCPR1H = ( uint8_t ) ( ( portTIMER_COMPARE_VALUE >> 8 ) & 0xff );
-    CCPR1L = ( uint8_t )   ( portTIMER_COMPARE_VALUE & 0xff );
+    CCPR1L = ( uint8_t ) ( portTIMER_COMPARE_VALUE & 0xff );
 
     /*
      * Set Compare Special Event Trigger Mode
      */
-    bCCP1M3     = portBIT_SET;
-    bCCP1M2     = portBIT_CLEAR;
-    bCCP1M1     = portBIT_SET;
-    bCCP1M0     = portBIT_SET;
+    bCCP1M3 = portBIT_SET;
+    bCCP1M2 = portBIT_CLEAR;
+    bCCP1M1 = portBIT_SET;
+    bCCP1M0 = portBIT_SET;
 
     /*
      * Enable CCP1 interrupt
      */
-    bCCP1IE     = portBIT_SET;
+    bCCP1IE = portBIT_SET;
 
     /*
      * We are only going to use the global interrupt bit, so disable
      * interruptpriorities and enable peripheral interrupts.
      */
-    bIPEN       = portBIT_CLEAR;
-    bPEIE       = portBIT_SET;
+    bIPEN = portBIT_CLEAR;
+    bPEIE = portBIT_SET;
 
     /*
      * Set up timer1
@@ -128,12 +128,12 @@ void portSetupTick( void )
     /*
      * Setup the timer
      */
-    bRD16       = portBIT_SET;              // 16-bit
-    bT1CKPS1    = portTIMER_COMPARE_PS1;    // prescaler
-    bT1CKPS0    = portTIMER_COMPARE_PS0;    // prescaler
-    bT1OSCEN    = portBIT_SET;              // Oscillator enable
-    bT1SYNC     = portBIT_SET;              // No external clock sync
-    bTMR1CS     = portBIT_CLEAR;            // Internal clock
+    bRD16 = portBIT_SET;              /* 16-bit */
+    bT1CKPS1 = portTIMER_COMPARE_PS1; /* prescaler */
+    bT1CKPS0 = portTIMER_COMPARE_PS0; /* prescaler */
+    bT1OSCEN = portBIT_SET;           /* Oscillator enable */
+    bT1SYNC = portBIT_SET;            /* No external clock sync */
+    bTMR1CS = portBIT_CLEAR;          /* Internal clock */
 
-    bTMR1ON     = portBIT_SET;              // Start timer1
+    bTMR1ON = portBIT_SET;            /* Start timer1 */
 }
diff --git a/portable/WizC/PIC18/Drivers/Tick/isrTick.c b/portable/WizC/PIC18/Drivers/Tick/isrTick.c
index f61047dc1..b4d1338b2 100644
--- a/portable/WizC/PIC18/Drivers/Tick/isrTick.c
+++ b/portable/WizC/PIC18/Drivers/Tick/isrTick.c
@@ -27,17 +27,17 @@
  */
 
 /*
-Changes from V3.0.0
-    + ISRcode pulled inline to reduce stack-usage.
-
-    + Added functionality to only call vTaskSwitchContext() once
-      when handling multiple interruptsources in a single interruptcall.
-
-    + Filename changed to a .c extension to allow stepping through code
-      using F7.
-
-Changes from V3.0.1
-*/
+ * Changes from V3.0.0
+ + ISRcode pulled inline to reduce stack-usage.
+ +
+ + Added functionality to only call vTaskSwitchContext() once
+ +    when handling multiple interruptsources in a single interruptcall.
+ +
+ + Filename changed to a .c extension to allow stepping through code
+ +    using F7.
+ +
+ + Changes from V3.0.1
+ */
 
 /*
  * ISR for the tick.
@@ -76,4 +76,4 @@ Changes from V3.0.1
 
 #pragma wizcpp uselib     "$__PATHNAME__/Tick.c"
 
-#endif  /* _FREERTOS_DRIVERS_TICK_ISRTICK_C */
+#endif /* _FREERTOS_DRIVERS_TICK_ISRTICK_C */
diff --git a/portable/WizC/PIC18/addFreeRTOS.h b/portable/WizC/PIC18/addFreeRTOS.h
index 178ca1089..28ea79c02 100644
--- a/portable/WizC/PIC18/addFreeRTOS.h
+++ b/portable/WizC/PIC18/addFreeRTOS.h
@@ -27,13 +27,13 @@
  */
 
 /*
-Changes from V3.0.0
-
-Changes from V3.0.1
-
-Changes from V4.0.1
-    Uselib pragma added for Croutine.c
-*/
+ * Changes from V3.0.0
+ *
+ * Changes from V3.0.1
+ *
+ * Changes from V4.0.1
+ *  Uselib pragma added for Croutine.c
+ */
 
 /*
  * The installation script will automatically prepend this file to the default FreeRTOS.h.
@@ -51,4 +51,4 @@ Changes from V4.0.1
 #pragma wizcpp uselib     "$__PATHNAME__/libFreeRTOS/Modules/List.c"
 #pragma wizcpp uselib     "$__PATHNAME__/libFreeRTOS/Modules/Port.c"
 
-#endif  /* WIZC_FREERTOS_H */
+#endif /* WIZC_FREERTOS_H */
diff --git a/portable/WizC/PIC18/port.c b/portable/WizC/PIC18/port.c
index e3cf9999a..13f8d4a1b 100644
--- a/portable/WizC/PIC18/port.c
+++ b/portable/WizC/PIC18/port.c
@@ -27,19 +27,19 @@
  */
 
 /*
-Changes from V3.2.1
-    + CallReturn Depth increased from 8 to 10 levels to accomodate wizC/fedC V12.
-
-Changes from V3.2.0
-    + TBLPTRU is now initialised to zero during the initial stack creation of a new task. This solves
-    an error on devices with more than 64kB ROM.
-
-Changes from V3.0.0
-    + ucCriticalNesting is now initialised to 0x7F to prevent interrupts from being
-          handled before the scheduler is started.
-
-Changes from V3.0.1
-*/
+ * Changes from V3.2.1
+ + CallReturn Depth increased from 8 to 10 levels to accommodate wizC/fedC V12.
+ +
+ + Changes from V3.2.0
+ + TBLPTRU is now initialised to zero during the initial stack creation of a new task. This solves
+ +  an error on devices with more than 64kB ROM.
+ +
+ + Changes from V3.0.0
+ + ucCriticalNesting is now initialised to 0x7F to prevent interrupts from being
+ +        handled before the scheduler is started.
+ +
+ + Changes from V3.0.1
+ */
 
 /* Scheduler include files. */
 #include <FreeRTOS.h>
@@ -78,17 +78,17 @@ extern volatile TCB_t * volatile pxCurrentTCB;
  *      16 bytes: Free space on stack
  */
 #if _ROMSIZE > 0x8000
-    #define portSTACK_FSR_BYTES             ( 15 )
-    #define portSTACK_CALLRETURN_ENTRY_SIZE (  3 )
+    #define portSTACK_FSR_BYTES                ( 15 )
+    #define portSTACK_CALLRETURN_ENTRY_SIZE    ( 3 )
 #else
-    #define portSTACK_FSR_BYTES             ( 13 )
-    #define portSTACK_CALLRETURN_ENTRY_SIZE (  2 )
+    #define portSTACK_FSR_BYTES                ( 13 )
+    #define portSTACK_CALLRETURN_ENTRY_SIZE    ( 2 )
 #endif
 
-#define portSTACK_MINIMAL_CALLRETURN_DEPTH  ( 10 )
-#define portSTACK_OTHER_BYTES               ( 20 )
+#define portSTACK_MINIMAL_CALLRETURN_DEPTH     ( 10 )
+#define portSTACK_OTHER_BYTES                  ( 20 )
 
-uint16_t usCalcMinStackSize     = 0;
+uint16_t usCalcMinStackSize = 0;
 
 /*-----------------------------------------------------------*/
 
@@ -106,16 +106,20 @@ register uint8_t ucCriticalNesting = 0x7F;
  * Initialise the stack of a new task.
  * See portSAVE_CONTEXT macro for description.
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
-uint8_t ucScratch;
+    uint8_t ucScratch;
+
     /*
      * Get the size of the RAMarea in page 0 used by the compiler
      * We do this here already to avoid W-register conflicts.
      */
     _Pragma("asm")
-        movlw   OVERHEADPAGE0-LOCOPTSIZE+MAXLOCOPTSIZE
-        movwf   PRODL,ACCESS        ; PRODL is used as temp register
+    movlw OVERHEADPAGE0 - LOCOPTSIZE + MAXLOCOPTSIZE
+    movwf PRODL, ACCESS;
+    PRODL is used as temp register
     _Pragma("asmend")
     ucScratch = PRODL;
 
@@ -123,9 +127,9 @@ uint8_t ucScratch;
      * Place a few bytes of known values on the bottom of the stack.
      * This is just useful for debugging.
      */
-//  *pxTopOfStack-- = 0x11;
-//  *pxTopOfStack-- = 0x22;
-//  *pxTopOfStack-- = 0x33;
+/*  *pxTopOfStack-- = 0x11; */
+/*  *pxTopOfStack-- = 0x22; */
+/*  *pxTopOfStack-- = 0x33; */
 
     /*
      * Simulate how the stack would look after a call to vPortYield()
@@ -136,36 +140,36 @@ uint8_t ucScratch;
      * First store the function parameters.  This is where the task expects
      * to find them when it starts running.
      */
-    *pxTopOfStack-- = ( StackType_t ) ( (( uint16_t ) pvParameters >> 8) & 0x00ff );
-    *pxTopOfStack-- = ( StackType_t ) (  ( uint16_t ) pvParameters       & 0x00ff );
+    *pxTopOfStack-- = ( StackType_t ) ( ( ( uint16_t ) pvParameters >> 8 ) & 0x00ff );
+    *pxTopOfStack-- = ( StackType_t ) ( ( uint16_t ) pvParameters & 0x00ff );
 
     /*
      * Next are all the registers that form part of the task context.
      */
-    *pxTopOfStack-- = ( StackType_t ) 0x11; /* STATUS. */
-    *pxTopOfStack-- = ( StackType_t ) 0x22; /* WREG. */
-    *pxTopOfStack-- = ( StackType_t ) 0x33; /* BSR. */
-    *pxTopOfStack-- = ( StackType_t ) 0x44; /* PRODH. */
-    *pxTopOfStack-- = ( StackType_t ) 0x55; /* PRODL. */
-    *pxTopOfStack-- = ( StackType_t ) 0x66; /* FSR0H. */
-    *pxTopOfStack-- = ( StackType_t ) 0x77; /* FSR0L. */
-    *pxTopOfStack-- = ( StackType_t ) 0x88; /* FSR1H. */
-    *pxTopOfStack-- = ( StackType_t ) 0x99; /* FSR1L. */
-    *pxTopOfStack-- = ( StackType_t ) 0xAA; /* TABLAT. */
-#if _ROMSIZE > 0x8000
-    *pxTopOfStack-- = ( StackType_t ) 0x00; /* TBLPTRU. */
-#endif
-    *pxTopOfStack-- = ( StackType_t ) 0xCC; /* TBLPTRH. */
-    *pxTopOfStack-- = ( StackType_t ) 0xDD; /* TBLPTRL. */
-#if _ROMSIZE > 0x8000
-    *pxTopOfStack-- = ( StackType_t ) 0xEE; /* PCLATU. */
-#endif
-    *pxTopOfStack-- = ( StackType_t ) 0xFF; /* PCLATH. */
+    *pxTopOfStack-- = ( StackType_t ) 0x11;     /* STATUS. */
+    *pxTopOfStack-- = ( StackType_t ) 0x22;     /* WREG. */
+    *pxTopOfStack-- = ( StackType_t ) 0x33;     /* BSR. */
+    *pxTopOfStack-- = ( StackType_t ) 0x44;     /* PRODH. */
+    *pxTopOfStack-- = ( StackType_t ) 0x55;     /* PRODL. */
+    *pxTopOfStack-- = ( StackType_t ) 0x66;     /* FSR0H. */
+    *pxTopOfStack-- = ( StackType_t ) 0x77;     /* FSR0L. */
+    *pxTopOfStack-- = ( StackType_t ) 0x88;     /* FSR1H. */
+    *pxTopOfStack-- = ( StackType_t ) 0x99;     /* FSR1L. */
+    *pxTopOfStack-- = ( StackType_t ) 0xAA;     /* TABLAT. */
+    #if _ROMSIZE > 0x8000
+        *pxTopOfStack-- = ( StackType_t ) 0x00; /* TBLPTRU. */
+    #endif
+    *pxTopOfStack-- = ( StackType_t ) 0xCC;     /* TBLPTRH. */
+    *pxTopOfStack-- = ( StackType_t ) 0xDD;     /* TBLPTRL. */
+    #if _ROMSIZE > 0x8000
+        *pxTopOfStack-- = ( StackType_t ) 0xEE; /* PCLATU. */
+    #endif
+    *pxTopOfStack-- = ( StackType_t ) 0xFF;     /* PCLATH. */
 
     /*
      * Next the compiler's scratchspace.
      */
-    while(ucScratch-- > 0)
+    while( ucScratch-- > 0 )
     {
         *pxTopOfStack-- = ( StackType_t ) 0;
     }
@@ -176,11 +180,11 @@ uint8_t ucScratch;
      * stack, too. TOSU is always written as zero here because wizC does not allow
      * functionpointers to point above 64kB in ROM.
      */
-#if _ROMSIZE > 0x8000
-    *pxTopOfStack-- = ( StackType_t ) 0;
-#endif
+    #if _ROMSIZE > 0x8000
+        *pxTopOfStack-- = ( StackType_t ) 0;
+    #endif
     *pxTopOfStack-- = ( StackType_t ) ( ( ( uint16_t ) pxCode >> 8 ) & 0x00ff );
-    *pxTopOfStack-- = ( StackType_t ) ( (   uint16_t ) pxCode        & 0x00ff );
+    *pxTopOfStack-- = ( StackType_t ) ( ( uint16_t ) pxCode & 0x00ff );
 
     /*
      * Store the number of return addresses on the hardware stack.
@@ -207,19 +211,19 @@ uint16_t usPortCALCULATE_MINIMAL_STACK_SIZE( void )
      * Fetch the size of compiler's scratchspace.
      */
     _Pragma("asm")
-        movlw   OVERHEADPAGE0-LOCOPTSIZE+MAXLOCOPTSIZE
-        movlb   usCalcMinStackSize>>8
-        movwf   usCalcMinStackSize,BANKED
+    movlw OVERHEADPAGE0 - LOCOPTSIZE + MAXLOCOPTSIZE
+    movlb usCalcMinStackSize >> 8
+    movwf usCalcMinStackSize, BANKED
     _Pragma("asmend")
 
     /*
      * Add minimum needed stackspace
      */
-    usCalcMinStackSize  +=  ( portSTACK_FSR_BYTES )
-        +   ( portSTACK_MINIMAL_CALLRETURN_DEPTH * portSTACK_CALLRETURN_ENTRY_SIZE )
-        +   ( portSTACK_OTHER_BYTES );
+    usCalcMinStackSize += ( portSTACK_FSR_BYTES )
+                          + ( portSTACK_MINIMAL_CALLRETURN_DEPTH * portSTACK_CALLRETURN_ENTRY_SIZE )
+                          + ( portSTACK_OTHER_BYTES );
 
-    return(usCalcMinStackSize);
+    return( usCalcMinStackSize );
 }
 
 /*-----------------------------------------------------------*/
@@ -282,11 +286,11 @@ void vPortYield( void )
 }
 /*-----------------------------------------------------------*/
 
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
 
-    void *pvPortMalloc( uint16_t usWantedSize )
+    void * pvPortMalloc( uint16_t usWantedSize )
     {
-    void *pvReturn;
+        void * pvReturn;
 
         vTaskSuspendAll();
         {
@@ -301,9 +305,9 @@ void vPortYield( void )
 
 /*-----------------------------------------------------------*/
 
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
 
-    void vPortFree( void *pv )
+    void vPortFree( void * pv )
     {
         if( pv )
         {
diff --git a/portable/WizC/PIC18/portmacro.h b/portable/WizC/PIC18/portmacro.h
index 0fdba688e..e272084b3 100644
--- a/portable/WizC/PIC18/portmacro.h
+++ b/portable/WizC/PIC18/portmacro.h
@@ -27,48 +27,48 @@
  */
 
 /*
-Changes from V3.0.0
-
-Changes from V3.0.1
-*/
+ * Changes from V3.0.0
+ *
+ * Changes from V3.0.1
+ */
 #ifndef PORTMACRO_H
 #define PORTMACRO_H
 
-#if !defined(_SERIES) || _SERIES != 18
+#if !defined( _SERIES ) || _SERIES != 18
     #error "WizC supports FreeRTOS on the Microchip PIC18-series only"
 #endif
 
-#if !defined(QUICKCALL) || QUICKCALL != 1
+#if !defined( QUICKCALL ) || QUICKCALL != 1
     #error "QuickCall must be enabled (see ProjectOptions/Optimisations)"
 #endif
 
 #include <stddef.h>
 #include <pic.h>
 
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      portFLOAT
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint8_t
-#define portBASE_TYPE   char
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        portFLOAT
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint8_t
+#define portBASE_TYPE     char
 
-typedef portSTACK_TYPE StackType_t;
-typedef signed char BaseType_t;
-typedef unsigned char UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef signed char      BaseType_t;
+typedef unsigned char    UBaseType_t;
 
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t )    ( 0xFFFF )
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) ( 0xFFFF )
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY ( TickType_t )    ( 0xFFFFFFFFUL )
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) ( 0xFFFFFFFFUL )
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
 
-#define portBYTE_ALIGNMENT          1
+#define portBYTE_ALIGNMENT    1
 
 /*-----------------------------------------------------------*/
 
@@ -76,33 +76,33 @@ typedef unsigned char UBaseType_t;
  * Constant used for context switch macro when we require the interrupt
  * enable state to be forced when the interrupted task is switched back in.
  */
-#define portINTERRUPTS_FORCED               (0x01)
+#define portINTERRUPTS_FORCED           ( 0x01 )
 
 /*
  * Constant used for context switch macro when we require the interrupt
  * enable state to be unchanged when the interrupted task is switched back in.
  */
-#define portINTERRUPTS_UNCHANGED            (0x00)
+#define portINTERRUPTS_UNCHANGED        ( 0x00 )
 
 /* Initial interrupt enable state for newly created tasks.  This value is
  * used when a task switches in for the first time.
  */
-#define portINTERRUPTS_INITIAL_STATE        (portINTERRUPTS_FORCED)
+#define portINTERRUPTS_INITIAL_STATE    ( portINTERRUPTS_FORCED )
 
 /*
  * Macros to modify the global interrupt enable bit in INTCON.
  */
-#define portDISABLE_INTERRUPTS()    \
-    do                              \
-    {                               \
-        bGIE=0;                     \
-    } while(bGIE)   // MicroChip recommends this check!
+#define portDISABLE_INTERRUPTS() \
+    do                           \
+    {                            \
+        bGIE = 0;                \
+    } while( bGIE ) /* MicroChip recommends this check! */
 
-#define portENABLE_INTERRUPTS()     \
-    do                              \
-    {                               \
-        bGIE=1;                     \
-    } while(0)
+#define portENABLE_INTERRUPTS() \
+    do                          \
+    {                           \
+        bGIE = 1;               \
+    } while( 0 )
 
 /*-----------------------------------------------------------*/
 
@@ -111,43 +111,43 @@ typedef unsigned char UBaseType_t;
  */
 extern uint8_t ucCriticalNesting;
 
-#define portNO_CRITICAL_SECTION_NESTING     ( ( uint8_t ) 0 )
+#define portNO_CRITICAL_SECTION_NESTING    ( ( uint8_t ) 0 )
 
-#define portENTER_CRITICAL()                                        \
-    do                                                              \
-    {                                                               \
-        portDISABLE_INTERRUPTS();                                   \
-                                                                    \
-        /*                                                          \
-         * Now interrupts are disabled ucCriticalNesting            \
-         * can be accessed directly. Increment                      \
-         * ucCriticalNesting to keep a count of how                 \
-         * many times portENTER_CRITICAL() has been called.         \
-         */                                                         \
-        ucCriticalNesting++;                                        \
-    } while(0)
+#define portENTER_CRITICAL()      \
+    do                            \
+    {                             \
+        portDISABLE_INTERRUPTS(); \
+                                  \
+        /* \
+         * Now interrupts are disabled ucCriticalNesting \
+         * can be accessed directly. Increment \
+         * ucCriticalNesting to keep a count of how \
+         * many times portENTER_CRITICAL() has been called. \
+         */                  \
+        ucCriticalNesting++; \
+    } while( 0 )
 
-#define portEXIT_CRITICAL()                                         \
-    do                                                              \
-    {                                                               \
-        if(ucCriticalNesting > portNO_CRITICAL_SECTION_NESTING)     \
-        {                                                           \
-            /*                                                      \
-             * Decrement the nesting count as we are leaving a      \
-             * critical section.                                    \
-             */                                                     \
-            ucCriticalNesting--;                                    \
-        }                                                           \
-                                                                    \
-        /*                                                          \
-         * If the nesting level has reached zero then               \
-         * interrupts should be re-enabled.                         \
-         */                                                         \
-        if( ucCriticalNesting == portNO_CRITICAL_SECTION_NESTING )  \
-        {                                                           \
-            portENABLE_INTERRUPTS();                                \
-        }                                                           \
-    } while(0)
+#define portEXIT_CRITICAL()                                       \
+    do                                                            \
+    {                                                             \
+        if( ucCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \
+        {                                                         \
+            /* \
+             * Decrement the nesting count as we are leaving a \
+             * critical section. \
+             */                  \
+            ucCriticalNesting--; \
+        }                        \
+                                 \
+        /* \
+         * If the nesting level has reached zero then \
+         * interrupts should be re-enabled. \
+         */                                                        \
+        if( ucCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \
+        {                                                          \
+            portENABLE_INTERRUPTS();                               \
+        }                                                          \
+    } while( 0 )
 
 /*-----------------------------------------------------------*/
 
@@ -159,15 +159,15 @@ extern uint8_t ucCriticalNesting;
 extern uint16_t usPortCALCULATE_MINIMAL_STACK_SIZE( void );
 extern uint16_t usCalcMinStackSize;
 
-#define portMINIMAL_STACK_SIZE                  \
-    ((usCalcMinStackSize == 0)                  \
-        ? usPortCALCULATE_MINIMAL_STACK_SIZE()  \
-        : usCalcMinStackSize )
+#define portMINIMAL_STACK_SIZE               \
+    ( ( usCalcMinStackSize == 0 )            \
+      ? usPortCALCULATE_MINIMAL_STACK_SIZE() \
+      : usCalcMinStackSize )
 
 /*
  * WizC uses a downgrowing stack
  */
-#define portSTACK_GROWTH            ( -1 )
+#define portSTACK_GROWTH    ( -1 )
 
 /*-----------------------------------------------------------*/
 
@@ -176,7 +176,7 @@ extern uint16_t usCalcMinStackSize;
  * the stack, then saves the new top of stack into the TCB. TOSU and TBLPTRU
  * are only saved/restored on devices with more than 64kB (32k Words) ROM.
  *
- * The stackpointer is helt by WizC in FSR2 and points to the first free byte.
+ * The stackpointer is held by WizC in FSR2 and points to the first free byte.
  * WizC uses a "downgrowing" stack. There is no framepointer.
  *
  * We keep track of the interruptstatus using ucCriticalNesting. When this
@@ -189,7 +189,7 @@ extern uint16_t usCalcMinStackSize;
  * re-enabled when the interrupted task is switched back in.
  *
  * If this is called from a manual context switch (i.e. from a call to yield),
- * then we want to keep the current value of ucCritialNesting so it is restored
+ * then we want to keep the current value of ucCriticalNesting so it is restored
  * with its current value. This allows a yield from within a critical section.
  *
  * The compiler uses some locations at the bottom of RAM for temporary
@@ -203,219 +203,220 @@ extern uint16_t usCalcMinStackSize;
  * assembler definitions.
  */
 
-#define portSAVE_CONTEXT( ucInterruptForced )                       \
-    do                                                              \
-    {                                                               \
-        portDISABLE_INTERRUPTS();                                   \
-                                                                    \
-        _Pragma("asm")                                              \
-            ;                                                       \
-            ; Push the relevant SFR's onto the task's stack         \
-            ;                                                       \
-            movff   STATUS,POSTDEC2                                 \
-            movff   WREG,POSTDEC2                                   \
-            movff   BSR,POSTDEC2                                    \
-            movff   PRODH,POSTDEC2                                  \
-            movff   PRODL,POSTDEC2                                  \
-            movff   FSR0H,POSTDEC2                                  \
-            movff   FSR0L,POSTDEC2                                  \
-            movff   FSR1H,POSTDEC2                                  \
-            movff   FSR1L,POSTDEC2                                  \
-            movff   TABLAT,POSTDEC2                                 \
-            if __ROMSIZE > 0x8000                                   \
-                movff   TBLPTRU,POSTDEC2                            \
-            endif                                                   \
-            movff   TBLPTRH,POSTDEC2                                \
-            movff   TBLPTRL,POSTDEC2                                \
-            if __ROMSIZE > 0x8000                                   \
-                movff   PCLATU,POSTDEC2                             \
-            endif                                                   \
-            movff   PCLATH,POSTDEC2                                 \
-            ;                                                       \
-            ; Store the compiler-scratch-area as described above.   \
-            ;                                                       \
-            movlw   OVERHEADPAGE0-LOCOPTSIZE+MAXLOCOPTSIZE          \
-            clrf    FSR0L,ACCESS                                    \
-            clrf    FSR0H,ACCESS                                    \
-        _rtos_S1:                                                   \
-            movff   POSTINC0,POSTDEC2                               \
-            decfsz  WREG,W,ACCESS                                   \
-            SMARTJUMP _rtos_S1                                      \
-            ;                                                       \
-            ; Save the pic call/return-stack belonging to the       \
-            ; current task by copying it to the task's software-    \
-            ; stack. We save the hardware stack pointer (which      \
-            ; is the number of addresses on the stack) in the       \
-            ; W-register first because we need it later and it      \
-            ; is modified in the save-loop by executing pop's.      \
-            ; After the loop the W-register is stored on the        \
-            ; stack, too.                                           \
-            ;                                                       \
-            movf    STKPTR,W,ACCESS                                 \
-            bz      _rtos_s3                                        \
-        _rtos_S2:                                                   \
-            if __ROMSIZE > 0x8000                                   \
-                movff   TOSU,POSTDEC2                               \
-            endif                                                   \
-            movff   TOSH,POSTDEC2                                   \
-            movff   TOSL,POSTDEC2                                   \
-            pop                                                     \
-            tstfsz  STKPTR,ACCESS                                   \
-            SMARTJUMP _rtos_S2                                      \
-        _rtos_s3:                                                   \
-            movwf   POSTDEC2,ACCESS                                 \
-            ;                                                       \
-            ; Next the value for ucCriticalNesting used by the      \
-            ; task is stored on the stack. When                     \
-            ; (ucInterruptForced == portINTERRUPTS_FORCED), we save \
-            ; it as 0 (portNO_CRITICAL_SECTION_NESTING).            \
-            ;                                                       \
-            if ucInterruptForced == portINTERRUPTS_FORCED           \
-                clrf POSTDEC2,ACCESS                                \
-            else                                                    \
-                movff   ucCriticalNesting,POSTDEC2                  \
-            endif                                                   \
-            ;                                                       \
-            ; Save the new top of the software stack in the TCB.    \
-            ;                                                       \
-            movff   pxCurrentTCB,FSR0L                              \
-            movff   pxCurrentTCB+1,FSR0H                            \
-            movff   FSR2L,POSTINC0                                  \
-            movff   FSR2H,POSTINC0                                  \
-        _Pragma("asmend")                                           \
-    } while(0)
+#define portSAVE_CONTEXT( ucInterruptForced )                   \
+    do                                                          \
+    {                                                           \
+        portDISABLE_INTERRUPTS();                               \
+                                                                \
+        _Pragma("asm")                                          \
+        ;                                                       \
+        ; Push the relevant SFR's onto the task's stack         \
+        ;                                                       \
+        movff   STATUS,POSTDEC2                                 \
+        movff   WREG,POSTDEC2                                   \
+        movff   BSR,POSTDEC2                                    \
+        movff   PRODH,POSTDEC2                                  \
+        movff   PRODL,POSTDEC2                                  \
+        movff   FSR0H,POSTDEC2                                  \
+        movff   FSR0L,POSTDEC2                                  \
+        movff   FSR1H,POSTDEC2                                  \
+        movff   FSR1L,POSTDEC2                                  \
+        movff   TABLAT,POSTDEC2                                 \
+        if __ROMSIZE > 0x8000                                   \
+        movff   TBLPTRU,POSTDEC2                                \
+        endif                                                   \
+        movff   TBLPTRH,POSTDEC2                                \
+        movff   TBLPTRL,POSTDEC2                                \
+        if __ROMSIZE > 0x8000                                   \
+        movff   PCLATU,POSTDEC2                                 \
+        endif                                                   \
+        movff   PCLATH,POSTDEC2                                 \
+        ;                                                       \
+        ; Store the compiler-scratch-area as described above.   \
+        ;                                                       \
+        movlw   OVERHEADPAGE0-LOCOPTSIZE+MAXLOCOPTSIZE          \
+        clrf    FSR0L,ACCESS                                    \
+        clrf    FSR0H,ACCESS                                    \
+        _rtos_S1:                                               \
+        movff   POSTINC0,POSTDEC2                               \
+        decfsz  WREG,W,ACCESS                                   \
+        SMARTJUMP _rtos_S1                                      \
+        ;                                                       \
+        ; Save the pic call/return-stack belonging to the       \
+        ; current task by copying it to the task's software-    \
+        ; stack. We save the hardware stack pointer (which      \
+        ; is the number of addresses on the stack) in the       \
+        ; W-register first because we need it later and it      \
+        ; is modified in the save-loop by executing pop's.      \
+        ; After the loop the W-register is stored on the        \
+        ; stack, too.                                           \
+        ;                                                       \
+        movf    STKPTR,W,ACCESS                                 \
+        bz      _rtos_s3                                        \
+        _rtos_S2:                                               \
+        if __ROMSIZE > 0x8000                                   \
+        movff   TOSU,POSTDEC2                                   \
+        endif                                                   \
+        movff   TOSH,POSTDEC2                                   \
+        movff   TOSL,POSTDEC2                                   \
+        pop                                                     \
+        tstfsz  STKPTR,ACCESS                                   \
+        SMARTJUMP _rtos_S2                                      \
+        _rtos_s3:                                               \
+        movwf   POSTDEC2,ACCESS                                 \
+        ;                                                       \
+        ; Next the value for ucCriticalNesting used by the      \
+        ; task is stored on the stack. When                     \
+        ; (ucInterruptForced == portINTERRUPTS_FORCED), we save \
+        ; it as 0 (portNO_CRITICAL_SECTION_NESTING).            \
+        ;                                                       \
+        if ucInterruptForced == portINTERRUPTS_FORCED           \
+        clrf POSTDEC2,ACCESS                                    \
+        else                                                    \
+        movff   ucCriticalNesting,POSTDEC2                      \
+        endif                                                   \
+        ;                                                       \
+        ; Save the new top of the software stack in the TCB.    \
+        ;                                                       \
+        movff   pxCurrentTCB,FSR0L                              \
+        movff   pxCurrentTCB+1,FSR0H                            \
+        movff   FSR2L,POSTINC0                                  \
+        movff   FSR2H,POSTINC0                                  \
+        _Pragma("asmend")                                       \
+        } while(0)
 
 /************************************************************/
 
 /*
  * This is the reverse of portSAVE_CONTEXT.
  */
-#define portRESTORE_CONTEXT()                                       \
-    do                                                              \
-    {                                                               \
-        _Pragma("asm")                                              \
-            ;                                                       \
-            ; Set FSR0 to point to pxCurrentTCB->pxTopOfStack.      \
-            ;                                                       \
-            movff   pxCurrentTCB,FSR0L                              \
-            movff   pxCurrentTCB+1,FSR0H                            \
-            ;                                                       \
-            ; De-reference FSR0 to set the address it holds into    \
-            ; FSR2 (i.e. *( pxCurrentTCB->pxTopOfStack ) ). FSR2    \
-            ; is used by wizC as stackpointer.                      \
-            ;                                                       \
-            movff   POSTINC0,FSR2L                                  \
-            movff   POSTINC0,FSR2H                                  \
-            ;                                                       \
-            ; Next, the value for ucCriticalNesting used by the     \
-            ; task is retrieved from the stack.                     \
-            ;                                                       \
-            movff   PREINC2,ucCriticalNesting                       \
-            ;                                                       \
-            ; Rebuild the pic call/return-stack. The number of      \
-            ; return addresses is the next item on the task stack.  \
-            ; Save this number in PRODL. Then fetch the addresses   \
-            ; and store them on the hardwarestack.                  \
-            ; The datasheets say we can't use movff here...         \
-            ;                                                       \
-            movff   PREINC2,PRODL   // Use PRODL as tempregister    \
-            clrf    STKPTR,ACCESS                                   \
-        _rtos_R1:                                                   \
-            push                                                    \
-            movf    PREINC2,W,ACCESS                                \
-            movwf   TOSL,ACCESS                                     \
-            movf    PREINC2,W,ACCESS                                \
-            movwf   TOSH,ACCESS                                     \
-            if __ROMSIZE > 0x8000                                   \
-                movf    PREINC2,W,ACCESS                            \
-                movwf   TOSU,ACCESS                                 \
-            else                                                    \
-                clrf    TOSU,ACCESS                                 \
-            endif                                                   \
-            decfsz  PRODL,F,ACCESS                                  \
-            SMARTJUMP _rtos_R1                                      \
-            ;                                                       \
-            ; Restore the compiler's working storage area to page 0 \
-            ;                                                       \
-            movlw   OVERHEADPAGE0-LOCOPTSIZE+MAXLOCOPTSIZE          \
-            movwf   FSR0L,ACCESS                                    \
-            clrf    FSR0H,ACCESS                                    \
-        _rtos_R2:                                                   \
-            decf    FSR0L,F,ACCESS                                  \
-            movff   PREINC2,INDF0                                   \
-            tstfsz  FSR0L,ACCESS                                    \
-            SMARTJUMP _rtos_R2                                      \
-            ;                                                       \
-            ; Restore the sfr's forming the tasks context.          \
-            ; We cannot yet restore bsr, w and status because       \
-            ; we need these registers for a final test.             \
-            ;                                                       \
-            movff   PREINC2,PCLATH                                  \
-            if __ROMSIZE > 0x8000                                   \
-                movff   PREINC2,PCLATU                              \
-            else                                                    \
-                clrf    PCLATU,ACCESS                               \
-            endif                                                   \
-            movff   PREINC2,TBLPTRL                                 \
-            movff   PREINC2,TBLPTRH                                 \
-            if __ROMSIZE > 0x8000                                   \
-                movff   PREINC2,TBLPTRU                             \
-            else                                                    \
-                clrf    TBLPTRU,ACCESS                              \
-            endif                                                   \
-            movff   PREINC2,TABLAT                                  \
-            movff   PREINC2,FSR1L                                   \
-            movff   PREINC2,FSR1H                                   \
-            movff   PREINC2,FSR0L                                   \
-            movff   PREINC2,FSR0H                                   \
-            movff   PREINC2,PRODL                                   \
-            movff   PREINC2,PRODH                                   \
-            ;                                                       \
-            ; The return from portRESTORE_CONTEXT() depends on      \
-            ; the value of ucCriticalNesting. When it is zero,      \
-            ; interrupts need to be enabled. This is done via a     \
-            ; retfie instruction because we need the                \
-            ; interrupt-enabling and the return to the restored     \
-            ; task to be uninterruptable.                           \
-            ; Because bsr, status and W are affected by the test    \
-            ; they are restored after the test.                     \
-            ;                                                       \
-            movlb   ucCriticalNesting>>8                            \
-            tstfsz  ucCriticalNesting,BANKED                        \
-            SMARTJUMP _rtos_R4                                      \
-        _rtos_R3:                                                   \
-            movff   PREINC2,BSR                                     \
-            movff   PREINC2,WREG                                    \
-            movff   PREINC2,STATUS                                  \
-            retfie  0       ; Return enabling interrupts            \
-        _rtos_R4:                                                   \
-            movff   PREINC2,BSR                                     \
-            movff   PREINC2,WREG                                    \
-            movff   PREINC2,STATUS                                  \
-            return  0       ; Return without affecting interrupts   \
-        _Pragma("asmend")                                           \
-    } while(0)
+#define portRESTORE_CONTEXT()                                   \
+    do                                                          \
+    {                                                           \
+        _Pragma("asm")                                          \
+        ;                                                       \
+        ; Set FSR0 to point to pxCurrentTCB->pxTopOfStack.      \
+        ;                                                       \
+        movff   pxCurrentTCB,FSR0L                              \
+        movff   pxCurrentTCB+1,FSR0H                            \
+        ;                                                       \
+        ; De-reference FSR0 to set the address it holds into    \
+        ; FSR2 (i.e. *( pxCurrentTCB->pxTopOfStack ) ). FSR2    \
+        ; is used by wizC as stackpointer.                      \
+        ;                                                       \
+        movff   POSTINC0,FSR2L                                  \
+        movff   POSTINC0,FSR2H                                  \
+        ;                                                       \
+        ; Next, the value for ucCriticalNesting used by the     \
+        ; task is retrieved from the stack.                     \
+        ;                                                       \
+        movff   PREINC2,ucCriticalNesting                       \
+        ;                                                       \
+        ; Rebuild the pic call/return-stack. The number of      \
+        ; return addresses is the next item on the task stack.  \
+        ; Save this number in PRODL. Then fetch the addresses   \
+        ; and store them on the hardwarestack.                  \
+        ; The datasheets say we can't use movff here...         \
+        ;                                                       \
+        movff   PREINC2,PRODL /* Use PRODL as tempregister */   \
+        clrf    STKPTR,ACCESS                                   \
+        _rtos_R1:                                               \
+        push                                                    \
+        movf    PREINC2,W,ACCESS                                \
+        movwf   TOSL,ACCESS                                     \
+        movf    PREINC2,W,ACCESS                                \
+        movwf   TOSH,ACCESS                                     \
+        if __ROMSIZE > 0x8000                                   \
+        movf    PREINC2,W,ACCESS                                \
+        movwf   TOSU,ACCESS                                     \
+        else                                                    \
+        clrf    TOSU,ACCESS                                     \
+        endif                                                   \
+        decfsz  PRODL,F,ACCESS                                  \
+        SMARTJUMP _rtos_R1                                      \
+        ;                                                       \
+        ; Restore the compiler's working storage area to page 0 \
+        ;                                                       \
+        movlw   OVERHEADPAGE0-LOCOPTSIZE+MAXLOCOPTSIZE          \
+        movwf   FSR0L,ACCESS                                    \
+        clrf    FSR0H,ACCESS                                    \
+        _rtos_R2:                                               \
+        decf    FSR0L,F,ACCESS                                  \
+        movff   PREINC2,INDF0                                   \
+        tstfsz  FSR0L,ACCESS                                    \
+        SMARTJUMP _rtos_R2                                      \
+        ;                                                       \
+        ; Restore the sfr's forming the tasks context.          \
+        ; We cannot yet restore bsr, w and status because       \
+        ; we need these registers for a final test.             \
+        ;                                                       \
+        movff   PREINC2,PCLATH                                  \
+        if __ROMSIZE > 0x8000                                   \
+        movff   PREINC2,PCLATU                                  \
+        else                                                    \
+        clrf    PCLATU,ACCESS                                   \
+        endif                                                   \
+        movff   PREINC2,TBLPTRL                                 \
+        movff   PREINC2,TBLPTRH                                 \
+        if __ROMSIZE > 0x8000                                   \
+        movff   PREINC2,TBLPTRU                                 \
+        else                                                    \
+        clrf    TBLPTRU,ACCESS                                  \
+        endif                                                   \
+        movff   PREINC2,TABLAT                                  \
+        movff   PREINC2,FSR1L                                   \
+        movff   PREINC2,FSR1H                                   \
+        movff   PREINC2,FSR0L                                   \
+        movff   PREINC2,FSR0H                                   \
+        movff   PREINC2,PRODL                                   \
+        movff   PREINC2,PRODH                                   \
+        ;                                                       \
+        ; The return from portRESTORE_CONTEXT() depends on      \
+        ; the value of ucCriticalNesting. When it is zero,      \
+        ; interrupts need to be enabled. This is done via a     \
+        ; retfie instruction because we need the                \
+        ; interrupt-enabling and the return to the restored     \
+        ; task to be uninterruptible.                           \
+        ; Because bsr, status and W are affected by the test    \
+        ; they are restored after the test.                     \
+        ;                                                       \
+        movlb   ucCriticalNesting>>8                            \
+        tstfsz  ucCriticalNesting,BANKED                        \
+        SMARTJUMP _rtos_R4                                      \
+        _rtos_R3:                                               \
+        movff   PREINC2,BSR                                     \
+        movff   PREINC2,WREG                                    \
+        movff   PREINC2,STATUS                                  \
+        retfie  0       ; Return enabling interrupts            \
+        _rtos_R4:                                               \
+        movff   PREINC2,BSR                                     \
+        movff   PREINC2,WREG                                    \
+        movff   PREINC2,STATUS                                  \
+        return  0       ; Return without affecting interrupts   \
+        _Pragma("asmend")                                       \
+        } while(0)
 
 /*-----------------------------------------------------------*/
 
-#define portTICK_PERIOD_MS  ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
 
 /*-----------------------------------------------------------*/
 
 extern void vPortYield( void );
-#define portYIELD()             vPortYield()
+#define portYIELD()    vPortYield()
 
-#define portNOP()   _Pragma("asm")                                  \
-                        nop                                         \
-                    _Pragma("asmend")
+#define portNOP()  \
+    _Pragma("asm") \
+    nop            \
+    _Pragma("asmend")
 
 /*-----------------------------------------------------------*/
 
-#define portTASK_FUNCTION( xFunction, pvParameters )        \
-    void pointed xFunction( void *pvParameters )        \
+#define portTASK_FUNCTION( xFunction, pvParameters ) \
+    void pointed xFunction( void * pvParameters )    \
     _Pragma(asmfunc xFunction)
 
-#define portTASK_FUNCTION_PROTO     portTASK_FUNCTION
+#define portTASK_FUNCTION_PROTO    portTASK_FUNCTION
 /*-----------------------------------------------------------*/
 
 
diff --git a/portable/oWatcom/16BitDOS/Flsh186/port.c b/portable/oWatcom/16BitDOS/Flsh186/port.c
index cc8863d1d..03feb21e6 100644
--- a/portable/oWatcom/16BitDOS/Flsh186/port.c
+++ b/portable/oWatcom/16BitDOS/Flsh186/port.c
@@ -27,27 +27,27 @@
  */
 
 /*
-Changes from V1.00:
-
-    + Call to taskYIELD() from within tick ISR has been replaced by the more
-      efficient portSWITCH_CONTEXT().
-    + ISR function definitions renamed to include the prv prefix.
-
-Changes from V1.2.0:
-
-    + portRESET_PIC() is now called last thing before the end of the preemptive
-      tick routine.
-
-Changes from V2.6.1
-
-    + Replaced the sUsingPreemption variable with the configUSE_PREEMPTION
-      macro to be consistent with the later ports.
-*/
+ * Changes from V1.00:
+ *
+ + Call to taskYIELD() from within tick ISR has been replaced by the more
+ +    efficient portSWITCH_CONTEXT().
+ + ISR function definitions renamed to include the prv prefix.
+ +
+ + Changes from V1.2.0:
+ +
+ + portRESET_PIC() is now called last thing before the end of the preemptive
+ +    tick routine.
+ +
+ + Changes from V2.6.1
+ +
+ + Replaced the sUsingPreemption variable with the configUSE_PREEMPTION
+ +    macro to be consistent with the later ports.
+ */
 
 /*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the Flashlite 186
- * port.
- *----------------------------------------------------------*/
+* Implementation of functions defined in portable.h for the Flashlite 186
+* port.
+*----------------------------------------------------------*/
 
 #include <stdlib.h>
 #include <i86.h>
@@ -60,9 +60,9 @@ Changes from V2.6.1
 
 /*lint -e950 Non ANSI reserved words okay in this file only. */
 
-#define portTIMER_EOI_TYPE      ( 8 )
-#define portRESET_PIC()         portOUTPUT_WORD( ( uint16_t ) 0xff22, portTIMER_EOI_TYPE )
-#define portTIMER_INT_NUMBER    0x12
+#define portTIMER_EOI_TYPE              ( 8 )
+#define portRESET_PIC()    portOUTPUT_WORD( ( uint16_t ) 0xff22, portTIMER_EOI_TYPE )
+#define portTIMER_INT_NUMBER            0x12
 
 #define portTIMER_1_CONTROL_REGISTER    ( ( uint16_t ) 0xff5e )
 #define portTIMER_0_CONTROL_REGISTER    ( ( uint16_t ) 0xff56 )
@@ -75,12 +75,14 @@ static void prvSetTickFrequency( uint32_t ulTickRateHz );
 static void prvExitFunction( void );
 
 #if configUSE_PREEMPTION == 1
-    /* Tick service routine used by the scheduler when preemptive scheduling is
-    being used. */
+
+/* Tick service routine used by the scheduler when preemptive scheduling is
+ * being used. */
     static void __interrupt __far prvPreemptiveTick( void );
 #else
-    /* Tick service routine used by the scheduler when cooperative scheduling is
-    being used. */
+
+/* Tick service routine used by the scheduler when cooperative scheduling is
+ * being used. */
     static void __interrupt __far prvNonPreemptiveTick( void );
 #endif
 
@@ -93,7 +95,7 @@ static void __interrupt __far prvYieldProcessor( void );
 static int16_t sSchedulerRunning = pdFALSE;
 
 /* Points to the original routine installed on the vector we use for manual context switches.  This is then used to restore the original routine during prvExitFunction(). */
-static void ( __interrupt __far *pxOldSwitchISR )();
+static void( __interrupt __far * pxOldSwitchISR )();
 
 /* Used to restore the original DOS context when the scheduler is ended. */
 static jmp_buf xJumpBuf;
@@ -106,11 +108,11 @@ BaseType_t xPortStartScheduler( void )
     /* This is called with interrupts already disabled. */
 
     /* Remember what was on the interrupts we are going to use
-    so we can put them back later if required. */
+     * so we can put them back later if required. */
     pxOldSwitchISR = _dos_getvect( portSWITCH_INT_NUMBER );
 
     /* Put our manual switch (yield) function on a known
-    vector. */
+     * vector. */
     _dos_setvect( portSWITCH_INT_NUMBER, prvYieldProcessor );
 
     #if configUSE_PREEMPTION == 1
@@ -146,7 +148,7 @@ BaseType_t xPortStartScheduler( void )
 /*-----------------------------------------------------------*/
 
 /* The tick ISR used depend on whether or not the preemptive or cooperative
-kernel is being used. */
+ * kernel is being used. */
 #if configUSE_PREEMPTION == 1
     static void __interrupt __far prvPreemptiveTick( void )
     {
@@ -160,15 +162,15 @@ kernel is being used. */
         /* Reset the PIC ready for the next time. */
         portRESET_PIC();
     }
-#else
+#else /* if configUSE_PREEMPTION == 1 */
     static void __interrupt __far prvNonPreemptiveTick( void )
     {
         /* Same as preemptive tick, but the cooperative scheduler is being used
-        so we don't have to switch in the context of the next task. */
+         * so we don't have to switch in the context of the next task. */
         xTaskIncrementTick();
         portRESET_PIC();
     }
-#endif
+#endif /* if configUSE_PREEMPTION == 1 */
 /*-----------------------------------------------------------*/
 
 static void __interrupt __far prvYieldProcessor( void )
@@ -181,30 +183,31 @@ static void __interrupt __far prvYieldProcessor( void )
 void vPortEndScheduler( void )
 {
     /* Jump back to the processor state prior to starting the
-    scheduler.  This means we are not going to be using a
-    task stack frame so the task can be deleted. */
+     * scheduler.  This means we are not going to be using a
+     * task stack frame so the task can be deleted. */
     longjmp( xJumpBuf, 1 );
 }
 /*-----------------------------------------------------------*/
 
 static void prvExitFunction( void )
 {
-const uint16_t usTimerDisable = 0x0000;
-uint16_t usTimer0Control;
+    const uint16_t usTimerDisable = 0x0000;
+    uint16_t usTimer0Control;
 
     /* Interrupts should be disabled here anyway - but no
-    harm in making sure. */
+     * harm in making sure. */
     portDISABLE_INTERRUPTS();
+
     if( sSchedulerRunning == pdTRUE )
     {
         /* Put back the switch interrupt routines that was in place
-        before the scheduler started. */
+         * before the scheduler started. */
         _dos_setvect( portSWITCH_INT_NUMBER, pxOldSwitchISR );
     }
 
     /* Disable the timer used for the tick to ensure the scheduler is
-    not called before restoring interrupts.  There was previously nothing
-    on this timer so there is no old ISR to restore. */
+     * not called before restoring interrupts.  There was previously nothing
+     * on this timer so there is no old ISR to restore. */
     portOUTPUT_WORD( portTIMER_1_CONTROL_REGISTER, usTimerDisable );
 
     /* Restart the DOS tick. */
@@ -219,18 +222,18 @@ uint16_t usTimer0Control;
 
 static void prvSetTickFrequency( uint32_t ulTickRateHz )
 {
-const uint16_t usMaxCountRegister = 0xff5a;
-const uint16_t usTimerPriorityRegister = 0xff32;
-const uint16_t usTimerEnable = 0xC000;
-const uint16_t usRetrigger = 0x0001;
-const uint16_t usTimerHighPriority = 0x0000;
-uint16_t usTimer0Control;
+    const uint16_t usMaxCountRegister = 0xff5a;
+    const uint16_t usTimerPriorityRegister = 0xff32;
+    const uint16_t usTimerEnable = 0xC000;
+    const uint16_t usRetrigger = 0x0001;
+    const uint16_t usTimerHighPriority = 0x0000;
+    uint16_t usTimer0Control;
 
 /* ( CPU frequency / 4 ) / clock 2 max count [inpw( 0xff62 ) = 7] */
 
-const uint32_t ulClockFrequency = 0x7f31a0;
+    const uint32_t ulClockFrequency = 0x7f31a0;
 
-uint32_t ulTimerCount = ulClockFrequency / ulTickRateHz;
+    uint32_t ulTimerCount = ulClockFrequency / ulTickRateHz;
 
     portOUTPUT_WORD( portTIMER_1_CONTROL_REGISTER, usTimerEnable | portTIMER_INTERRUPT_ENABLE | usRetrigger );
     portOUTPUT_WORD( usMaxCountRegister, ( uint16_t ) ulTimerCount );
diff --git a/portable/oWatcom/16BitDOS/Flsh186/portmacro.h b/portable/oWatcom/16BitDOS/Flsh186/portmacro.h
index 952e3f680..0488fd8b7 100644
--- a/portable/oWatcom/16BitDOS/Flsh186/portmacro.h
+++ b/portable/oWatcom/16BitDOS/Flsh186/portmacro.h
@@ -47,24 +47,24 @@
 
 
 /* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      long
-#define portLONG        long
-#define portSHORT       int
-#define portSTACK_TYPE  uint16_t
-#define portBASE_TYPE   short
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        long
+#define portLONG          long
+#define portSHORT         int
+#define portSTACK_TYPE    uint16_t
+#define portBASE_TYPE     short
 
-typedef portSTACK_TYPE StackType_t;
-typedef short BaseType_t;
-typedef unsigned short UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef short            BaseType_t;
+typedef unsigned short   UBaseType_t;
 
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-        typedef uint16_t TickType_t;
-        #define portMAX_DELAY ( TickType_t ) 0xffff
-#elif ( configTICK_TYPE_WIDTH_IN_BITS  == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t             TickType_t;
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+    typedef uint32_t     TickType_t;
     #define portMAX_DELAY    ( TickType_t ) 0xffffffffUL
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -74,7 +74,7 @@ typedef unsigned short UBaseType_t;
 /* Critical section management. */
 void portENTER_CRITICAL( void );
 #pragma aux portENTER_CRITICAL = "pushf" \
-                                 "cli";
+    "cli";
 
 void portEXIT_CRITICAL( void );
 #pragma aux portEXIT_CRITICAL   = "popf";
@@ -87,25 +87,25 @@ void portENABLE_INTERRUPTS( void );
 /*-----------------------------------------------------------*/
 
 /* Architecture specifics. */
-#define portSTACK_GROWTH        ( -1 )
-#define portSWITCH_INT_NUMBER   0x80
-#define portYIELD()             __asm{ int portSWITCH_INT_NUMBER }
-#define portTICK_PERIOD_MS        ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT      2
-#define portINITIAL_SW          ( ( portSTACK_TYPE ) 0x0202 )   /* Start the tasks with interrupts enabled. */
-#define portNOP()               __asm{ nop }
+#define portSTACK_GROWTH         ( -1 )
+#define portSWITCH_INT_NUMBER    0x80
+#define portYIELD()    __asm { int portSWITCH_INT_NUMBER }
+#define portTICK_PERIOD_MS       ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT       2
+#define portINITIAL_SW           ( ( portSTACK_TYPE ) 0x0202 )  /* Start the tasks with interrupts enabled. */
+#define portNOP()    __asm { nop }
 /*-----------------------------------------------------------*/
 
 /* Compiler specifics. */
-#define portINPUT_BYTE( xAddr )                 inp( xAddr )
-#define portOUTPUT_BYTE( xAddr, ucValue )       outp( xAddr, ucValue )
-#define portINPUT_WORD( xAddr )                 inpw( xAddr )
-#define portOUTPUT_WORD( xAddr, usValue )       outpw( xAddr, usValue )
+#define portINPUT_BYTE( xAddr )              inp( xAddr )
+#define portOUTPUT_BYTE( xAddr, ucValue )    outp( xAddr, ucValue )
+#define portINPUT_WORD( xAddr )              inpw( xAddr )
+#define portOUTPUT_WORD( xAddr, usValue )    outpw( xAddr, usValue )
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/oWatcom/16BitDOS/PC/port.c b/portable/oWatcom/16BitDOS/PC/port.c
index 6cb2de9e8..4c4011aa9 100644
--- a/portable/oWatcom/16BitDOS/PC/port.c
+++ b/portable/oWatcom/16BitDOS/PC/port.c
@@ -27,27 +27,27 @@
  */
 
 /*
-Changes from V1.00:
-
-    + Call to taskYIELD() from within tick ISR has been replaced by the more
-      efficient portSWITCH_CONTEXT().
-    + ISR function definitions renamed to include the prv prefix.
-
-Changes from V1.2.0:
-
-    + prvPortResetPIC() is now called last thing before the end of the
-      preemptive tick routine.
-
-Changes from V2.6.1
-
-    + Replaced the sUsingPreemption variable with the configUSE_PREEMPTION
-      macro to be consistent with the later ports.
-
-Changes from V4.0.1
-
-    + Add function prvSetTickFrequencyDefault() to set the DOS tick back to
-      its proper value when the scheduler exits.
-*/
+ * Changes from V1.00:
+ *
+ + Call to taskYIELD() from within tick ISR has been replaced by the more
+ +    efficient portSWITCH_CONTEXT().
+ + ISR function definitions renamed to include the prv prefix.
+ +
+ + Changes from V1.2.0:
+ +
+ + prvPortResetPIC() is now called last thing before the end of the
+ +    preemptive tick routine.
+ +
+ + Changes from V2.6.1
+ +
+ + Replaced the sUsingPreemption variable with the configUSE_PREEMPTION
+ +    macro to be consistent with the later ports.
+ +
+ + Changes from V4.0.1
+ +
+ + Add function prvSetTickFrequencyDefault() to set the DOS tick back to
+ +    its proper value when the scheduler exits.
+ */
 
 #include <stdlib.h>
 #include <stdio.h>
@@ -60,9 +60,9 @@ Changes from V4.0.1
 #include "portasm.h"
 
 /*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the industrial
- * PC port.
- *----------------------------------------------------------*/
+* Implementation of functions defined in portable.h for the industrial
+* PC port.
+*----------------------------------------------------------*/
 
 /*lint -e950 Non ANSI reserved words okay in this file only. */
 
@@ -75,26 +75,28 @@ static void prvSetTickFrequency( uint32_t ulTickRateHz );
 static void prvExitFunction( void );
 
 /* Either chain to the DOS tick (which itself clears the PIC) or clear the PIC
-directly.  We chain to the DOS tick as close as possible to the standard DOS
-tick rate. */
+ * directly.  We chain to the DOS tick as close as possible to the standard DOS
+ * tick rate. */
 static void prvPortResetPIC( void );
 
 /* The tick ISR used depends on whether the preemptive or cooperative scheduler
-is being used. */
+ * is being used. */
 #if configUSE_PREEMPTION == 1
-    /* Tick service routine used by the scheduler when preemptive scheduling is
-    being used. */
+
+/* Tick service routine used by the scheduler when preemptive scheduling is
+ * being used. */
     static void __interrupt __far prvPreemptiveTick( void );
 #else
-    /* Tick service routine used by the scheduler when cooperative scheduling is
-    being used. */
+
+/* Tick service routine used by the scheduler when cooperative scheduling is
+ * being used. */
     static void __interrupt __far prvNonPreemptiveTick( void );
 #endif
 /* Trap routine used by taskYIELD() to manually cause a context switch. */
 static void __interrupt __far prvYieldProcessor( void );
 
 /* Set the tick frequency back so the floppy drive works correctly when the
-scheduler exits. */
+ * scheduler exits. */
 static void prvSetTickFrequencyDefault( void );
 
 /*lint -e956 File scopes necessary here. */
@@ -106,10 +108,10 @@ static int16_t sDOSTickCounter;
 static int16_t sSchedulerRunning = pdFALSE;
 
 /* Points to the original routine installed on the vector we use for manual context switches.  This is then used to restore the original routine during prvExitFunction(). */
-static void ( __interrupt __far *pxOldSwitchISR )();
+static void( __interrupt __far * pxOldSwitchISR )();
 
 /* Points to the original routine installed on the vector we use to chain to the DOS tick.  This is then used to restore the original routine during prvExitFunction(). */
-static void ( __interrupt __far *pxOldSwitchISRPlus1 )();
+static void( __interrupt __far * pxOldSwitchISRPlus1 )();
 
 /* Used to restore the original DOS context when the scheduler is ended. */
 static jmp_buf xJumpBuf;
@@ -119,12 +121,12 @@ static jmp_buf xJumpBuf;
 /*-----------------------------------------------------------*/
 BaseType_t xPortStartScheduler( void )
 {
-pxISR pxOriginalTickISR;
+    pxISR pxOriginalTickISR;
 
     /* This is called with interrupts already disabled. */
 
     /* Remember what was on the interrupts we are going to use
-    so we can put them back later if required. */
+     * so we can put them back later if required. */
     pxOldSwitchISR = _dos_getvect( portSWITCH_INT_NUMBER );
     pxOriginalTickISR = _dos_getvect( portTIMER_INT_NUMBER );
     pxOldSwitchISRPlus1 = _dos_getvect( portSWITCH_INT_NUMBER + 1 );
@@ -132,11 +134,11 @@ pxISR pxOriginalTickISR;
     prvSetTickFrequency( configTICK_RATE_HZ );
 
     /* Put our manual switch (yield) function on a known
-    vector. */
+     * vector. */
     _dos_setvect( portSWITCH_INT_NUMBER, prvYieldProcessor );
 
     /* Put the old tick on a different interrupt number so we can
-    call it when we want. */
+     * call it when we want. */
     _dos_setvect( portSWITCH_INT_NUMBER + 1, pxOriginalTickISR );
 
     #if configUSE_PREEMPTION == 1
@@ -152,8 +154,8 @@ pxISR pxOriginalTickISR;
     #endif
 
     /* Setup a counter that is used to call the DOS interrupt as close
-    to it's original frequency as can be achieved given our chosen tick
-    frequency. */
+     * to it's original frequency as can be achieved given our chosen tick
+     * frequency. */
     sDOSTickCounter = portTICKS_PER_DOS_TICK;
 
     /* Clean up function if we want to return to DOS. */
@@ -175,10 +177,11 @@ pxISR pxOriginalTickISR;
 /*-----------------------------------------------------------*/
 
 /* The tick ISR used depends on whether the preemptive or cooperative scheduler
-is being used. */
+ * is being used. */
 #if configUSE_PREEMPTION == 1
-    /* Tick service routine used by the scheduler when preemptive scheduling is
-    being used. */
+
+/* Tick service routine used by the scheduler when preemptive scheduling is
+ * being used. */
     static void __interrupt __far prvPreemptiveTick( void )
     {
         /* Get the scheduler to update the task states following the tick. */
@@ -191,15 +194,15 @@ is being used. */
         /* Reset the PIC ready for the next time. */
         prvPortResetPIC();
     }
-#else
+#else /* if configUSE_PREEMPTION == 1 */
     static void __interrupt __far prvNonPreemptiveTick( void )
     {
         /* Same as preemptive tick, but the cooperative scheduler is being used
-        so we don't have to switch in the context of the next task. */
+         * so we don't have to switch in the context of the next task. */
         xTaskIncrementTick();
         prvPortResetPIC();
     }
-#endif
+#endif /* if configUSE_PREEMPTION == 1 */
 /*-----------------------------------------------------------*/
 
 
@@ -213,19 +216,22 @@ static void __interrupt __far prvYieldProcessor( void )
 static void prvPortResetPIC( void )
 {
     /* We are going to call the DOS tick interrupt at as close a
-    frequency to the normal DOS tick as possible. */
+     * frequency to the normal DOS tick as possible. */
 
     /* WE SHOULD NOT DO THIS IF YIELD WAS CALLED. */
     --sDOSTickCounter;
+
     if( sDOSTickCounter <= 0 )
     {
         sDOSTickCounter = ( int16_t ) portTICKS_PER_DOS_TICK;
-        __asm{ int  portSWITCH_INT_NUMBER + 1 };
+        __asm {
+            int portSWITCH_INT_NUMBER + 1
+        };
     }
     else
     {
         /* Reset the PIC as the DOS tick is not being called to
-        do it. */
+         * do it. */
         __asm
         {
             mov al, 20H
@@ -238,19 +244,20 @@ static void prvPortResetPIC( void )
 void vPortEndScheduler( void )
 {
     /* Jump back to the processor state prior to starting the
-    scheduler.  This means we are not going to be using a
-    task stack frame so the task can be deleted. */
+     * scheduler.  This means we are not going to be using a
+     * task stack frame so the task can be deleted. */
     longjmp( xJumpBuf, 1 );
 }
 /*-----------------------------------------------------------*/
 
 static void prvExitFunction( void )
 {
-void ( __interrupt __far *pxOriginalTickISR )();
+    void( __interrupt __far * pxOriginalTickISR )();
 
     /* Interrupts should be disabled here anyway - but no
-    harm in making sure. */
+     * harm in making sure. */
     portDISABLE_INTERRUPTS();
+
     if( sSchedulerRunning == pdTRUE )
     {
         /* Set the DOS tick back onto the timer ticker. */
@@ -259,29 +266,30 @@ void ( __interrupt __far *pxOriginalTickISR )();
         prvSetTickFrequencyDefault();
 
         /* Put back the switch interrupt routines that was in place
-        before the scheduler started. */
+         * before the scheduler started. */
         _dos_setvect( portSWITCH_INT_NUMBER, pxOldSwitchISR );
         _dos_setvect( portSWITCH_INT_NUMBER + 1, pxOldSwitchISRPlus1 );
     }
+
     /* The tick timer is back how DOS wants it.  We can re-enable
-    interrupts without the scheduler being called. */
+     * interrupts without the scheduler being called. */
     portENABLE_INTERRUPTS();
 }
 /*-----------------------------------------------------------*/
 
 static void prvSetTickFrequency( uint32_t ulTickRateHz )
 {
-const uint16_t usPIT_MODE = ( uint16_t ) 0x43;
-const uint16_t usPIT0 = ( uint16_t ) 0x40;
-const uint32_t ulPIT_CONST = ( uint32_t ) 1193180;
-const uint16_t us8254_CTR0_MODE3 = ( uint16_t ) 0x36;
-uint32_t ulOutput;
+    const uint16_t usPIT_MODE = ( uint16_t ) 0x43;
+    const uint16_t usPIT0 = ( uint16_t ) 0x40;
+    const uint32_t ulPIT_CONST = ( uint32_t ) 1193180;
+    const uint16_t us8254_CTR0_MODE3 = ( uint16_t ) 0x36;
+    uint32_t ulOutput;
 
     /* Setup the 8245 to tick at the wanted frequency. */
     portOUTPUT_BYTE( usPIT_MODE, us8254_CTR0_MODE3 );
     ulOutput = ulPIT_CONST / ulTickRateHz;
 
-    portOUTPUT_BYTE( usPIT0, ( uint16_t )( ulOutput & ( uint32_t ) 0xff ) );
+    portOUTPUT_BYTE( usPIT0, ( uint16_t ) ( ulOutput & ( uint32_t ) 0xff ) );
     ulOutput >>= 8;
     portOUTPUT_BYTE( usPIT0, ( uint16_t ) ( ulOutput & ( uint32_t ) 0xff ) );
 }
@@ -289,13 +297,13 @@ uint32_t ulOutput;
 
 static void prvSetTickFrequencyDefault( void )
 {
-const uint16_t usPIT_MODE = ( uint16_t ) 0x43;
-const uint16_t usPIT0 = ( uint16_t ) 0x40;
-const uint16_t us8254_CTR0_MODE3 = ( uint16_t ) 0x36;
+    const uint16_t usPIT_MODE = ( uint16_t ) 0x43;
+    const uint16_t usPIT0 = ( uint16_t ) 0x40;
+    const uint16_t us8254_CTR0_MODE3 = ( uint16_t ) 0x36;
 
     portOUTPUT_BYTE( usPIT_MODE, us8254_CTR0_MODE3 );
-    portOUTPUT_BYTE( usPIT0,0 );
-    portOUTPUT_BYTE( usPIT0,0 );
+    portOUTPUT_BYTE( usPIT0, 0 );
+    portOUTPUT_BYTE( usPIT0, 0 );
 }
 
 
diff --git a/portable/oWatcom/16BitDOS/PC/portmacro.h b/portable/oWatcom/16BitDOS/PC/portmacro.h
index 2fb753411..f2c585a14 100644
--- a/portable/oWatcom/16BitDOS/PC/portmacro.h
+++ b/portable/oWatcom/16BitDOS/PC/portmacro.h
@@ -46,24 +46,24 @@
  */
 
 /* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       int
-#define portSTACK_TYPE  uint16_t
-#define portBASE_TYPE   short
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         int
+#define portSTACK_TYPE    uint16_t
+#define portBASE_TYPE     short
 
-typedef portSTACK_TYPE StackType_t;
-typedef short BaseType_t;
-typedef unsigned short UBaseType_t;
+typedef portSTACK_TYPE   StackType_t;
+typedef short            BaseType_t;
+typedef unsigned short   UBaseType_t;
 
 
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
-#elif ( configTICK_TYPE_WIDTH_IN_BITS  == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t             TickType_t;
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+    typedef uint32_t     TickType_t;
     #define portMAX_DELAY    ( TickType_t ) 0xffffffffUL
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -71,11 +71,11 @@ typedef unsigned short UBaseType_t;
 /*-----------------------------------------------------------*/
 
 /* Critical section definitions.  portENTER_CRITICAL() must be defined as a
-macro for portable.h to work properly. */
+ * macro for portable.h to work properly. */
 void portLOCAL_ENTER_CRITICAL( void );
 #pragma aux portLOCAL_ENTER_CRITICAL =  "pushf" \
-                                        "cli";
-#define portENTER_CRITICAL() portLOCAL_ENTER_CRITICAL()
+    "cli";
+#define portENTER_CRITICAL()    portLOCAL_ENTER_CRITICAL()
 
 void portEXIT_CRITICAL( void );
 #pragma aux portEXIT_CRITICAL   =       "popf";
@@ -88,25 +88,25 @@ void portENABLE_INTERRUPTS( void );
 /*-----------------------------------------------------------*/
 
 /* Architecture specifics. */
-#define portSTACK_GROWTH        ( -1 )
-#define portSWITCH_INT_NUMBER   0x80
-#define portYIELD()             __asm{ int portSWITCH_INT_NUMBER }
-#define portDOS_TICK_RATE       ( 18.20648 )
+#define portSTACK_GROWTH          ( -1 )
+#define portSWITCH_INT_NUMBER     0x80
+#define portYIELD()    __asm { int portSWITCH_INT_NUMBER }
+#define portDOS_TICK_RATE         ( 18.20648 )
 #define portTICK_PERIOD_MS        ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portTICKS_PER_DOS_TICK  ( ( uint16_t ) ( ( ( portDOUBLE ) configTICK_RATE_HZ / portDOS_TICK_RATE ) + 0.5 ) )
-#define portINITIAL_SW          ( ( portSTACK_TYPE ) 0x0202 )   /* Start the tasks with interrupts enabled. */
-#define portBYTE_ALIGNMENT      ( 2 )
+#define portTICKS_PER_DOS_TICK    ( ( uint16_t ) ( ( ( portDOUBLE ) configTICK_RATE_HZ / portDOS_TICK_RATE ) + 0.5 ) )
+#define portINITIAL_SW            ( ( portSTACK_TYPE ) 0x0202 ) /* Start the tasks with interrupts enabled. */
+#define portBYTE_ALIGNMENT        ( 2 )
 /*-----------------------------------------------------------*/
 
 /* Compiler specifics. */
-#define portINPUT_BYTE( xAddr )             inp( xAddr )
-#define portOUTPUT_BYTE( xAddr, ucValue )   outp( xAddr, ucValue )
-#define portNOP() __asm{ nop }
+#define portINPUT_BYTE( xAddr )              inp( xAddr )
+#define portOUTPUT_BYTE( xAddr, ucValue )    outp( xAddr, ucValue )
+#define portNOP()                            __asm { nop }
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vTaskFunction, pvParameters ) void vTaskFunction( void *pvParameters )
-#define portTASK_FUNCTION( vTaskFunction, pvParameters ) void vTaskFunction( void *pvParameters )
+#define portTASK_FUNCTION_PROTO( vTaskFunction, pvParameters )    void vTaskFunction( void * pvParameters )
+#define portTASK_FUNCTION( vTaskFunction, pvParameters )          void vTaskFunction( void * pvParameters )
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/oWatcom/16BitDOS/common/portasm.h b/portable/oWatcom/16BitDOS/common/portasm.h
index f77e2b553..997243293 100644
--- a/portable/oWatcom/16BitDOS/common/portasm.h
+++ b/portable/oWatcom/16BitDOS/common/portasm.h
@@ -45,65 +45,65 @@ void portSWITCH_CONTEXT( void );
 void portFIRST_CONTEXT( void );
 
 /* There are slightly different versions depending on whether you are building
-to include debugger information.  If debugger information is used then there
-are a couple of extra bytes left of the ISR stack (presumably for use by the
-debugger).  The true stack pointer is then stored in the bp register.  We add
-2 to the stack pointer to remove the extra bytes before we restore our context. */
+ * to include debugger information.  If debugger information is used then there
+ * are a couple of extra bytes left of the ISR stack (presumably for use by the
+ * debugger).  The true stack pointer is then stored in the bp register.  We add
+ * 2 to the stack pointer to remove the extra bytes before we restore our context. */
 
 #ifdef DEBUG_BUILD
 
-    #pragma aux portSWITCH_CONTEXT =    "mov    ax, seg pxCurrentTCB"                                                       \
-                                        "mov    ds, ax"                                                                     \
-                                        "les    bx, pxCurrentTCB"           /* Save the stack pointer into the TCB. */      \
-                                        "mov    es:0x2[ bx ], ss"                                                           \
-                                        "mov    es:[ bx ], sp"                                                              \
-                                        "call   vTaskSwitchContext"         /* Perform the switch. */                       \
-                                        "mov    ax, seg pxCurrentTCB"       /* Restore the stack pointer from the TCB. */   \
-                                        "mov    ds, ax"                                                                     \
-                                        "les    bx, dword ptr pxCurrentTCB"                                                 \
-                                        "mov    ss, es:[ bx + 2 ]"                                                          \
-                                        "mov    sp, es:[ bx ]"                                                              \
-                                        "mov    bp, sp"                     /* Prepair the bp register for the restoration of the SP in the compiler generated portion of the ISR */    \
-                                        "add    bp, 0x0002"
+    #pragma aux portSWITCH_CONTEXT =    "mov    ax, seg pxCurrentTCB"                                                        \
+    "mov    ds, ax"                                                                                                          \
+    "les    bx, pxCurrentTCB" /* Save the stack pointer into the TCB. */                                                     \
+    "mov    es:0x2[ bx ], ss"                                                                                                \
+    "mov    es:[ bx ], sp"                                                                                                   \
+    "call   vTaskSwitchContext"   /* Perform the switch. */                                                                  \
+    "mov    ax, seg pxCurrentTCB" /* Restore the stack pointer from the TCB. */                                              \
+    "mov    ds, ax"                                                                                                          \
+    "les    bx, dword ptr pxCurrentTCB"                                                                                      \
+    "mov    ss, es:[ bx + 2 ]"                                                                                               \
+    "mov    sp, es:[ bx ]"                                                                                                   \
+    "mov    bp, sp" /* Prepair the bp register for the restoration of the SP in the compiler generated portion of the ISR */ \
+    "add    bp, 0x0002"
 
 
 
-    #pragma aux portFIRST_CONTEXT =     "mov    ax, seg pxCurrentTCB"           \
-                                        "mov    ds, ax"                         \
-                                        "les    bx, dword ptr pxCurrentTCB"     \
-                                        "mov    ss, es:[ bx + 2 ]"              \
-                                        "mov    sp, es:[ bx ]"                  \
-                                        "add    sp, 0x0002"                     /* Remove the extra bytes that exist in debug builds before restoring the context. */ \
-                                        "pop    ax"                             \
-                                        "pop    ax"                             \
-                                        "pop    es"                             \
-                                        "pop    ds"                             \
-                                        "popa"                                  \
-                                        "iret"
-#else
+    #pragma aux portFIRST_CONTEXT =     "mov    ax, seg pxCurrentTCB"                                         \
+    "mov    ds, ax"                                                                                           \
+    "les    bx, dword ptr pxCurrentTCB"                                                                       \
+    "mov    ss, es:[ bx + 2 ]"                                                                                \
+    "mov    sp, es:[ bx ]"                                                                                    \
+    "add    sp, 0x0002" /* Remove the extra bytes that exist in debug builds before restoring the context. */ \
+    "pop    ax"                                                                                               \
+    "pop    ax"                                                                                               \
+    "pop    es"                                                                                               \
+    "pop    ds"                                                                                               \
+    "popa"                                                                                                    \
+    "iret"
+#else /* ifdef DEBUG_BUILD */
 
-    #pragma aux portSWITCH_CONTEXT =    "mov    ax, seg pxCurrentTCB"                                                       \
-                                        "mov    ds, ax"                                                                     \
-                                        "les    bx, pxCurrentTCB"           /* Save the stack pointer into the TCB. */      \
-                                        "mov    es:0x2[ bx ], ss"                                                           \
-                                        "mov    es:[ bx ], sp"                                                              \
-                                        "call   vTaskSwitchContext"         /* Perform the switch. */                       \
-                                        "mov    ax, seg pxCurrentTCB"       /* Restore the stack pointer from the TCB. */   \
-                                        "mov    ds, ax"                                                                     \
-                                        "les    bx, dword ptr pxCurrentTCB"                                                 \
-                                        "mov    ss, es:[ bx + 2 ]"                                                          \
-                                        "mov    sp, es:[ bx ]"
+    #pragma aux portSWITCH_CONTEXT =    "mov    ax, seg pxCurrentTCB"           \
+    "mov    ds, ax"                                                             \
+    "les    bx, pxCurrentTCB" /* Save the stack pointer into the TCB. */        \
+    "mov    es:0x2[ bx ], ss"                                                   \
+    "mov    es:[ bx ], sp"                                                      \
+    "call   vTaskSwitchContext"   /* Perform the switch. */                     \
+    "mov    ax, seg pxCurrentTCB" /* Restore the stack pointer from the TCB. */ \
+    "mov    ds, ax"                                                             \
+    "les    bx, dword ptr pxCurrentTCB"                                         \
+    "mov    ss, es:[ bx + 2 ]"                                                  \
+    "mov    sp, es:[ bx ]"
 
 
-    #pragma aux portFIRST_CONTEXT =     "mov    ax, seg pxCurrentTCB"           \
-                                        "mov    ds, ax"                         \
-                                        "les    bx, dword ptr pxCurrentTCB"     \
-                                        "mov    ss, es:[ bx + 2 ]"              \
-                                        "mov    sp, es:[ bx ]"                  \
-                                        "pop    ax"                             \
-                                        "pop    ax"                             \
-                                        "pop    es"                             \
-                                        "pop    ds"                             \
-                                        "popa"                                  \
-                                        "iret"
-#endif
+    #pragma aux portFIRST_CONTEXT =     "mov    ax, seg pxCurrentTCB" \
+    "mov    ds, ax"                                                   \
+    "les    bx, dword ptr pxCurrentTCB"                               \
+    "mov    ss, es:[ bx + 2 ]"                                        \
+    "mov    sp, es:[ bx ]"                                            \
+    "pop    ax"                                                       \
+    "pop    ax"                                                       \
+    "pop    es"                                                       \
+    "pop    ds"                                                       \
+    "popa"                                                            \
+    "iret"
+#endif /* ifdef DEBUG_BUILD */
diff --git a/portable/oWatcom/16BitDOS/common/portcomn.c b/portable/oWatcom/16BitDOS/common/portcomn.c
index 2a7b66637..54c06f675 100644
--- a/portable/oWatcom/16BitDOS/common/portcomn.c
+++ b/portable/oWatcom/16BitDOS/common/portcomn.c
@@ -27,21 +27,21 @@
  */
 
 /*
-Changes from V1.00:
-
-    + pxPortInitialiseStack() now initialises the stack of new tasks to the
-      same format used by the compiler.  This allows the compiler generated
-      interrupt mechanism to be used for context switches.
-
-Changes from V2.4.2:
-
-    + pvPortMalloc and vPortFree have been removed.  The projects now use
-      the definitions from the source/portable/MemMang directory.
-
-Changes from V2.6.1:
-
-    + usPortCheckFreeStackSpace() has been moved to tasks.c.
-*/
+ * Changes from V1.00:
+ *
+ + pxPortInitialiseStack() now initialises the stack of new tasks to the
+ +    same format used by the compiler.  This allows the compiler generated
+ +    interrupt mechanism to be used for context switches.
+ +
+ + Changes from V2.4.2:
+ +
+ + pvPortMalloc and vPortFree have been removed.  The projects now use
+ +    the definitions from the source/portable/MemMang directory.
+ +
+ + Changes from V2.6.1:
+ +
+ + usPortCheckFreeStackSpace() has been moved to tasks.c.
+ */
 
 
 
@@ -51,13 +51,15 @@ Changes from V2.6.1:
 /*-----------------------------------------------------------*/
 
 /* See header file for description. */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
 {
-StackType_t DS_Reg = 0;
-StackType_t * pxOriginalSP;
+    StackType_t DS_Reg = 0;
+    StackType_t * pxOriginalSP;
 
     /* Place a few bytes of known values on the bottom of the stack.
-    This is just useful for debugging. */
+     * This is just useful for debugging. */
 
     *pxTopOfStack = 0x1111;
     pxTopOfStack--;
@@ -74,9 +76,9 @@ StackType_t * pxOriginalSP;
     /*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */
 
     /* We are going to start the scheduler using a return from interrupt
-    instruction to load the program counter, so first there would be the
-    status register and interrupt return address.  We make this the start
-    of the task. */
+     * instruction to load the program counter, so first there would be the
+     * status register and interrupt return address.  We make this the start
+     * of the task. */
     *pxTopOfStack = portINITIAL_SW;
     pxTopOfStack--;
     *pxTopOfStack = FP_SEG( pxCode );
@@ -85,24 +87,24 @@ StackType_t * pxOriginalSP;
     pxTopOfStack--;
 
     /* We are going to setup the stack for the new task to look like
-    the stack frame was setup by a compiler generated ISR.  We need to know
-    the address of the existing stack top to place in the SP register within
-    the stack frame.  pxOriginalSP holds SP before (simulated) pusha was
-    called. */
+     * the stack frame was setup by a compiler generated ISR.  We need to know
+     * the address of the existing stack top to place in the SP register within
+     * the stack frame.  pxOriginalSP holds SP before (simulated) pusha was
+     * called. */
     pxOriginalSP = pxTopOfStack;
 
     /* The remaining registers would be pushed on the stack by our context
-    switch function.  These are loaded with values simply to make debugging
-    easier. */
-    *pxTopOfStack = FP_OFF( pvParameters );     /* AX */
+     * switch function.  These are loaded with values simply to make debugging
+     * easier. */
+    *pxTopOfStack = FP_OFF( pvParameters ); /* AX */
     pxTopOfStack--;
     *pxTopOfStack = ( StackType_t ) 0xCCCC; /* CX */
     pxTopOfStack--;
-    *pxTopOfStack = FP_SEG( pvParameters );     /* DX */
+    *pxTopOfStack = FP_SEG( pvParameters ); /* DX */
     pxTopOfStack--;
     *pxTopOfStack = ( StackType_t ) 0xBBBB; /* BX */
     pxTopOfStack--;
-    *pxTopOfStack = FP_OFF( pxOriginalSP );     /* SP */
+    *pxTopOfStack = FP_OFF( pxOriginalSP ); /* SP */
     pxTopOfStack--;
     *pxTopOfStack = ( StackType_t ) 0xBBBB; /* BP */
     pxTopOfStack--;
@@ -111,7 +113,9 @@ StackType_t * pxOriginalSP;
     *pxTopOfStack = ( StackType_t ) 0xDDDD; /* DI */
 
     /* We need the true data segment. */
-    __asm{  MOV DS_Reg, DS };
+    __asm {
+        MOV DS_Reg, DS
+    };
 
     pxTopOfStack--;
     *pxTopOfStack = DS_Reg; /* DS */
@@ -121,16 +125,17 @@ StackType_t * pxOriginalSP;
 
     /* The AX register is pushed again twice - don't know why. */
     pxTopOfStack--;
-    *pxTopOfStack = FP_OFF( pvParameters );     /* AX */
+    *pxTopOfStack = FP_OFF( pvParameters ); /* AX */
     pxTopOfStack--;
-    *pxTopOfStack = FP_OFF( pvParameters );     /* AX */
+    *pxTopOfStack = FP_OFF( pvParameters ); /* AX */
 
 
     #ifdef DEBUG_BUILD
+
         /* The compiler adds space to each ISR stack if building to
-        include debug information.  Presumably this is used by the
-        debugger - we don't need to initialise it to anything just
-        make sure it is there. */
+         * include debug information.  Presumably this is used by the
+         * debugger - we don't need to initialise it to anything just
+         * make sure it is there. */
         pxTopOfStack--;
     #endif
 
diff --git a/queue.c b/queue.c
old mode 100755
new mode 100644
diff --git a/timers.c b/timers.c
index f2a210c51..abe39e12c 100644
--- a/timers.c
+++ b/timers.c
@@ -294,7 +294,7 @@
         {
             Timer_t * pxNewTimer;
 
-            pxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of Timer_t is always a pointer to the timer's mame. */
+            pxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of Timer_t is always a pointer to the timer's name. */
 
             if( pxNewTimer != NULL )
             {

From 288d143357e81768aa01500b1b875986df8da5a8 Mon Sep 17 00:00:00 2001
From: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Date: Wed, 6 Sep 2023 15:13:34 +0800
Subject: [PATCH 049/424] Update taskSELECT_HIGHEST_PRIORITY_TASK macro for SMP
 (#777)

* Move the configUSE_PORT_OPTIMISED_TASK_SELECTION check to FreeRTOS.h
* SMP also use taskSELECT_HIGHEST_PRIORITY_TASK macro
---------

Co-authored-by: Soren Ptak <ptaksoren@gmail.com>
---
 include/FreeRTOS.h |  4 ++++
 tasks.c            | 10 +++++-----
 2 files changed, 9 insertions(+), 5 deletions(-)

diff --git a/include/FreeRTOS.h b/include/FreeRTOS.h
index ca5818eae..1a6468b18 100644
--- a/include/FreeRTOS.h
+++ b/include/FreeRTOS.h
@@ -1165,6 +1165,10 @@
     #error configUSE_TASK_PREEMPTION_DISABLE is not supported in single core FreeRTOS
 #endif
 
+#if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_PORT_OPTIMISED_TASK_SELECTION != 0 ) )
+    #error configUSE_PORT_OPTIMISED_TASK_SELECTION is not supported in SMP FreeRTOS
+#endif
+
 #ifndef configINITIAL_TICK_COUNT
     #define configINITIAL_TICK_COUNT    0
 #endif
diff --git a/tasks.c b/tasks.c
index 6cb233e7a..a0651b1b6 100644
--- a/tasks.c
+++ b/tasks.c
@@ -152,6 +152,10 @@
         listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) ); \
         uxTopReadyPriority = uxTopPriority;                                                   \
     } while( 0 ) /* taskSELECT_HIGHEST_PRIORITY_TASK */
+    #else /* if ( configNUMBER_OF_CORES == 1 ) */
+
+        #define taskSELECT_HIGHEST_PRIORITY_TASK( xCoreID )    prvSelectHighestPriorityTask( xCoreID )
+
     #endif /* if ( configNUMBER_OF_CORES == 1 ) */
 
 /*-----------------------------------------------------------*/
@@ -164,10 +168,6 @@
 
 #else /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 
-    #if ( configNUMBER_OF_CORES > 1 )
-        #error configUSE_PORT_OPTIMISED_TASK_SELECTION not supported in FreeRTOS SMP.
-    #endif
-
 /* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 1 then task selection is
  * performed in a way that is tailored to the particular microcontroller
  * architecture being used. */
@@ -4701,7 +4701,7 @@ BaseType_t xTaskIncrementTick( void )
                 #endif
 
                 /* Select a new task to run. */
-                prvSelectHighestPriorityTask( xCoreID );
+                taskSELECT_HIGHEST_PRIORITY_TASK( xCoreID );
                 traceTASK_SWITCHED_IN();
 
                 /* After the new task is switched in, update the global errno. */

From 53229b15378b7464c0011961a72c6dfd1d9f01a2 Mon Sep 17 00:00:00 2001
From: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Date: Wed, 6 Sep 2023 17:47:41 +0800
Subject: [PATCH 050/424] Assert if prvCheckForRunStateChange is called in ISR
 (#779)

* Assert if prvCheckForRunStateChange is called in ISR
---
 tasks.c | 88 +++++++++++++++++++++++++++------------------------------
 1 file changed, 42 insertions(+), 46 deletions(-)

diff --git a/tasks.c b/tasks.c
index a0651b1b6..7eaef888b 100644
--- a/tasks.c
+++ b/tasks.c
@@ -693,62 +693,58 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
         UBaseType_t uxPrevCriticalNesting;
         const TCB_t * pxThisTCB;
 
-        /* This should be skipped if called from an ISR. If the task on the current
-         * core is no longer running, then vTaskSwitchContext() probably should
-         * be run before returning, but we don't have a way to force that to happen
-         * from here. */
-        if( portCHECK_IF_IN_ISR() == pdFALSE )
+        /* This must only be called from within a task. */
+        portASSERT_IF_IN_ISR();
+
+        /* This function is always called with interrupts disabled
+         * so this is safe. */
+        pxThisTCB = pxCurrentTCBs[ portGET_CORE_ID() ];
+
+        while( pxThisTCB->xTaskRunState == taskTASK_YIELDING )
         {
-            /* This function is always called with interrupts disabled
-             * so this is safe. */
-            pxThisTCB = pxCurrentTCBs[ portGET_CORE_ID() ];
+            /* We are only here if we just entered a critical section
+            * or if we just suspended the scheduler, and another task
+            * has requested that we yield.
+            *
+            * This is slightly complicated since we need to save and restore
+            * the suspension and critical nesting counts, as well as release
+            * and reacquire the correct locks. And then, do it all over again
+            * if our state changed again during the reacquisition. */
+            uxPrevCriticalNesting = portGET_CRITICAL_NESTING_COUNT();
 
-            while( pxThisTCB->xTaskRunState == taskTASK_YIELDING )
+            if( uxPrevCriticalNesting > 0U )
             {
-                /* We are only here if we just entered a critical section
-                * or if we just suspended the scheduler, and another task
-                * has requested that we yield.
-                *
-                * This is slightly complicated since we need to save and restore
-                * the suspension and critical nesting counts, as well as release
-                * and reacquire the correct locks. And then, do it all over again
-                * if our state changed again during the reacquisition. */
-                uxPrevCriticalNesting = portGET_CRITICAL_NESTING_COUNT();
+                portSET_CRITICAL_NESTING_COUNT( 0U );
+                portRELEASE_ISR_LOCK();
+            }
+            else
+            {
+                /* The scheduler is suspended. uxSchedulerSuspended is updated
+                 * only when the task is not requested to yield. */
+                mtCOVERAGE_TEST_MARKER();
+            }
 
-                if( uxPrevCriticalNesting > 0U )
-                {
-                    portSET_CRITICAL_NESTING_COUNT( 0U );
-                    portRELEASE_ISR_LOCK();
-                }
-                else
-                {
-                    /* The scheduler is suspended. uxSchedulerSuspended is updated
-                     * only when the task is not requested to yield. */
-                    mtCOVERAGE_TEST_MARKER();
-                }
+            portRELEASE_TASK_LOCK();
 
-                portRELEASE_TASK_LOCK();
+            portMEMORY_BARRIER();
+            configASSERT( pxThisTCB->xTaskRunState == taskTASK_YIELDING );
 
-                portMEMORY_BARRIER();
-                configASSERT( pxThisTCB->xTaskRunState == taskTASK_YIELDING );
+            portENABLE_INTERRUPTS();
 
-                portENABLE_INTERRUPTS();
+            /* Enabling interrupts should cause this core to immediately
+             * service the pending interrupt and yield. If the run state is still
+             * yielding here then that is a problem. */
+            configASSERT( pxThisTCB->xTaskRunState != taskTASK_YIELDING );
 
-                /* Enabling interrupts should cause this core to immediately
-                 * service the pending interrupt and yield. If the run state is still
-                 * yielding here then that is a problem. */
-                configASSERT( pxThisTCB->xTaskRunState != taskTASK_YIELDING );
+            portDISABLE_INTERRUPTS();
+            portGET_TASK_LOCK();
+            portGET_ISR_LOCK();
 
-                portDISABLE_INTERRUPTS();
-                portGET_TASK_LOCK();
-                portGET_ISR_LOCK();
+            portSET_CRITICAL_NESTING_COUNT( uxPrevCriticalNesting );
 
-                portSET_CRITICAL_NESTING_COUNT( uxPrevCriticalNesting );
-
-                if( uxPrevCriticalNesting == 0U )
-                {
-                    portRELEASE_ISR_LOCK();
-                }
+            if( uxPrevCriticalNesting == 0U )
+            {
+                portRELEASE_ISR_LOCK();
             }
         }
     }

From c93d3865f7a710083ee61d0b0fa689338891beb2 Mon Sep 17 00:00:00 2001
From: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Date: Wed, 6 Sep 2023 18:30:02 +0800
Subject: [PATCH 051/424] Update task running state type and related macros
 (#770)

* Remove unnecessary type TaskRunning_t
* Rename taskTASK_YIELD to taskTASK_SCHEDULED_TO_YIELD
---------
Co-authored-by: Soren Ptak <ptaksoren@gmail.com>
---
 tasks.c | 32 ++++++++++++++------------------
 1 file changed, 14 insertions(+), 18 deletions(-)

diff --git a/tasks.c b/tasks.c
index 7eaef888b..1efb0d3e3 100644
--- a/tasks.c
+++ b/tasks.c
@@ -259,14 +259,11 @@
     #define taskEVENT_LIST_ITEM_VALUE_IN_USE    0x8000000000000000ULL
 #endif
 
-/* Task state. */
-typedef BaseType_t TaskRunning_t;
-
 /* Indicates that the task is not actively running on any core. */
-#define taskTASK_NOT_RUNNING    ( TaskRunning_t ) ( -1 )
+#define taskTASK_NOT_RUNNING           ( ( BaseType_t ) ( -1 ) )
 
 /* Indicates that the task is actively running but scheduled to yield. */
-#define taskTASK_YIELDING       ( TaskRunning_t ) ( -2 )
+#define taskTASK_SCHEDULED_TO_YIELD    ( ( BaseType_t ) ( -2 ) )
 
 /* Returns pdTRUE if the task is actively running and not scheduled to yield. */
 #if ( configNUMBER_OF_CORES == 1 )
@@ -313,7 +310,7 @@ typedef struct tskTaskControlBlock       /* The old naming convention is used to
     UBaseType_t uxPriority;                     /**< The priority of the task.  0 is the lowest priority. */
     StackType_t * pxStack;                      /**< Points to the start of the stack. */
     #if ( configNUMBER_OF_CORES > 1 )
-        volatile TaskRunning_t xTaskRunState;   /**< Used to identify the core the task is running on, if the task is running. Otherwise, identifies the task's state - not running or yielding. */
+        volatile BaseType_t xTaskRunState;      /**< Used to identify the core the task is running on, if the task is running. Otherwise, identifies the task's state - not running or yielding. */
         UBaseType_t uxTaskAttributes;           /**< Task's attributes - currently used to identify the idle tasks. */
     #endif
     char pcTaskName[ configMAX_TASK_NAME_LEN ]; /**< Descriptive name given to the task when created.  Facilitates debugging only. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
@@ -700,7 +697,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
          * so this is safe. */
         pxThisTCB = pxCurrentTCBs[ portGET_CORE_ID() ];
 
-        while( pxThisTCB->xTaskRunState == taskTASK_YIELDING )
+        while( pxThisTCB->xTaskRunState == taskTASK_SCHEDULED_TO_YIELD )
         {
             /* We are only here if we just entered a critical section
             * or if we just suspended the scheduler, and another task
@@ -725,16 +722,15 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
             }
 
             portRELEASE_TASK_LOCK();
-
             portMEMORY_BARRIER();
-            configASSERT( pxThisTCB->xTaskRunState == taskTASK_YIELDING );
+            configASSERT( pxThisTCB->xTaskRunState == taskTASK_SCHEDULED_TO_YIELD );
 
             portENABLE_INTERRUPTS();
 
             /* Enabling interrupts should cause this core to immediately
              * service the pending interrupt and yield. If the run state is still
              * yielding here then that is a problem. */
-            configASSERT( pxThisTCB->xTaskRunState != taskTASK_YIELDING );
+            configASSERT( pxThisTCB->xTaskRunState != taskTASK_SCHEDULED_TO_YIELD );
 
             portDISABLE_INTERRUPTS();
             portGET_TASK_LOCK();
@@ -762,7 +758,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
         }
         else
         {
-            if( pxCurrentTCBs[ xCoreID ]->xTaskRunState != taskTASK_YIELDING )
+            if( pxCurrentTCBs[ xCoreID ]->xTaskRunState != taskTASK_SCHEDULED_TO_YIELD )
             {
                 if( xCoreID == ( BaseType_t ) portGET_CORE_ID() )
                 {
@@ -771,7 +767,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
                 else
                 {
                     portYIELD_CORE( xCoreID );
-                    pxCurrentTCBs[ xCoreID ]->xTaskRunState = taskTASK_YIELDING;
+                    pxCurrentTCBs[ xCoreID ]->xTaskRunState = taskTASK_SCHEDULED_TO_YIELD;
                 }
             }
         }
@@ -982,21 +978,21 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
                             #if ( configUSE_CORE_AFFINITY == 1 )
                                 pxPreviousTCB = pxCurrentTCBs[ xCoreID ];
                             #endif
-                            pxTCB->xTaskRunState = ( TaskRunning_t ) xCoreID;
+                            pxTCB->xTaskRunState = xCoreID;
                             pxCurrentTCBs[ xCoreID ] = pxTCB;
                             xTaskScheduled = pdTRUE;
                         }
                     }
                     else if( pxTCB == pxCurrentTCBs[ xCoreID ] )
                     {
-                        configASSERT( ( pxTCB->xTaskRunState == xCoreID ) || ( pxTCB->xTaskRunState == taskTASK_YIELDING ) );
+                        configASSERT( ( pxTCB->xTaskRunState == xCoreID ) || ( pxTCB->xTaskRunState == taskTASK_SCHEDULED_TO_YIELD ) );
 
                         #if ( configUSE_CORE_AFFINITY == 1 )
                             if( ( pxTCB->uxCoreAffinityMask & ( ( UBaseType_t ) 1U << ( UBaseType_t ) xCoreID ) ) != 0U )
                         #endif
                         {
                             /* The task is already running on this core, mark it as scheduled. */
-                            pxTCB->xTaskRunState = ( TaskRunning_t ) xCoreID;
+                            pxTCB->xTaskRunState = xCoreID;
                             xTaskScheduled = pdTRUE;
                         }
                     }
@@ -1999,7 +1995,7 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
             /* Force a reschedule if the task that has just been deleted was running. */
             if( ( xSchedulerRunning != pdFALSE ) && ( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE ) )
             {
-                if( pxTCB->xTaskRunState == ( TaskRunning_t ) portGET_CORE_ID() )
+                if( pxTCB->xTaskRunState == ( BaseType_t ) portGET_CORE_ID() )
                 {
                     configASSERT( uxSchedulerSuspended == 0 );
                     vTaskYieldWithinAPI();
@@ -2704,7 +2700,7 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
         TCB_t * pxTCB;
 
         #if ( configNUMBER_OF_CORES > 1 )
-            TaskRunning_t xTaskRunningOnCore;
+            BaseType_t xTaskRunningOnCore;
         #endif
 
         taskENTER_CRITICAL();
@@ -2827,7 +2823,7 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
             {
                 if( xSchedulerRunning != pdFALSE )
                 {
-                    if( xTaskRunningOnCore == ( TaskRunning_t ) portGET_CORE_ID() )
+                    if( xTaskRunningOnCore == ( BaseType_t ) portGET_CORE_ID() )
                     {
                         /* The current task has just been suspended. */
                         configASSERT( uxSchedulerSuspended == 0 );

From f7565c2d5e4b88a7d8ab2816834c6e6274b34234 Mon Sep 17 00:00:00 2001
From: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Date: Wed, 6 Sep 2023 19:09:52 +0800
Subject: [PATCH 052/424] Add configUSE_CORE_AFFINITY bits check (#776)

* Add core affinity bits check
* Add taskBITS_PER_BYTES
---
 include/FreeRTOS.h |  4 ++++
 tasks.c            | 12 +++++++++++-
 2 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/include/FreeRTOS.h b/include/FreeRTOS.h
index 1a6468b18..980c9d0f8 100644
--- a/include/FreeRTOS.h
+++ b/include/FreeRTOS.h
@@ -1165,6 +1165,10 @@
     #error configUSE_TASK_PREEMPTION_DISABLE is not supported in single core FreeRTOS
 #endif
 
+#if ( ( configNUMBER_OF_CORES == 1 ) && ( configUSE_CORE_AFFINITY != 0 ) )
+    #error configUSE_CORE_AFFINITY is not supported in single core FreeRTOS
+#endif
+
 #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_PORT_OPTIMISED_TASK_SELECTION != 0 ) )
     #error configUSE_PORT_OPTIMISED_TASK_SELECTION is not supported in SMP FreeRTOS
 #endif
diff --git a/tasks.c b/tasks.c
index 1efb0d3e3..6b1c7a65f 100644
--- a/tasks.c
+++ b/tasks.c
@@ -288,6 +288,8 @@
     #define INFINITE_LOOP()    1
 #endif
 
+#define taskBITS_PER_BYTE    ( ( size_t ) 8 )
+
 /*
  * Task control block.  A task control block (TCB) is allocated for each task,
  * and stores task state information, including a pointer to the task's context
@@ -302,7 +304,7 @@ typedef struct tskTaskControlBlock       /* The old naming convention is used to
     #endif
 
     #if ( configUSE_CORE_AFFINITY == 1 ) && ( configNUMBER_OF_CORES > 1 )
-        UBaseType_t uxCoreAffinityMask; /*< Used to link the task to certain cores.  UBaseType_t must have greater than or equal to the number of bits as confNUM_CORES. */
+        UBaseType_t uxCoreAffinityMask; /**< Used to link the task to certain cores.  UBaseType_t must have greater than or equal to the number of bits as configNUMBER_OF_CORES. */
     #endif
 
     ListItem_t xStateListItem;                  /**< The list that the state list item of a task is reference from denotes the state of that task (Ready, Blocked, Suspended ). */
@@ -3249,6 +3251,14 @@ void vTaskStartScheduler( void )
 {
     BaseType_t xReturn;
 
+    #if ( configUSE_CORE_AFFINITY == 1 ) && ( configNUMBER_OF_CORES > 1 )
+    {
+        /* Sanity check that the UBaseType_t must have greater than or equal to
+         * the number of bits as confNUMBER_OF_CORES. */
+        configASSERT( ( sizeof( UBaseType_t ) * taskBITS_PER_BYTE ) >= configNUMBER_OF_CORES );
+    }
+    #endif /* #if ( configUSE_CORE_AFFINITY == 1 ) && ( configNUMBER_OF_CORES > 1 ) */
+
     xReturn = prvCreateIdleTasks();
 
     #if ( configUSE_TIMERS == 1 )

From f13ad7789b73f227f2d4a5f3d98025b00314ee0c Mon Sep 17 00:00:00 2001
From: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Date: Wed, 6 Sep 2023 19:18:43 +0800
Subject: [PATCH 053/424] Add macro taskTASK_IS_RUNNING_OR_SCHEDULED_TO_YIELD
 (#780)

* Add macro taskTASK_IS_RUNNING_OR_SCHEDULED_TO_YIELD macro to align single core and SMP
* Update for explicit precedence in vTaskDelete
* Update comment when deleting a running task
---
 tasks.c | 27 +++++++++++++--------------
 1 file changed, 13 insertions(+), 14 deletions(-)

diff --git a/tasks.c b/tasks.c
index 6b1c7a65f..01f972ba0 100644
--- a/tasks.c
+++ b/tasks.c
@@ -267,9 +267,11 @@
 
 /* Returns pdTRUE if the task is actively running and not scheduled to yield. */
 #if ( configNUMBER_OF_CORES == 1 )
-    #define taskTASK_IS_RUNNING( pxTCB )    ( ( ( pxTCB ) == pxCurrentTCB ) ? ( pdTRUE ) : ( pdFALSE ) )
+    #define taskTASK_IS_RUNNING( pxTCB )                          ( ( ( pxTCB ) == pxCurrentTCB ) ? ( pdTRUE ) : ( pdFALSE ) )
+    #define taskTASK_IS_RUNNING_OR_SCHEDULED_TO_YIELD( pxTCB )    ( ( ( pxTCB ) == pxCurrentTCB ) ? ( pdTRUE ) : ( pdFALSE ) )
 #else
-    #define taskTASK_IS_RUNNING( pxTCB )    ( ( ( ( pxTCB )->xTaskRunState >= ( BaseType_t ) 0 ) && ( ( pxTCB )->xTaskRunState < ( BaseType_t ) configNUMBER_OF_CORES ) ) ? ( pdTRUE ) : ( pdFALSE ) )
+    #define taskTASK_IS_RUNNING( pxTCB )                          ( ( ( ( pxTCB )->xTaskRunState >= ( BaseType_t ) 0 ) && ( ( pxTCB )->xTaskRunState < ( BaseType_t ) configNUMBER_OF_CORES ) ) ? ( pdTRUE ) : ( pdFALSE ) )
+    #define taskTASK_IS_RUNNING_OR_SCHEDULED_TO_YIELD( pxTCB )    ( ( ( pxTCB )->xTaskRunState != taskTASK_NOT_RUNNING ) ? ( pdTRUE ) : ( pdFALSE ) )
 #endif
 
 /* Indicates that the task is an Idle task. */
@@ -1913,17 +1915,14 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
             /* If the task is running (or yielding), we must add it to the
              * termination list so that an idle task can delete it when it is
              * no longer running. */
-            #if ( configNUMBER_OF_CORES == 1 )
-                if( pxTCB == pxCurrentTCB )
-            #else
-                if( pxTCB->xTaskRunState != taskTASK_NOT_RUNNING )
-            #endif
+            if( taskTASK_IS_RUNNING_OR_SCHEDULED_TO_YIELD( pxTCB ) != pdFALSE )
             {
-                /* A running task is being deleted.  This cannot complete within the
-                 * task itself, as a context switch to another task is required.
-                 * Place the task in the termination list.  The idle task will
-                 * check the termination list and free up any memory allocated by
-                 * the scheduler for the TCB and stack of the deleted task. */
+                /* A running task or a task which is scheduled to yield is being
+                 * deleted. This cannot complete when the task is still running
+                 * on a core, as a context switch to another task is required.
+                 * Place the task in the termination list. The idle task will check
+                 * the termination list and free up any memory allocated by the
+                 * scheduler for the TCB and stack of the deleted task. */
                 vListInsertEnd( &xTasksWaitingTermination, &( pxTCB->xStateListItem ) );
 
                 /* Increment the ucTasksDeleted variable so the idle task knows
@@ -1941,9 +1940,9 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
                  * hence xYieldPending is used to latch that a context switch is
                  * required. */
                 #if ( configNUMBER_OF_CORES == 1 )
-                    portPRE_TASK_DELETE_HOOK( pxTCB, &xYieldPendings[ 0 ] );
+                    portPRE_TASK_DELETE_HOOK( pxTCB, &( xYieldPendings[ 0 ] ) );
                 #else
-                    portPRE_TASK_DELETE_HOOK( pxTCB, &xYieldPendings[ pxTCB->xTaskRunState ] );
+                    portPRE_TASK_DELETE_HOOK( pxTCB, &( xYieldPendings[ pxTCB->xTaskRunState ] ) );
                 #endif
             }
             else

From 2f94b181a2f049ec342deba0927bed51f7174ab0 Mon Sep 17 00:00:00 2001
From: Boris van der Meer <borisvandermeer@hotmail.com>
Date: Fri, 8 Sep 2023 01:20:13 +0200
Subject: [PATCH 054/424] Add Trace Hook Macros and function that returns the
 start of the stack. (#659)

* Add Trace Hook Macros and function that returns the start of the stack.

* Remove obsolete functions.

---------

Co-authored-by: kar-rahul-aws <118818625+kar-rahul-aws@users.noreply.github.com>
Co-authored-by: Rahul Kar <karahulx@amazon.com>
Co-authored-by: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
---
 include/FreeRTOS.h                    | 20 ++++++++++++++++++++
 portable/GCC/ARM_CM7/r0p1/port.c      |  7 +++++++
 portable/GCC/ARM_CM7/r0p1/portmacro.h |  7 +++++--
 tasks.c                               |  4 ++++
 4 files changed, 36 insertions(+), 2 deletions(-)

diff --git a/include/FreeRTOS.h b/include/FreeRTOS.h
index 980c9d0f8..a2b84185f 100644
--- a/include/FreeRTOS.h
+++ b/include/FreeRTOS.h
@@ -653,6 +653,14 @@
     #define tracePOST_MOVED_TASK_TO_READY_STATE( pxTCB )
 #endif
 
+#ifndef traceMOVED_TASK_TO_DELAYED_LIST
+    #define traceMOVED_TASK_TO_DELAYED_LIST()
+#endif
+
+#ifndef traceMOVED_TASK_TO_OVERFLOW_DELAYED_LIST
+    #define traceMOVED_TASK_TO_OVERFLOW_DELAYED_LIST()
+#endif
+
 #ifndef traceQUEUE_CREATE
     #define traceQUEUE_CREATE( pxNewQueue )
 #endif
@@ -901,6 +909,18 @@
     #define traceTASK_NOTIFY_GIVE_FROM_ISR( uxIndexToNotify )
 #endif
 
+#ifndef traceISR_EXIT_TO_SCHEDULER
+    #define traceISR_EXIT_TO_SCHEDULER()
+#endif
+
+#ifndef traceISR_EXIT
+    #define traceISR_EXIT()
+#endif
+
+#ifndef traceISR_ENTER
+    #define traceISR_ENTER()
+#endif
+
 #ifndef traceSTREAM_BUFFER_CREATE_FAILED
     #define traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer )
 #endif
diff --git a/portable/GCC/ARM_CM7/r0p1/port.c b/portable/GCC/ARM_CM7/r0p1/port.c
index ccaaf884e..c22a3592b 100644
--- a/portable/GCC/ARM_CM7/r0p1/port.c
+++ b/portable/GCC/ARM_CM7/r0p1/port.c
@@ -511,14 +511,21 @@ void xPortSysTickHandler( void )
      * save and then restore the interrupt mask value as its value is already
      * known. */
     portDISABLE_INTERRUPTS();
+    traceISR_ENTER();
     {
         /* Increment the RTOS tick. */
         if( xTaskIncrementTick() != pdFALSE )
         {
+            traceISR_EXIT_TO_SCHEDULER();
+
             /* A context switch is required.  Context switching is performed in
              * the PendSV interrupt.  Pend the PendSV interrupt. */
             portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
         }
+        else
+        {
+            traceISR_EXIT();
+        }
     }
     portENABLE_INTERRUPTS();
 }
diff --git a/portable/GCC/ARM_CM7/r0p1/portmacro.h b/portable/GCC/ARM_CM7/r0p1/portmacro.h
index 96d5e3579..d32af2b75 100644
--- a/portable/GCC/ARM_CM7/r0p1/portmacro.h
+++ b/portable/GCC/ARM_CM7/r0p1/portmacro.h
@@ -95,8 +95,11 @@ typedef unsigned long    UBaseType_t;
 
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired != pdFALSE ) portYIELD( ); } while( 0 )
-#define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+#define portEND_SWITCHING_ISR( xSwitchRequired )                                         \
+    do { if( xSwitchRequired != pdFALSE ) { traceISR_EXIT_TO_SCHEDULER(); portYIELD(); } \
+         else { traceISR_EXIT(); }                                                       \
+    } while( 0 )
+#define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
 /* Critical section management. */
diff --git a/tasks.c b/tasks.c
index 01f972ba0..eee6a8c70 100644
--- a/tasks.c
+++ b/tasks.c
@@ -7577,12 +7577,14 @@ static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait,
             {
                 /* Wake time has overflowed.  Place this item in the overflow
                  * list. */
+                traceMOVED_TASK_TO_OVERFLOW_DELAYED_LIST();
                 vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
             }
             else
             {
                 /* The wake time has not overflowed, so the current block list
                  * is used. */
+                traceMOVED_TASK_TO_DELAYED_LIST();
                 vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
 
                 /* If the task entering the blocked state was placed at the
@@ -7611,11 +7613,13 @@ static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait,
 
         if( xTimeToWake < xConstTickCount )
         {
+            traceMOVED_TASK_TO_OVERFLOW_DELAYED_LIST();
             /* Wake time has overflowed.  Place this item in the overflow list. */
             vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
         }
         else
         {
+            traceMOVED_TASK_TO_DELAYED_LIST();
             /* The wake time has not overflowed, so the current block list is used. */
             vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
 

From 26c48dec4668ca3c3a7c66a7a9665f31e200153b Mon Sep 17 00:00:00 2001
From: kar-rahul-aws <118818625+kar-rahul-aws@users.noreply.github.com>
Date: Wed, 13 Sep 2023 11:22:17 +0530
Subject: [PATCH 055/424] Fix xStreamBufferCreateStatic() API for buffer size 1
 (#793)

---
 stream_buffer.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/stream_buffer.c b/stream_buffer.c
index 3a82ba31c..7c91ec316 100644
--- a/stream_buffer.c
+++ b/stream_buffer.c
@@ -417,10 +417,16 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
             xTriggerLevelBytes = ( size_t ) 1;
         }
 
+        /* In case the stream buffer is going to be used as a message buffer
+         * (that is, it will hold discrete messages with a little meta data that
+         * says how big the next message is) check the buffer will be large enough
+         * to hold at least one message. */
+
         if( xIsMessageBuffer != pdFALSE )
         {
             /* Statically allocated message buffer. */
             ucFlags = sbFLAGS_IS_MESSAGE_BUFFER | sbFLAGS_IS_STATICALLY_ALLOCATED;
+            configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH );
         }
         else
         {
@@ -428,12 +434,6 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
             ucFlags = sbFLAGS_IS_STATICALLY_ALLOCATED;
         }
 
-        /* In case the stream buffer is going to be used as a message buffer
-         * (that is, it will hold discrete messages with a little meta data that
-         * says how big the next message is) check the buffer will be large enough
-         * to hold at least one message. */
-        configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH );
-
         #if ( configASSERT_DEFINED == 1 )
         {
             /* Sanity check that the size of the structure used to declare a

From 7db0e87af1a9068056424636b96d520771d3473a Mon Sep 17 00:00:00 2001
From: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Date: Mon, 18 Sep 2023 10:53:03 +0800
Subject: [PATCH 056/424] Update taskYIELD_IF_USING_PREEMPTION macro (#769)

* Add taskYIELD_TASK_CORE_IF_USING_PREEMPTION and taskYIELD_ANY_CORE_IF_USING_PREEMPTION to align task yield behavior for single core and SMP.
---------

Co-authored-by: Soren Ptak <ptaksoren@gmail.com>
---
 tasks.c | 157 ++++++++++++++++++++++++--------------------------------
 1 file changed, 66 insertions(+), 91 deletions(-)

diff --git a/tasks.c b/tasks.c
index eee6a8c70..31e375479 100644
--- a/tasks.c
+++ b/tasks.c
@@ -58,16 +58,49 @@
     #include <stdio.h>
 #endif /* configUSE_STATS_FORMATTING_FUNCTIONS == 1 ) */
 
-#if ( configNUMBER_OF_CORES == 1 )
-    #if ( configUSE_PREEMPTION == 0 )
+#if ( configUSE_PREEMPTION == 0 )
 
 /* If the cooperative scheduler is being used then a yield should not be
  * performed just because a higher priority task has been woken. */
-        #define taskYIELD_IF_USING_PREEMPTION()
-    #else
-        #define taskYIELD_IF_USING_PREEMPTION()    portYIELD_WITHIN_API()
-    #endif
-#endif /* if ( configNUMBER_OF_CORES == 1 ) */
+    #define taskYIELD_TASK_CORE_IF_USING_PREEMPTION( pxTCB )
+    #define taskYIELD_ANY_CORE_IF_USING_PREEMPTION( pxTCB )
+#else
+
+    #if ( configNUMBER_OF_CORES == 1 )
+
+/* This macro requests the running task pxTCB to yield. In single core
+ * scheduler, a running task always runs on core 0 and portYIELD_WITHIN_API()
+ * can be used to request the task running on core 0 to yield. Therefore, pxTCB
+ * is not used in this macro. */
+        #define taskYIELD_TASK_CORE_IF_USING_PREEMPTION( pxTCB ) \
+    do {                                                         \
+        ( void ) ( pxTCB );                                      \
+        portYIELD_WITHIN_API();                                  \
+    } while( 0 )
+
+        #define taskYIELD_ANY_CORE_IF_USING_PREEMPTION( pxTCB ) \
+    do {                                                        \
+        if( pxCurrentTCB->uxPriority < ( pxTCB )->uxPriority )  \
+        {                                                       \
+            portYIELD_WITHIN_API();                             \
+        }                                                       \
+        else                                                    \
+        {                                                       \
+            mtCOVERAGE_TEST_MARKER();                           \
+        }                                                       \
+    } while( 0 )
+
+    #else /* if ( configNUMBER_OF_CORES == 1 ) */
+
+/* Yield the core on which this task is running. */
+        #define taskYIELD_TASK_CORE_IF_USING_PREEMPTION( pxTCB )    prvYieldCore( ( pxTCB )->xTaskRunState )
+
+/* Yield for the task if a running task has priority lower than this task. */
+        #define taskYIELD_ANY_CORE_IF_USING_PREEMPTION( pxTCB )     prvYieldForTask( pxTCB )
+
+    #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
+
+#endif /* if ( configUSE_PREEMPTION == 0 ) */
 
 /* Values that can be assigned to the ucNotifyState member of the TCB. */
 #define taskNOT_WAITING_NOTIFICATION              ( ( uint8_t ) 0 ) /* Must be zero as it is the initialised value. */
@@ -1776,14 +1809,7 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
         {
             /* If the created task is of a higher priority than the current task
              * then it should run now. */
-            if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority )
-            {
-                taskYIELD_IF_USING_PREEMPTION();
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
+            taskYIELD_ANY_CORE_IF_USING_PREEMPTION( pxNewTCB );
         }
         else
         {
@@ -1859,9 +1885,7 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
                 /* If the created task is of a higher priority than another
                  * currently running task and preemption is on then it should
                  * run now. */
-                #if ( configUSE_PREEMPTION == 1 )
-                    prvYieldForTask( pxNewTCB );
-                #endif
+                taskYIELD_ANY_CORE_IF_USING_PREEMPTION( pxNewTCB );
             }
             else
             {
@@ -2525,37 +2549,27 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
                     #endif
                 }
 
-                #if ( configNUMBER_OF_CORES == 1 )
+                if( xYieldRequired != pdFALSE )
                 {
-                    if( xYieldRequired != pdFALSE )
-                    {
-                        taskYIELD_IF_USING_PREEMPTION();
-                    }
-                    else
+                    /* The running task priority is set down. Request the task to yield. */
+                    taskYIELD_TASK_CORE_IF_USING_PREEMPTION( pxTCB );
+                }
+                else
+                {
+                    #if ( configNUMBER_OF_CORES > 1 )
+                        if( xYieldForTask != pdFALSE )
+                        {
+                            /* The priority of the task is being raised. If a running
+                             * task has priority lower than this task, it should yield
+                             * for this task. */
+                            taskYIELD_ANY_CORE_IF_USING_PREEMPTION( pxTCB );
+                        }
+                        else
+                    #endif /* if ( configNUMBER_OF_CORES > 1 ) */
                     {
                         mtCOVERAGE_TEST_MARKER();
                     }
                 }
-                #else /* #if ( configNUMBER_OF_CORES == 1 ) */
-                {
-                    #if ( configUSE_PREEMPTION == 1 )
-                    {
-                        if( xYieldRequired != pdFALSE )
-                        {
-                            prvYieldCore( pxTCB->xTaskRunState );
-                        }
-                        else if( xYieldForTask != pdFALSE )
-                        {
-                            prvYieldForTask( pxTCB );
-                        }
-                        else
-                        {
-                            mtCOVERAGE_TEST_MARKER();
-                        }
-                    }
-                    #endif /* #if ( configUSE_PREEMPTION == 1 ) */
-                }
-                #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
 
                 /* Remove compiler warning about unused variables when the port
                  * optimised task selection is not being used. */
@@ -2939,30 +2953,10 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
                     ( void ) uxListRemove( &( pxTCB->xStateListItem ) );
                     prvAddTaskToReadyList( pxTCB );
 
-                    #if ( configNUMBER_OF_CORES == 1 )
-                    {
-                        /* A higher priority task may have just been resumed. */
-                        if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
-                        {
-                            /* This yield may not cause the task just resumed to run,
-                             * but will leave the lists in the correct state for the
-                             * next yield. */
-                            taskYIELD_IF_USING_PREEMPTION();
-                        }
-                        else
-                        {
-                            mtCOVERAGE_TEST_MARKER();
-                        }
-                    }
-                    #else /* #if ( configNUMBER_OF_CORES == 1 ) */
-                    {
-                        #if ( configUSE_PREEMPTION == 1 )
-                        {
-                            prvYieldForTask( pxTCB );
-                        }
-                        #endif /* #if ( configUSE_PREEMPTION == 1 ) */
-                    }
-                    #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
+                    /* This yield may not cause the task just resumed to run,
+                     * but will leave the lists in the correct state for the
+                     * next yield. */
+                    taskYIELD_ANY_CORE_IF_USING_PREEMPTION( pxTCB );
                 }
                 else
                 {
@@ -3618,7 +3612,7 @@ BaseType_t xTaskResumeAll( void )
 
                         #if ( configNUMBER_OF_CORES == 1 )
                         {
-                            taskYIELD_IF_USING_PREEMPTION();
+                            taskYIELD_TASK_CORE_IF_USING_PREEMPTION( pxCurrentTCB );
                         }
                         #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
                     }
@@ -7063,28 +7057,9 @@ TickType_t uxTaskResetEventItemValue( void )
                 }
                 #endif
 
-                #if ( configNUMBER_OF_CORES == 1 )
-                {
-                    if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
-                    {
-                        /* The notified task has a priority above the currently
-                         * executing task so a yield is required. */
-                        taskYIELD_IF_USING_PREEMPTION();
-                    }
-                    else
-                    {
-                        mtCOVERAGE_TEST_MARKER();
-                    }
-                }
-                #else /* #if ( configNUMBER_OF_CORES == 1 ) */
-                {
-                    #if ( configUSE_PREEMPTION == 1 )
-                    {
-                        prvYieldForTask( pxTCB );
-                    }
-                    #endif
-                }
-                #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
+                /* Check if the notified task has a priority above the currently
+                 * executing task. */
+                taskYIELD_ANY_CORE_IF_USING_PREEMPTION( pxTCB );
             }
             else
             {

From 170a291d4d2ab5e7a223ac3fceb7ee38e76d3ffc Mon Sep 17 00:00:00 2001
From: kar-rahul-aws <118818625+kar-rahul-aws@users.noreply.github.com>
Date: Mon, 18 Sep 2023 15:34:42 +0530
Subject: [PATCH 057/424] Add Access Control List to MPU ports (#765)

This PR adds Access Control to kernel objects on a per task basis to MPU
ports. The following needs to be defined in the `FreeRTOSConfig.h` to
enable this feature:

```c
#define configUSE_MPU_WRAPPERS_V1 0
#define configENABLE_ACCESS_CONTROL_LIST 1
```

This PR adds the following new APIs:

```c
void vGrantAccessToTask( TaskHandle_t xTask,
                         TaskHandle_t xTaskToGrantAccess );
void vRevokeAccessToTask( TaskHandle_t xTask,
                          TaskHandle_t xTaskToRevokeAccess );

void vGrantAccessToSemaphore( TaskHandle_t xTask,
                              SemaphoreHandle_t xSemaphoreToGrantAccess );
void vRevokeAccessToSemaphore( TaskHandle_t xTask,
                               SemaphoreHandle_t xSemaphoreToRevokeAccess );

void vGrantAccessToQueue( TaskHandle_t xTask,
                          QueueHandle_t xQueueToGrantAccess );
void vRevokeAccessToQueue( TaskHandle_t xTask,
                           QueueHandle_t xQueueToRevokeAccess );

void vGrantAccessToQueueSet( TaskHandle_t xTask,
                             QueueSetHandle_t xQueueSetToGrantAccess );
void vRevokeAccessToQueueSet( TaskHandle_t xTask,
                              QueueSetHandle_t xQueueSetToRevokeAccess );

void vGrantAccessToEventGroup( TaskHandle_t xTask,
                               EventGroupHandle_t xEventGroupToGrantAccess );
void vRevokeAccessToEventGroup( TaskHandle_t xTask,
                                EventGroupHandle_t xEventGroupToRevokeAccess );

void vGrantAccessToStreamBuffer( TaskHandle_t xTask,
                                 StreamBufferHandle_t xStreamBufferToGrantAccess );
void vRevokeAccessToStreamBuffer( TaskHandle_t xTask,
                                  StreamBufferHandle_t xStreamBufferToRevokeAccess );

void vGrantAccessToMessageBuffer( TaskHandle_t xTask,
                                  MessageBufferHandle_t xMessageBufferToGrantAccess );
void vRevokeAccessToMessageBuffer( TaskHandle_t xTask,
                                   MessageBufferHandle_t xMessageBufferToRevokeAccess );

void vGrantAccessToTimer( TaskHandle_t xTask,
                          TimerHandle_t xTimerToGrantAccess );
void vRevokeAccessToTimer( TaskHandle_t xTask,
                           TimerHandle_t xTimerToRevokeAccess );
```

An unprivileged task by default has access to itself only and no other
kernel object. The application writer needs to explicitly grant an
unprivileged task access to all the kernel objects it needs. The best
place to do that is before starting the scheduler when all the kernel
objects are created.

For example, let's say an unprivileged tasks needs access to a queue and
an event group, the application writer needs to do the following:

```c
vGrantAccessToQueue( xUnprivilegedTaskHandle, xQueue );
vGrantAccessToEventGroup( xUnprivilegedTaskHandle, xEventGroup );
```

The application writer MUST revoke all the accesses before deleting a
task. Failing to do so will result in undefined behavior. In the above
example, the application writer needs to make the following 2 calls
before deleting the task:

```c
vRevokeAccessToQueue( xUnprivilegedTaskHandle, xQueue );
vRevokeAccessToEventGroup( xUnprivilegedTaskHandle, xEventGroup );

```
---
 include/FreeRTOS.h                            |   5 +
 include/mpu_wrappers.h                        |  29 +
 include/portable.h                            |  15 +
 include/task.h                                |  21 +
 portable/ARMv8M/non_secure/port.c             |  82 ++
 portable/ARMv8M/non_secure/portmacrocommon.h  |   7 +
 portable/Common/mpu_wrappers.c                |   4 +
 portable/Common/mpu_wrappers_v2.c             | 863 +++++++++++++-----
 portable/GCC/ARM_CM23/non_secure/port.c       |  82 ++
 .../GCC/ARM_CM23/non_secure/portmacrocommon.h |   7 +
 portable/GCC/ARM_CM23_NTZ/non_secure/port.c   |  82 ++
 .../ARM_CM23_NTZ/non_secure/portmacrocommon.h |   7 +
 portable/GCC/ARM_CM33/non_secure/port.c       |  82 ++
 .../GCC/ARM_CM33/non_secure/portmacrocommon.h |   7 +
 portable/GCC/ARM_CM33_NTZ/non_secure/port.c   |  82 ++
 .../ARM_CM33_NTZ/non_secure/portmacrocommon.h |   7 +
 portable/GCC/ARM_CM35P/non_secure/port.c      |  82 ++
 .../ARM_CM35P/non_secure/portmacrocommon.h    |   7 +
 portable/GCC/ARM_CM35P_NTZ/non_secure/port.c  |  82 ++
 .../non_secure/portmacrocommon.h              |   7 +
 portable/GCC/ARM_CM3_MPU/port.c               |  82 ++
 portable/GCC/ARM_CM3_MPU/portmacro.h          |   9 +-
 portable/GCC/ARM_CM4_MPU/port.c               |  82 ++
 portable/GCC/ARM_CM4_MPU/portmacro.h          |   9 +-
 portable/GCC/ARM_CM55/non_secure/port.c       |  82 ++
 .../GCC/ARM_CM55/non_secure/portmacrocommon.h |   7 +
 portable/GCC/ARM_CM55_NTZ/non_secure/port.c   |  82 ++
 .../ARM_CM55_NTZ/non_secure/portmacrocommon.h |   7 +
 portable/GCC/ARM_CM85/non_secure/port.c       |  82 ++
 .../GCC/ARM_CM85/non_secure/portmacrocommon.h |   7 +
 portable/GCC/ARM_CM85_NTZ/non_secure/port.c   |  82 ++
 .../ARM_CM85_NTZ/non_secure/portmacrocommon.h |   7 +
 portable/IAR/ARM_CM23/non_secure/port.c       |  82 ++
 .../IAR/ARM_CM23/non_secure/portmacrocommon.h |   7 +
 portable/IAR/ARM_CM23_NTZ/non_secure/port.c   |  82 ++
 .../ARM_CM23_NTZ/non_secure/portmacrocommon.h |   7 +
 portable/IAR/ARM_CM33/non_secure/port.c       |  82 ++
 .../IAR/ARM_CM33/non_secure/portmacrocommon.h |   7 +
 portable/IAR/ARM_CM33_NTZ/non_secure/port.c   |  82 ++
 .../ARM_CM33_NTZ/non_secure/portmacrocommon.h |   7 +
 portable/IAR/ARM_CM35P/non_secure/port.c      |  82 ++
 .../ARM_CM35P/non_secure/portmacrocommon.h    |   7 +
 portable/IAR/ARM_CM35P_NTZ/non_secure/port.c  |  82 ++
 .../non_secure/portmacrocommon.h              |   7 +
 portable/IAR/ARM_CM4F_MPU/port.c              |  82 ++
 portable/IAR/ARM_CM4F_MPU/portmacro.h         |   9 +-
 portable/IAR/ARM_CM55/non_secure/port.c       |  82 ++
 .../IAR/ARM_CM55/non_secure/portmacrocommon.h |   7 +
 portable/IAR/ARM_CM55_NTZ/non_secure/port.c   |  82 ++
 .../ARM_CM55_NTZ/non_secure/portmacrocommon.h |   7 +
 portable/IAR/ARM_CM85/non_secure/port.c       |  82 ++
 .../IAR/ARM_CM85/non_secure/portmacrocommon.h |   7 +
 portable/IAR/ARM_CM85_NTZ/non_secure/port.c   |  82 ++
 .../ARM_CM85_NTZ/non_secure/portmacrocommon.h |   7 +
 portable/RVDS/ARM_CM4_MPU/port.c              |  83 ++
 portable/RVDS/ARM_CM4_MPU/portmacro.h         |   9 +-
 56 files changed, 2952 insertions(+), 219 deletions(-)

diff --git a/include/FreeRTOS.h b/include/FreeRTOS.h
index a2b84185f..e11bc6302 100644
--- a/include/FreeRTOS.h
+++ b/include/FreeRTOS.h
@@ -86,6 +86,11 @@
     #define configUSE_MPU_WRAPPERS_V1    0
 #endif
 
+/* Set configENABLE_ACCESS_CONTROL_LIST to 1 to enable access control list support. */
+#ifndef configENABLE_ACCESS_CONTROL_LIST
+    #define configENABLE_ACCESS_CONTROL_LIST    0
+#endif
+
 /* Set default value of configNUMBER_OF_CORES to 1 to use single core FreeRTOS. */
 #ifndef configNUMBER_OF_CORES
     #define configNUMBER_OF_CORES    1
diff --git a/include/mpu_wrappers.h b/include/mpu_wrappers.h
index 9d1d867e2..162f57ff3 100644
--- a/include/mpu_wrappers.h
+++ b/include/mpu_wrappers.h
@@ -234,6 +234,35 @@
         #define PRIVILEGED_DATA    __attribute__( ( section( "privileged_data" ) ) )
         #define FREERTOS_SYSTEM_CALL
 
+
+        #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+            #define vGrantAccessToTask( xTask, xTaskToGrantAccess )                        vGrantAccessToKernelObject( ( xTask ), ( int32_t ) ( xTaskToGrantAccess ) )
+            #define vRevokeAccessToTask( xTask, xTaskToRevokeAccess )                      vRevokeAccessToKernelObject( ( xTask ), ( int32_t ) ( xTaskToRevokeAccess ) )
+
+            #define vGrantAccessToSemaphore( xTask, xSemaphoreToGrantAccess )              vGrantAccessToKernelObject( ( xTask ), ( int32_t ) ( xSemaphoreToGrantAccess ) )
+            #define vRevokeAccessToSemaphore( xTask, xSemaphoreToRevokeAccess )            vRevokeAccessToKernelObject( ( xTask ), ( int32_t ) ( xSemaphoreToRevokeAccess ) )
+
+            #define vGrantAccessToQueue( xTask, xQueueToGrantAccess )                      vGrantAccessToKernelObject( ( xTask ), ( int32_t ) ( xQueueToGrantAccess ) )
+            #define vRevokeAccessToQueue( xTask, xQueueToRevokeAccess )                    vRevokeAccessToKernelObject( ( xTask ), ( int32_t ) ( xQueueToRevokeAccess ) )
+
+            #define vGrantAccessToQueueSet( xTask, xQueueSetToGrantAccess )                vGrantAccessToKernelObject( ( xTask ), ( int32_t ) ( xQueueSetToGrantAccess ) )
+            #define vRevokeAccessToQueueSet( xTask, xQueueSetToRevokeAccess )              vRevokeAccessToKernelObject( ( xTask ), ( int32_t ) ( xQueueSetToRevokeAccess ) )
+
+            #define vGrantAccessToEventGroup( xTask, xEventGroupToGrantAccess )            vGrantAccessToKernelObject( ( xTask ), ( int32_t ) ( xEventGroupToGrantAccess ) )
+            #define vRevokeAccessToEventGroup( xTask, xEventGroupToRevokeAccess )          vRevokeAccessToKernelObject( ( xTask ), ( int32_t ) ( xEventGroupToRevokeAccess ) )
+
+            #define vGrantAccessToStreamBuffer( xTask, xStreamBufferToGrantAccess )        vGrantAccessToKernelObject( ( xTask ), ( int32_t ) ( xStreamBufferToGrantAccess ) )
+            #define vRevokeAccessToStreamBuffer( xTask, xStreamBufferToRevokeAccess )      vRevokeAccessToKernelObject( ( xTask ), ( int32_t ) ( xStreamBufferToRevokeAccess ) )
+
+            #define vGrantAccessToMessageBuffer( xTask, xMessageBufferToGrantAccess )      vGrantAccessToKernelObject( ( xTask ), ( int32_t ) ( xMessageBufferToGrantAccess ) )
+            #define vRevokeAccessToMessageBuffer( xTask, xMessageBufferToRevokeAccess )    vRevokeAccessToKernelObject( ( xTask ), ( int32_t ) ( xMessageBufferToRevokeAccess ) )
+
+            #define vGrantAccessToTimer( xTask, xTimerToGrantAccess )                      vGrantAccessToKernelObject( ( xTask ), ( int32_t ) ( xTimerToGrantAccess ) )
+            #define vRevokeAccessToTimer( xTask, xTimerToRevokeAccess )                    vRevokeAccessToKernelObject( ( xTask ), ( int32_t ) ( xTimerToRevokeAccess ) )
+
+        #endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+
     #else /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
 
 /* Ensure API functions go in the privileged execution section. */
diff --git a/include/portable.h b/include/portable.h
index 5734eb720..615d77d5a 100644
--- a/include/portable.h
+++ b/include/portable.h
@@ -247,6 +247,21 @@ void vPortEndScheduler( void ) PRIVILEGED_FUNCTION;
                                                 uint32_t ulAccessRequested ) PRIVILEGED_FUNCTION;
 #endif
 
+/**
+ * @brief Checks if the calling task is authorized to access the given kernel object.
+ *
+ * @param lInternalIndexOfKernelObject The index of the kernel object in the kernel
+ *                                     object handle pool.
+ *
+ * @return pdTRUE if the calling task is authorized to access the kernel object,
+ *         pdFALSE otherwise.
+ */
+#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+    BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) PRIVILEGED_FUNCTION;
+
+#endif
+
 /* *INDENT-OFF* */
 #ifdef __cplusplus
     }
diff --git a/include/task.h b/include/task.h
index 97809fc33..a1e1a7fbb 100644
--- a/include/task.h
+++ b/include/task.h
@@ -3469,6 +3469,27 @@ void vTaskExitCriticalFromISR( UBaseType_t uxSavedInterruptStatus );
 
 #endif /* portUSING_MPU_WRAPPERS */
 
+
+#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+/*
+ * For internal use only.  Grant/Revoke a task's access to a kernel object.
+ */
+    void vGrantAccessToKernelObject( TaskHandle_t xExternalTaskHandle,
+                                     int32_t lExternalKernelObjectHandle ) PRIVILEGED_FUNCTION;
+    void vRevokeAccessToKernelObject( TaskHandle_t xExternalTaskHandle,
+                                      int32_t lExternalKernelObjectHandle ) PRIVILEGED_FUNCTION;
+
+/*
+ * For internal use only.  Grant/Revoke a task's access to a kernel object.
+ */
+    void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+                                         int32_t lInternalIndexOfKernelObject ) PRIVILEGED_FUNCTION;
+    void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+                                          int32_t lInternalIndexOfKernelObject ) PRIVILEGED_FUNCTION;
+
+#endif /* #if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+
 /* *INDENT-OFF* */
 #ifdef __cplusplus
     }
diff --git a/portable/ARMv8M/non_secure/port.c b/portable/ARMv8M/non_secure/port.c
index c940c304b..e8ad8cf4c 100644
--- a/portable/ARMv8M/non_secure/port.c
+++ b/portable/ARMv8M/non_secure/port.c
@@ -2019,3 +2019,85 @@ BaseType_t xPortIsInsideInterrupt( void )
 
 #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+    void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+                                         int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+    {
+        uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+        xMPU_SETTINGS * xTaskMpuSettings;
+
+        ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+        ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+        xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+        xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit );
+    }
+
+#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+    void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+                                          int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+    {
+        uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+        xMPU_SETTINGS * xTaskMpuSettings;
+
+        ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+        ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+        xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+        xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit );
+    }
+
+#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+
+    #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+
+        BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+        {
+            uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+            BaseType_t xAccessGranted = pdFALSE;
+            const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+            ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+            ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+            if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+            {
+                xAccessGranted = pdTRUE;
+            }
+            else
+            {
+                if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                {
+                    xAccessGranted = pdTRUE;
+                }
+            }
+
+            return xAccessGranted;
+        }
+
+    #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+        BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+        {
+            ( void ) lInternalIndexOfKernelObject;
+
+            /* If Access Control List feature is not used, all the tasks have
+             * access to all the kernel objects. */
+            return pdTRUE;
+        }
+
+    #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/ARMv8M/non_secure/portmacrocommon.h b/portable/ARMv8M/non_secure/portmacrocommon.h
index 62e462a27..cc2adb7fd 100644
--- a/portable/ARMv8M/non_secure/portmacrocommon.h
+++ b/portable/ARMv8M/non_secure/portmacrocommon.h
@@ -287,6 +287,10 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
+/* Size of an Access Control List (ACL) entry in bits and bytes. */
+    #define portACL_ENTRY_SIZE_BYTES            ( 4U )
+    #define portACL_ENTRY_SIZE_BITS             ( 32U )
+
     typedef struct MPU_SETTINGS
     {
         uint32_t ulMAIR0;                                              /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
@@ -296,6 +300,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
         #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
             xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
+            #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BYTES ) + 1 ];
+            #endif
         #endif
     } xMPU_SETTINGS;
 
diff --git a/portable/Common/mpu_wrappers.c b/portable/Common/mpu_wrappers.c
index a0d7ee0aa..487f8aaf7 100644
--- a/portable/Common/mpu_wrappers.c
+++ b/portable/Common/mpu_wrappers.c
@@ -50,6 +50,10 @@
 
 #if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
 
+    #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+        #error Access control list is not available with this MPU wrapper. Please set configENABLE_ACCESS_CONTROL_LIST to 0.
+    #endif
+
     #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
         BaseType_t MPU_xTaskCreate( TaskFunction_t pvTaskCode,
                                     const char * const pcName,
diff --git a/portable/Common/mpu_wrappers_v2.c b/portable/Common/mpu_wrappers_v2.c
index 3f71af8a6..9db5772ad 100644
--- a/portable/Common/mpu_wrappers_v2.c
+++ b/portable/Common/mpu_wrappers_v2.c
@@ -320,6 +320,76 @@
     }
 /*-----------------------------------------------------------*/
 
+    #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+
+        void vGrantAccessToKernelObject( TaskHandle_t xExternalTaskHandle,
+                                         int32_t lExternalKernelObjectHandle ) /* PRIVILEGED_FUNCTION */
+        {
+            int32_t lExternalTaskIndex;
+            TaskHandle_t xInternalTaskHandle = NULL;
+
+            if( IS_EXTERNAL_INDEX_VALID( lExternalKernelObjectHandle ) != pdFALSE )
+            {
+                if( xExternalTaskHandle == NULL )
+                {
+                    vPortGrantAccessToKernelObject( xExternalTaskHandle, CONVERT_TO_INTERNAL_INDEX( lExternalKernelObjectHandle ) );
+                }
+                else
+                {
+                    lExternalTaskIndex = ( int32_t ) xExternalTaskHandle;
+
+                    if( IS_EXTERNAL_INDEX_VALID( lExternalTaskIndex ) != pdFALSE )
+                    {
+                        xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lExternalTaskIndex ) );
+
+                        if( xInternalTaskHandle != NULL )
+                        {
+                            vPortGrantAccessToKernelObject( xInternalTaskHandle,
+                                                            CONVERT_TO_INTERNAL_INDEX( lExternalKernelObjectHandle ) );
+                        }
+                    }
+                }
+            }
+        }
+
+    #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+
+        void vRevokeAccessToKernelObject( TaskHandle_t xExternalTaskHandle,
+                                          int32_t lExternalKernelObjectHandle ) /* PRIVILEGED_FUNCTION */
+        {
+            int32_t lExternalTaskIndex;
+            TaskHandle_t xInternalTaskHandle = NULL;
+
+            if( IS_EXTERNAL_INDEX_VALID( lExternalKernelObjectHandle ) != pdFALSE )
+            {
+                if( xExternalTaskHandle == NULL )
+                {
+                    vPortRevokeAccessToKernelObject( xExternalTaskHandle, CONVERT_TO_INTERNAL_INDEX( lExternalKernelObjectHandle ) );
+                }
+                else
+                {
+                    lExternalTaskIndex = ( int32_t ) xExternalTaskHandle;
+
+                    if( IS_EXTERNAL_INDEX_VALID( lExternalTaskIndex ) != pdFALSE )
+                    {
+                        xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lExternalTaskIndex ) );
+
+                        if( xInternalTaskHandle != NULL )
+                        {
+                            vPortRevokeAccessToKernelObject( xInternalTaskHandle,
+                                                             CONVERT_TO_INTERNAL_INDEX( lExternalKernelObjectHandle ) );
+                        }
+                    }
+                }
+            }
+        }
+
+    #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+/*-----------------------------------------------------------*/
+
     #if ( configUSE_TIMERS == 1 )
 
         static void MPU_TimerCallback( TimerHandle_t xInternalHandle ) /* PRIVILEGED_FUNCTION */
@@ -391,6 +461,7 @@
         BaseType_t MPU_xTaskAbortDelayImpl( TaskHandle_t xTask ) /* PRIVILEGED_FUNCTION */
         {
             BaseType_t xReturn = pdFAIL;
+            BaseType_t xCallingTaskIsAuthorizedToAccessTask = pdFALSE;
             TaskHandle_t xInternalTaskHandle = NULL;
             int32_t lIndex;
 
@@ -398,11 +469,16 @@
 
             if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
             {
-                xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                xCallingTaskIsAuthorizedToAccessTask = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-                if( xInternalTaskHandle != NULL )
+                if( xCallingTaskIsAuthorizedToAccessTask == pdTRUE )
                 {
-                    xReturn = xTaskAbortDelay( xInternalTaskHandle );
+                    xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                    if( xInternalTaskHandle != NULL )
+                    {
+                        xReturn = xTaskAbortDelay( xInternalTaskHandle );
+                    }
                 }
             }
 
@@ -431,6 +507,7 @@
         UBaseType_t MPU_uxTaskPriorityGetImpl( const TaskHandle_t pxTask ) /* PRIVILEGED_FUNCTION */
         {
             UBaseType_t uxReturn = configMAX_PRIORITIES;
+            BaseType_t xCallingTaskIsAuthorizedToAccessTask = pdFALSE;
             int32_t lIndex;
             TaskHandle_t xInternalTaskHandle = NULL;
 
@@ -444,11 +521,16 @@
 
                 if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
                 {
-                    xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                    xCallingTaskIsAuthorizedToAccessTask = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-                    if( xInternalTaskHandle != NULL )
+                    if( xCallingTaskIsAuthorizedToAccessTask == pdTRUE )
                     {
-                        uxReturn = uxTaskPriorityGet( xInternalTaskHandle );
+                        xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                        if( xInternalTaskHandle != NULL )
+                        {
+                            uxReturn = uxTaskPriorityGet( xInternalTaskHandle );
+                        }
                     }
                 }
             }
@@ -468,16 +550,22 @@
             eTaskState eReturn = eInvalid;
             TaskHandle_t xInternalTaskHandle = NULL;
             int32_t lIndex;
+            BaseType_t xCallingTaskIsAuthorizedToAccessTask = pdFALSE;
 
             lIndex = ( int32_t ) pxTask;
 
             if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
             {
-                xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                xCallingTaskIsAuthorizedToAccessTask = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-                if( xInternalTaskHandle != NULL )
+                if( xCallingTaskIsAuthorizedToAccessTask == pdTRUE )
                 {
-                    eReturn = eTaskGetState( xInternalTaskHandle );
+                    xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                    if( xInternalTaskHandle != NULL )
+                    {
+                        eReturn = eTaskGetState( xInternalTaskHandle );
+                    }
                 }
             }
 
@@ -502,6 +590,7 @@
             int32_t lIndex;
             TaskHandle_t xInternalTaskHandle = NULL;
             BaseType_t xIsTaskStatusWriteable = pdFALSE;
+            BaseType_t xCallingTaskIsAuthorizedToAccessTask = pdFALSE;
 
             xIsTaskStatusWriteable = xPortIsAuthorizedToAccessBuffer( pxTaskStatus,
                                                                       sizeof( TaskStatus_t ),
@@ -519,11 +608,16 @@
 
                     if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
                     {
-                        xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                        xCallingTaskIsAuthorizedToAccessTask = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-                        if( xInternalTaskHandle != NULL )
+                        if( xCallingTaskIsAuthorizedToAccessTask == pdTRUE )
                         {
-                            vTaskGetInfo( xInternalTaskHandle, pxTaskStatus, xGetFreeStackSpace, eState );
+                            xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                            if( xInternalTaskHandle != NULL )
+                            {
+                                vTaskGetInfo( xInternalTaskHandle, pxTaskStatus, xGetFreeStackSpace, eState );
+                            }
                         }
                     }
                 }
@@ -557,6 +651,7 @@
         {
             int32_t lIndex;
             TaskHandle_t xInternalTaskHandle = NULL;
+            BaseType_t xCallingTaskIsAuthorizedToAccessTask = pdFALSE;
 
             if( pxTaskToSuspend == NULL )
             {
@@ -576,11 +671,16 @@
 
                     if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
                     {
-                        xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                        xCallingTaskIsAuthorizedToAccessTask = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-                        if( xInternalTaskHandle != NULL )
+                        if( xCallingTaskIsAuthorizedToAccessTask == pdTRUE )
                         {
-                            vTaskSuspend( xInternalTaskHandle );
+                            xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                            if( xInternalTaskHandle != NULL )
+                            {
+                                vTaskSuspend( xInternalTaskHandle );
+                            }
                         }
                     }
                 }
@@ -598,16 +698,22 @@
         {
             int32_t lIndex;
             TaskHandle_t xInternalTaskHandle = NULL;
+            BaseType_t xCallingTaskIsAuthorizedToAccessTask = pdFALSE;
 
             lIndex = ( int32_t ) pxTaskToResume;
 
             if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
             {
-                xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                xCallingTaskIsAuthorizedToAccessTask = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-                if( xInternalTaskHandle != NULL )
+                if( xCallingTaskIsAuthorizedToAccessTask == pdTRUE )
                 {
-                    vTaskResume( xInternalTaskHandle );
+                    xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                    if( xInternalTaskHandle != NULL )
+                    {
+                        vTaskResume( xInternalTaskHandle );
+                    }
                 }
             }
         }
@@ -648,6 +754,7 @@
             configRUN_TIME_COUNTER_TYPE xReturn = 0;
             int32_t lIndex;
             TaskHandle_t xInternalTaskHandle = NULL;
+            BaseType_t xCallingTaskIsAuthorizedToAccessTask = pdFALSE;
 
             if( xTask == NULL )
             {
@@ -659,11 +766,16 @@
 
                 if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
                 {
-                    xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                    xCallingTaskIsAuthorizedToAccessTask = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-                    if( xInternalTaskHandle != NULL )
+                    if( xCallingTaskIsAuthorizedToAccessTask == pdTRUE )
                     {
-                        xReturn = ulTaskGetRunTimeCounter( xInternalTaskHandle );
+                        xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                        if( xInternalTaskHandle != NULL )
+                        {
+                            xReturn = ulTaskGetRunTimeCounter( xInternalTaskHandle );
+                        }
                     }
                 }
             }
@@ -683,6 +795,7 @@
             configRUN_TIME_COUNTER_TYPE xReturn = 0;
             int32_t lIndex;
             TaskHandle_t xInternalTaskHandle = NULL;
+            BaseType_t xCallingTaskIsAuthorizedToAccessTask = pdFALSE;
 
             if( xTask == NULL )
             {
@@ -694,11 +807,16 @@
 
                 if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
                 {
-                    xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                    xCallingTaskIsAuthorizedToAccessTask = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-                    if( xInternalTaskHandle != NULL )
+                    if( xCallingTaskIsAuthorizedToAccessTask == pdTRUE )
                     {
-                        xReturn = ulTaskGetRunTimePercent( xInternalTaskHandle );
+                        xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                        if( xInternalTaskHandle != NULL )
+                        {
+                            xReturn = ulTaskGetRunTimePercent( xInternalTaskHandle );
+                        }
                     }
                 }
             }
@@ -751,6 +869,7 @@
         {
             TaskHandle_t xInternalTaskHandle = NULL;
             int32_t lIndex;
+            BaseType_t xCallingTaskIsAuthorizedToAccessTask = pdFALSE;
 
             if( xTask == NULL )
             {
@@ -762,11 +881,16 @@
 
                 if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
                 {
-                    xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                    xCallingTaskIsAuthorizedToAccessTask = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-                    if( xInternalTaskHandle != NULL )
+                    if( xCallingTaskIsAuthorizedToAccessTask == pdTRUE )
                     {
-                        vTaskSetApplicationTaskTag( xInternalTaskHandle, pxTagValue );
+                        xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                        if( xInternalTaskHandle != NULL )
+                        {
+                            vTaskSetApplicationTaskTag( xInternalTaskHandle, pxTagValue );
+                        }
                     }
                 }
             }
@@ -784,6 +908,7 @@
             TaskHookFunction_t xReturn = NULL;
             int32_t lIndex;
             TaskHandle_t xInternalTaskHandle = NULL;
+            BaseType_t xCallingTaskIsAuthorizedToAccessTask = pdFALSE;
 
             if( xTask == NULL )
             {
@@ -795,11 +920,16 @@
 
                 if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
                 {
-                    xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                    xCallingTaskIsAuthorizedToAccessTask = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-                    if( xInternalTaskHandle != NULL )
+                    if( xCallingTaskIsAuthorizedToAccessTask == pdTRUE )
                     {
-                        xReturn = xTaskGetApplicationTaskTag( xInternalTaskHandle );
+                        xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                        if( xInternalTaskHandle != NULL )
+                        {
+                            xReturn = xTaskGetApplicationTaskTag( xInternalTaskHandle );
+                        }
                     }
                 }
             }
@@ -822,6 +952,7 @@
         {
             int32_t lIndex;
             TaskHandle_t xInternalTaskHandle = NULL;
+            BaseType_t xCallingTaskIsAuthorizedToAccessTask = pdFALSE;
 
             if( xTaskToSet == NULL )
             {
@@ -833,11 +964,16 @@
 
                 if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
                 {
-                    xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                    xCallingTaskIsAuthorizedToAccessTask = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-                    if( xInternalTaskHandle != NULL )
+                    if( xCallingTaskIsAuthorizedToAccessTask == pdTRUE )
                     {
-                        vTaskSetThreadLocalStoragePointer( xInternalTaskHandle, xIndex, pvValue );
+                        xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                        if( xInternalTaskHandle != NULL )
+                        {
+                            vTaskSetThreadLocalStoragePointer( xInternalTaskHandle, xIndex, pvValue );
+                        }
                     }
                 }
             }
@@ -857,6 +993,7 @@
             void * pvReturn = NULL;
             int32_t lIndex;
             TaskHandle_t xInternalTaskHandle = NULL;
+            BaseType_t xCallingTaskIsAuthorizedToAccessTask = pdFALSE;
 
             if( xTaskToQuery == NULL )
             {
@@ -868,11 +1005,16 @@
 
                 if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
                 {
-                    xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                    xCallingTaskIsAuthorizedToAccessTask = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-                    if( xInternalTaskHandle != NULL )
+                    if( xCallingTaskIsAuthorizedToAccessTask == pdTRUE )
                     {
-                        pvReturn = pvTaskGetThreadLocalStoragePointer( xInternalTaskHandle, xIndex );
+                        xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                        if( xInternalTaskHandle != NULL )
+                        {
+                            pvReturn = pvTaskGetThreadLocalStoragePointer( xInternalTaskHandle, xIndex );
+                        }
                     }
                 }
             }
@@ -929,6 +1071,7 @@
             UBaseType_t uxReturn = 0;
             int32_t lIndex;
             TaskHandle_t xInternalTaskHandle = NULL;
+            BaseType_t xCallingTaskIsAuthorizedToAccessTask = pdFALSE;
 
             if( xTask == NULL )
             {
@@ -940,11 +1083,16 @@
 
                 if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
                 {
-                    xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                    xCallingTaskIsAuthorizedToAccessTask = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-                    if( xInternalTaskHandle != NULL )
+                    if( xCallingTaskIsAuthorizedToAccessTask == pdTRUE )
                     {
-                        uxReturn = uxTaskGetStackHighWaterMark( xInternalTaskHandle );
+                        xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                        if( xInternalTaskHandle != NULL )
+                        {
+                            uxReturn = uxTaskGetStackHighWaterMark( xInternalTaskHandle );
+                        }
                     }
                 }
             }
@@ -964,6 +1112,7 @@
             configSTACK_DEPTH_TYPE uxReturn = 0;
             int32_t lIndex;
             TaskHandle_t xInternalTaskHandle = NULL;
+            BaseType_t xCallingTaskIsAuthorizedToAccessTask = pdFALSE;
 
             if( xTask == NULL )
             {
@@ -975,11 +1124,16 @@
 
                 if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
                 {
-                    xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                    xCallingTaskIsAuthorizedToAccessTask = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-                    if( xInternalTaskHandle != NULL )
+                    if( xCallingTaskIsAuthorizedToAccessTask == pdTRUE )
                     {
-                        uxReturn = uxTaskGetStackHighWaterMark2( xInternalTaskHandle );
+                        xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                        if( xInternalTaskHandle != NULL )
+                        {
+                            uxReturn = uxTaskGetStackHighWaterMark2( xInternalTaskHandle );
+                        }
                     }
                 }
             }
@@ -1101,6 +1255,7 @@
             int32_t lIndex;
             TaskHandle_t xInternalTaskHandle = NULL;
             BaseType_t xIsPreviousNotificationValueWriteable = pdFALSE;
+            BaseType_t xCallingTaskIsAuthorizedToAccessTask = pdFALSE;
 
             if( uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES )
             {
@@ -1117,11 +1272,16 @@
 
                     if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
                     {
-                        xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                        xCallingTaskIsAuthorizedToAccessTask = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-                        if( xInternalTaskHandle != NULL )
+                        if( xCallingTaskIsAuthorizedToAccessTask == pdTRUE )
                         {
-                            xReturn = xTaskGenericNotify( xInternalTaskHandle, uxIndexToNotify, ulValue, eAction, pulPreviousNotificationValue );
+                            xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                            if( xInternalTaskHandle != NULL )
+                            {
+                                xReturn = xTaskGenericNotify( xInternalTaskHandle, uxIndexToNotify, ulValue, eAction, pulPreviousNotificationValue );
+                            }
                         }
                     }
                 }
@@ -1205,6 +1365,7 @@
             BaseType_t xReturn = pdFAIL;
             int32_t lIndex;
             TaskHandle_t xInternalTaskHandle = NULL;
+            BaseType_t xCallingTaskIsAuthorizedToAccessTask = pdFALSE;
 
             if( uxIndexToClear < configTASK_NOTIFICATION_ARRAY_ENTRIES )
             {
@@ -1218,11 +1379,16 @@
 
                     if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
                     {
-                        xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                        xCallingTaskIsAuthorizedToAccessTask = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-                        if( xInternalTaskHandle != NULL )
+                        if( xCallingTaskIsAuthorizedToAccessTask == pdTRUE )
                         {
-                            xReturn = xTaskGenericNotifyStateClear( xInternalTaskHandle, uxIndexToClear );
+                            xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                            if( xInternalTaskHandle != NULL )
+                            {
+                                xReturn = xTaskGenericNotifyStateClear( xInternalTaskHandle, uxIndexToClear );
+                            }
                         }
                     }
                 }
@@ -1247,6 +1413,7 @@
             uint32_t ulReturn = 0;
             int32_t lIndex;
             TaskHandle_t xInternalTaskHandle = NULL;
+            BaseType_t xCallingTaskIsAuthorizedToAccessTask = pdFALSE;
 
             if( uxIndexToClear < configTASK_NOTIFICATION_ARRAY_ENTRIES )
             {
@@ -1260,11 +1427,16 @@
 
                     if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
                     {
-                        xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                        xCallingTaskIsAuthorizedToAccessTask = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-                        if( xInternalTaskHandle != NULL )
+                        if( xCallingTaskIsAuthorizedToAccessTask == pdTRUE )
                         {
-                            ulReturn = ulTaskGenericNotifyValueClear( xInternalTaskHandle, uxIndexToClear, ulBitsToClear );
+                            xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                            if( xInternalTaskHandle != NULL )
+                            {
+                                ulReturn = ulTaskGenericNotifyValueClear( xInternalTaskHandle, uxIndexToClear, ulBitsToClear );
+                            }
                         }
                     }
                 }
@@ -1348,6 +1520,17 @@
                 if( xInternalTaskHandle != NULL )
                 {
                     MPU_StoreTaskHandleAtIndex( lIndex, xInternalTaskHandle );
+
+                    #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+                    {
+                        /* By default, an unprivileged task has access to itself. */
+                        if( ( uxPriority & portPRIVILEGE_BIT ) == 0 )
+                        {
+                            vPortGrantAccessToKernelObject( xInternalTaskHandle, lIndex );
+                        }
+                    }
+                    #endif
+
                     xExternalTaskHandle = ( TaskHandle_t ) CONVERT_TO_EXTERNAL_INDEX( lIndex );
                 }
                 else
@@ -1513,6 +1696,16 @@
                 {
                     MPU_StoreTaskHandleAtIndex( lIndex, xInternalTaskHandle );
 
+                    #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+                    {
+                        /* By default, an unprivileged task has access to itself. */
+                        if( ( pxTaskDefinition->uxPriority & portPRIVILEGE_BIT ) == 0 )
+                        {
+                            vPortGrantAccessToKernelObject( xInternalTaskHandle, lIndex );
+                        }
+                    }
+                    #endif
+
                     if( pxCreatedTask != NULL )
                     {
                         *pxCreatedTask = ( TaskHandle_t ) CONVERT_TO_EXTERNAL_INDEX( lIndex );
@@ -1549,6 +1742,16 @@
                 {
                     MPU_StoreTaskHandleAtIndex( lIndex, xInternalTaskHandle );
 
+                    #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+                    {
+                        /* By default, an unprivileged task has access to itself. */
+                        if( ( pxTaskDefinition->uxPriority & portPRIVILEGE_BIT ) == 0 )
+                        {
+                            vPortGrantAccessToKernelObject( xInternalTaskHandle, lIndex );
+                        }
+                    }
+                    #endif
+
                     if( pxCreatedTask != NULL )
                     {
                         *pxCreatedTask = ( TaskHandle_t ) CONVERT_TO_EXTERNAL_INDEX( lIndex );
@@ -1823,36 +2026,42 @@
         QueueHandle_t xInternalQueueHandle = NULL;
         BaseType_t xReturn = pdFAIL;
         BaseType_t xIsItemToQueueReadable = pdFALSE;
+        BaseType_t xCallingTaskIsAuthorizedToAccessQueue = pdFALSE;
         UBaseType_t uxQueueItemSize, uxQueueLength;
 
         lIndex = ( int32_t ) xQueue;
 
         if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
         {
-            xInternalQueueHandle = MPU_GetQueueHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+            xCallingTaskIsAuthorizedToAccessQueue = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-            if( xInternalQueueHandle != NULL )
+            if( xCallingTaskIsAuthorizedToAccessQueue == pdTRUE )
             {
-                uxQueueItemSize = uxQueueGetQueueItemSize( xInternalQueueHandle );
-                uxQueueLength = uxQueueGetQueueLength( xInternalQueueHandle );
+                xInternalQueueHandle = MPU_GetQueueHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-                if( ( !( ( pvItemToQueue == NULL ) && ( uxQueueItemSize != ( UBaseType_t ) 0U ) ) ) &&
-                    ( !( ( xCopyPosition == queueOVERWRITE ) && ( uxQueueLength != ( UBaseType_t ) 1U ) ) )
-                    #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
-                        && ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) )
-                    #endif
-                    )
+                if( xInternalQueueHandle != NULL )
                 {
-                    if( pvItemToQueue != NULL )
-                    {
-                        xIsItemToQueueReadable = xPortIsAuthorizedToAccessBuffer( pvItemToQueue,
-                                                                                  uxQueueGetQueueItemSize( xInternalQueueHandle ),
-                                                                                  tskMPU_READ_PERMISSION );
-                    }
+                    uxQueueItemSize = uxQueueGetQueueItemSize( xInternalQueueHandle );
+                    uxQueueLength = uxQueueGetQueueLength( xInternalQueueHandle );
 
-                    if( ( pvItemToQueue == NULL ) || ( xIsItemToQueueReadable == pdTRUE ) )
+                    if( ( !( ( pvItemToQueue == NULL ) && ( uxQueueItemSize != ( UBaseType_t ) 0U ) ) ) &&
+                        ( !( ( xCopyPosition == queueOVERWRITE ) && ( uxQueueLength != ( UBaseType_t ) 1U ) ) )
+                        #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+                            && ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) )
+                        #endif
+                        )
                     {
-                        xReturn = xQueueGenericSend( xInternalQueueHandle, pvItemToQueue, xTicksToWait, xCopyPosition );
+                        if( pvItemToQueue != NULL )
+                        {
+                            xIsItemToQueueReadable = xPortIsAuthorizedToAccessBuffer( pvItemToQueue,
+                                                                                      uxQueueGetQueueItemSize( xInternalQueueHandle ),
+                                                                                      tskMPU_READ_PERMISSION );
+                        }
+
+                        if( ( pvItemToQueue == NULL ) || ( xIsItemToQueueReadable == pdTRUE ) )
+                        {
+                            xReturn = xQueueGenericSend( xInternalQueueHandle, pvItemToQueue, xTicksToWait, xCopyPosition );
+                        }
                     }
                 }
             }
@@ -1869,16 +2078,22 @@
         int32_t lIndex;
         QueueHandle_t xInternalQueueHandle = NULL;
         UBaseType_t uxReturn = 0;
+        BaseType_t xCallingTaskIsAuthorizedToAccessQueue = pdFALSE;
 
         lIndex = ( int32_t ) pxQueue;
 
         if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
         {
-            xInternalQueueHandle = MPU_GetQueueHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+            xCallingTaskIsAuthorizedToAccessQueue = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-            if( xInternalQueueHandle != NULL )
+            if( xCallingTaskIsAuthorizedToAccessQueue == pdTRUE )
             {
-                uxReturn = uxQueueMessagesWaiting( xInternalQueueHandle );
+                xInternalQueueHandle = MPU_GetQueueHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                if( xInternalQueueHandle != NULL )
+                {
+                    uxReturn = uxQueueMessagesWaiting( xInternalQueueHandle );
+                }
             }
         }
 
@@ -1893,16 +2108,22 @@
         int32_t lIndex;
         QueueHandle_t xInternalQueueHandle = NULL;
         UBaseType_t uxReturn = 0;
+        BaseType_t xCallingTaskIsAuthorizedToAccessQueue = pdFALSE;
 
         lIndex = ( int32_t ) xQueue;
 
         if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
         {
-            xInternalQueueHandle = MPU_GetQueueHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+            xCallingTaskIsAuthorizedToAccessQueue = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-            if( xInternalQueueHandle != NULL )
+            if( xCallingTaskIsAuthorizedToAccessQueue == pdTRUE )
             {
-                uxReturn = uxQueueSpacesAvailable( xInternalQueueHandle );
+                xInternalQueueHandle = MPU_GetQueueHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                if( xInternalQueueHandle != NULL )
+                {
+                    uxReturn = uxQueueSpacesAvailable( xInternalQueueHandle );
+                }
             }
         }
 
@@ -1922,31 +2143,37 @@
         QueueHandle_t xInternalQueueHandle = NULL;
         BaseType_t xReturn = pdFAIL;
         BaseType_t xIsReceiveBufferWritable = pdFALSE;
+        BaseType_t xCallingTaskIsAuthorizedToAccessQueue = pdFALSE;
         UBaseType_t uxQueueItemSize;
 
         lIndex = ( int32_t ) pxQueue;
 
         if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
         {
-            xInternalQueueHandle = MPU_GetQueueHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+            xCallingTaskIsAuthorizedToAccessQueue = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-            if( xInternalQueueHandle != NULL )
+            if( xCallingTaskIsAuthorizedToAccessQueue == pdTRUE )
             {
-                uxQueueItemSize = uxQueueGetQueueItemSize( xInternalQueueHandle );
+                xInternalQueueHandle = MPU_GetQueueHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-                if( ( !( ( ( pvBuffer ) == NULL ) && ( uxQueueItemSize != ( UBaseType_t ) 0U ) ) )
-                    #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
-                        && ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) )
-                    #endif
-                    )
+                if( xInternalQueueHandle != NULL )
                 {
-                    xIsReceiveBufferWritable = xPortIsAuthorizedToAccessBuffer( pvBuffer,
-                                                                                uxQueueGetQueueItemSize( xInternalQueueHandle ),
-                                                                                tskMPU_WRITE_PERMISSION );
+                    uxQueueItemSize = uxQueueGetQueueItemSize( xInternalQueueHandle );
 
-                    if( xIsReceiveBufferWritable == pdTRUE )
+                    if( ( !( ( ( pvBuffer ) == NULL ) && ( uxQueueItemSize != ( UBaseType_t ) 0U ) ) )
+                        #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+                            && ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) )
+                        #endif
+                        )
                     {
-                        xReturn = xQueueReceive( xInternalQueueHandle, pvBuffer, xTicksToWait );
+                        xIsReceiveBufferWritable = xPortIsAuthorizedToAccessBuffer( pvBuffer,
+                                                                                    uxQueueGetQueueItemSize( xInternalQueueHandle ),
+                                                                                    tskMPU_WRITE_PERMISSION );
+
+                        if( xIsReceiveBufferWritable == pdTRUE )
+                        {
+                            xReturn = xQueueReceive( xInternalQueueHandle, pvBuffer, xTicksToWait );
+                        }
                     }
                 }
             }
@@ -1969,30 +2196,36 @@
         BaseType_t xReturn = pdFAIL;
         BaseType_t xIsReceiveBufferWritable = pdFALSE;
         UBaseType_t uxQueueItemSize;
+        BaseType_t xCallingTaskIsAuthorizedToAccessQueue = pdFALSE;
 
         lIndex = ( int32_t ) xQueue;
 
         if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
         {
-            xInternalQueueHandle = MPU_GetQueueHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+            xCallingTaskIsAuthorizedToAccessQueue = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-            if( xInternalQueueHandle != NULL )
+            if( xCallingTaskIsAuthorizedToAccessQueue == pdTRUE )
             {
-                uxQueueItemSize = uxQueueGetQueueItemSize( xInternalQueueHandle );
+                xInternalQueueHandle = MPU_GetQueueHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-                if( ( !( ( ( pvBuffer ) == NULL ) && ( uxQueueItemSize != ( UBaseType_t ) 0U ) ) )
-                    #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
-                        && ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) )
-                    #endif
-                    )
+                if( xInternalQueueHandle != NULL )
                 {
-                    xIsReceiveBufferWritable = xPortIsAuthorizedToAccessBuffer( pvBuffer,
-                                                                                uxQueueGetQueueItemSize( xInternalQueueHandle ),
-                                                                                tskMPU_WRITE_PERMISSION );
+                    uxQueueItemSize = uxQueueGetQueueItemSize( xInternalQueueHandle );
 
-                    if( xIsReceiveBufferWritable == pdTRUE )
+                    if( ( !( ( ( pvBuffer ) == NULL ) && ( uxQueueItemSize != ( UBaseType_t ) 0U ) ) )
+                        #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+                            && ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) )
+                        #endif
+                        )
                     {
-                        xReturn = xQueuePeek( xInternalQueueHandle, pvBuffer, xTicksToWait );
+                        xIsReceiveBufferWritable = xPortIsAuthorizedToAccessBuffer( pvBuffer,
+                                                                                    uxQueueGetQueueItemSize( xInternalQueueHandle ),
+                                                                                    tskMPU_WRITE_PERMISSION );
+
+                        if( xIsReceiveBufferWritable == pdTRUE )
+                        {
+                            xReturn = xQueuePeek( xInternalQueueHandle, pvBuffer, xTicksToWait );
+                        }
                     }
                 }
             }
@@ -2012,24 +2245,30 @@
         QueueHandle_t xInternalQueueHandle = NULL;
         BaseType_t xReturn = pdFAIL;
         UBaseType_t uxQueueItemSize;
+        BaseType_t xCallingTaskIsAuthorizedToAccessQueue = pdFALSE;
 
         lIndex = ( int32_t ) xQueue;
 
         if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
         {
-            xInternalQueueHandle = MPU_GetQueueHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+            xCallingTaskIsAuthorizedToAccessQueue = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-            if( xInternalQueueHandle != NULL )
+            if( xCallingTaskIsAuthorizedToAccessQueue == pdTRUE )
             {
-                uxQueueItemSize = uxQueueGetQueueItemSize( xInternalQueueHandle );
+                xInternalQueueHandle = MPU_GetQueueHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-                if( ( uxQueueItemSize == 0 )
-                    #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
-                        && ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) )
-                    #endif
-                    )
+                if( xInternalQueueHandle != NULL )
                 {
-                    xReturn = xQueueSemaphoreTake( xInternalQueueHandle, xTicksToWait );
+                    uxQueueItemSize = uxQueueGetQueueItemSize( xInternalQueueHandle );
+
+                    if( ( uxQueueItemSize == 0 )
+                        #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+                            && ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) )
+                        #endif
+                        )
+                    {
+                        xReturn = xQueueSemaphoreTake( xInternalQueueHandle, xTicksToWait );
+                    }
                 }
             }
         }
@@ -2048,25 +2287,31 @@
             TaskHandle_t xMutexHolderTaskExternalHandle = NULL;
             int32_t lIndex, lMutexHolderTaskIndex;
             QueueHandle_t xInternalQueueHandle = NULL;
+            BaseType_t xCallingTaskIsAuthorizedToAccessQueue = pdFALSE;
 
 
             lIndex = ( int32_t ) xSemaphore;
 
             if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
             {
-                xInternalQueueHandle = MPU_GetQueueHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                xCallingTaskIsAuthorizedToAccessQueue = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-                if( xInternalQueueHandle != NULL )
+                if( xCallingTaskIsAuthorizedToAccessQueue == pdTRUE )
                 {
-                    xMutexHolderTaskInternalHandle = xQueueGetMutexHolder( xInternalQueueHandle );
+                    xInternalQueueHandle = MPU_GetQueueHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-                    if( xMutexHolderTaskInternalHandle != NULL )
+                    if( xInternalQueueHandle != NULL )
                     {
-                        lMutexHolderTaskIndex = MPU_GetIndexForTaskHandle( xMutexHolderTaskInternalHandle );
+                        xMutexHolderTaskInternalHandle = xQueueGetMutexHolder( xInternalQueueHandle );
 
-                        if( lMutexHolderTaskIndex != -1 )
+                        if( xMutexHolderTaskInternalHandle != NULL )
                         {
-                            xMutexHolderTaskExternalHandle = ( TaskHandle_t ) ( CONVERT_TO_EXTERNAL_INDEX( lMutexHolderTaskIndex ) );
+                            lMutexHolderTaskIndex = MPU_GetIndexForTaskHandle( xMutexHolderTaskInternalHandle );
+
+                            if( lMutexHolderTaskIndex != -1 )
+                            {
+                                xMutexHolderTaskExternalHandle = ( TaskHandle_t ) ( CONVERT_TO_EXTERNAL_INDEX( lMutexHolderTaskIndex ) );
+                            }
                         }
                     }
                 }
@@ -2087,6 +2332,7 @@
                                                      TickType_t xBlockTime ) /* PRIVILEGED_FUNCTION */
         {
             BaseType_t xReturn = pdFAIL;
+            BaseType_t xCallingTaskIsAuthorizedToAccessQueue = pdFALSE;
             int32_t lIndex;
             QueueHandle_t xInternalQueueHandle = NULL;
 
@@ -2094,11 +2340,16 @@
 
             if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
             {
-                xInternalQueueHandle = MPU_GetQueueHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                xCallingTaskIsAuthorizedToAccessQueue = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-                if( xInternalQueueHandle != NULL )
+                if( xCallingTaskIsAuthorizedToAccessQueue == pdTRUE )
                 {
-                    xReturn = xQueueTakeMutexRecursive( xInternalQueueHandle, xBlockTime );
+                    xInternalQueueHandle = MPU_GetQueueHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                    if( xInternalQueueHandle != NULL )
+                    {
+                        xReturn = xQueueTakeMutexRecursive( xInternalQueueHandle, xBlockTime );
+                    }
                 }
             }
 
@@ -2115,6 +2366,7 @@
         BaseType_t MPU_xQueueGiveMutexRecursiveImpl( QueueHandle_t xMutex ) /* PRIVILEGED_FUNCTION */
         {
             BaseType_t xReturn = pdFAIL;
+            BaseType_t xCallingTaskIsAuthorizedToAccessQueue = pdFALSE;
             int32_t lIndex;
             QueueHandle_t xInternalQueueHandle = NULL;
 
@@ -2122,11 +2374,16 @@
 
             if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
             {
-                xInternalQueueHandle = MPU_GetQueueHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                xCallingTaskIsAuthorizedToAccessQueue = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-                if( xInternalQueueHandle != NULL )
+                if( xCallingTaskIsAuthorizedToAccessQueue == pdTRUE )
                 {
-                    xReturn = xQueueGiveMutexRecursive( xInternalQueueHandle );
+                    xInternalQueueHandle = MPU_GetQueueHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                    if( xInternalQueueHandle != NULL )
+                    {
+                        xReturn = xQueueGiveMutexRecursive( xInternalQueueHandle );
+                    }
                 }
             }
 
@@ -2148,24 +2405,30 @@
             QueueSetMemberHandle_t xSelectedMemberInternal = NULL;
             QueueSetMemberHandle_t xSelectedMemberExternal = NULL;
             int32_t lIndexQueueSet, lIndexSelectedMember;
+            BaseType_t xCallingTaskIsAuthorizedToAccessQueueSet = pdFALSE;
 
             lIndexQueueSet = ( int32_t ) xQueueSet;
 
             if( IS_EXTERNAL_INDEX_VALID( lIndexQueueSet ) != pdFALSE )
             {
-                xInternalQueueSetHandle = MPU_GetQueueSetHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndexQueueSet ) );
+                xCallingTaskIsAuthorizedToAccessQueueSet = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndexQueueSet ) );
 
-                if( xInternalQueueSetHandle != NULL )
+                if( xCallingTaskIsAuthorizedToAccessQueueSet == pdTRUE )
                 {
-                    xSelectedMemberInternal = xQueueSelectFromSet( xInternalQueueSetHandle, xBlockTimeTicks );
+                    xInternalQueueSetHandle = MPU_GetQueueSetHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndexQueueSet ) );
 
-                    if( xSelectedMemberInternal != NULL )
+                    if( xInternalQueueSetHandle != NULL )
                     {
-                        lIndexSelectedMember = MPU_GetIndexForQueueSetMemberHandle( xSelectedMemberInternal );
+                        xSelectedMemberInternal = xQueueSelectFromSet( xInternalQueueSetHandle, xBlockTimeTicks );
 
-                        if( lIndexSelectedMember != -1 )
+                        if( xSelectedMemberInternal != NULL )
                         {
-                            xSelectedMemberExternal = ( QueueSetMemberHandle_t ) ( CONVERT_TO_EXTERNAL_INDEX( lIndexSelectedMember ) );
+                            lIndexSelectedMember = MPU_GetIndexForQueueSetMemberHandle( xSelectedMemberInternal );
+
+                            if( lIndexSelectedMember != -1 )
+                            {
+                                xSelectedMemberExternal = ( QueueSetMemberHandle_t ) ( CONVERT_TO_EXTERNAL_INDEX( lIndexSelectedMember ) );
+                            }
                         }
                     }
                 }
@@ -2189,6 +2452,8 @@
             QueueSetMemberHandle_t xInternalQueueSetMemberHandle = NULL;
             QueueSetHandle_t xInternalQueueSetHandle = NULL;
             int32_t lIndexQueueSet, lIndexQueueSetMember;
+            BaseType_t xCallingTaskIsAuthorizedToAccessQueueSet = pdFALSE;
+            BaseType_t xCallingTaskIsAuthorizedToAccessQueueSetMember = pdFALSE;
 
             lIndexQueueSet = ( int32_t ) xQueueSet;
             lIndexQueueSetMember = ( int32_t ) xQueueOrSemaphore;
@@ -2196,12 +2461,18 @@
             if( ( IS_EXTERNAL_INDEX_VALID( lIndexQueueSet ) != pdFALSE ) &&
                 ( IS_EXTERNAL_INDEX_VALID( lIndexQueueSetMember ) != pdFALSE ) )
             {
-                xInternalQueueSetHandle = MPU_GetQueueSetHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndexQueueSet ) );
-                xInternalQueueSetMemberHandle = MPU_GetQueueSetMemberHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndexQueueSetMember ) );
+                xCallingTaskIsAuthorizedToAccessQueueSet = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndexQueueSet ) );
+                xCallingTaskIsAuthorizedToAccessQueueSetMember = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndexQueueSetMember ) );
 
-                if( ( xInternalQueueSetHandle != NULL ) && ( xInternalQueueSetMemberHandle != NULL ) )
+                if( ( xCallingTaskIsAuthorizedToAccessQueueSet == pdTRUE ) && ( xCallingTaskIsAuthorizedToAccessQueueSetMember == pdTRUE ) )
                 {
-                    xReturn = xQueueAddToSet( xInternalQueueSetMemberHandle, xInternalQueueSetHandle );
+                    xInternalQueueSetHandle = MPU_GetQueueSetHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndexQueueSet ) );
+                    xInternalQueueSetMemberHandle = MPU_GetQueueSetMemberHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndexQueueSetMember ) );
+
+                    if( ( xInternalQueueSetHandle != NULL ) && ( xInternalQueueSetMemberHandle != NULL ) )
+                    {
+                        xReturn = xQueueAddToSet( xInternalQueueSetMemberHandle, xInternalQueueSetHandle );
+                    }
                 }
             }
 
@@ -2221,16 +2492,22 @@
         {
             int32_t lIndex;
             QueueHandle_t xInternalQueueHandle = NULL;
+            BaseType_t xCallingTaskIsAuthorizedToAccessQueue = pdFALSE;
 
             lIndex = ( int32_t ) xQueue;
 
             if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
             {
-                xInternalQueueHandle = MPU_GetQueueHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                xCallingTaskIsAuthorizedToAccessQueue = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-                if( xInternalQueueHandle != NULL )
+                if( xCallingTaskIsAuthorizedToAccessQueue == pdTRUE )
                 {
-                    vQueueAddToRegistry( xInternalQueueHandle, pcName );
+                    xInternalQueueHandle = MPU_GetQueueHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                    if( xInternalQueueHandle != NULL )
+                    {
+                        vQueueAddToRegistry( xInternalQueueHandle, pcName );
+                    }
                 }
             }
         }
@@ -2246,16 +2523,22 @@
         {
             int32_t lIndex;
             QueueHandle_t xInternalQueueHandle = NULL;
+            BaseType_t xCallingTaskIsAuthorizedToAccessQueue = pdFALSE;
 
             lIndex = ( int32_t ) xQueue;
 
             if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
             {
-                xInternalQueueHandle = MPU_GetQueueHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                xCallingTaskIsAuthorizedToAccessQueue = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-                if( xInternalQueueHandle != NULL )
+                if( xCallingTaskIsAuthorizedToAccessQueue == pdTRUE )
                 {
-                    vQueueUnregisterQueue( xInternalQueueHandle );
+                    xInternalQueueHandle = MPU_GetQueueHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                    if( xInternalQueueHandle != NULL )
+                    {
+                        vQueueUnregisterQueue( xInternalQueueHandle );
+                    }
                 }
             }
         }
@@ -2272,16 +2555,22 @@
             const char * pcReturn = NULL;
             QueueHandle_t xInternalQueueHandle = NULL;
             int32_t lIndex;
+            BaseType_t xCallingTaskIsAuthorizedToAccessQueue = pdFALSE;
 
             lIndex = ( int32_t ) xQueue;
 
             if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
             {
-                xInternalQueueHandle = MPU_GetQueueHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                xCallingTaskIsAuthorizedToAccessQueue = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-                if( xInternalQueueHandle != NULL )
+                if( xCallingTaskIsAuthorizedToAccessQueue == pdTRUE )
                 {
-                    pcReturn = pcQueueGetName( xInternalQueueHandle );
+                    xInternalQueueHandle = MPU_GetQueueHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                    if( xInternalQueueHandle != NULL )
+                    {
+                        pcReturn = pcQueueGetName( xInternalQueueHandle );
+                    }
                 }
             }
 
@@ -2879,16 +3168,22 @@
             void * pvReturn = NULL;
             TimerHandle_t xInternalTimerHandle = NULL;
             int32_t lIndex;
+            BaseType_t xCallingTaskIsAuthorizedToAccessTimer = pdFALSE;
 
             lIndex = ( int32_t ) xTimer;
 
             if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
             {
-                xInternalTimerHandle = MPU_GetTimerHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                xCallingTaskIsAuthorizedToAccessTimer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-                if( xInternalTimerHandle != NULL )
+                if( xCallingTaskIsAuthorizedToAccessTimer == pdTRUE )
                 {
-                    pvReturn = pvTimerGetTimerID( xInternalTimerHandle );
+                    xInternalTimerHandle = MPU_GetTimerHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                    if( xInternalTimerHandle != NULL )
+                    {
+                        pvReturn = pvTimerGetTimerID( xInternalTimerHandle );
+                    }
                 }
             }
 
@@ -2908,16 +3203,22 @@
         {
             TimerHandle_t xInternalTimerHandle = NULL;
             int32_t lIndex;
+            BaseType_t xCallingTaskIsAuthorizedToAccessTimer = pdFALSE;
 
             lIndex = ( int32_t ) xTimer;
 
             if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
             {
-                xInternalTimerHandle = MPU_GetTimerHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                xCallingTaskIsAuthorizedToAccessTimer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-                if( xInternalTimerHandle != NULL )
+                if( xCallingTaskIsAuthorizedToAccessTimer == pdTRUE )
                 {
-                    vTimerSetTimerID( xInternalTimerHandle, pvNewID );
+                    xInternalTimerHandle = MPU_GetTimerHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                    if( xInternalTimerHandle != NULL )
+                    {
+                        vTimerSetTimerID( xInternalTimerHandle, pvNewID );
+                    }
                 }
             }
         }
@@ -2934,16 +3235,22 @@
             BaseType_t xReturn = pdFALSE;
             TimerHandle_t xInternalTimerHandle = NULL;
             int32_t lIndex;
+            BaseType_t xCallingTaskIsAuthorizedToAccessTimer = pdFALSE;
 
             lIndex = ( int32_t ) xTimer;
 
             if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
             {
-                xInternalTimerHandle = MPU_GetTimerHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                xCallingTaskIsAuthorizedToAccessTimer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-                if( xInternalTimerHandle != NULL )
+                if( xCallingTaskIsAuthorizedToAccessTimer == pdTRUE )
                 {
-                    xReturn = xTimerIsTimerActive( xInternalTimerHandle );
+                    xInternalTimerHandle = MPU_GetTimerHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                    if( xInternalTimerHandle != NULL )
+                    {
+                        xReturn = xTimerIsTimerActive( xInternalTimerHandle );
+                    }
                 }
             }
 
@@ -2987,6 +3294,7 @@
             TimerHandle_t xInternalTimerHandle = NULL;
             int32_t lIndex;
             BaseType_t xIsHigherPriorityTaskWokenWriteable = pdFALSE;
+            BaseType_t xCallingTaskIsAuthorizedToAccessTimer = pdFALSE;
 
             if( xCommandID < tmrFIRST_FROM_ISR_COMMAND )
             {
@@ -3003,11 +3311,16 @@
 
                     if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
                     {
-                        xInternalTimerHandle = MPU_GetTimerHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                        xCallingTaskIsAuthorizedToAccessTimer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-                        if( xInternalTimerHandle != NULL )
+                        if( xCallingTaskIsAuthorizedToAccessTimer == pdTRUE )
                         {
-                            xReturn = xTimerGenericCommandFromTask( xInternalTimerHandle, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait );
+                            xInternalTimerHandle = MPU_GetTimerHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                            if( xInternalTimerHandle != NULL )
+                            {
+                                xReturn = xTimerGenericCommandFromTask( xInternalTimerHandle, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait );
+                            }
                         }
                     }
                 }
@@ -3028,16 +3341,22 @@
             const char * pcReturn = NULL;
             TimerHandle_t xInternalTimerHandle = NULL;
             int32_t lIndex;
+            BaseType_t xCallingTaskIsAuthorizedToAccessTimer = pdFALSE;
 
             lIndex = ( int32_t ) xTimer;
 
             if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
             {
-                xInternalTimerHandle = MPU_GetTimerHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                xCallingTaskIsAuthorizedToAccessTimer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-                if( xInternalTimerHandle != NULL )
+                if( xCallingTaskIsAuthorizedToAccessTimer == pdTRUE )
                 {
-                    pcReturn = pcTimerGetName( xInternalTimerHandle );
+                    xInternalTimerHandle = MPU_GetTimerHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                    if( xInternalTimerHandle != NULL )
+                    {
+                        pcReturn = pcTimerGetName( xInternalTimerHandle );
+                    }
                 }
             }
 
@@ -3057,16 +3376,22 @@
         {
             TimerHandle_t xInternalTimerHandle = NULL;
             int32_t lIndex;
+            BaseType_t xCallingTaskIsAuthorizedToAccessTimer = pdFALSE;
 
             lIndex = ( int32_t ) xTimer;
 
             if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
             {
-                xInternalTimerHandle = MPU_GetTimerHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                xCallingTaskIsAuthorizedToAccessTimer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-                if( xInternalTimerHandle != NULL )
+                if( xCallingTaskIsAuthorizedToAccessTimer == pdTRUE )
                 {
-                    vTimerSetReloadMode( xInternalTimerHandle, uxAutoReload );
+                    xInternalTimerHandle = MPU_GetTimerHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                    if( xInternalTimerHandle != NULL )
+                    {
+                        vTimerSetReloadMode( xInternalTimerHandle, uxAutoReload );
+                    }
                 }
             }
         }
@@ -3083,16 +3408,22 @@
             BaseType_t xReturn = pdFALSE;
             TimerHandle_t xInternalTimerHandle = NULL;
             int32_t lIndex;
+            BaseType_t xCallingTaskIsAuthorizedToAccessTimer = pdFALSE;
 
             lIndex = ( int32_t ) xTimer;
 
             if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
             {
-                xInternalTimerHandle = MPU_GetTimerHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                xCallingTaskIsAuthorizedToAccessTimer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-                if( xInternalTimerHandle != NULL )
+                if( xCallingTaskIsAuthorizedToAccessTimer == pdTRUE )
                 {
-                    xReturn = xTimerGetReloadMode( xInternalTimerHandle );
+                    xInternalTimerHandle = MPU_GetTimerHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                    if( xInternalTimerHandle != NULL )
+                    {
+                        xReturn = xTimerGetReloadMode( xInternalTimerHandle );
+                    }
                 }
             }
 
@@ -3111,16 +3442,22 @@
             UBaseType_t uxReturn = 0;
             TimerHandle_t xInternalTimerHandle = NULL;
             int32_t lIndex;
+            BaseType_t xCallingTaskIsAuthorizedToAccessTimer = pdFALSE;
 
             lIndex = ( int32_t ) xTimer;
 
             if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
             {
-                xInternalTimerHandle = MPU_GetTimerHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                xCallingTaskIsAuthorizedToAccessTimer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-                if( xInternalTimerHandle != NULL )
+                if( xCallingTaskIsAuthorizedToAccessTimer == pdTRUE )
                 {
-                    uxReturn = uxTimerGetReloadMode( xInternalTimerHandle );
+                    xInternalTimerHandle = MPU_GetTimerHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                    if( xInternalTimerHandle != NULL )
+                    {
+                        uxReturn = uxTimerGetReloadMode( xInternalTimerHandle );
+                    }
                 }
             }
 
@@ -3139,16 +3476,22 @@
             TickType_t xReturn = 0;
             TimerHandle_t xInternalTimerHandle = NULL;
             int32_t lIndex;
+            BaseType_t xCallingTaskIsAuthorizedToAccessTimer = pdFALSE;
 
             lIndex = ( int32_t ) xTimer;
 
             if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
             {
-                xInternalTimerHandle = MPU_GetTimerHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                xCallingTaskIsAuthorizedToAccessTimer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-                if( xInternalTimerHandle != NULL )
+                if( xCallingTaskIsAuthorizedToAccessTimer == pdTRUE )
                 {
-                    xReturn = xTimerGetPeriod( xInternalTimerHandle );
+                    xInternalTimerHandle = MPU_GetTimerHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                    if( xInternalTimerHandle != NULL )
+                    {
+                        xReturn = xTimerGetPeriod( xInternalTimerHandle );
+                    }
                 }
             }
 
@@ -3167,16 +3510,22 @@
             TickType_t xReturn = 0;
             TimerHandle_t xInternalTimerHandle = NULL;
             int32_t lIndex;
+            BaseType_t xCallingTaskIsAuthorizedToAccessTimer = pdFALSE;
 
             lIndex = ( int32_t ) xTimer;
 
             if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
             {
-                xInternalTimerHandle = MPU_GetTimerHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                xCallingTaskIsAuthorizedToAccessTimer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-                if( xInternalTimerHandle != NULL )
+                if( xCallingTaskIsAuthorizedToAccessTimer == pdTRUE )
                 {
-                    xReturn = xTimerGetExpiryTime( xInternalTimerHandle );
+                    xInternalTimerHandle = MPU_GetTimerHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                    if( xInternalTimerHandle != NULL )
+                    {
+                        xReturn = xTimerGetExpiryTime( xInternalTimerHandle );
+                    }
                 }
             }
 
@@ -3349,6 +3698,7 @@
         EventBits_t xReturn = 0;
         EventGroupHandle_t xInternalEventGroupHandle = NULL;
         int32_t lIndex;
+        BaseType_t xCallingTaskIsAuthorizedToAccessEventGroup = pdFALSE;
 
         if( ( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 ) &&
             ( uxBitsToWaitFor != 0 )
@@ -3361,11 +3711,16 @@
 
             if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
             {
-                xInternalEventGroupHandle = MPU_GetEventGroupHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                xCallingTaskIsAuthorizedToAccessEventGroup = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-                if( xInternalEventGroupHandle != NULL )
+                if( xCallingTaskIsAuthorizedToAccessEventGroup == pdTRUE )
                 {
-                    xReturn = xEventGroupWaitBits( xInternalEventGroupHandle, uxBitsToWaitFor, xClearOnExit, xWaitForAllBits, xTicksToWait );
+                    xInternalEventGroupHandle = MPU_GetEventGroupHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                    if( xInternalEventGroupHandle != NULL )
+                    {
+                        xReturn = xEventGroupWaitBits( xInternalEventGroupHandle, uxBitsToWaitFor, xClearOnExit, xWaitForAllBits, xTicksToWait );
+                    }
                 }
             }
         }
@@ -3383,6 +3738,7 @@
         EventBits_t xReturn = 0;
         EventGroupHandle_t xInternalEventGroupHandle = NULL;
         int32_t lIndex;
+        BaseType_t xCallingTaskIsAuthorizedToAccessEventGroup = pdFALSE;
 
         if( ( uxBitsToClear & eventEVENT_BITS_CONTROL_BYTES ) == 0 )
         {
@@ -3390,11 +3746,16 @@
 
             if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
             {
-                xInternalEventGroupHandle = MPU_GetEventGroupHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                xCallingTaskIsAuthorizedToAccessEventGroup = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-                if( xInternalEventGroupHandle != NULL )
+                if( xCallingTaskIsAuthorizedToAccessEventGroup == pdTRUE )
                 {
-                    xReturn = xEventGroupClearBits( xInternalEventGroupHandle, uxBitsToClear );
+                    xInternalEventGroupHandle = MPU_GetEventGroupHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                    if( xInternalEventGroupHandle != NULL )
+                    {
+                        xReturn = xEventGroupClearBits( xInternalEventGroupHandle, uxBitsToClear );
+                    }
                 }
             }
         }
@@ -3412,6 +3773,7 @@
         EventBits_t xReturn = 0;
         EventGroupHandle_t xInternalEventGroupHandle = NULL;
         int32_t lIndex;
+        BaseType_t xCallingTaskIsAuthorizedToAccessEventGroup = pdFALSE;
 
         if( ( uxBitsToSet & eventEVENT_BITS_CONTROL_BYTES ) == 0 )
         {
@@ -3419,11 +3781,16 @@
 
             if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
             {
-                xInternalEventGroupHandle = MPU_GetEventGroupHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                xCallingTaskIsAuthorizedToAccessEventGroup = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-                if( xInternalEventGroupHandle != NULL )
+                if( xCallingTaskIsAuthorizedToAccessEventGroup == pdTRUE )
                 {
-                    xReturn = xEventGroupSetBits( xInternalEventGroupHandle, uxBitsToSet );
+                    xInternalEventGroupHandle = MPU_GetEventGroupHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                    if( xInternalEventGroupHandle != NULL )
+                    {
+                        xReturn = xEventGroupSetBits( xInternalEventGroupHandle, uxBitsToSet );
+                    }
                 }
             }
         }
@@ -3445,6 +3812,7 @@
         EventBits_t xReturn = 0;
         EventGroupHandle_t xInternalEventGroupHandle = NULL;
         int32_t lIndex;
+        BaseType_t xCallingTaskIsAuthorizedToAccessEventGroup = pdFALSE;
 
         if( ( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 ) &&
             ( uxBitsToWaitFor != 0 )
@@ -3457,11 +3825,16 @@
 
             if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
             {
-                xInternalEventGroupHandle = MPU_GetEventGroupHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                xCallingTaskIsAuthorizedToAccessEventGroup = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-                if( xInternalEventGroupHandle != NULL )
+                if( xCallingTaskIsAuthorizedToAccessEventGroup == pdTRUE )
                 {
-                    xReturn = xEventGroupSync( xInternalEventGroupHandle, uxBitsToSet, uxBitsToWaitFor, xTicksToWait );
+                    xInternalEventGroupHandle = MPU_GetEventGroupHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                    if( xInternalEventGroupHandle != NULL )
+                    {
+                        xReturn = xEventGroupSync( xInternalEventGroupHandle, uxBitsToSet, uxBitsToWaitFor, xTicksToWait );
+                    }
                 }
             }
         }
@@ -3479,16 +3852,22 @@
             UBaseType_t xReturn = 0;
             EventGroupHandle_t xInternalEventGroupHandle = NULL;
             int32_t lIndex;
+            BaseType_t xCallingTaskIsAuthorizedToAccessEventGroup = pdFALSE;
 
             lIndex = ( int32_t ) xEventGroup;
 
             if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
             {
-                xInternalEventGroupHandle = MPU_GetEventGroupHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                xCallingTaskIsAuthorizedToAccessEventGroup = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-                if( xInternalEventGroupHandle != NULL )
+                if( xCallingTaskIsAuthorizedToAccessEventGroup == pdTRUE )
                 {
-                    xReturn = uxEventGroupGetNumber( xInternalEventGroupHandle );
+                    xInternalEventGroupHandle = MPU_GetEventGroupHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                    if( xInternalEventGroupHandle != NULL )
+                    {
+                        xReturn = uxEventGroupGetNumber( xInternalEventGroupHandle );
+                    }
                 }
             }
 
@@ -3508,16 +3887,22 @@
         {
             EventGroupHandle_t xInternalEventGroupHandle = NULL;
             int32_t lIndex;
+            BaseType_t xCallingTaskIsAuthorizedToAccessEventGroup = pdFALSE;
 
             lIndex = ( int32_t ) xEventGroup;
 
             if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
             {
-                xInternalEventGroupHandle = MPU_GetEventGroupHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                xCallingTaskIsAuthorizedToAccessEventGroup = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-                if( xInternalEventGroupHandle != NULL )
+                if( xCallingTaskIsAuthorizedToAccessEventGroup == pdTRUE )
                 {
-                    vEventGroupSetNumber( xInternalEventGroupHandle, uxEventGroupNumber );
+                    xInternalEventGroupHandle = MPU_GetEventGroupHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                    if( xInternalEventGroupHandle != NULL )
+                    {
+                        vEventGroupSetNumber( xInternalEventGroupHandle, uxEventGroupNumber );
+                    }
                 }
             }
         }
@@ -3734,6 +4119,7 @@
         StreamBufferHandle_t xInternalStreamBufferHandle = NULL;
         int32_t lIndex;
         BaseType_t xIsTxDataBufferReadable = pdFALSE;
+        BaseType_t xCallingTaskIsAuthorizedToAccessStreamBuffer = pdFALSE;
 
         if( pvTxData != NULL )
         {
@@ -3747,11 +4133,16 @@
 
                 if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
                 {
-                    xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                    xCallingTaskIsAuthorizedToAccessStreamBuffer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-                    if( xInternalStreamBufferHandle != NULL )
+                    if( xCallingTaskIsAuthorizedToAccessStreamBuffer == pdTRUE )
                     {
-                        xReturn = xStreamBufferSend( xInternalStreamBufferHandle, pvTxData, xDataLengthBytes, xTicksToWait );
+                        xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                        if( xInternalStreamBufferHandle != NULL )
+                        {
+                            xReturn = xStreamBufferSend( xInternalStreamBufferHandle, pvTxData, xDataLengthBytes, xTicksToWait );
+                        }
                     }
                 }
             }
@@ -3775,6 +4166,7 @@
         StreamBufferHandle_t xInternalStreamBufferHandle = NULL;
         int32_t lIndex;
         BaseType_t xIsRxDataBufferWriteable = pdFALSE;
+        BaseType_t xCallingTaskIsAuthorizedToAccessStreamBuffer = pdFALSE;
 
         if( pvRxData != NULL )
         {
@@ -3788,11 +4180,16 @@
 
                 if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
                 {
-                    xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                    xCallingTaskIsAuthorizedToAccessStreamBuffer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-                    if( xInternalStreamBufferHandle != NULL )
+                    if( xCallingTaskIsAuthorizedToAccessStreamBuffer == pdTRUE )
                     {
-                        xReturn = xStreamBufferReceive( xInternalStreamBufferHandle, pvRxData, xBufferLengthBytes, xTicksToWait );
+                        xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                        if( xInternalStreamBufferHandle != NULL )
+                        {
+                            xReturn = xStreamBufferReceive( xInternalStreamBufferHandle, pvRxData, xBufferLengthBytes, xTicksToWait );
+                        }
                     }
                 }
             }
@@ -3809,16 +4206,22 @@
         BaseType_t xReturn = pdFALSE;
         StreamBufferHandle_t xInternalStreamBufferHandle = NULL;
         int32_t lIndex;
+        BaseType_t xCallingTaskIsAuthorizedToAccessStreamBuffer = pdFALSE;
 
         lIndex = ( int32_t ) xStreamBuffer;
 
         if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
         {
-            xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+            xCallingTaskIsAuthorizedToAccessStreamBuffer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-            if( xInternalStreamBufferHandle != NULL )
+            if( xCallingTaskIsAuthorizedToAccessStreamBuffer == pdTRUE )
             {
-                xReturn = xStreamBufferIsFull( xInternalStreamBufferHandle );
+                xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                if( xInternalStreamBufferHandle != NULL )
+                {
+                    xReturn = xStreamBufferIsFull( xInternalStreamBufferHandle );
+                }
             }
         }
 
@@ -3833,16 +4236,22 @@
         BaseType_t xReturn = pdFALSE;
         StreamBufferHandle_t xInternalStreamBufferHandle = NULL;
         int32_t lIndex;
+        BaseType_t xCallingTaskIsAuthorizedToAccessStreamBuffer = pdFALSE;
 
         lIndex = ( int32_t ) xStreamBuffer;
 
         if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
         {
-            xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+            xCallingTaskIsAuthorizedToAccessStreamBuffer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-            if( xInternalStreamBufferHandle != NULL )
+            if( xCallingTaskIsAuthorizedToAccessStreamBuffer == pdTRUE )
             {
-                xReturn = xStreamBufferIsEmpty( xInternalStreamBufferHandle );
+                xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                if( xInternalStreamBufferHandle != NULL )
+                {
+                    xReturn = xStreamBufferIsEmpty( xInternalStreamBufferHandle );
+                }
             }
         }
 
@@ -3857,16 +4266,22 @@
         size_t xReturn = 0;
         StreamBufferHandle_t xInternalStreamBufferHandle = NULL;
         int32_t lIndex;
+        BaseType_t xCallingTaskIsAuthorizedToAccessStreamBuffer = pdFALSE;
 
         lIndex = ( int32_t ) xStreamBuffer;
 
         if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
         {
-            xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+            xCallingTaskIsAuthorizedToAccessStreamBuffer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-            if( xInternalStreamBufferHandle != NULL )
+            if( xCallingTaskIsAuthorizedToAccessStreamBuffer == pdTRUE )
             {
-                xReturn = xStreamBufferSpacesAvailable( xInternalStreamBufferHandle );
+                xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                if( xInternalStreamBufferHandle != NULL )
+                {
+                    xReturn = xStreamBufferSpacesAvailable( xInternalStreamBufferHandle );
+                }
             }
         }
 
@@ -3881,16 +4296,22 @@
         size_t xReturn = 0;
         StreamBufferHandle_t xInternalStreamBufferHandle = NULL;
         int32_t lIndex;
+        BaseType_t xCallingTaskIsAuthorizedToAccessStreamBuffer = pdFALSE;
 
         lIndex = ( int32_t ) xStreamBuffer;
 
         if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
         {
-            xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+            xCallingTaskIsAuthorizedToAccessStreamBuffer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-            if( xInternalStreamBufferHandle != NULL )
+            if( xCallingTaskIsAuthorizedToAccessStreamBuffer == pdTRUE )
             {
-                xReturn = xStreamBufferBytesAvailable( xInternalStreamBufferHandle );
+                xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                if( xInternalStreamBufferHandle != NULL )
+                {
+                    xReturn = xStreamBufferBytesAvailable( xInternalStreamBufferHandle );
+                }
             }
         }
 
@@ -3907,16 +4328,22 @@
         BaseType_t xReturn = pdFALSE;
         StreamBufferHandle_t xInternalStreamBufferHandle = NULL;
         int32_t lIndex;
+        BaseType_t xCallingTaskIsAuthorizedToAccessStreamBuffer = pdFALSE;
 
         lIndex = ( int32_t ) xStreamBuffer;
 
         if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
         {
-            xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+            xCallingTaskIsAuthorizedToAccessStreamBuffer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-            if( xInternalStreamBufferHandle != NULL )
+            if( xCallingTaskIsAuthorizedToAccessStreamBuffer == pdTRUE )
             {
-                xReturn = xStreamBufferSetTriggerLevel( xInternalStreamBufferHandle, xTriggerLevel );
+                xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                if( xInternalStreamBufferHandle != NULL )
+                {
+                    xReturn = xStreamBufferSetTriggerLevel( xInternalStreamBufferHandle, xTriggerLevel );
+                }
             }
         }
 
@@ -3931,16 +4358,22 @@
         size_t xReturn = 0;
         StreamBufferHandle_t xInternalStreamBufferHandle = NULL;
         int32_t lIndex;
+        BaseType_t xCallingTaskIsAuthorizedToAccessStreamBuffer = pdFALSE;
 
         lIndex = ( int32_t ) xStreamBuffer;
 
         if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
         {
-            xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+            xCallingTaskIsAuthorizedToAccessStreamBuffer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-            if( xInternalStreamBufferHandle != NULL )
+            if( xCallingTaskIsAuthorizedToAccessStreamBuffer == pdTRUE )
             {
-                xReturn = xStreamBufferNextMessageLengthBytes( xInternalStreamBufferHandle );
+                xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                if( xInternalStreamBufferHandle != NULL )
+                {
+                    xReturn = xStreamBufferNextMessageLengthBytes( xInternalStreamBufferHandle );
+                }
             }
         }
 
diff --git a/portable/GCC/ARM_CM23/non_secure/port.c b/portable/GCC/ARM_CM23/non_secure/port.c
index c940c304b..e8ad8cf4c 100644
--- a/portable/GCC/ARM_CM23/non_secure/port.c
+++ b/portable/GCC/ARM_CM23/non_secure/port.c
@@ -2019,3 +2019,85 @@ BaseType_t xPortIsInsideInterrupt( void )
 
 #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+    void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+                                         int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+    {
+        uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+        xMPU_SETTINGS * xTaskMpuSettings;
+
+        ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+        ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+        xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+        xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit );
+    }
+
+#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+    void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+                                          int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+    {
+        uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+        xMPU_SETTINGS * xTaskMpuSettings;
+
+        ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+        ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+        xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+        xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit );
+    }
+
+#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+
+    #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+
+        BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+        {
+            uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+            BaseType_t xAccessGranted = pdFALSE;
+            const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+            ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+            ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+            if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+            {
+                xAccessGranted = pdTRUE;
+            }
+            else
+            {
+                if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                {
+                    xAccessGranted = pdTRUE;
+                }
+            }
+
+            return xAccessGranted;
+        }
+
+    #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+        BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+        {
+            ( void ) lInternalIndexOfKernelObject;
+
+            /* If Access Control List feature is not used, all the tasks have
+             * access to all the kernel objects. */
+            return pdTRUE;
+        }
+
+    #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h
index 62e462a27..cc2adb7fd 100644
--- a/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h
@@ -287,6 +287,10 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
+/* Size of an Access Control List (ACL) entry in bits and bytes. */
+    #define portACL_ENTRY_SIZE_BYTES            ( 4U )
+    #define portACL_ENTRY_SIZE_BITS             ( 32U )
+
     typedef struct MPU_SETTINGS
     {
         uint32_t ulMAIR0;                                              /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
@@ -296,6 +300,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
         #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
             xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
+            #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BYTES ) + 1 ];
+            #endif
         #endif
     } xMPU_SETTINGS;
 
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
index c940c304b..e8ad8cf4c 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
@@ -2019,3 +2019,85 @@ BaseType_t xPortIsInsideInterrupt( void )
 
 #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+    void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+                                         int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+    {
+        uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+        xMPU_SETTINGS * xTaskMpuSettings;
+
+        ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+        ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+        xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+        xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit );
+    }
+
+#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+    void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+                                          int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+    {
+        uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+        xMPU_SETTINGS * xTaskMpuSettings;
+
+        ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+        ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+        xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+        xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit );
+    }
+
+#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+
+    #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+
+        BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+        {
+            uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+            BaseType_t xAccessGranted = pdFALSE;
+            const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+            ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+            ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+            if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+            {
+                xAccessGranted = pdTRUE;
+            }
+            else
+            {
+                if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                {
+                    xAccessGranted = pdTRUE;
+                }
+            }
+
+            return xAccessGranted;
+        }
+
+    #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+        BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+        {
+            ( void ) lInternalIndexOfKernelObject;
+
+            /* If Access Control List feature is not used, all the tasks have
+             * access to all the kernel objects. */
+            return pdTRUE;
+        }
+
+    #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h
index 62e462a27..cc2adb7fd 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h
@@ -287,6 +287,10 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
+/* Size of an Access Control List (ACL) entry in bits and bytes. */
+    #define portACL_ENTRY_SIZE_BYTES            ( 4U )
+    #define portACL_ENTRY_SIZE_BITS             ( 32U )
+
     typedef struct MPU_SETTINGS
     {
         uint32_t ulMAIR0;                                              /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
@@ -296,6 +300,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
         #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
             xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
+            #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BYTES ) + 1 ];
+            #endif
         #endif
     } xMPU_SETTINGS;
 
diff --git a/portable/GCC/ARM_CM33/non_secure/port.c b/portable/GCC/ARM_CM33/non_secure/port.c
index c940c304b..e8ad8cf4c 100644
--- a/portable/GCC/ARM_CM33/non_secure/port.c
+++ b/portable/GCC/ARM_CM33/non_secure/port.c
@@ -2019,3 +2019,85 @@ BaseType_t xPortIsInsideInterrupt( void )
 
 #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+    void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+                                         int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+    {
+        uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+        xMPU_SETTINGS * xTaskMpuSettings;
+
+        ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+        ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+        xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+        xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit );
+    }
+
+#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+    void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+                                          int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+    {
+        uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+        xMPU_SETTINGS * xTaskMpuSettings;
+
+        ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+        ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+        xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+        xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit );
+    }
+
+#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+
+    #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+
+        BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+        {
+            uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+            BaseType_t xAccessGranted = pdFALSE;
+            const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+            ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+            ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+            if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+            {
+                xAccessGranted = pdTRUE;
+            }
+            else
+            {
+                if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                {
+                    xAccessGranted = pdTRUE;
+                }
+            }
+
+            return xAccessGranted;
+        }
+
+    #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+        BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+        {
+            ( void ) lInternalIndexOfKernelObject;
+
+            /* If Access Control List feature is not used, all the tasks have
+             * access to all the kernel objects. */
+            return pdTRUE;
+        }
+
+    #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h
index 62e462a27..cc2adb7fd 100644
--- a/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h
@@ -287,6 +287,10 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
+/* Size of an Access Control List (ACL) entry in bits and bytes. */
+    #define portACL_ENTRY_SIZE_BYTES            ( 4U )
+    #define portACL_ENTRY_SIZE_BITS             ( 32U )
+
     typedef struct MPU_SETTINGS
     {
         uint32_t ulMAIR0;                                              /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
@@ -296,6 +300,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
         #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
             xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
+            #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BYTES ) + 1 ];
+            #endif
         #endif
     } xMPU_SETTINGS;
 
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
index c940c304b..e8ad8cf4c 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
@@ -2019,3 +2019,85 @@ BaseType_t xPortIsInsideInterrupt( void )
 
 #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+    void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+                                         int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+    {
+        uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+        xMPU_SETTINGS * xTaskMpuSettings;
+
+        ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+        ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+        xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+        xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit );
+    }
+
+#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+    void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+                                          int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+    {
+        uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+        xMPU_SETTINGS * xTaskMpuSettings;
+
+        ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+        ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+        xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+        xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit );
+    }
+
+#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+
+    #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+
+        BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+        {
+            uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+            BaseType_t xAccessGranted = pdFALSE;
+            const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+            ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+            ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+            if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+            {
+                xAccessGranted = pdTRUE;
+            }
+            else
+            {
+                if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                {
+                    xAccessGranted = pdTRUE;
+                }
+            }
+
+            return xAccessGranted;
+        }
+
+    #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+        BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+        {
+            ( void ) lInternalIndexOfKernelObject;
+
+            /* If Access Control List feature is not used, all the tasks have
+             * access to all the kernel objects. */
+            return pdTRUE;
+        }
+
+    #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h
index 62e462a27..cc2adb7fd 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h
@@ -287,6 +287,10 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
+/* Size of an Access Control List (ACL) entry in bits and bytes. */
+    #define portACL_ENTRY_SIZE_BYTES            ( 4U )
+    #define portACL_ENTRY_SIZE_BITS             ( 32U )
+
     typedef struct MPU_SETTINGS
     {
         uint32_t ulMAIR0;                                              /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
@@ -296,6 +300,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
         #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
             xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
+            #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BYTES ) + 1 ];
+            #endif
         #endif
     } xMPU_SETTINGS;
 
diff --git a/portable/GCC/ARM_CM35P/non_secure/port.c b/portable/GCC/ARM_CM35P/non_secure/port.c
index c940c304b..e8ad8cf4c 100644
--- a/portable/GCC/ARM_CM35P/non_secure/port.c
+++ b/portable/GCC/ARM_CM35P/non_secure/port.c
@@ -2019,3 +2019,85 @@ BaseType_t xPortIsInsideInterrupt( void )
 
 #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+    void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+                                         int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+    {
+        uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+        xMPU_SETTINGS * xTaskMpuSettings;
+
+        ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+        ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+        xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+        xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit );
+    }
+
+#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+    void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+                                          int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+    {
+        uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+        xMPU_SETTINGS * xTaskMpuSettings;
+
+        ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+        ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+        xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+        xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit );
+    }
+
+#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+
+    #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+
+        BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+        {
+            uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+            BaseType_t xAccessGranted = pdFALSE;
+            const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+            ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+            ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+            if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+            {
+                xAccessGranted = pdTRUE;
+            }
+            else
+            {
+                if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                {
+                    xAccessGranted = pdTRUE;
+                }
+            }
+
+            return xAccessGranted;
+        }
+
+    #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+        BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+        {
+            ( void ) lInternalIndexOfKernelObject;
+
+            /* If Access Control List feature is not used, all the tasks have
+             * access to all the kernel objects. */
+            return pdTRUE;
+        }
+
+    #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h
index 62e462a27..cc2adb7fd 100644
--- a/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h
@@ -287,6 +287,10 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
+/* Size of an Access Control List (ACL) entry in bits and bytes. */
+    #define portACL_ENTRY_SIZE_BYTES            ( 4U )
+    #define portACL_ENTRY_SIZE_BITS             ( 32U )
+
     typedef struct MPU_SETTINGS
     {
         uint32_t ulMAIR0;                                              /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
@@ -296,6 +300,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
         #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
             xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
+            #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BYTES ) + 1 ];
+            #endif
         #endif
     } xMPU_SETTINGS;
 
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c b/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
index c940c304b..e8ad8cf4c 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
@@ -2019,3 +2019,85 @@ BaseType_t xPortIsInsideInterrupt( void )
 
 #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+    void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+                                         int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+    {
+        uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+        xMPU_SETTINGS * xTaskMpuSettings;
+
+        ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+        ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+        xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+        xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit );
+    }
+
+#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+    void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+                                          int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+    {
+        uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+        xMPU_SETTINGS * xTaskMpuSettings;
+
+        ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+        ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+        xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+        xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit );
+    }
+
+#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+
+    #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+
+        BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+        {
+            uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+            BaseType_t xAccessGranted = pdFALSE;
+            const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+            ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+            ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+            if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+            {
+                xAccessGranted = pdTRUE;
+            }
+            else
+            {
+                if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                {
+                    xAccessGranted = pdTRUE;
+                }
+            }
+
+            return xAccessGranted;
+        }
+
+    #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+        BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+        {
+            ( void ) lInternalIndexOfKernelObject;
+
+            /* If Access Control List feature is not used, all the tasks have
+             * access to all the kernel objects. */
+            return pdTRUE;
+        }
+
+    #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
index 62e462a27..cc2adb7fd 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
@@ -287,6 +287,10 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
+/* Size of an Access Control List (ACL) entry in bits and bytes. */
+    #define portACL_ENTRY_SIZE_BYTES            ( 4U )
+    #define portACL_ENTRY_SIZE_BITS             ( 32U )
+
     typedef struct MPU_SETTINGS
     {
         uint32_t ulMAIR0;                                              /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
@@ -296,6 +300,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
         #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
             xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
+            #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BYTES ) + 1 ];
+            #endif
         #endif
     } xMPU_SETTINGS;
 
diff --git a/portable/GCC/ARM_CM3_MPU/port.c b/portable/GCC/ARM_CM3_MPU/port.c
index 2fcd22e9b..a524f2b2a 100644
--- a/portable/GCC/ARM_CM3_MPU/port.c
+++ b/portable/GCC/ARM_CM3_MPU/port.c
@@ -1423,3 +1423,85 @@ BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
 
 #endif /* configASSERT_DEFINED */
 /*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+    void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+                                         int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+    {
+        uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+        xMPU_SETTINGS * xTaskMpuSettings;
+
+        ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+        ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+        xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+        xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit );
+    }
+
+#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+    void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+                                          int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+    {
+        uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+        xMPU_SETTINGS * xTaskMpuSettings;
+
+        ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+        ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+        xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+        xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit );
+    }
+
+#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+
+    #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+
+        BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+        {
+            uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+            BaseType_t xAccessGranted = pdFALSE;
+            const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+            ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+            ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+            if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+            {
+                xAccessGranted = pdTRUE;
+            }
+            else
+            {
+                if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                {
+                    xAccessGranted = pdTRUE;
+                }
+            }
+
+            return xAccessGranted;
+        }
+
+    #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+        BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+        {
+            ( void ) lInternalIndexOfKernelObject;
+
+            /* If Access Control List feature is not used, all the tasks have
+             * access to all the kernel objects. */
+            return pdTRUE;
+        }
+
+    #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM3_MPU/portmacro.h b/portable/GCC/ARM_CM3_MPU/portmacro.h
index 31a4812ea..c844a8e6f 100644
--- a/portable/GCC/ARM_CM3_MPU/portmacro.h
+++ b/portable/GCC/ARM_CM3_MPU/portmacro.h
@@ -127,7 +127,11 @@ typedef struct MPU_REGION_SETTINGS
 
 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
-#define MAX_CONTEXT_SIZE                    20
+#define MAX_CONTEXT_SIZE                    ( 20 )
+
+/* Size of an Access Control List (ACL) entry in bits and bytes. */
+#define portACL_ENTRY_SIZE_BYTES            ( 4U )
+#define portACL_ENTRY_SIZE_BITS             ( 32U )
 
 /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
 #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
@@ -142,6 +146,9 @@ typedef struct MPU_SETTINGS
 
     #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
         xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
+        #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+            uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BYTES ) + 1 ];
+        #endif
     #endif
 } xMPU_SETTINGS;
 
diff --git a/portable/GCC/ARM_CM4_MPU/port.c b/portable/GCC/ARM_CM4_MPU/port.c
index 886be7018..a59a651f4 100644
--- a/portable/GCC/ARM_CM4_MPU/port.c
+++ b/portable/GCC/ARM_CM4_MPU/port.c
@@ -1617,3 +1617,85 @@ BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
 
 #endif /* configASSERT_DEFINED */
 /*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+    void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+                                         int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+    {
+        uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+        xMPU_SETTINGS * xTaskMpuSettings;
+
+        ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+        ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+        xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+        xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit );
+    }
+
+#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+    void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+                                          int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+    {
+        uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+        xMPU_SETTINGS * xTaskMpuSettings;
+
+        ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+        ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+        xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+        xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit );
+    }
+
+#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+
+    #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+
+        BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+        {
+            uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+            BaseType_t xAccessGranted = pdFALSE;
+            const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+            ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+            ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+            if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+            {
+                xAccessGranted = pdTRUE;
+            }
+            else
+            {
+                if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                {
+                    xAccessGranted = pdTRUE;
+                }
+            }
+
+            return xAccessGranted;
+        }
+
+    #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+        BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+        {
+            ( void ) lInternalIndexOfKernelObject;
+
+            /* If Access Control List feature is not used, all the tasks have
+             * access to all the kernel objects. */
+            return pdTRUE;
+        }
+
+    #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM4_MPU/portmacro.h b/portable/GCC/ARM_CM4_MPU/portmacro.h
index c2d2464b4..e7d0c4105 100644
--- a/portable/GCC/ARM_CM4_MPU/portmacro.h
+++ b/portable/GCC/ARM_CM4_MPU/portmacro.h
@@ -221,7 +221,11 @@ typedef struct MPU_REGION_SETTINGS
 
 #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
-#define MAX_CONTEXT_SIZE                    52
+#define MAX_CONTEXT_SIZE                    ( 52 )
+
+/* Size of an Access Control List (ACL) entry in bits and bytes. */
+#define portACL_ENTRY_SIZE_BYTES            ( 4U )
+#define portACL_ENTRY_SIZE_BITS             ( 32U )
 
 /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
 #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
@@ -236,6 +240,9 @@ typedef struct MPU_SETTINGS
 
     #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
         xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
+        #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+            uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BYTES ) + 1 ];
+        #endif
     #endif
 } xMPU_SETTINGS;
 
diff --git a/portable/GCC/ARM_CM55/non_secure/port.c b/portable/GCC/ARM_CM55/non_secure/port.c
index c940c304b..e8ad8cf4c 100644
--- a/portable/GCC/ARM_CM55/non_secure/port.c
+++ b/portable/GCC/ARM_CM55/non_secure/port.c
@@ -2019,3 +2019,85 @@ BaseType_t xPortIsInsideInterrupt( void )
 
 #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+    void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+                                         int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+    {
+        uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+        xMPU_SETTINGS * xTaskMpuSettings;
+
+        ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+        ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+        xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+        xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit );
+    }
+
+#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+    void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+                                          int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+    {
+        uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+        xMPU_SETTINGS * xTaskMpuSettings;
+
+        ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+        ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+        xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+        xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit );
+    }
+
+#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+
+    #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+
+        BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+        {
+            uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+            BaseType_t xAccessGranted = pdFALSE;
+            const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+            ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+            ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+            if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+            {
+                xAccessGranted = pdTRUE;
+            }
+            else
+            {
+                if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                {
+                    xAccessGranted = pdTRUE;
+                }
+            }
+
+            return xAccessGranted;
+        }
+
+    #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+        BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+        {
+            ( void ) lInternalIndexOfKernelObject;
+
+            /* If Access Control List feature is not used, all the tasks have
+             * access to all the kernel objects. */
+            return pdTRUE;
+        }
+
+    #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h
index 62e462a27..cc2adb7fd 100644
--- a/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h
@@ -287,6 +287,10 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
+/* Size of an Access Control List (ACL) entry in bits and bytes. */
+    #define portACL_ENTRY_SIZE_BYTES            ( 4U )
+    #define portACL_ENTRY_SIZE_BITS             ( 32U )
+
     typedef struct MPU_SETTINGS
     {
         uint32_t ulMAIR0;                                              /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
@@ -296,6 +300,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
         #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
             xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
+            #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BYTES ) + 1 ];
+            #endif
         #endif
     } xMPU_SETTINGS;
 
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/port.c b/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
index c940c304b..e8ad8cf4c 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
@@ -2019,3 +2019,85 @@ BaseType_t xPortIsInsideInterrupt( void )
 
 #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+    void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+                                         int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+    {
+        uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+        xMPU_SETTINGS * xTaskMpuSettings;
+
+        ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+        ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+        xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+        xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit );
+    }
+
+#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+    void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+                                          int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+    {
+        uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+        xMPU_SETTINGS * xTaskMpuSettings;
+
+        ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+        ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+        xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+        xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit );
+    }
+
+#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+
+    #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+
+        BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+        {
+            uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+            BaseType_t xAccessGranted = pdFALSE;
+            const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+            ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+            ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+            if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+            {
+                xAccessGranted = pdTRUE;
+            }
+            else
+            {
+                if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                {
+                    xAccessGranted = pdTRUE;
+                }
+            }
+
+            return xAccessGranted;
+        }
+
+    #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+        BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+        {
+            ( void ) lInternalIndexOfKernelObject;
+
+            /* If Access Control List feature is not used, all the tasks have
+             * access to all the kernel objects. */
+            return pdTRUE;
+        }
+
+    #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h
index 62e462a27..cc2adb7fd 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h
@@ -287,6 +287,10 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
+/* Size of an Access Control List (ACL) entry in bits and bytes. */
+    #define portACL_ENTRY_SIZE_BYTES            ( 4U )
+    #define portACL_ENTRY_SIZE_BITS             ( 32U )
+
     typedef struct MPU_SETTINGS
     {
         uint32_t ulMAIR0;                                              /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
@@ -296,6 +300,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
         #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
             xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
+            #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BYTES ) + 1 ];
+            #endif
         #endif
     } xMPU_SETTINGS;
 
diff --git a/portable/GCC/ARM_CM85/non_secure/port.c b/portable/GCC/ARM_CM85/non_secure/port.c
index c940c304b..e8ad8cf4c 100644
--- a/portable/GCC/ARM_CM85/non_secure/port.c
+++ b/portable/GCC/ARM_CM85/non_secure/port.c
@@ -2019,3 +2019,85 @@ BaseType_t xPortIsInsideInterrupt( void )
 
 #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+    void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+                                         int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+    {
+        uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+        xMPU_SETTINGS * xTaskMpuSettings;
+
+        ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+        ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+        xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+        xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit );
+    }
+
+#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+    void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+                                          int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+    {
+        uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+        xMPU_SETTINGS * xTaskMpuSettings;
+
+        ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+        ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+        xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+        xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit );
+    }
+
+#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+
+    #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+
+        BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+        {
+            uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+            BaseType_t xAccessGranted = pdFALSE;
+            const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+            ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+            ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+            if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+            {
+                xAccessGranted = pdTRUE;
+            }
+            else
+            {
+                if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                {
+                    xAccessGranted = pdTRUE;
+                }
+            }
+
+            return xAccessGranted;
+        }
+
+    #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+        BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+        {
+            ( void ) lInternalIndexOfKernelObject;
+
+            /* If Access Control List feature is not used, all the tasks have
+             * access to all the kernel objects. */
+            return pdTRUE;
+        }
+
+    #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h
index 62e462a27..cc2adb7fd 100644
--- a/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h
@@ -287,6 +287,10 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
+/* Size of an Access Control List (ACL) entry in bits and bytes. */
+    #define portACL_ENTRY_SIZE_BYTES            ( 4U )
+    #define portACL_ENTRY_SIZE_BITS             ( 32U )
+
     typedef struct MPU_SETTINGS
     {
         uint32_t ulMAIR0;                                              /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
@@ -296,6 +300,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
         #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
             xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
+            #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BYTES ) + 1 ];
+            #endif
         #endif
     } xMPU_SETTINGS;
 
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/port.c b/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
index c940c304b..e8ad8cf4c 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
@@ -2019,3 +2019,85 @@ BaseType_t xPortIsInsideInterrupt( void )
 
 #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+    void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+                                         int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+    {
+        uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+        xMPU_SETTINGS * xTaskMpuSettings;
+
+        ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+        ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+        xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+        xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit );
+    }
+
+#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+    void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+                                          int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+    {
+        uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+        xMPU_SETTINGS * xTaskMpuSettings;
+
+        ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+        ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+        xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+        xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit );
+    }
+
+#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+
+    #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+
+        BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+        {
+            uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+            BaseType_t xAccessGranted = pdFALSE;
+            const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+            ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+            ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+            if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+            {
+                xAccessGranted = pdTRUE;
+            }
+            else
+            {
+                if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                {
+                    xAccessGranted = pdTRUE;
+                }
+            }
+
+            return xAccessGranted;
+        }
+
+    #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+        BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+        {
+            ( void ) lInternalIndexOfKernelObject;
+
+            /* If Access Control List feature is not used, all the tasks have
+             * access to all the kernel objects. */
+            return pdTRUE;
+        }
+
+    #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h
index 62e462a27..cc2adb7fd 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h
@@ -287,6 +287,10 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
+/* Size of an Access Control List (ACL) entry in bits and bytes. */
+    #define portACL_ENTRY_SIZE_BYTES            ( 4U )
+    #define portACL_ENTRY_SIZE_BITS             ( 32U )
+
     typedef struct MPU_SETTINGS
     {
         uint32_t ulMAIR0;                                              /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
@@ -296,6 +300,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
         #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
             xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
+            #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BYTES ) + 1 ];
+            #endif
         #endif
     } xMPU_SETTINGS;
 
diff --git a/portable/IAR/ARM_CM23/non_secure/port.c b/portable/IAR/ARM_CM23/non_secure/port.c
index c940c304b..e8ad8cf4c 100644
--- a/portable/IAR/ARM_CM23/non_secure/port.c
+++ b/portable/IAR/ARM_CM23/non_secure/port.c
@@ -2019,3 +2019,85 @@ BaseType_t xPortIsInsideInterrupt( void )
 
 #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+    void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+                                         int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+    {
+        uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+        xMPU_SETTINGS * xTaskMpuSettings;
+
+        ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+        ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+        xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+        xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit );
+    }
+
+#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+    void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+                                          int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+    {
+        uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+        xMPU_SETTINGS * xTaskMpuSettings;
+
+        ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+        ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+        xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+        xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit );
+    }
+
+#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+
+    #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+
+        BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+        {
+            uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+            BaseType_t xAccessGranted = pdFALSE;
+            const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+            ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+            ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+            if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+            {
+                xAccessGranted = pdTRUE;
+            }
+            else
+            {
+                if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                {
+                    xAccessGranted = pdTRUE;
+                }
+            }
+
+            return xAccessGranted;
+        }
+
+    #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+        BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+        {
+            ( void ) lInternalIndexOfKernelObject;
+
+            /* If Access Control List feature is not used, all the tasks have
+             * access to all the kernel objects. */
+            return pdTRUE;
+        }
+
+    #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h
index 62e462a27..cc2adb7fd 100644
--- a/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h
@@ -287,6 +287,10 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
+/* Size of an Access Control List (ACL) entry in bits and bytes. */
+    #define portACL_ENTRY_SIZE_BYTES            ( 4U )
+    #define portACL_ENTRY_SIZE_BITS             ( 32U )
+
     typedef struct MPU_SETTINGS
     {
         uint32_t ulMAIR0;                                              /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
@@ -296,6 +300,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
         #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
             xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
+            #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BYTES ) + 1 ];
+            #endif
         #endif
     } xMPU_SETTINGS;
 
diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
index c940c304b..e8ad8cf4c 100644
--- a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
@@ -2019,3 +2019,85 @@ BaseType_t xPortIsInsideInterrupt( void )
 
 #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+    void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+                                         int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+    {
+        uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+        xMPU_SETTINGS * xTaskMpuSettings;
+
+        ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+        ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+        xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+        xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit );
+    }
+
+#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+    void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+                                          int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+    {
+        uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+        xMPU_SETTINGS * xTaskMpuSettings;
+
+        ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+        ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+        xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+        xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit );
+    }
+
+#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+
+    #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+
+        BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+        {
+            uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+            BaseType_t xAccessGranted = pdFALSE;
+            const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+            ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+            ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+            if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+            {
+                xAccessGranted = pdTRUE;
+            }
+            else
+            {
+                if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                {
+                    xAccessGranted = pdTRUE;
+                }
+            }
+
+            return xAccessGranted;
+        }
+
+    #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+        BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+        {
+            ( void ) lInternalIndexOfKernelObject;
+
+            /* If Access Control List feature is not used, all the tasks have
+             * access to all the kernel objects. */
+            return pdTRUE;
+        }
+
+    #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h
index 62e462a27..cc2adb7fd 100644
--- a/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h
@@ -287,6 +287,10 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
+/* Size of an Access Control List (ACL) entry in bits and bytes. */
+    #define portACL_ENTRY_SIZE_BYTES            ( 4U )
+    #define portACL_ENTRY_SIZE_BITS             ( 32U )
+
     typedef struct MPU_SETTINGS
     {
         uint32_t ulMAIR0;                                              /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
@@ -296,6 +300,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
         #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
             xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
+            #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BYTES ) + 1 ];
+            #endif
         #endif
     } xMPU_SETTINGS;
 
diff --git a/portable/IAR/ARM_CM33/non_secure/port.c b/portable/IAR/ARM_CM33/non_secure/port.c
index c940c304b..e8ad8cf4c 100644
--- a/portable/IAR/ARM_CM33/non_secure/port.c
+++ b/portable/IAR/ARM_CM33/non_secure/port.c
@@ -2019,3 +2019,85 @@ BaseType_t xPortIsInsideInterrupt( void )
 
 #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+    void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+                                         int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+    {
+        uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+        xMPU_SETTINGS * xTaskMpuSettings;
+
+        ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+        ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+        xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+        xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit );
+    }
+
+#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+    void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+                                          int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+    {
+        uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+        xMPU_SETTINGS * xTaskMpuSettings;
+
+        ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+        ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+        xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+        xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit );
+    }
+
+#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+
+    #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+
+        BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+        {
+            uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+            BaseType_t xAccessGranted = pdFALSE;
+            const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+            ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+            ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+            if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+            {
+                xAccessGranted = pdTRUE;
+            }
+            else
+            {
+                if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                {
+                    xAccessGranted = pdTRUE;
+                }
+            }
+
+            return xAccessGranted;
+        }
+
+    #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+        BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+        {
+            ( void ) lInternalIndexOfKernelObject;
+
+            /* If Access Control List feature is not used, all the tasks have
+             * access to all the kernel objects. */
+            return pdTRUE;
+        }
+
+    #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h
index 62e462a27..cc2adb7fd 100644
--- a/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h
@@ -287,6 +287,10 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
+/* Size of an Access Control List (ACL) entry in bits and bytes. */
+    #define portACL_ENTRY_SIZE_BYTES            ( 4U )
+    #define portACL_ENTRY_SIZE_BITS             ( 32U )
+
     typedef struct MPU_SETTINGS
     {
         uint32_t ulMAIR0;                                              /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
@@ -296,6 +300,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
         #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
             xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
+            #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BYTES ) + 1 ];
+            #endif
         #endif
     } xMPU_SETTINGS;
 
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
index c940c304b..e8ad8cf4c 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
@@ -2019,3 +2019,85 @@ BaseType_t xPortIsInsideInterrupt( void )
 
 #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+    void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+                                         int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+    {
+        uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+        xMPU_SETTINGS * xTaskMpuSettings;
+
+        ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+        ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+        xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+        xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit );
+    }
+
+#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+    void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+                                          int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+    {
+        uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+        xMPU_SETTINGS * xTaskMpuSettings;
+
+        ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+        ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+        xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+        xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit );
+    }
+
+#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+
+    #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+
+        BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+        {
+            uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+            BaseType_t xAccessGranted = pdFALSE;
+            const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+            ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+            ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+            if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+            {
+                xAccessGranted = pdTRUE;
+            }
+            else
+            {
+                if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                {
+                    xAccessGranted = pdTRUE;
+                }
+            }
+
+            return xAccessGranted;
+        }
+
+    #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+        BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+        {
+            ( void ) lInternalIndexOfKernelObject;
+
+            /* If Access Control List feature is not used, all the tasks have
+             * access to all the kernel objects. */
+            return pdTRUE;
+        }
+
+    #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h
index 62e462a27..cc2adb7fd 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h
@@ -287,6 +287,10 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
+/* Size of an Access Control List (ACL) entry in bits and bytes. */
+    #define portACL_ENTRY_SIZE_BYTES            ( 4U )
+    #define portACL_ENTRY_SIZE_BITS             ( 32U )
+
     typedef struct MPU_SETTINGS
     {
         uint32_t ulMAIR0;                                              /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
@@ -296,6 +300,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
         #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
             xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
+            #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BYTES ) + 1 ];
+            #endif
         #endif
     } xMPU_SETTINGS;
 
diff --git a/portable/IAR/ARM_CM35P/non_secure/port.c b/portable/IAR/ARM_CM35P/non_secure/port.c
index c940c304b..e8ad8cf4c 100644
--- a/portable/IAR/ARM_CM35P/non_secure/port.c
+++ b/portable/IAR/ARM_CM35P/non_secure/port.c
@@ -2019,3 +2019,85 @@ BaseType_t xPortIsInsideInterrupt( void )
 
 #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+    void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+                                         int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+    {
+        uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+        xMPU_SETTINGS * xTaskMpuSettings;
+
+        ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+        ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+        xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+        xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit );
+    }
+
+#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+    void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+                                          int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+    {
+        uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+        xMPU_SETTINGS * xTaskMpuSettings;
+
+        ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+        ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+        xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+        xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit );
+    }
+
+#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+
+    #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+
+        BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+        {
+            uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+            BaseType_t xAccessGranted = pdFALSE;
+            const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+            ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+            ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+            if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+            {
+                xAccessGranted = pdTRUE;
+            }
+            else
+            {
+                if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                {
+                    xAccessGranted = pdTRUE;
+                }
+            }
+
+            return xAccessGranted;
+        }
+
+    #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+        BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+        {
+            ( void ) lInternalIndexOfKernelObject;
+
+            /* If Access Control List feature is not used, all the tasks have
+             * access to all the kernel objects. */
+            return pdTRUE;
+        }
+
+    #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h
index 62e462a27..cc2adb7fd 100644
--- a/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h
@@ -287,6 +287,10 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
+/* Size of an Access Control List (ACL) entry in bits and bytes. */
+    #define portACL_ENTRY_SIZE_BYTES            ( 4U )
+    #define portACL_ENTRY_SIZE_BITS             ( 32U )
+
     typedef struct MPU_SETTINGS
     {
         uint32_t ulMAIR0;                                              /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
@@ -296,6 +300,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
         #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
             xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
+            #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BYTES ) + 1 ];
+            #endif
         #endif
     } xMPU_SETTINGS;
 
diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c b/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
index c940c304b..e8ad8cf4c 100644
--- a/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
@@ -2019,3 +2019,85 @@ BaseType_t xPortIsInsideInterrupt( void )
 
 #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+    void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+                                         int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+    {
+        uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+        xMPU_SETTINGS * xTaskMpuSettings;
+
+        ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+        ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+        xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+        xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit );
+    }
+
+#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+    void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+                                          int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+    {
+        uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+        xMPU_SETTINGS * xTaskMpuSettings;
+
+        ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+        ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+        xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+        xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit );
+    }
+
+#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+
+    #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+
+        BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+        {
+            uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+            BaseType_t xAccessGranted = pdFALSE;
+            const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+            ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+            ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+            if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+            {
+                xAccessGranted = pdTRUE;
+            }
+            else
+            {
+                if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                {
+                    xAccessGranted = pdTRUE;
+                }
+            }
+
+            return xAccessGranted;
+        }
+
+    #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+        BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+        {
+            ( void ) lInternalIndexOfKernelObject;
+
+            /* If Access Control List feature is not used, all the tasks have
+             * access to all the kernel objects. */
+            return pdTRUE;
+        }
+
+    #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
index 62e462a27..cc2adb7fd 100644
--- a/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
@@ -287,6 +287,10 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
+/* Size of an Access Control List (ACL) entry in bits and bytes. */
+    #define portACL_ENTRY_SIZE_BYTES            ( 4U )
+    #define portACL_ENTRY_SIZE_BITS             ( 32U )
+
     typedef struct MPU_SETTINGS
     {
         uint32_t ulMAIR0;                                              /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
@@ -296,6 +300,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
         #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
             xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
+            #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BYTES ) + 1 ];
+            #endif
         #endif
     } xMPU_SETTINGS;
 
diff --git a/portable/IAR/ARM_CM4F_MPU/port.c b/portable/IAR/ARM_CM4F_MPU/port.c
index 5cd257044..2d90c348c 100644
--- a/portable/IAR/ARM_CM4F_MPU/port.c
+++ b/portable/IAR/ARM_CM4F_MPU/port.c
@@ -1332,3 +1332,85 @@ BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
 
 #endif /* configASSERT_DEFINED */
 /*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+    void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+                                         int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+    {
+        uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+        xMPU_SETTINGS * xTaskMpuSettings;
+
+        ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+        ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+        xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+        xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit );
+    }
+
+#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+    void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+                                          int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+    {
+        uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+        xMPU_SETTINGS * xTaskMpuSettings;
+
+        ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+        ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+        xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+        xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit );
+    }
+
+#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+
+    #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+
+        BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+        {
+            uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+            BaseType_t xAccessGranted = pdFALSE;
+            const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+            ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+            ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+            if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+            {
+                xAccessGranted = pdTRUE;
+            }
+            else
+            {
+                if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                {
+                    xAccessGranted = pdTRUE;
+                }
+            }
+
+            return xAccessGranted;
+        }
+
+    #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+        BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+        {
+            ( void ) lInternalIndexOfKernelObject;
+
+            /* If Access Control List feature is not used, all the tasks have
+             * access to all the kernel objects. */
+            return pdTRUE;
+        }
+
+    #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM4F_MPU/portmacro.h b/portable/IAR/ARM_CM4F_MPU/portmacro.h
index 799836b95..8a5538064 100644
--- a/portable/IAR/ARM_CM4F_MPU/portmacro.h
+++ b/portable/IAR/ARM_CM4F_MPU/portmacro.h
@@ -223,7 +223,11 @@ typedef struct MPU_REGION_SETTINGS
 
 #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
-#define MAX_CONTEXT_SIZE                    52
+#define MAX_CONTEXT_SIZE                    ( 52 )
+
+/* Size of an Access Control List (ACL) entry in bits and bytes. */
+#define portACL_ENTRY_SIZE_BYTES            ( 4U )
+#define portACL_ENTRY_SIZE_BITS             ( 32U )
 
 /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
 #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
@@ -238,6 +242,9 @@ typedef struct MPU_SETTINGS
 
     #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
         xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
+        #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+            uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BYTES ) + 1 ];
+        #endif
     #endif
 } xMPU_SETTINGS;
 
diff --git a/portable/IAR/ARM_CM55/non_secure/port.c b/portable/IAR/ARM_CM55/non_secure/port.c
index c940c304b..e8ad8cf4c 100644
--- a/portable/IAR/ARM_CM55/non_secure/port.c
+++ b/portable/IAR/ARM_CM55/non_secure/port.c
@@ -2019,3 +2019,85 @@ BaseType_t xPortIsInsideInterrupt( void )
 
 #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+    void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+                                         int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+    {
+        uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+        xMPU_SETTINGS * xTaskMpuSettings;
+
+        ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+        ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+        xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+        xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit );
+    }
+
+#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+    void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+                                          int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+    {
+        uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+        xMPU_SETTINGS * xTaskMpuSettings;
+
+        ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+        ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+        xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+        xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit );
+    }
+
+#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+
+    #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+
+        BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+        {
+            uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+            BaseType_t xAccessGranted = pdFALSE;
+            const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+            ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+            ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+            if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+            {
+                xAccessGranted = pdTRUE;
+            }
+            else
+            {
+                if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                {
+                    xAccessGranted = pdTRUE;
+                }
+            }
+
+            return xAccessGranted;
+        }
+
+    #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+        BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+        {
+            ( void ) lInternalIndexOfKernelObject;
+
+            /* If Access Control List feature is not used, all the tasks have
+             * access to all the kernel objects. */
+            return pdTRUE;
+        }
+
+    #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h
index 62e462a27..cc2adb7fd 100644
--- a/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h
@@ -287,6 +287,10 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
+/* Size of an Access Control List (ACL) entry in bits and bytes. */
+    #define portACL_ENTRY_SIZE_BYTES            ( 4U )
+    #define portACL_ENTRY_SIZE_BITS             ( 32U )
+
     typedef struct MPU_SETTINGS
     {
         uint32_t ulMAIR0;                                              /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
@@ -296,6 +300,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
         #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
             xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
+            #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BYTES ) + 1 ];
+            #endif
         #endif
     } xMPU_SETTINGS;
 
diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/port.c b/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
index c940c304b..e8ad8cf4c 100644
--- a/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
@@ -2019,3 +2019,85 @@ BaseType_t xPortIsInsideInterrupt( void )
 
 #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+    void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+                                         int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+    {
+        uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+        xMPU_SETTINGS * xTaskMpuSettings;
+
+        ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+        ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+        xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+        xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit );
+    }
+
+#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+    void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+                                          int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+    {
+        uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+        xMPU_SETTINGS * xTaskMpuSettings;
+
+        ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+        ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+        xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+        xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit );
+    }
+
+#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+
+    #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+
+        BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+        {
+            uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+            BaseType_t xAccessGranted = pdFALSE;
+            const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+            ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+            ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+            if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+            {
+                xAccessGranted = pdTRUE;
+            }
+            else
+            {
+                if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                {
+                    xAccessGranted = pdTRUE;
+                }
+            }
+
+            return xAccessGranted;
+        }
+
+    #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+        BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+        {
+            ( void ) lInternalIndexOfKernelObject;
+
+            /* If Access Control List feature is not used, all the tasks have
+             * access to all the kernel objects. */
+            return pdTRUE;
+        }
+
+    #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h
index 62e462a27..cc2adb7fd 100644
--- a/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h
@@ -287,6 +287,10 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
+/* Size of an Access Control List (ACL) entry in bits and bytes. */
+    #define portACL_ENTRY_SIZE_BYTES            ( 4U )
+    #define portACL_ENTRY_SIZE_BITS             ( 32U )
+
     typedef struct MPU_SETTINGS
     {
         uint32_t ulMAIR0;                                              /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
@@ -296,6 +300,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
         #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
             xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
+            #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BYTES ) + 1 ];
+            #endif
         #endif
     } xMPU_SETTINGS;
 
diff --git a/portable/IAR/ARM_CM85/non_secure/port.c b/portable/IAR/ARM_CM85/non_secure/port.c
index c940c304b..e8ad8cf4c 100644
--- a/portable/IAR/ARM_CM85/non_secure/port.c
+++ b/portable/IAR/ARM_CM85/non_secure/port.c
@@ -2019,3 +2019,85 @@ BaseType_t xPortIsInsideInterrupt( void )
 
 #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+    void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+                                         int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+    {
+        uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+        xMPU_SETTINGS * xTaskMpuSettings;
+
+        ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+        ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+        xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+        xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit );
+    }
+
+#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+    void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+                                          int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+    {
+        uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+        xMPU_SETTINGS * xTaskMpuSettings;
+
+        ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+        ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+        xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+        xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit );
+    }
+
+#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+
+    #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+
+        BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+        {
+            uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+            BaseType_t xAccessGranted = pdFALSE;
+            const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+            ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+            ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+            if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+            {
+                xAccessGranted = pdTRUE;
+            }
+            else
+            {
+                if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                {
+                    xAccessGranted = pdTRUE;
+                }
+            }
+
+            return xAccessGranted;
+        }
+
+    #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+        BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+        {
+            ( void ) lInternalIndexOfKernelObject;
+
+            /* If Access Control List feature is not used, all the tasks have
+             * access to all the kernel objects. */
+            return pdTRUE;
+        }
+
+    #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h
index 62e462a27..cc2adb7fd 100644
--- a/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h
@@ -287,6 +287,10 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
+/* Size of an Access Control List (ACL) entry in bits and bytes. */
+    #define portACL_ENTRY_SIZE_BYTES            ( 4U )
+    #define portACL_ENTRY_SIZE_BITS             ( 32U )
+
     typedef struct MPU_SETTINGS
     {
         uint32_t ulMAIR0;                                              /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
@@ -296,6 +300,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
         #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
             xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
+            #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BYTES ) + 1 ];
+            #endif
         #endif
     } xMPU_SETTINGS;
 
diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/port.c b/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
index c940c304b..e8ad8cf4c 100644
--- a/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
@@ -2019,3 +2019,85 @@ BaseType_t xPortIsInsideInterrupt( void )
 
 #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+    void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+                                         int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+    {
+        uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+        xMPU_SETTINGS * xTaskMpuSettings;
+
+        ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+        ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+        xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+        xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit );
+    }
+
+#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+    void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+                                          int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+    {
+        uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+        xMPU_SETTINGS * xTaskMpuSettings;
+
+        ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+        ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+        xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+        xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit );
+    }
+
+#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+
+    #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+
+        BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+        {
+            uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+            BaseType_t xAccessGranted = pdFALSE;
+            const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+            ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+            ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+            if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+            {
+                xAccessGranted = pdTRUE;
+            }
+            else
+            {
+                if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                {
+                    xAccessGranted = pdTRUE;
+                }
+            }
+
+            return xAccessGranted;
+        }
+
+    #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+        BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+        {
+            ( void ) lInternalIndexOfKernelObject;
+
+            /* If Access Control List feature is not used, all the tasks have
+             * access to all the kernel objects. */
+            return pdTRUE;
+        }
+
+    #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h
index 62e462a27..cc2adb7fd 100644
--- a/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h
@@ -287,6 +287,10 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
+/* Size of an Access Control List (ACL) entry in bits and bytes. */
+    #define portACL_ENTRY_SIZE_BYTES            ( 4U )
+    #define portACL_ENTRY_SIZE_BITS             ( 32U )
+
     typedef struct MPU_SETTINGS
     {
         uint32_t ulMAIR0;                                              /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
@@ -296,6 +300,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
         #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
             xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
+            #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BYTES ) + 1 ];
+            #endif
         #endif
     } xMPU_SETTINGS;
 
diff --git a/portable/RVDS/ARM_CM4_MPU/port.c b/portable/RVDS/ARM_CM4_MPU/port.c
index be087d823..e5324945a 100644
--- a/portable/RVDS/ARM_CM4_MPU/port.c
+++ b/portable/RVDS/ARM_CM4_MPU/port.c
@@ -1598,3 +1598,86 @@ __asm uint32_t prvPortGetIPSR( void )
     }
 
 #endif /* configASSERT_DEFINED */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+    void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+                                         int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+    {
+        uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+        xMPU_SETTINGS * xTaskMpuSettings;
+
+        ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+        ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+        xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+        xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit );
+    }
+
+#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+    void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+                                          int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+    {
+        uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+        xMPU_SETTINGS * xTaskMpuSettings;
+
+        ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+        ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+        xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+        xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit );
+    }
+
+#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+
+    #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+
+        BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+        {
+            uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+            BaseType_t xAccessGranted = pdFALSE;
+            const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+            ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+            ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+            if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+            {
+                xAccessGranted = pdTRUE;
+            }
+            else
+            {
+                if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                {
+                    xAccessGranted = pdTRUE;
+                }
+            }
+
+            return xAccessGranted;
+        }
+
+    #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+        BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+        {
+            ( void ) lInternalIndexOfKernelObject;
+
+            /* If Access Control List feature is not used, all the tasks have
+             * access to all the kernel objects. */
+            return pdTRUE;
+        }
+
+    #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/RVDS/ARM_CM4_MPU/portmacro.h b/portable/RVDS/ARM_CM4_MPU/portmacro.h
index e67086a7f..4566fba1c 100644
--- a/portable/RVDS/ARM_CM4_MPU/portmacro.h
+++ b/portable/RVDS/ARM_CM4_MPU/portmacro.h
@@ -221,7 +221,11 @@ typedef struct MPU_REGION_SETTINGS
 
 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
-#define MAX_CONTEXT_SIZE                    52
+#define MAX_CONTEXT_SIZE                    ( 52 )
+
+/* Size of an Access Control List (ACL) entry in bits and bytes. */
+#define portACL_ENTRY_SIZE_BYTES            ( 4U )
+#define portACL_ENTRY_SIZE_BITS             ( 32U )
 
 /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
 #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
@@ -236,6 +240,9 @@ typedef struct MPU_SETTINGS
 
     #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
         xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
+        #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+            uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BYTES ) + 1 ];
+        #endif
     #endif
 } xMPU_SETTINGS;
 

From 596292f8746200dd0794accb57a5711a8d2fa3a7 Mon Sep 17 00:00:00 2001
From: Soren Ptak <ptaksoren@gmail.com>
Date: Mon, 18 Sep 2023 15:48:26 -0400
Subject: [PATCH 058/424] Add the formatting bot action to FreeRTOS-Kernel
 (#787)

---
 .github/workflows/formatting.yml | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)
 create mode 100644 .github/workflows/formatting.yml

diff --git a/.github/workflows/formatting.yml b/.github/workflows/formatting.yml
new file mode 100644
index 000000000..8257addac
--- /dev/null
+++ b/.github/workflows/formatting.yml
@@ -0,0 +1,23 @@
+name: Format Pull Request Files
+
+on:
+  issue_comment:
+    types: [created]
+
+env:
+  bashPass: \033[32;1mPASSED -
+  bashInfo: \033[33;1mINFO -
+  bashFail: \033[31;1mFAILED -
+  bashEnd:  \033[0m
+
+jobs:
+  Formatting:
+    name: Run Formatting Check
+    if: ${{ github.event.issue.pull_request }} &&
+        ( ( github.event.comment.body == '/bot run uncrustify' ) ||
+          ( github.event.comment.body == '/bot run formatting' ) )
+    runs-on: ubuntu-20.04
+    steps:
+    - name: Apply Formatting Fix
+      uses: FreeRTOS/CI-CD-Github-Actions/formatting-bot@main
+      id: check-formatting

From c3ece081194453d1882564d19c33aa7b141a0b0b Mon Sep 17 00:00:00 2001
From: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Date: Wed, 20 Sep 2023 10:14:39 +0530
Subject: [PATCH 059/424] Fix prototype in mpu_prototypes.h (#797)

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 include/mpu_prototypes.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/mpu_prototypes.h b/include/mpu_prototypes.h
index 239e640bd..863bb5678 100644
--- a/include/mpu_prototypes.h
+++ b/include/mpu_prototypes.h
@@ -122,8 +122,8 @@ BaseType_t MPU_xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefin
                                       TaskHandle_t * pxCreatedTask ) PRIVILEGED_FUNCTION;
 BaseType_t MPU_xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition,
                                             TaskHandle_t * pxCreatedTask ) PRIVILEGED_FUNCTION;
-void vTaskAllocateMPURegions( TaskHandle_t xTaskToModify,
-                              const MemoryRegion_t * const xRegions ) PRIVILEGED_FUNCTION;
+void MPU_vTaskAllocateMPURegions( TaskHandle_t xTaskToModify,
+                                  const MemoryRegion_t * const xRegions ) PRIVILEGED_FUNCTION;
 BaseType_t MPU_xTaskGetStaticBuffers( TaskHandle_t xTask,
                                       StackType_t ** ppuxStackBuffer,
                                       StaticTask_t ** ppxTaskBuffer ) PRIVILEGED_FUNCTION;

From 7cd201c2907723db4602cd9b9af3203ac3374b15 Mon Sep 17 00:00:00 2001
From: Mehdi <37027977+mehdi-norouzi@users.noreply.github.com>
Date: Wed, 20 Sep 2023 09:09:37 +0330
Subject: [PATCH 060/424] Add default implementations of
 vApplicationGetIdleTaskMemory and vApplicationGetTimerTaskMemory (#790)

This PR introduces configKERNEL_PROVIDED_STATIC_MEMORY option
which the application can set to 1 to use the default implementations
of vApplicationGetIdleTaskMemory and vApplicationGetTimerTaskMemory
functions.

If the application enables static allocation (i.e. sets
configUSE_STATIC_ALLOCATION to 1) and does not provide the above 2
functions, it will result in linker error. The application has two options:

1. Set configKERNEL_PROVIDED_STATIC_MEMORY to 1 to use the default
    implementations of these functions.
2. Provide implementations of these 2 functions.

Note that default definitions are only available for non-MPU ports. The
reason is that the stack alignment requirements vary for different
architectures.
---
 include/FreeRTOS.h |  4 ++++
 tasks.c            | 49 ++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 53 insertions(+)

diff --git a/include/FreeRTOS.h b/include/FreeRTOS.h
index e11bc6302..33ce36bb9 100644
--- a/include/FreeRTOS.h
+++ b/include/FreeRTOS.h
@@ -1131,6 +1131,10 @@
     #define configSUPPORT_STATIC_ALLOCATION    0
 #endif
 
+#ifndef configKERNEL_PROVIDED_STATIC_MEMORY
+    #define configKERNEL_PROVIDED_STATIC_MEMORY    0
+#endif
+
 #ifndef configSUPPORT_DYNAMIC_ALLOCATION
     /* Defaults to 1 for backward compatibility. */
     #define configSUPPORT_DYNAMIC_ALLOCATION    1
diff --git a/tasks.c b/tasks.c
index 31e375479..99878a3a3 100644
--- a/tasks.c
+++ b/tasks.c
@@ -7653,3 +7653,52 @@ static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait,
     #endif
 
 #endif /* if ( configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H == 1 ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configKERNEL_PROVIDED_STATIC_MEMORY == 1 ) && ( portUSING_MPU_WRAPPERS == 0 ) )
+
+/*
+ * This is the kernel provided implementation of vApplicationGetIdleTaskMemory()
+ * to provide the memory that is used by the Idle task. It is used when
+ * configKERNEL_PROVIDED_STATIC_MEMORY is set to 1. The application can provide
+ * it's own implementation of vApplicationGetIdleTaskMemory by setting
+ * configKERNEL_PROVIDED_STATIC_MEMORY to 0 or leaving it undefined.
+ */
+    void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer,
+                                        StackType_t ** ppxIdleTaskStackBuffer,
+                                        uint32_t * pulIdleTaskStackSize )
+    {
+        static StaticTask_t xIdleTaskTCB;
+        static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ];
+
+        *ppxIdleTaskTCBBuffer = &( xIdleTaskTCB );
+        *ppxIdleTaskStackBuffer = &( uxIdleTaskStack[ 0 ] );
+        *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;
+    }
+
+#endif /* #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configKERNEL_PROVIDED_STATIC_MEMORY == 1 ) && ( portUSING_MPU_WRAPPERS == 0 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configKERNEL_PROVIDED_STATIC_MEMORY == 1 ) && ( portUSING_MPU_WRAPPERS == 0 ) )
+
+/*
+ * This is the kernel provided implementation of vApplicationGetTimerTaskMemory()
+ * to provide the memory that is used by the Timer service task. It is used when
+ * configKERNEL_PROVIDED_STATIC_MEMORY is set to 1. The application can provide
+ * it's own implementation of vApplicationGetTimerTaskMemory by setting
+ * configKERNEL_PROVIDED_STATIC_MEMORY to 0 or leaving it undefined.
+ */
+    void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer,
+                                         StackType_t ** ppxTimerTaskStackBuffer,
+                                         uint32_t * pulTimerTaskStackSize )
+    {
+        static StaticTask_t xTimerTaskTCB;
+        static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ];
+
+        *ppxTimerTaskTCBBuffer = &( xTimerTaskTCB );
+        *ppxTimerTaskStackBuffer = &( uxTimerTaskStack[ 0 ] );
+        *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH;
+    }
+
+#endif /* #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configKERNEL_PROVIDED_STATIC_MEMORY == 1 ) && ( portUSING_MPU_WRAPPERS == 0 ) ) */
+/*-----------------------------------------------------------*/

From c6ec8295e84ad8b64864b9595ca3a0cb5907d75e Mon Sep 17 00:00:00 2001
From: kar-rahul-aws <118818625+kar-rahul-aws@users.noreply.github.com>
Date: Wed, 20 Sep 2023 13:04:14 +0530
Subject: [PATCH 061/424] Remove CORTEX_M3_MPS2_QEMU_GCC Demo from kernel demos
 yaml file (#798)

---
 .github/workflows/kernel-demos.yml | 14 --------------
 1 file changed, 14 deletions(-)

diff --git a/.github/workflows/kernel-demos.yml b/.github/workflows/kernel-demos.yml
index 21cbd5c8d..62970a171 100644
--- a/.github/workflows/kernel-demos.yml
+++ b/.github/workflows/kernel-demos.yml
@@ -166,20 +166,6 @@ jobs:
         working-directory: FreeRTOS/Demo/CORTEX_LM3S102_GCC
         run: make -j
 
-      - name: Build CORTEX_M3_MPS2_QEMU_GCC Demo
-        shell: bash
-        working-directory: FreeRTOS/Demo/CORTEX_M3_MPS2_QEMU_GCC
-        run: |
-          make clean
-          make -j
-
-      - name: Build CORTEX_M3_MPS2_QEMU_GCC Demo
-        shell: bash
-        working-directory: FreeRTOS/Demo/CORTEX_M3_MPS2_QEMU_GCC
-        run: |
-          make clean
-          make FULL_DEMO=1 -j
-
       - name: Build CORTEX_LM3S811_GCC Demo
         shell: bash
         working-directory: FreeRTOS/Demo/CORTEX_LM3S811_GCC

From c59ce22c8fa119d7857cc2d614496e5c926b1773 Mon Sep 17 00:00:00 2001
From: Robert Berger <github@reliableembeddedsystems.com>
Date: Wed, 20 Sep 2023 09:47:26 +0200
Subject: [PATCH 062/424] Fix xQueueSendToFront code comment (#796)

Co-authored-by: Robert Berger <Robert.Berger@ReliableEmbeddedSystems.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Co-authored-by: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
---
 include/queue.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/queue.h b/include/queue.h
index db176e552..000003306 100644
--- a/include/queue.h
+++ b/include/queue.h
@@ -267,7 +267,7 @@ typedef struct QueueDefinition   * QueueSetMemberHandle_t;
 /**
  * queue. h
  * @code{c}
- * BaseType_t xQueueSendToToFront(
+ * BaseType_t xQueueSendToFront(
  *                                 QueueHandle_t    xQueue,
  *                                 const void       *pvItemToQueue,
  *                                 TickType_t       xTicksToWait

From 15e0364968aff9c6c3cc7b4893e8ec0311047ce2 Mon Sep 17 00:00:00 2001
From: Robert Berger <github@reliableembeddedsystems.com>
Date: Wed, 20 Sep 2023 11:03:56 +0200
Subject: [PATCH 063/424] xQueueSendToFromFromISR --> xQueueSendToFrontFromISR
 (#795)

Co-authored-by: Robert Berger <Robert.Berger@ReliableEmbeddedSystems.com>
Co-authored-by: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
---
 include/queue.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/queue.h b/include/queue.h
index 000003306..821545672 100644
--- a/include/queue.h
+++ b/include/queue.h
@@ -995,7 +995,7 @@ void vQueueDelete( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
  * @param pxHigherPriorityTaskWoken xQueueSendToFrontFromISR() will set
  * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
  * to unblock, and the unblocked task has a priority higher than the currently
- * running task.  If xQueueSendToFromFromISR() sets this value to pdTRUE then
+ * running task.  If xQueueSendToFrontFromISR() sets this value to pdTRUE then
  * a context switch should be requested before the interrupt is exited.
  *
  * @return pdTRUE if the data was successfully sent to the queue, otherwise

From 83861f5b1def1e4a3e1ea75562446f06e5b4359e Mon Sep 17 00:00:00 2001
From: Sebastian Brosch <9060129+Techcore123@users.noreply.github.com>
Date: Wed, 20 Sep 2023 12:17:42 +0200
Subject: [PATCH 064/424] Add Trace Hook Macros to all API calls (#786)

This pull-request adds out-of-the-box support for different tracing
tools. New trace hook macros have been added for all public API
functions, one for each function entry and one for each exit. There are
no functional changes, as the macros are by default empty.

For more information see following forum post:
https://forums.freertos.org/t/add-tracing-functionality-for-all-api-calls/18007.
---
 croutine.c         |   16 +
 event_groups.c     |   60 ++
 include/FreeRTOS.h | 1536 ++++++++++++++++++++++++++++++++++++++++++++
 list.c             |   26 +-
 queue.c            |  201 ++++++
 stream_buffer.c    |   79 +++
 tasks.c            |  353 ++++++++++
 timers.c           |   89 ++-
 8 files changed, 2357 insertions(+), 3 deletions(-)

diff --git a/croutine.c b/croutine.c
index 8969dc89b..f7d8ab95d 100644
--- a/croutine.c
+++ b/croutine.c
@@ -107,6 +107,8 @@
         BaseType_t xReturn;
         CRCB_t * pxCoRoutine;
 
+        traceENTER_xCoRoutineCreate( pxCoRoutineCode, uxPriority, uxIndex );
+
         /* Allocate the memory that will store the co-routine control block. */
         pxCoRoutine = ( CRCB_t * ) pvPortMalloc( sizeof( CRCB_t ) );
 
@@ -156,6 +158,8 @@
             xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
         }
 
+        traceRETURN_xCoRoutineCreate( xReturn );
+
         return xReturn;
     }
 /*-----------------------------------------------------------*/
@@ -165,6 +169,8 @@
     {
         TickType_t xTimeToWake;
 
+        traceENTER_vCoRoutineAddToDelayedList( xTicksToDelay, pxEventList );
+
         /* Calculate the time to wake - this may overflow but this is
          * not a problem. */
         xTimeToWake = xCoRoutineTickCount + xTicksToDelay;
@@ -196,6 +202,8 @@
              * function must be called with interrupts disabled. */
             vListInsert( pxEventList, &( pxCurrentCoRoutine->xEventListItem ) );
         }
+
+        traceRETURN_vCoRoutineAddToDelayedList();
     }
 /*-----------------------------------------------------------*/
 
@@ -283,6 +291,8 @@
 
     void vCoRoutineSchedule( void )
     {
+        traceENTER_vCoRoutineSchedule();
+
         /* Only run a co-routine after prvInitialiseCoRoutineLists() has been
          * called.  prvInitialiseCoRoutineLists() is called automatically when a
          * co-routine is created. */
@@ -313,6 +323,8 @@
             /* Call the co-routine. */
             ( pxCurrentCoRoutine->pxCoRoutineFunction )( pxCurrentCoRoutine, pxCurrentCoRoutine->uxIndex );
         }
+
+        traceRETURN_vCoRoutineSchedule();
     }
 /*-----------------------------------------------------------*/
 
@@ -341,6 +353,8 @@
         CRCB_t * pxUnblockedCRCB;
         BaseType_t xReturn;
 
+        traceENTER_xCoRoutineRemoveFromEventList( pxEventList );
+
         /* This function is called from within an interrupt.  It can only access
          * event lists and the pending ready list.  This function assumes that a
          * check has already been made to ensure pxEventList is not empty. */
@@ -357,6 +371,8 @@
             xReturn = pdFALSE;
         }
 
+        traceRETURN_xCoRoutineRemoveFromEventList( xReturn );
+
         return xReturn;
     }
 
diff --git a/event_groups.c b/event_groups.c
index 24d818711..6b68c087a 100644
--- a/event_groups.c
+++ b/event_groups.c
@@ -82,6 +82,8 @@ static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits,
     {
         EventGroup_t * pxEventBits;
 
+        traceENTER_xEventGroupCreateStatic( pxEventGroupBuffer );
+
         /* A StaticEventGroup_t object must be provided. */
         configASSERT( pxEventGroupBuffer );
 
@@ -122,6 +124,8 @@ static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits,
             traceEVENT_GROUP_CREATE_FAILED();
         }
 
+        traceRETURN_xEventGroupCreateStatic( pxEventBits );
+
         return pxEventBits;
     }
 
@@ -134,6 +138,8 @@ static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits,
     {
         EventGroup_t * pxEventBits;
 
+        traceENTER_xEventGroupCreate();
+
         /* Allocate the event group.  Justification for MISRA deviation as
          * follows:  pvPortMalloc() always ensures returned memory blocks are
          * aligned per the requirements of the MCU stack.  In this case
@@ -170,6 +176,8 @@ static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits,
             traceEVENT_GROUP_CREATE_FAILED(); /*lint !e9063 Else branch only exists to allow tracing and does not generate code if trace macros are not defined. */
         }
 
+        traceRETURN_xEventGroupCreate( pxEventBits );
+
         return pxEventBits;
     }
 
@@ -186,6 +194,8 @@ EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup,
     BaseType_t xAlreadyYielded;
     BaseType_t xTimeoutOccurred = pdFALSE;
 
+    traceENTER_xEventGroupSync( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTicksToWait );
+
     configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
     configASSERT( uxBitsToWaitFor != 0 );
     #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
@@ -303,6 +313,8 @@ EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup,
     /* Prevent compiler warnings when trace macros are not used. */
     ( void ) xTimeoutOccurred;
 
+    traceRETURN_xEventGroupSync( uxReturn );
+
     return uxReturn;
 }
 /*-----------------------------------------------------------*/
@@ -318,6 +330,8 @@ EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
     BaseType_t xWaitConditionMet, xAlreadyYielded;
     BaseType_t xTimeoutOccurred = pdFALSE;
 
+    traceENTER_xEventGroupWaitBits( xEventGroup, uxBitsToWaitFor, xClearOnExit, xWaitForAllBits, xTicksToWait );
+
     /* Check the user is not attempting to wait on the bits used by the kernel
      * itself, and that at least one bit is being requested. */
     configASSERT( xEventGroup );
@@ -467,6 +481,8 @@ EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
     /* Prevent compiler warnings when trace macros are not used. */
     ( void ) xTimeoutOccurred;
 
+    traceRETURN_xEventGroupWaitBits( uxReturn );
+
     return uxReturn;
 }
 /*-----------------------------------------------------------*/
@@ -477,6 +493,8 @@ EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup,
     EventGroup_t * pxEventBits = xEventGroup;
     EventBits_t uxReturn;
 
+    traceENTER_xEventGroupClearBits( xEventGroup, uxBitsToClear );
+
     /* Check the user is not attempting to clear the bits used by the kernel
      * itself. */
     configASSERT( xEventGroup );
@@ -495,6 +513,8 @@ EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup,
     }
     taskEXIT_CRITICAL();
 
+    traceRETURN_xEventGroupClearBits( uxReturn );
+
     return uxReturn;
 }
 /*-----------------------------------------------------------*/
@@ -506,9 +526,13 @@ EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup,
     {
         BaseType_t xReturn;
 
+        traceENTER_xEventGroupClearBitsFromISR( xEventGroup, uxBitsToClear );
+
         traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear );
         xReturn = xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL ); /*lint !e9087 Can't avoid cast to void* as a generic callback function not specific to this use case. Callback casts back to original type so safe. */
 
+        traceRETURN_xEventGroupClearBitsFromISR( xReturn );
+
         return xReturn;
     }
 
@@ -521,12 +545,16 @@ EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup )
     EventGroup_t const * const pxEventBits = xEventGroup;
     EventBits_t uxReturn;
 
+    traceENTER_xEventGroupGetBitsFromISR( xEventGroup );
+
     uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
     {
         uxReturn = pxEventBits->uxEventBits;
     }
     taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
 
+    traceRETURN_xEventGroupGetBitsFromISR( uxReturn );
+
     return uxReturn;
 } /*lint !e818 EventGroupHandle_t is a typedef used in other functions to so can't be pointer to const. */
 /*-----------------------------------------------------------*/
@@ -542,6 +570,8 @@ EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup,
     EventGroup_t * pxEventBits = xEventGroup;
     BaseType_t xMatchFound = pdFALSE;
 
+    traceENTER_xEventGroupSetBits( xEventGroup, uxBitsToSet );
+
     /* Check the user is not attempting to set the bits used by the kernel
      * itself. */
     configASSERT( xEventGroup );
@@ -623,6 +653,8 @@ EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup,
     }
     ( void ) xTaskResumeAll();
 
+    traceRETURN_xEventGroupSetBits( pxEventBits->uxEventBits );
+
     return pxEventBits->uxEventBits;
 }
 /*-----------------------------------------------------------*/
@@ -632,6 +664,8 @@ void vEventGroupDelete( EventGroupHandle_t xEventGroup )
     EventGroup_t * pxEventBits = xEventGroup;
     const List_t * pxTasksWaitingForBits;
 
+    traceENTER_vEventGroupDelete( xEventGroup );
+
     configASSERT( pxEventBits );
 
     pxTasksWaitingForBits = &( pxEventBits->xTasksWaitingForBits );
@@ -670,6 +704,8 @@ void vEventGroupDelete( EventGroupHandle_t xEventGroup )
         }
     }
     #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+
+    traceRETURN_vEventGroupDelete();
 }
 /*-----------------------------------------------------------*/
 
@@ -680,6 +716,8 @@ void vEventGroupDelete( EventGroupHandle_t xEventGroup )
         BaseType_t xReturn;
         EventGroup_t * pxEventBits = xEventGroup;
 
+        traceENTER_xEventGroupGetStaticBuffer( xEventGroup, ppxEventGroupBuffer );
+
         configASSERT( pxEventBits );
         configASSERT( ppxEventGroupBuffer );
 
@@ -704,6 +742,8 @@ void vEventGroupDelete( EventGroupHandle_t xEventGroup )
         }
         #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
 
+        traceRETURN_xEventGroupGetStaticBuffer( xReturn );
+
         return xReturn;
     }
 #endif /* configSUPPORT_STATIC_ALLOCATION */
@@ -714,7 +754,11 @@ void vEventGroupDelete( EventGroupHandle_t xEventGroup )
 void vEventGroupSetBitsCallback( void * pvEventGroup,
                                  const uint32_t ulBitsToSet )
 {
+    traceENTER_vEventGroupSetBitsCallback( pvEventGroup, ulBitsToSet );
+
     ( void ) xEventGroupSetBits( pvEventGroup, ( EventBits_t ) ulBitsToSet ); /*lint !e9079 Can't avoid cast to void* as a generic timer callback prototype. Callback casts back to original type so safe. */
+
+    traceRETURN_vEventGroupSetBitsCallback();
 }
 /*-----------------------------------------------------------*/
 
@@ -723,7 +767,11 @@ void vEventGroupSetBitsCallback( void * pvEventGroup,
 void vEventGroupClearBitsCallback( void * pvEventGroup,
                                    const uint32_t ulBitsToClear )
 {
+    traceENTER_vEventGroupClearBitsCallback( pvEventGroup, ulBitsToClear );
+
     ( void ) xEventGroupClearBits( pvEventGroup, ( EventBits_t ) ulBitsToClear ); /*lint !e9079 Can't avoid cast to void* as a generic timer callback prototype. Callback casts back to original type so safe. */
+
+    traceRETURN_vEventGroupClearBitsCallback();
 }
 /*-----------------------------------------------------------*/
 
@@ -772,9 +820,13 @@ static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits,
     {
         BaseType_t xReturn;
 
+        traceENTER_xEventGroupSetBitsFromISR( xEventGroup, uxBitsToSet, pxHigherPriorityTaskWoken );
+
         traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet );
         xReturn = xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken ); /*lint !e9087 Can't avoid cast to void* as a generic callback function not specific to this use case. Callback casts back to original type so safe. */
 
+        traceRETURN_xEventGroupSetBitsFromISR( xReturn );
+
         return xReturn;
     }
 
@@ -788,6 +840,8 @@ static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits,
         UBaseType_t xReturn;
         EventGroup_t const * pxEventBits = ( EventGroup_t * ) xEventGroup; /*lint !e9087 !e9079 EventGroupHandle_t is a pointer to an EventGroup_t, but EventGroupHandle_t is kept opaque outside of this file for data hiding purposes. */
 
+        traceENTER_uxEventGroupGetNumber( xEventGroup );
+
         if( xEventGroup == NULL )
         {
             xReturn = 0;
@@ -797,6 +851,8 @@ static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits,
             xReturn = pxEventBits->uxEventGroupNumber;
         }
 
+        traceRETURN_uxEventGroupGetNumber( xReturn );
+
         return xReturn;
     }
 
@@ -808,7 +864,11 @@ static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits,
     void vEventGroupSetNumber( void * xEventGroup,
                                UBaseType_t uxEventGroupNumber )
     {
+        traceENTER_vEventGroupSetNumber( xEventGroup, uxEventGroupNumber );
+
         ( ( EventGroup_t * ) xEventGroup )->uxEventGroupNumber = uxEventGroupNumber; /*lint !e9087 !e9079 EventGroupHandle_t is a pointer to an EventGroup_t, but EventGroupHandle_t is kept opaque outside of this file for data hiding purposes. */
+
+        traceRETURN_vEventGroupSetNumber();
     }
 
 #endif /* configUSE_TRACE_FACILITY */
diff --git a/include/FreeRTOS.h b/include/FreeRTOS.h
index 33ce36bb9..44ebb063e 100644
--- a/include/FreeRTOS.h
+++ b/include/FreeRTOS.h
@@ -978,6 +978,1542 @@
     #define traceSTREAM_BUFFER_RECEIVE_FROM_ISR( xStreamBuffer, xReceivedLength )
 #endif
 
+#ifndef traceENTER_xEventGroupCreateStatic
+    #define traceENTER_xEventGroupCreateStatic( pxEventGroupBuffer )
+#endif
+
+#ifndef traceRETURN_xEventGroupCreateStatic
+    #define traceRETURN_xEventGroupCreateStatic( pxEventBits )
+#endif
+
+#ifndef traceENTER_xEventGroupCreate
+    #define traceENTER_xEventGroupCreate()
+#endif
+
+#ifndef traceRETURN_xEventGroupCreate
+    #define traceRETURN_xEventGroupCreate( pxEventBits )
+#endif
+
+#ifndef traceENTER_xEventGroupSync
+    #define traceENTER_xEventGroupSync( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTicksToWait )
+#endif
+
+#ifndef traceRETURN_xEventGroupSync
+    #define traceRETURN_xEventGroupSync( uxReturn )
+#endif
+
+#ifndef traceENTER_xEventGroupWaitBits
+    #define traceENTER_xEventGroupWaitBits( xEventGroup, uxBitsToWaitFor, xClearOnExit, xWaitForAllBits, xTicksToWait )
+#endif
+
+#ifndef traceRETURN_xEventGroupWaitBits
+    #define traceRETURN_xEventGroupWaitBits( uxReturn )
+#endif
+
+#ifndef traceENTER_xEventGroupClearBits
+    #define traceENTER_xEventGroupClearBits( xEventGroup, uxBitsToClear )
+#endif
+
+#ifndef traceRETURN_xEventGroupClearBits
+    #define traceRETURN_xEventGroupClearBits( uxReturn )
+#endif
+
+#ifndef traceENTER_xEventGroupClearBitsFromISR
+    #define traceENTER_xEventGroupClearBitsFromISR( xEventGroup, uxBitsToClear )
+#endif
+
+#ifndef traceRETURN_xEventGroupClearBitsFromISR
+    #define traceRETURN_xEventGroupClearBitsFromISR( xReturn )
+#endif
+
+#ifndef traceENTER_xEventGroupGetBitsFromISR
+    #define traceENTER_xEventGroupGetBitsFromISR( xEventGroup )
+#endif
+
+#ifndef traceRETURN_xEventGroupGetBitsFromISR
+    #define traceRETURN_xEventGroupGetBitsFromISR( uxReturn )
+#endif
+
+#ifndef traceENTER_xEventGroupSetBits
+    #define traceENTER_xEventGroupSetBits( xEventGroup, uxBitsToSet )
+#endif
+
+#ifndef traceRETURN_xEventGroupSetBits
+    #define traceRETURN_xEventGroupSetBits( uxEventBits )
+#endif
+
+#ifndef traceENTER_vEventGroupDelete
+    #define traceENTER_vEventGroupDelete( xEventGroup )
+#endif
+
+#ifndef traceRETURN_vEventGroupDelete
+    #define traceRETURN_vEventGroupDelete()
+#endif
+
+#ifndef traceENTER_xEventGroupGetStaticBuffer
+    #define traceENTER_xEventGroupGetStaticBuffer( xEventGroup, ppxEventGroupBuffer )
+#endif
+
+#ifndef traceRETURN_xEventGroupGetStaticBuffer
+    #define traceRETURN_xEventGroupGetStaticBuffer( xReturn )
+#endif
+
+#ifndef traceENTER_vEventGroupSetBitsCallback
+    #define traceENTER_vEventGroupSetBitsCallback( pvEventGroup, ulBitsToSet )
+#endif
+
+#ifndef traceRETURN_vEventGroupSetBitsCallback
+    #define traceRETURN_vEventGroupSetBitsCallback()
+#endif
+
+#ifndef traceENTER_vEventGroupClearBitsCallback
+    #define traceENTER_vEventGroupClearBitsCallback( pvEventGroup, ulBitsToClear )
+#endif
+
+#ifndef traceRETURN_vEventGroupClearBitsCallback
+    #define traceRETURN_vEventGroupClearBitsCallback()
+#endif
+
+#ifndef traceENTER_xEventGroupSetBitsFromISR
+    #define traceENTER_xEventGroupSetBitsFromISR( xEventGroup, uxBitsToSet, pxHigherPriorityTaskWoken )
+#endif
+
+#ifndef traceRETURN_xEventGroupSetBitsFromISR
+    #define traceRETURN_xEventGroupSetBitsFromISR( xReturn )
+#endif
+
+#ifndef traceENTER_uxEventGroupGetNumber
+    #define traceENTER_uxEventGroupGetNumber( xEventGroup )
+#endif
+
+#ifndef traceRETURN_uxEventGroupGetNumber
+    #define traceRETURN_uxEventGroupGetNumber( xReturn )
+#endif
+
+#ifndef traceENTER_vEventGroupSetNumber
+    #define traceENTER_vEventGroupSetNumber( xEventGroup, uxEventGroupNumber )
+#endif
+
+#ifndef traceRETURN_vEventGroupSetNumber
+    #define traceRETURN_vEventGroupSetNumber()
+#endif
+
+#ifndef traceENTER_xQueueGenericReset
+    #define traceENTER_xQueueGenericReset( xQueue, xNewQueue )
+#endif
+
+#ifndef traceRETURN_xQueueGenericReset
+    #define traceRETURN_xQueueGenericReset( xReturn )
+#endif
+
+#ifndef traceENTER_xQueueGenericCreateStatic
+    #define traceENTER_xQueueGenericCreateStatic( uxQueueLength, uxItemSize, pucQueueStorage, pxStaticQueue, ucQueueType )
+#endif
+
+#ifndef traceRETURN_xQueueGenericCreateStatic
+    #define traceRETURN_xQueueGenericCreateStatic( pxNewQueue )
+#endif
+
+#ifndef traceENTER_xQueueGenericGetStaticBuffers
+    #define traceENTER_xQueueGenericGetStaticBuffers( xQueue, ppucQueueStorage, ppxStaticQueue )
+#endif
+
+#ifndef traceRETURN_xQueueGenericGetStaticBuffers
+    #define traceRETURN_xQueueGenericGetStaticBuffers( xReturn )
+#endif
+
+#ifndef traceENTER_xQueueGenericCreate
+    #define traceENTER_xQueueGenericCreate( uxQueueLength, uxItemSize, ucQueueType )
+#endif
+
+#ifndef traceRETURN_xQueueGenericCreate
+    #define traceRETURN_xQueueGenericCreate( pxNewQueue )
+#endif
+
+#ifndef traceENTER_xQueueCreateMutex
+    #define traceENTER_xQueueCreateMutex( ucQueueType )
+#endif
+
+#ifndef traceRETURN_xQueueCreateMutex
+    #define traceRETURN_xQueueCreateMutex( xNewQueue )
+#endif
+
+#ifndef traceENTER_xQueueCreateMutexStatic
+    #define traceENTER_xQueueCreateMutexStatic( ucQueueType, pxStaticQueue )
+#endif
+
+#ifndef traceRETURN_xQueueCreateMutexStatic
+    #define traceRETURN_xQueueCreateMutexStatic( xNewQueue )
+#endif
+
+#ifndef traceENTER_xQueueGetMutexHolder
+    #define traceENTER_xQueueGetMutexHolder( xSemaphore )
+#endif
+
+#ifndef traceRETURN_xQueueGetMutexHolder
+    #define traceRETURN_xQueueGetMutexHolder( pxReturn )
+#endif
+
+#ifndef traceENTER_xQueueGetMutexHolderFromISR
+    #define traceENTER_xQueueGetMutexHolderFromISR( xSemaphore )
+#endif
+
+#ifndef traceRETURN_xQueueGetMutexHolderFromISR
+    #define traceRETURN_xQueueGetMutexHolderFromISR( pxReturn )
+#endif
+
+#ifndef traceENTER_xQueueGiveMutexRecursive
+    #define traceENTER_xQueueGiveMutexRecursive( xMutex )
+#endif
+
+#ifndef traceRETURN_xQueueGiveMutexRecursive
+    #define traceRETURN_xQueueGiveMutexRecursive( xReturn )
+#endif
+
+#ifndef traceENTER_xQueueTakeMutexRecursive
+    #define traceENTER_xQueueTakeMutexRecursive( xMutex, xTicksToWait )
+#endif
+
+#ifndef traceRETURN_xQueueTakeMutexRecursive
+    #define traceRETURN_xQueueTakeMutexRecursive( xReturn )
+#endif
+
+#ifndef traceENTER_xQueueCreateCountingSemaphoreStatic
+    #define traceENTER_xQueueCreateCountingSemaphoreStatic( uxMaxCount, uxInitialCount, pxStaticQueue )
+#endif
+
+#ifndef traceRETURN_xQueueCreateCountingSemaphoreStatic
+    #define traceRETURN_xQueueCreateCountingSemaphoreStatic( xHandle )
+#endif
+
+#ifndef traceENTER_xQueueCreateCountingSemaphore
+    #define traceENTER_xQueueCreateCountingSemaphore( uxMaxCount, uxInitialCount )
+#endif
+
+#ifndef traceRETURN_xQueueCreateCountingSemaphore
+    #define traceRETURN_xQueueCreateCountingSemaphore( xHandle )
+#endif
+
+#ifndef traceENTER_xQueueGenericSend
+    #define traceENTER_xQueueGenericSend( xQueue, pvItemToQueue, xTicksToWait, xCopyPosition )
+#endif
+
+#ifndef traceRETURN_xQueueGenericSend
+    #define traceRETURN_xQueueGenericSend( xReturn )
+#endif
+
+#ifndef traceENTER_xQueueGenericSendFromISR
+    #define traceENTER_xQueueGenericSendFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken, xCopyPosition )
+#endif
+
+#ifndef traceRETURN_xQueueGenericSendFromISR
+    #define traceRETURN_xQueueGenericSendFromISR( xReturn )
+#endif
+
+#ifndef traceENTER_xQueueGiveFromISR
+    #define traceENTER_xQueueGiveFromISR( xQueue, pxHigherPriorityTaskWoken )
+#endif
+
+#ifndef traceRETURN_xQueueGiveFromISR
+    #define traceRETURN_xQueueGiveFromISR( xReturn )
+#endif
+
+#ifndef traceENTER_xQueueReceive
+    #define traceENTER_xQueueReceive( xQueue, pvBuffer, xTicksToWait )
+#endif
+
+#ifndef traceRETURN_xQueueReceive
+    #define traceRETURN_xQueueReceive( xReturn )
+#endif
+
+#ifndef traceENTER_xQueueSemaphoreTake
+    #define traceENTER_xQueueSemaphoreTake( xQueue, xTicksToWait )
+#endif
+
+#ifndef traceRETURN_xQueueSemaphoreTake
+    #define traceRETURN_xQueueSemaphoreTake( xReturn )
+#endif
+
+#ifndef traceENTER_xQueuePeek
+    #define traceENTER_xQueuePeek( xQueue, pvBuffer, xTicksToWait )
+#endif
+
+#ifndef traceRETURN_xQueuePeek
+    #define traceRETURN_xQueuePeek( xReturn )
+#endif
+
+#ifndef traceENTER_xQueueReceiveFromISR
+    #define traceENTER_xQueueReceiveFromISR( xQueue, pvBuffer, pxHigherPriorityTaskWoken )
+#endif
+
+#ifndef traceRETURN_xQueueReceiveFromISR
+    #define traceRETURN_xQueueReceiveFromISR( xReturn )
+#endif
+
+#ifndef traceENTER_xQueuePeekFromISR
+    #define traceENTER_xQueuePeekFromISR( xQueue, pvBuffer )
+#endif
+
+#ifndef traceRETURN_xQueuePeekFromISR
+    #define traceRETURN_xQueuePeekFromISR( xReturn )
+#endif
+
+#ifndef traceENTER_uxQueueMessagesWaiting
+    #define traceENTER_uxQueueMessagesWaiting( xQueue )
+#endif
+
+#ifndef traceRETURN_uxQueueMessagesWaiting
+    #define traceRETURN_uxQueueMessagesWaiting( uxReturn )
+#endif
+
+#ifndef traceENTER_uxQueueSpacesAvailable
+    #define traceENTER_uxQueueSpacesAvailable( xQueue )
+#endif
+
+#ifndef traceRETURN_uxQueueSpacesAvailable
+    #define traceRETURN_uxQueueSpacesAvailable( uxReturn )
+#endif
+
+#ifndef traceENTER_uxQueueMessagesWaitingFromISR
+    #define traceENTER_uxQueueMessagesWaitingFromISR( xQueue )
+#endif
+
+#ifndef traceRETURN_uxQueueMessagesWaitingFromISR
+    #define traceRETURN_uxQueueMessagesWaitingFromISR( uxReturn )
+#endif
+
+#ifndef traceENTER_vQueueDelete
+    #define traceENTER_vQueueDelete( xQueue )
+#endif
+
+#ifndef traceRETURN_vQueueDelete
+    #define traceRETURN_vQueueDelete()
+#endif
+
+#ifndef traceENTER_uxQueueGetQueueNumber
+    #define traceENTER_uxQueueGetQueueNumber( xQueue )
+#endif
+
+#ifndef traceRETURN_uxQueueGetQueueNumber
+    #define traceRETURN_uxQueueGetQueueNumber( uxQueueNumber )
+#endif
+
+#ifndef traceENTER_vQueueSetQueueNumber
+    #define traceENTER_vQueueSetQueueNumber( xQueue, uxQueueNumber )
+#endif
+
+#ifndef traceRETURN_vQueueSetQueueNumber
+    #define traceRETURN_vQueueSetQueueNumber()
+#endif
+
+#ifndef traceENTER_ucQueueGetQueueType
+    #define traceENTER_ucQueueGetQueueType( xQueue )
+#endif
+
+#ifndef traceRETURN_ucQueueGetQueueType
+    #define traceRETURN_ucQueueGetQueueType( ucQueueType )
+#endif
+
+#ifndef traceENTER_uxQueueGetQueueItemSize
+    #define traceENTER_uxQueueGetQueueItemSize( xQueue )
+#endif
+
+#ifndef traceRETURN_uxQueueGetQueueItemSize
+    #define traceRETURN_uxQueueGetQueueItemSize( uxItemSize )
+#endif
+
+#ifndef traceENTER_uxQueueGetQueueLength
+    #define traceENTER_uxQueueGetQueueLength( xQueue )
+#endif
+
+#ifndef traceRETURN_uxQueueGetQueueLength
+    #define traceRETURN_uxQueueGetQueueLength( uxLength )
+#endif
+
+#ifndef traceENTER_xQueueIsQueueEmptyFromISR
+    #define traceENTER_xQueueIsQueueEmptyFromISR( xQueue )
+#endif
+
+#ifndef traceRETURN_xQueueIsQueueEmptyFromISR
+    #define traceRETURN_xQueueIsQueueEmptyFromISR( xReturn )
+#endif
+
+#ifndef traceENTER_xQueueIsQueueFullFromISR
+    #define traceENTER_xQueueIsQueueFullFromISR( xQueue )
+#endif
+
+#ifndef traceRETURN_xQueueIsQueueFullFromISR
+    #define traceRETURN_xQueueIsQueueFullFromISR( xReturn )
+#endif
+
+#ifndef traceENTER_xQueueCRSend
+    #define traceENTER_xQueueCRSend( xQueue, pvItemToQueue, xTicksToWait )
+#endif
+
+#ifndef traceRETURN_xQueueCRSend
+    #define traceRETURN_xQueueCRSend( xReturn )
+#endif
+
+#ifndef traceENTER_xQueueCRReceive
+    #define traceENTER_xQueueCRReceive( xQueue, pvBuffer, xTicksToWait )
+#endif
+
+#ifndef traceRETURN_xQueueCRReceive
+    #define traceRETURN_xQueueCRReceive( xReturn )
+#endif
+
+#ifndef traceENTER_xQueueCRSendFromISR
+    #define traceENTER_xQueueCRSendFromISR( xQueue, pvItemToQueue, xCoRoutinePreviouslyWoken )
+#endif
+
+#ifndef traceRETURN_xQueueCRSendFromISR
+    #define traceRETURN_xQueueCRSendFromISR( xCoRoutinePreviouslyWoken )
+#endif
+
+#ifndef traceENTER_xQueueCRReceiveFromISR
+    #define traceENTER_xQueueCRReceiveFromISR( xQueue, pvBuffer, pxCoRoutineWoken )
+#endif
+
+#ifndef traceRETURN_xQueueCRReceiveFromISR
+    #define traceRETURN_xQueueCRReceiveFromISR( xReturn )
+#endif
+
+#ifndef traceENTER_vQueueAddToRegistry
+    #define traceENTER_vQueueAddToRegistry( xQueue, pcQueueName )
+#endif
+
+#ifndef traceRETURN_vQueueAddToRegistry
+    #define traceRETURN_vQueueAddToRegistry()
+#endif
+
+#ifndef traceENTER_pcQueueGetName
+    #define traceENTER_pcQueueGetName( xQueue )
+#endif
+
+#ifndef traceRETURN_pcQueueGetName
+    #define traceRETURN_pcQueueGetName( pcReturn )
+#endif
+
+#ifndef traceENTER_vQueueUnregisterQueue
+    #define traceENTER_vQueueUnregisterQueue( xQueue )
+#endif
+
+#ifndef traceRETURN_vQueueUnregisterQueue
+    #define traceRETURN_vQueueUnregisterQueue()
+#endif
+
+#ifndef traceENTER_vQueueWaitForMessageRestricted
+    #define traceENTER_vQueueWaitForMessageRestricted( xQueue, xTicksToWait, xWaitIndefinitely )
+#endif
+
+#ifndef traceRETURN_vQueueWaitForMessageRestricted
+    #define traceRETURN_vQueueWaitForMessageRestricted()
+#endif
+
+#ifndef traceENTER_xQueueCreateSet
+    #define traceENTER_xQueueCreateSet( uxEventQueueLength )
+#endif
+
+#ifndef traceRETURN_xQueueCreateSet
+    #define traceRETURN_xQueueCreateSet( pxQueue )
+#endif
+
+#ifndef traceENTER_xQueueAddToSet
+    #define traceENTER_xQueueAddToSet( xQueueOrSemaphore, xQueueSet )
+#endif
+
+#ifndef traceRETURN_xQueueAddToSet
+    #define traceRETURN_xQueueAddToSet( xReturn )
+#endif
+
+#ifndef traceENTER_xQueueRemoveFromSet
+    #define traceENTER_xQueueRemoveFromSet( xQueueOrSemaphore, xQueueSet )
+#endif
+
+#ifndef traceRETURN_xQueueRemoveFromSet
+    #define traceRETURN_xQueueRemoveFromSet( xReturn )
+#endif
+
+#ifndef traceENTER_xQueueSelectFromSet
+    #define traceENTER_xQueueSelectFromSet( xQueueSet, xTicksToWait )
+#endif
+
+#ifndef traceRETURN_xQueueSelectFromSet
+    #define traceRETURN_xQueueSelectFromSet( xReturn )
+#endif
+
+#ifndef traceENTER_xQueueSelectFromSetFromISR
+    #define traceENTER_xQueueSelectFromSetFromISR( xQueueSet )
+#endif
+
+#ifndef traceRETURN_xQueueSelectFromSetFromISR
+    #define traceRETURN_xQueueSelectFromSetFromISR( xReturn )
+#endif
+
+#ifndef traceENTER_xTimerCreateTimerTask
+    #define traceENTER_xTimerCreateTimerTask()
+#endif
+
+#ifndef traceRETURN_xTimerCreateTimerTask
+    #define traceRETURN_xTimerCreateTimerTask( xReturn )
+#endif
+
+#ifndef traceENTER_xTimerCreate
+    #define traceENTER_xTimerCreate( pcTimerName, xTimerPeriodInTicks, xAutoReload, pvTimerID, pxCallbackFunction )
+#endif
+
+#ifndef traceRETURN_xTimerCreate
+    #define traceRETURN_xTimerCreate( pxNewTimer )
+#endif
+
+#ifndef traceENTER_xTimerCreateStatic
+    #define traceENTER_xTimerCreateStatic( pcTimerName, xTimerPeriodInTicks, xAutoReload, pvTimerID, pxCallbackFunction, pxTimerBuffer )
+#endif
+
+#ifndef traceRETURN_xTimerCreateStatic
+    #define traceRETURN_xTimerCreateStatic( pxNewTimer )
+#endif
+
+#ifndef traceENTER_xTimerGenericCommandFromTask
+    #define traceENTER_xTimerGenericCommandFromTask( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait )
+#endif
+
+#ifndef traceRETURN_xTimerGenericCommandFromTask
+    #define traceRETURN_xTimerGenericCommandFromTask( xReturn )
+#endif
+
+#ifndef traceENTER_xTimerGenericCommandFromISR
+    #define traceENTER_xTimerGenericCommandFromISR( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait )
+#endif
+
+#ifndef traceRETURN_xTimerGenericCommandFromISR
+    #define traceRETURN_xTimerGenericCommandFromISR( xReturn )
+#endif
+
+#ifndef traceENTER_xTimerGetTimerDaemonTaskHandle
+    #define traceENTER_xTimerGetTimerDaemonTaskHandle()
+#endif
+
+#ifndef traceRETURN_xTimerGetTimerDaemonTaskHandle
+    #define traceRETURN_xTimerGetTimerDaemonTaskHandle( xTimerTaskHandle )
+#endif
+
+#ifndef traceENTER_xTimerGetPeriod
+    #define traceENTER_xTimerGetPeriod( xTimer )
+#endif
+
+#ifndef traceRETURN_xTimerGetPeriod
+    #define traceRETURN_xTimerGetPeriod( xTimerPeriodInTicks )
+#endif
+
+#ifndef traceENTER_vTimerSetReloadMode
+    #define traceENTER_vTimerSetReloadMode( xTimer, xAutoReload )
+#endif
+
+#ifndef traceRETURN_vTimerSetReloadMode
+    #define traceRETURN_vTimerSetReloadMode()
+#endif
+
+#ifndef traceENTER_xTimerGetReloadMode
+    #define traceENTER_xTimerGetReloadMode( xTimer )
+#endif
+
+#ifndef traceRETURN_xTimerGetReloadMode
+    #define traceRETURN_xTimerGetReloadMode( xReturn )
+#endif
+
+#ifndef traceENTER_uxTimerGetReloadMode
+    #define traceENTER_uxTimerGetReloadMode( xTimer )
+#endif
+
+#ifndef traceRETURN_uxTimerGetReloadMode
+    #define traceRETURN_uxTimerGetReloadMode( uxReturn )
+#endif
+
+#ifndef traceENTER_xTimerGetExpiryTime
+    #define traceENTER_xTimerGetExpiryTime( xTimer )
+#endif
+
+#ifndef traceRETURN_xTimerGetExpiryTime
+    #define traceRETURN_xTimerGetExpiryTime( xReturn )
+#endif
+
+#ifndef traceENTER_xTimerGetStaticBuffer
+    #define traceENTER_xTimerGetStaticBuffer( xTimer, ppxTimerBuffer )
+#endif
+
+#ifndef traceRETURN_xTimerGetStaticBuffer
+    #define traceRETURN_xTimerGetStaticBuffer( xReturn )
+#endif
+
+#ifndef traceENTER_pcTimerGetName
+    #define traceENTER_pcTimerGetName( xTimer )
+#endif
+
+#ifndef traceRETURN_pcTimerGetName
+    #define traceRETURN_pcTimerGetName( pcTimerName )
+#endif
+
+#ifndef traceENTER_xTimerIsTimerActive
+    #define traceENTER_xTimerIsTimerActive( xTimer )
+#endif
+
+#ifndef traceRETURN_xTimerIsTimerActive
+    #define traceRETURN_xTimerIsTimerActive( xReturn )
+#endif
+
+#ifndef traceENTER_pvTimerGetTimerID
+    #define traceENTER_pvTimerGetTimerID( xTimer )
+#endif
+
+#ifndef traceRETURN_pvTimerGetTimerID
+    #define traceRETURN_pvTimerGetTimerID( pvReturn )
+#endif
+
+#ifndef traceENTER_vTimerSetTimerID
+    #define traceENTER_vTimerSetTimerID( xTimer, pvNewID )
+#endif
+
+#ifndef traceRETURN_vTimerSetTimerID
+    #define traceRETURN_vTimerSetTimerID()
+#endif
+
+#ifndef traceENTER_xTimerPendFunctionCallFromISR
+    #define traceENTER_xTimerPendFunctionCallFromISR( xFunctionToPend, pvParameter1, ulParameter2, pxHigherPriorityTaskWoken )
+#endif
+
+#ifndef traceRETURN_xTimerPendFunctionCallFromISR
+    #define traceRETURN_xTimerPendFunctionCallFromISR( xReturn )
+#endif
+
+#ifndef traceENTER_xTimerPendFunctionCall
+    #define traceENTER_xTimerPendFunctionCall( xFunctionToPend, pvParameter1, ulParameter2, xTicksToWait )
+#endif
+
+#ifndef traceRETURN_xTimerPendFunctionCall
+    #define traceRETURN_xTimerPendFunctionCall( xReturn )
+#endif
+
+#ifndef traceENTER_uxTimerGetTimerNumber
+    #define traceENTER_uxTimerGetTimerNumber( xTimer )
+#endif
+
+#ifndef traceRETURN_uxTimerGetTimerNumber
+    #define traceRETURN_uxTimerGetTimerNumber( uxTimerNumber )
+#endif
+
+#ifndef traceENTER_vTimerSetTimerNumber
+    #define traceENTER_vTimerSetTimerNumber( xTimer, uxTimerNumber )
+#endif
+
+#ifndef traceRETURN_vTimerSetTimerNumber
+    #define traceRETURN_vTimerSetTimerNumber()
+#endif
+
+#ifndef traceENTER_xTaskCreateStatic
+    #define traceENTER_xTaskCreateStatic( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer )
+#endif
+
+#ifndef traceRETURN_xTaskCreateStatic
+    #define traceRETURN_xTaskCreateStatic( xReturn )
+#endif
+
+#ifndef traceENTER_xTaskCreateRestrictedStatic
+    #define traceENTER_xTaskCreateRestrictedStatic( pxTaskDefinition, pxCreatedTask )
+#endif
+
+#ifndef traceRETURN_xTaskCreateRestrictedStatic
+    #define traceRETURN_xTaskCreateRestrictedStatic( xReturn )
+#endif
+
+#ifndef traceENTER_xTaskCreateRestricted
+    #define traceENTER_xTaskCreateRestricted( pxTaskDefinition, pxCreatedTask )
+#endif
+
+#ifndef traceRETURN_xTaskCreateRestricted
+    #define traceRETURN_xTaskCreateRestricted( xReturn )
+#endif
+
+#ifndef traceENTER_xTaskCreate
+    #define traceENTER_xTaskCreate( pxTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask )
+#endif
+
+#ifndef traceRETURN_xTaskCreate
+    #define traceRETURN_xTaskCreate( xReturn )
+#endif
+
+#ifndef traceENTER_vTaskDelete
+    #define traceENTER_vTaskDelete( xTaskToDelete )
+#endif
+
+#ifndef traceRETURN_vTaskDelete
+    #define traceRETURN_vTaskDelete()
+#endif
+
+#ifndef traceENTER_xTaskDelayUntil
+    #define traceENTER_xTaskDelayUntil( pxPreviousWakeTime, xTimeIncrement )
+#endif
+
+#ifndef traceRETURN_xTaskDelayUntil
+    #define traceRETURN_xTaskDelayUntil( xShouldDelay )
+#endif
+
+#ifndef traceENTER_vTaskDelay
+    #define traceENTER_vTaskDelay( xTicksToDelay )
+#endif
+
+#ifndef traceRETURN_vTaskDelay
+    #define traceRETURN_vTaskDelay()
+#endif
+
+#ifndef traceENTER_eTaskGetState
+    #define traceENTER_eTaskGetState( xTask )
+#endif
+
+#ifndef traceRETURN_eTaskGetState
+    #define traceRETURN_eTaskGetState( eReturn )
+#endif
+
+#ifndef traceENTER_uxTaskPriorityGet
+    #define traceENTER_uxTaskPriorityGet( xTask )
+#endif
+
+#ifndef traceRETURN_uxTaskPriorityGet
+    #define traceRETURN_uxTaskPriorityGet( uxReturn )
+#endif
+
+#ifndef traceENTER_uxTaskPriorityGetFromISR
+    #define traceENTER_uxTaskPriorityGetFromISR( xTask )
+#endif
+
+#ifndef traceRETURN_uxTaskPriorityGetFromISR
+    #define traceRETURN_uxTaskPriorityGetFromISR( uxReturn )
+#endif
+
+#ifndef traceENTER_vTaskPrioritySet
+    #define traceENTER_vTaskPrioritySet( xTask, uxNewPriority )
+#endif
+
+#ifndef traceRETURN_vTaskPrioritySet
+    #define traceRETURN_vTaskPrioritySet()
+#endif
+
+#ifndef traceENTER_vTaskCoreAffinitySet
+    #define traceENTER_vTaskCoreAffinitySet( xTask, uxCoreAffinityMask )
+#endif
+
+#ifndef traceRETURN_vTaskCoreAffinitySet
+    #define traceRETURN_vTaskCoreAffinitySet()
+#endif
+
+#ifndef traceENTER_vTaskCoreAffinityGet
+    #define traceENTER_vTaskCoreAffinityGet( xTask )
+#endif
+
+#ifndef traceRETURN_vTaskCoreAffinityGet
+    #define traceRETURN_vTaskCoreAffinityGet( uxCoreAffinityMask )
+#endif
+
+#ifndef traceENTER_vTaskPreemptionDisable
+    #define traceENTER_vTaskPreemptionDisable( xTask )
+#endif
+
+#ifndef traceRETURN_vTaskPreemptionDisable
+    #define traceRETURN_vTaskPreemptionDisable()
+#endif
+
+#ifndef traceENTER_vTaskPreemptionEnable
+    #define traceENTER_vTaskPreemptionEnable( xTask )
+#endif
+
+#ifndef traceRETURN_vTaskPreemptionEnable
+    #define traceRETURN_vTaskPreemptionEnable()
+#endif
+
+#ifndef traceENTER_vTaskSuspend
+    #define traceENTER_vTaskSuspend( xTaskToSuspend )
+#endif
+
+#ifndef traceRETURN_vTaskSuspend
+    #define traceRETURN_vTaskSuspend()
+#endif
+
+#ifndef traceENTER_vTaskResume
+    #define traceENTER_vTaskResume( xTaskToResume )
+#endif
+
+#ifndef traceRETURN_vTaskResume
+    #define traceRETURN_vTaskResume()
+#endif
+
+#ifndef traceENTER_xTaskResumeFromISR
+    #define traceENTER_xTaskResumeFromISR( xTaskToResume )
+#endif
+
+#ifndef traceRETURN_xTaskResumeFromISR
+    #define traceRETURN_xTaskResumeFromISR( xYieldRequired )
+#endif
+
+#ifndef traceENTER_vTaskStartScheduler
+    #define traceENTER_vTaskStartScheduler()
+#endif
+
+#ifndef traceRETURN_vTaskStartScheduler
+    #define traceRETURN_vTaskStartScheduler()
+#endif
+
+#ifndef traceENTER_vTaskEndScheduler
+    #define traceENTER_vTaskEndScheduler()
+#endif
+
+#ifndef traceRETURN_vTaskEndScheduler
+    #define traceRETURN_vTaskEndScheduler()
+#endif
+
+#ifndef traceENTER_vTaskSuspendAll
+    #define traceENTER_vTaskSuspendAll()
+#endif
+
+#ifndef traceRETURN_vTaskSuspendAll
+    #define traceRETURN_vTaskSuspendAll()
+#endif
+
+#ifndef traceENTER_xTaskResumeAll
+    #define traceENTER_xTaskResumeAll()
+#endif
+
+#ifndef traceRETURN_xTaskResumeAll
+    #define traceRETURN_xTaskResumeAll( xAlreadyYielded )
+#endif
+
+#ifndef traceENTER_xTaskGetTickCount
+    #define traceENTER_xTaskGetTickCount()
+#endif
+
+#ifndef traceRETURN_xTaskGetTickCount
+    #define traceRETURN_xTaskGetTickCount( xTicks )
+#endif
+
+#ifndef traceENTER_xTaskGetTickCountFromISR
+    #define traceENTER_xTaskGetTickCountFromISR()
+#endif
+
+#ifndef traceRETURN_xTaskGetTickCountFromISR
+    #define traceRETURN_xTaskGetTickCountFromISR( xReturn )
+#endif
+
+#ifndef traceENTER_uxTaskGetNumberOfTasks
+    #define traceENTER_uxTaskGetNumberOfTasks()
+#endif
+
+#ifndef traceRETURN_uxTaskGetNumberOfTasks
+    #define traceRETURN_uxTaskGetNumberOfTasks( uxCurrentNumberOfTasks )
+#endif
+
+#ifndef traceENTER_pcTaskGetName
+    #define traceENTER_pcTaskGetName( xTaskToQuery )
+#endif
+
+#ifndef traceRETURN_pcTaskGetName
+    #define traceRETURN_pcTaskGetName( pcTaskName )
+#endif
+
+#ifndef traceENTER_xTaskGetHandle
+    #define traceENTER_xTaskGetHandle( pcNameToQuery )
+#endif
+
+#ifndef traceRETURN_xTaskGetHandle
+    #define traceRETURN_xTaskGetHandle( pxTCB )
+#endif
+
+#ifndef traceENTER_xTaskGetStaticBuffers
+    #define traceENTER_xTaskGetStaticBuffers( xTask, ppuxStackBuffer, ppxTaskBuffer )
+#endif
+
+#ifndef traceRETURN_xTaskGetStaticBuffers
+    #define traceRETURN_xTaskGetStaticBuffers( xReturn )
+#endif
+
+#ifndef traceENTER_uxTaskGetSystemState
+    #define traceENTER_uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, pulTotalRunTime )
+#endif
+
+#ifndef traceRETURN_uxTaskGetSystemState
+    #define traceRETURN_uxTaskGetSystemState( uxTask )
+#endif
+
+#ifndef traceENTER_xTaskGetIdleTaskHandle
+    #define traceENTER_xTaskGetIdleTaskHandle()
+#endif
+
+#ifndef traceRETURN_xTaskGetIdleTaskHandle
+    #define traceRETURN_xTaskGetIdleTaskHandle( xIdleTaskHandle )
+#endif
+
+#ifndef traceENTER_vTaskStepTick
+    #define traceENTER_vTaskStepTick( xTicksToJump )
+#endif
+
+#ifndef traceRETURN_vTaskStepTick
+    #define traceRETURN_vTaskStepTick()
+#endif
+
+#ifndef traceENTER_xTaskCatchUpTicks
+    #define traceENTER_xTaskCatchUpTicks( xTicksToCatchUp )
+#endif
+
+#ifndef traceRETURN_xTaskCatchUpTicks
+    #define traceRETURN_xTaskCatchUpTicks( xYieldOccurred )
+#endif
+
+#ifndef traceENTER_xTaskAbortDelay
+    #define traceENTER_xTaskAbortDelay( xTask )
+#endif
+
+#ifndef traceRETURN_xTaskAbortDelay
+    #define traceRETURN_xTaskAbortDelay( xReturn )
+#endif
+
+#ifndef traceENTER_xTaskIncrementTick
+    #define traceENTER_xTaskIncrementTick()
+#endif
+
+#ifndef traceRETURN_xTaskIncrementTick
+    #define traceRETURN_xTaskIncrementTick( xSwitchRequired )
+#endif
+
+#ifndef traceENTER_vTaskSetApplicationTaskTag
+    #define traceENTER_vTaskSetApplicationTaskTag( xTask, pxHookFunction )
+#endif
+
+#ifndef traceRETURN_vTaskSetApplicationTaskTag
+    #define traceRETURN_vTaskSetApplicationTaskTag()
+#endif
+
+#ifndef traceENTER_xTaskGetApplicationTaskTag
+    #define traceENTER_xTaskGetApplicationTaskTag( xTask )
+#endif
+
+#ifndef traceRETURN_xTaskGetApplicationTaskTag
+    #define traceRETURN_xTaskGetApplicationTaskTag( xReturn )
+#endif
+
+#ifndef traceENTER_xTaskGetApplicationTaskTagFromISR
+    #define traceENTER_xTaskGetApplicationTaskTagFromISR( xTask )
+#endif
+
+#ifndef traceRETURN_xTaskGetApplicationTaskTagFromISR
+    #define traceRETURN_xTaskGetApplicationTaskTagFromISR( xReturn )
+#endif
+
+#ifndef traceENTER_xTaskCallApplicationTaskHook
+    #define traceENTER_xTaskCallApplicationTaskHook( xTask, pvParameter )
+#endif
+
+#ifndef traceRETURN_xTaskCallApplicationTaskHook
+    #define traceRETURN_xTaskCallApplicationTaskHook( xReturn )
+#endif
+
+#ifndef traceENTER_vTaskSwitchContext
+    #define traceENTER_vTaskSwitchContext()
+#endif
+
+#ifndef traceRETURN_vTaskSwitchContext
+    #define traceRETURN_vTaskSwitchContext()
+#endif
+
+#ifndef traceENTER_vTaskPlaceOnEventList
+    #define traceENTER_vTaskPlaceOnEventList( pxEventList, xTicksToWait )
+#endif
+
+#ifndef traceRETURN_vTaskPlaceOnEventList
+    #define traceRETURN_vTaskPlaceOnEventList()
+#endif
+
+#ifndef traceENTER_vTaskPlaceOnUnorderedEventList
+    #define traceENTER_vTaskPlaceOnUnorderedEventList( pxEventList, xItemValue, xTicksToWait )
+#endif
+
+#ifndef traceRETURN_vTaskPlaceOnUnorderedEventList
+    #define traceRETURN_vTaskPlaceOnUnorderedEventList()
+#endif
+
+#ifndef traceENTER_vTaskPlaceOnEventListRestricted
+    #define traceENTER_vTaskPlaceOnEventListRestricted( pxEventList, xTicksToWait, xWaitIndefinitely )
+#endif
+
+#ifndef traceRETURN_vTaskPlaceOnEventListRestricted
+    #define traceRETURN_vTaskPlaceOnEventListRestricted()
+#endif
+
+#ifndef traceENTER_xTaskRemoveFromEventList
+    #define traceENTER_xTaskRemoveFromEventList( pxEventList )
+#endif
+
+#ifndef traceRETURN_xTaskRemoveFromEventList
+    #define traceRETURN_xTaskRemoveFromEventList( xReturn )
+#endif
+
+#ifndef traceENTER_vTaskRemoveFromUnorderedEventList
+    #define traceENTER_vTaskRemoveFromUnorderedEventList( pxEventListItem, xItemValue )
+#endif
+
+#ifndef traceRETURN_vTaskRemoveFromUnorderedEventList
+    #define traceRETURN_vTaskRemoveFromUnorderedEventList()
+#endif
+
+#ifndef traceENTER_vTaskSetTimeOutState
+    #define traceENTER_vTaskSetTimeOutState( pxTimeOut )
+#endif
+
+#ifndef traceRETURN_vTaskSetTimeOutState
+    #define traceRETURN_vTaskSetTimeOutState()
+#endif
+
+#ifndef traceENTER_vTaskInternalSetTimeOutState
+    #define traceENTER_vTaskInternalSetTimeOutState( pxTimeOut )
+#endif
+
+#ifndef traceRETURN_vTaskInternalSetTimeOutState
+    #define traceRETURN_vTaskInternalSetTimeOutState()
+#endif
+
+#ifndef traceENTER_xTaskCheckForTimeOut
+    #define traceENTER_xTaskCheckForTimeOut( pxTimeOut, pxTicksToWait )
+#endif
+
+#ifndef traceRETURN_xTaskCheckForTimeOut
+    #define traceRETURN_xTaskCheckForTimeOut( xReturn )
+#endif
+
+#ifndef traceENTER_vTaskMissedYield
+    #define traceENTER_vTaskMissedYield()
+#endif
+
+#ifndef traceRETURN_vTaskMissedYield
+    #define traceRETURN_vTaskMissedYield()
+#endif
+
+#ifndef traceENTER_uxTaskGetTaskNumber
+    #define traceENTER_uxTaskGetTaskNumber( xTask )
+#endif
+
+#ifndef traceRETURN_uxTaskGetTaskNumber
+    #define traceRETURN_uxTaskGetTaskNumber( uxReturn )
+#endif
+
+#ifndef traceENTER_vTaskSetTaskNumber
+    #define traceENTER_vTaskSetTaskNumber( xTask, uxHandle )
+#endif
+
+#ifndef traceRETURN_vTaskSetTaskNumber
+    #define traceRETURN_vTaskSetTaskNumber()
+#endif
+
+#ifndef traceENTER_eTaskConfirmSleepModeStatus
+    #define traceENTER_eTaskConfirmSleepModeStatus()
+#endif
+
+#ifndef traceRETURN_eTaskConfirmSleepModeStatus
+    #define traceRETURN_eTaskConfirmSleepModeStatus( eReturn )
+#endif
+
+#ifndef traceENTER_vTaskSetThreadLocalStoragePointer
+    #define traceENTER_vTaskSetThreadLocalStoragePointer( xTaskToSet, xIndex, pvValue )
+#endif
+
+#ifndef traceRETURN_vTaskSetThreadLocalStoragePointer
+    #define traceRETURN_vTaskSetThreadLocalStoragePointer()
+#endif
+
+#ifndef traceENTER_pvTaskGetThreadLocalStoragePointer
+    #define traceENTER_pvTaskGetThreadLocalStoragePointer( xTaskToQuery, xIndex )
+#endif
+
+#ifndef traceRETURN_pvTaskGetThreadLocalStoragePointer
+    #define traceRETURN_pvTaskGetThreadLocalStoragePointer( pvReturn )
+#endif
+
+#ifndef traceENTER_vTaskAllocateMPURegions
+    #define traceENTER_vTaskAllocateMPURegions( xTaskToModify, pxRegions )
+#endif
+
+#ifndef traceRETURN_vTaskAllocateMPURegions
+    #define traceRETURN_vTaskAllocateMPURegions()
+#endif
+
+#ifndef traceENTER_vTaskGetInfo
+    #define traceENTER_vTaskGetInfo( xTask, pxTaskStatus, xGetFreeStackSpace, eState )
+#endif
+
+#ifndef traceRETURN_vTaskGetInfo
+    #define traceRETURN_vTaskGetInfo()
+#endif
+
+#ifndef traceENTER_uxTaskGetStackHighWaterMark2
+    #define traceENTER_uxTaskGetStackHighWaterMark2( xTask )
+#endif
+
+#ifndef traceRETURN_uxTaskGetStackHighWaterMark2
+    #define traceRETURN_uxTaskGetStackHighWaterMark2( uxReturn )
+#endif
+
+#ifndef traceENTER_uxTaskGetStackHighWaterMark
+    #define traceENTER_uxTaskGetStackHighWaterMark( xTask )
+#endif
+
+#ifndef traceRETURN_uxTaskGetStackHighWaterMark
+    #define traceRETURN_uxTaskGetStackHighWaterMark( uxReturn )
+#endif
+
+#ifndef traceENTER_xTaskGetCurrentTaskHandle
+    #define traceENTER_xTaskGetCurrentTaskHandle()
+#endif
+
+#ifndef traceRETURN_xTaskGetCurrentTaskHandle
+    #define traceRETURN_xTaskGetCurrentTaskHandle( xReturn )
+#endif
+
+#ifndef traceENTER_xTaskGetCurrentTaskHandleCPU
+    #define traceENTER_xTaskGetCurrentTaskHandleCPU( xCoreID )
+#endif
+
+#ifndef traceRETURN_xTaskGetCurrentTaskHandleCPU
+    #define traceRETURN_xTaskGetCurrentTaskHandleCPU( xReturn )
+#endif
+
+#ifndef traceENTER_xTaskGetSchedulerState
+    #define traceENTER_xTaskGetSchedulerState()
+#endif
+
+#ifndef traceRETURN_xTaskGetSchedulerState
+    #define traceRETURN_xTaskGetSchedulerState( xReturn )
+#endif
+
+#ifndef traceENTER_xTaskPriorityInherit
+    #define traceENTER_xTaskPriorityInherit( pxMutexHolder )
+#endif
+
+#ifndef traceRETURN_xTaskPriorityInherit
+    #define traceRETURN_xTaskPriorityInherit( xReturn )
+#endif
+
+#ifndef traceENTER_xTaskPriorityDisinherit
+    #define traceENTER_xTaskPriorityDisinherit( pxMutexHolder )
+#endif
+
+#ifndef traceRETURN_xTaskPriorityDisinherit
+    #define traceRETURN_xTaskPriorityDisinherit( xReturn )
+#endif
+
+#ifndef traceENTER_vTaskPriorityDisinheritAfterTimeout
+    #define traceENTER_vTaskPriorityDisinheritAfterTimeout( pxMutexHolder, uxHighestPriorityWaitingTask )
+#endif
+
+#ifndef traceRETURN_vTaskPriorityDisinheritAfterTimeout
+    #define traceRETURN_vTaskPriorityDisinheritAfterTimeout()
+#endif
+
+#ifndef traceENTER_vTaskYieldWithinAPI
+    #define traceENTER_vTaskYieldWithinAPI()
+#endif
+
+#ifndef traceRETURN_vTaskYieldWithinAPI
+    #define traceRETURN_vTaskYieldWithinAPI()
+#endif
+
+#ifndef traceENTER_vTaskEnterCritical
+    #define traceENTER_vTaskEnterCritical()
+#endif
+
+#ifndef traceRETURN_vTaskEnterCritical
+    #define traceRETURN_vTaskEnterCritical()
+#endif
+
+#ifndef traceENTER_vTaskEnterCriticalFromISR
+    #define traceENTER_vTaskEnterCriticalFromISR()
+#endif
+
+#ifndef traceRETURN_vTaskEnterCriticalFromISR
+    #define traceRETURN_vTaskEnterCriticalFromISR( uxSavedInterruptStatus )
+#endif
+
+#ifndef traceENTER_vTaskExitCritical
+    #define traceENTER_vTaskExitCritical()
+#endif
+
+#ifndef traceRETURN_vTaskExitCritical
+    #define traceRETURN_vTaskExitCritical()
+#endif
+
+#ifndef traceENTER_vTaskExitCriticalFromISR
+    #define traceENTER_vTaskExitCriticalFromISR( uxSavedInterruptStatus )
+#endif
+
+#ifndef traceRETURN_vTaskExitCriticalFromISR
+    #define traceRETURN_vTaskExitCriticalFromISR()
+#endif
+
+#ifndef traceENTER_vTaskList
+    #define traceENTER_vTaskList( pcWriteBuffer )
+#endif
+
+#ifndef traceRETURN_vTaskList
+    #define traceRETURN_vTaskList()
+#endif
+
+#ifndef traceENTER_vTaskGetRunTimeStats
+    #define traceENTER_vTaskGetRunTimeStats( pcWriteBuffer )
+#endif
+
+#ifndef traceRETURN_vTaskGetRunTimeStats
+    #define traceRETURN_vTaskGetRunTimeStats()
+#endif
+
+#ifndef traceENTER_uxTaskResetEventItemValue
+    #define traceENTER_uxTaskResetEventItemValue()
+#endif
+
+#ifndef traceRETURN_uxTaskResetEventItemValue
+    #define traceRETURN_uxTaskResetEventItemValue( uxReturn )
+#endif
+
+#ifndef traceENTER_pvTaskIncrementMutexHeldCount
+    #define traceENTER_pvTaskIncrementMutexHeldCount()
+#endif
+
+#ifndef traceRETURN_pvTaskIncrementMutexHeldCount
+    #define traceRETURN_pvTaskIncrementMutexHeldCount( pxTCB )
+#endif
+
+#ifndef traceENTER_ulTaskGenericNotifyTake
+    #define traceENTER_ulTaskGenericNotifyTake( uxIndexToWaitOn, xClearCountOnExit, xTicksToWait )
+#endif
+
+#ifndef traceRETURN_ulTaskGenericNotifyTake
+    #define traceRETURN_ulTaskGenericNotifyTake( ulReturn )
+#endif
+
+#ifndef traceENTER_xTaskGenericNotifyWait
+    #define traceENTER_xTaskGenericNotifyWait( uxIndexToWaitOn, ulBitsToClearOnEntry, ulBitsToClearOnExit, pulNotificationValue, xTicksToWait )
+#endif
+
+#ifndef traceRETURN_xTaskGenericNotifyWait
+    #define traceRETURN_xTaskGenericNotifyWait( xReturn )
+#endif
+
+#ifndef traceENTER_xTaskGenericNotify
+    #define traceENTER_xTaskGenericNotify( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pulPreviousNotificationValue )
+#endif
+
+#ifndef traceRETURN_xTaskGenericNotify
+    #define traceRETURN_xTaskGenericNotify( xReturn )
+#endif
+
+#ifndef traceENTER_xTaskGenericNotifyFromISR
+    #define traceENTER_xTaskGenericNotifyFromISR( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pulPreviousNotificationValue, pxHigherPriorityTaskWoken )
+#endif
+
+#ifndef traceRETURN_xTaskGenericNotifyFromISR
+    #define traceRETURN_xTaskGenericNotifyFromISR( xReturn )
+#endif
+
+#ifndef traceENTER_vTaskGenericNotifyGiveFromISR
+    #define traceENTER_vTaskGenericNotifyGiveFromISR( xTaskToNotify, uxIndexToNotify, pxHigherPriorityTaskWoken )
+#endif
+
+#ifndef traceRETURN_vTaskGenericNotifyGiveFromISR
+    #define traceRETURN_vTaskGenericNotifyGiveFromISR()
+#endif
+
+#ifndef traceENTER_xTaskGenericNotifyStateClear
+    #define traceENTER_xTaskGenericNotifyStateClear( xTask, uxIndexToClear )
+#endif
+
+#ifndef traceRETURN_xTaskGenericNotifyStateClear
+    #define traceRETURN_xTaskGenericNotifyStateClear( xReturn )
+#endif
+
+#ifndef traceENTER_ulTaskGenericNotifyValueClear
+    #define traceENTER_ulTaskGenericNotifyValueClear( xTask, uxIndexToClear, ulBitsToClear )
+#endif
+
+#ifndef traceRETURN_ulTaskGenericNotifyValueClear
+    #define traceRETURN_ulTaskGenericNotifyValueClear( ulReturn )
+#endif
+
+#ifndef traceENTER_ulTaskGetRunTimeCounter
+    #define traceENTER_ulTaskGetRunTimeCounter( xTask )
+#endif
+
+#ifndef traceRETURN_ulTaskGetRunTimeCounter
+    #define traceRETURN_ulTaskGetRunTimeCounter( ulRunTimeCounter )
+#endif
+
+#ifndef traceENTER_ulTaskGetRunTimePercent
+    #define traceENTER_ulTaskGetRunTimePercent( xTask )
+#endif
+
+#ifndef traceRETURN_ulTaskGetRunTimePercent
+    #define traceRETURN_ulTaskGetRunTimePercent( ulReturn )
+#endif
+
+#ifndef traceENTER_ulTaskGetIdleRunTimeCounter
+    #define traceENTER_ulTaskGetIdleRunTimeCounter()
+#endif
+
+#ifndef traceRETURN_ulTaskGetIdleRunTimeCounter
+    #define traceRETURN_ulTaskGetIdleRunTimeCounter( ulReturn )
+#endif
+
+#ifndef traceENTER_ulTaskGetIdleRunTimePercent
+    #define traceENTER_ulTaskGetIdleRunTimePercent()
+#endif
+
+#ifndef traceRETURN_ulTaskGetIdleRunTimePercent
+    #define traceRETURN_ulTaskGetIdleRunTimePercent( ulReturn )
+#endif
+
+#ifndef traceENTER_xTaskGetMPUSettings
+    #define traceENTER_xTaskGetMPUSettings( xTask )
+#endif
+
+#ifndef traceRETURN_xTaskGetMPUSettings
+    #define traceRETURN_xTaskGetMPUSettings( xMPUSettings )
+#endif
+
+#ifndef traceENTER_xStreamBufferGenericCreate
+    #define traceENTER_xStreamBufferGenericCreate( xBufferSizeBytes, xTriggerLevelBytes, xIsMessageBuffer, pxSendCompletedCallback, pxReceiveCompletedCallback )
+#endif
+
+#ifndef traceRETURN_xStreamBufferGenericCreate
+    #define traceRETURN_xStreamBufferGenericCreate( pvAllocatedMemory )
+#endif
+
+#ifndef traceENTER_xStreamBufferGenericCreateStatic
+    #define traceENTER_xStreamBufferGenericCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, xIsMessageBuffer, pucStreamBufferStorageArea, pxStaticStreamBuffer, pxSendCompletedCallback, pxReceiveCompletedCallback )
+#endif
+
+#ifndef traceRETURN_xStreamBufferGenericCreateStatic
+    #define traceRETURN_xStreamBufferGenericCreateStatic( xReturn )
+#endif
+
+#ifndef traceENTER_xStreamBufferGetStaticBuffers
+    #define traceENTER_xStreamBufferGetStaticBuffers( xStreamBuffer, ppucStreamBufferStorageArea, ppxStaticStreamBuffer )
+#endif
+
+#ifndef traceRETURN_xStreamBufferGetStaticBuffers
+    #define traceRETURN_xStreamBufferGetStaticBuffers( xReturn )
+#endif
+
+#ifndef traceENTER_vStreamBufferDelete
+    #define traceENTER_vStreamBufferDelete( xStreamBuffer )
+#endif
+
+#ifndef traceRETURN_vStreamBufferDelete
+    #define traceRETURN_vStreamBufferDelete()
+#endif
+
+#ifndef traceENTER_xStreamBufferReset
+    #define traceENTER_xStreamBufferReset( xStreamBuffer )
+#endif
+
+#ifndef traceRETURN_xStreamBufferReset
+    #define traceRETURN_xStreamBufferReset( xReturn )
+#endif
+
+#ifndef traceENTER_xStreamBufferSetTriggerLevel
+    #define traceENTER_xStreamBufferSetTriggerLevel( xStreamBuffer, xTriggerLevel )
+#endif
+
+#ifndef traceRETURN_xStreamBufferSetTriggerLevel
+    #define traceRETURN_xStreamBufferSetTriggerLevel( xReturn )
+#endif
+
+#ifndef traceENTER_xStreamBufferSpacesAvailable
+    #define traceENTER_xStreamBufferSpacesAvailable( xStreamBuffer )
+#endif
+
+#ifndef traceRETURN_xStreamBufferSpacesAvailable
+    #define traceRETURN_xStreamBufferSpacesAvailable( xSpace )
+#endif
+
+#ifndef traceENTER_xStreamBufferBytesAvailable
+    #define traceENTER_xStreamBufferBytesAvailable( xStreamBuffer )
+#endif
+
+#ifndef traceRETURN_xStreamBufferBytesAvailable
+    #define traceRETURN_xStreamBufferBytesAvailable( xReturn )
+#endif
+
+#ifndef traceENTER_xStreamBufferSend
+    #define traceENTER_xStreamBufferSend( xStreamBuffer, pvTxData, xDataLengthBytes, xTicksToWait )
+#endif
+
+#ifndef traceRETURN_xStreamBufferSend
+    #define traceRETURN_xStreamBufferSend( xReturn )
+#endif
+
+#ifndef traceENTER_xStreamBufferSendFromISR
+    #define traceENTER_xStreamBufferSendFromISR( xStreamBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken )
+#endif
+
+#ifndef traceRETURN_xStreamBufferSendFromISR
+    #define traceRETURN_xStreamBufferSendFromISR( xReturn )
+#endif
+
+#ifndef traceENTER_xStreamBufferReceive
+    #define traceENTER_xStreamBufferReceive( xStreamBuffer, pvRxData, xBufferLengthBytes, xTicksToWait )
+#endif
+
+#ifndef traceRETURN_xStreamBufferReceive
+    #define traceRETURN_xStreamBufferReceive( xReceivedLength )
+#endif
+
+#ifndef traceENTER_xStreamBufferNextMessageLengthBytes
+    #define traceENTER_xStreamBufferNextMessageLengthBytes( xStreamBuffer )
+#endif
+
+#ifndef traceRETURN_xStreamBufferNextMessageLengthBytes
+    #define traceRETURN_xStreamBufferNextMessageLengthBytes( xReturn )
+#endif
+
+#ifndef traceENTER_xStreamBufferReceiveFromISR
+    #define traceENTER_xStreamBufferReceiveFromISR( xStreamBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken )
+#endif
+
+#ifndef traceRETURN_xStreamBufferReceiveFromISR
+    #define traceRETURN_xStreamBufferReceiveFromISR( xReceivedLength )
+#endif
+
+#ifndef traceENTER_xStreamBufferIsEmpty
+    #define traceENTER_xStreamBufferIsEmpty( xStreamBuffer )
+#endif
+
+#ifndef traceRETURN_xStreamBufferIsEmpty
+    #define traceRETURN_xStreamBufferIsEmpty( xReturn )
+#endif
+
+#ifndef traceENTER_xStreamBufferIsFull
+    #define traceENTER_xStreamBufferIsFull( xStreamBuffer )
+#endif
+
+#ifndef traceRETURN_xStreamBufferIsFull
+    #define traceRETURN_xStreamBufferIsFull( xReturn )
+#endif
+
+#ifndef traceENTER_xStreamBufferSendCompletedFromISR
+    #define traceENTER_xStreamBufferSendCompletedFromISR( xStreamBuffer, pxHigherPriorityTaskWoken )
+#endif
+
+#ifndef traceRETURN_xStreamBufferSendCompletedFromISR
+    #define traceRETURN_xStreamBufferSendCompletedFromISR( xReturn )
+#endif
+
+#ifndef traceENTER_xStreamBufferReceiveCompletedFromISR
+    #define traceENTER_xStreamBufferReceiveCompletedFromISR( xStreamBuffer, pxHigherPriorityTaskWoken )
+#endif
+
+#ifndef traceRETURN_xStreamBufferReceiveCompletedFromISR
+    #define traceRETURN_xStreamBufferReceiveCompletedFromISR( xReturn )
+#endif
+
+#ifndef traceENTER_uxStreamBufferGetStreamBufferNumber
+    #define traceENTER_uxStreamBufferGetStreamBufferNumber( xStreamBuffer )
+#endif
+
+#ifndef traceRETURN_uxStreamBufferGetStreamBufferNumber
+    #define traceRETURN_uxStreamBufferGetStreamBufferNumber( uxStreamBufferNumber )
+#endif
+
+#ifndef traceENTER_vStreamBufferSetStreamBufferNumber
+    #define traceENTER_vStreamBufferSetStreamBufferNumber( xStreamBuffer, uxStreamBufferNumber )
+#endif
+
+#ifndef traceRETURN_vStreamBufferSetStreamBufferNumber
+    #define traceRETURN_vStreamBufferSetStreamBufferNumber()
+#endif
+
+#ifndef traceENTER_ucStreamBufferGetStreamBufferType
+    #define traceENTER_ucStreamBufferGetStreamBufferType( xStreamBuffer )
+#endif
+
+#ifndef traceRETURN_ucStreamBufferGetStreamBufferType
+    #define traceRETURN_ucStreamBufferGetStreamBufferType( ucStreamBufferType )
+#endif
+
+#ifndef traceENTER_vListInitialise
+    #define traceENTER_vListInitialise( pxList )
+#endif
+
+#ifndef traceRETURN_vListInitialise
+    #define traceRETURN_vListInitialise()
+#endif
+
+#ifndef traceENTER_vListInitialiseItem
+    #define traceENTER_vListInitialiseItem( pxItem )
+#endif
+
+#ifndef traceRETURN_vListInitialiseItem
+    #define traceRETURN_vListInitialiseItem()
+#endif
+
+#ifndef traceENTER_vListInsertEnd
+    #define traceENTER_vListInsertEnd( pxList, pxNewListItem )
+#endif
+
+#ifndef traceRETURN_vListInsertEnd
+    #define traceRETURN_vListInsertEnd()
+#endif
+
+#ifndef traceENTER_vListInsert
+    #define traceENTER_vListInsert( pxList, pxNewListItem )
+#endif
+
+#ifndef traceRETURN_vListInsert
+    #define traceRETURN_vListInsert()
+#endif
+
+#ifndef traceENTER_uxListRemove
+    #define traceENTER_uxListRemove( pxItemToRemove )
+#endif
+
+#ifndef traceRETURN_uxListRemove
+    #define traceRETURN_uxListRemove( uxNumberOfItems )
+#endif
+
+#ifndef traceENTER_xCoRoutineCreate
+    #define traceENTER_xCoRoutineCreate( pxCoRoutineCode, uxPriority, uxIndex )
+#endif
+
+#ifndef traceRETURN_xCoRoutineCreate
+    #define traceRETURN_xCoRoutineCreate( xReturn )
+#endif
+
+#ifndef traceENTER_vCoRoutineAddToDelayedList
+    #define traceENTER_vCoRoutineAddToDelayedList( xTicksToDelay, pxEventList )
+#endif
+
+#ifndef traceRETURN_vCoRoutineAddToDelayedList
+    #define traceRETURN_vCoRoutineAddToDelayedList()
+#endif
+
+#ifndef traceENTER_vCoRoutineSchedule
+    #define traceENTER_vCoRoutineSchedule()
+#endif
+
+#ifndef traceRETURN_vCoRoutineSchedule
+    #define traceRETURN_vCoRoutineSchedule()
+#endif
+
+#ifndef traceENTER_xCoRoutineRemoveFromEventList
+    #define traceENTER_xCoRoutineRemoveFromEventList( pxEventList )
+#endif
+
+#ifndef traceRETURN_xCoRoutineRemoveFromEventList
+    #define traceRETURN_xCoRoutineRemoveFromEventList( xReturn )
+#endif
+
 #ifndef configGENERATE_RUN_TIME_STATS
     #define configGENERATE_RUN_TIME_STATS    0
 #endif
diff --git a/list.c b/list.c
index 649c4c302..ab5bf5653 100644
--- a/list.c
+++ b/list.c
@@ -49,6 +49,8 @@
 
 void vListInitialise( List_t * const pxList )
 {
+    traceENTER_vListInitialise( pxList );
+
     /* The list structure contains a list item which is used to mark the
      * end of the list.  To initialise the list the list end is inserted
      * as the only list entry. */
@@ -80,11 +82,15 @@ void vListInitialise( List_t * const pxList )
      * configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
     listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList );
     listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList );
+
+    traceRETURN_vListInitialise();
 }
 /*-----------------------------------------------------------*/
 
 void vListInitialiseItem( ListItem_t * const pxItem )
 {
+    traceENTER_vListInitialiseItem( pxItem );
+
     /* Make sure the list item is not recorded as being on a list. */
     pxItem->pxContainer = NULL;
 
@@ -92,6 +98,8 @@ void vListInitialiseItem( ListItem_t * const pxItem )
      * configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
     listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
     listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
+
+    traceRETURN_vListInitialiseItem();
 }
 /*-----------------------------------------------------------*/
 
@@ -100,6 +108,8 @@ void vListInsertEnd( List_t * const pxList,
 {
     ListItem_t * const pxIndex = pxList->pxIndex;
 
+    traceENTER_vListInsertEnd( pxList, pxNewListItem );
+
     /* Only effective when configASSERT() is also defined, these tests may catch
      * the list data structures being overwritten in memory.  They will not catch
      * data errors caused by incorrect configuration or use of FreeRTOS. */
@@ -122,6 +132,8 @@ void vListInsertEnd( List_t * const pxList,
     pxNewListItem->pxContainer = pxList;
 
     ( pxList->uxNumberOfItems )++;
+
+    traceRETURN_vListInsertEnd();
 }
 /*-----------------------------------------------------------*/
 
@@ -131,6 +143,8 @@ void vListInsert( List_t * const pxList,
     ListItem_t * pxIterator;
     const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;
 
+    traceENTER_vListInsert( pxList, pxNewListItem );
+
     /* Only effective when configASSERT() is also defined, these tests may catch
      * the list data structures being overwritten in memory.  They will not catch
      * data errors caused by incorrect configuration or use of FreeRTOS. */
@@ -193,15 +207,21 @@ void vListInsert( List_t * const pxList,
     pxNewListItem->pxContainer = pxList;
 
     ( pxList->uxNumberOfItems )++;
+
+    traceRETURN_vListInsert();
 }
 /*-----------------------------------------------------------*/
 
 UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )
 {
-/* The list item knows which list it is in.  Obtain the list from the list
- * item. */
+    /* The list item knows which list it is in.  Obtain the list from the list
+     * item. */
     List_t * const pxList = pxItemToRemove->pxContainer;
 
+    traceENTER_uxListRemove( pxItemToRemove );
+
+
+
     pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;
     pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;
 
@@ -221,6 +241,8 @@ UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )
     pxItemToRemove->pxContainer = NULL;
     ( pxList->uxNumberOfItems )--;
 
+    traceRETURN_uxListRemove( pxList->uxNumberOfItems );
+
     return pxList->uxNumberOfItems;
 }
 /*-----------------------------------------------------------*/
diff --git a/queue.c b/queue.c
index 9d300f861..91b9a0d67 100644
--- a/queue.c
+++ b/queue.c
@@ -303,6 +303,8 @@ BaseType_t xQueueGenericReset( QueueHandle_t xQueue,
     BaseType_t xReturn = pdPASS;
     Queue_t * const pxQueue = xQueue;
 
+    traceENTER_xQueueGenericReset( xQueue, xNewQueue );
+
     configASSERT( pxQueue );
 
     if( ( pxQueue != NULL ) &&
@@ -360,6 +362,8 @@ BaseType_t xQueueGenericReset( QueueHandle_t xQueue,
 
     /* A value is returned for calling semantic consistency with previous
      * versions. */
+    traceRETURN_xQueueGenericReset( xReturn );
+
     return xReturn;
 }
 /*-----------------------------------------------------------*/
@@ -374,6 +378,8 @@ BaseType_t xQueueGenericReset( QueueHandle_t xQueue,
     {
         Queue_t * pxNewQueue = NULL;
 
+        traceENTER_xQueueGenericCreateStatic( uxQueueLength, uxItemSize, pucQueueStorage, pxStaticQueue, ucQueueType );
+
         /* The StaticQueue_t structure and the queue storage area must be
          * supplied. */
         configASSERT( pxStaticQueue );
@@ -421,6 +427,8 @@ BaseType_t xQueueGenericReset( QueueHandle_t xQueue,
             mtCOVERAGE_TEST_MARKER();
         }
 
+        traceRETURN_xQueueGenericCreateStatic( pxNewQueue );
+
         return pxNewQueue;
     }
 
@@ -436,6 +444,8 @@ BaseType_t xQueueGenericReset( QueueHandle_t xQueue,
         BaseType_t xReturn;
         Queue_t * const pxQueue = xQueue;
 
+        traceENTER_xQueueGenericGetStaticBuffers( xQueue, ppucQueueStorage, ppxStaticQueue );
+
         configASSERT( pxQueue );
         configASSERT( ppxStaticQueue );
 
@@ -470,6 +480,8 @@ BaseType_t xQueueGenericReset( QueueHandle_t xQueue,
         }
         #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
 
+        traceRETURN_xQueueGenericGetStaticBuffers( xReturn );
+
         return xReturn;
     }
 
@@ -486,6 +498,8 @@ BaseType_t xQueueGenericReset( QueueHandle_t xQueue,
         size_t xQueueSizeInBytes;
         uint8_t * pucQueueStorage;
 
+        traceENTER_xQueueGenericCreate( uxQueueLength, uxItemSize, ucQueueType );
+
         if( ( uxQueueLength > ( UBaseType_t ) 0 ) &&
             /* Check for multiplication overflow. */
             ( ( SIZE_MAX / uxQueueLength ) >= uxItemSize ) &&
@@ -538,6 +552,8 @@ BaseType_t xQueueGenericReset( QueueHandle_t xQueue,
             mtCOVERAGE_TEST_MARKER();
         }
 
+        traceRETURN_xQueueGenericCreate( pxNewQueue );
+
         return pxNewQueue;
     }
 
@@ -627,9 +643,13 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength,
         QueueHandle_t xNewQueue;
         const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
 
+        traceENTER_xQueueCreateMutex( ucQueueType );
+
         xNewQueue = xQueueGenericCreate( uxMutexLength, uxMutexSize, ucQueueType );
         prvInitialiseMutex( ( Queue_t * ) xNewQueue );
 
+        traceRETURN_xQueueCreateMutex( xNewQueue );
+
         return xNewQueue;
     }
 
@@ -644,6 +664,8 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength,
         QueueHandle_t xNewQueue;
         const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
 
+        traceENTER_xQueueCreateMutexStatic( ucQueueType, pxStaticQueue );
+
         /* Prevent compiler warnings about unused parameters if
          * configUSE_TRACE_FACILITY does not equal 1. */
         ( void ) ucQueueType;
@@ -651,6 +673,8 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength,
         xNewQueue = xQueueGenericCreateStatic( uxMutexLength, uxMutexSize, NULL, pxStaticQueue, ucQueueType );
         prvInitialiseMutex( ( Queue_t * ) xNewQueue );
 
+        traceRETURN_xQueueCreateMutexStatic( xNewQueue );
+
         return xNewQueue;
     }
 
@@ -664,6 +688,8 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength,
         TaskHandle_t pxReturn;
         Queue_t * const pxSemaphore = ( Queue_t * ) xSemaphore;
 
+        traceENTER_xQueueGetMutexHolder( xSemaphore );
+
         configASSERT( xSemaphore );
 
         /* This function is called by xSemaphoreGetMutexHolder(), and should not
@@ -684,6 +710,8 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength,
         }
         taskEXIT_CRITICAL();
 
+        traceRETURN_xQueueGetMutexHolder( pxReturn );
+
         return pxReturn;
     } /*lint !e818 xSemaphore cannot be a pointer to const because it is a typedef. */
 
@@ -696,6 +724,8 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength,
     {
         TaskHandle_t pxReturn;
 
+        traceENTER_xQueueGetMutexHolderFromISR( xSemaphore );
+
         configASSERT( xSemaphore );
 
         /* Mutexes cannot be used in interrupt service routines, so the mutex
@@ -710,6 +740,8 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength,
             pxReturn = NULL;
         }
 
+        traceRETURN_xQueueGetMutexHolderFromISR( pxReturn );
+
         return pxReturn;
     } /*lint !e818 xSemaphore cannot be a pointer to const because it is a typedef. */
 
@@ -723,6 +755,8 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength,
         BaseType_t xReturn;
         Queue_t * const pxMutex = ( Queue_t * ) xMutex;
 
+        traceENTER_xQueueGiveMutexRecursive( xMutex );
+
         configASSERT( pxMutex );
 
         /* If this is the task that holds the mutex then xMutexHolder will not
@@ -765,6 +799,8 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength,
             traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex );
         }
 
+        traceRETURN_xQueueGiveMutexRecursive( xReturn );
+
         return xReturn;
     }
 
@@ -779,6 +815,8 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength,
         BaseType_t xReturn;
         Queue_t * const pxMutex = ( Queue_t * ) xMutex;
 
+        traceENTER_xQueueTakeMutexRecursive( xMutex, xTicksToWait );
+
         configASSERT( pxMutex );
 
         /* Comments regarding mutual exclusion as per those within
@@ -808,6 +846,8 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength,
             }
         }
 
+        traceRETURN_xQueueTakeMutexRecursive( xReturn );
+
         return xReturn;
     }
 
@@ -822,6 +862,8 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength,
     {
         QueueHandle_t xHandle = NULL;
 
+        traceENTER_xQueueCreateCountingSemaphoreStatic( uxMaxCount, uxInitialCount, pxStaticQueue );
+
         if( ( uxMaxCount != 0 ) &&
             ( uxInitialCount <= uxMaxCount ) )
         {
@@ -844,6 +886,8 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength,
             mtCOVERAGE_TEST_MARKER();
         }
 
+        traceRETURN_xQueueCreateCountingSemaphoreStatic( xHandle );
+
         return xHandle;
     }
 
@@ -857,6 +901,8 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength,
     {
         QueueHandle_t xHandle = NULL;
 
+        traceENTER_xQueueCreateCountingSemaphore( uxMaxCount, uxInitialCount );
+
         if( ( uxMaxCount != 0 ) &&
             ( uxInitialCount <= uxMaxCount ) )
         {
@@ -879,6 +925,8 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength,
             mtCOVERAGE_TEST_MARKER();
         }
 
+        traceRETURN_xQueueCreateCountingSemaphore( xHandle );
+
         return xHandle;
     }
 
@@ -894,6 +942,8 @@ BaseType_t xQueueGenericSend( QueueHandle_t xQueue,
     TimeOut_t xTimeOut;
     Queue_t * const pxQueue = xQueue;
 
+    traceENTER_xQueueGenericSend( xQueue, pvItemToQueue, xTicksToWait, xCopyPosition );
+
     configASSERT( pxQueue );
     configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
     configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
@@ -1015,6 +1065,9 @@ BaseType_t xQueueGenericSend( QueueHandle_t xQueue,
                 #endif /* configUSE_QUEUE_SETS */
 
                 taskEXIT_CRITICAL();
+
+                traceRETURN_xQueueGenericSend( pdPASS );
+
                 return pdPASS;
             }
             else
@@ -1028,6 +1081,8 @@ BaseType_t xQueueGenericSend( QueueHandle_t xQueue,
                     /* Return to the original privilege level before exiting
                      * the function. */
                     traceQUEUE_SEND_FAILED( pxQueue );
+                    traceRETURN_xQueueGenericSend( errQUEUE_FULL );
+
                     return errQUEUE_FULL;
                 }
                 else if( xEntryTimeSet == pdFALSE )
@@ -1099,6 +1154,8 @@ BaseType_t xQueueGenericSend( QueueHandle_t xQueue,
             ( void ) xTaskResumeAll();
 
             traceQUEUE_SEND_FAILED( pxQueue );
+            traceRETURN_xQueueGenericSend( errQUEUE_FULL );
+
             return errQUEUE_FULL;
         }
     } /*lint -restore */
@@ -1114,6 +1171,8 @@ BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue,
     UBaseType_t uxSavedInterruptStatus;
     Queue_t * const pxQueue = xQueue;
 
+    traceENTER_xQueueGenericSendFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken, xCopyPosition );
+
     configASSERT( pxQueue );
     configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
     configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
@@ -1266,6 +1325,8 @@ BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue,
     }
     taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
 
+    traceRETURN_xQueueGenericSendFromISR( xReturn );
+
     return xReturn;
 }
 /*-----------------------------------------------------------*/
@@ -1277,6 +1338,8 @@ BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue,
     UBaseType_t uxSavedInterruptStatus;
     Queue_t * const pxQueue = xQueue;
 
+    traceENTER_xQueueGiveFromISR( xQueue, pxHigherPriorityTaskWoken );
+
     /* Similar to xQueueGenericSendFromISR() but used with semaphores where the
      * item size is 0.  Don't directly wake a task that was blocked on a queue
      * read, instead return a flag to say whether a context switch is required or
@@ -1432,6 +1495,8 @@ BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue,
     }
     taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
 
+    traceRETURN_xQueueGiveFromISR( xReturn );
+
     return xReturn;
 }
 /*-----------------------------------------------------------*/
@@ -1444,6 +1509,8 @@ BaseType_t xQueueReceive( QueueHandle_t xQueue,
     TimeOut_t xTimeOut;
     Queue_t * const pxQueue = xQueue;
 
+    traceENTER_xQueueReceive( xQueue, pvBuffer, xTicksToWait );
+
     /* Check the pointer is not NULL. */
     configASSERT( ( pxQueue ) );
 
@@ -1496,6 +1563,9 @@ BaseType_t xQueueReceive( QueueHandle_t xQueue,
                 }
 
                 taskEXIT_CRITICAL();
+
+                traceRETURN_xQueueReceive( pdPASS );
+
                 return pdPASS;
             }
             else
@@ -1505,7 +1575,10 @@ BaseType_t xQueueReceive( QueueHandle_t xQueue,
                     /* The queue was empty and no block time is specified (or
                      * the block time has expired) so leave now. */
                     taskEXIT_CRITICAL();
+
                     traceQUEUE_RECEIVE_FAILED( pxQueue );
+                    traceRETURN_xQueueReceive( errQUEUE_EMPTY );
+
                     return errQUEUE_EMPTY;
                 }
                 else if( xEntryTimeSet == pdFALSE )
@@ -1576,6 +1649,8 @@ BaseType_t xQueueReceive( QueueHandle_t xQueue,
             if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
             {
                 traceQUEUE_RECEIVE_FAILED( pxQueue );
+                traceRETURN_xQueueReceive( errQUEUE_EMPTY );
+
                 return errQUEUE_EMPTY;
             }
             else
@@ -1598,6 +1673,8 @@ BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue,
         BaseType_t xInheritanceOccurred = pdFALSE;
     #endif
 
+    traceENTER_xQueueSemaphoreTake( xQueue, xTicksToWait );
+
     /* Check the queue pointer is not NULL. */
     configASSERT( ( pxQueue ) );
 
@@ -1667,6 +1744,9 @@ BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue,
                 }
 
                 taskEXIT_CRITICAL();
+
+                traceRETURN_xQueueSemaphoreTake( pdPASS );
+
                 return pdPASS;
             }
             else
@@ -1676,7 +1756,10 @@ BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue,
                     /* The semaphore count was 0 and no block time is specified
                      * (or the block time has expired) so exit now. */
                     taskEXIT_CRITICAL();
+
                     traceQUEUE_RECEIVE_FAILED( pxQueue );
+                    traceRETURN_xQueueSemaphoreTake( errQUEUE_EMPTY );
+
                     return errQUEUE_EMPTY;
                 }
                 else if( xEntryTimeSet == pdFALSE )
@@ -1794,6 +1877,8 @@ BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue,
                 #endif /* configUSE_MUTEXES */
 
                 traceQUEUE_RECEIVE_FAILED( pxQueue );
+                traceRETURN_xQueueSemaphoreTake( errQUEUE_EMPTY );
+
                 return errQUEUE_EMPTY;
             }
             else
@@ -1814,6 +1899,8 @@ BaseType_t xQueuePeek( QueueHandle_t xQueue,
     int8_t * pcOriginalReadPosition;
     Queue_t * const pxQueue = xQueue;
 
+    traceENTER_xQueuePeek( xQueue, pvBuffer, xTicksToWait );
+
     /* Check the pointer is not NULL. */
     configASSERT( ( pxQueue ) );
 
@@ -1872,6 +1959,9 @@ BaseType_t xQueuePeek( QueueHandle_t xQueue,
                 }
 
                 taskEXIT_CRITICAL();
+
+                traceRETURN_xQueuePeek( pdPASS );
+
                 return pdPASS;
             }
             else
@@ -1881,7 +1971,10 @@ BaseType_t xQueuePeek( QueueHandle_t xQueue,
                     /* The queue was empty and no block time is specified (or
                      * the block time has expired) so leave now. */
                     taskEXIT_CRITICAL();
+
                     traceQUEUE_PEEK_FAILED( pxQueue );
+                    traceRETURN_xQueuePeek( errQUEUE_EMPTY );
+
                     return errQUEUE_EMPTY;
                 }
                 else if( xEntryTimeSet == pdFALSE )
@@ -1953,6 +2046,8 @@ BaseType_t xQueuePeek( QueueHandle_t xQueue,
             if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
             {
                 traceQUEUE_PEEK_FAILED( pxQueue );
+                traceRETURN_xQueuePeek( errQUEUE_EMPTY );
+
                 return errQUEUE_EMPTY;
             }
             else
@@ -1972,6 +2067,8 @@ BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue,
     UBaseType_t uxSavedInterruptStatus;
     Queue_t * const pxQueue = xQueue;
 
+    traceENTER_xQueueReceiveFromISR( xQueue, pvBuffer, pxHigherPriorityTaskWoken );
+
     configASSERT( pxQueue );
     configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
 
@@ -2053,6 +2150,8 @@ BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue,
     }
     taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
 
+    traceRETURN_xQueueReceiveFromISR( xReturn );
+
     return xReturn;
 }
 /*-----------------------------------------------------------*/
@@ -2065,6 +2164,8 @@ BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue,
     int8_t * pcOriginalReadPosition;
     Queue_t * const pxQueue = xQueue;
 
+    traceENTER_xQueuePeekFromISR( xQueue, pvBuffer );
+
     configASSERT( pxQueue );
     configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
     configASSERT( pxQueue->uxItemSize != 0 ); /* Can't peek a semaphore. */
@@ -2108,6 +2209,8 @@ BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue,
     }
     taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
 
+    traceRETURN_xQueuePeekFromISR( xReturn );
+
     return xReturn;
 }
 /*-----------------------------------------------------------*/
@@ -2116,6 +2219,8 @@ UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue )
 {
     UBaseType_t uxReturn;
 
+    traceENTER_uxQueueMessagesWaiting( xQueue );
+
     configASSERT( xQueue );
 
     taskENTER_CRITICAL();
@@ -2124,6 +2229,8 @@ UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue )
     }
     taskEXIT_CRITICAL();
 
+    traceRETURN_uxQueueMessagesWaiting( uxReturn );
+
     return uxReturn;
 } /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
 /*-----------------------------------------------------------*/
@@ -2133,6 +2240,8 @@ UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue )
     UBaseType_t uxReturn;
     Queue_t * const pxQueue = xQueue;
 
+    traceENTER_uxQueueSpacesAvailable( xQueue );
+
     configASSERT( pxQueue );
 
     taskENTER_CRITICAL();
@@ -2141,6 +2250,8 @@ UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue )
     }
     taskEXIT_CRITICAL();
 
+    traceRETURN_uxQueueSpacesAvailable( uxReturn );
+
     return uxReturn;
 } /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
 /*-----------------------------------------------------------*/
@@ -2150,9 +2261,13 @@ UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue )
     UBaseType_t uxReturn;
     Queue_t * const pxQueue = xQueue;
 
+    traceENTER_uxQueueMessagesWaitingFromISR( xQueue );
+
     configASSERT( pxQueue );
     uxReturn = pxQueue->uxMessagesWaiting;
 
+    traceRETURN_uxQueueMessagesWaitingFromISR( uxReturn );
+
     return uxReturn;
 } /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
 /*-----------------------------------------------------------*/
@@ -2161,6 +2276,8 @@ void vQueueDelete( QueueHandle_t xQueue )
 {
     Queue_t * const pxQueue = xQueue;
 
+    traceENTER_vQueueDelete( xQueue );
+
     configASSERT( pxQueue );
     traceQUEUE_DELETE( pxQueue );
 
@@ -2196,6 +2313,8 @@ void vQueueDelete( QueueHandle_t xQueue )
         ( void ) pxQueue;
     }
     #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+
+    traceRETURN_vQueueDelete();
 }
 /*-----------------------------------------------------------*/
 
@@ -2203,6 +2322,10 @@ void vQueueDelete( QueueHandle_t xQueue )
 
     UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue )
     {
+        traceENTER_uxQueueGetQueueNumber( xQueue );
+
+        traceRETURN_uxQueueGetQueueNumber( ( ( Queue_t * ) xQueue )->uxQueueNumber );
+
         return ( ( Queue_t * ) xQueue )->uxQueueNumber;
     }
 
@@ -2214,7 +2337,11 @@ void vQueueDelete( QueueHandle_t xQueue )
     void vQueueSetQueueNumber( QueueHandle_t xQueue,
                                UBaseType_t uxQueueNumber )
     {
+        traceENTER_vQueueSetQueueNumber( xQueue, uxQueueNumber );
+
         ( ( Queue_t * ) xQueue )->uxQueueNumber = uxQueueNumber;
+
+        traceRETURN_vQueueSetQueueNumber();
     }
 
 #endif /* configUSE_TRACE_FACILITY */
@@ -2224,6 +2351,10 @@ void vQueueDelete( QueueHandle_t xQueue )
 
     uint8_t ucQueueGetQueueType( QueueHandle_t xQueue )
     {
+        traceENTER_ucQueueGetQueueType( xQueue );
+
+        traceRETURN_ucQueueGetQueueType( ( ( Queue_t * ) xQueue )->ucQueueType );
+
         return ( ( Queue_t * ) xQueue )->ucQueueType;
     }
 
@@ -2232,12 +2363,20 @@ void vQueueDelete( QueueHandle_t xQueue )
 
 UBaseType_t uxQueueGetQueueItemSize( QueueHandle_t xQueue ) /* PRIVILEGED_FUNCTION */
 {
+    traceENTER_uxQueueGetQueueItemSize( xQueue );
+
+    traceRETURN_uxQueueGetQueueItemSize( ( ( Queue_t * ) xQueue )->uxItemSize );
+
     return ( ( Queue_t * ) xQueue )->uxItemSize;
 }
 /*-----------------------------------------------------------*/
 
 UBaseType_t uxQueueGetQueueLength( QueueHandle_t xQueue ) /* PRIVILEGED_FUNCTION */
 {
+    traceENTER_uxQueueGetQueueLength( xQueue );
+
+    traceRETURN_uxQueueGetQueueLength( ( ( Queue_t * ) xQueue )->uxLength );
+
     return ( ( Queue_t * ) xQueue )->uxLength;
 }
 /*-----------------------------------------------------------*/
@@ -2519,6 +2658,8 @@ BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue )
     BaseType_t xReturn;
     Queue_t * const pxQueue = xQueue;
 
+    traceENTER_xQueueIsQueueEmptyFromISR( xQueue );
+
     configASSERT( pxQueue );
 
     if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
@@ -2530,6 +2671,8 @@ BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue )
         xReturn = pdFALSE;
     }
 
+    traceRETURN_xQueueIsQueueEmptyFromISR( xReturn );
+
     return xReturn;
 } /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
 /*-----------------------------------------------------------*/
@@ -2560,6 +2703,8 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )
     BaseType_t xReturn;
     Queue_t * const pxQueue = xQueue;
 
+    traceENTER_xQueueIsQueueFullFromISR( xQueue );
+
     configASSERT( pxQueue );
 
     if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
@@ -2571,6 +2716,8 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )
         xReturn = pdFALSE;
     }
 
+    traceRETURN_xQueueIsQueueFullFromISR( xReturn );
+
     return xReturn;
 } /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
 /*-----------------------------------------------------------*/
@@ -2584,6 +2731,8 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )
         BaseType_t xReturn;
         Queue_t * const pxQueue = xQueue;
 
+        traceENTER_xQueueCRSend( xQueue, pvItemToQueue, xTicksToWait );
+
         /* If the queue is already full we may have to block.  A critical section
          * is required to prevent an interrupt removing something from the queue
          * between the check to see if the queue is full and blocking on the queue. */
@@ -2648,6 +2797,8 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )
         }
         portENABLE_INTERRUPTS();
 
+        traceRETURN_xQueueCRSend( xReturn );
+
         return xReturn;
     }
 
@@ -2663,6 +2814,8 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )
         BaseType_t xReturn;
         Queue_t * const pxQueue = xQueue;
 
+        traceENTER_xQueueCRReceive( xQueue, pvBuffer, xTicksToWait );
+
         /* If the queue is already empty we may have to block.  A critical section
          * is required to prevent an interrupt adding something to the queue
          * between the check to see if the queue is empty and blocking on the queue. */
@@ -2742,6 +2895,8 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )
         }
         portENABLE_INTERRUPTS();
 
+        traceRETURN_xQueueCRReceive( xReturn );
+
         return xReturn;
     }
 
@@ -2756,6 +2911,8 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )
     {
         Queue_t * const pxQueue = xQueue;
 
+        traceENTER_xQueueCRSendFromISR( xQueue, pvItemToQueue, xCoRoutinePreviouslyWoken );
+
         /* Cannot block within an ISR so if there is no space on the queue then
          * exit without doing anything. */
         if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )
@@ -2792,6 +2949,8 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )
             mtCOVERAGE_TEST_MARKER();
         }
 
+        traceRETURN_xQueueCRSendFromISR( xCoRoutinePreviouslyWoken );
+
         return xCoRoutinePreviouslyWoken;
     }
 
@@ -2807,6 +2966,8 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )
         BaseType_t xReturn;
         Queue_t * const pxQueue = xQueue;
 
+        traceENTER_xQueueCRReceiveFromISR( xQueue, pvBuffer, pxCoRoutineWoken );
+
         /* We cannot block from an ISR, so check there is data available. If
          * not then just leave without doing anything. */
         if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
@@ -2856,6 +3017,8 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )
             xReturn = pdFAIL;
         }
 
+        traceRETURN_xQueueCRReceiveFromISR( xReturn );
+
         return xReturn;
     }
 
@@ -2870,6 +3033,8 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )
         UBaseType_t ux;
         QueueRegistryItem_t * pxEntryToWrite = NULL;
 
+        traceENTER_vQueueAddToRegistry( xQueue, pcQueueName );
+
         configASSERT( xQueue );
 
         if( pcQueueName != NULL )
@@ -2904,6 +3069,8 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )
 
             traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName );
         }
+
+        traceRETURN_vQueueAddToRegistry();
     }
 
 #endif /* configQUEUE_REGISTRY_SIZE */
@@ -2916,6 +3083,8 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )
         UBaseType_t ux;
         const char * pcReturn = NULL; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
 
+        traceENTER_pcQueueGetName( xQueue );
+
         configASSERT( xQueue );
 
         /* Note there is nothing here to protect against another task adding or
@@ -2934,6 +3103,8 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )
             }
         }
 
+        traceRETURN_pcQueueGetName( pcReturn );
+
         return pcReturn;
     } /*lint !e818 xQueue cannot be a pointer to const because it is a typedef. */
 
@@ -2946,6 +3117,8 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )
     {
         UBaseType_t ux;
 
+        traceENTER_vQueueUnregisterQueue( xQueue );
+
         configASSERT( xQueue );
 
         /* See if the handle of the queue being unregistered in actually in the
@@ -2968,6 +3141,8 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )
                 mtCOVERAGE_TEST_MARKER();
             }
         }
+
+        traceRETURN_vQueueUnregisterQueue();
     } /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
 
 #endif /* configQUEUE_REGISTRY_SIZE */
@@ -2981,6 +3156,8 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )
     {
         Queue_t * const pxQueue = xQueue;
 
+        traceENTER_vQueueWaitForMessageRestricted( xQueue, xTicksToWait, xWaitIndefinitely );
+
         /* This function should not be called by application code hence the
          * 'Restricted' in its name.  It is not part of the public API.  It is
          * designed for use by kernel code, and has special calling requirements.
@@ -3008,6 +3185,8 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )
         }
 
         prvUnlockQueue( pxQueue );
+
+        traceRETURN_vQueueWaitForMessageRestricted();
     }
 
 #endif /* configUSE_TIMERS */
@@ -3019,8 +3198,12 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )
     {
         QueueSetHandle_t pxQueue;
 
+        traceENTER_xQueueCreateSet( uxEventQueueLength );
+
         pxQueue = xQueueGenericCreate( uxEventQueueLength, ( UBaseType_t ) sizeof( Queue_t * ), queueQUEUE_TYPE_SET );
 
+        traceRETURN_xQueueCreateSet( pxQueue );
+
         return pxQueue;
     }
 
@@ -3034,6 +3217,8 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )
     {
         BaseType_t xReturn;
 
+        traceENTER_xQueueAddToSet( xQueueOrSemaphore, xQueueSet );
+
         taskENTER_CRITICAL();
         {
             if( ( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer != NULL )
@@ -3055,6 +3240,8 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )
         }
         taskEXIT_CRITICAL();
 
+        traceRETURN_xQueueAddToSet( xReturn );
+
         return xReturn;
     }
 
@@ -3069,6 +3256,8 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )
         BaseType_t xReturn;
         Queue_t * const pxQueueOrSemaphore = ( Queue_t * ) xQueueOrSemaphore;
 
+        traceENTER_xQueueRemoveFromSet( xQueueOrSemaphore, xQueueSet );
+
         if( pxQueueOrSemaphore->pxQueueSetContainer != xQueueSet )
         {
             /* The queue was not a member of the set. */
@@ -3092,6 +3281,8 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )
             xReturn = pdPASS;
         }
 
+        traceRETURN_xQueueRemoveFromSet( xReturn );
+
         return xReturn;
     } /*lint !e818 xQueueSet could not be declared as pointing to const as it is a typedef. */
 
@@ -3105,7 +3296,12 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )
     {
         QueueSetMemberHandle_t xReturn = NULL;
 
+        traceENTER_xQueueSelectFromSet( xQueueSet, xTicksToWait );
+
         ( void ) xQueueReceive( ( QueueHandle_t ) xQueueSet, &xReturn, xTicksToWait ); /*lint !e961 Casting from one typedef to another is not redundant. */
+
+        traceRETURN_xQueueSelectFromSet( xReturn );
+
         return xReturn;
     }
 
@@ -3118,7 +3314,12 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )
     {
         QueueSetMemberHandle_t xReturn = NULL;
 
+        traceENTER_xQueueSelectFromSetFromISR( xQueueSet );
+
         ( void ) xQueueReceiveFromISR( ( QueueHandle_t ) xQueueSet, &xReturn, NULL ); /*lint !e961 Casting from one typedef to another is not redundant. */
+
+        traceRETURN_xQueueSelectFromSetFromISR( xReturn );
+
         return xReturn;
     }
 
diff --git a/stream_buffer.c b/stream_buffer.c
index 7c91ec316..32aa8e4f2 100644
--- a/stream_buffer.c
+++ b/stream_buffer.c
@@ -326,6 +326,8 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
         void * pvAllocatedMemory;
         uint8_t ucFlags;
 
+        traceENTER_xStreamBufferGenericCreate( xBufferSizeBytes, xTriggerLevelBytes, xIsMessageBuffer, pxSendCompletedCallback, pxReceiveCompletedCallback );
+
         /* In case the stream buffer is going to be used as a message buffer
          * (that is, it will hold discrete messages with a little meta data that
          * says how big the next message is) check the buffer will be large enough
@@ -387,6 +389,8 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
             traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer );
         }
 
+        traceRETURN_xStreamBufferGenericCreate( pvAllocatedMemory );
+
         return ( StreamBufferHandle_t ) pvAllocatedMemory; /*lint !e9087 !e826 Safe cast as allocated memory is aligned. */
     }
 #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
@@ -406,6 +410,8 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
         StreamBufferHandle_t xReturn;
         uint8_t ucFlags;
 
+        traceENTER_xStreamBufferGenericCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, xIsMessageBuffer, pucStreamBufferStorageArea, pxStaticStreamBuffer, pxSendCompletedCallback, pxReceiveCompletedCallback );
+
         configASSERT( pucStreamBufferStorageArea );
         configASSERT( pxStaticStreamBuffer );
         configASSERT( xTriggerLevelBytes <= xBufferSizeBytes );
@@ -468,6 +474,8 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
             traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer );
         }
 
+        traceRETURN_xStreamBufferGenericCreateStatic( xReturn );
+
         return xReturn;
     }
 #endif /* ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
@@ -481,6 +489,8 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
         BaseType_t xReturn;
         StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
 
+        traceENTER_xStreamBufferGetStaticBuffers( xStreamBuffer, ppucStreamBufferStorageArea, ppxStaticStreamBuffer );
+
         configASSERT( pxStreamBuffer );
         configASSERT( ppucStreamBufferStorageArea );
         configASSERT( ppxStaticStreamBuffer );
@@ -496,6 +506,8 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
             xReturn = pdFALSE;
         }
 
+        traceRETURN_xStreamBufferGetStaticBuffers( xReturn );
+
         return xReturn;
     }
 #endif /* configSUPPORT_STATIC_ALLOCATION */
@@ -505,6 +517,8 @@ void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer )
 {
     StreamBuffer_t * pxStreamBuffer = xStreamBuffer;
 
+    traceENTER_vStreamBufferDelete( xStreamBuffer );
+
     configASSERT( pxStreamBuffer );
 
     traceSTREAM_BUFFER_DELETE( xStreamBuffer );
@@ -531,6 +545,8 @@ void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer )
          * freed - just scrub the structure so future use will assert. */
         ( void ) memset( pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) );
     }
+
+    traceRETURN_vStreamBufferDelete();
 }
 /*-----------------------------------------------------------*/
 
@@ -544,6 +560,8 @@ BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer )
         UBaseType_t uxStreamBufferNumber;
     #endif
 
+    traceENTER_xStreamBufferReset( xStreamBuffer );
+
     configASSERT( pxStreamBuffer );
 
     #if ( configUSE_TRACE_FACILITY == 1 )
@@ -587,6 +605,8 @@ BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer )
     }
     taskEXIT_CRITICAL();
 
+    traceRETURN_xStreamBufferReset( xReturn );
+
     return xReturn;
 }
 /*-----------------------------------------------------------*/
@@ -597,6 +617,8 @@ BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
     StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
     BaseType_t xReturn;
 
+    traceENTER_xStreamBufferSetTriggerLevel( xStreamBuffer, xTriggerLevel );
+
     configASSERT( pxStreamBuffer );
 
     /* It is not valid for the trigger level to be 0. */
@@ -617,6 +639,8 @@ BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
         xReturn = pdFALSE;
     }
 
+    traceRETURN_xStreamBufferSetTriggerLevel( xReturn );
+
     return xReturn;
 }
 /*-----------------------------------------------------------*/
@@ -627,6 +651,8 @@ size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer )
     size_t xSpace;
     size_t xOriginalTail;
 
+    traceENTER_xStreamBufferSpacesAvailable( xStreamBuffer );
+
     configASSERT( pxStreamBuffer );
 
     /* The code below reads xTail and then xHead.  This is safe if the stream
@@ -650,6 +676,8 @@ size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer )
         mtCOVERAGE_TEST_MARKER();
     }
 
+    traceRETURN_xStreamBufferSpacesAvailable( xSpace );
+
     return xSpace;
 }
 /*-----------------------------------------------------------*/
@@ -659,9 +687,14 @@ size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer )
     const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
     size_t xReturn;
 
+    traceENTER_xStreamBufferBytesAvailable( xStreamBuffer );
+
     configASSERT( pxStreamBuffer );
 
     xReturn = prvBytesInBuffer( pxStreamBuffer );
+
+    traceRETURN_xStreamBufferBytesAvailable( xReturn );
+
     return xReturn;
 }
 /*-----------------------------------------------------------*/
@@ -677,6 +710,8 @@ size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
     TimeOut_t xTimeOut;
     size_t xMaxReportedSpace = 0;
 
+    traceENTER_xStreamBufferSend( xStreamBuffer, pvTxData, xDataLengthBytes, xTicksToWait );
+
     configASSERT( pvTxData );
     configASSERT( pxStreamBuffer );
 
@@ -793,6 +828,8 @@ size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
         traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer );
     }
 
+    traceRETURN_xStreamBufferSend( xReturn );
+
     return xReturn;
 }
 /*-----------------------------------------------------------*/
@@ -806,6 +843,8 @@ size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
     size_t xReturn, xSpace;
     size_t xRequiredSpace = xDataLengthBytes;
 
+    traceENTER_xStreamBufferSendFromISR( xStreamBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken );
+
     configASSERT( pvTxData );
     configASSERT( pxStreamBuffer );
 
@@ -843,6 +882,7 @@ size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
     }
 
     traceSTREAM_BUFFER_SEND_FROM_ISR( xStreamBuffer, xReturn );
+    traceRETURN_xStreamBufferSendFromISR( xReturn );
 
     return xReturn;
 }
@@ -906,6 +946,8 @@ size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
     StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
     size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength;
 
+    traceENTER_xStreamBufferReceive( xStreamBuffer, pvRxData, xBufferLengthBytes, xTicksToWait );
+
     configASSERT( pvRxData );
     configASSERT( pxStreamBuffer );
 
@@ -998,6 +1040,8 @@ size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
         mtCOVERAGE_TEST_MARKER();
     }
 
+    traceRETURN_xStreamBufferReceive( xReceivedLength );
+
     return xReceivedLength;
 }
 /*-----------------------------------------------------------*/
@@ -1008,6 +1052,8 @@ size_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer )
     size_t xReturn, xBytesAvailable;
     configMESSAGE_BUFFER_LENGTH_TYPE xTempReturn;
 
+    traceENTER_xStreamBufferNextMessageLengthBytes( xStreamBuffer );
+
     configASSERT( pxStreamBuffer );
 
     /* Ensure the stream buffer is being used as a message buffer. */
@@ -1038,6 +1084,8 @@ size_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer )
         xReturn = 0;
     }
 
+    traceRETURN_xStreamBufferNextMessageLengthBytes( xReturn );
+
     return xReturn;
 }
 /*-----------------------------------------------------------*/
@@ -1050,6 +1098,8 @@ size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
     StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
     size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength;
 
+    traceENTER_xStreamBufferReceiveFromISR( xStreamBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken );
+
     configASSERT( pvRxData );
     configASSERT( pxStreamBuffer );
 
@@ -1094,6 +1144,7 @@ size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
     }
 
     traceSTREAM_BUFFER_RECEIVE_FROM_ISR( xStreamBuffer, xReceivedLength );
+    traceRETURN_xStreamBufferReceiveFromISR( xReceivedLength );
 
     return xReceivedLength;
 }
@@ -1157,6 +1208,8 @@ BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer )
     BaseType_t xReturn;
     size_t xTail;
 
+    traceENTER_xStreamBufferIsEmpty( xStreamBuffer );
+
     configASSERT( pxStreamBuffer );
 
     /* True if no bytes are available. */
@@ -1171,6 +1224,8 @@ BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer )
         xReturn = pdFALSE;
     }
 
+    traceRETURN_xStreamBufferIsEmpty( xReturn );
+
     return xReturn;
 }
 /*-----------------------------------------------------------*/
@@ -1181,6 +1236,8 @@ BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer )
     size_t xBytesToStoreMessageLength;
     const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
 
+    traceENTER_xStreamBufferIsFull( xStreamBuffer );
+
     configASSERT( pxStreamBuffer );
 
     /* This generic version of the receive function is used by both message
@@ -1206,6 +1263,8 @@ BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer )
         xReturn = pdFALSE;
     }
 
+    traceRETURN_xStreamBufferIsFull( xReturn );
+
     return xReturn;
 }
 /*-----------------------------------------------------------*/
@@ -1217,6 +1276,8 @@ BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer
     BaseType_t xReturn;
     UBaseType_t uxSavedInterruptStatus;
 
+    traceENTER_xStreamBufferSendCompletedFromISR( xStreamBuffer, pxHigherPriorityTaskWoken );
+
     configASSERT( pxStreamBuffer );
 
     uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
@@ -1237,6 +1298,8 @@ BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer
     }
     taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
 
+    traceRETURN_xStreamBufferSendCompletedFromISR( xReturn );
+
     return xReturn;
 }
 /*-----------------------------------------------------------*/
@@ -1248,6 +1311,8 @@ BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuf
     BaseType_t xReturn;
     UBaseType_t uxSavedInterruptStatus;
 
+    traceENTER_xStreamBufferReceiveCompletedFromISR( xStreamBuffer, pxHigherPriorityTaskWoken );
+
     configASSERT( pxStreamBuffer );
 
     uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
@@ -1268,6 +1333,8 @@ BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuf
     }
     taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
 
+    traceRETURN_xStreamBufferReceiveCompletedFromISR( xReturn );
+
     return xReturn;
 }
 /*-----------------------------------------------------------*/
@@ -1426,6 +1493,10 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
 
     UBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer )
     {
+        traceENTER_uxStreamBufferGetStreamBufferNumber( xStreamBuffer );
+
+        traceRETURN_uxStreamBufferGetStreamBufferNumber( xStreamBuffer->uxStreamBufferNumber );
+
         return xStreamBuffer->uxStreamBufferNumber;
     }
 
@@ -1437,7 +1508,11 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
     void vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer,
                                              UBaseType_t uxStreamBufferNumber )
     {
+        traceENTER_vStreamBufferSetStreamBufferNumber( xStreamBuffer, uxStreamBufferNumber );
+
         xStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber;
+
+        traceRETURN_vStreamBufferSetStreamBufferNumber();
     }
 
 #endif /* configUSE_TRACE_FACILITY */
@@ -1447,6 +1522,10 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
 
     uint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer )
     {
+        traceENTER_ucStreamBufferGetStreamBufferType( xStreamBuffer );
+
+        traceRETURN_ucStreamBufferGetStreamBufferType( ( uint8_t ) ( xStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) );
+
         return( ( uint8_t ) ( xStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) );
     }
 
diff --git a/tasks.c b/tasks.c
index 99878a3a3..863535c89 100644
--- a/tasks.c
+++ b/tasks.c
@@ -1204,6 +1204,8 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
         TCB_t * pxNewTCB;
         TaskHandle_t xReturn;
 
+        traceENTER_xTaskCreateStatic( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer );
+
         configASSERT( puxStackBuffer != NULL );
         configASSERT( pxTaskBuffer != NULL );
 
@@ -1250,6 +1252,8 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
             xReturn = NULL;
         }
 
+        traceRETURN_xTaskCreateStatic( xReturn );
+
         return xReturn;
     }
 
@@ -1273,6 +1277,8 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
         TCB_t * pxNewTCB;
         BaseType_t xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
 
+        traceENTER_xTaskCreateRestrictedStatic( pxTaskDefinition, pxCreatedTask );
+
         configASSERT( pxTaskDefinition->puxStackBuffer != NULL );
         configASSERT( pxTaskDefinition->pxTaskBuffer != NULL );
 
@@ -1314,6 +1320,8 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
             xReturn = pdPASS;
         }
 
+        traceRETURN_xTaskCreateRestrictedStatic( xReturn );
+
         return xReturn;
     }
 
@@ -1337,6 +1345,8 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
         TCB_t * pxNewTCB;
         BaseType_t xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
 
+        traceENTER_xTaskCreateRestricted( pxTaskDefinition, pxCreatedTask );
+
         configASSERT( pxTaskDefinition->puxStackBuffer );
 
         if( pxTaskDefinition->puxStackBuffer != NULL )
@@ -1379,6 +1389,8 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
             }
         }
 
+        traceRETURN_xTaskCreateRestricted( xReturn );
+
         return xReturn;
     }
 
@@ -1410,6 +1422,8 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
         TCB_t * pxNewTCB;
         BaseType_t xReturn;
 
+        traceENTER_xTaskCreate( pxTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask );
+
         /* If the stack grows down then allocate the stack then the TCB so the stack
          * does not grow into the TCB.  Likewise if the stack grows up then allocate
          * the TCB then the stack. */
@@ -1497,6 +1511,8 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
             xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
         }
 
+        traceRETURN_xTaskCreate( xReturn );
+
         return xReturn;
     }
 
@@ -1904,6 +1920,8 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
     {
         TCB_t * pxTCB;
 
+        traceENTER_vTaskDelete( xTaskToDelete );
+
         taskENTER_CRITICAL();
         {
             /* If null is passed in here then it is the calling task that is
@@ -2034,6 +2052,8 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
             taskEXIT_CRITICAL();
         }
         #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
+
+        traceRETURN_vTaskDelete();
     }
 
 #endif /* INCLUDE_vTaskDelete */
@@ -2047,6 +2067,8 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
         TickType_t xTimeToWake;
         BaseType_t xAlreadyYielded, xShouldDelay = pdFALSE;
 
+        traceENTER_xTaskDelayUntil( pxPreviousWakeTime, xTimeIncrement );
+
         configASSERT( pxPreviousWakeTime );
         configASSERT( ( xTimeIncrement > 0U ) );
 
@@ -2125,6 +2147,8 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
             mtCOVERAGE_TEST_MARKER();
         }
 
+        traceRETURN_xTaskDelayUntil( xShouldDelay );
+
         return xShouldDelay;
     }
 
@@ -2137,6 +2161,8 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
     {
         BaseType_t xAlreadyYielded = pdFALSE;
 
+        traceENTER_vTaskDelay( xTicksToDelay );
+
         /* A delay time of zero just forces a reschedule. */
         if( xTicksToDelay > ( TickType_t ) 0U )
         {
@@ -2176,6 +2202,8 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
         {
             mtCOVERAGE_TEST_MARKER();
         }
+
+        traceRETURN_vTaskDelay();
     }
 
 #endif /* INCLUDE_vTaskDelay */
@@ -2192,6 +2220,8 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
         List_t const * pxOverflowedDelayedList;
         const TCB_t * const pxTCB = xTask;
 
+        traceENTER_eTaskGetState( xTask );
+
         configASSERT( pxTCB );
 
         #if ( configNUMBER_OF_CORES == 1 )
@@ -2303,6 +2333,8 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
             }
         }
 
+        traceRETURN_eTaskGetState( eReturn );
+
         return eReturn;
     } /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */
 
@@ -2316,6 +2348,8 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
         TCB_t const * pxTCB;
         UBaseType_t uxReturn;
 
+        traceENTER_uxTaskPriorityGet( xTask );
+
         taskENTER_CRITICAL();
         {
             /* If null is passed in here then it is the priority of the task
@@ -2325,6 +2359,8 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
         }
         taskEXIT_CRITICAL();
 
+        traceRETURN_uxTaskPriorityGet( uxReturn );
+
         return uxReturn;
     }
 
@@ -2339,6 +2375,8 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
         UBaseType_t uxReturn;
         UBaseType_t uxSavedInterruptStatus;
 
+        traceENTER_uxTaskPriorityGetFromISR( xTask );
+
         /* RTOS ports that support interrupt nesting have the concept of a
          * maximum  system call (or maximum API call) interrupt priority.
          * Interrupts that are  above the maximum system call priority are keep
@@ -2366,6 +2404,8 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
         }
         taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
 
+        traceRETURN_uxTaskPriorityGetFromISR( uxReturn );
+
         return uxReturn;
     }
 
@@ -2381,6 +2421,8 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
         UBaseType_t uxCurrentBasePriority, uxPriorityUsedOnEntry;
         BaseType_t xYieldRequired = pdFALSE;
 
+        traceENTER_vTaskPrioritySet( xTask, uxNewPriority );
+
         #if ( configNUMBER_OF_CORES > 1 )
             BaseType_t xYieldForTask = pdFALSE;
         #endif
@@ -2577,6 +2619,8 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
             }
         }
         taskEXIT_CRITICAL();
+
+        traceRETURN_vTaskPrioritySet();
     }
 
 #endif /* INCLUDE_vTaskPrioritySet */
@@ -2594,6 +2638,8 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
             UBaseType_t uxPrevNotAllowedCores;
         #endif
 
+        traceENTER_vTaskCoreAffinitySet( xTask, uxCoreAffinityMask );
+
         taskENTER_CRITICAL();
         {
             pxTCB = prvGetTCBFromHandle( xTask );
@@ -2639,6 +2685,8 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
             }
         }
         taskEXIT_CRITICAL();
+
+        traceRETURN_vTaskCoreAffinitySet();
     }
 #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */
 /*-----------------------------------------------------------*/
@@ -2649,6 +2697,8 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
         const TCB_t * pxTCB;
         UBaseType_t uxCoreAffinityMask;
 
+        traceENTER_vTaskCoreAffinityGet( xTask );
+
         taskENTER_CRITICAL();
         {
             pxTCB = prvGetTCBFromHandle( xTask );
@@ -2656,6 +2706,8 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
         }
         taskEXIT_CRITICAL();
 
+        traceRETURN_vTaskCoreAffinityGet( uxCoreAffinityMask );
+
         return uxCoreAffinityMask;
     }
 #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */
@@ -2668,6 +2720,8 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
     {
         TCB_t * pxTCB;
 
+        traceENTER_vTaskPreemptionDisable( xTask );
+
         taskENTER_CRITICAL();
         {
             pxTCB = prvGetTCBFromHandle( xTask );
@@ -2675,6 +2729,8 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
             pxTCB->xPreemptionDisable = pdTRUE;
         }
         taskEXIT_CRITICAL();
+
+        traceRETURN_vTaskPreemptionDisable();
     }
 
 #endif /* #if ( configUSE_TASK_PREEMPTION_DISABLE == 1 ) */
@@ -2687,6 +2743,8 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
         TCB_t * pxTCB;
         BaseType_t xCoreID;
 
+        traceENTER_vTaskPreemptionEnable( xTask );
+
         taskENTER_CRITICAL();
         {
             pxTCB = prvGetTCBFromHandle( xTask );
@@ -2703,6 +2761,8 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
             }
         }
         taskEXIT_CRITICAL();
+
+        traceRETURN_vTaskPreemptionEnable();
     }
 
 #endif /* #if ( configUSE_TASK_PREEMPTION_DISABLE == 1 ) */
@@ -2718,6 +2778,8 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
             BaseType_t xTaskRunningOnCore;
         #endif
 
+        traceENTER_vTaskSuspend( xTaskToSuspend );
+
         taskENTER_CRITICAL();
         {
             /* If null is passed in here then it is the running task that is
@@ -2867,6 +2929,8 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
             taskEXIT_CRITICAL();
         }
         #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
+
+        traceRETURN_vTaskSuspend();
     }
 
 #endif /* INCLUDE_vTaskSuspend */
@@ -2924,6 +2988,8 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
     {
         TCB_t * const pxTCB = xTaskToResume;
 
+        traceENTER_vTaskResume( xTaskToResume );
+
         /* It does not make sense to resume the calling task. */
         configASSERT( xTaskToResume );
 
@@ -2969,6 +3035,8 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
         {
             mtCOVERAGE_TEST_MARKER();
         }
+
+        traceRETURN_vTaskResume();
     }
 
 #endif /* INCLUDE_vTaskSuspend */
@@ -2983,6 +3051,8 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
         TCB_t * const pxTCB = xTaskToResume;
         UBaseType_t uxSavedInterruptStatus;
 
+        traceENTER_xTaskResumeFromISR( xTaskToResume );
+
         configASSERT( xTaskToResume );
 
         /* RTOS ports that support interrupt nesting have the concept of a
@@ -3061,6 +3131,8 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
         }
         taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
 
+        traceRETURN_xTaskResumeFromISR( xYieldRequired );
+
         return xYieldRequired;
     }
 
@@ -3244,6 +3316,8 @@ void vTaskStartScheduler( void )
 {
     BaseType_t xReturn;
 
+    traceENTER_vTaskStartScheduler();
+
     #if ( configUSE_CORE_AFFINITY == 1 ) && ( configNUMBER_OF_CORES > 1 )
     {
         /* Sanity check that the UBaseType_t must have greater than or equal to
@@ -3333,22 +3407,30 @@ void vTaskStartScheduler( void )
     /* OpenOCD makes use of uxTopUsedPriority for thread debugging. Prevent uxTopUsedPriority
      * from getting optimized out as it is no longer used by the kernel. */
     ( void ) uxTopUsedPriority;
+
+    traceRETURN_vTaskStartScheduler();
 }
 /*-----------------------------------------------------------*/
 
 void vTaskEndScheduler( void )
 {
+    traceENTER_vTaskEndScheduler();
+
     /* Stop the scheduler interrupts and call the portable scheduler end
      * routine so the original ISRs can be restored if necessary.  The port
      * layer must ensure interrupts enable  bit is left in the correct state. */
     portDISABLE_INTERRUPTS();
     xSchedulerRunning = pdFALSE;
     vPortEndScheduler();
+
+    traceRETURN_vTaskEndScheduler();
 }
 /*----------------------------------------------------------*/
 
 void vTaskSuspendAll( void )
 {
+    traceENTER_vTaskSuspendAll();
+
     #if ( configNUMBER_OF_CORES == 1 )
     {
         /* A critical section is not required as the variable is of type
@@ -3424,6 +3506,8 @@ void vTaskSuspendAll( void )
         }
     }
     #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
+
+    traceRETURN_vTaskSuspendAll();
 }
 
 /*----------------------------------------------------------*/
@@ -3496,6 +3580,8 @@ BaseType_t xTaskResumeAll( void )
     TCB_t * pxTCB = NULL;
     BaseType_t xAlreadyYielded = pdFALSE;
 
+    traceENTER_xTaskResumeAll();
+
     #if ( configNUMBER_OF_CORES > 1 )
         if( xSchedulerRunning != pdFALSE )
     #endif
@@ -3630,6 +3716,8 @@ BaseType_t xTaskResumeAll( void )
         taskEXIT_CRITICAL();
     }
 
+    traceRETURN_xTaskResumeAll( xAlreadyYielded );
+
     return xAlreadyYielded;
 }
 /*-----------------------------------------------------------*/
@@ -3638,6 +3726,8 @@ TickType_t xTaskGetTickCount( void )
 {
     TickType_t xTicks;
 
+    traceENTER_xTaskGetTickCount();
+
     /* Critical section required if running on a 16 bit processor. */
     portTICK_TYPE_ENTER_CRITICAL();
     {
@@ -3645,6 +3735,8 @@ TickType_t xTaskGetTickCount( void )
     }
     portTICK_TYPE_EXIT_CRITICAL();
 
+    traceRETURN_xTaskGetTickCount( xTicks );
+
     return xTicks;
 }
 /*-----------------------------------------------------------*/
@@ -3654,6 +3746,8 @@ TickType_t xTaskGetTickCountFromISR( void )
     TickType_t xReturn;
     UBaseType_t uxSavedInterruptStatus;
 
+    traceENTER_xTaskGetTickCountFromISR();
+
     /* RTOS ports that support interrupt nesting have the concept of a maximum
      * system call (or maximum API call) interrupt priority.  Interrupts that are
      * above the maximum system call priority are kept permanently enabled, even
@@ -3676,14 +3770,20 @@ TickType_t xTaskGetTickCountFromISR( void )
     }
     portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
 
+    traceRETURN_xTaskGetTickCountFromISR( xReturn );
+
     return xReturn;
 }
 /*-----------------------------------------------------------*/
 
 UBaseType_t uxTaskGetNumberOfTasks( void )
 {
+    traceENTER_uxTaskGetNumberOfTasks();
+
     /* A critical section is not required because the variables are of type
      * BaseType_t. */
+    traceRETURN_uxTaskGetNumberOfTasks( uxCurrentNumberOfTasks );
+
     return uxCurrentNumberOfTasks;
 }
 /*-----------------------------------------------------------*/
@@ -3692,10 +3792,15 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char
 {
     TCB_t * pxTCB;
 
+    traceENTER_pcTaskGetName( xTaskToQuery );
+
     /* If null is passed in here then the name of the calling task is being
      * queried. */
     pxTCB = prvGetTCBFromHandle( xTaskToQuery );
     configASSERT( pxTCB );
+
+    traceRETURN_pcTaskGetName( &( pxTCB->pcTaskName[ 0 ] ) );
+
     return &( pxTCB->pcTaskName[ 0 ] );
 }
 /*-----------------------------------------------------------*/
@@ -3844,6 +3949,8 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char
         UBaseType_t uxQueue = configMAX_PRIORITIES;
         TCB_t * pxTCB;
 
+        traceENTER_xTaskGetHandle( pcNameToQuery );
+
         /* Task names will be truncated to configMAX_TASK_NAME_LEN - 1 bytes. */
         configASSERT( strlen( pcNameToQuery ) < configMAX_TASK_NAME_LEN );
 
@@ -3895,6 +4002,8 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char
         }
         ( void ) xTaskResumeAll();
 
+        traceRETURN_xTaskGetHandle( pxTCB );
+
         return pxTCB;
     }
 
@@ -3910,6 +4019,8 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char
         BaseType_t xReturn;
         TCB_t * pxTCB;
 
+        traceENTER_xTaskGetStaticBuffers( xTask, ppuxStackBuffer, ppxTaskBuffer );
+
         configASSERT( ppuxStackBuffer != NULL );
         configASSERT( ppxTaskBuffer != NULL );
 
@@ -3942,6 +4053,8 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char
         }
         #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE == 1 */
 
+        traceRETURN_xTaskGetStaticBuffers( xReturn );
+
         return xReturn;
     }
 
@@ -3956,6 +4069,8 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char
     {
         UBaseType_t uxTask = 0, uxQueue = configMAX_PRIORITIES;
 
+        traceENTER_uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, pulTotalRunTime );
+
         vTaskSuspendAll();
         {
             /* Is there a space in the array for each task in the system? */
@@ -4017,6 +4132,8 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char
         }
         ( void ) xTaskResumeAll();
 
+        traceRETURN_uxTaskGetSystemState( uxTask );
+
         return uxTask;
     }
 
@@ -4029,9 +4146,14 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char
  * Consider to add another function to return the idle task handles. */
     TaskHandle_t xTaskGetIdleTaskHandle( void )
     {
+        traceENTER_xTaskGetIdleTaskHandle();
+
         /* If xTaskGetIdleTaskHandle() is called before the scheduler has been
          * started, then xIdleTaskHandles will be NULL. */
         configASSERT( ( xIdleTaskHandles[ 0 ] != NULL ) );
+
+        traceRETURN_xTaskGetIdleTaskHandle( xIdleTaskHandles[ 0 ] );
+
         return xIdleTaskHandles[ 0 ];
     }
 
@@ -4046,6 +4168,8 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char
 
     void vTaskStepTick( TickType_t xTicksToJump )
     {
+        traceENTER_vTaskStepTick( xTicksToJump );
+
         /* Correct the tick count value after a period during which the tick
          * was suppressed.  Note this does *not* call the tick hook function for
          * each stepped tick. */
@@ -4073,7 +4197,9 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char
         }
 
         xTickCount += xTicksToJump;
+
         traceINCREASE_TICK_COUNT( xTicksToJump );
+        traceRETURN_vTaskStepTick();
     }
 
 #endif /* configUSE_TICKLESS_IDLE */
@@ -4083,6 +4209,8 @@ BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp )
 {
     BaseType_t xYieldOccurred;
 
+    traceENTER_xTaskCatchUpTicks( xTicksToCatchUp );
+
     /* Must not be called with the scheduler suspended as the implementation
      * relies on xPendedTicks being wound down to 0 in xTaskResumeAll(). */
     configASSERT( uxSchedulerSuspended == ( UBaseType_t ) 0U );
@@ -4099,6 +4227,8 @@ BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp )
     taskEXIT_CRITICAL();
     xYieldOccurred = xTaskResumeAll();
 
+    traceRETURN_xTaskCatchUpTicks( xYieldOccurred );
+
     return xYieldOccurred;
 }
 /*----------------------------------------------------------*/
@@ -4110,6 +4240,8 @@ BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp )
         TCB_t * pxTCB = xTask;
         BaseType_t xReturn;
 
+        traceENTER_xTaskAbortDelay( xTask );
+
         configASSERT( pxTCB );
 
         vTaskSuspendAll();
@@ -4189,6 +4321,8 @@ BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp )
         }
         ( void ) xTaskResumeAll();
 
+        traceRETURN_xTaskAbortDelay( xReturn );
+
         return xReturn;
     }
 
@@ -4201,6 +4335,8 @@ BaseType_t xTaskIncrementTick( void )
     TickType_t xItemValue;
     BaseType_t xSwitchRequired = pdFALSE;
 
+    traceENTER_xTaskIncrementTick();
+
     #if ( configUSE_PREEMPTION == 1 ) && ( configNUMBER_OF_CORES > 1 )
     BaseType_t xYieldRequiredForCore[ configNUMBER_OF_CORES ] = { pdFALSE };
     #endif /* #if ( configUSE_PREEMPTION == 1 ) && ( configNUMBER_OF_CORES > 1 ) */
@@ -4438,6 +4574,8 @@ BaseType_t xTaskIncrementTick( void )
         #endif
     }
 
+    traceRETURN_xTaskIncrementTick( xSwitchRequired );
+
     return xSwitchRequired;
 }
 /*-----------------------------------------------------------*/
@@ -4449,6 +4587,8 @@ BaseType_t xTaskIncrementTick( void )
     {
         TCB_t * xTCB;
 
+        traceENTER_vTaskSetApplicationTaskTag( xTask, pxHookFunction );
+
         /* If xTask is NULL then it is the task hook of the calling task that is
          * getting set. */
         if( xTask == NULL )
@@ -4467,6 +4607,8 @@ BaseType_t xTaskIncrementTick( void )
             xTCB->pxTaskTag = pxHookFunction;
         }
         taskEXIT_CRITICAL();
+
+        traceRETURN_vTaskSetApplicationTaskTag();
     }
 
 #endif /* configUSE_APPLICATION_TASK_TAG */
@@ -4479,6 +4621,8 @@ BaseType_t xTaskIncrementTick( void )
         TCB_t * pxTCB;
         TaskHookFunction_t xReturn;
 
+        traceENTER_xTaskGetApplicationTaskTag( xTask );
+
         /* If xTask is NULL then set the calling task's hook. */
         pxTCB = prvGetTCBFromHandle( xTask );
 
@@ -4490,6 +4634,8 @@ BaseType_t xTaskIncrementTick( void )
         }
         taskEXIT_CRITICAL();
 
+        traceRETURN_xTaskGetApplicationTaskTag( xReturn );
+
         return xReturn;
     }
 
@@ -4504,6 +4650,8 @@ BaseType_t xTaskIncrementTick( void )
         TaskHookFunction_t xReturn;
         UBaseType_t uxSavedInterruptStatus;
 
+        traceENTER_xTaskGetApplicationTaskTagFromISR( xTask );
+
         /* If xTask is NULL then set the calling task's hook. */
         pxTCB = prvGetTCBFromHandle( xTask );
 
@@ -4515,6 +4663,8 @@ BaseType_t xTaskIncrementTick( void )
         }
         taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
 
+        traceRETURN_xTaskGetApplicationTaskTagFromISR( xReturn );
+
         return xReturn;
     }
 
@@ -4529,6 +4679,8 @@ BaseType_t xTaskIncrementTick( void )
         TCB_t * xTCB;
         BaseType_t xReturn;
 
+        traceENTER_xTaskCallApplicationTaskHook( xTask, pvParameter );
+
         /* If xTask is NULL then we are calling our own task hook. */
         if( xTask == NULL )
         {
@@ -4548,6 +4700,8 @@ BaseType_t xTaskIncrementTick( void )
             xReturn = pdFAIL;
         }
 
+        traceRETURN_xTaskCallApplicationTaskHook( xReturn );
+
         return xReturn;
     }
 
@@ -4557,6 +4711,8 @@ BaseType_t xTaskIncrementTick( void )
 #if ( configNUMBER_OF_CORES == 1 )
     void vTaskSwitchContext( void )
     {
+        traceENTER_vTaskSwitchContext();
+
         if( uxSchedulerSuspended != ( UBaseType_t ) 0U )
         {
             /* The scheduler is currently suspended - do not allow a context
@@ -4626,10 +4782,14 @@ BaseType_t xTaskIncrementTick( void )
             }
             #endif
         }
+
+        traceRETURN_vTaskSwitchContext();
     }
 #else /* if ( configNUMBER_OF_CORES == 1 ) */
     void vTaskSwitchContext( BaseType_t xCoreID )
     {
+        traceENTER_vTaskSwitchContext();
+
         /* Acquire both locks:
          * - The ISR lock protects the ready list from simultaneous access by
          *   both other ISRs and tasks.
@@ -4717,6 +4877,8 @@ BaseType_t xTaskIncrementTick( void )
         }
         portRELEASE_ISR_LOCK();
         portRELEASE_TASK_LOCK();
+
+        traceRETURN_vTaskSwitchContext();
     }
 #endif /* if ( configNUMBER_OF_CORES > 1 ) */
 /*-----------------------------------------------------------*/
@@ -4724,6 +4886,8 @@ BaseType_t xTaskIncrementTick( void )
 void vTaskPlaceOnEventList( List_t * const pxEventList,
                             const TickType_t xTicksToWait )
 {
+    traceENTER_vTaskPlaceOnEventList( pxEventList, xTicksToWait );
+
     configASSERT( pxEventList );
 
     /* THIS FUNCTION MUST BE CALLED WITH EITHER INTERRUPTS DISABLED OR THE
@@ -4743,6 +4907,8 @@ void vTaskPlaceOnEventList( List_t * const pxEventList,
     vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) );
 
     prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+
+    traceRETURN_vTaskPlaceOnEventList();
 }
 /*-----------------------------------------------------------*/
 
@@ -4750,6 +4916,8 @@ void vTaskPlaceOnUnorderedEventList( List_t * pxEventList,
                                      const TickType_t xItemValue,
                                      const TickType_t xTicksToWait )
 {
+    traceENTER_vTaskPlaceOnUnorderedEventList( pxEventList, xItemValue, xTicksToWait );
+
     configASSERT( pxEventList );
 
     /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED.  It is used by
@@ -4769,6 +4937,8 @@ void vTaskPlaceOnUnorderedEventList( List_t * pxEventList,
     listINSERT_END( pxEventList, &( pxCurrentTCB->xEventListItem ) );
 
     prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+
+    traceRETURN_vTaskPlaceOnUnorderedEventList();
 }
 /*-----------------------------------------------------------*/
 
@@ -4778,6 +4948,8 @@ void vTaskPlaceOnUnorderedEventList( List_t * pxEventList,
                                           TickType_t xTicksToWait,
                                           const BaseType_t xWaitIndefinitely )
     {
+        traceENTER_vTaskPlaceOnEventListRestricted( pxEventList, xTicksToWait, xWaitIndefinitely );
+
         configASSERT( pxEventList );
 
         /* This function should not be called by application code hence the
@@ -4802,6 +4974,8 @@ void vTaskPlaceOnUnorderedEventList( List_t * pxEventList,
 
         traceTASK_DELAY_UNTIL( ( xTickCount + xTicksToWait ) );
         prvAddCurrentTaskToDelayedList( xTicksToWait, xWaitIndefinitely );
+
+        traceRETURN_vTaskPlaceOnEventListRestricted();
     }
 
 #endif /* configUSE_TIMERS */
@@ -4812,6 +4986,8 @@ BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList )
     TCB_t * pxUnblockedTCB;
     BaseType_t xReturn;
 
+    traceENTER_xTaskRemoveFromEventList( pxEventList );
+
     /* THIS FUNCTION MUST BE CALLED FROM A CRITICAL SECTION.  It can also be
      * called from a critical section within an ISR. */
 
@@ -4890,6 +5066,7 @@ BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList )
     }
     #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
 
+    traceRETURN_xTaskRemoveFromEventList( xReturn );
     return xReturn;
 }
 /*-----------------------------------------------------------*/
@@ -4899,6 +5076,8 @@ void vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem,
 {
     TCB_t * pxUnblockedTCB;
 
+    traceENTER_vTaskRemoveFromUnorderedEventList( pxEventListItem, xItemValue );
+
     /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED.  It is used by
      * the event flags implementation. */
     configASSERT( uxSchedulerSuspended != ( UBaseType_t ) 0U );
@@ -4956,11 +5135,15 @@ void vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem,
         #endif
     }
     #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
+
+    traceRETURN_vTaskRemoveFromUnorderedEventList();
 }
 /*-----------------------------------------------------------*/
 
 void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut )
 {
+    traceENTER_vTaskSetTimeOutState( pxTimeOut );
+
     configASSERT( pxTimeOut );
     taskENTER_CRITICAL();
     {
@@ -4968,14 +5151,20 @@ void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut )
         pxTimeOut->xTimeOnEntering = xTickCount;
     }
     taskEXIT_CRITICAL();
+
+    traceRETURN_vTaskSetTimeOutState();
 }
 /*-----------------------------------------------------------*/
 
 void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut )
 {
+    traceENTER_vTaskInternalSetTimeOutState( pxTimeOut );
+
     /* For internal use only as it does not use a critical section. */
     pxTimeOut->xOverflowCount = xNumOfOverflows;
     pxTimeOut->xTimeOnEntering = xTickCount;
+
+    traceRETURN_vTaskInternalSetTimeOutState();
 }
 /*-----------------------------------------------------------*/
 
@@ -4984,6 +5173,8 @@ BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
 {
     BaseType_t xReturn;
 
+    traceENTER_xTaskCheckForTimeOut( pxTimeOut, pxTicksToWait );
+
     configASSERT( pxTimeOut );
     configASSERT( pxTicksToWait );
 
@@ -5040,14 +5231,20 @@ BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
     }
     taskEXIT_CRITICAL();
 
+    traceRETURN_xTaskCheckForTimeOut( xReturn );
+
     return xReturn;
 }
 /*-----------------------------------------------------------*/
 
 void vTaskMissedYield( void )
 {
+    traceENTER_vTaskMissedYield();
+
     /* Must be called from within a critical section. */
     xYieldPendings[ portGET_CORE_ID() ] = pdTRUE;
+
+    traceRETURN_vTaskMissedYield();
 }
 /*-----------------------------------------------------------*/
 
@@ -5058,6 +5255,8 @@ void vTaskMissedYield( void )
         UBaseType_t uxReturn;
         TCB_t const * pxTCB;
 
+        traceENTER_uxTaskGetTaskNumber( xTask );
+
         if( xTask != NULL )
         {
             pxTCB = xTask;
@@ -5068,6 +5267,8 @@ void vTaskMissedYield( void )
             uxReturn = 0U;
         }
 
+        traceRETURN_uxTaskGetTaskNumber( uxReturn );
+
         return uxReturn;
     }
 
@@ -5081,11 +5282,15 @@ void vTaskMissedYield( void )
     {
         TCB_t * pxTCB;
 
+        traceENTER_vTaskSetTaskNumber( xTask, uxHandle );
+
         if( xTask != NULL )
         {
             pxTCB = xTask;
             pxTCB->uxTaskNumber = uxHandle;
         }
+
+        traceRETURN_vTaskSetTaskNumber();
     }
 
 #endif /* configUSE_TRACE_FACILITY */
@@ -5320,6 +5525,8 @@ static portTASK_FUNCTION( prvIdleTask, pvParameters )
             const UBaseType_t uxNonApplicationTasks = 1;
         #endif /* INCLUDE_vTaskSuspend */
 
+        traceENTER_eTaskConfirmSleepModeStatus();
+
         eSleepModeStatus eReturn = eStandardSleep;
 
         /* This function must be called from a critical section. */
@@ -5356,6 +5563,8 @@ static portTASK_FUNCTION( prvIdleTask, pvParameters )
             mtCOVERAGE_TEST_MARKER();
         }
 
+        traceRETURN_eTaskConfirmSleepModeStatus( eReturn );
+
         return eReturn;
     }
 
@@ -5370,6 +5579,8 @@ static portTASK_FUNCTION( prvIdleTask, pvParameters )
     {
         TCB_t * pxTCB;
 
+        traceENTER_vTaskSetThreadLocalStoragePointer( xTaskToSet, xIndex, pvValue );
+
         if( ( xIndex >= 0 ) &&
             ( xIndex < ( BaseType_t ) configNUM_THREAD_LOCAL_STORAGE_POINTERS ) )
         {
@@ -5377,6 +5588,8 @@ static portTASK_FUNCTION( prvIdleTask, pvParameters )
             configASSERT( pxTCB != NULL );
             pxTCB->pvThreadLocalStoragePointers[ xIndex ] = pvValue;
         }
+
+        traceRETURN_vTaskSetThreadLocalStoragePointer();
     }
 
 #endif /* configNUM_THREAD_LOCAL_STORAGE_POINTERS */
@@ -5390,6 +5603,8 @@ static portTASK_FUNCTION( prvIdleTask, pvParameters )
         void * pvReturn = NULL;
         TCB_t * pxTCB;
 
+        traceENTER_pvTaskGetThreadLocalStoragePointer( xTaskToQuery, xIndex );
+
         if( ( xIndex >= 0 ) &&
             ( xIndex < ( BaseType_t ) configNUM_THREAD_LOCAL_STORAGE_POINTERS ) )
         {
@@ -5401,6 +5616,8 @@ static portTASK_FUNCTION( prvIdleTask, pvParameters )
             pvReturn = NULL;
         }
 
+        traceRETURN_pvTaskGetThreadLocalStoragePointer( pvReturn );
+
         return pvReturn;
     }
 
@@ -5414,11 +5631,15 @@ static portTASK_FUNCTION( prvIdleTask, pvParameters )
     {
         TCB_t * pxTCB;
 
+        traceENTER_vTaskAllocateMPURegions( xTaskToModify, pxRegions );
+
         /* If null is passed in here then we are modifying the MPU settings of
          * the calling task. */
         pxTCB = prvGetTCBFromHandle( xTaskToModify );
 
         vPortStoreTaskMPUSettings( &( pxTCB->xMPUSettings ), pxRegions, NULL, 0 );
+
+        traceRETURN_vTaskAllocateMPURegions();
     }
 
 #endif /* portUSING_MPU_WRAPPERS */
@@ -5535,6 +5756,8 @@ static void prvCheckTasksWaitingTermination( void )
     {
         TCB_t * pxTCB;
 
+        traceENTER_vTaskGetInfo( xTask, pxTaskStatus, xGetFreeStackSpace, eState );
+
         /* xTask is NULL then get the state of the calling task. */
         pxTCB = prvGetTCBFromHandle( xTask );
 
@@ -5642,6 +5865,8 @@ static void prvCheckTasksWaitingTermination( void )
         {
             pxTaskStatus->usStackHighWaterMark = 0;
         }
+
+        traceRETURN_vTaskGetInfo();
     }
 
 #endif /* configUSE_TRACE_FACILITY */
@@ -5716,6 +5941,8 @@ static void prvCheckTasksWaitingTermination( void )
         uint8_t * pucEndOfStack;
         configSTACK_DEPTH_TYPE uxReturn;
 
+        traceENTER_uxTaskGetStackHighWaterMark2( xTask );
+
         /* uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are
          * the same except for their return type.  Using configSTACK_DEPTH_TYPE
          * allows the user to determine the return type.  It gets around the
@@ -5737,6 +5964,8 @@ static void prvCheckTasksWaitingTermination( void )
 
         uxReturn = prvTaskCheckFreeStackSpace( pucEndOfStack );
 
+        traceRETURN_uxTaskGetStackHighWaterMark2( uxReturn );
+
         return uxReturn;
     }
 
@@ -5751,6 +5980,8 @@ static void prvCheckTasksWaitingTermination( void )
         uint8_t * pucEndOfStack;
         UBaseType_t uxReturn;
 
+        traceENTER_uxTaskGetStackHighWaterMark( xTask );
+
         pxTCB = prvGetTCBFromHandle( xTask );
 
         #if portSTACK_GROWTH < 0
@@ -5765,6 +5996,8 @@ static void prvCheckTasksWaitingTermination( void )
 
         uxReturn = ( UBaseType_t ) prvTaskCheckFreeStackSpace( pucEndOfStack );
 
+        traceRETURN_uxTaskGetStackHighWaterMark( uxReturn );
+
         return uxReturn;
     }
 
@@ -5854,11 +6087,15 @@ static void prvResetNextTaskUnblockTime( void )
         {
             TaskHandle_t xReturn;
 
+            traceENTER_xTaskGetCurrentTaskHandle();
+
             /* A critical section is not required as this is not called from
              * an interrupt and the current TCB will always be the same for any
              * individual execution thread. */
             xReturn = pxCurrentTCB;
 
+            traceRETURN_xTaskGetCurrentTaskHandle( xReturn );
+
             return xReturn;
         }
     #else /* #if ( configNUMBER_OF_CORES == 1 ) */
@@ -5867,12 +6104,16 @@ static void prvResetNextTaskUnblockTime( void )
             TaskHandle_t xReturn;
             UBaseType_t uxSavedInterruptStatus;
 
+            traceENTER_xTaskGetCurrentTaskHandle();
+
             uxSavedInterruptStatus = portSET_INTERRUPT_MASK();
             {
                 xReturn = pxCurrentTCBs[ portGET_CORE_ID() ];
             }
             portCLEAR_INTERRUPT_MASK( uxSavedInterruptStatus );
 
+            traceRETURN_xTaskGetCurrentTaskHandle( xReturn );
+
             return xReturn;
         }
 
@@ -5880,11 +6121,15 @@ static void prvResetNextTaskUnblockTime( void )
         {
             TaskHandle_t xReturn = NULL;
 
+            traceENTER_xTaskGetCurrentTaskHandleCPU( xCoreID );
+
             if( taskVALID_CORE_ID( xCoreID ) != pdFALSE )
             {
                 xReturn = pxCurrentTCBs[ xCoreID ];
             }
 
+            traceRETURN_xTaskGetCurrentTaskHandleCPU( xReturn );
+
             return xReturn;
         }
     #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
@@ -5898,6 +6143,8 @@ static void prvResetNextTaskUnblockTime( void )
     {
         BaseType_t xReturn;
 
+        traceENTER_xTaskGetSchedulerState();
+
         if( xSchedulerRunning == pdFALSE )
         {
             xReturn = taskSCHEDULER_NOT_STARTED;
@@ -5922,6 +6169,8 @@ static void prvResetNextTaskUnblockTime( void )
             #endif
         }
 
+        traceRETURN_xTaskGetSchedulerState( xReturn );
+
         return xReturn;
     }
 
@@ -5935,6 +6184,8 @@ static void prvResetNextTaskUnblockTime( void )
         TCB_t * const pxMutexHolderTCB = pxMutexHolder;
         BaseType_t xReturn = pdFALSE;
 
+        traceENTER_xTaskPriorityInherit( pxMutexHolder );
+
         /* If the mutex was given back by an interrupt while the queue was
          * locked then the mutex holder might now be NULL.  _RB_ Is this still
          * needed as interrupts can no longer use mutexes? */
@@ -6022,6 +6273,8 @@ static void prvResetNextTaskUnblockTime( void )
             mtCOVERAGE_TEST_MARKER();
         }
 
+        traceRETURN_xTaskPriorityInherit( xReturn );
+
         return xReturn;
     }
 
@@ -6035,6 +6288,8 @@ static void prvResetNextTaskUnblockTime( void )
         TCB_t * const pxTCB = pxMutexHolder;
         BaseType_t xReturn = pdFALSE;
 
+        traceENTER_xTaskPriorityDisinherit( pxMutexHolder );
+
         if( pxMutexHolder != NULL )
         {
             /* A task can only have an inherited priority if it holds the mutex.
@@ -6112,6 +6367,8 @@ static void prvResetNextTaskUnblockTime( void )
             mtCOVERAGE_TEST_MARKER();
         }
 
+        traceRETURN_xTaskPriorityDisinherit( xReturn );
+
         return xReturn;
     }
 
@@ -6127,6 +6384,8 @@ static void prvResetNextTaskUnblockTime( void )
         UBaseType_t uxPriorityUsedOnEntry, uxPriorityToUse;
         const UBaseType_t uxOnlyOneMutexHeld = ( UBaseType_t ) 1;
 
+        traceENTER_vTaskPriorityDisinheritAfterTimeout( pxMutexHolder, uxHighestPriorityWaitingTask );
+
         if( pxMutexHolder != NULL )
         {
             /* If pxMutexHolder is not NULL then the holder must hold at least
@@ -6229,6 +6488,8 @@ static void prvResetNextTaskUnblockTime( void )
         {
             mtCOVERAGE_TEST_MARKER();
         }
+
+        traceRETURN_vTaskPriorityDisinheritAfterTimeout();
     }
 
 #endif /* configUSE_MUTEXES */
@@ -6242,6 +6503,8 @@ static void prvResetNextTaskUnblockTime( void )
  */
     void vTaskYieldWithinAPI( void )
     {
+        traceENTER_vTaskYieldWithinAPI();
+
         if( portGET_CRITICAL_NESTING_COUNT() == 0U )
         {
             portYIELD();
@@ -6250,6 +6513,8 @@ static void prvResetNextTaskUnblockTime( void )
         {
             xYieldPendings[ portGET_CORE_ID() ] = pdTRUE;
         }
+
+        traceRETURN_vTaskYieldWithinAPI();
     }
 #endif /* #if ( configNUMBER_OF_CORES > 1 ) */
 
@@ -6259,6 +6524,8 @@ static void prvResetNextTaskUnblockTime( void )
 
     void vTaskEnterCritical( void )
     {
+        traceENTER_vTaskEnterCritical();
+
         portDISABLE_INTERRUPTS();
 
         if( xSchedulerRunning != pdFALSE )
@@ -6280,6 +6547,8 @@ static void prvResetNextTaskUnblockTime( void )
         {
             mtCOVERAGE_TEST_MARKER();
         }
+
+        traceRETURN_vTaskEnterCritical();
     }
 
 #endif /* #if ( ( portCRITICAL_NESTING_IN_TCB == 1 ) && ( configNUMBER_OF_CORES == 1 ) ) */
@@ -6289,6 +6558,8 @@ static void prvResetNextTaskUnblockTime( void )
 
     void vTaskEnterCritical( void )
     {
+        traceENTER_vTaskEnterCritical();
+
         portDISABLE_INTERRUPTS();
 
         if( xSchedulerRunning != pdFALSE )
@@ -6325,6 +6596,8 @@ static void prvResetNextTaskUnblockTime( void )
         {
             mtCOVERAGE_TEST_MARKER();
         }
+
+        traceRETURN_vTaskEnterCritical();
     }
 
 #endif /* #if ( configNUMBER_OF_CORES > 1 ) */
@@ -6337,6 +6610,8 @@ static void prvResetNextTaskUnblockTime( void )
     {
         UBaseType_t uxSavedInterruptStatus = 0;
 
+        traceENTER_vTaskEnterCriticalFromISR();
+
         if( xSchedulerRunning != pdFALSE )
         {
             uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
@@ -6353,6 +6628,8 @@ static void prvResetNextTaskUnblockTime( void )
             mtCOVERAGE_TEST_MARKER();
         }
 
+        traceRETURN_vTaskEnterCriticalFromISR( uxSavedInterruptStatus );
+
         return uxSavedInterruptStatus;
     }
 
@@ -6363,6 +6640,8 @@ static void prvResetNextTaskUnblockTime( void )
 
     void vTaskExitCritical( void )
     {
+        traceENTER_vTaskExitCritical();
+
         if( xSchedulerRunning != pdFALSE )
         {
             /* If pxCurrentTCB->uxCriticalNesting is zero then this function
@@ -6395,6 +6674,8 @@ static void prvResetNextTaskUnblockTime( void )
         {
             mtCOVERAGE_TEST_MARKER();
         }
+
+        traceRETURN_vTaskExitCritical();
     }
 
 #endif /* #if ( ( portCRITICAL_NESTING_IN_TCB == 1 ) && ( configNUMBER_OF_CORES == 1 ) ) */
@@ -6404,6 +6685,8 @@ static void prvResetNextTaskUnblockTime( void )
 
     void vTaskExitCritical( void )
     {
+        traceENTER_vTaskExitCritical();
+
         if( xSchedulerRunning != pdFALSE )
         {
             /* If critical nesting count is zero then this function
@@ -6452,6 +6735,8 @@ static void prvResetNextTaskUnblockTime( void )
         {
             mtCOVERAGE_TEST_MARKER();
         }
+
+        traceRETURN_vTaskExitCritical();
     }
 
 #endif /* #if ( configNUMBER_OF_CORES > 1 ) */
@@ -6461,6 +6746,8 @@ static void prvResetNextTaskUnblockTime( void )
 
     void vTaskExitCriticalFromISR( UBaseType_t uxSavedInterruptStatus )
     {
+        traceENTER_vTaskExitCriticalFromISR( uxSavedInterruptStatus );
+
         if( xSchedulerRunning != pdFALSE )
         {
             /* If critical nesting count is zero then this function
@@ -6490,6 +6777,8 @@ static void prvResetNextTaskUnblockTime( void )
         {
             mtCOVERAGE_TEST_MARKER();
         }
+
+        traceRETURN_vTaskExitCriticalFromISR();
     }
 
 #endif /* #if ( configNUMBER_OF_CORES > 1 ) */
@@ -6530,6 +6819,8 @@ static void prvResetNextTaskUnblockTime( void )
         UBaseType_t uxArraySize, x;
         char cStatus;
 
+        traceENTER_vTaskList( pcWriteBuffer );
+
         /*
          * PLEASE NOTE:
          *
@@ -6623,6 +6914,8 @@ static void prvResetNextTaskUnblockTime( void )
         {
             mtCOVERAGE_TEST_MARKER();
         }
+
+        traceRETURN_vTaskList();
     }
 
 #endif /* ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) ) */
@@ -6636,6 +6929,8 @@ static void prvResetNextTaskUnblockTime( void )
         UBaseType_t uxArraySize, x;
         configRUN_TIME_COUNTER_TYPE ulTotalTime, ulStatsAsPercentage;
 
+        traceENTER_vTaskGetRunTimeStats( pcWriteBuffer );
+
         /*
          * PLEASE NOTE:
          *
@@ -6744,6 +7039,8 @@ static void prvResetNextTaskUnblockTime( void )
         {
             mtCOVERAGE_TEST_MARKER();
         }
+
+        traceRETURN_vTaskGetRunTimeStats();
     }
 
 #endif /* ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) ) */
@@ -6753,12 +7050,16 @@ TickType_t uxTaskResetEventItemValue( void )
 {
     TickType_t uxReturn;
 
+    traceENTER_uxTaskResetEventItemValue();
+
     uxReturn = listGET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ) );
 
     /* Reset the event list item to its normal value - so it can be used with
      * queues and semaphores. */
     listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
 
+    traceRETURN_uxTaskResetEventItemValue( uxReturn );
+
     return uxReturn;
 }
 /*-----------------------------------------------------------*/
@@ -6769,6 +7070,8 @@ TickType_t uxTaskResetEventItemValue( void )
     {
         TCB_t * pxTCB;
 
+        traceENTER_pvTaskIncrementMutexHeldCount();
+
         pxTCB = pxCurrentTCB;
 
         /* If xSemaphoreCreateMutex() is called before any tasks have been created
@@ -6778,6 +7081,8 @@ TickType_t uxTaskResetEventItemValue( void )
             ( pxTCB->uxMutexesHeld )++;
         }
 
+        traceRETURN_pvTaskIncrementMutexHeldCount( pxTCB );
+
         return pxTCB;
     }
 
@@ -6792,6 +7097,8 @@ TickType_t uxTaskResetEventItemValue( void )
     {
         uint32_t ulReturn;
 
+        traceENTER_ulTaskGenericNotifyTake( uxIndexToWaitOn, xClearCountOnExit, xTicksToWait );
+
         configASSERT( uxIndexToWaitOn < configTASK_NOTIFICATION_ARRAY_ENTRIES );
 
         taskENTER_CRITICAL();
@@ -6858,6 +7165,8 @@ TickType_t uxTaskResetEventItemValue( void )
         }
         taskEXIT_CRITICAL();
 
+        traceRETURN_ulTaskGenericNotifyTake( ulReturn );
+
         return ulReturn;
     }
 
@@ -6874,6 +7183,8 @@ TickType_t uxTaskResetEventItemValue( void )
     {
         BaseType_t xReturn;
 
+        traceENTER_xTaskGenericNotifyWait( uxIndexToWaitOn, ulBitsToClearOnEntry, ulBitsToClearOnExit, pulNotificationValue, xTicksToWait );
+
         configASSERT( uxIndexToWaitOn < configTASK_NOTIFICATION_ARRAY_ENTRIES );
 
         taskENTER_CRITICAL();
@@ -6952,6 +7263,8 @@ TickType_t uxTaskResetEventItemValue( void )
         }
         taskEXIT_CRITICAL();
 
+        traceRETURN_xTaskGenericNotifyWait( xReturn );
+
         return xReturn;
     }
 
@@ -6970,6 +7283,8 @@ TickType_t uxTaskResetEventItemValue( void )
         BaseType_t xReturn = pdPASS;
         uint8_t ucOriginalNotifyState;
 
+        traceENTER_xTaskGenericNotify( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pulPreviousNotificationValue );
+
         configASSERT( uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES );
         configASSERT( xTaskToNotify );
         pxTCB = xTaskToNotify;
@@ -7068,6 +7383,8 @@ TickType_t uxTaskResetEventItemValue( void )
         }
         taskEXIT_CRITICAL();
 
+        traceRETURN_xTaskGenericNotify( xReturn );
+
         return xReturn;
     }
 
@@ -7088,6 +7405,8 @@ TickType_t uxTaskResetEventItemValue( void )
         BaseType_t xReturn = pdPASS;
         UBaseType_t uxSavedInterruptStatus;
 
+        traceENTER_xTaskGenericNotifyFromISR( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pulPreviousNotificationValue, pxHigherPriorityTaskWoken );
+
         configASSERT( xTaskToNotify );
         configASSERT( uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES );
 
@@ -7227,6 +7546,8 @@ TickType_t uxTaskResetEventItemValue( void )
         }
         taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
 
+        traceRETURN_xTaskGenericNotifyFromISR( xReturn );
+
         return xReturn;
     }
 
@@ -7243,6 +7564,8 @@ TickType_t uxTaskResetEventItemValue( void )
         uint8_t ucOriginalNotifyState;
         UBaseType_t uxSavedInterruptStatus;
 
+        traceENTER_vTaskGenericNotifyGiveFromISR( xTaskToNotify, uxIndexToNotify, pxHigherPriorityTaskWoken );
+
         configASSERT( xTaskToNotify );
         configASSERT( uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES );
 
@@ -7337,6 +7660,8 @@ TickType_t uxTaskResetEventItemValue( void )
             }
         }
         taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
+
+        traceRETURN_vTaskGenericNotifyGiveFromISR();
     }
 
 #endif /* configUSE_TASK_NOTIFICATIONS */
@@ -7350,6 +7675,8 @@ TickType_t uxTaskResetEventItemValue( void )
         TCB_t * pxTCB;
         BaseType_t xReturn;
 
+        traceENTER_xTaskGenericNotifyStateClear( xTask, uxIndexToClear );
+
         configASSERT( uxIndexToClear < configTASK_NOTIFICATION_ARRAY_ENTRIES );
 
         /* If null is passed in here then it is the calling task that is having
@@ -7370,6 +7697,8 @@ TickType_t uxTaskResetEventItemValue( void )
         }
         taskEXIT_CRITICAL();
 
+        traceRETURN_xTaskGenericNotifyStateClear( xReturn );
+
         return xReturn;
     }
 
@@ -7385,6 +7714,8 @@ TickType_t uxTaskResetEventItemValue( void )
         TCB_t * pxTCB;
         uint32_t ulReturn;
 
+        traceENTER_ulTaskGenericNotifyValueClear( xTask, uxIndexToClear, ulBitsToClear );
+
         configASSERT( uxIndexToClear < configTASK_NOTIFICATION_ARRAY_ENTRIES );
 
         /* If null is passed in here then it is the calling task that is having
@@ -7400,6 +7731,8 @@ TickType_t uxTaskResetEventItemValue( void )
         }
         taskEXIT_CRITICAL();
 
+        traceRETURN_ulTaskGenericNotifyValueClear( ulReturn );
+
         return ulReturn;
     }
 
@@ -7412,8 +7745,12 @@ TickType_t uxTaskResetEventItemValue( void )
     {
         TCB_t * pxTCB;
 
+        traceENTER_ulTaskGetRunTimeCounter( xTask );
+
         pxTCB = prvGetTCBFromHandle( xTask );
 
+        traceRETURN_ulTaskGetRunTimeCounter( pxTCB->ulRunTimeCounter );
+
         return pxTCB->ulRunTimeCounter;
     }
 
@@ -7427,6 +7764,8 @@ TickType_t uxTaskResetEventItemValue( void )
         TCB_t * pxTCB;
         configRUN_TIME_COUNTER_TYPE ulTotalTime, ulReturn;
 
+        traceENTER_ulTaskGetRunTimePercent( xTask );
+
         ulTotalTime = ( configRUN_TIME_COUNTER_TYPE ) portGET_RUN_TIME_COUNTER_VALUE();
 
         /* For percentage calculations. */
@@ -7443,6 +7782,8 @@ TickType_t uxTaskResetEventItemValue( void )
             ulReturn = 0;
         }
 
+        traceRETURN_ulTaskGetRunTimePercent( ulReturn );
+
         return ulReturn;
     }
 
@@ -7456,11 +7797,15 @@ TickType_t uxTaskResetEventItemValue( void )
         configRUN_TIME_COUNTER_TYPE ulReturn = 0;
         BaseType_t i;
 
+        traceENTER_ulTaskGetIdleRunTimeCounter();
+
         for( i = 0; i < ( BaseType_t ) configNUMBER_OF_CORES; i++ )
         {
             ulReturn += xIdleTaskHandles[ i ]->ulRunTimeCounter;
         }
 
+        traceRETURN_ulTaskGetIdleRunTimeCounter( ulReturn );
+
         return ulReturn;
     }
 
@@ -7475,6 +7820,8 @@ TickType_t uxTaskResetEventItemValue( void )
         configRUN_TIME_COUNTER_TYPE ulRunTimeCounter = 0;
         BaseType_t i;
 
+        traceENTER_ulTaskGetIdleRunTimePercent();
+
         ulTotalTime = portGET_RUN_TIME_COUNTER_VALUE() * configNUMBER_OF_CORES;
 
         /* For percentage calculations. */
@@ -7495,6 +7842,8 @@ TickType_t uxTaskResetEventItemValue( void )
             ulReturn = 0;
         }
 
+        traceRETURN_ulTaskGetIdleRunTimePercent( ulReturn );
+
         return ulReturn;
     }
 
@@ -7624,8 +7973,12 @@ static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait,
     {
         TCB_t * pxTCB;
 
+        traceENTER_xTaskGetMPUSettings( xTask );
+
         pxTCB = prvGetTCBFromHandle( xTask );
 
+        traceRETURN_xTaskGetMPUSettings( &( pxTCB->xMPUSettings ) );
+
         return &( pxTCB->xMPUSettings );
     }
 
diff --git a/timers.c b/timers.c
index abe39e12c..0d7a0c0fe 100644
--- a/timers.c
+++ b/timers.c
@@ -235,6 +235,8 @@
     {
         BaseType_t xReturn = pdFAIL;
 
+        traceENTER_xTimerCreateTimerTask();
+
         /* This function is called when the scheduler is started if
          * configUSE_TIMERS is set to 1.  Check that the infrastructure used by the
          * timer service task has been created/initialised.  If timers have already
@@ -280,6 +282,9 @@
         }
 
         configASSERT( xReturn );
+
+        traceRETURN_xTimerCreateTimerTask( xReturn );
+
         return xReturn;
     }
 /*-----------------------------------------------------------*/
@@ -294,6 +299,8 @@
         {
             Timer_t * pxNewTimer;
 
+            traceENTER_xTimerCreate( pcTimerName, xTimerPeriodInTicks, xAutoReload, pvTimerID, pxCallbackFunction );
+
             pxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of Timer_t is always a pointer to the timer's name. */
 
             if( pxNewTimer != NULL )
@@ -305,6 +312,8 @@
                 prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, xAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer );
             }
 
+            traceRETURN_xTimerCreate( pxNewTimer );
+
             return pxNewTimer;
         }
 
@@ -322,6 +331,8 @@
         {
             Timer_t * pxNewTimer;
 
+            traceENTER_xTimerCreateStatic( pcTimerName, xTimerPeriodInTicks, xAutoReload, pvTimerID, pxCallbackFunction, pxTimerBuffer );
+
             #if ( configASSERT_DEFINED == 1 )
             {
                 /* Sanity check that the size of the structure used to declare a
@@ -347,6 +358,8 @@
                 prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, xAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer );
             }
 
+            traceRETURN_xTimerCreateStatic( pxNewTimer );
+
             return pxNewTimer;
         }
 
@@ -395,6 +408,8 @@
 
         ( void ) pxHigherPriorityTaskWoken;
 
+        traceENTER_xTimerGenericCommandFromTask( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait );
+
         configASSERT( xTimer );
 
         /* Send a message to the timer service task to perform a particular action
@@ -427,6 +442,8 @@
             mtCOVERAGE_TEST_MARKER();
         }
 
+        traceRETURN_xTimerGenericCommandFromTask( xReturn );
+
         return xReturn;
     }
 /*-----------------------------------------------------------*/
@@ -442,6 +459,8 @@
 
         ( void ) xTicksToWait;
 
+        traceENTER_xTimerGenericCommandFromISR( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait );
+
         configASSERT( xTimer );
 
         /* Send a message to the timer service task to perform a particular action
@@ -467,15 +486,22 @@
             mtCOVERAGE_TEST_MARKER();
         }
 
+        traceRETURN_xTimerGenericCommandFromISR( xReturn );
+
         return xReturn;
     }
 /*-----------------------------------------------------------*/
 
     TaskHandle_t xTimerGetTimerDaemonTaskHandle( void )
     {
+        traceENTER_xTimerGetTimerDaemonTaskHandle();
+
         /* If xTimerGetTimerDaemonTaskHandle() is called before the scheduler has been
          * started, then xTimerTaskHandle will be NULL. */
         configASSERT( ( xTimerTaskHandle != NULL ) );
+
+        traceRETURN_xTimerGetTimerDaemonTaskHandle( xTimerTaskHandle );
+
         return xTimerTaskHandle;
     }
 /*-----------------------------------------------------------*/
@@ -484,7 +510,12 @@
     {
         Timer_t * pxTimer = xTimer;
 
+        traceENTER_xTimerGetPeriod( xTimer );
+
         configASSERT( xTimer );
+
+        traceRETURN_xTimerGetPeriod( pxTimer->xTimerPeriodInTicks );
+
         return pxTimer->xTimerPeriodInTicks;
     }
 /*-----------------------------------------------------------*/
@@ -494,6 +525,8 @@
     {
         Timer_t * pxTimer = xTimer;
 
+        traceENTER_vTimerSetReloadMode( xTimer, xAutoReload );
+
         configASSERT( xTimer );
         taskENTER_CRITICAL();
         {
@@ -507,6 +540,8 @@
             }
         }
         taskEXIT_CRITICAL();
+
+        traceRETURN_vTimerSetReloadMode();
     }
 /*-----------------------------------------------------------*/
 
@@ -515,6 +550,8 @@
         Timer_t * pxTimer = xTimer;
         BaseType_t xReturn;
 
+        traceENTER_xTimerGetReloadMode( xTimer );
+
         configASSERT( xTimer );
         taskENTER_CRITICAL();
         {
@@ -531,12 +568,22 @@
         }
         taskEXIT_CRITICAL();
 
+        traceRETURN_xTimerGetReloadMode( xReturn );
+
         return xReturn;
     }
 
     UBaseType_t uxTimerGetReloadMode( TimerHandle_t xTimer )
     {
-        return ( UBaseType_t ) xTimerGetReloadMode( xTimer );
+        UBaseType_t uxReturn;
+
+        traceENTER_uxTimerGetReloadMode( xTimer );
+
+        uxReturn = ( UBaseType_t ) xTimerGetReloadMode( xTimer );
+
+        traceRETURN_uxTimerGetReloadMode( uxReturn );
+
+        return uxReturn;
     }
 /*-----------------------------------------------------------*/
 
@@ -545,8 +592,13 @@
         Timer_t * pxTimer = xTimer;
         TickType_t xReturn;
 
+        traceENTER_xTimerGetExpiryTime( xTimer );
+
         configASSERT( xTimer );
         xReturn = listGET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ) );
+
+        traceRETURN_xTimerGetExpiryTime( xReturn );
+
         return xReturn;
     }
 /*-----------------------------------------------------------*/
@@ -558,6 +610,8 @@
             BaseType_t xReturn;
             Timer_t * pxTimer = xTimer;
 
+            traceENTER_xTimerGetStaticBuffer( xTimer, ppxTimerBuffer );
+
             configASSERT( ppxTimerBuffer != NULL );
 
             if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) != 0 )
@@ -570,6 +624,8 @@
                 xReturn = pdFALSE;
             }
 
+            traceRETURN_xTimerGetStaticBuffer( xReturn );
+
             return xReturn;
         }
     #endif /* configSUPPORT_STATIC_ALLOCATION */
@@ -579,7 +635,12 @@
     {
         Timer_t * pxTimer = xTimer;
 
+        traceENTER_pcTimerGetName( xTimer );
+
         configASSERT( xTimer );
+
+        traceRETURN_pcTimerGetName( pxTimer->pcTimerName );
+
         return pxTimer->pcTimerName;
     }
 /*-----------------------------------------------------------*/
@@ -1057,6 +1118,8 @@
         BaseType_t xReturn;
         Timer_t * pxTimer = xTimer;
 
+        traceENTER_xTimerIsTimerActive( xTimer );
+
         configASSERT( xTimer );
 
         /* Is the timer in the list of active timers? */
@@ -1073,6 +1136,8 @@
         }
         taskEXIT_CRITICAL();
 
+        traceRETURN_xTimerIsTimerActive( xReturn );
+
         return xReturn;
     } /*lint !e818 Can't be pointer to const due to the typedef. */
 /*-----------------------------------------------------------*/
@@ -1082,6 +1147,8 @@
         Timer_t * const pxTimer = xTimer;
         void * pvReturn;
 
+        traceENTER_pvTimerGetTimerID( xTimer );
+
         configASSERT( xTimer );
 
         taskENTER_CRITICAL();
@@ -1090,6 +1157,8 @@
         }
         taskEXIT_CRITICAL();
 
+        traceRETURN_pvTimerGetTimerID( pvReturn );
+
         return pvReturn;
     }
 /*-----------------------------------------------------------*/
@@ -1099,6 +1168,8 @@
     {
         Timer_t * const pxTimer = xTimer;
 
+        traceENTER_vTimerSetTimerID( xTimer, pvNewID );
+
         configASSERT( xTimer );
 
         taskENTER_CRITICAL();
@@ -1106,6 +1177,8 @@
             pxTimer->pvTimerID = pvNewID;
         }
         taskEXIT_CRITICAL();
+
+        traceRETURN_vTimerSetTimerID();
     }
 /*-----------------------------------------------------------*/
 
@@ -1119,6 +1192,8 @@
             DaemonTaskMessage_t xMessage;
             BaseType_t xReturn;
 
+            traceENTER_xTimerPendFunctionCallFromISR( xFunctionToPend, pvParameter1, ulParameter2, pxHigherPriorityTaskWoken );
+
             /* Complete the message with the function parameters and post it to the
              * daemon task. */
             xMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR;
@@ -1129,6 +1204,7 @@
             xReturn = xQueueSendFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );
 
             tracePEND_FUNC_CALL_FROM_ISR( xFunctionToPend, pvParameter1, ulParameter2, xReturn );
+            traceRETURN_xTimerPendFunctionCallFromISR( xReturn );
 
             return xReturn;
         }
@@ -1146,6 +1222,8 @@
             DaemonTaskMessage_t xMessage;
             BaseType_t xReturn;
 
+            traceENTER_xTimerPendFunctionCall( xFunctionToPend, pvParameter1, ulParameter2, xTicksToWait );
+
             /* This function can only be called after a timer has been created or
              * after the scheduler has been started because, until then, the timer
              * queue does not exist. */
@@ -1161,6 +1239,7 @@
             xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );
 
             tracePEND_FUNC_CALL( xFunctionToPend, pvParameter1, ulParameter2, xReturn );
+            traceRETURN_xTimerPendFunctionCall( xReturn );
 
             return xReturn;
         }
@@ -1172,6 +1251,10 @@
 
         UBaseType_t uxTimerGetTimerNumber( TimerHandle_t xTimer )
         {
+            traceENTER_uxTimerGetTimerNumber( xTimer );
+
+            traceRETURN_uxTimerGetTimerNumber( ( ( Timer_t * ) xTimer )->uxTimerNumber );
+
             return ( ( Timer_t * ) xTimer )->uxTimerNumber;
         }
 
@@ -1183,7 +1266,11 @@
         void vTimerSetTimerNumber( TimerHandle_t xTimer,
                                    UBaseType_t uxTimerNumber )
         {
+            traceENTER_vTimerSetTimerNumber( xTimer, uxTimerNumber );
+
             ( ( Timer_t * ) xTimer )->uxTimerNumber = uxTimerNumber;
+
+            traceRETURN_vTimerSetTimerNumber();
         }
 
     #endif /* configUSE_TRACE_FACILITY */

From d43062ba7862f6c354ca414b411958ce12a7187f Mon Sep 17 00:00:00 2001
From: Boris van der Meer <borisvandermeer@hotmail.com>
Date: Wed, 20 Sep 2023 12:49:42 +0200
Subject: [PATCH 065/424] Add trace hook macro for most ports (#794)

Add trace hook macro for most ports

In pull request #659 we introduced better support for tracing
tools like systemview. This patchset adds support for more
ports as requested in the original pull request.
---
 portable/ARMv8M/non_secure/port.c              |  6 ++++++
 portable/ARMv8M/non_secure/portmacrocommon.h   | 16 +++++++++++++---
 portable/CCS/ARM_CM3/port.c                    |  7 +++++++
 portable/CCS/ARM_CM3/portmacro.h               | 16 ++++++++++++++--
 portable/CCS/ARM_CM4F/port.c                   |  7 +++++++
 portable/CCS/ARM_CM4F/portmacro.h              | 16 ++++++++++++++--
 portable/CodeWarrior/ColdFire_V1/portmacro.h   | 15 +++++++++++++--
 portable/CodeWarrior/ColdFire_V2/portmacro.h   | 15 +++++++++++++--
 portable/GCC/ARM_CM0/port.c                    |  6 ++++++
 portable/GCC/ARM_CM0/portmacro.h               | 16 +++++++++++++---
 portable/GCC/ARM_CM23/non_secure/port.c        |  6 ++++++
 .../GCC/ARM_CM23/non_secure/portmacrocommon.h  | 16 +++++++++++++---
 portable/GCC/ARM_CM23_NTZ/non_secure/port.c    |  6 ++++++
 .../ARM_CM23_NTZ/non_secure/portmacrocommon.h  | 16 +++++++++++++---
 portable/GCC/ARM_CM3/port.c                    |  7 +++++++
 portable/GCC/ARM_CM3/portmacro.h               | 16 ++++++++++++++--
 portable/GCC/ARM_CM33/non_secure/port.c        |  6 ++++++
 .../GCC/ARM_CM33/non_secure/portmacrocommon.h  | 16 +++++++++++++---
 portable/GCC/ARM_CM33_NTZ/non_secure/port.c    |  6 ++++++
 .../ARM_CM33_NTZ/non_secure/portmacrocommon.h  | 16 +++++++++++++---
 portable/GCC/ARM_CM35P/non_secure/port.c       |  6 ++++++
 .../GCC/ARM_CM35P/non_secure/portmacrocommon.h | 16 +++++++++++++---
 portable/GCC/ARM_CM35P_NTZ/non_secure/port.c   |  6 ++++++
 .../ARM_CM35P_NTZ/non_secure/portmacrocommon.h | 16 +++++++++++++---
 portable/GCC/ARM_CM3_MPU/port.c                |  6 ++++++
 portable/GCC/ARM_CM3_MPU/portmacro.h           | 16 +++++++++++++---
 portable/GCC/ARM_CM4F/port.c                   |  7 +++++++
 portable/GCC/ARM_CM4F/portmacro.h              | 16 ++++++++++++++--
 portable/GCC/ARM_CM4_MPU/port.c                |  6 ++++++
 portable/GCC/ARM_CM4_MPU/portmacro.h           | 16 +++++++++++++---
 portable/GCC/ARM_CM55/non_secure/port.c        |  6 ++++++
 .../GCC/ARM_CM55/non_secure/portmacrocommon.h  | 16 +++++++++++++---
 portable/GCC/ARM_CM55_NTZ/non_secure/port.c    |  6 ++++++
 .../ARM_CM55_NTZ/non_secure/portmacrocommon.h  | 16 +++++++++++++---
 portable/GCC/ARM_CM7/r0p1/portmacro.h          | 15 ++++++++++++---
 portable/GCC/ARM_CM85/non_secure/port.c        |  6 ++++++
 .../GCC/ARM_CM85/non_secure/portmacrocommon.h  | 16 +++++++++++++---
 portable/GCC/ARM_CM85_NTZ/non_secure/port.c    |  6 ++++++
 .../ARM_CM85_NTZ/non_secure/portmacrocommon.h  | 16 +++++++++++++---
 portable/GCC/ColdFire_V2/portmacro.h           | 14 +++++++++++++-
 portable/GCC/NiosII/portmacro.h                | 17 ++++++++++++++---
 portable/GCC/RISC-V/portmacro.h                | 18 +++++++++++++++---
 portable/GCC/STR75x/portmacro.h                |  5 +++++
 portable/IAR/ARM_CM0/port.c                    |  6 ++++++
 portable/IAR/ARM_CM0/portmacro.h               | 18 +++++++++++++++---
 portable/IAR/ARM_CM23/non_secure/port.c        |  6 ++++++
 .../IAR/ARM_CM23/non_secure/portmacrocommon.h  | 16 +++++++++++++---
 portable/IAR/ARM_CM23_NTZ/non_secure/port.c    |  6 ++++++
 .../ARM_CM23_NTZ/non_secure/portmacrocommon.h  | 16 +++++++++++++---
 portable/IAR/ARM_CM3/port.c                    |  7 +++++++
 portable/IAR/ARM_CM3/portmacro.h               | 16 ++++++++++++++--
 portable/IAR/ARM_CM33/non_secure/port.c        |  6 ++++++
 .../IAR/ARM_CM33/non_secure/portmacrocommon.h  | 16 +++++++++++++---
 portable/IAR/ARM_CM33_NTZ/non_secure/port.c    |  6 ++++++
 .../ARM_CM33_NTZ/non_secure/portmacrocommon.h  | 16 +++++++++++++---
 portable/IAR/ARM_CM35P/non_secure/port.c       |  6 ++++++
 .../IAR/ARM_CM35P/non_secure/portmacrocommon.h | 16 +++++++++++++---
 portable/IAR/ARM_CM35P_NTZ/non_secure/port.c   |  6 ++++++
 .../ARM_CM35P_NTZ/non_secure/portmacrocommon.h | 16 +++++++++++++---
 portable/IAR/ARM_CM4F/port.c                   |  7 +++++++
 portable/IAR/ARM_CM4F/portmacro.h              | 16 ++++++++++++++--
 portable/IAR/ARM_CM4F_MPU/port.c               |  7 +++++++
 portable/IAR/ARM_CM4F_MPU/portmacro.h          | 16 ++++++++++++++--
 portable/IAR/ARM_CM55/non_secure/port.c        |  6 ++++++
 .../IAR/ARM_CM55/non_secure/portmacrocommon.h  | 16 +++++++++++++---
 portable/IAR/ARM_CM55_NTZ/non_secure/port.c    |  6 ++++++
 .../ARM_CM55_NTZ/non_secure/portmacrocommon.h  | 16 +++++++++++++---
 portable/IAR/ARM_CM7/r0p1/port.c               |  7 +++++++
 portable/IAR/ARM_CM7/r0p1/portmacro.h          | 16 ++++++++++++++--
 portable/IAR/ARM_CM85/non_secure/port.c        |  6 ++++++
 .../IAR/ARM_CM85/non_secure/portmacrocommon.h  | 16 +++++++++++++---
 portable/IAR/ARM_CM85_NTZ/non_secure/port.c    |  6 ++++++
 .../ARM_CM85_NTZ/non_secure/portmacrocommon.h  | 16 +++++++++++++---
 portable/IAR/AtmelSAM7S64/portmacro.h          |  5 +++++
 portable/IAR/AtmelSAM9XE/portmacro.h           |  5 +++++
 portable/IAR/LPC2000/portmacro.h               |  5 +++++
 portable/IAR/RISC-V/portmacro.h                | 18 +++++++++++++++---
 portable/IAR/STR71x/portmacro.h                |  5 +++++
 portable/IAR/STR75x/portmacro.h                |  5 +++++
 portable/IAR/STR91x/portmacro.h                |  5 +++++
 portable/MPLAB/PIC32MEC14xx/portmacro.h        | 14 +++++++++++++-
 portable/MPLAB/PIC32MX/portmacro.h             | 14 +++++++++++++-
 portable/MPLAB/PIC32MZ/portmacro.h             | 14 +++++++++++++-
 portable/MikroC/ARM_CM4F/port.c                |  7 +++++++
 portable/MikroC/ARM_CM4F/portmacro.h           | 16 ++++++++++++++--
 portable/RVDS/ARM_CM0/port.c                   |  6 ++++++
 portable/RVDS/ARM_CM0/portmacro.h              | 16 +++++++++++++---
 portable/RVDS/ARM_CM3/port.c                   |  7 +++++++
 portable/RVDS/ARM_CM3/portmacro.h              | 16 ++++++++++++++--
 portable/RVDS/ARM_CM4F/port.c                  |  7 +++++++
 portable/RVDS/ARM_CM4F/portmacro.h             | 16 ++++++++++++++--
 portable/RVDS/ARM_CM4_MPU/port.c               |  6 ++++++
 portable/RVDS/ARM_CM4_MPU/portmacro.h          | 16 +++++++++++++---
 portable/RVDS/ARM_CM7/r0p1/port.c              |  7 +++++++
 portable/RVDS/ARM_CM7/r0p1/portmacro.h         | 16 ++++++++++++++--
 portable/Tasking/ARM_CM4F/port.c               |  6 ++++++
 portable/Tasking/ARM_CM4F/portmacro.h          | 18 +++++++++++++++---
 portable/ThirdParty/CDK/T-HEAD_CK802/port.c    |  6 ++++++
 .../ThirdParty/CDK/T-HEAD_CK802/portmacro.h    |  5 +++++
 portable/ThirdParty/GCC/Posix/portmacro.h      | 18 +++++++++++++++---
 .../ThirdParty/GCC/RP2040/include/portmacro.h  | 18 +++++++++++++++---
 portable/ThirdParty/GCC/RP2040/port.c          |  6 ++++++
 .../ThirdParty/GCC/Xtensa_ESP32/port_systick.c |  1 +
 103 files changed, 1005 insertions(+), 134 deletions(-)

diff --git a/portable/ARMv8M/non_secure/port.c b/portable/ARMv8M/non_secure/port.c
index e8ad8cf4c..0ba29f9b4 100644
--- a/portable/ARMv8M/non_secure/port.c
+++ b/portable/ARMv8M/non_secure/port.c
@@ -977,13 +977,19 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
     uint32_t ulPreviousMask;
 
     ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+    traceISR_ENTER();
     {
         /* Increment the RTOS tick. */
         if( xTaskIncrementTick() != pdFALSE )
         {
+            traceISR_EXIT_TO_SCHEDULER();
             /* Pend a context switch. */
             portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
         }
+        else
+        {
+            traceISR_EXIT();
+        }
     }
     portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
 }
diff --git a/portable/ARMv8M/non_secure/portmacrocommon.h b/portable/ARMv8M/non_secure/portmacrocommon.h
index cc2adb7fd..96a28ca4e 100644
--- a/portable/ARMv8M/non_secure/portmacrocommon.h
+++ b/portable/ARMv8M/non_secure/portmacrocommon.h
@@ -338,9 +338,19 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portYIELD()    vPortYield()
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )                                 \
-    do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
-    while( 0 )
+#define portEND_SWITCHING_ISR( xSwitchRequired )            \
+    do                                                      \
+    {                                                       \
+        if( xSwitchRequired )                               \
+        {                                                   \
+            traceISR_EXIT_TO_SCHEDULER();                   \
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+        }                                                   \
+        else                                                \
+        {                                                   \
+            traceISR_EXIT();                                \
+        }                                                   \
+    } while( 0 )
 #define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/CCS/ARM_CM3/port.c b/portable/CCS/ARM_CM3/port.c
index a1353c8bc..e55b01dbd 100644
--- a/portable/CCS/ARM_CM3/port.c
+++ b/portable/CCS/ARM_CM3/port.c
@@ -363,14 +363,21 @@ void xPortSysTickHandler( void )
      * save and then restore the interrupt mask value as its value is already
      * known. */
     ( void ) portSET_INTERRUPT_MASK_FROM_ISR();
+    traceISR_ENTER();
     {
         /* Increment the RTOS tick. */
         if( xTaskIncrementTick() != pdFALSE )
         {
+            traceISR_EXIT_TO_SCHEDULER();
+
             /* A context switch is required.  Context switching is performed in
              * the PendSV interrupt.  Pend the PendSV interrupt. */
             portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
         }
+        else
+        {
+            traceISR_EXIT();
+        }
     }
     portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );
 }
diff --git a/portable/CCS/ARM_CM3/portmacro.h b/portable/CCS/ARM_CM3/portmacro.h
index 6c9edc39e..1d9c8ff75 100644
--- a/portable/CCS/ARM_CM3/portmacro.h
+++ b/portable/CCS/ARM_CM3/portmacro.h
@@ -97,8 +97,20 @@ typedef unsigned long    UBaseType_t;
 
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired != pdFALSE ) portYIELD( ); } while( 0 )
-#define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+    do                                           \
+    {                                            \
+        if( xSwitchRequired != pdFALSE )         \
+        {                                        \
+            traceISR_EXIT_TO_SCHEDULER();        \
+            portYIELD();                         \
+        }                                        \
+        else                                     \
+        {                                        \
+            traceISR_EXIT();                     \
+        }                                        \
+    } while( 0 )
+#define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
 
 /*-----------------------------------------------------------*/
 
diff --git a/portable/CCS/ARM_CM4F/port.c b/portable/CCS/ARM_CM4F/port.c
index fa444d593..6cba0913e 100644
--- a/portable/CCS/ARM_CM4F/port.c
+++ b/portable/CCS/ARM_CM4F/port.c
@@ -388,14 +388,21 @@ void xPortSysTickHandler( void )
      * save and then restore the interrupt mask value as its value is already
      * known. */
     ( void ) portSET_INTERRUPT_MASK_FROM_ISR();
+    traceISR_ENTER();
     {
         /* Increment the RTOS tick. */
         if( xTaskIncrementTick() != pdFALSE )
         {
+            traceISR_EXIT_TO_SCHEDULER();
+
             /* A context switch is required.  Context switching is performed in
              * the PendSV interrupt.  Pend the PendSV interrupt. */
             portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
         }
+        else
+        {
+            traceISR_EXIT();
+        }
     }
     portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );
 }
diff --git a/portable/CCS/ARM_CM4F/portmacro.h b/portable/CCS/ARM_CM4F/portmacro.h
index ba4f7490d..5d01094c5 100644
--- a/portable/CCS/ARM_CM4F/portmacro.h
+++ b/portable/CCS/ARM_CM4F/portmacro.h
@@ -91,8 +91,20 @@ typedef unsigned long    UBaseType_t;
 
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired != pdFALSE ) portYIELD( ); } while( 0 )
-#define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+    do                                           \
+    {                                            \
+        if( xSwitchRequired != pdFALSE )         \
+        {                                        \
+            traceISR_EXIT_TO_SCHEDULER();        \
+            portYIELD();                         \
+        }                                        \
+        else                                     \
+        {                                        \
+            traceISR_EXIT();                     \
+        }                                        \
+    } while( 0 )
+#define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
 
 /*-----------------------------------------------------------*/
 
diff --git a/portable/CodeWarrior/ColdFire_V1/portmacro.h b/portable/CodeWarrior/ColdFire_V1/portmacro.h
index 0f62912d4..d72637801 100644
--- a/portable/CodeWarrior/ColdFire_V1/portmacro.h
+++ b/portable/CodeWarrior/ColdFire_V1/portmacro.h
@@ -106,8 +106,19 @@ extern void vPortClearInterruptMaskFromISR( UBaseType_t );
 #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 /*-----------------------------------------------------------*/
 
-#define portEND_SWITCHING_ISR( xSwitchRequired )              do { if( xSwitchRequired != pdFALSE ) { portYIELD(); } } while( 0 )
-
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+    do                                           \
+    {                                            \
+        if( xSwitchRequired != pdFALSE )         \
+        {                                        \
+            traceISR_EXIT_TO_SCHEDULER();        \
+            portYIELD();                         \
+        }                                        \
+        else                                     \
+        {                                        \
+            traceISR_EXIT();                     \
+        }                                        \
+    } while( 0 )
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/CodeWarrior/ColdFire_V2/portmacro.h b/portable/CodeWarrior/ColdFire_V2/portmacro.h
index a815e6469..e367e0774 100644
--- a/portable/CodeWarrior/ColdFire_V2/portmacro.h
+++ b/portable/CodeWarrior/ColdFire_V2/portmacro.h
@@ -105,8 +105,19 @@ extern void vPortClearInterruptMaskFromISR( UBaseType_t );
 #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 /*-----------------------------------------------------------*/
 
-#define portEND_SWITCHING_ISR( xSwitchRequired )              do { if( xSwitchRequired != pdFALSE ) { portYIELD(); } } while( 0 )
-
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+    do                                           \
+    {                                            \
+        if( xSwitchRequired != pdFALSE )         \
+        {                                        \
+            traceISR_EXIT_TO_SCHEDULER();        \
+            portYIELD();                         \
+        }                                        \
+        else                                     \
+        {                                        \
+            traceISR_EXIT();                     \
+        }                                        \
+    } while( 0 )
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/GCC/ARM_CM0/port.c b/portable/GCC/ARM_CM0/port.c
index e67a10fb5..93e6d0489 100644
--- a/portable/GCC/ARM_CM0/port.c
+++ b/portable/GCC/ARM_CM0/port.c
@@ -375,13 +375,19 @@ void xPortSysTickHandler( void )
     uint32_t ulPreviousMask;
 
     ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+    traceISR_ENTER();
     {
         /* Increment the RTOS tick. */
         if( xTaskIncrementTick() != pdFALSE )
         {
+            traceISR_EXIT_TO_SCHEDULER();
             /* Pend a context switch. */
             portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
         }
+        else
+        {
+            traceISR_EXIT();
+        }
     }
     portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
 }
diff --git a/portable/GCC/ARM_CM0/portmacro.h b/portable/GCC/ARM_CM0/portmacro.h
index df571eb53..3c55b5d0c 100644
--- a/portable/GCC/ARM_CM0/portmacro.h
+++ b/portable/GCC/ARM_CM0/portmacro.h
@@ -87,9 +87,19 @@ extern void vPortYield( void );
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
 #define portYIELD()                vPortYield()
-#define portEND_SWITCHING_ISR( xSwitchRequired )                                 \
-    do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
-    while( 0 )
+#define portEND_SWITCHING_ISR( xSwitchRequired )            \
+    do                                                      \
+    {                                                       \
+        if( xSwitchRequired )                               \
+        {                                                   \
+            traceISR_EXIT_TO_SCHEDULER();                   \
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+        }                                                   \
+        else                                                \
+        {                                                   \
+            traceISR_EXIT();                                \
+        }                                                   \
+    } while( 0 )
 #define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/GCC/ARM_CM23/non_secure/port.c b/portable/GCC/ARM_CM23/non_secure/port.c
index e8ad8cf4c..0ba29f9b4 100644
--- a/portable/GCC/ARM_CM23/non_secure/port.c
+++ b/portable/GCC/ARM_CM23/non_secure/port.c
@@ -977,13 +977,19 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
     uint32_t ulPreviousMask;
 
     ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+    traceISR_ENTER();
     {
         /* Increment the RTOS tick. */
         if( xTaskIncrementTick() != pdFALSE )
         {
+            traceISR_EXIT_TO_SCHEDULER();
             /* Pend a context switch. */
             portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
         }
+        else
+        {
+            traceISR_EXIT();
+        }
     }
     portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
 }
diff --git a/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h
index cc2adb7fd..96a28ca4e 100644
--- a/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h
@@ -338,9 +338,19 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portYIELD()    vPortYield()
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )                                 \
-    do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
-    while( 0 )
+#define portEND_SWITCHING_ISR( xSwitchRequired )            \
+    do                                                      \
+    {                                                       \
+        if( xSwitchRequired )                               \
+        {                                                   \
+            traceISR_EXIT_TO_SCHEDULER();                   \
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+        }                                                   \
+        else                                                \
+        {                                                   \
+            traceISR_EXIT();                                \
+        }                                                   \
+    } while( 0 )
 #define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
index e8ad8cf4c..0ba29f9b4 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
@@ -977,13 +977,19 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
     uint32_t ulPreviousMask;
 
     ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+    traceISR_ENTER();
     {
         /* Increment the RTOS tick. */
         if( xTaskIncrementTick() != pdFALSE )
         {
+            traceISR_EXIT_TO_SCHEDULER();
             /* Pend a context switch. */
             portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
         }
+        else
+        {
+            traceISR_EXIT();
+        }
     }
     portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
 }
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h
index cc2adb7fd..96a28ca4e 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h
@@ -338,9 +338,19 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portYIELD()    vPortYield()
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )                                 \
-    do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
-    while( 0 )
+#define portEND_SWITCHING_ISR( xSwitchRequired )            \
+    do                                                      \
+    {                                                       \
+        if( xSwitchRequired )                               \
+        {                                                   \
+            traceISR_EXIT_TO_SCHEDULER();                   \
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+        }                                                   \
+        else                                                \
+        {                                                   \
+            traceISR_EXIT();                                \
+        }                                                   \
+    } while( 0 )
 #define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/GCC/ARM_CM3/port.c b/portable/GCC/ARM_CM3/port.c
index df633d11e..483f81324 100644
--- a/portable/GCC/ARM_CM3/port.c
+++ b/portable/GCC/ARM_CM3/port.c
@@ -452,14 +452,21 @@ void xPortSysTickHandler( void )
      * save and then restore the interrupt mask value as its value is already
      * known. */
     portDISABLE_INTERRUPTS();
+    traceISR_ENTER();
     {
         /* Increment the RTOS tick. */
         if( xTaskIncrementTick() != pdFALSE )
         {
+            traceISR_EXIT_TO_SCHEDULER();
+
             /* A context switch is required.  Context switching is performed in
              * the PendSV interrupt.  Pend the PendSV interrupt. */
             portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
         }
+        else
+        {
+            traceISR_EXIT();
+        }
     }
     portENABLE_INTERRUPTS();
 }
diff --git a/portable/GCC/ARM_CM3/portmacro.h b/portable/GCC/ARM_CM3/portmacro.h
index 0d6782270..5d91d2139 100644
--- a/portable/GCC/ARM_CM3/portmacro.h
+++ b/portable/GCC/ARM_CM3/portmacro.h
@@ -95,8 +95,20 @@ typedef unsigned long    UBaseType_t;
 
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired != pdFALSE ) portYIELD( ); } while( 0 )
-#define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+    do                                           \
+    {                                            \
+        if( xSwitchRequired != pdFALSE )         \
+        {                                        \
+            traceISR_EXIT_TO_SCHEDULER();        \
+            portYIELD();                         \
+        }                                        \
+        else                                     \
+        {                                        \
+            traceISR_EXIT();                     \
+        }                                        \
+    } while( 0 )
+#define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
 /* Critical section management. */
diff --git a/portable/GCC/ARM_CM33/non_secure/port.c b/portable/GCC/ARM_CM33/non_secure/port.c
index e8ad8cf4c..0ba29f9b4 100644
--- a/portable/GCC/ARM_CM33/non_secure/port.c
+++ b/portable/GCC/ARM_CM33/non_secure/port.c
@@ -977,13 +977,19 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
     uint32_t ulPreviousMask;
 
     ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+    traceISR_ENTER();
     {
         /* Increment the RTOS tick. */
         if( xTaskIncrementTick() != pdFALSE )
         {
+            traceISR_EXIT_TO_SCHEDULER();
             /* Pend a context switch. */
             portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
         }
+        else
+        {
+            traceISR_EXIT();
+        }
     }
     portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
 }
diff --git a/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h
index cc2adb7fd..96a28ca4e 100644
--- a/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h
@@ -338,9 +338,19 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portYIELD()    vPortYield()
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )                                 \
-    do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
-    while( 0 )
+#define portEND_SWITCHING_ISR( xSwitchRequired )            \
+    do                                                      \
+    {                                                       \
+        if( xSwitchRequired )                               \
+        {                                                   \
+            traceISR_EXIT_TO_SCHEDULER();                   \
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+        }                                                   \
+        else                                                \
+        {                                                   \
+            traceISR_EXIT();                                \
+        }                                                   \
+    } while( 0 )
 #define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
index e8ad8cf4c..0ba29f9b4 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
@@ -977,13 +977,19 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
     uint32_t ulPreviousMask;
 
     ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+    traceISR_ENTER();
     {
         /* Increment the RTOS tick. */
         if( xTaskIncrementTick() != pdFALSE )
         {
+            traceISR_EXIT_TO_SCHEDULER();
             /* Pend a context switch. */
             portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
         }
+        else
+        {
+            traceISR_EXIT();
+        }
     }
     portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
 }
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h
index cc2adb7fd..96a28ca4e 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h
@@ -338,9 +338,19 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portYIELD()    vPortYield()
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )                                 \
-    do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
-    while( 0 )
+#define portEND_SWITCHING_ISR( xSwitchRequired )            \
+    do                                                      \
+    {                                                       \
+        if( xSwitchRequired )                               \
+        {                                                   \
+            traceISR_EXIT_TO_SCHEDULER();                   \
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+        }                                                   \
+        else                                                \
+        {                                                   \
+            traceISR_EXIT();                                \
+        }                                                   \
+    } while( 0 )
 #define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/GCC/ARM_CM35P/non_secure/port.c b/portable/GCC/ARM_CM35P/non_secure/port.c
index e8ad8cf4c..0ba29f9b4 100644
--- a/portable/GCC/ARM_CM35P/non_secure/port.c
+++ b/portable/GCC/ARM_CM35P/non_secure/port.c
@@ -977,13 +977,19 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
     uint32_t ulPreviousMask;
 
     ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+    traceISR_ENTER();
     {
         /* Increment the RTOS tick. */
         if( xTaskIncrementTick() != pdFALSE )
         {
+            traceISR_EXIT_TO_SCHEDULER();
             /* Pend a context switch. */
             portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
         }
+        else
+        {
+            traceISR_EXIT();
+        }
     }
     portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
 }
diff --git a/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h
index cc2adb7fd..96a28ca4e 100644
--- a/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h
@@ -338,9 +338,19 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portYIELD()    vPortYield()
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )                                 \
-    do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
-    while( 0 )
+#define portEND_SWITCHING_ISR( xSwitchRequired )            \
+    do                                                      \
+    {                                                       \
+        if( xSwitchRequired )                               \
+        {                                                   \
+            traceISR_EXIT_TO_SCHEDULER();                   \
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+        }                                                   \
+        else                                                \
+        {                                                   \
+            traceISR_EXIT();                                \
+        }                                                   \
+    } while( 0 )
 #define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c b/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
index e8ad8cf4c..0ba29f9b4 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
@@ -977,13 +977,19 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
     uint32_t ulPreviousMask;
 
     ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+    traceISR_ENTER();
     {
         /* Increment the RTOS tick. */
         if( xTaskIncrementTick() != pdFALSE )
         {
+            traceISR_EXIT_TO_SCHEDULER();
             /* Pend a context switch. */
             portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
         }
+        else
+        {
+            traceISR_EXIT();
+        }
     }
     portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
 }
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
index cc2adb7fd..96a28ca4e 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
@@ -338,9 +338,19 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portYIELD()    vPortYield()
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )                                 \
-    do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
-    while( 0 )
+#define portEND_SWITCHING_ISR( xSwitchRequired )            \
+    do                                                      \
+    {                                                       \
+        if( xSwitchRequired )                               \
+        {                                                   \
+            traceISR_EXIT_TO_SCHEDULER();                   \
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+        }                                                   \
+        else                                                \
+        {                                                   \
+            traceISR_EXIT();                                \
+        }                                                   \
+    } while( 0 )
 #define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/GCC/ARM_CM3_MPU/port.c b/portable/GCC/ARM_CM3_MPU/port.c
index a524f2b2a..3c46dfde8 100644
--- a/portable/GCC/ARM_CM3_MPU/port.c
+++ b/portable/GCC/ARM_CM3_MPU/port.c
@@ -1057,13 +1057,19 @@ void xPortSysTickHandler( void )
     uint32_t ulDummy;
 
     ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
+    traceISR_ENTER();
     {
         /* Increment the RTOS tick. */
         if( xTaskIncrementTick() != pdFALSE )
         {
+            traceISR_EXIT_TO_SCHEDULER();
             /* Pend a context switch. */
             portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
         }
+        else
+        {
+            traceISR_EXIT();
+        }
     }
     portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
 }
diff --git a/portable/GCC/ARM_CM3_MPU/portmacro.h b/portable/GCC/ARM_CM3_MPU/portmacro.h
index c844a8e6f..796e5253c 100644
--- a/portable/GCC/ARM_CM3_MPU/portmacro.h
+++ b/portable/GCC/ARM_CM3_MPU/portmacro.h
@@ -183,9 +183,19 @@ typedef struct MPU_SETTINGS
 
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )                                 \
-    do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
-    while( 0 )
+#define portEND_SWITCHING_ISR( xSwitchRequired )            \
+    do                                                      \
+    {                                                       \
+        if( xSwitchRequired )                               \
+        {                                                   \
+            traceISR_EXIT_TO_SCHEDULER();                   \
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+        }                                                   \
+        else                                                \
+        {                                                   \
+            traceISR_EXIT();                                \
+        }                                                   \
+    } while( 0 )
 #define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/GCC/ARM_CM4F/port.c b/portable/GCC/ARM_CM4F/port.c
index e5ea4e336..3846a50f6 100644
--- a/portable/GCC/ARM_CM4F/port.c
+++ b/portable/GCC/ARM_CM4F/port.c
@@ -521,14 +521,21 @@ void xPortSysTickHandler( void )
      * save and then restore the interrupt mask value as its value is already
      * known. */
     portDISABLE_INTERRUPTS();
+    traceISR_ENTER();
     {
         /* Increment the RTOS tick. */
         if( xTaskIncrementTick() != pdFALSE )
         {
+            traceISR_EXIT_TO_SCHEDULER();
+
             /* A context switch is required.  Context switching is performed in
              * the PendSV interrupt.  Pend the PendSV interrupt. */
             portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
         }
+        else
+        {
+            traceISR_EXIT();
+        }
     }
     portENABLE_INTERRUPTS();
 }
diff --git a/portable/GCC/ARM_CM4F/portmacro.h b/portable/GCC/ARM_CM4F/portmacro.h
index 5d70c0e22..40b2d03e9 100644
--- a/portable/GCC/ARM_CM4F/portmacro.h
+++ b/portable/GCC/ARM_CM4F/portmacro.h
@@ -98,8 +98,20 @@ typedef unsigned long    UBaseType_t;
 
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired != pdFALSE ) portYIELD( ); } while( 0 )
-#define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+    do                                           \
+    {                                            \
+        if( xSwitchRequired != pdFALSE )         \
+        {                                        \
+            traceISR_EXIT_TO_SCHEDULER();        \
+            portYIELD();                         \
+        }                                        \
+        else                                     \
+        {                                        \
+            traceISR_EXIT();                     \
+        }                                        \
+    } while( 0 )
+#define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
 /* Critical section management. */
diff --git a/portable/GCC/ARM_CM4_MPU/port.c b/portable/GCC/ARM_CM4_MPU/port.c
index a59a651f4..861c400cd 100644
--- a/portable/GCC/ARM_CM4_MPU/port.c
+++ b/portable/GCC/ARM_CM4_MPU/port.c
@@ -1203,13 +1203,19 @@ void xPortSysTickHandler( void )
     uint32_t ulDummy;
 
     ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
+    traceISR_ENTER();
     {
         /* Increment the RTOS tick. */
         if( xTaskIncrementTick() != pdFALSE )
         {
+            traceISR_EXIT_TO_SCHEDULER();
             /* Pend a context switch. */
             portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
         }
+        else
+        {
+            traceISR_EXIT();
+        }
     }
     portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
 }
diff --git a/portable/GCC/ARM_CM4_MPU/portmacro.h b/portable/GCC/ARM_CM4_MPU/portmacro.h
index e7d0c4105..efe8ed2ef 100644
--- a/portable/GCC/ARM_CM4_MPU/portmacro.h
+++ b/portable/GCC/ARM_CM4_MPU/portmacro.h
@@ -277,9 +277,19 @@ typedef struct MPU_SETTINGS
 
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )                                 \
-    do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
-    while( 0 )
+#define portEND_SWITCHING_ISR( xSwitchRequired )            \
+    do                                                      \
+    {                                                       \
+        if( xSwitchRequired )                               \
+        {                                                   \
+            traceISR_EXIT_TO_SCHEDULER();                   \
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+        }                                                   \
+        else                                                \
+        {                                                   \
+            traceISR_EXIT();                                \
+        }                                                   \
+    } while( 0 )
 #define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/GCC/ARM_CM55/non_secure/port.c b/portable/GCC/ARM_CM55/non_secure/port.c
index e8ad8cf4c..0ba29f9b4 100644
--- a/portable/GCC/ARM_CM55/non_secure/port.c
+++ b/portable/GCC/ARM_CM55/non_secure/port.c
@@ -977,13 +977,19 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
     uint32_t ulPreviousMask;
 
     ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+    traceISR_ENTER();
     {
         /* Increment the RTOS tick. */
         if( xTaskIncrementTick() != pdFALSE )
         {
+            traceISR_EXIT_TO_SCHEDULER();
             /* Pend a context switch. */
             portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
         }
+        else
+        {
+            traceISR_EXIT();
+        }
     }
     portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
 }
diff --git a/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h
index cc2adb7fd..96a28ca4e 100644
--- a/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h
@@ -338,9 +338,19 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portYIELD()    vPortYield()
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )                                 \
-    do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
-    while( 0 )
+#define portEND_SWITCHING_ISR( xSwitchRequired )            \
+    do                                                      \
+    {                                                       \
+        if( xSwitchRequired )                               \
+        {                                                   \
+            traceISR_EXIT_TO_SCHEDULER();                   \
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+        }                                                   \
+        else                                                \
+        {                                                   \
+            traceISR_EXIT();                                \
+        }                                                   \
+    } while( 0 )
 #define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/port.c b/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
index e8ad8cf4c..0ba29f9b4 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
@@ -977,13 +977,19 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
     uint32_t ulPreviousMask;
 
     ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+    traceISR_ENTER();
     {
         /* Increment the RTOS tick. */
         if( xTaskIncrementTick() != pdFALSE )
         {
+            traceISR_EXIT_TO_SCHEDULER();
             /* Pend a context switch. */
             portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
         }
+        else
+        {
+            traceISR_EXIT();
+        }
     }
     portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
 }
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h
index cc2adb7fd..96a28ca4e 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h
@@ -338,9 +338,19 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portYIELD()    vPortYield()
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )                                 \
-    do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
-    while( 0 )
+#define portEND_SWITCHING_ISR( xSwitchRequired )            \
+    do                                                      \
+    {                                                       \
+        if( xSwitchRequired )                               \
+        {                                                   \
+            traceISR_EXIT_TO_SCHEDULER();                   \
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+        }                                                   \
+        else                                                \
+        {                                                   \
+            traceISR_EXIT();                                \
+        }                                                   \
+    } while( 0 )
 #define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/GCC/ARM_CM7/r0p1/portmacro.h b/portable/GCC/ARM_CM7/r0p1/portmacro.h
index d32af2b75..aa2199c25 100644
--- a/portable/GCC/ARM_CM7/r0p1/portmacro.h
+++ b/portable/GCC/ARM_CM7/r0p1/portmacro.h
@@ -95,9 +95,18 @@ typedef unsigned long    UBaseType_t;
 
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )                                         \
-    do { if( xSwitchRequired != pdFALSE ) { traceISR_EXIT_TO_SCHEDULER(); portYIELD(); } \
-         else { traceISR_EXIT(); }                                                       \
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+    do                                           \
+    {                                            \
+        if( xSwitchRequired != pdFALSE )         \
+        {                                        \
+            traceISR_EXIT_TO_SCHEDULER();        \
+            portYIELD();                         \
+        }                                        \
+        else                                     \
+        {                                        \
+            traceISR_EXIT();                     \
+        }                                        \
     } while( 0 )
 #define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM85/non_secure/port.c b/portable/GCC/ARM_CM85/non_secure/port.c
index e8ad8cf4c..0ba29f9b4 100644
--- a/portable/GCC/ARM_CM85/non_secure/port.c
+++ b/portable/GCC/ARM_CM85/non_secure/port.c
@@ -977,13 +977,19 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
     uint32_t ulPreviousMask;
 
     ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+    traceISR_ENTER();
     {
         /* Increment the RTOS tick. */
         if( xTaskIncrementTick() != pdFALSE )
         {
+            traceISR_EXIT_TO_SCHEDULER();
             /* Pend a context switch. */
             portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
         }
+        else
+        {
+            traceISR_EXIT();
+        }
     }
     portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
 }
diff --git a/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h
index cc2adb7fd..96a28ca4e 100644
--- a/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h
@@ -338,9 +338,19 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portYIELD()    vPortYield()
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )                                 \
-    do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
-    while( 0 )
+#define portEND_SWITCHING_ISR( xSwitchRequired )            \
+    do                                                      \
+    {                                                       \
+        if( xSwitchRequired )                               \
+        {                                                   \
+            traceISR_EXIT_TO_SCHEDULER();                   \
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+        }                                                   \
+        else                                                \
+        {                                                   \
+            traceISR_EXIT();                                \
+        }                                                   \
+    } while( 0 )
 #define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/port.c b/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
index e8ad8cf4c..0ba29f9b4 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
@@ -977,13 +977,19 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
     uint32_t ulPreviousMask;
 
     ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+    traceISR_ENTER();
     {
         /* Increment the RTOS tick. */
         if( xTaskIncrementTick() != pdFALSE )
         {
+            traceISR_EXIT_TO_SCHEDULER();
             /* Pend a context switch. */
             portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
         }
+        else
+        {
+            traceISR_EXIT();
+        }
     }
     portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
 }
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h
index cc2adb7fd..96a28ca4e 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h
@@ -338,9 +338,19 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portYIELD()    vPortYield()
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )                                 \
-    do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
-    while( 0 )
+#define portEND_SWITCHING_ISR( xSwitchRequired )            \
+    do                                                      \
+    {                                                       \
+        if( xSwitchRequired )                               \
+        {                                                   \
+            traceISR_EXIT_TO_SCHEDULER();                   \
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+        }                                                   \
+        else                                                \
+        {                                                   \
+            traceISR_EXIT();                                \
+        }                                                   \
+    } while( 0 )
 #define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/GCC/ColdFire_V2/portmacro.h b/portable/GCC/ColdFire_V2/portmacro.h
index c1df5e9c8..1a1b618d0 100644
--- a/portable/GCC/ColdFire_V2/portmacro.h
+++ b/portable/GCC/ColdFire_V2/portmacro.h
@@ -105,7 +105,19 @@ extern void vPortClearInterruptMaskFromISR( UBaseType_t );
 #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 /*-----------------------------------------------------------*/
 
-#define portEND_SWITCHING_ISR( xSwitchRequired )              do { if( xSwitchRequired != pdFALSE ) { portYIELD(); } } while( 0 )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+    do                                           \
+    {                                            \
+        if( xSwitchRequired != pdFALSE )         \
+        {                                        \
+            traceISR_EXIT_TO_SCHEDULER();        \
+            portYIELD();                         \
+        }                                        \
+        else                                     \
+        {                                        \
+            traceISR_EXIT();                     \
+        }                                        \
+    } while( 0 )
 
 
 /* *INDENT-OFF* */
diff --git a/portable/GCC/NiosII/portmacro.h b/portable/GCC/NiosII/portmacro.h
index c6f1b32bc..b7b1d94a0 100644
--- a/portable/GCC/NiosII/portmacro.h
+++ b/portable/GCC/NiosII/portmacro.h
@@ -84,9 +84,20 @@ typedef unsigned long    UBaseType_t;
 /*-----------------------------------------------------------*/
 
 extern void vTaskSwitchContext( void );
-#define portYIELD()                                 asm volatile ( "trap" );
-#define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired ) vTaskSwitchContext( ); } while( 0 )
-
+#define portYIELD()    asm volatile ( "trap" );
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+    do                                           \
+    {                                            \
+        if( xSwitchRequired != pdFALSE )         \
+        {                                        \
+            traceISR_EXIT_TO_SCHEDULER();        \
+            vTaskSwitchContext();                \
+        }                                        \
+        else                                     \
+        {                                        \
+            traceISR_EXIT();                     \
+        }                                        \
+    } while( 0 )
 
 /* Include the port_asm.S file where the Context saving/restoring is defined. */
 __asm__ ( "\n\t.globl    save_context" );
diff --git a/portable/GCC/RISC-V/portmacro.h b/portable/GCC/RISC-V/portmacro.h
index 28778c78e..e40af6639 100644
--- a/portable/GCC/RISC-V/portmacro.h
+++ b/portable/GCC/RISC-V/portmacro.h
@@ -91,9 +91,21 @@ typedef portUBASE_TYPE   TickType_t;
 
 /* Scheduler utilities. */
 extern void vTaskSwitchContext( void );
-#define portYIELD()                                 __asm volatile ( "ecall" );
-#define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired ) vTaskSwitchContext( ); } while( 0 )
-#define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+#define portYIELD()                __asm volatile ( "ecall" );
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+    do                                           \
+    {                                            \
+        if( xSwitchRequired != pdFALSE )         \
+        {                                        \
+            traceISR_EXIT_TO_SCHEDULER();        \
+            vTaskSwitchContext();                \
+        }                                        \
+        else                                     \
+        {                                        \
+            traceISR_EXIT();                     \
+        }                                        \
+    } while( 0 )
+#define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
 /* Critical section management. */
diff --git a/portable/GCC/STR75x/portmacro.h b/portable/GCC/STR75x/portmacro.h
index 10c13c717..b52d3a513 100644
--- a/portable/GCC/STR75x/portmacro.h
+++ b/portable/GCC/STR75x/portmacro.h
@@ -129,8 +129,13 @@ extern void vPortExitCritical( void );
                                                  \
         if( xSwitchRequired )                    \
         {                                        \
+            traceISR_EXIT_TO_SCHEDULER();        \
             vTaskSwitchContext();                \
         }                                        \
+        else                                     \
+        {                                        \
+            traceISR_EXIT();                     \
+        }                                        \
     }
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM0/port.c b/portable/IAR/ARM_CM0/port.c
index c55af1fd8..f4d77120c 100644
--- a/portable/IAR/ARM_CM0/port.c
+++ b/portable/IAR/ARM_CM0/port.c
@@ -233,13 +233,19 @@ void xPortSysTickHandler( void )
     uint32_t ulPreviousMask;
 
     ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+    traceISR_ENTER();
     {
         /* Increment the RTOS tick. */
         if( xTaskIncrementTick() != pdFALSE )
         {
+            traceISR_EXIT_TO_SCHEDULER();
             /* Pend a context switch. */
             portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET;
         }
+        else
+        {
+            traceISR_EXIT();
+        }
     }
     portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
 }
diff --git a/portable/IAR/ARM_CM0/portmacro.h b/portable/IAR/ARM_CM0/portmacro.h
index 5dcc949b2..fa8438fec 100644
--- a/portable/IAR/ARM_CM0/portmacro.h
+++ b/portable/IAR/ARM_CM0/portmacro.h
@@ -86,9 +86,21 @@ typedef unsigned long    UBaseType_t;
 extern void vPortYield( void );
 #define portNVIC_INT_CTRL     ( ( volatile uint32_t * ) 0xe000ed04 )
 #define portNVIC_PENDSVSET    0x10000000
-#define portYIELD()                                 vPortYield()
-#define portEND_SWITCHING_ISR( xSwitchRequired )    if( xSwitchRequired ) *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET
-#define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+#define portYIELD()                vPortYield()
+#define portEND_SWITCHING_ISR( xSwitchRequired )        \
+    do                                                  \
+    {                                                   \
+        if( xSwitchRequired != pdFALSE )                \
+        {                                               \
+            traceISR_EXIT_TO_SCHEDULER();               \
+            *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET \
+        }                                               \
+        else                                            \
+        {                                               \
+            traceISR_EXIT();                            \
+        }                                               \
+    } while( 0 )
+#define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
 
diff --git a/portable/IAR/ARM_CM23/non_secure/port.c b/portable/IAR/ARM_CM23/non_secure/port.c
index e8ad8cf4c..0ba29f9b4 100644
--- a/portable/IAR/ARM_CM23/non_secure/port.c
+++ b/portable/IAR/ARM_CM23/non_secure/port.c
@@ -977,13 +977,19 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
     uint32_t ulPreviousMask;
 
     ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+    traceISR_ENTER();
     {
         /* Increment the RTOS tick. */
         if( xTaskIncrementTick() != pdFALSE )
         {
+            traceISR_EXIT_TO_SCHEDULER();
             /* Pend a context switch. */
             portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
         }
+        else
+        {
+            traceISR_EXIT();
+        }
     }
     portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
 }
diff --git a/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h
index cc2adb7fd..96a28ca4e 100644
--- a/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h
@@ -338,9 +338,19 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portYIELD()    vPortYield()
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )                                 \
-    do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
-    while( 0 )
+#define portEND_SWITCHING_ISR( xSwitchRequired )            \
+    do                                                      \
+    {                                                       \
+        if( xSwitchRequired )                               \
+        {                                                   \
+            traceISR_EXIT_TO_SCHEDULER();                   \
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+        }                                                   \
+        else                                                \
+        {                                                   \
+            traceISR_EXIT();                                \
+        }                                                   \
+    } while( 0 )
 #define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
index e8ad8cf4c..0ba29f9b4 100644
--- a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
@@ -977,13 +977,19 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
     uint32_t ulPreviousMask;
 
     ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+    traceISR_ENTER();
     {
         /* Increment the RTOS tick. */
         if( xTaskIncrementTick() != pdFALSE )
         {
+            traceISR_EXIT_TO_SCHEDULER();
             /* Pend a context switch. */
             portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
         }
+        else
+        {
+            traceISR_EXIT();
+        }
     }
     portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
 }
diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h
index cc2adb7fd..96a28ca4e 100644
--- a/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h
@@ -338,9 +338,19 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portYIELD()    vPortYield()
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )                                 \
-    do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
-    while( 0 )
+#define portEND_SWITCHING_ISR( xSwitchRequired )            \
+    do                                                      \
+    {                                                       \
+        if( xSwitchRequired )                               \
+        {                                                   \
+            traceISR_EXIT_TO_SCHEDULER();                   \
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+        }                                                   \
+        else                                                \
+        {                                                   \
+            traceISR_EXIT();                                \
+        }                                                   \
+    } while( 0 )
 #define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM3/port.c b/portable/IAR/ARM_CM3/port.c
index 5d44bdb32..1fbe96d44 100644
--- a/portable/IAR/ARM_CM3/port.c
+++ b/portable/IAR/ARM_CM3/port.c
@@ -355,14 +355,21 @@ void xPortSysTickHandler( void )
      * save and then restore the interrupt mask value as its value is already
      * known. */
     portDISABLE_INTERRUPTS();
+    traceISR_ENTER();
     {
         /* Increment the RTOS tick. */
         if( xTaskIncrementTick() != pdFALSE )
         {
+            traceISR_EXIT_TO_SCHEDULER();
+
             /* A context switch is required.  Context switching is performed in
              * the PendSV interrupt.  Pend the PendSV interrupt. */
             portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
         }
+        else
+        {
+            traceISR_EXIT();
+        }
     }
     portENABLE_INTERRUPTS();
 }
diff --git a/portable/IAR/ARM_CM3/portmacro.h b/portable/IAR/ARM_CM3/portmacro.h
index 7c7d5356d..c90a952e2 100644
--- a/portable/IAR/ARM_CM3/portmacro.h
+++ b/portable/IAR/ARM_CM3/portmacro.h
@@ -100,8 +100,20 @@ typedef unsigned long    UBaseType_t;
 
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired != pdFALSE ) portYIELD( ); } while( 0 )
-#define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+    do                                           \
+    {                                            \
+        if( xSwitchRequired != pdFALSE )         \
+        {                                        \
+            traceISR_EXIT_TO_SCHEDULER();        \
+            portYIELD();                         \
+        }                                        \
+        else                                     \
+        {                                        \
+            traceISR_EXIT();                     \
+        }                                        \
+    } while( 0 )
+#define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
 
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM33/non_secure/port.c b/portable/IAR/ARM_CM33/non_secure/port.c
index e8ad8cf4c..0ba29f9b4 100644
--- a/portable/IAR/ARM_CM33/non_secure/port.c
+++ b/portable/IAR/ARM_CM33/non_secure/port.c
@@ -977,13 +977,19 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
     uint32_t ulPreviousMask;
 
     ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+    traceISR_ENTER();
     {
         /* Increment the RTOS tick. */
         if( xTaskIncrementTick() != pdFALSE )
         {
+            traceISR_EXIT_TO_SCHEDULER();
             /* Pend a context switch. */
             portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
         }
+        else
+        {
+            traceISR_EXIT();
+        }
     }
     portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
 }
diff --git a/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h
index cc2adb7fd..96a28ca4e 100644
--- a/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h
@@ -338,9 +338,19 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portYIELD()    vPortYield()
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )                                 \
-    do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
-    while( 0 )
+#define portEND_SWITCHING_ISR( xSwitchRequired )            \
+    do                                                      \
+    {                                                       \
+        if( xSwitchRequired )                               \
+        {                                                   \
+            traceISR_EXIT_TO_SCHEDULER();                   \
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+        }                                                   \
+        else                                                \
+        {                                                   \
+            traceISR_EXIT();                                \
+        }                                                   \
+    } while( 0 )
 #define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
index e8ad8cf4c..0ba29f9b4 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
@@ -977,13 +977,19 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
     uint32_t ulPreviousMask;
 
     ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+    traceISR_ENTER();
     {
         /* Increment the RTOS tick. */
         if( xTaskIncrementTick() != pdFALSE )
         {
+            traceISR_EXIT_TO_SCHEDULER();
             /* Pend a context switch. */
             portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
         }
+        else
+        {
+            traceISR_EXIT();
+        }
     }
     portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
 }
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h
index cc2adb7fd..96a28ca4e 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h
@@ -338,9 +338,19 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portYIELD()    vPortYield()
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )                                 \
-    do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
-    while( 0 )
+#define portEND_SWITCHING_ISR( xSwitchRequired )            \
+    do                                                      \
+    {                                                       \
+        if( xSwitchRequired )                               \
+        {                                                   \
+            traceISR_EXIT_TO_SCHEDULER();                   \
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+        }                                                   \
+        else                                                \
+        {                                                   \
+            traceISR_EXIT();                                \
+        }                                                   \
+    } while( 0 )
 #define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM35P/non_secure/port.c b/portable/IAR/ARM_CM35P/non_secure/port.c
index e8ad8cf4c..0ba29f9b4 100644
--- a/portable/IAR/ARM_CM35P/non_secure/port.c
+++ b/portable/IAR/ARM_CM35P/non_secure/port.c
@@ -977,13 +977,19 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
     uint32_t ulPreviousMask;
 
     ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+    traceISR_ENTER();
     {
         /* Increment the RTOS tick. */
         if( xTaskIncrementTick() != pdFALSE )
         {
+            traceISR_EXIT_TO_SCHEDULER();
             /* Pend a context switch. */
             portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
         }
+        else
+        {
+            traceISR_EXIT();
+        }
     }
     portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
 }
diff --git a/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h
index cc2adb7fd..96a28ca4e 100644
--- a/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h
@@ -338,9 +338,19 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portYIELD()    vPortYield()
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )                                 \
-    do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
-    while( 0 )
+#define portEND_SWITCHING_ISR( xSwitchRequired )            \
+    do                                                      \
+    {                                                       \
+        if( xSwitchRequired )                               \
+        {                                                   \
+            traceISR_EXIT_TO_SCHEDULER();                   \
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+        }                                                   \
+        else                                                \
+        {                                                   \
+            traceISR_EXIT();                                \
+        }                                                   \
+    } while( 0 )
 #define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c b/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
index e8ad8cf4c..0ba29f9b4 100644
--- a/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
@@ -977,13 +977,19 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
     uint32_t ulPreviousMask;
 
     ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+    traceISR_ENTER();
     {
         /* Increment the RTOS tick. */
         if( xTaskIncrementTick() != pdFALSE )
         {
+            traceISR_EXIT_TO_SCHEDULER();
             /* Pend a context switch. */
             portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
         }
+        else
+        {
+            traceISR_EXIT();
+        }
     }
     portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
 }
diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
index cc2adb7fd..96a28ca4e 100644
--- a/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
@@ -338,9 +338,19 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portYIELD()    vPortYield()
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )                                 \
-    do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
-    while( 0 )
+#define portEND_SWITCHING_ISR( xSwitchRequired )            \
+    do                                                      \
+    {                                                       \
+        if( xSwitchRequired )                               \
+        {                                                   \
+            traceISR_EXIT_TO_SCHEDULER();                   \
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+        }                                                   \
+        else                                                \
+        {                                                   \
+            traceISR_EXIT();                                \
+        }                                                   \
+    } while( 0 )
 #define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM4F/port.c b/portable/IAR/ARM_CM4F/port.c
index dd328160b..effedcb14 100644
--- a/portable/IAR/ARM_CM4F/port.c
+++ b/portable/IAR/ARM_CM4F/port.c
@@ -399,14 +399,21 @@ void xPortSysTickHandler( void )
      * save and then restore the interrupt mask value as its value is already
      * known. */
     portDISABLE_INTERRUPTS();
+    traceISR_ENTER();
     {
         /* Increment the RTOS tick. */
         if( xTaskIncrementTick() != pdFALSE )
         {
+            traceISR_EXIT_TO_SCHEDULER();
+
             /* A context switch is required.  Context switching is performed in
              * the PendSV interrupt.  Pend the PendSV interrupt. */
             portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
         }
+        else
+        {
+            traceISR_EXIT();
+        }
     }
     portENABLE_INTERRUPTS();
 }
diff --git a/portable/IAR/ARM_CM4F/portmacro.h b/portable/IAR/ARM_CM4F/portmacro.h
index 5c4369418..20467efcb 100644
--- a/portable/IAR/ARM_CM4F/portmacro.h
+++ b/portable/IAR/ARM_CM4F/portmacro.h
@@ -99,8 +99,20 @@ typedef unsigned long    UBaseType_t;
 
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired != pdFALSE ) portYIELD( ); } while( 0 )
-#define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+    do                                           \
+    {                                            \
+        if( xSwitchRequired != pdFALSE )         \
+        {                                        \
+            traceISR_EXIT_TO_SCHEDULER();        \
+            portYIELD();                         \
+        }                                        \
+        else                                     \
+        {                                        \
+            traceISR_EXIT();                     \
+        }                                        \
+    } while( 0 )
+#define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
 
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM4F_MPU/port.c b/portable/IAR/ARM_CM4F_MPU/port.c
index 2d90c348c..f7b9f45ce 100644
--- a/portable/IAR/ARM_CM4F_MPU/port.c
+++ b/portable/IAR/ARM_CM4F_MPU/port.c
@@ -987,14 +987,21 @@ void xPortSysTickHandler( void )
      * save and then restore the interrupt mask value as its value is already
      * known. */
     portDISABLE_INTERRUPTS();
+    traceISR_ENTER();
     {
         /* Increment the RTOS tick. */
         if( xTaskIncrementTick() != pdFALSE )
         {
+            traceISR_EXIT_TO_SCHEDULER();
+
             /* A context switch is required.  Context switching is performed in
              * the PendSV interrupt.  Pend the PendSV interrupt. */
             portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
         }
+        else
+        {
+            traceISR_EXIT();
+        }
     }
     portENABLE_INTERRUPTS();
 }
diff --git a/portable/IAR/ARM_CM4F_MPU/portmacro.h b/portable/IAR/ARM_CM4F_MPU/portmacro.h
index 8a5538064..15e65619c 100644
--- a/portable/IAR/ARM_CM4F_MPU/portmacro.h
+++ b/portable/IAR/ARM_CM4F_MPU/portmacro.h
@@ -275,8 +275,20 @@ typedef struct MPU_SETTINGS
 
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired != pdFALSE ) portYIELD_WITHIN_API( ); } while( 0 )
-#define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+    do                                           \
+    {                                            \
+        if( xSwitchRequired != pdFALSE )         \
+        {                                        \
+            traceISR_EXIT_TO_SCHEDULER();        \
+            portYIELD_WITHIN_API();              \
+        }                                        \
+        else                                     \
+        {                                        \
+            traceISR_EXIT();                     \
+        }                                        \
+    } while( 0 )
+#define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
 /* Architecture specific optimisations. */
diff --git a/portable/IAR/ARM_CM55/non_secure/port.c b/portable/IAR/ARM_CM55/non_secure/port.c
index e8ad8cf4c..0ba29f9b4 100644
--- a/portable/IAR/ARM_CM55/non_secure/port.c
+++ b/portable/IAR/ARM_CM55/non_secure/port.c
@@ -977,13 +977,19 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
     uint32_t ulPreviousMask;
 
     ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+    traceISR_ENTER();
     {
         /* Increment the RTOS tick. */
         if( xTaskIncrementTick() != pdFALSE )
         {
+            traceISR_EXIT_TO_SCHEDULER();
             /* Pend a context switch. */
             portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
         }
+        else
+        {
+            traceISR_EXIT();
+        }
     }
     portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
 }
diff --git a/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h
index cc2adb7fd..96a28ca4e 100644
--- a/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h
@@ -338,9 +338,19 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portYIELD()    vPortYield()
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )                                 \
-    do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
-    while( 0 )
+#define portEND_SWITCHING_ISR( xSwitchRequired )            \
+    do                                                      \
+    {                                                       \
+        if( xSwitchRequired )                               \
+        {                                                   \
+            traceISR_EXIT_TO_SCHEDULER();                   \
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+        }                                                   \
+        else                                                \
+        {                                                   \
+            traceISR_EXIT();                                \
+        }                                                   \
+    } while( 0 )
 #define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/port.c b/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
index e8ad8cf4c..0ba29f9b4 100644
--- a/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
@@ -977,13 +977,19 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
     uint32_t ulPreviousMask;
 
     ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+    traceISR_ENTER();
     {
         /* Increment the RTOS tick. */
         if( xTaskIncrementTick() != pdFALSE )
         {
+            traceISR_EXIT_TO_SCHEDULER();
             /* Pend a context switch. */
             portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
         }
+        else
+        {
+            traceISR_EXIT();
+        }
     }
     portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
 }
diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h
index cc2adb7fd..96a28ca4e 100644
--- a/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h
@@ -338,9 +338,19 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portYIELD()    vPortYield()
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )                                 \
-    do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
-    while( 0 )
+#define portEND_SWITCHING_ISR( xSwitchRequired )            \
+    do                                                      \
+    {                                                       \
+        if( xSwitchRequired )                               \
+        {                                                   \
+            traceISR_EXIT_TO_SCHEDULER();                   \
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+        }                                                   \
+        else                                                \
+        {                                                   \
+            traceISR_EXIT();                                \
+        }                                                   \
+    } while( 0 )
 #define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM7/r0p1/port.c b/portable/IAR/ARM_CM7/r0p1/port.c
index 6d2c122d1..58129a4df 100644
--- a/portable/IAR/ARM_CM7/r0p1/port.c
+++ b/portable/IAR/ARM_CM7/r0p1/port.c
@@ -387,14 +387,21 @@ void xPortSysTickHandler( void )
      * save and then restore the interrupt mask value as its value is already
      * known. */
     portDISABLE_INTERRUPTS();
+    traceISR_ENTER();
     {
         /* Increment the RTOS tick. */
         if( xTaskIncrementTick() != pdFALSE )
         {
+            traceISR_EXIT_TO_SCHEDULER();
+
             /* A context switch is required.  Context switching is performed in
              * the PendSV interrupt.  Pend the PendSV interrupt. */
             portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
         }
+        else
+        {
+            traceISR_EXIT();
+        }
     }
     portENABLE_INTERRUPTS();
 }
diff --git a/portable/IAR/ARM_CM7/r0p1/portmacro.h b/portable/IAR/ARM_CM7/r0p1/portmacro.h
index 5f1c0488c..a6c377b6b 100644
--- a/portable/IAR/ARM_CM7/r0p1/portmacro.h
+++ b/portable/IAR/ARM_CM7/r0p1/portmacro.h
@@ -99,8 +99,20 @@ typedef unsigned long    UBaseType_t;
 
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired != pdFALSE ) portYIELD( ); } while( 0 )
-#define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+    do                                           \
+    {                                            \
+        if( xSwitchRequired != pdFALSE )         \
+        {                                        \
+            traceISR_EXIT_TO_SCHEDULER();        \
+            portYIELD();                         \
+        }                                        \
+        else                                     \
+        {                                        \
+            traceISR_EXIT();                     \
+        }                                        \
+    } while( 0 )
+#define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
 
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM85/non_secure/port.c b/portable/IAR/ARM_CM85/non_secure/port.c
index e8ad8cf4c..0ba29f9b4 100644
--- a/portable/IAR/ARM_CM85/non_secure/port.c
+++ b/portable/IAR/ARM_CM85/non_secure/port.c
@@ -977,13 +977,19 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
     uint32_t ulPreviousMask;
 
     ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+    traceISR_ENTER();
     {
         /* Increment the RTOS tick. */
         if( xTaskIncrementTick() != pdFALSE )
         {
+            traceISR_EXIT_TO_SCHEDULER();
             /* Pend a context switch. */
             portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
         }
+        else
+        {
+            traceISR_EXIT();
+        }
     }
     portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
 }
diff --git a/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h
index cc2adb7fd..96a28ca4e 100644
--- a/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h
@@ -338,9 +338,19 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portYIELD()    vPortYield()
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )                                 \
-    do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
-    while( 0 )
+#define portEND_SWITCHING_ISR( xSwitchRequired )            \
+    do                                                      \
+    {                                                       \
+        if( xSwitchRequired )                               \
+        {                                                   \
+            traceISR_EXIT_TO_SCHEDULER();                   \
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+        }                                                   \
+        else                                                \
+        {                                                   \
+            traceISR_EXIT();                                \
+        }                                                   \
+    } while( 0 )
 #define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/port.c b/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
index e8ad8cf4c..0ba29f9b4 100644
--- a/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
@@ -977,13 +977,19 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
     uint32_t ulPreviousMask;
 
     ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+    traceISR_ENTER();
     {
         /* Increment the RTOS tick. */
         if( xTaskIncrementTick() != pdFALSE )
         {
+            traceISR_EXIT_TO_SCHEDULER();
             /* Pend a context switch. */
             portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
         }
+        else
+        {
+            traceISR_EXIT();
+        }
     }
     portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
 }
diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h
index cc2adb7fd..96a28ca4e 100644
--- a/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h
@@ -338,9 +338,19 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portYIELD()    vPortYield()
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )                                 \
-    do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
-    while( 0 )
+#define portEND_SWITCHING_ISR( xSwitchRequired )            \
+    do                                                      \
+    {                                                       \
+        if( xSwitchRequired )                               \
+        {                                                   \
+            traceISR_EXIT_TO_SCHEDULER();                   \
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+        }                                                   \
+        else                                                \
+        {                                                   \
+            traceISR_EXIT();                                \
+        }                                                   \
+    } while( 0 )
 #define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/AtmelSAM7S64/portmacro.h b/portable/IAR/AtmelSAM7S64/portmacro.h
index dbea59237..337139712 100644
--- a/portable/IAR/AtmelSAM7S64/portmacro.h
+++ b/portable/IAR/AtmelSAM7S64/portmacro.h
@@ -97,8 +97,13 @@ __arm __interwork void vPortExitCritical( void );
                                                  \
         if( xSwitchRequired )                    \
         {                                        \
+            traceISR_EXIT_TO_SCHEDULER();        \
             vTaskSwitchContext();                \
         }                                        \
+        else                                     \
+        {                                        \
+            traceISR_EXIT();                     \
+        }                                        \
     }
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/AtmelSAM9XE/portmacro.h b/portable/IAR/AtmelSAM9XE/portmacro.h
index 54af3f1d6..6a234933e 100644
--- a/portable/IAR/AtmelSAM9XE/portmacro.h
+++ b/portable/IAR/AtmelSAM9XE/portmacro.h
@@ -100,8 +100,13 @@ __arm __interwork void vPortExitCritical( void );
                                                  \
         if( xSwitchRequired )                    \
         {                                        \
+            traceISR_EXIT_TO_SCHEDULER();        \
             vTaskSwitchContext();                \
         }                                        \
+        else                                     \
+        {                                        \
+            traceISR_EXIT();                     \
+        }                                        \
     }
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/LPC2000/portmacro.h b/portable/IAR/LPC2000/portmacro.h
index 28b8d7e77..40231e408 100644
--- a/portable/IAR/LPC2000/portmacro.h
+++ b/portable/IAR/LPC2000/portmacro.h
@@ -100,8 +100,13 @@ __arm __interwork void vPortExitCritical( void );
                                                  \
         if( xSwitchRequired )                    \
         {                                        \
+            traceISR_EXIT_TO_SCHEDULER();        \
             vTaskSwitchContext();                \
         }                                        \
+        else                                     \
+        {                                        \
+            traceISR_EXIT();                     \
+        }                                        \
     }
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/RISC-V/portmacro.h b/portable/IAR/RISC-V/portmacro.h
index f9431a6de..eba9eb6f2 100644
--- a/portable/IAR/RISC-V/portmacro.h
+++ b/portable/IAR/RISC-V/portmacro.h
@@ -93,9 +93,21 @@ typedef portUBASE_TYPE   TickType_t;
 
 /* Scheduler utilities. */
 extern void vTaskSwitchContext( void );
-#define portYIELD()                                 __asm volatile ( "ecall" );
-#define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired ) vTaskSwitchContext( ); } while( 0 )
-#define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+#define portYIELD()                __asm volatile ( "ecall" );
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+    do                                           \
+    {                                            \
+        if( xSwitchRequired != pdFALSE )         \
+        {                                        \
+            traceISR_EXIT_TO_SCHEDULER();        \
+            vTaskSwitchContext();                \
+        }                                        \
+        else                                     \
+        {                                        \
+            traceISR_EXIT();                     \
+        }                                        \
+    } while( 0 )
+#define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
 /* Critical section management. */
diff --git a/portable/IAR/STR71x/portmacro.h b/portable/IAR/STR71x/portmacro.h
index 7fa132cd9..7f5096c9d 100644
--- a/portable/IAR/STR71x/portmacro.h
+++ b/portable/IAR/STR71x/portmacro.h
@@ -101,8 +101,13 @@ __arm __interwork void vPortExitCritical( void );
                                                  \
         if( xSwitchRequired )                    \
         {                                        \
+            traceISR_EXIT_TO_SCHEDULER();        \
             vTaskSwitchContext();                \
         }                                        \
+        else                                     \
+        {                                        \
+            traceISR_EXIT();                     \
+        }                                        \
     }
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/STR75x/portmacro.h b/portable/IAR/STR75x/portmacro.h
index edbddd4d3..8be4a1a44 100644
--- a/portable/IAR/STR75x/portmacro.h
+++ b/portable/IAR/STR75x/portmacro.h
@@ -98,8 +98,13 @@ __arm __interwork void vPortExitCritical( void );
                                                  \
         if( xSwitchRequired )                    \
         {                                        \
+            traceISR_EXIT_TO_SCHEDULER();        \
             vTaskSwitchContext();                \
         }                                        \
+        else                                     \
+        {                                        \
+            traceISR_EXIT();                     \
+        }                                        \
     }
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/STR91x/portmacro.h b/portable/IAR/STR91x/portmacro.h
index fc4506d32..853b80139 100644
--- a/portable/IAR/STR91x/portmacro.h
+++ b/portable/IAR/STR91x/portmacro.h
@@ -100,8 +100,13 @@ __arm __interwork void vPortExitCritical( void );
                                                  \
         if( xSwitchRequired )                    \
         {                                        \
+            traceISR_EXIT_TO_SCHEDULER();        \
             vTaskSwitchContext();                \
         }                                        \
+        else                                     \
+        {                                        \
+            traceISR_EXIT();                     \
+        }                                        \
     }
 /*-----------------------------------------------------------*/
 
diff --git a/portable/MPLAB/PIC32MEC14xx/portmacro.h b/portable/MPLAB/PIC32MEC14xx/portmacro.h
index e20d7b68e..2b1fb9fa6 100644
--- a/portable/MPLAB/PIC32MEC14xx/portmacro.h
+++ b/portable/MPLAB/PIC32MEC14xx/portmacro.h
@@ -240,7 +240,19 @@ extern volatile UBaseType_t uxInterruptNesting;
 #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 /*-----------------------------------------------------------*/
 
-#define portEND_SWITCHING_ISR( xSwitchRequired )              do { if( xSwitchRequired ) { portYIELD(); } } while( 0 )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+    do                                           \
+    {                                            \
+        if( xSwitchRequired != pdFALSE )         \
+        {                                        \
+            traceISR_EXIT_TO_SCHEDULER();        \
+            portYIELD();                         \
+        }                                        \
+        else                                     \
+        {                                        \
+            traceISR_EXIT();                     \
+        }                                        \
+    } while( 0 )
 
 /* Required by the kernel aware debugger. */
 #ifdef __DEBUG
diff --git a/portable/MPLAB/PIC32MX/portmacro.h b/portable/MPLAB/PIC32MX/portmacro.h
index 535104d20..89777d80b 100644
--- a/portable/MPLAB/PIC32MX/portmacro.h
+++ b/portable/MPLAB/PIC32MX/portmacro.h
@@ -191,7 +191,19 @@ extern volatile UBaseType_t uxInterruptNesting;
 #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 /*-----------------------------------------------------------*/
 
-#define portEND_SWITCHING_ISR( xSwitchRequired )              do { if( xSwitchRequired ) { portYIELD(); } } while( 0 )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+    do                                           \
+    {                                            \
+        if( xSwitchRequired != pdFALSE )         \
+        {                                        \
+            traceISR_EXIT_TO_SCHEDULER();        \
+            portYIELD();                         \
+        }                                        \
+        else                                     \
+        {                                        \
+            traceISR_EXIT();                     \
+        }                                        \
+    } while( 0 )
 
 /* Required by the kernel aware debugger. */
 #ifdef __DEBUG
diff --git a/portable/MPLAB/PIC32MZ/portmacro.h b/portable/MPLAB/PIC32MZ/portmacro.h
index 63b69b436..050bb31fa 100644
--- a/portable/MPLAB/PIC32MZ/portmacro.h
+++ b/portable/MPLAB/PIC32MZ/portmacro.h
@@ -203,7 +203,19 @@ extern volatile UBaseType_t uxInterruptNesting;
 #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 /*-----------------------------------------------------------*/
 
-#define portEND_SWITCHING_ISR( xSwitchRequired )              do { if( xSwitchRequired ) { portYIELD(); } } while( 0 )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+    do                                           \
+    {                                            \
+        if( xSwitchRequired != pdFALSE )         \
+        {                                        \
+            traceISR_EXIT_TO_SCHEDULER();        \
+            portYIELD();                         \
+        }                                        \
+        else                                     \
+        {                                        \
+            traceISR_EXIT();                     \
+        }                                        \
+    } while( 0 )
 
 /* Required by the kernel aware debugger. */
 #ifdef __DEBUG
diff --git a/portable/MikroC/ARM_CM4F/port.c b/portable/MikroC/ARM_CM4F/port.c
index a1c3f4e61..1e5075d1d 100644
--- a/portable/MikroC/ARM_CM4F/port.c
+++ b/portable/MikroC/ARM_CM4F/port.c
@@ -509,14 +509,21 @@ void xPortSysTickHandler( void ) iv IVT_INT_SysTick ics ICS_AUTO
      * known - therefore the slightly faster portDISABLE_INTERRUPTS() function is
      * used in place of portSET_INTERRUPT_MASK_FROM_ISR(). */
     portDISABLE_INTERRUPTS();
+    traceISR_ENTER();
     {
         /* Increment the RTOS tick. */
         if( xTaskIncrementTick() != pdFALSE )
         {
+            traceISR_EXIT_TO_SCHEDULER();
+
             /* A context switch is required.  Context switching is performed in
              * the PendSV interrupt.  Pend the PendSV interrupt. */
             portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
         }
+        else
+        {
+            traceISR_EXIT();
+        }
     }
     portENABLE_INTERRUPTS();
 }
diff --git a/portable/MikroC/ARM_CM4F/portmacro.h b/portable/MikroC/ARM_CM4F/portmacro.h
index c7b4aae0f..6c169773c 100644
--- a/portable/MikroC/ARM_CM4F/portmacro.h
+++ b/portable/MikroC/ARM_CM4F/portmacro.h
@@ -99,8 +99,20 @@ typedef unsigned long    UBaseType_t;
 
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired != pdFALSE ) portYIELD( ); } while( 0 )
-#define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+    do                                           \
+    {                                            \
+        if( xSwitchRequired != pdFALSE )         \
+        {                                        \
+            traceISR_EXIT_TO_SCHEDULER();        \
+            portYIELD();                         \
+        }                                        \
+        else                                     \
+        {                                        \
+            traceISR_EXIT();                     \
+        }                                        \
+    } while( 0 )
+#define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
 /* Critical section management. */
diff --git a/portable/RVDS/ARM_CM0/port.c b/portable/RVDS/ARM_CM0/port.c
index 6af94943f..96947d215 100644
--- a/portable/RVDS/ARM_CM0/port.c
+++ b/portable/RVDS/ARM_CM0/port.c
@@ -352,13 +352,19 @@ void xPortSysTickHandler( void )
     uint32_t ulPreviousMask;
 
     ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+    traceISR_ENTER();
     {
         /* Increment the RTOS tick. */
         if( xTaskIncrementTick() != pdFALSE )
         {
+            traceISR_EXIT_TO_SCHEDULER();
             /* Pend a context switch. */
             portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
         }
+        else
+        {
+            traceISR_EXIT();
+        }
     }
     portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
 }
diff --git a/portable/RVDS/ARM_CM0/portmacro.h b/portable/RVDS/ARM_CM0/portmacro.h
index 134ee23b8..1b5821a71 100644
--- a/portable/RVDS/ARM_CM0/portmacro.h
+++ b/portable/RVDS/ARM_CM0/portmacro.h
@@ -86,9 +86,19 @@ extern void vPortYield( void );
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
 #define portYIELD()                vPortYield()
-#define portEND_SWITCHING_ISR( xSwitchRequired )                                 \
-    do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
-    while( 0 )
+#define portEND_SWITCHING_ISR( xSwitchRequired )            \
+    do                                                      \
+    {                                                       \
+        if( xSwitchRequired )                               \
+        {                                                   \
+            traceISR_EXIT_TO_SCHEDULER();                   \
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+        }                                                   \
+        else                                                \
+        {                                                   \
+            traceISR_EXIT();                                \
+        }                                                   \
+    } while( 0 )
 #define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/RVDS/ARM_CM3/port.c b/portable/RVDS/ARM_CM3/port.c
index ab9fb9f6b..9a6af5acc 100644
--- a/portable/RVDS/ARM_CM3/port.c
+++ b/portable/RVDS/ARM_CM3/port.c
@@ -449,14 +449,21 @@ void xPortSysTickHandler( void )
      * known - therefore the slightly faster vPortRaiseBASEPRI() function is used
      * in place of portSET_INTERRUPT_MASK_FROM_ISR(). */
     vPortRaiseBASEPRI();
+    traceISR_ENTER();
     {
         /* Increment the RTOS tick. */
         if( xTaskIncrementTick() != pdFALSE )
         {
+            traceISR_EXIT_TO_SCHEDULER();
+
             /* A context switch is required.  Context switching is performed in
              * the PendSV interrupt.  Pend the PendSV interrupt. */
             portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
         }
+        else
+        {
+            traceISR_EXIT();
+        }
     }
 
     vPortClearBASEPRIFromISR();
diff --git a/portable/RVDS/ARM_CM3/portmacro.h b/portable/RVDS/ARM_CM3/portmacro.h
index 56f59a6e9..4b8fbdb99 100644
--- a/portable/RVDS/ARM_CM3/portmacro.h
+++ b/portable/RVDS/ARM_CM3/portmacro.h
@@ -99,8 +99,20 @@ typedef unsigned long    UBaseType_t;
 
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired != pdFALSE ) portYIELD( ); } while( 0 )
-#define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+    do                                           \
+    {                                            \
+        if( xSwitchRequired != pdFALSE )         \
+        {                                        \
+            traceISR_EXIT_TO_SCHEDULER();        \
+            portYIELD();                         \
+        }                                        \
+        else                                     \
+        {                                        \
+            traceISR_EXIT();                     \
+        }                                        \
+    } while( 0 )
+#define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
 /* Critical section management. */
diff --git a/portable/RVDS/ARM_CM4F/port.c b/portable/RVDS/ARM_CM4F/port.c
index 6794feb3f..c6d825b82 100644
--- a/portable/RVDS/ARM_CM4F/port.c
+++ b/portable/RVDS/ARM_CM4F/port.c
@@ -545,14 +545,21 @@ void xPortSysTickHandler( void )
      * known - therefore the slightly faster vPortRaiseBASEPRI() function is used
      * in place of portSET_INTERRUPT_MASK_FROM_ISR(). */
     vPortRaiseBASEPRI();
+    traceISR_ENTER();
     {
         /* Increment the RTOS tick. */
         if( xTaskIncrementTick() != pdFALSE )
         {
+            traceISR_EXIT_TO_SCHEDULER();
+
             /* A context switch is required.  Context switching is performed in
              * the PendSV interrupt.  Pend the PendSV interrupt. */
             portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
         }
+        else
+        {
+            traceISR_EXIT();
+        }
     }
 
     vPortClearBASEPRIFromISR();
diff --git a/portable/RVDS/ARM_CM4F/portmacro.h b/portable/RVDS/ARM_CM4F/portmacro.h
index 645926822..03ea9e95a 100644
--- a/portable/RVDS/ARM_CM4F/portmacro.h
+++ b/portable/RVDS/ARM_CM4F/portmacro.h
@@ -99,8 +99,20 @@ typedef unsigned long    UBaseType_t;
 
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired != pdFALSE ) portYIELD( ); } while( 0 )
-#define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+    do                                           \
+    {                                            \
+        if( xSwitchRequired != pdFALSE )         \
+        {                                        \
+            traceISR_EXIT_TO_SCHEDULER();        \
+            portYIELD();                         \
+        }                                        \
+        else                                     \
+        {                                        \
+            traceISR_EXIT();                     \
+        }                                        \
+    } while( 0 )
+#define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
 /* Critical section management. */
diff --git a/portable/RVDS/ARM_CM4_MPU/port.c b/portable/RVDS/ARM_CM4_MPU/port.c
index e5324945a..68562f8ed 100644
--- a/portable/RVDS/ARM_CM4_MPU/port.c
+++ b/portable/RVDS/ARM_CM4_MPU/port.c
@@ -1185,13 +1185,19 @@ void xPortSysTickHandler( void )
     uint32_t ulDummy;
 
     ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
+    traceISR_ENTER();
     {
         /* Increment the RTOS tick. */
         if( xTaskIncrementTick() != pdFALSE )
         {
+            traceISR_EXIT_TO_SCHEDULER();
             /* Pend a context switch. */
             portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
         }
+        else
+        {
+            traceISR_EXIT();
+        }
     }
     portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
 }
diff --git a/portable/RVDS/ARM_CM4_MPU/portmacro.h b/portable/RVDS/ARM_CM4_MPU/portmacro.h
index 4566fba1c..6f7954e9f 100644
--- a/portable/RVDS/ARM_CM4_MPU/portmacro.h
+++ b/portable/RVDS/ARM_CM4_MPU/portmacro.h
@@ -281,9 +281,19 @@ typedef struct MPU_SETTINGS
 
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )                                 \
-    do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
-    while( 0 )
+#define portEND_SWITCHING_ISR( xSwitchRequired )            \
+    do                                                      \
+    {                                                       \
+        if( xSwitchRequired )                               \
+        {                                                   \
+            traceISR_EXIT_TO_SCHEDULER();                   \
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+        }                                                   \
+        else                                                \
+        {                                                   \
+            traceISR_EXIT();                                \
+        }                                                   \
+    } while( 0 )
 #define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/RVDS/ARM_CM7/r0p1/port.c b/portable/RVDS/ARM_CM7/r0p1/port.c
index a7dddc4eb..49310786c 100644
--- a/portable/RVDS/ARM_CM7/r0p1/port.c
+++ b/portable/RVDS/ARM_CM7/r0p1/port.c
@@ -531,14 +531,21 @@ void xPortSysTickHandler( void )
      * known - therefore the slightly faster vPortRaiseBASEPRI() function is used
      * in place of portSET_INTERRUPT_MASK_FROM_ISR(). */
     vPortRaiseBASEPRI();
+    traceISR_ENTER();
     {
         /* Increment the RTOS tick. */
         if( xTaskIncrementTick() != pdFALSE )
         {
+            traceISR_EXIT_TO_SCHEDULER();
+
             /* A context switch is required.  Context switching is performed in
              * the PendSV interrupt.  Pend the PendSV interrupt. */
             portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
         }
+        else
+        {
+            traceISR_EXIT();
+        }
     }
 
     vPortClearBASEPRIFromISR();
diff --git a/portable/RVDS/ARM_CM7/r0p1/portmacro.h b/portable/RVDS/ARM_CM7/r0p1/portmacro.h
index efc1a1a43..2fcf53dfa 100644
--- a/portable/RVDS/ARM_CM7/r0p1/portmacro.h
+++ b/portable/RVDS/ARM_CM7/r0p1/portmacro.h
@@ -99,8 +99,20 @@ typedef unsigned long    UBaseType_t;
 
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired != pdFALSE ) portYIELD( ); } while( 0 )
-#define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+    do                                           \
+    {                                            \
+        if( xSwitchRequired != pdFALSE )         \
+        {                                        \
+            traceISR_EXIT_TO_SCHEDULER();        \
+            portYIELD();                         \
+        }                                        \
+        else                                     \
+        {                                        \
+            traceISR_EXIT();                     \
+        }                                        \
+    } while( 0 )
+#define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
 /* Critical section management. */
diff --git a/portable/Tasking/ARM_CM4F/port.c b/portable/Tasking/ARM_CM4F/port.c
index 55237166b..bc01af91f 100644
--- a/portable/Tasking/ARM_CM4F/port.c
+++ b/portable/Tasking/ARM_CM4F/port.c
@@ -246,12 +246,18 @@ void SysTick_Handler( void )
     uint32_t ulDummy;
 
     ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
+    traceISR_ENTER();
     {
         if( xTaskIncrementTick() != pdFALSE )
         {
+            traceISR_EXIT_TO_SCHEDULER();
             /* Pend a context switch. */
             *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
         }
+        else
+        {
+            traceISR_EXIT();
+        }
     }
     portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
 }
diff --git a/portable/Tasking/ARM_CM4F/portmacro.h b/portable/Tasking/ARM_CM4F/portmacro.h
index 1f159e4b8..516d856d8 100644
--- a/portable/Tasking/ARM_CM4F/portmacro.h
+++ b/portable/Tasking/ARM_CM4F/portmacro.h
@@ -86,10 +86,22 @@ typedef unsigned long    UBaseType_t;
 extern void vPortYield( void );
 #define portNVIC_INT_CTRL     ( ( volatile uint32_t * ) 0xe000ed04 )
 #define portNVIC_PENDSVSET    0x10000000
-#define portYIELD()                                 vPortYield()
+#define portYIELD()                vPortYield()
 
-#define portEND_SWITCHING_ISR( xSwitchRequired )    if( xSwitchRequired ) *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET
-#define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+#define portEND_SWITCHING_ISR( xSwitchRequired )         \
+    do                                                   \
+    {                                                    \
+        if( xSwitchRequired != pdFALSE )                 \
+        {                                                \
+            traceISR_EXIT_TO_SCHEDULER();                \
+            *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET; \
+        }                                                \
+        else                                             \
+        {                                                \
+            traceISR_EXIT();                             \
+        }                                                \
+    } while( 0 )
+#define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
 
diff --git a/portable/ThirdParty/CDK/T-HEAD_CK802/port.c b/portable/ThirdParty/CDK/T-HEAD_CK802/port.c
index 900bae8b7..6e953a0cb 100644
--- a/portable/ThirdParty/CDK/T-HEAD_CK802/port.c
+++ b/portable/ThirdParty/CDK/T-HEAD_CK802/port.c
@@ -125,11 +125,17 @@ void vPortExitCritical( void )
         portLONG ulDummy;
 
         ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
+        traceISR_ENTER();
         {
             if( xTaskIncrementTick() != pdFALSE )
             {
+                traceISR_EXIT_TO_SCHEDULER();
                 portYIELD_FROM_ISR( pdTRUE );
             }
+            else
+            {
+                traceISR_EXIT();
+            }
         }
         portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
     }
diff --git a/portable/ThirdParty/CDK/T-HEAD_CK802/portmacro.h b/portable/ThirdParty/CDK/T-HEAD_CK802/portmacro.h
index d91f5251e..76c72f488 100644
--- a/portable/ThirdParty/CDK/T-HEAD_CK802/portmacro.h
+++ b/portable/ThirdParty/CDK/T-HEAD_CK802/portmacro.h
@@ -152,8 +152,13 @@ extern portLONG pendsvflag;
     do {                                         \
         if( xSwitchRequired != pdFALSE )         \
         {                                        \
+            traceISR_EXIT_TO_SCHEDULER();        \
             portYIELD();                         \
         }                                        \
+        else                                     \
+        {                                        \
+            traceISR_EXIT();                     \
+        }                                        \
     } while( 0 )
 
 #define portYIELD_FROM_ISR( a )    vTaskSwitchContext()
diff --git a/portable/ThirdParty/GCC/Posix/portmacro.h b/portable/ThirdParty/GCC/Posix/portmacro.h
index 6d141f145..6de25da45 100644
--- a/portable/ThirdParty/GCC/Posix/portmacro.h
+++ b/portable/ThirdParty/GCC/Posix/portmacro.h
@@ -81,10 +81,22 @@ typedef unsigned long    TickType_t;
 /* Scheduler utilities. */
 extern void vPortYield( void );
 
-#define portYIELD()                                 vPortYield()
+#define portYIELD()                vPortYield()
 
-#define portEND_SWITCHING_ISR( xSwitchRequired )    if( xSwitchRequired != pdFALSE ) vPortYield( )
-#define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+    do                                           \
+    {                                            \
+        if( xSwitchRequired != pdFALSE )         \
+        {                                        \
+            traceISR_EXIT_TO_SCHEDULER();        \
+            vPortYield();                        \
+        }                                        \
+        else                                     \
+        {                                        \
+            traceISR_EXIT();                     \
+        }                                        \
+    } while( 0 )
+#define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
 /* Critical section management. */
diff --git a/portable/ThirdParty/GCC/RP2040/include/portmacro.h b/portable/ThirdParty/GCC/RP2040/include/portmacro.h
index e1c483458..2b3f822b5 100644
--- a/portable/ThirdParty/GCC/RP2040/include/portmacro.h
+++ b/portable/ThirdParty/GCC/RP2040/include/portmacro.h
@@ -97,9 +97,21 @@ typedef uint32_t         UBaseType_t;
 extern void vPortYield( void );
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-#define portYIELD()                                 vPortYield()
-#define portEND_SWITCHING_ISR( xSwitchRequired )    if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
-#define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+#define portYIELD()                vPortYield()
+#define portEND_SWITCHING_ISR( xSwitchRequired )            \
+    do                                                      \
+    {                                                       \
+        if( xSwitchRequired )                               \
+        {                                                   \
+            traceISR_EXIT_TO_SCHEDULER();                   \
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+        }                                                   \
+        else                                                \
+        {                                                   \
+            traceISR_EXIT();                                \
+        }                                                   \
+    } while( 0 )
+#define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
 
 /*-----------------------------------------------------------*/
 
diff --git a/portable/ThirdParty/GCC/RP2040/port.c b/portable/ThirdParty/GCC/RP2040/port.c
index aef32afba..d022ca2fa 100644
--- a/portable/ThirdParty/GCC/RP2040/port.c
+++ b/portable/ThirdParty/GCC/RP2040/port.c
@@ -741,13 +741,19 @@ void xPortSysTickHandler( void )
     uint32_t ulPreviousMask;
 
     ulPreviousMask = taskENTER_CRITICAL_FROM_ISR();
+    traceISR_ENTER();
     {
         /* Increment the RTOS tick. */
         if( xTaskIncrementTick() != pdFALSE )
         {
+            traceISR_EXIT_TO_SCHEDULER();
             /* Pend a context switch. */
             portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
         }
+        else
+        {
+            traceISR_EXIT();
+        }
     }
     taskEXIT_CRITICAL_FROM_ISR( ulPreviousMask );
 }
diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/port_systick.c b/portable/ThirdParty/GCC/Xtensa_ESP32/port_systick.c
index 69d8e9a03..b7a49170b 100644
--- a/portable/ThirdParty/GCC/Xtensa_ESP32/port_systick.c
+++ b/portable/ThirdParty/GCC/Xtensa_ESP32/port_systick.c
@@ -185,6 +185,7 @@ BaseType_t xPortSysTickHandler( void )
 
     if( ret != pdFALSE )
     {
+        traceISR_EXIT_TO_SCHEDULER();
         portYIELD_FROM_ISR();
     }
     else

From 2bc6188be3957c0a36eed7b3b99f8d1c2054936d Mon Sep 17 00:00:00 2001
From: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Date: Mon, 25 Sep 2023 06:21:15 +0800
Subject: [PATCH 066/424] Update pxMutexHolder is NULL check description (#800)

---
 tasks.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/tasks.c b/tasks.c
index 863535c89..7e32232af 100644
--- a/tasks.c
+++ b/tasks.c
@@ -6186,9 +6186,8 @@ static void prvResetNextTaskUnblockTime( void )
 
         traceENTER_xTaskPriorityInherit( pxMutexHolder );
 
-        /* If the mutex was given back by an interrupt while the queue was
-         * locked then the mutex holder might now be NULL.  _RB_ Is this still
-         * needed as interrupts can no longer use mutexes? */
+        /* If the mutex is taken by an interrupt, the mutex holder is NULL. Priority
+         * inheritance is not applied in this scenario. */
         if( pxMutexHolder != NULL )
         {
             /* If the holder of the mutex has a priority below the priority of

From 2f25cb94f58a8dc86d255ca8fefcc13e632b4d5c Mon Sep 17 00:00:00 2001
From: Moral-Hao <sihunzhilei@126.com>
Date: Mon, 25 Sep 2023 19:22:55 +0800
Subject: [PATCH 067/424] Reduce memory usage of ACL. (#809)

Co-authored-by: Nikhil Kamath <110539926+amazonKamath@users.noreply.github.com>
---
 portable/ARMv8M/non_secure/portmacrocommon.h            | 2 +-
 portable/GCC/ARM_CM23/non_secure/portmacrocommon.h      | 2 +-
 portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h  | 2 +-
 portable/GCC/ARM_CM33/non_secure/portmacrocommon.h      | 2 +-
 portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h  | 2 +-
 portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h     | 2 +-
 portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h | 2 +-
 portable/GCC/ARM_CM3_MPU/portmacro.h                    | 2 +-
 portable/GCC/ARM_CM4_MPU/portmacro.h                    | 2 +-
 portable/GCC/ARM_CM55/non_secure/portmacrocommon.h      | 2 +-
 portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h  | 2 +-
 portable/GCC/ARM_CM85/non_secure/portmacrocommon.h      | 2 +-
 portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h  | 2 +-
 portable/IAR/ARM_CM23/non_secure/portmacrocommon.h      | 2 +-
 portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h  | 2 +-
 portable/IAR/ARM_CM33/non_secure/portmacrocommon.h      | 2 +-
 portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h  | 2 +-
 portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h     | 2 +-
 portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h | 2 +-
 portable/IAR/ARM_CM4F_MPU/portmacro.h                   | 2 +-
 portable/IAR/ARM_CM55/non_secure/portmacrocommon.h      | 2 +-
 portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h  | 2 +-
 portable/IAR/ARM_CM85/non_secure/portmacrocommon.h      | 2 +-
 portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h  | 2 +-
 portable/RVDS/ARM_CM4_MPU/portmacro.h                   | 2 +-
 25 files changed, 25 insertions(+), 25 deletions(-)

diff --git a/portable/ARMv8M/non_secure/portmacrocommon.h b/portable/ARMv8M/non_secure/portmacrocommon.h
index 96a28ca4e..bd6e2f4f2 100644
--- a/portable/ARMv8M/non_secure/portmacrocommon.h
+++ b/portable/ARMv8M/non_secure/portmacrocommon.h
@@ -301,7 +301,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
             xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
             #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
-                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BYTES ) + 1 ];
+                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ];
             #endif
         #endif
     } xMPU_SETTINGS;
diff --git a/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h
index 96a28ca4e..bd6e2f4f2 100644
--- a/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h
@@ -301,7 +301,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
             xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
             #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
-                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BYTES ) + 1 ];
+                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ];
             #endif
         #endif
     } xMPU_SETTINGS;
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h
index 96a28ca4e..bd6e2f4f2 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h
@@ -301,7 +301,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
             xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
             #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
-                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BYTES ) + 1 ];
+                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ];
             #endif
         #endif
     } xMPU_SETTINGS;
diff --git a/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h
index 96a28ca4e..bd6e2f4f2 100644
--- a/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h
@@ -301,7 +301,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
             xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
             #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
-                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BYTES ) + 1 ];
+                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ];
             #endif
         #endif
     } xMPU_SETTINGS;
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h
index 96a28ca4e..bd6e2f4f2 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h
@@ -301,7 +301,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
             xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
             #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
-                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BYTES ) + 1 ];
+                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ];
             #endif
         #endif
     } xMPU_SETTINGS;
diff --git a/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h
index 96a28ca4e..bd6e2f4f2 100644
--- a/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h
@@ -301,7 +301,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
             xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
             #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
-                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BYTES ) + 1 ];
+                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ];
             #endif
         #endif
     } xMPU_SETTINGS;
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
index 96a28ca4e..bd6e2f4f2 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
@@ -301,7 +301,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
             xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
             #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
-                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BYTES ) + 1 ];
+                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ];
             #endif
         #endif
     } xMPU_SETTINGS;
diff --git a/portable/GCC/ARM_CM3_MPU/portmacro.h b/portable/GCC/ARM_CM3_MPU/portmacro.h
index 796e5253c..6964a28ec 100644
--- a/portable/GCC/ARM_CM3_MPU/portmacro.h
+++ b/portable/GCC/ARM_CM3_MPU/portmacro.h
@@ -147,7 +147,7 @@ typedef struct MPU_SETTINGS
     #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
         xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
         #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
-            uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BYTES ) + 1 ];
+            uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ];
         #endif
     #endif
 } xMPU_SETTINGS;
diff --git a/portable/GCC/ARM_CM4_MPU/portmacro.h b/portable/GCC/ARM_CM4_MPU/portmacro.h
index efe8ed2ef..e1f307425 100644
--- a/portable/GCC/ARM_CM4_MPU/portmacro.h
+++ b/portable/GCC/ARM_CM4_MPU/portmacro.h
@@ -241,7 +241,7 @@ typedef struct MPU_SETTINGS
     #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
         xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
         #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
-            uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BYTES ) + 1 ];
+            uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ];
         #endif
     #endif
 } xMPU_SETTINGS;
diff --git a/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h
index 96a28ca4e..bd6e2f4f2 100644
--- a/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h
@@ -301,7 +301,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
             xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
             #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
-                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BYTES ) + 1 ];
+                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ];
             #endif
         #endif
     } xMPU_SETTINGS;
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h
index 96a28ca4e..bd6e2f4f2 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h
@@ -301,7 +301,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
             xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
             #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
-                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BYTES ) + 1 ];
+                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ];
             #endif
         #endif
     } xMPU_SETTINGS;
diff --git a/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h
index 96a28ca4e..bd6e2f4f2 100644
--- a/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h
@@ -301,7 +301,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
             xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
             #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
-                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BYTES ) + 1 ];
+                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ];
             #endif
         #endif
     } xMPU_SETTINGS;
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h
index 96a28ca4e..bd6e2f4f2 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h
@@ -301,7 +301,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
             xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
             #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
-                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BYTES ) + 1 ];
+                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ];
             #endif
         #endif
     } xMPU_SETTINGS;
diff --git a/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h
index 96a28ca4e..bd6e2f4f2 100644
--- a/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h
@@ -301,7 +301,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
             xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
             #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
-                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BYTES ) + 1 ];
+                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ];
             #endif
         #endif
     } xMPU_SETTINGS;
diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h
index 96a28ca4e..bd6e2f4f2 100644
--- a/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h
@@ -301,7 +301,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
             xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
             #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
-                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BYTES ) + 1 ];
+                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ];
             #endif
         #endif
     } xMPU_SETTINGS;
diff --git a/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h
index 96a28ca4e..bd6e2f4f2 100644
--- a/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h
@@ -301,7 +301,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
             xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
             #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
-                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BYTES ) + 1 ];
+                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ];
             #endif
         #endif
     } xMPU_SETTINGS;
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h
index 96a28ca4e..bd6e2f4f2 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h
@@ -301,7 +301,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
             xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
             #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
-                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BYTES ) + 1 ];
+                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ];
             #endif
         #endif
     } xMPU_SETTINGS;
diff --git a/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h
index 96a28ca4e..bd6e2f4f2 100644
--- a/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h
@@ -301,7 +301,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
             xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
             #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
-                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BYTES ) + 1 ];
+                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ];
             #endif
         #endif
     } xMPU_SETTINGS;
diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
index 96a28ca4e..bd6e2f4f2 100644
--- a/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
@@ -301,7 +301,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
             xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
             #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
-                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BYTES ) + 1 ];
+                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ];
             #endif
         #endif
     } xMPU_SETTINGS;
diff --git a/portable/IAR/ARM_CM4F_MPU/portmacro.h b/portable/IAR/ARM_CM4F_MPU/portmacro.h
index 15e65619c..d970edb09 100644
--- a/portable/IAR/ARM_CM4F_MPU/portmacro.h
+++ b/portable/IAR/ARM_CM4F_MPU/portmacro.h
@@ -243,7 +243,7 @@ typedef struct MPU_SETTINGS
     #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
         xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
         #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
-            uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BYTES ) + 1 ];
+            uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ];
         #endif
     #endif
 } xMPU_SETTINGS;
diff --git a/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h
index 96a28ca4e..bd6e2f4f2 100644
--- a/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h
@@ -301,7 +301,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
             xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
             #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
-                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BYTES ) + 1 ];
+                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ];
             #endif
         #endif
     } xMPU_SETTINGS;
diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h
index 96a28ca4e..bd6e2f4f2 100644
--- a/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h
@@ -301,7 +301,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
             xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
             #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
-                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BYTES ) + 1 ];
+                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ];
             #endif
         #endif
     } xMPU_SETTINGS;
diff --git a/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h
index 96a28ca4e..bd6e2f4f2 100644
--- a/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h
@@ -301,7 +301,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
             xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
             #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
-                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BYTES ) + 1 ];
+                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ];
             #endif
         #endif
     } xMPU_SETTINGS;
diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h
index 96a28ca4e..bd6e2f4f2 100644
--- a/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h
@@ -301,7 +301,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
         #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
             xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
             #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
-                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BYTES ) + 1 ];
+                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ];
             #endif
         #endif
     } xMPU_SETTINGS;
diff --git a/portable/RVDS/ARM_CM4_MPU/portmacro.h b/portable/RVDS/ARM_CM4_MPU/portmacro.h
index 6f7954e9f..c70e5719b 100644
--- a/portable/RVDS/ARM_CM4_MPU/portmacro.h
+++ b/portable/RVDS/ARM_CM4_MPU/portmacro.h
@@ -241,7 +241,7 @@ typedef struct MPU_SETTINGS
     #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
         xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
         #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
-            uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BYTES ) + 1 ];
+            uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ];
         #endif
     #endif
 } xMPU_SETTINGS;

From ac5deb155d10b4f68b361172ff21808e8103f903 Mon Sep 17 00:00:00 2001
From: kar-rahul-aws <118818625+kar-rahul-aws@users.noreply.github.com>
Date: Tue, 26 Sep 2023 09:58:02 +0530
Subject: [PATCH 068/424] Remove unwanted variable portACL_ENTRY_SIZE_BYTES
 (#810)

---
 portable/ARMv8M/non_secure/portmacrocommon.h            | 3 +--
 portable/GCC/ARM_CM23/non_secure/portmacrocommon.h      | 3 +--
 portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h  | 3 +--
 portable/GCC/ARM_CM33/non_secure/portmacrocommon.h      | 3 +--
 portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h  | 3 +--
 portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h     | 3 +--
 portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h | 3 +--
 portable/GCC/ARM_CM3_MPU/portmacro.h                    | 3 +--
 portable/GCC/ARM_CM4_MPU/portmacro.h                    | 3 +--
 portable/GCC/ARM_CM55/non_secure/portmacrocommon.h      | 3 +--
 portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h  | 3 +--
 portable/GCC/ARM_CM85/non_secure/portmacrocommon.h      | 3 +--
 portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h  | 3 +--
 portable/IAR/ARM_CM23/non_secure/portmacrocommon.h      | 3 +--
 portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h  | 3 +--
 portable/IAR/ARM_CM33/non_secure/portmacrocommon.h      | 3 +--
 portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h  | 3 +--
 portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h     | 3 +--
 portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h | 3 +--
 portable/IAR/ARM_CM4F_MPU/portmacro.h                   | 3 +--
 portable/IAR/ARM_CM55/non_secure/portmacrocommon.h      | 3 +--
 portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h  | 3 +--
 portable/IAR/ARM_CM85/non_secure/portmacrocommon.h      | 3 +--
 portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h  | 3 +--
 portable/RVDS/ARM_CM4_MPU/portmacro.h                   | 3 +--
 25 files changed, 25 insertions(+), 50 deletions(-)

diff --git a/portable/ARMv8M/non_secure/portmacrocommon.h b/portable/ARMv8M/non_secure/portmacrocommon.h
index bd6e2f4f2..6b389735a 100644
--- a/portable/ARMv8M/non_secure/portmacrocommon.h
+++ b/portable/ARMv8M/non_secure/portmacrocommon.h
@@ -287,8 +287,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
-/* Size of an Access Control List (ACL) entry in bits and bytes. */
-    #define portACL_ENTRY_SIZE_BYTES            ( 4U )
+/* Size of an Access Control List (ACL) entry in bits. */
     #define portACL_ENTRY_SIZE_BITS             ( 32U )
 
     typedef struct MPU_SETTINGS
diff --git a/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h
index bd6e2f4f2..6b389735a 100644
--- a/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h
@@ -287,8 +287,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
-/* Size of an Access Control List (ACL) entry in bits and bytes. */
-    #define portACL_ENTRY_SIZE_BYTES            ( 4U )
+/* Size of an Access Control List (ACL) entry in bits. */
     #define portACL_ENTRY_SIZE_BITS             ( 32U )
 
     typedef struct MPU_SETTINGS
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h
index bd6e2f4f2..6b389735a 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h
@@ -287,8 +287,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
-/* Size of an Access Control List (ACL) entry in bits and bytes. */
-    #define portACL_ENTRY_SIZE_BYTES            ( 4U )
+/* Size of an Access Control List (ACL) entry in bits. */
     #define portACL_ENTRY_SIZE_BITS             ( 32U )
 
     typedef struct MPU_SETTINGS
diff --git a/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h
index bd6e2f4f2..6b389735a 100644
--- a/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h
@@ -287,8 +287,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
-/* Size of an Access Control List (ACL) entry in bits and bytes. */
-    #define portACL_ENTRY_SIZE_BYTES            ( 4U )
+/* Size of an Access Control List (ACL) entry in bits. */
     #define portACL_ENTRY_SIZE_BITS             ( 32U )
 
     typedef struct MPU_SETTINGS
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h
index bd6e2f4f2..6b389735a 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h
@@ -287,8 +287,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
-/* Size of an Access Control List (ACL) entry in bits and bytes. */
-    #define portACL_ENTRY_SIZE_BYTES            ( 4U )
+/* Size of an Access Control List (ACL) entry in bits. */
     #define portACL_ENTRY_SIZE_BITS             ( 32U )
 
     typedef struct MPU_SETTINGS
diff --git a/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h
index bd6e2f4f2..6b389735a 100644
--- a/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h
@@ -287,8 +287,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
-/* Size of an Access Control List (ACL) entry in bits and bytes. */
-    #define portACL_ENTRY_SIZE_BYTES            ( 4U )
+/* Size of an Access Control List (ACL) entry in bits. */
     #define portACL_ENTRY_SIZE_BITS             ( 32U )
 
     typedef struct MPU_SETTINGS
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
index bd6e2f4f2..6b389735a 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
@@ -287,8 +287,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
-/* Size of an Access Control List (ACL) entry in bits and bytes. */
-    #define portACL_ENTRY_SIZE_BYTES            ( 4U )
+/* Size of an Access Control List (ACL) entry in bits. */
     #define portACL_ENTRY_SIZE_BITS             ( 32U )
 
     typedef struct MPU_SETTINGS
diff --git a/portable/GCC/ARM_CM3_MPU/portmacro.h b/portable/GCC/ARM_CM3_MPU/portmacro.h
index 6964a28ec..a65bb2162 100644
--- a/portable/GCC/ARM_CM3_MPU/portmacro.h
+++ b/portable/GCC/ARM_CM3_MPU/portmacro.h
@@ -129,8 +129,7 @@ typedef struct MPU_REGION_SETTINGS
 
 #define MAX_CONTEXT_SIZE                    ( 20 )
 
-/* Size of an Access Control List (ACL) entry in bits and bytes. */
-#define portACL_ENTRY_SIZE_BYTES            ( 4U )
+/* Size of an Access Control List (ACL) entry in bits. */
 #define portACL_ENTRY_SIZE_BITS             ( 32U )
 
 /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
diff --git a/portable/GCC/ARM_CM4_MPU/portmacro.h b/portable/GCC/ARM_CM4_MPU/portmacro.h
index e1f307425..6f8f0c4e9 100644
--- a/portable/GCC/ARM_CM4_MPU/portmacro.h
+++ b/portable/GCC/ARM_CM4_MPU/portmacro.h
@@ -223,8 +223,7 @@ typedef struct MPU_REGION_SETTINGS
 
 #define MAX_CONTEXT_SIZE                    ( 52 )
 
-/* Size of an Access Control List (ACL) entry in bits and bytes. */
-#define portACL_ENTRY_SIZE_BYTES            ( 4U )
+/* Size of an Access Control List (ACL) entry in bits. */
 #define portACL_ENTRY_SIZE_BITS             ( 32U )
 
 /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
diff --git a/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h
index bd6e2f4f2..6b389735a 100644
--- a/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h
@@ -287,8 +287,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
-/* Size of an Access Control List (ACL) entry in bits and bytes. */
-    #define portACL_ENTRY_SIZE_BYTES            ( 4U )
+/* Size of an Access Control List (ACL) entry in bits. */
     #define portACL_ENTRY_SIZE_BITS             ( 32U )
 
     typedef struct MPU_SETTINGS
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h
index bd6e2f4f2..6b389735a 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h
@@ -287,8 +287,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
-/* Size of an Access Control List (ACL) entry in bits and bytes. */
-    #define portACL_ENTRY_SIZE_BYTES            ( 4U )
+/* Size of an Access Control List (ACL) entry in bits. */
     #define portACL_ENTRY_SIZE_BITS             ( 32U )
 
     typedef struct MPU_SETTINGS
diff --git a/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h
index bd6e2f4f2..6b389735a 100644
--- a/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h
@@ -287,8 +287,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
-/* Size of an Access Control List (ACL) entry in bits and bytes. */
-    #define portACL_ENTRY_SIZE_BYTES            ( 4U )
+/* Size of an Access Control List (ACL) entry in bits. */
     #define portACL_ENTRY_SIZE_BITS             ( 32U )
 
     typedef struct MPU_SETTINGS
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h
index bd6e2f4f2..6b389735a 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h
@@ -287,8 +287,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
-/* Size of an Access Control List (ACL) entry in bits and bytes. */
-    #define portACL_ENTRY_SIZE_BYTES            ( 4U )
+/* Size of an Access Control List (ACL) entry in bits. */
     #define portACL_ENTRY_SIZE_BITS             ( 32U )
 
     typedef struct MPU_SETTINGS
diff --git a/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h
index bd6e2f4f2..6b389735a 100644
--- a/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h
@@ -287,8 +287,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
-/* Size of an Access Control List (ACL) entry in bits and bytes. */
-    #define portACL_ENTRY_SIZE_BYTES            ( 4U )
+/* Size of an Access Control List (ACL) entry in bits. */
     #define portACL_ENTRY_SIZE_BITS             ( 32U )
 
     typedef struct MPU_SETTINGS
diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h
index bd6e2f4f2..6b389735a 100644
--- a/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h
@@ -287,8 +287,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
-/* Size of an Access Control List (ACL) entry in bits and bytes. */
-    #define portACL_ENTRY_SIZE_BYTES            ( 4U )
+/* Size of an Access Control List (ACL) entry in bits. */
     #define portACL_ENTRY_SIZE_BITS             ( 32U )
 
     typedef struct MPU_SETTINGS
diff --git a/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h
index bd6e2f4f2..6b389735a 100644
--- a/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h
@@ -287,8 +287,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
-/* Size of an Access Control List (ACL) entry in bits and bytes. */
-    #define portACL_ENTRY_SIZE_BYTES            ( 4U )
+/* Size of an Access Control List (ACL) entry in bits. */
     #define portACL_ENTRY_SIZE_BITS             ( 32U )
 
     typedef struct MPU_SETTINGS
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h
index bd6e2f4f2..6b389735a 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h
@@ -287,8 +287,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
-/* Size of an Access Control List (ACL) entry in bits and bytes. */
-    #define portACL_ENTRY_SIZE_BYTES            ( 4U )
+/* Size of an Access Control List (ACL) entry in bits. */
     #define portACL_ENTRY_SIZE_BITS             ( 32U )
 
     typedef struct MPU_SETTINGS
diff --git a/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h
index bd6e2f4f2..6b389735a 100644
--- a/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h
@@ -287,8 +287,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
-/* Size of an Access Control List (ACL) entry in bits and bytes. */
-    #define portACL_ENTRY_SIZE_BYTES            ( 4U )
+/* Size of an Access Control List (ACL) entry in bits. */
     #define portACL_ENTRY_SIZE_BITS             ( 32U )
 
     typedef struct MPU_SETTINGS
diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
index bd6e2f4f2..6b389735a 100644
--- a/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
@@ -287,8 +287,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
-/* Size of an Access Control List (ACL) entry in bits and bytes. */
-    #define portACL_ENTRY_SIZE_BYTES            ( 4U )
+/* Size of an Access Control List (ACL) entry in bits. */
     #define portACL_ENTRY_SIZE_BITS             ( 32U )
 
     typedef struct MPU_SETTINGS
diff --git a/portable/IAR/ARM_CM4F_MPU/portmacro.h b/portable/IAR/ARM_CM4F_MPU/portmacro.h
index d970edb09..5a102d0ad 100644
--- a/portable/IAR/ARM_CM4F_MPU/portmacro.h
+++ b/portable/IAR/ARM_CM4F_MPU/portmacro.h
@@ -225,8 +225,7 @@ typedef struct MPU_REGION_SETTINGS
 
 #define MAX_CONTEXT_SIZE                    ( 52 )
 
-/* Size of an Access Control List (ACL) entry in bits and bytes. */
-#define portACL_ENTRY_SIZE_BYTES            ( 4U )
+/* Size of an Access Control List (ACL) entry in bits. */
 #define portACL_ENTRY_SIZE_BITS             ( 32U )
 
 /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
diff --git a/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h
index bd6e2f4f2..6b389735a 100644
--- a/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h
@@ -287,8 +287,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
-/* Size of an Access Control List (ACL) entry in bits and bytes. */
-    #define portACL_ENTRY_SIZE_BYTES            ( 4U )
+/* Size of an Access Control List (ACL) entry in bits. */
     #define portACL_ENTRY_SIZE_BITS             ( 32U )
 
     typedef struct MPU_SETTINGS
diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h
index bd6e2f4f2..6b389735a 100644
--- a/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h
@@ -287,8 +287,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
-/* Size of an Access Control List (ACL) entry in bits and bytes. */
-    #define portACL_ENTRY_SIZE_BYTES            ( 4U )
+/* Size of an Access Control List (ACL) entry in bits. */
     #define portACL_ENTRY_SIZE_BITS             ( 32U )
 
     typedef struct MPU_SETTINGS
diff --git a/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h
index bd6e2f4f2..6b389735a 100644
--- a/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h
@@ -287,8 +287,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
-/* Size of an Access Control List (ACL) entry in bits and bytes. */
-    #define portACL_ENTRY_SIZE_BYTES            ( 4U )
+/* Size of an Access Control List (ACL) entry in bits. */
     #define portACL_ENTRY_SIZE_BITS             ( 32U )
 
     typedef struct MPU_SETTINGS
diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h
index bd6e2f4f2..6b389735a 100644
--- a/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h
@@ -287,8 +287,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
-/* Size of an Access Control List (ACL) entry in bits and bytes. */
-    #define portACL_ENTRY_SIZE_BYTES            ( 4U )
+/* Size of an Access Control List (ACL) entry in bits. */
     #define portACL_ENTRY_SIZE_BITS             ( 32U )
 
     typedef struct MPU_SETTINGS
diff --git a/portable/RVDS/ARM_CM4_MPU/portmacro.h b/portable/RVDS/ARM_CM4_MPU/portmacro.h
index c70e5719b..5e32e4a47 100644
--- a/portable/RVDS/ARM_CM4_MPU/portmacro.h
+++ b/portable/RVDS/ARM_CM4_MPU/portmacro.h
@@ -223,8 +223,7 @@ typedef struct MPU_REGION_SETTINGS
 
 #define MAX_CONTEXT_SIZE                    ( 52 )
 
-/* Size of an Access Control List (ACL) entry in bits and bytes. */
-#define portACL_ENTRY_SIZE_BYTES            ( 4U )
+/* Size of an Access Control List (ACL) entry in bits. */
 #define portACL_ENTRY_SIZE_BITS             ( 32U )
 
 /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */

From 84bdb05bd284b9ef4c465331c9921200c5ee7bd6 Mon Sep 17 00:00:00 2001
From: Soren Ptak <ptaksoren@gmail.com>
Date: Tue, 26 Sep 2023 02:06:23 -0700
Subject: [PATCH 069/424] Fix portSWITCH_TO_USER_MODE() on Armv7-M MPU ports
 (#803)

A task's privilege level is stored in ulTaskFlag member in the TCB. Current
implementation of portSWITCH_TO_USER_MODE() does not update this
flag but just lowers the processor's privilege level. This results in many
APIs incorrectly determining task's privilege level and access permissions -

- xPortIsAuthorizedToAccessBuffer
- xPortIsTaskPrivileged
- xPortIsAuthorizedToAccessKernelObject

This PR fixes the portSWITCH_TO_USER_MODE() implementation to correctly
update the ulTaskFlag member in the TCB before lowering the processor's
privilege level.
---
 portable/GCC/ARM_CM3_MPU/port.c       | 20 +++++++++++-
 portable/GCC/ARM_CM3_MPU/portmacro.h  | 17 +++++++---
 portable/GCC/ARM_CM4_MPU/port.c       | 20 +++++++++++-
 portable/GCC/ARM_CM4_MPU/portmacro.h  | 17 +++++++---
 portable/IAR/ARM_CM4F_MPU/port.c      | 20 +++++++++++-
 portable/IAR/ARM_CM4F_MPU/portmacro.h | 17 +++++++---
 portable/RVDS/ARM_CM4_MPU/port.c      | 47 +++++++++++++++------------
 portable/RVDS/ARM_CM4_MPU/portmacro.h | 18 ++++++----
 8 files changed, 131 insertions(+), 45 deletions(-)

diff --git a/portable/GCC/ARM_CM3_MPU/port.c b/portable/GCC/ARM_CM3_MPU/port.c
index 3c46dfde8..ea2b9355e 100644
--- a/portable/GCC/ARM_CM3_MPU/port.c
+++ b/portable/GCC/ARM_CM3_MPU/port.c
@@ -185,6 +185,11 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
  */
 void vResetPrivilege( void ) __attribute__( ( naked ) );
 
+/**
+ * @brief Make a task unprivileged.
+ */
+void vPortSwitchToUserMode( void );
+
 /**
  * @brief Enter critical section.
  */
@@ -284,7 +289,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
     }
     else
     {
-        xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
+        xMPUSettings->ulTaskFlags &= ( ~( portTASK_IS_PRIVILEGED_FLAG ) );
         xMPUSettings->ulContext[ 0 ] = portINITIAL_CONTROL_IF_UNPRIVILEGED;
     }
 
@@ -1209,6 +1214,19 @@ void vResetPrivilege( void ) /* __attribute__ (( naked )) */
 }
 /*-----------------------------------------------------------*/
 
+void vPortSwitchToUserMode( void )
+{
+    /* Load the current task's MPU settings from its TCB. */
+    xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL );
+
+    /* Mark the task as unprivileged. */
+    xTaskMpuSettings->ulTaskFlags &= ( ~( portTASK_IS_PRIVILEGED_FLAG ) );
+
+    /* Lower the processor's privilege level. */
+    vResetPrivilege();
+}
+/*-----------------------------------------------------------*/
+
 void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
                                 const struct xMEMORY_REGION * const xRegions,
                                 StackType_t * pxBottomOfStack,
diff --git a/portable/GCC/ARM_CM3_MPU/portmacro.h b/portable/GCC/ARM_CM3_MPU/portmacro.h
index a65bb2162..d0822e144 100644
--- a/portable/GCC/ARM_CM3_MPU/portmacro.h
+++ b/portable/GCC/ARM_CM3_MPU/portmacro.h
@@ -96,8 +96,6 @@ typedef unsigned long    UBaseType_t;
 #define portNUM_CONFIGURABLE_REGIONS                             ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
 #define portTOTAL_NUM_REGIONS_IN_TCB                             ( portNUM_CONFIGURABLE_REGIONS + 1 )     /* Plus one to make space for the stack region. */
 
-#define portSWITCH_TO_USER_MODE()    __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0 " ::: "r0", "memory" )
-
 typedef struct MPU_REGION_REGISTERS
 {
     uint32_t ulRegionBaseAddress;
@@ -268,24 +266,33 @@ extern void vPortExitCritical( void );
 
 extern BaseType_t xIsPrivileged( void );
 extern void vResetPrivilege( void );
+extern void vPortSwitchToUserMode( void );
 
 /**
  * @brief Checks whether or not the processor is privileged.
  *
  * @return 1 if the processor is already privileged, 0 otherwise.
  */
-#define portIS_PRIVILEGED()      xIsPrivileged()
+#define portIS_PRIVILEGED()          xIsPrivileged()
 
 /**
  * @brief Raise an SVC request to raise privilege.
  */
-#define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+#define portRAISE_PRIVILEGE()        __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
 
 /**
  * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
  * register.
  */
-#define portRESET_PRIVILEGE()    vResetPrivilege()
+#define portRESET_PRIVILEGE()        vResetPrivilege()
+
+/**
+ * @brief Make a task unprivileged.
+ *
+ * It must be called from privileged tasks only. Calling it from unprivileged
+ * task will result in a memory protection fault.
+ */
+#define portSWITCH_TO_USER_MODE()    vPortSwitchToUserMode()
 /*-----------------------------------------------------------*/
 
 extern BaseType_t xPortIsTaskPrivileged( void );
diff --git a/portable/GCC/ARM_CM4_MPU/port.c b/portable/GCC/ARM_CM4_MPU/port.c
index 861c400cd..e2ef1f054 100644
--- a/portable/GCC/ARM_CM4_MPU/port.c
+++ b/portable/GCC/ARM_CM4_MPU/port.c
@@ -206,6 +206,11 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
  */
 void vResetPrivilege( void ) __attribute__( ( naked ) );
 
+/**
+ * @brief Make a task unprivileged.
+ */
+void vPortSwitchToUserMode( void );
+
 /**
  * @brief Enter critical section.
  */
@@ -312,7 +317,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
     }
     else
     {
-        xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
+        xMPUSettings->ulTaskFlags &= ( ~( portTASK_IS_PRIVILEGED_FLAG ) );
         xMPUSettings->ulContext[ 0 ] = portINITIAL_CONTROL_IF_UNPRIVILEGED;
     }
 
@@ -1390,6 +1395,19 @@ void vResetPrivilege( void ) /* __attribute__ (( naked )) */
 }
 /*-----------------------------------------------------------*/
 
+void vPortSwitchToUserMode( void )
+{
+    /* Load the current task's MPU settings from its TCB. */
+    xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL );
+
+    /* Mark the task as unprivileged. */
+    xTaskMpuSettings->ulTaskFlags &= ( ~( portTASK_IS_PRIVILEGED_FLAG ) );
+
+    /* Lower the processor's privilege level. */
+    vResetPrivilege();
+}
+/*-----------------------------------------------------------*/
+
 void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
                                 const struct xMEMORY_REGION * const xRegions,
                                 StackType_t * pxBottomOfStack,
diff --git a/portable/GCC/ARM_CM4_MPU/portmacro.h b/portable/GCC/ARM_CM4_MPU/portmacro.h
index 6f8f0c4e9..1f62279b0 100644
--- a/portable/GCC/ARM_CM4_MPU/portmacro.h
+++ b/portable/GCC/ARM_CM4_MPU/portmacro.h
@@ -190,8 +190,6 @@ typedef unsigned long    UBaseType_t;
 #define portNUM_CONFIGURABLE_REGIONS      ( configTOTAL_MPU_REGIONS - 5UL )
 #define portTOTAL_NUM_REGIONS_IN_TCB      ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus 1 to create space for the stack region. */
 
-#define portSWITCH_TO_USER_MODE()    __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0 " ::: "r0", "memory" )
-
 typedef struct MPU_REGION_REGISTERS
 {
     uint32_t ulRegionBaseAddress;
@@ -362,24 +360,33 @@ extern void vPortExitCritical( void );
 
 extern BaseType_t xIsPrivileged( void );
 extern void vResetPrivilege( void );
+extern void vPortSwitchToUserMode( void );
 
 /**
  * @brief Checks whether or not the processor is privileged.
  *
  * @return 1 if the processor is already privileged, 0 otherwise.
  */
-#define portIS_PRIVILEGED()      xIsPrivileged()
+#define portIS_PRIVILEGED()          xIsPrivileged()
 
 /**
  * @brief Raise an SVC request to raise privilege.
  */
-#define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+#define portRAISE_PRIVILEGE()        __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
 
 /**
  * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
  * register.
  */
-#define portRESET_PRIVILEGE()    vResetPrivilege()
+#define portRESET_PRIVILEGE()        vResetPrivilege()
+
+/**
+ * @brief Make a task unprivileged.
+ *
+ * It must be called from privileged tasks only. Calling it from unprivileged
+ * task will result in a memory protection fault.
+ */
+#define portSWITCH_TO_USER_MODE()    vPortSwitchToUserMode()
 /*-----------------------------------------------------------*/
 
 extern BaseType_t xPortIsTaskPrivileged( void );
diff --git a/portable/IAR/ARM_CM4F_MPU/port.c b/portable/IAR/ARM_CM4F_MPU/port.c
index f7b9f45ce..6db7bd796 100644
--- a/portable/IAR/ARM_CM4F_MPU/port.c
+++ b/portable/IAR/ARM_CM4F_MPU/port.c
@@ -283,6 +283,11 @@ extern void vPortRestoreContextOfFirstTask( void ) PRIVILEGED_FUNCTION;
  */
 BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
 
+/**
+ * @brief Make a task unprivileged.
+ */
+void vPortSwitchToUserMode( void );
+
 /*-----------------------------------------------------------*/
 
 /* Each task maintains its own interrupt status in the critical nesting
@@ -318,7 +323,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
     }
     else
     {
-        xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
+        xMPUSettings->ulTaskFlags &= ( ~( portTASK_IS_PRIVILEGED_FLAG ) );
         xMPUSettings->ulContext[ 0 ] = portINITIAL_CONTROL_IF_UNPRIVILEGED;
     }
 
@@ -741,6 +746,19 @@ BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */
 }
 /*-----------------------------------------------------------*/
 
+void vPortSwitchToUserMode( void )
+{
+    /* Load the current task's MPU settings from its TCB. */
+    xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL );
+
+    /* Mark the task as unprivileged. */
+    xTaskMpuSettings->ulTaskFlags &= ( ~( portTASK_IS_PRIVILEGED_FLAG ) );
+
+    /* Lower the processor's privilege level. */
+    vResetPrivilege();
+}
+/*-----------------------------------------------------------*/
+
 /*
  * See header file for description.
  */
diff --git a/portable/IAR/ARM_CM4F_MPU/portmacro.h b/portable/IAR/ARM_CM4F_MPU/portmacro.h
index 5a102d0ad..98b087e11 100644
--- a/portable/IAR/ARM_CM4F_MPU/portmacro.h
+++ b/portable/IAR/ARM_CM4F_MPU/portmacro.h
@@ -192,8 +192,6 @@ typedef unsigned long    UBaseType_t;
 #define portNUM_CONFIGURABLE_REGIONS      ( configTOTAL_MPU_REGIONS - 5UL )
 #define portTOTAL_NUM_REGIONS_IN_TCB      ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus 1 to create space for the stack region. */
 
-#define portSWITCH_TO_USER_MODE()    __asm volatile ( " mrs r0, control \n orr r0, r0, #1 \n msr control, r0 " ::: "r0", "memory" )
-
 typedef struct MPU_REGION_REGISTERS
 {
     uint32_t ulRegionBaseAddress;
@@ -390,24 +388,33 @@ portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
 
 extern BaseType_t xIsPrivileged( void );
 extern void vResetPrivilege( void );
+extern void vPortSwitchToUserMode( void );
 
 /**
  * @brief Checks whether or not the processor is privileged.
  *
  * @return 1 if the processor is already privileged, 0 otherwise.
  */
-#define portIS_PRIVILEGED()      xIsPrivileged()
+#define portIS_PRIVILEGED()          xIsPrivileged()
 
 /**
  * @brief Raise an SVC request to raise privilege.
  */
-#define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+#define portRAISE_PRIVILEGE()        __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
 
 /**
  * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
  * register.
  */
-#define portRESET_PRIVILEGE()    vResetPrivilege()
+#define portRESET_PRIVILEGE()        vResetPrivilege()
+
+/**
+ * @brief Make a task unprivileged.
+ *
+ * It must be called from privileged tasks only. Calling it from unprivileged
+ * task will result in a memory protection fault.
+ */
+#define portSWITCH_TO_USER_MODE()    vPortSwitchToUserMode()
 /*-----------------------------------------------------------*/
 
 extern BaseType_t xPortIsTaskPrivileged( void );
diff --git a/portable/RVDS/ARM_CM4_MPU/port.c b/portable/RVDS/ARM_CM4_MPU/port.c
index 68562f8ed..e7e26b969 100644
--- a/portable/RVDS/ARM_CM4_MPU/port.c
+++ b/portable/RVDS/ARM_CM4_MPU/port.c
@@ -219,6 +219,11 @@ BaseType_t xIsPrivileged( void );
  */
 void vResetPrivilege( void );
 
+/**
+ * @brief Make a task unprivileged.
+ */
+void vPortSwitchToUserMode( void );
+
 /**
  * @brief Enter critical section.
  */
@@ -312,7 +317,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
     }
     else
     {
-        xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
+        xMPUSettings->ulTaskFlags &= ( ~( portTASK_IS_PRIVILEGED_FLAG ) );
         xMPUSettings->ulContext[ 0 ] = portINITIAL_CONTROL_IF_UNPRIVILEGED;
     }
 
@@ -1219,19 +1224,6 @@ __weak void vSetupTimerInterrupt( void )
 }
 /*-----------------------------------------------------------*/
 
-__asm void vPortSwitchToUserMode( void )
-{
-/* *INDENT-OFF* */
-    PRESERVE8
-
-    mrs r0, control
-    orr r0, #1
-    msr control, r0
-    bx r14
-/* *INDENT-ON* */
-}
-/*-----------------------------------------------------------*/
-
 __asm void vPortEnableVFP( void )
 {
 /* *INDENT-OFF* */
@@ -1349,10 +1341,10 @@ __asm BaseType_t xIsPrivileged( void )
     PRESERVE8
 
     mrs r0, control /* r0 = CONTROL. */
-    tst r0, #1     /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+    tst r0, #1      /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
     ite ne
-    movne r0, #0   /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
-    moveq r0, #1   /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+    movne r0, #0    /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+    moveq r0, #1    /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
     bx lr           /* Return. */
 /* *INDENT-ON* */
 }
@@ -1363,14 +1355,27 @@ __asm void vResetPrivilege( void )
 /* *INDENT-OFF* */
     PRESERVE8
 
-    mrs r0, control /* r0 = CONTROL. */
-    orrs r0, #1    /* r0 = r0 | 1. */
-    msr control, r0 /* CONTROL = r0. */
-    bx lr           /* Return. */
+    mrs r0, control     /* r0 = CONTROL. */
+    orrs r0, #1         /* r0 = r0 | 1. */
+    msr control, r0     /* CONTROL = r0. */
+    bx lr               /* Return. */
 /* *INDENT-ON* */
 }
 /*-----------------------------------------------------------*/
 
+void vPortSwitchToUserMode( void )
+{
+    /* Load the current task's MPU settings from its TCB. */
+    xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL );
+
+    /* Mark the task as unprivileged. */
+    xTaskMpuSettings->ulTaskFlags &= ( ~( portTASK_IS_PRIVILEGED_FLAG ) );
+
+    /* Lower the processor's privilege level. */
+    vResetPrivilege();
+}
+/*-----------------------------------------------------------*/
+
 void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
                                 const struct xMEMORY_REGION * const xRegions,
                                 StackType_t * pxBottomOfStack,
diff --git a/portable/RVDS/ARM_CM4_MPU/portmacro.h b/portable/RVDS/ARM_CM4_MPU/portmacro.h
index 5e32e4a47..1d17b4c10 100644
--- a/portable/RVDS/ARM_CM4_MPU/portmacro.h
+++ b/portable/RVDS/ARM_CM4_MPU/portmacro.h
@@ -189,9 +189,6 @@ typedef unsigned long    UBaseType_t;
 #define portNUM_CONFIGURABLE_REGIONS      ( configTOTAL_MPU_REGIONS - 5UL )
 #define portTOTAL_NUM_REGIONS_IN_TCB      ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus 1 to create space for the stack region. */
 
-void vPortSwitchToUserMode( void );
-#define portSWITCH_TO_USER_MODE()    vPortSwitchToUserMode()
-
 typedef struct MPU_REGION_REGISTERS
 {
     uint32_t ulRegionBaseAddress;
@@ -356,24 +353,33 @@ extern void vPortExitCritical( void );
 
 extern BaseType_t xIsPrivileged( void );
 extern void vResetPrivilege( void );
+extern void vPortSwitchToUserMode( void );
 
 /**
  * @brief Checks whether or not the processor is privileged.
  *
  * @return 1 if the processor is already privileged, 0 otherwise.
  */
-#define portIS_PRIVILEGED()      xIsPrivileged()
+#define portIS_PRIVILEGED()          xIsPrivileged()
 
 /**
  * @brief Raise an SVC request to raise privilege.
  */
-#define portRAISE_PRIVILEGE()    __asm { svc portSVC_RAISE_PRIVILEGE }
+#define portRAISE_PRIVILEGE()        __asm { svc portSVC_RAISE_PRIVILEGE }
 
 /**
  * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
  * register.
  */
-#define portRESET_PRIVILEGE()    vResetPrivilege()
+#define portRESET_PRIVILEGE()        vResetPrivilege()
+
+/**
+ * @brief Make a task unprivileged.
+ *
+ * It must be called from privileged tasks only. Calling it from unprivileged
+ * task will result in a memory protection fault.
+ */
+#define portSWITCH_TO_USER_MODE()    vPortSwitchToUserMode()
 /*-----------------------------------------------------------*/
 
 extern BaseType_t xPortIsTaskPrivileged( void );

From 96d6190b61b4835cc36896668807f7b0d27f2745 Mon Sep 17 00:00:00 2001
From: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Date: Tue, 26 Sep 2023 23:07:18 +0530
Subject: [PATCH 070/424] Replace sprintf with snprintf (#802)

This change necessitates the introduction of 2 new APIs:

void vTaskListTasks( char * pcWriteBuffer, size_t uxBufferLength );
void vTaskGetRunTimeStatistics( char * pcWriteBuffer, size_t uxBufferLength );

These 2 APIs behave exactly as vTaskList and vTaskGetRunTimeStats
except the fact that they take the length of the pcWriteBuffer as the
second argument to ensure that we do not write past the buffer.

vTaskList and vTaskGetRunTimeStats assume that the length of the
buffer is configSTATS_BUFFER_MAX_LENGTH which defaults to 0xFFFF.
This is done to ensure that the existing applications do not break.
New applications should use the new APIs to avoid memory corruption.
---
 include/FreeRTOS.h |  20 ++--
 include/task.h     | 136 ++++++++++++++++++++++++--
 tasks.c            | 236 +++++++++++++++++++++++++++++++++++----------
 3 files changed, 328 insertions(+), 64 deletions(-)

diff --git a/include/FreeRTOS.h b/include/FreeRTOS.h
index 44ebb063e..d0d63f1a2 100644
--- a/include/FreeRTOS.h
+++ b/include/FreeRTOS.h
@@ -2154,20 +2154,20 @@
     #define traceRETURN_vTaskExitCriticalFromISR()
 #endif
 
-#ifndef traceENTER_vTaskList
-    #define traceENTER_vTaskList( pcWriteBuffer )
+#ifndef traceENTER_vTaskListTasks
+    #define traceENTER_vTaskListTasks( pcWriteBuffer, uxBufferLength )
 #endif
 
-#ifndef traceRETURN_vTaskList
-    #define traceRETURN_vTaskList()
+#ifndef traceRETURN_vTaskListTasks
+    #define traceRETURN_vTaskListTasks()
 #endif
 
-#ifndef traceENTER_vTaskGetRunTimeStats
-    #define traceENTER_vTaskGetRunTimeStats( pcWriteBuffer )
+#ifndef traceENTER_vTaskGetRunTimeStatistics
+    #define traceENTER_vTaskGetRunTimeStatistics( pcWriteBuffer, uxBufferLength )
 #endif
 
-#ifndef traceRETURN_vTaskGetRunTimeStats
-    #define traceRETURN_vTaskGetRunTimeStats()
+#ifndef traceRETURN_vTaskGetRunTimeStatistics
+    #define traceRETURN_vTaskGetRunTimeStatistics()
 #endif
 
 #ifndef traceENTER_uxTaskResetEventItemValue
@@ -2686,6 +2686,10 @@
     #endif
 #endif
 
+#ifndef configSTATS_BUFFER_MAX_LENGTH
+    #define configSTATS_BUFFER_MAX_LENGTH    0xFFFF
+#endif
+
 #ifndef configSTACK_DEPTH_TYPE
 
 /* Defaults to uint16_t for backward compatibility, but can be overridden
diff --git a/include/task.h b/include/task.h
index a1e1a7fbb..8d6742c7f 100644
--- a/include/task.h
+++ b/include/task.h
@@ -2074,6 +2074,60 @@ UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
                                   const UBaseType_t uxArraySize,
                                   configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) PRIVILEGED_FUNCTION;
 
+/**
+ * task. h
+ * @code{c}
+ * void vTaskListTasks( char *pcWriteBuffer, size_t uxBufferLength );
+ * @endcode
+ *
+ * configUSE_TRACE_FACILITY and configUSE_STATS_FORMATTING_FUNCTIONS must
+ * both be defined as 1 for this function to be available.  See the
+ * configuration section of the FreeRTOS.org website for more information.
+ *
+ * NOTE 1: This function will disable interrupts for its duration.  It is
+ * not intended for normal application runtime use but as a debug aid.
+ *
+ * Lists all the current tasks, along with their current state and stack
+ * usage high water mark.
+ *
+ * Tasks are reported as blocked ('B'), ready ('R'), deleted ('D') or
+ * suspended ('S').
+ *
+ * PLEASE NOTE:
+ *
+ * This function is provided for convenience only, and is used by many of the
+ * demo applications.  Do not consider it to be part of the scheduler.
+ *
+ * vTaskListTasks() calls uxTaskGetSystemState(), then formats part of the
+ * uxTaskGetSystemState() output into a human readable table that displays task:
+ * names, states, priority, stack usage and task number.
+ * Stack usage specified as the number of unused StackType_t words stack can hold
+ * on top of stack - not the number of bytes.
+ *
+ * vTaskListTasks() has a dependency on the snprintf() C library function that might
+ * bloat the code size, use a lot of stack, and provide different results on
+ * different platforms.  An alternative, tiny, third party, and limited
+ * functionality implementation of snprintf() is provided in many of the
+ * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note
+ * printf-stdarg.c does not provide a full snprintf() implementation!).
+ *
+ * It is recommended that production systems call uxTaskGetSystemState()
+ * directly to get access to raw stats data, rather than indirectly through a
+ * call to vTaskListTasks().
+ *
+ * @param pcWriteBuffer A buffer into which the above mentioned details
+ * will be written, in ASCII form.  This buffer is assumed to be large
+ * enough to contain the generated report.  Approximately 40 bytes per
+ * task should be sufficient.
+ *
+ * @param uxBufferLength Length of the pcWriteBuffer.
+ *
+ * \defgroup vTaskListTasks vTaskListTasks
+ * \ingroup TaskUtils
+ */
+void vTaskListTasks( char * pcWriteBuffer,
+                     size_t uxBufferLength ) PRIVILEGED_FUNCTION;
+
 /**
  * task. h
  * @code{c}
@@ -2084,6 +2138,11 @@ UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
  * both be defined as 1 for this function to be available.  See the
  * configuration section of the FreeRTOS.org website for more information.
  *
+ * WARN: This function assumes that the pcWriteBuffer is of length
+ * configSTATS_BUFFER_MAX_LENGTH. This function is there only for
+ * backward compatibility. New applications are recommended to
+ * use vTaskListTasks and supply the length of the pcWriteBuffer explicitly.
+ *
  * NOTE 1: This function will disable interrupts for its duration.  It is
  * not intended for normal application runtime use but as a debug aid.
  *
@@ -2104,10 +2163,10 @@ UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
  * Stack usage specified as the number of unused StackType_t words stack can hold
  * on top of stack - not the number of bytes.
  *
- * vTaskList() has a dependency on the sprintf() C library function that might
+ * vTaskList() has a dependency on the snprintf() C library function that might
  * bloat the code size, use a lot of stack, and provide different results on
  * different platforms.  An alternative, tiny, third party, and limited
- * functionality implementation of sprintf() is provided in many of the
+ * functionality implementation of snprintf() is provided in many of the
  * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note
  * printf-stdarg.c does not provide a full snprintf() implementation!).
  *
@@ -2123,7 +2182,66 @@ UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
  * \defgroup vTaskList vTaskList
  * \ingroup TaskUtils
  */
-void vTaskList( char * pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+#define vTaskList( pcWriteBuffer )    vTaskListTasks( pcWriteBuffer, configSTATS_BUFFER_MAX_LENGTH )
+
+/**
+ * task. h
+ * @code{c}
+ * void vTaskGetRunTimeStatistics( char *pcWriteBuffer, size_t uxBufferLength );
+ * @endcode
+ *
+ * configGENERATE_RUN_TIME_STATS and configUSE_STATS_FORMATTING_FUNCTIONS
+ * must both be defined as 1 for this function to be available.  The application
+ * must also then provide definitions for
+ * portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE()
+ * to configure a peripheral timer/counter and return the timers current count
+ * value respectively.  The counter should be at least 10 times the frequency of
+ * the tick count.
+ *
+ * NOTE 1: This function will disable interrupts for its duration.  It is
+ * not intended for normal application runtime use but as a debug aid.
+ *
+ * Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total
+ * accumulated execution time being stored for each task.  The resolution
+ * of the accumulated time value depends on the frequency of the timer
+ * configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro.
+ * Calling vTaskGetRunTimeStatistics() writes the total execution time of each
+ * task into a buffer, both as an absolute count value and as a percentage
+ * of the total system execution time.
+ *
+ * NOTE 2:
+ *
+ * This function is provided for convenience only, and is used by many of the
+ * demo applications.  Do not consider it to be part of the scheduler.
+ *
+ * vTaskGetRunTimeStatistics() calls uxTaskGetSystemState(), then formats part of
+ * the uxTaskGetSystemState() output into a human readable table that displays the
+ * amount of time each task has spent in the Running state in both absolute and
+ * percentage terms.
+ *
+ * vTaskGetRunTimeStatistics() has a dependency on the snprintf() C library function
+ * that might bloat the code size, use a lot of stack, and provide different
+ * results on different platforms.  An alternative, tiny, third party, and
+ * limited functionality implementation of snprintf() is provided in many of the
+ * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note
+ * printf-stdarg.c does not provide a full snprintf() implementation!).
+ *
+ * It is recommended that production systems call uxTaskGetSystemState() directly
+ * to get access to raw stats data, rather than indirectly through a call to
+ * vTaskGetRunTimeStatistics().
+ *
+ * @param pcWriteBuffer A buffer into which the execution times will be
+ * written, in ASCII form.  This buffer is assumed to be large enough to
+ * contain the generated report.  Approximately 40 bytes per task should
+ * be sufficient.
+ *
+ * @param uxBufferLength Length of the pcWriteBuffer.
+ *
+ * \defgroup vTaskGetRunTimeStatistics vTaskGetRunTimeStatistics
+ * \ingroup TaskUtils
+ */
+void vTaskGetRunTimeStatistics( char * pcWriteBuffer,
+                                size_t uxBufferLength ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
 
 /**
  * task. h
@@ -2139,6 +2257,12 @@ void vTaskList( char * pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unquali
  * value respectively.  The counter should be at least 10 times the frequency of
  * the tick count.
  *
+ * WARN: This function assumes that the pcWriteBuffer is of length
+ * configSTATS_BUFFER_MAX_LENGTH. This function is there only for
+ * backward compatiblity. New applications are recommended to use
+ * vTaskGetRunTimeStatistics and supply the length of the pcWriteBuffer
+ * explicitly.
+ *
  * NOTE 1: This function will disable interrupts for its duration.  It is
  * not intended for normal application runtime use but as a debug aid.
  *
@@ -2160,10 +2284,10 @@ void vTaskList( char * pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unquali
  * amount of time each task has spent in the Running state in both absolute and
  * percentage terms.
  *
- * vTaskGetRunTimeStats() has a dependency on the sprintf() C library function
+ * vTaskGetRunTimeStats() has a dependency on the snprintf() C library function
  * that might bloat the code size, use a lot of stack, and provide different
  * results on different platforms.  An alternative, tiny, third party, and
- * limited functionality implementation of sprintf() is provided in many of the
+ * limited functionality implementation of snprintf() is provided in many of the
  * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note
  * printf-stdarg.c does not provide a full snprintf() implementation!).
  *
@@ -2179,7 +2303,7 @@ void vTaskList( char * pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unquali
  * \defgroup vTaskGetRunTimeStats vTaskGetRunTimeStats
  * \ingroup TaskUtils
  */
-void vTaskGetRunTimeStats( char * pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+#define vTaskGetRunTimeStats( pcWriteBuffer )    vTaskGetRunTimeStatistics( pcWriteBuffer, configSTATS_BUFFER_MAX_LENGTH )
 
 /**
  * task. h
diff --git a/tasks.c b/tasks.c
index 7e32232af..84bc87bf2 100644
--- a/tasks.c
+++ b/tasks.c
@@ -719,6 +719,32 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
     extern void vApplicationMinimalIdleHook( void );
 #endif /* #if ( configUSE_MINIMAL_IDLE_HOOK == 1 ) */
 
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )
+
+/*
+ * Convert the snprintf return value to the number of characters
+ * written. The following are the possible cases:
+ *
+ * 1. The buffer supplied to snprintf is large enough to hold the
+ *    generated string. The return value in this case is the number
+ *    of characters actually written, not counting the terminating
+ *    null character.
+ * 2. The buffer supplied to snprintf is NOT large enough to hold
+ *    the generated string. The return value in this case is the
+ *    number of characters that would have been written if the
+ *    buffer had been sufficiently large, not counting the
+ *    terminating null character.
+ * 3. Encoding error. The return value in this case is a negative
+ *    number.
+ *
+ * From 1 and 2 above ==> Only when the return value is non-negative
+ * and less than the supplied buffer length, the string has been
+ * completely written.
+ */
+    static size_t prvSnprintfReturnValueToCharsWritten( int iSnprintfReturnValue,
+                                                        size_t n );
+
+#endif /* #if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) ) */
 /*-----------------------------------------------------------*/
 
 #if ( configNUMBER_OF_CORES > 1 )
@@ -1914,6 +1940,39 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
 #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
 /*-----------------------------------------------------------*/
 
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )
+
+    static size_t prvSnprintfReturnValueToCharsWritten( int iSnprintfReturnValue,
+                                                        size_t n )
+    {
+        size_t uxCharsWritten;
+
+        if( iSnprintfReturnValue < 0 )
+        {
+            /* Encoding error - Return 0 to indicate that nothing
+             * was written to the buffer. */
+            uxCharsWritten = 0;
+        }
+        else if( iSnprintfReturnValue >= ( int ) n )
+        {
+            /* This is the case when the supplied buffer is not
+             * large to hold the generated string. Return the
+             * number of characters actually written without
+             * counting the terminating NULL character. */
+            uxCharsWritten = n - 1;
+        }
+        else
+        {
+            /* Complete string was written to the buffer. */
+            uxCharsWritten = ( size_t ) iSnprintfReturnValue;
+        }
+
+        return uxCharsWritten;
+    }
+
+#endif /* #if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) ) */
+/*-----------------------------------------------------------*/
+
 #if ( INCLUDE_vTaskDelete == 1 )
 
     void vTaskDelete( TaskHandle_t xTaskToDelete )
@@ -6812,13 +6871,18 @@ static void prvResetNextTaskUnblockTime( void )
 
 #if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )
 
-    void vTaskList( char * pcWriteBuffer )
+    void vTaskListTasks( char * pcWriteBuffer,
+                         size_t uxBufferLength )
     {
         TaskStatus_t * pxTaskStatusArray;
+        size_t uxConsumedBufferLength = 0;
+        size_t uxCharsWrittenBySnprintf;
+        int iSnprintfReturnValue;
+        BaseType_t xOutputBufferFull = pdFALSE;
         UBaseType_t uxArraySize, x;
         char cStatus;
 
-        traceENTER_vTaskList( pcWriteBuffer );
+        traceENTER_vTaskListTasks( pcWriteBuffer, uxBufferLength );
 
         /*
          * PLEASE NOTE:
@@ -6827,23 +6891,23 @@ static void prvResetNextTaskUnblockTime( void )
          * of the demo applications.  Do not consider it to be part of the
          * scheduler.
          *
-         * vTaskList() calls uxTaskGetSystemState(), then formats part of the
+         * vTaskListTasks() calls uxTaskGetSystemState(), then formats part of the
          * uxTaskGetSystemState() output into a human readable table that
          * displays task: names, states, priority, stack usage and task number.
          * Stack usage specified as the number of unused StackType_t words stack can hold
          * on top of stack - not the number of bytes.
          *
-         * vTaskList() has a dependency on the sprintf() C library function that
+         * vTaskListTasks() has a dependency on the snprintf() C library function that
          * might bloat the code size, use a lot of stack, and provide different
          * results on different platforms.  An alternative, tiny, third party,
-         * and limited functionality implementation of sprintf() is provided in
+         * and limited functionality implementation of snprintf() is provided in
          * many of the FreeRTOS/Demo sub-directories in a file called
          * printf-stdarg.c (note printf-stdarg.c does not provide a full
          * snprintf() implementation!).
          *
          * It is recommended that production systems call uxTaskGetSystemState()
          * directly to get access to raw stats data, rather than indirectly
-         * through a call to vTaskList().
+         * through a call to vTaskListTasks().
          */
 
 
@@ -6865,7 +6929,7 @@ static void prvResetNextTaskUnblockTime( void )
             uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, NULL );
 
             /* Create a human readable table from the binary data. */
-            for( x = 0; x < uxArraySize; x++ )
+            for( x = 0; ( x < uxArraySize ) && ( xOutputBufferFull == pdFALSE ); x++ )
             {
                 switch( pxTaskStatusArray[ x ].eCurrentState )
                 {
@@ -6896,13 +6960,43 @@ static void prvResetNextTaskUnblockTime( void )
                         break;
                 }
 
-                /* Write the task name to the string, padding with spaces so it
-                 * can be printed in tabular form more easily. */
-                pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName );
+                /* Is there enough space in the buffer to hold task name? */
+                if( ( uxConsumedBufferLength + configMAX_TASK_NAME_LEN ) <= uxBufferLength )
+                {
+                    /* Write the task name to the string, padding with spaces so it
+                     * can be printed in tabular form more easily. */
+                    pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName );
+                    /* Do not count the terminating null character. */
+                    uxConsumedBufferLength = uxConsumedBufferLength + ( configMAX_TASK_NAME_LEN - 1 );
 
-                /* Write the rest of the string. */
-                sprintf( pcWriteBuffer, "\t%c\t%u\t%u\t%u\r\n", cStatus, ( unsigned int ) pxTaskStatusArray[ x ].uxCurrentPriority, ( unsigned int ) pxTaskStatusArray[ x ].usStackHighWaterMark, ( unsigned int ) pxTaskStatusArray[ x ].xTaskNumber ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
-                pcWriteBuffer += strlen( pcWriteBuffer );                                                                                                                                                                                                /*lint !e9016 Pointer arithmetic ok on char pointers especially as in this case where it best denotes the intent of the code. */
+                    /* Is there space left in the buffer? -1 is done because snprintf
+                     * writes a terminating null character. So we are essentially
+                     * checking if the buffer has space to write at least one non-null
+                     * character. */
+                    if( uxConsumedBufferLength < ( uxBufferLength - 1 ) )
+                    {
+                        /* Write the rest of the string. */
+                        iSnprintfReturnValue = snprintf( pcWriteBuffer,
+                                                         uxBufferLength - uxConsumedBufferLength,
+                                                         "\t%c\t%u\t%u\t%u\r\n",
+                                                         cStatus,
+                                                         ( unsigned int ) pxTaskStatusArray[ x ].uxCurrentPriority,
+                                                         ( unsigned int ) pxTaskStatusArray[ x ].usStackHighWaterMark,
+                                                         ( unsigned int ) pxTaskStatusArray[ x ].xTaskNumber ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
+                        uxCharsWrittenBySnprintf = prvSnprintfReturnValueToCharsWritten( iSnprintfReturnValue, uxBufferLength - uxConsumedBufferLength );
+
+                        uxConsumedBufferLength += uxCharsWrittenBySnprintf;
+                        pcWriteBuffer += uxCharsWrittenBySnprintf; /*lint !e9016 Pointer arithmetic ok on char pointers especially as in this case where it best denotes the intent of the code. */
+                    }
+                    else
+                    {
+                        xOutputBufferFull = pdTRUE;
+                    }
+                }
+                else
+                {
+                    xOutputBufferFull = pdTRUE;
+                }
             }
 
             /* Free the array again.  NOTE!  If configSUPPORT_DYNAMIC_ALLOCATION
@@ -6914,7 +7008,7 @@ static void prvResetNextTaskUnblockTime( void )
             mtCOVERAGE_TEST_MARKER();
         }
 
-        traceRETURN_vTaskList();
+        traceRETURN_vTaskListTasks();
     }
 
 #endif /* ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) ) */
@@ -6922,13 +7016,18 @@ static void prvResetNextTaskUnblockTime( void )
 
 #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configUSE_TRACE_FACILITY == 1 ) )
 
-    void vTaskGetRunTimeStats( char * pcWriteBuffer )
+    void vTaskGetRunTimeStatistics( char * pcWriteBuffer,
+                                    size_t uxBufferLength )
     {
         TaskStatus_t * pxTaskStatusArray;
+        size_t uxConsumedBufferLength = 0;
+        size_t uxCharsWrittenBySnprintf;
+        int iSnprintfReturnValue;
+        BaseType_t xOutputBufferFull = pdFALSE;
         UBaseType_t uxArraySize, x;
         configRUN_TIME_COUNTER_TYPE ulTotalTime, ulStatsAsPercentage;
 
-        traceENTER_vTaskGetRunTimeStats( pcWriteBuffer );
+        traceENTER_vTaskGetRunTimeStatistics( pcWriteBuffer, uxBufferLength );
 
         /*
          * PLEASE NOTE:
@@ -6937,22 +7036,22 @@ static void prvResetNextTaskUnblockTime( void )
          * of the demo applications.  Do not consider it to be part of the
          * scheduler.
          *
-         * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part
+         * vTaskGetRunTimeStatistics() calls uxTaskGetSystemState(), then formats part
          * of the uxTaskGetSystemState() output into a human readable table that
          * displays the amount of time each task has spent in the Running state
          * in both absolute and percentage terms.
          *
-         * vTaskGetRunTimeStats() has a dependency on the sprintf() C library
+         * vTaskGetRunTimeStatistics() has a dependency on the snprintf() C library
          * function that might bloat the code size, use a lot of stack, and
          * provide different results on different platforms.  An alternative,
          * tiny, third party, and limited functionality implementation of
-         * sprintf() is provided in many of the FreeRTOS/Demo sub-directories in
+         * snprintf() is provided in many of the FreeRTOS/Demo sub-directories in
          * a file called printf-stdarg.c (note printf-stdarg.c does not provide
          * a full snprintf() implementation!).
          *
          * It is recommended that production systems call uxTaskGetSystemState()
          * directly to get access to raw stats data, rather than indirectly
-         * through a call to vTaskGetRunTimeStats().
+         * through a call to vTaskGetRunTimeStatistics().
          */
 
         /* Make sure the write buffer does not contain a string. */
@@ -6979,50 +7078,87 @@ static void prvResetNextTaskUnblockTime( void )
             if( ulTotalTime > 0UL )
             {
                 /* Create a human readable table from the binary data. */
-                for( x = 0; x < uxArraySize; x++ )
+                for( x = 0; ( x < uxArraySize ) && ( xOutputBufferFull == pdFALSE ); x++ )
                 {
                     /* What percentage of the total run time has the task used?
                      * This will always be rounded down to the nearest integer.
                      * ulTotalRunTime has already been divided by 100. */
                     ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalTime;
 
-                    /* Write the task name to the string, padding with
-                     * spaces so it can be printed in tabular form more
-                     * easily. */
-                    pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName );
-
-                    if( ulStatsAsPercentage > 0UL )
+                    /* Is there enough space in the buffer to hold task name? */
+                    if( ( uxConsumedBufferLength + configMAX_TASK_NAME_LEN ) <= uxBufferLength )
                     {
-                        #ifdef portLU_PRINTF_SPECIFIER_REQUIRED
+                        /* Write the task name to the string, padding with
+                         * spaces so it can be printed in tabular form more
+                         * easily. */
+                        pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName );
+                        /* Do not count the terminating null character. */
+                        uxConsumedBufferLength = uxConsumedBufferLength + ( configMAX_TASK_NAME_LEN - 1 );
+
+                        /* Is there space left in the buffer? -1 is done because snprintf
+                         * writes a terminating null character. So we are essentially
+                         * checking if the buffer has space to write at least one non-null
+                         * character. */
+                        if( uxConsumedBufferLength < ( uxBufferLength - 1 ) )
                         {
-                            sprintf( pcWriteBuffer, "\t%lu\t\t%lu%%\r\n", pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage );
+                            if( ulStatsAsPercentage > 0UL )
+                            {
+                                #ifdef portLU_PRINTF_SPECIFIER_REQUIRED
+                                {
+                                    iSnprintfReturnValue = snprintf( pcWriteBuffer,
+                                                                     uxBufferLength - uxConsumedBufferLength,
+                                                                     "\t%lu\t\t%lu%%\r\n",
+                                                                     pxTaskStatusArray[ x ].ulRunTimeCounter,
+                                                                     ulStatsAsPercentage );
+                                }
+                                #else
+                                {
+                                    /* sizeof( int ) == sizeof( long ) so a smaller
+                                     * printf() library can be used. */
+                                    iSnprintfReturnValue = snprintf( pcWriteBuffer,
+                                                                     uxBufferLength - uxConsumedBufferLength,
+                                                                     "\t%u\t\t%u%%\r\n",
+                                                                     ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter,
+                                                                     ( unsigned int ) ulStatsAsPercentage ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
+                                }
+                                #endif /* ifdef portLU_PRINTF_SPECIFIER_REQUIRED */
+                            }
+                            else
+                            {
+                                /* If the percentage is zero here then the task has
+                                 * consumed less than 1% of the total run time. */
+                                #ifdef portLU_PRINTF_SPECIFIER_REQUIRED
+                                {
+                                    iSnprintfReturnValue = snprintf( pcWriteBuffer,
+                                                                     uxBufferLength - uxConsumedBufferLength,
+                                                                     "\t%lu\t\t<1%%\r\n",
+                                                                     pxTaskStatusArray[ x ].ulRunTimeCounter );
+                                }
+                                #else
+                                {
+                                    /* sizeof( int ) == sizeof( long ) so a smaller
+                                     * printf() library can be used. */
+                                    iSnprintfReturnValue = snprintf( pcWriteBuffer,
+                                                                     uxBufferLength - uxConsumedBufferLength,
+                                                                     "\t%u\t\t<1%%\r\n",
+                                                                     ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
+                                }
+                                #endif /* ifdef portLU_PRINTF_SPECIFIER_REQUIRED */
+                            }
+
+                            uxCharsWrittenBySnprintf = prvSnprintfReturnValueToCharsWritten( iSnprintfReturnValue, uxBufferLength - uxConsumedBufferLength );
+                            uxConsumedBufferLength += uxCharsWrittenBySnprintf;
+                            pcWriteBuffer += uxCharsWrittenBySnprintf; /*lint !e9016 Pointer arithmetic ok on char pointers especially as in this case where it best denotes the intent of the code. */
                         }
-                        #else
+                        else
                         {
-                            /* sizeof( int ) == sizeof( long ) so a smaller
-                             * printf() library can be used. */
-                            sprintf( pcWriteBuffer, "\t%u\t\t%u%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter, ( unsigned int ) ulStatsAsPercentage ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
+                            xOutputBufferFull = pdTRUE;
                         }
-                        #endif
                     }
                     else
                     {
-                        /* If the percentage is zero here then the task has
-                         * consumed less than 1% of the total run time. */
-                        #ifdef portLU_PRINTF_SPECIFIER_REQUIRED
-                        {
-                            sprintf( pcWriteBuffer, "\t%lu\t\t<1%%\r\n", pxTaskStatusArray[ x ].ulRunTimeCounter );
-                        }
-                        #else
-                        {
-                            /* sizeof( int ) == sizeof( long ) so a smaller
-                             * printf() library can be used. */
-                            sprintf( pcWriteBuffer, "\t%u\t\t<1%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
-                        }
-                        #endif
+                        xOutputBufferFull = pdTRUE;
                     }
-
-                    pcWriteBuffer += strlen( pcWriteBuffer ); /*lint !e9016 Pointer arithmetic ok on char pointers especially as in this case where it best denotes the intent of the code. */
                 }
             }
             else
@@ -7039,7 +7175,7 @@ static void prvResetNextTaskUnblockTime( void )
             mtCOVERAGE_TEST_MARKER();
         }
 
-        traceRETURN_vTaskGetRunTimeStats();
+        traceRETURN_vTaskGetRunTimeStatistics();
     }
 
 #endif /* ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) ) */

From a695b671aa88a9e61905400f1f28b470d7d306bf Mon Sep 17 00:00:00 2001
From: Soren Ptak <ptaksoren@gmail.com>
Date: Wed, 27 Sep 2023 12:03:41 -0700
Subject: [PATCH 071/424] Apply formatting bot fix (#806)

---
 .github/workflows/formatting.yml | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/.github/workflows/formatting.yml b/.github/workflows/formatting.yml
index 8257addac..04786bad5 100644
--- a/.github/workflows/formatting.yml
+++ b/.github/workflows/formatting.yml
@@ -13,9 +13,9 @@ env:
 jobs:
   Formatting:
     name: Run Formatting Check
-    if: ${{ github.event.issue.pull_request }} &&
+    if: ${{ github.event.issue.pull_request &&
         ( ( github.event.comment.body == '/bot run uncrustify' ) ||
-          ( github.event.comment.body == '/bot run formatting' ) )
+          ( github.event.comment.body == '/bot run formatting' ) ) }}
     runs-on: ubuntu-20.04
     steps:
     - name: Apply Formatting Fix

From 9d2571d2ed30d888c168412d41bcc31e84e12de4 Mon Sep 17 00:00:00 2001
From: Devaraj Ranganna <devaraj.ranganna@arm.com>
Date: Thu, 28 Sep 2023 10:08:55 +0100
Subject: [PATCH 072/424] Cortex-M23: Do not use PSPLIM_NS (#791)

According to Armv8-M technical reference manual, if the main extension
is not implemented then PSPLIM_NS is RES0. Update the cortex-M23
port to not use the reserved PSPLIM_NS.
---
 portable/ARMv8M/non_secure/port.c             | 40 ++++++++++++++++---
 .../portable/GCC/ARM_CM23/portasm.c           | 10 ++---
 .../portable/GCC/ARM_CM23_NTZ/portasm.c       | 28 ++++++++++---
 .../portable/IAR/ARM_CM23/portasm.s           | 11 ++---
 .../portable/IAR/ARM_CM23_NTZ/portasm.s       | 20 ++++++++++
 portable/GCC/ARM_CM23/non_secure/port.c       | 40 ++++++++++++++++---
 portable/GCC/ARM_CM23/non_secure/portasm.c    | 10 ++---
 portable/GCC/ARM_CM23_NTZ/non_secure/port.c   | 40 ++++++++++++++++---
 .../GCC/ARM_CM23_NTZ/non_secure/portasm.c     | 28 ++++++++++---
 portable/GCC/ARM_CM33/non_secure/port.c       | 40 ++++++++++++++++---
 portable/GCC/ARM_CM33_NTZ/non_secure/port.c   | 40 ++++++++++++++++---
 portable/GCC/ARM_CM35P/non_secure/port.c      | 40 ++++++++++++++++---
 portable/GCC/ARM_CM35P_NTZ/non_secure/port.c  | 40 ++++++++++++++++---
 portable/GCC/ARM_CM55/non_secure/port.c       | 40 ++++++++++++++++---
 portable/GCC/ARM_CM55_NTZ/non_secure/port.c   | 40 ++++++++++++++++---
 portable/GCC/ARM_CM85/non_secure/port.c       | 40 ++++++++++++++++---
 portable/GCC/ARM_CM85_NTZ/non_secure/port.c   | 40 ++++++++++++++++---
 portable/IAR/ARM_CM23/non_secure/port.c       | 40 ++++++++++++++++---
 portable/IAR/ARM_CM23/non_secure/portasm.s    | 11 ++---
 portable/IAR/ARM_CM23_NTZ/non_secure/port.c   | 40 ++++++++++++++++---
 .../IAR/ARM_CM23_NTZ/non_secure/portasm.s     | 20 ++++++++++
 portable/IAR/ARM_CM33/non_secure/port.c       | 40 ++++++++++++++++---
 portable/IAR/ARM_CM33_NTZ/non_secure/port.c   | 40 ++++++++++++++++---
 portable/IAR/ARM_CM35P/non_secure/port.c      | 40 ++++++++++++++++---
 portable/IAR/ARM_CM35P_NTZ/non_secure/port.c  | 40 ++++++++++++++++---
 portable/IAR/ARM_CM55/non_secure/port.c       | 40 ++++++++++++++++---
 portable/IAR/ARM_CM55_NTZ/non_secure/port.c   | 40 ++++++++++++++++---
 portable/IAR/ARM_CM85/non_secure/port.c       | 40 ++++++++++++++++---
 portable/IAR/ARM_CM85_NTZ/non_secure/port.c   | 40 ++++++++++++++++---
 29 files changed, 833 insertions(+), 145 deletions(-)

diff --git a/portable/ARMv8M/non_secure/port.c b/portable/ARMv8M/non_secure/port.c
index 0ba29f9b4..0c5b76488 100644
--- a/portable/ARMv8M/non_secure/port.c
+++ b/portable/ARMv8M/non_secure/port.c
@@ -67,6 +67,16 @@
 #if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
     #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
 #endif
+
+/**
+ * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23
+ * only when FreeRTOS runs on secure side.
+ */
+#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) )
+    #define portUSE_PSPLIM_REGISTER    0
+#else
+    #define portUSE_PSPLIM_REGISTER    1
+#endif
 /*-----------------------------------------------------------*/
 
 /**
@@ -1185,11 +1195,19 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
              * restore it when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* Use the pulSystemCallStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            }
+            #endif
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
@@ -1316,11 +1334,19 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Store the value of the LR and PSPLIM registers before the SVC was raised.
              * We need to restore it when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* Use the pulSystemCallStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            }
+            #endif
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
@@ -1415,7 +1441,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Restore the LR and PSPLIM to what they were at the time of
              * system call entry. */
             pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* If the hardware used padding to force the stack pointer
              * to be double word aligned, set the stacked xPSR bit[9],
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portasm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portasm.c
index d452c33b0..1b41d587f 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portasm.c
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portasm.c
@@ -109,7 +109,6 @@
             "    ldmia r2!, {r0, r3-r6}                       \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, r6 = LR. */
             "    subs r2, #20                                 \n"
             "    msr psp, r3                                  \n"
-            "    msr psplim, r4                               \n"
             "    msr control, r5                              \n"
             "    mov lr, r6                                   \n"
             "    ldr r4, xSecureContextConst2                 \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
@@ -160,7 +159,6 @@
             "   ldm  r0!, {r1-r3}                               \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
             "   ldr  r4, xSecureContextConst2                   \n"
             "   str  r1, [r4]                                   \n" /* Set xSecureContext to this task's value for the same. */
-            "   msr  psplim, r2                                 \n" /* Set this task's PSPLIM value. */
             "   movs r1, #2                                     \n" /* r1 = 2. */
             "   msr  CONTROL, r1                                \n" /* Switch to use PSP in the thread mode. */
             "   adds r0, #32                                    \n" /* Discard everything up to r0. */
@@ -324,7 +322,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "                                                 \n"
             " save_special_regs:                              \n"
             "    mrs r3, psp                                  \n" /* r3 = PSP. */
-            "    mrs r4, psplim                               \n" /* r4 = PSPLIM. */
+            "    movs r4, #0                                  \n" /* r4 = 0. 0 is stored in the PSPLIM slot. */
             "    mrs r5, control                              \n" /* r5 = CONTROL. */
             "    mov r6, lr                                   \n" /* r6 = LR. */
             "    stmia r2!, {r0, r3-r6}                       \n" /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
@@ -392,7 +390,6 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    ldmia r2!, {r0, r3-r6}                       \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, r6 = LR. */
             "    subs r2, #20                                 \n"
             "    msr psp, r3                                  \n"
-            "    msr psplim, r4                               \n"
             "    msr control, r5                              \n"
             "    mov lr, r6                                   \n"
             "    ldr r4, xSecureContextConst                  \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
@@ -467,7 +464,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
             "   subs r2, r2, #12                                \n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */
             "   str r2, [r1]                                    \n" /* Save the new top of stack in TCB. */
-            "   mrs r1, psplim                                  \n" /* r1 = PSPLIM. */
+            "   movs r1, #0                                     \n" /* r1 = 0. 0 is stored in the PSPLIM slot. */
             "   mov r3, lr                                      \n" /* r3 = LR/EXC_RETURN. */
             "   stmia r2!, {r0, r1, r3}                         \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
             "   b select_next_task                              \n"
@@ -477,7 +474,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
             "   subs r2, r2, #44                                \n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
             "   str r2, [r1]                                    \n" /* Save the new top of stack in TCB. */
-            "   mrs r1, psplim                                  \n" /* r1 = PSPLIM. */
+            "   movs r1, #0                                     \n" /* r1 = 0. 0 is stored in the PSPLIM slot. */
             "   mov r3, lr                                      \n" /* r3 = LR/EXC_RETURN. */
             "   stmia r2!, {r0, r1, r3-r7}                      \n" /* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */
             "   mov r4, r8                                      \n" /* r4 = r8. */
@@ -496,7 +493,6 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   ldr r2, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
             "                                                   \n"
             "   ldmia r2!, {r0, r1, r4}                         \n" /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
-            "   msr psplim, r1                                  \n" /* Restore the PSPLIM register value for the task. */
             "   mov lr, r4                                      \n" /* LR = r4. */
             "   ldr r3, xSecureContextConst                     \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
             "   str r0, [r3]                                    \n" /* Restore the task's xSecureContext. */
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portasm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portasm.c
index c1d3b4618..ed4933812 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portasm.c
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portasm.c
@@ -109,7 +109,9 @@
             "    ldmia r1!, {r2-r5}                           \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, r5 = LR. */
             "    subs r1, #16                                 \n"
             "    msr psp, r2                                  \n"
-            "    msr psplim, r3                               \n"
+            #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
+                "    msr psplim, r3                           \n"
+            #endif
             "    msr control, r4                              \n"
             "    mov lr, r5                                   \n"
             "                                                 \n"
@@ -155,7 +157,9 @@
             "   ldr  r0, [r1]                                   \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
             "                                                   \n"
             "   ldm  r0!, {r1-r2}                               \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
-            "   msr  psplim, r1                                 \n" /* Set this task's PSPLIM value. */
+            #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
+                "   msr  psplim, r1                             \n" /* Set this task's PSPLIM value. */
+            #endif
             "   movs r1, #2                                     \n" /* r1 = 2. */
             "   msr  CONTROL, r1                                \n" /* Switch to use PSP in the thread mode. */
             "   adds r0, #32                                    \n" /* Discard everything up to r0. */
@@ -302,7 +306,11 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "                                                 \n"
             " save_special_regs:                              \n"
             "    mrs r2, psp                                  \n" /* r2 = PSP. */
-            "    mrs r3, psplim                               \n" /* r3 = PSPLIM. */
+            #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
+                "    mrs r3, psplim                           \n" /* r3 = PSPLIM. */
+            #else
+                "    movs r3, #0                              \n" /* r3 = 0. 0 is stored in the PSPLIM slot. */
+            #endif
             "    mrs r4, control                              \n" /* r4 = CONTROL. */
             "    mov r5, lr                                   \n" /* r5 = LR. */
             "    stmia r1!, {r2-r5}                           \n" /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
@@ -370,7 +378,9 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    ldmia r1!, {r2-r5}                           \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, r5 = LR. */
             "    subs r1, #16                                 \n"
             "    msr psp, r2                                  \n"
-            "    msr psplim, r3                               \n"
+            #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
+                "    msr psplim, r3                           \n"
+            #endif
             "    msr control, r4                              \n"
             "    mov lr, r5                                   \n"
             "                                                 \n"
@@ -416,7 +426,11 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   ldr r1, [r2]                                    \n" /* Read pxCurrentTCB. */
             "   subs r0, r0, #40                                \n" /* Make space for PSPLIM, LR and the remaining registers on the stack. */
             "   str r0, [r1]                                    \n" /* Save the new top of stack in TCB. */
-            "   mrs r2, psplim                                  \n" /* r2 = PSPLIM. */
+            #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
+                "   mrs r2, psplim                              \n" /* r2 = PSPLIM. */
+            #else
+                "   movs r2, #0                                 \n" /* r2 = 0. 0 is stored in the PSPLIM slot. */
+            #endif
             "   mov r3, lr                                      \n" /* r3 = LR/EXC_RETURN. */
             "   stmia r0!, {r2-r7}                              \n" /* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */
             "   mov r4, r8                                      \n" /* r4 = r8. */
@@ -442,7 +456,9 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   msr psp, r0                                     \n" /* Remember the new top of stack for the task. */
             "   subs r0, r0, #40                                \n" /* Move to the starting of the saved context. */
             "   ldmia r0!, {r2-r7}                              \n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */
-            "   msr psplim, r2                                  \n" /* Restore the PSPLIM register value for the task. */
+            #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
+                "   msr psplim, r2                              \n" /* Restore the PSPLIM register value for the task. */
+            #endif
             "   bx r3                                           \n"
             "                                                   \n"
             "   .align 4                                        \n"
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portasm.s b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portasm.s
index 648ae0050..8c7000909 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portasm.s
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portasm.s
@@ -37,6 +37,7 @@ files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler.
     #define configUSE_MPU_WRAPPERS_V1 0
 #endif
 
+
     EXTERN pxCurrentTCB
     EXTERN xSecureContext
     EXTERN vTaskSwitchContext
@@ -167,7 +168,6 @@ vRestoreContextOfFirstTask:
         ldmia r2!, {r0, r3-r6}              /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, r6 = LR. */
         subs r2, #20
         msr psp, r3
-        msr psplim, r4
         msr control, r5
         mov lr, r6
         ldr r4, =xSecureContext             /* Read the location of xSecureContext i.e. &( xSecureContext ). */
@@ -203,7 +203,6 @@ vRestoreContextOfFirstTask:
     ldm  r0!, {r1-r3}                       /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
     ldr  r4, =xSecureContext
     str  r1, [r4]                           /* Set xSecureContext to this task's value for the same. */
-    msr  psplim, r2                         /* Set this task's PSPLIM value. */
     movs r1, #2                             /* r1 = 2. */
     msr  CONTROL, r1                        /* Switch to use PSP in the thread mode. */
     adds r0, #32                            /* Discard everything up to r0. */
@@ -279,7 +278,7 @@ PendSV_Handler:
 
     save_special_regs:
         mrs r3, psp                         /* r3 = PSP. */
-        mrs r4, psplim                      /* r4 = PSPLIM. */
+        movs r4, #0                         /* r4 = 0. 0 is stored in the PSPLIM slot. */
         mrs r5, control                     /* r5 = CONTROL. */
         mov r6, lr                          /* r6 = LR. */
         stmia r2!, {r0, r3-r6}              /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
@@ -347,7 +346,6 @@ PendSV_Handler:
         ldmia r2!, {r0, r3-r6}              /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, r6 = LR. */
         subs r2, #20
         msr psp, r3
-        msr psplim, r4
         msr control, r5
         mov lr, r6
         ldr r4, =xSecureContext             /* Read the location of xSecureContext i.e. &( xSecureContext ). */
@@ -406,7 +404,7 @@ PendSV_Handler:
 
     subs r2, r2, #12                        /* Make space for xSecureContext, PSPLIM and LR on the stack. */
     str r2, [r1]                            /* Save the new top of stack in TCB. */
-    mrs r1, psplim                          /* r1 = PSPLIM. */
+    movs r1, #0                             /* r1 = 0. 0 is stored in the PSPLIM slot. */
     mov r3, lr                              /* r3 = LR/EXC_RETURN. */
     stmia r2!, {r0, r1, r3}                 /* Store xSecureContext, PSPLIM and LR on the stack. */
 
@@ -417,7 +415,7 @@ PendSV_Handler:
         ldr r1, [r3]                        /* Read pxCurrentTCB. */
         subs r2, r2, #44                    /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
         str r2, [r1]                        /* Save the new top of stack in TCB. */
-        mrs r1, psplim                      /* r1 = PSPLIM. */
+        movs r1, #0                         /* r1 = 0. 0 is stored in the PSPLIM slot. */
         mov r3, lr                          /* r3 = LR/EXC_RETURN. */
         stmia r2!, {r0, r1, r3-r7}          /* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */
         mov r4, r8                          /* r4 = r8. */
@@ -436,7 +434,6 @@ PendSV_Handler:
         ldr r2, [r1]                        /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
 
         ldmia r2!, {r0, r1, r4}             /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
-        msr psplim, r1                      /* Restore the PSPLIM register value for the task. */
         mov lr, r4                          /* LR = r4. */
         ldr r3, =xSecureContext             /* Read the location of xSecureContext i.e. &( xSecureContext ). */
         str r0, [r3]                        /* Restore the task's xSecureContext. */
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portasm.s b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portasm.s
index 8f77c4daf..836a927c8 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portasm.s
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portasm.s
@@ -36,6 +36,10 @@ files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler.
     #define configUSE_MPU_WRAPPERS_V1 0
 #endif
 
+#ifndef configRUN_FREERTOS_SECURE_ONLY
+    #define configRUN_FREERTOS_SECURE_ONLY 0
+#endif
+
     EXTERN pxCurrentTCB
     EXTERN vTaskSwitchContext
     EXTERN vPortSVCHandler_C
@@ -157,7 +161,9 @@ vRestoreContextOfFirstTask:
         ldmia r1!, {r2-r5}                  /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, r5 = LR. */
         subs r1, #16
         msr psp, r2
+    #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
         msr psplim, r3
+    #endif
         msr control, r4
         mov lr, r5
 
@@ -189,7 +195,9 @@ vRestoreContextOfFirstTask:
     ldr  r0, [r1]                           /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
 
     ldm  r0!, {r1-r2}                       /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
+#if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
     msr  psplim, r1                         /* Set this task's PSPLIM value. */
+#endif
     movs r1, #2                             /* r1 = 2. */
     msr  CONTROL, r1                        /* Switch to use PSP in the thread mode. */
     adds r0, #32                            /* Discard everything up to r0. */
@@ -253,7 +261,11 @@ PendSV_Handler:
 
     save_special_regs:
         mrs r2, psp                         /* r2 = PSP. */
+    #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
         mrs r3, psplim                      /* r3 = PSPLIM. */
+    #else
+        movs r3, #0                         /* r3 = 0. 0 is stored in the PSPLIM slot. */
+    #endif
         mrs r4, control                     /* r4 = CONTROL. */
         mov r5, lr                          /* r5 = LR. */
         stmia r1!, {r2-r5}                  /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
@@ -321,7 +333,9 @@ PendSV_Handler:
         ldmia r1!, {r2-r5}                  /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, r5 = LR. */
         subs r1, #16
         msr psp, r2
+    #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
         msr psplim, r3
+    #endif
         msr control, r4
         mov lr, r5
 
@@ -354,7 +368,11 @@ PendSV_Handler:
 
     subs r0, r0, #40                        /* Make space for PSPLIM, LR and the remaining registers on the stack. */
     str r0, [r1]                            /* Save the new top of stack in TCB. */
+#if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
     mrs r2, psplim                          /* r2 = PSPLIM. */
+#else
+    movs r2, #0                             /* r0 = 0. 0 is stored in the PSPLIM slot. */
+#endif
     mov r3, lr                              /* r3 = LR/EXC_RETURN. */
     stmia r0!, {r2-r7}                      /* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */
     mov r4, r8                              /* r4 = r8. */
@@ -380,7 +398,9 @@ PendSV_Handler:
     msr psp, r0                             /* Remember the new top of stack for the task. */
     subs r0, r0, #40                        /* Move to the starting of the saved context. */
     ldmia r0!, {r2-r7}                      /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */
+#if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
     msr psplim, r2                          /* Restore the PSPLIM register value for the task. */
+#endif
     bx r3
 
 #endif /* configENABLE_MPU */
diff --git a/portable/GCC/ARM_CM23/non_secure/port.c b/portable/GCC/ARM_CM23/non_secure/port.c
index 0ba29f9b4..0c5b76488 100644
--- a/portable/GCC/ARM_CM23/non_secure/port.c
+++ b/portable/GCC/ARM_CM23/non_secure/port.c
@@ -67,6 +67,16 @@
 #if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
     #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
 #endif
+
+/**
+ * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23
+ * only when FreeRTOS runs on secure side.
+ */
+#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) )
+    #define portUSE_PSPLIM_REGISTER    0
+#else
+    #define portUSE_PSPLIM_REGISTER    1
+#endif
 /*-----------------------------------------------------------*/
 
 /**
@@ -1185,11 +1195,19 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
              * restore it when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* Use the pulSystemCallStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            }
+            #endif
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
@@ -1316,11 +1334,19 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Store the value of the LR and PSPLIM registers before the SVC was raised.
              * We need to restore it when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* Use the pulSystemCallStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            }
+            #endif
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
@@ -1415,7 +1441,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Restore the LR and PSPLIM to what they were at the time of
              * system call entry. */
             pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* If the hardware used padding to force the stack pointer
              * to be double word aligned, set the stacked xPSR bit[9],
diff --git a/portable/GCC/ARM_CM23/non_secure/portasm.c b/portable/GCC/ARM_CM23/non_secure/portasm.c
index d452c33b0..1b41d587f 100644
--- a/portable/GCC/ARM_CM23/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM23/non_secure/portasm.c
@@ -109,7 +109,6 @@
             "    ldmia r2!, {r0, r3-r6}                       \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, r6 = LR. */
             "    subs r2, #20                                 \n"
             "    msr psp, r3                                  \n"
-            "    msr psplim, r4                               \n"
             "    msr control, r5                              \n"
             "    mov lr, r6                                   \n"
             "    ldr r4, xSecureContextConst2                 \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
@@ -160,7 +159,6 @@
             "   ldm  r0!, {r1-r3}                               \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
             "   ldr  r4, xSecureContextConst2                   \n"
             "   str  r1, [r4]                                   \n" /* Set xSecureContext to this task's value for the same. */
-            "   msr  psplim, r2                                 \n" /* Set this task's PSPLIM value. */
             "   movs r1, #2                                     \n" /* r1 = 2. */
             "   msr  CONTROL, r1                                \n" /* Switch to use PSP in the thread mode. */
             "   adds r0, #32                                    \n" /* Discard everything up to r0. */
@@ -324,7 +322,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "                                                 \n"
             " save_special_regs:                              \n"
             "    mrs r3, psp                                  \n" /* r3 = PSP. */
-            "    mrs r4, psplim                               \n" /* r4 = PSPLIM. */
+            "    movs r4, #0                                  \n" /* r4 = 0. 0 is stored in the PSPLIM slot. */
             "    mrs r5, control                              \n" /* r5 = CONTROL. */
             "    mov r6, lr                                   \n" /* r6 = LR. */
             "    stmia r2!, {r0, r3-r6}                       \n" /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
@@ -392,7 +390,6 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    ldmia r2!, {r0, r3-r6}                       \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, r6 = LR. */
             "    subs r2, #20                                 \n"
             "    msr psp, r3                                  \n"
-            "    msr psplim, r4                               \n"
             "    msr control, r5                              \n"
             "    mov lr, r6                                   \n"
             "    ldr r4, xSecureContextConst                  \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
@@ -467,7 +464,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
             "   subs r2, r2, #12                                \n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */
             "   str r2, [r1]                                    \n" /* Save the new top of stack in TCB. */
-            "   mrs r1, psplim                                  \n" /* r1 = PSPLIM. */
+            "   movs r1, #0                                     \n" /* r1 = 0. 0 is stored in the PSPLIM slot. */
             "   mov r3, lr                                      \n" /* r3 = LR/EXC_RETURN. */
             "   stmia r2!, {r0, r1, r3}                         \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
             "   b select_next_task                              \n"
@@ -477,7 +474,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
             "   subs r2, r2, #44                                \n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
             "   str r2, [r1]                                    \n" /* Save the new top of stack in TCB. */
-            "   mrs r1, psplim                                  \n" /* r1 = PSPLIM. */
+            "   movs r1, #0                                     \n" /* r1 = 0. 0 is stored in the PSPLIM slot. */
             "   mov r3, lr                                      \n" /* r3 = LR/EXC_RETURN. */
             "   stmia r2!, {r0, r1, r3-r7}                      \n" /* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */
             "   mov r4, r8                                      \n" /* r4 = r8. */
@@ -496,7 +493,6 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   ldr r2, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
             "                                                   \n"
             "   ldmia r2!, {r0, r1, r4}                         \n" /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
-            "   msr psplim, r1                                  \n" /* Restore the PSPLIM register value for the task. */
             "   mov lr, r4                                      \n" /* LR = r4. */
             "   ldr r3, xSecureContextConst                     \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
             "   str r0, [r3]                                    \n" /* Restore the task's xSecureContext. */
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
index 0ba29f9b4..0c5b76488 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
@@ -67,6 +67,16 @@
 #if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
     #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
 #endif
+
+/**
+ * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23
+ * only when FreeRTOS runs on secure side.
+ */
+#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) )
+    #define portUSE_PSPLIM_REGISTER    0
+#else
+    #define portUSE_PSPLIM_REGISTER    1
+#endif
 /*-----------------------------------------------------------*/
 
 /**
@@ -1185,11 +1195,19 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
              * restore it when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* Use the pulSystemCallStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            }
+            #endif
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
@@ -1316,11 +1334,19 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Store the value of the LR and PSPLIM registers before the SVC was raised.
              * We need to restore it when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* Use the pulSystemCallStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            }
+            #endif
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
@@ -1415,7 +1441,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Restore the LR and PSPLIM to what they were at the time of
              * system call entry. */
             pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* If the hardware used padding to force the stack pointer
              * to be double word aligned, set the stacked xPSR bit[9],
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c b/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c
index c1d3b4618..ed4933812 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c
@@ -109,7 +109,9 @@
             "    ldmia r1!, {r2-r5}                           \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, r5 = LR. */
             "    subs r1, #16                                 \n"
             "    msr psp, r2                                  \n"
-            "    msr psplim, r3                               \n"
+            #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
+                "    msr psplim, r3                           \n"
+            #endif
             "    msr control, r4                              \n"
             "    mov lr, r5                                   \n"
             "                                                 \n"
@@ -155,7 +157,9 @@
             "   ldr  r0, [r1]                                   \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
             "                                                   \n"
             "   ldm  r0!, {r1-r2}                               \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
-            "   msr  psplim, r1                                 \n" /* Set this task's PSPLIM value. */
+            #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
+                "   msr  psplim, r1                             \n" /* Set this task's PSPLIM value. */
+            #endif
             "   movs r1, #2                                     \n" /* r1 = 2. */
             "   msr  CONTROL, r1                                \n" /* Switch to use PSP in the thread mode. */
             "   adds r0, #32                                    \n" /* Discard everything up to r0. */
@@ -302,7 +306,11 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "                                                 \n"
             " save_special_regs:                              \n"
             "    mrs r2, psp                                  \n" /* r2 = PSP. */
-            "    mrs r3, psplim                               \n" /* r3 = PSPLIM. */
+            #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
+                "    mrs r3, psplim                           \n" /* r3 = PSPLIM. */
+            #else
+                "    movs r3, #0                              \n" /* r3 = 0. 0 is stored in the PSPLIM slot. */
+            #endif
             "    mrs r4, control                              \n" /* r4 = CONTROL. */
             "    mov r5, lr                                   \n" /* r5 = LR. */
             "    stmia r1!, {r2-r5}                           \n" /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
@@ -370,7 +378,9 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    ldmia r1!, {r2-r5}                           \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, r5 = LR. */
             "    subs r1, #16                                 \n"
             "    msr psp, r2                                  \n"
-            "    msr psplim, r3                               \n"
+            #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
+                "    msr psplim, r3                           \n"
+            #endif
             "    msr control, r4                              \n"
             "    mov lr, r5                                   \n"
             "                                                 \n"
@@ -416,7 +426,11 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   ldr r1, [r2]                                    \n" /* Read pxCurrentTCB. */
             "   subs r0, r0, #40                                \n" /* Make space for PSPLIM, LR and the remaining registers on the stack. */
             "   str r0, [r1]                                    \n" /* Save the new top of stack in TCB. */
-            "   mrs r2, psplim                                  \n" /* r2 = PSPLIM. */
+            #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
+                "   mrs r2, psplim                              \n" /* r2 = PSPLIM. */
+            #else
+                "   movs r2, #0                                 \n" /* r2 = 0. 0 is stored in the PSPLIM slot. */
+            #endif
             "   mov r3, lr                                      \n" /* r3 = LR/EXC_RETURN. */
             "   stmia r0!, {r2-r7}                              \n" /* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */
             "   mov r4, r8                                      \n" /* r4 = r8. */
@@ -442,7 +456,9 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   msr psp, r0                                     \n" /* Remember the new top of stack for the task. */
             "   subs r0, r0, #40                                \n" /* Move to the starting of the saved context. */
             "   ldmia r0!, {r2-r7}                              \n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */
-            "   msr psplim, r2                                  \n" /* Restore the PSPLIM register value for the task. */
+            #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
+                "   msr psplim, r2                              \n" /* Restore the PSPLIM register value for the task. */
+            #endif
             "   bx r3                                           \n"
             "                                                   \n"
             "   .align 4                                        \n"
diff --git a/portable/GCC/ARM_CM33/non_secure/port.c b/portable/GCC/ARM_CM33/non_secure/port.c
index 0ba29f9b4..0c5b76488 100644
--- a/portable/GCC/ARM_CM33/non_secure/port.c
+++ b/portable/GCC/ARM_CM33/non_secure/port.c
@@ -67,6 +67,16 @@
 #if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
     #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
 #endif
+
+/**
+ * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23
+ * only when FreeRTOS runs on secure side.
+ */
+#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) )
+    #define portUSE_PSPLIM_REGISTER    0
+#else
+    #define portUSE_PSPLIM_REGISTER    1
+#endif
 /*-----------------------------------------------------------*/
 
 /**
@@ -1185,11 +1195,19 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
              * restore it when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* Use the pulSystemCallStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            }
+            #endif
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
@@ -1316,11 +1334,19 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Store the value of the LR and PSPLIM registers before the SVC was raised.
              * We need to restore it when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* Use the pulSystemCallStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            }
+            #endif
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
@@ -1415,7 +1441,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Restore the LR and PSPLIM to what they were at the time of
              * system call entry. */
             pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* If the hardware used padding to force the stack pointer
              * to be double word aligned, set the stacked xPSR bit[9],
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
index 0ba29f9b4..0c5b76488 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
@@ -67,6 +67,16 @@
 #if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
     #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
 #endif
+
+/**
+ * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23
+ * only when FreeRTOS runs on secure side.
+ */
+#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) )
+    #define portUSE_PSPLIM_REGISTER    0
+#else
+    #define portUSE_PSPLIM_REGISTER    1
+#endif
 /*-----------------------------------------------------------*/
 
 /**
@@ -1185,11 +1195,19 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
              * restore it when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* Use the pulSystemCallStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            }
+            #endif
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
@@ -1316,11 +1334,19 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Store the value of the LR and PSPLIM registers before the SVC was raised.
              * We need to restore it when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* Use the pulSystemCallStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            }
+            #endif
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
@@ -1415,7 +1441,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Restore the LR and PSPLIM to what they were at the time of
              * system call entry. */
             pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* If the hardware used padding to force the stack pointer
              * to be double word aligned, set the stacked xPSR bit[9],
diff --git a/portable/GCC/ARM_CM35P/non_secure/port.c b/portable/GCC/ARM_CM35P/non_secure/port.c
index 0ba29f9b4..0c5b76488 100644
--- a/portable/GCC/ARM_CM35P/non_secure/port.c
+++ b/portable/GCC/ARM_CM35P/non_secure/port.c
@@ -67,6 +67,16 @@
 #if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
     #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
 #endif
+
+/**
+ * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23
+ * only when FreeRTOS runs on secure side.
+ */
+#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) )
+    #define portUSE_PSPLIM_REGISTER    0
+#else
+    #define portUSE_PSPLIM_REGISTER    1
+#endif
 /*-----------------------------------------------------------*/
 
 /**
@@ -1185,11 +1195,19 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
              * restore it when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* Use the pulSystemCallStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            }
+            #endif
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
@@ -1316,11 +1334,19 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Store the value of the LR and PSPLIM registers before the SVC was raised.
              * We need to restore it when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* Use the pulSystemCallStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            }
+            #endif
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
@@ -1415,7 +1441,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Restore the LR and PSPLIM to what they were at the time of
              * system call entry. */
             pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* If the hardware used padding to force the stack pointer
              * to be double word aligned, set the stacked xPSR bit[9],
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c b/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
index 0ba29f9b4..0c5b76488 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
@@ -67,6 +67,16 @@
 #if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
     #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
 #endif
+
+/**
+ * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23
+ * only when FreeRTOS runs on secure side.
+ */
+#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) )
+    #define portUSE_PSPLIM_REGISTER    0
+#else
+    #define portUSE_PSPLIM_REGISTER    1
+#endif
 /*-----------------------------------------------------------*/
 
 /**
@@ -1185,11 +1195,19 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
              * restore it when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* Use the pulSystemCallStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            }
+            #endif
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
@@ -1316,11 +1334,19 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Store the value of the LR and PSPLIM registers before the SVC was raised.
              * We need to restore it when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* Use the pulSystemCallStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            }
+            #endif
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
@@ -1415,7 +1441,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Restore the LR and PSPLIM to what they were at the time of
              * system call entry. */
             pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* If the hardware used padding to force the stack pointer
              * to be double word aligned, set the stacked xPSR bit[9],
diff --git a/portable/GCC/ARM_CM55/non_secure/port.c b/portable/GCC/ARM_CM55/non_secure/port.c
index 0ba29f9b4..0c5b76488 100644
--- a/portable/GCC/ARM_CM55/non_secure/port.c
+++ b/portable/GCC/ARM_CM55/non_secure/port.c
@@ -67,6 +67,16 @@
 #if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
     #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
 #endif
+
+/**
+ * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23
+ * only when FreeRTOS runs on secure side.
+ */
+#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) )
+    #define portUSE_PSPLIM_REGISTER    0
+#else
+    #define portUSE_PSPLIM_REGISTER    1
+#endif
 /*-----------------------------------------------------------*/
 
 /**
@@ -1185,11 +1195,19 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
              * restore it when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* Use the pulSystemCallStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            }
+            #endif
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
@@ -1316,11 +1334,19 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Store the value of the LR and PSPLIM registers before the SVC was raised.
              * We need to restore it when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* Use the pulSystemCallStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            }
+            #endif
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
@@ -1415,7 +1441,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Restore the LR and PSPLIM to what they were at the time of
              * system call entry. */
             pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* If the hardware used padding to force the stack pointer
              * to be double word aligned, set the stacked xPSR bit[9],
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/port.c b/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
index 0ba29f9b4..0c5b76488 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
@@ -67,6 +67,16 @@
 #if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
     #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
 #endif
+
+/**
+ * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23
+ * only when FreeRTOS runs on secure side.
+ */
+#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) )
+    #define portUSE_PSPLIM_REGISTER    0
+#else
+    #define portUSE_PSPLIM_REGISTER    1
+#endif
 /*-----------------------------------------------------------*/
 
 /**
@@ -1185,11 +1195,19 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
              * restore it when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* Use the pulSystemCallStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            }
+            #endif
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
@@ -1316,11 +1334,19 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Store the value of the LR and PSPLIM registers before the SVC was raised.
              * We need to restore it when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* Use the pulSystemCallStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            }
+            #endif
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
@@ -1415,7 +1441,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Restore the LR and PSPLIM to what they were at the time of
              * system call entry. */
             pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* If the hardware used padding to force the stack pointer
              * to be double word aligned, set the stacked xPSR bit[9],
diff --git a/portable/GCC/ARM_CM85/non_secure/port.c b/portable/GCC/ARM_CM85/non_secure/port.c
index 0ba29f9b4..0c5b76488 100644
--- a/portable/GCC/ARM_CM85/non_secure/port.c
+++ b/portable/GCC/ARM_CM85/non_secure/port.c
@@ -67,6 +67,16 @@
 #if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
     #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
 #endif
+
+/**
+ * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23
+ * only when FreeRTOS runs on secure side.
+ */
+#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) )
+    #define portUSE_PSPLIM_REGISTER    0
+#else
+    #define portUSE_PSPLIM_REGISTER    1
+#endif
 /*-----------------------------------------------------------*/
 
 /**
@@ -1185,11 +1195,19 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
              * restore it when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* Use the pulSystemCallStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            }
+            #endif
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
@@ -1316,11 +1334,19 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Store the value of the LR and PSPLIM registers before the SVC was raised.
              * We need to restore it when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* Use the pulSystemCallStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            }
+            #endif
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
@@ -1415,7 +1441,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Restore the LR and PSPLIM to what they were at the time of
              * system call entry. */
             pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* If the hardware used padding to force the stack pointer
              * to be double word aligned, set the stacked xPSR bit[9],
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/port.c b/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
index 0ba29f9b4..0c5b76488 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
@@ -67,6 +67,16 @@
 #if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
     #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
 #endif
+
+/**
+ * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23
+ * only when FreeRTOS runs on secure side.
+ */
+#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) )
+    #define portUSE_PSPLIM_REGISTER    0
+#else
+    #define portUSE_PSPLIM_REGISTER    1
+#endif
 /*-----------------------------------------------------------*/
 
 /**
@@ -1185,11 +1195,19 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
              * restore it when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* Use the pulSystemCallStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            }
+            #endif
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
@@ -1316,11 +1334,19 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Store the value of the LR and PSPLIM registers before the SVC was raised.
              * We need to restore it when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* Use the pulSystemCallStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            }
+            #endif
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
@@ -1415,7 +1441,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Restore the LR and PSPLIM to what they were at the time of
              * system call entry. */
             pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* If the hardware used padding to force the stack pointer
              * to be double word aligned, set the stacked xPSR bit[9],
diff --git a/portable/IAR/ARM_CM23/non_secure/port.c b/portable/IAR/ARM_CM23/non_secure/port.c
index 0ba29f9b4..0c5b76488 100644
--- a/portable/IAR/ARM_CM23/non_secure/port.c
+++ b/portable/IAR/ARM_CM23/non_secure/port.c
@@ -67,6 +67,16 @@
 #if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
     #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
 #endif
+
+/**
+ * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23
+ * only when FreeRTOS runs on secure side.
+ */
+#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) )
+    #define portUSE_PSPLIM_REGISTER    0
+#else
+    #define portUSE_PSPLIM_REGISTER    1
+#endif
 /*-----------------------------------------------------------*/
 
 /**
@@ -1185,11 +1195,19 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
              * restore it when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* Use the pulSystemCallStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            }
+            #endif
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
@@ -1316,11 +1334,19 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Store the value of the LR and PSPLIM registers before the SVC was raised.
              * We need to restore it when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* Use the pulSystemCallStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            }
+            #endif
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
@@ -1415,7 +1441,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Restore the LR and PSPLIM to what they were at the time of
              * system call entry. */
             pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* If the hardware used padding to force the stack pointer
              * to be double word aligned, set the stacked xPSR bit[9],
diff --git a/portable/IAR/ARM_CM23/non_secure/portasm.s b/portable/IAR/ARM_CM23/non_secure/portasm.s
index 648ae0050..8c7000909 100644
--- a/portable/IAR/ARM_CM23/non_secure/portasm.s
+++ b/portable/IAR/ARM_CM23/non_secure/portasm.s
@@ -37,6 +37,7 @@ files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler.
     #define configUSE_MPU_WRAPPERS_V1 0
 #endif
 
+
     EXTERN pxCurrentTCB
     EXTERN xSecureContext
     EXTERN vTaskSwitchContext
@@ -167,7 +168,6 @@ vRestoreContextOfFirstTask:
         ldmia r2!, {r0, r3-r6}              /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, r6 = LR. */
         subs r2, #20
         msr psp, r3
-        msr psplim, r4
         msr control, r5
         mov lr, r6
         ldr r4, =xSecureContext             /* Read the location of xSecureContext i.e. &( xSecureContext ). */
@@ -203,7 +203,6 @@ vRestoreContextOfFirstTask:
     ldm  r0!, {r1-r3}                       /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
     ldr  r4, =xSecureContext
     str  r1, [r4]                           /* Set xSecureContext to this task's value for the same. */
-    msr  psplim, r2                         /* Set this task's PSPLIM value. */
     movs r1, #2                             /* r1 = 2. */
     msr  CONTROL, r1                        /* Switch to use PSP in the thread mode. */
     adds r0, #32                            /* Discard everything up to r0. */
@@ -279,7 +278,7 @@ PendSV_Handler:
 
     save_special_regs:
         mrs r3, psp                         /* r3 = PSP. */
-        mrs r4, psplim                      /* r4 = PSPLIM. */
+        movs r4, #0                         /* r4 = 0. 0 is stored in the PSPLIM slot. */
         mrs r5, control                     /* r5 = CONTROL. */
         mov r6, lr                          /* r6 = LR. */
         stmia r2!, {r0, r3-r6}              /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
@@ -347,7 +346,6 @@ PendSV_Handler:
         ldmia r2!, {r0, r3-r6}              /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, r6 = LR. */
         subs r2, #20
         msr psp, r3
-        msr psplim, r4
         msr control, r5
         mov lr, r6
         ldr r4, =xSecureContext             /* Read the location of xSecureContext i.e. &( xSecureContext ). */
@@ -406,7 +404,7 @@ PendSV_Handler:
 
     subs r2, r2, #12                        /* Make space for xSecureContext, PSPLIM and LR on the stack. */
     str r2, [r1]                            /* Save the new top of stack in TCB. */
-    mrs r1, psplim                          /* r1 = PSPLIM. */
+    movs r1, #0                             /* r1 = 0. 0 is stored in the PSPLIM slot. */
     mov r3, lr                              /* r3 = LR/EXC_RETURN. */
     stmia r2!, {r0, r1, r3}                 /* Store xSecureContext, PSPLIM and LR on the stack. */
 
@@ -417,7 +415,7 @@ PendSV_Handler:
         ldr r1, [r3]                        /* Read pxCurrentTCB. */
         subs r2, r2, #44                    /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
         str r2, [r1]                        /* Save the new top of stack in TCB. */
-        mrs r1, psplim                      /* r1 = PSPLIM. */
+        movs r1, #0                         /* r1 = 0. 0 is stored in the PSPLIM slot. */
         mov r3, lr                          /* r3 = LR/EXC_RETURN. */
         stmia r2!, {r0, r1, r3-r7}          /* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */
         mov r4, r8                          /* r4 = r8. */
@@ -436,7 +434,6 @@ PendSV_Handler:
         ldr r2, [r1]                        /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
 
         ldmia r2!, {r0, r1, r4}             /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
-        msr psplim, r1                      /* Restore the PSPLIM register value for the task. */
         mov lr, r4                          /* LR = r4. */
         ldr r3, =xSecureContext             /* Read the location of xSecureContext i.e. &( xSecureContext ). */
         str r0, [r3]                        /* Restore the task's xSecureContext. */
diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
index 0ba29f9b4..0c5b76488 100644
--- a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
@@ -67,6 +67,16 @@
 #if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
     #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
 #endif
+
+/**
+ * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23
+ * only when FreeRTOS runs on secure side.
+ */
+#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) )
+    #define portUSE_PSPLIM_REGISTER    0
+#else
+    #define portUSE_PSPLIM_REGISTER    1
+#endif
 /*-----------------------------------------------------------*/
 
 /**
@@ -1185,11 +1195,19 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
              * restore it when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* Use the pulSystemCallStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            }
+            #endif
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
@@ -1316,11 +1334,19 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Store the value of the LR and PSPLIM registers before the SVC was raised.
              * We need to restore it when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* Use the pulSystemCallStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            }
+            #endif
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
@@ -1415,7 +1441,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Restore the LR and PSPLIM to what they were at the time of
              * system call entry. */
             pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* If the hardware used padding to force the stack pointer
              * to be double word aligned, set the stacked xPSR bit[9],
diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s b/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s
index 8f77c4daf..836a927c8 100644
--- a/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s
+++ b/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s
@@ -36,6 +36,10 @@ files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler.
     #define configUSE_MPU_WRAPPERS_V1 0
 #endif
 
+#ifndef configRUN_FREERTOS_SECURE_ONLY
+    #define configRUN_FREERTOS_SECURE_ONLY 0
+#endif
+
     EXTERN pxCurrentTCB
     EXTERN vTaskSwitchContext
     EXTERN vPortSVCHandler_C
@@ -157,7 +161,9 @@ vRestoreContextOfFirstTask:
         ldmia r1!, {r2-r5}                  /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, r5 = LR. */
         subs r1, #16
         msr psp, r2
+    #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
         msr psplim, r3
+    #endif
         msr control, r4
         mov lr, r5
 
@@ -189,7 +195,9 @@ vRestoreContextOfFirstTask:
     ldr  r0, [r1]                           /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
 
     ldm  r0!, {r1-r2}                       /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
+#if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
     msr  psplim, r1                         /* Set this task's PSPLIM value. */
+#endif
     movs r1, #2                             /* r1 = 2. */
     msr  CONTROL, r1                        /* Switch to use PSP in the thread mode. */
     adds r0, #32                            /* Discard everything up to r0. */
@@ -253,7 +261,11 @@ PendSV_Handler:
 
     save_special_regs:
         mrs r2, psp                         /* r2 = PSP. */
+    #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
         mrs r3, psplim                      /* r3 = PSPLIM. */
+    #else
+        movs r3, #0                         /* r3 = 0. 0 is stored in the PSPLIM slot. */
+    #endif
         mrs r4, control                     /* r4 = CONTROL. */
         mov r5, lr                          /* r5 = LR. */
         stmia r1!, {r2-r5}                  /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
@@ -321,7 +333,9 @@ PendSV_Handler:
         ldmia r1!, {r2-r5}                  /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, r5 = LR. */
         subs r1, #16
         msr psp, r2
+    #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
         msr psplim, r3
+    #endif
         msr control, r4
         mov lr, r5
 
@@ -354,7 +368,11 @@ PendSV_Handler:
 
     subs r0, r0, #40                        /* Make space for PSPLIM, LR and the remaining registers on the stack. */
     str r0, [r1]                            /* Save the new top of stack in TCB. */
+#if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
     mrs r2, psplim                          /* r2 = PSPLIM. */
+#else
+    movs r2, #0                             /* r0 = 0. 0 is stored in the PSPLIM slot. */
+#endif
     mov r3, lr                              /* r3 = LR/EXC_RETURN. */
     stmia r0!, {r2-r7}                      /* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */
     mov r4, r8                              /* r4 = r8. */
@@ -380,7 +398,9 @@ PendSV_Handler:
     msr psp, r0                             /* Remember the new top of stack for the task. */
     subs r0, r0, #40                        /* Move to the starting of the saved context. */
     ldmia r0!, {r2-r7}                      /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */
+#if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
     msr psplim, r2                          /* Restore the PSPLIM register value for the task. */
+#endif
     bx r3
 
 #endif /* configENABLE_MPU */
diff --git a/portable/IAR/ARM_CM33/non_secure/port.c b/portable/IAR/ARM_CM33/non_secure/port.c
index 0ba29f9b4..0c5b76488 100644
--- a/portable/IAR/ARM_CM33/non_secure/port.c
+++ b/portable/IAR/ARM_CM33/non_secure/port.c
@@ -67,6 +67,16 @@
 #if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
     #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
 #endif
+
+/**
+ * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23
+ * only when FreeRTOS runs on secure side.
+ */
+#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) )
+    #define portUSE_PSPLIM_REGISTER    0
+#else
+    #define portUSE_PSPLIM_REGISTER    1
+#endif
 /*-----------------------------------------------------------*/
 
 /**
@@ -1185,11 +1195,19 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
              * restore it when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* Use the pulSystemCallStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            }
+            #endif
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
@@ -1316,11 +1334,19 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Store the value of the LR and PSPLIM registers before the SVC was raised.
              * We need to restore it when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* Use the pulSystemCallStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            }
+            #endif
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
@@ -1415,7 +1441,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Restore the LR and PSPLIM to what they were at the time of
              * system call entry. */
             pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* If the hardware used padding to force the stack pointer
              * to be double word aligned, set the stacked xPSR bit[9],
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
index 0ba29f9b4..0c5b76488 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
@@ -67,6 +67,16 @@
 #if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
     #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
 #endif
+
+/**
+ * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23
+ * only when FreeRTOS runs on secure side.
+ */
+#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) )
+    #define portUSE_PSPLIM_REGISTER    0
+#else
+    #define portUSE_PSPLIM_REGISTER    1
+#endif
 /*-----------------------------------------------------------*/
 
 /**
@@ -1185,11 +1195,19 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
              * restore it when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* Use the pulSystemCallStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            }
+            #endif
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
@@ -1316,11 +1334,19 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Store the value of the LR and PSPLIM registers before the SVC was raised.
              * We need to restore it when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* Use the pulSystemCallStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            }
+            #endif
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
@@ -1415,7 +1441,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Restore the LR and PSPLIM to what they were at the time of
              * system call entry. */
             pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* If the hardware used padding to force the stack pointer
              * to be double word aligned, set the stacked xPSR bit[9],
diff --git a/portable/IAR/ARM_CM35P/non_secure/port.c b/portable/IAR/ARM_CM35P/non_secure/port.c
index 0ba29f9b4..0c5b76488 100644
--- a/portable/IAR/ARM_CM35P/non_secure/port.c
+++ b/portable/IAR/ARM_CM35P/non_secure/port.c
@@ -67,6 +67,16 @@
 #if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
     #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
 #endif
+
+/**
+ * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23
+ * only when FreeRTOS runs on secure side.
+ */
+#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) )
+    #define portUSE_PSPLIM_REGISTER    0
+#else
+    #define portUSE_PSPLIM_REGISTER    1
+#endif
 /*-----------------------------------------------------------*/
 
 /**
@@ -1185,11 +1195,19 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
              * restore it when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* Use the pulSystemCallStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            }
+            #endif
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
@@ -1316,11 +1334,19 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Store the value of the LR and PSPLIM registers before the SVC was raised.
              * We need to restore it when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* Use the pulSystemCallStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            }
+            #endif
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
@@ -1415,7 +1441,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Restore the LR and PSPLIM to what they were at the time of
              * system call entry. */
             pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* If the hardware used padding to force the stack pointer
              * to be double word aligned, set the stacked xPSR bit[9],
diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c b/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
index 0ba29f9b4..0c5b76488 100644
--- a/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
@@ -67,6 +67,16 @@
 #if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
     #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
 #endif
+
+/**
+ * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23
+ * only when FreeRTOS runs on secure side.
+ */
+#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) )
+    #define portUSE_PSPLIM_REGISTER    0
+#else
+    #define portUSE_PSPLIM_REGISTER    1
+#endif
 /*-----------------------------------------------------------*/
 
 /**
@@ -1185,11 +1195,19 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
              * restore it when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* Use the pulSystemCallStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            }
+            #endif
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
@@ -1316,11 +1334,19 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Store the value of the LR and PSPLIM registers before the SVC was raised.
              * We need to restore it when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* Use the pulSystemCallStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            }
+            #endif
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
@@ -1415,7 +1441,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Restore the LR and PSPLIM to what they were at the time of
              * system call entry. */
             pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* If the hardware used padding to force the stack pointer
              * to be double word aligned, set the stacked xPSR bit[9],
diff --git a/portable/IAR/ARM_CM55/non_secure/port.c b/portable/IAR/ARM_CM55/non_secure/port.c
index 0ba29f9b4..0c5b76488 100644
--- a/portable/IAR/ARM_CM55/non_secure/port.c
+++ b/portable/IAR/ARM_CM55/non_secure/port.c
@@ -67,6 +67,16 @@
 #if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
     #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
 #endif
+
+/**
+ * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23
+ * only when FreeRTOS runs on secure side.
+ */
+#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) )
+    #define portUSE_PSPLIM_REGISTER    0
+#else
+    #define portUSE_PSPLIM_REGISTER    1
+#endif
 /*-----------------------------------------------------------*/
 
 /**
@@ -1185,11 +1195,19 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
              * restore it when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* Use the pulSystemCallStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            }
+            #endif
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
@@ -1316,11 +1334,19 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Store the value of the LR and PSPLIM registers before the SVC was raised.
              * We need to restore it when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* Use the pulSystemCallStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            }
+            #endif
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
@@ -1415,7 +1441,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Restore the LR and PSPLIM to what they were at the time of
              * system call entry. */
             pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* If the hardware used padding to force the stack pointer
              * to be double word aligned, set the stacked xPSR bit[9],
diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/port.c b/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
index 0ba29f9b4..0c5b76488 100644
--- a/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
@@ -67,6 +67,16 @@
 #if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
     #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
 #endif
+
+/**
+ * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23
+ * only when FreeRTOS runs on secure side.
+ */
+#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) )
+    #define portUSE_PSPLIM_REGISTER    0
+#else
+    #define portUSE_PSPLIM_REGISTER    1
+#endif
 /*-----------------------------------------------------------*/
 
 /**
@@ -1185,11 +1195,19 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
              * restore it when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* Use the pulSystemCallStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            }
+            #endif
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
@@ -1316,11 +1334,19 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Store the value of the LR and PSPLIM registers before the SVC was raised.
              * We need to restore it when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* Use the pulSystemCallStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            }
+            #endif
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
@@ -1415,7 +1441,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Restore the LR and PSPLIM to what they were at the time of
              * system call entry. */
             pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* If the hardware used padding to force the stack pointer
              * to be double word aligned, set the stacked xPSR bit[9],
diff --git a/portable/IAR/ARM_CM85/non_secure/port.c b/portable/IAR/ARM_CM85/non_secure/port.c
index 0ba29f9b4..0c5b76488 100644
--- a/portable/IAR/ARM_CM85/non_secure/port.c
+++ b/portable/IAR/ARM_CM85/non_secure/port.c
@@ -67,6 +67,16 @@
 #if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
     #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
 #endif
+
+/**
+ * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23
+ * only when FreeRTOS runs on secure side.
+ */
+#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) )
+    #define portUSE_PSPLIM_REGISTER    0
+#else
+    #define portUSE_PSPLIM_REGISTER    1
+#endif
 /*-----------------------------------------------------------*/
 
 /**
@@ -1185,11 +1195,19 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
              * restore it when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* Use the pulSystemCallStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            }
+            #endif
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
@@ -1316,11 +1334,19 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Store the value of the LR and PSPLIM registers before the SVC was raised.
              * We need to restore it when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* Use the pulSystemCallStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            }
+            #endif
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
@@ -1415,7 +1441,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Restore the LR and PSPLIM to what they were at the time of
              * system call entry. */
             pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* If the hardware used padding to force the stack pointer
              * to be double word aligned, set the stacked xPSR bit[9],
diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/port.c b/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
index 0ba29f9b4..0c5b76488 100644
--- a/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
@@ -67,6 +67,16 @@
 #if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
     #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
 #endif
+
+/**
+ * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23
+ * only when FreeRTOS runs on secure side.
+ */
+#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) )
+    #define portUSE_PSPLIM_REGISTER    0
+#else
+    #define portUSE_PSPLIM_REGISTER    1
+#endif
 /*-----------------------------------------------------------*/
 
 /**
@@ -1185,11 +1195,19 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
              * restore it when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* Use the pulSystemCallStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            }
+            #endif
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
@@ -1316,11 +1334,19 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Store the value of the LR and PSPLIM registers before the SVC was raised.
              * We need to restore it when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* Use the pulSystemCallStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+            }
+            #endif
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
@@ -1415,7 +1441,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Restore the LR and PSPLIM to what they were at the time of
              * system call entry. */
             pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
-            __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            #if ( portUSE_PSPLIM_REGISTER == 1 )
+            {
+                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+            }
+            #endif
 
             /* If the hardware used padding to force the stack pointer
              * to be double word aligned, set the stacked xPSR bit[9],

From 5a9d7c8388c32ff0bc530cd713f32e15c3e38d52 Mon Sep 17 00:00:00 2001
From: Joseph Julicher <jjulicher@mac.com>
Date: Fri, 29 Sep 2023 19:11:55 -0700
Subject: [PATCH 073/424] Sample FreeRTOSConfig.h and template port (#812)

* config file experiments

* adding a config file for an example

* Added a template port and updated the CMakeLists

* template and default configuration build

* finalising the sample FreeRTOSConfig.h header file

* removed .config hidden file

* further reductions in the template port

* Uncrustify: triggered by comment.

* Uncrustify: triggered by comment.

* minor readme updates

* fixed spelling error in HTTP

* fixed a type and added a link to the sample readme

* uncrustified FreeRTOSConfig.h

* Uncrustify: triggered by comment.

* Revert "Uncrustify: triggered by comment."

This reverts commit e534f46f2d772068fe787130ef615d2aea65a2df.

* Revert "Revert "Uncrustify: triggered by comment.""

This reverts commit c9058dd383ad475315c7867933dc9412918be81a.

* excluding the FreeRTOSConfig.h from copyright+license check because this file is intended to be incorporated into user code

* Removed the copyright and license from the template files

* put license copy in the template and sample files

* Uncrustify: triggered by comment.

---------

Co-authored-by: GitHub Action <action@github.com>
---
 .github/scripts/kernel_checker.py     |   4 +-
 CMakeLists.txt                        |   1 +
 README.md                             |  22 +-
 portable/CMakeLists.txt               |  11 +-
 portable/template/port.c              |  69 +++++
 portable/template/portmacro.h         | 114 +++++++
 sample_configuration/FreeRTOSConfig.h | 427 ++++++++++++++++++++++++++
 sample_configuration/readme.md        |   7 +
 8 files changed, 650 insertions(+), 5 deletions(-)
 create mode 100644 portable/template/port.c
 create mode 100644 portable/template/portmacro.h
 create mode 100644 sample_configuration/FreeRTOSConfig.h
 create mode 100644 sample_configuration/readme.md

diff --git a/.github/scripts/kernel_checker.py b/.github/scripts/kernel_checker.py
index 4b4fbe40d..9f23a79d8 100755
--- a/.github/scripts/kernel_checker.py
+++ b/.github/scripts/kernel_checker.py
@@ -38,6 +38,7 @@ KERNEL_IGNORED_FILES = [
     'Makefile',
     '.DS_Store',
     'cspell.config.yaml'
+    'FreeRTOSConfig.h'
 ]
 
 KERNEL_IGNORED_EXTENSIONS = [
@@ -92,7 +93,8 @@ KERNEL_IGNORED_PATTERNS = [
     r'.*portable/ThirdParty/xClang/XCOREAI/*',
     r'.*IAR/ARM_C*',
     r'.*IAR/78K0R/*',
-    r'.*CCS/MSP430X/*'
+    r'.*CCS/MSP430X/*',
+    r'.*portable/template/*'
 ]
 
 KERNEL_THIRD_PARTY_PATTERNS = [
diff --git a/CMakeLists.txt b/CMakeLists.txt
index 15bbe0bf6..5d27a58c6 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -196,6 +196,7 @@ if(NOT FREERTOS_PORT)
         " SOFTUNE_MB91460                  - Compiler: Softune       Target: MB91460\n"
         " SOFTUNE_MB96340                  - Compiler: Softune       Target: MB96340\n"
         " TASKING_ARM_CM4F                 - Compiler: Tasking       Target: ARM Cortex-M4 with FPU\n"
+        " TEMPLATE                         - Compiler: HOST          Target: None\n"
         " CDK_THEAD_CK802                  - Compiler: CDK           Target: T-head CK802\n"
         " XCC_XTENSA                       - Compiler: XCC           Target: Xtensa\n"
         " WIZC_PIC18                       - Compiler: WizC          Target: PIC18")
diff --git a/README.md b/README.md
index 75c7c66dc..a9a07040a 100644
--- a/README.md
+++ b/README.md
@@ -1,6 +1,8 @@
 [![CMock Unit Tests](https://github.com/FreeRTOS/FreeRTOS-Kernel/actions/workflows/unit-tests.yml/badge.svg?branch=main&event=push)](https://github.com/FreeRTOS/FreeRTOS-Kernel/actions/workflows/unit-tests.yml?query=branch%3Amain+event%3Apush+workflow%3A%22CMock+Unit+Tests%22++)
 [![codecov](https://codecov.io/gh/FreeRTOS/FreeRTOS-Kernel/badge.svg?branch=main)](https://codecov.io/gh/FreeRTOS/FreeRTOS-Kernel)
+
 ## Getting started
+
 This repository contains FreeRTOS kernel source/header files and kernel
 ports only. This repository is referenced as a submodule in
 [FreeRTOS/FreeRTOS](https://github.com/FreeRTOS/FreeRTOS)
@@ -20,6 +22,7 @@ Additionally, for FreeRTOS kernel feature information refer to the
 and [API Reference](https://www.FreeRTOS.org/a00106.html).
 
 ### Getting help
+
 If you have any questions or need assistance troubleshooting your FreeRTOS project,
 we have an active community that can help on the
 [FreeRTOS Community Support Forum](https://forums.freertos.org).
@@ -27,6 +30,7 @@ we have an active community that can help on the
 ## To consume FreeRTOS-Kernel
 
 ### Consume with CMake
+
 If using CMake, it is recommended to use this repository using FetchContent.
 Add the following into your project's main or a subdirectory's `CMakeLists.txt`:
 
@@ -42,12 +46,13 @@ FetchContent_Declare( freertos_kernel
 In case you prefer to add it as a git submodule, do:
 
 ```bash
-$ git submodule add https://github.com/FreeRTOS/FreeRTOS-Kernel.git <path of the submodule>
-$ git submodule update --init
+git submodule add https://github.com/FreeRTOS/FreeRTOS-Kernel.git <path of the submodule>
+git submodule update --init
 ```
 
 - Add a freertos_config library (typically an INTERFACE library) The following assumes the directory structure:
   - `include/FreeRTOSConfig.h`
+
 ```cmake
 add_library(freertos_config INTERFACE)
 
@@ -93,15 +98,19 @@ target_compile_options(freertos_config INTERFACE ${options})
 ### Consuming stand-alone - Cloning this repository
 
 To clone using HTTPS:
+
 ```
 git clone https://github.com/FreeRTOS/FreeRTOS-Kernel.git
 ```
+
 Using SSH:
+
 ```
 git clone git@github.com:FreeRTOS/FreeRTOS-Kernel.git
 ```
 
 ## Repository structure
+
 - The root of this repository contains the three files that are common to
 every port - list.c, queue.c and tasks.c.  The kernel is contained within these
 three files.  croutine.c implements the optional co-routine functionality - which
@@ -112,7 +121,11 @@ See the readme file in the ```./portable``` directory for more information.
 
 - The ```./include``` directory contains the real time kernel header files.
 
+- The ```./sample_configuration``` directory contains a sample `FreeRTOSConfig.h` to help jumpstart a new project.
+See the [FreeRTOSConfig.h](sample_configuration/FreeRTOSConfig.h) file for instructions.
+
 ### Code Formatting
+
 FreeRTOS files are formatted using the
 "[uncrustify](https://github.com/uncrustify/uncrustify)" tool.
 The configuration file used by uncrustify can be found in the
@@ -121,26 +134,31 @@ The configuration file used by uncrustify can be found in the
 file.
 
 ### Line Endings
+
 File checked into the FreeRTOS-Kernel repository use unix-style LF line endings
 for the best compatibility with git.
 
 For optimal compatibility with Microsoft Windows tools, it is best to enable
 the git autocrlf feature. You can enable this setting for the current
 repository using the following command:
+
 ```
 git config core.autocrlf true
 ```
 
 ### Git History Optimizations
+
 Some commits in this repository perform large refactors which touch many lines
 and lead to unwanted behavior when using the `git blame` command. You can
 configure git to ignore the list of large refactor commits in this repository
 with the following command:
+
 ```
 git config blame.ignoreRevsFile .git-blame-ignore-revs
 ```
 
 ### Spelling and Formatting
+
 We recommend using [Visual Studio Code](https://code.visualstudio.com),
 commonly referred to as VSCode, when working on the FreeRTOS-Kernel.
 The FreeRTOS-Kernel also uses [cSpell](https://cspell.org/) as part of its
diff --git a/portable/CMakeLists.txt b/portable/CMakeLists.txt
index a13e08820..327e9236b 100644
--- a/portable/CMakeLists.txt
+++ b/portable/CMakeLists.txt
@@ -8,7 +8,11 @@ endif()
 # FreeRTOS internal cmake file. Do not use it in user top-level project
 
 add_library(freertos_kernel_port STATIC
-    # 16-Bit DOS ports for BCC
+    # TEMPLATE Port
+    $<$<STREQUAL:${FREERTOS_PORT},TEMPLATE>:
+        template/port.c>
+
+        # 16-Bit DOS ports for BCC
     $<$<STREQUAL:${FREERTOS_PORT},BCC_16BIT_DOS_FLSH186>:
         BCC/16BitDOS/common/portcomn.c
         BCC/16BitDOS/Flsh186/port.c>
@@ -708,7 +712,10 @@ if( FREERTOS_PORT MATCHES "GCC_ARM_CM(3|4)_MPU" OR
 endif()
 
 target_include_directories(freertos_kernel_port PUBLIC
-    # 16-Bit DOS ports for BCC
+    # TEMPLATE Port
+    $<$<STREQUAL:${FREERTOS_PORT},TEMPLATE>:${CMAKE_CURRENT_LIST_DIR}/template>
+
+        # 16-Bit DOS ports for BCC
     $<$<STREQUAL:${FREERTOS_PORT},BCC_16BIT_DOS_FLSH186>:
         ${CMAKE_CURRENT_LIST_DIR}/BCC/16BitDOS/common
         ${CMAKE_CURRENT_LIST_DIR}/BCC/16BitDOS/Flsh186>
diff --git a/portable/template/port.c b/portable/template/port.c
new file mode 100644
index 000000000..5cbe72253
--- /dev/null
+++ b/portable/template/port.c
@@ -0,0 +1,69 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#include "FreeRTOS.h"
+#include "task.h"
+
+BaseType_t xPortStartScheduler( void )
+{
+    return pdTRUE;
+}
+
+void vPortEndScheduler( void )
+{
+}
+
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
+{
+    return NULL;
+}
+
+void vPortYield( void )
+{
+    /* Save the current Context */
+    /* Switch to the highest priority task that is ready to run. */
+    vTaskSwitchContext();
+    /* Start executing the task we have just switched to. */
+}
+
+static void prvTickISR( void )
+{
+    /* Interrupts must have been enabled for the ISR to fire, so we have to
+     * save the context with interrupts enabled. */
+
+    /* Maintain the tick count. */
+    if( xTaskIncrementTick() != pdFALSE )
+    {
+        /* Switch to the highest priority task that is ready to run. */
+        vTaskSwitchContext();
+    }
+
+    /* start executing the new task */
+}
diff --git a/portable/template/portmacro.h b/portable/template/portmacro.h
new file mode 100644
index 000000000..d2dfd161e
--- /dev/null
+++ b/portable/template/portmacro.h
@@ -0,0 +1,114 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR                 char
+#define portFLOAT                float
+#define portDOUBLE               double
+#define portLONG                 long
+#define portSHORT                int
+#define portSTACK_TYPE           uint8_t
+#define portBASE_TYPE            char
+
+#define portSTACK_GROWTH         ( -1 )
+#define portBYTE_ALIGNMENT       4
+#define portPOINTER_SIZE_TYPE    size_t
+typedef portSTACK_TYPE   StackType_t;
+typedef signed char      BaseType_t;
+typedef unsigned char    UBaseType_t;
+
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffffffffUL
+#else
+    #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+#endif
+
+/* Architecture specific optimisations. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+    #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+/* Check the configuration. */
+    #if ( configMAX_PRIORITIES > 32 )
+        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+    #endif
+
+/* Store/clear the ready priorities in a bit map. */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+/*-----------------------------------------------------------*/
+
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) \
+    {                                                                    \
+        uxTopPriority = 0;                                               \
+    }                                                                    \
+    while( 0 )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+#define portDISABLE_INTERRUPTS()   \
+    { /* Disable the interrupts */ \
+    }
+#define portENABLE_INTERRUPTS()   \
+    { /* Enable the interrupts */ \
+    }
+
+#define portENTER_CRITICAL()                                             \
+    { /* preserve current interrupt state and then disable interrupts */ \
+    }
+#define portEXIT_CRITICAL()                              \
+    { /* restore previously preserved interrupt state */ \
+    }
+
+extern void vPortYield( void );
+#define portYIELD()                                           vPortYield()
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+
+#endif /* PORTMACRO_H */
diff --git a/sample_configuration/FreeRTOSConfig.h b/sample_configuration/FreeRTOSConfig.h
new file mode 100644
index 000000000..43282118f
--- /dev/null
+++ b/sample_configuration/FreeRTOSConfig.h
@@ -0,0 +1,427 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*******************************************************************************
+ * This file provides an example FreeRTOSConfig.h header file, inclusive of an
+ * abbreviated explanation of each configuration item.  Online and reference
+ * documentation provides more information.
+ * https://www.freertos.org/a00110.html
+ *
+ * Constant values enclosed in square brackets ('[' and ']') must be completed
+ * before this file will build.
+ *
+ * Use the FreeRTOSConfig.h supplied with the RTOS port in use rather than this
+ * generic file, if one is available.
+ ******************************************************************************/
+
+#ifndef __FREERTOS_CONFIG_H__
+#define __FREERTOS_CONFIG_H__
+
+/******************************************************************************/
+/* Hardware description related definitions. **********************************/
+/******************************************************************************/
+
+/* In most cases, configCPU_CLOCK_HZ must be set to the frequency of the clock
+ * that drives the peripheral used to generate the kernels periodic tick interrupt.
+ * The default value is set to 20MHz and matches the QEMU demo settings.  Your
+ * application will certainly need a different value so set this correctly.
+ * This is very often, but not always, equal to the main system clock frequency. */
+#define configCPU_CLOCK_HZ    ( ( unsigned long ) 20000000 )
+
+/* configSYSTICK_CLOCK_HZ is an optional parameter for ARM Cortex-M ports only.
+ *
+ * By default ARM Cortex-M ports generate the RTOS tick interrupt from the
+ * Cortex-M SysTick timer. Most Cortex-M MCUs run the SysTick timer at the same
+ * frequency as the MCU itself - when that is the case configSYSTICK_CLOCK_HZ is
+ * not needed and should be left undefined. If the SysTick timer is clocked at a
+ * different frequency to the MCU core then set configCPU_CLOCK_HZ to the MCU clock
+ * frequency, as normal, and configSYSTICK_CLOCK_HZ to the SysTick clock
+ * frequency.  Not used if left undefined.
+ * The default value is undefined (commented out).  If you need this value bring it
+ * back and set it to a suitable value */
+
+/*
+ #define configSYSTICK_CLOCK_HZ                  [Platform specific]
+ */
+
+/******************************************************************************/
+/* Scheduling behaviour related definitions. **********************************/
+/******************************************************************************/
+
+/* configTICK_RATE_HZ sets frequency of the tick interrupt in Hz, normally
+ * calculated from the configCPU_CLOCK_HZ value. */
+#define configTICK_RATE_HZ                         100
+
+/* Set configUSE_PREEMPTION to 1 to use pre-emptive scheduling.  Set
+ * configUSE_PREEMPTION to 0 to use co-operative scheduling.
+ * See https://www.freertos.org/single-core-amp-smp-rtos-scheduling.html */
+#define configUSE_PREEMPTION                       1
+
+/* Set configUSE_TIME_SLICING to 1 to have the scheduler switch between Ready
+ * state tasks of equal priority on every tick interrupt.  Set
+ * configUSE_TIME_SLICING to 0 to prevent the scheduler switching between Ready
+ * state tasks just because there was a tick interrupt.  See
+ * https://freertos.org/single-core-amp-smp-rtos-scheduling.html */
+#define configUSE_TIME_SLICING                     0
+
+/* Set configUSE_PORT_OPTIMISED_TASK_SELECTION to 1 to select the next task to
+ * run using an algorithm optimised to the instruction set of the target hardware -
+ * normally using a count leading zeros assembly instruction.  Set to 0 to select
+ * the next task to run using a generic C algorithm that works for all FreeRTOS
+ * ports.  Not all FreeRTOS ports have this option.  Defaults to 0 if left
+ * undefined. */
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION    0
+
+/* Set configUSE_TICKLESS_IDLE to 1 to use the low power tickless mode.  Set to
+ * 0 to keep the tick interrupt running at all times.  Not all FreeRTOS ports
+ * support tickless mode. See https://www.freertos.org/low-power-tickless-rtos.html
+ * Defaults to 0 if left undefined. */
+#define configUSE_TICKLESS_IDLE                    0
+
+/* configMAX_PRIORITIES Sets the number of available task priorities.  Tasks can
+ * be assigned priorities of 0 to (configMAX_PRIORITIES - 1).  Zero is the lowest
+ * priority. */
+#define configMAX_PRIORITIES                       5
+
+/* configMINIMAL_STACK_SIZE defines the size of the stack used by the Idle task
+ * (in words, not in bytes!).  The kernel does not use this constant for any other
+ * purpose.  Demo applications use the constant to make the demos somewhat portable
+ * across hardware architectures. */
+#define configMINIMAL_STACK_SIZE                   128
+
+/* configMAX_TASK_NAME_LEN sets the maximum length (in characters) of a task's
+ * human readable name.  Includes the NULL terminator. */
+#define configMAX_TASK_NAME_LEN                    16
+
+/* The tick count is held in a variable of type TickType_t.  Set
+ * configUSE_16_BIT_TICKS to 1 to make TickType_t a 16-bit type.  Set
+ * configUSE_16_BIT_TICKS to 0 to make TickType_t either a 32 or 64-bit type
+ * depending on the architecture.  Using a 16-bit type can greatly improve
+ * efficiency on 8-bit and 16-bit microcontrollers, but at the cost of limiting the
+ * maximum specifiable block time to 0xffff. */
+#define configUSE_16_BIT_TICKS                     0
+
+/* Set configIDLE_SHOULD_YIELD to 1 to have the Idle task yield to an
+ * application task if there is an Idle priority (priority 0) application task that
+ * can run.  Set to 0 to have the Idle task use all of its timeslice.  Default to 1
+ * if left undefined. */
+#define configIDLE_SHOULD_YIELD                    1
+
+/* Each task has an array of task notifications.
+ * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the array.
+ * See https://www.freertos.org/RTOS-task-notifications.html  Defaults to 1 if
+ * left undefined. */
+#define configTASK_NOTIFICATION_ARRAY_ENTRIES      1
+
+/* configQUEUE_REGISTRY_SIZE sets the maximum number of queues and semaphores
+ * that can be referenced from the queue registry.  Only required when using a
+ * kernel aware debugger.  Defaults to 0 if left undefined. */
+#define configQUEUE_REGISTRY_SIZE                  0
+
+/* Set configENABLE_BACKWARD_COMPATIBILITY to 1 to map function names and
+ * datatypes from old version of FreeRTOS to their latest equivalent.  Defaults to
+ * 1 if left undefined. */
+#define configENABLE_BACKWARD_COMPATIBILITY        0
+
+/* Each task has its own array of pointers that can be used as thread local
+ * storage.  configNUM_THREAD_LOCAL_STORAGE_POINTERS set the number of indexes in
+ * the array.  See https://www.freertos.org/thread-local-storage-pointers.html
+ * Defaults to 0 if left undefined. */
+#define configNUM_THREAD_LOCAL_STORAGE_POINTERS    0
+
+/* Sets the type used by the parameter to xTaskCreate() that specifies the stack
+ * size of the task being created.  The same type is used to return information
+ * about stack usage in various other API calls.  Defaults to size_t if left
+ * undefined. */
+#define configSTACK_DEPTH_TYPE                     size_t
+
+/* configMESSAGE_BUFFER_LENGTH_TYPE sets the type used to store the length of
+ *  each message written to a FreeRTOS message buffer (the length is also written to
+ *  the message buffer.  Defaults to size_t if left undefined - but that may waste
+ *  space if messages never go above a length that could be held in a uint8_t. */
+#define configMESSAGE_BUFFER_LENGTH_TYPE           size_t
+
+/* Set configUSE_NEWLIB_REENTRANT to 1 to have a newlib reent structure
+ * allocated for each task.  Set to 0 to not support newlib reent structures.
+ * Default to 0 if left undefined.
+ *
+ * Note Newlib support has been included by popular demand, but is not used or
+ * tested by the FreeRTOS maintainers themselves. FreeRTOS is not responsible for
+ * resulting newlib operation. User must be familiar with newlib and must provide
+ * system-wide implementations of the necessary stubs. Note that (at the time of
+ * writing) the current newlib design implements a system-wide malloc() that must
+ * be provided with locks. */
+#define configUSE_NEWLIB_REENTRANT                 0
+
+/******************************************************************************/
+/* Software timer related definitions. ****************************************/
+/******************************************************************************/
+
+/* Set configUSE_TIMERS to 1 to include software timer functionality in the
+ * build.  Set to 0 to exclude software timer functionality from the build.  The
+ * FreeRTOS/source/timers.c source file must be included in the build if
+ * configUSE_TIMERS is set to 1.  Default to 0 if left undefined.  See
+ * https://www.freertos.org/RTOS-software-timer.html */
+#define configUSE_TIMERS                1
+
+/* configTIMER_TASK_PRIORITY sets the priority used by the timer task.  Only
+ * used if configUSE_TIMERS is set to 1.  The timer task is a standard FreeRTOS
+ * task, so its priority is set like any other task.  See
+ * https://www.freertos.org/RTOS-software-timer-service-daemon-task.html  Only used
+ * if configUSE_TIMERS is set to 1. */
+#define configTIMER_TASK_PRIORITY       ( configMAX_PRIORITIES - 1 )
+
+/* configTIMER_TASK_STACK_DEPTH sets the size of the stack allocated to the
+ * timer task (in words, not in bytes!).  The timer task is a standard FreeRTOS
+ * task.  See https://www.freertos.org/RTOS-software-timer-service-daemon-task.html
+ * Only used if configUSE_TIMERS is set to 1. */
+#define configTIMER_TASK_STACK_DEPTH    configMINIMAL_STACK_SIZE
+
+/* configTIMER_QUEUE_LENGTH sets the length of the queue (the number of discrete
+ * items the queue can hold) used to send commands to the timer task.  See
+ * https://www.freertos.org/RTOS-software-timer-service-daemon-task.html  Only used
+ * if configUSE_TIMERS is set to 1. */
+#define configTIMER_QUEUE_LENGTH        10
+
+/******************************************************************************/
+/* Memory allocation related definitions. *************************************/
+/******************************************************************************/
+
+/* Set configSUPPORT_STATIC_ALLOCATION to 1 to include FreeRTOS API functions
+ * that create FreeRTOS objects (tasks, queues, etc.) using statically allocated
+ * memory in the build.  Set to 0 to exclude the ability to create statically
+ * allocated objects from the build.  Defaults to 0 if left undefined.  See
+ * https://www.freertos.org/Static_Vs_Dynamic_Memory_Allocation.html */
+#define configSUPPORT_STATIC_ALLOCATION              1
+
+/* Set configSUPPORT_DYNAMIC_ALLOCATION to 1 to include FreeRTOS API functions
+ * that create FreeRTOS objects (tasks, queues, etc.) using dynamically allocated
+ * memory in the build.  Set to 0 to exclude the ability to create dynamically
+ * allocated objects from the build.  Defaults to 1 if left undefined.  See
+ * https://www.freertos.org/Static_Vs_Dynamic_Memory_Allocation.html */
+#define configSUPPORT_DYNAMIC_ALLOCATION             1
+
+/* Sets the total size of the FreeRTOS heap, in bytes, when heap_1.c, heap_2.c
+ * or heap_4.c are included in the build.  This value is defaulted to 4096 bytes but
+ * it must be tailored to each application.  Note the heap will appear in the .bss
+ * section.  See https://www.freertos.org/a00111.html */
+#define configTOTAL_HEAP_SIZE                        4096
+
+/* Set configAPPLICATION_ALLOCATED_HEAP to 1 to have the application allocate
+ * the array used as the FreeRTOS heap.  Set to 0 to have the linker allocate the
+ * array used as the FreeRTOS heap.  Defaults to 0 if left undefined. */
+#define configAPPLICATION_ALLOCATED_HEAP             0
+
+/* Set configSTACK_ALLOCATION_FROM_SEPARATE_HEAP to 1 to have task stacks
+ * allocated from somewhere other than the FreeRTOS heap.  This is useful if you
+ * want to ensure stacks are held in fast memory.  Set to 0 to have task stacks
+ * come from the standard FreeRTOS heap.  The application writer must provide
+ * implementations for pvPortMallocStack() and vPortFreeStack() if set to 1.
+ * Defaults to 0 if left undefined. */
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP    0
+
+/******************************************************************************/
+/* Interrupt nesting behaviour configuration. *********************************/
+/******************************************************************************/
+
+/* configKERNEL_INTERRUPT_PRIORITY sets the priority of the tick and context
+ * switch performing interrupts.  The default value is set to the highest interrupt
+ * priority (0).  Not supported by all FreeRTOS ports.  See
+ * https://www.freertos.org/RTOS-Cortex-M3-M4.html for information specific to ARM
+ * Cortex-M devices. */
+#define configKERNEL_INTERRUPT_PRIORITY          0
+
+/* configMAX_SYSCALL_INTERRUPT_PRIORITY sets the interrupt priority above which
+ * FreeRTOS API calls must not be made.  Interrupts above this priority are never
+ * disabled, so never delayed by RTOS activity.  The default value is set to the
+ * highest interrupt priority (0).  Not supported by all FreeRTOS ports.
+ * See https://www.freertos.org/RTOS-Cortex-M3-M4.html for information specific to
+ * ARM Cortex-M devices. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY     0
+
+/* Another name for configMAX_SYSCALL_INTERRUPT_PRIORITY - the name used depends
+ * on the FreeRTOS port. */
+#define configMAX_API_CALL_INTERRUPT_PRIORITY    0
+
+/******************************************************************************/
+/* Hook and callback function related definitions. ****************************/
+/******************************************************************************/
+
+/* Set the following configUSE_* constants to 1 to include the named hook
+ * functionality in the build.  Set to 0 to exclude the hook functionality from the
+ * build.  The application writer is responsible for providing the hook function
+ * for any set to 1.  See https://www.freertos.org/a00016.html */
+#define configUSE_IDLE_HOOK                   0
+#define configUSE_TICK_HOOK                   0
+#define configUSE_MALLOC_FAILED_HOOK          0
+#define configUSE_DAEMON_TASK_STARTUP_HOOK    0
+
+/* Set configCHECK_FOR_STACK_OVERFLOW to 1 or 2 for FreeRTOS to check for a
+ * stack overflow at the time of a context switch.  Set to 0 to not look for a
+ * stack overflow.  If configCHECK_FOR_STACK_OVERFLOW is 1 then the check only
+ * looks for the stack pointer being out of bounds when a task's context is saved
+ * to its stack - this is fast but somewhat ineffective.  If
+ * configCHECK_FOR_STACK_OVERFLOW is 2 then the check looks for a pattern written
+ * to the end of a task's stack having been overwritten.  This is slower, but will
+ * catch most (but not all) stack overflows.  The application writer must provide
+ * the stack overflow callback when configCHECK_FOR_STACK_OVERFLOW is set to 1.
+ * See https://www.freertos.org/Stacks-and-stack-overflow-checking.html  Defaults
+ * to 0 if left undefined. */
+#define configCHECK_FOR_STACK_OVERFLOW        2
+
+/******************************************************************************/
+/* Run time and task stats gathering related definitions. *********************/
+/******************************************************************************/
+
+/* Set configGENERATE_RUN_TIME_STATS to 1 to have FreeRTOS collect data on the
+* processing time used by each task.  Set to 0 to not collect the data.  The
+* application writer needs to provide a clock source if set to 1.  Defaults to 0
+* if left undefined.  See https://www.freertos.org/rtos-run-time-stats.html */
+#define configGENERATE_RUN_TIME_STATS           0
+
+/* Set configUSE_TRACE_FACILITY to include additional task structure members
+ * are used by trace and visualisation functions and tools.  Set to 0 to exclude
+ * the additional information from the structures.  Defaults to 0 if left
+ * undefined. */
+#define configUSE_TRACE_FACILITY                0
+
+/* Set to 1 to include the vTaskList() and vTaskGetRunTimeStats() functions in
+ * the build.  Set to 0 to exclude these functions from the build.  These two
+ * functions introduce a dependency on string formatting functions that would
+ * otherwise not exist - hence they are kept separate.  Defaults to 0 if left
+ * undefined. */
+#define configUSE_STATS_FORMATTING_FUNCTIONS    0
+
+/******************************************************************************/
+/* Debugging assistance. ******************************************************/
+/******************************************************************************/
+
+/* configASSERT() has the same semantics as the standard C assert().  It can
+ * either be defined to take an action when the assertion fails, or not defined
+ * at all (i.e. comment out or delete the definitions) to completely remove
+ * assertions.  configASSERT() can be defined to anything you want, for example
+ * you can call a function if an assert fails that passes the filename and line
+ * number of the failing assert (for example, "vAssertCalled( __FILE__, __LINE__ )"
+ * or it can simple disable interrupts and sit in a loop to halt all execution
+ * on the failing line for viewing in a debugger. */
+#define configASSERT( x )         \
+    if( ( x ) == 0 )              \
+    {                             \
+        taskDISABLE_INTERRUPTS(); \
+        for( ; ; )                \
+        ;                         \
+    }
+
+/******************************************************************************/
+/* Cortex-M MPU specific definitions. *****************************************/
+/******************************************************************************/
+
+/* If configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS is set to 1 then
+ * the application writer can provide functions that execute in privileged mode.
+ * See: https://www.freertos.org/a00110.html#configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS
+ * Defaults to 0 if left undefined.  Only used by the FreeRTOS Cortex-M MPU ports,
+ * not the standard ARMv7-M Cortex-M port. */
+#define configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS    0
+
+/* Set configTOTAL_MPU_REGIONS to the number of MPU regions implemented on your
+ * target hardware.  Normally 8 or 16.  Only used by the FreeRTOS Cortex-M MPU
+ * ports, not the standard ARMv7-M Cortex-M port.  Defaults to 8 if left
+ * undefined. */
+#define configTOTAL_MPU_REGIONS                                   8
+
+/* configTEX_S_C_B_FLASH allows application writers to override the default
+ * values for the for TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for
+ * the MPU region covering Flash.  Defaults to 0x07UL (which means TEX=000, S=1,
+ * C=1, B=1) if left undefined.  Only used by the FreeRTOS Cortex-M MPU ports, not
+ * the standard ARMv7-M Cortex-M port. */
+#define configTEX_S_C_B_FLASH                                     0x07UL
+
+/* configTEX_S_C_B_SRAM allows application writers to override the default
+ * values for the for TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for
+ * the MPU region covering RAM. Defaults to 0x07UL (which means TEX=000, S=1, C=1,
+ * B=1) if left undefined.  Only used by the FreeRTOS Cortex-M MPU ports, not
+ * the standard ARMv7-M Cortex-M port. */
+#define configTEX_S_C_B_SRAM                                      0x07UL
+
+/* Set configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY to 0 to prevent any privilege
+ * escalations originating from outside of the kernel code itself.  Set to 1 to
+ * allow application tasks to raise privilege.  Defaults to 1 if left undefined.
+ * Only used by the FreeRTOS Cortex-M MPU ports, not the standard ARMv7-M Cortex-M
+ * port.*/
+#define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY               1
+
+/* Set configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS to 1 to allow unprivileged
+ * tasks enter critical sections (effectively mask interrupts).  Set to 0 to
+ * prevent unprivileged tasks entering critical sections.  Defaults to 1 if left
+ * undefined.  Only used by the FreeRTOS Cortex-M MPU ports, not the standard
+ * ARMv7-M Cortex-M port.*/
+#define configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS                0
+
+/******************************************************************************/
+/* ARMv8-M secure side port related definitions. ******************************/
+/******************************************************************************/
+
+/* secureconfigMAX_SECURE_CONTEXTS define the maximum number of tasks that can
+ *  call into the secure side of an ARMv8-M chip.  Not used by any other ports. */
+#define secureconfigMAX_SECURE_CONTEXTS    5
+
+/******************************************************************************/
+/* Definitions that include or exclude functionality. *************************/
+/******************************************************************************/
+
+/* Set the following configUSE_* constants to 1 to include the named feature in
+ * the build, or 0 to exclude the named feature from the build. */
+#define configUSE_TASK_NOTIFICATIONS           1
+#define configUSE_MUTEXES                      1
+#define configUSE_RECURSIVE_MUTEXES            1
+#define configUSE_COUNTING_SEMAPHORES          1
+#define configUSE_QUEUE_SETS                   0
+#define configUSE_APPLICATION_TASK_TAG         0
+
+/* Set the following INCLUDE_* constants to 1 to incldue the named API function,
+ * or 0 to exclude the named API function.  Most linkers will remove unused
+ * functions even when the constant is 1. */
+#define INCLUDE_vTaskPrioritySet               1
+#define INCLUDE_uxTaskPriorityGet              1
+#define INCLUDE_vTaskDelete                    1
+#define INCLUDE_vTaskSuspend                   1
+#define INCLUDE_xResumeFromISR                 1
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         1
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       1
+#define INCLUDE_xTimerPendFunctionCall         0
+#define INCLUDE_xTaskAbortDelay                0
+#define INCLUDE_xTaskGetHandle                 0
+#define INCLUDE_xTaskResumeFromISR             1
+
+#endif /* __FREERTOS_CONFIG_H__ */
diff --git a/sample_configuration/readme.md b/sample_configuration/readme.md
new file mode 100644
index 000000000..61c81f975
--- /dev/null
+++ b/sample_configuration/readme.md
@@ -0,0 +1,7 @@
+# Configuration support for FreeRTOS
+
+## Overview
+
+Every FreeRTOS project requires FreeRTOSConfig.h located in their include path.  In this folder you will find a sample FreeRTOSConfig.h that will assist you in preparing the configuration for your application.
+
+The FreeRTOSConfig.h in this folder is used in the minimal_freertos_example project provided and it not guaranteed to have the same configuration between updates.
\ No newline at end of file

From 57f9eed00d21cbfd58dcd8f03a58f88c45f3cd9d Mon Sep 17 00:00:00 2001
From: Michael Fairman <52802839+tegimeki@users.noreply.github.com>
Date: Mon, 2 Oct 2023 23:00:33 -0700
Subject: [PATCH 074/424] bugfix: correct computation of stack size on Mac
 Posix port (#816)

Aligns the stack end to a page boundary before computing its
size, since the size depends on both the start and end.

The original change which introduced stack alignment (#674)
only worked for cases where the round + trunc operation would
wind up within the same area, but would lead to segfaults in
other cases.

Also adds a typecast to the `mach_vm_round_page()` call, as
it is actually a macro which casts to `mach_vm_offset_t` and
the result here is used as a `StackType_t` pointer.

Tested on ARM64 and Intel MacOS, as well as ARM64 and Intel
Linux.  The test code included a single-task case, as well
as a case with two tasks passing queue messages.
---
 portable/ThirdParty/GCC/Posix/port.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/portable/ThirdParty/GCC/Posix/port.c b/portable/ThirdParty/GCC/Posix/port.c
index 8ec819397..5dc3d73e2 100644
--- a/portable/ThirdParty/GCC/Posix/port.c
+++ b/portable/ThirdParty/GCC/Posix/port.c
@@ -148,10 +148,14 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
      */
     thread = ( Thread_t * ) ( pxTopOfStack + 1 ) - 1;
     pxTopOfStack = ( StackType_t * ) thread - 1;
+
+    #ifdef __APPLE__
+        pxEndOfStack = ( StackType_t * ) mach_vm_round_page( pxEndOfStack );
+    #endif
+
     ulStackSize = ( size_t ) ( pxTopOfStack + 1 - pxEndOfStack ) * sizeof( *pxTopOfStack );
 
     #ifdef __APPLE__
-        pxEndOfStack = mach_vm_round_page( pxEndOfStack );
         ulStackSize = mach_vm_trunc_page( ulStackSize );
     #endif
 

From 5cdb1bc4e1ed94468d8e81d6e70bce01a6180fbf Mon Sep 17 00:00:00 2001
From: Joseph Julicher <jjulicher@mac.com>
Date: Tue, 3 Oct 2023 10:43:45 -0700
Subject: [PATCH 075/424] removed the copyright and license header for select
 files (#815)

* removed the copyright and license header for files expected to be copied by users

* fixed a bug in the kernel checker.  temporarily restored the copyright in the sample config to allow this PR to pass the checks.

* Uncrustify: triggered by comment.

---------

Co-authored-by: GitHub Action <action@github.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
---
 .github/scripts/kernel_checker.py |  4 ++--
 portable/template/port.c          | 25 +------------------------
 portable/template/portmacro.h     | 26 ++------------------------
 3 files changed, 5 insertions(+), 50 deletions(-)

diff --git a/.github/scripts/kernel_checker.py b/.github/scripts/kernel_checker.py
index 9f23a79d8..9251c866c 100755
--- a/.github/scripts/kernel_checker.py
+++ b/.github/scripts/kernel_checker.py
@@ -38,7 +38,6 @@ KERNEL_IGNORED_FILES = [
     'Makefile',
     '.DS_Store',
     'cspell.config.yaml'
-    'FreeRTOSConfig.h'
 ]
 
 KERNEL_IGNORED_EXTENSIONS = [
@@ -94,7 +93,8 @@ KERNEL_IGNORED_PATTERNS = [
     r'.*IAR/ARM_C*',
     r'.*IAR/78K0R/*',
     r'.*CCS/MSP430X/*',
-    r'.*portable/template/*'
+    r'.*portable/template/*',
+    r'.*sample_configuration/*'
 ]
 
 KERNEL_THIRD_PARTY_PATTERNS = [
diff --git a/portable/template/port.c b/portable/template/port.c
index 5cbe72253..4011eac15 100644
--- a/portable/template/port.c
+++ b/portable/template/port.c
@@ -1,29 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
+ * license and copyright intentionally withheld to promote copying into user code.
  */
 
 #include "FreeRTOS.h"
diff --git a/portable/template/portmacro.h b/portable/template/portmacro.h
index d2dfd161e..96b400c15 100644
--- a/portable/template/portmacro.h
+++ b/portable/template/portmacro.h
@@ -1,30 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
+ * license and copyright intentionally withheld to promote copying into user code.
  */
+
 #ifndef PORTMACRO_H
 #define PORTMACRO_H
 

From 830533d49e70806b4f46dade245c2f05f0c06b0f Mon Sep 17 00:00:00 2001
From: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Date: Wed, 4 Oct 2023 17:38:27 +0800
Subject: [PATCH 076/424] Add taskYIELD_WITHIN_API macro (#782)

Add taskYIELD_WITHIN_API macro for readability improvement.
---
 event_groups.c | 20 ++------------------
 include/task.h |  6 ++++++
 queue.c        | 40 ++++------------------------------------
 tasks.c        | 32 ++++----------------------------
 timers.c       | 10 +---------
 5 files changed, 17 insertions(+), 91 deletions(-)

diff --git a/event_groups.c b/event_groups.c
index 6b68c087a..556637b4c 100644
--- a/event_groups.c
+++ b/event_groups.c
@@ -253,15 +253,7 @@ EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup,
     {
         if( xAlreadyYielded == pdFALSE )
         {
-            #if ( configNUMBER_OF_CORES == 1 )
-            {
-                portYIELD_WITHIN_API();
-            }
-            #else /* #if ( configNUMBER_OF_CORES == 1 ) */
-            {
-                vTaskYieldWithinAPI();
-            }
-            #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
+            taskYIELD_WITHIN_API();
         }
         else
         {
@@ -417,15 +409,7 @@ EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
     {
         if( xAlreadyYielded == pdFALSE )
         {
-            #if ( configNUMBER_OF_CORES == 1 )
-            {
-                portYIELD_WITHIN_API();
-            }
-            #else /* #if ( configNUMBER_OF_CORES == 1 ) */
-            {
-                vTaskYieldWithinAPI();
-            }
-            #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
+            taskYIELD_WITHIN_API();
         }
         else
         {
diff --git a/include/task.h b/include/task.h
index 8d6742c7f..448351876 100644
--- a/include/task.h
+++ b/include/task.h
@@ -3330,6 +3330,12 @@ BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) PRIVILEGED_FUNCTION;
 * SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES
 *----------------------------------------------------------*/
 
+#if ( configNUMBER_OF_CORES == 1 )
+    #define taskYIELD_WITHIN_API()    portYIELD_WITHIN_API()
+#else /* #if ( configNUMBER_OF_CORES == 1 ) */
+    #define taskYIELD_WITHIN_API()    vTaskYieldWithinAPI()
+#endif /* #if ( configNUMBER_OF_CORES == 1 ) */
+
 /*
  * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS ONLY
  * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS
diff --git a/queue.c b/queue.c
index 91b9a0d67..3bc959721 100644
--- a/queue.c
+++ b/queue.c
@@ -1129,15 +1129,7 @@ BaseType_t xQueueGenericSend( QueueHandle_t xQueue,
                  * is also a higher priority task in the pending ready list. */
                 if( xTaskResumeAll() == pdFALSE )
                 {
-                    #if ( configNUMBER_OF_CORES == 1 )
-                    {
-                        portYIELD_WITHIN_API();
-                    }
-                    #else /* #if ( configNUMBER_OF_CORES == 1 ) */
-                    {
-                        vTaskYieldWithinAPI();
-                    }
-                    #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
+                    taskYIELD_WITHIN_API();
                 }
             }
             else
@@ -1616,15 +1608,7 @@ BaseType_t xQueueReceive( QueueHandle_t xQueue,
 
                 if( xTaskResumeAll() == pdFALSE )
                 {
-                    #if ( configNUMBER_OF_CORES == 1 )
-                    {
-                        portYIELD_WITHIN_API();
-                    }
-                    #else /* #if ( configNUMBER_OF_CORES == 1 ) */
-                    {
-                        vTaskYieldWithinAPI();
-                    }
-                    #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
+                    taskYIELD_WITHIN_API();
                 }
                 else
                 {
@@ -1817,15 +1801,7 @@ BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue,
 
                 if( xTaskResumeAll() == pdFALSE )
                 {
-                    #if ( configNUMBER_OF_CORES == 1 )
-                    {
-                        portYIELD_WITHIN_API();
-                    }
-                    #else /* #if ( configNUMBER_OF_CORES == 1 ) */
-                    {
-                        vTaskYieldWithinAPI();
-                    }
-                    #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
+                    taskYIELD_WITHIN_API();
                 }
                 else
                 {
@@ -2013,15 +1989,7 @@ BaseType_t xQueuePeek( QueueHandle_t xQueue,
 
                 if( xTaskResumeAll() == pdFALSE )
                 {
-                    #if ( configNUMBER_OF_CORES == 1 )
-                    {
-                        portYIELD_WITHIN_API();
-                    }
-                    #else /* #if ( configNUMBER_OF_CORES == 1 ) */
-                    {
-                        vTaskYieldWithinAPI();
-                    }
-                    #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
+                    taskYIELD_WITHIN_API();
                 }
                 else
                 {
diff --git a/tasks.c b/tasks.c
index 84bc87bf2..000767bb5 100644
--- a/tasks.c
+++ b/tasks.c
@@ -2195,11 +2195,7 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
          * have put ourselves to sleep. */
         if( xAlreadyYielded == pdFALSE )
         {
-            #if ( configNUMBER_OF_CORES == 1 )
-                portYIELD_WITHIN_API();
-            #else
-                vTaskYieldWithinAPI();
-            #endif
+            taskYIELD_WITHIN_API();
         }
         else
         {
@@ -2251,11 +2247,7 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
          * have put ourselves to sleep. */
         if( xAlreadyYielded == pdFALSE )
         {
-            #if ( configNUMBER_OF_CORES == 1 )
-                portYIELD_WITHIN_API();
-            #else
-                vTaskYieldWithinAPI();
-            #endif
+            taskYIELD_WITHIN_API();
         }
         else
         {
@@ -7253,15 +7245,7 @@ TickType_t uxTaskResetEventItemValue( void )
                      * section (some will yield immediately, others wait until the
                      * critical section exits) - but it is not something that
                      * application code should ever do. */
-                    #if ( configNUMBER_OF_CORES == 1 )
-                    {
-                        portYIELD_WITHIN_API();
-                    }
-                    #else
-                    {
-                        vTaskYieldWithinAPI();
-                    }
-                    #endif
+                    taskYIELD_WITHIN_API();
                 }
                 else
                 {
@@ -7344,15 +7328,7 @@ TickType_t uxTaskResetEventItemValue( void )
                      * section (some will yield immediately, others wait until the
                      * critical section exits) - but it is not something that
                      * application code should ever do. */
-                    #if ( configNUMBER_OF_CORES == 1 )
-                    {
-                        portYIELD_WITHIN_API();
-                    }
-                    #else
-                    {
-                        vTaskYieldWithinAPI();
-                    }
-                    #endif
+                    taskYIELD_WITHIN_API();
                 }
                 else
                 {
diff --git a/timers.c b/timers.c
index 0d7a0c0fe..f27caba3f 100644
--- a/timers.c
+++ b/timers.c
@@ -771,15 +771,7 @@
                          * block time to expire.  If a command arrived between the
                          * critical section being exited and this yield then the yield
                          * will not cause the task to block. */
-                        #if ( configNUMBER_OF_CORES == 1 )
-                        {
-                            portYIELD_WITHIN_API();
-                        }
-                        #else /* #if ( configNUMBER_OF_CORES == 1 ) */
-                        {
-                            vTaskYieldWithinAPI();
-                        }
-                        #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
+                        taskYIELD_WITHIN_API();
                     }
                     else
                     {

From 30e13dac2bd97b7c1429cdead03406d94a83a042 Mon Sep 17 00:00:00 2001
From: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Date: Wed, 4 Oct 2023 19:33:28 +0800
Subject: [PATCH 077/424] Implement prvYieldCore with macro (#785)

* Implement prvYieldCore with macro for performance and memory
* Remove the portCHECK_IF_IN_ISR macro check. It is not required in SMP
  now

Co-authored-by: kar-rahul-aws <118818625+kar-rahul-aws@users.noreply.github.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
---
 include/FreeRTOS.h |  8 -------
 tasks.c            | 60 +++++++++++++++++++---------------------------
 2 files changed, 25 insertions(+), 43 deletions(-)

diff --git a/include/FreeRTOS.h b/include/FreeRTOS.h
index d0d63f1a2..712d8cb52 100644
--- a/include/FreeRTOS.h
+++ b/include/FreeRTOS.h
@@ -453,14 +453,6 @@
 
 #endif /* portGET_ISR_LOCK */
 
-#ifndef portCHECK_IF_IN_ISR
-
-    #if ( configNUMBER_OF_CORES > 1 )
-        #error portCHECK_IF_IN_ISR is required in SMP
-    #endif
-
-#endif /* portCHECK_IF_IN_ISR */
-
 #ifndef portENTER_CRITICAL_FROM_ISR
 
     #if ( configNUMBER_OF_CORES > 1 )
diff --git a/tasks.c b/tasks.c
index 000767bb5..e0fc15bcc 100644
--- a/tasks.c
+++ b/tasks.c
@@ -325,6 +325,31 @@
 
 #define taskBITS_PER_BYTE    ( ( size_t ) 8 )
 
+#if ( configNUMBER_OF_CORES > 1 )
+
+/* Yields the given core. This must be called from a critical section and xCoreID
+ * must be valid. This macro is not required in single core since there is only
+ * one core to yield. */
+    #define prvYieldCore( xCoreID )                                                      \
+    do {                                                                                 \
+        if( xCoreID == ( BaseType_t ) portGET_CORE_ID() )                                \
+        {                                                                                \
+            /* Pending a yield for this core since it is in the critical section. */     \
+            xYieldPendings[ xCoreID ] = pdTRUE;                                          \
+        }                                                                                \
+        else                                                                             \
+        {                                                                                \
+            /* Request other core to yield if it is not requested before. */             \
+            if( pxCurrentTCBs[ xCoreID ]->xTaskRunState != taskTASK_SCHEDULED_TO_YIELD ) \
+            {                                                                            \
+                portYIELD_CORE( xCoreID );                                               \
+                pxCurrentTCBs[ xCoreID ]->xTaskRunState = taskTASK_SCHEDULED_TO_YIELD;   \
+            }                                                                            \
+        }                                                                                \
+    } while( 0 )
+#endif /* #if ( configNUMBER_OF_CORES > 1 ) */
+/*-----------------------------------------------------------*/
+
 /*
  * Task control block.  A task control block (TCB) is allocated for each task,
  * and stores task state information, including a pointer to the task's context
@@ -527,14 +552,6 @@ static BaseType_t prvCreateIdleTasks( void );
 
 #if ( configNUMBER_OF_CORES > 1 )
 
-/*
- * Yields the given core.
- */
-    static void prvYieldCore( BaseType_t xCoreID );
-#endif /* #if ( configNUMBER_OF_CORES > 1 ) */
-
-#if ( configNUMBER_OF_CORES > 1 )
-
 /*
  * Yields a core, or cores if multiple priorities are not allowed to run
  * simultaneously, to allow the task pxTCB to run.
@@ -811,33 +828,6 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
 
 /*-----------------------------------------------------------*/
 
-#if ( configNUMBER_OF_CORES > 1 )
-    static void prvYieldCore( BaseType_t xCoreID )
-    {
-        /* This must be called from a critical section and xCoreID must be valid. */
-        if( ( portCHECK_IF_IN_ISR() == pdTRUE ) && ( xCoreID == ( BaseType_t ) portGET_CORE_ID() ) )
-        {
-            xYieldPendings[ xCoreID ] = pdTRUE;
-        }
-        else
-        {
-            if( pxCurrentTCBs[ xCoreID ]->xTaskRunState != taskTASK_SCHEDULED_TO_YIELD )
-            {
-                if( xCoreID == ( BaseType_t ) portGET_CORE_ID() )
-                {
-                    xYieldPendings[ xCoreID ] = pdTRUE;
-                }
-                else
-                {
-                    portYIELD_CORE( xCoreID );
-                    pxCurrentTCBs[ xCoreID ]->xTaskRunState = taskTASK_SCHEDULED_TO_YIELD;
-                }
-            }
-        }
-    }
-#endif /* #if ( configNUMBER_OF_CORES > 1 ) */
-/*-----------------------------------------------------------*/
-
 #if ( configNUMBER_OF_CORES > 1 )
     static void prvYieldForTask( const TCB_t * pxTCB )
     {

From 317bc0c89c2b8b1a8b01fcec83827092993e1e30 Mon Sep 17 00:00:00 2001
From: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Date: Thu, 5 Oct 2023 14:46:38 +0800
Subject: [PATCH 078/424] Move trace macro after declaration (#820)

* Move trace macro after declaration to comply with ISO C90
---
 tasks.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/tasks.c b/tasks.c
index e0fc15bcc..bea306ea5 100644
--- a/tasks.c
+++ b/tasks.c
@@ -2462,12 +2462,12 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
         UBaseType_t uxCurrentBasePriority, uxPriorityUsedOnEntry;
         BaseType_t xYieldRequired = pdFALSE;
 
-        traceENTER_vTaskPrioritySet( xTask, uxNewPriority );
-
         #if ( configNUMBER_OF_CORES > 1 )
             BaseType_t xYieldForTask = pdFALSE;
         #endif
 
+        traceENTER_vTaskPrioritySet( xTask, uxNewPriority );
+
         configASSERT( uxNewPriority < configMAX_PRIORITIES );
 
         /* Ensure the new priority is valid. */
@@ -4376,12 +4376,12 @@ BaseType_t xTaskIncrementTick( void )
     TickType_t xItemValue;
     BaseType_t xSwitchRequired = pdFALSE;
 
-    traceENTER_xTaskIncrementTick();
-
     #if ( configUSE_PREEMPTION == 1 ) && ( configNUMBER_OF_CORES > 1 )
     BaseType_t xYieldRequiredForCore[ configNUMBER_OF_CORES ] = { pdFALSE };
     #endif /* #if ( configUSE_PREEMPTION == 1 ) && ( configNUMBER_OF_CORES > 1 ) */
 
+    traceENTER_xTaskIncrementTick();
+
     /* Called by the portable layer each time a tick interrupt occurs.
      * Increments the tick then checks to see if the new tick value will cause any
      * tasks to be unblocked. */
@@ -5566,10 +5566,10 @@ static portTASK_FUNCTION( prvIdleTask, pvParameters )
             const UBaseType_t uxNonApplicationTasks = 1;
         #endif /* INCLUDE_vTaskSuspend */
 
-        traceENTER_eTaskConfirmSleepModeStatus();
-
         eSleepModeStatus eReturn = eStandardSleep;
 
+        traceENTER_eTaskConfirmSleepModeStatus();
+
         /* This function must be called from a critical section. */
 
         if( listCURRENT_LIST_LENGTH( &xPendingReadyList ) != 0 )

From 97d48ba94a3e22a98e4e2fd3cc6d77ab9c5d2134 Mon Sep 17 00:00:00 2001
From: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Date: Thu, 5 Oct 2023 15:39:24 +0800
Subject: [PATCH 079/424] Add more comment for core affinity in
 prvSelectHighestPriorityTask (#801)

* Add more comment for core affinity in prvSelectHighestPriorityTask

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: kar-rahul-aws <118818625+kar-rahul-aws@users.noreply.github.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 tasks.c | 27 +++++++++++++++++++++------
 1 file changed, 21 insertions(+), 6 deletions(-)

diff --git a/tasks.c b/tasks.c
index bea306ea5..c8a8cdea3 100644
--- a/tasks.c
+++ b/tasks.c
@@ -1134,16 +1134,31 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
 
                     if( ( uxCoreMap & ( ( UBaseType_t ) 1U << ( UBaseType_t ) xCoreID ) ) != 0U )
                     {
-                        /* The ready task that was removed from this core is not excluded from it.
-                         * Only look at the intersection of the cores the removed task is allowed to run
-                         * on with the cores that the new task is excluded from. It is possible that the
-                         * new task was only placed onto this core because it is excluded from another.
-                         * Check to see if the previous task could run on one of those cores. */
+                        /* pxPreviousTCB was removed from this core and this core is not excluded
+                         * from it's core affinity mask.
+                         *
+                         * pxPreviousTCB is preempted by the new higher priority task
+                         * pxCurrentTCBs[ xCoreID ]. When searching a new core for pxPreviousTCB,
+                         * we do not need to look at the cores on which pxCurrentTCBs[ xCoreID ]
+                         * is allowed to run. The reason is - when more than one cores are
+                         * eligible for an incoming task, we preempt the core with the minimum
+                         * priority task. Because this core (i.e. xCoreID) was preempted for
+                         * pxCurrentTCBs[ xCoreID ], this means that all the others cores
+                         * where pxCurrentTCBs[ xCoreID ] can run, are running tasks with priority
+                         * no lower than pxPreviousTCB's priority. Therefore, the only cores where
+                         * which can be preempted for pxPreviousTCB are the ones where
+                         * pxCurrentTCBs[ xCoreID ] is not allowed to run (and obviously,
+                         * pxPreviousTCB is allowed to run).
+                         *
+                         * This is an optimization which reduces the number of cores needed to be
+                         * searched for pxPreviousTCB to run. */
                         uxCoreMap &= ~( pxCurrentTCBs[ xCoreID ]->uxCoreAffinityMask );
                     }
                     else
                     {
-                        /* The ready task that was removed from this core is excluded from it. */
+                        /* pxPreviousTCB's core affinity mask is changed and it is no longer
+                         * allowed to run on this core. Searching all the cores in pxPreviousTCB's
+                         * new core affinity mask to find a core on which it can run. */
                     }
 
                     uxCoreMap &= ( ( 1U << configNUMBER_OF_CORES ) - 1U );

From d442d7908af72dfda220e0f44721f1e5425b6087 Mon Sep 17 00:00:00 2001
From: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Date: Thu, 5 Oct 2023 16:57:53 +0800
Subject: [PATCH 080/424] Add configCONTROL_INFINITE_LOOP for loop control in
 unit test (#783)

* Add configCONTROL_INFINITE_LOOP in FreeRTOS.h
* Use configCONTROL_INFINITE_LOOP in tasks.c and timer.c

---------

Co-authored-by: Soren Ptak <ptaksoren@gmail.com>
Co-authored-by: kar-rahul-aws <118818625+kar-rahul-aws@users.noreply.github.com>
---
 include/FreeRTOS.h |  6 ++++++
 tasks.c            | 10 ++--------
 timers.c           |  2 +-
 3 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/include/FreeRTOS.h b/include/FreeRTOS.h
index 712d8cb52..f57586375 100644
--- a/include/FreeRTOS.h
+++ b/include/FreeRTOS.h
@@ -2872,6 +2872,12 @@
     #define configRUN_ADDITIONAL_TESTS    0
 #endif
 
+/* The following config allows infinite loop control. For example, control the
+ * infinite loop in idle task function when performing unit tests. */
+#ifndef configCONTROL_INFINITE_LOOP
+    #define configCONTROL_INFINITE_LOOP()
+#endif
+
 /* Sometimes the FreeRTOSConfig.h settings only allow a task to be created using
  * dynamically allocated RAM, in which case when any task is deleted it is known
  * that both the task's stack and TCB need to be freed.  Sometimes the
diff --git a/tasks.c b/tasks.c
index c8a8cdea3..48c1960aa 100644
--- a/tasks.c
+++ b/tasks.c
@@ -317,12 +317,6 @@
     #define portDECREMENT_CRITICAL_NESTING_COUNT()    ( pxCurrentTCBs[ portGET_CORE_ID() ]->uxCriticalNesting-- )
 #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( portCRITICAL_NESTING_IN_TCB == 1 ) ) */
 
-/* Code below here allows infinite loop controlling, especially for the infinite loop
- * in idle task function (for example when performing unit tests). */
-#ifndef INFINITE_LOOP
-    #define INFINITE_LOOP()    1
-#endif
-
 #define taskBITS_PER_BYTE    ( ( size_t ) 8 )
 
 #if ( configNUMBER_OF_CORES > 1 )
@@ -5374,7 +5368,7 @@ void vTaskMissedYield( void )
 
         taskYIELD();
 
-        for( ; INFINITE_LOOP(); )
+        for( ; configCONTROL_INFINITE_LOOP(); )
         {
             #if ( configUSE_PREEMPTION == 0 )
             {
@@ -5459,7 +5453,7 @@ static portTASK_FUNCTION( prvIdleTask, pvParameters )
     }
     #endif /* #if ( configNUMBER_OF_CORES > 1 ) */
 
-    for( ; INFINITE_LOOP(); )
+    for( ; configCONTROL_INFINITE_LOOP(); )
     {
         /* See if any tasks have deleted themselves - if so then the idle task
          * is responsible for freeing the deleted task's TCB and stack. */
diff --git a/timers.c b/timers.c
index f27caba3f..e2f3f9809 100644
--- a/timers.c
+++ b/timers.c
@@ -709,7 +709,7 @@
         }
         #endif /* configUSE_DAEMON_TASK_STARTUP_HOOK */
 
-        for( ; ; )
+        for( ; configCONTROL_INFINITE_LOOP(); )
         {
             /* Query the timers list to see if it contains any timers, and if so,
              * obtain the time at which the next timer will expire. */

From 3d575b58a42b9c1618d91bfb8f44ceac5ba7a6fa Mon Sep 17 00:00:00 2001
From: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Date: Fri, 6 Oct 2023 10:22:06 +0530
Subject: [PATCH 081/424] Make taskYIELD available to unprivileged tasks (#817)

Make taskYIELD available to unprivileged tasks on ARMv8-M
ports.
---
 portable/ARMv8M/non_secure/port.c                      |  6 ++++++
 portable/ARMv8M/non_secure/portmacrocommon.h           | 10 +++++++++-
 portable/GCC/ARM_CM23/non_secure/port.c                |  6 ++++++
 portable/GCC/ARM_CM23/non_secure/portmacrocommon.h     | 10 +++++++++-
 portable/GCC/ARM_CM23_NTZ/non_secure/port.c            |  6 ++++++
 portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h | 10 +++++++++-
 portable/GCC/ARM_CM33/non_secure/port.c                |  6 ++++++
 portable/GCC/ARM_CM33/non_secure/portmacrocommon.h     | 10 +++++++++-
 portable/GCC/ARM_CM33_NTZ/non_secure/port.c            |  6 ++++++
 portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h | 10 +++++++++-
 portable/GCC/ARM_CM35P/non_secure/port.c               |  6 ++++++
 portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h    | 10 +++++++++-
 portable/GCC/ARM_CM35P_NTZ/non_secure/port.c           |  6 ++++++
 .../GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h     | 10 +++++++++-
 portable/GCC/ARM_CM55/non_secure/port.c                |  6 ++++++
 portable/GCC/ARM_CM55/non_secure/portmacrocommon.h     | 10 +++++++++-
 portable/GCC/ARM_CM55_NTZ/non_secure/port.c            |  6 ++++++
 portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h | 10 +++++++++-
 portable/GCC/ARM_CM85/non_secure/port.c                |  6 ++++++
 portable/GCC/ARM_CM85/non_secure/portmacrocommon.h     | 10 +++++++++-
 portable/GCC/ARM_CM85_NTZ/non_secure/port.c            |  6 ++++++
 portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h | 10 +++++++++-
 portable/IAR/ARM_CM23/non_secure/port.c                |  6 ++++++
 portable/IAR/ARM_CM23/non_secure/portmacrocommon.h     | 10 +++++++++-
 portable/IAR/ARM_CM23_NTZ/non_secure/port.c            |  6 ++++++
 portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h | 10 +++++++++-
 portable/IAR/ARM_CM33/non_secure/port.c                |  6 ++++++
 portable/IAR/ARM_CM33/non_secure/portmacrocommon.h     | 10 +++++++++-
 portable/IAR/ARM_CM33_NTZ/non_secure/port.c            |  6 ++++++
 portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h | 10 +++++++++-
 portable/IAR/ARM_CM35P/non_secure/port.c               |  6 ++++++
 portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h    | 10 +++++++++-
 portable/IAR/ARM_CM35P_NTZ/non_secure/port.c           |  6 ++++++
 .../IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h     | 10 +++++++++-
 portable/IAR/ARM_CM55/non_secure/port.c                |  6 ++++++
 portable/IAR/ARM_CM55/non_secure/portmacrocommon.h     | 10 +++++++++-
 portable/IAR/ARM_CM55_NTZ/non_secure/port.c            |  6 ++++++
 portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h | 10 +++++++++-
 portable/IAR/ARM_CM85/non_secure/port.c                |  6 ++++++
 portable/IAR/ARM_CM85/non_secure/portmacrocommon.h     | 10 +++++++++-
 portable/IAR/ARM_CM85_NTZ/non_secure/port.c            |  6 ++++++
 portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h | 10 +++++++++-
 42 files changed, 315 insertions(+), 21 deletions(-)

diff --git a/portable/ARMv8M/non_secure/port.c b/portable/ARMv8M/non_secure/port.c
index 0c5b76488..52d68d3ea 100644
--- a/portable/ARMv8M/non_secure/port.c
+++ b/portable/ARMv8M/non_secure/port.c
@@ -1118,6 +1118,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                     break;
             #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
+            #if ( configENABLE_MPU == 1 )
+                case portSVC_YIELD:
+                    vPortYield();
+                    break;
+            #endif /* configENABLE_MPU == 1 */
+
         default:
             /* Incorrect SVC call. */
             configASSERT( pdFALSE );
diff --git a/portable/ARMv8M/non_secure/portmacrocommon.h b/portable/ARMv8M/non_secure/portmacrocommon.h
index 6b389735a..60ef37380 100644
--- a/portable/ARMv8M/non_secure/portmacrocommon.h
+++ b/portable/ARMv8M/non_secure/portmacrocommon.h
@@ -329,12 +329,20 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portSVC_SYSTEM_CALL_ENTER          4   /* System calls with upto 4 parameters. */
 #define portSVC_SYSTEM_CALL_ENTER_1        5   /* System calls with 5 parameters. */
 #define portSVC_SYSTEM_CALL_EXIT           6
+#define portSVC_YIELD                      7
 /*-----------------------------------------------------------*/
 
 /**
  * @brief Scheduler utilities.
  */
-#define portYIELD()    vPortYield()
+#if ( configENABLE_MPU == 1 )
+    #define portYIELD()               __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" )
+    #define portYIELD_WITHIN_API()    vPortYield()
+#else
+    #define portYIELD()               vPortYield()
+    #define portYIELD_WITHIN_API()    vPortYield()
+#endif
+
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
 #define portEND_SWITCHING_ISR( xSwitchRequired )            \
diff --git a/portable/GCC/ARM_CM23/non_secure/port.c b/portable/GCC/ARM_CM23/non_secure/port.c
index 0c5b76488..52d68d3ea 100644
--- a/portable/GCC/ARM_CM23/non_secure/port.c
+++ b/portable/GCC/ARM_CM23/non_secure/port.c
@@ -1118,6 +1118,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                     break;
             #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
+            #if ( configENABLE_MPU == 1 )
+                case portSVC_YIELD:
+                    vPortYield();
+                    break;
+            #endif /* configENABLE_MPU == 1 */
+
         default:
             /* Incorrect SVC call. */
             configASSERT( pdFALSE );
diff --git a/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h
index 6b389735a..60ef37380 100644
--- a/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h
@@ -329,12 +329,20 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portSVC_SYSTEM_CALL_ENTER          4   /* System calls with upto 4 parameters. */
 #define portSVC_SYSTEM_CALL_ENTER_1        5   /* System calls with 5 parameters. */
 #define portSVC_SYSTEM_CALL_EXIT           6
+#define portSVC_YIELD                      7
 /*-----------------------------------------------------------*/
 
 /**
  * @brief Scheduler utilities.
  */
-#define portYIELD()    vPortYield()
+#if ( configENABLE_MPU == 1 )
+    #define portYIELD()               __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" )
+    #define portYIELD_WITHIN_API()    vPortYield()
+#else
+    #define portYIELD()               vPortYield()
+    #define portYIELD_WITHIN_API()    vPortYield()
+#endif
+
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
 #define portEND_SWITCHING_ISR( xSwitchRequired )            \
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
index 0c5b76488..52d68d3ea 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
@@ -1118,6 +1118,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                     break;
             #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
+            #if ( configENABLE_MPU == 1 )
+                case portSVC_YIELD:
+                    vPortYield();
+                    break;
+            #endif /* configENABLE_MPU == 1 */
+
         default:
             /* Incorrect SVC call. */
             configASSERT( pdFALSE );
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h
index 6b389735a..60ef37380 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h
@@ -329,12 +329,20 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portSVC_SYSTEM_CALL_ENTER          4   /* System calls with upto 4 parameters. */
 #define portSVC_SYSTEM_CALL_ENTER_1        5   /* System calls with 5 parameters. */
 #define portSVC_SYSTEM_CALL_EXIT           6
+#define portSVC_YIELD                      7
 /*-----------------------------------------------------------*/
 
 /**
  * @brief Scheduler utilities.
  */
-#define portYIELD()    vPortYield()
+#if ( configENABLE_MPU == 1 )
+    #define portYIELD()               __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" )
+    #define portYIELD_WITHIN_API()    vPortYield()
+#else
+    #define portYIELD()               vPortYield()
+    #define portYIELD_WITHIN_API()    vPortYield()
+#endif
+
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
 #define portEND_SWITCHING_ISR( xSwitchRequired )            \
diff --git a/portable/GCC/ARM_CM33/non_secure/port.c b/portable/GCC/ARM_CM33/non_secure/port.c
index 0c5b76488..52d68d3ea 100644
--- a/portable/GCC/ARM_CM33/non_secure/port.c
+++ b/portable/GCC/ARM_CM33/non_secure/port.c
@@ -1118,6 +1118,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                     break;
             #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
+            #if ( configENABLE_MPU == 1 )
+                case portSVC_YIELD:
+                    vPortYield();
+                    break;
+            #endif /* configENABLE_MPU == 1 */
+
         default:
             /* Incorrect SVC call. */
             configASSERT( pdFALSE );
diff --git a/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h
index 6b389735a..60ef37380 100644
--- a/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h
@@ -329,12 +329,20 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portSVC_SYSTEM_CALL_ENTER          4   /* System calls with upto 4 parameters. */
 #define portSVC_SYSTEM_CALL_ENTER_1        5   /* System calls with 5 parameters. */
 #define portSVC_SYSTEM_CALL_EXIT           6
+#define portSVC_YIELD                      7
 /*-----------------------------------------------------------*/
 
 /**
  * @brief Scheduler utilities.
  */
-#define portYIELD()    vPortYield()
+#if ( configENABLE_MPU == 1 )
+    #define portYIELD()               __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" )
+    #define portYIELD_WITHIN_API()    vPortYield()
+#else
+    #define portYIELD()               vPortYield()
+    #define portYIELD_WITHIN_API()    vPortYield()
+#endif
+
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
 #define portEND_SWITCHING_ISR( xSwitchRequired )            \
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
index 0c5b76488..52d68d3ea 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
@@ -1118,6 +1118,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                     break;
             #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
+            #if ( configENABLE_MPU == 1 )
+                case portSVC_YIELD:
+                    vPortYield();
+                    break;
+            #endif /* configENABLE_MPU == 1 */
+
         default:
             /* Incorrect SVC call. */
             configASSERT( pdFALSE );
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h
index 6b389735a..60ef37380 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h
@@ -329,12 +329,20 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portSVC_SYSTEM_CALL_ENTER          4   /* System calls with upto 4 parameters. */
 #define portSVC_SYSTEM_CALL_ENTER_1        5   /* System calls with 5 parameters. */
 #define portSVC_SYSTEM_CALL_EXIT           6
+#define portSVC_YIELD                      7
 /*-----------------------------------------------------------*/
 
 /**
  * @brief Scheduler utilities.
  */
-#define portYIELD()    vPortYield()
+#if ( configENABLE_MPU == 1 )
+    #define portYIELD()               __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" )
+    #define portYIELD_WITHIN_API()    vPortYield()
+#else
+    #define portYIELD()               vPortYield()
+    #define portYIELD_WITHIN_API()    vPortYield()
+#endif
+
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
 #define portEND_SWITCHING_ISR( xSwitchRequired )            \
diff --git a/portable/GCC/ARM_CM35P/non_secure/port.c b/portable/GCC/ARM_CM35P/non_secure/port.c
index 0c5b76488..52d68d3ea 100644
--- a/portable/GCC/ARM_CM35P/non_secure/port.c
+++ b/portable/GCC/ARM_CM35P/non_secure/port.c
@@ -1118,6 +1118,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                     break;
             #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
+            #if ( configENABLE_MPU == 1 )
+                case portSVC_YIELD:
+                    vPortYield();
+                    break;
+            #endif /* configENABLE_MPU == 1 */
+
         default:
             /* Incorrect SVC call. */
             configASSERT( pdFALSE );
diff --git a/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h
index 6b389735a..60ef37380 100644
--- a/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h
@@ -329,12 +329,20 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portSVC_SYSTEM_CALL_ENTER          4   /* System calls with upto 4 parameters. */
 #define portSVC_SYSTEM_CALL_ENTER_1        5   /* System calls with 5 parameters. */
 #define portSVC_SYSTEM_CALL_EXIT           6
+#define portSVC_YIELD                      7
 /*-----------------------------------------------------------*/
 
 /**
  * @brief Scheduler utilities.
  */
-#define portYIELD()    vPortYield()
+#if ( configENABLE_MPU == 1 )
+    #define portYIELD()               __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" )
+    #define portYIELD_WITHIN_API()    vPortYield()
+#else
+    #define portYIELD()               vPortYield()
+    #define portYIELD_WITHIN_API()    vPortYield()
+#endif
+
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
 #define portEND_SWITCHING_ISR( xSwitchRequired )            \
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c b/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
index 0c5b76488..52d68d3ea 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
@@ -1118,6 +1118,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                     break;
             #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
+            #if ( configENABLE_MPU == 1 )
+                case portSVC_YIELD:
+                    vPortYield();
+                    break;
+            #endif /* configENABLE_MPU == 1 */
+
         default:
             /* Incorrect SVC call. */
             configASSERT( pdFALSE );
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
index 6b389735a..60ef37380 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
@@ -329,12 +329,20 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portSVC_SYSTEM_CALL_ENTER          4   /* System calls with upto 4 parameters. */
 #define portSVC_SYSTEM_CALL_ENTER_1        5   /* System calls with 5 parameters. */
 #define portSVC_SYSTEM_CALL_EXIT           6
+#define portSVC_YIELD                      7
 /*-----------------------------------------------------------*/
 
 /**
  * @brief Scheduler utilities.
  */
-#define portYIELD()    vPortYield()
+#if ( configENABLE_MPU == 1 )
+    #define portYIELD()               __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" )
+    #define portYIELD_WITHIN_API()    vPortYield()
+#else
+    #define portYIELD()               vPortYield()
+    #define portYIELD_WITHIN_API()    vPortYield()
+#endif
+
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
 #define portEND_SWITCHING_ISR( xSwitchRequired )            \
diff --git a/portable/GCC/ARM_CM55/non_secure/port.c b/portable/GCC/ARM_CM55/non_secure/port.c
index 0c5b76488..52d68d3ea 100644
--- a/portable/GCC/ARM_CM55/non_secure/port.c
+++ b/portable/GCC/ARM_CM55/non_secure/port.c
@@ -1118,6 +1118,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                     break;
             #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
+            #if ( configENABLE_MPU == 1 )
+                case portSVC_YIELD:
+                    vPortYield();
+                    break;
+            #endif /* configENABLE_MPU == 1 */
+
         default:
             /* Incorrect SVC call. */
             configASSERT( pdFALSE );
diff --git a/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h
index 6b389735a..60ef37380 100644
--- a/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h
@@ -329,12 +329,20 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portSVC_SYSTEM_CALL_ENTER          4   /* System calls with upto 4 parameters. */
 #define portSVC_SYSTEM_CALL_ENTER_1        5   /* System calls with 5 parameters. */
 #define portSVC_SYSTEM_CALL_EXIT           6
+#define portSVC_YIELD                      7
 /*-----------------------------------------------------------*/
 
 /**
  * @brief Scheduler utilities.
  */
-#define portYIELD()    vPortYield()
+#if ( configENABLE_MPU == 1 )
+    #define portYIELD()               __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" )
+    #define portYIELD_WITHIN_API()    vPortYield()
+#else
+    #define portYIELD()               vPortYield()
+    #define portYIELD_WITHIN_API()    vPortYield()
+#endif
+
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
 #define portEND_SWITCHING_ISR( xSwitchRequired )            \
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/port.c b/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
index 0c5b76488..52d68d3ea 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
@@ -1118,6 +1118,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                     break;
             #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
+            #if ( configENABLE_MPU == 1 )
+                case portSVC_YIELD:
+                    vPortYield();
+                    break;
+            #endif /* configENABLE_MPU == 1 */
+
         default:
             /* Incorrect SVC call. */
             configASSERT( pdFALSE );
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h
index 6b389735a..60ef37380 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h
@@ -329,12 +329,20 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portSVC_SYSTEM_CALL_ENTER          4   /* System calls with upto 4 parameters. */
 #define portSVC_SYSTEM_CALL_ENTER_1        5   /* System calls with 5 parameters. */
 #define portSVC_SYSTEM_CALL_EXIT           6
+#define portSVC_YIELD                      7
 /*-----------------------------------------------------------*/
 
 /**
  * @brief Scheduler utilities.
  */
-#define portYIELD()    vPortYield()
+#if ( configENABLE_MPU == 1 )
+    #define portYIELD()               __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" )
+    #define portYIELD_WITHIN_API()    vPortYield()
+#else
+    #define portYIELD()               vPortYield()
+    #define portYIELD_WITHIN_API()    vPortYield()
+#endif
+
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
 #define portEND_SWITCHING_ISR( xSwitchRequired )            \
diff --git a/portable/GCC/ARM_CM85/non_secure/port.c b/portable/GCC/ARM_CM85/non_secure/port.c
index 0c5b76488..52d68d3ea 100644
--- a/portable/GCC/ARM_CM85/non_secure/port.c
+++ b/portable/GCC/ARM_CM85/non_secure/port.c
@@ -1118,6 +1118,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                     break;
             #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
+            #if ( configENABLE_MPU == 1 )
+                case portSVC_YIELD:
+                    vPortYield();
+                    break;
+            #endif /* configENABLE_MPU == 1 */
+
         default:
             /* Incorrect SVC call. */
             configASSERT( pdFALSE );
diff --git a/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h
index 6b389735a..60ef37380 100644
--- a/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h
@@ -329,12 +329,20 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portSVC_SYSTEM_CALL_ENTER          4   /* System calls with upto 4 parameters. */
 #define portSVC_SYSTEM_CALL_ENTER_1        5   /* System calls with 5 parameters. */
 #define portSVC_SYSTEM_CALL_EXIT           6
+#define portSVC_YIELD                      7
 /*-----------------------------------------------------------*/
 
 /**
  * @brief Scheduler utilities.
  */
-#define portYIELD()    vPortYield()
+#if ( configENABLE_MPU == 1 )
+    #define portYIELD()               __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" )
+    #define portYIELD_WITHIN_API()    vPortYield()
+#else
+    #define portYIELD()               vPortYield()
+    #define portYIELD_WITHIN_API()    vPortYield()
+#endif
+
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
 #define portEND_SWITCHING_ISR( xSwitchRequired )            \
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/port.c b/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
index 0c5b76488..52d68d3ea 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
@@ -1118,6 +1118,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                     break;
             #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
+            #if ( configENABLE_MPU == 1 )
+                case portSVC_YIELD:
+                    vPortYield();
+                    break;
+            #endif /* configENABLE_MPU == 1 */
+
         default:
             /* Incorrect SVC call. */
             configASSERT( pdFALSE );
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h
index 6b389735a..60ef37380 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h
@@ -329,12 +329,20 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portSVC_SYSTEM_CALL_ENTER          4   /* System calls with upto 4 parameters. */
 #define portSVC_SYSTEM_CALL_ENTER_1        5   /* System calls with 5 parameters. */
 #define portSVC_SYSTEM_CALL_EXIT           6
+#define portSVC_YIELD                      7
 /*-----------------------------------------------------------*/
 
 /**
  * @brief Scheduler utilities.
  */
-#define portYIELD()    vPortYield()
+#if ( configENABLE_MPU == 1 )
+    #define portYIELD()               __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" )
+    #define portYIELD_WITHIN_API()    vPortYield()
+#else
+    #define portYIELD()               vPortYield()
+    #define portYIELD_WITHIN_API()    vPortYield()
+#endif
+
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
 #define portEND_SWITCHING_ISR( xSwitchRequired )            \
diff --git a/portable/IAR/ARM_CM23/non_secure/port.c b/portable/IAR/ARM_CM23/non_secure/port.c
index 0c5b76488..52d68d3ea 100644
--- a/portable/IAR/ARM_CM23/non_secure/port.c
+++ b/portable/IAR/ARM_CM23/non_secure/port.c
@@ -1118,6 +1118,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                     break;
             #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
+            #if ( configENABLE_MPU == 1 )
+                case portSVC_YIELD:
+                    vPortYield();
+                    break;
+            #endif /* configENABLE_MPU == 1 */
+
         default:
             /* Incorrect SVC call. */
             configASSERT( pdFALSE );
diff --git a/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h
index 6b389735a..60ef37380 100644
--- a/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h
@@ -329,12 +329,20 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portSVC_SYSTEM_CALL_ENTER          4   /* System calls with upto 4 parameters. */
 #define portSVC_SYSTEM_CALL_ENTER_1        5   /* System calls with 5 parameters. */
 #define portSVC_SYSTEM_CALL_EXIT           6
+#define portSVC_YIELD                      7
 /*-----------------------------------------------------------*/
 
 /**
  * @brief Scheduler utilities.
  */
-#define portYIELD()    vPortYield()
+#if ( configENABLE_MPU == 1 )
+    #define portYIELD()               __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" )
+    #define portYIELD_WITHIN_API()    vPortYield()
+#else
+    #define portYIELD()               vPortYield()
+    #define portYIELD_WITHIN_API()    vPortYield()
+#endif
+
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
 #define portEND_SWITCHING_ISR( xSwitchRequired )            \
diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
index 0c5b76488..52d68d3ea 100644
--- a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
@@ -1118,6 +1118,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                     break;
             #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
+            #if ( configENABLE_MPU == 1 )
+                case portSVC_YIELD:
+                    vPortYield();
+                    break;
+            #endif /* configENABLE_MPU == 1 */
+
         default:
             /* Incorrect SVC call. */
             configASSERT( pdFALSE );
diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h
index 6b389735a..60ef37380 100644
--- a/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h
@@ -329,12 +329,20 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portSVC_SYSTEM_CALL_ENTER          4   /* System calls with upto 4 parameters. */
 #define portSVC_SYSTEM_CALL_ENTER_1        5   /* System calls with 5 parameters. */
 #define portSVC_SYSTEM_CALL_EXIT           6
+#define portSVC_YIELD                      7
 /*-----------------------------------------------------------*/
 
 /**
  * @brief Scheduler utilities.
  */
-#define portYIELD()    vPortYield()
+#if ( configENABLE_MPU == 1 )
+    #define portYIELD()               __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" )
+    #define portYIELD_WITHIN_API()    vPortYield()
+#else
+    #define portYIELD()               vPortYield()
+    #define portYIELD_WITHIN_API()    vPortYield()
+#endif
+
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
 #define portEND_SWITCHING_ISR( xSwitchRequired )            \
diff --git a/portable/IAR/ARM_CM33/non_secure/port.c b/portable/IAR/ARM_CM33/non_secure/port.c
index 0c5b76488..52d68d3ea 100644
--- a/portable/IAR/ARM_CM33/non_secure/port.c
+++ b/portable/IAR/ARM_CM33/non_secure/port.c
@@ -1118,6 +1118,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                     break;
             #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
+            #if ( configENABLE_MPU == 1 )
+                case portSVC_YIELD:
+                    vPortYield();
+                    break;
+            #endif /* configENABLE_MPU == 1 */
+
         default:
             /* Incorrect SVC call. */
             configASSERT( pdFALSE );
diff --git a/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h
index 6b389735a..60ef37380 100644
--- a/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h
@@ -329,12 +329,20 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portSVC_SYSTEM_CALL_ENTER          4   /* System calls with upto 4 parameters. */
 #define portSVC_SYSTEM_CALL_ENTER_1        5   /* System calls with 5 parameters. */
 #define portSVC_SYSTEM_CALL_EXIT           6
+#define portSVC_YIELD                      7
 /*-----------------------------------------------------------*/
 
 /**
  * @brief Scheduler utilities.
  */
-#define portYIELD()    vPortYield()
+#if ( configENABLE_MPU == 1 )
+    #define portYIELD()               __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" )
+    #define portYIELD_WITHIN_API()    vPortYield()
+#else
+    #define portYIELD()               vPortYield()
+    #define portYIELD_WITHIN_API()    vPortYield()
+#endif
+
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
 #define portEND_SWITCHING_ISR( xSwitchRequired )            \
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
index 0c5b76488..52d68d3ea 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
@@ -1118,6 +1118,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                     break;
             #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
+            #if ( configENABLE_MPU == 1 )
+                case portSVC_YIELD:
+                    vPortYield();
+                    break;
+            #endif /* configENABLE_MPU == 1 */
+
         default:
             /* Incorrect SVC call. */
             configASSERT( pdFALSE );
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h
index 6b389735a..60ef37380 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h
@@ -329,12 +329,20 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portSVC_SYSTEM_CALL_ENTER          4   /* System calls with upto 4 parameters. */
 #define portSVC_SYSTEM_CALL_ENTER_1        5   /* System calls with 5 parameters. */
 #define portSVC_SYSTEM_CALL_EXIT           6
+#define portSVC_YIELD                      7
 /*-----------------------------------------------------------*/
 
 /**
  * @brief Scheduler utilities.
  */
-#define portYIELD()    vPortYield()
+#if ( configENABLE_MPU == 1 )
+    #define portYIELD()               __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" )
+    #define portYIELD_WITHIN_API()    vPortYield()
+#else
+    #define portYIELD()               vPortYield()
+    #define portYIELD_WITHIN_API()    vPortYield()
+#endif
+
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
 #define portEND_SWITCHING_ISR( xSwitchRequired )            \
diff --git a/portable/IAR/ARM_CM35P/non_secure/port.c b/portable/IAR/ARM_CM35P/non_secure/port.c
index 0c5b76488..52d68d3ea 100644
--- a/portable/IAR/ARM_CM35P/non_secure/port.c
+++ b/portable/IAR/ARM_CM35P/non_secure/port.c
@@ -1118,6 +1118,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                     break;
             #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
+            #if ( configENABLE_MPU == 1 )
+                case portSVC_YIELD:
+                    vPortYield();
+                    break;
+            #endif /* configENABLE_MPU == 1 */
+
         default:
             /* Incorrect SVC call. */
             configASSERT( pdFALSE );
diff --git a/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h
index 6b389735a..60ef37380 100644
--- a/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h
@@ -329,12 +329,20 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portSVC_SYSTEM_CALL_ENTER          4   /* System calls with upto 4 parameters. */
 #define portSVC_SYSTEM_CALL_ENTER_1        5   /* System calls with 5 parameters. */
 #define portSVC_SYSTEM_CALL_EXIT           6
+#define portSVC_YIELD                      7
 /*-----------------------------------------------------------*/
 
 /**
  * @brief Scheduler utilities.
  */
-#define portYIELD()    vPortYield()
+#if ( configENABLE_MPU == 1 )
+    #define portYIELD()               __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" )
+    #define portYIELD_WITHIN_API()    vPortYield()
+#else
+    #define portYIELD()               vPortYield()
+    #define portYIELD_WITHIN_API()    vPortYield()
+#endif
+
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
 #define portEND_SWITCHING_ISR( xSwitchRequired )            \
diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c b/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
index 0c5b76488..52d68d3ea 100644
--- a/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
@@ -1118,6 +1118,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                     break;
             #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
+            #if ( configENABLE_MPU == 1 )
+                case portSVC_YIELD:
+                    vPortYield();
+                    break;
+            #endif /* configENABLE_MPU == 1 */
+
         default:
             /* Incorrect SVC call. */
             configASSERT( pdFALSE );
diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
index 6b389735a..60ef37380 100644
--- a/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
@@ -329,12 +329,20 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portSVC_SYSTEM_CALL_ENTER          4   /* System calls with upto 4 parameters. */
 #define portSVC_SYSTEM_CALL_ENTER_1        5   /* System calls with 5 parameters. */
 #define portSVC_SYSTEM_CALL_EXIT           6
+#define portSVC_YIELD                      7
 /*-----------------------------------------------------------*/
 
 /**
  * @brief Scheduler utilities.
  */
-#define portYIELD()    vPortYield()
+#if ( configENABLE_MPU == 1 )
+    #define portYIELD()               __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" )
+    #define portYIELD_WITHIN_API()    vPortYield()
+#else
+    #define portYIELD()               vPortYield()
+    #define portYIELD_WITHIN_API()    vPortYield()
+#endif
+
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
 #define portEND_SWITCHING_ISR( xSwitchRequired )            \
diff --git a/portable/IAR/ARM_CM55/non_secure/port.c b/portable/IAR/ARM_CM55/non_secure/port.c
index 0c5b76488..52d68d3ea 100644
--- a/portable/IAR/ARM_CM55/non_secure/port.c
+++ b/portable/IAR/ARM_CM55/non_secure/port.c
@@ -1118,6 +1118,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                     break;
             #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
+            #if ( configENABLE_MPU == 1 )
+                case portSVC_YIELD:
+                    vPortYield();
+                    break;
+            #endif /* configENABLE_MPU == 1 */
+
         default:
             /* Incorrect SVC call. */
             configASSERT( pdFALSE );
diff --git a/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h
index 6b389735a..60ef37380 100644
--- a/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h
@@ -329,12 +329,20 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portSVC_SYSTEM_CALL_ENTER          4   /* System calls with upto 4 parameters. */
 #define portSVC_SYSTEM_CALL_ENTER_1        5   /* System calls with 5 parameters. */
 #define portSVC_SYSTEM_CALL_EXIT           6
+#define portSVC_YIELD                      7
 /*-----------------------------------------------------------*/
 
 /**
  * @brief Scheduler utilities.
  */
-#define portYIELD()    vPortYield()
+#if ( configENABLE_MPU == 1 )
+    #define portYIELD()               __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" )
+    #define portYIELD_WITHIN_API()    vPortYield()
+#else
+    #define portYIELD()               vPortYield()
+    #define portYIELD_WITHIN_API()    vPortYield()
+#endif
+
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
 #define portEND_SWITCHING_ISR( xSwitchRequired )            \
diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/port.c b/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
index 0c5b76488..52d68d3ea 100644
--- a/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
@@ -1118,6 +1118,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                     break;
             #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
+            #if ( configENABLE_MPU == 1 )
+                case portSVC_YIELD:
+                    vPortYield();
+                    break;
+            #endif /* configENABLE_MPU == 1 */
+
         default:
             /* Incorrect SVC call. */
             configASSERT( pdFALSE );
diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h
index 6b389735a..60ef37380 100644
--- a/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h
@@ -329,12 +329,20 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portSVC_SYSTEM_CALL_ENTER          4   /* System calls with upto 4 parameters. */
 #define portSVC_SYSTEM_CALL_ENTER_1        5   /* System calls with 5 parameters. */
 #define portSVC_SYSTEM_CALL_EXIT           6
+#define portSVC_YIELD                      7
 /*-----------------------------------------------------------*/
 
 /**
  * @brief Scheduler utilities.
  */
-#define portYIELD()    vPortYield()
+#if ( configENABLE_MPU == 1 )
+    #define portYIELD()               __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" )
+    #define portYIELD_WITHIN_API()    vPortYield()
+#else
+    #define portYIELD()               vPortYield()
+    #define portYIELD_WITHIN_API()    vPortYield()
+#endif
+
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
 #define portEND_SWITCHING_ISR( xSwitchRequired )            \
diff --git a/portable/IAR/ARM_CM85/non_secure/port.c b/portable/IAR/ARM_CM85/non_secure/port.c
index 0c5b76488..52d68d3ea 100644
--- a/portable/IAR/ARM_CM85/non_secure/port.c
+++ b/portable/IAR/ARM_CM85/non_secure/port.c
@@ -1118,6 +1118,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                     break;
             #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
+            #if ( configENABLE_MPU == 1 )
+                case portSVC_YIELD:
+                    vPortYield();
+                    break;
+            #endif /* configENABLE_MPU == 1 */
+
         default:
             /* Incorrect SVC call. */
             configASSERT( pdFALSE );
diff --git a/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h
index 6b389735a..60ef37380 100644
--- a/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h
@@ -329,12 +329,20 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portSVC_SYSTEM_CALL_ENTER          4   /* System calls with upto 4 parameters. */
 #define portSVC_SYSTEM_CALL_ENTER_1        5   /* System calls with 5 parameters. */
 #define portSVC_SYSTEM_CALL_EXIT           6
+#define portSVC_YIELD                      7
 /*-----------------------------------------------------------*/
 
 /**
  * @brief Scheduler utilities.
  */
-#define portYIELD()    vPortYield()
+#if ( configENABLE_MPU == 1 )
+    #define portYIELD()               __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" )
+    #define portYIELD_WITHIN_API()    vPortYield()
+#else
+    #define portYIELD()               vPortYield()
+    #define portYIELD_WITHIN_API()    vPortYield()
+#endif
+
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
 #define portEND_SWITCHING_ISR( xSwitchRequired )            \
diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/port.c b/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
index 0c5b76488..52d68d3ea 100644
--- a/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
@@ -1118,6 +1118,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                     break;
             #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
+            #if ( configENABLE_MPU == 1 )
+                case portSVC_YIELD:
+                    vPortYield();
+                    break;
+            #endif /* configENABLE_MPU == 1 */
+
         default:
             /* Incorrect SVC call. */
             configASSERT( pdFALSE );
diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h
index 6b389735a..60ef37380 100644
--- a/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h
@@ -329,12 +329,20 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portSVC_SYSTEM_CALL_ENTER          4   /* System calls with upto 4 parameters. */
 #define portSVC_SYSTEM_CALL_ENTER_1        5   /* System calls with 5 parameters. */
 #define portSVC_SYSTEM_CALL_EXIT           6
+#define portSVC_YIELD                      7
 /*-----------------------------------------------------------*/
 
 /**
  * @brief Scheduler utilities.
  */
-#define portYIELD()    vPortYield()
+#if ( configENABLE_MPU == 1 )
+    #define portYIELD()               __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" )
+    #define portYIELD_WITHIN_API()    vPortYield()
+#else
+    #define portYIELD()               vPortYield()
+    #define portYIELD_WITHIN_API()    vPortYield()
+#endif
+
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
 #define portEND_SWITCHING_ISR( xSwitchRequired )            \

From abb5452a12ebff8e8af640e3ceb5fe16f30e6f54 Mon Sep 17 00:00:00 2001
From: Monika Singh <moninom@amazon.com>
Date: Mon, 9 Oct 2023 14:40:59 +0530
Subject: [PATCH 082/424] Update pull request information in readme (#821)

* Update pull request infomation in readme.

* Update link
---
 README.md | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/README.md b/README.md
index a9a07040a..43315a727 100644
--- a/README.md
+++ b/README.md
@@ -21,6 +21,9 @@ Additionally, for FreeRTOS kernel feature information refer to the
 [Developer Documentation](https://www.FreeRTOS.org/features.html),
 and [API Reference](https://www.FreeRTOS.org/a00106.html).
 
+Also for contributing and creating a Pull Request please refer to
+[the instructions here](https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/.github/CONTRIBUTING.md#contributing-via-pull-request).
+
 ### Getting help
 
 If you have any questions or need assistance troubleshooting your FreeRTOS project,

From 92a4d175e6f6273ac6ec6af8a2bd0310ac098f05 Mon Sep 17 00:00:00 2001
From: Soren Ptak <ptaksoren@gmail.com>
Date: Tue, 10 Oct 2023 23:34:01 -0700
Subject: [PATCH 083/424] Link to the CONTRIBUTING.md file in this repo, not
 the github repo itself (#827)

---
 README.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/README.md b/README.md
index 43315a727..2ef719972 100644
--- a/README.md
+++ b/README.md
@@ -22,7 +22,7 @@ Additionally, for FreeRTOS kernel feature information refer to the
 and [API Reference](https://www.FreeRTOS.org/a00106.html).
 
 Also for contributing and creating a Pull Request please refer to
-[the instructions here](https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/.github/CONTRIBUTING.md#contributing-via-pull-request).
+[the instructions here](.github/CONTRIBUTING.md#contributing-via-pull-request).
 
 ### Getting help
 

From 4bfb9b2d707304917f35fd5e7dcf692abb3d0cb2 Mon Sep 17 00:00:00 2001
From: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Date: Thu, 12 Oct 2023 10:41:16 +0800
Subject: [PATCH 084/424] Update SMP get idle task memory for static allocation
 (#784)

* Add static idle task memory support for SMP
* Rename vApplicationMinimalIdleTask to vApplicationPassiveIdleTask
* Rename the macro configUSE_MINIMAL_IDLE_HOOK to configUSE_PASSIVE_IDLE_HOOK
* Update xTaskGetIdleTaskHandle for SMP
* Add more check in xTaskGetIdleTaskHandle
* Support configKERNEL_PROVIDED_STATIC_MEMORY for SMP

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
---
 include/FreeRTOS.h |  20 ++-
 include/task.h     |  57 ++++++-
 tasks.c            | 362 ++++++++++++++++++++++-----------------------
 3 files changed, 241 insertions(+), 198 deletions(-)

diff --git a/include/FreeRTOS.h b/include/FreeRTOS.h
index f57586375..d0dfea9e5 100644
--- a/include/FreeRTOS.h
+++ b/include/FreeRTOS.h
@@ -175,8 +175,8 @@
 #endif
 
 #if ( configNUMBER_OF_CORES > 1 )
-    #ifndef configUSE_MINIMAL_IDLE_HOOK
-        #error Missing definition:  configUSE_MINIMAL_IDLE_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.
+    #ifndef configUSE_PASSIVE_IDLE_HOOK
+        #error Missing definition:  configUSE_PASSIVE_IDLE_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.
     #endif
 #endif
 
@@ -473,9 +473,9 @@
     #define configUSE_CORE_AFFINITY    0
 #endif /* configUSE_CORE_AFFINITY */
 
-#ifndef configUSE_MINIMAL_IDLE_HOOK
-    #define configUSE_MINIMAL_IDLE_HOOK    0
-#endif /* configUSE_MINIMAL_IDLE_HOOK */
+#ifndef configUSE_PASSIVE_IDLE_HOOK
+    #define configUSE_PASSIVE_IDLE_HOOK    0
+#endif /* configUSE_PASSIVE_IDLE_HOOK */
 
 /* The timers module relies on xTaskGetSchedulerState(). */
 #if configUSE_TIMERS == 1
@@ -1834,8 +1834,14 @@
     #define traceRETURN_uxTaskGetSystemState( uxTask )
 #endif
 
-#ifndef traceENTER_xTaskGetIdleTaskHandle
-    #define traceENTER_xTaskGetIdleTaskHandle()
+#if ( configNUMBER_OF_CORES == 1 )
+    #ifndef traceENTER_xTaskGetIdleTaskHandle
+        #define traceENTER_xTaskGetIdleTaskHandle()
+    #endif
+#else
+    #ifndef traceENTER_xTaskGetIdleTaskHandle
+        #define traceENTER_xTaskGetIdleTaskHandle( xCoreID )
+    #endif
 #endif
 
 #ifndef traceRETURN_xTaskGetIdleTaskHandle
diff --git a/include/task.h b/include/task.h
index 448351876..de3ab5531 100644
--- a/include/task.h
+++ b/include/task.h
@@ -1930,6 +1930,8 @@ configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) PRIVIL
 
 #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
 
+    #if ( configNUMBER_OF_CORES == 1 )
+
 /**
  * task.h
  * @code{c}
@@ -1943,10 +1945,41 @@ configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) PRIVIL
  * @param ppxIdleTaskStackBuffer A handle to a statically allocated Stack buffer for the idle task
  * @param pulIdleTaskStackSize A pointer to the number of elements that will fit in the allocated stack buffer
  */
-    void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer,
-                                        StackType_t ** ppxIdleTaskStackBuffer,
-                                        uint32_t * pulIdleTaskStackSize ); /*lint !e526 Symbol not defined as it is an application callback. */
-#endif
+        void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer,
+                                            StackType_t ** ppxIdleTaskStackBuffer,
+                                            uint32_t * pulIdleTaskStackSize ); /*lint !e526 Symbol not defined as it is an application callback. */
+    #else /* #if ( configNUMBER_OF_CORES == 1 ) */
+
+/**
+ * task.h
+ * @code{c}
+ * void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, StackType_t ** ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize, BaseType_t xCoreID )
+ * @endcode
+ *
+ * This function is used to provide a statically allocated block of memory to FreeRTOS to hold the Idle Tasks TCB.  This function is required when
+ * configSUPPORT_STATIC_ALLOCATION is set.  For more information see this URI: https://www.FreeRTOS.org/a00110.html#configSUPPORT_STATIC_ALLOCATION
+ *
+ * In the FreeRTOS SMP, there are a total of configNUMBER_OF_CORES idle tasks:
+ *  1. 1 Active idle task which does all the housekeeping.
+ *  2. ( configNUMBER_OF_CORES - 1 ) Passive idle tasks which do nothing.
+ * These idle tasks are created to ensure that each core has an idle task to run when
+ * no other task is available to run.
+ *
+ * The function vApplicationGetIdleTaskMemory is called with xCoreID 0 to get the
+ * memory for Active idle task. It is called with xCoreID 1, 2 ... ( configNUMBER_OF_CORES - 1 )
+ * to get memory for passive idle tasks.
+ *
+ * @param ppxIdleTaskTCBBuffer A handle to a statically allocated TCB buffer
+ * @param ppxIdleTaskStackBuffer A handle to a statically allocated Stack buffer for the idle task
+ * @param pulIdleTaskStackSize A pointer to the number of elements that will fit in the allocated stack buffer
+ * @param xCoreId The core index of the idle task buffer
+ */
+        void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer,
+                                            StackType_t ** ppxIdleTaskStackBuffer,
+                                            uint32_t * pulIdleTaskStackSize, /*lint !e526 Symbol not defined as it is an application callback. */
+                                            BaseType_t xCoreID );
+    #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
+#endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
 
 /**
  * task.h
@@ -1970,8 +2003,22 @@ BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask,
  *
  * Simply returns the handle of the idle task.  It is not valid to call
  * xTaskGetIdleTaskHandle() before the scheduler has been started.
+ *
+ * In the FreeRTOS SMP, there are a total of configNUMBER_OF_CORES idle tasks:
+ *  1. 1 Active idle task which does all the housekeeping.
+ *  2. ( configNUMBER_OF_CORES - 1 ) Passive idle tasks which do nothing.
+ * These idle tasks are created to ensure that each core has an idle task to run when
+ * no other task is available to run.
+ *
+ * Set xCoreID to 0 to get the Active idle task handle. Set xCoreID to
+ * 1,2 ... ( configNUMBER_OF_CORES - 1 ) to get the Passive idle task
+ * handles.
  */
-TaskHandle_t xTaskGetIdleTaskHandle( void ) PRIVILEGED_FUNCTION;
+#if ( configNUMBER_OF_CORES == 1 )
+    TaskHandle_t xTaskGetIdleTaskHandle( void ) PRIVILEGED_FUNCTION;
+#else /* #if ( configNUMBER_OF_CORES == 1 ) */
+    TaskHandle_t xTaskGetIdleTaskHandle( BaseType_t xCoreID ) PRIVILEGED_FUNCTION;
+#endif /* #if ( configNUMBER_OF_CORES == 1 ) */
 
 /**
  * configUSE_TRACE_FACILITY must be defined as 1 in FreeRTOSConfig.h for
diff --git a/tasks.c b/tasks.c
index 48c1960aa..d86c83429 100644
--- a/tasks.c
+++ b/tasks.c
@@ -515,15 +515,6 @@ PRIVILEGED_DATA static volatile configRUN_TIME_COUNTER_TYPE ulTotalRunTime[ conf
 
 #endif
 
-#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configNUMBER_OF_CORES > 1 )
-
-/* Do not move these variables to function scope as doing so prevents the
- * code working with debuggers that need to remove the static qualifier. */
-    static StaticTask_t xIdleTCBBuffers[ configNUMBER_OF_CORES - 1 ];
-    static StackType_t xIdleTaskStackBuffers[ configNUMBER_OF_CORES - 1 ][ configMINIMAL_STACK_SIZE ];
-
-#endif /* #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configNUMBER_OF_CORES > 1 ) */
-
 /*lint -restore */
 
 /*-----------------------------------------------------------*/
@@ -583,7 +574,7 @@ static void prvInitialiseTaskLists( void ) PRIVILEGED_FUNCTION;
  * The idle task is automatically created and added to the ready lists upon
  * creation of the first user task.
  *
- * In the FreeRTOS SMP, configNUMBER_OF_CORES - 1 minimal idle tasks are also
+ * In the FreeRTOS SMP, configNUMBER_OF_CORES - 1 passive idle tasks are also
  * created to ensure that each core has an idle task to run when no other
  * task is available to run.
  *
@@ -591,12 +582,12 @@ static void prvInitialiseTaskLists( void ) PRIVILEGED_FUNCTION;
  * language extensions.  The equivalent prototype for these functions are:
  *
  * void prvIdleTask( void *pvParameters );
- * void prvMinimalIdleTask( void *pvParameters );
+ * void prvPassiveIdleTask( void *pvParameters );
  *
  */
 static portTASK_FUNCTION_PROTO( prvIdleTask, pvParameters ) PRIVILEGED_FUNCTION;
 #if ( configNUMBER_OF_CORES > 1 )
-    static portTASK_FUNCTION_PROTO( prvMinimalIdleTask, pvParameters ) PRIVILEGED_FUNCTION;
+    static portTASK_FUNCTION_PROTO( prvPassiveIdleTask, pvParameters ) PRIVILEGED_FUNCTION;
 #endif
 
 /*
@@ -726,9 +717,9 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
 
 #endif
 
-#if ( configUSE_MINIMAL_IDLE_HOOK == 1 )
-    extern void vApplicationMinimalIdleHook( void );
-#endif /* #if ( configUSE_MINIMAL_IDLE_HOOK == 1 ) */
+#if ( configUSE_PASSIVE_IDLE_HOOK == 1 )
+    extern void vApplicationPassiveIdleHook( void );
+#endif /* #if ( configUSE_PASSIVE_IDLE_HOOK == 1 ) */
 
 #if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )
 
@@ -1760,7 +1751,7 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
         pxNewTCB->xTaskRunState = taskTASK_NOT_RUNNING;
 
         /* Is this an idle task? */
-        if( ( ( TaskFunction_t ) pxTaskCode == ( TaskFunction_t ) prvIdleTask ) || ( ( TaskFunction_t ) pxTaskCode == ( TaskFunction_t ) prvMinimalIdleTask ) )
+        if( ( ( TaskFunction_t ) pxTaskCode == ( TaskFunction_t ) prvIdleTask ) || ( ( TaskFunction_t ) pxTaskCode == ( TaskFunction_t ) prvPassiveIdleTask ) )
         {
             pxNewTCB->uxTaskAttributes |= taskATTRIBUTE_IS_IDLE;
         }
@@ -3192,10 +3183,78 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
 static BaseType_t prvCreateIdleTasks( void )
 {
     BaseType_t xReturn = pdPASS;
+    BaseType_t xCoreID;
+    char cIdleName[ configMAX_TASK_NAME_LEN ];
+    TaskFunction_t pxIdleTaskFunction = NULL;
+    BaseType_t xIdleTaskNameIndex;
 
-    #if ( configNUMBER_OF_CORES == 1 )
+    for( xIdleTaskNameIndex = ( BaseType_t ) 0; xIdleTaskNameIndex < ( BaseType_t ) configMAX_TASK_NAME_LEN; xIdleTaskNameIndex++ )
     {
-        /* Add the idle task at the lowest priority. */
+        cIdleName[ xIdleTaskNameIndex ] = configIDLE_TASK_NAME[ xIdleTaskNameIndex ];
+
+        /* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than
+         * configMAX_TASK_NAME_LEN characters just in case the memory after the
+         * string is not accessible (extremely unlikely). */
+        if( cIdleName[ xIdleTaskNameIndex ] == ( char ) 0x00 )
+        {
+            break;
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+
+    /* Add each idle task at the lowest priority. */
+    for( xCoreID = ( BaseType_t ) 0; xCoreID < ( BaseType_t ) configNUMBER_OF_CORES; xCoreID++ )
+    {
+        #if ( configNUMBER_OF_CORES == 1 )
+        {
+            pxIdleTaskFunction = prvIdleTask;
+        }
+        #else /* #if (  configNUMBER_OF_CORES == 1 ) */
+        {
+            /* In the FreeRTOS SMP, configNUMBER_OF_CORES - 1 passive idle tasks
+             * are also created to ensure that each core has an idle task to
+             * run when no other task is available to run. */
+            if( xCoreID == 0 )
+            {
+                pxIdleTaskFunction = prvIdleTask;
+            }
+            else
+            {
+                pxIdleTaskFunction = prvPassiveIdleTask;
+            }
+        }
+        #endif /* #if (  configNUMBER_OF_CORES == 1 ) */
+
+        /* Update the idle task name with suffix to differentiate the idle tasks.
+         * This function is not required in single core FreeRTOS since there is
+         * only one idle task. */
+        #if ( configNUMBER_OF_CORES > 1 )
+        {
+            /* Append the idle task number to the end of the name if there is space. */
+            if( xIdleTaskNameIndex < ( BaseType_t ) configMAX_TASK_NAME_LEN )
+            {
+                cIdleName[ xIdleTaskNameIndex ] = ( char ) ( xCoreID + '0' );
+
+                /* And append a null character if there is space. */
+                if( ( xIdleTaskNameIndex + 1 ) < ( BaseType_t ) configMAX_TASK_NAME_LEN )
+                {
+                    cIdleName[ xIdleTaskNameIndex + 1 ] = '\0';
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        #endif /* if ( configNUMBER_OF_CORES > 1 ) */
+
         #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
         {
             StaticTask_t * pxIdleTaskTCBBuffer = NULL;
@@ -3204,16 +3263,20 @@ static BaseType_t prvCreateIdleTasks( void )
 
             /* The Idle task is created using user provided RAM - obtain the
              * address of the RAM then create the idle task. */
-            vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize );
-            xIdleTaskHandles[ 0 ] = xTaskCreateStatic( prvIdleTask,
-                                                       configIDLE_TASK_NAME,
-                                                       ulIdleTaskStackSize,
-                                                       ( void * ) NULL,       /*lint !e961.  The cast is not redundant for all compilers. */
-                                                       portPRIVILEGE_BIT,     /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
-                                                       pxIdleTaskStackBuffer,
-                                                       pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
+            #if ( configNUMBER_OF_CORES == 1 )
+                vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize );
+            #else
+                vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize, xCoreID );
+            #endif
+            xIdleTaskHandles[ xCoreID ] = xTaskCreateStatic( pxIdleTaskFunction,
+                                                             cIdleName,
+                                                             ulIdleTaskStackSize,
+                                                             ( void * ) NULL,       /*lint !e961.  The cast is not redundant for all compilers. */
+                                                             portPRIVILEGE_BIT,     /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
+                                                             pxIdleTaskStackBuffer,
+                                                             pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
 
-            if( xIdleTaskHandles[ 0 ] != NULL )
+            if( xIdleTaskHandles[ xCoreID ] != NULL )
             {
                 xReturn = pdPASS;
             }
@@ -3225,137 +3288,25 @@ static BaseType_t prvCreateIdleTasks( void )
         #else /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
         {
             /* The Idle task is being created using dynamically allocated RAM. */
-            xReturn = xTaskCreate( prvIdleTask,
-                                   configIDLE_TASK_NAME,
+            xReturn = xTaskCreate( pxIdleTaskFunction,
+                                   cIdleName,
                                    configMINIMAL_STACK_SIZE,
                                    ( void * ) NULL,
-                                   portPRIVILEGE_BIT,        /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
-                                   &xIdleTaskHandles[ 0 ] ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
+                                   portPRIVILEGE_BIT,              /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
+                                   &xIdleTaskHandles[ xCoreID ] ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
         }
         #endif /* configSUPPORT_STATIC_ALLOCATION */
-    }
-    #else /* #if ( configNUMBER_OF_CORES == 1 ) */
-    {
-        BaseType_t xCoreID;
-        char cIdleName[ configMAX_TASK_NAME_LEN ];
 
-        /* Add each idle task at the lowest priority. */
-        for( xCoreID = ( BaseType_t ) 0; xCoreID < ( BaseType_t ) configNUMBER_OF_CORES; xCoreID++ )
+        /* Break the loop if any of the idle task is failed to be created. */
+        if( xReturn == pdFAIL )
         {
-            BaseType_t x;
-
-            if( xReturn == pdFAIL )
-            {
-                break;
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
-
-            for( x = ( BaseType_t ) 0; x < ( BaseType_t ) configMAX_TASK_NAME_LEN; x++ )
-            {
-                cIdleName[ x ] = configIDLE_TASK_NAME[ x ];
-
-                /* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than
-                 * configMAX_TASK_NAME_LEN characters just in case the memory after the
-                 * string is not accessible (extremely unlikely). */
-                if( cIdleName[ x ] == ( char ) 0x00 )
-                {
-                    break;
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
-            }
-
-            /* Append the idle task number to the end of the name if there is space. */
-            if( x < ( BaseType_t ) configMAX_TASK_NAME_LEN )
-            {
-                cIdleName[ x ] = ( char ) ( xCoreID + '0' );
-                x++;
-
-                /* And append a null character if there is space. */
-                if( x < ( BaseType_t ) configMAX_TASK_NAME_LEN )
-                {
-                    cIdleName[ x ] = '\0';
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
-
-            #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
-            {
-                if( xCoreID == 0 )
-                {
-                    StaticTask_t * pxIdleTaskTCBBuffer = NULL;
-                    StackType_t * pxIdleTaskStackBuffer = NULL;
-                    uint32_t ulIdleTaskStackSize;
-
-                    /* The Idle task is created using user provided RAM - obtain the
-                     * address of the RAM then create the idle task. */
-                    vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize );
-                    xIdleTaskHandles[ xCoreID ] = xTaskCreateStatic( prvIdleTask,
-                                                                     cIdleName,
-                                                                     ulIdleTaskStackSize,
-                                                                     ( void * ) NULL,       /*lint !e961.  The cast is not redundant for all compilers. */
-                                                                     portPRIVILEGE_BIT,     /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
-                                                                     pxIdleTaskStackBuffer,
-                                                                     pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
-                }
-                else
-                {
-                    xIdleTaskHandles[ xCoreID ] = xTaskCreateStatic( prvMinimalIdleTask,
-                                                                     cIdleName,
-                                                                     configMINIMAL_STACK_SIZE,
-                                                                     ( void * ) NULL,                   /*lint !e961.  The cast is not redundant for all compilers. */
-                                                                     portPRIVILEGE_BIT,                 /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
-                                                                     xIdleTaskStackBuffers[ xCoreID - 1 ],
-                                                                     &xIdleTCBBuffers[ xCoreID - 1 ] ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
-                }
-
-                if( xIdleTaskHandles[ xCoreID ] != NULL )
-                {
-                    xReturn = pdPASS;
-                }
-                else
-                {
-                    xReturn = pdFAIL;
-                }
-            }
-            #else /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
-            {
-                if( xCoreID == 0 )
-                {
-                    /* The Idle task is being created using dynamically allocated RAM. */
-                    xReturn = xTaskCreate( prvIdleTask,
-                                           cIdleName,
-                                           configMINIMAL_STACK_SIZE,
-                                           ( void * ) NULL,
-                                           portPRIVILEGE_BIT,              /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
-                                           &xIdleTaskHandles[ xCoreID ] ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
-                }
-                else
-                {
-                    xReturn = xTaskCreate( prvMinimalIdleTask,
-                                           cIdleName,
-                                           configMINIMAL_STACK_SIZE,
-                                           ( void * ) NULL,
-                                           portPRIVILEGE_BIT,              /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
-                                           &xIdleTaskHandles[ xCoreID ] ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
-                }
-            }
-            #endif /* configSUPPORT_STATIC_ALLOCATION */
+            break;
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
         }
     }
-    #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
 
     return xReturn;
 }
@@ -4192,20 +4143,40 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char
 
 #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
 
-/* SMP_TODO : This function returns only idle task handle for core 0.
- * Consider to add another function to return the idle task handles. */
-    TaskHandle_t xTaskGetIdleTaskHandle( void )
-    {
-        traceENTER_xTaskGetIdleTaskHandle();
+    #if ( configNUMBER_OF_CORES == 1 )
 
-        /* If xTaskGetIdleTaskHandle() is called before the scheduler has been
-         * started, then xIdleTaskHandles will be NULL. */
-        configASSERT( ( xIdleTaskHandles[ 0 ] != NULL ) );
+        TaskHandle_t xTaskGetIdleTaskHandle( void )
+        {
+            traceENTER_xTaskGetIdleTaskHandle();
 
-        traceRETURN_xTaskGetIdleTaskHandle( xIdleTaskHandles[ 0 ] );
+            /* If xTaskGetIdleTaskHandle() is called before the scheduler has been
+             * started, then xIdleTaskHandles will be NULL. */
+            configASSERT( ( xIdleTaskHandles[ 0 ] != NULL ) );
 
-        return xIdleTaskHandles[ 0 ];
-    }
+            traceRETURN_xTaskGetIdleTaskHandle( xIdleTaskHandles[ 0 ] );
+
+            return xIdleTaskHandles[ 0 ];
+        }
+
+    #else /* if ( configNUMBER_OF_CORES == 1 ) */
+
+        TaskHandle_t xTaskGetIdleTaskHandle( BaseType_t xCoreID )
+        {
+            traceENTER_xTaskGetIdleTaskHandle( xCoreID );
+
+            /* Ensure the core ID is valid. */
+            configASSERT( taskVALID_CORE_ID( xCoreID ) == pdTRUE );
+
+            /* If xTaskGetIdleTaskHandle() is called before the scheduler has been
+             * started, then xIdleTaskHandles will be NULL. */
+            configASSERT( ( xIdleTaskHandles[ xCoreID ] != NULL ) );
+
+            traceRETURN_xTaskGetIdleTaskHandle( xIdleTaskHandles[ xCoreID ] );
+
+            return xIdleTaskHandles[ xCoreID ];
+        }
+
+    #endif /* if ( configNUMBER_OF_CORES == 1 ) */
 
 #endif /* INCLUDE_xTaskGetIdleTaskHandle */
 /*----------------------------------------------------------*/
@@ -5348,21 +5319,21 @@ void vTaskMissedYield( void )
 
 /*
  * -----------------------------------------------------------
- * The MinimalIdle task.
+ * The passive idle task.
  * ----------------------------------------------------------
  *
- * The minimal idle task is used for all the additional cores in a SMP
- * system. There must be only 1 idle task and the rest are minimal idle
- * tasks.
+ * The passive idle task is used for all the additional cores in a SMP
+ * system. There must be only 1 active idle task and the rest are passive
+ * idle tasks.
  *
  * The portTASK_FUNCTION() macro is used to allow port/compiler specific
  * language extensions.  The equivalent prototype for this function is:
  *
- * void prvMinimalIdleTask( void *pvParameters );
+ * void prvPassiveIdleTask( void *pvParameters );
  */
 
 #if ( configNUMBER_OF_CORES > 1 )
-    static portTASK_FUNCTION( prvMinimalIdleTask, pvParameters )
+    static portTASK_FUNCTION( prvPassiveIdleTask, pvParameters )
     {
         ( void ) pvParameters;
 
@@ -5403,7 +5374,7 @@ void vTaskMissedYield( void )
             }
             #endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) ) */
 
-            #if ( configUSE_MINIMAL_IDLE_HOOK == 1 )
+            #if ( configUSE_PASSIVE_IDLE_HOOK == 1 )
             {
                 /* Call the user defined function from within the idle task.  This
                  * allows the application designer to add background functionality
@@ -5411,18 +5382,18 @@ void vTaskMissedYield( void )
                  *
                  * This hook is intended to manage core activity such as disabling cores that go idle.
                  *
-                 * NOTE: vApplicationMinimalIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES,
+                 * NOTE: vApplicationPassiveIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES,
                  * CALL A FUNCTION THAT MIGHT BLOCK. */
-                vApplicationMinimalIdleHook();
+                vApplicationPassiveIdleHook();
             }
-            #endif /* configUSE_MINIMAL_IDLE_HOOK */
+            #endif /* configUSE_PASSIVE_IDLE_HOOK */
         }
     }
 #endif /* #if ( configNUMBER_OF_CORES > 1 ) */
 
 /*
  * -----------------------------------------------------------
- * The Idle task.
+ * The idle task.
  * ----------------------------------------------------------
  *
  * The portTASK_FUNCTION() macro is used to allow port/compiler specific
@@ -5549,7 +5520,7 @@ static portTASK_FUNCTION( prvIdleTask, pvParameters )
         }
         #endif /* configUSE_TICKLESS_IDLE */
 
-        #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_MINIMAL_IDLE_HOOK == 1 ) )
+        #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_PASSIVE_IDLE_HOOK == 1 ) )
         {
             /* Call the user defined function from within the idle task.  This
              * allows the application designer to add background functionality
@@ -5557,11 +5528,11 @@ static portTASK_FUNCTION( prvIdleTask, pvParameters )
              *
              * This hook is intended to manage core activity such as disabling cores that go idle.
              *
-             * NOTE: vApplicationMinimalIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES,
+             * NOTE: vApplicationPassiveIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES,
              * CALL A FUNCTION THAT MIGHT BLOCK. */
-            vApplicationMinimalIdleHook();
+            vApplicationPassiveIdleHook();
         }
-        #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_MINIMAL_IDLE_HOOK == 1 ) ) */
+        #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_PASSIVE_IDLE_HOOK == 1 ) ) */
     }
 }
 /*-----------------------------------------------------------*/
@@ -8127,17 +8098,36 @@ static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait,
  * it's own implementation of vApplicationGetIdleTaskMemory by setting
  * configKERNEL_PROVIDED_STATIC_MEMORY to 0 or leaving it undefined.
  */
-    void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer,
-                                        StackType_t ** ppxIdleTaskStackBuffer,
-                                        uint32_t * pulIdleTaskStackSize )
-    {
-        static StaticTask_t xIdleTaskTCB;
-        static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ];
+    #if ( configNUMBER_OF_CORES == 1 )
 
-        *ppxIdleTaskTCBBuffer = &( xIdleTaskTCB );
-        *ppxIdleTaskStackBuffer = &( uxIdleTaskStack[ 0 ] );
-        *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;
-    }
+        void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer,
+                                            StackType_t ** ppxIdleTaskStackBuffer,
+                                            uint32_t * pulIdleTaskStackSize )
+        {
+            static StaticTask_t xIdleTaskTCB;
+            static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ];
+
+            *ppxIdleTaskTCBBuffer = &( xIdleTaskTCB );
+            *ppxIdleTaskStackBuffer = &( uxIdleTaskStack[ 0 ] );
+            *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;
+        }
+
+    #else /* #if ( configNUMBER_OF_CORES == 1 ) */
+
+        void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer,
+                                            StackType_t ** ppxIdleTaskStackBuffer,
+                                            uint32_t * pulIdleTaskStackSize,
+                                            BaseType_t xCoreId )
+        {
+            static StaticTask_t xIdleTaskTCBs[ configNUMBER_OF_CORES ];
+            static StackType_t uxIdleTaskStacks[ configNUMBER_OF_CORES ][ configMINIMAL_STACK_SIZE ];
+
+            *ppxIdleTaskTCBBuffer = &( xIdleTaskTCBs[ xCoreId ] );
+            *ppxIdleTaskStackBuffer = &( uxIdleTaskStacks[ xCoreId ][ 0 ] );
+            *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;
+        }
+
+    #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
 
 #endif /* #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configKERNEL_PROVIDED_STATIC_MEMORY == 1 ) && ( portUSING_MPU_WRAPPERS == 0 ) ) */
 /*-----------------------------------------------------------*/

From 2be332ae2161d893099cdd3fc8deec96fc734f20 Mon Sep 17 00:00:00 2001
From: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Date: Thu, 12 Oct 2023 17:30:24 +0800
Subject: [PATCH 085/424] Separate the task create function for core affinity
 (#789)

* Separate the task create function for core affinity
* Update function prototype and comment
* Code review suggestions

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: kar-rahul-aws <118818625+kar-rahul-aws@users.noreply.github.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
---
 include/FreeRTOS.h |  32 ++++
 tasks.c            | 424 ++++++++++++++++++++++++++++++++++-----------
 2 files changed, 352 insertions(+), 104 deletions(-)

diff --git a/include/FreeRTOS.h b/include/FreeRTOS.h
index d0dfea9e5..c15eb6d39 100644
--- a/include/FreeRTOS.h
+++ b/include/FreeRTOS.h
@@ -1610,6 +1610,14 @@
     #define traceRETURN_xTaskCreateStatic( xReturn )
 #endif
 
+#ifndef traceENTER_xTaskCreateStaticAffinitySet
+    #define traceENTER_xTaskCreateStaticAffinitySet( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer, uxCoreAffinityMask )
+#endif
+
+#ifndef traceRETURN_xTaskCreateStaticAffinitySet
+    #define traceRETURN_xTaskCreateStaticAffinitySet( xReturn )
+#endif
+
 #ifndef traceENTER_xTaskCreateRestrictedStatic
     #define traceENTER_xTaskCreateRestrictedStatic( pxTaskDefinition, pxCreatedTask )
 #endif
@@ -1618,6 +1626,14 @@
     #define traceRETURN_xTaskCreateRestrictedStatic( xReturn )
 #endif
 
+#ifndef traceENTER_xTaskCreateRestrictedStaticAffinitySet
+    #define traceENTER_xTaskCreateRestrictedStaticAffinitySet( pxTaskDefinition, uxCoreAffinityMask, pxCreatedTask )
+#endif
+
+#ifndef traceRETURN_xTaskCreateRestrictedStaticAffinitySet
+    #define traceRETURN_xTaskCreateRestrictedStaticAffinitySet( xReturn )
+#endif
+
 #ifndef traceENTER_xTaskCreateRestricted
     #define traceENTER_xTaskCreateRestricted( pxTaskDefinition, pxCreatedTask )
 #endif
@@ -1626,6 +1642,14 @@
     #define traceRETURN_xTaskCreateRestricted( xReturn )
 #endif
 
+#ifndef traceENTER_xTaskCreateRestrictedAffinitySet
+    #define traceENTER_xTaskCreateRestrictedAffinitySet( pxTaskDefinition, uxCoreAffinityMask, pxCreatedTask )
+#endif
+
+#ifndef traceRETURN_xTaskCreateRestrictedAffinitySet
+    #define traceRETURN_xTaskCreateRestrictedAffinitySet( xReturn )
+#endif
+
 #ifndef traceENTER_xTaskCreate
     #define traceENTER_xTaskCreate( pxTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask )
 #endif
@@ -1634,6 +1658,14 @@
     #define traceRETURN_xTaskCreate( xReturn )
 #endif
 
+#ifndef traceENTER_xTaskCreateAffinitySet
+    #define traceENTER_xTaskCreateAffinitySet( pxTaskCode, pcName, usStackDepth, pvParameters, uxPriority, uxCoreAffinityMask, pxCreatedTask )
+#endif
+
+#ifndef traceRETURN_xTaskCreateAffinitySet
+    #define traceRETURN_xTaskCreateAffinitySet( xReturn )
+#endif
+
 #ifndef traceENTER_vTaskDelete
     #define traceENTER_vTaskDelete( xTaskToDelete )
 #endif
diff --git a/tasks.c b/tasks.c
index d86c83429..2cd130a82 100644
--- a/tasks.c
+++ b/tasks.c
@@ -706,6 +706,53 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
  */
 static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
 
+/*
+ * Create a task with static buffer for both TCB and stack. Returns a handle to
+ * the task if it is created successfully. Otherwise, returns NULL.
+ */
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+    static TCB_t * prvCreateStaticTask( TaskFunction_t pxTaskCode,
+                                        const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+                                        const uint32_t ulStackDepth,
+                                        void * const pvParameters,
+                                        UBaseType_t uxPriority,
+                                        StackType_t * const puxStackBuffer,
+                                        StaticTask_t * const pxTaskBuffer,
+                                        TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION;
+#endif /* #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+
+/*
+ * Create a restricted task with static buffer for both TCB and stack. Returns
+ * a handle to the task if it is created successfully. Otherwise, returns NULL.
+ */
+#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+    static TCB_t * prvCreateRestrictedStaticTask( const TaskParameters_t * const pxTaskDefinition,
+                                                  TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION;
+#endif /* #if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) */
+
+/*
+ * Create a restricted task with static buffer for task stack and allocated buffer
+ * for TCB. Returns a handle to the task if it is created successfully. Otherwise,
+ * returns NULL.
+ */
+#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+    static TCB_t * prvCreateRestrictedTask( const TaskParameters_t * const pxTaskDefinition,
+                                            TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION;
+#endif /* #if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
+
+/*
+ * Create a task with allocated buffer for both TCB and stack. Returns a handle to
+ * the task if it is created successfully. Otherwise, returns NULL.
+ */
+#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+    static TCB_t * prvCreateTask( TaskFunction_t pxTaskCode,
+                                  const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+                                  const configSTACK_DEPTH_TYPE usStackDepth,
+                                  void * const pvParameters,
+                                  UBaseType_t uxPriority,
+                                  TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION;
+#endif /* #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) */
+
 /*
  * freertos_tasks_c_additions_init() should only be called if the user definable
  * macro FREERTOS_TASKS_C_ADDITIONS_INIT() is defined, as that is the only macro
@@ -1195,32 +1242,16 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
 
 #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
 
-    TaskHandle_t xTaskCreateStatic( TaskFunction_t pxTaskCode,
-                                    const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-                                    const uint32_t ulStackDepth,
-                                    void * const pvParameters,
-                                    UBaseType_t uxPriority,
-                                    StackType_t * const puxStackBuffer,
-                                    StaticTask_t * const pxTaskBuffer )
-    #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
-    {
-        return xTaskCreateStaticAffinitySet( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer, tskNO_AFFINITY );
-    }
-
-    TaskHandle_t xTaskCreateStaticAffinitySet( TaskFunction_t pxTaskCode,
-                                               const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-                                               const uint32_t ulStackDepth,
-                                               void * const pvParameters,
-                                               UBaseType_t uxPriority,
-                                               StackType_t * const puxStackBuffer,
-                                               StaticTask_t * const pxTaskBuffer,
-                                               UBaseType_t uxCoreAffinityMask )
-    #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */
+    static TCB_t * prvCreateStaticTask( TaskFunction_t pxTaskCode,
+                                        const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+                                        const uint32_t ulStackDepth,
+                                        void * const pvParameters,
+                                        UBaseType_t uxPriority,
+                                        StackType_t * const puxStackBuffer,
+                                        StaticTask_t * const pxTaskBuffer,
+                                        TaskHandle_t * const pxCreatedTask )
     {
         TCB_t * pxNewTCB;
-        TaskHandle_t xReturn;
-
-        traceENTER_xTaskCreateStatic( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer );
 
         configASSERT( puxStackBuffer != NULL );
         configASSERT( pxTaskBuffer != NULL );
@@ -1252,12 +1283,38 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
             }
             #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
 
-            prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL );
+            prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL );
+        }
+        else
+        {
+            pxNewTCB = NULL;
+        }
 
+        return pxNewTCB;
+    }
+/*-----------------------------------------------------------*/
+
+    TaskHandle_t xTaskCreateStatic( TaskFunction_t pxTaskCode,
+                                    const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+                                    const uint32_t ulStackDepth,
+                                    void * const pvParameters,
+                                    UBaseType_t uxPriority,
+                                    StackType_t * const puxStackBuffer,
+                                    StaticTask_t * const pxTaskBuffer )
+    {
+        TaskHandle_t xReturn = NULL;
+        TCB_t * pxNewTCB;
+
+        traceENTER_xTaskCreateStatic( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer );
+
+        pxNewTCB = prvCreateStaticTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer, &xReturn );
+
+        if( pxNewTCB != NULL )
+        {
             #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
             {
                 /* Set the task's affinity before scheduling it. */
-                pxNewTCB->uxCoreAffinityMask = uxCoreAffinityMask;
+                pxNewTCB->uxCoreAffinityMask = tskNO_AFFINITY;
             }
             #endif
 
@@ -1265,35 +1322,58 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
         }
         else
         {
-            xReturn = NULL;
+            mtCOVERAGE_TEST_MARKER();
         }
 
         traceRETURN_xTaskCreateStatic( xReturn );
 
         return xReturn;
     }
+/*-----------------------------------------------------------*/
+
+    #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
+        TaskHandle_t xTaskCreateStaticAffinitySet( TaskFunction_t pxTaskCode,
+                                                   const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+                                                   const uint32_t ulStackDepth,
+                                                   void * const pvParameters,
+                                                   UBaseType_t uxPriority,
+                                                   StackType_t * const puxStackBuffer,
+                                                   StaticTask_t * const pxTaskBuffer,
+                                                   UBaseType_t uxCoreAffinityMask )
+        {
+            TaskHandle_t xReturn = NULL;
+            TCB_t * pxNewTCB;
+
+            traceENTER_xTaskCreateStaticAffinitySet( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer, uxCoreAffinityMask );
+
+            pxNewTCB = prvCreateStaticTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer, &xReturn );
+
+            if( pxNewTCB != NULL )
+            {
+                /* Set the task's affinity before scheduling it. */
+                pxNewTCB->uxCoreAffinityMask = uxCoreAffinityMask;
+
+                prvAddNewTaskToReadyList( pxNewTCB );
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+
+            traceRETURN_xTaskCreateStaticAffinitySet( xReturn );
+
+            return xReturn;
+        }
+    #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */
 
 #endif /* SUPPORT_STATIC_ALLOCATION */
 /*-----------------------------------------------------------*/
 
 #if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
-
-    BaseType_t xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition,
-                                            TaskHandle_t * pxCreatedTask )
-    #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
-    {
-        return xTaskCreateRestrictedStaticAffinitySet( pxTaskDefinition, tskNO_AFFINITY, pxCreatedTask );
-    }
-
-    BaseType_t xTaskCreateRestrictedStaticAffinitySet( const TaskParameters_t * const pxTaskDefinition,
-                                                       UBaseType_t uxCoreAffinityMask,
-                                                       TaskHandle_t * pxCreatedTask )
-    #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */
+    static TCB_t * prvCreateRestrictedStaticTask( const TaskParameters_t * const pxTaskDefinition,
+                                                  TaskHandle_t * const pxCreatedTask )
     {
         TCB_t * pxNewTCB;
-        BaseType_t xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
-
-        traceENTER_xTaskCreateRestrictedStatic( pxTaskDefinition, pxCreatedTask );
 
         configASSERT( pxTaskDefinition->puxStackBuffer != NULL );
         configASSERT( pxTaskDefinition->pxTaskBuffer != NULL );
@@ -1324,44 +1404,92 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
                                   pxTaskDefinition->uxPriority,
                                   pxCreatedTask, pxNewTCB,
                                   pxTaskDefinition->xRegions );
+        }
+        else
+        {
+            pxNewTCB = NULL;
+        }
 
+        return pxNewTCB;
+    }
+/*-----------------------------------------------------------*/
+
+    BaseType_t xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition,
+                                            TaskHandle_t * pxCreatedTask )
+    {
+        TCB_t * pxNewTCB;
+        BaseType_t xReturn;
+
+        traceENTER_xTaskCreateRestrictedStatic( pxTaskDefinition, pxCreatedTask );
+
+        configASSERT( pxTaskDefinition != NULL );
+
+        pxNewTCB = prvCreateRestrictedStaticTask( pxTaskDefinition, pxCreatedTask );
+
+        if( pxNewTCB != NULL )
+        {
             #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
             {
                 /* Set the task's affinity before scheduling it. */
-                pxNewTCB->uxCoreAffinityMask = uxCoreAffinityMask;
+                pxNewTCB->uxCoreAffinityMask = tskNO_AFFINITY;
             }
             #endif
 
             prvAddNewTaskToReadyList( pxNewTCB );
             xReturn = pdPASS;
         }
+        else
+        {
+            xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+        }
 
         traceRETURN_xTaskCreateRestrictedStatic( xReturn );
 
         return xReturn;
     }
+/*-----------------------------------------------------------*/
+
+    #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
+        BaseType_t xTaskCreateRestrictedStaticAffinitySet( const TaskParameters_t * const pxTaskDefinition,
+                                                           UBaseType_t uxCoreAffinityMask,
+                                                           TaskHandle_t * pxCreatedTask )
+        {
+            TCB_t * pxNewTCB;
+            BaseType_t xReturn;
+
+            traceENTER_xTaskCreateRestrictedStaticAffinitySet( pxTaskDefinition, uxCoreAffinityMask, pxCreatedTask );
+
+            configASSERT( pxTaskDefinition != NULL );
+
+            pxNewTCB = prvCreateRestrictedStaticTask( pxTaskDefinition, pxCreatedTask );
+
+            if( pxNewTCB != NULL )
+            {
+                /* Set the task's affinity before scheduling it. */
+                pxNewTCB->uxCoreAffinityMask = uxCoreAffinityMask;
+
+                prvAddNewTaskToReadyList( pxNewTCB );
+                xReturn = pdPASS;
+            }
+            else
+            {
+                xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+            }
+
+            traceRETURN_xTaskCreateRestrictedStaticAffinitySet( xReturn );
+
+            return xReturn;
+        }
+    #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */
 
 #endif /* ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
 /*-----------------------------------------------------------*/
 
 #if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
-
-    BaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition,
-                                      TaskHandle_t * pxCreatedTask )
-    #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
-    {
-        return xTaskCreateRestrictedAffinitySet( pxTaskDefinition, tskNO_AFFINITY, pxCreatedTask );
-    }
-
-    BaseType_t xTaskCreateRestrictedAffinitySet( const TaskParameters_t * const pxTaskDefinition,
-                                                 UBaseType_t uxCoreAffinityMask,
-                                                 TaskHandle_t * pxCreatedTask )
-    #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */
+    static TCB_t * prvCreateRestrictedTask( const TaskParameters_t * const pxTaskDefinition,
+                                            TaskHandle_t * const pxCreatedTask )
     {
         TCB_t * pxNewTCB;
-        BaseType_t xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
-
-        traceENTER_xTaskCreateRestricted( pxTaskDefinition, pxCreatedTask );
 
         configASSERT( pxTaskDefinition->puxStackBuffer );
 
@@ -1392,53 +1520,96 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
                                       pxTaskDefinition->uxPriority,
                                       pxCreatedTask, pxNewTCB,
                                       pxTaskDefinition->xRegions );
-
-                #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
-                {
-                    /* Set the task's affinity before scheduling it. */
-                    pxNewTCB->uxCoreAffinityMask = uxCoreAffinityMask;
-                }
-                #endif
-
-                prvAddNewTaskToReadyList( pxNewTCB );
-                xReturn = pdPASS;
             }
         }
+        else
+        {
+            pxNewTCB = NULL;
+        }
+
+        return pxNewTCB;
+    }
+/*-----------------------------------------------------------*/
+
+    BaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition,
+                                      TaskHandle_t * pxCreatedTask )
+    {
+        TCB_t * pxNewTCB;
+        BaseType_t xReturn;
+
+        traceENTER_xTaskCreateRestricted( pxTaskDefinition, pxCreatedTask );
+
+        pxNewTCB = prvCreateRestrictedTask( pxTaskDefinition, pxCreatedTask );
+
+        if( pxNewTCB != NULL )
+        {
+            #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
+            {
+                /* Set the task's affinity before scheduling it. */
+                pxNewTCB->uxCoreAffinityMask = tskNO_AFFINITY;
+            }
+            #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */
+
+            prvAddNewTaskToReadyList( pxNewTCB );
+
+            xReturn = pdPASS;
+        }
+        else
+        {
+            xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+        }
 
         traceRETURN_xTaskCreateRestricted( xReturn );
 
         return xReturn;
     }
+/*-----------------------------------------------------------*/
+
+    #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
+        BaseType_t xTaskCreateRestrictedAffinitySet( const TaskParameters_t * const pxTaskDefinition,
+                                                     UBaseType_t uxCoreAffinityMask,
+                                                     TaskHandle_t * pxCreatedTask )
+        {
+            TCB_t * pxNewTCB;
+            BaseType_t xReturn;
+
+            traceENTER_xTaskCreateRestrictedAffinitySet( pxTaskDefinition, uxCoreAffinityMask, pxCreatedTask );
+
+            pxNewTCB = prvCreateRestrictedTask( pxTaskDefinition, pxCreatedTask );
+
+            if( pxNewTCB != NULL )
+            {
+                /* Set the task's affinity before scheduling it. */
+                pxNewTCB->uxCoreAffinityMask = uxCoreAffinityMask;
+
+                prvAddNewTaskToReadyList( pxNewTCB );
+
+                xReturn = pdPASS;
+            }
+            else
+            {
+                xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+            }
+
+            traceRETURN_xTaskCreateRestrictedAffinitySet( xReturn );
+
+            return xReturn;
+        }
+    #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */
+
 
 #endif /* portUSING_MPU_WRAPPERS */
 /*-----------------------------------------------------------*/
 
 #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-
-    BaseType_t xTaskCreate( TaskFunction_t pxTaskCode,
-                            const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-                            const configSTACK_DEPTH_TYPE usStackDepth,
-                            void * const pvParameters,
-                            UBaseType_t uxPriority,
-                            TaskHandle_t * const pxCreatedTask )
-    #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
-    {
-        return xTaskCreateAffinitySet( pxTaskCode, pcName, usStackDepth, pvParameters, uxPriority, tskNO_AFFINITY, pxCreatedTask );
-    }
-
-    BaseType_t xTaskCreateAffinitySet( TaskFunction_t pxTaskCode,
-                                       const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-                                       const configSTACK_DEPTH_TYPE usStackDepth,
-                                       void * const pvParameters,
-                                       UBaseType_t uxPriority,
-                                       UBaseType_t uxCoreAffinityMask,
-                                       TaskHandle_t * const pxCreatedTask )
-    #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */
+    static TCB_t * prvCreateTask( TaskFunction_t pxTaskCode,
+                                  const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+                                  const configSTACK_DEPTH_TYPE usStackDepth,
+                                  void * const pvParameters,
+                                  UBaseType_t uxPriority,
+                                  TaskHandle_t * const pxCreatedTask )
     {
         TCB_t * pxNewTCB;
-        BaseType_t xReturn;
-
-        traceENTER_xTaskCreate( pxTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask );
 
         /* If the stack grows down then allocate the stack then the TCB so the stack
          * does not grow into the TCB.  Likewise if the stack grows up then allocate
@@ -1511,11 +1682,32 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
             #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
 
             prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL );
+        }
 
+        return pxNewTCB;
+    }
+/*-----------------------------------------------------------*/
+
+    BaseType_t xTaskCreate( TaskFunction_t pxTaskCode,
+                            const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+                            const configSTACK_DEPTH_TYPE usStackDepth,
+                            void * const pvParameters,
+                            UBaseType_t uxPriority,
+                            TaskHandle_t * const pxCreatedTask )
+    {
+        TCB_t * pxNewTCB;
+        BaseType_t xReturn;
+
+        traceENTER_xTaskCreate( pxTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask );
+
+        pxNewTCB = prvCreateTask( pxTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask );
+
+        if( pxNewTCB != NULL )
+        {
             #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
             {
                 /* Set the task's affinity before scheduling it. */
-                pxNewTCB->uxCoreAffinityMask = uxCoreAffinityMask;
+                pxNewTCB->uxCoreAffinityMask = tskNO_AFFINITY;
             }
             #endif
 
@@ -1531,6 +1723,42 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
 
         return xReturn;
     }
+/*-----------------------------------------------------------*/
+
+    #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
+        BaseType_t xTaskCreateAffinitySet( TaskFunction_t pxTaskCode,
+                                           const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+                                           const configSTACK_DEPTH_TYPE usStackDepth,
+                                           void * const pvParameters,
+                                           UBaseType_t uxPriority,
+                                           UBaseType_t uxCoreAffinityMask,
+                                           TaskHandle_t * const pxCreatedTask )
+        {
+            TCB_t * pxNewTCB;
+            BaseType_t xReturn;
+
+            traceENTER_xTaskCreateAffinitySet( pxTaskCode, pcName, usStackDepth, pvParameters, uxPriority, uxCoreAffinityMask, pxCreatedTask );
+
+            pxNewTCB = prvCreateTask( pxTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask );
+
+            if( pxNewTCB != NULL )
+            {
+                /* Set the task's affinity before scheduling it. */
+                pxNewTCB->uxCoreAffinityMask = uxCoreAffinityMask;
+
+                prvAddNewTaskToReadyList( pxNewTCB );
+                xReturn = pdPASS;
+            }
+            else
+            {
+                xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+            }
+
+            traceRETURN_xTaskCreateAffinitySet( xReturn );
+
+            return xReturn;
+        }
+    #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */
 
 #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
 /*-----------------------------------------------------------*/
@@ -1681,18 +1909,6 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
     }
     #endif
 
-    #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
-    {
-        pxNewTCB->uxCoreAffinityMask = tskNO_AFFINITY;
-    }
-    #endif
-
-    #if ( configUSE_TASK_PREEMPTION_DISABLE == 1 )
-    {
-        pxNewTCB->xPreemptionDisable = 0;
-    }
-    #endif
-
     /* Initialize the TCB stack to look as if the task was already running,
      * but had been interrupted by the scheduler.  The return address is set
      * to the start of the task function. Once the stack has been initialised

From 1b2b0904cebfde89ac70446d4c16ac2d14a4d0b6 Mon Sep 17 00:00:00 2001
From: Joseph Julicher <jjulicher@mac.com>
Date: Sat, 14 Oct 2023 08:00:25 -0700
Subject: [PATCH 086/424] Added the minimal example (#823)

* re-adding main.c to the minimal example

* Uncrustify: triggered by comment.

* Update minimal_freertos_example/main.c

Co-authored-by: Soren Ptak <ptaksoren@gmail.com>

* Add in the deleted cmake list

* Added a single newline at the end of the cmake

* Cleanup the CMakelists

* updates the main & Cmake

* Formatting

---------

Co-authored-by: GitHub Action <action@github.com>
Co-authored-by: Soren Ptak <ptaksoren@gmail.com>
---
 cmake_example/CMakeLists.txt |  28 ++++++++++
 cmake_example/main.c         | 105 +++++++++++++++++++++++++++++++++++
 2 files changed, 133 insertions(+)
 create mode 100644 cmake_example/CMakeLists.txt
 create mode 100644 cmake_example/main.c

diff --git a/cmake_example/CMakeLists.txt b/cmake_example/CMakeLists.txt
new file mode 100644
index 000000000..723012039
--- /dev/null
+++ b/cmake_example/CMakeLists.txt
@@ -0,0 +1,28 @@
+cmake_minimum_required(VERSION 3.15)
+
+project(example)
+
+set(FREERTOS_KERNEL_PATH "../")
+
+# Add the freertos_config for FreeRTOS-Kernel
+add_library(freertos_config INTERFACE)
+
+target_include_directories(freertos_config
+    INTERFACE
+    ../sample_configuration
+)
+
+# Select the heap port.  values between 1-4 will pick a heap.
+# set(FREERTOS_HEAP "4" CACHE STRING "" FORCE)
+
+# Select the native compile PORT
+set(FREERTOS_PORT "TEMPLATE" CACHE STRING "" FORCE)
+
+# Adding the FreeRTOS-Kernel subdirectory
+add_subdirectory(${FREERTOS_KERNEL_PATH} FreeRTOS-Kernel)
+
+add_executable(${PROJECT_NAME}
+    main.c
+)
+
+target_link_libraries(${PROJECT_NAME} freertos_kernel freertos_config)
diff --git a/cmake_example/main.c b/cmake_example/main.c
new file mode 100644
index 000000000..f0eaf1cf1
--- /dev/null
+++ b/cmake_example/main.c
@@ -0,0 +1,105 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*
+ * This is a simple main that will start the FreeRTOS-Kernel and run a periodic task
+ * that only delays if compiled with the template port, this project will do nothing.
+ * For more information on getting started please look here:
+ * https://freertos.org/FreeRTOS-quick-start-guide.html
+ */
+
+#include <FreeRTOS.h>
+#include <task.h>
+#include <queue.h>
+#include <timers.h>
+#include <semphr.h>
+
+#include <stdio.h>
+
+static StaticTask_t exampleTaskTCB;
+static StackType_t exampleTaskStack[ configMINIMAL_STACK_SIZE ];
+
+static StaticTask_t xTimerTaskTCB;
+static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ];
+
+static StaticTask_t xIdleTaskTCB;
+static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ];
+
+void exampleTask( void * parameters )
+{
+    for( ; ; )
+    {
+        /* Example Task Code */
+        vTaskDelay( 100 ); /* delay 100 ticks */
+    }
+}
+
+int main( void )
+{
+    printf( "Example FreeRTOS Project\n" );
+
+    xTaskCreateStatic( exampleTask,
+                       "example",
+                       configMINIMAL_STACK_SIZE,
+                       NULL,
+                       configMAX_PRIORITIES - 1,
+                       exampleTaskStack,
+                       &exampleTaskTCB );
+
+    vTaskStartScheduler();
+
+    /* should never get here. */
+    for( ; ; )
+    {
+    }
+
+    return 0;
+}
+
+void vApplicationStackOverflowHook( TaskHandle_t xTask,
+                                    char * pcTaskName )
+{
+}
+
+void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer,
+                                     StackType_t ** ppxTimerTaskStackBuffer,
+                                     uint32_t * pulTimerTaskStackSize )
+{
+    *ppxTimerTaskTCBBuffer = &xTimerTaskTCB;
+    *ppxTimerTaskStackBuffer = uxTimerTaskStack;
+    *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH;
+}
+
+void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer,
+                                    StackType_t ** ppxIdleTaskStackBuffer,
+                                    uint32_t * pulIdleTaskStackSize )
+{
+    *ppxIdleTaskTCBBuffer = &xIdleTaskTCB;
+    *ppxIdleTaskStackBuffer = uxIdleTaskStack;
+    *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;
+}

From 631ae9e6e4828cf5c7d58bb7ac78a64fc309bcb7 Mon Sep 17 00:00:00 2001
From: Sudeep Mohanty <91244425+sudeep-mohanty@users.noreply.github.com>
Date: Mon, 16 Oct 2023 09:08:55 +0200
Subject: [PATCH 087/424] Add option to set the core affinity for the Timer Svc
 Task on SMP systems (#805)

This PR introduces the configTIMER_SERVICE_TASK_CORE_AFFINITY option
which allows the system to configure the core affinity of the Timer
Service Task on an SMP system. The default affinity of the Timer Service
Task is set to tskNO_AFFINITY which is the current behavior on SMP
systems.

Signed-off-by: Sudeep Mohanty <sudp.mohanty@gmail.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
---
 timers.c | 94 ++++++++++++++++++++++++++++++++++++++++++--------------
 1 file changed, 71 insertions(+), 23 deletions(-)

diff --git a/timers.c b/timers.c
index e2f3f9809..bff14ea7e 100644
--- a/timers.c
+++ b/timers.c
@@ -60,12 +60,21 @@
     #define tmrNO_DELAY                    ( ( TickType_t ) 0U )
     #define tmrMAX_TIME_BEFORE_OVERFLOW    ( ( TickType_t ) -1 )
 
-/* The name assigned to the timer service task.  This can be overridden by
- * defining trmTIMER_SERVICE_TASK_NAME in FreeRTOSConfig.h. */
+/* The name assigned to the timer service task. This can be overridden by
+ * defining configTIMER_SERVICE_TASK_NAME in FreeRTOSConfig.h. */
     #ifndef configTIMER_SERVICE_TASK_NAME
         #define configTIMER_SERVICE_TASK_NAME    "Tmr Svc"
     #endif
 
+    #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
+
+/* The core affinity assigned to the timer service task on SMP systems.
+ * This can be overridden by defining configTIMER_SERVICE_TASK_CORE_AFFINITY in FreeRTOSConfig.h. */
+        #ifndef configTIMER_SERVICE_TASK_CORE_AFFINITY
+            #define configTIMER_SERVICE_TASK_CORE_AFFINITY    tskNO_AFFINITY
+        #endif
+    #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */
+
 /* Bit definitions used in the ucStatus member of a timer structure. */
     #define tmrSTATUS_IS_ACTIVE                  ( 0x01U )
     #define tmrSTATUS_IS_STATICALLY_ALLOCATED    ( 0x02U )
@@ -245,36 +254,75 @@
 
         if( xTimerQueue != NULL )
         {
-            #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+            #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
             {
-                StaticTask_t * pxTimerTaskTCBBuffer = NULL;
-                StackType_t * pxTimerTaskStackBuffer = NULL;
-                uint32_t ulTimerTaskStackSize;
+                #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+                {
+                    StaticTask_t * pxTimerTaskTCBBuffer = NULL;
+                    StackType_t * pxTimerTaskStackBuffer = NULL;
+                    uint32_t ulTimerTaskStackSize;
 
-                vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize );
-                xTimerTaskHandle = xTaskCreateStatic( prvTimerTask,
+                    vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize );
+                    xTimerTaskHandle = xTaskCreateStaticAffinitySet( prvTimerTask,
+                                                                     configTIMER_SERVICE_TASK_NAME,
+                                                                     ulTimerTaskStackSize,
+                                                                     NULL,
+                                                                     ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
+                                                                     pxTimerTaskStackBuffer,
+                                                                     pxTimerTaskTCBBuffer,
+                                                                     configTIMER_SERVICE_TASK_CORE_AFFINITY );
+
+                    if( xTimerTaskHandle != NULL )
+                    {
+                        xReturn = pdPASS;
+                    }
+                }
+                #else /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+                {
+                    xReturn = xTaskCreateAffinitySet( prvTimerTask,
                                                       configTIMER_SERVICE_TASK_NAME,
-                                                      ulTimerTaskStackSize,
+                                                      configTIMER_TASK_STACK_DEPTH,
                                                       NULL,
                                                       ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
-                                                      pxTimerTaskStackBuffer,
-                                                      pxTimerTaskTCBBuffer );
-
-                if( xTimerTaskHandle != NULL )
-                {
-                    xReturn = pdPASS;
+                                                      configTIMER_SERVICE_TASK_CORE_AFFINITY,
+                                                      &xTimerTaskHandle );
                 }
+                #endif /* configSUPPORT_STATIC_ALLOCATION */
             }
-            #else /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+            #else /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */
             {
-                xReturn = xTaskCreate( prvTimerTask,
-                                       configTIMER_SERVICE_TASK_NAME,
-                                       configTIMER_TASK_STACK_DEPTH,
-                                       NULL,
-                                       ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
-                                       &xTimerTaskHandle );
+                #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+                {
+                    StaticTask_t * pxTimerTaskTCBBuffer = NULL;
+                    StackType_t * pxTimerTaskStackBuffer = NULL;
+                    uint32_t ulTimerTaskStackSize;
+
+                    vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize );
+                    xTimerTaskHandle = xTaskCreateStatic( prvTimerTask,
+                                                          configTIMER_SERVICE_TASK_NAME,
+                                                          ulTimerTaskStackSize,
+                                                          NULL,
+                                                          ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
+                                                          pxTimerTaskStackBuffer,
+                                                          pxTimerTaskTCBBuffer );
+
+                    if( xTimerTaskHandle != NULL )
+                    {
+                        xReturn = pdPASS;
+                    }
+                }
+                #else /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+                {
+                    xReturn = xTaskCreate( prvTimerTask,
+                                           configTIMER_SERVICE_TASK_NAME,
+                                           configTIMER_TASK_STACK_DEPTH,
+                                           NULL,
+                                           ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
+                                           &xTimerTaskHandle );
+                }
+                #endif /* configSUPPORT_STATIC_ALLOCATION */
             }
-            #endif /* configSUPPORT_STATIC_ALLOCATION */
+            #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */
         }
         else
         {

From 7ffc6a74655ec8a53fdc28fa1cccc74c1c747ecd Mon Sep 17 00:00:00 2001
From: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Date: Tue, 17 Oct 2023 12:19:17 +0800
Subject: [PATCH 088/424] Add base priority get APIs (#818)

* Add base priority get APIs
* Add MPU changes

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: kar-rahul-aws <118818625+kar-rahul-aws@users.noreply.github.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 include/FreeRTOS.h                | 16 +++++++
 include/mpu_prototypes.h          |  2 +
 include/mpu_wrappers.h            |  2 +
 include/task.h                    | 31 ++++++++++++++
 portable/Common/mpu_wrappers_v2.c | 66 ++++++++++++++++++++++++++++
 tasks.c                           | 71 +++++++++++++++++++++++++++++++
 6 files changed, 188 insertions(+)

diff --git a/include/FreeRTOS.h b/include/FreeRTOS.h
index c15eb6d39..ba7d083a6 100644
--- a/include/FreeRTOS.h
+++ b/include/FreeRTOS.h
@@ -1714,6 +1714,22 @@
     #define traceRETURN_uxTaskPriorityGetFromISR( uxReturn )
 #endif
 
+#ifndef traceENTER_uxTaskBasePriorityGet
+    #define traceENTER_uxTaskBasePriorityGet( xTask )
+#endif
+
+#ifndef traceRETURN_uxTaskBasePriorityGet
+    #define traceRETURN_uxTaskBasePriorityGet( uxReturn )
+#endif
+
+#ifndef traceENTER_uxTaskBasePriorityGetFromISR
+    #define traceENTER_uxTaskBasePriorityGetFromISR( xTask )
+#endif
+
+#ifndef traceRETURN_uxTaskBasePriorityGetFromISR
+    #define traceRETURN_uxTaskBasePriorityGetFromISR( uxReturn )
+#endif
+
 #ifndef traceENTER_vTaskPrioritySet
     #define traceENTER_vTaskPrioritySet( xTask, uxNewPriority )
 #endif
diff --git a/include/mpu_prototypes.h b/include/mpu_prototypes.h
index 863bb5678..1c9d8c048 100644
--- a/include/mpu_prototypes.h
+++ b/include/mpu_prototypes.h
@@ -128,6 +128,8 @@ BaseType_t MPU_xTaskGetStaticBuffers( TaskHandle_t xTask,
                                       StackType_t ** ppuxStackBuffer,
                                       StaticTask_t ** ppxTaskBuffer ) PRIVILEGED_FUNCTION;
 UBaseType_t MPU_uxTaskPriorityGetFromISR( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+UBaseType_t MPU_uxTaskBasePriorityGet( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+UBaseType_t MPU_uxTaskBasePriorityGetFromISR( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
 BaseType_t MPU_xTaskResumeFromISR( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION;
 TaskHookFunction_t MPU_xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
 BaseType_t MPU_xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify,
diff --git a/include/mpu_wrappers.h b/include/mpu_wrappers.h
index 162f57ff3..51e7bcf40 100644
--- a/include/mpu_wrappers.h
+++ b/include/mpu_wrappers.h
@@ -99,6 +99,8 @@
             #define vTaskAllocateMPURegions              MPU_vTaskAllocateMPURegions
             #define xTaskGetStaticBuffers                MPU_xTaskGetStaticBuffers
             #define uxTaskPriorityGetFromISR             MPU_uxTaskPriorityGetFromISR
+            #define uxTaskBasePriorityGet                MPU_uxTaskBasePriorityGet
+            #define uxTaskBasePriorityGetFromISR         MPU_uxTaskBasePriorityGetFromISR
             #define xTaskResumeFromISR                   MPU_xTaskResumeFromISR
             #define xTaskGetApplicationTaskTagFromISR    MPU_xTaskGetApplicationTaskTagFromISR
             #define xTaskGenericNotifyFromISR            MPU_xTaskGenericNotifyFromISR
diff --git a/include/task.h b/include/task.h
index de3ab5531..b6850e8bd 100644
--- a/include/task.h
+++ b/include/task.h
@@ -1021,6 +1021,37 @@ UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
  */
 UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
 
+/**
+ * task. h
+ * @code{c}
+ * UBaseType_t uxTaskBasePriorityGet( const TaskHandle_t xTask );
+ * @endcode
+ *
+ * INCLUDE_uxTaskPriorityGet and configUSE_MUTEXES must be defined as 1 for this
+ * function to be available. See the configuration section for more information.
+ *
+ * Obtain the base priority of any task.
+ *
+ * @param xTask Handle of the task to be queried.  Passing a NULL
+ * handle results in the base priority of the calling task being returned.
+ *
+ * @return The base priority of xTask.
+ *
+ * \defgroup uxTaskPriorityGet uxTaskBasePriorityGet
+ * \ingroup TaskCtrl
+ */
+UBaseType_t uxTaskBasePriorityGet( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * @code{c}
+ * UBaseType_t uxTaskBasePriorityGetFromISR( const TaskHandle_t xTask );
+ * @endcode
+ *
+ * A version of uxTaskBasePriorityGet() that can be used from an ISR.
+ */
+UBaseType_t uxTaskBasePriorityGetFromISR( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
 /**
  * task. h
  * @code{c}
diff --git a/portable/Common/mpu_wrappers_v2.c b/portable/Common/mpu_wrappers_v2.c
index 9db5772ad..0f2dc654b 100644
--- a/portable/Common/mpu_wrappers_v2.c
+++ b/portable/Common/mpu_wrappers_v2.c
@@ -1894,6 +1894,72 @@
     #endif /* #if ( INCLUDE_uxTaskPriorityGet == 1 ) */
 /*-----------------------------------------------------------*/
 
+    #if ( ( INCLUDE_uxTaskPriorityGet == 1 ) && ( configUSE_MUTEXES == 1 ) )
+
+        UBaseType_t MPU_uxTaskBasePriorityGet( const TaskHandle_t xTask ) /* PRIVILEGED_FUNCTION */
+        {
+            UBaseType_t uxReturn = configMAX_PRIORITIES;
+            int32_t lIndex;
+            TaskHandle_t xInternalTaskHandle = NULL;
+
+            if( xTask == NULL )
+            {
+                uxReturn = uxTaskBasePriorityGet( xTask );
+            }
+            else
+            {
+                lIndex = ( int32_t ) xTask;
+
+                if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+                {
+                    xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                    if( xInternalTaskHandle != NULL )
+                    {
+                        uxReturn = uxTaskBasePriorityGet( xInternalTaskHandle );
+                    }
+                }
+            }
+
+            return uxReturn;
+        }
+
+    #endif /* #if ( ( INCLUDE_uxTaskPriorityGet == 1 ) && ( configUSE_MUTEXES == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+    #if ( ( INCLUDE_uxTaskPriorityGet == 1 ) && ( configUSE_MUTEXES == 1 ) )
+
+        UBaseType_t MPU_uxTaskBasePriorityGetFromISR( const TaskHandle_t xTask ) /* PRIVILEGED_FUNCTION */
+        {
+            UBaseType_t uxReturn = configMAX_PRIORITIES;
+            int32_t lIndex;
+            TaskHandle_t xInternalTaskHandle = NULL;
+
+            if( xTask == NULL )
+            {
+                uxReturn = uxTaskBasePriorityGetFromISR( xTask );
+            }
+            else
+            {
+                lIndex = ( int32_t ) xTask;
+
+                if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+                {
+                    xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                    if( xInternalTaskHandle != NULL )
+                    {
+                        uxReturn = uxTaskBasePriorityGetFromISR( xInternalTaskHandle );
+                    }
+                }
+            }
+
+            return uxReturn;
+        }
+
+    #endif /* #if ( ( INCLUDE_uxTaskPriorityGet == 1 ) && ( configUSE_MUTEXES == 1 ) ) */
+/*-----------------------------------------------------------*/
+
     #if ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) )
 
         BaseType_t MPU_xTaskResumeFromISR( TaskHandle_t xTaskToResume ) /* PRIVILEGED_FUNCTION */
diff --git a/tasks.c b/tasks.c
index 2cd130a82..6edf36ff3 100644
--- a/tasks.c
+++ b/tasks.c
@@ -2669,6 +2669,77 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
 #endif /* INCLUDE_uxTaskPriorityGet */
 /*-----------------------------------------------------------*/
 
+#if ( ( INCLUDE_uxTaskPriorityGet == 1 ) && ( configUSE_MUTEXES == 1 ) )
+
+    UBaseType_t uxTaskBasePriorityGet( const TaskHandle_t xTask )
+    {
+        TCB_t const * pxTCB;
+        UBaseType_t uxReturn;
+
+        traceENTER_uxTaskBasePriorityGet( xTask );
+
+        taskENTER_CRITICAL();
+        {
+            /* If null is passed in here then it is the base priority of the task
+             * that called uxTaskBasePriorityGet() that is being queried. */
+            pxTCB = prvGetTCBFromHandle( xTask );
+            uxReturn = pxTCB->uxBasePriority;
+        }
+        taskEXIT_CRITICAL();
+
+        traceRETURN_uxTaskBasePriorityGet( uxReturn );
+
+        return uxReturn;
+    }
+
+#endif /* #if ( ( INCLUDE_uxTaskPriorityGet == 1 ) && ( configUSE_MUTEXES == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( INCLUDE_uxTaskPriorityGet == 1 ) && ( configUSE_MUTEXES == 1 ) )
+
+    UBaseType_t uxTaskBasePriorityGetFromISR( const TaskHandle_t xTask )
+    {
+        TCB_t const * pxTCB;
+        UBaseType_t uxReturn;
+        UBaseType_t uxSavedInterruptStatus;
+
+        traceENTER_uxTaskBasePriorityGetFromISR( xTask );
+
+        /* RTOS ports that support interrupt nesting have the concept of a
+         * maximum  system call (or maximum API call) interrupt priority.
+         * Interrupts that are  above the maximum system call priority are keep
+         * permanently enabled, even when the RTOS kernel is in a critical section,
+         * but cannot make any calls to FreeRTOS API functions.  If configASSERT()
+         * is defined in FreeRTOSConfig.h then
+         * portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+         * failure if a FreeRTOS API function is called from an interrupt that has
+         * been assigned a priority above the configured maximum system call
+         * priority.  Only FreeRTOS functions that end in FromISR can be called
+         * from interrupts  that have been assigned a priority at or (logically)
+         * below the maximum system call interrupt priority.  FreeRTOS maintains a
+         * separate interrupt safe API to ensure interrupt entry is as fast and as
+         * simple as possible.  More information (albeit Cortex-M specific) is
+         * provided on the following link:
+         * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+        portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+        uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
+        {
+            /* If null is passed in here then it is the base priority of the calling
+             * task that is being queried. */
+            pxTCB = prvGetTCBFromHandle( xTask );
+            uxReturn = pxTCB->uxBasePriority;
+        }
+        taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
+
+        traceRETURN_uxTaskBasePriorityGetFromISR( uxReturn );
+
+        return uxReturn;
+    }
+
+#endif /* #if ( ( INCLUDE_uxTaskPriorityGet == 1 ) && ( configUSE_MUTEXES == 1 ) ) */
+/*-----------------------------------------------------------*/
+
 #if ( INCLUDE_vTaskPrioritySet == 1 )
 
     void vTaskPrioritySet( TaskHandle_t xTask,

From 30283b57dfd23f017389f0cfaf9318f7f2469027 Mon Sep 17 00:00:00 2001
From: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Date: Tue, 17 Oct 2023 15:05:18 +0530
Subject: [PATCH 089/424] Fix xTaskNotifyWait & ulTaskNotifyTake determinism.
 (#833)

This PR fixes the bug described in the following issue:
https://github.com/FreeRTOS/FreeRTOS-Kernel/issues/612.
This was originally contributed in the following PR:
https://github.com/FreeRTOS/FreeRTOS-Kernel/pull/625.

The implementation suspends the scheduler before exiting the
critical section (i.e. before enabling interrupts). If we do not do
so, a notification sent from an ISR, which happens after exiting
the critical section and before suspending the scheduler, will
get lost. The sequence of events will be:

1. Exit critical section.
2. Interrupt - ISR calls xTaskNotifyFromISR which adds the task to
    the Ready list.
3. Suspend scheduler.
4. prvAddCurrentTaskToDelayedList moves the task to the delayed
    or suspended list.
5. Resume scheduler does not touch the task (because it is not on
    the pendingReady list), effectively losing the notification from
    the ISR.

The same does not happen when we suspend the scheduler before
exiting the critical section. The sequence of events in this case will
be:

1. Suspend scheduler.
2. Exit critical section.
3. Interrupt - ISR calls xTaskNotifyFromISR which adds the task to
    the pendingReady list as the scheduler is suspended.
4. prvAddCurrentTaskToDelayedList adds the task to delayed or
    suspended list. Note that this operation does not nullify the add
    to pendingReady list done in the above step because a different
    list item, namely xEventListItem, is used for adding the task to the
    pendingReady list. In other words, the task still remains on the
    pendingReady list.
5. Resume scheduler moves the task from pendingReady list to the Ready list.

------------

Co-authored-by: Jacob Carver <karver8@github.com>
---
 tasks.c | 151 +++++++++++++++++++++++++++++++++++++++++++-------------
 1 file changed, 118 insertions(+), 33 deletions(-)

diff --git a/tasks.c b/tasks.c
index 6edf36ff3..e941907cf 100644
--- a/tasks.c
+++ b/tasks.c
@@ -5198,7 +5198,7 @@ void vTaskPlaceOnEventList( List_t * const pxEventList,
 
     configASSERT( pxEventList );
 
-    /* THIS FUNCTION MUST BE CALLED WITH EITHER INTERRUPTS DISABLED OR THE
+    /* THIS FUNCTION MUST BE CALLED WITH THE
      * SCHEDULER SUSPENDED AND THE QUEUE BEING ACCESSED LOCKED. */
 
     /* Place the event list item of the TCB in the appropriate event list.
@@ -7480,28 +7480,68 @@ TickType_t uxTaskResetEventItemValue( void )
                                       TickType_t xTicksToWait )
     {
         uint32_t ulReturn;
+        BaseType_t xAlreadyYielded;
 
         traceENTER_ulTaskGenericNotifyTake( uxIndexToWaitOn, xClearCountOnExit, xTicksToWait );
 
         configASSERT( uxIndexToWaitOn < configTASK_NOTIFICATION_ARRAY_ENTRIES );
 
         taskENTER_CRITICAL();
+
+        /* Only block if the notification count is not already non-zero. */
+        if( pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ] == 0UL )
         {
-            /* Only block if the notification count is not already non-zero. */
-            if( pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ] == 0UL )
+            /* Mark this task as waiting for a notification. */
+            pxCurrentTCB->ucNotifyState[ uxIndexToWaitOn ] = taskWAITING_NOTIFICATION;
+
+            if( xTicksToWait > ( TickType_t ) 0 )
             {
-                /* Mark this task as waiting for a notification. */
-                pxCurrentTCB->ucNotifyState[ uxIndexToWaitOn ] = taskWAITING_NOTIFICATION;
+                traceTASK_NOTIFY_TAKE_BLOCK( uxIndexToWaitOn );
 
-                if( xTicksToWait > ( TickType_t ) 0 )
+                /* We MUST suspend the scheduler before exiting the critical
+                 * section (i.e. before enabling interrupts).
+                 *
+                 * If we do not do so, a notification sent from an ISR, which
+                 * happens after exiting the critical section and before
+                 * suspending the scheduler, will get lost. The sequence of
+                 * events will be:
+                 * 1. Exit critical section.
+                 * 2. Interrupt - ISR calls xTaskNotifyFromISR which adds the
+                 *    task to the Ready list.
+                 * 3. Suspend scheduler.
+                 * 4. prvAddCurrentTaskToDelayedList moves the task to the
+                 *    delayed or suspended list.
+                 * 5. Resume scheduler does not touch the task (because it is
+                 *    not on the pendingReady list), effectively losing the
+                 *    notification from the ISR.
+                 *
+                 * The same does not happen when we suspend the scheduler before
+                 * exiting the critical section. The sequence of events in this
+                 * case will be:
+                 * 1. Suspend scheduler.
+                 * 2. Exit critical section.
+                 * 3. Interrupt - ISR calls xTaskNotifyFromISR which adds the
+                 *    task to the pendingReady list as the scheduler is
+                 *    suspended.
+                 * 4. prvAddCurrentTaskToDelayedList adds the task to delayed or
+                 *    suspended list. Note that this operation does not nullify
+                 *    the add to pendingReady list done in the above step because
+                 *    a different list item, namely xEventListItem, is used for
+                 *    adding the task to the pendingReady list. In other words,
+                 *    the task still remains on the pendingReady list.
+                 * 5. Resume scheduler moves the task from pendingReady list to
+                 *    the Ready list.
+                 */
+                vTaskSuspendAll();
                 {
-                    prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
-                    traceTASK_NOTIFY_TAKE_BLOCK( uxIndexToWaitOn );
+                    taskEXIT_CRITICAL();
 
-                    /* All ports are written to allow a yield in a critical
-                     * section (some will yield immediately, others wait until the
-                     * critical section exits) - but it is not something that
-                     * application code should ever do. */
+                    prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+                }
+                xAlreadyYielded = xTaskResumeAll();
+
+                if( xAlreadyYielded == pdFALSE )
+                {
                     taskYIELD_WITHIN_API();
                 }
                 else
@@ -7511,10 +7551,13 @@ TickType_t uxTaskResetEventItemValue( void )
             }
             else
             {
-                mtCOVERAGE_TEST_MARKER();
+                taskEXIT_CRITICAL();
             }
         }
-        taskEXIT_CRITICAL();
+        else
+        {
+            taskEXIT_CRITICAL();
+        }
 
         taskENTER_CRITICAL();
         {
@@ -7557,34 +7600,73 @@ TickType_t uxTaskResetEventItemValue( void )
                                        uint32_t * pulNotificationValue,
                                        TickType_t xTicksToWait )
     {
-        BaseType_t xReturn;
+        BaseType_t xReturn, xAlreadyYielded;
 
         traceENTER_xTaskGenericNotifyWait( uxIndexToWaitOn, ulBitsToClearOnEntry, ulBitsToClearOnExit, pulNotificationValue, xTicksToWait );
 
         configASSERT( uxIndexToWaitOn < configTASK_NOTIFICATION_ARRAY_ENTRIES );
 
         taskENTER_CRITICAL();
+
+        /* Only block if a notification is not already pending. */
+        if( pxCurrentTCB->ucNotifyState[ uxIndexToWaitOn ] != taskNOTIFICATION_RECEIVED )
         {
-            /* Only block if a notification is not already pending. */
-            if( pxCurrentTCB->ucNotifyState[ uxIndexToWaitOn ] != taskNOTIFICATION_RECEIVED )
+            /* Clear bits in the task's notification value as bits may get
+             * set  by the notifying task or interrupt.  This can be used to
+             * clear the value to zero. */
+            pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ] &= ~ulBitsToClearOnEntry;
+
+            /* Mark this task as waiting for a notification. */
+            pxCurrentTCB->ucNotifyState[ uxIndexToWaitOn ] = taskWAITING_NOTIFICATION;
+
+            if( xTicksToWait > ( TickType_t ) 0 )
             {
-                /* Clear bits in the task's notification value as bits may get
-                 * set  by the notifying task or interrupt.  This can be used to
-                 * clear the value to zero. */
-                pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ] &= ~ulBitsToClearOnEntry;
+                traceTASK_NOTIFY_WAIT_BLOCK( uxIndexToWaitOn );
 
-                /* Mark this task as waiting for a notification. */
-                pxCurrentTCB->ucNotifyState[ uxIndexToWaitOn ] = taskWAITING_NOTIFICATION;
-
-                if( xTicksToWait > ( TickType_t ) 0 )
+                /* We MUST suspend the scheduler before exiting the critical
+                 * section (i.e. before enabling interrupts).
+                 *
+                 * If we do not do so, a notification sent from an ISR, which
+                 * happens after exiting the critical section and before
+                 * suspending the scheduler, will get lost. The sequence of
+                 * events will be:
+                 * 1. Exit critical section.
+                 * 2. Interrupt - ISR calls xTaskNotifyFromISR which adds the
+                 *    task to the Ready list.
+                 * 3. Suspend scheduler.
+                 * 4. prvAddCurrentTaskToDelayedList moves the task to the
+                 *    delayed or suspended list.
+                 * 5. Resume scheduler does not touch the task (because it is
+                 *    not on the pendingReady list), effectively losing the
+                 *    notification from the ISR.
+                 *
+                 * The same does not happen when we suspend the scheduler before
+                 * exiting the critical section. The sequence of events in this
+                 * case will be:
+                 * 1. Suspend scheduler.
+                 * 2. Exit critical section.
+                 * 3. Interrupt - ISR calls xTaskNotifyFromISR which adds the
+                 *    task to the pendingReady list as the scheduler is
+                 *    suspended.
+                 * 4. prvAddCurrentTaskToDelayedList adds the task to delayed or
+                 *    suspended list. Note that this operation does not nullify
+                 *    the add to pendingReady list done in the above step because
+                 *    a different list item, namely xEventListItem, is used for
+                 *    adding the task to the pendingReady list. In other words,
+                 *    the task still remains on the pendingReady list.
+                 * 5. Resume scheduler moves the task from pendingReady list to
+                 *    the Ready list.
+                 */
+                vTaskSuspendAll();
                 {
-                    prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
-                    traceTASK_NOTIFY_WAIT_BLOCK( uxIndexToWaitOn );
+                    taskEXIT_CRITICAL();
 
-                    /* All ports are written to allow a yield in a critical
-                     * section (some will yield immediately, others wait until the
-                     * critical section exits) - but it is not something that
-                     * application code should ever do. */
+                    prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+                }
+                xAlreadyYielded = xTaskResumeAll();
+
+                if( xAlreadyYielded == pdFALSE )
+                {
                     taskYIELD_WITHIN_API();
                 }
                 else
@@ -7594,10 +7676,13 @@ TickType_t uxTaskResetEventItemValue( void )
             }
             else
             {
-                mtCOVERAGE_TEST_MARKER();
+                taskEXIT_CRITICAL();
             }
         }
-        taskEXIT_CRITICAL();
+        else
+        {
+            taskEXIT_CRITICAL();
+        }
 
         taskENTER_CRITICAL();
         {

From 59ba98b2e3f4e8abe745e7e239c84575eecbd73b Mon Sep 17 00:00:00 2001
From: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Date: Tue, 17 Oct 2023 19:59:37 +0530
Subject: [PATCH 090/424] Fix reliability issues in CMake sample (#835)

* Fix reliability issues in CMake example sample.
---
 cmake_example/main.c | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/cmake_example/main.c b/cmake_example/main.c
index f0eaf1cf1..d00aeae72 100644
--- a/cmake_example/main.c
+++ b/cmake_example/main.c
@@ -52,6 +52,9 @@ static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ];
 
 void exampleTask( void * parameters )
 {
+    /* Unused parameters. */
+    ( void ) parameters;
+
     for( ; ; )
     {
         /* Example Task Code */
@@ -59,7 +62,7 @@ void exampleTask( void * parameters )
     }
 }
 
-int main( void )
+void main( void )
 {
     printf( "Example FreeRTOS Project\n" );
 
@@ -71,19 +74,22 @@ int main( void )
                        exampleTaskStack,
                        &exampleTaskTCB );
 
+    /* Start the scheduler. */
     vTaskStartScheduler();
 
-    /* should never get here. */
     for( ; ; )
     {
+        /* Should not reach here. */
     }
-
-    return 0;
 }
 
 void vApplicationStackOverflowHook( TaskHandle_t xTask,
                                     char * pcTaskName )
 {
+    /* Check pcTaskName for the name of the offending task,
+     * or pxCurrentTCB if pcTaskName has itself been corrupted. */
+    ( void ) xTask;
+    ( void ) pcTaskName;
 }
 
 void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer,

From 4ada1d7d5e853f0f9415dc99cafae72eaf571b59 Mon Sep 17 00:00:00 2001
From: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Date: Tue, 17 Oct 2023 21:31:43 +0530
Subject: [PATCH 091/424] Fix possible integer overflow (#836)

* Fix possible integer overflow

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 portable/Common/mpu_wrappers_v2.c | 41 ++++++++++++++++++++-----------
 1 file changed, 27 insertions(+), 14 deletions(-)

diff --git a/portable/Common/mpu_wrappers_v2.c b/portable/Common/mpu_wrappers_v2.c
index 0f2dc654b..30efa0773 100644
--- a/portable/Common/mpu_wrappers_v2.c
+++ b/portable/Common/mpu_wrappers_v2.c
@@ -112,6 +112,16 @@
  */
     #define CONVERT_TO_INTERNAL_INDEX( lIndex )    ( ( lIndex ) - INDEX_OFFSET )
 
+/**
+ * @brief Max value that fits in a size_t type.
+ */
+    #define mpuSIZE_MAX    ( ~( ( size_t ) 0 ) )
+
+/**
+ * @brief Check if multiplying a and b will result in overflow.
+ */
+    #define mpuMULTIPLY_WILL_OVERFLOW( a, b )    ( ( ( a ) > 0 ) && ( ( b ) > ( mpuSIZE_MAX / ( a ) ) ) )
+
 /**
  * @brief Get the index of a free slot in the kernel object pool.
  *
@@ -1035,25 +1045,28 @@
                                                   UBaseType_t uxArraySize,
                                                   configRUN_TIME_COUNTER_TYPE * pulTotalRunTime ) /* PRIVILEGED_FUNCTION */
         {
-            UBaseType_t uxReturn = pdFALSE;
+            UBaseType_t uxReturn = 0;
             UBaseType_t xIsTaskStatusArrayWriteable = pdFALSE;
             UBaseType_t xIsTotalRunTimeWriteable = pdFALSE;
 
-            xIsTaskStatusArrayWriteable = xPortIsAuthorizedToAccessBuffer( pxTaskStatusArray,
-                                                                           sizeof( TaskStatus_t ) * uxArraySize,
-                                                                           tskMPU_WRITE_PERMISSION );
-
-            if( pulTotalRunTime != NULL )
+            if( mpuMULTIPLY_WILL_OVERFLOW( sizeof( TaskStatus_t ), uxArraySize ) == 0 )
             {
-                xIsTotalRunTimeWriteable = xPortIsAuthorizedToAccessBuffer( pulTotalRunTime,
-                                                                            sizeof( configRUN_TIME_COUNTER_TYPE ),
-                                                                            tskMPU_WRITE_PERMISSION );
-            }
+                xIsTaskStatusArrayWriteable = xPortIsAuthorizedToAccessBuffer( pxTaskStatusArray,
+                                                                               sizeof( TaskStatus_t ) * uxArraySize,
+                                                                               tskMPU_WRITE_PERMISSION );
 
-            if( ( xIsTaskStatusArrayWriteable == pdTRUE ) &&
-                ( ( pulTotalRunTime == NULL ) || ( xIsTotalRunTimeWriteable == pdTRUE ) ) )
-            {
-                uxReturn = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, pulTotalRunTime );
+                if( pulTotalRunTime != NULL )
+                {
+                    xIsTotalRunTimeWriteable = xPortIsAuthorizedToAccessBuffer( pulTotalRunTime,
+                                                                                sizeof( configRUN_TIME_COUNTER_TYPE ),
+                                                                                tskMPU_WRITE_PERMISSION );
+                }
+
+                if( ( xIsTaskStatusArrayWriteable == pdTRUE ) &&
+                    ( ( pulTotalRunTime == NULL ) || ( xIsTotalRunTimeWriteable == pdTRUE ) ) )
+                {
+                    uxReturn = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, pulTotalRunTime );
+                }
             }
 
             return uxReturn;

From 220771565f3e8397409a6bc7520db00e7038efe8 Mon Sep 17 00:00:00 2001
From: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Date: Thu, 19 Oct 2023 11:20:19 +0530
Subject: [PATCH 092/424] Removes redundant API calls in MPU wrappers (#838)

* Remove redundant API calls in Queue wrappers
---
 portable/Common/mpu_wrappers_v2.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/portable/Common/mpu_wrappers_v2.c b/portable/Common/mpu_wrappers_v2.c
index 30efa0773..fb4bd45fe 100644
--- a/portable/Common/mpu_wrappers_v2.c
+++ b/portable/Common/mpu_wrappers_v2.c
@@ -2133,7 +2133,7 @@
                         if( pvItemToQueue != NULL )
                         {
                             xIsItemToQueueReadable = xPortIsAuthorizedToAccessBuffer( pvItemToQueue,
-                                                                                      uxQueueGetQueueItemSize( xInternalQueueHandle ),
+                                                                                      uxQueueItemSize,
                                                                                       tskMPU_READ_PERMISSION );
                         }
 
@@ -2246,7 +2246,7 @@
                         )
                     {
                         xIsReceiveBufferWritable = xPortIsAuthorizedToAccessBuffer( pvBuffer,
-                                                                                    uxQueueGetQueueItemSize( xInternalQueueHandle ),
+                                                                                    uxQueueItemSize,
                                                                                     tskMPU_WRITE_PERMISSION );
 
                         if( xIsReceiveBufferWritable == pdTRUE )
@@ -2298,7 +2298,7 @@
                         )
                     {
                         xIsReceiveBufferWritable = xPortIsAuthorizedToAccessBuffer( pvBuffer,
-                                                                                    uxQueueGetQueueItemSize( xInternalQueueHandle ),
+                                                                                    uxQueueItemSize,
                                                                                     tskMPU_WRITE_PERMISSION );
 
                         if( xIsReceiveBufferWritable == pdTRUE )

From b32aafe4dc16cb2474e0516019c2356cd01fb1c1 Mon Sep 17 00:00:00 2001
From: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Date: Thu, 19 Oct 2023 12:08:22 +0530
Subject: [PATCH 093/424] Fix size alignment in the integer overflow issue
 (#839)

---
 portable/Common/mpu_wrappers_v2.c | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/portable/Common/mpu_wrappers_v2.c b/portable/Common/mpu_wrappers_v2.c
index fb4bd45fe..87e849edf 100644
--- a/portable/Common/mpu_wrappers_v2.c
+++ b/portable/Common/mpu_wrappers_v2.c
@@ -113,14 +113,14 @@
     #define CONVERT_TO_INTERNAL_INDEX( lIndex )    ( ( lIndex ) - INDEX_OFFSET )
 
 /**
- * @brief Max value that fits in a size_t type.
+ * @brief Max value that fits in a uint32_t type.
  */
-    #define mpuSIZE_MAX    ( ~( ( size_t ) 0 ) )
+    #define mpuUINT32_MAX    ( ~( ( uint32_t ) 0 ) )
 
 /**
  * @brief Check if multiplying a and b will result in overflow.
  */
-    #define mpuMULTIPLY_WILL_OVERFLOW( a, b )    ( ( ( a ) > 0 ) && ( ( b ) > ( mpuSIZE_MAX / ( a ) ) ) )
+    #define mpuMULTIPLY_UINT32_WILL_OVERFLOW( a, b )    ( ( ( a ) > 0 ) && ( ( b ) > ( mpuUINT32_MAX / ( a ) ) ) )
 
 /**
  * @brief Get the index of a free slot in the kernel object pool.
@@ -1048,11 +1048,13 @@
             UBaseType_t uxReturn = 0;
             UBaseType_t xIsTaskStatusArrayWriteable = pdFALSE;
             UBaseType_t xIsTotalRunTimeWriteable = pdFALSE;
+            uint32_t ulArraySize = ( uint32_t ) uxArraySize;
+            uint32_t ulTaskStatusSize = ( uint32_t ) sizeof( TaskStatus_t );
 
-            if( mpuMULTIPLY_WILL_OVERFLOW( sizeof( TaskStatus_t ), uxArraySize ) == 0 )
+            if( mpuMULTIPLY_UINT32_WILL_OVERFLOW( ulTaskStatusSize, ulArraySize ) == 0 )
             {
                 xIsTaskStatusArrayWriteable = xPortIsAuthorizedToAccessBuffer( pxTaskStatusArray,
-                                                                               sizeof( TaskStatus_t ) * uxArraySize,
+                                                                               ulTaskStatusSize * ulArraySize,
                                                                                tskMPU_WRITE_PERMISSION );
 
                 if( pulTotalRunTime != NULL )
@@ -1065,7 +1067,7 @@
                 if( ( xIsTaskStatusArrayWriteable == pdTRUE ) &&
                     ( ( pulTotalRunTime == NULL ) || ( xIsTotalRunTimeWriteable == pdTRUE ) ) )
                 {
-                    uxReturn = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, pulTotalRunTime );
+                    uxReturn = uxTaskGetSystemState( pxTaskStatusArray, ( UBaseType_t ) ulArraySize, pulTotalRunTime );
                 }
             }
 

From a936a1b156450f2454b335f711776c8cce9bc668 Mon Sep 17 00:00:00 2001
From: Soren Ptak <ptaksoren@gmail.com>
Date: Thu, 19 Oct 2023 10:08:24 -0700
Subject: [PATCH 094/424] Kernel Checker CI Workflow File Updates (#804)

* Perform sparse checkout of just the .github folder for the header check instead of all the files. Update python checkout version being used. Update the version of the get changed files action being used.

* Use echo groups on the header check
---
 .github/workflows/kernel-checks.yml | 37 +++++++++++++++++++++++------
 1 file changed, 30 insertions(+), 7 deletions(-)

diff --git a/.github/workflows/kernel-checks.yml b/.github/workflows/kernel-checks.yml
index 679ede23e..cfaec5b12 100644
--- a/.github/workflows/kernel-checks.yml
+++ b/.github/workflows/kernel-checks.yml
@@ -9,10 +9,7 @@ jobs:
     steps:
       # Install python 3
       - name: Tool Setup
-        uses: actions/setup-python@v2
-        with:
-          python-version: 3.7.10
-          architecture:   x64
+        uses: actions/setup-python@v3
         env:
           GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
 
@@ -21,6 +18,7 @@ jobs:
         uses: actions/checkout@v3
         with:
           repository: FreeRTOS/FreeRTOS
+          sparse-checkout: '.github'
           ref:  main
           path: tools
 
@@ -32,15 +30,40 @@ jobs:
 
       # Collect all affected files
       - name: Collecting changed files
-        uses: lots0logs/gh-action-get-changed-files@2.1.4
+        uses: lots0logs/gh-action-get-changed-files@2.2.2
         with:
           token: ${{ secrets.GITHUB_TOKEN }}
 
       # Run checks
-      - name: Check File Headers
+      - env:
+          bashPass: \033[32;1mPASSED -
+          bashInfo: \033[33;1mINFO -
+          bashFail: \033[31;1mFAILED -
+          bashEnd:  \033[0m
+          stepName: Check File Headers
+        name: ${{ env.stepName }}
+        shell: bash
         run: |
+          # ${{ env.stepName }}
+          echo -e "::group::${{ env.bashInfo }} Install Dependencies ${{ env.bashEnd }}"
+
+          # Copy the common tools from the FreeRTOS/FreeRTOS repo.
           mv tools/.github/scripts/common inspect/.github/scripts
+
+          # Install the necessary python dependencies
           pip install -r inspect/.github/scripts/common/requirements.txt
           cd inspect
+
+          echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}"
+
+          # Use the python script to check the copyright header of modified files.
           .github/scripts/kernel_checker.py --json ${HOME}/files_modified.json ${HOME}/files_added.json ${HOME}/files_renamed.json
-          exit $?
+          exitStatus=$?
+          echo -e "::endgroup::"
+
+          if [ $exitStatus -eq 0 ]; then
+            echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }}"
+          else
+            echo -e "${{ env.bashFail }} ${{ env.stepName }} ${{ env.bashEnd }}"
+          fi
+          exit $exitStatus

From 7562ebc6e13ae560de98b00ac96c2d518b0c6639 Mon Sep 17 00:00:00 2001
From: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Date: Fri, 20 Oct 2023 22:08:03 +0530
Subject: [PATCH 095/424] Covert object type check to runtime check (#846)

* Covert object type check to runtime check

It was checked using assert earlier.

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 portable/Common/mpu_wrappers_v2.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/portable/Common/mpu_wrappers_v2.c b/portable/Common/mpu_wrappers_v2.c
index 87e849edf..beb21d271 100644
--- a/portable/Common/mpu_wrappers_v2.c
+++ b/portable/Common/mpu_wrappers_v2.c
@@ -324,9 +324,16 @@
     static OpaqueObjectHandle_t MPU_GetHandleAtIndex( int32_t lIndex,
                                                       uint32_t ulKernelObjectType ) /* PRIVILEGED_FUNCTION */
     {
+        OpaqueObjectHandle_t xObjectHandle = NULL;
+
         configASSERT( IS_INTERNAL_INDEX_VALID( lIndex ) != pdFALSE );
-        configASSERT( xKernelObjectPool[ lIndex ].ulKernelObjectType == ulKernelObjectType );
-        return xKernelObjectPool[ lIndex ].xInternalObjectHandle;
+
+        if( xKernelObjectPool[ lIndex ].ulKernelObjectType == ulKernelObjectType )
+        {
+            xObjectHandle = xKernelObjectPool[ lIndex ].xInternalObjectHandle;
+        }
+
+        return xObjectHandle;
     }
 /*-----------------------------------------------------------*/
 

From 9f4a0e308b311e9fa7ae112a74a27b62a2bbb138 Mon Sep 17 00:00:00 2001
From: Boris van der Meer <borisvandermeer@hotmail.com>
Date: Mon, 23 Oct 2023 08:57:54 +0200
Subject: [PATCH 096/424] Remove default behaviour of FREERTOS_HEAP. (#807)

To build a complete static application (configSUPPORT_DYNAMIC_ALLOCATION
set to 0) an ugly workaround is necessary, because when FREERTOS_HEAP is
not set, heap 4 is automatically selected in the current CMake.

Co-authored-by: kar-rahul-aws <118818625+kar-rahul-aws@users.noreply.github.com>
Co-authored-by: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Co-authored-by: Soren Ptak <ptaksoren@gmail.com>
---
 CMakeLists.txt | 22 +++++++++++++---------
 1 file changed, 13 insertions(+), 9 deletions(-)

diff --git a/CMakeLists.txt b/CMakeLists.txt
index 5d27a58c6..984e36ecd 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -8,10 +8,12 @@ cmake_minimum_required(VERSION 3.15)
 #
 # DEPRECATED: FREERTOS_CONFIG_FILE_DIRECTORY - but still supported if no freertos_config defined for now.
 #             May be removed at some point in the future.
+#
 # User can choose which heap implementation to use (either the implementations
-# included with FreeRTOS [1..5] or a custom implementation ) by providing the
-# option FREERTOS_HEAP. If the option is not set, the cmake will default to
-# using heap_4.c.
+# included with FreeRTOS [1..5] or a custom implementation) by providing the
+# option FREERTOS_HEAP. When dynamic allocation is used, the user must specify a
+# heap implementation. If the option is not set, the cmake will use no heap
+# implementation (e.g. when only static allocation is used).
 
 # `freertos_config` target defines the path to FreeRTOSConfig.h and optionally other freertos based config files
 if(NOT TARGET freertos_config )
@@ -37,9 +39,6 @@ if(NOT TARGET freertos_config )
     endif()
 endif()
 
-# Heap number or absolute path to custom heap implementation provided by user
-set(FREERTOS_HEAP "4" CACHE STRING "FreeRTOS heap model number. 1 .. 5. Or absolute path to custom heap source file")
-
 # FreeRTOS port option
 if(NOT FREERTOS_PORT)
     message(WARNING " FREERTOS_PORT is not set. Please specify it from top-level CMake file (example):\n"
@@ -285,11 +284,16 @@ target_sources(freertos_kernel PRIVATE
     stream_buffer.c
     tasks.c
     timers.c
-
-    # If FREERTOS_HEAP is digit between 1 .. 5 - it is heap number, otherwise - it is path to custom heap source file
-    $<IF:$<BOOL:$<FILTER:${FREERTOS_HEAP},EXCLUDE,^[1-5]$>>,${FREERTOS_HEAP},portable/MemMang/heap_${FREERTOS_HEAP}.c>
 )
 
+if (DEFINED FREERTOS_HEAP )
+    # User specified a heap implementation add heap implementation to freertos_kernel.
+    target_sources(freertos_kernel PRIVATE
+        # If FREERTOS_HEAP is digit between 1 .. 5 - it is heap number, otherwise - it is path to custom heap source file
+        $<IF:$<BOOL:$<FILTER:${FREERTOS_HEAP},EXCLUDE,^[1-5]$>>,${FREERTOS_HEAP},portable/MemMang/heap_${FREERTOS_HEAP}.c>
+    )
+endif()
+
 
 target_link_libraries(freertos_kernel
     PUBLIC

From fc7aca7ff239ac988b7cb28a73ca6c66f4efcb84 Mon Sep 17 00:00:00 2001
From: Darian <32921628+Dazza0@users.noreply.github.com>
Date: Mon, 23 Oct 2023 15:20:24 +0800
Subject: [PATCH 097/424] Rename CPU to Core (#849)

This commit renames "CPU" to "Core" for any public facing API for consistency
with other SMP related APIs (e.g., "configNUMBER_OF_CORES").

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
---
 include/FreeRTOS.h | 8 ++++----
 include/task.h     | 2 +-
 tasks.c            | 6 +++---
 3 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/include/FreeRTOS.h b/include/FreeRTOS.h
index ba7d083a6..b8153ac64 100644
--- a/include/FreeRTOS.h
+++ b/include/FreeRTOS.h
@@ -2120,12 +2120,12 @@
     #define traceRETURN_xTaskGetCurrentTaskHandle( xReturn )
 #endif
 
-#ifndef traceENTER_xTaskGetCurrentTaskHandleCPU
-    #define traceENTER_xTaskGetCurrentTaskHandleCPU( xCoreID )
+#ifndef traceENTER_xTaskGetCurrentTaskHandleForCore
+    #define traceENTER_xTaskGetCurrentTaskHandleForCore( xCoreID )
 #endif
 
-#ifndef traceRETURN_xTaskGetCurrentTaskHandleCPU
-    #define traceRETURN_xTaskGetCurrentTaskHandleCPU( xReturn )
+#ifndef traceRETURN_xTaskGetCurrentTaskHandleForCore
+    #define traceRETURN_xTaskGetCurrentTaskHandleForCore( xReturn )
 #endif
 
 #ifndef traceENTER_xTaskGetSchedulerState
diff --git a/include/task.h b/include/task.h
index b6850e8bd..c369f0c1d 100644
--- a/include/task.h
+++ b/include/task.h
@@ -3539,7 +3539,7 @@ TaskHandle_t xTaskGetCurrentTaskHandle( void ) PRIVILEGED_FUNCTION;
 /*
  * Return the handle of the task running on specified core.
  */
-TaskHandle_t xTaskGetCurrentTaskHandleCPU( BaseType_t xCoreID ) PRIVILEGED_FUNCTION;
+TaskHandle_t xTaskGetCurrentTaskHandleForCore( BaseType_t xCoreID ) PRIVILEGED_FUNCTION;
 
 /*
  * Shortcut used by the queue implementation to prevent unnecessary call to
diff --git a/tasks.c b/tasks.c
index e941907cf..d74a4ccac 100644
--- a/tasks.c
+++ b/tasks.c
@@ -6425,18 +6425,18 @@ static void prvResetNextTaskUnblockTime( void )
             return xReturn;
         }
 
-        TaskHandle_t xTaskGetCurrentTaskHandleCPU( BaseType_t xCoreID )
+        TaskHandle_t xTaskGetCurrentTaskHandleForCore( BaseType_t xCoreID )
         {
             TaskHandle_t xReturn = NULL;
 
-            traceENTER_xTaskGetCurrentTaskHandleCPU( xCoreID );
+            traceENTER_xTaskGetCurrentTaskHandleForCore( xCoreID );
 
             if( taskVALID_CORE_ID( xCoreID ) != pdFALSE )
             {
                 xReturn = pxCurrentTCBs[ xCoreID ];
             }
 
-            traceRETURN_xTaskGetCurrentTaskHandleCPU( xReturn );
+            traceRETURN_xTaskGetCurrentTaskHandleForCore( xReturn );
 
             return xReturn;
         }

From a8650b99a33cd6fbc557748ef719e0229296676d Mon Sep 17 00:00:00 2001
From: Tony Josi <tonyjosi@amazon.com>
Date: Mon, 23 Oct 2023 14:50:41 +0530
Subject: [PATCH 098/424] Update example cmake project path (#851)

* fix build on 64 bit platform

* moving sample cmake project to a separate root level dir

* moving sample cmake project to a separate root level dir

* updating paths for the sample cmake project

* rename example folder

* use configKERNEL_PROVIDED_STATIC_MEMORY

* update comments

* update comments

* rename folder to examples

* fix formatting
---
 README.md                                     |  2 +-
 .../cmake_example}/CMakeLists.txt             |  4 +--
 .../cmake_example}/main.c                     | 24 --------------
 .../sample_configuration}/FreeRTOSConfig.h    | 32 ++++++++++++++-----
 .../sample_configuration}/readme.md           |  0
 portable/template/portmacro.h                 |  3 ++
 6 files changed, 30 insertions(+), 35 deletions(-)
 rename {cmake_example => examples/cmake_example}/CMakeLists.txt (88%)
 rename {cmake_example => examples/cmake_example}/main.c (74%)
 rename {sample_configuration => examples/sample_configuration}/FreeRTOSConfig.h (94%)
 rename {sample_configuration => examples/sample_configuration}/readme.md (100%)

diff --git a/README.md b/README.md
index 2ef719972..c6633563f 100644
--- a/README.md
+++ b/README.md
@@ -125,7 +125,7 @@ See the readme file in the ```./portable``` directory for more information.
 - The ```./include``` directory contains the real time kernel header files.
 
 - The ```./sample_configuration``` directory contains a sample `FreeRTOSConfig.h` to help jumpstart a new project.
-See the [FreeRTOSConfig.h](sample_configuration/FreeRTOSConfig.h) file for instructions.
+See the [FreeRTOSConfig.h](examples/sample_configuration/FreeRTOSConfig.h) file for instructions.
 
 ### Code Formatting
 
diff --git a/cmake_example/CMakeLists.txt b/examples/cmake_example/CMakeLists.txt
similarity index 88%
rename from cmake_example/CMakeLists.txt
rename to examples/cmake_example/CMakeLists.txt
index 723012039..2bb317296 100644
--- a/cmake_example/CMakeLists.txt
+++ b/examples/cmake_example/CMakeLists.txt
@@ -2,7 +2,7 @@ cmake_minimum_required(VERSION 3.15)
 
 project(example)
 
-set(FREERTOS_KERNEL_PATH "../")
+set(FREERTOS_KERNEL_PATH "../../")
 
 # Add the freertos_config for FreeRTOS-Kernel
 add_library(freertos_config INTERFACE)
@@ -13,7 +13,7 @@ target_include_directories(freertos_config
 )
 
 # Select the heap port.  values between 1-4 will pick a heap.
-# set(FREERTOS_HEAP "4" CACHE STRING "" FORCE)
+set(FREERTOS_HEAP "4" CACHE STRING "" FORCE)
 
 # Select the native compile PORT
 set(FREERTOS_PORT "TEMPLATE" CACHE STRING "" FORCE)
diff --git a/cmake_example/main.c b/examples/cmake_example/main.c
similarity index 74%
rename from cmake_example/main.c
rename to examples/cmake_example/main.c
index d00aeae72..bf1717e95 100644
--- a/cmake_example/main.c
+++ b/examples/cmake_example/main.c
@@ -44,12 +44,6 @@
 static StaticTask_t exampleTaskTCB;
 static StackType_t exampleTaskStack[ configMINIMAL_STACK_SIZE ];
 
-static StaticTask_t xTimerTaskTCB;
-static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ];
-
-static StaticTask_t xIdleTaskTCB;
-static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ];
-
 void exampleTask( void * parameters )
 {
     /* Unused parameters. */
@@ -91,21 +85,3 @@ void vApplicationStackOverflowHook( TaskHandle_t xTask,
     ( void ) xTask;
     ( void ) pcTaskName;
 }
-
-void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer,
-                                     StackType_t ** ppxTimerTaskStackBuffer,
-                                     uint32_t * pulTimerTaskStackSize )
-{
-    *ppxTimerTaskTCBBuffer = &xTimerTaskTCB;
-    *ppxTimerTaskStackBuffer = uxTimerTaskStack;
-    *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH;
-}
-
-void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer,
-                                    StackType_t ** ppxIdleTaskStackBuffer,
-                                    uint32_t * pulIdleTaskStackSize )
-{
-    *ppxIdleTaskTCBBuffer = &xIdleTaskTCB;
-    *ppxIdleTaskStackBuffer = uxIdleTaskStack;
-    *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;
-}
diff --git a/sample_configuration/FreeRTOSConfig.h b/examples/sample_configuration/FreeRTOSConfig.h
similarity index 94%
rename from sample_configuration/FreeRTOSConfig.h
rename to examples/sample_configuration/FreeRTOSConfig.h
index 43282118f..32b75bc9d 100644
--- a/sample_configuration/FreeRTOSConfig.h
+++ b/examples/sample_configuration/FreeRTOSConfig.h
@@ -118,13 +118,21 @@
  * human readable name.  Includes the NULL terminator. */
 #define configMAX_TASK_NAME_LEN                    16
 
-/* The tick count is held in a variable of type TickType_t.  Set
- * configUSE_16_BIT_TICKS to 1 to make TickType_t a 16-bit type.  Set
- * configUSE_16_BIT_TICKS to 0 to make TickType_t either a 32 or 64-bit type
- * depending on the architecture.  Using a 16-bit type can greatly improve
- * efficiency on 8-bit and 16-bit microcontrollers, but at the cost of limiting the
- * maximum specifiable block time to 0xffff. */
-#define configUSE_16_BIT_TICKS                     0
+/* Time is measured in 'ticks' - which is the number of times the tick interrupt
+ * has executed since the RTOS kernel was started.
+ * The tick count is held in a variable of type TickType_t.
+ *
+ * configTICK_TYPE_WIDTH_IN_BITS controls the type (and therefore bit-width) of TickType_t:
+ *
+ * Defining configTICK_TYPE_WIDTH_IN_BITS as TICK_TYPE_WIDTH_16_BITS causes
+ * TickType_t to be defined (typedef'ed) as an unsigned 16-bit type.
+ *
+ * Defining configTICK_TYPE_WIDTH_IN_BITS as TICK_TYPE_WIDTH_32_BITS causes
+ * TickType_t to be defined (typedef'ed) as an unsigned 32-bit type.
+ *
+ * Defining configTICK_TYPE_WIDTH_IN_BITS as TICK_TYPE_WIDTH_64_BITS causes
+ * TickType_t to be defined (typedef'ed) as an unsigned 64-bit type. */
+#define configTICK_TYPE_WIDTH_IN_BITS              TICK_TYPE_WIDTH_64_BITS
 
 /* Set configIDLE_SHOULD_YIELD to 1 to have the Idle task yield to an
  * application task if there is an Idle priority (priority 0) application task that
@@ -388,7 +396,15 @@
 
 /* secureconfigMAX_SECURE_CONTEXTS define the maximum number of tasks that can
  *  call into the secure side of an ARMv8-M chip.  Not used by any other ports. */
-#define secureconfigMAX_SECURE_CONTEXTS    5
+#define secureconfigMAX_SECURE_CONTEXTS        5
+
+/* Defines the kernel provided implementation of
+ * vApplicationGetIdleTaskMemory() and vApplicationGetTimerTaskMemory()
+ * to provide the memory that is used by the Idle task and Timer task respectively.
+ * The application can provide it's own implementation of
+ * vApplicationGetIdleTaskMemory() and vApplicationGetTimerTaskMemory() by
+ * setting configKERNEL_PROVIDED_STATIC_MEMORY to 0 or leaving it undefined. */
+#define configKERNEL_PROVIDED_STATIC_MEMORY    1
 
 /******************************************************************************/
 /* Definitions that include or exclude functionality. *************************/
diff --git a/sample_configuration/readme.md b/examples/sample_configuration/readme.md
similarity index 100%
rename from sample_configuration/readme.md
rename to examples/sample_configuration/readme.md
diff --git a/portable/template/portmacro.h b/portable/template/portmacro.h
index 96b400c15..4e4aa934d 100644
--- a/portable/template/portmacro.h
+++ b/portable/template/portmacro.h
@@ -38,6 +38,9 @@ typedef unsigned char    UBaseType_t;
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
     typedef uint32_t     TickType_t;
     #define portMAX_DELAY    ( TickType_t ) 0xffffffffUL
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_64_BITS )
+    typedef uint64_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffffffffffffffffULL
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif

From 4ef0bb676cd4114ab21d21d03f31b4eb17d97a70 Mon Sep 17 00:00:00 2001
From: Darian <32921628+Dazza0@users.noreply.github.com>
Date: Thu, 26 Oct 2023 05:45:03 +0800
Subject: [PATCH 099/424] vTaskListTasks prints core affinity mask (#850)

This commit updates vTaskListTasks so that it prints uxCoreAffinityMask if
core affinity is enabled in configuration.
---
 tasks.c | 25 ++++++++++++++++++-------
 1 file changed, 18 insertions(+), 7 deletions(-)

diff --git a/tasks.c b/tasks.c
index d74a4ccac..2e1cce402 100644
--- a/tasks.c
+++ b/tasks.c
@@ -7225,13 +7225,24 @@ static void prvResetNextTaskUnblockTime( void )
                     if( uxConsumedBufferLength < ( uxBufferLength - 1 ) )
                     {
                         /* Write the rest of the string. */
-                        iSnprintfReturnValue = snprintf( pcWriteBuffer,
-                                                         uxBufferLength - uxConsumedBufferLength,
-                                                         "\t%c\t%u\t%u\t%u\r\n",
-                                                         cStatus,
-                                                         ( unsigned int ) pxTaskStatusArray[ x ].uxCurrentPriority,
-                                                         ( unsigned int ) pxTaskStatusArray[ x ].usStackHighWaterMark,
-                                                         ( unsigned int ) pxTaskStatusArray[ x ].xTaskNumber ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
+                        #if ( ( configUSE_CORE_AFFINITY == 1 ) && ( configNUMBER_OF_CORES > 1 ) )
+                            iSnprintfReturnValue = snprintf( pcWriteBuffer,
+                                                             uxBufferLength - uxConsumedBufferLength,
+                                                             "\t%c\t%u\t%u\t%u\t0x%x\r\n",
+                                                             cStatus,
+                                                             ( unsigned int ) pxTaskStatusArray[ x ].uxCurrentPriority,
+                                                             ( unsigned int ) pxTaskStatusArray[ x ].usStackHighWaterMark,
+                                                             ( unsigned int ) pxTaskStatusArray[ x ].xTaskNumber,
+                                                             ( unsigned int ) pxTaskStatusArray[ x ].uxCoreAffinityMask ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
+                        #else /* ( ( configUSE_CORE_AFFINITY == 1 ) && ( configNUMBER_OF_CORES > 1 ) ) */
+                            iSnprintfReturnValue = snprintf( pcWriteBuffer,
+                                                             uxBufferLength - uxConsumedBufferLength,
+                                                             "\t%c\t%u\t%u\t%u\r\n",
+                                                             cStatus,
+                                                             ( unsigned int ) pxTaskStatusArray[ x ].uxCurrentPriority,
+                                                             ( unsigned int ) pxTaskStatusArray[ x ].usStackHighWaterMark,
+                                                             ( unsigned int ) pxTaskStatusArray[ x ].xTaskNumber ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
+                        #endif /* ( ( configUSE_CORE_AFFINITY == 1 ) && ( configNUMBER_OF_CORES > 1 ) ) */
                         uxCharsWrittenBySnprintf = prvSnprintfReturnValueToCharsWritten( iSnprintfReturnValue, uxBufferLength - uxConsumedBufferLength );
 
                         uxConsumedBufferLength += uxCharsWrittenBySnprintf;

From 5281427a9942bf12d35240d388fcfe60fa7dd682 Mon Sep 17 00:00:00 2001
From: Tony Josi <tonyjosi@amazon.com>
Date: Thu, 26 Oct 2023 11:27:45 +0530
Subject: [PATCH 100/424] Add nightly coverity scan (#859)

* coverity scan job

* coverity scan badge in readme

* Update cron schedule

* revert adding badge

* update description

* updating review feedback
---
 .github/workflows/coverity_scan.yml | 46 +++++++++++++++++++++++++++++
 1 file changed, 46 insertions(+)
 create mode 100644 .github/workflows/coverity_scan.yml

diff --git a/.github/workflows/coverity_scan.yml b/.github/workflows/coverity_scan.yml
new file mode 100644
index 000000000..6f492d7fd
--- /dev/null
+++ b/.github/workflows/coverity_scan.yml
@@ -0,0 +1,46 @@
+name: FreeRTOS-Kernel Coverity Scan
+on:
+  schedule: ## Scheduled to run at 1:15 AM UTC daily.
+    - cron: '15 1 * * *'
+
+
+jobs:
+
+  Coverity-Scan:
+    name: Coverity Scan
+    runs-on: ubuntu-latest
+    steps:
+      - name: Checkout the Repository
+        uses: actions/checkout@v3
+
+      - name: Install Build Essentials
+        shell: bash
+        run: |
+          sudo apt-get -y update
+          sudo apt-get -y install build-essential
+
+      - name: Install Coverity Build
+        shell: bash
+        env:
+          COVERITY_TOKEN: ${{ secrets.COVERITY_SCAN_TOKEN }}
+        run: |
+          wget -nv -qO- https://scan.coverity.com/download/linux64 --post-data "token=${COVERITY_TOKEN}&project=FreeRTOS-Kernel" | tar -zx --one-top-level=cov_scan --strip-components 1
+          echo "cov_scan_path=$(pwd)/cov_scan/bin" >> $GITHUB_ENV
+
+      - name: Coverity Build & Upload for Scan
+        shell: bash
+        env:
+          COVERITY_TOKEN: ${{ secrets.COVERITY_SCAN_TOKEN }}
+        run: |
+          export PATH="$PATH:${{env.cov_scan_path}}"
+          cmake -S ./examples/cmake_example/ -B build
+          cd build
+          cov-build --dir cov-int make -j
+          tar czvf gcc_freertos_kerenl_sample_build.tgz cov-int
+          COV_SCAN_UPLOAD_STATUS=$(curl --form token=${COVERITY_TOKEN} \
+            --form email=tonyjosi@amazon.com \
+            --form file=@gcc_freertos_kerenl_sample_build.tgz \
+            --form version="Mainline" \
+            --form description="FreeRTOS Kernel Nightly Scan" \
+            https://scan.coverity.com/builds?project=FreeRTOS-Kernel)
+          echo "${COV_SCAN_UPLOAD_STATUS}" | grep -q -e 'Build successfully submitted' || echo >&2 "Error submitting build for analysis: ${COV_SCAN_UPLOAD_STATUS}"

From 37678b06568fda7aaff090b77e8e34d6ab29ede4 Mon Sep 17 00:00:00 2001
From: Joe Benczarski <joebenczarski@gmail.com>
Date: Fri, 27 Oct 2023 14:57:52 -0400
Subject: [PATCH 101/424] Support configurable RISC-V chip extension (#773)

* Support configurable RISC-V chip extension

Added the FREERTOS_RISCV_EXTENSION option to allow the user
to select which chip extension they want included. Removed the
port for pulpino to instead use the new option.

* Add port GCC_RISC_V_GENERIC and IAR_RISC_V_GENERIC

* Add two rics-v generic ports to support FREERTOS_RISCV_EXTENSION
  config

---------

Co-authored-by: Joe Benczarski <jbenczarski@trijicon.com>
Co-authored-by: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Co-authored-by: Ching-Hsin Lee <chinglee@amazon.com>
Co-authored-by: kar-rahul-aws <118818625+kar-rahul-aws@users.noreply.github.com>
Co-authored-by: Soren Ptak <ptaksoren@gmail.com>
---
 CMakeLists.txt                            |  2 ++
 portable/CMakeLists.txt                   | 24 +++++++++++++++++++++++
 portable/GCC/RISC-V/chip_extensions.cmake | 19 ++++++++++++++++++
 portable/IAR/RISC-V/chip_extensions.cmake | 16 +++++++++++++++
 4 files changed, 61 insertions(+)
 create mode 100644 portable/GCC/RISC-V/chip_extensions.cmake
 create mode 100644 portable/IAR/RISC-V/chip_extensions.cmake

diff --git a/CMakeLists.txt b/CMakeLists.txt
index 984e36ecd..d9ddb7ed7 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -106,6 +106,7 @@ if(NOT FREERTOS_PORT)
         " GCC_PPC440_XILINX                - Compiler: GCC           Target: Xilinx PPC440\n"
         " GCC_RISC_V                       - Compiler: GCC           Target: RISC-V\n"
         " GCC_RISC_V_PULPINO_VEGA_RV32M1RM - Compiler: GCC           Target: RISC-V Pulpino Vega RV32M1RM\n"
+        " GCC_RISC_V_GENERIC               - Compiler: GCC           Target: RISC-V with FREERTOS_RISCV_EXTENSION\n"
         " GCC_RL78                         - Compiler: GCC           Target: Renesas RL78\n"
         " GCC_RX100                        - Compiler: GCC           Target: Renesas RX100\n"
         " GCC_RX200                        - Compiler: GCC           Target: Renesas RX200\n"
@@ -156,6 +157,7 @@ if(NOT FREERTOS_PORT)
         " IAR_MSP430                       - Compiler: IAR           Target: MSP430\n"
         " IAR_MSP430X                      - Compiler: IAR           Target: MSP430X\n"
         " IAR_RISC_V                       - Compiler: IAR           Target: RISC-V\n"
+        " IAR_RISC_V_GENERIC               - Compiler: IAR           Target: RISC-V with FREERTOS_RISCV_EXTENSION\n"
         " IAR_RL78                         - Compiler: IAR           Target: Renesas RL78\n"
         " IAR_RX100                        - Compiler: IAR           Target: Renesas RX100\n"
         " IAR_RX600                        - Compiler: IAR           Target: Renesas RX600\n"
diff --git a/portable/CMakeLists.txt b/portable/CMakeLists.txt
index 327e9236b..4d81ef6c0 100644
--- a/portable/CMakeLists.txt
+++ b/portable/CMakeLists.txt
@@ -1,3 +1,11 @@
+if( FREERTOS_PORT STREQUAL "GCC_RISC_V_GENERIC" )
+    include( GCC/RISC-V/chip_extensions.cmake )
+endif()
+
+if( FREERTOS_PORT STREQUAL "IAR_RISC_V_GENERIC" )
+    include( IAR/RISC-V/chip_extensions.cmake )
+endif()
+
 # FreeRTOS internal cmake file. Do not use it in user top-level project
 
 if (FREERTOS_PORT STREQUAL "A_CUSTOM_PORT")
@@ -292,6 +300,10 @@ add_library(freertos_kernel_port STATIC
         GCC/RISC-V/port.c
         GCC/RISC-V/portASM.S>
 
+    $<$<STREQUAL:${FREERTOS_PORT},GCC_RISC_V_GENERIC>:
+        GCC/RISC-V/port.c
+        GCC/RISC-V/portASM.S>
+
     # Renesas RL78 port for GCC
     $<$<STREQUAL:${FREERTOS_PORT},GCC_RL78>:
         GCC/RL78/port.c
@@ -497,6 +509,10 @@ add_library(freertos_kernel_port STATIC
         IAR/RISC-V/port.c
         IAR/RISC-V/portASM.s>
 
+    $<$<STREQUAL:${FREERTOS_PORT},IAR_RISC_V_GENERIC>:
+        IAR/RISC-V/port.c
+        IAR/RISC-V/portASM.s>
+
     # Renesas RL78 port for IAR EWRL78
     $<$<STREQUAL:${FREERTOS_PORT},IAR_RL78>:
         IAR/RL78/port.c
@@ -845,6 +861,10 @@ target_include_directories(freertos_kernel_port PUBLIC
         ${CMAKE_CURRENT_LIST_DIR}/GCC/RISC-V
         ${CMAKE_CURRENT_LIST_DIR}/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM>
 
+    $<$<STREQUAL:${FREERTOS_PORT},GCC_RISC_V_GENERIC>:
+        ${CMAKE_CURRENT_LIST_DIR}/GCC/RISC-V
+        ${CMAKE_CURRENT_LIST_DIR}/GCC/RISC-V/chip_specific_extensions/${FREERTOS_RISCV_EXTENSION}>
+
     # Renesas RL78 port for GCC
     $<$<STREQUAL:${FREERTOS_PORT},GCC_RL78>:${CMAKE_CURRENT_LIST_DIR}/GCC/RL78>
 
@@ -942,6 +962,10 @@ target_include_directories(freertos_kernel_port PUBLIC
         ${CMAKE_CURRENT_LIST_DIR}/IAR/RISC-V
         ${CMAKE_CURRENT_LIST_DIR}/IAR/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions>
 
+    $<$<STREQUAL:${FREERTOS_PORT},IAR_RISC_V_GENERIC>:
+        ${CMAKE_CURRENT_LIST_DIR}/IAR/RISC-V
+        ${CMAKE_CURRENT_LIST_DIR}/IAR/RISC-V/chip_specific_extensions/${FREERTOS_RISCV_EXTENSION}>
+
     # Renesas RL78 port for IAR EWRL78
     $<$<STREQUAL:${FREERTOS_PORT},IAR_RL78>:${CMAKE_CURRENT_LIST_DIR}/IAR/RL78>
 
diff --git a/portable/GCC/RISC-V/chip_extensions.cmake b/portable/GCC/RISC-V/chip_extensions.cmake
new file mode 100644
index 000000000..c0d2c0d86
--- /dev/null
+++ b/portable/GCC/RISC-V/chip_extensions.cmake
@@ -0,0 +1,19 @@
+if( FREERTOS_PORT STREQUAL "GCC_RISC_V_GENERIC" )
+    set( VALID_CHIP_EXTENSIONS
+            "Pulpino_Vega_RV32M1RM"
+            "RISCV_MTIME_CLINT_no_extensions"
+            "RISCV_no_extensions"
+            "RV32I_CLINT_no_extensions" )
+
+    if( ( NOT FREERTOS_RISCV_EXTENSION ) OR ( NOT ( ${FREERTOS_RISCV_EXTENSION} IN_LIST VALID_CHIP_EXTENSIONS ) ) )
+        message(FATAL_ERROR
+                "FREERTOS_RISCV_EXTENSION \"${FREERTOS_RISCV_EXTENSION}\" is not set or unsupported.\n"
+                "Please specify it from top-level CMake file (example):\n"
+                "   set(FREERTOS_RISCV_EXTENSION RISCV_MTIME_CLINT_no_extensions CACHE STRING \"\")\n"
+                " or from CMake command line option:\n"
+                "   -DFREERTOS_RISCV_EXTENSION=RISCV_MTIME_CLINT_no_extensions\n"
+                "\n"
+                " Available extension options:\n"
+                "   ${VALID_CHIP_EXTENSIONS} \n")
+    endif()
+endif()
diff --git a/portable/IAR/RISC-V/chip_extensions.cmake b/portable/IAR/RISC-V/chip_extensions.cmake
new file mode 100644
index 000000000..110ec4a2e
--- /dev/null
+++ b/portable/IAR/RISC-V/chip_extensions.cmake
@@ -0,0 +1,16 @@
+if( FREERTOS_PORT STREQUAL "IAR_RISC_V_GENERIC" )
+    set( VALID_CHIP_EXTENSIONS
+            "RV32I_CLINT_no_extensions" )
+
+    if( ( NOT FREERTOS_RISCV_EXTENSION ) OR ( NOT ( ${FREERTOS_RISCV_EXTENSION} IN_LIST VALID_CHIP_EXTENSIONS ) ) )
+        message(FATAL_ERROR
+                "FREERTOS_RISCV_EXTENSION \"${FREERTOS_RISCV_EXTENSION}\" is not set or unsupported.\n"
+                "Please specify it from top-level CMake file (example):\n"
+                "   set(FREERTOS_RISCV_EXTENSION RISCV_MTIME_CLINT_no_extensions CACHE STRING \"\")\n"
+                " or from CMake command line option:\n"
+                "   -DFREERTOS_RISCV_EXTENSION=RISCV_MTIME_CLINT_no_extensions\n"
+                "\n"
+                " Available extension options:\n"
+                "   ${VALID_CHIP_EXTENSIONS} \n")
+    endif()
+endif()

From 1c465a0890bb5051a0c262ea1ed7cf6e40246499 Mon Sep 17 00:00:00 2001
From: Tony Josi <tonyjosi@amazon.com>
Date: Mon, 30 Oct 2023 18:19:29 +0530
Subject: [PATCH 102/424] update coverity scan email (#871)

---
 .github/workflows/coverity_scan.yml | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/.github/workflows/coverity_scan.yml b/.github/workflows/coverity_scan.yml
index 6f492d7fd..050ea325b 100644
--- a/.github/workflows/coverity_scan.yml
+++ b/.github/workflows/coverity_scan.yml
@@ -31,6 +31,7 @@ jobs:
         shell: bash
         env:
           COVERITY_TOKEN: ${{ secrets.COVERITY_SCAN_TOKEN }}
+          COVERITY_EMAIL: ${{ secrets.COVERITY_SCAN_EMAIL }}
         run: |
           export PATH="$PATH:${{env.cov_scan_path}}"
           cmake -S ./examples/cmake_example/ -B build
@@ -38,7 +39,7 @@ jobs:
           cov-build --dir cov-int make -j
           tar czvf gcc_freertos_kerenl_sample_build.tgz cov-int
           COV_SCAN_UPLOAD_STATUS=$(curl --form token=${COVERITY_TOKEN} \
-            --form email=tonyjosi@amazon.com \
+            --form email=${COVERITY_EMAIL} \
             --form file=@gcc_freertos_kerenl_sample_build.tgz \
             --form version="Mainline" \
             --form description="FreeRTOS Kernel Nightly Scan" \

From ef0104e7685c45eeebf6ebe06a24f4eb1a28c045 Mon Sep 17 00:00:00 2001
From: ActoryOu <jay2002824@gmail.com>
Date: Mon, 30 Oct 2023 23:35:42 +0800
Subject: [PATCH 103/424] Move cmake compile options to the example project
 (#872)

* Move GCC compile option to GCC folder with toolchain option

* Add CI flow to build cmake example

* Fix CI

* formatting && enable Werror

* Add useless variable to test CI

* revert useless variable

* Add comments as examples.

* Remove default compile options.

* Formatting

* Remove compile option in kernel cmake and put the sample in examples/cmake_example

---------

Co-authored-by: Joseph Julicher <jjulicher@mac.com>
---
 .github/workflows/kernel-demos.yml    | 21 ++++++++++++++
 CMakeLists.txt                        | 42 ---------------------------
 examples/cmake_example/CMakeLists.txt | 39 +++++++++++++++++++++++++
 3 files changed, 60 insertions(+), 42 deletions(-)

diff --git a/.github/workflows/kernel-demos.yml b/.github/workflows/kernel-demos.yml
index 62970a171..7d83d7482 100644
--- a/.github/workflows/kernel-demos.yml
+++ b/.github/workflows/kernel-demos.yml
@@ -90,6 +90,27 @@ jobs:
         working-directory: FreeRTOS/Demo/Posix_GCC
         run: make -j COVERAGE_TEST=1
 
+  CMake-Example:
+    name: CMake Example with Native GCC
+    runs-on: ubuntu-latest
+    steps:
+      # Checkout user pull request changes
+      - name: Checkout Repository
+        uses: actions/checkout@v3
+
+      - name: Install GCC
+        shell: bash
+        run: |
+          sudo apt-get -y update
+          sudo apt-get -y install build-essential
+
+      - name: Build CMake Example Demo
+        shell: bash
+        working-directory: examples/cmake_example
+        run: |
+          cmake -S . -B build
+          cmake --build build
+
   MSP430-GCC:
     name: GNU MSP430 Toolchain
     runs-on: ubuntu-latest
diff --git a/CMakeLists.txt b/CMakeLists.txt
index d9ddb7ed7..30172870a 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -230,50 +230,8 @@ elseif((FREERTOS_PORT STREQUAL "A_CUSTOM_PORT") AND (NOT TARGET freertos_kernel_
     "       freertos_kernel_include)")
 endif()
 
-
 add_library(freertos_kernel STATIC)
 
-########################################################################
-# Overall Compile Options
-# Note the compile option strategy is to error on everything and then
-# Per library opt-out of things that are warnings/errors.
-# This ensures that no matter what strategy for compilation you take, the
-# builds will still occur.
-#
-# Only tested with GNU and Clang.
-# Other options are https://cmake.org/cmake/help/latest/variable/CMAKE_LANG_COMPILER_ID.html#variable:CMAKE_%3CLANG%3E_COMPILER_ID
-# Naming of compilers translation map:
-#
-#   FreeRTOS    | CMake
-#   -------------------
-#   CCS         | ?TBD?
-#   GCC         | GNU, Clang, *Clang Others?
-#   IAR         | IAR
-#   Keil        | ARMCC
-#   MSVC        | MSVC # Note only for MinGW?
-#   Renesas     | ?TBD?
-
-target_compile_options(freertos_kernel PRIVATE
-    ### Gnu/Clang C Options
-    $<$<COMPILE_LANG_AND_ID:C,GNU>:-fdiagnostics-color=always>
-    $<$<COMPILE_LANG_AND_ID:C,Clang>:-fcolor-diagnostics>
-
-    $<$<COMPILE_LANG_AND_ID:C,Clang,GNU>:-Wall>
-    $<$<COMPILE_LANG_AND_ID:C,Clang,GNU>:-Wextra>
-    $<$<COMPILE_LANG_AND_ID:C,Clang,GNU>:-Wpedantic>
-    $<$<COMPILE_LANG_AND_ID:C,Clang,GNU>:-Werror>
-    $<$<COMPILE_LANG_AND_ID:C,Clang,GNU>:-Wconversion>
-    $<$<COMPILE_LANG_AND_ID:C,Clang>:-Weverything>
-
-    # Suppressions required to build clean with clang.
-    $<$<COMPILE_LANG_AND_ID:C,Clang>:-Wno-unused-macros>
-    $<$<COMPILE_LANG_AND_ID:C,Clang>:-Wno-padded>
-    $<$<COMPILE_LANG_AND_ID:C,Clang>:-Wno-missing-variable-declarations>
-    $<$<COMPILE_LANG_AND_ID:C,Clang>:-Wno-covered-switch-default>
-    $<$<COMPILE_LANG_AND_ID:C,Clang>:-Wno-cast-align>
-)
-
-
 ########################################################################
 add_subdirectory(include)
 add_subdirectory(portable)
diff --git a/examples/cmake_example/CMakeLists.txt b/examples/cmake_example/CMakeLists.txt
index 2bb317296..85329678d 100644
--- a/examples/cmake_example/CMakeLists.txt
+++ b/examples/cmake_example/CMakeLists.txt
@@ -21,6 +21,45 @@ set(FREERTOS_PORT "TEMPLATE" CACHE STRING "" FORCE)
 # Adding the FreeRTOS-Kernel subdirectory
 add_subdirectory(${FREERTOS_KERNEL_PATH} FreeRTOS-Kernel)
 
+########################################################################
+# Overall Compile Options
+# Note the compile option strategy is to error on everything and then
+# Per library opt-out of things that are warnings/errors.
+# This ensures that no matter what strategy for compilation you take, the
+# builds will still occur.
+#
+# Only tested with GNU and Clang.
+# Other options are https://cmake.org/cmake/help/latest/variable/CMAKE_LANG_COMPILER_ID.html#variable:CMAKE_%3CLANG%3E_COMPILER_ID
+# Naming of compilers translation map:
+#
+#   FreeRTOS    | CMake
+#   -------------------
+#   CCS         | ?TBD?
+#   GCC         | GNU, Clang, *Clang Others?
+#   IAR         | IAR
+#   Keil        | ARMCC
+#   MSVC        | MSVC # Note only for MinGW?
+#   Renesas     | ?TBD?
+
+target_compile_options(freertos_kernel PRIVATE
+    ### Gnu/Clang C Options
+    $<$<COMPILE_LANG_AND_ID:C,GNU>:-fdiagnostics-color=always>
+    $<$<COMPILE_LANG_AND_ID:C,Clang>:-fcolor-diagnostics>
+
+    $<$<COMPILE_LANG_AND_ID:C,Clang,GNU>:-Wall>
+    $<$<COMPILE_LANG_AND_ID:C,Clang,GNU>:-Wextra>
+    $<$<COMPILE_LANG_AND_ID:C,Clang,GNU>:-Wpedantic>
+    $<$<COMPILE_LANG_AND_ID:C,Clang,GNU>:-Werror>
+    $<$<COMPILE_LANG_AND_ID:C,Clang,GNU>:-Wconversion>
+    $<$<COMPILE_LANG_AND_ID:C,Clang>:-Weverything>
+
+    # Suppressions required to build clean with clang.
+    $<$<COMPILE_LANG_AND_ID:C,Clang>:-Wno-unused-macros>
+    $<$<COMPILE_LANG_AND_ID:C,Clang>:-Wno-padded>
+    $<$<COMPILE_LANG_AND_ID:C,Clang>:-Wno-missing-variable-declarations>
+    $<$<COMPILE_LANG_AND_ID:C,Clang>:-Wno-covered-switch-default>
+    $<$<COMPILE_LANG_AND_ID:C,Clang>:-Wno-cast-align> )
+
 add_executable(${PROJECT_NAME}
     main.c
 )

From 83083a8a1371359e66af4a5aecb5e3110100f5c9 Mon Sep 17 00:00:00 2001
From: Devaraj Ranganna <devaraj.ranganna@arm.com>
Date: Tue, 31 Oct 2023 04:36:39 +0000
Subject: [PATCH 104/424] aarch64: Rename ARM_CA53_64_BIT/_SRE to
 Arm_AARCH64/_SRE (#822)

The Cortex-A53 ports are generic and can be used as a starting point
for other Armv8-A application processors. Therefore, rename
`ARM_CA53_64_BIT` to `Arm_AARCH64` and `ARM_CA53_64_BIT_SRE` to
`Arm_AARCH64_SRE`.

With this renaming, existing projects that use old port, should
migrate to renamed port as follows:

* `ARM_CA53_64_BIT` -> `Arm_AARCH64`
* `ARM_CA53_64_BIT_SRE` -> `Arm_AARCH64_SRE`

Signed-off-by: Devaraj Ranganna <devaraj.ranganna@arm.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
---
 CMakeLists.txt                                |  4 ++--
 portable/CMakeLists.txt                       | 16 ++++++-------
 portable/GCC/ARM_CA53_64_BIT/README.md        | 16 +++++++++++++
 portable/GCC/ARM_CA53_64_BIT_SRE/README.md    | 16 +++++++++++++
 portable/GCC/Arm_AARCH64/README.md            | 23 +++++++++++++++++++
 .../{ARM_CA53_64_BIT => Arm_AARCH64}/port.c   |  0
 .../portASM.S                                 |  0
 .../portmacro.h                               |  0
 portable/GCC/Arm_AARCH64_SRE/README.md        | 23 +++++++++++++++++++
 .../port.c                                    |  0
 .../portASM.S                                 |  0
 .../portmacro.h                               |  0
 12 files changed, 88 insertions(+), 10 deletions(-)
 create mode 100644 portable/GCC/ARM_CA53_64_BIT/README.md
 create mode 100644 portable/GCC/ARM_CA53_64_BIT_SRE/README.md
 create mode 100644 portable/GCC/Arm_AARCH64/README.md
 rename portable/GCC/{ARM_CA53_64_BIT => Arm_AARCH64}/port.c (100%)
 rename portable/GCC/{ARM_CA53_64_BIT => Arm_AARCH64}/portASM.S (100%)
 rename portable/GCC/{ARM_CA53_64_BIT => Arm_AARCH64}/portmacro.h (100%)
 create mode 100644 portable/GCC/Arm_AARCH64_SRE/README.md
 rename portable/GCC/{ARM_CA53_64_BIT_SRE => Arm_AARCH64_SRE}/port.c (100%)
 rename portable/GCC/{ARM_CA53_64_BIT_SRE => Arm_AARCH64_SRE}/portASM.S (100%)
 rename portable/GCC/{ARM_CA53_64_BIT_SRE => Arm_AARCH64_SRE}/portmacro.h (100%)

diff --git a/CMakeLists.txt b/CMakeLists.txt
index 30172870a..5323ec19b 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -58,8 +58,8 @@ if(NOT FREERTOS_PORT)
         " CODEWARRIOR_COLDFIRE_V2          - Compiler: CoreWarrior   Target: ColdFire V2\n"
         " CODEWARRIOR_HCS12                - Compiler: CoreWarrior   Target: HCS12\n"
         " GCC_ARM_CA9                      - Compiler: GCC           Target: ARM Cortex-A9\n"
-        " GCC_ARM_CA53_64_BIT              - Compiler: GCC           Target: ARM Cortex-A53 64 bit\n"
-        " GCC_ARM_CA53_64_BIT_SRE          - Compiler: GCC           Target: ARM Cortex-A53 64 bit SRE\n"
+        " GCC_ARM_AARCH64                  - Compiler: GCC           Target: ARM v8-A\n"
+        " GCC_ARM_AARCH64_SRE              - Compiler: GCC           Target: ARM v8-A SRE\n"
         " GCC_ARM_CM0                      - Compiler: GCC           Target: ARM Cortex-M0\n"
         " GCC_ARM_CM3                      - Compiler: GCC           Target: ARM Cortex-M3\n"
         " GCC_ARM_CM3_MPU                  - Compiler: GCC           Target: ARM Cortex-M3 with MPU\n"
diff --git a/portable/CMakeLists.txt b/portable/CMakeLists.txt
index 4d81ef6c0..b84b3018b 100644
--- a/portable/CMakeLists.txt
+++ b/portable/CMakeLists.txt
@@ -67,13 +67,13 @@ add_library(freertos_kernel_port STATIC
         GCC/ARM_CA9/portASM.S>
 
     # ARMv8-A ports for GCC
-    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CA53_64_BIT>:
-        GCC/ARM_CA53_64_BIT/port.c
-        GCC/ARM_CA53_64_BIT/portASM.S>
+    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_AARCH64>:
+        GCC/Arm_AARCH64/port.c
+        GCC/Arm_AARCH64/portASM.S>
 
-    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CA53_64_BIT_SRE>:
-        GCC/ARM_CA53_64_BIT_SRE/port.c
-        GCC/ARM_CA53_64_BIT_SRE/portASM.S>
+    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_AARCH64_SRE>:
+        GCC/Arm_AARCH64_SRE/port.c
+        GCC/Arm_AARCH64_SRE/portASM.S>
 
     # ARMv6-M port for GCC
     $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM0>:
@@ -761,8 +761,8 @@ target_include_directories(freertos_kernel_port PUBLIC
     $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CA9>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CA9>
 
     # ARMv8-A ports for GCC
-    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CA53_64_BIT>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CA53_64_BIT>
-    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CA53_64_BIT_SRE>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CA53_64_BIT_SRE>
+    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_AARCH64>:${CMAKE_CURRENT_LIST_DIR}/GCC/Arm_AARCH64>
+    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_AARCH64_SRE>:${CMAKE_CURRENT_LIST_DIR}/GCC/Arm_AARCH64_SRE>
 
     # ARMv6-M port for GCC
     $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM0>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM0>
diff --git a/portable/GCC/ARM_CA53_64_BIT/README.md b/portable/GCC/ARM_CA53_64_BIT/README.md
new file mode 100644
index 000000000..b3d56c040
--- /dev/null
+++ b/portable/GCC/ARM_CA53_64_BIT/README.md
@@ -0,0 +1,16 @@
+# ARM_CA53_64_BIT port
+
+Initial port to support Armv8-A architecture in FreeRTOS kernel was written for
+Arm Cortex-A53 processor.
+
+* ARM_CA53_64_BIT
+    * Memory mapped interace to access Arm GIC registers
+
+This port is generic and can be used as a starting point for other Armv8-A
+application processors. Therefore, the port `ARM_CA53_64_BIT` is renamed as
+`Arm_AARCH64`. The existing projects that use old port `ARM_CA53_64_BIT`,
+should migrate to renamed port `Arm_AARCH64`.
+
+**NOTE**
+
+This port uses memory mapped interace to access Arm GIC registers.
diff --git a/portable/GCC/ARM_CA53_64_BIT_SRE/README.md b/portable/GCC/ARM_CA53_64_BIT_SRE/README.md
new file mode 100644
index 000000000..fb5d7936a
--- /dev/null
+++ b/portable/GCC/ARM_CA53_64_BIT_SRE/README.md
@@ -0,0 +1,16 @@
+# ARM_CA53_64_BIT_SRE port
+
+Initial port to support Armv8-A architecture in FreeRTOS kernel was written for
+Arm Cortex-A53 processor.
+
+* ARM_CA53_64_BIT_SRE
+    * System Register interace to access Arm GIC registers
+
+This port is generic and can be used as a starting point for other Armv8-A
+application processors. Therefore, the port `Arm_AARCH64_SRE` is renamed as
+`Arm_AARCH64_SRE`. The existing projects that use old port `Arm_AARCH64_SRE`,
+should migrate to renamed port `Arm_AARCH64_SRE`.
+
+**NOTE**
+
+This port uses System Register interace to access Arm GIC registers.
diff --git a/portable/GCC/Arm_AARCH64/README.md b/portable/GCC/Arm_AARCH64/README.md
new file mode 100644
index 000000000..70552c202
--- /dev/null
+++ b/portable/GCC/Arm_AARCH64/README.md
@@ -0,0 +1,23 @@
+# Armv8-A architecture support
+
+The Armv8-A architecture introduces the ability to use 64-bit and 32-bit
+Execution states, known as AArch64 and AArch32 respectively. The AArch64
+Execution state supports the A64 instruction set. It holds addresses in 64-bit
+registers and allows instructions in the base instruction set to use 64-bit
+registers for their processing.
+
+The AArch32 Execution state is a 32-bit Execution state that preserves
+backwards compatibility with the Armv7-A architecture, enhancing that profile
+so that it can support some features included in the AArch64 state. It supports
+the T32 and A32 instruction sets. Follow the
+[link](https://developer.arm.com/Architectures/A-Profile%20Architecture)
+for more information.
+
+## Arm_AARCH64 port
+
+This port adds support for Armv8-A architecture AArch64 execution state.
+This port is generic and can be used as a starting point for Armv8-A
+application processors.
+
+* Arm_AARCH64
+    * Memory mapped interace to access Arm GIC registers
diff --git a/portable/GCC/ARM_CA53_64_BIT/port.c b/portable/GCC/Arm_AARCH64/port.c
similarity index 100%
rename from portable/GCC/ARM_CA53_64_BIT/port.c
rename to portable/GCC/Arm_AARCH64/port.c
diff --git a/portable/GCC/ARM_CA53_64_BIT/portASM.S b/portable/GCC/Arm_AARCH64/portASM.S
similarity index 100%
rename from portable/GCC/ARM_CA53_64_BIT/portASM.S
rename to portable/GCC/Arm_AARCH64/portASM.S
diff --git a/portable/GCC/ARM_CA53_64_BIT/portmacro.h b/portable/GCC/Arm_AARCH64/portmacro.h
similarity index 100%
rename from portable/GCC/ARM_CA53_64_BIT/portmacro.h
rename to portable/GCC/Arm_AARCH64/portmacro.h
diff --git a/portable/GCC/Arm_AARCH64_SRE/README.md b/portable/GCC/Arm_AARCH64_SRE/README.md
new file mode 100644
index 000000000..0b2e0e485
--- /dev/null
+++ b/portable/GCC/Arm_AARCH64_SRE/README.md
@@ -0,0 +1,23 @@
+# Armv8-A architecture support
+
+The Armv8-A architecture introduces the ability to use 64-bit and 32-bit
+Execution states, known as AArch64 and AArch32 respectively. The AArch64
+Execution state supports the A64 instruction set. It holds addresses in 64-bit
+registers and allows instructions in the base instruction set to use 64-bit
+registers for their processing.
+
+The AArch32 Execution state is a 32-bit Execution state that preserves
+backwards compatibility with the Armv7-A architecture, enhancing that profile
+so that it can support some features included in the AArch64 state. It supports
+the T32 and A32 instruction sets. Follow the
+[link](https://developer.arm.com/Architectures/A-Profile%20Architecture)
+for more information.
+
+## Arm_AARCH64_SRE port
+
+This port adds support for Armv8-A architecture AArch64 execution state.
+This port is generic and can be used as a starting point for Armv8-A
+application processors.
+
+* Arm_AARCH64_SRE
+    * System Register interace to access Arm GIC registers
diff --git a/portable/GCC/ARM_CA53_64_BIT_SRE/port.c b/portable/GCC/Arm_AARCH64_SRE/port.c
similarity index 100%
rename from portable/GCC/ARM_CA53_64_BIT_SRE/port.c
rename to portable/GCC/Arm_AARCH64_SRE/port.c
diff --git a/portable/GCC/ARM_CA53_64_BIT_SRE/portASM.S b/portable/GCC/Arm_AARCH64_SRE/portASM.S
similarity index 100%
rename from portable/GCC/ARM_CA53_64_BIT_SRE/portASM.S
rename to portable/GCC/Arm_AARCH64_SRE/portASM.S
diff --git a/portable/GCC/ARM_CA53_64_BIT_SRE/portmacro.h b/portable/GCC/Arm_AARCH64_SRE/portmacro.h
similarity index 100%
rename from portable/GCC/ARM_CA53_64_BIT_SRE/portmacro.h
rename to portable/GCC/Arm_AARCH64_SRE/portmacro.h

From 8ede50cafd8279f0aff1da59d6d1b89a1fa5c2c3 Mon Sep 17 00:00:00 2001
From: Moral-Hao <sihunzhilei@126.com>
Date: Mon, 6 Nov 2023 17:50:32 +0800
Subject: [PATCH 105/424] Fix vTaskSwitchContext for smp. (#879)

The function vTaskSwitchContext in smp has an parameter of core id,
which means this function is not only used for the core who call it.
Thus we should use the task running on the specific core id,
instead of use the task running on the core who call this function.

Co-authored-by: moral-hao <405197809@qq.com>
---
 tasks.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/tasks.c b/tasks.c
index 2e1cce402..75dded41f 100644
--- a/tasks.c
+++ b/tasks.c
@@ -5142,7 +5142,7 @@ BaseType_t xTaskIncrementTick( void )
                      * are provided by the application, not the kernel. */
                     if( ulTotalRunTime[ xCoreID ] > ulTaskSwitchedInTime[ xCoreID ] )
                     {
-                        pxCurrentTCB->ulRunTimeCounter += ( ulTotalRunTime[ xCoreID ] - ulTaskSwitchedInTime[ xCoreID ] );
+                        pxCurrentTCBs[ xCoreID ]->ulRunTimeCounter += ( ulTotalRunTime[ xCoreID ] - ulTaskSwitchedInTime[ xCoreID ] );
                     }
                     else
                     {
@@ -5159,7 +5159,7 @@ BaseType_t xTaskIncrementTick( void )
                 /* Before the currently running task is switched out, save its errno. */
                 #if ( configUSE_POSIX_ERRNO == 1 )
                 {
-                    pxCurrentTCB->iTaskErrno = FreeRTOS_errno;
+                    pxCurrentTCBs[ xCoreID ]->iTaskErrno = FreeRTOS_errno;
                 }
                 #endif
 
@@ -5170,7 +5170,7 @@ BaseType_t xTaskIncrementTick( void )
                 /* After the new task is switched in, update the global errno. */
                 #if ( configUSE_POSIX_ERRNO == 1 )
                 {
-                    FreeRTOS_errno = pxCurrentTCB->iTaskErrno;
+                    FreeRTOS_errno = pxCurrentTCBs[ xCoreID ]->iTaskErrno;
                 }
                 #endif
 
@@ -5178,7 +5178,7 @@ BaseType_t xTaskIncrementTick( void )
                 {
                     /* Switch C-Runtime's TLS Block to point to the TLS
                      * Block specific to this task. */
-                    configSET_TLS_BLOCK( pxCurrentTCB->xTLSBlock );
+                    configSET_TLS_BLOCK( pxCurrentTCBs[ xCoreID ]->xTLSBlock );
                 }
                 #endif
             }

From 0640b2e4863bfdf628406cc90e29200a9220e088 Mon Sep 17 00:00:00 2001
From: Moral-Hao <sihunzhilei@126.com>
Date: Tue, 7 Nov 2023 15:33:07 +0800
Subject: [PATCH 106/424] Distinguish waiting for notify status from suspend
 status (#865)

* Fix prvTaskIsTaskSuspended.

Just like eTaskGetState, distinguish waiting for notify from suspend.

* Fix vTaskGetInfo.

Just like eTaskGetState, distinguish block state (waiting on notification)
from suspend state.

* Add missing definition of variable x.

* Fix formatting syntax.

---------

Co-authored-by: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Co-authored-by: Tony Josi <tonyjosi@amazon.com>
---
 tasks.c | 46 ++++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 44 insertions(+), 2 deletions(-)

diff --git a/tasks.c b/tasks.c
index 75dded41f..5500bf435 100644
--- a/tasks.c
+++ b/tasks.c
@@ -3284,10 +3284,34 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
             if( listIS_CONTAINED_WITHIN( &xPendingReadyList, &( pxTCB->xEventListItem ) ) == pdFALSE )
             {
                 /* Is it in the suspended list because it is in the Suspended
-                 * state, or because is is blocked with no timeout? */
+                 * state, or because it is blocked with no timeout? */
                 if( listIS_CONTAINED_WITHIN( NULL, &( pxTCB->xEventListItem ) ) != pdFALSE ) /*lint !e961.  The cast is only redundant when NULL is used. */
                 {
-                    xReturn = pdTRUE;
+                    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
+                    {
+                        BaseType_t x;
+
+                        /* The task does not appear on the event list item of
+                         * and of the RTOS objects, but could still be in the
+                         * blocked state if it is waiting on its notification
+                         * rather than waiting on an object.  If not, is
+                         * suspended. */
+                        xReturn = pdTRUE;
+
+                        for( x = ( BaseType_t ) 0; x < ( BaseType_t ) configTASK_NOTIFICATION_ARRAY_ENTRIES; x++ )
+                        {
+                            if( pxTCB->ucNotifyState[ x ] == taskWAITING_NOTIFICATION )
+                            {
+                                xReturn = pdFALSE;
+                                break;
+                            }
+                        }
+                    }
+                    #else /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+                    {
+                        xReturn = pdTRUE;
+                    }
+                    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
                 }
                 else
                 {
@@ -6131,6 +6155,24 @@ static void prvCheckTasksWaitingTermination( void )
                             {
                                 pxTaskStatus->eCurrentState = eBlocked;
                             }
+                            else
+                            {
+                                BaseType_t x;
+
+                                /* The task does not appear on the event list item of
+                                 * and of the RTOS objects, but could still be in the
+                                 * blocked state if it is waiting on its notification
+                                 * rather than waiting on an object.  If not, is
+                                 * suspended. */
+                                for( x = ( BaseType_t ) 0; x < ( BaseType_t ) configTASK_NOTIFICATION_ARRAY_ENTRIES; x++ )
+                                {
+                                    if( pxTCB->ucNotifyState[ x ] == taskWAITING_NOTIFICATION )
+                                    {
+                                        pxTaskStatus->eCurrentState = eBlocked;
+                                        break;
+                                    }
+                                }
+                            }
                         }
                         ( void ) xTaskResumeAll();
                     }

From 9c649ea7d1dd0206092697d73c894fd2c4fe29b3 Mon Sep 17 00:00:00 2001
From: Darian <32921628+Dazza0@users.noreply.github.com>
Date: Wed, 8 Nov 2023 13:34:53 +0800
Subject: [PATCH 107/424] Add time conversion macros (#866)

This commit updates the following time conversion macros:

- pdMS_TO_TICKS: Added cast to "uint64_t" to prevent overflow
- pdTICKS_TO_MS: Added macro to convert ticks to milliseconds

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Co-authored-by: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
---
 include/projdefs.h | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/include/projdefs.h b/include/projdefs.h
index c81ad5684..26f6e4f0c 100644
--- a/include/projdefs.h
+++ b/include/projdefs.h
@@ -39,7 +39,14 @@ typedef void (* TaskFunction_t)( void * );
  * overridden by a macro of the same name defined in FreeRTOSConfig.h in case the
  * definition here is not suitable for your application. */
 #ifndef pdMS_TO_TICKS
-    #define pdMS_TO_TICKS( xTimeInMs )    ( ( TickType_t ) ( ( ( TickType_t ) ( xTimeInMs ) * ( TickType_t ) configTICK_RATE_HZ ) / ( TickType_t ) 1000U ) )
+    #define pdMS_TO_TICKS( xTimeInMs )    ( ( TickType_t ) ( ( ( uint64_t ) ( xTimeInMs ) * ( uint64_t ) configTICK_RATE_HZ ) / ( uint64_t ) 1000U ) )
+#endif
+
+/* Converts a time in ticks to a time in milliseconds.  This macro can be
+ * overridden by a macro of the same name defined in FreeRTOSConfig.h in case the
+ * definition here is not suitable for your application. */
+#ifndef pdTICKS_TO_MS
+    #define pdTICKS_TO_MS( xTimeInTicks )    ( ( TickType_t ) ( ( ( uint64_t ) ( xTimeInTicks ) * ( uint64_t ) 1000U ) / ( uint64_t ) configTICK_RATE_HZ ) )
 #endif
 
 #define pdFALSE                                  ( ( BaseType_t ) 0 )

From ad13a1f8dfeb444dd8a8af52c00814954900dfca Mon Sep 17 00:00:00 2001
From: Soren Ptak <ptaksoren@gmail.com>
Date: Thu, 9 Nov 2023 15:00:06 -0800
Subject: [PATCH 108/424] CI-CD URL Check Change (#880)

* Remove the Kernel's custom URL check to just use the CI-CD Actions one
* Exclude portable directory from formatting check.
---
 .github/actions/url_verifier.sh  | 65 --------------------------------
 .github/workflows/ci.yml         | 15 ++------
 .github/workflows/formatting.yml |  4 +-
 3 files changed, 6 insertions(+), 78 deletions(-)
 delete mode 100755 .github/actions/url_verifier.sh

diff --git a/.github/actions/url_verifier.sh b/.github/actions/url_verifier.sh
deleted file mode 100755
index e9804657b..000000000
--- a/.github/actions/url_verifier.sh
+++ /dev/null
@@ -1,65 +0,0 @@
-#!/bin/bash -
-
-PROJECT=$1
-echo "Verifying url links of: ${PROJECT}"
-if [ ! -d "$PROJECT" ]
-then
-    echo "Directory passed does not exist"
-    exit 2
-fi
-
-USER_AGENT="Mozilla/5.0 (Macintosh; Intel Mac OS X 10_14_6) AppleWebKit/537.36 (KHTML, like Gecko) Chrome/88.0.4324.146 Safari/537.36"
-SCRIPT_RET=0
-
-set -o nounset        # Treat unset variables as an error
-
-declare -A dict
-
-function test {
-    while IFS= read -r LINE; do
-        FILE=$(echo $LINE | cut -f 1 -d ':')
-        URL=$(echo $LINE | grep -IoE '\b(https?|ftp|file)://[-A-Za-z0-9+&@#/%?=~_|!:,.;]*[-A-Za-z0-9+&@#/%=~_|]')
-
-        # remove trailing / if it exists curl diferenciate between links with
-        # and without / at the end
-        # URL=`echo "$URL" | sed 's,/$,,'`
-        dict+=(["$URL"]="$FILE ")
-    done < <(grep -e 'https\?://' ${PROJECT} -RIa --exclude='*.exe' --exclude-dir=.git | tr '*' ' ')
-
-    for UNIQ_URL in ${!dict[@]} # loop urls
-    do
-     CURL_RES=$(curl -si --user-agent "${USER_AGENT}" ${UNIQ_URL} 2>/dev/null| head -n 1 | cut -f 2 -d ' ')
-     RES=$?
-
-        echo "================================="
-        echo "Checking URL: ${UNIQ_URL}"
-
-        if [ "${CURL_RES}" == '' -o "${CURL_RES}" != '200' ]
-        then
-            if [ "${CURL_RES}" == '' ]  # curl returned an error
-            then
-                CURL_RES=$RES
-                SCRIPT_RET=1
-                echo ERROR: Result is: "${CURL_RES}"
-            elif [ "${CURL_RES}" == '403' ]
-            then
-                SCRIPT_RET=1
-                echo ERROR: Result is: "${CURL_RES}"
-            else
-                echo WARNING: Result is: "${CURL_RES}"
-            fi
-        else
-            echo SUCCESS: Result is: "${CURL_RES}"
-        fi
-        echo "================================="
-    done
-
-    if [ "${SCRIPT_RET}" -eq 0 ]
-    then
-        exit 0
-    else
-        exit 1
-    fi
-}
-
-test
diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
index 46c6f7ee0..bc6d8802b 100644
--- a/.github/workflows/ci.yml
+++ b/.github/workflows/ci.yml
@@ -12,6 +12,8 @@ jobs:
       - uses: actions/checkout@v3
       - name: Check Formatting of FreeRTOS-Kernel Files
         uses: FreeRTOS/CI-CD-Github-Actions/formatting@main
+        with:
+          exclude-dirs: portable
 
   spell-check:
       runs-on: ubuntu-latest
@@ -30,18 +32,7 @@ jobs:
       - name: Clone This Repo
         uses: actions/checkout@v3
       - name: Link Verification
-        uses: FreeRTOS/CI-CD-Github-Actions/link-verifier@v2
-
-  url-check:
-    runs-on: ubuntu-latest
-    steps:
-      - uses: actions/checkout@v3
-        with:
-          path: ./kernel
-
-      - name: URL Checker
-        run: |
-          bash kernel/.github/actions/url_verifier.sh kernel
+        uses: FreeRTOS/CI-CD-Github-Actions/link-verifier@main
 
   verify-manifest:
     runs-on: ubuntu-latest
diff --git a/.github/workflows/formatting.yml b/.github/workflows/formatting.yml
index 04786bad5..14d41c9c0 100644
--- a/.github/workflows/formatting.yml
+++ b/.github/workflows/formatting.yml
@@ -19,5 +19,7 @@ jobs:
     runs-on: ubuntu-20.04
     steps:
     - name: Apply Formatting Fix
+      id: check-formatting  
       uses: FreeRTOS/CI-CD-Github-Actions/formatting-bot@main
-      id: check-formatting
+      with:
+        exclude-dirs: portable

From dc09a3dd5144c4033607565c71b9919900f95cff Mon Sep 17 00:00:00 2001
From: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Date: Thu, 16 Nov 2023 09:04:05 +0800
Subject: [PATCH 109/424] Add vApplicationGetPassiveIdleTaskMemory for SMP
 (#890)

* Update vApplicationGetIdleTaskMemory prototype for SMP. Now SMP and
  single core use the same prototype for compatibility.
* Add vApplicationGetPassiveIdleTaskMemory for SMP to get passive idle
  task memory.
---
 include/task.h | 30 ++++++++++++-------------
 tasks.c        | 61 +++++++++++++++++++++++++++++---------------------
 2 files changed, 49 insertions(+), 42 deletions(-)

diff --git a/include/task.h b/include/task.h
index c369f0c1d..9ff199287 100644
--- a/include/task.h
+++ b/include/task.h
@@ -1961,8 +1961,6 @@ configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) PRIVIL
 
 #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
 
-    #if ( configNUMBER_OF_CORES == 1 )
-
 /**
  * task.h
  * @code{c}
@@ -1976,15 +1974,14 @@ configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) PRIVIL
  * @param ppxIdleTaskStackBuffer A handle to a statically allocated Stack buffer for the idle task
  * @param pulIdleTaskStackSize A pointer to the number of elements that will fit in the allocated stack buffer
  */
-        void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer,
-                                            StackType_t ** ppxIdleTaskStackBuffer,
-                                            uint32_t * pulIdleTaskStackSize ); /*lint !e526 Symbol not defined as it is an application callback. */
-    #else /* #if ( configNUMBER_OF_CORES == 1 ) */
+    void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer,
+                                        StackType_t ** ppxIdleTaskStackBuffer,
+                                        uint32_t * pulIdleTaskStackSize ); /*lint !e526 Symbol not defined as it is an application callback. */
 
 /**
  * task.h
  * @code{c}
- * void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, StackType_t ** ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize, BaseType_t xCoreID )
+ * void vApplicationGetPassiveIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, StackType_t ** ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize, BaseType_t xCoreID )
  * @endcode
  *
  * This function is used to provide a statically allocated block of memory to FreeRTOS to hold the Idle Tasks TCB.  This function is required when
@@ -1996,20 +1993,21 @@ configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) PRIVIL
  * These idle tasks are created to ensure that each core has an idle task to run when
  * no other task is available to run.
  *
- * The function vApplicationGetIdleTaskMemory is called with xCoreID 0 to get the
- * memory for Active idle task. It is called with xCoreID 1, 2 ... ( configNUMBER_OF_CORES - 1 )
- * to get memory for passive idle tasks.
+ * The function vApplicationGetPassiveIdleTaskMemory is called with passive idle
+ * task index 0, 1 ... ( configNUMBER_OF_CORES - 2 ) to get memory for passive idle
+ * tasks.
  *
  * @param ppxIdleTaskTCBBuffer A handle to a statically allocated TCB buffer
  * @param ppxIdleTaskStackBuffer A handle to a statically allocated Stack buffer for the idle task
  * @param pulIdleTaskStackSize A pointer to the number of elements that will fit in the allocated stack buffer
- * @param xCoreId The core index of the idle task buffer
+ * @param xPassiveIdleTaskIndex The passive idle task index of the idle task buffer
  */
-        void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer,
-                                            StackType_t ** ppxIdleTaskStackBuffer,
-                                            uint32_t * pulIdleTaskStackSize, /*lint !e526 Symbol not defined as it is an application callback. */
-                                            BaseType_t xCoreID );
-    #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
+    #if ( configNUMBER_OF_CORES > 1 )
+        void vApplicationGetPassiveIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer,
+                                                   StackType_t ** ppxIdleTaskStackBuffer,
+                                                   uint32_t * pulIdleTaskStackSize,
+                                                   BaseType_t xPassiveIdleTaskIndex );
+    #endif /* #if ( configNUMBER_OF_CORES > 1 ) */
 #endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
 
 /**
diff --git a/tasks.c b/tasks.c
index 5500bf435..7770838b2 100644
--- a/tasks.c
+++ b/tasks.c
@@ -3575,10 +3575,21 @@ static BaseType_t prvCreateIdleTasks( void )
             /* The Idle task is created using user provided RAM - obtain the
              * address of the RAM then create the idle task. */
             #if ( configNUMBER_OF_CORES == 1 )
+            {
                 vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize );
+            }
             #else
-                vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize, xCoreID );
-            #endif
+            {
+                if( xCoreID == 0 )
+                {
+                    vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize );
+                }
+                else
+                {
+                    vApplicationGetPassiveIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize, xCoreID - 1 );
+                }
+            }
+            #endif /* if ( configNUMBER_OF_CORES == 1 ) */
             xIdleTaskHandles[ xCoreID ] = xTaskCreateStatic( pxIdleTaskFunction,
                                                              cIdleName,
                                                              ulIdleTaskStackSize,
@@ -8523,36 +8534,34 @@ static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait,
  * it's own implementation of vApplicationGetIdleTaskMemory by setting
  * configKERNEL_PROVIDED_STATIC_MEMORY to 0 or leaving it undefined.
  */
-    #if ( configNUMBER_OF_CORES == 1 )
+    void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer,
+                                        StackType_t ** ppxIdleTaskStackBuffer,
+                                        uint32_t * pulIdleTaskStackSize )
+    {
+        static StaticTask_t xIdleTaskTCB;
+        static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ];
 
-        void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer,
-                                            StackType_t ** ppxIdleTaskStackBuffer,
-                                            uint32_t * pulIdleTaskStackSize )
+        *ppxIdleTaskTCBBuffer = &( xIdleTaskTCB );
+        *ppxIdleTaskStackBuffer = &( uxIdleTaskStack[ 0 ] );
+        *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;
+    }
+
+    #if ( configNUMBER_OF_CORES > 1 )
+
+        void vApplicationGetPassiveIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer,
+                                                   StackType_t ** ppxIdleTaskStackBuffer,
+                                                   uint32_t * pulIdleTaskStackSize,
+                                                   BaseType_t xPassiveIdleTaskIndex )
         {
-            static StaticTask_t xIdleTaskTCB;
-            static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ];
+            static StaticTask_t xIdleTaskTCBs[ configNUMBER_OF_CORES - 1 ];
+            static StackType_t uxIdleTaskStacks[ configNUMBER_OF_CORES - 1 ][ configMINIMAL_STACK_SIZE ];
 
-            *ppxIdleTaskTCBBuffer = &( xIdleTaskTCB );
-            *ppxIdleTaskStackBuffer = &( uxIdleTaskStack[ 0 ] );
+            *ppxIdleTaskTCBBuffer = &( xIdleTaskTCBs[ xPassiveIdleTaskIndex ] );
+            *ppxIdleTaskStackBuffer = &( uxIdleTaskStacks[ xPassiveIdleTaskIndex ][ 0 ] );
             *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;
         }
 
-    #else /* #if ( configNUMBER_OF_CORES == 1 ) */
-
-        void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer,
-                                            StackType_t ** ppxIdleTaskStackBuffer,
-                                            uint32_t * pulIdleTaskStackSize,
-                                            BaseType_t xCoreId )
-        {
-            static StaticTask_t xIdleTaskTCBs[ configNUMBER_OF_CORES ];
-            static StackType_t uxIdleTaskStacks[ configNUMBER_OF_CORES ][ configMINIMAL_STACK_SIZE ];
-
-            *ppxIdleTaskTCBBuffer = &( xIdleTaskTCBs[ xCoreId ] );
-            *ppxIdleTaskStackBuffer = &( uxIdleTaskStacks[ xCoreId ][ 0 ] );
-            *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;
-        }
-
-    #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
+    #endif /* #if ( configNUMBER_OF_CORES > 1 ) */
 
 #endif /* #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configKERNEL_PROVIDED_STATIC_MEMORY == 1 ) && ( portUSING_MPU_WRAPPERS == 0 ) ) */
 /*-----------------------------------------------------------*/

From 5f2bb1b48b6dcd33bcec4309e2df3448a64a7d67 Mon Sep 17 00:00:00 2001
From: Moral-Hao <sihunzhilei@126.com>
Date: Fri, 17 Nov 2023 03:53:27 +0800
Subject: [PATCH 110/424] In smp, every core has a idle task. (#893)

Co-authored-by: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
---
 tasks.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tasks.c b/tasks.c
index 7770838b2..7aa93f7f3 100644
--- a/tasks.c
+++ b/tasks.c
@@ -5865,7 +5865,7 @@ static portTASK_FUNCTION( prvIdleTask, pvParameters )
     {
         #if ( INCLUDE_vTaskSuspend == 1 )
             /* The idle task exists in addition to the application tasks. */
-            const UBaseType_t uxNonApplicationTasks = 1;
+            const UBaseType_t uxNonApplicationTasks = configNUMBER_OF_CORES;
         #endif /* INCLUDE_vTaskSuspend */
 
         eSleepModeStatus eReturn = eStandardSleep;

From 4ff01a7a4a51f53b44496aefee1e3c0071b7b173 Mon Sep 17 00:00:00 2001
From: Ha Thach <thach@tinyusb.org>
Date: Sat, 18 Nov 2023 15:01:50 +0700
Subject: [PATCH 111/424] fix IAR/CM0/portmacro.h missing semicolon (#894)

Co-authored-by: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
---
 portable/IAR/ARM_CM0/portmacro.h | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/portable/IAR/ARM_CM0/portmacro.h b/portable/IAR/ARM_CM0/portmacro.h
index fa8438fec..88cba2016 100644
--- a/portable/IAR/ARM_CM0/portmacro.h
+++ b/portable/IAR/ARM_CM0/portmacro.h
@@ -87,18 +87,18 @@ extern void vPortYield( void );
 #define portNVIC_INT_CTRL     ( ( volatile uint32_t * ) 0xe000ed04 )
 #define portNVIC_PENDSVSET    0x10000000
 #define portYIELD()                vPortYield()
-#define portEND_SWITCHING_ISR( xSwitchRequired )        \
-    do                                                  \
-    {                                                   \
-        if( xSwitchRequired != pdFALSE )                \
-        {                                               \
-            traceISR_EXIT_TO_SCHEDULER();               \
-            *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET \
-        }                                               \
-        else                                            \
-        {                                               \
-            traceISR_EXIT();                            \
-        }                                               \
+#define portEND_SWITCHING_ISR( xSwitchRequired )         \
+    do                                                   \
+    {                                                    \
+        if( xSwitchRequired != pdFALSE )                 \
+        {                                                \
+            traceISR_EXIT_TO_SCHEDULER();                \
+            *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET; \
+        }                                                \
+        else                                             \
+        {                                                \
+            traceISR_EXIT();                             \
+        }                                                \
     } while( 0 )
 #define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/

From 76be28cdc680039cbb748b5bf757d35c26802895 Mon Sep 17 00:00:00 2001
From: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Date: Thu, 23 Nov 2023 10:47:47 +0530
Subject: [PATCH 112/424] Update system call entry mechanism (#898)

Earlier the System Call entry from an unprivileged task
looked like:

1. SVC for entering system call.
2. System call implementation.
3. SVC for exiting system call.

Now, the system call entry needs to make only one SVC
call and everything else is handled internally.

This PR also makes the following changes:

1. Update the Access Control List (ACL) mechanism to
    grant access to all the kernel objects before the
    scheduler is started.
2. Add one struct param for system calls with 5 parameters.
    This removes the need for special handling for system
    calls with 5 parameters.
3. Remove raise privilege SVC when MPU wrapper v2 is used.
4. Add additional run time parameter checks to MPU wrappers
    for xTaskGenericNotify and xQueueTakeMutexRecursive APIs.
---
 include/mpu_prototypes.h                      |   42 +-
 include/mpu_syscall_numbers.h                 |  105 +
 portable/ARMv8M/non_secure/port.c             |  270 +-
 .../GCC/ARM_CM23/mpu_wrappers_v2_asm.c        |  400 +-
 .../portable/GCC/ARM_CM23/portasm.c           |   22 +-
 .../GCC/ARM_CM23_NTZ/mpu_wrappers_v2_asm.c    |  400 +-
 .../portable/GCC/ARM_CM23_NTZ/portasm.c       |   22 +-
 .../GCC/ARM_CM33/mpu_wrappers_v2_asm.c        |  400 +-
 .../portable/GCC/ARM_CM33/portasm.c           |   14 +-
 .../GCC/ARM_CM33_NTZ/mpu_wrappers_v2_asm.c    |  400 +-
 .../portable/GCC/ARM_CM33_NTZ/portasm.c       |   14 +-
 .../IAR/ARM_CM23/mpu_wrappers_v2_asm.S        |  371 +-
 .../portable/IAR/ARM_CM23/portasm.s           |   26 +-
 .../IAR/ARM_CM23_NTZ/mpu_wrappers_v2_asm.S    |  371 +-
 .../portable/IAR/ARM_CM23_NTZ/portasm.s       |   22 +-
 .../IAR/ARM_CM33/mpu_wrappers_v2_asm.S        |  371 +-
 .../portable/IAR/ARM_CM33/portasm.s           |   22 +-
 .../IAR/ARM_CM33_NTZ/mpu_wrappers_v2_asm.S    |  371 +-
 .../portable/IAR/ARM_CM33_NTZ/portasm.s       |   18 +-
 portable/ARMv8M/non_secure/portmacrocommon.h  |   14 +-
 portable/Common/mpu_wrappers_v2.c             |  553 ++-
 .../ARM_CM23/non_secure/mpu_wrappers_v2_asm.c |  400 +-
 portable/GCC/ARM_CM23/non_secure/port.c       |  270 +-
 portable/GCC/ARM_CM23/non_secure/portasm.c    |   22 +-
 .../GCC/ARM_CM23/non_secure/portmacrocommon.h |   14 +-
 .../non_secure/mpu_wrappers_v2_asm.c          |  400 +-
 portable/GCC/ARM_CM23_NTZ/non_secure/port.c   |  270 +-
 .../GCC/ARM_CM23_NTZ/non_secure/portasm.c     |   22 +-
 .../ARM_CM23_NTZ/non_secure/portmacrocommon.h |   14 +-
 .../ARM_CM33/non_secure/mpu_wrappers_v2_asm.c |  400 +-
 portable/GCC/ARM_CM33/non_secure/port.c       |  270 +-
 portable/GCC/ARM_CM33/non_secure/portasm.c    |   14 +-
 .../GCC/ARM_CM33/non_secure/portmacrocommon.h |   14 +-
 .../non_secure/mpu_wrappers_v2_asm.c          |  400 +-
 portable/GCC/ARM_CM33_NTZ/non_secure/port.c   |  270 +-
 .../GCC/ARM_CM33_NTZ/non_secure/portasm.c     |   14 +-
 .../ARM_CM33_NTZ/non_secure/portmacrocommon.h |   14 +-
 .../non_secure/mpu_wrappers_v2_asm.c          |  400 +-
 portable/GCC/ARM_CM35P/non_secure/port.c      |  270 +-
 portable/GCC/ARM_CM35P/non_secure/portasm.c   |   14 +-
 .../ARM_CM35P/non_secure/portmacrocommon.h    |   14 +-
 .../non_secure/mpu_wrappers_v2_asm.c          |  400 +-
 portable/GCC/ARM_CM35P_NTZ/non_secure/port.c  |  270 +-
 .../GCC/ARM_CM35P_NTZ/non_secure/portasm.c    |   14 +-
 .../non_secure/portmacrocommon.h              |   14 +-
 .../GCC/ARM_CM3_MPU/mpu_wrappers_v2_asm.c     |  400 +-
 portable/GCC/ARM_CM3_MPU/port.c               |  281 +-
 portable/GCC/ARM_CM3_MPU/portmacro.h          |   10 +-
 .../GCC/ARM_CM4_MPU/mpu_wrappers_v2_asm.c     |  400 +-
 portable/GCC/ARM_CM4_MPU/port.c               |  295 +-
 portable/GCC/ARM_CM4_MPU/portmacro.h          |   10 +-
 .../ARM_CM55/non_secure/mpu_wrappers_v2_asm.c |  400 +-
 portable/GCC/ARM_CM55/non_secure/port.c       |  270 +-
 portable/GCC/ARM_CM55/non_secure/portasm.c    |   14 +-
 .../GCC/ARM_CM55/non_secure/portmacrocommon.h |   14 +-
 .../non_secure/mpu_wrappers_v2_asm.c          |  400 +-
 portable/GCC/ARM_CM55_NTZ/non_secure/port.c   |  270 +-
 .../GCC/ARM_CM55_NTZ/non_secure/portasm.c     |   14 +-
 .../ARM_CM55_NTZ/non_secure/portmacrocommon.h |   14 +-
 .../ARM_CM85/non_secure/mpu_wrappers_v2_asm.c |  400 +-
 portable/GCC/ARM_CM85/non_secure/port.c       |  270 +-
 portable/GCC/ARM_CM85/non_secure/portasm.c    |   14 +-
 .../GCC/ARM_CM85/non_secure/portmacrocommon.h |   14 +-
 .../non_secure/mpu_wrappers_v2_asm.c          |  400 +-
 portable/GCC/ARM_CM85_NTZ/non_secure/port.c   |  270 +-
 .../GCC/ARM_CM85_NTZ/non_secure/portasm.c     |   14 +-
 .../ARM_CM85_NTZ/non_secure/portmacrocommon.h |   14 +-
 .../ARM_CM23/non_secure/mpu_wrappers_v2_asm.S |  371 +-
 portable/IAR/ARM_CM23/non_secure/port.c       |  270 +-
 portable/IAR/ARM_CM23/non_secure/portasm.s    |   26 +-
 .../IAR/ARM_CM23/non_secure/portmacrocommon.h |   14 +-
 .../non_secure/mpu_wrappers_v2_asm.S          |  371 +-
 portable/IAR/ARM_CM23_NTZ/non_secure/port.c   |  270 +-
 .../IAR/ARM_CM23_NTZ/non_secure/portasm.s     |   22 +-
 .../ARM_CM23_NTZ/non_secure/portmacrocommon.h |   14 +-
 .../ARM_CM33/non_secure/mpu_wrappers_v2_asm.S |  371 +-
 portable/IAR/ARM_CM33/non_secure/port.c       |  270 +-
 portable/IAR/ARM_CM33/non_secure/portasm.s    |   22 +-
 .../IAR/ARM_CM33/non_secure/portmacrocommon.h |   14 +-
 .../non_secure/mpu_wrappers_v2_asm.S          |  371 +-
 portable/IAR/ARM_CM33_NTZ/non_secure/port.c   |  270 +-
 .../IAR/ARM_CM33_NTZ/non_secure/portasm.s     |   18 +-
 .../ARM_CM33_NTZ/non_secure/portmacrocommon.h |   14 +-
 .../non_secure/mpu_wrappers_v2_asm.S          |  371 +-
 portable/IAR/ARM_CM35P/non_secure/port.c      |  270 +-
 portable/IAR/ARM_CM35P/non_secure/portasm.s   |   22 +-
 .../ARM_CM35P/non_secure/portmacrocommon.h    |   14 +-
 .../non_secure/mpu_wrappers_v2_asm.S          |  371 +-
 portable/IAR/ARM_CM35P_NTZ/non_secure/port.c  |  270 +-
 .../IAR/ARM_CM35P_NTZ/non_secure/portasm.s    |   18 +-
 .../non_secure/portmacrocommon.h              |   14 +-
 .../IAR/ARM_CM4F_MPU/mpu_wrappers_v2_asm.S    |  371 +-
 portable/IAR/ARM_CM4F_MPU/port.c              |  285 +-
 portable/IAR/ARM_CM4F_MPU/portasm.s           |   19 +-
 portable/IAR/ARM_CM4F_MPU/portmacro.h         |   10 +-
 .../ARM_CM55/non_secure/mpu_wrappers_v2_asm.S |  371 +-
 portable/IAR/ARM_CM55/non_secure/port.c       |  270 +-
 portable/IAR/ARM_CM55/non_secure/portasm.s    |   22 +-
 .../IAR/ARM_CM55/non_secure/portmacrocommon.h |   14 +-
 .../non_secure/mpu_wrappers_v2_asm.S          |  371 +-
 portable/IAR/ARM_CM55_NTZ/non_secure/port.c   |  270 +-
 .../IAR/ARM_CM55_NTZ/non_secure/portasm.s     |   18 +-
 .../ARM_CM55_NTZ/non_secure/portmacrocommon.h |   14 +-
 .../ARM_CM85/non_secure/mpu_wrappers_v2_asm.S |  371 +-
 portable/IAR/ARM_CM85/non_secure/port.c       |  270 +-
 portable/IAR/ARM_CM85/non_secure/portasm.s    |   22 +-
 .../IAR/ARM_CM85/non_secure/portmacrocommon.h |   14 +-
 .../non_secure/mpu_wrappers_v2_asm.S          |  371 +-
 portable/IAR/ARM_CM85_NTZ/non_secure/port.c   |  270 +-
 .../IAR/ARM_CM85_NTZ/non_secure/portasm.s     |   18 +-
 .../ARM_CM85_NTZ/non_secure/portmacrocommon.h |   14 +-
 .../RVDS/ARM_CM4_MPU/mpu_wrappers_v2_asm.c    | 3434 +++++++----------
 portable/RVDS/ARM_CM4_MPU/port.c              |  334 +-
 portable/RVDS/ARM_CM4_MPU/portmacro.h         |   10 +-
 114 files changed, 7521 insertions(+), 16320 deletions(-)
 create mode 100644 include/mpu_syscall_numbers.h

diff --git a/include/mpu_prototypes.h b/include/mpu_prototypes.h
index 1c9d8c048..547320180 100644
--- a/include/mpu_prototypes.h
+++ b/include/mpu_prototypes.h
@@ -38,6 +38,42 @@
 #ifndef MPU_PROTOTYPES_H
 #define MPU_PROTOTYPES_H
 
+typedef struct xTaskGenericNotifyParams
+{
+    TaskHandle_t xTaskToNotify;
+    UBaseType_t uxIndexToNotify;
+    uint32_t ulValue;
+    eNotifyAction eAction;
+    uint32_t * pulPreviousNotificationValue;
+} xTaskGenericNotifyParams_t;
+
+typedef struct xTaskGenericNotifyWaitParams
+{
+    UBaseType_t uxIndexToWaitOn;
+    uint32_t ulBitsToClearOnEntry;
+    uint32_t ulBitsToClearOnExit;
+    uint32_t * pulNotificationValue;
+    TickType_t xTicksToWait;
+} xTaskGenericNotifyWaitParams_t;
+
+typedef struct xTimerGenericCommandFromTaskParams
+{
+    TimerHandle_t xTimer;
+    BaseType_t xCommandID;
+    TickType_t xOptionalValue;
+    BaseType_t * pxHigherPriorityTaskWoken;
+    TickType_t xTicksToWait;
+} xTimerGenericCommandFromTaskParams_t;
+
+typedef struct xEventGroupWaitBitsParams
+{
+    EventGroupHandle_t xEventGroup;
+    EventBits_t uxBitsToWaitFor;
+    BaseType_t xClearOnExit;
+    BaseType_t xWaitForAllBits;
+    TickType_t xTicksToWait;
+} xEventGroupWaitBitsParams_t;
+
 /* MPU versions of task.h API functions. */
 void MPU_vTaskDelay( const TickType_t xTicksToDelay ) FREERTOS_SYSTEM_CALL;
 BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
@@ -76,11 +112,13 @@ BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
                                    uint32_t ulValue,
                                    eNotifyAction eAction,
                                    uint32_t * pulPreviousNotificationValue ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) FREERTOS_SYSTEM_CALL;
 BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
                                        uint32_t ulBitsToClearOnEntry,
                                        uint32_t ulBitsToClearOnExit,
                                        uint32_t * pulNotificationValue,
                                        TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) FREERTOS_SYSTEM_CALL;
 uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
                                       BaseType_t xClearCountOnExit,
                                       TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
@@ -230,9 +268,10 @@ BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
                                              const TickType_t xOptionalValue,
                                              BaseType_t * const pxHigherPriorityTaskWoken,
                                              const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) FREERTOS_SYSTEM_CALL;
 const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
 void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                              const UBaseType_t uxAutoReload ) FREERTOS_SYSTEM_CALL;
+                              const BaseType_t uxAutoReload ) FREERTOS_SYSTEM_CALL;
 BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
 UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
 TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
@@ -266,6 +305,7 @@ EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
                                      const BaseType_t xClearOnExit,
                                      const BaseType_t xWaitForAllBits,
                                      TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) FREERTOS_SYSTEM_CALL;
 EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
                                       const EventBits_t uxBitsToClear ) FREERTOS_SYSTEM_CALL;
 EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
diff --git a/include/mpu_syscall_numbers.h b/include/mpu_syscall_numbers.h
new file mode 100644
index 000000000..47913c998
--- /dev/null
+++ b/include/mpu_syscall_numbers.h
@@ -0,0 +1,105 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef MPU_SYSCALL_NUMBERS_H
+#define MPU_SYSCALL_NUMBERS_H
+
+/* Numbers assigned to various system calls. */
+#define SYSTEM_CALL_xTaskGenericNotify                     0
+#define SYSTEM_CALL_xTaskGenericNotifyWait                 1
+#define SYSTEM_CALL_xTimerGenericCommandFromTask           2
+#define SYSTEM_CALL_xEventGroupWaitBits                    3
+#define SYSTEM_CALL_xTaskDelayUntil                        4
+#define SYSTEM_CALL_xTaskAbortDelay                        5
+#define SYSTEM_CALL_vTaskDelay                             6
+#define SYSTEM_CALL_uxTaskPriorityGet                      7
+#define SYSTEM_CALL_eTaskGetState                          8
+#define SYSTEM_CALL_vTaskGetInfo                           9
+#define SYSTEM_CALL_xTaskGetIdleTaskHandle                 10
+#define SYSTEM_CALL_vTaskSuspend                           11
+#define SYSTEM_CALL_vTaskResume                            12
+#define SYSTEM_CALL_xTaskGetTickCount                      13
+#define SYSTEM_CALL_uxTaskGetNumberOfTasks                 14
+#define SYSTEM_CALL_ulTaskGetRunTimeCounter                15
+#define SYSTEM_CALL_ulTaskGetRunTimePercent                16
+#define SYSTEM_CALL_ulTaskGetIdleRunTimePercent            17
+#define SYSTEM_CALL_ulTaskGetIdleRunTimeCounter            18
+#define SYSTEM_CALL_vTaskSetApplicationTaskTag             19
+#define SYSTEM_CALL_xTaskGetApplicationTaskTag             20
+#define SYSTEM_CALL_vTaskSetThreadLocalStoragePointer      21
+#define SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer     22
+#define SYSTEM_CALL_uxTaskGetSystemState                   23
+#define SYSTEM_CALL_uxTaskGetStackHighWaterMark            24
+#define SYSTEM_CALL_uxTaskGetStackHighWaterMark2           25
+#define SYSTEM_CALL_xTaskGetCurrentTaskHandle              26
+#define SYSTEM_CALL_xTaskGetSchedulerState                 27
+#define SYSTEM_CALL_vTaskSetTimeOutState                   28
+#define SYSTEM_CALL_xTaskCheckForTimeOut                   29
+#define SYSTEM_CALL_ulTaskGenericNotifyTake                30
+#define SYSTEM_CALL_xTaskGenericNotifyStateClear           31
+#define SYSTEM_CALL_ulTaskGenericNotifyValueClear          32
+#define SYSTEM_CALL_xQueueGenericSend                      33
+#define SYSTEM_CALL_uxQueueMessagesWaiting                 34
+#define SYSTEM_CALL_uxQueueSpacesAvailable                 35
+#define SYSTEM_CALL_xQueueReceive                          36
+#define SYSTEM_CALL_xQueuePeek                             37
+#define SYSTEM_CALL_xQueueSemaphoreTake                    38
+#define SYSTEM_CALL_xQueueGetMutexHolder                   39
+#define SYSTEM_CALL_xQueueTakeMutexRecursive               40
+#define SYSTEM_CALL_xQueueGiveMutexRecursive               41
+#define SYSTEM_CALL_xQueueSelectFromSet                    42
+#define SYSTEM_CALL_xQueueAddToSet                         43
+#define SYSTEM_CALL_vQueueAddToRegistry                    44
+#define SYSTEM_CALL_vQueueUnregisterQueue                  45
+#define SYSTEM_CALL_pcQueueGetName                         46
+#define SYSTEM_CALL_pvTimerGetTimerID                      47
+#define SYSTEM_CALL_vTimerSetTimerID                       48
+#define SYSTEM_CALL_xTimerIsTimerActive                    49
+#define SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle         50
+#define SYSTEM_CALL_pcTimerGetName                         51
+#define SYSTEM_CALL_vTimerSetReloadMode                    52
+#define SYSTEM_CALL_xTimerGetReloadMode                    53
+#define SYSTEM_CALL_uxTimerGetReloadMode                   54
+#define SYSTEM_CALL_xTimerGetPeriod                        55
+#define SYSTEM_CALL_xTimerGetExpiryTime                    56
+#define SYSTEM_CALL_xEventGroupClearBits                   57
+#define SYSTEM_CALL_xEventGroupSetBits                     58
+#define SYSTEM_CALL_xEventGroupSync                        59
+#define SYSTEM_CALL_uxEventGroupGetNumber                  60
+#define SYSTEM_CALL_vEventGroupSetNumber                   61
+#define SYSTEM_CALL_xStreamBufferSend                      62
+#define SYSTEM_CALL_xStreamBufferReceive                   63
+#define SYSTEM_CALL_xStreamBufferIsFull                    64
+#define SYSTEM_CALL_xStreamBufferIsEmpty                   65
+#define SYSTEM_CALL_xStreamBufferSpacesAvailable           66
+#define SYSTEM_CALL_xStreamBufferBytesAvailable            67
+#define SYSTEM_CALL_xStreamBufferSetTriggerLevel           68
+#define SYSTEM_CALL_xStreamBufferNextMessageLengthBytes    69
+#define NUM_SYSTEM_CALLS                                   70  /* Total number of system calls. */
+
+#endif /* MPU_SYSCALL_NUMBERS_H */
diff --git a/portable/ARMv8M/non_secure/port.c b/portable/ARMv8M/non_secure/port.c
index 52d68d3ea..6a3877894 100644
--- a/portable/ARMv8M/non_secure/port.c
+++ b/portable/ARMv8M/non_secure/port.c
@@ -35,8 +35,9 @@
 #include "FreeRTOS.h"
 #include "task.h"
 
-/* MPU wrappers includes. */
+/* MPU includes. */
 #include "mpu_wrappers.h"
+#include "mpu_syscall_numbers.h"
 
 /* Portasm includes. */
 #include "portasm.h"
@@ -436,29 +437,22 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
  * @brief Sets up the system call stack so that upon returning from
  * SVC, the system call stack is used.
  *
- * It is used for the system calls with up to 4 parameters.
- *
  * @param pulTaskStack The current SP when the SVC was raised.
  * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ * @param ucSystemCallNumber The system call number of the system call.
  */
     void vSystemCallEnter( uint32_t * pulTaskStack,
-                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
+                           uint32_t ulLR,
+                           uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
- * @brief Sets up the system call stack so that upon returning from
- * SVC, the system call stack is used.
- *
- * It is used for the system calls with 5 parameters.
- *
- * @param pulTaskStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ * @brief Raise SVC for exiting from a system call.
  */
-    void vSystemCallEnter_1( uint32_t * pulTaskStack,
-                             uint32_t ulLR ) PRIVILEGED_FUNCTION;
+    void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
@@ -488,6 +482,15 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+/**
+ * @brief This variable is set to pdTRUE when the scheduler is started.
+ */
+    PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
+
+#endif
+
 /**
  * @brief Each task maintains its own interrupt status in the critical nesting
  * variable.
@@ -1134,15 +1137,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     void vSystemCallEnter( uint32_t * pulTaskStack,
-                           uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
+                           uint32_t ulLR,
+                           uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */
     {
         extern TaskHandle_t pxCurrentTCB;
+        extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ];
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulSystemCallStack;
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
-
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __syscalls_flash_start__;
@@ -1154,17 +1158,27 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         #endif /* #if defined( __ARMCC_VERSION ) */
 
         ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
 
-        /* If the request did not come from the system call section, do nothing. */
+        /* Checks:
+         * 1. SVC is raised from the system call section (i.e. application is
+         *    not raising SVC directly).
+         * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as
+         *    it is non-NULL only during the execution of a system call (i.e.
+         *    between system call enter and exit).
+         * 3. System call is not for a kernel API disabled by the configuration
+         *    in FreeRTOSConfig.h.
+         * 4. We do not need to check that ucSystemCallNumber is within range
+         *    because the assembly SVC handler checks that before calling
+         *    this function.
+         */
         if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) &&
+            ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) &&
+            ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) )
         {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
             pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
 
-            /* This is not NULL only for the duration of the system call. */
-            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
-
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
@@ -1198,9 +1212,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 pulSystemCallStack[ i ] = pulTaskStack[ i ];
             }
 
-            /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
-             * restore it when we exit from the system call. */
+            /* Store the value of the Link Register before the SVC was raised.
+             * It contains the address of the caller of the System Call entry
+             * point (i.e. the caller of the MPU_<API>). We need to restore it
+             * when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            /* Store the value of the PSPLIM register before the SVC was raised.
+             * We need to restore it when we exit from the system call. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
             {
                 __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
@@ -1215,6 +1233,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             }
             #endif
 
+            /* Start executing the system call upon returning from this handler. */
+            pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
+            /* Raise a request to exit from the system call upon finishing the
+             * system call. */
+            pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit;
+
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
             pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
@@ -1251,127 +1275,9 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    void vSystemCallEnter_1( uint32_t * pulTaskStack,
-                             uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
+    void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */
     {
-        extern TaskHandle_t pxCurrentTCB;
-        xMPU_SETTINGS * pxMpuSettings;
-        uint32_t * pulSystemCallStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-
-        #if defined( __ARMCC_VERSION )
-
-            /* Declaration when these variable are defined in code instead of being
-             * exported from linker scripts. */
-            extern uint32_t * __syscalls_flash_start__;
-            extern uint32_t * __syscalls_flash_end__;
-        #else
-            /* Declaration when these variable are exported from linker scripts. */
-            extern uint32_t __syscalls_flash_start__[];
-            extern uint32_t __syscalls_flash_end__[];
-        #endif /* #if defined( __ARMCC_VERSION ) */
-
-        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-        /* If the request did not come from the system call section, do nothing. */
-        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
-        {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
-
-            /* This is not NULL only for the duration of the system call. */
-            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
-
-            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-            {
-                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
-                {
-                    /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
-                    __asm volatile (
-                        " vpush {s0}         \n" /* Trigger lazy stacking. */
-                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                        ::: "memory"
-                        );
-                }
-                else
-                {
-                    /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
-                }
-            }
-            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
-            {
-                ulStackFrameSize = 8;
-            }
-            #endif /* configENABLE_FPU || configENABLE_MVE */
-
-            /* Make space on the system call stack for the stack frame and
-             * the parameter passed on the stack. We only need to copy one
-             * parameter but we still reserve 2 spaces to keep the stack
-             * double word aligned. */
-            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
-
-            /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
-            {
-                pulSystemCallStack[ i ] = pulTaskStack[ i ];
-            }
-
-            /* Copy the parameter which is passed the stack. */
-            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-            {
-                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
-
-                /* Record if the hardware used padding to force the stack pointer
-                 * to be double word aligned. */
-                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-            }
-            else
-            {
-                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
-
-                /* Record if the hardware used padding to force the stack pointer
-                 * to be double word aligned. */
-                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-            }
-
-            /* Store the value of the LR and PSPLIM registers before the SVC was raised.
-             * We need to restore it when we exit from the system call. */
-            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            #if ( portUSE_PSPLIM_REGISTER == 1 )
-            {
-                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-            }
-            #endif
-
-            /* Use the pulSystemCallStack in thread mode. */
-            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            #if ( portUSE_PSPLIM_REGISTER == 1 )
-            {
-                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-            }
-            #endif
-
-            /* Remember the location where we should copy the stack frame when we exit from
-             * the system call. */
-            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-            /* We ensure in pxPortInitialiseStack that the system call stack is
-             * double word aligned and therefore, there is no need of padding.
-             * Clear the bit[9] of stacked xPSR. */
-            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-            /* Raise the privilege for the duration of the system call. */
-            __asm volatile (
-                " mrs r0, control     \n" /* Obtain current control value. */
-                " movs r1, #1         \n" /* r1 = 1. */
-                " bics r0, r1         \n" /* Clear nPRIV bit. */
-                " msr control, r0     \n" /* Write back new control value. */
-                ::: "r0", "r1", "memory"
-                );
-        }
+        __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" );
     }
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@@ -1388,24 +1294,32 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
-
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
-            extern uint32_t * __syscalls_flash_start__;
-            extern uint32_t * __syscalls_flash_end__;
+            extern uint32_t * __privileged_functions_start__;
+            extern uint32_t * __privileged_functions_end__;
         #else
             /* Declaration when these variable are exported from linker scripts. */
-            extern uint32_t __syscalls_flash_start__[];
-            extern uint32_t __syscalls_flash_end__[];
+            extern uint32_t __privileged_functions_start__[];
+            extern uint32_t __privileged_functions_end__[];
         #endif /* #if defined( __ARMCC_VERSION ) */
 
         ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
+        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
 
-        /* If the request did not come from the system call section, do nothing. */
-        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+        /* Checks:
+         * 1. SVC is raised from the privileged code (i.e. application is not
+         *    raising SVC directly). This SVC is only raised from
+         *    vRequestSystemCallExit which is in the privileged code section.
+         * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL -
+         *    this means that we previously entered a system call and the
+         *    application is not attempting to exit without entering a system
+         *    call.
+         */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) &&
+            ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) )
         {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
             pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
 
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
@@ -1444,9 +1358,14 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Use the pulTaskStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
 
-            /* Restore the LR and PSPLIM to what they were at the time of
-             * system call entry. */
+            /* Return to the caller of the System Call entry point (i.e. the
+             * caller of the MPU_<API>). */
+            pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+            /* Ensure that LR has a valid value.*/
             pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+
+            /* Restore the PSPLIM register to what it was at the time of
+             * system call entry. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
             {
                 __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
@@ -1780,6 +1699,12 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     /* Initialize the critical nesting count ready for the first task. */
     ulCriticalNesting = 0;
 
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+    {
+        xSchedulerRunning = pdTRUE;
+    }
+    #endif
+
     /* Start the first task. */
     vStartFirstTask();
 
@@ -2062,7 +1987,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
 
     void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
                                          int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
@@ -2078,10 +2003,10 @@ BaseType_t xPortIsInsideInterrupt( void )
         xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit );
     }
 
-#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
 
     void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
                                           int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
@@ -2097,10 +2022,10 @@ BaseType_t xPortIsInsideInterrupt( void )
         xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit );
     }
 
-#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
 
@@ -2108,21 +2033,34 @@ BaseType_t xPortIsInsideInterrupt( void )
         {
             uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
             BaseType_t xAccessGranted = pdFALSE;
-            const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+            const xMPU_SETTINGS * xTaskMpuSettings;
 
-            ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
-            ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
-
-            if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+            if( xSchedulerRunning == pdFALSE )
             {
+                /* Grant access to all the kernel objects before the scheduler
+                 * is started. It is necessary because there is no task running
+                 * yet and therefore, we cannot use the permissions of any
+                 * task. */
                 xAccessGranted = pdTRUE;
             }
             else
             {
-                if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+                ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+                ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+                if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
                 {
                     xAccessGranted = pdTRUE;
                 }
+                else
+                {
+                    if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                    {
+                        xAccessGranted = pdTRUE;
+                    }
+                }
             }
 
             return xAccessGranted;
@@ -2141,5 +2079,5 @@ BaseType_t xPortIsInsideInterrupt( void )
 
     #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
 
-#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/mpu_wrappers_v2_asm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/mpu_wrappers_v2_asm.c
index 00c8bcfa8..e67f3cbae 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/mpu_wrappers_v2_asm.c
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/mpu_wrappers_v2_asm.c
@@ -38,6 +38,8 @@
 #include "timers.h"
 #include "event_groups.h"
 #include "stream_buffer.h"
+#include "mpu_prototypes.h"
+#include "mpu_syscall_numbers.h"
 
 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
 /*-----------------------------------------------------------*/
@@ -68,11 +70,8 @@
                 " MPU_xTaskDelayUntil_Unpriv:                           \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskDelayUntilImpl                        \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory"
             );
         }
 
@@ -101,11 +100,8 @@
                 " MPU_xTaskAbortDelay_Unpriv:                           \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskAbortDelayImpl                        \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory"
             );
         }
 
@@ -134,11 +130,8 @@
                 " MPU_vTaskDelay_Unpriv:                                \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskDelayImpl                             \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory"
             );
         }
 
@@ -167,11 +160,8 @@
                 " MPU_uxTaskPriorityGet_Unpriv:                         \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskPriorityGetImpl                      \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory"
             );
         }
 
@@ -200,11 +190,8 @@
                 " MPU_eTaskGetState_Unpriv:                             \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_eTaskGetStateImpl                          \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory"
             );
         }
 
@@ -239,11 +226,8 @@
                 " MPU_vTaskGetInfo_Unpriv:                              \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskGetInfoImpl                           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory"
             );
         }
 
@@ -272,11 +256,8 @@
                 " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetIdleTaskHandleImpl                 \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory"
             );
         }
 
@@ -305,11 +286,8 @@
                 " MPU_vTaskSuspend_Unpriv:                              \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskSuspendImpl                           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory"
             );
         }
 
@@ -338,11 +316,8 @@
                 " MPU_vTaskResume_Unpriv:                               \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskResumeImpl                            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskResume ) : "memory"
             );
         }
 
@@ -369,11 +344,8 @@
             " MPU_xTaskGetTickCount_Unpriv:                         \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xTaskGetTickCountImpl                      \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -398,11 +370,8 @@
             " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_uxTaskGetNumberOfTasksImpl                 \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -429,11 +398,8 @@
                 " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetRunTimeCounterImpl                \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory"
             );
         }
 
@@ -462,11 +428,8 @@
                 " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetRunTimePercentImpl                \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory"
             );
         }
 
@@ -495,11 +458,8 @@
                 " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetIdleRunTimePercentImpl            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory"
             );
         }
 
@@ -528,11 +488,8 @@
                 " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetIdleRunTimeCounterImpl            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory"
             );
         }
 
@@ -563,11 +520,8 @@
                 " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskSetApplicationTaskTagImpl             \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory"
             );
         }
 
@@ -596,11 +550,8 @@
                 " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetApplicationTaskTagImpl             \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory"
             );
         }
 
@@ -633,11 +584,8 @@
                 " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskSetThreadLocalStoragePointerImpl      \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory"
             );
         }
 
@@ -668,11 +616,8 @@
                 " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pvTaskGetThreadLocalStoragePointerImpl     \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory"
             );
         }
 
@@ -705,11 +650,8 @@
                 " MPU_uxTaskGetSystemState_Unpriv:                      \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskGetSystemStateImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory"
             );
         }
 
@@ -738,11 +680,8 @@
                 " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskGetStackHighWaterMarkImpl            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory"
             );
         }
 
@@ -771,11 +710,8 @@
                 " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskGetStackHighWaterMark2Impl           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory"
             );
         }
 
@@ -804,11 +740,8 @@
                 " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetCurrentTaskHandleImpl              \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory"
             );
         }
 
@@ -837,11 +770,8 @@
                 " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetSchedulerStateImpl                 \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory"
             );
         }
 
@@ -868,11 +798,8 @@
             " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_vTaskSetTimeOutStateImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -899,28 +826,17 @@
             " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xTaskCheckForTimeOutImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
 
     #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                           UBaseType_t uxIndexToNotify,
-                                           uint32_t ulValue,
-                                           eNotifyAction eAction,
-                                           uint32_t * pulPreviousNotificationValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                           UBaseType_t uxIndexToNotify,
-                                           uint32_t ulValue,
-                                           eNotifyAction eAction,
-                                           uint32_t * pulPreviousNotificationValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
@@ -938,11 +854,8 @@
                 " MPU_xTaskGenericNotify_Unpriv:                        \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGenericNotifyImpl                     \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory"
             );
         }
 
@@ -951,17 +864,9 @@
 
     #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                               uint32_t ulBitsToClearOnEntry,
-                                               uint32_t ulBitsToClearOnExit,
-                                               uint32_t * pulNotificationValue,
-                                               TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                               uint32_t ulBitsToClearOnEntry,
-                                               uint32_t ulBitsToClearOnExit,
-                                               uint32_t * pulNotificationValue,
-                                               TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
@@ -979,11 +884,8 @@
                 " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGenericNotifyWaitImpl                 \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory"
             );
         }
 
@@ -1016,11 +918,8 @@
                 " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGenericNotifyTakeImpl                \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory"
             );
         }
 
@@ -1051,11 +950,8 @@
                 " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGenericNotifyStateClearImpl           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory"
             );
         }
 
@@ -1088,11 +984,8 @@
                 " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGenericNotifyValueClearImpl          \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory"
             );
         }
 
@@ -1125,11 +1018,8 @@
             " MPU_xQueueGenericSend_Unpriv:                         \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueueGenericSendImpl                      \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1154,11 +1044,8 @@
             " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_uxQueueMessagesWaitingImpl                 \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1183,11 +1070,8 @@
             " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_uxQueueSpacesAvailableImpl                 \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1216,11 +1100,8 @@
             " MPU_xQueueReceive_Unpriv:                             \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueueReceiveImpl                          \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1249,11 +1130,8 @@
             " MPU_xQueuePeek_Unpriv:                                \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueuePeekImpl                             \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1280,11 +1158,8 @@
             " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueueSemaphoreTakeImpl                    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1311,11 +1186,8 @@
                 " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueGetMutexHolderImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory"
             );
         }
 
@@ -1346,11 +1218,8 @@
                 " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueTakeMutexRecursiveImpl               \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory"
             );
         }
 
@@ -1379,11 +1248,8 @@
                 " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueGiveMutexRecursiveImpl               \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory"
             );
         }
 
@@ -1414,11 +1280,8 @@
                 " MPU_xQueueSelectFromSet_Unpriv:                       \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueSelectFromSetImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory"
             );
         }
 
@@ -1449,11 +1312,8 @@
                 " MPU_xQueueAddToSet_Unpriv:                            \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueAddToSetImpl                         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory"
             );
         }
 
@@ -1484,11 +1344,8 @@
                 " MPU_vQueueAddToRegistry_Unpriv:                       \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vQueueAddToRegistryImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory"
             );
         }
 
@@ -1517,11 +1374,8 @@
                 " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vQueueUnregisterQueueImpl                  \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory"
             );
         }
 
@@ -1550,11 +1404,8 @@
                 " MPU_pcQueueGetName_Unpriv:                            \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pcQueueGetNameImpl                         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory"
             );
         }
 
@@ -1583,11 +1434,8 @@
                 " MPU_pvTimerGetTimerID_Unpriv:                         \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pvTimerGetTimerIDImpl                      \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory"
             );
         }
 
@@ -1618,11 +1466,8 @@
                 " MPU_vTimerSetTimerID_Unpriv:                          \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTimerSetTimerIDImpl                       \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory"
             );
         }
 
@@ -1651,11 +1496,8 @@
                 " MPU_xTimerIsTimerActive_Unpriv:                       \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerIsTimerActiveImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory"
             );
         }
 
@@ -1684,11 +1526,8 @@
                 " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetTimerDaemonTaskHandleImpl         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory"
             );
         }
 
@@ -1697,17 +1536,9 @@
 
     #if ( configUSE_TIMERS == 1 )
 
-        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                                     const BaseType_t xCommandID,
-                                                     const TickType_t xOptionalValue,
-                                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                                     const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                                     const BaseType_t xCommandID,
-                                                     const TickType_t xOptionalValue,
-                                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                                     const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
@@ -1725,11 +1556,8 @@
                 " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
                 "     pop {r0, r1}                                              \n"
                 "     svc %0                                                    \n"
-                "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
-                "     svc %1                                                    \n"
-                "     bx lr                                                     \n"
                 "                                                               \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory"
             );
         }
 
@@ -1758,11 +1586,8 @@
                 " MPU_pcTimerGetName_Unpriv:                            \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pcTimerGetNameImpl                         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory"
             );
         }
 
@@ -1793,11 +1618,8 @@
                 " MPU_vTimerSetReloadMode_Unpriv:                       \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTimerSetReloadModeImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory"
             );
         }
 
@@ -1826,11 +1648,8 @@
                 " MPU_xTimerGetReloadMode_Unpriv:                       \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetReloadModeImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory"
             );
         }
 
@@ -1859,11 +1678,8 @@
                 " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTimerGetReloadModeImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory"
             );
         }
 
@@ -1892,11 +1708,8 @@
                 " MPU_xTimerGetPeriod_Unpriv:                           \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetPeriodImpl                        \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory"
             );
         }
 
@@ -1925,28 +1738,17 @@
                 " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetExpiryTimeImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory"
             );
         }
 
     #endif /* if ( configUSE_TIMERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
-                                         const EventBits_t uxBitsToWaitFor,
-                                         const BaseType_t xClearOnExit,
-                                         const BaseType_t xWaitForAllBits,
-                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
-                                         const EventBits_t uxBitsToWaitFor,
-                                         const BaseType_t xClearOnExit,
-                                         const BaseType_t xWaitForAllBits,
-                                         TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
     {
         __asm volatile
         (
@@ -1964,11 +1766,8 @@
             " MPU_xEventGroupWaitBits_Unpriv:                       \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupWaitBitsImpl                    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1995,11 +1794,8 @@
             " MPU_xEventGroupClearBits_Unpriv:                      \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupClearBitsImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2026,11 +1822,8 @@
             " MPU_xEventGroupSetBits_Unpriv:                        \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupSetBitsImpl                     \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2061,11 +1854,8 @@
             " MPU_xEventGroupSync_Unpriv:                           \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupSyncImpl                        \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2092,11 +1882,8 @@
                 " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxEventGroupGetNumberImpl                  \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory"
             );
         }
 
@@ -2127,11 +1914,8 @@
                 " MPU_vEventGroupSetNumber_Unpriv:                      \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vEventGroupSetNumberImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory"
             );
         }
 
@@ -2164,11 +1948,8 @@
             " MPU_xStreamBufferSend_Unpriv:                         \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferSendImpl                      \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2199,11 +1980,8 @@
             " MPU_xStreamBufferReceive_Unpriv:                      \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferReceiveImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2228,11 +2006,8 @@
             " MPU_xStreamBufferIsFull_Unpriv:                       \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferIsFullImpl                    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2257,11 +2032,8 @@
             " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferIsEmptyImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2286,11 +2058,8 @@
             " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferSpacesAvailableImpl           \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2315,11 +2084,8 @@
             " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferBytesAvailableImpl            \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2346,11 +2112,8 @@
             " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferSetTriggerLevelImpl           \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2375,11 +2138,8 @@
             " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferNextMessageLengthBytesImpl    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portasm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portasm.c
index 1b41d587f..f8b37b691 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portasm.c
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portasm.c
@@ -36,6 +36,9 @@
 /* Portasm includes. */
 #include "portasm.h"
 
+/* System call numbers includes. */
+#include "mpu_syscall_numbers.h"
+
 /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
  * header files. */
 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
@@ -538,7 +541,6 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             ".syntax unified                \n"
             ".extern vPortSVCHandler_C      \n"
             ".extern vSystemCallEnter       \n"
-            ".extern vSystemCallEnter_1     \n"
             ".extern vSystemCallExit        \n"
             "                               \n"
             "movs r0, #4                    \n"
@@ -553,26 +555,22 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    b route_svc                \n"
             "                               \n"
             "route_svc:                     \n"
-            "    ldr r2, [r0, #24]          \n"
-            "    subs r2, #2                \n"
-            "    ldrb r3, [r2, #0]          \n"
-            "    cmp r3, %0                 \n"
-            "    beq system_call_enter      \n"
-            "    cmp r3, %1                 \n"
-            "    beq system_call_enter_1    \n"
-            "    cmp r3, %2                 \n"
+            "    ldr r3, [r0, #24]          \n"
+            "    subs r3, #2                \n"
+            "    ldrb r2, [r3, #0]          \n"
+            "    cmp r2, %0                 \n"
+            "    blt system_call_enter      \n"
+            "    cmp r2, %1                 \n"
             "    beq system_call_exit       \n"
             "    b vPortSVCHandler_C        \n"
             "                               \n"
             "system_call_enter:             \n"
             "    b vSystemCallEnter         \n"
-            "system_call_enter_1:           \n"
-            "    b vSystemCallEnter_1       \n"
             "system_call_exit:              \n"
             "    b vSystemCallExit          \n"
             "                               \n"
             : /* No outputs. */
-            : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT )
+            : "i" ( NUM_SYSTEM_CALLS ), "i" ( portSVC_SYSTEM_CALL_EXIT )
             : "r0", "r1", "r2", "r3", "memory"
         );
     }
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/mpu_wrappers_v2_asm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/mpu_wrappers_v2_asm.c
index 00c8bcfa8..e67f3cbae 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/mpu_wrappers_v2_asm.c
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/mpu_wrappers_v2_asm.c
@@ -38,6 +38,8 @@
 #include "timers.h"
 #include "event_groups.h"
 #include "stream_buffer.h"
+#include "mpu_prototypes.h"
+#include "mpu_syscall_numbers.h"
 
 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
 /*-----------------------------------------------------------*/
@@ -68,11 +70,8 @@
                 " MPU_xTaskDelayUntil_Unpriv:                           \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskDelayUntilImpl                        \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory"
             );
         }
 
@@ -101,11 +100,8 @@
                 " MPU_xTaskAbortDelay_Unpriv:                           \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskAbortDelayImpl                        \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory"
             );
         }
 
@@ -134,11 +130,8 @@
                 " MPU_vTaskDelay_Unpriv:                                \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskDelayImpl                             \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory"
             );
         }
 
@@ -167,11 +160,8 @@
                 " MPU_uxTaskPriorityGet_Unpriv:                         \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskPriorityGetImpl                      \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory"
             );
         }
 
@@ -200,11 +190,8 @@
                 " MPU_eTaskGetState_Unpriv:                             \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_eTaskGetStateImpl                          \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory"
             );
         }
 
@@ -239,11 +226,8 @@
                 " MPU_vTaskGetInfo_Unpriv:                              \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskGetInfoImpl                           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory"
             );
         }
 
@@ -272,11 +256,8 @@
                 " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetIdleTaskHandleImpl                 \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory"
             );
         }
 
@@ -305,11 +286,8 @@
                 " MPU_vTaskSuspend_Unpriv:                              \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskSuspendImpl                           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory"
             );
         }
 
@@ -338,11 +316,8 @@
                 " MPU_vTaskResume_Unpriv:                               \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskResumeImpl                            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskResume ) : "memory"
             );
         }
 
@@ -369,11 +344,8 @@
             " MPU_xTaskGetTickCount_Unpriv:                         \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xTaskGetTickCountImpl                      \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -398,11 +370,8 @@
             " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_uxTaskGetNumberOfTasksImpl                 \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -429,11 +398,8 @@
                 " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetRunTimeCounterImpl                \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory"
             );
         }
 
@@ -462,11 +428,8 @@
                 " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetRunTimePercentImpl                \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory"
             );
         }
 
@@ -495,11 +458,8 @@
                 " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetIdleRunTimePercentImpl            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory"
             );
         }
 
@@ -528,11 +488,8 @@
                 " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetIdleRunTimeCounterImpl            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory"
             );
         }
 
@@ -563,11 +520,8 @@
                 " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskSetApplicationTaskTagImpl             \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory"
             );
         }
 
@@ -596,11 +550,8 @@
                 " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetApplicationTaskTagImpl             \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory"
             );
         }
 
@@ -633,11 +584,8 @@
                 " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskSetThreadLocalStoragePointerImpl      \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory"
             );
         }
 
@@ -668,11 +616,8 @@
                 " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pvTaskGetThreadLocalStoragePointerImpl     \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory"
             );
         }
 
@@ -705,11 +650,8 @@
                 " MPU_uxTaskGetSystemState_Unpriv:                      \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskGetSystemStateImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory"
             );
         }
 
@@ -738,11 +680,8 @@
                 " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskGetStackHighWaterMarkImpl            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory"
             );
         }
 
@@ -771,11 +710,8 @@
                 " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskGetStackHighWaterMark2Impl           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory"
             );
         }
 
@@ -804,11 +740,8 @@
                 " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetCurrentTaskHandleImpl              \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory"
             );
         }
 
@@ -837,11 +770,8 @@
                 " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetSchedulerStateImpl                 \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory"
             );
         }
 
@@ -868,11 +798,8 @@
             " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_vTaskSetTimeOutStateImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -899,28 +826,17 @@
             " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xTaskCheckForTimeOutImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
 
     #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                           UBaseType_t uxIndexToNotify,
-                                           uint32_t ulValue,
-                                           eNotifyAction eAction,
-                                           uint32_t * pulPreviousNotificationValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                           UBaseType_t uxIndexToNotify,
-                                           uint32_t ulValue,
-                                           eNotifyAction eAction,
-                                           uint32_t * pulPreviousNotificationValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
@@ -938,11 +854,8 @@
                 " MPU_xTaskGenericNotify_Unpriv:                        \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGenericNotifyImpl                     \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory"
             );
         }
 
@@ -951,17 +864,9 @@
 
     #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                               uint32_t ulBitsToClearOnEntry,
-                                               uint32_t ulBitsToClearOnExit,
-                                               uint32_t * pulNotificationValue,
-                                               TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                               uint32_t ulBitsToClearOnEntry,
-                                               uint32_t ulBitsToClearOnExit,
-                                               uint32_t * pulNotificationValue,
-                                               TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
@@ -979,11 +884,8 @@
                 " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGenericNotifyWaitImpl                 \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory"
             );
         }
 
@@ -1016,11 +918,8 @@
                 " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGenericNotifyTakeImpl                \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory"
             );
         }
 
@@ -1051,11 +950,8 @@
                 " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGenericNotifyStateClearImpl           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory"
             );
         }
 
@@ -1088,11 +984,8 @@
                 " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGenericNotifyValueClearImpl          \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory"
             );
         }
 
@@ -1125,11 +1018,8 @@
             " MPU_xQueueGenericSend_Unpriv:                         \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueueGenericSendImpl                      \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1154,11 +1044,8 @@
             " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_uxQueueMessagesWaitingImpl                 \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1183,11 +1070,8 @@
             " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_uxQueueSpacesAvailableImpl                 \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1216,11 +1100,8 @@
             " MPU_xQueueReceive_Unpriv:                             \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueueReceiveImpl                          \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1249,11 +1130,8 @@
             " MPU_xQueuePeek_Unpriv:                                \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueuePeekImpl                             \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1280,11 +1158,8 @@
             " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueueSemaphoreTakeImpl                    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1311,11 +1186,8 @@
                 " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueGetMutexHolderImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory"
             );
         }
 
@@ -1346,11 +1218,8 @@
                 " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueTakeMutexRecursiveImpl               \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory"
             );
         }
 
@@ -1379,11 +1248,8 @@
                 " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueGiveMutexRecursiveImpl               \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory"
             );
         }
 
@@ -1414,11 +1280,8 @@
                 " MPU_xQueueSelectFromSet_Unpriv:                       \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueSelectFromSetImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory"
             );
         }
 
@@ -1449,11 +1312,8 @@
                 " MPU_xQueueAddToSet_Unpriv:                            \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueAddToSetImpl                         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory"
             );
         }
 
@@ -1484,11 +1344,8 @@
                 " MPU_vQueueAddToRegistry_Unpriv:                       \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vQueueAddToRegistryImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory"
             );
         }
 
@@ -1517,11 +1374,8 @@
                 " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vQueueUnregisterQueueImpl                  \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory"
             );
         }
 
@@ -1550,11 +1404,8 @@
                 " MPU_pcQueueGetName_Unpriv:                            \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pcQueueGetNameImpl                         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory"
             );
         }
 
@@ -1583,11 +1434,8 @@
                 " MPU_pvTimerGetTimerID_Unpriv:                         \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pvTimerGetTimerIDImpl                      \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory"
             );
         }
 
@@ -1618,11 +1466,8 @@
                 " MPU_vTimerSetTimerID_Unpriv:                          \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTimerSetTimerIDImpl                       \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory"
             );
         }
 
@@ -1651,11 +1496,8 @@
                 " MPU_xTimerIsTimerActive_Unpriv:                       \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerIsTimerActiveImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory"
             );
         }
 
@@ -1684,11 +1526,8 @@
                 " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetTimerDaemonTaskHandleImpl         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory"
             );
         }
 
@@ -1697,17 +1536,9 @@
 
     #if ( configUSE_TIMERS == 1 )
 
-        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                                     const BaseType_t xCommandID,
-                                                     const TickType_t xOptionalValue,
-                                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                                     const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                                     const BaseType_t xCommandID,
-                                                     const TickType_t xOptionalValue,
-                                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                                     const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
@@ -1725,11 +1556,8 @@
                 " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
                 "     pop {r0, r1}                                              \n"
                 "     svc %0                                                    \n"
-                "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
-                "     svc %1                                                    \n"
-                "     bx lr                                                     \n"
                 "                                                               \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory"
             );
         }
 
@@ -1758,11 +1586,8 @@
                 " MPU_pcTimerGetName_Unpriv:                            \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pcTimerGetNameImpl                         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory"
             );
         }
 
@@ -1793,11 +1618,8 @@
                 " MPU_vTimerSetReloadMode_Unpriv:                       \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTimerSetReloadModeImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory"
             );
         }
 
@@ -1826,11 +1648,8 @@
                 " MPU_xTimerGetReloadMode_Unpriv:                       \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetReloadModeImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory"
             );
         }
 
@@ -1859,11 +1678,8 @@
                 " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTimerGetReloadModeImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory"
             );
         }
 
@@ -1892,11 +1708,8 @@
                 " MPU_xTimerGetPeriod_Unpriv:                           \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetPeriodImpl                        \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory"
             );
         }
 
@@ -1925,28 +1738,17 @@
                 " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetExpiryTimeImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory"
             );
         }
 
     #endif /* if ( configUSE_TIMERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
-                                         const EventBits_t uxBitsToWaitFor,
-                                         const BaseType_t xClearOnExit,
-                                         const BaseType_t xWaitForAllBits,
-                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
-                                         const EventBits_t uxBitsToWaitFor,
-                                         const BaseType_t xClearOnExit,
-                                         const BaseType_t xWaitForAllBits,
-                                         TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
     {
         __asm volatile
         (
@@ -1964,11 +1766,8 @@
             " MPU_xEventGroupWaitBits_Unpriv:                       \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupWaitBitsImpl                    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1995,11 +1794,8 @@
             " MPU_xEventGroupClearBits_Unpriv:                      \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupClearBitsImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2026,11 +1822,8 @@
             " MPU_xEventGroupSetBits_Unpriv:                        \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupSetBitsImpl                     \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2061,11 +1854,8 @@
             " MPU_xEventGroupSync_Unpriv:                           \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupSyncImpl                        \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2092,11 +1882,8 @@
                 " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxEventGroupGetNumberImpl                  \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory"
             );
         }
 
@@ -2127,11 +1914,8 @@
                 " MPU_vEventGroupSetNumber_Unpriv:                      \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vEventGroupSetNumberImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory"
             );
         }
 
@@ -2164,11 +1948,8 @@
             " MPU_xStreamBufferSend_Unpriv:                         \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferSendImpl                      \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2199,11 +1980,8 @@
             " MPU_xStreamBufferReceive_Unpriv:                      \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferReceiveImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2228,11 +2006,8 @@
             " MPU_xStreamBufferIsFull_Unpriv:                       \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferIsFullImpl                    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2257,11 +2032,8 @@
             " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferIsEmptyImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2286,11 +2058,8 @@
             " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferSpacesAvailableImpl           \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2315,11 +2084,8 @@
             " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferBytesAvailableImpl            \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2346,11 +2112,8 @@
             " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferSetTriggerLevelImpl           \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2375,11 +2138,8 @@
             " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferNextMessageLengthBytesImpl    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portasm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portasm.c
index ed4933812..5fde8342e 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portasm.c
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portasm.c
@@ -36,6 +36,9 @@
 /* Portasm includes. */
 #include "portasm.h"
 
+/* System call numbers includes. */
+#include "mpu_syscall_numbers.h"
+
 /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
  * header files. */
 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
@@ -478,7 +481,6 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             ".syntax unified                \n"
             ".extern vPortSVCHandler_C      \n"
             ".extern vSystemCallEnter       \n"
-            ".extern vSystemCallEnter_1     \n"
             ".extern vSystemCallExit        \n"
             "                               \n"
             "movs r0, #4                    \n"
@@ -493,26 +495,22 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    b route_svc                \n"
             "                               \n"
             "route_svc:                     \n"
-            "    ldr r2, [r0, #24]          \n"
-            "    subs r2, #2                \n"
-            "    ldrb r3, [r2, #0]          \n"
-            "    cmp r3, %0                 \n"
-            "    beq system_call_enter      \n"
-            "    cmp r3, %1                 \n"
-            "    beq system_call_enter_1    \n"
-            "    cmp r3, %2                 \n"
+            "    ldr r3, [r0, #24]          \n"
+            "    subs r3, #2                \n"
+            "    ldrb r2, [r3, #0]          \n"
+            "    cmp r2, %0                 \n"
+            "    blt system_call_enter      \n"
+            "    cmp r2, %1                 \n"
             "    beq system_call_exit       \n"
             "    b vPortSVCHandler_C        \n"
             "                               \n"
             "system_call_enter:             \n"
             "    b vSystemCallEnter         \n"
-            "system_call_enter_1:           \n"
-            "    b vSystemCallEnter_1       \n"
             "system_call_exit:              \n"
             "    b vSystemCallExit          \n"
             "                               \n"
             : /* No outputs. */
-            : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT )
+            : "i" ( NUM_SYSTEM_CALLS ), "i" ( portSVC_SYSTEM_CALL_EXIT )
             : "r0", "r1", "r2", "r3", "memory"
         );
     }
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/mpu_wrappers_v2_asm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/mpu_wrappers_v2_asm.c
index d1fbdc0e5..4cb310afd 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/mpu_wrappers_v2_asm.c
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/mpu_wrappers_v2_asm.c
@@ -38,6 +38,8 @@
 #include "timers.h"
 #include "event_groups.h"
 #include "stream_buffer.h"
+#include "mpu_prototypes.h"
+#include "mpu_syscall_numbers.h"
 
 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
 /*-----------------------------------------------------------*/
@@ -67,11 +69,8 @@
                 " MPU_xTaskDelayUntil_Unpriv:                           \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskDelayUntilImpl                        \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory"
             );
         }
 
@@ -99,11 +98,8 @@
                 " MPU_xTaskAbortDelay_Unpriv:                           \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskAbortDelayImpl                        \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory"
             );
         }
 
@@ -131,11 +127,8 @@
                 " MPU_vTaskDelay_Unpriv:                                \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskDelayImpl                             \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory"
             );
         }
 
@@ -163,11 +156,8 @@
                 " MPU_uxTaskPriorityGet_Unpriv:                         \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskPriorityGetImpl                      \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory"
             );
         }
 
@@ -195,11 +185,8 @@
                 " MPU_eTaskGetState_Unpriv:                             \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_eTaskGetStateImpl                          \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory"
             );
         }
 
@@ -233,11 +220,8 @@
                 " MPU_vTaskGetInfo_Unpriv:                              \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskGetInfoImpl                           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory"
             );
         }
 
@@ -265,11 +249,8 @@
                 " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetIdleTaskHandleImpl                 \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory"
             );
         }
 
@@ -297,11 +278,8 @@
                 " MPU_vTaskSuspend_Unpriv:                              \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskSuspendImpl                           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory"
             );
         }
 
@@ -329,11 +307,8 @@
                 " MPU_vTaskResume_Unpriv:                               \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskResumeImpl                            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskResume ) : "memory"
             );
         }
 
@@ -359,11 +334,8 @@
             " MPU_xTaskGetTickCount_Unpriv:                         \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xTaskGetTickCountImpl                      \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -387,11 +359,8 @@
             " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_uxTaskGetNumberOfTasksImpl                 \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -417,11 +386,8 @@
                 " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetRunTimeCounterImpl                \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory"
             );
         }
 
@@ -449,11 +415,8 @@
                 " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetRunTimePercentImpl                \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory"
             );
         }
 
@@ -481,11 +444,8 @@
                 " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetIdleRunTimePercentImpl            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory"
             );
         }
 
@@ -513,11 +473,8 @@
                 " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetIdleRunTimeCounterImpl            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory"
             );
         }
 
@@ -547,11 +504,8 @@
                 " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskSetApplicationTaskTagImpl             \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory"
             );
         }
 
@@ -579,11 +533,8 @@
                 " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetApplicationTaskTagImpl             \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory"
             );
         }
 
@@ -615,11 +566,8 @@
                 " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskSetThreadLocalStoragePointerImpl      \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory"
             );
         }
 
@@ -649,11 +597,8 @@
                 " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pvTaskGetThreadLocalStoragePointerImpl     \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory"
             );
         }
 
@@ -685,11 +630,8 @@
                 " MPU_uxTaskGetSystemState_Unpriv:                      \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskGetSystemStateImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory"
             );
         }
 
@@ -717,11 +659,8 @@
                 " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskGetStackHighWaterMarkImpl            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory"
             );
         }
 
@@ -749,11 +688,8 @@
                 " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskGetStackHighWaterMark2Impl           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory"
             );
         }
 
@@ -781,11 +717,8 @@
                 " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetCurrentTaskHandleImpl              \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory"
             );
         }
 
@@ -813,11 +746,8 @@
                 " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetSchedulerStateImpl                 \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory"
             );
         }
 
@@ -843,11 +773,8 @@
             " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_vTaskSetTimeOutStateImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -873,28 +800,17 @@
             " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xTaskCheckForTimeOutImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
 
     #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                           UBaseType_t uxIndexToNotify,
-                                           uint32_t ulValue,
-                                           eNotifyAction eAction,
-                                           uint32_t * pulPreviousNotificationValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                           UBaseType_t uxIndexToNotify,
-                                           uint32_t ulValue,
-                                           eNotifyAction eAction,
-                                           uint32_t * pulPreviousNotificationValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
@@ -911,11 +827,8 @@
                 " MPU_xTaskGenericNotify_Unpriv:                        \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGenericNotifyImpl                     \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory"
             );
         }
 
@@ -924,17 +837,9 @@
 
     #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                               uint32_t ulBitsToClearOnEntry,
-                                               uint32_t ulBitsToClearOnExit,
-                                               uint32_t * pulNotificationValue,
-                                               TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                               uint32_t ulBitsToClearOnEntry,
-                                               uint32_t ulBitsToClearOnExit,
-                                               uint32_t * pulNotificationValue,
-                                               TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
@@ -951,11 +856,8 @@
                 " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGenericNotifyWaitImpl                 \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory"
             );
         }
 
@@ -987,11 +889,8 @@
                 " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGenericNotifyTakeImpl                \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory"
             );
         }
 
@@ -1021,11 +920,8 @@
                 " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGenericNotifyStateClearImpl           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory"
             );
         }
 
@@ -1057,11 +953,8 @@
                 " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGenericNotifyValueClearImpl          \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory"
             );
         }
 
@@ -1093,11 +986,8 @@
             " MPU_xQueueGenericSend_Unpriv:                         \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueueGenericSendImpl                      \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1121,11 +1011,8 @@
             " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_uxQueueMessagesWaitingImpl                 \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1149,11 +1036,8 @@
             " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_uxQueueSpacesAvailableImpl                 \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1181,11 +1065,8 @@
             " MPU_xQueueReceive_Unpriv:                             \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueueReceiveImpl                          \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1213,11 +1094,8 @@
             " MPU_xQueuePeek_Unpriv:                                \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueuePeekImpl                             \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1243,11 +1121,8 @@
             " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueueSemaphoreTakeImpl                    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1273,11 +1148,8 @@
                 " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueGetMutexHolderImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory"
             );
         }
 
@@ -1307,11 +1179,8 @@
                 " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueTakeMutexRecursiveImpl               \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory"
             );
         }
 
@@ -1339,11 +1208,8 @@
                 " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueGiveMutexRecursiveImpl               \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory"
             );
         }
 
@@ -1373,11 +1239,8 @@
                 " MPU_xQueueSelectFromSet_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueSelectFromSetImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory"
             );
         }
 
@@ -1407,11 +1270,8 @@
                 " MPU_xQueueAddToSet_Unpriv:                            \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueAddToSetImpl                         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory"
             );
         }
 
@@ -1441,11 +1301,8 @@
                 " MPU_vQueueAddToRegistry_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vQueueAddToRegistryImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory"
             );
         }
 
@@ -1473,11 +1330,8 @@
                 " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vQueueUnregisterQueueImpl                  \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory"
             );
         }
 
@@ -1505,11 +1359,8 @@
                 " MPU_pcQueueGetName_Unpriv:                            \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pcQueueGetNameImpl                         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory"
             );
         }
 
@@ -1537,11 +1388,8 @@
                 " MPU_pvTimerGetTimerID_Unpriv:                         \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pvTimerGetTimerIDImpl                      \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory"
             );
         }
 
@@ -1571,11 +1419,8 @@
                 " MPU_vTimerSetTimerID_Unpriv:                          \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTimerSetTimerIDImpl                       \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory"
             );
         }
 
@@ -1603,11 +1448,8 @@
                 " MPU_xTimerIsTimerActive_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerIsTimerActiveImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory"
             );
         }
 
@@ -1635,11 +1477,8 @@
                 " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetTimerDaemonTaskHandleImpl         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory"
             );
         }
 
@@ -1648,17 +1487,9 @@
 
     #if ( configUSE_TIMERS == 1 )
 
-        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                                     const BaseType_t xCommandID,
-                                                     const TickType_t xOptionalValue,
-                                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                                     const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                                     const BaseType_t xCommandID,
-                                                     const TickType_t xOptionalValue,
-                                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                                     const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
@@ -1675,11 +1506,8 @@
                 " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
                 "     pop {r0}                                                  \n"
                 "     svc %0                                                    \n"
-                "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
-                "     svc %1                                                    \n"
-                "     bx lr                                                     \n"
                 "                                                               \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory"
             );
         }
 
@@ -1707,11 +1535,8 @@
                 " MPU_pcTimerGetName_Unpriv:                            \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pcTimerGetNameImpl                         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory"
             );
         }
 
@@ -1741,11 +1566,8 @@
                 " MPU_vTimerSetReloadMode_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTimerSetReloadModeImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory"
             );
         }
 
@@ -1773,11 +1595,8 @@
                 " MPU_xTimerGetReloadMode_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetReloadModeImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory"
             );
         }
 
@@ -1805,11 +1624,8 @@
                 " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTimerGetReloadModeImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory"
             );
         }
 
@@ -1837,11 +1653,8 @@
                 " MPU_xTimerGetPeriod_Unpriv:                           \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetPeriodImpl                        \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory"
             );
         }
 
@@ -1869,28 +1682,17 @@
                 " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetExpiryTimeImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory"
             );
         }
 
     #endif /* if ( configUSE_TIMERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
-                                         const EventBits_t uxBitsToWaitFor,
-                                         const BaseType_t xClearOnExit,
-                                         const BaseType_t xWaitForAllBits,
-                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
-                                         const EventBits_t uxBitsToWaitFor,
-                                         const BaseType_t xClearOnExit,
-                                         const BaseType_t xWaitForAllBits,
-                                         TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
     {
         __asm volatile
         (
@@ -1907,11 +1709,8 @@
             " MPU_xEventGroupWaitBits_Unpriv:                       \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupWaitBitsImpl                    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1937,11 +1736,8 @@
             " MPU_xEventGroupClearBits_Unpriv:                      \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupClearBitsImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1967,11 +1763,8 @@
             " MPU_xEventGroupSetBits_Unpriv:                        \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupSetBitsImpl                     \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2001,11 +1794,8 @@
             " MPU_xEventGroupSync_Unpriv:                           \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupSyncImpl                        \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2031,11 +1821,8 @@
                 " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxEventGroupGetNumberImpl                  \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory"
             );
         }
 
@@ -2065,11 +1852,8 @@
                 " MPU_vEventGroupSetNumber_Unpriv:                      \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vEventGroupSetNumberImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory"
             );
         }
 
@@ -2101,11 +1885,8 @@
             " MPU_xStreamBufferSend_Unpriv:                         \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferSendImpl                      \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2135,11 +1916,8 @@
             " MPU_xStreamBufferReceive_Unpriv:                      \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferReceiveImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2163,11 +1941,8 @@
             " MPU_xStreamBufferIsFull_Unpriv:                       \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferIsFullImpl                    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2191,11 +1966,8 @@
             " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferIsEmptyImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2219,11 +1991,8 @@
             " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferSpacesAvailableImpl           \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2247,11 +2016,8 @@
             " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferBytesAvailableImpl            \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2277,11 +2043,8 @@
             " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferSetTriggerLevelImpl           \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2305,11 +2068,8 @@
             " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferNextMessageLengthBytesImpl    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c
index ba8f6c62d..16c598ad7 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c
@@ -36,6 +36,9 @@
 /* Portasm includes. */
 #include "portasm.h"
 
+/* System call numbers includes. */
+#include "mpu_syscall_numbers.h"
+
 /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
  * header files. */
 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
@@ -522,7 +525,6 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             ".syntax unified                \n"
             ".extern vPortSVCHandler_C      \n"
             ".extern vSystemCallEnter       \n"
-            ".extern vSystemCallEnter_1     \n"
             ".extern vSystemCallExit        \n"
             "                               \n"
             "tst lr, #4                     \n"
@@ -533,10 +535,8 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "ldr r1, [r0, #24]              \n"
             "ldrb r2, [r1, #-2]             \n"
             "cmp r2, %0                     \n"
-            "beq syscall_enter              \n"
+            "blt syscall_enter              \n"
             "cmp r2, %1                     \n"
-            "beq syscall_enter_1            \n"
-            "cmp r2, %2                     \n"
             "beq syscall_exit               \n"
             "b vPortSVCHandler_C            \n"
             "                               \n"
@@ -544,16 +544,12 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    mov r1, lr                 \n"
             "    b vSystemCallEnter         \n"
             "                               \n"
-            "syscall_enter_1:               \n"
-            "    mov r1, lr                 \n"
-            "    b vSystemCallEnter_1       \n"
-            "                               \n"
             "syscall_exit:                  \n"
             "    mov r1, lr                 \n"
             "    b vSystemCallExit          \n"
             "                               \n"
             : /* No outputs. */
-            : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT )
+            : "i" ( NUM_SYSTEM_CALLS ), "i" ( portSVC_SYSTEM_CALL_EXIT )
             : "r0", "r1", "r2", "memory"
         );
     }
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/mpu_wrappers_v2_asm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/mpu_wrappers_v2_asm.c
index d1fbdc0e5..4cb310afd 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/mpu_wrappers_v2_asm.c
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/mpu_wrappers_v2_asm.c
@@ -38,6 +38,8 @@
 #include "timers.h"
 #include "event_groups.h"
 #include "stream_buffer.h"
+#include "mpu_prototypes.h"
+#include "mpu_syscall_numbers.h"
 
 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
 /*-----------------------------------------------------------*/
@@ -67,11 +69,8 @@
                 " MPU_xTaskDelayUntil_Unpriv:                           \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskDelayUntilImpl                        \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory"
             );
         }
 
@@ -99,11 +98,8 @@
                 " MPU_xTaskAbortDelay_Unpriv:                           \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskAbortDelayImpl                        \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory"
             );
         }
 
@@ -131,11 +127,8 @@
                 " MPU_vTaskDelay_Unpriv:                                \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskDelayImpl                             \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory"
             );
         }
 
@@ -163,11 +156,8 @@
                 " MPU_uxTaskPriorityGet_Unpriv:                         \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskPriorityGetImpl                      \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory"
             );
         }
 
@@ -195,11 +185,8 @@
                 " MPU_eTaskGetState_Unpriv:                             \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_eTaskGetStateImpl                          \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory"
             );
         }
 
@@ -233,11 +220,8 @@
                 " MPU_vTaskGetInfo_Unpriv:                              \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskGetInfoImpl                           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory"
             );
         }
 
@@ -265,11 +249,8 @@
                 " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetIdleTaskHandleImpl                 \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory"
             );
         }
 
@@ -297,11 +278,8 @@
                 " MPU_vTaskSuspend_Unpriv:                              \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskSuspendImpl                           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory"
             );
         }
 
@@ -329,11 +307,8 @@
                 " MPU_vTaskResume_Unpriv:                               \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskResumeImpl                            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskResume ) : "memory"
             );
         }
 
@@ -359,11 +334,8 @@
             " MPU_xTaskGetTickCount_Unpriv:                         \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xTaskGetTickCountImpl                      \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -387,11 +359,8 @@
             " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_uxTaskGetNumberOfTasksImpl                 \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -417,11 +386,8 @@
                 " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetRunTimeCounterImpl                \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory"
             );
         }
 
@@ -449,11 +415,8 @@
                 " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetRunTimePercentImpl                \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory"
             );
         }
 
@@ -481,11 +444,8 @@
                 " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetIdleRunTimePercentImpl            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory"
             );
         }
 
@@ -513,11 +473,8 @@
                 " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetIdleRunTimeCounterImpl            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory"
             );
         }
 
@@ -547,11 +504,8 @@
                 " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskSetApplicationTaskTagImpl             \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory"
             );
         }
 
@@ -579,11 +533,8 @@
                 " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetApplicationTaskTagImpl             \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory"
             );
         }
 
@@ -615,11 +566,8 @@
                 " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskSetThreadLocalStoragePointerImpl      \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory"
             );
         }
 
@@ -649,11 +597,8 @@
                 " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pvTaskGetThreadLocalStoragePointerImpl     \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory"
             );
         }
 
@@ -685,11 +630,8 @@
                 " MPU_uxTaskGetSystemState_Unpriv:                      \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskGetSystemStateImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory"
             );
         }
 
@@ -717,11 +659,8 @@
                 " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskGetStackHighWaterMarkImpl            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory"
             );
         }
 
@@ -749,11 +688,8 @@
                 " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskGetStackHighWaterMark2Impl           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory"
             );
         }
 
@@ -781,11 +717,8 @@
                 " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetCurrentTaskHandleImpl              \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory"
             );
         }
 
@@ -813,11 +746,8 @@
                 " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetSchedulerStateImpl                 \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory"
             );
         }
 
@@ -843,11 +773,8 @@
             " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_vTaskSetTimeOutStateImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -873,28 +800,17 @@
             " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xTaskCheckForTimeOutImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
 
     #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                           UBaseType_t uxIndexToNotify,
-                                           uint32_t ulValue,
-                                           eNotifyAction eAction,
-                                           uint32_t * pulPreviousNotificationValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                           UBaseType_t uxIndexToNotify,
-                                           uint32_t ulValue,
-                                           eNotifyAction eAction,
-                                           uint32_t * pulPreviousNotificationValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
@@ -911,11 +827,8 @@
                 " MPU_xTaskGenericNotify_Unpriv:                        \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGenericNotifyImpl                     \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory"
             );
         }
 
@@ -924,17 +837,9 @@
 
     #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                               uint32_t ulBitsToClearOnEntry,
-                                               uint32_t ulBitsToClearOnExit,
-                                               uint32_t * pulNotificationValue,
-                                               TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                               uint32_t ulBitsToClearOnEntry,
-                                               uint32_t ulBitsToClearOnExit,
-                                               uint32_t * pulNotificationValue,
-                                               TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
@@ -951,11 +856,8 @@
                 " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGenericNotifyWaitImpl                 \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory"
             );
         }
 
@@ -987,11 +889,8 @@
                 " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGenericNotifyTakeImpl                \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory"
             );
         }
 
@@ -1021,11 +920,8 @@
                 " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGenericNotifyStateClearImpl           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory"
             );
         }
 
@@ -1057,11 +953,8 @@
                 " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGenericNotifyValueClearImpl          \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory"
             );
         }
 
@@ -1093,11 +986,8 @@
             " MPU_xQueueGenericSend_Unpriv:                         \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueueGenericSendImpl                      \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1121,11 +1011,8 @@
             " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_uxQueueMessagesWaitingImpl                 \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1149,11 +1036,8 @@
             " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_uxQueueSpacesAvailableImpl                 \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1181,11 +1065,8 @@
             " MPU_xQueueReceive_Unpriv:                             \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueueReceiveImpl                          \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1213,11 +1094,8 @@
             " MPU_xQueuePeek_Unpriv:                                \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueuePeekImpl                             \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1243,11 +1121,8 @@
             " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueueSemaphoreTakeImpl                    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1273,11 +1148,8 @@
                 " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueGetMutexHolderImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory"
             );
         }
 
@@ -1307,11 +1179,8 @@
                 " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueTakeMutexRecursiveImpl               \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory"
             );
         }
 
@@ -1339,11 +1208,8 @@
                 " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueGiveMutexRecursiveImpl               \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory"
             );
         }
 
@@ -1373,11 +1239,8 @@
                 " MPU_xQueueSelectFromSet_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueSelectFromSetImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory"
             );
         }
 
@@ -1407,11 +1270,8 @@
                 " MPU_xQueueAddToSet_Unpriv:                            \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueAddToSetImpl                         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory"
             );
         }
 
@@ -1441,11 +1301,8 @@
                 " MPU_vQueueAddToRegistry_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vQueueAddToRegistryImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory"
             );
         }
 
@@ -1473,11 +1330,8 @@
                 " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vQueueUnregisterQueueImpl                  \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory"
             );
         }
 
@@ -1505,11 +1359,8 @@
                 " MPU_pcQueueGetName_Unpriv:                            \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pcQueueGetNameImpl                         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory"
             );
         }
 
@@ -1537,11 +1388,8 @@
                 " MPU_pvTimerGetTimerID_Unpriv:                         \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pvTimerGetTimerIDImpl                      \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory"
             );
         }
 
@@ -1571,11 +1419,8 @@
                 " MPU_vTimerSetTimerID_Unpriv:                          \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTimerSetTimerIDImpl                       \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory"
             );
         }
 
@@ -1603,11 +1448,8 @@
                 " MPU_xTimerIsTimerActive_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerIsTimerActiveImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory"
             );
         }
 
@@ -1635,11 +1477,8 @@
                 " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetTimerDaemonTaskHandleImpl         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory"
             );
         }
 
@@ -1648,17 +1487,9 @@
 
     #if ( configUSE_TIMERS == 1 )
 
-        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                                     const BaseType_t xCommandID,
-                                                     const TickType_t xOptionalValue,
-                                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                                     const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                                     const BaseType_t xCommandID,
-                                                     const TickType_t xOptionalValue,
-                                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                                     const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
@@ -1675,11 +1506,8 @@
                 " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
                 "     pop {r0}                                                  \n"
                 "     svc %0                                                    \n"
-                "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
-                "     svc %1                                                    \n"
-                "     bx lr                                                     \n"
                 "                                                               \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory"
             );
         }
 
@@ -1707,11 +1535,8 @@
                 " MPU_pcTimerGetName_Unpriv:                            \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pcTimerGetNameImpl                         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory"
             );
         }
 
@@ -1741,11 +1566,8 @@
                 " MPU_vTimerSetReloadMode_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTimerSetReloadModeImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory"
             );
         }
 
@@ -1773,11 +1595,8 @@
                 " MPU_xTimerGetReloadMode_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetReloadModeImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory"
             );
         }
 
@@ -1805,11 +1624,8 @@
                 " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTimerGetReloadModeImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory"
             );
         }
 
@@ -1837,11 +1653,8 @@
                 " MPU_xTimerGetPeriod_Unpriv:                           \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetPeriodImpl                        \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory"
             );
         }
 
@@ -1869,28 +1682,17 @@
                 " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetExpiryTimeImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory"
             );
         }
 
     #endif /* if ( configUSE_TIMERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
-                                         const EventBits_t uxBitsToWaitFor,
-                                         const BaseType_t xClearOnExit,
-                                         const BaseType_t xWaitForAllBits,
-                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
-                                         const EventBits_t uxBitsToWaitFor,
-                                         const BaseType_t xClearOnExit,
-                                         const BaseType_t xWaitForAllBits,
-                                         TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
     {
         __asm volatile
         (
@@ -1907,11 +1709,8 @@
             " MPU_xEventGroupWaitBits_Unpriv:                       \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupWaitBitsImpl                    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1937,11 +1736,8 @@
             " MPU_xEventGroupClearBits_Unpriv:                      \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupClearBitsImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1967,11 +1763,8 @@
             " MPU_xEventGroupSetBits_Unpriv:                        \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupSetBitsImpl                     \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2001,11 +1794,8 @@
             " MPU_xEventGroupSync_Unpriv:                           \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupSyncImpl                        \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2031,11 +1821,8 @@
                 " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxEventGroupGetNumberImpl                  \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory"
             );
         }
 
@@ -2065,11 +1852,8 @@
                 " MPU_vEventGroupSetNumber_Unpriv:                      \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vEventGroupSetNumberImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory"
             );
         }
 
@@ -2101,11 +1885,8 @@
             " MPU_xStreamBufferSend_Unpriv:                         \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferSendImpl                      \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2135,11 +1916,8 @@
             " MPU_xStreamBufferReceive_Unpriv:                      \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferReceiveImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2163,11 +1941,8 @@
             " MPU_xStreamBufferIsFull_Unpriv:                       \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferIsFullImpl                    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2191,11 +1966,8 @@
             " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferIsEmptyImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2219,11 +1991,8 @@
             " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferSpacesAvailableImpl           \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2247,11 +2016,8 @@
             " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferBytesAvailableImpl            \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2277,11 +2043,8 @@
             " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferSetTriggerLevelImpl           \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2305,11 +2068,8 @@
             " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferNextMessageLengthBytesImpl    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c
index e533dd7e9..76ba642a0 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c
@@ -36,6 +36,9 @@
 /* Portasm includes. */
 #include "portasm.h"
 
+/* System call numbers includes. */
+#include "mpu_syscall_numbers.h"
+
 /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
  * header files. */
 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
@@ -443,7 +446,6 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             ".syntax unified                \n"
             ".extern vPortSVCHandler_C      \n"
             ".extern vSystemCallEnter       \n"
-            ".extern vSystemCallEnter_1     \n"
             ".extern vSystemCallExit        \n"
             "                               \n"
             "tst lr, #4                     \n"
@@ -454,10 +456,8 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "ldr r1, [r0, #24]              \n"
             "ldrb r2, [r1, #-2]             \n"
             "cmp r2, %0                     \n"
-            "beq syscall_enter              \n"
+            "blt syscall_enter              \n"
             "cmp r2, %1                     \n"
-            "beq syscall_enter_1            \n"
-            "cmp r2, %2                     \n"
             "beq syscall_exit               \n"
             "b vPortSVCHandler_C            \n"
             "                               \n"
@@ -465,16 +465,12 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    mov r1, lr                 \n"
             "    b vSystemCallEnter         \n"
             "                               \n"
-            "syscall_enter_1:               \n"
-            "    mov r1, lr                 \n"
-            "    b vSystemCallEnter_1       \n"
-            "                               \n"
             "syscall_exit:                  \n"
             "    mov r1, lr                 \n"
             "    b vSystemCallExit          \n"
             "                               \n"
             : /* No outputs. */
-            : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT )
+            : "i" ( NUM_SYSTEM_CALLS ), "i" ( portSVC_SYSTEM_CALL_EXIT )
             : "r0", "r1", "r2", "memory"
         );
     }
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/mpu_wrappers_v2_asm.S b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/mpu_wrappers_v2_asm.S
index 5300a99ec..419df5b1e 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/mpu_wrappers_v2_asm.S
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/mpu_wrappers_v2_asm.S
@@ -32,15 +32,12 @@
 /*-----------------------------------------------------------*/
 
 #include "FreeRTOSConfig.h"
+#include "mpu_syscall_numbers.h"
 
 #ifndef configUSE_MPU_WRAPPERS_V1
     #define configUSE_MPU_WRAPPERS_V1 0
 #endif
 
-/* These must be in sync with portmacro.h. */
-#define portSVC_SYSTEM_CALL_ENTER   4 /* System calls with upto 4 parameters. */
-#define portSVC_SYSTEM_CALL_ENTER_1 5 /* System calls with 5 parameters. */
-#define portSVC_SYSTEM_CALL_EXIT    6
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
@@ -57,10 +54,7 @@ MPU_xTaskDelayUntil:
         b MPU_xTaskDelayUntilImpl
     MPU_xTaskDelayUntil_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskDelayUntilImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskDelayUntil
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskAbortDelay
@@ -75,10 +69,7 @@ MPU_xTaskAbortDelay:
         b MPU_xTaskAbortDelayImpl
     MPU_xTaskAbortDelay_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskAbortDelayImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskAbortDelay
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskDelay
@@ -93,10 +84,7 @@ MPU_vTaskDelay:
         b MPU_vTaskDelayImpl
     MPU_vTaskDelay_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskDelayImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskDelay
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskPriorityGet
@@ -111,10 +99,7 @@ MPU_uxTaskPriorityGet:
         b MPU_uxTaskPriorityGetImpl
     MPU_uxTaskPriorityGet_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskPriorityGetImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskPriorityGet
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_eTaskGetState
@@ -129,10 +114,7 @@ MPU_eTaskGetState:
         b MPU_eTaskGetStateImpl
     MPU_eTaskGetState_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_eTaskGetStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_eTaskGetState
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskGetInfo
@@ -147,10 +129,7 @@ MPU_vTaskGetInfo:
         b MPU_vTaskGetInfoImpl
     MPU_vTaskGetInfo_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskGetInfoImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskGetInfo
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetIdleTaskHandle
@@ -165,10 +144,7 @@ MPU_xTaskGetIdleTaskHandle:
         b MPU_xTaskGetIdleTaskHandleImpl
     MPU_xTaskGetIdleTaskHandle_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetIdleTaskHandleImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetIdleTaskHandle
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskSuspend
@@ -183,10 +159,7 @@ MPU_vTaskSuspend:
         b MPU_vTaskSuspendImpl
     MPU_vTaskSuspend_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSuspendImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskSuspend
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskResume
@@ -201,10 +174,7 @@ MPU_vTaskResume:
         b MPU_vTaskResumeImpl
     MPU_vTaskResume_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskResumeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskResume
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetTickCount
@@ -219,10 +189,7 @@ MPU_xTaskGetTickCount:
         b MPU_xTaskGetTickCountImpl
     MPU_xTaskGetTickCount_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetTickCountImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetTickCount
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskGetNumberOfTasks
@@ -237,10 +204,7 @@ MPU_uxTaskGetNumberOfTasks:
         b MPU_uxTaskGetNumberOfTasksImpl
     MPU_uxTaskGetNumberOfTasks_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetNumberOfTasksImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskGetNumberOfTasks
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGetRunTimeCounter
@@ -255,10 +219,7 @@ MPU_ulTaskGetRunTimeCounter:
         b MPU_ulTaskGetRunTimeCounterImpl
     MPU_ulTaskGetRunTimeCounter_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetRunTimeCounterImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGetRunTimeCounter
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGetRunTimePercent
@@ -273,10 +234,7 @@ MPU_ulTaskGetRunTimePercent:
         b MPU_ulTaskGetRunTimePercentImpl
     MPU_ulTaskGetRunTimePercent_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetRunTimePercentImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGetRunTimePercent
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGetIdleRunTimePercent
@@ -291,10 +249,7 @@ MPU_ulTaskGetIdleRunTimePercent:
         b MPU_ulTaskGetIdleRunTimePercentImpl
     MPU_ulTaskGetIdleRunTimePercent_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetIdleRunTimePercentImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGetIdleRunTimeCounter
@@ -309,10 +264,7 @@ MPU_ulTaskGetIdleRunTimeCounter:
         b MPU_ulTaskGetIdleRunTimeCounterImpl
     MPU_ulTaskGetIdleRunTimeCounter_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetIdleRunTimeCounterImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskSetApplicationTaskTag
@@ -327,10 +279,7 @@ MPU_vTaskSetApplicationTaskTag:
         b MPU_vTaskSetApplicationTaskTagImpl
     MPU_vTaskSetApplicationTaskTag_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSetApplicationTaskTagImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskSetApplicationTaskTag
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetApplicationTaskTag
@@ -345,10 +294,7 @@ MPU_xTaskGetApplicationTaskTag:
         b MPU_xTaskGetApplicationTaskTagImpl
     MPU_xTaskGetApplicationTaskTag_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetApplicationTaskTagImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetApplicationTaskTag
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskSetThreadLocalStoragePointer
@@ -363,10 +309,7 @@ MPU_vTaskSetThreadLocalStoragePointer:
         b MPU_vTaskSetThreadLocalStoragePointerImpl
     MPU_vTaskSetThreadLocalStoragePointer_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSetThreadLocalStoragePointerImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pvTaskGetThreadLocalStoragePointer
@@ -381,10 +324,7 @@ MPU_pvTaskGetThreadLocalStoragePointer:
         b MPU_pvTaskGetThreadLocalStoragePointerImpl
     MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pvTaskGetThreadLocalStoragePointerImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskGetSystemState
@@ -399,10 +339,7 @@ MPU_uxTaskGetSystemState:
         b MPU_uxTaskGetSystemStateImpl
     MPU_uxTaskGetSystemState_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetSystemStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskGetSystemState
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskGetStackHighWaterMark
@@ -417,10 +354,7 @@ MPU_uxTaskGetStackHighWaterMark:
         b MPU_uxTaskGetStackHighWaterMarkImpl
     MPU_uxTaskGetStackHighWaterMark_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetStackHighWaterMarkImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskGetStackHighWaterMark2
@@ -435,10 +369,7 @@ MPU_uxTaskGetStackHighWaterMark2:
         b MPU_uxTaskGetStackHighWaterMark2Impl
     MPU_uxTaskGetStackHighWaterMark2_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetStackHighWaterMark2Impl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetCurrentTaskHandle
@@ -453,10 +384,7 @@ MPU_xTaskGetCurrentTaskHandle:
         b MPU_xTaskGetCurrentTaskHandleImpl
     MPU_xTaskGetCurrentTaskHandle_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetCurrentTaskHandleImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetSchedulerState
@@ -471,10 +399,7 @@ MPU_xTaskGetSchedulerState:
         b MPU_xTaskGetSchedulerStateImpl
     MPU_xTaskGetSchedulerState_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetSchedulerStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetSchedulerState
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskSetTimeOutState
@@ -489,10 +414,7 @@ MPU_vTaskSetTimeOutState:
         b MPU_vTaskSetTimeOutStateImpl
     MPU_vTaskSetTimeOutState_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSetTimeOutStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskSetTimeOutState
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskCheckForTimeOut
@@ -507,14 +429,11 @@ MPU_xTaskCheckForTimeOut:
         b MPU_xTaskCheckForTimeOutImpl
     MPU_xTaskCheckForTimeOut_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskCheckForTimeOutImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskCheckForTimeOut
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xTaskGenericNotify
-MPU_xTaskGenericNotify:
+    PUBLIC MPU_xTaskGenericNotifyEntry
+MPU_xTaskGenericNotifyEntry:
     push {r0, r1}
     mrs r0, control
     movs r1, #1
@@ -525,14 +444,11 @@ MPU_xTaskGenericNotify:
         b MPU_xTaskGenericNotifyImpl
     MPU_xTaskGenericNotify_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTaskGenericNotifyImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGenericNotify
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xTaskGenericNotifyWait
-MPU_xTaskGenericNotifyWait:
+    PUBLIC MPU_xTaskGenericNotifyWaitEntry
+MPU_xTaskGenericNotifyWaitEntry:
     push {r0, r1}
     mrs r0, control
     movs r1, #1
@@ -543,10 +459,7 @@ MPU_xTaskGenericNotifyWait:
         b MPU_xTaskGenericNotifyWaitImpl
     MPU_xTaskGenericNotifyWait_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTaskGenericNotifyWaitImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGenericNotifyWait
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGenericNotifyTake
@@ -561,10 +474,7 @@ MPU_ulTaskGenericNotifyTake:
         b MPU_ulTaskGenericNotifyTakeImpl
     MPU_ulTaskGenericNotifyTake_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGenericNotifyTakeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGenericNotifyTake
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGenericNotifyStateClear
@@ -579,10 +489,7 @@ MPU_xTaskGenericNotifyStateClear:
         b MPU_xTaskGenericNotifyStateClearImpl
     MPU_xTaskGenericNotifyStateClear_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGenericNotifyStateClearImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGenericNotifyStateClear
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGenericNotifyValueClear
@@ -597,10 +504,7 @@ MPU_ulTaskGenericNotifyValueClear:
         b MPU_ulTaskGenericNotifyValueClearImpl
     MPU_ulTaskGenericNotifyValueClear_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGenericNotifyValueClearImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueGenericSend
@@ -615,10 +519,7 @@ MPU_xQueueGenericSend:
         b MPU_xQueueGenericSendImpl
     MPU_xQueueGenericSend_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueGenericSendImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueGenericSend
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxQueueMessagesWaiting
@@ -633,10 +534,7 @@ MPU_uxQueueMessagesWaiting:
         b MPU_uxQueueMessagesWaitingImpl
     MPU_uxQueueMessagesWaiting_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxQueueMessagesWaitingImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxQueueMessagesWaiting
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxQueueSpacesAvailable
@@ -651,10 +549,7 @@ MPU_uxQueueSpacesAvailable:
         b MPU_uxQueueSpacesAvailableImpl
     MPU_uxQueueSpacesAvailable_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxQueueSpacesAvailableImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxQueueSpacesAvailable
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueReceive
@@ -669,10 +564,7 @@ MPU_xQueueReceive:
         b MPU_xQueueReceiveImpl
     MPU_xQueueReceive_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueReceiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueReceive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueuePeek
@@ -687,10 +579,7 @@ MPU_xQueuePeek:
         b MPU_xQueuePeekImpl
     MPU_xQueuePeek_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueuePeekImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueuePeek
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueSemaphoreTake
@@ -705,10 +594,7 @@ MPU_xQueueSemaphoreTake:
         b MPU_xQueueSemaphoreTakeImpl
     MPU_xQueueSemaphoreTake_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueSemaphoreTakeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueSemaphoreTake
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueGetMutexHolder
@@ -723,10 +609,7 @@ MPU_xQueueGetMutexHolder:
         b MPU_xQueueGetMutexHolderImpl
     MPU_xQueueGetMutexHolder_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueGetMutexHolderImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueGetMutexHolder
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueTakeMutexRecursive
@@ -741,10 +624,7 @@ MPU_xQueueTakeMutexRecursive:
         b MPU_xQueueTakeMutexRecursiveImpl
     MPU_xQueueTakeMutexRecursive_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueTakeMutexRecursiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueTakeMutexRecursive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueGiveMutexRecursive
@@ -759,10 +639,7 @@ MPU_xQueueGiveMutexRecursive:
         b MPU_xQueueGiveMutexRecursiveImpl
     MPU_xQueueGiveMutexRecursive_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueGiveMutexRecursiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueGiveMutexRecursive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueSelectFromSet
@@ -777,10 +654,7 @@ MPU_xQueueSelectFromSet:
         b MPU_xQueueSelectFromSetImpl
     MPU_xQueueSelectFromSet_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueSelectFromSetImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueSelectFromSet
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueAddToSet
@@ -795,10 +669,7 @@ MPU_xQueueAddToSet:
         b MPU_xQueueAddToSetImpl
     MPU_xQueueAddToSet_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueAddToSetImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueAddToSet
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vQueueAddToRegistry
@@ -813,10 +684,7 @@ MPU_vQueueAddToRegistry:
         b MPU_vQueueAddToRegistryImpl
     MPU_vQueueAddToRegistry_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vQueueAddToRegistryImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vQueueAddToRegistry
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vQueueUnregisterQueue
@@ -831,10 +699,7 @@ MPU_vQueueUnregisterQueue:
         b MPU_vQueueUnregisterQueueImpl
     MPU_vQueueUnregisterQueue_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vQueueUnregisterQueueImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vQueueUnregisterQueue
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pcQueueGetName
@@ -849,10 +714,7 @@ MPU_pcQueueGetName:
         b MPU_pcQueueGetNameImpl
     MPU_pcQueueGetName_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pcQueueGetNameImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_pcQueueGetName
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pvTimerGetTimerID
@@ -867,10 +729,7 @@ MPU_pvTimerGetTimerID:
         b MPU_pvTimerGetTimerIDImpl
     MPU_pvTimerGetTimerID_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pvTimerGetTimerIDImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_pvTimerGetTimerID
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTimerSetTimerID
@@ -885,10 +744,7 @@ MPU_vTimerSetTimerID:
         b MPU_vTimerSetTimerIDImpl
     MPU_vTimerSetTimerID_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTimerSetTimerIDImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTimerSetTimerID
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerIsTimerActive
@@ -903,10 +759,7 @@ MPU_xTimerIsTimerActive:
         b MPU_xTimerIsTimerActiveImpl
     MPU_xTimerIsTimerActive_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerIsTimerActiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerIsTimerActive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerGetTimerDaemonTaskHandle
@@ -921,14 +774,11 @@ MPU_xTimerGetTimerDaemonTaskHandle:
         b MPU_xTimerGetTimerDaemonTaskHandleImpl
     MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetTimerDaemonTaskHandleImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xTimerGenericCommandFromTask
-MPU_xTimerGenericCommandFromTask:
+    PUBLIC MPU_xTimerGenericCommandFromTaskEntry
+MPU_xTimerGenericCommandFromTaskEntry:
     push {r0, r1}
     mrs r0, control
     movs r1, #1
@@ -939,10 +789,7 @@ MPU_xTimerGenericCommandFromTask:
         b MPU_xTimerGenericCommandFromTaskImpl
     MPU_xTimerGenericCommandFromTask_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTimerGenericCommandFromTaskImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGenericCommandFromTask
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pcTimerGetName
@@ -957,10 +804,7 @@ MPU_pcTimerGetName:
         b MPU_pcTimerGetNameImpl
     MPU_pcTimerGetName_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pcTimerGetNameImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_pcTimerGetName
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTimerSetReloadMode
@@ -975,10 +819,7 @@ MPU_vTimerSetReloadMode:
         b MPU_vTimerSetReloadModeImpl
     MPU_vTimerSetReloadMode_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTimerSetReloadModeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTimerSetReloadMode
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerGetReloadMode
@@ -993,10 +834,7 @@ MPU_xTimerGetReloadMode:
         b MPU_xTimerGetReloadModeImpl
     MPU_xTimerGetReloadMode_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetReloadModeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGetReloadMode
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTimerGetReloadMode
@@ -1011,10 +849,7 @@ MPU_uxTimerGetReloadMode:
         b MPU_uxTimerGetReloadModeImpl
     MPU_uxTimerGetReloadMode_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTimerGetReloadModeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTimerGetReloadMode
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerGetPeriod
@@ -1029,10 +864,7 @@ MPU_xTimerGetPeriod:
         b MPU_xTimerGetPeriodImpl
     MPU_xTimerGetPeriod_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetPeriodImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGetPeriod
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerGetExpiryTime
@@ -1047,14 +879,11 @@ MPU_xTimerGetExpiryTime:
         b MPU_xTimerGetExpiryTimeImpl
     MPU_xTimerGetExpiryTime_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetExpiryTimeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGetExpiryTime
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xEventGroupWaitBits
-MPU_xEventGroupWaitBits:
+    PUBLIC MPU_xEventGroupWaitBitsEntry
+MPU_xEventGroupWaitBitsEntry:
     push {r0, r1}
     mrs r0, control
     movs r1, #1
@@ -1065,10 +894,7 @@ MPU_xEventGroupWaitBits:
         b MPU_xEventGroupWaitBitsImpl
     MPU_xEventGroupWaitBits_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xEventGroupWaitBitsImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xEventGroupWaitBits
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xEventGroupClearBits
@@ -1083,10 +909,7 @@ MPU_xEventGroupClearBits:
         b MPU_xEventGroupClearBitsImpl
     MPU_xEventGroupClearBits_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xEventGroupClearBitsImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xEventGroupClearBits
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xEventGroupSetBits
@@ -1101,10 +924,7 @@ MPU_xEventGroupSetBits:
         b MPU_xEventGroupSetBitsImpl
     MPU_xEventGroupSetBits_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xEventGroupSetBitsImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xEventGroupSetBits
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xEventGroupSync
@@ -1119,10 +939,7 @@ MPU_xEventGroupSync:
         b MPU_xEventGroupSyncImpl
     MPU_xEventGroupSync_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xEventGroupSyncImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xEventGroupSync
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxEventGroupGetNumber
@@ -1137,10 +954,7 @@ MPU_uxEventGroupGetNumber:
         b MPU_uxEventGroupGetNumberImpl
     MPU_uxEventGroupGetNumber_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxEventGroupGetNumberImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxEventGroupGetNumber
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vEventGroupSetNumber
@@ -1155,10 +969,7 @@ MPU_vEventGroupSetNumber:
         b MPU_vEventGroupSetNumberImpl
     MPU_vEventGroupSetNumber_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vEventGroupSetNumberImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vEventGroupSetNumber
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferSend
@@ -1173,10 +984,7 @@ MPU_xStreamBufferSend:
         b MPU_xStreamBufferSendImpl
     MPU_xStreamBufferSend_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferSendImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferSend
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferReceive
@@ -1191,10 +999,7 @@ MPU_xStreamBufferReceive:
         b MPU_xStreamBufferReceiveImpl
     MPU_xStreamBufferReceive_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferReceiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferReceive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferIsFull
@@ -1209,10 +1014,7 @@ MPU_xStreamBufferIsFull:
         b MPU_xStreamBufferIsFullImpl
     MPU_xStreamBufferIsFull_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferIsFullImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferIsFull
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferIsEmpty
@@ -1227,10 +1029,7 @@ MPU_xStreamBufferIsEmpty:
         b MPU_xStreamBufferIsEmptyImpl
     MPU_xStreamBufferIsEmpty_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferIsEmptyImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferIsEmpty
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferSpacesAvailable
@@ -1245,10 +1044,7 @@ MPU_xStreamBufferSpacesAvailable:
         b MPU_xStreamBufferSpacesAvailableImpl
     MPU_xStreamBufferSpacesAvailable_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferSpacesAvailableImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferSpacesAvailable
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferBytesAvailable
@@ -1263,10 +1059,7 @@ MPU_xStreamBufferBytesAvailable:
         b MPU_xStreamBufferBytesAvailableImpl
     MPU_xStreamBufferBytesAvailable_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferBytesAvailableImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferBytesAvailable
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferSetTriggerLevel
@@ -1281,10 +1074,7 @@ MPU_xStreamBufferSetTriggerLevel:
         b MPU_xStreamBufferSetTriggerLevelImpl
     MPU_xStreamBufferSetTriggerLevel_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferSetTriggerLevelImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferNextMessageLengthBytes
@@ -1299,10 +1089,7 @@ MPU_xStreamBufferNextMessageLengthBytes:
         b MPU_xStreamBufferNextMessageLengthBytesImpl
     MPU_xStreamBufferNextMessageLengthBytes_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferNextMessageLengthBytesImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes
 /*-----------------------------------------------------------*/
 
 /* Default weak implementations in case one is not available from
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portasm.s b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portasm.s
index 8c7000909..06c761090 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portasm.s
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portasm.s
@@ -33,6 +33,9 @@ the code is included in C files but excluded by the preprocessor in assembly
 files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
 #include "FreeRTOSConfig.h"
 
+/* System call numbers includes. */
+#include "mpu_syscall_numbers.h"
+
 #ifndef configUSE_MPU_WRAPPERS_V1
     #define configUSE_MPU_WRAPPERS_V1 0
 #endif
@@ -46,7 +49,6 @@ files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler.
     EXTERN SecureContext_LoadContext
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
     EXTERN vSystemCallEnter
-    EXTERN vSystemCallEnter_1
     EXTERN vSystemCallExit
 #endif
 
@@ -96,7 +98,7 @@ vResetPrivilege:
 /*-----------------------------------------------------------*/
 
 vPortAllocateSecureContext:
-    svc 0                                   /* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 0. */
+    svc 100                                 /* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 100. */
     bx lr                                   /* Return. */
 /*-----------------------------------------------------------*/
 
@@ -229,7 +231,7 @@ vStartFirstTask:
     cpsie i                                 /* Globally enable interrupts. */
     dsb
     isb
-    svc 2                                   /* System call to start the first task. portSVC_START_SCHEDULER = 2. */
+    svc 102                                 /* System call to start the first task. portSVC_START_SCHEDULER = 102. */
 /*-----------------------------------------------------------*/
 
 ulSetInterruptMask:
@@ -479,21 +481,17 @@ SVC_Handler:
         b route_svc
 
     route_svc:
-        ldr r2, [r0, #24]
-        subs r2, #2
-        ldrb r3, [r2, #0]
-        cmp r3, #4          /* portSVC_SYSTEM_CALL_ENTER. */
-        beq system_call_enter
-        cmp r3, #5          /* portSVC_SYSTEM_CALL_ENTER_1. */
-        beq system_call_enter_1
-        cmp r3, #6          /* portSVC_SYSTEM_CALL_EXIT. */
+        ldr r3, [r0, #24]
+        subs r3, #2
+        ldrb r2, [r3, #0]
+        cmp r2, #NUM_SYSTEM_CALLS
+        blt system_call_enter
+        cmp r2, #104        /* portSVC_SYSTEM_CALL_EXIT. */
         beq system_call_exit
         b vPortSVCHandler_C
 
     system_call_enter:
         b vSystemCallEnter
-    system_call_enter_1:
-        b vSystemCallEnter_1
     system_call_exit:
         b vSystemCallExit
 
@@ -520,7 +518,7 @@ vPortFreeSecureContext:
     bne free_secure_context                 /* Branch if r1 != 0. */
     bx lr                                   /* There is no secure context (xSecureContext is NULL). */
     free_secure_context:
-        svc 1                               /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */
+        svc 101                             /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 101. */
         bx lr                               /* Return. */
 /*-----------------------------------------------------------*/
 
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/mpu_wrappers_v2_asm.S b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/mpu_wrappers_v2_asm.S
index 5300a99ec..419df5b1e 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/mpu_wrappers_v2_asm.S
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/mpu_wrappers_v2_asm.S
@@ -32,15 +32,12 @@
 /*-----------------------------------------------------------*/
 
 #include "FreeRTOSConfig.h"
+#include "mpu_syscall_numbers.h"
 
 #ifndef configUSE_MPU_WRAPPERS_V1
     #define configUSE_MPU_WRAPPERS_V1 0
 #endif
 
-/* These must be in sync with portmacro.h. */
-#define portSVC_SYSTEM_CALL_ENTER   4 /* System calls with upto 4 parameters. */
-#define portSVC_SYSTEM_CALL_ENTER_1 5 /* System calls with 5 parameters. */
-#define portSVC_SYSTEM_CALL_EXIT    6
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
@@ -57,10 +54,7 @@ MPU_xTaskDelayUntil:
         b MPU_xTaskDelayUntilImpl
     MPU_xTaskDelayUntil_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskDelayUntilImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskDelayUntil
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskAbortDelay
@@ -75,10 +69,7 @@ MPU_xTaskAbortDelay:
         b MPU_xTaskAbortDelayImpl
     MPU_xTaskAbortDelay_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskAbortDelayImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskAbortDelay
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskDelay
@@ -93,10 +84,7 @@ MPU_vTaskDelay:
         b MPU_vTaskDelayImpl
     MPU_vTaskDelay_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskDelayImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskDelay
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskPriorityGet
@@ -111,10 +99,7 @@ MPU_uxTaskPriorityGet:
         b MPU_uxTaskPriorityGetImpl
     MPU_uxTaskPriorityGet_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskPriorityGetImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskPriorityGet
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_eTaskGetState
@@ -129,10 +114,7 @@ MPU_eTaskGetState:
         b MPU_eTaskGetStateImpl
     MPU_eTaskGetState_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_eTaskGetStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_eTaskGetState
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskGetInfo
@@ -147,10 +129,7 @@ MPU_vTaskGetInfo:
         b MPU_vTaskGetInfoImpl
     MPU_vTaskGetInfo_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskGetInfoImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskGetInfo
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetIdleTaskHandle
@@ -165,10 +144,7 @@ MPU_xTaskGetIdleTaskHandle:
         b MPU_xTaskGetIdleTaskHandleImpl
     MPU_xTaskGetIdleTaskHandle_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetIdleTaskHandleImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetIdleTaskHandle
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskSuspend
@@ -183,10 +159,7 @@ MPU_vTaskSuspend:
         b MPU_vTaskSuspendImpl
     MPU_vTaskSuspend_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSuspendImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskSuspend
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskResume
@@ -201,10 +174,7 @@ MPU_vTaskResume:
         b MPU_vTaskResumeImpl
     MPU_vTaskResume_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskResumeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskResume
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetTickCount
@@ -219,10 +189,7 @@ MPU_xTaskGetTickCount:
         b MPU_xTaskGetTickCountImpl
     MPU_xTaskGetTickCount_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetTickCountImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetTickCount
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskGetNumberOfTasks
@@ -237,10 +204,7 @@ MPU_uxTaskGetNumberOfTasks:
         b MPU_uxTaskGetNumberOfTasksImpl
     MPU_uxTaskGetNumberOfTasks_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetNumberOfTasksImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskGetNumberOfTasks
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGetRunTimeCounter
@@ -255,10 +219,7 @@ MPU_ulTaskGetRunTimeCounter:
         b MPU_ulTaskGetRunTimeCounterImpl
     MPU_ulTaskGetRunTimeCounter_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetRunTimeCounterImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGetRunTimeCounter
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGetRunTimePercent
@@ -273,10 +234,7 @@ MPU_ulTaskGetRunTimePercent:
         b MPU_ulTaskGetRunTimePercentImpl
     MPU_ulTaskGetRunTimePercent_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetRunTimePercentImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGetRunTimePercent
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGetIdleRunTimePercent
@@ -291,10 +249,7 @@ MPU_ulTaskGetIdleRunTimePercent:
         b MPU_ulTaskGetIdleRunTimePercentImpl
     MPU_ulTaskGetIdleRunTimePercent_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetIdleRunTimePercentImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGetIdleRunTimeCounter
@@ -309,10 +264,7 @@ MPU_ulTaskGetIdleRunTimeCounter:
         b MPU_ulTaskGetIdleRunTimeCounterImpl
     MPU_ulTaskGetIdleRunTimeCounter_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetIdleRunTimeCounterImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskSetApplicationTaskTag
@@ -327,10 +279,7 @@ MPU_vTaskSetApplicationTaskTag:
         b MPU_vTaskSetApplicationTaskTagImpl
     MPU_vTaskSetApplicationTaskTag_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSetApplicationTaskTagImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskSetApplicationTaskTag
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetApplicationTaskTag
@@ -345,10 +294,7 @@ MPU_xTaskGetApplicationTaskTag:
         b MPU_xTaskGetApplicationTaskTagImpl
     MPU_xTaskGetApplicationTaskTag_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetApplicationTaskTagImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetApplicationTaskTag
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskSetThreadLocalStoragePointer
@@ -363,10 +309,7 @@ MPU_vTaskSetThreadLocalStoragePointer:
         b MPU_vTaskSetThreadLocalStoragePointerImpl
     MPU_vTaskSetThreadLocalStoragePointer_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSetThreadLocalStoragePointerImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pvTaskGetThreadLocalStoragePointer
@@ -381,10 +324,7 @@ MPU_pvTaskGetThreadLocalStoragePointer:
         b MPU_pvTaskGetThreadLocalStoragePointerImpl
     MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pvTaskGetThreadLocalStoragePointerImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskGetSystemState
@@ -399,10 +339,7 @@ MPU_uxTaskGetSystemState:
         b MPU_uxTaskGetSystemStateImpl
     MPU_uxTaskGetSystemState_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetSystemStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskGetSystemState
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskGetStackHighWaterMark
@@ -417,10 +354,7 @@ MPU_uxTaskGetStackHighWaterMark:
         b MPU_uxTaskGetStackHighWaterMarkImpl
     MPU_uxTaskGetStackHighWaterMark_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetStackHighWaterMarkImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskGetStackHighWaterMark2
@@ -435,10 +369,7 @@ MPU_uxTaskGetStackHighWaterMark2:
         b MPU_uxTaskGetStackHighWaterMark2Impl
     MPU_uxTaskGetStackHighWaterMark2_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetStackHighWaterMark2Impl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetCurrentTaskHandle
@@ -453,10 +384,7 @@ MPU_xTaskGetCurrentTaskHandle:
         b MPU_xTaskGetCurrentTaskHandleImpl
     MPU_xTaskGetCurrentTaskHandle_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetCurrentTaskHandleImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetSchedulerState
@@ -471,10 +399,7 @@ MPU_xTaskGetSchedulerState:
         b MPU_xTaskGetSchedulerStateImpl
     MPU_xTaskGetSchedulerState_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetSchedulerStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetSchedulerState
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskSetTimeOutState
@@ -489,10 +414,7 @@ MPU_vTaskSetTimeOutState:
         b MPU_vTaskSetTimeOutStateImpl
     MPU_vTaskSetTimeOutState_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSetTimeOutStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskSetTimeOutState
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskCheckForTimeOut
@@ -507,14 +429,11 @@ MPU_xTaskCheckForTimeOut:
         b MPU_xTaskCheckForTimeOutImpl
     MPU_xTaskCheckForTimeOut_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskCheckForTimeOutImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskCheckForTimeOut
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xTaskGenericNotify
-MPU_xTaskGenericNotify:
+    PUBLIC MPU_xTaskGenericNotifyEntry
+MPU_xTaskGenericNotifyEntry:
     push {r0, r1}
     mrs r0, control
     movs r1, #1
@@ -525,14 +444,11 @@ MPU_xTaskGenericNotify:
         b MPU_xTaskGenericNotifyImpl
     MPU_xTaskGenericNotify_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTaskGenericNotifyImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGenericNotify
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xTaskGenericNotifyWait
-MPU_xTaskGenericNotifyWait:
+    PUBLIC MPU_xTaskGenericNotifyWaitEntry
+MPU_xTaskGenericNotifyWaitEntry:
     push {r0, r1}
     mrs r0, control
     movs r1, #1
@@ -543,10 +459,7 @@ MPU_xTaskGenericNotifyWait:
         b MPU_xTaskGenericNotifyWaitImpl
     MPU_xTaskGenericNotifyWait_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTaskGenericNotifyWaitImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGenericNotifyWait
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGenericNotifyTake
@@ -561,10 +474,7 @@ MPU_ulTaskGenericNotifyTake:
         b MPU_ulTaskGenericNotifyTakeImpl
     MPU_ulTaskGenericNotifyTake_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGenericNotifyTakeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGenericNotifyTake
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGenericNotifyStateClear
@@ -579,10 +489,7 @@ MPU_xTaskGenericNotifyStateClear:
         b MPU_xTaskGenericNotifyStateClearImpl
     MPU_xTaskGenericNotifyStateClear_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGenericNotifyStateClearImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGenericNotifyStateClear
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGenericNotifyValueClear
@@ -597,10 +504,7 @@ MPU_ulTaskGenericNotifyValueClear:
         b MPU_ulTaskGenericNotifyValueClearImpl
     MPU_ulTaskGenericNotifyValueClear_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGenericNotifyValueClearImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueGenericSend
@@ -615,10 +519,7 @@ MPU_xQueueGenericSend:
         b MPU_xQueueGenericSendImpl
     MPU_xQueueGenericSend_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueGenericSendImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueGenericSend
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxQueueMessagesWaiting
@@ -633,10 +534,7 @@ MPU_uxQueueMessagesWaiting:
         b MPU_uxQueueMessagesWaitingImpl
     MPU_uxQueueMessagesWaiting_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxQueueMessagesWaitingImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxQueueMessagesWaiting
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxQueueSpacesAvailable
@@ -651,10 +549,7 @@ MPU_uxQueueSpacesAvailable:
         b MPU_uxQueueSpacesAvailableImpl
     MPU_uxQueueSpacesAvailable_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxQueueSpacesAvailableImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxQueueSpacesAvailable
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueReceive
@@ -669,10 +564,7 @@ MPU_xQueueReceive:
         b MPU_xQueueReceiveImpl
     MPU_xQueueReceive_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueReceiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueReceive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueuePeek
@@ -687,10 +579,7 @@ MPU_xQueuePeek:
         b MPU_xQueuePeekImpl
     MPU_xQueuePeek_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueuePeekImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueuePeek
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueSemaphoreTake
@@ -705,10 +594,7 @@ MPU_xQueueSemaphoreTake:
         b MPU_xQueueSemaphoreTakeImpl
     MPU_xQueueSemaphoreTake_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueSemaphoreTakeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueSemaphoreTake
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueGetMutexHolder
@@ -723,10 +609,7 @@ MPU_xQueueGetMutexHolder:
         b MPU_xQueueGetMutexHolderImpl
     MPU_xQueueGetMutexHolder_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueGetMutexHolderImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueGetMutexHolder
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueTakeMutexRecursive
@@ -741,10 +624,7 @@ MPU_xQueueTakeMutexRecursive:
         b MPU_xQueueTakeMutexRecursiveImpl
     MPU_xQueueTakeMutexRecursive_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueTakeMutexRecursiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueTakeMutexRecursive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueGiveMutexRecursive
@@ -759,10 +639,7 @@ MPU_xQueueGiveMutexRecursive:
         b MPU_xQueueGiveMutexRecursiveImpl
     MPU_xQueueGiveMutexRecursive_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueGiveMutexRecursiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueGiveMutexRecursive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueSelectFromSet
@@ -777,10 +654,7 @@ MPU_xQueueSelectFromSet:
         b MPU_xQueueSelectFromSetImpl
     MPU_xQueueSelectFromSet_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueSelectFromSetImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueSelectFromSet
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueAddToSet
@@ -795,10 +669,7 @@ MPU_xQueueAddToSet:
         b MPU_xQueueAddToSetImpl
     MPU_xQueueAddToSet_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueAddToSetImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueAddToSet
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vQueueAddToRegistry
@@ -813,10 +684,7 @@ MPU_vQueueAddToRegistry:
         b MPU_vQueueAddToRegistryImpl
     MPU_vQueueAddToRegistry_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vQueueAddToRegistryImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vQueueAddToRegistry
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vQueueUnregisterQueue
@@ -831,10 +699,7 @@ MPU_vQueueUnregisterQueue:
         b MPU_vQueueUnregisterQueueImpl
     MPU_vQueueUnregisterQueue_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vQueueUnregisterQueueImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vQueueUnregisterQueue
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pcQueueGetName
@@ -849,10 +714,7 @@ MPU_pcQueueGetName:
         b MPU_pcQueueGetNameImpl
     MPU_pcQueueGetName_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pcQueueGetNameImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_pcQueueGetName
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pvTimerGetTimerID
@@ -867,10 +729,7 @@ MPU_pvTimerGetTimerID:
         b MPU_pvTimerGetTimerIDImpl
     MPU_pvTimerGetTimerID_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pvTimerGetTimerIDImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_pvTimerGetTimerID
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTimerSetTimerID
@@ -885,10 +744,7 @@ MPU_vTimerSetTimerID:
         b MPU_vTimerSetTimerIDImpl
     MPU_vTimerSetTimerID_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTimerSetTimerIDImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTimerSetTimerID
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerIsTimerActive
@@ -903,10 +759,7 @@ MPU_xTimerIsTimerActive:
         b MPU_xTimerIsTimerActiveImpl
     MPU_xTimerIsTimerActive_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerIsTimerActiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerIsTimerActive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerGetTimerDaemonTaskHandle
@@ -921,14 +774,11 @@ MPU_xTimerGetTimerDaemonTaskHandle:
         b MPU_xTimerGetTimerDaemonTaskHandleImpl
     MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetTimerDaemonTaskHandleImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xTimerGenericCommandFromTask
-MPU_xTimerGenericCommandFromTask:
+    PUBLIC MPU_xTimerGenericCommandFromTaskEntry
+MPU_xTimerGenericCommandFromTaskEntry:
     push {r0, r1}
     mrs r0, control
     movs r1, #1
@@ -939,10 +789,7 @@ MPU_xTimerGenericCommandFromTask:
         b MPU_xTimerGenericCommandFromTaskImpl
     MPU_xTimerGenericCommandFromTask_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTimerGenericCommandFromTaskImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGenericCommandFromTask
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pcTimerGetName
@@ -957,10 +804,7 @@ MPU_pcTimerGetName:
         b MPU_pcTimerGetNameImpl
     MPU_pcTimerGetName_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pcTimerGetNameImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_pcTimerGetName
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTimerSetReloadMode
@@ -975,10 +819,7 @@ MPU_vTimerSetReloadMode:
         b MPU_vTimerSetReloadModeImpl
     MPU_vTimerSetReloadMode_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTimerSetReloadModeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTimerSetReloadMode
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerGetReloadMode
@@ -993,10 +834,7 @@ MPU_xTimerGetReloadMode:
         b MPU_xTimerGetReloadModeImpl
     MPU_xTimerGetReloadMode_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetReloadModeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGetReloadMode
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTimerGetReloadMode
@@ -1011,10 +849,7 @@ MPU_uxTimerGetReloadMode:
         b MPU_uxTimerGetReloadModeImpl
     MPU_uxTimerGetReloadMode_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTimerGetReloadModeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTimerGetReloadMode
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerGetPeriod
@@ -1029,10 +864,7 @@ MPU_xTimerGetPeriod:
         b MPU_xTimerGetPeriodImpl
     MPU_xTimerGetPeriod_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetPeriodImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGetPeriod
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerGetExpiryTime
@@ -1047,14 +879,11 @@ MPU_xTimerGetExpiryTime:
         b MPU_xTimerGetExpiryTimeImpl
     MPU_xTimerGetExpiryTime_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetExpiryTimeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGetExpiryTime
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xEventGroupWaitBits
-MPU_xEventGroupWaitBits:
+    PUBLIC MPU_xEventGroupWaitBitsEntry
+MPU_xEventGroupWaitBitsEntry:
     push {r0, r1}
     mrs r0, control
     movs r1, #1
@@ -1065,10 +894,7 @@ MPU_xEventGroupWaitBits:
         b MPU_xEventGroupWaitBitsImpl
     MPU_xEventGroupWaitBits_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xEventGroupWaitBitsImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xEventGroupWaitBits
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xEventGroupClearBits
@@ -1083,10 +909,7 @@ MPU_xEventGroupClearBits:
         b MPU_xEventGroupClearBitsImpl
     MPU_xEventGroupClearBits_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xEventGroupClearBitsImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xEventGroupClearBits
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xEventGroupSetBits
@@ -1101,10 +924,7 @@ MPU_xEventGroupSetBits:
         b MPU_xEventGroupSetBitsImpl
     MPU_xEventGroupSetBits_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xEventGroupSetBitsImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xEventGroupSetBits
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xEventGroupSync
@@ -1119,10 +939,7 @@ MPU_xEventGroupSync:
         b MPU_xEventGroupSyncImpl
     MPU_xEventGroupSync_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xEventGroupSyncImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xEventGroupSync
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxEventGroupGetNumber
@@ -1137,10 +954,7 @@ MPU_uxEventGroupGetNumber:
         b MPU_uxEventGroupGetNumberImpl
     MPU_uxEventGroupGetNumber_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxEventGroupGetNumberImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxEventGroupGetNumber
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vEventGroupSetNumber
@@ -1155,10 +969,7 @@ MPU_vEventGroupSetNumber:
         b MPU_vEventGroupSetNumberImpl
     MPU_vEventGroupSetNumber_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vEventGroupSetNumberImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vEventGroupSetNumber
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferSend
@@ -1173,10 +984,7 @@ MPU_xStreamBufferSend:
         b MPU_xStreamBufferSendImpl
     MPU_xStreamBufferSend_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferSendImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferSend
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferReceive
@@ -1191,10 +999,7 @@ MPU_xStreamBufferReceive:
         b MPU_xStreamBufferReceiveImpl
     MPU_xStreamBufferReceive_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferReceiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferReceive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferIsFull
@@ -1209,10 +1014,7 @@ MPU_xStreamBufferIsFull:
         b MPU_xStreamBufferIsFullImpl
     MPU_xStreamBufferIsFull_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferIsFullImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferIsFull
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferIsEmpty
@@ -1227,10 +1029,7 @@ MPU_xStreamBufferIsEmpty:
         b MPU_xStreamBufferIsEmptyImpl
     MPU_xStreamBufferIsEmpty_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferIsEmptyImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferIsEmpty
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferSpacesAvailable
@@ -1245,10 +1044,7 @@ MPU_xStreamBufferSpacesAvailable:
         b MPU_xStreamBufferSpacesAvailableImpl
     MPU_xStreamBufferSpacesAvailable_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferSpacesAvailableImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferSpacesAvailable
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferBytesAvailable
@@ -1263,10 +1059,7 @@ MPU_xStreamBufferBytesAvailable:
         b MPU_xStreamBufferBytesAvailableImpl
     MPU_xStreamBufferBytesAvailable_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferBytesAvailableImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferBytesAvailable
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferSetTriggerLevel
@@ -1281,10 +1074,7 @@ MPU_xStreamBufferSetTriggerLevel:
         b MPU_xStreamBufferSetTriggerLevelImpl
     MPU_xStreamBufferSetTriggerLevel_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferSetTriggerLevelImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferNextMessageLengthBytes
@@ -1299,10 +1089,7 @@ MPU_xStreamBufferNextMessageLengthBytes:
         b MPU_xStreamBufferNextMessageLengthBytesImpl
     MPU_xStreamBufferNextMessageLengthBytes_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferNextMessageLengthBytesImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes
 /*-----------------------------------------------------------*/
 
 /* Default weak implementations in case one is not available from
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portasm.s b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portasm.s
index 836a927c8..d4487dfac 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portasm.s
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portasm.s
@@ -32,6 +32,9 @@ the code is included in C files but excluded by the preprocessor in assembly
 files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
 #include "FreeRTOSConfig.h"
 
+/* System call numbers includes. */
+#include "mpu_syscall_numbers.h"
+
 #ifndef configUSE_MPU_WRAPPERS_V1
     #define configUSE_MPU_WRAPPERS_V1 0
 #endif
@@ -45,7 +48,6 @@ files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler.
     EXTERN vPortSVCHandler_C
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
     EXTERN vSystemCallEnter
-    EXTERN vSystemCallEnter_1
     EXTERN vSystemCallExit
 #endif
 
@@ -224,7 +226,7 @@ vStartFirstTask:
     cpsie i                                 /* Globally enable interrupts. */
     dsb
     isb
-    svc 2                                   /* System call to start the first task. portSVC_START_SCHEDULER = 2. */
+    svc 102                                 /* System call to start the first task. portSVC_START_SCHEDULER = 102. */
     nop
 /*-----------------------------------------------------------*/
 
@@ -421,21 +423,17 @@ SVC_Handler:
         b route_svc
 
     route_svc:
-        ldr r2, [r0, #24]
-        subs r2, #2
-        ldrb r3, [r2, #0]
-        cmp r3, #4          /* portSVC_SYSTEM_CALL_ENTER. */
-        beq system_call_enter
-        cmp r3, #5          /* portSVC_SYSTEM_CALL_ENTER_1. */
-        beq system_call_enter_1
-        cmp r3, #6          /* portSVC_SYSTEM_CALL_EXIT. */
+        ldr r3, [r0, #24]
+        subs r3, #2
+        ldrb r2, [r3, #0]
+        cmp r2, #NUM_SYSTEM_CALLS
+        blt system_call_enter
+        cmp r2, #104        /* portSVC_SYSTEM_CALL_EXIT. */
         beq system_call_exit
         b vPortSVCHandler_C
 
     system_call_enter:
         b vSystemCallEnter
-    system_call_enter_1:
-        b vSystemCallEnter_1
     system_call_exit:
         b vSystemCallExit
 
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/mpu_wrappers_v2_asm.S b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/mpu_wrappers_v2_asm.S
index 1005dad33..80d5a1c63 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/mpu_wrappers_v2_asm.S
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/mpu_wrappers_v2_asm.S
@@ -32,15 +32,12 @@
 /*-----------------------------------------------------------*/
 
 #include "FreeRTOSConfig.h"
+#include "mpu_syscall_numbers.h"
 
 #ifndef configUSE_MPU_WRAPPERS_V1
     #define configUSE_MPU_WRAPPERS_V1 0
 #endif
 
-/* These must be in sync with portmacro.h. */
-#define portSVC_SYSTEM_CALL_ENTER   4 /* System calls with upto 4 parameters. */
-#define portSVC_SYSTEM_CALL_ENTER_1 5 /* System calls with 5 parameters. */
-#define portSVC_SYSTEM_CALL_EXIT    6
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
@@ -56,10 +53,7 @@ MPU_xTaskDelayUntil:
         b MPU_xTaskDelayUntilImpl
     MPU_xTaskDelayUntil_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskDelayUntilImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskDelayUntil
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskAbortDelay
@@ -73,10 +67,7 @@ MPU_xTaskAbortDelay:
         b MPU_xTaskAbortDelayImpl
     MPU_xTaskAbortDelay_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskAbortDelayImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskAbortDelay
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskDelay
@@ -90,10 +81,7 @@ MPU_vTaskDelay:
         b MPU_vTaskDelayImpl
     MPU_vTaskDelay_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskDelayImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskDelay
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskPriorityGet
@@ -107,10 +95,7 @@ MPU_uxTaskPriorityGet:
         b MPU_uxTaskPriorityGetImpl
     MPU_uxTaskPriorityGet_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskPriorityGetImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskPriorityGet
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_eTaskGetState
@@ -124,10 +109,7 @@ MPU_eTaskGetState:
         b MPU_eTaskGetStateImpl
     MPU_eTaskGetState_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_eTaskGetStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_eTaskGetState
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskGetInfo
@@ -141,10 +123,7 @@ MPU_vTaskGetInfo:
         b MPU_vTaskGetInfoImpl
     MPU_vTaskGetInfo_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskGetInfoImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskGetInfo
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetIdleTaskHandle
@@ -158,10 +137,7 @@ MPU_xTaskGetIdleTaskHandle:
         b MPU_xTaskGetIdleTaskHandleImpl
     MPU_xTaskGetIdleTaskHandle_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetIdleTaskHandleImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetIdleTaskHandle
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskSuspend
@@ -175,10 +151,7 @@ MPU_vTaskSuspend:
         b MPU_vTaskSuspendImpl
     MPU_vTaskSuspend_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSuspendImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskSuspend
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskResume
@@ -192,10 +165,7 @@ MPU_vTaskResume:
         b MPU_vTaskResumeImpl
     MPU_vTaskResume_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskResumeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskResume
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetTickCount
@@ -209,10 +179,7 @@ MPU_xTaskGetTickCount:
         b MPU_xTaskGetTickCountImpl
     MPU_xTaskGetTickCount_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetTickCountImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetTickCount
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskGetNumberOfTasks
@@ -226,10 +193,7 @@ MPU_uxTaskGetNumberOfTasks:
         b MPU_uxTaskGetNumberOfTasksImpl
     MPU_uxTaskGetNumberOfTasks_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetNumberOfTasksImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskGetNumberOfTasks
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGetRunTimeCounter
@@ -243,10 +207,7 @@ MPU_ulTaskGetRunTimeCounter:
         b MPU_ulTaskGetRunTimeCounterImpl
     MPU_ulTaskGetRunTimeCounter_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetRunTimeCounterImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGetRunTimeCounter
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGetRunTimePercent
@@ -260,10 +221,7 @@ MPU_ulTaskGetRunTimePercent:
         b MPU_ulTaskGetRunTimePercentImpl
     MPU_ulTaskGetRunTimePercent_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetRunTimePercentImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGetRunTimePercent
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGetIdleRunTimePercent
@@ -277,10 +235,7 @@ MPU_ulTaskGetIdleRunTimePercent:
         b MPU_ulTaskGetIdleRunTimePercentImpl
     MPU_ulTaskGetIdleRunTimePercent_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetIdleRunTimePercentImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGetIdleRunTimeCounter
@@ -294,10 +249,7 @@ MPU_ulTaskGetIdleRunTimeCounter:
         b MPU_ulTaskGetIdleRunTimeCounterImpl
     MPU_ulTaskGetIdleRunTimeCounter_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetIdleRunTimeCounterImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskSetApplicationTaskTag
@@ -311,10 +263,7 @@ MPU_vTaskSetApplicationTaskTag:
         b MPU_vTaskSetApplicationTaskTagImpl
     MPU_vTaskSetApplicationTaskTag_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSetApplicationTaskTagImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskSetApplicationTaskTag
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetApplicationTaskTag
@@ -328,10 +277,7 @@ MPU_xTaskGetApplicationTaskTag:
         b MPU_xTaskGetApplicationTaskTagImpl
     MPU_xTaskGetApplicationTaskTag_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetApplicationTaskTagImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetApplicationTaskTag
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskSetThreadLocalStoragePointer
@@ -345,10 +291,7 @@ MPU_vTaskSetThreadLocalStoragePointer:
         b MPU_vTaskSetThreadLocalStoragePointerImpl
     MPU_vTaskSetThreadLocalStoragePointer_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSetThreadLocalStoragePointerImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pvTaskGetThreadLocalStoragePointer
@@ -362,10 +305,7 @@ MPU_pvTaskGetThreadLocalStoragePointer:
         b MPU_pvTaskGetThreadLocalStoragePointerImpl
     MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pvTaskGetThreadLocalStoragePointerImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskGetSystemState
@@ -379,10 +319,7 @@ MPU_uxTaskGetSystemState:
         b MPU_uxTaskGetSystemStateImpl
     MPU_uxTaskGetSystemState_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetSystemStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskGetSystemState
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskGetStackHighWaterMark
@@ -396,10 +333,7 @@ MPU_uxTaskGetStackHighWaterMark:
         b MPU_uxTaskGetStackHighWaterMarkImpl
     MPU_uxTaskGetStackHighWaterMark_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetStackHighWaterMarkImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskGetStackHighWaterMark2
@@ -413,10 +347,7 @@ MPU_uxTaskGetStackHighWaterMark2:
         b MPU_uxTaskGetStackHighWaterMark2Impl
     MPU_uxTaskGetStackHighWaterMark2_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetStackHighWaterMark2Impl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetCurrentTaskHandle
@@ -430,10 +361,7 @@ MPU_xTaskGetCurrentTaskHandle:
         b MPU_xTaskGetCurrentTaskHandleImpl
     MPU_xTaskGetCurrentTaskHandle_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetCurrentTaskHandleImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetSchedulerState
@@ -447,10 +375,7 @@ MPU_xTaskGetSchedulerState:
         b MPU_xTaskGetSchedulerStateImpl
     MPU_xTaskGetSchedulerState_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetSchedulerStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetSchedulerState
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskSetTimeOutState
@@ -464,10 +389,7 @@ MPU_vTaskSetTimeOutState:
         b MPU_vTaskSetTimeOutStateImpl
     MPU_vTaskSetTimeOutState_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSetTimeOutStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskSetTimeOutState
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskCheckForTimeOut
@@ -481,14 +403,11 @@ MPU_xTaskCheckForTimeOut:
         b MPU_xTaskCheckForTimeOutImpl
     MPU_xTaskCheckForTimeOut_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskCheckForTimeOutImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskCheckForTimeOut
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xTaskGenericNotify
-MPU_xTaskGenericNotify:
+    PUBLIC MPU_xTaskGenericNotifyEntry
+MPU_xTaskGenericNotifyEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
@@ -498,14 +417,11 @@ MPU_xTaskGenericNotify:
         b MPU_xTaskGenericNotifyImpl
     MPU_xTaskGenericNotify_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTaskGenericNotifyImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGenericNotify
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xTaskGenericNotifyWait
-MPU_xTaskGenericNotifyWait:
+    PUBLIC MPU_xTaskGenericNotifyWaitEntry
+MPU_xTaskGenericNotifyWaitEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
@@ -515,10 +431,7 @@ MPU_xTaskGenericNotifyWait:
         b MPU_xTaskGenericNotifyWaitImpl
     MPU_xTaskGenericNotifyWait_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTaskGenericNotifyWaitImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGenericNotifyWait
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGenericNotifyTake
@@ -532,10 +445,7 @@ MPU_ulTaskGenericNotifyTake:
         b MPU_ulTaskGenericNotifyTakeImpl
     MPU_ulTaskGenericNotifyTake_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGenericNotifyTakeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGenericNotifyTake
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGenericNotifyStateClear
@@ -549,10 +459,7 @@ MPU_xTaskGenericNotifyStateClear:
         b MPU_xTaskGenericNotifyStateClearImpl
     MPU_xTaskGenericNotifyStateClear_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGenericNotifyStateClearImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGenericNotifyStateClear
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGenericNotifyValueClear
@@ -566,10 +473,7 @@ MPU_ulTaskGenericNotifyValueClear:
         b MPU_ulTaskGenericNotifyValueClearImpl
     MPU_ulTaskGenericNotifyValueClear_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGenericNotifyValueClearImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueGenericSend
@@ -583,10 +487,7 @@ MPU_xQueueGenericSend:
         b MPU_xQueueGenericSendImpl
     MPU_xQueueGenericSend_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueGenericSendImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueGenericSend
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxQueueMessagesWaiting
@@ -600,10 +501,7 @@ MPU_uxQueueMessagesWaiting:
         b MPU_uxQueueMessagesWaitingImpl
     MPU_uxQueueMessagesWaiting_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxQueueMessagesWaitingImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxQueueMessagesWaiting
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxQueueSpacesAvailable
@@ -617,10 +515,7 @@ MPU_uxQueueSpacesAvailable:
         b MPU_uxQueueSpacesAvailableImpl
     MPU_uxQueueSpacesAvailable_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxQueueSpacesAvailableImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxQueueSpacesAvailable
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueReceive
@@ -634,10 +529,7 @@ MPU_xQueueReceive:
         b MPU_xQueueReceiveImpl
     MPU_xQueueReceive_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueReceiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueReceive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueuePeek
@@ -651,10 +543,7 @@ MPU_xQueuePeek:
         b MPU_xQueuePeekImpl
     MPU_xQueuePeek_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueuePeekImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueuePeek
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueSemaphoreTake
@@ -668,10 +557,7 @@ MPU_xQueueSemaphoreTake:
         b MPU_xQueueSemaphoreTakeImpl
     MPU_xQueueSemaphoreTake_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueSemaphoreTakeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueSemaphoreTake
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueGetMutexHolder
@@ -685,10 +571,7 @@ MPU_xQueueGetMutexHolder:
         b MPU_xQueueGetMutexHolderImpl
     MPU_xQueueGetMutexHolder_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueGetMutexHolderImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueGetMutexHolder
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueTakeMutexRecursive
@@ -702,10 +585,7 @@ MPU_xQueueTakeMutexRecursive:
         b MPU_xQueueTakeMutexRecursiveImpl
     MPU_xQueueTakeMutexRecursive_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueTakeMutexRecursiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueTakeMutexRecursive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueGiveMutexRecursive
@@ -719,10 +599,7 @@ MPU_xQueueGiveMutexRecursive:
         b MPU_xQueueGiveMutexRecursiveImpl
     MPU_xQueueGiveMutexRecursive_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueGiveMutexRecursiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueGiveMutexRecursive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueSelectFromSet
@@ -736,10 +613,7 @@ MPU_xQueueSelectFromSet:
         b MPU_xQueueSelectFromSetImpl
     MPU_xQueueSelectFromSet_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueSelectFromSetImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueSelectFromSet
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueAddToSet
@@ -753,10 +627,7 @@ MPU_xQueueAddToSet:
         b MPU_xQueueAddToSetImpl
     MPU_xQueueAddToSet_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueAddToSetImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueAddToSet
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vQueueAddToRegistry
@@ -770,10 +641,7 @@ MPU_vQueueAddToRegistry:
         b MPU_vQueueAddToRegistryImpl
     MPU_vQueueAddToRegistry_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vQueueAddToRegistryImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vQueueAddToRegistry
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vQueueUnregisterQueue
@@ -787,10 +655,7 @@ MPU_vQueueUnregisterQueue:
         b MPU_vQueueUnregisterQueueImpl
     MPU_vQueueUnregisterQueue_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vQueueUnregisterQueueImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vQueueUnregisterQueue
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pcQueueGetName
@@ -804,10 +669,7 @@ MPU_pcQueueGetName:
         b MPU_pcQueueGetNameImpl
     MPU_pcQueueGetName_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pcQueueGetNameImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_pcQueueGetName
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pvTimerGetTimerID
@@ -821,10 +683,7 @@ MPU_pvTimerGetTimerID:
         b MPU_pvTimerGetTimerIDImpl
     MPU_pvTimerGetTimerID_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pvTimerGetTimerIDImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_pvTimerGetTimerID
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTimerSetTimerID
@@ -838,10 +697,7 @@ MPU_vTimerSetTimerID:
         b MPU_vTimerSetTimerIDImpl
     MPU_vTimerSetTimerID_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTimerSetTimerIDImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTimerSetTimerID
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerIsTimerActive
@@ -855,10 +711,7 @@ MPU_xTimerIsTimerActive:
         b MPU_xTimerIsTimerActiveImpl
     MPU_xTimerIsTimerActive_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerIsTimerActiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerIsTimerActive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerGetTimerDaemonTaskHandle
@@ -872,14 +725,11 @@ MPU_xTimerGetTimerDaemonTaskHandle:
         b MPU_xTimerGetTimerDaemonTaskHandleImpl
     MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetTimerDaemonTaskHandleImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xTimerGenericCommandFromTask
-MPU_xTimerGenericCommandFromTask:
+    PUBLIC MPU_xTimerGenericCommandFromTaskEntry
+MPU_xTimerGenericCommandFromTaskEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
@@ -889,10 +739,7 @@ MPU_xTimerGenericCommandFromTask:
         b MPU_xTimerGenericCommandFromTaskImpl
     MPU_xTimerGenericCommandFromTask_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTimerGenericCommandFromTaskImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGenericCommandFromTask
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pcTimerGetName
@@ -906,10 +753,7 @@ MPU_pcTimerGetName:
         b MPU_pcTimerGetNameImpl
     MPU_pcTimerGetName_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pcTimerGetNameImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_pcTimerGetName
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTimerSetReloadMode
@@ -923,10 +767,7 @@ MPU_vTimerSetReloadMode:
         b MPU_vTimerSetReloadModeImpl
     MPU_vTimerSetReloadMode_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTimerSetReloadModeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTimerSetReloadMode
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerGetReloadMode
@@ -940,10 +781,7 @@ MPU_xTimerGetReloadMode:
         b MPU_xTimerGetReloadModeImpl
     MPU_xTimerGetReloadMode_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetReloadModeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGetReloadMode
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTimerGetReloadMode
@@ -957,10 +795,7 @@ MPU_uxTimerGetReloadMode:
         b MPU_uxTimerGetReloadModeImpl
     MPU_uxTimerGetReloadMode_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTimerGetReloadModeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTimerGetReloadMode
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerGetPeriod
@@ -974,10 +809,7 @@ MPU_xTimerGetPeriod:
         b MPU_xTimerGetPeriodImpl
     MPU_xTimerGetPeriod_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetPeriodImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGetPeriod
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerGetExpiryTime
@@ -991,14 +823,11 @@ MPU_xTimerGetExpiryTime:
         b MPU_xTimerGetExpiryTimeImpl
     MPU_xTimerGetExpiryTime_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetExpiryTimeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGetExpiryTime
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xEventGroupWaitBits
-MPU_xEventGroupWaitBits:
+    PUBLIC MPU_xEventGroupWaitBitsEntry
+MPU_xEventGroupWaitBitsEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
@@ -1008,10 +837,7 @@ MPU_xEventGroupWaitBits:
         b MPU_xEventGroupWaitBitsImpl
     MPU_xEventGroupWaitBits_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xEventGroupWaitBitsImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xEventGroupWaitBits
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xEventGroupClearBits
@@ -1025,10 +851,7 @@ MPU_xEventGroupClearBits:
         b MPU_xEventGroupClearBitsImpl
     MPU_xEventGroupClearBits_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xEventGroupClearBitsImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xEventGroupClearBits
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xEventGroupSetBits
@@ -1042,10 +865,7 @@ MPU_xEventGroupSetBits:
         b MPU_xEventGroupSetBitsImpl
     MPU_xEventGroupSetBits_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xEventGroupSetBitsImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xEventGroupSetBits
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xEventGroupSync
@@ -1059,10 +879,7 @@ MPU_xEventGroupSync:
         b MPU_xEventGroupSyncImpl
     MPU_xEventGroupSync_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xEventGroupSyncImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xEventGroupSync
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxEventGroupGetNumber
@@ -1076,10 +893,7 @@ MPU_uxEventGroupGetNumber:
         b MPU_uxEventGroupGetNumberImpl
     MPU_uxEventGroupGetNumber_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxEventGroupGetNumberImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxEventGroupGetNumber
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vEventGroupSetNumber
@@ -1093,10 +907,7 @@ MPU_vEventGroupSetNumber:
         b MPU_vEventGroupSetNumberImpl
     MPU_vEventGroupSetNumber_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vEventGroupSetNumberImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vEventGroupSetNumber
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferSend
@@ -1110,10 +921,7 @@ MPU_xStreamBufferSend:
         b MPU_xStreamBufferSendImpl
     MPU_xStreamBufferSend_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferSendImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferSend
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferReceive
@@ -1127,10 +935,7 @@ MPU_xStreamBufferReceive:
         b MPU_xStreamBufferReceiveImpl
     MPU_xStreamBufferReceive_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferReceiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferReceive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferIsFull
@@ -1144,10 +949,7 @@ MPU_xStreamBufferIsFull:
         b MPU_xStreamBufferIsFullImpl
     MPU_xStreamBufferIsFull_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferIsFullImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferIsFull
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferIsEmpty
@@ -1161,10 +963,7 @@ MPU_xStreamBufferIsEmpty:
         b MPU_xStreamBufferIsEmptyImpl
     MPU_xStreamBufferIsEmpty_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferIsEmptyImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferIsEmpty
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferSpacesAvailable
@@ -1178,10 +977,7 @@ MPU_xStreamBufferSpacesAvailable:
         b MPU_xStreamBufferSpacesAvailableImpl
     MPU_xStreamBufferSpacesAvailable_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferSpacesAvailableImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferSpacesAvailable
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferBytesAvailable
@@ -1195,10 +991,7 @@ MPU_xStreamBufferBytesAvailable:
         b MPU_xStreamBufferBytesAvailableImpl
     MPU_xStreamBufferBytesAvailable_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferBytesAvailableImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferBytesAvailable
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferSetTriggerLevel
@@ -1212,10 +1005,7 @@ MPU_xStreamBufferSetTriggerLevel:
         b MPU_xStreamBufferSetTriggerLevelImpl
     MPU_xStreamBufferSetTriggerLevel_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferSetTriggerLevelImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferNextMessageLengthBytes
@@ -1229,10 +1019,7 @@ MPU_xStreamBufferNextMessageLengthBytes:
         b MPU_xStreamBufferNextMessageLengthBytesImpl
     MPU_xStreamBufferNextMessageLengthBytes_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferNextMessageLengthBytesImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes
 /*-----------------------------------------------------------*/
 
 /* Default weak implementations in case one is not available from
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s
index 15e74ffc1..d8f1b1d9a 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s
@@ -32,6 +32,9 @@ the code is included in C files but excluded by the preprocessor in assembly
 files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
 #include "FreeRTOSConfig.h"
 
+/* System call numbers includes. */
+#include "mpu_syscall_numbers.h"
+
 #ifndef configUSE_MPU_WRAPPERS_V1
     #define configUSE_MPU_WRAPPERS_V1 0
 #endif
@@ -44,7 +47,6 @@ files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler.
     EXTERN SecureContext_LoadContext
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
     EXTERN vSystemCallEnter
-    EXTERN vSystemCallEnter_1
     EXTERN vSystemCallExit
 #endif
 
@@ -86,7 +88,7 @@ vResetPrivilege:
 /*-----------------------------------------------------------*/
 
 vPortAllocateSecureContext:
-    svc 0                                   /* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 0. */
+    svc 100                                 /* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 100. */
     bx lr                                   /* Return. */
 /*-----------------------------------------------------------*/
 
@@ -205,7 +207,7 @@ vStartFirstTask:
     cpsie f
     dsb
     isb
-    svc 2                                   /* System call to start the first task. portSVC_START_SCHEDULER = 2. */
+    svc 102                                 /* System call to start the first task. portSVC_START_SCHEDULER = 102. */
 /*-----------------------------------------------------------*/
 
 ulSetInterruptMask:
@@ -455,11 +457,9 @@ SVC_Handler:
 
     ldr r1, [r0, #24]
     ldrb r2, [r1, #-2]
-    cmp r2, #4          /* portSVC_SYSTEM_CALL_ENTER. */
-    beq syscall_enter
-    cmp r2, #5          /* portSVC_SYSTEM_CALL_ENTER_1. */
-    beq syscall_enter_1
-    cmp r2, #6          /* portSVC_SYSTEM_CALL_EXIT. */
+    cmp r2, #NUM_SYSTEM_CALLS
+    blt syscall_enter
+    cmp r2, #104            /* portSVC_SYSTEM_CALL_EXIT. */
     beq syscall_exit
     b vPortSVCHandler_C
 
@@ -467,10 +467,6 @@ SVC_Handler:
         mov r1, lr
         b vSystemCallEnter
 
-    syscall_enter_1:
-        mov r1, lr
-        b vSystemCallEnter_1
-
     syscall_exit:
         mov r1, lr
         b vSystemCallExit
@@ -493,7 +489,7 @@ vPortFreeSecureContext:
     ldr r1, [r2]                            /* The first item on the stack is the task's xSecureContext. */
     cmp r1, #0                              /* Raise svc if task's xSecureContext is not NULL. */
     it ne
-    svcne 1                                 /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */
+    svcne 101                               /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 101. */
     bx lr                                   /* Return. */
 /*-----------------------------------------------------------*/
 
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/mpu_wrappers_v2_asm.S b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/mpu_wrappers_v2_asm.S
index 1005dad33..80d5a1c63 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/mpu_wrappers_v2_asm.S
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/mpu_wrappers_v2_asm.S
@@ -32,15 +32,12 @@
 /*-----------------------------------------------------------*/
 
 #include "FreeRTOSConfig.h"
+#include "mpu_syscall_numbers.h"
 
 #ifndef configUSE_MPU_WRAPPERS_V1
     #define configUSE_MPU_WRAPPERS_V1 0
 #endif
 
-/* These must be in sync with portmacro.h. */
-#define portSVC_SYSTEM_CALL_ENTER   4 /* System calls with upto 4 parameters. */
-#define portSVC_SYSTEM_CALL_ENTER_1 5 /* System calls with 5 parameters. */
-#define portSVC_SYSTEM_CALL_EXIT    6
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
@@ -56,10 +53,7 @@ MPU_xTaskDelayUntil:
         b MPU_xTaskDelayUntilImpl
     MPU_xTaskDelayUntil_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskDelayUntilImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskDelayUntil
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskAbortDelay
@@ -73,10 +67,7 @@ MPU_xTaskAbortDelay:
         b MPU_xTaskAbortDelayImpl
     MPU_xTaskAbortDelay_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskAbortDelayImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskAbortDelay
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskDelay
@@ -90,10 +81,7 @@ MPU_vTaskDelay:
         b MPU_vTaskDelayImpl
     MPU_vTaskDelay_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskDelayImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskDelay
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskPriorityGet
@@ -107,10 +95,7 @@ MPU_uxTaskPriorityGet:
         b MPU_uxTaskPriorityGetImpl
     MPU_uxTaskPriorityGet_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskPriorityGetImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskPriorityGet
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_eTaskGetState
@@ -124,10 +109,7 @@ MPU_eTaskGetState:
         b MPU_eTaskGetStateImpl
     MPU_eTaskGetState_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_eTaskGetStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_eTaskGetState
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskGetInfo
@@ -141,10 +123,7 @@ MPU_vTaskGetInfo:
         b MPU_vTaskGetInfoImpl
     MPU_vTaskGetInfo_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskGetInfoImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskGetInfo
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetIdleTaskHandle
@@ -158,10 +137,7 @@ MPU_xTaskGetIdleTaskHandle:
         b MPU_xTaskGetIdleTaskHandleImpl
     MPU_xTaskGetIdleTaskHandle_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetIdleTaskHandleImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetIdleTaskHandle
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskSuspend
@@ -175,10 +151,7 @@ MPU_vTaskSuspend:
         b MPU_vTaskSuspendImpl
     MPU_vTaskSuspend_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSuspendImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskSuspend
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskResume
@@ -192,10 +165,7 @@ MPU_vTaskResume:
         b MPU_vTaskResumeImpl
     MPU_vTaskResume_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskResumeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskResume
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetTickCount
@@ -209,10 +179,7 @@ MPU_xTaskGetTickCount:
         b MPU_xTaskGetTickCountImpl
     MPU_xTaskGetTickCount_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetTickCountImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetTickCount
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskGetNumberOfTasks
@@ -226,10 +193,7 @@ MPU_uxTaskGetNumberOfTasks:
         b MPU_uxTaskGetNumberOfTasksImpl
     MPU_uxTaskGetNumberOfTasks_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetNumberOfTasksImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskGetNumberOfTasks
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGetRunTimeCounter
@@ -243,10 +207,7 @@ MPU_ulTaskGetRunTimeCounter:
         b MPU_ulTaskGetRunTimeCounterImpl
     MPU_ulTaskGetRunTimeCounter_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetRunTimeCounterImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGetRunTimeCounter
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGetRunTimePercent
@@ -260,10 +221,7 @@ MPU_ulTaskGetRunTimePercent:
         b MPU_ulTaskGetRunTimePercentImpl
     MPU_ulTaskGetRunTimePercent_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetRunTimePercentImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGetRunTimePercent
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGetIdleRunTimePercent
@@ -277,10 +235,7 @@ MPU_ulTaskGetIdleRunTimePercent:
         b MPU_ulTaskGetIdleRunTimePercentImpl
     MPU_ulTaskGetIdleRunTimePercent_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetIdleRunTimePercentImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGetIdleRunTimeCounter
@@ -294,10 +249,7 @@ MPU_ulTaskGetIdleRunTimeCounter:
         b MPU_ulTaskGetIdleRunTimeCounterImpl
     MPU_ulTaskGetIdleRunTimeCounter_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetIdleRunTimeCounterImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskSetApplicationTaskTag
@@ -311,10 +263,7 @@ MPU_vTaskSetApplicationTaskTag:
         b MPU_vTaskSetApplicationTaskTagImpl
     MPU_vTaskSetApplicationTaskTag_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSetApplicationTaskTagImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskSetApplicationTaskTag
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetApplicationTaskTag
@@ -328,10 +277,7 @@ MPU_xTaskGetApplicationTaskTag:
         b MPU_xTaskGetApplicationTaskTagImpl
     MPU_xTaskGetApplicationTaskTag_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetApplicationTaskTagImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetApplicationTaskTag
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskSetThreadLocalStoragePointer
@@ -345,10 +291,7 @@ MPU_vTaskSetThreadLocalStoragePointer:
         b MPU_vTaskSetThreadLocalStoragePointerImpl
     MPU_vTaskSetThreadLocalStoragePointer_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSetThreadLocalStoragePointerImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pvTaskGetThreadLocalStoragePointer
@@ -362,10 +305,7 @@ MPU_pvTaskGetThreadLocalStoragePointer:
         b MPU_pvTaskGetThreadLocalStoragePointerImpl
     MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pvTaskGetThreadLocalStoragePointerImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskGetSystemState
@@ -379,10 +319,7 @@ MPU_uxTaskGetSystemState:
         b MPU_uxTaskGetSystemStateImpl
     MPU_uxTaskGetSystemState_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetSystemStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskGetSystemState
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskGetStackHighWaterMark
@@ -396,10 +333,7 @@ MPU_uxTaskGetStackHighWaterMark:
         b MPU_uxTaskGetStackHighWaterMarkImpl
     MPU_uxTaskGetStackHighWaterMark_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetStackHighWaterMarkImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskGetStackHighWaterMark2
@@ -413,10 +347,7 @@ MPU_uxTaskGetStackHighWaterMark2:
         b MPU_uxTaskGetStackHighWaterMark2Impl
     MPU_uxTaskGetStackHighWaterMark2_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetStackHighWaterMark2Impl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetCurrentTaskHandle
@@ -430,10 +361,7 @@ MPU_xTaskGetCurrentTaskHandle:
         b MPU_xTaskGetCurrentTaskHandleImpl
     MPU_xTaskGetCurrentTaskHandle_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetCurrentTaskHandleImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetSchedulerState
@@ -447,10 +375,7 @@ MPU_xTaskGetSchedulerState:
         b MPU_xTaskGetSchedulerStateImpl
     MPU_xTaskGetSchedulerState_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetSchedulerStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetSchedulerState
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskSetTimeOutState
@@ -464,10 +389,7 @@ MPU_vTaskSetTimeOutState:
         b MPU_vTaskSetTimeOutStateImpl
     MPU_vTaskSetTimeOutState_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSetTimeOutStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskSetTimeOutState
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskCheckForTimeOut
@@ -481,14 +403,11 @@ MPU_xTaskCheckForTimeOut:
         b MPU_xTaskCheckForTimeOutImpl
     MPU_xTaskCheckForTimeOut_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskCheckForTimeOutImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskCheckForTimeOut
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xTaskGenericNotify
-MPU_xTaskGenericNotify:
+    PUBLIC MPU_xTaskGenericNotifyEntry
+MPU_xTaskGenericNotifyEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
@@ -498,14 +417,11 @@ MPU_xTaskGenericNotify:
         b MPU_xTaskGenericNotifyImpl
     MPU_xTaskGenericNotify_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTaskGenericNotifyImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGenericNotify
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xTaskGenericNotifyWait
-MPU_xTaskGenericNotifyWait:
+    PUBLIC MPU_xTaskGenericNotifyWaitEntry
+MPU_xTaskGenericNotifyWaitEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
@@ -515,10 +431,7 @@ MPU_xTaskGenericNotifyWait:
         b MPU_xTaskGenericNotifyWaitImpl
     MPU_xTaskGenericNotifyWait_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTaskGenericNotifyWaitImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGenericNotifyWait
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGenericNotifyTake
@@ -532,10 +445,7 @@ MPU_ulTaskGenericNotifyTake:
         b MPU_ulTaskGenericNotifyTakeImpl
     MPU_ulTaskGenericNotifyTake_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGenericNotifyTakeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGenericNotifyTake
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGenericNotifyStateClear
@@ -549,10 +459,7 @@ MPU_xTaskGenericNotifyStateClear:
         b MPU_xTaskGenericNotifyStateClearImpl
     MPU_xTaskGenericNotifyStateClear_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGenericNotifyStateClearImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGenericNotifyStateClear
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGenericNotifyValueClear
@@ -566,10 +473,7 @@ MPU_ulTaskGenericNotifyValueClear:
         b MPU_ulTaskGenericNotifyValueClearImpl
     MPU_ulTaskGenericNotifyValueClear_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGenericNotifyValueClearImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueGenericSend
@@ -583,10 +487,7 @@ MPU_xQueueGenericSend:
         b MPU_xQueueGenericSendImpl
     MPU_xQueueGenericSend_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueGenericSendImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueGenericSend
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxQueueMessagesWaiting
@@ -600,10 +501,7 @@ MPU_uxQueueMessagesWaiting:
         b MPU_uxQueueMessagesWaitingImpl
     MPU_uxQueueMessagesWaiting_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxQueueMessagesWaitingImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxQueueMessagesWaiting
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxQueueSpacesAvailable
@@ -617,10 +515,7 @@ MPU_uxQueueSpacesAvailable:
         b MPU_uxQueueSpacesAvailableImpl
     MPU_uxQueueSpacesAvailable_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxQueueSpacesAvailableImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxQueueSpacesAvailable
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueReceive
@@ -634,10 +529,7 @@ MPU_xQueueReceive:
         b MPU_xQueueReceiveImpl
     MPU_xQueueReceive_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueReceiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueReceive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueuePeek
@@ -651,10 +543,7 @@ MPU_xQueuePeek:
         b MPU_xQueuePeekImpl
     MPU_xQueuePeek_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueuePeekImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueuePeek
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueSemaphoreTake
@@ -668,10 +557,7 @@ MPU_xQueueSemaphoreTake:
         b MPU_xQueueSemaphoreTakeImpl
     MPU_xQueueSemaphoreTake_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueSemaphoreTakeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueSemaphoreTake
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueGetMutexHolder
@@ -685,10 +571,7 @@ MPU_xQueueGetMutexHolder:
         b MPU_xQueueGetMutexHolderImpl
     MPU_xQueueGetMutexHolder_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueGetMutexHolderImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueGetMutexHolder
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueTakeMutexRecursive
@@ -702,10 +585,7 @@ MPU_xQueueTakeMutexRecursive:
         b MPU_xQueueTakeMutexRecursiveImpl
     MPU_xQueueTakeMutexRecursive_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueTakeMutexRecursiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueTakeMutexRecursive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueGiveMutexRecursive
@@ -719,10 +599,7 @@ MPU_xQueueGiveMutexRecursive:
         b MPU_xQueueGiveMutexRecursiveImpl
     MPU_xQueueGiveMutexRecursive_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueGiveMutexRecursiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueGiveMutexRecursive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueSelectFromSet
@@ -736,10 +613,7 @@ MPU_xQueueSelectFromSet:
         b MPU_xQueueSelectFromSetImpl
     MPU_xQueueSelectFromSet_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueSelectFromSetImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueSelectFromSet
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueAddToSet
@@ -753,10 +627,7 @@ MPU_xQueueAddToSet:
         b MPU_xQueueAddToSetImpl
     MPU_xQueueAddToSet_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueAddToSetImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueAddToSet
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vQueueAddToRegistry
@@ -770,10 +641,7 @@ MPU_vQueueAddToRegistry:
         b MPU_vQueueAddToRegistryImpl
     MPU_vQueueAddToRegistry_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vQueueAddToRegistryImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vQueueAddToRegistry
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vQueueUnregisterQueue
@@ -787,10 +655,7 @@ MPU_vQueueUnregisterQueue:
         b MPU_vQueueUnregisterQueueImpl
     MPU_vQueueUnregisterQueue_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vQueueUnregisterQueueImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vQueueUnregisterQueue
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pcQueueGetName
@@ -804,10 +669,7 @@ MPU_pcQueueGetName:
         b MPU_pcQueueGetNameImpl
     MPU_pcQueueGetName_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pcQueueGetNameImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_pcQueueGetName
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pvTimerGetTimerID
@@ -821,10 +683,7 @@ MPU_pvTimerGetTimerID:
         b MPU_pvTimerGetTimerIDImpl
     MPU_pvTimerGetTimerID_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pvTimerGetTimerIDImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_pvTimerGetTimerID
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTimerSetTimerID
@@ -838,10 +697,7 @@ MPU_vTimerSetTimerID:
         b MPU_vTimerSetTimerIDImpl
     MPU_vTimerSetTimerID_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTimerSetTimerIDImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTimerSetTimerID
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerIsTimerActive
@@ -855,10 +711,7 @@ MPU_xTimerIsTimerActive:
         b MPU_xTimerIsTimerActiveImpl
     MPU_xTimerIsTimerActive_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerIsTimerActiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerIsTimerActive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerGetTimerDaemonTaskHandle
@@ -872,14 +725,11 @@ MPU_xTimerGetTimerDaemonTaskHandle:
         b MPU_xTimerGetTimerDaemonTaskHandleImpl
     MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetTimerDaemonTaskHandleImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xTimerGenericCommandFromTask
-MPU_xTimerGenericCommandFromTask:
+    PUBLIC MPU_xTimerGenericCommandFromTaskEntry
+MPU_xTimerGenericCommandFromTaskEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
@@ -889,10 +739,7 @@ MPU_xTimerGenericCommandFromTask:
         b MPU_xTimerGenericCommandFromTaskImpl
     MPU_xTimerGenericCommandFromTask_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTimerGenericCommandFromTaskImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGenericCommandFromTask
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pcTimerGetName
@@ -906,10 +753,7 @@ MPU_pcTimerGetName:
         b MPU_pcTimerGetNameImpl
     MPU_pcTimerGetName_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pcTimerGetNameImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_pcTimerGetName
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTimerSetReloadMode
@@ -923,10 +767,7 @@ MPU_vTimerSetReloadMode:
         b MPU_vTimerSetReloadModeImpl
     MPU_vTimerSetReloadMode_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTimerSetReloadModeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTimerSetReloadMode
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerGetReloadMode
@@ -940,10 +781,7 @@ MPU_xTimerGetReloadMode:
         b MPU_xTimerGetReloadModeImpl
     MPU_xTimerGetReloadMode_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetReloadModeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGetReloadMode
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTimerGetReloadMode
@@ -957,10 +795,7 @@ MPU_uxTimerGetReloadMode:
         b MPU_uxTimerGetReloadModeImpl
     MPU_uxTimerGetReloadMode_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTimerGetReloadModeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTimerGetReloadMode
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerGetPeriod
@@ -974,10 +809,7 @@ MPU_xTimerGetPeriod:
         b MPU_xTimerGetPeriodImpl
     MPU_xTimerGetPeriod_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetPeriodImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGetPeriod
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerGetExpiryTime
@@ -991,14 +823,11 @@ MPU_xTimerGetExpiryTime:
         b MPU_xTimerGetExpiryTimeImpl
     MPU_xTimerGetExpiryTime_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetExpiryTimeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGetExpiryTime
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xEventGroupWaitBits
-MPU_xEventGroupWaitBits:
+    PUBLIC MPU_xEventGroupWaitBitsEntry
+MPU_xEventGroupWaitBitsEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
@@ -1008,10 +837,7 @@ MPU_xEventGroupWaitBits:
         b MPU_xEventGroupWaitBitsImpl
     MPU_xEventGroupWaitBits_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xEventGroupWaitBitsImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xEventGroupWaitBits
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xEventGroupClearBits
@@ -1025,10 +851,7 @@ MPU_xEventGroupClearBits:
         b MPU_xEventGroupClearBitsImpl
     MPU_xEventGroupClearBits_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xEventGroupClearBitsImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xEventGroupClearBits
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xEventGroupSetBits
@@ -1042,10 +865,7 @@ MPU_xEventGroupSetBits:
         b MPU_xEventGroupSetBitsImpl
     MPU_xEventGroupSetBits_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xEventGroupSetBitsImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xEventGroupSetBits
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xEventGroupSync
@@ -1059,10 +879,7 @@ MPU_xEventGroupSync:
         b MPU_xEventGroupSyncImpl
     MPU_xEventGroupSync_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xEventGroupSyncImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xEventGroupSync
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxEventGroupGetNumber
@@ -1076,10 +893,7 @@ MPU_uxEventGroupGetNumber:
         b MPU_uxEventGroupGetNumberImpl
     MPU_uxEventGroupGetNumber_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxEventGroupGetNumberImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxEventGroupGetNumber
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vEventGroupSetNumber
@@ -1093,10 +907,7 @@ MPU_vEventGroupSetNumber:
         b MPU_vEventGroupSetNumberImpl
     MPU_vEventGroupSetNumber_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vEventGroupSetNumberImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vEventGroupSetNumber
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferSend
@@ -1110,10 +921,7 @@ MPU_xStreamBufferSend:
         b MPU_xStreamBufferSendImpl
     MPU_xStreamBufferSend_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferSendImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferSend
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferReceive
@@ -1127,10 +935,7 @@ MPU_xStreamBufferReceive:
         b MPU_xStreamBufferReceiveImpl
     MPU_xStreamBufferReceive_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferReceiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferReceive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferIsFull
@@ -1144,10 +949,7 @@ MPU_xStreamBufferIsFull:
         b MPU_xStreamBufferIsFullImpl
     MPU_xStreamBufferIsFull_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferIsFullImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferIsFull
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferIsEmpty
@@ -1161,10 +963,7 @@ MPU_xStreamBufferIsEmpty:
         b MPU_xStreamBufferIsEmptyImpl
     MPU_xStreamBufferIsEmpty_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferIsEmptyImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferIsEmpty
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferSpacesAvailable
@@ -1178,10 +977,7 @@ MPU_xStreamBufferSpacesAvailable:
         b MPU_xStreamBufferSpacesAvailableImpl
     MPU_xStreamBufferSpacesAvailable_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferSpacesAvailableImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferSpacesAvailable
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferBytesAvailable
@@ -1195,10 +991,7 @@ MPU_xStreamBufferBytesAvailable:
         b MPU_xStreamBufferBytesAvailableImpl
     MPU_xStreamBufferBytesAvailable_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferBytesAvailableImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferBytesAvailable
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferSetTriggerLevel
@@ -1212,10 +1005,7 @@ MPU_xStreamBufferSetTriggerLevel:
         b MPU_xStreamBufferSetTriggerLevelImpl
     MPU_xStreamBufferSetTriggerLevel_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferSetTriggerLevelImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferNextMessageLengthBytes
@@ -1229,10 +1019,7 @@ MPU_xStreamBufferNextMessageLengthBytes:
         b MPU_xStreamBufferNextMessageLengthBytesImpl
     MPU_xStreamBufferNextMessageLengthBytes_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferNextMessageLengthBytesImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes
 /*-----------------------------------------------------------*/
 
 /* Default weak implementations in case one is not available from
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s
index ec5202527..7cf467d22 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s
@@ -32,6 +32,9 @@ the code is included in C files but excluded by the preprocessor in assembly
 files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
 #include "FreeRTOSConfig.h"
 
+/* System call numbers includes. */
+#include "mpu_syscall_numbers.h"
+
 #ifndef configUSE_MPU_WRAPPERS_V1
     #define configUSE_MPU_WRAPPERS_V1 0
 #endif
@@ -41,7 +44,6 @@ files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler.
     EXTERN vPortSVCHandler_C
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
     EXTERN vSystemCallEnter
-    EXTERN vSystemCallEnter_1
     EXTERN vSystemCallExit
 #endif
 
@@ -191,7 +193,7 @@ vStartFirstTask:
     cpsie f
     dsb
     isb
-    svc 2                                   /* System call to start the first task. portSVC_START_SCHEDULER = 2. */
+    svc 102                                 /* System call to start the first task. portSVC_START_SCHEDULER = 102. */
 /*-----------------------------------------------------------*/
 
 ulSetInterruptMask:
@@ -371,11 +373,9 @@ SVC_Handler:
 
     ldr r1, [r0, #24]
     ldrb r2, [r1, #-2]
-    cmp r2, #4          /* portSVC_SYSTEM_CALL_ENTER. */
-    beq syscall_enter
-    cmp r2, #5          /* portSVC_SYSTEM_CALL_ENTER_1. */
-    beq syscall_enter_1
-    cmp r2, #6          /* portSVC_SYSTEM_CALL_EXIT. */
+    cmp r2, #NUM_SYSTEM_CALLS
+    blt syscall_enter
+    cmp r2, #104            /* portSVC_SYSTEM_CALL_EXIT. */
     beq syscall_exit
     b vPortSVCHandler_C
 
@@ -383,10 +383,6 @@ SVC_Handler:
         mov r1, lr
         b vSystemCallEnter
 
-    syscall_enter_1:
-        mov r1, lr
-        b vSystemCallEnter_1
-
     syscall_exit:
         mov r1, lr
         b vSystemCallExit
diff --git a/portable/ARMv8M/non_secure/portmacrocommon.h b/portable/ARMv8M/non_secure/portmacrocommon.h
index 60ef37380..672b0dbdc 100644
--- a/portable/ARMv8M/non_secure/portmacrocommon.h
+++ b/portable/ARMv8M/non_secure/portmacrocommon.h
@@ -322,14 +322,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 /**
  * @brief SVC numbers.
  */
-#define portSVC_ALLOCATE_SECURE_CONTEXT    0
-#define portSVC_FREE_SECURE_CONTEXT        1
-#define portSVC_START_SCHEDULER            2
-#define portSVC_RAISE_PRIVILEGE            3
-#define portSVC_SYSTEM_CALL_ENTER          4   /* System calls with upto 4 parameters. */
-#define portSVC_SYSTEM_CALL_ENTER_1        5   /* System calls with 5 parameters. */
-#define portSVC_SYSTEM_CALL_EXIT           6
-#define portSVC_YIELD                      7
+#define portSVC_ALLOCATE_SECURE_CONTEXT    100
+#define portSVC_FREE_SECURE_CONTEXT        101
+#define portSVC_START_SCHEDULER            102
+#define portSVC_RAISE_PRIVILEGE            103
+#define portSVC_SYSTEM_CALL_EXIT           104
+#define portSVC_YIELD                      105
 /*-----------------------------------------------------------*/
 
 /**
diff --git a/portable/Common/mpu_wrappers_v2.c b/portable/Common/mpu_wrappers_v2.c
index beb21d271..832a7f844 100644
--- a/portable/Common/mpu_wrappers_v2.c
+++ b/portable/Common/mpu_wrappers_v2.c
@@ -44,6 +44,7 @@
 #include "event_groups.h"
 #include "stream_buffer.h"
 #include "mpu_prototypes.h"
+#include "mpu_syscall_numbers.h"
 
 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
 /*-----------------------------------------------------------*/
@@ -1261,48 +1262,81 @@
 
     #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-        BaseType_t MPU_xTaskGenericNotifyImpl( TaskHandle_t xTaskToNotify,
-                                               UBaseType_t uxIndexToNotify,
-                                               uint32_t ulValue,
-                                               eNotifyAction eAction,
-                                               uint32_t * pulPreviousNotificationValue ) PRIVILEGED_FUNCTION;
+        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
+                                           UBaseType_t uxIndexToNotify,
+                                           uint32_t ulValue,
+                                           eNotifyAction eAction,
+                                           uint32_t * pulPreviousNotificationValue ) /* FREERTOS_SYSTEM_CALL */
+        {
+            BaseType_t xReturn = pdFAIL;
+            xTaskGenericNotifyParams_t xParams;
 
-        BaseType_t MPU_xTaskGenericNotifyImpl( TaskHandle_t xTaskToNotify,
-                                               UBaseType_t uxIndexToNotify,
-                                               uint32_t ulValue,
-                                               eNotifyAction eAction,
-                                               uint32_t * pulPreviousNotificationValue ) /* PRIVILEGED_FUNCTION */
+            xParams.xTaskToNotify = xTaskToNotify;
+            xParams.uxIndexToNotify = uxIndexToNotify;
+            xParams.ulValue = ulValue;
+            xParams.eAction = eAction;
+            xParams.pulPreviousNotificationValue = pulPreviousNotificationValue;
+
+            xReturn = MPU_xTaskGenericNotifyEntry( &( xParams ) );
+
+            return xReturn;
+        }
+
+        BaseType_t MPU_xTaskGenericNotifyImpl( const xTaskGenericNotifyParams_t * pxParams ) PRIVILEGED_FUNCTION;
+
+        BaseType_t MPU_xTaskGenericNotifyImpl( const xTaskGenericNotifyParams_t * pxParams ) /* PRIVILEGED_FUNCTION */
         {
             BaseType_t xReturn = pdFAIL;
             int32_t lIndex;
             TaskHandle_t xInternalTaskHandle = NULL;
             BaseType_t xIsPreviousNotificationValueWriteable = pdFALSE;
             BaseType_t xCallingTaskIsAuthorizedToAccessTask = pdFALSE;
+            BaseType_t xAreParamsReadable = pdFALSE;
 
-            if( uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES )
+            if( pxParams != NULL )
             {
-                if( pulPreviousNotificationValue != NULL )
-                {
-                    xIsPreviousNotificationValueWriteable = xPortIsAuthorizedToAccessBuffer( pulPreviousNotificationValue,
-                                                                                             sizeof( uint32_t ),
-                                                                                             tskMPU_WRITE_PERMISSION );
-                }
+                xAreParamsReadable = xPortIsAuthorizedToAccessBuffer( pxParams,
+                                                                      sizeof( xTaskGenericNotifyParams_t ),
+                                                                      tskMPU_READ_PERMISSION );
+            }
 
-                if( ( pulPreviousNotificationValue == NULL ) || ( xIsPreviousNotificationValueWriteable == pdTRUE ) )
+            if( xAreParamsReadable == pdTRUE )
+            {
+                if( ( pxParams->uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES ) &&
+                    ( ( pxParams->eAction == eNoAction ) ||
+                      ( pxParams->eAction == eSetBits ) ||
+                      ( pxParams->eAction == eIncrement ) ||
+                      ( pxParams->eAction == eSetValueWithOverwrite ) ||
+                      ( pxParams->eAction == eSetValueWithoutOverwrite ) ) )
                 {
-                    lIndex = ( int32_t ) xTaskToNotify;
-
-                    if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+                    if( pxParams->pulPreviousNotificationValue != NULL )
                     {
-                        xCallingTaskIsAuthorizedToAccessTask = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                        xIsPreviousNotificationValueWriteable = xPortIsAuthorizedToAccessBuffer( pxParams->pulPreviousNotificationValue,
+                                                                                                 sizeof( uint32_t ),
+                                                                                                 tskMPU_WRITE_PERMISSION );
+                    }
 
-                        if( xCallingTaskIsAuthorizedToAccessTask == pdTRUE )
+                    if( ( pxParams->pulPreviousNotificationValue == NULL ) ||
+                        ( xIsPreviousNotificationValueWriteable == pdTRUE ) )
+                    {
+                        lIndex = ( int32_t ) ( pxParams->xTaskToNotify );
+
+                        if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
                         {
-                            xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                            xCallingTaskIsAuthorizedToAccessTask = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-                            if( xInternalTaskHandle != NULL )
+                            if( xCallingTaskIsAuthorizedToAccessTask == pdTRUE )
                             {
-                                xReturn = xTaskGenericNotify( xInternalTaskHandle, uxIndexToNotify, ulValue, eAction, pulPreviousNotificationValue );
+                                xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                                if( xInternalTaskHandle != NULL )
+                                {
+                                    xReturn = xTaskGenericNotify( xInternalTaskHandle,
+                                                                  pxParams->uxIndexToNotify,
+                                                                  pxParams->ulValue,
+                                                                  pxParams->eAction,
+                                                                  pxParams->pulPreviousNotificationValue );
+                                }
                             }
                         }
                     }
@@ -1317,33 +1351,61 @@
 
     #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-        BaseType_t MPU_xTaskGenericNotifyWaitImpl( UBaseType_t uxIndexToWaitOn,
-                                                   uint32_t ulBitsToClearOnEntry,
-                                                   uint32_t ulBitsToClearOnExit,
-                                                   uint32_t * pulNotificationValue,
-                                                   TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
+                                               uint32_t ulBitsToClearOnEntry,
+                                               uint32_t ulBitsToClearOnExit,
+                                               uint32_t * pulNotificationValue,
+                                               TickType_t xTicksToWait )
+        {
+            BaseType_t xReturn = pdFAIL;
+            xTaskGenericNotifyWaitParams_t xParams;
 
-        BaseType_t MPU_xTaskGenericNotifyWaitImpl( UBaseType_t uxIndexToWaitOn,
-                                                   uint32_t ulBitsToClearOnEntry,
-                                                   uint32_t ulBitsToClearOnExit,
-                                                   uint32_t * pulNotificationValue,
-                                                   TickType_t xTicksToWait ) /* PRIVILEGED_FUNCTION */
+            xParams.uxIndexToWaitOn = uxIndexToWaitOn;
+            xParams.ulBitsToClearOnEntry = ulBitsToClearOnEntry;
+            xParams.ulBitsToClearOnExit = ulBitsToClearOnExit;
+            xParams.pulNotificationValue = pulNotificationValue;
+            xParams.xTicksToWait = xTicksToWait;
+
+            xReturn = MPU_xTaskGenericNotifyWaitEntry( &( xParams ) );
+
+            return xReturn;
+        }
+
+        BaseType_t MPU_xTaskGenericNotifyWaitImpl( const xTaskGenericNotifyWaitParams_t * pxParams ) PRIVILEGED_FUNCTION;
+
+        BaseType_t MPU_xTaskGenericNotifyWaitImpl( const xTaskGenericNotifyWaitParams_t * pxParams ) /* PRIVILEGED_FUNCTION */
         {
             BaseType_t xReturn = pdFAIL;
             BaseType_t xIsNotificationValueWritable = pdFALSE;
+            BaseType_t xAreParamsReadable = pdFALSE;
 
-            if( uxIndexToWaitOn < configTASK_NOTIFICATION_ARRAY_ENTRIES )
+            if( pxParams != NULL )
             {
-                if( pulNotificationValue != NULL )
-                {
-                    xIsNotificationValueWritable = xPortIsAuthorizedToAccessBuffer( pulNotificationValue,
-                                                                                    sizeof( uint32_t ),
-                                                                                    tskMPU_WRITE_PERMISSION );
-                }
+                xAreParamsReadable = xPortIsAuthorizedToAccessBuffer( pxParams,
+                                                                      sizeof( xTaskGenericNotifyWaitParams_t ),
+                                                                      tskMPU_READ_PERMISSION );
+            }
 
-                if( ( pulNotificationValue == NULL ) || ( xIsNotificationValueWritable == pdTRUE ) )
+            if( xAreParamsReadable == pdTRUE )
+            {
+                if( pxParams->uxIndexToWaitOn < configTASK_NOTIFICATION_ARRAY_ENTRIES )
                 {
-                    xReturn = xTaskGenericNotifyWait( uxIndexToWaitOn, ulBitsToClearOnEntry, ulBitsToClearOnExit, pulNotificationValue, xTicksToWait );
+                    if( pxParams->pulNotificationValue != NULL )
+                    {
+                        xIsNotificationValueWritable = xPortIsAuthorizedToAccessBuffer( pxParams->pulNotificationValue,
+                                                                                        sizeof( uint32_t ),
+                                                                                        tskMPU_WRITE_PERMISSION );
+                    }
+
+                    if( ( pxParams->pulNotificationValue == NULL ) ||
+                        ( xIsNotificationValueWritable == pdTRUE ) )
+                    {
+                        xReturn = xTaskGenericNotifyWait( pxParams->uxIndexToWaitOn,
+                                                          pxParams->ulBitsToClearOnEntry,
+                                                          pxParams->ulBitsToClearOnExit,
+                                                          pxParams->pulNotificationValue,
+                                                          pxParams->xTicksToWait );
+                    }
                 }
             }
 
@@ -2423,6 +2485,7 @@
             BaseType_t xCallingTaskIsAuthorizedToAccessQueue = pdFALSE;
             int32_t lIndex;
             QueueHandle_t xInternalQueueHandle = NULL;
+            UBaseType_t uxQueueItemSize;
 
             lIndex = ( int32_t ) xMutex;
 
@@ -2436,7 +2499,12 @@
 
                     if( xInternalQueueHandle != NULL )
                     {
-                        xReturn = xQueueTakeMutexRecursive( xInternalQueueHandle, xBlockTime );
+                        uxQueueItemSize = uxQueueGetQueueItemSize( xInternalQueueHandle );
+
+                        if( uxQueueItemSize == 0 )
+                        {
+                            xReturn = xQueueTakeMutexRecursive( xInternalQueueHandle, xBlockTime );
+                        }
                     }
                 }
             }
@@ -3366,48 +3434,76 @@
 
     #if ( configUSE_TIMERS == 1 )
 
-        BaseType_t MPU_xTimerGenericCommandFromTaskImpl( TimerHandle_t xTimer,
-                                                         const BaseType_t xCommandID,
-                                                         const TickType_t xOptionalValue,
-                                                         BaseType_t * const pxHigherPriorityTaskWoken,
-                                                         const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                                     const BaseType_t xCommandID,
+                                                     const TickType_t xOptionalValue,
+                                                     BaseType_t * const pxHigherPriorityTaskWoken,
+                                                     const TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+        {
+            BaseType_t xReturn = pdFALSE;
+            xTimerGenericCommandFromTaskParams_t xParams;
 
-        BaseType_t MPU_xTimerGenericCommandFromTaskImpl( TimerHandle_t xTimer,
-                                                         const BaseType_t xCommandID,
-                                                         const TickType_t xOptionalValue,
-                                                         BaseType_t * const pxHigherPriorityTaskWoken,
-                                                         const TickType_t xTicksToWait ) /* PRIVILEGED_FUNCTION */
+            xParams.xTimer = xTimer;
+            xParams.xCommandID = xCommandID;
+            xParams.xOptionalValue = xOptionalValue;
+            xParams.pxHigherPriorityTaskWoken = pxHigherPriorityTaskWoken;
+            xParams.xTicksToWait = xTicksToWait;
+
+            xReturn = MPU_xTimerGenericCommandFromTaskEntry( &( xParams ) );
+
+            return xReturn;
+        }
+
+        BaseType_t MPU_xTimerGenericCommandFromTaskImpl( const xTimerGenericCommandFromTaskParams_t * pxParams ) PRIVILEGED_FUNCTION;
+
+        BaseType_t MPU_xTimerGenericCommandFromTaskImpl( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* PRIVILEGED_FUNCTION */
         {
             BaseType_t xReturn = pdFALSE;
             TimerHandle_t xInternalTimerHandle = NULL;
             int32_t lIndex;
             BaseType_t xIsHigherPriorityTaskWokenWriteable = pdFALSE;
             BaseType_t xCallingTaskIsAuthorizedToAccessTimer = pdFALSE;
+            BaseType_t xAreParamsReadable = pdFALSE;
 
-            if( xCommandID < tmrFIRST_FROM_ISR_COMMAND )
+            if( pxParams != NULL )
             {
-                if( pxHigherPriorityTaskWoken != NULL )
-                {
-                    xIsHigherPriorityTaskWokenWriteable = xPortIsAuthorizedToAccessBuffer( pxHigherPriorityTaskWoken,
-                                                                                           sizeof( BaseType_t ),
-                                                                                           tskMPU_WRITE_PERMISSION );
-                }
+                xAreParamsReadable = xPortIsAuthorizedToAccessBuffer( pxParams,
+                                                                      sizeof( xTimerGenericCommandFromTaskParams_t ),
+                                                                      tskMPU_READ_PERMISSION );
+            }
 
-                if( ( pxHigherPriorityTaskWoken == NULL ) || ( xIsHigherPriorityTaskWokenWriteable == pdTRUE ) )
+            if( xAreParamsReadable == pdTRUE )
+            {
+                if( pxParams->xCommandID < tmrFIRST_FROM_ISR_COMMAND )
                 {
-                    lIndex = ( int32_t ) xTimer;
-
-                    if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+                    if( pxParams->pxHigherPriorityTaskWoken != NULL )
                     {
-                        xCallingTaskIsAuthorizedToAccessTimer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                        xIsHigherPriorityTaskWokenWriteable = xPortIsAuthorizedToAccessBuffer( pxParams->pxHigherPriorityTaskWoken,
+                                                                                               sizeof( BaseType_t ),
+                                                                                               tskMPU_WRITE_PERMISSION );
+                    }
 
-                        if( xCallingTaskIsAuthorizedToAccessTimer == pdTRUE )
+                    if( ( pxParams->pxHigherPriorityTaskWoken == NULL ) ||
+                        ( xIsHigherPriorityTaskWokenWriteable == pdTRUE ) )
+                    {
+                        lIndex = ( int32_t ) ( pxParams->xTimer );
+
+                        if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
                         {
-                            xInternalTimerHandle = MPU_GetTimerHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                            xCallingTaskIsAuthorizedToAccessTimer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-                            if( xInternalTimerHandle != NULL )
+                            if( xCallingTaskIsAuthorizedToAccessTimer == pdTRUE )
                             {
-                                xReturn = xTimerGenericCommandFromTask( xInternalTimerHandle, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait );
+                                xInternalTimerHandle = MPU_GetTimerHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                                if( xInternalTimerHandle != NULL )
+                                {
+                                    xReturn = xTimerGenericCommandFromTask( xInternalTimerHandle,
+                                                                            pxParams->xCommandID,
+                                                                            pxParams->xOptionalValue,
+                                                                            pxParams->pxHigherPriorityTaskWoken,
+                                                                            pxParams->xTicksToWait );
+                                }
                             }
                         }
                     }
@@ -3771,43 +3867,70 @@
 /*           MPU wrappers for event group APIs.              */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupWaitBitsImpl( EventGroupHandle_t xEventGroup,
-                                             const EventBits_t uxBitsToWaitFor,
-                                             const BaseType_t xClearOnExit,
-                                             const BaseType_t xWaitForAllBits,
-                                             TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         const BaseType_t xClearOnExit,
+                                         const BaseType_t xWaitForAllBits,
+                                         TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+    {
+        EventBits_t xReturn = 0;
+        xEventGroupWaitBitsParams_t xParams;
 
-    EventBits_t MPU_xEventGroupWaitBitsImpl( EventGroupHandle_t xEventGroup,
-                                             const EventBits_t uxBitsToWaitFor,
-                                             const BaseType_t xClearOnExit,
-                                             const BaseType_t xWaitForAllBits,
-                                             TickType_t xTicksToWait ) /* PRIVILEGED_FUNCTION */
+        xParams.xEventGroup = xEventGroup;
+        xParams.uxBitsToWaitFor = uxBitsToWaitFor;
+        xParams.xClearOnExit = xClearOnExit;
+        xParams.xWaitForAllBits = xWaitForAllBits;
+        xParams.xTicksToWait = xTicksToWait;
+
+        xReturn = MPU_xEventGroupWaitBitsEntry( &( xParams ) );
+
+        return xReturn;
+    }
+
+    EventBits_t MPU_xEventGroupWaitBitsImpl( const xEventGroupWaitBitsParams_t * pxParams ) PRIVILEGED_FUNCTION;
+
+    EventBits_t MPU_xEventGroupWaitBitsImpl( const xEventGroupWaitBitsParams_t * pxParams ) /* PRIVILEGED_FUNCTION */
     {
         EventBits_t xReturn = 0;
         EventGroupHandle_t xInternalEventGroupHandle = NULL;
         int32_t lIndex;
         BaseType_t xCallingTaskIsAuthorizedToAccessEventGroup = pdFALSE;
+        BaseType_t xAreParamsReadable = pdFALSE;
 
-        if( ( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 ) &&
-            ( uxBitsToWaitFor != 0 )
-            #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
-                && ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) )
-            #endif
-            )
+        if( pxParams != NULL )
         {
-            lIndex = ( int32_t ) xEventGroup;
+            xAreParamsReadable = xPortIsAuthorizedToAccessBuffer( pxParams,
+                                                                  sizeof( xEventGroupWaitBitsParams_t ),
+                                                                  tskMPU_READ_PERMISSION );
+        }
 
-            if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+        if( xAreParamsReadable == pdTRUE )
+        {
+            if( ( ( pxParams->uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 ) &&
+                ( pxParams->uxBitsToWaitFor != 0 )
+                #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+                    && ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( pxParams->xTicksToWait != 0 ) ) )
+                #endif
+                )
             {
-                xCallingTaskIsAuthorizedToAccessEventGroup = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                lIndex = ( int32_t ) ( pxParams->xEventGroup );
 
-                if( xCallingTaskIsAuthorizedToAccessEventGroup == pdTRUE )
+                if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
                 {
-                    xInternalEventGroupHandle = MPU_GetEventGroupHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                    xCallingTaskIsAuthorizedToAccessEventGroup = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-                    if( xInternalEventGroupHandle != NULL )
+                    if( xCallingTaskIsAuthorizedToAccessEventGroup == pdTRUE )
                     {
-                        xReturn = xEventGroupWaitBits( xInternalEventGroupHandle, uxBitsToWaitFor, xClearOnExit, xWaitForAllBits, xTicksToWait );
+                        xInternalEventGroupHandle = MPU_GetEventGroupHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                        if( xInternalEventGroupHandle != NULL )
+                        {
+                            xReturn = xEventGroupWaitBits( xInternalEventGroupHandle,
+                                                           pxParams->uxBitsToWaitFor,
+                                                           pxParams->xClearOnExit,
+                                                           pxParams->xWaitForAllBits,
+                                                           pxParams->xTicksToWait );
+                        }
                     }
                 }
             }
@@ -4764,5 +4887,245 @@
     #endif
 /*-----------------------------------------------------------*/
 
+/**
+ * @brief Array of system call implementation functions.
+ *
+ * The index in the array MUST match the corresponding system call number
+ * defined in mpu_wrappers.h.
+ */
+    PRIVILEGED_DATA UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ] =
+    {
+        #if ( configUSE_TASK_NOTIFICATIONS == 1 )
+            ( UBaseType_t ) MPU_xTaskGenericNotifyImpl,                     /* SYSTEM_CALL_xTaskGenericNotify. */
+            ( UBaseType_t ) MPU_xTaskGenericNotifyWaitImpl,                 /* SYSTEM_CALL_xTaskGenericNotifyWait. */
+        #else
+            ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_xTaskGenericNotify. */
+            ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_xTaskGenericNotifyWait. */
+        #endif
+
+        #if ( configUSE_TIMERS == 1 )
+            ( UBaseType_t ) MPU_xTimerGenericCommandFromTaskImpl,           /* SYSTEM_CALL_xTimerGenericCommandFromTask. */
+        #else
+            ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_xTimerGenericCommandFromTask. */
+        #endif
+
+        ( UBaseType_t ) MPU_xEventGroupWaitBitsImpl,                        /* SYSTEM_CALL_xEventGroupWaitBits. */
+
+        /* The system calls above this line take 5 parameters. */
+
+        #if ( INCLUDE_xTaskDelayUntil == 1 )
+            ( UBaseType_t ) MPU_xTaskDelayUntilImpl,                        /* SYSTEM_CALL_xTaskDelayUntil. */
+        #else
+            ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_xTaskDelayUntil. */
+        #endif
+
+        #if ( INCLUDE_xTaskAbortDelay == 1 )
+            ( UBaseType_t ) MPU_xTaskAbortDelayImpl,                        /* SYSTEM_CALL_xTaskAbortDelay. */
+        #else
+            ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_xTaskAbortDelay. */
+        #endif
+
+        #if ( INCLUDE_vTaskDelay == 1 )
+            ( UBaseType_t ) MPU_vTaskDelayImpl,                             /* SYSTEM_CALL_vTaskDelay. */
+        #else
+            ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_vTaskDelay. */
+        #endif
+
+        #if ( INCLUDE_uxTaskPriorityGet == 1 )
+            ( UBaseType_t ) MPU_uxTaskPriorityGetImpl,                      /* SYSTEM_CALL_uxTaskPriorityGet. */
+        #else
+            ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_uxTaskPriorityGet. */
+        #endif
+
+        #if ( INCLUDE_eTaskGetState == 1 )
+            ( UBaseType_t ) MPU_eTaskGetStateImpl,                          /* SYSTEM_CALL_eTaskGetState. */
+        #else
+            ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_eTaskGetState. */
+        #endif
+
+        #if ( configUSE_TRACE_FACILITY == 1 )
+            ( UBaseType_t ) MPU_vTaskGetInfoImpl,                           /* SYSTEM_CALL_vTaskGetInfo. */
+        #else
+            ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_vTaskGetInfo. */
+        #endif
+
+        #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
+            ( UBaseType_t ) MPU_xTaskGetIdleTaskHandleImpl,                 /* SYSTEM_CALL_xTaskGetIdleTaskHandle. */
+        #else
+            ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_xTaskGetIdleTaskHandle. */
+        #endif
+
+        #if ( INCLUDE_vTaskSuspend == 1 )
+            ( UBaseType_t ) MPU_vTaskSuspendImpl,                           /* SYSTEM_CALL_vTaskSuspend. */
+            ( UBaseType_t ) MPU_vTaskResumeImpl,                            /* SYSTEM_CALL_vTaskResume. */
+        #else
+            ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_vTaskSuspend. */
+            ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_vTaskResume. */
+        #endif
+
+        ( UBaseType_t ) MPU_xTaskGetTickCountImpl,                          /* SYSTEM_CALL_xTaskGetTickCount. */
+        ( UBaseType_t ) MPU_uxTaskGetNumberOfTasksImpl,                     /* SYSTEM_CALL_uxTaskGetNumberOfTasks. */
+
+        #if ( configGENERATE_RUN_TIME_STATS == 1 )
+            ( UBaseType_t ) MPU_ulTaskGetRunTimeCounterImpl,                /* SYSTEM_CALL_ulTaskGetRunTimeCounter. */
+            ( UBaseType_t ) MPU_ulTaskGetRunTimePercentImpl,                /* SYSTEM_CALL_ulTaskGetRunTimePercent. */
+        #else
+            ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_ulTaskGetRunTimeCounter. */
+            ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_ulTaskGetRunTimePercent. */
+        #endif
+
+        #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+            ( UBaseType_t ) MPU_ulTaskGetIdleRunTimePercentImpl,            /* SYSTEM_CALL_ulTaskGetIdleRunTimePercent. */
+            ( UBaseType_t ) MPU_ulTaskGetIdleRunTimeCounterImpl,            /* SYSTEM_CALL_ulTaskGetIdleRunTimeCounter. */
+        #else
+            ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_ulTaskGetIdleRunTimePercent. */
+            ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_ulTaskGetIdleRunTimeCounter. */
+        #endif
+
+        #if ( configUSE_APPLICATION_TASK_TAG == 1 )
+            ( UBaseType_t ) MPU_vTaskSetApplicationTaskTagImpl,             /* SYSTEM_CALL_vTaskSetApplicationTaskTag. */
+            ( UBaseType_t ) MPU_xTaskGetApplicationTaskTagImpl,             /* SYSTEM_CALL_xTaskGetApplicationTaskTag. */
+        #else
+            ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_vTaskSetApplicationTaskTag. */
+            ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_xTaskGetApplicationTaskTag. */
+        #endif
+
+        #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+            ( UBaseType_t ) MPU_vTaskSetThreadLocalStoragePointerImpl,      /* SYSTEM_CALL_vTaskSetThreadLocalStoragePointer. */
+            ( UBaseType_t ) MPU_pvTaskGetThreadLocalStoragePointerImpl,     /* SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer. */
+        #else
+            ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_vTaskSetThreadLocalStoragePointer. */
+            ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer. */
+        #endif
+
+        #if ( configUSE_TRACE_FACILITY == 1 )
+            ( UBaseType_t ) MPU_uxTaskGetSystemStateImpl,                   /* SYSTEM_CALL_uxTaskGetSystemState. */
+        #else
+            ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_uxTaskGetSystemState. */
+        #endif
+
+        #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
+            ( UBaseType_t ) MPU_uxTaskGetStackHighWaterMarkImpl,            /* SYSTEM_CALL_uxTaskGetStackHighWaterMark. */
+        #else
+            ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_uxTaskGetStackHighWaterMark. */
+        #endif
+
+        #if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
+            ( UBaseType_t ) MPU_uxTaskGetStackHighWaterMark2Impl,           /* SYSTEM_CALL_uxTaskGetStackHighWaterMark2. */
+        #else
+            ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_uxTaskGetStackHighWaterMark2. */
+        #endif
+
+        #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
+            ( UBaseType_t ) MPU_xTaskGetCurrentTaskHandleImpl,              /* SYSTEM_CALL_xTaskGetCurrentTaskHandle. */
+        #else
+            ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_xTaskGetCurrentTaskHandle. */
+        #endif
+
+        #if ( INCLUDE_xTaskGetSchedulerState == 1 )
+            ( UBaseType_t ) MPU_xTaskGetSchedulerStateImpl,                 /* SYSTEM_CALL_xTaskGetSchedulerState. */
+        #else
+            ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_xTaskGetSchedulerState. */
+        #endif
+
+        ( UBaseType_t ) MPU_vTaskSetTimeOutStateImpl,                       /* SYSTEM_CALL_vTaskSetTimeOutState. */
+        ( UBaseType_t ) MPU_xTaskCheckForTimeOutImpl,                       /* SYSTEM_CALL_xTaskCheckForTimeOut. */
+
+        #if ( configUSE_TASK_NOTIFICATIONS == 1 )
+            ( UBaseType_t ) MPU_ulTaskGenericNotifyTakeImpl,                /* SYSTEM_CALL_ulTaskGenericNotifyTake. */
+            ( UBaseType_t ) MPU_xTaskGenericNotifyStateClearImpl,           /* SYSTEM_CALL_xTaskGenericNotifyStateClear. */
+            ( UBaseType_t ) MPU_ulTaskGenericNotifyValueClearImpl,          /* SYSTEM_CALL_ulTaskGenericNotifyValueClear. */
+        #else
+            ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_ulTaskGenericNotifyTake. */
+            ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_xTaskGenericNotifyStateClear. */
+            ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_ulTaskGenericNotifyValueClear. */
+        #endif
+
+        ( UBaseType_t ) MPU_xQueueGenericSendImpl,                          /* SYSTEM_CALL_xQueueGenericSend. */
+        ( UBaseType_t ) MPU_uxQueueMessagesWaitingImpl,                     /* SYSTEM_CALL_uxQueueMessagesWaiting. */
+        ( UBaseType_t ) MPU_uxQueueSpacesAvailableImpl,                     /* SYSTEM_CALL_uxQueueSpacesAvailable. */
+        ( UBaseType_t ) MPU_xQueueReceiveImpl,                              /* SYSTEM_CALL_xQueueReceive. */
+        ( UBaseType_t ) MPU_xQueuePeekImpl,                                 /* SYSTEM_CALL_xQueuePeek. */
+        ( UBaseType_t ) MPU_xQueueSemaphoreTakeImpl,                        /* SYSTEM_CALL_xQueueSemaphoreTake. */
+
+        #if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+            ( UBaseType_t ) MPU_xQueueGetMutexHolderImpl,                   /* SYSTEM_CALL_xQueueGetMutexHolder. */
+        #else
+            ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_xQueueGetMutexHolder. */
+        #endif
+
+        #if ( configUSE_RECURSIVE_MUTEXES == 1 )
+            ( UBaseType_t ) MPU_xQueueTakeMutexRecursiveImpl,               /* SYSTEM_CALL_xQueueTakeMutexRecursive. */
+            ( UBaseType_t ) MPU_xQueueGiveMutexRecursiveImpl,               /* SYSTEM_CALL_xQueueGiveMutexRecursive. */
+        #else
+            ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_xQueueTakeMutexRecursive. */
+            ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_xQueueGiveMutexRecursive. */
+        #endif
+
+        #if ( configUSE_QUEUE_SETS == 1 )
+            ( UBaseType_t ) MPU_xQueueSelectFromSetImpl,                    /* SYSTEM_CALL_xQueueSelectFromSet. */
+            ( UBaseType_t ) MPU_xQueueAddToSetImpl,                         /* SYSTEM_CALL_xQueueAddToSet. */
+        #else
+            ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_xQueueSelectFromSet. */
+            ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_xQueueAddToSet. */
+        #endif
+
+        #if configQUEUE_REGISTRY_SIZE > 0
+            ( UBaseType_t ) MPU_vQueueAddToRegistryImpl,                    /* SYSTEM_CALL_vQueueAddToRegistry. */
+            ( UBaseType_t ) MPU_vQueueUnregisterQueueImpl,                  /* SYSTEM_CALL_vQueueUnregisterQueue. */
+            ( UBaseType_t ) MPU_pcQueueGetNameImpl,                         /* SYSTEM_CALL_pcQueueGetName. */
+        #else
+            ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_vQueueAddToRegistry. */
+            ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_vQueueUnregisterQueue. */
+            ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_pcQueueGetName. */
+        #endif
+
+        #if ( configUSE_TIMERS == 1 )
+            ( UBaseType_t ) MPU_pvTimerGetTimerIDImpl,                      /* SYSTEM_CALL_pvTimerGetTimerID. */
+            ( UBaseType_t ) MPU_vTimerSetTimerIDImpl,                       /* SYSTEM_CALL_vTimerSetTimerID. */
+            ( UBaseType_t ) MPU_xTimerIsTimerActiveImpl,                    /* SYSTEM_CALL_xTimerIsTimerActive. */
+            ( UBaseType_t ) MPU_xTimerGetTimerDaemonTaskHandleImpl,         /* SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle. */
+            ( UBaseType_t ) MPU_pcTimerGetNameImpl,                         /* SYSTEM_CALL_pcTimerGetName. */
+            ( UBaseType_t ) MPU_vTimerSetReloadModeImpl,                    /* SYSTEM_CALL_vTimerSetReloadMode. */
+            ( UBaseType_t ) MPU_xTimerGetReloadModeImpl,                    /* SYSTEM_CALL_xTimerGetReloadMode. */
+            ( UBaseType_t ) MPU_uxTimerGetReloadModeImpl,                   /* SYSTEM_CALL_uxTimerGetReloadMode. */
+            ( UBaseType_t ) MPU_xTimerGetPeriodImpl,                        /* SYSTEM_CALL_xTimerGetPeriod. */
+            ( UBaseType_t ) MPU_xTimerGetExpiryTimeImpl,                    /* SYSTEM_CALL_xTimerGetExpiryTime. */
+        #else
+            ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_pvTimerGetTimerID. */
+            ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_vTimerSetTimerID. */
+            ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_xTimerIsTimerActive. */
+            ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle. */
+            ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_pcTimerGetName. */
+            ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_vTimerSetReloadMode. */
+            ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_xTimerGetReloadMode. */
+            ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_uxTimerGetReloadMode. */
+            ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_xTimerGetPeriod. */
+            ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_xTimerGetExpiryTime. */
+        #endif
+
+        ( UBaseType_t ) MPU_xEventGroupClearBitsImpl,                       /* SYSTEM_CALL_xEventGroupClearBits. */
+        ( UBaseType_t ) MPU_xEventGroupSetBitsImpl,                         /* SYSTEM_CALL_xEventGroupSetBits. */
+        ( UBaseType_t ) MPU_xEventGroupSyncImpl,                            /* SYSTEM_CALL_xEventGroupSync. */
+
+        #if ( configUSE_TRACE_FACILITY == 1 )
+            ( UBaseType_t ) MPU_uxEventGroupGetNumberImpl,                  /* SYSTEM_CALL_uxEventGroupGetNumber. */
+            ( UBaseType_t ) MPU_vEventGroupSetNumberImpl,                   /* SYSTEM_CALL_vEventGroupSetNumber. */
+        #else
+            ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_uxEventGroupGetNumber. */
+            ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_vEventGroupSetNumber. */
+        #endif
+
+        ( UBaseType_t ) MPU_xStreamBufferSendImpl,                          /* SYSTEM_CALL_xStreamBufferSend. */
+        ( UBaseType_t ) MPU_xStreamBufferReceiveImpl,                       /* SYSTEM_CALL_xStreamBufferReceive. */
+        ( UBaseType_t ) MPU_xStreamBufferIsFullImpl,                        /* SYSTEM_CALL_xStreamBufferIsFull. */
+        ( UBaseType_t ) MPU_xStreamBufferIsEmptyImpl,                       /* SYSTEM_CALL_xStreamBufferIsEmpty. */
+        ( UBaseType_t ) MPU_xStreamBufferSpacesAvailableImpl,               /* SYSTEM_CALL_xStreamBufferSpacesAvailable. */
+        ( UBaseType_t ) MPU_xStreamBufferBytesAvailableImpl,                /* SYSTEM_CALL_xStreamBufferBytesAvailable. */
+        ( UBaseType_t ) MPU_xStreamBufferSetTriggerLevelImpl,               /* SYSTEM_CALL_xStreamBufferSetTriggerLevel. */
+        ( UBaseType_t ) MPU_xStreamBufferNextMessageLengthBytesImpl         /* SYSTEM_CALL_xStreamBufferNextMessageLengthBytes. */
+    };
+/*-----------------------------------------------------------*/
+
 #endif /* #if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM23/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM23/non_secure/mpu_wrappers_v2_asm.c
index 00c8bcfa8..e67f3cbae 100644
--- a/portable/GCC/ARM_CM23/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM23/non_secure/mpu_wrappers_v2_asm.c
@@ -38,6 +38,8 @@
 #include "timers.h"
 #include "event_groups.h"
 #include "stream_buffer.h"
+#include "mpu_prototypes.h"
+#include "mpu_syscall_numbers.h"
 
 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
 /*-----------------------------------------------------------*/
@@ -68,11 +70,8 @@
                 " MPU_xTaskDelayUntil_Unpriv:                           \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskDelayUntilImpl                        \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory"
             );
         }
 
@@ -101,11 +100,8 @@
                 " MPU_xTaskAbortDelay_Unpriv:                           \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskAbortDelayImpl                        \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory"
             );
         }
 
@@ -134,11 +130,8 @@
                 " MPU_vTaskDelay_Unpriv:                                \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskDelayImpl                             \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory"
             );
         }
 
@@ -167,11 +160,8 @@
                 " MPU_uxTaskPriorityGet_Unpriv:                         \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskPriorityGetImpl                      \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory"
             );
         }
 
@@ -200,11 +190,8 @@
                 " MPU_eTaskGetState_Unpriv:                             \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_eTaskGetStateImpl                          \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory"
             );
         }
 
@@ -239,11 +226,8 @@
                 " MPU_vTaskGetInfo_Unpriv:                              \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskGetInfoImpl                           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory"
             );
         }
 
@@ -272,11 +256,8 @@
                 " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetIdleTaskHandleImpl                 \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory"
             );
         }
 
@@ -305,11 +286,8 @@
                 " MPU_vTaskSuspend_Unpriv:                              \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskSuspendImpl                           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory"
             );
         }
 
@@ -338,11 +316,8 @@
                 " MPU_vTaskResume_Unpriv:                               \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskResumeImpl                            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskResume ) : "memory"
             );
         }
 
@@ -369,11 +344,8 @@
             " MPU_xTaskGetTickCount_Unpriv:                         \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xTaskGetTickCountImpl                      \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -398,11 +370,8 @@
             " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_uxTaskGetNumberOfTasksImpl                 \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -429,11 +398,8 @@
                 " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetRunTimeCounterImpl                \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory"
             );
         }
 
@@ -462,11 +428,8 @@
                 " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetRunTimePercentImpl                \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory"
             );
         }
 
@@ -495,11 +458,8 @@
                 " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetIdleRunTimePercentImpl            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory"
             );
         }
 
@@ -528,11 +488,8 @@
                 " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetIdleRunTimeCounterImpl            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory"
             );
         }
 
@@ -563,11 +520,8 @@
                 " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskSetApplicationTaskTagImpl             \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory"
             );
         }
 
@@ -596,11 +550,8 @@
                 " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetApplicationTaskTagImpl             \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory"
             );
         }
 
@@ -633,11 +584,8 @@
                 " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskSetThreadLocalStoragePointerImpl      \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory"
             );
         }
 
@@ -668,11 +616,8 @@
                 " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pvTaskGetThreadLocalStoragePointerImpl     \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory"
             );
         }
 
@@ -705,11 +650,8 @@
                 " MPU_uxTaskGetSystemState_Unpriv:                      \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskGetSystemStateImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory"
             );
         }
 
@@ -738,11 +680,8 @@
                 " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskGetStackHighWaterMarkImpl            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory"
             );
         }
 
@@ -771,11 +710,8 @@
                 " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskGetStackHighWaterMark2Impl           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory"
             );
         }
 
@@ -804,11 +740,8 @@
                 " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetCurrentTaskHandleImpl              \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory"
             );
         }
 
@@ -837,11 +770,8 @@
                 " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetSchedulerStateImpl                 \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory"
             );
         }
 
@@ -868,11 +798,8 @@
             " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_vTaskSetTimeOutStateImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -899,28 +826,17 @@
             " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xTaskCheckForTimeOutImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
 
     #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                           UBaseType_t uxIndexToNotify,
-                                           uint32_t ulValue,
-                                           eNotifyAction eAction,
-                                           uint32_t * pulPreviousNotificationValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                           UBaseType_t uxIndexToNotify,
-                                           uint32_t ulValue,
-                                           eNotifyAction eAction,
-                                           uint32_t * pulPreviousNotificationValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
@@ -938,11 +854,8 @@
                 " MPU_xTaskGenericNotify_Unpriv:                        \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGenericNotifyImpl                     \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory"
             );
         }
 
@@ -951,17 +864,9 @@
 
     #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                               uint32_t ulBitsToClearOnEntry,
-                                               uint32_t ulBitsToClearOnExit,
-                                               uint32_t * pulNotificationValue,
-                                               TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                               uint32_t ulBitsToClearOnEntry,
-                                               uint32_t ulBitsToClearOnExit,
-                                               uint32_t * pulNotificationValue,
-                                               TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
@@ -979,11 +884,8 @@
                 " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGenericNotifyWaitImpl                 \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory"
             );
         }
 
@@ -1016,11 +918,8 @@
                 " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGenericNotifyTakeImpl                \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory"
             );
         }
 
@@ -1051,11 +950,8 @@
                 " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGenericNotifyStateClearImpl           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory"
             );
         }
 
@@ -1088,11 +984,8 @@
                 " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGenericNotifyValueClearImpl          \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory"
             );
         }
 
@@ -1125,11 +1018,8 @@
             " MPU_xQueueGenericSend_Unpriv:                         \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueueGenericSendImpl                      \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1154,11 +1044,8 @@
             " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_uxQueueMessagesWaitingImpl                 \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1183,11 +1070,8 @@
             " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_uxQueueSpacesAvailableImpl                 \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1216,11 +1100,8 @@
             " MPU_xQueueReceive_Unpriv:                             \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueueReceiveImpl                          \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1249,11 +1130,8 @@
             " MPU_xQueuePeek_Unpriv:                                \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueuePeekImpl                             \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1280,11 +1158,8 @@
             " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueueSemaphoreTakeImpl                    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1311,11 +1186,8 @@
                 " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueGetMutexHolderImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory"
             );
         }
 
@@ -1346,11 +1218,8 @@
                 " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueTakeMutexRecursiveImpl               \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory"
             );
         }
 
@@ -1379,11 +1248,8 @@
                 " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueGiveMutexRecursiveImpl               \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory"
             );
         }
 
@@ -1414,11 +1280,8 @@
                 " MPU_xQueueSelectFromSet_Unpriv:                       \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueSelectFromSetImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory"
             );
         }
 
@@ -1449,11 +1312,8 @@
                 " MPU_xQueueAddToSet_Unpriv:                            \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueAddToSetImpl                         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory"
             );
         }
 
@@ -1484,11 +1344,8 @@
                 " MPU_vQueueAddToRegistry_Unpriv:                       \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vQueueAddToRegistryImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory"
             );
         }
 
@@ -1517,11 +1374,8 @@
                 " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vQueueUnregisterQueueImpl                  \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory"
             );
         }
 
@@ -1550,11 +1404,8 @@
                 " MPU_pcQueueGetName_Unpriv:                            \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pcQueueGetNameImpl                         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory"
             );
         }
 
@@ -1583,11 +1434,8 @@
                 " MPU_pvTimerGetTimerID_Unpriv:                         \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pvTimerGetTimerIDImpl                      \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory"
             );
         }
 
@@ -1618,11 +1466,8 @@
                 " MPU_vTimerSetTimerID_Unpriv:                          \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTimerSetTimerIDImpl                       \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory"
             );
         }
 
@@ -1651,11 +1496,8 @@
                 " MPU_xTimerIsTimerActive_Unpriv:                       \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerIsTimerActiveImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory"
             );
         }
 
@@ -1684,11 +1526,8 @@
                 " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetTimerDaemonTaskHandleImpl         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory"
             );
         }
 
@@ -1697,17 +1536,9 @@
 
     #if ( configUSE_TIMERS == 1 )
 
-        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                                     const BaseType_t xCommandID,
-                                                     const TickType_t xOptionalValue,
-                                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                                     const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                                     const BaseType_t xCommandID,
-                                                     const TickType_t xOptionalValue,
-                                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                                     const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
@@ -1725,11 +1556,8 @@
                 " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
                 "     pop {r0, r1}                                              \n"
                 "     svc %0                                                    \n"
-                "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
-                "     svc %1                                                    \n"
-                "     bx lr                                                     \n"
                 "                                                               \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory"
             );
         }
 
@@ -1758,11 +1586,8 @@
                 " MPU_pcTimerGetName_Unpriv:                            \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pcTimerGetNameImpl                         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory"
             );
         }
 
@@ -1793,11 +1618,8 @@
                 " MPU_vTimerSetReloadMode_Unpriv:                       \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTimerSetReloadModeImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory"
             );
         }
 
@@ -1826,11 +1648,8 @@
                 " MPU_xTimerGetReloadMode_Unpriv:                       \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetReloadModeImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory"
             );
         }
 
@@ -1859,11 +1678,8 @@
                 " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTimerGetReloadModeImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory"
             );
         }
 
@@ -1892,11 +1708,8 @@
                 " MPU_xTimerGetPeriod_Unpriv:                           \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetPeriodImpl                        \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory"
             );
         }
 
@@ -1925,28 +1738,17 @@
                 " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetExpiryTimeImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory"
             );
         }
 
     #endif /* if ( configUSE_TIMERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
-                                         const EventBits_t uxBitsToWaitFor,
-                                         const BaseType_t xClearOnExit,
-                                         const BaseType_t xWaitForAllBits,
-                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
-                                         const EventBits_t uxBitsToWaitFor,
-                                         const BaseType_t xClearOnExit,
-                                         const BaseType_t xWaitForAllBits,
-                                         TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
     {
         __asm volatile
         (
@@ -1964,11 +1766,8 @@
             " MPU_xEventGroupWaitBits_Unpriv:                       \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupWaitBitsImpl                    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1995,11 +1794,8 @@
             " MPU_xEventGroupClearBits_Unpriv:                      \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupClearBitsImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2026,11 +1822,8 @@
             " MPU_xEventGroupSetBits_Unpriv:                        \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupSetBitsImpl                     \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2061,11 +1854,8 @@
             " MPU_xEventGroupSync_Unpriv:                           \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupSyncImpl                        \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2092,11 +1882,8 @@
                 " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxEventGroupGetNumberImpl                  \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory"
             );
         }
 
@@ -2127,11 +1914,8 @@
                 " MPU_vEventGroupSetNumber_Unpriv:                      \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vEventGroupSetNumberImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory"
             );
         }
 
@@ -2164,11 +1948,8 @@
             " MPU_xStreamBufferSend_Unpriv:                         \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferSendImpl                      \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2199,11 +1980,8 @@
             " MPU_xStreamBufferReceive_Unpriv:                      \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferReceiveImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2228,11 +2006,8 @@
             " MPU_xStreamBufferIsFull_Unpriv:                       \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferIsFullImpl                    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2257,11 +2032,8 @@
             " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferIsEmptyImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2286,11 +2058,8 @@
             " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferSpacesAvailableImpl           \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2315,11 +2084,8 @@
             " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferBytesAvailableImpl            \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2346,11 +2112,8 @@
             " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferSetTriggerLevelImpl           \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2375,11 +2138,8 @@
             " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferNextMessageLengthBytesImpl    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM23/non_secure/port.c b/portable/GCC/ARM_CM23/non_secure/port.c
index 52d68d3ea..6a3877894 100644
--- a/portable/GCC/ARM_CM23/non_secure/port.c
+++ b/portable/GCC/ARM_CM23/non_secure/port.c
@@ -35,8 +35,9 @@
 #include "FreeRTOS.h"
 #include "task.h"
 
-/* MPU wrappers includes. */
+/* MPU includes. */
 #include "mpu_wrappers.h"
+#include "mpu_syscall_numbers.h"
 
 /* Portasm includes. */
 #include "portasm.h"
@@ -436,29 +437,22 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
  * @brief Sets up the system call stack so that upon returning from
  * SVC, the system call stack is used.
  *
- * It is used for the system calls with up to 4 parameters.
- *
  * @param pulTaskStack The current SP when the SVC was raised.
  * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ * @param ucSystemCallNumber The system call number of the system call.
  */
     void vSystemCallEnter( uint32_t * pulTaskStack,
-                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
+                           uint32_t ulLR,
+                           uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
- * @brief Sets up the system call stack so that upon returning from
- * SVC, the system call stack is used.
- *
- * It is used for the system calls with 5 parameters.
- *
- * @param pulTaskStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ * @brief Raise SVC for exiting from a system call.
  */
-    void vSystemCallEnter_1( uint32_t * pulTaskStack,
-                             uint32_t ulLR ) PRIVILEGED_FUNCTION;
+    void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
@@ -488,6 +482,15 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+/**
+ * @brief This variable is set to pdTRUE when the scheduler is started.
+ */
+    PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
+
+#endif
+
 /**
  * @brief Each task maintains its own interrupt status in the critical nesting
  * variable.
@@ -1134,15 +1137,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     void vSystemCallEnter( uint32_t * pulTaskStack,
-                           uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
+                           uint32_t ulLR,
+                           uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */
     {
         extern TaskHandle_t pxCurrentTCB;
+        extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ];
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulSystemCallStack;
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
-
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __syscalls_flash_start__;
@@ -1154,17 +1158,27 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         #endif /* #if defined( __ARMCC_VERSION ) */
 
         ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
 
-        /* If the request did not come from the system call section, do nothing. */
+        /* Checks:
+         * 1. SVC is raised from the system call section (i.e. application is
+         *    not raising SVC directly).
+         * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as
+         *    it is non-NULL only during the execution of a system call (i.e.
+         *    between system call enter and exit).
+         * 3. System call is not for a kernel API disabled by the configuration
+         *    in FreeRTOSConfig.h.
+         * 4. We do not need to check that ucSystemCallNumber is within range
+         *    because the assembly SVC handler checks that before calling
+         *    this function.
+         */
         if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) &&
+            ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) &&
+            ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) )
         {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
             pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
 
-            /* This is not NULL only for the duration of the system call. */
-            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
-
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
@@ -1198,9 +1212,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 pulSystemCallStack[ i ] = pulTaskStack[ i ];
             }
 
-            /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
-             * restore it when we exit from the system call. */
+            /* Store the value of the Link Register before the SVC was raised.
+             * It contains the address of the caller of the System Call entry
+             * point (i.e. the caller of the MPU_<API>). We need to restore it
+             * when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            /* Store the value of the PSPLIM register before the SVC was raised.
+             * We need to restore it when we exit from the system call. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
             {
                 __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
@@ -1215,6 +1233,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             }
             #endif
 
+            /* Start executing the system call upon returning from this handler. */
+            pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
+            /* Raise a request to exit from the system call upon finishing the
+             * system call. */
+            pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit;
+
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
             pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
@@ -1251,127 +1275,9 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    void vSystemCallEnter_1( uint32_t * pulTaskStack,
-                             uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
+    void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */
     {
-        extern TaskHandle_t pxCurrentTCB;
-        xMPU_SETTINGS * pxMpuSettings;
-        uint32_t * pulSystemCallStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-
-        #if defined( __ARMCC_VERSION )
-
-            /* Declaration when these variable are defined in code instead of being
-             * exported from linker scripts. */
-            extern uint32_t * __syscalls_flash_start__;
-            extern uint32_t * __syscalls_flash_end__;
-        #else
-            /* Declaration when these variable are exported from linker scripts. */
-            extern uint32_t __syscalls_flash_start__[];
-            extern uint32_t __syscalls_flash_end__[];
-        #endif /* #if defined( __ARMCC_VERSION ) */
-
-        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-        /* If the request did not come from the system call section, do nothing. */
-        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
-        {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
-
-            /* This is not NULL only for the duration of the system call. */
-            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
-
-            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-            {
-                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
-                {
-                    /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
-                    __asm volatile (
-                        " vpush {s0}         \n" /* Trigger lazy stacking. */
-                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                        ::: "memory"
-                        );
-                }
-                else
-                {
-                    /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
-                }
-            }
-            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
-            {
-                ulStackFrameSize = 8;
-            }
-            #endif /* configENABLE_FPU || configENABLE_MVE */
-
-            /* Make space on the system call stack for the stack frame and
-             * the parameter passed on the stack. We only need to copy one
-             * parameter but we still reserve 2 spaces to keep the stack
-             * double word aligned. */
-            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
-
-            /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
-            {
-                pulSystemCallStack[ i ] = pulTaskStack[ i ];
-            }
-
-            /* Copy the parameter which is passed the stack. */
-            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-            {
-                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
-
-                /* Record if the hardware used padding to force the stack pointer
-                 * to be double word aligned. */
-                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-            }
-            else
-            {
-                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
-
-                /* Record if the hardware used padding to force the stack pointer
-                 * to be double word aligned. */
-                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-            }
-
-            /* Store the value of the LR and PSPLIM registers before the SVC was raised.
-             * We need to restore it when we exit from the system call. */
-            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            #if ( portUSE_PSPLIM_REGISTER == 1 )
-            {
-                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-            }
-            #endif
-
-            /* Use the pulSystemCallStack in thread mode. */
-            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            #if ( portUSE_PSPLIM_REGISTER == 1 )
-            {
-                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-            }
-            #endif
-
-            /* Remember the location where we should copy the stack frame when we exit from
-             * the system call. */
-            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-            /* We ensure in pxPortInitialiseStack that the system call stack is
-             * double word aligned and therefore, there is no need of padding.
-             * Clear the bit[9] of stacked xPSR. */
-            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-            /* Raise the privilege for the duration of the system call. */
-            __asm volatile (
-                " mrs r0, control     \n" /* Obtain current control value. */
-                " movs r1, #1         \n" /* r1 = 1. */
-                " bics r0, r1         \n" /* Clear nPRIV bit. */
-                " msr control, r0     \n" /* Write back new control value. */
-                ::: "r0", "r1", "memory"
-                );
-        }
+        __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" );
     }
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@@ -1388,24 +1294,32 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
-
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
-            extern uint32_t * __syscalls_flash_start__;
-            extern uint32_t * __syscalls_flash_end__;
+            extern uint32_t * __privileged_functions_start__;
+            extern uint32_t * __privileged_functions_end__;
         #else
             /* Declaration when these variable are exported from linker scripts. */
-            extern uint32_t __syscalls_flash_start__[];
-            extern uint32_t __syscalls_flash_end__[];
+            extern uint32_t __privileged_functions_start__[];
+            extern uint32_t __privileged_functions_end__[];
         #endif /* #if defined( __ARMCC_VERSION ) */
 
         ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
+        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
 
-        /* If the request did not come from the system call section, do nothing. */
-        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+        /* Checks:
+         * 1. SVC is raised from the privileged code (i.e. application is not
+         *    raising SVC directly). This SVC is only raised from
+         *    vRequestSystemCallExit which is in the privileged code section.
+         * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL -
+         *    this means that we previously entered a system call and the
+         *    application is not attempting to exit without entering a system
+         *    call.
+         */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) &&
+            ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) )
         {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
             pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
 
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
@@ -1444,9 +1358,14 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Use the pulTaskStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
 
-            /* Restore the LR and PSPLIM to what they were at the time of
-             * system call entry. */
+            /* Return to the caller of the System Call entry point (i.e. the
+             * caller of the MPU_<API>). */
+            pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+            /* Ensure that LR has a valid value.*/
             pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+
+            /* Restore the PSPLIM register to what it was at the time of
+             * system call entry. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
             {
                 __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
@@ -1780,6 +1699,12 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     /* Initialize the critical nesting count ready for the first task. */
     ulCriticalNesting = 0;
 
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+    {
+        xSchedulerRunning = pdTRUE;
+    }
+    #endif
+
     /* Start the first task. */
     vStartFirstTask();
 
@@ -2062,7 +1987,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
 
     void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
                                          int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
@@ -2078,10 +2003,10 @@ BaseType_t xPortIsInsideInterrupt( void )
         xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit );
     }
 
-#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
 
     void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
                                           int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
@@ -2097,10 +2022,10 @@ BaseType_t xPortIsInsideInterrupt( void )
         xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit );
     }
 
-#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
 
@@ -2108,21 +2033,34 @@ BaseType_t xPortIsInsideInterrupt( void )
         {
             uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
             BaseType_t xAccessGranted = pdFALSE;
-            const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+            const xMPU_SETTINGS * xTaskMpuSettings;
 
-            ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
-            ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
-
-            if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+            if( xSchedulerRunning == pdFALSE )
             {
+                /* Grant access to all the kernel objects before the scheduler
+                 * is started. It is necessary because there is no task running
+                 * yet and therefore, we cannot use the permissions of any
+                 * task. */
                 xAccessGranted = pdTRUE;
             }
             else
             {
-                if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+                ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+                ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+                if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
                 {
                     xAccessGranted = pdTRUE;
                 }
+                else
+                {
+                    if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                    {
+                        xAccessGranted = pdTRUE;
+                    }
+                }
             }
 
             return xAccessGranted;
@@ -2141,5 +2079,5 @@ BaseType_t xPortIsInsideInterrupt( void )
 
     #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
 
-#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM23/non_secure/portasm.c b/portable/GCC/ARM_CM23/non_secure/portasm.c
index 1b41d587f..f8b37b691 100644
--- a/portable/GCC/ARM_CM23/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM23/non_secure/portasm.c
@@ -36,6 +36,9 @@
 /* Portasm includes. */
 #include "portasm.h"
 
+/* System call numbers includes. */
+#include "mpu_syscall_numbers.h"
+
 /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
  * header files. */
 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
@@ -538,7 +541,6 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             ".syntax unified                \n"
             ".extern vPortSVCHandler_C      \n"
             ".extern vSystemCallEnter       \n"
-            ".extern vSystemCallEnter_1     \n"
             ".extern vSystemCallExit        \n"
             "                               \n"
             "movs r0, #4                    \n"
@@ -553,26 +555,22 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    b route_svc                \n"
             "                               \n"
             "route_svc:                     \n"
-            "    ldr r2, [r0, #24]          \n"
-            "    subs r2, #2                \n"
-            "    ldrb r3, [r2, #0]          \n"
-            "    cmp r3, %0                 \n"
-            "    beq system_call_enter      \n"
-            "    cmp r3, %1                 \n"
-            "    beq system_call_enter_1    \n"
-            "    cmp r3, %2                 \n"
+            "    ldr r3, [r0, #24]          \n"
+            "    subs r3, #2                \n"
+            "    ldrb r2, [r3, #0]          \n"
+            "    cmp r2, %0                 \n"
+            "    blt system_call_enter      \n"
+            "    cmp r2, %1                 \n"
             "    beq system_call_exit       \n"
             "    b vPortSVCHandler_C        \n"
             "                               \n"
             "system_call_enter:             \n"
             "    b vSystemCallEnter         \n"
-            "system_call_enter_1:           \n"
-            "    b vSystemCallEnter_1       \n"
             "system_call_exit:              \n"
             "    b vSystemCallExit          \n"
             "                               \n"
             : /* No outputs. */
-            : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT )
+            : "i" ( NUM_SYSTEM_CALLS ), "i" ( portSVC_SYSTEM_CALL_EXIT )
             : "r0", "r1", "r2", "r3", "memory"
         );
     }
diff --git a/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h
index 60ef37380..672b0dbdc 100644
--- a/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h
@@ -322,14 +322,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 /**
  * @brief SVC numbers.
  */
-#define portSVC_ALLOCATE_SECURE_CONTEXT    0
-#define portSVC_FREE_SECURE_CONTEXT        1
-#define portSVC_START_SCHEDULER            2
-#define portSVC_RAISE_PRIVILEGE            3
-#define portSVC_SYSTEM_CALL_ENTER          4   /* System calls with upto 4 parameters. */
-#define portSVC_SYSTEM_CALL_ENTER_1        5   /* System calls with 5 parameters. */
-#define portSVC_SYSTEM_CALL_EXIT           6
-#define portSVC_YIELD                      7
+#define portSVC_ALLOCATE_SECURE_CONTEXT    100
+#define portSVC_FREE_SECURE_CONTEXT        101
+#define portSVC_START_SCHEDULER            102
+#define portSVC_RAISE_PRIVILEGE            103
+#define portSVC_SYSTEM_CALL_EXIT           104
+#define portSVC_YIELD                      105
 /*-----------------------------------------------------------*/
 
 /**
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.c
index 00c8bcfa8..e67f3cbae 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.c
@@ -38,6 +38,8 @@
 #include "timers.h"
 #include "event_groups.h"
 #include "stream_buffer.h"
+#include "mpu_prototypes.h"
+#include "mpu_syscall_numbers.h"
 
 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
 /*-----------------------------------------------------------*/
@@ -68,11 +70,8 @@
                 " MPU_xTaskDelayUntil_Unpriv:                           \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskDelayUntilImpl                        \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory"
             );
         }
 
@@ -101,11 +100,8 @@
                 " MPU_xTaskAbortDelay_Unpriv:                           \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskAbortDelayImpl                        \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory"
             );
         }
 
@@ -134,11 +130,8 @@
                 " MPU_vTaskDelay_Unpriv:                                \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskDelayImpl                             \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory"
             );
         }
 
@@ -167,11 +160,8 @@
                 " MPU_uxTaskPriorityGet_Unpriv:                         \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskPriorityGetImpl                      \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory"
             );
         }
 
@@ -200,11 +190,8 @@
                 " MPU_eTaskGetState_Unpriv:                             \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_eTaskGetStateImpl                          \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory"
             );
         }
 
@@ -239,11 +226,8 @@
                 " MPU_vTaskGetInfo_Unpriv:                              \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskGetInfoImpl                           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory"
             );
         }
 
@@ -272,11 +256,8 @@
                 " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetIdleTaskHandleImpl                 \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory"
             );
         }
 
@@ -305,11 +286,8 @@
                 " MPU_vTaskSuspend_Unpriv:                              \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskSuspendImpl                           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory"
             );
         }
 
@@ -338,11 +316,8 @@
                 " MPU_vTaskResume_Unpriv:                               \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskResumeImpl                            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskResume ) : "memory"
             );
         }
 
@@ -369,11 +344,8 @@
             " MPU_xTaskGetTickCount_Unpriv:                         \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xTaskGetTickCountImpl                      \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -398,11 +370,8 @@
             " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_uxTaskGetNumberOfTasksImpl                 \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -429,11 +398,8 @@
                 " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetRunTimeCounterImpl                \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory"
             );
         }
 
@@ -462,11 +428,8 @@
                 " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetRunTimePercentImpl                \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory"
             );
         }
 
@@ -495,11 +458,8 @@
                 " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetIdleRunTimePercentImpl            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory"
             );
         }
 
@@ -528,11 +488,8 @@
                 " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetIdleRunTimeCounterImpl            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory"
             );
         }
 
@@ -563,11 +520,8 @@
                 " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskSetApplicationTaskTagImpl             \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory"
             );
         }
 
@@ -596,11 +550,8 @@
                 " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetApplicationTaskTagImpl             \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory"
             );
         }
 
@@ -633,11 +584,8 @@
                 " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskSetThreadLocalStoragePointerImpl      \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory"
             );
         }
 
@@ -668,11 +616,8 @@
                 " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pvTaskGetThreadLocalStoragePointerImpl     \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory"
             );
         }
 
@@ -705,11 +650,8 @@
                 " MPU_uxTaskGetSystemState_Unpriv:                      \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskGetSystemStateImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory"
             );
         }
 
@@ -738,11 +680,8 @@
                 " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskGetStackHighWaterMarkImpl            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory"
             );
         }
 
@@ -771,11 +710,8 @@
                 " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskGetStackHighWaterMark2Impl           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory"
             );
         }
 
@@ -804,11 +740,8 @@
                 " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetCurrentTaskHandleImpl              \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory"
             );
         }
 
@@ -837,11 +770,8 @@
                 " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetSchedulerStateImpl                 \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory"
             );
         }
 
@@ -868,11 +798,8 @@
             " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_vTaskSetTimeOutStateImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -899,28 +826,17 @@
             " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xTaskCheckForTimeOutImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
 
     #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                           UBaseType_t uxIndexToNotify,
-                                           uint32_t ulValue,
-                                           eNotifyAction eAction,
-                                           uint32_t * pulPreviousNotificationValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                           UBaseType_t uxIndexToNotify,
-                                           uint32_t ulValue,
-                                           eNotifyAction eAction,
-                                           uint32_t * pulPreviousNotificationValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
@@ -938,11 +854,8 @@
                 " MPU_xTaskGenericNotify_Unpriv:                        \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGenericNotifyImpl                     \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory"
             );
         }
 
@@ -951,17 +864,9 @@
 
     #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                               uint32_t ulBitsToClearOnEntry,
-                                               uint32_t ulBitsToClearOnExit,
-                                               uint32_t * pulNotificationValue,
-                                               TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                               uint32_t ulBitsToClearOnEntry,
-                                               uint32_t ulBitsToClearOnExit,
-                                               uint32_t * pulNotificationValue,
-                                               TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
@@ -979,11 +884,8 @@
                 " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGenericNotifyWaitImpl                 \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory"
             );
         }
 
@@ -1016,11 +918,8 @@
                 " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGenericNotifyTakeImpl                \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory"
             );
         }
 
@@ -1051,11 +950,8 @@
                 " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGenericNotifyStateClearImpl           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory"
             );
         }
 
@@ -1088,11 +984,8 @@
                 " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGenericNotifyValueClearImpl          \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory"
             );
         }
 
@@ -1125,11 +1018,8 @@
             " MPU_xQueueGenericSend_Unpriv:                         \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueueGenericSendImpl                      \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1154,11 +1044,8 @@
             " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_uxQueueMessagesWaitingImpl                 \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1183,11 +1070,8 @@
             " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_uxQueueSpacesAvailableImpl                 \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1216,11 +1100,8 @@
             " MPU_xQueueReceive_Unpriv:                             \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueueReceiveImpl                          \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1249,11 +1130,8 @@
             " MPU_xQueuePeek_Unpriv:                                \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueuePeekImpl                             \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1280,11 +1158,8 @@
             " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueueSemaphoreTakeImpl                    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1311,11 +1186,8 @@
                 " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueGetMutexHolderImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory"
             );
         }
 
@@ -1346,11 +1218,8 @@
                 " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueTakeMutexRecursiveImpl               \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory"
             );
         }
 
@@ -1379,11 +1248,8 @@
                 " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueGiveMutexRecursiveImpl               \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory"
             );
         }
 
@@ -1414,11 +1280,8 @@
                 " MPU_xQueueSelectFromSet_Unpriv:                       \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueSelectFromSetImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory"
             );
         }
 
@@ -1449,11 +1312,8 @@
                 " MPU_xQueueAddToSet_Unpriv:                            \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueAddToSetImpl                         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory"
             );
         }
 
@@ -1484,11 +1344,8 @@
                 " MPU_vQueueAddToRegistry_Unpriv:                       \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vQueueAddToRegistryImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory"
             );
         }
 
@@ -1517,11 +1374,8 @@
                 " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vQueueUnregisterQueueImpl                  \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory"
             );
         }
 
@@ -1550,11 +1404,8 @@
                 " MPU_pcQueueGetName_Unpriv:                            \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pcQueueGetNameImpl                         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory"
             );
         }
 
@@ -1583,11 +1434,8 @@
                 " MPU_pvTimerGetTimerID_Unpriv:                         \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pvTimerGetTimerIDImpl                      \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory"
             );
         }
 
@@ -1618,11 +1466,8 @@
                 " MPU_vTimerSetTimerID_Unpriv:                          \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTimerSetTimerIDImpl                       \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory"
             );
         }
 
@@ -1651,11 +1496,8 @@
                 " MPU_xTimerIsTimerActive_Unpriv:                       \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerIsTimerActiveImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory"
             );
         }
 
@@ -1684,11 +1526,8 @@
                 " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetTimerDaemonTaskHandleImpl         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory"
             );
         }
 
@@ -1697,17 +1536,9 @@
 
     #if ( configUSE_TIMERS == 1 )
 
-        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                                     const BaseType_t xCommandID,
-                                                     const TickType_t xOptionalValue,
-                                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                                     const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                                     const BaseType_t xCommandID,
-                                                     const TickType_t xOptionalValue,
-                                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                                     const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
@@ -1725,11 +1556,8 @@
                 " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
                 "     pop {r0, r1}                                              \n"
                 "     svc %0                                                    \n"
-                "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
-                "     svc %1                                                    \n"
-                "     bx lr                                                     \n"
                 "                                                               \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory"
             );
         }
 
@@ -1758,11 +1586,8 @@
                 " MPU_pcTimerGetName_Unpriv:                            \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pcTimerGetNameImpl                         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory"
             );
         }
 
@@ -1793,11 +1618,8 @@
                 " MPU_vTimerSetReloadMode_Unpriv:                       \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTimerSetReloadModeImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory"
             );
         }
 
@@ -1826,11 +1648,8 @@
                 " MPU_xTimerGetReloadMode_Unpriv:                       \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetReloadModeImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory"
             );
         }
 
@@ -1859,11 +1678,8 @@
                 " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTimerGetReloadModeImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory"
             );
         }
 
@@ -1892,11 +1708,8 @@
                 " MPU_xTimerGetPeriod_Unpriv:                           \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetPeriodImpl                        \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory"
             );
         }
 
@@ -1925,28 +1738,17 @@
                 " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetExpiryTimeImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory"
             );
         }
 
     #endif /* if ( configUSE_TIMERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
-                                         const EventBits_t uxBitsToWaitFor,
-                                         const BaseType_t xClearOnExit,
-                                         const BaseType_t xWaitForAllBits,
-                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
-                                         const EventBits_t uxBitsToWaitFor,
-                                         const BaseType_t xClearOnExit,
-                                         const BaseType_t xWaitForAllBits,
-                                         TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
     {
         __asm volatile
         (
@@ -1964,11 +1766,8 @@
             " MPU_xEventGroupWaitBits_Unpriv:                       \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupWaitBitsImpl                    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1995,11 +1794,8 @@
             " MPU_xEventGroupClearBits_Unpriv:                      \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupClearBitsImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2026,11 +1822,8 @@
             " MPU_xEventGroupSetBits_Unpriv:                        \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupSetBitsImpl                     \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2061,11 +1854,8 @@
             " MPU_xEventGroupSync_Unpriv:                           \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupSyncImpl                        \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2092,11 +1882,8 @@
                 " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxEventGroupGetNumberImpl                  \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory"
             );
         }
 
@@ -2127,11 +1914,8 @@
                 " MPU_vEventGroupSetNumber_Unpriv:                      \n"
                 "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vEventGroupSetNumberImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory"
             );
         }
 
@@ -2164,11 +1948,8 @@
             " MPU_xStreamBufferSend_Unpriv:                         \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferSendImpl                      \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2199,11 +1980,8 @@
             " MPU_xStreamBufferReceive_Unpriv:                      \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferReceiveImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2228,11 +2006,8 @@
             " MPU_xStreamBufferIsFull_Unpriv:                       \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferIsFullImpl                    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2257,11 +2032,8 @@
             " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferIsEmptyImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2286,11 +2058,8 @@
             " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferSpacesAvailableImpl           \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2315,11 +2084,8 @@
             " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferBytesAvailableImpl            \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2346,11 +2112,8 @@
             " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferSetTriggerLevelImpl           \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2375,11 +2138,8 @@
             " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
             "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferNextMessageLengthBytesImpl    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
index 52d68d3ea..6a3877894 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
@@ -35,8 +35,9 @@
 #include "FreeRTOS.h"
 #include "task.h"
 
-/* MPU wrappers includes. */
+/* MPU includes. */
 #include "mpu_wrappers.h"
+#include "mpu_syscall_numbers.h"
 
 /* Portasm includes. */
 #include "portasm.h"
@@ -436,29 +437,22 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
  * @brief Sets up the system call stack so that upon returning from
  * SVC, the system call stack is used.
  *
- * It is used for the system calls with up to 4 parameters.
- *
  * @param pulTaskStack The current SP when the SVC was raised.
  * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ * @param ucSystemCallNumber The system call number of the system call.
  */
     void vSystemCallEnter( uint32_t * pulTaskStack,
-                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
+                           uint32_t ulLR,
+                           uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
- * @brief Sets up the system call stack so that upon returning from
- * SVC, the system call stack is used.
- *
- * It is used for the system calls with 5 parameters.
- *
- * @param pulTaskStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ * @brief Raise SVC for exiting from a system call.
  */
-    void vSystemCallEnter_1( uint32_t * pulTaskStack,
-                             uint32_t ulLR ) PRIVILEGED_FUNCTION;
+    void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
@@ -488,6 +482,15 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+/**
+ * @brief This variable is set to pdTRUE when the scheduler is started.
+ */
+    PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
+
+#endif
+
 /**
  * @brief Each task maintains its own interrupt status in the critical nesting
  * variable.
@@ -1134,15 +1137,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     void vSystemCallEnter( uint32_t * pulTaskStack,
-                           uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
+                           uint32_t ulLR,
+                           uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */
     {
         extern TaskHandle_t pxCurrentTCB;
+        extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ];
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulSystemCallStack;
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
-
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __syscalls_flash_start__;
@@ -1154,17 +1158,27 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         #endif /* #if defined( __ARMCC_VERSION ) */
 
         ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
 
-        /* If the request did not come from the system call section, do nothing. */
+        /* Checks:
+         * 1. SVC is raised from the system call section (i.e. application is
+         *    not raising SVC directly).
+         * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as
+         *    it is non-NULL only during the execution of a system call (i.e.
+         *    between system call enter and exit).
+         * 3. System call is not for a kernel API disabled by the configuration
+         *    in FreeRTOSConfig.h.
+         * 4. We do not need to check that ucSystemCallNumber is within range
+         *    because the assembly SVC handler checks that before calling
+         *    this function.
+         */
         if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) &&
+            ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) &&
+            ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) )
         {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
             pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
 
-            /* This is not NULL only for the duration of the system call. */
-            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
-
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
@@ -1198,9 +1212,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 pulSystemCallStack[ i ] = pulTaskStack[ i ];
             }
 
-            /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
-             * restore it when we exit from the system call. */
+            /* Store the value of the Link Register before the SVC was raised.
+             * It contains the address of the caller of the System Call entry
+             * point (i.e. the caller of the MPU_<API>). We need to restore it
+             * when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            /* Store the value of the PSPLIM register before the SVC was raised.
+             * We need to restore it when we exit from the system call. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
             {
                 __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
@@ -1215,6 +1233,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             }
             #endif
 
+            /* Start executing the system call upon returning from this handler. */
+            pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
+            /* Raise a request to exit from the system call upon finishing the
+             * system call. */
+            pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit;
+
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
             pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
@@ -1251,127 +1275,9 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    void vSystemCallEnter_1( uint32_t * pulTaskStack,
-                             uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
+    void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */
     {
-        extern TaskHandle_t pxCurrentTCB;
-        xMPU_SETTINGS * pxMpuSettings;
-        uint32_t * pulSystemCallStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-
-        #if defined( __ARMCC_VERSION )
-
-            /* Declaration when these variable are defined in code instead of being
-             * exported from linker scripts. */
-            extern uint32_t * __syscalls_flash_start__;
-            extern uint32_t * __syscalls_flash_end__;
-        #else
-            /* Declaration when these variable are exported from linker scripts. */
-            extern uint32_t __syscalls_flash_start__[];
-            extern uint32_t __syscalls_flash_end__[];
-        #endif /* #if defined( __ARMCC_VERSION ) */
-
-        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-        /* If the request did not come from the system call section, do nothing. */
-        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
-        {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
-
-            /* This is not NULL only for the duration of the system call. */
-            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
-
-            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-            {
-                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
-                {
-                    /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
-                    __asm volatile (
-                        " vpush {s0}         \n" /* Trigger lazy stacking. */
-                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                        ::: "memory"
-                        );
-                }
-                else
-                {
-                    /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
-                }
-            }
-            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
-            {
-                ulStackFrameSize = 8;
-            }
-            #endif /* configENABLE_FPU || configENABLE_MVE */
-
-            /* Make space on the system call stack for the stack frame and
-             * the parameter passed on the stack. We only need to copy one
-             * parameter but we still reserve 2 spaces to keep the stack
-             * double word aligned. */
-            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
-
-            /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
-            {
-                pulSystemCallStack[ i ] = pulTaskStack[ i ];
-            }
-
-            /* Copy the parameter which is passed the stack. */
-            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-            {
-                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
-
-                /* Record if the hardware used padding to force the stack pointer
-                 * to be double word aligned. */
-                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-            }
-            else
-            {
-                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
-
-                /* Record if the hardware used padding to force the stack pointer
-                 * to be double word aligned. */
-                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-            }
-
-            /* Store the value of the LR and PSPLIM registers before the SVC was raised.
-             * We need to restore it when we exit from the system call. */
-            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            #if ( portUSE_PSPLIM_REGISTER == 1 )
-            {
-                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-            }
-            #endif
-
-            /* Use the pulSystemCallStack in thread mode. */
-            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            #if ( portUSE_PSPLIM_REGISTER == 1 )
-            {
-                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-            }
-            #endif
-
-            /* Remember the location where we should copy the stack frame when we exit from
-             * the system call. */
-            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-            /* We ensure in pxPortInitialiseStack that the system call stack is
-             * double word aligned and therefore, there is no need of padding.
-             * Clear the bit[9] of stacked xPSR. */
-            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-            /* Raise the privilege for the duration of the system call. */
-            __asm volatile (
-                " mrs r0, control     \n" /* Obtain current control value. */
-                " movs r1, #1         \n" /* r1 = 1. */
-                " bics r0, r1         \n" /* Clear nPRIV bit. */
-                " msr control, r0     \n" /* Write back new control value. */
-                ::: "r0", "r1", "memory"
-                );
-        }
+        __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" );
     }
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@@ -1388,24 +1294,32 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
-
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
-            extern uint32_t * __syscalls_flash_start__;
-            extern uint32_t * __syscalls_flash_end__;
+            extern uint32_t * __privileged_functions_start__;
+            extern uint32_t * __privileged_functions_end__;
         #else
             /* Declaration when these variable are exported from linker scripts. */
-            extern uint32_t __syscalls_flash_start__[];
-            extern uint32_t __syscalls_flash_end__[];
+            extern uint32_t __privileged_functions_start__[];
+            extern uint32_t __privileged_functions_end__[];
         #endif /* #if defined( __ARMCC_VERSION ) */
 
         ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
+        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
 
-        /* If the request did not come from the system call section, do nothing. */
-        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+        /* Checks:
+         * 1. SVC is raised from the privileged code (i.e. application is not
+         *    raising SVC directly). This SVC is only raised from
+         *    vRequestSystemCallExit which is in the privileged code section.
+         * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL -
+         *    this means that we previously entered a system call and the
+         *    application is not attempting to exit without entering a system
+         *    call.
+         */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) &&
+            ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) )
         {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
             pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
 
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
@@ -1444,9 +1358,14 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Use the pulTaskStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
 
-            /* Restore the LR and PSPLIM to what they were at the time of
-             * system call entry. */
+            /* Return to the caller of the System Call entry point (i.e. the
+             * caller of the MPU_<API>). */
+            pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+            /* Ensure that LR has a valid value.*/
             pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+
+            /* Restore the PSPLIM register to what it was at the time of
+             * system call entry. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
             {
                 __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
@@ -1780,6 +1699,12 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     /* Initialize the critical nesting count ready for the first task. */
     ulCriticalNesting = 0;
 
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+    {
+        xSchedulerRunning = pdTRUE;
+    }
+    #endif
+
     /* Start the first task. */
     vStartFirstTask();
 
@@ -2062,7 +1987,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
 
     void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
                                          int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
@@ -2078,10 +2003,10 @@ BaseType_t xPortIsInsideInterrupt( void )
         xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit );
     }
 
-#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
 
     void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
                                           int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
@@ -2097,10 +2022,10 @@ BaseType_t xPortIsInsideInterrupt( void )
         xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit );
     }
 
-#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
 
@@ -2108,21 +2033,34 @@ BaseType_t xPortIsInsideInterrupt( void )
         {
             uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
             BaseType_t xAccessGranted = pdFALSE;
-            const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+            const xMPU_SETTINGS * xTaskMpuSettings;
 
-            ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
-            ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
-
-            if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+            if( xSchedulerRunning == pdFALSE )
             {
+                /* Grant access to all the kernel objects before the scheduler
+                 * is started. It is necessary because there is no task running
+                 * yet and therefore, we cannot use the permissions of any
+                 * task. */
                 xAccessGranted = pdTRUE;
             }
             else
             {
-                if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+                ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+                ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+                if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
                 {
                     xAccessGranted = pdTRUE;
                 }
+                else
+                {
+                    if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                    {
+                        xAccessGranted = pdTRUE;
+                    }
+                }
             }
 
             return xAccessGranted;
@@ -2141,5 +2079,5 @@ BaseType_t xPortIsInsideInterrupt( void )
 
     #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
 
-#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c b/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c
index ed4933812..5fde8342e 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c
@@ -36,6 +36,9 @@
 /* Portasm includes. */
 #include "portasm.h"
 
+/* System call numbers includes. */
+#include "mpu_syscall_numbers.h"
+
 /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
  * header files. */
 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
@@ -478,7 +481,6 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             ".syntax unified                \n"
             ".extern vPortSVCHandler_C      \n"
             ".extern vSystemCallEnter       \n"
-            ".extern vSystemCallEnter_1     \n"
             ".extern vSystemCallExit        \n"
             "                               \n"
             "movs r0, #4                    \n"
@@ -493,26 +495,22 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    b route_svc                \n"
             "                               \n"
             "route_svc:                     \n"
-            "    ldr r2, [r0, #24]          \n"
-            "    subs r2, #2                \n"
-            "    ldrb r3, [r2, #0]          \n"
-            "    cmp r3, %0                 \n"
-            "    beq system_call_enter      \n"
-            "    cmp r3, %1                 \n"
-            "    beq system_call_enter_1    \n"
-            "    cmp r3, %2                 \n"
+            "    ldr r3, [r0, #24]          \n"
+            "    subs r3, #2                \n"
+            "    ldrb r2, [r3, #0]          \n"
+            "    cmp r2, %0                 \n"
+            "    blt system_call_enter      \n"
+            "    cmp r2, %1                 \n"
             "    beq system_call_exit       \n"
             "    b vPortSVCHandler_C        \n"
             "                               \n"
             "system_call_enter:             \n"
             "    b vSystemCallEnter         \n"
-            "system_call_enter_1:           \n"
-            "    b vSystemCallEnter_1       \n"
             "system_call_exit:              \n"
             "    b vSystemCallExit          \n"
             "                               \n"
             : /* No outputs. */
-            : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT )
+            : "i" ( NUM_SYSTEM_CALLS ), "i" ( portSVC_SYSTEM_CALL_EXIT )
             : "r0", "r1", "r2", "r3", "memory"
         );
     }
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h
index 60ef37380..672b0dbdc 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h
@@ -322,14 +322,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 /**
  * @brief SVC numbers.
  */
-#define portSVC_ALLOCATE_SECURE_CONTEXT    0
-#define portSVC_FREE_SECURE_CONTEXT        1
-#define portSVC_START_SCHEDULER            2
-#define portSVC_RAISE_PRIVILEGE            3
-#define portSVC_SYSTEM_CALL_ENTER          4   /* System calls with upto 4 parameters. */
-#define portSVC_SYSTEM_CALL_ENTER_1        5   /* System calls with 5 parameters. */
-#define portSVC_SYSTEM_CALL_EXIT           6
-#define portSVC_YIELD                      7
+#define portSVC_ALLOCATE_SECURE_CONTEXT    100
+#define portSVC_FREE_SECURE_CONTEXT        101
+#define portSVC_START_SCHEDULER            102
+#define portSVC_RAISE_PRIVILEGE            103
+#define portSVC_SYSTEM_CALL_EXIT           104
+#define portSVC_YIELD                      105
 /*-----------------------------------------------------------*/
 
 /**
diff --git a/portable/GCC/ARM_CM33/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM33/non_secure/mpu_wrappers_v2_asm.c
index d1fbdc0e5..4cb310afd 100644
--- a/portable/GCC/ARM_CM33/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM33/non_secure/mpu_wrappers_v2_asm.c
@@ -38,6 +38,8 @@
 #include "timers.h"
 #include "event_groups.h"
 #include "stream_buffer.h"
+#include "mpu_prototypes.h"
+#include "mpu_syscall_numbers.h"
 
 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
 /*-----------------------------------------------------------*/
@@ -67,11 +69,8 @@
                 " MPU_xTaskDelayUntil_Unpriv:                           \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskDelayUntilImpl                        \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory"
             );
         }
 
@@ -99,11 +98,8 @@
                 " MPU_xTaskAbortDelay_Unpriv:                           \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskAbortDelayImpl                        \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory"
             );
         }
 
@@ -131,11 +127,8 @@
                 " MPU_vTaskDelay_Unpriv:                                \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskDelayImpl                             \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory"
             );
         }
 
@@ -163,11 +156,8 @@
                 " MPU_uxTaskPriorityGet_Unpriv:                         \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskPriorityGetImpl                      \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory"
             );
         }
 
@@ -195,11 +185,8 @@
                 " MPU_eTaskGetState_Unpriv:                             \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_eTaskGetStateImpl                          \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory"
             );
         }
 
@@ -233,11 +220,8 @@
                 " MPU_vTaskGetInfo_Unpriv:                              \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskGetInfoImpl                           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory"
             );
         }
 
@@ -265,11 +249,8 @@
                 " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetIdleTaskHandleImpl                 \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory"
             );
         }
 
@@ -297,11 +278,8 @@
                 " MPU_vTaskSuspend_Unpriv:                              \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskSuspendImpl                           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory"
             );
         }
 
@@ -329,11 +307,8 @@
                 " MPU_vTaskResume_Unpriv:                               \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskResumeImpl                            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskResume ) : "memory"
             );
         }
 
@@ -359,11 +334,8 @@
             " MPU_xTaskGetTickCount_Unpriv:                         \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xTaskGetTickCountImpl                      \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -387,11 +359,8 @@
             " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_uxTaskGetNumberOfTasksImpl                 \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -417,11 +386,8 @@
                 " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetRunTimeCounterImpl                \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory"
             );
         }
 
@@ -449,11 +415,8 @@
                 " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetRunTimePercentImpl                \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory"
             );
         }
 
@@ -481,11 +444,8 @@
                 " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetIdleRunTimePercentImpl            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory"
             );
         }
 
@@ -513,11 +473,8 @@
                 " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetIdleRunTimeCounterImpl            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory"
             );
         }
 
@@ -547,11 +504,8 @@
                 " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskSetApplicationTaskTagImpl             \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory"
             );
         }
 
@@ -579,11 +533,8 @@
                 " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetApplicationTaskTagImpl             \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory"
             );
         }
 
@@ -615,11 +566,8 @@
                 " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskSetThreadLocalStoragePointerImpl      \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory"
             );
         }
 
@@ -649,11 +597,8 @@
                 " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pvTaskGetThreadLocalStoragePointerImpl     \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory"
             );
         }
 
@@ -685,11 +630,8 @@
                 " MPU_uxTaskGetSystemState_Unpriv:                      \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskGetSystemStateImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory"
             );
         }
 
@@ -717,11 +659,8 @@
                 " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskGetStackHighWaterMarkImpl            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory"
             );
         }
 
@@ -749,11 +688,8 @@
                 " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskGetStackHighWaterMark2Impl           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory"
             );
         }
 
@@ -781,11 +717,8 @@
                 " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetCurrentTaskHandleImpl              \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory"
             );
         }
 
@@ -813,11 +746,8 @@
                 " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetSchedulerStateImpl                 \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory"
             );
         }
 
@@ -843,11 +773,8 @@
             " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_vTaskSetTimeOutStateImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -873,28 +800,17 @@
             " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xTaskCheckForTimeOutImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
 
     #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                           UBaseType_t uxIndexToNotify,
-                                           uint32_t ulValue,
-                                           eNotifyAction eAction,
-                                           uint32_t * pulPreviousNotificationValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                           UBaseType_t uxIndexToNotify,
-                                           uint32_t ulValue,
-                                           eNotifyAction eAction,
-                                           uint32_t * pulPreviousNotificationValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
@@ -911,11 +827,8 @@
                 " MPU_xTaskGenericNotify_Unpriv:                        \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGenericNotifyImpl                     \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory"
             );
         }
 
@@ -924,17 +837,9 @@
 
     #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                               uint32_t ulBitsToClearOnEntry,
-                                               uint32_t ulBitsToClearOnExit,
-                                               uint32_t * pulNotificationValue,
-                                               TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                               uint32_t ulBitsToClearOnEntry,
-                                               uint32_t ulBitsToClearOnExit,
-                                               uint32_t * pulNotificationValue,
-                                               TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
@@ -951,11 +856,8 @@
                 " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGenericNotifyWaitImpl                 \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory"
             );
         }
 
@@ -987,11 +889,8 @@
                 " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGenericNotifyTakeImpl                \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory"
             );
         }
 
@@ -1021,11 +920,8 @@
                 " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGenericNotifyStateClearImpl           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory"
             );
         }
 
@@ -1057,11 +953,8 @@
                 " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGenericNotifyValueClearImpl          \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory"
             );
         }
 
@@ -1093,11 +986,8 @@
             " MPU_xQueueGenericSend_Unpriv:                         \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueueGenericSendImpl                      \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1121,11 +1011,8 @@
             " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_uxQueueMessagesWaitingImpl                 \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1149,11 +1036,8 @@
             " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_uxQueueSpacesAvailableImpl                 \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1181,11 +1065,8 @@
             " MPU_xQueueReceive_Unpriv:                             \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueueReceiveImpl                          \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1213,11 +1094,8 @@
             " MPU_xQueuePeek_Unpriv:                                \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueuePeekImpl                             \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1243,11 +1121,8 @@
             " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueueSemaphoreTakeImpl                    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1273,11 +1148,8 @@
                 " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueGetMutexHolderImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory"
             );
         }
 
@@ -1307,11 +1179,8 @@
                 " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueTakeMutexRecursiveImpl               \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory"
             );
         }
 
@@ -1339,11 +1208,8 @@
                 " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueGiveMutexRecursiveImpl               \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory"
             );
         }
 
@@ -1373,11 +1239,8 @@
                 " MPU_xQueueSelectFromSet_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueSelectFromSetImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory"
             );
         }
 
@@ -1407,11 +1270,8 @@
                 " MPU_xQueueAddToSet_Unpriv:                            \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueAddToSetImpl                         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory"
             );
         }
 
@@ -1441,11 +1301,8 @@
                 " MPU_vQueueAddToRegistry_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vQueueAddToRegistryImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory"
             );
         }
 
@@ -1473,11 +1330,8 @@
                 " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vQueueUnregisterQueueImpl                  \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory"
             );
         }
 
@@ -1505,11 +1359,8 @@
                 " MPU_pcQueueGetName_Unpriv:                            \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pcQueueGetNameImpl                         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory"
             );
         }
 
@@ -1537,11 +1388,8 @@
                 " MPU_pvTimerGetTimerID_Unpriv:                         \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pvTimerGetTimerIDImpl                      \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory"
             );
         }
 
@@ -1571,11 +1419,8 @@
                 " MPU_vTimerSetTimerID_Unpriv:                          \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTimerSetTimerIDImpl                       \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory"
             );
         }
 
@@ -1603,11 +1448,8 @@
                 " MPU_xTimerIsTimerActive_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerIsTimerActiveImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory"
             );
         }
 
@@ -1635,11 +1477,8 @@
                 " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetTimerDaemonTaskHandleImpl         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory"
             );
         }
 
@@ -1648,17 +1487,9 @@
 
     #if ( configUSE_TIMERS == 1 )
 
-        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                                     const BaseType_t xCommandID,
-                                                     const TickType_t xOptionalValue,
-                                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                                     const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                                     const BaseType_t xCommandID,
-                                                     const TickType_t xOptionalValue,
-                                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                                     const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
@@ -1675,11 +1506,8 @@
                 " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
                 "     pop {r0}                                                  \n"
                 "     svc %0                                                    \n"
-                "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
-                "     svc %1                                                    \n"
-                "     bx lr                                                     \n"
                 "                                                               \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory"
             );
         }
 
@@ -1707,11 +1535,8 @@
                 " MPU_pcTimerGetName_Unpriv:                            \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pcTimerGetNameImpl                         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory"
             );
         }
 
@@ -1741,11 +1566,8 @@
                 " MPU_vTimerSetReloadMode_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTimerSetReloadModeImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory"
             );
         }
 
@@ -1773,11 +1595,8 @@
                 " MPU_xTimerGetReloadMode_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetReloadModeImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory"
             );
         }
 
@@ -1805,11 +1624,8 @@
                 " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTimerGetReloadModeImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory"
             );
         }
 
@@ -1837,11 +1653,8 @@
                 " MPU_xTimerGetPeriod_Unpriv:                           \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetPeriodImpl                        \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory"
             );
         }
 
@@ -1869,28 +1682,17 @@
                 " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetExpiryTimeImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory"
             );
         }
 
     #endif /* if ( configUSE_TIMERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
-                                         const EventBits_t uxBitsToWaitFor,
-                                         const BaseType_t xClearOnExit,
-                                         const BaseType_t xWaitForAllBits,
-                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
-                                         const EventBits_t uxBitsToWaitFor,
-                                         const BaseType_t xClearOnExit,
-                                         const BaseType_t xWaitForAllBits,
-                                         TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
     {
         __asm volatile
         (
@@ -1907,11 +1709,8 @@
             " MPU_xEventGroupWaitBits_Unpriv:                       \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupWaitBitsImpl                    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1937,11 +1736,8 @@
             " MPU_xEventGroupClearBits_Unpriv:                      \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupClearBitsImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1967,11 +1763,8 @@
             " MPU_xEventGroupSetBits_Unpriv:                        \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupSetBitsImpl                     \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2001,11 +1794,8 @@
             " MPU_xEventGroupSync_Unpriv:                           \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupSyncImpl                        \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2031,11 +1821,8 @@
                 " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxEventGroupGetNumberImpl                  \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory"
             );
         }
 
@@ -2065,11 +1852,8 @@
                 " MPU_vEventGroupSetNumber_Unpriv:                      \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vEventGroupSetNumberImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory"
             );
         }
 
@@ -2101,11 +1885,8 @@
             " MPU_xStreamBufferSend_Unpriv:                         \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferSendImpl                      \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2135,11 +1916,8 @@
             " MPU_xStreamBufferReceive_Unpriv:                      \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferReceiveImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2163,11 +1941,8 @@
             " MPU_xStreamBufferIsFull_Unpriv:                       \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferIsFullImpl                    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2191,11 +1966,8 @@
             " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferIsEmptyImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2219,11 +1991,8 @@
             " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferSpacesAvailableImpl           \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2247,11 +2016,8 @@
             " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferBytesAvailableImpl            \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2277,11 +2043,8 @@
             " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferSetTriggerLevelImpl           \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2305,11 +2068,8 @@
             " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferNextMessageLengthBytesImpl    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM33/non_secure/port.c b/portable/GCC/ARM_CM33/non_secure/port.c
index 52d68d3ea..6a3877894 100644
--- a/portable/GCC/ARM_CM33/non_secure/port.c
+++ b/portable/GCC/ARM_CM33/non_secure/port.c
@@ -35,8 +35,9 @@
 #include "FreeRTOS.h"
 #include "task.h"
 
-/* MPU wrappers includes. */
+/* MPU includes. */
 #include "mpu_wrappers.h"
+#include "mpu_syscall_numbers.h"
 
 /* Portasm includes. */
 #include "portasm.h"
@@ -436,29 +437,22 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
  * @brief Sets up the system call stack so that upon returning from
  * SVC, the system call stack is used.
  *
- * It is used for the system calls with up to 4 parameters.
- *
  * @param pulTaskStack The current SP when the SVC was raised.
  * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ * @param ucSystemCallNumber The system call number of the system call.
  */
     void vSystemCallEnter( uint32_t * pulTaskStack,
-                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
+                           uint32_t ulLR,
+                           uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
- * @brief Sets up the system call stack so that upon returning from
- * SVC, the system call stack is used.
- *
- * It is used for the system calls with 5 parameters.
- *
- * @param pulTaskStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ * @brief Raise SVC for exiting from a system call.
  */
-    void vSystemCallEnter_1( uint32_t * pulTaskStack,
-                             uint32_t ulLR ) PRIVILEGED_FUNCTION;
+    void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
@@ -488,6 +482,15 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+/**
+ * @brief This variable is set to pdTRUE when the scheduler is started.
+ */
+    PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
+
+#endif
+
 /**
  * @brief Each task maintains its own interrupt status in the critical nesting
  * variable.
@@ -1134,15 +1137,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     void vSystemCallEnter( uint32_t * pulTaskStack,
-                           uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
+                           uint32_t ulLR,
+                           uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */
     {
         extern TaskHandle_t pxCurrentTCB;
+        extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ];
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulSystemCallStack;
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
-
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __syscalls_flash_start__;
@@ -1154,17 +1158,27 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         #endif /* #if defined( __ARMCC_VERSION ) */
 
         ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
 
-        /* If the request did not come from the system call section, do nothing. */
+        /* Checks:
+         * 1. SVC is raised from the system call section (i.e. application is
+         *    not raising SVC directly).
+         * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as
+         *    it is non-NULL only during the execution of a system call (i.e.
+         *    between system call enter and exit).
+         * 3. System call is not for a kernel API disabled by the configuration
+         *    in FreeRTOSConfig.h.
+         * 4. We do not need to check that ucSystemCallNumber is within range
+         *    because the assembly SVC handler checks that before calling
+         *    this function.
+         */
         if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) &&
+            ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) &&
+            ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) )
         {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
             pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
 
-            /* This is not NULL only for the duration of the system call. */
-            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
-
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
@@ -1198,9 +1212,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 pulSystemCallStack[ i ] = pulTaskStack[ i ];
             }
 
-            /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
-             * restore it when we exit from the system call. */
+            /* Store the value of the Link Register before the SVC was raised.
+             * It contains the address of the caller of the System Call entry
+             * point (i.e. the caller of the MPU_<API>). We need to restore it
+             * when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            /* Store the value of the PSPLIM register before the SVC was raised.
+             * We need to restore it when we exit from the system call. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
             {
                 __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
@@ -1215,6 +1233,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             }
             #endif
 
+            /* Start executing the system call upon returning from this handler. */
+            pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
+            /* Raise a request to exit from the system call upon finishing the
+             * system call. */
+            pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit;
+
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
             pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
@@ -1251,127 +1275,9 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    void vSystemCallEnter_1( uint32_t * pulTaskStack,
-                             uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
+    void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */
     {
-        extern TaskHandle_t pxCurrentTCB;
-        xMPU_SETTINGS * pxMpuSettings;
-        uint32_t * pulSystemCallStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-
-        #if defined( __ARMCC_VERSION )
-
-            /* Declaration when these variable are defined in code instead of being
-             * exported from linker scripts. */
-            extern uint32_t * __syscalls_flash_start__;
-            extern uint32_t * __syscalls_flash_end__;
-        #else
-            /* Declaration when these variable are exported from linker scripts. */
-            extern uint32_t __syscalls_flash_start__[];
-            extern uint32_t __syscalls_flash_end__[];
-        #endif /* #if defined( __ARMCC_VERSION ) */
-
-        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-        /* If the request did not come from the system call section, do nothing. */
-        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
-        {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
-
-            /* This is not NULL only for the duration of the system call. */
-            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
-
-            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-            {
-                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
-                {
-                    /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
-                    __asm volatile (
-                        " vpush {s0}         \n" /* Trigger lazy stacking. */
-                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                        ::: "memory"
-                        );
-                }
-                else
-                {
-                    /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
-                }
-            }
-            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
-            {
-                ulStackFrameSize = 8;
-            }
-            #endif /* configENABLE_FPU || configENABLE_MVE */
-
-            /* Make space on the system call stack for the stack frame and
-             * the parameter passed on the stack. We only need to copy one
-             * parameter but we still reserve 2 spaces to keep the stack
-             * double word aligned. */
-            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
-
-            /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
-            {
-                pulSystemCallStack[ i ] = pulTaskStack[ i ];
-            }
-
-            /* Copy the parameter which is passed the stack. */
-            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-            {
-                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
-
-                /* Record if the hardware used padding to force the stack pointer
-                 * to be double word aligned. */
-                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-            }
-            else
-            {
-                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
-
-                /* Record if the hardware used padding to force the stack pointer
-                 * to be double word aligned. */
-                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-            }
-
-            /* Store the value of the LR and PSPLIM registers before the SVC was raised.
-             * We need to restore it when we exit from the system call. */
-            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            #if ( portUSE_PSPLIM_REGISTER == 1 )
-            {
-                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-            }
-            #endif
-
-            /* Use the pulSystemCallStack in thread mode. */
-            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            #if ( portUSE_PSPLIM_REGISTER == 1 )
-            {
-                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-            }
-            #endif
-
-            /* Remember the location where we should copy the stack frame when we exit from
-             * the system call. */
-            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-            /* We ensure in pxPortInitialiseStack that the system call stack is
-             * double word aligned and therefore, there is no need of padding.
-             * Clear the bit[9] of stacked xPSR. */
-            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-            /* Raise the privilege for the duration of the system call. */
-            __asm volatile (
-                " mrs r0, control     \n" /* Obtain current control value. */
-                " movs r1, #1         \n" /* r1 = 1. */
-                " bics r0, r1         \n" /* Clear nPRIV bit. */
-                " msr control, r0     \n" /* Write back new control value. */
-                ::: "r0", "r1", "memory"
-                );
-        }
+        __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" );
     }
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@@ -1388,24 +1294,32 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
-
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
-            extern uint32_t * __syscalls_flash_start__;
-            extern uint32_t * __syscalls_flash_end__;
+            extern uint32_t * __privileged_functions_start__;
+            extern uint32_t * __privileged_functions_end__;
         #else
             /* Declaration when these variable are exported from linker scripts. */
-            extern uint32_t __syscalls_flash_start__[];
-            extern uint32_t __syscalls_flash_end__[];
+            extern uint32_t __privileged_functions_start__[];
+            extern uint32_t __privileged_functions_end__[];
         #endif /* #if defined( __ARMCC_VERSION ) */
 
         ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
+        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
 
-        /* If the request did not come from the system call section, do nothing. */
-        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+        /* Checks:
+         * 1. SVC is raised from the privileged code (i.e. application is not
+         *    raising SVC directly). This SVC is only raised from
+         *    vRequestSystemCallExit which is in the privileged code section.
+         * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL -
+         *    this means that we previously entered a system call and the
+         *    application is not attempting to exit without entering a system
+         *    call.
+         */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) &&
+            ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) )
         {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
             pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
 
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
@@ -1444,9 +1358,14 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Use the pulTaskStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
 
-            /* Restore the LR and PSPLIM to what they were at the time of
-             * system call entry. */
+            /* Return to the caller of the System Call entry point (i.e. the
+             * caller of the MPU_<API>). */
+            pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+            /* Ensure that LR has a valid value.*/
             pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+
+            /* Restore the PSPLIM register to what it was at the time of
+             * system call entry. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
             {
                 __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
@@ -1780,6 +1699,12 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     /* Initialize the critical nesting count ready for the first task. */
     ulCriticalNesting = 0;
 
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+    {
+        xSchedulerRunning = pdTRUE;
+    }
+    #endif
+
     /* Start the first task. */
     vStartFirstTask();
 
@@ -2062,7 +1987,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
 
     void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
                                          int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
@@ -2078,10 +2003,10 @@ BaseType_t xPortIsInsideInterrupt( void )
         xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit );
     }
 
-#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
 
     void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
                                           int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
@@ -2097,10 +2022,10 @@ BaseType_t xPortIsInsideInterrupt( void )
         xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit );
     }
 
-#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
 
@@ -2108,21 +2033,34 @@ BaseType_t xPortIsInsideInterrupt( void )
         {
             uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
             BaseType_t xAccessGranted = pdFALSE;
-            const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+            const xMPU_SETTINGS * xTaskMpuSettings;
 
-            ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
-            ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
-
-            if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+            if( xSchedulerRunning == pdFALSE )
             {
+                /* Grant access to all the kernel objects before the scheduler
+                 * is started. It is necessary because there is no task running
+                 * yet and therefore, we cannot use the permissions of any
+                 * task. */
                 xAccessGranted = pdTRUE;
             }
             else
             {
-                if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+                ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+                ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+                if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
                 {
                     xAccessGranted = pdTRUE;
                 }
+                else
+                {
+                    if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                    {
+                        xAccessGranted = pdTRUE;
+                    }
+                }
             }
 
             return xAccessGranted;
@@ -2141,5 +2079,5 @@ BaseType_t xPortIsInsideInterrupt( void )
 
     #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
 
-#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM33/non_secure/portasm.c b/portable/GCC/ARM_CM33/non_secure/portasm.c
index ba8f6c62d..16c598ad7 100644
--- a/portable/GCC/ARM_CM33/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM33/non_secure/portasm.c
@@ -36,6 +36,9 @@
 /* Portasm includes. */
 #include "portasm.h"
 
+/* System call numbers includes. */
+#include "mpu_syscall_numbers.h"
+
 /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
  * header files. */
 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
@@ -522,7 +525,6 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             ".syntax unified                \n"
             ".extern vPortSVCHandler_C      \n"
             ".extern vSystemCallEnter       \n"
-            ".extern vSystemCallEnter_1     \n"
             ".extern vSystemCallExit        \n"
             "                               \n"
             "tst lr, #4                     \n"
@@ -533,10 +535,8 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "ldr r1, [r0, #24]              \n"
             "ldrb r2, [r1, #-2]             \n"
             "cmp r2, %0                     \n"
-            "beq syscall_enter              \n"
+            "blt syscall_enter              \n"
             "cmp r2, %1                     \n"
-            "beq syscall_enter_1            \n"
-            "cmp r2, %2                     \n"
             "beq syscall_exit               \n"
             "b vPortSVCHandler_C            \n"
             "                               \n"
@@ -544,16 +544,12 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    mov r1, lr                 \n"
             "    b vSystemCallEnter         \n"
             "                               \n"
-            "syscall_enter_1:               \n"
-            "    mov r1, lr                 \n"
-            "    b vSystemCallEnter_1       \n"
-            "                               \n"
             "syscall_exit:                  \n"
             "    mov r1, lr                 \n"
             "    b vSystemCallExit          \n"
             "                               \n"
             : /* No outputs. */
-            : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT )
+            : "i" ( NUM_SYSTEM_CALLS ), "i" ( portSVC_SYSTEM_CALL_EXIT )
             : "r0", "r1", "r2", "memory"
         );
     }
diff --git a/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h
index 60ef37380..672b0dbdc 100644
--- a/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h
@@ -322,14 +322,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 /**
  * @brief SVC numbers.
  */
-#define portSVC_ALLOCATE_SECURE_CONTEXT    0
-#define portSVC_FREE_SECURE_CONTEXT        1
-#define portSVC_START_SCHEDULER            2
-#define portSVC_RAISE_PRIVILEGE            3
-#define portSVC_SYSTEM_CALL_ENTER          4   /* System calls with upto 4 parameters. */
-#define portSVC_SYSTEM_CALL_ENTER_1        5   /* System calls with 5 parameters. */
-#define portSVC_SYSTEM_CALL_EXIT           6
-#define portSVC_YIELD                      7
+#define portSVC_ALLOCATE_SECURE_CONTEXT    100
+#define portSVC_FREE_SECURE_CONTEXT        101
+#define portSVC_START_SCHEDULER            102
+#define portSVC_RAISE_PRIVILEGE            103
+#define portSVC_SYSTEM_CALL_EXIT           104
+#define portSVC_YIELD                      105
 /*-----------------------------------------------------------*/
 
 /**
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.c
index d1fbdc0e5..4cb310afd 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.c
@@ -38,6 +38,8 @@
 #include "timers.h"
 #include "event_groups.h"
 #include "stream_buffer.h"
+#include "mpu_prototypes.h"
+#include "mpu_syscall_numbers.h"
 
 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
 /*-----------------------------------------------------------*/
@@ -67,11 +69,8 @@
                 " MPU_xTaskDelayUntil_Unpriv:                           \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskDelayUntilImpl                        \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory"
             );
         }
 
@@ -99,11 +98,8 @@
                 " MPU_xTaskAbortDelay_Unpriv:                           \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskAbortDelayImpl                        \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory"
             );
         }
 
@@ -131,11 +127,8 @@
                 " MPU_vTaskDelay_Unpriv:                                \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskDelayImpl                             \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory"
             );
         }
 
@@ -163,11 +156,8 @@
                 " MPU_uxTaskPriorityGet_Unpriv:                         \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskPriorityGetImpl                      \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory"
             );
         }
 
@@ -195,11 +185,8 @@
                 " MPU_eTaskGetState_Unpriv:                             \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_eTaskGetStateImpl                          \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory"
             );
         }
 
@@ -233,11 +220,8 @@
                 " MPU_vTaskGetInfo_Unpriv:                              \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskGetInfoImpl                           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory"
             );
         }
 
@@ -265,11 +249,8 @@
                 " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetIdleTaskHandleImpl                 \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory"
             );
         }
 
@@ -297,11 +278,8 @@
                 " MPU_vTaskSuspend_Unpriv:                              \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskSuspendImpl                           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory"
             );
         }
 
@@ -329,11 +307,8 @@
                 " MPU_vTaskResume_Unpriv:                               \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskResumeImpl                            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskResume ) : "memory"
             );
         }
 
@@ -359,11 +334,8 @@
             " MPU_xTaskGetTickCount_Unpriv:                         \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xTaskGetTickCountImpl                      \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -387,11 +359,8 @@
             " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_uxTaskGetNumberOfTasksImpl                 \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -417,11 +386,8 @@
                 " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetRunTimeCounterImpl                \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory"
             );
         }
 
@@ -449,11 +415,8 @@
                 " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetRunTimePercentImpl                \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory"
             );
         }
 
@@ -481,11 +444,8 @@
                 " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetIdleRunTimePercentImpl            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory"
             );
         }
 
@@ -513,11 +473,8 @@
                 " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetIdleRunTimeCounterImpl            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory"
             );
         }
 
@@ -547,11 +504,8 @@
                 " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskSetApplicationTaskTagImpl             \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory"
             );
         }
 
@@ -579,11 +533,8 @@
                 " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetApplicationTaskTagImpl             \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory"
             );
         }
 
@@ -615,11 +566,8 @@
                 " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskSetThreadLocalStoragePointerImpl      \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory"
             );
         }
 
@@ -649,11 +597,8 @@
                 " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pvTaskGetThreadLocalStoragePointerImpl     \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory"
             );
         }
 
@@ -685,11 +630,8 @@
                 " MPU_uxTaskGetSystemState_Unpriv:                      \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskGetSystemStateImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory"
             );
         }
 
@@ -717,11 +659,8 @@
                 " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskGetStackHighWaterMarkImpl            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory"
             );
         }
 
@@ -749,11 +688,8 @@
                 " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskGetStackHighWaterMark2Impl           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory"
             );
         }
 
@@ -781,11 +717,8 @@
                 " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetCurrentTaskHandleImpl              \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory"
             );
         }
 
@@ -813,11 +746,8 @@
                 " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetSchedulerStateImpl                 \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory"
             );
         }
 
@@ -843,11 +773,8 @@
             " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_vTaskSetTimeOutStateImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -873,28 +800,17 @@
             " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xTaskCheckForTimeOutImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
 
     #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                           UBaseType_t uxIndexToNotify,
-                                           uint32_t ulValue,
-                                           eNotifyAction eAction,
-                                           uint32_t * pulPreviousNotificationValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                           UBaseType_t uxIndexToNotify,
-                                           uint32_t ulValue,
-                                           eNotifyAction eAction,
-                                           uint32_t * pulPreviousNotificationValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
@@ -911,11 +827,8 @@
                 " MPU_xTaskGenericNotify_Unpriv:                        \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGenericNotifyImpl                     \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory"
             );
         }
 
@@ -924,17 +837,9 @@
 
     #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                               uint32_t ulBitsToClearOnEntry,
-                                               uint32_t ulBitsToClearOnExit,
-                                               uint32_t * pulNotificationValue,
-                                               TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                               uint32_t ulBitsToClearOnEntry,
-                                               uint32_t ulBitsToClearOnExit,
-                                               uint32_t * pulNotificationValue,
-                                               TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
@@ -951,11 +856,8 @@
                 " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGenericNotifyWaitImpl                 \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory"
             );
         }
 
@@ -987,11 +889,8 @@
                 " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGenericNotifyTakeImpl                \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory"
             );
         }
 
@@ -1021,11 +920,8 @@
                 " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGenericNotifyStateClearImpl           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory"
             );
         }
 
@@ -1057,11 +953,8 @@
                 " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGenericNotifyValueClearImpl          \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory"
             );
         }
 
@@ -1093,11 +986,8 @@
             " MPU_xQueueGenericSend_Unpriv:                         \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueueGenericSendImpl                      \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1121,11 +1011,8 @@
             " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_uxQueueMessagesWaitingImpl                 \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1149,11 +1036,8 @@
             " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_uxQueueSpacesAvailableImpl                 \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1181,11 +1065,8 @@
             " MPU_xQueueReceive_Unpriv:                             \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueueReceiveImpl                          \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1213,11 +1094,8 @@
             " MPU_xQueuePeek_Unpriv:                                \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueuePeekImpl                             \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1243,11 +1121,8 @@
             " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueueSemaphoreTakeImpl                    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1273,11 +1148,8 @@
                 " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueGetMutexHolderImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory"
             );
         }
 
@@ -1307,11 +1179,8 @@
                 " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueTakeMutexRecursiveImpl               \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory"
             );
         }
 
@@ -1339,11 +1208,8 @@
                 " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueGiveMutexRecursiveImpl               \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory"
             );
         }
 
@@ -1373,11 +1239,8 @@
                 " MPU_xQueueSelectFromSet_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueSelectFromSetImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory"
             );
         }
 
@@ -1407,11 +1270,8 @@
                 " MPU_xQueueAddToSet_Unpriv:                            \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueAddToSetImpl                         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory"
             );
         }
 
@@ -1441,11 +1301,8 @@
                 " MPU_vQueueAddToRegistry_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vQueueAddToRegistryImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory"
             );
         }
 
@@ -1473,11 +1330,8 @@
                 " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vQueueUnregisterQueueImpl                  \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory"
             );
         }
 
@@ -1505,11 +1359,8 @@
                 " MPU_pcQueueGetName_Unpriv:                            \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pcQueueGetNameImpl                         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory"
             );
         }
 
@@ -1537,11 +1388,8 @@
                 " MPU_pvTimerGetTimerID_Unpriv:                         \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pvTimerGetTimerIDImpl                      \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory"
             );
         }
 
@@ -1571,11 +1419,8 @@
                 " MPU_vTimerSetTimerID_Unpriv:                          \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTimerSetTimerIDImpl                       \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory"
             );
         }
 
@@ -1603,11 +1448,8 @@
                 " MPU_xTimerIsTimerActive_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerIsTimerActiveImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory"
             );
         }
 
@@ -1635,11 +1477,8 @@
                 " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetTimerDaemonTaskHandleImpl         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory"
             );
         }
 
@@ -1648,17 +1487,9 @@
 
     #if ( configUSE_TIMERS == 1 )
 
-        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                                     const BaseType_t xCommandID,
-                                                     const TickType_t xOptionalValue,
-                                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                                     const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                                     const BaseType_t xCommandID,
-                                                     const TickType_t xOptionalValue,
-                                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                                     const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
@@ -1675,11 +1506,8 @@
                 " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
                 "     pop {r0}                                                  \n"
                 "     svc %0                                                    \n"
-                "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
-                "     svc %1                                                    \n"
-                "     bx lr                                                     \n"
                 "                                                               \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory"
             );
         }
 
@@ -1707,11 +1535,8 @@
                 " MPU_pcTimerGetName_Unpriv:                            \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pcTimerGetNameImpl                         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory"
             );
         }
 
@@ -1741,11 +1566,8 @@
                 " MPU_vTimerSetReloadMode_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTimerSetReloadModeImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory"
             );
         }
 
@@ -1773,11 +1595,8 @@
                 " MPU_xTimerGetReloadMode_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetReloadModeImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory"
             );
         }
 
@@ -1805,11 +1624,8 @@
                 " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTimerGetReloadModeImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory"
             );
         }
 
@@ -1837,11 +1653,8 @@
                 " MPU_xTimerGetPeriod_Unpriv:                           \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetPeriodImpl                        \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory"
             );
         }
 
@@ -1869,28 +1682,17 @@
                 " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetExpiryTimeImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory"
             );
         }
 
     #endif /* if ( configUSE_TIMERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
-                                         const EventBits_t uxBitsToWaitFor,
-                                         const BaseType_t xClearOnExit,
-                                         const BaseType_t xWaitForAllBits,
-                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
-                                         const EventBits_t uxBitsToWaitFor,
-                                         const BaseType_t xClearOnExit,
-                                         const BaseType_t xWaitForAllBits,
-                                         TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
     {
         __asm volatile
         (
@@ -1907,11 +1709,8 @@
             " MPU_xEventGroupWaitBits_Unpriv:                       \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupWaitBitsImpl                    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1937,11 +1736,8 @@
             " MPU_xEventGroupClearBits_Unpriv:                      \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupClearBitsImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1967,11 +1763,8 @@
             " MPU_xEventGroupSetBits_Unpriv:                        \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupSetBitsImpl                     \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2001,11 +1794,8 @@
             " MPU_xEventGroupSync_Unpriv:                           \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupSyncImpl                        \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2031,11 +1821,8 @@
                 " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxEventGroupGetNumberImpl                  \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory"
             );
         }
 
@@ -2065,11 +1852,8 @@
                 " MPU_vEventGroupSetNumber_Unpriv:                      \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vEventGroupSetNumberImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory"
             );
         }
 
@@ -2101,11 +1885,8 @@
             " MPU_xStreamBufferSend_Unpriv:                         \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferSendImpl                      \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2135,11 +1916,8 @@
             " MPU_xStreamBufferReceive_Unpriv:                      \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferReceiveImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2163,11 +1941,8 @@
             " MPU_xStreamBufferIsFull_Unpriv:                       \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferIsFullImpl                    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2191,11 +1966,8 @@
             " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferIsEmptyImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2219,11 +1991,8 @@
             " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferSpacesAvailableImpl           \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2247,11 +2016,8 @@
             " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferBytesAvailableImpl            \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2277,11 +2043,8 @@
             " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferSetTriggerLevelImpl           \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2305,11 +2068,8 @@
             " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferNextMessageLengthBytesImpl    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
index 52d68d3ea..6a3877894 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
@@ -35,8 +35,9 @@
 #include "FreeRTOS.h"
 #include "task.h"
 
-/* MPU wrappers includes. */
+/* MPU includes. */
 #include "mpu_wrappers.h"
+#include "mpu_syscall_numbers.h"
 
 /* Portasm includes. */
 #include "portasm.h"
@@ -436,29 +437,22 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
  * @brief Sets up the system call stack so that upon returning from
  * SVC, the system call stack is used.
  *
- * It is used for the system calls with up to 4 parameters.
- *
  * @param pulTaskStack The current SP when the SVC was raised.
  * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ * @param ucSystemCallNumber The system call number of the system call.
  */
     void vSystemCallEnter( uint32_t * pulTaskStack,
-                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
+                           uint32_t ulLR,
+                           uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
- * @brief Sets up the system call stack so that upon returning from
- * SVC, the system call stack is used.
- *
- * It is used for the system calls with 5 parameters.
- *
- * @param pulTaskStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ * @brief Raise SVC for exiting from a system call.
  */
-    void vSystemCallEnter_1( uint32_t * pulTaskStack,
-                             uint32_t ulLR ) PRIVILEGED_FUNCTION;
+    void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
@@ -488,6 +482,15 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+/**
+ * @brief This variable is set to pdTRUE when the scheduler is started.
+ */
+    PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
+
+#endif
+
 /**
  * @brief Each task maintains its own interrupt status in the critical nesting
  * variable.
@@ -1134,15 +1137,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     void vSystemCallEnter( uint32_t * pulTaskStack,
-                           uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
+                           uint32_t ulLR,
+                           uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */
     {
         extern TaskHandle_t pxCurrentTCB;
+        extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ];
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulSystemCallStack;
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
-
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __syscalls_flash_start__;
@@ -1154,17 +1158,27 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         #endif /* #if defined( __ARMCC_VERSION ) */
 
         ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
 
-        /* If the request did not come from the system call section, do nothing. */
+        /* Checks:
+         * 1. SVC is raised from the system call section (i.e. application is
+         *    not raising SVC directly).
+         * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as
+         *    it is non-NULL only during the execution of a system call (i.e.
+         *    between system call enter and exit).
+         * 3. System call is not for a kernel API disabled by the configuration
+         *    in FreeRTOSConfig.h.
+         * 4. We do not need to check that ucSystemCallNumber is within range
+         *    because the assembly SVC handler checks that before calling
+         *    this function.
+         */
         if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) &&
+            ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) &&
+            ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) )
         {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
             pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
 
-            /* This is not NULL only for the duration of the system call. */
-            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
-
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
@@ -1198,9 +1212,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 pulSystemCallStack[ i ] = pulTaskStack[ i ];
             }
 
-            /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
-             * restore it when we exit from the system call. */
+            /* Store the value of the Link Register before the SVC was raised.
+             * It contains the address of the caller of the System Call entry
+             * point (i.e. the caller of the MPU_<API>). We need to restore it
+             * when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            /* Store the value of the PSPLIM register before the SVC was raised.
+             * We need to restore it when we exit from the system call. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
             {
                 __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
@@ -1215,6 +1233,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             }
             #endif
 
+            /* Start executing the system call upon returning from this handler. */
+            pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
+            /* Raise a request to exit from the system call upon finishing the
+             * system call. */
+            pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit;
+
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
             pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
@@ -1251,127 +1275,9 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    void vSystemCallEnter_1( uint32_t * pulTaskStack,
-                             uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
+    void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */
     {
-        extern TaskHandle_t pxCurrentTCB;
-        xMPU_SETTINGS * pxMpuSettings;
-        uint32_t * pulSystemCallStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-
-        #if defined( __ARMCC_VERSION )
-
-            /* Declaration when these variable are defined in code instead of being
-             * exported from linker scripts. */
-            extern uint32_t * __syscalls_flash_start__;
-            extern uint32_t * __syscalls_flash_end__;
-        #else
-            /* Declaration when these variable are exported from linker scripts. */
-            extern uint32_t __syscalls_flash_start__[];
-            extern uint32_t __syscalls_flash_end__[];
-        #endif /* #if defined( __ARMCC_VERSION ) */
-
-        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-        /* If the request did not come from the system call section, do nothing. */
-        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
-        {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
-
-            /* This is not NULL only for the duration of the system call. */
-            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
-
-            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-            {
-                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
-                {
-                    /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
-                    __asm volatile (
-                        " vpush {s0}         \n" /* Trigger lazy stacking. */
-                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                        ::: "memory"
-                        );
-                }
-                else
-                {
-                    /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
-                }
-            }
-            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
-            {
-                ulStackFrameSize = 8;
-            }
-            #endif /* configENABLE_FPU || configENABLE_MVE */
-
-            /* Make space on the system call stack for the stack frame and
-             * the parameter passed on the stack. We only need to copy one
-             * parameter but we still reserve 2 spaces to keep the stack
-             * double word aligned. */
-            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
-
-            /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
-            {
-                pulSystemCallStack[ i ] = pulTaskStack[ i ];
-            }
-
-            /* Copy the parameter which is passed the stack. */
-            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-            {
-                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
-
-                /* Record if the hardware used padding to force the stack pointer
-                 * to be double word aligned. */
-                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-            }
-            else
-            {
-                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
-
-                /* Record if the hardware used padding to force the stack pointer
-                 * to be double word aligned. */
-                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-            }
-
-            /* Store the value of the LR and PSPLIM registers before the SVC was raised.
-             * We need to restore it when we exit from the system call. */
-            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            #if ( portUSE_PSPLIM_REGISTER == 1 )
-            {
-                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-            }
-            #endif
-
-            /* Use the pulSystemCallStack in thread mode. */
-            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            #if ( portUSE_PSPLIM_REGISTER == 1 )
-            {
-                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-            }
-            #endif
-
-            /* Remember the location where we should copy the stack frame when we exit from
-             * the system call. */
-            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-            /* We ensure in pxPortInitialiseStack that the system call stack is
-             * double word aligned and therefore, there is no need of padding.
-             * Clear the bit[9] of stacked xPSR. */
-            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-            /* Raise the privilege for the duration of the system call. */
-            __asm volatile (
-                " mrs r0, control     \n" /* Obtain current control value. */
-                " movs r1, #1         \n" /* r1 = 1. */
-                " bics r0, r1         \n" /* Clear nPRIV bit. */
-                " msr control, r0     \n" /* Write back new control value. */
-                ::: "r0", "r1", "memory"
-                );
-        }
+        __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" );
     }
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@@ -1388,24 +1294,32 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
-
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
-            extern uint32_t * __syscalls_flash_start__;
-            extern uint32_t * __syscalls_flash_end__;
+            extern uint32_t * __privileged_functions_start__;
+            extern uint32_t * __privileged_functions_end__;
         #else
             /* Declaration when these variable are exported from linker scripts. */
-            extern uint32_t __syscalls_flash_start__[];
-            extern uint32_t __syscalls_flash_end__[];
+            extern uint32_t __privileged_functions_start__[];
+            extern uint32_t __privileged_functions_end__[];
         #endif /* #if defined( __ARMCC_VERSION ) */
 
         ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
+        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
 
-        /* If the request did not come from the system call section, do nothing. */
-        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+        /* Checks:
+         * 1. SVC is raised from the privileged code (i.e. application is not
+         *    raising SVC directly). This SVC is only raised from
+         *    vRequestSystemCallExit which is in the privileged code section.
+         * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL -
+         *    this means that we previously entered a system call and the
+         *    application is not attempting to exit without entering a system
+         *    call.
+         */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) &&
+            ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) )
         {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
             pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
 
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
@@ -1444,9 +1358,14 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Use the pulTaskStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
 
-            /* Restore the LR and PSPLIM to what they were at the time of
-             * system call entry. */
+            /* Return to the caller of the System Call entry point (i.e. the
+             * caller of the MPU_<API>). */
+            pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+            /* Ensure that LR has a valid value.*/
             pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+
+            /* Restore the PSPLIM register to what it was at the time of
+             * system call entry. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
             {
                 __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
@@ -1780,6 +1699,12 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     /* Initialize the critical nesting count ready for the first task. */
     ulCriticalNesting = 0;
 
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+    {
+        xSchedulerRunning = pdTRUE;
+    }
+    #endif
+
     /* Start the first task. */
     vStartFirstTask();
 
@@ -2062,7 +1987,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
 
     void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
                                          int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
@@ -2078,10 +2003,10 @@ BaseType_t xPortIsInsideInterrupt( void )
         xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit );
     }
 
-#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
 
     void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
                                           int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
@@ -2097,10 +2022,10 @@ BaseType_t xPortIsInsideInterrupt( void )
         xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit );
     }
 
-#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
 
@@ -2108,21 +2033,34 @@ BaseType_t xPortIsInsideInterrupt( void )
         {
             uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
             BaseType_t xAccessGranted = pdFALSE;
-            const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+            const xMPU_SETTINGS * xTaskMpuSettings;
 
-            ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
-            ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
-
-            if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+            if( xSchedulerRunning == pdFALSE )
             {
+                /* Grant access to all the kernel objects before the scheduler
+                 * is started. It is necessary because there is no task running
+                 * yet and therefore, we cannot use the permissions of any
+                 * task. */
                 xAccessGranted = pdTRUE;
             }
             else
             {
-                if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+                ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+                ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+                if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
                 {
                     xAccessGranted = pdTRUE;
                 }
+                else
+                {
+                    if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                    {
+                        xAccessGranted = pdTRUE;
+                    }
+                }
             }
 
             return xAccessGranted;
@@ -2141,5 +2079,5 @@ BaseType_t xPortIsInsideInterrupt( void )
 
     #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
 
-#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c b/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c
index e533dd7e9..76ba642a0 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c
@@ -36,6 +36,9 @@
 /* Portasm includes. */
 #include "portasm.h"
 
+/* System call numbers includes. */
+#include "mpu_syscall_numbers.h"
+
 /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
  * header files. */
 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
@@ -443,7 +446,6 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             ".syntax unified                \n"
             ".extern vPortSVCHandler_C      \n"
             ".extern vSystemCallEnter       \n"
-            ".extern vSystemCallEnter_1     \n"
             ".extern vSystemCallExit        \n"
             "                               \n"
             "tst lr, #4                     \n"
@@ -454,10 +456,8 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "ldr r1, [r0, #24]              \n"
             "ldrb r2, [r1, #-2]             \n"
             "cmp r2, %0                     \n"
-            "beq syscall_enter              \n"
+            "blt syscall_enter              \n"
             "cmp r2, %1                     \n"
-            "beq syscall_enter_1            \n"
-            "cmp r2, %2                     \n"
             "beq syscall_exit               \n"
             "b vPortSVCHandler_C            \n"
             "                               \n"
@@ -465,16 +465,12 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    mov r1, lr                 \n"
             "    b vSystemCallEnter         \n"
             "                               \n"
-            "syscall_enter_1:               \n"
-            "    mov r1, lr                 \n"
-            "    b vSystemCallEnter_1       \n"
-            "                               \n"
             "syscall_exit:                  \n"
             "    mov r1, lr                 \n"
             "    b vSystemCallExit          \n"
             "                               \n"
             : /* No outputs. */
-            : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT )
+            : "i" ( NUM_SYSTEM_CALLS ), "i" ( portSVC_SYSTEM_CALL_EXIT )
             : "r0", "r1", "r2", "memory"
         );
     }
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h
index 60ef37380..672b0dbdc 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h
@@ -322,14 +322,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 /**
  * @brief SVC numbers.
  */
-#define portSVC_ALLOCATE_SECURE_CONTEXT    0
-#define portSVC_FREE_SECURE_CONTEXT        1
-#define portSVC_START_SCHEDULER            2
-#define portSVC_RAISE_PRIVILEGE            3
-#define portSVC_SYSTEM_CALL_ENTER          4   /* System calls with upto 4 parameters. */
-#define portSVC_SYSTEM_CALL_ENTER_1        5   /* System calls with 5 parameters. */
-#define portSVC_SYSTEM_CALL_EXIT           6
-#define portSVC_YIELD                      7
+#define portSVC_ALLOCATE_SECURE_CONTEXT    100
+#define portSVC_FREE_SECURE_CONTEXT        101
+#define portSVC_START_SCHEDULER            102
+#define portSVC_RAISE_PRIVILEGE            103
+#define portSVC_SYSTEM_CALL_EXIT           104
+#define portSVC_YIELD                      105
 /*-----------------------------------------------------------*/
 
 /**
diff --git a/portable/GCC/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.c
index d1fbdc0e5..4cb310afd 100644
--- a/portable/GCC/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.c
@@ -38,6 +38,8 @@
 #include "timers.h"
 #include "event_groups.h"
 #include "stream_buffer.h"
+#include "mpu_prototypes.h"
+#include "mpu_syscall_numbers.h"
 
 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
 /*-----------------------------------------------------------*/
@@ -67,11 +69,8 @@
                 " MPU_xTaskDelayUntil_Unpriv:                           \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskDelayUntilImpl                        \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory"
             );
         }
 
@@ -99,11 +98,8 @@
                 " MPU_xTaskAbortDelay_Unpriv:                           \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskAbortDelayImpl                        \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory"
             );
         }
 
@@ -131,11 +127,8 @@
                 " MPU_vTaskDelay_Unpriv:                                \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskDelayImpl                             \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory"
             );
         }
 
@@ -163,11 +156,8 @@
                 " MPU_uxTaskPriorityGet_Unpriv:                         \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskPriorityGetImpl                      \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory"
             );
         }
 
@@ -195,11 +185,8 @@
                 " MPU_eTaskGetState_Unpriv:                             \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_eTaskGetStateImpl                          \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory"
             );
         }
 
@@ -233,11 +220,8 @@
                 " MPU_vTaskGetInfo_Unpriv:                              \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskGetInfoImpl                           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory"
             );
         }
 
@@ -265,11 +249,8 @@
                 " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetIdleTaskHandleImpl                 \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory"
             );
         }
 
@@ -297,11 +278,8 @@
                 " MPU_vTaskSuspend_Unpriv:                              \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskSuspendImpl                           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory"
             );
         }
 
@@ -329,11 +307,8 @@
                 " MPU_vTaskResume_Unpriv:                               \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskResumeImpl                            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskResume ) : "memory"
             );
         }
 
@@ -359,11 +334,8 @@
             " MPU_xTaskGetTickCount_Unpriv:                         \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xTaskGetTickCountImpl                      \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -387,11 +359,8 @@
             " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_uxTaskGetNumberOfTasksImpl                 \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -417,11 +386,8 @@
                 " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetRunTimeCounterImpl                \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory"
             );
         }
 
@@ -449,11 +415,8 @@
                 " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetRunTimePercentImpl                \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory"
             );
         }
 
@@ -481,11 +444,8 @@
                 " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetIdleRunTimePercentImpl            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory"
             );
         }
 
@@ -513,11 +473,8 @@
                 " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetIdleRunTimeCounterImpl            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory"
             );
         }
 
@@ -547,11 +504,8 @@
                 " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskSetApplicationTaskTagImpl             \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory"
             );
         }
 
@@ -579,11 +533,8 @@
                 " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetApplicationTaskTagImpl             \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory"
             );
         }
 
@@ -615,11 +566,8 @@
                 " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskSetThreadLocalStoragePointerImpl      \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory"
             );
         }
 
@@ -649,11 +597,8 @@
                 " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pvTaskGetThreadLocalStoragePointerImpl     \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory"
             );
         }
 
@@ -685,11 +630,8 @@
                 " MPU_uxTaskGetSystemState_Unpriv:                      \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskGetSystemStateImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory"
             );
         }
 
@@ -717,11 +659,8 @@
                 " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskGetStackHighWaterMarkImpl            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory"
             );
         }
 
@@ -749,11 +688,8 @@
                 " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskGetStackHighWaterMark2Impl           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory"
             );
         }
 
@@ -781,11 +717,8 @@
                 " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetCurrentTaskHandleImpl              \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory"
             );
         }
 
@@ -813,11 +746,8 @@
                 " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetSchedulerStateImpl                 \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory"
             );
         }
 
@@ -843,11 +773,8 @@
             " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_vTaskSetTimeOutStateImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -873,28 +800,17 @@
             " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xTaskCheckForTimeOutImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
 
     #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                           UBaseType_t uxIndexToNotify,
-                                           uint32_t ulValue,
-                                           eNotifyAction eAction,
-                                           uint32_t * pulPreviousNotificationValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                           UBaseType_t uxIndexToNotify,
-                                           uint32_t ulValue,
-                                           eNotifyAction eAction,
-                                           uint32_t * pulPreviousNotificationValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
@@ -911,11 +827,8 @@
                 " MPU_xTaskGenericNotify_Unpriv:                        \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGenericNotifyImpl                     \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory"
             );
         }
 
@@ -924,17 +837,9 @@
 
     #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                               uint32_t ulBitsToClearOnEntry,
-                                               uint32_t ulBitsToClearOnExit,
-                                               uint32_t * pulNotificationValue,
-                                               TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                               uint32_t ulBitsToClearOnEntry,
-                                               uint32_t ulBitsToClearOnExit,
-                                               uint32_t * pulNotificationValue,
-                                               TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
@@ -951,11 +856,8 @@
                 " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGenericNotifyWaitImpl                 \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory"
             );
         }
 
@@ -987,11 +889,8 @@
                 " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGenericNotifyTakeImpl                \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory"
             );
         }
 
@@ -1021,11 +920,8 @@
                 " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGenericNotifyStateClearImpl           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory"
             );
         }
 
@@ -1057,11 +953,8 @@
                 " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGenericNotifyValueClearImpl          \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory"
             );
         }
 
@@ -1093,11 +986,8 @@
             " MPU_xQueueGenericSend_Unpriv:                         \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueueGenericSendImpl                      \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1121,11 +1011,8 @@
             " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_uxQueueMessagesWaitingImpl                 \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1149,11 +1036,8 @@
             " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_uxQueueSpacesAvailableImpl                 \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1181,11 +1065,8 @@
             " MPU_xQueueReceive_Unpriv:                             \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueueReceiveImpl                          \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1213,11 +1094,8 @@
             " MPU_xQueuePeek_Unpriv:                                \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueuePeekImpl                             \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1243,11 +1121,8 @@
             " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueueSemaphoreTakeImpl                    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1273,11 +1148,8 @@
                 " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueGetMutexHolderImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory"
             );
         }
 
@@ -1307,11 +1179,8 @@
                 " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueTakeMutexRecursiveImpl               \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory"
             );
         }
 
@@ -1339,11 +1208,8 @@
                 " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueGiveMutexRecursiveImpl               \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory"
             );
         }
 
@@ -1373,11 +1239,8 @@
                 " MPU_xQueueSelectFromSet_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueSelectFromSetImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory"
             );
         }
 
@@ -1407,11 +1270,8 @@
                 " MPU_xQueueAddToSet_Unpriv:                            \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueAddToSetImpl                         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory"
             );
         }
 
@@ -1441,11 +1301,8 @@
                 " MPU_vQueueAddToRegistry_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vQueueAddToRegistryImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory"
             );
         }
 
@@ -1473,11 +1330,8 @@
                 " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vQueueUnregisterQueueImpl                  \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory"
             );
         }
 
@@ -1505,11 +1359,8 @@
                 " MPU_pcQueueGetName_Unpriv:                            \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pcQueueGetNameImpl                         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory"
             );
         }
 
@@ -1537,11 +1388,8 @@
                 " MPU_pvTimerGetTimerID_Unpriv:                         \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pvTimerGetTimerIDImpl                      \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory"
             );
         }
 
@@ -1571,11 +1419,8 @@
                 " MPU_vTimerSetTimerID_Unpriv:                          \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTimerSetTimerIDImpl                       \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory"
             );
         }
 
@@ -1603,11 +1448,8 @@
                 " MPU_xTimerIsTimerActive_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerIsTimerActiveImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory"
             );
         }
 
@@ -1635,11 +1477,8 @@
                 " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetTimerDaemonTaskHandleImpl         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory"
             );
         }
 
@@ -1648,17 +1487,9 @@
 
     #if ( configUSE_TIMERS == 1 )
 
-        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                                     const BaseType_t xCommandID,
-                                                     const TickType_t xOptionalValue,
-                                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                                     const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                                     const BaseType_t xCommandID,
-                                                     const TickType_t xOptionalValue,
-                                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                                     const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
@@ -1675,11 +1506,8 @@
                 " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
                 "     pop {r0}                                                  \n"
                 "     svc %0                                                    \n"
-                "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
-                "     svc %1                                                    \n"
-                "     bx lr                                                     \n"
                 "                                                               \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory"
             );
         }
 
@@ -1707,11 +1535,8 @@
                 " MPU_pcTimerGetName_Unpriv:                            \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pcTimerGetNameImpl                         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory"
             );
         }
 
@@ -1741,11 +1566,8 @@
                 " MPU_vTimerSetReloadMode_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTimerSetReloadModeImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory"
             );
         }
 
@@ -1773,11 +1595,8 @@
                 " MPU_xTimerGetReloadMode_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetReloadModeImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory"
             );
         }
 
@@ -1805,11 +1624,8 @@
                 " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTimerGetReloadModeImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory"
             );
         }
 
@@ -1837,11 +1653,8 @@
                 " MPU_xTimerGetPeriod_Unpriv:                           \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetPeriodImpl                        \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory"
             );
         }
 
@@ -1869,28 +1682,17 @@
                 " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetExpiryTimeImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory"
             );
         }
 
     #endif /* if ( configUSE_TIMERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
-                                         const EventBits_t uxBitsToWaitFor,
-                                         const BaseType_t xClearOnExit,
-                                         const BaseType_t xWaitForAllBits,
-                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
-                                         const EventBits_t uxBitsToWaitFor,
-                                         const BaseType_t xClearOnExit,
-                                         const BaseType_t xWaitForAllBits,
-                                         TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
     {
         __asm volatile
         (
@@ -1907,11 +1709,8 @@
             " MPU_xEventGroupWaitBits_Unpriv:                       \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupWaitBitsImpl                    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1937,11 +1736,8 @@
             " MPU_xEventGroupClearBits_Unpriv:                      \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupClearBitsImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1967,11 +1763,8 @@
             " MPU_xEventGroupSetBits_Unpriv:                        \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupSetBitsImpl                     \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2001,11 +1794,8 @@
             " MPU_xEventGroupSync_Unpriv:                           \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupSyncImpl                        \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2031,11 +1821,8 @@
                 " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxEventGroupGetNumberImpl                  \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory"
             );
         }
 
@@ -2065,11 +1852,8 @@
                 " MPU_vEventGroupSetNumber_Unpriv:                      \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vEventGroupSetNumberImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory"
             );
         }
 
@@ -2101,11 +1885,8 @@
             " MPU_xStreamBufferSend_Unpriv:                         \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferSendImpl                      \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2135,11 +1916,8 @@
             " MPU_xStreamBufferReceive_Unpriv:                      \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferReceiveImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2163,11 +1941,8 @@
             " MPU_xStreamBufferIsFull_Unpriv:                       \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferIsFullImpl                    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2191,11 +1966,8 @@
             " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferIsEmptyImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2219,11 +1991,8 @@
             " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferSpacesAvailableImpl           \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2247,11 +2016,8 @@
             " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferBytesAvailableImpl            \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2277,11 +2043,8 @@
             " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferSetTriggerLevelImpl           \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2305,11 +2068,8 @@
             " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferNextMessageLengthBytesImpl    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM35P/non_secure/port.c b/portable/GCC/ARM_CM35P/non_secure/port.c
index 52d68d3ea..6a3877894 100644
--- a/portable/GCC/ARM_CM35P/non_secure/port.c
+++ b/portable/GCC/ARM_CM35P/non_secure/port.c
@@ -35,8 +35,9 @@
 #include "FreeRTOS.h"
 #include "task.h"
 
-/* MPU wrappers includes. */
+/* MPU includes. */
 #include "mpu_wrappers.h"
+#include "mpu_syscall_numbers.h"
 
 /* Portasm includes. */
 #include "portasm.h"
@@ -436,29 +437,22 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
  * @brief Sets up the system call stack so that upon returning from
  * SVC, the system call stack is used.
  *
- * It is used for the system calls with up to 4 parameters.
- *
  * @param pulTaskStack The current SP when the SVC was raised.
  * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ * @param ucSystemCallNumber The system call number of the system call.
  */
     void vSystemCallEnter( uint32_t * pulTaskStack,
-                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
+                           uint32_t ulLR,
+                           uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
- * @brief Sets up the system call stack so that upon returning from
- * SVC, the system call stack is used.
- *
- * It is used for the system calls with 5 parameters.
- *
- * @param pulTaskStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ * @brief Raise SVC for exiting from a system call.
  */
-    void vSystemCallEnter_1( uint32_t * pulTaskStack,
-                             uint32_t ulLR ) PRIVILEGED_FUNCTION;
+    void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
@@ -488,6 +482,15 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+/**
+ * @brief This variable is set to pdTRUE when the scheduler is started.
+ */
+    PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
+
+#endif
+
 /**
  * @brief Each task maintains its own interrupt status in the critical nesting
  * variable.
@@ -1134,15 +1137,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     void vSystemCallEnter( uint32_t * pulTaskStack,
-                           uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
+                           uint32_t ulLR,
+                           uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */
     {
         extern TaskHandle_t pxCurrentTCB;
+        extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ];
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulSystemCallStack;
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
-
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __syscalls_flash_start__;
@@ -1154,17 +1158,27 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         #endif /* #if defined( __ARMCC_VERSION ) */
 
         ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
 
-        /* If the request did not come from the system call section, do nothing. */
+        /* Checks:
+         * 1. SVC is raised from the system call section (i.e. application is
+         *    not raising SVC directly).
+         * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as
+         *    it is non-NULL only during the execution of a system call (i.e.
+         *    between system call enter and exit).
+         * 3. System call is not for a kernel API disabled by the configuration
+         *    in FreeRTOSConfig.h.
+         * 4. We do not need to check that ucSystemCallNumber is within range
+         *    because the assembly SVC handler checks that before calling
+         *    this function.
+         */
         if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) &&
+            ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) &&
+            ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) )
         {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
             pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
 
-            /* This is not NULL only for the duration of the system call. */
-            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
-
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
@@ -1198,9 +1212,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 pulSystemCallStack[ i ] = pulTaskStack[ i ];
             }
 
-            /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
-             * restore it when we exit from the system call. */
+            /* Store the value of the Link Register before the SVC was raised.
+             * It contains the address of the caller of the System Call entry
+             * point (i.e. the caller of the MPU_<API>). We need to restore it
+             * when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            /* Store the value of the PSPLIM register before the SVC was raised.
+             * We need to restore it when we exit from the system call. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
             {
                 __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
@@ -1215,6 +1233,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             }
             #endif
 
+            /* Start executing the system call upon returning from this handler. */
+            pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
+            /* Raise a request to exit from the system call upon finishing the
+             * system call. */
+            pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit;
+
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
             pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
@@ -1251,127 +1275,9 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    void vSystemCallEnter_1( uint32_t * pulTaskStack,
-                             uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
+    void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */
     {
-        extern TaskHandle_t pxCurrentTCB;
-        xMPU_SETTINGS * pxMpuSettings;
-        uint32_t * pulSystemCallStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-
-        #if defined( __ARMCC_VERSION )
-
-            /* Declaration when these variable are defined in code instead of being
-             * exported from linker scripts. */
-            extern uint32_t * __syscalls_flash_start__;
-            extern uint32_t * __syscalls_flash_end__;
-        #else
-            /* Declaration when these variable are exported from linker scripts. */
-            extern uint32_t __syscalls_flash_start__[];
-            extern uint32_t __syscalls_flash_end__[];
-        #endif /* #if defined( __ARMCC_VERSION ) */
-
-        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-        /* If the request did not come from the system call section, do nothing. */
-        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
-        {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
-
-            /* This is not NULL only for the duration of the system call. */
-            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
-
-            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-            {
-                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
-                {
-                    /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
-                    __asm volatile (
-                        " vpush {s0}         \n" /* Trigger lazy stacking. */
-                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                        ::: "memory"
-                        );
-                }
-                else
-                {
-                    /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
-                }
-            }
-            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
-            {
-                ulStackFrameSize = 8;
-            }
-            #endif /* configENABLE_FPU || configENABLE_MVE */
-
-            /* Make space on the system call stack for the stack frame and
-             * the parameter passed on the stack. We only need to copy one
-             * parameter but we still reserve 2 spaces to keep the stack
-             * double word aligned. */
-            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
-
-            /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
-            {
-                pulSystemCallStack[ i ] = pulTaskStack[ i ];
-            }
-
-            /* Copy the parameter which is passed the stack. */
-            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-            {
-                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
-
-                /* Record if the hardware used padding to force the stack pointer
-                 * to be double word aligned. */
-                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-            }
-            else
-            {
-                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
-
-                /* Record if the hardware used padding to force the stack pointer
-                 * to be double word aligned. */
-                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-            }
-
-            /* Store the value of the LR and PSPLIM registers before the SVC was raised.
-             * We need to restore it when we exit from the system call. */
-            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            #if ( portUSE_PSPLIM_REGISTER == 1 )
-            {
-                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-            }
-            #endif
-
-            /* Use the pulSystemCallStack in thread mode. */
-            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            #if ( portUSE_PSPLIM_REGISTER == 1 )
-            {
-                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-            }
-            #endif
-
-            /* Remember the location where we should copy the stack frame when we exit from
-             * the system call. */
-            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-            /* We ensure in pxPortInitialiseStack that the system call stack is
-             * double word aligned and therefore, there is no need of padding.
-             * Clear the bit[9] of stacked xPSR. */
-            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-            /* Raise the privilege for the duration of the system call. */
-            __asm volatile (
-                " mrs r0, control     \n" /* Obtain current control value. */
-                " movs r1, #1         \n" /* r1 = 1. */
-                " bics r0, r1         \n" /* Clear nPRIV bit. */
-                " msr control, r0     \n" /* Write back new control value. */
-                ::: "r0", "r1", "memory"
-                );
-        }
+        __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" );
     }
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@@ -1388,24 +1294,32 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
-
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
-            extern uint32_t * __syscalls_flash_start__;
-            extern uint32_t * __syscalls_flash_end__;
+            extern uint32_t * __privileged_functions_start__;
+            extern uint32_t * __privileged_functions_end__;
         #else
             /* Declaration when these variable are exported from linker scripts. */
-            extern uint32_t __syscalls_flash_start__[];
-            extern uint32_t __syscalls_flash_end__[];
+            extern uint32_t __privileged_functions_start__[];
+            extern uint32_t __privileged_functions_end__[];
         #endif /* #if defined( __ARMCC_VERSION ) */
 
         ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
+        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
 
-        /* If the request did not come from the system call section, do nothing. */
-        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+        /* Checks:
+         * 1. SVC is raised from the privileged code (i.e. application is not
+         *    raising SVC directly). This SVC is only raised from
+         *    vRequestSystemCallExit which is in the privileged code section.
+         * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL -
+         *    this means that we previously entered a system call and the
+         *    application is not attempting to exit without entering a system
+         *    call.
+         */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) &&
+            ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) )
         {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
             pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
 
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
@@ -1444,9 +1358,14 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Use the pulTaskStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
 
-            /* Restore the LR and PSPLIM to what they were at the time of
-             * system call entry. */
+            /* Return to the caller of the System Call entry point (i.e. the
+             * caller of the MPU_<API>). */
+            pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+            /* Ensure that LR has a valid value.*/
             pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+
+            /* Restore the PSPLIM register to what it was at the time of
+             * system call entry. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
             {
                 __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
@@ -1780,6 +1699,12 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     /* Initialize the critical nesting count ready for the first task. */
     ulCriticalNesting = 0;
 
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+    {
+        xSchedulerRunning = pdTRUE;
+    }
+    #endif
+
     /* Start the first task. */
     vStartFirstTask();
 
@@ -2062,7 +1987,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
 
     void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
                                          int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
@@ -2078,10 +2003,10 @@ BaseType_t xPortIsInsideInterrupt( void )
         xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit );
     }
 
-#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
 
     void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
                                           int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
@@ -2097,10 +2022,10 @@ BaseType_t xPortIsInsideInterrupt( void )
         xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit );
     }
 
-#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
 
@@ -2108,21 +2033,34 @@ BaseType_t xPortIsInsideInterrupt( void )
         {
             uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
             BaseType_t xAccessGranted = pdFALSE;
-            const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+            const xMPU_SETTINGS * xTaskMpuSettings;
 
-            ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
-            ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
-
-            if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+            if( xSchedulerRunning == pdFALSE )
             {
+                /* Grant access to all the kernel objects before the scheduler
+                 * is started. It is necessary because there is no task running
+                 * yet and therefore, we cannot use the permissions of any
+                 * task. */
                 xAccessGranted = pdTRUE;
             }
             else
             {
-                if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+                ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+                ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+                if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
                 {
                     xAccessGranted = pdTRUE;
                 }
+                else
+                {
+                    if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                    {
+                        xAccessGranted = pdTRUE;
+                    }
+                }
             }
 
             return xAccessGranted;
@@ -2141,5 +2079,5 @@ BaseType_t xPortIsInsideInterrupt( void )
 
     #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
 
-#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM35P/non_secure/portasm.c b/portable/GCC/ARM_CM35P/non_secure/portasm.c
index ba8f6c62d..16c598ad7 100644
--- a/portable/GCC/ARM_CM35P/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM35P/non_secure/portasm.c
@@ -36,6 +36,9 @@
 /* Portasm includes. */
 #include "portasm.h"
 
+/* System call numbers includes. */
+#include "mpu_syscall_numbers.h"
+
 /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
  * header files. */
 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
@@ -522,7 +525,6 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             ".syntax unified                \n"
             ".extern vPortSVCHandler_C      \n"
             ".extern vSystemCallEnter       \n"
-            ".extern vSystemCallEnter_1     \n"
             ".extern vSystemCallExit        \n"
             "                               \n"
             "tst lr, #4                     \n"
@@ -533,10 +535,8 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "ldr r1, [r0, #24]              \n"
             "ldrb r2, [r1, #-2]             \n"
             "cmp r2, %0                     \n"
-            "beq syscall_enter              \n"
+            "blt syscall_enter              \n"
             "cmp r2, %1                     \n"
-            "beq syscall_enter_1            \n"
-            "cmp r2, %2                     \n"
             "beq syscall_exit               \n"
             "b vPortSVCHandler_C            \n"
             "                               \n"
@@ -544,16 +544,12 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    mov r1, lr                 \n"
             "    b vSystemCallEnter         \n"
             "                               \n"
-            "syscall_enter_1:               \n"
-            "    mov r1, lr                 \n"
-            "    b vSystemCallEnter_1       \n"
-            "                               \n"
             "syscall_exit:                  \n"
             "    mov r1, lr                 \n"
             "    b vSystemCallExit          \n"
             "                               \n"
             : /* No outputs. */
-            : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT )
+            : "i" ( NUM_SYSTEM_CALLS ), "i" ( portSVC_SYSTEM_CALL_EXIT )
             : "r0", "r1", "r2", "memory"
         );
     }
diff --git a/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h
index 60ef37380..672b0dbdc 100644
--- a/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h
@@ -322,14 +322,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 /**
  * @brief SVC numbers.
  */
-#define portSVC_ALLOCATE_SECURE_CONTEXT    0
-#define portSVC_FREE_SECURE_CONTEXT        1
-#define portSVC_START_SCHEDULER            2
-#define portSVC_RAISE_PRIVILEGE            3
-#define portSVC_SYSTEM_CALL_ENTER          4   /* System calls with upto 4 parameters. */
-#define portSVC_SYSTEM_CALL_ENTER_1        5   /* System calls with 5 parameters. */
-#define portSVC_SYSTEM_CALL_EXIT           6
-#define portSVC_YIELD                      7
+#define portSVC_ALLOCATE_SECURE_CONTEXT    100
+#define portSVC_FREE_SECURE_CONTEXT        101
+#define portSVC_START_SCHEDULER            102
+#define portSVC_RAISE_PRIVILEGE            103
+#define portSVC_SYSTEM_CALL_EXIT           104
+#define portSVC_YIELD                      105
 /*-----------------------------------------------------------*/
 
 /**
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.c
index d1fbdc0e5..4cb310afd 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.c
@@ -38,6 +38,8 @@
 #include "timers.h"
 #include "event_groups.h"
 #include "stream_buffer.h"
+#include "mpu_prototypes.h"
+#include "mpu_syscall_numbers.h"
 
 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
 /*-----------------------------------------------------------*/
@@ -67,11 +69,8 @@
                 " MPU_xTaskDelayUntil_Unpriv:                           \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskDelayUntilImpl                        \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory"
             );
         }
 
@@ -99,11 +98,8 @@
                 " MPU_xTaskAbortDelay_Unpriv:                           \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskAbortDelayImpl                        \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory"
             );
         }
 
@@ -131,11 +127,8 @@
                 " MPU_vTaskDelay_Unpriv:                                \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskDelayImpl                             \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory"
             );
         }
 
@@ -163,11 +156,8 @@
                 " MPU_uxTaskPriorityGet_Unpriv:                         \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskPriorityGetImpl                      \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory"
             );
         }
 
@@ -195,11 +185,8 @@
                 " MPU_eTaskGetState_Unpriv:                             \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_eTaskGetStateImpl                          \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory"
             );
         }
 
@@ -233,11 +220,8 @@
                 " MPU_vTaskGetInfo_Unpriv:                              \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskGetInfoImpl                           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory"
             );
         }
 
@@ -265,11 +249,8 @@
                 " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetIdleTaskHandleImpl                 \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory"
             );
         }
 
@@ -297,11 +278,8 @@
                 " MPU_vTaskSuspend_Unpriv:                              \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskSuspendImpl                           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory"
             );
         }
 
@@ -329,11 +307,8 @@
                 " MPU_vTaskResume_Unpriv:                               \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskResumeImpl                            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskResume ) : "memory"
             );
         }
 
@@ -359,11 +334,8 @@
             " MPU_xTaskGetTickCount_Unpriv:                         \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xTaskGetTickCountImpl                      \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -387,11 +359,8 @@
             " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_uxTaskGetNumberOfTasksImpl                 \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -417,11 +386,8 @@
                 " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetRunTimeCounterImpl                \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory"
             );
         }
 
@@ -449,11 +415,8 @@
                 " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetRunTimePercentImpl                \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory"
             );
         }
 
@@ -481,11 +444,8 @@
                 " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetIdleRunTimePercentImpl            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory"
             );
         }
 
@@ -513,11 +473,8 @@
                 " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetIdleRunTimeCounterImpl            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory"
             );
         }
 
@@ -547,11 +504,8 @@
                 " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskSetApplicationTaskTagImpl             \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory"
             );
         }
 
@@ -579,11 +533,8 @@
                 " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetApplicationTaskTagImpl             \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory"
             );
         }
 
@@ -615,11 +566,8 @@
                 " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskSetThreadLocalStoragePointerImpl      \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory"
             );
         }
 
@@ -649,11 +597,8 @@
                 " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pvTaskGetThreadLocalStoragePointerImpl     \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory"
             );
         }
 
@@ -685,11 +630,8 @@
                 " MPU_uxTaskGetSystemState_Unpriv:                      \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskGetSystemStateImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory"
             );
         }
 
@@ -717,11 +659,8 @@
                 " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskGetStackHighWaterMarkImpl            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory"
             );
         }
 
@@ -749,11 +688,8 @@
                 " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskGetStackHighWaterMark2Impl           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory"
             );
         }
 
@@ -781,11 +717,8 @@
                 " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetCurrentTaskHandleImpl              \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory"
             );
         }
 
@@ -813,11 +746,8 @@
                 " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetSchedulerStateImpl                 \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory"
             );
         }
 
@@ -843,11 +773,8 @@
             " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_vTaskSetTimeOutStateImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -873,28 +800,17 @@
             " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xTaskCheckForTimeOutImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
 
     #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                           UBaseType_t uxIndexToNotify,
-                                           uint32_t ulValue,
-                                           eNotifyAction eAction,
-                                           uint32_t * pulPreviousNotificationValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                           UBaseType_t uxIndexToNotify,
-                                           uint32_t ulValue,
-                                           eNotifyAction eAction,
-                                           uint32_t * pulPreviousNotificationValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
@@ -911,11 +827,8 @@
                 " MPU_xTaskGenericNotify_Unpriv:                        \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGenericNotifyImpl                     \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory"
             );
         }
 
@@ -924,17 +837,9 @@
 
     #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                               uint32_t ulBitsToClearOnEntry,
-                                               uint32_t ulBitsToClearOnExit,
-                                               uint32_t * pulNotificationValue,
-                                               TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                               uint32_t ulBitsToClearOnEntry,
-                                               uint32_t ulBitsToClearOnExit,
-                                               uint32_t * pulNotificationValue,
-                                               TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
@@ -951,11 +856,8 @@
                 " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGenericNotifyWaitImpl                 \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory"
             );
         }
 
@@ -987,11 +889,8 @@
                 " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGenericNotifyTakeImpl                \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory"
             );
         }
 
@@ -1021,11 +920,8 @@
                 " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGenericNotifyStateClearImpl           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory"
             );
         }
 
@@ -1057,11 +953,8 @@
                 " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGenericNotifyValueClearImpl          \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory"
             );
         }
 
@@ -1093,11 +986,8 @@
             " MPU_xQueueGenericSend_Unpriv:                         \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueueGenericSendImpl                      \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1121,11 +1011,8 @@
             " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_uxQueueMessagesWaitingImpl                 \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1149,11 +1036,8 @@
             " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_uxQueueSpacesAvailableImpl                 \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1181,11 +1065,8 @@
             " MPU_xQueueReceive_Unpriv:                             \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueueReceiveImpl                          \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1213,11 +1094,8 @@
             " MPU_xQueuePeek_Unpriv:                                \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueuePeekImpl                             \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1243,11 +1121,8 @@
             " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueueSemaphoreTakeImpl                    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1273,11 +1148,8 @@
                 " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueGetMutexHolderImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory"
             );
         }
 
@@ -1307,11 +1179,8 @@
                 " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueTakeMutexRecursiveImpl               \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory"
             );
         }
 
@@ -1339,11 +1208,8 @@
                 " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueGiveMutexRecursiveImpl               \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory"
             );
         }
 
@@ -1373,11 +1239,8 @@
                 " MPU_xQueueSelectFromSet_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueSelectFromSetImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory"
             );
         }
 
@@ -1407,11 +1270,8 @@
                 " MPU_xQueueAddToSet_Unpriv:                            \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueAddToSetImpl                         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory"
             );
         }
 
@@ -1441,11 +1301,8 @@
                 " MPU_vQueueAddToRegistry_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vQueueAddToRegistryImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory"
             );
         }
 
@@ -1473,11 +1330,8 @@
                 " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vQueueUnregisterQueueImpl                  \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory"
             );
         }
 
@@ -1505,11 +1359,8 @@
                 " MPU_pcQueueGetName_Unpriv:                            \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pcQueueGetNameImpl                         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory"
             );
         }
 
@@ -1537,11 +1388,8 @@
                 " MPU_pvTimerGetTimerID_Unpriv:                         \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pvTimerGetTimerIDImpl                      \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory"
             );
         }
 
@@ -1571,11 +1419,8 @@
                 " MPU_vTimerSetTimerID_Unpriv:                          \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTimerSetTimerIDImpl                       \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory"
             );
         }
 
@@ -1603,11 +1448,8 @@
                 " MPU_xTimerIsTimerActive_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerIsTimerActiveImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory"
             );
         }
 
@@ -1635,11 +1477,8 @@
                 " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetTimerDaemonTaskHandleImpl         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory"
             );
         }
 
@@ -1648,17 +1487,9 @@
 
     #if ( configUSE_TIMERS == 1 )
 
-        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                                     const BaseType_t xCommandID,
-                                                     const TickType_t xOptionalValue,
-                                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                                     const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                                     const BaseType_t xCommandID,
-                                                     const TickType_t xOptionalValue,
-                                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                                     const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
@@ -1675,11 +1506,8 @@
                 " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
                 "     pop {r0}                                                  \n"
                 "     svc %0                                                    \n"
-                "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
-                "     svc %1                                                    \n"
-                "     bx lr                                                     \n"
                 "                                                               \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory"
             );
         }
 
@@ -1707,11 +1535,8 @@
                 " MPU_pcTimerGetName_Unpriv:                            \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pcTimerGetNameImpl                         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory"
             );
         }
 
@@ -1741,11 +1566,8 @@
                 " MPU_vTimerSetReloadMode_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTimerSetReloadModeImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory"
             );
         }
 
@@ -1773,11 +1595,8 @@
                 " MPU_xTimerGetReloadMode_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetReloadModeImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory"
             );
         }
 
@@ -1805,11 +1624,8 @@
                 " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTimerGetReloadModeImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory"
             );
         }
 
@@ -1837,11 +1653,8 @@
                 " MPU_xTimerGetPeriod_Unpriv:                           \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetPeriodImpl                        \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory"
             );
         }
 
@@ -1869,28 +1682,17 @@
                 " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetExpiryTimeImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory"
             );
         }
 
     #endif /* if ( configUSE_TIMERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
-                                         const EventBits_t uxBitsToWaitFor,
-                                         const BaseType_t xClearOnExit,
-                                         const BaseType_t xWaitForAllBits,
-                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
-                                         const EventBits_t uxBitsToWaitFor,
-                                         const BaseType_t xClearOnExit,
-                                         const BaseType_t xWaitForAllBits,
-                                         TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
     {
         __asm volatile
         (
@@ -1907,11 +1709,8 @@
             " MPU_xEventGroupWaitBits_Unpriv:                       \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupWaitBitsImpl                    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1937,11 +1736,8 @@
             " MPU_xEventGroupClearBits_Unpriv:                      \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupClearBitsImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1967,11 +1763,8 @@
             " MPU_xEventGroupSetBits_Unpriv:                        \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupSetBitsImpl                     \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2001,11 +1794,8 @@
             " MPU_xEventGroupSync_Unpriv:                           \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupSyncImpl                        \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2031,11 +1821,8 @@
                 " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxEventGroupGetNumberImpl                  \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory"
             );
         }
 
@@ -2065,11 +1852,8 @@
                 " MPU_vEventGroupSetNumber_Unpriv:                      \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vEventGroupSetNumberImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory"
             );
         }
 
@@ -2101,11 +1885,8 @@
             " MPU_xStreamBufferSend_Unpriv:                         \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferSendImpl                      \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2135,11 +1916,8 @@
             " MPU_xStreamBufferReceive_Unpriv:                      \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferReceiveImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2163,11 +1941,8 @@
             " MPU_xStreamBufferIsFull_Unpriv:                       \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferIsFullImpl                    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2191,11 +1966,8 @@
             " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferIsEmptyImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2219,11 +1991,8 @@
             " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferSpacesAvailableImpl           \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2247,11 +2016,8 @@
             " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferBytesAvailableImpl            \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2277,11 +2043,8 @@
             " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferSetTriggerLevelImpl           \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2305,11 +2068,8 @@
             " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferNextMessageLengthBytesImpl    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c b/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
index 52d68d3ea..6a3877894 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
@@ -35,8 +35,9 @@
 #include "FreeRTOS.h"
 #include "task.h"
 
-/* MPU wrappers includes. */
+/* MPU includes. */
 #include "mpu_wrappers.h"
+#include "mpu_syscall_numbers.h"
 
 /* Portasm includes. */
 #include "portasm.h"
@@ -436,29 +437,22 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
  * @brief Sets up the system call stack so that upon returning from
  * SVC, the system call stack is used.
  *
- * It is used for the system calls with up to 4 parameters.
- *
  * @param pulTaskStack The current SP when the SVC was raised.
  * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ * @param ucSystemCallNumber The system call number of the system call.
  */
     void vSystemCallEnter( uint32_t * pulTaskStack,
-                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
+                           uint32_t ulLR,
+                           uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
- * @brief Sets up the system call stack so that upon returning from
- * SVC, the system call stack is used.
- *
- * It is used for the system calls with 5 parameters.
- *
- * @param pulTaskStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ * @brief Raise SVC for exiting from a system call.
  */
-    void vSystemCallEnter_1( uint32_t * pulTaskStack,
-                             uint32_t ulLR ) PRIVILEGED_FUNCTION;
+    void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
@@ -488,6 +482,15 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+/**
+ * @brief This variable is set to pdTRUE when the scheduler is started.
+ */
+    PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
+
+#endif
+
 /**
  * @brief Each task maintains its own interrupt status in the critical nesting
  * variable.
@@ -1134,15 +1137,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     void vSystemCallEnter( uint32_t * pulTaskStack,
-                           uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
+                           uint32_t ulLR,
+                           uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */
     {
         extern TaskHandle_t pxCurrentTCB;
+        extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ];
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulSystemCallStack;
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
-
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __syscalls_flash_start__;
@@ -1154,17 +1158,27 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         #endif /* #if defined( __ARMCC_VERSION ) */
 
         ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
 
-        /* If the request did not come from the system call section, do nothing. */
+        /* Checks:
+         * 1. SVC is raised from the system call section (i.e. application is
+         *    not raising SVC directly).
+         * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as
+         *    it is non-NULL only during the execution of a system call (i.e.
+         *    between system call enter and exit).
+         * 3. System call is not for a kernel API disabled by the configuration
+         *    in FreeRTOSConfig.h.
+         * 4. We do not need to check that ucSystemCallNumber is within range
+         *    because the assembly SVC handler checks that before calling
+         *    this function.
+         */
         if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) &&
+            ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) &&
+            ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) )
         {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
             pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
 
-            /* This is not NULL only for the duration of the system call. */
-            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
-
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
@@ -1198,9 +1212,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 pulSystemCallStack[ i ] = pulTaskStack[ i ];
             }
 
-            /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
-             * restore it when we exit from the system call. */
+            /* Store the value of the Link Register before the SVC was raised.
+             * It contains the address of the caller of the System Call entry
+             * point (i.e. the caller of the MPU_<API>). We need to restore it
+             * when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            /* Store the value of the PSPLIM register before the SVC was raised.
+             * We need to restore it when we exit from the system call. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
             {
                 __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
@@ -1215,6 +1233,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             }
             #endif
 
+            /* Start executing the system call upon returning from this handler. */
+            pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
+            /* Raise a request to exit from the system call upon finishing the
+             * system call. */
+            pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit;
+
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
             pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
@@ -1251,127 +1275,9 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    void vSystemCallEnter_1( uint32_t * pulTaskStack,
-                             uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
+    void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */
     {
-        extern TaskHandle_t pxCurrentTCB;
-        xMPU_SETTINGS * pxMpuSettings;
-        uint32_t * pulSystemCallStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-
-        #if defined( __ARMCC_VERSION )
-
-            /* Declaration when these variable are defined in code instead of being
-             * exported from linker scripts. */
-            extern uint32_t * __syscalls_flash_start__;
-            extern uint32_t * __syscalls_flash_end__;
-        #else
-            /* Declaration when these variable are exported from linker scripts. */
-            extern uint32_t __syscalls_flash_start__[];
-            extern uint32_t __syscalls_flash_end__[];
-        #endif /* #if defined( __ARMCC_VERSION ) */
-
-        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-        /* If the request did not come from the system call section, do nothing. */
-        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
-        {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
-
-            /* This is not NULL only for the duration of the system call. */
-            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
-
-            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-            {
-                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
-                {
-                    /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
-                    __asm volatile (
-                        " vpush {s0}         \n" /* Trigger lazy stacking. */
-                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                        ::: "memory"
-                        );
-                }
-                else
-                {
-                    /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
-                }
-            }
-            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
-            {
-                ulStackFrameSize = 8;
-            }
-            #endif /* configENABLE_FPU || configENABLE_MVE */
-
-            /* Make space on the system call stack for the stack frame and
-             * the parameter passed on the stack. We only need to copy one
-             * parameter but we still reserve 2 spaces to keep the stack
-             * double word aligned. */
-            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
-
-            /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
-            {
-                pulSystemCallStack[ i ] = pulTaskStack[ i ];
-            }
-
-            /* Copy the parameter which is passed the stack. */
-            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-            {
-                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
-
-                /* Record if the hardware used padding to force the stack pointer
-                 * to be double word aligned. */
-                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-            }
-            else
-            {
-                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
-
-                /* Record if the hardware used padding to force the stack pointer
-                 * to be double word aligned. */
-                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-            }
-
-            /* Store the value of the LR and PSPLIM registers before the SVC was raised.
-             * We need to restore it when we exit from the system call. */
-            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            #if ( portUSE_PSPLIM_REGISTER == 1 )
-            {
-                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-            }
-            #endif
-
-            /* Use the pulSystemCallStack in thread mode. */
-            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            #if ( portUSE_PSPLIM_REGISTER == 1 )
-            {
-                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-            }
-            #endif
-
-            /* Remember the location where we should copy the stack frame when we exit from
-             * the system call. */
-            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-            /* We ensure in pxPortInitialiseStack that the system call stack is
-             * double word aligned and therefore, there is no need of padding.
-             * Clear the bit[9] of stacked xPSR. */
-            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-            /* Raise the privilege for the duration of the system call. */
-            __asm volatile (
-                " mrs r0, control     \n" /* Obtain current control value. */
-                " movs r1, #1         \n" /* r1 = 1. */
-                " bics r0, r1         \n" /* Clear nPRIV bit. */
-                " msr control, r0     \n" /* Write back new control value. */
-                ::: "r0", "r1", "memory"
-                );
-        }
+        __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" );
     }
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@@ -1388,24 +1294,32 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
-
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
-            extern uint32_t * __syscalls_flash_start__;
-            extern uint32_t * __syscalls_flash_end__;
+            extern uint32_t * __privileged_functions_start__;
+            extern uint32_t * __privileged_functions_end__;
         #else
             /* Declaration when these variable are exported from linker scripts. */
-            extern uint32_t __syscalls_flash_start__[];
-            extern uint32_t __syscalls_flash_end__[];
+            extern uint32_t __privileged_functions_start__[];
+            extern uint32_t __privileged_functions_end__[];
         #endif /* #if defined( __ARMCC_VERSION ) */
 
         ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
+        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
 
-        /* If the request did not come from the system call section, do nothing. */
-        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+        /* Checks:
+         * 1. SVC is raised from the privileged code (i.e. application is not
+         *    raising SVC directly). This SVC is only raised from
+         *    vRequestSystemCallExit which is in the privileged code section.
+         * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL -
+         *    this means that we previously entered a system call and the
+         *    application is not attempting to exit without entering a system
+         *    call.
+         */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) &&
+            ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) )
         {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
             pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
 
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
@@ -1444,9 +1358,14 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Use the pulTaskStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
 
-            /* Restore the LR and PSPLIM to what they were at the time of
-             * system call entry. */
+            /* Return to the caller of the System Call entry point (i.e. the
+             * caller of the MPU_<API>). */
+            pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+            /* Ensure that LR has a valid value.*/
             pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+
+            /* Restore the PSPLIM register to what it was at the time of
+             * system call entry. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
             {
                 __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
@@ -1780,6 +1699,12 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     /* Initialize the critical nesting count ready for the first task. */
     ulCriticalNesting = 0;
 
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+    {
+        xSchedulerRunning = pdTRUE;
+    }
+    #endif
+
     /* Start the first task. */
     vStartFirstTask();
 
@@ -2062,7 +1987,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
 
     void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
                                          int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
@@ -2078,10 +2003,10 @@ BaseType_t xPortIsInsideInterrupt( void )
         xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit );
     }
 
-#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
 
     void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
                                           int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
@@ -2097,10 +2022,10 @@ BaseType_t xPortIsInsideInterrupt( void )
         xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit );
     }
 
-#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
 
@@ -2108,21 +2033,34 @@ BaseType_t xPortIsInsideInterrupt( void )
         {
             uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
             BaseType_t xAccessGranted = pdFALSE;
-            const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+            const xMPU_SETTINGS * xTaskMpuSettings;
 
-            ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
-            ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
-
-            if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+            if( xSchedulerRunning == pdFALSE )
             {
+                /* Grant access to all the kernel objects before the scheduler
+                 * is started. It is necessary because there is no task running
+                 * yet and therefore, we cannot use the permissions of any
+                 * task. */
                 xAccessGranted = pdTRUE;
             }
             else
             {
-                if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+                ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+                ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+                if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
                 {
                     xAccessGranted = pdTRUE;
                 }
+                else
+                {
+                    if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                    {
+                        xAccessGranted = pdTRUE;
+                    }
+                }
             }
 
             return xAccessGranted;
@@ -2141,5 +2079,5 @@ BaseType_t xPortIsInsideInterrupt( void )
 
     #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
 
-#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.c b/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.c
index e533dd7e9..76ba642a0 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.c
@@ -36,6 +36,9 @@
 /* Portasm includes. */
 #include "portasm.h"
 
+/* System call numbers includes. */
+#include "mpu_syscall_numbers.h"
+
 /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
  * header files. */
 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
@@ -443,7 +446,6 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             ".syntax unified                \n"
             ".extern vPortSVCHandler_C      \n"
             ".extern vSystemCallEnter       \n"
-            ".extern vSystemCallEnter_1     \n"
             ".extern vSystemCallExit        \n"
             "                               \n"
             "tst lr, #4                     \n"
@@ -454,10 +456,8 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "ldr r1, [r0, #24]              \n"
             "ldrb r2, [r1, #-2]             \n"
             "cmp r2, %0                     \n"
-            "beq syscall_enter              \n"
+            "blt syscall_enter              \n"
             "cmp r2, %1                     \n"
-            "beq syscall_enter_1            \n"
-            "cmp r2, %2                     \n"
             "beq syscall_exit               \n"
             "b vPortSVCHandler_C            \n"
             "                               \n"
@@ -465,16 +465,12 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    mov r1, lr                 \n"
             "    b vSystemCallEnter         \n"
             "                               \n"
-            "syscall_enter_1:               \n"
-            "    mov r1, lr                 \n"
-            "    b vSystemCallEnter_1       \n"
-            "                               \n"
             "syscall_exit:                  \n"
             "    mov r1, lr                 \n"
             "    b vSystemCallExit          \n"
             "                               \n"
             : /* No outputs. */
-            : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT )
+            : "i" ( NUM_SYSTEM_CALLS ), "i" ( portSVC_SYSTEM_CALL_EXIT )
             : "r0", "r1", "r2", "memory"
         );
     }
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
index 60ef37380..672b0dbdc 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
@@ -322,14 +322,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 /**
  * @brief SVC numbers.
  */
-#define portSVC_ALLOCATE_SECURE_CONTEXT    0
-#define portSVC_FREE_SECURE_CONTEXT        1
-#define portSVC_START_SCHEDULER            2
-#define portSVC_RAISE_PRIVILEGE            3
-#define portSVC_SYSTEM_CALL_ENTER          4   /* System calls with upto 4 parameters. */
-#define portSVC_SYSTEM_CALL_ENTER_1        5   /* System calls with 5 parameters. */
-#define portSVC_SYSTEM_CALL_EXIT           6
-#define portSVC_YIELD                      7
+#define portSVC_ALLOCATE_SECURE_CONTEXT    100
+#define portSVC_FREE_SECURE_CONTEXT        101
+#define portSVC_START_SCHEDULER            102
+#define portSVC_RAISE_PRIVILEGE            103
+#define portSVC_SYSTEM_CALL_EXIT           104
+#define portSVC_YIELD                      105
 /*-----------------------------------------------------------*/
 
 /**
diff --git a/portable/GCC/ARM_CM3_MPU/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM3_MPU/mpu_wrappers_v2_asm.c
index 9a8cf55eb..6b76b376c 100644
--- a/portable/GCC/ARM_CM3_MPU/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM3_MPU/mpu_wrappers_v2_asm.c
@@ -38,6 +38,8 @@
 #include "timers.h"
 #include "event_groups.h"
 #include "stream_buffer.h"
+#include "mpu_prototypes.h"
+#include "mpu_syscall_numbers.h"
 
 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
 /*-----------------------------------------------------------*/
@@ -67,11 +69,8 @@
                 " MPU_xTaskDelayUntil_Unpriv:                           \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskDelayUntilImpl                        \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory"
             );
         }
 
@@ -99,11 +98,8 @@
                 " MPU_xTaskAbortDelay_Unpriv:                           \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskAbortDelayImpl                        \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory"
             );
         }
 
@@ -131,11 +127,8 @@
                 " MPU_vTaskDelay_Unpriv:                                \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskDelayImpl                             \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory"
             );
         }
 
@@ -163,11 +156,8 @@
                 " MPU_uxTaskPriorityGet_Unpriv:                         \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskPriorityGetImpl                      \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory"
             );
         }
 
@@ -195,11 +185,8 @@
                 " MPU_eTaskGetState_Unpriv:                             \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_eTaskGetStateImpl                          \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory"
             );
         }
 
@@ -233,11 +220,8 @@
                 " MPU_vTaskGetInfo_Unpriv:                              \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskGetInfoImpl                           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory"
             );
         }
 
@@ -265,11 +249,8 @@
                 " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetIdleTaskHandleImpl                 \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory"
             );
         }
 
@@ -297,11 +278,8 @@
                 " MPU_vTaskSuspend_Unpriv:                              \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskSuspendImpl                           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory"
             );
         }
 
@@ -329,11 +307,8 @@
                 " MPU_vTaskResume_Unpriv:                               \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskResumeImpl                            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskResume ) : "memory"
             );
         }
 
@@ -359,11 +334,8 @@
             " MPU_xTaskGetTickCount_Unpriv:                         \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xTaskGetTickCountImpl                      \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -387,11 +359,8 @@
             " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_uxTaskGetNumberOfTasksImpl                 \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -417,11 +386,8 @@
                 " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetRunTimeCounterImpl                \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory"
             );
         }
 
@@ -449,11 +415,8 @@
                 " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetRunTimePercentImpl                \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory"
             );
         }
 
@@ -481,11 +444,8 @@
                 " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetIdleRunTimePercentImpl            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory"
             );
         }
 
@@ -513,11 +473,8 @@
                 " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetIdleRunTimeCounterImpl            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory"
             );
         }
 
@@ -547,11 +504,8 @@
                 " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskSetApplicationTaskTagImpl             \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory"
             );
         }
 
@@ -579,11 +533,8 @@
                 " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetApplicationTaskTagImpl             \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory"
             );
         }
 
@@ -615,11 +566,8 @@
                 " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskSetThreadLocalStoragePointerImpl      \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory"
             );
         }
 
@@ -649,11 +597,8 @@
                 " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pvTaskGetThreadLocalStoragePointerImpl     \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory"
             );
         }
 
@@ -685,11 +630,8 @@
                 " MPU_uxTaskGetSystemState_Unpriv:                      \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskGetSystemStateImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory"
             );
         }
 
@@ -717,11 +659,8 @@
                 " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskGetStackHighWaterMarkImpl            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory"
             );
         }
 
@@ -749,11 +688,8 @@
                 " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskGetStackHighWaterMark2Impl           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory"
             );
         }
 
@@ -781,11 +717,8 @@
                 " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetCurrentTaskHandleImpl              \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory"
             );
         }
 
@@ -813,11 +746,8 @@
                 " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetSchedulerStateImpl                 \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory"
             );
         }
 
@@ -843,11 +773,8 @@
             " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_vTaskSetTimeOutStateImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -873,28 +800,17 @@
             " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xTaskCheckForTimeOutImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
 
     #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                           UBaseType_t uxIndexToNotify,
-                                           uint32_t ulValue,
-                                           eNotifyAction eAction,
-                                           uint32_t * pulPreviousNotificationValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                           UBaseType_t uxIndexToNotify,
-                                           uint32_t ulValue,
-                                           eNotifyAction eAction,
-                                           uint32_t * pulPreviousNotificationValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
@@ -911,11 +827,8 @@
                 " MPU_xTaskGenericNotify_Unpriv:                        \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGenericNotifyImpl                     \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory"
             );
         }
 
@@ -924,17 +837,9 @@
 
     #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                               uint32_t ulBitsToClearOnEntry,
-                                               uint32_t ulBitsToClearOnExit,
-                                               uint32_t * pulNotificationValue,
-                                               TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                               uint32_t ulBitsToClearOnEntry,
-                                               uint32_t ulBitsToClearOnExit,
-                                               uint32_t * pulNotificationValue,
-                                               TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
@@ -951,11 +856,8 @@
                 " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGenericNotifyWaitImpl                 \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory"
             );
         }
 
@@ -987,11 +889,8 @@
                 " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGenericNotifyTakeImpl                \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory"
             );
         }
 
@@ -1021,11 +920,8 @@
                 " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGenericNotifyStateClearImpl           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory"
             );
         }
 
@@ -1057,11 +953,8 @@
                 " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGenericNotifyValueClearImpl          \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory"
             );
         }
 
@@ -1093,11 +986,8 @@
             " MPU_xQueueGenericSend_Unpriv:                         \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueueGenericSendImpl                      \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1121,11 +1011,8 @@
             " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_uxQueueMessagesWaitingImpl                 \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1149,11 +1036,8 @@
             " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_uxQueueSpacesAvailableImpl                 \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1181,11 +1065,8 @@
             " MPU_xQueueReceive_Unpriv:                             \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueueReceiveImpl                          \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1213,11 +1094,8 @@
             " MPU_xQueuePeek_Unpriv:                                \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueuePeekImpl                             \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1243,11 +1121,8 @@
             " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueueSemaphoreTakeImpl                    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1273,11 +1148,8 @@
                 " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueGetMutexHolderImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory"
             );
         }
 
@@ -1307,11 +1179,8 @@
                 " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueTakeMutexRecursiveImpl               \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory"
             );
         }
 
@@ -1339,11 +1208,8 @@
                 " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueGiveMutexRecursiveImpl               \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory"
             );
         }
 
@@ -1373,11 +1239,8 @@
                 " MPU_xQueueSelectFromSet_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueSelectFromSetImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory"
             );
         }
 
@@ -1407,11 +1270,8 @@
                 " MPU_xQueueAddToSet_Unpriv:                            \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueAddToSetImpl                         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory"
             );
         }
 
@@ -1441,11 +1301,8 @@
                 " MPU_vQueueAddToRegistry_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vQueueAddToRegistryImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory"
             );
         }
 
@@ -1473,11 +1330,8 @@
                 " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vQueueUnregisterQueueImpl                  \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory"
             );
         }
 
@@ -1505,11 +1359,8 @@
                 " MPU_pcQueueGetName_Unpriv:                            \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pcQueueGetNameImpl                         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory"
             );
         }
 
@@ -1537,11 +1388,8 @@
                 " MPU_pvTimerGetTimerID_Unpriv:                         \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pvTimerGetTimerIDImpl                      \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory"
             );
         }
 
@@ -1571,11 +1419,8 @@
                 " MPU_vTimerSetTimerID_Unpriv:                          \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTimerSetTimerIDImpl                       \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory"
             );
         }
 
@@ -1603,11 +1448,8 @@
                 " MPU_xTimerIsTimerActive_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerIsTimerActiveImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory"
             );
         }
 
@@ -1635,11 +1477,8 @@
                 " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetTimerDaemonTaskHandleImpl         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory"
             );
         }
 
@@ -1648,17 +1487,9 @@
 
     #if ( configUSE_TIMERS == 1 )
 
-        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                                     const BaseType_t xCommandID,
-                                                     const TickType_t xOptionalValue,
-                                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                                     const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                                     const BaseType_t xCommandID,
-                                                     const TickType_t xOptionalValue,
-                                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                                     const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
@@ -1675,11 +1506,8 @@
                 " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
                 "     pop {r0}                                                  \n"
                 "     svc %0                                                    \n"
-                "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
-                "     svc %1                                                    \n"
-                "     bx lr                                                     \n"
                 "                                                               \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory"
             );
         }
 
@@ -1707,11 +1535,8 @@
                 " MPU_pcTimerGetName_Unpriv:                            \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pcTimerGetNameImpl                         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory"
             );
         }
 
@@ -1741,11 +1566,8 @@
                 " MPU_vTimerSetReloadMode_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTimerSetReloadModeImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory"
             );
         }
 
@@ -1773,11 +1595,8 @@
                 " MPU_xTimerGetReloadMode_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetReloadModeImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory"
             );
         }
 
@@ -1805,11 +1624,8 @@
                 " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTimerGetReloadModeImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory"
             );
         }
 
@@ -1837,11 +1653,8 @@
                 " MPU_xTimerGetPeriod_Unpriv:                           \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetPeriodImpl                        \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory"
             );
         }
 
@@ -1869,28 +1682,17 @@
                 " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetExpiryTimeImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory"
             );
         }
 
     #endif /* if ( configUSE_TIMERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
-                                         const EventBits_t uxBitsToWaitFor,
-                                         const BaseType_t xClearOnExit,
-                                         const BaseType_t xWaitForAllBits,
-                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
-                                         const EventBits_t uxBitsToWaitFor,
-                                         const BaseType_t xClearOnExit,
-                                         const BaseType_t xWaitForAllBits,
-                                         TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
     {
         __asm volatile
         (
@@ -1907,11 +1709,8 @@
             " MPU_xEventGroupWaitBits_Unpriv:                       \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupWaitBitsImpl                    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1937,11 +1736,8 @@
             " MPU_xEventGroupClearBits_Unpriv:                      \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupClearBitsImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1967,11 +1763,8 @@
             " MPU_xEventGroupSetBits_Unpriv:                        \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupSetBitsImpl                     \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2001,11 +1794,8 @@
             " MPU_xEventGroupSync_Unpriv:                           \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupSyncImpl                        \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2031,11 +1821,8 @@
                 " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxEventGroupGetNumberImpl                  \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory"
             );
         }
 
@@ -2065,11 +1852,8 @@
                 " MPU_vEventGroupSetNumber_Unpriv:                      \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vEventGroupSetNumberImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory"
             );
         }
 
@@ -2101,11 +1885,8 @@
             " MPU_xStreamBufferSend_Unpriv:                         \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferSendImpl                      \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2135,11 +1916,8 @@
             " MPU_xStreamBufferReceive_Unpriv:                      \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferReceiveImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2163,11 +1941,8 @@
             " MPU_xStreamBufferIsFull_Unpriv:                       \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferIsFullImpl                    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2191,11 +1966,8 @@
             " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferIsEmptyImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2219,11 +1991,8 @@
             " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferSpacesAvailableImpl           \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2247,11 +2016,8 @@
             " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferBytesAvailableImpl            \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2277,11 +2043,8 @@
             " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferSetTriggerLevelImpl           \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2305,11 +2068,8 @@
             " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferNextMessageLengthBytesImpl    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM3_MPU/port.c b/portable/GCC/ARM_CM3_MPU/port.c
index ea2b9355e..1b774bdc7 100644
--- a/portable/GCC/ARM_CM3_MPU/port.c
+++ b/portable/GCC/ARM_CM3_MPU/port.c
@@ -38,6 +38,7 @@
 /* Scheduler includes. */
 #include "FreeRTOS.h"
 #include "task.h"
+#include "mpu_syscall_numbers.h"
 
 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
 
@@ -214,25 +215,20 @@ void vPortSwitchToUserMode( void );
  * @brief Sets up the system call stack so that upon returning from
  * SVC, the system call stack is used.
  *
- * It is used for the system calls with up to 4 parameters.
- *
  * @param pulTaskStack The current SP when the SVC was raised.
+ * @param ucSystemCallNumber The system call number of the system call.
  */
-    void vSystemCallEnter( uint32_t * pulTaskStack ) PRIVILEGED_FUNCTION;
+    void vSystemCallEnter( uint32_t * pulTaskStack,
+                           uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION;
 
 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
 
 /**
- * @brief Sets up the system call stack so that upon returning from
- * SVC, the system call stack is used.
- *
- * It is used for the system calls with 5 parameters.
- *
- * @param pulTaskStack The current SP when the SVC was raised.
+ * @brief Raise SVC for exiting from a system call.
  */
-    void vSystemCallEnter_1( uint32_t * pulTaskStack ) PRIVILEGED_FUNCTION;
+    void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
 
 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
@@ -261,6 +257,15 @@ BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
  * switches can only occur when uxCriticalNesting is zero. */
 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
 
+#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+/*
+ * This variable is set to pdTRUE when the scheduler is started.
+ */
+    PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
+
+#endif
+
 /*
  * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
  * FreeRTOS API functions are not called from interrupts that have been assigned
@@ -338,7 +343,6 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
             ".syntax unified                \n"
             ".extern vSVCHandler_C          \n"
             ".extern vSystemCallEnter       \n"
-            ".extern vSystemCallEnter_1     \n"
             ".extern vSystemCallExit        \n"
             "                               \n"
             "tst lr, #4                     \n"
@@ -346,18 +350,16 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
             "mrseq r0, msp                  \n"
             "mrsne r0, psp                  \n"
             "                               \n"
-            "ldr r1, [r0, #24]              \n"
-            "ldrb r2, [r1, #-2]             \n"
-            "cmp r2, %0                     \n"
-            "beq vSystemCallEnter           \n"
-            "cmp r2, %1                     \n"
-            "beq vSystemCallEnter_1         \n"
-            "cmp r2, %2                     \n"
+            "ldr r2, [r0, #24]              \n"
+            "ldrb r1, [r2, #-2]             \n"
+            "cmp r1, %0                     \n"
+            "blt vSystemCallEnter           \n"
+            "cmp r1, %1                     \n"
             "beq vSystemCallExit            \n"
             "b vSVCHandler_C                \n"
             "                               \n"
             : /* No outputs. */
-            : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT )
+            : "i" ( NUM_SYSTEM_CALLS ), "i" ( portSVC_SYSTEM_CALL_EXIT )
             : "r0", "r1", "r2", "memory"
         );
     }
@@ -390,7 +392,7 @@ void vSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
     uint8_t ucSVCNumber;
     uint32_t ulPC;
 
-    #if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )
+    #if ( ( configUSE_MPU_WRAPPERS_V1 == 1 ) && ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) )
         #if defined( __ARMCC_VERSION )
 
             /* Declaration when these variable are defined in code instead of being
@@ -402,7 +404,7 @@ void vSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
             extern uint32_t __syscalls_flash_start__[];
             extern uint32_t __syscalls_flash_end__[];
         #endif /* #if defined( __ARMCC_VERSION ) */
-    #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
+    #endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 1 ) && ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) ) */
 
     /* The stack contains: r0, r1, r2, r3, r12, LR, PC and xPSR.  The first
      * argument (r0) is pulParam[ 0 ]. */
@@ -428,26 +430,15 @@ void vSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
 
             break;
 
-            #if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )
-                case portSVC_RAISE_PRIVILEGE: /* Only raise the privilege, if the
-                                               * svc was raised from any of the
-                                               * system calls. */
+    #if ( configUSE_MPU_WRAPPERS_V1 == 1 )
+        #if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )
+            case portSVC_RAISE_PRIVILEGE: /* Only raise the privilege, if the
+                                           * svc was raised from any of the
+                                           * system calls. */
 
-                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
-                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
-                    {
-                        __asm volatile
-                        (
-                            "   mrs r1, control     \n" /* Obtain current control value. */
-                            "   bic r1, #1          \n" /* Set privilege bit. */
-                            "   msr control, r1     \n" /* Write back new control value. */
-                            ::: "r1", "memory"
-                        );
-                    }
-
-                    break;
-            #else /* if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
-                case portSVC_RAISE_PRIVILEGE:
+                if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+                    ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+                {
                     __asm volatile
                     (
                         "   mrs r1, control     \n" /* Obtain current control value. */
@@ -455,27 +446,41 @@ void vSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
                         "   msr control, r1     \n" /* Write back new control value. */
                         ::: "r1", "memory"
                     );
-                    break;
-                    #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
+                }
 
-                default: /* Unknown SVC call. */
-                    break;
+                break;
+        #else /* if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
+            case portSVC_RAISE_PRIVILEGE:
+                __asm volatile
+                (
+                    "   mrs r1, control     \n" /* Obtain current control value. */
+                    "   bic r1, #1          \n" /* Set privilege bit. */
+                    "   msr control, r1     \n" /* Write back new control value. */
+                    ::: "r1", "memory"
+                );
+                break;
+        #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
+    #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+
+        default: /* Unknown SVC call. */
+            break;
     }
 }
 /*-----------------------------------------------------------*/
 
 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
 
-    void vSystemCallEnter( uint32_t * pulTaskStack ) /* PRIVILEGED_FUNCTION */
+    void vSystemCallEnter( uint32_t * pulTaskStack,
+                           uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */
     {
         extern TaskHandle_t pxCurrentTCB;
+        extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ];
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulSystemCallStack;
         uint32_t ulSystemCallLocation, i;
         const uint32_t ulStackFrameSize = 8;
 
         #if defined( __ARMCC_VERSION )
-
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __syscalls_flash_start__;
@@ -487,17 +492,27 @@ void vSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
         #endif /* #if defined( __ARMCC_VERSION ) */
 
         ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
 
-        /* If the request did not come from the system call section, do nothing. */
+        /* Checks:
+         * 1. SVC is raised from the system call section (i.e. application is
+         *    not raising SVC directly).
+         * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as
+         *    it is non-NULL only during the execution of a system call (i.e.
+         *    between system call enter and exit).
+         * 3. System call is not for a kernel API disabled by the configuration
+         *    in FreeRTOSConfig.h.
+         * 4. We do not need to check that ucSystemCallNumber is within range
+         *    because the assembly SVC handler checks that before calling
+         *    this function.
+         */
         if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) &&
+            ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) &&
+            ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) )
         {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
             pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
 
-            /* This is not NULL only for the duration of the system call. */
-            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
-
             /* Make space on the system call stack for the stack frame. */
             pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
 
@@ -522,10 +537,18 @@ void vSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
              * the system call. */
             pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
 
-            /* Store the value of the Link Register before the SVC was raised. We need to
-             * restore it when we exit from the system call. */
+            /* Store the value of the Link Register before the SVC was raised.
+             * It contains the address of the caller of the System Call entry
+             * point (i.e. the caller of the MPU_<API>). We need to restore it
+             * when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
 
+            /* Start executing the system call upon returning from this handler. */
+            pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
+            /* Raise a request to exit from the system call upon finishing the
+             * system call. */
+            pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit;
+
             /* Record if the hardware used padding to force the stack pointer
              * to be double word aligned. */
             if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
@@ -549,92 +572,9 @@ void vSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
 
 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
 
-    void vSystemCallEnter_1( uint32_t * pulTaskStack ) /* PRIVILEGED_FUNCTION */
+    void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */
     {
-        extern TaskHandle_t pxCurrentTCB;
-        xMPU_SETTINGS * pxMpuSettings;
-        uint32_t * pulSystemCallStack;
-        uint32_t ulSystemCallLocation, i;
-        const uint32_t ulStackFrameSize = 8;
-
-        #if defined( __ARMCC_VERSION )
-
-            /* Declaration when these variable are defined in code instead of being
-             * exported from linker scripts. */
-            extern uint32_t * __syscalls_flash_start__;
-            extern uint32_t * __syscalls_flash_end__;
-        #else
-            /* Declaration when these variable are exported from linker scripts. */
-            extern uint32_t __syscalls_flash_start__[];
-            extern uint32_t __syscalls_flash_end__[];
-        #endif /* #if defined( __ARMCC_VERSION ) */
-
-        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-        /* If the request did not come from the system call section, do nothing. */
-        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
-        {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
-
-            /* This is not NULL only for the duration of the system call. */
-            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
-
-            /* Make space on the system call stack for the stack frame and
-             * the parameter passed on the stack. We only need to copy one
-             * parameter but we still reserve 2 spaces to keep the stack
-             * double word aligned. */
-            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
-
-            /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
-            {
-                pulSystemCallStack[ i ] = pulTaskStack[ i ];
-            }
-
-            /* Copy the parameter which is passed the stack. */
-            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-            {
-                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
-
-                /* Record if the hardware used padding to force the stack pointer
-                 * to be double word aligned. */
-                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-            }
-            else
-            {
-                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
-
-                /* Record if the hardware used padding to force the stack pointer
-                 * to be double word aligned. */
-                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-            }
-
-            /* Use the pulSystemCallStack in thread mode. */
-            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-
-            /* Raise the privilege for the duration of the system call. */
-            __asm volatile (
-                " mrs r1, control     \n" /* Obtain current control value. */
-                " bic r1, #1          \n" /* Clear nPRIV bit. */
-                " msr control, r1     \n" /* Write back new control value. */
-                ::: "r1", "memory"
-                );
-
-            /* Remember the location where we should copy the stack frame when we exit from
-             * the system call. */
-            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-            /* Store the value of the Link Register before the SVC was raised. We need to
-             * restore it when we exit from the system call. */
-            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-
-            /* We ensure in pxPortInitialiseStack that the system call stack is
-             * double word aligned and therefore, there is no need of padding.
-             * Clear the bit[9] of stacked xPSR. */
-            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-        }
+        __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" );
     }
 
 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@@ -651,24 +591,32 @@ void vSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
         const uint32_t ulStackFrameSize = 8;
 
         #if defined( __ARMCC_VERSION )
-
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
-            extern uint32_t * __syscalls_flash_start__;
-            extern uint32_t * __syscalls_flash_end__;
+            extern uint32_t * __privileged_functions_start__;
+            extern uint32_t * __privileged_functions_end__;
         #else
             /* Declaration when these variable are exported from linker scripts. */
-            extern uint32_t __syscalls_flash_start__[];
-            extern uint32_t __syscalls_flash_end__[];
+            extern uint32_t __privileged_functions_start__[];
+            extern uint32_t __privileged_functions_end__[];
         #endif /* #if defined( __ARMCC_VERSION ) */
 
         ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
+        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
 
-        /* If the request did not come from the system call section, do nothing. */
-        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+        /* Checks:
+         * 1. SVC is raised from the privileged code (i.e. application is not
+         *    raising SVC directly). This SVC is only raised from
+         *    vRequestSystemCallExit which is in the privileged code section.
+         * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL -
+         *    this means that we previously entered a system call and the
+         *    application is not attempting to exit without entering a system
+         *    call.
+         */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) &&
+            ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) )
         {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
             pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
 
             /* Make space on the task stack for the stack frame. */
@@ -691,8 +639,10 @@ void vSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
                 ::: "r1", "memory"
                 );
 
-            /* Restore the stacked link register to what it was at the time of
-             * system call entry. */
+            /* Return to the caller of the System Call entry point (i.e. the
+             * caller of the MPU_<API>). */
+            pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+            /* Ensure that LR has a valid value.*/
             pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
 
             /* If the hardware used padding to force the stack pointer
@@ -887,6 +837,12 @@ BaseType_t xPortStartScheduler( void )
     /* Initialise the critical nesting count ready for the first task. */
     uxCriticalNesting = 0;
 
+    #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+    {
+        xSchedulerRunning = pdTRUE;
+    }
+    #endif
+
     /* Start the first task. */
     __asm volatile (
         " ldr r0, =0xE000ED08   \n" /* Use the NVIC offset register to locate the stack. */
@@ -1494,21 +1450,34 @@ BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
         {
             uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
             BaseType_t xAccessGranted = pdFALSE;
-            const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+            const xMPU_SETTINGS * xTaskMpuSettings;
 
-            ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
-            ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
-
-            if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+            if( xSchedulerRunning == pdFALSE )
             {
+                /* Grant access to all the kernel objects before the scheduler
+                 * is started. It is necessary because there is no task running
+                 * yet and therefore, we cannot use the permissions of any
+                 * task. */
                 xAccessGranted = pdTRUE;
             }
             else
             {
-                if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+                ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+                ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+                if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
                 {
                     xAccessGranted = pdTRUE;
                 }
+                else
+                {
+                    if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                    {
+                        xAccessGranted = pdTRUE;
+                    }
+                }
             }
 
             return xAccessGranted;
diff --git a/portable/GCC/ARM_CM3_MPU/portmacro.h b/portable/GCC/ARM_CM3_MPU/portmacro.h
index d0822e144..5983c7912 100644
--- a/portable/GCC/ARM_CM3_MPU/portmacro.h
+++ b/portable/GCC/ARM_CM3_MPU/portmacro.h
@@ -157,12 +157,10 @@ typedef struct MPU_SETTINGS
 /*-----------------------------------------------------------*/
 
 /* SVC numbers for various services. */
-#define portSVC_START_SCHEDULER        0
-#define portSVC_YIELD                  1
-#define portSVC_RAISE_PRIVILEGE        2
-#define portSVC_SYSTEM_CALL_ENTER      3    /* System calls with upto 4 parameters. */
-#define portSVC_SYSTEM_CALL_ENTER_1    4    /* System calls with 5 parameters. */
-#define portSVC_SYSTEM_CALL_EXIT       5
+#define portSVC_START_SCHEDULER        100
+#define portSVC_YIELD                  101
+#define portSVC_RAISE_PRIVILEGE        102
+#define portSVC_SYSTEM_CALL_EXIT       103
 
 /* Scheduler utilities. */
 
diff --git a/portable/GCC/ARM_CM4_MPU/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM4_MPU/mpu_wrappers_v2_asm.c
index 9a8cf55eb..6b76b376c 100644
--- a/portable/GCC/ARM_CM4_MPU/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM4_MPU/mpu_wrappers_v2_asm.c
@@ -38,6 +38,8 @@
 #include "timers.h"
 #include "event_groups.h"
 #include "stream_buffer.h"
+#include "mpu_prototypes.h"
+#include "mpu_syscall_numbers.h"
 
 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
 /*-----------------------------------------------------------*/
@@ -67,11 +69,8 @@
                 " MPU_xTaskDelayUntil_Unpriv:                           \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskDelayUntilImpl                        \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory"
             );
         }
 
@@ -99,11 +98,8 @@
                 " MPU_xTaskAbortDelay_Unpriv:                           \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskAbortDelayImpl                        \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory"
             );
         }
 
@@ -131,11 +127,8 @@
                 " MPU_vTaskDelay_Unpriv:                                \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskDelayImpl                             \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory"
             );
         }
 
@@ -163,11 +156,8 @@
                 " MPU_uxTaskPriorityGet_Unpriv:                         \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskPriorityGetImpl                      \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory"
             );
         }
 
@@ -195,11 +185,8 @@
                 " MPU_eTaskGetState_Unpriv:                             \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_eTaskGetStateImpl                          \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory"
             );
         }
 
@@ -233,11 +220,8 @@
                 " MPU_vTaskGetInfo_Unpriv:                              \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskGetInfoImpl                           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory"
             );
         }
 
@@ -265,11 +249,8 @@
                 " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetIdleTaskHandleImpl                 \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory"
             );
         }
 
@@ -297,11 +278,8 @@
                 " MPU_vTaskSuspend_Unpriv:                              \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskSuspendImpl                           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory"
             );
         }
 
@@ -329,11 +307,8 @@
                 " MPU_vTaskResume_Unpriv:                               \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskResumeImpl                            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskResume ) : "memory"
             );
         }
 
@@ -359,11 +334,8 @@
             " MPU_xTaskGetTickCount_Unpriv:                         \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xTaskGetTickCountImpl                      \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -387,11 +359,8 @@
             " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_uxTaskGetNumberOfTasksImpl                 \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -417,11 +386,8 @@
                 " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetRunTimeCounterImpl                \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory"
             );
         }
 
@@ -449,11 +415,8 @@
                 " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetRunTimePercentImpl                \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory"
             );
         }
 
@@ -481,11 +444,8 @@
                 " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetIdleRunTimePercentImpl            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory"
             );
         }
 
@@ -513,11 +473,8 @@
                 " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetIdleRunTimeCounterImpl            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory"
             );
         }
 
@@ -547,11 +504,8 @@
                 " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskSetApplicationTaskTagImpl             \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory"
             );
         }
 
@@ -579,11 +533,8 @@
                 " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetApplicationTaskTagImpl             \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory"
             );
         }
 
@@ -615,11 +566,8 @@
                 " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskSetThreadLocalStoragePointerImpl      \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory"
             );
         }
 
@@ -649,11 +597,8 @@
                 " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pvTaskGetThreadLocalStoragePointerImpl     \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory"
             );
         }
 
@@ -685,11 +630,8 @@
                 " MPU_uxTaskGetSystemState_Unpriv:                      \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskGetSystemStateImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory"
             );
         }
 
@@ -717,11 +659,8 @@
                 " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskGetStackHighWaterMarkImpl            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory"
             );
         }
 
@@ -749,11 +688,8 @@
                 " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskGetStackHighWaterMark2Impl           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory"
             );
         }
 
@@ -781,11 +717,8 @@
                 " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetCurrentTaskHandleImpl              \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory"
             );
         }
 
@@ -813,11 +746,8 @@
                 " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetSchedulerStateImpl                 \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory"
             );
         }
 
@@ -843,11 +773,8 @@
             " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_vTaskSetTimeOutStateImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -873,28 +800,17 @@
             " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xTaskCheckForTimeOutImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
 
     #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                           UBaseType_t uxIndexToNotify,
-                                           uint32_t ulValue,
-                                           eNotifyAction eAction,
-                                           uint32_t * pulPreviousNotificationValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                           UBaseType_t uxIndexToNotify,
-                                           uint32_t ulValue,
-                                           eNotifyAction eAction,
-                                           uint32_t * pulPreviousNotificationValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
@@ -911,11 +827,8 @@
                 " MPU_xTaskGenericNotify_Unpriv:                        \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGenericNotifyImpl                     \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory"
             );
         }
 
@@ -924,17 +837,9 @@
 
     #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                               uint32_t ulBitsToClearOnEntry,
-                                               uint32_t ulBitsToClearOnExit,
-                                               uint32_t * pulNotificationValue,
-                                               TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                               uint32_t ulBitsToClearOnEntry,
-                                               uint32_t ulBitsToClearOnExit,
-                                               uint32_t * pulNotificationValue,
-                                               TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
@@ -951,11 +856,8 @@
                 " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGenericNotifyWaitImpl                 \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory"
             );
         }
 
@@ -987,11 +889,8 @@
                 " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGenericNotifyTakeImpl                \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory"
             );
         }
 
@@ -1021,11 +920,8 @@
                 " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGenericNotifyStateClearImpl           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory"
             );
         }
 
@@ -1057,11 +953,8 @@
                 " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGenericNotifyValueClearImpl          \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory"
             );
         }
 
@@ -1093,11 +986,8 @@
             " MPU_xQueueGenericSend_Unpriv:                         \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueueGenericSendImpl                      \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1121,11 +1011,8 @@
             " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_uxQueueMessagesWaitingImpl                 \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1149,11 +1036,8 @@
             " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_uxQueueSpacesAvailableImpl                 \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1181,11 +1065,8 @@
             " MPU_xQueueReceive_Unpriv:                             \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueueReceiveImpl                          \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1213,11 +1094,8 @@
             " MPU_xQueuePeek_Unpriv:                                \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueuePeekImpl                             \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1243,11 +1121,8 @@
             " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueueSemaphoreTakeImpl                    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1273,11 +1148,8 @@
                 " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueGetMutexHolderImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory"
             );
         }
 
@@ -1307,11 +1179,8 @@
                 " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueTakeMutexRecursiveImpl               \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory"
             );
         }
 
@@ -1339,11 +1208,8 @@
                 " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueGiveMutexRecursiveImpl               \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory"
             );
         }
 
@@ -1373,11 +1239,8 @@
                 " MPU_xQueueSelectFromSet_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueSelectFromSetImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory"
             );
         }
 
@@ -1407,11 +1270,8 @@
                 " MPU_xQueueAddToSet_Unpriv:                            \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueAddToSetImpl                         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory"
             );
         }
 
@@ -1441,11 +1301,8 @@
                 " MPU_vQueueAddToRegistry_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vQueueAddToRegistryImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory"
             );
         }
 
@@ -1473,11 +1330,8 @@
                 " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vQueueUnregisterQueueImpl                  \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory"
             );
         }
 
@@ -1505,11 +1359,8 @@
                 " MPU_pcQueueGetName_Unpriv:                            \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pcQueueGetNameImpl                         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory"
             );
         }
 
@@ -1537,11 +1388,8 @@
                 " MPU_pvTimerGetTimerID_Unpriv:                         \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pvTimerGetTimerIDImpl                      \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory"
             );
         }
 
@@ -1571,11 +1419,8 @@
                 " MPU_vTimerSetTimerID_Unpriv:                          \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTimerSetTimerIDImpl                       \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory"
             );
         }
 
@@ -1603,11 +1448,8 @@
                 " MPU_xTimerIsTimerActive_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerIsTimerActiveImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory"
             );
         }
 
@@ -1635,11 +1477,8 @@
                 " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetTimerDaemonTaskHandleImpl         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory"
             );
         }
 
@@ -1648,17 +1487,9 @@
 
     #if ( configUSE_TIMERS == 1 )
 
-        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                                     const BaseType_t xCommandID,
-                                                     const TickType_t xOptionalValue,
-                                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                                     const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                                     const BaseType_t xCommandID,
-                                                     const TickType_t xOptionalValue,
-                                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                                     const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
@@ -1675,11 +1506,8 @@
                 " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
                 "     pop {r0}                                                  \n"
                 "     svc %0                                                    \n"
-                "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
-                "     svc %1                                                    \n"
-                "     bx lr                                                     \n"
                 "                                                               \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory"
             );
         }
 
@@ -1707,11 +1535,8 @@
                 " MPU_pcTimerGetName_Unpriv:                            \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pcTimerGetNameImpl                         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory"
             );
         }
 
@@ -1741,11 +1566,8 @@
                 " MPU_vTimerSetReloadMode_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTimerSetReloadModeImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory"
             );
         }
 
@@ -1773,11 +1595,8 @@
                 " MPU_xTimerGetReloadMode_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetReloadModeImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory"
             );
         }
 
@@ -1805,11 +1624,8 @@
                 " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTimerGetReloadModeImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory"
             );
         }
 
@@ -1837,11 +1653,8 @@
                 " MPU_xTimerGetPeriod_Unpriv:                           \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetPeriodImpl                        \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory"
             );
         }
 
@@ -1869,28 +1682,17 @@
                 " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetExpiryTimeImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory"
             );
         }
 
     #endif /* if ( configUSE_TIMERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
-                                         const EventBits_t uxBitsToWaitFor,
-                                         const BaseType_t xClearOnExit,
-                                         const BaseType_t xWaitForAllBits,
-                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
-                                         const EventBits_t uxBitsToWaitFor,
-                                         const BaseType_t xClearOnExit,
-                                         const BaseType_t xWaitForAllBits,
-                                         TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
     {
         __asm volatile
         (
@@ -1907,11 +1709,8 @@
             " MPU_xEventGroupWaitBits_Unpriv:                       \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupWaitBitsImpl                    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1937,11 +1736,8 @@
             " MPU_xEventGroupClearBits_Unpriv:                      \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupClearBitsImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1967,11 +1763,8 @@
             " MPU_xEventGroupSetBits_Unpriv:                        \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupSetBitsImpl                     \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2001,11 +1794,8 @@
             " MPU_xEventGroupSync_Unpriv:                           \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupSyncImpl                        \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2031,11 +1821,8 @@
                 " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxEventGroupGetNumberImpl                  \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory"
             );
         }
 
@@ -2065,11 +1852,8 @@
                 " MPU_vEventGroupSetNumber_Unpriv:                      \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vEventGroupSetNumberImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory"
             );
         }
 
@@ -2101,11 +1885,8 @@
             " MPU_xStreamBufferSend_Unpriv:                         \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferSendImpl                      \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2135,11 +1916,8 @@
             " MPU_xStreamBufferReceive_Unpriv:                      \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferReceiveImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2163,11 +1941,8 @@
             " MPU_xStreamBufferIsFull_Unpriv:                       \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferIsFullImpl                    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2191,11 +1966,8 @@
             " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferIsEmptyImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2219,11 +1991,8 @@
             " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferSpacesAvailableImpl           \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2247,11 +2016,8 @@
             " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferBytesAvailableImpl            \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2277,11 +2043,8 @@
             " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferSetTriggerLevelImpl           \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2305,11 +2068,8 @@
             " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferNextMessageLengthBytesImpl    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM4_MPU/port.c b/portable/GCC/ARM_CM4_MPU/port.c
index e2ef1f054..ac602caaf 100644
--- a/portable/GCC/ARM_CM4_MPU/port.c
+++ b/portable/GCC/ARM_CM4_MPU/port.c
@@ -38,6 +38,7 @@
 /* Scheduler includes. */
 #include "FreeRTOS.h"
 #include "task.h"
+#include "mpu_syscall_numbers.h"
 
 #ifndef __VFP_FP__
     #error This port can only be used when the project options are configured to enable hardware floating point support.
@@ -235,29 +236,22 @@ void vPortSwitchToUserMode( void );
  * @brief Sets up the system call stack so that upon returning from
  * SVC, the system call stack is used.
  *
- * It is used for the system calls with up to 4 parameters.
- *
  * @param pulTaskStack The current SP when the SVC was raised.
  * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ * @param ucSystemCallNumber The system call number of the system call.
  */
     void vSystemCallEnter( uint32_t * pulTaskStack,
-                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
+                           uint32_t ulLR,
+                           uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION;
 
 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
 
 /**
- * @brief Sets up the system call stack so that upon returning from
- * SVC, the system call stack is used.
- *
- * It is used for the system calls with 5 parameters.
- *
- * @param pulTaskStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ * @brief Raise SVC for exiting from a system call.
  */
-    void vSystemCallEnter_1( uint32_t * pulTaskStack,
-                             uint32_t ulLR ) PRIVILEGED_FUNCTION;
+    void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
 
 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
@@ -288,6 +282,15 @@ BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
  * switches can only occur when uxCriticalNesting is zero. */
 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
 
+#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+/*
+ * This variable is set to pdTRUE when the scheduler is started.
+ */
+    PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
+
+#endif
+
 /*
  * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
  * FreeRTOS API functions are not called from interrupts that have been assigned
@@ -366,7 +369,6 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
             ".syntax unified                \n"
             ".extern vSVCHandler_C          \n"
             ".extern vSystemCallEnter       \n"
-            ".extern vSystemCallEnter_1     \n"
             ".extern vSystemCallExit        \n"
             "                               \n"
             "tst lr, #4                     \n"
@@ -377,10 +379,8 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
             "ldr r1, [r0, #24]              \n"
             "ldrb r2, [r1, #-2]             \n"
             "cmp r2, %0                     \n"
-            "beq syscall_enter              \n"
+            "blt syscall_enter              \n"
             "cmp r2, %1                     \n"
-            "beq syscall_enter_1            \n"
-            "cmp r2, %2                     \n"
             "beq syscall_exit               \n"
             "b vSVCHandler_C                \n"
             "                               \n"
@@ -388,16 +388,12 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
             "    mov r1, lr                 \n"
             "    b vSystemCallEnter         \n"
             "                               \n"
-            "syscall_enter_1:               \n"
-            "    mov r1, lr                 \n"
-            "    b vSystemCallEnter_1       \n"
-            "                               \n"
             "syscall_exit:                  \n"
             "    mov r1, lr                 \n"
             "    b vSystemCallExit          \n"
             "                               \n"
             : /* No outputs. */
-            : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT )
+            : "i" ( NUM_SYSTEM_CALLS ), "i" ( portSVC_SYSTEM_CALL_EXIT )
             : "r0", "r1", "r2", "memory"
         );
     }
@@ -430,7 +426,7 @@ void vSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
     uint8_t ucSVCNumber;
     uint32_t ulPC;
 
-    #if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )
+    #if ( ( configUSE_MPU_WRAPPERS_V1 == 1 ) && ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) )
         #if defined( __ARMCC_VERSION )
 
             /* Declaration when these variable are defined in code instead of being
@@ -442,7 +438,7 @@ void vSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
             extern uint32_t __syscalls_flash_start__[];
             extern uint32_t __syscalls_flash_end__[];
         #endif /* #if defined( __ARMCC_VERSION ) */
-    #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
+    #endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 1 ) && ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) ) */
 
     /* The stack contains: r0, r1, r2, r3, r12, LR, PC and xPSR.  The first
      * argument (r0) is pulParam[ 0 ]. */
@@ -468,26 +464,15 @@ void vSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
 
             break;
 
-            #if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )
-                case portSVC_RAISE_PRIVILEGE: /* Only raise the privilege, if the
-                                               * svc was raised from any of the
-                                               * system calls. */
+    #if ( configUSE_MPU_WRAPPERS_V1 == 1 )
+        #if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )
+            case portSVC_RAISE_PRIVILEGE: /* Only raise the privilege, if the
+                                           * svc was raised from any of the
+                                           * system calls. */
 
-                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
-                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
-                    {
-                        __asm volatile
-                        (
-                            "   mrs r1, control     \n" /* Obtain current control value. */
-                            "   bic r1, #1          \n" /* Set privilege bit. */
-                            "   msr control, r1     \n" /* Write back new control value. */
-                            ::: "r1", "memory"
-                        );
-                    }
-
-                    break;
-            #else /* if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
-                case portSVC_RAISE_PRIVILEGE:
+                if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+                    ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+                {
                     __asm volatile
                     (
                         "   mrs r1, control     \n" /* Obtain current control value. */
@@ -495,11 +480,24 @@ void vSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
                         "   msr control, r1     \n" /* Write back new control value. */
                         ::: "r1", "memory"
                     );
-                    break;
-                    #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
+                }
 
-                default: /* Unknown SVC call. */
-                    break;
+                break;
+        #else /* if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
+            case portSVC_RAISE_PRIVILEGE:
+                __asm volatile
+                (
+                    "   mrs r1, control     \n" /* Obtain current control value. */
+                    "   bic r1, #1          \n" /* Set privilege bit. */
+                    "   msr control, r1     \n" /* Write back new control value. */
+                    ::: "r1", "memory"
+                );
+                break;
+        #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
+    #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+
+        default: /* Unknown SVC call. */
+            break;
     }
 }
 /*-----------------------------------------------------------*/
@@ -507,15 +505,16 @@ void vSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
 
     void vSystemCallEnter( uint32_t * pulTaskStack,
-                           uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
+                           uint32_t ulLR,
+                           uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */
     {
         extern TaskHandle_t pxCurrentTCB;
+        extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ];
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulSystemCallStack;
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
-
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __syscalls_flash_start__;
@@ -527,17 +526,27 @@ void vSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
         #endif /* #if defined( __ARMCC_VERSION ) */
 
         ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
 
-        /* If the request did not come from the system call section, do nothing. */
+        /* Checks:
+         * 1. SVC is raised from the system call section (i.e. application is
+         *    not raising SVC directly).
+         * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as
+         *    it is non-NULL only during the execution of a system call (i.e.
+         *    between system call enter and exit).
+         * 3. System call is not for a kernel API disabled by the configuration
+         *    in FreeRTOSConfig.h.
+         * 4. We do not need to check that ucSystemCallNumber is within range
+         *    because the assembly SVC handler checks that before calling
+         *    this function.
+         */
         if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) &&
+            ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) &&
+            ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) )
         {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
             pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
 
-            /* This is not NULL only for the duration of the system call. */
-            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
-
             if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
             {
                 /* Extended frame i.e. FPU in use. */
@@ -578,10 +587,18 @@ void vSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
              * the system call. */
             pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
 
-            /* Store the value of the Link Register before the SVC was raised. We need to
-             * restore it when we exit from the system call. */
+            /* Store the value of the Link Register before the SVC was raised.
+             * It contains the address of the caller of the System Call entry
+             * point (i.e. the caller of the MPU_<API>). We need to restore it
+             * when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
 
+            /* Start executing the system call upon returning from this handler. */
+            pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
+            /* Raise a request to exit from the system call upon finishing the
+             * system call. */
+            pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit;
+
             /* Record if the hardware used padding to force the stack pointer
              * to be double word aligned. */
             if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
@@ -605,108 +622,9 @@ void vSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
 
 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
 
-    void vSystemCallEnter_1( uint32_t * pulTaskStack,
-                             uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
+    void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */
     {
-        extern TaskHandle_t pxCurrentTCB;
-        xMPU_SETTINGS * pxMpuSettings;
-        uint32_t * pulSystemCallStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-
-        #if defined( __ARMCC_VERSION )
-
-            /* Declaration when these variable are defined in code instead of being
-             * exported from linker scripts. */
-            extern uint32_t * __syscalls_flash_start__;
-            extern uint32_t * __syscalls_flash_end__;
-        #else
-            /* Declaration when these variable are exported from linker scripts. */
-            extern uint32_t __syscalls_flash_start__[];
-            extern uint32_t __syscalls_flash_end__[];
-        #endif /* #if defined( __ARMCC_VERSION ) */
-
-        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-        /* If the request did not come from the system call section, do nothing. */
-        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
-        {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
-
-            /* This is not NULL only for the duration of the system call. */
-            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
-
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
-            {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                    ::: "memory"
-                    );
-            }
-            else
-            {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
-            }
-
-            /* Make space on the system call stack for the stack frame and
-             * the parameter passed on the stack. We only need to copy one
-             * parameter but we still reserve 2 spaces to keep the stack
-             * double word aligned. */
-            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
-
-            /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
-            {
-                pulSystemCallStack[ i ] = pulTaskStack[ i ];
-            }
-
-            /* Copy the parameter which is passed the stack. */
-            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-            {
-                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
-
-                /* Record if the hardware used padding to force the stack pointer
-                 * to be double word aligned. */
-                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-            }
-            else
-            {
-                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
-
-                /* Record if the hardware used padding to force the stack pointer
-                 * to be double word aligned. */
-                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-            }
-
-            /* Use the pulSystemCallStack in thread mode. */
-            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-
-            /* Raise the privilege for the duration of the system call. */
-            __asm volatile (
-                " mrs r1, control     \n" /* Obtain current control value. */
-                " bic r1, #1          \n" /* Clear nPRIV bit. */
-                " msr control, r1     \n" /* Write back new control value. */
-                ::: "r1", "memory"
-                );
-
-            /* Remember the location where we should copy the stack frame when we exit from
-             * the system call. */
-            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-            /* Store the value of the Link Register before the SVC was raised. We need to
-             * restore it when we exit from the system call. */
-            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-
-            /* We ensure in pxPortInitialiseStack that the system call stack is
-             * double word aligned and therefore, there is no need of padding.
-             * Clear the bit[9] of stacked xPSR. */
-            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-        }
+        __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" );
     }
 
 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@@ -723,24 +641,32 @@ void vSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
-
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
-            extern uint32_t * __syscalls_flash_start__;
-            extern uint32_t * __syscalls_flash_end__;
+            extern uint32_t * __privileged_functions_start__;
+            extern uint32_t * __privileged_functions_end__;
         #else
             /* Declaration when these variable are exported from linker scripts. */
-            extern uint32_t __syscalls_flash_start__[];
-            extern uint32_t __syscalls_flash_end__[];
+            extern uint32_t __privileged_functions_start__[];
+            extern uint32_t __privileged_functions_end__[];
         #endif /* #if defined( __ARMCC_VERSION ) */
 
         ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
+        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
 
-        /* If the request did not come from the system call section, do nothing. */
-        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+        /* Checks:
+         * 1. SVC is raised from the privileged code (i.e. application is not
+         *    raising SVC directly). This SVC is only raised from
+         *    vRequestSystemCallExit which is in the privileged code section.
+         * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL -
+         *    this means that we previously entered a system call and the
+         *    application is not attempting to exit without entering a system
+         *    call.
+         */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) &&
+            ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) )
         {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
             pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
 
             if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
@@ -779,8 +705,10 @@ void vSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
                 ::: "r1", "memory"
                 );
 
-            /* Restore the stacked link register to what it was at the time of
-             * system call entry. */
+            /* Return to the caller of the System Call entry point (i.e. the
+             * caller of the MPU_<API>). */
+            pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+            /* Ensure that LR has a valid value.*/
             pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
 
             /* If the hardware used padding to force the stack pointer
@@ -995,6 +923,12 @@ BaseType_t xPortStartScheduler( void )
     /* Initialise the critical nesting count ready for the first task. */
     uxCriticalNesting = 0;
 
+    #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+    {
+        xSchedulerRunning = pdTRUE;
+    }
+    #endif
+
     /* Ensure the VFP is enabled - it should be anyway. */
     vPortEnableVFP();
 
@@ -1688,21 +1622,34 @@ BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
         {
             uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
             BaseType_t xAccessGranted = pdFALSE;
-            const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+            const xMPU_SETTINGS * xTaskMpuSettings;
 
-            ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
-            ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
-
-            if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+            if( xSchedulerRunning == pdFALSE )
             {
+                /* Grant access to all the kernel objects before the scheduler
+                 * is started. It is necessary because there is no task running
+                 * yet and therefore, we cannot use the permissions of any
+                 * task. */
                 xAccessGranted = pdTRUE;
             }
             else
             {
-                if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+                ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+                ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+                if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
                 {
                     xAccessGranted = pdTRUE;
                 }
+                else
+                {
+                    if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                    {
+                        xAccessGranted = pdTRUE;
+                    }
+                }
             }
 
             return xAccessGranted;
diff --git a/portable/GCC/ARM_CM4_MPU/portmacro.h b/portable/GCC/ARM_CM4_MPU/portmacro.h
index 1f62279b0..4b941e6fa 100644
--- a/portable/GCC/ARM_CM4_MPU/portmacro.h
+++ b/portable/GCC/ARM_CM4_MPU/portmacro.h
@@ -251,12 +251,10 @@ typedef struct MPU_SETTINGS
 /*-----------------------------------------------------------*/
 
 /* SVC numbers for various services. */
-#define portSVC_START_SCHEDULER        0
-#define portSVC_YIELD                  1
-#define portSVC_RAISE_PRIVILEGE        2
-#define portSVC_SYSTEM_CALL_ENTER      3 /* System calls with upto 4 parameters. */
-#define portSVC_SYSTEM_CALL_ENTER_1    4 /* System calls with 5 parameters. */
-#define portSVC_SYSTEM_CALL_EXIT       5
+#define portSVC_START_SCHEDULER        100
+#define portSVC_YIELD                  101
+#define portSVC_RAISE_PRIVILEGE        102
+#define portSVC_SYSTEM_CALL_EXIT       103
 
 /* Scheduler utilities. */
 
diff --git a/portable/GCC/ARM_CM55/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM55/non_secure/mpu_wrappers_v2_asm.c
index d1fbdc0e5..4cb310afd 100644
--- a/portable/GCC/ARM_CM55/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM55/non_secure/mpu_wrappers_v2_asm.c
@@ -38,6 +38,8 @@
 #include "timers.h"
 #include "event_groups.h"
 #include "stream_buffer.h"
+#include "mpu_prototypes.h"
+#include "mpu_syscall_numbers.h"
 
 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
 /*-----------------------------------------------------------*/
@@ -67,11 +69,8 @@
                 " MPU_xTaskDelayUntil_Unpriv:                           \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskDelayUntilImpl                        \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory"
             );
         }
 
@@ -99,11 +98,8 @@
                 " MPU_xTaskAbortDelay_Unpriv:                           \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskAbortDelayImpl                        \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory"
             );
         }
 
@@ -131,11 +127,8 @@
                 " MPU_vTaskDelay_Unpriv:                                \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskDelayImpl                             \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory"
             );
         }
 
@@ -163,11 +156,8 @@
                 " MPU_uxTaskPriorityGet_Unpriv:                         \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskPriorityGetImpl                      \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory"
             );
         }
 
@@ -195,11 +185,8 @@
                 " MPU_eTaskGetState_Unpriv:                             \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_eTaskGetStateImpl                          \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory"
             );
         }
 
@@ -233,11 +220,8 @@
                 " MPU_vTaskGetInfo_Unpriv:                              \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskGetInfoImpl                           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory"
             );
         }
 
@@ -265,11 +249,8 @@
                 " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetIdleTaskHandleImpl                 \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory"
             );
         }
 
@@ -297,11 +278,8 @@
                 " MPU_vTaskSuspend_Unpriv:                              \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskSuspendImpl                           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory"
             );
         }
 
@@ -329,11 +307,8 @@
                 " MPU_vTaskResume_Unpriv:                               \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskResumeImpl                            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskResume ) : "memory"
             );
         }
 
@@ -359,11 +334,8 @@
             " MPU_xTaskGetTickCount_Unpriv:                         \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xTaskGetTickCountImpl                      \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -387,11 +359,8 @@
             " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_uxTaskGetNumberOfTasksImpl                 \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -417,11 +386,8 @@
                 " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetRunTimeCounterImpl                \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory"
             );
         }
 
@@ -449,11 +415,8 @@
                 " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetRunTimePercentImpl                \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory"
             );
         }
 
@@ -481,11 +444,8 @@
                 " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetIdleRunTimePercentImpl            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory"
             );
         }
 
@@ -513,11 +473,8 @@
                 " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetIdleRunTimeCounterImpl            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory"
             );
         }
 
@@ -547,11 +504,8 @@
                 " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskSetApplicationTaskTagImpl             \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory"
             );
         }
 
@@ -579,11 +533,8 @@
                 " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetApplicationTaskTagImpl             \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory"
             );
         }
 
@@ -615,11 +566,8 @@
                 " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskSetThreadLocalStoragePointerImpl      \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory"
             );
         }
 
@@ -649,11 +597,8 @@
                 " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pvTaskGetThreadLocalStoragePointerImpl     \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory"
             );
         }
 
@@ -685,11 +630,8 @@
                 " MPU_uxTaskGetSystemState_Unpriv:                      \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskGetSystemStateImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory"
             );
         }
 
@@ -717,11 +659,8 @@
                 " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskGetStackHighWaterMarkImpl            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory"
             );
         }
 
@@ -749,11 +688,8 @@
                 " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskGetStackHighWaterMark2Impl           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory"
             );
         }
 
@@ -781,11 +717,8 @@
                 " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetCurrentTaskHandleImpl              \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory"
             );
         }
 
@@ -813,11 +746,8 @@
                 " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetSchedulerStateImpl                 \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory"
             );
         }
 
@@ -843,11 +773,8 @@
             " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_vTaskSetTimeOutStateImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -873,28 +800,17 @@
             " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xTaskCheckForTimeOutImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
 
     #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                           UBaseType_t uxIndexToNotify,
-                                           uint32_t ulValue,
-                                           eNotifyAction eAction,
-                                           uint32_t * pulPreviousNotificationValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                           UBaseType_t uxIndexToNotify,
-                                           uint32_t ulValue,
-                                           eNotifyAction eAction,
-                                           uint32_t * pulPreviousNotificationValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
@@ -911,11 +827,8 @@
                 " MPU_xTaskGenericNotify_Unpriv:                        \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGenericNotifyImpl                     \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory"
             );
         }
 
@@ -924,17 +837,9 @@
 
     #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                               uint32_t ulBitsToClearOnEntry,
-                                               uint32_t ulBitsToClearOnExit,
-                                               uint32_t * pulNotificationValue,
-                                               TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                               uint32_t ulBitsToClearOnEntry,
-                                               uint32_t ulBitsToClearOnExit,
-                                               uint32_t * pulNotificationValue,
-                                               TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
@@ -951,11 +856,8 @@
                 " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGenericNotifyWaitImpl                 \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory"
             );
         }
 
@@ -987,11 +889,8 @@
                 " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGenericNotifyTakeImpl                \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory"
             );
         }
 
@@ -1021,11 +920,8 @@
                 " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGenericNotifyStateClearImpl           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory"
             );
         }
 
@@ -1057,11 +953,8 @@
                 " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGenericNotifyValueClearImpl          \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory"
             );
         }
 
@@ -1093,11 +986,8 @@
             " MPU_xQueueGenericSend_Unpriv:                         \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueueGenericSendImpl                      \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1121,11 +1011,8 @@
             " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_uxQueueMessagesWaitingImpl                 \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1149,11 +1036,8 @@
             " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_uxQueueSpacesAvailableImpl                 \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1181,11 +1065,8 @@
             " MPU_xQueueReceive_Unpriv:                             \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueueReceiveImpl                          \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1213,11 +1094,8 @@
             " MPU_xQueuePeek_Unpriv:                                \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueuePeekImpl                             \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1243,11 +1121,8 @@
             " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueueSemaphoreTakeImpl                    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1273,11 +1148,8 @@
                 " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueGetMutexHolderImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory"
             );
         }
 
@@ -1307,11 +1179,8 @@
                 " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueTakeMutexRecursiveImpl               \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory"
             );
         }
 
@@ -1339,11 +1208,8 @@
                 " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueGiveMutexRecursiveImpl               \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory"
             );
         }
 
@@ -1373,11 +1239,8 @@
                 " MPU_xQueueSelectFromSet_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueSelectFromSetImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory"
             );
         }
 
@@ -1407,11 +1270,8 @@
                 " MPU_xQueueAddToSet_Unpriv:                            \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueAddToSetImpl                         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory"
             );
         }
 
@@ -1441,11 +1301,8 @@
                 " MPU_vQueueAddToRegistry_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vQueueAddToRegistryImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory"
             );
         }
 
@@ -1473,11 +1330,8 @@
                 " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vQueueUnregisterQueueImpl                  \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory"
             );
         }
 
@@ -1505,11 +1359,8 @@
                 " MPU_pcQueueGetName_Unpriv:                            \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pcQueueGetNameImpl                         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory"
             );
         }
 
@@ -1537,11 +1388,8 @@
                 " MPU_pvTimerGetTimerID_Unpriv:                         \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pvTimerGetTimerIDImpl                      \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory"
             );
         }
 
@@ -1571,11 +1419,8 @@
                 " MPU_vTimerSetTimerID_Unpriv:                          \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTimerSetTimerIDImpl                       \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory"
             );
         }
 
@@ -1603,11 +1448,8 @@
                 " MPU_xTimerIsTimerActive_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerIsTimerActiveImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory"
             );
         }
 
@@ -1635,11 +1477,8 @@
                 " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetTimerDaemonTaskHandleImpl         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory"
             );
         }
 
@@ -1648,17 +1487,9 @@
 
     #if ( configUSE_TIMERS == 1 )
 
-        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                                     const BaseType_t xCommandID,
-                                                     const TickType_t xOptionalValue,
-                                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                                     const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                                     const BaseType_t xCommandID,
-                                                     const TickType_t xOptionalValue,
-                                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                                     const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
@@ -1675,11 +1506,8 @@
                 " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
                 "     pop {r0}                                                  \n"
                 "     svc %0                                                    \n"
-                "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
-                "     svc %1                                                    \n"
-                "     bx lr                                                     \n"
                 "                                                               \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory"
             );
         }
 
@@ -1707,11 +1535,8 @@
                 " MPU_pcTimerGetName_Unpriv:                            \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pcTimerGetNameImpl                         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory"
             );
         }
 
@@ -1741,11 +1566,8 @@
                 " MPU_vTimerSetReloadMode_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTimerSetReloadModeImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory"
             );
         }
 
@@ -1773,11 +1595,8 @@
                 " MPU_xTimerGetReloadMode_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetReloadModeImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory"
             );
         }
 
@@ -1805,11 +1624,8 @@
                 " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTimerGetReloadModeImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory"
             );
         }
 
@@ -1837,11 +1653,8 @@
                 " MPU_xTimerGetPeriod_Unpriv:                           \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetPeriodImpl                        \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory"
             );
         }
 
@@ -1869,28 +1682,17 @@
                 " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetExpiryTimeImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory"
             );
         }
 
     #endif /* if ( configUSE_TIMERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
-                                         const EventBits_t uxBitsToWaitFor,
-                                         const BaseType_t xClearOnExit,
-                                         const BaseType_t xWaitForAllBits,
-                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
-                                         const EventBits_t uxBitsToWaitFor,
-                                         const BaseType_t xClearOnExit,
-                                         const BaseType_t xWaitForAllBits,
-                                         TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
     {
         __asm volatile
         (
@@ -1907,11 +1709,8 @@
             " MPU_xEventGroupWaitBits_Unpriv:                       \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupWaitBitsImpl                    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1937,11 +1736,8 @@
             " MPU_xEventGroupClearBits_Unpriv:                      \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupClearBitsImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1967,11 +1763,8 @@
             " MPU_xEventGroupSetBits_Unpriv:                        \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupSetBitsImpl                     \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2001,11 +1794,8 @@
             " MPU_xEventGroupSync_Unpriv:                           \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupSyncImpl                        \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2031,11 +1821,8 @@
                 " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxEventGroupGetNumberImpl                  \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory"
             );
         }
 
@@ -2065,11 +1852,8 @@
                 " MPU_vEventGroupSetNumber_Unpriv:                      \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vEventGroupSetNumberImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory"
             );
         }
 
@@ -2101,11 +1885,8 @@
             " MPU_xStreamBufferSend_Unpriv:                         \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferSendImpl                      \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2135,11 +1916,8 @@
             " MPU_xStreamBufferReceive_Unpriv:                      \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferReceiveImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2163,11 +1941,8 @@
             " MPU_xStreamBufferIsFull_Unpriv:                       \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferIsFullImpl                    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2191,11 +1966,8 @@
             " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferIsEmptyImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2219,11 +1991,8 @@
             " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferSpacesAvailableImpl           \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2247,11 +2016,8 @@
             " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferBytesAvailableImpl            \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2277,11 +2043,8 @@
             " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferSetTriggerLevelImpl           \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2305,11 +2068,8 @@
             " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferNextMessageLengthBytesImpl    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM55/non_secure/port.c b/portable/GCC/ARM_CM55/non_secure/port.c
index 52d68d3ea..6a3877894 100644
--- a/portable/GCC/ARM_CM55/non_secure/port.c
+++ b/portable/GCC/ARM_CM55/non_secure/port.c
@@ -35,8 +35,9 @@
 #include "FreeRTOS.h"
 #include "task.h"
 
-/* MPU wrappers includes. */
+/* MPU includes. */
 #include "mpu_wrappers.h"
+#include "mpu_syscall_numbers.h"
 
 /* Portasm includes. */
 #include "portasm.h"
@@ -436,29 +437,22 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
  * @brief Sets up the system call stack so that upon returning from
  * SVC, the system call stack is used.
  *
- * It is used for the system calls with up to 4 parameters.
- *
  * @param pulTaskStack The current SP when the SVC was raised.
  * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ * @param ucSystemCallNumber The system call number of the system call.
  */
     void vSystemCallEnter( uint32_t * pulTaskStack,
-                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
+                           uint32_t ulLR,
+                           uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
- * @brief Sets up the system call stack so that upon returning from
- * SVC, the system call stack is used.
- *
- * It is used for the system calls with 5 parameters.
- *
- * @param pulTaskStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ * @brief Raise SVC for exiting from a system call.
  */
-    void vSystemCallEnter_1( uint32_t * pulTaskStack,
-                             uint32_t ulLR ) PRIVILEGED_FUNCTION;
+    void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
@@ -488,6 +482,15 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+/**
+ * @brief This variable is set to pdTRUE when the scheduler is started.
+ */
+    PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
+
+#endif
+
 /**
  * @brief Each task maintains its own interrupt status in the critical nesting
  * variable.
@@ -1134,15 +1137,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     void vSystemCallEnter( uint32_t * pulTaskStack,
-                           uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
+                           uint32_t ulLR,
+                           uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */
     {
         extern TaskHandle_t pxCurrentTCB;
+        extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ];
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulSystemCallStack;
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
-
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __syscalls_flash_start__;
@@ -1154,17 +1158,27 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         #endif /* #if defined( __ARMCC_VERSION ) */
 
         ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
 
-        /* If the request did not come from the system call section, do nothing. */
+        /* Checks:
+         * 1. SVC is raised from the system call section (i.e. application is
+         *    not raising SVC directly).
+         * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as
+         *    it is non-NULL only during the execution of a system call (i.e.
+         *    between system call enter and exit).
+         * 3. System call is not for a kernel API disabled by the configuration
+         *    in FreeRTOSConfig.h.
+         * 4. We do not need to check that ucSystemCallNumber is within range
+         *    because the assembly SVC handler checks that before calling
+         *    this function.
+         */
         if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) &&
+            ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) &&
+            ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) )
         {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
             pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
 
-            /* This is not NULL only for the duration of the system call. */
-            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
-
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
@@ -1198,9 +1212,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 pulSystemCallStack[ i ] = pulTaskStack[ i ];
             }
 
-            /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
-             * restore it when we exit from the system call. */
+            /* Store the value of the Link Register before the SVC was raised.
+             * It contains the address of the caller of the System Call entry
+             * point (i.e. the caller of the MPU_<API>). We need to restore it
+             * when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            /* Store the value of the PSPLIM register before the SVC was raised.
+             * We need to restore it when we exit from the system call. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
             {
                 __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
@@ -1215,6 +1233,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             }
             #endif
 
+            /* Start executing the system call upon returning from this handler. */
+            pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
+            /* Raise a request to exit from the system call upon finishing the
+             * system call. */
+            pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit;
+
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
             pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
@@ -1251,127 +1275,9 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    void vSystemCallEnter_1( uint32_t * pulTaskStack,
-                             uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
+    void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */
     {
-        extern TaskHandle_t pxCurrentTCB;
-        xMPU_SETTINGS * pxMpuSettings;
-        uint32_t * pulSystemCallStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-
-        #if defined( __ARMCC_VERSION )
-
-            /* Declaration when these variable are defined in code instead of being
-             * exported from linker scripts. */
-            extern uint32_t * __syscalls_flash_start__;
-            extern uint32_t * __syscalls_flash_end__;
-        #else
-            /* Declaration when these variable are exported from linker scripts. */
-            extern uint32_t __syscalls_flash_start__[];
-            extern uint32_t __syscalls_flash_end__[];
-        #endif /* #if defined( __ARMCC_VERSION ) */
-
-        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-        /* If the request did not come from the system call section, do nothing. */
-        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
-        {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
-
-            /* This is not NULL only for the duration of the system call. */
-            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
-
-            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-            {
-                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
-                {
-                    /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
-                    __asm volatile (
-                        " vpush {s0}         \n" /* Trigger lazy stacking. */
-                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                        ::: "memory"
-                        );
-                }
-                else
-                {
-                    /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
-                }
-            }
-            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
-            {
-                ulStackFrameSize = 8;
-            }
-            #endif /* configENABLE_FPU || configENABLE_MVE */
-
-            /* Make space on the system call stack for the stack frame and
-             * the parameter passed on the stack. We only need to copy one
-             * parameter but we still reserve 2 spaces to keep the stack
-             * double word aligned. */
-            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
-
-            /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
-            {
-                pulSystemCallStack[ i ] = pulTaskStack[ i ];
-            }
-
-            /* Copy the parameter which is passed the stack. */
-            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-            {
-                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
-
-                /* Record if the hardware used padding to force the stack pointer
-                 * to be double word aligned. */
-                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-            }
-            else
-            {
-                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
-
-                /* Record if the hardware used padding to force the stack pointer
-                 * to be double word aligned. */
-                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-            }
-
-            /* Store the value of the LR and PSPLIM registers before the SVC was raised.
-             * We need to restore it when we exit from the system call. */
-            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            #if ( portUSE_PSPLIM_REGISTER == 1 )
-            {
-                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-            }
-            #endif
-
-            /* Use the pulSystemCallStack in thread mode. */
-            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            #if ( portUSE_PSPLIM_REGISTER == 1 )
-            {
-                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-            }
-            #endif
-
-            /* Remember the location where we should copy the stack frame when we exit from
-             * the system call. */
-            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-            /* We ensure in pxPortInitialiseStack that the system call stack is
-             * double word aligned and therefore, there is no need of padding.
-             * Clear the bit[9] of stacked xPSR. */
-            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-            /* Raise the privilege for the duration of the system call. */
-            __asm volatile (
-                " mrs r0, control     \n" /* Obtain current control value. */
-                " movs r1, #1         \n" /* r1 = 1. */
-                " bics r0, r1         \n" /* Clear nPRIV bit. */
-                " msr control, r0     \n" /* Write back new control value. */
-                ::: "r0", "r1", "memory"
-                );
-        }
+        __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" );
     }
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@@ -1388,24 +1294,32 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
-
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
-            extern uint32_t * __syscalls_flash_start__;
-            extern uint32_t * __syscalls_flash_end__;
+            extern uint32_t * __privileged_functions_start__;
+            extern uint32_t * __privileged_functions_end__;
         #else
             /* Declaration when these variable are exported from linker scripts. */
-            extern uint32_t __syscalls_flash_start__[];
-            extern uint32_t __syscalls_flash_end__[];
+            extern uint32_t __privileged_functions_start__[];
+            extern uint32_t __privileged_functions_end__[];
         #endif /* #if defined( __ARMCC_VERSION ) */
 
         ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
+        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
 
-        /* If the request did not come from the system call section, do nothing. */
-        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+        /* Checks:
+         * 1. SVC is raised from the privileged code (i.e. application is not
+         *    raising SVC directly). This SVC is only raised from
+         *    vRequestSystemCallExit which is in the privileged code section.
+         * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL -
+         *    this means that we previously entered a system call and the
+         *    application is not attempting to exit without entering a system
+         *    call.
+         */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) &&
+            ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) )
         {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
             pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
 
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
@@ -1444,9 +1358,14 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Use the pulTaskStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
 
-            /* Restore the LR and PSPLIM to what they were at the time of
-             * system call entry. */
+            /* Return to the caller of the System Call entry point (i.e. the
+             * caller of the MPU_<API>). */
+            pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+            /* Ensure that LR has a valid value.*/
             pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+
+            /* Restore the PSPLIM register to what it was at the time of
+             * system call entry. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
             {
                 __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
@@ -1780,6 +1699,12 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     /* Initialize the critical nesting count ready for the first task. */
     ulCriticalNesting = 0;
 
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+    {
+        xSchedulerRunning = pdTRUE;
+    }
+    #endif
+
     /* Start the first task. */
     vStartFirstTask();
 
@@ -2062,7 +1987,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
 
     void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
                                          int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
@@ -2078,10 +2003,10 @@ BaseType_t xPortIsInsideInterrupt( void )
         xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit );
     }
 
-#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
 
     void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
                                           int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
@@ -2097,10 +2022,10 @@ BaseType_t xPortIsInsideInterrupt( void )
         xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit );
     }
 
-#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
 
@@ -2108,21 +2033,34 @@ BaseType_t xPortIsInsideInterrupt( void )
         {
             uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
             BaseType_t xAccessGranted = pdFALSE;
-            const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+            const xMPU_SETTINGS * xTaskMpuSettings;
 
-            ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
-            ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
-
-            if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+            if( xSchedulerRunning == pdFALSE )
             {
+                /* Grant access to all the kernel objects before the scheduler
+                 * is started. It is necessary because there is no task running
+                 * yet and therefore, we cannot use the permissions of any
+                 * task. */
                 xAccessGranted = pdTRUE;
             }
             else
             {
-                if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+                ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+                ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+                if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
                 {
                     xAccessGranted = pdTRUE;
                 }
+                else
+                {
+                    if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                    {
+                        xAccessGranted = pdTRUE;
+                    }
+                }
             }
 
             return xAccessGranted;
@@ -2141,5 +2079,5 @@ BaseType_t xPortIsInsideInterrupt( void )
 
     #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
 
-#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM55/non_secure/portasm.c b/portable/GCC/ARM_CM55/non_secure/portasm.c
index ba8f6c62d..16c598ad7 100644
--- a/portable/GCC/ARM_CM55/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM55/non_secure/portasm.c
@@ -36,6 +36,9 @@
 /* Portasm includes. */
 #include "portasm.h"
 
+/* System call numbers includes. */
+#include "mpu_syscall_numbers.h"
+
 /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
  * header files. */
 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
@@ -522,7 +525,6 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             ".syntax unified                \n"
             ".extern vPortSVCHandler_C      \n"
             ".extern vSystemCallEnter       \n"
-            ".extern vSystemCallEnter_1     \n"
             ".extern vSystemCallExit        \n"
             "                               \n"
             "tst lr, #4                     \n"
@@ -533,10 +535,8 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "ldr r1, [r0, #24]              \n"
             "ldrb r2, [r1, #-2]             \n"
             "cmp r2, %0                     \n"
-            "beq syscall_enter              \n"
+            "blt syscall_enter              \n"
             "cmp r2, %1                     \n"
-            "beq syscall_enter_1            \n"
-            "cmp r2, %2                     \n"
             "beq syscall_exit               \n"
             "b vPortSVCHandler_C            \n"
             "                               \n"
@@ -544,16 +544,12 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    mov r1, lr                 \n"
             "    b vSystemCallEnter         \n"
             "                               \n"
-            "syscall_enter_1:               \n"
-            "    mov r1, lr                 \n"
-            "    b vSystemCallEnter_1       \n"
-            "                               \n"
             "syscall_exit:                  \n"
             "    mov r1, lr                 \n"
             "    b vSystemCallExit          \n"
             "                               \n"
             : /* No outputs. */
-            : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT )
+            : "i" ( NUM_SYSTEM_CALLS ), "i" ( portSVC_SYSTEM_CALL_EXIT )
             : "r0", "r1", "r2", "memory"
         );
     }
diff --git a/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h
index 60ef37380..672b0dbdc 100644
--- a/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h
@@ -322,14 +322,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 /**
  * @brief SVC numbers.
  */
-#define portSVC_ALLOCATE_SECURE_CONTEXT    0
-#define portSVC_FREE_SECURE_CONTEXT        1
-#define portSVC_START_SCHEDULER            2
-#define portSVC_RAISE_PRIVILEGE            3
-#define portSVC_SYSTEM_CALL_ENTER          4   /* System calls with upto 4 parameters. */
-#define portSVC_SYSTEM_CALL_ENTER_1        5   /* System calls with 5 parameters. */
-#define portSVC_SYSTEM_CALL_EXIT           6
-#define portSVC_YIELD                      7
+#define portSVC_ALLOCATE_SECURE_CONTEXT    100
+#define portSVC_FREE_SECURE_CONTEXT        101
+#define portSVC_START_SCHEDULER            102
+#define portSVC_RAISE_PRIVILEGE            103
+#define portSVC_SYSTEM_CALL_EXIT           104
+#define portSVC_YIELD                      105
 /*-----------------------------------------------------------*/
 
 /**
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.c
index d1fbdc0e5..4cb310afd 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.c
@@ -38,6 +38,8 @@
 #include "timers.h"
 #include "event_groups.h"
 #include "stream_buffer.h"
+#include "mpu_prototypes.h"
+#include "mpu_syscall_numbers.h"
 
 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
 /*-----------------------------------------------------------*/
@@ -67,11 +69,8 @@
                 " MPU_xTaskDelayUntil_Unpriv:                           \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskDelayUntilImpl                        \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory"
             );
         }
 
@@ -99,11 +98,8 @@
                 " MPU_xTaskAbortDelay_Unpriv:                           \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskAbortDelayImpl                        \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory"
             );
         }
 
@@ -131,11 +127,8 @@
                 " MPU_vTaskDelay_Unpriv:                                \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskDelayImpl                             \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory"
             );
         }
 
@@ -163,11 +156,8 @@
                 " MPU_uxTaskPriorityGet_Unpriv:                         \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskPriorityGetImpl                      \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory"
             );
         }
 
@@ -195,11 +185,8 @@
                 " MPU_eTaskGetState_Unpriv:                             \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_eTaskGetStateImpl                          \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory"
             );
         }
 
@@ -233,11 +220,8 @@
                 " MPU_vTaskGetInfo_Unpriv:                              \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskGetInfoImpl                           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory"
             );
         }
 
@@ -265,11 +249,8 @@
                 " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetIdleTaskHandleImpl                 \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory"
             );
         }
 
@@ -297,11 +278,8 @@
                 " MPU_vTaskSuspend_Unpriv:                              \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskSuspendImpl                           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory"
             );
         }
 
@@ -329,11 +307,8 @@
                 " MPU_vTaskResume_Unpriv:                               \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskResumeImpl                            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskResume ) : "memory"
             );
         }
 
@@ -359,11 +334,8 @@
             " MPU_xTaskGetTickCount_Unpriv:                         \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xTaskGetTickCountImpl                      \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -387,11 +359,8 @@
             " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_uxTaskGetNumberOfTasksImpl                 \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -417,11 +386,8 @@
                 " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetRunTimeCounterImpl                \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory"
             );
         }
 
@@ -449,11 +415,8 @@
                 " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetRunTimePercentImpl                \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory"
             );
         }
 
@@ -481,11 +444,8 @@
                 " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetIdleRunTimePercentImpl            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory"
             );
         }
 
@@ -513,11 +473,8 @@
                 " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetIdleRunTimeCounterImpl            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory"
             );
         }
 
@@ -547,11 +504,8 @@
                 " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskSetApplicationTaskTagImpl             \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory"
             );
         }
 
@@ -579,11 +533,8 @@
                 " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetApplicationTaskTagImpl             \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory"
             );
         }
 
@@ -615,11 +566,8 @@
                 " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskSetThreadLocalStoragePointerImpl      \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory"
             );
         }
 
@@ -649,11 +597,8 @@
                 " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pvTaskGetThreadLocalStoragePointerImpl     \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory"
             );
         }
 
@@ -685,11 +630,8 @@
                 " MPU_uxTaskGetSystemState_Unpriv:                      \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskGetSystemStateImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory"
             );
         }
 
@@ -717,11 +659,8 @@
                 " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskGetStackHighWaterMarkImpl            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory"
             );
         }
 
@@ -749,11 +688,8 @@
                 " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskGetStackHighWaterMark2Impl           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory"
             );
         }
 
@@ -781,11 +717,8 @@
                 " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetCurrentTaskHandleImpl              \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory"
             );
         }
 
@@ -813,11 +746,8 @@
                 " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetSchedulerStateImpl                 \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory"
             );
         }
 
@@ -843,11 +773,8 @@
             " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_vTaskSetTimeOutStateImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -873,28 +800,17 @@
             " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xTaskCheckForTimeOutImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
 
     #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                           UBaseType_t uxIndexToNotify,
-                                           uint32_t ulValue,
-                                           eNotifyAction eAction,
-                                           uint32_t * pulPreviousNotificationValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                           UBaseType_t uxIndexToNotify,
-                                           uint32_t ulValue,
-                                           eNotifyAction eAction,
-                                           uint32_t * pulPreviousNotificationValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
@@ -911,11 +827,8 @@
                 " MPU_xTaskGenericNotify_Unpriv:                        \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGenericNotifyImpl                     \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory"
             );
         }
 
@@ -924,17 +837,9 @@
 
     #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                               uint32_t ulBitsToClearOnEntry,
-                                               uint32_t ulBitsToClearOnExit,
-                                               uint32_t * pulNotificationValue,
-                                               TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                               uint32_t ulBitsToClearOnEntry,
-                                               uint32_t ulBitsToClearOnExit,
-                                               uint32_t * pulNotificationValue,
-                                               TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
@@ -951,11 +856,8 @@
                 " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGenericNotifyWaitImpl                 \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory"
             );
         }
 
@@ -987,11 +889,8 @@
                 " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGenericNotifyTakeImpl                \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory"
             );
         }
 
@@ -1021,11 +920,8 @@
                 " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGenericNotifyStateClearImpl           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory"
             );
         }
 
@@ -1057,11 +953,8 @@
                 " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGenericNotifyValueClearImpl          \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory"
             );
         }
 
@@ -1093,11 +986,8 @@
             " MPU_xQueueGenericSend_Unpriv:                         \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueueGenericSendImpl                      \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1121,11 +1011,8 @@
             " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_uxQueueMessagesWaitingImpl                 \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1149,11 +1036,8 @@
             " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_uxQueueSpacesAvailableImpl                 \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1181,11 +1065,8 @@
             " MPU_xQueueReceive_Unpriv:                             \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueueReceiveImpl                          \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1213,11 +1094,8 @@
             " MPU_xQueuePeek_Unpriv:                                \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueuePeekImpl                             \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1243,11 +1121,8 @@
             " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueueSemaphoreTakeImpl                    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1273,11 +1148,8 @@
                 " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueGetMutexHolderImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory"
             );
         }
 
@@ -1307,11 +1179,8 @@
                 " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueTakeMutexRecursiveImpl               \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory"
             );
         }
 
@@ -1339,11 +1208,8 @@
                 " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueGiveMutexRecursiveImpl               \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory"
             );
         }
 
@@ -1373,11 +1239,8 @@
                 " MPU_xQueueSelectFromSet_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueSelectFromSetImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory"
             );
         }
 
@@ -1407,11 +1270,8 @@
                 " MPU_xQueueAddToSet_Unpriv:                            \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueAddToSetImpl                         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory"
             );
         }
 
@@ -1441,11 +1301,8 @@
                 " MPU_vQueueAddToRegistry_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vQueueAddToRegistryImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory"
             );
         }
 
@@ -1473,11 +1330,8 @@
                 " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vQueueUnregisterQueueImpl                  \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory"
             );
         }
 
@@ -1505,11 +1359,8 @@
                 " MPU_pcQueueGetName_Unpriv:                            \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pcQueueGetNameImpl                         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory"
             );
         }
 
@@ -1537,11 +1388,8 @@
                 " MPU_pvTimerGetTimerID_Unpriv:                         \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pvTimerGetTimerIDImpl                      \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory"
             );
         }
 
@@ -1571,11 +1419,8 @@
                 " MPU_vTimerSetTimerID_Unpriv:                          \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTimerSetTimerIDImpl                       \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory"
             );
         }
 
@@ -1603,11 +1448,8 @@
                 " MPU_xTimerIsTimerActive_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerIsTimerActiveImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory"
             );
         }
 
@@ -1635,11 +1477,8 @@
                 " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetTimerDaemonTaskHandleImpl         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory"
             );
         }
 
@@ -1648,17 +1487,9 @@
 
     #if ( configUSE_TIMERS == 1 )
 
-        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                                     const BaseType_t xCommandID,
-                                                     const TickType_t xOptionalValue,
-                                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                                     const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                                     const BaseType_t xCommandID,
-                                                     const TickType_t xOptionalValue,
-                                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                                     const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
@@ -1675,11 +1506,8 @@
                 " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
                 "     pop {r0}                                                  \n"
                 "     svc %0                                                    \n"
-                "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
-                "     svc %1                                                    \n"
-                "     bx lr                                                     \n"
                 "                                                               \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory"
             );
         }
 
@@ -1707,11 +1535,8 @@
                 " MPU_pcTimerGetName_Unpriv:                            \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pcTimerGetNameImpl                         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory"
             );
         }
 
@@ -1741,11 +1566,8 @@
                 " MPU_vTimerSetReloadMode_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTimerSetReloadModeImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory"
             );
         }
 
@@ -1773,11 +1595,8 @@
                 " MPU_xTimerGetReloadMode_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetReloadModeImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory"
             );
         }
 
@@ -1805,11 +1624,8 @@
                 " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTimerGetReloadModeImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory"
             );
         }
 
@@ -1837,11 +1653,8 @@
                 " MPU_xTimerGetPeriod_Unpriv:                           \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetPeriodImpl                        \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory"
             );
         }
 
@@ -1869,28 +1682,17 @@
                 " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetExpiryTimeImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory"
             );
         }
 
     #endif /* if ( configUSE_TIMERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
-                                         const EventBits_t uxBitsToWaitFor,
-                                         const BaseType_t xClearOnExit,
-                                         const BaseType_t xWaitForAllBits,
-                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
-                                         const EventBits_t uxBitsToWaitFor,
-                                         const BaseType_t xClearOnExit,
-                                         const BaseType_t xWaitForAllBits,
-                                         TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
     {
         __asm volatile
         (
@@ -1907,11 +1709,8 @@
             " MPU_xEventGroupWaitBits_Unpriv:                       \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupWaitBitsImpl                    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1937,11 +1736,8 @@
             " MPU_xEventGroupClearBits_Unpriv:                      \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupClearBitsImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1967,11 +1763,8 @@
             " MPU_xEventGroupSetBits_Unpriv:                        \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupSetBitsImpl                     \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2001,11 +1794,8 @@
             " MPU_xEventGroupSync_Unpriv:                           \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupSyncImpl                        \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2031,11 +1821,8 @@
                 " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxEventGroupGetNumberImpl                  \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory"
             );
         }
 
@@ -2065,11 +1852,8 @@
                 " MPU_vEventGroupSetNumber_Unpriv:                      \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vEventGroupSetNumberImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory"
             );
         }
 
@@ -2101,11 +1885,8 @@
             " MPU_xStreamBufferSend_Unpriv:                         \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferSendImpl                      \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2135,11 +1916,8 @@
             " MPU_xStreamBufferReceive_Unpriv:                      \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferReceiveImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2163,11 +1941,8 @@
             " MPU_xStreamBufferIsFull_Unpriv:                       \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferIsFullImpl                    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2191,11 +1966,8 @@
             " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferIsEmptyImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2219,11 +1991,8 @@
             " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferSpacesAvailableImpl           \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2247,11 +2016,8 @@
             " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferBytesAvailableImpl            \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2277,11 +2043,8 @@
             " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferSetTriggerLevelImpl           \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2305,11 +2068,8 @@
             " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferNextMessageLengthBytesImpl    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/port.c b/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
index 52d68d3ea..6a3877894 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
@@ -35,8 +35,9 @@
 #include "FreeRTOS.h"
 #include "task.h"
 
-/* MPU wrappers includes. */
+/* MPU includes. */
 #include "mpu_wrappers.h"
+#include "mpu_syscall_numbers.h"
 
 /* Portasm includes. */
 #include "portasm.h"
@@ -436,29 +437,22 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
  * @brief Sets up the system call stack so that upon returning from
  * SVC, the system call stack is used.
  *
- * It is used for the system calls with up to 4 parameters.
- *
  * @param pulTaskStack The current SP when the SVC was raised.
  * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ * @param ucSystemCallNumber The system call number of the system call.
  */
     void vSystemCallEnter( uint32_t * pulTaskStack,
-                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
+                           uint32_t ulLR,
+                           uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
- * @brief Sets up the system call stack so that upon returning from
- * SVC, the system call stack is used.
- *
- * It is used for the system calls with 5 parameters.
- *
- * @param pulTaskStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ * @brief Raise SVC for exiting from a system call.
  */
-    void vSystemCallEnter_1( uint32_t * pulTaskStack,
-                             uint32_t ulLR ) PRIVILEGED_FUNCTION;
+    void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
@@ -488,6 +482,15 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+/**
+ * @brief This variable is set to pdTRUE when the scheduler is started.
+ */
+    PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
+
+#endif
+
 /**
  * @brief Each task maintains its own interrupt status in the critical nesting
  * variable.
@@ -1134,15 +1137,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     void vSystemCallEnter( uint32_t * pulTaskStack,
-                           uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
+                           uint32_t ulLR,
+                           uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */
     {
         extern TaskHandle_t pxCurrentTCB;
+        extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ];
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulSystemCallStack;
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
-
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __syscalls_flash_start__;
@@ -1154,17 +1158,27 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         #endif /* #if defined( __ARMCC_VERSION ) */
 
         ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
 
-        /* If the request did not come from the system call section, do nothing. */
+        /* Checks:
+         * 1. SVC is raised from the system call section (i.e. application is
+         *    not raising SVC directly).
+         * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as
+         *    it is non-NULL only during the execution of a system call (i.e.
+         *    between system call enter and exit).
+         * 3. System call is not for a kernel API disabled by the configuration
+         *    in FreeRTOSConfig.h.
+         * 4. We do not need to check that ucSystemCallNumber is within range
+         *    because the assembly SVC handler checks that before calling
+         *    this function.
+         */
         if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) &&
+            ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) &&
+            ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) )
         {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
             pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
 
-            /* This is not NULL only for the duration of the system call. */
-            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
-
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
@@ -1198,9 +1212,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 pulSystemCallStack[ i ] = pulTaskStack[ i ];
             }
 
-            /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
-             * restore it when we exit from the system call. */
+            /* Store the value of the Link Register before the SVC was raised.
+             * It contains the address of the caller of the System Call entry
+             * point (i.e. the caller of the MPU_<API>). We need to restore it
+             * when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            /* Store the value of the PSPLIM register before the SVC was raised.
+             * We need to restore it when we exit from the system call. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
             {
                 __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
@@ -1215,6 +1233,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             }
             #endif
 
+            /* Start executing the system call upon returning from this handler. */
+            pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
+            /* Raise a request to exit from the system call upon finishing the
+             * system call. */
+            pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit;
+
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
             pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
@@ -1251,127 +1275,9 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    void vSystemCallEnter_1( uint32_t * pulTaskStack,
-                             uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
+    void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */
     {
-        extern TaskHandle_t pxCurrentTCB;
-        xMPU_SETTINGS * pxMpuSettings;
-        uint32_t * pulSystemCallStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-
-        #if defined( __ARMCC_VERSION )
-
-            /* Declaration when these variable are defined in code instead of being
-             * exported from linker scripts. */
-            extern uint32_t * __syscalls_flash_start__;
-            extern uint32_t * __syscalls_flash_end__;
-        #else
-            /* Declaration when these variable are exported from linker scripts. */
-            extern uint32_t __syscalls_flash_start__[];
-            extern uint32_t __syscalls_flash_end__[];
-        #endif /* #if defined( __ARMCC_VERSION ) */
-
-        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-        /* If the request did not come from the system call section, do nothing. */
-        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
-        {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
-
-            /* This is not NULL only for the duration of the system call. */
-            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
-
-            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-            {
-                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
-                {
-                    /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
-                    __asm volatile (
-                        " vpush {s0}         \n" /* Trigger lazy stacking. */
-                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                        ::: "memory"
-                        );
-                }
-                else
-                {
-                    /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
-                }
-            }
-            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
-            {
-                ulStackFrameSize = 8;
-            }
-            #endif /* configENABLE_FPU || configENABLE_MVE */
-
-            /* Make space on the system call stack for the stack frame and
-             * the parameter passed on the stack. We only need to copy one
-             * parameter but we still reserve 2 spaces to keep the stack
-             * double word aligned. */
-            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
-
-            /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
-            {
-                pulSystemCallStack[ i ] = pulTaskStack[ i ];
-            }
-
-            /* Copy the parameter which is passed the stack. */
-            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-            {
-                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
-
-                /* Record if the hardware used padding to force the stack pointer
-                 * to be double word aligned. */
-                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-            }
-            else
-            {
-                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
-
-                /* Record if the hardware used padding to force the stack pointer
-                 * to be double word aligned. */
-                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-            }
-
-            /* Store the value of the LR and PSPLIM registers before the SVC was raised.
-             * We need to restore it when we exit from the system call. */
-            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            #if ( portUSE_PSPLIM_REGISTER == 1 )
-            {
-                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-            }
-            #endif
-
-            /* Use the pulSystemCallStack in thread mode. */
-            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            #if ( portUSE_PSPLIM_REGISTER == 1 )
-            {
-                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-            }
-            #endif
-
-            /* Remember the location where we should copy the stack frame when we exit from
-             * the system call. */
-            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-            /* We ensure in pxPortInitialiseStack that the system call stack is
-             * double word aligned and therefore, there is no need of padding.
-             * Clear the bit[9] of stacked xPSR. */
-            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-            /* Raise the privilege for the duration of the system call. */
-            __asm volatile (
-                " mrs r0, control     \n" /* Obtain current control value. */
-                " movs r1, #1         \n" /* r1 = 1. */
-                " bics r0, r1         \n" /* Clear nPRIV bit. */
-                " msr control, r0     \n" /* Write back new control value. */
-                ::: "r0", "r1", "memory"
-                );
-        }
+        __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" );
     }
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@@ -1388,24 +1294,32 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
-
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
-            extern uint32_t * __syscalls_flash_start__;
-            extern uint32_t * __syscalls_flash_end__;
+            extern uint32_t * __privileged_functions_start__;
+            extern uint32_t * __privileged_functions_end__;
         #else
             /* Declaration when these variable are exported from linker scripts. */
-            extern uint32_t __syscalls_flash_start__[];
-            extern uint32_t __syscalls_flash_end__[];
+            extern uint32_t __privileged_functions_start__[];
+            extern uint32_t __privileged_functions_end__[];
         #endif /* #if defined( __ARMCC_VERSION ) */
 
         ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
+        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
 
-        /* If the request did not come from the system call section, do nothing. */
-        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+        /* Checks:
+         * 1. SVC is raised from the privileged code (i.e. application is not
+         *    raising SVC directly). This SVC is only raised from
+         *    vRequestSystemCallExit which is in the privileged code section.
+         * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL -
+         *    this means that we previously entered a system call and the
+         *    application is not attempting to exit without entering a system
+         *    call.
+         */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) &&
+            ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) )
         {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
             pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
 
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
@@ -1444,9 +1358,14 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Use the pulTaskStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
 
-            /* Restore the LR and PSPLIM to what they were at the time of
-             * system call entry. */
+            /* Return to the caller of the System Call entry point (i.e. the
+             * caller of the MPU_<API>). */
+            pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+            /* Ensure that LR has a valid value.*/
             pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+
+            /* Restore the PSPLIM register to what it was at the time of
+             * system call entry. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
             {
                 __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
@@ -1780,6 +1699,12 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     /* Initialize the critical nesting count ready for the first task. */
     ulCriticalNesting = 0;
 
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+    {
+        xSchedulerRunning = pdTRUE;
+    }
+    #endif
+
     /* Start the first task. */
     vStartFirstTask();
 
@@ -2062,7 +1987,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
 
     void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
                                          int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
@@ -2078,10 +2003,10 @@ BaseType_t xPortIsInsideInterrupt( void )
         xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit );
     }
 
-#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
 
     void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
                                           int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
@@ -2097,10 +2022,10 @@ BaseType_t xPortIsInsideInterrupt( void )
         xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit );
     }
 
-#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
 
@@ -2108,21 +2033,34 @@ BaseType_t xPortIsInsideInterrupt( void )
         {
             uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
             BaseType_t xAccessGranted = pdFALSE;
-            const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+            const xMPU_SETTINGS * xTaskMpuSettings;
 
-            ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
-            ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
-
-            if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+            if( xSchedulerRunning == pdFALSE )
             {
+                /* Grant access to all the kernel objects before the scheduler
+                 * is started. It is necessary because there is no task running
+                 * yet and therefore, we cannot use the permissions of any
+                 * task. */
                 xAccessGranted = pdTRUE;
             }
             else
             {
-                if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+                ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+                ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+                if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
                 {
                     xAccessGranted = pdTRUE;
                 }
+                else
+                {
+                    if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                    {
+                        xAccessGranted = pdTRUE;
+                    }
+                }
             }
 
             return xAccessGranted;
@@ -2141,5 +2079,5 @@ BaseType_t xPortIsInsideInterrupt( void )
 
     #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
 
-#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.c b/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.c
index e533dd7e9..76ba642a0 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.c
@@ -36,6 +36,9 @@
 /* Portasm includes. */
 #include "portasm.h"
 
+/* System call numbers includes. */
+#include "mpu_syscall_numbers.h"
+
 /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
  * header files. */
 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
@@ -443,7 +446,6 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             ".syntax unified                \n"
             ".extern vPortSVCHandler_C      \n"
             ".extern vSystemCallEnter       \n"
-            ".extern vSystemCallEnter_1     \n"
             ".extern vSystemCallExit        \n"
             "                               \n"
             "tst lr, #4                     \n"
@@ -454,10 +456,8 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "ldr r1, [r0, #24]              \n"
             "ldrb r2, [r1, #-2]             \n"
             "cmp r2, %0                     \n"
-            "beq syscall_enter              \n"
+            "blt syscall_enter              \n"
             "cmp r2, %1                     \n"
-            "beq syscall_enter_1            \n"
-            "cmp r2, %2                     \n"
             "beq syscall_exit               \n"
             "b vPortSVCHandler_C            \n"
             "                               \n"
@@ -465,16 +465,12 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    mov r1, lr                 \n"
             "    b vSystemCallEnter         \n"
             "                               \n"
-            "syscall_enter_1:               \n"
-            "    mov r1, lr                 \n"
-            "    b vSystemCallEnter_1       \n"
-            "                               \n"
             "syscall_exit:                  \n"
             "    mov r1, lr                 \n"
             "    b vSystemCallExit          \n"
             "                               \n"
             : /* No outputs. */
-            : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT )
+            : "i" ( NUM_SYSTEM_CALLS ), "i" ( portSVC_SYSTEM_CALL_EXIT )
             : "r0", "r1", "r2", "memory"
         );
     }
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h
index 60ef37380..672b0dbdc 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h
@@ -322,14 +322,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 /**
  * @brief SVC numbers.
  */
-#define portSVC_ALLOCATE_SECURE_CONTEXT    0
-#define portSVC_FREE_SECURE_CONTEXT        1
-#define portSVC_START_SCHEDULER            2
-#define portSVC_RAISE_PRIVILEGE            3
-#define portSVC_SYSTEM_CALL_ENTER          4   /* System calls with upto 4 parameters. */
-#define portSVC_SYSTEM_CALL_ENTER_1        5   /* System calls with 5 parameters. */
-#define portSVC_SYSTEM_CALL_EXIT           6
-#define portSVC_YIELD                      7
+#define portSVC_ALLOCATE_SECURE_CONTEXT    100
+#define portSVC_FREE_SECURE_CONTEXT        101
+#define portSVC_START_SCHEDULER            102
+#define portSVC_RAISE_PRIVILEGE            103
+#define portSVC_SYSTEM_CALL_EXIT           104
+#define portSVC_YIELD                      105
 /*-----------------------------------------------------------*/
 
 /**
diff --git a/portable/GCC/ARM_CM85/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM85/non_secure/mpu_wrappers_v2_asm.c
index d1fbdc0e5..4cb310afd 100644
--- a/portable/GCC/ARM_CM85/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM85/non_secure/mpu_wrappers_v2_asm.c
@@ -38,6 +38,8 @@
 #include "timers.h"
 #include "event_groups.h"
 #include "stream_buffer.h"
+#include "mpu_prototypes.h"
+#include "mpu_syscall_numbers.h"
 
 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
 /*-----------------------------------------------------------*/
@@ -67,11 +69,8 @@
                 " MPU_xTaskDelayUntil_Unpriv:                           \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskDelayUntilImpl                        \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory"
             );
         }
 
@@ -99,11 +98,8 @@
                 " MPU_xTaskAbortDelay_Unpriv:                           \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskAbortDelayImpl                        \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory"
             );
         }
 
@@ -131,11 +127,8 @@
                 " MPU_vTaskDelay_Unpriv:                                \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskDelayImpl                             \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory"
             );
         }
 
@@ -163,11 +156,8 @@
                 " MPU_uxTaskPriorityGet_Unpriv:                         \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskPriorityGetImpl                      \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory"
             );
         }
 
@@ -195,11 +185,8 @@
                 " MPU_eTaskGetState_Unpriv:                             \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_eTaskGetStateImpl                          \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory"
             );
         }
 
@@ -233,11 +220,8 @@
                 " MPU_vTaskGetInfo_Unpriv:                              \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskGetInfoImpl                           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory"
             );
         }
 
@@ -265,11 +249,8 @@
                 " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetIdleTaskHandleImpl                 \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory"
             );
         }
 
@@ -297,11 +278,8 @@
                 " MPU_vTaskSuspend_Unpriv:                              \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskSuspendImpl                           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory"
             );
         }
 
@@ -329,11 +307,8 @@
                 " MPU_vTaskResume_Unpriv:                               \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskResumeImpl                            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskResume ) : "memory"
             );
         }
 
@@ -359,11 +334,8 @@
             " MPU_xTaskGetTickCount_Unpriv:                         \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xTaskGetTickCountImpl                      \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -387,11 +359,8 @@
             " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_uxTaskGetNumberOfTasksImpl                 \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -417,11 +386,8 @@
                 " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetRunTimeCounterImpl                \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory"
             );
         }
 
@@ -449,11 +415,8 @@
                 " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetRunTimePercentImpl                \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory"
             );
         }
 
@@ -481,11 +444,8 @@
                 " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetIdleRunTimePercentImpl            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory"
             );
         }
 
@@ -513,11 +473,8 @@
                 " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetIdleRunTimeCounterImpl            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory"
             );
         }
 
@@ -547,11 +504,8 @@
                 " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskSetApplicationTaskTagImpl             \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory"
             );
         }
 
@@ -579,11 +533,8 @@
                 " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetApplicationTaskTagImpl             \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory"
             );
         }
 
@@ -615,11 +566,8 @@
                 " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskSetThreadLocalStoragePointerImpl      \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory"
             );
         }
 
@@ -649,11 +597,8 @@
                 " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pvTaskGetThreadLocalStoragePointerImpl     \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory"
             );
         }
 
@@ -685,11 +630,8 @@
                 " MPU_uxTaskGetSystemState_Unpriv:                      \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskGetSystemStateImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory"
             );
         }
 
@@ -717,11 +659,8 @@
                 " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskGetStackHighWaterMarkImpl            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory"
             );
         }
 
@@ -749,11 +688,8 @@
                 " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskGetStackHighWaterMark2Impl           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory"
             );
         }
 
@@ -781,11 +717,8 @@
                 " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetCurrentTaskHandleImpl              \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory"
             );
         }
 
@@ -813,11 +746,8 @@
                 " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetSchedulerStateImpl                 \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory"
             );
         }
 
@@ -843,11 +773,8 @@
             " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_vTaskSetTimeOutStateImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -873,28 +800,17 @@
             " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xTaskCheckForTimeOutImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
 
     #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                           UBaseType_t uxIndexToNotify,
-                                           uint32_t ulValue,
-                                           eNotifyAction eAction,
-                                           uint32_t * pulPreviousNotificationValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                           UBaseType_t uxIndexToNotify,
-                                           uint32_t ulValue,
-                                           eNotifyAction eAction,
-                                           uint32_t * pulPreviousNotificationValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
@@ -911,11 +827,8 @@
                 " MPU_xTaskGenericNotify_Unpriv:                        \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGenericNotifyImpl                     \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory"
             );
         }
 
@@ -924,17 +837,9 @@
 
     #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                               uint32_t ulBitsToClearOnEntry,
-                                               uint32_t ulBitsToClearOnExit,
-                                               uint32_t * pulNotificationValue,
-                                               TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                               uint32_t ulBitsToClearOnEntry,
-                                               uint32_t ulBitsToClearOnExit,
-                                               uint32_t * pulNotificationValue,
-                                               TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
@@ -951,11 +856,8 @@
                 " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGenericNotifyWaitImpl                 \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory"
             );
         }
 
@@ -987,11 +889,8 @@
                 " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGenericNotifyTakeImpl                \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory"
             );
         }
 
@@ -1021,11 +920,8 @@
                 " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGenericNotifyStateClearImpl           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory"
             );
         }
 
@@ -1057,11 +953,8 @@
                 " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGenericNotifyValueClearImpl          \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory"
             );
         }
 
@@ -1093,11 +986,8 @@
             " MPU_xQueueGenericSend_Unpriv:                         \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueueGenericSendImpl                      \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1121,11 +1011,8 @@
             " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_uxQueueMessagesWaitingImpl                 \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1149,11 +1036,8 @@
             " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_uxQueueSpacesAvailableImpl                 \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1181,11 +1065,8 @@
             " MPU_xQueueReceive_Unpriv:                             \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueueReceiveImpl                          \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1213,11 +1094,8 @@
             " MPU_xQueuePeek_Unpriv:                                \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueuePeekImpl                             \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1243,11 +1121,8 @@
             " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueueSemaphoreTakeImpl                    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1273,11 +1148,8 @@
                 " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueGetMutexHolderImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory"
             );
         }
 
@@ -1307,11 +1179,8 @@
                 " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueTakeMutexRecursiveImpl               \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory"
             );
         }
 
@@ -1339,11 +1208,8 @@
                 " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueGiveMutexRecursiveImpl               \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory"
             );
         }
 
@@ -1373,11 +1239,8 @@
                 " MPU_xQueueSelectFromSet_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueSelectFromSetImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory"
             );
         }
 
@@ -1407,11 +1270,8 @@
                 " MPU_xQueueAddToSet_Unpriv:                            \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueAddToSetImpl                         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory"
             );
         }
 
@@ -1441,11 +1301,8 @@
                 " MPU_vQueueAddToRegistry_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vQueueAddToRegistryImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory"
             );
         }
 
@@ -1473,11 +1330,8 @@
                 " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vQueueUnregisterQueueImpl                  \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory"
             );
         }
 
@@ -1505,11 +1359,8 @@
                 " MPU_pcQueueGetName_Unpriv:                            \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pcQueueGetNameImpl                         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory"
             );
         }
 
@@ -1537,11 +1388,8 @@
                 " MPU_pvTimerGetTimerID_Unpriv:                         \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pvTimerGetTimerIDImpl                      \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory"
             );
         }
 
@@ -1571,11 +1419,8 @@
                 " MPU_vTimerSetTimerID_Unpriv:                          \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTimerSetTimerIDImpl                       \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory"
             );
         }
 
@@ -1603,11 +1448,8 @@
                 " MPU_xTimerIsTimerActive_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerIsTimerActiveImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory"
             );
         }
 
@@ -1635,11 +1477,8 @@
                 " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetTimerDaemonTaskHandleImpl         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory"
             );
         }
 
@@ -1648,17 +1487,9 @@
 
     #if ( configUSE_TIMERS == 1 )
 
-        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                                     const BaseType_t xCommandID,
-                                                     const TickType_t xOptionalValue,
-                                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                                     const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                                     const BaseType_t xCommandID,
-                                                     const TickType_t xOptionalValue,
-                                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                                     const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
@@ -1675,11 +1506,8 @@
                 " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
                 "     pop {r0}                                                  \n"
                 "     svc %0                                                    \n"
-                "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
-                "     svc %1                                                    \n"
-                "     bx lr                                                     \n"
                 "                                                               \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory"
             );
         }
 
@@ -1707,11 +1535,8 @@
                 " MPU_pcTimerGetName_Unpriv:                            \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pcTimerGetNameImpl                         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory"
             );
         }
 
@@ -1741,11 +1566,8 @@
                 " MPU_vTimerSetReloadMode_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTimerSetReloadModeImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory"
             );
         }
 
@@ -1773,11 +1595,8 @@
                 " MPU_xTimerGetReloadMode_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetReloadModeImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory"
             );
         }
 
@@ -1805,11 +1624,8 @@
                 " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTimerGetReloadModeImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory"
             );
         }
 
@@ -1837,11 +1653,8 @@
                 " MPU_xTimerGetPeriod_Unpriv:                           \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetPeriodImpl                        \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory"
             );
         }
 
@@ -1869,28 +1682,17 @@
                 " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetExpiryTimeImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory"
             );
         }
 
     #endif /* if ( configUSE_TIMERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
-                                         const EventBits_t uxBitsToWaitFor,
-                                         const BaseType_t xClearOnExit,
-                                         const BaseType_t xWaitForAllBits,
-                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
-                                         const EventBits_t uxBitsToWaitFor,
-                                         const BaseType_t xClearOnExit,
-                                         const BaseType_t xWaitForAllBits,
-                                         TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
     {
         __asm volatile
         (
@@ -1907,11 +1709,8 @@
             " MPU_xEventGroupWaitBits_Unpriv:                       \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupWaitBitsImpl                    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1937,11 +1736,8 @@
             " MPU_xEventGroupClearBits_Unpriv:                      \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupClearBitsImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1967,11 +1763,8 @@
             " MPU_xEventGroupSetBits_Unpriv:                        \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupSetBitsImpl                     \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2001,11 +1794,8 @@
             " MPU_xEventGroupSync_Unpriv:                           \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupSyncImpl                        \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2031,11 +1821,8 @@
                 " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxEventGroupGetNumberImpl                  \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory"
             );
         }
 
@@ -2065,11 +1852,8 @@
                 " MPU_vEventGroupSetNumber_Unpriv:                      \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vEventGroupSetNumberImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory"
             );
         }
 
@@ -2101,11 +1885,8 @@
             " MPU_xStreamBufferSend_Unpriv:                         \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferSendImpl                      \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2135,11 +1916,8 @@
             " MPU_xStreamBufferReceive_Unpriv:                      \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferReceiveImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2163,11 +1941,8 @@
             " MPU_xStreamBufferIsFull_Unpriv:                       \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferIsFullImpl                    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2191,11 +1966,8 @@
             " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferIsEmptyImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2219,11 +1991,8 @@
             " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferSpacesAvailableImpl           \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2247,11 +2016,8 @@
             " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferBytesAvailableImpl            \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2277,11 +2043,8 @@
             " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferSetTriggerLevelImpl           \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2305,11 +2068,8 @@
             " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferNextMessageLengthBytesImpl    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM85/non_secure/port.c b/portable/GCC/ARM_CM85/non_secure/port.c
index 52d68d3ea..6a3877894 100644
--- a/portable/GCC/ARM_CM85/non_secure/port.c
+++ b/portable/GCC/ARM_CM85/non_secure/port.c
@@ -35,8 +35,9 @@
 #include "FreeRTOS.h"
 #include "task.h"
 
-/* MPU wrappers includes. */
+/* MPU includes. */
 #include "mpu_wrappers.h"
+#include "mpu_syscall_numbers.h"
 
 /* Portasm includes. */
 #include "portasm.h"
@@ -436,29 +437,22 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
  * @brief Sets up the system call stack so that upon returning from
  * SVC, the system call stack is used.
  *
- * It is used for the system calls with up to 4 parameters.
- *
  * @param pulTaskStack The current SP when the SVC was raised.
  * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ * @param ucSystemCallNumber The system call number of the system call.
  */
     void vSystemCallEnter( uint32_t * pulTaskStack,
-                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
+                           uint32_t ulLR,
+                           uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
- * @brief Sets up the system call stack so that upon returning from
- * SVC, the system call stack is used.
- *
- * It is used for the system calls with 5 parameters.
- *
- * @param pulTaskStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ * @brief Raise SVC for exiting from a system call.
  */
-    void vSystemCallEnter_1( uint32_t * pulTaskStack,
-                             uint32_t ulLR ) PRIVILEGED_FUNCTION;
+    void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
@@ -488,6 +482,15 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+/**
+ * @brief This variable is set to pdTRUE when the scheduler is started.
+ */
+    PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
+
+#endif
+
 /**
  * @brief Each task maintains its own interrupt status in the critical nesting
  * variable.
@@ -1134,15 +1137,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     void vSystemCallEnter( uint32_t * pulTaskStack,
-                           uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
+                           uint32_t ulLR,
+                           uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */
     {
         extern TaskHandle_t pxCurrentTCB;
+        extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ];
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulSystemCallStack;
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
-
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __syscalls_flash_start__;
@@ -1154,17 +1158,27 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         #endif /* #if defined( __ARMCC_VERSION ) */
 
         ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
 
-        /* If the request did not come from the system call section, do nothing. */
+        /* Checks:
+         * 1. SVC is raised from the system call section (i.e. application is
+         *    not raising SVC directly).
+         * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as
+         *    it is non-NULL only during the execution of a system call (i.e.
+         *    between system call enter and exit).
+         * 3. System call is not for a kernel API disabled by the configuration
+         *    in FreeRTOSConfig.h.
+         * 4. We do not need to check that ucSystemCallNumber is within range
+         *    because the assembly SVC handler checks that before calling
+         *    this function.
+         */
         if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) &&
+            ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) &&
+            ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) )
         {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
             pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
 
-            /* This is not NULL only for the duration of the system call. */
-            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
-
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
@@ -1198,9 +1212,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 pulSystemCallStack[ i ] = pulTaskStack[ i ];
             }
 
-            /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
-             * restore it when we exit from the system call. */
+            /* Store the value of the Link Register before the SVC was raised.
+             * It contains the address of the caller of the System Call entry
+             * point (i.e. the caller of the MPU_<API>). We need to restore it
+             * when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            /* Store the value of the PSPLIM register before the SVC was raised.
+             * We need to restore it when we exit from the system call. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
             {
                 __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
@@ -1215,6 +1233,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             }
             #endif
 
+            /* Start executing the system call upon returning from this handler. */
+            pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
+            /* Raise a request to exit from the system call upon finishing the
+             * system call. */
+            pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit;
+
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
             pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
@@ -1251,127 +1275,9 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    void vSystemCallEnter_1( uint32_t * pulTaskStack,
-                             uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
+    void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */
     {
-        extern TaskHandle_t pxCurrentTCB;
-        xMPU_SETTINGS * pxMpuSettings;
-        uint32_t * pulSystemCallStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-
-        #if defined( __ARMCC_VERSION )
-
-            /* Declaration when these variable are defined in code instead of being
-             * exported from linker scripts. */
-            extern uint32_t * __syscalls_flash_start__;
-            extern uint32_t * __syscalls_flash_end__;
-        #else
-            /* Declaration when these variable are exported from linker scripts. */
-            extern uint32_t __syscalls_flash_start__[];
-            extern uint32_t __syscalls_flash_end__[];
-        #endif /* #if defined( __ARMCC_VERSION ) */
-
-        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-        /* If the request did not come from the system call section, do nothing. */
-        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
-        {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
-
-            /* This is not NULL only for the duration of the system call. */
-            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
-
-            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-            {
-                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
-                {
-                    /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
-                    __asm volatile (
-                        " vpush {s0}         \n" /* Trigger lazy stacking. */
-                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                        ::: "memory"
-                        );
-                }
-                else
-                {
-                    /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
-                }
-            }
-            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
-            {
-                ulStackFrameSize = 8;
-            }
-            #endif /* configENABLE_FPU || configENABLE_MVE */
-
-            /* Make space on the system call stack for the stack frame and
-             * the parameter passed on the stack. We only need to copy one
-             * parameter but we still reserve 2 spaces to keep the stack
-             * double word aligned. */
-            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
-
-            /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
-            {
-                pulSystemCallStack[ i ] = pulTaskStack[ i ];
-            }
-
-            /* Copy the parameter which is passed the stack. */
-            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-            {
-                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
-
-                /* Record if the hardware used padding to force the stack pointer
-                 * to be double word aligned. */
-                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-            }
-            else
-            {
-                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
-
-                /* Record if the hardware used padding to force the stack pointer
-                 * to be double word aligned. */
-                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-            }
-
-            /* Store the value of the LR and PSPLIM registers before the SVC was raised.
-             * We need to restore it when we exit from the system call. */
-            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            #if ( portUSE_PSPLIM_REGISTER == 1 )
-            {
-                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-            }
-            #endif
-
-            /* Use the pulSystemCallStack in thread mode. */
-            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            #if ( portUSE_PSPLIM_REGISTER == 1 )
-            {
-                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-            }
-            #endif
-
-            /* Remember the location where we should copy the stack frame when we exit from
-             * the system call. */
-            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-            /* We ensure in pxPortInitialiseStack that the system call stack is
-             * double word aligned and therefore, there is no need of padding.
-             * Clear the bit[9] of stacked xPSR. */
-            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-            /* Raise the privilege for the duration of the system call. */
-            __asm volatile (
-                " mrs r0, control     \n" /* Obtain current control value. */
-                " movs r1, #1         \n" /* r1 = 1. */
-                " bics r0, r1         \n" /* Clear nPRIV bit. */
-                " msr control, r0     \n" /* Write back new control value. */
-                ::: "r0", "r1", "memory"
-                );
-        }
+        __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" );
     }
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@@ -1388,24 +1294,32 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
-
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
-            extern uint32_t * __syscalls_flash_start__;
-            extern uint32_t * __syscalls_flash_end__;
+            extern uint32_t * __privileged_functions_start__;
+            extern uint32_t * __privileged_functions_end__;
         #else
             /* Declaration when these variable are exported from linker scripts. */
-            extern uint32_t __syscalls_flash_start__[];
-            extern uint32_t __syscalls_flash_end__[];
+            extern uint32_t __privileged_functions_start__[];
+            extern uint32_t __privileged_functions_end__[];
         #endif /* #if defined( __ARMCC_VERSION ) */
 
         ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
+        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
 
-        /* If the request did not come from the system call section, do nothing. */
-        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+        /* Checks:
+         * 1. SVC is raised from the privileged code (i.e. application is not
+         *    raising SVC directly). This SVC is only raised from
+         *    vRequestSystemCallExit which is in the privileged code section.
+         * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL -
+         *    this means that we previously entered a system call and the
+         *    application is not attempting to exit without entering a system
+         *    call.
+         */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) &&
+            ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) )
         {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
             pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
 
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
@@ -1444,9 +1358,14 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Use the pulTaskStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
 
-            /* Restore the LR and PSPLIM to what they were at the time of
-             * system call entry. */
+            /* Return to the caller of the System Call entry point (i.e. the
+             * caller of the MPU_<API>). */
+            pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+            /* Ensure that LR has a valid value.*/
             pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+
+            /* Restore the PSPLIM register to what it was at the time of
+             * system call entry. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
             {
                 __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
@@ -1780,6 +1699,12 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     /* Initialize the critical nesting count ready for the first task. */
     ulCriticalNesting = 0;
 
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+    {
+        xSchedulerRunning = pdTRUE;
+    }
+    #endif
+
     /* Start the first task. */
     vStartFirstTask();
 
@@ -2062,7 +1987,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
 
     void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
                                          int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
@@ -2078,10 +2003,10 @@ BaseType_t xPortIsInsideInterrupt( void )
         xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit );
     }
 
-#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
 
     void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
                                           int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
@@ -2097,10 +2022,10 @@ BaseType_t xPortIsInsideInterrupt( void )
         xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit );
     }
 
-#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
 
@@ -2108,21 +2033,34 @@ BaseType_t xPortIsInsideInterrupt( void )
         {
             uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
             BaseType_t xAccessGranted = pdFALSE;
-            const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+            const xMPU_SETTINGS * xTaskMpuSettings;
 
-            ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
-            ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
-
-            if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+            if( xSchedulerRunning == pdFALSE )
             {
+                /* Grant access to all the kernel objects before the scheduler
+                 * is started. It is necessary because there is no task running
+                 * yet and therefore, we cannot use the permissions of any
+                 * task. */
                 xAccessGranted = pdTRUE;
             }
             else
             {
-                if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+                ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+                ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+                if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
                 {
                     xAccessGranted = pdTRUE;
                 }
+                else
+                {
+                    if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                    {
+                        xAccessGranted = pdTRUE;
+                    }
+                }
             }
 
             return xAccessGranted;
@@ -2141,5 +2079,5 @@ BaseType_t xPortIsInsideInterrupt( void )
 
     #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
 
-#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM85/non_secure/portasm.c b/portable/GCC/ARM_CM85/non_secure/portasm.c
index ba8f6c62d..16c598ad7 100644
--- a/portable/GCC/ARM_CM85/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM85/non_secure/portasm.c
@@ -36,6 +36,9 @@
 /* Portasm includes. */
 #include "portasm.h"
 
+/* System call numbers includes. */
+#include "mpu_syscall_numbers.h"
+
 /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
  * header files. */
 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
@@ -522,7 +525,6 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             ".syntax unified                \n"
             ".extern vPortSVCHandler_C      \n"
             ".extern vSystemCallEnter       \n"
-            ".extern vSystemCallEnter_1     \n"
             ".extern vSystemCallExit        \n"
             "                               \n"
             "tst lr, #4                     \n"
@@ -533,10 +535,8 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "ldr r1, [r0, #24]              \n"
             "ldrb r2, [r1, #-2]             \n"
             "cmp r2, %0                     \n"
-            "beq syscall_enter              \n"
+            "blt syscall_enter              \n"
             "cmp r2, %1                     \n"
-            "beq syscall_enter_1            \n"
-            "cmp r2, %2                     \n"
             "beq syscall_exit               \n"
             "b vPortSVCHandler_C            \n"
             "                               \n"
@@ -544,16 +544,12 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    mov r1, lr                 \n"
             "    b vSystemCallEnter         \n"
             "                               \n"
-            "syscall_enter_1:               \n"
-            "    mov r1, lr                 \n"
-            "    b vSystemCallEnter_1       \n"
-            "                               \n"
             "syscall_exit:                  \n"
             "    mov r1, lr                 \n"
             "    b vSystemCallExit          \n"
             "                               \n"
             : /* No outputs. */
-            : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT )
+            : "i" ( NUM_SYSTEM_CALLS ), "i" ( portSVC_SYSTEM_CALL_EXIT )
             : "r0", "r1", "r2", "memory"
         );
     }
diff --git a/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h
index 60ef37380..672b0dbdc 100644
--- a/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h
@@ -322,14 +322,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 /**
  * @brief SVC numbers.
  */
-#define portSVC_ALLOCATE_SECURE_CONTEXT    0
-#define portSVC_FREE_SECURE_CONTEXT        1
-#define portSVC_START_SCHEDULER            2
-#define portSVC_RAISE_PRIVILEGE            3
-#define portSVC_SYSTEM_CALL_ENTER          4   /* System calls with upto 4 parameters. */
-#define portSVC_SYSTEM_CALL_ENTER_1        5   /* System calls with 5 parameters. */
-#define portSVC_SYSTEM_CALL_EXIT           6
-#define portSVC_YIELD                      7
+#define portSVC_ALLOCATE_SECURE_CONTEXT    100
+#define portSVC_FREE_SECURE_CONTEXT        101
+#define portSVC_START_SCHEDULER            102
+#define portSVC_RAISE_PRIVILEGE            103
+#define portSVC_SYSTEM_CALL_EXIT           104
+#define portSVC_YIELD                      105
 /*-----------------------------------------------------------*/
 
 /**
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.c
index d1fbdc0e5..4cb310afd 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.c
@@ -38,6 +38,8 @@
 #include "timers.h"
 #include "event_groups.h"
 #include "stream_buffer.h"
+#include "mpu_prototypes.h"
+#include "mpu_syscall_numbers.h"
 
 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
 /*-----------------------------------------------------------*/
@@ -67,11 +69,8 @@
                 " MPU_xTaskDelayUntil_Unpriv:                           \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskDelayUntilImpl                        \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory"
             );
         }
 
@@ -99,11 +98,8 @@
                 " MPU_xTaskAbortDelay_Unpriv:                           \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskAbortDelayImpl                        \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory"
             );
         }
 
@@ -131,11 +127,8 @@
                 " MPU_vTaskDelay_Unpriv:                                \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskDelayImpl                             \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory"
             );
         }
 
@@ -163,11 +156,8 @@
                 " MPU_uxTaskPriorityGet_Unpriv:                         \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskPriorityGetImpl                      \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory"
             );
         }
 
@@ -195,11 +185,8 @@
                 " MPU_eTaskGetState_Unpriv:                             \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_eTaskGetStateImpl                          \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory"
             );
         }
 
@@ -233,11 +220,8 @@
                 " MPU_vTaskGetInfo_Unpriv:                              \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskGetInfoImpl                           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory"
             );
         }
 
@@ -265,11 +249,8 @@
                 " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetIdleTaskHandleImpl                 \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory"
             );
         }
 
@@ -297,11 +278,8 @@
                 " MPU_vTaskSuspend_Unpriv:                              \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskSuspendImpl                           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory"
             );
         }
 
@@ -329,11 +307,8 @@
                 " MPU_vTaskResume_Unpriv:                               \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskResumeImpl                            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskResume ) : "memory"
             );
         }
 
@@ -359,11 +334,8 @@
             " MPU_xTaskGetTickCount_Unpriv:                         \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xTaskGetTickCountImpl                      \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -387,11 +359,8 @@
             " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_uxTaskGetNumberOfTasksImpl                 \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -417,11 +386,8 @@
                 " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetRunTimeCounterImpl                \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory"
             );
         }
 
@@ -449,11 +415,8 @@
                 " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetRunTimePercentImpl                \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory"
             );
         }
 
@@ -481,11 +444,8 @@
                 " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetIdleRunTimePercentImpl            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory"
             );
         }
 
@@ -513,11 +473,8 @@
                 " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGetIdleRunTimeCounterImpl            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory"
             );
         }
 
@@ -547,11 +504,8 @@
                 " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskSetApplicationTaskTagImpl             \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory"
             );
         }
 
@@ -579,11 +533,8 @@
                 " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetApplicationTaskTagImpl             \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory"
             );
         }
 
@@ -615,11 +566,8 @@
                 " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTaskSetThreadLocalStoragePointerImpl      \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory"
             );
         }
 
@@ -649,11 +597,8 @@
                 " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pvTaskGetThreadLocalStoragePointerImpl     \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory"
             );
         }
 
@@ -685,11 +630,8 @@
                 " MPU_uxTaskGetSystemState_Unpriv:                      \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskGetSystemStateImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory"
             );
         }
 
@@ -717,11 +659,8 @@
                 " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskGetStackHighWaterMarkImpl            \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory"
             );
         }
 
@@ -749,11 +688,8 @@
                 " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTaskGetStackHighWaterMark2Impl           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory"
             );
         }
 
@@ -781,11 +717,8 @@
                 " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetCurrentTaskHandleImpl              \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory"
             );
         }
 
@@ -813,11 +746,8 @@
                 " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGetSchedulerStateImpl                 \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory"
             );
         }
 
@@ -843,11 +773,8 @@
             " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_vTaskSetTimeOutStateImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -873,28 +800,17 @@
             " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xTaskCheckForTimeOutImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
 
     #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                           UBaseType_t uxIndexToNotify,
-                                           uint32_t ulValue,
-                                           eNotifyAction eAction,
-                                           uint32_t * pulPreviousNotificationValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                           UBaseType_t uxIndexToNotify,
-                                           uint32_t ulValue,
-                                           eNotifyAction eAction,
-                                           uint32_t * pulPreviousNotificationValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
@@ -911,11 +827,8 @@
                 " MPU_xTaskGenericNotify_Unpriv:                        \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGenericNotifyImpl                     \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory"
             );
         }
 
@@ -924,17 +837,9 @@
 
     #if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                               uint32_t ulBitsToClearOnEntry,
-                                               uint32_t ulBitsToClearOnExit,
-                                               uint32_t * pulNotificationValue,
-                                               TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                               uint32_t ulBitsToClearOnEntry,
-                                               uint32_t ulBitsToClearOnExit,
-                                               uint32_t * pulNotificationValue,
-                                               TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
@@ -951,11 +856,8 @@
                 " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGenericNotifyWaitImpl                 \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory"
             );
         }
 
@@ -987,11 +889,8 @@
                 " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGenericNotifyTakeImpl                \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory"
             );
         }
 
@@ -1021,11 +920,8 @@
                 " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTaskGenericNotifyStateClearImpl           \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory"
             );
         }
 
@@ -1057,11 +953,8 @@
                 " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_ulTaskGenericNotifyValueClearImpl          \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory"
             );
         }
 
@@ -1093,11 +986,8 @@
             " MPU_xQueueGenericSend_Unpriv:                         \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueueGenericSendImpl                      \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1121,11 +1011,8 @@
             " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_uxQueueMessagesWaitingImpl                 \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1149,11 +1036,8 @@
             " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_uxQueueSpacesAvailableImpl                 \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1181,11 +1065,8 @@
             " MPU_xQueueReceive_Unpriv:                             \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueueReceiveImpl                          \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1213,11 +1094,8 @@
             " MPU_xQueuePeek_Unpriv:                                \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueuePeekImpl                             \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1243,11 +1121,8 @@
             " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xQueueSemaphoreTakeImpl                    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1273,11 +1148,8 @@
                 " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueGetMutexHolderImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory"
             );
         }
 
@@ -1307,11 +1179,8 @@
                 " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueTakeMutexRecursiveImpl               \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory"
             );
         }
 
@@ -1339,11 +1208,8 @@
                 " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueGiveMutexRecursiveImpl               \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory"
             );
         }
 
@@ -1373,11 +1239,8 @@
                 " MPU_xQueueSelectFromSet_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueSelectFromSetImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory"
             );
         }
 
@@ -1407,11 +1270,8 @@
                 " MPU_xQueueAddToSet_Unpriv:                            \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xQueueAddToSetImpl                         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory"
             );
         }
 
@@ -1441,11 +1301,8 @@
                 " MPU_vQueueAddToRegistry_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vQueueAddToRegistryImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory"
             );
         }
 
@@ -1473,11 +1330,8 @@
                 " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vQueueUnregisterQueueImpl                  \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory"
             );
         }
 
@@ -1505,11 +1359,8 @@
                 " MPU_pcQueueGetName_Unpriv:                            \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pcQueueGetNameImpl                         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory"
             );
         }
 
@@ -1537,11 +1388,8 @@
                 " MPU_pvTimerGetTimerID_Unpriv:                         \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pvTimerGetTimerIDImpl                      \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory"
             );
         }
 
@@ -1571,11 +1419,8 @@
                 " MPU_vTimerSetTimerID_Unpriv:                          \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTimerSetTimerIDImpl                       \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory"
             );
         }
 
@@ -1603,11 +1448,8 @@
                 " MPU_xTimerIsTimerActive_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerIsTimerActiveImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory"
             );
         }
 
@@ -1635,11 +1477,8 @@
                 " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetTimerDaemonTaskHandleImpl         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory"
             );
         }
 
@@ -1648,17 +1487,9 @@
 
     #if ( configUSE_TIMERS == 1 )
 
-        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                                     const BaseType_t xCommandID,
-                                                     const TickType_t xOptionalValue,
-                                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                                     const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+        BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                                     const BaseType_t xCommandID,
-                                                     const TickType_t xOptionalValue,
-                                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                                     const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
@@ -1675,11 +1506,8 @@
                 " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
                 "     pop {r0}                                                  \n"
                 "     svc %0                                                    \n"
-                "     bl MPU_xTimerGenericCommandFromTaskImpl                   \n"
-                "     svc %1                                                    \n"
-                "     bx lr                                                     \n"
                 "                                                               \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory"
             );
         }
 
@@ -1707,11 +1535,8 @@
                 " MPU_pcTimerGetName_Unpriv:                            \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_pcTimerGetNameImpl                         \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory"
             );
         }
 
@@ -1741,11 +1566,8 @@
                 " MPU_vTimerSetReloadMode_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vTimerSetReloadModeImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory"
             );
         }
 
@@ -1773,11 +1595,8 @@
                 " MPU_xTimerGetReloadMode_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetReloadModeImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory"
             );
         }
 
@@ -1805,11 +1624,8 @@
                 " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxTimerGetReloadModeImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory"
             );
         }
 
@@ -1837,11 +1653,8 @@
                 " MPU_xTimerGetPeriod_Unpriv:                           \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetPeriodImpl                        \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory"
             );
         }
 
@@ -1869,28 +1682,17 @@
                 " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_xTimerGetExpiryTimeImpl                    \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory"
             );
         }
 
     #endif /* if ( configUSE_TIMERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
-                                         const EventBits_t uxBitsToWaitFor,
-                                         const BaseType_t xClearOnExit,
-                                         const BaseType_t xWaitForAllBits,
-                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
-    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
-                                         const EventBits_t uxBitsToWaitFor,
-                                         const BaseType_t xClearOnExit,
-                                         const BaseType_t xWaitForAllBits,
-                                         TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
     {
         __asm volatile
         (
@@ -1907,11 +1709,8 @@
             " MPU_xEventGroupWaitBits_Unpriv:                       \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupWaitBitsImpl                    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1937,11 +1736,8 @@
             " MPU_xEventGroupClearBits_Unpriv:                      \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupClearBitsImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -1967,11 +1763,8 @@
             " MPU_xEventGroupSetBits_Unpriv:                        \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupSetBitsImpl                     \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2001,11 +1794,8 @@
             " MPU_xEventGroupSync_Unpriv:                           \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xEventGroupSyncImpl                        \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2031,11 +1821,8 @@
                 " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_uxEventGroupGetNumberImpl                  \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory"
             );
         }
 
@@ -2065,11 +1852,8 @@
                 " MPU_vEventGroupSetNumber_Unpriv:                      \n"
                 "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
-                "     bl MPU_vEventGroupSetNumberImpl                   \n"
-                "     svc %1                                            \n"
-                "     bx lr                                             \n"
                 "                                                       \n"
-                : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+                : : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory"
             );
         }
 
@@ -2101,11 +1885,8 @@
             " MPU_xStreamBufferSend_Unpriv:                         \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferSendImpl                      \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2135,11 +1916,8 @@
             " MPU_xStreamBufferReceive_Unpriv:                      \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferReceiveImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2163,11 +1941,8 @@
             " MPU_xStreamBufferIsFull_Unpriv:                       \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferIsFullImpl                    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2191,11 +1966,8 @@
             " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferIsEmptyImpl                   \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2219,11 +1991,8 @@
             " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferSpacesAvailableImpl           \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2247,11 +2016,8 @@
             " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferBytesAvailableImpl            \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2277,11 +2043,8 @@
             " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferSetTriggerLevelImpl           \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
@@ -2305,11 +2068,8 @@
             " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
             "     pop {r0}                                          \n"
             "     svc %0                                            \n"
-            "     bl MPU_xStreamBufferNextMessageLengthBytesImpl    \n"
-            "     svc %1                                            \n"
-            "     bx lr                                             \n"
             "                                                       \n"
-            : : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory"
+            : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
         );
     }
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/port.c b/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
index 52d68d3ea..6a3877894 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
@@ -35,8 +35,9 @@
 #include "FreeRTOS.h"
 #include "task.h"
 
-/* MPU wrappers includes. */
+/* MPU includes. */
 #include "mpu_wrappers.h"
+#include "mpu_syscall_numbers.h"
 
 /* Portasm includes. */
 #include "portasm.h"
@@ -436,29 +437,22 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
  * @brief Sets up the system call stack so that upon returning from
  * SVC, the system call stack is used.
  *
- * It is used for the system calls with up to 4 parameters.
- *
  * @param pulTaskStack The current SP when the SVC was raised.
  * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ * @param ucSystemCallNumber The system call number of the system call.
  */
     void vSystemCallEnter( uint32_t * pulTaskStack,
-                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
+                           uint32_t ulLR,
+                           uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
- * @brief Sets up the system call stack so that upon returning from
- * SVC, the system call stack is used.
- *
- * It is used for the system calls with 5 parameters.
- *
- * @param pulTaskStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ * @brief Raise SVC for exiting from a system call.
  */
-    void vSystemCallEnter_1( uint32_t * pulTaskStack,
-                             uint32_t ulLR ) PRIVILEGED_FUNCTION;
+    void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
@@ -488,6 +482,15 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+/**
+ * @brief This variable is set to pdTRUE when the scheduler is started.
+ */
+    PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
+
+#endif
+
 /**
  * @brief Each task maintains its own interrupt status in the critical nesting
  * variable.
@@ -1134,15 +1137,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     void vSystemCallEnter( uint32_t * pulTaskStack,
-                           uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
+                           uint32_t ulLR,
+                           uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */
     {
         extern TaskHandle_t pxCurrentTCB;
+        extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ];
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulSystemCallStack;
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
-
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __syscalls_flash_start__;
@@ -1154,17 +1158,27 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         #endif /* #if defined( __ARMCC_VERSION ) */
 
         ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
 
-        /* If the request did not come from the system call section, do nothing. */
+        /* Checks:
+         * 1. SVC is raised from the system call section (i.e. application is
+         *    not raising SVC directly).
+         * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as
+         *    it is non-NULL only during the execution of a system call (i.e.
+         *    between system call enter and exit).
+         * 3. System call is not for a kernel API disabled by the configuration
+         *    in FreeRTOSConfig.h.
+         * 4. We do not need to check that ucSystemCallNumber is within range
+         *    because the assembly SVC handler checks that before calling
+         *    this function.
+         */
         if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) &&
+            ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) &&
+            ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) )
         {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
             pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
 
-            /* This is not NULL only for the duration of the system call. */
-            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
-
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
@@ -1198,9 +1212,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 pulSystemCallStack[ i ] = pulTaskStack[ i ];
             }
 
-            /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
-             * restore it when we exit from the system call. */
+            /* Store the value of the Link Register before the SVC was raised.
+             * It contains the address of the caller of the System Call entry
+             * point (i.e. the caller of the MPU_<API>). We need to restore it
+             * when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            /* Store the value of the PSPLIM register before the SVC was raised.
+             * We need to restore it when we exit from the system call. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
             {
                 __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
@@ -1215,6 +1233,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             }
             #endif
 
+            /* Start executing the system call upon returning from this handler. */
+            pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
+            /* Raise a request to exit from the system call upon finishing the
+             * system call. */
+            pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit;
+
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
             pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
@@ -1251,127 +1275,9 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    void vSystemCallEnter_1( uint32_t * pulTaskStack,
-                             uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
+    void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */
     {
-        extern TaskHandle_t pxCurrentTCB;
-        xMPU_SETTINGS * pxMpuSettings;
-        uint32_t * pulSystemCallStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-
-        #if defined( __ARMCC_VERSION )
-
-            /* Declaration when these variable are defined in code instead of being
-             * exported from linker scripts. */
-            extern uint32_t * __syscalls_flash_start__;
-            extern uint32_t * __syscalls_flash_end__;
-        #else
-            /* Declaration when these variable are exported from linker scripts. */
-            extern uint32_t __syscalls_flash_start__[];
-            extern uint32_t __syscalls_flash_end__[];
-        #endif /* #if defined( __ARMCC_VERSION ) */
-
-        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-        /* If the request did not come from the system call section, do nothing. */
-        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
-        {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
-
-            /* This is not NULL only for the duration of the system call. */
-            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
-
-            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-            {
-                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
-                {
-                    /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
-                    __asm volatile (
-                        " vpush {s0}         \n" /* Trigger lazy stacking. */
-                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                        ::: "memory"
-                        );
-                }
-                else
-                {
-                    /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
-                }
-            }
-            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
-            {
-                ulStackFrameSize = 8;
-            }
-            #endif /* configENABLE_FPU || configENABLE_MVE */
-
-            /* Make space on the system call stack for the stack frame and
-             * the parameter passed on the stack. We only need to copy one
-             * parameter but we still reserve 2 spaces to keep the stack
-             * double word aligned. */
-            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
-
-            /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
-            {
-                pulSystemCallStack[ i ] = pulTaskStack[ i ];
-            }
-
-            /* Copy the parameter which is passed the stack. */
-            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-            {
-                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
-
-                /* Record if the hardware used padding to force the stack pointer
-                 * to be double word aligned. */
-                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-            }
-            else
-            {
-                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
-
-                /* Record if the hardware used padding to force the stack pointer
-                 * to be double word aligned. */
-                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-            }
-
-            /* Store the value of the LR and PSPLIM registers before the SVC was raised.
-             * We need to restore it when we exit from the system call. */
-            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            #if ( portUSE_PSPLIM_REGISTER == 1 )
-            {
-                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-            }
-            #endif
-
-            /* Use the pulSystemCallStack in thread mode. */
-            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            #if ( portUSE_PSPLIM_REGISTER == 1 )
-            {
-                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-            }
-            #endif
-
-            /* Remember the location where we should copy the stack frame when we exit from
-             * the system call. */
-            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-            /* We ensure in pxPortInitialiseStack that the system call stack is
-             * double word aligned and therefore, there is no need of padding.
-             * Clear the bit[9] of stacked xPSR. */
-            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-            /* Raise the privilege for the duration of the system call. */
-            __asm volatile (
-                " mrs r0, control     \n" /* Obtain current control value. */
-                " movs r1, #1         \n" /* r1 = 1. */
-                " bics r0, r1         \n" /* Clear nPRIV bit. */
-                " msr control, r0     \n" /* Write back new control value. */
-                ::: "r0", "r1", "memory"
-                );
-        }
+        __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" );
     }
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@@ -1388,24 +1294,32 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
-
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
-            extern uint32_t * __syscalls_flash_start__;
-            extern uint32_t * __syscalls_flash_end__;
+            extern uint32_t * __privileged_functions_start__;
+            extern uint32_t * __privileged_functions_end__;
         #else
             /* Declaration when these variable are exported from linker scripts. */
-            extern uint32_t __syscalls_flash_start__[];
-            extern uint32_t __syscalls_flash_end__[];
+            extern uint32_t __privileged_functions_start__[];
+            extern uint32_t __privileged_functions_end__[];
         #endif /* #if defined( __ARMCC_VERSION ) */
 
         ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
+        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
 
-        /* If the request did not come from the system call section, do nothing. */
-        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+        /* Checks:
+         * 1. SVC is raised from the privileged code (i.e. application is not
+         *    raising SVC directly). This SVC is only raised from
+         *    vRequestSystemCallExit which is in the privileged code section.
+         * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL -
+         *    this means that we previously entered a system call and the
+         *    application is not attempting to exit without entering a system
+         *    call.
+         */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) &&
+            ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) )
         {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
             pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
 
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
@@ -1444,9 +1358,14 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Use the pulTaskStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
 
-            /* Restore the LR and PSPLIM to what they were at the time of
-             * system call entry. */
+            /* Return to the caller of the System Call entry point (i.e. the
+             * caller of the MPU_<API>). */
+            pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+            /* Ensure that LR has a valid value.*/
             pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+
+            /* Restore the PSPLIM register to what it was at the time of
+             * system call entry. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
             {
                 __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
@@ -1780,6 +1699,12 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     /* Initialize the critical nesting count ready for the first task. */
     ulCriticalNesting = 0;
 
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+    {
+        xSchedulerRunning = pdTRUE;
+    }
+    #endif
+
     /* Start the first task. */
     vStartFirstTask();
 
@@ -2062,7 +1987,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
 
     void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
                                          int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
@@ -2078,10 +2003,10 @@ BaseType_t xPortIsInsideInterrupt( void )
         xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit );
     }
 
-#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
 
     void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
                                           int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
@@ -2097,10 +2022,10 @@ BaseType_t xPortIsInsideInterrupt( void )
         xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit );
     }
 
-#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
 
@@ -2108,21 +2033,34 @@ BaseType_t xPortIsInsideInterrupt( void )
         {
             uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
             BaseType_t xAccessGranted = pdFALSE;
-            const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+            const xMPU_SETTINGS * xTaskMpuSettings;
 
-            ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
-            ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
-
-            if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+            if( xSchedulerRunning == pdFALSE )
             {
+                /* Grant access to all the kernel objects before the scheduler
+                 * is started. It is necessary because there is no task running
+                 * yet and therefore, we cannot use the permissions of any
+                 * task. */
                 xAccessGranted = pdTRUE;
             }
             else
             {
-                if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+                ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+                ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+                if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
                 {
                     xAccessGranted = pdTRUE;
                 }
+                else
+                {
+                    if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                    {
+                        xAccessGranted = pdTRUE;
+                    }
+                }
             }
 
             return xAccessGranted;
@@ -2141,5 +2079,5 @@ BaseType_t xPortIsInsideInterrupt( void )
 
     #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
 
-#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.c b/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.c
index e533dd7e9..76ba642a0 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.c
@@ -36,6 +36,9 @@
 /* Portasm includes. */
 #include "portasm.h"
 
+/* System call numbers includes. */
+#include "mpu_syscall_numbers.h"
+
 /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
  * header files. */
 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
@@ -443,7 +446,6 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             ".syntax unified                \n"
             ".extern vPortSVCHandler_C      \n"
             ".extern vSystemCallEnter       \n"
-            ".extern vSystemCallEnter_1     \n"
             ".extern vSystemCallExit        \n"
             "                               \n"
             "tst lr, #4                     \n"
@@ -454,10 +456,8 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "ldr r1, [r0, #24]              \n"
             "ldrb r2, [r1, #-2]             \n"
             "cmp r2, %0                     \n"
-            "beq syscall_enter              \n"
+            "blt syscall_enter              \n"
             "cmp r2, %1                     \n"
-            "beq syscall_enter_1            \n"
-            "cmp r2, %2                     \n"
             "beq syscall_exit               \n"
             "b vPortSVCHandler_C            \n"
             "                               \n"
@@ -465,16 +465,12 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    mov r1, lr                 \n"
             "    b vSystemCallEnter         \n"
             "                               \n"
-            "syscall_enter_1:               \n"
-            "    mov r1, lr                 \n"
-            "    b vSystemCallEnter_1       \n"
-            "                               \n"
             "syscall_exit:                  \n"
             "    mov r1, lr                 \n"
             "    b vSystemCallExit          \n"
             "                               \n"
             : /* No outputs. */
-            : "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT )
+            : "i" ( NUM_SYSTEM_CALLS ), "i" ( portSVC_SYSTEM_CALL_EXIT )
             : "r0", "r1", "r2", "memory"
         );
     }
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h
index 60ef37380..672b0dbdc 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h
@@ -322,14 +322,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 /**
  * @brief SVC numbers.
  */
-#define portSVC_ALLOCATE_SECURE_CONTEXT    0
-#define portSVC_FREE_SECURE_CONTEXT        1
-#define portSVC_START_SCHEDULER            2
-#define portSVC_RAISE_PRIVILEGE            3
-#define portSVC_SYSTEM_CALL_ENTER          4   /* System calls with upto 4 parameters. */
-#define portSVC_SYSTEM_CALL_ENTER_1        5   /* System calls with 5 parameters. */
-#define portSVC_SYSTEM_CALL_EXIT           6
-#define portSVC_YIELD                      7
+#define portSVC_ALLOCATE_SECURE_CONTEXT    100
+#define portSVC_FREE_SECURE_CONTEXT        101
+#define portSVC_START_SCHEDULER            102
+#define portSVC_RAISE_PRIVILEGE            103
+#define portSVC_SYSTEM_CALL_EXIT           104
+#define portSVC_YIELD                      105
 /*-----------------------------------------------------------*/
 
 /**
diff --git a/portable/IAR/ARM_CM23/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM23/non_secure/mpu_wrappers_v2_asm.S
index 5300a99ec..419df5b1e 100644
--- a/portable/IAR/ARM_CM23/non_secure/mpu_wrappers_v2_asm.S
+++ b/portable/IAR/ARM_CM23/non_secure/mpu_wrappers_v2_asm.S
@@ -32,15 +32,12 @@
 /*-----------------------------------------------------------*/
 
 #include "FreeRTOSConfig.h"
+#include "mpu_syscall_numbers.h"
 
 #ifndef configUSE_MPU_WRAPPERS_V1
     #define configUSE_MPU_WRAPPERS_V1 0
 #endif
 
-/* These must be in sync with portmacro.h. */
-#define portSVC_SYSTEM_CALL_ENTER   4 /* System calls with upto 4 parameters. */
-#define portSVC_SYSTEM_CALL_ENTER_1 5 /* System calls with 5 parameters. */
-#define portSVC_SYSTEM_CALL_EXIT    6
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
@@ -57,10 +54,7 @@ MPU_xTaskDelayUntil:
         b MPU_xTaskDelayUntilImpl
     MPU_xTaskDelayUntil_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskDelayUntilImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskDelayUntil
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskAbortDelay
@@ -75,10 +69,7 @@ MPU_xTaskAbortDelay:
         b MPU_xTaskAbortDelayImpl
     MPU_xTaskAbortDelay_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskAbortDelayImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskAbortDelay
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskDelay
@@ -93,10 +84,7 @@ MPU_vTaskDelay:
         b MPU_vTaskDelayImpl
     MPU_vTaskDelay_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskDelayImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskDelay
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskPriorityGet
@@ -111,10 +99,7 @@ MPU_uxTaskPriorityGet:
         b MPU_uxTaskPriorityGetImpl
     MPU_uxTaskPriorityGet_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskPriorityGetImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskPriorityGet
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_eTaskGetState
@@ -129,10 +114,7 @@ MPU_eTaskGetState:
         b MPU_eTaskGetStateImpl
     MPU_eTaskGetState_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_eTaskGetStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_eTaskGetState
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskGetInfo
@@ -147,10 +129,7 @@ MPU_vTaskGetInfo:
         b MPU_vTaskGetInfoImpl
     MPU_vTaskGetInfo_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskGetInfoImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskGetInfo
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetIdleTaskHandle
@@ -165,10 +144,7 @@ MPU_xTaskGetIdleTaskHandle:
         b MPU_xTaskGetIdleTaskHandleImpl
     MPU_xTaskGetIdleTaskHandle_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetIdleTaskHandleImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetIdleTaskHandle
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskSuspend
@@ -183,10 +159,7 @@ MPU_vTaskSuspend:
         b MPU_vTaskSuspendImpl
     MPU_vTaskSuspend_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSuspendImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskSuspend
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskResume
@@ -201,10 +174,7 @@ MPU_vTaskResume:
         b MPU_vTaskResumeImpl
     MPU_vTaskResume_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskResumeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskResume
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetTickCount
@@ -219,10 +189,7 @@ MPU_xTaskGetTickCount:
         b MPU_xTaskGetTickCountImpl
     MPU_xTaskGetTickCount_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetTickCountImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetTickCount
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskGetNumberOfTasks
@@ -237,10 +204,7 @@ MPU_uxTaskGetNumberOfTasks:
         b MPU_uxTaskGetNumberOfTasksImpl
     MPU_uxTaskGetNumberOfTasks_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetNumberOfTasksImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskGetNumberOfTasks
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGetRunTimeCounter
@@ -255,10 +219,7 @@ MPU_ulTaskGetRunTimeCounter:
         b MPU_ulTaskGetRunTimeCounterImpl
     MPU_ulTaskGetRunTimeCounter_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetRunTimeCounterImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGetRunTimeCounter
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGetRunTimePercent
@@ -273,10 +234,7 @@ MPU_ulTaskGetRunTimePercent:
         b MPU_ulTaskGetRunTimePercentImpl
     MPU_ulTaskGetRunTimePercent_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetRunTimePercentImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGetRunTimePercent
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGetIdleRunTimePercent
@@ -291,10 +249,7 @@ MPU_ulTaskGetIdleRunTimePercent:
         b MPU_ulTaskGetIdleRunTimePercentImpl
     MPU_ulTaskGetIdleRunTimePercent_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetIdleRunTimePercentImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGetIdleRunTimeCounter
@@ -309,10 +264,7 @@ MPU_ulTaskGetIdleRunTimeCounter:
         b MPU_ulTaskGetIdleRunTimeCounterImpl
     MPU_ulTaskGetIdleRunTimeCounter_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetIdleRunTimeCounterImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskSetApplicationTaskTag
@@ -327,10 +279,7 @@ MPU_vTaskSetApplicationTaskTag:
         b MPU_vTaskSetApplicationTaskTagImpl
     MPU_vTaskSetApplicationTaskTag_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSetApplicationTaskTagImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskSetApplicationTaskTag
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetApplicationTaskTag
@@ -345,10 +294,7 @@ MPU_xTaskGetApplicationTaskTag:
         b MPU_xTaskGetApplicationTaskTagImpl
     MPU_xTaskGetApplicationTaskTag_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetApplicationTaskTagImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetApplicationTaskTag
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskSetThreadLocalStoragePointer
@@ -363,10 +309,7 @@ MPU_vTaskSetThreadLocalStoragePointer:
         b MPU_vTaskSetThreadLocalStoragePointerImpl
     MPU_vTaskSetThreadLocalStoragePointer_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSetThreadLocalStoragePointerImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pvTaskGetThreadLocalStoragePointer
@@ -381,10 +324,7 @@ MPU_pvTaskGetThreadLocalStoragePointer:
         b MPU_pvTaskGetThreadLocalStoragePointerImpl
     MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pvTaskGetThreadLocalStoragePointerImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskGetSystemState
@@ -399,10 +339,7 @@ MPU_uxTaskGetSystemState:
         b MPU_uxTaskGetSystemStateImpl
     MPU_uxTaskGetSystemState_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetSystemStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskGetSystemState
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskGetStackHighWaterMark
@@ -417,10 +354,7 @@ MPU_uxTaskGetStackHighWaterMark:
         b MPU_uxTaskGetStackHighWaterMarkImpl
     MPU_uxTaskGetStackHighWaterMark_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetStackHighWaterMarkImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskGetStackHighWaterMark2
@@ -435,10 +369,7 @@ MPU_uxTaskGetStackHighWaterMark2:
         b MPU_uxTaskGetStackHighWaterMark2Impl
     MPU_uxTaskGetStackHighWaterMark2_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetStackHighWaterMark2Impl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetCurrentTaskHandle
@@ -453,10 +384,7 @@ MPU_xTaskGetCurrentTaskHandle:
         b MPU_xTaskGetCurrentTaskHandleImpl
     MPU_xTaskGetCurrentTaskHandle_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetCurrentTaskHandleImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetSchedulerState
@@ -471,10 +399,7 @@ MPU_xTaskGetSchedulerState:
         b MPU_xTaskGetSchedulerStateImpl
     MPU_xTaskGetSchedulerState_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetSchedulerStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetSchedulerState
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskSetTimeOutState
@@ -489,10 +414,7 @@ MPU_vTaskSetTimeOutState:
         b MPU_vTaskSetTimeOutStateImpl
     MPU_vTaskSetTimeOutState_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSetTimeOutStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskSetTimeOutState
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskCheckForTimeOut
@@ -507,14 +429,11 @@ MPU_xTaskCheckForTimeOut:
         b MPU_xTaskCheckForTimeOutImpl
     MPU_xTaskCheckForTimeOut_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskCheckForTimeOutImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskCheckForTimeOut
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xTaskGenericNotify
-MPU_xTaskGenericNotify:
+    PUBLIC MPU_xTaskGenericNotifyEntry
+MPU_xTaskGenericNotifyEntry:
     push {r0, r1}
     mrs r0, control
     movs r1, #1
@@ -525,14 +444,11 @@ MPU_xTaskGenericNotify:
         b MPU_xTaskGenericNotifyImpl
     MPU_xTaskGenericNotify_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTaskGenericNotifyImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGenericNotify
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xTaskGenericNotifyWait
-MPU_xTaskGenericNotifyWait:
+    PUBLIC MPU_xTaskGenericNotifyWaitEntry
+MPU_xTaskGenericNotifyWaitEntry:
     push {r0, r1}
     mrs r0, control
     movs r1, #1
@@ -543,10 +459,7 @@ MPU_xTaskGenericNotifyWait:
         b MPU_xTaskGenericNotifyWaitImpl
     MPU_xTaskGenericNotifyWait_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTaskGenericNotifyWaitImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGenericNotifyWait
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGenericNotifyTake
@@ -561,10 +474,7 @@ MPU_ulTaskGenericNotifyTake:
         b MPU_ulTaskGenericNotifyTakeImpl
     MPU_ulTaskGenericNotifyTake_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGenericNotifyTakeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGenericNotifyTake
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGenericNotifyStateClear
@@ -579,10 +489,7 @@ MPU_xTaskGenericNotifyStateClear:
         b MPU_xTaskGenericNotifyStateClearImpl
     MPU_xTaskGenericNotifyStateClear_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGenericNotifyStateClearImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGenericNotifyStateClear
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGenericNotifyValueClear
@@ -597,10 +504,7 @@ MPU_ulTaskGenericNotifyValueClear:
         b MPU_ulTaskGenericNotifyValueClearImpl
     MPU_ulTaskGenericNotifyValueClear_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGenericNotifyValueClearImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueGenericSend
@@ -615,10 +519,7 @@ MPU_xQueueGenericSend:
         b MPU_xQueueGenericSendImpl
     MPU_xQueueGenericSend_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueGenericSendImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueGenericSend
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxQueueMessagesWaiting
@@ -633,10 +534,7 @@ MPU_uxQueueMessagesWaiting:
         b MPU_uxQueueMessagesWaitingImpl
     MPU_uxQueueMessagesWaiting_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxQueueMessagesWaitingImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxQueueMessagesWaiting
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxQueueSpacesAvailable
@@ -651,10 +549,7 @@ MPU_uxQueueSpacesAvailable:
         b MPU_uxQueueSpacesAvailableImpl
     MPU_uxQueueSpacesAvailable_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxQueueSpacesAvailableImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxQueueSpacesAvailable
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueReceive
@@ -669,10 +564,7 @@ MPU_xQueueReceive:
         b MPU_xQueueReceiveImpl
     MPU_xQueueReceive_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueReceiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueReceive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueuePeek
@@ -687,10 +579,7 @@ MPU_xQueuePeek:
         b MPU_xQueuePeekImpl
     MPU_xQueuePeek_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueuePeekImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueuePeek
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueSemaphoreTake
@@ -705,10 +594,7 @@ MPU_xQueueSemaphoreTake:
         b MPU_xQueueSemaphoreTakeImpl
     MPU_xQueueSemaphoreTake_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueSemaphoreTakeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueSemaphoreTake
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueGetMutexHolder
@@ -723,10 +609,7 @@ MPU_xQueueGetMutexHolder:
         b MPU_xQueueGetMutexHolderImpl
     MPU_xQueueGetMutexHolder_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueGetMutexHolderImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueGetMutexHolder
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueTakeMutexRecursive
@@ -741,10 +624,7 @@ MPU_xQueueTakeMutexRecursive:
         b MPU_xQueueTakeMutexRecursiveImpl
     MPU_xQueueTakeMutexRecursive_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueTakeMutexRecursiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueTakeMutexRecursive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueGiveMutexRecursive
@@ -759,10 +639,7 @@ MPU_xQueueGiveMutexRecursive:
         b MPU_xQueueGiveMutexRecursiveImpl
     MPU_xQueueGiveMutexRecursive_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueGiveMutexRecursiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueGiveMutexRecursive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueSelectFromSet
@@ -777,10 +654,7 @@ MPU_xQueueSelectFromSet:
         b MPU_xQueueSelectFromSetImpl
     MPU_xQueueSelectFromSet_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueSelectFromSetImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueSelectFromSet
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueAddToSet
@@ -795,10 +669,7 @@ MPU_xQueueAddToSet:
         b MPU_xQueueAddToSetImpl
     MPU_xQueueAddToSet_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueAddToSetImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueAddToSet
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vQueueAddToRegistry
@@ -813,10 +684,7 @@ MPU_vQueueAddToRegistry:
         b MPU_vQueueAddToRegistryImpl
     MPU_vQueueAddToRegistry_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vQueueAddToRegistryImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vQueueAddToRegistry
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vQueueUnregisterQueue
@@ -831,10 +699,7 @@ MPU_vQueueUnregisterQueue:
         b MPU_vQueueUnregisterQueueImpl
     MPU_vQueueUnregisterQueue_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vQueueUnregisterQueueImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vQueueUnregisterQueue
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pcQueueGetName
@@ -849,10 +714,7 @@ MPU_pcQueueGetName:
         b MPU_pcQueueGetNameImpl
     MPU_pcQueueGetName_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pcQueueGetNameImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_pcQueueGetName
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pvTimerGetTimerID
@@ -867,10 +729,7 @@ MPU_pvTimerGetTimerID:
         b MPU_pvTimerGetTimerIDImpl
     MPU_pvTimerGetTimerID_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pvTimerGetTimerIDImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_pvTimerGetTimerID
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTimerSetTimerID
@@ -885,10 +744,7 @@ MPU_vTimerSetTimerID:
         b MPU_vTimerSetTimerIDImpl
     MPU_vTimerSetTimerID_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTimerSetTimerIDImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTimerSetTimerID
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerIsTimerActive
@@ -903,10 +759,7 @@ MPU_xTimerIsTimerActive:
         b MPU_xTimerIsTimerActiveImpl
     MPU_xTimerIsTimerActive_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerIsTimerActiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerIsTimerActive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerGetTimerDaemonTaskHandle
@@ -921,14 +774,11 @@ MPU_xTimerGetTimerDaemonTaskHandle:
         b MPU_xTimerGetTimerDaemonTaskHandleImpl
     MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetTimerDaemonTaskHandleImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xTimerGenericCommandFromTask
-MPU_xTimerGenericCommandFromTask:
+    PUBLIC MPU_xTimerGenericCommandFromTaskEntry
+MPU_xTimerGenericCommandFromTaskEntry:
     push {r0, r1}
     mrs r0, control
     movs r1, #1
@@ -939,10 +789,7 @@ MPU_xTimerGenericCommandFromTask:
         b MPU_xTimerGenericCommandFromTaskImpl
     MPU_xTimerGenericCommandFromTask_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTimerGenericCommandFromTaskImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGenericCommandFromTask
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pcTimerGetName
@@ -957,10 +804,7 @@ MPU_pcTimerGetName:
         b MPU_pcTimerGetNameImpl
     MPU_pcTimerGetName_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pcTimerGetNameImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_pcTimerGetName
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTimerSetReloadMode
@@ -975,10 +819,7 @@ MPU_vTimerSetReloadMode:
         b MPU_vTimerSetReloadModeImpl
     MPU_vTimerSetReloadMode_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTimerSetReloadModeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTimerSetReloadMode
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerGetReloadMode
@@ -993,10 +834,7 @@ MPU_xTimerGetReloadMode:
         b MPU_xTimerGetReloadModeImpl
     MPU_xTimerGetReloadMode_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetReloadModeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGetReloadMode
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTimerGetReloadMode
@@ -1011,10 +849,7 @@ MPU_uxTimerGetReloadMode:
         b MPU_uxTimerGetReloadModeImpl
     MPU_uxTimerGetReloadMode_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTimerGetReloadModeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTimerGetReloadMode
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerGetPeriod
@@ -1029,10 +864,7 @@ MPU_xTimerGetPeriod:
         b MPU_xTimerGetPeriodImpl
     MPU_xTimerGetPeriod_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetPeriodImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGetPeriod
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerGetExpiryTime
@@ -1047,14 +879,11 @@ MPU_xTimerGetExpiryTime:
         b MPU_xTimerGetExpiryTimeImpl
     MPU_xTimerGetExpiryTime_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetExpiryTimeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGetExpiryTime
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xEventGroupWaitBits
-MPU_xEventGroupWaitBits:
+    PUBLIC MPU_xEventGroupWaitBitsEntry
+MPU_xEventGroupWaitBitsEntry:
     push {r0, r1}
     mrs r0, control
     movs r1, #1
@@ -1065,10 +894,7 @@ MPU_xEventGroupWaitBits:
         b MPU_xEventGroupWaitBitsImpl
     MPU_xEventGroupWaitBits_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xEventGroupWaitBitsImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xEventGroupWaitBits
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xEventGroupClearBits
@@ -1083,10 +909,7 @@ MPU_xEventGroupClearBits:
         b MPU_xEventGroupClearBitsImpl
     MPU_xEventGroupClearBits_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xEventGroupClearBitsImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xEventGroupClearBits
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xEventGroupSetBits
@@ -1101,10 +924,7 @@ MPU_xEventGroupSetBits:
         b MPU_xEventGroupSetBitsImpl
     MPU_xEventGroupSetBits_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xEventGroupSetBitsImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xEventGroupSetBits
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xEventGroupSync
@@ -1119,10 +939,7 @@ MPU_xEventGroupSync:
         b MPU_xEventGroupSyncImpl
     MPU_xEventGroupSync_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xEventGroupSyncImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xEventGroupSync
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxEventGroupGetNumber
@@ -1137,10 +954,7 @@ MPU_uxEventGroupGetNumber:
         b MPU_uxEventGroupGetNumberImpl
     MPU_uxEventGroupGetNumber_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxEventGroupGetNumberImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxEventGroupGetNumber
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vEventGroupSetNumber
@@ -1155,10 +969,7 @@ MPU_vEventGroupSetNumber:
         b MPU_vEventGroupSetNumberImpl
     MPU_vEventGroupSetNumber_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vEventGroupSetNumberImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vEventGroupSetNumber
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferSend
@@ -1173,10 +984,7 @@ MPU_xStreamBufferSend:
         b MPU_xStreamBufferSendImpl
     MPU_xStreamBufferSend_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferSendImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferSend
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferReceive
@@ -1191,10 +999,7 @@ MPU_xStreamBufferReceive:
         b MPU_xStreamBufferReceiveImpl
     MPU_xStreamBufferReceive_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferReceiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferReceive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferIsFull
@@ -1209,10 +1014,7 @@ MPU_xStreamBufferIsFull:
         b MPU_xStreamBufferIsFullImpl
     MPU_xStreamBufferIsFull_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferIsFullImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferIsFull
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferIsEmpty
@@ -1227,10 +1029,7 @@ MPU_xStreamBufferIsEmpty:
         b MPU_xStreamBufferIsEmptyImpl
     MPU_xStreamBufferIsEmpty_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferIsEmptyImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferIsEmpty
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferSpacesAvailable
@@ -1245,10 +1044,7 @@ MPU_xStreamBufferSpacesAvailable:
         b MPU_xStreamBufferSpacesAvailableImpl
     MPU_xStreamBufferSpacesAvailable_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferSpacesAvailableImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferSpacesAvailable
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferBytesAvailable
@@ -1263,10 +1059,7 @@ MPU_xStreamBufferBytesAvailable:
         b MPU_xStreamBufferBytesAvailableImpl
     MPU_xStreamBufferBytesAvailable_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferBytesAvailableImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferBytesAvailable
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferSetTriggerLevel
@@ -1281,10 +1074,7 @@ MPU_xStreamBufferSetTriggerLevel:
         b MPU_xStreamBufferSetTriggerLevelImpl
     MPU_xStreamBufferSetTriggerLevel_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferSetTriggerLevelImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferNextMessageLengthBytes
@@ -1299,10 +1089,7 @@ MPU_xStreamBufferNextMessageLengthBytes:
         b MPU_xStreamBufferNextMessageLengthBytesImpl
     MPU_xStreamBufferNextMessageLengthBytes_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferNextMessageLengthBytesImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes
 /*-----------------------------------------------------------*/
 
 /* Default weak implementations in case one is not available from
diff --git a/portable/IAR/ARM_CM23/non_secure/port.c b/portable/IAR/ARM_CM23/non_secure/port.c
index 52d68d3ea..6a3877894 100644
--- a/portable/IAR/ARM_CM23/non_secure/port.c
+++ b/portable/IAR/ARM_CM23/non_secure/port.c
@@ -35,8 +35,9 @@
 #include "FreeRTOS.h"
 #include "task.h"
 
-/* MPU wrappers includes. */
+/* MPU includes. */
 #include "mpu_wrappers.h"
+#include "mpu_syscall_numbers.h"
 
 /* Portasm includes. */
 #include "portasm.h"
@@ -436,29 +437,22 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
  * @brief Sets up the system call stack so that upon returning from
  * SVC, the system call stack is used.
  *
- * It is used for the system calls with up to 4 parameters.
- *
  * @param pulTaskStack The current SP when the SVC was raised.
  * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ * @param ucSystemCallNumber The system call number of the system call.
  */
     void vSystemCallEnter( uint32_t * pulTaskStack,
-                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
+                           uint32_t ulLR,
+                           uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
- * @brief Sets up the system call stack so that upon returning from
- * SVC, the system call stack is used.
- *
- * It is used for the system calls with 5 parameters.
- *
- * @param pulTaskStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ * @brief Raise SVC for exiting from a system call.
  */
-    void vSystemCallEnter_1( uint32_t * pulTaskStack,
-                             uint32_t ulLR ) PRIVILEGED_FUNCTION;
+    void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
@@ -488,6 +482,15 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+/**
+ * @brief This variable is set to pdTRUE when the scheduler is started.
+ */
+    PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
+
+#endif
+
 /**
  * @brief Each task maintains its own interrupt status in the critical nesting
  * variable.
@@ -1134,15 +1137,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     void vSystemCallEnter( uint32_t * pulTaskStack,
-                           uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
+                           uint32_t ulLR,
+                           uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */
     {
         extern TaskHandle_t pxCurrentTCB;
+        extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ];
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulSystemCallStack;
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
-
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __syscalls_flash_start__;
@@ -1154,17 +1158,27 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         #endif /* #if defined( __ARMCC_VERSION ) */
 
         ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
 
-        /* If the request did not come from the system call section, do nothing. */
+        /* Checks:
+         * 1. SVC is raised from the system call section (i.e. application is
+         *    not raising SVC directly).
+         * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as
+         *    it is non-NULL only during the execution of a system call (i.e.
+         *    between system call enter and exit).
+         * 3. System call is not for a kernel API disabled by the configuration
+         *    in FreeRTOSConfig.h.
+         * 4. We do not need to check that ucSystemCallNumber is within range
+         *    because the assembly SVC handler checks that before calling
+         *    this function.
+         */
         if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) &&
+            ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) &&
+            ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) )
         {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
             pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
 
-            /* This is not NULL only for the duration of the system call. */
-            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
-
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
@@ -1198,9 +1212,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 pulSystemCallStack[ i ] = pulTaskStack[ i ];
             }
 
-            /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
-             * restore it when we exit from the system call. */
+            /* Store the value of the Link Register before the SVC was raised.
+             * It contains the address of the caller of the System Call entry
+             * point (i.e. the caller of the MPU_<API>). We need to restore it
+             * when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            /* Store the value of the PSPLIM register before the SVC was raised.
+             * We need to restore it when we exit from the system call. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
             {
                 __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
@@ -1215,6 +1233,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             }
             #endif
 
+            /* Start executing the system call upon returning from this handler. */
+            pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
+            /* Raise a request to exit from the system call upon finishing the
+             * system call. */
+            pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit;
+
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
             pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
@@ -1251,127 +1275,9 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    void vSystemCallEnter_1( uint32_t * pulTaskStack,
-                             uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
+    void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */
     {
-        extern TaskHandle_t pxCurrentTCB;
-        xMPU_SETTINGS * pxMpuSettings;
-        uint32_t * pulSystemCallStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-
-        #if defined( __ARMCC_VERSION )
-
-            /* Declaration when these variable are defined in code instead of being
-             * exported from linker scripts. */
-            extern uint32_t * __syscalls_flash_start__;
-            extern uint32_t * __syscalls_flash_end__;
-        #else
-            /* Declaration when these variable are exported from linker scripts. */
-            extern uint32_t __syscalls_flash_start__[];
-            extern uint32_t __syscalls_flash_end__[];
-        #endif /* #if defined( __ARMCC_VERSION ) */
-
-        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-        /* If the request did not come from the system call section, do nothing. */
-        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
-        {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
-
-            /* This is not NULL only for the duration of the system call. */
-            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
-
-            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-            {
-                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
-                {
-                    /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
-                    __asm volatile (
-                        " vpush {s0}         \n" /* Trigger lazy stacking. */
-                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                        ::: "memory"
-                        );
-                }
-                else
-                {
-                    /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
-                }
-            }
-            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
-            {
-                ulStackFrameSize = 8;
-            }
-            #endif /* configENABLE_FPU || configENABLE_MVE */
-
-            /* Make space on the system call stack for the stack frame and
-             * the parameter passed on the stack. We only need to copy one
-             * parameter but we still reserve 2 spaces to keep the stack
-             * double word aligned. */
-            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
-
-            /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
-            {
-                pulSystemCallStack[ i ] = pulTaskStack[ i ];
-            }
-
-            /* Copy the parameter which is passed the stack. */
-            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-            {
-                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
-
-                /* Record if the hardware used padding to force the stack pointer
-                 * to be double word aligned. */
-                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-            }
-            else
-            {
-                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
-
-                /* Record if the hardware used padding to force the stack pointer
-                 * to be double word aligned. */
-                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-            }
-
-            /* Store the value of the LR and PSPLIM registers before the SVC was raised.
-             * We need to restore it when we exit from the system call. */
-            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            #if ( portUSE_PSPLIM_REGISTER == 1 )
-            {
-                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-            }
-            #endif
-
-            /* Use the pulSystemCallStack in thread mode. */
-            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            #if ( portUSE_PSPLIM_REGISTER == 1 )
-            {
-                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-            }
-            #endif
-
-            /* Remember the location where we should copy the stack frame when we exit from
-             * the system call. */
-            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-            /* We ensure in pxPortInitialiseStack that the system call stack is
-             * double word aligned and therefore, there is no need of padding.
-             * Clear the bit[9] of stacked xPSR. */
-            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-            /* Raise the privilege for the duration of the system call. */
-            __asm volatile (
-                " mrs r0, control     \n" /* Obtain current control value. */
-                " movs r1, #1         \n" /* r1 = 1. */
-                " bics r0, r1         \n" /* Clear nPRIV bit. */
-                " msr control, r0     \n" /* Write back new control value. */
-                ::: "r0", "r1", "memory"
-                );
-        }
+        __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" );
     }
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@@ -1388,24 +1294,32 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
-
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
-            extern uint32_t * __syscalls_flash_start__;
-            extern uint32_t * __syscalls_flash_end__;
+            extern uint32_t * __privileged_functions_start__;
+            extern uint32_t * __privileged_functions_end__;
         #else
             /* Declaration when these variable are exported from linker scripts. */
-            extern uint32_t __syscalls_flash_start__[];
-            extern uint32_t __syscalls_flash_end__[];
+            extern uint32_t __privileged_functions_start__[];
+            extern uint32_t __privileged_functions_end__[];
         #endif /* #if defined( __ARMCC_VERSION ) */
 
         ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
+        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
 
-        /* If the request did not come from the system call section, do nothing. */
-        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+        /* Checks:
+         * 1. SVC is raised from the privileged code (i.e. application is not
+         *    raising SVC directly). This SVC is only raised from
+         *    vRequestSystemCallExit which is in the privileged code section.
+         * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL -
+         *    this means that we previously entered a system call and the
+         *    application is not attempting to exit without entering a system
+         *    call.
+         */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) &&
+            ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) )
         {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
             pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
 
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
@@ -1444,9 +1358,14 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Use the pulTaskStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
 
-            /* Restore the LR and PSPLIM to what they were at the time of
-             * system call entry. */
+            /* Return to the caller of the System Call entry point (i.e. the
+             * caller of the MPU_<API>). */
+            pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+            /* Ensure that LR has a valid value.*/
             pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+
+            /* Restore the PSPLIM register to what it was at the time of
+             * system call entry. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
             {
                 __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
@@ -1780,6 +1699,12 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     /* Initialize the critical nesting count ready for the first task. */
     ulCriticalNesting = 0;
 
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+    {
+        xSchedulerRunning = pdTRUE;
+    }
+    #endif
+
     /* Start the first task. */
     vStartFirstTask();
 
@@ -2062,7 +1987,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
 
     void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
                                          int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
@@ -2078,10 +2003,10 @@ BaseType_t xPortIsInsideInterrupt( void )
         xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit );
     }
 
-#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
 
     void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
                                           int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
@@ -2097,10 +2022,10 @@ BaseType_t xPortIsInsideInterrupt( void )
         xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit );
     }
 
-#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
 
@@ -2108,21 +2033,34 @@ BaseType_t xPortIsInsideInterrupt( void )
         {
             uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
             BaseType_t xAccessGranted = pdFALSE;
-            const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+            const xMPU_SETTINGS * xTaskMpuSettings;
 
-            ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
-            ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
-
-            if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+            if( xSchedulerRunning == pdFALSE )
             {
+                /* Grant access to all the kernel objects before the scheduler
+                 * is started. It is necessary because there is no task running
+                 * yet and therefore, we cannot use the permissions of any
+                 * task. */
                 xAccessGranted = pdTRUE;
             }
             else
             {
-                if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+                ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+                ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+                if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
                 {
                     xAccessGranted = pdTRUE;
                 }
+                else
+                {
+                    if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                    {
+                        xAccessGranted = pdTRUE;
+                    }
+                }
             }
 
             return xAccessGranted;
@@ -2141,5 +2079,5 @@ BaseType_t xPortIsInsideInterrupt( void )
 
     #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
 
-#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM23/non_secure/portasm.s b/portable/IAR/ARM_CM23/non_secure/portasm.s
index 8c7000909..06c761090 100644
--- a/portable/IAR/ARM_CM23/non_secure/portasm.s
+++ b/portable/IAR/ARM_CM23/non_secure/portasm.s
@@ -33,6 +33,9 @@ the code is included in C files but excluded by the preprocessor in assembly
 files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
 #include "FreeRTOSConfig.h"
 
+/* System call numbers includes. */
+#include "mpu_syscall_numbers.h"
+
 #ifndef configUSE_MPU_WRAPPERS_V1
     #define configUSE_MPU_WRAPPERS_V1 0
 #endif
@@ -46,7 +49,6 @@ files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler.
     EXTERN SecureContext_LoadContext
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
     EXTERN vSystemCallEnter
-    EXTERN vSystemCallEnter_1
     EXTERN vSystemCallExit
 #endif
 
@@ -96,7 +98,7 @@ vResetPrivilege:
 /*-----------------------------------------------------------*/
 
 vPortAllocateSecureContext:
-    svc 0                                   /* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 0. */
+    svc 100                                 /* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 100. */
     bx lr                                   /* Return. */
 /*-----------------------------------------------------------*/
 
@@ -229,7 +231,7 @@ vStartFirstTask:
     cpsie i                                 /* Globally enable interrupts. */
     dsb
     isb
-    svc 2                                   /* System call to start the first task. portSVC_START_SCHEDULER = 2. */
+    svc 102                                 /* System call to start the first task. portSVC_START_SCHEDULER = 102. */
 /*-----------------------------------------------------------*/
 
 ulSetInterruptMask:
@@ -479,21 +481,17 @@ SVC_Handler:
         b route_svc
 
     route_svc:
-        ldr r2, [r0, #24]
-        subs r2, #2
-        ldrb r3, [r2, #0]
-        cmp r3, #4          /* portSVC_SYSTEM_CALL_ENTER. */
-        beq system_call_enter
-        cmp r3, #5          /* portSVC_SYSTEM_CALL_ENTER_1. */
-        beq system_call_enter_1
-        cmp r3, #6          /* portSVC_SYSTEM_CALL_EXIT. */
+        ldr r3, [r0, #24]
+        subs r3, #2
+        ldrb r2, [r3, #0]
+        cmp r2, #NUM_SYSTEM_CALLS
+        blt system_call_enter
+        cmp r2, #104        /* portSVC_SYSTEM_CALL_EXIT. */
         beq system_call_exit
         b vPortSVCHandler_C
 
     system_call_enter:
         b vSystemCallEnter
-    system_call_enter_1:
-        b vSystemCallEnter_1
     system_call_exit:
         b vSystemCallExit
 
@@ -520,7 +518,7 @@ vPortFreeSecureContext:
     bne free_secure_context                 /* Branch if r1 != 0. */
     bx lr                                   /* There is no secure context (xSecureContext is NULL). */
     free_secure_context:
-        svc 1                               /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */
+        svc 101                             /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 101. */
         bx lr                               /* Return. */
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h
index 60ef37380..672b0dbdc 100644
--- a/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h
@@ -322,14 +322,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 /**
  * @brief SVC numbers.
  */
-#define portSVC_ALLOCATE_SECURE_CONTEXT    0
-#define portSVC_FREE_SECURE_CONTEXT        1
-#define portSVC_START_SCHEDULER            2
-#define portSVC_RAISE_PRIVILEGE            3
-#define portSVC_SYSTEM_CALL_ENTER          4   /* System calls with upto 4 parameters. */
-#define portSVC_SYSTEM_CALL_ENTER_1        5   /* System calls with 5 parameters. */
-#define portSVC_SYSTEM_CALL_EXIT           6
-#define portSVC_YIELD                      7
+#define portSVC_ALLOCATE_SECURE_CONTEXT    100
+#define portSVC_FREE_SECURE_CONTEXT        101
+#define portSVC_START_SCHEDULER            102
+#define portSVC_RAISE_PRIVILEGE            103
+#define portSVC_SYSTEM_CALL_EXIT           104
+#define portSVC_YIELD                      105
 /*-----------------------------------------------------------*/
 
 /**
diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.S
index 5300a99ec..419df5b1e 100644
--- a/portable/IAR/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.S
+++ b/portable/IAR/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.S
@@ -32,15 +32,12 @@
 /*-----------------------------------------------------------*/
 
 #include "FreeRTOSConfig.h"
+#include "mpu_syscall_numbers.h"
 
 #ifndef configUSE_MPU_WRAPPERS_V1
     #define configUSE_MPU_WRAPPERS_V1 0
 #endif
 
-/* These must be in sync with portmacro.h. */
-#define portSVC_SYSTEM_CALL_ENTER   4 /* System calls with upto 4 parameters. */
-#define portSVC_SYSTEM_CALL_ENTER_1 5 /* System calls with 5 parameters. */
-#define portSVC_SYSTEM_CALL_EXIT    6
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
@@ -57,10 +54,7 @@ MPU_xTaskDelayUntil:
         b MPU_xTaskDelayUntilImpl
     MPU_xTaskDelayUntil_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskDelayUntilImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskDelayUntil
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskAbortDelay
@@ -75,10 +69,7 @@ MPU_xTaskAbortDelay:
         b MPU_xTaskAbortDelayImpl
     MPU_xTaskAbortDelay_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskAbortDelayImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskAbortDelay
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskDelay
@@ -93,10 +84,7 @@ MPU_vTaskDelay:
         b MPU_vTaskDelayImpl
     MPU_vTaskDelay_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskDelayImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskDelay
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskPriorityGet
@@ -111,10 +99,7 @@ MPU_uxTaskPriorityGet:
         b MPU_uxTaskPriorityGetImpl
     MPU_uxTaskPriorityGet_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskPriorityGetImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskPriorityGet
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_eTaskGetState
@@ -129,10 +114,7 @@ MPU_eTaskGetState:
         b MPU_eTaskGetStateImpl
     MPU_eTaskGetState_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_eTaskGetStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_eTaskGetState
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskGetInfo
@@ -147,10 +129,7 @@ MPU_vTaskGetInfo:
         b MPU_vTaskGetInfoImpl
     MPU_vTaskGetInfo_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskGetInfoImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskGetInfo
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetIdleTaskHandle
@@ -165,10 +144,7 @@ MPU_xTaskGetIdleTaskHandle:
         b MPU_xTaskGetIdleTaskHandleImpl
     MPU_xTaskGetIdleTaskHandle_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetIdleTaskHandleImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetIdleTaskHandle
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskSuspend
@@ -183,10 +159,7 @@ MPU_vTaskSuspend:
         b MPU_vTaskSuspendImpl
     MPU_vTaskSuspend_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSuspendImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskSuspend
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskResume
@@ -201,10 +174,7 @@ MPU_vTaskResume:
         b MPU_vTaskResumeImpl
     MPU_vTaskResume_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskResumeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskResume
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetTickCount
@@ -219,10 +189,7 @@ MPU_xTaskGetTickCount:
         b MPU_xTaskGetTickCountImpl
     MPU_xTaskGetTickCount_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetTickCountImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetTickCount
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskGetNumberOfTasks
@@ -237,10 +204,7 @@ MPU_uxTaskGetNumberOfTasks:
         b MPU_uxTaskGetNumberOfTasksImpl
     MPU_uxTaskGetNumberOfTasks_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetNumberOfTasksImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskGetNumberOfTasks
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGetRunTimeCounter
@@ -255,10 +219,7 @@ MPU_ulTaskGetRunTimeCounter:
         b MPU_ulTaskGetRunTimeCounterImpl
     MPU_ulTaskGetRunTimeCounter_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetRunTimeCounterImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGetRunTimeCounter
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGetRunTimePercent
@@ -273,10 +234,7 @@ MPU_ulTaskGetRunTimePercent:
         b MPU_ulTaskGetRunTimePercentImpl
     MPU_ulTaskGetRunTimePercent_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetRunTimePercentImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGetRunTimePercent
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGetIdleRunTimePercent
@@ -291,10 +249,7 @@ MPU_ulTaskGetIdleRunTimePercent:
         b MPU_ulTaskGetIdleRunTimePercentImpl
     MPU_ulTaskGetIdleRunTimePercent_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetIdleRunTimePercentImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGetIdleRunTimeCounter
@@ -309,10 +264,7 @@ MPU_ulTaskGetIdleRunTimeCounter:
         b MPU_ulTaskGetIdleRunTimeCounterImpl
     MPU_ulTaskGetIdleRunTimeCounter_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetIdleRunTimeCounterImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskSetApplicationTaskTag
@@ -327,10 +279,7 @@ MPU_vTaskSetApplicationTaskTag:
         b MPU_vTaskSetApplicationTaskTagImpl
     MPU_vTaskSetApplicationTaskTag_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSetApplicationTaskTagImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskSetApplicationTaskTag
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetApplicationTaskTag
@@ -345,10 +294,7 @@ MPU_xTaskGetApplicationTaskTag:
         b MPU_xTaskGetApplicationTaskTagImpl
     MPU_xTaskGetApplicationTaskTag_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetApplicationTaskTagImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetApplicationTaskTag
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskSetThreadLocalStoragePointer
@@ -363,10 +309,7 @@ MPU_vTaskSetThreadLocalStoragePointer:
         b MPU_vTaskSetThreadLocalStoragePointerImpl
     MPU_vTaskSetThreadLocalStoragePointer_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSetThreadLocalStoragePointerImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pvTaskGetThreadLocalStoragePointer
@@ -381,10 +324,7 @@ MPU_pvTaskGetThreadLocalStoragePointer:
         b MPU_pvTaskGetThreadLocalStoragePointerImpl
     MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pvTaskGetThreadLocalStoragePointerImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskGetSystemState
@@ -399,10 +339,7 @@ MPU_uxTaskGetSystemState:
         b MPU_uxTaskGetSystemStateImpl
     MPU_uxTaskGetSystemState_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetSystemStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskGetSystemState
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskGetStackHighWaterMark
@@ -417,10 +354,7 @@ MPU_uxTaskGetStackHighWaterMark:
         b MPU_uxTaskGetStackHighWaterMarkImpl
     MPU_uxTaskGetStackHighWaterMark_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetStackHighWaterMarkImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskGetStackHighWaterMark2
@@ -435,10 +369,7 @@ MPU_uxTaskGetStackHighWaterMark2:
         b MPU_uxTaskGetStackHighWaterMark2Impl
     MPU_uxTaskGetStackHighWaterMark2_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetStackHighWaterMark2Impl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetCurrentTaskHandle
@@ -453,10 +384,7 @@ MPU_xTaskGetCurrentTaskHandle:
         b MPU_xTaskGetCurrentTaskHandleImpl
     MPU_xTaskGetCurrentTaskHandle_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetCurrentTaskHandleImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetSchedulerState
@@ -471,10 +399,7 @@ MPU_xTaskGetSchedulerState:
         b MPU_xTaskGetSchedulerStateImpl
     MPU_xTaskGetSchedulerState_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetSchedulerStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetSchedulerState
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskSetTimeOutState
@@ -489,10 +414,7 @@ MPU_vTaskSetTimeOutState:
         b MPU_vTaskSetTimeOutStateImpl
     MPU_vTaskSetTimeOutState_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSetTimeOutStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskSetTimeOutState
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskCheckForTimeOut
@@ -507,14 +429,11 @@ MPU_xTaskCheckForTimeOut:
         b MPU_xTaskCheckForTimeOutImpl
     MPU_xTaskCheckForTimeOut_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskCheckForTimeOutImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskCheckForTimeOut
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xTaskGenericNotify
-MPU_xTaskGenericNotify:
+    PUBLIC MPU_xTaskGenericNotifyEntry
+MPU_xTaskGenericNotifyEntry:
     push {r0, r1}
     mrs r0, control
     movs r1, #1
@@ -525,14 +444,11 @@ MPU_xTaskGenericNotify:
         b MPU_xTaskGenericNotifyImpl
     MPU_xTaskGenericNotify_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTaskGenericNotifyImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGenericNotify
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xTaskGenericNotifyWait
-MPU_xTaskGenericNotifyWait:
+    PUBLIC MPU_xTaskGenericNotifyWaitEntry
+MPU_xTaskGenericNotifyWaitEntry:
     push {r0, r1}
     mrs r0, control
     movs r1, #1
@@ -543,10 +459,7 @@ MPU_xTaskGenericNotifyWait:
         b MPU_xTaskGenericNotifyWaitImpl
     MPU_xTaskGenericNotifyWait_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTaskGenericNotifyWaitImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGenericNotifyWait
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGenericNotifyTake
@@ -561,10 +474,7 @@ MPU_ulTaskGenericNotifyTake:
         b MPU_ulTaskGenericNotifyTakeImpl
     MPU_ulTaskGenericNotifyTake_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGenericNotifyTakeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGenericNotifyTake
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGenericNotifyStateClear
@@ -579,10 +489,7 @@ MPU_xTaskGenericNotifyStateClear:
         b MPU_xTaskGenericNotifyStateClearImpl
     MPU_xTaskGenericNotifyStateClear_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGenericNotifyStateClearImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGenericNotifyStateClear
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGenericNotifyValueClear
@@ -597,10 +504,7 @@ MPU_ulTaskGenericNotifyValueClear:
         b MPU_ulTaskGenericNotifyValueClearImpl
     MPU_ulTaskGenericNotifyValueClear_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGenericNotifyValueClearImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueGenericSend
@@ -615,10 +519,7 @@ MPU_xQueueGenericSend:
         b MPU_xQueueGenericSendImpl
     MPU_xQueueGenericSend_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueGenericSendImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueGenericSend
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxQueueMessagesWaiting
@@ -633,10 +534,7 @@ MPU_uxQueueMessagesWaiting:
         b MPU_uxQueueMessagesWaitingImpl
     MPU_uxQueueMessagesWaiting_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxQueueMessagesWaitingImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxQueueMessagesWaiting
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxQueueSpacesAvailable
@@ -651,10 +549,7 @@ MPU_uxQueueSpacesAvailable:
         b MPU_uxQueueSpacesAvailableImpl
     MPU_uxQueueSpacesAvailable_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxQueueSpacesAvailableImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxQueueSpacesAvailable
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueReceive
@@ -669,10 +564,7 @@ MPU_xQueueReceive:
         b MPU_xQueueReceiveImpl
     MPU_xQueueReceive_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueReceiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueReceive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueuePeek
@@ -687,10 +579,7 @@ MPU_xQueuePeek:
         b MPU_xQueuePeekImpl
     MPU_xQueuePeek_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueuePeekImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueuePeek
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueSemaphoreTake
@@ -705,10 +594,7 @@ MPU_xQueueSemaphoreTake:
         b MPU_xQueueSemaphoreTakeImpl
     MPU_xQueueSemaphoreTake_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueSemaphoreTakeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueSemaphoreTake
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueGetMutexHolder
@@ -723,10 +609,7 @@ MPU_xQueueGetMutexHolder:
         b MPU_xQueueGetMutexHolderImpl
     MPU_xQueueGetMutexHolder_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueGetMutexHolderImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueGetMutexHolder
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueTakeMutexRecursive
@@ -741,10 +624,7 @@ MPU_xQueueTakeMutexRecursive:
         b MPU_xQueueTakeMutexRecursiveImpl
     MPU_xQueueTakeMutexRecursive_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueTakeMutexRecursiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueTakeMutexRecursive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueGiveMutexRecursive
@@ -759,10 +639,7 @@ MPU_xQueueGiveMutexRecursive:
         b MPU_xQueueGiveMutexRecursiveImpl
     MPU_xQueueGiveMutexRecursive_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueGiveMutexRecursiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueGiveMutexRecursive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueSelectFromSet
@@ -777,10 +654,7 @@ MPU_xQueueSelectFromSet:
         b MPU_xQueueSelectFromSetImpl
     MPU_xQueueSelectFromSet_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueSelectFromSetImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueSelectFromSet
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueAddToSet
@@ -795,10 +669,7 @@ MPU_xQueueAddToSet:
         b MPU_xQueueAddToSetImpl
     MPU_xQueueAddToSet_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueAddToSetImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueAddToSet
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vQueueAddToRegistry
@@ -813,10 +684,7 @@ MPU_vQueueAddToRegistry:
         b MPU_vQueueAddToRegistryImpl
     MPU_vQueueAddToRegistry_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vQueueAddToRegistryImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vQueueAddToRegistry
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vQueueUnregisterQueue
@@ -831,10 +699,7 @@ MPU_vQueueUnregisterQueue:
         b MPU_vQueueUnregisterQueueImpl
     MPU_vQueueUnregisterQueue_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vQueueUnregisterQueueImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vQueueUnregisterQueue
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pcQueueGetName
@@ -849,10 +714,7 @@ MPU_pcQueueGetName:
         b MPU_pcQueueGetNameImpl
     MPU_pcQueueGetName_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pcQueueGetNameImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_pcQueueGetName
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pvTimerGetTimerID
@@ -867,10 +729,7 @@ MPU_pvTimerGetTimerID:
         b MPU_pvTimerGetTimerIDImpl
     MPU_pvTimerGetTimerID_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pvTimerGetTimerIDImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_pvTimerGetTimerID
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTimerSetTimerID
@@ -885,10 +744,7 @@ MPU_vTimerSetTimerID:
         b MPU_vTimerSetTimerIDImpl
     MPU_vTimerSetTimerID_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTimerSetTimerIDImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTimerSetTimerID
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerIsTimerActive
@@ -903,10 +759,7 @@ MPU_xTimerIsTimerActive:
         b MPU_xTimerIsTimerActiveImpl
     MPU_xTimerIsTimerActive_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerIsTimerActiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerIsTimerActive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerGetTimerDaemonTaskHandle
@@ -921,14 +774,11 @@ MPU_xTimerGetTimerDaemonTaskHandle:
         b MPU_xTimerGetTimerDaemonTaskHandleImpl
     MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetTimerDaemonTaskHandleImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xTimerGenericCommandFromTask
-MPU_xTimerGenericCommandFromTask:
+    PUBLIC MPU_xTimerGenericCommandFromTaskEntry
+MPU_xTimerGenericCommandFromTaskEntry:
     push {r0, r1}
     mrs r0, control
     movs r1, #1
@@ -939,10 +789,7 @@ MPU_xTimerGenericCommandFromTask:
         b MPU_xTimerGenericCommandFromTaskImpl
     MPU_xTimerGenericCommandFromTask_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTimerGenericCommandFromTaskImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGenericCommandFromTask
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pcTimerGetName
@@ -957,10 +804,7 @@ MPU_pcTimerGetName:
         b MPU_pcTimerGetNameImpl
     MPU_pcTimerGetName_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pcTimerGetNameImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_pcTimerGetName
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTimerSetReloadMode
@@ -975,10 +819,7 @@ MPU_vTimerSetReloadMode:
         b MPU_vTimerSetReloadModeImpl
     MPU_vTimerSetReloadMode_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTimerSetReloadModeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTimerSetReloadMode
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerGetReloadMode
@@ -993,10 +834,7 @@ MPU_xTimerGetReloadMode:
         b MPU_xTimerGetReloadModeImpl
     MPU_xTimerGetReloadMode_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetReloadModeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGetReloadMode
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTimerGetReloadMode
@@ -1011,10 +849,7 @@ MPU_uxTimerGetReloadMode:
         b MPU_uxTimerGetReloadModeImpl
     MPU_uxTimerGetReloadMode_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTimerGetReloadModeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTimerGetReloadMode
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerGetPeriod
@@ -1029,10 +864,7 @@ MPU_xTimerGetPeriod:
         b MPU_xTimerGetPeriodImpl
     MPU_xTimerGetPeriod_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetPeriodImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGetPeriod
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerGetExpiryTime
@@ -1047,14 +879,11 @@ MPU_xTimerGetExpiryTime:
         b MPU_xTimerGetExpiryTimeImpl
     MPU_xTimerGetExpiryTime_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetExpiryTimeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGetExpiryTime
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xEventGroupWaitBits
-MPU_xEventGroupWaitBits:
+    PUBLIC MPU_xEventGroupWaitBitsEntry
+MPU_xEventGroupWaitBitsEntry:
     push {r0, r1}
     mrs r0, control
     movs r1, #1
@@ -1065,10 +894,7 @@ MPU_xEventGroupWaitBits:
         b MPU_xEventGroupWaitBitsImpl
     MPU_xEventGroupWaitBits_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xEventGroupWaitBitsImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xEventGroupWaitBits
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xEventGroupClearBits
@@ -1083,10 +909,7 @@ MPU_xEventGroupClearBits:
         b MPU_xEventGroupClearBitsImpl
     MPU_xEventGroupClearBits_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xEventGroupClearBitsImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xEventGroupClearBits
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xEventGroupSetBits
@@ -1101,10 +924,7 @@ MPU_xEventGroupSetBits:
         b MPU_xEventGroupSetBitsImpl
     MPU_xEventGroupSetBits_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xEventGroupSetBitsImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xEventGroupSetBits
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xEventGroupSync
@@ -1119,10 +939,7 @@ MPU_xEventGroupSync:
         b MPU_xEventGroupSyncImpl
     MPU_xEventGroupSync_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xEventGroupSyncImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xEventGroupSync
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxEventGroupGetNumber
@@ -1137,10 +954,7 @@ MPU_uxEventGroupGetNumber:
         b MPU_uxEventGroupGetNumberImpl
     MPU_uxEventGroupGetNumber_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxEventGroupGetNumberImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxEventGroupGetNumber
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vEventGroupSetNumber
@@ -1155,10 +969,7 @@ MPU_vEventGroupSetNumber:
         b MPU_vEventGroupSetNumberImpl
     MPU_vEventGroupSetNumber_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vEventGroupSetNumberImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vEventGroupSetNumber
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferSend
@@ -1173,10 +984,7 @@ MPU_xStreamBufferSend:
         b MPU_xStreamBufferSendImpl
     MPU_xStreamBufferSend_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferSendImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferSend
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferReceive
@@ -1191,10 +999,7 @@ MPU_xStreamBufferReceive:
         b MPU_xStreamBufferReceiveImpl
     MPU_xStreamBufferReceive_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferReceiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferReceive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferIsFull
@@ -1209,10 +1014,7 @@ MPU_xStreamBufferIsFull:
         b MPU_xStreamBufferIsFullImpl
     MPU_xStreamBufferIsFull_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferIsFullImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferIsFull
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferIsEmpty
@@ -1227,10 +1029,7 @@ MPU_xStreamBufferIsEmpty:
         b MPU_xStreamBufferIsEmptyImpl
     MPU_xStreamBufferIsEmpty_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferIsEmptyImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferIsEmpty
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferSpacesAvailable
@@ -1245,10 +1044,7 @@ MPU_xStreamBufferSpacesAvailable:
         b MPU_xStreamBufferSpacesAvailableImpl
     MPU_xStreamBufferSpacesAvailable_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferSpacesAvailableImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferSpacesAvailable
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferBytesAvailable
@@ -1263,10 +1059,7 @@ MPU_xStreamBufferBytesAvailable:
         b MPU_xStreamBufferBytesAvailableImpl
     MPU_xStreamBufferBytesAvailable_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferBytesAvailableImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferBytesAvailable
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferSetTriggerLevel
@@ -1281,10 +1074,7 @@ MPU_xStreamBufferSetTriggerLevel:
         b MPU_xStreamBufferSetTriggerLevelImpl
     MPU_xStreamBufferSetTriggerLevel_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferSetTriggerLevelImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferNextMessageLengthBytes
@@ -1299,10 +1089,7 @@ MPU_xStreamBufferNextMessageLengthBytes:
         b MPU_xStreamBufferNextMessageLengthBytesImpl
     MPU_xStreamBufferNextMessageLengthBytes_Unpriv:
         pop {r0, r1}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferNextMessageLengthBytesImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes
 /*-----------------------------------------------------------*/
 
 /* Default weak implementations in case one is not available from
diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
index 52d68d3ea..6a3877894 100644
--- a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
@@ -35,8 +35,9 @@
 #include "FreeRTOS.h"
 #include "task.h"
 
-/* MPU wrappers includes. */
+/* MPU includes. */
 #include "mpu_wrappers.h"
+#include "mpu_syscall_numbers.h"
 
 /* Portasm includes. */
 #include "portasm.h"
@@ -436,29 +437,22 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
  * @brief Sets up the system call stack so that upon returning from
  * SVC, the system call stack is used.
  *
- * It is used for the system calls with up to 4 parameters.
- *
  * @param pulTaskStack The current SP when the SVC was raised.
  * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ * @param ucSystemCallNumber The system call number of the system call.
  */
     void vSystemCallEnter( uint32_t * pulTaskStack,
-                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
+                           uint32_t ulLR,
+                           uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
- * @brief Sets up the system call stack so that upon returning from
- * SVC, the system call stack is used.
- *
- * It is used for the system calls with 5 parameters.
- *
- * @param pulTaskStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ * @brief Raise SVC for exiting from a system call.
  */
-    void vSystemCallEnter_1( uint32_t * pulTaskStack,
-                             uint32_t ulLR ) PRIVILEGED_FUNCTION;
+    void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
@@ -488,6 +482,15 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+/**
+ * @brief This variable is set to pdTRUE when the scheduler is started.
+ */
+    PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
+
+#endif
+
 /**
  * @brief Each task maintains its own interrupt status in the critical nesting
  * variable.
@@ -1134,15 +1137,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     void vSystemCallEnter( uint32_t * pulTaskStack,
-                           uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
+                           uint32_t ulLR,
+                           uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */
     {
         extern TaskHandle_t pxCurrentTCB;
+        extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ];
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulSystemCallStack;
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
-
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __syscalls_flash_start__;
@@ -1154,17 +1158,27 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         #endif /* #if defined( __ARMCC_VERSION ) */
 
         ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
 
-        /* If the request did not come from the system call section, do nothing. */
+        /* Checks:
+         * 1. SVC is raised from the system call section (i.e. application is
+         *    not raising SVC directly).
+         * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as
+         *    it is non-NULL only during the execution of a system call (i.e.
+         *    between system call enter and exit).
+         * 3. System call is not for a kernel API disabled by the configuration
+         *    in FreeRTOSConfig.h.
+         * 4. We do not need to check that ucSystemCallNumber is within range
+         *    because the assembly SVC handler checks that before calling
+         *    this function.
+         */
         if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) &&
+            ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) &&
+            ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) )
         {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
             pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
 
-            /* This is not NULL only for the duration of the system call. */
-            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
-
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
@@ -1198,9 +1212,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 pulSystemCallStack[ i ] = pulTaskStack[ i ];
             }
 
-            /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
-             * restore it when we exit from the system call. */
+            /* Store the value of the Link Register before the SVC was raised.
+             * It contains the address of the caller of the System Call entry
+             * point (i.e. the caller of the MPU_<API>). We need to restore it
+             * when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            /* Store the value of the PSPLIM register before the SVC was raised.
+             * We need to restore it when we exit from the system call. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
             {
                 __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
@@ -1215,6 +1233,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             }
             #endif
 
+            /* Start executing the system call upon returning from this handler. */
+            pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
+            /* Raise a request to exit from the system call upon finishing the
+             * system call. */
+            pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit;
+
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
             pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
@@ -1251,127 +1275,9 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    void vSystemCallEnter_1( uint32_t * pulTaskStack,
-                             uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
+    void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */
     {
-        extern TaskHandle_t pxCurrentTCB;
-        xMPU_SETTINGS * pxMpuSettings;
-        uint32_t * pulSystemCallStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-
-        #if defined( __ARMCC_VERSION )
-
-            /* Declaration when these variable are defined in code instead of being
-             * exported from linker scripts. */
-            extern uint32_t * __syscalls_flash_start__;
-            extern uint32_t * __syscalls_flash_end__;
-        #else
-            /* Declaration when these variable are exported from linker scripts. */
-            extern uint32_t __syscalls_flash_start__[];
-            extern uint32_t __syscalls_flash_end__[];
-        #endif /* #if defined( __ARMCC_VERSION ) */
-
-        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-        /* If the request did not come from the system call section, do nothing. */
-        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
-        {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
-
-            /* This is not NULL only for the duration of the system call. */
-            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
-
-            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-            {
-                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
-                {
-                    /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
-                    __asm volatile (
-                        " vpush {s0}         \n" /* Trigger lazy stacking. */
-                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                        ::: "memory"
-                        );
-                }
-                else
-                {
-                    /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
-                }
-            }
-            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
-            {
-                ulStackFrameSize = 8;
-            }
-            #endif /* configENABLE_FPU || configENABLE_MVE */
-
-            /* Make space on the system call stack for the stack frame and
-             * the parameter passed on the stack. We only need to copy one
-             * parameter but we still reserve 2 spaces to keep the stack
-             * double word aligned. */
-            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
-
-            /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
-            {
-                pulSystemCallStack[ i ] = pulTaskStack[ i ];
-            }
-
-            /* Copy the parameter which is passed the stack. */
-            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-            {
-                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
-
-                /* Record if the hardware used padding to force the stack pointer
-                 * to be double word aligned. */
-                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-            }
-            else
-            {
-                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
-
-                /* Record if the hardware used padding to force the stack pointer
-                 * to be double word aligned. */
-                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-            }
-
-            /* Store the value of the LR and PSPLIM registers before the SVC was raised.
-             * We need to restore it when we exit from the system call. */
-            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            #if ( portUSE_PSPLIM_REGISTER == 1 )
-            {
-                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-            }
-            #endif
-
-            /* Use the pulSystemCallStack in thread mode. */
-            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            #if ( portUSE_PSPLIM_REGISTER == 1 )
-            {
-                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-            }
-            #endif
-
-            /* Remember the location where we should copy the stack frame when we exit from
-             * the system call. */
-            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-            /* We ensure in pxPortInitialiseStack that the system call stack is
-             * double word aligned and therefore, there is no need of padding.
-             * Clear the bit[9] of stacked xPSR. */
-            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-            /* Raise the privilege for the duration of the system call. */
-            __asm volatile (
-                " mrs r0, control     \n" /* Obtain current control value. */
-                " movs r1, #1         \n" /* r1 = 1. */
-                " bics r0, r1         \n" /* Clear nPRIV bit. */
-                " msr control, r0     \n" /* Write back new control value. */
-                ::: "r0", "r1", "memory"
-                );
-        }
+        __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" );
     }
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@@ -1388,24 +1294,32 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
-
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
-            extern uint32_t * __syscalls_flash_start__;
-            extern uint32_t * __syscalls_flash_end__;
+            extern uint32_t * __privileged_functions_start__;
+            extern uint32_t * __privileged_functions_end__;
         #else
             /* Declaration when these variable are exported from linker scripts. */
-            extern uint32_t __syscalls_flash_start__[];
-            extern uint32_t __syscalls_flash_end__[];
+            extern uint32_t __privileged_functions_start__[];
+            extern uint32_t __privileged_functions_end__[];
         #endif /* #if defined( __ARMCC_VERSION ) */
 
         ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
+        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
 
-        /* If the request did not come from the system call section, do nothing. */
-        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+        /* Checks:
+         * 1. SVC is raised from the privileged code (i.e. application is not
+         *    raising SVC directly). This SVC is only raised from
+         *    vRequestSystemCallExit which is in the privileged code section.
+         * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL -
+         *    this means that we previously entered a system call and the
+         *    application is not attempting to exit without entering a system
+         *    call.
+         */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) &&
+            ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) )
         {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
             pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
 
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
@@ -1444,9 +1358,14 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Use the pulTaskStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
 
-            /* Restore the LR and PSPLIM to what they were at the time of
-             * system call entry. */
+            /* Return to the caller of the System Call entry point (i.e. the
+             * caller of the MPU_<API>). */
+            pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+            /* Ensure that LR has a valid value.*/
             pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+
+            /* Restore the PSPLIM register to what it was at the time of
+             * system call entry. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
             {
                 __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
@@ -1780,6 +1699,12 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     /* Initialize the critical nesting count ready for the first task. */
     ulCriticalNesting = 0;
 
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+    {
+        xSchedulerRunning = pdTRUE;
+    }
+    #endif
+
     /* Start the first task. */
     vStartFirstTask();
 
@@ -2062,7 +1987,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
 
     void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
                                          int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
@@ -2078,10 +2003,10 @@ BaseType_t xPortIsInsideInterrupt( void )
         xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit );
     }
 
-#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
 
     void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
                                           int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
@@ -2097,10 +2022,10 @@ BaseType_t xPortIsInsideInterrupt( void )
         xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit );
     }
 
-#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
 
@@ -2108,21 +2033,34 @@ BaseType_t xPortIsInsideInterrupt( void )
         {
             uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
             BaseType_t xAccessGranted = pdFALSE;
-            const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+            const xMPU_SETTINGS * xTaskMpuSettings;
 
-            ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
-            ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
-
-            if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+            if( xSchedulerRunning == pdFALSE )
             {
+                /* Grant access to all the kernel objects before the scheduler
+                 * is started. It is necessary because there is no task running
+                 * yet and therefore, we cannot use the permissions of any
+                 * task. */
                 xAccessGranted = pdTRUE;
             }
             else
             {
-                if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+                ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+                ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+                if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
                 {
                     xAccessGranted = pdTRUE;
                 }
+                else
+                {
+                    if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                    {
+                        xAccessGranted = pdTRUE;
+                    }
+                }
             }
 
             return xAccessGranted;
@@ -2141,5 +2079,5 @@ BaseType_t xPortIsInsideInterrupt( void )
 
     #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
 
-#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s b/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s
index 836a927c8..d4487dfac 100644
--- a/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s
+++ b/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s
@@ -32,6 +32,9 @@ the code is included in C files but excluded by the preprocessor in assembly
 files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
 #include "FreeRTOSConfig.h"
 
+/* System call numbers includes. */
+#include "mpu_syscall_numbers.h"
+
 #ifndef configUSE_MPU_WRAPPERS_V1
     #define configUSE_MPU_WRAPPERS_V1 0
 #endif
@@ -45,7 +48,6 @@ files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler.
     EXTERN vPortSVCHandler_C
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
     EXTERN vSystemCallEnter
-    EXTERN vSystemCallEnter_1
     EXTERN vSystemCallExit
 #endif
 
@@ -224,7 +226,7 @@ vStartFirstTask:
     cpsie i                                 /* Globally enable interrupts. */
     dsb
     isb
-    svc 2                                   /* System call to start the first task. portSVC_START_SCHEDULER = 2. */
+    svc 102                                 /* System call to start the first task. portSVC_START_SCHEDULER = 102. */
     nop
 /*-----------------------------------------------------------*/
 
@@ -421,21 +423,17 @@ SVC_Handler:
         b route_svc
 
     route_svc:
-        ldr r2, [r0, #24]
-        subs r2, #2
-        ldrb r3, [r2, #0]
-        cmp r3, #4          /* portSVC_SYSTEM_CALL_ENTER. */
-        beq system_call_enter
-        cmp r3, #5          /* portSVC_SYSTEM_CALL_ENTER_1. */
-        beq system_call_enter_1
-        cmp r3, #6          /* portSVC_SYSTEM_CALL_EXIT. */
+        ldr r3, [r0, #24]
+        subs r3, #2
+        ldrb r2, [r3, #0]
+        cmp r2, #NUM_SYSTEM_CALLS
+        blt system_call_enter
+        cmp r2, #104        /* portSVC_SYSTEM_CALL_EXIT. */
         beq system_call_exit
         b vPortSVCHandler_C
 
     system_call_enter:
         b vSystemCallEnter
-    system_call_enter_1:
-        b vSystemCallEnter_1
     system_call_exit:
         b vSystemCallExit
 
diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h
index 60ef37380..672b0dbdc 100644
--- a/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h
@@ -322,14 +322,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 /**
  * @brief SVC numbers.
  */
-#define portSVC_ALLOCATE_SECURE_CONTEXT    0
-#define portSVC_FREE_SECURE_CONTEXT        1
-#define portSVC_START_SCHEDULER            2
-#define portSVC_RAISE_PRIVILEGE            3
-#define portSVC_SYSTEM_CALL_ENTER          4   /* System calls with upto 4 parameters. */
-#define portSVC_SYSTEM_CALL_ENTER_1        5   /* System calls with 5 parameters. */
-#define portSVC_SYSTEM_CALL_EXIT           6
-#define portSVC_YIELD                      7
+#define portSVC_ALLOCATE_SECURE_CONTEXT    100
+#define portSVC_FREE_SECURE_CONTEXT        101
+#define portSVC_START_SCHEDULER            102
+#define portSVC_RAISE_PRIVILEGE            103
+#define portSVC_SYSTEM_CALL_EXIT           104
+#define portSVC_YIELD                      105
 /*-----------------------------------------------------------*/
 
 /**
diff --git a/portable/IAR/ARM_CM33/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM33/non_secure/mpu_wrappers_v2_asm.S
index 1005dad33..80d5a1c63 100644
--- a/portable/IAR/ARM_CM33/non_secure/mpu_wrappers_v2_asm.S
+++ b/portable/IAR/ARM_CM33/non_secure/mpu_wrappers_v2_asm.S
@@ -32,15 +32,12 @@
 /*-----------------------------------------------------------*/
 
 #include "FreeRTOSConfig.h"
+#include "mpu_syscall_numbers.h"
 
 #ifndef configUSE_MPU_WRAPPERS_V1
     #define configUSE_MPU_WRAPPERS_V1 0
 #endif
 
-/* These must be in sync with portmacro.h. */
-#define portSVC_SYSTEM_CALL_ENTER   4 /* System calls with upto 4 parameters. */
-#define portSVC_SYSTEM_CALL_ENTER_1 5 /* System calls with 5 parameters. */
-#define portSVC_SYSTEM_CALL_EXIT    6
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
@@ -56,10 +53,7 @@ MPU_xTaskDelayUntil:
         b MPU_xTaskDelayUntilImpl
     MPU_xTaskDelayUntil_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskDelayUntilImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskDelayUntil
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskAbortDelay
@@ -73,10 +67,7 @@ MPU_xTaskAbortDelay:
         b MPU_xTaskAbortDelayImpl
     MPU_xTaskAbortDelay_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskAbortDelayImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskAbortDelay
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskDelay
@@ -90,10 +81,7 @@ MPU_vTaskDelay:
         b MPU_vTaskDelayImpl
     MPU_vTaskDelay_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskDelayImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskDelay
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskPriorityGet
@@ -107,10 +95,7 @@ MPU_uxTaskPriorityGet:
         b MPU_uxTaskPriorityGetImpl
     MPU_uxTaskPriorityGet_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskPriorityGetImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskPriorityGet
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_eTaskGetState
@@ -124,10 +109,7 @@ MPU_eTaskGetState:
         b MPU_eTaskGetStateImpl
     MPU_eTaskGetState_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_eTaskGetStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_eTaskGetState
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskGetInfo
@@ -141,10 +123,7 @@ MPU_vTaskGetInfo:
         b MPU_vTaskGetInfoImpl
     MPU_vTaskGetInfo_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskGetInfoImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskGetInfo
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetIdleTaskHandle
@@ -158,10 +137,7 @@ MPU_xTaskGetIdleTaskHandle:
         b MPU_xTaskGetIdleTaskHandleImpl
     MPU_xTaskGetIdleTaskHandle_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetIdleTaskHandleImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetIdleTaskHandle
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskSuspend
@@ -175,10 +151,7 @@ MPU_vTaskSuspend:
         b MPU_vTaskSuspendImpl
     MPU_vTaskSuspend_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSuspendImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskSuspend
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskResume
@@ -192,10 +165,7 @@ MPU_vTaskResume:
         b MPU_vTaskResumeImpl
     MPU_vTaskResume_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskResumeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskResume
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetTickCount
@@ -209,10 +179,7 @@ MPU_xTaskGetTickCount:
         b MPU_xTaskGetTickCountImpl
     MPU_xTaskGetTickCount_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetTickCountImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetTickCount
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskGetNumberOfTasks
@@ -226,10 +193,7 @@ MPU_uxTaskGetNumberOfTasks:
         b MPU_uxTaskGetNumberOfTasksImpl
     MPU_uxTaskGetNumberOfTasks_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetNumberOfTasksImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskGetNumberOfTasks
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGetRunTimeCounter
@@ -243,10 +207,7 @@ MPU_ulTaskGetRunTimeCounter:
         b MPU_ulTaskGetRunTimeCounterImpl
     MPU_ulTaskGetRunTimeCounter_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetRunTimeCounterImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGetRunTimeCounter
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGetRunTimePercent
@@ -260,10 +221,7 @@ MPU_ulTaskGetRunTimePercent:
         b MPU_ulTaskGetRunTimePercentImpl
     MPU_ulTaskGetRunTimePercent_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetRunTimePercentImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGetRunTimePercent
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGetIdleRunTimePercent
@@ -277,10 +235,7 @@ MPU_ulTaskGetIdleRunTimePercent:
         b MPU_ulTaskGetIdleRunTimePercentImpl
     MPU_ulTaskGetIdleRunTimePercent_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetIdleRunTimePercentImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGetIdleRunTimeCounter
@@ -294,10 +249,7 @@ MPU_ulTaskGetIdleRunTimeCounter:
         b MPU_ulTaskGetIdleRunTimeCounterImpl
     MPU_ulTaskGetIdleRunTimeCounter_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetIdleRunTimeCounterImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskSetApplicationTaskTag
@@ -311,10 +263,7 @@ MPU_vTaskSetApplicationTaskTag:
         b MPU_vTaskSetApplicationTaskTagImpl
     MPU_vTaskSetApplicationTaskTag_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSetApplicationTaskTagImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskSetApplicationTaskTag
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetApplicationTaskTag
@@ -328,10 +277,7 @@ MPU_xTaskGetApplicationTaskTag:
         b MPU_xTaskGetApplicationTaskTagImpl
     MPU_xTaskGetApplicationTaskTag_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetApplicationTaskTagImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetApplicationTaskTag
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskSetThreadLocalStoragePointer
@@ -345,10 +291,7 @@ MPU_vTaskSetThreadLocalStoragePointer:
         b MPU_vTaskSetThreadLocalStoragePointerImpl
     MPU_vTaskSetThreadLocalStoragePointer_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSetThreadLocalStoragePointerImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pvTaskGetThreadLocalStoragePointer
@@ -362,10 +305,7 @@ MPU_pvTaskGetThreadLocalStoragePointer:
         b MPU_pvTaskGetThreadLocalStoragePointerImpl
     MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pvTaskGetThreadLocalStoragePointerImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskGetSystemState
@@ -379,10 +319,7 @@ MPU_uxTaskGetSystemState:
         b MPU_uxTaskGetSystemStateImpl
     MPU_uxTaskGetSystemState_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetSystemStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskGetSystemState
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskGetStackHighWaterMark
@@ -396,10 +333,7 @@ MPU_uxTaskGetStackHighWaterMark:
         b MPU_uxTaskGetStackHighWaterMarkImpl
     MPU_uxTaskGetStackHighWaterMark_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetStackHighWaterMarkImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskGetStackHighWaterMark2
@@ -413,10 +347,7 @@ MPU_uxTaskGetStackHighWaterMark2:
         b MPU_uxTaskGetStackHighWaterMark2Impl
     MPU_uxTaskGetStackHighWaterMark2_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetStackHighWaterMark2Impl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetCurrentTaskHandle
@@ -430,10 +361,7 @@ MPU_xTaskGetCurrentTaskHandle:
         b MPU_xTaskGetCurrentTaskHandleImpl
     MPU_xTaskGetCurrentTaskHandle_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetCurrentTaskHandleImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetSchedulerState
@@ -447,10 +375,7 @@ MPU_xTaskGetSchedulerState:
         b MPU_xTaskGetSchedulerStateImpl
     MPU_xTaskGetSchedulerState_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetSchedulerStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetSchedulerState
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskSetTimeOutState
@@ -464,10 +389,7 @@ MPU_vTaskSetTimeOutState:
         b MPU_vTaskSetTimeOutStateImpl
     MPU_vTaskSetTimeOutState_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSetTimeOutStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskSetTimeOutState
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskCheckForTimeOut
@@ -481,14 +403,11 @@ MPU_xTaskCheckForTimeOut:
         b MPU_xTaskCheckForTimeOutImpl
     MPU_xTaskCheckForTimeOut_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskCheckForTimeOutImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskCheckForTimeOut
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xTaskGenericNotify
-MPU_xTaskGenericNotify:
+    PUBLIC MPU_xTaskGenericNotifyEntry
+MPU_xTaskGenericNotifyEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
@@ -498,14 +417,11 @@ MPU_xTaskGenericNotify:
         b MPU_xTaskGenericNotifyImpl
     MPU_xTaskGenericNotify_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTaskGenericNotifyImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGenericNotify
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xTaskGenericNotifyWait
-MPU_xTaskGenericNotifyWait:
+    PUBLIC MPU_xTaskGenericNotifyWaitEntry
+MPU_xTaskGenericNotifyWaitEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
@@ -515,10 +431,7 @@ MPU_xTaskGenericNotifyWait:
         b MPU_xTaskGenericNotifyWaitImpl
     MPU_xTaskGenericNotifyWait_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTaskGenericNotifyWaitImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGenericNotifyWait
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGenericNotifyTake
@@ -532,10 +445,7 @@ MPU_ulTaskGenericNotifyTake:
         b MPU_ulTaskGenericNotifyTakeImpl
     MPU_ulTaskGenericNotifyTake_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGenericNotifyTakeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGenericNotifyTake
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGenericNotifyStateClear
@@ -549,10 +459,7 @@ MPU_xTaskGenericNotifyStateClear:
         b MPU_xTaskGenericNotifyStateClearImpl
     MPU_xTaskGenericNotifyStateClear_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGenericNotifyStateClearImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGenericNotifyStateClear
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGenericNotifyValueClear
@@ -566,10 +473,7 @@ MPU_ulTaskGenericNotifyValueClear:
         b MPU_ulTaskGenericNotifyValueClearImpl
     MPU_ulTaskGenericNotifyValueClear_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGenericNotifyValueClearImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueGenericSend
@@ -583,10 +487,7 @@ MPU_xQueueGenericSend:
         b MPU_xQueueGenericSendImpl
     MPU_xQueueGenericSend_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueGenericSendImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueGenericSend
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxQueueMessagesWaiting
@@ -600,10 +501,7 @@ MPU_uxQueueMessagesWaiting:
         b MPU_uxQueueMessagesWaitingImpl
     MPU_uxQueueMessagesWaiting_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxQueueMessagesWaitingImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxQueueMessagesWaiting
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxQueueSpacesAvailable
@@ -617,10 +515,7 @@ MPU_uxQueueSpacesAvailable:
         b MPU_uxQueueSpacesAvailableImpl
     MPU_uxQueueSpacesAvailable_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxQueueSpacesAvailableImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxQueueSpacesAvailable
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueReceive
@@ -634,10 +529,7 @@ MPU_xQueueReceive:
         b MPU_xQueueReceiveImpl
     MPU_xQueueReceive_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueReceiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueReceive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueuePeek
@@ -651,10 +543,7 @@ MPU_xQueuePeek:
         b MPU_xQueuePeekImpl
     MPU_xQueuePeek_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueuePeekImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueuePeek
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueSemaphoreTake
@@ -668,10 +557,7 @@ MPU_xQueueSemaphoreTake:
         b MPU_xQueueSemaphoreTakeImpl
     MPU_xQueueSemaphoreTake_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueSemaphoreTakeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueSemaphoreTake
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueGetMutexHolder
@@ -685,10 +571,7 @@ MPU_xQueueGetMutexHolder:
         b MPU_xQueueGetMutexHolderImpl
     MPU_xQueueGetMutexHolder_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueGetMutexHolderImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueGetMutexHolder
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueTakeMutexRecursive
@@ -702,10 +585,7 @@ MPU_xQueueTakeMutexRecursive:
         b MPU_xQueueTakeMutexRecursiveImpl
     MPU_xQueueTakeMutexRecursive_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueTakeMutexRecursiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueTakeMutexRecursive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueGiveMutexRecursive
@@ -719,10 +599,7 @@ MPU_xQueueGiveMutexRecursive:
         b MPU_xQueueGiveMutexRecursiveImpl
     MPU_xQueueGiveMutexRecursive_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueGiveMutexRecursiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueGiveMutexRecursive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueSelectFromSet
@@ -736,10 +613,7 @@ MPU_xQueueSelectFromSet:
         b MPU_xQueueSelectFromSetImpl
     MPU_xQueueSelectFromSet_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueSelectFromSetImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueSelectFromSet
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueAddToSet
@@ -753,10 +627,7 @@ MPU_xQueueAddToSet:
         b MPU_xQueueAddToSetImpl
     MPU_xQueueAddToSet_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueAddToSetImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueAddToSet
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vQueueAddToRegistry
@@ -770,10 +641,7 @@ MPU_vQueueAddToRegistry:
         b MPU_vQueueAddToRegistryImpl
     MPU_vQueueAddToRegistry_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vQueueAddToRegistryImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vQueueAddToRegistry
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vQueueUnregisterQueue
@@ -787,10 +655,7 @@ MPU_vQueueUnregisterQueue:
         b MPU_vQueueUnregisterQueueImpl
     MPU_vQueueUnregisterQueue_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vQueueUnregisterQueueImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vQueueUnregisterQueue
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pcQueueGetName
@@ -804,10 +669,7 @@ MPU_pcQueueGetName:
         b MPU_pcQueueGetNameImpl
     MPU_pcQueueGetName_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pcQueueGetNameImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_pcQueueGetName
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pvTimerGetTimerID
@@ -821,10 +683,7 @@ MPU_pvTimerGetTimerID:
         b MPU_pvTimerGetTimerIDImpl
     MPU_pvTimerGetTimerID_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pvTimerGetTimerIDImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_pvTimerGetTimerID
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTimerSetTimerID
@@ -838,10 +697,7 @@ MPU_vTimerSetTimerID:
         b MPU_vTimerSetTimerIDImpl
     MPU_vTimerSetTimerID_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTimerSetTimerIDImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTimerSetTimerID
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerIsTimerActive
@@ -855,10 +711,7 @@ MPU_xTimerIsTimerActive:
         b MPU_xTimerIsTimerActiveImpl
     MPU_xTimerIsTimerActive_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerIsTimerActiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerIsTimerActive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerGetTimerDaemonTaskHandle
@@ -872,14 +725,11 @@ MPU_xTimerGetTimerDaemonTaskHandle:
         b MPU_xTimerGetTimerDaemonTaskHandleImpl
     MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetTimerDaemonTaskHandleImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xTimerGenericCommandFromTask
-MPU_xTimerGenericCommandFromTask:
+    PUBLIC MPU_xTimerGenericCommandFromTaskEntry
+MPU_xTimerGenericCommandFromTaskEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
@@ -889,10 +739,7 @@ MPU_xTimerGenericCommandFromTask:
         b MPU_xTimerGenericCommandFromTaskImpl
     MPU_xTimerGenericCommandFromTask_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTimerGenericCommandFromTaskImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGenericCommandFromTask
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pcTimerGetName
@@ -906,10 +753,7 @@ MPU_pcTimerGetName:
         b MPU_pcTimerGetNameImpl
     MPU_pcTimerGetName_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pcTimerGetNameImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_pcTimerGetName
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTimerSetReloadMode
@@ -923,10 +767,7 @@ MPU_vTimerSetReloadMode:
         b MPU_vTimerSetReloadModeImpl
     MPU_vTimerSetReloadMode_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTimerSetReloadModeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTimerSetReloadMode
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerGetReloadMode
@@ -940,10 +781,7 @@ MPU_xTimerGetReloadMode:
         b MPU_xTimerGetReloadModeImpl
     MPU_xTimerGetReloadMode_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetReloadModeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGetReloadMode
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTimerGetReloadMode
@@ -957,10 +795,7 @@ MPU_uxTimerGetReloadMode:
         b MPU_uxTimerGetReloadModeImpl
     MPU_uxTimerGetReloadMode_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTimerGetReloadModeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTimerGetReloadMode
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerGetPeriod
@@ -974,10 +809,7 @@ MPU_xTimerGetPeriod:
         b MPU_xTimerGetPeriodImpl
     MPU_xTimerGetPeriod_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetPeriodImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGetPeriod
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerGetExpiryTime
@@ -991,14 +823,11 @@ MPU_xTimerGetExpiryTime:
         b MPU_xTimerGetExpiryTimeImpl
     MPU_xTimerGetExpiryTime_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetExpiryTimeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGetExpiryTime
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xEventGroupWaitBits
-MPU_xEventGroupWaitBits:
+    PUBLIC MPU_xEventGroupWaitBitsEntry
+MPU_xEventGroupWaitBitsEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
@@ -1008,10 +837,7 @@ MPU_xEventGroupWaitBits:
         b MPU_xEventGroupWaitBitsImpl
     MPU_xEventGroupWaitBits_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xEventGroupWaitBitsImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xEventGroupWaitBits
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xEventGroupClearBits
@@ -1025,10 +851,7 @@ MPU_xEventGroupClearBits:
         b MPU_xEventGroupClearBitsImpl
     MPU_xEventGroupClearBits_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xEventGroupClearBitsImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xEventGroupClearBits
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xEventGroupSetBits
@@ -1042,10 +865,7 @@ MPU_xEventGroupSetBits:
         b MPU_xEventGroupSetBitsImpl
     MPU_xEventGroupSetBits_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xEventGroupSetBitsImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xEventGroupSetBits
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xEventGroupSync
@@ -1059,10 +879,7 @@ MPU_xEventGroupSync:
         b MPU_xEventGroupSyncImpl
     MPU_xEventGroupSync_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xEventGroupSyncImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xEventGroupSync
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxEventGroupGetNumber
@@ -1076,10 +893,7 @@ MPU_uxEventGroupGetNumber:
         b MPU_uxEventGroupGetNumberImpl
     MPU_uxEventGroupGetNumber_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxEventGroupGetNumberImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxEventGroupGetNumber
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vEventGroupSetNumber
@@ -1093,10 +907,7 @@ MPU_vEventGroupSetNumber:
         b MPU_vEventGroupSetNumberImpl
     MPU_vEventGroupSetNumber_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vEventGroupSetNumberImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vEventGroupSetNumber
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferSend
@@ -1110,10 +921,7 @@ MPU_xStreamBufferSend:
         b MPU_xStreamBufferSendImpl
     MPU_xStreamBufferSend_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferSendImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferSend
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferReceive
@@ -1127,10 +935,7 @@ MPU_xStreamBufferReceive:
         b MPU_xStreamBufferReceiveImpl
     MPU_xStreamBufferReceive_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferReceiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferReceive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferIsFull
@@ -1144,10 +949,7 @@ MPU_xStreamBufferIsFull:
         b MPU_xStreamBufferIsFullImpl
     MPU_xStreamBufferIsFull_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferIsFullImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferIsFull
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferIsEmpty
@@ -1161,10 +963,7 @@ MPU_xStreamBufferIsEmpty:
         b MPU_xStreamBufferIsEmptyImpl
     MPU_xStreamBufferIsEmpty_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferIsEmptyImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferIsEmpty
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferSpacesAvailable
@@ -1178,10 +977,7 @@ MPU_xStreamBufferSpacesAvailable:
         b MPU_xStreamBufferSpacesAvailableImpl
     MPU_xStreamBufferSpacesAvailable_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferSpacesAvailableImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferSpacesAvailable
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferBytesAvailable
@@ -1195,10 +991,7 @@ MPU_xStreamBufferBytesAvailable:
         b MPU_xStreamBufferBytesAvailableImpl
     MPU_xStreamBufferBytesAvailable_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferBytesAvailableImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferBytesAvailable
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferSetTriggerLevel
@@ -1212,10 +1005,7 @@ MPU_xStreamBufferSetTriggerLevel:
         b MPU_xStreamBufferSetTriggerLevelImpl
     MPU_xStreamBufferSetTriggerLevel_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferSetTriggerLevelImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferNextMessageLengthBytes
@@ -1229,10 +1019,7 @@ MPU_xStreamBufferNextMessageLengthBytes:
         b MPU_xStreamBufferNextMessageLengthBytesImpl
     MPU_xStreamBufferNextMessageLengthBytes_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferNextMessageLengthBytesImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes
 /*-----------------------------------------------------------*/
 
 /* Default weak implementations in case one is not available from
diff --git a/portable/IAR/ARM_CM33/non_secure/port.c b/portable/IAR/ARM_CM33/non_secure/port.c
index 52d68d3ea..6a3877894 100644
--- a/portable/IAR/ARM_CM33/non_secure/port.c
+++ b/portable/IAR/ARM_CM33/non_secure/port.c
@@ -35,8 +35,9 @@
 #include "FreeRTOS.h"
 #include "task.h"
 
-/* MPU wrappers includes. */
+/* MPU includes. */
 #include "mpu_wrappers.h"
+#include "mpu_syscall_numbers.h"
 
 /* Portasm includes. */
 #include "portasm.h"
@@ -436,29 +437,22 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
  * @brief Sets up the system call stack so that upon returning from
  * SVC, the system call stack is used.
  *
- * It is used for the system calls with up to 4 parameters.
- *
  * @param pulTaskStack The current SP when the SVC was raised.
  * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ * @param ucSystemCallNumber The system call number of the system call.
  */
     void vSystemCallEnter( uint32_t * pulTaskStack,
-                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
+                           uint32_t ulLR,
+                           uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
- * @brief Sets up the system call stack so that upon returning from
- * SVC, the system call stack is used.
- *
- * It is used for the system calls with 5 parameters.
- *
- * @param pulTaskStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ * @brief Raise SVC for exiting from a system call.
  */
-    void vSystemCallEnter_1( uint32_t * pulTaskStack,
-                             uint32_t ulLR ) PRIVILEGED_FUNCTION;
+    void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
@@ -488,6 +482,15 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+/**
+ * @brief This variable is set to pdTRUE when the scheduler is started.
+ */
+    PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
+
+#endif
+
 /**
  * @brief Each task maintains its own interrupt status in the critical nesting
  * variable.
@@ -1134,15 +1137,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     void vSystemCallEnter( uint32_t * pulTaskStack,
-                           uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
+                           uint32_t ulLR,
+                           uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */
     {
         extern TaskHandle_t pxCurrentTCB;
+        extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ];
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulSystemCallStack;
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
-
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __syscalls_flash_start__;
@@ -1154,17 +1158,27 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         #endif /* #if defined( __ARMCC_VERSION ) */
 
         ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
 
-        /* If the request did not come from the system call section, do nothing. */
+        /* Checks:
+         * 1. SVC is raised from the system call section (i.e. application is
+         *    not raising SVC directly).
+         * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as
+         *    it is non-NULL only during the execution of a system call (i.e.
+         *    between system call enter and exit).
+         * 3. System call is not for a kernel API disabled by the configuration
+         *    in FreeRTOSConfig.h.
+         * 4. We do not need to check that ucSystemCallNumber is within range
+         *    because the assembly SVC handler checks that before calling
+         *    this function.
+         */
         if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) &&
+            ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) &&
+            ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) )
         {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
             pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
 
-            /* This is not NULL only for the duration of the system call. */
-            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
-
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
@@ -1198,9 +1212,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 pulSystemCallStack[ i ] = pulTaskStack[ i ];
             }
 
-            /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
-             * restore it when we exit from the system call. */
+            /* Store the value of the Link Register before the SVC was raised.
+             * It contains the address of the caller of the System Call entry
+             * point (i.e. the caller of the MPU_<API>). We need to restore it
+             * when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            /* Store the value of the PSPLIM register before the SVC was raised.
+             * We need to restore it when we exit from the system call. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
             {
                 __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
@@ -1215,6 +1233,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             }
             #endif
 
+            /* Start executing the system call upon returning from this handler. */
+            pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
+            /* Raise a request to exit from the system call upon finishing the
+             * system call. */
+            pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit;
+
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
             pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
@@ -1251,127 +1275,9 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    void vSystemCallEnter_1( uint32_t * pulTaskStack,
-                             uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
+    void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */
     {
-        extern TaskHandle_t pxCurrentTCB;
-        xMPU_SETTINGS * pxMpuSettings;
-        uint32_t * pulSystemCallStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-
-        #if defined( __ARMCC_VERSION )
-
-            /* Declaration when these variable are defined in code instead of being
-             * exported from linker scripts. */
-            extern uint32_t * __syscalls_flash_start__;
-            extern uint32_t * __syscalls_flash_end__;
-        #else
-            /* Declaration when these variable are exported from linker scripts. */
-            extern uint32_t __syscalls_flash_start__[];
-            extern uint32_t __syscalls_flash_end__[];
-        #endif /* #if defined( __ARMCC_VERSION ) */
-
-        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-        /* If the request did not come from the system call section, do nothing. */
-        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
-        {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
-
-            /* This is not NULL only for the duration of the system call. */
-            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
-
-            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-            {
-                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
-                {
-                    /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
-                    __asm volatile (
-                        " vpush {s0}         \n" /* Trigger lazy stacking. */
-                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                        ::: "memory"
-                        );
-                }
-                else
-                {
-                    /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
-                }
-            }
-            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
-            {
-                ulStackFrameSize = 8;
-            }
-            #endif /* configENABLE_FPU || configENABLE_MVE */
-
-            /* Make space on the system call stack for the stack frame and
-             * the parameter passed on the stack. We only need to copy one
-             * parameter but we still reserve 2 spaces to keep the stack
-             * double word aligned. */
-            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
-
-            /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
-            {
-                pulSystemCallStack[ i ] = pulTaskStack[ i ];
-            }
-
-            /* Copy the parameter which is passed the stack. */
-            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-            {
-                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
-
-                /* Record if the hardware used padding to force the stack pointer
-                 * to be double word aligned. */
-                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-            }
-            else
-            {
-                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
-
-                /* Record if the hardware used padding to force the stack pointer
-                 * to be double word aligned. */
-                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-            }
-
-            /* Store the value of the LR and PSPLIM registers before the SVC was raised.
-             * We need to restore it when we exit from the system call. */
-            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            #if ( portUSE_PSPLIM_REGISTER == 1 )
-            {
-                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-            }
-            #endif
-
-            /* Use the pulSystemCallStack in thread mode. */
-            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            #if ( portUSE_PSPLIM_REGISTER == 1 )
-            {
-                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-            }
-            #endif
-
-            /* Remember the location where we should copy the stack frame when we exit from
-             * the system call. */
-            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-            /* We ensure in pxPortInitialiseStack that the system call stack is
-             * double word aligned and therefore, there is no need of padding.
-             * Clear the bit[9] of stacked xPSR. */
-            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-            /* Raise the privilege for the duration of the system call. */
-            __asm volatile (
-                " mrs r0, control     \n" /* Obtain current control value. */
-                " movs r1, #1         \n" /* r1 = 1. */
-                " bics r0, r1         \n" /* Clear nPRIV bit. */
-                " msr control, r0     \n" /* Write back new control value. */
-                ::: "r0", "r1", "memory"
-                );
-        }
+        __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" );
     }
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@@ -1388,24 +1294,32 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
-
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
-            extern uint32_t * __syscalls_flash_start__;
-            extern uint32_t * __syscalls_flash_end__;
+            extern uint32_t * __privileged_functions_start__;
+            extern uint32_t * __privileged_functions_end__;
         #else
             /* Declaration when these variable are exported from linker scripts. */
-            extern uint32_t __syscalls_flash_start__[];
-            extern uint32_t __syscalls_flash_end__[];
+            extern uint32_t __privileged_functions_start__[];
+            extern uint32_t __privileged_functions_end__[];
         #endif /* #if defined( __ARMCC_VERSION ) */
 
         ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
+        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
 
-        /* If the request did not come from the system call section, do nothing. */
-        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+        /* Checks:
+         * 1. SVC is raised from the privileged code (i.e. application is not
+         *    raising SVC directly). This SVC is only raised from
+         *    vRequestSystemCallExit which is in the privileged code section.
+         * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL -
+         *    this means that we previously entered a system call and the
+         *    application is not attempting to exit without entering a system
+         *    call.
+         */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) &&
+            ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) )
         {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
             pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
 
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
@@ -1444,9 +1358,14 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Use the pulTaskStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
 
-            /* Restore the LR and PSPLIM to what they were at the time of
-             * system call entry. */
+            /* Return to the caller of the System Call entry point (i.e. the
+             * caller of the MPU_<API>). */
+            pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+            /* Ensure that LR has a valid value.*/
             pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+
+            /* Restore the PSPLIM register to what it was at the time of
+             * system call entry. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
             {
                 __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
@@ -1780,6 +1699,12 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     /* Initialize the critical nesting count ready for the first task. */
     ulCriticalNesting = 0;
 
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+    {
+        xSchedulerRunning = pdTRUE;
+    }
+    #endif
+
     /* Start the first task. */
     vStartFirstTask();
 
@@ -2062,7 +1987,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
 
     void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
                                          int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
@@ -2078,10 +2003,10 @@ BaseType_t xPortIsInsideInterrupt( void )
         xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit );
     }
 
-#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
 
     void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
                                           int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
@@ -2097,10 +2022,10 @@ BaseType_t xPortIsInsideInterrupt( void )
         xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit );
     }
 
-#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
 
@@ -2108,21 +2033,34 @@ BaseType_t xPortIsInsideInterrupt( void )
         {
             uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
             BaseType_t xAccessGranted = pdFALSE;
-            const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+            const xMPU_SETTINGS * xTaskMpuSettings;
 
-            ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
-            ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
-
-            if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+            if( xSchedulerRunning == pdFALSE )
             {
+                /* Grant access to all the kernel objects before the scheduler
+                 * is started. It is necessary because there is no task running
+                 * yet and therefore, we cannot use the permissions of any
+                 * task. */
                 xAccessGranted = pdTRUE;
             }
             else
             {
-                if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+                ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+                ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+                if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
                 {
                     xAccessGranted = pdTRUE;
                 }
+                else
+                {
+                    if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                    {
+                        xAccessGranted = pdTRUE;
+                    }
+                }
             }
 
             return xAccessGranted;
@@ -2141,5 +2079,5 @@ BaseType_t xPortIsInsideInterrupt( void )
 
     #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
 
-#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM33/non_secure/portasm.s b/portable/IAR/ARM_CM33/non_secure/portasm.s
index 15e74ffc1..d8f1b1d9a 100644
--- a/portable/IAR/ARM_CM33/non_secure/portasm.s
+++ b/portable/IAR/ARM_CM33/non_secure/portasm.s
@@ -32,6 +32,9 @@ the code is included in C files but excluded by the preprocessor in assembly
 files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
 #include "FreeRTOSConfig.h"
 
+/* System call numbers includes. */
+#include "mpu_syscall_numbers.h"
+
 #ifndef configUSE_MPU_WRAPPERS_V1
     #define configUSE_MPU_WRAPPERS_V1 0
 #endif
@@ -44,7 +47,6 @@ files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler.
     EXTERN SecureContext_LoadContext
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
     EXTERN vSystemCallEnter
-    EXTERN vSystemCallEnter_1
     EXTERN vSystemCallExit
 #endif
 
@@ -86,7 +88,7 @@ vResetPrivilege:
 /*-----------------------------------------------------------*/
 
 vPortAllocateSecureContext:
-    svc 0                                   /* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 0. */
+    svc 100                                 /* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 100. */
     bx lr                                   /* Return. */
 /*-----------------------------------------------------------*/
 
@@ -205,7 +207,7 @@ vStartFirstTask:
     cpsie f
     dsb
     isb
-    svc 2                                   /* System call to start the first task. portSVC_START_SCHEDULER = 2. */
+    svc 102                                 /* System call to start the first task. portSVC_START_SCHEDULER = 102. */
 /*-----------------------------------------------------------*/
 
 ulSetInterruptMask:
@@ -455,11 +457,9 @@ SVC_Handler:
 
     ldr r1, [r0, #24]
     ldrb r2, [r1, #-2]
-    cmp r2, #4          /* portSVC_SYSTEM_CALL_ENTER. */
-    beq syscall_enter
-    cmp r2, #5          /* portSVC_SYSTEM_CALL_ENTER_1. */
-    beq syscall_enter_1
-    cmp r2, #6          /* portSVC_SYSTEM_CALL_EXIT. */
+    cmp r2, #NUM_SYSTEM_CALLS
+    blt syscall_enter
+    cmp r2, #104            /* portSVC_SYSTEM_CALL_EXIT. */
     beq syscall_exit
     b vPortSVCHandler_C
 
@@ -467,10 +467,6 @@ SVC_Handler:
         mov r1, lr
         b vSystemCallEnter
 
-    syscall_enter_1:
-        mov r1, lr
-        b vSystemCallEnter_1
-
     syscall_exit:
         mov r1, lr
         b vSystemCallExit
@@ -493,7 +489,7 @@ vPortFreeSecureContext:
     ldr r1, [r2]                            /* The first item on the stack is the task's xSecureContext. */
     cmp r1, #0                              /* Raise svc if task's xSecureContext is not NULL. */
     it ne
-    svcne 1                                 /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */
+    svcne 101                               /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 101. */
     bx lr                                   /* Return. */
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h
index 60ef37380..672b0dbdc 100644
--- a/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h
@@ -322,14 +322,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 /**
  * @brief SVC numbers.
  */
-#define portSVC_ALLOCATE_SECURE_CONTEXT    0
-#define portSVC_FREE_SECURE_CONTEXT        1
-#define portSVC_START_SCHEDULER            2
-#define portSVC_RAISE_PRIVILEGE            3
-#define portSVC_SYSTEM_CALL_ENTER          4   /* System calls with upto 4 parameters. */
-#define portSVC_SYSTEM_CALL_ENTER_1        5   /* System calls with 5 parameters. */
-#define portSVC_SYSTEM_CALL_EXIT           6
-#define portSVC_YIELD                      7
+#define portSVC_ALLOCATE_SECURE_CONTEXT    100
+#define portSVC_FREE_SECURE_CONTEXT        101
+#define portSVC_START_SCHEDULER            102
+#define portSVC_RAISE_PRIVILEGE            103
+#define portSVC_SYSTEM_CALL_EXIT           104
+#define portSVC_YIELD                      105
 /*-----------------------------------------------------------*/
 
 /**
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.S
index 1005dad33..80d5a1c63 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.S
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.S
@@ -32,15 +32,12 @@
 /*-----------------------------------------------------------*/
 
 #include "FreeRTOSConfig.h"
+#include "mpu_syscall_numbers.h"
 
 #ifndef configUSE_MPU_WRAPPERS_V1
     #define configUSE_MPU_WRAPPERS_V1 0
 #endif
 
-/* These must be in sync with portmacro.h. */
-#define portSVC_SYSTEM_CALL_ENTER   4 /* System calls with upto 4 parameters. */
-#define portSVC_SYSTEM_CALL_ENTER_1 5 /* System calls with 5 parameters. */
-#define portSVC_SYSTEM_CALL_EXIT    6
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
@@ -56,10 +53,7 @@ MPU_xTaskDelayUntil:
         b MPU_xTaskDelayUntilImpl
     MPU_xTaskDelayUntil_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskDelayUntilImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskDelayUntil
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskAbortDelay
@@ -73,10 +67,7 @@ MPU_xTaskAbortDelay:
         b MPU_xTaskAbortDelayImpl
     MPU_xTaskAbortDelay_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskAbortDelayImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskAbortDelay
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskDelay
@@ -90,10 +81,7 @@ MPU_vTaskDelay:
         b MPU_vTaskDelayImpl
     MPU_vTaskDelay_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskDelayImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskDelay
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskPriorityGet
@@ -107,10 +95,7 @@ MPU_uxTaskPriorityGet:
         b MPU_uxTaskPriorityGetImpl
     MPU_uxTaskPriorityGet_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskPriorityGetImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskPriorityGet
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_eTaskGetState
@@ -124,10 +109,7 @@ MPU_eTaskGetState:
         b MPU_eTaskGetStateImpl
     MPU_eTaskGetState_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_eTaskGetStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_eTaskGetState
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskGetInfo
@@ -141,10 +123,7 @@ MPU_vTaskGetInfo:
         b MPU_vTaskGetInfoImpl
     MPU_vTaskGetInfo_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskGetInfoImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskGetInfo
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetIdleTaskHandle
@@ -158,10 +137,7 @@ MPU_xTaskGetIdleTaskHandle:
         b MPU_xTaskGetIdleTaskHandleImpl
     MPU_xTaskGetIdleTaskHandle_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetIdleTaskHandleImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetIdleTaskHandle
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskSuspend
@@ -175,10 +151,7 @@ MPU_vTaskSuspend:
         b MPU_vTaskSuspendImpl
     MPU_vTaskSuspend_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSuspendImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskSuspend
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskResume
@@ -192,10 +165,7 @@ MPU_vTaskResume:
         b MPU_vTaskResumeImpl
     MPU_vTaskResume_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskResumeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskResume
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetTickCount
@@ -209,10 +179,7 @@ MPU_xTaskGetTickCount:
         b MPU_xTaskGetTickCountImpl
     MPU_xTaskGetTickCount_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetTickCountImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetTickCount
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskGetNumberOfTasks
@@ -226,10 +193,7 @@ MPU_uxTaskGetNumberOfTasks:
         b MPU_uxTaskGetNumberOfTasksImpl
     MPU_uxTaskGetNumberOfTasks_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetNumberOfTasksImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskGetNumberOfTasks
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGetRunTimeCounter
@@ -243,10 +207,7 @@ MPU_ulTaskGetRunTimeCounter:
         b MPU_ulTaskGetRunTimeCounterImpl
     MPU_ulTaskGetRunTimeCounter_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetRunTimeCounterImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGetRunTimeCounter
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGetRunTimePercent
@@ -260,10 +221,7 @@ MPU_ulTaskGetRunTimePercent:
         b MPU_ulTaskGetRunTimePercentImpl
     MPU_ulTaskGetRunTimePercent_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetRunTimePercentImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGetRunTimePercent
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGetIdleRunTimePercent
@@ -277,10 +235,7 @@ MPU_ulTaskGetIdleRunTimePercent:
         b MPU_ulTaskGetIdleRunTimePercentImpl
     MPU_ulTaskGetIdleRunTimePercent_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetIdleRunTimePercentImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGetIdleRunTimeCounter
@@ -294,10 +249,7 @@ MPU_ulTaskGetIdleRunTimeCounter:
         b MPU_ulTaskGetIdleRunTimeCounterImpl
     MPU_ulTaskGetIdleRunTimeCounter_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetIdleRunTimeCounterImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskSetApplicationTaskTag
@@ -311,10 +263,7 @@ MPU_vTaskSetApplicationTaskTag:
         b MPU_vTaskSetApplicationTaskTagImpl
     MPU_vTaskSetApplicationTaskTag_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSetApplicationTaskTagImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskSetApplicationTaskTag
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetApplicationTaskTag
@@ -328,10 +277,7 @@ MPU_xTaskGetApplicationTaskTag:
         b MPU_xTaskGetApplicationTaskTagImpl
     MPU_xTaskGetApplicationTaskTag_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetApplicationTaskTagImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetApplicationTaskTag
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskSetThreadLocalStoragePointer
@@ -345,10 +291,7 @@ MPU_vTaskSetThreadLocalStoragePointer:
         b MPU_vTaskSetThreadLocalStoragePointerImpl
     MPU_vTaskSetThreadLocalStoragePointer_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSetThreadLocalStoragePointerImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pvTaskGetThreadLocalStoragePointer
@@ -362,10 +305,7 @@ MPU_pvTaskGetThreadLocalStoragePointer:
         b MPU_pvTaskGetThreadLocalStoragePointerImpl
     MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pvTaskGetThreadLocalStoragePointerImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskGetSystemState
@@ -379,10 +319,7 @@ MPU_uxTaskGetSystemState:
         b MPU_uxTaskGetSystemStateImpl
     MPU_uxTaskGetSystemState_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetSystemStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskGetSystemState
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskGetStackHighWaterMark
@@ -396,10 +333,7 @@ MPU_uxTaskGetStackHighWaterMark:
         b MPU_uxTaskGetStackHighWaterMarkImpl
     MPU_uxTaskGetStackHighWaterMark_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetStackHighWaterMarkImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskGetStackHighWaterMark2
@@ -413,10 +347,7 @@ MPU_uxTaskGetStackHighWaterMark2:
         b MPU_uxTaskGetStackHighWaterMark2Impl
     MPU_uxTaskGetStackHighWaterMark2_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetStackHighWaterMark2Impl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetCurrentTaskHandle
@@ -430,10 +361,7 @@ MPU_xTaskGetCurrentTaskHandle:
         b MPU_xTaskGetCurrentTaskHandleImpl
     MPU_xTaskGetCurrentTaskHandle_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetCurrentTaskHandleImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetSchedulerState
@@ -447,10 +375,7 @@ MPU_xTaskGetSchedulerState:
         b MPU_xTaskGetSchedulerStateImpl
     MPU_xTaskGetSchedulerState_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetSchedulerStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetSchedulerState
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskSetTimeOutState
@@ -464,10 +389,7 @@ MPU_vTaskSetTimeOutState:
         b MPU_vTaskSetTimeOutStateImpl
     MPU_vTaskSetTimeOutState_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSetTimeOutStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskSetTimeOutState
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskCheckForTimeOut
@@ -481,14 +403,11 @@ MPU_xTaskCheckForTimeOut:
         b MPU_xTaskCheckForTimeOutImpl
     MPU_xTaskCheckForTimeOut_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskCheckForTimeOutImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskCheckForTimeOut
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xTaskGenericNotify
-MPU_xTaskGenericNotify:
+    PUBLIC MPU_xTaskGenericNotifyEntry
+MPU_xTaskGenericNotifyEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
@@ -498,14 +417,11 @@ MPU_xTaskGenericNotify:
         b MPU_xTaskGenericNotifyImpl
     MPU_xTaskGenericNotify_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTaskGenericNotifyImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGenericNotify
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xTaskGenericNotifyWait
-MPU_xTaskGenericNotifyWait:
+    PUBLIC MPU_xTaskGenericNotifyWaitEntry
+MPU_xTaskGenericNotifyWaitEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
@@ -515,10 +431,7 @@ MPU_xTaskGenericNotifyWait:
         b MPU_xTaskGenericNotifyWaitImpl
     MPU_xTaskGenericNotifyWait_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTaskGenericNotifyWaitImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGenericNotifyWait
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGenericNotifyTake
@@ -532,10 +445,7 @@ MPU_ulTaskGenericNotifyTake:
         b MPU_ulTaskGenericNotifyTakeImpl
     MPU_ulTaskGenericNotifyTake_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGenericNotifyTakeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGenericNotifyTake
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGenericNotifyStateClear
@@ -549,10 +459,7 @@ MPU_xTaskGenericNotifyStateClear:
         b MPU_xTaskGenericNotifyStateClearImpl
     MPU_xTaskGenericNotifyStateClear_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGenericNotifyStateClearImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGenericNotifyStateClear
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGenericNotifyValueClear
@@ -566,10 +473,7 @@ MPU_ulTaskGenericNotifyValueClear:
         b MPU_ulTaskGenericNotifyValueClearImpl
     MPU_ulTaskGenericNotifyValueClear_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGenericNotifyValueClearImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueGenericSend
@@ -583,10 +487,7 @@ MPU_xQueueGenericSend:
         b MPU_xQueueGenericSendImpl
     MPU_xQueueGenericSend_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueGenericSendImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueGenericSend
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxQueueMessagesWaiting
@@ -600,10 +501,7 @@ MPU_uxQueueMessagesWaiting:
         b MPU_uxQueueMessagesWaitingImpl
     MPU_uxQueueMessagesWaiting_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxQueueMessagesWaitingImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxQueueMessagesWaiting
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxQueueSpacesAvailable
@@ -617,10 +515,7 @@ MPU_uxQueueSpacesAvailable:
         b MPU_uxQueueSpacesAvailableImpl
     MPU_uxQueueSpacesAvailable_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxQueueSpacesAvailableImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxQueueSpacesAvailable
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueReceive
@@ -634,10 +529,7 @@ MPU_xQueueReceive:
         b MPU_xQueueReceiveImpl
     MPU_xQueueReceive_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueReceiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueReceive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueuePeek
@@ -651,10 +543,7 @@ MPU_xQueuePeek:
         b MPU_xQueuePeekImpl
     MPU_xQueuePeek_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueuePeekImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueuePeek
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueSemaphoreTake
@@ -668,10 +557,7 @@ MPU_xQueueSemaphoreTake:
         b MPU_xQueueSemaphoreTakeImpl
     MPU_xQueueSemaphoreTake_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueSemaphoreTakeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueSemaphoreTake
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueGetMutexHolder
@@ -685,10 +571,7 @@ MPU_xQueueGetMutexHolder:
         b MPU_xQueueGetMutexHolderImpl
     MPU_xQueueGetMutexHolder_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueGetMutexHolderImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueGetMutexHolder
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueTakeMutexRecursive
@@ -702,10 +585,7 @@ MPU_xQueueTakeMutexRecursive:
         b MPU_xQueueTakeMutexRecursiveImpl
     MPU_xQueueTakeMutexRecursive_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueTakeMutexRecursiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueTakeMutexRecursive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueGiveMutexRecursive
@@ -719,10 +599,7 @@ MPU_xQueueGiveMutexRecursive:
         b MPU_xQueueGiveMutexRecursiveImpl
     MPU_xQueueGiveMutexRecursive_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueGiveMutexRecursiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueGiveMutexRecursive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueSelectFromSet
@@ -736,10 +613,7 @@ MPU_xQueueSelectFromSet:
         b MPU_xQueueSelectFromSetImpl
     MPU_xQueueSelectFromSet_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueSelectFromSetImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueSelectFromSet
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueAddToSet
@@ -753,10 +627,7 @@ MPU_xQueueAddToSet:
         b MPU_xQueueAddToSetImpl
     MPU_xQueueAddToSet_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueAddToSetImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueAddToSet
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vQueueAddToRegistry
@@ -770,10 +641,7 @@ MPU_vQueueAddToRegistry:
         b MPU_vQueueAddToRegistryImpl
     MPU_vQueueAddToRegistry_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vQueueAddToRegistryImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vQueueAddToRegistry
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vQueueUnregisterQueue
@@ -787,10 +655,7 @@ MPU_vQueueUnregisterQueue:
         b MPU_vQueueUnregisterQueueImpl
     MPU_vQueueUnregisterQueue_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vQueueUnregisterQueueImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vQueueUnregisterQueue
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pcQueueGetName
@@ -804,10 +669,7 @@ MPU_pcQueueGetName:
         b MPU_pcQueueGetNameImpl
     MPU_pcQueueGetName_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pcQueueGetNameImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_pcQueueGetName
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pvTimerGetTimerID
@@ -821,10 +683,7 @@ MPU_pvTimerGetTimerID:
         b MPU_pvTimerGetTimerIDImpl
     MPU_pvTimerGetTimerID_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pvTimerGetTimerIDImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_pvTimerGetTimerID
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTimerSetTimerID
@@ -838,10 +697,7 @@ MPU_vTimerSetTimerID:
         b MPU_vTimerSetTimerIDImpl
     MPU_vTimerSetTimerID_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTimerSetTimerIDImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTimerSetTimerID
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerIsTimerActive
@@ -855,10 +711,7 @@ MPU_xTimerIsTimerActive:
         b MPU_xTimerIsTimerActiveImpl
     MPU_xTimerIsTimerActive_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerIsTimerActiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerIsTimerActive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerGetTimerDaemonTaskHandle
@@ -872,14 +725,11 @@ MPU_xTimerGetTimerDaemonTaskHandle:
         b MPU_xTimerGetTimerDaemonTaskHandleImpl
     MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetTimerDaemonTaskHandleImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xTimerGenericCommandFromTask
-MPU_xTimerGenericCommandFromTask:
+    PUBLIC MPU_xTimerGenericCommandFromTaskEntry
+MPU_xTimerGenericCommandFromTaskEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
@@ -889,10 +739,7 @@ MPU_xTimerGenericCommandFromTask:
         b MPU_xTimerGenericCommandFromTaskImpl
     MPU_xTimerGenericCommandFromTask_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTimerGenericCommandFromTaskImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGenericCommandFromTask
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pcTimerGetName
@@ -906,10 +753,7 @@ MPU_pcTimerGetName:
         b MPU_pcTimerGetNameImpl
     MPU_pcTimerGetName_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pcTimerGetNameImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_pcTimerGetName
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTimerSetReloadMode
@@ -923,10 +767,7 @@ MPU_vTimerSetReloadMode:
         b MPU_vTimerSetReloadModeImpl
     MPU_vTimerSetReloadMode_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTimerSetReloadModeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTimerSetReloadMode
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerGetReloadMode
@@ -940,10 +781,7 @@ MPU_xTimerGetReloadMode:
         b MPU_xTimerGetReloadModeImpl
     MPU_xTimerGetReloadMode_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetReloadModeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGetReloadMode
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTimerGetReloadMode
@@ -957,10 +795,7 @@ MPU_uxTimerGetReloadMode:
         b MPU_uxTimerGetReloadModeImpl
     MPU_uxTimerGetReloadMode_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTimerGetReloadModeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTimerGetReloadMode
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerGetPeriod
@@ -974,10 +809,7 @@ MPU_xTimerGetPeriod:
         b MPU_xTimerGetPeriodImpl
     MPU_xTimerGetPeriod_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetPeriodImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGetPeriod
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerGetExpiryTime
@@ -991,14 +823,11 @@ MPU_xTimerGetExpiryTime:
         b MPU_xTimerGetExpiryTimeImpl
     MPU_xTimerGetExpiryTime_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetExpiryTimeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGetExpiryTime
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xEventGroupWaitBits
-MPU_xEventGroupWaitBits:
+    PUBLIC MPU_xEventGroupWaitBitsEntry
+MPU_xEventGroupWaitBitsEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
@@ -1008,10 +837,7 @@ MPU_xEventGroupWaitBits:
         b MPU_xEventGroupWaitBitsImpl
     MPU_xEventGroupWaitBits_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xEventGroupWaitBitsImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xEventGroupWaitBits
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xEventGroupClearBits
@@ -1025,10 +851,7 @@ MPU_xEventGroupClearBits:
         b MPU_xEventGroupClearBitsImpl
     MPU_xEventGroupClearBits_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xEventGroupClearBitsImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xEventGroupClearBits
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xEventGroupSetBits
@@ -1042,10 +865,7 @@ MPU_xEventGroupSetBits:
         b MPU_xEventGroupSetBitsImpl
     MPU_xEventGroupSetBits_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xEventGroupSetBitsImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xEventGroupSetBits
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xEventGroupSync
@@ -1059,10 +879,7 @@ MPU_xEventGroupSync:
         b MPU_xEventGroupSyncImpl
     MPU_xEventGroupSync_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xEventGroupSyncImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xEventGroupSync
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxEventGroupGetNumber
@@ -1076,10 +893,7 @@ MPU_uxEventGroupGetNumber:
         b MPU_uxEventGroupGetNumberImpl
     MPU_uxEventGroupGetNumber_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxEventGroupGetNumberImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxEventGroupGetNumber
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vEventGroupSetNumber
@@ -1093,10 +907,7 @@ MPU_vEventGroupSetNumber:
         b MPU_vEventGroupSetNumberImpl
     MPU_vEventGroupSetNumber_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vEventGroupSetNumberImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vEventGroupSetNumber
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferSend
@@ -1110,10 +921,7 @@ MPU_xStreamBufferSend:
         b MPU_xStreamBufferSendImpl
     MPU_xStreamBufferSend_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferSendImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferSend
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferReceive
@@ -1127,10 +935,7 @@ MPU_xStreamBufferReceive:
         b MPU_xStreamBufferReceiveImpl
     MPU_xStreamBufferReceive_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferReceiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferReceive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferIsFull
@@ -1144,10 +949,7 @@ MPU_xStreamBufferIsFull:
         b MPU_xStreamBufferIsFullImpl
     MPU_xStreamBufferIsFull_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferIsFullImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferIsFull
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferIsEmpty
@@ -1161,10 +963,7 @@ MPU_xStreamBufferIsEmpty:
         b MPU_xStreamBufferIsEmptyImpl
     MPU_xStreamBufferIsEmpty_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferIsEmptyImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferIsEmpty
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferSpacesAvailable
@@ -1178,10 +977,7 @@ MPU_xStreamBufferSpacesAvailable:
         b MPU_xStreamBufferSpacesAvailableImpl
     MPU_xStreamBufferSpacesAvailable_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferSpacesAvailableImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferSpacesAvailable
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferBytesAvailable
@@ -1195,10 +991,7 @@ MPU_xStreamBufferBytesAvailable:
         b MPU_xStreamBufferBytesAvailableImpl
     MPU_xStreamBufferBytesAvailable_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferBytesAvailableImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferBytesAvailable
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferSetTriggerLevel
@@ -1212,10 +1005,7 @@ MPU_xStreamBufferSetTriggerLevel:
         b MPU_xStreamBufferSetTriggerLevelImpl
     MPU_xStreamBufferSetTriggerLevel_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferSetTriggerLevelImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferNextMessageLengthBytes
@@ -1229,10 +1019,7 @@ MPU_xStreamBufferNextMessageLengthBytes:
         b MPU_xStreamBufferNextMessageLengthBytesImpl
     MPU_xStreamBufferNextMessageLengthBytes_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferNextMessageLengthBytesImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes
 /*-----------------------------------------------------------*/
 
 /* Default weak implementations in case one is not available from
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
index 52d68d3ea..6a3877894 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
@@ -35,8 +35,9 @@
 #include "FreeRTOS.h"
 #include "task.h"
 
-/* MPU wrappers includes. */
+/* MPU includes. */
 #include "mpu_wrappers.h"
+#include "mpu_syscall_numbers.h"
 
 /* Portasm includes. */
 #include "portasm.h"
@@ -436,29 +437,22 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
  * @brief Sets up the system call stack so that upon returning from
  * SVC, the system call stack is used.
  *
- * It is used for the system calls with up to 4 parameters.
- *
  * @param pulTaskStack The current SP when the SVC was raised.
  * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ * @param ucSystemCallNumber The system call number of the system call.
  */
     void vSystemCallEnter( uint32_t * pulTaskStack,
-                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
+                           uint32_t ulLR,
+                           uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
- * @brief Sets up the system call stack so that upon returning from
- * SVC, the system call stack is used.
- *
- * It is used for the system calls with 5 parameters.
- *
- * @param pulTaskStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ * @brief Raise SVC for exiting from a system call.
  */
-    void vSystemCallEnter_1( uint32_t * pulTaskStack,
-                             uint32_t ulLR ) PRIVILEGED_FUNCTION;
+    void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
@@ -488,6 +482,15 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+/**
+ * @brief This variable is set to pdTRUE when the scheduler is started.
+ */
+    PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
+
+#endif
+
 /**
  * @brief Each task maintains its own interrupt status in the critical nesting
  * variable.
@@ -1134,15 +1137,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     void vSystemCallEnter( uint32_t * pulTaskStack,
-                           uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
+                           uint32_t ulLR,
+                           uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */
     {
         extern TaskHandle_t pxCurrentTCB;
+        extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ];
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulSystemCallStack;
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
-
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __syscalls_flash_start__;
@@ -1154,17 +1158,27 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         #endif /* #if defined( __ARMCC_VERSION ) */
 
         ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
 
-        /* If the request did not come from the system call section, do nothing. */
+        /* Checks:
+         * 1. SVC is raised from the system call section (i.e. application is
+         *    not raising SVC directly).
+         * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as
+         *    it is non-NULL only during the execution of a system call (i.e.
+         *    between system call enter and exit).
+         * 3. System call is not for a kernel API disabled by the configuration
+         *    in FreeRTOSConfig.h.
+         * 4. We do not need to check that ucSystemCallNumber is within range
+         *    because the assembly SVC handler checks that before calling
+         *    this function.
+         */
         if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) &&
+            ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) &&
+            ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) )
         {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
             pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
 
-            /* This is not NULL only for the duration of the system call. */
-            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
-
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
@@ -1198,9 +1212,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 pulSystemCallStack[ i ] = pulTaskStack[ i ];
             }
 
-            /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
-             * restore it when we exit from the system call. */
+            /* Store the value of the Link Register before the SVC was raised.
+             * It contains the address of the caller of the System Call entry
+             * point (i.e. the caller of the MPU_<API>). We need to restore it
+             * when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            /* Store the value of the PSPLIM register before the SVC was raised.
+             * We need to restore it when we exit from the system call. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
             {
                 __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
@@ -1215,6 +1233,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             }
             #endif
 
+            /* Start executing the system call upon returning from this handler. */
+            pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
+            /* Raise a request to exit from the system call upon finishing the
+             * system call. */
+            pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit;
+
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
             pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
@@ -1251,127 +1275,9 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    void vSystemCallEnter_1( uint32_t * pulTaskStack,
-                             uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
+    void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */
     {
-        extern TaskHandle_t pxCurrentTCB;
-        xMPU_SETTINGS * pxMpuSettings;
-        uint32_t * pulSystemCallStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-
-        #if defined( __ARMCC_VERSION )
-
-            /* Declaration when these variable are defined in code instead of being
-             * exported from linker scripts. */
-            extern uint32_t * __syscalls_flash_start__;
-            extern uint32_t * __syscalls_flash_end__;
-        #else
-            /* Declaration when these variable are exported from linker scripts. */
-            extern uint32_t __syscalls_flash_start__[];
-            extern uint32_t __syscalls_flash_end__[];
-        #endif /* #if defined( __ARMCC_VERSION ) */
-
-        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-        /* If the request did not come from the system call section, do nothing. */
-        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
-        {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
-
-            /* This is not NULL only for the duration of the system call. */
-            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
-
-            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-            {
-                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
-                {
-                    /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
-                    __asm volatile (
-                        " vpush {s0}         \n" /* Trigger lazy stacking. */
-                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                        ::: "memory"
-                        );
-                }
-                else
-                {
-                    /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
-                }
-            }
-            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
-            {
-                ulStackFrameSize = 8;
-            }
-            #endif /* configENABLE_FPU || configENABLE_MVE */
-
-            /* Make space on the system call stack for the stack frame and
-             * the parameter passed on the stack. We only need to copy one
-             * parameter but we still reserve 2 spaces to keep the stack
-             * double word aligned. */
-            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
-
-            /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
-            {
-                pulSystemCallStack[ i ] = pulTaskStack[ i ];
-            }
-
-            /* Copy the parameter which is passed the stack. */
-            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-            {
-                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
-
-                /* Record if the hardware used padding to force the stack pointer
-                 * to be double word aligned. */
-                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-            }
-            else
-            {
-                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
-
-                /* Record if the hardware used padding to force the stack pointer
-                 * to be double word aligned. */
-                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-            }
-
-            /* Store the value of the LR and PSPLIM registers before the SVC was raised.
-             * We need to restore it when we exit from the system call. */
-            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            #if ( portUSE_PSPLIM_REGISTER == 1 )
-            {
-                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-            }
-            #endif
-
-            /* Use the pulSystemCallStack in thread mode. */
-            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            #if ( portUSE_PSPLIM_REGISTER == 1 )
-            {
-                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-            }
-            #endif
-
-            /* Remember the location where we should copy the stack frame when we exit from
-             * the system call. */
-            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-            /* We ensure in pxPortInitialiseStack that the system call stack is
-             * double word aligned and therefore, there is no need of padding.
-             * Clear the bit[9] of stacked xPSR. */
-            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-            /* Raise the privilege for the duration of the system call. */
-            __asm volatile (
-                " mrs r0, control     \n" /* Obtain current control value. */
-                " movs r1, #1         \n" /* r1 = 1. */
-                " bics r0, r1         \n" /* Clear nPRIV bit. */
-                " msr control, r0     \n" /* Write back new control value. */
-                ::: "r0", "r1", "memory"
-                );
-        }
+        __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" );
     }
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@@ -1388,24 +1294,32 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
-
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
-            extern uint32_t * __syscalls_flash_start__;
-            extern uint32_t * __syscalls_flash_end__;
+            extern uint32_t * __privileged_functions_start__;
+            extern uint32_t * __privileged_functions_end__;
         #else
             /* Declaration when these variable are exported from linker scripts. */
-            extern uint32_t __syscalls_flash_start__[];
-            extern uint32_t __syscalls_flash_end__[];
+            extern uint32_t __privileged_functions_start__[];
+            extern uint32_t __privileged_functions_end__[];
         #endif /* #if defined( __ARMCC_VERSION ) */
 
         ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
+        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
 
-        /* If the request did not come from the system call section, do nothing. */
-        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+        /* Checks:
+         * 1. SVC is raised from the privileged code (i.e. application is not
+         *    raising SVC directly). This SVC is only raised from
+         *    vRequestSystemCallExit which is in the privileged code section.
+         * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL -
+         *    this means that we previously entered a system call and the
+         *    application is not attempting to exit without entering a system
+         *    call.
+         */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) &&
+            ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) )
         {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
             pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
 
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
@@ -1444,9 +1358,14 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Use the pulTaskStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
 
-            /* Restore the LR and PSPLIM to what they were at the time of
-             * system call entry. */
+            /* Return to the caller of the System Call entry point (i.e. the
+             * caller of the MPU_<API>). */
+            pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+            /* Ensure that LR has a valid value.*/
             pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+
+            /* Restore the PSPLIM register to what it was at the time of
+             * system call entry. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
             {
                 __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
@@ -1780,6 +1699,12 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     /* Initialize the critical nesting count ready for the first task. */
     ulCriticalNesting = 0;
 
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+    {
+        xSchedulerRunning = pdTRUE;
+    }
+    #endif
+
     /* Start the first task. */
     vStartFirstTask();
 
@@ -2062,7 +1987,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
 
     void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
                                          int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
@@ -2078,10 +2003,10 @@ BaseType_t xPortIsInsideInterrupt( void )
         xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit );
     }
 
-#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
 
     void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
                                           int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
@@ -2097,10 +2022,10 @@ BaseType_t xPortIsInsideInterrupt( void )
         xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit );
     }
 
-#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
 
@@ -2108,21 +2033,34 @@ BaseType_t xPortIsInsideInterrupt( void )
         {
             uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
             BaseType_t xAccessGranted = pdFALSE;
-            const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+            const xMPU_SETTINGS * xTaskMpuSettings;
 
-            ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
-            ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
-
-            if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+            if( xSchedulerRunning == pdFALSE )
             {
+                /* Grant access to all the kernel objects before the scheduler
+                 * is started. It is necessary because there is no task running
+                 * yet and therefore, we cannot use the permissions of any
+                 * task. */
                 xAccessGranted = pdTRUE;
             }
             else
             {
-                if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+                ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+                ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+                if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
                 {
                     xAccessGranted = pdTRUE;
                 }
+                else
+                {
+                    if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                    {
+                        xAccessGranted = pdTRUE;
+                    }
+                }
             }
 
             return xAccessGranted;
@@ -2141,5 +2079,5 @@ BaseType_t xPortIsInsideInterrupt( void )
 
     #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
 
-#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s b/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s
index ec5202527..7cf467d22 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s
@@ -32,6 +32,9 @@ the code is included in C files but excluded by the preprocessor in assembly
 files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
 #include "FreeRTOSConfig.h"
 
+/* System call numbers includes. */
+#include "mpu_syscall_numbers.h"
+
 #ifndef configUSE_MPU_WRAPPERS_V1
     #define configUSE_MPU_WRAPPERS_V1 0
 #endif
@@ -41,7 +44,6 @@ files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler.
     EXTERN vPortSVCHandler_C
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
     EXTERN vSystemCallEnter
-    EXTERN vSystemCallEnter_1
     EXTERN vSystemCallExit
 #endif
 
@@ -191,7 +193,7 @@ vStartFirstTask:
     cpsie f
     dsb
     isb
-    svc 2                                   /* System call to start the first task. portSVC_START_SCHEDULER = 2. */
+    svc 102                                 /* System call to start the first task. portSVC_START_SCHEDULER = 102. */
 /*-----------------------------------------------------------*/
 
 ulSetInterruptMask:
@@ -371,11 +373,9 @@ SVC_Handler:
 
     ldr r1, [r0, #24]
     ldrb r2, [r1, #-2]
-    cmp r2, #4          /* portSVC_SYSTEM_CALL_ENTER. */
-    beq syscall_enter
-    cmp r2, #5          /* portSVC_SYSTEM_CALL_ENTER_1. */
-    beq syscall_enter_1
-    cmp r2, #6          /* portSVC_SYSTEM_CALL_EXIT. */
+    cmp r2, #NUM_SYSTEM_CALLS
+    blt syscall_enter
+    cmp r2, #104            /* portSVC_SYSTEM_CALL_EXIT. */
     beq syscall_exit
     b vPortSVCHandler_C
 
@@ -383,10 +383,6 @@ SVC_Handler:
         mov r1, lr
         b vSystemCallEnter
 
-    syscall_enter_1:
-        mov r1, lr
-        b vSystemCallEnter_1
-
     syscall_exit:
         mov r1, lr
         b vSystemCallExit
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h
index 60ef37380..672b0dbdc 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h
@@ -322,14 +322,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 /**
  * @brief SVC numbers.
  */
-#define portSVC_ALLOCATE_SECURE_CONTEXT    0
-#define portSVC_FREE_SECURE_CONTEXT        1
-#define portSVC_START_SCHEDULER            2
-#define portSVC_RAISE_PRIVILEGE            3
-#define portSVC_SYSTEM_CALL_ENTER          4   /* System calls with upto 4 parameters. */
-#define portSVC_SYSTEM_CALL_ENTER_1        5   /* System calls with 5 parameters. */
-#define portSVC_SYSTEM_CALL_EXIT           6
-#define portSVC_YIELD                      7
+#define portSVC_ALLOCATE_SECURE_CONTEXT    100
+#define portSVC_FREE_SECURE_CONTEXT        101
+#define portSVC_START_SCHEDULER            102
+#define portSVC_RAISE_PRIVILEGE            103
+#define portSVC_SYSTEM_CALL_EXIT           104
+#define portSVC_YIELD                      105
 /*-----------------------------------------------------------*/
 
 /**
diff --git a/portable/IAR/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.S
index 1005dad33..80d5a1c63 100644
--- a/portable/IAR/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.S
+++ b/portable/IAR/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.S
@@ -32,15 +32,12 @@
 /*-----------------------------------------------------------*/
 
 #include "FreeRTOSConfig.h"
+#include "mpu_syscall_numbers.h"
 
 #ifndef configUSE_MPU_WRAPPERS_V1
     #define configUSE_MPU_WRAPPERS_V1 0
 #endif
 
-/* These must be in sync with portmacro.h. */
-#define portSVC_SYSTEM_CALL_ENTER   4 /* System calls with upto 4 parameters. */
-#define portSVC_SYSTEM_CALL_ENTER_1 5 /* System calls with 5 parameters. */
-#define portSVC_SYSTEM_CALL_EXIT    6
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
@@ -56,10 +53,7 @@ MPU_xTaskDelayUntil:
         b MPU_xTaskDelayUntilImpl
     MPU_xTaskDelayUntil_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskDelayUntilImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskDelayUntil
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskAbortDelay
@@ -73,10 +67,7 @@ MPU_xTaskAbortDelay:
         b MPU_xTaskAbortDelayImpl
     MPU_xTaskAbortDelay_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskAbortDelayImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskAbortDelay
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskDelay
@@ -90,10 +81,7 @@ MPU_vTaskDelay:
         b MPU_vTaskDelayImpl
     MPU_vTaskDelay_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskDelayImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskDelay
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskPriorityGet
@@ -107,10 +95,7 @@ MPU_uxTaskPriorityGet:
         b MPU_uxTaskPriorityGetImpl
     MPU_uxTaskPriorityGet_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskPriorityGetImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskPriorityGet
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_eTaskGetState
@@ -124,10 +109,7 @@ MPU_eTaskGetState:
         b MPU_eTaskGetStateImpl
     MPU_eTaskGetState_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_eTaskGetStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_eTaskGetState
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskGetInfo
@@ -141,10 +123,7 @@ MPU_vTaskGetInfo:
         b MPU_vTaskGetInfoImpl
     MPU_vTaskGetInfo_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskGetInfoImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskGetInfo
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetIdleTaskHandle
@@ -158,10 +137,7 @@ MPU_xTaskGetIdleTaskHandle:
         b MPU_xTaskGetIdleTaskHandleImpl
     MPU_xTaskGetIdleTaskHandle_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetIdleTaskHandleImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetIdleTaskHandle
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskSuspend
@@ -175,10 +151,7 @@ MPU_vTaskSuspend:
         b MPU_vTaskSuspendImpl
     MPU_vTaskSuspend_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSuspendImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskSuspend
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskResume
@@ -192,10 +165,7 @@ MPU_vTaskResume:
         b MPU_vTaskResumeImpl
     MPU_vTaskResume_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskResumeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskResume
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetTickCount
@@ -209,10 +179,7 @@ MPU_xTaskGetTickCount:
         b MPU_xTaskGetTickCountImpl
     MPU_xTaskGetTickCount_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetTickCountImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetTickCount
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskGetNumberOfTasks
@@ -226,10 +193,7 @@ MPU_uxTaskGetNumberOfTasks:
         b MPU_uxTaskGetNumberOfTasksImpl
     MPU_uxTaskGetNumberOfTasks_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetNumberOfTasksImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskGetNumberOfTasks
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGetRunTimeCounter
@@ -243,10 +207,7 @@ MPU_ulTaskGetRunTimeCounter:
         b MPU_ulTaskGetRunTimeCounterImpl
     MPU_ulTaskGetRunTimeCounter_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetRunTimeCounterImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGetRunTimeCounter
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGetRunTimePercent
@@ -260,10 +221,7 @@ MPU_ulTaskGetRunTimePercent:
         b MPU_ulTaskGetRunTimePercentImpl
     MPU_ulTaskGetRunTimePercent_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetRunTimePercentImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGetRunTimePercent
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGetIdleRunTimePercent
@@ -277,10 +235,7 @@ MPU_ulTaskGetIdleRunTimePercent:
         b MPU_ulTaskGetIdleRunTimePercentImpl
     MPU_ulTaskGetIdleRunTimePercent_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetIdleRunTimePercentImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGetIdleRunTimeCounter
@@ -294,10 +249,7 @@ MPU_ulTaskGetIdleRunTimeCounter:
         b MPU_ulTaskGetIdleRunTimeCounterImpl
     MPU_ulTaskGetIdleRunTimeCounter_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetIdleRunTimeCounterImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskSetApplicationTaskTag
@@ -311,10 +263,7 @@ MPU_vTaskSetApplicationTaskTag:
         b MPU_vTaskSetApplicationTaskTagImpl
     MPU_vTaskSetApplicationTaskTag_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSetApplicationTaskTagImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskSetApplicationTaskTag
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetApplicationTaskTag
@@ -328,10 +277,7 @@ MPU_xTaskGetApplicationTaskTag:
         b MPU_xTaskGetApplicationTaskTagImpl
     MPU_xTaskGetApplicationTaskTag_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetApplicationTaskTagImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetApplicationTaskTag
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskSetThreadLocalStoragePointer
@@ -345,10 +291,7 @@ MPU_vTaskSetThreadLocalStoragePointer:
         b MPU_vTaskSetThreadLocalStoragePointerImpl
     MPU_vTaskSetThreadLocalStoragePointer_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSetThreadLocalStoragePointerImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pvTaskGetThreadLocalStoragePointer
@@ -362,10 +305,7 @@ MPU_pvTaskGetThreadLocalStoragePointer:
         b MPU_pvTaskGetThreadLocalStoragePointerImpl
     MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pvTaskGetThreadLocalStoragePointerImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskGetSystemState
@@ -379,10 +319,7 @@ MPU_uxTaskGetSystemState:
         b MPU_uxTaskGetSystemStateImpl
     MPU_uxTaskGetSystemState_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetSystemStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskGetSystemState
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskGetStackHighWaterMark
@@ -396,10 +333,7 @@ MPU_uxTaskGetStackHighWaterMark:
         b MPU_uxTaskGetStackHighWaterMarkImpl
     MPU_uxTaskGetStackHighWaterMark_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetStackHighWaterMarkImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskGetStackHighWaterMark2
@@ -413,10 +347,7 @@ MPU_uxTaskGetStackHighWaterMark2:
         b MPU_uxTaskGetStackHighWaterMark2Impl
     MPU_uxTaskGetStackHighWaterMark2_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetStackHighWaterMark2Impl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetCurrentTaskHandle
@@ -430,10 +361,7 @@ MPU_xTaskGetCurrentTaskHandle:
         b MPU_xTaskGetCurrentTaskHandleImpl
     MPU_xTaskGetCurrentTaskHandle_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetCurrentTaskHandleImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetSchedulerState
@@ -447,10 +375,7 @@ MPU_xTaskGetSchedulerState:
         b MPU_xTaskGetSchedulerStateImpl
     MPU_xTaskGetSchedulerState_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetSchedulerStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetSchedulerState
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskSetTimeOutState
@@ -464,10 +389,7 @@ MPU_vTaskSetTimeOutState:
         b MPU_vTaskSetTimeOutStateImpl
     MPU_vTaskSetTimeOutState_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSetTimeOutStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskSetTimeOutState
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskCheckForTimeOut
@@ -481,14 +403,11 @@ MPU_xTaskCheckForTimeOut:
         b MPU_xTaskCheckForTimeOutImpl
     MPU_xTaskCheckForTimeOut_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskCheckForTimeOutImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskCheckForTimeOut
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xTaskGenericNotify
-MPU_xTaskGenericNotify:
+    PUBLIC MPU_xTaskGenericNotifyEntry
+MPU_xTaskGenericNotifyEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
@@ -498,14 +417,11 @@ MPU_xTaskGenericNotify:
         b MPU_xTaskGenericNotifyImpl
     MPU_xTaskGenericNotify_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTaskGenericNotifyImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGenericNotify
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xTaskGenericNotifyWait
-MPU_xTaskGenericNotifyWait:
+    PUBLIC MPU_xTaskGenericNotifyWaitEntry
+MPU_xTaskGenericNotifyWaitEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
@@ -515,10 +431,7 @@ MPU_xTaskGenericNotifyWait:
         b MPU_xTaskGenericNotifyWaitImpl
     MPU_xTaskGenericNotifyWait_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTaskGenericNotifyWaitImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGenericNotifyWait
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGenericNotifyTake
@@ -532,10 +445,7 @@ MPU_ulTaskGenericNotifyTake:
         b MPU_ulTaskGenericNotifyTakeImpl
     MPU_ulTaskGenericNotifyTake_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGenericNotifyTakeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGenericNotifyTake
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGenericNotifyStateClear
@@ -549,10 +459,7 @@ MPU_xTaskGenericNotifyStateClear:
         b MPU_xTaskGenericNotifyStateClearImpl
     MPU_xTaskGenericNotifyStateClear_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGenericNotifyStateClearImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGenericNotifyStateClear
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGenericNotifyValueClear
@@ -566,10 +473,7 @@ MPU_ulTaskGenericNotifyValueClear:
         b MPU_ulTaskGenericNotifyValueClearImpl
     MPU_ulTaskGenericNotifyValueClear_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGenericNotifyValueClearImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueGenericSend
@@ -583,10 +487,7 @@ MPU_xQueueGenericSend:
         b MPU_xQueueGenericSendImpl
     MPU_xQueueGenericSend_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueGenericSendImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueGenericSend
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxQueueMessagesWaiting
@@ -600,10 +501,7 @@ MPU_uxQueueMessagesWaiting:
         b MPU_uxQueueMessagesWaitingImpl
     MPU_uxQueueMessagesWaiting_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxQueueMessagesWaitingImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxQueueMessagesWaiting
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxQueueSpacesAvailable
@@ -617,10 +515,7 @@ MPU_uxQueueSpacesAvailable:
         b MPU_uxQueueSpacesAvailableImpl
     MPU_uxQueueSpacesAvailable_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxQueueSpacesAvailableImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxQueueSpacesAvailable
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueReceive
@@ -634,10 +529,7 @@ MPU_xQueueReceive:
         b MPU_xQueueReceiveImpl
     MPU_xQueueReceive_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueReceiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueReceive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueuePeek
@@ -651,10 +543,7 @@ MPU_xQueuePeek:
         b MPU_xQueuePeekImpl
     MPU_xQueuePeek_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueuePeekImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueuePeek
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueSemaphoreTake
@@ -668,10 +557,7 @@ MPU_xQueueSemaphoreTake:
         b MPU_xQueueSemaphoreTakeImpl
     MPU_xQueueSemaphoreTake_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueSemaphoreTakeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueSemaphoreTake
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueGetMutexHolder
@@ -685,10 +571,7 @@ MPU_xQueueGetMutexHolder:
         b MPU_xQueueGetMutexHolderImpl
     MPU_xQueueGetMutexHolder_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueGetMutexHolderImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueGetMutexHolder
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueTakeMutexRecursive
@@ -702,10 +585,7 @@ MPU_xQueueTakeMutexRecursive:
         b MPU_xQueueTakeMutexRecursiveImpl
     MPU_xQueueTakeMutexRecursive_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueTakeMutexRecursiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueTakeMutexRecursive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueGiveMutexRecursive
@@ -719,10 +599,7 @@ MPU_xQueueGiveMutexRecursive:
         b MPU_xQueueGiveMutexRecursiveImpl
     MPU_xQueueGiveMutexRecursive_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueGiveMutexRecursiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueGiveMutexRecursive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueSelectFromSet
@@ -736,10 +613,7 @@ MPU_xQueueSelectFromSet:
         b MPU_xQueueSelectFromSetImpl
     MPU_xQueueSelectFromSet_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueSelectFromSetImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueSelectFromSet
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueAddToSet
@@ -753,10 +627,7 @@ MPU_xQueueAddToSet:
         b MPU_xQueueAddToSetImpl
     MPU_xQueueAddToSet_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueAddToSetImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueAddToSet
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vQueueAddToRegistry
@@ -770,10 +641,7 @@ MPU_vQueueAddToRegistry:
         b MPU_vQueueAddToRegistryImpl
     MPU_vQueueAddToRegistry_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vQueueAddToRegistryImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vQueueAddToRegistry
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vQueueUnregisterQueue
@@ -787,10 +655,7 @@ MPU_vQueueUnregisterQueue:
         b MPU_vQueueUnregisterQueueImpl
     MPU_vQueueUnregisterQueue_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vQueueUnregisterQueueImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vQueueUnregisterQueue
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pcQueueGetName
@@ -804,10 +669,7 @@ MPU_pcQueueGetName:
         b MPU_pcQueueGetNameImpl
     MPU_pcQueueGetName_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pcQueueGetNameImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_pcQueueGetName
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pvTimerGetTimerID
@@ -821,10 +683,7 @@ MPU_pvTimerGetTimerID:
         b MPU_pvTimerGetTimerIDImpl
     MPU_pvTimerGetTimerID_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pvTimerGetTimerIDImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_pvTimerGetTimerID
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTimerSetTimerID
@@ -838,10 +697,7 @@ MPU_vTimerSetTimerID:
         b MPU_vTimerSetTimerIDImpl
     MPU_vTimerSetTimerID_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTimerSetTimerIDImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTimerSetTimerID
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerIsTimerActive
@@ -855,10 +711,7 @@ MPU_xTimerIsTimerActive:
         b MPU_xTimerIsTimerActiveImpl
     MPU_xTimerIsTimerActive_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerIsTimerActiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerIsTimerActive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerGetTimerDaemonTaskHandle
@@ -872,14 +725,11 @@ MPU_xTimerGetTimerDaemonTaskHandle:
         b MPU_xTimerGetTimerDaemonTaskHandleImpl
     MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetTimerDaemonTaskHandleImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xTimerGenericCommandFromTask
-MPU_xTimerGenericCommandFromTask:
+    PUBLIC MPU_xTimerGenericCommandFromTaskEntry
+MPU_xTimerGenericCommandFromTaskEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
@@ -889,10 +739,7 @@ MPU_xTimerGenericCommandFromTask:
         b MPU_xTimerGenericCommandFromTaskImpl
     MPU_xTimerGenericCommandFromTask_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTimerGenericCommandFromTaskImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGenericCommandFromTask
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pcTimerGetName
@@ -906,10 +753,7 @@ MPU_pcTimerGetName:
         b MPU_pcTimerGetNameImpl
     MPU_pcTimerGetName_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pcTimerGetNameImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_pcTimerGetName
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTimerSetReloadMode
@@ -923,10 +767,7 @@ MPU_vTimerSetReloadMode:
         b MPU_vTimerSetReloadModeImpl
     MPU_vTimerSetReloadMode_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTimerSetReloadModeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTimerSetReloadMode
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerGetReloadMode
@@ -940,10 +781,7 @@ MPU_xTimerGetReloadMode:
         b MPU_xTimerGetReloadModeImpl
     MPU_xTimerGetReloadMode_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetReloadModeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGetReloadMode
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTimerGetReloadMode
@@ -957,10 +795,7 @@ MPU_uxTimerGetReloadMode:
         b MPU_uxTimerGetReloadModeImpl
     MPU_uxTimerGetReloadMode_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTimerGetReloadModeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTimerGetReloadMode
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerGetPeriod
@@ -974,10 +809,7 @@ MPU_xTimerGetPeriod:
         b MPU_xTimerGetPeriodImpl
     MPU_xTimerGetPeriod_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetPeriodImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGetPeriod
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerGetExpiryTime
@@ -991,14 +823,11 @@ MPU_xTimerGetExpiryTime:
         b MPU_xTimerGetExpiryTimeImpl
     MPU_xTimerGetExpiryTime_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetExpiryTimeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGetExpiryTime
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xEventGroupWaitBits
-MPU_xEventGroupWaitBits:
+    PUBLIC MPU_xEventGroupWaitBitsEntry
+MPU_xEventGroupWaitBitsEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
@@ -1008,10 +837,7 @@ MPU_xEventGroupWaitBits:
         b MPU_xEventGroupWaitBitsImpl
     MPU_xEventGroupWaitBits_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xEventGroupWaitBitsImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xEventGroupWaitBits
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xEventGroupClearBits
@@ -1025,10 +851,7 @@ MPU_xEventGroupClearBits:
         b MPU_xEventGroupClearBitsImpl
     MPU_xEventGroupClearBits_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xEventGroupClearBitsImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xEventGroupClearBits
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xEventGroupSetBits
@@ -1042,10 +865,7 @@ MPU_xEventGroupSetBits:
         b MPU_xEventGroupSetBitsImpl
     MPU_xEventGroupSetBits_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xEventGroupSetBitsImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xEventGroupSetBits
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xEventGroupSync
@@ -1059,10 +879,7 @@ MPU_xEventGroupSync:
         b MPU_xEventGroupSyncImpl
     MPU_xEventGroupSync_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xEventGroupSyncImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xEventGroupSync
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxEventGroupGetNumber
@@ -1076,10 +893,7 @@ MPU_uxEventGroupGetNumber:
         b MPU_uxEventGroupGetNumberImpl
     MPU_uxEventGroupGetNumber_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxEventGroupGetNumberImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxEventGroupGetNumber
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vEventGroupSetNumber
@@ -1093,10 +907,7 @@ MPU_vEventGroupSetNumber:
         b MPU_vEventGroupSetNumberImpl
     MPU_vEventGroupSetNumber_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vEventGroupSetNumberImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vEventGroupSetNumber
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferSend
@@ -1110,10 +921,7 @@ MPU_xStreamBufferSend:
         b MPU_xStreamBufferSendImpl
     MPU_xStreamBufferSend_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferSendImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferSend
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferReceive
@@ -1127,10 +935,7 @@ MPU_xStreamBufferReceive:
         b MPU_xStreamBufferReceiveImpl
     MPU_xStreamBufferReceive_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferReceiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferReceive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferIsFull
@@ -1144,10 +949,7 @@ MPU_xStreamBufferIsFull:
         b MPU_xStreamBufferIsFullImpl
     MPU_xStreamBufferIsFull_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferIsFullImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferIsFull
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferIsEmpty
@@ -1161,10 +963,7 @@ MPU_xStreamBufferIsEmpty:
         b MPU_xStreamBufferIsEmptyImpl
     MPU_xStreamBufferIsEmpty_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferIsEmptyImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferIsEmpty
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferSpacesAvailable
@@ -1178,10 +977,7 @@ MPU_xStreamBufferSpacesAvailable:
         b MPU_xStreamBufferSpacesAvailableImpl
     MPU_xStreamBufferSpacesAvailable_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferSpacesAvailableImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferSpacesAvailable
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferBytesAvailable
@@ -1195,10 +991,7 @@ MPU_xStreamBufferBytesAvailable:
         b MPU_xStreamBufferBytesAvailableImpl
     MPU_xStreamBufferBytesAvailable_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferBytesAvailableImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferBytesAvailable
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferSetTriggerLevel
@@ -1212,10 +1005,7 @@ MPU_xStreamBufferSetTriggerLevel:
         b MPU_xStreamBufferSetTriggerLevelImpl
     MPU_xStreamBufferSetTriggerLevel_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferSetTriggerLevelImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferNextMessageLengthBytes
@@ -1229,10 +1019,7 @@ MPU_xStreamBufferNextMessageLengthBytes:
         b MPU_xStreamBufferNextMessageLengthBytesImpl
     MPU_xStreamBufferNextMessageLengthBytes_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferNextMessageLengthBytesImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes
 /*-----------------------------------------------------------*/
 
 /* Default weak implementations in case one is not available from
diff --git a/portable/IAR/ARM_CM35P/non_secure/port.c b/portable/IAR/ARM_CM35P/non_secure/port.c
index 52d68d3ea..6a3877894 100644
--- a/portable/IAR/ARM_CM35P/non_secure/port.c
+++ b/portable/IAR/ARM_CM35P/non_secure/port.c
@@ -35,8 +35,9 @@
 #include "FreeRTOS.h"
 #include "task.h"
 
-/* MPU wrappers includes. */
+/* MPU includes. */
 #include "mpu_wrappers.h"
+#include "mpu_syscall_numbers.h"
 
 /* Portasm includes. */
 #include "portasm.h"
@@ -436,29 +437,22 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
  * @brief Sets up the system call stack so that upon returning from
  * SVC, the system call stack is used.
  *
- * It is used for the system calls with up to 4 parameters.
- *
  * @param pulTaskStack The current SP when the SVC was raised.
  * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ * @param ucSystemCallNumber The system call number of the system call.
  */
     void vSystemCallEnter( uint32_t * pulTaskStack,
-                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
+                           uint32_t ulLR,
+                           uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
- * @brief Sets up the system call stack so that upon returning from
- * SVC, the system call stack is used.
- *
- * It is used for the system calls with 5 parameters.
- *
- * @param pulTaskStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ * @brief Raise SVC for exiting from a system call.
  */
-    void vSystemCallEnter_1( uint32_t * pulTaskStack,
-                             uint32_t ulLR ) PRIVILEGED_FUNCTION;
+    void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
@@ -488,6 +482,15 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+/**
+ * @brief This variable is set to pdTRUE when the scheduler is started.
+ */
+    PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
+
+#endif
+
 /**
  * @brief Each task maintains its own interrupt status in the critical nesting
  * variable.
@@ -1134,15 +1137,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     void vSystemCallEnter( uint32_t * pulTaskStack,
-                           uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
+                           uint32_t ulLR,
+                           uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */
     {
         extern TaskHandle_t pxCurrentTCB;
+        extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ];
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulSystemCallStack;
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
-
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __syscalls_flash_start__;
@@ -1154,17 +1158,27 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         #endif /* #if defined( __ARMCC_VERSION ) */
 
         ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
 
-        /* If the request did not come from the system call section, do nothing. */
+        /* Checks:
+         * 1. SVC is raised from the system call section (i.e. application is
+         *    not raising SVC directly).
+         * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as
+         *    it is non-NULL only during the execution of a system call (i.e.
+         *    between system call enter and exit).
+         * 3. System call is not for a kernel API disabled by the configuration
+         *    in FreeRTOSConfig.h.
+         * 4. We do not need to check that ucSystemCallNumber is within range
+         *    because the assembly SVC handler checks that before calling
+         *    this function.
+         */
         if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) &&
+            ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) &&
+            ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) )
         {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
             pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
 
-            /* This is not NULL only for the duration of the system call. */
-            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
-
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
@@ -1198,9 +1212,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 pulSystemCallStack[ i ] = pulTaskStack[ i ];
             }
 
-            /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
-             * restore it when we exit from the system call. */
+            /* Store the value of the Link Register before the SVC was raised.
+             * It contains the address of the caller of the System Call entry
+             * point (i.e. the caller of the MPU_<API>). We need to restore it
+             * when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            /* Store the value of the PSPLIM register before the SVC was raised.
+             * We need to restore it when we exit from the system call. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
             {
                 __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
@@ -1215,6 +1233,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             }
             #endif
 
+            /* Start executing the system call upon returning from this handler. */
+            pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
+            /* Raise a request to exit from the system call upon finishing the
+             * system call. */
+            pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit;
+
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
             pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
@@ -1251,127 +1275,9 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    void vSystemCallEnter_1( uint32_t * pulTaskStack,
-                             uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
+    void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */
     {
-        extern TaskHandle_t pxCurrentTCB;
-        xMPU_SETTINGS * pxMpuSettings;
-        uint32_t * pulSystemCallStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-
-        #if defined( __ARMCC_VERSION )
-
-            /* Declaration when these variable are defined in code instead of being
-             * exported from linker scripts. */
-            extern uint32_t * __syscalls_flash_start__;
-            extern uint32_t * __syscalls_flash_end__;
-        #else
-            /* Declaration when these variable are exported from linker scripts. */
-            extern uint32_t __syscalls_flash_start__[];
-            extern uint32_t __syscalls_flash_end__[];
-        #endif /* #if defined( __ARMCC_VERSION ) */
-
-        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-        /* If the request did not come from the system call section, do nothing. */
-        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
-        {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
-
-            /* This is not NULL only for the duration of the system call. */
-            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
-
-            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-            {
-                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
-                {
-                    /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
-                    __asm volatile (
-                        " vpush {s0}         \n" /* Trigger lazy stacking. */
-                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                        ::: "memory"
-                        );
-                }
-                else
-                {
-                    /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
-                }
-            }
-            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
-            {
-                ulStackFrameSize = 8;
-            }
-            #endif /* configENABLE_FPU || configENABLE_MVE */
-
-            /* Make space on the system call stack for the stack frame and
-             * the parameter passed on the stack. We only need to copy one
-             * parameter but we still reserve 2 spaces to keep the stack
-             * double word aligned. */
-            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
-
-            /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
-            {
-                pulSystemCallStack[ i ] = pulTaskStack[ i ];
-            }
-
-            /* Copy the parameter which is passed the stack. */
-            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-            {
-                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
-
-                /* Record if the hardware used padding to force the stack pointer
-                 * to be double word aligned. */
-                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-            }
-            else
-            {
-                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
-
-                /* Record if the hardware used padding to force the stack pointer
-                 * to be double word aligned. */
-                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-            }
-
-            /* Store the value of the LR and PSPLIM registers before the SVC was raised.
-             * We need to restore it when we exit from the system call. */
-            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            #if ( portUSE_PSPLIM_REGISTER == 1 )
-            {
-                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-            }
-            #endif
-
-            /* Use the pulSystemCallStack in thread mode. */
-            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            #if ( portUSE_PSPLIM_REGISTER == 1 )
-            {
-                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-            }
-            #endif
-
-            /* Remember the location where we should copy the stack frame when we exit from
-             * the system call. */
-            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-            /* We ensure in pxPortInitialiseStack that the system call stack is
-             * double word aligned and therefore, there is no need of padding.
-             * Clear the bit[9] of stacked xPSR. */
-            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-            /* Raise the privilege for the duration of the system call. */
-            __asm volatile (
-                " mrs r0, control     \n" /* Obtain current control value. */
-                " movs r1, #1         \n" /* r1 = 1. */
-                " bics r0, r1         \n" /* Clear nPRIV bit. */
-                " msr control, r0     \n" /* Write back new control value. */
-                ::: "r0", "r1", "memory"
-                );
-        }
+        __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" );
     }
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@@ -1388,24 +1294,32 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
-
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
-            extern uint32_t * __syscalls_flash_start__;
-            extern uint32_t * __syscalls_flash_end__;
+            extern uint32_t * __privileged_functions_start__;
+            extern uint32_t * __privileged_functions_end__;
         #else
             /* Declaration when these variable are exported from linker scripts. */
-            extern uint32_t __syscalls_flash_start__[];
-            extern uint32_t __syscalls_flash_end__[];
+            extern uint32_t __privileged_functions_start__[];
+            extern uint32_t __privileged_functions_end__[];
         #endif /* #if defined( __ARMCC_VERSION ) */
 
         ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
+        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
 
-        /* If the request did not come from the system call section, do nothing. */
-        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+        /* Checks:
+         * 1. SVC is raised from the privileged code (i.e. application is not
+         *    raising SVC directly). This SVC is only raised from
+         *    vRequestSystemCallExit which is in the privileged code section.
+         * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL -
+         *    this means that we previously entered a system call and the
+         *    application is not attempting to exit without entering a system
+         *    call.
+         */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) &&
+            ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) )
         {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
             pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
 
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
@@ -1444,9 +1358,14 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Use the pulTaskStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
 
-            /* Restore the LR and PSPLIM to what they were at the time of
-             * system call entry. */
+            /* Return to the caller of the System Call entry point (i.e. the
+             * caller of the MPU_<API>). */
+            pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+            /* Ensure that LR has a valid value.*/
             pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+
+            /* Restore the PSPLIM register to what it was at the time of
+             * system call entry. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
             {
                 __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
@@ -1780,6 +1699,12 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     /* Initialize the critical nesting count ready for the first task. */
     ulCriticalNesting = 0;
 
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+    {
+        xSchedulerRunning = pdTRUE;
+    }
+    #endif
+
     /* Start the first task. */
     vStartFirstTask();
 
@@ -2062,7 +1987,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
 
     void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
                                          int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
@@ -2078,10 +2003,10 @@ BaseType_t xPortIsInsideInterrupt( void )
         xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit );
     }
 
-#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
 
     void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
                                           int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
@@ -2097,10 +2022,10 @@ BaseType_t xPortIsInsideInterrupt( void )
         xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit );
     }
 
-#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
 
@@ -2108,21 +2033,34 @@ BaseType_t xPortIsInsideInterrupt( void )
         {
             uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
             BaseType_t xAccessGranted = pdFALSE;
-            const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+            const xMPU_SETTINGS * xTaskMpuSettings;
 
-            ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
-            ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
-
-            if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+            if( xSchedulerRunning == pdFALSE )
             {
+                /* Grant access to all the kernel objects before the scheduler
+                 * is started. It is necessary because there is no task running
+                 * yet and therefore, we cannot use the permissions of any
+                 * task. */
                 xAccessGranted = pdTRUE;
             }
             else
             {
-                if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+                ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+                ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+                if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
                 {
                     xAccessGranted = pdTRUE;
                 }
+                else
+                {
+                    if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                    {
+                        xAccessGranted = pdTRUE;
+                    }
+                }
             }
 
             return xAccessGranted;
@@ -2141,5 +2079,5 @@ BaseType_t xPortIsInsideInterrupt( void )
 
     #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
 
-#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM35P/non_secure/portasm.s b/portable/IAR/ARM_CM35P/non_secure/portasm.s
index 15e74ffc1..d8f1b1d9a 100644
--- a/portable/IAR/ARM_CM35P/non_secure/portasm.s
+++ b/portable/IAR/ARM_CM35P/non_secure/portasm.s
@@ -32,6 +32,9 @@ the code is included in C files but excluded by the preprocessor in assembly
 files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
 #include "FreeRTOSConfig.h"
 
+/* System call numbers includes. */
+#include "mpu_syscall_numbers.h"
+
 #ifndef configUSE_MPU_WRAPPERS_V1
     #define configUSE_MPU_WRAPPERS_V1 0
 #endif
@@ -44,7 +47,6 @@ files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler.
     EXTERN SecureContext_LoadContext
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
     EXTERN vSystemCallEnter
-    EXTERN vSystemCallEnter_1
     EXTERN vSystemCallExit
 #endif
 
@@ -86,7 +88,7 @@ vResetPrivilege:
 /*-----------------------------------------------------------*/
 
 vPortAllocateSecureContext:
-    svc 0                                   /* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 0. */
+    svc 100                                 /* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 100. */
     bx lr                                   /* Return. */
 /*-----------------------------------------------------------*/
 
@@ -205,7 +207,7 @@ vStartFirstTask:
     cpsie f
     dsb
     isb
-    svc 2                                   /* System call to start the first task. portSVC_START_SCHEDULER = 2. */
+    svc 102                                 /* System call to start the first task. portSVC_START_SCHEDULER = 102. */
 /*-----------------------------------------------------------*/
 
 ulSetInterruptMask:
@@ -455,11 +457,9 @@ SVC_Handler:
 
     ldr r1, [r0, #24]
     ldrb r2, [r1, #-2]
-    cmp r2, #4          /* portSVC_SYSTEM_CALL_ENTER. */
-    beq syscall_enter
-    cmp r2, #5          /* portSVC_SYSTEM_CALL_ENTER_1. */
-    beq syscall_enter_1
-    cmp r2, #6          /* portSVC_SYSTEM_CALL_EXIT. */
+    cmp r2, #NUM_SYSTEM_CALLS
+    blt syscall_enter
+    cmp r2, #104            /* portSVC_SYSTEM_CALL_EXIT. */
     beq syscall_exit
     b vPortSVCHandler_C
 
@@ -467,10 +467,6 @@ SVC_Handler:
         mov r1, lr
         b vSystemCallEnter
 
-    syscall_enter_1:
-        mov r1, lr
-        b vSystemCallEnter_1
-
     syscall_exit:
         mov r1, lr
         b vSystemCallExit
@@ -493,7 +489,7 @@ vPortFreeSecureContext:
     ldr r1, [r2]                            /* The first item on the stack is the task's xSecureContext. */
     cmp r1, #0                              /* Raise svc if task's xSecureContext is not NULL. */
     it ne
-    svcne 1                                 /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */
+    svcne 101                               /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 101. */
     bx lr                                   /* Return. */
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h
index 60ef37380..672b0dbdc 100644
--- a/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h
@@ -322,14 +322,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 /**
  * @brief SVC numbers.
  */
-#define portSVC_ALLOCATE_SECURE_CONTEXT    0
-#define portSVC_FREE_SECURE_CONTEXT        1
-#define portSVC_START_SCHEDULER            2
-#define portSVC_RAISE_PRIVILEGE            3
-#define portSVC_SYSTEM_CALL_ENTER          4   /* System calls with upto 4 parameters. */
-#define portSVC_SYSTEM_CALL_ENTER_1        5   /* System calls with 5 parameters. */
-#define portSVC_SYSTEM_CALL_EXIT           6
-#define portSVC_YIELD                      7
+#define portSVC_ALLOCATE_SECURE_CONTEXT    100
+#define portSVC_FREE_SECURE_CONTEXT        101
+#define portSVC_START_SCHEDULER            102
+#define portSVC_RAISE_PRIVILEGE            103
+#define portSVC_SYSTEM_CALL_EXIT           104
+#define portSVC_YIELD                      105
 /*-----------------------------------------------------------*/
 
 /**
diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.S
index 1005dad33..80d5a1c63 100644
--- a/portable/IAR/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.S
+++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.S
@@ -32,15 +32,12 @@
 /*-----------------------------------------------------------*/
 
 #include "FreeRTOSConfig.h"
+#include "mpu_syscall_numbers.h"
 
 #ifndef configUSE_MPU_WRAPPERS_V1
     #define configUSE_MPU_WRAPPERS_V1 0
 #endif
 
-/* These must be in sync with portmacro.h. */
-#define portSVC_SYSTEM_CALL_ENTER   4 /* System calls with upto 4 parameters. */
-#define portSVC_SYSTEM_CALL_ENTER_1 5 /* System calls with 5 parameters. */
-#define portSVC_SYSTEM_CALL_EXIT    6
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
@@ -56,10 +53,7 @@ MPU_xTaskDelayUntil:
         b MPU_xTaskDelayUntilImpl
     MPU_xTaskDelayUntil_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskDelayUntilImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskDelayUntil
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskAbortDelay
@@ -73,10 +67,7 @@ MPU_xTaskAbortDelay:
         b MPU_xTaskAbortDelayImpl
     MPU_xTaskAbortDelay_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskAbortDelayImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskAbortDelay
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskDelay
@@ -90,10 +81,7 @@ MPU_vTaskDelay:
         b MPU_vTaskDelayImpl
     MPU_vTaskDelay_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskDelayImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskDelay
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskPriorityGet
@@ -107,10 +95,7 @@ MPU_uxTaskPriorityGet:
         b MPU_uxTaskPriorityGetImpl
     MPU_uxTaskPriorityGet_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskPriorityGetImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskPriorityGet
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_eTaskGetState
@@ -124,10 +109,7 @@ MPU_eTaskGetState:
         b MPU_eTaskGetStateImpl
     MPU_eTaskGetState_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_eTaskGetStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_eTaskGetState
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskGetInfo
@@ -141,10 +123,7 @@ MPU_vTaskGetInfo:
         b MPU_vTaskGetInfoImpl
     MPU_vTaskGetInfo_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskGetInfoImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskGetInfo
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetIdleTaskHandle
@@ -158,10 +137,7 @@ MPU_xTaskGetIdleTaskHandle:
         b MPU_xTaskGetIdleTaskHandleImpl
     MPU_xTaskGetIdleTaskHandle_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetIdleTaskHandleImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetIdleTaskHandle
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskSuspend
@@ -175,10 +151,7 @@ MPU_vTaskSuspend:
         b MPU_vTaskSuspendImpl
     MPU_vTaskSuspend_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSuspendImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskSuspend
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskResume
@@ -192,10 +165,7 @@ MPU_vTaskResume:
         b MPU_vTaskResumeImpl
     MPU_vTaskResume_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskResumeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskResume
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetTickCount
@@ -209,10 +179,7 @@ MPU_xTaskGetTickCount:
         b MPU_xTaskGetTickCountImpl
     MPU_xTaskGetTickCount_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetTickCountImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetTickCount
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskGetNumberOfTasks
@@ -226,10 +193,7 @@ MPU_uxTaskGetNumberOfTasks:
         b MPU_uxTaskGetNumberOfTasksImpl
     MPU_uxTaskGetNumberOfTasks_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetNumberOfTasksImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskGetNumberOfTasks
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGetRunTimeCounter
@@ -243,10 +207,7 @@ MPU_ulTaskGetRunTimeCounter:
         b MPU_ulTaskGetRunTimeCounterImpl
     MPU_ulTaskGetRunTimeCounter_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetRunTimeCounterImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGetRunTimeCounter
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGetRunTimePercent
@@ -260,10 +221,7 @@ MPU_ulTaskGetRunTimePercent:
         b MPU_ulTaskGetRunTimePercentImpl
     MPU_ulTaskGetRunTimePercent_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetRunTimePercentImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGetRunTimePercent
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGetIdleRunTimePercent
@@ -277,10 +235,7 @@ MPU_ulTaskGetIdleRunTimePercent:
         b MPU_ulTaskGetIdleRunTimePercentImpl
     MPU_ulTaskGetIdleRunTimePercent_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetIdleRunTimePercentImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGetIdleRunTimeCounter
@@ -294,10 +249,7 @@ MPU_ulTaskGetIdleRunTimeCounter:
         b MPU_ulTaskGetIdleRunTimeCounterImpl
     MPU_ulTaskGetIdleRunTimeCounter_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetIdleRunTimeCounterImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskSetApplicationTaskTag
@@ -311,10 +263,7 @@ MPU_vTaskSetApplicationTaskTag:
         b MPU_vTaskSetApplicationTaskTagImpl
     MPU_vTaskSetApplicationTaskTag_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSetApplicationTaskTagImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskSetApplicationTaskTag
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetApplicationTaskTag
@@ -328,10 +277,7 @@ MPU_xTaskGetApplicationTaskTag:
         b MPU_xTaskGetApplicationTaskTagImpl
     MPU_xTaskGetApplicationTaskTag_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetApplicationTaskTagImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetApplicationTaskTag
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskSetThreadLocalStoragePointer
@@ -345,10 +291,7 @@ MPU_vTaskSetThreadLocalStoragePointer:
         b MPU_vTaskSetThreadLocalStoragePointerImpl
     MPU_vTaskSetThreadLocalStoragePointer_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSetThreadLocalStoragePointerImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pvTaskGetThreadLocalStoragePointer
@@ -362,10 +305,7 @@ MPU_pvTaskGetThreadLocalStoragePointer:
         b MPU_pvTaskGetThreadLocalStoragePointerImpl
     MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pvTaskGetThreadLocalStoragePointerImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskGetSystemState
@@ -379,10 +319,7 @@ MPU_uxTaskGetSystemState:
         b MPU_uxTaskGetSystemStateImpl
     MPU_uxTaskGetSystemState_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetSystemStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskGetSystemState
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskGetStackHighWaterMark
@@ -396,10 +333,7 @@ MPU_uxTaskGetStackHighWaterMark:
         b MPU_uxTaskGetStackHighWaterMarkImpl
     MPU_uxTaskGetStackHighWaterMark_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetStackHighWaterMarkImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskGetStackHighWaterMark2
@@ -413,10 +347,7 @@ MPU_uxTaskGetStackHighWaterMark2:
         b MPU_uxTaskGetStackHighWaterMark2Impl
     MPU_uxTaskGetStackHighWaterMark2_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetStackHighWaterMark2Impl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetCurrentTaskHandle
@@ -430,10 +361,7 @@ MPU_xTaskGetCurrentTaskHandle:
         b MPU_xTaskGetCurrentTaskHandleImpl
     MPU_xTaskGetCurrentTaskHandle_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetCurrentTaskHandleImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetSchedulerState
@@ -447,10 +375,7 @@ MPU_xTaskGetSchedulerState:
         b MPU_xTaskGetSchedulerStateImpl
     MPU_xTaskGetSchedulerState_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetSchedulerStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetSchedulerState
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskSetTimeOutState
@@ -464,10 +389,7 @@ MPU_vTaskSetTimeOutState:
         b MPU_vTaskSetTimeOutStateImpl
     MPU_vTaskSetTimeOutState_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSetTimeOutStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskSetTimeOutState
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskCheckForTimeOut
@@ -481,14 +403,11 @@ MPU_xTaskCheckForTimeOut:
         b MPU_xTaskCheckForTimeOutImpl
     MPU_xTaskCheckForTimeOut_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskCheckForTimeOutImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskCheckForTimeOut
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xTaskGenericNotify
-MPU_xTaskGenericNotify:
+    PUBLIC MPU_xTaskGenericNotifyEntry
+MPU_xTaskGenericNotifyEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
@@ -498,14 +417,11 @@ MPU_xTaskGenericNotify:
         b MPU_xTaskGenericNotifyImpl
     MPU_xTaskGenericNotify_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTaskGenericNotifyImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGenericNotify
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xTaskGenericNotifyWait
-MPU_xTaskGenericNotifyWait:
+    PUBLIC MPU_xTaskGenericNotifyWaitEntry
+MPU_xTaskGenericNotifyWaitEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
@@ -515,10 +431,7 @@ MPU_xTaskGenericNotifyWait:
         b MPU_xTaskGenericNotifyWaitImpl
     MPU_xTaskGenericNotifyWait_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTaskGenericNotifyWaitImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGenericNotifyWait
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGenericNotifyTake
@@ -532,10 +445,7 @@ MPU_ulTaskGenericNotifyTake:
         b MPU_ulTaskGenericNotifyTakeImpl
     MPU_ulTaskGenericNotifyTake_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGenericNotifyTakeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGenericNotifyTake
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGenericNotifyStateClear
@@ -549,10 +459,7 @@ MPU_xTaskGenericNotifyStateClear:
         b MPU_xTaskGenericNotifyStateClearImpl
     MPU_xTaskGenericNotifyStateClear_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGenericNotifyStateClearImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGenericNotifyStateClear
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGenericNotifyValueClear
@@ -566,10 +473,7 @@ MPU_ulTaskGenericNotifyValueClear:
         b MPU_ulTaskGenericNotifyValueClearImpl
     MPU_ulTaskGenericNotifyValueClear_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGenericNotifyValueClearImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueGenericSend
@@ -583,10 +487,7 @@ MPU_xQueueGenericSend:
         b MPU_xQueueGenericSendImpl
     MPU_xQueueGenericSend_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueGenericSendImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueGenericSend
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxQueueMessagesWaiting
@@ -600,10 +501,7 @@ MPU_uxQueueMessagesWaiting:
         b MPU_uxQueueMessagesWaitingImpl
     MPU_uxQueueMessagesWaiting_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxQueueMessagesWaitingImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxQueueMessagesWaiting
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxQueueSpacesAvailable
@@ -617,10 +515,7 @@ MPU_uxQueueSpacesAvailable:
         b MPU_uxQueueSpacesAvailableImpl
     MPU_uxQueueSpacesAvailable_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxQueueSpacesAvailableImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxQueueSpacesAvailable
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueReceive
@@ -634,10 +529,7 @@ MPU_xQueueReceive:
         b MPU_xQueueReceiveImpl
     MPU_xQueueReceive_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueReceiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueReceive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueuePeek
@@ -651,10 +543,7 @@ MPU_xQueuePeek:
         b MPU_xQueuePeekImpl
     MPU_xQueuePeek_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueuePeekImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueuePeek
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueSemaphoreTake
@@ -668,10 +557,7 @@ MPU_xQueueSemaphoreTake:
         b MPU_xQueueSemaphoreTakeImpl
     MPU_xQueueSemaphoreTake_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueSemaphoreTakeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueSemaphoreTake
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueGetMutexHolder
@@ -685,10 +571,7 @@ MPU_xQueueGetMutexHolder:
         b MPU_xQueueGetMutexHolderImpl
     MPU_xQueueGetMutexHolder_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueGetMutexHolderImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueGetMutexHolder
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueTakeMutexRecursive
@@ -702,10 +585,7 @@ MPU_xQueueTakeMutexRecursive:
         b MPU_xQueueTakeMutexRecursiveImpl
     MPU_xQueueTakeMutexRecursive_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueTakeMutexRecursiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueTakeMutexRecursive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueGiveMutexRecursive
@@ -719,10 +599,7 @@ MPU_xQueueGiveMutexRecursive:
         b MPU_xQueueGiveMutexRecursiveImpl
     MPU_xQueueGiveMutexRecursive_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueGiveMutexRecursiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueGiveMutexRecursive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueSelectFromSet
@@ -736,10 +613,7 @@ MPU_xQueueSelectFromSet:
         b MPU_xQueueSelectFromSetImpl
     MPU_xQueueSelectFromSet_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueSelectFromSetImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueSelectFromSet
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueAddToSet
@@ -753,10 +627,7 @@ MPU_xQueueAddToSet:
         b MPU_xQueueAddToSetImpl
     MPU_xQueueAddToSet_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueAddToSetImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueAddToSet
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vQueueAddToRegistry
@@ -770,10 +641,7 @@ MPU_vQueueAddToRegistry:
         b MPU_vQueueAddToRegistryImpl
     MPU_vQueueAddToRegistry_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vQueueAddToRegistryImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vQueueAddToRegistry
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vQueueUnregisterQueue
@@ -787,10 +655,7 @@ MPU_vQueueUnregisterQueue:
         b MPU_vQueueUnregisterQueueImpl
     MPU_vQueueUnregisterQueue_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vQueueUnregisterQueueImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vQueueUnregisterQueue
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pcQueueGetName
@@ -804,10 +669,7 @@ MPU_pcQueueGetName:
         b MPU_pcQueueGetNameImpl
     MPU_pcQueueGetName_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pcQueueGetNameImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_pcQueueGetName
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pvTimerGetTimerID
@@ -821,10 +683,7 @@ MPU_pvTimerGetTimerID:
         b MPU_pvTimerGetTimerIDImpl
     MPU_pvTimerGetTimerID_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pvTimerGetTimerIDImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_pvTimerGetTimerID
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTimerSetTimerID
@@ -838,10 +697,7 @@ MPU_vTimerSetTimerID:
         b MPU_vTimerSetTimerIDImpl
     MPU_vTimerSetTimerID_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTimerSetTimerIDImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTimerSetTimerID
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerIsTimerActive
@@ -855,10 +711,7 @@ MPU_xTimerIsTimerActive:
         b MPU_xTimerIsTimerActiveImpl
     MPU_xTimerIsTimerActive_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerIsTimerActiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerIsTimerActive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerGetTimerDaemonTaskHandle
@@ -872,14 +725,11 @@ MPU_xTimerGetTimerDaemonTaskHandle:
         b MPU_xTimerGetTimerDaemonTaskHandleImpl
     MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetTimerDaemonTaskHandleImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xTimerGenericCommandFromTask
-MPU_xTimerGenericCommandFromTask:
+    PUBLIC MPU_xTimerGenericCommandFromTaskEntry
+MPU_xTimerGenericCommandFromTaskEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
@@ -889,10 +739,7 @@ MPU_xTimerGenericCommandFromTask:
         b MPU_xTimerGenericCommandFromTaskImpl
     MPU_xTimerGenericCommandFromTask_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTimerGenericCommandFromTaskImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGenericCommandFromTask
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pcTimerGetName
@@ -906,10 +753,7 @@ MPU_pcTimerGetName:
         b MPU_pcTimerGetNameImpl
     MPU_pcTimerGetName_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pcTimerGetNameImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_pcTimerGetName
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTimerSetReloadMode
@@ -923,10 +767,7 @@ MPU_vTimerSetReloadMode:
         b MPU_vTimerSetReloadModeImpl
     MPU_vTimerSetReloadMode_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTimerSetReloadModeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTimerSetReloadMode
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerGetReloadMode
@@ -940,10 +781,7 @@ MPU_xTimerGetReloadMode:
         b MPU_xTimerGetReloadModeImpl
     MPU_xTimerGetReloadMode_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetReloadModeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGetReloadMode
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTimerGetReloadMode
@@ -957,10 +795,7 @@ MPU_uxTimerGetReloadMode:
         b MPU_uxTimerGetReloadModeImpl
     MPU_uxTimerGetReloadMode_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTimerGetReloadModeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTimerGetReloadMode
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerGetPeriod
@@ -974,10 +809,7 @@ MPU_xTimerGetPeriod:
         b MPU_xTimerGetPeriodImpl
     MPU_xTimerGetPeriod_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetPeriodImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGetPeriod
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerGetExpiryTime
@@ -991,14 +823,11 @@ MPU_xTimerGetExpiryTime:
         b MPU_xTimerGetExpiryTimeImpl
     MPU_xTimerGetExpiryTime_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetExpiryTimeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGetExpiryTime
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xEventGroupWaitBits
-MPU_xEventGroupWaitBits:
+    PUBLIC MPU_xEventGroupWaitBitsEntry
+MPU_xEventGroupWaitBitsEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
@@ -1008,10 +837,7 @@ MPU_xEventGroupWaitBits:
         b MPU_xEventGroupWaitBitsImpl
     MPU_xEventGroupWaitBits_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xEventGroupWaitBitsImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xEventGroupWaitBits
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xEventGroupClearBits
@@ -1025,10 +851,7 @@ MPU_xEventGroupClearBits:
         b MPU_xEventGroupClearBitsImpl
     MPU_xEventGroupClearBits_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xEventGroupClearBitsImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xEventGroupClearBits
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xEventGroupSetBits
@@ -1042,10 +865,7 @@ MPU_xEventGroupSetBits:
         b MPU_xEventGroupSetBitsImpl
     MPU_xEventGroupSetBits_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xEventGroupSetBitsImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xEventGroupSetBits
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xEventGroupSync
@@ -1059,10 +879,7 @@ MPU_xEventGroupSync:
         b MPU_xEventGroupSyncImpl
     MPU_xEventGroupSync_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xEventGroupSyncImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xEventGroupSync
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxEventGroupGetNumber
@@ -1076,10 +893,7 @@ MPU_uxEventGroupGetNumber:
         b MPU_uxEventGroupGetNumberImpl
     MPU_uxEventGroupGetNumber_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxEventGroupGetNumberImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxEventGroupGetNumber
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vEventGroupSetNumber
@@ -1093,10 +907,7 @@ MPU_vEventGroupSetNumber:
         b MPU_vEventGroupSetNumberImpl
     MPU_vEventGroupSetNumber_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vEventGroupSetNumberImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vEventGroupSetNumber
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferSend
@@ -1110,10 +921,7 @@ MPU_xStreamBufferSend:
         b MPU_xStreamBufferSendImpl
     MPU_xStreamBufferSend_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferSendImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferSend
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferReceive
@@ -1127,10 +935,7 @@ MPU_xStreamBufferReceive:
         b MPU_xStreamBufferReceiveImpl
     MPU_xStreamBufferReceive_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferReceiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferReceive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferIsFull
@@ -1144,10 +949,7 @@ MPU_xStreamBufferIsFull:
         b MPU_xStreamBufferIsFullImpl
     MPU_xStreamBufferIsFull_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferIsFullImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferIsFull
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferIsEmpty
@@ -1161,10 +963,7 @@ MPU_xStreamBufferIsEmpty:
         b MPU_xStreamBufferIsEmptyImpl
     MPU_xStreamBufferIsEmpty_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferIsEmptyImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferIsEmpty
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferSpacesAvailable
@@ -1178,10 +977,7 @@ MPU_xStreamBufferSpacesAvailable:
         b MPU_xStreamBufferSpacesAvailableImpl
     MPU_xStreamBufferSpacesAvailable_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferSpacesAvailableImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferSpacesAvailable
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferBytesAvailable
@@ -1195,10 +991,7 @@ MPU_xStreamBufferBytesAvailable:
         b MPU_xStreamBufferBytesAvailableImpl
     MPU_xStreamBufferBytesAvailable_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferBytesAvailableImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferBytesAvailable
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferSetTriggerLevel
@@ -1212,10 +1005,7 @@ MPU_xStreamBufferSetTriggerLevel:
         b MPU_xStreamBufferSetTriggerLevelImpl
     MPU_xStreamBufferSetTriggerLevel_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferSetTriggerLevelImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferNextMessageLengthBytes
@@ -1229,10 +1019,7 @@ MPU_xStreamBufferNextMessageLengthBytes:
         b MPU_xStreamBufferNextMessageLengthBytesImpl
     MPU_xStreamBufferNextMessageLengthBytes_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferNextMessageLengthBytesImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes
 /*-----------------------------------------------------------*/
 
 /* Default weak implementations in case one is not available from
diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c b/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
index 52d68d3ea..6a3877894 100644
--- a/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
@@ -35,8 +35,9 @@
 #include "FreeRTOS.h"
 #include "task.h"
 
-/* MPU wrappers includes. */
+/* MPU includes. */
 #include "mpu_wrappers.h"
+#include "mpu_syscall_numbers.h"
 
 /* Portasm includes. */
 #include "portasm.h"
@@ -436,29 +437,22 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
  * @brief Sets up the system call stack so that upon returning from
  * SVC, the system call stack is used.
  *
- * It is used for the system calls with up to 4 parameters.
- *
  * @param pulTaskStack The current SP when the SVC was raised.
  * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ * @param ucSystemCallNumber The system call number of the system call.
  */
     void vSystemCallEnter( uint32_t * pulTaskStack,
-                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
+                           uint32_t ulLR,
+                           uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
- * @brief Sets up the system call stack so that upon returning from
- * SVC, the system call stack is used.
- *
- * It is used for the system calls with 5 parameters.
- *
- * @param pulTaskStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ * @brief Raise SVC for exiting from a system call.
  */
-    void vSystemCallEnter_1( uint32_t * pulTaskStack,
-                             uint32_t ulLR ) PRIVILEGED_FUNCTION;
+    void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
@@ -488,6 +482,15 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+/**
+ * @brief This variable is set to pdTRUE when the scheduler is started.
+ */
+    PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
+
+#endif
+
 /**
  * @brief Each task maintains its own interrupt status in the critical nesting
  * variable.
@@ -1134,15 +1137,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     void vSystemCallEnter( uint32_t * pulTaskStack,
-                           uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
+                           uint32_t ulLR,
+                           uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */
     {
         extern TaskHandle_t pxCurrentTCB;
+        extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ];
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulSystemCallStack;
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
-
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __syscalls_flash_start__;
@@ -1154,17 +1158,27 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         #endif /* #if defined( __ARMCC_VERSION ) */
 
         ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
 
-        /* If the request did not come from the system call section, do nothing. */
+        /* Checks:
+         * 1. SVC is raised from the system call section (i.e. application is
+         *    not raising SVC directly).
+         * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as
+         *    it is non-NULL only during the execution of a system call (i.e.
+         *    between system call enter and exit).
+         * 3. System call is not for a kernel API disabled by the configuration
+         *    in FreeRTOSConfig.h.
+         * 4. We do not need to check that ucSystemCallNumber is within range
+         *    because the assembly SVC handler checks that before calling
+         *    this function.
+         */
         if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) &&
+            ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) &&
+            ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) )
         {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
             pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
 
-            /* This is not NULL only for the duration of the system call. */
-            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
-
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
@@ -1198,9 +1212,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 pulSystemCallStack[ i ] = pulTaskStack[ i ];
             }
 
-            /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
-             * restore it when we exit from the system call. */
+            /* Store the value of the Link Register before the SVC was raised.
+             * It contains the address of the caller of the System Call entry
+             * point (i.e. the caller of the MPU_<API>). We need to restore it
+             * when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            /* Store the value of the PSPLIM register before the SVC was raised.
+             * We need to restore it when we exit from the system call. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
             {
                 __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
@@ -1215,6 +1233,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             }
             #endif
 
+            /* Start executing the system call upon returning from this handler. */
+            pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
+            /* Raise a request to exit from the system call upon finishing the
+             * system call. */
+            pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit;
+
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
             pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
@@ -1251,127 +1275,9 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    void vSystemCallEnter_1( uint32_t * pulTaskStack,
-                             uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
+    void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */
     {
-        extern TaskHandle_t pxCurrentTCB;
-        xMPU_SETTINGS * pxMpuSettings;
-        uint32_t * pulSystemCallStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-
-        #if defined( __ARMCC_VERSION )
-
-            /* Declaration when these variable are defined in code instead of being
-             * exported from linker scripts. */
-            extern uint32_t * __syscalls_flash_start__;
-            extern uint32_t * __syscalls_flash_end__;
-        #else
-            /* Declaration when these variable are exported from linker scripts. */
-            extern uint32_t __syscalls_flash_start__[];
-            extern uint32_t __syscalls_flash_end__[];
-        #endif /* #if defined( __ARMCC_VERSION ) */
-
-        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-        /* If the request did not come from the system call section, do nothing. */
-        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
-        {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
-
-            /* This is not NULL only for the duration of the system call. */
-            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
-
-            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-            {
-                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
-                {
-                    /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
-                    __asm volatile (
-                        " vpush {s0}         \n" /* Trigger lazy stacking. */
-                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                        ::: "memory"
-                        );
-                }
-                else
-                {
-                    /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
-                }
-            }
-            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
-            {
-                ulStackFrameSize = 8;
-            }
-            #endif /* configENABLE_FPU || configENABLE_MVE */
-
-            /* Make space on the system call stack for the stack frame and
-             * the parameter passed on the stack. We only need to copy one
-             * parameter but we still reserve 2 spaces to keep the stack
-             * double word aligned. */
-            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
-
-            /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
-            {
-                pulSystemCallStack[ i ] = pulTaskStack[ i ];
-            }
-
-            /* Copy the parameter which is passed the stack. */
-            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-            {
-                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
-
-                /* Record if the hardware used padding to force the stack pointer
-                 * to be double word aligned. */
-                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-            }
-            else
-            {
-                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
-
-                /* Record if the hardware used padding to force the stack pointer
-                 * to be double word aligned. */
-                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-            }
-
-            /* Store the value of the LR and PSPLIM registers before the SVC was raised.
-             * We need to restore it when we exit from the system call. */
-            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            #if ( portUSE_PSPLIM_REGISTER == 1 )
-            {
-                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-            }
-            #endif
-
-            /* Use the pulSystemCallStack in thread mode. */
-            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            #if ( portUSE_PSPLIM_REGISTER == 1 )
-            {
-                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-            }
-            #endif
-
-            /* Remember the location where we should copy the stack frame when we exit from
-             * the system call. */
-            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-            /* We ensure in pxPortInitialiseStack that the system call stack is
-             * double word aligned and therefore, there is no need of padding.
-             * Clear the bit[9] of stacked xPSR. */
-            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-            /* Raise the privilege for the duration of the system call. */
-            __asm volatile (
-                " mrs r0, control     \n" /* Obtain current control value. */
-                " movs r1, #1         \n" /* r1 = 1. */
-                " bics r0, r1         \n" /* Clear nPRIV bit. */
-                " msr control, r0     \n" /* Write back new control value. */
-                ::: "r0", "r1", "memory"
-                );
-        }
+        __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" );
     }
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@@ -1388,24 +1294,32 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
-
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
-            extern uint32_t * __syscalls_flash_start__;
-            extern uint32_t * __syscalls_flash_end__;
+            extern uint32_t * __privileged_functions_start__;
+            extern uint32_t * __privileged_functions_end__;
         #else
             /* Declaration when these variable are exported from linker scripts. */
-            extern uint32_t __syscalls_flash_start__[];
-            extern uint32_t __syscalls_flash_end__[];
+            extern uint32_t __privileged_functions_start__[];
+            extern uint32_t __privileged_functions_end__[];
         #endif /* #if defined( __ARMCC_VERSION ) */
 
         ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
+        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
 
-        /* If the request did not come from the system call section, do nothing. */
-        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+        /* Checks:
+         * 1. SVC is raised from the privileged code (i.e. application is not
+         *    raising SVC directly). This SVC is only raised from
+         *    vRequestSystemCallExit which is in the privileged code section.
+         * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL -
+         *    this means that we previously entered a system call and the
+         *    application is not attempting to exit without entering a system
+         *    call.
+         */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) &&
+            ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) )
         {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
             pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
 
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
@@ -1444,9 +1358,14 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Use the pulTaskStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
 
-            /* Restore the LR and PSPLIM to what they were at the time of
-             * system call entry. */
+            /* Return to the caller of the System Call entry point (i.e. the
+             * caller of the MPU_<API>). */
+            pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+            /* Ensure that LR has a valid value.*/
             pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+
+            /* Restore the PSPLIM register to what it was at the time of
+             * system call entry. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
             {
                 __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
@@ -1780,6 +1699,12 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     /* Initialize the critical nesting count ready for the first task. */
     ulCriticalNesting = 0;
 
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+    {
+        xSchedulerRunning = pdTRUE;
+    }
+    #endif
+
     /* Start the first task. */
     vStartFirstTask();
 
@@ -2062,7 +1987,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
 
     void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
                                          int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
@@ -2078,10 +2003,10 @@ BaseType_t xPortIsInsideInterrupt( void )
         xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit );
     }
 
-#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
 
     void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
                                           int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
@@ -2097,10 +2022,10 @@ BaseType_t xPortIsInsideInterrupt( void )
         xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit );
     }
 
-#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
 
@@ -2108,21 +2033,34 @@ BaseType_t xPortIsInsideInterrupt( void )
         {
             uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
             BaseType_t xAccessGranted = pdFALSE;
-            const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+            const xMPU_SETTINGS * xTaskMpuSettings;
 
-            ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
-            ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
-
-            if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+            if( xSchedulerRunning == pdFALSE )
             {
+                /* Grant access to all the kernel objects before the scheduler
+                 * is started. It is necessary because there is no task running
+                 * yet and therefore, we cannot use the permissions of any
+                 * task. */
                 xAccessGranted = pdTRUE;
             }
             else
             {
-                if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+                ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+                ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+                if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
                 {
                     xAccessGranted = pdTRUE;
                 }
+                else
+                {
+                    if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                    {
+                        xAccessGranted = pdTRUE;
+                    }
+                }
             }
 
             return xAccessGranted;
@@ -2141,5 +2079,5 @@ BaseType_t xPortIsInsideInterrupt( void )
 
     #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
 
-#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.s b/portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.s
index ec5202527..7cf467d22 100644
--- a/portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.s
+++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.s
@@ -32,6 +32,9 @@ the code is included in C files but excluded by the preprocessor in assembly
 files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
 #include "FreeRTOSConfig.h"
 
+/* System call numbers includes. */
+#include "mpu_syscall_numbers.h"
+
 #ifndef configUSE_MPU_WRAPPERS_V1
     #define configUSE_MPU_WRAPPERS_V1 0
 #endif
@@ -41,7 +44,6 @@ files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler.
     EXTERN vPortSVCHandler_C
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
     EXTERN vSystemCallEnter
-    EXTERN vSystemCallEnter_1
     EXTERN vSystemCallExit
 #endif
 
@@ -191,7 +193,7 @@ vStartFirstTask:
     cpsie f
     dsb
     isb
-    svc 2                                   /* System call to start the first task. portSVC_START_SCHEDULER = 2. */
+    svc 102                                 /* System call to start the first task. portSVC_START_SCHEDULER = 102. */
 /*-----------------------------------------------------------*/
 
 ulSetInterruptMask:
@@ -371,11 +373,9 @@ SVC_Handler:
 
     ldr r1, [r0, #24]
     ldrb r2, [r1, #-2]
-    cmp r2, #4          /* portSVC_SYSTEM_CALL_ENTER. */
-    beq syscall_enter
-    cmp r2, #5          /* portSVC_SYSTEM_CALL_ENTER_1. */
-    beq syscall_enter_1
-    cmp r2, #6          /* portSVC_SYSTEM_CALL_EXIT. */
+    cmp r2, #NUM_SYSTEM_CALLS
+    blt syscall_enter
+    cmp r2, #104            /* portSVC_SYSTEM_CALL_EXIT. */
     beq syscall_exit
     b vPortSVCHandler_C
 
@@ -383,10 +383,6 @@ SVC_Handler:
         mov r1, lr
         b vSystemCallEnter
 
-    syscall_enter_1:
-        mov r1, lr
-        b vSystemCallEnter_1
-
     syscall_exit:
         mov r1, lr
         b vSystemCallExit
diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
index 60ef37380..672b0dbdc 100644
--- a/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
@@ -322,14 +322,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 /**
  * @brief SVC numbers.
  */
-#define portSVC_ALLOCATE_SECURE_CONTEXT    0
-#define portSVC_FREE_SECURE_CONTEXT        1
-#define portSVC_START_SCHEDULER            2
-#define portSVC_RAISE_PRIVILEGE            3
-#define portSVC_SYSTEM_CALL_ENTER          4   /* System calls with upto 4 parameters. */
-#define portSVC_SYSTEM_CALL_ENTER_1        5   /* System calls with 5 parameters. */
-#define portSVC_SYSTEM_CALL_EXIT           6
-#define portSVC_YIELD                      7
+#define portSVC_ALLOCATE_SECURE_CONTEXT    100
+#define portSVC_FREE_SECURE_CONTEXT        101
+#define portSVC_START_SCHEDULER            102
+#define portSVC_RAISE_PRIVILEGE            103
+#define portSVC_SYSTEM_CALL_EXIT           104
+#define portSVC_YIELD                      105
 /*-----------------------------------------------------------*/
 
 /**
diff --git a/portable/IAR/ARM_CM4F_MPU/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM4F_MPU/mpu_wrappers_v2_asm.S
index 8d88af630..d21dbaa7f 100644
--- a/portable/IAR/ARM_CM4F_MPU/mpu_wrappers_v2_asm.S
+++ b/portable/IAR/ARM_CM4F_MPU/mpu_wrappers_v2_asm.S
@@ -32,6 +32,7 @@
  * the code is included in C files but excluded by the preprocessor in assembly
  * files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
 #include "FreeRTOSConfig.h"
+#include "mpu_syscall_numbers.h"
 
     SECTION freertos_system_calls:CODE:NOROOT(2)
     THUMB
@@ -41,10 +42,6 @@
     #define configUSE_MPU_WRAPPERS_V1 0
 #endif
 
-/* These must be in sync with portmacro.h. */
-#define portSVC_SYSTEM_CALL_ENTER   3 /* System calls with upto 4 parameters. */
-#define portSVC_SYSTEM_CALL_ENTER_1 4 /* System calls with 5 parameters. */
-#define portSVC_SYSTEM_CALL_EXIT    5
 /*-----------------------------------------------------------*/
 
 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
@@ -60,10 +57,7 @@ MPU_xTaskDelayUntil:
         b MPU_xTaskDelayUntilImpl
     MPU_xTaskDelayUntil_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskDelayUntilImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskDelayUntil
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskAbortDelay
@@ -77,10 +71,7 @@ MPU_xTaskAbortDelay:
         b MPU_xTaskAbortDelayImpl
     MPU_xTaskAbortDelay_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskAbortDelayImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskAbortDelay
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskDelay
@@ -94,10 +85,7 @@ MPU_vTaskDelay:
         b MPU_vTaskDelayImpl
     MPU_vTaskDelay_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskDelayImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskDelay
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskPriorityGet
@@ -111,10 +99,7 @@ MPU_uxTaskPriorityGet:
         b MPU_uxTaskPriorityGetImpl
     MPU_uxTaskPriorityGet_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskPriorityGetImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskPriorityGet
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_eTaskGetState
@@ -128,10 +113,7 @@ MPU_eTaskGetState:
         b MPU_eTaskGetStateImpl
     MPU_eTaskGetState_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_eTaskGetStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_eTaskGetState
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskGetInfo
@@ -145,10 +127,7 @@ MPU_vTaskGetInfo:
         b MPU_vTaskGetInfoImpl
     MPU_vTaskGetInfo_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskGetInfoImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskGetInfo
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetIdleTaskHandle
@@ -162,10 +141,7 @@ MPU_xTaskGetIdleTaskHandle:
         b MPU_xTaskGetIdleTaskHandleImpl
     MPU_xTaskGetIdleTaskHandle_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetIdleTaskHandleImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetIdleTaskHandle
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskSuspend
@@ -179,10 +155,7 @@ MPU_vTaskSuspend:
         b MPU_vTaskSuspendImpl
     MPU_vTaskSuspend_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSuspendImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskSuspend
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskResume
@@ -196,10 +169,7 @@ MPU_vTaskResume:
         b MPU_vTaskResumeImpl
     MPU_vTaskResume_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskResumeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskResume
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetTickCount
@@ -213,10 +183,7 @@ MPU_xTaskGetTickCount:
         b MPU_xTaskGetTickCountImpl
     MPU_xTaskGetTickCount_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetTickCountImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetTickCount
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskGetNumberOfTasks
@@ -230,10 +197,7 @@ MPU_uxTaskGetNumberOfTasks:
         b MPU_uxTaskGetNumberOfTasksImpl
     MPU_uxTaskGetNumberOfTasks_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetNumberOfTasksImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskGetNumberOfTasks
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGetRunTimeCounter
@@ -247,10 +211,7 @@ MPU_ulTaskGetRunTimeCounter:
         b MPU_ulTaskGetRunTimeCounterImpl
     MPU_ulTaskGetRunTimeCounter_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetRunTimeCounterImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGetRunTimeCounter
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGetRunTimePercent
@@ -264,10 +225,7 @@ MPU_ulTaskGetRunTimePercent:
         b MPU_ulTaskGetRunTimePercentImpl
     MPU_ulTaskGetRunTimePercent_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetRunTimePercentImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGetRunTimePercent
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGetIdleRunTimePercent
@@ -281,10 +239,7 @@ MPU_ulTaskGetIdleRunTimePercent:
         b MPU_ulTaskGetIdleRunTimePercentImpl
     MPU_ulTaskGetIdleRunTimePercent_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetIdleRunTimePercentImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGetIdleRunTimeCounter
@@ -298,10 +253,7 @@ MPU_ulTaskGetIdleRunTimeCounter:
         b MPU_ulTaskGetIdleRunTimeCounterImpl
     MPU_ulTaskGetIdleRunTimeCounter_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetIdleRunTimeCounterImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskSetApplicationTaskTag
@@ -315,10 +267,7 @@ MPU_vTaskSetApplicationTaskTag:
         b MPU_vTaskSetApplicationTaskTagImpl
     MPU_vTaskSetApplicationTaskTag_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSetApplicationTaskTagImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskSetApplicationTaskTag
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetApplicationTaskTag
@@ -332,10 +281,7 @@ MPU_xTaskGetApplicationTaskTag:
         b MPU_xTaskGetApplicationTaskTagImpl
     MPU_xTaskGetApplicationTaskTag_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetApplicationTaskTagImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetApplicationTaskTag
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskSetThreadLocalStoragePointer
@@ -349,10 +295,7 @@ MPU_vTaskSetThreadLocalStoragePointer:
         b MPU_vTaskSetThreadLocalStoragePointerImpl
     MPU_vTaskSetThreadLocalStoragePointer_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSetThreadLocalStoragePointerImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pvTaskGetThreadLocalStoragePointer
@@ -366,10 +309,7 @@ MPU_pvTaskGetThreadLocalStoragePointer:
         b MPU_pvTaskGetThreadLocalStoragePointerImpl
     MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pvTaskGetThreadLocalStoragePointerImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskGetSystemState
@@ -383,10 +323,7 @@ MPU_uxTaskGetSystemState:
         b MPU_uxTaskGetSystemStateImpl
     MPU_uxTaskGetSystemState_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetSystemStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskGetSystemState
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskGetStackHighWaterMark
@@ -400,10 +337,7 @@ MPU_uxTaskGetStackHighWaterMark:
         b MPU_uxTaskGetStackHighWaterMarkImpl
     MPU_uxTaskGetStackHighWaterMark_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetStackHighWaterMarkImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskGetStackHighWaterMark2
@@ -417,10 +351,7 @@ MPU_uxTaskGetStackHighWaterMark2:
         b MPU_uxTaskGetStackHighWaterMark2Impl
     MPU_uxTaskGetStackHighWaterMark2_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetStackHighWaterMark2Impl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetCurrentTaskHandle
@@ -434,10 +365,7 @@ MPU_xTaskGetCurrentTaskHandle:
         b MPU_xTaskGetCurrentTaskHandleImpl
     MPU_xTaskGetCurrentTaskHandle_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetCurrentTaskHandleImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetSchedulerState
@@ -451,10 +379,7 @@ MPU_xTaskGetSchedulerState:
         b MPU_xTaskGetSchedulerStateImpl
     MPU_xTaskGetSchedulerState_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetSchedulerStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetSchedulerState
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskSetTimeOutState
@@ -468,10 +393,7 @@ MPU_vTaskSetTimeOutState:
         b MPU_vTaskSetTimeOutStateImpl
     MPU_vTaskSetTimeOutState_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSetTimeOutStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskSetTimeOutState
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskCheckForTimeOut
@@ -485,14 +407,11 @@ MPU_xTaskCheckForTimeOut:
         b MPU_xTaskCheckForTimeOutImpl
     MPU_xTaskCheckForTimeOut_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskCheckForTimeOutImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskCheckForTimeOut
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xTaskGenericNotify
-MPU_xTaskGenericNotify:
+    PUBLIC MPU_xTaskGenericNotifyEntry
+MPU_xTaskGenericNotifyEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
@@ -502,14 +421,11 @@ MPU_xTaskGenericNotify:
         b MPU_xTaskGenericNotifyImpl
     MPU_xTaskGenericNotify_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTaskGenericNotifyImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGenericNotify
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xTaskGenericNotifyWait
-MPU_xTaskGenericNotifyWait:
+    PUBLIC MPU_xTaskGenericNotifyWaitEntry
+MPU_xTaskGenericNotifyWaitEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
@@ -519,10 +435,7 @@ MPU_xTaskGenericNotifyWait:
         b MPU_xTaskGenericNotifyWaitImpl
     MPU_xTaskGenericNotifyWait_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTaskGenericNotifyWaitImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGenericNotifyWait
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGenericNotifyTake
@@ -536,10 +449,7 @@ MPU_ulTaskGenericNotifyTake:
         b MPU_ulTaskGenericNotifyTakeImpl
     MPU_ulTaskGenericNotifyTake_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGenericNotifyTakeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGenericNotifyTake
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGenericNotifyStateClear
@@ -553,10 +463,7 @@ MPU_xTaskGenericNotifyStateClear:
         b MPU_xTaskGenericNotifyStateClearImpl
     MPU_xTaskGenericNotifyStateClear_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGenericNotifyStateClearImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGenericNotifyStateClear
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGenericNotifyValueClear
@@ -570,10 +477,7 @@ MPU_ulTaskGenericNotifyValueClear:
         b MPU_ulTaskGenericNotifyValueClearImpl
     MPU_ulTaskGenericNotifyValueClear_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGenericNotifyValueClearImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueGenericSend
@@ -587,10 +491,7 @@ MPU_xQueueGenericSend:
         b MPU_xQueueGenericSendImpl
     MPU_xQueueGenericSend_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueGenericSendImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueGenericSend
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxQueueMessagesWaiting
@@ -604,10 +505,7 @@ MPU_uxQueueMessagesWaiting:
         b MPU_uxQueueMessagesWaitingImpl
     MPU_uxQueueMessagesWaiting_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxQueueMessagesWaitingImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxQueueMessagesWaiting
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxQueueSpacesAvailable
@@ -621,10 +519,7 @@ MPU_uxQueueSpacesAvailable:
         b MPU_uxQueueSpacesAvailableImpl
     MPU_uxQueueSpacesAvailable_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxQueueSpacesAvailableImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxQueueSpacesAvailable
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueReceive
@@ -638,10 +533,7 @@ MPU_xQueueReceive:
         b MPU_xQueueReceiveImpl
     MPU_xQueueReceive_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueReceiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueReceive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueuePeek
@@ -655,10 +547,7 @@ MPU_xQueuePeek:
         b MPU_xQueuePeekImpl
     MPU_xQueuePeek_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueuePeekImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueuePeek
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueSemaphoreTake
@@ -672,10 +561,7 @@ MPU_xQueueSemaphoreTake:
         b MPU_xQueueSemaphoreTakeImpl
     MPU_xQueueSemaphoreTake_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueSemaphoreTakeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueSemaphoreTake
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueGetMutexHolder
@@ -689,10 +575,7 @@ MPU_xQueueGetMutexHolder:
         b MPU_xQueueGetMutexHolderImpl
     MPU_xQueueGetMutexHolder_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueGetMutexHolderImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueGetMutexHolder
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueTakeMutexRecursive
@@ -706,10 +589,7 @@ MPU_xQueueTakeMutexRecursive:
         b MPU_xQueueTakeMutexRecursiveImpl
     MPU_xQueueTakeMutexRecursive_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueTakeMutexRecursiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueTakeMutexRecursive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueGiveMutexRecursive
@@ -723,10 +603,7 @@ MPU_xQueueGiveMutexRecursive:
         b MPU_xQueueGiveMutexRecursiveImpl
     MPU_xQueueGiveMutexRecursive_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueGiveMutexRecursiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueGiveMutexRecursive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueSelectFromSet
@@ -740,10 +617,7 @@ MPU_xQueueSelectFromSet:
         b MPU_xQueueSelectFromSetImpl
     MPU_xQueueSelectFromSet_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueSelectFromSetImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueSelectFromSet
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueAddToSet
@@ -757,10 +631,7 @@ MPU_xQueueAddToSet:
         b MPU_xQueueAddToSetImpl
     MPU_xQueueAddToSet_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueAddToSetImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueAddToSet
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vQueueAddToRegistry
@@ -774,10 +645,7 @@ MPU_vQueueAddToRegistry:
         b MPU_vQueueAddToRegistryImpl
     MPU_vQueueAddToRegistry_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vQueueAddToRegistryImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vQueueAddToRegistry
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vQueueUnregisterQueue
@@ -791,10 +659,7 @@ MPU_vQueueUnregisterQueue:
         b MPU_vQueueUnregisterQueueImpl
     MPU_vQueueUnregisterQueue_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vQueueUnregisterQueueImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vQueueUnregisterQueue
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pcQueueGetName
@@ -808,10 +673,7 @@ MPU_pcQueueGetName:
         b MPU_pcQueueGetNameImpl
     MPU_pcQueueGetName_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pcQueueGetNameImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_pcQueueGetName
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pvTimerGetTimerID
@@ -825,10 +687,7 @@ MPU_pvTimerGetTimerID:
         b MPU_pvTimerGetTimerIDImpl
     MPU_pvTimerGetTimerID_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pvTimerGetTimerIDImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_pvTimerGetTimerID
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTimerSetTimerID
@@ -842,10 +701,7 @@ MPU_vTimerSetTimerID:
         b MPU_vTimerSetTimerIDImpl
     MPU_vTimerSetTimerID_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTimerSetTimerIDImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTimerSetTimerID
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerIsTimerActive
@@ -859,10 +715,7 @@ MPU_xTimerIsTimerActive:
         b MPU_xTimerIsTimerActiveImpl
     MPU_xTimerIsTimerActive_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerIsTimerActiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerIsTimerActive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerGetTimerDaemonTaskHandle
@@ -876,14 +729,11 @@ MPU_xTimerGetTimerDaemonTaskHandle:
         b MPU_xTimerGetTimerDaemonTaskHandleImpl
     MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetTimerDaemonTaskHandleImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xTimerGenericCommandFromTask
-MPU_xTimerGenericCommandFromTask:
+    PUBLIC MPU_xTimerGenericCommandFromTaskEntry
+MPU_xTimerGenericCommandFromTaskEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
@@ -893,10 +743,7 @@ MPU_xTimerGenericCommandFromTask:
         b MPU_xTimerGenericCommandFromTaskImpl
     MPU_xTimerGenericCommandFromTask_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTimerGenericCommandFromTaskImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGenericCommandFromTask
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pcTimerGetName
@@ -910,10 +757,7 @@ MPU_pcTimerGetName:
         b MPU_pcTimerGetNameImpl
     MPU_pcTimerGetName_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pcTimerGetNameImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_pcTimerGetName
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTimerSetReloadMode
@@ -927,10 +771,7 @@ MPU_vTimerSetReloadMode:
         b MPU_vTimerSetReloadModeImpl
     MPU_vTimerSetReloadMode_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTimerSetReloadModeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTimerSetReloadMode
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerGetReloadMode
@@ -944,10 +785,7 @@ MPU_xTimerGetReloadMode:
         b MPU_xTimerGetReloadModeImpl
     MPU_xTimerGetReloadMode_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetReloadModeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGetReloadMode
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTimerGetReloadMode
@@ -961,10 +799,7 @@ MPU_uxTimerGetReloadMode:
         b MPU_uxTimerGetReloadModeImpl
     MPU_uxTimerGetReloadMode_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTimerGetReloadModeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTimerGetReloadMode
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerGetPeriod
@@ -978,10 +813,7 @@ MPU_xTimerGetPeriod:
         b MPU_xTimerGetPeriodImpl
     MPU_xTimerGetPeriod_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetPeriodImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGetPeriod
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerGetExpiryTime
@@ -995,14 +827,11 @@ MPU_xTimerGetExpiryTime:
         b MPU_xTimerGetExpiryTimeImpl
     MPU_xTimerGetExpiryTime_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetExpiryTimeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGetExpiryTime
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xEventGroupWaitBits
-MPU_xEventGroupWaitBits:
+    PUBLIC MPU_xEventGroupWaitBitsEntry
+MPU_xEventGroupWaitBitsEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
@@ -1012,10 +841,7 @@ MPU_xEventGroupWaitBits:
         b MPU_xEventGroupWaitBitsImpl
     MPU_xEventGroupWaitBits_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xEventGroupWaitBitsImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xEventGroupWaitBits
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xEventGroupClearBits
@@ -1029,10 +855,7 @@ MPU_xEventGroupClearBits:
         b MPU_xEventGroupClearBitsImpl
     MPU_xEventGroupClearBits_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xEventGroupClearBitsImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xEventGroupClearBits
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xEventGroupSetBits
@@ -1046,10 +869,7 @@ MPU_xEventGroupSetBits:
         b MPU_xEventGroupSetBitsImpl
     MPU_xEventGroupSetBits_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xEventGroupSetBitsImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xEventGroupSetBits
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xEventGroupSync
@@ -1063,10 +883,7 @@ MPU_xEventGroupSync:
         b MPU_xEventGroupSyncImpl
     MPU_xEventGroupSync_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xEventGroupSyncImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xEventGroupSync
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxEventGroupGetNumber
@@ -1080,10 +897,7 @@ MPU_uxEventGroupGetNumber:
         b MPU_uxEventGroupGetNumberImpl
     MPU_uxEventGroupGetNumber_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxEventGroupGetNumberImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxEventGroupGetNumber
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vEventGroupSetNumber
@@ -1097,10 +911,7 @@ MPU_vEventGroupSetNumber:
         b MPU_vEventGroupSetNumberImpl
     MPU_vEventGroupSetNumber_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vEventGroupSetNumberImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vEventGroupSetNumber
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferSend
@@ -1114,10 +925,7 @@ MPU_xStreamBufferSend:
         b MPU_xStreamBufferSendImpl
     MPU_xStreamBufferSend_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferSendImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferSend
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferReceive
@@ -1131,10 +939,7 @@ MPU_xStreamBufferReceive:
         b MPU_xStreamBufferReceiveImpl
     MPU_xStreamBufferReceive_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferReceiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferReceive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferIsFull
@@ -1148,10 +953,7 @@ MPU_xStreamBufferIsFull:
         b MPU_xStreamBufferIsFullImpl
     MPU_xStreamBufferIsFull_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferIsFullImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferIsFull
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferIsEmpty
@@ -1165,10 +967,7 @@ MPU_xStreamBufferIsEmpty:
         b MPU_xStreamBufferIsEmptyImpl
     MPU_xStreamBufferIsEmpty_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferIsEmptyImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferIsEmpty
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferSpacesAvailable
@@ -1182,10 +981,7 @@ MPU_xStreamBufferSpacesAvailable:
         b MPU_xStreamBufferSpacesAvailableImpl
     MPU_xStreamBufferSpacesAvailable_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferSpacesAvailableImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferSpacesAvailable
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferBytesAvailable
@@ -1199,10 +995,7 @@ MPU_xStreamBufferBytesAvailable:
         b MPU_xStreamBufferBytesAvailableImpl
     MPU_xStreamBufferBytesAvailable_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferBytesAvailableImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferBytesAvailable
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferSetTriggerLevel
@@ -1216,10 +1009,7 @@ MPU_xStreamBufferSetTriggerLevel:
         b MPU_xStreamBufferSetTriggerLevelImpl
     MPU_xStreamBufferSetTriggerLevel_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferSetTriggerLevelImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferNextMessageLengthBytes
@@ -1233,10 +1023,7 @@ MPU_xStreamBufferNextMessageLengthBytes:
         b MPU_xStreamBufferNextMessageLengthBytesImpl
     MPU_xStreamBufferNextMessageLengthBytes_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferNextMessageLengthBytesImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes
 /*-----------------------------------------------------------*/
 
 /* Default weak implementations in case one is not available from
diff --git a/portable/IAR/ARM_CM4F_MPU/port.c b/portable/IAR/ARM_CM4F_MPU/port.c
index 6db7bd796..4f0b617ce 100644
--- a/portable/IAR/ARM_CM4F_MPU/port.c
+++ b/portable/IAR/ARM_CM4F_MPU/port.c
@@ -41,6 +41,7 @@
 /* Scheduler includes. */
 #include "FreeRTOS.h"
 #include "task.h"
+#include "mpu_syscall_numbers.h"
 
 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
 
@@ -236,29 +237,22 @@ extern void vPortRestoreContextOfFirstTask( void ) PRIVILEGED_FUNCTION;
  * @brief Sets up the system call stack so that upon returning from
  * SVC, the system call stack is used.
  *
- * It is used for the system calls with up to 4 parameters.
- *
  * @param pulTaskStack The current SP when the SVC was raised.
  * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ * @param ucSystemCallNumber The system call number of the system call.
  */
     void vSystemCallEnter( uint32_t * pulTaskStack,
-                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
+                           uint32_t ulLR,
+                           uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION;
 
 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
 
 /**
- * @brief Sets up the system call stack so that upon returning from
- * SVC, the system call stack is used.
- *
- * It is used for the system calls with 5 parameters.
- *
- * @param pulTaskStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ * @brief Raise SVC for exiting from a system call.
  */
-    void vSystemCallEnter_1( uint32_t * pulTaskStack,
-                             uint32_t ulLR ) PRIVILEGED_FUNCTION;
+    void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
 
 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
@@ -294,6 +288,15 @@ void vPortSwitchToUserMode( void );
  * variable. */
 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
 
+#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+/*
+ * This variable is set to pdTRUE when the scheduler is started.
+ */
+    PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
+
+#endif
+
 /*
  * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
  * FreeRTOS API functions are not called from interrupts that have been assigned
@@ -368,10 +371,10 @@ void vPortSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
     uint8_t ucSVCNumber;
     uint32_t ulPC;
 
-    #if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )
+    #if ( ( configUSE_MPU_WRAPPERS_V1 == 1 ) && ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) )
         extern uint32_t __syscalls_flash_start__[];
         extern uint32_t __syscalls_flash_end__[];
-    #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
+    #endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 1 ) && ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) ) */
 
     /* The stack contains: r0, r1, r2, r3, r12, LR, PC and xPSR. The first
      * argument (r0) is pulParam[ 0 ]. */
@@ -397,26 +400,15 @@ void vPortSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
 
             break;
 
-            #if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )
-                case portSVC_RAISE_PRIVILEGE: /* Only raise the privilege, if the
-                                               * svc was raised from any of the
-                                               * system calls. */
+    #if ( configUSE_MPU_WRAPPERS_V1 == 1 )
+        #if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )
+            case portSVC_RAISE_PRIVILEGE: /* Only raise the privilege, if the
+                                           * svc was raised from any of the
+                                           * system calls. */
 
-                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
-                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
-                    {
-                        __asm volatile
-                        (
-                            "   mrs r1, control     \n" /* Obtain current control value. */
-                            "   bic r1, r1, #1      \n" /* Set privilege bit. */
-                            "   msr control, r1     \n" /* Write back new control value. */
-                            ::: "r1", "memory"
-                        );
-                    }
-
-                    break;
-            #else /* if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
-                case portSVC_RAISE_PRIVILEGE:
+                if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+                    ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+                {
                     __asm volatile
                     (
                         "   mrs r1, control     \n" /* Obtain current control value. */
@@ -424,11 +416,24 @@ void vPortSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
                         "   msr control, r1     \n" /* Write back new control value. */
                         ::: "r1", "memory"
                     );
-                    break;
-                    #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
+                }
 
-                default: /* Unknown SVC call. */
-                    break;
+                break;
+        #else /* if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
+            case portSVC_RAISE_PRIVILEGE:
+                __asm volatile
+                (
+                    "   mrs r1, control     \n" /* Obtain current control value. */
+                    "   bic r1, r1, #1      \n" /* Set privilege bit. */
+                    "   msr control, r1     \n" /* Write back new control value. */
+                    ::: "r1", "memory"
+                );
+                break;
+        #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
+    #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+
+        default: /* Unknown SVC call. */
+            break;
     }
 }
 /*-----------------------------------------------------------*/
@@ -436,15 +441,16 @@ void vPortSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
 
     void vSystemCallEnter( uint32_t * pulTaskStack,
-                           uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
+                           uint32_t ulLR,
+                           uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */
     {
         extern TaskHandle_t pxCurrentTCB;
+        extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ];
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulSystemCallStack;
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
-
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __syscalls_flash_start__;
@@ -456,17 +462,27 @@ void vPortSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
         #endif /* #if defined( __ARMCC_VERSION ) */
 
         ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
 
-        /* If the request did not come from the system call section, do nothing. */
+        /* Checks:
+         * 1. SVC is raised from the system call section (i.e. application is
+         *    not raising SVC directly).
+         * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as
+         *    it is non-NULL only during the execution of a system call (i.e.
+         *    between system call enter and exit).
+         * 3. System call is not for a kernel API disabled by the configuration
+         *    in FreeRTOSConfig.h.
+         * 4. We do not need to check that ucSystemCallNumber is within range
+         *    because the assembly SVC handler checks that before calling
+         *    this function.
+         */
         if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) &&
+            ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) &&
+            ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) )
         {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
             pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
 
-            /* This is not NULL only for the duration of the system call. */
-            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
-
             if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
             {
                 /* Extended frame i.e. FPU in use. */
@@ -507,10 +523,19 @@ void vPortSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
              * the system call. */
             pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
 
-            /* Store the value of the Link Register before the SVC was raised. We need to
-             * restore it when we exit from the system call. */
+            /* Store the value of the Link Register before the SVC was raised.
+             * It contains the address of the caller of the System Call entry
+             * point (i.e. the caller of the MPU_<API>). We need to restore it
+             * when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
 
+
+            /* Start executing the system call upon returning from this handler. */
+            pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
+            /* Raise a request to exit from the system call upon finishing the
+             * system call. */
+            pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit;
+
             /* Record if the hardware used padding to force the stack pointer
              * to be double word aligned. */
             if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
@@ -534,108 +559,9 @@ void vPortSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
 
 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
 
-    void vSystemCallEnter_1( uint32_t * pulTaskStack,
-                             uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
+    void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */
     {
-        extern TaskHandle_t pxCurrentTCB;
-        xMPU_SETTINGS * pxMpuSettings;
-        uint32_t * pulSystemCallStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-
-        #if defined( __ARMCC_VERSION )
-
-            /* Declaration when these variable are defined in code instead of being
-             * exported from linker scripts. */
-            extern uint32_t * __syscalls_flash_start__;
-            extern uint32_t * __syscalls_flash_end__;
-        #else
-            /* Declaration when these variable are exported from linker scripts. */
-            extern uint32_t __syscalls_flash_start__[];
-            extern uint32_t __syscalls_flash_end__[];
-        #endif /* #if defined( __ARMCC_VERSION ) */
-
-        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-        /* If the request did not come from the system call section, do nothing. */
-        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
-        {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
-
-            /* This is not NULL only for the duration of the system call. */
-            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
-
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
-            {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                __asm volatile (
-                    " vpush {s0}         \n" /* Trigger lazy stacking. */
-                    " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                    ::: "memory"
-                    );
-            }
-            else
-            {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
-            }
-
-            /* Make space on the system call stack for the stack frame and
-             * the parameter passed on the stack. We only need to copy one
-             * parameter but we still reserve 2 spaces to keep the stack
-             * double word aligned. */
-            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
-
-            /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
-            {
-                pulSystemCallStack[ i ] = pulTaskStack[ i ];
-            }
-
-            /* Copy the parameter which is passed the stack. */
-            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-            {
-                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
-
-                /* Record if the hardware used padding to force the stack pointer
-                 * to be double word aligned. */
-                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-            }
-            else
-            {
-                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
-
-                /* Record if the hardware used padding to force the stack pointer
-                 * to be double word aligned. */
-                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-            }
-
-            /* Use the pulSystemCallStack in thread mode. */
-            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-
-            /* Raise the privilege for the duration of the system call. */
-            __asm volatile (
-                " mrs r1, control     \n" /* Obtain current control value. */
-                " bic r1, #1          \n" /* Clear nPRIV bit. */
-                " msr control, r1     \n" /* Write back new control value. */
-                ::: "r1", "memory"
-                );
-
-            /* Remember the location where we should copy the stack frame when we exit from
-             * the system call. */
-            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-            /* Store the value of the Link Register before the SVC was raised. We need to
-             * restore it when we exit from the system call. */
-            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-
-            /* We ensure in pxPortInitialiseStack that the system call stack is
-             * double word aligned and therefore, there is no need of padding.
-             * Clear the bit[9] of stacked xPSR. */
-            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-        }
+        __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" );
     }
 
 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@@ -652,24 +578,32 @@ void vPortSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
-
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
-            extern uint32_t * __syscalls_flash_start__;
-            extern uint32_t * __syscalls_flash_end__;
+            extern uint32_t * __privileged_functions_start__;
+            extern uint32_t * __privileged_functions_end__;
         #else
             /* Declaration when these variable are exported from linker scripts. */
-            extern uint32_t __syscalls_flash_start__[];
-            extern uint32_t __syscalls_flash_end__[];
+            extern uint32_t __privileged_functions_start__[];
+            extern uint32_t __privileged_functions_end__[];
         #endif /* #if defined( __ARMCC_VERSION ) */
 
         ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
+        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
 
-        /* If the request did not come from the system call section, do nothing. */
-        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+        /* Checks:
+         * 1. SVC is raised from the privileged code (i.e. application is not
+         *    raising SVC directly). This SVC is only raised from
+         *    vRequestSystemCallExit which is in the privileged code section.
+         * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL -
+         *    this means that we previously entered a system call and the
+         *    application is not attempting to exit without entering a system
+         *    call.
+         */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) &&
+            ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) )
         {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
             pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
 
             if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
@@ -708,8 +642,10 @@ void vPortSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
                 ::: "r1", "memory"
                 );
 
-            /* Restore the stacked link register to what it was at the time of
-             * system call entry. */
+            /* Return to the caller of the System Call entry point (i.e. the
+             * caller of the MPU_<API>). */
+            pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+            /* Ensure that LR has a valid value.*/
             pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
 
             /* If the hardware used padding to force the stack pointer
@@ -875,6 +811,12 @@ BaseType_t xPortStartScheduler( void )
     /* Initialise the critical nesting count ready for the first task. */
     uxCriticalNesting = 0;
 
+    #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+    {
+        xSchedulerRunning = pdTRUE;
+    }
+    #endif
+
     /* Ensure the VFP is enabled - it should be anyway. */
     vPortEnableVFP();
 
@@ -1404,21 +1346,34 @@ BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
         {
             uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
             BaseType_t xAccessGranted = pdFALSE;
-            const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+            const xMPU_SETTINGS * xTaskMpuSettings;
 
-            ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
-            ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
-
-            if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+            if( xSchedulerRunning == pdFALSE )
             {
+                /* Grant access to all the kernel objects before the scheduler
+                 * is started. It is necessary because there is no task running
+                 * yet and therefore, we cannot use the permissions of any
+                 * task. */
                 xAccessGranted = pdTRUE;
             }
             else
             {
-                if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+                ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+                ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+                if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
                 {
                     xAccessGranted = pdTRUE;
                 }
+                else
+                {
+                    if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                    {
+                        xAccessGranted = pdTRUE;
+                    }
+                }
             }
 
             return xAccessGranted;
diff --git a/portable/IAR/ARM_CM4F_MPU/portasm.s b/portable/IAR/ARM_CM4F_MPU/portasm.s
index 5d7b41061..7866d9ee9 100644
--- a/portable/IAR/ARM_CM4F_MPU/portasm.s
+++ b/portable/IAR/ARM_CM4F_MPU/portasm.s
@@ -32,6 +32,7 @@ To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so
 the code is included in C files but excluded by the preprocessor in assembly
 files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
 #include <FreeRTOSConfig.h>
+#include <mpu_syscall_numbers.h>
 
     RSEG    CODE:CODE(2)
     thumb
@@ -40,7 +41,6 @@ files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler.
     EXTERN vTaskSwitchContext
     EXTERN vPortSVCHandler_C
     EXTERN vSystemCallEnter
-    EXTERN vSystemCallEnter_1
     EXTERN vSystemCallExit
 
     PUBLIC xPortPendSVHandler
@@ -64,9 +64,8 @@ files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler.
 #endif
 
 /* These must be in sync with portmacro.h. */
-#define portSVC_SYSTEM_CALL_ENTER   3
-#define portSVC_SYSTEM_CALL_ENTER_1 4
-#define portSVC_SYSTEM_CALL_EXIT    5
+#define portSVC_START_SCHEDULER        100
+#define portSVC_SYSTEM_CALL_EXIT       103
 /*-----------------------------------------------------------*/
 
 xPortPendSVHandler:
@@ -170,10 +169,8 @@ vPortSVCHandler:
 
     ldr r1, [r0, #24]
     ldrb r2, [r1, #-2]
-    cmp r2, #portSVC_SYSTEM_CALL_ENTER
-    beq syscall_enter
-    cmp r2, #portSVC_SYSTEM_CALL_ENTER_1
-    beq syscall_enter_1
+    cmp r2, #NUM_SYSTEM_CALLS
+    blt syscall_enter
     cmp r2, #portSVC_SYSTEM_CALL_EXIT
     beq syscall_exit
     b vPortSVCHandler_C
@@ -182,10 +179,6 @@ vPortSVCHandler:
         mov r1, lr
         b vSystemCallEnter
 
-    syscall_enter_1:
-        mov r1, lr
-        b vSystemCallEnter_1
-
     syscall_exit:
         mov r1, lr
         b vSystemCallExit
@@ -224,7 +217,7 @@ vPortStartFirstTask:
     cpsie f
     dsb
     isb
-    svc 0
+    svc #portSVC_START_SCHEDULER
 
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM4F_MPU/portmacro.h b/portable/IAR/ARM_CM4F_MPU/portmacro.h
index 98b087e11..5b994cca9 100644
--- a/portable/IAR/ARM_CM4F_MPU/portmacro.h
+++ b/portable/IAR/ARM_CM4F_MPU/portmacro.h
@@ -252,12 +252,10 @@ typedef struct MPU_SETTINGS
 /*-----------------------------------------------------------*/
 
 /* SVC numbers for various services. */
-#define portSVC_START_SCHEDULER        0
-#define portSVC_YIELD                  1
-#define portSVC_RAISE_PRIVILEGE        2
-#define portSVC_SYSTEM_CALL_ENTER      3 /* System calls with upto 4 parameters. */
-#define portSVC_SYSTEM_CALL_ENTER_1    4 /* System calls with 5 parameters. */
-#define portSVC_SYSTEM_CALL_EXIT       5
+#define portSVC_START_SCHEDULER        100
+#define portSVC_YIELD                  101
+#define portSVC_RAISE_PRIVILEGE        102
+#define portSVC_SYSTEM_CALL_EXIT       103
 
 /* Scheduler utilities. */
 
diff --git a/portable/IAR/ARM_CM55/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM55/non_secure/mpu_wrappers_v2_asm.S
index 1005dad33..80d5a1c63 100644
--- a/portable/IAR/ARM_CM55/non_secure/mpu_wrappers_v2_asm.S
+++ b/portable/IAR/ARM_CM55/non_secure/mpu_wrappers_v2_asm.S
@@ -32,15 +32,12 @@
 /*-----------------------------------------------------------*/
 
 #include "FreeRTOSConfig.h"
+#include "mpu_syscall_numbers.h"
 
 #ifndef configUSE_MPU_WRAPPERS_V1
     #define configUSE_MPU_WRAPPERS_V1 0
 #endif
 
-/* These must be in sync with portmacro.h. */
-#define portSVC_SYSTEM_CALL_ENTER   4 /* System calls with upto 4 parameters. */
-#define portSVC_SYSTEM_CALL_ENTER_1 5 /* System calls with 5 parameters. */
-#define portSVC_SYSTEM_CALL_EXIT    6
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
@@ -56,10 +53,7 @@ MPU_xTaskDelayUntil:
         b MPU_xTaskDelayUntilImpl
     MPU_xTaskDelayUntil_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskDelayUntilImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskDelayUntil
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskAbortDelay
@@ -73,10 +67,7 @@ MPU_xTaskAbortDelay:
         b MPU_xTaskAbortDelayImpl
     MPU_xTaskAbortDelay_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskAbortDelayImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskAbortDelay
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskDelay
@@ -90,10 +81,7 @@ MPU_vTaskDelay:
         b MPU_vTaskDelayImpl
     MPU_vTaskDelay_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskDelayImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskDelay
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskPriorityGet
@@ -107,10 +95,7 @@ MPU_uxTaskPriorityGet:
         b MPU_uxTaskPriorityGetImpl
     MPU_uxTaskPriorityGet_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskPriorityGetImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskPriorityGet
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_eTaskGetState
@@ -124,10 +109,7 @@ MPU_eTaskGetState:
         b MPU_eTaskGetStateImpl
     MPU_eTaskGetState_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_eTaskGetStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_eTaskGetState
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskGetInfo
@@ -141,10 +123,7 @@ MPU_vTaskGetInfo:
         b MPU_vTaskGetInfoImpl
     MPU_vTaskGetInfo_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskGetInfoImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskGetInfo
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetIdleTaskHandle
@@ -158,10 +137,7 @@ MPU_xTaskGetIdleTaskHandle:
         b MPU_xTaskGetIdleTaskHandleImpl
     MPU_xTaskGetIdleTaskHandle_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetIdleTaskHandleImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetIdleTaskHandle
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskSuspend
@@ -175,10 +151,7 @@ MPU_vTaskSuspend:
         b MPU_vTaskSuspendImpl
     MPU_vTaskSuspend_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSuspendImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskSuspend
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskResume
@@ -192,10 +165,7 @@ MPU_vTaskResume:
         b MPU_vTaskResumeImpl
     MPU_vTaskResume_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskResumeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskResume
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetTickCount
@@ -209,10 +179,7 @@ MPU_xTaskGetTickCount:
         b MPU_xTaskGetTickCountImpl
     MPU_xTaskGetTickCount_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetTickCountImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetTickCount
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskGetNumberOfTasks
@@ -226,10 +193,7 @@ MPU_uxTaskGetNumberOfTasks:
         b MPU_uxTaskGetNumberOfTasksImpl
     MPU_uxTaskGetNumberOfTasks_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetNumberOfTasksImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskGetNumberOfTasks
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGetRunTimeCounter
@@ -243,10 +207,7 @@ MPU_ulTaskGetRunTimeCounter:
         b MPU_ulTaskGetRunTimeCounterImpl
     MPU_ulTaskGetRunTimeCounter_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetRunTimeCounterImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGetRunTimeCounter
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGetRunTimePercent
@@ -260,10 +221,7 @@ MPU_ulTaskGetRunTimePercent:
         b MPU_ulTaskGetRunTimePercentImpl
     MPU_ulTaskGetRunTimePercent_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetRunTimePercentImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGetRunTimePercent
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGetIdleRunTimePercent
@@ -277,10 +235,7 @@ MPU_ulTaskGetIdleRunTimePercent:
         b MPU_ulTaskGetIdleRunTimePercentImpl
     MPU_ulTaskGetIdleRunTimePercent_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetIdleRunTimePercentImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGetIdleRunTimeCounter
@@ -294,10 +249,7 @@ MPU_ulTaskGetIdleRunTimeCounter:
         b MPU_ulTaskGetIdleRunTimeCounterImpl
     MPU_ulTaskGetIdleRunTimeCounter_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetIdleRunTimeCounterImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskSetApplicationTaskTag
@@ -311,10 +263,7 @@ MPU_vTaskSetApplicationTaskTag:
         b MPU_vTaskSetApplicationTaskTagImpl
     MPU_vTaskSetApplicationTaskTag_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSetApplicationTaskTagImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskSetApplicationTaskTag
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetApplicationTaskTag
@@ -328,10 +277,7 @@ MPU_xTaskGetApplicationTaskTag:
         b MPU_xTaskGetApplicationTaskTagImpl
     MPU_xTaskGetApplicationTaskTag_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetApplicationTaskTagImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetApplicationTaskTag
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskSetThreadLocalStoragePointer
@@ -345,10 +291,7 @@ MPU_vTaskSetThreadLocalStoragePointer:
         b MPU_vTaskSetThreadLocalStoragePointerImpl
     MPU_vTaskSetThreadLocalStoragePointer_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSetThreadLocalStoragePointerImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pvTaskGetThreadLocalStoragePointer
@@ -362,10 +305,7 @@ MPU_pvTaskGetThreadLocalStoragePointer:
         b MPU_pvTaskGetThreadLocalStoragePointerImpl
     MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pvTaskGetThreadLocalStoragePointerImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskGetSystemState
@@ -379,10 +319,7 @@ MPU_uxTaskGetSystemState:
         b MPU_uxTaskGetSystemStateImpl
     MPU_uxTaskGetSystemState_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetSystemStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskGetSystemState
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskGetStackHighWaterMark
@@ -396,10 +333,7 @@ MPU_uxTaskGetStackHighWaterMark:
         b MPU_uxTaskGetStackHighWaterMarkImpl
     MPU_uxTaskGetStackHighWaterMark_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetStackHighWaterMarkImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskGetStackHighWaterMark2
@@ -413,10 +347,7 @@ MPU_uxTaskGetStackHighWaterMark2:
         b MPU_uxTaskGetStackHighWaterMark2Impl
     MPU_uxTaskGetStackHighWaterMark2_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetStackHighWaterMark2Impl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetCurrentTaskHandle
@@ -430,10 +361,7 @@ MPU_xTaskGetCurrentTaskHandle:
         b MPU_xTaskGetCurrentTaskHandleImpl
     MPU_xTaskGetCurrentTaskHandle_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetCurrentTaskHandleImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetSchedulerState
@@ -447,10 +375,7 @@ MPU_xTaskGetSchedulerState:
         b MPU_xTaskGetSchedulerStateImpl
     MPU_xTaskGetSchedulerState_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetSchedulerStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetSchedulerState
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskSetTimeOutState
@@ -464,10 +389,7 @@ MPU_vTaskSetTimeOutState:
         b MPU_vTaskSetTimeOutStateImpl
     MPU_vTaskSetTimeOutState_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSetTimeOutStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskSetTimeOutState
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskCheckForTimeOut
@@ -481,14 +403,11 @@ MPU_xTaskCheckForTimeOut:
         b MPU_xTaskCheckForTimeOutImpl
     MPU_xTaskCheckForTimeOut_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskCheckForTimeOutImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskCheckForTimeOut
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xTaskGenericNotify
-MPU_xTaskGenericNotify:
+    PUBLIC MPU_xTaskGenericNotifyEntry
+MPU_xTaskGenericNotifyEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
@@ -498,14 +417,11 @@ MPU_xTaskGenericNotify:
         b MPU_xTaskGenericNotifyImpl
     MPU_xTaskGenericNotify_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTaskGenericNotifyImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGenericNotify
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xTaskGenericNotifyWait
-MPU_xTaskGenericNotifyWait:
+    PUBLIC MPU_xTaskGenericNotifyWaitEntry
+MPU_xTaskGenericNotifyWaitEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
@@ -515,10 +431,7 @@ MPU_xTaskGenericNotifyWait:
         b MPU_xTaskGenericNotifyWaitImpl
     MPU_xTaskGenericNotifyWait_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTaskGenericNotifyWaitImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGenericNotifyWait
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGenericNotifyTake
@@ -532,10 +445,7 @@ MPU_ulTaskGenericNotifyTake:
         b MPU_ulTaskGenericNotifyTakeImpl
     MPU_ulTaskGenericNotifyTake_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGenericNotifyTakeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGenericNotifyTake
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGenericNotifyStateClear
@@ -549,10 +459,7 @@ MPU_xTaskGenericNotifyStateClear:
         b MPU_xTaskGenericNotifyStateClearImpl
     MPU_xTaskGenericNotifyStateClear_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGenericNotifyStateClearImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGenericNotifyStateClear
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGenericNotifyValueClear
@@ -566,10 +473,7 @@ MPU_ulTaskGenericNotifyValueClear:
         b MPU_ulTaskGenericNotifyValueClearImpl
     MPU_ulTaskGenericNotifyValueClear_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGenericNotifyValueClearImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueGenericSend
@@ -583,10 +487,7 @@ MPU_xQueueGenericSend:
         b MPU_xQueueGenericSendImpl
     MPU_xQueueGenericSend_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueGenericSendImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueGenericSend
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxQueueMessagesWaiting
@@ -600,10 +501,7 @@ MPU_uxQueueMessagesWaiting:
         b MPU_uxQueueMessagesWaitingImpl
     MPU_uxQueueMessagesWaiting_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxQueueMessagesWaitingImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxQueueMessagesWaiting
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxQueueSpacesAvailable
@@ -617,10 +515,7 @@ MPU_uxQueueSpacesAvailable:
         b MPU_uxQueueSpacesAvailableImpl
     MPU_uxQueueSpacesAvailable_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxQueueSpacesAvailableImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxQueueSpacesAvailable
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueReceive
@@ -634,10 +529,7 @@ MPU_xQueueReceive:
         b MPU_xQueueReceiveImpl
     MPU_xQueueReceive_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueReceiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueReceive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueuePeek
@@ -651,10 +543,7 @@ MPU_xQueuePeek:
         b MPU_xQueuePeekImpl
     MPU_xQueuePeek_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueuePeekImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueuePeek
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueSemaphoreTake
@@ -668,10 +557,7 @@ MPU_xQueueSemaphoreTake:
         b MPU_xQueueSemaphoreTakeImpl
     MPU_xQueueSemaphoreTake_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueSemaphoreTakeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueSemaphoreTake
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueGetMutexHolder
@@ -685,10 +571,7 @@ MPU_xQueueGetMutexHolder:
         b MPU_xQueueGetMutexHolderImpl
     MPU_xQueueGetMutexHolder_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueGetMutexHolderImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueGetMutexHolder
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueTakeMutexRecursive
@@ -702,10 +585,7 @@ MPU_xQueueTakeMutexRecursive:
         b MPU_xQueueTakeMutexRecursiveImpl
     MPU_xQueueTakeMutexRecursive_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueTakeMutexRecursiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueTakeMutexRecursive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueGiveMutexRecursive
@@ -719,10 +599,7 @@ MPU_xQueueGiveMutexRecursive:
         b MPU_xQueueGiveMutexRecursiveImpl
     MPU_xQueueGiveMutexRecursive_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueGiveMutexRecursiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueGiveMutexRecursive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueSelectFromSet
@@ -736,10 +613,7 @@ MPU_xQueueSelectFromSet:
         b MPU_xQueueSelectFromSetImpl
     MPU_xQueueSelectFromSet_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueSelectFromSetImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueSelectFromSet
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueAddToSet
@@ -753,10 +627,7 @@ MPU_xQueueAddToSet:
         b MPU_xQueueAddToSetImpl
     MPU_xQueueAddToSet_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueAddToSetImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueAddToSet
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vQueueAddToRegistry
@@ -770,10 +641,7 @@ MPU_vQueueAddToRegistry:
         b MPU_vQueueAddToRegistryImpl
     MPU_vQueueAddToRegistry_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vQueueAddToRegistryImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vQueueAddToRegistry
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vQueueUnregisterQueue
@@ -787,10 +655,7 @@ MPU_vQueueUnregisterQueue:
         b MPU_vQueueUnregisterQueueImpl
     MPU_vQueueUnregisterQueue_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vQueueUnregisterQueueImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vQueueUnregisterQueue
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pcQueueGetName
@@ -804,10 +669,7 @@ MPU_pcQueueGetName:
         b MPU_pcQueueGetNameImpl
     MPU_pcQueueGetName_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pcQueueGetNameImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_pcQueueGetName
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pvTimerGetTimerID
@@ -821,10 +683,7 @@ MPU_pvTimerGetTimerID:
         b MPU_pvTimerGetTimerIDImpl
     MPU_pvTimerGetTimerID_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pvTimerGetTimerIDImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_pvTimerGetTimerID
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTimerSetTimerID
@@ -838,10 +697,7 @@ MPU_vTimerSetTimerID:
         b MPU_vTimerSetTimerIDImpl
     MPU_vTimerSetTimerID_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTimerSetTimerIDImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTimerSetTimerID
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerIsTimerActive
@@ -855,10 +711,7 @@ MPU_xTimerIsTimerActive:
         b MPU_xTimerIsTimerActiveImpl
     MPU_xTimerIsTimerActive_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerIsTimerActiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerIsTimerActive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerGetTimerDaemonTaskHandle
@@ -872,14 +725,11 @@ MPU_xTimerGetTimerDaemonTaskHandle:
         b MPU_xTimerGetTimerDaemonTaskHandleImpl
     MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetTimerDaemonTaskHandleImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xTimerGenericCommandFromTask
-MPU_xTimerGenericCommandFromTask:
+    PUBLIC MPU_xTimerGenericCommandFromTaskEntry
+MPU_xTimerGenericCommandFromTaskEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
@@ -889,10 +739,7 @@ MPU_xTimerGenericCommandFromTask:
         b MPU_xTimerGenericCommandFromTaskImpl
     MPU_xTimerGenericCommandFromTask_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTimerGenericCommandFromTaskImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGenericCommandFromTask
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pcTimerGetName
@@ -906,10 +753,7 @@ MPU_pcTimerGetName:
         b MPU_pcTimerGetNameImpl
     MPU_pcTimerGetName_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pcTimerGetNameImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_pcTimerGetName
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTimerSetReloadMode
@@ -923,10 +767,7 @@ MPU_vTimerSetReloadMode:
         b MPU_vTimerSetReloadModeImpl
     MPU_vTimerSetReloadMode_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTimerSetReloadModeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTimerSetReloadMode
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerGetReloadMode
@@ -940,10 +781,7 @@ MPU_xTimerGetReloadMode:
         b MPU_xTimerGetReloadModeImpl
     MPU_xTimerGetReloadMode_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetReloadModeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGetReloadMode
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTimerGetReloadMode
@@ -957,10 +795,7 @@ MPU_uxTimerGetReloadMode:
         b MPU_uxTimerGetReloadModeImpl
     MPU_uxTimerGetReloadMode_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTimerGetReloadModeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTimerGetReloadMode
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerGetPeriod
@@ -974,10 +809,7 @@ MPU_xTimerGetPeriod:
         b MPU_xTimerGetPeriodImpl
     MPU_xTimerGetPeriod_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetPeriodImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGetPeriod
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerGetExpiryTime
@@ -991,14 +823,11 @@ MPU_xTimerGetExpiryTime:
         b MPU_xTimerGetExpiryTimeImpl
     MPU_xTimerGetExpiryTime_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetExpiryTimeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGetExpiryTime
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xEventGroupWaitBits
-MPU_xEventGroupWaitBits:
+    PUBLIC MPU_xEventGroupWaitBitsEntry
+MPU_xEventGroupWaitBitsEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
@@ -1008,10 +837,7 @@ MPU_xEventGroupWaitBits:
         b MPU_xEventGroupWaitBitsImpl
     MPU_xEventGroupWaitBits_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xEventGroupWaitBitsImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xEventGroupWaitBits
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xEventGroupClearBits
@@ -1025,10 +851,7 @@ MPU_xEventGroupClearBits:
         b MPU_xEventGroupClearBitsImpl
     MPU_xEventGroupClearBits_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xEventGroupClearBitsImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xEventGroupClearBits
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xEventGroupSetBits
@@ -1042,10 +865,7 @@ MPU_xEventGroupSetBits:
         b MPU_xEventGroupSetBitsImpl
     MPU_xEventGroupSetBits_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xEventGroupSetBitsImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xEventGroupSetBits
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xEventGroupSync
@@ -1059,10 +879,7 @@ MPU_xEventGroupSync:
         b MPU_xEventGroupSyncImpl
     MPU_xEventGroupSync_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xEventGroupSyncImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xEventGroupSync
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxEventGroupGetNumber
@@ -1076,10 +893,7 @@ MPU_uxEventGroupGetNumber:
         b MPU_uxEventGroupGetNumberImpl
     MPU_uxEventGroupGetNumber_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxEventGroupGetNumberImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxEventGroupGetNumber
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vEventGroupSetNumber
@@ -1093,10 +907,7 @@ MPU_vEventGroupSetNumber:
         b MPU_vEventGroupSetNumberImpl
     MPU_vEventGroupSetNumber_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vEventGroupSetNumberImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vEventGroupSetNumber
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferSend
@@ -1110,10 +921,7 @@ MPU_xStreamBufferSend:
         b MPU_xStreamBufferSendImpl
     MPU_xStreamBufferSend_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferSendImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferSend
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferReceive
@@ -1127,10 +935,7 @@ MPU_xStreamBufferReceive:
         b MPU_xStreamBufferReceiveImpl
     MPU_xStreamBufferReceive_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferReceiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferReceive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferIsFull
@@ -1144,10 +949,7 @@ MPU_xStreamBufferIsFull:
         b MPU_xStreamBufferIsFullImpl
     MPU_xStreamBufferIsFull_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferIsFullImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferIsFull
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferIsEmpty
@@ -1161,10 +963,7 @@ MPU_xStreamBufferIsEmpty:
         b MPU_xStreamBufferIsEmptyImpl
     MPU_xStreamBufferIsEmpty_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferIsEmptyImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferIsEmpty
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferSpacesAvailable
@@ -1178,10 +977,7 @@ MPU_xStreamBufferSpacesAvailable:
         b MPU_xStreamBufferSpacesAvailableImpl
     MPU_xStreamBufferSpacesAvailable_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferSpacesAvailableImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferSpacesAvailable
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferBytesAvailable
@@ -1195,10 +991,7 @@ MPU_xStreamBufferBytesAvailable:
         b MPU_xStreamBufferBytesAvailableImpl
     MPU_xStreamBufferBytesAvailable_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferBytesAvailableImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferBytesAvailable
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferSetTriggerLevel
@@ -1212,10 +1005,7 @@ MPU_xStreamBufferSetTriggerLevel:
         b MPU_xStreamBufferSetTriggerLevelImpl
     MPU_xStreamBufferSetTriggerLevel_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferSetTriggerLevelImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferNextMessageLengthBytes
@@ -1229,10 +1019,7 @@ MPU_xStreamBufferNextMessageLengthBytes:
         b MPU_xStreamBufferNextMessageLengthBytesImpl
     MPU_xStreamBufferNextMessageLengthBytes_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferNextMessageLengthBytesImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes
 /*-----------------------------------------------------------*/
 
 /* Default weak implementations in case one is not available from
diff --git a/portable/IAR/ARM_CM55/non_secure/port.c b/portable/IAR/ARM_CM55/non_secure/port.c
index 52d68d3ea..6a3877894 100644
--- a/portable/IAR/ARM_CM55/non_secure/port.c
+++ b/portable/IAR/ARM_CM55/non_secure/port.c
@@ -35,8 +35,9 @@
 #include "FreeRTOS.h"
 #include "task.h"
 
-/* MPU wrappers includes. */
+/* MPU includes. */
 #include "mpu_wrappers.h"
+#include "mpu_syscall_numbers.h"
 
 /* Portasm includes. */
 #include "portasm.h"
@@ -436,29 +437,22 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
  * @brief Sets up the system call stack so that upon returning from
  * SVC, the system call stack is used.
  *
- * It is used for the system calls with up to 4 parameters.
- *
  * @param pulTaskStack The current SP when the SVC was raised.
  * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ * @param ucSystemCallNumber The system call number of the system call.
  */
     void vSystemCallEnter( uint32_t * pulTaskStack,
-                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
+                           uint32_t ulLR,
+                           uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
- * @brief Sets up the system call stack so that upon returning from
- * SVC, the system call stack is used.
- *
- * It is used for the system calls with 5 parameters.
- *
- * @param pulTaskStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ * @brief Raise SVC for exiting from a system call.
  */
-    void vSystemCallEnter_1( uint32_t * pulTaskStack,
-                             uint32_t ulLR ) PRIVILEGED_FUNCTION;
+    void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
@@ -488,6 +482,15 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+/**
+ * @brief This variable is set to pdTRUE when the scheduler is started.
+ */
+    PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
+
+#endif
+
 /**
  * @brief Each task maintains its own interrupt status in the critical nesting
  * variable.
@@ -1134,15 +1137,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     void vSystemCallEnter( uint32_t * pulTaskStack,
-                           uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
+                           uint32_t ulLR,
+                           uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */
     {
         extern TaskHandle_t pxCurrentTCB;
+        extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ];
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulSystemCallStack;
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
-
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __syscalls_flash_start__;
@@ -1154,17 +1158,27 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         #endif /* #if defined( __ARMCC_VERSION ) */
 
         ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
 
-        /* If the request did not come from the system call section, do nothing. */
+        /* Checks:
+         * 1. SVC is raised from the system call section (i.e. application is
+         *    not raising SVC directly).
+         * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as
+         *    it is non-NULL only during the execution of a system call (i.e.
+         *    between system call enter and exit).
+         * 3. System call is not for a kernel API disabled by the configuration
+         *    in FreeRTOSConfig.h.
+         * 4. We do not need to check that ucSystemCallNumber is within range
+         *    because the assembly SVC handler checks that before calling
+         *    this function.
+         */
         if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) &&
+            ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) &&
+            ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) )
         {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
             pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
 
-            /* This is not NULL only for the duration of the system call. */
-            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
-
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
@@ -1198,9 +1212,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 pulSystemCallStack[ i ] = pulTaskStack[ i ];
             }
 
-            /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
-             * restore it when we exit from the system call. */
+            /* Store the value of the Link Register before the SVC was raised.
+             * It contains the address of the caller of the System Call entry
+             * point (i.e. the caller of the MPU_<API>). We need to restore it
+             * when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            /* Store the value of the PSPLIM register before the SVC was raised.
+             * We need to restore it when we exit from the system call. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
             {
                 __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
@@ -1215,6 +1233,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             }
             #endif
 
+            /* Start executing the system call upon returning from this handler. */
+            pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
+            /* Raise a request to exit from the system call upon finishing the
+             * system call. */
+            pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit;
+
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
             pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
@@ -1251,127 +1275,9 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    void vSystemCallEnter_1( uint32_t * pulTaskStack,
-                             uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
+    void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */
     {
-        extern TaskHandle_t pxCurrentTCB;
-        xMPU_SETTINGS * pxMpuSettings;
-        uint32_t * pulSystemCallStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-
-        #if defined( __ARMCC_VERSION )
-
-            /* Declaration when these variable are defined in code instead of being
-             * exported from linker scripts. */
-            extern uint32_t * __syscalls_flash_start__;
-            extern uint32_t * __syscalls_flash_end__;
-        #else
-            /* Declaration when these variable are exported from linker scripts. */
-            extern uint32_t __syscalls_flash_start__[];
-            extern uint32_t __syscalls_flash_end__[];
-        #endif /* #if defined( __ARMCC_VERSION ) */
-
-        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-        /* If the request did not come from the system call section, do nothing. */
-        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
-        {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
-
-            /* This is not NULL only for the duration of the system call. */
-            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
-
-            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-            {
-                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
-                {
-                    /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
-                    __asm volatile (
-                        " vpush {s0}         \n" /* Trigger lazy stacking. */
-                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                        ::: "memory"
-                        );
-                }
-                else
-                {
-                    /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
-                }
-            }
-            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
-            {
-                ulStackFrameSize = 8;
-            }
-            #endif /* configENABLE_FPU || configENABLE_MVE */
-
-            /* Make space on the system call stack for the stack frame and
-             * the parameter passed on the stack. We only need to copy one
-             * parameter but we still reserve 2 spaces to keep the stack
-             * double word aligned. */
-            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
-
-            /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
-            {
-                pulSystemCallStack[ i ] = pulTaskStack[ i ];
-            }
-
-            /* Copy the parameter which is passed the stack. */
-            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-            {
-                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
-
-                /* Record if the hardware used padding to force the stack pointer
-                 * to be double word aligned. */
-                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-            }
-            else
-            {
-                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
-
-                /* Record if the hardware used padding to force the stack pointer
-                 * to be double word aligned. */
-                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-            }
-
-            /* Store the value of the LR and PSPLIM registers before the SVC was raised.
-             * We need to restore it when we exit from the system call. */
-            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            #if ( portUSE_PSPLIM_REGISTER == 1 )
-            {
-                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-            }
-            #endif
-
-            /* Use the pulSystemCallStack in thread mode. */
-            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            #if ( portUSE_PSPLIM_REGISTER == 1 )
-            {
-                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-            }
-            #endif
-
-            /* Remember the location where we should copy the stack frame when we exit from
-             * the system call. */
-            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-            /* We ensure in pxPortInitialiseStack that the system call stack is
-             * double word aligned and therefore, there is no need of padding.
-             * Clear the bit[9] of stacked xPSR. */
-            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-            /* Raise the privilege for the duration of the system call. */
-            __asm volatile (
-                " mrs r0, control     \n" /* Obtain current control value. */
-                " movs r1, #1         \n" /* r1 = 1. */
-                " bics r0, r1         \n" /* Clear nPRIV bit. */
-                " msr control, r0     \n" /* Write back new control value. */
-                ::: "r0", "r1", "memory"
-                );
-        }
+        __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" );
     }
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@@ -1388,24 +1294,32 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
-
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
-            extern uint32_t * __syscalls_flash_start__;
-            extern uint32_t * __syscalls_flash_end__;
+            extern uint32_t * __privileged_functions_start__;
+            extern uint32_t * __privileged_functions_end__;
         #else
             /* Declaration when these variable are exported from linker scripts. */
-            extern uint32_t __syscalls_flash_start__[];
-            extern uint32_t __syscalls_flash_end__[];
+            extern uint32_t __privileged_functions_start__[];
+            extern uint32_t __privileged_functions_end__[];
         #endif /* #if defined( __ARMCC_VERSION ) */
 
         ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
+        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
 
-        /* If the request did not come from the system call section, do nothing. */
-        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+        /* Checks:
+         * 1. SVC is raised from the privileged code (i.e. application is not
+         *    raising SVC directly). This SVC is only raised from
+         *    vRequestSystemCallExit which is in the privileged code section.
+         * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL -
+         *    this means that we previously entered a system call and the
+         *    application is not attempting to exit without entering a system
+         *    call.
+         */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) &&
+            ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) )
         {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
             pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
 
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
@@ -1444,9 +1358,14 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Use the pulTaskStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
 
-            /* Restore the LR and PSPLIM to what they were at the time of
-             * system call entry. */
+            /* Return to the caller of the System Call entry point (i.e. the
+             * caller of the MPU_<API>). */
+            pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+            /* Ensure that LR has a valid value.*/
             pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+
+            /* Restore the PSPLIM register to what it was at the time of
+             * system call entry. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
             {
                 __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
@@ -1780,6 +1699,12 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     /* Initialize the critical nesting count ready for the first task. */
     ulCriticalNesting = 0;
 
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+    {
+        xSchedulerRunning = pdTRUE;
+    }
+    #endif
+
     /* Start the first task. */
     vStartFirstTask();
 
@@ -2062,7 +1987,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
 
     void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
                                          int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
@@ -2078,10 +2003,10 @@ BaseType_t xPortIsInsideInterrupt( void )
         xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit );
     }
 
-#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
 
     void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
                                           int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
@@ -2097,10 +2022,10 @@ BaseType_t xPortIsInsideInterrupt( void )
         xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit );
     }
 
-#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
 
@@ -2108,21 +2033,34 @@ BaseType_t xPortIsInsideInterrupt( void )
         {
             uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
             BaseType_t xAccessGranted = pdFALSE;
-            const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+            const xMPU_SETTINGS * xTaskMpuSettings;
 
-            ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
-            ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
-
-            if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+            if( xSchedulerRunning == pdFALSE )
             {
+                /* Grant access to all the kernel objects before the scheduler
+                 * is started. It is necessary because there is no task running
+                 * yet and therefore, we cannot use the permissions of any
+                 * task. */
                 xAccessGranted = pdTRUE;
             }
             else
             {
-                if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+                ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+                ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+                if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
                 {
                     xAccessGranted = pdTRUE;
                 }
+                else
+                {
+                    if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                    {
+                        xAccessGranted = pdTRUE;
+                    }
+                }
             }
 
             return xAccessGranted;
@@ -2141,5 +2079,5 @@ BaseType_t xPortIsInsideInterrupt( void )
 
     #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
 
-#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM55/non_secure/portasm.s b/portable/IAR/ARM_CM55/non_secure/portasm.s
index 15e74ffc1..d8f1b1d9a 100644
--- a/portable/IAR/ARM_CM55/non_secure/portasm.s
+++ b/portable/IAR/ARM_CM55/non_secure/portasm.s
@@ -32,6 +32,9 @@ the code is included in C files but excluded by the preprocessor in assembly
 files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
 #include "FreeRTOSConfig.h"
 
+/* System call numbers includes. */
+#include "mpu_syscall_numbers.h"
+
 #ifndef configUSE_MPU_WRAPPERS_V1
     #define configUSE_MPU_WRAPPERS_V1 0
 #endif
@@ -44,7 +47,6 @@ files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler.
     EXTERN SecureContext_LoadContext
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
     EXTERN vSystemCallEnter
-    EXTERN vSystemCallEnter_1
     EXTERN vSystemCallExit
 #endif
 
@@ -86,7 +88,7 @@ vResetPrivilege:
 /*-----------------------------------------------------------*/
 
 vPortAllocateSecureContext:
-    svc 0                                   /* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 0. */
+    svc 100                                 /* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 100. */
     bx lr                                   /* Return. */
 /*-----------------------------------------------------------*/
 
@@ -205,7 +207,7 @@ vStartFirstTask:
     cpsie f
     dsb
     isb
-    svc 2                                   /* System call to start the first task. portSVC_START_SCHEDULER = 2. */
+    svc 102                                 /* System call to start the first task. portSVC_START_SCHEDULER = 102. */
 /*-----------------------------------------------------------*/
 
 ulSetInterruptMask:
@@ -455,11 +457,9 @@ SVC_Handler:
 
     ldr r1, [r0, #24]
     ldrb r2, [r1, #-2]
-    cmp r2, #4          /* portSVC_SYSTEM_CALL_ENTER. */
-    beq syscall_enter
-    cmp r2, #5          /* portSVC_SYSTEM_CALL_ENTER_1. */
-    beq syscall_enter_1
-    cmp r2, #6          /* portSVC_SYSTEM_CALL_EXIT. */
+    cmp r2, #NUM_SYSTEM_CALLS
+    blt syscall_enter
+    cmp r2, #104            /* portSVC_SYSTEM_CALL_EXIT. */
     beq syscall_exit
     b vPortSVCHandler_C
 
@@ -467,10 +467,6 @@ SVC_Handler:
         mov r1, lr
         b vSystemCallEnter
 
-    syscall_enter_1:
-        mov r1, lr
-        b vSystemCallEnter_1
-
     syscall_exit:
         mov r1, lr
         b vSystemCallExit
@@ -493,7 +489,7 @@ vPortFreeSecureContext:
     ldr r1, [r2]                            /* The first item on the stack is the task's xSecureContext. */
     cmp r1, #0                              /* Raise svc if task's xSecureContext is not NULL. */
     it ne
-    svcne 1                                 /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */
+    svcne 101                               /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 101. */
     bx lr                                   /* Return. */
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h
index 60ef37380..672b0dbdc 100644
--- a/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h
@@ -322,14 +322,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 /**
  * @brief SVC numbers.
  */
-#define portSVC_ALLOCATE_SECURE_CONTEXT    0
-#define portSVC_FREE_SECURE_CONTEXT        1
-#define portSVC_START_SCHEDULER            2
-#define portSVC_RAISE_PRIVILEGE            3
-#define portSVC_SYSTEM_CALL_ENTER          4   /* System calls with upto 4 parameters. */
-#define portSVC_SYSTEM_CALL_ENTER_1        5   /* System calls with 5 parameters. */
-#define portSVC_SYSTEM_CALL_EXIT           6
-#define portSVC_YIELD                      7
+#define portSVC_ALLOCATE_SECURE_CONTEXT    100
+#define portSVC_FREE_SECURE_CONTEXT        101
+#define portSVC_START_SCHEDULER            102
+#define portSVC_RAISE_PRIVILEGE            103
+#define portSVC_SYSTEM_CALL_EXIT           104
+#define portSVC_YIELD                      105
 /*-----------------------------------------------------------*/
 
 /**
diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.S
index 1005dad33..80d5a1c63 100644
--- a/portable/IAR/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.S
+++ b/portable/IAR/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.S
@@ -32,15 +32,12 @@
 /*-----------------------------------------------------------*/
 
 #include "FreeRTOSConfig.h"
+#include "mpu_syscall_numbers.h"
 
 #ifndef configUSE_MPU_WRAPPERS_V1
     #define configUSE_MPU_WRAPPERS_V1 0
 #endif
 
-/* These must be in sync with portmacro.h. */
-#define portSVC_SYSTEM_CALL_ENTER   4 /* System calls with upto 4 parameters. */
-#define portSVC_SYSTEM_CALL_ENTER_1 5 /* System calls with 5 parameters. */
-#define portSVC_SYSTEM_CALL_EXIT    6
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
@@ -56,10 +53,7 @@ MPU_xTaskDelayUntil:
         b MPU_xTaskDelayUntilImpl
     MPU_xTaskDelayUntil_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskDelayUntilImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskDelayUntil
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskAbortDelay
@@ -73,10 +67,7 @@ MPU_xTaskAbortDelay:
         b MPU_xTaskAbortDelayImpl
     MPU_xTaskAbortDelay_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskAbortDelayImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskAbortDelay
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskDelay
@@ -90,10 +81,7 @@ MPU_vTaskDelay:
         b MPU_vTaskDelayImpl
     MPU_vTaskDelay_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskDelayImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskDelay
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskPriorityGet
@@ -107,10 +95,7 @@ MPU_uxTaskPriorityGet:
         b MPU_uxTaskPriorityGetImpl
     MPU_uxTaskPriorityGet_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskPriorityGetImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskPriorityGet
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_eTaskGetState
@@ -124,10 +109,7 @@ MPU_eTaskGetState:
         b MPU_eTaskGetStateImpl
     MPU_eTaskGetState_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_eTaskGetStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_eTaskGetState
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskGetInfo
@@ -141,10 +123,7 @@ MPU_vTaskGetInfo:
         b MPU_vTaskGetInfoImpl
     MPU_vTaskGetInfo_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskGetInfoImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskGetInfo
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetIdleTaskHandle
@@ -158,10 +137,7 @@ MPU_xTaskGetIdleTaskHandle:
         b MPU_xTaskGetIdleTaskHandleImpl
     MPU_xTaskGetIdleTaskHandle_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetIdleTaskHandleImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetIdleTaskHandle
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskSuspend
@@ -175,10 +151,7 @@ MPU_vTaskSuspend:
         b MPU_vTaskSuspendImpl
     MPU_vTaskSuspend_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSuspendImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskSuspend
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskResume
@@ -192,10 +165,7 @@ MPU_vTaskResume:
         b MPU_vTaskResumeImpl
     MPU_vTaskResume_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskResumeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskResume
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetTickCount
@@ -209,10 +179,7 @@ MPU_xTaskGetTickCount:
         b MPU_xTaskGetTickCountImpl
     MPU_xTaskGetTickCount_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetTickCountImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetTickCount
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskGetNumberOfTasks
@@ -226,10 +193,7 @@ MPU_uxTaskGetNumberOfTasks:
         b MPU_uxTaskGetNumberOfTasksImpl
     MPU_uxTaskGetNumberOfTasks_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetNumberOfTasksImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskGetNumberOfTasks
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGetRunTimeCounter
@@ -243,10 +207,7 @@ MPU_ulTaskGetRunTimeCounter:
         b MPU_ulTaskGetRunTimeCounterImpl
     MPU_ulTaskGetRunTimeCounter_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetRunTimeCounterImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGetRunTimeCounter
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGetRunTimePercent
@@ -260,10 +221,7 @@ MPU_ulTaskGetRunTimePercent:
         b MPU_ulTaskGetRunTimePercentImpl
     MPU_ulTaskGetRunTimePercent_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetRunTimePercentImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGetRunTimePercent
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGetIdleRunTimePercent
@@ -277,10 +235,7 @@ MPU_ulTaskGetIdleRunTimePercent:
         b MPU_ulTaskGetIdleRunTimePercentImpl
     MPU_ulTaskGetIdleRunTimePercent_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetIdleRunTimePercentImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGetIdleRunTimeCounter
@@ -294,10 +249,7 @@ MPU_ulTaskGetIdleRunTimeCounter:
         b MPU_ulTaskGetIdleRunTimeCounterImpl
     MPU_ulTaskGetIdleRunTimeCounter_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetIdleRunTimeCounterImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskSetApplicationTaskTag
@@ -311,10 +263,7 @@ MPU_vTaskSetApplicationTaskTag:
         b MPU_vTaskSetApplicationTaskTagImpl
     MPU_vTaskSetApplicationTaskTag_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSetApplicationTaskTagImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskSetApplicationTaskTag
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetApplicationTaskTag
@@ -328,10 +277,7 @@ MPU_xTaskGetApplicationTaskTag:
         b MPU_xTaskGetApplicationTaskTagImpl
     MPU_xTaskGetApplicationTaskTag_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetApplicationTaskTagImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetApplicationTaskTag
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskSetThreadLocalStoragePointer
@@ -345,10 +291,7 @@ MPU_vTaskSetThreadLocalStoragePointer:
         b MPU_vTaskSetThreadLocalStoragePointerImpl
     MPU_vTaskSetThreadLocalStoragePointer_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSetThreadLocalStoragePointerImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pvTaskGetThreadLocalStoragePointer
@@ -362,10 +305,7 @@ MPU_pvTaskGetThreadLocalStoragePointer:
         b MPU_pvTaskGetThreadLocalStoragePointerImpl
     MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pvTaskGetThreadLocalStoragePointerImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskGetSystemState
@@ -379,10 +319,7 @@ MPU_uxTaskGetSystemState:
         b MPU_uxTaskGetSystemStateImpl
     MPU_uxTaskGetSystemState_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetSystemStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskGetSystemState
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskGetStackHighWaterMark
@@ -396,10 +333,7 @@ MPU_uxTaskGetStackHighWaterMark:
         b MPU_uxTaskGetStackHighWaterMarkImpl
     MPU_uxTaskGetStackHighWaterMark_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetStackHighWaterMarkImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskGetStackHighWaterMark2
@@ -413,10 +347,7 @@ MPU_uxTaskGetStackHighWaterMark2:
         b MPU_uxTaskGetStackHighWaterMark2Impl
     MPU_uxTaskGetStackHighWaterMark2_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetStackHighWaterMark2Impl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetCurrentTaskHandle
@@ -430,10 +361,7 @@ MPU_xTaskGetCurrentTaskHandle:
         b MPU_xTaskGetCurrentTaskHandleImpl
     MPU_xTaskGetCurrentTaskHandle_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetCurrentTaskHandleImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetSchedulerState
@@ -447,10 +375,7 @@ MPU_xTaskGetSchedulerState:
         b MPU_xTaskGetSchedulerStateImpl
     MPU_xTaskGetSchedulerState_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetSchedulerStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetSchedulerState
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskSetTimeOutState
@@ -464,10 +389,7 @@ MPU_vTaskSetTimeOutState:
         b MPU_vTaskSetTimeOutStateImpl
     MPU_vTaskSetTimeOutState_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSetTimeOutStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskSetTimeOutState
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskCheckForTimeOut
@@ -481,14 +403,11 @@ MPU_xTaskCheckForTimeOut:
         b MPU_xTaskCheckForTimeOutImpl
     MPU_xTaskCheckForTimeOut_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskCheckForTimeOutImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskCheckForTimeOut
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xTaskGenericNotify
-MPU_xTaskGenericNotify:
+    PUBLIC MPU_xTaskGenericNotifyEntry
+MPU_xTaskGenericNotifyEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
@@ -498,14 +417,11 @@ MPU_xTaskGenericNotify:
         b MPU_xTaskGenericNotifyImpl
     MPU_xTaskGenericNotify_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTaskGenericNotifyImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGenericNotify
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xTaskGenericNotifyWait
-MPU_xTaskGenericNotifyWait:
+    PUBLIC MPU_xTaskGenericNotifyWaitEntry
+MPU_xTaskGenericNotifyWaitEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
@@ -515,10 +431,7 @@ MPU_xTaskGenericNotifyWait:
         b MPU_xTaskGenericNotifyWaitImpl
     MPU_xTaskGenericNotifyWait_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTaskGenericNotifyWaitImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGenericNotifyWait
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGenericNotifyTake
@@ -532,10 +445,7 @@ MPU_ulTaskGenericNotifyTake:
         b MPU_ulTaskGenericNotifyTakeImpl
     MPU_ulTaskGenericNotifyTake_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGenericNotifyTakeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGenericNotifyTake
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGenericNotifyStateClear
@@ -549,10 +459,7 @@ MPU_xTaskGenericNotifyStateClear:
         b MPU_xTaskGenericNotifyStateClearImpl
     MPU_xTaskGenericNotifyStateClear_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGenericNotifyStateClearImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGenericNotifyStateClear
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGenericNotifyValueClear
@@ -566,10 +473,7 @@ MPU_ulTaskGenericNotifyValueClear:
         b MPU_ulTaskGenericNotifyValueClearImpl
     MPU_ulTaskGenericNotifyValueClear_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGenericNotifyValueClearImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueGenericSend
@@ -583,10 +487,7 @@ MPU_xQueueGenericSend:
         b MPU_xQueueGenericSendImpl
     MPU_xQueueGenericSend_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueGenericSendImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueGenericSend
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxQueueMessagesWaiting
@@ -600,10 +501,7 @@ MPU_uxQueueMessagesWaiting:
         b MPU_uxQueueMessagesWaitingImpl
     MPU_uxQueueMessagesWaiting_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxQueueMessagesWaitingImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxQueueMessagesWaiting
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxQueueSpacesAvailable
@@ -617,10 +515,7 @@ MPU_uxQueueSpacesAvailable:
         b MPU_uxQueueSpacesAvailableImpl
     MPU_uxQueueSpacesAvailable_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxQueueSpacesAvailableImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxQueueSpacesAvailable
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueReceive
@@ -634,10 +529,7 @@ MPU_xQueueReceive:
         b MPU_xQueueReceiveImpl
     MPU_xQueueReceive_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueReceiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueReceive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueuePeek
@@ -651,10 +543,7 @@ MPU_xQueuePeek:
         b MPU_xQueuePeekImpl
     MPU_xQueuePeek_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueuePeekImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueuePeek
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueSemaphoreTake
@@ -668,10 +557,7 @@ MPU_xQueueSemaphoreTake:
         b MPU_xQueueSemaphoreTakeImpl
     MPU_xQueueSemaphoreTake_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueSemaphoreTakeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueSemaphoreTake
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueGetMutexHolder
@@ -685,10 +571,7 @@ MPU_xQueueGetMutexHolder:
         b MPU_xQueueGetMutexHolderImpl
     MPU_xQueueGetMutexHolder_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueGetMutexHolderImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueGetMutexHolder
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueTakeMutexRecursive
@@ -702,10 +585,7 @@ MPU_xQueueTakeMutexRecursive:
         b MPU_xQueueTakeMutexRecursiveImpl
     MPU_xQueueTakeMutexRecursive_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueTakeMutexRecursiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueTakeMutexRecursive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueGiveMutexRecursive
@@ -719,10 +599,7 @@ MPU_xQueueGiveMutexRecursive:
         b MPU_xQueueGiveMutexRecursiveImpl
     MPU_xQueueGiveMutexRecursive_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueGiveMutexRecursiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueGiveMutexRecursive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueSelectFromSet
@@ -736,10 +613,7 @@ MPU_xQueueSelectFromSet:
         b MPU_xQueueSelectFromSetImpl
     MPU_xQueueSelectFromSet_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueSelectFromSetImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueSelectFromSet
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueAddToSet
@@ -753,10 +627,7 @@ MPU_xQueueAddToSet:
         b MPU_xQueueAddToSetImpl
     MPU_xQueueAddToSet_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueAddToSetImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueAddToSet
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vQueueAddToRegistry
@@ -770,10 +641,7 @@ MPU_vQueueAddToRegistry:
         b MPU_vQueueAddToRegistryImpl
     MPU_vQueueAddToRegistry_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vQueueAddToRegistryImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vQueueAddToRegistry
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vQueueUnregisterQueue
@@ -787,10 +655,7 @@ MPU_vQueueUnregisterQueue:
         b MPU_vQueueUnregisterQueueImpl
     MPU_vQueueUnregisterQueue_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vQueueUnregisterQueueImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vQueueUnregisterQueue
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pcQueueGetName
@@ -804,10 +669,7 @@ MPU_pcQueueGetName:
         b MPU_pcQueueGetNameImpl
     MPU_pcQueueGetName_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pcQueueGetNameImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_pcQueueGetName
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pvTimerGetTimerID
@@ -821,10 +683,7 @@ MPU_pvTimerGetTimerID:
         b MPU_pvTimerGetTimerIDImpl
     MPU_pvTimerGetTimerID_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pvTimerGetTimerIDImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_pvTimerGetTimerID
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTimerSetTimerID
@@ -838,10 +697,7 @@ MPU_vTimerSetTimerID:
         b MPU_vTimerSetTimerIDImpl
     MPU_vTimerSetTimerID_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTimerSetTimerIDImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTimerSetTimerID
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerIsTimerActive
@@ -855,10 +711,7 @@ MPU_xTimerIsTimerActive:
         b MPU_xTimerIsTimerActiveImpl
     MPU_xTimerIsTimerActive_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerIsTimerActiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerIsTimerActive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerGetTimerDaemonTaskHandle
@@ -872,14 +725,11 @@ MPU_xTimerGetTimerDaemonTaskHandle:
         b MPU_xTimerGetTimerDaemonTaskHandleImpl
     MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetTimerDaemonTaskHandleImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xTimerGenericCommandFromTask
-MPU_xTimerGenericCommandFromTask:
+    PUBLIC MPU_xTimerGenericCommandFromTaskEntry
+MPU_xTimerGenericCommandFromTaskEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
@@ -889,10 +739,7 @@ MPU_xTimerGenericCommandFromTask:
         b MPU_xTimerGenericCommandFromTaskImpl
     MPU_xTimerGenericCommandFromTask_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTimerGenericCommandFromTaskImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGenericCommandFromTask
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pcTimerGetName
@@ -906,10 +753,7 @@ MPU_pcTimerGetName:
         b MPU_pcTimerGetNameImpl
     MPU_pcTimerGetName_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pcTimerGetNameImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_pcTimerGetName
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTimerSetReloadMode
@@ -923,10 +767,7 @@ MPU_vTimerSetReloadMode:
         b MPU_vTimerSetReloadModeImpl
     MPU_vTimerSetReloadMode_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTimerSetReloadModeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTimerSetReloadMode
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerGetReloadMode
@@ -940,10 +781,7 @@ MPU_xTimerGetReloadMode:
         b MPU_xTimerGetReloadModeImpl
     MPU_xTimerGetReloadMode_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetReloadModeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGetReloadMode
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTimerGetReloadMode
@@ -957,10 +795,7 @@ MPU_uxTimerGetReloadMode:
         b MPU_uxTimerGetReloadModeImpl
     MPU_uxTimerGetReloadMode_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTimerGetReloadModeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTimerGetReloadMode
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerGetPeriod
@@ -974,10 +809,7 @@ MPU_xTimerGetPeriod:
         b MPU_xTimerGetPeriodImpl
     MPU_xTimerGetPeriod_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetPeriodImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGetPeriod
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerGetExpiryTime
@@ -991,14 +823,11 @@ MPU_xTimerGetExpiryTime:
         b MPU_xTimerGetExpiryTimeImpl
     MPU_xTimerGetExpiryTime_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetExpiryTimeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGetExpiryTime
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xEventGroupWaitBits
-MPU_xEventGroupWaitBits:
+    PUBLIC MPU_xEventGroupWaitBitsEntry
+MPU_xEventGroupWaitBitsEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
@@ -1008,10 +837,7 @@ MPU_xEventGroupWaitBits:
         b MPU_xEventGroupWaitBitsImpl
     MPU_xEventGroupWaitBits_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xEventGroupWaitBitsImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xEventGroupWaitBits
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xEventGroupClearBits
@@ -1025,10 +851,7 @@ MPU_xEventGroupClearBits:
         b MPU_xEventGroupClearBitsImpl
     MPU_xEventGroupClearBits_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xEventGroupClearBitsImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xEventGroupClearBits
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xEventGroupSetBits
@@ -1042,10 +865,7 @@ MPU_xEventGroupSetBits:
         b MPU_xEventGroupSetBitsImpl
     MPU_xEventGroupSetBits_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xEventGroupSetBitsImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xEventGroupSetBits
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xEventGroupSync
@@ -1059,10 +879,7 @@ MPU_xEventGroupSync:
         b MPU_xEventGroupSyncImpl
     MPU_xEventGroupSync_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xEventGroupSyncImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xEventGroupSync
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxEventGroupGetNumber
@@ -1076,10 +893,7 @@ MPU_uxEventGroupGetNumber:
         b MPU_uxEventGroupGetNumberImpl
     MPU_uxEventGroupGetNumber_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxEventGroupGetNumberImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxEventGroupGetNumber
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vEventGroupSetNumber
@@ -1093,10 +907,7 @@ MPU_vEventGroupSetNumber:
         b MPU_vEventGroupSetNumberImpl
     MPU_vEventGroupSetNumber_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vEventGroupSetNumberImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vEventGroupSetNumber
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferSend
@@ -1110,10 +921,7 @@ MPU_xStreamBufferSend:
         b MPU_xStreamBufferSendImpl
     MPU_xStreamBufferSend_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferSendImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferSend
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferReceive
@@ -1127,10 +935,7 @@ MPU_xStreamBufferReceive:
         b MPU_xStreamBufferReceiveImpl
     MPU_xStreamBufferReceive_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferReceiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferReceive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferIsFull
@@ -1144,10 +949,7 @@ MPU_xStreamBufferIsFull:
         b MPU_xStreamBufferIsFullImpl
     MPU_xStreamBufferIsFull_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferIsFullImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferIsFull
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferIsEmpty
@@ -1161,10 +963,7 @@ MPU_xStreamBufferIsEmpty:
         b MPU_xStreamBufferIsEmptyImpl
     MPU_xStreamBufferIsEmpty_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferIsEmptyImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferIsEmpty
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferSpacesAvailable
@@ -1178,10 +977,7 @@ MPU_xStreamBufferSpacesAvailable:
         b MPU_xStreamBufferSpacesAvailableImpl
     MPU_xStreamBufferSpacesAvailable_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferSpacesAvailableImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferSpacesAvailable
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferBytesAvailable
@@ -1195,10 +991,7 @@ MPU_xStreamBufferBytesAvailable:
         b MPU_xStreamBufferBytesAvailableImpl
     MPU_xStreamBufferBytesAvailable_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferBytesAvailableImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferBytesAvailable
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferSetTriggerLevel
@@ -1212,10 +1005,7 @@ MPU_xStreamBufferSetTriggerLevel:
         b MPU_xStreamBufferSetTriggerLevelImpl
     MPU_xStreamBufferSetTriggerLevel_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferSetTriggerLevelImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferNextMessageLengthBytes
@@ -1229,10 +1019,7 @@ MPU_xStreamBufferNextMessageLengthBytes:
         b MPU_xStreamBufferNextMessageLengthBytesImpl
     MPU_xStreamBufferNextMessageLengthBytes_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferNextMessageLengthBytesImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes
 /*-----------------------------------------------------------*/
 
 /* Default weak implementations in case one is not available from
diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/port.c b/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
index 52d68d3ea..6a3877894 100644
--- a/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
@@ -35,8 +35,9 @@
 #include "FreeRTOS.h"
 #include "task.h"
 
-/* MPU wrappers includes. */
+/* MPU includes. */
 #include "mpu_wrappers.h"
+#include "mpu_syscall_numbers.h"
 
 /* Portasm includes. */
 #include "portasm.h"
@@ -436,29 +437,22 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
  * @brief Sets up the system call stack so that upon returning from
  * SVC, the system call stack is used.
  *
- * It is used for the system calls with up to 4 parameters.
- *
  * @param pulTaskStack The current SP when the SVC was raised.
  * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ * @param ucSystemCallNumber The system call number of the system call.
  */
     void vSystemCallEnter( uint32_t * pulTaskStack,
-                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
+                           uint32_t ulLR,
+                           uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
- * @brief Sets up the system call stack so that upon returning from
- * SVC, the system call stack is used.
- *
- * It is used for the system calls with 5 parameters.
- *
- * @param pulTaskStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ * @brief Raise SVC for exiting from a system call.
  */
-    void vSystemCallEnter_1( uint32_t * pulTaskStack,
-                             uint32_t ulLR ) PRIVILEGED_FUNCTION;
+    void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
@@ -488,6 +482,15 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+/**
+ * @brief This variable is set to pdTRUE when the scheduler is started.
+ */
+    PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
+
+#endif
+
 /**
  * @brief Each task maintains its own interrupt status in the critical nesting
  * variable.
@@ -1134,15 +1137,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     void vSystemCallEnter( uint32_t * pulTaskStack,
-                           uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
+                           uint32_t ulLR,
+                           uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */
     {
         extern TaskHandle_t pxCurrentTCB;
+        extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ];
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulSystemCallStack;
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
-
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __syscalls_flash_start__;
@@ -1154,17 +1158,27 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         #endif /* #if defined( __ARMCC_VERSION ) */
 
         ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
 
-        /* If the request did not come from the system call section, do nothing. */
+        /* Checks:
+         * 1. SVC is raised from the system call section (i.e. application is
+         *    not raising SVC directly).
+         * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as
+         *    it is non-NULL only during the execution of a system call (i.e.
+         *    between system call enter and exit).
+         * 3. System call is not for a kernel API disabled by the configuration
+         *    in FreeRTOSConfig.h.
+         * 4. We do not need to check that ucSystemCallNumber is within range
+         *    because the assembly SVC handler checks that before calling
+         *    this function.
+         */
         if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) &&
+            ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) &&
+            ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) )
         {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
             pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
 
-            /* This is not NULL only for the duration of the system call. */
-            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
-
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
@@ -1198,9 +1212,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 pulSystemCallStack[ i ] = pulTaskStack[ i ];
             }
 
-            /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
-             * restore it when we exit from the system call. */
+            /* Store the value of the Link Register before the SVC was raised.
+             * It contains the address of the caller of the System Call entry
+             * point (i.e. the caller of the MPU_<API>). We need to restore it
+             * when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            /* Store the value of the PSPLIM register before the SVC was raised.
+             * We need to restore it when we exit from the system call. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
             {
                 __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
@@ -1215,6 +1233,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             }
             #endif
 
+            /* Start executing the system call upon returning from this handler. */
+            pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
+            /* Raise a request to exit from the system call upon finishing the
+             * system call. */
+            pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit;
+
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
             pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
@@ -1251,127 +1275,9 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    void vSystemCallEnter_1( uint32_t * pulTaskStack,
-                             uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
+    void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */
     {
-        extern TaskHandle_t pxCurrentTCB;
-        xMPU_SETTINGS * pxMpuSettings;
-        uint32_t * pulSystemCallStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-
-        #if defined( __ARMCC_VERSION )
-
-            /* Declaration when these variable are defined in code instead of being
-             * exported from linker scripts. */
-            extern uint32_t * __syscalls_flash_start__;
-            extern uint32_t * __syscalls_flash_end__;
-        #else
-            /* Declaration when these variable are exported from linker scripts. */
-            extern uint32_t __syscalls_flash_start__[];
-            extern uint32_t __syscalls_flash_end__[];
-        #endif /* #if defined( __ARMCC_VERSION ) */
-
-        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-        /* If the request did not come from the system call section, do nothing. */
-        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
-        {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
-
-            /* This is not NULL only for the duration of the system call. */
-            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
-
-            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-            {
-                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
-                {
-                    /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
-                    __asm volatile (
-                        " vpush {s0}         \n" /* Trigger lazy stacking. */
-                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                        ::: "memory"
-                        );
-                }
-                else
-                {
-                    /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
-                }
-            }
-            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
-            {
-                ulStackFrameSize = 8;
-            }
-            #endif /* configENABLE_FPU || configENABLE_MVE */
-
-            /* Make space on the system call stack for the stack frame and
-             * the parameter passed on the stack. We only need to copy one
-             * parameter but we still reserve 2 spaces to keep the stack
-             * double word aligned. */
-            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
-
-            /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
-            {
-                pulSystemCallStack[ i ] = pulTaskStack[ i ];
-            }
-
-            /* Copy the parameter which is passed the stack. */
-            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-            {
-                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
-
-                /* Record if the hardware used padding to force the stack pointer
-                 * to be double word aligned. */
-                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-            }
-            else
-            {
-                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
-
-                /* Record if the hardware used padding to force the stack pointer
-                 * to be double word aligned. */
-                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-            }
-
-            /* Store the value of the LR and PSPLIM registers before the SVC was raised.
-             * We need to restore it when we exit from the system call. */
-            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            #if ( portUSE_PSPLIM_REGISTER == 1 )
-            {
-                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-            }
-            #endif
-
-            /* Use the pulSystemCallStack in thread mode. */
-            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            #if ( portUSE_PSPLIM_REGISTER == 1 )
-            {
-                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-            }
-            #endif
-
-            /* Remember the location where we should copy the stack frame when we exit from
-             * the system call. */
-            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-            /* We ensure in pxPortInitialiseStack that the system call stack is
-             * double word aligned and therefore, there is no need of padding.
-             * Clear the bit[9] of stacked xPSR. */
-            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-            /* Raise the privilege for the duration of the system call. */
-            __asm volatile (
-                " mrs r0, control     \n" /* Obtain current control value. */
-                " movs r1, #1         \n" /* r1 = 1. */
-                " bics r0, r1         \n" /* Clear nPRIV bit. */
-                " msr control, r0     \n" /* Write back new control value. */
-                ::: "r0", "r1", "memory"
-                );
-        }
+        __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" );
     }
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@@ -1388,24 +1294,32 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
-
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
-            extern uint32_t * __syscalls_flash_start__;
-            extern uint32_t * __syscalls_flash_end__;
+            extern uint32_t * __privileged_functions_start__;
+            extern uint32_t * __privileged_functions_end__;
         #else
             /* Declaration when these variable are exported from linker scripts. */
-            extern uint32_t __syscalls_flash_start__[];
-            extern uint32_t __syscalls_flash_end__[];
+            extern uint32_t __privileged_functions_start__[];
+            extern uint32_t __privileged_functions_end__[];
         #endif /* #if defined( __ARMCC_VERSION ) */
 
         ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
+        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
 
-        /* If the request did not come from the system call section, do nothing. */
-        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+        /* Checks:
+         * 1. SVC is raised from the privileged code (i.e. application is not
+         *    raising SVC directly). This SVC is only raised from
+         *    vRequestSystemCallExit which is in the privileged code section.
+         * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL -
+         *    this means that we previously entered a system call and the
+         *    application is not attempting to exit without entering a system
+         *    call.
+         */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) &&
+            ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) )
         {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
             pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
 
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
@@ -1444,9 +1358,14 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Use the pulTaskStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
 
-            /* Restore the LR and PSPLIM to what they were at the time of
-             * system call entry. */
+            /* Return to the caller of the System Call entry point (i.e. the
+             * caller of the MPU_<API>). */
+            pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+            /* Ensure that LR has a valid value.*/
             pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+
+            /* Restore the PSPLIM register to what it was at the time of
+             * system call entry. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
             {
                 __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
@@ -1780,6 +1699,12 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     /* Initialize the critical nesting count ready for the first task. */
     ulCriticalNesting = 0;
 
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+    {
+        xSchedulerRunning = pdTRUE;
+    }
+    #endif
+
     /* Start the first task. */
     vStartFirstTask();
 
@@ -2062,7 +1987,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
 
     void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
                                          int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
@@ -2078,10 +2003,10 @@ BaseType_t xPortIsInsideInterrupt( void )
         xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit );
     }
 
-#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
 
     void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
                                           int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
@@ -2097,10 +2022,10 @@ BaseType_t xPortIsInsideInterrupt( void )
         xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit );
     }
 
-#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
 
@@ -2108,21 +2033,34 @@ BaseType_t xPortIsInsideInterrupt( void )
         {
             uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
             BaseType_t xAccessGranted = pdFALSE;
-            const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+            const xMPU_SETTINGS * xTaskMpuSettings;
 
-            ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
-            ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
-
-            if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+            if( xSchedulerRunning == pdFALSE )
             {
+                /* Grant access to all the kernel objects before the scheduler
+                 * is started. It is necessary because there is no task running
+                 * yet and therefore, we cannot use the permissions of any
+                 * task. */
                 xAccessGranted = pdTRUE;
             }
             else
             {
-                if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+                ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+                ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+                if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
                 {
                     xAccessGranted = pdTRUE;
                 }
+                else
+                {
+                    if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                    {
+                        xAccessGranted = pdTRUE;
+                    }
+                }
             }
 
             return xAccessGranted;
@@ -2141,5 +2079,5 @@ BaseType_t xPortIsInsideInterrupt( void )
 
     #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
 
-#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.s b/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.s
index ec5202527..7cf467d22 100644
--- a/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.s
+++ b/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.s
@@ -32,6 +32,9 @@ the code is included in C files but excluded by the preprocessor in assembly
 files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
 #include "FreeRTOSConfig.h"
 
+/* System call numbers includes. */
+#include "mpu_syscall_numbers.h"
+
 #ifndef configUSE_MPU_WRAPPERS_V1
     #define configUSE_MPU_WRAPPERS_V1 0
 #endif
@@ -41,7 +44,6 @@ files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler.
     EXTERN vPortSVCHandler_C
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
     EXTERN vSystemCallEnter
-    EXTERN vSystemCallEnter_1
     EXTERN vSystemCallExit
 #endif
 
@@ -191,7 +193,7 @@ vStartFirstTask:
     cpsie f
     dsb
     isb
-    svc 2                                   /* System call to start the first task. portSVC_START_SCHEDULER = 2. */
+    svc 102                                 /* System call to start the first task. portSVC_START_SCHEDULER = 102. */
 /*-----------------------------------------------------------*/
 
 ulSetInterruptMask:
@@ -371,11 +373,9 @@ SVC_Handler:
 
     ldr r1, [r0, #24]
     ldrb r2, [r1, #-2]
-    cmp r2, #4          /* portSVC_SYSTEM_CALL_ENTER. */
-    beq syscall_enter
-    cmp r2, #5          /* portSVC_SYSTEM_CALL_ENTER_1. */
-    beq syscall_enter_1
-    cmp r2, #6          /* portSVC_SYSTEM_CALL_EXIT. */
+    cmp r2, #NUM_SYSTEM_CALLS
+    blt syscall_enter
+    cmp r2, #104            /* portSVC_SYSTEM_CALL_EXIT. */
     beq syscall_exit
     b vPortSVCHandler_C
 
@@ -383,10 +383,6 @@ SVC_Handler:
         mov r1, lr
         b vSystemCallEnter
 
-    syscall_enter_1:
-        mov r1, lr
-        b vSystemCallEnter_1
-
     syscall_exit:
         mov r1, lr
         b vSystemCallExit
diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h
index 60ef37380..672b0dbdc 100644
--- a/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h
@@ -322,14 +322,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 /**
  * @brief SVC numbers.
  */
-#define portSVC_ALLOCATE_SECURE_CONTEXT    0
-#define portSVC_FREE_SECURE_CONTEXT        1
-#define portSVC_START_SCHEDULER            2
-#define portSVC_RAISE_PRIVILEGE            3
-#define portSVC_SYSTEM_CALL_ENTER          4   /* System calls with upto 4 parameters. */
-#define portSVC_SYSTEM_CALL_ENTER_1        5   /* System calls with 5 parameters. */
-#define portSVC_SYSTEM_CALL_EXIT           6
-#define portSVC_YIELD                      7
+#define portSVC_ALLOCATE_SECURE_CONTEXT    100
+#define portSVC_FREE_SECURE_CONTEXT        101
+#define portSVC_START_SCHEDULER            102
+#define portSVC_RAISE_PRIVILEGE            103
+#define portSVC_SYSTEM_CALL_EXIT           104
+#define portSVC_YIELD                      105
 /*-----------------------------------------------------------*/
 
 /**
diff --git a/portable/IAR/ARM_CM85/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM85/non_secure/mpu_wrappers_v2_asm.S
index 1005dad33..80d5a1c63 100644
--- a/portable/IAR/ARM_CM85/non_secure/mpu_wrappers_v2_asm.S
+++ b/portable/IAR/ARM_CM85/non_secure/mpu_wrappers_v2_asm.S
@@ -32,15 +32,12 @@
 /*-----------------------------------------------------------*/
 
 #include "FreeRTOSConfig.h"
+#include "mpu_syscall_numbers.h"
 
 #ifndef configUSE_MPU_WRAPPERS_V1
     #define configUSE_MPU_WRAPPERS_V1 0
 #endif
 
-/* These must be in sync with portmacro.h. */
-#define portSVC_SYSTEM_CALL_ENTER   4 /* System calls with upto 4 parameters. */
-#define portSVC_SYSTEM_CALL_ENTER_1 5 /* System calls with 5 parameters. */
-#define portSVC_SYSTEM_CALL_EXIT    6
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
@@ -56,10 +53,7 @@ MPU_xTaskDelayUntil:
         b MPU_xTaskDelayUntilImpl
     MPU_xTaskDelayUntil_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskDelayUntilImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskDelayUntil
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskAbortDelay
@@ -73,10 +67,7 @@ MPU_xTaskAbortDelay:
         b MPU_xTaskAbortDelayImpl
     MPU_xTaskAbortDelay_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskAbortDelayImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskAbortDelay
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskDelay
@@ -90,10 +81,7 @@ MPU_vTaskDelay:
         b MPU_vTaskDelayImpl
     MPU_vTaskDelay_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskDelayImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskDelay
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskPriorityGet
@@ -107,10 +95,7 @@ MPU_uxTaskPriorityGet:
         b MPU_uxTaskPriorityGetImpl
     MPU_uxTaskPriorityGet_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskPriorityGetImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskPriorityGet
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_eTaskGetState
@@ -124,10 +109,7 @@ MPU_eTaskGetState:
         b MPU_eTaskGetStateImpl
     MPU_eTaskGetState_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_eTaskGetStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_eTaskGetState
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskGetInfo
@@ -141,10 +123,7 @@ MPU_vTaskGetInfo:
         b MPU_vTaskGetInfoImpl
     MPU_vTaskGetInfo_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskGetInfoImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskGetInfo
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetIdleTaskHandle
@@ -158,10 +137,7 @@ MPU_xTaskGetIdleTaskHandle:
         b MPU_xTaskGetIdleTaskHandleImpl
     MPU_xTaskGetIdleTaskHandle_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetIdleTaskHandleImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetIdleTaskHandle
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskSuspend
@@ -175,10 +151,7 @@ MPU_vTaskSuspend:
         b MPU_vTaskSuspendImpl
     MPU_vTaskSuspend_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSuspendImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskSuspend
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskResume
@@ -192,10 +165,7 @@ MPU_vTaskResume:
         b MPU_vTaskResumeImpl
     MPU_vTaskResume_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskResumeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskResume
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetTickCount
@@ -209,10 +179,7 @@ MPU_xTaskGetTickCount:
         b MPU_xTaskGetTickCountImpl
     MPU_xTaskGetTickCount_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetTickCountImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetTickCount
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskGetNumberOfTasks
@@ -226,10 +193,7 @@ MPU_uxTaskGetNumberOfTasks:
         b MPU_uxTaskGetNumberOfTasksImpl
     MPU_uxTaskGetNumberOfTasks_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetNumberOfTasksImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskGetNumberOfTasks
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGetRunTimeCounter
@@ -243,10 +207,7 @@ MPU_ulTaskGetRunTimeCounter:
         b MPU_ulTaskGetRunTimeCounterImpl
     MPU_ulTaskGetRunTimeCounter_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetRunTimeCounterImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGetRunTimeCounter
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGetRunTimePercent
@@ -260,10 +221,7 @@ MPU_ulTaskGetRunTimePercent:
         b MPU_ulTaskGetRunTimePercentImpl
     MPU_ulTaskGetRunTimePercent_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetRunTimePercentImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGetRunTimePercent
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGetIdleRunTimePercent
@@ -277,10 +235,7 @@ MPU_ulTaskGetIdleRunTimePercent:
         b MPU_ulTaskGetIdleRunTimePercentImpl
     MPU_ulTaskGetIdleRunTimePercent_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetIdleRunTimePercentImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGetIdleRunTimeCounter
@@ -294,10 +249,7 @@ MPU_ulTaskGetIdleRunTimeCounter:
         b MPU_ulTaskGetIdleRunTimeCounterImpl
     MPU_ulTaskGetIdleRunTimeCounter_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetIdleRunTimeCounterImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskSetApplicationTaskTag
@@ -311,10 +263,7 @@ MPU_vTaskSetApplicationTaskTag:
         b MPU_vTaskSetApplicationTaskTagImpl
     MPU_vTaskSetApplicationTaskTag_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSetApplicationTaskTagImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskSetApplicationTaskTag
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetApplicationTaskTag
@@ -328,10 +277,7 @@ MPU_xTaskGetApplicationTaskTag:
         b MPU_xTaskGetApplicationTaskTagImpl
     MPU_xTaskGetApplicationTaskTag_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetApplicationTaskTagImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetApplicationTaskTag
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskSetThreadLocalStoragePointer
@@ -345,10 +291,7 @@ MPU_vTaskSetThreadLocalStoragePointer:
         b MPU_vTaskSetThreadLocalStoragePointerImpl
     MPU_vTaskSetThreadLocalStoragePointer_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSetThreadLocalStoragePointerImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pvTaskGetThreadLocalStoragePointer
@@ -362,10 +305,7 @@ MPU_pvTaskGetThreadLocalStoragePointer:
         b MPU_pvTaskGetThreadLocalStoragePointerImpl
     MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pvTaskGetThreadLocalStoragePointerImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskGetSystemState
@@ -379,10 +319,7 @@ MPU_uxTaskGetSystemState:
         b MPU_uxTaskGetSystemStateImpl
     MPU_uxTaskGetSystemState_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetSystemStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskGetSystemState
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskGetStackHighWaterMark
@@ -396,10 +333,7 @@ MPU_uxTaskGetStackHighWaterMark:
         b MPU_uxTaskGetStackHighWaterMarkImpl
     MPU_uxTaskGetStackHighWaterMark_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetStackHighWaterMarkImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskGetStackHighWaterMark2
@@ -413,10 +347,7 @@ MPU_uxTaskGetStackHighWaterMark2:
         b MPU_uxTaskGetStackHighWaterMark2Impl
     MPU_uxTaskGetStackHighWaterMark2_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetStackHighWaterMark2Impl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetCurrentTaskHandle
@@ -430,10 +361,7 @@ MPU_xTaskGetCurrentTaskHandle:
         b MPU_xTaskGetCurrentTaskHandleImpl
     MPU_xTaskGetCurrentTaskHandle_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetCurrentTaskHandleImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetSchedulerState
@@ -447,10 +375,7 @@ MPU_xTaskGetSchedulerState:
         b MPU_xTaskGetSchedulerStateImpl
     MPU_xTaskGetSchedulerState_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetSchedulerStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetSchedulerState
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskSetTimeOutState
@@ -464,10 +389,7 @@ MPU_vTaskSetTimeOutState:
         b MPU_vTaskSetTimeOutStateImpl
     MPU_vTaskSetTimeOutState_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSetTimeOutStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskSetTimeOutState
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskCheckForTimeOut
@@ -481,14 +403,11 @@ MPU_xTaskCheckForTimeOut:
         b MPU_xTaskCheckForTimeOutImpl
     MPU_xTaskCheckForTimeOut_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskCheckForTimeOutImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskCheckForTimeOut
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xTaskGenericNotify
-MPU_xTaskGenericNotify:
+    PUBLIC MPU_xTaskGenericNotifyEntry
+MPU_xTaskGenericNotifyEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
@@ -498,14 +417,11 @@ MPU_xTaskGenericNotify:
         b MPU_xTaskGenericNotifyImpl
     MPU_xTaskGenericNotify_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTaskGenericNotifyImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGenericNotify
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xTaskGenericNotifyWait
-MPU_xTaskGenericNotifyWait:
+    PUBLIC MPU_xTaskGenericNotifyWaitEntry
+MPU_xTaskGenericNotifyWaitEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
@@ -515,10 +431,7 @@ MPU_xTaskGenericNotifyWait:
         b MPU_xTaskGenericNotifyWaitImpl
     MPU_xTaskGenericNotifyWait_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTaskGenericNotifyWaitImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGenericNotifyWait
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGenericNotifyTake
@@ -532,10 +445,7 @@ MPU_ulTaskGenericNotifyTake:
         b MPU_ulTaskGenericNotifyTakeImpl
     MPU_ulTaskGenericNotifyTake_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGenericNotifyTakeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGenericNotifyTake
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGenericNotifyStateClear
@@ -549,10 +459,7 @@ MPU_xTaskGenericNotifyStateClear:
         b MPU_xTaskGenericNotifyStateClearImpl
     MPU_xTaskGenericNotifyStateClear_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGenericNotifyStateClearImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGenericNotifyStateClear
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGenericNotifyValueClear
@@ -566,10 +473,7 @@ MPU_ulTaskGenericNotifyValueClear:
         b MPU_ulTaskGenericNotifyValueClearImpl
     MPU_ulTaskGenericNotifyValueClear_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGenericNotifyValueClearImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueGenericSend
@@ -583,10 +487,7 @@ MPU_xQueueGenericSend:
         b MPU_xQueueGenericSendImpl
     MPU_xQueueGenericSend_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueGenericSendImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueGenericSend
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxQueueMessagesWaiting
@@ -600,10 +501,7 @@ MPU_uxQueueMessagesWaiting:
         b MPU_uxQueueMessagesWaitingImpl
     MPU_uxQueueMessagesWaiting_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxQueueMessagesWaitingImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxQueueMessagesWaiting
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxQueueSpacesAvailable
@@ -617,10 +515,7 @@ MPU_uxQueueSpacesAvailable:
         b MPU_uxQueueSpacesAvailableImpl
     MPU_uxQueueSpacesAvailable_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxQueueSpacesAvailableImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxQueueSpacesAvailable
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueReceive
@@ -634,10 +529,7 @@ MPU_xQueueReceive:
         b MPU_xQueueReceiveImpl
     MPU_xQueueReceive_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueReceiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueReceive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueuePeek
@@ -651,10 +543,7 @@ MPU_xQueuePeek:
         b MPU_xQueuePeekImpl
     MPU_xQueuePeek_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueuePeekImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueuePeek
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueSemaphoreTake
@@ -668,10 +557,7 @@ MPU_xQueueSemaphoreTake:
         b MPU_xQueueSemaphoreTakeImpl
     MPU_xQueueSemaphoreTake_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueSemaphoreTakeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueSemaphoreTake
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueGetMutexHolder
@@ -685,10 +571,7 @@ MPU_xQueueGetMutexHolder:
         b MPU_xQueueGetMutexHolderImpl
     MPU_xQueueGetMutexHolder_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueGetMutexHolderImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueGetMutexHolder
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueTakeMutexRecursive
@@ -702,10 +585,7 @@ MPU_xQueueTakeMutexRecursive:
         b MPU_xQueueTakeMutexRecursiveImpl
     MPU_xQueueTakeMutexRecursive_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueTakeMutexRecursiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueTakeMutexRecursive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueGiveMutexRecursive
@@ -719,10 +599,7 @@ MPU_xQueueGiveMutexRecursive:
         b MPU_xQueueGiveMutexRecursiveImpl
     MPU_xQueueGiveMutexRecursive_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueGiveMutexRecursiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueGiveMutexRecursive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueSelectFromSet
@@ -736,10 +613,7 @@ MPU_xQueueSelectFromSet:
         b MPU_xQueueSelectFromSetImpl
     MPU_xQueueSelectFromSet_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueSelectFromSetImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueSelectFromSet
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueAddToSet
@@ -753,10 +627,7 @@ MPU_xQueueAddToSet:
         b MPU_xQueueAddToSetImpl
     MPU_xQueueAddToSet_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueAddToSetImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueAddToSet
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vQueueAddToRegistry
@@ -770,10 +641,7 @@ MPU_vQueueAddToRegistry:
         b MPU_vQueueAddToRegistryImpl
     MPU_vQueueAddToRegistry_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vQueueAddToRegistryImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vQueueAddToRegistry
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vQueueUnregisterQueue
@@ -787,10 +655,7 @@ MPU_vQueueUnregisterQueue:
         b MPU_vQueueUnregisterQueueImpl
     MPU_vQueueUnregisterQueue_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vQueueUnregisterQueueImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vQueueUnregisterQueue
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pcQueueGetName
@@ -804,10 +669,7 @@ MPU_pcQueueGetName:
         b MPU_pcQueueGetNameImpl
     MPU_pcQueueGetName_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pcQueueGetNameImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_pcQueueGetName
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pvTimerGetTimerID
@@ -821,10 +683,7 @@ MPU_pvTimerGetTimerID:
         b MPU_pvTimerGetTimerIDImpl
     MPU_pvTimerGetTimerID_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pvTimerGetTimerIDImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_pvTimerGetTimerID
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTimerSetTimerID
@@ -838,10 +697,7 @@ MPU_vTimerSetTimerID:
         b MPU_vTimerSetTimerIDImpl
     MPU_vTimerSetTimerID_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTimerSetTimerIDImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTimerSetTimerID
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerIsTimerActive
@@ -855,10 +711,7 @@ MPU_xTimerIsTimerActive:
         b MPU_xTimerIsTimerActiveImpl
     MPU_xTimerIsTimerActive_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerIsTimerActiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerIsTimerActive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerGetTimerDaemonTaskHandle
@@ -872,14 +725,11 @@ MPU_xTimerGetTimerDaemonTaskHandle:
         b MPU_xTimerGetTimerDaemonTaskHandleImpl
     MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetTimerDaemonTaskHandleImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xTimerGenericCommandFromTask
-MPU_xTimerGenericCommandFromTask:
+    PUBLIC MPU_xTimerGenericCommandFromTaskEntry
+MPU_xTimerGenericCommandFromTaskEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
@@ -889,10 +739,7 @@ MPU_xTimerGenericCommandFromTask:
         b MPU_xTimerGenericCommandFromTaskImpl
     MPU_xTimerGenericCommandFromTask_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTimerGenericCommandFromTaskImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGenericCommandFromTask
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pcTimerGetName
@@ -906,10 +753,7 @@ MPU_pcTimerGetName:
         b MPU_pcTimerGetNameImpl
     MPU_pcTimerGetName_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pcTimerGetNameImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_pcTimerGetName
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTimerSetReloadMode
@@ -923,10 +767,7 @@ MPU_vTimerSetReloadMode:
         b MPU_vTimerSetReloadModeImpl
     MPU_vTimerSetReloadMode_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTimerSetReloadModeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTimerSetReloadMode
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerGetReloadMode
@@ -940,10 +781,7 @@ MPU_xTimerGetReloadMode:
         b MPU_xTimerGetReloadModeImpl
     MPU_xTimerGetReloadMode_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetReloadModeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGetReloadMode
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTimerGetReloadMode
@@ -957,10 +795,7 @@ MPU_uxTimerGetReloadMode:
         b MPU_uxTimerGetReloadModeImpl
     MPU_uxTimerGetReloadMode_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTimerGetReloadModeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTimerGetReloadMode
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerGetPeriod
@@ -974,10 +809,7 @@ MPU_xTimerGetPeriod:
         b MPU_xTimerGetPeriodImpl
     MPU_xTimerGetPeriod_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetPeriodImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGetPeriod
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerGetExpiryTime
@@ -991,14 +823,11 @@ MPU_xTimerGetExpiryTime:
         b MPU_xTimerGetExpiryTimeImpl
     MPU_xTimerGetExpiryTime_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetExpiryTimeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGetExpiryTime
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xEventGroupWaitBits
-MPU_xEventGroupWaitBits:
+    PUBLIC MPU_xEventGroupWaitBitsEntry
+MPU_xEventGroupWaitBitsEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
@@ -1008,10 +837,7 @@ MPU_xEventGroupWaitBits:
         b MPU_xEventGroupWaitBitsImpl
     MPU_xEventGroupWaitBits_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xEventGroupWaitBitsImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xEventGroupWaitBits
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xEventGroupClearBits
@@ -1025,10 +851,7 @@ MPU_xEventGroupClearBits:
         b MPU_xEventGroupClearBitsImpl
     MPU_xEventGroupClearBits_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xEventGroupClearBitsImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xEventGroupClearBits
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xEventGroupSetBits
@@ -1042,10 +865,7 @@ MPU_xEventGroupSetBits:
         b MPU_xEventGroupSetBitsImpl
     MPU_xEventGroupSetBits_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xEventGroupSetBitsImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xEventGroupSetBits
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xEventGroupSync
@@ -1059,10 +879,7 @@ MPU_xEventGroupSync:
         b MPU_xEventGroupSyncImpl
     MPU_xEventGroupSync_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xEventGroupSyncImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xEventGroupSync
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxEventGroupGetNumber
@@ -1076,10 +893,7 @@ MPU_uxEventGroupGetNumber:
         b MPU_uxEventGroupGetNumberImpl
     MPU_uxEventGroupGetNumber_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxEventGroupGetNumberImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxEventGroupGetNumber
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vEventGroupSetNumber
@@ -1093,10 +907,7 @@ MPU_vEventGroupSetNumber:
         b MPU_vEventGroupSetNumberImpl
     MPU_vEventGroupSetNumber_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vEventGroupSetNumberImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vEventGroupSetNumber
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferSend
@@ -1110,10 +921,7 @@ MPU_xStreamBufferSend:
         b MPU_xStreamBufferSendImpl
     MPU_xStreamBufferSend_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferSendImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferSend
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferReceive
@@ -1127,10 +935,7 @@ MPU_xStreamBufferReceive:
         b MPU_xStreamBufferReceiveImpl
     MPU_xStreamBufferReceive_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferReceiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferReceive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferIsFull
@@ -1144,10 +949,7 @@ MPU_xStreamBufferIsFull:
         b MPU_xStreamBufferIsFullImpl
     MPU_xStreamBufferIsFull_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferIsFullImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferIsFull
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferIsEmpty
@@ -1161,10 +963,7 @@ MPU_xStreamBufferIsEmpty:
         b MPU_xStreamBufferIsEmptyImpl
     MPU_xStreamBufferIsEmpty_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferIsEmptyImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferIsEmpty
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferSpacesAvailable
@@ -1178,10 +977,7 @@ MPU_xStreamBufferSpacesAvailable:
         b MPU_xStreamBufferSpacesAvailableImpl
     MPU_xStreamBufferSpacesAvailable_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferSpacesAvailableImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferSpacesAvailable
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferBytesAvailable
@@ -1195,10 +991,7 @@ MPU_xStreamBufferBytesAvailable:
         b MPU_xStreamBufferBytesAvailableImpl
     MPU_xStreamBufferBytesAvailable_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferBytesAvailableImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferBytesAvailable
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferSetTriggerLevel
@@ -1212,10 +1005,7 @@ MPU_xStreamBufferSetTriggerLevel:
         b MPU_xStreamBufferSetTriggerLevelImpl
     MPU_xStreamBufferSetTriggerLevel_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferSetTriggerLevelImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferNextMessageLengthBytes
@@ -1229,10 +1019,7 @@ MPU_xStreamBufferNextMessageLengthBytes:
         b MPU_xStreamBufferNextMessageLengthBytesImpl
     MPU_xStreamBufferNextMessageLengthBytes_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferNextMessageLengthBytesImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes
 /*-----------------------------------------------------------*/
 
 /* Default weak implementations in case one is not available from
diff --git a/portable/IAR/ARM_CM85/non_secure/port.c b/portable/IAR/ARM_CM85/non_secure/port.c
index 52d68d3ea..6a3877894 100644
--- a/portable/IAR/ARM_CM85/non_secure/port.c
+++ b/portable/IAR/ARM_CM85/non_secure/port.c
@@ -35,8 +35,9 @@
 #include "FreeRTOS.h"
 #include "task.h"
 
-/* MPU wrappers includes. */
+/* MPU includes. */
 #include "mpu_wrappers.h"
+#include "mpu_syscall_numbers.h"
 
 /* Portasm includes. */
 #include "portasm.h"
@@ -436,29 +437,22 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
  * @brief Sets up the system call stack so that upon returning from
  * SVC, the system call stack is used.
  *
- * It is used for the system calls with up to 4 parameters.
- *
  * @param pulTaskStack The current SP when the SVC was raised.
  * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ * @param ucSystemCallNumber The system call number of the system call.
  */
     void vSystemCallEnter( uint32_t * pulTaskStack,
-                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
+                           uint32_t ulLR,
+                           uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
- * @brief Sets up the system call stack so that upon returning from
- * SVC, the system call stack is used.
- *
- * It is used for the system calls with 5 parameters.
- *
- * @param pulTaskStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ * @brief Raise SVC for exiting from a system call.
  */
-    void vSystemCallEnter_1( uint32_t * pulTaskStack,
-                             uint32_t ulLR ) PRIVILEGED_FUNCTION;
+    void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
@@ -488,6 +482,15 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+/**
+ * @brief This variable is set to pdTRUE when the scheduler is started.
+ */
+    PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
+
+#endif
+
 /**
  * @brief Each task maintains its own interrupt status in the critical nesting
  * variable.
@@ -1134,15 +1137,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     void vSystemCallEnter( uint32_t * pulTaskStack,
-                           uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
+                           uint32_t ulLR,
+                           uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */
     {
         extern TaskHandle_t pxCurrentTCB;
+        extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ];
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulSystemCallStack;
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
-
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __syscalls_flash_start__;
@@ -1154,17 +1158,27 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         #endif /* #if defined( __ARMCC_VERSION ) */
 
         ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
 
-        /* If the request did not come from the system call section, do nothing. */
+        /* Checks:
+         * 1. SVC is raised from the system call section (i.e. application is
+         *    not raising SVC directly).
+         * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as
+         *    it is non-NULL only during the execution of a system call (i.e.
+         *    between system call enter and exit).
+         * 3. System call is not for a kernel API disabled by the configuration
+         *    in FreeRTOSConfig.h.
+         * 4. We do not need to check that ucSystemCallNumber is within range
+         *    because the assembly SVC handler checks that before calling
+         *    this function.
+         */
         if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) &&
+            ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) &&
+            ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) )
         {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
             pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
 
-            /* This is not NULL only for the duration of the system call. */
-            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
-
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
@@ -1198,9 +1212,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 pulSystemCallStack[ i ] = pulTaskStack[ i ];
             }
 
-            /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
-             * restore it when we exit from the system call. */
+            /* Store the value of the Link Register before the SVC was raised.
+             * It contains the address of the caller of the System Call entry
+             * point (i.e. the caller of the MPU_<API>). We need to restore it
+             * when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            /* Store the value of the PSPLIM register before the SVC was raised.
+             * We need to restore it when we exit from the system call. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
             {
                 __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
@@ -1215,6 +1233,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             }
             #endif
 
+            /* Start executing the system call upon returning from this handler. */
+            pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
+            /* Raise a request to exit from the system call upon finishing the
+             * system call. */
+            pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit;
+
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
             pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
@@ -1251,127 +1275,9 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    void vSystemCallEnter_1( uint32_t * pulTaskStack,
-                             uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
+    void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */
     {
-        extern TaskHandle_t pxCurrentTCB;
-        xMPU_SETTINGS * pxMpuSettings;
-        uint32_t * pulSystemCallStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-
-        #if defined( __ARMCC_VERSION )
-
-            /* Declaration when these variable are defined in code instead of being
-             * exported from linker scripts. */
-            extern uint32_t * __syscalls_flash_start__;
-            extern uint32_t * __syscalls_flash_end__;
-        #else
-            /* Declaration when these variable are exported from linker scripts. */
-            extern uint32_t __syscalls_flash_start__[];
-            extern uint32_t __syscalls_flash_end__[];
-        #endif /* #if defined( __ARMCC_VERSION ) */
-
-        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-        /* If the request did not come from the system call section, do nothing. */
-        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
-        {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
-
-            /* This is not NULL only for the duration of the system call. */
-            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
-
-            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-            {
-                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
-                {
-                    /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
-                    __asm volatile (
-                        " vpush {s0}         \n" /* Trigger lazy stacking. */
-                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                        ::: "memory"
-                        );
-                }
-                else
-                {
-                    /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
-                }
-            }
-            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
-            {
-                ulStackFrameSize = 8;
-            }
-            #endif /* configENABLE_FPU || configENABLE_MVE */
-
-            /* Make space on the system call stack for the stack frame and
-             * the parameter passed on the stack. We only need to copy one
-             * parameter but we still reserve 2 spaces to keep the stack
-             * double word aligned. */
-            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
-
-            /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
-            {
-                pulSystemCallStack[ i ] = pulTaskStack[ i ];
-            }
-
-            /* Copy the parameter which is passed the stack. */
-            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-            {
-                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
-
-                /* Record if the hardware used padding to force the stack pointer
-                 * to be double word aligned. */
-                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-            }
-            else
-            {
-                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
-
-                /* Record if the hardware used padding to force the stack pointer
-                 * to be double word aligned. */
-                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-            }
-
-            /* Store the value of the LR and PSPLIM registers before the SVC was raised.
-             * We need to restore it when we exit from the system call. */
-            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            #if ( portUSE_PSPLIM_REGISTER == 1 )
-            {
-                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-            }
-            #endif
-
-            /* Use the pulSystemCallStack in thread mode. */
-            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            #if ( portUSE_PSPLIM_REGISTER == 1 )
-            {
-                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-            }
-            #endif
-
-            /* Remember the location where we should copy the stack frame when we exit from
-             * the system call. */
-            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-            /* We ensure in pxPortInitialiseStack that the system call stack is
-             * double word aligned and therefore, there is no need of padding.
-             * Clear the bit[9] of stacked xPSR. */
-            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-            /* Raise the privilege for the duration of the system call. */
-            __asm volatile (
-                " mrs r0, control     \n" /* Obtain current control value. */
-                " movs r1, #1         \n" /* r1 = 1. */
-                " bics r0, r1         \n" /* Clear nPRIV bit. */
-                " msr control, r0     \n" /* Write back new control value. */
-                ::: "r0", "r1", "memory"
-                );
-        }
+        __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" );
     }
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@@ -1388,24 +1294,32 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
-
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
-            extern uint32_t * __syscalls_flash_start__;
-            extern uint32_t * __syscalls_flash_end__;
+            extern uint32_t * __privileged_functions_start__;
+            extern uint32_t * __privileged_functions_end__;
         #else
             /* Declaration when these variable are exported from linker scripts. */
-            extern uint32_t __syscalls_flash_start__[];
-            extern uint32_t __syscalls_flash_end__[];
+            extern uint32_t __privileged_functions_start__[];
+            extern uint32_t __privileged_functions_end__[];
         #endif /* #if defined( __ARMCC_VERSION ) */
 
         ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
+        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
 
-        /* If the request did not come from the system call section, do nothing. */
-        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+        /* Checks:
+         * 1. SVC is raised from the privileged code (i.e. application is not
+         *    raising SVC directly). This SVC is only raised from
+         *    vRequestSystemCallExit which is in the privileged code section.
+         * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL -
+         *    this means that we previously entered a system call and the
+         *    application is not attempting to exit without entering a system
+         *    call.
+         */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) &&
+            ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) )
         {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
             pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
 
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
@@ -1444,9 +1358,14 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Use the pulTaskStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
 
-            /* Restore the LR and PSPLIM to what they were at the time of
-             * system call entry. */
+            /* Return to the caller of the System Call entry point (i.e. the
+             * caller of the MPU_<API>). */
+            pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+            /* Ensure that LR has a valid value.*/
             pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+
+            /* Restore the PSPLIM register to what it was at the time of
+             * system call entry. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
             {
                 __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
@@ -1780,6 +1699,12 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     /* Initialize the critical nesting count ready for the first task. */
     ulCriticalNesting = 0;
 
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+    {
+        xSchedulerRunning = pdTRUE;
+    }
+    #endif
+
     /* Start the first task. */
     vStartFirstTask();
 
@@ -2062,7 +1987,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
 
     void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
                                          int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
@@ -2078,10 +2003,10 @@ BaseType_t xPortIsInsideInterrupt( void )
         xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit );
     }
 
-#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
 
     void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
                                           int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
@@ -2097,10 +2022,10 @@ BaseType_t xPortIsInsideInterrupt( void )
         xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit );
     }
 
-#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
 
@@ -2108,21 +2033,34 @@ BaseType_t xPortIsInsideInterrupt( void )
         {
             uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
             BaseType_t xAccessGranted = pdFALSE;
-            const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+            const xMPU_SETTINGS * xTaskMpuSettings;
 
-            ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
-            ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
-
-            if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+            if( xSchedulerRunning == pdFALSE )
             {
+                /* Grant access to all the kernel objects before the scheduler
+                 * is started. It is necessary because there is no task running
+                 * yet and therefore, we cannot use the permissions of any
+                 * task. */
                 xAccessGranted = pdTRUE;
             }
             else
             {
-                if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+                ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+                ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+                if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
                 {
                     xAccessGranted = pdTRUE;
                 }
+                else
+                {
+                    if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                    {
+                        xAccessGranted = pdTRUE;
+                    }
+                }
             }
 
             return xAccessGranted;
@@ -2141,5 +2079,5 @@ BaseType_t xPortIsInsideInterrupt( void )
 
     #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
 
-#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM85/non_secure/portasm.s b/portable/IAR/ARM_CM85/non_secure/portasm.s
index 15e74ffc1..d8f1b1d9a 100644
--- a/portable/IAR/ARM_CM85/non_secure/portasm.s
+++ b/portable/IAR/ARM_CM85/non_secure/portasm.s
@@ -32,6 +32,9 @@ the code is included in C files but excluded by the preprocessor in assembly
 files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
 #include "FreeRTOSConfig.h"
 
+/* System call numbers includes. */
+#include "mpu_syscall_numbers.h"
+
 #ifndef configUSE_MPU_WRAPPERS_V1
     #define configUSE_MPU_WRAPPERS_V1 0
 #endif
@@ -44,7 +47,6 @@ files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler.
     EXTERN SecureContext_LoadContext
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
     EXTERN vSystemCallEnter
-    EXTERN vSystemCallEnter_1
     EXTERN vSystemCallExit
 #endif
 
@@ -86,7 +88,7 @@ vResetPrivilege:
 /*-----------------------------------------------------------*/
 
 vPortAllocateSecureContext:
-    svc 0                                   /* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 0. */
+    svc 100                                 /* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 100. */
     bx lr                                   /* Return. */
 /*-----------------------------------------------------------*/
 
@@ -205,7 +207,7 @@ vStartFirstTask:
     cpsie f
     dsb
     isb
-    svc 2                                   /* System call to start the first task. portSVC_START_SCHEDULER = 2. */
+    svc 102                                 /* System call to start the first task. portSVC_START_SCHEDULER = 102. */
 /*-----------------------------------------------------------*/
 
 ulSetInterruptMask:
@@ -455,11 +457,9 @@ SVC_Handler:
 
     ldr r1, [r0, #24]
     ldrb r2, [r1, #-2]
-    cmp r2, #4          /* portSVC_SYSTEM_CALL_ENTER. */
-    beq syscall_enter
-    cmp r2, #5          /* portSVC_SYSTEM_CALL_ENTER_1. */
-    beq syscall_enter_1
-    cmp r2, #6          /* portSVC_SYSTEM_CALL_EXIT. */
+    cmp r2, #NUM_SYSTEM_CALLS
+    blt syscall_enter
+    cmp r2, #104            /* portSVC_SYSTEM_CALL_EXIT. */
     beq syscall_exit
     b vPortSVCHandler_C
 
@@ -467,10 +467,6 @@ SVC_Handler:
         mov r1, lr
         b vSystemCallEnter
 
-    syscall_enter_1:
-        mov r1, lr
-        b vSystemCallEnter_1
-
     syscall_exit:
         mov r1, lr
         b vSystemCallExit
@@ -493,7 +489,7 @@ vPortFreeSecureContext:
     ldr r1, [r2]                            /* The first item on the stack is the task's xSecureContext. */
     cmp r1, #0                              /* Raise svc if task's xSecureContext is not NULL. */
     it ne
-    svcne 1                                 /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */
+    svcne 101                               /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 101. */
     bx lr                                   /* Return. */
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h
index 60ef37380..672b0dbdc 100644
--- a/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h
@@ -322,14 +322,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 /**
  * @brief SVC numbers.
  */
-#define portSVC_ALLOCATE_SECURE_CONTEXT    0
-#define portSVC_FREE_SECURE_CONTEXT        1
-#define portSVC_START_SCHEDULER            2
-#define portSVC_RAISE_PRIVILEGE            3
-#define portSVC_SYSTEM_CALL_ENTER          4   /* System calls with upto 4 parameters. */
-#define portSVC_SYSTEM_CALL_ENTER_1        5   /* System calls with 5 parameters. */
-#define portSVC_SYSTEM_CALL_EXIT           6
-#define portSVC_YIELD                      7
+#define portSVC_ALLOCATE_SECURE_CONTEXT    100
+#define portSVC_FREE_SECURE_CONTEXT        101
+#define portSVC_START_SCHEDULER            102
+#define portSVC_RAISE_PRIVILEGE            103
+#define portSVC_SYSTEM_CALL_EXIT           104
+#define portSVC_YIELD                      105
 /*-----------------------------------------------------------*/
 
 /**
diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.S
index 1005dad33..80d5a1c63 100644
--- a/portable/IAR/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.S
+++ b/portable/IAR/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.S
@@ -32,15 +32,12 @@
 /*-----------------------------------------------------------*/
 
 #include "FreeRTOSConfig.h"
+#include "mpu_syscall_numbers.h"
 
 #ifndef configUSE_MPU_WRAPPERS_V1
     #define configUSE_MPU_WRAPPERS_V1 0
 #endif
 
-/* These must be in sync with portmacro.h. */
-#define portSVC_SYSTEM_CALL_ENTER   4 /* System calls with upto 4 parameters. */
-#define portSVC_SYSTEM_CALL_ENTER_1 5 /* System calls with 5 parameters. */
-#define portSVC_SYSTEM_CALL_EXIT    6
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
@@ -56,10 +53,7 @@ MPU_xTaskDelayUntil:
         b MPU_xTaskDelayUntilImpl
     MPU_xTaskDelayUntil_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskDelayUntilImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskDelayUntil
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskAbortDelay
@@ -73,10 +67,7 @@ MPU_xTaskAbortDelay:
         b MPU_xTaskAbortDelayImpl
     MPU_xTaskAbortDelay_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskAbortDelayImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskAbortDelay
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskDelay
@@ -90,10 +81,7 @@ MPU_vTaskDelay:
         b MPU_vTaskDelayImpl
     MPU_vTaskDelay_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskDelayImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskDelay
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskPriorityGet
@@ -107,10 +95,7 @@ MPU_uxTaskPriorityGet:
         b MPU_uxTaskPriorityGetImpl
     MPU_uxTaskPriorityGet_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskPriorityGetImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskPriorityGet
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_eTaskGetState
@@ -124,10 +109,7 @@ MPU_eTaskGetState:
         b MPU_eTaskGetStateImpl
     MPU_eTaskGetState_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_eTaskGetStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_eTaskGetState
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskGetInfo
@@ -141,10 +123,7 @@ MPU_vTaskGetInfo:
         b MPU_vTaskGetInfoImpl
     MPU_vTaskGetInfo_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskGetInfoImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskGetInfo
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetIdleTaskHandle
@@ -158,10 +137,7 @@ MPU_xTaskGetIdleTaskHandle:
         b MPU_xTaskGetIdleTaskHandleImpl
     MPU_xTaskGetIdleTaskHandle_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetIdleTaskHandleImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetIdleTaskHandle
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskSuspend
@@ -175,10 +151,7 @@ MPU_vTaskSuspend:
         b MPU_vTaskSuspendImpl
     MPU_vTaskSuspend_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSuspendImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskSuspend
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskResume
@@ -192,10 +165,7 @@ MPU_vTaskResume:
         b MPU_vTaskResumeImpl
     MPU_vTaskResume_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskResumeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskResume
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetTickCount
@@ -209,10 +179,7 @@ MPU_xTaskGetTickCount:
         b MPU_xTaskGetTickCountImpl
     MPU_xTaskGetTickCount_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetTickCountImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetTickCount
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskGetNumberOfTasks
@@ -226,10 +193,7 @@ MPU_uxTaskGetNumberOfTasks:
         b MPU_uxTaskGetNumberOfTasksImpl
     MPU_uxTaskGetNumberOfTasks_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetNumberOfTasksImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskGetNumberOfTasks
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGetRunTimeCounter
@@ -243,10 +207,7 @@ MPU_ulTaskGetRunTimeCounter:
         b MPU_ulTaskGetRunTimeCounterImpl
     MPU_ulTaskGetRunTimeCounter_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetRunTimeCounterImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGetRunTimeCounter
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGetRunTimePercent
@@ -260,10 +221,7 @@ MPU_ulTaskGetRunTimePercent:
         b MPU_ulTaskGetRunTimePercentImpl
     MPU_ulTaskGetRunTimePercent_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetRunTimePercentImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGetRunTimePercent
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGetIdleRunTimePercent
@@ -277,10 +235,7 @@ MPU_ulTaskGetIdleRunTimePercent:
         b MPU_ulTaskGetIdleRunTimePercentImpl
     MPU_ulTaskGetIdleRunTimePercent_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetIdleRunTimePercentImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGetIdleRunTimeCounter
@@ -294,10 +249,7 @@ MPU_ulTaskGetIdleRunTimeCounter:
         b MPU_ulTaskGetIdleRunTimeCounterImpl
     MPU_ulTaskGetIdleRunTimeCounter_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGetIdleRunTimeCounterImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskSetApplicationTaskTag
@@ -311,10 +263,7 @@ MPU_vTaskSetApplicationTaskTag:
         b MPU_vTaskSetApplicationTaskTagImpl
     MPU_vTaskSetApplicationTaskTag_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSetApplicationTaskTagImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskSetApplicationTaskTag
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetApplicationTaskTag
@@ -328,10 +277,7 @@ MPU_xTaskGetApplicationTaskTag:
         b MPU_xTaskGetApplicationTaskTagImpl
     MPU_xTaskGetApplicationTaskTag_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetApplicationTaskTagImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetApplicationTaskTag
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskSetThreadLocalStoragePointer
@@ -345,10 +291,7 @@ MPU_vTaskSetThreadLocalStoragePointer:
         b MPU_vTaskSetThreadLocalStoragePointerImpl
     MPU_vTaskSetThreadLocalStoragePointer_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSetThreadLocalStoragePointerImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pvTaskGetThreadLocalStoragePointer
@@ -362,10 +305,7 @@ MPU_pvTaskGetThreadLocalStoragePointer:
         b MPU_pvTaskGetThreadLocalStoragePointerImpl
     MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pvTaskGetThreadLocalStoragePointerImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskGetSystemState
@@ -379,10 +319,7 @@ MPU_uxTaskGetSystemState:
         b MPU_uxTaskGetSystemStateImpl
     MPU_uxTaskGetSystemState_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetSystemStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskGetSystemState
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskGetStackHighWaterMark
@@ -396,10 +333,7 @@ MPU_uxTaskGetStackHighWaterMark:
         b MPU_uxTaskGetStackHighWaterMarkImpl
     MPU_uxTaskGetStackHighWaterMark_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetStackHighWaterMarkImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTaskGetStackHighWaterMark2
@@ -413,10 +347,7 @@ MPU_uxTaskGetStackHighWaterMark2:
         b MPU_uxTaskGetStackHighWaterMark2Impl
     MPU_uxTaskGetStackHighWaterMark2_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetStackHighWaterMark2Impl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetCurrentTaskHandle
@@ -430,10 +361,7 @@ MPU_xTaskGetCurrentTaskHandle:
         b MPU_xTaskGetCurrentTaskHandleImpl
     MPU_xTaskGetCurrentTaskHandle_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetCurrentTaskHandleImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGetSchedulerState
@@ -447,10 +375,7 @@ MPU_xTaskGetSchedulerState:
         b MPU_xTaskGetSchedulerStateImpl
     MPU_xTaskGetSchedulerState_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetSchedulerStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGetSchedulerState
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTaskSetTimeOutState
@@ -464,10 +389,7 @@ MPU_vTaskSetTimeOutState:
         b MPU_vTaskSetTimeOutStateImpl
     MPU_vTaskSetTimeOutState_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSetTimeOutStateImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTaskSetTimeOutState
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskCheckForTimeOut
@@ -481,14 +403,11 @@ MPU_xTaskCheckForTimeOut:
         b MPU_xTaskCheckForTimeOutImpl
     MPU_xTaskCheckForTimeOut_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskCheckForTimeOutImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskCheckForTimeOut
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xTaskGenericNotify
-MPU_xTaskGenericNotify:
+    PUBLIC MPU_xTaskGenericNotifyEntry
+MPU_xTaskGenericNotifyEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
@@ -498,14 +417,11 @@ MPU_xTaskGenericNotify:
         b MPU_xTaskGenericNotifyImpl
     MPU_xTaskGenericNotify_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTaskGenericNotifyImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGenericNotify
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xTaskGenericNotifyWait
-MPU_xTaskGenericNotifyWait:
+    PUBLIC MPU_xTaskGenericNotifyWaitEntry
+MPU_xTaskGenericNotifyWaitEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
@@ -515,10 +431,7 @@ MPU_xTaskGenericNotifyWait:
         b MPU_xTaskGenericNotifyWaitImpl
     MPU_xTaskGenericNotifyWait_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTaskGenericNotifyWaitImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGenericNotifyWait
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGenericNotifyTake
@@ -532,10 +445,7 @@ MPU_ulTaskGenericNotifyTake:
         b MPU_ulTaskGenericNotifyTakeImpl
     MPU_ulTaskGenericNotifyTake_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGenericNotifyTakeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGenericNotifyTake
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTaskGenericNotifyStateClear
@@ -549,10 +459,7 @@ MPU_xTaskGenericNotifyStateClear:
         b MPU_xTaskGenericNotifyStateClearImpl
     MPU_xTaskGenericNotifyStateClear_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGenericNotifyStateClearImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTaskGenericNotifyStateClear
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_ulTaskGenericNotifyValueClear
@@ -566,10 +473,7 @@ MPU_ulTaskGenericNotifyValueClear:
         b MPU_ulTaskGenericNotifyValueClearImpl
     MPU_ulTaskGenericNotifyValueClear_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_ulTaskGenericNotifyValueClearImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueGenericSend
@@ -583,10 +487,7 @@ MPU_xQueueGenericSend:
         b MPU_xQueueGenericSendImpl
     MPU_xQueueGenericSend_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueGenericSendImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueGenericSend
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxQueueMessagesWaiting
@@ -600,10 +501,7 @@ MPU_uxQueueMessagesWaiting:
         b MPU_uxQueueMessagesWaitingImpl
     MPU_uxQueueMessagesWaiting_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxQueueMessagesWaitingImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxQueueMessagesWaiting
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxQueueSpacesAvailable
@@ -617,10 +515,7 @@ MPU_uxQueueSpacesAvailable:
         b MPU_uxQueueSpacesAvailableImpl
     MPU_uxQueueSpacesAvailable_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxQueueSpacesAvailableImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxQueueSpacesAvailable
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueReceive
@@ -634,10 +529,7 @@ MPU_xQueueReceive:
         b MPU_xQueueReceiveImpl
     MPU_xQueueReceive_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueReceiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueReceive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueuePeek
@@ -651,10 +543,7 @@ MPU_xQueuePeek:
         b MPU_xQueuePeekImpl
     MPU_xQueuePeek_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueuePeekImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueuePeek
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueSemaphoreTake
@@ -668,10 +557,7 @@ MPU_xQueueSemaphoreTake:
         b MPU_xQueueSemaphoreTakeImpl
     MPU_xQueueSemaphoreTake_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueSemaphoreTakeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueSemaphoreTake
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueGetMutexHolder
@@ -685,10 +571,7 @@ MPU_xQueueGetMutexHolder:
         b MPU_xQueueGetMutexHolderImpl
     MPU_xQueueGetMutexHolder_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueGetMutexHolderImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueGetMutexHolder
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueTakeMutexRecursive
@@ -702,10 +585,7 @@ MPU_xQueueTakeMutexRecursive:
         b MPU_xQueueTakeMutexRecursiveImpl
     MPU_xQueueTakeMutexRecursive_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueTakeMutexRecursiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueTakeMutexRecursive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueGiveMutexRecursive
@@ -719,10 +599,7 @@ MPU_xQueueGiveMutexRecursive:
         b MPU_xQueueGiveMutexRecursiveImpl
     MPU_xQueueGiveMutexRecursive_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueGiveMutexRecursiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueGiveMutexRecursive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueSelectFromSet
@@ -736,10 +613,7 @@ MPU_xQueueSelectFromSet:
         b MPU_xQueueSelectFromSetImpl
     MPU_xQueueSelectFromSet_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueSelectFromSetImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueSelectFromSet
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xQueueAddToSet
@@ -753,10 +627,7 @@ MPU_xQueueAddToSet:
         b MPU_xQueueAddToSetImpl
     MPU_xQueueAddToSet_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueAddToSetImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xQueueAddToSet
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vQueueAddToRegistry
@@ -770,10 +641,7 @@ MPU_vQueueAddToRegistry:
         b MPU_vQueueAddToRegistryImpl
     MPU_vQueueAddToRegistry_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vQueueAddToRegistryImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vQueueAddToRegistry
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vQueueUnregisterQueue
@@ -787,10 +655,7 @@ MPU_vQueueUnregisterQueue:
         b MPU_vQueueUnregisterQueueImpl
     MPU_vQueueUnregisterQueue_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vQueueUnregisterQueueImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vQueueUnregisterQueue
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pcQueueGetName
@@ -804,10 +669,7 @@ MPU_pcQueueGetName:
         b MPU_pcQueueGetNameImpl
     MPU_pcQueueGetName_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pcQueueGetNameImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_pcQueueGetName
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pvTimerGetTimerID
@@ -821,10 +683,7 @@ MPU_pvTimerGetTimerID:
         b MPU_pvTimerGetTimerIDImpl
     MPU_pvTimerGetTimerID_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pvTimerGetTimerIDImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_pvTimerGetTimerID
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTimerSetTimerID
@@ -838,10 +697,7 @@ MPU_vTimerSetTimerID:
         b MPU_vTimerSetTimerIDImpl
     MPU_vTimerSetTimerID_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTimerSetTimerIDImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTimerSetTimerID
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerIsTimerActive
@@ -855,10 +711,7 @@ MPU_xTimerIsTimerActive:
         b MPU_xTimerIsTimerActiveImpl
     MPU_xTimerIsTimerActive_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerIsTimerActiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerIsTimerActive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerGetTimerDaemonTaskHandle
@@ -872,14 +725,11 @@ MPU_xTimerGetTimerDaemonTaskHandle:
         b MPU_xTimerGetTimerDaemonTaskHandleImpl
     MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetTimerDaemonTaskHandleImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xTimerGenericCommandFromTask
-MPU_xTimerGenericCommandFromTask:
+    PUBLIC MPU_xTimerGenericCommandFromTaskEntry
+MPU_xTimerGenericCommandFromTaskEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
@@ -889,10 +739,7 @@ MPU_xTimerGenericCommandFromTask:
         b MPU_xTimerGenericCommandFromTaskImpl
     MPU_xTimerGenericCommandFromTask_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xTimerGenericCommandFromTaskImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGenericCommandFromTask
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_pcTimerGetName
@@ -906,10 +753,7 @@ MPU_pcTimerGetName:
         b MPU_pcTimerGetNameImpl
     MPU_pcTimerGetName_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_pcTimerGetNameImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_pcTimerGetName
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vTimerSetReloadMode
@@ -923,10 +767,7 @@ MPU_vTimerSetReloadMode:
         b MPU_vTimerSetReloadModeImpl
     MPU_vTimerSetReloadMode_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTimerSetReloadModeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vTimerSetReloadMode
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerGetReloadMode
@@ -940,10 +781,7 @@ MPU_xTimerGetReloadMode:
         b MPU_xTimerGetReloadModeImpl
     MPU_xTimerGetReloadMode_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetReloadModeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGetReloadMode
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxTimerGetReloadMode
@@ -957,10 +795,7 @@ MPU_uxTimerGetReloadMode:
         b MPU_uxTimerGetReloadModeImpl
     MPU_uxTimerGetReloadMode_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTimerGetReloadModeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxTimerGetReloadMode
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerGetPeriod
@@ -974,10 +809,7 @@ MPU_xTimerGetPeriod:
         b MPU_xTimerGetPeriodImpl
     MPU_xTimerGetPeriod_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetPeriodImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGetPeriod
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xTimerGetExpiryTime
@@ -991,14 +823,11 @@ MPU_xTimerGetExpiryTime:
         b MPU_xTimerGetExpiryTimeImpl
     MPU_xTimerGetExpiryTime_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTimerGetExpiryTimeImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xTimerGetExpiryTime
 /*-----------------------------------------------------------*/
 
-    PUBLIC MPU_xEventGroupWaitBits
-MPU_xEventGroupWaitBits:
+    PUBLIC MPU_xEventGroupWaitBitsEntry
+MPU_xEventGroupWaitBitsEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
@@ -1008,10 +837,7 @@ MPU_xEventGroupWaitBits:
         b MPU_xEventGroupWaitBitsImpl
     MPU_xEventGroupWaitBits_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xEventGroupWaitBitsImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xEventGroupWaitBits
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xEventGroupClearBits
@@ -1025,10 +851,7 @@ MPU_xEventGroupClearBits:
         b MPU_xEventGroupClearBitsImpl
     MPU_xEventGroupClearBits_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xEventGroupClearBitsImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xEventGroupClearBits
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xEventGroupSetBits
@@ -1042,10 +865,7 @@ MPU_xEventGroupSetBits:
         b MPU_xEventGroupSetBitsImpl
     MPU_xEventGroupSetBits_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xEventGroupSetBitsImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xEventGroupSetBits
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xEventGroupSync
@@ -1059,10 +879,7 @@ MPU_xEventGroupSync:
         b MPU_xEventGroupSyncImpl
     MPU_xEventGroupSync_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xEventGroupSyncImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xEventGroupSync
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_uxEventGroupGetNumber
@@ -1076,10 +893,7 @@ MPU_uxEventGroupGetNumber:
         b MPU_uxEventGroupGetNumberImpl
     MPU_uxEventGroupGetNumber_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxEventGroupGetNumberImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_uxEventGroupGetNumber
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_vEventGroupSetNumber
@@ -1093,10 +907,7 @@ MPU_vEventGroupSetNumber:
         b MPU_vEventGroupSetNumberImpl
     MPU_vEventGroupSetNumber_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vEventGroupSetNumberImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_vEventGroupSetNumber
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferSend
@@ -1110,10 +921,7 @@ MPU_xStreamBufferSend:
         b MPU_xStreamBufferSendImpl
     MPU_xStreamBufferSend_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferSendImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferSend
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferReceive
@@ -1127,10 +935,7 @@ MPU_xStreamBufferReceive:
         b MPU_xStreamBufferReceiveImpl
     MPU_xStreamBufferReceive_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferReceiveImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferReceive
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferIsFull
@@ -1144,10 +949,7 @@ MPU_xStreamBufferIsFull:
         b MPU_xStreamBufferIsFullImpl
     MPU_xStreamBufferIsFull_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferIsFullImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferIsFull
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferIsEmpty
@@ -1161,10 +963,7 @@ MPU_xStreamBufferIsEmpty:
         b MPU_xStreamBufferIsEmptyImpl
     MPU_xStreamBufferIsEmpty_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferIsEmptyImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferIsEmpty
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferSpacesAvailable
@@ -1178,10 +977,7 @@ MPU_xStreamBufferSpacesAvailable:
         b MPU_xStreamBufferSpacesAvailableImpl
     MPU_xStreamBufferSpacesAvailable_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferSpacesAvailableImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferSpacesAvailable
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferBytesAvailable
@@ -1195,10 +991,7 @@ MPU_xStreamBufferBytesAvailable:
         b MPU_xStreamBufferBytesAvailableImpl
     MPU_xStreamBufferBytesAvailable_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferBytesAvailableImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferBytesAvailable
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferSetTriggerLevel
@@ -1212,10 +1005,7 @@ MPU_xStreamBufferSetTriggerLevel:
         b MPU_xStreamBufferSetTriggerLevelImpl
     MPU_xStreamBufferSetTriggerLevel_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferSetTriggerLevelImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel
 /*-----------------------------------------------------------*/
 
     PUBLIC MPU_xStreamBufferNextMessageLengthBytes
@@ -1229,10 +1019,7 @@ MPU_xStreamBufferNextMessageLengthBytes:
         b MPU_xStreamBufferNextMessageLengthBytesImpl
     MPU_xStreamBufferNextMessageLengthBytes_Unpriv:
         pop {r0}
-        svc #portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferNextMessageLengthBytesImpl
-        svc #portSVC_SYSTEM_CALL_EXIT
-        bx lr
+        svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes
 /*-----------------------------------------------------------*/
 
 /* Default weak implementations in case one is not available from
diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/port.c b/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
index 52d68d3ea..6a3877894 100644
--- a/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
@@ -35,8 +35,9 @@
 #include "FreeRTOS.h"
 #include "task.h"
 
-/* MPU wrappers includes. */
+/* MPU includes. */
 #include "mpu_wrappers.h"
+#include "mpu_syscall_numbers.h"
 
 /* Portasm includes. */
 #include "portasm.h"
@@ -436,29 +437,22 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
  * @brief Sets up the system call stack so that upon returning from
  * SVC, the system call stack is used.
  *
- * It is used for the system calls with up to 4 parameters.
- *
  * @param pulTaskStack The current SP when the SVC was raised.
  * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ * @param ucSystemCallNumber The system call number of the system call.
  */
     void vSystemCallEnter( uint32_t * pulTaskStack,
-                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
+                           uint32_t ulLR,
+                           uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
- * @brief Sets up the system call stack so that upon returning from
- * SVC, the system call stack is used.
- *
- * It is used for the system calls with 5 parameters.
- *
- * @param pulTaskStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ * @brief Raise SVC for exiting from a system call.
  */
-    void vSystemCallEnter_1( uint32_t * pulTaskStack,
-                             uint32_t ulLR ) PRIVILEGED_FUNCTION;
+    void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
@@ -488,6 +482,15 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+/**
+ * @brief This variable is set to pdTRUE when the scheduler is started.
+ */
+    PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
+
+#endif
+
 /**
  * @brief Each task maintains its own interrupt status in the critical nesting
  * variable.
@@ -1134,15 +1137,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     void vSystemCallEnter( uint32_t * pulTaskStack,
-                           uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
+                           uint32_t ulLR,
+                           uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */
     {
         extern TaskHandle_t pxCurrentTCB;
+        extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ];
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulSystemCallStack;
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
-
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __syscalls_flash_start__;
@@ -1154,17 +1158,27 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         #endif /* #if defined( __ARMCC_VERSION ) */
 
         ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
 
-        /* If the request did not come from the system call section, do nothing. */
+        /* Checks:
+         * 1. SVC is raised from the system call section (i.e. application is
+         *    not raising SVC directly).
+         * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as
+         *    it is non-NULL only during the execution of a system call (i.e.
+         *    between system call enter and exit).
+         * 3. System call is not for a kernel API disabled by the configuration
+         *    in FreeRTOSConfig.h.
+         * 4. We do not need to check that ucSystemCallNumber is within range
+         *    because the assembly SVC handler checks that before calling
+         *    this function.
+         */
         if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) &&
+            ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) &&
+            ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) )
         {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
             pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
 
-            /* This is not NULL only for the duration of the system call. */
-            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
-
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
@@ -1198,9 +1212,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 pulSystemCallStack[ i ] = pulTaskStack[ i ];
             }
 
-            /* Store the value of the LR and PSPLIM registers before the SVC was raised. We need to
-             * restore it when we exit from the system call. */
+            /* Store the value of the Link Register before the SVC was raised.
+             * It contains the address of the caller of the System Call entry
+             * point (i.e. the caller of the MPU_<API>). We need to restore it
+             * when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+            /* Store the value of the PSPLIM register before the SVC was raised.
+             * We need to restore it when we exit from the system call. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
             {
                 __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
@@ -1215,6 +1233,12 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             }
             #endif
 
+            /* Start executing the system call upon returning from this handler. */
+            pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
+            /* Raise a request to exit from the system call upon finishing the
+             * system call. */
+            pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit;
+
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
             pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
@@ -1251,127 +1275,9 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-    void vSystemCallEnter_1( uint32_t * pulTaskStack,
-                             uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
+    void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */
     {
-        extern TaskHandle_t pxCurrentTCB;
-        xMPU_SETTINGS * pxMpuSettings;
-        uint32_t * pulSystemCallStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
-
-        #if defined( __ARMCC_VERSION )
-
-            /* Declaration when these variable are defined in code instead of being
-             * exported from linker scripts. */
-            extern uint32_t * __syscalls_flash_start__;
-            extern uint32_t * __syscalls_flash_end__;
-        #else
-            /* Declaration when these variable are exported from linker scripts. */
-            extern uint32_t __syscalls_flash_start__[];
-            extern uint32_t __syscalls_flash_end__[];
-        #endif /* #if defined( __ARMCC_VERSION ) */
-
-        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-        /* If the request did not come from the system call section, do nothing. */
-        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
-        {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
-
-            /* This is not NULL only for the duration of the system call. */
-            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
-
-            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-            {
-                if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
-                {
-                    /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
-                    __asm volatile (
-                        " vpush {s0}         \n" /* Trigger lazy stacking. */
-                        " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
-                        ::: "memory"
-                        );
-                }
-                else
-                {
-                    /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
-                }
-            }
-            #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
-            {
-                ulStackFrameSize = 8;
-            }
-            #endif /* configENABLE_FPU || configENABLE_MVE */
-
-            /* Make space on the system call stack for the stack frame and
-             * the parameter passed on the stack. We only need to copy one
-             * parameter but we still reserve 2 spaces to keep the stack
-             * double word aligned. */
-            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
-
-            /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
-            {
-                pulSystemCallStack[ i ] = pulTaskStack[ i ];
-            }
-
-            /* Copy the parameter which is passed the stack. */
-            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-            {
-                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
-
-                /* Record if the hardware used padding to force the stack pointer
-                 * to be double word aligned. */
-                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-            }
-            else
-            {
-                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
-
-                /* Record if the hardware used padding to force the stack pointer
-                 * to be double word aligned. */
-                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-            }
-
-            /* Store the value of the LR and PSPLIM registers before the SVC was raised.
-             * We need to restore it when we exit from the system call. */
-            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-            #if ( portUSE_PSPLIM_REGISTER == 1 )
-            {
-                __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
-            }
-            #endif
-
-            /* Use the pulSystemCallStack in thread mode. */
-            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
-            #if ( portUSE_PSPLIM_REGISTER == 1 )
-            {
-                __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
-            }
-            #endif
-
-            /* Remember the location where we should copy the stack frame when we exit from
-             * the system call. */
-            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-            /* We ensure in pxPortInitialiseStack that the system call stack is
-             * double word aligned and therefore, there is no need of padding.
-             * Clear the bit[9] of stacked xPSR. */
-            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-
-            /* Raise the privilege for the duration of the system call. */
-            __asm volatile (
-                " mrs r0, control     \n" /* Obtain current control value. */
-                " movs r1, #1         \n" /* r1 = 1. */
-                " bics r0, r1         \n" /* Clear nPRIV bit. */
-                " msr control, r0     \n" /* Write back new control value. */
-                ::: "r0", "r1", "memory"
-                );
-        }
+        __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" );
     }
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@@ -1388,24 +1294,32 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
-
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
-            extern uint32_t * __syscalls_flash_start__;
-            extern uint32_t * __syscalls_flash_end__;
+            extern uint32_t * __privileged_functions_start__;
+            extern uint32_t * __privileged_functions_end__;
         #else
             /* Declaration when these variable are exported from linker scripts. */
-            extern uint32_t __syscalls_flash_start__[];
-            extern uint32_t __syscalls_flash_end__[];
+            extern uint32_t __privileged_functions_start__[];
+            extern uint32_t __privileged_functions_end__[];
         #endif /* #if defined( __ARMCC_VERSION ) */
 
         ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
+        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
 
-        /* If the request did not come from the system call section, do nothing. */
-        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+        /* Checks:
+         * 1. SVC is raised from the privileged code (i.e. application is not
+         *    raising SVC directly). This SVC is only raised from
+         *    vRequestSystemCallExit which is in the privileged code section.
+         * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL -
+         *    this means that we previously entered a system call and the
+         *    application is not attempting to exit without entering a system
+         *    call.
+         */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) &&
+            ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) )
         {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
             pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
 
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
@@ -1444,9 +1358,14 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             /* Use the pulTaskStack in thread mode. */
             __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
 
-            /* Restore the LR and PSPLIM to what they were at the time of
-             * system call entry. */
+            /* Return to the caller of the System Call entry point (i.e. the
+             * caller of the MPU_<API>). */
+            pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+            /* Ensure that LR has a valid value.*/
             pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+
+            /* Restore the PSPLIM register to what it was at the time of
+             * system call entry. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
             {
                 __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
@@ -1780,6 +1699,12 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     /* Initialize the critical nesting count ready for the first task. */
     ulCriticalNesting = 0;
 
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+    {
+        xSchedulerRunning = pdTRUE;
+    }
+    #endif
+
     /* Start the first task. */
     vStartFirstTask();
 
@@ -2062,7 +1987,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
 
     void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
                                          int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
@@ -2078,10 +2003,10 @@ BaseType_t xPortIsInsideInterrupt( void )
         xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit );
     }
 
-#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
 
     void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
                                           int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
@@ -2097,10 +2022,10 @@ BaseType_t xPortIsInsideInterrupt( void )
         xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit );
     }
 
-#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
 
@@ -2108,21 +2033,34 @@ BaseType_t xPortIsInsideInterrupt( void )
         {
             uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
             BaseType_t xAccessGranted = pdFALSE;
-            const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+            const xMPU_SETTINGS * xTaskMpuSettings;
 
-            ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
-            ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
-
-            if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+            if( xSchedulerRunning == pdFALSE )
             {
+                /* Grant access to all the kernel objects before the scheduler
+                 * is started. It is necessary because there is no task running
+                 * yet and therefore, we cannot use the permissions of any
+                 * task. */
                 xAccessGranted = pdTRUE;
             }
             else
             {
-                if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+                ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+                ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+                if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
                 {
                     xAccessGranted = pdTRUE;
                 }
+                else
+                {
+                    if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                    {
+                        xAccessGranted = pdTRUE;
+                    }
+                }
             }
 
             return xAccessGranted;
@@ -2141,5 +2079,5 @@ BaseType_t xPortIsInsideInterrupt( void )
 
     #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
 
-#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.s b/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.s
index ec5202527..7cf467d22 100644
--- a/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.s
+++ b/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.s
@@ -32,6 +32,9 @@ the code is included in C files but excluded by the preprocessor in assembly
 files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
 #include "FreeRTOSConfig.h"
 
+/* System call numbers includes. */
+#include "mpu_syscall_numbers.h"
+
 #ifndef configUSE_MPU_WRAPPERS_V1
     #define configUSE_MPU_WRAPPERS_V1 0
 #endif
@@ -41,7 +44,6 @@ files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler.
     EXTERN vPortSVCHandler_C
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
     EXTERN vSystemCallEnter
-    EXTERN vSystemCallEnter_1
     EXTERN vSystemCallExit
 #endif
 
@@ -191,7 +193,7 @@ vStartFirstTask:
     cpsie f
     dsb
     isb
-    svc 2                                   /* System call to start the first task. portSVC_START_SCHEDULER = 2. */
+    svc 102                                 /* System call to start the first task. portSVC_START_SCHEDULER = 102. */
 /*-----------------------------------------------------------*/
 
 ulSetInterruptMask:
@@ -371,11 +373,9 @@ SVC_Handler:
 
     ldr r1, [r0, #24]
     ldrb r2, [r1, #-2]
-    cmp r2, #4          /* portSVC_SYSTEM_CALL_ENTER. */
-    beq syscall_enter
-    cmp r2, #5          /* portSVC_SYSTEM_CALL_ENTER_1. */
-    beq syscall_enter_1
-    cmp r2, #6          /* portSVC_SYSTEM_CALL_EXIT. */
+    cmp r2, #NUM_SYSTEM_CALLS
+    blt syscall_enter
+    cmp r2, #104            /* portSVC_SYSTEM_CALL_EXIT. */
     beq syscall_exit
     b vPortSVCHandler_C
 
@@ -383,10 +383,6 @@ SVC_Handler:
         mov r1, lr
         b vSystemCallEnter
 
-    syscall_enter_1:
-        mov r1, lr
-        b vSystemCallEnter_1
-
     syscall_exit:
         mov r1, lr
         b vSystemCallExit
diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h
index 60ef37380..672b0dbdc 100644
--- a/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h
@@ -322,14 +322,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 /**
  * @brief SVC numbers.
  */
-#define portSVC_ALLOCATE_SECURE_CONTEXT    0
-#define portSVC_FREE_SECURE_CONTEXT        1
-#define portSVC_START_SCHEDULER            2
-#define portSVC_RAISE_PRIVILEGE            3
-#define portSVC_SYSTEM_CALL_ENTER          4   /* System calls with upto 4 parameters. */
-#define portSVC_SYSTEM_CALL_ENTER_1        5   /* System calls with 5 parameters. */
-#define portSVC_SYSTEM_CALL_EXIT           6
-#define portSVC_YIELD                      7
+#define portSVC_ALLOCATE_SECURE_CONTEXT    100
+#define portSVC_FREE_SECURE_CONTEXT        101
+#define portSVC_START_SCHEDULER            102
+#define portSVC_RAISE_PRIVILEGE            103
+#define portSVC_SYSTEM_CALL_EXIT           104
+#define portSVC_YIELD                      105
 /*-----------------------------------------------------------*/
 
 /**
diff --git a/portable/RVDS/ARM_CM4_MPU/mpu_wrappers_v2_asm.c b/portable/RVDS/ARM_CM4_MPU/mpu_wrappers_v2_asm.c
index 931a9ffd4..d65876356 100644
--- a/portable/RVDS/ARM_CM4_MPU/mpu_wrappers_v2_asm.c
+++ b/portable/RVDS/ARM_CM4_MPU/mpu_wrappers_v2_asm.c
@@ -38,2350 +38,1690 @@
 #include "timers.h"
 #include "event_groups.h"
 #include "stream_buffer.h"
+#include "mpu_prototypes.h"
+#include "mpu_syscall_numbers.h"
 
 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
 /*-----------------------------------------------------------*/
 
 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
 
-    #if ( INCLUDE_xTaskDelayUntil == 1 )
+#if ( INCLUDE_xTaskDelayUntil == 1 )
 
-        BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
-                                        const TickType_t xTimeIncrement ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
+                                const TickType_t xTimeIncrement ) FREERTOS_SYSTEM_CALL;
 
-        __asm BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
-                                              const TickType_t xTimeIncrement ) /* FREERTOS_SYSTEM_CALL */
-        {
-            PRESERVE8
-            extern MPU_xTaskDelayUntilImpl
+__asm BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
+                                      const TickType_t xTimeIncrement ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_xTaskDelayUntilImpl
 
-                push {
-                r0
-            }
-            mrs r0, control
-            tst r0, # 1
-            bne MPU_xTaskDelayUntil_Unpriv
-            MPU_xTaskDelayUntil_Priv
-                pop {
-                r0
-            }
-            b MPU_xTaskDelayUntilImpl
-            MPU_xTaskDelayUntil_Unpriv
-                pop {
-                r0
-            }
-            svc # portSVC_SYSTEM_CALL_ENTER
-            bl MPU_xTaskDelayUntilImpl
-            svc # portSVC_SYSTEM_CALL_EXIT
-            bx lr
-        }
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_xTaskDelayUntil_Unpriv
+MPU_xTaskDelayUntil_Priv
+        pop {r0}
+        b MPU_xTaskDelayUntilImpl
+MPU_xTaskDelayUntil_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_xTaskDelayUntil
+}
 
-    #endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */
+#endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */
 /*-----------------------------------------------------------*/
 
-    #if ( INCLUDE_xTaskAbortDelay == 1 )
+#if ( INCLUDE_xTaskAbortDelay == 1 )
 
-        BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
 
-        __asm BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
-        {
-            PRESERVE8
-            extern MPU_xTaskAbortDelayImpl
+__asm BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_xTaskAbortDelayImpl
 
-                push {
-                r0
-            }
-            mrs r0, control
-            tst r0, # 1
-            bne MPU_xTaskAbortDelay_Unpriv
-            MPU_xTaskAbortDelay_Priv
-                pop {
-                r0
-            }
-            b MPU_xTaskAbortDelayImpl
-            MPU_xTaskAbortDelay_Unpriv
-                pop {
-                r0
-            }
-            svc # portSVC_SYSTEM_CALL_ENTER
-            bl MPU_xTaskAbortDelayImpl
-            svc # portSVC_SYSTEM_CALL_EXIT
-            bx lr
-        }
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_xTaskAbortDelay_Unpriv
+MPU_xTaskAbortDelay_Priv
+        pop {r0}
+        b MPU_xTaskAbortDelayImpl
+MPU_xTaskAbortDelay_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_xTaskAbortDelay
+}
 
-    #endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */
+#endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */
 /*-----------------------------------------------------------*/
 
-    #if ( INCLUDE_vTaskDelay == 1 )
+#if ( INCLUDE_vTaskDelay == 1 )
 
-        void MPU_vTaskDelay( const TickType_t xTicksToDelay ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskDelay( const TickType_t xTicksToDelay ) FREERTOS_SYSTEM_CALL;
 
-        __asm void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* FREERTOS_SYSTEM_CALL */
-        {
-            PRESERVE8
-            extern MPU_vTaskDelayImpl
+__asm void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_vTaskDelayImpl
 
-                push {
-                r0
-            }
-            mrs r0, control
-            tst r0, # 1
-            bne MPU_vTaskDelay_Unpriv
-            MPU_vTaskDelay_Priv
-                pop {
-                r0
-            }
-            b MPU_vTaskDelayImpl
-            MPU_vTaskDelay_Unpriv
-                pop {
-                r0
-            }
-            svc # portSVC_SYSTEM_CALL_ENTER
-            bl MPU_vTaskDelayImpl
-            svc # portSVC_SYSTEM_CALL_EXIT
-            bx lr
-        }
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_vTaskDelay_Unpriv
+MPU_vTaskDelay_Priv
+        pop {r0}
+        b MPU_vTaskDelayImpl
+MPU_vTaskDelay_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_vTaskDelay
+}
 
-    #endif /* if ( INCLUDE_vTaskDelay == 1 ) */
+#endif /* if ( INCLUDE_vTaskDelay == 1 ) */
 /*-----------------------------------------------------------*/
 
-    #if ( INCLUDE_uxTaskPriorityGet == 1 )
+#if ( INCLUDE_uxTaskPriorityGet == 1 )
 
-        UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
 
-        __asm UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
-        {
-            PRESERVE8
-            extern MPU_uxTaskPriorityGetImpl
+__asm UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_uxTaskPriorityGetImpl
 
-                push {
-                r0
-            }
-            mrs r0, control
-            tst r0, # 1
-            bne MPU_uxTaskPriorityGet_Unpriv
-            MPU_uxTaskPriorityGet_Priv
-                pop {
-                r0
-            }
-            b MPU_uxTaskPriorityGetImpl
-            MPU_uxTaskPriorityGet_Unpriv
-                pop {
-                r0
-            }
-            svc # portSVC_SYSTEM_CALL_ENTER
-            bl MPU_uxTaskPriorityGetImpl
-            svc # portSVC_SYSTEM_CALL_EXIT
-            bx lr
-        }
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_uxTaskPriorityGet_Unpriv
+MPU_uxTaskPriorityGet_Priv
+        pop {r0}
+        b MPU_uxTaskPriorityGetImpl
+MPU_uxTaskPriorityGet_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_uxTaskPriorityGet
+}
 
-    #endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */
+#endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */
 /*-----------------------------------------------------------*/
 
-    #if ( INCLUDE_eTaskGetState == 1 )
+#if ( INCLUDE_eTaskGetState == 1 )
 
-        eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
 
-        __asm eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
-        {
-            PRESERVE8
-            extern MPU_eTaskGetStateImpl
+__asm eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_eTaskGetStateImpl
 
-                push {
-                r0
-            }
-            mrs r0, control
-            tst r0, # 1
-            bne MPU_eTaskGetState_Unpriv
-            MPU_eTaskGetState_Priv
-                pop {
-                r0
-            }
-            b MPU_eTaskGetStateImpl
-            MPU_eTaskGetState_Unpriv
-                pop {
-                r0
-            }
-            svc # portSVC_SYSTEM_CALL_ENTER
-            bl MPU_eTaskGetStateImpl
-            svc # portSVC_SYSTEM_CALL_EXIT
-            bx lr
-        }
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_eTaskGetState_Unpriv
+MPU_eTaskGetState_Priv
+        pop {r0}
+        b MPU_eTaskGetStateImpl
+MPU_eTaskGetState_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_eTaskGetState
+}
 
-    #endif /* if ( INCLUDE_eTaskGetState == 1 ) */
+#endif /* if ( INCLUDE_eTaskGetState == 1 ) */
 /*-----------------------------------------------------------*/
 
-    #if ( configUSE_TRACE_FACILITY == 1 )
+#if ( configUSE_TRACE_FACILITY == 1 )
 
-        void MPU_vTaskGetInfo( TaskHandle_t xTask,
-                               TaskStatus_t * pxTaskStatus,
-                               BaseType_t xGetFreeStackSpace,
-                               eTaskState eState ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskGetInfo( TaskHandle_t xTask,
+                       TaskStatus_t * pxTaskStatus,
+                       BaseType_t xGetFreeStackSpace,
+                       eTaskState eState ) FREERTOS_SYSTEM_CALL;
 
-        __asm void MPU_vTaskGetInfo( TaskHandle_t xTask,
-                                     TaskStatus_t * pxTaskStatus,
-                                     BaseType_t xGetFreeStackSpace,
-                                     eTaskState eState ) /* FREERTOS_SYSTEM_CALL */
-        {
-            PRESERVE8
-            extern MPU_vTaskGetInfoImpl
+__asm void MPU_vTaskGetInfo( TaskHandle_t xTask,
+                             TaskStatus_t * pxTaskStatus,
+                             BaseType_t xGetFreeStackSpace,
+                             eTaskState eState ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_vTaskGetInfoImpl
 
-                push {
-                r0
-            }
-            mrs r0, control
-            tst r0, # 1
-            bne MPU_vTaskGetInfo_Unpriv
-            MPU_vTaskGetInfo_Priv
-                pop {
-                r0
-            }
-            b MPU_vTaskGetInfoImpl
-            MPU_vTaskGetInfo_Unpriv
-                pop {
-                r0
-            }
-            svc # portSVC_SYSTEM_CALL_ENTER
-            bl MPU_vTaskGetInfoImpl
-            svc # portSVC_SYSTEM_CALL_EXIT
-            bx lr
-        }
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_vTaskGetInfo_Unpriv
+MPU_vTaskGetInfo_Priv
+        pop {r0}
+        b MPU_vTaskGetInfoImpl
+MPU_vTaskGetInfo_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_vTaskGetInfo
+}
 
-    #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
+#endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
 /*-----------------------------------------------------------*/
 
-    #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
+#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
 
-        TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) FREERTOS_SYSTEM_CALL;
 
-        __asm TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* FREERTOS_SYSTEM_CALL */
-        {
-            PRESERVE8
-            extern MPU_xTaskGetIdleTaskHandleImpl
+__asm TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_xTaskGetIdleTaskHandleImpl
 
-                push {
-                r0
-            }
-            mrs r0, control
-            tst r0, # 1
-            bne MPU_xTaskGetIdleTaskHandle_Unpriv
-            MPU_xTaskGetIdleTaskHandle_Priv
-                pop {
-                r0
-            }
-            b MPU_xTaskGetIdleTaskHandleImpl
-            MPU_xTaskGetIdleTaskHandle_Unpriv
-                pop {
-                r0
-            }
-            svc # portSVC_SYSTEM_CALL_ENTER
-            bl MPU_xTaskGetIdleTaskHandleImpl
-            svc # portSVC_SYSTEM_CALL_EXIT
-            bx lr
-        }
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_xTaskGetIdleTaskHandle_Unpriv
+MPU_xTaskGetIdleTaskHandle_Priv
+        pop {r0}
+        b MPU_xTaskGetIdleTaskHandleImpl
+MPU_xTaskGetIdleTaskHandle_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_xTaskGetIdleTaskHandle
+}
 
-    #endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */
+#endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */
 /*-----------------------------------------------------------*/
 
-    #if ( INCLUDE_vTaskSuspend == 1 )
+#if ( INCLUDE_vTaskSuspend == 1 )
 
-        void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) FREERTOS_SYSTEM_CALL;
 
-        __asm void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* FREERTOS_SYSTEM_CALL */
-        {
-            PRESERVE8
-            extern MPU_vTaskSuspendImpl
+__asm void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_vTaskSuspendImpl
 
-                push {
-                r0
-            }
-            mrs r0, control
-            tst r0, # 1
-            bne MPU_vTaskSuspend_Unpriv
-            MPU_vTaskSuspend_Priv
-                pop {
-                r0
-            }
-            b MPU_vTaskSuspendImpl
-            MPU_vTaskSuspend_Unpriv
-                pop {
-                r0
-            }
-            svc # portSVC_SYSTEM_CALL_ENTER
-            bl MPU_vTaskSuspendImpl
-            svc # portSVC_SYSTEM_CALL_EXIT
-            bx lr
-        }
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_vTaskSuspend_Unpriv
+MPU_vTaskSuspend_Priv
+        pop {r0}
+        b MPU_vTaskSuspendImpl
+MPU_vTaskSuspend_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_vTaskSuspend
+}
 
-    #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
+#endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
 /*-----------------------------------------------------------*/
 
-    #if ( INCLUDE_vTaskSuspend == 1 )
+#if ( INCLUDE_vTaskSuspend == 1 )
 
-        void MPU_vTaskResume( TaskHandle_t xTaskToResume ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskResume( TaskHandle_t xTaskToResume ) FREERTOS_SYSTEM_CALL;
 
-        __asm void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* FREERTOS_SYSTEM_CALL */
-        {
-            PRESERVE8
-            extern MPU_vTaskResumeImpl
+__asm void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_vTaskResumeImpl
 
-                push {
-                r0
-            }
-            mrs r0, control
-            tst r0, # 1
-            bne MPU_vTaskResume_Unpriv
-            MPU_vTaskResume_Priv
-                pop {
-                r0
-            }
-            b MPU_vTaskResumeImpl
-            MPU_vTaskResume_Unpriv
-                pop {
-                r0
-            }
-            svc # portSVC_SYSTEM_CALL_ENTER
-            bl MPU_vTaskResumeImpl
-            svc # portSVC_SYSTEM_CALL_EXIT
-            bx lr
-        }
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_vTaskResume_Unpriv
+MPU_vTaskResume_Priv
+        pop {r0}
+        b MPU_vTaskResumeImpl
+MPU_vTaskResume_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_vTaskResume
+}
 
-    #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
+#endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
 /*-----------------------------------------------------------*/
 
-    TickType_t MPU_xTaskGetTickCount( void ) FREERTOS_SYSTEM_CALL;
+TickType_t MPU_xTaskGetTickCount( void ) FREERTOS_SYSTEM_CALL;
 
-    __asm TickType_t MPU_xTaskGetTickCount( void ) /* FREERTOS_SYSTEM_CALL */
-    {
-        PRESERVE8
-        extern MPU_xTaskGetTickCountImpl
+__asm TickType_t MPU_xTaskGetTickCount( void ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_xTaskGetTickCountImpl
 
-            push {
-            r0
-        }
-        mrs r0, control
-        tst r0, # 1
-        bne MPU_xTaskGetTickCount_Unpriv
-        MPU_xTaskGetTickCount_Priv
-            pop {
-            r0
-        }
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_xTaskGetTickCount_Unpriv
+MPU_xTaskGetTickCount_Priv
+        pop {r0}
         b MPU_xTaskGetTickCountImpl
-        MPU_xTaskGetTickCount_Unpriv
-            pop {
-            r0
-        }
-        svc # portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskGetTickCountImpl
-        svc # portSVC_SYSTEM_CALL_EXIT
-        bx lr
-    }
+MPU_xTaskGetTickCount_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_xTaskGetTickCount
+}
 /*-----------------------------------------------------------*/
 
-    UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) FREERTOS_SYSTEM_CALL;
 
-    __asm UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* FREERTOS_SYSTEM_CALL */
-    {
-        PRESERVE8
-        extern MPU_uxTaskGetNumberOfTasksImpl
+__asm UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_uxTaskGetNumberOfTasksImpl
 
-            push {
-            r0
-        }
-        mrs r0, control
-        tst r0, # 1
-        bne MPU_uxTaskGetNumberOfTasks_Unpriv
-        MPU_uxTaskGetNumberOfTasks_Priv
-            pop {
-            r0
-        }
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_uxTaskGetNumberOfTasks_Unpriv
+MPU_uxTaskGetNumberOfTasks_Priv
+        pop {r0}
         b MPU_uxTaskGetNumberOfTasksImpl
-        MPU_uxTaskGetNumberOfTasks_Unpriv
-            pop {
-            r0
-        }
-        svc # portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxTaskGetNumberOfTasksImpl
-        svc # portSVC_SYSTEM_CALL_EXIT
-        bx lr
-    }
+MPU_uxTaskGetNumberOfTasks_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_uxTaskGetNumberOfTasks
+}
 /*-----------------------------------------------------------*/
 
-    #if ( configGENERATE_RUN_TIME_STATS == 1 )
+#if ( configGENERATE_RUN_TIME_STATS == 1 )
 
-        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
 
-        __asm configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
-        {
-            PRESERVE8
-            extern MPU_ulTaskGetRunTimeCounterImpl
+__asm configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_ulTaskGetRunTimeCounterImpl
 
-                push {
-                r0
-            }
-            mrs r0, control
-            tst r0, # 1
-            bne MPU_ulTaskGetRunTimeCounter_Unpriv
-            MPU_ulTaskGetRunTimeCounter_Priv
-                pop {
-                r0
-            }
-            b MPU_ulTaskGetRunTimeCounterImpl
-            MPU_ulTaskGetRunTimeCounter_Unpriv
-                pop {
-                r0
-            }
-            svc # portSVC_SYSTEM_CALL_ENTER
-            bl MPU_ulTaskGetRunTimeCounterImpl
-            svc # portSVC_SYSTEM_CALL_EXIT
-            bx lr
-        }
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_ulTaskGetRunTimeCounter_Unpriv
+MPU_ulTaskGetRunTimeCounter_Priv
+        pop {r0}
+        b MPU_ulTaskGetRunTimeCounterImpl
+MPU_ulTaskGetRunTimeCounter_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_ulTaskGetRunTimeCounter
+}
 
-    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
+#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    #if ( configGENERATE_RUN_TIME_STATS == 1 )
+#if ( configGENERATE_RUN_TIME_STATS == 1 )
 
-        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
 
-        __asm configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
-        {
-            PRESERVE8
-            extern MPU_ulTaskGetRunTimePercentImpl
+__asm configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_ulTaskGetRunTimePercentImpl
 
-                push {
-                r0
-            }
-            mrs r0, control
-            tst r0, # 1
-            bne MPU_ulTaskGetRunTimePercent_Unpriv
-            MPU_ulTaskGetRunTimePercent_Priv
-                pop {
-                r0
-            }
-            b MPU_ulTaskGetRunTimePercentImpl
-            MPU_ulTaskGetRunTimePercent_Unpriv
-                pop {
-                r0
-            }
-            svc # portSVC_SYSTEM_CALL_ENTER
-            bl MPU_ulTaskGetRunTimePercentImpl
-            svc # portSVC_SYSTEM_CALL_EXIT
-            bx lr
-        }
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_ulTaskGetRunTimePercent_Unpriv
+MPU_ulTaskGetRunTimePercent_Priv
+        pop {r0}
+        b MPU_ulTaskGetRunTimePercentImpl
+MPU_ulTaskGetRunTimePercent_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_ulTaskGetRunTimePercent
+}
 
-    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
+#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
 
-        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) FREERTOS_SYSTEM_CALL;
+configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) FREERTOS_SYSTEM_CALL;
 
-        __asm configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* FREERTOS_SYSTEM_CALL */
-        {
-            PRESERVE8
-            extern MPU_ulTaskGetIdleRunTimePercentImpl
+__asm configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_ulTaskGetIdleRunTimePercentImpl
 
-                push {
-                r0
-            }
-            mrs r0, control
-            tst r0, # 1
-            bne MPU_ulTaskGetIdleRunTimePercent_Unpriv
-            MPU_ulTaskGetIdleRunTimePercent_Priv
-                pop {
-                r0
-            }
-            b MPU_ulTaskGetIdleRunTimePercentImpl
-            MPU_ulTaskGetIdleRunTimePercent_Unpriv
-                pop {
-                r0
-            }
-            svc # portSVC_SYSTEM_CALL_ENTER
-            bl MPU_ulTaskGetIdleRunTimePercentImpl
-            svc # portSVC_SYSTEM_CALL_EXIT
-            bx lr
-        }
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_ulTaskGetIdleRunTimePercent_Unpriv
+MPU_ulTaskGetIdleRunTimePercent_Priv
+        pop {r0}
+        b MPU_ulTaskGetIdleRunTimePercentImpl
+MPU_ulTaskGetIdleRunTimePercent_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent
+}
 
-    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
+#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-    #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
 
-        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) FREERTOS_SYSTEM_CALL;
+configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) FREERTOS_SYSTEM_CALL;
 
-        __asm configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* FREERTOS_SYSTEM_CALL */
-        {
-            PRESERVE8
-            extern MPU_ulTaskGetIdleRunTimeCounterImpl
+__asm configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_ulTaskGetIdleRunTimeCounterImpl
 
-                push {
-                r0
-            }
-            mrs r0, control
-            tst r0, # 1
-            bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv
-            MPU_ulTaskGetIdleRunTimeCounter_Priv
-                pop {
-                r0
-            }
-            b MPU_ulTaskGetIdleRunTimeCounterImpl
-            MPU_ulTaskGetIdleRunTimeCounter_Unpriv
-                pop {
-                r0
-            }
-            svc # portSVC_SYSTEM_CALL_ENTER
-            bl MPU_ulTaskGetIdleRunTimeCounterImpl
-            svc # portSVC_SYSTEM_CALL_EXIT
-            bx lr
-        }
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv
+MPU_ulTaskGetIdleRunTimeCounter_Priv
+        pop {r0}
+        b MPU_ulTaskGetIdleRunTimeCounterImpl
+MPU_ulTaskGetIdleRunTimeCounter_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter
+}
 
-    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
+#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-    #if ( configUSE_APPLICATION_TASK_TAG == 1 )
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
 
-        void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
-                                             TaskHookFunction_t pxHookFunction ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
+                                     TaskHookFunction_t pxHookFunction ) FREERTOS_SYSTEM_CALL;
 
-        __asm void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
-                                                   TaskHookFunction_t pxHookFunction ) /* FREERTOS_SYSTEM_CALL */
-        {
-            PRESERVE8
-            extern MPU_vTaskSetApplicationTaskTagImpl
+__asm void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
+                                           TaskHookFunction_t pxHookFunction ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_vTaskSetApplicationTaskTagImpl
 
-                push {
-                r0
-            }
-            mrs r0, control
-            tst r0, # 1
-            bne MPU_vTaskSetApplicationTaskTag_Unpriv
-            MPU_vTaskSetApplicationTaskTag_Priv
-                pop {
-                r0
-            }
-            b MPU_vTaskSetApplicationTaskTagImpl
-            MPU_vTaskSetApplicationTaskTag_Unpriv
-                pop {
-                r0
-            }
-            svc # portSVC_SYSTEM_CALL_ENTER
-            bl MPU_vTaskSetApplicationTaskTagImpl
-            svc # portSVC_SYSTEM_CALL_EXIT
-            bx lr
-        }
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_vTaskSetApplicationTaskTag_Unpriv
+MPU_vTaskSetApplicationTaskTag_Priv
+        pop {r0}
+        b MPU_vTaskSetApplicationTaskTagImpl
+MPU_vTaskSetApplicationTaskTag_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_vTaskSetApplicationTaskTag
+}
 
-    #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
+#endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
 /*-----------------------------------------------------------*/
 
-    #if ( configUSE_APPLICATION_TASK_TAG == 1 )
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
 
-        TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
 
-        __asm TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
-        {
-            PRESERVE8
-            extern MPU_xTaskGetApplicationTaskTagImpl
+__asm TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_xTaskGetApplicationTaskTagImpl
 
-                push {
-                r0
-            }
-            mrs r0, control
-            tst r0, # 1
-            bne MPU_xTaskGetApplicationTaskTag_Unpriv
-            MPU_xTaskGetApplicationTaskTag_Priv
-                pop {
-                r0
-            }
-            b MPU_xTaskGetApplicationTaskTagImpl
-            MPU_xTaskGetApplicationTaskTag_Unpriv
-                pop {
-                r0
-            }
-            svc # portSVC_SYSTEM_CALL_ENTER
-            bl MPU_xTaskGetApplicationTaskTagImpl
-            svc # portSVC_SYSTEM_CALL_EXIT
-            bx lr
-        }
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_xTaskGetApplicationTaskTag_Unpriv
+MPU_xTaskGetApplicationTaskTag_Priv
+        pop {r0}
+        b MPU_xTaskGetApplicationTaskTagImpl
+MPU_xTaskGetApplicationTaskTag_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_xTaskGetApplicationTaskTag
+}
 
-    #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
+#endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
 /*-----------------------------------------------------------*/
 
-    #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
 
-        void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
-                                                    BaseType_t xIndex,
-                                                    void * pvValue ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
+                                            BaseType_t xIndex,
+                                            void * pvValue ) FREERTOS_SYSTEM_CALL;
 
-        __asm void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
-                                                          BaseType_t xIndex,
-                                                          void * pvValue ) /* FREERTOS_SYSTEM_CALL */
-        {
-            PRESERVE8
-            extern MPU_vTaskSetThreadLocalStoragePointerImpl
+__asm void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
+                                                  BaseType_t xIndex,
+                                                  void * pvValue ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_vTaskSetThreadLocalStoragePointerImpl
 
-                push {
-                r0
-            }
-            mrs r0, control
-            tst r0, # 1
-            bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv
-            MPU_vTaskSetThreadLocalStoragePointer_Priv
-                pop {
-                r0
-            }
-            b MPU_vTaskSetThreadLocalStoragePointerImpl
-            MPU_vTaskSetThreadLocalStoragePointer_Unpriv
-                pop {
-                r0
-            }
-            svc # portSVC_SYSTEM_CALL_ENTER
-            bl MPU_vTaskSetThreadLocalStoragePointerImpl
-            svc # portSVC_SYSTEM_CALL_EXIT
-            bx lr
-        }
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv
+MPU_vTaskSetThreadLocalStoragePointer_Priv
+        pop {r0}
+        b MPU_vTaskSetThreadLocalStoragePointerImpl
+MPU_vTaskSetThreadLocalStoragePointer_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer
+}
 
-    #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
+#endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
 /*-----------------------------------------------------------*/
 
-    #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
 
-        void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
-                                                       BaseType_t xIndex ) FREERTOS_SYSTEM_CALL;
+void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
+                                               BaseType_t xIndex ) FREERTOS_SYSTEM_CALL;
 
-        __asm void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
-                                                             BaseType_t xIndex ) /* FREERTOS_SYSTEM_CALL */
-        {
-            PRESERVE8
-            extern MPU_pvTaskGetThreadLocalStoragePointerImpl
+__asm void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
+                                                     BaseType_t xIndex ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_pvTaskGetThreadLocalStoragePointerImpl
 
-                push {
-                r0
-            }
-            mrs r0, control
-            tst r0, # 1
-            bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv
-            MPU_pvTaskGetThreadLocalStoragePointer_Priv
-                pop {
-                r0
-            }
-            b MPU_pvTaskGetThreadLocalStoragePointerImpl
-            MPU_pvTaskGetThreadLocalStoragePointer_Unpriv
-                pop {
-                r0
-            }
-            svc # portSVC_SYSTEM_CALL_ENTER
-            bl MPU_pvTaskGetThreadLocalStoragePointerImpl
-            svc # portSVC_SYSTEM_CALL_EXIT
-            bx lr
-        }
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv
+MPU_pvTaskGetThreadLocalStoragePointer_Priv
+        pop {r0}
+        b MPU_pvTaskGetThreadLocalStoragePointerImpl
+MPU_pvTaskGetThreadLocalStoragePointer_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer
+}
 
-    #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
+#endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
 /*-----------------------------------------------------------*/
 
-    #if ( configUSE_TRACE_FACILITY == 1 )
+#if ( configUSE_TRACE_FACILITY == 1 )
 
-        UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
-                                              const UBaseType_t uxArraySize,
-                                              configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
+                                      const UBaseType_t uxArraySize,
+                                      configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) FREERTOS_SYSTEM_CALL;
 
-        __asm UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
-                                                    const UBaseType_t uxArraySize,
-                                                    configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* FREERTOS_SYSTEM_CALL */
-        {
-            PRESERVE8
-            extern MPU_uxTaskGetSystemStateImpl
+__asm UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
+                                            const UBaseType_t uxArraySize,
+                                            configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_uxTaskGetSystemStateImpl
 
-                push {
-                r0
-            }
-            mrs r0, control
-            tst r0, # 1
-            bne MPU_uxTaskGetSystemState_Unpriv
-            MPU_uxTaskGetSystemState_Priv
-                pop {
-                r0
-            }
-            b MPU_uxTaskGetSystemStateImpl
-            MPU_uxTaskGetSystemState_Unpriv
-                pop {
-                r0
-            }
-            svc # portSVC_SYSTEM_CALL_ENTER
-            bl MPU_uxTaskGetSystemStateImpl
-            svc # portSVC_SYSTEM_CALL_EXIT
-            bx lr
-        }
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_uxTaskGetSystemState_Unpriv
+MPU_uxTaskGetSystemState_Priv
+        pop {r0}
+        b MPU_uxTaskGetSystemStateImpl
+MPU_uxTaskGetSystemState_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_uxTaskGetSystemState
+}
 
-    #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
+#endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
 /*-----------------------------------------------------------*/
 
-    #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
+#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
 
-        UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
 
-        __asm UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
-        {
-            PRESERVE8
-            extern MPU_uxTaskGetStackHighWaterMarkImpl
+__asm UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_uxTaskGetStackHighWaterMarkImpl
 
-                push {
-                r0
-            }
-            mrs r0, control
-            tst r0, # 1
-            bne MPU_uxTaskGetStackHighWaterMark_Unpriv
-            MPU_uxTaskGetStackHighWaterMark_Priv
-                pop {
-                r0
-            }
-            b MPU_uxTaskGetStackHighWaterMarkImpl
-            MPU_uxTaskGetStackHighWaterMark_Unpriv
-                pop {
-                r0
-            }
-            svc # portSVC_SYSTEM_CALL_ENTER
-            bl MPU_uxTaskGetStackHighWaterMarkImpl
-            svc # portSVC_SYSTEM_CALL_EXIT
-            bx lr
-        }
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_uxTaskGetStackHighWaterMark_Unpriv
+MPU_uxTaskGetStackHighWaterMark_Priv
+        pop {r0}
+        b MPU_uxTaskGetStackHighWaterMarkImpl
+MPU_uxTaskGetStackHighWaterMark_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark
+}
 
-    #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */
+#endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */
 /*-----------------------------------------------------------*/
 
-    #if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
+#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
 
-        configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
 
-        __asm configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
-        {
-            PRESERVE8
-            extern MPU_uxTaskGetStackHighWaterMark2Impl
+__asm configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_uxTaskGetStackHighWaterMark2Impl
 
-                push {
-                r0
-            }
-            mrs r0, control
-            tst r0, # 1
-            bne MPU_uxTaskGetStackHighWaterMark2_Unpriv
-            MPU_uxTaskGetStackHighWaterMark2_Priv
-                pop {
-                r0
-            }
-            b MPU_uxTaskGetStackHighWaterMark2Impl
-            MPU_uxTaskGetStackHighWaterMark2_Unpriv
-                pop {
-                r0
-            }
-            svc # portSVC_SYSTEM_CALL_ENTER
-            bl MPU_uxTaskGetStackHighWaterMark2Impl
-            svc # portSVC_SYSTEM_CALL_EXIT
-            bx lr
-        }
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_uxTaskGetStackHighWaterMark2_Unpriv
+MPU_uxTaskGetStackHighWaterMark2_Priv
+        pop {r0}
+        b MPU_uxTaskGetStackHighWaterMark2Impl
+MPU_uxTaskGetStackHighWaterMark2_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2
+}
 
-    #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */
+#endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */
 /*-----------------------------------------------------------*/
 
-    #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
+#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
 
-        TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) FREERTOS_SYSTEM_CALL;
 
-        __asm TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* FREERTOS_SYSTEM_CALL */
-        {
-            PRESERVE8
-            extern MPU_xTaskGetCurrentTaskHandleImpl
+__asm TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_xTaskGetCurrentTaskHandleImpl
 
-                push {
-                r0
-            }
-            mrs r0, control
-            tst r0, # 1
-            bne MPU_xTaskGetCurrentTaskHandle_Unpriv
-            MPU_xTaskGetCurrentTaskHandle_Priv
-                pop {
-                r0
-            }
-            b MPU_xTaskGetCurrentTaskHandleImpl
-            MPU_xTaskGetCurrentTaskHandle_Unpriv
-                pop {
-                r0
-            }
-            svc # portSVC_SYSTEM_CALL_ENTER
-            bl MPU_xTaskGetCurrentTaskHandleImpl
-            svc # portSVC_SYSTEM_CALL_EXIT
-            bx lr
-        }
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_xTaskGetCurrentTaskHandle_Unpriv
+MPU_xTaskGetCurrentTaskHandle_Priv
+        pop {r0}
+        b MPU_xTaskGetCurrentTaskHandleImpl
+MPU_xTaskGetCurrentTaskHandle_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle
+}
 
-    #endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
+#endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-    #if ( INCLUDE_xTaskGetSchedulerState == 1 )
+#if ( INCLUDE_xTaskGetSchedulerState == 1 )
 
-        BaseType_t MPU_xTaskGetSchedulerState( void ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskGetSchedulerState( void ) FREERTOS_SYSTEM_CALL;
 
-        __asm BaseType_t MPU_xTaskGetSchedulerState( void ) /* FREERTOS_SYSTEM_CALL */
-        {
-            PRESERVE8
-            extern MPU_xTaskGetSchedulerStateImpl
+__asm BaseType_t MPU_xTaskGetSchedulerState( void ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_xTaskGetSchedulerStateImpl
 
-                push {
-                r0
-            }
-            mrs r0, control
-            tst r0, # 1
-            bne MPU_xTaskGetSchedulerState_Unpriv
-            MPU_xTaskGetSchedulerState_Priv
-                pop {
-                r0
-            }
-            b MPU_xTaskGetSchedulerStateImpl
-            MPU_xTaskGetSchedulerState_Unpriv
-                pop {
-                r0
-            }
-            svc # portSVC_SYSTEM_CALL_ENTER
-            bl MPU_xTaskGetSchedulerStateImpl
-            svc # portSVC_SYSTEM_CALL_EXIT
-            bx lr
-        }
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_xTaskGetSchedulerState_Unpriv
+MPU_xTaskGetSchedulerState_Priv
+        pop {r0}
+        b MPU_xTaskGetSchedulerStateImpl
+MPU_xTaskGetSchedulerState_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_xTaskGetSchedulerState
+}
 
-    #endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */
+#endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */
 /*-----------------------------------------------------------*/
 
-    void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) FREERTOS_SYSTEM_CALL;
 
-    __asm void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* FREERTOS_SYSTEM_CALL */
-    {
-        PRESERVE8
-        extern MPU_vTaskSetTimeOutStateImpl
+__asm void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_vTaskSetTimeOutStateImpl
 
-            push {
-            r0
-        }
-        mrs r0, control
-        tst r0, # 1
-        bne MPU_vTaskSetTimeOutState_Unpriv
-        MPU_vTaskSetTimeOutState_Priv
-            pop {
-            r0
-        }
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_vTaskSetTimeOutState_Unpriv
+MPU_vTaskSetTimeOutState_Priv
+        pop {r0}
         b MPU_vTaskSetTimeOutStateImpl
-        MPU_vTaskSetTimeOutState_Unpriv
-            pop {
-            r0
-        }
-        svc # portSVC_SYSTEM_CALL_ENTER
-        bl MPU_vTaskSetTimeOutStateImpl
-        svc # portSVC_SYSTEM_CALL_EXIT
-        bx lr
-    }
+MPU_vTaskSetTimeOutState_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_vTaskSetTimeOutState
+}
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
-                                         TickType_t * const pxTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
+                                     TickType_t * const pxTicksToWait ) FREERTOS_SYSTEM_CALL;
 
-    __asm BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
-                                               TickType_t * const pxTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-    {
-        PRESERVE8
-        extern MPU_xTaskCheckForTimeOutImpl
+__asm BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
+                                     TickType_t * const pxTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_xTaskCheckForTimeOutImpl
 
-            push {
-            r0
-        }
-        mrs r0, control
-        tst r0, # 1
-        bne MPU_xTaskCheckForTimeOut_Unpriv
-        MPU_xTaskCheckForTimeOut_Priv
-            pop {
-            r0
-        }
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_xTaskCheckForTimeOut_Unpriv
+MPU_xTaskCheckForTimeOut_Priv
+        pop {r0}
         b MPU_xTaskCheckForTimeOutImpl
-        MPU_xTaskCheckForTimeOut_Unpriv
-            pop {
-            r0
-        }
-        svc # portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xTaskCheckForTimeOutImpl
-        svc # portSVC_SYSTEM_CALL_EXIT
-        bx lr
-    }
+MPU_xTaskCheckForTimeOut_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_xTaskCheckForTimeOut
+}
 /*-----------------------------------------------------------*/
 
-    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
+#if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-        BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                           UBaseType_t uxIndexToNotify,
-                                           uint32_t ulValue,
-                                           eNotifyAction eAction,
-                                           uint32_t * pulPreviousNotificationValue ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) FREERTOS_SYSTEM_CALL;
 
-        __asm BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
-                                                 UBaseType_t uxIndexToNotify,
-                                                 uint32_t ulValue,
-                                                 eNotifyAction eAction,
-                                                 uint32_t * pulPreviousNotificationValue ) /* FREERTOS_SYSTEM_CALL */
-        {
-            PRESERVE8
-            extern MPU_xTaskGenericNotifyImpl
+__asm BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_xTaskGenericNotifyImpl
 
-                push {
-                r0
-            }
-            mrs r0, control
-            tst r0, # 1
-            bne MPU_xTaskGenericNotify_Unpriv
-            MPU_xTaskGenericNotify_Priv
-                pop {
-                r0
-            }
-            b MPU_xTaskGenericNotifyImpl
-            MPU_xTaskGenericNotify_Unpriv
-                pop {
-                r0
-            }
-            svc # portSVC_SYSTEM_CALL_ENTER_1
-            bl MPU_xTaskGenericNotifyImpl
-            svc # portSVC_SYSTEM_CALL_EXIT
-            bx lr
-        }
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_xTaskGenericNotify_Unpriv
+MPU_xTaskGenericNotify_Priv
+        pop {r0}
+        b MPU_xTaskGenericNotifyImpl
+MPU_xTaskGenericNotify_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_xTaskGenericNotify
+}
 
-    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
+#if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-        BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                               uint32_t ulBitsToClearOnEntry,
-                                               uint32_t ulBitsToClearOnExit,
-                                               uint32_t * pulNotificationValue,
-                                               TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) FREERTOS_SYSTEM_CALL;
 
-        __asm BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
-                                                     uint32_t ulBitsToClearOnEntry,
-                                                     uint32_t ulBitsToClearOnExit,
-                                                     uint32_t * pulNotificationValue,
-                                                     TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-        {
-            PRESERVE8
-            extern MPU_xTaskGenericNotifyWaitImpl
+__asm BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_xTaskGenericNotifyWaitImpl
 
-                push {
-                r0
-            }
-            mrs r0, control
-            tst r0, # 1
-            bne MPU_xTaskGenericNotifyWait_Unpriv
-            MPU_xTaskGenericNotifyWait_Priv
-                pop {
-                r0
-            }
-            b MPU_xTaskGenericNotifyWaitImpl
-            MPU_xTaskGenericNotifyWait_Unpriv
-                pop {
-                r0
-            }
-            svc # portSVC_SYSTEM_CALL_ENTER_1
-            bl MPU_xTaskGenericNotifyWaitImpl
-            svc # portSVC_SYSTEM_CALL_EXIT
-            bx lr
-        }
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_xTaskGenericNotifyWait_Unpriv
+MPU_xTaskGenericNotifyWait_Priv
+        pop {r0}
+        b MPU_xTaskGenericNotifyWaitImpl
+MPU_xTaskGenericNotifyWait_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_xTaskGenericNotifyWait
+}
 
-    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
+#if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-        uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
-                                              BaseType_t xClearCountOnExit,
-                                              TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
+                                      BaseType_t xClearCountOnExit,
+                                      TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
 
-        __asm uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
-                                                    BaseType_t xClearCountOnExit,
-                                                    TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-        {
-            PRESERVE8
-            extern MPU_ulTaskGenericNotifyTakeImpl
+__asm uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
+                                            BaseType_t xClearCountOnExit,
+                                            TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_ulTaskGenericNotifyTakeImpl
 
-                push {
-                r0
-            }
-            mrs r0, control
-            tst r0, # 1
-            bne MPU_ulTaskGenericNotifyTake_Unpriv
-            MPU_ulTaskGenericNotifyTake_Priv
-                pop {
-                r0
-            }
-            b MPU_ulTaskGenericNotifyTakeImpl
-            MPU_ulTaskGenericNotifyTake_Unpriv
-                pop {
-                r0
-            }
-            svc # portSVC_SYSTEM_CALL_ENTER
-            bl MPU_ulTaskGenericNotifyTakeImpl
-            svc # portSVC_SYSTEM_CALL_EXIT
-            bx lr
-        }
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_ulTaskGenericNotifyTake_Unpriv
+MPU_ulTaskGenericNotifyTake_Priv
+        pop {r0}
+        b MPU_ulTaskGenericNotifyTakeImpl
+MPU_ulTaskGenericNotifyTake_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_ulTaskGenericNotifyTake
+}
 
-    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
+#if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-        BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
-                                                     UBaseType_t uxIndexToClear ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
+                                             UBaseType_t uxIndexToClear ) FREERTOS_SYSTEM_CALL;
 
-        __asm BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
-                                                           UBaseType_t uxIndexToClear ) /* FREERTOS_SYSTEM_CALL */
-        {
-            PRESERVE8
-            extern MPU_xTaskGenericNotifyStateClearImpl
+__asm BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
+                                                   UBaseType_t uxIndexToClear ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_xTaskGenericNotifyStateClearImpl
 
-                push {
-                r0
-            }
-            mrs r0, control
-            tst r0, # 1
-            bne MPU_xTaskGenericNotifyStateClear_Unpriv
-            MPU_xTaskGenericNotifyStateClear_Priv
-                pop {
-                r0
-            }
-            b MPU_xTaskGenericNotifyStateClearImpl
-            MPU_xTaskGenericNotifyStateClear_Unpriv
-                pop {
-                r0
-            }
-            svc # portSVC_SYSTEM_CALL_ENTER
-            bl MPU_xTaskGenericNotifyStateClearImpl
-            svc # portSVC_SYSTEM_CALL_EXIT
-            bx lr
-        }
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_xTaskGenericNotifyStateClear_Unpriv
+MPU_xTaskGenericNotifyStateClear_Priv
+        pop {r0}
+        b MPU_xTaskGenericNotifyStateClearImpl
+MPU_xTaskGenericNotifyStateClear_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_xTaskGenericNotifyStateClear
+}
 
-    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
+#if ( configUSE_TASK_NOTIFICATIONS == 1 )
 
-        uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
-                                                    UBaseType_t uxIndexToClear,
-                                                    uint32_t ulBitsToClear ) FREERTOS_SYSTEM_CALL;
+uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
+                                            UBaseType_t uxIndexToClear,
+                                            uint32_t ulBitsToClear ) FREERTOS_SYSTEM_CALL;
 
-        __asm uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
-                                                          UBaseType_t uxIndexToClear,
-                                                          uint32_t ulBitsToClear ) /* FREERTOS_SYSTEM_CALL */
-        {
-            PRESERVE8
-            extern MPU_ulTaskGenericNotifyValueClearImpl
+__asm uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
+                                                  UBaseType_t uxIndexToClear,
+                                                  uint32_t ulBitsToClear ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_ulTaskGenericNotifyValueClearImpl
 
-                push {
-                r0
-            }
-            mrs r0, control
-            tst r0, # 1
-            bne MPU_ulTaskGenericNotifyValueClear_Unpriv
-            MPU_ulTaskGenericNotifyValueClear_Priv
-                pop {
-                r0
-            }
-            b MPU_ulTaskGenericNotifyValueClearImpl
-            MPU_ulTaskGenericNotifyValueClear_Unpriv
-                pop {
-                r0
-            }
-            svc # portSVC_SYSTEM_CALL_ENTER
-            bl MPU_ulTaskGenericNotifyValueClearImpl
-            svc # portSVC_SYSTEM_CALL_EXIT
-            bx lr
-        }
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_ulTaskGenericNotifyValueClear_Unpriv
+MPU_ulTaskGenericNotifyValueClear_Priv
+        pop {r0}
+        b MPU_ulTaskGenericNotifyValueClearImpl
+MPU_ulTaskGenericNotifyValueClear_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear
+}
 
-    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
-                                      const void * const pvItemToQueue,
-                                      TickType_t xTicksToWait,
-                                      const BaseType_t xCopyPosition ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
+                                  const void * const pvItemToQueue,
+                                  TickType_t xTicksToWait,
+                                  const BaseType_t xCopyPosition ) FREERTOS_SYSTEM_CALL;
 
-    __asm BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
-                                            const void * const pvItemToQueue,
-                                            TickType_t xTicksToWait,
-                                            const BaseType_t xCopyPosition ) /* FREERTOS_SYSTEM_CALL */
-    {
-        PRESERVE8
-        extern MPU_xQueueGenericSendImpl
+__asm BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
+                                        const void * const pvItemToQueue,
+                                        TickType_t xTicksToWait,
+                                        const BaseType_t xCopyPosition ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_xQueueGenericSendImpl
 
-            push {
-            r0
-        }
-        mrs r0, control
-        tst r0, # 1
-        bne MPU_xQueueGenericSend_Unpriv
-        MPU_xQueueGenericSend_Priv
-            pop {
-            r0
-        }
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_xQueueGenericSend_Unpriv
+MPU_xQueueGenericSend_Priv
+        pop {r0}
         b MPU_xQueueGenericSendImpl
-        MPU_xQueueGenericSend_Unpriv
-            pop {
-            r0
-        }
-        svc # portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueGenericSendImpl
-        svc # portSVC_SYSTEM_CALL_EXIT
-        bx lr
-    }
+MPU_xQueueGenericSend_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_xQueueGenericSend
+}
 /*-----------------------------------------------------------*/
 
-    UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
 
-    __asm UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */
-    {
-        PRESERVE8
-        extern MPU_uxQueueMessagesWaitingImpl
+__asm UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_uxQueueMessagesWaitingImpl
 
-            push {
-            r0
-        }
-        mrs r0, control
-        tst r0, # 1
-        bne MPU_uxQueueMessagesWaiting_Unpriv
-        MPU_uxQueueMessagesWaiting_Priv
-            pop {
-            r0
-        }
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_uxQueueMessagesWaiting_Unpriv
+MPU_uxQueueMessagesWaiting_Priv
+        pop {r0}
         b MPU_uxQueueMessagesWaitingImpl
-        MPU_uxQueueMessagesWaiting_Unpriv
-            pop {
-            r0
-        }
-        svc # portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxQueueMessagesWaitingImpl
-        svc # portSVC_SYSTEM_CALL_EXIT
-        bx lr
-    }
+MPU_uxQueueMessagesWaiting_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_uxQueueMessagesWaiting
+}
 /*-----------------------------------------------------------*/
 
-    UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
 
-    __asm UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */
-    {
-        PRESERVE8
-        extern MPU_uxQueueSpacesAvailableImpl
+__asm UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_uxQueueSpacesAvailableImpl
 
-            push {
-            r0
-        }
-        mrs r0, control
-        tst r0, # 1
-        bne MPU_uxQueueSpacesAvailable_Unpriv
-        MPU_uxQueueSpacesAvailable_Priv
-            pop {
-            r0
-        }
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_uxQueueSpacesAvailable_Unpriv
+MPU_uxQueueSpacesAvailable_Priv
+        pop {r0}
         b MPU_uxQueueSpacesAvailableImpl
-        MPU_uxQueueSpacesAvailable_Unpriv
-            pop {
-            r0
-        }
-        svc # portSVC_SYSTEM_CALL_ENTER
-        bl MPU_uxQueueSpacesAvailableImpl
-        svc # portSVC_SYSTEM_CALL_EXIT
-        bx lr
-    }
+MPU_uxQueueSpacesAvailable_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_uxQueueSpacesAvailable
+}
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
-                                  void * const pvBuffer,
-                                  TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
+                              void * const pvBuffer,
+                              TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
 
-    __asm BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
-                                        void * const pvBuffer,
-                                        TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-    {
-        PRESERVE8
-        extern MPU_xQueueReceiveImpl
+__asm BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
+                                    void * const pvBuffer,
+                                    TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_xQueueReceiveImpl
 
-            push {
-            r0
-        }
-        mrs r0, control
-        tst r0, # 1
-        bne MPU_xQueueReceive_Unpriv
-        MPU_xQueueReceive_Priv
-            pop {
-            r0
-        }
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_xQueueReceive_Unpriv
+MPU_xQueueReceive_Priv
+        pop {r0}
         b MPU_xQueueReceiveImpl
-        MPU_xQueueReceive_Unpriv
-            pop {
-            r0
-        }
-        svc # portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueReceiveImpl
-        svc # portSVC_SYSTEM_CALL_EXIT
-        bx lr
-    }
+MPU_xQueueReceive_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_xQueueReceive
+}
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
-                               void * const pvBuffer,
-                               TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
+                           void * const pvBuffer,
+                           TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
 
-    __asm BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
-                                     void * const pvBuffer,
-                                     TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-    {
-        PRESERVE8
-        extern MPU_xQueuePeekImpl
+__asm BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
+                                 void * const pvBuffer,
+                                 TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_xQueuePeekImpl
 
-            push {
-            r0
-        }
-        mrs r0, control
-        tst r0, # 1
-        bne MPU_xQueuePeek_Unpriv
-        MPU_xQueuePeek_Priv
-            pop {
-            r0
-        }
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_xQueuePeek_Unpriv
+MPU_xQueuePeek_Priv
+        pop {r0}
         b MPU_xQueuePeekImpl
-        MPU_xQueuePeek_Unpriv
-            pop {
-            r0
-        }
-        svc # portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueuePeekImpl
-        svc # portSVC_SYSTEM_CALL_EXIT
-        bx lr
-    }
+MPU_xQueuePeek_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_xQueuePeek
+}
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
-                                        TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
+                                    TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
 
-    __asm BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
-                                              TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-    {
-        PRESERVE8
-        extern MPU_xQueueSemaphoreTakeImpl
+__asm BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
+                                          TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_xQueueSemaphoreTakeImpl
 
-            push {
-            r0
-        }
-        mrs r0, control
-        tst r0, # 1
-        bne MPU_xQueueSemaphoreTake_Unpriv
-        MPU_xQueueSemaphoreTake_Priv
-            pop {
-            r0
-        }
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_xQueueSemaphoreTake_Unpriv
+MPU_xQueueSemaphoreTake_Priv
+        pop {r0}
         b MPU_xQueueSemaphoreTakeImpl
-        MPU_xQueueSemaphoreTake_Unpriv
-            pop {
-            r0
-        }
-        svc # portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xQueueSemaphoreTakeImpl
-        svc # portSVC_SYSTEM_CALL_EXIT
-        bx lr
-    }
+MPU_xQueueSemaphoreTake_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_xQueueSemaphoreTake
+}
 /*-----------------------------------------------------------*/
 
-    #if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
 
-        TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) FREERTOS_SYSTEM_CALL;
 
-        __asm TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* FREERTOS_SYSTEM_CALL */
-        {
-            PRESERVE8
-            extern MPU_xQueueGetMutexHolderImpl
+__asm TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_xQueueGetMutexHolderImpl
 
-                push {
-                r0
-            }
-            mrs r0, control
-            tst r0, # 1
-            bne MPU_xQueueGetMutexHolder_Unpriv
-            MPU_xQueueGetMutexHolder_Priv
-                pop {
-                r0
-            }
-            b MPU_xQueueGetMutexHolderImpl
-            MPU_xQueueGetMutexHolder_Unpriv
-                pop {
-                r0
-            }
-            svc # portSVC_SYSTEM_CALL_ENTER
-            bl MPU_xQueueGetMutexHolderImpl
-            svc # portSVC_SYSTEM_CALL_EXIT
-            bx lr
-        }
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_xQueueGetMutexHolder_Unpriv
+MPU_xQueueGetMutexHolder_Priv
+        pop {r0}
+        b MPU_xQueueGetMutexHolderImpl
+MPU_xQueueGetMutexHolder_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_xQueueGetMutexHolder
+}
 
-    #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */
+#endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-    #if ( configUSE_RECURSIVE_MUTEXES == 1 )
+#if ( configUSE_RECURSIVE_MUTEXES == 1 )
 
-        BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
-                                                 TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-
-        __asm BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
-                                                       TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-        {
-            PRESERVE8
-            extern MPU_xQueueTakeMutexRecursiveImpl
-
-                push {
-                r0
-            }
-            mrs r0, control
-            tst r0, # 1
-            bne MPU_xQueueTakeMutexRecursive_Unpriv
-            MPU_xQueueTakeMutexRecursive_Priv
-                pop {
-                r0
-            }
-            b MPU_xQueueTakeMutexRecursiveImpl
-            MPU_xQueueTakeMutexRecursive_Unpriv
-                pop {
-                r0
-            }
-            svc # portSVC_SYSTEM_CALL_ENTER
-            bl MPU_xQueueTakeMutexRecursiveImpl
-            svc # portSVC_SYSTEM_CALL_EXIT
-            bx lr
-        }
-
-    #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
-/*-----------------------------------------------------------*/
-
-    #if ( configUSE_RECURSIVE_MUTEXES == 1 )
-
-        BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) FREERTOS_SYSTEM_CALL;
-
-        __asm BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* FREERTOS_SYSTEM_CALL */
-        {
-            PRESERVE8
-            extern MPU_xQueueGiveMutexRecursiveImpl
-
-                push {
-                r0
-            }
-            mrs r0, control
-            tst r0, # 1
-            bne MPU_xQueueGiveMutexRecursive_Unpriv
-            MPU_xQueueGiveMutexRecursive_Priv
-                pop {
-                r0
-            }
-            b MPU_xQueueGiveMutexRecursiveImpl
-            MPU_xQueueGiveMutexRecursive_Unpriv
-                pop {
-                r0
-            }
-            svc # portSVC_SYSTEM_CALL_ENTER
-            bl MPU_xQueueGiveMutexRecursiveImpl
-            svc # portSVC_SYSTEM_CALL_EXIT
-            bx lr
-        }
-
-    #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
-/*-----------------------------------------------------------*/
-
-    #if ( configUSE_QUEUE_SETS == 1 )
-
-        QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
-                                                        const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-
-        __asm QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
-                                                              const TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-        {
-            PRESERVE8
-            extern MPU_xQueueSelectFromSetImpl
-
-                push {
-                r0
-            }
-            mrs r0, control
-            tst r0, # 1
-            bne MPU_xQueueSelectFromSet_Unpriv
-            MPU_xQueueSelectFromSet_Priv
-                pop {
-                r0
-            }
-            b MPU_xQueueSelectFromSetImpl
-            MPU_xQueueSelectFromSet_Unpriv
-                pop {
-                r0
-            }
-            svc # portSVC_SYSTEM_CALL_ENTER
-            bl MPU_xQueueSelectFromSetImpl
-            svc # portSVC_SYSTEM_CALL_EXIT
-            bx lr
-        }
-
-    #endif /* if ( configUSE_QUEUE_SETS == 1 ) */
-/*-----------------------------------------------------------*/
-
-    #if ( configUSE_QUEUE_SETS == 1 )
-
-        BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
-                                       QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL;
-
-        __asm BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
-                                             QueueSetHandle_t xQueueSet ) /* FREERTOS_SYSTEM_CALL */
-        {
-            PRESERVE8
-            extern MPU_xQueueAddToSetImpl
-
-                push {
-                r0
-            }
-            mrs r0, control
-            tst r0, # 1
-            bne MPU_xQueueAddToSet_Unpriv
-            MPU_xQueueAddToSet_Priv
-                pop {
-                r0
-            }
-            b MPU_xQueueAddToSetImpl
-            MPU_xQueueAddToSet_Unpriv
-                pop {
-                r0
-            }
-            svc # portSVC_SYSTEM_CALL_ENTER
-            bl MPU_xQueueAddToSetImpl
-            svc # portSVC_SYSTEM_CALL_EXIT
-            bx lr
-        }
-
-    #endif /* if ( configUSE_QUEUE_SETS == 1 ) */
-/*-----------------------------------------------------------*/
-
-    #if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-        void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
-                                      const char * pcName ) FREERTOS_SYSTEM_CALL;
-
-        __asm void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
-                                            const char * pcName ) /* FREERTOS_SYSTEM_CALL */
-        {
-            PRESERVE8
-            extern MPU_vQueueAddToRegistryImpl
-
-                push {
-                r0
-            }
-            mrs r0, control
-            tst r0, # 1
-            bne MPU_vQueueAddToRegistry_Unpriv
-            MPU_vQueueAddToRegistry_Priv
-                pop {
-                r0
-            }
-            b MPU_vQueueAddToRegistryImpl
-            MPU_vQueueAddToRegistry_Unpriv
-                pop {
-                r0
-            }
-            svc # portSVC_SYSTEM_CALL_ENTER
-            bl MPU_vQueueAddToRegistryImpl
-            svc # portSVC_SYSTEM_CALL_EXIT
-            bx lr
-        }
-
-    #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
-/*-----------------------------------------------------------*/
-
-    #if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-        void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
-
-        __asm void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */
-        {
-            PRESERVE8
-            extern MPU_vQueueUnregisterQueueImpl
-
-                push {
-                r0
-            }
-            mrs r0, control
-            tst r0, # 1
-            bne MPU_vQueueUnregisterQueue_Unpriv
-            MPU_vQueueUnregisterQueue_Priv
-                pop {
-                r0
-            }
-            b MPU_vQueueUnregisterQueueImpl
-            MPU_vQueueUnregisterQueue_Unpriv
-                pop {
-                r0
-            }
-            svc # portSVC_SYSTEM_CALL_ENTER
-            bl MPU_vQueueUnregisterQueueImpl
-            svc # portSVC_SYSTEM_CALL_EXIT
-            bx lr
-        }
-
-    #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
-/*-----------------------------------------------------------*/
-
-    #if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-        const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
-
-        __asm const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */
-        {
-            PRESERVE8
-            extern MPU_pcQueueGetNameImpl
-
-                push {
-                r0
-            }
-            mrs r0, control
-            tst r0, # 1
-            bne MPU_pcQueueGetName_Unpriv
-            MPU_pcQueueGetName_Priv
-                pop {
-                r0
-            }
-            b MPU_pcQueueGetNameImpl
-            MPU_pcQueueGetName_Unpriv
-                pop {
-                r0
-            }
-            svc # portSVC_SYSTEM_CALL_ENTER
-            bl MPU_pcQueueGetNameImpl
-            svc # portSVC_SYSTEM_CALL_EXIT
-            bx lr
-        }
-
-    #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
-/*-----------------------------------------------------------*/
-
-    #if ( configUSE_TIMERS == 1 )
-
-        void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
-
-        __asm void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
-        {
-            PRESERVE8
-            extern MPU_pvTimerGetTimerIDImpl
-
-                push {
-                r0
-            }
-            mrs r0, control
-            tst r0, # 1
-            bne MPU_pvTimerGetTimerID_Unpriv
-            MPU_pvTimerGetTimerID_Priv
-                pop {
-                r0
-            }
-            b MPU_pvTimerGetTimerIDImpl
-            MPU_pvTimerGetTimerID_Unpriv
-                pop {
-                r0
-            }
-            svc # portSVC_SYSTEM_CALL_ENTER
-            bl MPU_pvTimerGetTimerIDImpl
-            svc # portSVC_SYSTEM_CALL_EXIT
-            bx lr
-        }
-
-    #endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-    #if ( configUSE_TIMERS == 1 )
-
-        void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
-                                   void * pvNewID ) FREERTOS_SYSTEM_CALL;
-
-        __asm void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
-                                         void * pvNewID ) /* FREERTOS_SYSTEM_CALL */
-        {
-            PRESERVE8
-            extern MPU_vTimerSetTimerIDImpl
-
-                push {
-                r0
-            }
-            mrs r0, control
-            tst r0, # 1
-            bne MPU_vTimerSetTimerID_Unpriv
-            MPU_vTimerSetTimerID_Priv
-                pop {
-                r0
-            }
-            b MPU_vTimerSetTimerIDImpl
-            MPU_vTimerSetTimerID_Unpriv
-                pop {
-                r0
-            }
-            svc # portSVC_SYSTEM_CALL_ENTER
-            bl MPU_vTimerSetTimerIDImpl
-            svc # portSVC_SYSTEM_CALL_EXIT
-            bx lr
-        }
-
-    #endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-    #if ( configUSE_TIMERS == 1 )
-
-        BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
-
-        __asm BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
-        {
-            PRESERVE8
-            extern MPU_xTimerIsTimerActiveImpl
-
-                push {
-                r0
-            }
-            mrs r0, control
-            tst r0, # 1
-            bne MPU_xTimerIsTimerActive_Unpriv
-            MPU_xTimerIsTimerActive_Priv
-                pop {
-                r0
-            }
-            b MPU_xTimerIsTimerActiveImpl
-            MPU_xTimerIsTimerActive_Unpriv
-                pop {
-                r0
-            }
-            svc # portSVC_SYSTEM_CALL_ENTER
-            bl MPU_xTimerIsTimerActiveImpl
-            svc # portSVC_SYSTEM_CALL_EXIT
-            bx lr
-        }
-
-    #endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-    #if ( configUSE_TIMERS == 1 )
-
-        TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) FREERTOS_SYSTEM_CALL;
-
-        __asm TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* FREERTOS_SYSTEM_CALL */
-        {
-            PRESERVE8
-            extern MPU_xTimerGetTimerDaemonTaskHandleImpl
-
-                push {
-                r0
-            }
-            mrs r0, control
-            tst r0, # 1
-            bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv
-            MPU_xTimerGetTimerDaemonTaskHandle_Priv
-                pop {
-                r0
-            }
-            b MPU_xTimerGetTimerDaemonTaskHandleImpl
-            MPU_xTimerGetTimerDaemonTaskHandle_Unpriv
-                pop {
-                r0
-            }
-            svc # portSVC_SYSTEM_CALL_ENTER
-            bl MPU_xTimerGetTimerDaemonTaskHandleImpl
-            svc # portSVC_SYSTEM_CALL_EXIT
-            bx lr
-        }
-
-    #endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-    #if ( configUSE_TIMERS == 1 )
-
-        BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                                     const BaseType_t xCommandID,
-                                                     const TickType_t xOptionalValue,
-                                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                                     const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-
-        __asm BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
-                                                           const BaseType_t xCommandID,
-                                                           const TickType_t xOptionalValue,
-                                                           BaseType_t * const pxHigherPriorityTaskWoken,
-                                                           const TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-        {
-            PRESERVE8
-            extern MPU_xTimerGenericCommandFromTaskImpl
-
-                push {
-                r0
-            }
-            mrs r0, control
-            tst r0, # 1
-            bne MPU_xTimerGenericCommandFromTask_Unpriv
-            MPU_xTimerGenericCommandFromTask_Priv
-                pop {
-                r0
-            }
-            b MPU_xTimerGenericCommandFromTaskImpl
-            MPU_xTimerGenericCommandFromTask_Unpriv
-                pop {
-                r0
-            }
-            svc # portSVC_SYSTEM_CALL_ENTER_1
-            bl MPU_xTimerGenericCommandFromTaskImpl
-            svc # portSVC_SYSTEM_CALL_EXIT
-            bx lr
-        }
-
-    #endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-    #if ( configUSE_TIMERS == 1 )
-
-        const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
-
-        __asm const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
-        {
-            PRESERVE8
-            extern MPU_pcTimerGetNameImpl
-
-                push {
-                r0
-            }
-            mrs r0, control
-            tst r0, # 1
-            bne MPU_pcTimerGetName_Unpriv
-            MPU_pcTimerGetName_Priv
-                pop {
-                r0
-            }
-            b MPU_pcTimerGetNameImpl
-            MPU_pcTimerGetName_Unpriv
-                pop {
-                r0
-            }
-            svc # portSVC_SYSTEM_CALL_ENTER
-            bl MPU_pcTimerGetNameImpl
-            svc # portSVC_SYSTEM_CALL_EXIT
-            bx lr
-        }
-
-    #endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-    #if ( configUSE_TIMERS == 1 )
-
-        void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                                      const BaseType_t uxAutoReload ) FREERTOS_SYSTEM_CALL;
-
-        __asm void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                                            const BaseType_t uxAutoReload ) /* FREERTOS_SYSTEM_CALL */
-        {
-            PRESERVE8
-            extern MPU_vTimerSetReloadModeImpl
-
-                push {
-                r0
-            }
-            mrs r0, control
-            tst r0, # 1
-            bne MPU_vTimerSetReloadMode_Unpriv
-            MPU_vTimerSetReloadMode_Priv
-                pop {
-                r0
-            }
-            b MPU_vTimerSetReloadModeImpl
-            MPU_vTimerSetReloadMode_Unpriv
-                pop {
-                r0
-            }
-            svc # portSVC_SYSTEM_CALL_ENTER
-            bl MPU_vTimerSetReloadModeImpl
-            svc # portSVC_SYSTEM_CALL_EXIT
-            bx lr
-        }
-
-    #endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-    #if ( configUSE_TIMERS == 1 )
-
-        BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
-
-        __asm BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
-        {
-            PRESERVE8
-            extern MPU_xTimerGetReloadModeImpl
-
-                push {
-                r0
-            }
-            mrs r0, control
-            tst r0, # 1
-            bne MPU_xTimerGetReloadMode_Unpriv
-            MPU_xTimerGetReloadMode_Priv
-                pop {
-                r0
-            }
-            b MPU_xTimerGetReloadModeImpl
-            MPU_xTimerGetReloadMode_Unpriv
-                pop {
-                r0
-            }
-            svc # portSVC_SYSTEM_CALL_ENTER
-            bl MPU_xTimerGetReloadModeImpl
-            svc # portSVC_SYSTEM_CALL_EXIT
-            bx lr
-        }
-
-    #endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-    #if ( configUSE_TIMERS == 1 )
-
-        UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
-
-        __asm UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
-        {
-            PRESERVE8
-            extern MPU_uxTimerGetReloadModeImpl
-
-                push {
-                r0
-            }
-            mrs r0, control
-            tst r0, # 1
-            bne MPU_uxTimerGetReloadMode_Unpriv
-            MPU_uxTimerGetReloadMode_Priv
-                pop {
-                r0
-            }
-            b MPU_uxTimerGetReloadModeImpl
-            MPU_uxTimerGetReloadMode_Unpriv
-                pop {
-                r0
-            }
-            svc # portSVC_SYSTEM_CALL_ENTER
-            bl MPU_uxTimerGetReloadModeImpl
-            svc # portSVC_SYSTEM_CALL_EXIT
-            bx lr
-        }
-
-    #endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-    #if ( configUSE_TIMERS == 1 )
-
-        TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
-
-        __asm TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
-        {
-            PRESERVE8
-            extern MPU_xTimerGetPeriodImpl
-
-                push {
-                r0
-            }
-            mrs r0, control
-            tst r0, # 1
-            bne MPU_xTimerGetPeriod_Unpriv
-            MPU_xTimerGetPeriod_Priv
-                pop {
-                r0
-            }
-            b MPU_xTimerGetPeriodImpl
-            MPU_xTimerGetPeriod_Unpriv
-                pop {
-                r0
-            }
-            svc # portSVC_SYSTEM_CALL_ENTER
-            bl MPU_xTimerGetPeriodImpl
-            svc # portSVC_SYSTEM_CALL_EXIT
-            bx lr
-        }
-
-    #endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-    #if ( configUSE_TIMERS == 1 )
-
-        TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
-
-        __asm TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
-        {
-            PRESERVE8
-            extern MPU_xTimerGetExpiryTimeImpl
-
-                push {
-                r0
-            }
-            mrs r0, control
-            tst r0, # 1
-            bne MPU_xTimerGetExpiryTime_Unpriv
-            MPU_xTimerGetExpiryTime_Priv
-                pop {
-                r0
-            }
-            b MPU_xTimerGetExpiryTimeImpl
-            MPU_xTimerGetExpiryTime_Unpriv
-                pop {
-                r0
-            }
-            svc # portSVC_SYSTEM_CALL_ENTER
-            bl MPU_xTimerGetExpiryTimeImpl
-            svc # portSVC_SYSTEM_CALL_EXIT
-            bx lr
-        }
-
-    #endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
-                                         const EventBits_t uxBitsToWaitFor,
-                                         const BaseType_t xClearOnExit,
-                                         const BaseType_t xWaitForAllBits,
+BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
                                          TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
 
-    __asm EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
-                                               const EventBits_t uxBitsToWaitFor,
-                                               const BaseType_t xClearOnExit,
-                                               const BaseType_t xWaitForAllBits,
+__asm BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
                                                TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-    {
-        PRESERVE8
-        extern MPU_xEventGroupWaitBitsImpl
+{
+    PRESERVE8
+    extern MPU_xQueueTakeMutexRecursiveImpl
 
-            push {
-            r0
-        }
-        mrs r0, control
-        tst r0, # 1
-        bne MPU_xEventGroupWaitBits_Unpriv
-        MPU_xEventGroupWaitBits_Priv
-            pop {
-            r0
-        }
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_xQueueTakeMutexRecursive_Unpriv
+MPU_xQueueTakeMutexRecursive_Priv
+        pop {r0}
+        b MPU_xQueueTakeMutexRecursiveImpl
+MPU_xQueueTakeMutexRecursive_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_xQueueTakeMutexRecursive
+}
+
+#endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+
+BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) FREERTOS_SYSTEM_CALL;
+
+__asm BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_xQueueGiveMutexRecursiveImpl
+
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_xQueueGiveMutexRecursive_Unpriv
+MPU_xQueueGiveMutexRecursive_Priv
+        pop {r0}
+        b MPU_xQueueGiveMutexRecursiveImpl
+MPU_xQueueGiveMutexRecursive_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_xQueueGiveMutexRecursive
+}
+
+#endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
+                                                const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+
+__asm QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
+                                                      const TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_xQueueSelectFromSetImpl
+
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_xQueueSelectFromSet_Unpriv
+MPU_xQueueSelectFromSet_Priv
+        pop {r0}
+        b MPU_xQueueSelectFromSetImpl
+MPU_xQueueSelectFromSet_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_xQueueSelectFromSet
+}
+
+#endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                               QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL;
+
+__asm BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                                     QueueSetHandle_t xQueueSet ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_xQueueAddToSetImpl
+
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_xQueueAddToSet_Unpriv
+MPU_xQueueAddToSet_Priv
+        pop {r0}
+        b MPU_xQueueAddToSetImpl
+MPU_xQueueAddToSet_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_xQueueAddToSet
+}
+
+#endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+/*-----------------------------------------------------------*/
+
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
+                              const char * pcName ) FREERTOS_SYSTEM_CALL;
+
+__asm void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
+                                    const char * pcName ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_vQueueAddToRegistryImpl
+
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_vQueueAddToRegistry_Unpriv
+MPU_vQueueAddToRegistry_Priv
+        pop {r0}
+        b MPU_vQueueAddToRegistryImpl
+MPU_vQueueAddToRegistry_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_vQueueAddToRegistry
+}
+
+#endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+
+__asm void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_vQueueUnregisterQueueImpl
+
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_vQueueUnregisterQueue_Unpriv
+MPU_vQueueUnregisterQueue_Priv
+        pop {r0}
+        b MPU_vQueueUnregisterQueueImpl
+MPU_vQueueUnregisterQueue_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_vQueueUnregisterQueue
+}
+
+#endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+
+__asm const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_pcQueueGetNameImpl
+
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_pcQueueGetName_Unpriv
+MPU_pcQueueGetName_Priv
+        pop {r0}
+        b MPU_pcQueueGetNameImpl
+MPU_pcQueueGetName_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_pcQueueGetName
+}
+
+#endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TIMERS == 1 )
+
+void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+
+__asm void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_pvTimerGetTimerIDImpl
+
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_pvTimerGetTimerID_Unpriv
+MPU_pvTimerGetTimerID_Priv
+        pop {r0}
+        b MPU_pvTimerGetTimerIDImpl
+MPU_pvTimerGetTimerID_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_pvTimerGetTimerID
+}
+
+#endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TIMERS == 1 )
+
+void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
+                           void * pvNewID ) FREERTOS_SYSTEM_CALL;
+
+__asm void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
+                                 void * pvNewID ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_vTimerSetTimerIDImpl
+
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_vTimerSetTimerID_Unpriv
+MPU_vTimerSetTimerID_Priv
+        pop {r0}
+        b MPU_vTimerSetTimerIDImpl
+MPU_vTimerSetTimerID_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_vTimerSetTimerID
+}
+
+#endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TIMERS == 1 )
+
+BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+
+__asm BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_xTimerIsTimerActiveImpl
+
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_xTimerIsTimerActive_Unpriv
+MPU_xTimerIsTimerActive_Priv
+        pop {r0}
+        b MPU_xTimerIsTimerActiveImpl
+MPU_xTimerIsTimerActive_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_xTimerIsTimerActive
+}
+
+#endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TIMERS == 1 )
+
+TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) FREERTOS_SYSTEM_CALL;
+
+__asm TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_xTimerGetTimerDaemonTaskHandleImpl
+
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv
+MPU_xTimerGetTimerDaemonTaskHandle_Priv
+        pop {r0}
+        b MPU_xTimerGetTimerDaemonTaskHandleImpl
+MPU_xTimerGetTimerDaemonTaskHandle_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle
+}
+
+#endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TIMERS == 1 )
+
+BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) FREERTOS_SYSTEM_CALL;
+
+__asm BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_xTimerGenericCommandFromTaskImpl
+
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_xTimerGenericCommandFromTask_Unpriv
+MPU_xTimerGenericCommandFromTask_Priv
+        pop {r0}
+        b MPU_xTimerGenericCommandFromTaskImpl
+MPU_xTimerGenericCommandFromTask_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_xTimerGenericCommandFromTask
+}
+
+#endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TIMERS == 1 )
+
+const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+
+__asm const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_pcTimerGetNameImpl
+
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_pcTimerGetName_Unpriv
+MPU_pcTimerGetName_Priv
+        pop {r0}
+        b MPU_pcTimerGetNameImpl
+MPU_pcTimerGetName_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_pcTimerGetName
+}
+
+#endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TIMERS == 1 )
+
+void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
+                              const BaseType_t uxAutoReload ) FREERTOS_SYSTEM_CALL;
+
+__asm void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
+                                    const BaseType_t uxAutoReload ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_vTimerSetReloadModeImpl
+
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_vTimerSetReloadMode_Unpriv
+MPU_vTimerSetReloadMode_Priv
+        pop {r0}
+        b MPU_vTimerSetReloadModeImpl
+MPU_vTimerSetReloadMode_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_vTimerSetReloadMode
+}
+
+#endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TIMERS == 1 )
+
+BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+
+__asm BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_xTimerGetReloadModeImpl
+
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_xTimerGetReloadMode_Unpriv
+MPU_xTimerGetReloadMode_Priv
+        pop {r0}
+        b MPU_xTimerGetReloadModeImpl
+MPU_xTimerGetReloadMode_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_xTimerGetReloadMode
+}
+
+#endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TIMERS == 1 )
+
+UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+
+__asm UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_uxTimerGetReloadModeImpl
+
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_uxTimerGetReloadMode_Unpriv
+MPU_uxTimerGetReloadMode_Priv
+        pop {r0}
+        b MPU_uxTimerGetReloadModeImpl
+MPU_uxTimerGetReloadMode_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_uxTimerGetReloadMode
+}
+
+#endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TIMERS == 1 )
+
+TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+
+__asm TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_xTimerGetPeriodImpl
+
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_xTimerGetPeriod_Unpriv
+MPU_xTimerGetPeriod_Priv
+        pop {r0}
+        b MPU_xTimerGetPeriodImpl
+MPU_xTimerGetPeriod_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_xTimerGetPeriod
+}
+
+#endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TIMERS == 1 )
+
+TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+
+__asm TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_xTimerGetExpiryTimeImpl
+
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_xTimerGetExpiryTime_Unpriv
+MPU_xTimerGetExpiryTime_Priv
+        pop {r0}
+        b MPU_xTimerGetExpiryTimeImpl
+MPU_xTimerGetExpiryTime_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_xTimerGetExpiryTime
+}
+
+#endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) FREERTOS_SYSTEM_CALL;
+
+__asm EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_xEventGroupWaitBitsImpl
+
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_xEventGroupWaitBits_Unpriv
+MPU_xEventGroupWaitBits_Priv
+        pop {r0}
         b MPU_xEventGroupWaitBitsImpl
-        MPU_xEventGroupWaitBits_Unpriv
-            pop {
-            r0
-        }
-        svc # portSVC_SYSTEM_CALL_ENTER_1
-        bl MPU_xEventGroupWaitBitsImpl
-        svc # portSVC_SYSTEM_CALL_EXIT
-        bx lr
-    }
+MPU_xEventGroupWaitBits_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_xEventGroupWaitBits
+}
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                          const EventBits_t uxBitsToClear ) FREERTOS_SYSTEM_CALL;
+EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                      const EventBits_t uxBitsToClear ) FREERTOS_SYSTEM_CALL;
 
-    __asm EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                                const EventBits_t uxBitsToClear ) /* FREERTOS_SYSTEM_CALL */
-    {
-        PRESERVE8
-        extern MPU_xEventGroupClearBitsImpl
+__asm EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                            const EventBits_t uxBitsToClear ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_xEventGroupClearBitsImpl
 
-            push {
-            r0
-        }
-        mrs r0, control
-        tst r0, # 1
-        bne MPU_xEventGroupClearBits_Unpriv
-        MPU_xEventGroupClearBits_Priv
-            pop {
-            r0
-        }
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_xEventGroupClearBits_Unpriv
+MPU_xEventGroupClearBits_Priv
+        pop {r0}
         b MPU_xEventGroupClearBitsImpl
-        MPU_xEventGroupClearBits_Unpriv
-            pop {
-            r0
-        }
-        svc # portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xEventGroupClearBitsImpl
-        svc # portSVC_SYSTEM_CALL_EXIT
-        bx lr
-    }
+MPU_xEventGroupClearBits_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_xEventGroupClearBits
+}
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                        const EventBits_t uxBitsToSet ) FREERTOS_SYSTEM_CALL;
+EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                    const EventBits_t uxBitsToSet ) FREERTOS_SYSTEM_CALL;
 
-    __asm EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                              const EventBits_t uxBitsToSet ) /* FREERTOS_SYSTEM_CALL */
-    {
-        PRESERVE8
-        extern MPU_xEventGroupSetBitsImpl
+__asm EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                          const EventBits_t uxBitsToSet ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_xEventGroupSetBitsImpl
 
-            push {
-            r0
-        }
-        mrs r0, control
-        tst r0, # 1
-        bne MPU_xEventGroupSetBits_Unpriv
-        MPU_xEventGroupSetBits_Priv
-            pop {
-            r0
-        }
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_xEventGroupSetBits_Unpriv
+MPU_xEventGroupSetBits_Priv
+        pop {r0}
         b MPU_xEventGroupSetBitsImpl
-        MPU_xEventGroupSetBits_Unpriv
-            pop {
-            r0
-        }
-        svc # portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xEventGroupSetBitsImpl
-        svc # portSVC_SYSTEM_CALL_EXIT
-        bx lr
-    }
+MPU_xEventGroupSetBits_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_xEventGroupSetBits
+}
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                     const EventBits_t uxBitsToSet,
-                                     const EventBits_t uxBitsToWaitFor,
-                                     TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                 const EventBits_t uxBitsToSet,
+                                 const EventBits_t uxBitsToWaitFor,
+                                 TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
 
-    __asm EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                           const EventBits_t uxBitsToSet,
-                                           const EventBits_t uxBitsToWaitFor,
-                                           TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-    {
-        PRESERVE8
-        extern MPU_xEventGroupSyncImpl
+__asm EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                       const EventBits_t uxBitsToSet,
+                                       const EventBits_t uxBitsToWaitFor,
+                                       TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_xEventGroupSyncImpl
 
-            push {
-            r0
-        }
-        mrs r0, control
-        tst r0, # 1
-        bne MPU_xEventGroupSync_Unpriv
-        MPU_xEventGroupSync_Priv
-            pop {
-            r0
-        }
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_xEventGroupSync_Unpriv
+MPU_xEventGroupSync_Priv
+        pop {r0}
         b MPU_xEventGroupSyncImpl
-        MPU_xEventGroupSync_Unpriv
-            pop {
-            r0
-        }
-        svc # portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xEventGroupSyncImpl
-        svc # portSVC_SYSTEM_CALL_EXIT
-        bx lr
-    }
+MPU_xEventGroupSync_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_xEventGroupSync
+}
 /*-----------------------------------------------------------*/
 
-    #if ( configUSE_TRACE_FACILITY == 1 )
+#if ( configUSE_TRACE_FACILITY == 1 )
 
-        UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) FREERTOS_SYSTEM_CALL;
 
-        __asm UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* FREERTOS_SYSTEM_CALL */
-        {
-            PRESERVE8
-            extern MPU_uxEventGroupGetNumberImpl
+__asm UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_uxEventGroupGetNumberImpl
 
-                push {
-                r0
-            }
-            mrs r0, control
-            tst r0, # 1
-            bne MPU_uxEventGroupGetNumber_Unpriv
-            MPU_uxEventGroupGetNumber_Priv
-                pop {
-                r0
-            }
-            b MPU_uxEventGroupGetNumberImpl
-            MPU_uxEventGroupGetNumber_Unpriv
-                pop {
-                r0
-            }
-            svc # portSVC_SYSTEM_CALL_ENTER
-            bl MPU_uxEventGroupGetNumberImpl
-            svc # portSVC_SYSTEM_CALL_EXIT
-            bx lr
-        }
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_uxEventGroupGetNumber_Unpriv
+MPU_uxEventGroupGetNumber_Priv
+        pop {r0}
+        b MPU_uxEventGroupGetNumberImpl
+MPU_uxEventGroupGetNumber_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_uxEventGroupGetNumber
+}
 
-    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+#endif /*( configUSE_TRACE_FACILITY == 1 )*/
 /*-----------------------------------------------------------*/
 
-    #if ( configUSE_TRACE_FACILITY == 1 )
+#if ( configUSE_TRACE_FACILITY == 1 )
 
-        void MPU_vEventGroupSetNumber( void * xEventGroup,
-                                       UBaseType_t uxEventGroupNumber ) FREERTOS_SYSTEM_CALL;
+void MPU_vEventGroupSetNumber( void * xEventGroup,
+                               UBaseType_t uxEventGroupNumber ) FREERTOS_SYSTEM_CALL;
 
-        __asm void MPU_vEventGroupSetNumber( void * xEventGroup,
-                                             UBaseType_t uxEventGroupNumber ) /* FREERTOS_SYSTEM_CALL */
-        {
-            PRESERVE8
-            extern MPU_vEventGroupSetNumberImpl
+__asm void MPU_vEventGroupSetNumber( void * xEventGroup,
+                                     UBaseType_t uxEventGroupNumber ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_vEventGroupSetNumberImpl
 
-                push {
-                r0
-            }
-            mrs r0, control
-            tst r0, # 1
-            bne MPU_vEventGroupSetNumber_Unpriv
-            MPU_vEventGroupSetNumber_Priv
-                pop {
-                r0
-            }
-            b MPU_vEventGroupSetNumberImpl
-            MPU_vEventGroupSetNumber_Unpriv
-                pop {
-                r0
-            }
-            svc # portSVC_SYSTEM_CALL_ENTER
-            bl MPU_vEventGroupSetNumberImpl
-            svc # portSVC_SYSTEM_CALL_EXIT
-            bx lr
-        }
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_vEventGroupSetNumber_Unpriv
+MPU_vEventGroupSetNumber_Priv
+        pop {r0}
+        b MPU_vEventGroupSetNumberImpl
+MPU_vEventGroupSetNumber_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_vEventGroupSetNumber
+}
 
-    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+#endif /*( configUSE_TRACE_FACILITY == 1 )*/
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                                  const void * pvTxData,
-                                  size_t xDataLengthBytes,
-                                  TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                              const void * pvTxData,
+                              size_t xDataLengthBytes,
+                              TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
 
-    __asm size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                                        const void * pvTxData,
-                                        size_t xDataLengthBytes,
-                                        TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-    {
-        PRESERVE8
-        extern MPU_xStreamBufferSendImpl
+__asm size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                    const void * pvTxData,
+                                    size_t xDataLengthBytes,
+                                    TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_xStreamBufferSendImpl
 
-            push {
-            r0
-        }
-        mrs r0, control
-        tst r0, # 1
-        bne MPU_xStreamBufferSend_Unpriv
-        MPU_xStreamBufferSend_Priv
-            pop {
-            r0
-        }
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_xStreamBufferSend_Unpriv
+MPU_xStreamBufferSend_Priv
+        pop {r0}
         b MPU_xStreamBufferSendImpl
-        MPU_xStreamBufferSend_Unpriv
-            pop {
-            r0
-        }
-        svc # portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferSendImpl
-        svc # portSVC_SYSTEM_CALL_EXIT
-        bx lr
-    }
+MPU_xStreamBufferSend_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_xStreamBufferSend
+}
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                     void * pvRxData,
-                                     size_t xBufferLengthBytes,
-                                     TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                 void * pvRxData,
+                                 size_t xBufferLengthBytes,
+                                 TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
 
-    __asm size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                           void * pvRxData,
-                                           size_t xBufferLengthBytes,
-                                           TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-    {
-        PRESERVE8
-        extern MPU_xStreamBufferReceiveImpl
+__asm size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                       void * pvRxData,
+                                       size_t xBufferLengthBytes,
+                                       TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_xStreamBufferReceiveImpl
 
-            push {
-            r0
-        }
-        mrs r0, control
-        tst r0, # 1
-        bne MPU_xStreamBufferReceive_Unpriv
-        MPU_xStreamBufferReceive_Priv
-            pop {
-            r0
-        }
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_xStreamBufferReceive_Unpriv
+MPU_xStreamBufferReceive_Priv
+        pop {r0}
         b MPU_xStreamBufferReceiveImpl
-        MPU_xStreamBufferReceive_Unpriv
-            pop {
-            r0
-        }
-        svc # portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferReceiveImpl
-        svc # portSVC_SYSTEM_CALL_EXIT
-        bx lr
-    }
+MPU_xStreamBufferReceive_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_xStreamBufferReceive
+}
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
 
-    __asm BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
-    {
-        PRESERVE8
-        extern MPU_xStreamBufferIsFullImpl
+__asm BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_xStreamBufferIsFullImpl
 
-            push {
-            r0
-        }
-        mrs r0, control
-        tst r0, # 1
-        bne MPU_xStreamBufferIsFull_Unpriv
-        MPU_xStreamBufferIsFull_Priv
-            pop {
-            r0
-        }
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_xStreamBufferIsFull_Unpriv
+MPU_xStreamBufferIsFull_Priv
+        pop {r0}
         b MPU_xStreamBufferIsFullImpl
-        MPU_xStreamBufferIsFull_Unpriv
-            pop {
-            r0
-        }
-        svc # portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferIsFullImpl
-        svc # portSVC_SYSTEM_CALL_EXIT
-        bx lr
-    }
+MPU_xStreamBufferIsFull_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_xStreamBufferIsFull
+}
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
 
-    __asm BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
-    {
-        PRESERVE8
-        extern MPU_xStreamBufferIsEmptyImpl
+__asm BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_xStreamBufferIsEmptyImpl
 
-            push {
-            r0
-        }
-        mrs r0, control
-        tst r0, # 1
-        bne MPU_xStreamBufferIsEmpty_Unpriv
-        MPU_xStreamBufferIsEmpty_Priv
-            pop {
-            r0
-        }
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_xStreamBufferIsEmpty_Unpriv
+MPU_xStreamBufferIsEmpty_Priv
+        pop {r0}
         b MPU_xStreamBufferIsEmptyImpl
-        MPU_xStreamBufferIsEmpty_Unpriv
-            pop {
-            r0
-        }
-        svc # portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferIsEmptyImpl
-        svc # portSVC_SYSTEM_CALL_EXIT
-        bx lr
-    }
+MPU_xStreamBufferIsEmpty_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_xStreamBufferIsEmpty
+}
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
 
-    __asm size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
-    {
-        PRESERVE8
-        extern MPU_xStreamBufferSpacesAvailableImpl
+__asm size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_xStreamBufferSpacesAvailableImpl
 
-            push {
-            r0
-        }
-        mrs r0, control
-        tst r0, # 1
-        bne MPU_xStreamBufferSpacesAvailable_Unpriv
-        MPU_xStreamBufferSpacesAvailable_Priv
-            pop {
-            r0
-        }
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_xStreamBufferSpacesAvailable_Unpriv
+MPU_xStreamBufferSpacesAvailable_Priv
+        pop {r0}
         b MPU_xStreamBufferSpacesAvailableImpl
-        MPU_xStreamBufferSpacesAvailable_Unpriv
-            pop {
-            r0
-        }
-        svc # portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferSpacesAvailableImpl
-        svc # portSVC_SYSTEM_CALL_EXIT
-        bx lr
-    }
+MPU_xStreamBufferSpacesAvailable_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_xStreamBufferSpacesAvailable
+}
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
 
-    __asm size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
-    {
-        PRESERVE8
-        extern MPU_xStreamBufferBytesAvailableImpl
+__asm size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_xStreamBufferBytesAvailableImpl
 
-            push {
-            r0
-        }
-        mrs r0, control
-        tst r0, # 1
-        bne MPU_xStreamBufferBytesAvailable_Unpriv
-        MPU_xStreamBufferBytesAvailable_Priv
-            pop {
-            r0
-        }
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_xStreamBufferBytesAvailable_Unpriv
+MPU_xStreamBufferBytesAvailable_Priv
+        pop {r0}
         b MPU_xStreamBufferBytesAvailableImpl
-        MPU_xStreamBufferBytesAvailable_Unpriv
-            pop {
-            r0
-        }
-        svc # portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferBytesAvailableImpl
-        svc # portSVC_SYSTEM_CALL_EXIT
-        bx lr
-    }
+MPU_xStreamBufferBytesAvailable_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_xStreamBufferBytesAvailable
+}
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                                 size_t xTriggerLevel ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                             size_t xTriggerLevel ) FREERTOS_SYSTEM_CALL;
 
-    __asm BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                                       size_t xTriggerLevel ) /* FREERTOS_SYSTEM_CALL */
-    {
-        PRESERVE8
-        extern MPU_xStreamBufferSetTriggerLevelImpl
+__asm BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                   size_t xTriggerLevel ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_xStreamBufferSetTriggerLevelImpl
 
-            push {
-            r0
-        }
-        mrs r0, control
-        tst r0, # 1
-        bne MPU_xStreamBufferSetTriggerLevel_Unpriv
-        MPU_xStreamBufferSetTriggerLevel_Priv
-            pop {
-            r0
-        }
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_xStreamBufferSetTriggerLevel_Unpriv
+MPU_xStreamBufferSetTriggerLevel_Priv
+        pop {r0}
         b MPU_xStreamBufferSetTriggerLevelImpl
-        MPU_xStreamBufferSetTriggerLevel_Unpriv
-            pop {
-            r0
-        }
-        svc # portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferSetTriggerLevelImpl
-        svc # portSVC_SYSTEM_CALL_EXIT
-        bx lr
-    }
+MPU_xStreamBufferSetTriggerLevel_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel
+}
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
 
-    __asm size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
-    {
-        PRESERVE8
-        extern MPU_xStreamBufferNextMessageLengthBytesImpl
+__asm size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
+{
+    PRESERVE8
+    extern MPU_xStreamBufferNextMessageLengthBytesImpl
 
-            push {
-            r0
-        }
-        mrs r0, control
-        tst r0, # 1
-        bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv
-        MPU_xStreamBufferNextMessageLengthBytes_Priv
-            pop {
-            r0
-        }
+    push {r0}
+    mrs r0, control
+    tst r0, #1
+    bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv
+MPU_xStreamBufferNextMessageLengthBytes_Priv
+        pop {r0}
         b MPU_xStreamBufferNextMessageLengthBytesImpl
-        MPU_xStreamBufferNextMessageLengthBytes_Unpriv
-            pop {
-            r0
-        }
-        svc # portSVC_SYSTEM_CALL_ENTER
-        bl MPU_xStreamBufferNextMessageLengthBytesImpl
-        svc # portSVC_SYSTEM_CALL_EXIT
-        bx lr
-    }
+MPU_xStreamBufferNextMessageLengthBytes_Unpriv
+        pop {r0}
+        svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes
+}
 /*-----------------------------------------------------------*/
 
 #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
diff --git a/portable/RVDS/ARM_CM4_MPU/port.c b/portable/RVDS/ARM_CM4_MPU/port.c
index e7e26b969..566d4f737 100644
--- a/portable/RVDS/ARM_CM4_MPU/port.c
+++ b/portable/RVDS/ARM_CM4_MPU/port.c
@@ -38,6 +38,7 @@
 /* Scheduler includes. */
 #include "FreeRTOS.h"
 #include "task.h"
+#include "mpu_syscall_numbers.h"
 
 #ifndef __TARGET_FPU_VFP
     #error This port can only be used when the project options are configured to enable hardware floating point support.
@@ -139,7 +140,16 @@
 /* Each task maintains its own interrupt status in the critical nesting
  * variable.  Note this is not saved as part of the task context as context
  * switches can only occur when uxCriticalNesting is zero. */
-static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+PRIVILEGED_DATA static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+
+#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+/*
+ * This variable is set to pdTRUE when the scheduler is started.
+ */
+    PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
+
+#endif
 
 /*
  * Setup the timer to generate the tick interrupts.
@@ -242,24 +252,12 @@ void vPortSwitchToUserMode( void );
     void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
 #endif
 
-/**
- * @brief Triggers lazy stacking of FPU registers.
- */
-static void prvTriggerLazyStacking( void ) PRIVILEGED_FUNCTION;
-
 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
 
 /**
- * @brief Sets up the system call stack so that upon returning from
- * SVC, the system call stack is used.
- *
- * It is used for the system calls with up to 4 parameters.
- *
- * @param pulTaskStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ * @brief Triggers lazy stacking of FPU registers.
  */
-    void vSystemCallEnter( uint32_t * pulTaskStack,
-                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
+    static void prvTriggerLazyStacking( void ) PRIVILEGED_FUNCTION;
 
 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
@@ -269,13 +267,22 @@ static void prvTriggerLazyStacking( void ) PRIVILEGED_FUNCTION;
  * @brief Sets up the system call stack so that upon returning from
  * SVC, the system call stack is used.
  *
- * It is used for the system calls with 5 parameters.
- *
  * @param pulTaskStack The current SP when the SVC was raised.
  * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ * @param ucSystemCallNumber The system call number of the system call.
  */
-    void vSystemCallEnter_1( uint32_t * pulTaskStack,
-                             uint32_t ulLR ) PRIVILEGED_FUNCTION;
+    void vSystemCallEnter( uint32_t * pulTaskStack,
+                           uint32_t ulLR,
+                           uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION;
+
+#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+
+#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+
+/**
+ * @brief Raise SVC for exiting from a system call.
+ */
+    void vRequestSystemCallExit( void ) PRIVILEGED_FUNCTION;
 
 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
@@ -360,12 +367,16 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
 void vSVCHandler_C( uint32_t * pulParam )
 {
     uint8_t ucSVCNumber;
-    uint32_t ulPC, ulReg;
+    uint32_t ulPC;
 
-    #if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )
+    #if ( configUSE_MPU_WRAPPERS_V1 == 1 )
+        uint32_t ulReg;
+    #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+
+    #if ( ( configUSE_MPU_WRAPPERS_V1 == 1 ) && ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) )
         extern uint32_t __syscalls_flash_start__;
         extern uint32_t __syscalls_flash_end__;
-    #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
+    #endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 1 ) && ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) ) */
 
     /* The stack contains: r0, r1, r2, r3, r12, LR, PC and xPSR. The first
      * argument (r0) is pulParam[ 0 ]. */
@@ -391,27 +402,15 @@ void vSVCHandler_C( uint32_t * pulParam )
 
             break;
 
-            #if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )
-                case portSVC_RAISE_PRIVILEGE: /* Only raise the privilege, if the
-                                               * svc was raised from any of the
-                                               * system calls. */
+    #if ( configUSE_MPU_WRAPPERS_V1 == 1 )
+        #if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )
+            case portSVC_RAISE_PRIVILEGE: /* Only raise the privilege, if the
+                                           * svc was raised from any of the
+                                           * system calls. */
 
-                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
-                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
-                    {
-                        __asm
-                        {
-                            /* *INDENT-OFF* */
-                            mrs ulReg, control /* Obtain current control value. */
-                            bic ulReg, # 1     /* Set privilege bit. */
-                            msr control, ulReg /* Write back new control value. */
-                            /* *INDENT-ON* */
-                        }
-                    }
-
-                    break;
-            #else /* if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
-                case portSVC_RAISE_PRIVILEGE:
+                if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+                    ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+                {
                     __asm
                     {
                         /* *INDENT-OFF* */
@@ -420,33 +419,53 @@ void vSVCHandler_C( uint32_t * pulParam )
                         msr control, ulReg /* Write back new control value. */
                         /* *INDENT-ON* */
                     }
-                    break;
-                    #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
+                }
 
-                default: /* Unknown SVC call. */
-                    break;
+                break;
+        #else /* if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
+            case portSVC_RAISE_PRIVILEGE:
+                __asm
+                {
+                    /* *INDENT-OFF* */
+                    mrs ulReg, control /* Obtain current control value. */
+                    bic ulReg, # 1     /* Set privilege bit. */
+                    msr control, ulReg /* Write back new control value. */
+                    /* *INDENT-ON* */
+                }
+                break;
+        #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
+    #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+
+        default: /* Unknown SVC call. */
+            break;
     }
 }
 /*-----------------------------------------------------------*/
 
-__asm void prvTriggerLazyStacking( void ) /* PRIVILEGED_FUNCTION */
-{
-/* *INDENT-OFF* */
-    PRESERVE8
-
-    vpush {s0} /* Trigger lazy stacking. */
-    vpop  {s0} /* Nullify the affect of the above instruction. */
-
-/* *INDENT-ON* */
-}
-/*-----------------------------------------------------------*/
-
+#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+
+    __asm void prvTriggerLazyStacking( void ) /* PRIVILEGED_FUNCTION */
+    {
+    /* *INDENT-OFF* */
+        PRESERVE8
+
+        vpush {s0} /* Trigger lazy stacking. */
+        vpop  {s0} /* Nullify the affect of the above instruction. */
+
+    /* *INDENT-ON* */
+    }
+
+#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+/*-----------------------------------------------------------*/
+
 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
 
     void vSystemCallEnter( uint32_t * pulTaskStack,
-                           uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
+                           uint32_t ulLR,
+                           uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */
     {
         extern TaskHandle_t pxCurrentTCB;
+        extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ];
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulSystemCallStack;
         uint32_t ulStackFrameSize, ulSystemCallLocation, i, r1;
@@ -454,17 +473,27 @@ __asm void prvTriggerLazyStacking( void ) /* PRIVILEGED_FUNCTION */
         extern uint32_t __syscalls_flash_end__;
 
         ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
 
-        /* If the request did not come from the system call section, do nothing. */
+        /* Checks:
+         * 1. SVC is raised from the system call section (i.e. application is
+         *    not raising SVC directly).
+         * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as
+         *    it is non-NULL only during the execution of a system call (i.e.
+         *    between system call enter and exit).
+         * 3. System call is not for a kernel API disabled by the configuration
+         *    in FreeRTOSConfig.h.
+         * 4. We do not need to check that ucSystemCallNumber is within range
+         *    because the assembly SVC handler checks that before calling
+         *    this function.
+         */
         if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) &&
+            ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) &&
+            ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) )
         {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
             pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
 
-            /* This is not NULL only for the duration of the system call. */
-            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
-
             if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
             {
                 /* Extended frame i.e. FPU in use. */
@@ -504,10 +533,18 @@ __asm void prvTriggerLazyStacking( void ) /* PRIVILEGED_FUNCTION */
              * the system call. */
             pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
 
-            /* Store the value of the Link Register before the SVC was raised. We need to
-             * restore it when we exit from the system call. */
+            /* Store the value of the Link Register before the SVC was raised.
+             * It contains the address of the caller of the System Call entry
+             * point (i.e. the caller of the MPU_<API>). We need to restore it
+             * when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
 
+            /* Start executing the system call upon returning from this handler. */
+            pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
+            /* Raise a request to exit from the system call upon finishing the
+             * system call. */
+            pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit;
+
             /* Record if the hardware used padding to force the stack pointer
              * to be double word aligned. */
             if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
@@ -531,97 +568,11 @@ __asm void prvTriggerLazyStacking( void ) /* PRIVILEGED_FUNCTION */
 
 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
 
-    void vSystemCallEnter_1( uint32_t * pulTaskStack,
-                             uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
+    __asm void vRequestSystemCallExit( void ) /* PRIVILEGED_FUNCTION */
     {
-        extern TaskHandle_t pxCurrentTCB;
-        xMPU_SETTINGS * pxMpuSettings;
-        uint32_t * pulSystemCallStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i, r1;
-        extern uint32_t __syscalls_flash_start__;
-        extern uint32_t __syscalls_flash_end__;
+        PRESERVE8
 
-        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
-
-        /* If the request did not come from the system call section, do nothing. */
-        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
-        {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
-            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
-
-            /* This is not NULL only for the duration of the system call. */
-            configASSERT( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL );
-
-            if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
-            {
-                /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
-                prvTriggerLazyStacking();
-            }
-            else
-            {
-                /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
-            }
-
-            /* Make space on the system call stack for the stack frame and
-             * the parameter passed on the stack. We only need to copy one
-             * parameter but we still reserve 2 spaces to keep the stack
-             * double word aligned. */
-            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize - 2UL;
-
-            /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
-            {
-                pulSystemCallStack[ i ] = pulTaskStack[ i ];
-            }
-
-            /* Copy the parameter which is passed the stack. */
-            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
-            {
-                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize + 1 ];
-
-                /* Record if the hardware used padding to force the stack pointer
-                 * to be double word aligned. */
-                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
-            }
-            else
-            {
-                pulSystemCallStack[ ulStackFrameSize ] = pulTaskStack[ ulStackFrameSize ];
-
-                /* Record if the hardware used padding to force the stack pointer
-                 * to be double word aligned. */
-                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
-            }
-
-            /* Use the pulSystemCallStack in thread mode. */
-            __asm
-            {
-                msr psp, pulSystemCallStack
-            };
-
-            /* Raise the privilege for the duration of the system call. */
-            __asm
-            {
-                mrs r1, control /* Obtain current control value. */
-                bic r1, # 1     /* Clear nPRIV bit. */
-                msr control, r1 /* Write back new control value. */
-            };
-
-            /* Remember the location where we should copy the stack frame when we exit from
-             * the system call. */
-            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
-
-            /* Store the value of the Link Register before the SVC was raised. We need to
-             * restore it when we exit from the system call. */
-            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
-
-            /* We ensure in pxPortInitialiseStack that the system call stack is
-             * double word aligned and therefore, there is no need of padding.
-             * Clear the bit[9] of stacked xPSR. */
-            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
-        }
+        svc #portSVC_SYSTEM_CALL_EXIT
     }
 
 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@@ -636,16 +587,25 @@ __asm void prvTriggerLazyStacking( void ) /* PRIVILEGED_FUNCTION */
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulTaskStack;
         uint32_t ulStackFrameSize, ulSystemCallLocation, i, r1;
-        extern uint32_t __syscalls_flash_start__;
-        extern uint32_t __syscalls_flash_end__;
+        extern uint32_t __privileged_functions_start__;
+        extern uint32_t __privileged_functions_end__;
 
         ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
+        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
 
-        /* If the request did not come from the system call section, do nothing. */
-        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
-            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) )
+        /* Checks:
+         * 1. SVC is raised from the privileged code (i.e. application is not
+         *    raising SVC directly). This SVC is only raised from
+         *    vRequestSystemCallExit which is in the privileged code section.
+         * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL -
+         *    this means that we previously entered a system call and the
+         *    application is not attempting to exit without entering a system
+         *    call.
+         */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) &&
+            ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) )
         {
-            pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
             pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
 
             if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
@@ -683,8 +643,10 @@ __asm void prvTriggerLazyStacking( void ) /* PRIVILEGED_FUNCTION */
                 msr control, r1 /* Write back new control value. */
             };
 
-            /* Restore the stacked link register to what it was at the time of
-             * system call entry. */
+            /* Return to the caller of the System Call entry point (i.e. the
+             * caller of the MPU_<API>). */
+            pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+            /* Ensure that LR has a valid value.*/
             pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
 
             /* If the hardware used padding to force the stack pointer
@@ -727,7 +689,6 @@ BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */
     {
         extern vSVCHandler_C
         extern vSystemCallEnter
-        extern vSystemCallEnter_1
         extern vSystemCallExit
 
 /* *INDENT-OFF* */
@@ -740,10 +701,8 @@ BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */
 
     ldr r1, [r0, #24]
     ldrb r2, [r1, #-2]
-    cmp r2, #portSVC_SYSTEM_CALL_ENTER
-    beq syscall_enter
-    cmp r2, #portSVC_SYSTEM_CALL_ENTER_1
-    beq syscall_enter_1
+    cmp r2, #NUM_SYSTEM_CALLS
+    blt syscall_enter
     cmp r2, #portSVC_SYSTEM_CALL_EXIT
     beq syscall_exit
     b vSVCHandler_C
@@ -752,10 +711,6 @@ syscall_enter
         mov r1, lr
         b vSystemCallEnter
 
-syscall_enter_1
-        mov r1, lr
-        b vSystemCallEnter_1
-
 syscall_exit
         mov r1, lr
         b vSystemCallExit
@@ -967,6 +922,12 @@ BaseType_t xPortStartScheduler( void )
     /* Initialise the critical nesting count ready for the first task. */
     uxCriticalNesting = 0;
 
+    #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+    {
+        xSchedulerRunning = pdTRUE;
+    }
+    #endif
+
     /* Ensure the VFP is enabled - it should be anyway. */
     vPortEnableVFP();
 
@@ -1235,8 +1196,6 @@ __asm void vPortEnableVFP( void )
     orr r1, r1, #( 0xf << 20 ) /* Enable CP10 and CP11 coprocessors, then save back. */
     str r1, [ r0 ]
     bx r14
-    nop
-    nop
 /* *INDENT-ON* */
 }
 /*-----------------------------------------------------------*/
@@ -1657,21 +1616,34 @@ __asm uint32_t prvPortGetIPSR( void )
         {
             uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
             BaseType_t xAccessGranted = pdFALSE;
-            const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+            const xMPU_SETTINGS * xTaskMpuSettings;
 
-            ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
-            ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
-
-            if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+            if( xSchedulerRunning == pdFALSE )
             {
+                /* Grant access to all the kernel objects before the scheduler
+                 * is started. It is necessary because there is no task running
+                 * yet and therefore, we cannot use the permissions of any
+                 * task. */
                 xAccessGranted = pdTRUE;
             }
             else
             {
-                if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+                ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+                ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+                if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
                 {
                     xAccessGranted = pdTRUE;
                 }
+                else
+                {
+                    if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                    {
+                        xAccessGranted = pdTRUE;
+                    }
+                }
             }
 
             return xAccessGranted;
diff --git a/portable/RVDS/ARM_CM4_MPU/portmacro.h b/portable/RVDS/ARM_CM4_MPU/portmacro.h
index 1d17b4c10..455aa84cd 100644
--- a/portable/RVDS/ARM_CM4_MPU/portmacro.h
+++ b/portable/RVDS/ARM_CM4_MPU/portmacro.h
@@ -253,12 +253,10 @@ typedef struct MPU_SETTINGS
 /*-----------------------------------------------------------*/
 
 /* SVC numbers for various services. */
-#define portSVC_START_SCHEDULER        0
-#define portSVC_YIELD                  1
-#define portSVC_RAISE_PRIVILEGE        2
-#define portSVC_SYSTEM_CALL_ENTER      3 /* System calls with upto 4 parameters. */
-#define portSVC_SYSTEM_CALL_ENTER_1    4 /* System calls with 5 parameters. */
-#define portSVC_SYSTEM_CALL_EXIT       5
+#define portSVC_START_SCHEDULER        100
+#define portSVC_YIELD                  101
+#define portSVC_RAISE_PRIVILEGE        102
+#define portSVC_SYSTEM_CALL_EXIT       103
 
 /* Scheduler utilities. */
 

From a8a17dc4b5c9c1a5d7e84a33852746fff1e16282 Mon Sep 17 00:00:00 2001
From: Soren Ptak <ptaksoren@gmail.com>
Date: Thu, 23 Nov 2023 02:09:09 -0800
Subject: [PATCH 113/424] Revert formatting on CCS port files (#881)

Co-authored-by: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
---
 portable/CCS/ARM_CM3/port.c            |  32 +++----
 portable/CCS/ARM_CM3/portmacro.h       | 124 ++++++++++++-------------
 portable/CCS/ARM_CM4F/port.c           |  32 +++----
 portable/CCS/ARM_CM4F/portmacro.h      | 122 ++++++++++++------------
 portable/CCS/ARM_Cortex-R4/port.c      | 108 +++++++++++----------
 portable/CCS/ARM_Cortex-R4/portmacro.h |  80 ++++++++--------
 portable/CCS/MSP430X/data_model.h      |  96 +++++++++----------
 portable/CCS/MSP430X/port.c            |  68 +++++++-------
 portable/CCS/MSP430X/portmacro.h       | 110 +++++++++++-----------
 9 files changed, 383 insertions(+), 389 deletions(-)

diff --git a/portable/CCS/ARM_CM3/port.c b/portable/CCS/ARM_CM3/port.c
index e55b01dbd..e8b0f0d74 100644
--- a/portable/CCS/ARM_CM3/port.c
+++ b/portable/CCS/ARM_CM3/port.c
@@ -265,22 +265,22 @@ BaseType_t xPortStartScheduler( void )
         if( ulImplementedPrioBits == 8 )
         {
             /* When the hardware implements 8 priority bits, there is no way for
-             * the software to configure PRIGROUP to not have sub-priorities. As
-             * a result, the least significant bit is always used for sub-priority
-             * and there are 128 preemption priorities and 2 sub-priorities.
-             *
-             * This may cause some confusion in some cases - for example, if
-             * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
-             * priority interrupts will be masked in Critical Sections as those
-             * are at the same preemption priority. This may appear confusing as
-             * 4 is higher (numerically lower) priority than
-             * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
-             * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
-             * to 4, this confusion does not happen and the behaviour remains the same.
-             *
-             * The following assert ensures that the sub-priority bit in the
-             * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
-             * confusion. */
+            * the software to configure PRIGROUP to not have sub-priorities. As
+            * a result, the least significant bit is always used for sub-priority
+            * and there are 128 preemption priorities and 2 sub-priorities.
+            *
+            * This may cause some confusion in some cases - for example, if
+            * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
+            * priority interrupts will be masked in Critical Sections as those
+            * are at the same preemption priority. This may appear confusing as
+            * 4 is higher (numerically lower) priority than
+            * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
+            * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
+            * to 4, this confusion does not happen and the behaviour remains the same.
+            *
+            * The following assert ensures that the sub-priority bit in the
+            * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
+            * confusion. */
             configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
             ulMaxPRIGROUPValue = 0;
         }
diff --git a/portable/CCS/ARM_CM3/portmacro.h b/portable/CCS/ARM_CM3/portmacro.h
index 1d9c8ff75..29d9bc033 100644
--- a/portable/CCS/ARM_CM3/portmacro.h
+++ b/portable/CCS/ARM_CM3/portmacro.h
@@ -28,7 +28,7 @@
 
 
 #ifndef PORTMACRO_H
-#define PORTMACRO_H
+    #define PORTMACRO_H
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
@@ -47,52 +47,52 @@
  */
 
 /* Type definitions. */
-#define portCHAR          char
-#define portFLOAT         float
-#define portDOUBLE        double
-#define portLONG          long
-#define portSHORT         short
-#define portSTACK_TYPE    uint32_t
-#define portBASE_TYPE     long
+    #define portCHAR          char
+    #define portFLOAT         float
+    #define portDOUBLE        double
+    #define portLONG          long
+    #define portSHORT         short
+    #define portSTACK_TYPE    uint32_t
+    #define portBASE_TYPE     long
 
-typedef portSTACK_TYPE   StackType_t;
-typedef long             BaseType_t;
-typedef unsigned long    UBaseType_t;
+    typedef portSTACK_TYPE   StackType_t;
+    typedef long             BaseType_t;
+    typedef unsigned long    UBaseType_t;
 
-#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t     TickType_t;
-    #define portMAX_DELAY              ( TickType_t ) 0xffff
-#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t     TickType_t;
-    #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+    #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+        typedef uint16_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffff
+    #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+        typedef uint32_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
  * not need to be guarded with a critical section. */
-    #define portTICK_TYPE_IS_ATOMIC    1
-#else
-    #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
-#endif
+        #define portTICK_TYPE_IS_ATOMIC    1
+    #else
+        #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+    #endif
 /*-----------------------------------------------------------*/
 
 /* Architecture specifics. */
-#define portSTACK_GROWTH      ( -1 )
-#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT    8
+    #define portSTACK_GROWTH      ( -1 )
+    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+    #define portBYTE_ALIGNMENT    8
 
 /*-----------------------------------------------------------*/
 
 /* Compiler directives. */
-#define portWEAK_SYMBOL    __attribute__( ( weak ) )
+    #define portWEAK_SYMBOL    __attribute__( ( weak ) )
 
 /*-----------------------------------------------------------*/
 
 /* Scheduler utilities. */
-#define portYIELD()                                     \
+    #define portYIELD()                                 \
     {                                                   \
         /* Set a PendSV to request a context switch. */ \
         portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
-        __asm( "    dsb" );                             \
-        __asm( "    isb" );                             \
+        __asm( "    dsb");                                \
+        __asm( "    isb");                                \
     }
 
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
@@ -115,68 +115,68 @@ typedef unsigned long    UBaseType_t;
 /*-----------------------------------------------------------*/
 
 /* Architecture specific optimisations. */
-#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-    #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
-#endif
-
-#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-
-/* Check the configuration. */
-    #if ( configMAX_PRIORITIES > 32 )
-        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+    #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
     #endif
 
+    #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+/* Check the configuration. */
+        #if ( configMAX_PRIORITIES > 32 )
+            #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+        #endif
+
 /* Store/clear the ready priorities in a bit map. */
-    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+        #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+        #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 
 /*-----------------------------------------------------------*/
 
-    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31 - __clz( ( uxReadyPriorities ) ) )
+        #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31 - __clz( ( uxReadyPriorities ) ) )
 
-#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+    #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 /*-----------------------------------------------------------*/
 
 /* Critical section management. */
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
+    extern void vPortEnterCritical( void );
+    extern void vPortExitCritical( void );
 
-#define portDISABLE_INTERRUPTS()                                         \
+    #define portDISABLE_INTERRUPTS()                                     \
     {                                                                    \
         _set_interrupt_priority( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \
-        __asm( "    dsb" );                                              \
-        __asm( "    isb" );                                              \
+        __asm( "    dsb");                                               \
+        __asm( "    isb");                                               \
     }
 
-#define portENABLE_INTERRUPTS()                   _set_interrupt_priority( 0 )
-#define portENTER_CRITICAL()                      vPortEnterCritical()
-#define portEXIT_CRITICAL()                       vPortExitCritical()
-#define portSET_INTERRUPT_MASK_FROM_ISR()         _set_interrupt_priority( configMAX_SYSCALL_INTERRUPT_PRIORITY ); __asm( " dsb" ); __asm( "    isb" )
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    _set_interrupt_priority( x )
+    #define portENABLE_INTERRUPTS()                   _set_interrupt_priority( 0 )
+    #define portENTER_CRITICAL()                      vPortEnterCritical()
+    #define portEXIT_CRITICAL()                       vPortExitCritical()
+    #define portSET_INTERRUPT_MASK_FROM_ISR()         _set_interrupt_priority( configMAX_SYSCALL_INTERRUPT_PRIORITY ); __asm( " dsb" ); __asm( "    isb")
+    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    _set_interrupt_priority( x )
 /*-----------------------------------------------------------*/
 
 /* Tickless idle/low power functionality. */
-#ifndef portSUPPRESS_TICKS_AND_SLEEP
-    extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
-    #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
-#endif
+    #ifndef portSUPPRESS_TICKS_AND_SLEEP
+        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
+    #endif
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site.  These are
  * not necessary for to use this port.  They are defined so the common demo files
  * (which build with all the ports) will build. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 /*-----------------------------------------------------------*/
 
-#ifdef configASSERT
-    void vPortValidateInterruptPriority( void );
-    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
-#endif
+    #ifdef configASSERT
+        void vPortValidateInterruptPriority( void );
+        #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
+    #endif
 
 /* portNOP() is not required by this port. */
-#define portNOP()
+    #define portNOP()
 
 /*-----------------------------------------------------------*/
 
diff --git a/portable/CCS/ARM_CM4F/port.c b/portable/CCS/ARM_CM4F/port.c
index 6cba0913e..c3a9b0f4b 100644
--- a/portable/CCS/ARM_CM4F/port.c
+++ b/portable/CCS/ARM_CM4F/port.c
@@ -284,22 +284,22 @@ BaseType_t xPortStartScheduler( void )
         if( ulImplementedPrioBits == 8 )
         {
             /* When the hardware implements 8 priority bits, there is no way for
-             * the software to configure PRIGROUP to not have sub-priorities. As
-             * a result, the least significant bit is always used for sub-priority
-             * and there are 128 preemption priorities and 2 sub-priorities.
-             *
-             * This may cause some confusion in some cases - for example, if
-             * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
-             * priority interrupts will be masked in Critical Sections as those
-             * are at the same preemption priority. This may appear confusing as
-             * 4 is higher (numerically lower) priority than
-             * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
-             * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
-             * to 4, this confusion does not happen and the behaviour remains the same.
-             *
-             * The following assert ensures that the sub-priority bit in the
-             * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
-             * confusion. */
+            * the software to configure PRIGROUP to not have sub-priorities. As
+            * a result, the least significant bit is always used for sub-priority
+            * and there are 128 preemption priorities and 2 sub-priorities.
+            *
+            * This may cause some confusion in some cases - for example, if
+            * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
+            * priority interrupts will be masked in Critical Sections as those
+            * are at the same preemption priority. This may appear confusing as
+            * 4 is higher (numerically lower) priority than
+            * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
+            * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
+            * to 4, this confusion does not happen and the behaviour remains the same.
+            *
+            * The following assert ensures that the sub-priority bit in the
+            * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
+            * confusion. */
             configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
             ulMaxPRIGROUPValue = 0;
         }
diff --git a/portable/CCS/ARM_CM4F/portmacro.h b/portable/CCS/ARM_CM4F/portmacro.h
index 5d01094c5..f4405ab1b 100644
--- a/portable/CCS/ARM_CM4F/portmacro.h
+++ b/portable/CCS/ARM_CM4F/portmacro.h
@@ -28,7 +28,7 @@
 
 
 #ifndef PORTMACRO_H
-#define PORTMACRO_H
+    #define PORTMACRO_H
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
@@ -47,46 +47,46 @@
  */
 
 /* Type definitions. */
-#define portCHAR          char
-#define portFLOAT         float
-#define portDOUBLE        double
-#define portLONG          long
-#define portSHORT         short
-#define portSTACK_TYPE    uint32_t
-#define portBASE_TYPE     long
+    #define portCHAR          char
+    #define portFLOAT         float
+    #define portDOUBLE        double
+    #define portLONG          long
+    #define portSHORT         short
+    #define portSTACK_TYPE    uint32_t
+    #define portBASE_TYPE     long
 
-typedef portSTACK_TYPE   StackType_t;
-typedef long             BaseType_t;
-typedef unsigned long    UBaseType_t;
+    typedef portSTACK_TYPE   StackType_t;
+    typedef long             BaseType_t;
+    typedef unsigned long    UBaseType_t;
 
-#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t     TickType_t;
-    #define portMAX_DELAY              ( TickType_t ) 0xffff
-#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t     TickType_t;
-    #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+    #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+        typedef uint16_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffff
+    #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+        typedef uint32_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
  * not need to be guarded with a critical section. */
-    #define portTICK_TYPE_IS_ATOMIC    1
-#else
-    #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
-#endif
+        #define portTICK_TYPE_IS_ATOMIC    1
+    #else
+        #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+    #endif
 /*-----------------------------------------------------------*/
 
 /* Architecture specifics. */
-#define portSTACK_GROWTH      ( -1 )
-#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT    8
+    #define portSTACK_GROWTH      ( -1 )
+    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+    #define portBYTE_ALIGNMENT    8
 /*-----------------------------------------------------------*/
 
 /* Scheduler utilities. */
-#define portYIELD()                                     \
+    #define portYIELD()                                 \
     {                                                   \
         /* Set a PendSV to request a context switch. */ \
         portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
-        __asm( "    dsb" );                             \
-        __asm( "    isb" );                             \
+        __asm( "    dsb");                                \
+        __asm( "    isb");                                \
     }
 
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
@@ -109,68 +109,68 @@ typedef unsigned long    UBaseType_t;
 /*-----------------------------------------------------------*/
 
 /* Architecture specific optimisations. */
-#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-    #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
-#endif
-
-#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-
-/* Check the configuration. */
-    #if ( configMAX_PRIORITIES > 32 )
-        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+    #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
     #endif
 
+    #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+/* Check the configuration. */
+        #if ( configMAX_PRIORITIES > 32 )
+            #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+        #endif
+
 /* Store/clear the ready priorities in a bit map. */
-    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+        #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+        #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 
 /*-----------------------------------------------------------*/
 
-    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31 - __clz( ( uxReadyPriorities ) ) )
+        #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31 - __clz( ( uxReadyPriorities ) ) )
 
-#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+    #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 /*-----------------------------------------------------------*/
 
 /* Critical section management. */
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
+    extern void vPortEnterCritical( void );
+    extern void vPortExitCritical( void );
 
-#define portDISABLE_INTERRUPTS()                                         \
+    #define portDISABLE_INTERRUPTS()                                     \
     {                                                                    \
         _set_interrupt_priority( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \
-        __asm( "    dsb" );                                              \
-        __asm( "    isb" );                                              \
+        __asm( "    dsb");                                                 \
+        __asm( "    isb");                                                 \
     }
 
-#define portENABLE_INTERRUPTS()                   _set_interrupt_priority( 0 )
-#define portENTER_CRITICAL()                      vPortEnterCritical()
-#define portEXIT_CRITICAL()                       vPortExitCritical()
-#define portSET_INTERRUPT_MASK_FROM_ISR()         _set_interrupt_priority( configMAX_SYSCALL_INTERRUPT_PRIORITY ); __asm( " dsb" ); __asm( "    isb" )
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    _set_interrupt_priority( x )
+    #define portENABLE_INTERRUPTS()                   _set_interrupt_priority( 0 )
+    #define portENTER_CRITICAL()                      vPortEnterCritical()
+    #define portEXIT_CRITICAL()                       vPortExitCritical()
+    #define portSET_INTERRUPT_MASK_FROM_ISR()         _set_interrupt_priority( configMAX_SYSCALL_INTERRUPT_PRIORITY ); __asm( " dsb" ); __asm( "    isb")
+    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    _set_interrupt_priority( x )
 /*-----------------------------------------------------------*/
 
 /* Tickless idle/low power functionality. */
-#ifndef portSUPPRESS_TICKS_AND_SLEEP
-    extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
-    #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
-#endif
+    #ifndef portSUPPRESS_TICKS_AND_SLEEP
+        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
+    #endif
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site.  These are
  * not necessary for to use this port.  They are defined so the common demo files
  * (which build with all the ports) will build. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 /*-----------------------------------------------------------*/
 
-#ifdef configASSERT
-    void vPortValidateInterruptPriority( void );
-    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
-#endif
+    #ifdef configASSERT
+        void vPortValidateInterruptPriority( void );
+        #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
+    #endif
 
 /* portNOP() is not required by this port. */
-#define portNOP()
+    #define portNOP()
 
 /*-----------------------------------------------------------*/
 
diff --git a/portable/CCS/ARM_Cortex-R4/port.c b/portable/CCS/ARM_Cortex-R4/port.c
index 9eff9cf29..6c63a5a71 100644
--- a/portable/CCS/ARM_Cortex-R4/port.c
+++ b/portable/CCS/ARM_Cortex-R4/port.c
@@ -38,27 +38,27 @@ uint32_t ulCriticalNesting = 9999;
 /*-----------------------------------------------------------*/
 
 /* Registers required to configure the RTI. */
-#define portRTI_GCTRL_REG          ( *( ( volatile uint32_t * ) 0xFFFFFC00 ) )
-#define portRTI_TBCTRL_REG         ( *( ( volatile uint32_t * ) 0xFFFFFC04 ) )
-#define portRTI_COMPCTRL_REG       ( *( ( volatile uint32_t * ) 0xFFFFFC0C ) )
-#define portRTI_CNT0_FRC0_REG      ( *( ( volatile uint32_t * ) 0xFFFFFC10 ) )
-#define portRTI_CNT0_UC0_REG       ( *( ( volatile uint32_t * ) 0xFFFFFC14 ) )
-#define portRTI_CNT0_CPUC0_REG     ( *( ( volatile uint32_t * ) 0xFFFFFC18 ) )
-#define portRTI_CNT0_COMP0_REG     ( *( ( volatile uint32_t * ) 0xFFFFFC50 ) )
-#define portRTI_CNT0_UDCP0_REG     ( *( ( volatile uint32_t * ) 0xFFFFFC54 ) )
-#define portRTI_SETINTENA_REG      ( *( ( volatile uint32_t * ) 0xFFFFFC80 ) )
-#define portRTI_CLEARINTENA_REG    ( *( ( volatile uint32_t * ) 0xFFFFFC84 ) )
-#define portRTI_INTFLAG_REG        ( *( ( volatile uint32_t * ) 0xFFFFFC88 ) )
+#define portRTI_GCTRL_REG       ( * ( ( volatile uint32_t * ) 0xFFFFFC00 ) )
+#define portRTI_TBCTRL_REG      ( * ( ( volatile uint32_t * ) 0xFFFFFC04 ) )
+#define portRTI_COMPCTRL_REG    ( * ( ( volatile uint32_t * ) 0xFFFFFC0C ) )
+#define portRTI_CNT0_FRC0_REG   ( * ( ( volatile uint32_t * ) 0xFFFFFC10 ) )
+#define portRTI_CNT0_UC0_REG    ( * ( ( volatile uint32_t * ) 0xFFFFFC14 ) )
+#define portRTI_CNT0_CPUC0_REG  ( * ( ( volatile uint32_t * ) 0xFFFFFC18 ) )
+#define portRTI_CNT0_COMP0_REG  ( * ( ( volatile uint32_t * ) 0xFFFFFC50 ) )
+#define portRTI_CNT0_UDCP0_REG  ( * ( ( volatile uint32_t * ) 0xFFFFFC54 ) )
+#define portRTI_SETINTENA_REG   ( * ( ( volatile uint32_t * ) 0xFFFFFC80 ) )
+#define portRTI_CLEARINTENA_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC84 ) )
+#define portRTI_INTFLAG_REG     ( * ( ( volatile uint32_t * ) 0xFFFFFC88 ) )
 
 
 /* Constants required to set up the initial stack of each task. */
-#define portINITIAL_SPSR                        ( ( StackType_t ) 0x1F )
-#define portINITIAL_FPSCR                       ( ( StackType_t ) 0x00 )
-#define portINSTRUCTION_SIZE                    ( ( StackType_t ) 0x04 )
-#define portTHUMB_MODE_BIT                      ( ( StackType_t ) 0x20 )
+#define portINITIAL_SPSR        ( ( StackType_t ) 0x1F )
+#define portINITIAL_FPSCR       ( ( StackType_t ) 0x00 )
+#define portINSTRUCTION_SIZE    ( ( StackType_t ) 0x04 )
+#define portTHUMB_MODE_BIT      ( ( StackType_t ) 0x20 )
 
 /* The number of words on the stack frame between the saved Top Of Stack and
- * R0 (in which the parameters are passed. */
+R0 (in which the parameters are passed. */
 #define portSPACE_BETWEEN_TOS_AND_PARAMETERS    ( 12 )
 
 /*-----------------------------------------------------------*/
@@ -69,7 +69,7 @@ extern void vPortStartFirstTask( void );
 /*-----------------------------------------------------------*/
 
 /* Saved as part of the task context.  Set to pdFALSE if the task does not
- * require an FPU context. */
+require an FPU context. */
 uint32_t ulTaskHasFPUContext = 0;
 
 /*-----------------------------------------------------------*/
@@ -78,11 +78,9 @@ uint32_t ulTaskHasFPUContext = 0;
 /*
  * See header file for description.
  */
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
 {
-    StackType_t * pxOriginalTOS;
+StackType_t *pxOriginalTOS;
 
     pxOriginalTOS = pxTopOfStack;
 
@@ -94,15 +92,15 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
     #endif
 
     /* Setup the initial stack of the task.  The stack is set exactly as
-     * expected by the portRESTORE_CONTEXT() macro. */
+    expected by the portRESTORE_CONTEXT() macro. */
 
     /* First on the stack is the return address - which is the start of the as
-     * the task has not executed yet.  The offset is added to make the return
-     * address appear as it would within an IRQ ISR. */
+    the task has not executed yet.  The offset is added to make the return
+    address appear as it would within an IRQ ISR. */
     *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
     pxTopOfStack--;
 
-    *pxTopOfStack = ( StackType_t ) 0x00000000;    /* R14 */
+    *pxTopOfStack = ( StackType_t ) 0x00000000; /* R14 */
     pxTopOfStack--;
     *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
     pxTopOfStack--;
@@ -134,11 +132,11 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
         *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
         pxTopOfStack--;
     }
-    #else /* ifdef portPRELOAD_TASK_REGISTERS */
+    #else
     {
         pxTopOfStack -= portSPACE_BETWEEN_TOS_AND_PARAMETERS;
     }
-    #endif /* ifdef portPRELOAD_TASK_REGISTERS */
+    #endif
 
     /* Function parameters are passed in R0. */
     *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
@@ -158,8 +156,8 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
         pxTopOfStack--;
 
         /* The last thing on the stack is the tasks ulUsingFPU value, which by
-         * default is set to indicate that the stack frame does not include FPU
-         * registers. */
+        default is set to indicate that the stack frame does not include FPU
+        registers. */
         *pxTopOfStack = pdFALSE;
     }
     #endif
@@ -168,7 +166,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
 }
 /*-----------------------------------------------------------*/
 
-static void prvSetupTimerInterrupt( void )
+static void prvSetupTimerInterrupt(void)
 {
     /* Disable timer 0. */
     portRTI_GCTRL_REG &= 0xFFFFFFFEUL;
@@ -180,8 +178,8 @@ static void prvSetupTimerInterrupt( void )
     portRTI_COMPCTRL_REG = 0x00000000U;
 
     /* Initialise the counter and the prescale counter registers. */
-    portRTI_CNT0_UC0_REG = 0x00000000U;
-    portRTI_CNT0_FRC0_REG = 0x00000000U;
+    portRTI_CNT0_UC0_REG =  0x00000000U;
+    portRTI_CNT0_FRC0_REG =  0x00000000U;
 
     /* Set Prescalar for RTI clock. */
     portRTI_CNT0_CPUC0_REG = 0x00000001U;
@@ -189,7 +187,7 @@ static void prvSetupTimerInterrupt( void )
     portRTI_CNT0_UDCP0_REG = ( configCPU_CLOCK_HZ / 2 ) / configTICK_RATE_HZ;
 
     /* Clear interrupts. */
-    portRTI_INTFLAG_REG = 0x0007000FU;
+    portRTI_INTFLAG_REG =  0x0007000FU;
     portRTI_CLEARINTENA_REG = 0x00070F0FU;
 
     /* Enable the compare 0 interrupt. */
@@ -201,7 +199,7 @@ static void prvSetupTimerInterrupt( void )
 /*
  * See header file for description.
  */
-BaseType_t xPortStartScheduler( void )
+BaseType_t xPortStartScheduler(void)
 {
     /* Start the timer that generates the tick ISR. */
     prvSetupTimerInterrupt();
@@ -210,7 +208,7 @@ BaseType_t xPortStartScheduler( void )
     ulCriticalNesting = 0;
 
     /* Start the first task.  This is done from portASM.asm as ARM mode must be
-     * used. */
+    used. */
     vPortStartFirstTask();
 
     /* Should not get here! */
@@ -221,40 +219,40 @@ BaseType_t xPortStartScheduler( void )
 /*
  * See header file for description.
  */
-void vPortEndScheduler( void )
+void vPortEndScheduler(void)
 {
     /* Not implemented in ports where there is nothing to return to.
-     * Artificially force an assert. */
+    Artificially force an assert. */
     configASSERT( ulCriticalNesting == 1000UL );
 }
 /*-----------------------------------------------------------*/
 
 #if configUSE_PREEMPTION == 0
 
-/* The cooperative scheduler requires a normal IRQ service routine to
- * simply increment the system tick. */
+    /* The cooperative scheduler requires a normal IRQ service routine to
+     * simply increment the system tick. */
     __interrupt void vPortNonPreemptiveTick( void )
     {
         /* clear clock interrupt flag */
         portRTI_INTFLAG_REG = 0x00000001;
 
         /* Increment the tick count - this may make a delaying task ready
-         * to run - but a context switch is not performed. */
+        to run - but a context switch is not performed. */
         xTaskIncrementTick();
     }
 
-#else /* if configUSE_PREEMPTION == 0 */
+ #else
 
-/*
- **************************************************************************
- * The preemptive scheduler ISR is written in assembler and can be found
- * in the portASM.asm file. This will only get used if portUSE_PREEMPTION
- * is set to 1 in portmacro.h
- **************************************************************************
- */
+    /*
+     **************************************************************************
+     * The preemptive scheduler ISR is written in assembler and can be found
+     * in the portASM.asm file. This will only get used if portUSE_PREEMPTION
+     * is set to 1 in portmacro.h
+     **************************************************************************
+     */
     void vPortPreemptiveTick( void );
 
-#endif /* if configUSE_PREEMPTION == 0 */
+#endif
 /*-----------------------------------------------------------*/
 
 
@@ -266,9 +264,9 @@ void vPortEnterCritical( void )
     /* Disable interrupts as per portDISABLE_INTERRUPTS(); */
     portDISABLE_INTERRUPTS();
 
-    /* Now that interrupts are disabled, ulCriticalNesting can be accessed
-     * directly.  Increment ulCriticalNesting to keep a count of how many times
-     * portENTER_CRITICAL() has been called. */
+    /* Now interrupts are disabled ulCriticalNesting can be accessed
+    directly.  Increment ulCriticalNesting to keep a count of how many times
+    portENTER_CRITICAL() has been called. */
     ulCriticalNesting++;
 }
 /*-----------------------------------------------------------*/
@@ -285,7 +283,7 @@ void vPortExitCritical( void )
         ulCriticalNesting--;
 
         /* If the nesting level has reached zero then interrupts should be
-         * re-enabled. */
+        re-enabled. */
         if( ulCriticalNesting == 0 )
         {
             /* Enable interrupts as per portENABLE_INTERRUPTS(). */
@@ -299,10 +297,10 @@ void vPortExitCritical( void )
 
     void vPortTaskUsesFPU( void )
     {
-        extern void vPortInitialiseFPSCR( void );
+    extern void vPortInitialiseFPSCR( void );
 
         /* A task is registering the fact that it needs an FPU context.  Set the
-         * FPU flag (saved as part of the task context. */
+        FPU flag (saved as part of the task context. */
         ulTaskHasFPUContext = pdTRUE;
 
         /* Initialise the floating point status register. */
diff --git a/portable/CCS/ARM_Cortex-R4/portmacro.h b/portable/CCS/ARM_Cortex-R4/portmacro.h
index 06c758aec..07c1827cb 100644
--- a/portable/CCS/ARM_Cortex-R4/portmacro.h
+++ b/portable/CCS/ARM_Cortex-R4/portmacro.h
@@ -40,80 +40,80 @@
  */
 
 /* Type definitions. */
-#define portCHAR          char
-#define portFLOAT         float
-#define portDOUBLE        double
-#define portLONG          long
-#define portSHORT         short
-#define portSTACK_TYPE    uint32_t
-#define portBASE_TYPE     long
+#define portCHAR        char
+#define portFLOAT       float
+#define portDOUBLE      double
+#define portLONG        long
+#define portSHORT       short
+#define portSTACK_TYPE  uint32_t
+#define portBASE_TYPE   long
 
-typedef portSTACK_TYPE   StackType_t;
-typedef long             BaseType_t;
-typedef unsigned long    UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
 
-#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t     TickType_t;
-    #define portMAX_DELAY              ( TickType_t ) 0xFFFF
+#if (configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS)
+    typedef uint16_t TickType_t;
+    #define portMAX_DELAY (TickType_t) 0xFFFF
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t     TickType_t;
-    #define portMAX_DELAY              ( TickType_t ) 0xFFFFFFFFF
+    typedef uint32_t TickType_t;
+    #define portMAX_DELAY (TickType_t) 0xFFFFFFFFF
 
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
-    #define portTICK_TYPE_IS_ATOMIC    1
+    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+    not need to be guarded with a critical section. */
+    #define portTICK_TYPE_IS_ATOMIC 1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
 
 
 /* Architecture specifics. */
-#define portSTACK_GROWTH      ( -1 )
-#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT    8
+#define portSTACK_GROWTH    (-1)
+#define portTICK_PERIOD_MS    ((TickType_t) 1000 / configTICK_RATE_HZ)
+#define portBYTE_ALIGNMENT  8
 
 /* Critical section handling. */
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
+extern void vPortEnterCritical(void);
+extern void vPortExitCritical(void);
 #define portENTER_CRITICAL()        vPortEnterCritical()
 #define portEXIT_CRITICAL()         vPortExitCritical()
-#define portDISABLE_INTERRUPTS()    asm ( " CPSID I" )
-#define portENABLE_INTERRUPTS()     asm ( " CPSIE I" )
+#define portDISABLE_INTERRUPTS()    asm( " CPSID I" )
+#define portENABLE_INTERRUPTS()     asm( " CPSIE I" )
 
 /* Scheduler utilities. */
 #pragma SWI_ALIAS( vPortYield, 0 )
 extern void vPortYield( void );
-#define portYIELD()                vPortYield()
-#define portSYS_SSIR1_REG      ( *( ( volatile uint32_t * ) 0xFFFFFFB0 ) )
-#define portSYS_SSIR1_SSKEY    ( 0x7500UL )
-#define portYIELD_WITHIN_API()     { portSYS_SSIR1_REG = portSYS_SSIR1_SSKEY;  asm ( " DSB " ); asm ( " ISB " ); }
-#define portYIELD_FROM_ISR( x )    do { if( x != pdFALSE ) { portSYS_SSIR1_REG = portSYS_SSIR1_SSKEY;  ( void ) portSYS_SSIR1_REG; } } while( 0 )
+#define portYIELD()                 vPortYield()
+#define portSYS_SSIR1_REG           ( * ( ( volatile uint32_t * ) 0xFFFFFFB0 ) )
+#define portSYS_SSIR1_SSKEY         ( 0x7500UL )
+#define portYIELD_WITHIN_API()      { portSYS_SSIR1_REG = portSYS_SSIR1_SSKEY;  asm( " DSB " ); asm( " ISB " ); }
+#define portYIELD_FROM_ISR( x )     do { if( x != pdFALSE ) { portSYS_SSIR1_REG = portSYS_SSIR1_SSKEY;  ( void ) portSYS_SSIR1_REG; } } while( 0 )
 
 #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-    #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
+    #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
 #endif
 
 /* Architecture specific optimisations. */
 #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
 
-/* Check the configuration. */
-    #if ( configMAX_PRIORITIES > 32 )
+    /* Check the configuration. */
+    #if( configMAX_PRIORITIES > 32 )
         #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
     #endif
 
-/* Store/clear the ready priorities in a bit map. */
-    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+    /* Store/clear the ready priorities in a bit map. */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 
-/*-----------------------------------------------------------*/
+    /*-----------------------------------------------------------*/
 
-    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31 - __clz( ( uxReadyPriorities ) ) )
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __clz( ( uxReadyPriorities ) ) )
 
 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION(vFunction, pvParameters)       void vFunction(void *pvParameters)
+#define portTASK_FUNCTION_PROTO(vFunction, pvParameters) void vFunction(void *pvParameters)
 
 #endif /* __PORTMACRO_H__ */
diff --git a/portable/CCS/MSP430X/data_model.h b/portable/CCS/MSP430X/data_model.h
index 15a88ca78..186caa65d 100644
--- a/portable/CCS/MSP430X/data_model.h
+++ b/portable/CCS/MSP430X/data_model.h
@@ -1,53 +1,49 @@
-; /*
-   * ; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
-   * ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
-   * ; *
-   * ; * SPDX-License-Identifier: MIT
-   * ; *
-   * ; * Permission is hereby granted, free of charge, to any person obtaining a copy of
-   * ; * this software and associated documentation files (the "Software"), to deal in
-   * ; * the Software without restriction, including without limitation the rights to
-   * ; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
-   * ; * the Software, and to permit persons to whom the Software is furnished to do so,
-   * ; * subject to the following conditions:
-   * ; *
-   * ; * The above copyright notice and this permission notice shall be included in all
-   * ; * copies or substantial portions of the Software.
-   * ; *
-   * ; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-   * ; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-   * ; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-   * ; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-   * ; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-   * ; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-   * ; *
-   * ; * https://www.FreeRTOS.org
-   * ; * https://github.com/FreeRTOS
-   * ; *
-   * ; */
+;/*
+; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * SPDX-License-Identifier: MIT
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * https://www.FreeRTOS.org
+; * https://github.com/FreeRTOS
+; *
+; */
 
-.
+    .if $DEFINED( __LARGE_DATA_MODEL__ )
+        .define "pushm.a", pushm_x
+        .define "popm.a", popm_x
+        .define "push.a", push_x
+        .define "pop.a", pop_x
+        .define "mov.a", mov_x
+    .else
+        .define "pushm.w", pushm_x
+        .define "popm.w", popm_x
+        .define "push.w", push_x
+        .define "pop.w", pop_x
+        .define "mov.w", mov_x
+    .endif
 
-   if $DEFINED( __LARGE_DATA_MODEL__ )
-   .define "pushm.a", pushm_x
-   .define "popm.a", popm_x
-   .define "push.a", push_x
-   .define "pop.a", pop_x
-   .define "mov.a", mov_x
-   .else
-    .define "pushm.w", pushm_x
-       .define "popm.w", popm_x
-       .define "push.w", push_x
-       .define "pop.w", pop_x
-       .define "mov.w", mov_x
-       .endif
-
-       .
-
-       if $DEFINED( __LARGE_CODE_MODEL__ )
-       .define "calla", call_x
-       .define "reta", ret_x
-       .else
+    .if $DEFINED( __LARGE_CODE_MODEL__ )
+        .define "calla", call_x
+        .define "reta", ret_x
+    .else
         .define "call", call_x
-           .define "ret", ret_x
-           .endif
+        .define "ret", ret_x
+    .endif
diff --git a/portable/CCS/MSP430X/port.c b/portable/CCS/MSP430X/port.c
index d8ddfe432..c691b5d9f 100644
--- a/portable/CCS/MSP430X/port.c
+++ b/portable/CCS/MSP430X/port.c
@@ -31,28 +31,28 @@
 #include "task.h"
 
 /*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the MSP430X port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the MSP430X port.
+ *----------------------------------------------------------*/
 
 /* Constants required for hardware setup.  The tick ISR runs off the ACLK,
- * not the MCLK. */
+not the MCLK. */
 #define portACLK_FREQUENCY_HZ           ( ( TickType_t ) 32768 )
 #define portINITIAL_CRITICAL_NESTING    ( ( uint16_t ) 10 )
 #define portFLAGS_INT_ENABLED           ( ( StackType_t ) 0x08 )
 
 /* We require the address of the pxCurrentTCB variable, but don't want to know
- * any details of its type. */
+any details of its type. */
 typedef void TCB_t;
 extern volatile TCB_t * volatile pxCurrentTCB;
 
 /* Each task maintains a count of the critical section nesting depth.  Each
- * time a critical section is entered the count is incremented.  Each time a
- * critical section is exited the count is decremented - with interrupts only
- * being re-enabled if the count is zero.
- *
- * usCriticalNesting will get set to zero when the scheduler starts, but must
- * not be initialised to zero as this will cause problems during the startup
- * sequence. */
+time a critical section is entered the count is incremented.  Each time a
+critical section is exited the count is decremented - with interrupts only
+being re-enabled if the count is zero.
+
+usCriticalNesting will get set to zero when the scheduler starts, but must
+not be initialised to zero as this will cause problems during the startup
+sequence. */
 volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;
 /*-----------------------------------------------------------*/
 
@@ -70,27 +70,25 @@ void vPortSetupTimerInterrupt( void );
  *
  * See the header file portable.h.
  */
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
 {
-    uint16_t * pusTopOfStack;
-    uint32_t * pulTopOfStack, ulTemp;
+uint16_t *pusTopOfStack;
+uint32_t *pulTopOfStack, ulTemp;
 
     /*
-     *  Place a few bytes of known values on the bottom of the stack.
-     *  This is just useful for debugging and can be included if required.
-     *
-     * pxTopOfStack = ( StackType_t ) 0x1111;
-     *  pxTopOfStack--;
-     * pxTopOfStack = ( StackType_t ) 0x2222;
-     *  pxTopOfStack--;
-     * pxTopOfStack = ( StackType_t ) 0x3333;
-     *  pxTopOfStack--;
-     */
+        Place a few bytes of known values on the bottom of the stack.
+        This is just useful for debugging and can be included if required.
+
+        *pxTopOfStack = ( StackType_t ) 0x1111;
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) 0x2222;
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) 0x3333;
+        pxTopOfStack--;
+    */
 
     /* Data types are need either 16 bits or 32 bits depending on the data
-     * and code model used. */
+    and code model used. */
     if( sizeof( pxCode ) == sizeof( uint16_t ) )
     {
         pusTopOfStack = ( uint16_t * ) pxTopOfStack;
@@ -139,19 +137,19 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
         pxTopOfStack--;
         *pxTopOfStack = ( StackType_t ) 0x4444;
         pxTopOfStack--;
-    #else /* ifdef PRELOAD_REGISTER_VALUES */
+    #else
         pxTopOfStack -= 3;
         *pxTopOfStack = ( StackType_t ) pvParameters;
         pxTopOfStack -= 9;
-    #endif /* ifdef PRELOAD_REGISTER_VALUES */
+    #endif
 
     /* A variable is used to keep track of the critical section nesting.
-     * This variable has to be stored as part of the task context and is
-     * initially set to zero. */
+    This variable has to be stored as part of the task context and is
+    initially set to zero. */
     *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;
 
     /* Return a pointer to the top of the stack we have generated so this can
-     * be stored in the task control block for the task. */
+    be stored in the task control block for the task. */
     return pxTopOfStack;
 }
 /*-----------------------------------------------------------*/
@@ -159,7 +157,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
 void vPortEndScheduler( void )
 {
     /* It is unlikely that the MSP430 port will get stopped.  If required simply
-     * disable the tick interrupt here. */
+    disable the tick interrupt here. */
 }
 /*-----------------------------------------------------------*/
 
@@ -175,7 +173,7 @@ void vPortSetupTimerInterrupt( void )
 #pragma vector=configTICK_VECTOR
 interrupt void vTickISREntry( void )
 {
-    extern void vPortTickISR( void );
+extern void vPortTickISR( void );
 
     __bic_SR_register_on_exit( SCG1 + SCG0 + OSCOFF + CPUOFF );
     #if configUSE_PREEMPTION == 1
@@ -186,3 +184,5 @@ interrupt void vTickISREntry( void )
         vPortCooperativeTickISR();
     #endif
 }
+
+
diff --git a/portable/CCS/MSP430X/portmacro.h b/portable/CCS/MSP430X/portmacro.h
index 5b5a87184..064b0503a 100644
--- a/portable/CCS/MSP430X/portmacro.h
+++ b/portable/CCS/MSP430X/portmacro.h
@@ -43,31 +43,31 @@
 #include "msp430.h"
 
 /* Type definitions. */
-#define portCHAR         char
-#define portFLOAT        float
-#define portDOUBLE       double
-#define portLONG         long
-#define portSHORT        int
-#define portBASE_TYPE    portSHORT
+#define portCHAR        char
+#define portFLOAT       float
+#define portDOUBLE      double
+#define portLONG        long
+#define portSHORT       int
+#define portBASE_TYPE   portSHORT
 
 /* The stack type changes depending on the data model. */
 #ifdef __LARGE_DATA_MODEL__
-    #define portSTACK_TYPE           uint32_t
+    #define portSTACK_TYPE uint32_t
 #else
-    #define portSTACK_TYPE           uint16_t
-    #define portPOINTER_SIZE_TYPE    uint16_t
+    #define portSTACK_TYPE uint16_t
+    #define portPOINTER_SIZE_TYPE uint16_t
 #endif
 
-typedef portSTACK_TYPE   StackType_t;
-typedef short            BaseType_t;
-typedef unsigned short   UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef short BaseType_t;
+typedef unsigned short UBaseType_t;
 
-#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t     TickType_t;
-    #define portMAX_DELAY    ( TickType_t ) 0xffff
+#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t TickType_t;
+    #define portMAX_DELAY ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t     TickType_t;
-    #define portMAX_DELAY    ( TickType_t ) ( 0xFFFFFFFFUL )
+    typedef uint32_t TickType_t;
+    #define portMAX_DELAY ( TickType_t )    ( 0xFFFFFFFFUL )
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
@@ -80,37 +80,37 @@ typedef unsigned short   UBaseType_t;
 /*-----------------------------------------------------------*/
 
 /* Critical section control macros. */
-#define portNO_CRITICAL_SECTION_NESTING    ( ( uint16_t ) 0 )
+#define portNO_CRITICAL_SECTION_NESTING     ( ( uint16_t ) 0 )
 
-#define portENTER_CRITICAL()                                                     \
-    {                                                                            \
-        extern volatile uint16_t usCriticalNesting;                              \
-                                                                                 \
-        portDISABLE_INTERRUPTS();                                                \
-                                                                                 \
-        /* Now interrupts are disabled usCriticalNesting can be accessed */      \
-        /* directly.  Increment ulCriticalNesting to keep a count of how many */ \
-        /* times portENTER_CRITICAL() has been called. */                        \
-        usCriticalNesting++;                                                     \
-    }
+#define portENTER_CRITICAL()                                                    \
+{                                                                               \
+extern volatile uint16_t usCriticalNesting;                                     \
+                                                                                \
+    portDISABLE_INTERRUPTS();                                                   \
+                                                                                \
+    /* Now interrupts are disabled usCriticalNesting can be accessed */         \
+    /* directly.  Increment ulCriticalNesting to keep a count of how many */    \
+    /* times portENTER_CRITICAL() has been called. */                           \
+    usCriticalNesting++;                                                        \
+}
 
-#define portEXIT_CRITICAL()                                                         \
-    {                                                                               \
-        extern volatile uint16_t usCriticalNesting;                                 \
-                                                                                    \
-        if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING )                   \
-        {                                                                           \
-            /* Decrement the nesting count as we are leaving a critical section. */ \
-            usCriticalNesting--;                                                    \
-                                                                                    \
-            /* If the nesting level has reached zero then interrupts should be */   \
-            /* re-enabled. */                                                       \
-            if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING )              \
-            {                                                                       \
-                portENABLE_INTERRUPTS();                                            \
-            }                                                                       \
-        }                                                                           \
-    }
+#define portEXIT_CRITICAL()                                                     \
+{                                                                               \
+extern volatile uint16_t usCriticalNesting;                                     \
+                                                                                \
+    if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING )                   \
+    {                                                                           \
+        /* Decrement the nesting count as we are leaving a critical section. */ \
+        usCriticalNesting--;                                                    \
+                                                                                \
+        /* If the nesting level has reached zero then interrupts should be */   \
+        /* re-enabled. */                                                       \
+        if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING )              \
+        {                                                                       \
+            portENABLE_INTERRUPTS();                                            \
+        }                                                                       \
+    }                                                                           \
+}
 /*-----------------------------------------------------------*/
 
 /* Task utilities. */
@@ -119,27 +119,27 @@ typedef unsigned short   UBaseType_t;
  * Manual context switch called by portYIELD or taskYIELD.
  */
 extern void vPortYield( void );
-#define portYIELD()    vPortYield()
+#define portYIELD() vPortYield()
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portBYTE_ALIGNMENT    2
-#define portSTACK_GROWTH      ( -1 )
-#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portNOP()    __no_operation()
+#define portBYTE_ALIGNMENT          2
+#define portSTACK_GROWTH            ( -1 )
+#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()                   __no_operation()
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
 
 extern void vTaskSwitchContext( void );
-#define portYIELD_FROM_ISR( x )                               do { if( x ) vPortYield( ); } while( 0 )
+#define portYIELD_FROM_ISR( x ) do { if( x ) vPortYield(); } while( 0 )
 
 void vApplicationSetupTimerInterrupt( void );
 
 /* sizeof( int ) != sizeof( long ) so a full printf() library is required if
- * run time stats information is to be displayed. */
+run time stats information is to be displayed. */
 #define portLU_PRINTF_SPECIFIER_REQUIRED
 
 #endif /* PORTMACRO_H */

From 2dfc5142f413eda38f30aaa6a4027c7657b7bf86 Mon Sep 17 00:00:00 2001
From: Soren Ptak <ptaksoren@gmail.com>
Date: Thu, 23 Nov 2023 02:20:15 -0800
Subject: [PATCH 114/424] Revert the formatting changes on MikroC ports. (#882)

Co-authored-by: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
---
 portable/MikroC/ARM_CM4F/port.c      |  32 +++---
 portable/MikroC/ARM_CM4F/portmacro.h | 166 +++++++++++++--------------
 2 files changed, 97 insertions(+), 101 deletions(-)

diff --git a/portable/MikroC/ARM_CM4F/port.c b/portable/MikroC/ARM_CM4F/port.c
index 1e5075d1d..eeeb6b70b 100644
--- a/portable/MikroC/ARM_CM4F/port.c
+++ b/portable/MikroC/ARM_CM4F/port.c
@@ -345,22 +345,22 @@ BaseType_t xPortStartScheduler( void )
         if( ulImplementedPrioBits == 8 )
         {
             /* When the hardware implements 8 priority bits, there is no way for
-             * the software to configure PRIGROUP to not have sub-priorities. As
-             * a result, the least significant bit is always used for sub-priority
-             * and there are 128 preemption priorities and 2 sub-priorities.
-             *
-             * This may cause some confusion in some cases - for example, if
-             * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
-             * priority interrupts will be masked in Critical Sections as those
-             * are at the same preemption priority. This may appear confusing as
-             * 4 is higher (numerically lower) priority than
-             * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
-             * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
-             * to 4, this confusion does not happen and the behaviour remains the same.
-             *
-             * The following assert ensures that the sub-priority bit in the
-             * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
-             * confusion. */
+            * the software to configure PRIGROUP to not have sub-priorities. As
+            * a result, the least significant bit is always used for sub-priority
+            * and there are 128 preemption priorities and 2 sub-priorities.
+            *
+            * This may cause some confusion in some cases - for example, if
+            * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
+            * priority interrupts will be masked in Critical Sections as those
+            * are at the same preemption priority. This may appear confusing as
+            * 4 is higher (numerically lower) priority than
+            * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
+            * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
+            * to 4, this confusion does not happen and the behaviour remains the same.
+            *
+            * The following assert ensures that the sub-priority bit in the
+            * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
+            * confusion. */
             configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
             ulMaxPRIGROUPValue = 0;
         }
diff --git a/portable/MikroC/ARM_CM4F/portmacro.h b/portable/MikroC/ARM_CM4F/portmacro.h
index 6c169773c..3d00da05a 100644
--- a/portable/MikroC/ARM_CM4F/portmacro.h
+++ b/portable/MikroC/ARM_CM4F/portmacro.h
@@ -27,7 +27,7 @@
  */
 
 #ifndef PORTMACRO_H
-#define PORTMACRO_H
+    #define PORTMACRO_H
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
@@ -48,53 +48,53 @@
 /* The compiler needs to be told functions that are only referenced by pointer
  * are to be included in the build.  NOTE:  Omitting these lines will result in a
  * run-time crash, not a linker error! */
-#pragma funcall vTaskStartScheduler prvIdleTask
-#pragma funcall xTimerCreateTimerTask prvTimerTask
+    #pragma funcall vTaskStartScheduler prvIdleTask
+    #pragma funcall xTimerCreateTimerTask prvTimerTask
 
 /* Type definitions. */
-#define portCHAR          char
-#define portFLOAT         float
-#define portDOUBLE        double
-#define portLONG          long
-#define portSHORT         short
-#define portSTACK_TYPE    uint32_t
-#define portBASE_TYPE     long
+    #define portCHAR          char
+    #define portFLOAT         float
+    #define portDOUBLE        double
+    #define portLONG          long
+    #define portSHORT         short
+    #define portSTACK_TYPE    uint32_t
+    #define portBASE_TYPE     long
 
-typedef portSTACK_TYPE   StackType_t;
-typedef long             BaseType_t;
-typedef unsigned long    UBaseType_t;
+    typedef portSTACK_TYPE   StackType_t;
+    typedef long             BaseType_t;
+    typedef unsigned long    UBaseType_t;
 
-#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t     TickType_t;
-    #define portMAX_DELAY              ( TickType_t ) 0xffff
-#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t     TickType_t;
-    #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+    #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+        typedef uint16_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffff
+    #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+        typedef uint32_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
  * not need to be guarded with a critical section. */
-    #define portTICK_TYPE_IS_ATOMIC    1
-#else
-    #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
-#endif
+        #define portTICK_TYPE_IS_ATOMIC    1
+    #else
+        #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+    #endif
 /*-----------------------------------------------------------*/
 
 /* Architecture specifics. */
-#define portSTACK_GROWTH      ( -1 )
-#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT    8
+    #define portSTACK_GROWTH      ( -1 )
+    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+    #define portBYTE_ALIGNMENT    8
 /*-----------------------------------------------------------*/
 
 /* Scheduler utilities. */
-#define portYIELD()                                     \
+    #define portYIELD()                                 \
     {                                                   \
         /* Set a PendSV to request a context switch. */ \
         portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
                                                         \
         /* Barriers are normally not required but do ensure the code is completely \
          * within the specified behaviour for the architecture. */ \
-        __asm { dsb };                                             \
-        __asm { isb };                                             \
+        __asm{ dsb };                                              \
+        __asm{ isb };                                              \
     }
 
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
@@ -116,91 +116,87 @@ typedef unsigned long    UBaseType_t;
 /*-----------------------------------------------------------*/
 
 /* Critical section management. */
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-#define portDISABLE_INTERRUPTS()                  CPU_REG_SET( CPU_BASEPRI, configMAX_SYSCALL_INTERRUPT_PRIORITY ); __asm { dsb }; __asm { isb }
-#define portENABLE_INTERRUPTS()                   CPU_REG_SET( CPU_BASEPRI, 0 );
-#define portENTER_CRITICAL()                      vPortEnterCritical()
-#define portEXIT_CRITICAL()                       vPortExitCritical()
-#define portSET_INTERRUPT_MASK_FROM_ISR()         ulPortRaiseBASEPRI()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    CPU_REG_SET( CPU_BASEPRI, x );     /* Barrier instructions not used as this is only used to lower the basepri. */
+    extern void vPortEnterCritical( void );
+    extern void vPortExitCritical( void );
+    #define portDISABLE_INTERRUPTS()                  CPU_REG_SET( CPU_BASEPRI, configMAX_SYSCALL_INTERRUPT_PRIORITY ); __asm{ dsb }; __asm{ isb }
+    #define portENABLE_INTERRUPTS()                   CPU_REG_SET( CPU_BASEPRI, 0 );
+    #define portENTER_CRITICAL()                      vPortEnterCritical()
+    #define portEXIT_CRITICAL()                       vPortExitCritical()
+    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulPortRaiseBASEPRI()
+    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    CPU_REG_SET( CPU_BASEPRI, x ); /* Barrier instructions not used as this is only used to lower the basepri. */
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site.  These are
  * not necessary for to use this port.  They are defined so the common demo files
  * (which build with all the ports) will build. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 /*-----------------------------------------------------------*/
 
 /* Tickless idle/low power functionality. */
-#ifndef portSUPPRESS_TICKS_AND_SLEEP
-    extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
-    #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
-#endif
+    #ifndef portSUPPRESS_TICKS_AND_SLEEP
+        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
+    #endif
 /*-----------------------------------------------------------*/
 
 /* Architecture specific optimisations. */
-#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-    #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
-#endif
-
-#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-
-/* Generic helper function. */
-    __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
-    {
-        uint8_t ucReturn;
-
-        __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) );
-
-        return ucReturn;
-    }
-
-/* Check the configuration. */
-    #if ( configMAX_PRIORITIES > 32 )
-        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+    #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
     #endif
 
+    #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+/* Generic helper function. */
+        __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
+        {
+            uint8_t ucReturn;
+
+            __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) );
+
+            return ucReturn;
+        }
+
+/* Check the configuration. */
+        #if ( configMAX_PRIORITIES > 32 )
+            #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+        #endif
+
 /* Store/clear the ready priorities in a bit map. */
-    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+        #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+        #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 
 /*-----------------------------------------------------------*/
 
-    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+        #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
 
-#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+    #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 
 /*-----------------------------------------------------------*/
 
-#ifdef configASSERT
-    void vPortValidateInterruptPriority( void );
-    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
-#endif
+    #ifdef configASSERT
+        void vPortValidateInterruptPriority( void );
+        #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
+    #endif
 
 /* portNOP() is not required by this port. */
-#define portNOP()
+    #define portNOP()
 
-BaseType_t xPortIsInsideInterrupt( void );
+    BaseType_t xPortIsInsideInterrupt( void );
 
 /*-----------------------------------------------------------*/
 
-static inline uint32_t ulPortRaiseBASEPRI( void )
-{
-    uint32_t ulOriginalBASEPRI;
+    static inline uint32_t ulPortRaiseBASEPRI( void )
+    {
+        uint32_t ulOriginalBASEPRI;
 
-    ulOriginalBASEPRI = CPU_REG_GET( CPU_BASEPRI );
-    CPU_REG_SET( CPU_BASEPRI, configMAX_SYSCALL_INTERRUPT_PRIORITY );
-    __asm {
-        dsb
-    };
-    __asm {
-        isb
-    };
-    return ulOriginalBASEPRI;
-}
+        ulOriginalBASEPRI = CPU_REG_GET( CPU_BASEPRI );
+        CPU_REG_SET( CPU_BASEPRI, configMAX_SYSCALL_INTERRUPT_PRIORITY );
+        __asm{ dsb };
+        __asm{ isb };
+        return ulOriginalBASEPRI;
+    }
 /*-----------------------------------------------------------*/
 
 /* *INDENT-OFF* */

From 8d1da77d0d9bda1fb9294856e81137a8eabc43d8 Mon Sep 17 00:00:00 2001
From: Soren Ptak <ptaksoren@gmail.com>
Date: Thu, 23 Nov 2023 02:29:40 -0800
Subject: [PATCH 115/424] Revert Portable/MPLAB Formatting (#883)

* Revert the formatting PR

* Fix spelling mistakes

---------

Co-authored-by: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
---
 portable/MPLAB/PIC18F/port.c              | 514 ++++++++-------
 portable/MPLAB/PIC18F/portmacro.h         |  77 ++-
 portable/MPLAB/PIC24_dsPIC/port.c         | 261 ++++----
 portable/MPLAB/PIC24_dsPIC/portmacro.h    |  64 +-
 portable/MPLAB/PIC32MEC14xx/ISR_Support.h | 278 ++++----
 portable/MPLAB/PIC32MEC14xx/port.c        | 198 +++---
 portable/MPLAB/PIC32MEC14xx/portmacro.h   | 201 +++---
 portable/MPLAB/PIC32MX/ISR_Support.h      | 271 ++++----
 portable/MPLAB/PIC32MX/port.c             | 178 +++---
 portable/MPLAB/PIC32MX/portmacro.h        | 170 ++---
 portable/MPLAB/PIC32MZ/ISR_Support.h      | 737 +++++++++++-----------
 portable/MPLAB/PIC32MZ/port.c             | 210 +++---
 portable/MPLAB/PIC32MZ/portmacro.h        | 175 +++--
 13 files changed, 1648 insertions(+), 1686 deletions(-)

diff --git a/portable/MPLAB/PIC18F/port.c b/portable/MPLAB/PIC18F/port.c
index 471a6955e..a26d97116 100644
--- a/portable/MPLAB/PIC18F/port.c
+++ b/portable/MPLAB/PIC18F/port.c
@@ -27,33 +27,33 @@
  */
 
 /*
- * Changes between V1.2.4 and V1.2.5
- *
- + Introduced portGLOBAL_INTERRUPT_FLAG definition to test the global
- +    interrupt flag setting.  Using the two bits defined within
- +    portINITAL_INTERRUPT_STATE was causing the w register to get clobbered
- +    before the test was performed.
- +
- + Changes from V1.2.5
- +
- + Set the interrupt vector address to 0x08.  Previously it was at the
- +    incorrect address for compatibility mode of 0x18.
- +
- + Changes from V2.1.1
- +
- + PCLATU and PCLATH are now saved as part of the context.  This allows
- +    function pointers to be used within tasks.  Thanks to Javier Espeche
- +    for the enhancement.
- +
- + Changes from V2.3.1
- +
- + TABLAT is now saved as part of the task context.
- +
- + Changes from V3.2.0
- +
- + TBLPTRU is now initialised to zero as the MPLAB compiler expects this
- +    value and does not write to the register.
- */
+Changes between V1.2.4 and V1.2.5
+
+    + Introduced portGLOBAL_INTERRUPT_FLAG definition to test the global
+      interrupt flag setting.  Using the two bits defined within
+      portINITAL_INTERRUPT_STATE was causing the w register to get clobbered
+      before the test was performed.
+
+Changes from V1.2.5
+
+    + Set the interrupt vector address to 0x08.  Previously it was at the
+      incorrect address for compatibility mode of 0x18.
+
+Changes from V2.1.1
+
+    + PCLATU and PCLATH are now saved as part of the context.  This allows
+      function pointers to be used within tasks.  Thanks to Javier Espeche
+      for the enhancement.
+
+Changes from V2.3.1
+
+    + TABLAT is now saved as part of the task context.
+
+Changes from V3.2.0
+
+    + TBLPTRU is now initialised to zero as the MPLAB compiler expects this
+      value and does not write to the register.
+*/
 
 /* Scheduler include files. */
 #include "FreeRTOS.h"
@@ -63,37 +63,37 @@
 #include "timers.h"
 
 /*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the PIC port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the PIC port.
+ *----------------------------------------------------------*/
 
 /* Hardware setup for tick. */
-#define portTIMER_FOSC_SCALE                ( ( uint32_t ) 4 )
+#define portTIMER_FOSC_SCALE            ( ( uint32_t ) 4 )
 
 /* Initial interrupt enable state for newly created tasks.  This value is
- * copied into INTCON when a task switches in for the first time. */
+copied into INTCON when a task switches in for the first time. */
 #define portINITAL_INTERRUPT_STATE          0xc0
 
 /* Just the bit within INTCON for the global interrupt flag. */
 #define portGLOBAL_INTERRUPT_FLAG           0x80
 
 /* Constant used for context switch macro when we require the interrupt
- * enable state to be unchanged when the interrupted task is switched back in. */
+enable state to be unchanged when the interrupted task is switched back in. */
 #define portINTERRUPTS_UNCHANGED            0x00
 
 /* Some memory areas get saved as part of the task context.  These memory
- * area's get used by the compiler for temporary storage, especially when
- * performing mathematical operations, or when using 32bit data types.  This
- * constant defines the size of memory area which must be saved. */
+area's get used by the compiler for temporary storage, especially when
+performing mathematical operations, or when using 32bit data types.  This
+constant defines the size of memory area which must be saved. */
 #define portCOMPILER_MANAGED_MEMORY_SIZE    ( ( uint8_t ) 0x13 )
 
 /* We require the address of the pxCurrentTCB variable, but don't want to know
- * any details of its type. */
+any details of its type. */
 typedef void TCB_t;
 extern volatile TCB_t * volatile pxCurrentTCB;
 
 /* IO port constants. */
-#define portBIT_SET      ( ( uint8_t ) 1 )
-#define portBIT_CLEAR    ( ( uint8_t ) 0 )
+#define portBIT_SET     ( ( uint8_t ) 1 )
+#define portBIT_CLEAR   ( ( uint8_t ) 0 )
 
 /*
  * The serial port ISR's are defined in serial.c, but are called from portable
@@ -136,7 +136,7 @@ static void prvLowInterrupt( void );
  *
  * The compiler uses some locations at the bottom of the memory for temporary
  * storage during math and other computations.  This is especially true if
- * 32bit data types are used (as they are by the scheduler).  The .tmpdata
+ * 32bit data types are utilized (as they are by the scheduler).  The .tmpdata
  * and MATH_DATA sections have to be stored in there entirety as part of a task
  * context.  This macro stores from data address 0x00 to
  * portCOMPILER_MANAGED_MEMORY_SIZE.  This is sufficient for the demo
@@ -144,214 +144,212 @@ static void prvLowInterrupt( void );
  * this is sufficient for your needs.  It is not clear whether this size is
  * fixed for all compilations or has the potential to be program specific.
  */
-#define portSAVE_CONTEXT( ucForcedInterruptFlags ) \
-    {                                              \
-        _asm                                       \
+#define portSAVE_CONTEXT( ucForcedInterruptFlags )                              \
+{                                                                               \
+    _asm                                                                        \
         /* Save the status and WREG registers first, as these will get modified \
-         * by the operations below. */ \
-        MOVFF WREG, PREINC1            \
-        MOVFF STATUS, PREINC1          \
-        /* Save the INTCON register with the appropriate bits forced if \
-         * necessary - as described above. */                             \
-        MOVFF INTCON, WREG                                                \
-        IORLW ucForcedInterruptFlags                                      \
-        MOVFF WREG, PREINC1                                               \
-        _endasm                                                           \
-                                                                          \
-        portDISABLE_INTERRUPTS();                                         \
-                                                                          \
-        _asm                                                              \
-        /* Store the necessary registers to the stack. */                 \
-        MOVFF BSR, PREINC1                                                \
-        MOVFF FSR2L, PREINC1                                              \
-        MOVFF FSR2H, PREINC1                                              \
-        MOVFF FSR0L, PREINC1                                              \
-        MOVFF FSR0H, PREINC1                                              \
-        MOVFF TABLAT, PREINC1                                             \
-        MOVFF TBLPTRU, PREINC1                                            \
-        MOVFF TBLPTRH, PREINC1                                            \
-        MOVFF TBLPTRL, PREINC1                                            \
-        MOVFF PRODH, PREINC1                                              \
-        MOVFF PRODL, PREINC1                                              \
-        MOVFF PCLATU, PREINC1                                             \
-        MOVFF PCLATH, PREINC1                                             \
-        /* Store the .tempdata and MATH_DATA areas as described above. */ \
-        CLRF FSR0L, 0                                                     \
-        CLRF FSR0H, 0                                                     \
-        MOVFF POSTINC0, PREINC1                                           \
-        MOVFF POSTINC0, PREINC1                                           \
-        MOVFF POSTINC0, PREINC1                                           \
-        MOVFF POSTINC0, PREINC1                                           \
-        MOVFF POSTINC0, PREINC1                                           \
-        MOVFF POSTINC0, PREINC1                                           \
-        MOVFF POSTINC0, PREINC1                                           \
-        MOVFF POSTINC0, PREINC1                                           \
-        MOVFF POSTINC0, PREINC1                                           \
-        MOVFF POSTINC0, PREINC1                                           \
-        MOVFF POSTINC0, PREINC1                                           \
-        MOVFF POSTINC0, PREINC1                                           \
-        MOVFF POSTINC0, PREINC1                                           \
-        MOVFF POSTINC0, PREINC1                                           \
-        MOVFF POSTINC0, PREINC1                                           \
-        MOVFF POSTINC0, PREINC1                                           \
-        MOVFF POSTINC0, PREINC1                                           \
-        MOVFF POSTINC0, PREINC1                                           \
-        MOVFF POSTINC0, PREINC1                                           \
-        MOVFF INDF0, PREINC1                                              \
-        MOVFF FSR0L, PREINC1                                              \
-        MOVFF FSR0H, PREINC1                                              \
-        /* Store the hardware stack pointer in a temp register before we \
-         * modify it. */                                  \
-        MOVFF STKPTR, FSR0L                               \
-        _endasm                                           \
-                                                          \
-        /* Store each address from the hardware stack. */ \
-        while( STKPTR > ( uint8_t ) 0 )                   \
-        {                                                 \
-            _asm                                          \
-            MOVFF TOSL, PREINC1                           \
-            MOVFF TOSH, PREINC1                           \
-            MOVFF TOSU, PREINC1                           \
-            POP                                           \
-            _endasm                                       \
-        }                                                 \
-                                                          \
-        _asm                                              \
-        /* Store the number of addresses on the hardware stack (from the \
-         * temporary register). */                               \
-        MOVFF FSR0L, PREINC1                                     \
-        MOVF PREINC1, 1, 0                                       \
-        _endasm                                                  \
-                                                                 \
-        /* Save the new top of the software stack in the TCB. */ \
-        _asm                                                     \
-        MOVFF pxCurrentTCB, FSR0L                                \
-        MOVFF pxCurrentTCB + 1, FSR0H                            \
-        MOVFF FSR1L, POSTINC0                                    \
-        MOVFF FSR1H, POSTINC0                                    \
-        _endasm                                                  \
-    }
+        by the operations below. */                                             \
+        MOVFF   WREG, PREINC1                                                   \
+        MOVFF   STATUS, PREINC1                                                 \
+        /* Save the INTCON register with the appropriate bits forced if         \
+        necessary - as described above. */                                      \
+        MOVFF   INTCON, WREG                                                    \
+        IORLW   ucForcedInterruptFlags                                          \
+        MOVFF   WREG, PREINC1                                                   \
+    _endasm                                                                     \
+                                                                                \
+    portDISABLE_INTERRUPTS();                                                   \
+                                                                                \
+    _asm                                                                        \
+        /* Store the necessary registers to the stack. */                       \
+        MOVFF   BSR, PREINC1                                                    \
+        MOVFF   FSR2L, PREINC1                                                  \
+        MOVFF   FSR2H, PREINC1                                                  \
+        MOVFF   FSR0L, PREINC1                                                  \
+        MOVFF   FSR0H, PREINC1                                                  \
+        MOVFF   TABLAT, PREINC1                                                 \
+        MOVFF   TBLPTRU, PREINC1                                                \
+        MOVFF   TBLPTRH, PREINC1                                                \
+        MOVFF   TBLPTRL, PREINC1                                                \
+        MOVFF   PRODH, PREINC1                                                  \
+        MOVFF   PRODL, PREINC1                                                  \
+        MOVFF   PCLATU, PREINC1                                                 \
+        MOVFF   PCLATH, PREINC1                                                 \
+        /* Store the .tempdata and MATH_DATA areas as described above. */       \
+        CLRF    FSR0L, 0                                                        \
+        CLRF    FSR0H, 0                                                        \
+        MOVFF   POSTINC0, PREINC1                                               \
+        MOVFF   POSTINC0, PREINC1                                               \
+        MOVFF   POSTINC0, PREINC1                                               \
+        MOVFF   POSTINC0, PREINC1                                               \
+        MOVFF   POSTINC0, PREINC1                                               \
+        MOVFF   POSTINC0, PREINC1                                               \
+        MOVFF   POSTINC0, PREINC1                                               \
+        MOVFF   POSTINC0, PREINC1                                               \
+        MOVFF   POSTINC0, PREINC1                                               \
+        MOVFF   POSTINC0, PREINC1                                               \
+        MOVFF   POSTINC0, PREINC1                                               \
+        MOVFF   POSTINC0, PREINC1                                               \
+        MOVFF   POSTINC0, PREINC1                                               \
+        MOVFF   POSTINC0, PREINC1                                               \
+        MOVFF   POSTINC0, PREINC1                                               \
+        MOVFF   POSTINC0, PREINC1                                               \
+        MOVFF   POSTINC0, PREINC1                                               \
+        MOVFF   POSTINC0, PREINC1                                               \
+        MOVFF   POSTINC0, PREINC1                                               \
+        MOVFF   INDF0, PREINC1                                                  \
+        MOVFF   FSR0L, PREINC1                                                  \
+        MOVFF   FSR0H, PREINC1                                                  \
+        /* Store the hardware stack pointer in a temp register before we        \
+        modify it. */                                                           \
+        MOVFF   STKPTR, FSR0L                                                   \
+    _endasm                                                                     \
+                                                                                \
+        /* Store each address from the hardware stack. */                       \
+        while( STKPTR > ( uint8_t ) 0 )                             \
+        {                                                                       \
+            _asm                                                                \
+                MOVFF   TOSL, PREINC1                                           \
+                MOVFF   TOSH, PREINC1                                           \
+                MOVFF   TOSU, PREINC1                                           \
+                POP                                                             \
+            _endasm                                                             \
+        }                                                                       \
+                                                                                \
+    _asm                                                                        \
+        /* Store the number of addresses on the hardware stack (from the        \
+        temporary register). */                                                 \
+        MOVFF   FSR0L, PREINC1                                                  \
+        MOVF    PREINC1, 1, 0                                                   \
+    _endasm                                                                     \
+                                                                                \
+    /* Save the new top of the software stack in the TCB. */                    \
+    _asm                                                                        \
+        MOVFF   pxCurrentTCB, FSR0L                                             \
+        MOVFF   pxCurrentTCB + 1, FSR0H                                         \
+        MOVFF   FSR1L, POSTINC0                                                 \
+        MOVFF   FSR1H, POSTINC0                                                 \
+    _endasm                                                                     \
+}
 /*-----------------------------------------------------------*/
 
 /*
  * This is the reverse of portSAVE_CONTEXT.  See portSAVE_CONTEXT for more
  * details.
  */
-#define portRESTORE_CONTEXT()                                  \
-    {                                                          \
-        _asm                                                   \
-        /* Set FSR0 to point to pxCurrentTCB->pxTopOfStack. */ \
-        MOVFF pxCurrentTCB, FSR0L                              \
-        MOVFF pxCurrentTCB + 1, FSR0H                          \
-                                                               \
-        /* De-reference FSR0 to set the address it holds into FSR1. \
-         * (i.e. *( pxCurrentTCB->pxTopOfStack ) ). */ \
-        MOVFF POSTINC0, FSR1L                          \
-        MOVFF POSTINC0, FSR1H                          \
-                                                       \
-        /* How many return addresses are there on the hardware stack?  Discard \
-         * the first byte as we are pointing to the next free space. */ \
-        MOVFF POSTDEC1, FSR0L                                           \
-        MOVFF POSTDEC1, FSR0L                                           \
-        _endasm                                                         \
-                                                                        \
-        /* Fill the hardware stack from our software stack. */          \
-        STKPTR = 0;                                                     \
-                                                                        \
-        while( STKPTR < FSR0L )                                         \
-        {                                                               \
-            _asm                                                        \
-            PUSH                                                        \
-            MOVF POSTDEC1, 0, 0                                         \
-            MOVWF TOSU, 0                                               \
-            MOVF POSTDEC1, 0, 0                                         \
-            MOVWF TOSH, 0                                               \
-            MOVF POSTDEC1, 0, 0                                         \
-            MOVWF TOSL, 0                                               \
-            _endasm                                                     \
-        }                                                               \
-                                                                        \
-        _asm                                                            \
-        /* Restore the .tmpdata and MATH_DATA memory. */                \
-        MOVFF POSTDEC1, FSR0H                                           \
-        MOVFF POSTDEC1, FSR0L                                           \
-        MOVFF POSTDEC1, POSTDEC0                                        \
-        MOVFF POSTDEC1, POSTDEC0                                        \
-        MOVFF POSTDEC1, POSTDEC0                                        \
-        MOVFF POSTDEC1, POSTDEC0                                        \
-        MOVFF POSTDEC1, POSTDEC0                                        \
-        MOVFF POSTDEC1, POSTDEC0                                        \
-        MOVFF POSTDEC1, POSTDEC0                                        \
-        MOVFF POSTDEC1, POSTDEC0                                        \
-        MOVFF POSTDEC1, POSTDEC0                                        \
-        MOVFF POSTDEC1, POSTDEC0                                        \
-        MOVFF POSTDEC1, POSTDEC0                                        \
-        MOVFF POSTDEC1, POSTDEC0                                        \
-        MOVFF POSTDEC1, POSTDEC0                                        \
-        MOVFF POSTDEC1, POSTDEC0                                        \
-        MOVFF POSTDEC1, POSTDEC0                                        \
-        MOVFF POSTDEC1, POSTDEC0                                        \
-        MOVFF POSTDEC1, POSTDEC0                                        \
-        MOVFF POSTDEC1, POSTDEC0                                        \
-        MOVFF POSTDEC1, POSTDEC0                                        \
-        MOVFF POSTDEC1, INDF0                                           \
-        /* Restore the other registers forming the tasks context. */    \
-        MOVFF POSTDEC1, PCLATH                                          \
-        MOVFF POSTDEC1, PCLATU                                          \
-        MOVFF POSTDEC1, PRODL                                           \
-        MOVFF POSTDEC1, PRODH                                           \
-        MOVFF POSTDEC1, TBLPTRL                                         \
-        MOVFF POSTDEC1, TBLPTRH                                         \
-        MOVFF POSTDEC1, TBLPTRU                                         \
-        MOVFF POSTDEC1, TABLAT                                          \
-        MOVFF POSTDEC1, FSR0H                                           \
-        MOVFF POSTDEC1, FSR0L                                           \
-        MOVFF POSTDEC1, FSR2H                                           \
-        MOVFF POSTDEC1, FSR2L                                           \
-        MOVFF POSTDEC1, BSR                                             \
-        /* The next byte is the INTCON register.  Read this into WREG as some \
-         * manipulation is required. */ \
-        MOVFF POSTDEC1, WREG            \
-        _endasm                         \
-                                        \
-        /* From the INTCON register, only the interrupt enable bits form part \
-         * of the tasks context.  It is perfectly legitimate for another task to \
-         * have modified any other bits.  We therefore only restore the top two bits. \
-         */                                   \
-        if( WREG &portGLOBAL_INTERRUPT_FLAG ) \
-        {                                     \
-            _asm                              \
-            MOVFF POSTDEC1, STATUS            \
-            MOVFF POSTDEC1, WREG              \
-            /* Return enabling interrupts. */ \
-            RETFIE 0                          \
-            _endasm                           \
-        }                                     \
-        else                                  \
-        {                                     \
-            _asm                              \
-            MOVFF POSTDEC1, STATUS            \
-            MOVFF POSTDEC1, WREG              \
-            /* Return without effecting interrupts.  The context may have \
-             * been saved from a critical region. */ \
-            RETURN 0                                 \
-            _endasm                                  \
-        }                                            \
-    }
+#define portRESTORE_CONTEXT()                                                   \
+{                                                                               \
+    _asm                                                                        \
+        /* Set FSR0 to point to pxCurrentTCB->pxTopOfStack. */                  \
+        MOVFF   pxCurrentTCB, FSR0L                                             \
+        MOVFF   pxCurrentTCB + 1, FSR0H                                         \
+                                                                                \
+        /* De-reference FSR0 to set the address it holds into FSR1.             \
+        (i.e. *( pxCurrentTCB->pxTopOfStack ) ). */                             \
+        MOVFF   POSTINC0, FSR1L                                                 \
+        MOVFF   POSTINC0, FSR1H                                                 \
+                                                                                \
+        /* How many return addresses are there on the hardware stack?  Discard  \
+        the first byte as we are pointing to the next free space. */            \
+        MOVFF   POSTDEC1, FSR0L                                                 \
+        MOVFF   POSTDEC1, FSR0L                                                 \
+    _endasm                                                                     \
+                                                                                \
+    /* Fill the hardware stack from our software stack. */                      \
+    STKPTR = 0;                                                                 \
+                                                                                \
+    while( STKPTR < FSR0L )                                                     \
+    {                                                                           \
+        _asm                                                                    \
+            PUSH                                                                \
+            MOVF    POSTDEC1, 0, 0                                              \
+            MOVWF   TOSU, 0                                                     \
+            MOVF    POSTDEC1, 0, 0                                              \
+            MOVWF   TOSH, 0                                                     \
+            MOVF    POSTDEC1, 0, 0                                              \
+            MOVWF   TOSL, 0                                                     \
+        _endasm                                                                 \
+    }                                                                           \
+                                                                                \
+    _asm                                                                        \
+        /* Restore the .tmpdata and MATH_DATA memory. */                        \
+        MOVFF   POSTDEC1, FSR0H                                                 \
+        MOVFF   POSTDEC1, FSR0L                                                 \
+        MOVFF   POSTDEC1, POSTDEC0                                              \
+        MOVFF   POSTDEC1, POSTDEC0                                              \
+        MOVFF   POSTDEC1, POSTDEC0                                              \
+        MOVFF   POSTDEC1, POSTDEC0                                              \
+        MOVFF   POSTDEC1, POSTDEC0                                              \
+        MOVFF   POSTDEC1, POSTDEC0                                              \
+        MOVFF   POSTDEC1, POSTDEC0                                              \
+        MOVFF   POSTDEC1, POSTDEC0                                              \
+        MOVFF   POSTDEC1, POSTDEC0                                              \
+        MOVFF   POSTDEC1, POSTDEC0                                              \
+        MOVFF   POSTDEC1, POSTDEC0                                              \
+        MOVFF   POSTDEC1, POSTDEC0                                              \
+        MOVFF   POSTDEC1, POSTDEC0                                              \
+        MOVFF   POSTDEC1, POSTDEC0                                              \
+        MOVFF   POSTDEC1, POSTDEC0                                              \
+        MOVFF   POSTDEC1, POSTDEC0                                              \
+        MOVFF   POSTDEC1, POSTDEC0                                              \
+        MOVFF   POSTDEC1, POSTDEC0                                              \
+        MOVFF   POSTDEC1, POSTDEC0                                              \
+        MOVFF   POSTDEC1, INDF0                                                 \
+        /* Restore the other registers forming the tasks context. */            \
+        MOVFF   POSTDEC1, PCLATH                                                \
+        MOVFF   POSTDEC1, PCLATU                                                \
+        MOVFF   POSTDEC1, PRODL                                                 \
+        MOVFF   POSTDEC1, PRODH                                                 \
+        MOVFF   POSTDEC1, TBLPTRL                                               \
+        MOVFF   POSTDEC1, TBLPTRH                                               \
+        MOVFF   POSTDEC1, TBLPTRU                                               \
+        MOVFF   POSTDEC1, TABLAT                                                \
+        MOVFF   POSTDEC1, FSR0H                                                 \
+        MOVFF   POSTDEC1, FSR0L                                                 \
+        MOVFF   POSTDEC1, FSR2H                                                 \
+        MOVFF   POSTDEC1, FSR2L                                                 \
+        MOVFF   POSTDEC1, BSR                                                   \
+        /* The next byte is the INTCON register.  Read this into WREG as some   \
+        manipulation is required. */                                            \
+        MOVFF   POSTDEC1, WREG                                                  \
+    _endasm                                                                     \
+                                                                                \
+    /* From the INTCON register, only the interrupt enable bits form part       \
+    of the tasks context.  It is perfectly legitimate for another task to       \
+    have modified any other bits.  We therefore only restore the top two bits.  \
+    */                                                                          \
+    if( WREG & portGLOBAL_INTERRUPT_FLAG )                                      \
+    {                                                                           \
+        _asm                                                                    \
+            MOVFF   POSTDEC1, STATUS                                            \
+            MOVFF   POSTDEC1, WREG                                              \
+            /* Return enabling interrupts. */                                   \
+            RETFIE  0                                                           \
+        _endasm                                                                 \
+    }                                                                           \
+    else                                                                        \
+    {                                                                           \
+        _asm                                                                    \
+            MOVFF   POSTDEC1, STATUS                                            \
+            MOVFF   POSTDEC1, WREG                                              \
+            /* Return without effecting interrupts.  The context may have       \
+            been saved from a critical region. */                               \
+            RETURN  0                                                           \
+        _endasm                                                                 \
+    }                                                                           \
+}
 /*-----------------------------------------------------------*/
 
 /*
  * See header file for description.
  */
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
 {
-    uint32_t ulAddress;
-    uint8_t ucBlock;
+uint32_t ulAddress;
+uint8_t ucBlock;
 
     /* Place a few bytes of known values on the bottom of the stack.
-     * This is just useful for debugging. */
+    This is just useful for debugging. */
 
     *pxTopOfStack = 0x11;
     pxTopOfStack++;
@@ -362,10 +360,10 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
 
 
     /* Simulate how the stack would look after a call to vPortYield() generated
-     * by the compiler.
-     *
-     * First store the function parameters.  This is where the task will expect to
-     * find them when it starts running. */
+    by the compiler.
+
+    First store the function parameters.  This is where the task will expect to
+    find them when it starts running. */
     ulAddress = ( uint32_t ) pvParameters;
     *pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
     pxTopOfStack++;
@@ -375,9 +373,9 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
     pxTopOfStack++;
 
     /* Next we just leave a space.  When a context is saved the stack pointer
-     * is incremented before it is used so as not to corrupt whatever the stack
-     * pointer is actually pointing to.  This is especially necessary during
-     * function epilogue code generated by the compiler. */
+    is incremented before it is used so as not to corrupt whatever the stack
+    pointer is actually pointing to.  This is especially necessary during
+    function epilogue code generated by the compiler. */
     *pxTopOfStack = 0x44;
     pxTopOfStack++;
 
@@ -447,7 +445,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
     pxTopOfStack++;
 
     /* The only function return address so far is the address of the
-     * task. */
+    task. */
     ulAddress = ( uint32_t ) pxCode;
 
     /* TOS low. */
@@ -465,7 +463,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
     pxTopOfStack++;
 
     /* Store the number of return addresses on the hardware stack - so far only
-     * the address of the task entry point. */
+    the address of the task entry point. */
     *pxTopOfStack = ( StackType_t ) 1;
     pxTopOfStack++;
 
@@ -492,8 +490,8 @@ BaseType_t xPortStartScheduler( void )
 void vPortEndScheduler( void )
 {
     /* It is unlikely that the scheduler for the PIC port will get stopped
-     * once running.  If required disable the tick interrupt here, then return
-     * to xPortStartScheduler(). */
+    once running.  If required disable the tick interrupt here, then return
+    to xPortStartScheduler(). */
 }
 /*-----------------------------------------------------------*/
 
@@ -505,7 +503,7 @@ void vPortEndScheduler( void )
 void vPortYield( void )
 {
     /* This can get called with interrupts either enabled or disabled.  We
-     * will save the INTCON register with the interrupt enable bits unmodified. */
+    will save the INTCON register with the interrupt enable bits unmodified. */
     portSAVE_CONTEXT( portINTERRUPTS_UNCHANGED );
 
     /* Switch to the highest priority task that is ready to run. */
@@ -526,7 +524,7 @@ static void prvLowInterrupt( void )
     if( PIR1bits.CCP1IF )
     {
         _asm
-        goto prvTickISR
+            goto prvTickISR
         _endasm
     }
 
@@ -534,7 +532,7 @@ static void prvLowInterrupt( void )
     if( PIR1bits.RCIF )
     {
         _asm
-        goto vSerialRxISR
+            goto vSerialRxISR
         _endasm
     }
 
@@ -544,7 +542,7 @@ static void prvLowInterrupt( void )
         if( PIE1bits.TXIE )
         {
             _asm
-            goto vSerialTxISR
+                goto vSerialTxISR
             _endasm
         }
     }
@@ -562,7 +560,7 @@ static void prvLowInterrupt( void )
 static void prvTickISR( void )
 {
     /* Interrupts must have been enabled for the ISR to fire, so we have to
-     * save the context with interrupts enabled. */
+    save the context with interrupts enabled. */
     portSAVE_CONTEXT( portGLOBAL_INTERRUPT_FLAG );
     PIR1bits.CCP1IF = 0;
 
@@ -582,16 +580,16 @@ static void prvTickISR( void )
  */
 static void prvSetupTimerInterrupt( void )
 {
-    const uint32_t ulConstCompareValue = ( ( configCPU_CLOCK_HZ / portTIMER_FOSC_SCALE ) / configTICK_RATE_HZ );
-    uint32_t ulCompareValue;
-    uint8_t ucByte;
+const uint32_t ulConstCompareValue = ( ( configCPU_CLOCK_HZ / portTIMER_FOSC_SCALE ) / configTICK_RATE_HZ );
+uint32_t ulCompareValue;
+uint8_t ucByte;
 
     /* Interrupts are disabled when this function is called.
-     *
-     * Setup CCP1 to provide the tick interrupt using a compare match on timer
-     * 1.
-     *
-     * Clear the time count then setup timer. */
+
+    Setup CCP1 to provide the tick interrupt using a compare match on timer
+    1.
+
+    Clear the time count then setup timer. */
     TMR1H = ( uint8_t ) 0x00;
     TMR1L = ( uint8_t ) 0x00;
 
@@ -608,10 +606,10 @@ static void prvSetupTimerInterrupt( void )
     PIE1bits.CCP1IE = portBIT_SET;      /*< Interrupt enable. */
 
     /* We are only going to use the global interrupt bit, so set the peripheral
-     * bit to true. */
+    bit to true. */
     INTCONbits.GIEL = portBIT_SET;
 
     /* Provided library function for setting up the timer that will produce the
-     * tick. */
+    tick. */
     OpenTimer1( T1_16BIT_RW & T1_SOURCE_INT & T1_PS_1_1 & T1_CCP1_T3_CCP2 );
 }
diff --git a/portable/MPLAB/PIC18F/portmacro.h b/portable/MPLAB/PIC18F/portmacro.h
index 11f21cfc9..80e83ed9e 100644
--- a/portable/MPLAB/PIC18F/portmacro.h
+++ b/portable/MPLAB/PIC18F/portmacro.h
@@ -40,23 +40,23 @@
  */
 
 /* Type definitions. */
-#define portCHAR          char
-#define portFLOAT         float
-#define portDOUBLE        double
-#define portLONG          long
-#define portSHORT         int
-#define portSTACK_TYPE    uint8_t
-#define portBASE_TYPE     char
+#define portCHAR        char
+#define portFLOAT       float
+#define portDOUBLE      double
+#define portLONG        long
+#define portSHORT       int
+#define portSTACK_TYPE  uint8_t
+#define portBASE_TYPE   char
 
-typedef portSTACK_TYPE   StackType_t;
-typedef signed char      BaseType_t;
-typedef unsigned char    UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef signed char BaseType_t;
+typedef unsigned char UBaseType_t;
 
-#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t     TickType_t;
-    #define portMAX_DELAY    ( TickType_t ) 0xffff
-#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t     TickType_t;
+#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t TickType_t;
+    #define portMAX_DELAY ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS  == TICK_TYPE_WIDTH_32_BITS )
+    typedef uint32_t             TickType_t;
     #define portMAX_DELAY    ( TickType_t ) 0xffffffffUL
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -64,10 +64,10 @@ typedef unsigned char    UBaseType_t;
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portBYTE_ALIGNMENT           1
-#define portGLOBAL_INT_ENABLE_BIT    0x80
-#define portSTACK_GROWTH             1
-#define portTICK_PERIOD_MS           ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT          1
+#define portGLOBAL_INT_ENABLE_BIT   0x80
+#define portSTACK_GROWTH            1
+#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
 /*-----------------------------------------------------------*/
 
 /* Critical section management. */
@@ -75,32 +75,30 @@ typedef unsigned char    UBaseType_t;
 #define portENABLE_INTERRUPTS()     INTCONbits.GIEH = 1;
 
 /* Push the INTCON register onto the stack, then disable interrupts. */
-#define portENTER_CRITICAL() \
-    POSTINC1 = INTCON;       \
-    INTCONbits.GIEH = 0;
+#define portENTER_CRITICAL()        POSTINC1 = INTCON;              \
+                                    INTCONbits.GIEH = 0;
 
 /* Retrieve the INTCON register from the stack, and enable interrupts
- * if they were saved as being enabled.  Don't modify any other bits
- * within the INTCON register as these may have legitimately have been
- * modified within the critical region. */
-#define portEXIT_CRITICAL()                 \
-    _asm                                    \
-    MOVF POSTDEC1, 1, 0                     \
-    _endasm                                 \
-    if( INDF1 & portGLOBAL_INT_ENABLE_BIT ) \
-    {                                       \
-        portENABLE_INTERRUPTS();            \
-    }
+if they were saved as being enabled.  Don't modify any other bits
+within the INTCON register as these may have legitimately have been
+modified within the critical region. */
+#define portEXIT_CRITICAL()         _asm                                    \
+                                        MOVF    POSTDEC1, 1, 0              \
+                                    _endasm                                 \
+                                    if( INDF1 & portGLOBAL_INT_ENABLE_BIT ) \
+                                    {                                       \
+                                        portENABLE_INTERRUPTS();            \
+                                    }
 /*-----------------------------------------------------------*/
 
 /* Task utilities. */
 extern void vPortYield( void );
-#define portYIELD()    vPortYield()
+#define portYIELD()             vPortYield()
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
 /*-----------------------------------------------------------*/
 
 /* Required by the kernel aware debugger. */
@@ -109,9 +107,8 @@ extern void vPortYield( void );
 #endif
 
 
-#define portNOP() \
-    _asm          \
-    NOP           \
-    _endasm
+#define portNOP()               _asm    \
+                                    NOP \
+                                _endasm
 
 #endif /* PORTMACRO_H */
diff --git a/portable/MPLAB/PIC24_dsPIC/port.c b/portable/MPLAB/PIC24_dsPIC/port.c
index dfbce1128..6f23fe8a2 100644
--- a/portable/MPLAB/PIC24_dsPIC/port.c
+++ b/portable/MPLAB/PIC24_dsPIC/port.c
@@ -27,38 +27,38 @@
  */
 
 /*
- *  Changes from V4.2.1
- *
- + Introduced the configKERNEL_INTERRUPT_PRIORITY definition.
- */
+    Changes from V4.2.1
+
+    + Introduced the configKERNEL_INTERRUPT_PRIORITY definition.
+*/
 
 /*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the PIC24 port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the PIC24 port.
+ *----------------------------------------------------------*/
 
 /* Scheduler include files. */
 #include "FreeRTOS.h"
 #include "task.h"
 
 /* Hardware specifics. */
-#define portBIT_SET           1
-#define portTIMER_PRESCALE    8
-#define portINITIAL_SR        0
+#define portBIT_SET 1
+#define portTIMER_PRESCALE 8
+#define portINITIAL_SR  0
 
 /* Defined for backward compatability with project created prior to
- * FreeRTOS.org V4.3.0. */
+FreeRTOS.org V4.3.0. */
 #ifndef configKERNEL_INTERRUPT_PRIORITY
-    #define configKERNEL_INTERRUPT_PRIORITY    1
+    #define configKERNEL_INTERRUPT_PRIORITY 1
 #endif
 
 /* Use _T1Interrupt as the interrupt handler name if the application writer has
- * not provided their own. */
+not provided their own. */
 #ifndef configTICK_INTERRUPT_HANDLER
-    #define configTICK_INTERRUPT_HANDLER    _T1Interrupt
+    #define configTICK_INTERRUPT_HANDLER _T1Interrupt
 #endif /* configTICK_INTERRUPT_HANDLER */
 
 /* The program counter is only 23 bits. */
-#define portUNUSED_PR_BITS    0x7f
+#define portUNUSED_PR_BITS  0x7f
 
 /* Records the nesting depth of calls to portENTER_CRITICAL(). */
 UBaseType_t uxCriticalNesting = 0xef;
@@ -67,89 +67,89 @@ UBaseType_t uxCriticalNesting = 0xef;
     #error If configKERNEL_INTERRUPT_PRIORITY is not 1 then the #32 in the following macros needs changing to equal the portINTERRUPT_BITS value, which is ( configKERNEL_INTERRUPT_PRIORITY << 5 )
 #endif
 
-#if defined( __PIC24E__ ) || defined( __PIC24F__ ) || defined( __PIC24FK__ ) || defined( __PIC24H__ )
+#if defined( __PIC24E__ ) || defined ( __PIC24F__ ) || defined( __PIC24FK__ ) || defined( __PIC24H__ )
 
     #ifdef __HAS_EDS__
-        #define portRESTORE_CONTEXT()                                                                           \
-    asm volatile ( "MOV    _pxCurrentTCB, W0       \n" /* Restore the stack pointer for the task. */            \
-                   "MOV    [W0], W15               \n"                                                          \
-                   "POP    W0                      \n" /* Restore the critical nesting counter for the task. */ \
-                   "MOV    W0, _uxCriticalNesting  \n"                                                          \
-                   "POP    DSWPAG                  \n"                                                          \
-                   "POP    DSRPAG                  \n"                                                          \
-                   "POP    CORCON                  \n"                                                          \
-                   "POP    TBLPAG                  \n"                                                          \
-                   "POP    RCOUNT                  \n" /* Restore the registers from the stack. */              \
-                   "POP    W14                     \n"                                                          \
-                   "POP.D  W12                     \n"                                                          \
-                   "POP.D  W10                     \n"                                                          \
-                   "POP.D  W8                      \n"                                                          \
-                   "POP.D  W6                      \n"                                                          \
-                   "POP.D  W4                      \n"                                                          \
-                   "POP.D  W2                      \n"                                                          \
-                   "POP.D  W0                      \n"                                                          \
-                   "POP    SR                        " );
+        #define portRESTORE_CONTEXT()                                                                                       \
+                    asm volatile(   "MOV    _pxCurrentTCB, W0       \n" /* Restore the stack pointer for the task. */       \
+                            "MOV    [W0], W15               \n"                                                             \
+                            "POP    W0                      \n" /* Restore the critical nesting counter for the task. */    \
+                            "MOV    W0, _uxCriticalNesting  \n"                                                             \
+                            "POP    DSWPAG                  \n"                                                             \
+                            "POP    DSRPAG                  \n"                                                             \
+                            "POP    CORCON                  \n"                                                             \
+                            "POP    TBLPAG                  \n"                                                             \
+                            "POP    RCOUNT                  \n" /* Restore the registers from the stack. */                 \
+                            "POP    W14                     \n"                                                             \
+                            "POP.D  W12                     \n"                                                             \
+                            "POP.D  W10                     \n"                                                             \
+                            "POP.D  W8                      \n"                                                             \
+                            "POP.D  W6                      \n"                                                             \
+                            "POP.D  W4                      \n"                                                             \
+                            "POP.D  W2                      \n"                                                             \
+                            "POP.D  W0                      \n"                                                             \
+                            "POP    SR                        " );
     #else /* __HAS_EDS__ */
-        #define portRESTORE_CONTEXT()                                                                           \
-    asm volatile ( "MOV    _pxCurrentTCB, W0       \n" /* Restore the stack pointer for the task. */            \
-                   "MOV    [W0], W15               \n"                                                          \
-                   "POP    W0                      \n" /* Restore the critical nesting counter for the task. */ \
-                   "MOV    W0, _uxCriticalNesting  \n"                                                          \
-                   "POP    PSVPAG                  \n"                                                          \
-                   "POP    CORCON                  \n"                                                          \
-                   "POP    TBLPAG                  \n"                                                          \
-                   "POP    RCOUNT                  \n" /* Restore the registers from the stack. */              \
-                   "POP    W14                     \n"                                                          \
-                   "POP.D  W12                     \n"                                                          \
-                   "POP.D  W10                     \n"                                                          \
-                   "POP.D  W8                      \n"                                                          \
-                   "POP.D  W6                      \n"                                                          \
-                   "POP.D  W4                      \n"                                                          \
-                   "POP.D  W2                      \n"                                                          \
-                   "POP.D  W0                      \n"                                                          \
-                   "POP    SR                        " );
-    #endif /* __HAS_EDS__ */
+        #define portRESTORE_CONTEXT()                                                                                       \
+            asm volatile(   "MOV    _pxCurrentTCB, W0       \n" /* Restore the stack pointer for the task. */               \
+                            "MOV    [W0], W15               \n"                                                             \
+                            "POP    W0                      \n" /* Restore the critical nesting counter for the task. */    \
+                            "MOV    W0, _uxCriticalNesting  \n"                                                             \
+                            "POP    PSVPAG                  \n"                                                             \
+                            "POP    CORCON                  \n"                                                             \
+                            "POP    TBLPAG                  \n"                                                             \
+                            "POP    RCOUNT                  \n" /* Restore the registers from the stack. */                 \
+                            "POP    W14                     \n"                                                             \
+                            "POP.D  W12                     \n"                                                             \
+                            "POP.D  W10                     \n"                                                             \
+                            "POP.D  W8                      \n"                                                             \
+                            "POP.D  W6                      \n"                                                             \
+                            "POP.D  W4                      \n"                                                             \
+                            "POP.D  W2                      \n"                                                             \
+                            "POP.D  W0                      \n"                                                             \
+                            "POP    SR                        " );
+        #endif /* __HAS_EDS__ */
 #endif /* defined( __PIC24E__ ) || defined ( __PIC24F__ ) || defined( __PIC24FK__ ) || defined( __PIC24H__ ) */
 
 #if defined( __dsPIC30F__ ) || defined( __dsPIC33F__ )
 
-    #define portRESTORE_CONTEXT()                                                                               \
-    asm volatile ( "MOV    _pxCurrentTCB, W0       \n" /* Restore the stack pointer for the task. */            \
-                   "MOV    [W0], W15               \n"                                                          \
-                   "POP    W0                      \n" /* Restore the critical nesting counter for the task. */ \
-                   "MOV    W0, _uxCriticalNesting  \n"                                                          \
-                   "POP    PSVPAG                  \n"                                                          \
-                   "POP    CORCON                  \n"                                                          \
-                   "POP    DOENDH                  \n"                                                          \
-                   "POP    DOENDL                  \n"                                                          \
-                   "POP    DOSTARTH                \n"                                                          \
-                   "POP    DOSTARTL                \n"                                                          \
-                   "POP    DCOUNT                  \n"                                                          \
-                   "POP    ACCBU                   \n"                                                          \
-                   "POP    ACCBH                   \n"                                                          \
-                   "POP    ACCBL                   \n"                                                          \
-                   "POP    ACCAU                   \n"                                                          \
-                   "POP    ACCAH                   \n"                                                          \
-                   "POP    ACCAL                   \n"                                                          \
-                   "POP    TBLPAG                  \n"                                                          \
-                   "POP    RCOUNT                  \n" /* Restore the registers from the stack. */              \
-                   "POP    W14                     \n"                                                          \
-                   "POP.D  W12                     \n"                                                          \
-                   "POP.D  W10                     \n"                                                          \
-                   "POP.D  W8                      \n"                                                          \
-                   "POP.D  W6                      \n"                                                          \
-                   "POP.D  W4                      \n"                                                          \
-                   "POP.D  W2                      \n"                                                          \
-                   "POP.D  W0                      \n"                                                          \
-                   "POP    SR                        " );
+    #define portRESTORE_CONTEXT()                                                                                       \
+        asm volatile(   "MOV    _pxCurrentTCB, W0       \n" /* Restore the stack pointer for the task. */               \
+                        "MOV    [W0], W15               \n"                                                             \
+                        "POP    W0                      \n" /* Restore the critical nesting counter for the task. */    \
+                        "MOV    W0, _uxCriticalNesting  \n"                                                             \
+                        "POP    PSVPAG                  \n"                                                             \
+                        "POP    CORCON                  \n"                                                             \
+                        "POP    DOENDH                  \n"                                                             \
+                        "POP    DOENDL                  \n"                                                             \
+                        "POP    DOSTARTH                \n"                                                             \
+                        "POP    DOSTARTL                \n"                                                             \
+                        "POP    DCOUNT                  \n"                                                             \
+                        "POP    ACCBU                   \n"                                                             \
+                        "POP    ACCBH                   \n"                                                             \
+                        "POP    ACCBL                   \n"                                                             \
+                        "POP    ACCAU                   \n"                                                             \
+                        "POP    ACCAH                   \n"                                                             \
+                        "POP    ACCAL                   \n"                                                             \
+                        "POP    TBLPAG                  \n"                                                             \
+                        "POP    RCOUNT                  \n" /* Restore the registers from the stack. */                 \
+                        "POP    W14                     \n"                                                             \
+                        "POP.D  W12                     \n"                                                             \
+                        "POP.D  W10                     \n"                                                             \
+                        "POP.D  W8                      \n"                                                             \
+                        "POP.D  W6                      \n"                                                             \
+                        "POP.D  W4                      \n"                                                             \
+                        "POP.D  W2                      \n"                                                             \
+                        "POP.D  W0                      \n"                                                             \
+                        "POP    SR                        " );
 
 #endif /* defined( __dsPIC30F__ ) || defined( __dsPIC33F__ ) */
 
 #ifndef portRESTORE_CONTEXT
     #error Unrecognised device selected
 
-/* Note:  dsPIC parts with EDS are not supported as there is no easy way to
- * recover the hardware stacked copies for DOCOUNT, DOHIGH, DOLOW. */
+    /* Note:  dsPIC parts with EDS are not supported as there is no easy way to
+    recover the hardware stacked copies for DOCOUNT, DOHIGH, DOLOW. */
 #endif
 
 /*
@@ -160,58 +160,56 @@ void vApplicationSetupTickTimerInterrupt( void );
 /*
  * See header file for description.
  */
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
 {
-    uint16_t usCode;
-    UBaseType_t i;
+uint16_t usCode;
+UBaseType_t i;
 
-    const StackType_t xInitialStack[] =
-    {
-        0x1111, /* W1 */
-        0x2222, /* W2 */
-        0x3333, /* W3 */
-        0x4444, /* W4 */
-        0x5555, /* W5 */
-        0x6666, /* W6 */
-        0x7777, /* W7 */
-        0x8888, /* W8 */
-        0x9999, /* W9 */
-        0xaaaa, /* W10 */
-        0xbbbb, /* W11 */
-        0xcccc, /* W12 */
-        0xdddd, /* W13 */
-        0xeeee, /* W14 */
-        0xcdce, /* RCOUNT */
-        0xabac, /* TBLPAG */
+const StackType_t xInitialStack[] =
+{
+    0x1111, /* W1 */
+    0x2222, /* W2 */
+    0x3333, /* W3 */
+    0x4444, /* W4 */
+    0x5555, /* W5 */
+    0x6666, /* W6 */
+    0x7777, /* W7 */
+    0x8888, /* W8 */
+    0x9999, /* W9 */
+    0xaaaa, /* W10 */
+    0xbbbb, /* W11 */
+    0xcccc, /* W12 */
+    0xdddd, /* W13 */
+    0xeeee, /* W14 */
+    0xcdce, /* RCOUNT */
+    0xabac, /* TBLPAG */
 
-        /* dsPIC specific registers. */
-        #if defined( __dsPIC30F__ ) || defined( __dsPIC33F__ )
-            0x0202, /* ACCAL */
-            0x0303, /* ACCAH */
-            0x0404, /* ACCAU */
-            0x0505, /* ACCBL */
-            0x0606, /* ACCBH */
-            0x0707, /* ACCBU */
-            0x0808, /* DCOUNT */
-            0x090a, /* DOSTARTL */
-            0x1010, /* DOSTARTH */
-            0x1110, /* DOENDL */
-            0x1212, /* DOENDH */
-        #endif /* if defined( __dsPIC30F__ ) || defined( __dsPIC33F__ ) */
-    };
+    /* dsPIC specific registers. */
+    #if defined( __dsPIC30F__ ) || defined( __dsPIC33F__ )
+        0x0202, /* ACCAL */
+        0x0303, /* ACCAH */
+        0x0404, /* ACCAU */
+        0x0505, /* ACCBL */
+        0x0606, /* ACCBH */
+        0x0707, /* ACCBU */
+        0x0808, /* DCOUNT */
+        0x090a, /* DOSTARTL */
+        0x1010, /* DOSTARTH */
+        0x1110, /* DOENDL */
+        0x1212, /* DOENDH */
+    #endif
+};
 
     /* Setup the stack as if a yield had occurred.
-     *
-     * Save the low bytes of the program counter. */
+
+    Save the low bytes of the program counter. */
     usCode = ( uint16_t ) pxCode;
     *pxTopOfStack = ( StackType_t ) usCode;
     pxTopOfStack++;
 
     /* Save the high byte of the program counter.  This will always be zero
-     * here as it is passed in a 16bit pointer.  If the address is greater than
-     * 16 bits then the pointer will point to a jump table. */
+    here as it is passed in a 16bit pointer.  If the address is greater than
+    16 bits then the pointer will point to a jump table. */
     *pxTopOfStack = ( StackType_t ) 0;
     pxTopOfStack++;
 
@@ -232,7 +230,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
     *pxTopOfStack = CORCON;
     pxTopOfStack++;
 
-    #if defined( __HAS_EDS__ )
+    #if defined(__HAS_EDS__)
         *pxTopOfStack = DSRPAG;
         pxTopOfStack++;
         *pxTopOfStack = DSWPAG;
@@ -269,7 +267,7 @@ BaseType_t xPortStartScheduler( void )
 void vPortEndScheduler( void )
 {
     /* Not implemented in ports where there is nothing to return to.
-     * Artificially force an assert. */
+    Artificially force an assert. */
     configASSERT( uxCriticalNesting == 1000UL );
 }
 /*-----------------------------------------------------------*/
@@ -277,9 +275,9 @@ void vPortEndScheduler( void )
 /*
  * Setup a timer for a regular tick.
  */
-__attribute__( ( weak ) ) void vApplicationSetupTickTimerInterrupt( void )
+__attribute__(( weak )) void vApplicationSetupTickTimerInterrupt( void )
 {
-    const uint32_t ulCompareMatch = ( ( configCPU_CLOCK_HZ / portTIMER_PRESCALE ) / configTICK_RATE_HZ ) - 1;
+const uint32_t ulCompareMatch = ( ( configCPU_CLOCK_HZ / portTIMER_PRESCALE ) / configTICK_RATE_HZ ) - 1;
 
     /* Prescale of 8. */
     T1CON = 0;
@@ -316,7 +314,6 @@ void vPortExitCritical( void )
 {
     configASSERT( uxCriticalNesting );
     uxCriticalNesting--;
-
     if( uxCriticalNesting == 0 )
     {
         portENABLE_INTERRUPTS();
@@ -324,7 +321,7 @@ void vPortExitCritical( void )
 }
 /*-----------------------------------------------------------*/
 
-void __attribute__( ( __interrupt__, auto_psv ) ) configTICK_INTERRUPT_HANDLER( void )
+void __attribute__((__interrupt__, auto_psv)) configTICK_INTERRUPT_HANDLER( void )
 {
     /* Clear the timer interrupt. */
     IFS0bits.T1IF = 0;
diff --git a/portable/MPLAB/PIC24_dsPIC/portmacro.h b/portable/MPLAB/PIC24_dsPIC/portmacro.h
index 7590d7c74..f01ee9c9b 100644
--- a/portable/MPLAB/PIC24_dsPIC/portmacro.h
+++ b/portable/MPLAB/PIC24_dsPIC/portmacro.h
@@ -46,63 +46,61 @@
  */
 
 /* Type definitions. */
-#define portCHAR                 char
-#define portFLOAT                float
-#define portDOUBLE               double
-#define portLONG                 long
-#define portSHORT                short
-#define portSTACK_TYPE           uint16_t
-#define portBASE_TYPE            short
-#define portPOINTER_SIZE_TYPE    size_t
-#define SIZE_MAX                 ( ( size_t ) -1 )
+#define portCHAR        char
+#define portFLOAT       float
+#define portDOUBLE      double
+#define portLONG        long
+#define portSHORT       short
+#define portSTACK_TYPE  uint16_t
+#define portBASE_TYPE   short
+#define portPOINTER_SIZE_TYPE size_t
+#define SIZE_MAX    ( ( size_t ) -1 )
 
-typedef portSTACK_TYPE   StackType_t;
-typedef short            BaseType_t;
-typedef unsigned short   UBaseType_t;
-
-#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t     TickType_t;
-    #define portMAX_DELAY              ( TickType_t ) 0xffff
+typedef portSTACK_TYPE StackType_t;
+typedef short BaseType_t;
+typedef unsigned short UBaseType_t;
 
+#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t TickType_t;
+    #define portMAX_DELAY ( TickType_t ) 0xffff
 /* 16-bit tick type on a 16-bit architecture, so reads of the tick count do
  * not need to be guarded with a critical section. */
-    #define portTICK_TYPE_IS_ATOMIC    1
-#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+    #define portTICK_TYPE_IS_ATOMIC 1
+#elif ( configTICK_TYPE_WIDTH_IN_BITS  == TICK_TYPE_WIDTH_32_BITS )
+    typedef uint32_t             TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffffffffUL
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portBYTE_ALIGNMENT    2
-#define portSTACK_GROWTH      1
-#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT          2
+#define portSTACK_GROWTH            1
+#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
 /*-----------------------------------------------------------*/
 
 /* Critical section management. */
 #define portDISABLE_INTERRUPTS()    SET_CPU_IPL( configKERNEL_INTERRUPT_PRIORITY ); __asm volatile ( "NOP" )
 #define portENABLE_INTERRUPTS()     SET_CPU_IPL( 0 )
 
-/* Note that exiting a critical section will set the IPL bits to 0, no
- *  matter what their value was prior to entering the critical section. */
+/* Note that exiting a critical sectino will set the IPL bits to 0, no matter
+what their value was prior to entering the critical section. */
 extern void vPortEnterCritical( void );
 extern void vPortExitCritical( void );
-#define portENTER_CRITICAL()    vPortEnterCritical()
-#define portEXIT_CRITICAL()     vPortExitCritical()
+#define portENTER_CRITICAL()        vPortEnterCritical()
+#define portEXIT_CRITICAL()         vPortExitCritical()
 /*-----------------------------------------------------------*/
 
 /* Task utilities. */
 extern void vPortYield( void );
-#define portYIELD()                                 \
-    asm volatile ( "CALL _vPortYield            \n" \
-                   "NOP                      " );
+#define portYIELD()             asm volatile ( "CALL _vPortYield            \n"     \
+                                                "NOP                      " );
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
 /*-----------------------------------------------------------*/
 
 /* Required by the kernel aware debugger. */
@@ -110,7 +108,7 @@ extern void vPortYield( void );
     #define portREMOVE_STATIC_QUALIFIER
 #endif
 
-#define portNOP()    asm volatile ( "NOP" )
+#define portNOP()               asm volatile ( "NOP" )
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/MPLAB/PIC32MEC14xx/ISR_Support.h b/portable/MPLAB/PIC32MEC14xx/ISR_Support.h
index eda3e13e7..d2fa5bb4d 100644
--- a/portable/MPLAB/PIC32MEC14xx/ISR_Support.h
+++ b/portable/MPLAB/PIC32MEC14xx/ISR_Support.h
@@ -28,187 +28,187 @@
 
 #include "FreeRTOSConfig.h"
 
-#define portCONTEXT_SIZE             132
-#define portEPC_STACK_LOCATION       124
-#define portSTATUS_STACK_LOCATION    128
+#define portCONTEXT_SIZE 132
+#define portEPC_STACK_LOCATION 124
+#define portSTATUS_STACK_LOCATION 128
 
 #ifdef __LANGUAGE_ASSEMBLY__
 
 /******************************************************************/
-    .macro portSAVE_CONTEXT
+.macro  portSAVE_CONTEXT
 
-/* Make room for the context. First save the current status so it can be
- * manipulated, and the cause and EPC registers so their original values are
- * captured. */
-    mfc0 k0, _CP0_CAUSE
-    addiu sp, sp, -portCONTEXT_SIZE
-    mfc0 k1, _CP0_STATUS
+    /* Make room for the context. First save the current status so it can be
+    manipulated, and the cause and EPC registers so their original values are
+    captured. */
+    mfc0    k0, _CP0_CAUSE
+    addiu   sp, sp, -portCONTEXT_SIZE
+    mfc0    k1, _CP0_STATUS
 
-/* Also save s6 and s5 so they can be used.  Any nesting interrupts should
- * maintain the values of these registers across the ISR. */
-    sw s6, 44 ( sp )
-    sw s5, 40 ( sp )
-    sw k1, portSTATUS_STACK_LOCATION( sp )
+    /* Also save s6 and s5 so they can be used.  Any nesting interrupts should
+    maintain the values of these registers across the ISR. */
+    sw      s6, 44(sp)
+    sw      s5, 40(sp)
+    sw      k1, portSTATUS_STACK_LOCATION(sp)
 
-/* Prepare to enable interrupts above the current priority.
- * k0 = k0 >> 10. Moves RIPL[17:10] to [7:0] */
-    srl k0, k0, 0xa
+    /* Prepare to enable interrupts above the current priority.
+    k0 = k0 >> 10. Moves RIPL[17:10] to [7:0] */
+    srl     k0, k0, 0xa
 
-/* Insert bit field. 7 bits k0[6:0] to k1[16:10] */
-    ins k1, k0, 10, 7
+    /* Insert bit field. 7 bits k0[6:0] to k1[16:10] */
+    ins     k1, k0, 10, 7
 
-/* Sets CP0.Status.IPL = CP0.Cause.RIPL
- * Copy the MSB of the IPL, but it would be an error if it was set anyway. */
-    srl k0, k0, 0x7
+    /* Sets CP0.Status.IPL = CP0.Cause.RIPL
+    Copy the MSB of the IPL, but it would be an error if it was set anyway. */
+    srl     k0, k0, 0x7
 
-/* MSB of IPL is bit[18] of CP0.Status */
-    ins k1, k0, 18, 1
+    /* MSB of IPL is bit[18] of CP0.Status */
+    ins     k1, k0, 18, 1
 
-/* CP0.Status[5:1] = 0 b[5]=Rsvd, b[4]=UM,
- * b[3]=Rsvd, b[2]=ERL, b[1]=EXL
- * Setting EXL=0 allows higher priority interrupts
- * to preempt this handler */
-    ins k1, zero, 1, 4
+    /* CP0.Status[5:1] = 0 b[5]=Rsvd, b[4]=UM,
+       b[3]=Rsvd, b[2]=ERL, b[1]=EXL
+       Setting EXL=0 allows higher priority interrupts
+       to preempt this handler */
+    ins     k1, zero, 1, 4
 
 
-/* s5 is used as the frame pointer. */
-    add s5, zero, sp
+    /* s5 is used as the frame pointer. */
+    add     s5, zero, sp
 
-/* Check the nesting count value. */
-    la k0, uxInterruptNesting
-    lw s6, ( k0 )
+    /* Check the nesting count value. */
+    la      k0, uxInterruptNesting
+    lw      s6, (k0)
 
-/* If the nesting count is 0 then swap to the the system stack, otherwise
- * the system stack is already being used. */
-    bne s6, zero, 1f
+    /* If the nesting count is 0 then swap to the the system stack, otherwise
+    the system stack is already being used. */
+    bne     s6, zero, 1f
     nop
 
-/* Swap to the system stack. */
-    la sp, xISRStackTop
-    lw sp, ( sp )
+    /* Swap to the system stack. */
+    la      sp, xISRStackTop
+    lw      sp, (sp)
 
-/* Increment and save the nesting count. */
-    1 :  addiu s6, s6, 1
-    sw s6, 0 ( k0 )
+    /* Increment and save the nesting count. */
+1:  addiu   s6, s6, 1
+    sw      s6, 0(k0)
 
-/* s6 holds the EPC value, this is saved after interrupts are re-enabled. */
-    mfc0 s6, _CP0_EPC
+    /* s6 holds the EPC value, this is saved after interrupts are re-enabled. */
+    mfc0    s6, _CP0_EPC
 
-/* Re-enable interrupts. */
-    mtc0 k1, _CP0_STATUS
+    /* Re-enable interrupts. */
+    mtc0    k1, _CP0_STATUS
 
-/* Save the context into the space just created.  s6 is saved again
- * here as it now contains the EPC value.  No other s registers need be
- * saved. */
-    sw ra, 120 ( s5 ) /* Return address (RA=R31) */
-    sw s8, 116 ( s5 ) /* Frame Pointer (FP=R30) */
-    sw t9, 112 ( s5 )
-    sw t8, 108 ( s5 )
-    sw t7, 104 ( s5 )
-    sw t6, 100 ( s5 )
-    sw t5, 96 ( s5 )
-    sw t4, 92 ( s5 )
-    sw t3, 88 ( s5 )
-    sw t2, 84 ( s5 )
-    sw t1, 80 ( s5 )
-    sw t0, 76 ( s5 )
-    sw a3, 72 ( s5 )
-    sw a2, 68 ( s5 )
-    sw a1, 64 ( s5 )
-    sw a0, 60 ( s5 )
-    sw v1, 56 ( s5 )
-    sw v0, 52 ( s5 )
-    sw s6, portEPC_STACK_LOCATION( s5 )
-    sw $1, 16 ( s5 )
+    /* Save the context into the space just created.  s6 is saved again
+    here as it now contains the EPC value.  No other s registers need be
+    saved. */
+    sw      ra, 120(s5) /* Return address (RA=R31) */
+    sw      s8, 116(s5) /* Frame Pointer (FP=R30) */
+    sw      t9, 112(s5)
+    sw      t8, 108(s5)
+    sw      t7, 104(s5)
+    sw      t6, 100(s5)
+    sw      t5, 96(s5)
+    sw      t4, 92(s5)
+    sw      t3, 88(s5)
+    sw      t2, 84(s5)
+    sw      t1, 80(s5)
+    sw      t0, 76(s5)
+    sw      a3, 72(s5)
+    sw      a2, 68(s5)
+    sw      a1, 64(s5)
+    sw      a0, 60(s5)
+    sw      v1, 56(s5)
+    sw      v0, 52(s5)
+    sw      s6, portEPC_STACK_LOCATION(s5)
+    sw      $1, 16(s5)
 
-/* MEC14xx does not have DSP, removed 7 words */
-    mfhi s6
-    sw s6, 12 ( s5 )
-    mflo s6
-    sw s6, 8 ( s5 )
+    /* MEC14xx does not have DSP, removed 7 words */
+    mfhi    s6
+    sw      s6, 12(s5)
+    mflo    s6
+    sw      s6, 8(s5)
 
-/* Update the task stack pointer value if nesting is zero. */
-    la s6, uxInterruptNesting
-    lw s6, ( s6 )
-    addiu s6, s6, -1
-    bne s6, zero, 1f
+    /* Update the task stack pointer value if nesting is zero. */
+    la      s6, uxInterruptNesting
+    lw      s6, (s6)
+    addiu   s6, s6, -1
+    bne     s6, zero, 1f
     nop
 
-/* Save the stack pointer. */
-    la s6, uxSavedTaskStackPointer
-    sw s5, ( s6 )
-    1 :
+    /* Save the stack pointer. */
+    la      s6, uxSavedTaskStackPointer
+    sw      s5, (s6)
+1:
     .endm
 
 /******************************************************************/
-       .macro portRESTORE_CONTEXT
+.macro  portRESTORE_CONTEXT
 
-/* Restore the stack pointer from the TCB.  This is only done if the
- * nesting count is 1. */
-    la s6, uxInterruptNesting
-    lw s6, ( s6 )
-    addiu s6, s6, -1
-    bne s6, zero, 1f
+    /* Restore the stack pointer from the TCB.  This is only done if the
+    nesting count is 1. */
+    la      s6, uxInterruptNesting
+    lw      s6, (s6)
+    addiu   s6, s6, -1
+    bne     s6, zero, 1f
     nop
-    la s6, uxSavedTaskStackPointer
-    lw s5, ( s6 )
+    la      s6, uxSavedTaskStackPointer
+    lw      s5, (s6)
 
-/* Restore the context.
- * MCHP MEC14xx does not include DSP */
-    1 :
-    lw s6, 8 ( s5 )
-    mtlo s6
-    lw s6, 12 ( s5 )
-    mthi s6
-    lw $1, 16 ( s5 )
+    /* Restore the context.
+    MCHP MEC14xx does not include DSP */
+1:
+    lw      s6, 8(s5)
+    mtlo    s6
+    lw      s6, 12(s5)
+    mthi    s6
+    lw      $1, 16(s5)
 
-/* s6 is loaded as it was used as a scratch register and therefore saved
- * as part of the interrupt context. */
-    lw s6, 44 ( s5 )
-    lw v0, 52 ( s5 )
-    lw v1, 56 ( s5 )
-    lw a0, 60 ( s5 )
-    lw a1, 64 ( s5 )
-    lw a2, 68 ( s5 )
-    lw a3, 72 ( s5 )
-    lw t0, 76 ( s5 )
-    lw t1, 80 ( s5 )
-    lw t2, 84 ( s5 )
-    lw t3, 88 ( s5 )
-    lw t4, 92 ( s5 )
-    lw t5, 96 ( s5 )
-    lw t6, 100 ( s5 )
-    lw t7, 104 ( s5 )
-    lw t8, 108 ( s5 )
-    lw t9, 112 ( s5 )
-    lw s8, 116 ( s5 )
-    lw ra, 120 ( s5 )
+    /* s6 is loaded as it was used as a scratch register and therefore saved
+    as part of the interrupt context. */
+    lw      s6, 44(s5)
+    lw      v0, 52(s5)
+    lw      v1, 56(s5)
+    lw      a0, 60(s5)
+    lw      a1, 64(s5)
+    lw      a2, 68(s5)
+    lw      a3, 72(s5)
+    lw      t0, 76(s5)
+    lw      t1, 80(s5)
+    lw      t2, 84(s5)
+    lw      t3, 88(s5)
+    lw      t4, 92(s5)
+    lw      t5, 96(s5)
+    lw      t6, 100(s5)
+    lw      t7, 104(s5)
+    lw      t8, 108(s5)
+    lw      t9, 112(s5)
+    lw      s8, 116(s5)
+    lw      ra, 120(s5)
 
-/* Protect access to the k registers, and others. */
+    /* Protect access to the k registers, and others. */
     di
     ehb
 
-/* Decrement the nesting count. */
-    la k0, uxInterruptNesting
-    lw k1, ( k0 )
-    addiu k1, k1, -1
-    sw k1, 0 ( k0 )
+    /* Decrement the nesting count. */
+    la      k0, uxInterruptNesting
+    lw      k1, (k0)
+    addiu   k1, k1, -1
+    sw      k1, 0(k0)
 
-    lw k0, portSTATUS_STACK_LOCATION( s5 )
-    lw k1, portEPC_STACK_LOCATION( s5 )
+    lw      k0, portSTATUS_STACK_LOCATION(s5)
+    lw      k1, portEPC_STACK_LOCATION(s5)
 
-/* Leave the stack in its original state.  First load sp from s5, then
- * restore s5 from the stack. */
-    add sp, zero, s5
-    lw s5, 40 ( sp )
-    addiu sp, sp, portCONTEXT_SIZE
+    /* Leave the stack in its original state.  First load sp from s5, then
+    restore s5 from the stack. */
+    add     sp, zero, s5
+    lw      s5, 40(sp)
+    addiu   sp, sp, portCONTEXT_SIZE
 
-    mtc0 k0, _CP0_STATUS
-    mtc0 k1, _CP0_EPC
+    mtc0    k0, _CP0_STATUS
+    mtc0    k1, _CP0_EPC
     ehb
     eret
     nop
 
-       .endm
+    .endm
 
 #endif /* #ifdef __LANGUAGE_ASSEMBLY__ */
diff --git a/portable/MPLAB/PIC32MEC14xx/port.c b/portable/MPLAB/PIC32MEC14xx/port.c
index 5eb6e567b..ebe9bdb7c 100644
--- a/portable/MPLAB/PIC32MEC14xx/port.c
+++ b/portable/MPLAB/PIC32MEC14xx/port.c
@@ -27,8 +27,8 @@
  */
 
 /*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the PIC32MEC14xx  port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the PIC32MEC14xx  port.
+ *----------------------------------------------------------*/
 
 /* Scheduler include files. */
 #include "FreeRTOS.h"
@@ -38,57 +38,57 @@
 #include <xc.h>
 #include <cp0defs.h>
 
-#if !defined( __MEC__ )
+#if !defined(__MEC__)
     #error This port is designed to work with XC32 on MEC14xx.  Please update your C compiler version or settings.
 #endif
 
-#if ( ( configMAX_SYSCALL_INTERRUPT_PRIORITY >= 0x7 ) || ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 ) )
+#if( ( configMAX_SYSCALL_INTERRUPT_PRIORITY >= 0x7 ) || ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 ) )
     #error configMAX_SYSCALL_INTERRUPT_PRIORITY must be less than 7 and greater than 0
 #endif
 
 /* Bits within various registers. */
-#define portIE_BIT                         ( 0x00000001 )
-#define portEXL_BIT                        ( 0x00000002 )
+#define portIE_BIT                  ( 0x00000001 )
+#define portEXL_BIT                 ( 0x00000002 )
 
 /* The EXL bit is set to ensure interrupts do not occur while the context of
- * the first task is being restored.  MEC14xx does not have DSP HW. */
-#define portINITIAL_SR                     ( portIE_BIT | portEXL_BIT )
+the first task is being restored.  MEC14xx does not have DSP HW. */
+#define portINITIAL_SR              ( portIE_BIT | portEXL_BIT )
 
 /* MEC14xx RTOS Timer MMCR's. */
-#define portMMCR_RTMR_PRELOAD              *( ( volatile uint32_t * ) ( 0xA0007404ul ) )
-#define portMMCR_RTMR_CONTROL              *( ( volatile uint32_t * ) ( 0xA0007408ul ) )
+#define portMMCR_RTMR_PRELOAD   *((volatile uint32_t *)(0xA0007404ul))
+#define portMMCR_RTMR_CONTROL   *((volatile uint32_t *)(0xA0007408ul))
 
 /* MEC14xx JTVIC external interrupt controller is mapped to M14K closely-coupled
- * peripheral space. */
-#define portGIRQ23_RTOS_TIMER_BITPOS       ( 4 )
-#define portGIRQ23_RTOS_TIMER_MASK         ( 1ul << ( portGIRQ23_RTOS_TIMER_BITPOS ) )
-#define portMMCR_JTVIC_GIRQ23_SRC          *( ( volatile uint32_t * ) ( 0xBFFFC0F0ul ) )
-#define portMMCR_JTVIC_GIRQ23_SETEN        *( ( volatile uint32_t * ) ( 0xBFFFC0F4ul ) )
-#define portMMCR_JTVIC_GIRQ23_PRIA         *( ( volatile uint32_t * ) ( 0xBFFFC3F0ul ) )
+peripheral space. */
+#define portGIRQ23_RTOS_TIMER_BITPOS    ( 4 )
+#define portGIRQ23_RTOS_TIMER_MASK      ( 1ul << ( portGIRQ23_RTOS_TIMER_BITPOS ) )
+#define portMMCR_JTVIC_GIRQ23_SRC       *((volatile uint32_t *)(0xBFFFC0F0ul))
+#define portMMCR_JTVIC_GIRQ23_SETEN     *((volatile uint32_t *)(0xBFFFC0F4ul))
+#define portMMCR_JTVIC_GIRQ23_PRIA      *((volatile uint32_t *)(0xBFFFC3F0ul))
 
 /* MIPS Software Interrupts are routed through JTVIC GIRQ24 */
-#define portGIRQ24_M14K_SOFTIRQ0_BITPOS    ( 1 )
-#define portGIRQ24_M14K_SOFTIRQ0_MASK      ( 1ul << ( portGIRQ24_M14K_SOFTIRQ0_BITPOS ) )
-#define portMMCR_JTVIC_GIRQ24_SRC          *( ( volatile uint32_t * ) ( 0xBFFFC100ul ) )
-#define portMMCR_JTVIC_GIRQ24_SETEN        *( ( volatile uint32_t * ) ( 0xBFFFC104ul ) )
-#define portMMCR_JTVIC_GIRQ24_PRIA         *( ( volatile uint32_t * ) ( 0xBFFFC400ul ) )
+#define portGIRQ24_M14K_SOFTIRQ0_BITPOS ( 1 )
+#define portGIRQ24_M14K_SOFTIRQ0_MASK   ( 1ul << ( portGIRQ24_M14K_SOFTIRQ0_BITPOS ) )
+#define portMMCR_JTVIC_GIRQ24_SRC       *((volatile uint32_t *)(0xBFFFC100ul))
+#define portMMCR_JTVIC_GIRQ24_SETEN     *((volatile uint32_t *)(0xBFFFC104ul))
+#define portMMCR_JTVIC_GIRQ24_PRIA      *((volatile uint32_t *)(0xBFFFC400ul))
 
 /*
- * By default port.c generates its tick interrupt from the RTOS timer.  The user
- * can override this behaviour by:
- *  1: Providing their own implementation of vApplicationSetupTickTimerInterrupt(),
- *     which is the function that configures the timer.  The function is defined
- *     as a weak symbol in this file so if the same function name is used in the
- *     application code then the version in the application code will be linked
- *     into the application in preference to the version defined in this file.
- *  2: Provide a vector implementation in port_asm.S that overrides the default
- *     behaviour for the specified interrupt vector.
- *  3: Specify the correct bit to clear the interrupt during the timer interrupt
- *     handler.
- */
+By default port.c generates its tick interrupt from the RTOS timer.  The user
+can override this behaviour by:
+    1: Providing their own implementation of vApplicationSetupTickTimerInterrupt(),
+       which is the function that configures the timer.  The function is defined
+       as a weak symbol in this file so if the same function name is used in the
+       application code then the version in the application code will be linked
+       into the application in preference to the version defined in this file.
+    2: Provide a vector implementation in port_asm.S that overrides the default
+       behaviour for the specified interrupt vector.
+    3: Specify the correct bit to clear the interrupt during the timer interrupt
+       handler.
+*/
 #ifndef configTICK_INTERRUPT_VECTOR
-    #define configTICK_INTERRUPT_VECTOR    girq23_b4
-    #define configCLEAR_TICK_TIMER_INTERRUPT()    portMMCR_JTVIC_GIRQ23_SRC = portGIRQ23_RTOS_TIMER_MASK
+    #define configTICK_INTERRUPT_VECTOR girq23_b4
+    #define configCLEAR_TICK_TIMER_INTERRUPT() portMMCR_JTVIC_GIRQ23_SRC = portGIRQ23_RTOS_TIMER_MASK
 #else
     #ifndef configCLEAR_TICK_TIMER_INTERRUPT
         #error If configTICK_INTERRUPT_VECTOR is defined in application code then configCLEAR_TICK_TIMER_INTERRUPT must also be defined in application code.
@@ -96,36 +96,34 @@
 #endif
 
 /* Let the user override the pre-loading of the initial RA with the address of
- * prvTaskExitError() in case it messes up unwinding of the stack in the debugger -
- * in which case configTASK_RETURN_ADDRESS can be defined as 0 (NULL). */
+prvTaskExitError() in case it messes up unwinding of the stack in the debugger -
+in which case configTASK_RETURN_ADDRESS can be defined as 0 (NULL). */
 #ifdef configTASK_RETURN_ADDRESS
-    #define portTASK_RETURN_ADDRESS    configTASK_RETURN_ADDRESS
+    #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
 #else
-    #define portTASK_RETURN_ADDRESS    prvTaskExitError
+    #define portTASK_RETURN_ADDRESS prvTaskExitError
 #endif
 
 /* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task
- * stack checking.  A problem in the ISR stack will trigger an assert, not call the
- * stack overflow hook function (because the stack overflow hook is specific to a
- * task stack, not the ISR stack). */
-#if ( configCHECK_FOR_STACK_OVERFLOW > 2 )
+stack checking.  A problem in the ISR stack will trigger an assert, not call the
+stack overflow hook function (because the stack overflow hook is specific to a
+task stack, not the ISR stack). */
+#if( configCHECK_FOR_STACK_OVERFLOW > 2 )
 
-/* Don't use 0xa5 as the stack fill bytes as that is used by the kernel for
- * the task stacks, and so will legitimately appear in many positions within
- * the ISR stack. */
-    #define portISR_STACK_FILL_BYTE    0xee
+    /* Don't use 0xa5 as the stack fill bytes as that is used by the kernel for
+    the task stacks, and so will legitimately appear in many positions within
+    the ISR stack. */
+    #define portISR_STACK_FILL_BYTE 0xee
 
-    static const uint8_t ucExpectedStackBytes[] =
-    {
-        portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
-        portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
-        portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
-        portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
-        portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE
-    }; \
+    static const uint8_t ucExpectedStackBytes[] = {
+                            portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,     \
+                            portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,     \
+                            portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,     \
+                            portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,     \
+                            portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE };   \
 
-    #define portCHECK_ISR_STACK()    configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
-#else /* if ( configCHECK_FOR_STACK_OVERFLOW > 2 ) */
+    #define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
+#else
     /* Define the function away. */
     #define portCHECK_ISR_STACK()
 #endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
@@ -141,7 +139,7 @@ static void prvTaskExitError( void );
 /*-----------------------------------------------------------*/
 
 /* Records the interrupt nesting depth.  This is initialised to one as it is
- * decremented to 0 when the first task starts. */
+decremented to 0 when the first task starts. */
 volatile UBaseType_t uxInterruptNesting = 0x01;
 
 /* Stores the task stack pointer when a switch is made to use the system stack. */
@@ -151,7 +149,7 @@ UBaseType_t uxSavedTaskStackPointer = 0;
 StackType_t xISRStack[ configISR_STACK_SIZE ] = { 0 };
 
 /* The top of stack value ensures there is enough space to store 6 registers on
- * the callers stack, as some functions seem to want to do this. */
+the callers stack, as some functions seem to want to do this. */
 const StackType_t * const xISRStackTop = &( xISRStack[ configISR_STACK_SIZE - 7 ] );
 
 /*-----------------------------------------------------------*/
@@ -159,32 +157,30 @@ const StackType_t * const xISRStackTop = &( xISRStack[ configISR_STACK_SIZE - 7
 /*
  * See header file for description.
  */
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
 {
     /* Ensure byte alignment is maintained when leaving this function. */
     pxTopOfStack--;
 
-    *pxTopOfStack = ( StackType_t ) 0xDEADBEEF;
+    *pxTopOfStack = (StackType_t) 0xDEADBEEF;
     pxTopOfStack--;
 
-    *pxTopOfStack = ( StackType_t ) 0x12345678; /* Word to which the stack pointer will be left pointing after context restore. */
+    *pxTopOfStack = (StackType_t) 0x12345678;   /* Word to which the stack pointer will be left pointing after context restore. */
     pxTopOfStack--;
 
-    *pxTopOfStack = ( StackType_t ) ulPortGetCP0Cause();
+    *pxTopOfStack = (StackType_t) ulPortGetCP0Cause();
     pxTopOfStack--;
 
-    *pxTopOfStack = ( StackType_t ) portINITIAL_SR; /* CP0_STATUS */
+    *pxTopOfStack = (StackType_t) portINITIAL_SR;   /* CP0_STATUS */
     pxTopOfStack--;
 
-    *pxTopOfStack = ( StackType_t ) pxCode; /* CP0_EPC */
+    *pxTopOfStack = (StackType_t) pxCode;       /* CP0_EPC */
     pxTopOfStack--;
 
-    *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* ra */
+    *pxTopOfStack = (StackType_t) portTASK_RETURN_ADDRESS;  /* ra */
     pxTopOfStack -= 15;
 
-    *pxTopOfStack = ( StackType_t ) pvParameters; /* Parameters to pass in. */
+    *pxTopOfStack = (StackType_t) pvParameters; /* Parameters to pass in. */
     pxTopOfStack -= 15;
 
     return pxTopOfStack;
@@ -193,10 +189,9 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
 
 static __inline uint32_t prvDisableInterrupt( void )
 {
-    uint32_t prev_state;
-
-    __asm volatile ( "di %0; ehb" : "=r" ( prev_state )::"memory" );
+uint32_t prev_state;
 
+    __asm volatile( "di %0; ehb" : "=r" ( prev_state ) :: "memory" );
     return prev_state;
 }
 /*-----------------------------------------------------------*/
@@ -204,17 +199,14 @@ static __inline uint32_t prvDisableInterrupt( void )
 static void prvTaskExitError( void )
 {
     /* A function that implements a task must not exit or attempt to return to
-     * its caller as there is nothing to return to.  If a task wants to exit it
-     * should instead call vTaskDelete( NULL ).
-     *
-     * Artificially force an assert() to be triggered if configASSERT() is
-     * defined, then stop here so application writers can catch the error. */
+    its caller as there is nothing to return to.  If a task wants to exit it
+    should instead call vTaskDelete( NULL ).
+
+    Artificially force an assert() to be triggered if configASSERT() is
+    defined, then stop here so application writers can catch the error. */
     configASSERT( uxSavedTaskStackPointer == 0UL );
     portDISABLE_INTERRUPTS();
-
-    for( ; ; )
-    {
-    }
+    for( ;; );
 }
 /*-----------------------------------------------------------*/
 
@@ -226,10 +218,10 @@ static void prvTaskExitError( void )
  * ensure the RTOS provided tick interrupt handler is installed on the correct
  * vector number.
  */
-__attribute__( ( weak ) ) void vApplicationSetupTickTimerInterrupt( void )
+__attribute__(( weak )) void vApplicationSetupTickTimerInterrupt( void )
 {
 /* MEC14xx RTOS Timer whose input clock is 32KHz. */
-    const uint32_t ulPreload = ( 32768ul / ( configTICK_RATE_HZ ) );
+const uint32_t ulPreload = ( 32768ul / ( configTICK_RATE_HZ ) );
 
     configASSERT( ulPreload != 0UL );
 
@@ -248,18 +240,18 @@ __attribute__( ( weak ) ) void vApplicationSetupTickTimerInterrupt( void )
 }
 /*-----------------------------------------------------------*/
 
-void vPortEndScheduler( void )
+void vPortEndScheduler(void)
 {
     /* Not implemented in ports where there is nothing to return to.
-     * Artificially force an assert. */
+    Artificially force an assert. */
     configASSERT( uxInterruptNesting == 1000UL );
 }
 /*-----------------------------------------------------------*/
 
 BaseType_t xPortStartScheduler( void )
 {
-    extern void vPortStartFirstTask( void );
-    extern void * pxCurrentTCB;
+extern void vPortStartFirstTask( void );
+extern void *pxCurrentTCB;
 
     #if ( configCHECK_FOR_STACK_OVERFLOW > 2 )
     {
@@ -269,29 +261,29 @@ BaseType_t xPortStartScheduler( void )
     #endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
 
     /* Clear the software interrupt flag. */
-    portMMCR_JTVIC_GIRQ24_SRC = ( portGIRQ24_M14K_SOFTIRQ0_MASK );
+    portMMCR_JTVIC_GIRQ24_SRC = (portGIRQ24_M14K_SOFTIRQ0_MASK);
 
     /* Set software timer priority.  Each GIRQn has one nibble containing its
-     * priority */
-    portMMCR_JTVIC_GIRQ24_PRIA &= ~( 0xF0ul );
+    priority */
+    portMMCR_JTVIC_GIRQ24_PRIA &= ~(0xF0ul);
     portMMCR_JTVIC_GIRQ24_PRIA |= ( portIPL_TO_CODE( configKERNEL_INTERRUPT_PRIORITY ) << 4 );
 
     /* Enable software interrupt. */
     portMMCR_JTVIC_GIRQ24_SETEN = ( portGIRQ24_M14K_SOFTIRQ0_MASK );
 
     /* Setup the timer to generate the tick.  Interrupts will have been disabled
-     * by the time we get here. */
+    by the time we get here. */
     vApplicationSetupTickTimerInterrupt();
 
     /* Start the highest priority task that has been created so far.  Its stack
-     * location is loaded into uxSavedTaskStackPointer. */
+    location is loaded into uxSavedTaskStackPointer. */
     uxSavedTaskStackPointer = *( UBaseType_t * ) pxCurrentTCB;
     vPortStartFirstTask();
 
     /* Should never get here as the tasks will now be executing!  Call the task
-     * exit error function to prevent compiler warnings about a static function
-     * not being called in the case that the application writer overrides this
-     * functionality by defining configTASK_RETURN_ADDRESS. */
+    exit error function to prevent compiler warnings about a static function
+    not being called in the case that the application writer overrides this
+    functionality by defining configTASK_RETURN_ADDRESS. */
     prvTaskExitError();
 
     return pdFALSE;
@@ -300,8 +292,8 @@ BaseType_t xPortStartScheduler( void )
 
 void vPortIncrementTick( void )
 {
-    UBaseType_t uxSavedStatus;
-    uint32_t ulCause;
+UBaseType_t uxSavedStatus;
+uint32_t ulCause;
 
     uxSavedStatus = uxPortSetInterruptMaskFromISR();
     {
@@ -325,17 +317,17 @@ void vPortIncrementTick( void )
 
 UBaseType_t uxPortSetInterruptMaskFromISR( void )
 {
-    UBaseType_t uxSavedStatusRegister;
+UBaseType_t uxSavedStatusRegister;
 
     prvDisableInterrupt();
     uxSavedStatusRegister = ulPortGetCP0Status() | 0x01;
 
     /* This clears the IPL bits, then sets them to
-     * configMAX_SYSCALL_INTERRUPT_PRIORITY.  This function should not be called
-     * from an interrupt that has a priority above
-     * configMAX_SYSCALL_INTERRUPT_PRIORITY so, when used correctly, the action
-     * can only result in the IPL being unchanged or raised, and therefore never
-     * lowered. */
+    configMAX_SYSCALL_INTERRUPT_PRIORITY.  This function should not be called
+    from an interrupt that has a priority above
+    configMAX_SYSCALL_INTERRUPT_PRIORITY so, when used correctly, the action
+    can only result in the IPL being unchanged or raised, and therefore never
+    lowered. */
     vPortSetCP0Status( ( ( uxSavedStatusRegister & ( ~portALL_IPL_BITS ) ) ) | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) );
 
     return uxSavedStatusRegister;
diff --git a/portable/MPLAB/PIC32MEC14xx/portmacro.h b/portable/MPLAB/PIC32MEC14xx/portmacro.h
index 2b1fb9fa6..d4d4f50dc 100644
--- a/portable/MPLAB/PIC32MEC14xx/portmacro.h
+++ b/portable/MPLAB/PIC32MEC14xx/portmacro.h
@@ -46,23 +46,23 @@
  */
 
 /* Type definitions. */
-#define portCHAR          char
-#define portFLOAT         float
-#define portDOUBLE        double
-#define portLONG          long
-#define portSHORT         short
-#define portSTACK_TYPE    uint32_t
-#define portBASE_TYPE     long
+#define portCHAR        char
+#define portFLOAT       float
+#define portDOUBLE      double
+#define portLONG        long
+#define portSHORT       short
+#define portSTACK_TYPE  uint32_t
+#define portBASE_TYPE   long
 
-typedef portSTACK_TYPE   StackType_t;
-typedef long             BaseType_t;
-typedef unsigned long    UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
 
-#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t     TickType_t;
-    #define portMAX_DELAY    ( TickType_t ) 0xffff
-#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t     TickType_t;
+#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t TickType_t;
+    #define portMAX_DELAY ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS  == TICK_TYPE_WIDTH_32_BITS )
+    typedef uint32_t             TickType_t;
     #define portMAX_DELAY    ( TickType_t ) 0xffffffffUL
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -70,16 +70,15 @@ typedef unsigned long    UBaseType_t;
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portBYTE_ALIGNMENT    8
-#define portSTACK_GROWTH      -1
-#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT  8
+#define portSTACK_GROWTH    -1
+#define portTICK_PERIOD_MS  ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
 /*-----------------------------------------------------------*/
 
 /* Critical section management. */
 #define portIPL_SHIFT       ( 10UL )
-
 /* Don't straddle the CEE bit.  Interrupts calling FreeRTOS functions should
- * never have higher IPL bits set anyway. */
+never have higher IPL bits set anyway. */
 #define portALL_IPL_BITS    ( 0x7FUL << portIPL_SHIFT )
 #define portSW0_BIT         ( 0x01 << 8 )
 
@@ -91,38 +90,38 @@ typedef unsigned long    UBaseType_t;
 
 static inline uint32_t ulPortGetCP0Status( void )
 {
-    uint32_t rv;
+uint32_t rv;
 
-    __asm volatile (
-        "\n\t"
-        "mfc0 %0,$12,0      \n\t"
-        : "=r" ( rv )::);
+    __asm volatile(
+            "\n\t"
+            "mfc0 %0,$12,0      \n\t"
+            : "=r" ( rv ) :: );
 
     return rv;
 }
 /*-----------------------------------------------------------*/
 
-static inline void vPortSetCP0Status( uint32_t new_status )
+static inline void vPortSetCP0Status( uint32_t new_status)
 {
     ( void ) new_status;
 
-    __asm__ __volatile__ (
-        "\n\t"
-        "mtc0 %0,$12,0      \n\t"
-        "ehb                \n\t"
-        :
-        : "r" ( new_status ) : );
+    __asm__ __volatile__(
+            "\n\t"
+            "mtc0 %0,$12,0      \n\t"
+            "ehb                \n\t"
+            :
+            :"r" ( new_status ) : );
 }
 /*-----------------------------------------------------------*/
 
 static inline uint32_t ulPortGetCP0Cause( void )
 {
-    uint32_t rv;
+uint32_t rv;
 
-    __asm volatile (
-        "\n\t"
-        "mfc0 %0,$13,0      \n\t"
-        : "=r" ( rv )::);
+    __asm volatile(
+            "\n\t"
+            "mfc0 %0,$13,0      \n\t"
+            : "=r" ( rv ) :: );
 
     return rv;
 }
@@ -132,86 +131,86 @@ static inline void vPortSetCP0Cause( uint32_t new_cause )
 {
     ( void ) new_cause;
 
-    __asm__ __volatile__ (
-        "\n\t"
-        "mtc0 %0,$13,0      \n\t"
-        "ehb                \n\t"
-        :
-        : "r" ( new_cause ) : );
+    __asm__ __volatile__(
+            "\n\t"
+            "mtc0 %0,$13,0      \n\t"
+            "ehb                \n\t"
+            :
+            :"r" ( new_cause ) : );
 }
 /*-----------------------------------------------------------*/
 
 /* This clears the IPL bits, then sets them to
- * configMAX_SYSCALL_INTERRUPT_PRIORITY.  An extra check is performed if
- * configASSERT() is defined to ensure an assertion handler does not inadvertently
- * attempt to lower the IPL when the call to assert was triggered because the IPL
- * value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY when an ISR
- * safe FreeRTOS API function was executed.  ISR safe FreeRTOS API functions are
- * those that end in FromISR.  FreeRTOS maintains a separate interrupt API to
- * ensure API function and interrupt entry is as fast and as simple as possible. */
+configMAX_SYSCALL_INTERRUPT_PRIORITY.  An extra check is performed if
+configASSERT() is defined to ensure an assertion handler does not inadvertently
+attempt to lower the IPL when the call to assert was triggered because the IPL
+value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY when an ISR
+safe FreeRTOS API function was executed.  ISR safe FreeRTOS API functions are
+those that end in FromISR.  FreeRTOS maintains a separate interrupt API to
+ensure API function and interrupt entry is as fast and as simple as possible. */
 #ifdef configASSERT
-    #define portDISABLE_INTERRUPTS()                                                                       \
-    {                                                                                                      \
-        uint32_t ulStatus;                                                                                 \
-        /* Mask interrupts at and below the kernel interrupt priority. */                                  \
-        ulStatus = ulPortGetCP0Status();                                                                   \
-        /* Is the current IPL below configMAX_SYSCALL_INTERRUPT_PRIORITY? */                               \
-        if( ( ( ulStatus & portALL_IPL_BITS ) >> portIPL_SHIFT ) < configMAX_SYSCALL_INTERRUPT_PRIORITY )  \
-        {                                                                                                  \
-            ulStatus &= ~portALL_IPL_BITS;                                                                 \
-            vPortSetCP0Status( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
-        }                                                                                                  \
+    #define portDISABLE_INTERRUPTS()                                                                            \
+    {                                                                                                           \
+    uint32_t ulStatus;                                                                                          \
+        /* Mask interrupts at and below the kernel interrupt priority. */                                       \
+        ulStatus = ulPortGetCP0Status();                                                                        \
+        /* Is the current IPL below configMAX_SYSCALL_INTERRUPT_PRIORITY? */                                    \
+        if( ( ( ulStatus & portALL_IPL_BITS ) >> portIPL_SHIFT ) < configMAX_SYSCALL_INTERRUPT_PRIORITY )       \
+        {                                                                                                       \
+            ulStatus &= ~portALL_IPL_BITS;                                                                      \
+            vPortSetCP0Status( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) );      \
+        }                                                                                                       \
     }
 #else /* configASSERT */
-    #define portDISABLE_INTERRUPTS()                                                                   \
-    {                                                                                                  \
-        uint32_t ulStatus;                                                                             \
-        /* Mask interrupts at and below the kernel interrupt priority. */                              \
-        ulStatus = ulPortGetCP0Status();                                                               \
-        ulStatus &= ~portALL_IPL_BITS;                                                                 \
-        vPortSetCP0Status( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
+    #define portDISABLE_INTERRUPTS()                                                                            \
+    {                                                                                                           \
+    uint32_t ulStatus;                                                                                          \
+        /* Mask interrupts at and below the kernel interrupt priority. */                                       \
+        ulStatus = ulPortGetCP0Status();                                                                        \
+        ulStatus &= ~portALL_IPL_BITS;                                                                          \
+        vPortSetCP0Status( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) );          \
     }
 #endif /* configASSERT */
 
-#define portENABLE_INTERRUPTS()          \
-    {                                    \
-        uint32_t ulStatus;               \
-        /* Unmask all interrupts. */     \
-        ulStatus = ulPortGetCP0Status(); \
-        ulStatus &= ~portALL_IPL_BITS;   \
-        vPortSetCP0Status( ulStatus );   \
-    }
+#define portENABLE_INTERRUPTS()             \
+{                                           \
+uint32_t ulStatus;                          \
+    /* Unmask all interrupts. */            \
+    ulStatus = ulPortGetCP0Status();        \
+    ulStatus &= ~portALL_IPL_BITS;          \
+    vPortSetCP0Status( ulStatus );          \
+}
 
 
 extern void vTaskEnterCritical( void );
 extern void vTaskExitCritical( void );
-#define portCRITICAL_NESTING_IN_TCB    1
-#define portENTER_CRITICAL()    vTaskEnterCritical()
-#define portEXIT_CRITICAL()     vTaskExitCritical()
+#define portCRITICAL_NESTING_IN_TCB 1
+#define portENTER_CRITICAL()        vTaskEnterCritical()
+#define portEXIT_CRITICAL()         vTaskExitCritical()
 
 extern UBaseType_t uxPortSetInterruptMaskFromISR();
 extern void vPortClearInterruptMaskFromISR( UBaseType_t );
-#define portSET_INTERRUPT_MASK_FROM_ISR()                             uxPortSetInterruptMaskFromISR()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister )    vPortClearInterruptMaskFromISR( uxSavedStatusRegister )
+#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMaskFromISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) vPortClearInterruptMaskFromISR( uxSavedStatusRegister )
 
 #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-    #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
+    #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
 #endif
 
 #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
 
-/* Check the configuration. */
-    #if ( configMAX_PRIORITIES > 32 )
+    /* Check the configuration. */
+    #if( configMAX_PRIORITIES > 32 )
         #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
     #endif
 
-/* Store/clear the ready priorities in a bit map. */
-    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+    /* Store/clear the ready priorities in a bit map. */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 
-/*-----------------------------------------------------------*/
+    /*-----------------------------------------------------------*/
 
-    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31 - _clz( ( uxReadyPriorities ) ) )
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - _clz( ( uxReadyPriorities ) ) )
 
 #endif /* taskRECORD_READY_PRIORITY */
 
@@ -219,25 +218,25 @@ extern void vPortClearInterruptMaskFromISR( UBaseType_t );
 
 /* Task utilities. */
 
-#define portYIELD()                       \
-    {                                     \
-        uint32_t ulCause;                 \
-        /* Trigger software interrupt. */ \
-        ulCause = ulPortGetCP0Cause();    \
-        ulCause |= portSW0_BIT;           \
-        vPortSetCP0Cause( ulCause );      \
-    }
+#define portYIELD()                         \
+{                                           \
+uint32_t ulCause;                           \
+    /* Trigger software interrupt. */       \
+    ulCause = ulPortGetCP0Cause();          \
+    ulCause |= portSW0_BIT;                 \
+    vPortSetCP0Cause( ulCause );            \
+}
 
 extern volatile UBaseType_t uxInterruptNesting;
-#define portASSERT_IF_IN_ISR()    configASSERT( uxInterruptNesting == 0 )
+#define portASSERT_IF_IN_ISR() configASSERT( uxInterruptNesting == 0 )
 
-#define portNOP()                 __asm volatile ( "nop" )
+#define portNOP() __asm volatile ( "nop" )
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters ) __attribute__( ( noreturn ) )
-#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn))
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
 /*-----------------------------------------------------------*/
 
 #define portEND_SWITCHING_ISR( xSwitchRequired ) \
diff --git a/portable/MPLAB/PIC32MX/ISR_Support.h b/portable/MPLAB/PIC32MX/ISR_Support.h
index 38c8d6a35..d594c7cc7 100644
--- a/portable/MPLAB/PIC32MX/ISR_Support.h
+++ b/portable/MPLAB/PIC32MX/ISR_Support.h
@@ -28,165 +28,164 @@
 
 #include "FreeRTOSConfig.h"
 
-#define portCONTEXT_SIZE             132
-#define portEPC_STACK_LOCATION       124
-#define portSTATUS_STACK_LOCATION    128
+#define portCONTEXT_SIZE 132
+#define portEPC_STACK_LOCATION  124
+#define portSTATUS_STACK_LOCATION 128
 
 /******************************************************************/
-.macro portSAVE_CONTEXT
+.macro  portSAVE_CONTEXT
 
-/* Make room for the context. First save the current status so it can be
- * manipulated, and the cause and EPC registers so their original values are
- * captured. */
-mfc0 k0, _CP0_CAUSE
-addiu sp, sp, -portCONTEXT_SIZE
-mfc0 k1, _CP0_STATUS
+    /* Make room for the context. First save the current status so it can be
+    manipulated, and the cause and EPC registers so their original values are
+    captured. */
+    mfc0        k0, _CP0_CAUSE
+    addiu       sp, sp, -portCONTEXT_SIZE
+    mfc0        k1, _CP0_STATUS
 
-/* Also save s6 and s5 so they can be used.  Any nesting interrupts should
- * maintain the values of these registers across the ISR. */
-sw s6, 44 ( sp )
-sw s5, 40 ( sp )
-sw k1, portSTATUS_STACK_LOCATION( sp )
+    /* Also save s6 and s5 so they can be used.  Any nesting interrupts should
+    maintain the values of these registers across the ISR. */
+    sw          s6, 44(sp)
+    sw          s5, 40(sp)
+    sw          k1, portSTATUS_STACK_LOCATION(sp)
 
-/* Prepare to enable interrupts above the current priority. */
-srl k0, k0, 0xa
-ins k1, k0, 10, 6
-ins k1, zero, 1, 4
+    /* Prepare to enable interrupts above the current priority. */
+    srl         k0, k0, 0xa
+    ins         k1, k0, 10, 6
+    ins         k1, zero, 1, 4
 
-/* s5 is used as the frame pointer. */
-add s5, zero, sp
+    /* s5 is used as the frame pointer. */
+    add         s5, zero, sp
 
-/* Check the nesting count value. */
-la k0, uxInterruptNesting
-lw s6, ( k0 )
+    /* Check the nesting count value. */
+    la          k0, uxInterruptNesting
+    lw          s6, (k0)
 
-/* If the nesting count is 0 then swap to the the system stack, otherwise
- * the system stack is already being used. */
-bne s6, zero, 1f
-nop
+    /* If the nesting count is 0 then swap to the the system stack, otherwise
+    the system stack is already being used. */
+    bne         s6, zero, 1f
+    nop
 
-/* Swap to the system stack. */
-la sp, xISRStackTop
-lw sp, ( sp )
+    /* Swap to the system stack. */
+    la          sp, xISRStackTop
+    lw          sp, (sp)
 
-/* Increment and save the nesting count. */
-1 :  addiu s6, s6, 1
-sw s6, 0 ( k0 )
+    /* Increment and save the nesting count. */
+1:  addiu       s6, s6, 1
+    sw          s6, 0(k0)
 
-/* s6 holds the EPC value, this is saved after interrupts are re-enabled. */
-mfc0 s6, _CP0_EPC
+    /* s6 holds the EPC value, this is saved after interrupts are re-enabled. */
+    mfc0        s6, _CP0_EPC
 
-/* Re-enable interrupts. */
-mtc0 k1, _CP0_STATUS
+    /* Re-enable interrupts. */
+    mtc0        k1, _CP0_STATUS
 
-/* Save the context into the space just created.  s6 is saved again
- * here as it now contains the EPC value.  No other s registers need be
- * saved. */
-sw ra, 120 ( s5 )
-sw s8, 116 ( s5 )
-sw t9, 112 ( s5 )
-sw t8, 108 ( s5 )
-sw t7, 104 ( s5 )
-sw t6, 100 ( s5 )
-sw t5, 96 ( s5 )
-sw t4, 92 ( s5 )
-sw t3, 88 ( s5 )
-sw t2, 84 ( s5 )
-sw t1, 80 ( s5 )
-sw t0, 76 ( s5 )
-sw a3, 72 ( s5 )
-sw a2, 68 ( s5 )
-sw a1, 64 ( s5 )
-sw a0, 60 ( s5 )
-sw v1, 56 ( s5 )
-sw v0, 52 ( s5 )
-sw s6, portEPC_STACK_LOCATION( s5 )
-sw $1, 16 ( s5 )
+    /* Save the context into the space just created.  s6 is saved again
+    here as it now contains the EPC value.  No other s registers need be
+    saved. */
+    sw          ra, 120(s5)
+    sw          s8, 116(s5)
+    sw          t9, 112(s5)
+    sw          t8, 108(s5)
+    sw          t7, 104(s5)
+    sw          t6, 100(s5)
+    sw          t5, 96(s5)
+    sw          t4, 92(s5)
+    sw          t3, 88(s5)
+    sw          t2, 84(s5)
+    sw          t1, 80(s5)
+    sw          t0, 76(s5)
+    sw          a3, 72(s5)
+    sw          a2, 68(s5)
+    sw          a1, 64(s5)
+    sw          a0, 60(s5)
+    sw          v1, 56(s5)
+    sw          v0, 52(s5)
+    sw          s6, portEPC_STACK_LOCATION(s5)
+    sw          $1, 16(s5)
 
-/* s6 is used as a scratch register. */
-mfhi s6
-sw s6, 12 ( s5 )
-mflo s6
-sw s6, 8 ( s5 )
+    /* s6 is used as a scratch register. */
+    mfhi        s6
+    sw          s6, 12(s5)
+    mflo        s6
+    sw          s6, 8(s5)
 
-/* Update the task stack pointer value if nesting is zero. */
-la s6, uxInterruptNesting
-lw s6, ( s6 )
-addiu s6, s6, -1
-bne s6, zero, 1f
-nop
+    /* Update the task stack pointer value if nesting is zero. */
+    la          s6, uxInterruptNesting
+    lw          s6, (s6)
+    addiu       s6, s6, -1
+    bne         s6, zero, 1f
+    nop
 
-/* Save the stack pointer. */
-la s6, uxSavedTaskStackPointer
-sw s5, ( s6 )
-1 :
-.endm
+    /* Save the stack pointer. */
+    la          s6, uxSavedTaskStackPointer
+    sw          s5, (s6)
+1:
+    .endm
 
 /******************************************************************/
-   .macro portRESTORE_CONTEXT
+.macro  portRESTORE_CONTEXT
 
-/* Restore the stack pointer from the TCB.  This is only done if the
- * nesting count is 1. */
-la s6, uxInterruptNesting
-lw s6, ( s6 )
-addiu s6, s6, -1
-bne s6, zero, 1f
-nop
-la s6, uxSavedTaskStackPointer
-lw s5, ( s6 )
+    /* Restore the stack pointer from the TCB.  This is only done if the
+    nesting count is 1. */
+    la          s6, uxInterruptNesting
+    lw          s6, (s6)
+    addiu       s6, s6, -1
+    bne         s6, zero, 1f
+    nop
+    la          s6, uxSavedTaskStackPointer
+    lw          s5, (s6)
 
-/* Restore the context. */
-1 :  lw s6, 8 ( s5 )
-mtlo s6
-lw s6, 12 ( s5 )
-mthi s6
-lw $1, 16 ( s5 )
+    /* Restore the context. */
+1:  lw          s6, 8(s5)
+    mtlo        s6
+    lw          s6, 12(s5)
+    mthi        s6
+    lw          $1, 16(s5)
+    /* s6 is loaded as it was used as a scratch register and therefore saved
+    as part of the interrupt context. */
+    lw          s6, 44(s5)
+    lw          v0, 52(s5)
+    lw          v1, 56(s5)
+    lw          a0, 60(s5)
+    lw          a1, 64(s5)
+    lw          a2, 68(s5)
+    lw          a3, 72(s5)
+    lw          t0, 76(s5)
+    lw          t1, 80(s5)
+    lw          t2, 84(s5)
+    lw          t3, 88(s5)
+    lw          t4, 92(s5)
+    lw          t5, 96(s5)
+    lw          t6, 100(s5)
+    lw          t7, 104(s5)
+    lw          t8, 108(s5)
+    lw          t9, 112(s5)
+    lw          s8, 116(s5)
+    lw          ra, 120(s5)
 
-/* s6 is loaded as it was used as a scratch register and therefore saved
- * as part of the interrupt context. */
-lw s6, 44 ( s5 )
-lw v0, 52 ( s5 )
-lw v1, 56 ( s5 )
-lw a0, 60 ( s5 )
-lw a1, 64 ( s5 )
-lw a2, 68 ( s5 )
-lw a3, 72 ( s5 )
-lw t0, 76 ( s5 )
-lw t1, 80 ( s5 )
-lw t2, 84 ( s5 )
-lw t3, 88 ( s5 )
-lw t4, 92 ( s5 )
-lw t5, 96 ( s5 )
-lw t6, 100 ( s5 )
-lw t7, 104 ( s5 )
-lw t8, 108 ( s5 )
-lw t9, 112 ( s5 )
-lw s8, 116 ( s5 )
-lw ra, 120 ( s5 )
+    /* Protect access to the k registers, and others. */
+    di
+    ehb
 
-/* Protect access to the k registers, and others. */
-di
-ehb
+    /* Decrement the nesting count. */
+    la          k0, uxInterruptNesting
+    lw          k1, (k0)
+    addiu       k1, k1, -1
+    sw          k1, 0(k0)
 
-/* Decrement the nesting count. */
-la k0, uxInterruptNesting
-lw k1, ( k0 )
-addiu k1, k1, -1
-sw k1, 0 ( k0 )
+    lw          k0, portSTATUS_STACK_LOCATION(s5)
+    lw          k1, portEPC_STACK_LOCATION(s5)
 
-lw k0, portSTATUS_STACK_LOCATION( s5 )
-lw k1, portEPC_STACK_LOCATION( s5 )
+    /* Leave the stack in its original state.  First load sp from s5, then
+    restore s5 from the stack. */
+    add         sp, zero, s5
+    lw          s5, 40(sp)
+    addiu       sp, sp, portCONTEXT_SIZE
 
-/* Leave the stack in its original state.  First load sp from s5, then
- * restore s5 from the stack. */
-add sp, zero, s5
-lw s5, 40 ( sp )
-addiu sp, sp, portCONTEXT_SIZE
+    mtc0        k0, _CP0_STATUS
+    mtc0        k1, _CP0_EPC
+    ehb
+    eret
+    nop
 
-mtc0 k0, _CP0_STATUS
-mtc0 k1, _CP0_EPC
-ehb
-eret
-nop
-
-   .endm
+    .endm
diff --git a/portable/MPLAB/PIC32MX/port.c b/portable/MPLAB/PIC32MX/port.c
index 6c71f7257..9f9140763 100644
--- a/portable/MPLAB/PIC32MX/port.c
+++ b/portable/MPLAB/PIC32MX/port.c
@@ -27,8 +27,8 @@
  */
 
 /*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the PIC32MX port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the PIC32MX port.
+  *----------------------------------------------------------*/
 
 #ifndef __XC
     #error This port is designed to work with XC32.  Please update your C compiler version.
@@ -39,41 +39,41 @@
 #include "task.h"
 
 /* Hardware specifics. */
-#define portTIMER_PRESCALE    8
-#define portPRESCALE_BITS     1
+#define portTIMER_PRESCALE  8
+#define portPRESCALE_BITS   1
 
 /* Bits within various registers. */
-#define portIE_BIT            ( 0x00000001 )
-#define portEXL_BIT           ( 0x00000002 )
+#define portIE_BIT                      ( 0x00000001 )
+#define portEXL_BIT                     ( 0x00000002 )
 
 /* Bits within the CAUSE register. */
-#define portCORE_SW_0         ( 0x00000100 )
-#define portCORE_SW_1         ( 0x00000200 )
+#define portCORE_SW_0                   ( 0x00000100 )
+#define portCORE_SW_1                   ( 0x00000200 )
 
 /* The EXL bit is set to ensure interrupts do not occur while the context of
- * the first task is being restored. */
-#define portINITIAL_SR        ( portIE_BIT | portEXL_BIT )
+the first task is being restored. */
+#define portINITIAL_SR                  ( portIE_BIT | portEXL_BIT )
 
 /*
- * By default port.c generates its tick interrupt from TIMER1.  The user can
- * override this behaviour by:
- *  1: Providing their own implementation of vApplicationSetupTickTimerInterrupt(),
- *     which is the function that configures the timer.  The function is defined
- *     as a weak symbol in this file so if the same function name is used in the
- *     application code then the version in the application code will be linked
- *     into the application in preference to the version defined in this file.
- *  2: Define configTICK_INTERRUPT_VECTOR to the vector number of the timer used
- *     to generate the tick interrupt.  For example, when timer 1 is used then
- *     configTICK_INTERRUPT_VECTOR is set to _TIMER_1_VECTOR.
- *     configTICK_INTERRUPT_VECTOR should be defined in FreeRTOSConfig.h.
- *  3: Define configCLEAR_TICK_TIMER_INTERRUPT() to clear the interrupt in the
- *     timer used to generate the tick interrupt.  For example, when timer 1 is
- *     used configCLEAR_TICK_TIMER_INTERRUPT() is defined to
- *     IFS0CLR = _IFS0_T1IF_MASK.
- */
+By default port.c generates its tick interrupt from TIMER1.  The user can
+override this behaviour by:
+    1: Providing their own implementation of vApplicationSetupTickTimerInterrupt(),
+       which is the function that configures the timer.  The function is defined
+       as a weak symbol in this file so if the same function name is used in the
+       application code then the version in the application code will be linked
+       into the application in preference to the version defined in this file.
+    2: Define configTICK_INTERRUPT_VECTOR to the vector number of the timer used
+       to generate the tick interrupt.  For example, when timer 1 is used then
+       configTICK_INTERRUPT_VECTOR is set to _TIMER_1_VECTOR.
+       configTICK_INTERRUPT_VECTOR should be defined in FreeRTOSConfig.h.
+    3: Define configCLEAR_TICK_TIMER_INTERRUPT() to clear the interrupt in the
+       timer used to generate the tick interrupt.  For example, when timer 1 is
+       used configCLEAR_TICK_TIMER_INTERRUPT() is defined to
+       IFS0CLR = _IFS0_T1IF_MASK.
+*/
 #ifndef configTICK_INTERRUPT_VECTOR
-    #define configTICK_INTERRUPT_VECTOR    _TIMER_1_VECTOR
-    #define configCLEAR_TICK_TIMER_INTERRUPT()    IFS0CLR = _IFS0_T1IF_MASK
+    #define configTICK_INTERRUPT_VECTOR _TIMER_1_VECTOR
+    #define configCLEAR_TICK_TIMER_INTERRUPT() IFS0CLR = _IFS0_T1IF_MASK
 #else
     #ifndef configCLEAR_TICK_TIMER_INTERRUPT
         #error If configTICK_INTERRUPT_VECTOR is defined in application code then configCLEAR_TICK_TIMER_INTERRUPT must also be defined in application code.
@@ -81,36 +81,34 @@
 #endif
 
 /* Let the user override the pre-loading of the initial RA with the address of
- * prvTaskExitError() in case it messes up unwinding of the stack in the
- * debugger - in which case configTASK_RETURN_ADDRESS can be defined as 0 (NULL). */
+prvTaskExitError() in case it messes up unwinding of the stack in the
+debugger - in which case configTASK_RETURN_ADDRESS can be defined as 0 (NULL). */
 #ifdef configTASK_RETURN_ADDRESS
-    #define portTASK_RETURN_ADDRESS    configTASK_RETURN_ADDRESS
+    #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
 #else
-    #define portTASK_RETURN_ADDRESS    prvTaskExitError
+    #define portTASK_RETURN_ADDRESS prvTaskExitError
 #endif
 
 /* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task
- * stack checking.  A problem in the ISR stack will trigger an assert, not call the
- * stack overflow hook function (because the stack overflow hook is specific to a
- * task stack, not the ISR stack). */
-#if ( configCHECK_FOR_STACK_OVERFLOW > 2 )
+stack checking.  A problem in the ISR stack will trigger an assert, not call the
+stack overflow hook function (because the stack overflow hook is specific to a
+task stack, not the ISR stack). */
+#if( configCHECK_FOR_STACK_OVERFLOW > 2 )
 
-/* Don't use 0xa5 as the stack fill bytes as that is used by the kernel for
- * the task stacks, and so will legitimately appear in many positions within
- * the ISR stack. */
-    #define portISR_STACK_FILL_BYTE    0xee
+    /* Don't use 0xa5 as the stack fill bytes as that is used by the kernel for
+    the task stacks, and so will legitimately appear in many positions within
+    the ISR stack. */
+    #define portISR_STACK_FILL_BYTE 0xee
 
-    static const uint8_t ucExpectedStackBytes[] =
-    {
-        portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
-        portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
-        portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
-        portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
-        portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE
-    }; \
+    static const uint8_t ucExpectedStackBytes[] = {
+                                    portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,     \
+                                    portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,     \
+                                    portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,     \
+                                    portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,     \
+                                    portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE };   \
 
-    #define portCHECK_ISR_STACK()    configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
-#else /* if ( configCHECK_FOR_STACK_OVERFLOW > 2 ) */
+    #define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
+#else
     /* Define the function away. */
     #define portCHECK_ISR_STACK()
 #endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
@@ -124,7 +122,7 @@
  * following line of code has no effect.  The interrupt priority is set by the
  * call to ConfigIntTimer1() in vApplicationSetupTickTimerInterrupt().
  */
-extern void __attribute__( ( interrupt( IPL1AUTO ), vector( configTICK_INTERRUPT_VECTOR ) ) ) vPortTickInterruptHandler( void );
+extern void __attribute__( (interrupt(IPL1AUTO), vector( configTICK_INTERRUPT_VECTOR ))) vPortTickInterruptHandler( void );
 
 /*
  * The software interrupt handler that performs the yield.  Note that, because
@@ -132,7 +130,7 @@ extern void __attribute__( ( interrupt( IPL1AUTO ), vector( configTICK_INTERRUPT
  * code has no effect.  The interrupt priority is set by the call to
  * mConfigIntCoreSW0() in xPortStartScheduler().
  */
-void __attribute__( ( interrupt( IPL1AUTO ), vector( _CORE_SOFTWARE_0_VECTOR ) ) ) vPortYieldISR( void );
+void __attribute__( (interrupt(IPL1AUTO), vector(_CORE_SOFTWARE_0_VECTOR))) vPortYieldISR( void );
 
 /*
  * Used to catch tasks that attempt to return from their implementing function.
@@ -142,17 +140,17 @@ static void prvTaskExitError( void );
 /*-----------------------------------------------------------*/
 
 /* Records the interrupt nesting depth.  This is initialised to one as it is
- * decremented to 0 when the first task starts. */
+decremented to 0 when the first task starts. */
 volatile UBaseType_t uxInterruptNesting = 0x01;
 
 /* Stores the task stack pointer when a switch is made to use the system stack. */
 UBaseType_t uxSavedTaskStackPointer = 0;
 
 /* The stack used by interrupt service routines that cause a context switch. */
-__attribute__( ( aligned( 8 ) ) ) StackType_t xISRStack[ configISR_STACK_SIZE ] = { 0 };
+__attribute__ ((aligned(8))) StackType_t xISRStack[ configISR_STACK_SIZE ] = { 0 };
 
 /* The top of stack value ensures there is enough space to store 6 registers on
- * the callers stack, as some functions seem to want to do this. */
+the callers stack, as some functions seem to want to do this. */
 const StackType_t * const xISRStackTop = &( xISRStack[ ( configISR_STACK_SIZE & ~portBYTE_ALIGNMENT_MASK ) - 8 ] );
 
 /*-----------------------------------------------------------*/
@@ -160,34 +158,32 @@ const StackType_t * const xISRStackTop = &( xISRStack[ ( configISR_STACK_SIZE &
 /*
  * See header file for description.
  */
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
 {
     /* Ensure 8 byte alignment is maintained when the context is popped from
      * stack. The size of the context is 33 words (132 bytes). */
     pxTopOfStack--;
     pxTopOfStack--;
 
-    *pxTopOfStack = ( StackType_t ) 0xDEADBEEF;
+    *pxTopOfStack = (StackType_t) 0xDEADBEEF;
     pxTopOfStack--;
 
-    *pxTopOfStack = ( StackType_t ) 0x12345678; /* Word to which the stack pointer will be left pointing after context restore. */
+    *pxTopOfStack = (StackType_t) 0x12345678;   /* Word to which the stack pointer will be left pointing after context restore. */
     pxTopOfStack--;
 
-    *pxTopOfStack = ( StackType_t ) _CP0_GET_CAUSE();
+    *pxTopOfStack = (StackType_t) _CP0_GET_CAUSE();
     pxTopOfStack--;
 
-    *pxTopOfStack = ( StackType_t ) portINITIAL_SR; /* CP0_STATUS */
+    *pxTopOfStack = (StackType_t) portINITIAL_SR;/* CP0_STATUS */
     pxTopOfStack--;
 
-    *pxTopOfStack = ( StackType_t ) pxCode; /* CP0_EPC */
+    *pxTopOfStack = (StackType_t) pxCode;       /* CP0_EPC */
     pxTopOfStack--;
 
-    *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* ra */
+    *pxTopOfStack = (StackType_t) portTASK_RETURN_ADDRESS;  /* ra */
     pxTopOfStack -= 15;
 
-    *pxTopOfStack = ( StackType_t ) pvParameters; /* Parameters to pass in. */
+    *pxTopOfStack = (StackType_t) pvParameters; /* Parameters to pass in. */
     pxTopOfStack -= 15;
 
     return pxTopOfStack;
@@ -197,17 +193,14 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
 static void prvTaskExitError( void )
 {
     /* A function that implements a task must not exit or attempt to return to
-     * its caller as there is nothing to return to.  If a task wants to exit it
-     * should instead call vTaskDelete( NULL ).
-     *
-     * Artificially force an assert() to be triggered if configASSERT() is
-     * defined, then stop here so application writers can catch the error. */
+    its caller as there is nothing to return to.  If a task wants to exit it
+    should instead call vTaskDelete( NULL ).
+
+    Artificially force an assert() to be triggered if configASSERT() is
+    defined, then stop here so application writers can catch the error. */
     configASSERT( uxSavedTaskStackPointer == 0UL );
     portDISABLE_INTERRUPTS();
-
-    for( ; ; )
-    {
-    }
+    for( ;; );
 }
 /*-----------------------------------------------------------*/
 
@@ -220,9 +213,9 @@ static void prvTaskExitError( void )
  * vector number.  When Timer 1 is used the vector number is defined as
  * _TIMER_1_VECTOR.
  */
-__attribute__( ( weak ) ) void vApplicationSetupTickTimerInterrupt( void )
+__attribute__(( weak )) void vApplicationSetupTickTimerInterrupt( void )
 {
-    const uint32_t ulCompareMatch = ( ( configPERIPHERAL_CLOCK_HZ / portTIMER_PRESCALE ) / configTICK_RATE_HZ ) - 1;
+const uint32_t ulCompareMatch = ( (configPERIPHERAL_CLOCK_HZ / portTIMER_PRESCALE) / configTICK_RATE_HZ ) - 1;
 
     T1CON = 0x0000;
     T1CONbits.TCKPS = portPRESCALE_BITS;
@@ -240,18 +233,18 @@ __attribute__( ( weak ) ) void vApplicationSetupTickTimerInterrupt( void )
 }
 /*-----------------------------------------------------------*/
 
-void vPortEndScheduler( void )
+void vPortEndScheduler(void)
 {
     /* Not implemented in ports where there is nothing to return to.
-     * Artificially force an assert. */
+    Artificially force an assert. */
     configASSERT( uxInterruptNesting == 1000UL );
 }
 /*-----------------------------------------------------------*/
 
 BaseType_t xPortStartScheduler( void )
 {
-    extern void vPortStartFirstTask( void );
-    extern void * pxCurrentTCB;
+extern void vPortStartFirstTask( void );
+extern void *pxCurrentTCB;
 
     #if ( configCHECK_FOR_STACK_OVERFLOW > 2 )
     {
@@ -272,18 +265,18 @@ BaseType_t xPortStartScheduler( void )
     IEC0SET = 1 << _IEC0_CS0IE_POSITION;
 
     /* Setup the timer to generate the tick.  Interrupts will have been
-     * disabled by the time we get here. */
+    disabled by the time we get here. */
     vApplicationSetupTickTimerInterrupt();
 
     /* Kick off the highest priority task that has been created so far.
-     * Its stack location is loaded into uxSavedTaskStackPointer. */
+    Its stack location is loaded into uxSavedTaskStackPointer. */
     uxSavedTaskStackPointer = *( UBaseType_t * ) pxCurrentTCB;
     vPortStartFirstTask();
 
     /* Should never get here as the tasks will now be executing!  Call the task
-     * exit error function to prevent compiler warnings about a static function
-     * not being called in the case that the application writer overrides this
-     * functionality by defining configTASK_RETURN_ADDRESS. */
+    exit error function to prevent compiler warnings about a static function
+    not being called in the case that the application writer overrides this
+    functionality by defining configTASK_RETURN_ADDRESS. */
     prvTaskExitError();
 
     return pdFALSE;
@@ -292,7 +285,7 @@ BaseType_t xPortStartScheduler( void )
 
 void vPortIncrementTick( void )
 {
-    UBaseType_t uxSavedStatus;
+UBaseType_t uxSavedStatus;
 
     uxSavedStatus = uxPortSetInterruptMaskFromISR();
     {
@@ -314,17 +307,16 @@ void vPortIncrementTick( void )
 
 UBaseType_t uxPortSetInterruptMaskFromISR( void )
 {
-    UBaseType_t uxSavedStatusRegister;
+UBaseType_t uxSavedStatusRegister;
 
     __builtin_disable_interrupts();
     uxSavedStatusRegister = _CP0_GET_STATUS() | 0x01;
-
     /* This clears the IPL bits, then sets them to
-     * configMAX_SYSCALL_INTERRUPT_PRIORITY.  This function should not be called
-     * from an interrupt that has a priority above
-     * configMAX_SYSCALL_INTERRUPT_PRIORITY so, when used correctly, the action
-     * can only result in the IPL being unchanged or raised, and therefore never
-     * lowered. */
+    configMAX_SYSCALL_INTERRUPT_PRIORITY.  This function should not be called
+    from an interrupt that has a priority above
+    configMAX_SYSCALL_INTERRUPT_PRIORITY so, when used correctly, the action
+    can only result in the IPL being unchanged or raised, and therefore never
+    lowered. */
     _CP0_SET_STATUS( ( ( uxSavedStatusRegister & ( ~portALL_IPL_BITS ) ) ) | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) );
 
     return uxSavedStatusRegister;
diff --git a/portable/MPLAB/PIC32MX/portmacro.h b/portable/MPLAB/PIC32MX/portmacro.h
index 89777d80b..b481165e6 100644
--- a/portable/MPLAB/PIC32MX/portmacro.h
+++ b/portable/MPLAB/PIC32MX/portmacro.h
@@ -49,119 +49,119 @@
  */
 
 /* Type definitions. */
-#define portCHAR          char
-#define portFLOAT         float
-#define portDOUBLE        double
-#define portLONG          long
-#define portSHORT         short
-#define portSTACK_TYPE    uint32_t
-#define portBASE_TYPE     long
+#define portCHAR        char
+#define portFLOAT       float
+#define portDOUBLE      double
+#define portLONG        long
+#define portSHORT       short
+#define portSTACK_TYPE  uint32_t
+#define portBASE_TYPE   long
 
-typedef portSTACK_TYPE   StackType_t;
-typedef long             BaseType_t;
-typedef unsigned long    UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
 
-#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t     TickType_t;
-    #define portMAX_DELAY              ( TickType_t ) 0xffff
+#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t TickType_t;
+    #define portMAX_DELAY ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t     TickType_t;
-    #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+    typedef uint32_t TickType_t;
+    #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
 
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
-    #define portTICK_TYPE_IS_ATOMIC    1
+    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+    not need to be guarded with a critical section. */
+    #define portTICK_TYPE_IS_ATOMIC 1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portBYTE_ALIGNMENT    8
-#define portSTACK_GROWTH      -1
-#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT          8
+#define portSTACK_GROWTH            -1
+#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
 /*-----------------------------------------------------------*/
 
 /* Critical section management. */
-#define portIPL_SHIFT       ( 10UL )
-#define portALL_IPL_BITS    ( 0x3fUL << portIPL_SHIFT )
-#define portSW0_BIT         ( 0x01 << 8 )
+#define portIPL_SHIFT               ( 10UL )
+#define portALL_IPL_BITS            ( 0x3fUL << portIPL_SHIFT )
+#define portSW0_BIT                 ( 0x01 << 8 )
 
 /* This clears the IPL bits, then sets them to
- * configMAX_SYSCALL_INTERRUPT_PRIORITY.  An extra check is performed if
- * configASSERT() is defined to ensure an assertion handler does not inadvertently
- * attempt to lower the IPL when the call to assert was triggered because the IPL
- * value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY when an ISR
- * safe FreeRTOS API function was executed.  ISR safe FreeRTOS API functions are
- * those that end in FromISR.  FreeRTOS maintains a separate interrupt API to
- * ensure API function and interrupt entry is as fast and as simple as possible. */
+configMAX_SYSCALL_INTERRUPT_PRIORITY.  An extra check is performed if
+configASSERT() is defined to ensure an assertion handler does not inadvertently
+attempt to lower the IPL when the call to assert was triggered because the IPL
+value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY when an ISR
+safe FreeRTOS API function was executed.  ISR safe FreeRTOS API functions are
+those that end in FromISR.  FreeRTOS maintains a separate interrupt API to
+ensure API function and interrupt entry is as fast and as simple as possible. */
 #ifdef configASSERT
-    #define portDISABLE_INTERRUPTS()                                                                      \
-    {                                                                                                     \
-        uint32_t ulStatus;                                                                                \
-                                                                                                          \
-        /* Mask interrupts at and below the kernel interrupt priority. */                                 \
-        ulStatus = _CP0_GET_STATUS();                                                                     \
-                                                                                                          \
-        /* Is the current IPL below configMAX_SYSCALL_INTERRUPT_PRIORITY? */                              \
+    #define portDISABLE_INTERRUPTS()                                            \
+    {                                                                           \
+    uint32_t ulStatus;                                                      \
+                                                                                \
+        /* Mask interrupts at and below the kernel interrupt priority. */       \
+        ulStatus = _CP0_GET_STATUS();                                           \
+                                                                                \
+        /* Is the current IPL below configMAX_SYSCALL_INTERRUPT_PRIORITY? */    \
         if( ( ( ulStatus & portALL_IPL_BITS ) >> portIPL_SHIFT ) < configMAX_SYSCALL_INTERRUPT_PRIORITY ) \
-        {                                                                                                 \
-            ulStatus &= ~portALL_IPL_BITS;                                                                \
-            _CP0_SET_STATUS( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) );  \
-        }                                                                                                 \
+        {                                                                       \
+            ulStatus &= ~portALL_IPL_BITS;                                      \
+            _CP0_SET_STATUS( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
+        }                                                                       \
     }
 #else /* configASSERT */
-    #define portDISABLE_INTERRUPTS()                                                                 \
-    {                                                                                                \
-        uint32_t ulStatus;                                                                           \
-                                                                                                     \
-        /* Mask interrupts at and below the kernel interrupt priority. */                            \
-        ulStatus = _CP0_GET_STATUS();                                                                \
-        ulStatus &= ~portALL_IPL_BITS;                                                               \
+    #define portDISABLE_INTERRUPTS()                                        \
+    {                                                                       \
+    uint32_t ulStatus;                                                  \
+                                                                            \
+        /* Mask interrupts at and below the kernel interrupt priority. */   \
+        ulStatus = _CP0_GET_STATUS();                                       \
+        ulStatus &= ~portALL_IPL_BITS;                                      \
         _CP0_SET_STATUS( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
     }
 #endif /* configASSERT */
 
-#define portENABLE_INTERRUPTS()        \
-    {                                  \
-        uint32_t ulStatus;             \
-                                       \
-        /* Unmask all interrupts. */   \
-        ulStatus = _CP0_GET_STATUS();  \
-        ulStatus &= ~portALL_IPL_BITS; \
-        _CP0_SET_STATUS( ulStatus );   \
-    }
+#define portENABLE_INTERRUPTS()                                         \
+{                                                                       \
+uint32_t ulStatus;                                                  \
+                                                                        \
+    /* Unmask all interrupts. */                                        \
+    ulStatus = _CP0_GET_STATUS();                                       \
+    ulStatus &= ~portALL_IPL_BITS;                                      \
+    _CP0_SET_STATUS( ulStatus );                                        \
+}
 
 
 extern void vTaskEnterCritical( void );
 extern void vTaskExitCritical( void );
-#define portCRITICAL_NESTING_IN_TCB    1
-#define portENTER_CRITICAL()    vTaskEnterCritical()
-#define portEXIT_CRITICAL()     vTaskExitCritical()
+#define portCRITICAL_NESTING_IN_TCB 1
+#define portENTER_CRITICAL()        vTaskEnterCritical()
+#define portEXIT_CRITICAL()         vTaskExitCritical()
 
 extern UBaseType_t uxPortSetInterruptMaskFromISR();
 extern void vPortClearInterruptMaskFromISR( UBaseType_t );
-#define portSET_INTERRUPT_MASK_FROM_ISR()                             uxPortSetInterruptMaskFromISR()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister )    vPortClearInterruptMaskFromISR( uxSavedStatusRegister )
+#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMaskFromISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) vPortClearInterruptMaskFromISR( uxSavedStatusRegister )
 
 #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-    #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
+    #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
 #endif
 
 #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
 
-/* Check the configuration. */
-    #if ( configMAX_PRIORITIES > 32 )
+    /* Check the configuration. */
+    #if( configMAX_PRIORITIES > 32 )
         #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
     #endif
 
-/* Store/clear the ready priorities in a bit map. */
-    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+    /* Store/clear the ready priorities in a bit map. */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 
-/*-----------------------------------------------------------*/
+    /*-----------------------------------------------------------*/
 
-    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - _clz( ( uxReadyPriorities ) ) )
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - _clz( ( uxReadyPriorities ) ) )
 
 #endif /* taskRECORD_READY_PRIORITY */
 
@@ -169,26 +169,26 @@ extern void vPortClearInterruptMaskFromISR( UBaseType_t );
 
 /* Task utilities. */
 
-#define portYIELD()                       \
-    {                                     \
-        uint32_t ulCause;                 \
-                                          \
-        /* Trigger software interrupt. */ \
-        ulCause = _CP0_GET_CAUSE();       \
-        ulCause |= portSW0_BIT;           \
-        _CP0_SET_CAUSE( ulCause );        \
-    }
+#define portYIELD()                             \
+{                                               \
+uint32_t ulCause;                           \
+                                                \
+    /* Trigger software interrupt. */           \
+    ulCause = _CP0_GET_CAUSE();                 \
+    ulCause |= portSW0_BIT;                     \
+    _CP0_SET_CAUSE( ulCause );                  \
+}
 
 extern volatile UBaseType_t uxInterruptNesting;
-#define portASSERT_IF_IN_ISR()    configASSERT( uxInterruptNesting == 0 )
+#define portASSERT_IF_IN_ISR() configASSERT( uxInterruptNesting == 0 )
 
-#define portNOP()                 __asm volatile ( "nop" )
+#define portNOP()   __asm volatile ( "nop" )
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters ) __attribute__( ( noreturn ) )
-#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn))
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
 /*-----------------------------------------------------------*/
 
 #define portEND_SWITCHING_ISR( xSwitchRequired ) \
diff --git a/portable/MPLAB/PIC32MZ/ISR_Support.h b/portable/MPLAB/PIC32MZ/ISR_Support.h
index 459ee2e3f..a9ddee0f4 100644
--- a/portable/MPLAB/PIC32MZ/ISR_Support.h
+++ b/portable/MPLAB/PIC32MZ/ISR_Support.h
@@ -28,406 +28,405 @@
 
 #include "FreeRTOSConfig.h"
 
-#define portCONTEXT_SIZE                   160
-#define portEPC_STACK_LOCATION             152
-#define portSTATUS_STACK_LOCATION          156
-#define portFPCSR_STACK_LOCATION           0
-#define portTASK_HAS_FPU_STACK_LOCATION    0
-#define portFPU_CONTEXT_SIZE               264
+#define portCONTEXT_SIZE                160
+#define portEPC_STACK_LOCATION          152
+#define portSTATUS_STACK_LOCATION       156
+#define portFPCSR_STACK_LOCATION        0
+#define portTASK_HAS_FPU_STACK_LOCATION     0
+#define portFPU_CONTEXT_SIZE            264
 
 /******************************************************************/
-.macro portSAVE_FPU_REGS offset, base
+.macro  portSAVE_FPU_REGS    offset, base
+    /* Macro to assist with saving just the FPU registers to the
+     * specified address and base offset,
+     * offset is a constant, base is the base pointer register  */
 
-/* Macro to assist with saving just the FPU registers to the
- * specified address and base offset,
- * offset is a constant, base is the base pointer register  */
+    sdc1        $f31, \offset + 248(\base)
+    sdc1        $f30, \offset + 240(\base)
+    sdc1        $f29, \offset + 232(\base)
+    sdc1        $f28, \offset + 224(\base)
+    sdc1        $f27, \offset + 216(\base)
+    sdc1        $f26, \offset + 208(\base)
+    sdc1        $f25, \offset + 200(\base)
+    sdc1        $f24, \offset + 192(\base)
+    sdc1        $f23, \offset + 184(\base)
+    sdc1        $f22, \offset + 176(\base)
+    sdc1        $f21, \offset + 168(\base)
+    sdc1        $f20, \offset + 160(\base)
+    sdc1        $f19, \offset + 152(\base)
+    sdc1        $f18, \offset + 144(\base)
+    sdc1        $f17, \offset + 136(\base)
+    sdc1        $f16, \offset + 128(\base)
+    sdc1        $f15, \offset + 120(\base)
+    sdc1        $f14, \offset + 112(\base)
+    sdc1        $f13, \offset + 104(\base)
+    sdc1        $f12, \offset + 96(\base)
+    sdc1        $f11, \offset + 88(\base)
+    sdc1        $f10, \offset + 80(\base)
+    sdc1        $f9, \offset + 72(\base)
+    sdc1        $f8, \offset + 64(\base)
+    sdc1        $f7, \offset + 56(\base)
+    sdc1        $f6, \offset + 48(\base)
+    sdc1        $f5, \offset + 40(\base)
+    sdc1        $f4, \offset + 32(\base)
+    sdc1        $f3, \offset + 24(\base)
+    sdc1        $f2, \offset + 16(\base)
+    sdc1        $f1, \offset + 8(\base)
+    sdc1        $f0, \offset + 0(\base)
 
-sdc1 $f31, \ offset + 248 ( \ base )
-sdc1 $f30, \ offset + 240 ( \ base )
-sdc1 $f29, \ offset + 232 ( \ base )
-sdc1 $f28, \ offset + 224 ( \ base )
-sdc1 $f27, \ offset + 216 ( \ base )
-sdc1 $f26, \ offset + 208 ( \ base )
-sdc1 $f25, \ offset + 200 ( \ base )
-sdc1 $f24, \ offset + 192 ( \ base )
-sdc1 $f23, \ offset + 184 ( \ base )
-sdc1 $f22, \ offset + 176 ( \ base )
-sdc1 $f21, \ offset + 168 ( \ base )
-sdc1 $f20, \ offset + 160 ( \ base )
-sdc1 $f19, \ offset + 152 ( \ base )
-sdc1 $f18, \ offset + 144 ( \ base )
-sdc1 $f17, \ offset + 136 ( \ base )
-sdc1 $f16, \ offset + 128 ( \ base )
-sdc1 $f15, \ offset + 120 ( \ base )
-sdc1 $f14, \ offset + 112 ( \ base )
-sdc1 $f13, \ offset + 104 ( \ base )
-sdc1 $f12, \ offset + 96 ( \ base )
-sdc1 $f11, \ offset + 88 ( \ base )
-sdc1 $f10, \ offset + 80 ( \ base )
-sdc1 $f9, \ offset + 72 ( \ base )
-sdc1 $f8, \ offset + 64 ( \ base )
-sdc1 $f7, \ offset + 56 ( \ base )
-sdc1 $f6, \ offset + 48 ( \ base )
-sdc1 $f5, \ offset + 40 ( \ base )
-sdc1 $f4, \ offset + 32 ( \ base )
-sdc1 $f3, \ offset + 24 ( \ base )
-sdc1 $f2, \ offset + 16 ( \ base )
-sdc1 $f1, \ offset + 8 ( \ base )
-sdc1 $f0, \ offset + 0 ( \ base )
-
-   .endm
+    .endm
 
 /******************************************************************/
-   .macro portLOAD_FPU_REGS offset, base
+.macro  portLOAD_FPU_REGS    offset, base
+    /* Macro to assist with loading just the FPU registers from the
+     * specified address and base offset, offset is a constant,
+     * base is the base pointer register  */
 
-/* Macro to assist with loading just the FPU registers from the
- * specified address and base offset, offset is a constant,
- * base is the base pointer register  */
+    ldc1        $f0, \offset + 0(\base)
+    ldc1        $f1, \offset + 8(\base)
+    ldc1        $f2, \offset + 16(\base)
+    ldc1        $f3, \offset + 24(\base)
+    ldc1        $f4, \offset + 32(\base)
+    ldc1        $f5, \offset + 40(\base)
+    ldc1        $f6, \offset + 48(\base)
+    ldc1        $f7, \offset + 56(\base)
+    ldc1        $f8, \offset + 64(\base)
+    ldc1        $f9, \offset + 72(\base)
+    ldc1        $f10, \offset + 80(\base)
+    ldc1        $f11, \offset + 88(\base)
+    ldc1        $f12, \offset + 96(\base)
+    ldc1        $f13, \offset + 104(\base)
+    ldc1        $f14, \offset + 112(\base)
+    ldc1        $f15, \offset + 120(\base)
+    ldc1        $f16, \offset + 128(\base)
+    ldc1        $f17, \offset + 136(\base)
+    ldc1        $f18, \offset + 144(\base)
+    ldc1        $f19, \offset + 152(\base)
+    ldc1        $f20, \offset + 160(\base)
+    ldc1        $f21, \offset + 168(\base)
+    ldc1        $f22, \offset + 176(\base)
+    ldc1        $f23, \offset + 184(\base)
+    ldc1        $f24, \offset + 192(\base)
+    ldc1        $f25, \offset + 200(\base)
+    ldc1        $f26, \offset + 208(\base)
+    ldc1        $f27, \offset + 216(\base)
+    ldc1        $f28, \offset + 224(\base)
+    ldc1        $f29, \offset + 232(\base)
+    ldc1        $f30, \offset + 240(\base)
+    ldc1        $f31, \offset + 248(\base)
 
-ldc1 $f0, \ offset + 0 ( \ base )
-ldc1 $f1, \ offset + 8 ( \ base )
-ldc1 $f2, \ offset + 16 ( \ base )
-ldc1 $f3, \ offset + 24 ( \ base )
-ldc1 $f4, \ offset + 32 ( \ base )
-ldc1 $f5, \ offset + 40 ( \ base )
-ldc1 $f6, \ offset + 48 ( \ base )
-ldc1 $f7, \ offset + 56 ( \ base )
-ldc1 $f8, \ offset + 64 ( \ base )
-ldc1 $f9, \ offset + 72 ( \ base )
-ldc1 $f10, \ offset + 80 ( \ base )
-ldc1 $f11, \ offset + 88 ( \ base )
-ldc1 $f12, \ offset + 96 ( \ base )
-ldc1 $f13, \ offset + 104 ( \ base )
-ldc1 $f14, \ offset + 112 ( \ base )
-ldc1 $f15, \ offset + 120 ( \ base )
-ldc1 $f16, \ offset + 128 ( \ base )
-ldc1 $f17, \ offset + 136 ( \ base )
-ldc1 $f18, \ offset + 144 ( \ base )
-ldc1 $f19, \ offset + 152 ( \ base )
-ldc1 $f20, \ offset + 160 ( \ base )
-ldc1 $f21, \ offset + 168 ( \ base )
-ldc1 $f22, \ offset + 176 ( \ base )
-ldc1 $f23, \ offset + 184 ( \ base )
-ldc1 $f24, \ offset + 192 ( \ base )
-ldc1 $f25, \ offset + 200 ( \ base )
-ldc1 $f26, \ offset + 208 ( \ base )
-ldc1 $f27, \ offset + 216 ( \ base )
-ldc1 $f28, \ offset + 224 ( \ base )
-ldc1 $f29, \ offset + 232 ( \ base )
-ldc1 $f30, \ offset + 240 ( \ base )
-ldc1 $f31, \ offset + 248 ( \ base )
-
-   .endm
+    .endm
 
 /******************************************************************/
-   .macro portSAVE_CONTEXT
+.macro  portSAVE_CONTEXT
 
-/* Make room for the context. First save the current status so it can be
- * manipulated, and the cause and EPC registers so their original values are
- * captured. */
-mfc0 k0, _CP0_CAUSE
-addiu sp, sp, -portCONTEXT_SIZE
+    /* Make room for the context. First save the current status so it can be
+    manipulated, and the cause and EPC registers so their original values are
+    captured. */
+    mfc0        k0, _CP0_CAUSE
+    addiu       sp, sp, -portCONTEXT_SIZE
 
-#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
+    #if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
+        /* Test if we are already using the system stack. Only tasks may use the
+        FPU so if we are already in a nested interrupt then the FPU context does
+        not require saving. */
+        la          k1, uxInterruptNesting
+        lw          k1, 0(k1)
+        bne         k1, zero, 2f
+        nop
 
-/* Test if we are already using the system stack. Only tasks may use the
- * FPU so if we are already in a nested interrupt then the FPU context does
- * not require saving. */
-    la k1, uxInterruptNesting
-    lw k1, 0 ( k1 )
-    bne k1, zero, 2f
+        /* Test if the current task needs the FPU context saving. */
+        la          k1, ulTaskHasFPUContext
+        lw          k1, 0(k1)
+        beq         k1, zero, 1f
+        nop
+
+        /* Adjust the stack to account for the additional FPU context.*/
+        addiu       sp, sp, -portFPU_CONTEXT_SIZE
+
+    1:
+        /* Save the ulTaskHasFPUContext flag. */
+        sw          k1, portTASK_HAS_FPU_STACK_LOCATION(sp)
+
+    2:
+    #endif
+
+    mfc0        k1, _CP0_STATUS
+
+    /* Also save s7, s6 and s5 so they can be used.  Any nesting interrupts
+    should maintain the values of these registers across the ISR. */
+    sw          s7, 48(sp)
+    sw          s6, 44(sp)
+    sw          s5, 40(sp)
+    sw          k1, portSTATUS_STACK_LOCATION(sp)
+
+    /* Prepare to enable interrupts above the current priority. */
+    srl         k0, k0, 0xa
+    ins         k1, k0, 10, 7
+    srl         k0, k0, 0x7 /* This copies the MSB of the IPL, but it would be an error if it was set anyway. */
+    ins         k1, k0, 18, 1
+    ins         k1, zero, 1, 4
+
+    /* s5 is used as the frame pointer. */
+    add         s5, zero, sp
+
+    /* Check the nesting count value. */
+    la          k0, uxInterruptNesting
+    lw          s6, (k0)
+
+    /* If the nesting count is 0 then swap to the the system stack, otherwise
+    the system stack is already being used. */
+    bne         s6, zero, 1f
     nop
 
-/* Test if the current task needs the FPU context saving. */
-    la k1, ulTaskHasFPUContext
-    lw k1, 0 ( k1 )
-    beq k1, zero, 1f
+    /* Swap to the system stack. */
+    la          sp, xISRStackTop
+    lw          sp, (sp)
+
+    /* Increment and save the nesting count. */
+1:  addiu       s6, s6, 1
+    sw          s6, 0(k0)
+
+    /* s6 holds the EPC value, this is saved after interrupts are re-enabled. */
+    mfc0        s6, _CP0_EPC
+
+    /* Re-enable interrupts. */
+    mtc0        k1, _CP0_STATUS
+
+    /* Save the context into the space just created.  s6 is saved again
+    here as it now contains the EPC value.  No other s registers need be
+    saved. */
+    sw          ra, 120(s5)
+    sw          s8, 116(s5)
+    sw          t9, 112(s5)
+    sw          t8, 108(s5)
+    sw          t7, 104(s5)
+    sw          t6, 100(s5)
+    sw          t5, 96(s5)
+    sw          t4, 92(s5)
+    sw          t3, 88(s5)
+    sw          t2, 84(s5)
+    sw          t1, 80(s5)
+    sw          t0, 76(s5)
+    sw          a3, 72(s5)
+    sw          a2, 68(s5)
+    sw          a1, 64(s5)
+    sw          a0, 60(s5)
+    sw          v1, 56(s5)
+    sw          v0, 52(s5)
+    sw          s6, portEPC_STACK_LOCATION(s5)
+    sw          $1, 16(s5)
+
+    /* Save the AC0, AC1, AC2, AC3 registers from the DSP.  s6 is used as a
+    scratch register. */
+    mfhi        s6, $ac1
+    sw          s6, 128(s5)
+    mflo        s6, $ac1
+    sw          s6, 124(s5)
+
+    mfhi        s6, $ac2
+    sw          s6, 136(s5)
+    mflo        s6, $ac2
+    sw          s6, 132(s5)
+
+    mfhi        s6, $ac3
+    sw          s6, 144(s5)
+    mflo        s6, $ac3
+    sw          s6, 140(s5)
+
+    /* Save the DSP Control register */
+    rddsp       s6
+    sw          s6, 148(s5)
+
+    /* ac0 is done separately to match the MX port. */
+    mfhi        s6, $ac0
+    sw          s6, 12(s5)
+    mflo        s6, $ac0
+    sw          s6, 8(s5)
+
+    /* Save the FPU context if the nesting count was zero. */
+    #if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
+        la          s6, uxInterruptNesting
+        lw          s6, 0(s6)
+        addiu       s6, s6, -1
+        bne         s6, zero, 1f
+        nop
+
+        /* Test if the current task needs the FPU context saving. */
+        lw          s6, portTASK_HAS_FPU_STACK_LOCATION(s5)
+        beq         s6, zero, 1f
+        nop
+
+        /* Save the FPU registers. */
+        portSAVE_FPU_REGS ( portCONTEXT_SIZE + 8 ), s5
+
+        /* Save the FPU status register */
+        cfc1        s6, $f31
+        sw          s6, (portCONTEXT_SIZE + portFPCSR_STACK_LOCATION)(s5)
+
+        1:
+    #endif
+
+    /* Update the task stack pointer value if nesting is zero. */
+    la          s6, uxInterruptNesting
+    lw          s6, (s6)
+    addiu       s6, s6, -1
+    bne         s6, zero, 1f
     nop
 
-/* Adjust the stack to account for the additional FPU context.*/
-    addiu sp, sp, -portFPU_CONTEXT_SIZE
-
-    1 :
-    /* Save the ulTaskHasFPUContext flag. */
-    sw k1, portTASK_HAS_FPU_STACK_LOCATION( sp )
-
-    2 :
-#endif /* if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) */
-
-mfc0 k1, _CP0_STATUS
-
-/* Also save s7, s6 and s5 so they can be used.  Any nesting interrupts
- * should maintain the values of these registers across the ISR. */
-sw s7, 48 ( sp )
-sw s6, 44 ( sp )
-sw s5, 40 ( sp )
-sw k1, portSTATUS_STACK_LOCATION( sp )
-
-/* Prepare to enable interrupts above the current priority. */
-srl k0, k0, 0xa
-ins k1, k0, 10, 7
-srl k0, k0, 0x7 /* This copies the MSB of the IPL, but it would be an error if it was set anyway. */
-ins k1, k0, 18, 1
-ins k1, zero, 1, 4
-
-/* s5 is used as the frame pointer. */
-add s5, zero, sp
-
-/* Check the nesting count value. */
-la k0, uxInterruptNesting
-lw s6, ( k0 )
-
-/* If the nesting count is 0 then swap to the the system stack, otherwise
- * the system stack is already being used. */
-bne s6, zero, 1f
-nop
-
-/* Swap to the system stack. */
-la sp, xISRStackTop
-lw sp, ( sp )
-
-/* Increment and save the nesting count. */
-1 :  addiu s6, s6, 1
-sw s6, 0 ( k0 )
-
-/* s6 holds the EPC value, this is saved after interrupts are re-enabled. */
-mfc0 s6, _CP0_EPC
-
-/* Re-enable interrupts. */
-mtc0 k1, _CP0_STATUS
-
-/* Save the context into the space just created.  s6 is saved again
- * here as it now contains the EPC value.  No other s registers need be
- * saved. */
-sw ra, 120 ( s5 )
-sw s8, 116 ( s5 )
-sw t9, 112 ( s5 )
-sw t8, 108 ( s5 )
-sw t7, 104 ( s5 )
-sw t6, 100 ( s5 )
-sw t5, 96 ( s5 )
-sw t4, 92 ( s5 )
-sw t3, 88 ( s5 )
-sw t2, 84 ( s5 )
-sw t1, 80 ( s5 )
-sw t0, 76 ( s5 )
-sw a3, 72 ( s5 )
-sw a2, 68 ( s5 )
-sw a1, 64 ( s5 )
-sw a0, 60 ( s5 )
-sw v1, 56 ( s5 )
-sw v0, 52 ( s5 )
-sw s6, portEPC_STACK_LOCATION( s5 )
-sw $1, 16 ( s5 )
-
-/* Save the AC0, AC1, AC2, AC3 registers from the DSP.  s6 is used as a
- * scratch register. */
-mfhi s6, $ac1
-sw s6, 128 ( s5 )
-mflo s6, $ac1
-sw s6, 124 ( s5 )
-
-mfhi s6, $ac2
-sw s6, 136 ( s5 )
-mflo s6, $ac2
-sw s6, 132 ( s5 )
-
-mfhi s6, $ac3
-sw s6, 144 ( s5 )
-mflo s6, $ac3
-sw s6, 140 ( s5 )
-
-/* Save the DSP Control register */
-rddsp s6
-sw s6, 148 ( s5 )
-
-/* ac0 is done separately to match the MX port. */
-mfhi s6, $ac0
-sw s6, 12 ( s5 )
-mflo s6, $ac0
-sw s6, 8 ( s5 )
-
-/* Save the FPU context if the nesting count was zero. */
-#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
-    la s6, uxInterruptNesting
-    lw s6, 0 ( s6 )
-    addiu s6, s6, -1
-    bne s6, zero, 1f
-    nop
-
-/* Test if the current task needs the FPU context saving. */
-    lw s6, portTASK_HAS_FPU_STACK_LOCATION( s5 )
-    beq s6, zero, 1f
-    nop
-    /* Save the FPU registers. */
-    portSAVE_FPU_REGS( portCONTEXT_SIZE + 8 ), s5
-
-/* Save the FPU status register */
-    cfc1 s6, $f31
-    sw s6, ( portCONTEXT_SIZE + portFPCSR_STACK_LOCATION )( s5 )
-
-    1 :
-#endif /* if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) */
-
-/* Update the task stack pointer value if nesting is zero. */
-la s6, uxInterruptNesting
-lw s6, ( s6 )
-addiu s6, s6, -1
-bne s6, zero, 1f
-nop
-
-/* Save the stack pointer. */
-la s6, uxSavedTaskStackPointer
-sw s5, ( s6 )
-1 :
-.endm
+    /* Save the stack pointer. */
+    la          s6, uxSavedTaskStackPointer
+    sw          s5, (s6)
+1:
+    .endm
 
 /******************************************************************/
-   .macro portRESTORE_CONTEXT
+.macro  portRESTORE_CONTEXT
 
-/* Restore the stack pointer from the TCB.  This is only done if the
- * nesting count is 1. */
-la s6, uxInterruptNesting
-lw s6, ( s6 )
-addiu s6, s6, -1
-bne s6, zero, 1f
-nop
-la s6, uxSavedTaskStackPointer
-lw s5, ( s6 )
-
-#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
-    /* Restore the FPU context if required. */
-    lw s6, portTASK_HAS_FPU_STACK_LOCATION( s5 )
-    beq s6, zero, 1f
+    /* Restore the stack pointer from the TCB.  This is only done if the
+    nesting count is 1. */
+    la          s6, uxInterruptNesting
+    lw          s6, (s6)
+    addiu       s6, s6, -1
+    bne         s6, zero, 1f
     nop
-    /* Restore the FPU registers. */
-    portLOAD_FPU_REGS( portCONTEXT_SIZE + 8 ), s5
+    la          s6, uxSavedTaskStackPointer
+    lw          s5, (s6)
 
-/* Restore the FPU status register. */
-    lw s6, ( portCONTEXT_SIZE + portFPCSR_STACK_LOCATION )( s5 )
-    ctc1 s6, $f31
-#endif /* if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) */
+    #if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
+        /* Restore the FPU context if required. */
+        lw          s6, portTASK_HAS_FPU_STACK_LOCATION(s5)
+        beq         s6, zero, 1f
+        nop
 
-1 :
+        /* Restore the FPU registers. */
+        portLOAD_FPU_REGS   ( portCONTEXT_SIZE + 8 ), s5
 
-/* Restore the context. */
-lw s6, 128 ( s5 )
-mthi s6, $ac1
-lw s6, 124 ( s5 )
-mtlo s6, $ac1
+        /* Restore the FPU status register. */
+        lw          s6, ( portCONTEXT_SIZE + portFPCSR_STACK_LOCATION )(s5)
+        ctc1        s6, $f31
+    #endif
 
-lw s6, 136 ( s5 )
-mthi s6, $ac2
-lw s6, 132 ( s5 )
-mtlo s6, $ac2
+1:
 
-lw s6, 144 ( s5 )
-mthi s6, $ac3
-lw s6, 140 ( s5 )
-mtlo s6, $ac3
+    /* Restore the context. */
+    lw          s6, 128(s5)
+    mthi        s6, $ac1
+    lw          s6, 124(s5)
+    mtlo        s6, $ac1
 
-/* Restore DSPControl. */
-lw s6, 148 ( s5 )
-wrdsp s6
+    lw          s6, 136(s5)
+    mthi        s6, $ac2
+    lw          s6, 132(s5)
+    mtlo        s6, $ac2
 
-lw s6, 8 ( s5 )
-mtlo s6, $ac0
-lw s6, 12 ( s5 )
-mthi s6, $ac0
-lw $1, 16 ( s5 )
+    lw          s6, 144(s5)
+    mthi        s6, $ac3
+    lw          s6, 140(s5)
+    mtlo        s6, $ac3
 
-/* s6 is loaded as it was used as a scratch register and therefore saved
- * as part of the interrupt context. */
-lw s7, 48 ( s5 )
-lw s6, 44 ( s5 )
-lw v0, 52 ( s5 )
-lw v1, 56 ( s5 )
-lw a0, 60 ( s5 )
-lw a1, 64 ( s5 )
-lw a2, 68 ( s5 )
-lw a3, 72 ( s5 )
-lw t0, 76 ( s5 )
-lw t1, 80 ( s5 )
-lw t2, 84 ( s5 )
-lw t3, 88 ( s5 )
-lw t4, 92 ( s5 )
-lw t5, 96 ( s5 )
-lw t6, 100 ( s5 )
-lw t7, 104 ( s5 )
-lw t8, 108 ( s5 )
-lw t9, 112 ( s5 )
-lw s8, 116 ( s5 )
-lw ra, 120 ( s5 )
+    /* Restore DSPControl. */
+    lw          s6, 148(s5)
+    wrdsp       s6
 
-/* Protect access to the k registers, and others. */
-di
-ehb
+    lw          s6, 8(s5)
+    mtlo        s6, $ac0
+    lw          s6, 12(s5)
+    mthi        s6, $ac0
+    lw          $1, 16(s5)
 
-/* Decrement the nesting count. */
-la k0, uxInterruptNesting
-lw k1, ( k0 )
-addiu k1, k1, -1
-sw k1, 0 ( k0 )
+    /* s6 is loaded as it was used as a scratch register and therefore saved
+    as part of the interrupt context. */
+    lw          s7, 48(s5)
+    lw          s6, 44(s5)
+    lw          v0, 52(s5)
+    lw          v1, 56(s5)
+    lw          a0, 60(s5)
+    lw          a1, 64(s5)
+    lw          a2, 68(s5)
+    lw          a3, 72(s5)
+    lw          t0, 76(s5)
+    lw          t1, 80(s5)
+    lw          t2, 84(s5)
+    lw          t3, 88(s5)
+    lw          t4, 92(s5)
+    lw          t5, 96(s5)
+    lw          t6, 100(s5)
+    lw          t7, 104(s5)
+    lw          t8, 108(s5)
+    lw          t9, 112(s5)
+    lw          s8, 116(s5)
+    lw          ra, 120(s5)
 
-#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
-    /* If the nesting count is now zero then the FPU context may be restored. */
-    bne k1, zero, 1f
+    /* Protect access to the k registers, and others. */
+    di
+    ehb
+
+    /* Decrement the nesting count. */
+    la          k0, uxInterruptNesting
+    lw          k1, (k0)
+    addiu       k1, k1, -1
+    sw          k1, 0(k0)
+
+    #if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
+        /* If the nesting count is now zero then the FPU context may be restored. */
+        bne         k1, zero, 1f
+        nop
+
+        /* Restore the value of ulTaskHasFPUContext */
+        la          k0, ulTaskHasFPUContext
+        lw          k1, 0(s5)
+        sw          k1, 0(k0)
+
+        /* If the task does not have an FPU context then adjust the stack normally. */
+        beq         k1, zero, 1f
+        nop
+
+        /* Restore the STATUS and EPC registers */
+        lw          k0, portSTATUS_STACK_LOCATION(s5)
+        lw          k1, portEPC_STACK_LOCATION(s5)
+
+        /* Leave the stack in its original state.  First load sp from s5, then
+        restore s5 from the stack. */
+        add         sp, zero, s5
+        lw          s5, 40(sp)
+
+        /* Adjust the stack pointer to remove the FPU context */
+        addiu       sp, sp, portFPU_CONTEXT_SIZE
+        beq         zero, zero, 2f
+        nop
+
+        1:  /* Restore the STATUS and EPC registers */
+        lw          k0, portSTATUS_STACK_LOCATION(s5)
+        lw          k1, portEPC_STACK_LOCATION(s5)
+
+        /* Leave the stack in its original state.  First load sp from s5, then
+        restore s5 from the stack. */
+        add         sp, zero, s5
+        lw          s5, 40(sp)
+
+        2:  /* Adjust the stack pointer */
+        addiu       sp, sp, portCONTEXT_SIZE
+
+    #else
+
+        /* Restore the frame when there is no hardware FP support. */
+        lw          k0, portSTATUS_STACK_LOCATION(s5)
+        lw          k1, portEPC_STACK_LOCATION(s5)
+
+        /* Leave the stack in its original state.  First load sp from s5, then
+        restore s5 from the stack. */
+        add         sp, zero, s5
+        lw          s5, 40(sp)
+
+        addiu       sp, sp, portCONTEXT_SIZE
+
+    #endif // ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
+
+    mtc0        k0, _CP0_STATUS
+    mtc0        k1, _CP0_EPC
+    ehb
+    eret
     nop
 
-/* Restore the value of ulTaskHasFPUContext */
-    la k0, ulTaskHasFPUContext
-    lw k1, 0 ( s5 )
-    sw k1, 0 ( k0 )
-
-/* If the task does not have an FPU context then adjust the stack normally. */
-    beq k1, zero, 1f
-    nop
-
-/* Restore the STATUS and EPC registers */
-    lw k0, portSTATUS_STACK_LOCATION( s5 )
-    lw k1, portEPC_STACK_LOCATION( s5 )
-
-/* Leave the stack in its original state.  First load sp from s5, then
- * restore s5 from the stack. */
-    add sp, zero, s5
-    lw s5, 40 ( sp )
-
-/* Adjust the stack pointer to remove the FPU context */
-    addiu sp, sp, portFPU_CONTEXT_SIZE
-    beq zero, zero, 2f
-    nop
-
-    1 : /* Restore the STATUS and EPC registers */
-    lw k0, portSTATUS_STACK_LOCATION( s5 )
-    lw k1, portEPC_STACK_LOCATION( s5 )
-
-/* Leave the stack in its original state.  First load sp from s5, then
- * restore s5 from the stack. */
-    add sp, zero, s5
-    lw s5, 40 ( sp )
-
-    2 : /* Adjust the stack pointer */
-    addiu sp, sp, portCONTEXT_SIZE
-
-#else /* if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) */
-
-/* Restore the frame when there is no hardware FP support. */
-    lw k0, portSTATUS_STACK_LOCATION( s5 )
-    lw k1, portEPC_STACK_LOCATION( s5 )
-
-/* Leave the stack in its original state.  First load sp from s5, then
- * restore s5 from the stack. */
-    add sp, zero, s5
-    lw s5, 40 ( sp )
-
-    addiu sp, sp, portCONTEXT_SIZE
-
-#endif // ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
-
-mtc0 k0, _CP0_STATUS
-mtc0 k1, _CP0_EPC
-ehb
-eret
-nop
-
-   .endm
+    .endm
diff --git a/portable/MPLAB/PIC32MZ/port.c b/portable/MPLAB/PIC32MZ/port.c
index dafbf1d94..b8b5708fe 100644
--- a/portable/MPLAB/PIC32MZ/port.c
+++ b/portable/MPLAB/PIC32MZ/port.c
@@ -27,8 +27,8 @@
  */
 
 /*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the PIC32MZ port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the PIC32MZ port.
+  *----------------------------------------------------------*/
 
 /* Microchip specific headers. */
 #include <xc.h>
@@ -40,62 +40,62 @@
 #include "FreeRTOS.h"
 #include "task.h"
 
-#if !defined( __PIC32MZ__ )
+#if !defined(__PIC32MZ__)
     #error This port is designed to work with XC32 on PIC32MZ MCUs.  Please update your C compiler version or settings.
 #endif
 
-#if ( ( configMAX_SYSCALL_INTERRUPT_PRIORITY >= 0x7 ) || ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 ) )
+#if( ( configMAX_SYSCALL_INTERRUPT_PRIORITY >= 0x7 ) || ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 ) )
     #error configMAX_SYSCALL_INTERRUPT_PRIORITY must be less than 7 and greater than 0
 #endif
 
 /* Hardware specifics. */
-#define portTIMER_PRESCALE    8
-#define portPRESCALE_BITS     1
+#define portTIMER_PRESCALE  8
+#define portPRESCALE_BITS   1
 
 /* Bits within various registers. */
-#define portIE_BIT            ( 0x00000001 )
-#define portEXL_BIT           ( 0x00000002 )
-#define portMX_BIT            ( 0x01000000 )       /* Allow access to DSP instructions. */
-#define portCU1_BIT           ( 0x20000000 )       /* enable CP1 for parts with hardware. */
-#define portFR_BIT            ( 0x04000000 )       /* Enable 64 bit floating point registers. */
+#define portIE_BIT                  ( 0x00000001 )
+#define portEXL_BIT                 ( 0x00000002 )
+#define portMX_BIT                  ( 0x01000000 ) /* Allow access to DSP instructions. */
+#define portCU1_BIT                 ( 0x20000000 ) /* enable CP1 for parts with hardware. */
+#define portFR_BIT                  ( 0x04000000 ) /* Enable 64 bit floating point registers. */
 
 /* Bits within the CAUSE register. */
-#define portCORE_SW_0         ( 0x00000100 )
-#define portCORE_SW_1         ( 0x00000200 )
+#define portCORE_SW_0               ( 0x00000100 )
+#define portCORE_SW_1               ( 0x00000200 )
 
 /* The EXL bit is set to ensure interrupts do not occur while the context of
- * the first task is being restored. */
+the first task is being restored. */
 #if ( __mips_hard_float == 1 )
-    #define portINITIAL_SR    ( portIE_BIT | portEXL_BIT | portMX_BIT | portFR_BIT | portCU1_BIT )
+    #define portINITIAL_SR          ( portIE_BIT | portEXL_BIT | portMX_BIT | portFR_BIT | portCU1_BIT )
 #else
-    #define portINITIAL_SR    ( portIE_BIT | portEXL_BIT | portMX_BIT )
+    #define portINITIAL_SR          ( portIE_BIT | portEXL_BIT | portMX_BIT )
 #endif
 
 /* The initial value to store into the FPU status and control register. This is
- * only used on parts that support a hardware FPU. */
-#define portINITIAL_FPSCR    ( 0x1000000 )      /* High perf on denormal ops */
+ only used on parts that support a hardware FPU. */
+#define portINITIAL_FPSCR           (0x1000000) /* High perf on denormal ops */
 
 
 /*
- * By default port.c generates its tick interrupt from TIMER1.  The user can
- * override this behaviour by:
- *  1: Providing their own implementation of vApplicationSetupTickTimerInterrupt(),
- *     which is the function that configures the timer.  The function is defined
- *     as a weak symbol in this file so if the same function name is used in the
- *     application code then the version in the application code will be linked
- *     into the application in preference to the version defined in this file.
- *  2: Define configTICK_INTERRUPT_VECTOR to the vector number of the timer used
- *     to generate the tick interrupt.  For example, when timer 1 is used then
- *     configTICK_INTERRUPT_VECTOR is set to _TIMER_1_VECTOR.
- *     configTICK_INTERRUPT_VECTOR should be defined in FreeRTOSConfig.h.
- *  3: Define configCLEAR_TICK_TIMER_INTERRUPT() to clear the interrupt in the
- *     timer used to generate the tick interrupt.  For example, when timer 1 is
- *     used configCLEAR_TICK_TIMER_INTERRUPT() is defined to
- *     IFS0CLR = _IFS0_T1IF_MASK.
- */
+By default port.c generates its tick interrupt from TIMER1.  The user can
+override this behaviour by:
+    1: Providing their own implementation of vApplicationSetupTickTimerInterrupt(),
+       which is the function that configures the timer.  The function is defined
+       as a weak symbol in this file so if the same function name is used in the
+       application code then the version in the application code will be linked
+       into the application in preference to the version defined in this file.
+    2: Define configTICK_INTERRUPT_VECTOR to the vector number of the timer used
+       to generate the tick interrupt.  For example, when timer 1 is used then
+       configTICK_INTERRUPT_VECTOR is set to _TIMER_1_VECTOR.
+       configTICK_INTERRUPT_VECTOR should be defined in FreeRTOSConfig.h.
+    3: Define configCLEAR_TICK_TIMER_INTERRUPT() to clear the interrupt in the
+       timer used to generate the tick interrupt.  For example, when timer 1 is
+       used configCLEAR_TICK_TIMER_INTERRUPT() is defined to
+       IFS0CLR = _IFS0_T1IF_MASK.
+*/
 #ifndef configTICK_INTERRUPT_VECTOR
-    #define configTICK_INTERRUPT_VECTOR    _TIMER_1_VECTOR
-    #define configCLEAR_TICK_TIMER_INTERRUPT()    IFS0CLR = _IFS0_T1IF_MASK
+    #define configTICK_INTERRUPT_VECTOR _TIMER_1_VECTOR
+    #define configCLEAR_TICK_TIMER_INTERRUPT() IFS0CLR = _IFS0_T1IF_MASK
 #else
     #ifndef configCLEAR_TICK_TIMER_INTERRUPT
         #error If configTICK_INTERRUPT_VECTOR is defined in application code then configCLEAR_TICK_TIMER_INTERRUPT must also be defined in application code.
@@ -103,36 +103,34 @@
 #endif
 
 /* Let the user override the pre-loading of the initial RA with the address of
- * prvTaskExitError() in case it messes up unwinding of the stack in the
- * debugger - in which case configTASK_RETURN_ADDRESS can be defined as 0 (NULL). */
+prvTaskExitError() in case it messes up unwinding of the stack in the
+debugger - in which case configTASK_RETURN_ADDRESS can be defined as 0 (NULL). */
 #ifdef configTASK_RETURN_ADDRESS
-    #define portTASK_RETURN_ADDRESS    configTASK_RETURN_ADDRESS
+    #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
 #else
-    #define portTASK_RETURN_ADDRESS    prvTaskExitError
+    #define portTASK_RETURN_ADDRESS prvTaskExitError
 #endif
 
 /* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task
- * stack checking.  A problem in the ISR stack will trigger an assert, not call the
- * stack overflow hook function (because the stack overflow hook is specific to a
- * task stack, not the ISR stack). */
-#if ( configCHECK_FOR_STACK_OVERFLOW > 2 )
+stack checking.  A problem in the ISR stack will trigger an assert, not call the
+stack overflow hook function (because the stack overflow hook is specific to a
+task stack, not the ISR stack). */
+#if( configCHECK_FOR_STACK_OVERFLOW > 2 )
 
-/* Don't use 0xa5 as the stack fill bytes as that is used by the kernel for
- * the task stacks, and so will legitimately appear in many positions within
- * the ISR stack. */
-    #define portISR_STACK_FILL_BYTE    0xee
+    /* Don't use 0xa5 as the stack fill bytes as that is used by the kernel for
+    the task stacks, and so will legitimately appear in many positions within
+    the ISR stack. */
+    #define portISR_STACK_FILL_BYTE 0xee
 
-    static const uint8_t ucExpectedStackBytes[] =
-    {
-        portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
-        portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
-        portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
-        portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
-        portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE
-    }; \
+    static const uint8_t ucExpectedStackBytes[] = {
+                                    portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,     \
+                                    portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,     \
+                                    portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,     \
+                                    portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,     \
+                                    portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE };   \
 
-    #define portCHECK_ISR_STACK()    configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
-#else /* if ( configCHECK_FOR_STACK_OVERFLOW > 2 ) */
+    #define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
+#else
     /* Define the function away. */
     #define portCHECK_ISR_STACK()
 #endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
@@ -147,23 +145,23 @@ static void prvTaskExitError( void );
 /*-----------------------------------------------------------*/
 
 /* Records the interrupt nesting depth.  This is initialised to one as it is
- * decremented to 0 when the first task starts. */
+decremented to 0 when the first task starts. */
 volatile UBaseType_t uxInterruptNesting = 0x01;
 
 /* Stores the task stack pointer when a switch is made to use the system stack. */
 UBaseType_t uxSavedTaskStackPointer = 0;
 
 /* The stack used by interrupt service routines that cause a context switch. */
-__attribute__( ( aligned( 8 ) ) ) StackType_t xISRStack[ configISR_STACK_SIZE ] = { 0 };
+__attribute__ ((aligned(8))) StackType_t xISRStack[ configISR_STACK_SIZE ] = { 0 };
 
 /* The top of stack value ensures there is enough space to store 6 registers on
- * the callers stack, as some functions seem to want to do this.  8 byte alignment
- * is required to allow double word floating point stack pushes generated by the
- * compiler. */
+the callers stack, as some functions seem to want to do this.  8 byte alignment
+is required to allow double word floating point stack pushes generated by the
+compiler. */
 const StackType_t * const xISRStackTop = &( xISRStack[ ( configISR_STACK_SIZE & ~portBYTE_ALIGNMENT_MASK ) - 8 ] );
 
 /* Saved as part of the task context. Set to pdFALSE if the task does not
- * require an FPU context. */
+ require an FPU context. */
 #if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
     uint32_t ulTaskHasFPUContext = 0;
 #endif
@@ -173,39 +171,37 @@ const StackType_t * const xISRStackTop = &( xISRStack[ ( configISR_STACK_SIZE &
 /*
  * See header file for description.
  */
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
 {
     /* Ensure 8 byte alignment is maintained when leaving this function. */
     pxTopOfStack--;
     pxTopOfStack--;
 
-    *pxTopOfStack = ( StackType_t ) 0xDEADBEEF;
+    *pxTopOfStack = (StackType_t) 0xDEADBEEF;
     pxTopOfStack--;
 
-    *pxTopOfStack = ( StackType_t ) 0x12345678; /* Word to which the stack pointer will be left pointing after context restore. */
+    *pxTopOfStack = (StackType_t) 0x12345678;   /* Word to which the stack pointer will be left pointing after context restore. */
     pxTopOfStack--;
 
-    *pxTopOfStack = ( StackType_t ) _CP0_GET_CAUSE();
+    *pxTopOfStack = (StackType_t) _CP0_GET_CAUSE();
     pxTopOfStack--;
 
-    *pxTopOfStack = ( StackType_t ) portINITIAL_SR; /* CP0_STATUS */
+    *pxTopOfStack = (StackType_t) portINITIAL_SR;/* CP0_STATUS */
     pxTopOfStack--;
 
-    *pxTopOfStack = ( StackType_t ) pxCode; /* CP0_EPC */
+    *pxTopOfStack = (StackType_t) pxCode;       /* CP0_EPC */
     pxTopOfStack--;
 
-    *pxTopOfStack = ( StackType_t ) 0x00000000;              /* DSPControl */
-    pxTopOfStack -= 7;                                       /* Includes space for AC1 - AC3. */
+    *pxTopOfStack = (StackType_t) 0x00000000;   /* DSPControl */
+    pxTopOfStack -= 7;                          /* Includes space for AC1 - AC3. */
 
-    *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* ra */
+    *pxTopOfStack = (StackType_t) portTASK_RETURN_ADDRESS;  /* ra */
     pxTopOfStack -= 15;
 
-    *pxTopOfStack = ( StackType_t ) pvParameters; /* Parameters to pass in. */
+    *pxTopOfStack = (StackType_t) pvParameters; /* Parameters to pass in. */
     pxTopOfStack -= 15;
 
-    *pxTopOfStack = ( StackType_t ) pdFALSE; /*by default disable FPU context save on parts with FPU */
+    *pxTopOfStack = (StackType_t) pdFALSE; /*by default disable FPU context save on parts with FPU */
 
     return pxTopOfStack;
 }
@@ -214,17 +210,14 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
 static void prvTaskExitError( void )
 {
     /* A function that implements a task must not exit or attempt to return to
-     * its caller as there is nothing to return to.  If a task wants to exit it
-     * should instead call vTaskDelete( NULL ).
-     *
-     * Artificially force an assert() to be triggered if configASSERT() is
-     * defined, then stop here so application writers can catch the error. */
+    its caller as there is nothing to return to.  If a task wants to exit it
+    should instead call vTaskDelete( NULL ).
+
+    Artificially force an assert() to be triggered if configASSERT() is
+    defined, then stop here so application writers can catch the error. */
     configASSERT( uxSavedTaskStackPointer == 0UL );
     portDISABLE_INTERRUPTS();
-
-    for( ; ; )
-    {
-    }
+    for( ;; );
 }
 /*-----------------------------------------------------------*/
 
@@ -237,9 +230,9 @@ static void prvTaskExitError( void )
  * vector number.  When Timer 1 is used the vector number is defined as
  * _TIMER_1_VECTOR.
  */
-__attribute__( ( weak ) ) void vApplicationSetupTickTimerInterrupt( void )
+__attribute__(( weak )) void vApplicationSetupTickTimerInterrupt( void )
 {
-    const uint32_t ulCompareMatch = ( ( configPERIPHERAL_CLOCK_HZ / portTIMER_PRESCALE ) / configTICK_RATE_HZ ) - 1UL;
+const uint32_t ulCompareMatch = ( (configPERIPHERAL_CLOCK_HZ / portTIMER_PRESCALE) / configTICK_RATE_HZ ) - 1UL;
 
     T1CON = 0x0000;
     T1CONbits.TCKPS = portPRESCALE_BITS;
@@ -257,18 +250,18 @@ __attribute__( ( weak ) ) void vApplicationSetupTickTimerInterrupt( void )
 }
 /*-----------------------------------------------------------*/
 
-void vPortEndScheduler( void )
+void vPortEndScheduler(void)
 {
     /* Not implemented in ports where there is nothing to return to.
-     * Artificially force an assert. */
+    Artificially force an assert. */
     configASSERT( uxInterruptNesting == 1000UL );
 }
 /*-----------------------------------------------------------*/
 
 BaseType_t xPortStartScheduler( void )
 {
-    extern void vPortStartFirstTask( void );
-    extern void * pxCurrentTCB;
+extern void vPortStartFirstTask( void );
+extern void *pxCurrentTCB;
 
     #if ( configCHECK_FOR_STACK_OVERFLOW > 2 )
     {
@@ -289,18 +282,18 @@ BaseType_t xPortStartScheduler( void )
     IEC0SET = 1 << _IEC0_CS0IE_POSITION;
 
     /* Setup the timer to generate the tick.  Interrupts will have been
-     * disabled by the time we get here. */
+    disabled by the time we get here. */
     vApplicationSetupTickTimerInterrupt();
 
     /* Kick off the highest priority task that has been created so far.
-     * Its stack location is loaded into uxSavedTaskStackPointer. */
+    Its stack location is loaded into uxSavedTaskStackPointer. */
     uxSavedTaskStackPointer = *( UBaseType_t * ) pxCurrentTCB;
     vPortStartFirstTask();
 
     /* Should never get here as the tasks will now be executing!  Call the task
-     * exit error function to prevent compiler warnings about a static function
-     * not being called in the case that the application writer overrides this
-     * functionality by defining configTASK_RETURN_ADDRESS. */
+    exit error function to prevent compiler warnings about a static function
+    not being called in the case that the application writer overrides this
+    functionality by defining configTASK_RETURN_ADDRESS. */
     prvTaskExitError();
 
     return pdFALSE;
@@ -309,7 +302,7 @@ BaseType_t xPortStartScheduler( void )
 
 void vPortIncrementTick( void )
 {
-    UBaseType_t uxSavedStatus;
+UBaseType_t uxSavedStatus;
 
     uxSavedStatus = uxPortSetInterruptMaskFromISR();
     {
@@ -331,17 +324,16 @@ void vPortIncrementTick( void )
 
 UBaseType_t uxPortSetInterruptMaskFromISR( void )
 {
-    UBaseType_t uxSavedStatusRegister;
+UBaseType_t uxSavedStatusRegister;
 
     __builtin_disable_interrupts();
     uxSavedStatusRegister = _CP0_GET_STATUS() | 0x01;
-
     /* This clears the IPL bits, then sets them to
-     * configMAX_SYSCALL_INTERRUPT_PRIORITY.  This function should not be called
-     * from an interrupt that has a priority above
-     * configMAX_SYSCALL_INTERRUPT_PRIORITY so, when used correctly, the action
-     * can only result in the IPL being unchanged or raised, and therefore never
-     * lowered. */
+    configMAX_SYSCALL_INTERRUPT_PRIORITY.  This function should not be called
+    from an interrupt that has a priority above
+    configMAX_SYSCALL_INTERRUPT_PRIORITY so, when used correctly, the action
+    can only result in the IPL being unchanged or raised, and therefore never
+    lowered. */
     _CP0_SET_STATUS( ( ( uxSavedStatusRegister & ( ~portALL_IPL_BITS ) ) ) | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) );
 
     return uxSavedStatusRegister;
@@ -356,17 +348,17 @@ void vPortClearInterruptMaskFromISR( UBaseType_t uxSavedStatusRegister )
 
 #if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
 
-    void vPortTaskUsesFPU( void )
+    void vPortTaskUsesFPU(void)
     {
-        extern void vPortInitialiseFPSCR( uint32_t uxFPSCRInit );
+    extern void vPortInitialiseFPSCR( uint32_t uxFPSCRInit );
 
         portENTER_CRITICAL();
 
         /* Initialise the floating point status register. */
-        vPortInitialiseFPSCR( portINITIAL_FPSCR );
+        vPortInitialiseFPSCR(portINITIAL_FPSCR);
 
         /* A task is registering the fact that it needs a FPU context. Set the
-         * FPU flag (saved as part of the task context). */
+        FPU flag (saved as part of the task context). */
         ulTaskHasFPUContext = pdTRUE;
 
         portEXIT_CRITICAL();
diff --git a/portable/MPLAB/PIC32MZ/portmacro.h b/portable/MPLAB/PIC32MZ/portmacro.h
index 050bb31fa..e6a3f5508 100644
--- a/portable/MPLAB/PIC32MZ/portmacro.h
+++ b/portable/MPLAB/PIC32MZ/portmacro.h
@@ -49,103 +49,102 @@
  */
 
 /* Type definitions. */
-#define portCHAR          char
-#define portFLOAT         float
-#define portDOUBLE        double
-#define portLONG          long
-#define portSHORT         short
-#define portSTACK_TYPE    uint32_t
-#define portBASE_TYPE     long
+#define portCHAR        char
+#define portFLOAT       float
+#define portDOUBLE      double
+#define portLONG        long
+#define portSHORT       short
+#define portSTACK_TYPE  uint32_t
+#define portBASE_TYPE   long
 
-typedef portSTACK_TYPE   StackType_t;
-typedef long             BaseType_t;
-typedef unsigned long    UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
 
-#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t     TickType_t;
-    #define portMAX_DELAY              ( TickType_t ) 0xffff
+#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t TickType_t;
+    #define portMAX_DELAY ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t     TickType_t;
-    #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+    typedef uint32_t TickType_t;
+    #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
 
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
-    #define portTICK_TYPE_IS_ATOMIC    1
+    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+    not need to be guarded with a critical section. */
+    #define portTICK_TYPE_IS_ATOMIC 1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portBYTE_ALIGNMENT    8
-#define portSTACK_GROWTH      -1
-#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT          8
+#define portSTACK_GROWTH            -1
+#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
 /*-----------------------------------------------------------*/
 
 /* Critical section management. */
-#define portIPL_SHIFT       ( 10UL )
-
+#define portIPL_SHIFT               ( 10UL )
 /* Don't straddle the CEE bit.  Interrupts calling FreeRTOS functions should
- * never have higher IPL bits set anyway. */
-#define portALL_IPL_BITS    ( 0x7FUL << portIPL_SHIFT )
-#define portSW0_BIT         ( 0x01 << 8 )
+never have higher IPL bits set anyway. */
+#define portALL_IPL_BITS            ( 0x7FUL << portIPL_SHIFT )
+#define portSW0_BIT                 ( 0x01 << 8 )
 
 /* This clears the IPL bits, then sets them to
- * configMAX_SYSCALL_INTERRUPT_PRIORITY.  An extra check is performed if
- * configASSERT() is defined to ensure an assertion handler does not inadvertently
- * attempt to lower the IPL when the call to assert was triggered because the IPL
- * value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY when an ISR
- * safe FreeRTOS API function was executed.  ISR safe FreeRTOS API functions are
- * those that end in FromISR.  FreeRTOS maintains a separate interrupt API to
- * ensure API function and interrupt entry is as fast and as simple as possible. */
+configMAX_SYSCALL_INTERRUPT_PRIORITY.  An extra check is performed if
+configASSERT() is defined to ensure an assertion handler does not inadvertently
+attempt to lower the IPL when the call to assert was triggered because the IPL
+value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY when an ISR
+safe FreeRTOS API function was executed.  ISR safe FreeRTOS API functions are
+those that end in FromISR.  FreeRTOS maintains a separate interrupt API to
+ensure API function and interrupt entry is as fast and as simple as possible. */
 #ifdef configASSERT
-    #define portDISABLE_INTERRUPTS()                                                                      \
-    {                                                                                                     \
-        uint32_t ulStatus;                                                                                \
-                                                                                                          \
-        /* Mask interrupts at and below the kernel interrupt priority. */                                 \
-        ulStatus = _CP0_GET_STATUS();                                                                     \
-                                                                                                          \
-        /* Is the current IPL below configMAX_SYSCALL_INTERRUPT_PRIORITY? */                              \
+    #define portDISABLE_INTERRUPTS()                                            \
+    {                                                                           \
+    uint32_t ulStatus;                                                          \
+                                                                                \
+        /* Mask interrupts at and below the kernel interrupt priority. */       \
+        ulStatus = _CP0_GET_STATUS();                                           \
+                                                                                \
+        /* Is the current IPL below configMAX_SYSCALL_INTERRUPT_PRIORITY? */    \
         if( ( ( ulStatus & portALL_IPL_BITS ) >> portIPL_SHIFT ) < configMAX_SYSCALL_INTERRUPT_PRIORITY ) \
-        {                                                                                                 \
-            ulStatus &= ~portALL_IPL_BITS;                                                                \
-            _CP0_SET_STATUS( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) );  \
-        }                                                                                                 \
+        {                                                                       \
+            ulStatus &= ~portALL_IPL_BITS;                                      \
+            _CP0_SET_STATUS( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
+        }                                                                       \
     }
 #else /* configASSERT */
-    #define portDISABLE_INTERRUPTS()                                                                 \
-    {                                                                                                \
-        uint32_t ulStatus;                                                                           \
-                                                                                                     \
-        /* Mask interrupts at and below the kernel interrupt priority. */                            \
-        ulStatus = _CP0_GET_STATUS();                                                                \
-        ulStatus &= ~portALL_IPL_BITS;                                                               \
+    #define portDISABLE_INTERRUPTS()                                        \
+    {                                                                       \
+    uint32_t ulStatus;                                                      \
+                                                                            \
+        /* Mask interrupts at and below the kernel interrupt priority. */   \
+        ulStatus = _CP0_GET_STATUS();                                       \
+        ulStatus &= ~portALL_IPL_BITS;                                      \
         _CP0_SET_STATUS( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
     }
 #endif /* configASSERT */
 
-#define portENABLE_INTERRUPTS()        \
-    {                                  \
-        uint32_t ulStatus;             \
-                                       \
-        /* Unmask all interrupts. */   \
-        ulStatus = _CP0_GET_STATUS();  \
-        ulStatus &= ~portALL_IPL_BITS; \
-        _CP0_SET_STATUS( ulStatus );   \
-    }
+#define portENABLE_INTERRUPTS()                                         \
+{                                                                       \
+uint32_t ulStatus;                                                      \
+                                                                        \
+    /* Unmask all interrupts. */                                        \
+    ulStatus = _CP0_GET_STATUS();                                       \
+    ulStatus &= ~portALL_IPL_BITS;                                      \
+    _CP0_SET_STATUS( ulStatus );                                        \
+}
 
 
 extern void vTaskEnterCritical( void );
 extern void vTaskExitCritical( void );
-#define portCRITICAL_NESTING_IN_TCB    1
-#define portENTER_CRITICAL()    vTaskEnterCritical()
-#define portEXIT_CRITICAL()     vTaskExitCritical()
+#define portCRITICAL_NESTING_IN_TCB 1
+#define portENTER_CRITICAL()        vTaskEnterCritical()
+#define portEXIT_CRITICAL()         vTaskExitCritical()
 
 extern UBaseType_t uxPortSetInterruptMaskFromISR();
 extern void vPortClearInterruptMaskFromISR( UBaseType_t );
-#define portSET_INTERRUPT_MASK_FROM_ISR()                             uxPortSetInterruptMaskFromISR()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister )    vPortClearInterruptMaskFromISR( uxSavedStatusRegister )
+#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMaskFromISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) vPortClearInterruptMaskFromISR( uxSavedStatusRegister )
 
 #if ( __mips_hard_float == 0 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
     #error configUSE_TASK_FPU_SUPPORT can only be set to 1 when the part supports a hardware FPU module.
@@ -153,27 +152,27 @@ extern void vPortClearInterruptMaskFromISR( UBaseType_t );
 
 #if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
     void vPortTaskUsesFPU( void );
-    #define portTASK_USES_FLOATING_POINT()    vPortTaskUsesFPU()
+    #define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
 #endif
 
 #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-    #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
+    #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
 #endif
 
 #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
 
-/* Check the configuration. */
-    #if ( configMAX_PRIORITIES > 32 )
+    /* Check the configuration. */
+    #if( configMAX_PRIORITIES > 32 )
         #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
     #endif
 
-/* Store/clear the ready priorities in a bit map. */
-    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+    /* Store/clear the ready priorities in a bit map. */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 
-/*-----------------------------------------------------------*/
+    /*-----------------------------------------------------------*/
 
-    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - _clz( ( uxReadyPriorities ) ) )
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - _clz( ( uxReadyPriorities ) ) )
 
 #endif /* taskRECORD_READY_PRIORITY */
 
@@ -181,26 +180,26 @@ extern void vPortClearInterruptMaskFromISR( UBaseType_t );
 
 /* Task utilities. */
 
-#define portYIELD()                       \
-    {                                     \
-        uint32_t ulCause;                 \
-                                          \
-        /* Trigger software interrupt. */ \
-        ulCause = _CP0_GET_CAUSE();       \
-        ulCause |= portSW0_BIT;           \
-        _CP0_SET_CAUSE( ulCause );        \
-    }
+#define portYIELD()                             \
+{                                               \
+uint32_t ulCause;                               \
+                                                \
+    /* Trigger software interrupt. */           \
+    ulCause = _CP0_GET_CAUSE();                 \
+    ulCause |= portSW0_BIT;                     \
+    _CP0_SET_CAUSE( ulCause );                  \
+}
 
 extern volatile UBaseType_t uxInterruptNesting;
-#define portASSERT_IF_IN_ISR()    configASSERT( uxInterruptNesting == 0 )
+#define portASSERT_IF_IN_ISR() configASSERT( uxInterruptNesting == 0 )
 
-#define portNOP()                 __asm volatile ( "nop" )
+#define portNOP()   __asm volatile ( "nop" )
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters ) __attribute__( ( noreturn ) )
-#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn))
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
 /*-----------------------------------------------------------*/
 
 #define portEND_SWITCHING_ISR( xSwitchRequired ) \

From 9a2ce912ffae4294276dd9b0fd91c23e351c63b0 Mon Sep 17 00:00:00 2001
From: Soren Ptak <ptaksoren@gmail.com>
Date: Thu, 23 Nov 2023 02:53:55 -0800
Subject: [PATCH 116/424] Revert formatting on Rowley ports (#884)

Co-authored-by: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
---
 portable/Rowley/MSP430F449/port.c      |  65 ++++++++--------
 portable/Rowley/MSP430F449/portasm.h   |  82 +++++++++----------
 portable/Rowley/MSP430F449/portmacro.h | 104 ++++++++++++-------------
 3 files changed, 126 insertions(+), 125 deletions(-)

diff --git a/portable/Rowley/MSP430F449/port.c b/portable/Rowley/MSP430F449/port.c
index b2628aaf7..992e3e763 100644
--- a/portable/Rowley/MSP430F449/port.c
+++ b/portable/Rowley/MSP430F449/port.c
@@ -31,28 +31,28 @@
 #include "task.h"
 
 /*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the MSP430 port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the MSP430 port.
+ *----------------------------------------------------------*/
 
 /* Constants required for hardware setup.  The tick ISR runs off the ACLK,
- * not the MCLK. */
+not the MCLK. */
 #define portACLK_FREQUENCY_HZ           ( ( TickType_t ) 32768 )
 #define portINITIAL_CRITICAL_NESTING    ( ( uint16_t ) 10 )
 #define portFLAGS_INT_ENABLED           ( ( StackType_t ) 0x08 )
 
 /* We require the address of the pxCurrentTCB variable, but don't want to know
- * any details of its type. */
+any details of its type. */
 typedef void TCB_t;
 extern volatile TCB_t * volatile pxCurrentTCB;
 
 /* Each task maintains a count of the critical section nesting depth.  Each
- * time a critical section is entered the count is incremented.  Each time a
- * critical section is exited the count is decremented - with interrupts only
- * being re-enabled if the count is zero.
- *
- * usCriticalNesting will get set to zero when the scheduler starts, but must
- * not be initialised to zero as this will cause problems during the startup
- * sequence. */
+time a critical section is entered the count is incremented.  Each time a
+critical section is exited the count is decremented - with interrupts only
+being re-enabled if the count is zero.
+
+usCriticalNesting will get set to zero when the scheduler starts, but must
+not be initialised to zero as this will cause problems during the startup
+sequence. */
 volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;
 /*-----------------------------------------------------------*/
 
@@ -70,26 +70,24 @@ void prvSetupTimerInterrupt( void );
  *
  * See the header file portable.h.
  */
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
 {
     /*
-     *  Place a few bytes of known values on the bottom of the stack.
-     *  This is just useful for debugging and can be included if required.
-     *
-     * pxTopOfStack = ( StackType_t ) 0x1111;
-     *  pxTopOfStack--;
-     * pxTopOfStack = ( StackType_t ) 0x2222;
-     *  pxTopOfStack--;
-     * pxTopOfStack = ( StackType_t ) 0x3333;
-     *  pxTopOfStack--;
-     */
+        Place a few bytes of known values on the bottom of the stack.
+        This is just useful for debugging and can be included if required.
+
+        *pxTopOfStack = ( StackType_t ) 0x1111;
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) 0x2222;
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) 0x3333;
+        pxTopOfStack--;
+    */
 
     /* The msp430 automatically pushes the PC then SR onto the stack before
-     * executing an ISR.  We want the stack to look just as if this has happened
-     * so place a pointer to the start of the task on the stack first - followed
-     * by the flags we want the task to use when it starts up. */
+    executing an ISR.  We want the stack to look just as if this has happened
+    so place a pointer to the start of the task on the stack first - followed
+    by the flags we want the task to use when it starts up. */
     *pxTopOfStack = ( StackType_t ) pxCode;
     pxTopOfStack--;
     *pxTopOfStack = portFLAGS_INT_ENABLED;
@@ -120,17 +118,17 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
     pxTopOfStack--;
 
     /* When the task starts is will expect to find the function parameter in
-     * R15. */
+    R15. */
     *pxTopOfStack = ( StackType_t ) pvParameters;
     pxTopOfStack--;
 
     /* A variable is used to keep track of the critical section nesting.
-     * This variable has to be stored as part of the task context and is
-     * initially set to zero. */
+    This variable has to be stored as part of the task context and is
+    initially set to zero. */
     *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;
 
     /* Return a pointer to the top of the stack we have generated so this can
-     * be stored in the task control block for the task. */
+    be stored in the task control block for the task. */
     return pxTopOfStack;
 }
 /*-----------------------------------------------------------*/
@@ -138,7 +136,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
 void vPortEndScheduler( void )
 {
     /* It is unlikely that the MSP430 port will get stopped.  If required simply
-     * disable the tick interrupt here. */
+    disable the tick interrupt here. */
 }
 /*-----------------------------------------------------------*/
 
@@ -170,3 +168,6 @@ void prvSetupTimerInterrupt( void )
     TACTL |= MC_1;
 }
 /*-----------------------------------------------------------*/
+
+
+
diff --git a/portable/Rowley/MSP430F449/portasm.h b/portable/Rowley/MSP430F449/portasm.h
index 45ffd0e08..96c27cdac 100644
--- a/portable/Rowley/MSP430F449/portasm.h
+++ b/portable/Rowley/MSP430F449/portasm.h
@@ -30,51 +30,51 @@
 #define PORT_ASM_H
 
 portSAVE_CONTEXT macro
-/* Save the remaining registers. */
-push r4
-push r5
-push r6
-push r7
-push r8
-push r9
-push r10
-push r11
-push r12
-push r13
-push r14
-push r15
-mov.w &_usCriticalNesting, r14
-push r14
-       mov.w &_pxCurrentTCB, r12
-       mov.w r1, @r12
-endm
+                /* Save the remaining registers. */
+        push    r4
+        push    r5
+        push    r6
+        push    r7
+        push    r8
+        push    r9
+        push    r10
+        push    r11
+        push    r12
+        push    r13
+        push    r14
+        push    r15
+        mov.w   &_usCriticalNesting, r14
+        push    r14
+        mov.w   &_pxCurrentTCB, r12
+        mov.w   r1, @r12
+        endm
 /*-----------------------------------------------------------*/
 
 portRESTORE_CONTEXT macro
-       mov.w &_pxCurrentTCB, r12
-       mov.w @r12, r1
-pop r15
-       mov.w r15, &_usCriticalNesting
-pop r15
-pop r14
-pop r13
-pop r12
-pop r11
-pop r10
-pop r9
-pop r8
-pop r7
-pop r6
-pop r5
-pop r4
+        mov.w   &_pxCurrentTCB, r12
+        mov.w   @r12, r1
+        pop     r15
+        mov.w   r15, &_usCriticalNesting
+        pop     r15
+        pop     r14
+        pop     r13
+        pop     r12
+        pop     r11
+        pop     r10
+        pop     r9
+        pop     r8
+        pop     r7
+        pop     r6
+        pop     r5
+        pop     r4
 
-/* The last thing on the stack will be the status register.
- *      Ensure the power down bits are clear ready for the next
- *      time this power down register is popped from the stack. */
-       bic.w   # 0xf0, 0 ( SP )
+        /* The last thing on the stack will be the status register.
+                Ensure the power down bits are clear ready for the next
+                time this power down register is popped from the stack. */
+        bic.w   #0xf0,0(SP)
 
-reti
-endm
+        reti
+        endm
 /*-----------------------------------------------------------*/
 
-#endif /* ifndef PORT_ASM_H */
+#endif
diff --git a/portable/Rowley/MSP430F449/portmacro.h b/portable/Rowley/MSP430F449/portmacro.h
index 80da469c8..7137a6e09 100644
--- a/portable/Rowley/MSP430F449/portmacro.h
+++ b/portable/Rowley/MSP430F449/portmacro.h
@@ -40,24 +40,24 @@
  */
 
 /* Type definitions. */
-#define portCHAR          char
-#define portFLOAT         float
-#define portDOUBLE        double
-#define portLONG          long
-#define portSHORT         int
-#define portSTACK_TYPE    uint16_t
-#define portBASE_TYPE     short
+#define portCHAR        char
+#define portFLOAT       float
+#define portDOUBLE      double
+#define portLONG        long
+#define portSHORT       int
+#define portSTACK_TYPE  uint16_t
+#define portBASE_TYPE   short
 
-typedef portSTACK_TYPE   StackType_t;
-typedef short            BaseType_t;
-typedef unsigned short   UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef short BaseType_t;
+typedef unsigned short UBaseType_t;
 
 
-#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t     TickType_t;
-    #define portMAX_DELAY    ( TickType_t ) 0xffff
-#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t     TickType_t;
+#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t TickType_t;
+    #define portMAX_DELAY ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS  == TICK_TYPE_WIDTH_32_BITS )
+    typedef uint32_t             TickType_t;
     #define portMAX_DELAY    ( TickType_t ) 0xffffffffUL
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -71,37 +71,37 @@ typedef unsigned short   UBaseType_t;
 /*-----------------------------------------------------------*/
 
 /* Critical section control macros. */
-#define portNO_CRITICAL_SECTION_NESTING    ( ( uint16_t ) 0 )
+#define portNO_CRITICAL_SECTION_NESTING     ( ( uint16_t ) 0 )
 
-#define portENTER_CRITICAL()                                                     \
-    {                                                                            \
-        extern volatile uint16_t usCriticalNesting;                              \
-                                                                                 \
-        portDISABLE_INTERRUPTS();                                                \
-                                                                                 \
-        /* Now interrupts are disabled usCriticalNesting can be accessed */      \
-        /* directly.  Increment ulCriticalNesting to keep a count of how many */ \
-        /* times portENTER_CRITICAL() has been called. */                        \
-        usCriticalNesting++;                                                     \
-    }
+#define portENTER_CRITICAL()                                                    \
+{                                                                               \
+extern volatile uint16_t usCriticalNesting;                         \
+                                                                                \
+    portDISABLE_INTERRUPTS();                                                   \
+                                                                                \
+    /* Now interrupts are disabled usCriticalNesting can be accessed */         \
+    /* directly.  Increment ulCriticalNesting to keep a count of how many */    \
+    /* times portENTER_CRITICAL() has been called. */                           \
+    usCriticalNesting++;                                                        \
+}
 
-#define portEXIT_CRITICAL()                                                         \
-    {                                                                               \
-        extern volatile uint16_t usCriticalNesting;                                 \
-                                                                                    \
-        if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING )                   \
-        {                                                                           \
-            /* Decrement the nesting count as we are leaving a critical section. */ \
-            usCriticalNesting--;                                                    \
-                                                                                    \
-            /* If the nesting level has reached zero then interrupts should be */   \
-            /* re-enabled. */                                                       \
-            if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING )              \
-            {                                                                       \
-                portENABLE_INTERRUPTS();                                            \
-            }                                                                       \
-        }                                                                           \
-    }
+#define portEXIT_CRITICAL()                                                     \
+{                                                                               \
+extern volatile uint16_t usCriticalNesting;                         \
+                                                                                \
+    if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING )                   \
+    {                                                                           \
+        /* Decrement the nesting count as we are leaving a critical section. */ \
+        usCriticalNesting--;                                                    \
+                                                                                \
+        /* If the nesting level has reached zero then interrupts should be */   \
+        /* re-enabled. */                                                       \
+        if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING )              \
+        {                                                                       \
+            portENABLE_INTERRUPTS();                                            \
+        }                                                                       \
+    }                                                                           \
+}
 /*-----------------------------------------------------------*/
 
 /* Task utilities. */
@@ -110,24 +110,24 @@ typedef unsigned short   UBaseType_t;
  * Manual context switch called by portYIELD or taskYIELD.
  */
 extern void vPortYield( void );
-#define portYIELD()    vPortYield()
+#define portYIELD() vPortYield()
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portBYTE_ALIGNMENT    2
-#define portSTACK_GROWTH      ( -1 )
-#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT          2
+#define portSTACK_GROWTH            ( -1 )
+#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
 #define portNOP()
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters ) __toplevel
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) __toplevel
 
 #if configINTERRUPT_EXAMPLE_METHOD == 2
 
-    extern void vTaskSwitchContext( void );
-    #define portYIELD_FROM_ISR( x )    do { if( x ) vTaskSwitchContext( ); } while( 0 )
+extern void vTaskSwitchContext( void );
+#define portYIELD_FROM_ISR( x ) do { if( x ) vTaskSwitchContext(); } while( 0 )
 
 #endif
 

From 96cdeaa7259b33fed1a599131c5245ad5a968366 Mon Sep 17 00:00:00 2001
From: Soren Ptak <ptaksoren@gmail.com>
Date: Thu, 23 Nov 2023 03:14:36 -0800
Subject: [PATCH 117/424] Revert formatting on SDCC ports (#885)

Co-authored-by: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
---
 portable/SDCC/Cygnal/port.c      | 541 +++++++++++++++----------------
 portable/SDCC/Cygnal/portmacro.h |  77 +++--
 2 files changed, 306 insertions(+), 312 deletions(-)

diff --git a/portable/SDCC/Cygnal/port.c b/portable/SDCC/Cygnal/port.c
index 61a7f8f24..8bf739eb7 100644
--- a/portable/SDCC/Cygnal/port.c
+++ b/portable/SDCC/Cygnal/port.c
@@ -27,8 +27,8 @@
  */
 
 /*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the Cygnal port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the Cygnal port.
+ *----------------------------------------------------------*/
 
 /* Standard includes. */
 #include <string.h>
@@ -38,34 +38,34 @@
 #include "task.h"
 
 /* Constants required to setup timer 2 to produce the RTOS tick. */
-#define portCLOCK_DIVISOR               ( ( uint32_t ) 12 )
-#define portMAX_TIMER_VALUE             ( ( uint32_t ) 0xffff )
-#define portENABLE_TIMER                ( ( uint8_t ) 0x04 )
-#define portTIMER_2_INTERRUPT_ENABLE    ( ( uint8_t ) 0x20 )
+#define portCLOCK_DIVISOR                               ( ( uint32_t ) 12 )
+#define portMAX_TIMER_VALUE                             ( ( uint32_t ) 0xffff )
+#define portENABLE_TIMER                                ( ( uint8_t ) 0x04 )
+#define portTIMER_2_INTERRUPT_ENABLE                    ( ( uint8_t ) 0x20 )
 
 /* The value used in the IE register when a task first starts. */
-#define portGLOBAL_INTERRUPT_BIT        ( ( StackType_t ) 0x80 )
+#define portGLOBAL_INTERRUPT_BIT                        ( ( StackType_t ) 0x80 )
 
 /* The value used in the PSW register when a task first starts. */
-#define portINITIAL_PSW                 ( ( StackType_t ) 0x00 )
+#define portINITIAL_PSW                                 ( ( StackType_t ) 0x00 )
 
 /* Macro to clear the timer 2 interrupt flag. */
-#define portCLEAR_INTERRUPT_FLAG()    TMR2CN &= ~0x80;
+#define portCLEAR_INTERRUPT_FLAG()                      TMR2CN &= ~0x80;
 
 /* Used during a context switch to store the size of the stack being copied
- * to or from XRAM. */
+to or from XRAM. */
 data static uint8_t ucStackBytes;
 
 /* Used during a context switch to point to the next byte in XRAM from/to which
- * a RAM byte is to be copied. */
+a RAM byte is to be copied. */
 xdata static StackType_t * data pxXRAMStack;
 
 /* Used during a context switch to point to the next byte in RAM from/to which
- * an XRAM byte is to be copied. */
+an XRAM byte is to be copied. */
 data static StackType_t * data pxRAMStack;
 
 /* We require the address of the pxCurrentTCB variable, but don't want to know
- * any details of its type. */
+any details of its type. */
 typedef void TCB_t;
 extern volatile TCB_t * volatile pxCurrentTCB;
 
@@ -76,226 +76,223 @@ extern volatile TCB_t * volatile pxCurrentTCB;
 static void prvSetupTimerInterrupt( void );
 
 /*-----------------------------------------------------------*/
-
 /*
  * Macro that copies the current stack from internal RAM to XRAM.  This is
  * required as the 8051 only contains enough internal RAM for a single stack,
  * but we have a stack for every task.
  */
-#define portCOPY_STACK_TO_XRAM() \
-    {                            \
-        /* pxCurrentTCB points to a TCB which itself points to the location into \
-         * which the first stack byte should be copied. Set pxXRAMStack to point \
-         * to the location into which the first stack byte is to be copied. */            \
-        pxXRAMStack = ( xdata StackType_t * ) *( ( xdata StackType_t ** ) pxCurrentTCB ); \
-                                                                                          \
-        /* Set pxRAMStack to point to the first byte to be coped from the stack. */       \
-        pxRAMStack = ( data StackType_t * data ) configSTACK_START;                       \
-                                                                                          \
-        /* Calculate the size of the stack we are about to copy from the current \
-         * stack pointer value. */                     \
-        ucStackBytes = SP - ( configSTACK_START - 1 ); \
-                                                       \
-        /* Before starting to copy the stack, store the calculated stack size so \
-         * the stack can be restored when the task is resumed. */ \
-        * pxXRAMStack = ucStackBytes;                             \
-                                                                  \
-        /* Copy each stack byte in turn.  pxXRAMStack is incremented first as we \
-         * have already stored the stack size into XRAM. */ \
-        while( ucStackBytes )                               \
-        {                                                   \
-            pxXRAMStack ++;                                 \
-            * pxXRAMStack = * pxRAMStack;                   \
-            pxRAMStack ++;                                  \
-            ucStackBytes --;                                \
-        }                                                   \
-    }
+#define portCOPY_STACK_TO_XRAM()                                                            \
+{                                                                                           \
+        /* pxCurrentTCB points to a TCB which itself points to the location into            \
+        which the first stack byte should be copied. Set pxXRAMStack to point               \
+        to the location into which the first stack byte is to be copied. */                 \
+        pxXRAMStack = ( xdata StackType_t * ) *( ( xdata StackType_t ** ) pxCurrentTCB );   \
+                                                                                            \
+        /* Set pxRAMStack to point to the first byte to be coped from the stack. */         \
+        pxRAMStack = ( data StackType_t * data ) configSTACK_START;                         \
+                                                                                            \
+        /* Calculate the size of the stack we are about to copy from the current            \
+        stack pointer value. */                                                             \
+        ucStackBytes = SP - ( configSTACK_START - 1 );                                      \
+                                                                                            \
+        /* Before starting to copy the stack, store the calculated stack size so            \
+        the stack can be restored when the task is resumed. */                              \
+        *pxXRAMStack = ucStackBytes;                                                        \
+                                                                                            \
+        /* Copy each stack byte in turn.  pxXRAMStack is incremented first as we            \
+        have already stored the stack size into XRAM. */                                    \
+        while( ucStackBytes )                                                               \
+        {                                                                                   \
+                pxXRAMStack++;                                                              \
+                *pxXRAMStack = *pxRAMStack;                                                 \
+                pxRAMStack++;                                                               \
+                ucStackBytes--;                                                             \
+        }                                                                                   \
+}
 /*-----------------------------------------------------------*/
 
 /*
  * Macro that copies the stack of the task being resumed from XRAM into
  * internal RAM.
  */
-#define portCOPY_XRAM_TO_STACK() \
-    {                            \
-        /* Setup the pointers as per portCOPY_STACK_TO_XRAM(), but this time to \
-         * copy the data back out of XRAM and into the stack. */                          \
-        pxXRAMStack = ( xdata StackType_t * ) *( ( xdata StackType_t ** ) pxCurrentTCB ); \
-        pxRAMStack = ( data StackType_t * data )( configSTACK_START - 1 );                \
-                                                                                          \
-        /* The first value stored in XRAM was the size of the stack - i.e. the \
-         * number of bytes we need to copy back. */                      \
-        ucStackBytes = pxXRAMStack[ 0 ];                                 \
-                                                                         \
-        /* Copy the required number of bytes back into the stack. */     \
-        do                                                               \
-        {                                                                \
-            pxXRAMStack ++;                                              \
-            pxRAMStack ++;                                               \
-            * pxRAMStack = * pxXRAMStack;                                \
-            ucStackBytes --;                                             \
-        } while( ucStackBytes );                                         \
-                                                                         \
-        /* Restore the stack pointer ready to use the restored stack. */ \
-        SP = ( uint8_t ) pxRAMStack;                                     \
-    }
+#define portCOPY_XRAM_TO_STACK()                                                            \
+{                                                                                           \
+        /* Setup the pointers as per portCOPY_STACK_TO_XRAM(), but this time to             \
+        copy the data back out of XRAM and into the stack. */                               \
+        pxXRAMStack = ( xdata StackType_t * ) *( ( xdata StackType_t ** ) pxCurrentTCB );   \
+        pxRAMStack = ( data StackType_t * data ) ( configSTACK_START - 1 );                 \
+                                                                                            \
+        /* The first value stored in XRAM was the size of the stack - i.e. the              \
+        number of bytes we need to copy back. */                                            \
+        ucStackBytes = pxXRAMStack[ 0 ];                                                    \
+                                                                                            \
+        /* Copy the required number of bytes back into the stack. */                        \
+        do                                                                                  \
+        {                                                                                   \
+                pxXRAMStack++;                                                              \
+                pxRAMStack++;                                                               \
+                *pxRAMStack = *pxXRAMStack;                                                 \
+                ucStackBytes--;                                                             \
+        } while( ucStackBytes );                                                            \
+                                                                                            \
+        /* Restore the stack pointer ready to use the restored stack. */                    \
+        SP = ( uint8_t ) pxRAMStack;                                                        \
+}
 /*-----------------------------------------------------------*/
 
 /*
  * Macro to push the current execution context onto the stack, before the stack
  * is moved to XRAM.
  */
-#define portSAVE_CONTEXT() \
-    {                      \
-        _asm               \
-        /* Push ACC first, as when restoring the context it must be restored \
-         * last (it is used to set the IE register). */      \
-        push ACC                                             \
-        /* Store the IE register then disable interrupts. */ \
-        push IE                                              \
-        clr _EA                                              \
-        push DPL                                             \
-        push DPH                                             \
-        push b                                               \
-        push ar2                                             \
-        push ar3                                             \
-        push ar4                                             \
-        push ar5                                             \
-        push ar6                                             \
-        push ar7                                             \
-        push ar0                                             \
-        push ar1                                             \
-        push PSW                                             \
-        _endasm;                                             \
-        PSW = 0;                                             \
-        _asm                                                 \
-        push _bp                                             \
-        _endasm;                                             \
-    }
+#define portSAVE_CONTEXT()                                                                  \
+{                                                                                           \
+        _asm                                                                                \
+                /* Push ACC first, as when restoring the context it must be restored        \
+                last (it is used to set the IE register). */                                \
+                push        ACC                                                             \
+                /* Store the IE register then disable interrupts. */                        \
+                push        IE                                                              \
+                clr                _EA                                                      \
+                push        DPL                                                             \
+                push        DPH                                                             \
+                push        b                                                               \
+                push        ar2                                                             \
+                push        ar3                                                             \
+                push        ar4                                                             \
+                push        ar5                                                             \
+                push        ar6                                                             \
+                push        ar7                                                             \
+                push        ar0                                                             \
+                push        ar1                                                             \
+                push        PSW                                                             \
+        _endasm;                                                                            \
+                PSW = 0;                                                                    \
+        _asm                                                                                \
+                push        _bp                                                             \
+        _endasm;                                                                            \
+}
 /*-----------------------------------------------------------*/
 
 /*
  * Macro that restores the execution context from the stack.  The execution
  * context was saved into the stack before the stack was copied into XRAM.
  */
-#define portRESTORE_CONTEXT() \
-    {                         \
-        _asm                  \
-        pop _bp               \
-        pop PSW               \
-        pop ar1               \
-        pop ar0               \
-        pop ar7               \
-        pop ar6               \
-        pop ar5               \
-        pop ar4               \
-        pop ar3               \
-        pop ar2               \
-        pop b                 \
-        pop DPH               \
-        pop DPL               \
-        /* The next byte of the stack is the IE register.  Only the global \
-         * enable bit forms part of the task context.  Pop off the IE then set \
-         * the global enable bit to match that of the stored IE register. */ \
-        pop ACC                                                              \
-        JB ACC .7, 00 98$                                                    \
-        CLR IE .7                                                            \
-        LJMP 00 99$                                                          \
-        00 98$ :                                                             \
-        SETB IE .7                                                           \
-        00 99$ :                                                             \
-        /* Finally pop off the ACC, which was the first register saved. */   \
-        pop ACC                                                              \
-        reti                                                                 \
-        _endasm;                                                             \
-    }
+#define portRESTORE_CONTEXT()                                                               \
+{                                                                                           \
+        _asm                                                                                \
+                pop                _bp                                                      \
+                pop                PSW                                                      \
+                pop                ar1                                                      \
+                pop                ar0                                                      \
+                pop                ar7                                                      \
+                pop                ar6                                                      \
+                pop                ar5                                                      \
+                pop                ar4                                                      \
+                pop                ar3                                                      \
+                pop                ar2                                                      \
+                pop                b                                                        \
+                pop                DPH                                                      \
+                pop                DPL                                                      \
+                /* The next byte of the stack is the IE register.  Only the global          \
+                enable bit forms part of the task context.  Pop off the IE then set         \
+                the global enable bit to match that of the stored IE register. */           \
+                pop                ACC                                                      \
+                JB                ACC.7,0098$                                               \
+                CLR                IE.7                                                     \
+                LJMP        0099$                                                           \
+        0098$:                                                                              \
+                SETB        IE.7                                                            \
+        0099$:                                                                              \
+                /* Finally pop off the ACC, which was the first register saved. */          \
+                pop                ACC                                                      \
+                reti                                                                        \
+        _endasm;                                                                            \
+}
 /*-----------------------------------------------------------*/
 
 /*
  * See header file for description.
  */
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
 {
-    uint32_t ulAddress;
-    StackType_t * pxStartOfStack;
+uint32_t ulAddress;
+StackType_t *pxStartOfStack;
 
-    /* Leave space to write the size of the stack as the first byte. */
-    pxStartOfStack = pxTopOfStack;
-    pxTopOfStack++;
+        /* Leave space to write the size of the stack as the first byte. */
+        pxStartOfStack = pxTopOfStack;
+        pxTopOfStack++;
 
-    /* Place a few bytes of known values on the bottom of the stack.
-     * This is just useful for debugging and can be uncommented if required.
-     * pxTopOfStack = 0x11;
-     * pxTopOfStack++;
-     * pxTopOfStack = 0x22;
-     * pxTopOfStack++;
-     * pxTopOfStack = 0x33;
-     * pxTopOfStack++;
-     */
+        /* Place a few bytes of known values on the bottom of the stack.
+        This is just useful for debugging and can be uncommented if required.
+        *pxTopOfStack = 0x11;
+        pxTopOfStack++;
+        *pxTopOfStack = 0x22;
+        pxTopOfStack++;
+        *pxTopOfStack = 0x33;
+        pxTopOfStack++;
+        */
 
-    /* Simulate how the stack would look after a call to the scheduler tick
-     * ISR.
-     *
-     * The return address that would have been pushed by the MCU. */
-    ulAddress = ( uint32_t ) pxCode;
-    *pxTopOfStack = ( StackType_t ) ulAddress;
-    ulAddress >>= 8;
-    pxTopOfStack++;
-    *pxTopOfStack = ( StackType_t ) ( ulAddress );
-    pxTopOfStack++;
+        /* Simulate how the stack would look after a call to the scheduler tick
+        ISR.
 
-    /* Next all the registers will have been pushed by portSAVE_CONTEXT(). */
-    *pxTopOfStack = 0xaa; /* acc */
-    pxTopOfStack++;
+        The return address that would have been pushed by the MCU. */
+        ulAddress = ( uint32_t ) pxCode;
+        *pxTopOfStack = ( StackType_t ) ulAddress;
+        ulAddress >>= 8;
+        pxTopOfStack++;
+        *pxTopOfStack = ( StackType_t ) ( ulAddress );
+        pxTopOfStack++;
 
-    /* We want tasks to start with interrupts enabled. */
-    *pxTopOfStack = portGLOBAL_INTERRUPT_BIT;
-    pxTopOfStack++;
+        /* Next all the registers will have been pushed by portSAVE_CONTEXT(). */
+        *pxTopOfStack = 0xaa;        /* acc */
+        pxTopOfStack++;
 
-    /* The function parameters will be passed in the DPTR and B register as
-     * a three byte generic pointer is used. */
-    ulAddress = ( uint32_t ) pvParameters;
-    *pxTopOfStack = ( StackType_t ) ulAddress; /* DPL */
-    ulAddress >>= 8;
-    *pxTopOfStack++;
-    *pxTopOfStack = ( StackType_t ) ulAddress; /* DPH */
-    ulAddress >>= 8;
-    pxTopOfStack++;
-    *pxTopOfStack = ( StackType_t ) ulAddress; /* b */
-    pxTopOfStack++;
+        /* We want tasks to start with interrupts enabled. */
+        *pxTopOfStack = portGLOBAL_INTERRUPT_BIT;
+        pxTopOfStack++;
 
-    /* The remaining registers are straight forward. */
-    *pxTopOfStack = 0x02; /* R2 */
-    pxTopOfStack++;
-    *pxTopOfStack = 0x03; /* R3 */
-    pxTopOfStack++;
-    *pxTopOfStack = 0x04; /* R4 */
-    pxTopOfStack++;
-    *pxTopOfStack = 0x05; /* R5 */
-    pxTopOfStack++;
-    *pxTopOfStack = 0x06; /* R6 */
-    pxTopOfStack++;
-    *pxTopOfStack = 0x07; /* R7 */
-    pxTopOfStack++;
-    *pxTopOfStack = 0x00; /* R0 */
-    pxTopOfStack++;
-    *pxTopOfStack = 0x01; /* R1 */
-    pxTopOfStack++;
-    *pxTopOfStack = 0x00; /* PSW */
-    pxTopOfStack++;
-    *pxTopOfStack = 0xbb; /* BP */
+        /* The function parameters will be passed in the DPTR and B register as
+        a three byte generic pointer is used. */
+        ulAddress = ( uint32_t ) pvParameters;
+        *pxTopOfStack = ( StackType_t ) ulAddress;        /* DPL */
+        ulAddress >>= 8;
+        *pxTopOfStack++;
+        *pxTopOfStack = ( StackType_t ) ulAddress;        /* DPH */
+        ulAddress >>= 8;
+        pxTopOfStack++;
+        *pxTopOfStack = ( StackType_t ) ulAddress;        /* b */
+        pxTopOfStack++;
 
-    /* Dont increment the stack size here as we don't want to include
-     * the stack size byte as part of the stack size count.
-     *
-     * Finally we place the stack size at the beginning. */
-    *pxStartOfStack = ( StackType_t ) ( pxTopOfStack - pxStartOfStack );
+        /* The remaining registers are straight forward. */
+        *pxTopOfStack = 0x02;        /* R2 */
+        pxTopOfStack++;
+        *pxTopOfStack = 0x03;        /* R3 */
+        pxTopOfStack++;
+        *pxTopOfStack = 0x04;        /* R4 */
+        pxTopOfStack++;
+        *pxTopOfStack = 0x05;        /* R5 */
+        pxTopOfStack++;
+        *pxTopOfStack = 0x06;        /* R6 */
+        pxTopOfStack++;
+        *pxTopOfStack = 0x07;        /* R7 */
+        pxTopOfStack++;
+        *pxTopOfStack = 0x00;        /* R0 */
+        pxTopOfStack++;
+        *pxTopOfStack = 0x01;        /* R1 */
+        pxTopOfStack++;
+        *pxTopOfStack = 0x00;        /* PSW */
+        pxTopOfStack++;
+        *pxTopOfStack = 0xbb;        /* BP */
 
-    /* Unlike most ports, we return the start of the stack as this is where the
-     * size of the stack is stored. */
-    return pxStartOfStack;
+        /* Dont increment the stack size here as we don't want to include
+        the stack size byte as part of the stack size count.
+
+        Finally we place the stack size at the beginning. */
+        *pxStartOfStack = ( StackType_t ) ( pxTopOfStack - pxStartOfStack );
+
+        /* Unlike most ports, we return the start of the stack as this is where the
+        size of the stack is stored. */
+        return pxStartOfStack;
 }
 /*-----------------------------------------------------------*/
 
@@ -304,26 +301,26 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
  */
 BaseType_t xPortStartScheduler( void )
 {
-    /* Setup timer 2 to generate the RTOS tick. */
-    prvSetupTimerInterrupt();
+        /* Setup timer 2 to generate the RTOS tick. */
+        prvSetupTimerInterrupt();
 
-    /* Make sure we start with the expected SFR page.  This line should not
-     * really be required. */
-    SFRPAGE = 0;
+        /* Make sure we start with the expected SFR page.  This line should not
+        really be required. */
+        SFRPAGE = 0;
 
-    /* Copy the stack for the first task to execute from XRAM into the stack,
-     * restore the task context from the new stack, then start running the task. */
-    portCOPY_XRAM_TO_STACK();
-    portRESTORE_CONTEXT();
+        /* Copy the stack for the first task to execute from XRAM into the stack,
+        restore the task context from the new stack, then start running the task. */
+        portCOPY_XRAM_TO_STACK();
+        portRESTORE_CONTEXT();
 
-    /* Should never get here! */
-    return pdTRUE;
+        /* Should never get here! */
+        return pdTRUE;
 }
 /*-----------------------------------------------------------*/
 
 void vPortEndScheduler( void )
 {
-    /* Not implemented for this port. */
+        /* Not implemented for this port. */
 }
 /*-----------------------------------------------------------*/
 
@@ -333,92 +330,92 @@ void vPortEndScheduler( void )
  */
 void vPortYield( void ) _naked
 {
-    /* Save the execution context onto the stack, then copy the entire stack
-     * to XRAM.  This is necessary as the internal RAM is only large enough to
-     * hold one stack, and we want one per task.
-     *
-     * PERFORMANCE COULD BE IMPROVED BY ONLY COPYING TO XRAM IF A TASK SWITCH
-     * IS REQUIRED. */
-    portSAVE_CONTEXT();
-    portCOPY_STACK_TO_XRAM();
+        /* Save the execution context onto the stack, then copy the entire stack
+        to XRAM.  This is necessary as the internal RAM is only large enough to
+        hold one stack, and we want one per task.
 
-    /* Call the standard scheduler context switch function. */
-    vTaskSwitchContext();
+        PERFORMANCE COULD BE IMPROVED BY ONLY COPYING TO XRAM IF A TASK SWITCH
+        IS REQUIRED. */
+        portSAVE_CONTEXT();
+        portCOPY_STACK_TO_XRAM();
 
-    /* Copy the stack of the task about to execute from XRAM into RAM and
-     * restore it's context ready to run on exiting. */
-    portCOPY_XRAM_TO_STACK();
-    portRESTORE_CONTEXT();
+        /* Call the standard scheduler context switch function. */
+        vTaskSwitchContext();
+
+        /* Copy the stack of the task about to execute from XRAM into RAM and
+        restore it's context ready to run on exiting. */
+        portCOPY_XRAM_TO_STACK();
+        portRESTORE_CONTEXT();
 }
 /*-----------------------------------------------------------*/
 
 #if configUSE_PREEMPTION == 1
-    void vTimer2ISR( void ) interrupt 5 _naked
-    {
-        /* Preemptive context switch function triggered by the timer 2 ISR.
-         * This does the same as vPortYield() (see above) with the addition
-         * of incrementing the RTOS tick count. */
-
-        portSAVE_CONTEXT();
-        portCOPY_STACK_TO_XRAM();
-
-        if( xTaskIncrementTick() != pdFALSE )
+        void vTimer2ISR( void ) interrupt 5 _naked
         {
-            vTaskSwitchContext();
+                /* Preemptive context switch function triggered by the timer 2 ISR.
+                This does the same as vPortYield() (see above) with the addition
+                of incrementing the RTOS tick count. */
+
+                portSAVE_CONTEXT();
+                portCOPY_STACK_TO_XRAM();
+
+                if( xTaskIncrementTick() != pdFALSE )
+                {
+                        vTaskSwitchContext();
+                }
+
+                portCLEAR_INTERRUPT_FLAG();
+                portCOPY_XRAM_TO_STACK();
+                portRESTORE_CONTEXT();
         }
+#else
+        void vTimer2ISR( void ) interrupt 5
+        {
+                /* When using the cooperative scheduler the timer 2 ISR is only
+                required to increment the RTOS tick count. */
 
-        portCLEAR_INTERRUPT_FLAG();
-        portCOPY_XRAM_TO_STACK();
-        portRESTORE_CONTEXT();
-    }
-#else /* if configUSE_PREEMPTION == 1 */
-    void vTimer2ISR( void ) interrupt 5
-    {
-        /* When using the cooperative scheduler the timer 2 ISR is only
-         * required to increment the RTOS tick count. */
-
-        xTaskIncrementTick();
-        portCLEAR_INTERRUPT_FLAG();
-    }
-#endif /* if configUSE_PREEMPTION == 1 */
+                xTaskIncrementTick();
+                portCLEAR_INTERRUPT_FLAG();
+        }
+#endif
 /*-----------------------------------------------------------*/
 
 static void prvSetupTimerInterrupt( void )
 {
-    uint8_t ucOriginalSFRPage;
+uint8_t ucOriginalSFRPage;
 
 /* Constants calculated to give the required timer capture values. */
-    const uint32_t ulTicksPerSecond = configCPU_CLOCK_HZ / portCLOCK_DIVISOR;
-    const uint32_t ulCaptureTime = ulTicksPerSecond / configTICK_RATE_HZ;
-    const uint32_t ulCaptureValue = portMAX_TIMER_VALUE - ulCaptureTime;
-    const uint8_t ucLowCaptureByte = ( uint8_t ) ( ulCaptureValue & ( uint32_t ) 0xff );
-    const uint8_t ucHighCaptureByte = ( uint8_t ) ( ulCaptureValue >> ( uint32_t ) 8 );
+const uint32_t ulTicksPerSecond = configCPU_CLOCK_HZ / portCLOCK_DIVISOR;
+const uint32_t ulCaptureTime = ulTicksPerSecond / configTICK_RATE_HZ;
+const uint32_t ulCaptureValue = portMAX_TIMER_VALUE - ulCaptureTime;
+const uint8_t ucLowCaptureByte = ( uint8_t ) ( ulCaptureValue & ( uint32_t ) 0xff );
+const uint8_t ucHighCaptureByte = ( uint8_t ) ( ulCaptureValue >> ( uint32_t ) 8 );
 
-    /* NOTE:  This uses a timer only present on 8052 architecture. */
+        /* NOTE:  This uses a timer only present on 8052 architecture. */
 
-    /* Remember the current SFR page so we can restore it at the end of the
-     * function. */
-    ucOriginalSFRPage = SFRPAGE;
-    SFRPAGE = 0;
+        /* Remember the current SFR page so we can restore it at the end of the
+        function. */
+        ucOriginalSFRPage = SFRPAGE;
+        SFRPAGE = 0;
 
-    /* TMR2CF can be left in its default state. */
-    TMR2CF = ( uint8_t ) 0;
+        /* TMR2CF can be left in its default state. */
+        TMR2CF = ( uint8_t ) 0;
 
-    /* Setup the overflow reload value. */
-    RCAP2L = ucLowCaptureByte;
-    RCAP2H = ucHighCaptureByte;
+        /* Setup the overflow reload value. */
+        RCAP2L = ucLowCaptureByte;
+        RCAP2H = ucHighCaptureByte;
 
-    /* The initial load is performed manually. */
-    TMR2L = ucLowCaptureByte;
-    TMR2H = ucHighCaptureByte;
+        /* The initial load is performed manually. */
+        TMR2L = ucLowCaptureByte;
+        TMR2H = ucHighCaptureByte;
 
-    /* Enable the timer 2 interrupts. */
-    IE |= portTIMER_2_INTERRUPT_ENABLE;
+        /* Enable the timer 2 interrupts. */
+        IE |= portTIMER_2_INTERRUPT_ENABLE;
 
-    /* Interrupts are disabled when this is called so the timer can be started
-     * here. */
-    TMR2CN = portENABLE_TIMER;
+        /* Interrupts are disabled when this is called so the timer can be started
+        here. */
+        TMR2CN = portENABLE_TIMER;
 
-    /* Restore the original SFR page. */
-    SFRPAGE = ucOriginalSFRPage;
+        /* Restore the original SFR page. */
+        SFRPAGE = ucOriginalSFRPage;
 }
diff --git a/portable/SDCC/Cygnal/portmacro.h b/portable/SDCC/Cygnal/portmacro.h
index 7cfbc8cc9..04186381f 100644
--- a/portable/SDCC/Cygnal/portmacro.h
+++ b/portable/SDCC/Cygnal/portmacro.h
@@ -49,23 +49,23 @@ void vSerialISR( void ) interrupt 4;
  */
 
 /* Type definitions. */
-#define portCHAR          char
-#define portFLOAT         float
-#define portDOUBLE        float
-#define portLONG          long
-#define portSHORT         short
-#define portSTACK_TYPE    uint8_t
-#define portBASE_TYPE     char
+#define portCHAR        char
+#define portFLOAT       float
+#define portDOUBLE      float
+#define portLONG        long
+#define portSHORT       short
+#define portSTACK_TYPE  uint8_t
+#define portBASE_TYPE   char
 
-typedef portSTACK_TYPE   StackType_t;
-typedef signed char      BaseType_t;
-typedef unsigned char    UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef signed char BaseType_t;
+typedef unsigned char UBaseType_t;
 
-#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t     TickType_t;
-    #define portMAX_DELAY    ( TickType_t ) 0xffff
-#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t     TickType_t;
+#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t TickType_t;
+    #define portMAX_DELAY ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS  == TICK_TYPE_WIDTH_32_BITS )
+    typedef uint32_t             TickType_t;
     #define portMAX_DELAY    ( TickType_t ) 0xffffffffUL
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -73,47 +73,44 @@ typedef unsigned char    UBaseType_t;
 /*-----------------------------------------------------------*/
 
 /* Critical section management. */
-#define portENTER_CRITICAL() \
-    _asm                     \
-    push ACC                 \
-    push IE                  \
-    _endasm;                 \
-    EA = 0;
+#define portENTER_CRITICAL()        _asm        \
+                                    push    ACC \
+                                    push    IE  \
+                                    _endasm;    \
+                                    EA = 0;
 
-#define portEXIT_CRITICAL() \
-    _asm                    \
-    pop ACC                 \
-    _endasm;                \
-    ACC &= 0x80;            \
-    IE |= ACC;              \
-    _asm                    \
-    pop ACC                 \
-        _endasm;
+#define portEXIT_CRITICAL()         _asm            \
+                                    pop     ACC     \
+                                    _endasm;        \
+                                    ACC &= 0x80;    \
+                                    IE |= ACC;      \
+                                    _asm            \
+                                    pop     ACC     \
+                                    _endasm;
 
 #define portDISABLE_INTERRUPTS()    EA = 0;
 #define portENABLE_INTERRUPTS()     EA = 1;
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portBYTE_ALIGNMENT    1
-#define portSTACK_GROWTH      ( 1 )
-#define portTICK_PERIOD_MS    ( ( uint32_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT          1
+#define portSTACK_GROWTH            ( 1 )
+#define portTICK_PERIOD_MS          ( ( uint32_t ) 1000 / configTICK_RATE_HZ )
 /*-----------------------------------------------------------*/
 
 /* Task utilities. */
 void vPortYield( void ) _naked;
-#define portYIELD()    vPortYield();
+#define portYIELD() vPortYield();
 /*-----------------------------------------------------------*/
 
-#define portNOP() \
-    _asm          \
-    nop           \
-    _endasm;
+#define portNOP()               _asm    \
+                                    nop \
+                                _endasm;
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
 
 #endif /* PORTMACRO_H */

From 92365c9784d26e9d530aee62fb8c5583dc966b65 Mon Sep 17 00:00:00 2001
From: Soren Ptak <ptaksoren@gmail.com>
Date: Thu, 23 Nov 2023 03:39:28 -0800
Subject: [PATCH 118/424] Revert Portable/Softune Formatting (#886)

* Revert formatting on Softune ports

* Fix spelling mistakes

---------

Co-authored-by: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
---
 portable/Softune/MB91460/__STD_LIB_sbrk.c |  33 +-
 portable/Softune/MB91460/port.c           |  98 +++---
 portable/Softune/MB91460/portmacro.h      |  62 ++--
 portable/Softune/MB96340/__STD_LIB_sbrk.c |  33 +-
 portable/Softune/MB96340/port.c           | 360 +++++++++++-----------
 portable/Softune/MB96340/portmacro.h      |  76 ++---
 6 files changed, 326 insertions(+), 336 deletions(-)

diff --git a/portable/Softune/MB91460/__STD_LIB_sbrk.c b/portable/Softune/MB91460/__STD_LIB_sbrk.c
index 0be354fec..d328a65fc 100644
--- a/portable/Softune/MB91460/__STD_LIB_sbrk.c
+++ b/portable/Softune/MB91460/__STD_LIB_sbrk.c
@@ -30,29 +30,26 @@
 /* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */
 /* ELIGIBILITY FOR ANY PURPOSES.                                             */
 /*                 (C) Fujitsu Microelectronics Europe GmbH                  */
-
 /*---------------------------------------------------------------------------
- * __STD_LIB_sbrk.C
- * - Used by heap_3.c for memory allocation and deletion.
- *
- * /*---------------------------------------------------------------------------*/
+  __STD_LIB_sbrk.C
+  - Used by heap_3.c for memory allocation and deletion.
+
+/*---------------------------------------------------------------------------*/
 
 #include "FreeRTOSConfig.h"
 #include <stdlib.h>
 
-static long brk_siz = 0;
-typedef int _heep_t;
-#define ROUNDUP( s )    ( ( ( s ) + sizeof( _heep_t ) - 1 ) & ~( sizeof( _heep_t ) - 1 ) )
-static _heep_t _heep[ ROUNDUP( configTOTAL_HEAP_SIZE ) / sizeof( _heep_t ) ];
-#define              _heep_size    ROUNDUP( configTOTAL_HEAP_SIZE )
+    static  long         brk_siz  =  0;
+    typedef int          _heep_t;
+    #define ROUNDUP(s)   (((s)+sizeof(_heep_t)-1)&~(sizeof(_heep_t)-1))
+    static  _heep_t      _heep[ROUNDUP(configTOTAL_HEAP_SIZE)/sizeof(_heep_t)];
+    #define              _heep_size      ROUNDUP(configTOTAL_HEAP_SIZE)
 
-extern char * sbrk( int size )
-{
-    if( ( brk_siz + size > _heep_size ) || ( brk_siz + size < 0 ) )
+    extern  char  *sbrk(int  size)
     {
-        return( ( char * ) -1 );
-    }
+       if  (brk_siz  +  size  >  _heep_size  ||  brk_siz  +  size  <  0)
 
-    brk_siz += size;
-    return( ( char * ) _heep + brk_siz - size );
-}
+          return((char*)-1);
+       brk_siz  +=  size;
+       return(  (char*)_heep  +  brk_siz  -  size);
+    }
diff --git a/portable/Softune/MB91460/port.c b/portable/Softune/MB91460/port.c
index b8248f2b3..08e197b06 100644
--- a/portable/Softune/MB91460/port.c
+++ b/portable/Softune/MB91460/port.c
@@ -33,7 +33,7 @@
 /*-----------------------------------------------------------*/
 
 /* We require the address of the pxCurrentTCB variable, but don't want to know
- * any details of its type. */
+any details of its type. */
 typedef void TCB_t;
 extern volatile TCB_t * volatile pxCurrentTCB;
 
@@ -106,12 +106,10 @@ static void prvSetupTimerInterrupt( void );
  *
  * See the header file portable.h.
  */
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
 {
     /* Place a few bytes of known values on the bottom of the stack.
-     * This is just useful for debugging. */
+    This is just useful for debugging. */
 
     *pxTopOfStack = 0x11111111;
     pxTopOfStack--;
@@ -121,9 +119,9 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
     pxTopOfStack--;
 
     /* This is a redundant push to the stack, it may be required if
-     * in some implementations of the compiler the parameter to the task
-     * is passed on to the stack rather than in R4 register. */
-    *pxTopOfStack = ( StackType_t ) ( pvParameters );
+    in some implementations of the compiler the parameter to the task
+    is passed on to the stack rather than in R4 register. */
+    *pxTopOfStack = (StackType_t)(pvParameters);
     pxTopOfStack--;
 
     *pxTopOfStack = ( StackType_t ) 0x00000000; /* RP */
@@ -136,36 +134,36 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
     pxTopOfStack--;
 
     /* In the current implementation of the compiler the first
-     * parameter to the task (or function) is passed via R4 parameter
-     * to the task, hence the pvParameters pointer is copied into the R4
-     * register. See compiler manual section 4.6.2 for more information. */
-    *pxTopOfStack = ( StackType_t ) ( pvParameters ); /* R4 */
+    parameter to the task (or function) is passed via R4 parameter
+    to the task, hence the pvParameters pointer is copied into the R4
+    register. See compiler manual section 4.6.2 for more information. */
+    *pxTopOfStack = ( StackType_t ) (pvParameters); /* R4 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x00003333;       /* R3 */
+    *pxTopOfStack = ( StackType_t ) 0x00003333; /* R3 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x00002222;       /* R2 */
+    *pxTopOfStack = ( StackType_t ) 0x00002222; /* R2 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x00001111;       /* R1 */
+    *pxTopOfStack = ( StackType_t ) 0x00001111; /* R1 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x00000001;       /* R0 */
+    *pxTopOfStack = ( StackType_t ) 0x00000001; /* R0 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x0000EEEE;       /* R14 */
+    *pxTopOfStack = ( StackType_t ) 0x0000EEEE; /* R14 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x0000DDDD;       /* R13 */
+    *pxTopOfStack = ( StackType_t ) 0x0000DDDD; /* R13 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x0000CCCC;       /* R12 */
+    *pxTopOfStack = ( StackType_t ) 0x0000CCCC; /* R12 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x0000BBBB;       /* R11 */
+    *pxTopOfStack = ( StackType_t ) 0x0000BBBB; /* R11 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x0000AAAA;       /* R10 */
+    *pxTopOfStack = ( StackType_t ) 0x0000AAAA; /* R10 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x00009999;       /* R9 */
+    *pxTopOfStack = ( StackType_t ) 0x00009999; /* R9 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x00008888;       /* R8 */
+    *pxTopOfStack = ( StackType_t ) 0x00008888; /* R8 */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x11110000;       /* MDH */
+    *pxTopOfStack = ( StackType_t ) 0x11110000; /* MDH */
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0x22220000;       /* MDL */
+    *pxTopOfStack = ( StackType_t ) 0x22220000; /* MDL */
     pxTopOfStack--;
 
     /* The start of the task code. */
@@ -190,8 +188,8 @@ BaseType_t xPortStartScheduler( void )
     #pragma endasm
 
     /* Simulate a function call end as generated by the compiler.  We will now
-     * jump to the start of the task the context of which we have just restored. */
-    __asm( " reti " );
+    jump to the start of the task the context of which we have just restored. */
+    __asm(" reti ");
 
     /* Should not get here. */
     return pdFAIL;
@@ -201,39 +199,39 @@ BaseType_t xPortStartScheduler( void )
 void vPortEndScheduler( void )
 {
     /* Not implemented - unlikely to ever be required as there is nothing to
-     * return to. */
+    return to. */
 }
 /*-----------------------------------------------------------*/
 
 static void prvSetupTimerInterrupt( void )
 {
 /* The peripheral clock divided by 32 is used by the timer. */
-    const uint16_t usReloadValue = ( uint16_t ) ( ( ( configPER_CLOCK_HZ / configTICK_RATE_HZ ) / 32UL ) - 1UL );
+const uint16_t usReloadValue = ( uint16_t ) ( ( ( configPER_CLOCK_HZ / configTICK_RATE_HZ ) / 32UL ) - 1UL );
 
     /* Setup RLT0 to generate a tick interrupt. */
 
-    TMCSR0_CNTE = 0;  /* Count Disable */
-    TMCSR0_CSL = 0x2; /* CLKP/32 */
-    TMCSR0_MOD = 0;   /* Software trigger */
-    TMCSR0_RELD = 1;  /* Reload */
+    TMCSR0_CNTE = 0;        /* Count Disable */
+    TMCSR0_CSL = 0x2;       /* CLKP/32 */
+    TMCSR0_MOD = 0;         /* Software trigger */
+    TMCSR0_RELD = 1;        /* Reload */
 
-    TMCSR0_UF = 0;    /* Clear underflow flag */
+    TMCSR0_UF = 0;          /* Clear underflow flag */
     TMRLR0 = usReloadValue;
-    TMCSR0_INTE = 1;  /* Interrupt Enable */
-    TMCSR0_CNTE = 1;  /* Count Enable */
-    TMCSR0_TRG = 1;   /* Trigger */
+    TMCSR0_INTE = 1;        /* Interrupt Enable */
+    TMCSR0_CNTE = 1;        /* Count Enable */
+    TMCSR0_TRG = 1;         /* Trigger */
 
-    PORTEN = 0x3;     /* Port Enable */
+    PORTEN = 0x3;           /* Port Enable */
 }
 /*-----------------------------------------------------------*/
 
 #if configUSE_PREEMPTION == 1
 
-/*
- * Tick ISR for preemptive scheduler. The tick count is incremented
- * after the context is saved. Then the context is switched if required,
- * and last the context of the task which is to be resumed is restored.
- */
+    /*
+     * Tick ISR for preemptive scheduler. The tick count is incremented
+     * after the context is saved. Then the context is switched if required,
+     * and last the context of the task which is to be resumed is restored.
+     */
 
     #pragma asm
 
@@ -259,13 +257,13 @@ static void prvSetupTimerInterrupt( void )
 
     #pragma endasm
 
-#else /* if configUSE_PREEMPTION == 1 */
+#else
 
-/*
- * Tick ISR for the cooperative scheduler.  All this does is increment the
- * tick count.  We don't need to switch context, this can only be done by
- * manual calls to taskYIELD();
- */
+    /*
+     * Tick ISR for the cooperative scheduler.  All this does is increment the
+     * tick count.  We don't need to switch context, this can only be done by
+     * manual calls to taskYIELD();
+     */
     __interrupt void ReloadTimer0_IRQHandler( void )
     {
         /* Clear RLT0 interrupt flag */
@@ -273,7 +271,7 @@ static void prvSetupTimerInterrupt( void )
         xTaskIncrementTick();
     }
 
-#endif /* if configUSE_PREEMPTION == 1 */
+#endif
 
 /*
  * Manual context switch. We can use a __nosavereg attribute  as the context
diff --git a/portable/Softune/MB91460/portmacro.h b/portable/Softune/MB91460/portmacro.h
index a80760b88..9ae6959c4 100644
--- a/portable/Softune/MB91460/portmacro.h
+++ b/portable/Softune/MB91460/portmacro.h
@@ -46,24 +46,24 @@
  */
 
 /* Type definitions. */
-#define portCHAR          char
-#define portFLOAT         float
-#define portDOUBLE        double
-#define portLONG          long
-#define portSHORT         short
-#define portSTACK_TYPE    uint32_t
-#define portBASE_TYPE     long
+#define portCHAR        char
+#define portFLOAT       float
+#define portDOUBLE      double
+#define portLONG        long
+#define portSHORT       short
+#define portSTACK_TYPE  uint32_t
+#define portBASE_TYPE   long
 
-typedef portSTACK_TYPE   StackType_t;
-typedef long             BaseType_t;
-typedef unsigned long    UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
 
 
-#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t     TickType_t;
-    #define portMAX_DELAY    ( TickType_t ) 0xffff
-#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t     TickType_t;
+#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t TickType_t;
+    #define portMAX_DELAY ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS  == TICK_TYPE_WIDTH_32_BITS )
+    typedef uint32_t             TickType_t;
     #define portMAX_DELAY    ( TickType_t ) 0xffffffffUL
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -74,38 +74,38 @@ typedef unsigned long    UBaseType_t;
 #if configKERNEL_INTERRUPT_PRIORITY != 30
     #error configKERNEL_INTERRUPT_PRIORITY (set in FreeRTOSConfig.h) must match the ILM value set in the following line - 30 (1Eh) being the default.
 #endif
-#define portDISABLE_INTERRUPTS()    __asm( " STILM #1Eh " )
-#define portENABLE_INTERRUPTS()     __asm( " STILM #1Fh " )
+#define portDISABLE_INTERRUPTS() __asm(" STILM #1Eh ")
+#define portENABLE_INTERRUPTS() __asm(" STILM #1Fh ")
 
-#define portENTER_CRITICAL()   \
-    __asm( " ST PS,@-R15 " );  \
-    __asm( " ANDCCR #0xef " ); \
+#define portENTER_CRITICAL()    \
+    __asm(" ST PS,@-R15 ");     \
+    __asm(" ANDCCR #0xef ");    \
 
 
-#define portEXIT_CRITICAL()   \
-    __asm( " LD @R15+,PS " ); \
+#define portEXIT_CRITICAL()     \
+    __asm(" LD @R15+,PS ");     \
 
 /*-----------------------------------------------------------*/
 
 /* Architecture specifics. */
-#define portSTACK_GROWTH      ( -1 )
-#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT    4
-#define portNOP()    __asm( " nop " );
+#define portSTACK_GROWTH            ( -1 )
+#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT          4
+#define portNOP()                   __asm( " nop " );
 /*-----------------------------------------------------------*/
 
 /* portYIELD() uses a SW interrupt */
-#define portYIELD()             __asm( " INT #40H " );
+#define portYIELD()                 __asm( " INT #40H " );
 
 /* portYIELD_FROM_ISR() uses delayed interrupt */
-#define portYIELD_FROM_ISR()    DICR_DLYI = 1
+#define portYIELD_FROM_ISR()            DICR_DLYI = 1
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
 
-#define portMINIMAL_STACK_SIZE    configMINIMAL_STACK_SIZE
+#define portMINIMAL_STACK_SIZE configMINIMAL_STACK_SIZE
 
 
 #endif /* PORTMACRO_H */
diff --git a/portable/Softune/MB96340/__STD_LIB_sbrk.c b/portable/Softune/MB96340/__STD_LIB_sbrk.c
index 0be354fec..d328a65fc 100644
--- a/portable/Softune/MB96340/__STD_LIB_sbrk.c
+++ b/portable/Softune/MB96340/__STD_LIB_sbrk.c
@@ -30,29 +30,26 @@
 /* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */
 /* ELIGIBILITY FOR ANY PURPOSES.                                             */
 /*                 (C) Fujitsu Microelectronics Europe GmbH                  */
-
 /*---------------------------------------------------------------------------
- * __STD_LIB_sbrk.C
- * - Used by heap_3.c for memory allocation and deletion.
- *
- * /*---------------------------------------------------------------------------*/
+  __STD_LIB_sbrk.C
+  - Used by heap_3.c for memory allocation and deletion.
+
+/*---------------------------------------------------------------------------*/
 
 #include "FreeRTOSConfig.h"
 #include <stdlib.h>
 
-static long brk_siz = 0;
-typedef int _heep_t;
-#define ROUNDUP( s )    ( ( ( s ) + sizeof( _heep_t ) - 1 ) & ~( sizeof( _heep_t ) - 1 ) )
-static _heep_t _heep[ ROUNDUP( configTOTAL_HEAP_SIZE ) / sizeof( _heep_t ) ];
-#define              _heep_size    ROUNDUP( configTOTAL_HEAP_SIZE )
+    static  long         brk_siz  =  0;
+    typedef int          _heep_t;
+    #define ROUNDUP(s)   (((s)+sizeof(_heep_t)-1)&~(sizeof(_heep_t)-1))
+    static  _heep_t      _heep[ROUNDUP(configTOTAL_HEAP_SIZE)/sizeof(_heep_t)];
+    #define              _heep_size      ROUNDUP(configTOTAL_HEAP_SIZE)
 
-extern char * sbrk( int size )
-{
-    if( ( brk_siz + size > _heep_size ) || ( brk_siz + size < 0 ) )
+    extern  char  *sbrk(int  size)
     {
-        return( ( char * ) -1 );
-    }
+       if  (brk_siz  +  size  >  _heep_size  ||  brk_siz  +  size  <  0)
 
-    brk_siz += size;
-    return( ( char * ) _heep + brk_siz - size );
-}
+          return((char*)-1);
+       brk_siz  +=  size;
+       return(  (char*)_heep  +  brk_siz  -  size);
+    }
diff --git a/portable/Softune/MB96340/port.c b/portable/Softune/MB96340/port.c
index 21d2cc14d..aef0d65a9 100644
--- a/portable/Softune/MB96340/port.c
+++ b/portable/Softune/MB96340/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -30,8 +30,8 @@
 #include "task.h"
 
 /*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the 16FX port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the 16FX port.
+ *----------------------------------------------------------*/
 
 /*
  * Get current value of DPR and ADB registers
@@ -44,7 +44,7 @@ StackType_t xGet_DPR_ADB_bank( void );
 StackType_t xGet_DTB_PCB_bank( void );
 
 /*
- * Sets up the periodic ISR used for the RTOS tick. This uses RLT0, but
+ * Sets up the periodic ISR used for the RTOS tick.  This uses RLT0, but
  * can be done using any given RLT.
  */
 static void prvSetupRLT0Interrupt( void );
@@ -61,164 +61,164 @@ extern volatile TCB_t * volatile pxCurrentTCB;
 /*-----------------------------------------------------------*/
 
 /*
- * Macro to save a task context to the task stack. This macro copies the
- * saved context (AH:AL, DPR:ADB, DTB:PCB , PC and PS) from the system
- * stack to task stack pointed by user stack pointer ( USP for SMALL and
- * MEDIUM memory model amd USB:USP for COMPACT and LARGE memory model ),
- * then it pushes the general purpose registers RW0-RW7 on to the task
- * stack. Finally the resultant stack pointer value is saved into the
- * task control block so it can be retrieved the next time the task
+ * Macro to save a task context to the task stack. This macro  copies the
+ * saved context (AH:AL, DPR:ADB, DTB:PCB , PC and PS) from  the   system
+ * stack to task stack pointed by user stack pointer ( USP  for SMALL and
+ * MEDIUM memory model amd USB:USP for COMPACT  and LARGE memory model ),
+ * then  it pushes the general purpose registers RW0-RW7  on  to the task
+ * stack. Finally the  resultant  stack  pointer  value is saved into the
+ * task  control  block  so  it  can  be retrieved the next time the task
  * executes.
  */
-#if ( ( configMEMMODEL == portSMALL ) || ( configMEMMODEL == portMEDIUM ) )
+#if( ( configMEMMODEL == portSMALL ) || ( configMEMMODEL == portMEDIUM ) )
 
-    #define portSAVE_CONTEXT()                              \
-    { __asm( " POPW  A " );                                 \
-      __asm( " AND  CCR,#H'DF " );                          \
-      __asm( " PUSHW  A " );                                \
-      __asm( " OR   CCR,#H'20 " );                          \
-      __asm( " POPW  A " );                                 \
-      __asm( " AND  CCR,#H'DF " );                          \
-      __asm( " PUSHW  A " );                                \
-      __asm( " OR   CCR,#H'20 " );                          \
-      __asm( " POPW  A " );                                 \
-      __asm( " AND  CCR,#H'DF " );                          \
-      __asm( " PUSHW  A " );                                \
-      __asm( " OR   CCR,#H'20 " );                          \
-      __asm( " POPW  A " );                                 \
-      __asm( " AND  CCR,#H'DF " );                          \
-      __asm( " PUSHW  A " );                                \
-      __asm( " OR   CCR,#H'20 " );                          \
-      __asm( " POPW  A " );                                 \
-      __asm( " AND  CCR,#H'DF " );                          \
-      __asm( " PUSHW  A " );                                \
-      __asm( " OR   CCR,#H'20 " );                          \
-      __asm( " POPW  A " );                                 \
-      __asm( " AND  CCR,#H'DF " );                          \
-      __asm( " PUSHW  A " );                                \
-      __asm( " PUSHW (RW0,RW1,RW2,RW3,RW4,RW5,RW6,RW7) " ); \
-      __asm( " MOVW A, _pxCurrentTCB " );                   \
-      __asm( " MOVW A, SP " );                              \
-      __asm( " SWAPW " );                                   \
-      __asm( " MOVW @AL, AH " );                            \
-      __asm( " OR   CCR,#H'20 " );                          \
-    }
+    #define portSAVE_CONTEXT()                                          \
+            {   __asm(" POPW  A ");                                     \
+                __asm(" AND  CCR,#H'DF ");                              \
+                __asm(" PUSHW  A ");                                    \
+                __asm(" OR   CCR,#H'20 ");                              \
+                __asm(" POPW  A ");                                     \
+                __asm(" AND  CCR,#H'DF ");                              \
+                __asm(" PUSHW  A ");                                    \
+                __asm(" OR   CCR,#H'20 ");                              \
+                __asm(" POPW  A ");                                     \
+                __asm(" AND  CCR,#H'DF ");                              \
+                __asm(" PUSHW  A ");                                    \
+                __asm(" OR   CCR,#H'20 ");                              \
+                __asm(" POPW  A ");                                     \
+                __asm(" AND  CCR,#H'DF ");                              \
+                __asm(" PUSHW  A ");                                    \
+                __asm(" OR   CCR,#H'20 ");                              \
+                __asm(" POPW  A ");                                     \
+                __asm(" AND  CCR,#H'DF ");                              \
+                __asm(" PUSHW  A ");                                    \
+                __asm(" OR   CCR,#H'20 ");                              \
+                __asm(" POPW  A ");                                     \
+                __asm(" AND  CCR,#H'DF ");                              \
+                __asm(" PUSHW  A ");                                    \
+                __asm(" PUSHW (RW0,RW1,RW2,RW3,RW4,RW5,RW6,RW7) ");     \
+                __asm(" MOVW A, _pxCurrentTCB ");                       \
+                __asm(" MOVW A, SP ");                                  \
+                __asm(" SWAPW ");                                       \
+                __asm(" MOVW @AL, AH ");                                \
+                __asm(" OR   CCR,#H'20 ");                              \
+            }
 
 /*
  * Macro to restore a task context from the task stack. This is
  * effectively the reverse of SAVE_CONTEXT(). First the stack pointer
  * value (USP for SMALL and MEDIUM memory model amd USB:USP for COMPACT
- * and LARGE memory model ) is loaded from the task control block. Next the
- * value of all the general purpose registers RW0-RW7 is retrieved.
+ * and LARGE memory model ) is loaded from the task  control block. Next
+ * the value of all the general purpose registers RW0-RW7 is retrieved.
  * Finally it copies of the context ( AH:AL, DPR:ADB, DTB:PCB, PC and PS)
  * of the task to be executed upon RETI from user stack to system stack.
  */
 
-    #define portRESTORE_CONTEXT()                          \
-    { __asm( " MOVW A, _pxCurrentTCB " );                  \
-      __asm( " MOVW A, @A " );                             \
-      __asm( " AND  CCR,#H'DF " );                         \
-      __asm( " MOVW SP, A " );                             \
-      __asm( " POPW (RW0,RW1,RW2,RW3,RW4,RW5,RW6,RW7) " ); \
-      __asm( " POPW  A " );                                \
-      __asm( " OR   CCR,#H'20 " );                         \
-      __asm( " PUSHW  A " );                               \
-      __asm( " AND  CCR,#H'DF " );                         \
-      __asm( " POPW  A " );                                \
-      __asm( " OR   CCR,#H'20 " );                         \
-      __asm( " PUSHW  A " );                               \
-      __asm( " AND  CCR,#H'DF " );                         \
-      __asm( " POPW  A " );                                \
-      __asm( " OR   CCR,#H'20 " );                         \
-      __asm( " PUSHW  A " );                               \
-      __asm( " AND  CCR,#H'DF " );                         \
-      __asm( " POPW  A " );                                \
-      __asm( " OR   CCR,#H'20 " );                         \
-      __asm( " PUSHW  A " );                               \
-      __asm( " AND  CCR,#H'DF " );                         \
-      __asm( " POPW  A " );                                \
-      __asm( " OR   CCR,#H'20 " );                         \
-      __asm( " PUSHW  A " );                               \
-      __asm( " AND  CCR,#H'DF " );                         \
-      __asm( " POPW  A " );                                \
-      __asm( " OR   CCR,#H'20 " );                         \
-      __asm( " PUSHW  A " );                               \
-    }
+    #define portRESTORE_CONTEXT()                                       \
+            {   __asm(" MOVW A, _pxCurrentTCB ");                       \
+                __asm(" MOVW A, @A ");                                  \
+                __asm(" AND  CCR,#H'DF ");                              \
+                __asm(" MOVW SP, A ");                                  \
+                __asm(" POPW (RW0,RW1,RW2,RW3,RW4,RW5,RW6,RW7) ");      \
+                __asm(" POPW  A ");                                     \
+                __asm(" OR   CCR,#H'20 ");                              \
+                __asm(" PUSHW  A ");                                    \
+                __asm(" AND  CCR,#H'DF ");                              \
+                __asm(" POPW  A ");                                     \
+                __asm(" OR   CCR,#H'20 ");                              \
+                __asm(" PUSHW  A ");                                    \
+                __asm(" AND  CCR,#H'DF ");                              \
+                __asm(" POPW  A ");                                     \
+                __asm(" OR   CCR,#H'20 ");                              \
+                __asm(" PUSHW  A ");                                    \
+                __asm(" AND  CCR,#H'DF ");                              \
+                __asm(" POPW  A ");                                     \
+                __asm(" OR   CCR,#H'20 ");                              \
+                __asm(" PUSHW  A ");                                    \
+                __asm(" AND  CCR,#H'DF ");                              \
+                __asm(" POPW  A ");                                     \
+                __asm(" OR   CCR,#H'20 ");                              \
+                __asm(" PUSHW  A ");                                    \
+                __asm(" AND  CCR,#H'DF ");                              \
+                __asm(" POPW  A ");                                     \
+                __asm(" OR   CCR,#H'20 ");                              \
+                __asm(" PUSHW  A ");                                    \
+            }
 
-#elif ( ( configMEMMODEL == portCOMPACT ) || ( configMEMMODEL == portLARGE ) )
+#elif( ( configMEMMODEL == portCOMPACT ) || ( configMEMMODEL == portLARGE ) )
 
-    #define portSAVE_CONTEXT()                              \
-    { __asm( " POPW  A " );                                 \
-      __asm( " AND  CCR,#H'DF " );                          \
-      __asm( " PUSHW  A " );                                \
-      __asm( " OR   CCR,#H'20 " );                          \
-      __asm( " POPW  A " );                                 \
-      __asm( " AND  CCR,#H'DF " );                          \
-      __asm( " PUSHW  A " );                                \
-      __asm( " OR   CCR,#H'20 " );                          \
-      __asm( " POPW  A " );                                 \
-      __asm( " AND  CCR,#H'DF " );                          \
-      __asm( " PUSHW  A " );                                \
-      __asm( " OR   CCR,#H'20 " );                          \
-      __asm( " POPW  A " );                                 \
-      __asm( " AND  CCR,#H'DF " );                          \
-      __asm( " PUSHW  A " );                                \
-      __asm( " OR   CCR,#H'20 " );                          \
-      __asm( " POPW  A " );                                 \
-      __asm( " AND  CCR,#H'DF " );                          \
-      __asm( " PUSHW  A " );                                \
-      __asm( " OR   CCR,#H'20 " );                          \
-      __asm( " POPW  A " );                                 \
-      __asm( " AND  CCR,#H'DF " );                          \
-      __asm( " PUSHW  A " );                                \
-      __asm( " PUSHW (RW0,RW1,RW2,RW3,RW4,RW5,RW6,RW7) " ); \
-      __asm( " MOVL A, _pxCurrentTCB " );                   \
-      __asm( " MOVL RL2, A " );                             \
-      __asm( " MOVW A, SP " );                              \
-      __asm( " MOVW @RL2+0, A " );                          \
-      __asm( " MOV A, USB " );                              \
-      __asm( " MOV @RL2+2, A " );                           \
-    }
+    #define portSAVE_CONTEXT()                                          \
+            {   __asm(" POPW  A ");                                     \
+                __asm(" AND  CCR,#H'DF ");                              \
+                __asm(" PUSHW  A ");                                    \
+                __asm(" OR   CCR,#H'20 ");                              \
+                __asm(" POPW  A ");                                     \
+                __asm(" AND  CCR,#H'DF ");                              \
+                __asm(" PUSHW  A ");                                    \
+                __asm(" OR   CCR,#H'20 ");                              \
+                __asm(" POPW  A ");                                     \
+                __asm(" AND  CCR,#H'DF ");                              \
+                __asm(" PUSHW  A ");                                    \
+                __asm(" OR   CCR,#H'20 ");                              \
+                __asm(" POPW  A ");                                     \
+                __asm(" AND  CCR,#H'DF ");                              \
+                __asm(" PUSHW  A ");                                    \
+                __asm(" OR   CCR,#H'20 ");                              \
+                __asm(" POPW  A ");                                     \
+                __asm(" AND  CCR,#H'DF ");                              \
+                __asm(" PUSHW  A ");                                    \
+                __asm(" OR   CCR,#H'20 ");                              \
+                __asm(" POPW  A ");                                     \
+                __asm(" AND  CCR,#H'DF ");                              \
+                __asm(" PUSHW  A ");                                    \
+                __asm(" PUSHW (RW0,RW1,RW2,RW3,RW4,RW5,RW6,RW7) ");     \
+                __asm(" MOVL A, _pxCurrentTCB ");                       \
+                __asm(" MOVL RL2, A ");                                 \
+                __asm(" MOVW A, SP ");                                  \
+                __asm(" MOVW @RL2+0, A ");                              \
+                __asm(" MOV A, USB ");                                  \
+                __asm(" MOV @RL2+2, A ");                               \
+            }
 
-    #define portRESTORE_CONTEXT()                          \
-    { __asm( " MOVL A, _pxCurrentTCB " );                  \
-      __asm( " MOVL RL2, A " );                            \
-      __asm( " MOVW A, @RL2+0 " );                         \
-      __asm( " AND  CCR,#H'DF " );                         \
-      __asm( " MOVW SP, A " );                             \
-      __asm( " MOV A, @RL2+2 " );                          \
-      __asm( " MOV USB, A " );                             \
-      __asm( " POPW (RW0,RW1,RW2,RW3,RW4,RW5,RW6,RW7) " ); \
-      __asm( " POPW  A " );                                \
-      __asm( " OR   CCR,#H'20 " );                         \
-      __asm( " PUSHW  A " );                               \
-      __asm( " AND  CCR,#H'DF " );                         \
-      __asm( " POPW  A " );                                \
-      __asm( " OR   CCR,#H'20 " );                         \
-      __asm( " PUSHW  A " );                               \
-      __asm( " AND  CCR,#H'DF " );                         \
-      __asm( " POPW  A " );                                \
-      __asm( " OR   CCR,#H'20 " );                         \
-      __asm( " PUSHW  A " );                               \
-      __asm( " AND  CCR,#H'DF " );                         \
-      __asm( " POPW  A " );                                \
-      __asm( " OR   CCR,#H'20 " );                         \
-      __asm( " PUSHW  A " );                               \
-      __asm( " AND  CCR,#H'DF " );                         \
-      __asm( " POPW  A " );                                \
-      __asm( " OR   CCR,#H'20 " );                         \
-      __asm( " PUSHW  A " );                               \
-      __asm( " AND  CCR,#H'DF " );                         \
-      __asm( " POPW  A " );                                \
-      __asm( " OR   CCR,#H'20 " );                         \
-      __asm( " PUSHW  A " );                               \
-    }
-#endif /* if ( ( configMEMMODEL == portSMALL ) || ( configMEMMODEL == portMEDIUM ) ) */
+    #define portRESTORE_CONTEXT()                                       \
+            {   __asm(" MOVL A, _pxCurrentTCB ");                       \
+                __asm(" MOVL RL2, A ");                                 \
+                __asm(" MOVW A, @RL2+0 ");                              \
+                __asm(" AND  CCR,#H'DF ");                              \
+                __asm(" MOVW SP, A ");                                  \
+                __asm(" MOV A, @RL2+2 ");                               \
+                __asm(" MOV USB, A ");                                  \
+                __asm(" POPW (RW0,RW1,RW2,RW3,RW4,RW5,RW6,RW7) ");      \
+                __asm(" POPW  A ");                                     \
+                __asm(" OR   CCR,#H'20 ");                              \
+                __asm(" PUSHW  A ");                                    \
+                __asm(" AND  CCR,#H'DF ");                              \
+                __asm(" POPW  A ");                                     \
+                __asm(" OR   CCR,#H'20 ");                              \
+                __asm(" PUSHW  A ");                                    \
+                __asm(" AND  CCR,#H'DF ");                              \
+                __asm(" POPW  A ");                                     \
+                __asm(" OR   CCR,#H'20 ");                              \
+                __asm(" PUSHW  A ");                                    \
+                __asm(" AND  CCR,#H'DF ");                              \
+                __asm(" POPW  A ");                                     \
+                __asm(" OR   CCR,#H'20 ");                              \
+                __asm(" PUSHW  A ");                                    \
+                __asm(" AND  CCR,#H'DF ");                              \
+                __asm(" POPW  A ");                                     \
+                __asm(" OR   CCR,#H'20 ");                              \
+                __asm(" PUSHW  A ");                                    \
+                __asm(" AND  CCR,#H'DF ");                              \
+                __asm(" POPW  A ");                                     \
+                __asm(" OR   CCR,#H'20 ");                              \
+                __asm(" PUSHW  A ");                                    \
+            }
+#endif
 
 /*-----------------------------------------------------------*/
 
 /*
- * Functions for obtaining the current value of DPR:ADB, DTB:PCB bank registers
+ * Functions for obtaining the current value  of  DPR:ADB, DTB:PCB bank registers
  */
 
 #pragma asm
@@ -261,12 +261,10 @@ _xGet_DTB_PCB_bank:
  *
  * See the header file portable.h.
  */
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
 {
     /* Place a few bytes of known values on the bottom of the stack.
-     * This is just useful for debugging. */
+    This is just useful for debugging. */
     *pxTopOfStack = 0x1111;
     pxTopOfStack--;
     *pxTopOfStack = 0x2222;
@@ -274,12 +272,12 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
     *pxTopOfStack = 0x3333;
     pxTopOfStack--;
 
-    /* Once the task is called the task would push the pointer to the
-     * parameter onto the stack. Hence here the pointer would be copied to the stack
-     * first. When using the COMPACT or LARGE memory model the pointer would be 24
-     * bits, and when using the SMALL or MEDIUM memory model the pointer would be 16
-     * bits. */
-    #if ( ( configMEMMODEL == portCOMPACT ) || ( configMEMMODEL == portLARGE ) )
+    /* Once the task is called the task  would  push  the  pointer to the
+    parameter onto the stack. Hence here the pointer would be copied to the stack
+    first.  When using the COMPACT or LARGE memory model the pointer would be 24
+    bits, and when using the SMALL or MEDIUM memory model the pointer would be 16
+    bits. */
+    #if( ( configMEMMODEL == portCOMPACT ) || ( configMEMMODEL == portLARGE ) )
     {
         *pxTopOfStack = ( StackType_t ) ( ( uint32_t ) ( pvParameters ) >> 16 );
         pxTopOfStack--;
@@ -290,9 +288,9 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
     pxTopOfStack--;
 
     /* This is redundant push to the stack. This is required in order to introduce
-     * an offset so that the task accesses a parameter correctly that is passed on to
-     * the task stack. */
-    #if ( ( configMEMMODEL == portMEDIUM ) || ( configMEMMODEL == portLARGE ) )
+    an offset so that the task accesses a parameter correctly that is passed on to
+    the task stack. */
+    #if( ( configMEMMODEL == portMEDIUM ) || ( configMEMMODEL == portLARGE ) )
     {
         *pxTopOfStack = ( xGet_DTB_PCB_bank() & 0xff00 ) | ( ( ( int32_t ) ( pxCode ) >> 16 ) & 0xff );
         pxTopOfStack--;
@@ -300,7 +298,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
     #endif
 
     /* This is redundant push to the stack. This is required in order to introduce
-     * an offset so the task correctly accesses the parameter passed on the task stack. */
+    an offset so the task correctly accesses the parameter passed on the task stack. */
     *pxTopOfStack = ( StackType_t ) ( pxCode );
     pxTopOfStack--;
 
@@ -321,15 +319,15 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
     #endif
 
     /* DTB | PCB, in case of MEDIUM and LARGE memory models, PCB would be used
-     * along with PC to indicate the start address of the function. */
-    #if ( ( configMEMMODEL == portMEDIUM ) || ( configMEMMODEL == portLARGE ) )
+    along with PC to indicate the start address of the function. */
+    #if( ( configMEMMODEL == portMEDIUM ) || ( configMEMMODEL == portLARGE ) )
     {
         *pxTopOfStack = ( xGet_DTB_PCB_bank() & 0xff00 ) | ( ( ( int32_t ) ( pxCode ) >> 16 ) & 0xff );
         pxTopOfStack--;
     }
     #endif
 
-    /* DPR | ADB */
+    /* DPR | ADB  */
     *pxTopOfStack = xGet_DPR_ADB_bank();
     pxTopOfStack--;
 
@@ -365,7 +363,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
 static void prvSetupRLT0Interrupt( void )
 {
 /* The peripheral clock divided by 16 is used by the timer. */
-    const uint16_t usReloadValue = ( uint16_t ) ( ( ( configCLKP1_CLOCK_HZ / configTICK_RATE_HZ ) / 16UL ) - 1UL );
+const uint16_t usReloadValue = ( uint16_t ) ( ( ( configCLKP1_CLOCK_HZ / configTICK_RATE_HZ ) / 16UL ) - 1UL );
 
     /* set reload value = 34999+1, TICK Interrupt after 10 ms @ 56MHz of CLKP1 */
     TMRLR0 = usReloadValue;
@@ -383,9 +381,9 @@ BaseType_t xPortStartScheduler( void )
     /* Restore the context of the first task that is going to run. */
     portRESTORE_CONTEXT();
 
-    /* Simulate a function call end as generated by the compiler. We will now
-     * jump to the start of the task the context of which we have just restored. */
-    __asm( " reti " );
+    /* Simulate a function call end as generated by the compiler.  We will now
+    jump to the start of the task the context of which we have just restored. */
+    __asm(" reti ");
 
 
     /* Should not get here. */
@@ -396,7 +394,7 @@ BaseType_t xPortStartScheduler( void )
 void vPortEndScheduler( void )
 {
     /* Not implemented - unlikely to ever be required as there is nothing to
-     * return to. */
+    return to. */
 }
 
 /*-----------------------------------------------------------*/
@@ -408,12 +406,12 @@ void vPortEndScheduler( void )
 
 #if configUSE_PREEMPTION == 1
 
-/*
- * Tick ISR for preemptive scheduler. We can use a __nosavereg attribute
- * as the context is to be saved by the portSAVE_CONTEXT() macro, not the
- * compiler generated code. The tick count is incremented after the context
- * is saved.
- */
+    /*
+     * Tick ISR for preemptive scheduler.  We can use a __nosavereg attribute
+     * as the context is to be saved by the portSAVE_CONTEXT() macro, not the
+     * compiler generated code.  The tick count is incremented after the context
+     * is saved.
+     */
     __nosavereg __interrupt void prvRLT0_TICKISR( void )
     {
         /* Disable interrupts so that portSAVE_CONTEXT() is not interrupted */
@@ -429,7 +427,7 @@ void vPortEndScheduler( void )
         TMCSR0_UF = 0;
 
         /* Increment the tick count then switch to the highest priority task
-         * that is ready to run. */
+        that is ready to run. */
         if( xTaskIncrementTick() != pdFALSE )
         {
             vTaskSwitchContext();
@@ -445,13 +443,13 @@ void vPortEndScheduler( void )
         __EI();
     }
 
-#else /* if configUSE_PREEMPTION == 1 */
+#else
 
-/*
- * Tick ISR for the cooperative scheduler. All this does is increment the
- * tick count. We don't need to switch context, this can only be done by
- * manual calls to taskYIELD();
- */
+    /*
+     * Tick ISR for the cooperative scheduler.  All this does is increment the
+     * tick count.  We don't need to switch context, this can only be done by
+     * manual calls to taskYIELD();
+     */
     __interrupt void prvRLT0_TICKISR( void )
     {
         /* Clear RLT0 interrupt flag */
@@ -460,12 +458,12 @@ void vPortEndScheduler( void )
         xTaskIncrementTick();
     }
 
-#endif /* if configUSE_PREEMPTION == 1 */
+#endif
 
 /*-----------------------------------------------------------*/
 
 /*
- * Manual context switch. We can use a __nosavereg attribute as the context
+ * Manual context switch. We can use a __nosavereg attribute  as the context
  * is to be saved by the portSAVE_CONTEXT() macro, not the compiler generated
  * code.
  */
@@ -494,7 +492,7 @@ __nosavereg __interrupt void vPortYieldDelayed( void )
     __EI();
 
     /* Clear delayed interrupt flag */
-    __asm( " CLRB  03A4H:0 " );
+    __asm (" CLRB  03A4H:0 ");
 
     /* Switch to the highest priority task that is ready to run. */
     vTaskSwitchContext();
diff --git a/portable/Softune/MB96340/portmacro.h b/portable/Softune/MB96340/portmacro.h
index 7f36aad59..827874fde 100644
--- a/portable/Softune/MB96340/portmacro.h
+++ b/portable/Softune/MB96340/portmacro.h
@@ -34,11 +34,11 @@
 #include <stddef.h>
 
 /* Constants denoting the available memory models.  These are used within
- * FreeRTOSConfig.h to set the configMEMMODEL value. */
-#define portSMALL      0
-#define portMEDIUM     1
-#define portCOMPACT    2
-#define portLARGE      3
+FreeRTOSConfig.h to set the configMEMMODEL value. */
+#define portSMALL     0
+#define portMEDIUM    1
+#define portCOMPACT   2
+#define portLARGE     3
 
 
 /*-----------------------------------------------------------
@@ -52,24 +52,24 @@
  */
 
 /* Type definitions. */
-#define portCHAR          char
-#define portFLOAT         float
-#define portDOUBLE        double
-#define portLONG          long
-#define portSHORT         short
-#define portSTACK_TYPE    uint16_t
-#define portBASE_TYPE     short
+#define portCHAR        char
+#define portFLOAT       float
+#define portDOUBLE      double
+#define portLONG        long
+#define portSHORT       short
+#define portSTACK_TYPE  uint16_t
+#define portBASE_TYPE   short
 
-typedef portSTACK_TYPE   StackType_t;
-typedef short            BaseType_t;
-typedef unsigned short   UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef short BaseType_t;
+typedef unsigned short UBaseType_t;
 
 
-#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t     TickType_t;
-    #define portMAX_DELAY    ( TickType_t ) 0xffff
-#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t     TickType_t;
+#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t TickType_t;
+    #define portMAX_DELAY ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS  == TICK_TYPE_WIDTH_32_BITS )
+    typedef uint32_t             TickType_t;
     #define portMAX_DELAY    ( TickType_t ) 0xffffffffUL
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -80,39 +80,39 @@ typedef unsigned short   UBaseType_t;
 #if configKERNEL_INTERRUPT_PRIORITY != 6
     #error configKERNEL_INTERRUPT_PRIORITY (set in FreeRTOSConfig.h) must match the ILM value set in the following line - #06H being the default.
 #endif
-#define portDISABLE_INTERRUPTS()    __asm( " MOV ILM, #06h " )
-#define portENABLE_INTERRUPTS()     __asm( " MOV ILM, #07h " )
+#define portDISABLE_INTERRUPTS()    __asm(" MOV ILM, #06h ")
+#define portENABLE_INTERRUPTS()     __asm(" MOV ILM, #07h ")
 
-#define portENTER_CRITICAL()    \
-    { __asm( " PUSHW PS " );    \
-      portDISABLE_INTERRUPTS(); \
-    }
+#define portENTER_CRITICAL()                                \
+        {   __asm(" PUSHW PS ");                            \
+            portDISABLE_INTERRUPTS();                       \
+        }
 
-#define portEXIT_CRITICAL() \
-    { __asm( " POPW PS " ); \
-    }
+#define portEXIT_CRITICAL()                                 \
+        {   __asm(" POPW PS ");                             \
+        }
 
 /*-----------------------------------------------------------*/
 
 /* Architecture specifics. */
-#define portSTACK_GROWTH      ( -1 )
-#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT    2
-#define portNOP()    __asm( " NOP " );
+#define portSTACK_GROWTH            ( -1 )
+#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT          2
+#define portNOP()                   __asm( " NOP " );
 /*-----------------------------------------------------------*/
 
 /* portYIELD() uses SW interrupt */
-#define portYIELD()             __asm( " INT #122 " );
+#define portYIELD()                 __asm( " INT #122 " );
 
 /* portYIELD_FROM_ISR() uses delayed interrupt */
-#define portYIELD_FROM_ISR()    __asm( " SETB  03A4H:0 " );
+#define portYIELD_FROM_ISR()         __asm( " SETB  03A4H:0 " );
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
 
-#define portMINIMAL_STACK_SIZE    configMINIMAL_STACK_SIZE
+#define portMINIMAL_STACK_SIZE configMINIMAL_STACK_SIZE
 
 
 #endif /* PORTMACRO_H */

From b3febb74166a061bd1efcefa2f5e34f2b2d5cba0 Mon Sep 17 00:00:00 2001
From: Soren Ptak <ptaksoren@gmail.com>
Date: Thu, 23 Nov 2023 03:51:23 -0800
Subject: [PATCH 119/424] Revert formatting on Tasking ports (#887)

Co-authored-by: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
---
 portable/Tasking/ARM_CM4F/port.c      | 30 +++++------
 portable/Tasking/ARM_CM4F/portmacro.h | 78 +++++++++++++--------------
 2 files changed, 54 insertions(+), 54 deletions(-)

diff --git a/portable/Tasking/ARM_CM4F/port.c b/portable/Tasking/ARM_CM4F/port.c
index bc01af91f..df79a9ac0 100644
--- a/portable/Tasking/ARM_CM4F/port.c
+++ b/portable/Tasking/ARM_CM4F/port.c
@@ -35,26 +35,26 @@
 #include "task.h"
 
 /* Constants required to manipulate the NVIC. */
-#define portNVIC_SYSTICK_CTRL         ( ( volatile uint32_t * ) 0xe000e010 )
-#define portNVIC_SYSTICK_LOAD         ( ( volatile uint32_t * ) 0xe000e014 )
-#define portNVIC_SHPR3_REG            ( ( volatile uint32_t * ) 0xe000ed20 )
-#define portNVIC_SYSTICK_CLK          0x00000004
-#define portNVIC_SYSTICK_INT          0x00000002
-#define portNVIC_SYSTICK_ENABLE       0x00000001
-#define portMIN_INTERRUPT_PRIORITY    ( 255UL )
-#define portNVIC_PENDSV_PRI           ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
-#define portNVIC_SYSTICK_PRI          ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
+#define portNVIC_SYSTICK_CTRL       ( ( volatile uint32_t * ) 0xe000e010 )
+#define portNVIC_SYSTICK_LOAD       ( ( volatile uint32_t * ) 0xe000e014 )
+#define portNVIC_SHPR3_REG          ( ( volatile uint32_t * ) 0xe000ed20 )
+#define portNVIC_SYSTICK_CLK        0x00000004
+#define portNVIC_SYSTICK_INT        0x00000002
+#define portNVIC_SYSTICK_ENABLE     0x00000001
+#define portMIN_INTERRUPT_PRIORITY  ( 255UL )
+#define portNVIC_PENDSV_PRI         ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI        ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
 
 /* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
-#define portVECTACTIVE_MASK           ( 0xFFUL )
+#define portVECTACTIVE_MASK         ( 0xFFUL )
 
 /* Constants required to manipulate the VFP. */
-#define portFPCCR                     ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
-#define portASPEN_AND_LSPEN_BITS      ( 0x3UL << 30UL )
+#define portFPCCR                   ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
+#define portASPEN_AND_LSPEN_BITS    ( 0x3UL << 30UL )
 
 /* Constants required to set up the initial stack. */
-#define portINITIAL_XPSR              ( 0x01000000 )
-#define portINITIAL_EXC_RETURN        ( 0xfffffffd )
+#define portINITIAL_XPSR            ( 0x01000000 )
+#define portINITIAL_EXC_RETURN      ( 0xfffffffd )
 
 /* Let the user override the pre-loading of the initial LR with the address of
  * prvTaskExitError() in case it messes up unwinding of the stack in the
@@ -272,4 +272,4 @@ void prvSetupTimerInterrupt( void )
     /* Configure SysTick to interrupt at the requested rate. */
     *( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
     *( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
-}
+}
\ No newline at end of file
diff --git a/portable/Tasking/ARM_CM4F/portmacro.h b/portable/Tasking/ARM_CM4F/portmacro.h
index 516d856d8..243e6856b 100644
--- a/portable/Tasking/ARM_CM4F/portmacro.h
+++ b/portable/Tasking/ARM_CM4F/portmacro.h
@@ -28,7 +28,7 @@
 
 
 #ifndef PORTMACRO_H
-#define PORTMACRO_H
+    #define PORTMACRO_H
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
@@ -47,38 +47,38 @@
  */
 
 /* Type definitions. */
-#define portCHAR          char
-#define portFLOAT         float
-#define portDOUBLE        double
-#define portLONG          long
-#define portSHORT         short
-#define portSTACK_TYPE    uint32_t
-#define portBASE_TYPE     long
+    #define portCHAR          char
+    #define portFLOAT         float
+    #define portDOUBLE        double
+    #define portLONG          long
+    #define portSHORT         short
+    #define portSTACK_TYPE    uint32_t
+    #define portBASE_TYPE     long
 
-typedef portSTACK_TYPE   StackType_t;
-typedef long             BaseType_t;
-typedef unsigned long    UBaseType_t;
+    typedef portSTACK_TYPE   StackType_t;
+    typedef long             BaseType_t;
+    typedef unsigned long    UBaseType_t;
 
 
-#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t     TickType_t;
-    #define portMAX_DELAY              ( TickType_t ) 0xffff
-#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t     TickType_t;
-    #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+    #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+        typedef uint16_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffff
+    #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+        typedef uint32_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
  * not need to be guarded with a critical section. */
-    #define portTICK_TYPE_IS_ATOMIC    1
-#else
-    #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
-#endif
+        #define portTICK_TYPE_IS_ATOMIC    1
+    #else
+        #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+    #endif
 /*-----------------------------------------------------------*/
 
 /* Architecture specifics. */
-#define portSTACK_GROWTH      ( -1 )
-#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT    8
+    #define portSTACK_GROWTH      ( -1 )
+    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+    #define portBYTE_ALIGNMENT    8
 /*-----------------------------------------------------------*/
 
 
@@ -111,36 +111,36 @@ extern void vPortYield( void );
  * Set basepri to portMAX_SYSCALL_INTERRUPT_PRIORITY without effecting other
  * registers.  r0 is clobbered.
  */
-#define portSET_INTERRUPT_MASK()      __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+    #define portSET_INTERRUPT_MASK()      __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY )
 
 /*
  * Set basepri back to 0 without effective other registers.
  * r0 is clobbered.  FAQ:  Setting BASEPRI to 0 is not a bug.  Please see
  * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing.
  */
-#define portCLEAR_INTERRUPT_MASK()    __set_BASEPRI( 0 )
+    #define portCLEAR_INTERRUPT_MASK()    __set_BASEPRI( 0 )
 
-extern uint32_t ulPortSetInterruptMask( void );
-extern void vPortClearInterruptMask( uint32_t ulNewMask );
-#define portSET_INTERRUPT_MASK_FROM_ISR()         ulPortSetInterruptMask()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vPortClearInterruptMask( x )
+    extern uint32_t ulPortSetInterruptMask( void );
+    extern void vPortClearInterruptMask( uint32_t ulNewMask );
+    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulPortSetInterruptMask()
+    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vPortClearInterruptMask( x )
 
 
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
+    extern void vPortEnterCritical( void );
+    extern void vPortExitCritical( void );
 
-#define portDISABLE_INTERRUPTS()    portSET_INTERRUPT_MASK()
-#define portENABLE_INTERRUPTS()     portCLEAR_INTERRUPT_MASK()
-#define portENTER_CRITICAL()        vPortEnterCritical()
-#define portEXIT_CRITICAL()         vPortExitCritical()
+    #define portDISABLE_INTERRUPTS()    portSET_INTERRUPT_MASK()
+    #define portENABLE_INTERRUPTS()     portCLEAR_INTERRUPT_MASK()
+    #define portENTER_CRITICAL()        vPortEnterCritical()
+    #define portEXIT_CRITICAL()         vPortExitCritical()
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
-#define portNOP()
+    #define portNOP()
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus

From cb196ddbb1a7b504fb3d4f349065c1ee625de93e Mon Sep 17 00:00:00 2001
From: Soren Ptak <ptaksoren@gmail.com>
Date: Thu, 23 Nov 2023 04:04:07 -0800
Subject: [PATCH 120/424] Revert Portable/WizC Formatting (#888)

* Revert formatting on WizC ports

* Fix spelling mistakes

---------

Co-authored-by: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
---
 portable/WizC/PIC18/Drivers/Tick/Tick.c    |  84 ++--
 portable/WizC/PIC18/Drivers/Tick/isrTick.c |  24 +-
 portable/WizC/PIC18/addFreeRTOS.h          |  16 +-
 portable/WizC/PIC18/port.c                 | 134 +++--
 portable/WizC/PIC18/portmacro.h            | 539 ++++++++++-----------
 5 files changed, 396 insertions(+), 401 deletions(-)

diff --git a/portable/WizC/PIC18/Drivers/Tick/Tick.c b/portable/WizC/PIC18/Drivers/Tick/Tick.c
index 16d7bc12a..5dfa080b6 100644
--- a/portable/WizC/PIC18/Drivers/Tick/Tick.c
+++ b/portable/WizC/PIC18/Drivers/Tick/Tick.c
@@ -27,22 +27,22 @@
  */
 
 /*
- * Changes from V3.0.0
- + ISRcode is pulled inline and portTICKisr() is therefore
- +    deleted from this file.
- +
- + Prescaler logic for Timer1 added to allow for a wider
- +    range of TickRates.
- +
- + Changes from V3.0.1
- */
+Changes from V3.0.0
+    + ISRcode is pulled inline and portTICKisr() is therefore
+      deleted from this file.
+
+    + Prescaler logic for Timer1 added to allow for a wider
+      range of TickRates.
+
+Changes from V3.0.1
+*/
 
 #include <FreeRTOS.h>
 #include <task.h>
 
 /* IO port constants. */
-#define portBIT_SET                    ( 1 )
-#define portBIT_CLEAR                  ( 0 )
+#define portBIT_SET     (1)
+#define portBIT_CLEAR   (0)
 
 /*
  * Hardware setup for the tick.
@@ -50,27 +50,27 @@
  * and requested tickrate, a prescaled value with a matching
  * prescaler are determined.
  */
-#define portTIMER_COMPARE_BASE         ( ( APROCFREQ / 4 ) / configTICK_RATE_HZ )
+#define portTIMER_COMPARE_BASE          ((APROCFREQ/4)/configTICK_RATE_HZ)
 
-#if portTIMER_COMPARE_BASE < 0x10000
-    #define portTIMER_COMPARE_VALUE    ( portTIMER_COMPARE_BASE )
-    #define portTIMER_COMPARE_PS1      ( portBIT_CLEAR )
-    #define portTIMER_COMPARE_PS0      ( portBIT_CLEAR )
+#if portTIMER_COMPARE_BASE   < 0x10000
+    #define portTIMER_COMPARE_VALUE     (portTIMER_COMPARE_BASE)
+    #define portTIMER_COMPARE_PS1       (portBIT_CLEAR)
+    #define portTIMER_COMPARE_PS0       (portBIT_CLEAR)
 #elif portTIMER_COMPARE_BASE < 0x20000
-    #define portTIMER_COMPARE_VALUE    ( portTIMER_COMPARE_BASE / 2 )
-    #define portTIMER_COMPARE_PS1      ( portBIT_CLEAR )
-    #define portTIMER_COMPARE_PS0      ( portBIT_SET )
+    #define portTIMER_COMPARE_VALUE     (portTIMER_COMPARE_BASE / 2)
+    #define portTIMER_COMPARE_PS1       (portBIT_CLEAR)
+    #define portTIMER_COMPARE_PS0       (portBIT_SET)
 #elif portTIMER_COMPARE_BASE < 0x40000
-    #define portTIMER_COMPARE_VALUE    ( portTIMER_COMPARE_BASE / 4 )
-    #define portTIMER_COMPARE_PS1      ( portBIT_SET )
-    #define portTIMER_COMPARE_PS0      ( portBIT_CLEAR )
+    #define portTIMER_COMPARE_VALUE     (portTIMER_COMPARE_BASE / 4)
+    #define portTIMER_COMPARE_PS1       (portBIT_SET)
+    #define portTIMER_COMPARE_PS0       (portBIT_CLEAR)
 #elif portTIMER_COMPARE_BASE < 0x80000
-    #define portTIMER_COMPARE_VALUE    ( portTIMER_COMPARE_BASE / 8 )
-    #define portTIMER_COMPARE_PS1      ( portBIT_SET )
-    #define portTIMER_COMPARE_PS0      ( portBIT_SET )
-#else /* if portTIMER_COMPARE_BASE < 0x10000 */
+    #define portTIMER_COMPARE_VALUE     (portTIMER_COMPARE_BASE / 8)
+    #define portTIMER_COMPARE_PS1       (portBIT_SET)
+    #define portTIMER_COMPARE_PS0       (portBIT_SET)
+#else
     #error "TickRate out of range"
-#endif /* if portTIMER_COMPARE_BASE < 0x10000 */
+#endif
 
 /*-----------------------------------------------------------*/
 
@@ -92,27 +92,27 @@ void portSetupTick( void )
      * Set the compare match value.
      */
     CCPR1H = ( uint8_t ) ( ( portTIMER_COMPARE_VALUE >> 8 ) & 0xff );
-    CCPR1L = ( uint8_t ) ( portTIMER_COMPARE_VALUE & 0xff );
+    CCPR1L = ( uint8_t )   ( portTIMER_COMPARE_VALUE & 0xff );
 
     /*
      * Set Compare Special Event Trigger Mode
      */
-    bCCP1M3 = portBIT_SET;
-    bCCP1M2 = portBIT_CLEAR;
-    bCCP1M1 = portBIT_SET;
-    bCCP1M0 = portBIT_SET;
+    bCCP1M3     = portBIT_SET;
+    bCCP1M2     = portBIT_CLEAR;
+    bCCP1M1     = portBIT_SET;
+    bCCP1M0     = portBIT_SET;
 
     /*
      * Enable CCP1 interrupt
      */
-    bCCP1IE = portBIT_SET;
+    bCCP1IE     = portBIT_SET;
 
     /*
      * We are only going to use the global interrupt bit, so disable
      * interruptpriorities and enable peripheral interrupts.
      */
-    bIPEN = portBIT_CLEAR;
-    bPEIE = portBIT_SET;
+    bIPEN       = portBIT_CLEAR;
+    bPEIE       = portBIT_SET;
 
     /*
      * Set up timer1
@@ -128,12 +128,12 @@ void portSetupTick( void )
     /*
      * Setup the timer
      */
-    bRD16 = portBIT_SET;              /* 16-bit */
-    bT1CKPS1 = portTIMER_COMPARE_PS1; /* prescaler */
-    bT1CKPS0 = portTIMER_COMPARE_PS0; /* prescaler */
-    bT1OSCEN = portBIT_SET;           /* Oscillator enable */
-    bT1SYNC = portBIT_SET;            /* No external clock sync */
-    bTMR1CS = portBIT_CLEAR;          /* Internal clock */
+    bRD16       = portBIT_SET;              // 16-bit
+    bT1CKPS1    = portTIMER_COMPARE_PS1;    // prescaler
+    bT1CKPS0    = portTIMER_COMPARE_PS0;    // prescaler
+    bT1OSCEN    = portBIT_SET;              // Oscillator enable
+    bT1SYNC     = portBIT_SET;              // No external clock sync
+    bTMR1CS     = portBIT_CLEAR;            // Internal clock
 
-    bTMR1ON = portBIT_SET;            /* Start timer1 */
+    bTMR1ON     = portBIT_SET;              // Start timer1
 }
diff --git a/portable/WizC/PIC18/Drivers/Tick/isrTick.c b/portable/WizC/PIC18/Drivers/Tick/isrTick.c
index b4d1338b2..f61047dc1 100644
--- a/portable/WizC/PIC18/Drivers/Tick/isrTick.c
+++ b/portable/WizC/PIC18/Drivers/Tick/isrTick.c
@@ -27,17 +27,17 @@
  */
 
 /*
- * Changes from V3.0.0
- + ISRcode pulled inline to reduce stack-usage.
- +
- + Added functionality to only call vTaskSwitchContext() once
- +    when handling multiple interruptsources in a single interruptcall.
- +
- + Filename changed to a .c extension to allow stepping through code
- +    using F7.
- +
- + Changes from V3.0.1
- */
+Changes from V3.0.0
+    + ISRcode pulled inline to reduce stack-usage.
+
+    + Added functionality to only call vTaskSwitchContext() once
+      when handling multiple interruptsources in a single interruptcall.
+
+    + Filename changed to a .c extension to allow stepping through code
+      using F7.
+
+Changes from V3.0.1
+*/
 
 /*
  * ISR for the tick.
@@ -76,4 +76,4 @@
 
 #pragma wizcpp uselib     "$__PATHNAME__/Tick.c"
 
-#endif /* _FREERTOS_DRIVERS_TICK_ISRTICK_C */
+#endif  /* _FREERTOS_DRIVERS_TICK_ISRTICK_C */
diff --git a/portable/WizC/PIC18/addFreeRTOS.h b/portable/WizC/PIC18/addFreeRTOS.h
index 28ea79c02..178ca1089 100644
--- a/portable/WizC/PIC18/addFreeRTOS.h
+++ b/portable/WizC/PIC18/addFreeRTOS.h
@@ -27,13 +27,13 @@
  */
 
 /*
- * Changes from V3.0.0
- *
- * Changes from V3.0.1
- *
- * Changes from V4.0.1
- *  Uselib pragma added for Croutine.c
- */
+Changes from V3.0.0
+
+Changes from V3.0.1
+
+Changes from V4.0.1
+    Uselib pragma added for Croutine.c
+*/
 
 /*
  * The installation script will automatically prepend this file to the default FreeRTOS.h.
@@ -51,4 +51,4 @@
 #pragma wizcpp uselib     "$__PATHNAME__/libFreeRTOS/Modules/List.c"
 #pragma wizcpp uselib     "$__PATHNAME__/libFreeRTOS/Modules/Port.c"
 
-#endif /* WIZC_FREERTOS_H */
+#endif  /* WIZC_FREERTOS_H */
diff --git a/portable/WizC/PIC18/port.c b/portable/WizC/PIC18/port.c
index 13f8d4a1b..edabae61d 100644
--- a/portable/WizC/PIC18/port.c
+++ b/portable/WizC/PIC18/port.c
@@ -27,19 +27,19 @@
  */
 
 /*
- * Changes from V3.2.1
- + CallReturn Depth increased from 8 to 10 levels to accommodate wizC/fedC V12.
- +
- + Changes from V3.2.0
- + TBLPTRU is now initialised to zero during the initial stack creation of a new task. This solves
- +  an error on devices with more than 64kB ROM.
- +
- + Changes from V3.0.0
- + ucCriticalNesting is now initialised to 0x7F to prevent interrupts from being
- +        handled before the scheduler is started.
- +
- + Changes from V3.0.1
- */
+Changes from V3.2.1
+    + CallReturn Depth increased from 8 to 10 levels to accommodate wizC/fedC V12.
+
+Changes from V3.2.0
+    + TBLPTRU is now initialised to zero during the initial stack creation of a new task. This solves
+    an error on devices with more than 64kB ROM.
+
+Changes from V3.0.0
+    + ucCriticalNesting is now initialised to 0x7F to prevent interrupts from being
+          handled before the scheduler is started.
+
+Changes from V3.0.1
+*/
 
 /* Scheduler include files. */
 #include <FreeRTOS.h>
@@ -78,17 +78,17 @@ extern volatile TCB_t * volatile pxCurrentTCB;
  *      16 bytes: Free space on stack
  */
 #if _ROMSIZE > 0x8000
-    #define portSTACK_FSR_BYTES                ( 15 )
-    #define portSTACK_CALLRETURN_ENTRY_SIZE    ( 3 )
+    #define portSTACK_FSR_BYTES             ( 15 )
+    #define portSTACK_CALLRETURN_ENTRY_SIZE (  3 )
 #else
-    #define portSTACK_FSR_BYTES                ( 13 )
-    #define portSTACK_CALLRETURN_ENTRY_SIZE    ( 2 )
+    #define portSTACK_FSR_BYTES             ( 13 )
+    #define portSTACK_CALLRETURN_ENTRY_SIZE (  2 )
 #endif
 
-#define portSTACK_MINIMAL_CALLRETURN_DEPTH     ( 10 )
-#define portSTACK_OTHER_BYTES                  ( 20 )
+#define portSTACK_MINIMAL_CALLRETURN_DEPTH  ( 10 )
+#define portSTACK_OTHER_BYTES               ( 20 )
 
-uint16_t usCalcMinStackSize = 0;
+uint16_t usCalcMinStackSize     = 0;
 
 /*-----------------------------------------------------------*/
 
@@ -106,20 +106,16 @@ register uint8_t ucCriticalNesting = 0x7F;
  * Initialise the stack of a new task.
  * See portSAVE_CONTEXT macro for description.
  */
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
 {
-    uint8_t ucScratch;
-
+uint8_t ucScratch;
     /*
      * Get the size of the RAMarea in page 0 used by the compiler
      * We do this here already to avoid W-register conflicts.
      */
     _Pragma("asm")
-    movlw OVERHEADPAGE0 - LOCOPTSIZE + MAXLOCOPTSIZE
-    movwf PRODL, ACCESS;
-    PRODL is used as temp register
+        movlw   OVERHEADPAGE0-LOCOPTSIZE+MAXLOCOPTSIZE
+        movwf   PRODL,ACCESS        ; PRODL is used as temp register
     _Pragma("asmend")
     ucScratch = PRODL;
 
@@ -127,9 +123,9 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
      * Place a few bytes of known values on the bottom of the stack.
      * This is just useful for debugging.
      */
-/*  *pxTopOfStack-- = 0x11; */
-/*  *pxTopOfStack-- = 0x22; */
-/*  *pxTopOfStack-- = 0x33; */
+//  *pxTopOfStack-- = 0x11;
+//  *pxTopOfStack-- = 0x22;
+//  *pxTopOfStack-- = 0x33;
 
     /*
      * Simulate how the stack would look after a call to vPortYield()
@@ -140,36 +136,36 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
      * First store the function parameters.  This is where the task expects
      * to find them when it starts running.
      */
-    *pxTopOfStack-- = ( StackType_t ) ( ( ( uint16_t ) pvParameters >> 8 ) & 0x00ff );
-    *pxTopOfStack-- = ( StackType_t ) ( ( uint16_t ) pvParameters & 0x00ff );
+    *pxTopOfStack-- = ( StackType_t ) ( (( uint16_t ) pvParameters >> 8) & 0x00ff );
+    *pxTopOfStack-- = ( StackType_t ) (  ( uint16_t ) pvParameters       & 0x00ff );
 
     /*
      * Next are all the registers that form part of the task context.
      */
-    *pxTopOfStack-- = ( StackType_t ) 0x11;     /* STATUS. */
-    *pxTopOfStack-- = ( StackType_t ) 0x22;     /* WREG. */
-    *pxTopOfStack-- = ( StackType_t ) 0x33;     /* BSR. */
-    *pxTopOfStack-- = ( StackType_t ) 0x44;     /* PRODH. */
-    *pxTopOfStack-- = ( StackType_t ) 0x55;     /* PRODL. */
-    *pxTopOfStack-- = ( StackType_t ) 0x66;     /* FSR0H. */
-    *pxTopOfStack-- = ( StackType_t ) 0x77;     /* FSR0L. */
-    *pxTopOfStack-- = ( StackType_t ) 0x88;     /* FSR1H. */
-    *pxTopOfStack-- = ( StackType_t ) 0x99;     /* FSR1L. */
-    *pxTopOfStack-- = ( StackType_t ) 0xAA;     /* TABLAT. */
-    #if _ROMSIZE > 0x8000
-        *pxTopOfStack-- = ( StackType_t ) 0x00; /* TBLPTRU. */
-    #endif
-    *pxTopOfStack-- = ( StackType_t ) 0xCC;     /* TBLPTRH. */
-    *pxTopOfStack-- = ( StackType_t ) 0xDD;     /* TBLPTRL. */
-    #if _ROMSIZE > 0x8000
-        *pxTopOfStack-- = ( StackType_t ) 0xEE; /* PCLATU. */
-    #endif
-    *pxTopOfStack-- = ( StackType_t ) 0xFF;     /* PCLATH. */
+    *pxTopOfStack-- = ( StackType_t ) 0x11; /* STATUS. */
+    *pxTopOfStack-- = ( StackType_t ) 0x22; /* WREG. */
+    *pxTopOfStack-- = ( StackType_t ) 0x33; /* BSR. */
+    *pxTopOfStack-- = ( StackType_t ) 0x44; /* PRODH. */
+    *pxTopOfStack-- = ( StackType_t ) 0x55; /* PRODL. */
+    *pxTopOfStack-- = ( StackType_t ) 0x66; /* FSR0H. */
+    *pxTopOfStack-- = ( StackType_t ) 0x77; /* FSR0L. */
+    *pxTopOfStack-- = ( StackType_t ) 0x88; /* FSR1H. */
+    *pxTopOfStack-- = ( StackType_t ) 0x99; /* FSR1L. */
+    *pxTopOfStack-- = ( StackType_t ) 0xAA; /* TABLAT. */
+#if _ROMSIZE > 0x8000
+    *pxTopOfStack-- = ( StackType_t ) 0x00; /* TBLPTRU. */
+#endif
+    *pxTopOfStack-- = ( StackType_t ) 0xCC; /* TBLPTRH. */
+    *pxTopOfStack-- = ( StackType_t ) 0xDD; /* TBLPTRL. */
+#if _ROMSIZE > 0x8000
+    *pxTopOfStack-- = ( StackType_t ) 0xEE; /* PCLATU. */
+#endif
+    *pxTopOfStack-- = ( StackType_t ) 0xFF; /* PCLATH. */
 
     /*
      * Next the compiler's scratchspace.
      */
-    while( ucScratch-- > 0 )
+    while(ucScratch-- > 0)
     {
         *pxTopOfStack-- = ( StackType_t ) 0;
     }
@@ -180,11 +176,11 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
      * stack, too. TOSU is always written as zero here because wizC does not allow
      * functionpointers to point above 64kB in ROM.
      */
-    #if _ROMSIZE > 0x8000
-        *pxTopOfStack-- = ( StackType_t ) 0;
-    #endif
+#if _ROMSIZE > 0x8000
+    *pxTopOfStack-- = ( StackType_t ) 0;
+#endif
     *pxTopOfStack-- = ( StackType_t ) ( ( ( uint16_t ) pxCode >> 8 ) & 0x00ff );
-    *pxTopOfStack-- = ( StackType_t ) ( ( uint16_t ) pxCode & 0x00ff );
+    *pxTopOfStack-- = ( StackType_t ) ( (   uint16_t ) pxCode        & 0x00ff );
 
     /*
      * Store the number of return addresses on the hardware stack.
@@ -211,19 +207,19 @@ uint16_t usPortCALCULATE_MINIMAL_STACK_SIZE( void )
      * Fetch the size of compiler's scratchspace.
      */
     _Pragma("asm")
-    movlw OVERHEADPAGE0 - LOCOPTSIZE + MAXLOCOPTSIZE
-    movlb usCalcMinStackSize >> 8
-    movwf usCalcMinStackSize, BANKED
+        movlw   OVERHEADPAGE0-LOCOPTSIZE+MAXLOCOPTSIZE
+        movlb   usCalcMinStackSize>>8
+        movwf   usCalcMinStackSize,BANKED
     _Pragma("asmend")
 
     /*
      * Add minimum needed stackspace
      */
-    usCalcMinStackSize += ( portSTACK_FSR_BYTES )
-                          + ( portSTACK_MINIMAL_CALLRETURN_DEPTH * portSTACK_CALLRETURN_ENTRY_SIZE )
-                          + ( portSTACK_OTHER_BYTES );
+    usCalcMinStackSize  +=  ( portSTACK_FSR_BYTES )
+        +   ( portSTACK_MINIMAL_CALLRETURN_DEPTH * portSTACK_CALLRETURN_ENTRY_SIZE )
+        +   ( portSTACK_OTHER_BYTES );
 
-    return( usCalcMinStackSize );
+    return(usCalcMinStackSize);
 }
 
 /*-----------------------------------------------------------*/
@@ -286,11 +282,11 @@ void vPortYield( void )
 }
 /*-----------------------------------------------------------*/
 
-#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
 
-    void * pvPortMalloc( uint16_t usWantedSize )
+    void *pvPortMalloc( uint16_t usWantedSize )
     {
-        void * pvReturn;
+    void *pvReturn;
 
         vTaskSuspendAll();
         {
@@ -305,9 +301,9 @@ void vPortYield( void )
 
 /*-----------------------------------------------------------*/
 
-#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
 
-    void vPortFree( void * pv )
+    void vPortFree( void *pv )
     {
         if( pv )
         {
diff --git a/portable/WizC/PIC18/portmacro.h b/portable/WizC/PIC18/portmacro.h
index e272084b3..44d26592f 100644
--- a/portable/WizC/PIC18/portmacro.h
+++ b/portable/WizC/PIC18/portmacro.h
@@ -27,48 +27,48 @@
  */
 
 /*
- * Changes from V3.0.0
- *
- * Changes from V3.0.1
- */
+Changes from V3.0.0
+
+Changes from V3.0.1
+*/
 #ifndef PORTMACRO_H
 #define PORTMACRO_H
 
-#if !defined( _SERIES ) || _SERIES != 18
+#if !defined(_SERIES) || _SERIES != 18
     #error "WizC supports FreeRTOS on the Microchip PIC18-series only"
 #endif
 
-#if !defined( QUICKCALL ) || QUICKCALL != 1
+#if !defined(QUICKCALL) || QUICKCALL != 1
     #error "QuickCall must be enabled (see ProjectOptions/Optimisations)"
 #endif
 
 #include <stddef.h>
 #include <pic.h>
 
-#define portCHAR          char
-#define portFLOAT         float
-#define portDOUBLE        portFLOAT
-#define portLONG          long
-#define portSHORT         short
-#define portSTACK_TYPE    uint8_t
-#define portBASE_TYPE     char
+#define portCHAR        char
+#define portFLOAT       float
+#define portDOUBLE      portFLOAT
+#define portLONG        long
+#define portSHORT       short
+#define portSTACK_TYPE  uint8_t
+#define portBASE_TYPE   char
 
-typedef portSTACK_TYPE   StackType_t;
-typedef signed char      BaseType_t;
-typedef unsigned char    UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef signed char BaseType_t;
+typedef unsigned char UBaseType_t;
 
 
-#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t     TickType_t;
-    #define portMAX_DELAY    ( TickType_t ) ( 0xFFFF )
+#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t TickType_t;
+    #define portMAX_DELAY ( TickType_t )    ( 0xFFFF )
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t     TickType_t;
-    #define portMAX_DELAY    ( TickType_t ) ( 0xFFFFFFFFUL )
+    typedef uint32_t TickType_t;
+    #define portMAX_DELAY ( TickType_t )    ( 0xFFFFFFFFUL )
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
 
-#define portBYTE_ALIGNMENT    1
+#define portBYTE_ALIGNMENT          1
 
 /*-----------------------------------------------------------*/
 
@@ -76,33 +76,33 @@ typedef unsigned char    UBaseType_t;
  * Constant used for context switch macro when we require the interrupt
  * enable state to be forced when the interrupted task is switched back in.
  */
-#define portINTERRUPTS_FORCED           ( 0x01 )
+#define portINTERRUPTS_FORCED               (0x01)
 
 /*
  * Constant used for context switch macro when we require the interrupt
  * enable state to be unchanged when the interrupted task is switched back in.
  */
-#define portINTERRUPTS_UNCHANGED        ( 0x00 )
+#define portINTERRUPTS_UNCHANGED            (0x00)
 
 /* Initial interrupt enable state for newly created tasks.  This value is
  * used when a task switches in for the first time.
  */
-#define portINTERRUPTS_INITIAL_STATE    ( portINTERRUPTS_FORCED )
+#define portINTERRUPTS_INITIAL_STATE        (portINTERRUPTS_FORCED)
 
 /*
  * Macros to modify the global interrupt enable bit in INTCON.
  */
-#define portDISABLE_INTERRUPTS() \
-    do                           \
-    {                            \
-        bGIE = 0;                \
-    } while( bGIE ) /* MicroChip recommends this check! */
+#define portDISABLE_INTERRUPTS()    \
+    do                              \
+    {                               \
+        bGIE=0;                     \
+    } while(bGIE)   // MicroChip recommends this check!
 
-#define portENABLE_INTERRUPTS() \
-    do                          \
-    {                           \
-        bGIE = 1;               \
-    } while( 0 )
+#define portENABLE_INTERRUPTS()     \
+    do                              \
+    {                               \
+        bGIE=1;                     \
+    } while(0)
 
 /*-----------------------------------------------------------*/
 
@@ -111,43 +111,43 @@ typedef unsigned char    UBaseType_t;
  */
 extern uint8_t ucCriticalNesting;
 
-#define portNO_CRITICAL_SECTION_NESTING    ( ( uint8_t ) 0 )
+#define portNO_CRITICAL_SECTION_NESTING     ( ( uint8_t ) 0 )
 
-#define portENTER_CRITICAL()      \
-    do                            \
-    {                             \
-        portDISABLE_INTERRUPTS(); \
-                                  \
-        /* \
-         * Now interrupts are disabled ucCriticalNesting \
-         * can be accessed directly. Increment \
-         * ucCriticalNesting to keep a count of how \
-         * many times portENTER_CRITICAL() has been called. \
-         */                  \
-        ucCriticalNesting++; \
-    } while( 0 )
+#define portENTER_CRITICAL()                                        \
+    do                                                              \
+    {                                                               \
+        portDISABLE_INTERRUPTS();                                   \
+                                                                    \
+        /*                                                          \
+         * Now interrupts are disabled ucCriticalNesting            \
+         * can be accessed directly. Increment                      \
+         * ucCriticalNesting to keep a count of how                 \
+         * many times portENTER_CRITICAL() has been called.         \
+         */                                                         \
+        ucCriticalNesting++;                                        \
+    } while(0)
 
-#define portEXIT_CRITICAL()                                       \
-    do                                                            \
-    {                                                             \
-        if( ucCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \
-        {                                                         \
-            /* \
-             * Decrement the nesting count as we are leaving a \
-             * critical section. \
-             */                  \
-            ucCriticalNesting--; \
-        }                        \
-                                 \
-        /* \
-         * If the nesting level has reached zero then \
-         * interrupts should be re-enabled. \
-         */                                                        \
-        if( ucCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \
-        {                                                          \
-            portENABLE_INTERRUPTS();                               \
-        }                                                          \
-    } while( 0 )
+#define portEXIT_CRITICAL()                                         \
+    do                                                              \
+    {                                                               \
+        if(ucCriticalNesting > portNO_CRITICAL_SECTION_NESTING)     \
+        {                                                           \
+            /*                                                      \
+             * Decrement the nesting count as we are leaving a      \
+             * critical section.                                    \
+             */                                                     \
+            ucCriticalNesting--;                                    \
+        }                                                           \
+                                                                    \
+        /*                                                          \
+         * If the nesting level has reached zero then               \
+         * interrupts should be re-enabled.                         \
+         */                                                         \
+        if( ucCriticalNesting == portNO_CRITICAL_SECTION_NESTING )  \
+        {                                                           \
+            portENABLE_INTERRUPTS();                                \
+        }                                                           \
+    } while(0)
 
 /*-----------------------------------------------------------*/
 
@@ -159,15 +159,15 @@ extern uint8_t ucCriticalNesting;
 extern uint16_t usPortCALCULATE_MINIMAL_STACK_SIZE( void );
 extern uint16_t usCalcMinStackSize;
 
-#define portMINIMAL_STACK_SIZE               \
-    ( ( usCalcMinStackSize == 0 )            \
-      ? usPortCALCULATE_MINIMAL_STACK_SIZE() \
-      : usCalcMinStackSize )
+#define portMINIMAL_STACK_SIZE                  \
+    ((usCalcMinStackSize == 0)                  \
+        ? usPortCALCULATE_MINIMAL_STACK_SIZE()  \
+        : usCalcMinStackSize )
 
 /*
  * WizC uses a downgrowing stack
  */
-#define portSTACK_GROWTH    ( -1 )
+#define portSTACK_GROWTH            ( -1 )
 
 /*-----------------------------------------------------------*/
 
@@ -203,220 +203,219 @@ extern uint16_t usCalcMinStackSize;
  * assembler definitions.
  */
 
-#define portSAVE_CONTEXT( ucInterruptForced )                   \
-    do                                                          \
-    {                                                           \
-        portDISABLE_INTERRUPTS();                               \
-                                                                \
-        _Pragma("asm")                                          \
-        ;                                                       \
-        ; Push the relevant SFR's onto the task's stack         \
-        ;                                                       \
-        movff   STATUS,POSTDEC2                                 \
-        movff   WREG,POSTDEC2                                   \
-        movff   BSR,POSTDEC2                                    \
-        movff   PRODH,POSTDEC2                                  \
-        movff   PRODL,POSTDEC2                                  \
-        movff   FSR0H,POSTDEC2                                  \
-        movff   FSR0L,POSTDEC2                                  \
-        movff   FSR1H,POSTDEC2                                  \
-        movff   FSR1L,POSTDEC2                                  \
-        movff   TABLAT,POSTDEC2                                 \
-        if __ROMSIZE > 0x8000                                   \
-        movff   TBLPTRU,POSTDEC2                                \
-        endif                                                   \
-        movff   TBLPTRH,POSTDEC2                                \
-        movff   TBLPTRL,POSTDEC2                                \
-        if __ROMSIZE > 0x8000                                   \
-        movff   PCLATU,POSTDEC2                                 \
-        endif                                                   \
-        movff   PCLATH,POSTDEC2                                 \
-        ;                                                       \
-        ; Store the compiler-scratch-area as described above.   \
-        ;                                                       \
-        movlw   OVERHEADPAGE0-LOCOPTSIZE+MAXLOCOPTSIZE          \
-        clrf    FSR0L,ACCESS                                    \
-        clrf    FSR0H,ACCESS                                    \
-        _rtos_S1:                                               \
-        movff   POSTINC0,POSTDEC2                               \
-        decfsz  WREG,W,ACCESS                                   \
-        SMARTJUMP _rtos_S1                                      \
-        ;                                                       \
-        ; Save the pic call/return-stack belonging to the       \
-        ; current task by copying it to the task's software-    \
-        ; stack. We save the hardware stack pointer (which      \
-        ; is the number of addresses on the stack) in the       \
-        ; W-register first because we need it later and it      \
-        ; is modified in the save-loop by executing pop's.      \
-        ; After the loop the W-register is stored on the        \
-        ; stack, too.                                           \
-        ;                                                       \
-        movf    STKPTR,W,ACCESS                                 \
-        bz      _rtos_s3                                        \
-        _rtos_S2:                                               \
-        if __ROMSIZE > 0x8000                                   \
-        movff   TOSU,POSTDEC2                                   \
-        endif                                                   \
-        movff   TOSH,POSTDEC2                                   \
-        movff   TOSL,POSTDEC2                                   \
-        pop                                                     \
-        tstfsz  STKPTR,ACCESS                                   \
-        SMARTJUMP _rtos_S2                                      \
-        _rtos_s3:                                               \
-        movwf   POSTDEC2,ACCESS                                 \
-        ;                                                       \
-        ; Next the value for ucCriticalNesting used by the      \
-        ; task is stored on the stack. When                     \
-        ; (ucInterruptForced == portINTERRUPTS_FORCED), we save \
-        ; it as 0 (portNO_CRITICAL_SECTION_NESTING).            \
-        ;                                                       \
-        if ucInterruptForced == portINTERRUPTS_FORCED           \
-        clrf POSTDEC2,ACCESS                                    \
-        else                                                    \
-        movff   ucCriticalNesting,POSTDEC2                      \
-        endif                                                   \
-        ;                                                       \
-        ; Save the new top of the software stack in the TCB.    \
-        ;                                                       \
-        movff   pxCurrentTCB,FSR0L                              \
-        movff   pxCurrentTCB+1,FSR0H                            \
-        movff   FSR2L,POSTINC0                                  \
-        movff   FSR2H,POSTINC0                                  \
-        _Pragma("asmend")                                       \
-        } while(0)
+#define portSAVE_CONTEXT( ucInterruptForced )                       \
+    do                                                              \
+    {                                                               \
+        portDISABLE_INTERRUPTS();                                   \
+                                                                    \
+        _Pragma("asm")                                              \
+            ;                                                       \
+            ; Push the relevant SFR's onto the task's stack         \
+            ;                                                       \
+            movff   STATUS,POSTDEC2                                 \
+            movff   WREG,POSTDEC2                                   \
+            movff   BSR,POSTDEC2                                    \
+            movff   PRODH,POSTDEC2                                  \
+            movff   PRODL,POSTDEC2                                  \
+            movff   FSR0H,POSTDEC2                                  \
+            movff   FSR0L,POSTDEC2                                  \
+            movff   FSR1H,POSTDEC2                                  \
+            movff   FSR1L,POSTDEC2                                  \
+            movff   TABLAT,POSTDEC2                                 \
+            if __ROMSIZE > 0x8000                                   \
+                movff   TBLPTRU,POSTDEC2                            \
+            endif                                                   \
+            movff   TBLPTRH,POSTDEC2                                \
+            movff   TBLPTRL,POSTDEC2                                \
+            if __ROMSIZE > 0x8000                                   \
+                movff   PCLATU,POSTDEC2                             \
+            endif                                                   \
+            movff   PCLATH,POSTDEC2                                 \
+            ;                                                       \
+            ; Store the compiler-scratch-area as described above.   \
+            ;                                                       \
+            movlw   OVERHEADPAGE0-LOCOPTSIZE+MAXLOCOPTSIZE          \
+            clrf    FSR0L,ACCESS                                    \
+            clrf    FSR0H,ACCESS                                    \
+        _rtos_S1:                                                   \
+            movff   POSTINC0,POSTDEC2                               \
+            decfsz  WREG,W,ACCESS                                   \
+            SMARTJUMP _rtos_S1                                      \
+            ;                                                       \
+            ; Save the pic call/return-stack belonging to the       \
+            ; current task by copying it to the task's software-    \
+            ; stack. We save the hardware stack pointer (which      \
+            ; is the number of addresses on the stack) in the       \
+            ; W-register first because we need it later and it      \
+            ; is modified in the save-loop by executing pop's.      \
+            ; After the loop the W-register is stored on the        \
+            ; stack, too.                                           \
+            ;                                                       \
+            movf    STKPTR,W,ACCESS                                 \
+            bz      _rtos_s3                                        \
+        _rtos_S2:                                                   \
+            if __ROMSIZE > 0x8000                                   \
+                movff   TOSU,POSTDEC2                               \
+            endif                                                   \
+            movff   TOSH,POSTDEC2                                   \
+            movff   TOSL,POSTDEC2                                   \
+            pop                                                     \
+            tstfsz  STKPTR,ACCESS                                   \
+            SMARTJUMP _rtos_S2                                      \
+        _rtos_s3:                                                   \
+            movwf   POSTDEC2,ACCESS                                 \
+            ;                                                       \
+            ; Next the value for ucCriticalNesting used by the      \
+            ; task is stored on the stack. When                     \
+            ; (ucInterruptForced == portINTERRUPTS_FORCED), we save \
+            ; it as 0 (portNO_CRITICAL_SECTION_NESTING).            \
+            ;                                                       \
+            if ucInterruptForced == portINTERRUPTS_FORCED           \
+                clrf POSTDEC2,ACCESS                                \
+            else                                                    \
+                movff   ucCriticalNesting,POSTDEC2                  \
+            endif                                                   \
+            ;                                                       \
+            ; Save the new top of the software stack in the TCB.    \
+            ;                                                       \
+            movff   pxCurrentTCB,FSR0L                              \
+            movff   pxCurrentTCB+1,FSR0H                            \
+            movff   FSR2L,POSTINC0                                  \
+            movff   FSR2H,POSTINC0                                  \
+        _Pragma("asmend")                                           \
+    } while(0)
 
 /************************************************************/
 
 /*
  * This is the reverse of portSAVE_CONTEXT.
  */
-#define portRESTORE_CONTEXT()                                   \
-    do                                                          \
-    {                                                           \
-        _Pragma("asm")                                          \
-        ;                                                       \
-        ; Set FSR0 to point to pxCurrentTCB->pxTopOfStack.      \
-        ;                                                       \
-        movff   pxCurrentTCB,FSR0L                              \
-        movff   pxCurrentTCB+1,FSR0H                            \
-        ;                                                       \
-        ; De-reference FSR0 to set the address it holds into    \
-        ; FSR2 (i.e. *( pxCurrentTCB->pxTopOfStack ) ). FSR2    \
-        ; is used by wizC as stackpointer.                      \
-        ;                                                       \
-        movff   POSTINC0,FSR2L                                  \
-        movff   POSTINC0,FSR2H                                  \
-        ;                                                       \
-        ; Next, the value for ucCriticalNesting used by the     \
-        ; task is retrieved from the stack.                     \
-        ;                                                       \
-        movff   PREINC2,ucCriticalNesting                       \
-        ;                                                       \
-        ; Rebuild the pic call/return-stack. The number of      \
-        ; return addresses is the next item on the task stack.  \
-        ; Save this number in PRODL. Then fetch the addresses   \
-        ; and store them on the hardwarestack.                  \
-        ; The datasheets say we can't use movff here...         \
-        ;                                                       \
-        movff   PREINC2,PRODL /* Use PRODL as tempregister */   \
-        clrf    STKPTR,ACCESS                                   \
-        _rtos_R1:                                               \
-        push                                                    \
-        movf    PREINC2,W,ACCESS                                \
-        movwf   TOSL,ACCESS                                     \
-        movf    PREINC2,W,ACCESS                                \
-        movwf   TOSH,ACCESS                                     \
-        if __ROMSIZE > 0x8000                                   \
-        movf    PREINC2,W,ACCESS                                \
-        movwf   TOSU,ACCESS                                     \
-        else                                                    \
-        clrf    TOSU,ACCESS                                     \
-        endif                                                   \
-        decfsz  PRODL,F,ACCESS                                  \
-        SMARTJUMP _rtos_R1                                      \
-        ;                                                       \
-        ; Restore the compiler's working storage area to page 0 \
-        ;                                                       \
-        movlw   OVERHEADPAGE0-LOCOPTSIZE+MAXLOCOPTSIZE          \
-        movwf   FSR0L,ACCESS                                    \
-        clrf    FSR0H,ACCESS                                    \
-        _rtos_R2:                                               \
-        decf    FSR0L,F,ACCESS                                  \
-        movff   PREINC2,INDF0                                   \
-        tstfsz  FSR0L,ACCESS                                    \
-        SMARTJUMP _rtos_R2                                      \
-        ;                                                       \
-        ; Restore the sfr's forming the tasks context.          \
-        ; We cannot yet restore bsr, w and status because       \
-        ; we need these registers for a final test.             \
-        ;                                                       \
-        movff   PREINC2,PCLATH                                  \
-        if __ROMSIZE > 0x8000                                   \
-        movff   PREINC2,PCLATU                                  \
-        else                                                    \
-        clrf    PCLATU,ACCESS                                   \
-        endif                                                   \
-        movff   PREINC2,TBLPTRL                                 \
-        movff   PREINC2,TBLPTRH                                 \
-        if __ROMSIZE > 0x8000                                   \
-        movff   PREINC2,TBLPTRU                                 \
-        else                                                    \
-        clrf    TBLPTRU,ACCESS                                  \
-        endif                                                   \
-        movff   PREINC2,TABLAT                                  \
-        movff   PREINC2,FSR1L                                   \
-        movff   PREINC2,FSR1H                                   \
-        movff   PREINC2,FSR0L                                   \
-        movff   PREINC2,FSR0H                                   \
-        movff   PREINC2,PRODL                                   \
-        movff   PREINC2,PRODH                                   \
-        ;                                                       \
-        ; The return from portRESTORE_CONTEXT() depends on      \
-        ; the value of ucCriticalNesting. When it is zero,      \
-        ; interrupts need to be enabled. This is done via a     \
-        ; retfie instruction because we need the                \
-        ; interrupt-enabling and the return to the restored     \
-        ; task to be uninterruptible.                           \
-        ; Because bsr, status and W are affected by the test    \
-        ; they are restored after the test.                     \
-        ;                                                       \
-        movlb   ucCriticalNesting>>8                            \
-        tstfsz  ucCriticalNesting,BANKED                        \
-        SMARTJUMP _rtos_R4                                      \
-        _rtos_R3:                                               \
-        movff   PREINC2,BSR                                     \
-        movff   PREINC2,WREG                                    \
-        movff   PREINC2,STATUS                                  \
-        retfie  0       ; Return enabling interrupts            \
-        _rtos_R4:                                               \
-        movff   PREINC2,BSR                                     \
-        movff   PREINC2,WREG                                    \
-        movff   PREINC2,STATUS                                  \
-        return  0       ; Return without affecting interrupts   \
-        _Pragma("asmend")                                       \
-        } while(0)
+#define portRESTORE_CONTEXT()                                       \
+    do                                                              \
+    {                                                               \
+        _Pragma("asm")                                              \
+            ;                                                       \
+            ; Set FSR0 to point to pxCurrentTCB->pxTopOfStack.      \
+            ;                                                       \
+            movff   pxCurrentTCB,FSR0L                              \
+            movff   pxCurrentTCB+1,FSR0H                            \
+            ;                                                       \
+            ; De-reference FSR0 to set the address it holds into    \
+            ; FSR2 (i.e. *( pxCurrentTCB->pxTopOfStack ) ). FSR2    \
+            ; is used by wizC as stackpointer.                      \
+            ;                                                       \
+            movff   POSTINC0,FSR2L                                  \
+            movff   POSTINC0,FSR2H                                  \
+            ;                                                       \
+            ; Next, the value for ucCriticalNesting used by the     \
+            ; task is retrieved from the stack.                     \
+            ;                                                       \
+            movff   PREINC2,ucCriticalNesting                       \
+            ;                                                       \
+            ; Rebuild the pic call/return-stack. The number of      \
+            ; return addresses is the next item on the task stack.  \
+            ; Save this number in PRODL. Then fetch the addresses   \
+            ; and store them on the hardwarestack.                  \
+            ; The datasheets say we can't use movff here...         \
+            ;                                                       \
+            movff   PREINC2,PRODL   // Use PRODL as tempregister    \
+            clrf    STKPTR,ACCESS                                   \
+        _rtos_R1:                                                   \
+            push                                                    \
+            movf    PREINC2,W,ACCESS                                \
+            movwf   TOSL,ACCESS                                     \
+            movf    PREINC2,W,ACCESS                                \
+            movwf   TOSH,ACCESS                                     \
+            if __ROMSIZE > 0x8000                                   \
+                movf    PREINC2,W,ACCESS                            \
+                movwf   TOSU,ACCESS                                 \
+            else                                                    \
+                clrf    TOSU,ACCESS                                 \
+            endif                                                   \
+            decfsz  PRODL,F,ACCESS                                  \
+            SMARTJUMP _rtos_R1                                      \
+            ;                                                       \
+            ; Restore the compiler's working storage area to page 0 \
+            ;                                                       \
+            movlw   OVERHEADPAGE0-LOCOPTSIZE+MAXLOCOPTSIZE          \
+            movwf   FSR0L,ACCESS                                    \
+            clrf    FSR0H,ACCESS                                    \
+        _rtos_R2:                                                   \
+            decf    FSR0L,F,ACCESS                                  \
+            movff   PREINC2,INDF0                                   \
+            tstfsz  FSR0L,ACCESS                                    \
+            SMARTJUMP _rtos_R2                                      \
+            ;                                                       \
+            ; Restore the sfr's forming the tasks context.          \
+            ; We cannot yet restore bsr, w and status because       \
+            ; we need these registers for a final test.             \
+            ;                                                       \
+            movff   PREINC2,PCLATH                                  \
+            if __ROMSIZE > 0x8000                                   \
+                movff   PREINC2,PCLATU                              \
+            else                                                    \
+                clrf    PCLATU,ACCESS                               \
+            endif                                                   \
+            movff   PREINC2,TBLPTRL                                 \
+            movff   PREINC2,TBLPTRH                                 \
+            if __ROMSIZE > 0x8000                                   \
+                movff   PREINC2,TBLPTRU                             \
+            else                                                    \
+                clrf    TBLPTRU,ACCESS                              \
+            endif                                                   \
+            movff   PREINC2,TABLAT                                  \
+            movff   PREINC2,FSR1L                                   \
+            movff   PREINC2,FSR1H                                   \
+            movff   PREINC2,FSR0L                                   \
+            movff   PREINC2,FSR0H                                   \
+            movff   PREINC2,PRODL                                   \
+            movff   PREINC2,PRODH                                   \
+            ;                                                       \
+            ; The return from portRESTORE_CONTEXT() depends on      \
+            ; the value of ucCriticalNesting. When it is zero,      \
+            ; interrupts need to be enabled. This is done via a     \
+            ; retfie instruction because we need the                \
+            ; interrupt-enabling and the return to the restored     \
+            ; task to be uninterruptible.                           \
+            ; Because bsr, status and W are affected by the test    \
+            ; they are restored after the test.                     \
+            ;                                                       \
+            movlb   ucCriticalNesting>>8                            \
+            tstfsz  ucCriticalNesting,BANKED                        \
+            SMARTJUMP _rtos_R4                                      \
+        _rtos_R3:                                                   \
+            movff   PREINC2,BSR                                     \
+            movff   PREINC2,WREG                                    \
+            movff   PREINC2,STATUS                                  \
+            retfie  0       ; Return enabling interrupts            \
+        _rtos_R4:                                                   \
+            movff   PREINC2,BSR                                     \
+            movff   PREINC2,WREG                                    \
+            movff   PREINC2,STATUS                                  \
+            return  0       ; Return without affecting interrupts   \
+        _Pragma("asmend")                                           \
+    } while(0)
 
 /*-----------------------------------------------------------*/
 
-#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portTICK_PERIOD_MS  ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
 
 /*-----------------------------------------------------------*/
 
 extern void vPortYield( void );
-#define portYIELD()    vPortYield()
+#define portYIELD()             vPortYield()
 
-#define portNOP()  \
-    _Pragma("asm") \
-    nop            \
-    _Pragma("asmend")
+#define portNOP()   _Pragma("asm")                                  \
+                        nop                                         \
+                    _Pragma("asmend")
 
 /*-----------------------------------------------------------*/
 
-#define portTASK_FUNCTION( xFunction, pvParameters ) \
-    void pointed xFunction( void * pvParameters )    \
+#define portTASK_FUNCTION( xFunction, pvParameters )        \
+    void pointed xFunction( void *pvParameters )        \
     _Pragma(asmfunc xFunction)
 
-#define portTASK_FUNCTION_PROTO    portTASK_FUNCTION
+#define portTASK_FUNCTION_PROTO     portTASK_FUNCTION
 /*-----------------------------------------------------------*/
 
 

From 09c4c4bae968084ac2ba26af81d160bdfcab841c Mon Sep 17 00:00:00 2001
From: Soren Ptak <ptaksoren@gmail.com>
Date: Thu, 23 Nov 2023 08:47:31 -0800
Subject: [PATCH 121/424] Coverity Scan Workflow Fix (#891)

Currently the Coverity Scan attempts to run on every fork that pulls
the file. This leads to anybody who pulls this file getting emails that
their workflow failed to run when the cron job attempts to run. This
PR sets the scan to only run if the repo is FreeRTOS/FreeRTOS-Kernel.
Also, change the scan from a cron job to a job that runs on a commit
to mainline, or if triggered manually.
---
 .github/workflows/coverity_scan.yml | 68 +++++++++++++++++++++++------
 1 file changed, 54 insertions(+), 14 deletions(-)

diff --git a/.github/workflows/coverity_scan.yml b/.github/workflows/coverity_scan.yml
index 050ea325b..bd6f77abc 100644
--- a/.github/workflows/coverity_scan.yml
+++ b/.github/workflows/coverity_scan.yml
@@ -1,47 +1,87 @@
-name: FreeRTOS-Kernel Coverity Scan
+name: Coverity Scan
 on:
-  schedule: ## Scheduled to run at 1:15 AM UTC daily.
-    - cron: '15 1 * * *'
+  # Run on every commit to mainline
+  push:
+    branches: main
+  # Allow manual running of the scan
+  workflow_dispatch:
 
+env:
+  bashPass: \033[32;1mPASSED -
+  bashInfo: \033[33;1mINFO -
+  bashFail: \033[31;1mFAILED -
+  bashEnd:  \033[0m
 
 jobs:
-
   Coverity-Scan:
+    if: ( github.repository == 'FreeRTOS/FreeRTOS-Kernel' )
     name: Coverity Scan
     runs-on: ubuntu-latest
     steps:
       - name: Checkout the Repository
         uses: actions/checkout@v3
 
-      - name: Install Build Essentials
+      - env:
+          stepName: Install Build Essentials
         shell: bash
         run: |
+          # ${{ env.stepName }}
+          echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}"
+
           sudo apt-get -y update
           sudo apt-get -y install build-essential
 
-      - name: Install Coverity Build
-        shell: bash
-        env:
+          echo "::endgroup::"
+          echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }}"
+
+      - env:
+          stepName: Install Coverity Build
           COVERITY_TOKEN: ${{ secrets.COVERITY_SCAN_TOKEN }}
+        shell: bash
         run: |
+          # ${{ env.stepName }}
+          echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}"
+
           wget -nv -qO- https://scan.coverity.com/download/linux64 --post-data "token=${COVERITY_TOKEN}&project=FreeRTOS-Kernel" | tar -zx --one-top-level=cov_scan --strip-components 1
           echo "cov_scan_path=$(pwd)/cov_scan/bin" >> $GITHUB_ENV
 
-      - name: Coverity Build & Upload for Scan
-        shell: bash
-        env:
+          echo "::endgroup::"
+          echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }} "
+
+      - env:
+          stepName: Coverity Build & Upload for Scan
           COVERITY_TOKEN: ${{ secrets.COVERITY_SCAN_TOKEN }}
           COVERITY_EMAIL: ${{ secrets.COVERITY_SCAN_EMAIL }}
+        shell: bash
         run: |
+          # ${{ env.stepName }}
+          echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}"
+
           export PATH="$PATH:${{env.cov_scan_path}}"
           cmake -S ./examples/cmake_example/ -B build
           cd build
           cov-build --dir cov-int make -j
-          tar czvf gcc_freertos_kerenl_sample_build.tgz cov-int
+          tar czvf gcc_freertos_kernel_sample_build.tgz cov-int
+
+          echo "::endgroup::"
+          echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }} "
+
+      - env:
+          stepName: Upload Coverity Report for Scan
+          COVERITY_TOKEN: ${{ secrets.COVERITY_SCAN_TOKEN }}
+          COVERITY_EMAIL: ${{ secrets.COVERITY_SCAN_EMAIL }}
+        shell: bash
+        run: |
+          # ${{ env.stepName }}
+          echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}"
+
           COV_SCAN_UPLOAD_STATUS=$(curl --form token=${COVERITY_TOKEN} \
             --form email=${COVERITY_EMAIL} \
-            --form file=@gcc_freertos_kerenl_sample_build.tgz \
+            --form file=@gcc_freertos_kernel_sample_build.tgz \
             --form version="Mainline" \
-            --form description="FreeRTOS Kernel Nightly Scan" \
+            --form description="FreeRTOS Kernel Commit Scan" \
             https://scan.coverity.com/builds?project=FreeRTOS-Kernel)
+
+          echo "::endgroup::"
+          echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }} "
           echo "${COV_SCAN_UPLOAD_STATUS}" | grep -q -e 'Build successfully submitted' || echo >&2 "Error submitting build for analysis: ${COV_SCAN_UPLOAD_STATUS}"

From ac4313560f8d4ec4408a4c425242a4f3467b8c69 Mon Sep 17 00:00:00 2001
From: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Date: Fri, 24 Nov 2023 14:08:34 +0800
Subject: [PATCH 122/424] Not to use object modified in the loop body (#861)

Co-authored-by: Ubuntu <ubuntu@ip-172-31-34-245.ap-northeast-1.compute.internal>
Co-authored-by: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
---
 tasks.c | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/tasks.c b/tasks.c
index 7aa93f7f3..0907d35b9 100644
--- a/tasks.c
+++ b/tasks.c
@@ -7231,7 +7231,7 @@ static void prvResetNextTaskUnblockTime( void )
             uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, NULL );
 
             /* Create a human readable table from the binary data. */
-            for( x = 0; ( x < uxArraySize ) && ( xOutputBufferFull == pdFALSE ); x++ )
+            for( x = 0; x < uxArraySize; x++ )
             {
                 switch( pxTaskStatusArray[ x ].eCurrentState )
                 {
@@ -7310,6 +7310,11 @@ static void prvResetNextTaskUnblockTime( void )
                 {
                     xOutputBufferFull = pdTRUE;
                 }
+
+                if( xOutputBufferFull == pdTRUE )
+                {
+                    break;
+                }
             }
 
             /* Free the array again.  NOTE!  If configSUPPORT_DYNAMIC_ALLOCATION
@@ -7391,7 +7396,7 @@ static void prvResetNextTaskUnblockTime( void )
             if( ulTotalTime > 0UL )
             {
                 /* Create a human readable table from the binary data. */
-                for( x = 0; ( x < uxArraySize ) && ( xOutputBufferFull == pdFALSE ); x++ )
+                for( x = 0; x < uxArraySize; x++ )
                 {
                     /* What percentage of the total run time has the task used?
                      * This will always be rounded down to the nearest integer.
@@ -7472,6 +7477,11 @@ static void prvResetNextTaskUnblockTime( void )
                     {
                         xOutputBufferFull = pdTRUE;
                     }
+
+                    if( xOutputBufferFull == pdTRUE )
+                    {
+                        break;
+                    }
                 }
             }
             else

From 61f35dc6b1ba8707dc6a8afce65ed7b8a3af1c82 Mon Sep 17 00:00:00 2001
From: Tony Josi <tonyjosi@amazon.com>
Date: Mon, 27 Nov 2023 09:20:41 +0530
Subject: [PATCH 123/424] Coverity scan and upload in single step (#902)

---
 .github/workflows/coverity_scan.yml | 12 ------------
 1 file changed, 12 deletions(-)

diff --git a/.github/workflows/coverity_scan.yml b/.github/workflows/coverity_scan.yml
index bd6f77abc..5fa15f736 100644
--- a/.github/workflows/coverity_scan.yml
+++ b/.github/workflows/coverity_scan.yml
@@ -63,18 +63,6 @@ jobs:
           cov-build --dir cov-int make -j
           tar czvf gcc_freertos_kernel_sample_build.tgz cov-int
 
-          echo "::endgroup::"
-          echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }} "
-
-      - env:
-          stepName: Upload Coverity Report for Scan
-          COVERITY_TOKEN: ${{ secrets.COVERITY_SCAN_TOKEN }}
-          COVERITY_EMAIL: ${{ secrets.COVERITY_SCAN_EMAIL }}
-        shell: bash
-        run: |
-          # ${{ env.stepName }}
-          echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}"
-
           COV_SCAN_UPLOAD_STATUS=$(curl --form token=${COVERITY_TOKEN} \
             --form email=${COVERITY_EMAIL} \
             --form file=@gcc_freertos_kernel_sample_build.tgz \

From 76f3aa5b05e5c38e423e83eea23f5b34c15d3316 Mon Sep 17 00:00:00 2001
From: Soren Ptak <ptaksoren@gmail.com>
Date: Tue, 28 Nov 2023 00:08:57 -0500
Subject: [PATCH 124/424] The curl command to send the report expects the tar
 file to be in its current directory. The step either needed to have the
 working-directory: set to the build directory, or the tar file needs to be
 created in the parent directory. (#903)

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
---
 .github/workflows/coverity_scan.yml | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/.github/workflows/coverity_scan.yml b/.github/workflows/coverity_scan.yml
index 5fa15f736..21e7359f6 100644
--- a/.github/workflows/coverity_scan.yml
+++ b/.github/workflows/coverity_scan.yml
@@ -61,7 +61,8 @@ jobs:
           cmake -S ./examples/cmake_example/ -B build
           cd build
           cov-build --dir cov-int make -j
-          tar czvf gcc_freertos_kernel_sample_build.tgz cov-int
+          # Move the report out of the build directory
+          tar czvf ../gcc_freertos_kernel_sample_build.tgz cov-int
 
           COV_SCAN_UPLOAD_STATUS=$(curl --form token=${COVERITY_TOKEN} \
             --form email=${COVERITY_EMAIL} \

From ce88adea2a043dca6104e4fd80b920166cade8c8 Mon Sep 17 00:00:00 2001
From: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Date: Tue, 28 Nov 2023 13:29:07 +0800
Subject: [PATCH 125/424] Fix MISRA C 2012 Rule 10.3 errors (#860)

* The value of an expression shall not be assigned to an object with a narrower essential type or of a different essential type category.
---------

Co-authored-by: Ubuntu <ubuntu@ip-172-31-34-245.ap-northeast-1.compute.internal>
Co-authored-by: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
---
 include/event_groups.h | 24 ++++++++++++------------
 tasks.c                | 16 ++++++++--------
 timers.c               |  2 +-
 3 files changed, 21 insertions(+), 21 deletions(-)

diff --git a/include/event_groups.h b/include/event_groups.h
index 1322eae39..f1f86fb7f 100644
--- a/include/event_groups.h
+++ b/include/event_groups.h
@@ -40,20 +40,20 @@
  * item value.  It is important they don't clash with the
  * taskEVENT_LIST_ITEM_VALUE_IN_USE definition. */
 #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    #define eventCLEAR_EVENTS_ON_EXIT_BIT    0x0100U
-    #define eventUNBLOCKED_DUE_TO_BIT_SET    0x0200U
-    #define eventWAIT_FOR_ALL_BITS           0x0400U
-    #define eventEVENT_BITS_CONTROL_BYTES    0xff00U
+    #define eventCLEAR_EVENTS_ON_EXIT_BIT    ( ( uint16_t ) 0x0100U )
+    #define eventUNBLOCKED_DUE_TO_BIT_SET    ( ( uint16_t ) 0x0200U )
+    #define eventWAIT_FOR_ALL_BITS           ( ( uint16_t ) 0x0400U )
+    #define eventEVENT_BITS_CONTROL_BYTES    ( ( uint16_t ) 0xff00U )
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    #define eventCLEAR_EVENTS_ON_EXIT_BIT    0x01000000UL
-    #define eventUNBLOCKED_DUE_TO_BIT_SET    0x02000000UL
-    #define eventWAIT_FOR_ALL_BITS           0x04000000UL
-    #define eventEVENT_BITS_CONTROL_BYTES    0xff000000UL
+    #define eventCLEAR_EVENTS_ON_EXIT_BIT    ( ( uint32_t ) 0x01000000UL )
+    #define eventUNBLOCKED_DUE_TO_BIT_SET    ( ( uint32_t ) 0x02000000UL )
+    #define eventWAIT_FOR_ALL_BITS           ( ( uint32_t ) 0x04000000UL )
+    #define eventEVENT_BITS_CONTROL_BYTES    ( ( uint32_t ) 0xff000000UL )
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_64_BITS )
-    #define eventCLEAR_EVENTS_ON_EXIT_BIT    0x0100000000000000ULL
-    #define eventUNBLOCKED_DUE_TO_BIT_SET    0x0200000000000000ULL
-    #define eventWAIT_FOR_ALL_BITS           0x0400000000000000ULL
-    #define eventEVENT_BITS_CONTROL_BYTES    0xff00000000000000ULL
+    #define eventCLEAR_EVENTS_ON_EXIT_BIT    ( ( uint64_t ) 0x0100000000000000ULL )
+    #define eventUNBLOCKED_DUE_TO_BIT_SET    ( ( uint64_t ) 0x0200000000000000ULL )
+    #define eventWAIT_FOR_ALL_BITS           ( ( uint64_t ) 0x0400000000000000ULL )
+    #define eventEVENT_BITS_CONTROL_BYTES    ( ( uint64_t ) 0xff00000000000000ULL )
 #endif /* if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) */
 
 /* *INDENT-OFF* */
diff --git a/tasks.c b/tasks.c
index 0907d35b9..50706ad44 100644
--- a/tasks.c
+++ b/tasks.c
@@ -285,11 +285,11 @@
  * responsibility of whichever module is using the value to ensure it gets set back
  * to its original value when it is released. */
 #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    #define taskEVENT_LIST_ITEM_VALUE_IN_USE    0x8000U
+    #define taskEVENT_LIST_ITEM_VALUE_IN_USE    ( ( uint16_t ) 0x8000U )
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    #define taskEVENT_LIST_ITEM_VALUE_IN_USE    0x80000000UL
+    #define taskEVENT_LIST_ITEM_VALUE_IN_USE    ( ( uint32_t ) 0x80000000UL )
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_64_BITS )
-    #define taskEVENT_LIST_ITEM_VALUE_IN_USE    0x8000000000000000ULL
+    #define taskEVENT_LIST_ITEM_VALUE_IN_USE    ( ( uint64_t ) 0x8000000000000000ULL )
 #endif
 
 /* Indicates that the task is not actively running on any core. */
@@ -2871,7 +2871,7 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
 
                 /* Only reset the event list item value if the value is not
                  * being used for anything else. */
-                if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
+                if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == ( ( TickType_t ) 0UL ) )
                 {
                     listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxNewPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
                 }
@@ -6559,7 +6559,7 @@ static void prvResetNextTaskUnblockTime( void )
                 /* Adjust the mutex holder state to account for its new
                  * priority.  Only reset the event list item value if the value is
                  * not being used for anything else. */
-                if( ( listGET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
+                if( ( listGET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == ( ( TickType_t ) 0UL ) )
                 {
                     listSET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
                 }
@@ -6788,7 +6788,7 @@ static void prvResetNextTaskUnblockTime( void )
 
                     /* Only reset the event list item value if the value is not
                      * being used for anything else. */
-                    if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
+                    if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == ( ( TickType_t ) 0UL ) )
                     {
                         listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriorityToUse ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
                     }
@@ -7390,7 +7390,7 @@ static void prvResetNextTaskUnblockTime( void )
             uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalTime );
 
             /* For percentage calculations. */
-            ulTotalTime /= 100UL;
+            ulTotalTime /= ( ( configRUN_TIME_COUNTER_TYPE ) 100UL );
 
             /* Avoid divide by zero errors. */
             if( ulTotalTime > 0UL )
@@ -7642,7 +7642,7 @@ TickType_t uxTaskResetEventItemValue( void )
             {
                 if( xClearCountOnExit != pdFALSE )
                 {
-                    pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ] = 0UL;
+                    pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ] = ( uint32_t ) 0UL;
                 }
                 else
                 {
diff --git a/timers.c b/timers.c
index bff14ea7e..2f575627a 100644
--- a/timers.c
+++ b/timers.c
@@ -1127,7 +1127,7 @@
                 }
                 #else
                 {
-                    xTimerQueue = xQueueCreate( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, sizeof( DaemonTaskMessage_t ) );
+                    xTimerQueue = xQueueCreate( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ) );
                 }
                 #endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
 

From 1813a4551e4edbba215b6f1cb3c484c41d369f96 Mon Sep 17 00:00:00 2001
From: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Date: Tue, 28 Nov 2023 19:21:03 +0800
Subject: [PATCH 126/424] Fix MISRA 2012 rule 10.4 violations (#852)

Fix MISRA 2012 rule 10.4 violations
---
 queue.c         |  8 ++++----
 stream_buffer.c |  2 +-
 tasks.c         | 34 +++++++++++++++++-----------------
 timers.c        | 10 +++++-----
 4 files changed, 27 insertions(+), 27 deletions(-)

diff --git a/queue.c b/queue.c
index 3bc959721..ffb180ec8 100644
--- a/queue.c
+++ b/queue.c
@@ -389,8 +389,8 @@ BaseType_t xQueueGenericReset( QueueHandle_t xQueue,
 
             /* A queue storage area should be provided if the item size is not 0, and
              * should not be provided if the item size is 0. */
-            ( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) ) &&
-            ( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) ) )
+            ( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0U ) ) ) &&
+            ( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0U ) ) ) )
         {
             #if ( configASSERT_DEFINED == 1 )
             {
@@ -864,7 +864,7 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength,
 
         traceENTER_xQueueCreateCountingSemaphoreStatic( uxMaxCount, uxInitialCount, pxStaticQueue );
 
-        if( ( uxMaxCount != 0 ) &&
+        if( ( uxMaxCount != 0U ) &&
             ( uxInitialCount <= uxMaxCount ) )
         {
             xHandle = xQueueGenericCreateStatic( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticQueue, queueQUEUE_TYPE_COUNTING_SEMAPHORE );
@@ -903,7 +903,7 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength,
 
         traceENTER_xQueueCreateCountingSemaphore( uxMaxCount, uxInitialCount );
 
-        if( ( uxMaxCount != 0 ) &&
+        if( ( uxMaxCount != 0U ) &&
             ( uxInitialCount <= uxMaxCount ) )
         {
             xHandle = xQueueGenericCreate( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_COUNTING_SEMAPHORE );
diff --git a/stream_buffer.c b/stream_buffer.c
index 32aa8e4f2..10123b916 100644
--- a/stream_buffer.c
+++ b/stream_buffer.c
@@ -362,7 +362,7 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
          * this is a quirk of the implementation that means otherwise the free
          * space would be reported as one byte smaller than would be logically
          * expected. */
-        if( xBufferSizeBytes < ( xBufferSizeBytes + 1 + sizeof( StreamBuffer_t ) ) )
+        if( xBufferSizeBytes < ( xBufferSizeBytes + 1U + sizeof( StreamBuffer_t ) ) )
         {
             xBufferSizeBytes++;
             pvAllocatedMemory = pvPortMalloc( xBufferSizeBytes + sizeof( StreamBuffer_t ) );
diff --git a/tasks.c b/tasks.c
index 50706ad44..c83912dd2 100644
--- a/tasks.c
+++ b/tasks.c
@@ -962,7 +962,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
 
             #if ( configRUN_MULTIPLE_PRIORITIES == 0 )
                 /* Verify that the calling core always yields to higher priority tasks. */
-                if( ( ( pxCurrentTCBs[ portGET_CORE_ID() ]->uxTaskAttributes & taskATTRIBUTE_IS_IDLE ) == 0 ) &&
+                if( ( ( pxCurrentTCBs[ portGET_CORE_ID() ]->uxTaskAttributes & taskATTRIBUTE_IS_IDLE ) == 0U ) &&
                     ( pxTCB->uxPriority > pxCurrentTCBs[ portGET_CORE_ID() ]->uxPriority ) )
                 {
                     configASSERT( ( xYieldPendings[ portGET_CORE_ID() ] == pdTRUE ) ||
@@ -1044,7 +1044,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
                          * idle tasks, not user tasks at the idle priority. */
                         if( uxCurrentPriority < uxTopReadyPriority )
                         {
-                            if( ( pxTCB->uxTaskAttributes & taskATTRIBUTE_IS_IDLE ) == 0 )
+                            if( ( pxTCB->uxTaskAttributes & taskATTRIBUTE_IS_IDLE ) == 0U )
                             {
                                 continue;
                             }
@@ -1136,7 +1136,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
 
                     for( x = ( BaseType_t ) 0; x < ( BaseType_t ) configNUMBER_OF_CORES; x++ )
                     {
-                        if( ( pxCurrentTCBs[ x ]->uxTaskAttributes & taskATTRIBUTE_IS_IDLE ) != 0 )
+                        if( ( pxCurrentTCBs[ x ]->uxTaskAttributes & taskATTRIBUTE_IS_IDLE ) != 0U )
                         {
                             prvYieldCore( x );
                         }
@@ -1854,7 +1854,7 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
 
         /* Ensure the name string is terminated in the case that the string length
          * was greater or equal to configMAX_TASK_NAME_LEN. */
-        pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0';
+        pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1U ] = '\0';
     }
     else
     {
@@ -2165,7 +2165,7 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
              * large to hold the generated string. Return the
              * number of characters actually written without
              * counting the terminating NULL character. */
-            uxCharsWritten = n - 1;
+            uxCharsWritten = n - 1U;
         }
         else
         {
@@ -3873,7 +3873,7 @@ void vTaskSuspendAll( void )
         {
             xReturn = 0;
         }
-        else if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > 1 )
+        else if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > 1U )
         {
             /* There are other idle priority tasks in the ready state.  If
              * time slicing is used then the very next tick interrupt must be
@@ -4813,7 +4813,7 @@ BaseType_t xTaskIncrementTick( void )
         {
             #if ( configNUMBER_OF_CORES == 1 )
             {
-                if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 )
+                if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > 1U )
                 {
                     xSwitchRequired = pdTRUE;
                 }
@@ -4828,7 +4828,7 @@ BaseType_t xTaskIncrementTick( void )
 
                 for( xCoreID = 0; xCoreID < ( ( BaseType_t ) configNUMBER_OF_CORES ); xCoreID++ )
                 {
-                    if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCBs[ xCoreID ]->uxPriority ] ) ) > 1 )
+                    if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCBs[ xCoreID ]->uxPriority ] ) ) > 1U )
                     {
                         xYieldRequiredForCore[ xCoreID ] = pdTRUE;
                     }
@@ -5807,7 +5807,7 @@ static portTASK_FUNCTION( prvIdleTask, pvParameters )
              * valid. */
             xExpectedIdleTime = prvGetExpectedIdleTime();
 
-            if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP )
+            if( xExpectedIdleTime >= ( TickType_t ) configEXPECTED_IDLE_TIME_BEFORE_SLEEP )
             {
                 vTaskSuspendAll();
                 {
@@ -5822,7 +5822,7 @@ static portTASK_FUNCTION( prvIdleTask, pvParameters )
                      * portSUPPRESS_TICKS_AND_SLEEP() to be called. */
                     configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( xExpectedIdleTime );
 
-                    if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP )
+                    if( xExpectedIdleTime >= ( TickType_t ) configEXPECTED_IDLE_TIME_BEFORE_SLEEP )
                     {
                         traceLOW_POWER_IDLE_BEGIN();
                         portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime );
@@ -5874,7 +5874,7 @@ static portTASK_FUNCTION( prvIdleTask, pvParameters )
 
         /* This function must be called from a critical section. */
 
-        if( listCURRENT_LIST_LENGTH( &xPendingReadyList ) != 0 )
+        if( listCURRENT_LIST_LENGTH( &xPendingReadyList ) != 0U )
         {
             /* A task was made ready while the scheduler was suspended. */
             eReturn = eAbortSleep;
@@ -5884,7 +5884,7 @@ static portTASK_FUNCTION( prvIdleTask, pvParameters )
             /* A yield was pended while the scheduler was suspended. */
             eReturn = eAbortSleep;
         }
-        else if( xPendedTicks != 0 )
+        else if( xPendedTicks != 0U )
         {
             /* A tick interrupt has already occurred but was held pending
              * because the scheduler is suspended. */
@@ -6898,7 +6898,7 @@ static void prvResetNextTaskUnblockTime( void )
              * interrupt.  Only assert if the critical nesting count is 1 to
              * protect against recursive calls if the assert function also uses a
              * critical section. */
-            if( pxCurrentTCB->uxCriticalNesting == 1 )
+            if( pxCurrentTCB->uxCriticalNesting == 1U )
             {
                 portASSERT_IF_IN_ISR();
             }
@@ -7269,13 +7269,13 @@ static void prvResetNextTaskUnblockTime( void )
                      * can be printed in tabular form more easily. */
                     pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName );
                     /* Do not count the terminating null character. */
-                    uxConsumedBufferLength = uxConsumedBufferLength + ( configMAX_TASK_NAME_LEN - 1 );
+                    uxConsumedBufferLength = uxConsumedBufferLength + ( configMAX_TASK_NAME_LEN - 1U );
 
                     /* Is there space left in the buffer? -1 is done because snprintf
                      * writes a terminating null character. So we are essentially
                      * checking if the buffer has space to write at least one non-null
                      * character. */
-                    if( uxConsumedBufferLength < ( uxBufferLength - 1 ) )
+                    if( uxConsumedBufferLength < ( uxBufferLength - 1U ) )
                     {
                         /* Write the rest of the string. */
                         #if ( ( configUSE_CORE_AFFINITY == 1 ) && ( configNUMBER_OF_CORES > 1 ) )
@@ -7411,13 +7411,13 @@ static void prvResetNextTaskUnblockTime( void )
                          * easily. */
                         pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName );
                         /* Do not count the terminating null character. */
-                        uxConsumedBufferLength = uxConsumedBufferLength + ( configMAX_TASK_NAME_LEN - 1 );
+                        uxConsumedBufferLength = uxConsumedBufferLength + ( configMAX_TASK_NAME_LEN - 1U );
 
                         /* Is there space left in the buffer? -1 is done because snprintf
                          * writes a terminating null character. So we are essentially
                          * checking if the buffer has space to write at least one non-null
                          * character. */
-                        if( uxConsumedBufferLength < ( uxBufferLength - 1 ) )
+                        if( uxConsumedBufferLength < ( uxBufferLength - 1U ) )
                         {
                             if( ulStatsAsPercentage > 0UL )
                             {
diff --git a/timers.c b/timers.c
index 2f575627a..878e7db11 100644
--- a/timers.c
+++ b/timers.c
@@ -603,7 +603,7 @@
         configASSERT( xTimer );
         taskENTER_CRITICAL();
         {
-            if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) == 0 )
+            if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) == 0U )
             {
                 /* Not an auto-reload timer. */
                 xReturn = pdFALSE;
@@ -662,7 +662,7 @@
 
             configASSERT( ppxTimerBuffer != NULL );
 
-            if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) != 0 )
+            if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) != 0U )
             {
                 *ppxTimerBuffer = ( StaticTimer_t * ) pxTimer;
                 xReturn = pdTRUE;
@@ -724,7 +724,7 @@
 
         /* If the timer is an auto-reload timer then calculate the next
          * expiry time and re-insert the timer in the list of active timers. */
-        if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
+        if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0U )
         {
             prvReloadTimer( pxTimer, xNextExpireTime, xTimeNow );
         }
@@ -1001,7 +1001,7 @@
                         {
                             /* The timer expired before it was added to the active
                              * timer list.  Process it now. */
-                            if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
+                            if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0U )
                             {
                                 prvReloadTimer( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow );
                             }
@@ -1165,7 +1165,7 @@
         /* Is the timer in the list of active timers? */
         taskENTER_CRITICAL();
         {
-            if( ( pxTimer->ucStatus & tmrSTATUS_IS_ACTIVE ) == 0 )
+            if( ( pxTimer->ucStatus & tmrSTATUS_IS_ACTIVE ) == 0U )
             {
                 xReturn = pdFALSE;
             }

From f2637bae55405b11c8ea80e919bfab16ef4dd26b Mon Sep 17 00:00:00 2001
From: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Date: Tue, 28 Nov 2023 19:34:13 +0800
Subject: [PATCH 127/424] Fix MISRA 2012 Rule 10.8 violation (#853)

Co-authored-by: Ubuntu <ubuntu@ip-172-31-34-245.ap-northeast-1.compute.internal>
Co-authored-by: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
---
 queue.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/queue.c b/queue.c
index ffb180ec8..6429307ec 100644
--- a/queue.c
+++ b/queue.c
@@ -509,7 +509,7 @@ BaseType_t xQueueGenericReset( QueueHandle_t xQueue,
             /* Allocate enough space to hold the maximum number of items that
              * can be in the queue at any time.  It is valid for uxItemSize to be
              * zero in the case the queue is used as a semaphore. */
-            xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+            xQueueSizeInBytes = ( size_t ) ( ( size_t ) uxQueueLength * ( size_t ) uxItemSize );
 
             /* Allocate the queue and storage area.  Justification for MISRA
              * deviation as follows:  pvPortMalloc() always ensures returned memory

From dabbc05a39977e1d414b9885f5ee4f8c32c74691 Mon Sep 17 00:00:00 2001
From: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Date: Tue, 28 Nov 2023 21:34:29 +0800
Subject: [PATCH 128/424] Suppress MISRA C rule 11.3 in MISRA.md (#857)

Suppress MISRA C rule 11.3 in MISRA.md
---
 MISRA.md        | 21 ++++++++++++++++++++-
 event_groups.c  | 11 ++++++++++-
 queue.c         |  8 +++++++-
 stream_buffer.c | 13 +++++++++++--
 tasks.c         |  8 +++++++-
 timers.c        |  8 +++++++-
 6 files changed, 62 insertions(+), 7 deletions(-)

diff --git a/MISRA.md b/MISRA.md
index e7ebf77ea..b6a5ee197 100644
--- a/MISRA.md
+++ b/MISRA.md
@@ -31,6 +31,25 @@ _Ref 8.4.1_
         a declaration in header file is not useful as the assembly code will
         still need to declare it separately.
 
+
+#### Rule 11.3
+
+_Ref 11.3.1_
+
+- MISRA C:2012 Rule 11.3: A cast shall not be performed between a pointer to
+        object type and a pointer to a different object type.
+        This rule prohibits casting a pointer to object into a pointer to a
+        different object because it may result in an incorrectly aligned pointer,
+        leading to undefined behavior. Even if the casting produces a correctly
+        aligned pointer, the behavior may be still undefined if the pointer is
+        used to access an object. FreeRTOS deliberately creates external aliases
+        for all the kernel object types (StaticEventGroup_t, StaticQueue_t,
+        StaticStreamBuffer_t, StaticTimer_t and StaticTask_t) for data hiding
+        purposes. The internal object types and the corresponding external
+        aliases are guaranteed to have the same size and alignment which is
+        checked using configASSERT.
+
+
 ### MISRA configuration
 
 Copy below content to `misra.conf` to run Coverity on FreeRTOS-Kernel.
@@ -69,4 +88,4 @@ Copy below content to `misra.conf` to run Coverity on FreeRTOS-Kernel.
         }
     ]
 }
-```
\ No newline at end of file
+```
diff --git a/event_groups.c b/event_groups.c
index 556637b4c..e6fc7e68c 100644
--- a/event_groups.c
+++ b/event_groups.c
@@ -98,7 +98,10 @@ static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits,
         #endif /* configASSERT_DEFINED */
 
         /* The user has provided a statically allocated event group - use it. */
-        pxEventBits = ( EventGroup_t * ) pxEventGroupBuffer; /*lint !e740 !e9087 EventGroup_t and StaticEventGroup_t are deliberately aliased for data hiding purposes and guaranteed to have the same size and alignment requirement - checked by configASSERT(). */
+        /* MISRA Ref 11.3.1 [Misaligned access] */
+        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */
+        /* coverity[misra_c_2012_rule_11_3_violation] */
+        pxEventBits = ( EventGroup_t * ) pxEventGroupBuffer;
 
         if( pxEventBits != NULL )
         {
@@ -710,6 +713,9 @@ void vEventGroupDelete( EventGroupHandle_t xEventGroup )
             /* Check if the event group was statically allocated. */
             if( pxEventBits->ucStaticallyAllocated == ( uint8_t ) pdTRUE )
             {
+                /* MISRA Ref 11.3.1 [Misaligned access] */
+                /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */
+                /* coverity[misra_c_2012_rule_11_3_violation] */
                 *ppxEventGroupBuffer = ( StaticEventGroup_t * ) pxEventBits;
                 xReturn = pdTRUE;
             }
@@ -721,6 +727,9 @@ void vEventGroupDelete( EventGroupHandle_t xEventGroup )
         #else /* configSUPPORT_DYNAMIC_ALLOCATION */
         {
             /* Event group must have been statically allocated. */
+            /* MISRA Ref 11.3.1 [Misaligned access] */
+            /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */
+            /* coverity[misra_c_2012_rule_11_3_violation] */
             *ppxEventGroupBuffer = ( StaticEventGroup_t * ) pxEventBits;
             xReturn = pdTRUE;
         }
diff --git a/queue.c b/queue.c
index 6429307ec..00eed7351 100644
--- a/queue.c
+++ b/queue.c
@@ -408,7 +408,10 @@ BaseType_t xQueueGenericReset( QueueHandle_t xQueue,
             /* The address of a statically allocated queue was passed in, use it.
              * The address of a statically allocated storage area was also passed in
              * but is already set. */
-            pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
+            /* MISRA Ref 11.3.1 [Misaligned access] */
+            /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */
+            /* coverity[misra_c_2012_rule_11_3_violation] */
+            pxNewQueue = ( Queue_t * ) pxStaticQueue;
 
             #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
             {
@@ -459,6 +462,9 @@ BaseType_t xQueueGenericReset( QueueHandle_t xQueue,
                     *ppucQueueStorage = ( uint8_t * ) pxQueue->pcHead;
                 }
 
+                /* MISRA Ref 11.3.1 [Misaligned access] */
+                /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */
+                /* coverity[misra_c_2012_rule_11_3_violation] */
                 *ppxStaticQueue = ( StaticQueue_t * ) pxQueue;
                 xReturn = pdTRUE;
             }
diff --git a/stream_buffer.c b/stream_buffer.c
index 10123b916..47e82512f 100644
--- a/stream_buffer.c
+++ b/stream_buffer.c
@@ -406,7 +406,10 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
                                                            StreamBufferCallbackFunction_t pxSendCompletedCallback,
                                                            StreamBufferCallbackFunction_t pxReceiveCompletedCallback )
     {
-        StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) pxStaticStreamBuffer; /*lint !e740 !e9087 Safe cast as StaticStreamBuffer_t is opaque Streambuffer_t. */
+        /* MISRA Ref 11.3.1 [Misaligned access] */
+        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */
+        /* coverity[misra_c_2012_rule_11_3_violation] */
+        StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) pxStaticStreamBuffer;
         StreamBufferHandle_t xReturn;
         uint8_t ucFlags;
 
@@ -466,7 +469,10 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
 
             traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xIsMessageBuffer );
 
-            xReturn = ( StreamBufferHandle_t ) pxStaticStreamBuffer; /*lint !e9087 Data hiding requires cast to opaque type. */
+            /* MISRA Ref 11.3.1 [Misaligned access] */
+            /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */
+            /* coverity[misra_c_2012_rule_11_3_violation] */
+            xReturn = ( StreamBufferHandle_t ) pxStaticStreamBuffer;
         }
         else
         {
@@ -498,6 +504,9 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
         if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_STATICALLY_ALLOCATED ) != ( uint8_t ) 0 )
         {
             *ppucStreamBufferStorageArea = pxStreamBuffer->pucBuffer;
+            /* MISRA Ref 11.3.1 [Misaligned access] */
+            /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */
+            /* coverity[misra_c_2012_rule_11_3_violation] */
             *ppxStaticStreamBuffer = ( StaticStreamBuffer_t * ) pxStreamBuffer;
             xReturn = pdTRUE;
         }
diff --git a/tasks.c b/tasks.c
index c83912dd2..4a6c78a8c 100644
--- a/tasks.c
+++ b/tasks.c
@@ -1271,7 +1271,10 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
         {
             /* The memory used for the task's TCB and stack are passed into this
              * function - use them. */
-            pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
+            /* MISRA Ref 11.3.1 [Misaligned access] */
+            /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */
+            /* coverity[misra_c_2012_rule_11_3_violation] */
+            pxNewTCB = ( TCB_t * ) pxTaskBuffer;
             ( void ) memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) );
             pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer;
 
@@ -4354,6 +4357,9 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char
             if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB )
             {
                 *ppuxStackBuffer = pxTCB->pxStack;
+                /* MISRA Ref 11.3.1 [Misaligned access] */
+                /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */
+                /* coverity[misra_c_2012_rule_11_3_violation] */
                 *ppxTaskBuffer = ( StaticTask_t * ) pxTCB;
                 xReturn = pdTRUE;
             }
diff --git a/timers.c b/timers.c
index 878e7db11..b5a8d3846 100644
--- a/timers.c
+++ b/timers.c
@@ -394,7 +394,10 @@
 
             /* A pointer to a StaticTimer_t structure MUST be provided, use it. */
             configASSERT( pxTimerBuffer );
-            pxNewTimer = ( Timer_t * ) pxTimerBuffer; /*lint !e740 !e9087 StaticTimer_t is a pointer to a Timer_t, so guaranteed to be aligned and sized correctly (checked by an assert()), so this is safe. */
+            /* MISRA Ref 11.3.1 [Misaligned access] */
+            /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */
+            /* coverity[misra_c_2012_rule_11_3_violation] */
+            pxNewTimer = ( Timer_t * ) pxTimerBuffer;
 
             if( pxNewTimer != NULL )
             {
@@ -664,6 +667,9 @@
 
             if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) != 0U )
             {
+                /* MISRA Ref 11.3.1 [Misaligned access] */
+                /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */
+                /* coverity[misra_c_2012_rule_11_3_violation] */
                 *ppxTimerBuffer = ( StaticTimer_t * ) pxTimer;
                 xReturn = pdTRUE;
             }

From a2a4485ed3050bcc2271688f0e253009be38751a Mon Sep 17 00:00:00 2001
From: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Date: Tue, 28 Nov 2023 19:16:15 +0530
Subject: [PATCH 129/424] Coverity Report Directory Fix (#909)

* Revert "The curl command to send the report expects the tar file to be in its current directory. The step either needed to have the working-directory: set to the build directory, or the tar file needs to be created in the parent directory. (#903)"

This reverts commit 76f3aa5b05e5c38e423e83eea23f5b34c15d3316.

* Update to separate build and upload steps

---------

Co-authored-by: tony-josi-aws <tonyjosi@amazon.com>
---
 .github/workflows/coverity_scan.yml | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/.github/workflows/coverity_scan.yml b/.github/workflows/coverity_scan.yml
index 21e7359f6..85db51800 100644
--- a/.github/workflows/coverity_scan.yml
+++ b/.github/workflows/coverity_scan.yml
@@ -49,7 +49,7 @@ jobs:
           echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }} "
 
       - env:
-          stepName: Coverity Build & Upload for Scan
+          stepName: Coverity Build
           COVERITY_TOKEN: ${{ secrets.COVERITY_SCAN_TOKEN }}
           COVERITY_EMAIL: ${{ secrets.COVERITY_SCAN_EMAIL }}
         shell: bash
@@ -64,6 +64,18 @@ jobs:
           # Move the report out of the build directory
           tar czvf ../gcc_freertos_kernel_sample_build.tgz cov-int
 
+          echo "::endgroup::"
+          echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }} "
+
+      - env:
+          stepName: Upload Coverity Report for Scan
+          COVERITY_TOKEN: ${{ secrets.COVERITY_SCAN_TOKEN }}
+          COVERITY_EMAIL: ${{ secrets.COVERITY_SCAN_EMAIL }}
+        shell: bash
+        run: |
+          # ${{ env.stepName }}
+          echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}"
+
           COV_SCAN_UPLOAD_STATUS=$(curl --form token=${COVERITY_TOKEN} \
             --form email=${COVERITY_EMAIL} \
             --form file=@gcc_freertos_kernel_sample_build.tgz \

From 147f34ab5f36c6d59f709a8a38dd2606eb2fe00e Mon Sep 17 00:00:00 2001
From: Soren Ptak <ptaksoren@gmail.com>
Date: Tue, 28 Nov 2023 13:56:15 -0500
Subject: [PATCH 130/424] Revert Portable/Renesas formatting (#876)

* Revert the formatting on Renesas ports
---
 portable/Renesas/RX100/port.c              | 294 +++++------
 portable/Renesas/RX100/portmacro.h         | 100 ++--
 portable/Renesas/RX200/port.c              | 147 +++---
 portable/Renesas/RX200/portmacro.h         |  98 ++--
 portable/Renesas/RX600/port.c              | 153 +++---
 portable/Renesas/RX600/portmacro.h         |  98 ++--
 portable/Renesas/RX600v2/port.c            | 205 ++++----
 portable/Renesas/RX600v2/portmacro.h       |  98 ++--
 portable/Renesas/RX700v3_DPFPU/port.c      | 570 +++++++++++----------
 portable/Renesas/RX700v3_DPFPU/portmacro.h | 132 +++--
 10 files changed, 932 insertions(+), 963 deletions(-)

diff --git a/portable/Renesas/RX100/port.c b/portable/Renesas/RX100/port.c
index 1c5a98930..9e8db4f04 100644
--- a/portable/Renesas/RX100/port.c
+++ b/portable/Renesas/RX100/port.c
@@ -27,8 +27,8 @@
  */
 
 /*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the RX100 port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the RX100 port.
+ *----------------------------------------------------------*/
 
 /* Standard C includes. */
 #include "limits.h"
@@ -46,35 +46,35 @@
 /*-----------------------------------------------------------*/
 
 /* Tasks should start with interrupts enabled and in Supervisor mode, therefore
- * PSW is set with U and I set, and PM and IPL clear. */
-#define portINITIAL_PSW    ( ( StackType_t ) 0x00030000 )
+PSW is set with U and I set, and PM and IPL clear. */
+#define portINITIAL_PSW     ( ( StackType_t ) 0x00030000 )
 
 /* The peripheral clock is divided by this value before being supplying the
- * CMT. */
+CMT. */
 #if ( configUSE_TICKLESS_IDLE == 0 )
     /* If tickless idle is not used then the divisor can be fixed. */
-    #define portCLOCK_DIVISOR    8UL
+    #define portCLOCK_DIVISOR   8UL
 #elif ( configPERIPHERAL_CLOCK_HZ >= 12000000 )
-    #define portCLOCK_DIVISOR    512UL
+    #define portCLOCK_DIVISOR   512UL
 #elif ( configPERIPHERAL_CLOCK_HZ >= 6000000 )
-    #define portCLOCK_DIVISOR    128UL
+    #define portCLOCK_DIVISOR   128UL
 #elif ( configPERIPHERAL_CLOCK_HZ >= 1000000 )
-    #define portCLOCK_DIVISOR    32UL
+    #define portCLOCK_DIVISOR   32UL
 #else
-    #define portCLOCK_DIVISOR    8UL
+    #define portCLOCK_DIVISOR   8UL
 #endif
 
 
 /* Keys required to lock and unlock access to certain system registers
- * respectively. */
-#define portUNLOCK_KEY    0xA50B
-#define portLOCK_KEY      0xA500
+respectively. */
+#define portUNLOCK_KEY      0xA50B
+#define portLOCK_KEY        0xA500
 
 /*-----------------------------------------------------------*/
 
 /* The following lines are to ensure vSoftwareInterruptEntry can be referenced,
- * and therefore installed in the vector table, when the FreeRTOS code is built
- * as a library. */
+ and therefore installed in the vector table, when the FreeRTOS code is built
+as a library. */
 extern BaseType_t vSoftwareInterruptEntry;
 const BaseType_t * p_vSoftwareInterruptEntry = &vSoftwareInterruptEntry;
 
@@ -109,10 +109,9 @@ void vSoftwareInterruptISR( void );
  */
 static void prvSetupTimerInterrupt( void );
 #ifndef configSETUP_TICK_INTERRUPT
-
-/* The user has not provided their own tick interrupt configuration so use
- * the definition in this file (which uses the interval timer). */
-    #define configSETUP_TICK_INTERRUPT()    prvSetupTimerInterrupt()
+    /* The user has not provided their own tick interrupt configuration so use
+    the definition in this file (which uses the interval timer). */
+    #define configSETUP_TICK_INTERRUPT() prvSetupTimerInterrupt()
 #endif /* configSETUP_TICK_INTERRUPT */
 
 /*
@@ -127,7 +126,7 @@ static void prvSetupTimerInterrupt( void );
 /*-----------------------------------------------------------*/
 
 /* These is accessed by the inline assembler functions. */
-extern void * pxCurrentTCB;
+extern void *pxCurrentTCB;
 extern void vTaskSwitchContext( void );
 
 /*-----------------------------------------------------------*/
@@ -137,35 +136,33 @@ static const uint32_t ulMatchValueForOneTick = ( ( configPERIPHERAL_CLOCK_HZ / p
 
 #if configUSE_TICKLESS_IDLE == 1
 
-/* Holds the maximum number of ticks that can be suppressed - which is
- * basically how far into the future an interrupt can be generated. Set
- * during initialisation.  This is the maximum possible value that the
- * compare match register can hold divided by ulMatchValueForOneTick. */
+    /* Holds the maximum number of ticks that can be suppressed - which is
+    basically how far into the future an interrupt can be generated. Set
+    during initialisation.  This is the maximum possible value that the
+    compare match register can hold divided by ulMatchValueForOneTick. */
     static const TickType_t xMaximumPossibleSuppressedTicks = USHRT_MAX / ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
 
-/* Flag set from the tick interrupt to allow the sleep processing to know if
- * sleep mode was exited because of a tick interrupt, or an interrupt
- * generated by something else. */
+    /* Flag set from the tick interrupt to allow the sleep processing to know if
+    sleep mode was exited because of a tick interrupt, or an interrupt
+    generated by something else. */
     static volatile uint32_t ulTickFlag = pdFALSE;
 
-/* The CMT counter is stopped temporarily each time it is re-programmed.
- * The following constant offsets the CMT counter match value by the number of
- * CMT counts that would typically be missed while the counter was stopped to
- * compensate for the lost time.  The large difference between the divided CMT
- * clock and the CPU clock means it is likely ulStoppedTimerCompensation will
- * equal zero - and be optimised away. */
+    /* The CMT counter is stopped temporarily each time it is re-programmed.
+    The following constant offsets the CMT counter match value by the number of
+    CMT counts that would typically be missed while the counter was stopped to
+    compensate for the lost time.  The large difference between the divided CMT
+    clock and the CPU clock means it is likely ulStoppedTimerCompensation will
+    equal zero - and be optimised away. */
     static const uint32_t ulStoppedTimerCompensation = 100UL / ( configCPU_CLOCK_HZ / ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) );
 
-#endif /* if configUSE_TICKLESS_IDLE == 1 */
+#endif
 
 /*-----------------------------------------------------------*/
 
 /*
  * See header file for description.
  */
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
 {
     /* Offset to end up on 8 byte boundary. */
     pxTopOfStack--;
@@ -180,8 +177,8 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
     *pxTopOfStack = ( StackType_t ) pxCode;
 
     /* When debugging it can be useful if every register is set to a known
-     * value.  Otherwise code space can be saved by just setting the registers
-     * that need to be set. */
+    value.  Otherwise code space can be saved by just setting the registers
+    that need to be set. */
     #ifdef USE_FULL_REGISTER_INITIALISATION
     {
         pxTopOfStack--;
@@ -214,19 +211,19 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
         *pxTopOfStack = 0x22222222;
         pxTopOfStack--;
     }
-    #else /* ifdef USE_FULL_REGISTER_INITIALISATION */
+    #else
     {
         /* Leave space for the registers that will get popped from the stack
-         * when the task first starts executing. */
+        when the task first starts executing. */
         pxTopOfStack -= 15;
     }
-    #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */
+    #endif
 
     *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
     pxTopOfStack--;
-    *pxTopOfStack = 0x12345678;                   /* Accumulator. */
+    *pxTopOfStack = 0x12345678; /* Accumulator. */
     pxTopOfStack--;
-    *pxTopOfStack = 0x87654321;                   /* Accumulator. */
+    *pxTopOfStack = 0x87654321; /* Accumulator. */
 
     return pxTopOfStack;
 }
@@ -238,10 +235,10 @@ BaseType_t xPortStartScheduler( void )
     if( pxCurrentTCB != NULL )
     {
         /* Call an application function to set up the timer that will generate
-         * the tick interrupt.  This way the application can decide which
-         * peripheral to use.  If tickless mode is used then the default
-         * implementation defined in this file (which uses CMT0) should not be
-         * overridden. */
+        the tick interrupt.  This way the application can decide which
+        peripheral to use.  If tickless mode is used then the default
+        implementation defined in this file (which uses CMT0) should not be
+        overridden. */
         configSETUP_TICK_INTERRUPT();
 
         /* Enable the software interrupt. */
@@ -258,11 +255,11 @@ BaseType_t xPortStartScheduler( void )
     }
 
     /* Execution should not reach here as the tasks are now running!
-     * prvSetupTimerInterrupt() is called here to prevent the compiler outputting
-     * a warning about a statically declared function not being referenced in the
-     * case that the application writer has provided their own tick interrupt
-     * configuration routine (and defined configSETUP_TICK_INTERRUPT() such that
-     * their own routine will be called in place of prvSetupTimerInterrupt()). */
+    prvSetupTimerInterrupt() is called here to prevent the compiler outputting
+    a warning about a statically declared function not being referenced in the
+    case that the application writer has provided their own tick interrupt
+    configuration routine (and defined configSETUP_TICK_INTERRUPT() such that
+    their own routine will be called in place of prvSetupTimerInterrupt()). */
     prvSetupTimerInterrupt();
 
     /* Just to make sure the function is not optimised away. */
@@ -277,26 +274,26 @@ BaseType_t xPortStartScheduler( void )
 static void prvStartFirstTask( void )
 {
     /* When starting the scheduler there is nothing that needs moving to the
-     * interrupt stack because the function is not called from an interrupt.
-     * Just ensure the current stack is the user stack. */
-    SETPSW U
+    interrupt stack because the function is not called from an interrupt.
+    Just ensure the current stack is the user stack. */
+    SETPSW  U
 
     /* Obtain the location of the stack associated with which ever task
-     * pxCurrentTCB is currently pointing to. */
-    MOV.L   # _pxCurrentTCB, R15
-        MOV.L[ R15 ], R15
-        MOV.L[ R15 ], R0
+    pxCurrentTCB is currently pointing to. */
+    MOV.L   #_pxCurrentTCB, R15
+    MOV.L   [R15], R15
+    MOV.L   [R15], R0
 
     /* Restore the registers from the stack of the task pointed to by
-     * pxCurrentTCB. */
-    POP R15
-    MVTACLO R15   /* Accumulator low 32 bits. */
-    POP R15
-    MVTACHI R15   /* Accumulator high 32 bits. */
-    POPM R1 - R15 /* R1 to R15 - R0 is not included as it is the SP. */
-    RTE           /* This pops the remaining registers. */
+    pxCurrentTCB. */
+    POP     R15
+    MVTACLO R15         /* Accumulator low 32 bits. */
+    POP     R15
+    MVTACHI R15         /* Accumulator high 32 bits. */
+    POPM    R1-R15      /* R1 to R15 - R0 is not included as it is the SP. */
+    RTE                 /* This pops the remaining registers. */
+    NOP
     NOP
-        NOP
 }
 /*-----------------------------------------------------------*/
 
@@ -304,7 +301,7 @@ static void prvStartFirstTask( void )
 void prvTickISR( void )
 {
     /* Increment the tick, and perform any processing the new tick value
-     * necessitates. */
+    necessitates. */
     set_ipl( configMAX_SYSCALL_INTERRUPT_PRIORITY );
     {
         if( xTaskIncrementTick() != pdFALSE )
@@ -312,7 +309,6 @@ void prvTickISR( void )
             taskYIELD();
         }
     }
-
     set_ipl( configKERNEL_INTERRUPT_PRIORITY );
 
     #if configUSE_TICKLESS_IDLE == 1
@@ -321,7 +317,7 @@ void prvTickISR( void )
         ulTickFlag = pdTRUE;
 
         /* If this is the first tick since exiting tickless mode then the CMT
-         * compare match value needs resetting. */
+        compare match value needs resetting. */
         CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;
     }
     #endif
@@ -338,87 +334,81 @@ void vSoftwareInterruptISR( void )
 static void prvYieldHandler( void )
 {
     /* Re-enable interrupts. */
-    SETPSW I
+    SETPSW  I
 
     /* Move the data that was automatically pushed onto the interrupt stack
-     * when the interrupt occurred from the interrupt stack to the user stack.
-     *
-     * R15 is saved before it is clobbered. */
-    PUSH.L R15
+    when the interrupt occurred from the interrupt stack to the user stack.
+
+    R15 is saved before it is clobbered. */
+    PUSH.L  R15
 
     /* Read the user stack pointer. */
-    MVFC USP, R15
+    MVFC    USP, R15
 
     /* Move the address down to the data being moved. */
-         SUB     # 12, R15
-    MVTC R15, USP
+    SUB     #12, R15
+    MVTC    R15, USP
 
     /* Copy the data across. */
-         MOV.L[ R0 ], [ R15 ];
-    R15
-
-    MOV.L   4[ R0 ], 4[ R15 ];
-    PC
-    MOV.L   8[ R0 ], 8[ R15 ];
-    PSW
+    MOV.L   [ R0 ], [ R15 ] ; R15
+    MOV.L   4[ R0 ], 4[ R15 ]  ; PC
+    MOV.L   8[ R0 ], 8[ R15 ]  ; PSW
 
     /* Move the interrupt stack pointer to its new correct position. */
-        ADD # 12, R0
+    ADD #12, R0
 
     /* All the rest of the registers are saved directly to the user stack. */
-    SETPSW U
+    SETPSW  U
 
     /* Save the rest of the general registers (R15 has been saved already). */
-    PUSHM R1 - R14
+    PUSHM   R1-R14
 
     /* Save the accumulator. */
     MVFACHI R15
-        PUSH.L R15
-    MVFACMI R15;
-    Middle order word.
-       SHLL    # 16, R15;
-    Shifted left as it is restored to the low order word.
-       PUSH.L R15
+    PUSH.L  R15
+    MVFACMI R15 ; Middle order word.
+    SHLL    #16, R15 ; Shifted left as it is restored to the low order word.
+    PUSH.L  R15
 
     /* Save the stack pointer to the TCB. */
-    MOV.L   # _pxCurrentTCB, R15
-        MOV.L[ R15 ], R15
-        MOV.L R0, [ R15 ]
+    MOV.L   #_pxCurrentTCB, R15
+    MOV.L   [ R15 ], R15
+    MOV.L   R0, [ R15 ]
 
     /* Ensure the interrupt mask is set to the syscall priority while the
-     * kernel structures are being accessed. */
-    MVTIPL  # configMAX_SYSCALL_INTERRUPT_PRIORITY
+    kernel structures are being accessed. */
+    MVTIPL  #configMAX_SYSCALL_INTERRUPT_PRIORITY
 
     /* Select the next task to run. */
-    BSR.A _vTaskSwitchContext
+    BSR.A   _vTaskSwitchContext
 
     /* Reset the interrupt mask as no more data structure access is
-     * required. */
-    MVTIPL  # configKERNEL_INTERRUPT_PRIORITY
+    required. */
+    MVTIPL  #configKERNEL_INTERRUPT_PRIORITY
 
     /* Load the stack pointer of the task that is now selected as the Running
-     * state task from its TCB. */
-    MOV.L   # _pxCurrentTCB, R15
-        MOV.L[ R15 ], R15
-        MOV.L[ R15 ], R0
+    state task from its TCB. */
+    MOV.L   #_pxCurrentTCB,R15
+    MOV.L   [ R15 ], R15
+    MOV.L   [ R15 ], R0
 
     /* Restore the context of the new task.  The PSW (Program Status Word) and
-     * PC will be popped by the RTE instruction. */
-    POP R15
+    PC will be popped by the RTE instruction. */
+    POP     R15
     MVTACLO R15
-    POP R15
+    POP     R15
     MVTACHI R15
-    POPM R1 - R15
+    POPM    R1-R15
     RTE
     NOP
-        NOP
+    NOP
 }
 /*-----------------------------------------------------------*/
 
 void vPortEndScheduler( void )
 {
     /* Not implemented in ports where there is nothing to return to.
-     * Artificially force an assert. */
+    Artificially force an assert. */
     configASSERT( pxCurrentTCB == NULL );
 
     /* The following line is just to prevent the symbol getting optimised away. */
@@ -460,11 +450,11 @@ static void prvSetupTimerInterrupt( void )
     {
         CMT0.CMCR.BIT.CKS = 0;
     }
-    #else /* if portCLOCK_DIVISOR == 512 */
+    #else
     {
         #error Invalid portCLOCK_DIVISOR setting
     }
-    #endif /* if portCLOCK_DIVISOR == 512 */
+    #endif
 
 
     /* Enable the interrupt... */
@@ -486,8 +476,8 @@ static void prvSetupTimerInterrupt( void )
         configPRE_SLEEP_PROCESSING( xExpectedIdleTime );
 
         /* xExpectedIdleTime being set to 0 by configPRE_SLEEP_PROCESSING()
-         * means the application defined code has already executed the WAIT
-         * instruction. */
+        means the application defined code has already executed the WAIT
+        instruction. */
         if( xExpectedIdleTime > 0 )
         {
             wait();
@@ -504,8 +494,8 @@ static void prvSetupTimerInterrupt( void )
 
     void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
     {
-        uint32_t ulMatchValue, ulCompleteTickPeriods, ulCurrentCount;
-        eSleepModeStatus eSleepAction;
+    uint32_t ulMatchValue, ulCompleteTickPeriods, ulCurrentCount;
+    eSleepModeStatus eSleepAction;
 
         /* THIS FUNCTION IS CALLED WITH THE SCHEDULER SUSPENDED. */
 
@@ -516,41 +506,38 @@ static void prvSetupTimerInterrupt( void )
         }
 
         /* Calculate the reload value required to wait xExpectedIdleTime tick
-         * periods. */
+        periods. */
         ulMatchValue = ulMatchValueForOneTick * xExpectedIdleTime;
-
         if( ulMatchValue > ulStoppedTimerCompensation )
         {
             /* Compensate for the fact that the CMT is going to be stopped
-             * momentarily. */
+            momentarily. */
             ulMatchValue -= ulStoppedTimerCompensation;
         }
 
         /* Stop the CMT momentarily.  The time the CMT is stopped for is
-         * accounted for as best it can be, but using the tickless mode will
-         * inevitably result in some tiny drift of the time maintained by the
-         * kernel with respect to calendar time. */
+        accounted for as best it can be, but using the tickless mode will
+        inevitably result in some tiny drift of the time maintained by the
+        kernel with respect to calendar time. */
         CMT.CMSTR0.BIT.STR0 = 0;
-
         while( CMT.CMSTR0.BIT.STR0 == 1 )
         {
             /* Nothing to do here. */
         }
 
         /* Critical section using the global interrupt bit as the i bit is
-         * automatically reset by the WAIT instruction. */
+        automatically reset by the WAIT instruction. */
         clrpsw_i();
 
         /* The tick flag is set to false before sleeping.  If it is true when
-         * sleep mode is exited then sleep mode was probably exited because the
-         * tick was suppressed for the entire xExpectedIdleTime period. */
+        sleep mode is exited then sleep mode was probably exited because the
+        tick was suppressed for the entire xExpectedIdleTime period. */
         ulTickFlag = pdFALSE;
 
         /* If a context switch is pending then abandon the low power entry as
-         * the context switch might have been pended by an external interrupt that
-         * requires processing. */
+        the context switch might have been pended by an external interrupt that
+        requires processing. */
         eSleepAction = eTaskConfirmSleepModeStatus();
-
         if( eSleepAction == eAbortSleep )
         {
             /* Restart tick. */
@@ -569,7 +556,7 @@ static void prvSetupTimerInterrupt( void )
             SYSTEM.PRCR.WORD = portLOCK_KEY;
 
             /* Sleep until something happens.  Calling prvSleep() will
-             * automatically reset the i bit in the PSW. */
+            automatically reset the i bit in the PSW. */
             prvSleep( xExpectedIdleTime );
 
             /* Restart the CMT. */
@@ -589,7 +576,7 @@ static void prvSetupTimerInterrupt( void )
             SYSTEM.PRCR.WORD = portLOCK_KEY;
 
             /* Adjust the match value to take into account that the current
-             * time slice is already partially complete. */
+            time slice is already partially complete. */
             ulMatchValue -= ( uint32_t ) CMT0.CMCNT;
             CMT0.CMCOR = ( uint16_t ) ulMatchValue;
 
@@ -598,15 +585,14 @@ static void prvSetupTimerInterrupt( void )
             CMT.CMSTR0.BIT.STR0 = 1;
 
             /* Sleep until something happens.  Calling prvSleep() will
-             * automatically reset the i bit in the PSW. */
+            automatically reset the i bit in the PSW. */
             prvSleep( xExpectedIdleTime );
 
             /* Stop CMT.  Again, the time the SysTick is stopped for is
-             * accounted for as best it can be, but using the tickless mode will
-             * inevitably result in some tiny drift of the time maintained by the
-             * kernel with respect to calendar time. */
+            accounted for as best it can be, but using the tickless mode will
+            inevitably result in some tiny drift of the time maintained by the
+            kernel with respect to calendar time. */
             CMT.CMSTR0.BIT.STR0 = 0;
-
             while( CMT.CMSTR0.BIT.STR0 == 1 )
             {
                 /* Nothing to do here. */
@@ -617,42 +603,42 @@ static void prvSetupTimerInterrupt( void )
             if( ulTickFlag != pdFALSE )
             {
                 /* The tick interrupt has already executed, although because
-                 * this function is called with the scheduler suspended the actual
-                 * tick processing will not occur until after this function has
-                 * exited.  Reset the match value with whatever remains of this
-                 * tick period. */
+                this function is called with the scheduler suspended the actual
+                tick processing will not occur until after this function has
+                exited.  Reset the match value with whatever remains of this
+                tick period. */
                 ulMatchValue = ulMatchValueForOneTick - ulCurrentCount;
                 CMT0.CMCOR = ( uint16_t ) ulMatchValue;
 
                 /* The tick interrupt handler will already have pended the tick
-                 * processing in the kernel.  As the pending tick will be
-                 * processed as soon as this function exits, the tick value
-                 * maintained by the tick is stepped forward by one less than the
-                 * time spent sleeping.  The actual stepping of the tick appears
-                 * later in this function. */
+                processing in the kernel.  As the pending tick will be
+                processed as soon as this function exits, the tick value
+                maintained by the tick is stepped forward by one less than the
+                time spent sleeping.  The actual stepping of the tick appears
+                later in this function. */
                 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
             }
             else
             {
                 /* Something other than the tick interrupt ended the sleep.
-                 * How many complete tick periods passed while the processor was
-                 * sleeping? */
+                How many complete tick periods passed while the processor was
+                sleeping? */
                 ulCompleteTickPeriods = ulCurrentCount / ulMatchValueForOneTick;
 
                 /* The match value is set to whatever fraction of a single tick
-                 * period remains. */
+                period remains. */
                 ulMatchValue = ulCurrentCount - ( ulCompleteTickPeriods * ulMatchValueForOneTick );
                 CMT0.CMCOR = ( uint16_t ) ulMatchValue;
             }
 
             /* Restart the CMT so it runs up to the match value.  The match value
-             * will get set to the value required to generate exactly one tick period
-             * the next time the CMT interrupt executes. */
+            will get set to the value required to generate exactly one tick period
+            the next time the CMT interrupt executes. */
             CMT0.CMCNT = 0;
             CMT.CMSTR0.BIT.STR0 = 1;
 
             /* Wind the tick forward by the number of tick periods that the CPU
-             * remained in a low power state. */
+            remained in a low power state. */
             vTaskStepTick( ulCompleteTickPeriods );
         }
     }
diff --git a/portable/Renesas/RX100/portmacro.h b/portable/Renesas/RX100/portmacro.h
index d6a758bb7..b82fdca24 100644
--- a/portable/Renesas/RX100/portmacro.h
+++ b/portable/Renesas/RX100/portmacro.h
@@ -50,87 +50,87 @@
  */
 
 /* Type definitions - these are a bit legacy and not really used now, other
- * than portSTACK_TYPE and portBASE_TYPE. */
-#define portCHAR          char
-#define portFLOAT         float
-#define portDOUBLE        double
-#define portLONG          long
-#define portSHORT         short
-#define portSTACK_TYPE    uint32_t
-#define portBASE_TYPE     long
+than portSTACK_TYPE and portBASE_TYPE. */
+#define portCHAR        char
+#define portFLOAT       float
+#define portDOUBLE      double
+#define portLONG        long
+#define portSHORT       short
+#define portSTACK_TYPE  uint32_t
+#define portBASE_TYPE   long
 
-typedef portSTACK_TYPE   StackType_t;
-typedef long             BaseType_t;
-typedef unsigned long    UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
 
-#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t     TickType_t;
-    #define portMAX_DELAY              ( TickType_t ) 0xffff
+#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t TickType_t;
+    #define portMAX_DELAY ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t     TickType_t;
-    #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+    typedef uint32_t TickType_t;
+    #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
 
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
-    #define portTICK_TYPE_IS_ATOMIC    1
+    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+    not need to be guarded with a critical section. */
+    #define portTICK_TYPE_IS_ATOMIC 1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portBYTE_ALIGNMENT    8             /* Could make four, according to manual. */
-#define portSTACK_GROWTH      -1
-#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portNOP()    nop()
+#define portBYTE_ALIGNMENT              8   /* Could make four, according to manual. */
+#define portSTACK_GROWTH                -1
+#define portTICK_PERIOD_MS              ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()                       nop()
 
 #pragma inline_asm vPortYield
 static void vPortYield( void )
 {
     /* Save clobbered register - may not actually be necessary if inline asm
-     * functions are considered to use the same rules as function calls by the
-     * compiler. */
+    functions are considered to use the same rules as function calls by the
+    compiler. */
     PUSH.L R5
     /* Set ITU SWINTR. */
-    MOV.L # 872E0H, R5
-        MOV.B # 1, [ R5 ]
+    MOV.L #872E0H, R5
+    MOV.B #1, [R5]
     /* Read back to ensure the value is taken before proceeding. */
-    MOV.L[ R5 ], R5
+    MOV.L [R5], R5
     /* Restore clobbered register to its previous value. */
     POP R5
 }
-#define portYIELD()                                       vPortYield()
-#define portYIELD_FROM_ISR( x )                           do { if( x != pdFALSE ) { portYIELD(); } } while( 0 )
+#define portYIELD() vPortYield()
+#define portYIELD_FROM_ISR( x ) do { if( x != pdFALSE ) { portYIELD(); } } while( 0 )
 
 /* These macros should not be called directly, but through the
- * taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
- * performed if configASSERT() is defined to ensure an assertion handler does not
- * inadvertently attempt to lower the IPL when the call to assert was triggered
- * because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
- * when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
- * functions are those that end in FromISR.  FreeRTOS maintains a separate
- * interrupt API to ensure API function and interrupt entry is as fast and as
- * simple as possible. */
-#define portENABLE_INTERRUPTS()                           set_ipl( ( long ) 0 )
+taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
+performed if configASSERT() is defined to ensure an assertion handler does not
+inadvertently attempt to lower the IPL when the call to assert was triggered
+because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
+when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
+functions are those that end in FromISR.  FreeRTOS maintains a separate
+interrupt API to ensure API function and interrupt entry is as fast and as
+simple as possible. */
+#define portENABLE_INTERRUPTS()     set_ipl( ( long ) 0 )
 #ifdef configASSERT
-    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    configASSERT( ( get_ipl() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
-    #define portDISABLE_INTERRUPTS()                      if( get_ipl() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( get_ipl() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+    #define portDISABLE_INTERRUPTS()    if( get_ipl() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
 #else
-    #define portDISABLE_INTERRUPTS()                      set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+    #define portDISABLE_INTERRUPTS()    set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
 #endif
 
 /* Critical nesting counts are stored in the TCB. */
-#define portCRITICAL_NESTING_IN_TCB    ( 1 )
+#define portCRITICAL_NESTING_IN_TCB ( 1 )
 
 /* The critical nesting functions defined within tasks.c. */
 extern void vTaskEnterCritical( void );
 extern void vTaskExitCritical( void );
-#define portENTER_CRITICAL()                                           vTaskEnterCritical()
-#define portEXIT_CRITICAL()                                            vTaskExitCritical()
+#define portENTER_CRITICAL()    vTaskEnterCritical()
+#define portEXIT_CRITICAL()     vTaskExitCritical()
 
 /* As this port allows interrupt nesting... */
-#define portSET_INTERRUPT_MASK_FROM_ISR()                              ( UBaseType_t ) get_ipl(); set_ipl( ( signed long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus )    set_ipl( ( signed long ) uxSavedInterruptStatus )
+#define portSET_INTERRUPT_MASK_FROM_ISR() ( UBaseType_t ) get_ipl(); set_ipl( ( signed long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) set_ipl( ( signed long ) uxSavedInterruptStatus )
 
 /*-----------------------------------------------------------*/
 
@@ -138,15 +138,15 @@ extern void vTaskExitCritical( void );
 #if configUSE_TICKLESS_IDLE == 1
     #ifndef portSUPPRESS_TICKS_AND_SLEEP
         extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
-        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
+        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
     #endif
 #endif
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/Renesas/RX200/port.c b/portable/Renesas/RX200/port.c
index 13d035434..d60ac8fff 100644
--- a/portable/Renesas/RX200/port.c
+++ b/portable/Renesas/RX200/port.c
@@ -27,8 +27,8 @@
  */
 
 /*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the RX200 port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the RX200 port.
+ *----------------------------------------------------------*/
 
 /* Scheduler includes. */
 #include "FreeRTOS.h"
@@ -43,14 +43,14 @@
 /*-----------------------------------------------------------*/
 
 /* Tasks should start with interrupts enabled and in Supervisor mode, therefore
- * PSW is set with U and I set, and PM and IPL clear. */
-#define portINITIAL_PSW    ( ( StackType_t ) 0x00030000 )
+PSW is set with U and I set, and PM and IPL clear. */
+#define portINITIAL_PSW     ( ( StackType_t ) 0x00030000 )
 
 /*-----------------------------------------------------------*/
 
 /* The following lines are to ensure vSoftwareInterruptEntry can be referenced,
- * and therefore installed in the vector table, when the FreeRTOS code is built
- * as a library. */
+ and therefore installed in the vector table, when the FreeRTOS code is built
+as a library. */
 extern BaseType_t vSoftwareInterruptEntry;
 const BaseType_t * p_vSoftwareInterruptEntry = &vSoftwareInterruptEntry;
 
@@ -80,8 +80,8 @@ void vSoftwareInterruptISR( void );
 /*-----------------------------------------------------------*/
 
 /* This is accessed by the inline assembler functions so is file scope for
- * convenience. */
-extern void * pxCurrentTCB;
+convenience. */
+extern void *pxCurrentTCB;
 extern void vTaskSwitchContext( void );
 
 /*-----------------------------------------------------------*/
@@ -89,9 +89,7 @@ extern void vTaskSwitchContext( void );
 /*
  * See header file for description.
  */
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
 {
     /* Offset to end up on 8 byte boundary. */
     pxTopOfStack--;
@@ -106,8 +104,8 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
     *pxTopOfStack = ( StackType_t ) pxCode;
 
     /* When debugging it can be useful if every register is set to a known
-     * value.  Otherwise code space can be saved by just setting the registers
-     * that need to be set. */
+    value.  Otherwise code space can be saved by just setting the registers
+    that need to be set. */
     #ifdef USE_FULL_REGISTER_INITIALISATION
     {
         pxTopOfStack--;
@@ -140,17 +138,17 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
         *pxTopOfStack = 0x22222222;
         pxTopOfStack--;
     }
-    #else /* ifdef USE_FULL_REGISTER_INITIALISATION */
+    #else
     {
         pxTopOfStack -= 15;
     }
-    #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */
+    #endif
 
     *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
     pxTopOfStack--;
-    *pxTopOfStack = 0x12345678;                   /* Accumulator. */
+    *pxTopOfStack = 0x12345678; /* Accumulator. */
     pxTopOfStack--;
-    *pxTopOfStack = 0x87654321;                   /* Accumulator. */
+    *pxTopOfStack = 0x87654321; /* Accumulator. */
 
     return pxTopOfStack;
 }
@@ -158,14 +156,14 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
 
 BaseType_t xPortStartScheduler( void )
 {
-    extern void vApplicationSetupTimerInterrupt( void );
+extern void vApplicationSetupTimerInterrupt( void );
 
     /* Use pxCurrentTCB just so it does not get optimised away. */
     if( pxCurrentTCB != NULL )
     {
         /* Call an application function to set up the timer that will generate the
-         * tick interrupt.  This way the application can decide which peripheral to
-         * use.  A demo application is provided to show a suitable example. */
+        tick interrupt.  This way the application can decide which peripheral to
+        use.  A demo application is provided to show a suitable example. */
         vApplicationSetupTimerInterrupt();
 
         /* Enable the software interrupt. */
@@ -193,26 +191,26 @@ BaseType_t xPortStartScheduler( void )
 static void prvStartFirstTask( void )
 {
     /* When starting the scheduler there is nothing that needs moving to the
-     * interrupt stack because the function is not called from an interrupt.
-     * Just ensure the current stack is the user stack. */
-    SETPSW U
+    interrupt stack because the function is not called from an interrupt.
+    Just ensure the current stack is the user stack. */
+    SETPSW  U
 
     /* Obtain the location of the stack associated with which ever task
-     * pxCurrentTCB is currently pointing to. */
-    MOV.L   # _pxCurrentTCB, R15
-        MOV.L[ R15 ], R15
-        MOV.L[ R15 ], R0
+    pxCurrentTCB is currently pointing to. */
+    MOV.L   #_pxCurrentTCB, R15
+    MOV.L   [R15], R15
+    MOV.L   [R15], R0
 
     /* Restore the registers from the stack of the task pointed to by
-     * pxCurrentTCB. */
-    POP R15
-    MVTACLO R15   /* Accumulator low 32 bits. */
-    POP R15
-    MVTACHI R15   /* Accumulator high 32 bits. */
-    POPM R1 - R15 /* R1 to R15 - R0 is not included as it is the SP. */
-    RTE           /* This pops the remaining registers. */
+    pxCurrentTCB. */
+    POP     R15
+    MVTACLO R15         /* Accumulator low 32 bits. */
+    POP     R15
+    MVTACHI R15         /* Accumulator high 32 bits. */
+    POPM    R1-R15      /* R1 to R15 - R0 is not included as it is the SP. */
+    RTE                 /* This pops the remaining registers. */
+    NOP
     NOP
-        NOP
 }
 /*-----------------------------------------------------------*/
 
@@ -220,7 +218,7 @@ static void prvStartFirstTask( void )
 void vTickISR( void )
 {
     /* Increment the tick, and perform any processing the new tick value
-     * necessitates. */
+    necessitates. */
     set_ipl( configMAX_SYSCALL_INTERRUPT_PRIORITY );
     {
         if( xTaskIncrementTick() != pdFALSE )
@@ -228,7 +226,6 @@ void vTickISR( void )
             taskYIELD();
         }
     }
-
     set_ipl( configKERNEL_INTERRUPT_PRIORITY );
 }
 /*-----------------------------------------------------------*/
@@ -243,86 +240,80 @@ void vSoftwareInterruptISR( void )
 static void prvYieldHandler( void )
 {
     /* Re-enable interrupts. */
-    SETPSW I
+    SETPSW  I
 
     /* Move the data that was automatically pushed onto the interrupt stack when
-     * the interrupt occurred from the interrupt stack to the user stack.
-     *
-     * R15 is saved before it is clobbered. */
-    PUSH.L R15
+    the interrupt occurred from the interrupt stack to the user stack.
+
+    R15 is saved before it is clobbered. */
+    PUSH.L  R15
 
     /* Read the user stack pointer. */
-    MVFC USP, R15
+    MVFC    USP, R15
 
     /* Move the address down to the data being moved. */
-         SUB     # 12, R15
-    MVTC R15, USP
+    SUB     #12, R15
+    MVTC    R15, USP
 
     /* Copy the data across. */
-         MOV.L[ R0 ], [ R15 ];
-    R15
-
-    MOV.L   4[ R0 ], 4[ R15 ];
-    PC
-    MOV.L   8[ R0 ], 8[ R15 ];
-    PSW
+    MOV.L   [ R0 ], [ R15 ] ; R15
+    MOV.L   4[ R0 ], 4[ R15 ]  ; PC
+    MOV.L   8[ R0 ], 8[ R15 ]  ; PSW
 
     /* Move the interrupt stack pointer to its new correct position. */
-        ADD # 12, R0
+    ADD #12, R0
 
     /* All the rest of the registers are saved directly to the user stack. */
-    SETPSW U
+    SETPSW  U
 
     /* Save the rest of the general registers (R15 has been saved already). */
-    PUSHM R1 - R14
+    PUSHM   R1-R14
 
     /* Save the accumulator. */
     MVFACHI R15
-        PUSH.L R15
-    MVFACMI R15;
-    Middle order word.
-       SHLL    # 16, R15;
-    Shifted left as it is restored to the low order word.
-       PUSH.L R15
+    PUSH.L  R15
+    MVFACMI R15 ; Middle order word.
+    SHLL    #16, R15 ; Shifted left as it is restored to the low order word.
+    PUSH.L  R15
 
     /* Save the stack pointer to the TCB. */
-    MOV.L   # _pxCurrentTCB, R15
-        MOV.L[ R15 ], R15
-        MOV.L R0, [ R15 ]
+    MOV.L   #_pxCurrentTCB, R15
+    MOV.L   [ R15 ], R15
+    MOV.L   R0, [ R15 ]
 
     /* Ensure the interrupt mask is set to the syscall priority while the kernel
-     * structures are being accessed. */
-    MVTIPL  # configMAX_SYSCALL_INTERRUPT_PRIORITY
+    structures are being accessed. */
+    MVTIPL  #configMAX_SYSCALL_INTERRUPT_PRIORITY
 
     /* Select the next task to run. */
-    BSR.A _vTaskSwitchContext
+    BSR.A   _vTaskSwitchContext
 
     /* Reset the interrupt mask as no more data structure access is required. */
-    MVTIPL  # configKERNEL_INTERRUPT_PRIORITY
+    MVTIPL  #configKERNEL_INTERRUPT_PRIORITY
 
     /* Load the stack pointer of the task that is now selected as the Running
-     * state task from its TCB. */
-    MOV.L   # _pxCurrentTCB, R15
-        MOV.L[ R15 ], R15
-        MOV.L[ R15 ], R0
+    state task from its TCB. */
+    MOV.L   #_pxCurrentTCB,R15
+    MOV.L   [ R15 ], R15
+    MOV.L   [ R15 ], R0
 
     /* Restore the context of the new task.  The PSW (Program Status Word) and
-     * PC will be popped by the RTE instruction. */
-    POP R15
+    PC will be popped by the RTE instruction. */
+    POP     R15
     MVTACLO R15
-    POP R15
+    POP     R15
     MVTACHI R15
-    POPM R1 - R15
+    POPM    R1-R15
     RTE
     NOP
-        NOP
+    NOP
 }
 /*-----------------------------------------------------------*/
 
 void vPortEndScheduler( void )
 {
     /* Not implemented in ports where there is nothing to return to.
-     * Artificially force an assert. */
+    Artificially force an assert. */
     configASSERT( pxCurrentTCB == NULL );
 
     /* The following line is just to prevent the symbol getting optimised away. */
diff --git a/portable/Renesas/RX200/portmacro.h b/portable/Renesas/RX200/portmacro.h
index c768be9ec..55278dacb 100644
--- a/portable/Renesas/RX200/portmacro.h
+++ b/portable/Renesas/RX200/portmacro.h
@@ -50,93 +50,93 @@
  */
 
 /* Type definitions - these are a bit legacy and not really used now, other than
- * portSTACK_TYPE and portBASE_TYPE. */
-#define portCHAR          char
-#define portFLOAT         float
-#define portDOUBLE        double
-#define portLONG          long
-#define portSHORT         short
-#define portSTACK_TYPE    uint32_t
-#define portBASE_TYPE     long
+portSTACK_TYPE and portBASE_TYPE. */
+#define portCHAR        char
+#define portFLOAT       float
+#define portDOUBLE      double
+#define portLONG        long
+#define portSHORT       short
+#define portSTACK_TYPE  uint32_t
+#define portBASE_TYPE   long
 
-typedef portSTACK_TYPE   StackType_t;
-typedef long             BaseType_t;
-typedef unsigned long    UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
 
-#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t     TickType_t;
-    #define portMAX_DELAY              ( TickType_t ) 0xffff
+#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t TickType_t;
+    #define portMAX_DELAY ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t     TickType_t;
-    #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+    typedef uint32_t TickType_t;
+    #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
 
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
-    #define portTICK_TYPE_IS_ATOMIC    1
+    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+    not need to be guarded with a critical section. */
+    #define portTICK_TYPE_IS_ATOMIC 1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portBYTE_ALIGNMENT    8             /* Could make four, according to manual. */
-#define portSTACK_GROWTH      -1
-#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portNOP()    nop()
+#define portBYTE_ALIGNMENT              8   /* Could make four, according to manual. */
+#define portSTACK_GROWTH                -1
+#define portTICK_PERIOD_MS              ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()                       nop()
 
 #pragma inline_asm vPortYield
 static void vPortYield( void )
 {
     /* Save clobbered register - may not actually be necessary if inline asm
-     * functions are considered to use the same rules as function calls by the
-     * compiler. */
+    functions are considered to use the same rules as function calls by the
+    compiler. */
     PUSH.L R5
     /* Set ITU SWINTR. */
-    MOV.L # 553696, R5
-        MOV.B # 1, [ R5 ]
+    MOV.L #553696, R5
+    MOV.B #1, [R5]
     /* Read back to ensure the value is taken before proceeding. */
-    MOV.L[ R5 ], R5
+    MOV.L [R5], R5
     /* Restore clobbered register to its previous value. */
     POP R5
 }
-#define portYIELD()                                       vPortYield()
-#define portYIELD_FROM_ISR( x )                           do { if( x != pdFALSE ) portYIELD( ); } while( 0 )
+#define portYIELD() vPortYield()
+#define portYIELD_FROM_ISR( x ) do { if( x != pdFALSE ) portYIELD(); } while( 0 )
 
 /* These macros should not be called directly, but through the
- * taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
- * performed if configASSERT() is defined to ensure an assertion handler does not
- * inadvertently attempt to lower the IPL when the call to assert was triggered
- * because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
- * when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
- * functions are those that end in FromISR.  FreeRTOS maintains a separate
- * interrupt API to ensure API function and interrupt entry is as fast and as
- * simple as possible. */
-#define portENABLE_INTERRUPTS()                           set_ipl( ( long ) 0 )
+taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
+performed if configASSERT() is defined to ensure an assertion handler does not
+inadvertently attempt to lower the IPL when the call to assert was triggered
+because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
+when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
+functions are those that end in FromISR.  FreeRTOS maintains a separate
+interrupt API to ensure API function and interrupt entry is as fast and as
+simple as possible. */
+#define portENABLE_INTERRUPTS()     set_ipl( ( long ) 0 )
 #ifdef configASSERT
-    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    configASSERT( ( get_ipl() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
-    #define portDISABLE_INTERRUPTS()                      if( get_ipl() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( get_ipl() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+    #define portDISABLE_INTERRUPTS()    if( get_ipl() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
 #else
-    #define portDISABLE_INTERRUPTS()                      set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+    #define portDISABLE_INTERRUPTS()    set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
 #endif
 
 /* Critical nesting counts are stored in the TCB. */
-#define portCRITICAL_NESTING_IN_TCB    ( 1 )
+#define portCRITICAL_NESTING_IN_TCB ( 1 )
 
 /* The critical nesting functions defined within tasks.c. */
 extern void vTaskEnterCritical( void );
 extern void vTaskExitCritical( void );
-#define portENTER_CRITICAL()                                           vTaskEnterCritical()
-#define portEXIT_CRITICAL()                                            vTaskExitCritical()
+#define portENTER_CRITICAL()    vTaskEnterCritical()
+#define portEXIT_CRITICAL()     vTaskExitCritical()
 
 /* As this port allows interrupt nesting... */
-#define portSET_INTERRUPT_MASK_FROM_ISR()                              get_ipl(); set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus )    set_ipl( ( long ) uxSavedInterruptStatus )
+#define portSET_INTERRUPT_MASK_FROM_ISR() get_ipl(); set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) set_ipl( ( long ) uxSavedInterruptStatus )
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/Renesas/RX600/port.c b/portable/Renesas/RX600/port.c
index 5fca0d72d..5438f5764 100644
--- a/portable/Renesas/RX600/port.c
+++ b/portable/Renesas/RX600/port.c
@@ -27,8 +27,8 @@
  */
 
 /*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the RX600 port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the RX600 port.
+ *----------------------------------------------------------*/
 
 /* Scheduler includes. */
 #include "FreeRTOS.h"
@@ -43,15 +43,15 @@
 /*-----------------------------------------------------------*/
 
 /* Tasks should start with interrupts enabled and in Supervisor mode, therefore
- * PSW is set with U and I set, and PM and IPL clear. */
+PSW is set with U and I set, and PM and IPL clear. */
 #define portINITIAL_PSW     ( ( StackType_t ) 0x00030000 )
 #define portINITIAL_FPSW    ( ( StackType_t ) 0x00000100 )
 
 /*-----------------------------------------------------------*/
 
 /* The following lines are to ensure vSoftwareInterruptEntry can be referenced,
- * and therefore installed in the vector table, when the FreeRTOS code is built
- * as a library. */
+ and therefore installed in the vector table, when the FreeRTOS code is built
+as a library. */
 extern BaseType_t vSoftwareInterruptEntry;
 const BaseType_t * p_vSoftwareInterruptEntry = &vSoftwareInterruptEntry;
 
@@ -81,8 +81,8 @@ void vSoftwareInterruptISR( void );
 /*-----------------------------------------------------------*/
 
 /* This is accessed by the inline assembler functions so is file scope for
- * convenience. */
-extern void * pxCurrentTCB;
+convenience. */
+extern void *pxCurrentTCB;
 extern void vTaskSwitchContext( void );
 
 /*-----------------------------------------------------------*/
@@ -90,9 +90,7 @@ extern void vTaskSwitchContext( void );
 /*
  * See header file for description.
  */
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
 {
     /* R0 is not included as it is the stack pointer. */
 
@@ -103,8 +101,8 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
     *pxTopOfStack = ( StackType_t ) pxCode;
 
     /* When debugging it can be useful if every register is set to a known
-     * value.  Otherwise code space can be saved by just setting the registers
-     * that need to be set. */
+    value.  Otherwise code space can be saved by just setting the registers
+    that need to be set. */
     #ifdef USE_FULL_REGISTER_INITIALISATION
     {
         pxTopOfStack--;
@@ -137,11 +135,11 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
         *pxTopOfStack = 0x22222222;
         pxTopOfStack--;
     }
-    #else /* ifdef USE_FULL_REGISTER_INITIALISATION */
+    #else
     {
         pxTopOfStack -= 15;
     }
-    #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */
+    #endif
 
     *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
     pxTopOfStack--;
@@ -157,14 +155,14 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
 
 BaseType_t xPortStartScheduler( void )
 {
-    extern void vApplicationSetupTimerInterrupt( void );
+extern void vApplicationSetupTimerInterrupt( void );
 
     /* Use pxCurrentTCB just so it does not get optimised away. */
     if( pxCurrentTCB != NULL )
     {
         /* Call an application function to set up the timer that will generate the
-         * tick interrupt.  This way the application can decide which peripheral to
-         * use.  A demo application is provided to show a suitable example. */
+        tick interrupt.  This way the application can decide which peripheral to
+        use.  A demo application is provided to show a suitable example. */
         vApplicationSetupTimerInterrupt();
 
         /* Enable the software interrupt. */
@@ -192,28 +190,28 @@ BaseType_t xPortStartScheduler( void )
 static void prvStartFirstTask( void )
 {
     /* When starting the scheduler there is nothing that needs moving to the
-     * interrupt stack because the function is not called from an interrupt.
-     * Just ensure the current stack is the user stack. */
-    SETPSW U
+    interrupt stack because the function is not called from an interrupt.
+    Just ensure the current stack is the user stack. */
+    SETPSW  U
 
     /* Obtain the location of the stack associated with which ever task
-     * pxCurrentTCB is currently pointing to. */
-    MOV.L   # _pxCurrentTCB, R15
-        MOV.L[ R15 ], R15
-        MOV.L[ R15 ], R0
+    pxCurrentTCB is currently pointing to. */
+    MOV.L   #_pxCurrentTCB, R15
+    MOV.L   [R15], R15
+    MOV.L   [R15], R0
 
     /* Restore the registers from the stack of the task pointed to by
-     * pxCurrentTCB. */
-    POP R15
-    MVTACLO R15    /* Accumulator low 32 bits. */
-    POP R15
-    MVTACHI R15    /* Accumulator high 32 bits. */
-    POP R15
-    MVTC R15, FPSW /* Floating point status word. */
-    POPM R1 - R15  /* R1 to R15 - R0 is not included as it is the SP. */
-    RTE            /* This pops the remaining registers. */
+    pxCurrentTCB. */
+    POP     R15
+    MVTACLO R15         /* Accumulator low 32 bits. */
+    POP     R15
+    MVTACHI R15         /* Accumulator high 32 bits. */
+    POP     R15
+    MVTC    R15,FPSW    /* Floating point status word. */
+    POPM    R1-R15      /* R1 to R15 - R0 is not included as it is the SP. */
+    RTE                 /* This pops the remaining registers. */
+    NOP
     NOP
-        NOP
 }
 /*-----------------------------------------------------------*/
 
@@ -221,7 +219,7 @@ static void prvStartFirstTask( void )
 void vTickISR( void )
 {
     /* Increment the tick, and perform any processing the new tick value
-     * necessitates. */
+    necessitates. */
     set_ipl( configMAX_SYSCALL_INTERRUPT_PRIORITY );
     {
         if( xTaskIncrementTick() != pdFALSE )
@@ -229,7 +227,6 @@ void vTickISR( void )
             taskYIELD();
         }
     }
-
     set_ipl( configKERNEL_INTERRUPT_PRIORITY );
 }
 /*-----------------------------------------------------------*/
@@ -244,90 +241,84 @@ void vSoftwareInterruptISR( void )
 static void prvYieldHandler( void )
 {
     /* Re-enable interrupts. */
-    SETPSW I
+    SETPSW  I
 
     /* Move the data that was automatically pushed onto the interrupt stack when
-     * the interrupt occurred from the interrupt stack to the user stack.
-     *
-     * R15 is saved before it is clobbered. */
-    PUSH.L R15
+    the interrupt occurred from the interrupt stack to the user stack.
+
+    R15 is saved before it is clobbered. */
+    PUSH.L  R15
 
     /* Read the user stack pointer. */
-    MVFC USP, R15
+    MVFC    USP, R15
 
     /* Move the address down to the data being moved. */
-         SUB     # 12, R15
-    MVTC R15, USP
+    SUB     #12, R15
+    MVTC    R15, USP
 
     /* Copy the data across. */
-         MOV.L[ R0 ], [ R15 ];
-    R15
-
-    MOV.L   4[ R0 ], 4[ R15 ];
-    PC
-    MOV.L   8[ R0 ], 8[ R15 ];
-    PSW
+    MOV.L   [ R0 ], [ R15 ] ; R15
+    MOV.L   4[ R0 ], 4[ R15 ]  ; PC
+    MOV.L   8[ R0 ], 8[ R15 ]  ; PSW
 
     /* Move the interrupt stack pointer to its new correct position. */
-        ADD # 12, R0
+    ADD #12, R0
 
     /* All the rest of the registers are saved directly to the user stack. */
-    SETPSW U
+    SETPSW  U
 
     /* Save the rest of the general registers (R15 has been saved already). */
-    PUSHM R1 - R14
+    PUSHM   R1-R14
 
     /* Save the FPSW and accumulator. */
-    MVFC FPSW, R15
-        PUSH.L R15
+    MVFC    FPSW, R15
+    PUSH.L  R15
     MVFACHI R15
-        PUSH.L R15
-    MVFACMI R15;
-    Middle order word.
-       SHLL    # 16, R15;
-    Shifted left as it is restored to the low order word.
-       PUSH.L R15
+    PUSH.L  R15
+    MVFACMI R15 ; Middle order word.
+    SHLL    #16, R15 ; Shifted left as it is restored to the low order word.
+    PUSH.L  R15
 
     /* Save the stack pointer to the TCB. */
-    MOV.L   # _pxCurrentTCB, R15
-        MOV.L[ R15 ], R15
-        MOV.L R0, [ R15 ]
+    MOV.L   #_pxCurrentTCB, R15
+    MOV.L   [ R15 ], R15
+    MOV.L   R0, [ R15 ]
 
     /* Ensure the interrupt mask is set to the syscall priority while the kernel
-     * structures are being accessed. */
-    MVTIPL  # configMAX_SYSCALL_INTERRUPT_PRIORITY
+    structures are being accessed. */
+    MVTIPL  #configMAX_SYSCALL_INTERRUPT_PRIORITY
 
     /* Select the next task to run. */
-    BSR.A _vTaskSwitchContext
+    BSR.A   _vTaskSwitchContext
 
     /* Reset the interrupt mask as no more data structure access is required. */
-    MVTIPL  # configKERNEL_INTERRUPT_PRIORITY
+    MVTIPL  #configKERNEL_INTERRUPT_PRIORITY
 
     /* Load the stack pointer of the task that is now selected as the Running
-     * state task from its TCB. */
-    MOV.L   # _pxCurrentTCB, R15
-        MOV.L[ R15 ], R15
-        MOV.L[ R15 ], R0
+    state task from its TCB. */
+    MOV.L   #_pxCurrentTCB,R15
+    MOV.L   [ R15 ], R15
+    MOV.L   [ R15 ], R0
 
     /* Restore the context of the new task.  The PSW (Program Status Word) and
-     * PC will be popped by the RTE instruction. */
-    POP R15
+    PC will be popped by the RTE instruction. */
+    POP     R15
     MVTACLO R15
-    POP R15
+    POP     R15
     MVTACHI R15
-    POP R15
-    MVTC R15, FPSW
-    POPM R1 - R15
+    POP     R15
+    MVTC    R15,FPSW
+    POPM    R1-R15
     RTE
     NOP
-        NOP
+    NOP
 }
 /*-----------------------------------------------------------*/
 
 void vPortEndScheduler( void )
 {
     /* Not implemented in ports where there is nothing to return to.
-     * Artificially force an assert. */
+    Artificially force an assert. */
     configASSERT( pxCurrentTCB == NULL );
 
     /* The following line is just to prevent the symbol getting optimised away. */
diff --git a/portable/Renesas/RX600/portmacro.h b/portable/Renesas/RX600/portmacro.h
index 9e5ed59db..60106ae13 100644
--- a/portable/Renesas/RX600/portmacro.h
+++ b/portable/Renesas/RX600/portmacro.h
@@ -50,94 +50,94 @@
  */
 
 /* Type definitions - these are a bit legacy and not really used now, other than
- * portSTACK_TYPE and portBASE_TYPE. */
-#define portCHAR          char
-#define portFLOAT         float
-#define portDOUBLE        double
-#define portLONG          long
-#define portSHORT         short
-#define portSTACK_TYPE    uint32_t
-#define portBASE_TYPE     long
+portSTACK_TYPE and portBASE_TYPE. */
+#define portCHAR        char
+#define portFLOAT       float
+#define portDOUBLE      double
+#define portLONG        long
+#define portSHORT       short
+#define portSTACK_TYPE  uint32_t
+#define portBASE_TYPE   long
 
-typedef portSTACK_TYPE   StackType_t;
-typedef long             BaseType_t;
-typedef unsigned long    UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
 
-#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t     TickType_t;
-    #define portMAX_DELAY              ( TickType_t ) 0xffff
+#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t TickType_t;
+    #define portMAX_DELAY ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t     TickType_t;
-    #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+    typedef uint32_t TickType_t;
+    #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
 
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
-    #define portTICK_TYPE_IS_ATOMIC    1
+    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+    not need to be guarded with a critical section. */
+    #define portTICK_TYPE_IS_ATOMIC 1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portBYTE_ALIGNMENT    8             /* Could make four, according to manual. */
-#define portSTACK_GROWTH      -1
-#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portNOP()    nop()
+#define portBYTE_ALIGNMENT              8   /* Could make four, according to manual. */
+#define portSTACK_GROWTH                -1
+#define portTICK_PERIOD_MS              ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()                       nop()
 
 
 #pragma inline_asm vPortYield
 static void vPortYield( void )
 {
     /* Save clobbered register - may not actually be necessary if inline asm
-     * functions are considered to use the same rules as function calls by the
-     * compiler. */
+    functions are considered to use the same rules as function calls by the
+    compiler. */
     PUSH.L R5
     /* Set ITU SWINTR. */
-    MOV.L # 553696, R5
-        MOV.B # 1, [ R5 ]
+    MOV.L #553696, R5
+    MOV.B #1, [R5]
     /* Read back to ensure the value is taken before proceeding. */
-    MOV.L[ R5 ], R5
+    MOV.L [R5], R5
     /* Restore clobbered register to its previous value. */
     POP R5
 }
-#define portYIELD()                                       vPortYield()
-#define portYIELD_FROM_ISR( x )                           do { if( x != pdFALSE ) portYIELD( ); } while( 0 )
+#define portYIELD() vPortYield()
+#define portYIELD_FROM_ISR( x ) do { if( x != pdFALSE ) portYIELD(); } while( 0 )
 
 /* These macros should not be called directly, but through the
- * taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
- * performed if configASSERT() is defined to ensure an assertion handler does not
- * inadvertently attempt to lower the IPL when the call to assert was triggered
- * because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
- * when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
- * functions are those that end in FromISR.  FreeRTOS maintains a separate
- * interrupt API to ensure API function and interrupt entry is as fast and as
- * simple as possible. */
-#define portENABLE_INTERRUPTS()                           set_ipl( ( long ) 0 )
+taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
+performed if configASSERT() is defined to ensure an assertion handler does not
+inadvertently attempt to lower the IPL when the call to assert was triggered
+because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
+when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
+functions are those that end in FromISR.  FreeRTOS maintains a separate
+interrupt API to ensure API function and interrupt entry is as fast and as
+simple as possible. */
+#define portENABLE_INTERRUPTS()     set_ipl( ( long ) 0 )
 #ifdef configASSERT
-    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    configASSERT( ( get_ipl() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
-    #define portDISABLE_INTERRUPTS()                      if( get_ipl() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( get_ipl() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+    #define portDISABLE_INTERRUPTS()    if( get_ipl() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
 #else
-    #define portDISABLE_INTERRUPTS()                      set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+    #define portDISABLE_INTERRUPTS()    set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
 #endif
 
 /* Critical nesting counts are stored in the TCB. */
-#define portCRITICAL_NESTING_IN_TCB    ( 1 )
+#define portCRITICAL_NESTING_IN_TCB ( 1 )
 
 /* The critical nesting functions defined within tasks.c. */
 extern void vTaskEnterCritical( void );
 extern void vTaskExitCritical( void );
-#define portENTER_CRITICAL()                                           vTaskEnterCritical()
-#define portEXIT_CRITICAL()                                            vTaskExitCritical()
+#define portENTER_CRITICAL()    vTaskEnterCritical()
+#define portEXIT_CRITICAL()     vTaskExitCritical()
 
 /* As this port allows interrupt nesting... */
-#define portSET_INTERRUPT_MASK_FROM_ISR()                              get_ipl(); set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus )    set_ipl( ( long ) uxSavedInterruptStatus )
+#define portSET_INTERRUPT_MASK_FROM_ISR() get_ipl(); set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) set_ipl( ( long ) uxSavedInterruptStatus )
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/Renesas/RX600v2/port.c b/portable/Renesas/RX600v2/port.c
index 39136f882..ee7da87e6 100644
--- a/portable/Renesas/RX600v2/port.c
+++ b/portable/Renesas/RX600v2/port.c
@@ -27,8 +27,8 @@
  */
 
 /*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the RX600 port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the RX600 port.
+ *----------------------------------------------------------*/
 
 /* Scheduler includes. */
 #include "FreeRTOS.h"
@@ -47,15 +47,15 @@
 /*-----------------------------------------------------------*/
 
 /* Tasks should start with interrupts enabled and in Supervisor mode, therefore
- * PSW is set with U and I set, and PM and IPL clear. */
+PSW is set with U and I set, and PM and IPL clear. */
 #define portINITIAL_PSW     ( ( StackType_t ) 0x00030000 )
 #define portINITIAL_FPSW    ( ( StackType_t ) 0x00000100 )
 
 /*-----------------------------------------------------------*/
 
 /* The following lines are to ensure vSoftwareInterruptEntry can be referenced,
- * and therefore installed in the vector table, when the FreeRTOS code is built
- * as a library. */
+ and therefore installed in the vector table, when the FreeRTOS code is built
+as a library. */
 extern BaseType_t vSoftwareInterruptEntry;
 const BaseType_t * p_vSoftwareInterruptEntry = &vSoftwareInterruptEntry;
 
@@ -85,8 +85,8 @@ void vSoftwareInterruptISR( void );
 /*-----------------------------------------------------------*/
 
 /* This is accessed by the inline assembler functions so is file scope for
- * convenience. */
-extern void * pxCurrentTCB;
+convenience. */
+extern void *pxCurrentTCB;
 extern void vTaskSwitchContext( void );
 
 /*-----------------------------------------------------------*/
@@ -94,9 +94,7 @@ extern void vTaskSwitchContext( void );
 /*
  * See header file for description.
  */
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
 {
     /* R0 is not included as it is the stack pointer. */
 
@@ -107,8 +105,8 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
     *pxTopOfStack = ( StackType_t ) pxCode;
 
     /* When debugging it can be useful if every register is set to a known
-     * value.  Otherwise code space can be saved by just setting the registers
-     * that need to be set. */
+    value.  Otherwise code space can be saved by just setting the registers
+    that need to be set. */
     #ifdef USE_FULL_REGISTER_INITIALISATION
     {
         pxTopOfStack--;
@@ -141,11 +139,11 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
         *pxTopOfStack = 0x22222222;
         pxTopOfStack--;
     }
-    #else /* ifdef USE_FULL_REGISTER_INITIALISATION */
+    #else
     {
         pxTopOfStack -= 15;
     }
-    #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */
+    #endif
 
     *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
     pxTopOfStack--;
@@ -169,14 +167,14 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
 
 BaseType_t xPortStartScheduler( void )
 {
-    extern void vApplicationSetupTimerInterrupt( void );
+extern void vApplicationSetupTimerInterrupt( void );
 
     /* Use pxCurrentTCB just so it does not get optimised away. */
     if( pxCurrentTCB != NULL )
     {
         /* Call an application function to set up the timer that will generate the
-         * tick interrupt.  This way the application can decide which peripheral to
-         * use.  A demo application is provided to show a suitable example. */
+        tick interrupt.  This way the application can decide which peripheral to
+        use.  A demo application is provided to show a suitable example. */
         vApplicationSetupTimerInterrupt();
 
         /* Enable the software interrupt. */
@@ -204,36 +202,36 @@ BaseType_t xPortStartScheduler( void )
 static void prvStartFirstTask( void )
 {
     /* When starting the scheduler there is nothing that needs moving to the
-     * interrupt stack because the function is not called from an interrupt.
-     * Just ensure the current stack is the user stack. */
-    SETPSW U
+    interrupt stack because the function is not called from an interrupt.
+    Just ensure the current stack is the user stack. */
+    SETPSW  U
 
     /* Obtain the location of the stack associated with which ever task
-     * pxCurrentTCB is currently pointing to. */
-    MOV.L   # _pxCurrentTCB, R15
-        MOV.L[ R15 ], R15
-        MOV.L[ R15 ], R0
+    pxCurrentTCB is currently pointing to. */
+    MOV.L   #_pxCurrentTCB, R15
+    MOV.L   [R15], R15
+    MOV.L   [R15], R0
 
     /* Restore the registers from the stack of the task pointed to by
-     * pxCurrentTCB. */
-    POP R15
-    MVTACLO R15, A0 /* Accumulator low 32 bits. */
-    POP R15
-    MVTACHI R15, A0 /* Accumulator high 32 bits. */
-    POP R15
-    MVTACGU R15, A0 /* Accumulator guard. */
-    POP R15
-    MVTACLO R15, A1 /* Accumulator low 32 bits. */
-    POP R15
-    MVTACHI R15, A1 /* Accumulator high 32 bits. */
-    POP R15
-    MVTACGU R15, A1 /* Accumulator guard. */
-    POP R15
-    MVTC R15, FPSW  /* Floating point status word. */
-    POPM R1 - R15   /* R1 to R15 - R0 is not included as it is the SP. */
-    RTE             /* This pops the remaining registers. */
+    pxCurrentTCB. */
+    POP     R15
+    MVTACLO R15, A0     /* Accumulator low 32 bits. */
+    POP     R15
+    MVTACHI R15, A0     /* Accumulator high 32 bits. */
+    POP     R15
+    MVTACGU R15, A0     /* Accumulator guard. */
+    POP     R15
+    MVTACLO R15, A1     /* Accumulator low 32 bits. */
+    POP     R15
+    MVTACHI R15, A1     /* Accumulator high 32 bits. */
+    POP     R15
+    MVTACGU R15, A1     /* Accumulator guard. */
+    POP     R15
+    MVTC    R15,FPSW    /* Floating point status word. */
+    POPM    R1-R15      /* R1 to R15 - R0 is not included as it is the SP. */
+    RTE                 /* This pops the remaining registers. */
+    NOP
     NOP
-        NOP
 }
 /*-----------------------------------------------------------*/
 
@@ -241,7 +239,7 @@ static void prvStartFirstTask( void )
 void vTickISR( void )
 {
     /* Increment the tick, and perform any processing the new tick value
-     * necessitates. */
+    necessitates. */
     set_ipl( configMAX_SYSCALL_INTERRUPT_PRIORITY );
     {
         if( xTaskIncrementTick() != pdFALSE )
@@ -249,7 +247,6 @@ void vTickISR( void )
             taskYIELD();
         }
     }
-
     set_ipl( configKERNEL_INTERRUPT_PRIORITY );
 }
 /*-----------------------------------------------------------*/
@@ -264,105 +261,99 @@ void vSoftwareInterruptISR( void )
 static void prvYieldHandler( void )
 {
     /* Re-enable interrupts. */
-    SETPSW I
+    SETPSW  I
 
     /* Move the data that was automatically pushed onto the interrupt stack when
-     * the interrupt occurred from the interrupt stack to the user stack.
-     *
-     * R15 is saved before it is clobbered. */
-    PUSH.L R15
+    the interrupt occurred from the interrupt stack to the user stack.
+
+    R15 is saved before it is clobbered. */
+    PUSH.L  R15
 
     /* Read the user stack pointer. */
-    MVFC USP, R15
+    MVFC    USP, R15
 
     /* Move the address down to the data being moved. */
-         SUB     # 12, R15
-    MVTC R15, USP
+    SUB     #12, R15
+    MVTC    R15, USP
 
     /* Copy the data across. */
-         MOV.L[ R0 ], [ R15 ];
-    R15
-
-    MOV.L   4[ R0 ], 4[ R15 ];
-    PC
-    MOV.L   8[ R0 ], 8[ R15 ];
-    PSW
+    MOV.L   [ R0 ], [ R15 ] ; R15
+    MOV.L   4[ R0 ], 4[ R15 ]  ; PC
+    MOV.L   8[ R0 ], 8[ R15 ]  ; PSW
 
     /* Move the interrupt stack pointer to its new correct position. */
-        ADD # 12, R0
+    ADD #12, R0
 
     /* All the rest of the registers are saved directly to the user stack. */
-    SETPSW U
+    SETPSW  U
 
     /* Save the rest of the general registers (R15 has been saved already). */
-    PUSHM R1 - R14
+    PUSHM   R1-R14
 
     /* Save the FPSW and accumulators. */
-    MVFC FPSW, R15
-        PUSH.L R15
-        MVFACGU # 0, A1, R15
-        PUSH.L R15
-        MVFACHI # 0, A1, R15
-        PUSH.L R15
-        MVFACLO # 0, A1, R15;
-    Low order word.
-       PUSH.L R15
-        MVFACGU # 0, A0, R15
-        PUSH.L R15
-        MVFACHI # 0, A0, R15
-        PUSH.L R15
-        MVFACLO # 0, A0, R15;
-    Low order word.
-       PUSH.L R15
+    MVFC    FPSW, R15
+    PUSH.L  R15
+    MVFACGU #0, A1, R15
+    PUSH.L  R15
+    MVFACHI #0, A1, R15
+    PUSH.L  R15
+    MVFACLO #0, A1, R15 ; Low order word.
+    PUSH.L  R15
+    MVFACGU #0, A0, R15
+    PUSH.L  R15
+    MVFACHI #0, A0, R15
+    PUSH.L  R15
+    MVFACLO #0, A0, R15 ; Low order word.
+    PUSH.L  R15
 
     /* Save the stack pointer to the TCB. */
-    MOV.L   # _pxCurrentTCB, R15
-        MOV.L[ R15 ], R15
-        MOV.L R0, [ R15 ]
+    MOV.L   #_pxCurrentTCB, R15
+    MOV.L   [ R15 ], R15
+    MOV.L   R0, [ R15 ]
 
     /* Ensure the interrupt mask is set to the syscall priority while the kernel
-     * structures are being accessed. */
-    MVTIPL  # configMAX_SYSCALL_INTERRUPT_PRIORITY
+    structures are being accessed. */
+    MVTIPL  #configMAX_SYSCALL_INTERRUPT_PRIORITY
 
     /* Select the next task to run. */
-    BSR.A _vTaskSwitchContext
+    BSR.A   _vTaskSwitchContext
 
     /* Reset the interrupt mask as no more data structure access is required. */
-    MVTIPL  # configKERNEL_INTERRUPT_PRIORITY
+    MVTIPL  #configKERNEL_INTERRUPT_PRIORITY
 
     /* Load the stack pointer of the task that is now selected as the Running
-     * state task from its TCB. */
-    MOV.L   # _pxCurrentTCB, R15
-        MOV.L[ R15 ], R15
-        MOV.L[ R15 ], R0
+    state task from its TCB. */
+    MOV.L   #_pxCurrentTCB,R15
+    MOV.L   [ R15 ], R15
+    MOV.L   [ R15 ], R0
 
     /* Restore the context of the new task.  The PSW (Program Status Word) and
-     * PC will be popped by the RTE instruction. */
-    POP R15
-    MVTACLO R15, A0 /* Accumulator low 32 bits. */
-    POP R15
-    MVTACHI R15, A0 /* Accumulator high 32 bits. */
-    POP R15
-    MVTACGU R15, A0 /* Accumulator guard. */
-    POP R15
-    MVTACLO R15, A1 /* Accumulator low 32 bits. */
-    POP R15
-    MVTACHI R15, A1 /* Accumulator high 32 bits. */
-    POP R15
-    MVTACGU R15, A1 /* Accumulator guard. */
-    POP R15
-    MVTC R15, FPSW
-    POPM R1 - R15
+    PC will be popped by the RTE instruction. */
+    POP     R15
+    MVTACLO R15, A0     /* Accumulator low 32 bits. */
+    POP     R15
+    MVTACHI R15, A0     /* Accumulator high 32 bits. */
+    POP     R15
+    MVTACGU R15, A0     /* Accumulator guard. */
+    POP     R15
+    MVTACLO R15, A1     /* Accumulator low 32 bits. */
+    POP     R15
+    MVTACHI R15, A1     /* Accumulator high 32 bits. */
+    POP     R15
+    MVTACGU R15, A1     /* Accumulator guard. */
+    POP     R15
+    MVTC    R15,FPSW
+    POPM    R1-R15
     RTE
     NOP
-        NOP
+    NOP
 }
 /*-----------------------------------------------------------*/
 
 void vPortEndScheduler( void )
 {
     /* Not implemented in ports where there is nothing to return to.
-     * Artificially force an assert. */
+    Artificially force an assert. */
     configASSERT( pxCurrentTCB == NULL );
 
     /* The following line is just to prevent the symbol getting optimised away. */
diff --git a/portable/Renesas/RX600v2/portmacro.h b/portable/Renesas/RX600v2/portmacro.h
index a35beaaca..6efba647d 100644
--- a/portable/Renesas/RX600v2/portmacro.h
+++ b/portable/Renesas/RX600v2/portmacro.h
@@ -50,94 +50,94 @@
  */
 
 /* Type definitions - these are a bit legacy and not really used now, other than
- * portSTACK_TYPE and portBASE_TYPE. */
-#define portCHAR          char
-#define portFLOAT         float
-#define portDOUBLE        double
-#define portLONG          long
-#define portSHORT         short
-#define portSTACK_TYPE    uint32_t
-#define portBASE_TYPE     long
+portSTACK_TYPE and portBASE_TYPE. */
+#define portCHAR        char
+#define portFLOAT       float
+#define portDOUBLE      double
+#define portLONG        long
+#define portSHORT       short
+#define portSTACK_TYPE  uint32_t
+#define portBASE_TYPE   long
 
-typedef portSTACK_TYPE   StackType_t;
-typedef long             BaseType_t;
-typedef unsigned long    UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
 
-#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t     TickType_t;
-    #define portMAX_DELAY              ( TickType_t ) 0xffff
+#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t TickType_t;
+    #define portMAX_DELAY ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t     TickType_t;
-    #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+    typedef uint32_t TickType_t;
+    #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
 
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
-    #define portTICK_TYPE_IS_ATOMIC    1
+    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+    not need to be guarded with a critical section. */
+    #define portTICK_TYPE_IS_ATOMIC 1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portBYTE_ALIGNMENT    8             /* Could make four, according to manual. */
-#define portSTACK_GROWTH      -1
-#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portNOP()    nop()
+#define portBYTE_ALIGNMENT              8   /* Could make four, according to manual. */
+#define portSTACK_GROWTH                -1
+#define portTICK_PERIOD_MS              ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()                       nop()
 
 
 #pragma inline_asm vPortYield
 static void vPortYield( void )
 {
     /* Save clobbered register - may not actually be necessary if inline asm
-     * functions are considered to use the same rules as function calls by the
-     * compiler. */
+    functions are considered to use the same rules as function calls by the
+    compiler. */
     PUSH.L R5
     /* Set ITU SWINTR. */
-    MOV.L # 553696, R5
-        MOV.B # 1, [ R5 ]
+    MOV.L #553696, R5
+    MOV.B #1, [R5]
     /* Read back to ensure the value is taken before proceeding. */
-    MOV.L[ R5 ], R5
+    MOV.L [R5], R5
     /* Restore clobbered register to its previous value. */
     POP R5
 }
-#define portYIELD()                                       vPortYield()
-#define portYIELD_FROM_ISR( x )                           do { if( x != pdFALSE ) portYIELD( ); } while( 0 )
+#define portYIELD() vPortYield()
+#define portYIELD_FROM_ISR( x ) do { if( x != pdFALSE ) portYIELD(); } while( 0 )
 
 /* These macros should not be called directly, but through the
- * taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
- * performed if configASSERT() is defined to ensure an assertion handler does not
- * inadvertently attempt to lower the IPL when the call to assert was triggered
- * because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
- * when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
- * functions are those that end in FromISR.  FreeRTOS maintains a separate
- * interrupt API to ensure API function and interrupt entry is as fast and as
- * simple as possible. */
-#define portENABLE_INTERRUPTS()                           set_ipl( ( long ) 0 )
+taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
+performed if configASSERT() is defined to ensure an assertion handler does not
+inadvertently attempt to lower the IPL when the call to assert was triggered
+because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
+when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
+functions are those that end in FromISR.  FreeRTOS maintains a separate
+interrupt API to ensure API function and interrupt entry is as fast and as
+simple as possible. */
+#define portENABLE_INTERRUPTS()     set_ipl( ( long ) 0 )
 #ifdef configASSERT
-    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    configASSERT( ( get_ipl() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
-    #define portDISABLE_INTERRUPTS()                      if( get_ipl() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( get_ipl() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+    #define portDISABLE_INTERRUPTS()    if( get_ipl() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
 #else
-    #define portDISABLE_INTERRUPTS()                      set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+    #define portDISABLE_INTERRUPTS()    set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
 #endif
 
 /* Critical nesting counts are stored in the TCB. */
-#define portCRITICAL_NESTING_IN_TCB    ( 1 )
+#define portCRITICAL_NESTING_IN_TCB ( 1 )
 
 /* The critical nesting functions defined within tasks.c. */
 extern void vTaskEnterCritical( void );
 extern void vTaskExitCritical( void );
-#define portENTER_CRITICAL()                                           vTaskEnterCritical()
-#define portEXIT_CRITICAL()                                            vTaskExitCritical()
+#define portENTER_CRITICAL()    vTaskEnterCritical()
+#define portEXIT_CRITICAL()     vTaskExitCritical()
 
 /* As this port allows interrupt nesting... */
-#define portSET_INTERRUPT_MASK_FROM_ISR()                              ( UBaseType_t ) get_ipl(); set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus )    set_ipl( ( long ) uxSavedInterruptStatus )
+#define portSET_INTERRUPT_MASK_FROM_ISR() ( UBaseType_t ) get_ipl(); set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) set_ipl( ( long ) uxSavedInterruptStatus )
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/Renesas/RX700v3_DPFPU/port.c b/portable/Renesas/RX700v3_DPFPU/port.c
index 99f14c7aa..26cb9f020 100644
--- a/portable/Renesas/RX700v3_DPFPU/port.c
+++ b/portable/Renesas/RX700v3_DPFPU/port.c
@@ -54,22 +54,22 @@
 
 /* Tasks should start with interrupts enabled and in Supervisor mode, therefore
  * PSW is set with U and I set, and PM and IPL clear. */
-#define portINITIAL_PSW                  ( ( StackType_t ) 0x00030000 )
-#define portINITIAL_FPSW                 ( ( StackType_t ) 0x00000100 )
-#define portINITIAL_DPSW                 ( ( StackType_t ) 0x00000100 )
-#define portINITIAL_DCMR                 ( ( StackType_t ) 0x00000000 )
-#define portINITIAL_DECNT                ( ( StackType_t ) 0x00000001 )
+#define portINITIAL_PSW     ( ( StackType_t ) 0x00030000 )
+#define portINITIAL_FPSW    ( ( StackType_t ) 0x00000100 )
+#define portINITIAL_DPSW    ( ( StackType_t ) 0x00000100 )
+#define portINITIAL_DCMR    ( ( StackType_t ) 0x00000000 )
+#define portINITIAL_DECNT   ( ( StackType_t ) 0x00000001 )
 
 /* Tasks are not created with a DPFPU context, but can be given a DPFPU context
  * after they have been created.  A variable is stored as part of the tasks context
  * that holds portNO_DPFPU_CONTEXT if the task does not have a DPFPU context, or
  * any other value if the task does have a DPFPU context. */
-#define portNO_DPFPU_CONTEXT             ( ( StackType_t ) 0 )
-#define portHAS_DPFPU_CONTEXT            ( ( StackType_t ) 1 )
+#define portNO_DPFPU_CONTEXT    ( ( StackType_t ) 0 )
+#define portHAS_DPFPU_CONTEXT   ( ( StackType_t ) 1 )
 
 /* The space on the stack required to hold the DPFPU data registers.  This is 16
  * 64-bit registers. */
-#define portDPFPU_DATA_REGISTER_WORDS    ( 16 * 2 )
+#define portDPFPU_DATA_REGISTER_WORDS   ( 16 * 2 )
 
 /*-----------------------------------------------------------*/
 
@@ -144,41 +144,41 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
      * value.  Otherwise code space can be saved by just setting the registers
      * that need to be set. */
     #ifdef USE_FULL_REGISTER_INITIALISATION
-    {
-        pxTopOfStack--;
-        *pxTopOfStack = 0xffffffff; /* r15. */
-        pxTopOfStack--;
-        *pxTopOfStack = 0xeeeeeeee;
-        pxTopOfStack--;
-        *pxTopOfStack = 0xdddddddd;
-        pxTopOfStack--;
-        *pxTopOfStack = 0xcccccccc;
-        pxTopOfStack--;
-        *pxTopOfStack = 0xbbbbbbbb;
-        pxTopOfStack--;
-        *pxTopOfStack = 0xaaaaaaaa;
-        pxTopOfStack--;
-        *pxTopOfStack = 0x99999999;
-        pxTopOfStack--;
-        *pxTopOfStack = 0x88888888;
-        pxTopOfStack--;
-        *pxTopOfStack = 0x77777777;
-        pxTopOfStack--;
-        *pxTopOfStack = 0x66666666;
-        pxTopOfStack--;
-        *pxTopOfStack = 0x55555555;
-        pxTopOfStack--;
-        *pxTopOfStack = 0x44444444;
-        pxTopOfStack--;
-        *pxTopOfStack = 0x33333333;
-        pxTopOfStack--;
-        *pxTopOfStack = 0x22222222;
-        pxTopOfStack--;
-    }
+        {
+            pxTopOfStack--;
+            *pxTopOfStack = 0xffffffff; /* r15. */
+            pxTopOfStack--;
+            *pxTopOfStack = 0xeeeeeeee;
+            pxTopOfStack--;
+            *pxTopOfStack = 0xdddddddd;
+            pxTopOfStack--;
+            *pxTopOfStack = 0xcccccccc;
+            pxTopOfStack--;
+            *pxTopOfStack = 0xbbbbbbbb;
+            pxTopOfStack--;
+            *pxTopOfStack = 0xaaaaaaaa;
+            pxTopOfStack--;
+            *pxTopOfStack = 0x99999999;
+            pxTopOfStack--;
+            *pxTopOfStack = 0x88888888;
+            pxTopOfStack--;
+            *pxTopOfStack = 0x77777777;
+            pxTopOfStack--;
+            *pxTopOfStack = 0x66666666;
+            pxTopOfStack--;
+            *pxTopOfStack = 0x55555555;
+            pxTopOfStack--;
+            *pxTopOfStack = 0x44444444;
+            pxTopOfStack--;
+            *pxTopOfStack = 0x33333333;
+            pxTopOfStack--;
+            *pxTopOfStack = 0x22222222;
+            pxTopOfStack--;
+        }
     #else /* ifdef USE_FULL_REGISTER_INITIALISATION */
-    {
-        pxTopOfStack -= 15;
-    }
+        {
+            pxTopOfStack -= 15;
+        }
     #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */
 
     *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
@@ -198,73 +198,73 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
     *pxTopOfStack = 0x66666666; /* Accumulator 0. */
 
     #if ( configUSE_TASK_DPFPU_SUPPORT == 1 )
-    {
-        /* The task will start without a DPFPU context.  A task that
-         * uses the DPFPU hardware must call vPortTaskUsesDPFPU() before
-         * executing any floating point instructions. */
-        pxTopOfStack--;
-        *pxTopOfStack = portNO_DPFPU_CONTEXT;
-    }
+        {
+            /* The task will start without a DPFPU context.  A task that
+             * uses the DPFPU hardware must call vPortTaskUsesDPFPU() before
+             * executing any floating point instructions. */
+            pxTopOfStack--;
+            *pxTopOfStack = portNO_DPFPU_CONTEXT;
+        }
     #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 )
-    {
-        /* The task will start with a DPFPU context.  Leave enough
-         * space for the registers - and ensure they are initialised if desired. */
-        #ifdef USE_FULL_REGISTER_INITIALISATION
         {
-            pxTopOfStack -= 2;
-            *( double * ) pxTopOfStack = 1515.1515;  /* DR15. */
-            pxTopOfStack -= 2;
-            *( double * ) pxTopOfStack = 1414.1414;  /* DR14. */
-            pxTopOfStack -= 2;
-            *( double * ) pxTopOfStack = 1313.1313;  /* DR13. */
-            pxTopOfStack -= 2;
-            *( double * ) pxTopOfStack = 1212.1212;  /* DR12. */
-            pxTopOfStack -= 2;
-            *( double * ) pxTopOfStack = 1111.1111;  /* DR11. */
-            pxTopOfStack -= 2;
-            *( double * ) pxTopOfStack = 1010.1010;  /* DR10. */
-            pxTopOfStack -= 2;
-            *( double * ) pxTopOfStack = 909.0909;   /* DR9. */
-            pxTopOfStack -= 2;
-            *( double * ) pxTopOfStack = 808.0808;   /* DR8. */
-            pxTopOfStack -= 2;
-            *( double * ) pxTopOfStack = 707.0707;   /* DR7. */
-            pxTopOfStack -= 2;
-            *( double * ) pxTopOfStack = 606.0606;   /* DR6. */
-            pxTopOfStack -= 2;
-            *( double * ) pxTopOfStack = 505.0505;   /* DR5. */
-            pxTopOfStack -= 2;
-            *( double * ) pxTopOfStack = 404.0404;   /* DR4. */
-            pxTopOfStack -= 2;
-            *( double * ) pxTopOfStack = 303.0303;   /* DR3. */
-            pxTopOfStack -= 2;
-            *( double * ) pxTopOfStack = 202.0202;   /* DR2. */
-            pxTopOfStack -= 2;
-            *( double * ) pxTopOfStack = 101.0101;   /* DR1. */
-            pxTopOfStack -= 2;
-            *( double * ) pxTopOfStack = 9876.54321; /* DR0. */
+            /* The task will start with a DPFPU context.  Leave enough
+             * space for the registers - and ensure they are initialised if desired. */
+            #ifdef USE_FULL_REGISTER_INITIALISATION
+                {
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack = 1515.1515; /* DR15. */
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack = 1414.1414; /* DR14. */
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack = 1313.1313; /* DR13. */
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack = 1212.1212; /* DR12. */
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack = 1111.1111; /* DR11. */
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack = 1010.1010; /* DR10. */
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack =  909.0909; /* DR9. */
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack =  808.0808; /* DR8. */
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack =  707.0707; /* DR7. */
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack =  606.0606; /* DR6. */
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack =  505.0505; /* DR5. */
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack =  404.0404; /* DR4. */
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack =  303.0303; /* DR3. */
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack =  202.0202; /* DR2. */
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack =  101.0101; /* DR1. */
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack = 9876.54321;/* DR0. */
+                }
+            #else /* ifdef USE_FULL_REGISTER_INITIALISATION */
+                {
+                    pxTopOfStack -= portDPFPU_DATA_REGISTER_WORDS;
+                    memset( pxTopOfStack, 0x00, portDPFPU_DATA_REGISTER_WORDS * sizeof( StackType_t ) );
+                }
+            #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */
+            pxTopOfStack--;
+            *pxTopOfStack = portINITIAL_DECNT; /* DECNT. */
+            pxTopOfStack--;
+            *pxTopOfStack = portINITIAL_DCMR;  /* DCMR. */
+            pxTopOfStack--;
+            *pxTopOfStack = portINITIAL_DPSW;  /* DPSW. */
         }
-        #else /* ifdef USE_FULL_REGISTER_INITIALISATION */
-        {
-            pxTopOfStack -= portDPFPU_DATA_REGISTER_WORDS;
-            memset( pxTopOfStack, 0x00, portDPFPU_DATA_REGISTER_WORDS * sizeof( StackType_t ) );
-        }
-        #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */
-        pxTopOfStack--;
-        *pxTopOfStack = portINITIAL_DECNT; /* DECNT. */
-        pxTopOfStack--;
-        *pxTopOfStack = portINITIAL_DCMR;  /* DCMR. */
-        pxTopOfStack--;
-        *pxTopOfStack = portINITIAL_DPSW;  /* DPSW. */
-    }
     #elif ( configUSE_TASK_DPFPU_SUPPORT == 0 )
-    {
-        /* Omit DPFPU support. */
-    }
+        {
+            /* Omit DPFPU support. */
+        }
     #else /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */
-    {
-        #error Invalid configUSE_TASK_DPFPU_SUPPORT setting - configUSE_TASK_DPFPU_SUPPORT must be set to 0, 1, 2, or left undefined.
-    }
+        {
+            #error Invalid configUSE_TASK_DPFPU_SUPPORT setting - configUSE_TASK_DPFPU_SUPPORT must be set to 0, 1, 2, or left undefined.
+        }
     #endif /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */
 
     return pxTopOfStack;
@@ -330,74 +330,78 @@ void vPortEndScheduler( void )
 #pragma inline_asm prvStartFirstTask
 static void prvStartFirstTask( void )
 {
-    #ifndef __CDT_PARSER__
+#ifndef __CDT_PARSER__
 
-        /* When starting the scheduler there is nothing that needs moving to the
-         * interrupt stack because the function is not called from an interrupt.
-         * Just ensure the current stack is the user stack. */
-        SETPSW U
+    /* When starting the scheduler there is nothing that needs moving to the
+     * interrupt stack because the function is not called from an interrupt.
+     * Just ensure the current stack is the user stack. */
+    SETPSW U
 
 
-        /* Obtain the location of the stack associated with which ever task
-         * pxCurrentTCB is currently pointing to. */
-        MOV.L # _pxCurrentTCB, R15
-            MOV.L[ R15 ], R15
-            MOV.L[ R15 ], R0
+    /* Obtain the location of the stack associated with which ever task
+     * pxCurrentTCB is currently pointing to. */
+    MOV.L # _pxCurrentTCB, R15
+    MOV.L [ R15 ], R15
+    MOV.L [ R15 ], R0
 
 
-        /* Restore the registers from the stack of the task pointed to by
-         * pxCurrentTCB. */
+    /* Restore the registers from the stack of the task pointed to by
+     * pxCurrentTCB. */
 
-        #if ( configUSE_TASK_DPFPU_SUPPORT == 1 )
-
-            /* The restored ulPortTaskHasDPFPUContext is to be zero here.
-             * So, it is never necessary to restore the DPFPU context here. */
-            POP R15
-            MOV.L # _ulPortTaskHasDPFPUContext, R14
-            MOV.L R15, [ R14 ]
-        #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 )
-            /* Restore the DPFPU context. */
-            DPOPM.L DPSW - DECNT
-            DPOPM.D DR0 - DR15
-        #endif /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */
+    #if ( configUSE_TASK_DPFPU_SUPPORT == 1 )
 
+        /* The restored ulPortTaskHasDPFPUContext is to be zero here.
+         * So, it is never necessary to restore the DPFPU context here. */
         POP R15
+        MOV.L # _ulPortTaskHasDPFPUContext, R14
+        MOV.L R15, [ R14 ]
 
-        /* Accumulator low 32 bits. */
-        MVTACLO R15, A0
-        POP R15
+    #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 )
 
-        /* Accumulator high 32 bits. */
-        MVTACHI R15, A0
-        POP R15
+        /* Restore the DPFPU context. */
+        DPOPM.L DPSW-DECNT
+        DPOPM.D DR0-DR15
 
-        /* Accumulator guard. */
-        MVTACGU R15, A0
-        POP R15
+    #endif /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */
 
-        /* Accumulator low 32 bits. */
-        MVTACLO R15, A1
-        POP R15
+    POP R15
 
-        /* Accumulator high 32 bits. */
-        MVTACHI R15, A1
-        POP R15
+    /* Accumulator low 32 bits. */
+    MVTACLO R15, A0
+    POP R15
 
-        /* Accumulator guard. */
-        MVTACGU R15, A1
-        POP R15
+    /* Accumulator high 32 bits. */
+    MVTACHI R15, A0
+    POP R15
 
-        /* Floating point status word. */
-        MVTC R15, FPSW
+    /* Accumulator guard. */
+    MVTACGU R15, A0
+    POP R15
 
-        /* R1 to R15 - R0 is not included as it is the SP. */
-        POPM R1 - R15
+    /* Accumulator low 32 bits. */
+    MVTACLO R15, A1
+    POP R15
 
-        /* This pops the remaining registers. */
-        RTE
-        NOP
-            NOP
-    #endif /* ifndef __CDT_PARSER__ */
+    /* Accumulator high 32 bits. */
+    MVTACHI R15, A1
+    POP R15
+
+    /* Accumulator guard. */
+    MVTACGU R15, A1
+    POP R15
+
+    /* Floating point status word. */
+    MVTC R15, FPSW
+
+    /* R1 to R15 - R0 is not included as it is the SP. */
+    POPM R1-R15
+
+    /* This pops the remaining registers. */
+    RTE
+    NOP
+    NOP
+
+#endif /* ifndef __CDT_PARSER__ */
 }
 /*-----------------------------------------------------------*/
 
@@ -410,155 +414,163 @@ void vSoftwareInterruptISR( void )
 #pragma inline_asm prvYieldHandler
 static void prvYieldHandler( void )
 {
-    #ifndef __CDT_PARSER__
-        /* Re-enable interrupts. */
-        SETPSW I
+#ifndef __CDT_PARSER__
+
+    /* Re-enable interrupts. */
+    SETPSW I
 
 
-        /* Move the data that was automatically pushed onto the interrupt stack when
-         * the interrupt occurred from the interrupt stack to the user stack.
-         *
-         * R15 is saved before it is clobbered. */
+    /* Move the data that was automatically pushed onto the interrupt stack when
+     * the interrupt occurred from the interrupt stack to the user stack.
+     *
+     * R15 is saved before it is clobbered. */
+    PUSH.L R15
+
+    /* Read the user stack pointer. */
+    MVFC USP, R15
+
+    /* Move the address down to the data being moved. */
+    SUB # 12, R15
+    MVTC R15, USP
+
+    /* Copy the data across, R15, then PC, then PSW. */
+    MOV.L [ R0 ], [ R15 ]
+    MOV.L 4[ R0 ], 4[ R15 ]
+    MOV.L 8[ R0 ], 8[ R15 ]
+
+    /* Move the interrupt stack pointer to its new correct position. */
+    ADD # 12, R0
+
+    /* All the rest of the registers are saved directly to the user stack. */
+    SETPSW U
+
+    /* Save the rest of the general registers (R15 has been saved already). */
+    PUSHM R1-R14
+
+    /* Save the FPSW and accumulators. */
+    MVFC FPSW, R15
+    PUSH.L R15
+    MVFACGU # 0, A1, R15
+    PUSH.L R15
+    MVFACHI # 0, A1, R15
+    PUSH.L R15
+    MVFACLO # 0, A1, R15 /* Low order word. */
+    PUSH.L R15
+    MVFACGU # 0, A0, R15
+    PUSH.L R15
+    MVFACHI # 0, A0, R15
+    PUSH.L R15
+    MVFACLO # 0, A0, R15 /* Low order word. */
+    PUSH.L R15
+
+    #if ( configUSE_TASK_DPFPU_SUPPORT == 1 )
+
+        /* Does the task have a DPFPU context that needs saving?  If
+         * ulPortTaskHasDPFPUContext is 0 then no. */
+        MOV.L # _ulPortTaskHasDPFPUContext, R15
+        MOV.L [ R15 ], R15
+        CMP # 0, R15
+
+        /* Save the DPFPU context, if any. */
+        BEQ.B ?+
+        DPUSHM.D DR0-DR15
+        DPUSHM.L DPSW-DECNT
+        ?:
+
+        /* Save ulPortTaskHasDPFPUContext itself. */
         PUSH.L R15
 
-        /* Read the user stack pointer. */
-        MVFC USP, R15
+    #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 )
 
-        /* Move the address down to the data being moved. */
-             SUB # 12, R15
-        MVTC R15, USP
+        /* Save the DPFPU context, always. */
+        DPUSHM.D DR0-DR15
+        DPUSHM.L DPSW-DECNT
 
-        /* Copy the data across, R15, then PC, then PSW. */
-             MOV.L[ R0 ], [ R15 ]
-        MOV.L 4[ R0 ], 4[ R15 ]
-        MOV.L 8[ R0 ], 8[ R15 ]
-
-        /* Move the interrupt stack pointer to its new correct position. */
-        ADD # 12, R0
-
-        /* All the rest of the registers are saved directly to the user stack. */
-        SETPSW U
-
-        /* Save the rest of the general registers (R15 has been saved already). */
-        PUSHM R1 - R14
-
-        /* Save the FPSW and accumulators. */
-        MVFC FPSW, R15
-             PUSH.L R15
-             MVFACGU # 0, A1, R15
-             PUSH.L R15
-             MVFACHI # 0, A1, R15
-             PUSH.L R15
-             MVFACLO # 0, A1, R15 /* Low order word. */
-             PUSH.L R15
-             MVFACGU # 0, A0, R15
-             PUSH.L R15
-             MVFACHI # 0, A0, R15
-             PUSH.L R15
-             MVFACLO # 0, A0, R15 /* Low order word. */
-             PUSH.L R15
-
-        #if ( configUSE_TASK_DPFPU_SUPPORT == 1 )
-
-            /* Does the task have a DPFPU context that needs saving?  If
-             * ulPortTaskHasDPFPUContext is 0 then no. */
-            MOV.L # _ulPortTaskHasDPFPUContext, R15
-             MOV.L[ R15 ], R15
-             CMP # 0, R15
-
-            /* Save the DPFPU context, if any. */
-             BEQ.B ? +
-            DPUSHM.D DR0 - DR15
-             DPUSHM.L DPSW - DECNT
-            ? :
-
-            /* Save ulPortTaskHasDPFPUContext itself. */
-            PUSH.L R15
-        #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 )
-            /* Save the DPFPU context, always. */
-            DPUSHM.D DR0 - DR15
-             DPUSHM.L DPSW - DECNT
-        #endif /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */
+    #endif /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */
 
 
-        /* Save the stack pointer to the TCB. */
-        MOV.L # _pxCurrentTCB, R15
-             MOV.L[ R15 ], R15
-             MOV.L R0, [ R15 ]
+    /* Save the stack pointer to the TCB. */
+    MOV.L # _pxCurrentTCB, R15
+    MOV.L [ R15 ], R15
+    MOV.L R0, [ R15 ]
 
 
-        /* Ensure the interrupt mask is set to the syscall priority while the kernel
-         * structures are being accessed. */
-        MVTIPL # configMAX_SYSCALL_INTERRUPT_PRIORITY
+    /* Ensure the interrupt mask is set to the syscall priority while the kernel
+     * structures are being accessed. */
+    MVTIPL # configMAX_SYSCALL_INTERRUPT_PRIORITY
 
-        /* Select the next task to run. */
-        BSR.A _vTaskSwitchContext
+    /* Select the next task to run. */
+    BSR.A _vTaskSwitchContext
 
-        /* Reset the interrupt mask as no more data structure access is required. */
-        MVTIPL # configKERNEL_INTERRUPT_PRIORITY
+    /* Reset the interrupt mask as no more data structure access is required. */
+    MVTIPL # configKERNEL_INTERRUPT_PRIORITY
 
 
-        /* Load the stack pointer of the task that is now selected as the Running
-         * state task from its TCB. */
-        MOV.L # _pxCurrentTCB, R15
-             MOV.L[ R15 ], R15
-             MOV.L[ R15 ], R0
+    /* Load the stack pointer of the task that is now selected as the Running
+     * state task from its TCB. */
+    MOV.L # _pxCurrentTCB, R15
+    MOV.L [ R15 ], R15
+    MOV.L [ R15 ], R0
 
 
-        /* Restore the context of the new task.  The PSW (Program Status Word) and
-         * PC will be popped by the RTE instruction. */
+    /* Restore the context of the new task.  The PSW (Program Status Word) and
+     * PC will be popped by the RTE instruction. */
 
-        #if ( configUSE_TASK_DPFPU_SUPPORT == 1 )
-
-            /* Is there a DPFPU context to restore?  If the restored
-             * ulPortTaskHasDPFPUContext is zero then no. */
-            POP R15
-             MOV.L # _ulPortTaskHasDPFPUContext, R14
-             MOV.L R15, [ R14 ]
-            CMP # 0, R15
-
-            /* Restore the DPFPU context, if any. */
-             BEQ.B ? +
-            DPOPM.L DPSW - DECNT
-             DPOPM.D DR0 - DR15
-            ? :
-        #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 )
-            /* Restore the DPFPU context, always. */
-            DPOPM.L DPSW - DECNT
-             DPOPM.D DR0 - DR15
-        #endif /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */
+    #if ( configUSE_TASK_DPFPU_SUPPORT == 1 )
 
+        /* Is there a DPFPU context to restore?  If the restored
+         * ulPortTaskHasDPFPUContext is zero then no. */
         POP R15
+        MOV.L # _ulPortTaskHasDPFPUContext, R14
+        MOV.L R15, [ R14 ]
+        CMP # 0, R15
 
-        /* Accumulator low 32 bits. */
-        MVTACLO R15, A0
-        POP R15
+        /* Restore the DPFPU context, if any. */
+        BEQ.B ?+
+        DPOPM.L DPSW-DECNT
+        DPOPM.D DR0-DR15
+        ?:
 
-        /* Accumulator high 32 bits. */
-        MVTACHI R15, A0
-        POP R15
+    #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 )
 
-        /* Accumulator guard. */
-        MVTACGU R15, A0
-        POP R15
+        /* Restore the DPFPU context, always. */
+        DPOPM.L DPSW-DECNT
+        DPOPM.D DR0-DR15
 
-        /* Accumulator low 32 bits. */
-        MVTACLO R15, A1
-        POP R15
+    #endif /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */
 
-        /* Accumulator high 32 bits. */
-        MVTACHI R15, A1
-        POP R15
+    POP R15
 
-        /* Accumulator guard. */
-        MVTACGU R15, A1
-        POP R15
-        MVTC R15, FPSW
-        POPM R1 - R15
-        RTE
-        NOP
-             NOP
-    #endif /* ifndef __CDT_PARSER__ */
+    /* Accumulator low 32 bits. */
+    MVTACLO R15, A0
+    POP R15
+
+    /* Accumulator high 32 bits. */
+    MVTACHI R15, A0
+    POP R15
+
+    /* Accumulator guard. */
+    MVTACGU R15, A0
+    POP R15
+
+    /* Accumulator low 32 bits. */
+    MVTACLO R15, A1
+    POP R15
+
+    /* Accumulator high 32 bits. */
+    MVTACHI R15, A1
+    POP R15
+
+    /* Accumulator guard. */
+    MVTACGU R15, A1
+    POP R15
+    MVTC R15, FPSW
+    POPM R1-R15
+    RTE
+    NOP
+    NOP
+
+#endif /* ifndef __CDT_PARSER__ */
 }
 /*-----------------------------------------------------------*/
 
diff --git a/portable/Renesas/RX700v3_DPFPU/portmacro.h b/portable/Renesas/RX700v3_DPFPU/portmacro.h
index 050d82432..fef13556e 100644
--- a/portable/Renesas/RX700v3_DPFPU/portmacro.h
+++ b/portable/Renesas/RX700v3_DPFPU/portmacro.h
@@ -28,7 +28,7 @@
 
 
 #ifndef PORTMACRO_H
-#define PORTMACRO_H
+    #define PORTMACRO_H
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
@@ -37,7 +37,7 @@
 /* *INDENT-ON* */
 
 /* Hardware specifics. */
-#include <machine.h>
+    #include <machine.h>
 
 /*-----------------------------------------------------------
  * Port specific definitions.
@@ -51,9 +51,9 @@
 
 /* When the FIT configurator or the Smart Configurator is used, platform.h has to be
  * used. */
-#ifndef configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H
-    #define configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H    0
-#endif
+    #ifndef configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H
+        #define configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H 0
+    #endif
 
 /* If configUSE_TASK_DPFPU_SUPPORT is set to 1 (or undefined) then each task will
  * be created without a DPFPU context, and a task must call vTaskUsesDPFPU() before
@@ -61,73 +61,72 @@
  * tasks are created with a DPFPU context by default, and calling vTaskUsesDPFPU() has
  * no effect.  If configUSE_TASK_DPFPU_SUPPORT is set to 0 then tasks never take care
  * of any DPFPU context (even if DPFPU registers are used). */
-#ifndef configUSE_TASK_DPFPU_SUPPORT
-    #define configUSE_TASK_DPFPU_SUPPORT    1
-#endif
+    #ifndef configUSE_TASK_DPFPU_SUPPORT
+        #define configUSE_TASK_DPFPU_SUPPORT 1
+    #endif
 
 /*-----------------------------------------------------------*/
 
 /* Type definitions - these are a bit legacy and not really used now, other than
  * portSTACK_TYPE and portBASE_TYPE. */
-#define portCHAR          char
-#define portFLOAT         float
-#define portDOUBLE        double
-#define portLONG          long
-#define portSHORT         short
-#define portSTACK_TYPE    uint32_t
-#define portBASE_TYPE     long
+    #define portCHAR          char
+    #define portFLOAT         float
+    #define portDOUBLE        double
+    #define portLONG          long
+    #define portSHORT         short
+    #define portSTACK_TYPE    uint32_t
+    #define portBASE_TYPE     long
 
-typedef portSTACK_TYPE   StackType_t;
-typedef long             BaseType_t;
-typedef unsigned long    UBaseType_t;
+    typedef portSTACK_TYPE   StackType_t;
+    typedef long             BaseType_t;
+    typedef unsigned long    UBaseType_t;
 
-#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t     TickType_t;
-    #define portMAX_DELAY              ( TickType_t ) 0xffff
-#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t     TickType_t;
-    #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+    #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+        typedef uint16_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffff
+    #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+        typedef uint32_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
  * not need to be guarded with a critical section. */
-    #define portTICK_TYPE_IS_ATOMIC    1
-#else
-    #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
-#endif
+        #define portTICK_TYPE_IS_ATOMIC    1
+    #else
+        #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+    #endif
 
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portBYTE_ALIGNMENT    8         /* Could make four, according to manual. */
-#define portSTACK_GROWTH      -1
-#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portNOP()    nop()
+    #define portBYTE_ALIGNMENT    8     /* Could make four, according to manual. */
+    #define portSTACK_GROWTH      -1
+    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+    #define portNOP()    nop()
 
 /* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;"
  * where portITU_SWINTR is the location of the software interrupt register
  * (0x000872E0).  Don't rely on the assembler to select a register, so instead
  * save and restore clobbered registers manually. */
-#pragma inline_asm vPortYield
-static void vPortYield( void )
-{
+    #pragma inline_asm vPortYield
+    static void vPortYield( void )
+    {
     #ifndef __CDT_PARSER__
-
         /* Save clobbered register - may not actually be necessary if inline asm
          * functions are considered to use the same rules as function calls by the
          * compiler. */
         PUSH.L R5
         /* Set ITU SWINTR. */
-        MOV.L # 000 872E0H, R5
-            MOV.B # 1, [ R5 ]
+        MOV.L # 000872E0H, R5
+        MOV.B # 1, [ R5 ]
         /* Read back to ensure the value is taken before proceeding. */
-        CMP[ R5 ].UB, R5
+        CMP [ R5 ].UB, R5
         /* Restore clobbered register to its previous value. */
         POP R5
-    #endif /* ifndef __CDT_PARSER__ */
-}
+    #endif
+    }
 
-#define portYIELD()                                       vPortYield()
-#define portYIELD_FROM_ISR( x )                           do { if( ( x ) != pdFALSE ) portYIELD( ); } while( 0 )
+    #define portYIELD()                                       vPortYield()
+    #define portYIELD_FROM_ISR( x )                           do { if( ( x ) != pdFALSE ) portYIELD(); } while( 0 )
 
 /* These macros should not be called directly, but through the
  * taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
@@ -138,32 +137,32 @@ static void vPortYield( void )
  * functions are those that end in FromISR.  FreeRTOS maintains a separate
  * interrupt API to ensure API function and interrupt entry is as fast and as
  * simple as possible. */
-#define portENABLE_INTERRUPTS()                           set_ipl( ( long ) 0 )
-#ifdef configASSERT
-    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    configASSERT( ( get_ipl() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
-    #define portDISABLE_INTERRUPTS()                      if( get_ipl() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
-#else
-    #define portDISABLE_INTERRUPTS()                      set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
-#endif
+    #define portENABLE_INTERRUPTS()                           set_ipl( ( long ) 0 )
+    #ifdef configASSERT
+        #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    configASSERT( ( get_ipl() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+        #define portDISABLE_INTERRUPTS()                      if( get_ipl() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+    #else
+        #define portDISABLE_INTERRUPTS()                      set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+    #endif
 
 /* Critical nesting counts are stored in the TCB. */
-#define portCRITICAL_NESTING_IN_TCB    ( 1 )
+    #define portCRITICAL_NESTING_IN_TCB    ( 1 )
 
 /* The critical nesting functions defined within tasks.c. */
-extern void vTaskEnterCritical( void );
-extern void vTaskExitCritical( void );
-#define portENTER_CRITICAL()                                           vTaskEnterCritical()
-#define portEXIT_CRITICAL()                                            vTaskExitCritical()
+    extern void vTaskEnterCritical( void );
+    extern void vTaskExitCritical( void );
+    #define portENTER_CRITICAL()    vTaskEnterCritical()
+    #define portEXIT_CRITICAL()     vTaskExitCritical()
 
 /* As this port allows interrupt nesting... */
-#define portSET_INTERRUPT_MASK_FROM_ISR()                              ( UBaseType_t ) get_ipl(); set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus )    set_ipl( ( long ) uxSavedInterruptStatus )
+    #define portSET_INTERRUPT_MASK_FROM_ISR()                              ( UBaseType_t ) get_ipl(); set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus )    set_ipl( ( long ) uxSavedInterruptStatus )
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
 /*-----------------------------------------------------------*/
 
@@ -172,18 +171,17 @@ extern void vTaskExitCritical( void );
  * themselves a DPFPU context before using any DPFPU instructions.  If
  * configUSE_TASK_DPFPU_SUPPORT is set to 2 then all tasks will have a DPFPU context
  * by default. */
-#if ( configUSE_TASK_DPFPU_SUPPORT == 1 )
-    void vPortTaskUsesDPFPU( void );
-#else
-
+    #if( configUSE_TASK_DPFPU_SUPPORT == 1 )
+        void vPortTaskUsesDPFPU( void );
+    #else
 /* Each task has a DPFPU context already, so define this function away to
  * nothing to prevent it being called accidentally. */
-    #define vPortTaskUsesDPFPU()
-#endif
-#define portTASK_USES_DPFPU()             vPortTaskUsesDPFPU()
+        #define vPortTaskUsesDPFPU()
+    #endif
+    #define portTASK_USES_DPFPU() vPortTaskUsesDPFPU()
 
 /* Definition to allow compatibility with existing FreeRTOS Demo using flop.c. */
-#define portTASK_USES_FLOATING_POINT()    vPortTaskUsesDPFPU()
+    #define portTASK_USES_FLOATING_POINT() vPortTaskUsesDPFPU()
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus

From 6a4143249812fbcf9023bd653c4d7acbdeba34b8 Mon Sep 17 00:00:00 2001
From: Soren Ptak <ptaksoren@gmail.com>
Date: Tue, 28 Nov 2023 15:16:16 -0500
Subject: [PATCH 131/424] Upgrade msvc port to winsock2 (#895)

* Add the changes needed to the MSVC windows port to get it to build with winsock2.h
* Rely upon the WIN32_LEAN_AND_MEAN define to include winsock2.h
---
 portable/MSVC-MingW/portmacro.h | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/portable/MSVC-MingW/portmacro.h b/portable/MSVC-MingW/portmacro.h
index d15300772..48a8bf4b0 100644
--- a/portable/MSVC-MingW/portmacro.h
+++ b/portable/MSVC-MingW/portmacro.h
@@ -29,7 +29,15 @@
 #ifndef PORTMACRO_H
 #define PORTMACRO_H
 
+#ifdef WIN32_LEAN_AND_MEAN
+    #include <winsock2.h>
+#else
+    #include <winsock.h>
+#endif
+
 #include <windows.h>
+#include <timeapi.h>
+#include <mmsystem.h>
 #include <winbase.h>
 
 /******************************************************************************

From 6a9f5a244a75ddec0017a7dda55f0f5323c67723 Mon Sep 17 00:00:00 2001
From: Soren Ptak <ptaksoren@gmail.com>
Date: Wed, 29 Nov 2023 05:22:16 -0500
Subject: [PATCH 132/424] Add portMEMORY_BARRIER() to RX MCU ports (#864)

* Add portMEMORY_BARRIER() to RX MCU ports

* Remove the memory barrier from the SH2A_FPU portable directory

---------

Co-authored-by: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
---
 portable/GCC/RX100/portmacro.h             | 2 ++
 portable/GCC/RX200/portmacro.h             | 2 ++
 portable/GCC/RX600/portmacro.h             | 2 ++
 portable/GCC/RX600v2/portmacro.h           | 2 ++
 portable/GCC/RX700v3_DPFPU/portmacro.h     | 2 ++
 portable/Renesas/RX100/portmacro.h         | 7 +++++++
 portable/Renesas/RX200/portmacro.h         | 6 ++++++
 portable/Renesas/RX600/portmacro.h         | 7 +++++++
 portable/Renesas/RX600v2/portmacro.h       | 7 +++++++
 portable/Renesas/RX700v3_DPFPU/portmacro.h | 7 +++++++
 10 files changed, 44 insertions(+)

diff --git a/portable/GCC/RX100/portmacro.h b/portable/GCC/RX100/portmacro.h
index b32d2007b..01bc3621b 100644
--- a/portable/GCC/RX100/portmacro.h
+++ b/portable/GCC/RX100/portmacro.h
@@ -147,6 +147,8 @@ void vPortSetIPL( uint32_t ulNewIPL ) __attribute__( ( naked ) );
 #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
 #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
+#define portMEMORY_BARRIER()                                  __asm volatile ( "" ::: "memory" )
+
 /* *INDENT-OFF* */
 #ifdef __cplusplus
     }
diff --git a/portable/GCC/RX200/portmacro.h b/portable/GCC/RX200/portmacro.h
index 2f153f87c..aee4e4de3 100644
--- a/portable/GCC/RX200/portmacro.h
+++ b/portable/GCC/RX200/portmacro.h
@@ -141,6 +141,8 @@ void vPortSetIPL( uint32_t ulNewIPL ) __attribute__( ( naked ) );
 #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
 #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
+#define portMEMORY_BARRIER()                                  __asm volatile ( "" ::: "memory" )
+
 /* *INDENT-OFF* */
 #ifdef __cplusplus
     }
diff --git a/portable/GCC/RX600/portmacro.h b/portable/GCC/RX600/portmacro.h
index 7d1fdb6c7..d441eb784 100644
--- a/portable/GCC/RX600/portmacro.h
+++ b/portable/GCC/RX600/portmacro.h
@@ -141,6 +141,8 @@ void vPortSetIPL( uint32_t ulNewIPL ) __attribute__( ( naked ) );
 #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
 #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
+#define portMEMORY_BARRIER()                                  __asm volatile ( "" ::: "memory" )
+
 /* *INDENT-OFF* */
 #ifdef __cplusplus
     }
diff --git a/portable/GCC/RX600v2/portmacro.h b/portable/GCC/RX600v2/portmacro.h
index 7d1fdb6c7..d441eb784 100644
--- a/portable/GCC/RX600v2/portmacro.h
+++ b/portable/GCC/RX600v2/portmacro.h
@@ -141,6 +141,8 @@ void vPortSetIPL( uint32_t ulNewIPL ) __attribute__( ( naked ) );
 #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
 #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
+#define portMEMORY_BARRIER()                                  __asm volatile ( "" ::: "memory" )
+
 /* *INDENT-OFF* */
 #ifdef __cplusplus
     }
diff --git a/portable/GCC/RX700v3_DPFPU/portmacro.h b/portable/GCC/RX700v3_DPFPU/portmacro.h
index 8e67724e9..4f9b8a087 100644
--- a/portable/GCC/RX700v3_DPFPU/portmacro.h
+++ b/portable/GCC/RX700v3_DPFPU/portmacro.h
@@ -185,6 +185,8 @@ void vPortSetIPL( uint32_t ulNewIPL ) __attribute__( ( naked ) );
 /* Definition to allow compatibility with existing FreeRTOS Demo using flop.c. */
 #define portTASK_USES_FLOATING_POINT()    vPortTaskUsesDPFPU()
 
+#define portMEMORY_BARRIER()              __asm volatile ( "" ::: "memory" )
+
 /* *INDENT-OFF* */
 #ifdef __cplusplus
     }
diff --git a/portable/Renesas/RX100/portmacro.h b/portable/Renesas/RX100/portmacro.h
index b82fdca24..a954bb71c 100644
--- a/portable/Renesas/RX100/portmacro.h
+++ b/portable/Renesas/RX100/portmacro.h
@@ -148,6 +148,13 @@ extern void vTaskExitCritical( void );
 #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
 #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
 
+#pragma inline_asm vPortMemoryBarrier
+static void vPortMemoryBarrier( void )
+{
+}
+
+#define portMEMORY_BARRIER()    vPortMemoryBarrier()
+
 /* *INDENT-OFF* */
 #ifdef __cplusplus
     }
diff --git a/portable/Renesas/RX200/portmacro.h b/portable/Renesas/RX200/portmacro.h
index 55278dacb..efb9d93c8 100644
--- a/portable/Renesas/RX200/portmacro.h
+++ b/portable/Renesas/RX200/portmacro.h
@@ -138,6 +138,12 @@ extern void vTaskExitCritical( void );
 #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
 #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
 
+#pragma inline_asm vPortMemoryBarrier
+static void vPortMemoryBarrier( void )
+{
+}
+
+#define portMEMORY_BARRIER()    vPortMemoryBarrier()
 /* *INDENT-OFF* */
 #ifdef __cplusplus
     }
diff --git a/portable/Renesas/RX600/portmacro.h b/portable/Renesas/RX600/portmacro.h
index 60106ae13..5ba1c067b 100644
--- a/portable/Renesas/RX600/portmacro.h
+++ b/portable/Renesas/RX600/portmacro.h
@@ -139,6 +139,13 @@ extern void vTaskExitCritical( void );
 #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
 #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
 
+#pragma inline_asm vPortMemoryBarrier
+static void vPortMemoryBarrier( void )
+{
+}
+
+#define portMEMORY_BARRIER()    vPortMemoryBarrier()
+
 /* *INDENT-OFF* */
 #ifdef __cplusplus
     }
diff --git a/portable/Renesas/RX600v2/portmacro.h b/portable/Renesas/RX600v2/portmacro.h
index 6efba647d..630a34eee 100644
--- a/portable/Renesas/RX600v2/portmacro.h
+++ b/portable/Renesas/RX600v2/portmacro.h
@@ -139,6 +139,13 @@ extern void vTaskExitCritical( void );
 #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
 #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
 
+#pragma inline_asm vPortMemoryBarrier
+static void vPortMemoryBarrier( void )
+{
+}
+
+#define portMEMORY_BARRIER()    vPortMemoryBarrier()
+
 /* *INDENT-OFF* */
 #ifdef __cplusplus
     }
diff --git a/portable/Renesas/RX700v3_DPFPU/portmacro.h b/portable/Renesas/RX700v3_DPFPU/portmacro.h
index fef13556e..891024a22 100644
--- a/portable/Renesas/RX700v3_DPFPU/portmacro.h
+++ b/portable/Renesas/RX700v3_DPFPU/portmacro.h
@@ -183,6 +183,13 @@
 /* Definition to allow compatibility with existing FreeRTOS Demo using flop.c. */
     #define portTASK_USES_FLOATING_POINT() vPortTaskUsesDPFPU()
 
+#pragma inline_asm vPortMemoryBarrier
+static void vPortMemoryBarrier( void )
+{
+}
+
+#define portMEMORY_BARRIER()    vPortMemoryBarrier()
+
 /* *INDENT-OFF* */
 #ifdef __cplusplus
     }

From 592bfe0e015ded4acf431482c646821a9efe6d62 Mon Sep 17 00:00:00 2001
From: Legend <me@liux.pro>
Date: Wed, 29 Nov 2023 23:32:30 +0800
Subject: [PATCH 133/424] Fix typo in comment (#910)

Co-authored-by: Tony Josi <tonyjosi@amazon.com>
Co-authored-by: Soren Ptak <ptaksoren@gmail.com>
Co-authored-by: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Co-authored-by: Nikhil Kamath <110539926+amazonKamath@users.noreply.github.com>
---
 portable/MemMang/heap_5.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/portable/MemMang/heap_5.c b/portable/MemMang/heap_5.c
index 127b28f5e..18234626a 100644
--- a/portable/MemMang/heap_5.c
+++ b/portable/MemMang/heap_5.c
@@ -214,7 +214,7 @@ void * pvPortMalloc( size_t xWantedSize )
     size_t xAdditionalRequiredSize;
 
     /* The heap must be initialised before the first call to
-     * prvPortMalloc(). */
+     * pvPortMalloc(). */
     configASSERT( pxEnd );
 
     if( xWantedSize > 0 )

From f8ef5f605b28c00b5251e8cf7c45b8ac1a54ef86 Mon Sep 17 00:00:00 2001
From: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Date: Thu, 30 Nov 2023 05:47:56 +0530
Subject: [PATCH 134/424] Fix prototype of MPU_vTimerSetReloadMode (#913)

---
 portable/Common/mpu_wrappers.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/portable/Common/mpu_wrappers.c b/portable/Common/mpu_wrappers.c
index 487f8aaf7..969bf2d3e 100644
--- a/portable/Common/mpu_wrappers.c
+++ b/portable/Common/mpu_wrappers.c
@@ -1797,7 +1797,7 @@
 
     #if ( configUSE_TIMERS == 1 )
         void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                                      const UBaseType_t uxAutoReload ) /* FREERTOS_SYSTEM_CALL */
+                                      const BaseType_t uxAutoReload ) /* FREERTOS_SYSTEM_CALL */
         {
             if( portIS_PRIVILEGED() == pdFALSE )
             {

From c0ce725293bb8cf9b30626a8bba173af33163533 Mon Sep 17 00:00:00 2001
From: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Date: Mon, 4 Dec 2023 10:49:41 +0800
Subject: [PATCH 135/424] Add SMP template port and example (#900)

* Add SMP template port and example
* Add readme file for smp configuration
* Update SMP build flow and add CI build

---------

Co-authored-by: Soren Ptak <ptaksoren@gmail.com>
Co-authored-by: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
---
 .github/workflows/kernel-demos.yml            |  7 ++
 examples/cmake_example/CMakeLists.txt         | 17 +++-
 .../sample_configuration/smp/FreeRTOSConfig.h | 65 ++++++++++++++++
 examples/sample_configuration/smp/readme.md   | 10 +++
 portable/template/port.c                      | 42 ++++++++--
 portable/template/portmacro.h                 | 77 +++++++++++++++----
 6 files changed, 194 insertions(+), 24 deletions(-)
 create mode 100644 examples/sample_configuration/smp/FreeRTOSConfig.h
 create mode 100644 examples/sample_configuration/smp/readme.md

diff --git a/.github/workflows/kernel-demos.yml b/.github/workflows/kernel-demos.yml
index 7d83d7482..bae32c966 100644
--- a/.github/workflows/kernel-demos.yml
+++ b/.github/workflows/kernel-demos.yml
@@ -111,6 +111,13 @@ jobs:
           cmake -S . -B build
           cmake --build build
 
+      - name: Build CMake SMP Example Demo
+        shell: bash
+        working-directory: examples/cmake_example
+        run: |
+          cmake -S . -B build -DFREERTOS_SMP_EXAMPLE=1
+          cmake --build build
+
   MSP430-GCC:
     name: GNU MSP430 Toolchain
     runs-on: ubuntu-latest
diff --git a/examples/cmake_example/CMakeLists.txt b/examples/cmake_example/CMakeLists.txt
index 85329678d..f8a4e2d63 100644
--- a/examples/cmake_example/CMakeLists.txt
+++ b/examples/cmake_example/CMakeLists.txt
@@ -7,10 +7,19 @@ set(FREERTOS_KERNEL_PATH "../../")
 # Add the freertos_config for FreeRTOS-Kernel
 add_library(freertos_config INTERFACE)
 
-target_include_directories(freertos_config
-    INTERFACE
-    ../sample_configuration
-)
+if (DEFINED FREERTOS_SMP_EXAMPLE AND FREERTOS_SMP_EXAMPLE STREQUAL "1")
+    message(STATUS "Build FreeRTOS SMP example")
+    target_include_directories(freertos_config
+        INTERFACE
+        "../sample_configuration/smp"
+    )
+else()
+    message(STATUS "Build FreeRTOS example")
+    target_include_directories(freertos_config
+        INTERFACE
+        "../sample_configuration"
+    )
+endif()
 
 # Select the heap port.  values between 1-4 will pick a heap.
 set(FREERTOS_HEAP "4" CACHE STRING "" FORCE)
diff --git a/examples/sample_configuration/smp/FreeRTOSConfig.h b/examples/sample_configuration/smp/FreeRTOSConfig.h
new file mode 100644
index 000000000..f3b68a444
--- /dev/null
+++ b/examples/sample_configuration/smp/FreeRTOSConfig.h
@@ -0,0 +1,65 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*******************************************************************************
+ * This file provides an example FreeRTOSConfig.h header file, inclusive of an
+ * abbreviated explanation of each configuration item.  Online and reference
+ * documentation provides more information.
+ * https://www.freertos.org/a00110.html
+ *
+ * Constant values enclosed in square brackets ('[' and ']') must be completed
+ * before this file will build.
+ *
+ * Use the FreeRTOSConfig.h supplied with the RTOS port in use rather than this
+ * generic file, if one is available.
+ ******************************************************************************/
+
+#ifndef __FREERTOS_CONFIG_SMP_H__
+#define __FREERTOS_CONFIG_SMP_H__
+
+#include "../FreeRTOSConfig.h"
+
+/******************************************************************************/
+/* Scheduling behaviour related definitions. **********************************/
+/******************************************************************************/
+
+/* Set configNUMBER_OF_CORES to greater than 1 to enable running one instance of
+ * FreeRTOS kernel to schedule tasks across multiple identical processor cores. */
+#define configNUMBER_OF_CORES    2
+
+/******************************************************************************/
+/* Hook and callback function related definitions. ****************************/
+/******************************************************************************/
+
+/* Set the following configUSE_* constants to 1 to include the named hook
+ * functionality in the build.  Set to 0 to exclude the hook functionality from the
+ * build.  The application writer is responsible for providing the hook function
+ * for any set to 1.  See https://www.freertos.org/a00016.html */
+#define configUSE_PASSIVE_IDLE_HOOK    0
+
+#endif /* __FREERTOS_CONFIG_SMP_H__ */
diff --git a/examples/sample_configuration/smp/readme.md b/examples/sample_configuration/smp/readme.md
new file mode 100644
index 000000000..8dc02bd56
--- /dev/null
+++ b/examples/sample_configuration/smp/readme.md
@@ -0,0 +1,10 @@
+# Configuration support for FreeRTOS SMP
+
+## Overview
+The FreeRTOSConfig.h provided in this folder is a sample configuration that will
+assist you in preparing the configuration to enable SMP support in the FreeRTOS
+Kernel for your application.
+
+Based on single core sample configuration file, this configuration file is created
+with minimal configuration change. More SMP scheduler configurations can be found
+in [Symmetric Multiprocessing (SMP) with FreeRTOS](https://freertos.org/symmetric-multiprocessing-introduction.html)
diff --git a/portable/template/port.c b/portable/template/port.c
index 4011eac15..d4eb56eac 100644
--- a/portable/template/port.c
+++ b/portable/template/port.c
@@ -25,8 +25,18 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
 void vPortYield( void )
 {
     /* Save the current Context */
+
     /* Switch to the highest priority task that is ready to run. */
-    vTaskSwitchContext();
+    #if ( configNUMBER_OF_CORES == 1 )
+    {
+        vTaskSwitchContext();
+    }
+    #else
+    {
+        vTaskSwitchContext( portGET_CORE_ID() );
+    }
+    #endif
+
     /* Start executing the task we have just switched to. */
 }
 
@@ -35,12 +45,34 @@ static void prvTickISR( void )
     /* Interrupts must have been enabled for the ISR to fire, so we have to
      * save the context with interrupts enabled. */
 
-    /* Maintain the tick count. */
-    if( xTaskIncrementTick() != pdFALSE )
+    #if ( configNUMBER_OF_CORES == 1 )
     {
-        /* Switch to the highest priority task that is ready to run. */
-        vTaskSwitchContext();
+        /* Maintain the tick count. */
+        if( xTaskIncrementTick() != pdFALSE )
+        {
+            /* Switch to the highest priority task that is ready to run. */
+            vTaskSwitchContext();
+        }
     }
+    #else
+    {
+        UBaseType_t ulPreviousMask;
+
+        /* Tasks or ISRs running on other cores may still in critical section in
+         * multiple cores environment. Incrementing tick needs to performed in
+         * critical section. */
+        ulPreviousMask = taskENTER_CRITICAL_FROM_ISR();
+
+        /* Maintain the tick count. */
+        if( xTaskIncrementTick() != pdFALSE )
+        {
+            /* Switch to the highest priority task that is ready to run. */
+            vTaskSwitchContext( portGET_CORE_ID() );
+        }
+
+        taskEXIT_CRITICAL_FROM_ISR( ulPreviousMask );
+    }
+    #endif /* if ( configNUMBER_OF_CORES == 1 ) */
 
     /* start executing the new task */
 }
diff --git a/portable/template/portmacro.h b/portable/template/portmacro.h
index 4e4aa934d..199053208 100644
--- a/portable/template/portmacro.h
+++ b/portable/template/portmacro.h
@@ -64,26 +64,42 @@ typedef unsigned char    UBaseType_t;
 /*-----------------------------------------------------------*/
 
     #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) \
-    {                                                                    \
+    do {                                                                 \
         uxTopPriority = 0;                                               \
-    }                                                                    \
-    while( 0 )
+    } while( 0 )
 
 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 
-#define portDISABLE_INTERRUPTS()   \
-    { /* Disable the interrupts */ \
-    }
-#define portENABLE_INTERRUPTS()   \
-    { /* Enable the interrupts */ \
-    }
+/* Disable the interrupts */
+#define portDISABLE_INTERRUPTS()    do {} while( 0 )
 
-#define portENTER_CRITICAL()                                             \
-    { /* preserve current interrupt state and then disable interrupts */ \
-    }
-#define portEXIT_CRITICAL()                              \
-    { /* restore previously preserved interrupt state */ \
-    }
+/* Enable the interrupts */
+#define portENABLE_INTERRUPTS()     do {} while( 0 )
+
+#if ( configNUMBER_OF_CORES == 1 )
+/* preserve current interrupt state and then disable interrupts */
+    #define portENTER_CRITICAL()    do {} while( 0 )
+
+/* restore previously preserved interrupt state */
+    #define portEXIT_CRITICAL()     do {} while( 0 )
+#else
+
+/* The port can maintain the critical nesting count in TCB or maintain the critical
+ * nesting count in the port. */
+    #define portCRITICAL_NESTING_IN_TCB    1
+
+/* vTaskEnterCritical and vTaskExitCritical should be used in the implementation
+ * of portENTER/EXIT_CRITICAL if the number of cores is more than 1 in the system. */
+    #define portENTER_CRITICAL             vTaskEnterCritical
+    #define portEXIT_CRITICAL              vTaskExitCritical
+
+/* vTaskEnterCriticalFromISR and vTaskExitCriticalFromISR should be used in the
+ * implementation of portENTER/EXIT_CRITICAL_FROM_ISR if the number of cores is
+ * more than 1 in the system. */
+    #define portENTER_CRITICAL_FROM_ISR    vTaskEnterCriticalFromISR
+    #define portEXIT_CRITICAL_FROM_ISR     vTaskExitCriticalFromISR
+
+#endif /* if ( configNUMBER_OF_CORES == 1 ) */
 
 extern void vPortYield( void );
 #define portYIELD()                                           vPortYield()
@@ -92,4 +108,35 @@ extern void vPortYield( void );
 #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
 #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
+#if ( configNUMBER_OF_CORES > 1 )
+    /* Return the core ID on which the code is running. */
+    #define portGET_CORE_ID()                0
+
+/* Set the interrupt mask. */
+    #define portSET_INTERRUPT_MASK()         0
+
+/* Clear the interrupt mask. */
+    #define portCLEAR_INTERRUPT_MASK( x )    ( ( void ) ( x ) )
+
+/* Request the core ID x to yield. */
+    #define portYIELD_CORE( x )              do {} while( 0 )
+
+/* Acquire the TASK lock. TASK lock is a recursive lock.
+ * It should be able to be locked by the same core multiple times. */
+    #define portGET_TASK_LOCK()              do {} while( 0 )
+
+/* Release the TASK lock. If a TASK lock is locked by the same core multiple times,
+ * it should be released as many times as it is locked. */
+    #define portRELEASE_TASK_LOCK()          do {} while( 0 )
+
+/* Acquire the ISR lock. ISR lock is a recursive lock.
+ * It should be able to be locked by the same core multiple times. */
+    #define portGET_ISR_LOCK()               do {} while( 0 )
+
+/* Release the ISR lock. If a ISR lock is locked by the same core multiple times, \
+ * it should be released as many times as it is locked. */
+    #define portRELEASE_ISR_LOCK()           do {} while( 0 )
+
+#endif /* if ( configNUMBER_OF_CORES > 1 ) */
+
 #endif /* PORTMACRO_H */

From cd5c774b2bda6eeec55862f79e164843508e96d9 Mon Sep 17 00:00:00 2001
From: Darian <32921628+Dazza0@users.noreply.github.com>
Date: Tue, 5 Dec 2023 14:31:11 +0800
Subject: [PATCH 136/424] Update xTaskGetIdleTaskHandle() For SMP (#868)

* Update xTaskGetIdleTaskHandle() in SMP

This commit updates xTaskGetIdleTaskHandle() for SMP in the following ways:

- xTaskGetIdleTaskHandle() no longer accepts xCoreID argument in SMP so that
there is not change in API between single-core and SMP
- xTaskGetIdleTaskHandle() now returns the Active idle task handle in SMP,
which matches the behavior in single-core.
- Added xTaskGetIdleTaskHandleForCore() in SMP which accepts an xCoreID
argument. This function can be used to obtain the Passive idle task handles.

* Update xTaskGetIdleTaskHandle

---------

Co-authored-by: Ching-Hsin Lee <chinglee@amazon.com>
Co-authored-by: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Co-authored-by: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
---
 include/FreeRTOS.h | 16 +++++++++++-----
 include/task.h     | 17 ++++++++---------
 tasks.c            | 36 ++++++++++++++++--------------------
 3 files changed, 35 insertions(+), 34 deletions(-)

diff --git a/include/FreeRTOS.h b/include/FreeRTOS.h
index b8153ac64..06c50adf3 100644
--- a/include/FreeRTOS.h
+++ b/include/FreeRTOS.h
@@ -1886,14 +1886,20 @@
     #ifndef traceENTER_xTaskGetIdleTaskHandle
         #define traceENTER_xTaskGetIdleTaskHandle()
     #endif
-#else
-    #ifndef traceENTER_xTaskGetIdleTaskHandle
-        #define traceENTER_xTaskGetIdleTaskHandle( xCoreID )
+#endif
+
+#if ( configNUMBER_OF_CORES == 1 )
+    #ifndef traceRETURN_xTaskGetIdleTaskHandle
+        #define traceRETURN_xTaskGetIdleTaskHandle( xIdleTaskHandle )
     #endif
 #endif
 
-#ifndef traceRETURN_xTaskGetIdleTaskHandle
-    #define traceRETURN_xTaskGetIdleTaskHandle( xIdleTaskHandle )
+#ifndef traceENTER_xTaskGetIdleTaskHandleForCore
+    #define traceENTER_xTaskGetIdleTaskHandleForCore( xCoreID )
+#endif
+
+#ifndef traceRETURN_xTaskGetIdleTaskHandleForCore
+    #define traceRETURN_xTaskGetIdleTaskHandleForCore( xIdleTaskHandle )
 #endif
 
 #ifndef traceENTER_vTaskStepTick
diff --git a/include/task.h b/include/task.h
index 9ff199287..cb06c2370 100644
--- a/include/task.h
+++ b/include/task.h
@@ -2030,24 +2030,23 @@ BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask,
  * xTaskGetIdleTaskHandle() is only available if
  * INCLUDE_xTaskGetIdleTaskHandle is set to 1 in FreeRTOSConfig.h.
  *
- * Simply returns the handle of the idle task.  It is not valid to call
- * xTaskGetIdleTaskHandle() before the scheduler has been started.
+ * In single-core FreeRTOS, this function simply returns the handle of the idle
+ * task. It is not valid to call xTaskGetIdleTaskHandle() before the scheduler
+ * has been started.
  *
  * In the FreeRTOS SMP, there are a total of configNUMBER_OF_CORES idle tasks:
  *  1. 1 Active idle task which does all the housekeeping.
  *  2. ( configNUMBER_OF_CORES - 1 ) Passive idle tasks which do nothing.
  * These idle tasks are created to ensure that each core has an idle task to run when
- * no other task is available to run.
- *
- * Set xCoreID to 0 to get the Active idle task handle. Set xCoreID to
- * 1,2 ... ( configNUMBER_OF_CORES - 1 ) to get the Passive idle task
- * handles.
+ * no other task is available to run. Call xTaskGetIdleTaskHandle() or
+ * xTaskGetIdleTaskHandleForCore() with xCoreID set to 0  to get the Active
+ * idle task handle. Call xTaskGetIdleTaskHandleForCore() with xCoreID set to
+ * 1,2 ... ( configNUMBER_OF_CORES - 1 ) to get the Passive idle task handles.
  */
 #if ( configNUMBER_OF_CORES == 1 )
     TaskHandle_t xTaskGetIdleTaskHandle( void ) PRIVILEGED_FUNCTION;
-#else /* #if ( configNUMBER_OF_CORES == 1 ) */
-    TaskHandle_t xTaskGetIdleTaskHandle( BaseType_t xCoreID ) PRIVILEGED_FUNCTION;
 #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
+TaskHandle_t xTaskGetIdleTaskHandleForCore( BaseType_t xCoreID ) PRIVILEGED_FUNCTION;
 
 /**
  * configUSE_TRACE_FACILITY must be defined as 1 in FreeRTOSConfig.h for
diff --git a/tasks.c b/tasks.c
index 4a6c78a8c..a26f8b500 100644
--- a/tasks.c
+++ b/tasks.c
@@ -4472,7 +4472,6 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char
 #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
 
     #if ( configNUMBER_OF_CORES == 1 )
-
         TaskHandle_t xTaskGetIdleTaskHandle( void )
         {
             traceENTER_xTaskGetIdleTaskHandle();
@@ -4485,27 +4484,24 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char
 
             return xIdleTaskHandles[ 0 ];
         }
-
-    #else /* if ( configNUMBER_OF_CORES == 1 ) */
-
-        TaskHandle_t xTaskGetIdleTaskHandle( BaseType_t xCoreID )
-        {
-            traceENTER_xTaskGetIdleTaskHandle( xCoreID );
-
-            /* Ensure the core ID is valid. */
-            configASSERT( taskVALID_CORE_ID( xCoreID ) == pdTRUE );
-
-            /* If xTaskGetIdleTaskHandle() is called before the scheduler has been
-             * started, then xIdleTaskHandles will be NULL. */
-            configASSERT( ( xIdleTaskHandles[ xCoreID ] != NULL ) );
-
-            traceRETURN_xTaskGetIdleTaskHandle( xIdleTaskHandles[ xCoreID ] );
-
-            return xIdleTaskHandles[ xCoreID ];
-        }
-
     #endif /* if ( configNUMBER_OF_CORES == 1 ) */
 
+    TaskHandle_t xTaskGetIdleTaskHandleForCore( BaseType_t xCoreID )
+    {
+        traceENTER_xTaskGetIdleTaskHandleForCore( xCoreID );
+
+        /* Ensure the core ID is valid. */
+        configASSERT( taskVALID_CORE_ID( xCoreID ) == pdTRUE );
+
+        /* If xTaskGetIdleTaskHandle() is called before the scheduler has been
+         * started, then xIdleTaskHandles will be NULL. */
+        configASSERT( ( xIdleTaskHandles[ xCoreID ] != NULL ) );
+
+        traceRETURN_xTaskGetIdleTaskHandleForCore( xIdleTaskHandles[ xCoreID ] );
+
+        return xIdleTaskHandles[ xCoreID ];
+    }
+
 #endif /* INCLUDE_xTaskGetIdleTaskHandle */
 /*----------------------------------------------------------*/
 

From 84c0047ccd8bfa1936eace051be9f72f950372ab Mon Sep 17 00:00:00 2001
From: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Date: Wed, 6 Dec 2023 09:51:52 +0800
Subject: [PATCH 137/424] Suppress MISRA C:2012 rule 11.5 deviations (#878)

* Suppress MISRA C:2012 rule 11.5 deviations by comment also remove this rule in global config

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Ubuntu <ubuntu@ip-172-31-34-245.ap-northeast-1.compute.internal>
Co-authored-by: Rahul Kar <karahulx@amazon.com>
Co-authored-by: Soren Ptak <ptaksoren@gmail.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 MISRA.md        | 84 ++++++++++++++++++++++++++++++--------------
 croutine.c      |  3 ++
 event_groups.c  | 39 +++++++++++----------
 queue.c         | 14 +++-----
 stream_buffer.c | 25 +++++++++++---
 tasks.c         | 92 ++++++++++++++++++++++++++++++++++++++++---------
 timers.c        | 10 ++++--
 7 files changed, 191 insertions(+), 76 deletions(-)

diff --git a/MISRA.md b/MISRA.md
index b6a5ee197..33e966817 100644
--- a/MISRA.md
+++ b/MISRA.md
@@ -20,34 +20,72 @@ grep 'MISRA Ref 8.4.1' . -rI
 
 #### Rule 8.4
 
+MISRA C:2012 Rule 8.4: A compatible declaration shall be visible when an
+        object or function with external linkage is defined.
+
 _Ref 8.4.1_
 
-- MISRA C:2012 Rule 8.4: A compatible declaration shall be visible when an
-        object or function with external linkage is defined.
-        This rule requires that a compatible declaration is made available
-        in a header file when an object with external linkage is defined.
-        pxCurrentTCB(s) is defined with external linkage but it is only
-        referenced from the assembly code in the port files. Therefore, adding
-        a declaration in header file is not useful as the assembly code will
-        still need to declare it separately.
+- This rule requires that a compatible declaration is made available
+  in a header file when an object with external linkage is defined.
+  pxCurrentTCB(s) is defined with external linkage but it is only
+  referenced from the assembly code in the port files. Therefore, adding
+  a declaration in header file is not useful as the assembly code will
+  still need to declare it separately.
 
 
 #### Rule 11.3
 
-_Ref 11.3.1_
+MISRA C:2012 Rule 11.3: A cast shall not be performed between a pointer to
+object type and a pointer to a different object type.
 
-- MISRA C:2012 Rule 11.3: A cast shall not be performed between a pointer to
-        object type and a pointer to a different object type.
-        This rule prohibits casting a pointer to object into a pointer to a
-        different object because it may result in an incorrectly aligned pointer,
-        leading to undefined behavior. Even if the casting produces a correctly
-        aligned pointer, the behavior may be still undefined if the pointer is
-        used to access an object. FreeRTOS deliberately creates external aliases
-        for all the kernel object types (StaticEventGroup_t, StaticQueue_t,
-        StaticStreamBuffer_t, StaticTimer_t and StaticTask_t) for data hiding
-        purposes. The internal object types and the corresponding external
-        aliases are guaranteed to have the same size and alignment which is
-        checked using configASSERT.
+_Ref 11.3.1_
+ - This rule prohibits casting a pointer to object into a pointer to a
+   different object because it may result in an incorrectly aligned pointer,
+   leading to undefined behavior. Even if the casting produces a correctly
+   aligned pointer, the behavior may be still undefined if the pointer is
+   used to access an object. FreeRTOS deliberately creates external aliases
+   for all the kernel object types (StaticEventGroup_t, StaticQueue_t,
+   StaticStreamBuffer_t, StaticTimer_t and StaticTask_t) for data hiding
+   purposes. The internal object types and the corresponding external
+   aliases are guaranteed to have the same size and alignment which is
+   checked using configASSERT.
+
+
+#### Rule 11.5
+
+MISRA C:2012 Rule 11.5: A conversion should not be performed from pointer to
+void into pointer to object.
+This rule prohibits conversion of a pointer to void into a pointer to
+object because it may result in an incorrectly aligned pointer leading
+to undefined behavior.
+
+_Ref 11.5.1_
+ - The memory blocks returned by pvPortMalloc() are guaranteed to meet the
+   architecture alignment requirements specified by portBYTE_ALIGNMENT.
+   The casting of the pointer to void returned by pvPortMalloc() is,
+   therefore, safe because it is guaranteed to be aligned.
+
+_Ref 11.5.2_
+ - The conversion from a pointer to void into a pointer to EventGroup_t is
+   safe because it is a pointer to EventGroup_t, which is returned to the
+   application at the time of event group creation for data hiding
+   purposes.
+
+_Ref 11.5.3_
+ - The conversion from a pointer to void in list macros for list item owner
+   is safe because the type of the pointer stored and retrieved is the
+   same.
+
+_Ref 11.5.4_
+ - The conversion from a pointer to void into a pointer to EventGroup_t is
+   safe because it is a pointer to EventGroup_t, which is passed as a
+   parameter to the xTimerPendFunctionCallFromISR API when the callback is
+   pended.
+
+_Ref 11.5.5_
+ - The conversion from a pointer to void into a pointer to uint8_t is safe
+   because data storage buffers are implemented as uint8_t arrays for the
+   ease of sizing, alignment and access.
 
 
 ### MISRA configuration
@@ -81,10 +119,6 @@ Copy below content to `misra.conf` to run Coverity on FreeRTOS-Kernel.
         {
             deviation: "Rule 8.7",
             reason: "API functions are not used by the library outside of the files they are defined; however, they must be externally visible in order to be used by an application."
-        },
-        {
-            deviation: "Rule 11.5",
-            reason: "Allow casts from `void *`. List owner, pvOwner, is stored as `void *` and are cast to various types for use in functions."
         }
     ]
 }
diff --git a/croutine.c b/croutine.c
index f7d8ab95d..daa88275f 100644
--- a/croutine.c
+++ b/croutine.c
@@ -110,6 +110,9 @@
         traceENTER_xCoRoutineCreate( pxCoRoutineCode, uxPriority, uxIndex );
 
         /* Allocate the memory that will store the co-routine control block. */
+        /* MISRA Ref 11.5.1 [Malloc memory assignment] */
+        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+        /* coverity[misra_c_2012_rule_11_5_violation] */
         pxCoRoutine = ( CRCB_t * ) pvPortMalloc( sizeof( CRCB_t ) );
 
         if( pxCoRoutine )
diff --git a/event_groups.c b/event_groups.c
index e6fc7e68c..68f8e9ddb 100644
--- a/event_groups.c
+++ b/event_groups.c
@@ -143,20 +143,10 @@ static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits,
 
         traceENTER_xEventGroupCreate();
 
-        /* Allocate the event group.  Justification for MISRA deviation as
-         * follows:  pvPortMalloc() always ensures returned memory blocks are
-         * aligned per the requirements of the MCU stack.  In this case
-         * pvPortMalloc() must return a pointer that is guaranteed to meet the
-         * alignment requirements of the EventGroup_t structure - which (if you
-         * follow it through) is the alignment requirements of the TickType_t type
-         * (EventBits_t being of TickType_t itself).  Therefore, whenever the
-         * stack alignment requirements are greater than or equal to the
-         * TickType_t alignment requirements the cast is safe.  In other cases,
-         * where the natural word size of the architecture is less than
-         * sizeof( TickType_t ), the TickType_t variables will be accessed in two
-         * or more reads operations, and the alignment requirements is only that
-         * of each individual read. */
-        pxEventBits = ( EventGroup_t * ) pvPortMalloc( sizeof( EventGroup_t ) ); /*lint !e9087 !e9079 see comment above. */
+        /* MISRA Ref 11.5.1 [Malloc memory assignment] */
+        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+        /* coverity[misra_c_2012_rule_11_5_violation] */
+        pxEventBits = ( EventGroup_t * ) pvPortMalloc( sizeof( EventGroup_t ) );
 
         if( pxEventBits != NULL )
         {
@@ -749,7 +739,10 @@ void vEventGroupSetBitsCallback( void * pvEventGroup,
 {
     traceENTER_vEventGroupSetBitsCallback( pvEventGroup, ulBitsToSet );
 
-    ( void ) xEventGroupSetBits( pvEventGroup, ( EventBits_t ) ulBitsToSet ); /*lint !e9079 Can't avoid cast to void* as a generic timer callback prototype. Callback casts back to original type so safe. */
+    /* MISRA Ref 11.5.4 [Callback function parameter] */
+    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+    /* coverity[misra_c_2012_rule_11_5_violation] */
+    ( void ) xEventGroupSetBits( pvEventGroup, ( EventBits_t ) ulBitsToSet );
 
     traceRETURN_vEventGroupSetBitsCallback();
 }
@@ -762,7 +755,10 @@ void vEventGroupClearBitsCallback( void * pvEventGroup,
 {
     traceENTER_vEventGroupClearBitsCallback( pvEventGroup, ulBitsToClear );
 
-    ( void ) xEventGroupClearBits( pvEventGroup, ( EventBits_t ) ulBitsToClear ); /*lint !e9079 Can't avoid cast to void* as a generic timer callback prototype. Callback casts back to original type so safe. */
+    /* MISRA Ref 11.5.4 [Callback function parameter] */
+    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+    /* coverity[misra_c_2012_rule_11_5_violation] */
+    ( void ) xEventGroupClearBits( pvEventGroup, ( EventBits_t ) ulBitsToClear );
 
     traceRETURN_vEventGroupClearBitsCallback();
 }
@@ -831,7 +827,11 @@ static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits,
     UBaseType_t uxEventGroupGetNumber( void * xEventGroup )
     {
         UBaseType_t xReturn;
-        EventGroup_t const * pxEventBits = ( EventGroup_t * ) xEventGroup; /*lint !e9087 !e9079 EventGroupHandle_t is a pointer to an EventGroup_t, but EventGroupHandle_t is kept opaque outside of this file for data hiding purposes. */
+
+        /* MISRA Ref 11.5.2 [Opaque pointer] */
+        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+        /* coverity[misra_c_2012_rule_11_5_violation] */
+        EventGroup_t const * pxEventBits = ( EventGroup_t * ) xEventGroup;
 
         traceENTER_uxEventGroupGetNumber( xEventGroup );
 
@@ -859,7 +859,10 @@ static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits,
     {
         traceENTER_vEventGroupSetNumber( xEventGroup, uxEventGroupNumber );
 
-        ( ( EventGroup_t * ) xEventGroup )->uxEventGroupNumber = uxEventGroupNumber; /*lint !e9087 !e9079 EventGroupHandle_t is a pointer to an EventGroup_t, but EventGroupHandle_t is kept opaque outside of this file for data hiding purposes. */
+        /* MISRA Ref 11.5.2 [Opaque pointer] */
+        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+        /* coverity[misra_c_2012_rule_11_5_violation] */
+        ( ( EventGroup_t * ) xEventGroup )->uxEventGroupNumber = uxEventGroupNumber;
 
         traceRETURN_vEventGroupSetNumber();
     }
diff --git a/queue.c b/queue.c
index 00eed7351..1aabc9f31 100644
--- a/queue.c
+++ b/queue.c
@@ -517,16 +517,10 @@ BaseType_t xQueueGenericReset( QueueHandle_t xQueue,
              * zero in the case the queue is used as a semaphore. */
             xQueueSizeInBytes = ( size_t ) ( ( size_t ) uxQueueLength * ( size_t ) uxItemSize );
 
-            /* Allocate the queue and storage area.  Justification for MISRA
-             * deviation as follows:  pvPortMalloc() always ensures returned memory
-             * blocks are aligned per the requirements of the MCU stack.  In this case
-             * pvPortMalloc() must return a pointer that is guaranteed to meet the
-             * alignment requirements of the Queue_t structure - which in this case
-             * is an int8_t *.  Therefore, whenever the stack alignment requirements
-             * are greater than or equal to the pointer to char requirements the cast
-             * is safe.  In other cases alignment requirements are not strict (one or
-             * two bytes). */
-            pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); /*lint !e9087 !e9079 see comment above. */
+            /* MISRA Ref 11.5.1 [Malloc memory assignment] */
+            /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+            /* coverity[misra_c_2012_rule_11_5_violation] */
+            pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes );
 
             if( pxNewQueue != NULL )
             {
diff --git a/stream_buffer.c b/stream_buffer.c
index 47e82512f..d6a9ffffc 100644
--- a/stream_buffer.c
+++ b/stream_buffer.c
@@ -374,8 +374,14 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
 
         if( pvAllocatedMemory != NULL )
         {
-            prvInitialiseNewStreamBuffer( ( StreamBuffer_t * ) pvAllocatedMemory,                         /* Structure at the start of the allocated memory. */ /*lint !e9087 Safe cast as allocated memory is aligned. */ /*lint !e826 Area is not too small and alignment is guaranteed provided malloc() behaves as expected and returns aligned buffer. */
-                                          ( ( uint8_t * ) pvAllocatedMemory ) + sizeof( StreamBuffer_t ), /* Storage area follows. */ /*lint !e9016 Indexing past structure valid for uint8_t pointer, also storage area has no alignment requirement. */
+            /* MISRA Ref 11.5.1 [Malloc memory assignment] */
+            /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+            /* coverity[misra_c_2012_rule_11_5_violation] */
+            prvInitialiseNewStreamBuffer( ( StreamBuffer_t * ) pvAllocatedMemory,                         /* Structure at the start of the allocated memory. */
+                                                                                                          /* MISRA Ref 11.5.1 [Malloc memory assignment] */
+                                                                                                          /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+                                                                                                          /* coverity[misra_c_2012_rule_11_5_violation] */
+                                          ( ( uint8_t * ) pvAllocatedMemory ) + sizeof( StreamBuffer_t ), /* Storage area follows. */
                                           xBufferSizeBytes,
                                           xTriggerLevelBytes,
                                           ucFlags,
@@ -391,7 +397,10 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
 
         traceRETURN_xStreamBufferGenericCreate( pvAllocatedMemory );
 
-        return ( StreamBufferHandle_t ) pvAllocatedMemory; /*lint !e9087 !e826 Safe cast as allocated memory is aligned. */
+        /* MISRA Ref 11.5.1 [Malloc memory assignment] */
+        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+        /* coverity[misra_c_2012_rule_11_5_violation] */
+        return ( StreamBufferHandle_t ) pvAllocatedMemory;
     }
 #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
 /*-----------------------------------------------------------*/
@@ -940,7 +949,10 @@ static size_t prvWriteMessageToBuffer( StreamBuffer_t * const pxStreamBuffer,
     if( xDataLengthBytes != ( size_t ) 0 )
     {
         /* Write the data to the buffer. */
-        pxStreamBuffer->xHead = prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) pvTxData, xDataLengthBytes, xNextHead ); /*lint !e9079 Storage buffer is implemented as uint8_t for ease of sizing, alignment and access. */
+        /* MISRA Ref 11.5.5 [Void pointer assignment] */
+        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+        /* coverity[misra_c_2012_rule_11_5_violation] */
+        pxStreamBuffer->xHead = prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) pvTxData, xDataLengthBytes, xNextHead );
     }
 
     return xDataLengthBytes;
@@ -1204,7 +1216,10 @@ static size_t prvReadMessageFromBuffer( StreamBuffer_t * pxStreamBuffer,
     if( xCount != ( size_t ) 0 )
     {
         /* Read the actual data and update the tail to mark the data as officially consumed. */
-        pxStreamBuffer->xTail = prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) pvRxData, xCount, xNextTail ); /*lint !e9079 Data storage area is implemented as uint8_t array for ease of sizing, indexing and alignment. */
+        /* MISRA Ref 11.5.5 [Void pointer assignment] */
+        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+        /* coverity[misra_c_2012_rule_11_5_violation] */
+        pxStreamBuffer->xTail = prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) pvRxData, xCount, xNextTail );
     }
 
     return xCount;
diff --git a/tasks.c b/tasks.c
index a26f8b500..a9427539a 100644
--- a/tasks.c
+++ b/tasks.c
@@ -1035,6 +1035,9 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
 
                 for( pxIterator = listGET_HEAD_ENTRY( pxReadyList ); pxIterator != pxEndMarker; pxIterator = listGET_NEXT( pxIterator ) )
                 {
+                    /* MISRA Ref 11.5.3 [Void pointer assignment] */
+                    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+                    /* coverity[misra_c_2012_rule_11_5_violation] */
                     TCB_t * pxTCB = ( TCB_t * ) listGET_LIST_ITEM_OWNER( pxIterator );
 
                     #if ( configRUN_MULTIPLE_PRIORITIES == 0 )
@@ -1498,6 +1501,9 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
 
         if( pxTaskDefinition->puxStackBuffer != NULL )
         {
+            /* MISRA Ref 11.5.1 [Malloc memory assignment] */
+            /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+            /* coverity[misra_c_2012_rule_11_5_violation] */
             pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) );
 
             if( pxNewTCB != NULL )
@@ -1622,6 +1628,9 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
             /* Allocate space for the TCB.  Where the memory comes from depends on
              * the implementation of the port malloc function and whether or not static
              * allocation is being used. */
+            /* MISRA Ref 11.5.1 [Malloc memory assignment] */
+            /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+            /* coverity[misra_c_2012_rule_11_5_violation] */
             pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) );
 
             if( pxNewTCB != NULL )
@@ -1631,7 +1640,10 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
                 /* Allocate space for the stack used by the task being created.
                  * The base of the stack memory stored in the TCB so the task can
                  * be deleted later if required. */
-                pxNewTCB->pxStack = ( StackType_t * ) pvPortMallocStack( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+                /* MISRA Ref 11.5.1 [Malloc memory assignment] */
+                /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+                /* coverity[misra_c_2012_rule_11_5_violation] */
+                pxNewTCB->pxStack = ( StackType_t * ) pvPortMallocStack( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) );
 
                 if( pxNewTCB->pxStack == NULL )
                 {
@@ -1646,12 +1658,18 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
             StackType_t * pxStack;
 
             /* Allocate space for the stack used by the task being created. */
-            pxStack = pvPortMallocStack( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */
+            /* MISRA Ref 11.5.1 [Malloc memory assignment] */
+            /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+            /* coverity[misra_c_2012_rule_11_5_violation] */
+            pxStack = pvPortMallocStack( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) );
 
             if( pxStack != NULL )
             {
                 /* Allocate space for the TCB. */
-                pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */
+                /* MISRA Ref 11.5.1 [Malloc memory assignment] */
+                /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+                /* coverity[misra_c_2012_rule_11_5_violation] */
+                pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) );
 
                 if( pxNewTCB != NULL )
                 {
@@ -3937,7 +3955,10 @@ BaseType_t xTaskResumeAll( void )
                      * appropriate ready list. */
                     while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
                     {
-                        pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+                        /* MISRA Ref 11.5.3 [Void pointer assignment] */
+                        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+                        /* coverity[misra_c_2012_rule_11_5_violation] */
+                        pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) );
                         listREMOVE_ITEM( &( pxTCB->xEventListItem ) );
                         portMEMORY_BARRIER();
                         listREMOVE_ITEM( &( pxTCB->xStateListItem ) );
@@ -4148,11 +4169,17 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char
 
             if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )
             {
-                listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+                /* MISRA Ref 11.5.3 [Void pointer assignment] */
+                /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+                /* coverity[misra_c_2012_rule_11_5_violation] */
+                listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList );
 
                 do
                 {
-                    listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+                    /* MISRA Ref 11.5.3 [Void pointer assignment] */
+                    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+                    /* coverity[misra_c_2012_rule_11_5_violation] */
+                    listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList );
 
                     /* Check each character in the name looking for a match or
                      * mismatch. */
@@ -4216,6 +4243,9 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char
             {
                 for( pxIterator = listGET_HEAD_ENTRY( pxList ); pxIterator != pxEndMarker; pxIterator = listGET_NEXT( pxIterator ) )
                 {
+                    /* MISRA Ref 11.5.3 [Void pointer assignment] */
+                    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+                    /* coverity[misra_c_2012_rule_11_5_violation] */
                     TCB_t * pxTCB = listGET_LIST_ITEM_OWNER( pxIterator );
 
                     /* Check each character in the name looking for a match or
@@ -4738,7 +4768,10 @@ BaseType_t xTaskIncrementTick( void )
                      * item at the head of the delayed list.  This is the time
                      * at which the task at the head of the delayed list must
                      * be removed from the Blocked state. */
-                    pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+                    /* MISRA Ref 11.5.3 [Void pointer assignment] */
+                    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+                    /* coverity[misra_c_2012_rule_11_5_violation] */
+                    pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList );
                     xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) );
 
                     if( xConstTickCount < xItemValue )
@@ -5109,7 +5142,10 @@ BaseType_t xTaskIncrementTick( void )
 
             /* Select a new task to run using either the generic C or port
              * optimised asm code. */
-            taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+            /* MISRA Ref 11.5.3 [Void pointer assignment] */
+            /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+            /* coverity[misra_c_2012_rule_11_5_violation] */
+            taskSELECT_HIGHEST_PRIORITY_TASK();
             traceTASK_SWITCHED_IN();
 
             /* After the new task is switched in, update the global errno. */
@@ -5346,7 +5382,10 @@ BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList )
      *
      * This function assumes that a check has already been made to ensure that
      * pxEventList is not empty. */
-    pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+    /* MISRA Ref 11.5.3 [Void pointer assignment] */
+    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+    /* coverity[misra_c_2012_rule_11_5_violation] */
+    pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList );
     configASSERT( pxUnblockedTCB );
     listREMOVE_ITEM( &( pxUnblockedTCB->xEventListItem ) );
 
@@ -5432,7 +5471,10 @@ void vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem,
 
     /* Remove the event list form the event flag.  Interrupts do not access
      * event flags. */
-    pxUnblockedTCB = listGET_LIST_ITEM_OWNER( pxEventListItem ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+    /* MISRA Ref 11.5.3 [Void pointer assignment] */
+    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+    /* coverity[misra_c_2012_rule_11_5_violation] */
+    pxUnblockedTCB = listGET_LIST_ITEM_OWNER( pxEventListItem );
     configASSERT( pxUnblockedTCB );
     listREMOVE_ITEM( pxEventListItem );
 
@@ -6039,7 +6081,10 @@ static void prvCheckTasksWaitingTermination( void )
                 taskENTER_CRITICAL();
                 {
                     {
-                        pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+                        /* MISRA Ref 11.5.3 [Void pointer assignment] */
+                        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+                        /* coverity[misra_c_2012_rule_11_5_violation] */
+                        pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) );
                         ( void ) uxListRemove( &( pxTCB->xStateListItem ) );
                         --uxCurrentNumberOfTasks;
                         --uxDeletedTasksWaitingCleanUp;
@@ -6060,7 +6105,10 @@ static void prvCheckTasksWaitingTermination( void )
                      * waiting to enter the critical section. */
                     if( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
                     {
-                        pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+                        /* MISRA Ref 11.5.3 [Void pointer assignment] */
+                        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+                        /* coverity[misra_c_2012_rule_11_5_violation] */
+                        pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) );
 
                         if( pxTCB->xTaskRunState == taskTASK_NOT_RUNNING )
                         {
@@ -6247,7 +6295,10 @@ static void prvCheckTasksWaitingTermination( void )
 
         if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )
         {
-            listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+            /* MISRA Ref 11.5.3 [Void pointer assignment] */
+            /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+            /* coverity[misra_c_2012_rule_11_5_violation] */
+            listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList );
 
             /* Populate an TaskStatus_t structure within the
              * pxTaskStatusArray array for each task that is referenced from
@@ -6255,7 +6306,10 @@ static void prvCheckTasksWaitingTermination( void )
              * meaning of each TaskStatus_t structure member. */
             do
             {
-                listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+                /* MISRA Ref 11.5.3 [Void pointer assignment] */
+                /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+                /* coverity[misra_c_2012_rule_11_5_violation] */
+                listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList );
                 vTaskGetInfo( ( TaskHandle_t ) pxNextTCB, &( pxTaskStatusArray[ uxTask ] ), pdTRUE, eState );
                 uxTask++;
             } while( pxNextTCB != pxFirstTCB );
@@ -7225,7 +7279,10 @@ static void prvResetNextTaskUnblockTime( void )
         /* Allocate an array index for each task.  NOTE!  if
          * configSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will
          * equate to NULL. */
-        pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation allocates a struct that has the alignment requirements of a pointer. */
+        /* MISRA Ref 11.5.1 [Malloc memory assignment] */
+        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+        /* coverity[misra_c_2012_rule_11_5_violation] */
+        pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) );
 
         if( pxTaskStatusArray != NULL )
         {
@@ -7384,7 +7441,10 @@ static void prvResetNextTaskUnblockTime( void )
         /* Allocate an array index for each task.  NOTE!  If
          * configSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will
          * equate to NULL. */
-        pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation allocates a struct that has the alignment requirements of a pointer. */
+        /* MISRA Ref 11.5.1 [Malloc memory assignment] */
+        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+        /* coverity[misra_c_2012_rule_11_5_violation] */
+        pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) );
 
         if( pxTaskStatusArray != NULL )
         {
diff --git a/timers.c b/timers.c
index b5a8d3846..2d24bf042 100644
--- a/timers.c
+++ b/timers.c
@@ -349,7 +349,10 @@
 
             traceENTER_xTimerCreate( pcTimerName, xTimerPeriodInTicks, xAutoReload, pvTimerID, pxCallbackFunction );
 
-            pxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of Timer_t is always a pointer to the timer's name. */
+            /* MISRA Ref 11.5.1 [Malloc memory assignment] */
+            /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+            /* coverity[misra_c_2012_rule_11_5_violation] */
+            pxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) );
 
             if( pxNewTimer != NULL )
             {
@@ -721,7 +724,10 @@
     static void prvProcessExpiredTimer( const TickType_t xNextExpireTime,
                                         const TickType_t xTimeNow )
     {
-        Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+        /* MISRA Ref 11.5.3 [Void pointer assignment] */
+        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+        /* coverity[misra_c_2012_rule_11_5_violation] */
+        Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList );
 
         /* Remove the timer from the list of active timers.  A check has already
          * been performed to ensure the list is not empty. */

From edce1e94b3ab06000e99727897f51a5845bbba16 Mon Sep 17 00:00:00 2001
From: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Date: Wed, 6 Dec 2023 13:57:10 +0530
Subject: [PATCH 138/424] Fix MISRA_C_2012 rule 20.7 violation (#843)

* Wrap macro parameter expansion by parentheses
* Update parentheses in SMP macro definition

---------

Co-authored-by: Soren Ptak <ptaksoren@gmail.com>
Co-authored-by: Monika Singh <moninom@amazon.com>
Co-authored-by: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
---
 stream_buffer.c | 20 ++++++++++----------
 tasks.c         | 32 ++++++++++++++++----------------
 2 files changed, 26 insertions(+), 26 deletions(-)

diff --git a/stream_buffer.c b/stream_buffer.c
index d6a9ffffc..35e67cf35 100644
--- a/stream_buffer.c
+++ b/stream_buffer.c
@@ -153,16 +153,16 @@
  * invoke the callback else use the send complete macro which is provided by default for all instances.
  */
 #if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
-    #define prvSEND_COMPLETED( pxStreamBuffer )                                           \
-    do {                                                                                  \
-        if( ( pxStreamBuffer )->pxSendCompletedCallback != NULL )                         \
-        {                                                                                 \
-            pxStreamBuffer->pxSendCompletedCallback( ( pxStreamBuffer ), pdFALSE, NULL ); \
-        }                                                                                 \
-        else                                                                              \
-        {                                                                                 \
-            sbSEND_COMPLETED( ( pxStreamBuffer ) );                                       \
-        }                                                                                 \
+    #define prvSEND_COMPLETED( pxStreamBuffer )                                               \
+    do {                                                                                      \
+        if( ( pxStreamBuffer )->pxSendCompletedCallback != NULL )                             \
+        {                                                                                     \
+            ( pxStreamBuffer )->pxSendCompletedCallback( ( pxStreamBuffer ), pdFALSE, NULL ); \
+        }                                                                                     \
+        else                                                                                  \
+        {                                                                                     \
+            sbSEND_COMPLETED( ( pxStreamBuffer ) );                                           \
+        }                                                                                     \
     } while( 0 )
 #else /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */
     #define prvSEND_COMPLETED( pxStreamBuffer )    sbSEND_COMPLETED( ( pxStreamBuffer ) )
diff --git a/tasks.c b/tasks.c
index a9427539a..8f691d117 100644
--- a/tasks.c
+++ b/tasks.c
@@ -324,22 +324,22 @@
 /* Yields the given core. This must be called from a critical section and xCoreID
  * must be valid. This macro is not required in single core since there is only
  * one core to yield. */
-    #define prvYieldCore( xCoreID )                                                      \
-    do {                                                                                 \
-        if( xCoreID == ( BaseType_t ) portGET_CORE_ID() )                                \
-        {                                                                                \
-            /* Pending a yield for this core since it is in the critical section. */     \
-            xYieldPendings[ xCoreID ] = pdTRUE;                                          \
-        }                                                                                \
-        else                                                                             \
-        {                                                                                \
-            /* Request other core to yield if it is not requested before. */             \
-            if( pxCurrentTCBs[ xCoreID ]->xTaskRunState != taskTASK_SCHEDULED_TO_YIELD ) \
-            {                                                                            \
-                portYIELD_CORE( xCoreID );                                               \
-                pxCurrentTCBs[ xCoreID ]->xTaskRunState = taskTASK_SCHEDULED_TO_YIELD;   \
-            }                                                                            \
-        }                                                                                \
+    #define prvYieldCore( xCoreID )                                                          \
+    do {                                                                                     \
+        if( ( xCoreID ) == ( BaseType_t ) portGET_CORE_ID() )                                \
+        {                                                                                    \
+            /* Pending a yield for this core since it is in the critical section. */         \
+            xYieldPendings[ ( xCoreID ) ] = pdTRUE;                                          \
+        }                                                                                    \
+        else                                                                                 \
+        {                                                                                    \
+            /* Request other core to yield if it is not requested before. */                 \
+            if( pxCurrentTCBs[ ( xCoreID ) ]->xTaskRunState != taskTASK_SCHEDULED_TO_YIELD ) \
+            {                                                                                \
+                portYIELD_CORE( xCoreID );                                                   \
+                pxCurrentTCBs[ ( xCoreID ) ]->xTaskRunState = taskTASK_SCHEDULED_TO_YIELD;   \
+            }                                                                                \
+        }                                                                                    \
     } while( 0 )
 #endif /* #if ( configNUMBER_OF_CORES > 1 ) */
 /*-----------------------------------------------------------*/

From 71d86f9a6e9c46e678aa51ca3fd746b1d0859636 Mon Sep 17 00:00:00 2001
From: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Date: Wed, 6 Dec 2023 16:33:18 +0530
Subject: [PATCH 139/424] Fix MISRA_C_2012 rule 17.7 violation (#848)

* Assign return value of xPortStartScheduler API to a variable

* Add void datatype

---------

Co-authored-by: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
---
 tasks.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/tasks.c b/tasks.c
index 8f691d117..f5d031227 100644
--- a/tasks.c
+++ b/tasks.c
@@ -3727,7 +3727,10 @@ void vTaskStartScheduler( void )
 
         /* Setting up the timer tick is hardware specific and thus in the
          * portable interface. */
-        xPortStartScheduler();
+
+        /* The return value for xPortStartScheduler is not required
+         * hence using a void datatype. */
+        ( void ) xPortStartScheduler();
 
         /* In most cases, xPortStartScheduler() will not return. If it
          * returns pdTRUE then there was not enough heap memory available

From ce41f6ec748f35ba059c3c9f20550162e61fde66 Mon Sep 17 00:00:00 2001
From: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Date: Wed, 6 Dec 2023 21:37:52 +0530
Subject: [PATCH 140/424] Fix MISRA_C_2012 rule 7.2 violation (#842)

* Add a u or U suffix for unsigned numerical literals

* Fix formatting

* Replace u with U for naming convention

---------

Co-authored-by: Soren Ptak <ptaksoren@gmail.com>
Co-authored-by: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
---
 include/stack_macros.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/stack_macros.h b/include/stack_macros.h
index 7ead99ffd..0fd58139b 100644
--- a/include/stack_macros.h
+++ b/include/stack_macros.h
@@ -89,7 +89,7 @@
     #define taskCHECK_FOR_STACK_OVERFLOW()                                                            \
     do {                                                                                              \
         const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack;                       \
-        const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5;                                        \
+        const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5U;                                       \
                                                                                                       \
         if( ( pulStack[ 0 ] != ulCheckValue ) ||                                                      \
             ( pulStack[ 1 ] != ulCheckValue ) ||                                                      \

From 22eb827b3d71d44db3324ab273913e3940cb5ea7 Mon Sep 17 00:00:00 2001
From: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Date: Wed, 6 Dec 2023 21:53:52 +0530
Subject: [PATCH 141/424] Add parameter name for function type (#845)

Co-authored-by: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
---
 include/croutine.h | 4 ++--
 include/projdefs.h | 2 +-
 include/task.h     | 2 +-
 include/timers.h   | 4 ++--
 4 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/include/croutine.h b/include/croutine.h
index 664e38b37..40ac9765b 100644
--- a/include/croutine.h
+++ b/include/croutine.h
@@ -47,8 +47,8 @@
 typedef void * CoRoutineHandle_t;
 
 /* Defines the prototype to which co-routine functions must conform. */
-typedef void (* crCOROUTINE_CODE)( CoRoutineHandle_t,
-                                   UBaseType_t );
+typedef void (* crCOROUTINE_CODE)( CoRoutineHandle_t xHandle,
+                                   UBaseType_t uxIndex );
 
 typedef struct corCoRoutineControlBlock
 {
diff --git a/include/projdefs.h b/include/projdefs.h
index 26f6e4f0c..370285d30 100644
--- a/include/projdefs.h
+++ b/include/projdefs.h
@@ -33,7 +33,7 @@
  * Defines the prototype to which task functions must conform.  Defined in this
  * file to ensure the type is known before portable.h is included.
  */
-typedef void (* TaskFunction_t)( void * );
+typedef void (* TaskFunction_t)( void * arg );
 
 /* Converts a time in milliseconds to a time in ticks.  This macro can be
  * overridden by a macro of the same name defined in FreeRTOSConfig.h in case the
diff --git a/include/task.h b/include/task.h
index cb06c2370..26c32aa72 100644
--- a/include/task.h
+++ b/include/task.h
@@ -96,7 +96,7 @@ typedef const struct tskTaskControlBlock   * ConstTaskHandle_t;
  * Defines the prototype to which the application task hook function must
  * conform.
  */
-typedef BaseType_t (* TaskHookFunction_t)( void * );
+typedef BaseType_t (* TaskHookFunction_t)( void * arg );
 
 /* Task states returned by eTaskGetState. */
 typedef enum
diff --git a/include/timers.h b/include/timers.h
index 054ec097f..894087ec2 100644
--- a/include/timers.h
+++ b/include/timers.h
@@ -88,8 +88,8 @@ typedef void (* TimerCallbackFunction_t)( TimerHandle_t xTimer );
  * Defines the prototype to which functions used with the
  * xTimerPendFunctionCallFromISR() function must conform.
  */
-typedef void (* PendedFunction_t)( void *,
-                                   uint32_t );
+typedef void (* PendedFunction_t)( void * arg1,
+                                   uint32_t arg2 );
 
 /**
  * TimerHandle_t xTimerCreate(  const char * const pcTimerName,

From d1a02021251e3cddcaf60a26bdb5c04c77500704 Mon Sep 17 00:00:00 2001
From: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Date: Thu, 7 Dec 2023 11:27:50 +0530
Subject: [PATCH 142/424] Fix MISRA_C_2012 rule 8.4 violation (#844)

Fix MISRA_C_2012 rule 8.4 violation
---
 MISRA.md | 15 ++++++++-------
 queue.c  |  4 ++++
 tasks.c  |  5 ++++-
 3 files changed, 16 insertions(+), 8 deletions(-)

diff --git a/MISRA.md b/MISRA.md
index 33e966817..72103a0dc 100644
--- a/MISRA.md
+++ b/MISRA.md
@@ -24,14 +24,15 @@ MISRA C:2012 Rule 8.4: A compatible declaration shall be visible when an
         object or function with external linkage is defined.
 
 _Ref 8.4.1_
+ - pxCurrentTCB(s) is defined with external linkage but it is only referenced
+   from the assembly code in the port files. Therefore, adding a declaration in
+   header file is not useful as the assembly code will still need to declare it
+   separately.
 
-- This rule requires that a compatible declaration is made available
-  in a header file when an object with external linkage is defined.
-  pxCurrentTCB(s) is defined with external linkage but it is only
-  referenced from the assembly code in the port files. Therefore, adding
-  a declaration in header file is not useful as the assembly code will
-  still need to declare it separately.
-
+_Ref 8.4.2_
+ - xQueueRegistry is defined with external linkage because it is accessed by the
+   kernel unit tests. It is not meant to be directly accessed by the application
+   and therefore, not declared in a header file.
 
 #### Rule 11.3
 
diff --git a/queue.c b/queue.c
index 1aabc9f31..a6fe52eac 100644
--- a/queue.c
+++ b/queue.c
@@ -165,6 +165,10 @@ typedef xQUEUE Queue_t;
 /* The queue registry is simply an array of QueueRegistryItem_t structures.
  * The pcQueueName member of a structure being NULL is indicative of the
  * array position being vacant. */
+
+/* MISRA Ref 8.4.2 [Declaration shall be visible] */
+/* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-84 */
+/* coverity[misra_c_2012_rule_8_4_violation] */
     PRIVILEGED_DATA QueueRegistryItem_t xQueueRegistry[ configQUEUE_REGISTRY_SIZE ];
 
 #endif /* configQUEUE_REGISTRY_SIZE */
diff --git a/tasks.c b/tasks.c
index f5d031227..697be9c99 100644
--- a/tasks.c
+++ b/tasks.c
@@ -436,6 +436,9 @@ typedef tskTCB TCB_t;
 /*lint -save -e956 A manual analysis and inspection has been used to determine
  * which static variables must be declared volatile. */
 #if ( configNUMBER_OF_CORES == 1 )
+    /* MISRA Ref 8.4.1 [Declaration shall be visible] */
+    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-84 */
+    /* coverity[misra_c_2012_rule_8_4_violation] */
     portDONT_DISCARD PRIVILEGED_DATA TCB_t * volatile pxCurrentTCB = NULL;
 #else
     /* MISRA Ref 8.4.1 [Declaration shall be visible] */
@@ -490,7 +493,7 @@ PRIVILEGED_DATA static TaskHandle_t xIdleTaskHandles[ configNUMBER_OF_CORES ];
 /* Improve support for OpenOCD. The kernel tracks Ready tasks via priority lists.
  * For tracking the state of remote threads, OpenOCD uses uxTopUsedPriority
  * to determine the number of priority lists to read back from the remote target. */
-const volatile UBaseType_t uxTopUsedPriority = configMAX_PRIORITIES - 1U;
+static const volatile UBaseType_t uxTopUsedPriority = configMAX_PRIORITIES - 1U;
 
 /* Context switches are held pending while the scheduler is suspended.  Also,
  * interrupts must not manipulate the xStateListItem of a TCB, or any of the

From 55094e2ddf4006f03492bcb3ca82efc6954fb071 Mon Sep 17 00:00:00 2001
From: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Date: Thu, 7 Dec 2023 12:15:09 +0530
Subject: [PATCH 143/424] Fix MISRA_C_2012 rule 13.2 violation (#855)

* Assign volatile variables to local non-volatile variables before read

* Fix stack macro overflow check volatile access

* Explicit the read order of volatile variable

* Fix issue : ISO C90 forbids mixed declarations and code



---------

Co-authored-by: Ubuntu <ubuntu@ip-172-31-34-245.ap-northeast-1.compute.internal>
Co-authored-by: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Co-authored-by: Monika Singh <moninom@amazon.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
---
 include/stack_macros.h | 60 ++++++++++++++++++++++--------------------
 tasks.c                | 20 +++++++++-----
 2 files changed, 45 insertions(+), 35 deletions(-)

diff --git a/include/stack_macros.h b/include/stack_macros.h
index 0fd58139b..f53afb2cd 100644
--- a/include/stack_macros.h
+++ b/include/stack_macros.h
@@ -56,13 +56,14 @@
 #if ( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH < 0 ) )
 
 /* Only the current stack state is to be checked. */
-    #define taskCHECK_FOR_STACK_OVERFLOW()                                                            \
-    do {                                                                                              \
-        /* Is the currently saved stack pointer within the stack limit? */                            \
-        if( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack + portSTACK_LIMIT_PADDING )           \
-        {                                                                                             \
-            vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \
-        }                                                                                             \
+    #define taskCHECK_FOR_STACK_OVERFLOW()                                                      \
+    do {                                                                                        \
+        /* Is the currently saved stack pointer within the stack limit? */                      \
+        if( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack + portSTACK_LIMIT_PADDING )     \
+        {                                                                                       \
+            char * pcOverflowTaskName = pxCurrentTCB->pcTaskName;                               \
+            vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pcOverflowTaskName ); \
+        }                                                                                       \
     } while( 0 )
 
 #endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
@@ -71,14 +72,15 @@
 #if ( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH > 0 ) )
 
 /* Only the current stack state is to be checked. */
-    #define taskCHECK_FOR_STACK_OVERFLOW()                                                            \
-    do {                                                                                              \
-                                                                                                      \
-        /* Is the currently saved stack pointer within the stack limit? */                            \
-        if( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack - portSTACK_LIMIT_PADDING )      \
-        {                                                                                             \
-            vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \
-        }                                                                                             \
+    #define taskCHECK_FOR_STACK_OVERFLOW()                                                       \
+    do {                                                                                         \
+                                                                                                 \
+        /* Is the currently saved stack pointer within the stack limit? */                       \
+        if( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack - portSTACK_LIMIT_PADDING ) \
+        {                                                                                        \
+            char * pcOverflowTaskName = pxCurrentTCB->pcTaskName;                                \
+            vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pcOverflowTaskName );  \
+        }                                                                                        \
     } while( 0 )
 
 #endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
@@ -86,18 +88,19 @@
 
 #if ( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) )
 
-    #define taskCHECK_FOR_STACK_OVERFLOW()                                                            \
-    do {                                                                                              \
-        const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack;                       \
-        const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5U;                                       \
-                                                                                                      \
-        if( ( pulStack[ 0 ] != ulCheckValue ) ||                                                      \
-            ( pulStack[ 1 ] != ulCheckValue ) ||                                                      \
-            ( pulStack[ 2 ] != ulCheckValue ) ||                                                      \
-            ( pulStack[ 3 ] != ulCheckValue ) )                                                       \
-        {                                                                                             \
-            vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \
-        }                                                                                             \
+    #define taskCHECK_FOR_STACK_OVERFLOW()                                                      \
+    do {                                                                                        \
+        const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack;                 \
+        const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5;                                  \
+                                                                                                \
+        if( ( pulStack[ 0 ] != ulCheckValue ) ||                                                \
+            ( pulStack[ 1 ] != ulCheckValue ) ||                                                \
+            ( pulStack[ 2 ] != ulCheckValue ) ||                                                \
+            ( pulStack[ 3 ] != ulCheckValue ) )                                                 \
+        {                                                                                       \
+            char * pcOverflowTaskName = pxCurrentTCB->pcTaskName;                               \
+            vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pcOverflowTaskName ); \
+        }                                                                                       \
     } while( 0 )
 
 #endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
@@ -120,7 +123,8 @@
         /* Has the extremity of the task stack ever been written over? */                                                                 \
         if( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 )                     \
         {                                                                                                                                 \
-            vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );                                     \
+            char * pcOverflowTaskName = pxCurrentTCB->pcTaskName;                                                                         \
+            vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pcOverflowTaskName );                                           \
         }                                                                                                                                 \
     } while( 0 )
 
diff --git a/tasks.c b/tasks.c
index 697be9c99..5df19ddb0 100644
--- a/tasks.c
+++ b/tasks.c
@@ -3916,7 +3916,8 @@ void vTaskSuspendAll( void )
         }
         else
         {
-            xReturn = xNextTaskUnblockTime - xTickCount;
+            xReturn = xNextTaskUnblockTime;
+            xReturn -= xTickCount;
         }
 
         return xReturn;
@@ -4549,14 +4550,17 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char
 
     void vTaskStepTick( TickType_t xTicksToJump )
     {
+        TickType_t xUpdatedTickCount;
+
         traceENTER_vTaskStepTick( xTicksToJump );
 
         /* Correct the tick count value after a period during which the tick
          * was suppressed.  Note this does *not* call the tick hook function for
          * each stepped tick. */
-        configASSERT( ( xTickCount + xTicksToJump ) <= xNextTaskUnblockTime );
+        xUpdatedTickCount = xTickCount + xTicksToJump;
+        configASSERT( xUpdatedTickCount <= xNextTaskUnblockTime );
 
-        if( ( xTickCount + xTicksToJump ) == xNextTaskUnblockTime )
+        if( xUpdatedTickCount == xNextTaskUnblockTime )
         {
             /* Arrange for xTickCount to reach xNextTaskUnblockTime in
              * xTaskIncrementTick() when the scheduler resumes.  This ensures
@@ -8450,6 +8454,8 @@ static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait,
 {
     TickType_t xTimeToWake;
     const TickType_t xConstTickCount = xTickCount;
+    List_t * const pxDelayedList = pxDelayedTaskList;
+    List_t * const pxOverflowDelayedList = pxOverflowDelayedTaskList;
 
     #if ( INCLUDE_xTaskAbortDelay == 1 )
     {
@@ -8497,14 +8503,14 @@ static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait,
                 /* Wake time has overflowed.  Place this item in the overflow
                  * list. */
                 traceMOVED_TASK_TO_OVERFLOW_DELAYED_LIST();
-                vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+                vListInsert( pxOverflowDelayedList, &( pxCurrentTCB->xStateListItem ) );
             }
             else
             {
                 /* The wake time has not overflowed, so the current block list
                  * is used. */
                 traceMOVED_TASK_TO_DELAYED_LIST();
-                vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+                vListInsert( pxDelayedList, &( pxCurrentTCB->xStateListItem ) );
 
                 /* If the task entering the blocked state was placed at the
                  * head of the list of blocked tasks then xNextTaskUnblockTime
@@ -8534,13 +8540,13 @@ static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait,
         {
             traceMOVED_TASK_TO_OVERFLOW_DELAYED_LIST();
             /* Wake time has overflowed.  Place this item in the overflow list. */
-            vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+            vListInsert( pxOverflowDelayedList, &( pxCurrentTCB->xStateListItem ) );
         }
         else
         {
             traceMOVED_TASK_TO_DELAYED_LIST();
             /* The wake time has not overflowed, so the current block list is used. */
-            vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+            vListInsert( pxDelayedList, &( pxCurrentTCB->xStateListItem ) );
 
             /* If the task entering the blocked state was placed at the head of the
              * list of blocked tasks then xNextTaskUnblockTime needs to be updated

From 51437bf9433a0043f29921348097069fdd4ae4b9 Mon Sep 17 00:00:00 2001
From: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Date: Thu, 7 Dec 2023 16:53:02 +0800
Subject: [PATCH 144/424] Fix MISRA C 2012 rule 8.6 errors (#862)

* Fix MISRA C 2012 rule 8.6 errors

* Add suppression for hook function

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Ubuntu <ubuntu@ip-172-31-34-245.ap-northeast-1.compute.internal>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 MISRA.md                |  13 +++-
 include/queue.h         | 103 ++++++++++++++++++++----------
 include/stream_buffer.h |  17 ++---
 include/task.h          | 136 ++++++++++++++++++++++++++++------------
 include/timers.h        |  23 ++++---
 5 files changed, 203 insertions(+), 89 deletions(-)

diff --git a/MISRA.md b/MISRA.md
index 72103a0dc..9296cb961 100644
--- a/MISRA.md
+++ b/MISRA.md
@@ -21,7 +21,7 @@ grep 'MISRA Ref 8.4.1' . -rI
 #### Rule 8.4
 
 MISRA C:2012 Rule 8.4: A compatible declaration shall be visible when an
-        object or function with external linkage is defined.
+object or function with external linkage is defined.
 
 _Ref 8.4.1_
  - pxCurrentTCB(s) is defined with external linkage but it is only referenced
@@ -34,6 +34,17 @@ _Ref 8.4.2_
    kernel unit tests. It is not meant to be directly accessed by the application
    and therefore, not declared in a header file.
 
+
+#### Rule 8.6
+
+MISRA C:2012 Rule 8.6: An identifier with external linkage shall have exactly
+one external definition.
+
+_Ref 8.6.1_
+ - This rule prohibits an identifier with external linkage to have multiple
+   definitions or no definition. FreeRTOS hook functions are implemented in
+   the application and therefore, have no definition in the Kernel code.
+
 #### Rule 11.3
 
 MISRA C:2012 Rule 11.3: A cast shall not be performed between a pointer to
diff --git a/include/queue.h b/include/queue.h
index 821545672..a3d2400f4 100644
--- a/include/queue.h
+++ b/include/queue.h
@@ -1455,6 +1455,8 @@ BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FU
 BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
 UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
 
+#if ( configUSE_CO_ROUTINES == 1 )
+
 /*
  * The functions defined above are for passing data to and from tasks.  The
  * functions below are the equivalents for passing data to and from
@@ -1464,18 +1466,20 @@ UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue ) PRIVILEG
  * should not be called directly from application code.  Instead use the macro
  * wrappers defined within croutine.h.
  */
-BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue,
-                                const void * pvItemToQueue,
-                                BaseType_t xCoRoutinePreviouslyWoken );
-BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue,
-                                   void * pvBuffer,
-                                   BaseType_t * pxTaskWoken );
-BaseType_t xQueueCRSend( QueueHandle_t xQueue,
-                         const void * pvItemToQueue,
-                         TickType_t xTicksToWait );
-BaseType_t xQueueCRReceive( QueueHandle_t xQueue,
-                            void * pvBuffer,
-                            TickType_t xTicksToWait );
+    BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue,
+                                    const void * pvItemToQueue,
+                                    BaseType_t xCoRoutinePreviouslyWoken );
+    BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue,
+                                       void * pvBuffer,
+                                       BaseType_t * pxTaskWoken );
+    BaseType_t xQueueCRSend( QueueHandle_t xQueue,
+                             const void * pvItemToQueue,
+                             TickType_t xTicksToWait );
+    BaseType_t xQueueCRReceive( QueueHandle_t xQueue,
+                                void * pvBuffer,
+                                TickType_t xTicksToWait );
+
+#endif /* if ( configUSE_CO_ROUTINES == 1 ) */
 
 /*
  * For internal use only.  Use xSemaphoreCreateMutex(),
@@ -1483,17 +1487,30 @@ BaseType_t xQueueCRReceive( QueueHandle_t xQueue,
  * these functions directly.
  */
 QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
-QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType,
-                                       StaticQueue_t * pxStaticQueue ) PRIVILEGED_FUNCTION;
-QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount,
-                                             const UBaseType_t uxInitialCount ) PRIVILEGED_FUNCTION;
-QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount,
-                                                   const UBaseType_t uxInitialCount,
-                                                   StaticQueue_t * pxStaticQueue ) PRIVILEGED_FUNCTION;
+
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+    QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType,
+                                           StaticQueue_t * pxStaticQueue ) PRIVILEGED_FUNCTION;
+#endif
+
+#if ( configUSE_COUNTING_SEMAPHORES == 1 )
+    QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount,
+                                                 const UBaseType_t uxInitialCount ) PRIVILEGED_FUNCTION;
+#endif
+
+#if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+    QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount,
+                                                       const UBaseType_t uxInitialCount,
+                                                       StaticQueue_t * pxStaticQueue ) PRIVILEGED_FUNCTION;
+#endif
+
 BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue,
                                 TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
-TaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;
-TaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;
+
+#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+    TaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;
+    TaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;
+#endif
 
 /*
  * For internal use only.  Use xSemaphoreTakeMutexRecursive() or
@@ -1653,7 +1670,9 @@ BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex ) PRIVILEGED_FUNCTION;
  * @return If the queue set is created successfully then a handle to the created
  * queue set is returned.  Otherwise NULL is returned.
  */
-QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength ) PRIVILEGED_FUNCTION;
+#if ( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+    QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength ) PRIVILEGED_FUNCTION;
+#endif
 
 /*
  * Adds a queue or semaphore to a queue set that was previously created by a
@@ -1677,8 +1696,10 @@ QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength ) PRIVILE
  * queue set because it is already a member of a different queue set then pdFAIL
  * is returned.
  */
-BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
-                           QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+#if ( configUSE_QUEUE_SETS == 1 )
+    BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                               QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+#endif
 
 /*
  * Removes a queue or semaphore from a queue set.  A queue or semaphore can only
@@ -1697,8 +1718,10 @@ BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
  * then pdPASS is returned.  If the queue was not in the queue set, or the
  * queue (or semaphore) was not empty, then pdFAIL is returned.
  */
-BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore,
-                                QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+#if ( configUSE_QUEUE_SETS == 1 )
+    BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                                    QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+#endif
 
 /*
  * xQueueSelectFromSet() selects from the members of a queue set a queue or
@@ -1734,13 +1757,17 @@ BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore,
  * in the queue set that is available, or NULL if no such queue or semaphore
  * exists before before the specified block time expires.
  */
-QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
-                                            const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+#if ( configUSE_QUEUE_SETS == 1 )
+    QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
+                                                const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+#endif
 
 /*
  * A version of xQueueSelectFromSet() that can be used from an ISR.
  */
-QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+#if ( configUSE_QUEUE_SETS == 1 )
+    QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+#endif
 
 /* Not public API functions. */
 void vQueueWaitForMessageRestricted( QueueHandle_t xQueue,
@@ -1748,10 +1775,20 @@ void vQueueWaitForMessageRestricted( QueueHandle_t xQueue,
                                      const BaseType_t xWaitIndefinitely ) PRIVILEGED_FUNCTION;
 BaseType_t xQueueGenericReset( QueueHandle_t xQueue,
                                BaseType_t xNewQueue ) PRIVILEGED_FUNCTION;
-void vQueueSetQueueNumber( QueueHandle_t xQueue,
-                           UBaseType_t uxQueueNumber ) PRIVILEGED_FUNCTION;
-UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
-uint8_t ucQueueGetQueueType( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+    void vQueueSetQueueNumber( QueueHandle_t xQueue,
+                               UBaseType_t uxQueueNumber ) PRIVILEGED_FUNCTION;
+#endif
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+    UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+#endif
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+    uint8_t ucQueueGetQueueType( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+#endif
+
 UBaseType_t uxQueueGetQueueItemSize( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
 UBaseType_t uxQueueGetQueueLength( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
 
diff --git a/include/stream_buffer.h b/include/stream_buffer.h
index 521c178ef..68d12e08f 100644
--- a/include/stream_buffer.h
+++ b/include/stream_buffer.h
@@ -918,14 +918,15 @@ StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes,
                                                  StreamBufferCallbackFunction_t pxSendCompletedCallback,
                                                  StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) PRIVILEGED_FUNCTION;
 
-
-StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
-                                                       size_t xTriggerLevelBytes,
-                                                       BaseType_t xIsMessageBuffer,
-                                                       uint8_t * const pucStreamBufferStorageArea,
-                                                       StaticStreamBuffer_t * const pxStaticStreamBuffer,
-                                                       StreamBufferCallbackFunction_t pxSendCompletedCallback,
-                                                       StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) PRIVILEGED_FUNCTION;
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+    StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
+                                                           size_t xTriggerLevelBytes,
+                                                           BaseType_t xIsMessageBuffer,
+                                                           uint8_t * const pucStreamBufferStorageArea,
+                                                           StaticStreamBuffer_t * const pxStaticStreamBuffer,
+                                                           StreamBufferCallbackFunction_t pxSendCompletedCallback,
+                                                           StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) PRIVILEGED_FUNCTION;
+#endif
 
 size_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
 
diff --git a/include/task.h b/include/task.h
index 26c32aa72..9ed722c15 100644
--- a/include/task.h
+++ b/include/task.h
@@ -752,8 +752,10 @@ typedef enum
  * \defgroup vTaskAllocateMPURegions vTaskAllocateMPURegions
  * \ingroup Tasks
  */
-void vTaskAllocateMPURegions( TaskHandle_t xTaskToModify,
-                              const MemoryRegion_t * const pxRegions ) PRIVILEGED_FUNCTION;
+#if ( portUSING_MPU_WRAPPERS == 1 )
+    void vTaskAllocateMPURegions( TaskHandle_t xTaskToModify,
+                                  const MemoryRegion_t * const pxRegions ) PRIVILEGED_FUNCTION;
+#endif
 
 /**
  * task. h
@@ -960,7 +962,9 @@ BaseType_t xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
  * \defgroup xTaskAbortDelay xTaskAbortDelay
  * \ingroup TaskCtrl
  */
-BaseType_t xTaskAbortDelay( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+#if ( INCLUDE_xTaskAbortDelay == 1 )
+    BaseType_t xTaskAbortDelay( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+#endif
 
 /**
  * task. h
@@ -1070,7 +1074,9 @@ UBaseType_t uxTaskBasePriorityGetFromISR( const TaskHandle_t xTask ) PRIVILEGED_
  * state of the task might change between the function being called, and the
  * functions return value being tested by the calling task.
  */
-eTaskState eTaskGetState( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+#if ( ( INCLUDE_eTaskGetState == 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_xTaskAbortDelay == 1 ) )
+    eTaskState eTaskGetState( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+#endif
 
 /**
  * task. h
@@ -1128,10 +1134,12 @@ eTaskState eTaskGetState( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
  * \defgroup vTaskGetInfo vTaskGetInfo
  * \ingroup TaskCtrl
  */
-void vTaskGetInfo( TaskHandle_t xTask,
-                   TaskStatus_t * pxTaskStatus,
-                   BaseType_t xGetFreeStackSpace,
-                   eTaskState eState ) PRIVILEGED_FUNCTION;
+#if ( configUSE_TRACE_FACILITY == 1 )
+    void vTaskGetInfo( TaskHandle_t xTask,
+                       TaskStatus_t * pxTaskStatus,
+                       BaseType_t xGetFreeStackSpace,
+                       eTaskState eState ) PRIVILEGED_FUNCTION;
+#endif
 
 /**
  * task. h
@@ -1755,7 +1763,9 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION; /*lint !e
  * \defgroup pcTaskGetHandle pcTaskGetHandle
  * \ingroup TaskUtils
  */
-TaskHandle_t xTaskGetHandle( const char * pcNameToQuery ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+#if ( INCLUDE_xTaskGetHandle == 1 )
+    TaskHandle_t xTaskGetHandle( const char * pcNameToQuery ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+#endif
 
 /**
  * task. h
@@ -1814,7 +1824,9 @@ TaskHandle_t xTaskGetHandle( const char * pcNameToQuery ) PRIVILEGED_FUNCTION; /
  * actual spaces on the stack rather than bytes) since the task referenced by
  * xTask was created.
  */
-UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
+    UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+#endif
 
 /**
  * task.h
@@ -1843,7 +1855,9 @@ UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) PRIVILEGED_FUNCTIO
  * actual spaces on the stack rather than bytes) since the task referenced by
  * xTask was created.
  */
-configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
+    configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+#endif
 
 /* When using trace macros it is sometimes necessary to include task.h before
  * FreeRTOS.h.  When this is done TaskHookFunction_t will not yet have been defined,
@@ -1922,6 +1936,9 @@ configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) PRIVIL
  * @param xTask the task that just exceeded its stack boundaries.
  * @param pcTaskName A character string containing the name of the offending task.
  */
+    /* MISRA Ref 8.6.1 [External linkage] */
+    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-86 */
+    /* coverity[misra_c_2012_rule_8_6_violation] */
     void vApplicationStackOverflowHook( TaskHandle_t xTask,
                                         char * pcTaskName );
 
@@ -1940,6 +1957,9 @@ configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) PRIVIL
  * the overhead of a separate task.
  * NOTE: vApplicationIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES, CALL A FUNCTION THAT MIGHT BLOCK.
  */
+    /* MISRA Ref 8.6.1 [External linkage] */
+    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-86 */
+    /* coverity[misra_c_2012_rule_8_6_violation] */
     void vApplicationIdleHook( void );
 
 #endif
@@ -1955,6 +1975,9 @@ configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) PRIVIL
  *
  * This hook function is called in the system tick handler after any OS work is completed.
  */
+    /* MISRA Ref 8.6.1 [External linkage] */
+    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-86 */
+    /* coverity[misra_c_2012_rule_8_6_violation] */
     void vApplicationTickHook( void ); /*lint !e526 Symbol not defined as it is an application callback. */
 
 #endif
@@ -2023,8 +2046,10 @@ configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) PRIVIL
  * wants.  The return value is the value returned by the task hook function
  * registered by the user.
  */
-BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask,
-                                         void * pvParameter ) PRIVILEGED_FUNCTION;
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+    BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask,
+                                             void * pvParameter ) PRIVILEGED_FUNCTION;
+#endif
 
 /**
  * xTaskGetIdleTaskHandle() is only available if
@@ -2043,10 +2068,13 @@ BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask,
  * idle task handle. Call xTaskGetIdleTaskHandleForCore() with xCoreID set to
  * 1,2 ... ( configNUMBER_OF_CORES - 1 ) to get the Passive idle task handles.
  */
-#if ( configNUMBER_OF_CORES == 1 )
-    TaskHandle_t xTaskGetIdleTaskHandle( void ) PRIVILEGED_FUNCTION;
-#endif /* #if ( configNUMBER_OF_CORES == 1 ) */
-TaskHandle_t xTaskGetIdleTaskHandleForCore( BaseType_t xCoreID ) PRIVILEGED_FUNCTION;
+#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
+    #if ( configNUMBER_OF_CORES == 1 )
+        TaskHandle_t xTaskGetIdleTaskHandle( void ) PRIVILEGED_FUNCTION;
+    #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
+
+    TaskHandle_t xTaskGetIdleTaskHandleForCore( BaseType_t xCoreID ) PRIVILEGED_FUNCTION;
+#endif /* #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */
 
 /**
  * configUSE_TRACE_FACILITY must be defined as 1 in FreeRTOSConfig.h for
@@ -2145,9 +2173,11 @@ TaskHandle_t xTaskGetIdleTaskHandleForCore( BaseType_t xCoreID ) PRIVILEGED_FUNC
  *  }
  *  @endcode
  */
-UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
-                                  const UBaseType_t uxArraySize,
-                                  configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) PRIVILEGED_FUNCTION;
+#if ( configUSE_TRACE_FACILITY == 1 )
+    UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
+                                      const UBaseType_t uxArraySize,
+                                      configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) PRIVILEGED_FUNCTION;
+#endif
 
 /**
  * task. h
@@ -2200,8 +2230,10 @@ UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
  * \defgroup vTaskListTasks vTaskListTasks
  * \ingroup TaskUtils
  */
-void vTaskListTasks( char * pcWriteBuffer,
-                     size_t uxBufferLength ) PRIVILEGED_FUNCTION;
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )
+    void vTaskListTasks( char * pcWriteBuffer,
+                         size_t uxBufferLength ) PRIVILEGED_FUNCTION;
+#endif
 
 /**
  * task. h
@@ -2315,8 +2347,10 @@ void vTaskListTasks( char * pcWriteBuffer,
  * \defgroup vTaskGetRunTimeStatistics vTaskGetRunTimeStatistics
  * \ingroup TaskUtils
  */
-void vTaskGetRunTimeStatistics( char * pcWriteBuffer,
-                                size_t uxBufferLength ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configUSE_TRACE_FACILITY == 1 ) )
+    void vTaskGetRunTimeStatistics( char * pcWriteBuffer,
+                                    size_t uxBufferLength ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+#endif
 
 /**
  * task. h
@@ -2413,8 +2447,10 @@ void vTaskGetRunTimeStatistics( char * pcWriteBuffer,
  * \defgroup ulTaskGetRunTimeCounter ulTaskGetRunTimeCounter
  * \ingroup TaskUtils
  */
-configRUN_TIME_COUNTER_TYPE ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
-configRUN_TIME_COUNTER_TYPE ulTaskGetRunTimePercent( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+#if ( configGENERATE_RUN_TIME_STATS == 1 )
+    configRUN_TIME_COUNTER_TYPE ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+    configRUN_TIME_COUNTER_TYPE ulTaskGetRunTimePercent( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+#endif
 
 /**
  * task. h
@@ -2453,8 +2489,10 @@ configRUN_TIME_COUNTER_TYPE ulTaskGetRunTimePercent( const TaskHandle_t xTask )
  * \defgroup ulTaskGetIdleRunTimeCounter ulTaskGetIdleRunTimeCounter
  * \ingroup TaskUtils
  */
-configRUN_TIME_COUNTER_TYPE ulTaskGetIdleRunTimeCounter( void ) PRIVILEGED_FUNCTION;
-configRUN_TIME_COUNTER_TYPE ulTaskGetIdleRunTimePercent( void ) PRIVILEGED_FUNCTION;
+#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+    configRUN_TIME_COUNTER_TYPE ulTaskGetIdleRunTimeCounter( void ) PRIVILEGED_FUNCTION;
+    configRUN_TIME_COUNTER_TYPE ulTaskGetIdleRunTimePercent( void ) PRIVILEGED_FUNCTION;
+#endif
 
 /**
  * task. h
@@ -3536,7 +3574,9 @@ TaskHandle_t xTaskGetCurrentTaskHandle( void ) PRIVILEGED_FUNCTION;
 /*
  * Return the handle of the task running on specified core.
  */
-TaskHandle_t xTaskGetCurrentTaskHandleForCore( BaseType_t xCoreID ) PRIVILEGED_FUNCTION;
+#if ( configNUMBER_OF_CORES > 1 )
+    TaskHandle_t xTaskGetCurrentTaskHandleForCore( BaseType_t xCoreID ) PRIVILEGED_FUNCTION;
+#endif
 
 /*
  * Shortcut used by the queue implementation to prevent unnecessary call to
@@ -3576,14 +3616,18 @@ void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder,
 /*
  * Get the uxTaskNumber assigned to the task referenced by the xTask parameter.
  */
-UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+#if ( configUSE_TRACE_FACILITY == 1 )
+    UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+#endif
 
 /*
  * Set the uxTaskNumber of the task referenced by the xTask parameter to
  * uxHandle.
  */
-void vTaskSetTaskNumber( TaskHandle_t xTask,
-                         const UBaseType_t uxHandle ) PRIVILEGED_FUNCTION;
+#if ( configUSE_TRACE_FACILITY == 1 )
+    void vTaskSetTaskNumber( TaskHandle_t xTask,
+                             const UBaseType_t uxHandle ) PRIVILEGED_FUNCTION;
+#endif
 
 /*
  * Only available when configUSE_TICKLESS_IDLE is set to 1.
@@ -3593,7 +3637,9 @@ void vTaskSetTaskNumber( TaskHandle_t xTask,
  * to date with the actual execution time by being skipped forward by a time
  * equal to the idle period.
  */
-void vTaskStepTick( TickType_t xTicksToJump ) PRIVILEGED_FUNCTION;
+#if ( configUSE_TICKLESS_IDLE != 0 )
+    void vTaskStepTick( TickType_t xTicksToJump ) PRIVILEGED_FUNCTION;
+#endif
 
 /*
  * Only available when configUSE_TICKLESS_IDLE is set to 1.
@@ -3609,7 +3655,9 @@ void vTaskStepTick( TickType_t xTicksToJump ) PRIVILEGED_FUNCTION;
  * critical section between the timer being stopped and the sleep mode being
  * entered to ensure it is ok to proceed into the sleep mode.
  */
-eSleepModeStatus eTaskConfirmSleepModeStatus( void ) PRIVILEGED_FUNCTION;
+#if ( configUSE_TICKLESS_IDLE != 0 )
+    eSleepModeStatus eTaskConfirmSleepModeStatus( void ) PRIVILEGED_FUNCTION;
+#endif
 
 /*
  * For internal use only.  Increment the mutex held count when a mutex is
@@ -3627,7 +3675,9 @@ void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNC
  * For internal use only. Same as portYIELD_WITHIN_API() in single core FreeRTOS.
  * For SMP this is not defined by the port.
  */
-void vTaskYieldWithinAPI( void );
+#if ( configNUMBER_OF_CORES > 1 )
+    void vTaskYieldWithinAPI( void );
+#endif
 
 /*
  * This function is only intended for use when implementing a port of the scheduler
@@ -3637,7 +3687,9 @@ void vTaskYieldWithinAPI( void );
  * It should be used in the implementation of portENTER_CRITICAL if port is running a
  * multiple core FreeRTOS.
  */
-void vTaskEnterCritical( void );
+#if ( ( portCRITICAL_NESTING_IN_TCB == 1 ) || ( configNUMBER_OF_CORES > 1 ) )
+    void vTaskEnterCritical( void );
+#endif
 
 /*
  * This function is only intended for use when implementing a port of the scheduler
@@ -3647,7 +3699,9 @@ void vTaskEnterCritical( void );
  * It should be used in the implementation of portEXIT_CRITICAL if port is running a
  * multiple core FreeRTOS.
  */
-void vTaskExitCritical( void );
+#if ( ( portCRITICAL_NESTING_IN_TCB == 1 ) || ( configNUMBER_OF_CORES > 1 ) )
+    void vTaskExitCritical( void );
+#endif
 
 /*
  * This function is only intended for use when implementing a port of the scheduler
@@ -3655,7 +3709,9 @@ void vTaskExitCritical( void );
  * should be used in the implementation of portENTER_CRITICAL_FROM_ISR if port is
  * running a multiple core FreeRTOS.
  */
-UBaseType_t vTaskEnterCriticalFromISR( void );
+#if ( configNUMBER_OF_CORES > 1 )
+    UBaseType_t vTaskEnterCriticalFromISR( void );
+#endif
 
 /*
  * This function is only intended for use when implementing a port of the scheduler
@@ -3663,7 +3719,9 @@ UBaseType_t vTaskEnterCriticalFromISR( void );
  * should be used in the implementation of portEXIT_CRITICAL_FROM_ISR if port is
  * running a multiple core FreeRTOS.
  */
-void vTaskExitCriticalFromISR( UBaseType_t uxSavedInterruptStatus );
+#if ( configNUMBER_OF_CORES > 1 )
+    void vTaskExitCriticalFromISR( UBaseType_t uxSavedInterruptStatus );
+#endif
 
 #if ( portUSING_MPU_WRAPPERS == 1 )
 
diff --git a/include/timers.h b/include/timers.h
index 894087ec2..1653dbb3a 100644
--- a/include/timers.h
+++ b/include/timers.h
@@ -1198,10 +1198,12 @@ TaskHandle_t xTimerGetTimerDaemonTaskHandle( void ) PRIVILEGED_FUNCTION;
  *  }
  * @endverbatim
  */
-BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend,
-                                          void * pvParameter1,
-                                          uint32_t ulParameter2,
-                                          BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+#if ( INCLUDE_xTimerPendFunctionCall == 1 )
+    BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend,
+                                              void * pvParameter1,
+                                              uint32_t ulParameter2,
+                                              BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+#endif
 
 /**
  * BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend,
@@ -1235,10 +1237,12 @@ BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend,
  * timer daemon task, otherwise pdFALSE is returned.
  *
  */
-BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend,
-                                   void * pvParameter1,
-                                   uint32_t ulParameter2,
-                                   TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+#if ( INCLUDE_xTimerPendFunctionCall == 1 )
+    BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend,
+                                       void * pvParameter1,
+                                       uint32_t ulParameter2,
+                                       TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+#endif
 
 /**
  * const char * const pcTimerGetName( TimerHandle_t xTimer );
@@ -1408,6 +1412,9 @@ BaseType_t xTimerGenericCommandFromISR( TimerHandle_t xTimer,
  *
  * This hook function is called form the timer task once when the task starts running.
  */
+    /* MISRA Ref 8.6.1 [External linkage] */
+    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-86 */
+    /* coverity[misra_c_2012_rule_8_6_violation] */
     void vApplicationDaemonTaskStartupHook( void );
 
 #endif

From 93ef558fa8484211bd1d78c06bbd14aae1b2ece5 Mon Sep 17 00:00:00 2001
From: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Date: Thu, 7 Dec 2023 14:56:44 +0530
Subject: [PATCH 145/424] Declare variable without initializer (#841)

Co-authored-by: Soren Ptak <ptaksoren@gmail.com>
Co-authored-by: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
---
 tasks.c  | 3 ++-
 timers.c | 4 ++--
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/tasks.c b/tasks.c
index 5df19ddb0..7c05bd531 100644
--- a/tasks.c
+++ b/tasks.c
@@ -7412,7 +7412,8 @@ static void prvResetNextTaskUnblockTime( void )
         int iSnprintfReturnValue;
         BaseType_t xOutputBufferFull = pdFALSE;
         UBaseType_t uxArraySize, x;
-        configRUN_TIME_COUNTER_TYPE ulTotalTime, ulStatsAsPercentage;
+        configRUN_TIME_COUNTER_TYPE ulTotalTime = 0;
+        configRUN_TIME_COUNTER_TYPE ulStatsAsPercentage;
 
         traceENTER_vTaskGetRunTimeStatistics( pcWriteBuffer, uxBufferLength );
 
diff --git a/timers.c b/timers.c
index 2d24bf042..72636cf46 100644
--- a/timers.c
+++ b/timers.c
@@ -943,12 +943,12 @@
 
     static void prvProcessReceivedCommands( void )
     {
-        DaemonTaskMessage_t xMessage;
+        DaemonTaskMessage_t xMessage = { 0 };
         Timer_t * pxTimer;
         BaseType_t xTimerListsWereSwitched;
         TickType_t xTimeNow;
 
-        while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */
+        while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL )
         {
             #if ( INCLUDE_xTimerPendFunctionCall == 1 )
             {

From 15af8e072d7299d92a38a2f634c3bf3f095d3a32 Mon Sep 17 00:00:00 2001
From: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Date: Thu, 7 Dec 2023 17:52:21 +0800
Subject: [PATCH 146/424] Add description about overrun warning in queue.c
 (#869)

* Add description about overrun warning in queue.c

* Remove the unreachable configASSERT

* Code review suggestions

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Fix formatting

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Ubuntu <ubuntu@ip-172-31-34-245.ap-northeast-1.compute.internal>
Co-authored-by: Soren Ptak <ptaksoren@gmail.com>
Co-authored-by: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 queue.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/queue.c b/queue.c
index a6fe52eac..6a462607a 100644
--- a/queue.c
+++ b/queue.c
@@ -1849,6 +1849,14 @@ BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue,
                              * again, but only as low as the next highest priority
                              * task that is waiting for the same mutex. */
                             uxHighestWaitingPriority = prvGetDisinheritPriorityAfterTimeout( pxQueue );
+
+                            /* vTaskPriorityDisinheritAfterTimeout uses the uxHighestWaitingPriority
+                             * parameter to index pxReadyTasksLists when adding the task holding
+                             * mutex to the ready list for its new priority. Coverity thinks that
+                             * it can result in out-of-bounds access which is not true because
+                             * uxHighestWaitingPriority, as returned by prvGetDisinheritPriorityAfterTimeout,
+                             * is capped at ( configMAX_PRIORITIES - 1 ). */
+                            /* coverity[overrun] */
                             vTaskPriorityDisinheritAfterTimeout( pxQueue->u.xSemaphore.xMutexHolder, uxHighestWaitingPriority );
                         }
                         taskEXIT_CRITICAL();

From 877484cd7e6422e7bd7a4df4029afe8bca8b81e5 Mon Sep 17 00:00:00 2001
From: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Date: Thu, 7 Dec 2023 18:15:19 +0800
Subject: [PATCH 147/424] Fix MISRA C 2012 Rule 11.1 deviations (#856)

* Update callback function prototype to align with definition
* Suppress unused function pointer parameter

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Ubuntu <ubuntu@ip-172-31-34-245.ap-northeast-1.compute.internal>
Co-authored-by: GitHub Action <action@github.com>
Co-authored-by: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 MISRA.md               | 10 +++++++++-
 event_groups.c         |  8 ++++----
 include/event_groups.h |  4 ++--
 stream_buffer.c        |  9 ++++++++-
 4 files changed, 23 insertions(+), 8 deletions(-)

diff --git a/MISRA.md b/MISRA.md
index 9296cb961..1cca337ff 100644
--- a/MISRA.md
+++ b/MISRA.md
@@ -34,7 +34,6 @@ _Ref 8.4.2_
    kernel unit tests. It is not meant to be directly accessed by the application
    and therefore, not declared in a header file.
 
-
 #### Rule 8.6
 
 MISRA C:2012 Rule 8.6: An identifier with external linkage shall have exactly
@@ -45,6 +44,15 @@ _Ref 8.6.1_
    definitions or no definition. FreeRTOS hook functions are implemented in
    the application and therefore, have no definition in the Kernel code.
 
+#### Rule 11.1
+MISRA C:2012 Rule 11.1: Conversions shall not be performed between a pointer to
+function and any other type.
+
+_Ref 11.1.1_
+ - The pointer to function is casted into void to avoid unused parameter
+   compiler warning when Stream Buffer's Tx and Rx Completed callback feature is
+   not used.
+
 #### Rule 11.3
 
 MISRA C:2012 Rule 11.3: A cast shall not be performed between a pointer to
diff --git a/event_groups.c b/event_groups.c
index 68f8e9ddb..cb154a82c 100644
--- a/event_groups.c
+++ b/event_groups.c
@@ -506,7 +506,7 @@ EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup,
         traceENTER_xEventGroupClearBitsFromISR( xEventGroup, uxBitsToClear );
 
         traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear );
-        xReturn = xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL ); /*lint !e9087 Can't avoid cast to void* as a generic callback function not specific to this use case. Callback casts back to original type so safe. */
+        xReturn = xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL );
 
         traceRETURN_xEventGroupClearBitsFromISR( xReturn );
 
@@ -735,7 +735,7 @@ void vEventGroupDelete( EventGroupHandle_t xEventGroup )
 /* For internal use only - execute a 'set bits' command that was pended from
  * an interrupt. */
 void vEventGroupSetBitsCallback( void * pvEventGroup,
-                                 const uint32_t ulBitsToSet )
+                                 uint32_t ulBitsToSet )
 {
     traceENTER_vEventGroupSetBitsCallback( pvEventGroup, ulBitsToSet );
 
@@ -751,7 +751,7 @@ void vEventGroupSetBitsCallback( void * pvEventGroup,
 /* For internal use only - execute a 'clear bits' command that was pended from
  * an interrupt. */
 void vEventGroupClearBitsCallback( void * pvEventGroup,
-                                   const uint32_t ulBitsToClear )
+                                   uint32_t ulBitsToClear )
 {
     traceENTER_vEventGroupClearBitsCallback( pvEventGroup, ulBitsToClear );
 
@@ -812,7 +812,7 @@ static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits,
         traceENTER_xEventGroupSetBitsFromISR( xEventGroup, uxBitsToSet, pxHigherPriorityTaskWoken );
 
         traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet );
-        xReturn = xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken ); /*lint !e9087 Can't avoid cast to void* as a generic callback function not specific to this use case. Callback casts back to original type so safe. */
+        xReturn = xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken );
 
         traceRETURN_xEventGroupSetBitsFromISR( xReturn );
 
diff --git a/include/event_groups.h b/include/event_groups.h
index f1f86fb7f..d66ab262c 100644
--- a/include/event_groups.h
+++ b/include/event_groups.h
@@ -807,9 +807,9 @@ void vEventGroupDelete( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION;
 
 /* For internal use only. */
 void vEventGroupSetBitsCallback( void * pvEventGroup,
-                                 const uint32_t ulBitsToSet ) PRIVILEGED_FUNCTION;
+                                 uint32_t ulBitsToSet ) PRIVILEGED_FUNCTION;
 void vEventGroupClearBitsCallback( void * pvEventGroup,
-                                   const uint32_t ulBitsToClear ) PRIVILEGED_FUNCTION;
+                                   uint32_t ulBitsToClear ) PRIVILEGED_FUNCTION;
 
 
 #if ( configUSE_TRACE_FACILITY == 1 )
diff --git a/stream_buffer.c b/stream_buffer.c
index 35e67cf35..9899e30ee 100644
--- a/stream_buffer.c
+++ b/stream_buffer.c
@@ -1507,10 +1507,17 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
     }
     #else
     {
+        /* MISRA Ref 11.1.1 [Object type casting] */
+        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-111 */
+        /* coverity[misra_c_2012_rule_11_1_violation] */
         ( void ) pxSendCompletedCallback;
+
+        /* MISRA Ref 11.1.1 [Object type casting] */
+        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-111 */
+        /* coverity[misra_c_2012_rule_11_1_violation] */
         ( void ) pxReceiveCompletedCallback;
     }
-    #endif
+    #endif /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */
 }
 
 #if ( configUSE_TRACE_FACILITY == 1 )

From d95b05ea5f5697f1435d303fe1ea27321d3147f4 Mon Sep 17 00:00:00 2001
From: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Date: Thu, 7 Dec 2023 18:51:14 +0800
Subject: [PATCH 148/424] Suppress MISRA C:2012 rule 21.6 for snprintf (#877)

Suppress MISRA C:2012 rule 21.6 for snprintf
---
 MISRA.md |  9 +++++++++
 tasks.c  | 28 +++++++++++++++++++++++-----
 2 files changed, 32 insertions(+), 5 deletions(-)

diff --git a/MISRA.md b/MISRA.md
index 1cca337ff..734a51291 100644
--- a/MISRA.md
+++ b/MISRA.md
@@ -107,6 +107,15 @@ _Ref 11.5.5_
    because data storage buffers are implemented as uint8_t arrays for the
    ease of sizing, alignment and access.
 
+#### Rule 21.6
+
+MISRA C-2012 Rule 21.6: The Standard Library input/output functions shall not
+be used.
+
+_Ref 21.6.1_
+ - The Standard Library function snprintf is used in vTaskListTasks and
+   vTaskGetRunTimeStatistics APIs, both of which are utility functions only and
+   are not considered part of core kernel implementation.
 
 ### MISRA configuration
 
diff --git a/tasks.c b/tasks.c
index 7c05bd531..1bb8a05a9 100644
--- a/tasks.c
+++ b/tasks.c
@@ -7348,6 +7348,9 @@ static void prvResetNextTaskUnblockTime( void )
                     {
                         /* Write the rest of the string. */
                         #if ( ( configUSE_CORE_AFFINITY == 1 ) && ( configNUMBER_OF_CORES > 1 ) )
+                            /* MISRA Ref 21.6.1 [snprintf for utility] */
+                            /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-216 */
+                            /* coverity[misra_c_2012_rule_21_6_violation] */
                             iSnprintfReturnValue = snprintf( pcWriteBuffer,
                                                              uxBufferLength - uxConsumedBufferLength,
                                                              "\t%c\t%u\t%u\t%u\t0x%x\r\n",
@@ -7355,15 +7358,18 @@ static void prvResetNextTaskUnblockTime( void )
                                                              ( unsigned int ) pxTaskStatusArray[ x ].uxCurrentPriority,
                                                              ( unsigned int ) pxTaskStatusArray[ x ].usStackHighWaterMark,
                                                              ( unsigned int ) pxTaskStatusArray[ x ].xTaskNumber,
-                                                             ( unsigned int ) pxTaskStatusArray[ x ].uxCoreAffinityMask ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
+                                                             ( unsigned int ) pxTaskStatusArray[ x ].uxCoreAffinityMask );
                         #else /* ( ( configUSE_CORE_AFFINITY == 1 ) && ( configNUMBER_OF_CORES > 1 ) ) */
+                            /* MISRA Ref 21.6.1 [snprintf for utility] */
+                            /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-216 */
+                            /* coverity[misra_c_2012_rule_21_6_violation] */
                             iSnprintfReturnValue = snprintf( pcWriteBuffer,
                                                              uxBufferLength - uxConsumedBufferLength,
                                                              "\t%c\t%u\t%u\t%u\r\n",
                                                              cStatus,
                                                              ( unsigned int ) pxTaskStatusArray[ x ].uxCurrentPriority,
                                                              ( unsigned int ) pxTaskStatusArray[ x ].usStackHighWaterMark,
-                                                             ( unsigned int ) pxTaskStatusArray[ x ].xTaskNumber ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
+                                                             ( unsigned int ) pxTaskStatusArray[ x ].xTaskNumber );
                         #endif /* ( ( configUSE_CORE_AFFINITY == 1 ) && ( configNUMBER_OF_CORES > 1 ) ) */
                         uxCharsWrittenBySnprintf = prvSnprintfReturnValueToCharsWritten( iSnprintfReturnValue, uxBufferLength - uxConsumedBufferLength );
 
@@ -7496,21 +7502,27 @@ static void prvResetNextTaskUnblockTime( void )
                             {
                                 #ifdef portLU_PRINTF_SPECIFIER_REQUIRED
                                 {
+                                    /* MISRA Ref 21.6.1 [snprintf for utility] */
+                                    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-216 */
+                                    /* coverity[misra_c_2012_rule_21_6_violation] */
                                     iSnprintfReturnValue = snprintf( pcWriteBuffer,
                                                                      uxBufferLength - uxConsumedBufferLength,
                                                                      "\t%lu\t\t%lu%%\r\n",
                                                                      pxTaskStatusArray[ x ].ulRunTimeCounter,
                                                                      ulStatsAsPercentage );
                                 }
-                                #else
+                                #else /* ifdef portLU_PRINTF_SPECIFIER_REQUIRED */
                                 {
                                     /* sizeof( int ) == sizeof( long ) so a smaller
                                      * printf() library can be used. */
+                                    /* MISRA Ref 21.6.1 [snprintf for utility] */
+                                    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-216 */
+                                    /* coverity[misra_c_2012_rule_21_6_violation] */
                                     iSnprintfReturnValue = snprintf( pcWriteBuffer,
                                                                      uxBufferLength - uxConsumedBufferLength,
                                                                      "\t%u\t\t%u%%\r\n",
                                                                      ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter,
-                                                                     ( unsigned int ) ulStatsAsPercentage ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
+                                                                     ( unsigned int ) ulStatsAsPercentage );
                                 }
                                 #endif /* ifdef portLU_PRINTF_SPECIFIER_REQUIRED */
                             }
@@ -7520,6 +7532,9 @@ static void prvResetNextTaskUnblockTime( void )
                                  * consumed less than 1% of the total run time. */
                                 #ifdef portLU_PRINTF_SPECIFIER_REQUIRED
                                 {
+                                    /* MISRA Ref 21.6.1 [snprintf for utility] */
+                                    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-216 */
+                                    /* coverity[misra_c_2012_rule_21_6_violation] */
                                     iSnprintfReturnValue = snprintf( pcWriteBuffer,
                                                                      uxBufferLength - uxConsumedBufferLength,
                                                                      "\t%lu\t\t<1%%\r\n",
@@ -7529,10 +7544,13 @@ static void prvResetNextTaskUnblockTime( void )
                                 {
                                     /* sizeof( int ) == sizeof( long ) so a smaller
                                      * printf() library can be used. */
+                                    /* MISRA Ref 21.6.1 [snprintf for utility] */
+                                    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-216 */
+                                    /* coverity[misra_c_2012_rule_21_6_violation] */
                                     iSnprintfReturnValue = snprintf( pcWriteBuffer,
                                                                      uxBufferLength - uxConsumedBufferLength,
                                                                      "\t%u\t\t<1%%\r\n",
-                                                                     ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
+                                                                     ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter );
                                 }
                                 #endif /* ifdef portLU_PRINTF_SPECIFIER_REQUIRED */
                             }

From de2c0c1a9556c8b1ec9eb9ecc0fff72a129f23cb Mon Sep 17 00:00:00 2001
From: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Date: Thu, 7 Dec 2023 19:43:02 +0800
Subject: [PATCH 149/424] Update partner and community supported port submodule
 pointer (#919)

---
 portable/ThirdParty/Community-Supported-Ports | 2 +-
 portable/ThirdParty/Partner-Supported-Ports   | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/portable/ThirdParty/Community-Supported-Ports b/portable/ThirdParty/Community-Supported-Ports
index d4cccca29..f051e9bff 160000
--- a/portable/ThirdParty/Community-Supported-Ports
+++ b/portable/ThirdParty/Community-Supported-Ports
@@ -1 +1 @@
-Subproject commit d4cccca2971d6ffca581564f8142069cb854bd15
+Subproject commit f051e9bff812aa3c10c5417e064671a1c4eeb314
diff --git a/portable/ThirdParty/Partner-Supported-Ports b/portable/ThirdParty/Partner-Supported-Ports
index d38f59dbc..da0185fbf 160000
--- a/portable/ThirdParty/Partner-Supported-Ports
+++ b/portable/ThirdParty/Partner-Supported-Ports
@@ -1 +1 @@
-Subproject commit d38f59dbcdfabbe71361764e194e1ad6202f902c
+Subproject commit da0185fbf1215706af66d020a67edf912193979a

From db5df4bfde3ae0b306e63d9e912a4b0f78876e31 Mon Sep 17 00:00:00 2001
From: Soren Ptak <ptaksoren@gmail.com>
Date: Thu, 7 Dec 2023 11:16:33 -0500
Subject: [PATCH 150/424] Revert Portable/CodeWarrior formatting (#831)

Revert the formatting on CodeWarrior ports
---
 portable/CodeWarrior/ColdFire_V1/port.c      |  39 ++--
 portable/CodeWarrior/ColdFire_V1/portmacro.h |  53 ++---
 portable/CodeWarrior/ColdFire_V2/port.c      |  50 +++--
 portable/CodeWarrior/ColdFire_V2/portmacro.h |  52 ++---
 portable/CodeWarrior/HCS12/port.c            |  90 ++++-----
 portable/CodeWarrior/HCS12/portmacro.h       | 201 +++++++++----------
 6 files changed, 237 insertions(+), 248 deletions(-)

diff --git a/portable/CodeWarrior/ColdFire_V1/port.c b/portable/CodeWarrior/ColdFire_V1/port.c
index dd6d794e9..d9831384e 100644
--- a/portable/CodeWarrior/ColdFire_V1/port.c
+++ b/portable/CodeWarrior/ColdFire_V1/port.c
@@ -31,38 +31,35 @@
 #include "task.h"
 
 
-#define portINITIAL_FORMAT_VECTOR      ( ( StackType_t ) 0x4000 )
+#define portINITIAL_FORMAT_VECTOR       ( ( StackType_t ) 0x4000 )
 
 /* Supervisor mode set. */
-#define portINITIAL_STATUS_REGISTER    ( ( StackType_t ) 0x2000 )
+#define portINITIAL_STATUS_REGISTER     ( ( StackType_t ) 0x2000)
 
 /* The clock prescale into the timer peripheral. */
-#define portPRESCALE_VALUE             ( ( uint8_t ) 10 )
+#define portPRESCALE_VALUE              ( ( uint8_t ) 10 )
 
 /* The clock frequency into the RTC. */
-#define portRTC_CLOCK_HZ               ( ( uint32_t ) 1000 )
+#define portRTC_CLOCK_HZ                ( ( uint32_t ) 1000 )
 
 asm void interrupt VectorNumber_VL1swi vPortYieldISR( void );
 static void prvSetupTimerInterrupt( void );
 
 /* Used to keep track of the number of nested calls to taskENTER_CRITICAL().  This
- * will be set to 0 prior to the first task being started. */
+will be set to 0 prior to the first task being started. */
 static uint32_t ulCriticalNesting = 0x9999UL;
 
 /*-----------------------------------------------------------*/
 
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
 {
-    uint32_t ulOriginalA5;
 
-    __asm {
-        MOVE.L A5, ulOriginalA5
-    };
+uint32_t ulOriginalA5;
+
+    __asm{ MOVE.L A5, ulOriginalA5 };
 
 
-    *pxTopOfStack = ( StackType_t ) 0xDEADBEEF;
+    *pxTopOfStack = (StackType_t) 0xDEADBEEF;
     pxTopOfStack--;
 
     /* Exception stack frame starts with the return address. */
@@ -73,7 +70,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
     pxTopOfStack--;
 
     *pxTopOfStack = ( StackType_t ) 0x0; /*FP*/
-    pxTopOfStack -= 14;                  /* A5 to D0. */
+    pxTopOfStack -= 14; /* A5 to D0. */
 
     /* Parameter in A0. */
     *( pxTopOfStack + 8 ) = ( StackType_t ) pvParameters;
@@ -87,7 +84,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
 
 BaseType_t xPortStartScheduler( void )
 {
-    extern void vPortStartFirstTask( void );
+extern void vPortStartFirstTask( void );
 
     ulCriticalNesting = 0UL;
 
@@ -110,7 +107,7 @@ static void prvSetupTimerInterrupt( void )
     RTCMOD = portRTC_CLOCK_HZ / configTICK_RATE_HZ;
 
     /* Enable the RTC to generate interrupts - interrupts are already disabled
-     * when this code executes. */
+    when this code executes. */
     RTCSC_RTIE = 1;
 }
 /*-----------------------------------------------------------*/
@@ -126,20 +123,19 @@ void vPortEnterCritical( void )
     if( ulCriticalNesting == 0UL )
     {
         /* Guard against context switches being pended simultaneously with a
-         * critical section being entered. */
+        critical section being entered. */
         do
         {
             portDISABLE_INTERRUPTS();
-
             if( INTC_FRC == 0UL )
             {
                 break;
             }
 
             portENABLE_INTERRUPTS();
+
         } while( 1 );
     }
-
     ulCriticalNesting++;
 }
 /*-----------------------------------------------------------*/
@@ -147,7 +143,6 @@ void vPortEnterCritical( void )
 void vPortExitCritical( void )
 {
     ulCriticalNesting--;
-
     if( ulCriticalNesting == 0 )
     {
         portENABLE_INTERRUPTS();
@@ -157,7 +152,7 @@ void vPortExitCritical( void )
 
 void vPortYieldHandler( void )
 {
-    uint32_t ulSavedInterruptMask;
+uint32_t ulSavedInterruptMask;
 
     ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR();
     {
@@ -171,7 +166,7 @@ void vPortYieldHandler( void )
 
 void interrupt VectorNumber_Vrtc vPortTickISR( void )
 {
-    uint32_t ulSavedInterruptMask;
+uint32_t ulSavedInterruptMask;
 
     /* Clear the interrupt. */
     RTCSC |= RTCSC_RTIF_MASK;
diff --git a/portable/CodeWarrior/ColdFire_V1/portmacro.h b/portable/CodeWarrior/ColdFire_V1/portmacro.h
index d72637801..a98093d72 100644
--- a/portable/CodeWarrior/ColdFire_V1/portmacro.h
+++ b/portable/CodeWarrior/ColdFire_V1/portmacro.h
@@ -46,34 +46,34 @@
  */
 
 /* Type definitions. */
-#define portCHAR          char
-#define portFLOAT         float
-#define portDOUBLE        double
-#define portLONG          long
-#define portSHORT         short
-#define portSTACK_TYPE    uint32_t
-#define portBASE_TYPE     long
+#define portCHAR        char
+#define portFLOAT       float
+#define portDOUBLE      double
+#define portLONG        long
+#define portSHORT       short
+#define portSTACK_TYPE  uint32_t
+#define portBASE_TYPE   long
 
-typedef portSTACK_TYPE   StackType_t;
-typedef long             BaseType_t;
-typedef unsigned long    UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
 
 
-#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t     TickType_t;
-    #define portMAX_DELAY    ( TickType_t ) 0xffff
+#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t TickType_t;
+    #define portMAX_DELAY ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t     TickType_t;
-    #define portMAX_DELAY    ( TickType_t ) ( 0xFFFFFFFFUL )
+    typedef uint32_t TickType_t;
+    #define portMAX_DELAY ( TickType_t )    ( 0xFFFFFFFFUL )
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portBYTE_ALIGNMENT    4
-#define portSTACK_GROWTH      -1
-#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT          4
+#define portSTACK_GROWTH            -1
+#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
 /*-----------------------------------------------------------*/
 
 uint32_t ulPortSetIPL( uint32_t );
@@ -83,29 +83,30 @@ uint32_t ulPortSetIPL( uint32_t );
 
 extern void vPortEnterCritical( void );
 extern void vPortExitCritical( void );
-#define portENTER_CRITICAL()    vPortEnterCritical()
-#define portEXIT_CRITICAL()     vPortExitCritical()
+#define portENTER_CRITICAL()        vPortEnterCritical()
+#define portEXIT_CRITICAL()         vPortExitCritical()
 
 extern UBaseType_t uxPortSetInterruptMaskFromISR( void );
 extern void vPortClearInterruptMaskFromISR( UBaseType_t );
-#define portSET_INTERRUPT_MASK_FROM_ISR()                             ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY )
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister )    ulPortSetIPL( uxSavedStatusRegister )
+#define portSET_INTERRUPT_MASK_FROM_ISR()   ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) ulPortSetIPL( uxSavedStatusRegister )
 
 /*-----------------------------------------------------------*/
 
 /* Task utilities. */
-#define portNOP()      asm volatile ( "nop" )
+#define portNOP()   asm volatile ( "nop" )
 
 /* Context switches are requested using the force register. */
-#define portYIELD()    INTC_SFRC = 0x3E; portNOP(); portNOP(); portNOP(); portNOP(); portNOP()
+#define portYIELD() INTC_SFRC = 0x3E; portNOP(); portNOP(); portNOP(); portNOP(); portNOP()
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters ) __attribute__( ( noreturn ) )
-#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn))
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
 /*-----------------------------------------------------------*/
 
+
 #define portEND_SWITCHING_ISR( xSwitchRequired ) \
     do                                           \
     {                                            \
diff --git a/portable/CodeWarrior/ColdFire_V2/port.c b/portable/CodeWarrior/ColdFire_V2/port.c
index a7a78a7e9..5bca650fe 100644
--- a/portable/CodeWarrior/ColdFire_V2/port.c
+++ b/portable/CodeWarrior/ColdFire_V2/port.c
@@ -31,41 +31,39 @@
 #include "task.h"
 
 
-#define portINITIAL_FORMAT_VECTOR      ( ( StackType_t ) 0x4000 )
+#define portINITIAL_FORMAT_VECTOR       ( ( StackType_t ) 0x4000 )
 
 /* Supervisor mode set. */
-#define portINITIAL_STATUS_REGISTER    ( ( StackType_t ) 0x2000 )
+#define portINITIAL_STATUS_REGISTER     ( ( StackType_t ) 0x2000)
 
 /* Used to keep track of the number of nested calls to taskENTER_CRITICAL().  This
- * will be set to 0 prior to the first task being started. */
+will be set to 0 prior to the first task being started. */
 static uint32_t ulCriticalNesting = 0x9999UL;
 
 
-#define portSAVE_CONTEXT()         \
-    lea.l( -60, % sp ), % sp;      \
-    movem.l % d0 - % fp, ( % sp ); \
-    move.l pxCurrentTCB, % a0;     \
-    move.l % sp, ( % a0 );
+#define portSAVE_CONTEXT()              \
+    lea.l       (-60, %sp), %sp;        \
+    movem.l     %d0-%fp, (%sp);         \
+    move.l      pxCurrentTCB, %a0;      \
+    move.l      %sp, (%a0);
 
-#define portRESTORE_CONTEXT()     \
-    move.l pxCurrentTCB, % a0;    \
-    move.l( % a0 ), % sp;         \
-    movem.l( % sp ), % d0 - % fp; \
-    lea.l % sp@( 60 ), % sp;      \
+#define portRESTORE_CONTEXT()           \
+    move.l      pxCurrentTCB, %a0;      \
+    move.l      (%a0), %sp;             \
+    movem.l     (%sp), %d0-%fp;         \
+    lea.l       %sp@(60), %sp;          \
     rte
 
 
 
 /*-----------------------------------------------------------*/
 
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
 {
     *pxTopOfStack = ( StackType_t ) pvParameters;
     pxTopOfStack--;
 
-    *pxTopOfStack = ( StackType_t ) 0xDEADBEEF;
+    *pxTopOfStack = (StackType_t) 0xDEADBEEF;
     pxTopOfStack--;
 
     /* Exception stack frame starts with the return address. */
@@ -76,7 +74,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
     pxTopOfStack--;
 
     *pxTopOfStack = ( StackType_t ) 0x0; /*FP*/
-    pxTopOfStack -= 14;                  /* A5 to D0. */
+    pxTopOfStack -= 14; /* A5 to D0. */
 
     return pxTopOfStack;
 }
@@ -84,7 +82,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
 
 BaseType_t xPortStartScheduler( void )
 {
-    extern void vPortStartFirstTask( void );
+extern void vPortStartFirstTask( void );
 
     ulCriticalNesting = 0UL;
 
@@ -109,20 +107,19 @@ void vPortEnterCritical( void )
     if( ulCriticalNesting == 0UL )
     {
         /* Guard against context switches being pended simultaneously with a
-         * critical section being entered. */
+        critical section being entered. */
         do
         {
             portDISABLE_INTERRUPTS();
-
             if( MCF_INTC0_INTFRCH == 0UL )
             {
                 break;
             }
 
             portENABLE_INTERRUPTS();
+
         } while( 1 );
     }
-
     ulCriticalNesting++;
 }
 /*-----------------------------------------------------------*/
@@ -130,7 +127,6 @@ void vPortEnterCritical( void )
 void vPortExitCritical( void )
 {
     ulCriticalNesting--;
-
     if( ulCriticalNesting == 0 )
     {
         portENABLE_INTERRUPTS();
@@ -140,12 +136,12 @@ void vPortExitCritical( void )
 
 void vPortYieldHandler( void )
 {
-    uint32_t ulSavedInterruptMask;
+uint32_t ulSavedInterruptMask;
 
     ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR();
-    /* Note this will clear all forced interrupts - this is done for speed. */
-    MCF_INTC0_INTFRCL = 0;
-    vTaskSwitchContext();
+        /* Note this will clear all forced interrupts - this is done for speed. */
+        MCF_INTC0_INTFRCL = 0;
+        vTaskSwitchContext();
     portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask );
 }
 /*-----------------------------------------------------------*/
diff --git a/portable/CodeWarrior/ColdFire_V2/portmacro.h b/portable/CodeWarrior/ColdFire_V2/portmacro.h
index e367e0774..a59dff9dd 100644
--- a/portable/CodeWarrior/ColdFire_V2/portmacro.h
+++ b/portable/CodeWarrior/ColdFire_V2/portmacro.h
@@ -46,33 +46,33 @@
  */
 
 /* Type definitions. */
-#define portCHAR          char
-#define portFLOAT         float
-#define portDOUBLE        double
-#define portLONG          long
-#define portSHORT         short
-#define portSTACK_TYPE    uint32_t
-#define portBASE_TYPE     long
+#define portCHAR        char
+#define portFLOAT       float
+#define portDOUBLE      double
+#define portLONG        long
+#define portSHORT       short
+#define portSTACK_TYPE  uint32_t
+#define portBASE_TYPE   long
 
-typedef portSTACK_TYPE   StackType_t;
-typedef long             BaseType_t;
-typedef unsigned long    UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
 
-#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t     TickType_t;
-    #define portMAX_DELAY    ( TickType_t ) 0xffff
+#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t TickType_t;
+    #define portMAX_DELAY ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t     TickType_t;
-    #define portMAX_DELAY    ( TickType_t ) ( 0xFFFFFFFFUL )
+    typedef uint32_t TickType_t;
+    #define portMAX_DELAY ( TickType_t )    ( 0xFFFFFFFFUL )
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portBYTE_ALIGNMENT    4
-#define portSTACK_GROWTH      -1
-#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT          4
+#define portSTACK_GROWTH            -1
+#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
 /*-----------------------------------------------------------*/
 uint32_t ulPortSetIPL( uint32_t );
 #define portDISABLE_INTERRUPTS()    ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY )
@@ -81,28 +81,28 @@ uint32_t ulPortSetIPL( uint32_t );
 
 extern void vPortEnterCritical( void );
 extern void vPortExitCritical( void );
-#define portENTER_CRITICAL()    vPortEnterCritical()
-#define portEXIT_CRITICAL()     vPortExitCritical()
+#define portENTER_CRITICAL()        vPortEnterCritical()
+#define portEXIT_CRITICAL()         vPortExitCritical()
 
 extern UBaseType_t uxPortSetInterruptMaskFromISR( void );
 extern void vPortClearInterruptMaskFromISR( UBaseType_t );
-#define portSET_INTERRUPT_MASK_FROM_ISR()                             ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY )
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister )    ulPortSetIPL( uxSavedStatusRegister )
+#define portSET_INTERRUPT_MASK_FROM_ISR()   ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) ulPortSetIPL( uxSavedStatusRegister )
 
 /*-----------------------------------------------------------*/
 
 /* Task utilities. */
 
-#define portNOP()      asm volatile ( "nop" )
+#define portNOP()   asm volatile (  "nop" )
 
 /* Note this will overwrite all other bits in the force register, it is done this way for speed. */
-#define portYIELD()    MCF_INTC0_INTFRCL = ( 1UL << configYIELD_INTERRUPT_VECTOR ); portNOP(); portNOP()      /* -32 as we are using the high word of the 64bit mask. */
+#define portYIELD()         MCF_INTC0_INTFRCL = ( 1UL << configYIELD_INTERRUPT_VECTOR ); portNOP(); portNOP() /* -32 as we are using the high word of the 64bit mask. */
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters ) __attribute__( ( noreturn ) )
-#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn))
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
 /*-----------------------------------------------------------*/
 
 #define portEND_SWITCHING_ISR( xSwitchRequired ) \
diff --git a/portable/CodeWarrior/HCS12/port.c b/portable/CodeWarrior/HCS12/port.c
index 1b6f5c37d..e4876125a 100644
--- a/portable/CodeWarrior/HCS12/port.c
+++ b/portable/CodeWarrior/HCS12/port.c
@@ -32,8 +32,8 @@
 
 
 /*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the HCS12 port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the HCS12 port.
+ *----------------------------------------------------------*/
 
 
 /*
@@ -43,29 +43,29 @@
 static void prvSetupTimerInterrupt( void );
 
 /* Interrupt service routines have to be in non-banked memory - as does the
- * scheduler startup function. */
+scheduler startup function. */
 #pragma CODE_SEG __NEAR_SEG NON_BANKED
 
-/* Manual context switch function.  This is the SWI ISR. */
-void interrupt vPortYield( void );
+    /* Manual context switch function.  This is the SWI ISR. */
+    void interrupt vPortYield( void );
 
-/* Tick context switch function.  This is the timer ISR. */
-void interrupt vPortTickInterrupt( void );
+    /* Tick context switch function.  This is the timer ISR. */
+    void interrupt vPortTickInterrupt( void );
 
-/* Simply called by xPortStartScheduler().  xPortStartScheduler() does not
- * start the scheduler directly because the header file containing the
- * xPortStartScheduler() prototype is part of the common kernel code, and
- * therefore cannot use the CODE_SEG pragma. */
-static BaseType_t xBankedStartScheduler( void );
+    /* Simply called by xPortStartScheduler().  xPortStartScheduler() does not
+    start the scheduler directly because the header file containing the
+    xPortStartScheduler() prototype is part of the common kernel code, and
+    therefore cannot use the CODE_SEG pragma. */
+    static BaseType_t xBankedStartScheduler( void );
 
 #pragma CODE_SEG DEFAULT
 
 /* Calls to portENTER_CRITICAL() can be nested.  When they are nested the
- * critical section should not be left (i.e. interrupts should not be re-enabled)
- * until the nesting depth reaches 0.  This variable simply tracks the nesting
- * depth.  Each task maintains it's own critical nesting depth variable so
- * uxCriticalNesting is saved and restored from the task stack during a context
- * switch. */
+critical section should not be left (i.e. interrupts should not be re-enabled)
+until the nesting depth reaches 0.  This variable simply tracks the nesting
+depth.  Each task maintains it's own critical nesting depth variable so
+uxCriticalNesting is saved and restored from the task stack during a context
+switch. */
 volatile UBaseType_t uxCriticalNesting = 0xff;
 
 /*-----------------------------------------------------------*/
@@ -73,33 +73,31 @@ volatile UBaseType_t uxCriticalNesting = 0xff;
 /*
  * See header file for description.
  */
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
 {
     /*
-     *  Place a few bytes of known values on the bottom of the stack.
-     *  This can be uncommented to provide useful stack markers when debugging.
-     *
-     * pxTopOfStack = ( StackType_t ) 0x11;
-     *  pxTopOfStack--;
-     * pxTopOfStack = ( StackType_t ) 0x22;
-     *  pxTopOfStack--;
-     * pxTopOfStack = ( StackType_t ) 0x33;
-     *  pxTopOfStack--;
-     */
+        Place a few bytes of known values on the bottom of the stack.
+        This can be uncommented to provide useful stack markers when debugging.
+
+        *pxTopOfStack = ( StackType_t ) 0x11;
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) 0x22;
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) 0x33;
+        pxTopOfStack--;
+    */
 
 
 
     /* Setup the initial stack of the task.  The stack is set exactly as
-     * expected by the portRESTORE_CONTEXT() macro.  In this case the stack as
-     * expected by the HCS12 RTI instruction. */
+    expected by the portRESTORE_CONTEXT() macro.  In this case the stack as
+    expected by the HCS12 RTI instruction. */
 
 
     /* The address of the task function is placed in the stack byte at a time. */
-    *pxTopOfStack = ( StackType_t ) *( ( ( StackType_t * ) ( &pxCode ) ) + 1 );
+    *pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pxCode) ) + 1 );
     pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) *( ( ( StackType_t * ) ( &pxCode ) ) + 0 );
+    *pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pxCode) ) + 0 );
     pxTopOfStack--;
 
     /* Next are all the registers that form part of the task context. */
@@ -117,15 +115,15 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
     pxTopOfStack--;
 
     /* A register contains parameter high byte. */
-    *pxTopOfStack = ( StackType_t ) *( ( ( StackType_t * ) ( &pvParameters ) ) + 0 );
+    *pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pvParameters) ) + 0 );
     pxTopOfStack--;
 
     /* B register contains parameter low byte. */
-    *pxTopOfStack = ( StackType_t ) *( ( ( StackType_t * ) ( &pvParameters ) ) + 1 );
+    *pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pvParameters) ) + 1 );
     pxTopOfStack--;
 
     /* CCR: Note that when the task starts interrupts will be enabled since
-     * "I" bit of CCR is cleared */
+    "I" bit of CCR is cleared */
     *pxTopOfStack = ( StackType_t ) 0x00;
     pxTopOfStack--;
 
@@ -136,7 +134,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
     #endif
 
     /* Finally the critical nesting depth is initialised with 0 (not within
-     * a critical section). */
+    a critical section). */
     *pxTopOfStack = ( StackType_t ) 0x00;
 
     return pxTopOfStack;
@@ -159,10 +157,10 @@ static void prvSetupTimerInterrupt( void )
 BaseType_t xPortStartScheduler( void )
 {
     /* xPortStartScheduler() does not start the scheduler directly because
-     * the header file containing the xPortStartScheduler() prototype is part
-     * of the common kernel code, and therefore cannot use the CODE_SEG pragma.
-     * Instead it simply calls the locally defined xBankedStartScheduler() -
-     * which does use the CODE_SEG pragma. */
+    the header file containing the xPortStartScheduler() prototype is part
+    of the common kernel code, and therefore cannot use the CODE_SEG pragma.
+    Instead it simply calls the locally defined xBankedStartScheduler() -
+    which does use the CODE_SEG pragma. */
 
     return xBankedStartScheduler();
 }
@@ -173,7 +171,7 @@ BaseType_t xPortStartScheduler( void )
 static BaseType_t xBankedStartScheduler( void )
 {
     /* Configure the timer that will generate the RTOS tick.  Interrupts are
-     * disabled when this function is called. */
+    disabled when this function is called. */
     prvSetupTimerInterrupt();
 
     /* Restore the context of the first task. */
@@ -224,15 +222,15 @@ void interrupt vPortTickInterrupt( void )
         TFLG1 = 1;
 
         /* Restore the context of a task - which may be a different task
-         * to that interrupted. */
+        to that interrupted. */
         portRESTORE_CONTEXT();
     }
-    #else /* if configUSE_PREEMPTION == 1 */
+    #else
     {
         xTaskIncrementTick();
         TFLG1 = 1;
     }
-    #endif /* if configUSE_PREEMPTION == 1 */
+    #endif
 }
 
 #pragma CODE_SEG DEFAULT
diff --git a/portable/CodeWarrior/HCS12/portmacro.h b/portable/CodeWarrior/HCS12/portmacro.h
index f2f899346..d0d0a140e 100644
--- a/portable/CodeWarrior/HCS12/portmacro.h
+++ b/portable/CodeWarrior/HCS12/portmacro.h
@@ -41,40 +41,40 @@
  */
 
 /* Type definitions. */
-#define portCHAR          char
-#define portFLOAT         float
-#define portDOUBLE        double
-#define portLONG          long
-#define portSHORT         short
-#define portSTACK_TYPE    uint8_t
-#define portBASE_TYPE     char
+#define portCHAR        char
+#define portFLOAT       float
+#define portDOUBLE      double
+#define portLONG        long
+#define portSHORT       short
+#define portSTACK_TYPE  uint8_t
+#define portBASE_TYPE   char
 
-typedef portSTACK_TYPE   StackType_t;
-typedef signed char      BaseType_t;
-typedef unsigned char    UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef signed char BaseType_t;
+typedef unsigned char UBaseType_t;
 
-#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t     TickType_t;
-    #define portMAX_DELAY    ( TickType_t ) 0xffff
+#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t TickType_t;
+    #define portMAX_DELAY ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t     TickType_t;
-    #define portMAX_DELAY    ( TickType_t ) ( 0xFFFFFFFFUL )
+    typedef uint32_t TickType_t;
+    #define portMAX_DELAY ( TickType_t )    ( 0xFFFFFFFFUL )
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portBYTE_ALIGNMENT    1
-#define portSTACK_GROWTH      ( -1 )
-#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portYIELD()    __asm( "swi" );
-#define portNOP()      __asm( "nop" );
+#define portBYTE_ALIGNMENT          1
+#define portSTACK_GROWTH            ( -1 )
+#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portYIELD()                 __asm( "swi" );
+#define portNOP()                   __asm( "nop" );
 /*-----------------------------------------------------------*/
 
 /* Critical section handling. */
-#define portENABLE_INTERRUPTS()     __asm( "cli" )
-#define portDISABLE_INTERRUPTS()    __asm( "sei" )
+#define portENABLE_INTERRUPTS()             __asm( "cli" )
+#define portDISABLE_INTERRUPTS()            __asm( "sei" )
 
 /*
  * Disable interrupts before incrementing the count of critical section nesting.
@@ -82,29 +82,29 @@ typedef unsigned char    UBaseType_t;
  * re-enabled.  Once interrupts are disabled the nesting count can be accessed
  * directly.  Each task maintains its own nesting count.
  */
-#define portENTER_CRITICAL()                           \
-    {                                                  \
-        extern volatile UBaseType_t uxCriticalNesting; \
-                                                       \
-        portDISABLE_INTERRUPTS();                      \
-        uxCriticalNesting++;                           \
-    }
+#define portENTER_CRITICAL()                                    \
+{                                                               \
+    extern volatile UBaseType_t uxCriticalNesting;  \
+                                                                \
+    portDISABLE_INTERRUPTS();                                   \
+    uxCriticalNesting++;                                        \
+}
 
 /*
  * Interrupts are disabled so we can access the nesting count directly.  If the
  * nesting is found to be 0 (no nesting) then we are leaving the critical
  * section and interrupts can be re-enabled.
  */
-#define  portEXIT_CRITICAL()                           \
-    {                                                  \
-        extern volatile UBaseType_t uxCriticalNesting; \
-                                                       \
-        uxCriticalNesting--;                           \
-        if( uxCriticalNesting == 0 )                   \
-        {                                              \
-            portENABLE_INTERRUPTS();                   \
-        }                                              \
-    }
+#define  portEXIT_CRITICAL()                                    \
+{                                                               \
+    extern volatile UBaseType_t uxCriticalNesting;  \
+                                                                \
+    uxCriticalNesting--;                                        \
+    if( uxCriticalNesting == 0 )                                \
+    {                                                           \
+        portENABLE_INTERRUPTS();                                \
+    }                                                           \
+}
 /*-----------------------------------------------------------*/
 
 /* Task utilities. */
@@ -120,71 +120,70 @@ typedef unsigned char    UBaseType_t;
  */
 
 #ifdef BANKED_MODEL
-
-/*
- * Load the stack pointer for the task, then pull the critical nesting
- * count and PPAGE register from the stack.  The remains of the
- * context are restored by the RTI instruction.
- */
-    #define portRESTORE_CONTEXT()                      \
-    {                                                  \
-        extern volatile void * pxCurrentTCB;           \
-        extern volatile UBaseType_t uxCriticalNesting; \
-                                                       \
-        __asm( "ldx pxCurrentTCB" );                   \
-        __asm( "lds 0, x" );                           \
-        __asm( "pula" );                               \
-        __asm( "staa uxCriticalNesting" );             \
-        __asm( "pula" );                               \
-        __asm( "staa 0x30" ); /* 0x30 = PPAGE */       \
+    /*
+     * Load the stack pointer for the task, then pull the critical nesting
+     * count and PPAGE register from the stack.  The remains of the
+     * context are restored by the RTI instruction.
+     */
+    #define portRESTORE_CONTEXT()                                   \
+    {                                                               \
+        extern volatile void * pxCurrentTCB;                        \
+        extern volatile UBaseType_t uxCriticalNesting;  \
+                                                                    \
+        __asm( "ldx pxCurrentTCB" );                                \
+        __asm( "lds 0, x" );                                        \
+        __asm( "pula" );                                            \
+        __asm( "staa uxCriticalNesting" );                          \
+        __asm( "pula" );                                            \
+        __asm( "staa 0x30" ); /* 0x30 = PPAGE */                    \
     }
 
-/*
- * By the time this macro is called the processor has already stacked the
- * registers.  Simply stack the nesting count and PPAGE value, then save
- * the task stack pointer.
- */
-    #define portSAVE_CONTEXT()                         \
-    {                                                  \
-        extern volatile void * pxCurrentTCB;           \
-        extern volatile UBaseType_t uxCriticalNesting; \
-                                                       \
-        __asm( "ldaa 0x30" ); /* 0x30 = PPAGE */       \
-        __asm( "psha" );                               \
-        __asm( "ldaa uxCriticalNesting" );             \
-        __asm( "psha" );                               \
-        __asm( "ldx pxCurrentTCB" );                   \
-        __asm( "sts 0, x" );                           \
+    /*
+     * By the time this macro is called the processor has already stacked the
+     * registers.  Simply stack the nesting count and PPAGE value, then save
+     * the task stack pointer.
+     */
+    #define portSAVE_CONTEXT()                                      \
+    {                                                               \
+        extern volatile void * pxCurrentTCB;                        \
+        extern volatile UBaseType_t uxCriticalNesting;  \
+                                                                    \
+        __asm( "ldaa 0x30" );  /* 0x30 = PPAGE */                   \
+        __asm( "psha" );                                            \
+        __asm( "ldaa uxCriticalNesting" );                          \
+        __asm( "psha" );                                            \
+        __asm( "ldx pxCurrentTCB" );                                \
+        __asm( "sts 0, x" );                                        \
     }
-#else /* ifdef BANKED_MODEL */
+#else
 
-/*
- * These macros are as per the BANKED versions above, but without saving
- * and restoring the PPAGE register.
- */
+    /*
+     * These macros are as per the BANKED versions above, but without saving
+     * and restoring the PPAGE register.
+     */
 
-    #define portRESTORE_CONTEXT()                      \
-    {                                                  \
-        extern volatile void * pxCurrentTCB;           \
-        extern volatile UBaseType_t uxCriticalNesting; \
-                                                       \
-        __asm( "ldx pxCurrentTCB" );                   \
-        __asm( "lds 0, x" );                           \
-        __asm( "pula" );                               \
-        __asm( "staa uxCriticalNesting" );             \
+    #define portRESTORE_CONTEXT()                                   \
+    {                                                               \
+        extern volatile void * pxCurrentTCB;                        \
+        extern volatile UBaseType_t uxCriticalNesting;  \
+                                                                    \
+        __asm( "ldx pxCurrentTCB" );                                \
+        __asm( "lds 0, x" );                                        \
+        __asm( "pula" );                                            \
+        __asm( "staa uxCriticalNesting" );                          \
     }
 
-    #define portSAVE_CONTEXT()                         \
-    {                                                  \
-        extern volatile void * pxCurrentTCB;           \
-        extern volatile UBaseType_t uxCriticalNesting; \
-                                                       \
-        __asm( "ldaa uxCriticalNesting" );             \
-        __asm( "psha" );                               \
-        __asm( "ldx pxCurrentTCB" );                   \
-        __asm( "sts 0, x" );                           \
+    #define portSAVE_CONTEXT()                                      \
+    {                                                               \
+        extern volatile void * pxCurrentTCB;                        \
+        extern volatile UBaseType_t uxCriticalNesting;  \
+                                                                    \
+        __asm( "ldaa uxCriticalNesting" );                          \
+        __asm( "psha" );                                            \
+        __asm( "ldx pxCurrentTCB" );                                \
+        __asm( "sts 0, x" );                                        \
     }
-#endif /* ifdef BANKED_MODEL */
+#endif
 
 /*
  * Utility macro to call macros above in correct order in order to perform a
@@ -192,14 +191,14 @@ typedef unsigned char    UBaseType_t;
  * the ISR does not use any local (stack) variables.  If the ISR uses stack
  * variables portYIELD() should be used in it's place.
  */
-#define portTASK_SWITCH_FROM_ISR() \
-    portSAVE_CONTEXT();            \
-    vTaskSwitchContext();          \
+#define portTASK_SWITCH_FROM_ISR()                              \
+    portSAVE_CONTEXT();                                         \
+    vTaskSwitchContext();                                       \
     portRESTORE_CONTEXT();
 
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
 
 #endif /* PORTMACRO_H */

From 0debe8c6691da615320bb833da70a5c7aa7a91b0 Mon Sep 17 00:00:00 2001
From: Soren Ptak <ptaksoren@gmail.com>
Date: Thu, 7 Dec 2023 11:32:49 -0500
Subject: [PATCH 151/424] Revert Portable/Paradigm formatting (#830)

Revert the formatting on Paradigm ports
---
 .../Paradigm/Tern_EE/large_untested/port.c    | 84 +++++++++----------
 .../Paradigm/Tern_EE/large_untested/portasm.h | 56 ++++++-------
 .../Tern_EE/large_untested/portmacro.h        | 67 ++++++++-------
 portable/Paradigm/Tern_EE/small/port.c        | 78 ++++++++---------
 portable/Paradigm/Tern_EE/small/portasm.h     | 40 ++++-----
 portable/Paradigm/Tern_EE/small/portmacro.h   | 69 ++++++++-------
 6 files changed, 188 insertions(+), 206 deletions(-)

diff --git a/portable/Paradigm/Tern_EE/large_untested/port.c b/portable/Paradigm/Tern_EE/large_untested/port.c
index fdb275f2b..4ecffe01a 100644
--- a/portable/Paradigm/Tern_EE/large_untested/port.c
+++ b/portable/Paradigm/Tern_EE/large_untested/port.c
@@ -28,9 +28,9 @@
 
 
 /*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the Tern EE 186
-* port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the Tern EE 186
+ * port.
+ *----------------------------------------------------------*/
 
 /* Library includes. */
 #include <embedded.h>
@@ -42,29 +42,27 @@
 #include "portasm.h"
 
 /* The timer increments every four clocks, hence the divide by 4. */
-#define portTIMER_COMPARE                 ( uint16_t ) ( ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) / ( uint32_t ) 4 )
+#define portTIMER_COMPARE ( uint16_t ) ( ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) / ( uint32_t ) 4 )
 
 /* From the RDC data sheet. */
-#define portENABLE_TIMER_AND_INTERRUPT    ( uint16_t ) 0xe001
+#define portENABLE_TIMER_AND_INTERRUPT ( uint16_t ) 0xe001
 
 /* Interrupt control. */
-#define portEIO_REGISTER                  0xff22
-#define portCLEAR_INTERRUPT               0x0008
+#define portEIO_REGISTER 0xff22
+#define portCLEAR_INTERRUPT 0x0008
 
 /* Setup the hardware to generate the required tick frequency. */
 static void prvSetupTimerInterrupt( void );
 
 /* The ISR used depends on whether the preemptive or cooperative scheduler
- * is being used. */
-#if ( configUSE_PREEMPTION == 1 )
-
-/* Tick service routine used by the scheduler when preemptive scheduling is
- * being used. */
+is being used. */
+#if( configUSE_PREEMPTION == 1 )
+    /* Tick service routine used by the scheduler when preemptive scheduling is
+    being used. */
     static void __interrupt __far prvPreemptiveTick( void );
 #else
-
-/* Tick service routine used by the scheduler when cooperative scheduling is
- * being used. */
+    /* Tick service routine used by the scheduler when cooperative scheduling is
+    being used. */
     static void __interrupt __far prvNonPreemptiveTick( void );
 #endif
 
@@ -72,20 +70,18 @@ static void prvSetupTimerInterrupt( void );
 static void __interrupt __far prvYieldProcessor( void );
 
 /* The timer initialisation functions leave interrupts enabled,
- * which is not what we want.  This ISR is installed temporarily in case
- * the timer fires before we get a change to disable interrupts again. */
+which is not what we want.  This ISR is installed temporarily in case
+the timer fires before we get a change to disable interrupts again. */
 static void __interrupt __far prvDummyISR( void );
 
 /*-----------------------------------------------------------*/
 /* See header file for description. */
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
 {
-    StackType_t DS_Reg = 0;
+StackType_t DS_Reg = 0;
 
     /* Place a few bytes of known values on the bottom of the stack.
-     * This is just useful for debugging. */
+    This is just useful for debugging. */
 
     *pxTopOfStack = 0x1111;
     pxTopOfStack--;
@@ -95,8 +91,8 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
     pxTopOfStack--;
 
     /* We are going to start the scheduler using a return from interrupt
-     * instruction to load the program counter, so first there would be the
-     * function call with parameters preamble. */
+    instruction to load the program counter, so first there would be the
+    function call with parameters preamble. */
 
     *pxTopOfStack = FP_SEG( pvParameters );
     pxTopOfStack--;
@@ -116,8 +112,8 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
     pxTopOfStack--;
 
     /* The remaining registers would be pushed on the stack by our context
-     * switch function.  These are loaded with values simply to make debugging
-     * easier. */
+    switch function.  These are loaded with values simply to make debugging
+    easier. */
     *pxTopOfStack = ( StackType_t ) 0xAAAA; /* AX */
     pxTopOfStack--;
     *pxTopOfStack = ( StackType_t ) 0xBBBB; /* BX */
@@ -130,11 +126,9 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
     pxTopOfStack--;
 
     /* We need the true data segment. */
-    __asm {
-        MOV DS_Reg, DS
-    };
+    __asm{  MOV DS_Reg, DS };
 
-    *pxTopOfStack = DS_Reg;                 /* DS */
+    *pxTopOfStack = DS_Reg;                     /* DS */
     pxTopOfStack--;
     *pxTopOfStack = ( StackType_t ) 0x0123; /* SI */
     pxTopOfStack--;
@@ -151,7 +145,7 @@ BaseType_t xPortStartScheduler( void )
     /* This is called with interrupts already disabled. */
 
     /* Put our manual switch (yield) function on a known
-     * vector. */
+    vector. */
     setvect( portSWITCH_INT_NUMBER, prvYieldProcessor );
 
     /* Setup the tick interrupt. */
@@ -168,15 +162,15 @@ BaseType_t xPortStartScheduler( void )
 static void __interrupt __far prvDummyISR( void )
 {
     /* The timer initialisation functions leave interrupts enabled,
-     * which is not what we want.  This ISR is installed temporarily in case
-     * the timer fires before we get a change to disable interrupts again. */
+    which is not what we want.  This ISR is installed temporarily in case
+    the timer fires before we get a change to disable interrupts again. */
     outport( portEIO_REGISTER, portCLEAR_INTERRUPT );
 }
 /*-----------------------------------------------------------*/
 
 /* The ISR used depends on whether the preemptive or cooperative scheduler
- * is being used. */
-#if ( configUSE_PREEMPTION == 1 )
+is being used. */
+#if( configUSE_PREEMPTION == 1 )
     static void __interrupt __far prvPreemptiveTick( void )
     {
         /* Get the scheduler to update the task states following the tick. */
@@ -189,17 +183,17 @@ static void __interrupt __far prvDummyISR( void )
         /* Reset interrupt. */
         outport( portEIO_REGISTER, portCLEAR_INTERRUPT );
     }
-#else /* if ( configUSE_PREEMPTION == 1 ) */
+#else
     static void __interrupt __far prvNonPreemptiveTick( void )
     {
         /* Same as preemptive tick, but the cooperative scheduler is being used
-         * so we don't have to switch in the context of the next task. */
+        so we don't have to switch in the context of the next task. */
         xTaskIncrementTick();
 
         /* Reset interrupt. */
         outport( portEIO_REGISTER, portCLEAR_INTERRUPT );
     }
-#endif /* if ( configUSE_PREEMPTION == 1 ) */
+#endif
 /*-----------------------------------------------------------*/
 
 static void __interrupt __far prvYieldProcessor( void )
@@ -217,25 +211,23 @@ void vPortEndScheduler( void )
 
 static void prvSetupTimerInterrupt( void )
 {
-    const uint16_t usTimerACompare = portTIMER_COMPARE, usTimerAMode = portENABLE_TIMER_AND_INTERRUPT;
-    const uint16_t usT2_IRQ = 0x13;
+const uint16_t usTimerACompare = portTIMER_COMPARE, usTimerAMode = portENABLE_TIMER_AND_INTERRUPT;
+const uint16_t usT2_IRQ = 0x13;
 
     /* Configure the timer, the dummy handler is used here as the init
-     * function leaves interrupts enabled. */
+    function leaves interrupts enabled. */
     t2_init( usTimerAMode, usTimerACompare, prvDummyISR );
 
     /* Disable interrupts again before installing the real handlers. */
     portDISABLE_INTERRUPTS();
 
-    #if ( configUSE_PREEMPTION == 1 )
-
+    #if( configUSE_PREEMPTION == 1 )
         /* Tick service routine used by the scheduler when preemptive scheduling is
-         * being used. */
+        being used. */
         setvect( usT2_IRQ, prvPreemptiveTick );
     #else
-
         /* Tick service routine used by the scheduler when cooperative scheduling is
-         * being used. */
+        being used. */
         setvect( usT2_IRQ, prvNonPreemptiveTick );
     #endif
 }
diff --git a/portable/Paradigm/Tern_EE/large_untested/portasm.h b/portable/Paradigm/Tern_EE/large_untested/portasm.h
index e0321a8b0..c3c7456a3 100644
--- a/portable/Paradigm/Tern_EE/large_untested/portasm.h
+++ b/portable/Paradigm/Tern_EE/large_untested/portasm.h
@@ -44,32 +44,32 @@ void portSWITCH_CONTEXT( void );
  */
 void portFIRST_CONTEXT( void );
 
-#define portSWITCH_CONTEXT()                                                              \
-    asm { mov ax, seg pxCurrentTCB }                                                      \
-    asm { mov ds, ax }                                                                    \
-    asm { les bx, pxCurrentTCB } /* Save the stack pointer into the TCB. */               \
-    asm { mov es : 0x2[ bx ], ss }                                                        \
-    asm { mov es:[ bx ], sp }                                                                      \
-    asm { call far ptr vTaskSwitchContext } /* Perform the switch. */                     \
-    asm { mov ax, seg pxCurrentTCB }        /* Restore the stack pointer from the TCB. */ \
-    asm { mov ds, ax }                                                                    \
-    asm { les bx, dword ptr pxCurrentTCB }                                                \
-    asm { mov ss, es:[ bx + 2 ] }                                                                      \
-    asm { mov sp, es:[ bx ] }
+#define portSWITCH_CONTEXT()                                         \
+                        asm { mov   ax, seg pxCurrentTCB        } \
+                            asm { mov   ds, ax                      }  \
+                            asm { les   bx, pxCurrentTCB            }   /* Save the stack pointer into the TCB. */    \
+                            asm { mov   es:0x2[ bx ], ss            }   \
+                            asm { mov   es:[ bx ], sp               }   \
+                            asm { call  far ptr vTaskSwitchContext  }   /* Perform the switch. */   \
+                            asm { mov   ax, seg pxCurrentTCB        }   /* Restore the stack pointer from the TCB. */  \
+                            asm { mov   ds, ax                      }   \
+                            asm { les   bx, dword ptr pxCurrentTCB  }   \
+                            asm { mov   ss, es:[ bx + 2 ]           }      \
+                            asm { mov   sp, es:[ bx ]               }
 
-#define portFIRST_CONTEXT()                \
-    asm { mov ax, seg pxCurrentTCB }       \
-    asm { mov ds, ax }                     \
-    asm { les bx, dword ptr pxCurrentTCB } \
-    asm { mov ss, es:[ bx + 2 ] }                       \
-    asm { mov sp, es:[ bx ] }                           \
-    asm { pop bp }                         \
-    asm { pop di }                         \
-    asm { pop si }                         \
-    asm { pop ds }                         \
-    asm { pop es }                         \
-    asm { pop dx }                         \
-    asm { pop cx }                         \
-    asm { pop bx }                         \
-    asm { pop ax }                         \
-    asm { iret }
+#define portFIRST_CONTEXT()                                             \
+                            asm { mov   ax, seg pxCurrentTCB        }   \
+                            asm { mov   ds, ax                      }   \
+                            asm { les   bx, dword ptr pxCurrentTCB  }   \
+                            asm { mov   ss, es:[ bx + 2 ]           }   \
+                            asm { mov   sp, es:[ bx ]               }   \
+                            asm { pop   bp                          }   \
+                            asm { pop   di                          }   \
+                            asm { pop   si                          }   \
+                            asm { pop   ds                          }   \
+                            asm { pop   es                          }   \
+                            asm { pop   dx                          }   \
+                            asm { pop   cx                          }   \
+                            asm { pop   bx                          }   \
+                            asm { pop   ax                          }   \
+                            asm { iret                              }
diff --git a/portable/Paradigm/Tern_EE/large_untested/portmacro.h b/portable/Paradigm/Tern_EE/large_untested/portmacro.h
index 2027213a1..292c9e260 100644
--- a/portable/Paradigm/Tern_EE/large_untested/portmacro.h
+++ b/portable/Paradigm/Tern_EE/large_untested/portmacro.h
@@ -46,24 +46,24 @@
  */
 
 /* Type definitions. */
-#define portCHAR          char
-#define portFLOAT         float
-#define portDOUBLE        long
-#define portLONG          long
-#define portSHORT         int
-#define portSTACK_TYPE    uint16_t
-#define portBASE_TYPE     short
+#define portCHAR        char
+#define portFLOAT       float
+#define portDOUBLE      long
+#define portLONG        long
+#define portSHORT       int
+#define portSTACK_TYPE  uint16_t
+#define portBASE_TYPE   short
 
-typedef portSTACK_TYPE   StackType_t;
-typedef short            BaseType_t;
-typedef unsigned short   UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef short BaseType_t;
+typedef unsigned short UBaseType_t;
 
 
-#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t     TickType_t;
-    #define portMAX_DELAY    ( TickType_t ) 0xffff
-#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t     TickType_t;
+#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t TickType_t;
+    #define portMAX_DELAY ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS  == TICK_TYPE_WIDTH_32_BITS )
+    typedef uint32_t             TickType_t;
     #define portMAX_DELAY    ( TickType_t ) 0xffffffffUL
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -71,37 +71,36 @@ typedef unsigned short   UBaseType_t;
 /*-----------------------------------------------------------*/
 
 /* Critical section handling. */
-#define portENTER_CRITICAL() \
-    __asm { pushf }          \
-    __asm { cli }            \
+#define portENTER_CRITICAL()            __asm{ pushf }  \
+                                        __asm{ cli   }  \
 
-#define portEXIT_CRITICAL()         __asm { popf }
+#define portEXIT_CRITICAL()             __asm{ popf }
 
-#define portDISABLE_INTERRUPTS()    __asm { cli }
+#define portDISABLE_INTERRUPTS()        __asm{ cli }
 
-#define portENABLE_INTERRUPTS()     __asm { sti }
+#define portENABLE_INTERRUPTS()         __asm{ sti }
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portNOP()      __asm { nop }
-#define portSTACK_GROWTH         ( -1 )
-#define portSWITCH_INT_NUMBER    0x80
-#define portYIELD()    __asm { int portSWITCH_INT_NUMBER }
-#define portTICK_PERIOD_MS       ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT       2
-#define portINITIAL_SW           ( ( portSTACK_TYPE ) 0x0202 )          /* Start the tasks with interrupts enabled. */
+#define portNOP()                       __asm{ nop }
+#define portSTACK_GROWTH                ( -1 )
+#define portSWITCH_INT_NUMBER           0x80
+#define portYIELD()                     __asm{ int portSWITCH_INT_NUMBER }
+#define portTICK_PERIOD_MS              ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT              2
+#define portINITIAL_SW                  ( ( portSTACK_TYPE ) 0x0202 )   /* Start the tasks with interrupts enabled. */
 /*-----------------------------------------------------------*/
 
 /* Compiler specifics. */
-#define portINPUT_BYTE( xAddr )              inp( xAddr )
-#define portOUTPUT_BYTE( xAddr, ucValue )    outp( xAddr, ucValue )
-#define portINPUT_WORD( xAddr )              inpw( xAddr )
-#define portOUTPUT_WORD( xAddr, usValue )    outpw( xAddr, usValue )
+#define portINPUT_BYTE( xAddr )             inp( xAddr )
+#define portOUTPUT_BYTE( xAddr, ucValue )   outp( xAddr, ucValue )
+#define portINPUT_WORD( xAddr )             inpw( xAddr )
+#define portOUTPUT_WORD( xAddr, usValue )   outpw( xAddr, usValue )
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vTaskFunction, vParameters )    void vTaskFunction( void * pvParameters )
-#define portTASK_FUNCTION( vTaskFunction, vParameters )          void vTaskFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters )
+#define portTASK_FUNCTION( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters )
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/Paradigm/Tern_EE/small/port.c b/portable/Paradigm/Tern_EE/small/port.c
index 6d27ba991..2a1c0d962 100644
--- a/portable/Paradigm/Tern_EE/small/port.c
+++ b/portable/Paradigm/Tern_EE/small/port.c
@@ -28,9 +28,9 @@
 
 
 /*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the Tern EE 186
-* port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the Tern EE 186
+ * port.
+ *----------------------------------------------------------*/
 
 /* Library includes. */
 #include <embedded.h>
@@ -42,31 +42,29 @@
 #include "portasm.h"
 
 /* The timer increments every four clocks, hence the divide by 4. */
-#define portPRESCALE_VALUE                ( 16 )
-#define portTIMER_COMPARE                 ( configCPU_CLOCK_HZ / ( configTICK_RATE_HZ * 4UL ) )
+#define portPRESCALE_VALUE ( 16 )
+#define portTIMER_COMPARE ( configCPU_CLOCK_HZ  / ( configTICK_RATE_HZ * 4UL ) )
 
 /* From the RDC data sheet. */
-#define portENABLE_TIMER_AND_INTERRUPT    ( uint16_t ) 0xe00b
-#define portENABLE_TIMER                  ( uint16_t ) 0xC001
+#define portENABLE_TIMER_AND_INTERRUPT  ( uint16_t ) 0xe00b
+#define portENABLE_TIMER                ( uint16_t ) 0xC001
 
 /* Interrupt control. */
-#define portEIO_REGISTER                  0xff22
-#define portCLEAR_INTERRUPT               0x0008
+#define portEIO_REGISTER 0xff22
+#define portCLEAR_INTERRUPT 0x0008
 
 /* Setup the hardware to generate the required tick frequency. */
 static void prvSetupTimerInterrupt( void );
 
 /* The ISR used depends on whether the preemptive or cooperative scheduler
- * is being used. */
-#if ( configUSE_PREEMPTION == 1 )
-
-/* Tick service routine used by the scheduler when preemptive scheduling is
- * being used. */
+is being used. */
+#if( configUSE_PREEMPTION == 1 )
+    /* Tick service routine used by the scheduler when preemptive scheduling is
+    being used. */
     static void __interrupt __far prvPreemptiveTick( void );
 #else
-
-/* Tick service routine used by the scheduler when cooperative scheduling is
- * being used. */
+    /* Tick service routine used by the scheduler when cooperative scheduling is
+    being used. */
     static void __interrupt __far prvNonPreemptiveTick( void );
 #endif
 
@@ -75,19 +73,15 @@ static void __interrupt __far prvYieldProcessor( void );
 
 /*-----------------------------------------------------------*/
 /* See header file for description. */
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
 {
-    StackType_t DS_Reg = 0;
+StackType_t DS_Reg = 0;
 
     /* We need the true data segment. */
-    __asm {
-        MOV DS_Reg, DS
-    };
+    __asm{  MOV DS_Reg, DS };
 
     /* Place a few bytes of known values on the bottom of the stack.
-     * This is just useful for debugging. */
+    This is just useful for debugging. */
 
     *pxTopOfStack = 0x1111;
     pxTopOfStack--;
@@ -97,8 +91,8 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
     pxTopOfStack--;
 
     /* We are going to start the scheduler using a return from interrupt
-     * instruction to load the program counter, so first there would be the
-     * function call with parameters preamble. */
+    instruction to load the program counter, so first there would be the
+    function call with parameters preamble. */
 
     *pxTopOfStack = FP_OFF( pvParameters );
     pxTopOfStack--;
@@ -114,8 +108,8 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
     pxTopOfStack--;
 
     /* The remaining registers would be pushed on the stack by our context
-     * switch function.  These are loaded with values simply to make debugging
-     * easier. */
+    switch function.  These are loaded with values simply to make debugging
+    easier. */
     *pxTopOfStack = ( StackType_t ) 0xAAAA; /* AX */
     pxTopOfStack--;
     *pxTopOfStack = ( StackType_t ) 0xBBBB; /* BX */
@@ -127,7 +121,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
     *pxTopOfStack = ( StackType_t ) 0xEEEE; /* ES */
     pxTopOfStack--;
 
-    *pxTopOfStack = DS_Reg;                 /* DS */
+    *pxTopOfStack = DS_Reg;                     /* DS */
     pxTopOfStack--;
     *pxTopOfStack = ( StackType_t ) 0x0123; /* SI */
     pxTopOfStack--;
@@ -144,7 +138,7 @@ BaseType_t xPortStartScheduler( void )
     /* This is called with interrupts already disabled. */
 
     /* Put our manual switch (yield) function on a known
-     * vector. */
+    vector. */
     setvect( portSWITCH_INT_NUMBER, prvYieldProcessor );
 
     /* Setup the tick interrupt. */
@@ -159,8 +153,8 @@ BaseType_t xPortStartScheduler( void )
 /*-----------------------------------------------------------*/
 
 /* The ISR used depends on whether the preemptive or cooperative scheduler
- * is being used. */
-#if ( configUSE_PREEMPTION == 1 )
+is being used. */
+#if( configUSE_PREEMPTION == 1 )
     static void __interrupt __far prvPreemptiveTick( void )
     {
         /* Get the scheduler to update the task states following the tick. */
@@ -173,17 +167,17 @@ BaseType_t xPortStartScheduler( void )
         /* Reset interrupt. */
         outport( portEIO_REGISTER, portCLEAR_INTERRUPT );
     }
-#else /* if ( configUSE_PREEMPTION == 1 ) */
+#else
     static void __interrupt __far prvNonPreemptiveTick( void )
     {
         /* Same as preemptive tick, but the cooperative scheduler is being used
-         * so we don't have to switch in the context of the next task. */
+        so we don't have to switch in the context of the next task. */
         xTaskIncrementTick();
 
         /* Reset interrupt. */
         outport( portEIO_REGISTER, portCLEAR_INTERRUPT );
     }
-#endif /* if ( configUSE_PREEMPTION == 1 ) */
+#endif
 /*-----------------------------------------------------------*/
 
 static void __interrupt __far prvYieldProcessor( void )
@@ -201,21 +195,19 @@ void vPortEndScheduler( void )
 
 static void prvSetupTimerInterrupt( void )
 {
-    const uint32_t ulCompareValue = portTIMER_COMPARE;
-    uint16_t usTimerCompare;
+const uint32_t ulCompareValue = portTIMER_COMPARE;
+uint16_t usTimerCompare;
 
     usTimerCompare = ( uint16_t ) ( ulCompareValue >> 4 );
     t2_init( portENABLE_TIMER, portPRESCALE_VALUE, NULL );
 
-    #if ( configUSE_PREEMPTION == 1 )
-
+    #if( configUSE_PREEMPTION == 1 )
         /* Tick service routine used by the scheduler when preemptive scheduling is
-         * being used. */
+        being used. */
         t1_init( portENABLE_TIMER_AND_INTERRUPT, usTimerCompare, usTimerCompare, prvPreemptiveTick );
     #else
-
         /* Tick service routine used by the scheduler when cooperative scheduling is
-         * being used. */
+        being used. */
         t1_init( portENABLE_TIMER_AND_INTERRUPT, usTimerCompare, usTimerCompare, prvNonPreemptiveTick );
     #endif
 }
diff --git a/portable/Paradigm/Tern_EE/small/portasm.h b/portable/Paradigm/Tern_EE/small/portasm.h
index 2acba2443..930da20b0 100644
--- a/portable/Paradigm/Tern_EE/small/portasm.h
+++ b/portable/Paradigm/Tern_EE/small/portasm.h
@@ -47,26 +47,26 @@ void portEND_SWITCHING_ISR( void );
  */
 void portFIRST_CONTEXT( void );
 
-#define portEND_SWITCHING_ISR()             \
-    asm { mov bx, [ pxCurrentTCB ] }        \
-    asm { mov word ptr[ bx ], sp }          \
-    asm { call far ptr vTaskSwitchContext } \
-    asm { mov bx, [ pxCurrentTCB ] }        \
-    asm { mov sp, [ bx ] }
+#define portEND_SWITCHING_ISR()                                         \
+                            asm { mov   bx, [pxCurrentTCB]          }   \
+                            asm { mov   word ptr [bx], sp           }   \
+                            asm { call  far ptr vTaskSwitchContext  }   \
+                            asm { mov   bx, [pxCurrentTCB]          }   \
+                            asm { mov   sp, [bx]                    }
 
-#define portFIRST_CONTEXT()          \
-    asm { mov bx, [ pxCurrentTCB ] } \
-    asm { mov sp, [ bx ] }           \
-    asm { pop bp }                   \
-    asm { pop di }                   \
-    asm { pop si }                   \
-    asm { pop ds }                   \
-    asm { pop es }                   \
-    asm { pop dx }                   \
-    asm { pop cx }                   \
-    asm { pop bx }                   \
-    asm { pop ax }                   \
-    asm { iret }
+#define portFIRST_CONTEXT()                                         \
+                            asm { mov   bx, [pxCurrentTCB]          }   \
+                            asm { mov   sp, [bx]                    }   \
+                            asm { pop   bp                          }   \
+                            asm { pop   di                          }   \
+                            asm { pop   si                          }   \
+                            asm { pop   ds                          }   \
+                            asm { pop   es                          }   \
+                            asm { pop   dx                          }   \
+                            asm { pop   cx                          }   \
+                            asm { pop   bx                          }   \
+                            asm { pop   ax                          }   \
+                            asm { iret                              }
 
 
-#endif /* ifndef PORT_ASM_H */
+#endif
diff --git a/portable/Paradigm/Tern_EE/small/portmacro.h b/portable/Paradigm/Tern_EE/small/portmacro.h
index 393e6faa5..ff0b34b20 100644
--- a/portable/Paradigm/Tern_EE/small/portmacro.h
+++ b/portable/Paradigm/Tern_EE/small/portmacro.h
@@ -46,26 +46,26 @@
  */
 
 /* Type definitions. */
-#define portCHAR          char
-#define portFLOAT         float
-#define portDOUBLE        long
-#define portLONG          long
-#define portSHORT         int
-#define portSTACK_TYPE    uint16_t
-#define portBASE_TYPE     short
+#define portCHAR        char
+#define portFLOAT       float
+#define portDOUBLE      long
+#define portLONG        long
+#define portSHORT       int
+#define portSTACK_TYPE  uint16_t
+#define portBASE_TYPE   short
 
-typedef portSTACK_TYPE   StackType_t;
-typedef short            BaseType_t;
-typedef unsigned short   UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef short BaseType_t;
+typedef unsigned short UBaseType_t;
 
 
-typedef void ( __interrupt __far * pxISR )();
+typedef void ( __interrupt __far *pxISR )();
 
-#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t   TickType_t;
-    #define portMAX_DELAY    ( TickType_t ) 0xffff
-#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t   TickType_t;
+#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t TickType_t;
+    #define portMAX_DELAY ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS  == TICK_TYPE_WIDTH_32_BITS )
+    typedef uint32_t             TickType_t;
     #define portMAX_DELAY    ( TickType_t ) 0xffffffffUL
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -73,37 +73,36 @@ typedef void ( __interrupt __far * pxISR )();
 /*-----------------------------------------------------------*/
 
 /* Critical section handling. */
-#define portENTER_CRITICAL() \
-    __asm { pushf }          \
-    __asm { cli }            \
+#define portENTER_CRITICAL()            __asm{ pushf }  \
+                                        __asm{ cli   }  \
 
-#define portEXIT_CRITICAL()         __asm { popf }
+#define portEXIT_CRITICAL()             __asm{ popf }
 
-#define portDISABLE_INTERRUPTS()    __asm { cli }
+#define portDISABLE_INTERRUPTS()        __asm{ cli }
 
-#define portENABLE_INTERRUPTS()     __asm { sti }
+#define portENABLE_INTERRUPTS()         __asm{ sti }
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portNOP()      __asm { nop }
-#define portSTACK_GROWTH         ( -1 )
-#define portSWITCH_INT_NUMBER    0x80
-#define portYIELD()    __asm { int portSWITCH_INT_NUMBER }
-#define portTICK_PERIOD_MS       ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT       2
-#define portINITIAL_SW           ( ( portSTACK_TYPE ) 0x0202 )          /* Start the tasks with interrupts enabled. */
+#define portNOP()                       __asm{ nop }
+#define portSTACK_GROWTH                ( -1 )
+#define portSWITCH_INT_NUMBER           0x80
+#define portYIELD()                     __asm{ int portSWITCH_INT_NUMBER }
+#define portTICK_PERIOD_MS              ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT              2
+#define portINITIAL_SW                  ( ( portSTACK_TYPE ) 0x0202 )   /* Start the tasks with interrupts enabled. */
 /*-----------------------------------------------------------*/
 
 /* Compiler specifics. */
-#define portINPUT_BYTE( xAddr )              inp( xAddr )
-#define portOUTPUT_BYTE( xAddr, ucValue )    outp( xAddr, ucValue )
-#define portINPUT_WORD( xAddr )              inpw( xAddr )
-#define portOUTPUT_WORD( xAddr, usValue )    outpw( xAddr, usValue )
+#define portINPUT_BYTE( xAddr )             inp( xAddr )
+#define portOUTPUT_BYTE( xAddr, ucValue )   outp( xAddr, ucValue )
+#define portINPUT_WORD( xAddr )             inpw( xAddr )
+#define portOUTPUT_WORD( xAddr, usValue )   outpw( xAddr, usValue )
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vTaskFunction, vParameters )    void vTaskFunction( void * pvParameters )
-#define portTASK_FUNCTION( vTaskFunction, vParameters )          void vTaskFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters )
+#define portTASK_FUNCTION( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters )
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus

From bcf7bdaa13c38cee1de25fdce4426a6b0b3c3c88 Mon Sep 17 00:00:00 2001
From: Soren Ptak <ptaksoren@gmail.com>
Date: Thu, 7 Dec 2023 11:40:50 -0500
Subject: [PATCH 152/424] Revert Portable/oWatcom formatting (#829)

Revert the formatting on oWatcom ports
---
 portable/oWatcom/16BitDOS/Flsh186/port.c      | 101 ++++++-------
 portable/oWatcom/16BitDOS/Flsh186/portmacro.h |  58 ++++----
 portable/oWatcom/16BitDOS/PC/port.c           | 140 +++++++++---------
 portable/oWatcom/16BitDOS/PC/portmacro.h      |  60 ++++----
 portable/oWatcom/16BitDOS/common/portasm.h    | 106 ++++++-------
 portable/oWatcom/16BitDOS/common/portcomn.c   |  79 +++++-----
 6 files changed, 264 insertions(+), 280 deletions(-)

diff --git a/portable/oWatcom/16BitDOS/Flsh186/port.c b/portable/oWatcom/16BitDOS/Flsh186/port.c
index 03feb21e6..cc8863d1d 100644
--- a/portable/oWatcom/16BitDOS/Flsh186/port.c
+++ b/portable/oWatcom/16BitDOS/Flsh186/port.c
@@ -27,27 +27,27 @@
  */
 
 /*
- * Changes from V1.00:
- *
- + Call to taskYIELD() from within tick ISR has been replaced by the more
- +    efficient portSWITCH_CONTEXT().
- + ISR function definitions renamed to include the prv prefix.
- +
- + Changes from V1.2.0:
- +
- + portRESET_PIC() is now called last thing before the end of the preemptive
- +    tick routine.
- +
- + Changes from V2.6.1
- +
- + Replaced the sUsingPreemption variable with the configUSE_PREEMPTION
- +    macro to be consistent with the later ports.
- */
+Changes from V1.00:
+
+    + Call to taskYIELD() from within tick ISR has been replaced by the more
+      efficient portSWITCH_CONTEXT().
+    + ISR function definitions renamed to include the prv prefix.
+
+Changes from V1.2.0:
+
+    + portRESET_PIC() is now called last thing before the end of the preemptive
+      tick routine.
+
+Changes from V2.6.1
+
+    + Replaced the sUsingPreemption variable with the configUSE_PREEMPTION
+      macro to be consistent with the later ports.
+*/
 
 /*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the Flashlite 186
-* port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the Flashlite 186
+ * port.
+ *----------------------------------------------------------*/
 
 #include <stdlib.h>
 #include <i86.h>
@@ -60,9 +60,9 @@
 
 /*lint -e950 Non ANSI reserved words okay in this file only. */
 
-#define portTIMER_EOI_TYPE              ( 8 )
-#define portRESET_PIC()    portOUTPUT_WORD( ( uint16_t ) 0xff22, portTIMER_EOI_TYPE )
-#define portTIMER_INT_NUMBER            0x12
+#define portTIMER_EOI_TYPE      ( 8 )
+#define portRESET_PIC()         portOUTPUT_WORD( ( uint16_t ) 0xff22, portTIMER_EOI_TYPE )
+#define portTIMER_INT_NUMBER    0x12
 
 #define portTIMER_1_CONTROL_REGISTER    ( ( uint16_t ) 0xff5e )
 #define portTIMER_0_CONTROL_REGISTER    ( ( uint16_t ) 0xff56 )
@@ -75,14 +75,12 @@ static void prvSetTickFrequency( uint32_t ulTickRateHz );
 static void prvExitFunction( void );
 
 #if configUSE_PREEMPTION == 1
-
-/* Tick service routine used by the scheduler when preemptive scheduling is
- * being used. */
+    /* Tick service routine used by the scheduler when preemptive scheduling is
+    being used. */
     static void __interrupt __far prvPreemptiveTick( void );
 #else
-
-/* Tick service routine used by the scheduler when cooperative scheduling is
- * being used. */
+    /* Tick service routine used by the scheduler when cooperative scheduling is
+    being used. */
     static void __interrupt __far prvNonPreemptiveTick( void );
 #endif
 
@@ -95,7 +93,7 @@ static void __interrupt __far prvYieldProcessor( void );
 static int16_t sSchedulerRunning = pdFALSE;
 
 /* Points to the original routine installed on the vector we use for manual context switches.  This is then used to restore the original routine during prvExitFunction(). */
-static void( __interrupt __far * pxOldSwitchISR )();
+static void ( __interrupt __far *pxOldSwitchISR )();
 
 /* Used to restore the original DOS context when the scheduler is ended. */
 static jmp_buf xJumpBuf;
@@ -108,11 +106,11 @@ BaseType_t xPortStartScheduler( void )
     /* This is called with interrupts already disabled. */
 
     /* Remember what was on the interrupts we are going to use
-     * so we can put them back later if required. */
+    so we can put them back later if required. */
     pxOldSwitchISR = _dos_getvect( portSWITCH_INT_NUMBER );
 
     /* Put our manual switch (yield) function on a known
-     * vector. */
+    vector. */
     _dos_setvect( portSWITCH_INT_NUMBER, prvYieldProcessor );
 
     #if configUSE_PREEMPTION == 1
@@ -148,7 +146,7 @@ BaseType_t xPortStartScheduler( void )
 /*-----------------------------------------------------------*/
 
 /* The tick ISR used depend on whether or not the preemptive or cooperative
- * kernel is being used. */
+kernel is being used. */
 #if configUSE_PREEMPTION == 1
     static void __interrupt __far prvPreemptiveTick( void )
     {
@@ -162,15 +160,15 @@ BaseType_t xPortStartScheduler( void )
         /* Reset the PIC ready for the next time. */
         portRESET_PIC();
     }
-#else /* if configUSE_PREEMPTION == 1 */
+#else
     static void __interrupt __far prvNonPreemptiveTick( void )
     {
         /* Same as preemptive tick, but the cooperative scheduler is being used
-         * so we don't have to switch in the context of the next task. */
+        so we don't have to switch in the context of the next task. */
         xTaskIncrementTick();
         portRESET_PIC();
     }
-#endif /* if configUSE_PREEMPTION == 1 */
+#endif
 /*-----------------------------------------------------------*/
 
 static void __interrupt __far prvYieldProcessor( void )
@@ -183,31 +181,30 @@ static void __interrupt __far prvYieldProcessor( void )
 void vPortEndScheduler( void )
 {
     /* Jump back to the processor state prior to starting the
-     * scheduler.  This means we are not going to be using a
-     * task stack frame so the task can be deleted. */
+    scheduler.  This means we are not going to be using a
+    task stack frame so the task can be deleted. */
     longjmp( xJumpBuf, 1 );
 }
 /*-----------------------------------------------------------*/
 
 static void prvExitFunction( void )
 {
-    const uint16_t usTimerDisable = 0x0000;
-    uint16_t usTimer0Control;
+const uint16_t usTimerDisable = 0x0000;
+uint16_t usTimer0Control;
 
     /* Interrupts should be disabled here anyway - but no
-     * harm in making sure. */
+    harm in making sure. */
     portDISABLE_INTERRUPTS();
-
     if( sSchedulerRunning == pdTRUE )
     {
         /* Put back the switch interrupt routines that was in place
-         * before the scheduler started. */
+        before the scheduler started. */
         _dos_setvect( portSWITCH_INT_NUMBER, pxOldSwitchISR );
     }
 
     /* Disable the timer used for the tick to ensure the scheduler is
-     * not called before restoring interrupts.  There was previously nothing
-     * on this timer so there is no old ISR to restore. */
+    not called before restoring interrupts.  There was previously nothing
+    on this timer so there is no old ISR to restore. */
     portOUTPUT_WORD( portTIMER_1_CONTROL_REGISTER, usTimerDisable );
 
     /* Restart the DOS tick. */
@@ -222,18 +219,18 @@ static void prvExitFunction( void )
 
 static void prvSetTickFrequency( uint32_t ulTickRateHz )
 {
-    const uint16_t usMaxCountRegister = 0xff5a;
-    const uint16_t usTimerPriorityRegister = 0xff32;
-    const uint16_t usTimerEnable = 0xC000;
-    const uint16_t usRetrigger = 0x0001;
-    const uint16_t usTimerHighPriority = 0x0000;
-    uint16_t usTimer0Control;
+const uint16_t usMaxCountRegister = 0xff5a;
+const uint16_t usTimerPriorityRegister = 0xff32;
+const uint16_t usTimerEnable = 0xC000;
+const uint16_t usRetrigger = 0x0001;
+const uint16_t usTimerHighPriority = 0x0000;
+uint16_t usTimer0Control;
 
 /* ( CPU frequency / 4 ) / clock 2 max count [inpw( 0xff62 ) = 7] */
 
-    const uint32_t ulClockFrequency = 0x7f31a0;
+const uint32_t ulClockFrequency = 0x7f31a0;
 
-    uint32_t ulTimerCount = ulClockFrequency / ulTickRateHz;
+uint32_t ulTimerCount = ulClockFrequency / ulTickRateHz;
 
     portOUTPUT_WORD( portTIMER_1_CONTROL_REGISTER, usTimerEnable | portTIMER_INTERRUPT_ENABLE | usRetrigger );
     portOUTPUT_WORD( usMaxCountRegister, ( uint16_t ) ulTimerCount );
diff --git a/portable/oWatcom/16BitDOS/Flsh186/portmacro.h b/portable/oWatcom/16BitDOS/Flsh186/portmacro.h
index 0488fd8b7..952e3f680 100644
--- a/portable/oWatcom/16BitDOS/Flsh186/portmacro.h
+++ b/portable/oWatcom/16BitDOS/Flsh186/portmacro.h
@@ -47,24 +47,24 @@
 
 
 /* Type definitions. */
-#define portCHAR          char
-#define portFLOAT         float
-#define portDOUBLE        long
-#define portLONG          long
-#define portSHORT         int
-#define portSTACK_TYPE    uint16_t
-#define portBASE_TYPE     short
+#define portCHAR        char
+#define portFLOAT       float
+#define portDOUBLE      long
+#define portLONG        long
+#define portSHORT       int
+#define portSTACK_TYPE  uint16_t
+#define portBASE_TYPE   short
 
-typedef portSTACK_TYPE   StackType_t;
-typedef short            BaseType_t;
-typedef unsigned short   UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef short BaseType_t;
+typedef unsigned short UBaseType_t;
 
 
-#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t     TickType_t;
-    #define portMAX_DELAY    ( TickType_t ) 0xffff
-#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t     TickType_t;
+#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+        typedef uint16_t TickType_t;
+        #define portMAX_DELAY ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS  == TICK_TYPE_WIDTH_32_BITS )
+    typedef uint32_t             TickType_t;
     #define portMAX_DELAY    ( TickType_t ) 0xffffffffUL
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -74,7 +74,7 @@ typedef unsigned short   UBaseType_t;
 /* Critical section management. */
 void portENTER_CRITICAL( void );
 #pragma aux portENTER_CRITICAL = "pushf" \
-    "cli";
+                                 "cli";
 
 void portEXIT_CRITICAL( void );
 #pragma aux portEXIT_CRITICAL   = "popf";
@@ -87,25 +87,25 @@ void portENABLE_INTERRUPTS( void );
 /*-----------------------------------------------------------*/
 
 /* Architecture specifics. */
-#define portSTACK_GROWTH         ( -1 )
-#define portSWITCH_INT_NUMBER    0x80
-#define portYIELD()    __asm { int portSWITCH_INT_NUMBER }
-#define portTICK_PERIOD_MS       ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT       2
-#define portINITIAL_SW           ( ( portSTACK_TYPE ) 0x0202 )  /* Start the tasks with interrupts enabled. */
-#define portNOP()    __asm { nop }
+#define portSTACK_GROWTH        ( -1 )
+#define portSWITCH_INT_NUMBER   0x80
+#define portYIELD()             __asm{ int portSWITCH_INT_NUMBER }
+#define portTICK_PERIOD_MS        ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT      2
+#define portINITIAL_SW          ( ( portSTACK_TYPE ) 0x0202 )   /* Start the tasks with interrupts enabled. */
+#define portNOP()               __asm{ nop }
 /*-----------------------------------------------------------*/
 
 /* Compiler specifics. */
-#define portINPUT_BYTE( xAddr )              inp( xAddr )
-#define portOUTPUT_BYTE( xAddr, ucValue )    outp( xAddr, ucValue )
-#define portINPUT_WORD( xAddr )              inpw( xAddr )
-#define portOUTPUT_WORD( xAddr, usValue )    outpw( xAddr, usValue )
+#define portINPUT_BYTE( xAddr )                 inp( xAddr )
+#define portOUTPUT_BYTE( xAddr, ucValue )       outp( xAddr, ucValue )
+#define portINPUT_WORD( xAddr )                 inpw( xAddr )
+#define portOUTPUT_WORD( xAddr, usValue )       outpw( xAddr, usValue )
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/oWatcom/16BitDOS/PC/port.c b/portable/oWatcom/16BitDOS/PC/port.c
index 4c4011aa9..6cb2de9e8 100644
--- a/portable/oWatcom/16BitDOS/PC/port.c
+++ b/portable/oWatcom/16BitDOS/PC/port.c
@@ -27,27 +27,27 @@
  */
 
 /*
- * Changes from V1.00:
- *
- + Call to taskYIELD() from within tick ISR has been replaced by the more
- +    efficient portSWITCH_CONTEXT().
- + ISR function definitions renamed to include the prv prefix.
- +
- + Changes from V1.2.0:
- +
- + prvPortResetPIC() is now called last thing before the end of the
- +    preemptive tick routine.
- +
- + Changes from V2.6.1
- +
- + Replaced the sUsingPreemption variable with the configUSE_PREEMPTION
- +    macro to be consistent with the later ports.
- +
- + Changes from V4.0.1
- +
- + Add function prvSetTickFrequencyDefault() to set the DOS tick back to
- +    its proper value when the scheduler exits.
- */
+Changes from V1.00:
+
+    + Call to taskYIELD() from within tick ISR has been replaced by the more
+      efficient portSWITCH_CONTEXT().
+    + ISR function definitions renamed to include the prv prefix.
+
+Changes from V1.2.0:
+
+    + prvPortResetPIC() is now called last thing before the end of the
+      preemptive tick routine.
+
+Changes from V2.6.1
+
+    + Replaced the sUsingPreemption variable with the configUSE_PREEMPTION
+      macro to be consistent with the later ports.
+
+Changes from V4.0.1
+
+    + Add function prvSetTickFrequencyDefault() to set the DOS tick back to
+      its proper value when the scheduler exits.
+*/
 
 #include <stdlib.h>
 #include <stdio.h>
@@ -60,9 +60,9 @@
 #include "portasm.h"
 
 /*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the industrial
-* PC port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the industrial
+ * PC port.
+ *----------------------------------------------------------*/
 
 /*lint -e950 Non ANSI reserved words okay in this file only. */
 
@@ -75,28 +75,26 @@ static void prvSetTickFrequency( uint32_t ulTickRateHz );
 static void prvExitFunction( void );
 
 /* Either chain to the DOS tick (which itself clears the PIC) or clear the PIC
- * directly.  We chain to the DOS tick as close as possible to the standard DOS
- * tick rate. */
+directly.  We chain to the DOS tick as close as possible to the standard DOS
+tick rate. */
 static void prvPortResetPIC( void );
 
 /* The tick ISR used depends on whether the preemptive or cooperative scheduler
- * is being used. */
+is being used. */
 #if configUSE_PREEMPTION == 1
-
-/* Tick service routine used by the scheduler when preemptive scheduling is
- * being used. */
+    /* Tick service routine used by the scheduler when preemptive scheduling is
+    being used. */
     static void __interrupt __far prvPreemptiveTick( void );
 #else
-
-/* Tick service routine used by the scheduler when cooperative scheduling is
- * being used. */
+    /* Tick service routine used by the scheduler when cooperative scheduling is
+    being used. */
     static void __interrupt __far prvNonPreemptiveTick( void );
 #endif
 /* Trap routine used by taskYIELD() to manually cause a context switch. */
 static void __interrupt __far prvYieldProcessor( void );
 
 /* Set the tick frequency back so the floppy drive works correctly when the
- * scheduler exits. */
+scheduler exits. */
 static void prvSetTickFrequencyDefault( void );
 
 /*lint -e956 File scopes necessary here. */
@@ -108,10 +106,10 @@ static int16_t sDOSTickCounter;
 static int16_t sSchedulerRunning = pdFALSE;
 
 /* Points to the original routine installed on the vector we use for manual context switches.  This is then used to restore the original routine during prvExitFunction(). */
-static void( __interrupt __far * pxOldSwitchISR )();
+static void ( __interrupt __far *pxOldSwitchISR )();
 
 /* Points to the original routine installed on the vector we use to chain to the DOS tick.  This is then used to restore the original routine during prvExitFunction(). */
-static void( __interrupt __far * pxOldSwitchISRPlus1 )();
+static void ( __interrupt __far *pxOldSwitchISRPlus1 )();
 
 /* Used to restore the original DOS context when the scheduler is ended. */
 static jmp_buf xJumpBuf;
@@ -121,12 +119,12 @@ static jmp_buf xJumpBuf;
 /*-----------------------------------------------------------*/
 BaseType_t xPortStartScheduler( void )
 {
-    pxISR pxOriginalTickISR;
+pxISR pxOriginalTickISR;
 
     /* This is called with interrupts already disabled. */
 
     /* Remember what was on the interrupts we are going to use
-     * so we can put them back later if required. */
+    so we can put them back later if required. */
     pxOldSwitchISR = _dos_getvect( portSWITCH_INT_NUMBER );
     pxOriginalTickISR = _dos_getvect( portTIMER_INT_NUMBER );
     pxOldSwitchISRPlus1 = _dos_getvect( portSWITCH_INT_NUMBER + 1 );
@@ -134,11 +132,11 @@ BaseType_t xPortStartScheduler( void )
     prvSetTickFrequency( configTICK_RATE_HZ );
 
     /* Put our manual switch (yield) function on a known
-     * vector. */
+    vector. */
     _dos_setvect( portSWITCH_INT_NUMBER, prvYieldProcessor );
 
     /* Put the old tick on a different interrupt number so we can
-     * call it when we want. */
+    call it when we want. */
     _dos_setvect( portSWITCH_INT_NUMBER + 1, pxOriginalTickISR );
 
     #if configUSE_PREEMPTION == 1
@@ -154,8 +152,8 @@ BaseType_t xPortStartScheduler( void )
     #endif
 
     /* Setup a counter that is used to call the DOS interrupt as close
-     * to it's original frequency as can be achieved given our chosen tick
-     * frequency. */
+    to it's original frequency as can be achieved given our chosen tick
+    frequency. */
     sDOSTickCounter = portTICKS_PER_DOS_TICK;
 
     /* Clean up function if we want to return to DOS. */
@@ -177,11 +175,10 @@ BaseType_t xPortStartScheduler( void )
 /*-----------------------------------------------------------*/
 
 /* The tick ISR used depends on whether the preemptive or cooperative scheduler
- * is being used. */
+is being used. */
 #if configUSE_PREEMPTION == 1
-
-/* Tick service routine used by the scheduler when preemptive scheduling is
- * being used. */
+    /* Tick service routine used by the scheduler when preemptive scheduling is
+    being used. */
     static void __interrupt __far prvPreemptiveTick( void )
     {
         /* Get the scheduler to update the task states following the tick. */
@@ -194,15 +191,15 @@ BaseType_t xPortStartScheduler( void )
         /* Reset the PIC ready for the next time. */
         prvPortResetPIC();
     }
-#else /* if configUSE_PREEMPTION == 1 */
+#else
     static void __interrupt __far prvNonPreemptiveTick( void )
     {
         /* Same as preemptive tick, but the cooperative scheduler is being used
-         * so we don't have to switch in the context of the next task. */
+        so we don't have to switch in the context of the next task. */
         xTaskIncrementTick();
         prvPortResetPIC();
     }
-#endif /* if configUSE_PREEMPTION == 1 */
+#endif
 /*-----------------------------------------------------------*/
 
 
@@ -216,22 +213,19 @@ static void __interrupt __far prvYieldProcessor( void )
 static void prvPortResetPIC( void )
 {
     /* We are going to call the DOS tick interrupt at as close a
-     * frequency to the normal DOS tick as possible. */
+    frequency to the normal DOS tick as possible. */
 
     /* WE SHOULD NOT DO THIS IF YIELD WAS CALLED. */
     --sDOSTickCounter;
-
     if( sDOSTickCounter <= 0 )
     {
         sDOSTickCounter = ( int16_t ) portTICKS_PER_DOS_TICK;
-        __asm {
-            int portSWITCH_INT_NUMBER + 1
-        };
+        __asm{ int  portSWITCH_INT_NUMBER + 1 };
     }
     else
     {
         /* Reset the PIC as the DOS tick is not being called to
-         * do it. */
+        do it. */
         __asm
         {
             mov al, 20H
@@ -244,20 +238,19 @@ static void prvPortResetPIC( void )
 void vPortEndScheduler( void )
 {
     /* Jump back to the processor state prior to starting the
-     * scheduler.  This means we are not going to be using a
-     * task stack frame so the task can be deleted. */
+    scheduler.  This means we are not going to be using a
+    task stack frame so the task can be deleted. */
     longjmp( xJumpBuf, 1 );
 }
 /*-----------------------------------------------------------*/
 
 static void prvExitFunction( void )
 {
-    void( __interrupt __far * pxOriginalTickISR )();
+void ( __interrupt __far *pxOriginalTickISR )();
 
     /* Interrupts should be disabled here anyway - but no
-     * harm in making sure. */
+    harm in making sure. */
     portDISABLE_INTERRUPTS();
-
     if( sSchedulerRunning == pdTRUE )
     {
         /* Set the DOS tick back onto the timer ticker. */
@@ -266,30 +259,29 @@ static void prvExitFunction( void )
         prvSetTickFrequencyDefault();
 
         /* Put back the switch interrupt routines that was in place
-         * before the scheduler started. */
+        before the scheduler started. */
         _dos_setvect( portSWITCH_INT_NUMBER, pxOldSwitchISR );
         _dos_setvect( portSWITCH_INT_NUMBER + 1, pxOldSwitchISRPlus1 );
     }
-
     /* The tick timer is back how DOS wants it.  We can re-enable
-     * interrupts without the scheduler being called. */
+    interrupts without the scheduler being called. */
     portENABLE_INTERRUPTS();
 }
 /*-----------------------------------------------------------*/
 
 static void prvSetTickFrequency( uint32_t ulTickRateHz )
 {
-    const uint16_t usPIT_MODE = ( uint16_t ) 0x43;
-    const uint16_t usPIT0 = ( uint16_t ) 0x40;
-    const uint32_t ulPIT_CONST = ( uint32_t ) 1193180;
-    const uint16_t us8254_CTR0_MODE3 = ( uint16_t ) 0x36;
-    uint32_t ulOutput;
+const uint16_t usPIT_MODE = ( uint16_t ) 0x43;
+const uint16_t usPIT0 = ( uint16_t ) 0x40;
+const uint32_t ulPIT_CONST = ( uint32_t ) 1193180;
+const uint16_t us8254_CTR0_MODE3 = ( uint16_t ) 0x36;
+uint32_t ulOutput;
 
     /* Setup the 8245 to tick at the wanted frequency. */
     portOUTPUT_BYTE( usPIT_MODE, us8254_CTR0_MODE3 );
     ulOutput = ulPIT_CONST / ulTickRateHz;
 
-    portOUTPUT_BYTE( usPIT0, ( uint16_t ) ( ulOutput & ( uint32_t ) 0xff ) );
+    portOUTPUT_BYTE( usPIT0, ( uint16_t )( ulOutput & ( uint32_t ) 0xff ) );
     ulOutput >>= 8;
     portOUTPUT_BYTE( usPIT0, ( uint16_t ) ( ulOutput & ( uint32_t ) 0xff ) );
 }
@@ -297,13 +289,13 @@ static void prvSetTickFrequency( uint32_t ulTickRateHz )
 
 static void prvSetTickFrequencyDefault( void )
 {
-    const uint16_t usPIT_MODE = ( uint16_t ) 0x43;
-    const uint16_t usPIT0 = ( uint16_t ) 0x40;
-    const uint16_t us8254_CTR0_MODE3 = ( uint16_t ) 0x36;
+const uint16_t usPIT_MODE = ( uint16_t ) 0x43;
+const uint16_t usPIT0 = ( uint16_t ) 0x40;
+const uint16_t us8254_CTR0_MODE3 = ( uint16_t ) 0x36;
 
     portOUTPUT_BYTE( usPIT_MODE, us8254_CTR0_MODE3 );
-    portOUTPUT_BYTE( usPIT0, 0 );
-    portOUTPUT_BYTE( usPIT0, 0 );
+    portOUTPUT_BYTE( usPIT0,0 );
+    portOUTPUT_BYTE( usPIT0,0 );
 }
 
 
diff --git a/portable/oWatcom/16BitDOS/PC/portmacro.h b/portable/oWatcom/16BitDOS/PC/portmacro.h
index f2c585a14..2fb753411 100644
--- a/portable/oWatcom/16BitDOS/PC/portmacro.h
+++ b/portable/oWatcom/16BitDOS/PC/portmacro.h
@@ -46,24 +46,24 @@
  */
 
 /* Type definitions. */
-#define portCHAR          char
-#define portFLOAT         float
-#define portDOUBLE        double
-#define portLONG          long
-#define portSHORT         int
-#define portSTACK_TYPE    uint16_t
-#define portBASE_TYPE     short
+#define portCHAR        char
+#define portFLOAT       float
+#define portDOUBLE      double
+#define portLONG        long
+#define portSHORT       int
+#define portSTACK_TYPE  uint16_t
+#define portBASE_TYPE   short
 
-typedef portSTACK_TYPE   StackType_t;
-typedef short            BaseType_t;
-typedef unsigned short   UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef short BaseType_t;
+typedef unsigned short UBaseType_t;
 
 
-#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t     TickType_t;
-    #define portMAX_DELAY    ( TickType_t ) 0xffff
-#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t     TickType_t;
+#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t TickType_t;
+    #define portMAX_DELAY ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS  == TICK_TYPE_WIDTH_32_BITS )
+    typedef uint32_t             TickType_t;
     #define portMAX_DELAY    ( TickType_t ) 0xffffffffUL
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
@@ -71,11 +71,11 @@ typedef unsigned short   UBaseType_t;
 /*-----------------------------------------------------------*/
 
 /* Critical section definitions.  portENTER_CRITICAL() must be defined as a
- * macro for portable.h to work properly. */
+macro for portable.h to work properly. */
 void portLOCAL_ENTER_CRITICAL( void );
 #pragma aux portLOCAL_ENTER_CRITICAL =  "pushf" \
-    "cli";
-#define portENTER_CRITICAL()    portLOCAL_ENTER_CRITICAL()
+                                        "cli";
+#define portENTER_CRITICAL() portLOCAL_ENTER_CRITICAL()
 
 void portEXIT_CRITICAL( void );
 #pragma aux portEXIT_CRITICAL   =       "popf";
@@ -88,25 +88,25 @@ void portENABLE_INTERRUPTS( void );
 /*-----------------------------------------------------------*/
 
 /* Architecture specifics. */
-#define portSTACK_GROWTH          ( -1 )
-#define portSWITCH_INT_NUMBER     0x80
-#define portYIELD()    __asm { int portSWITCH_INT_NUMBER }
-#define portDOS_TICK_RATE         ( 18.20648 )
+#define portSTACK_GROWTH        ( -1 )
+#define portSWITCH_INT_NUMBER   0x80
+#define portYIELD()             __asm{ int portSWITCH_INT_NUMBER }
+#define portDOS_TICK_RATE       ( 18.20648 )
 #define portTICK_PERIOD_MS        ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portTICKS_PER_DOS_TICK    ( ( uint16_t ) ( ( ( portDOUBLE ) configTICK_RATE_HZ / portDOS_TICK_RATE ) + 0.5 ) )
-#define portINITIAL_SW            ( ( portSTACK_TYPE ) 0x0202 ) /* Start the tasks with interrupts enabled. */
-#define portBYTE_ALIGNMENT        ( 2 )
+#define portTICKS_PER_DOS_TICK  ( ( uint16_t ) ( ( ( portDOUBLE ) configTICK_RATE_HZ / portDOS_TICK_RATE ) + 0.5 ) )
+#define portINITIAL_SW          ( ( portSTACK_TYPE ) 0x0202 )   /* Start the tasks with interrupts enabled. */
+#define portBYTE_ALIGNMENT      ( 2 )
 /*-----------------------------------------------------------*/
 
 /* Compiler specifics. */
-#define portINPUT_BYTE( xAddr )              inp( xAddr )
-#define portOUTPUT_BYTE( xAddr, ucValue )    outp( xAddr, ucValue )
-#define portNOP()                            __asm { nop }
+#define portINPUT_BYTE( xAddr )             inp( xAddr )
+#define portOUTPUT_BYTE( xAddr, ucValue )   outp( xAddr, ucValue )
+#define portNOP() __asm{ nop }
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vTaskFunction, pvParameters )    void vTaskFunction( void * pvParameters )
-#define portTASK_FUNCTION( vTaskFunction, pvParameters )          void vTaskFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vTaskFunction, pvParameters ) void vTaskFunction( void *pvParameters )
+#define portTASK_FUNCTION( vTaskFunction, pvParameters ) void vTaskFunction( void *pvParameters )
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
diff --git a/portable/oWatcom/16BitDOS/common/portasm.h b/portable/oWatcom/16BitDOS/common/portasm.h
index 997243293..f77e2b553 100644
--- a/portable/oWatcom/16BitDOS/common/portasm.h
+++ b/portable/oWatcom/16BitDOS/common/portasm.h
@@ -45,65 +45,65 @@ void portSWITCH_CONTEXT( void );
 void portFIRST_CONTEXT( void );
 
 /* There are slightly different versions depending on whether you are building
- * to include debugger information.  If debugger information is used then there
- * are a couple of extra bytes left of the ISR stack (presumably for use by the
- * debugger).  The true stack pointer is then stored in the bp register.  We add
- * 2 to the stack pointer to remove the extra bytes before we restore our context. */
+to include debugger information.  If debugger information is used then there
+are a couple of extra bytes left of the ISR stack (presumably for use by the
+debugger).  The true stack pointer is then stored in the bp register.  We add
+2 to the stack pointer to remove the extra bytes before we restore our context. */
 
 #ifdef DEBUG_BUILD
 
-    #pragma aux portSWITCH_CONTEXT =    "mov    ax, seg pxCurrentTCB"                                                        \
-    "mov    ds, ax"                                                                                                          \
-    "les    bx, pxCurrentTCB" /* Save the stack pointer into the TCB. */                                                     \
-    "mov    es:0x2[ bx ], ss"                                                                                                \
-    "mov    es:[ bx ], sp"                                                                                                   \
-    "call   vTaskSwitchContext"   /* Perform the switch. */                                                                  \
-    "mov    ax, seg pxCurrentTCB" /* Restore the stack pointer from the TCB. */                                              \
-    "mov    ds, ax"                                                                                                          \
-    "les    bx, dword ptr pxCurrentTCB"                                                                                      \
-    "mov    ss, es:[ bx + 2 ]"                                                                                               \
-    "mov    sp, es:[ bx ]"                                                                                                   \
-    "mov    bp, sp" /* Prepair the bp register for the restoration of the SP in the compiler generated portion of the ISR */ \
-    "add    bp, 0x0002"
+    #pragma aux portSWITCH_CONTEXT =    "mov    ax, seg pxCurrentTCB"                                                       \
+                                        "mov    ds, ax"                                                                     \
+                                        "les    bx, pxCurrentTCB"           /* Save the stack pointer into the TCB. */      \
+                                        "mov    es:0x2[ bx ], ss"                                                           \
+                                        "mov    es:[ bx ], sp"                                                              \
+                                        "call   vTaskSwitchContext"         /* Perform the switch. */                       \
+                                        "mov    ax, seg pxCurrentTCB"       /* Restore the stack pointer from the TCB. */   \
+                                        "mov    ds, ax"                                                                     \
+                                        "les    bx, dword ptr pxCurrentTCB"                                                 \
+                                        "mov    ss, es:[ bx + 2 ]"                                                          \
+                                        "mov    sp, es:[ bx ]"                                                              \
+                                        "mov    bp, sp"                     /* Prepair the bp register for the restoration of the SP in the compiler generated portion of the ISR */    \
+                                        "add    bp, 0x0002"
 
 
 
-    #pragma aux portFIRST_CONTEXT =     "mov    ax, seg pxCurrentTCB"                                         \
-    "mov    ds, ax"                                                                                           \
-    "les    bx, dword ptr pxCurrentTCB"                                                                       \
-    "mov    ss, es:[ bx + 2 ]"                                                                                \
-    "mov    sp, es:[ bx ]"                                                                                    \
-    "add    sp, 0x0002" /* Remove the extra bytes that exist in debug builds before restoring the context. */ \
-    "pop    ax"                                                                                               \
-    "pop    ax"                                                                                               \
-    "pop    es"                                                                                               \
-    "pop    ds"                                                                                               \
-    "popa"                                                                                                    \
-    "iret"
-#else /* ifdef DEBUG_BUILD */
+    #pragma aux portFIRST_CONTEXT =     "mov    ax, seg pxCurrentTCB"           \
+                                        "mov    ds, ax"                         \
+                                        "les    bx, dword ptr pxCurrentTCB"     \
+                                        "mov    ss, es:[ bx + 2 ]"              \
+                                        "mov    sp, es:[ bx ]"                  \
+                                        "add    sp, 0x0002"                     /* Remove the extra bytes that exist in debug builds before restoring the context. */ \
+                                        "pop    ax"                             \
+                                        "pop    ax"                             \
+                                        "pop    es"                             \
+                                        "pop    ds"                             \
+                                        "popa"                                  \
+                                        "iret"
+#else
 
-    #pragma aux portSWITCH_CONTEXT =    "mov    ax, seg pxCurrentTCB"           \
-    "mov    ds, ax"                                                             \
-    "les    bx, pxCurrentTCB" /* Save the stack pointer into the TCB. */        \
-    "mov    es:0x2[ bx ], ss"                                                   \
-    "mov    es:[ bx ], sp"                                                      \
-    "call   vTaskSwitchContext"   /* Perform the switch. */                     \
-    "mov    ax, seg pxCurrentTCB" /* Restore the stack pointer from the TCB. */ \
-    "mov    ds, ax"                                                             \
-    "les    bx, dword ptr pxCurrentTCB"                                         \
-    "mov    ss, es:[ bx + 2 ]"                                                  \
-    "mov    sp, es:[ bx ]"
+    #pragma aux portSWITCH_CONTEXT =    "mov    ax, seg pxCurrentTCB"                                                       \
+                                        "mov    ds, ax"                                                                     \
+                                        "les    bx, pxCurrentTCB"           /* Save the stack pointer into the TCB. */      \
+                                        "mov    es:0x2[ bx ], ss"                                                           \
+                                        "mov    es:[ bx ], sp"                                                              \
+                                        "call   vTaskSwitchContext"         /* Perform the switch. */                       \
+                                        "mov    ax, seg pxCurrentTCB"       /* Restore the stack pointer from the TCB. */   \
+                                        "mov    ds, ax"                                                                     \
+                                        "les    bx, dword ptr pxCurrentTCB"                                                 \
+                                        "mov    ss, es:[ bx + 2 ]"                                                          \
+                                        "mov    sp, es:[ bx ]"
 
 
-    #pragma aux portFIRST_CONTEXT =     "mov    ax, seg pxCurrentTCB" \
-    "mov    ds, ax"                                                   \
-    "les    bx, dword ptr pxCurrentTCB"                               \
-    "mov    ss, es:[ bx + 2 ]"                                        \
-    "mov    sp, es:[ bx ]"                                            \
-    "pop    ax"                                                       \
-    "pop    ax"                                                       \
-    "pop    es"                                                       \
-    "pop    ds"                                                       \
-    "popa"                                                            \
-    "iret"
-#endif /* ifdef DEBUG_BUILD */
+    #pragma aux portFIRST_CONTEXT =     "mov    ax, seg pxCurrentTCB"           \
+                                        "mov    ds, ax"                         \
+                                        "les    bx, dword ptr pxCurrentTCB"     \
+                                        "mov    ss, es:[ bx + 2 ]"              \
+                                        "mov    sp, es:[ bx ]"                  \
+                                        "pop    ax"                             \
+                                        "pop    ax"                             \
+                                        "pop    es"                             \
+                                        "pop    ds"                             \
+                                        "popa"                                  \
+                                        "iret"
+#endif
diff --git a/portable/oWatcom/16BitDOS/common/portcomn.c b/portable/oWatcom/16BitDOS/common/portcomn.c
index 54c06f675..2a7b66637 100644
--- a/portable/oWatcom/16BitDOS/common/portcomn.c
+++ b/portable/oWatcom/16BitDOS/common/portcomn.c
@@ -27,21 +27,21 @@
  */
 
 /*
- * Changes from V1.00:
- *
- + pxPortInitialiseStack() now initialises the stack of new tasks to the
- +    same format used by the compiler.  This allows the compiler generated
- +    interrupt mechanism to be used for context switches.
- +
- + Changes from V2.4.2:
- +
- + pvPortMalloc and vPortFree have been removed.  The projects now use
- +    the definitions from the source/portable/MemMang directory.
- +
- + Changes from V2.6.1:
- +
- + usPortCheckFreeStackSpace() has been moved to tasks.c.
- */
+Changes from V1.00:
+
+    + pxPortInitialiseStack() now initialises the stack of new tasks to the
+      same format used by the compiler.  This allows the compiler generated
+      interrupt mechanism to be used for context switches.
+
+Changes from V2.4.2:
+
+    + pvPortMalloc and vPortFree have been removed.  The projects now use
+      the definitions from the source/portable/MemMang directory.
+
+Changes from V2.6.1:
+
+    + usPortCheckFreeStackSpace() has been moved to tasks.c.
+*/
 
 
 
@@ -51,15 +51,13 @@
 /*-----------------------------------------------------------*/
 
 /* See header file for description. */
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
 {
-    StackType_t DS_Reg = 0;
-    StackType_t * pxOriginalSP;
+StackType_t DS_Reg = 0;
+StackType_t * pxOriginalSP;
 
     /* Place a few bytes of known values on the bottom of the stack.
-     * This is just useful for debugging. */
+    This is just useful for debugging. */
 
     *pxTopOfStack = 0x1111;
     pxTopOfStack--;
@@ -76,9 +74,9 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
     /*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */
 
     /* We are going to start the scheduler using a return from interrupt
-     * instruction to load the program counter, so first there would be the
-     * status register and interrupt return address.  We make this the start
-     * of the task. */
+    instruction to load the program counter, so first there would be the
+    status register and interrupt return address.  We make this the start
+    of the task. */
     *pxTopOfStack = portINITIAL_SW;
     pxTopOfStack--;
     *pxTopOfStack = FP_SEG( pxCode );
@@ -87,24 +85,24 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
     pxTopOfStack--;
 
     /* We are going to setup the stack for the new task to look like
-     * the stack frame was setup by a compiler generated ISR.  We need to know
-     * the address of the existing stack top to place in the SP register within
-     * the stack frame.  pxOriginalSP holds SP before (simulated) pusha was
-     * called. */
+    the stack frame was setup by a compiler generated ISR.  We need to know
+    the address of the existing stack top to place in the SP register within
+    the stack frame.  pxOriginalSP holds SP before (simulated) pusha was
+    called. */
     pxOriginalSP = pxTopOfStack;
 
     /* The remaining registers would be pushed on the stack by our context
-     * switch function.  These are loaded with values simply to make debugging
-     * easier. */
-    *pxTopOfStack = FP_OFF( pvParameters ); /* AX */
+    switch function.  These are loaded with values simply to make debugging
+    easier. */
+    *pxTopOfStack = FP_OFF( pvParameters );     /* AX */
     pxTopOfStack--;
     *pxTopOfStack = ( StackType_t ) 0xCCCC; /* CX */
     pxTopOfStack--;
-    *pxTopOfStack = FP_SEG( pvParameters ); /* DX */
+    *pxTopOfStack = FP_SEG( pvParameters );     /* DX */
     pxTopOfStack--;
     *pxTopOfStack = ( StackType_t ) 0xBBBB; /* BX */
     pxTopOfStack--;
-    *pxTopOfStack = FP_OFF( pxOriginalSP ); /* SP */
+    *pxTopOfStack = FP_OFF( pxOriginalSP );     /* SP */
     pxTopOfStack--;
     *pxTopOfStack = ( StackType_t ) 0xBBBB; /* BP */
     pxTopOfStack--;
@@ -113,9 +111,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
     *pxTopOfStack = ( StackType_t ) 0xDDDD; /* DI */
 
     /* We need the true data segment. */
-    __asm {
-        MOV DS_Reg, DS
-    };
+    __asm{  MOV DS_Reg, DS };
 
     pxTopOfStack--;
     *pxTopOfStack = DS_Reg; /* DS */
@@ -125,17 +121,16 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
 
     /* The AX register is pushed again twice - don't know why. */
     pxTopOfStack--;
-    *pxTopOfStack = FP_OFF( pvParameters ); /* AX */
+    *pxTopOfStack = FP_OFF( pvParameters );     /* AX */
     pxTopOfStack--;
-    *pxTopOfStack = FP_OFF( pvParameters ); /* AX */
+    *pxTopOfStack = FP_OFF( pvParameters );     /* AX */
 
 
     #ifdef DEBUG_BUILD
-
         /* The compiler adds space to each ISR stack if building to
-         * include debug information.  Presumably this is used by the
-         * debugger - we don't need to initialise it to anything just
-         * make sure it is there. */
+        include debug information.  Presumably this is used by the
+        debugger - we don't need to initialise it to anything just
+        make sure it is there. */
         pxTopOfStack--;
     #endif
 

From ac7fc396a0f26ce7bf9d7dc93fdd4c8095571314 Mon Sep 17 00:00:00 2001
From: Soren Ptak <ptaksoren@gmail.com>
Date: Thu, 7 Dec 2023 11:51:11 -0500
Subject: [PATCH 153/424] Revert Portable/BCC formatting (#828)

Revert Portable/BCC formatting
---
 portable/BCC/16BitDOS/Flsh186/port.c     | 103 ++++++++++---------
 portable/BCC/16BitDOS/Flsh186/prtmacro.h |  67 +++++++------
 portable/BCC/16BitDOS/PC/port.c          | 121 +++++++++++------------
 portable/BCC/16BitDOS/PC/prtmacro.h      |  67 +++++++------
 portable/BCC/16BitDOS/common/portasm.h   |  66 ++++++-------
 portable/BCC/16BitDOS/common/portcomn.c  |  42 ++++----
 6 files changed, 225 insertions(+), 241 deletions(-)

diff --git a/portable/BCC/16BitDOS/Flsh186/port.c b/portable/BCC/16BitDOS/Flsh186/port.c
index 6697de2f9..66b8b7b7b 100644
--- a/portable/BCC/16BitDOS/Flsh186/port.c
+++ b/portable/BCC/16BitDOS/Flsh186/port.c
@@ -27,22 +27,22 @@
  */
 
 /*
- * Changes from V1.00:
- *
- + Call to taskYIELD() from within tick ISR has been replaced by the more
- +    efficient portSWITCH_CONTEXT().
- + ISR function definitions renamed to include the prv prefix.
- +
- + Changes from V2.6.1
- +
- + Replaced the sUsingPreemption variable with the configUSE_PREEMPTION
- +    macro to be consistent with the later ports.
- */
+Changes from V1.00:
+
+    + Call to taskYIELD() from within tick ISR has been replaced by the more
+      efficient portSWITCH_CONTEXT().
+    + ISR function definitions renamed to include the prv prefix.
+
+Changes from V2.6.1
+
+    + Replaced the sUsingPreemption variable with the configUSE_PREEMPTION
+      macro to be consistent with the later ports.
+*/
 
 /*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the Flashlite 186
-* port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the Flashlite 186
+ * port.
+ *----------------------------------------------------------*/
 
 #include <dos.h>
 #include <stdlib.h>
@@ -54,9 +54,9 @@
 
 /*lint -e950 Non ANSI reserved words okay in this file only. */
 
-#define portTIMER_EOI_TYPE              ( 8 )
-#define portRESET_PIC()    portOUTPUT_WORD( ( uint16_t ) 0xff22, portTIMER_EOI_TYPE )
-#define portTIMER_INT_NUMBER            0x12
+#define portTIMER_EOI_TYPE      ( 8 )
+#define portRESET_PIC()         portOUTPUT_WORD( ( uint16_t ) 0xff22, portTIMER_EOI_TYPE )
+#define portTIMER_INT_NUMBER    0x12
 
 #define portTIMER_1_CONTROL_REGISTER    ( ( uint16_t ) 0xff5e )
 #define portTIMER_0_CONTROL_REGISTER    ( ( uint16_t ) 0xff56 )
@@ -69,16 +69,14 @@ static void prvSetTickFrequency( uint32_t ulTickRateHz );
 static void prvExitFunction( void );
 
 /* The ISR used depends on whether the preemptive or cooperative scheduler
- * is being used. */
-#if ( configUSE_PREEMPTION == 1 )
-
-/* Tick service routine used by the scheduler when preemptive scheduling is
- * being used. */
+is being used. */
+#if( configUSE_PREEMPTION == 1 )
+    /* Tick service routine used by the scheduler when preemptive scheduling is
+    being used. */
     static void __interrupt __far prvPreemptiveTick( void );
 #else
-
-/* Tick service routine used by the scheduler when cooperative scheduling is
- * being used. */
+    /* Tick service routine used by the scheduler when cooperative scheduling is
+    being used. */
     static void __interrupt __far prvNonPreemptiveTick( void );
 #endif
 
@@ -91,9 +89,9 @@ static void __interrupt __far prvYieldProcessor( void );
 static BaseType_t xSchedulerRunning = pdFALSE;
 
 /* Points to the original routine installed on the vector we use for manual
- * context switches.  This is then used to restore the original routine during
- * prvExitFunction(). */
-static void( __interrupt __far * pxOldSwitchISR )();
+context switches.  This is then used to restore the original routine during
+prvExitFunction(). */
+static void ( __interrupt __far *pxOldSwitchISR )();
 
 /* Used to restore the original DOS context when the scheduler is ended. */
 static jmp_buf xJumpBuf;
@@ -106,14 +104,14 @@ BaseType_t xPortStartScheduler( void )
     /* This is called with interrupts already disabled. */
 
     /* Remember what was on the interrupts we are going to use
-     * so we can put them back later if required. */
+    so we can put them back later if required. */
     pxOldSwitchISR = _dos_getvect( portSWITCH_INT_NUMBER );
 
     /* Put our manual switch (yield) function on a known
-     * vector. */
+    vector. */
     _dos_setvect( portSWITCH_INT_NUMBER, prvYieldProcessor );
 
-    #if ( configUSE_PREEMPTION == 1 )
+    #if( configUSE_PREEMPTION == 1 )
     {
         /* Put our tick switch function on the timer interrupt. */
         _dos_setvect( portTIMER_INT_NUMBER, prvPreemptiveTick );
@@ -146,8 +144,8 @@ BaseType_t xPortStartScheduler( void )
 /*-----------------------------------------------------------*/
 
 /* The ISR used depends on whether the preemptive or cooperative scheduler
- * is being used. */
-#if ( configUSE_PREEMPTION == 1 )
+is being used. */
+#if( configUSE_PREEMPTION == 1 )
     static void __interrupt __far prvPreemptiveTick( void )
     {
         /* Get the scheduler to update the task states following the tick. */
@@ -160,15 +158,15 @@ BaseType_t xPortStartScheduler( void )
         /* Reset the PIC ready for the next time. */
         portRESET_PIC();
     }
-#else /* if ( configUSE_PREEMPTION == 1 ) */
+#else
     static void __interrupt __far prvNonPreemptiveTick( void )
     {
         /* Same as preemptive tick, but the cooperative scheduler is being used
-         * so we don't have to switch in the context of the next task. */
+        so we don't have to switch in the context of the next task. */
         xTaskIncrementTick();
         portRESET_PIC();
     }
-#endif /* if ( configUSE_PREEMPTION == 1 ) */
+#endif
 /*-----------------------------------------------------------*/
 
 static void __interrupt __far prvYieldProcessor( void )
@@ -181,31 +179,30 @@ static void __interrupt __far prvYieldProcessor( void )
 void vPortEndScheduler( void )
 {
     /* Jump back to the processor state prior to starting the
-     * scheduler.  This means we are not going to be using a
-     * task stack frame so the task can be deleted. */
+    scheduler.  This means we are not going to be using a
+    task stack frame so the task can be deleted. */
     longjmp( xJumpBuf, 1 );
 }
 /*-----------------------------------------------------------*/
 
 static void prvExitFunction( void )
 {
-    const uint16_t usTimerDisable = 0x0000;
-    uint16_t usTimer0Control;
+const uint16_t usTimerDisable = 0x0000;
+uint16_t usTimer0Control;
 
     /* Interrupts should be disabled here anyway - but no
-     * harm in making sure. */
+    harm in making sure. */
     portDISABLE_INTERRUPTS();
-
     if( xSchedulerRunning == pdTRUE )
     {
         /* Put back the switch interrupt routines that was in place
-         * before the scheduler started. */
+        before the scheduler started. */
         _dos_setvect( portSWITCH_INT_NUMBER, pxOldSwitchISR );
     }
 
     /* Disable the timer used for the tick to ensure the scheduler is
-     * not called before restoring interrupts.  There was previously nothing
-     * on this timer so there is no old ISR to restore. */
+    not called before restoring interrupts.  There was previously nothing
+    on this timer so there is no old ISR to restore. */
     portOUTPUT_WORD( portTIMER_1_CONTROL_REGISTER, usTimerDisable );
 
     /* Restart the DOS tick. */
@@ -220,18 +217,18 @@ static void prvExitFunction( void )
 
 static void prvSetTickFrequency( uint32_t ulTickRateHz )
 {
-    const uint16_t usMaxCountRegister = 0xff5a;
-    const uint16_t usTimerPriorityRegister = 0xff32;
-    const uint16_t usTimerEnable = 0xC000;
-    const uint16_t usRetrigger = 0x0001;
-    const uint16_t usTimerHighPriority = 0x0000;
-    uint16_t usTimer0Control;
+const uint16_t usMaxCountRegister = 0xff5a;
+const uint16_t usTimerPriorityRegister = 0xff32;
+const uint16_t usTimerEnable = 0xC000;
+const uint16_t usRetrigger = 0x0001;
+const uint16_t usTimerHighPriority = 0x0000;
+uint16_t usTimer0Control;
 
 /* ( CPU frequency / 4 ) / clock 2 max count [inpw( 0xff62 ) = 7] */
 
-    const uint32_t ulClockFrequency = ( uint32_t ) 0x7f31a0UL;
+const uint32_t ulClockFrequency = ( uint32_t ) 0x7f31a0UL;
 
-    uint32_t ulTimerCount = ulClockFrequency / ulTickRateHz;
+uint32_t ulTimerCount = ulClockFrequency / ulTickRateHz;
 
     portOUTPUT_WORD( portTIMER_1_CONTROL_REGISTER, usTimerEnable | portTIMER_INTERRUPT_ENABLE | usRetrigger );
     portOUTPUT_WORD( usMaxCountRegister, ( uint16_t ) ulTimerCount );
diff --git a/portable/BCC/16BitDOS/Flsh186/prtmacro.h b/portable/BCC/16BitDOS/Flsh186/prtmacro.h
index 2fd9f91b2..295c0bc73 100644
--- a/portable/BCC/16BitDOS/Flsh186/prtmacro.h
+++ b/portable/BCC/16BitDOS/Flsh186/prtmacro.h
@@ -40,61 +40,60 @@
  */
 
 /* Type definitions. */
-#define portCHAR          char
-#define portFLOAT         float
-#define portDOUBLE        long
-#define portLONG          long
-#define portSHORT         int
-#define portSTACK_TYPE    uint16_t
-#define portBASE_TYPE     portSHORT
+#define portCHAR        char
+#define portFLOAT       float
+#define portDOUBLE      long
+#define portLONG        long
+#define portSHORT       int
+#define portSTACK_TYPE  uint16_t
+#define portBASE_TYPE   portSHORT
 
-typedef portSTACK_TYPE   StackType_t;
-typedef short            BaseType_t;
-typedef unsigned short   UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef short BaseType_t;
+typedef unsigned short UBaseType_t;
 
-#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t     TickType_t;
-    #define portMAX_DELAY    ( TickType_t ) 0xffff
+#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t TickType_t;
+    #define portMAX_DELAY ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t     TickType_t;
-    #define portMAX_DELAY    ( TickType_t ) 0xffffffffUL
+    typedef uint32_t TickType_t;
+    #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
 /*-----------------------------------------------------------*/
 
 /* Critical section handling. */
-#define portENTER_CRITICAL() \
-    __asm { pushf }          \
-    __asm { cli }            \
+#define portENTER_CRITICAL()            __asm{ pushf }  \
+                                        __asm{ cli   }  \
 
-#define portEXIT_CRITICAL()         __asm { popf }
+#define portEXIT_CRITICAL()             __asm{ popf }
 
-#define portDISABLE_INTERRUPTS()    __asm { cli }
+#define portDISABLE_INTERRUPTS()        __asm{ cli }
 
-#define portENABLE_INTERRUPTS()     __asm { sti }
+#define portENABLE_INTERRUPTS()         __asm{ sti }
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portNOP()      __asm { nop }
-#define portSTACK_GROWTH         ( -1 )
-#define portSWITCH_INT_NUMBER    0x80
-#define portYIELD()    __asm { int portSWITCH_INT_NUMBER }
-#define portTICK_PERIOD_MS       ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT       2
-#define portINITIAL_SW           ( ( portSTACK_TYPE ) 0x0202 ) /* Start the tasks with interrupts enabled. */
+#define portNOP()                       __asm{ nop }
+#define portSTACK_GROWTH                ( -1 )
+#define portSWITCH_INT_NUMBER           0x80
+#define portYIELD()                     __asm{ int portSWITCH_INT_NUMBER }
+#define portTICK_PERIOD_MS      ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT      2
+#define portINITIAL_SW      ( ( portSTACK_TYPE ) 0x0202 )   /* Start the tasks with interrupts enabled. */
 /*-----------------------------------------------------------*/
 
 /* Compiler specifics. */
-#define portINPUT_BYTE( xAddr )              inp( xAddr )
-#define portOUTPUT_BYTE( xAddr, ucValue )    outp( xAddr, ucValue )
-#define portINPUT_WORD( xAddr )              inpw( xAddr )
-#define portOUTPUT_WORD( xAddr, usValue )    outpw( xAddr, usValue )
+#define portINPUT_BYTE( xAddr )             inp( xAddr )
+#define portOUTPUT_BYTE( xAddr, ucValue )   outp( xAddr, ucValue )
+#define portINPUT_WORD( xAddr )             inpw( xAddr )
+#define portOUTPUT_WORD( xAddr, usValue )   outpw( xAddr, usValue )
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vTaskFunction, vParameters )    void vTaskFunction( void * pvParameters )
-#define portTASK_FUNCTION( vTaskFunction, vParameters )          void vTaskFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters )
+#define portTASK_FUNCTION( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters )
 
 #endif /* PORTMACRO_H */
diff --git a/portable/BCC/16BitDOS/PC/port.c b/portable/BCC/16BitDOS/PC/port.c
index e8a14a881..6940b1a67 100644
--- a/portable/BCC/16BitDOS/PC/port.c
+++ b/portable/BCC/16BitDOS/PC/port.c
@@ -27,16 +27,16 @@
  */
 
 /*
- * Changes from V2.6.1
- *
- + Replaced the sUsingPreemption variable with the configUSE_PREEMPTION
- +    macro to be consistent with the later ports.
- +
- + Changes from V4.0.1
- +
- + Add function prvSetTickFrequencyDefault() to set the DOS tick back to
- +    its proper value when the scheduler exits.
- */
+Changes from V2.6.1
+
+    + Replaced the sUsingPreemption variable with the configUSE_PREEMPTION
+      macro to be consistent with the later ports.
+
+Changes from V4.0.1
+
+    + Add function prvSetTickFrequencyDefault() to set the DOS tick back to
+      its proper value when the scheduler exits.
+*/
 
 #include <stdlib.h>
 #include <dos.h>
@@ -47,9 +47,9 @@
 #include "portasm.h"
 
 /*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the industrial
-* PC port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the industrial
+ * PC port.
+ *----------------------------------------------------------*/
 
 /*lint -e950 Non ANSI reserved words okay in this file only. */
 
@@ -62,21 +62,19 @@ static void prvSetTickFrequency( uint32_t ulTickRateHz );
 static void prvExitFunction( void );
 
 /* Either chain to the DOS tick (which itself clears the PIC) or clear the PIC
- * directly.  We chain to the DOS tick as close as possible to the standard DOS
- * tick rate. */
+directly.  We chain to the DOS tick as close as possible to the standard DOS
+tick rate. */
 static void prvPortResetPIC( void );
 
 /* The ISR used depends on whether the preemptive or cooperative
- * scheduler is being used. */
-#if ( configUSE_PREEMPTION == 1 )
-
-/* Tick service routine used by the scheduler when preemptive scheduling is
- * being used. */
+scheduler is being used. */
+#if( configUSE_PREEMPTION == 1 )
+    /* Tick service routine used by the scheduler when preemptive scheduling is
+    being used. */
     static void __interrupt __far prvPreemptiveTick( void );
 #else
-
-/* Tick service routine used by the scheduler when cooperative scheduling is
- * being used. */
+    /* Tick service routine used by the scheduler when cooperative scheduling is
+    being used. */
     static void __interrupt __far prvNonPreemptiveTick( void );
 #endif
 
@@ -84,7 +82,7 @@ static void prvPortResetPIC( void );
 static void __interrupt __far prvYieldProcessor( void );
 
 /* Set the tick frequency back so the floppy drive works correctly when the
- * scheduler exits. */
+scheduler exits. */
 static void prvSetTickFrequencyDefault( void );
 
 /*lint -e956 File scopes necessary here. */
@@ -96,10 +94,10 @@ static int16_t sDOSTickCounter;
 static BaseType_t xSchedulerRunning = pdFALSE;
 
 /* Points to the original routine installed on the vector we use for manual context switches.  This is then used to restore the original routine during prvExitFunction(). */
-static void( __interrupt __far * pxOldSwitchISR )();
+static void ( __interrupt __far *pxOldSwitchISR )();
 
 /* Points to the original routine installed on the vector we use to chain to the DOS tick.  This is then used to restore the original routine during prvExitFunction(). */
-static void( __interrupt __far * pxOldSwitchISRPlus1 )();
+static void ( __interrupt __far *pxOldSwitchISRPlus1 )();
 
 /* Used to restore the original DOS context when the scheduler is ended. */
 static jmp_buf xJumpBuf;
@@ -109,12 +107,12 @@ static jmp_buf xJumpBuf;
 /*-----------------------------------------------------------*/
 BaseType_t xPortStartScheduler( void )
 {
-    pxISR pxOriginalTickISR;
+pxISR pxOriginalTickISR;
 
     /* This is called with interrupts already disabled. */
 
     /* Remember what was on the interrupts we are going to use
-     * so we can put them back later if required. */
+    so we can put them back later if required. */
     pxOldSwitchISR = _dos_getvect( portSWITCH_INT_NUMBER );
     pxOriginalTickISR = _dos_getvect( portTIMER_INT_NUMBER );
     pxOldSwitchISRPlus1 = _dos_getvect( portSWITCH_INT_NUMBER + 1 );
@@ -122,16 +120,16 @@ BaseType_t xPortStartScheduler( void )
     prvSetTickFrequency( configTICK_RATE_HZ );
 
     /* Put our manual switch (yield) function on a known
-     * vector. */
+    vector. */
     _dos_setvect( portSWITCH_INT_NUMBER, prvYieldProcessor );
 
     /* Put the old tick on a different interrupt number so we can
-     * call it when we want. */
+    call it when we want. */
     _dos_setvect( portSWITCH_INT_NUMBER + 1, pxOriginalTickISR );
 
     /* The ISR used depends on whether the preemptive or cooperative
-     * scheduler is being used. */
-    #if ( configUSE_PREEMPTION == 1 )
+    scheduler is being used. */
+    #if( configUSE_PREEMPTION == 1 )
     {
         /* Put our tick switch function on the timer interrupt. */
         _dos_setvect( portTIMER_INT_NUMBER, prvPreemptiveTick );
@@ -144,8 +142,8 @@ BaseType_t xPortStartScheduler( void )
     #endif
 
     /* Setup a counter that is used to call the DOS interrupt as close
-     * to it's original frequency as can be achieved given our chosen tick
-     * frequency. */
+    to it's original frequency as can be achieved given our chosen tick
+    frequency. */
     sDOSTickCounter = portTICKS_PER_DOS_TICK;
 
     /* Clean up function if we want to return to DOS. */
@@ -167,8 +165,8 @@ BaseType_t xPortStartScheduler( void )
 /*-----------------------------------------------------------*/
 
 /* The ISR used depends on whether the preemptive or cooperative
- * scheduler is being used. */
-#if ( configUSE_PREEMPTION == 1 )
+scheduler is being used. */
+#if( configUSE_PREEMPTION == 1 )
     static void __interrupt __far prvPreemptiveTick( void )
     {
         /* Get the scheduler to update the task states following the tick. */
@@ -181,15 +179,15 @@ BaseType_t xPortStartScheduler( void )
         /* Reset the PIC ready for the next time. */
         prvPortResetPIC();
     }
-#else /* if ( configUSE_PREEMPTION == 1 ) */
+#else
     static void __interrupt __far prvNonPreemptiveTick( void )
     {
         /* Same as preemptive tick, but the cooperative scheduler is being used
-         * so we don't have to switch in the context of the next task. */
+        so we don't have to switch in the context of the next task. */
         xTaskIncrementTick();
         prvPortResetPIC();
     }
-#endif /* if ( configUSE_PREEMPTION == 1 ) */
+#endif
 /*-----------------------------------------------------------*/
 
 static void __interrupt __far prvYieldProcessor( void )
@@ -202,22 +200,19 @@ static void __interrupt __far prvYieldProcessor( void )
 static void prvPortResetPIC( void )
 {
     /* We are going to call the DOS tick interrupt at as close a
-     * frequency to the normal DOS tick as possible. */
+    frequency to the normal DOS tick as possible. */
 
     /* WE SHOULD NOT DO THIS IF YIELD WAS CALLED. */
     --sDOSTickCounter;
-
     if( sDOSTickCounter <= 0 )
     {
         sDOSTickCounter = ( int16_t ) portTICKS_PER_DOS_TICK;
-        __asm {
-            int portSWITCH_INT_NUMBER + 1
-        };
+        __asm{ int  portSWITCH_INT_NUMBER + 1 };
     }
     else
     {
         /* Reset the PIC as the DOS tick is not being called to
-         * do it. */
+        do it. */
         __asm
         {
             mov al, 20H
@@ -230,20 +225,19 @@ static void prvPortResetPIC( void )
 void vPortEndScheduler( void )
 {
     /* Jump back to the processor state prior to starting the
-     * scheduler.  This means we are not going to be using a
-     * task stack frame so the task can be deleted. */
+    scheduler.  This means we are not going to be using a
+    task stack frame so the task can be deleted. */
     longjmp( xJumpBuf, 1 );
 }
 /*-----------------------------------------------------------*/
 
 static void prvExitFunction( void )
 {
-    void( __interrupt __far * pxOriginalTickISR )();
+void ( __interrupt __far *pxOriginalTickISR )();
 
     /* Interrupts should be disabled here anyway - but no
-     * harm in making sure. */
+    harm in making sure. */
     portDISABLE_INTERRUPTS();
-
     if( xSchedulerRunning == pdTRUE )
     {
         /* Set the DOS tick back onto the timer ticker. */
@@ -252,29 +246,28 @@ static void prvExitFunction( void )
         prvSetTickFrequencyDefault();
 
         /* Put back the switch interrupt routines that was in place
-         * before the scheduler started. */
+        before the scheduler started. */
         _dos_setvect( portSWITCH_INT_NUMBER, pxOldSwitchISR );
         _dos_setvect( portSWITCH_INT_NUMBER + 1, pxOldSwitchISRPlus1 );
     }
-
     /* The tick timer is back how DOS wants it.  We can re-enable
-     * interrupts without the scheduler being called. */
+    interrupts without the scheduler being called. */
     portENABLE_INTERRUPTS();
 }
 /*-----------------------------------------------------------*/
 
 static void prvSetTickFrequency( uint32_t ulTickRateHz )
 {
-    const uint16_t usPIT_MODE = ( uint16_t ) 0x43;
-    const uint16_t usPIT0 = ( uint16_t ) 0x40;
-    const uint32_t ulPIT_CONST = ( uint32_t ) 1193180UL;
-    const uint16_t us8254_CTR0_MODE3 = ( uint16_t ) 0x36;
-    uint32_t ulOutput;
+const uint16_t usPIT_MODE = ( uint16_t ) 0x43;
+const uint16_t usPIT0 = ( uint16_t ) 0x40;
+const uint32_t ulPIT_CONST = ( uint32_t ) 1193180UL;
+const uint16_t us8254_CTR0_MODE3 = ( uint16_t ) 0x36;
+uint32_t ulOutput;
 
     /* Setup the 8245 to tick at the wanted frequency. */
     portOUTPUT_BYTE( usPIT_MODE, us8254_CTR0_MODE3 );
     ulOutput = ulPIT_CONST / ulTickRateHz;
-    portOUTPUT_BYTE( usPIT0, ( uint16_t ) ( ulOutput & ( uint32_t ) 0xff ) );
+    portOUTPUT_BYTE( usPIT0, ( uint16_t )( ulOutput & ( uint32_t ) 0xff ) );
     ulOutput >>= 8;
     portOUTPUT_BYTE( usPIT0, ( uint16_t ) ( ulOutput & ( uint32_t ) 0xff ) );
 }
@@ -282,13 +275,13 @@ static void prvSetTickFrequency( uint32_t ulTickRateHz )
 
 static void prvSetTickFrequencyDefault( void )
 {
-    const uint16_t usPIT_MODE = ( uint16_t ) 0x43;
-    const uint16_t usPIT0 = ( uint16_t ) 0x40;
-    const uint16_t us8254_CTR0_MODE3 = ( uint16_t ) 0x36;
+const uint16_t usPIT_MODE = ( uint16_t ) 0x43;
+const uint16_t usPIT0 = ( uint16_t ) 0x40;
+const uint16_t us8254_CTR0_MODE3 = ( uint16_t ) 0x36;
 
     portOUTPUT_BYTE( usPIT_MODE, us8254_CTR0_MODE3 );
-    portOUTPUT_BYTE( usPIT0, 0 );
-    portOUTPUT_BYTE( usPIT0, 0 );
+    portOUTPUT_BYTE( usPIT0,0 );
+    portOUTPUT_BYTE( usPIT0,0 );
 }
 
 
diff --git a/portable/BCC/16BitDOS/PC/prtmacro.h b/portable/BCC/16BitDOS/PC/prtmacro.h
index e9e7b4ad0..5fb4ed6a4 100644
--- a/portable/BCC/16BitDOS/PC/prtmacro.h
+++ b/portable/BCC/16BitDOS/PC/prtmacro.h
@@ -40,61 +40,60 @@
  */
 
 /* Type definitions. */
-#define portCHAR          char
-#define portFLOAT         long
-#define portDOUBLE        long
-#define portLONG          long
-#define portSHORT         int
-#define portSTACK_TYPE    uint16_t
-#define portBASE_TYPE     portSHORT
+#define portCHAR        char
+#define portFLOAT       long
+#define portDOUBLE      long
+#define portLONG        long
+#define portSHORT       int
+#define portSTACK_TYPE  uint16_t
+#define portBASE_TYPE   portSHORT
 
-typedef portSTACK_TYPE   StackType_t;
-typedef short            BaseType_t;
-typedef unsigned short   UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef short BaseType_t;
+typedef unsigned short UBaseType_t;
 
-#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t     TickType_t;
-    #define portMAX_DELAY    ( TickType_t ) 0xffff
+#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t TickType_t;
+    #define portMAX_DELAY ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t     TickType_t;
-    #define portMAX_DELAY    ( TickType_t ) 0xffffffffUL
+    typedef uint32_t TickType_t;
+    #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
 /*-----------------------------------------------------------*/
 
 /* Critical section management. */
-#define portENTER_CRITICAL() \
-    __asm { pushf }          \
-    __asm { cli }            \
+#define portENTER_CRITICAL()            __asm{ pushf }  \
+                                        __asm{ cli   }  \
 
-#define portEXIT_CRITICAL()         __asm { popf }
+#define portEXIT_CRITICAL()             __asm{ popf }
 
-#define portDISABLE_INTERRUPTS()    __asm { cli }
+#define portDISABLE_INTERRUPTS()        __asm{ cli }
 
-#define portENABLE_INTERRUPTS()     __asm { sti }
+#define portENABLE_INTERRUPTS()         __asm{ sti }
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portNOP()      __asm { nop }
-#define portSTACK_GROWTH          ( -1 )
-#define portSWITCH_INT_NUMBER     0x80
-#define portYIELD()    __asm { int portSWITCH_INT_NUMBER }
-#define portDOS_TICK_RATE         ( 18.20648 )
-#define portTICK_PERIOD_MS        ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portTICKS_PER_DOS_TICK    ( ( uint16_t ) ( ( ( portDOUBLE ) configTICK_RATE_HZ / portDOS_TICK_RATE ) + 0.5 ) )
-#define portINITIAL_SW            ( ( portSTACK_TYPE ) 0x0202 ) /* Start the tasks with interrupts enabled. */
-#define portBYTE_ALIGNMENT        ( 2 )
+#define portNOP()               __asm{ nop }
+#define portSTACK_GROWTH        ( -1 )
+#define portSWITCH_INT_NUMBER   0x80
+#define portYIELD()             __asm{ int portSWITCH_INT_NUMBER }
+#define portDOS_TICK_RATE       ( 18.20648 )
+#define portTICK_PERIOD_MS      ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portTICKS_PER_DOS_TICK  ( ( uint16_t ) ( ( ( portDOUBLE ) configTICK_RATE_HZ / portDOS_TICK_RATE ) + 0.5 ) )
+#define portINITIAL_SW          ( ( portSTACK_TYPE ) 0x0202 )   /* Start the tasks with interrupts enabled. */
+#define portBYTE_ALIGNMENT      ( 2 )
 /*-----------------------------------------------------------*/
 
 /* Compiler specifics. */
-#define portINPUT_BYTE( xAddr )              inp( xAddr )
-#define portOUTPUT_BYTE( xAddr, ucValue )    outp( xAddr, ucValue )
+#define portINPUT_BYTE( xAddr )             inp( xAddr )
+#define portOUTPUT_BYTE( xAddr, ucValue )   outp( xAddr, ucValue )
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vTaskFunction, pvParameters )    void vTaskFunction( void * pvParameters )
-#define portTASK_FUNCTION( vTaskFunction, pvParameters )          void vTaskFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vTaskFunction, pvParameters ) void vTaskFunction( void *pvParameters )
+#define portTASK_FUNCTION( vTaskFunction, pvParameters ) void vTaskFunction( void *pvParameters )
 
 #endif /* PORTMACRO_H */
diff --git a/portable/BCC/16BitDOS/common/portasm.h b/portable/BCC/16BitDOS/common/portasm.h
index f78147d20..e53d257c8 100644
--- a/portable/BCC/16BitDOS/common/portasm.h
+++ b/portable/BCC/16BitDOS/common/portasm.h
@@ -48,40 +48,40 @@ void portSWITCH_CONTEXT( void );
 void portFIRST_CONTEXT( void );
 
 /* There are slightly different versions depending on whether you are building
- * to include debugger information.  If debugger information is used then there
- * are a couple of extra bytes left of the ISR stack (presumably for use by the
- * debugger).  The true stack pointer is then stored in the bp register.  We add
- * 2 to the stack pointer to remove the extra bytes before we restore our context. */
+to include debugger information.  If debugger information is used then there
+are a couple of extra bytes left of the ISR stack (presumably for use by the
+debugger).  The true stack pointer is then stored in the bp register.  We add
+2 to the stack pointer to remove the extra bytes before we restore our context. */
 
-#define portSWITCH_CONTEXT()                                                              \
-    asm { mov ax, seg pxCurrentTCB }                                                      \
-    asm { mov ds, ax }                                                                    \
-    asm { les bx, pxCurrentTCB } /* Save the stack pointer into the TCB. */               \
-    asm { mov es : 0x2[ bx ], ss }                                                        \
-    asm { mov es:[ bx ], sp }                                                                      \
-    asm { call far ptr vTaskSwitchContext } /* Perform the switch. */                     \
-    asm { mov ax, seg pxCurrentTCB }        /* Restore the stack pointer from the TCB. */ \
-    asm { mov ds, ax }                                                                    \
-    asm { les bx, dword ptr pxCurrentTCB }                                                \
-    asm { mov ss, es:[ bx + 2 ] }                                                                      \
-    asm { mov sp, es:[ bx ] }
+#define portSWITCH_CONTEXT()                                            \
+                            asm { mov   ax, seg pxCurrentTCB        }   \
+                            asm { mov   ds, ax                      }   \
+                            asm { les   bx, pxCurrentTCB            }   /* Save the stack pointer into the TCB. */      \
+                            asm { mov   es:0x2[ bx ], ss            }   \
+                            asm { mov   es:[ bx ], sp               }   \
+                            asm { call  far ptr vTaskSwitchContext  }   /* Perform the switch. */                       \
+                            asm { mov   ax, seg pxCurrentTCB        }   /* Restore the stack pointer from the TCB. */   \
+                            asm { mov   ds, ax                      }   \
+                            asm { les   bx, dword ptr pxCurrentTCB  }   \
+                            asm { mov   ss, es:[ bx + 2 ]           }   \
+                            asm { mov   sp, es:[ bx ]               }
 
-#define portFIRST_CONTEXT()                  \
-    __asm { mov ax, seg pxCurrentTCB }       \
-    __asm { mov ds, ax }                     \
-    __asm { les bx, dword ptr pxCurrentTCB } \
-    __asm { mov ss, es:[ bx + 2 ] }                         \
-    __asm { mov sp, es:[ bx ] }                             \
-    __asm { pop bp }                         \
-    __asm { pop di }                         \
-    __asm { pop si }                         \
-    __asm { pop ds }                         \
-    __asm { pop es }                         \
-    __asm { pop dx }                         \
-    __asm { pop cx }                         \
-    __asm { pop bx }                         \
-    __asm { pop ax }                         \
-    __asm { iret }
+#define portFIRST_CONTEXT()                                             \
+                            __asm { mov ax, seg pxCurrentTCB        }   \
+                            __asm { mov ds, ax                      }   \
+                            __asm { les bx, dword ptr pxCurrentTCB  }   \
+                            __asm { mov ss, es:[ bx + 2 ]           }   \
+                            __asm { mov sp, es:[ bx ]               }   \
+                            __asm { pop bp                          }   \
+                            __asm { pop di                          }   \
+                            __asm { pop si                          }   \
+                            __asm { pop ds                          }   \
+                            __asm { pop es                          }   \
+                            __asm { pop dx                          }   \
+                            __asm { pop cx                          }   \
+                            __asm { pop bx                          }   \
+                            __asm { pop ax                          }   \
+                            __asm { iret                            }
 
 
-#endif /* ifndef PORT_ASM_H */
+#endif
diff --git a/portable/BCC/16BitDOS/common/portcomn.c b/portable/BCC/16BitDOS/common/portcomn.c
index d9a1a43c8..69ab45ba7 100644
--- a/portable/BCC/16BitDOS/common/portcomn.c
+++ b/portable/BCC/16BitDOS/common/portcomn.c
@@ -27,16 +27,16 @@
  */
 
 /*
- * Changes from V1.00:
- *
- + pxPortInitialiseStack() now initialises the stack of new tasks to the
- +    same format used by the compiler.  This allows the compiler generated
- +    interrupt mechanism to be used for context switches.
- +
- + Changes from V2.6.1
- +
- + Move usPortCheckFreeStackSpace() to tasks.c.
- */
+Changes from V1.00:
+
+    + pxPortInitialiseStack() now initialises the stack of new tasks to the
+      same format used by the compiler.  This allows the compiler generated
+      interrupt mechanism to be used for context switches.
+
+Changes from V2.6.1
+
+    + Move usPortCheckFreeStackSpace() to tasks.c.
+*/
 
 
 #include <dos.h>
@@ -46,14 +46,12 @@
 /*-----------------------------------------------------------*/
 
 /* See header file for description. */
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
 {
-    StackType_t DS_Reg = 0;
+StackType_t DS_Reg = 0;
 
     /* Place a few bytes of known values on the bottom of the stack.
-     * This is just useful for debugging. */
+    This is just useful for debugging. */
 
     *pxTopOfStack = 0x1111;
     pxTopOfStack--;
@@ -70,8 +68,8 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
     /*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */
 
     /* We are going to start the scheduler using a return from interrupt
-     * instruction to load the program counter, so first there would be the
-     * function call with parameters preamble. */
+    instruction to load the program counter, so first there would be the
+    function call with parameters preamble. */
 
     *pxTopOfStack = FP_SEG( pvParameters );
     pxTopOfStack--;
@@ -91,8 +89,8 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
     pxTopOfStack--;
 
     /* The remaining registers would be pushed on the stack by our context
-     * switch function.  These are loaded with values simply to make debugging
-     * easier. */
+    switch function.  These are loaded with values simply to make debugging
+    easier. */
     *pxTopOfStack = ( StackType_t ) 0xAAAA; /* AX */
     pxTopOfStack--;
     *pxTopOfStack = ( StackType_t ) 0xBBBB; /* BX */
@@ -105,11 +103,9 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
     pxTopOfStack--;
 
     /* We need the true data segment. */
-    __asm {
-        MOV DS_Reg, DS
-    };
+    __asm{  MOV DS_Reg, DS };
 
-    *pxTopOfStack = DS_Reg;                 /* DS */
+    *pxTopOfStack = DS_Reg;                     /* DS */
     pxTopOfStack--;
     *pxTopOfStack = ( StackType_t ) 0x0123; /* SI */
     pxTopOfStack--;

From 5dbfd380f0e9cca8dddd9ddddbe0c750af460ff5 Mon Sep 17 00:00:00 2001
From: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Date: Fri, 8 Dec 2023 03:24:20 +0800
Subject: [PATCH 154/424] Add coverity example (#870)

* Add coverity example

* Update for CI

* Fix for CI 2

* Update kernel_misra.config

* Rename coverity example to coverity

* Update FreeRTOSConfig.h for coverity project

* Update MISRA.md

* Move coverity config to coverity_misra.config

* Update coverity misra config

* Add README.md file

* Update FreeRTOSConfig.h for coverity

* Fix uncrustify and spell

* Update README.md for relative link path

Update README.md for relative link path

* Update README.md for relative link 2

* Update MISRA.md for relateive path

* Fix for format

* Update coverity_misra.config

* Update configuration folder

* Update README.md for link

* Code review suggestions

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Ubuntu <ubuntu@ip-172-31-34-245.ap-northeast-1.compute.internal>
Co-authored-by: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Co-authored-by: Soren Ptak <ptaksoren@gmail.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 .github/scripts/kernel_checker.py       |   3 +-
 MISRA.md                                |  40 +------
 examples/cmake_example/main.c           |  15 ++-
 examples/coverity/CMakeLists.txt        |  39 +++++++
 examples/coverity/FreeRTOSConfig.h      | 135 ++++++++++++++++++++++++
 examples/coverity/README.md             |  58 ++++++++++
 examples/coverity/coverity_misra.config |  97 +++++++++++++++++
 7 files changed, 343 insertions(+), 44 deletions(-)
 create mode 100644 examples/coverity/CMakeLists.txt
 create mode 100644 examples/coverity/FreeRTOSConfig.h
 create mode 100644 examples/coverity/README.md
 create mode 100644 examples/coverity/coverity_misra.config

diff --git a/.github/scripts/kernel_checker.py b/.github/scripts/kernel_checker.py
index 9251c866c..3373cd50c 100755
--- a/.github/scripts/kernel_checker.py
+++ b/.github/scripts/kernel_checker.py
@@ -62,7 +62,8 @@ KERNEL_IGNORED_EXTENSIONS = [
     '.bat',
     '.sh',
     '.txt',
-    '.cmake'
+    '.cmake',
+    '.config'
 ]
 
 KERNEL_ASM_EXTENSIONS = [
diff --git a/MISRA.md b/MISRA.md
index 734a51291..8d501e0bd 100644
--- a/MISRA.md
+++ b/MISRA.md
@@ -8,8 +8,8 @@ has to be efficient. To achieve that and to increase the performance, it
 deviates from some MISRA rules. The specific deviations, suppressed inline,
 are listed below.
 
-Additionally, [MISRA configuration](#misra-configuration) contains project
-wide deviations.
+Additionally, [MISRA configuration file](examples/coverity/coverity_misra.config)
+contains project wide deviations.
 
 ### Suppressed with Coverity Comments
 To find the violation references in the source files run grep on the source code
@@ -116,39 +116,3 @@ _Ref 21.6.1_
  - The Standard Library function snprintf is used in vTaskListTasks and
    vTaskGetRunTimeStatistics APIs, both of which are utility functions only and
    are not considered part of core kernel implementation.
-
-### MISRA configuration
-
-Copy below content to `misra.conf` to run Coverity on FreeRTOS-Kernel.
-
-```
-// MISRA C-2012 Rules
-{
-    version : "2.0",
-    standard : "c2012",
-    title: "Coverity MISRA Configuration",
-    deviations : [
-        // Disable the following rules.
-        {
-            deviation: "Directive 4.8",
-            reason: "HeapRegion_t and HeapStats_t are used only in heap files but declared in portable.h which is included in multiple source files. As a result, these definitions appear in multiple source files where they are not used."
-        },
-        {
-            deviation: "Directive 4.9",
-            reason: "FreeRTOS-Kernel is optimised to work on small micro-controllers. To achieve that, function-like macros are used."
-        },
-        {
-            deviation: "Rule 1.2",
-            reason: "The __attribute__ tags are used via macros which are defined in port files."
-        },
-        {
-            deviation: "Rule 3.1",
-            reason: "We post HTTP links in code comments which contain // inside comments blocks."
-        },
-        {
-            deviation: "Rule 8.7",
-            reason: "API functions are not used by the library outside of the files they are defined; however, they must be externally visible in order to be used by an application."
-        }
-    ]
-}
-```
diff --git a/examples/cmake_example/main.c b/examples/cmake_example/main.c
index bf1717e95..4825f2d19 100644
--- a/examples/cmake_example/main.c
+++ b/examples/cmake_example/main.c
@@ -33,17 +33,16 @@
  * https://freertos.org/FreeRTOS-quick-start-guide.html
  */
 
+/* FreeRTOS includes. */
 #include <FreeRTOS.h>
 #include <task.h>
 #include <queue.h>
 #include <timers.h>
 #include <semphr.h>
 
+/* Standard includes. */
 #include <stdio.h>
 
-static StaticTask_t exampleTaskTCB;
-static StackType_t exampleTaskStack[ configMINIMAL_STACK_SIZE ];
-
 void exampleTask( void * parameters )
 {
     /* Unused parameters. */
@@ -55,9 +54,13 @@ void exampleTask( void * parameters )
         vTaskDelay( 100 ); /* delay 100 ticks */
     }
 }
+/*-----------------------------------------------------------*/
 
 void main( void )
 {
+    static StaticTask_t exampleTaskTCB;
+    static StackType_t exampleTaskStack[ configMINIMAL_STACK_SIZE ];
+
     printf( "Example FreeRTOS Project\n" );
 
     xTaskCreateStatic( exampleTask,
@@ -65,8 +68,8 @@ void main( void )
                        configMINIMAL_STACK_SIZE,
                        NULL,
                        configMAX_PRIORITIES - 1,
-                       exampleTaskStack,
-                       &exampleTaskTCB );
+                       &( exampleTaskStack[ 0 ] ),
+                       &( exampleTaskTCB ) );
 
     /* Start the scheduler. */
     vTaskStartScheduler();
@@ -76,6 +79,7 @@ void main( void )
         /* Should not reach here. */
     }
 }
+/*-----------------------------------------------------------*/
 
 void vApplicationStackOverflowHook( TaskHandle_t xTask,
                                     char * pcTaskName )
@@ -85,3 +89,4 @@ void vApplicationStackOverflowHook( TaskHandle_t xTask,
     ( void ) xTask;
     ( void ) pcTaskName;
 }
+/*-----------------------------------------------------------*/
diff --git a/examples/coverity/CMakeLists.txt b/examples/coverity/CMakeLists.txt
new file mode 100644
index 000000000..b4538655e
--- /dev/null
+++ b/examples/coverity/CMakeLists.txt
@@ -0,0 +1,39 @@
+cmake_minimum_required(VERSION 3.15)
+
+project(coverity)
+
+set(FREERTOS_KERNEL_PATH "../../")
+FILE(GLOB FREERTOS_KERNEL_SOURCE ${FREERTOS_KERNEL_PATH}*.c)
+
+# Coverity incorrectly infers the type of pdTRUE and pdFALSE as boolean because
+# of their names. This generates multiple false positive warnings about type
+# mismatch. Replace pdTRUE with pdPASS and pdFALSE with pdFAIL to avoid these
+# false positive warnings. This workaround will not be needed after Coverity
+# fixes the issue of incorrectly inferring the type of pdTRUE and pdFALSE as
+# boolean.
+add_custom_target(fix_source ALL
+                  COMMAND sed -i -b -e 's/pdFALSE/pdFAIL/g' -e 's/pdTRUE/pdPASS/g' ${FREERTOS_KERNEL_SOURCE}
+                  DEPENDS ${FREERTOS_KERNEL_SOURCE})
+
+# Add the freertos_config for FreeRTOS-Kernel.
+add_library(freertos_config INTERFACE)
+
+target_include_directories(freertos_config
+                           INTERFACE
+                           ./)
+
+# Select the heap. Values between 1-5 will pick a heap.
+set(FREERTOS_HEAP "3" CACHE STRING "" FORCE)
+
+# Select the FreeRTOS port.
+set(FREERTOS_PORT "TEMPLATE" CACHE STRING "" FORCE)
+
+# Add the FreeRTOS-Kernel subdirectory.
+add_subdirectory(${FREERTOS_KERNEL_PATH} FreeRTOS-Kernel)
+
+add_executable(${PROJECT_NAME}
+               ../cmake_example/main.c)
+
+add_dependencies(${PROJECT_NAME} fix_source)
+
+target_link_libraries(${PROJECT_NAME} freertos_kernel freertos_config)
diff --git a/examples/coverity/FreeRTOSConfig.h b/examples/coverity/FreeRTOSConfig.h
new file mode 100644
index 000000000..4d957872d
--- /dev/null
+++ b/examples/coverity/FreeRTOSConfig.h
@@ -0,0 +1,135 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/******************************************************************************/
+/* Hardware description related definitions. **********************************/
+/******************************************************************************/
+
+#define configCPU_CLOCK_HZ    ( ( unsigned long ) 20000000 )
+
+/******************************************************************************/
+/* Scheduling behaviour related definitions. **********************************/
+/******************************************************************************/
+
+#define configTICK_RATE_HZ                         ( 100U )
+#define configUSE_PREEMPTION                       1
+#define configUSE_TIME_SLICING                     1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION    0
+#define configUSE_TICKLESS_IDLE                    1
+#define configMAX_PRIORITIES                       5U
+#define configMINIMAL_STACK_SIZE                   128U
+#define configMAX_TASK_NAME_LEN                    4U
+#define configTICK_TYPE_WIDTH_IN_BITS              TICK_TYPE_WIDTH_64_BITS
+#define configIDLE_SHOULD_YIELD                    1
+#define configTASK_NOTIFICATION_ARRAY_ENTRIES      1U
+#define configQUEUE_REGISTRY_SIZE                  0U
+#define configENABLE_BACKWARD_COMPATIBILITY        1
+#define configNUM_THREAD_LOCAL_STORAGE_POINTERS    0
+#define configSTACK_DEPTH_TYPE                     size_t
+#define configMESSAGE_BUFFER_LENGTH_TYPE           size_t
+#define configUSE_NEWLIB_REENTRANT                 0
+
+/******************************************************************************/
+/* Software timer related definitions. ****************************************/
+/******************************************************************************/
+
+#define configUSE_TIMERS                1
+#define configTIMER_TASK_PRIORITY       ( configMAX_PRIORITIES - 1U )
+#define configTIMER_TASK_STACK_DEPTH    configMINIMAL_STACK_SIZE
+#define configTIMER_QUEUE_LENGTH        10U
+
+/******************************************************************************/
+/* Memory allocation related definitions. *************************************/
+/******************************************************************************/
+
+#define configSUPPORT_STATIC_ALLOCATION              1
+#define configSUPPORT_DYNAMIC_ALLOCATION             1
+#define configTOTAL_HEAP_SIZE                        4096U
+#define configAPPLICATION_ALLOCATED_HEAP             1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP    0
+#define configUSE_MINI_LIST_ITEM                     0
+
+/******************************************************************************/
+/* Interrupt nesting behaviour configuration. *********************************/
+/******************************************************************************/
+
+#define configKERNEL_INTERRUPT_PRIORITY          0U
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY     0U
+#define configMAX_API_CALL_INTERRUPT_PRIORITY    0U
+
+/******************************************************************************/
+/* Hook and callback function related definitions. ****************************/
+/******************************************************************************/
+
+#define configUSE_IDLE_HOOK                   0
+#define configUSE_TICK_HOOK                   0
+#define configUSE_MALLOC_FAILED_HOOK          0
+#define configUSE_DAEMON_TASK_STARTUP_HOOK    0
+#define configCHECK_FOR_STACK_OVERFLOW        0
+
+/******************************************************************************/
+/* Run time and task stats gathering related definitions. *********************/
+/******************************************************************************/
+
+#define configGENERATE_RUN_TIME_STATS           0
+#define configUSE_TRACE_FACILITY                0
+#define configUSE_STATS_FORMATTING_FUNCTIONS    0
+#define configKERNEL_PROVIDED_STATIC_MEMORY     1
+
+/******************************************************************************/
+/* Definitions that include or exclude functionality. *************************/
+/******************************************************************************/
+
+#define configUSE_TASK_NOTIFICATIONS           1
+#define configUSE_MUTEXES                      1
+#define configUSE_RECURSIVE_MUTEXES            1
+#define configUSE_COUNTING_SEMAPHORES          1
+#define configUSE_QUEUE_SETS                   1
+#define configUSE_APPLICATION_TASK_TAG         1
+#define INCLUDE_vTaskPrioritySet               1
+#define INCLUDE_uxTaskPriorityGet              1
+#define INCLUDE_vTaskDelete                    1
+#define INCLUDE_vTaskSuspend                   1
+#define INCLUDE_xResumeFromISR                 1
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         1
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    1
+#define INCLUDE_xTaskGetIdleTaskHandle         1
+#define INCLUDE_eTaskGetState                  1
+#define INCLUDE_xEventGroupSetBitFromISR       1
+#define INCLUDE_xTimerPendFunctionCall         1
+#define INCLUDE_xTaskAbortDelay                1
+#define INCLUDE_xTaskGetHandle                 1
+#define INCLUDE_xTaskResumeFromISR             1
+
+#endif /* FREERTOS_CONFIG_H */
diff --git a/examples/coverity/README.md b/examples/coverity/README.md
new file mode 100644
index 000000000..0daed7b22
--- /dev/null
+++ b/examples/coverity/README.md
@@ -0,0 +1,58 @@
+# MISRA Compliance for FreeRTOS-Kernel
+FreeRTOS-Kernel is MISRA C:2012 compliant. This directory contains a project to
+run [Synopsys Coverity](https://www.synopsys.com/software-integrity/security-testing/static-analysis-sast.html)
+for checking MISRA compliance.
+
+> **Note**
+Coverity version 2022.6.1 incorrectly infers the type of `pdTRUE` and `pdFALSE`
+as boolean because of their names, resulting in multiple false positive warnings
+about type mismatch. We replace `pdTRUE` with `pdPASS` and `pdFALSE` with
+`pdFAIL` to avoid these false positive warnings. This workaround will not be
+needed after Coverity fixes the issue of incorrectly inferring the type of
+`pdTRUE` and `pdFALSE` as boolean.
+
+Deviations from the MISRA C:2012 guidelines are documented in
+[MISRA.md](../../MISRA.md) and [coverity_misra.config](coverity_misra.config)
+files.
+
+## Getting Started
+### Prerequisites
+Coverity can be run on any platform mentioned [here](https://sig-docs.synopsys.com/polaris/topics/c_coverity-compatible-platforms.html).
+The following are the prerequisites to generate coverity report:
+
+1. CMake version > 3.13.0 (You can check whether you have this by typing `cmake --version`).
+2. GCC compiler.
+    - See download and installation instructions [here](https://gcc.gnu.org/install/).
+3. Clone the repo using the following command:
+    - `git clone https://github.com/FreeRTOS/FreeRTOS-Kernel.git ./FreeRTOS-Kernel`
+
+### Generating Report
+Go to the root directory of the FreeRTOS-Kernel repo and run the following
+commands in a terminal:
+1. Update the compiler configuration in Coverity:
+  ~~~
+  cov-configure --force --compiler cc --comptype gcc
+  ~~~
+2. Create the build files using CMake in a `build` directory:
+  ~~~
+  cmake -B build -S examples/coverity
+  ~~~
+3. Build the (pseudo) application:
+  ~~~
+  cd build/
+  cov-build --emit-complementary-info --dir cov-out make
+  ~~~
+4. Go to the Coverity output directory (`cov-out`) and begin Coverity static
+   analysis:
+  ~~~
+  cd cov-out/
+  cov-analyze --dir ./cov-out \
+    --coding-standard-config ../examples/coverity/coverity_misra.config \
+    --tu-pattern "file('.*/FreeRTOS/Source/[A-Za-z_]*\.c')
+  ~~~
+5. Generate the HTML report:
+  ~~~
+  cov-format-errors --dir ./cov-out --html-output html-output
+  ~~~
+
+HTML report should now be generated in a directory named `html-output`.
diff --git a/examples/coverity/coverity_misra.config b/examples/coverity/coverity_misra.config
new file mode 100644
index 000000000..101b20031
--- /dev/null
+++ b/examples/coverity/coverity_misra.config
@@ -0,0 +1,97 @@
+// MISRA C-2012 Rules
+
+{
+    version : "2.0",
+    standard : "c2012",
+    title: "Coverity MISRA Configuration",
+    deviations : [
+        // Disable the following rules.
+        {
+            deviation: "Rule 3.1",
+            reason: "We post HTTP links in code comments which contain // inside comments blocks."
+        },
+        {
+            deviation: "Rule 14.4",
+            reason: "do while( 0 ) pattern is used in macros to prevent extra semi-colon."
+        },
+
+        // Disable the following advisory rules and directives.
+        {
+            deviation: "Directive 4.4",
+            reason: "Code snippet is used in comment to help explanation."
+        },
+        {
+            deviation: "Directive 4.5",
+            reason: "Allow names that MISRA considers ambiguous."
+        },
+        {
+            deviation: "Directive 4.6",
+            reason: "Allow port to use primitive type with typedefs."
+        },
+        {
+            deviation: "Directive 4.8",
+            reason: "HeapRegion_t and HeapStats_t are used only in heap files but declared in portable.h which is included in multiple source files. As a result, these definitions appear in multiple source files where they are not used."
+        },
+        {
+            deviation: "Directive 4.9",
+            reason: "FreeRTOS-Kernel is optimised to work on small micro-controllers. To achieve that, function-like macros are used."
+        },
+        {
+            deviation: "Rule 2.3",
+            reason: "FreeRTOS defines types which is used in application."
+        },
+        {
+            deviation: "Rule 2.4",
+            reason: "Allow to define unused tag."
+        },
+        {
+            deviation: "Rule 2.5",
+            reason: "Allow to define unused macro."
+        },
+        {
+            deviation: "Rule 5.9",
+            reason: "Allow to define identifier with the same name in structure and global variable."
+        },
+        {
+            deviation: "Rule 8.7",
+            reason: "API functions are not used by the library outside of the files they are defined; however, they must be externally visible in order to be used by an application."
+        },
+        {
+            deviation: "Rule 8.9",
+            reason: "Allow to object to be defined in wider scope for debug purpose."
+        },
+        {
+            deviation: "Rule 8.13",
+            reason: "Allow to not to use const-qualified type for callback function."
+        },
+        {
+            deviation: "Rule 11.4",
+            reason: "Allow to convert between a pointer to object and an interger type for stack alignment."
+        },
+        {
+            deviation: "Rule 15.4",
+            reason: "Allow to use multiple break statements in a loop."
+        },
+        {
+            deviation: "Rule 15.5",
+            reason: "Allow to use multiple points of exit."
+        },
+        {
+            deviation: "Rule 17.8",
+            reason: "Allow to update the parameters of a function."
+        },
+        {
+            deviation: "Rule 18.4",
+            reason: "Allow to use pointer arithmetic."
+        },
+        {
+            deviation: "Rule 19.2",
+            reason: "Allow to use union."
+        },
+        {
+            deviation: "Rule 20.5",
+            reason: "Allow to use #undef for MPU wrappers."
+        }
+    ]
+}
+

From a2712b5e3833ad60b88ea7b48bb482777947760f Mon Sep 17 00:00:00 2001
From: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Date: Fri, 8 Dec 2023 14:06:55 +0800
Subject: [PATCH 155/424] Add constanst suffix to prevent potential type
 conversion (#921)

Co-authored-by: Ubuntu <ubuntu@ip-172-31-34-245.ap-northeast-1.compute.internal>
---
 include/stack_macros.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/stack_macros.h b/include/stack_macros.h
index f53afb2cd..bd9ec2770 100644
--- a/include/stack_macros.h
+++ b/include/stack_macros.h
@@ -91,7 +91,7 @@
     #define taskCHECK_FOR_STACK_OVERFLOW()                                                      \
     do {                                                                                        \
         const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack;                 \
-        const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5;                                  \
+        const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5U;                                 \
                                                                                                 \
         if( ( pulStack[ 0 ] != ulCheckValue ) ||                                                \
             ( pulStack[ 1 ] != ulCheckValue ) ||                                                \

From a79752a04a4334fc0b51d6555ebbb84f0ed71204 Mon Sep 17 00:00:00 2001
From: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Date: Fri, 8 Dec 2023 14:49:42 +0800
Subject: [PATCH 156/424] Remove lint suppression comment (#920)

Remove lint suppression comment
---
 event_groups.c     |  13 +++---
 include/list.h     |   2 +-
 include/portable.h |   2 +-
 include/queue.h    |   4 +-
 include/task.h     |  22 +++++-----
 include/timers.h   |  10 ++---
 list.c             |  13 +++---
 queue.c            |  81 +++++++++++++++-------------------
 stream_buffer.c    |  51 +++++++++++-----------
 tasks.c            | 105 +++++++++++++++++++++------------------------
 timers.c           |  36 +++++++---------
 11 files changed, 155 insertions(+), 184 deletions(-)

diff --git a/event_groups.c b/event_groups.c
index cb154a82c..3fac0d9c8 100644
--- a/event_groups.c
+++ b/event_groups.c
@@ -40,11 +40,10 @@
 #include "timers.h"
 #include "event_groups.h"
 
-/* Lint e961, e750 and e9021 are suppressed as a MISRA exception justified
- * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+/* The MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
  * for the header files above, but not in this file, in order to generate the
  * correct privileged Vs unprivileged linkage and placement. */
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021 See comment above. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
 
 typedef struct EventGroupDef_t
 {
@@ -94,7 +93,7 @@ static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits,
              * event group structure. */
             volatile size_t xSize = sizeof( StaticEventGroup_t );
             configASSERT( xSize == sizeof( EventGroup_t ) );
-        } /*lint !e529 xSize is referenced if configASSERT() is defined. */
+        }
         #endif /* configASSERT_DEFINED */
 
         /* The user has provided a statically allocated event group - use it. */
@@ -166,7 +165,7 @@ static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits,
         }
         else
         {
-            traceEVENT_GROUP_CREATE_FAILED(); /*lint !e9063 Else branch only exists to allow tracing and does not generate code if trace macros are not defined. */
+            traceEVENT_GROUP_CREATE_FAILED();
         }
 
         traceRETURN_xEventGroupCreate( pxEventBits );
@@ -533,7 +532,7 @@ EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup )
     traceRETURN_xEventGroupGetBitsFromISR( uxReturn );
 
     return uxReturn;
-} /*lint !e818 EventGroupHandle_t is a typedef used in other functions to so can't be pointer to const. */
+}
 /*-----------------------------------------------------------*/
 
 EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup,
@@ -555,7 +554,7 @@ EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup,
     configASSERT( ( uxBitsToSet & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
 
     pxList = &( pxEventBits->xTasksWaitingForBits );
-    pxListEnd = listGET_END_MARKER( pxList ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+    pxListEnd = listGET_END_MARKER( pxList );
     vTaskSuspendAll();
     {
         traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet );
diff --git a/include/list.h b/include/list.h
index c86eb7165..7084834dc 100644
--- a/include/list.h
+++ b/include/list.h
@@ -151,7 +151,7 @@ struct xLIST_ITEM
     struct xLIST * configLIST_VOLATILE pxContainer;     /**< Pointer to the list in which this list item is placed (if any). */
     listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE          /**< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
 };
-typedef struct xLIST_ITEM ListItem_t;                   /* For some reason lint wants this as two separate definitions. */
+typedef struct xLIST_ITEM ListItem_t;
 
 #if ( configUSE_MINI_LIST_ITEM == 1 )
     struct xMINI_LIST_ITEM
diff --git a/include/portable.h b/include/portable.h
index 615d77d5a..ab8a26df0 100644
--- a/include/portable.h
+++ b/include/portable.h
@@ -200,7 +200,7 @@ size_t xPortGetMinimumEverFreeHeapSize( void ) PRIVILEGED_FUNCTION;
  *
  * This hook function is called when allocation failed.
  */
-    void vApplicationMallocFailedHook( void ); /*lint !e526 Symbol not defined as it is an application callback. */
+    void vApplicationMallocFailedHook( void );
 #endif
 
 /*
diff --git a/include/queue.h b/include/queue.h
index a3d2400f4..b00a07f37 100644
--- a/include/queue.h
+++ b/include/queue.h
@@ -1554,7 +1554,7 @@ BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex ) PRIVILEGED_FUNCTION;
  */
 #if ( configQUEUE_REGISTRY_SIZE > 0 )
     void vQueueAddToRegistry( QueueHandle_t xQueue,
-                              const char * pcQueueName ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+                              const char * pcQueueName ) PRIVILEGED_FUNCTION;
 #endif
 
 /*
@@ -1583,7 +1583,7 @@ BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex ) PRIVILEGED_FUNCTION;
  * returned.
  */
 #if ( configQUEUE_REGISTRY_SIZE > 0 )
-    const char * pcQueueGetName( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+    const char * pcQueueGetName( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
 #endif
 
 /*
diff --git a/include/task.h b/include/task.h
index 9ed722c15..5a845f0ef 100644
--- a/include/task.h
+++ b/include/task.h
@@ -144,7 +144,7 @@ typedef struct xMEMORY_REGION
 typedef struct xTASK_PARAMETERS
 {
     TaskFunction_t pvTaskCode;
-    const char * pcName; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+    const char * pcName;
     configSTACK_DEPTH_TYPE usStackDepth;
     void * pvParameters;
     UBaseType_t uxPriority;
@@ -160,7 +160,7 @@ typedef struct xTASK_PARAMETERS
 typedef struct xTASK_STATUS
 {
     TaskHandle_t xHandle;                         /* The handle of the task to which the rest of the information in the structure relates. */
-    const char * pcTaskName;                      /* A pointer to the task's name.  This value will be invalid if the task was deleted since the structure was populated! */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+    const char * pcTaskName;                      /* A pointer to the task's name.  This value will be invalid if the task was deleted since the structure was populated! */
     UBaseType_t xTaskNumber;                      /* A number unique to the task. */
     eTaskState eCurrentState;                     /* The state in which the task existed when the structure was populated. */
     UBaseType_t uxCurrentPriority;                /* The priority at which the task was running (may be inherited) when the structure was populated. */
@@ -379,7 +379,7 @@ typedef enum
  */
 #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
     BaseType_t xTaskCreate( TaskFunction_t pxTaskCode,
-                            const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+                            const char * const pcName,
                             const configSTACK_DEPTH_TYPE usStackDepth,
                             void * const pvParameters,
                             UBaseType_t uxPriority,
@@ -388,7 +388,7 @@ typedef enum
 
 #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
     BaseType_t xTaskCreateAffinitySet( TaskFunction_t pxTaskCode,
-                                       const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+                                       const char * const pcName,
                                        const configSTACK_DEPTH_TYPE usStackDepth,
                                        void * const pvParameters,
                                        UBaseType_t uxPriority,
@@ -506,7 +506,7 @@ typedef enum
  */
 #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
     TaskHandle_t xTaskCreateStatic( TaskFunction_t pxTaskCode,
-                                    const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+                                    const char * const pcName,
                                     const uint32_t ulStackDepth,
                                     void * const pvParameters,
                                     UBaseType_t uxPriority,
@@ -516,7 +516,7 @@ typedef enum
 
 #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
     TaskHandle_t xTaskCreateStaticAffinitySet( TaskFunction_t pxTaskCode,
-                                               const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+                                               const char * const pcName,
                                                const uint32_t ulStackDepth,
                                                void * const pvParameters,
                                                UBaseType_t uxPriority,
@@ -1745,7 +1745,7 @@ UBaseType_t uxTaskGetNumberOfTasks( void ) PRIVILEGED_FUNCTION;
  * \defgroup pcTaskGetName pcTaskGetName
  * \ingroup TaskUtils
  */
-char * pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+char * pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION;
 
 /**
  * task. h
@@ -1764,7 +1764,7 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION; /*lint !e
  * \ingroup TaskUtils
  */
 #if ( INCLUDE_xTaskGetHandle == 1 )
-    TaskHandle_t xTaskGetHandle( const char * pcNameToQuery ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+    TaskHandle_t xTaskGetHandle( const char * pcNameToQuery ) PRIVILEGED_FUNCTION;
 #endif
 
 /**
@@ -1978,7 +1978,7 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION; /*lint !e
     /* MISRA Ref 8.6.1 [External linkage] */
     /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-86 */
     /* coverity[misra_c_2012_rule_8_6_violation] */
-    void vApplicationTickHook( void ); /*lint !e526 Symbol not defined as it is an application callback. */
+    void vApplicationTickHook( void );
 
 #endif
 
@@ -1999,7 +1999,7 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION; /*lint !e
  */
     void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer,
                                         StackType_t ** ppxIdleTaskStackBuffer,
-                                        uint32_t * pulIdleTaskStackSize ); /*lint !e526 Symbol not defined as it is an application callback. */
+                                        uint32_t * pulIdleTaskStackSize );
 
 /**
  * task.h
@@ -2349,7 +2349,7 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION; /*lint !e
  */
 #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configUSE_TRACE_FACILITY == 1 ) )
     void vTaskGetRunTimeStatistics( char * pcWriteBuffer,
-                                    size_t uxBufferLength ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+                                    size_t uxBufferLength ) PRIVILEGED_FUNCTION;
 #endif
 
 /**
diff --git a/include/timers.h b/include/timers.h
index 1653dbb3a..e874d2434 100644
--- a/include/timers.h
+++ b/include/timers.h
@@ -34,10 +34,8 @@
     #error "include FreeRTOS.h must appear in source files before include timers.h"
 #endif
 
-/*lint -save -e537 This headers are only multiply included if the application code
- * happens to also be including task.h. */
 #include "task.h"
-/*lint -restore */
+
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
@@ -229,7 +227,7 @@ typedef void (* PendedFunction_t)( void * arg1,
  * @endverbatim
  */
 #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-    TimerHandle_t xTimerCreate( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+    TimerHandle_t xTimerCreate( const char * const pcTimerName,
                                 const TickType_t xTimerPeriodInTicks,
                                 const BaseType_t xAutoReload,
                                 void * const pvTimerID,
@@ -359,7 +357,7 @@ typedef void (* PendedFunction_t)( void * arg1,
  * @endverbatim
  */
 #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
-    TimerHandle_t xTimerCreateStatic( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+    TimerHandle_t xTimerCreateStatic( const char * const pcTimerName,
                                       const TickType_t xTimerPeriodInTicks,
                                       const BaseType_t xAutoReload,
                                       void * const pvTimerID,
@@ -1253,7 +1251,7 @@ TaskHandle_t xTimerGetTimerDaemonTaskHandle( void ) PRIVILEGED_FUNCTION;
  *
  * @return The name assigned to the timer specified by the xTimer parameter.
  */
-const char * pcTimerGetName( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+const char * pcTimerGetName( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
 
 /**
  * void vTimerSetReloadMode( TimerHandle_t xTimer, const BaseType_t xAutoReload );
diff --git a/list.c b/list.c
index ab5bf5653..907300896 100644
--- a/list.c
+++ b/list.c
@@ -37,11 +37,10 @@
 #include "FreeRTOS.h"
 #include "list.h"
 
-/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified
- * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be
+/* The MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be
  * defined for the header files above, but not in this file, in order to
  * generate the correct privileged Vs unprivileged linkage and placement. */
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
 
 /*-----------------------------------------------------------
 * PUBLIC LIST API documented in list.h
@@ -54,7 +53,7 @@ void vListInitialise( List_t * const pxList )
     /* The list structure contains a list item which is used to mark the
      * end of the list.  To initialise the list the list end is inserted
      * as the only list entry. */
-    pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+    pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd );
 
     listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( &( pxList->xListEnd ) );
 
@@ -64,8 +63,8 @@ void vListInitialise( List_t * const pxList )
 
     /* The list end next and previous pointers point to itself so we know
      * when the list is empty. */
-    pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd );     /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
-    pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+    pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd );
+    pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );
 
     /* Initialize the remaining fields of xListEnd when it is a proper ListItem_t */
     #if ( configUSE_MINI_LIST_ITEM == 0 )
@@ -190,7 +189,7 @@ void vListInsert( List_t * const pxList,
         *      configMAX_SYSCALL_INTERRUPT_PRIORITY.
         **********************************************************************/
 
-        for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */
+        for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext )
         {
             /* There is nothing to do here, just iterating to the wanted
              * insertion position. */
diff --git a/queue.c b/queue.c
index 6a462607a..18618202c 100644
--- a/queue.c
+++ b/queue.c
@@ -42,11 +42,10 @@
     #include "croutine.h"
 #endif
 
-/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified
- * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+/* The MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
  * for the header files above, but not in this file, in order to generate the
  * correct privileged Vs unprivileged linkage and placement. */
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
 
 
 /* Constants used with the cRxLock and cTxLock structure members. */
@@ -153,7 +152,7 @@ typedef xQUEUE Queue_t;
  * more user friendly. */
     typedef struct QUEUE_REGISTRY_ITEM
     {
-        const char * pcQueueName; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+        const char * pcQueueName;
         QueueHandle_t xHandle;
     } xQueueRegistryItem;
 
@@ -318,10 +317,10 @@ BaseType_t xQueueGenericReset( QueueHandle_t xQueue,
     {
         taskENTER_CRITICAL();
         {
-            pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
+            pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize );
             pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;
             pxQueue->pcWriteTo = pxQueue->pcHead;
-            pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
+            pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize );
             pxQueue->cRxLock = queueUNLOCKED;
             pxQueue->cTxLock = queueUNLOCKED;
 
@@ -405,7 +404,7 @@ BaseType_t xQueueGenericReset( QueueHandle_t xQueue,
 
                 /* This assertion cannot be branch covered in unit tests */
                 configASSERT( xSize == sizeof( Queue_t ) ); /* LCOV_EXCL_BR_LINE */
-                ( void ) xSize;                             /* Keeps lint quiet when configASSERT() is not defined. */
+                ( void ) xSize;                             /* Prevent unused variable warning when configASSERT() is not defined. */
             }
             #endif /* configASSERT_DEFINED */
 
@@ -531,7 +530,7 @@ BaseType_t xQueueGenericReset( QueueHandle_t xQueue,
                 /* Jump past the queue structure to find the location of the queue
                  * storage area. */
                 pucQueueStorage = ( uint8_t * ) pxNewQueue;
-                pucQueueStorage += sizeof( Queue_t ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
+                pucQueueStorage += sizeof( Queue_t );
 
                 #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
                 {
@@ -717,7 +716,7 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength,
         traceRETURN_xQueueGetMutexHolder( pxReturn );
 
         return pxReturn;
-    } /*lint !e818 xSemaphore cannot be a pointer to const because it is a typedef. */
+    }
 
 #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */
 /*-----------------------------------------------------------*/
@@ -747,7 +746,7 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength,
         traceRETURN_xQueueGetMutexHolderFromISR( pxReturn );
 
         return pxReturn;
-    } /*lint !e818 xSemaphore cannot be a pointer to const because it is a typedef. */
+    }
 
 #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */
 /*-----------------------------------------------------------*/
@@ -957,9 +956,6 @@ BaseType_t xQueueGenericSend( QueueHandle_t xQueue,
     }
     #endif
 
-    /*lint -save -e904 This function relaxes the coding standard somewhat to
-     * allow return statements within the function itself.  This is done in the
-     * interest of execution time efficiency. */
     for( ; ; )
     {
         taskENTER_CRITICAL();
@@ -1154,7 +1150,7 @@ BaseType_t xQueueGenericSend( QueueHandle_t xQueue,
 
             return errQUEUE_FULL;
         }
-    } /*lint -restore */
+    }
 }
 /*-----------------------------------------------------------*/
 
@@ -1521,9 +1517,6 @@ BaseType_t xQueueReceive( QueueHandle_t xQueue,
     }
     #endif
 
-    /*lint -save -e904  This function relaxes the coding standard somewhat to
-     * allow return statements within the function itself.  This is done in the
-     * interest of execution time efficiency. */
     for( ; ; )
     {
         taskENTER_CRITICAL();
@@ -1646,7 +1639,7 @@ BaseType_t xQueueReceive( QueueHandle_t xQueue,
                 mtCOVERAGE_TEST_MARKER();
             }
         }
-    } /*lint -restore */
+    }
 }
 /*-----------------------------------------------------------*/
 
@@ -1677,9 +1670,6 @@ BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue,
     }
     #endif
 
-    /*lint -save -e904 This function relaxes the coding standard somewhat to allow return
-     * statements within the function itself.  This is done in the interest
-     * of execution time efficiency. */
     for( ; ; )
     {
         taskENTER_CRITICAL();
@@ -1874,7 +1864,7 @@ BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue,
                 mtCOVERAGE_TEST_MARKER();
             }
         }
-    } /*lint -restore */
+    }
 }
 /*-----------------------------------------------------------*/
 
@@ -1903,9 +1893,6 @@ BaseType_t xQueuePeek( QueueHandle_t xQueue,
     }
     #endif
 
-    /*lint -save -e904  This function relaxes the coding standard somewhat to
-     * allow return statements within the function itself.  This is done in the
-     * interest of execution time efficiency. */
     for( ; ; )
     {
         taskENTER_CRITICAL();
@@ -2035,7 +2022,7 @@ BaseType_t xQueuePeek( QueueHandle_t xQueue,
                 mtCOVERAGE_TEST_MARKER();
             }
         }
-    } /*lint -restore */
+    }
 }
 /*-----------------------------------------------------------*/
 
@@ -2212,7 +2199,7 @@ UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue )
     traceRETURN_uxQueueMessagesWaiting( uxReturn );
 
     return uxReturn;
-} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
+}
 /*-----------------------------------------------------------*/
 
 UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue )
@@ -2233,7 +2220,7 @@ UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue )
     traceRETURN_uxQueueSpacesAvailable( uxReturn );
 
     return uxReturn;
-} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
+}
 /*-----------------------------------------------------------*/
 
 UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue )
@@ -2249,7 +2236,7 @@ UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue )
     traceRETURN_uxQueueMessagesWaitingFromISR( uxReturn );
 
     return uxReturn;
-} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
+}
 /*-----------------------------------------------------------*/
 
 void vQueueDelete( QueueHandle_t xQueue )
@@ -2418,10 +2405,10 @@ static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue,
     }
     else if( xPosition == queueSEND_TO_BACK )
     {
-        ( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
-        pxQueue->pcWriteTo += pxQueue->uxItemSize;                                                       /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
+        ( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize );
+        pxQueue->pcWriteTo += pxQueue->uxItemSize;
 
-        if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail )                                             /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
+        if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail )
         {
             pxQueue->pcWriteTo = pxQueue->pcHead;
         }
@@ -2432,10 +2419,10 @@ static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue,
     }
     else
     {
-        ( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes.  Assert checks null pointer only used when length is 0. */
+        ( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize );
         pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize;
 
-        if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
+        if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead )
         {
             pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize );
         }
@@ -2476,9 +2463,9 @@ static void prvCopyDataFromQueue( Queue_t * const pxQueue,
 {
     if( pxQueue->uxItemSize != ( UBaseType_t ) 0 )
     {
-        pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize;           /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
+        pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize;
 
-        if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */
+        if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail )
         {
             pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
         }
@@ -2487,7 +2474,7 @@ static void prvCopyDataFromQueue( Queue_t * const pxQueue,
             mtCOVERAGE_TEST_MARKER();
         }
 
-        ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports.  Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
+        ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize );
     }
 }
 /*-----------------------------------------------------------*/
@@ -2654,7 +2641,7 @@ BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue )
     traceRETURN_xQueueIsQueueEmptyFromISR( xReturn );
 
     return xReturn;
-} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
+}
 /*-----------------------------------------------------------*/
 
 static BaseType_t prvIsQueueFull( const Queue_t * pxQueue )
@@ -2699,7 +2686,7 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )
     traceRETURN_xQueueIsQueueFullFromISR( xReturn );
 
     return xReturn;
-} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
+}
 /*-----------------------------------------------------------*/
 
 #if ( configUSE_CO_ROUTINES == 1 )
@@ -3008,7 +2995,7 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )
 #if ( configQUEUE_REGISTRY_SIZE > 0 )
 
     void vQueueAddToRegistry( QueueHandle_t xQueue,
-                              const char * pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+                              const char * pcQueueName )
     {
         UBaseType_t ux;
         QueueRegistryItem_t * pxEntryToWrite = NULL;
@@ -3058,10 +3045,10 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )
 
 #if ( configQUEUE_REGISTRY_SIZE > 0 )
 
-    const char * pcQueueGetName( QueueHandle_t xQueue ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+    const char * pcQueueGetName( QueueHandle_t xQueue )
     {
         UBaseType_t ux;
-        const char * pcReturn = NULL; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+        const char * pcReturn = NULL;
 
         traceENTER_pcQueueGetName( xQueue );
 
@@ -3086,7 +3073,7 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )
         traceRETURN_pcQueueGetName( pcReturn );
 
         return pcReturn;
-    } /*lint !e818 xQueue cannot be a pointer to const because it is a typedef. */
+    }
 
 #endif /* configQUEUE_REGISTRY_SIZE */
 /*-----------------------------------------------------------*/
@@ -3123,7 +3110,7 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )
         }
 
         traceRETURN_vQueueUnregisterQueue();
-    } /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
+    }
 
 #endif /* configQUEUE_REGISTRY_SIZE */
 /*-----------------------------------------------------------*/
@@ -3264,7 +3251,7 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )
         traceRETURN_xQueueRemoveFromSet( xReturn );
 
         return xReturn;
-    } /*lint !e818 xQueueSet could not be declared as pointing to const as it is a typedef. */
+    }
 
 #endif /* configUSE_QUEUE_SETS */
 /*-----------------------------------------------------------*/
@@ -3278,7 +3265,7 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )
 
         traceENTER_xQueueSelectFromSet( xQueueSet, xTicksToWait );
 
-        ( void ) xQueueReceive( ( QueueHandle_t ) xQueueSet, &xReturn, xTicksToWait ); /*lint !e961 Casting from one typedef to another is not redundant. */
+        ( void ) xQueueReceive( ( QueueHandle_t ) xQueueSet, &xReturn, xTicksToWait );
 
         traceRETURN_xQueueSelectFromSet( xReturn );
 
@@ -3296,7 +3283,7 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )
 
         traceENTER_xQueueSelectFromSetFromISR( xQueueSet );
 
-        ( void ) xQueueReceiveFromISR( ( QueueHandle_t ) xQueueSet, &xReturn, NULL ); /*lint !e961 Casting from one typedef to another is not redundant. */
+        ( void ) xQueueReceiveFromISR( ( QueueHandle_t ) xQueueSet, &xReturn, NULL );
 
         traceRETURN_xQueueSelectFromSetFromISR( xReturn );
 
diff --git a/stream_buffer.c b/stream_buffer.c
index 9899e30ee..3ea7baa4b 100644
--- a/stream_buffer.c
+++ b/stream_buffer.c
@@ -47,29 +47,30 @@
     #error INCLUDE_xTaskGetCurrentTaskHandle must be set to 1 to build stream_buffer.c
 #endif
 
-/* Lint e961, e9021 and e750 are suppressed as a MISRA exception justified
- * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+/* The MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
  * for the header files above, but not in this file, in order to generate the
  * correct privileged Vs unprivileged linkage and placement. */
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
 
 /* If the user has not provided application specific Rx notification macros,
  * or #defined the notification macros away, then provide default implementations
  * that uses task notifications. */
-/*lint -save -e9026 Function like macros allowed and needed here so they can be overridden. */
 #ifndef sbRECEIVE_COMPLETED
-    #define sbRECEIVE_COMPLETED( pxStreamBuffer )                         \
-    vTaskSuspendAll();                                                    \
-    {                                                                     \
-        if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )              \
-        {                                                                 \
-            ( void ) xTaskNotify( ( pxStreamBuffer )->xTaskWaitingToSend, \
-                                  ( uint32_t ) 0,                         \
-                                  eNoAction );                            \
-            ( pxStreamBuffer )->xTaskWaitingToSend = NULL;                \
-        }                                                                 \
-    }                                                                     \
-    ( void ) xTaskResumeAll()
+    #define sbRECEIVE_COMPLETED( pxStreamBuffer )                             \
+    do                                                                        \
+    {                                                                         \
+        vTaskSuspendAll();                                                    \
+        {                                                                     \
+            if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )              \
+            {                                                                 \
+                ( void ) xTaskNotify( ( pxStreamBuffer )->xTaskWaitingToSend, \
+                                      ( uint32_t ) 0,                         \
+                                      eNoAction );                            \
+                ( pxStreamBuffer )->xTaskWaitingToSend = NULL;                \
+            }                                                                 \
+        }                                                                     \
+        ( void ) xTaskResumeAll();                                            \
+    } while( 0 )
 #endif /* sbRECEIVE_COMPLETED */
 
 /* If user has provided a per-instance receive complete callback, then
@@ -207,8 +208,6 @@
     sbSEND_COMPLETE_FROM_ISR( ( pxStreamBuffer ), ( pxHigherPriorityTaskWoken ) )
 #endif /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */
 
-/*lint -restore (9026) */
-
 /* The number of bytes used to hold the length of a message in the buffer. */
 #define sbBYTES_TO_STORE_MESSAGE_LENGTH    ( sizeof( configMESSAGE_BUFFER_LENGTH_TYPE ) )
 
@@ -219,7 +218,7 @@
 /*-----------------------------------------------------------*/
 
 /* Structure that hold state information on the buffer. */
-typedef struct StreamBufferDef_t                 /*lint !e9058 Style convention uses tag. */
+typedef struct StreamBufferDef_t
 {
     volatile size_t xTail;                       /* Index to the next item to read within the buffer. */
     volatile size_t xHead;                       /* Index to the next item to write within the buffer. */
@@ -459,7 +458,7 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
              * message buffer structure. */
             volatile size_t xSize = sizeof( StaticStreamBuffer_t );
             configASSERT( xSize == sizeof( StreamBuffer_t ) );
-        } /*lint !e529 xSize is referenced is configASSERT() is defined. */
+        }
         #endif /* configASSERT_DEFINED */
 
         if( ( pucStreamBufferStorageArea != NULL ) && ( pxStaticStreamBuffer != NULL ) )
@@ -547,7 +546,7 @@ void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer )
         {
             /* Both the structure and the buffer were allocated using a single call
             * to pvPortMalloc(), hence only one call to vPortFree() is required. */
-            vPortFree( ( void * ) pxStreamBuffer ); /*lint !e9087 Standard free() semantics require void *, plus pxStreamBuffer was allocated by pvPortMalloc(). */
+            vPortFree( ( void * ) pxStreamBuffer );
         }
         #else
         {
@@ -1379,7 +1378,7 @@ static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer,
 
     /* Write as many bytes as can be written in the first write. */
     configASSERT( ( xHead + xFirstLength ) <= pxStreamBuffer->xLength );
-    ( void ) memcpy( ( void * ) ( &( pxStreamBuffer->pucBuffer[ xHead ] ) ), ( const void * ) pucData, xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+    ( void ) memcpy( ( void * ) ( &( pxStreamBuffer->pucBuffer[ xHead ] ) ), ( const void * ) pucData, xFirstLength );
 
     /* If the number of bytes written was less than the number that could be
      * written in the first write... */
@@ -1387,7 +1386,7 @@ static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer,
     {
         /* ...then write the remaining bytes to the start of the buffer. */
         configASSERT( ( xCount - xFirstLength ) <= pxStreamBuffer->xLength );
-        ( void ) memcpy( ( void * ) pxStreamBuffer->pucBuffer, ( const void * ) &( pucData[ xFirstLength ] ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+        ( void ) memcpy( ( void * ) pxStreamBuffer->pucBuffer, ( const void * ) &( pucData[ xFirstLength ] ), xCount - xFirstLength );
     }
     else
     {
@@ -1427,14 +1426,14 @@ static size_t prvReadBytesFromBuffer( StreamBuffer_t * pxStreamBuffer,
      * read.  Asserts check bounds of read and write. */
     configASSERT( xFirstLength <= xCount );
     configASSERT( ( xTail + xFirstLength ) <= pxStreamBuffer->xLength );
-    ( void ) memcpy( ( void * ) pucData, ( const void * ) &( pxStreamBuffer->pucBuffer[ xTail ] ), xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+    ( void ) memcpy( ( void * ) pucData, ( const void * ) &( pxStreamBuffer->pucBuffer[ xTail ] ), xFirstLength );
 
     /* If the total number of wanted bytes is greater than the number
      * that could be read in the first read... */
     if( xCount > xFirstLength )
     {
         /* ...then read the remaining bytes from the start of the buffer. */
-        ( void ) memcpy( ( void * ) &( pucData[ xFirstLength ] ), ( void * ) ( pxStreamBuffer->pucBuffer ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+        ( void ) memcpy( ( void * ) &( pucData[ xFirstLength ] ), ( void * ) ( pxStreamBuffer->pucBuffer ), xCount - xFirstLength );
     }
     else
     {
@@ -1495,7 +1494,7 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
     }
     #endif
 
-    ( void ) memset( ( void * ) pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) ); /*lint !e9087 memset() requires void *. */
+    ( void ) memset( ( void * ) pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) );
     pxStreamBuffer->pucBuffer = pucBuffer;
     pxStreamBuffer->xLength = xBufferSizeBytes;
     pxStreamBuffer->xTriggerLevelBytes = xTriggerLevelBytes;
diff --git a/tasks.c b/tasks.c
index 1bb8a05a9..a19ab9195 100644
--- a/tasks.c
+++ b/tasks.c
@@ -41,11 +41,10 @@
 #include "timers.h"
 #include "stack_macros.h"
 
-/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified
- * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+/* The MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
  * for the header files above, but not in this file, in order to generate the
  * correct privileged Vs unprivileged linkage and placement. */
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
 
 /* Set configUSE_STATS_FORMATTING_FUNCTIONS to 2 to include the stats formatting
  * functions but without including stdio.h here. */
@@ -369,7 +368,7 @@ typedef struct tskTaskControlBlock       /* The old naming convention is used to
         volatile BaseType_t xTaskRunState;      /**< Used to identify the core the task is running on, if the task is running. Otherwise, identifies the task's state - not running or yielding. */
         UBaseType_t uxTaskAttributes;           /**< Task's attributes - currently used to identify the idle tasks. */
     #endif
-    char pcTaskName[ configMAX_TASK_NAME_LEN ]; /**< Descriptive name given to the task when created.  Facilitates debugging only. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+    char pcTaskName[ configMAX_TASK_NAME_LEN ]; /**< Descriptive name given to the task when created.  Facilitates debugging only. */
 
     #if ( configUSE_TASK_PREEMPTION_DISABLE == 1 )
         BaseType_t xPreemptionDisable; /**< Used to prevent the task from being preempted. */
@@ -416,8 +415,8 @@ typedef struct tskTaskControlBlock       /* The old naming convention is used to
 
     /* See the comments in FreeRTOS.h with the definition of
      * tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE. */
-    #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
-        uint8_t ucStaticallyAllocated;                     /**< Set to pdTRUE if the task is a statically allocated to ensure no attempt is made to free the memory. */
+    #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
+        uint8_t ucStaticallyAllocated; /**< Set to pdTRUE if the task is a statically allocated to ensure no attempt is made to free the memory. */
     #endif
 
     #if ( INCLUDE_xTaskAbortDelay == 1 )
@@ -433,8 +432,6 @@ typedef struct tskTaskControlBlock       /* The old naming convention is used to
  * below to enable the use of older kernel aware debuggers. */
 typedef tskTCB TCB_t;
 
-/*lint -save -e956 A manual analysis and inspection has been used to determine
- * which static variables must be declared volatile. */
 #if ( configNUMBER_OF_CORES == 1 )
     /* MISRA Ref 8.4.1 [Declaration shall be visible] */
     /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-84 */
@@ -518,8 +515,6 @@ PRIVILEGED_DATA static volatile configRUN_TIME_COUNTER_TYPE ulTotalRunTime[ conf
 
 #endif
 
-/*lint -restore */
-
 /*-----------------------------------------------------------*/
 
 /* File private functions. --------------------------------*/
@@ -695,7 +690,7 @@ static void prvResetNextTaskUnblockTime( void ) PRIVILEGED_FUNCTION;
  * dynamically to fill in the structure's members.
  */
 static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
-                                  const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+                                  const char * const pcName,
                                   const uint32_t ulStackDepth,
                                   void * const pvParameters,
                                   UBaseType_t uxPriority,
@@ -715,7 +710,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
  */
 #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
     static TCB_t * prvCreateStaticTask( TaskFunction_t pxTaskCode,
-                                        const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+                                        const char * const pcName,
                                         const uint32_t ulStackDepth,
                                         void * const pvParameters,
                                         UBaseType_t uxPriority,
@@ -749,7 +744,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
  */
 #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
     static TCB_t * prvCreateTask( TaskFunction_t pxTaskCode,
-                                  const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+                                  const char * const pcName,
                                   const configSTACK_DEPTH_TYPE usStackDepth,
                                   void * const pvParameters,
                                   UBaseType_t uxPriority,
@@ -1249,7 +1244,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
 #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
 
     static TCB_t * prvCreateStaticTask( TaskFunction_t pxTaskCode,
-                                        const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+                                        const char * const pcName,
                                         const uint32_t ulStackDepth,
                                         void * const pvParameters,
                                         UBaseType_t uxPriority,
@@ -1269,7 +1264,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
              * structure. */
             volatile size_t xSize = sizeof( StaticTask_t );
             configASSERT( xSize == sizeof( TCB_t ) );
-            ( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */
+            ( void ) xSize; /* Prevent unused variable warning when configASSERT() is not used. */
         }
         #endif /* configASSERT_DEFINED */
 
@@ -1284,7 +1279,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
             ( void ) memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) );
             pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer;
 
-            #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
+            #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
             {
                 /* Tasks can be created statically or dynamically, so note this
                  * task was created statically in case the task is later deleted. */
@@ -1304,7 +1299,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
 /*-----------------------------------------------------------*/
 
     TaskHandle_t xTaskCreateStatic( TaskFunction_t pxTaskCode,
-                                    const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+                                    const char * const pcName,
                                     const uint32_t ulStackDepth,
                                     void * const pvParameters,
                                     UBaseType_t uxPriority,
@@ -1342,7 +1337,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
 
     #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
         TaskHandle_t xTaskCreateStaticAffinitySet( TaskFunction_t pxTaskCode,
-                                                   const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+                                                   const char * const pcName,
                                                    const uint32_t ulStackDepth,
                                                    void * const pvParameters,
                                                    UBaseType_t uxPriority,
@@ -1615,7 +1610,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
 
 #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
     static TCB_t * prvCreateTask( TaskFunction_t pxTaskCode,
-                                  const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+                                  const char * const pcName,
                                   const configSTACK_DEPTH_TYPE usStackDepth,
                                   void * const pvParameters,
                                   UBaseType_t uxPriority,
@@ -1697,7 +1692,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
 
         if( pxNewTCB != NULL )
         {
-            #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */
+            #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
             {
                 /* Tasks can be created statically or dynamically, so note this
                  * task was created dynamically in case it is later deleted. */
@@ -1713,7 +1708,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
 /*-----------------------------------------------------------*/
 
     BaseType_t xTaskCreate( TaskFunction_t pxTaskCode,
-                            const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+                            const char * const pcName,
                             const configSTACK_DEPTH_TYPE usStackDepth,
                             void * const pvParameters,
                             UBaseType_t uxPriority,
@@ -1751,7 +1746,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
 
     #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
         BaseType_t xTaskCreateAffinitySet( TaskFunction_t pxTaskCode,
-                                           const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+                                           const char * const pcName,
                                            const configSTACK_DEPTH_TYPE usStackDepth,
                                            void * const pvParameters,
                                            UBaseType_t uxPriority,
@@ -1788,7 +1783,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
 /*-----------------------------------------------------------*/
 
 static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
-                                  const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+                                  const char * const pcName,
                                   const uint32_t ulStackDepth,
                                   void * const pvParameters,
                                   UBaseType_t uxPriority,
@@ -1829,7 +1824,7 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
     #if ( portSTACK_GROWTH < 0 )
     {
         pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] );
-        pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception.  Avoiding casts between pointers and integers is not practical.  Size differences accounted for using portPOINTER_SIZE_TYPE type.  Checked by assert(). */
+        pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) );
 
         /* Check the alignment of the calculated top of stack is correct. */
         configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
@@ -1845,7 +1840,7 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
     #else /* portSTACK_GROWTH */
     {
         pxTopOfStack = pxNewTCB->pxStack;
-        pxTopOfStack = ( StackType_t * ) ( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) + portBYTE_ALIGNMENT_MASK ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception.  Avoiding casts between pointers and integers is not practical.  Size differences accounted for using portPOINTER_SIZE_TYPE type.  Checked by assert(). */
+        pxTopOfStack = ( StackType_t * ) ( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) + portBYTE_ALIGNMENT_MASK ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) );
 
         /* Check the alignment of the calculated top of stack is correct. */
         configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
@@ -1912,7 +1907,7 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
     listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB );
 
     /* Event lists are always in priority order. */
-    listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+    listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority );
     listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB );
 
     #if ( portUSING_MPU_WRAPPERS == 1 )
@@ -2588,7 +2583,7 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
                 }
             #endif
 
-            else /*lint !e525 Negative indentation is intended to make use of pre-processor clearer. */
+            else
             {
                 #if ( configNUMBER_OF_CORES == 1 )
                 {
@@ -2617,7 +2612,7 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
         traceRETURN_eTaskGetState( eReturn );
 
         return eReturn;
-    } /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */
+    }
 
 #endif /* INCLUDE_eTaskGetState */
 /*-----------------------------------------------------------*/
@@ -2897,7 +2892,7 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
                  * being used for anything else. */
                 if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == ( ( TickType_t ) 0UL ) )
                 {
-                    listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxNewPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+                    listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxNewPriority ) );
                 }
                 else
                 {
@@ -3216,7 +3211,7 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
                     /* The scheduler is not running, but the task that was pointed
                      * to by pxCurrentTCB has just been suspended and pxCurrentTCB
                      * must be adjusted to point to a different task. */
-                    if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == uxCurrentNumberOfTasks ) /*lint !e931 Right has no side effect, just volatile. */
+                    if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == uxCurrentNumberOfTasks )
                     {
                         /* No other tasks are ready, so set pxCurrentTCB back to
                          * NULL so when the next task is created pxCurrentTCB will
@@ -3309,7 +3304,7 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
             {
                 /* Is it in the suspended list because it is in the Suspended
                  * state, or because it is blocked with no timeout? */
-                if( listIS_CONTAINED_WITHIN( NULL, &( pxTCB->xEventListItem ) ) != pdFALSE ) /*lint !e961.  The cast is only redundant when NULL is used. */
+                if( listIS_CONTAINED_WITHIN( NULL, &( pxTCB->xEventListItem ) ) != pdFALSE )
                 {
                     #if ( configUSE_TASK_NOTIFICATIONS == 1 )
                     {
@@ -3353,7 +3348,7 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
         }
 
         return xReturn;
-    } /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */
+    }
 
 #endif /* INCLUDE_vTaskSuspend */
 /*-----------------------------------------------------------*/
@@ -3617,10 +3612,10 @@ static BaseType_t prvCreateIdleTasks( void )
             xIdleTaskHandles[ xCoreID ] = xTaskCreateStatic( pxIdleTaskFunction,
                                                              cIdleName,
                                                              ulIdleTaskStackSize,
-                                                             ( void * ) NULL,       /*lint !e961.  The cast is not redundant for all compilers. */
-                                                             portPRIVILEGE_BIT,     /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
+                                                             ( void * ) NULL,
+                                                             portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
                                                              pxIdleTaskStackBuffer,
-                                                             pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
+                                                             pxIdleTaskTCBBuffer );
 
             if( xIdleTaskHandles[ xCoreID ] != NULL )
             {
@@ -3638,8 +3633,8 @@ static BaseType_t prvCreateIdleTasks( void )
                                    cIdleName,
                                    configMINIMAL_STACK_SIZE,
                                    ( void * ) NULL,
-                                   portPRIVILEGE_BIT,              /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
-                                   &xIdleTaskHandles[ xCoreID ] ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
+                                   portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
+                                   &xIdleTaskHandles[ xCoreID ] );
         }
         #endif /* configSUPPORT_STATIC_ALLOCATION */
 
@@ -4142,7 +4137,7 @@ UBaseType_t uxTaskGetNumberOfTasks( void )
 }
 /*-----------------------------------------------------------*/
 
-char * pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+char * pcTaskGetName( TaskHandle_t xTaskToQuery )
 {
     TCB_t * pxTCB;
 
@@ -4307,7 +4302,7 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char
 
 #if ( INCLUDE_xTaskGetHandle == 1 )
 
-    TaskHandle_t xTaskGetHandle( const char * pcNameToQuery ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+    TaskHandle_t xTaskGetHandle( const char * pcNameToQuery )
     {
         UBaseType_t uxQueue = configMAX_PRIORITIES;
         TCB_t * pxTCB;
@@ -4330,7 +4325,7 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char
                     /* Found the handle. */
                     break;
                 }
-            } while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+            } while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY );
 
             /* Search the delayed lists. */
             if( pxTCB == NULL )
@@ -4448,7 +4443,7 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char
                 {
                     uxQueue--;
                     uxTask = ( UBaseType_t ) ( uxTask + prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &( pxReadyTasksLists[ uxQueue ] ), eReady ) );
-                } while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+                } while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY );
 
                 /* Fill in an TaskStatus_t structure with information on each
                  * task in the Blocked state. */
@@ -4745,7 +4740,7 @@ BaseType_t xTaskIncrementTick( void )
          * delayed lists if it wraps to 0. */
         xTickCount = xConstTickCount;
 
-        if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */
+        if( xConstTickCount == ( TickType_t ) 0U )
         {
             taskSWITCH_DELAYED_LISTS();
         }
@@ -4769,7 +4764,7 @@ BaseType_t xTaskIncrementTick( void )
                      * unlikely that the
                      * if( xTickCount >= xNextTaskUnblockTime ) test will pass
                      * next time through. */
-                    xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+                    xNextTaskUnblockTime = portMAX_DELAY;
                     break;
                 }
                 else
@@ -4792,7 +4787,7 @@ BaseType_t xTaskIncrementTick( void )
                          * state -  so record the item value in
                          * xNextTaskUnblockTime. */
                         xNextTaskUnblockTime = xItemValue;
-                        break; /*lint !e9011 Code structure here is deemed easier to understand with multiple breaks. */
+                        break;
                     }
                     else
                     {
@@ -5603,7 +5598,7 @@ BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
             else
         #endif
 
-        if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */
+        if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) )
         {
             /* The tick count is greater than the time at which
              * vTaskSetTimeout() was called, but has also overflowed since
@@ -5613,7 +5608,7 @@ BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
             xReturn = pdTRUE;
             *pxTicksToWait = ( TickType_t ) 0;
         }
-        else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */
+        else if( xElapsedTime < *pxTicksToWait )
         {
             /* Not a genuine timeout. Adjust parameters for time remaining. */
             *pxTicksToWait -= xElapsedTime;
@@ -6347,7 +6342,7 @@ static void prvCheckTasksWaitingTermination( void )
             ulCount++;
         }
 
-        ulCount /= ( uint32_t ) sizeof( StackType_t ); /*lint !e961 Casting is not redundant on smaller architectures. */
+        ulCount /= ( uint32_t ) sizeof( StackType_t );
 
         return ( configSTACK_DEPTH_TYPE ) ulCount;
     }
@@ -6454,7 +6449,7 @@ static void prvCheckTasksWaitingTermination( void )
             vPortFreeStack( pxTCB->pxStack );
             vPortFree( pxTCB );
         }
-        #elif ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
+        #elif ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
         {
             /* The task could have been allocated statically or dynamically, so
              * check what was statically allocated before trying to free the
@@ -6627,7 +6622,7 @@ static void prvResetNextTaskUnblockTime( void )
                  * not being used for anything else. */
                 if( ( listGET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == ( ( TickType_t ) 0UL ) )
                 {
-                    listSET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+                    listSET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority );
                 }
                 else
                 {
@@ -6755,7 +6750,7 @@ static void prvResetNextTaskUnblockTime( void )
                     /* Reset the event list item value.  It cannot be in use for
                      * any other purpose if this task is running, and it must be
                      * running to give back the mutex. */
-                    listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+                    listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority );
                     prvAddTaskToReadyList( pxTCB );
                     #if ( configNUMBER_OF_CORES > 1 )
                     {
@@ -6856,7 +6851,7 @@ static void prvResetNextTaskUnblockTime( void )
                      * being used for anything else. */
                     if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == ( ( TickType_t ) 0UL ) )
                     {
-                        listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriorityToUse ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+                        listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriorityToUse );
                     }
                     else
                     {
@@ -7374,7 +7369,7 @@ static void prvResetNextTaskUnblockTime( void )
                         uxCharsWrittenBySnprintf = prvSnprintfReturnValueToCharsWritten( iSnprintfReturnValue, uxBufferLength - uxConsumedBufferLength );
 
                         uxConsumedBufferLength += uxCharsWrittenBySnprintf;
-                        pcWriteBuffer += uxCharsWrittenBySnprintf; /*lint !e9016 Pointer arithmetic ok on char pointers especially as in this case where it best denotes the intent of the code. */
+                        pcWriteBuffer += uxCharsWrittenBySnprintf;
                     }
                     else
                     {
@@ -7557,7 +7552,7 @@ static void prvResetNextTaskUnblockTime( void )
 
                             uxCharsWrittenBySnprintf = prvSnprintfReturnValueToCharsWritten( iSnprintfReturnValue, uxBufferLength - uxConsumedBufferLength );
                             uxConsumedBufferLength += uxCharsWrittenBySnprintf;
-                            pcWriteBuffer += uxCharsWrittenBySnprintf; /*lint !e9016 Pointer arithmetic ok on char pointers especially as in this case where it best denotes the intent of the code. */
+                            pcWriteBuffer += uxCharsWrittenBySnprintf;
                         }
                         else
                         {
@@ -7605,7 +7600,7 @@ TickType_t uxTaskResetEventItemValue( void )
 
     /* Reset the event list item to its normal value - so it can be used with
      * queues and semaphores. */
-    listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+    listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ) );
 
     traceRETURN_uxTaskResetEventItemValue( uxReturn );
 
@@ -8491,7 +8486,7 @@ static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait,
     {
         /* The current task must be in a ready list, so there is no need to
          * check, and the port reset macro can be called directly. */
-        portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority ); /*lint !e931 pxCurrentTCB cannot change as it is the calling task.  pxCurrentTCB->uxPriority and uxTopReadyPriority cannot change as called with scheduler suspended or in a critical section. */
+        portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority );
     }
     else
     {
diff --git a/timers.c b/timers.c
index 72636cf46..df7f442c3 100644
--- a/timers.c
+++ b/timers.c
@@ -43,11 +43,10 @@
     #error configUSE_TIMERS must be set to 1 to make the xTimerPendFunctionCall() function available.
 #endif
 
-/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified
- * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+/* The MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
  * for the header files above, but not in this file, in order to generate the
  * correct privileged Vs unprivileged linkage and placement. */
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e9021 !e961 !e750. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
 
 
 /* This entire source file will be skipped if the application is not configured
@@ -83,7 +82,7 @@
 /* The definition of the timers themselves. */
     typedef struct tmrTimerControl                                               /* The old naming convention is used to prevent breaking kernel aware debuggers. */
     {
-        const char * pcTimerName;                                                /**< Text name.  This is not used by the kernel, it is included simply to make debugging easier. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+        const char * pcTimerName;                                                /**< Text name.  This is not used by the kernel, it is included simply to make debugging easier. */
         ListItem_t xTimerListItem;                                               /**< Standard linked list item as used by all kernel features for event management. */
         TickType_t xTimerPeriodInTicks;                                          /**< How quickly and often the timer expires. */
         void * pvTimerID;                                                        /**< An ID to identify the timer.  This allows the timer to be identified when the same callback is used for multiple timers. */
@@ -135,9 +134,6 @@
         } u;
     } DaemonTaskMessage_t;
 
-/*lint -save -e956 A manual analysis and inspection has been used to determine
- * which static variables must be declared volatile. */
-
 /* The list in which active timers are stored.  Timers are referenced in expire
  * time order, with the nearest expiry time at the front of the list.  Only the
  * timer service task is allowed to access these lists.
@@ -153,8 +149,6 @@
     PRIVILEGED_DATA static QueueHandle_t xTimerQueue = NULL;
     PRIVILEGED_DATA static TaskHandle_t xTimerTaskHandle = NULL;
 
-/*lint -restore */
-
 /*-----------------------------------------------------------*/
 
 /*
@@ -232,7 +226,7 @@
  * Called after a Timer_t structure has been allocated either statically or
  * dynamically to fill in the structure's members.
  */
-    static void prvInitialiseNewTimer( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+    static void prvInitialiseNewTimer( const char * const pcTimerName,
                                        const TickType_t xTimerPeriodInTicks,
                                        const BaseType_t xAutoReload,
                                        void * const pvTimerID,
@@ -339,7 +333,7 @@
 
     #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
 
-        TimerHandle_t xTimerCreate( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+        TimerHandle_t xTimerCreate( const char * const pcTimerName,
                                     const TickType_t xTimerPeriodInTicks,
                                     const BaseType_t xAutoReload,
                                     void * const pvTimerID,
@@ -373,7 +367,7 @@
 
     #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
 
-        TimerHandle_t xTimerCreateStatic( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+        TimerHandle_t xTimerCreateStatic( const char * const pcTimerName,
                                           const TickType_t xTimerPeriodInTicks,
                                           const BaseType_t xAutoReload,
                                           void * const pvTimerID,
@@ -391,7 +385,7 @@
                  * structure. */
                 volatile size_t xSize = sizeof( StaticTimer_t );
                 configASSERT( xSize == sizeof( Timer_t ) );
-                ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
+                ( void ) xSize; /* Prevent unused variable warning when configASSERT() is not defined. */
             }
             #endif /* configASSERT_DEFINED */
 
@@ -420,7 +414,7 @@
     #endif /* configSUPPORT_STATIC_ALLOCATION */
 /*-----------------------------------------------------------*/
 
-    static void prvInitialiseNewTimer( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+    static void prvInitialiseNewTimer( const char * const pcTimerName,
                                        const TickType_t xTimerPeriodInTicks,
                                        const BaseType_t xAutoReload,
                                        void * const pvTimerID,
@@ -688,7 +682,7 @@
     #endif /* configSUPPORT_STATIC_ALLOCATION */
 /*-----------------------------------------------------------*/
 
-    const char * pcTimerGetName( TimerHandle_t xTimer ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+    const char * pcTimerGetName( TimerHandle_t xTimer )
     {
         Timer_t * pxTimer = xTimer;
 
@@ -877,7 +871,7 @@
     static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched )
     {
         TickType_t xTimeNow;
-        PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */
+        PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U;
 
         xTimeNow = xTaskGetTickCount();
 
@@ -911,7 +905,7 @@
         {
             /* Has the expiry time elapsed between the command to start/reset a
              * timer was issued, and the time the command was processed? */
-            if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+            if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks )
             {
                 /* The time between a command being issued and the command being
                  * processed actually exceeds the timers period.  */
@@ -980,7 +974,7 @@
                  * software timer. */
                 pxTimer = xMessage.u.xTimerParameters.pxTimer;
 
-                if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE ) /*lint !e961. The cast is only redundant when NULL is passed into the macro. */
+                if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE )
                 {
                     /* The timer is in a list, remove it. */
                     ( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
@@ -1132,8 +1126,8 @@
                 {
                     /* The timer queue is allocated statically in case
                      * configSUPPORT_DYNAMIC_ALLOCATION is 0. */
-                    PRIVILEGED_DATA static StaticQueue_t xStaticTimerQueue;                                                                          /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
-                    PRIVILEGED_DATA static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ]; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
+                    PRIVILEGED_DATA static StaticQueue_t xStaticTimerQueue;
+                    PRIVILEGED_DATA static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ];
 
                     xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue );
                 }
@@ -1191,7 +1185,7 @@
         traceRETURN_xTimerIsTimerActive( xReturn );
 
         return xReturn;
-    } /*lint !e818 Can't be pointer to const due to the typedef. */
+    }
 /*-----------------------------------------------------------*/
 
     void * pvTimerGetTimerID( const TimerHandle_t xTimer )

From 553caa18ced4906cf5060823ada7a10e73c7b535 Mon Sep 17 00:00:00 2001
From: RichardBarry <3073890+RichardBarry@users.noreply.github.com>
Date: Sat, 9 Dec 2023 01:19:39 -0800
Subject: [PATCH 157/424] Update the memory alignment within the Cortex-A9 port
 asm code (#426)

Update alignment in ARM_CA9 port.
---
 portable/GCC/ARM_CA9/portASM.S | 19 ++++++++++++++++---
 1 file changed, 16 insertions(+), 3 deletions(-)

diff --git a/portable/GCC/ARM_CA9/portASM.S b/portable/GCC/ARM_CA9/portASM.S
index 150cfabad..55baabbd3 100644
--- a/portable/GCC/ARM_CA9/portASM.S
+++ b/portable/GCC/ARM_CA9/portASM.S
@@ -75,9 +75,9 @@
 
     /* Save the floating point context, if any. */
     FMRXNE  R1,  FPSCR
+    PUSHNE  {R1}
     VPUSHNE {D0-D15}
     VPUSHNE {D16-D31}
-    PUSHNE  {R1}
 
     /* Save ulPortTaskHasFPUContext itself. */
     PUSH    {R3}
@@ -106,9 +106,9 @@
     CMP     R1, #0
 
     /* Restore the floating point context, if any. */
-    POPNE   {R0}
     VPOPNE  {D16-D31}
     VPOPNE  {D0-D15}
+    POPNE   {R0}
     VMSRNE  FPSCR, R0
 
     /* Restore the critical section nesting depth. */
@@ -145,8 +145,15 @@
 FreeRTOS_SWI_Handler:
     /* Save the context of the current task and select a new task to run. */
     portSAVE_CONTEXT
+
+    /* Ensure bit 2 of the stack pointer is clear. */
+    MOV     r2, sp
+    AND     r2, r2, #4
+    SUB     sp, sp, r2
+
     LDR R0, vTaskSwitchContextConst
     BLX R0
+
     portRESTORE_CONTEXT
 
 
@@ -256,7 +263,13 @@ switch_before_exit:
     /* Call the function that selects the new task to execute.
     vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD
     instructions, or 8 byte aligned stack allocated data.  LR does not need
-    saving as a new LR will be loaded by portRESTORE_CONTEXT anyway. */
+    saving as a new LR will be loaded by portRESTORE_CONTEXT anyway.
+    Ensure bit 2 of the stack pointer is clear.  r2 holds the bit 2 value for
+    future use. */
+    MOV     r2, sp
+    AND     r2, r2, #4
+    SUB     sp, sp, r2
+
     LDR     R0, vTaskSwitchContextConst
     BLX     R0
 

From 30e6b8a5eadbf61b7118c3d0ad8d205c16dfbb1c Mon Sep 17 00:00:00 2001
From: Jeff Tenney <jeff.tenney@gmail.com>
Date: Sun, 10 Dec 2023 21:57:47 -0700
Subject: [PATCH 158/424] Detect more startup config errors on Cortex M (#832)

Verify that the application has correctly installed PendSV
and SVCall handlers. The application can choose to
disable these checks by setting configCHECK_HANDLER_INSTALLATION
to 0 in their FreeRTOSConfig.h.
---
 include/FreeRTOS.h                           | 11 +++
 portable/ARMv8M/non_secure/port.c            | 71 +++++++++++++++-----
 portable/GCC/ARM_CM0/port.c                  | 58 +++++++++++++---
 portable/GCC/ARM_CM23/non_secure/port.c      | 71 +++++++++++++++-----
 portable/GCC/ARM_CM23_NTZ/non_secure/port.c  | 71 +++++++++++++++-----
 portable/GCC/ARM_CM3/port.c                  | 47 ++++++++++++-
 portable/GCC/ARM_CM33/non_secure/port.c      | 71 +++++++++++++++-----
 portable/GCC/ARM_CM33_NTZ/non_secure/port.c  | 71 +++++++++++++++-----
 portable/GCC/ARM_CM35P/non_secure/port.c     | 71 +++++++++++++++-----
 portable/GCC/ARM_CM35P_NTZ/non_secure/port.c | 71 +++++++++++++++-----
 portable/GCC/ARM_CM3_MPU/port.c              | 51 ++++++++++++--
 portable/GCC/ARM_CM4F/port.c                 | 47 ++++++++++++-
 portable/GCC/ARM_CM4_MPU/port.c              | 50 ++++++++++++--
 portable/GCC/ARM_CM55/non_secure/port.c      | 71 +++++++++++++++-----
 portable/GCC/ARM_CM55_NTZ/non_secure/port.c  | 71 +++++++++++++++-----
 portable/GCC/ARM_CM7/r0p1/port.c             | 47 ++++++++++++-
 portable/GCC/ARM_CM85/non_secure/port.c      | 71 +++++++++++++++-----
 portable/GCC/ARM_CM85_NTZ/non_secure/port.c  | 71 +++++++++++++++-----
 portable/IAR/ARM_CM0/port.c                  | 46 +++++++++++++
 portable/IAR/ARM_CM0/portasm.s               |  8 +--
 portable/IAR/ARM_CM23/non_secure/port.c      | 71 +++++++++++++++-----
 portable/IAR/ARM_CM23_NTZ/non_secure/port.c  | 71 +++++++++++++++-----
 portable/IAR/ARM_CM3/port.c                  | 52 +++++++++++++-
 portable/IAR/ARM_CM33/non_secure/port.c      | 71 +++++++++++++++-----
 portable/IAR/ARM_CM33_NTZ/non_secure/port.c  | 71 +++++++++++++++-----
 portable/IAR/ARM_CM35P/non_secure/port.c     | 71 +++++++++++++++-----
 portable/IAR/ARM_CM35P_NTZ/non_secure/port.c | 71 +++++++++++++++-----
 portable/IAR/ARM_CM4F/port.c                 | 52 +++++++++++++-
 portable/IAR/ARM_CM4F_MPU/port.c             | 53 ++++++++++++++-
 portable/IAR/ARM_CM55/non_secure/port.c      | 71 +++++++++++++++-----
 portable/IAR/ARM_CM55_NTZ/non_secure/port.c  | 71 +++++++++++++++-----
 portable/IAR/ARM_CM7/r0p1/port.c             | 52 +++++++++++++-
 portable/IAR/ARM_CM85/non_secure/port.c      | 71 +++++++++++++++-----
 portable/IAR/ARM_CM85_NTZ/non_secure/port.c  | 71 +++++++++++++++-----
 portable/RVDS/ARM_CM4_MPU/port.c             | 50 ++++++++++++--
 35 files changed, 1765 insertions(+), 350 deletions(-)

diff --git a/include/FreeRTOS.h b/include/FreeRTOS.h
index 06c50adf3..b6caec77f 100644
--- a/include/FreeRTOS.h
+++ b/include/FreeRTOS.h
@@ -365,6 +365,17 @@
     #define configPRECONDITION_DEFINED    1
 #endif
 
+#ifndef configCHECK_HANDLER_INSTALLATION
+    #define configCHECK_HANDLER_INSTALLATION    1
+#else
+
+/* The application has explicitly defined configCHECK_HANDLER_INSTALLATION
+ * to 1. The checks requires configASSERT() to be defined. */
+    #if ( ( configCHECK_HANDLER_INSTALLATION == 1 ) && ( configASSERT_DEFINED == 0 ) )
+        #error You must define configASSERT() when configCHECK_HANDLER_INSTALLATION is 1.
+    #endif
+#endif
+
 #ifndef portMEMORY_BARRIER
     #define portMEMORY_BARRIER()
 #endif
diff --git a/portable/ARMv8M/non_secure/port.c b/portable/ARMv8M/non_secure/port.c
index 6a3877894..a5ed7004a 100644
--- a/portable/ARMv8M/non_secure/port.c
+++ b/portable/ARMv8M/non_secure/port.c
@@ -80,6 +80,12 @@
 #endif
 /*-----------------------------------------------------------*/
 
+/**
+ * @brief Prototype of all Interrupt Service Routines (ISRs).
+ */
+typedef void ( * portISR_t )( void );
+/*-----------------------------------------------------------*/
+
 /**
  * @brief Constants required to manipulate the NVIC.
  */
@@ -101,10 +107,18 @@
 /**
  * @brief Constants required to manipulate the SCB.
  */
-#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_VTOR_REG                      ( *( ( portISR_t ** ) 0xe000ed08 ) )
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
 #define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )
 /*-----------------------------------------------------------*/
 
+/**
+ * @brief Constants used to check the installation of the FreeRTOS interrupt handlers.
+ */
+#define portVECTOR_INDEX_SVC       ( 11 )
+#define portVECTOR_INDEX_PENDSV    ( 14 )
+/*-----------------------------------------------------------*/
+
 /**
  * @brief Constants required to check the validity of an interrupt priority.
  */
@@ -1598,22 +1612,52 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
+    /* An application can install FreeRTOS interrupt handlers in one of the
+     * folllowing ways:
+     * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
+     *    for SVCall and PendSV interrupts respectively.
+     * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+     *    interrupts and route program control from those handlers to
+     *    SVC_Handler and PendSV_Handler functions.
+     *
+     * Applications that use Indirect Routing must set
+     * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+     * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+     * is 1, should be preferred when possible. */
+    #if ( configCHECK_HANDLER_INSTALLATION == 1 )
+    {
+        const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+        /* Validate that the application has correctly installed the FreeRTOS
+         * handlers for SVCall and PendSV interrupts. We do not check the
+         * installation of the SysTick handler because the application may
+         * choose to drive the RTOS tick using a timer other than the SysTick
+         * timer by overriding the weak function vPortSetupTimerInterrupt().
+         *
+         * Assertion failures here indicate incorrect installation of the
+         * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+         * https://www.FreeRTOS.org/FAQHelp.html.
+         *
+         * Systems with a configurable address for the interrupt vector table
+         * can also encounter assertion failures or even system faults here if
+         * VTOR is not set correctly to point to the application's vector table. */
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler );
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler );
+    }
+    #endif /* configCHECK_HANDLER_INSTALLATION */
+
     #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
     {
-        volatile uint32_t ulOriginalPriority;
         volatile uint32_t ulImplementedPrioBits = 0;
         volatile uint8_t ucMaxPriorityValue;
 
         /* Determine the maximum priority from which ISR safe FreeRTOS API
-         * functions can be called.  ISR safe functions are those that end in
-         * "FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+         * functions can be called. ISR safe functions are those that end in
+         * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
          * ensure interrupt entry is as fast and simple as possible.
          *
-         * Save the interrupt priority value that is about to be clobbered. */
-        ulOriginalPriority = portNVIC_SHPR2_REG;
-
-        /* Determine the number of priority bits available.  First write to all
-         * possible bits. */
+         * First, determine the number of priority bits available. Write to all
+         * possible bits in the priority setting for SVCall. */
         portNVIC_SHPR2_REG = 0xFF000000;
 
         /* Read the value back to see how many bits stuck. */
@@ -1636,7 +1680,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         /* Calculate the maximum acceptable priority group value for the number
          * of bits read back. */
-
         while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
         {
             ulImplementedPrioBits++;
@@ -1674,16 +1717,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          * register. */
         ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
         ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
-        /* Restore the clobbered interrupt priority register to its original
-         * value. */
-        portNVIC_SHPR2_REG = ulOriginalPriority;
     }
     #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
-    /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+    /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
+     * the highest priority. */
     portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+    portNVIC_SHPR2_REG = 0;
 
     #if ( configENABLE_MPU == 1 )
     {
diff --git a/portable/GCC/ARM_CM0/port.c b/portable/GCC/ARM_CM0/port.c
index 93e6d0489..53bc33a41 100644
--- a/portable/GCC/ARM_CM0/port.c
+++ b/portable/GCC/ARM_CM0/port.c
@@ -34,6 +34,9 @@
 #include "FreeRTOS.h"
 #include "task.h"
 
+/* Prototype of all Interrupt Service Routines (ISRs). */
+typedef void ( * portISR_t )( void );
+
 /* Constants required to manipulate the NVIC. */
 #define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )
 #define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )
@@ -51,6 +54,10 @@
 #define portNVIC_PENDSV_PRI                   ( portMIN_INTERRUPT_PRIORITY << 16UL )
 #define portNVIC_SYSTICK_PRI                  ( portMIN_INTERRUPT_PRIORITY << 24UL )
 
+/* Constants used to check the installation of the FreeRTOS interrupt handlers. */
+#define portSCB_VTOR_REG                      ( *( ( portISR_t ** ) 0xe000ed08 ) )
+#define portVECTOR_INDEX_PENDSV               ( 14 )
+
 /* Constants required to set up the initial stack. */
 #define portINITIAL_XPSR                      ( 0x01000000 )
 
@@ -200,20 +207,20 @@ void vPortSVCHandler( void )
 
 void vPortStartFirstTask( void )
 {
-    /* The MSP stack is not reset as, unlike on M3/4 parts, there is no vector
-     * table offset register that can be used to locate the initial stack value.
-     * Not all M0 parts have the application vector table at address 0. */
+    /* Don't reset the MSP stack as is done on CM3/4 devices. The vector table
+     * in some CM0 devices cannot be modified and thus may not hold the
+     * application's initial MSP value. */
     __asm volatile (
         "   .syntax unified             \n"
         "   ldr  r2, pxCurrentTCBConst2 \n"     /* Obtain location of pxCurrentTCB. */
         "   ldr  r3, [r2]               \n"
         "   ldr  r0, [r3]               \n"     /* The first item in pxCurrentTCB is the task top of stack. */
-        "   adds r0, #32                    \n" /* Discard everything up to r0. */
-        "   msr  psp, r0                    \n" /* This is now the new top of stack to use in the task. */
+        "   adds r0, #32                \n"     /* Discard everything up to r0. */
+        "   msr  psp, r0                \n"     /* This is now the new top of stack to use in the task. */
         "   movs r0, #2                 \n"     /* Switch to the psp stack. */
-        "   msr  CONTROL, r0                \n"
+        "   msr  CONTROL, r0            \n"
         "   isb                         \n"
-        "   pop  {r0-r5}                    \n" /* Pop the registers that are saved automatically. */
+        "   pop  {r0-r5}                \n"     /* Pop the registers that are saved automatically. */
         "   mov  lr, r5                 \n"     /* lr is now in r5. */
         "   pop  {r3}                   \n"     /* Return address is now in r3. */
         "   pop  {r2}                   \n"     /* Pop and discard XPSR. */
@@ -231,7 +238,42 @@ void vPortStartFirstTask( void )
  */
 BaseType_t xPortStartScheduler( void )
 {
-    /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+    /* An application can install FreeRTOS interrupt handlers in one of the
+     * folllowing ways:
+     * 1. Direct Routing - Install the function xPortPendSVHandler for PendSV
+     *    interrupt.
+     * 2. Indirect Routing - Install separate handler for PendSV interrupt and
+     *    route program control from that handler to xPortPendSVHandler function.
+     *
+     * Applications that use Indirect Routing must set
+     * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+     * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+     * is 1, should be preferred when possible. */
+    #if ( configCHECK_HANDLER_INSTALLATION == 1 )
+    {
+        /* Point pxVectorTable to the interrupt vector table. Systems without
+         * a VTOR register provide the value zero in the VTOR register and
+         * the vector table itself is located at the address 0x00000000. */
+        const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+        /* Validate that the application has correctly installed the FreeRTOS
+         * handler for PendSV interrupt. We do not check the installation of the
+         * SysTick handler because the application may choose to drive the RTOS
+         * tick using a timer other than the SysTick timer by overriding the
+         * weak function vPortSetupTimerInterrupt().
+         *
+         * Assertion failures here indicate incorrect installation of the
+         * FreeRTOS handler. For help installing the FreeRTOS handler, see
+         * https://www.FreeRTOS.org/FAQHelp.html.
+         *
+         * Systems with a configurable address for the interrupt vector table
+         * can also encounter assertion failures or even system faults here if
+         * VTOR is not set correctly to point to the application's vector table. */
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == xPortPendSVHandler );
+    }
+    #endif /* configCHECK_HANDLER_INSTALLATION */
+
+    /* Make PendSV and SysTick the lowest priority interrupts. */
     portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
 
diff --git a/portable/GCC/ARM_CM23/non_secure/port.c b/portable/GCC/ARM_CM23/non_secure/port.c
index 6a3877894..a5ed7004a 100644
--- a/portable/GCC/ARM_CM23/non_secure/port.c
+++ b/portable/GCC/ARM_CM23/non_secure/port.c
@@ -80,6 +80,12 @@
 #endif
 /*-----------------------------------------------------------*/
 
+/**
+ * @brief Prototype of all Interrupt Service Routines (ISRs).
+ */
+typedef void ( * portISR_t )( void );
+/*-----------------------------------------------------------*/
+
 /**
  * @brief Constants required to manipulate the NVIC.
  */
@@ -101,10 +107,18 @@
 /**
  * @brief Constants required to manipulate the SCB.
  */
-#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_VTOR_REG                      ( *( ( portISR_t ** ) 0xe000ed08 ) )
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
 #define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )
 /*-----------------------------------------------------------*/
 
+/**
+ * @brief Constants used to check the installation of the FreeRTOS interrupt handlers.
+ */
+#define portVECTOR_INDEX_SVC       ( 11 )
+#define portVECTOR_INDEX_PENDSV    ( 14 )
+/*-----------------------------------------------------------*/
+
 /**
  * @brief Constants required to check the validity of an interrupt priority.
  */
@@ -1598,22 +1612,52 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
+    /* An application can install FreeRTOS interrupt handlers in one of the
+     * folllowing ways:
+     * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
+     *    for SVCall and PendSV interrupts respectively.
+     * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+     *    interrupts and route program control from those handlers to
+     *    SVC_Handler and PendSV_Handler functions.
+     *
+     * Applications that use Indirect Routing must set
+     * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+     * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+     * is 1, should be preferred when possible. */
+    #if ( configCHECK_HANDLER_INSTALLATION == 1 )
+    {
+        const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+        /* Validate that the application has correctly installed the FreeRTOS
+         * handlers for SVCall and PendSV interrupts. We do not check the
+         * installation of the SysTick handler because the application may
+         * choose to drive the RTOS tick using a timer other than the SysTick
+         * timer by overriding the weak function vPortSetupTimerInterrupt().
+         *
+         * Assertion failures here indicate incorrect installation of the
+         * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+         * https://www.FreeRTOS.org/FAQHelp.html.
+         *
+         * Systems with a configurable address for the interrupt vector table
+         * can also encounter assertion failures or even system faults here if
+         * VTOR is not set correctly to point to the application's vector table. */
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler );
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler );
+    }
+    #endif /* configCHECK_HANDLER_INSTALLATION */
+
     #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
     {
-        volatile uint32_t ulOriginalPriority;
         volatile uint32_t ulImplementedPrioBits = 0;
         volatile uint8_t ucMaxPriorityValue;
 
         /* Determine the maximum priority from which ISR safe FreeRTOS API
-         * functions can be called.  ISR safe functions are those that end in
-         * "FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+         * functions can be called. ISR safe functions are those that end in
+         * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
          * ensure interrupt entry is as fast and simple as possible.
          *
-         * Save the interrupt priority value that is about to be clobbered. */
-        ulOriginalPriority = portNVIC_SHPR2_REG;
-
-        /* Determine the number of priority bits available.  First write to all
-         * possible bits. */
+         * First, determine the number of priority bits available. Write to all
+         * possible bits in the priority setting for SVCall. */
         portNVIC_SHPR2_REG = 0xFF000000;
 
         /* Read the value back to see how many bits stuck. */
@@ -1636,7 +1680,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         /* Calculate the maximum acceptable priority group value for the number
          * of bits read back. */
-
         while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
         {
             ulImplementedPrioBits++;
@@ -1674,16 +1717,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          * register. */
         ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
         ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
-        /* Restore the clobbered interrupt priority register to its original
-         * value. */
-        portNVIC_SHPR2_REG = ulOriginalPriority;
     }
     #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
-    /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+    /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
+     * the highest priority. */
     portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+    portNVIC_SHPR2_REG = 0;
 
     #if ( configENABLE_MPU == 1 )
     {
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
index 6a3877894..a5ed7004a 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
@@ -80,6 +80,12 @@
 #endif
 /*-----------------------------------------------------------*/
 
+/**
+ * @brief Prototype of all Interrupt Service Routines (ISRs).
+ */
+typedef void ( * portISR_t )( void );
+/*-----------------------------------------------------------*/
+
 /**
  * @brief Constants required to manipulate the NVIC.
  */
@@ -101,10 +107,18 @@
 /**
  * @brief Constants required to manipulate the SCB.
  */
-#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_VTOR_REG                      ( *( ( portISR_t ** ) 0xe000ed08 ) )
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
 #define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )
 /*-----------------------------------------------------------*/
 
+/**
+ * @brief Constants used to check the installation of the FreeRTOS interrupt handlers.
+ */
+#define portVECTOR_INDEX_SVC       ( 11 )
+#define portVECTOR_INDEX_PENDSV    ( 14 )
+/*-----------------------------------------------------------*/
+
 /**
  * @brief Constants required to check the validity of an interrupt priority.
  */
@@ -1598,22 +1612,52 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
+    /* An application can install FreeRTOS interrupt handlers in one of the
+     * folllowing ways:
+     * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
+     *    for SVCall and PendSV interrupts respectively.
+     * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+     *    interrupts and route program control from those handlers to
+     *    SVC_Handler and PendSV_Handler functions.
+     *
+     * Applications that use Indirect Routing must set
+     * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+     * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+     * is 1, should be preferred when possible. */
+    #if ( configCHECK_HANDLER_INSTALLATION == 1 )
+    {
+        const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+        /* Validate that the application has correctly installed the FreeRTOS
+         * handlers for SVCall and PendSV interrupts. We do not check the
+         * installation of the SysTick handler because the application may
+         * choose to drive the RTOS tick using a timer other than the SysTick
+         * timer by overriding the weak function vPortSetupTimerInterrupt().
+         *
+         * Assertion failures here indicate incorrect installation of the
+         * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+         * https://www.FreeRTOS.org/FAQHelp.html.
+         *
+         * Systems with a configurable address for the interrupt vector table
+         * can also encounter assertion failures or even system faults here if
+         * VTOR is not set correctly to point to the application's vector table. */
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler );
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler );
+    }
+    #endif /* configCHECK_HANDLER_INSTALLATION */
+
     #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
     {
-        volatile uint32_t ulOriginalPriority;
         volatile uint32_t ulImplementedPrioBits = 0;
         volatile uint8_t ucMaxPriorityValue;
 
         /* Determine the maximum priority from which ISR safe FreeRTOS API
-         * functions can be called.  ISR safe functions are those that end in
-         * "FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+         * functions can be called. ISR safe functions are those that end in
+         * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
          * ensure interrupt entry is as fast and simple as possible.
          *
-         * Save the interrupt priority value that is about to be clobbered. */
-        ulOriginalPriority = portNVIC_SHPR2_REG;
-
-        /* Determine the number of priority bits available.  First write to all
-         * possible bits. */
+         * First, determine the number of priority bits available. Write to all
+         * possible bits in the priority setting for SVCall. */
         portNVIC_SHPR2_REG = 0xFF000000;
 
         /* Read the value back to see how many bits stuck. */
@@ -1636,7 +1680,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         /* Calculate the maximum acceptable priority group value for the number
          * of bits read back. */
-
         while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
         {
             ulImplementedPrioBits++;
@@ -1674,16 +1717,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          * register. */
         ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
         ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
-        /* Restore the clobbered interrupt priority register to its original
-         * value. */
-        portNVIC_SHPR2_REG = ulOriginalPriority;
     }
     #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
-    /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+    /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
+     * the highest priority. */
     portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+    portNVIC_SHPR2_REG = 0;
 
     #if ( configENABLE_MPU == 1 )
     {
diff --git a/portable/GCC/ARM_CM3/port.c b/portable/GCC/ARM_CM3/port.c
index 483f81324..8ce6fa6c4 100644
--- a/portable/GCC/ARM_CM3/port.c
+++ b/portable/GCC/ARM_CM3/port.c
@@ -34,10 +34,14 @@
 #include "FreeRTOS.h"
 #include "task.h"
 
+/* Prototype of all Interrupt Service Routines (ISRs). */
+typedef void ( * portISR_t )( void );
+
 /* Constants required to manipulate the core.  Registers first... */
 #define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )
 #define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )
 #define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SHPR2_REG                    ( *( ( volatile uint32_t * ) 0xe000ed1c ) )
 #define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
 /* ...then bits in the registers. */
 #define portNVIC_SYSTICK_CLK_BIT              ( 1UL << 2UL )
@@ -52,6 +56,11 @@
 #define portNVIC_PENDSV_PRI                   ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
 #define portNVIC_SYSTICK_PRI                  ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
 
+/* Constants used to check the installation of the FreeRTOS interrupt handlers. */
+#define portSCB_VTOR_REG                      ( *( ( portISR_t ** ) 0xE000ED08 ) )
+#define portVECTOR_INDEX_SVC                  ( 11 )
+#define portVECTOR_INDEX_PENDSV               ( 14 )
+
 /* Constants required to check the validity of an interrupt priority. */
 #define portFIRST_USER_INTERRUPT_NUMBER       ( 16 )
 #define portNVIC_IP_REGISTERS_OFFSET_16       ( 0xE000E3F0 )
@@ -259,6 +268,40 @@ static void prvPortStartFirstTask( void )
  */
 BaseType_t xPortStartScheduler( void )
 {
+    /* An application can install FreeRTOS interrupt handlers in one of the
+     * folllowing ways:
+     * 1. Direct Routing - Install the functions vPortSVCHandler and
+     *    xPortPendSVHandler for SVCall and PendSV interrupts respectively.
+     * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+     *    interrupts and route program control from those handlers to
+     *    vPortSVCHandler and xPortPendSVHandler functions.
+     *
+     * Applications that use Indirect Routing must set
+     * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+     * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+     * is 1, should be preferred when possible. */
+    #if ( configCHECK_HANDLER_INSTALLATION == 1 )
+    {
+        const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+        /* Validate that the application has correctly installed the FreeRTOS
+         * handlers for SVCall and PendSV interrupts. We do not check the
+         * installation of the SysTick handler because the application may
+         * choose to drive the RTOS tick using a timer other than the SysTick
+         * timer by overriding the weak function vPortSetupTimerInterrupt().
+         *
+         * Assertion failures here indicate incorrect installation of the
+         * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+         * https://www.FreeRTOS.org/FAQHelp.html.
+         *
+         * Systems with a configurable address for the interrupt vector table
+         * can also encounter assertion failures or even system faults here if
+         * VTOR is not set correctly to point to the application's vector table. */
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == vPortSVCHandler );
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == xPortPendSVHandler );
+    }
+    #endif /* configCHECK_HANDLER_INSTALLATION */
+
     #if ( configASSERT_DEFINED == 1 )
     {
         volatile uint8_t ucOriginalPriority;
@@ -343,9 +386,11 @@ BaseType_t xPortStartScheduler( void )
     }
     #endif /* configASSERT_DEFINED */
 
-    /* Make PendSV and SysTick the lowest priority interrupts. */
+    /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
+     * the highest priority. */
     portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+    portNVIC_SHPR2_REG = 0;
 
     /* Start the timer that generates the tick ISR.  Interrupts are disabled
      * here already. */
diff --git a/portable/GCC/ARM_CM33/non_secure/port.c b/portable/GCC/ARM_CM33/non_secure/port.c
index 6a3877894..a5ed7004a 100644
--- a/portable/GCC/ARM_CM33/non_secure/port.c
+++ b/portable/GCC/ARM_CM33/non_secure/port.c
@@ -80,6 +80,12 @@
 #endif
 /*-----------------------------------------------------------*/
 
+/**
+ * @brief Prototype of all Interrupt Service Routines (ISRs).
+ */
+typedef void ( * portISR_t )( void );
+/*-----------------------------------------------------------*/
+
 /**
  * @brief Constants required to manipulate the NVIC.
  */
@@ -101,10 +107,18 @@
 /**
  * @brief Constants required to manipulate the SCB.
  */
-#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_VTOR_REG                      ( *( ( portISR_t ** ) 0xe000ed08 ) )
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
 #define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )
 /*-----------------------------------------------------------*/
 
+/**
+ * @brief Constants used to check the installation of the FreeRTOS interrupt handlers.
+ */
+#define portVECTOR_INDEX_SVC       ( 11 )
+#define portVECTOR_INDEX_PENDSV    ( 14 )
+/*-----------------------------------------------------------*/
+
 /**
  * @brief Constants required to check the validity of an interrupt priority.
  */
@@ -1598,22 +1612,52 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
+    /* An application can install FreeRTOS interrupt handlers in one of the
+     * folllowing ways:
+     * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
+     *    for SVCall and PendSV interrupts respectively.
+     * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+     *    interrupts and route program control from those handlers to
+     *    SVC_Handler and PendSV_Handler functions.
+     *
+     * Applications that use Indirect Routing must set
+     * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+     * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+     * is 1, should be preferred when possible. */
+    #if ( configCHECK_HANDLER_INSTALLATION == 1 )
+    {
+        const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+        /* Validate that the application has correctly installed the FreeRTOS
+         * handlers for SVCall and PendSV interrupts. We do not check the
+         * installation of the SysTick handler because the application may
+         * choose to drive the RTOS tick using a timer other than the SysTick
+         * timer by overriding the weak function vPortSetupTimerInterrupt().
+         *
+         * Assertion failures here indicate incorrect installation of the
+         * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+         * https://www.FreeRTOS.org/FAQHelp.html.
+         *
+         * Systems with a configurable address for the interrupt vector table
+         * can also encounter assertion failures or even system faults here if
+         * VTOR is not set correctly to point to the application's vector table. */
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler );
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler );
+    }
+    #endif /* configCHECK_HANDLER_INSTALLATION */
+
     #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
     {
-        volatile uint32_t ulOriginalPriority;
         volatile uint32_t ulImplementedPrioBits = 0;
         volatile uint8_t ucMaxPriorityValue;
 
         /* Determine the maximum priority from which ISR safe FreeRTOS API
-         * functions can be called.  ISR safe functions are those that end in
-         * "FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+         * functions can be called. ISR safe functions are those that end in
+         * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
          * ensure interrupt entry is as fast and simple as possible.
          *
-         * Save the interrupt priority value that is about to be clobbered. */
-        ulOriginalPriority = portNVIC_SHPR2_REG;
-
-        /* Determine the number of priority bits available.  First write to all
-         * possible bits. */
+         * First, determine the number of priority bits available. Write to all
+         * possible bits in the priority setting for SVCall. */
         portNVIC_SHPR2_REG = 0xFF000000;
 
         /* Read the value back to see how many bits stuck. */
@@ -1636,7 +1680,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         /* Calculate the maximum acceptable priority group value for the number
          * of bits read back. */
-
         while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
         {
             ulImplementedPrioBits++;
@@ -1674,16 +1717,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          * register. */
         ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
         ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
-        /* Restore the clobbered interrupt priority register to its original
-         * value. */
-        portNVIC_SHPR2_REG = ulOriginalPriority;
     }
     #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
-    /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+    /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
+     * the highest priority. */
     portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+    portNVIC_SHPR2_REG = 0;
 
     #if ( configENABLE_MPU == 1 )
     {
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
index 6a3877894..a5ed7004a 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
@@ -80,6 +80,12 @@
 #endif
 /*-----------------------------------------------------------*/
 
+/**
+ * @brief Prototype of all Interrupt Service Routines (ISRs).
+ */
+typedef void ( * portISR_t )( void );
+/*-----------------------------------------------------------*/
+
 /**
  * @brief Constants required to manipulate the NVIC.
  */
@@ -101,10 +107,18 @@
 /**
  * @brief Constants required to manipulate the SCB.
  */
-#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_VTOR_REG                      ( *( ( portISR_t ** ) 0xe000ed08 ) )
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
 #define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )
 /*-----------------------------------------------------------*/
 
+/**
+ * @brief Constants used to check the installation of the FreeRTOS interrupt handlers.
+ */
+#define portVECTOR_INDEX_SVC       ( 11 )
+#define portVECTOR_INDEX_PENDSV    ( 14 )
+/*-----------------------------------------------------------*/
+
 /**
  * @brief Constants required to check the validity of an interrupt priority.
  */
@@ -1598,22 +1612,52 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
+    /* An application can install FreeRTOS interrupt handlers in one of the
+     * folllowing ways:
+     * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
+     *    for SVCall and PendSV interrupts respectively.
+     * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+     *    interrupts and route program control from those handlers to
+     *    SVC_Handler and PendSV_Handler functions.
+     *
+     * Applications that use Indirect Routing must set
+     * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+     * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+     * is 1, should be preferred when possible. */
+    #if ( configCHECK_HANDLER_INSTALLATION == 1 )
+    {
+        const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+        /* Validate that the application has correctly installed the FreeRTOS
+         * handlers for SVCall and PendSV interrupts. We do not check the
+         * installation of the SysTick handler because the application may
+         * choose to drive the RTOS tick using a timer other than the SysTick
+         * timer by overriding the weak function vPortSetupTimerInterrupt().
+         *
+         * Assertion failures here indicate incorrect installation of the
+         * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+         * https://www.FreeRTOS.org/FAQHelp.html.
+         *
+         * Systems with a configurable address for the interrupt vector table
+         * can also encounter assertion failures or even system faults here if
+         * VTOR is not set correctly to point to the application's vector table. */
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler );
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler );
+    }
+    #endif /* configCHECK_HANDLER_INSTALLATION */
+
     #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
     {
-        volatile uint32_t ulOriginalPriority;
         volatile uint32_t ulImplementedPrioBits = 0;
         volatile uint8_t ucMaxPriorityValue;
 
         /* Determine the maximum priority from which ISR safe FreeRTOS API
-         * functions can be called.  ISR safe functions are those that end in
-         * "FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+         * functions can be called. ISR safe functions are those that end in
+         * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
          * ensure interrupt entry is as fast and simple as possible.
          *
-         * Save the interrupt priority value that is about to be clobbered. */
-        ulOriginalPriority = portNVIC_SHPR2_REG;
-
-        /* Determine the number of priority bits available.  First write to all
-         * possible bits. */
+         * First, determine the number of priority bits available. Write to all
+         * possible bits in the priority setting for SVCall. */
         portNVIC_SHPR2_REG = 0xFF000000;
 
         /* Read the value back to see how many bits stuck. */
@@ -1636,7 +1680,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         /* Calculate the maximum acceptable priority group value for the number
          * of bits read back. */
-
         while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
         {
             ulImplementedPrioBits++;
@@ -1674,16 +1717,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          * register. */
         ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
         ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
-        /* Restore the clobbered interrupt priority register to its original
-         * value. */
-        portNVIC_SHPR2_REG = ulOriginalPriority;
     }
     #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
-    /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+    /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
+     * the highest priority. */
     portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+    portNVIC_SHPR2_REG = 0;
 
     #if ( configENABLE_MPU == 1 )
     {
diff --git a/portable/GCC/ARM_CM35P/non_secure/port.c b/portable/GCC/ARM_CM35P/non_secure/port.c
index 6a3877894..a5ed7004a 100644
--- a/portable/GCC/ARM_CM35P/non_secure/port.c
+++ b/portable/GCC/ARM_CM35P/non_secure/port.c
@@ -80,6 +80,12 @@
 #endif
 /*-----------------------------------------------------------*/
 
+/**
+ * @brief Prototype of all Interrupt Service Routines (ISRs).
+ */
+typedef void ( * portISR_t )( void );
+/*-----------------------------------------------------------*/
+
 /**
  * @brief Constants required to manipulate the NVIC.
  */
@@ -101,10 +107,18 @@
 /**
  * @brief Constants required to manipulate the SCB.
  */
-#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_VTOR_REG                      ( *( ( portISR_t ** ) 0xe000ed08 ) )
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
 #define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )
 /*-----------------------------------------------------------*/
 
+/**
+ * @brief Constants used to check the installation of the FreeRTOS interrupt handlers.
+ */
+#define portVECTOR_INDEX_SVC       ( 11 )
+#define portVECTOR_INDEX_PENDSV    ( 14 )
+/*-----------------------------------------------------------*/
+
 /**
  * @brief Constants required to check the validity of an interrupt priority.
  */
@@ -1598,22 +1612,52 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
+    /* An application can install FreeRTOS interrupt handlers in one of the
+     * folllowing ways:
+     * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
+     *    for SVCall and PendSV interrupts respectively.
+     * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+     *    interrupts and route program control from those handlers to
+     *    SVC_Handler and PendSV_Handler functions.
+     *
+     * Applications that use Indirect Routing must set
+     * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+     * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+     * is 1, should be preferred when possible. */
+    #if ( configCHECK_HANDLER_INSTALLATION == 1 )
+    {
+        const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+        /* Validate that the application has correctly installed the FreeRTOS
+         * handlers for SVCall and PendSV interrupts. We do not check the
+         * installation of the SysTick handler because the application may
+         * choose to drive the RTOS tick using a timer other than the SysTick
+         * timer by overriding the weak function vPortSetupTimerInterrupt().
+         *
+         * Assertion failures here indicate incorrect installation of the
+         * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+         * https://www.FreeRTOS.org/FAQHelp.html.
+         *
+         * Systems with a configurable address for the interrupt vector table
+         * can also encounter assertion failures or even system faults here if
+         * VTOR is not set correctly to point to the application's vector table. */
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler );
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler );
+    }
+    #endif /* configCHECK_HANDLER_INSTALLATION */
+
     #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
     {
-        volatile uint32_t ulOriginalPriority;
         volatile uint32_t ulImplementedPrioBits = 0;
         volatile uint8_t ucMaxPriorityValue;
 
         /* Determine the maximum priority from which ISR safe FreeRTOS API
-         * functions can be called.  ISR safe functions are those that end in
-         * "FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+         * functions can be called. ISR safe functions are those that end in
+         * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
          * ensure interrupt entry is as fast and simple as possible.
          *
-         * Save the interrupt priority value that is about to be clobbered. */
-        ulOriginalPriority = portNVIC_SHPR2_REG;
-
-        /* Determine the number of priority bits available.  First write to all
-         * possible bits. */
+         * First, determine the number of priority bits available. Write to all
+         * possible bits in the priority setting for SVCall. */
         portNVIC_SHPR2_REG = 0xFF000000;
 
         /* Read the value back to see how many bits stuck. */
@@ -1636,7 +1680,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         /* Calculate the maximum acceptable priority group value for the number
          * of bits read back. */
-
         while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
         {
             ulImplementedPrioBits++;
@@ -1674,16 +1717,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          * register. */
         ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
         ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
-        /* Restore the clobbered interrupt priority register to its original
-         * value. */
-        portNVIC_SHPR2_REG = ulOriginalPriority;
     }
     #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
-    /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+    /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
+     * the highest priority. */
     portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+    portNVIC_SHPR2_REG = 0;
 
     #if ( configENABLE_MPU == 1 )
     {
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c b/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
index 6a3877894..a5ed7004a 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
@@ -80,6 +80,12 @@
 #endif
 /*-----------------------------------------------------------*/
 
+/**
+ * @brief Prototype of all Interrupt Service Routines (ISRs).
+ */
+typedef void ( * portISR_t )( void );
+/*-----------------------------------------------------------*/
+
 /**
  * @brief Constants required to manipulate the NVIC.
  */
@@ -101,10 +107,18 @@
 /**
  * @brief Constants required to manipulate the SCB.
  */
-#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_VTOR_REG                      ( *( ( portISR_t ** ) 0xe000ed08 ) )
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
 #define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )
 /*-----------------------------------------------------------*/
 
+/**
+ * @brief Constants used to check the installation of the FreeRTOS interrupt handlers.
+ */
+#define portVECTOR_INDEX_SVC       ( 11 )
+#define portVECTOR_INDEX_PENDSV    ( 14 )
+/*-----------------------------------------------------------*/
+
 /**
  * @brief Constants required to check the validity of an interrupt priority.
  */
@@ -1598,22 +1612,52 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
+    /* An application can install FreeRTOS interrupt handlers in one of the
+     * folllowing ways:
+     * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
+     *    for SVCall and PendSV interrupts respectively.
+     * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+     *    interrupts and route program control from those handlers to
+     *    SVC_Handler and PendSV_Handler functions.
+     *
+     * Applications that use Indirect Routing must set
+     * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+     * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+     * is 1, should be preferred when possible. */
+    #if ( configCHECK_HANDLER_INSTALLATION == 1 )
+    {
+        const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+        /* Validate that the application has correctly installed the FreeRTOS
+         * handlers for SVCall and PendSV interrupts. We do not check the
+         * installation of the SysTick handler because the application may
+         * choose to drive the RTOS tick using a timer other than the SysTick
+         * timer by overriding the weak function vPortSetupTimerInterrupt().
+         *
+         * Assertion failures here indicate incorrect installation of the
+         * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+         * https://www.FreeRTOS.org/FAQHelp.html.
+         *
+         * Systems with a configurable address for the interrupt vector table
+         * can also encounter assertion failures or even system faults here if
+         * VTOR is not set correctly to point to the application's vector table. */
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler );
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler );
+    }
+    #endif /* configCHECK_HANDLER_INSTALLATION */
+
     #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
     {
-        volatile uint32_t ulOriginalPriority;
         volatile uint32_t ulImplementedPrioBits = 0;
         volatile uint8_t ucMaxPriorityValue;
 
         /* Determine the maximum priority from which ISR safe FreeRTOS API
-         * functions can be called.  ISR safe functions are those that end in
-         * "FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+         * functions can be called. ISR safe functions are those that end in
+         * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
          * ensure interrupt entry is as fast and simple as possible.
          *
-         * Save the interrupt priority value that is about to be clobbered. */
-        ulOriginalPriority = portNVIC_SHPR2_REG;
-
-        /* Determine the number of priority bits available.  First write to all
-         * possible bits. */
+         * First, determine the number of priority bits available. Write to all
+         * possible bits in the priority setting for SVCall. */
         portNVIC_SHPR2_REG = 0xFF000000;
 
         /* Read the value back to see how many bits stuck. */
@@ -1636,7 +1680,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         /* Calculate the maximum acceptable priority group value for the number
          * of bits read back. */
-
         while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
         {
             ulImplementedPrioBits++;
@@ -1674,16 +1717,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          * register. */
         ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
         ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
-        /* Restore the clobbered interrupt priority register to its original
-         * value. */
-        portNVIC_SHPR2_REG = ulOriginalPriority;
     }
     #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
-    /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+    /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
+     * the highest priority. */
     portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+    portNVIC_SHPR2_REG = 0;
 
     #if ( configENABLE_MPU == 1 )
     {
diff --git a/portable/GCC/ARM_CM3_MPU/port.c b/portable/GCC/ARM_CM3_MPU/port.c
index 1b774bdc7..d8c18325c 100644
--- a/portable/GCC/ARM_CM3_MPU/port.c
+++ b/portable/GCC/ARM_CM3_MPU/port.c
@@ -58,6 +58,9 @@
     #define configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS    1
 #endif
 
+/* Prototype of all Interrupt Service Routines (ISRs). */
+typedef void ( * portISR_t )( void );
+
 /* Constants required to access and manipulate the NVIC. */
 #define portNVIC_SYSTICK_CTRL_REG                 ( *( ( volatile uint32_t * ) 0xe000e010 ) )
 #define portNVIC_SYSTICK_LOAD_REG                 ( *( ( volatile uint32_t * ) 0xe000e014 ) )
@@ -87,7 +90,6 @@
 #define portMIN_INTERRUPT_PRIORITY                ( 255UL )
 #define portNVIC_PENDSV_PRI                       ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
 #define portNVIC_SYSTICK_PRI                      ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
-#define portNVIC_SVC_PRI                          ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )
 
 /* Constants required to set up the initial stack. */
 #define portINITIAL_XPSR                          ( 0x01000000 )
@@ -95,6 +97,11 @@
 #define portINITIAL_CONTROL_IF_UNPRIVILEGED       ( 0x03 )
 #define portINITIAL_CONTROL_IF_PRIVILEGED         ( 0x02 )
 
+/* Constants used to check the installation of the FreeRTOS interrupt handlers. */
+#define portSCB_VTOR_REG                          ( *( ( portISR_t ** ) 0xE000ED08 ) )
+#define portVECTOR_INDEX_SVC                      ( 11 )
+#define portVECTOR_INDEX_PENDSV                   ( 14 )
+
 /* Constants required to check the validity of an interrupt priority. */
 #define portFIRST_USER_INTERRUPT_NUMBER           ( 16 )
 #define portNVIC_IP_REGISTERS_OFFSET_16           ( 0xE000E3F0 )
@@ -414,7 +421,6 @@ void vSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
     switch( ucSVCNumber )
     {
         case portSVC_START_SCHEDULER:
-            portNVIC_SHPR2_REG |= portNVIC_SVC_PRI;
             prvRestoreContextOfFirstTask();
             break;
 
@@ -737,6 +743,40 @@ static void prvRestoreContextOfFirstTask( void )
  */
 BaseType_t xPortStartScheduler( void )
 {
+    /* An application can install FreeRTOS interrupt handlers in one of the
+     * folllowing ways:
+     * 1. Direct Routing - Install the functions vPortSVCHandler and
+     *    xPortPendSVHandler for SVCall and PendSV interrupts respectively.
+     * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+     *    interrupts and route program control from those handlers to
+     *    vPortSVCHandler and xPortPendSVHandler functions.
+     *
+     * Applications that use Indirect Routing must set
+     * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+     * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+     * is 1, should be preferred when possible. */
+    #if ( configCHECK_HANDLER_INSTALLATION == 1 )
+    {
+        const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+        /* Validate that the application has correctly installed the FreeRTOS
+         * handlers for SVCall and PendSV interrupts. We do not check the
+         * installation of the SysTick handler because the application may
+         * choose to drive the RTOS tick using a timer other than the SysTick
+         * timer by overriding the weak function vPortSetupTimerInterrupt().
+         *
+         * Assertion failures here indicate incorrect installation of the
+         * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+         * https://www.FreeRTOS.org/FAQHelp.html.
+         *
+         * Systems with a configurable address for the interrupt vector table
+         * can also encounter assertion failures or even system faults here if
+         * VTOR is not set correctly to point to the application's vector table. */
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == vPortSVCHandler );
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == xPortPendSVHandler );
+    }
+    #endif /* configCHECK_HANDLER_INSTALLATION */
+
     #if ( configASSERT_DEFINED == 1 )
     {
         volatile uint8_t ucOriginalPriority;
@@ -821,11 +861,12 @@ BaseType_t xPortStartScheduler( void )
     }
     #endif /* configASSERT_DEFINED */
 
-    /* Make PendSV and SysTick the same priority as the kernel, and the SVC
-     * handler higher priority so it can be used to exit a critical section (where
-     * lower priorities are masked). */
+    /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
+     * the highest priority. */
     portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+    portNVIC_SHPR2_REG = 0;
+
 
     /* Configure the regions in the MPU that are common to all tasks. */
     prvSetupMPU();
diff --git a/portable/GCC/ARM_CM4F/port.c b/portable/GCC/ARM_CM4F/port.c
index 3846a50f6..3e5151bdc 100644
--- a/portable/GCC/ARM_CM4F/port.c
+++ b/portable/GCC/ARM_CM4F/port.c
@@ -38,10 +38,14 @@
     #error This port can only be used when the project options are configured to enable hardware floating point support.
 #endif
 
+/* Prototype of all Interrupt Service Routines (ISRs). */
+typedef void ( * portISR_t )( void );
+
 /* Constants required to manipulate the core.  Registers first... */
 #define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )
 #define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )
 #define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SHPR2_REG                    ( *( ( volatile uint32_t * ) 0xe000ed1c ) )
 #define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
 /* ...then bits in the registers. */
 #define portNVIC_SYSTICK_CLK_BIT              ( 1UL << 2UL )
@@ -62,6 +66,11 @@
 #define portNVIC_PENDSV_PRI                   ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
 #define portNVIC_SYSTICK_PRI                  ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
 
+/* Constants used to check the installation of the FreeRTOS interrupt handlers. */
+#define portSCB_VTOR_REG                      ( *( ( portISR_t ** ) 0xE000ED08 ) )
+#define portVECTOR_INDEX_SVC                  ( 11 )
+#define portVECTOR_INDEX_PENDSV               ( 14 )
+
 /* Constants required to check the validity of an interrupt priority. */
 #define portFIRST_USER_INTERRUPT_NUMBER       ( 16 )
 #define portNVIC_IP_REGISTERS_OFFSET_16       ( 0xE000E3F0 )
@@ -302,6 +311,40 @@ BaseType_t xPortStartScheduler( void )
     configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
     configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
 
+    /* An application can install FreeRTOS interrupt handlers in one of the
+     * folllowing ways:
+     * 1. Direct Routing - Install the functions vPortSVCHandler and
+     *    xPortPendSVHandler for SVCall and PendSV interrupts respectively.
+     * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+     *    interrupts and route program control from those handlers to
+     *    vPortSVCHandler and xPortPendSVHandler functions.
+     *
+     * Applications that use Indirect Routing must set
+     * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+     * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+     * is 1, should be preferred when possible. */
+    #if ( configCHECK_HANDLER_INSTALLATION == 1 )
+    {
+        const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+        /* Validate that the application has correctly installed the FreeRTOS
+         * handlers for SVCall and PendSV interrupts. We do not check the
+         * installation of the SysTick handler because the application may
+         * choose to drive the RTOS tick using a timer other than the SysTick
+         * timer by overriding the weak function vPortSetupTimerInterrupt().
+         *
+         * Assertion failures here indicate incorrect installation of the
+         * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+         * https://www.FreeRTOS.org/FAQHelp.html.
+         *
+         * Systems with a configurable address for the interrupt vector table
+         * can also encounter assertion failures or even system faults here if
+         * VTOR is not set correctly to point to the application's vector table. */
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == vPortSVCHandler );
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == xPortPendSVHandler );
+    }
+    #endif /* configCHECK_HANDLER_INSTALLATION */
+
     #if ( configASSERT_DEFINED == 1 )
     {
         volatile uint8_t ucOriginalPriority;
@@ -386,9 +429,11 @@ BaseType_t xPortStartScheduler( void )
     }
     #endif /* configASSERT_DEFINED */
 
-    /* Make PendSV and SysTick the lowest priority interrupts. */
+    /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
+     * the highest priority. */
     portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+    portNVIC_SHPR2_REG = 0;
 
     /* Start the timer that generates the tick ISR.  Interrupts are disabled
      * here already. */
diff --git a/portable/GCC/ARM_CM4_MPU/port.c b/portable/GCC/ARM_CM4_MPU/port.c
index ac602caaf..0775cfbf8 100644
--- a/portable/GCC/ARM_CM4_MPU/port.c
+++ b/portable/GCC/ARM_CM4_MPU/port.c
@@ -62,6 +62,9 @@
     #define configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS    1
 #endif
 
+/* Prototype of all Interrupt Service Routines (ISRs). */
+typedef void ( * portISR_t )( void );
+
 /* Constants required to access and manipulate the NVIC. */
 #define portNVIC_SYSTICK_CTRL_REG                 ( *( ( volatile uint32_t * ) 0xe000e010 ) )
 #define portNVIC_SYSTICK_LOAD_REG                 ( *( ( volatile uint32_t * ) 0xe000e014 ) )
@@ -97,7 +100,6 @@
 #define portMIN_INTERRUPT_PRIORITY                ( 255UL )
 #define portNVIC_PENDSV_PRI                       ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
 #define portNVIC_SYSTICK_PRI                      ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
-#define portNVIC_SVC_PRI                          ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )
 
 /* Constants required to manipulate the VFP. */
 #define portFPCCR                                 ( ( volatile uint32_t * ) 0xe000ef34UL ) /* Floating point context control register. */
@@ -109,6 +111,11 @@
 #define portINITIAL_CONTROL_IF_UNPRIVILEGED       ( 0x03 )
 #define portINITIAL_CONTROL_IF_PRIVILEGED         ( 0x02 )
 
+/* Constants used to check the installation of the FreeRTOS interrupt handlers. */
+#define portSCB_VTOR_REG                          ( *( ( portISR_t ** ) 0xE000ED08 ) )
+#define portVECTOR_INDEX_SVC                      ( 11 )
+#define portVECTOR_INDEX_PENDSV                   ( 14 )
+
 /* Constants required to check the validity of an interrupt priority. */
 #define portFIRST_USER_INTERRUPT_NUMBER           ( 16 )
 #define portNVIC_IP_REGISTERS_OFFSET_16           ( 0xE000E3F0 )
@@ -448,7 +455,6 @@ void vSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
     switch( ucSVCNumber )
     {
         case portSVC_START_SCHEDULER:
-            portNVIC_SHPR2_REG |= portNVIC_SVC_PRI;
             prvRestoreContextOfFirstTask();
             break;
 
@@ -823,6 +829,40 @@ BaseType_t xPortStartScheduler( void )
         configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
     #endif
 
+    /* An application can install FreeRTOS interrupt handlers in one of the
+     * folllowing ways:
+     * 1. Direct Routing - Install the functions vPortSVCHandler and
+     *    xPortPendSVHandler for SVCall and PendSV interrupts respectively.
+     * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+     *    interrupts and route program control from those handlers to
+     *    vPortSVCHandler and xPortPendSVHandler functions.
+     *
+     * Applications that use Indirect Routing must set
+     * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+     * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+     * is 1, should be preferred when possible. */
+    #if ( configCHECK_HANDLER_INSTALLATION == 1 )
+    {
+        const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+        /* Validate that the application has correctly installed the FreeRTOS
+         * handlers for SVCall and PendSV interrupts. We do not check the
+         * installation of the SysTick handler because the application may
+         * choose to drive the RTOS tick using a timer other than the SysTick
+         * timer by overriding the weak function vPortSetupTimerInterrupt().
+         *
+         * Assertion failures here indicate incorrect installation of the
+         * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+         * https://www.FreeRTOS.org/FAQHelp.html.
+         *
+         * Systems with a configurable address for the interrupt vector table
+         * can also encounter assertion failures or even system faults here if
+         * VTOR is not set correctly to point to the application's vector table. */
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == vPortSVCHandler );
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == xPortPendSVHandler );
+    }
+    #endif /* configCHECK_HANDLER_INSTALLATION */
+
     #if ( configASSERT_DEFINED == 1 )
     {
         volatile uint8_t ucOriginalPriority;
@@ -907,11 +947,11 @@ BaseType_t xPortStartScheduler( void )
     }
     #endif /* configASSERT_DEFINED */
 
-    /* Make PendSV and SysTick the same priority as the kernel, and the SVC
-     * handler higher priority so it can be used to exit a critical section (where
-     * lower priorities are masked). */
+    /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
+     * the highest priority. */
     portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+    portNVIC_SHPR2_REG = 0;
 
     /* Configure the regions in the MPU that are common to all tasks. */
     prvSetupMPU();
diff --git a/portable/GCC/ARM_CM55/non_secure/port.c b/portable/GCC/ARM_CM55/non_secure/port.c
index 6a3877894..a5ed7004a 100644
--- a/portable/GCC/ARM_CM55/non_secure/port.c
+++ b/portable/GCC/ARM_CM55/non_secure/port.c
@@ -80,6 +80,12 @@
 #endif
 /*-----------------------------------------------------------*/
 
+/**
+ * @brief Prototype of all Interrupt Service Routines (ISRs).
+ */
+typedef void ( * portISR_t )( void );
+/*-----------------------------------------------------------*/
+
 /**
  * @brief Constants required to manipulate the NVIC.
  */
@@ -101,10 +107,18 @@
 /**
  * @brief Constants required to manipulate the SCB.
  */
-#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_VTOR_REG                      ( *( ( portISR_t ** ) 0xe000ed08 ) )
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
 #define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )
 /*-----------------------------------------------------------*/
 
+/**
+ * @brief Constants used to check the installation of the FreeRTOS interrupt handlers.
+ */
+#define portVECTOR_INDEX_SVC       ( 11 )
+#define portVECTOR_INDEX_PENDSV    ( 14 )
+/*-----------------------------------------------------------*/
+
 /**
  * @brief Constants required to check the validity of an interrupt priority.
  */
@@ -1598,22 +1612,52 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
+    /* An application can install FreeRTOS interrupt handlers in one of the
+     * folllowing ways:
+     * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
+     *    for SVCall and PendSV interrupts respectively.
+     * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+     *    interrupts and route program control from those handlers to
+     *    SVC_Handler and PendSV_Handler functions.
+     *
+     * Applications that use Indirect Routing must set
+     * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+     * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+     * is 1, should be preferred when possible. */
+    #if ( configCHECK_HANDLER_INSTALLATION == 1 )
+    {
+        const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+        /* Validate that the application has correctly installed the FreeRTOS
+         * handlers for SVCall and PendSV interrupts. We do not check the
+         * installation of the SysTick handler because the application may
+         * choose to drive the RTOS tick using a timer other than the SysTick
+         * timer by overriding the weak function vPortSetupTimerInterrupt().
+         *
+         * Assertion failures here indicate incorrect installation of the
+         * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+         * https://www.FreeRTOS.org/FAQHelp.html.
+         *
+         * Systems with a configurable address for the interrupt vector table
+         * can also encounter assertion failures or even system faults here if
+         * VTOR is not set correctly to point to the application's vector table. */
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler );
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler );
+    }
+    #endif /* configCHECK_HANDLER_INSTALLATION */
+
     #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
     {
-        volatile uint32_t ulOriginalPriority;
         volatile uint32_t ulImplementedPrioBits = 0;
         volatile uint8_t ucMaxPriorityValue;
 
         /* Determine the maximum priority from which ISR safe FreeRTOS API
-         * functions can be called.  ISR safe functions are those that end in
-         * "FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+         * functions can be called. ISR safe functions are those that end in
+         * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
          * ensure interrupt entry is as fast and simple as possible.
          *
-         * Save the interrupt priority value that is about to be clobbered. */
-        ulOriginalPriority = portNVIC_SHPR2_REG;
-
-        /* Determine the number of priority bits available.  First write to all
-         * possible bits. */
+         * First, determine the number of priority bits available. Write to all
+         * possible bits in the priority setting for SVCall. */
         portNVIC_SHPR2_REG = 0xFF000000;
 
         /* Read the value back to see how many bits stuck. */
@@ -1636,7 +1680,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         /* Calculate the maximum acceptable priority group value for the number
          * of bits read back. */
-
         while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
         {
             ulImplementedPrioBits++;
@@ -1674,16 +1717,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          * register. */
         ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
         ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
-        /* Restore the clobbered interrupt priority register to its original
-         * value. */
-        portNVIC_SHPR2_REG = ulOriginalPriority;
     }
     #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
-    /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+    /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
+     * the highest priority. */
     portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+    portNVIC_SHPR2_REG = 0;
 
     #if ( configENABLE_MPU == 1 )
     {
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/port.c b/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
index 6a3877894..a5ed7004a 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
@@ -80,6 +80,12 @@
 #endif
 /*-----------------------------------------------------------*/
 
+/**
+ * @brief Prototype of all Interrupt Service Routines (ISRs).
+ */
+typedef void ( * portISR_t )( void );
+/*-----------------------------------------------------------*/
+
 /**
  * @brief Constants required to manipulate the NVIC.
  */
@@ -101,10 +107,18 @@
 /**
  * @brief Constants required to manipulate the SCB.
  */
-#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_VTOR_REG                      ( *( ( portISR_t ** ) 0xe000ed08 ) )
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
 #define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )
 /*-----------------------------------------------------------*/
 
+/**
+ * @brief Constants used to check the installation of the FreeRTOS interrupt handlers.
+ */
+#define portVECTOR_INDEX_SVC       ( 11 )
+#define portVECTOR_INDEX_PENDSV    ( 14 )
+/*-----------------------------------------------------------*/
+
 /**
  * @brief Constants required to check the validity of an interrupt priority.
  */
@@ -1598,22 +1612,52 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
+    /* An application can install FreeRTOS interrupt handlers in one of the
+     * folllowing ways:
+     * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
+     *    for SVCall and PendSV interrupts respectively.
+     * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+     *    interrupts and route program control from those handlers to
+     *    SVC_Handler and PendSV_Handler functions.
+     *
+     * Applications that use Indirect Routing must set
+     * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+     * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+     * is 1, should be preferred when possible. */
+    #if ( configCHECK_HANDLER_INSTALLATION == 1 )
+    {
+        const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+        /* Validate that the application has correctly installed the FreeRTOS
+         * handlers for SVCall and PendSV interrupts. We do not check the
+         * installation of the SysTick handler because the application may
+         * choose to drive the RTOS tick using a timer other than the SysTick
+         * timer by overriding the weak function vPortSetupTimerInterrupt().
+         *
+         * Assertion failures here indicate incorrect installation of the
+         * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+         * https://www.FreeRTOS.org/FAQHelp.html.
+         *
+         * Systems with a configurable address for the interrupt vector table
+         * can also encounter assertion failures or even system faults here if
+         * VTOR is not set correctly to point to the application's vector table. */
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler );
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler );
+    }
+    #endif /* configCHECK_HANDLER_INSTALLATION */
+
     #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
     {
-        volatile uint32_t ulOriginalPriority;
         volatile uint32_t ulImplementedPrioBits = 0;
         volatile uint8_t ucMaxPriorityValue;
 
         /* Determine the maximum priority from which ISR safe FreeRTOS API
-         * functions can be called.  ISR safe functions are those that end in
-         * "FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+         * functions can be called. ISR safe functions are those that end in
+         * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
          * ensure interrupt entry is as fast and simple as possible.
          *
-         * Save the interrupt priority value that is about to be clobbered. */
-        ulOriginalPriority = portNVIC_SHPR2_REG;
-
-        /* Determine the number of priority bits available.  First write to all
-         * possible bits. */
+         * First, determine the number of priority bits available. Write to all
+         * possible bits in the priority setting for SVCall. */
         portNVIC_SHPR2_REG = 0xFF000000;
 
         /* Read the value back to see how many bits stuck. */
@@ -1636,7 +1680,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         /* Calculate the maximum acceptable priority group value for the number
          * of bits read back. */
-
         while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
         {
             ulImplementedPrioBits++;
@@ -1674,16 +1717,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          * register. */
         ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
         ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
-        /* Restore the clobbered interrupt priority register to its original
-         * value. */
-        portNVIC_SHPR2_REG = ulOriginalPriority;
     }
     #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
-    /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+    /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
+     * the highest priority. */
     portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+    portNVIC_SHPR2_REG = 0;
 
     #if ( configENABLE_MPU == 1 )
     {
diff --git a/portable/GCC/ARM_CM7/r0p1/port.c b/portable/GCC/ARM_CM7/r0p1/port.c
index c22a3592b..3070445ab 100644
--- a/portable/GCC/ARM_CM7/r0p1/port.c
+++ b/portable/GCC/ARM_CM7/r0p1/port.c
@@ -38,10 +38,14 @@
     #error This port can only be used when the project options are configured to enable hardware floating point support.
 #endif
 
+/* Prototype of all Interrupt Service Routines (ISRs). */
+typedef void ( * portISR_t )( void );
+
 /* Constants required to manipulate the core.  Registers first... */
 #define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )
 #define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )
 #define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SHPR2_REG                    ( *( ( volatile uint32_t * ) 0xe000ed1c ) )
 #define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
 /* ...then bits in the registers. */
 #define portNVIC_SYSTICK_CLK_BIT              ( 1UL << 2UL )
@@ -56,6 +60,11 @@
 #define portNVIC_PENDSV_PRI                   ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
 #define portNVIC_SYSTICK_PRI                  ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
 
+/* Constants used to check the installation of the FreeRTOS interrupt handlers. */
+#define portSCB_VTOR_REG                      ( *( ( portISR_t ** ) 0xE000ED08 ) )
+#define portVECTOR_INDEX_SVC                  ( 11 )
+#define portVECTOR_INDEX_PENDSV               ( 14 )
+
 /* Constants required to check the validity of an interrupt priority. */
 #define portFIRST_USER_INTERRUPT_NUMBER       ( 16 )
 #define portNVIC_IP_REGISTERS_OFFSET_16       ( 0xE000E3F0 )
@@ -290,6 +299,40 @@ static void prvPortStartFirstTask( void )
  */
 BaseType_t xPortStartScheduler( void )
 {
+    /* An application can install FreeRTOS interrupt handlers in one of the
+     * folllowing ways:
+     * 1. Direct Routing - Install the functions vPortSVCHandler and
+     *    xPortPendSVHandler for SVCall and PendSV interrupts respectively.
+     * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+     *    interrupts and route program control from those handlers to
+     *    vPortSVCHandler and xPortPendSVHandler functions.
+     *
+     * Applications that use Indirect Routing must set
+     * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+     * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+     * is 1, should be preferred when possible. */
+    #if ( configCHECK_HANDLER_INSTALLATION == 1 )
+    {
+        const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+        /* Validate that the application has correctly installed the FreeRTOS
+         * handlers for SVCall and PendSV interrupts. We do not check the
+         * installation of the SysTick handler because the application may
+         * choose to drive the RTOS tick using a timer other than the SysTick
+         * timer by overriding the weak function vPortSetupTimerInterrupt().
+         *
+         * Assertion failures here indicate incorrect installation of the
+         * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+         * https://www.FreeRTOS.org/FAQHelp.html.
+         *
+         * Systems with a configurable address for the interrupt vector table
+         * can also encounter assertion failures or even system faults here if
+         * VTOR is not set correctly to point to the application's vector table. */
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == vPortSVCHandler );
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == xPortPendSVHandler );
+    }
+    #endif /* configCHECK_HANDLER_INSTALLATION */
+
     #if ( configASSERT_DEFINED == 1 )
     {
         volatile uint8_t ucOriginalPriority;
@@ -374,9 +417,11 @@ BaseType_t xPortStartScheduler( void )
     }
     #endif /* configASSERT_DEFINED */
 
-    /* Make PendSV and SysTick the lowest priority interrupts. */
+    /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
+     * the highest priority. */
     portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+    portNVIC_SHPR2_REG = 0;
 
     /* Start the timer that generates the tick ISR.  Interrupts are disabled
      * here already. */
diff --git a/portable/GCC/ARM_CM85/non_secure/port.c b/portable/GCC/ARM_CM85/non_secure/port.c
index 6a3877894..a5ed7004a 100644
--- a/portable/GCC/ARM_CM85/non_secure/port.c
+++ b/portable/GCC/ARM_CM85/non_secure/port.c
@@ -80,6 +80,12 @@
 #endif
 /*-----------------------------------------------------------*/
 
+/**
+ * @brief Prototype of all Interrupt Service Routines (ISRs).
+ */
+typedef void ( * portISR_t )( void );
+/*-----------------------------------------------------------*/
+
 /**
  * @brief Constants required to manipulate the NVIC.
  */
@@ -101,10 +107,18 @@
 /**
  * @brief Constants required to manipulate the SCB.
  */
-#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_VTOR_REG                      ( *( ( portISR_t ** ) 0xe000ed08 ) )
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
 #define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )
 /*-----------------------------------------------------------*/
 
+/**
+ * @brief Constants used to check the installation of the FreeRTOS interrupt handlers.
+ */
+#define portVECTOR_INDEX_SVC       ( 11 )
+#define portVECTOR_INDEX_PENDSV    ( 14 )
+/*-----------------------------------------------------------*/
+
 /**
  * @brief Constants required to check the validity of an interrupt priority.
  */
@@ -1598,22 +1612,52 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
+    /* An application can install FreeRTOS interrupt handlers in one of the
+     * folllowing ways:
+     * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
+     *    for SVCall and PendSV interrupts respectively.
+     * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+     *    interrupts and route program control from those handlers to
+     *    SVC_Handler and PendSV_Handler functions.
+     *
+     * Applications that use Indirect Routing must set
+     * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+     * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+     * is 1, should be preferred when possible. */
+    #if ( configCHECK_HANDLER_INSTALLATION == 1 )
+    {
+        const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+        /* Validate that the application has correctly installed the FreeRTOS
+         * handlers for SVCall and PendSV interrupts. We do not check the
+         * installation of the SysTick handler because the application may
+         * choose to drive the RTOS tick using a timer other than the SysTick
+         * timer by overriding the weak function vPortSetupTimerInterrupt().
+         *
+         * Assertion failures here indicate incorrect installation of the
+         * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+         * https://www.FreeRTOS.org/FAQHelp.html.
+         *
+         * Systems with a configurable address for the interrupt vector table
+         * can also encounter assertion failures or even system faults here if
+         * VTOR is not set correctly to point to the application's vector table. */
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler );
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler );
+    }
+    #endif /* configCHECK_HANDLER_INSTALLATION */
+
     #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
     {
-        volatile uint32_t ulOriginalPriority;
         volatile uint32_t ulImplementedPrioBits = 0;
         volatile uint8_t ucMaxPriorityValue;
 
         /* Determine the maximum priority from which ISR safe FreeRTOS API
-         * functions can be called.  ISR safe functions are those that end in
-         * "FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+         * functions can be called. ISR safe functions are those that end in
+         * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
          * ensure interrupt entry is as fast and simple as possible.
          *
-         * Save the interrupt priority value that is about to be clobbered. */
-        ulOriginalPriority = portNVIC_SHPR2_REG;
-
-        /* Determine the number of priority bits available.  First write to all
-         * possible bits. */
+         * First, determine the number of priority bits available. Write to all
+         * possible bits in the priority setting for SVCall. */
         portNVIC_SHPR2_REG = 0xFF000000;
 
         /* Read the value back to see how many bits stuck. */
@@ -1636,7 +1680,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         /* Calculate the maximum acceptable priority group value for the number
          * of bits read back. */
-
         while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
         {
             ulImplementedPrioBits++;
@@ -1674,16 +1717,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          * register. */
         ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
         ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
-        /* Restore the clobbered interrupt priority register to its original
-         * value. */
-        portNVIC_SHPR2_REG = ulOriginalPriority;
     }
     #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
-    /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+    /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
+     * the highest priority. */
     portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+    portNVIC_SHPR2_REG = 0;
 
     #if ( configENABLE_MPU == 1 )
     {
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/port.c b/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
index 6a3877894..a5ed7004a 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
@@ -80,6 +80,12 @@
 #endif
 /*-----------------------------------------------------------*/
 
+/**
+ * @brief Prototype of all Interrupt Service Routines (ISRs).
+ */
+typedef void ( * portISR_t )( void );
+/*-----------------------------------------------------------*/
+
 /**
  * @brief Constants required to manipulate the NVIC.
  */
@@ -101,10 +107,18 @@
 /**
  * @brief Constants required to manipulate the SCB.
  */
-#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_VTOR_REG                      ( *( ( portISR_t ** ) 0xe000ed08 ) )
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
 #define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )
 /*-----------------------------------------------------------*/
 
+/**
+ * @brief Constants used to check the installation of the FreeRTOS interrupt handlers.
+ */
+#define portVECTOR_INDEX_SVC       ( 11 )
+#define portVECTOR_INDEX_PENDSV    ( 14 )
+/*-----------------------------------------------------------*/
+
 /**
  * @brief Constants required to check the validity of an interrupt priority.
  */
@@ -1598,22 +1612,52 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
+    /* An application can install FreeRTOS interrupt handlers in one of the
+     * folllowing ways:
+     * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
+     *    for SVCall and PendSV interrupts respectively.
+     * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+     *    interrupts and route program control from those handlers to
+     *    SVC_Handler and PendSV_Handler functions.
+     *
+     * Applications that use Indirect Routing must set
+     * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+     * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+     * is 1, should be preferred when possible. */
+    #if ( configCHECK_HANDLER_INSTALLATION == 1 )
+    {
+        const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+        /* Validate that the application has correctly installed the FreeRTOS
+         * handlers for SVCall and PendSV interrupts. We do not check the
+         * installation of the SysTick handler because the application may
+         * choose to drive the RTOS tick using a timer other than the SysTick
+         * timer by overriding the weak function vPortSetupTimerInterrupt().
+         *
+         * Assertion failures here indicate incorrect installation of the
+         * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+         * https://www.FreeRTOS.org/FAQHelp.html.
+         *
+         * Systems with a configurable address for the interrupt vector table
+         * can also encounter assertion failures or even system faults here if
+         * VTOR is not set correctly to point to the application's vector table. */
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler );
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler );
+    }
+    #endif /* configCHECK_HANDLER_INSTALLATION */
+
     #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
     {
-        volatile uint32_t ulOriginalPriority;
         volatile uint32_t ulImplementedPrioBits = 0;
         volatile uint8_t ucMaxPriorityValue;
 
         /* Determine the maximum priority from which ISR safe FreeRTOS API
-         * functions can be called.  ISR safe functions are those that end in
-         * "FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+         * functions can be called. ISR safe functions are those that end in
+         * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
          * ensure interrupt entry is as fast and simple as possible.
          *
-         * Save the interrupt priority value that is about to be clobbered. */
-        ulOriginalPriority = portNVIC_SHPR2_REG;
-
-        /* Determine the number of priority bits available.  First write to all
-         * possible bits. */
+         * First, determine the number of priority bits available. Write to all
+         * possible bits in the priority setting for SVCall. */
         portNVIC_SHPR2_REG = 0xFF000000;
 
         /* Read the value back to see how many bits stuck. */
@@ -1636,7 +1680,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         /* Calculate the maximum acceptable priority group value for the number
          * of bits read back. */
-
         while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
         {
             ulImplementedPrioBits++;
@@ -1674,16 +1717,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          * register. */
         ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
         ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
-        /* Restore the clobbered interrupt priority register to its original
-         * value. */
-        portNVIC_SHPR2_REG = ulOriginalPriority;
     }
     #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
-    /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+    /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
+     * the highest priority. */
     portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+    portNVIC_SHPR2_REG = 0;
 
     #if ( configENABLE_MPU == 1 )
     {
diff --git a/portable/IAR/ARM_CM0/port.c b/portable/IAR/ARM_CM0/port.c
index f4d77120c..1b9caa13a 100644
--- a/portable/IAR/ARM_CM0/port.c
+++ b/portable/IAR/ARM_CM0/port.c
@@ -37,6 +37,9 @@
 #include "FreeRTOS.h"
 #include "task.h"
 
+/* Prototype of all Interrupt Service Routines (ISRs). */
+typedef void ( * portISR_t )( void );
+
 /* Constants required to manipulate the NVIC. */
 #define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )
 #define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )
@@ -53,6 +56,10 @@
 #define portNVIC_PENDSV_PRI                   ( portMIN_INTERRUPT_PRIORITY << 16UL )
 #define portNVIC_SYSTICK_PRI                  ( portMIN_INTERRUPT_PRIORITY << 24UL )
 
+/* Constants used to check the installation of the FreeRTOS interrupt handlers. */
+#define portSCB_VTOR_REG                      ( *( ( portISR_t ** ) 0xe000ed08 ) )
+#define portVECTOR_INDEX_PENDSV               ( 14 )
+
 /* Constants required to set up the initial stack. */
 #define portINITIAL_XPSR                      ( 0x01000000 )
 
@@ -121,6 +128,10 @@ extern void vPortStartFirstTask( void );
  */
 static void prvTaskExitError( void );
 
+/*
+ * FreeRTOS handlers implemented in assembly.
+ */
+extern void xPortPendSVHandler( void );
 /*-----------------------------------------------------------*/
 
 /*
@@ -168,6 +179,41 @@ static void prvTaskExitError( void )
  */
 BaseType_t xPortStartScheduler( void )
 {
+    /* An application can install FreeRTOS interrupt handlers in one of the
+     * folllowing ways:
+     * 1. Direct Routing - Install the function xPortPendSVHandler for PendSV
+     *    interrupt.
+     * 2. Indirect Routing - Install separate handler for PendSV interrupt and
+     *    route program control from that handler to xPortPendSVHandler function.
+     *
+     * Applications that use Indirect Routing must set
+     * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+     * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+     * is 1, should be preferred when possible. */
+    #if ( configCHECK_HANDLER_INSTALLATION == 1 )
+    {
+        /* Point pxVectorTable to the interrupt vector table. Systems without
+         * a VTOR register provide the value zero in the VTOR register and
+         * the vector table itself is located at the address 0x00000000. */
+        const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+        /* Validate that the application has correctly installed the FreeRTOS
+         * handler for PendSV interrupt. We do not check the installation of the
+         * SysTick handler because the application may choose to drive the RTOS
+         * tick using a timer other than the SysTick timer by overriding the
+         * weak function vPortSetupTimerInterrupt().
+         *
+         * Assertion failures here indicate incorrect installation of the
+         * FreeRTOS handler. For help installing the FreeRTOS handler, see
+         * https://www.FreeRTOS.org/FAQHelp.html.
+         *
+         * Systems with a configurable address for the interrupt vector table
+         * can also encounter assertion failures or even system faults here if
+         * VTOR is not set correctly to point to the application's vector table. */
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == xPortPendSVHandler );
+    }
+    #endif /* configCHECK_HANDLER_INSTALLATION */
+
     /* Make PendSV and SysTick the lowest priority interrupts. */
     portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
diff --git a/portable/IAR/ARM_CM0/portasm.s b/portable/IAR/ARM_CM0/portasm.s
index 768ce41cb..ede492135 100644
--- a/portable/IAR/ARM_CM0/portasm.s
+++ b/portable/IAR/ARM_CM0/portasm.s
@@ -91,15 +91,15 @@ xPortPendSVHandler:
 
 vPortSVCHandler;
     /* This function is no longer used, but retained for backward
-    compatibility. */
+     * compatibility. */
     bx lr
 
 /*-----------------------------------------------------------*/
 
 vPortStartFirstTask
-    /* The MSP stack is not reset as, unlike on M3/4 parts, there is no vector
-    table offset register that can be used to locate the initial stack value.
-    Not all M0 parts have the application vector table at address 0. */
+    /* Don't reset the MSP stack as is done on CM3/4 devices. The vector table
+     * in some CM0 devices cannot be modified and thus may not hold the
+     * application's initial MSP value. */
 
     ldr r3, =pxCurrentTCB   /* Obtain location of pxCurrentTCB. */
     ldr r1, [r3]
diff --git a/portable/IAR/ARM_CM23/non_secure/port.c b/portable/IAR/ARM_CM23/non_secure/port.c
index 6a3877894..a5ed7004a 100644
--- a/portable/IAR/ARM_CM23/non_secure/port.c
+++ b/portable/IAR/ARM_CM23/non_secure/port.c
@@ -80,6 +80,12 @@
 #endif
 /*-----------------------------------------------------------*/
 
+/**
+ * @brief Prototype of all Interrupt Service Routines (ISRs).
+ */
+typedef void ( * portISR_t )( void );
+/*-----------------------------------------------------------*/
+
 /**
  * @brief Constants required to manipulate the NVIC.
  */
@@ -101,10 +107,18 @@
 /**
  * @brief Constants required to manipulate the SCB.
  */
-#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_VTOR_REG                      ( *( ( portISR_t ** ) 0xe000ed08 ) )
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
 #define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )
 /*-----------------------------------------------------------*/
 
+/**
+ * @brief Constants used to check the installation of the FreeRTOS interrupt handlers.
+ */
+#define portVECTOR_INDEX_SVC       ( 11 )
+#define portVECTOR_INDEX_PENDSV    ( 14 )
+/*-----------------------------------------------------------*/
+
 /**
  * @brief Constants required to check the validity of an interrupt priority.
  */
@@ -1598,22 +1612,52 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
+    /* An application can install FreeRTOS interrupt handlers in one of the
+     * folllowing ways:
+     * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
+     *    for SVCall and PendSV interrupts respectively.
+     * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+     *    interrupts and route program control from those handlers to
+     *    SVC_Handler and PendSV_Handler functions.
+     *
+     * Applications that use Indirect Routing must set
+     * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+     * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+     * is 1, should be preferred when possible. */
+    #if ( configCHECK_HANDLER_INSTALLATION == 1 )
+    {
+        const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+        /* Validate that the application has correctly installed the FreeRTOS
+         * handlers for SVCall and PendSV interrupts. We do not check the
+         * installation of the SysTick handler because the application may
+         * choose to drive the RTOS tick using a timer other than the SysTick
+         * timer by overriding the weak function vPortSetupTimerInterrupt().
+         *
+         * Assertion failures here indicate incorrect installation of the
+         * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+         * https://www.FreeRTOS.org/FAQHelp.html.
+         *
+         * Systems with a configurable address for the interrupt vector table
+         * can also encounter assertion failures or even system faults here if
+         * VTOR is not set correctly to point to the application's vector table. */
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler );
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler );
+    }
+    #endif /* configCHECK_HANDLER_INSTALLATION */
+
     #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
     {
-        volatile uint32_t ulOriginalPriority;
         volatile uint32_t ulImplementedPrioBits = 0;
         volatile uint8_t ucMaxPriorityValue;
 
         /* Determine the maximum priority from which ISR safe FreeRTOS API
-         * functions can be called.  ISR safe functions are those that end in
-         * "FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+         * functions can be called. ISR safe functions are those that end in
+         * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
          * ensure interrupt entry is as fast and simple as possible.
          *
-         * Save the interrupt priority value that is about to be clobbered. */
-        ulOriginalPriority = portNVIC_SHPR2_REG;
-
-        /* Determine the number of priority bits available.  First write to all
-         * possible bits. */
+         * First, determine the number of priority bits available. Write to all
+         * possible bits in the priority setting for SVCall. */
         portNVIC_SHPR2_REG = 0xFF000000;
 
         /* Read the value back to see how many bits stuck. */
@@ -1636,7 +1680,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         /* Calculate the maximum acceptable priority group value for the number
          * of bits read back. */
-
         while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
         {
             ulImplementedPrioBits++;
@@ -1674,16 +1717,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          * register. */
         ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
         ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
-        /* Restore the clobbered interrupt priority register to its original
-         * value. */
-        portNVIC_SHPR2_REG = ulOriginalPriority;
     }
     #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
-    /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+    /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
+     * the highest priority. */
     portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+    portNVIC_SHPR2_REG = 0;
 
     #if ( configENABLE_MPU == 1 )
     {
diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
index 6a3877894..a5ed7004a 100644
--- a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
@@ -80,6 +80,12 @@
 #endif
 /*-----------------------------------------------------------*/
 
+/**
+ * @brief Prototype of all Interrupt Service Routines (ISRs).
+ */
+typedef void ( * portISR_t )( void );
+/*-----------------------------------------------------------*/
+
 /**
  * @brief Constants required to manipulate the NVIC.
  */
@@ -101,10 +107,18 @@
 /**
  * @brief Constants required to manipulate the SCB.
  */
-#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_VTOR_REG                      ( *( ( portISR_t ** ) 0xe000ed08 ) )
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
 #define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )
 /*-----------------------------------------------------------*/
 
+/**
+ * @brief Constants used to check the installation of the FreeRTOS interrupt handlers.
+ */
+#define portVECTOR_INDEX_SVC       ( 11 )
+#define portVECTOR_INDEX_PENDSV    ( 14 )
+/*-----------------------------------------------------------*/
+
 /**
  * @brief Constants required to check the validity of an interrupt priority.
  */
@@ -1598,22 +1612,52 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
+    /* An application can install FreeRTOS interrupt handlers in one of the
+     * folllowing ways:
+     * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
+     *    for SVCall and PendSV interrupts respectively.
+     * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+     *    interrupts and route program control from those handlers to
+     *    SVC_Handler and PendSV_Handler functions.
+     *
+     * Applications that use Indirect Routing must set
+     * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+     * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+     * is 1, should be preferred when possible. */
+    #if ( configCHECK_HANDLER_INSTALLATION == 1 )
+    {
+        const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+        /* Validate that the application has correctly installed the FreeRTOS
+         * handlers for SVCall and PendSV interrupts. We do not check the
+         * installation of the SysTick handler because the application may
+         * choose to drive the RTOS tick using a timer other than the SysTick
+         * timer by overriding the weak function vPortSetupTimerInterrupt().
+         *
+         * Assertion failures here indicate incorrect installation of the
+         * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+         * https://www.FreeRTOS.org/FAQHelp.html.
+         *
+         * Systems with a configurable address for the interrupt vector table
+         * can also encounter assertion failures or even system faults here if
+         * VTOR is not set correctly to point to the application's vector table. */
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler );
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler );
+    }
+    #endif /* configCHECK_HANDLER_INSTALLATION */
+
     #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
     {
-        volatile uint32_t ulOriginalPriority;
         volatile uint32_t ulImplementedPrioBits = 0;
         volatile uint8_t ucMaxPriorityValue;
 
         /* Determine the maximum priority from which ISR safe FreeRTOS API
-         * functions can be called.  ISR safe functions are those that end in
-         * "FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+         * functions can be called. ISR safe functions are those that end in
+         * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
          * ensure interrupt entry is as fast and simple as possible.
          *
-         * Save the interrupt priority value that is about to be clobbered. */
-        ulOriginalPriority = portNVIC_SHPR2_REG;
-
-        /* Determine the number of priority bits available.  First write to all
-         * possible bits. */
+         * First, determine the number of priority bits available. Write to all
+         * possible bits in the priority setting for SVCall. */
         portNVIC_SHPR2_REG = 0xFF000000;
 
         /* Read the value back to see how many bits stuck. */
@@ -1636,7 +1680,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         /* Calculate the maximum acceptable priority group value for the number
          * of bits read back. */
-
         while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
         {
             ulImplementedPrioBits++;
@@ -1674,16 +1717,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          * register. */
         ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
         ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
-        /* Restore the clobbered interrupt priority register to its original
-         * value. */
-        portNVIC_SHPR2_REG = ulOriginalPriority;
     }
     #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
-    /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+    /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
+     * the highest priority. */
     portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+    portNVIC_SHPR2_REG = 0;
 
     #if ( configENABLE_MPU == 1 )
     {
diff --git a/portable/IAR/ARM_CM3/port.c b/portable/IAR/ARM_CM3/port.c
index 1fbe96d44..460826872 100644
--- a/portable/IAR/ARM_CM3/port.c
+++ b/portable/IAR/ARM_CM3/port.c
@@ -41,10 +41,14 @@
     #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
 #endif
 
+/* Prototype of all Interrupt Service Routines (ISRs). */
+typedef void ( * portISR_t )( void );
+
 /* Constants required to manipulate the core.  Registers first... */
 #define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )
 #define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )
 #define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SHPR2_REG                    ( *( ( volatile uint32_t * ) 0xe000ed1c ) )
 #define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
 /* ...then bits in the registers. */
 #define portNVIC_SYSTICK_CLK_BIT              ( 1UL << 2UL )
@@ -59,6 +63,11 @@
 #define portNVIC_PENDSV_PRI                   ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
 #define portNVIC_SYSTICK_PRI                  ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
 
+/* Constants used to check the installation of the FreeRTOS interrupt handlers. */
+#define portSCB_VTOR_REG                      ( *( ( portISR_t ** ) 0xE000ED08 ) )
+#define portVECTOR_INDEX_SVC                  ( 11 )
+#define portVECTOR_INDEX_PENDSV               ( 14 )
+
 /* Constants required to check the validity of an interrupt priority. */
 #define portFIRST_USER_INTERRUPT_NUMBER       ( 16 )
 #define portNVIC_IP_REGISTERS_OFFSET_16       ( 0xE000E3F0 )
@@ -121,6 +130,11 @@ extern void vPortStartFirstTask( void );
  */
 static void prvTaskExitError( void );
 
+/*
+ * FreeRTOS handlers implemented in assembly.
+ */
+extern void vPortSVCHandler( void );
+extern void xPortPendSVHandler( void );
 /*-----------------------------------------------------------*/
 
 /* Each task maintains its own interrupt status in the critical nesting
@@ -208,6 +222,40 @@ static void prvTaskExitError( void )
  */
 BaseType_t xPortStartScheduler( void )
 {
+    /* An application can install FreeRTOS interrupt handlers in one of the
+     * folllowing ways:
+     * 1. Direct Routing - Install the functions vPortSVCHandler and
+     *    xPortPendSVHandler for SVCall and PendSV interrupts respectively.
+     * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+     *    interrupts and route program control from those handlers to
+     *    vPortSVCHandler and xPortPendSVHandler functions.
+     *
+     * Applications that use Indirect Routing must set
+     * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+     * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+     * is 1, should be preferred when possible. */
+    #if ( configCHECK_HANDLER_INSTALLATION == 1 )
+    {
+        const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+        /* Validate that the application has correctly installed the FreeRTOS
+         * handlers for SVCall and PendSV interrupts. We do not check the
+         * installation of the SysTick handler because the application may
+         * choose to drive the RTOS tick using a timer other than the SysTick
+         * timer by overriding the weak function vPortSetupTimerInterrupt().
+         *
+         * Assertion failures here indicate incorrect installation of the
+         * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+         * https://www.FreeRTOS.org/FAQHelp.html.
+         *
+         * Systems with a configurable address for the interrupt vector table
+         * can also encounter assertion failures or even system faults here if
+         * VTOR is not set correctly to point to the application's vector table. */
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == vPortSVCHandler );
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == xPortPendSVHandler );
+    }
+    #endif /* configCHECK_HANDLER_INSTALLATION */
+
     #if ( configASSERT_DEFINED == 1 )
     {
         volatile uint8_t ucOriginalPriority;
@@ -292,9 +340,11 @@ BaseType_t xPortStartScheduler( void )
     }
     #endif /* configASSERT_DEFINED */
 
-    /* Make PendSV and SysTick the lowest priority interrupts. */
+    /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
+     * the highest priority. */
     portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+    portNVIC_SHPR2_REG = 0;
 
     /* Start the timer that generates the tick ISR.  Interrupts are disabled
      * here already. */
diff --git a/portable/IAR/ARM_CM33/non_secure/port.c b/portable/IAR/ARM_CM33/non_secure/port.c
index 6a3877894..a5ed7004a 100644
--- a/portable/IAR/ARM_CM33/non_secure/port.c
+++ b/portable/IAR/ARM_CM33/non_secure/port.c
@@ -80,6 +80,12 @@
 #endif
 /*-----------------------------------------------------------*/
 
+/**
+ * @brief Prototype of all Interrupt Service Routines (ISRs).
+ */
+typedef void ( * portISR_t )( void );
+/*-----------------------------------------------------------*/
+
 /**
  * @brief Constants required to manipulate the NVIC.
  */
@@ -101,10 +107,18 @@
 /**
  * @brief Constants required to manipulate the SCB.
  */
-#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_VTOR_REG                      ( *( ( portISR_t ** ) 0xe000ed08 ) )
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
 #define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )
 /*-----------------------------------------------------------*/
 
+/**
+ * @brief Constants used to check the installation of the FreeRTOS interrupt handlers.
+ */
+#define portVECTOR_INDEX_SVC       ( 11 )
+#define portVECTOR_INDEX_PENDSV    ( 14 )
+/*-----------------------------------------------------------*/
+
 /**
  * @brief Constants required to check the validity of an interrupt priority.
  */
@@ -1598,22 +1612,52 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
+    /* An application can install FreeRTOS interrupt handlers in one of the
+     * folllowing ways:
+     * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
+     *    for SVCall and PendSV interrupts respectively.
+     * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+     *    interrupts and route program control from those handlers to
+     *    SVC_Handler and PendSV_Handler functions.
+     *
+     * Applications that use Indirect Routing must set
+     * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+     * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+     * is 1, should be preferred when possible. */
+    #if ( configCHECK_HANDLER_INSTALLATION == 1 )
+    {
+        const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+        /* Validate that the application has correctly installed the FreeRTOS
+         * handlers for SVCall and PendSV interrupts. We do not check the
+         * installation of the SysTick handler because the application may
+         * choose to drive the RTOS tick using a timer other than the SysTick
+         * timer by overriding the weak function vPortSetupTimerInterrupt().
+         *
+         * Assertion failures here indicate incorrect installation of the
+         * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+         * https://www.FreeRTOS.org/FAQHelp.html.
+         *
+         * Systems with a configurable address for the interrupt vector table
+         * can also encounter assertion failures or even system faults here if
+         * VTOR is not set correctly to point to the application's vector table. */
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler );
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler );
+    }
+    #endif /* configCHECK_HANDLER_INSTALLATION */
+
     #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
     {
-        volatile uint32_t ulOriginalPriority;
         volatile uint32_t ulImplementedPrioBits = 0;
         volatile uint8_t ucMaxPriorityValue;
 
         /* Determine the maximum priority from which ISR safe FreeRTOS API
-         * functions can be called.  ISR safe functions are those that end in
-         * "FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+         * functions can be called. ISR safe functions are those that end in
+         * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
          * ensure interrupt entry is as fast and simple as possible.
          *
-         * Save the interrupt priority value that is about to be clobbered. */
-        ulOriginalPriority = portNVIC_SHPR2_REG;
-
-        /* Determine the number of priority bits available.  First write to all
-         * possible bits. */
+         * First, determine the number of priority bits available. Write to all
+         * possible bits in the priority setting for SVCall. */
         portNVIC_SHPR2_REG = 0xFF000000;
 
         /* Read the value back to see how many bits stuck. */
@@ -1636,7 +1680,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         /* Calculate the maximum acceptable priority group value for the number
          * of bits read back. */
-
         while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
         {
             ulImplementedPrioBits++;
@@ -1674,16 +1717,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          * register. */
         ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
         ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
-        /* Restore the clobbered interrupt priority register to its original
-         * value. */
-        portNVIC_SHPR2_REG = ulOriginalPriority;
     }
     #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
-    /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+    /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
+     * the highest priority. */
     portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+    portNVIC_SHPR2_REG = 0;
 
     #if ( configENABLE_MPU == 1 )
     {
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
index 6a3877894..a5ed7004a 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
@@ -80,6 +80,12 @@
 #endif
 /*-----------------------------------------------------------*/
 
+/**
+ * @brief Prototype of all Interrupt Service Routines (ISRs).
+ */
+typedef void ( * portISR_t )( void );
+/*-----------------------------------------------------------*/
+
 /**
  * @brief Constants required to manipulate the NVIC.
  */
@@ -101,10 +107,18 @@
 /**
  * @brief Constants required to manipulate the SCB.
  */
-#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_VTOR_REG                      ( *( ( portISR_t ** ) 0xe000ed08 ) )
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
 #define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )
 /*-----------------------------------------------------------*/
 
+/**
+ * @brief Constants used to check the installation of the FreeRTOS interrupt handlers.
+ */
+#define portVECTOR_INDEX_SVC       ( 11 )
+#define portVECTOR_INDEX_PENDSV    ( 14 )
+/*-----------------------------------------------------------*/
+
 /**
  * @brief Constants required to check the validity of an interrupt priority.
  */
@@ -1598,22 +1612,52 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
+    /* An application can install FreeRTOS interrupt handlers in one of the
+     * folllowing ways:
+     * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
+     *    for SVCall and PendSV interrupts respectively.
+     * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+     *    interrupts and route program control from those handlers to
+     *    SVC_Handler and PendSV_Handler functions.
+     *
+     * Applications that use Indirect Routing must set
+     * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+     * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+     * is 1, should be preferred when possible. */
+    #if ( configCHECK_HANDLER_INSTALLATION == 1 )
+    {
+        const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+        /* Validate that the application has correctly installed the FreeRTOS
+         * handlers for SVCall and PendSV interrupts. We do not check the
+         * installation of the SysTick handler because the application may
+         * choose to drive the RTOS tick using a timer other than the SysTick
+         * timer by overriding the weak function vPortSetupTimerInterrupt().
+         *
+         * Assertion failures here indicate incorrect installation of the
+         * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+         * https://www.FreeRTOS.org/FAQHelp.html.
+         *
+         * Systems with a configurable address for the interrupt vector table
+         * can also encounter assertion failures or even system faults here if
+         * VTOR is not set correctly to point to the application's vector table. */
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler );
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler );
+    }
+    #endif /* configCHECK_HANDLER_INSTALLATION */
+
     #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
     {
-        volatile uint32_t ulOriginalPriority;
         volatile uint32_t ulImplementedPrioBits = 0;
         volatile uint8_t ucMaxPriorityValue;
 
         /* Determine the maximum priority from which ISR safe FreeRTOS API
-         * functions can be called.  ISR safe functions are those that end in
-         * "FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+         * functions can be called. ISR safe functions are those that end in
+         * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
          * ensure interrupt entry is as fast and simple as possible.
          *
-         * Save the interrupt priority value that is about to be clobbered. */
-        ulOriginalPriority = portNVIC_SHPR2_REG;
-
-        /* Determine the number of priority bits available.  First write to all
-         * possible bits. */
+         * First, determine the number of priority bits available. Write to all
+         * possible bits in the priority setting for SVCall. */
         portNVIC_SHPR2_REG = 0xFF000000;
 
         /* Read the value back to see how many bits stuck. */
@@ -1636,7 +1680,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         /* Calculate the maximum acceptable priority group value for the number
          * of bits read back. */
-
         while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
         {
             ulImplementedPrioBits++;
@@ -1674,16 +1717,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          * register. */
         ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
         ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
-        /* Restore the clobbered interrupt priority register to its original
-         * value. */
-        portNVIC_SHPR2_REG = ulOriginalPriority;
     }
     #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
-    /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+    /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
+     * the highest priority. */
     portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+    portNVIC_SHPR2_REG = 0;
 
     #if ( configENABLE_MPU == 1 )
     {
diff --git a/portable/IAR/ARM_CM35P/non_secure/port.c b/portable/IAR/ARM_CM35P/non_secure/port.c
index 6a3877894..a5ed7004a 100644
--- a/portable/IAR/ARM_CM35P/non_secure/port.c
+++ b/portable/IAR/ARM_CM35P/non_secure/port.c
@@ -80,6 +80,12 @@
 #endif
 /*-----------------------------------------------------------*/
 
+/**
+ * @brief Prototype of all Interrupt Service Routines (ISRs).
+ */
+typedef void ( * portISR_t )( void );
+/*-----------------------------------------------------------*/
+
 /**
  * @brief Constants required to manipulate the NVIC.
  */
@@ -101,10 +107,18 @@
 /**
  * @brief Constants required to manipulate the SCB.
  */
-#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_VTOR_REG                      ( *( ( portISR_t ** ) 0xe000ed08 ) )
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
 #define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )
 /*-----------------------------------------------------------*/
 
+/**
+ * @brief Constants used to check the installation of the FreeRTOS interrupt handlers.
+ */
+#define portVECTOR_INDEX_SVC       ( 11 )
+#define portVECTOR_INDEX_PENDSV    ( 14 )
+/*-----------------------------------------------------------*/
+
 /**
  * @brief Constants required to check the validity of an interrupt priority.
  */
@@ -1598,22 +1612,52 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
+    /* An application can install FreeRTOS interrupt handlers in one of the
+     * folllowing ways:
+     * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
+     *    for SVCall and PendSV interrupts respectively.
+     * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+     *    interrupts and route program control from those handlers to
+     *    SVC_Handler and PendSV_Handler functions.
+     *
+     * Applications that use Indirect Routing must set
+     * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+     * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+     * is 1, should be preferred when possible. */
+    #if ( configCHECK_HANDLER_INSTALLATION == 1 )
+    {
+        const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+        /* Validate that the application has correctly installed the FreeRTOS
+         * handlers for SVCall and PendSV interrupts. We do not check the
+         * installation of the SysTick handler because the application may
+         * choose to drive the RTOS tick using a timer other than the SysTick
+         * timer by overriding the weak function vPortSetupTimerInterrupt().
+         *
+         * Assertion failures here indicate incorrect installation of the
+         * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+         * https://www.FreeRTOS.org/FAQHelp.html.
+         *
+         * Systems with a configurable address for the interrupt vector table
+         * can also encounter assertion failures or even system faults here if
+         * VTOR is not set correctly to point to the application's vector table. */
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler );
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler );
+    }
+    #endif /* configCHECK_HANDLER_INSTALLATION */
+
     #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
     {
-        volatile uint32_t ulOriginalPriority;
         volatile uint32_t ulImplementedPrioBits = 0;
         volatile uint8_t ucMaxPriorityValue;
 
         /* Determine the maximum priority from which ISR safe FreeRTOS API
-         * functions can be called.  ISR safe functions are those that end in
-         * "FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+         * functions can be called. ISR safe functions are those that end in
+         * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
          * ensure interrupt entry is as fast and simple as possible.
          *
-         * Save the interrupt priority value that is about to be clobbered. */
-        ulOriginalPriority = portNVIC_SHPR2_REG;
-
-        /* Determine the number of priority bits available.  First write to all
-         * possible bits. */
+         * First, determine the number of priority bits available. Write to all
+         * possible bits in the priority setting for SVCall. */
         portNVIC_SHPR2_REG = 0xFF000000;
 
         /* Read the value back to see how many bits stuck. */
@@ -1636,7 +1680,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         /* Calculate the maximum acceptable priority group value for the number
          * of bits read back. */
-
         while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
         {
             ulImplementedPrioBits++;
@@ -1674,16 +1717,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          * register. */
         ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
         ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
-        /* Restore the clobbered interrupt priority register to its original
-         * value. */
-        portNVIC_SHPR2_REG = ulOriginalPriority;
     }
     #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
-    /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+    /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
+     * the highest priority. */
     portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+    portNVIC_SHPR2_REG = 0;
 
     #if ( configENABLE_MPU == 1 )
     {
diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c b/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
index 6a3877894..a5ed7004a 100644
--- a/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
@@ -80,6 +80,12 @@
 #endif
 /*-----------------------------------------------------------*/
 
+/**
+ * @brief Prototype of all Interrupt Service Routines (ISRs).
+ */
+typedef void ( * portISR_t )( void );
+/*-----------------------------------------------------------*/
+
 /**
  * @brief Constants required to manipulate the NVIC.
  */
@@ -101,10 +107,18 @@
 /**
  * @brief Constants required to manipulate the SCB.
  */
-#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_VTOR_REG                      ( *( ( portISR_t ** ) 0xe000ed08 ) )
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
 #define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )
 /*-----------------------------------------------------------*/
 
+/**
+ * @brief Constants used to check the installation of the FreeRTOS interrupt handlers.
+ */
+#define portVECTOR_INDEX_SVC       ( 11 )
+#define portVECTOR_INDEX_PENDSV    ( 14 )
+/*-----------------------------------------------------------*/
+
 /**
  * @brief Constants required to check the validity of an interrupt priority.
  */
@@ -1598,22 +1612,52 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
+    /* An application can install FreeRTOS interrupt handlers in one of the
+     * folllowing ways:
+     * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
+     *    for SVCall and PendSV interrupts respectively.
+     * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+     *    interrupts and route program control from those handlers to
+     *    SVC_Handler and PendSV_Handler functions.
+     *
+     * Applications that use Indirect Routing must set
+     * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+     * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+     * is 1, should be preferred when possible. */
+    #if ( configCHECK_HANDLER_INSTALLATION == 1 )
+    {
+        const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+        /* Validate that the application has correctly installed the FreeRTOS
+         * handlers for SVCall and PendSV interrupts. We do not check the
+         * installation of the SysTick handler because the application may
+         * choose to drive the RTOS tick using a timer other than the SysTick
+         * timer by overriding the weak function vPortSetupTimerInterrupt().
+         *
+         * Assertion failures here indicate incorrect installation of the
+         * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+         * https://www.FreeRTOS.org/FAQHelp.html.
+         *
+         * Systems with a configurable address for the interrupt vector table
+         * can also encounter assertion failures or even system faults here if
+         * VTOR is not set correctly to point to the application's vector table. */
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler );
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler );
+    }
+    #endif /* configCHECK_HANDLER_INSTALLATION */
+
     #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
     {
-        volatile uint32_t ulOriginalPriority;
         volatile uint32_t ulImplementedPrioBits = 0;
         volatile uint8_t ucMaxPriorityValue;
 
         /* Determine the maximum priority from which ISR safe FreeRTOS API
-         * functions can be called.  ISR safe functions are those that end in
-         * "FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+         * functions can be called. ISR safe functions are those that end in
+         * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
          * ensure interrupt entry is as fast and simple as possible.
          *
-         * Save the interrupt priority value that is about to be clobbered. */
-        ulOriginalPriority = portNVIC_SHPR2_REG;
-
-        /* Determine the number of priority bits available.  First write to all
-         * possible bits. */
+         * First, determine the number of priority bits available. Write to all
+         * possible bits in the priority setting for SVCall. */
         portNVIC_SHPR2_REG = 0xFF000000;
 
         /* Read the value back to see how many bits stuck. */
@@ -1636,7 +1680,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         /* Calculate the maximum acceptable priority group value for the number
          * of bits read back. */
-
         while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
         {
             ulImplementedPrioBits++;
@@ -1674,16 +1717,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          * register. */
         ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
         ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
-        /* Restore the clobbered interrupt priority register to its original
-         * value. */
-        portNVIC_SHPR2_REG = ulOriginalPriority;
     }
     #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
-    /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+    /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
+     * the highest priority. */
     portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+    portNVIC_SHPR2_REG = 0;
 
     #if ( configENABLE_MPU == 1 )
     {
diff --git a/portable/IAR/ARM_CM4F/port.c b/portable/IAR/ARM_CM4F/port.c
index effedcb14..763ff2a5c 100644
--- a/portable/IAR/ARM_CM4F/port.c
+++ b/portable/IAR/ARM_CM4F/port.c
@@ -45,10 +45,14 @@
     #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
 #endif
 
+/* Prototype of all Interrupt Service Routines (ISRs). */
+typedef void ( * portISR_t )( void );
+
 /* Constants required to manipulate the core.  Registers first... */
 #define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )
 #define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )
 #define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SHPR2_REG                    ( *( ( volatile uint32_t * ) 0xe000ed1c ) )
 #define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
 /* ...then bits in the registers. */
 #define portNVIC_SYSTICK_CLK_BIT              ( 1UL << 2UL )
@@ -69,6 +73,11 @@
 #define portNVIC_PENDSV_PRI                   ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
 #define portNVIC_SYSTICK_PRI                  ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
 
+/* Constants used to check the installation of the FreeRTOS interrupt handlers. */
+#define portSCB_VTOR_REG                      ( *( ( portISR_t ** ) 0xE000ED08 ) )
+#define portVECTOR_INDEX_SVC                  ( 11 )
+#define portVECTOR_INDEX_PENDSV               ( 14 )
+
 /* Constants required to check the validity of an interrupt priority. */
 #define portFIRST_USER_INTERRUPT_NUMBER       ( 16 )
 #define portNVIC_IP_REGISTERS_OFFSET_16       ( 0xE000E3F0 )
@@ -141,6 +150,11 @@ extern void vPortEnableVFP( void );
  */
 static void prvTaskExitError( void );
 
+/*
+ * FreeRTOS handlers implemented in assembly.
+ */
+extern void vPortSVCHandler( void );
+extern void xPortPendSVHandler( void );
 /*-----------------------------------------------------------*/
 
 /* Each task maintains its own interrupt status in the critical nesting
@@ -246,6 +260,40 @@ BaseType_t xPortStartScheduler( void )
     configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
     configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
 
+    /* An application can install FreeRTOS interrupt handlers in one of the
+     * folllowing ways:
+     * 1. Direct Routing - Install the functions vPortSVCHandler and
+     *    xPortPendSVHandler for SVCall and PendSV interrupts respectively.
+     * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+     *    interrupts and route program control from those handlers to
+     *    vPortSVCHandler and xPortPendSVHandler functions.
+     *
+     * Applications that use Indirect Routing must set
+     * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+     * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+     * is 1, should be preferred when possible. */
+    #if ( configCHECK_HANDLER_INSTALLATION == 1 )
+    {
+        const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+        /* Validate that the application has correctly installed the FreeRTOS
+         * handlers for SVCall and PendSV interrupts. We do not check the
+         * installation of the SysTick handler because the application may
+         * choose to drive the RTOS tick using a timer other than the SysTick
+         * timer by overriding the weak function vPortSetupTimerInterrupt().
+         *
+         * Assertion failures here indicate incorrect installation of the
+         * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+         * https://www.FreeRTOS.org/FAQHelp.html.
+         *
+         * Systems with a configurable address for the interrupt vector table
+         * can also encounter assertion failures or even system faults here if
+         * VTOR is not set correctly to point to the application's vector table. */
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == vPortSVCHandler );
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == xPortPendSVHandler );
+    }
+    #endif /* configCHECK_HANDLER_INSTALLATION */
+
     #if ( configASSERT_DEFINED == 1 )
     {
         volatile uint8_t ucOriginalPriority;
@@ -330,9 +378,11 @@ BaseType_t xPortStartScheduler( void )
     }
     #endif /* configASSERT_DEFINED */
 
-    /* Make PendSV and SysTick the lowest priority interrupts. */
+    /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
+     * the highest priority. */
     portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+    portNVIC_SHPR2_REG = 0;
 
     /* Start the timer that generates the tick ISR.  Interrupts are disabled
      * here already. */
diff --git a/portable/IAR/ARM_CM4F_MPU/port.c b/portable/IAR/ARM_CM4F_MPU/port.c
index 4f0b617ce..c3bab2671 100644
--- a/portable/IAR/ARM_CM4F_MPU/port.c
+++ b/portable/IAR/ARM_CM4F_MPU/port.c
@@ -69,6 +69,9 @@
     #define configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS    1
 #endif
 
+/* Prototype of all Interrupt Service Routines (ISRs). */
+typedef void ( * portISR_t )( void );
+
 /* Constants required to manipulate the core.  Registers first... */
 #define portNVIC_SYSTICK_CTRL_REG                 ( *( ( volatile uint32_t * ) 0xe000e010 ) )
 #define portNVIC_SYSTICK_LOAD_REG                 ( *( ( volatile uint32_t * ) 0xe000e014 ) )
@@ -108,7 +111,11 @@
 #define portMIN_INTERRUPT_PRIORITY                ( 255UL )
 #define portNVIC_PENDSV_PRI                       ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
 #define portNVIC_SYSTICK_PRI                      ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
-#define portNVIC_SVC_PRI                          ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )
+
+/* Constants used to check the installation of the FreeRTOS interrupt handlers. */
+#define portSCB_VTOR_REG                          ( *( ( portISR_t ** ) 0xE000ED08 ) )
+#define portVECTOR_INDEX_SVC                      ( 11 )
+#define portVECTOR_INDEX_PENDSV                   ( 14 )
 
 /* Constants required to check the validity of an interrupt priority. */
 #define portFIRST_USER_INTERRUPT_NUMBER           ( 16 )
@@ -282,6 +289,11 @@ BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
  */
 void vPortSwitchToUserMode( void );
 
+/*
+ * FreeRTOS handlers implemented in assembly.
+ */
+extern void vPortSVCHandler( void ) PRIVILEGED_FUNCTION;
+extern void xPortPendSVHandler( void ) PRIVILEGED_FUNCTION;
 /*-----------------------------------------------------------*/
 
 /* Each task maintains its own interrupt status in the critical nesting
@@ -384,7 +396,6 @@ void vPortSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
     switch( ucSVCNumber )
     {
         case portSVC_START_SCHEDULER:
-            portNVIC_SHPR2_REG |= portNVIC_SVC_PRI;
             vPortRestoreContextOfFirstTask();
             break;
 
@@ -713,6 +724,40 @@ BaseType_t xPortStartScheduler( void )
         configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
     #endif
 
+    /* An application can install FreeRTOS interrupt handlers in one of the
+     * folllowing ways:
+     * 1. Direct Routing - Install the functions vPortSVCHandler and
+     *    xPortPendSVHandler for SVCall and PendSV interrupts respectively.
+     * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+     *    interrupts and route program control from those handlers to
+     *    vPortSVCHandler and xPortPendSVHandler functions.
+     *
+     * Applications that use Indirect Routing must set
+     * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+     * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+     * is 1, should be preferred when possible. */
+    #if ( configCHECK_HANDLER_INSTALLATION == 1 )
+    {
+        const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+        /* Validate that the application has correctly installed the FreeRTOS
+         * handlers for SVCall and PendSV interrupts. We do not check the
+         * installation of the SysTick handler because the application may
+         * choose to drive the RTOS tick using a timer other than the SysTick
+         * timer by overriding the weak function vPortSetupTimerInterrupt().
+         *
+         * Assertion failures here indicate incorrect installation of the
+         * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+         * https://www.FreeRTOS.org/FAQHelp.html.
+         *
+         * Systems with a configurable address for the interrupt vector table
+         * can also encounter assertion failures or even system faults here if
+         * VTOR is not set correctly to point to the application's vector table. */
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == vPortSVCHandler );
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == xPortPendSVHandler );
+    }
+    #endif /* configCHECK_HANDLER_INSTALLATION */
+
     #if ( configASSERT_DEFINED == 1 )
     {
         volatile uint8_t ucOriginalPriority;
@@ -797,9 +842,11 @@ BaseType_t xPortStartScheduler( void )
     }
     #endif /* configASSERT_DEFINED */
 
-    /* Make PendSV and SysTick the lowest priority interrupts. */
+    /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
+     * the highest priority. */
     portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+    portNVIC_SHPR2_REG = 0;
 
     /* Configure the regions in the MPU that are common to all tasks. */
     prvSetupMPU();
diff --git a/portable/IAR/ARM_CM55/non_secure/port.c b/portable/IAR/ARM_CM55/non_secure/port.c
index 6a3877894..a5ed7004a 100644
--- a/portable/IAR/ARM_CM55/non_secure/port.c
+++ b/portable/IAR/ARM_CM55/non_secure/port.c
@@ -80,6 +80,12 @@
 #endif
 /*-----------------------------------------------------------*/
 
+/**
+ * @brief Prototype of all Interrupt Service Routines (ISRs).
+ */
+typedef void ( * portISR_t )( void );
+/*-----------------------------------------------------------*/
+
 /**
  * @brief Constants required to manipulate the NVIC.
  */
@@ -101,10 +107,18 @@
 /**
  * @brief Constants required to manipulate the SCB.
  */
-#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_VTOR_REG                      ( *( ( portISR_t ** ) 0xe000ed08 ) )
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
 #define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )
 /*-----------------------------------------------------------*/
 
+/**
+ * @brief Constants used to check the installation of the FreeRTOS interrupt handlers.
+ */
+#define portVECTOR_INDEX_SVC       ( 11 )
+#define portVECTOR_INDEX_PENDSV    ( 14 )
+/*-----------------------------------------------------------*/
+
 /**
  * @brief Constants required to check the validity of an interrupt priority.
  */
@@ -1598,22 +1612,52 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
+    /* An application can install FreeRTOS interrupt handlers in one of the
+     * folllowing ways:
+     * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
+     *    for SVCall and PendSV interrupts respectively.
+     * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+     *    interrupts and route program control from those handlers to
+     *    SVC_Handler and PendSV_Handler functions.
+     *
+     * Applications that use Indirect Routing must set
+     * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+     * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+     * is 1, should be preferred when possible. */
+    #if ( configCHECK_HANDLER_INSTALLATION == 1 )
+    {
+        const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+        /* Validate that the application has correctly installed the FreeRTOS
+         * handlers for SVCall and PendSV interrupts. We do not check the
+         * installation of the SysTick handler because the application may
+         * choose to drive the RTOS tick using a timer other than the SysTick
+         * timer by overriding the weak function vPortSetupTimerInterrupt().
+         *
+         * Assertion failures here indicate incorrect installation of the
+         * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+         * https://www.FreeRTOS.org/FAQHelp.html.
+         *
+         * Systems with a configurable address for the interrupt vector table
+         * can also encounter assertion failures or even system faults here if
+         * VTOR is not set correctly to point to the application's vector table. */
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler );
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler );
+    }
+    #endif /* configCHECK_HANDLER_INSTALLATION */
+
     #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
     {
-        volatile uint32_t ulOriginalPriority;
         volatile uint32_t ulImplementedPrioBits = 0;
         volatile uint8_t ucMaxPriorityValue;
 
         /* Determine the maximum priority from which ISR safe FreeRTOS API
-         * functions can be called.  ISR safe functions are those that end in
-         * "FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+         * functions can be called. ISR safe functions are those that end in
+         * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
          * ensure interrupt entry is as fast and simple as possible.
          *
-         * Save the interrupt priority value that is about to be clobbered. */
-        ulOriginalPriority = portNVIC_SHPR2_REG;
-
-        /* Determine the number of priority bits available.  First write to all
-         * possible bits. */
+         * First, determine the number of priority bits available. Write to all
+         * possible bits in the priority setting for SVCall. */
         portNVIC_SHPR2_REG = 0xFF000000;
 
         /* Read the value back to see how many bits stuck. */
@@ -1636,7 +1680,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         /* Calculate the maximum acceptable priority group value for the number
          * of bits read back. */
-
         while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
         {
             ulImplementedPrioBits++;
@@ -1674,16 +1717,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          * register. */
         ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
         ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
-        /* Restore the clobbered interrupt priority register to its original
-         * value. */
-        portNVIC_SHPR2_REG = ulOriginalPriority;
     }
     #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
-    /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+    /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
+     * the highest priority. */
     portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+    portNVIC_SHPR2_REG = 0;
 
     #if ( configENABLE_MPU == 1 )
     {
diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/port.c b/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
index 6a3877894..a5ed7004a 100644
--- a/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
@@ -80,6 +80,12 @@
 #endif
 /*-----------------------------------------------------------*/
 
+/**
+ * @brief Prototype of all Interrupt Service Routines (ISRs).
+ */
+typedef void ( * portISR_t )( void );
+/*-----------------------------------------------------------*/
+
 /**
  * @brief Constants required to manipulate the NVIC.
  */
@@ -101,10 +107,18 @@
 /**
  * @brief Constants required to manipulate the SCB.
  */
-#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_VTOR_REG                      ( *( ( portISR_t ** ) 0xe000ed08 ) )
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
 #define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )
 /*-----------------------------------------------------------*/
 
+/**
+ * @brief Constants used to check the installation of the FreeRTOS interrupt handlers.
+ */
+#define portVECTOR_INDEX_SVC       ( 11 )
+#define portVECTOR_INDEX_PENDSV    ( 14 )
+/*-----------------------------------------------------------*/
+
 /**
  * @brief Constants required to check the validity of an interrupt priority.
  */
@@ -1598,22 +1612,52 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
+    /* An application can install FreeRTOS interrupt handlers in one of the
+     * folllowing ways:
+     * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
+     *    for SVCall and PendSV interrupts respectively.
+     * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+     *    interrupts and route program control from those handlers to
+     *    SVC_Handler and PendSV_Handler functions.
+     *
+     * Applications that use Indirect Routing must set
+     * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+     * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+     * is 1, should be preferred when possible. */
+    #if ( configCHECK_HANDLER_INSTALLATION == 1 )
+    {
+        const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+        /* Validate that the application has correctly installed the FreeRTOS
+         * handlers for SVCall and PendSV interrupts. We do not check the
+         * installation of the SysTick handler because the application may
+         * choose to drive the RTOS tick using a timer other than the SysTick
+         * timer by overriding the weak function vPortSetupTimerInterrupt().
+         *
+         * Assertion failures here indicate incorrect installation of the
+         * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+         * https://www.FreeRTOS.org/FAQHelp.html.
+         *
+         * Systems with a configurable address for the interrupt vector table
+         * can also encounter assertion failures or even system faults here if
+         * VTOR is not set correctly to point to the application's vector table. */
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler );
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler );
+    }
+    #endif /* configCHECK_HANDLER_INSTALLATION */
+
     #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
     {
-        volatile uint32_t ulOriginalPriority;
         volatile uint32_t ulImplementedPrioBits = 0;
         volatile uint8_t ucMaxPriorityValue;
 
         /* Determine the maximum priority from which ISR safe FreeRTOS API
-         * functions can be called.  ISR safe functions are those that end in
-         * "FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+         * functions can be called. ISR safe functions are those that end in
+         * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
          * ensure interrupt entry is as fast and simple as possible.
          *
-         * Save the interrupt priority value that is about to be clobbered. */
-        ulOriginalPriority = portNVIC_SHPR2_REG;
-
-        /* Determine the number of priority bits available.  First write to all
-         * possible bits. */
+         * First, determine the number of priority bits available. Write to all
+         * possible bits in the priority setting for SVCall. */
         portNVIC_SHPR2_REG = 0xFF000000;
 
         /* Read the value back to see how many bits stuck. */
@@ -1636,7 +1680,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         /* Calculate the maximum acceptable priority group value for the number
          * of bits read back. */
-
         while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
         {
             ulImplementedPrioBits++;
@@ -1674,16 +1717,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          * register. */
         ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
         ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
-        /* Restore the clobbered interrupt priority register to its original
-         * value. */
-        portNVIC_SHPR2_REG = ulOriginalPriority;
     }
     #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
-    /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+    /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
+     * the highest priority. */
     portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+    portNVIC_SHPR2_REG = 0;
 
     #if ( configENABLE_MPU == 1 )
     {
diff --git a/portable/IAR/ARM_CM7/r0p1/port.c b/portable/IAR/ARM_CM7/r0p1/port.c
index 58129a4df..2790028f4 100644
--- a/portable/IAR/ARM_CM7/r0p1/port.c
+++ b/portable/IAR/ARM_CM7/r0p1/port.c
@@ -45,10 +45,14 @@
     #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
 #endif
 
+/* Prototype of all Interrupt Service Routines (ISRs). */
+typedef void ( * portISR_t )( void );
+
 /* Constants required to manipulate the core.  Registers first... */
 #define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )
 #define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )
 #define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SHPR2_REG                    ( *( ( volatile uint32_t * ) 0xe000ed1c ) )
 #define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
 /* ...then bits in the registers. */
 #define portNVIC_SYSTICK_CLK_BIT              ( 1UL << 2UL )
@@ -63,6 +67,11 @@
 #define portNVIC_PENDSV_PRI                   ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
 #define portNVIC_SYSTICK_PRI                  ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
 
+/* Constants used to check the installation of the FreeRTOS interrupt handlers. */
+#define portSCB_VTOR_REG                      ( *( ( portISR_t ** ) 0xE000ED08 ) )
+#define portVECTOR_INDEX_SVC                  ( 11 )
+#define portVECTOR_INDEX_PENDSV               ( 14 )
+
 /* Constants required to check the validity of an interrupt priority. */
 #define portFIRST_USER_INTERRUPT_NUMBER       ( 16 )
 #define portNVIC_IP_REGISTERS_OFFSET_16       ( 0xE000E3F0 )
@@ -135,6 +144,11 @@ extern void vPortEnableVFP( void );
  */
 static void prvTaskExitError( void );
 
+/*
+ * FreeRTOS handlers implemented in assembly.
+ */
+extern void vPortSVCHandler( void );
+extern void xPortPendSVHandler( void );
 /*-----------------------------------------------------------*/
 
 /* Each task maintains its own interrupt status in the critical nesting
@@ -234,6 +248,40 @@ static void prvTaskExitError( void )
  */
 BaseType_t xPortStartScheduler( void )
 {
+    /* An application can install FreeRTOS interrupt handlers in one of the
+     * folllowing ways:
+     * 1. Direct Routing - Install the functions vPortSVCHandler and
+     *    xPortPendSVHandler for SVCall and PendSV interrupts respectively.
+     * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+     *    interrupts and route program control from those handlers to
+     *    vPortSVCHandler and xPortPendSVHandler functions.
+     *
+     * Applications that use Indirect Routing must set
+     * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+     * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+     * is 1, should be preferred when possible. */
+    #if ( configCHECK_HANDLER_INSTALLATION == 1 )
+    {
+        const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+        /* Validate that the application has correctly installed the FreeRTOS
+         * handlers for SVCall and PendSV interrupts. We do not check the
+         * installation of the SysTick handler because the application may
+         * choose to drive the RTOS tick using a timer other than the SysTick
+         * timer by overriding the weak function vPortSetupTimerInterrupt().
+         *
+         * Assertion failures here indicate incorrect installation of the
+         * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+         * https://www.FreeRTOS.org/FAQHelp.html.
+         *
+         * Systems with a configurable address for the interrupt vector table
+         * can also encounter assertion failures or even system faults here if
+         * VTOR is not set correctly to point to the application's vector table. */
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == vPortSVCHandler );
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == xPortPendSVHandler );
+    }
+    #endif /* configCHECK_HANDLER_INSTALLATION */
+
     #if ( configASSERT_DEFINED == 1 )
     {
         volatile uint8_t ucOriginalPriority;
@@ -318,9 +366,11 @@ BaseType_t xPortStartScheduler( void )
     }
     #endif /* configASSERT_DEFINED */
 
-    /* Make PendSV and SysTick the lowest priority interrupts. */
+    /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
+     * the highest priority. */
     portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+    portNVIC_SHPR2_REG = 0;
 
     /* Start the timer that generates the tick ISR.  Interrupts are disabled
      * here already. */
diff --git a/portable/IAR/ARM_CM85/non_secure/port.c b/portable/IAR/ARM_CM85/non_secure/port.c
index 6a3877894..a5ed7004a 100644
--- a/portable/IAR/ARM_CM85/non_secure/port.c
+++ b/portable/IAR/ARM_CM85/non_secure/port.c
@@ -80,6 +80,12 @@
 #endif
 /*-----------------------------------------------------------*/
 
+/**
+ * @brief Prototype of all Interrupt Service Routines (ISRs).
+ */
+typedef void ( * portISR_t )( void );
+/*-----------------------------------------------------------*/
+
 /**
  * @brief Constants required to manipulate the NVIC.
  */
@@ -101,10 +107,18 @@
 /**
  * @brief Constants required to manipulate the SCB.
  */
-#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_VTOR_REG                      ( *( ( portISR_t ** ) 0xe000ed08 ) )
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
 #define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )
 /*-----------------------------------------------------------*/
 
+/**
+ * @brief Constants used to check the installation of the FreeRTOS interrupt handlers.
+ */
+#define portVECTOR_INDEX_SVC       ( 11 )
+#define portVECTOR_INDEX_PENDSV    ( 14 )
+/*-----------------------------------------------------------*/
+
 /**
  * @brief Constants required to check the validity of an interrupt priority.
  */
@@ -1598,22 +1612,52 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
+    /* An application can install FreeRTOS interrupt handlers in one of the
+     * folllowing ways:
+     * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
+     *    for SVCall and PendSV interrupts respectively.
+     * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+     *    interrupts and route program control from those handlers to
+     *    SVC_Handler and PendSV_Handler functions.
+     *
+     * Applications that use Indirect Routing must set
+     * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+     * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+     * is 1, should be preferred when possible. */
+    #if ( configCHECK_HANDLER_INSTALLATION == 1 )
+    {
+        const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+        /* Validate that the application has correctly installed the FreeRTOS
+         * handlers for SVCall and PendSV interrupts. We do not check the
+         * installation of the SysTick handler because the application may
+         * choose to drive the RTOS tick using a timer other than the SysTick
+         * timer by overriding the weak function vPortSetupTimerInterrupt().
+         *
+         * Assertion failures here indicate incorrect installation of the
+         * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+         * https://www.FreeRTOS.org/FAQHelp.html.
+         *
+         * Systems with a configurable address for the interrupt vector table
+         * can also encounter assertion failures or even system faults here if
+         * VTOR is not set correctly to point to the application's vector table. */
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler );
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler );
+    }
+    #endif /* configCHECK_HANDLER_INSTALLATION */
+
     #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
     {
-        volatile uint32_t ulOriginalPriority;
         volatile uint32_t ulImplementedPrioBits = 0;
         volatile uint8_t ucMaxPriorityValue;
 
         /* Determine the maximum priority from which ISR safe FreeRTOS API
-         * functions can be called.  ISR safe functions are those that end in
-         * "FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+         * functions can be called. ISR safe functions are those that end in
+         * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
          * ensure interrupt entry is as fast and simple as possible.
          *
-         * Save the interrupt priority value that is about to be clobbered. */
-        ulOriginalPriority = portNVIC_SHPR2_REG;
-
-        /* Determine the number of priority bits available.  First write to all
-         * possible bits. */
+         * First, determine the number of priority bits available. Write to all
+         * possible bits in the priority setting for SVCall. */
         portNVIC_SHPR2_REG = 0xFF000000;
 
         /* Read the value back to see how many bits stuck. */
@@ -1636,7 +1680,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         /* Calculate the maximum acceptable priority group value for the number
          * of bits read back. */
-
         while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
         {
             ulImplementedPrioBits++;
@@ -1674,16 +1717,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          * register. */
         ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
         ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
-        /* Restore the clobbered interrupt priority register to its original
-         * value. */
-        portNVIC_SHPR2_REG = ulOriginalPriority;
     }
     #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
-    /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+    /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
+     * the highest priority. */
     portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+    portNVIC_SHPR2_REG = 0;
 
     #if ( configENABLE_MPU == 1 )
     {
diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/port.c b/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
index 6a3877894..a5ed7004a 100644
--- a/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
@@ -80,6 +80,12 @@
 #endif
 /*-----------------------------------------------------------*/
 
+/**
+ * @brief Prototype of all Interrupt Service Routines (ISRs).
+ */
+typedef void ( * portISR_t )( void );
+/*-----------------------------------------------------------*/
+
 /**
  * @brief Constants required to manipulate the NVIC.
  */
@@ -101,10 +107,18 @@
 /**
  * @brief Constants required to manipulate the SCB.
  */
-#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_VTOR_REG                      ( *( ( portISR_t ** ) 0xe000ed08 ) )
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
 #define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )
 /*-----------------------------------------------------------*/
 
+/**
+ * @brief Constants used to check the installation of the FreeRTOS interrupt handlers.
+ */
+#define portVECTOR_INDEX_SVC       ( 11 )
+#define portVECTOR_INDEX_PENDSV    ( 14 )
+/*-----------------------------------------------------------*/
+
 /**
  * @brief Constants required to check the validity of an interrupt priority.
  */
@@ -1598,22 +1612,52 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
+    /* An application can install FreeRTOS interrupt handlers in one of the
+     * folllowing ways:
+     * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
+     *    for SVCall and PendSV interrupts respectively.
+     * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+     *    interrupts and route program control from those handlers to
+     *    SVC_Handler and PendSV_Handler functions.
+     *
+     * Applications that use Indirect Routing must set
+     * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+     * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+     * is 1, should be preferred when possible. */
+    #if ( configCHECK_HANDLER_INSTALLATION == 1 )
+    {
+        const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+        /* Validate that the application has correctly installed the FreeRTOS
+         * handlers for SVCall and PendSV interrupts. We do not check the
+         * installation of the SysTick handler because the application may
+         * choose to drive the RTOS tick using a timer other than the SysTick
+         * timer by overriding the weak function vPortSetupTimerInterrupt().
+         *
+         * Assertion failures here indicate incorrect installation of the
+         * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+         * https://www.FreeRTOS.org/FAQHelp.html.
+         *
+         * Systems with a configurable address for the interrupt vector table
+         * can also encounter assertion failures or even system faults here if
+         * VTOR is not set correctly to point to the application's vector table. */
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler );
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler );
+    }
+    #endif /* configCHECK_HANDLER_INSTALLATION */
+
     #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
     {
-        volatile uint32_t ulOriginalPriority;
         volatile uint32_t ulImplementedPrioBits = 0;
         volatile uint8_t ucMaxPriorityValue;
 
         /* Determine the maximum priority from which ISR safe FreeRTOS API
-         * functions can be called.  ISR safe functions are those that end in
-         * "FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+         * functions can be called. ISR safe functions are those that end in
+         * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
          * ensure interrupt entry is as fast and simple as possible.
          *
-         * Save the interrupt priority value that is about to be clobbered. */
-        ulOriginalPriority = portNVIC_SHPR2_REG;
-
-        /* Determine the number of priority bits available.  First write to all
-         * possible bits. */
+         * First, determine the number of priority bits available. Write to all
+         * possible bits in the priority setting for SVCall. */
         portNVIC_SHPR2_REG = 0xFF000000;
 
         /* Read the value back to see how many bits stuck. */
@@ -1636,7 +1680,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         /* Calculate the maximum acceptable priority group value for the number
          * of bits read back. */
-
         while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
         {
             ulImplementedPrioBits++;
@@ -1674,16 +1717,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          * register. */
         ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
         ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
-        /* Restore the clobbered interrupt priority register to its original
-         * value. */
-        portNVIC_SHPR2_REG = ulOriginalPriority;
     }
     #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
 
-    /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+    /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
+     * the highest priority. */
     portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+    portNVIC_SHPR2_REG = 0;
 
     #if ( configENABLE_MPU == 1 )
     {
diff --git a/portable/RVDS/ARM_CM4_MPU/port.c b/portable/RVDS/ARM_CM4_MPU/port.c
index 566d4f737..af4ea632f 100644
--- a/portable/RVDS/ARM_CM4_MPU/port.c
+++ b/portable/RVDS/ARM_CM4_MPU/port.c
@@ -51,6 +51,9 @@
     #define configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS    1
 #endif
 
+/* Prototype of all Interrupt Service Routines (ISRs). */
+typedef void ( * portISR_t )( void );
+
 /* Constants required to access and manipulate the NVIC. */
 #define portNVIC_SYSTICK_CTRL_REG                 ( *( ( volatile uint32_t * ) 0xe000e010 ) )
 #define portNVIC_SYSTICK_LOAD_REG                 ( *( ( volatile uint32_t * ) 0xe000e014 ) )
@@ -87,7 +90,6 @@
 #define portMIN_INTERRUPT_PRIORITY                ( 255UL )
 #define portNVIC_PENDSV_PRI                       ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
 #define portNVIC_SYSTICK_PRI                      ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
-#define portNVIC_SVC_PRI                          ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )
 
 /* Constants required to manipulate the VFP. */
 #define portFPCCR                                 ( ( volatile uint32_t * ) 0xe000ef34UL ) /* Floating point context control register. */
@@ -99,6 +101,11 @@
 #define portINITIAL_CONTROL_IF_UNPRIVILEGED       ( 0x03 )
 #define portINITIAL_CONTROL_IF_PRIVILEGED         ( 0x02 )
 
+/* Constants used to check the installation of the FreeRTOS interrupt handlers. */
+#define portSCB_VTOR_REG                          ( *( ( portISR_t ** ) 0xE000ED08 ) )
+#define portVECTOR_INDEX_SVC                      ( 11 )
+#define portVECTOR_INDEX_PENDSV                   ( 14 )
+
 /* Constants required to check the validity of an interrupt priority. */
 #define portFIRST_USER_INTERRUPT_NUMBER           ( 16 )
 #define portNVIC_IP_REGISTERS_OFFSET_16           ( 0xE000E3F0 )
@@ -386,7 +393,6 @@ void vSVCHandler_C( uint32_t * pulParam )
     switch( ucSVCNumber )
     {
         case portSVC_START_SCHEDULER:
-            portNVIC_SHPR2_REG |= portNVIC_SVC_PRI;
             prvRestoreContextOfFirstTask();
             break;
 
@@ -822,6 +828,40 @@ BaseType_t xPortStartScheduler( void )
         configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
     #endif
 
+    /* An application can install FreeRTOS interrupt handlers in one of the
+     * folllowing ways:
+     * 1. Direct Routing - Install the functions vPortSVCHandler and
+     *    xPortPendSVHandler for SVCall and PendSV interrupts respectively.
+     * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+     *    interrupts and route program control from those handlers to
+     *    vPortSVCHandler and xPortPendSVHandler functions.
+     *
+     * Applications that use Indirect Routing must set
+     * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+     * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+     * is 1, should be preferred when possible. */
+    #if ( configCHECK_HANDLER_INSTALLATION == 1 )
+    {
+        const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+        /* Validate that the application has correctly installed the FreeRTOS
+         * handlers for SVCall and PendSV interrupts. We do not check the
+         * installation of the SysTick handler because the application may
+         * choose to drive the RTOS tick using a timer other than the SysTick
+         * timer by overriding the weak function vPortSetupTimerInterrupt().
+         *
+         * Assertion failures here indicate incorrect installation of the
+         * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+         * https://www.FreeRTOS.org/FAQHelp.html.
+         *
+         * Systems with a configurable address for the interrupt vector table
+         * can also encounter assertion failures or even system faults here if
+         * VTOR is not set correctly to point to the application's vector table. */
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == vPortSVCHandler );
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == xPortPendSVHandler );
+    }
+    #endif /* configCHECK_HANDLER_INSTALLATION */
+
     #if ( configASSERT_DEFINED == 1 )
     {
         volatile uint8_t ucOriginalPriority;
@@ -907,10 +947,11 @@ BaseType_t xPortStartScheduler( void )
     #endif /* configASSERT_DEFINED */
 
     /* Make PendSV and SysTick the same priority as the kernel, and the SVC
-     * handler higher priority so it can be used to exit a critical section (where
-     * lower priorities are masked). */
+     * handler highest priority so it can be used to exit a critical section
+     * (where lower priorities are masked). */
     portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+    portNVIC_SHPR2_REG = 0;
 
     /* Configure the regions in the MPU that are common to all tasks. */
     prvSetupMPU();
@@ -1196,6 +1237,7 @@ __asm void vPortEnableVFP( void )
     orr r1, r1, #( 0xf << 20 ) /* Enable CP10 and CP11 coprocessors, then save back. */
     str r1, [ r0 ]
     bx r14
+    nop
 /* *INDENT-ON* */
 }
 /*-----------------------------------------------------------*/

From bd0f87c18b292f45ebf4d4b4c5bb96765465f760 Mon Sep 17 00:00:00 2001
From: Darian <32921628+Dazza0@users.noreply.github.com>
Date: Mon, 11 Dec 2023 15:12:53 +0800
Subject: [PATCH 159/424] Add portTASK_SWITCH_HOOK (#867)

This commit adds a portTASK_SWITCH_HOOK() macro which allows ports to inject
behavior immediately after a context switch. For example, this macro could be
used by ports that need to set an end of stack watchpoint after a context
swtich.

Co-authored-by: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Co-authored-by: Soren Ptak <ptaksoren@gmail.com>
Co-authored-by: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Co-authored-by: Tony Josi <tonyjosi@amazon.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
---
 include/FreeRTOS.h |  4 ++++
 tasks.c            | 10 ++++++++++
 2 files changed, 14 insertions(+)

diff --git a/include/FreeRTOS.h b/include/FreeRTOS.h
index b6caec77f..23526bb02 100644
--- a/include/FreeRTOS.h
+++ b/include/FreeRTOS.h
@@ -529,6 +529,10 @@
     #define portSETUP_TCB( pxTCB )    ( void ) ( pxTCB )
 #endif
 
+#ifndef portTASK_SWITCH_HOOK
+    #define portTASK_SWITCH_HOOK( pxTCB )    ( void ) ( pxTCB )
+#endif
+
 #ifndef configQUEUE_REGISTRY_SIZE
     #define configQUEUE_REGISTRY_SIZE    0U
 #endif
diff --git a/tasks.c b/tasks.c
index a19ab9195..ccafc1e25 100644
--- a/tasks.c
+++ b/tasks.c
@@ -5153,6 +5153,11 @@ BaseType_t xTaskIncrementTick( void )
             taskSELECT_HIGHEST_PRIORITY_TASK();
             traceTASK_SWITCHED_IN();
 
+            /* Macro to inject port specific behaviour immediately after
+             * switching tasks, such as setting an end of stack watchpoint
+             * or reconfiguring the MPU. */
+            portTASK_SWITCH_HOOK( pxCurrentTCB );
+
             /* After the new task is switched in, update the global errno. */
             #if ( configUSE_POSIX_ERRNO == 1 )
             {
@@ -5245,6 +5250,11 @@ BaseType_t xTaskIncrementTick( void )
                 taskSELECT_HIGHEST_PRIORITY_TASK( xCoreID );
                 traceTASK_SWITCHED_IN();
 
+                /* Macro to inject port specific behaviour immediately after
+                 * switching tasks, such as setting an end of stack watchpoint
+                 * or reconfiguring the MPU. */
+                portTASK_SWITCH_HOOK( pxCurrentTCBs[ portGET_CORE_ID() ] );
+
                 /* After the new task is switched in, update the global errno. */
                 #if ( configUSE_POSIX_ERRNO == 1 )
                 {

From e0bb21f832cdcef9250e7dfe1c82abf9264f9d31 Mon Sep 17 00:00:00 2001
From: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Date: Wed, 13 Dec 2023 16:11:29 +0800
Subject: [PATCH 160/424] Remove the sample smp configuration folder (#922)

* Remove the sample smp configuration folder
---
 .github/.cSpellWords.txt                      |  1 +
 examples/cmake_example/CMakeLists.txt         | 17 ++---
 .../sample_configuration/smp/FreeRTOSConfig.h | 65 -------------------
 examples/sample_configuration/smp/readme.md   | 10 ---
 4 files changed, 8 insertions(+), 85 deletions(-)
 delete mode 100644 examples/sample_configuration/smp/FreeRTOSConfig.h
 delete mode 100644 examples/sample_configuration/smp/readme.md

diff --git a/.github/.cSpellWords.txt b/.github/.cSpellWords.txt
index f9e1c9bbf..9e0f6560b 100644
--- a/.github/.cSpellWords.txt
+++ b/.github/.cSpellWords.txt
@@ -175,6 +175,7 @@ DATRDY
 DBGU
 DCDIC
 DCMR
+Dconfig
 DCOUNT
 decf
 decfsz
diff --git a/examples/cmake_example/CMakeLists.txt b/examples/cmake_example/CMakeLists.txt
index f8a4e2d63..4d13c4c77 100644
--- a/examples/cmake_example/CMakeLists.txt
+++ b/examples/cmake_example/CMakeLists.txt
@@ -7,18 +7,15 @@ set(FREERTOS_KERNEL_PATH "../../")
 # Add the freertos_config for FreeRTOS-Kernel
 add_library(freertos_config INTERFACE)
 
+target_include_directories(freertos_config
+    INTERFACE
+    "../sample_configuration"
+)
+
 if (DEFINED FREERTOS_SMP_EXAMPLE AND FREERTOS_SMP_EXAMPLE STREQUAL "1")
     message(STATUS "Build FreeRTOS SMP example")
-    target_include_directories(freertos_config
-        INTERFACE
-        "../sample_configuration/smp"
-    )
-else()
-    message(STATUS "Build FreeRTOS example")
-    target_include_directories(freertos_config
-        INTERFACE
-        "../sample_configuration"
-    )
+    # Adding the following configurations to build SMP template port
+    add_compile_options( -DconfigNUMBER_OF_CORES=2 -DconfigUSE_PASSIVE_IDLE_HOOK=0 )
 endif()
 
 # Select the heap port.  values between 1-4 will pick a heap.
diff --git a/examples/sample_configuration/smp/FreeRTOSConfig.h b/examples/sample_configuration/smp/FreeRTOSConfig.h
deleted file mode 100644
index f3b68a444..000000000
--- a/examples/sample_configuration/smp/FreeRTOSConfig.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/*******************************************************************************
- * This file provides an example FreeRTOSConfig.h header file, inclusive of an
- * abbreviated explanation of each configuration item.  Online and reference
- * documentation provides more information.
- * https://www.freertos.org/a00110.html
- *
- * Constant values enclosed in square brackets ('[' and ']') must be completed
- * before this file will build.
- *
- * Use the FreeRTOSConfig.h supplied with the RTOS port in use rather than this
- * generic file, if one is available.
- ******************************************************************************/
-
-#ifndef __FREERTOS_CONFIG_SMP_H__
-#define __FREERTOS_CONFIG_SMP_H__
-
-#include "../FreeRTOSConfig.h"
-
-/******************************************************************************/
-/* Scheduling behaviour related definitions. **********************************/
-/******************************************************************************/
-
-/* Set configNUMBER_OF_CORES to greater than 1 to enable running one instance of
- * FreeRTOS kernel to schedule tasks across multiple identical processor cores. */
-#define configNUMBER_OF_CORES    2
-
-/******************************************************************************/
-/* Hook and callback function related definitions. ****************************/
-/******************************************************************************/
-
-/* Set the following configUSE_* constants to 1 to include the named hook
- * functionality in the build.  Set to 0 to exclude the hook functionality from the
- * build.  The application writer is responsible for providing the hook function
- * for any set to 1.  See https://www.freertos.org/a00016.html */
-#define configUSE_PASSIVE_IDLE_HOOK    0
-
-#endif /* __FREERTOS_CONFIG_SMP_H__ */
diff --git a/examples/sample_configuration/smp/readme.md b/examples/sample_configuration/smp/readme.md
deleted file mode 100644
index 8dc02bd56..000000000
--- a/examples/sample_configuration/smp/readme.md
+++ /dev/null
@@ -1,10 +0,0 @@
-# Configuration support for FreeRTOS SMP
-
-## Overview
-The FreeRTOSConfig.h provided in this folder is a sample configuration that will
-assist you in preparing the configuration to enable SMP support in the FreeRTOS
-Kernel for your application.
-
-Based on single core sample configuration file, this configuration file is created
-with minimal configuration change. More SMP scheduler configurations can be found
-in [Symmetric Multiprocessing (SMP) with FreeRTOS](https://freertos.org/symmetric-multiprocessing-introduction.html)

From 1384c68dc78643aa3f251a57ebf3069e59ccaa0e Mon Sep 17 00:00:00 2001
From: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Date: Fri, 15 Dec 2023 10:01:18 +0530
Subject: [PATCH 161/424] Update sample configuration file  (#923)

* Update sample configuration file in the examples folder

* Add SMP Configuration definitions

* Fix build issue in cmake example

* Add CoRoutine Configuration definitions

* Code review suggestions

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Fix formatting

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 .../sample_configuration/FreeRTOSConfig.h     | 167 +++++++++++++++---
 1 file changed, 146 insertions(+), 21 deletions(-)

diff --git a/examples/sample_configuration/FreeRTOSConfig.h b/examples/sample_configuration/FreeRTOSConfig.h
index 32b75bc9d..a672600ff 100644
--- a/examples/sample_configuration/FreeRTOSConfig.h
+++ b/examples/sample_configuration/FreeRTOSConfig.h
@@ -39,8 +39,8 @@
  * generic file, if one is available.
  ******************************************************************************/
 
-#ifndef __FREERTOS_CONFIG_H__
-#define __FREERTOS_CONFIG_H__
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
 
 /******************************************************************************/
 /* Hardware description related definitions. **********************************/
@@ -63,7 +63,7 @@
  * frequency, as normal, and configSYSTICK_CLOCK_HZ to the SysTick clock
  * frequency.  Not used if left undefined.
  * The default value is undefined (commented out).  If you need this value bring it
- * back and set it to a suitable value */
+ * back and set it to a suitable value. */
 
 /*
  #define configSYSTICK_CLOCK_HZ                  [Platform specific]
@@ -79,14 +79,14 @@
 
 /* Set configUSE_PREEMPTION to 1 to use pre-emptive scheduling.  Set
  * configUSE_PREEMPTION to 0 to use co-operative scheduling.
- * See https://www.freertos.org/single-core-amp-smp-rtos-scheduling.html */
+ * See https://www.freertos.org/single-core-amp-smp-rtos-scheduling.html. */
 #define configUSE_PREEMPTION                       1
 
 /* Set configUSE_TIME_SLICING to 1 to have the scheduler switch between Ready
  * state tasks of equal priority on every tick interrupt.  Set
  * configUSE_TIME_SLICING to 0 to prevent the scheduler switching between Ready
  * state tasks just because there was a tick interrupt.  See
- * https://freertos.org/single-core-amp-smp-rtos-scheduling.html */
+ * https://freertos.org/single-core-amp-smp-rtos-scheduling.html. */
 #define configUSE_TIME_SLICING                     0
 
 /* Set configUSE_PORT_OPTIMISED_TASK_SELECTION to 1 to select the next task to
@@ -162,6 +162,13 @@
  * Defaults to 0 if left undefined. */
 #define configNUM_THREAD_LOCAL_STORAGE_POINTERS    0
 
+/* When configUSE_MINI_LIST_ITEM is set to 0, MiniListItem_t and ListItem_t are
+ * both the same. When configUSE_MINI_LIST_ITEM is set to 1, MiniListItem_t contains
+ * 3 fewer fields than ListItem_t which saves some RAM at the cost of violating
+ * strict aliasing rules which some compilers depend on for optimization. Defaults
+ * to 1 if left undefined. */
+#define configUSE_MINI_LIST_ITEM                   1
+
 /* Sets the type used by the parameter to xTaskCreate() that specifies the stack
  * size of the task being created.  The same type is used to return information
  * about stack usage in various other API calls.  Defaults to size_t if left
@@ -169,11 +176,24 @@
 #define configSTACK_DEPTH_TYPE                     size_t
 
 /* configMESSAGE_BUFFER_LENGTH_TYPE sets the type used to store the length of
- *  each message written to a FreeRTOS message buffer (the length is also written to
- *  the message buffer.  Defaults to size_t if left undefined - but that may waste
- *  space if messages never go above a length that could be held in a uint8_t. */
+ * each message written to a FreeRTOS message buffer (the length is also written to
+ * the message buffer.  Defaults to size_t if left undefined - but that may waste
+ * space if messages never go above a length that could be held in a uint8_t. */
 #define configMESSAGE_BUFFER_LENGTH_TYPE           size_t
 
+/* If configHEAP_CLEAR_MEMORY_ON_FREE is set to 1, then blocks of memory allocated
+ * using pvPortMalloc() will be cleared (i.e. set to zero) when freed using
+ * vPortFree(). Defaults to 0 if left undefined. */
+#define configHEAP_CLEAR_MEMORY_ON_FREE            1
+
+/* vTaskList and vTaskGetRunTimeStats APIs take a buffer as a parameter and assume
+ * that the length of the buffer is configSTATS_BUFFER_MAX_LENGTH. Defaults to
+ * 0xFFFF if left undefined.
+ * New applications are recommended to use vTaskListTasks and
+ * vTaskGetRunTimeStatistics APIs instead and supply the length of the buffer
+ * explicitly to avoid memory corruption. */
+#define configSTATS_BUFFER_MAX_LENGTH              0xFFFF
+
 /* Set configUSE_NEWLIB_REENTRANT to 1 to have a newlib reent structure
  * allocated for each task.  Set to 0 to not support newlib reent structures.
  * Default to 0 if left undefined.
@@ -194,7 +214,7 @@
  * build.  Set to 0 to exclude software timer functionality from the build.  The
  * FreeRTOS/source/timers.c source file must be included in the build if
  * configUSE_TIMERS is set to 1.  Default to 0 if left undefined.  See
- * https://www.freertos.org/RTOS-software-timer.html */
+ * https://www.freertos.org/RTOS-software-timer.html. */
 #define configUSE_TIMERS                1
 
 /* configTIMER_TASK_PRIORITY sets the priority used by the timer task.  Only
@@ -224,20 +244,20 @@
  * that create FreeRTOS objects (tasks, queues, etc.) using statically allocated
  * memory in the build.  Set to 0 to exclude the ability to create statically
  * allocated objects from the build.  Defaults to 0 if left undefined.  See
- * https://www.freertos.org/Static_Vs_Dynamic_Memory_Allocation.html */
+ * https://www.freertos.org/Static_Vs_Dynamic_Memory_Allocation.html. */
 #define configSUPPORT_STATIC_ALLOCATION              1
 
 /* Set configSUPPORT_DYNAMIC_ALLOCATION to 1 to include FreeRTOS API functions
  * that create FreeRTOS objects (tasks, queues, etc.) using dynamically allocated
  * memory in the build.  Set to 0 to exclude the ability to create dynamically
  * allocated objects from the build.  Defaults to 1 if left undefined.  See
- * https://www.freertos.org/Static_Vs_Dynamic_Memory_Allocation.html */
+ * https://www.freertos.org/Static_Vs_Dynamic_Memory_Allocation.html. */
 #define configSUPPORT_DYNAMIC_ALLOCATION             1
 
 /* Sets the total size of the FreeRTOS heap, in bytes, when heap_1.c, heap_2.c
  * or heap_4.c are included in the build.  This value is defaulted to 4096 bytes but
  * it must be tailored to each application.  Note the heap will appear in the .bss
- * section.  See https://www.freertos.org/a00111.html */
+ * section.  See https://www.freertos.org/a00111.html. */
 #define configTOTAL_HEAP_SIZE                        4096
 
 /* Set configAPPLICATION_ALLOCATED_HEAP to 1 to have the application allocate
@@ -253,6 +273,11 @@
  * Defaults to 0 if left undefined. */
 #define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP    0
 
+/* Set configENABLE_HEAP_PROTECTOR to 1 to enable bounds checking and obfuscation
+ * to internal heap block pointers in heap_4.c and heap_5.c to help catch pointer
+ * corruptions. Defaults to 0 if left undefined. */
+#define configENABLE_HEAP_PROTECTOR                  0
+
 /******************************************************************************/
 /* Interrupt nesting behaviour configuration. *********************************/
 /******************************************************************************/
@@ -283,12 +308,20 @@
 /* Set the following configUSE_* constants to 1 to include the named hook
  * functionality in the build.  Set to 0 to exclude the hook functionality from the
  * build.  The application writer is responsible for providing the hook function
- * for any set to 1.  See https://www.freertos.org/a00016.html */
+ * for any set to 1.  See https://www.freertos.org/a00016.html. */
 #define configUSE_IDLE_HOOK                   0
 #define configUSE_TICK_HOOK                   0
 #define configUSE_MALLOC_FAILED_HOOK          0
 #define configUSE_DAEMON_TASK_STARTUP_HOOK    0
 
+/* Set configUSE_SB_COMPLETED_CALLBACK to 1 to have send and receive completed
+ * callbacks for each instance of a stream buffer or message buffer. When the
+ * option is set to 1, APIs xStreamBufferCreateWithCallback() and
+ * xStreamBufferCreateStaticWithCallback() (and likewise APIs for message
+ * buffer) can be used to create a stream buffer or message buffer instance
+ * with application provided callbacks. Defaults to 0 if left undefined. */
+#define configUSE_SB_COMPLETED_CALLBACK       0
+
 /* Set configCHECK_FOR_STACK_OVERFLOW to 1 or 2 for FreeRTOS to check for a
  * stack overflow at the time of a context switch.  Set to 0 to not look for a
  * stack overflow.  If configCHECK_FOR_STACK_OVERFLOW is 1 then the check only
@@ -307,14 +340,14 @@
 /******************************************************************************/
 
 /* Set configGENERATE_RUN_TIME_STATS to 1 to have FreeRTOS collect data on the
-* processing time used by each task.  Set to 0 to not collect the data.  The
-* application writer needs to provide a clock source if set to 1.  Defaults to 0
-* if left undefined.  See https://www.freertos.org/rtos-run-time-stats.html */
+ * processing time used by each task.  Set to 0 to not collect the data.  The
+ * application writer needs to provide a clock source if set to 1.  Defaults to 0
+ * if left undefined.  See https://www.freertos.org/rtos-run-time-stats.html. */
 #define configGENERATE_RUN_TIME_STATS           0
 
 /* Set configUSE_TRACE_FACILITY to include additional task structure members
  * are used by trace and visualisation functions and tools.  Set to 0 to exclude
- * the additional information from the structures.  Defaults to 0 if left
+ * the additional information from the structures. Defaults to 0 if left
  * undefined. */
 #define configUSE_TRACE_FACILITY                0
 
@@ -325,6 +358,21 @@
  * undefined. */
 #define configUSE_STATS_FORMATTING_FUNCTIONS    0
 
+/******************************************************************************/
+/* Co-routine related definitions. ********************************************/
+/******************************************************************************/
+
+/* Set configUSE_CO_ROUTINES to 1 to include co-routine functionality in the
+ * build, or 0 to omit co-routine functionality from the build. To include
+ * co-routines, croutine.c must be included in the project. Defaults to 0 if left
+ * undefined. */
+#define configUSE_CO_ROUTINES              0
+
+/* configMAX_CO_ROUTINE_PRIORITIES defines the number of priorities available
+ * to the application co-routines. Any number of co-routines can share the same
+ * priority. Defaults to 0 if left undefined. */
+#define configMAX_CO_ROUTINE_PRIORITIES    1
+
 /******************************************************************************/
 /* Debugging assistance. ******************************************************/
 /******************************************************************************/
@@ -346,7 +394,7 @@
     }
 
 /******************************************************************************/
-/* Cortex-M MPU specific definitions. *****************************************/
+/* FreeRTOS MPU specific definitions. *****************************************/
 /******************************************************************************/
 
 /* If configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS is set to 1 then
@@ -380,16 +428,93 @@
  * escalations originating from outside of the kernel code itself.  Set to 1 to
  * allow application tasks to raise privilege.  Defaults to 1 if left undefined.
  * Only used by the FreeRTOS Cortex-M MPU ports, not the standard ARMv7-M Cortex-M
- * port.*/
+ * port. */
 #define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY               1
 
 /* Set configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS to 1 to allow unprivileged
  * tasks enter critical sections (effectively mask interrupts).  Set to 0 to
  * prevent unprivileged tasks entering critical sections.  Defaults to 1 if left
  * undefined.  Only used by the FreeRTOS Cortex-M MPU ports, not the standard
- * ARMv7-M Cortex-M port.*/
+ * ARMv7-M Cortex-M port. */
 #define configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS                0
 
+/* FreeRTOS Kernel version 10.6.0 introduced a new v2 MPU wrapper, namely
+ * mpu_wrappers_v2.c. Set configUSE_MPU_WRAPPERS_V1 to 0 to use the new v2 MPU
+ * wrapper. Set configUSE_MPU_WRAPPERS_V1 to 1 to use the old v1 MPU wrapper
+ * (mpu_wrappers.c). Defaults to 0 if left undefined. */
+#define configUSE_MPU_WRAPPERS_V1                                 0
+
+/* When using the v2 MPU wrapper, set configPROTECTED_KERNEL_OBJECT_POOL_SIZE to
+ * the total number of kernel objects, which includes tasks, queues, semaphores,
+ * mutexes, event groups, timers, stream buffers and message buffers, in your
+ * application. The application will not be able to have more than
+ * configPROTECTED_KERNEL_OBJECT_POOL_SIZE kernel objects at any point of
+ * time. */
+#define configPROTECTED_KERNEL_OBJECT_POOL_SIZE                   10
+
+/* When using the v2 MPU wrapper, set configSYSTEM_CALL_STACK_SIZE to the size
+ * of the system call stack in words. Each task has a statically allocated
+ * memory buffer of this size which is used as the stack to execute system
+ * calls. For example, if configSYSTEM_CALL_STACK_SIZE is defined as 128 and
+ * there are 10 tasks in the application, the total amount of memory used for
+ * system call stacks is 128 * 10 = 1280 words. */
+#define configSYSTEM_CALL_STACK_SIZE                              128
+
+/* When using the v2 MPU wrapper, set configENABLE_ACCESS_CONTROL_LIST to 1 to
+ * enable Access Control List (ACL) feature. When ACL is enabled, an
+ * unprivileged task by default does not have access to any kernel object other
+ * than itself. The application writer needs to explicitly grant the
+ * unprivileged task access to the kernel objects it needs using the APIs
+ * provided for the same. Defaults to 0 if left undefined. */
+#define configENABLE_ACCESS_CONTROL_LIST                          1
+
+/******************************************************************************/
+/* SMP( Symmetric MultiProcessing ) Specific Configuration definitions. *******/
+/******************************************************************************/
+
+/* Set configNUMBER_OF_CORES to the number of available processor cores. Defaults
+ * to 1 if left undefined. */
+
+/*
+ #define configNUMBER_OF_CORES                     [Num of available cores]
+ */
+
+/* When using SMP (i.e. configNUMBER_OF_CORES is greater than one), set
+ * configRUN_MULTIPLE_PRIORITIES to 0 to allow multiple tasks to run
+ * simultaneously only if they do not have equal priority, thereby maintaining
+ * the paradigm of a lower priority task never running if a higher priority task
+ * is able to run. If configRUN_MULTIPLE_PRIORITIES is set to 1, multiple tasks
+ * with different priorities may run simultaneously - so a higher and lower
+ * priority task may run on different cores at the same time. */
+#define configRUN_MULTIPLE_PRIORITIES             0
+
+/* When using SMP (i.e. configNUMBER_OF_CORES is greater than one), set
+ * configUSE_CORE_AFFINITY to 1 to enable core affinity feature. When core
+ * affinity feature is enabled, the vTaskCoreAffinitySet and vTaskCoreAffinityGet
+ * APIs can be used to set and retrieve which cores a task can run on. If
+ * configUSE_CORE_AFFINITY is set to 0 then the FreeRTOS scheduler is free to
+ * run any task on any available core. */
+#define configUSE_CORE_AFFINITY                   0
+
+/* When using SMP (i.e. configNUMBER_OF_CORES is greater than one), if
+ * configUSE_TASK_PREEMPTION_DISABLE is set to 1, individual tasks can be set to
+ * either pre-emptive or co-operative mode using the vTaskPreemptionDisable and
+ * vTaskPreemptionEnable APIs. */
+#define configUSE_TASK_PREEMPTION_DISABLE         0
+
+/* When using SMP (i.e. configNUMBER_OF_CORES is greater than one), set
+ * configUSE_PASSIVE_IDLE_HOOK to 1 to allow the application writer to use
+ * the passive idle task hook to add background functionality without the overhead
+ * of a separate task. Defaults to 0 if left undefined. */
+#define configUSE_PASSIVE_IDLE_HOOK               0
+
+/* When using SMP (i.e. configNUMBER_OF_CORES is greater than one),
+ * configTIMER_SERVICE_TASK_CORE_AFFINITY allows the application writer to set
+ * the core affinity of the RTOS Daemon/Timer Service task. Defaults to
+ * tskNO_AFFINITY if left undefined. */
+#define configTIMER_SERVICE_TASK_CORE_AFFINITY    tskNO_AFFINITY
+
+
 /******************************************************************************/
 /* ARMv8-M secure side port related definitions. ******************************/
 /******************************************************************************/
@@ -440,4 +565,4 @@
 #define INCLUDE_xTaskGetHandle                 0
 #define INCLUDE_xTaskResumeFromISR             1
 
-#endif /* __FREERTOS_CONFIG_H__ */
+#endif /* FREERTOS_CONFIG_H */

From 553b0ad5d395fb06e205907edd875b0abca235d0 Mon Sep 17 00:00:00 2001
From: Soren Ptak <ptaksoren@gmail.com>
Date: Fri, 15 Dec 2023 12:34:52 -0500
Subject: [PATCH 162/424] Update comments related to portYIELD_FROM_ISR() in
 queue.h #925

---
 include/queue.h | 23 ++++++++++++++++-------
 tasks.c         |  2 +-
 2 files changed, 17 insertions(+), 8 deletions(-)

diff --git a/include/queue.h b/include/queue.h
index b00a07f37..c6497b5b6 100644
--- a/include/queue.h
+++ b/include/queue.h
@@ -1185,9 +1185,12 @@ void vQueueDelete( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
  *  {
  *      // Writing to the queue caused a task to unblock and the unblocked task
  *      // has a priority higher than or equal to the priority of the currently
- *      // executing task (the task this interrupt interrupted).  Perform a context
+ *      // executing task (the task this interrupt interrupted). Perform a context
  *      // switch so this interrupt returns directly to the unblocked task.
- *      portYIELD_FROM_ISR(); // or portEND_SWITCHING_ISR() depending on the port.
+ *      // The macro used is port specific and will be either
+ *      // portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() - refer to the documentation
+ *      // page for the port being used.
+ *      portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
  *  }
  * }
  * @endcode
@@ -1260,8 +1263,11 @@ void vQueueDelete( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
  *  // Now the buffer is empty we can switch context if necessary.
  *  if( xHigherPriorityTaskWoken )
  *  {
- *      // Actual macro used here is port specific.
- *      portYIELD_FROM_ISR ();
+ *       // As xHigherPriorityTaskWoken is now set to pdTRUE then a context
+ *       // switch should be requested. The macro used is port specific and
+ *       // will be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() -
+ *       // refer to the documentation page for the port being used.
+ *       portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
  *  }
  * }
  * @endcode
@@ -1337,11 +1343,14 @@ void vQueueDelete( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
  *
  *  } while( portINPUT_BYTE( BUFFER_COUNT ) );
  *
- *  // Now the buffer is empty we can switch context if necessary.  Note that the
- *  // name of the yield function required is port specific.
+ *  // Now the buffer is empty we can switch context if necessary.
  *  if( xHigherPriorityTaskWokenByPost )
  *  {
- *      portYIELD_FROM_ISR();
+ *       // As xHigherPriorityTaskWokenByPost is now set to pdTRUE then a context
+ *       // switch should be requested. The macro used is port specific and
+ *       // will be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() -
+ *       // refer to the documentation page for the port being used.
+ *       portYIELD_FROM_ISR( xHigherPriorityTaskWokenByPost );
  *  }
  * }
  * @endcode
diff --git a/tasks.c b/tasks.c
index ccafc1e25..279d4bdb3 100644
--- a/tasks.c
+++ b/tasks.c
@@ -3463,7 +3463,7 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
 
                             /* Mark that a yield is pending in case the user is not
                              * using the return value to initiate a context switch
-                             * from the ISR using portYIELD_FROM_ISR. */
+                             * from the ISR using the port specific portYIELD_FROM_ISR(). */
                             xYieldPendings[ 0 ] = pdTRUE;
                         }
                         else

From b0439d3283c3f46af68d4a3c02c1b40fe64534af Mon Sep 17 00:00:00 2001
From: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Date: Mon, 18 Dec 2023 10:43:08 +0530
Subject: [PATCH 163/424] Rename sample configuration to template configuration
 (#927)

* Rename sample configuration to template configuration

* Rename sample configuration to template configuration in cmake example file
---
 .github/scripts/kernel_checker.py                             | 2 +-
 README.md                                                     | 4 ++--
 examples/cmake_example/CMakeLists.txt                         | 2 +-
 .../FreeRTOSConfig.h                                          | 0
 .../readme.md                                                 | 0
 5 files changed, 4 insertions(+), 4 deletions(-)
 rename examples/{sample_configuration => template_configuration}/FreeRTOSConfig.h (100%)
 rename examples/{sample_configuration => template_configuration}/readme.md (100%)

diff --git a/.github/scripts/kernel_checker.py b/.github/scripts/kernel_checker.py
index 3373cd50c..0e8556350 100755
--- a/.github/scripts/kernel_checker.py
+++ b/.github/scripts/kernel_checker.py
@@ -95,7 +95,7 @@ KERNEL_IGNORED_PATTERNS = [
     r'.*IAR/78K0R/*',
     r'.*CCS/MSP430X/*',
     r'.*portable/template/*',
-    r'.*sample_configuration/*'
+    r'.*template_configuration/*'
 ]
 
 KERNEL_THIRD_PARTY_PATTERNS = [
diff --git a/README.md b/README.md
index c6633563f..7a60f3594 100644
--- a/README.md
+++ b/README.md
@@ -124,8 +124,8 @@ See the readme file in the ```./portable``` directory for more information.
 
 - The ```./include``` directory contains the real time kernel header files.
 
-- The ```./sample_configuration``` directory contains a sample `FreeRTOSConfig.h` to help jumpstart a new project.
-See the [FreeRTOSConfig.h](examples/sample_configuration/FreeRTOSConfig.h) file for instructions.
+- The ```./template_configuration``` directory contains a sample `FreeRTOSConfig.h` to help jumpstart a new project.
+See the [FreeRTOSConfig.h](examples/template_configuration/FreeRTOSConfig.h) file for instructions.
 
 ### Code Formatting
 
diff --git a/examples/cmake_example/CMakeLists.txt b/examples/cmake_example/CMakeLists.txt
index 4d13c4c77..bff9317de 100644
--- a/examples/cmake_example/CMakeLists.txt
+++ b/examples/cmake_example/CMakeLists.txt
@@ -9,7 +9,7 @@ add_library(freertos_config INTERFACE)
 
 target_include_directories(freertos_config
     INTERFACE
-    "../sample_configuration"
+    "../template_configuration"
 )
 
 if (DEFINED FREERTOS_SMP_EXAMPLE AND FREERTOS_SMP_EXAMPLE STREQUAL "1")
diff --git a/examples/sample_configuration/FreeRTOSConfig.h b/examples/template_configuration/FreeRTOSConfig.h
similarity index 100%
rename from examples/sample_configuration/FreeRTOSConfig.h
rename to examples/template_configuration/FreeRTOSConfig.h
diff --git a/examples/sample_configuration/readme.md b/examples/template_configuration/readme.md
similarity index 100%
rename from examples/sample_configuration/readme.md
rename to examples/template_configuration/readme.md

From 5bb2b59db4bc92a6fe4c8fde67e535da086f208f Mon Sep 17 00:00:00 2001
From: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Date: Mon, 18 Dec 2023 17:16:22 +0800
Subject: [PATCH 164/424] Update History.txt for v11.0.0 (#926)

* Update History.txt for v11.0.0
---
 History.txt | 114 ++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 114 insertions(+)

diff --git a/History.txt b/History.txt
index d1dba2546..ff27af544 100644
--- a/History.txt
+++ b/History.txt
@@ -1,5 +1,119 @@
 Documentation and download available at https://www.FreeRTOS.org/
 
+Changes between FreeRTOS V10.6.2 and FreeRTOS V11.0.0 released December 18, 2023
+
+    + SMP merged into the mainline:  While FreeRTOS introduced Asymmetric
+      Multiprocessing (AMP) support in 2017, FreeRTOS Version 11.0.0 is the
+      first to merge Symmetric Multiprocessing (SMP) support into the mainline
+      release. SMP enables one instance of the FreeRTOS Kernel to schedule tasks
+      across multiple identical processor cores.  We thank Mike Bruno and Jerry
+      McCarthy of XMOS and, Darian Liang, Sudeep Mohanty and Zim Kalinowski of
+      Espressif Systems for their contributions.
+    + Switch MISRA compliance checking from PC Lint to Coverity, and update from
+      MISRA C:2004 to MISRA C:2012.
+    + Add a template FreeRTOSConfig.h, inclusive of an abbreviated explanation of
+      each configuration item. Application writers can use this template as a
+      starting point to create the FreeRTOSConfig.h file for their application.
+    + Add a template FreeRTOS port which can be used as a starting point for
+      developing a new FreeRTOS port.
+    + Add bounds checking and obfuscation to internal heap block pointers in
+      heap_4.c and heap_5.c to help catch pointer corruptions. The application can
+      enable these checks by setting configENABLE_HEAP_PROTECTOR to 1 in their
+      FreeRTOSConfig.h. We thank @oliverlavery for their contribution.
+    + Update vTaskList and vTaskGetRunTimeStats APIs to replace the use of sprintf
+      with snprintf.
+    + Add trace macros to ports that enable tracing the interaction of ISRs with
+      scheduler events. We thank @conara for their contribution.
+    + Add trace macros that enable tracing of entering and exiting all APIs. We
+      thank @Techcore123 for their contribution.
+    + Add uxTaskBasePriorityGet and uxTaskBasePriorityGetFromISR APIs to get the
+      base priority of a task. The base priority of a task is the priority that
+      was last assigned to the task - which due to priority inheritance, may not
+      be the current priority of the task.
+    + Add pdTICKS_TO_MS macro to convert time in FreeRTOS ticks to time in
+      milliseconds. We thank @Dazza0 for their contribution.
+    + Add default implementations of vApplicationGetIdleTaskMemory and
+      vApplicationGetTimerTaskMemory. The application can enable these default
+      implementations by setting configKERNEL_PROVIDED_STATIC_MEMORY to 1 in their
+      FreeRTOSConfig.h. We thank @mdnr-g for their contribution.
+    + Update vTaskGetInfo to include start and end of the stack whenever both
+      values are available. We thank @vinceburns for their contribution.
+    + Prevent tasks waiting for a notification from being resumed by calls to
+      vTaskResume or vTaskResumeFromISR. We thank @Moral-Hao for their
+      contribution.
+    + Add asserts to validate that the application has correctly installed
+      FreeRTOS handlers for PendSV and SVCall interrupts on Cortex-M devices.
+      We thank @jefftenney for their contribution.
+    + Rename ARM_CA53_64_BIT and ARM_CA53_64_BIT_SRE ports to Arm_AARCH64 and
+      Arm_AARCH64_SRE respectively as these ports are applicable to all AArch64
+      architecture. We thank @urutva for their contribution.
+    + Add CMake support to allow the application writer to select the RISC-V
+      chip extension. We thank @JoeBenczarski for their contribution.
+    + Add CMake support to allow the application writer to build an application
+      with static allocation only. We thank @conara for their contribution.
+    + Make taskYIELD available to unprivileged tasks for ARMv8-M ports.
+    + Update Cortex-M23 ports to not use PSPLIM_NS. We thank @urutva for their
+      contribution.
+    + Update the SysTick setup code for ARMv8-M ports to first configure the clock
+      source and then enable SysTick. This is needed to address a bug in QEMU
+      versions older than 7.0.0, which causes an emulation error if SysTick is
+      enabled without first selecting a valid clock source. We thank @jefftenney
+      for their contribution.
+    + Add the port-optimized task selection algorithm optionally available for
+      ARMv7-M ports to the ARMv8-M ports. We thank @jefftenney for their
+      contribution.
+    + Improve the speed of pvPortMalloc in heap_4.c and heap_5.c by removing
+      unnecessary steps while splitting a large memory block into two. We thank
+      @Moral-Hao for their contribution.
+    + Shorten the critical section in pvPortMalloc in heap_2.c, heap_4.c and
+      heap_5.c by moving the size calculation out of the critical section. We thank
+      @Moral-Hao for their contribution.
+    + Update xTaskNotifyWait and ulTaskNotifyTake to remove the non-deterministic
+      operation of traversing a linked link from a critical section. We thank
+      @karver8 for their contribution.
+    + Fix stack end and stack size computation in POSIX port to meet the stack
+      alignment requirements on MacOS. We thank @tegimeki for their contribution.
+    + Update the vTaskPrioritySet implementation to use the new priority when the
+      task has inherited priority from a mutex it is holding, and the new priority
+      is bigger than the inherited priority. We thank @Moral-Hao for their
+      contribution.
+    + Add stack alignment adjustment if stack grows upwards. We thank @ivq for
+      their contribution.
+    + Fix pxTopOfStack calculation in configINIT_TLS_BLOCK when picolib C is
+      selected as the C library implementation to ensure that
+      pxPortInitialiseStack does not overwrite the data in the TLS block portion
+      of the stack. We thank @bebebib-rs for their contribution.
+    + Fix vPortEndScheduler() for the MSVC port so that the function
+      prvProcessSimulatedInterrupts is not stuck in an infinite loop when the
+      scheduler is stopped. We thank @Ju1He1 for their contribution.
+    + Add the Pull Request (PR) Process explaining the stages a PR goes through.
+
+Changes between FreeRTOS V10.6.1 and FreeRTOS V10.6.2 released November 29, 2023
+
+	+ Add the following improvements to the new MPU wrapper (mpu_wrappers_v2.c)
+	  introduced in version 10.6.0:
+	  - Introduce Access Control List (ACL) feature to allow the application
+	    writer to control an unprivileged task’s access to kernel objects.
+	  - Update the system call entry mechanism to only require one Supervisor
+	    Call (SVC) instruction.
+	  - Wrap parameters for system calls with more than four parameters in a
+	    struct to avoid special handling during system call entry.
+	  - Fix 2 possible integer overflows.
+	  - Convert some asserts to run time parameter checks.
+
+Changes between FreeRTOS V10.6.0 and FreeRTOS V10.6.1 released August 17, 2023
+
+	+ Add runtime parameter checks to functions in mpu_wrappers_v2.c file.
+	  The same checks are already performed in API implementations using
+	  asserts.
+	  We thank the following people for their inputs in these changes:
+	  - Lan Luo, Zixia Liu of School of Computer Science and Technology,
+	    Anhui University of Technology, China.
+	  - Xinwen Fu of Department of Computer Science, University of
+	    Massachusetts Lowell, USA.
+	  - Xinhui Shao, Yumeng Wei, Huaiyu Yan, Zhen Ling of School of
+	    Computer Science and Engineering, Southeast University, China.
+
 Changes between FreeRTOS V10.5.1 and FreeRTOS 10.6.0 released July 13, 2023
 
 	+ Add a new MPU wrapper that places additional restrictions on unprivileged

From 4e7ca2d704f0f21323016d6218b26af72155a144 Mon Sep 17 00:00:00 2001
From: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Date: Thu, 21 Dec 2023 11:43:30 +0530
Subject: [PATCH 165/424] Update History.txt for V11.0.1 (#932)

* Update History for V11.0.1
---
 History.txt | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/History.txt b/History.txt
index ff27af544..a8e5ac7ba 100644
--- a/History.txt
+++ b/History.txt
@@ -1,5 +1,9 @@
 Documentation and download available at https://www.FreeRTOS.org/
 
+Changes between FreeRTOS V11.0.0 and FreeRTOS V11.0.1 released December 21, 2023
+
+    + Updated the SBOM file.
+
 Changes between FreeRTOS V10.6.2 and FreeRTOS V11.0.0 released December 18, 2023
 
     + SMP merged into the mainline:  While FreeRTOS introduced Asymmetric

From ec93432a5974b8edd9391758490c492266bf29df Mon Sep 17 00:00:00 2001
From: Forty-Bot <Forty-Bot@users.noreply.github.com>
Date: Fri, 22 Dec 2023 16:09:55 -0500
Subject: [PATCH 166/424] Fix build with modern GCC (#933)

* GCC: MSP430F449: Add missing attributes

Apparently at some point in the past, GCC (or TI's GCC) used to define
these attributes. Define them ourselves so that we can compile the demo
application.

* GCC: MSP430F449: Make interrupts return void

If a return type of a function is not specified, it defaults to int. Set
the return type of interrupts to void to avoid warnings.

* GCC: MSP430F449: Define portPOINTER_SIZE_TYPE

portPOINTER_SIZE_TYPE defaults to uint32_t if undefined. Define it to
uint16_t, which is correct for this port.
---
 portable/GCC/MSP430F449/port.c      | 8 ++++----
 portable/GCC/MSP430F449/portmacro.h | 6 ++++++
 2 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/portable/GCC/MSP430F449/port.c b/portable/GCC/MSP430F449/port.c
index 0b41665ce..ca72b410b 100644
--- a/portable/GCC/MSP430F449/port.c
+++ b/portable/GCC/MSP430F449/port.c
@@ -296,8 +296,8 @@ static void prvSetupTimerInterrupt( void )
  * the context is saved at the start of vPortYieldFromTick().  The tick
  * count is incremented after the context is saved.
  */
-    interrupt( TIMERA0_VECTOR ) prvTickISR( void ) __attribute__( ( naked ) );
-    interrupt( TIMERA0_VECTOR ) prvTickISR( void )
+    interrupt( TIMERA0_VECTOR ) void prvTickISR( void ) __attribute__( ( naked ) );
+    interrupt( TIMERA0_VECTOR ) void prvTickISR( void )
     {
         /* Save the context of the interrupted task. */
         portSAVE_CONTEXT();
@@ -320,8 +320,8 @@ static void prvSetupTimerInterrupt( void )
  * tick count.  We don't need to switch context, this can only be done by
  * manual calls to taskYIELD();
  */
-    interrupt( TIMERA0_VECTOR ) prvTickISR( void );
-    interrupt( TIMERA0_VECTOR ) prvTickISR( void )
+    interrupt( TIMERA0_VECTOR ) void prvTickISR( void );
+    interrupt( TIMERA0_VECTOR ) void prvTickISR( void )
     {
         xTaskIncrementTick();
     }
diff --git a/portable/GCC/MSP430F449/portmacro.h b/portable/GCC/MSP430F449/portmacro.h
index 445279f5c..f9470f096 100644
--- a/portable/GCC/MSP430F449/portmacro.h
+++ b/portable/GCC/MSP430F449/portmacro.h
@@ -53,6 +53,7 @@
 #define portSHORT         int
 #define portSTACK_TYPE    uint16_t
 #define portBASE_TYPE     short
+#define portPOINTER_SIZE_TYPE uint16_t
 
 typedef portSTACK_TYPE   StackType_t;
 typedef short            BaseType_t;
@@ -118,6 +119,11 @@ extern void vPortYield( void ) __attribute__( ( naked ) );
 #define portBYTE_ALIGNMENT    2
 #define portSTACK_GROWTH      ( -1 )
 #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+
+/* GCC used to define these but doesn't any more */
+#define interrupt(vector) __attribute__((__interrupt__(vector)))
+#define wakeup __attribute__((__wakeup__))
+
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */

From 93380c02a1e9de182952c0a25837a79f4ae9d9c1 Mon Sep 17 00:00:00 2001
From: "dps.lwk" <dps.lwk@gmail.com>
Date: Tue, 26 Dec 2023 09:02:47 +0000
Subject: [PATCH 167/424] RP2040: FreeRTOS-Kernel-Static use
 configKERNEL_PROVIDED_STATIC_MEMORY (#934)

Remove the idle_task_static_memory.c and use the new default implementations
to allows for FreeRTOS-Kernel-Static to be used with configNUMBER_OF_CORES > 1
---
 .../GCC/RP2040/idle_task_static_memory.c      | 52 -------------------
 portable/ThirdParty/GCC/RP2040/library.cmake  |  2 +-
 2 files changed, 1 insertion(+), 53 deletions(-)
 delete mode 100644 portable/ThirdParty/GCC/RP2040/idle_task_static_memory.c

diff --git a/portable/ThirdParty/GCC/RP2040/idle_task_static_memory.c b/portable/ThirdParty/GCC/RP2040/idle_task_static_memory.c
deleted file mode 100644
index aaeec1881..000000000
--- a/portable/ThirdParty/GCC/RP2040/idle_task_static_memory.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
- *
- * SPDX-License-Identifier: MIT AND BSD-3-Clause
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- */
-
-#include "FreeRTOS.h"
-
-void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer,
-                                    StackType_t ** ppxIdleTaskStackBuffer,
-                                    uint32_t * pulIdleTaskStackSize )
-{
-    /* If the buffers to be provided to the Idle task are declared inside this
-     * function then they must be declared static - otherwise they will be allocated on
-     * the stack and so not exists after this function exits. */
-    static StaticTask_t xIdleTaskTCB;
-    static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ];
-
-    /* Pass out a pointer to the StaticTask_t structure in which the Idle task's
-     * state will be stored. */
-    *ppxIdleTaskTCBBuffer = &xIdleTaskTCB;
-
-    /* Pass out the array that will be used as the Idle task's stack. */
-    *ppxIdleTaskStackBuffer = uxIdleTaskStack;
-
-    /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer.
-     * Note that, as the array is necessarily of type StackType_t,
-     * configMINIMAL_STACK_SIZE is specified in words, not bytes. */
-    *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;
-}
diff --git a/portable/ThirdParty/GCC/RP2040/library.cmake b/portable/ThirdParty/GCC/RP2040/library.cmake
index 1db96517a..33968de85 100644
--- a/portable/ThirdParty/GCC/RP2040/library.cmake
+++ b/portable/ThirdParty/GCC/RP2040/library.cmake
@@ -46,9 +46,9 @@ target_compile_definitions(FreeRTOS-Kernel INTERFACE
 add_library(FreeRTOS-Kernel-Static INTERFACE)
 target_compile_definitions(FreeRTOS-Kernel-Static INTERFACE
         configSUPPORT_STATIC_ALLOCATION=1
+        configKERNEL_PROVIDED_STATIC_MEMORY=1
         )
 
-target_sources(FreeRTOS-Kernel-Static INTERFACE ${CMAKE_CURRENT_LIST_DIR}/idle_task_static_memory.c)
 target_link_libraries(FreeRTOS-Kernel-Static INTERFACE FreeRTOS-Kernel)
 
 add_library(FreeRTOS-Kernel-Heap1 INTERFACE)

From 58f0d36e7623db377e589c69114cb9e05c75a161 Mon Sep 17 00:00:00 2001
From: Soren Ptak <ptaksoren@gmail.com>
Date: Tue, 26 Dec 2023 05:36:50 -0500
Subject: [PATCH 168/424] Export MPU Section Attributes (#931)

Export the PRIVILEGED_FUNCTION, PRIVILEGED_DATA, and FREERTOS_SYSTEM_CALL
attributes to make it easier for end users to add their own privileged functions and
system calls.
---
 include/mpu_wrappers.h | 19 ++++---------------
 1 file changed, 4 insertions(+), 15 deletions(-)

diff --git a/include/mpu_wrappers.h b/include/mpu_wrappers.h
index 51e7bcf40..6117bbbcc 100644
--- a/include/mpu_wrappers.h
+++ b/include/mpu_wrappers.h
@@ -229,14 +229,6 @@
             #define xStreamBufferReceiveCompletedFromISR    MPU_xStreamBufferReceiveCompletedFromISR
         #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
-/* Remove the privileged function macro, but keep the PRIVILEGED_DATA
- * macro so applications can place data in privileged access sections
- * (useful when using statically allocated objects). */
-        #define PRIVILEGED_FUNCTION
-        #define PRIVILEGED_DATA    __attribute__( ( section( "privileged_data" ) ) )
-        #define FREERTOS_SYSTEM_CALL
-
-
         #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
 
             #define vGrantAccessToTask( xTask, xTaskToGrantAccess )                        vGrantAccessToKernelObject( ( xTask ), ( int32_t ) ( xTaskToGrantAccess ) )
@@ -265,15 +257,12 @@
 
         #endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
 
-    #else /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
-
-/* Ensure API functions go in the privileged execution section. */
-        #define PRIVILEGED_FUNCTION     __attribute__( ( section( "privileged_functions" ) ) )
-        #define PRIVILEGED_DATA         __attribute__( ( section( "privileged_data" ) ) )
-        #define FREERTOS_SYSTEM_CALL    __attribute__( ( section( "freertos_system_calls" ) ) )
-
     #endif /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
 
+    #define PRIVILEGED_FUNCTION     __attribute__( ( section( "privileged_functions" ) ) )
+    #define PRIVILEGED_DATA         __attribute__( ( section( "privileged_data" ) ) )
+    #define FREERTOS_SYSTEM_CALL    __attribute__( ( section( "freertos_system_calls" ) ) )
+
 #else /* portUSING_MPU_WRAPPERS */
 
     #define PRIVILEGED_FUNCTION

From 5544c7829965d4f098725defa18657c1c2361e07 Mon Sep 17 00:00:00 2001
From: Jeff Tenney <jeff.tenney@gmail.com>
Date: Fri, 29 Dec 2023 12:48:56 -0700
Subject: [PATCH 169/424] Fix build error for MSP430 and Cortex A with IAR
 (#937)

* fix whitespace in asm macros

* Revert formatting ARM_CA5_No_GIC and ARM_CA9
---
 portable/IAR/ARM_CA5_No_GIC/portASM.h | 221 ++++++++++---------------
 portable/IAR/ARM_CA9/portASM.h        | 227 ++++++++++----------------
 portable/IAR/MSP430/portasm.h         |  84 +++++-----
 3 files changed, 217 insertions(+), 315 deletions(-)

diff --git a/portable/IAR/ARM_CA5_No_GIC/portASM.h b/portable/IAR/ARM_CA5_No_GIC/portASM.h
index 85050e523..1a9006df3 100644
--- a/portable/IAR/ARM_CA5_No_GIC/portASM.h
+++ b/portable/IAR/ARM_CA5_No_GIC/portASM.h
@@ -1,158 +1,109 @@
-; /*
-   * ; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
-   * ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
-   * ; *
-   * ; * SPDX-License-Identifier: MIT
-   * ; *
-   * ; * Permission is hereby granted, free of charge, to any person obtaining a copy of
-   * ; * this software and associated documentation files (the "Software"), to deal in
-   * ; * the Software without restriction, including without limitation the rights to
-   * ; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
-   * ; * the Software, and to permit persons to whom the Software is furnished to do so,
-   * ; * subject to the following conditions:
-   * ; *
-   * ; * The above copyright notice and this permission notice shall be included in all
-   * ; * copies or substantial portions of the Software.
-   * ; *
-   * ; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-   * ; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-   * ; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-   * ; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-   * ; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-   * ; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-   * ; *
-   * ; * https://www.FreeRTOS.org
-   * ; * https://github.com/FreeRTOS
-   * ; *
-   * ; */
+;/*
+; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * SPDX-License-Identifier: MIT
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * https://www.FreeRTOS.org
+; * https://github.com/FreeRTOS
+; *
+; */
 
-EXTERN vTaskSwitchContext
-EXTERN ulCriticalNesting
-EXTERN pxCurrentTCB
-EXTERN ulPortTaskHasFPUContext
-EXTERN ulAsmAPIPriorityMask
+    EXTERN  vTaskSwitchContext
+    EXTERN  ulCriticalNesting
+    EXTERN  pxCurrentTCB
+    EXTERN  ulPortTaskHasFPUContext
+    EXTERN  ulAsmAPIPriorityMask
 
 portSAVE_CONTEXT macro
 
-;
-Save the LR and SPSR onto the system mode stack before switching to
-;
-system mode to save the remaining system mode registers
-SRSDB sp !, # SYS_MODE
-      CPS     # SYS_MODE
-      PUSH    {
-    R0 - R12, R14
-}
+    ; Save the LR and SPSR onto the system mode stack before switching to
+    ; system mode to save the remaining system mode registers
+    SRSDB   sp!, #SYS_MODE
+    CPS     #SYS_MODE
+    PUSH    {R0-R12, R14}
 
-;
-Push the critical nesting count
-LDR R2, = ulCriticalNesting
-          LDR R1, [ R2 ]
-PUSH    {
-    R1
-}
+    ; Push the critical nesting count
+    LDR     R2, =ulCriticalNesting
+    LDR     R1, [R2]
+    PUSH    {R1}
 
-;
-Does the task have a floating point context that needs saving ? If
-;
-ulPortTaskHasFPUContext is 0 then no.
-   LDR R2, = ulPortTaskHasFPUContext
-             LDR R3, [ R2 ]
-CMP R3, # 0
-
-;
-Save the floating point context,
-
-if any
-FMRXNE R1, FPSCR
-                        VPUSHNE {
-    D0 - D15
-}
+    ; Does the task have a floating point context that needs saving?  If
+    ; ulPortTaskHasFPUContext is 0 then no.
+    LDR     R2, =ulPortTaskHasFPUContext
+    LDR     R3, [R2]
+    CMP     R3, #0
 
+    ; Save the floating point context, if any
+    FMRXNE  R1,  FPSCR
+    VPUSHNE {D0-D15}
 #if configFPU_D32 == 1
-VPUSHNE {
-    D16 - D31
-}
-#endif; configFPU_D32
-PUSHNE  {
-    R1
-}
+    VPUSHNE {D16-D31}
+#endif ; configFPU_D32
+    PUSHNE  {R1}
 
-;
-Save ulPortTaskHasFPUContext itself
-    PUSH    {
-    R3
-}
+    ; Save ulPortTaskHasFPUContext itself
+    PUSH    {R3}
 
-;
-Save the stack pointer in the TCB
-LDR R0, = pxCurrentTCB
-          LDR R1, [ R0 ]
-STR SP, [ R1 ]
+    ; Save the stack pointer in the TCB
+    LDR     R0, =pxCurrentTCB
+    LDR     R1, [R0]
+    STR     SP, [R1]
 
-endm
+    endm
 
 ; /**********************************************************************/
 
 portRESTORE_CONTEXT macro
 
-;
-Set the SP to point to the stack of the task being restored.
-   LDR R0, = pxCurrentTCB
-             LDR R1, [ R0 ]
-LDR SP, [ R1 ]
+    ; Set the SP to point to the stack of the task being restored.
+    LDR     R0, =pxCurrentTCB
+    LDR     R1, [R0]
+    LDR     SP, [R1]
 
-;
-Is there a floating point context to restore ? If the restored
-;
-ulPortTaskHasFPUContext is zero then no.
-   LDR R0, = ulPortTaskHasFPUContext
-             POP     {
-    R1
-}
-STR R1, [ R0 ]
-CMP R1, # 0
-
-;
-Restore the floating point context,
-
-if any
-                           POPNE   {
-    R0
-}
+    ; Is there a floating point context to restore?  If the restored
+    ; ulPortTaskHasFPUContext is zero then no.
+    LDR     R0, =ulPortTaskHasFPUContext
+    POP     {R1}
+    STR     R1, [R0]
+    CMP     R1, #0
 
+    ; Restore the floating point context, if any
+    POPNE   {R0}
 #if configFPU_D32 == 1
-VPOPNE  {
-    D16 - D31
-}
-#endif; configFPU_D32
-VPOPNE  {
-    D0 - D15
-}
-VMSRNE FPSCR, R0
+    VPOPNE  {D16-D31}
+#endif ; configFPU_D32
+    VPOPNE  {D0-D15}
+    VMSRNE  FPSCR, R0
 
-;
-Restore the critical section nesting depth
-LDR R0, = ulCriticalNesting
-          POP     {
-    R1
-}
-STR R1, [ R0 ]
+    ; Restore the critical section nesting depth
+    LDR     R0, =ulCriticalNesting
+    POP     {R1}
+    STR     R1, [R0]
 
-;
-Restore all system mode registers other than the SP( which is already
-                                                     ;
-                                                     being used )
-POP
-{
-    R0 - R12, R14
-}
+    ; Restore all system mode registers other than the SP (which is already
+    ; being used)
+    POP     {R0-R12, R14}
 
-Return to the task code, loading CPSR on the way.CPSR has the interrupt
-;
-enable bit set appropriately
+    ; Return to the task code, loading CPSR on the way.  CPSR has the interrupt
+    ; enable bit set appropriately for the task about to execute.
+    RFEIA   sp!
 
-for the task about to execute.
-   RFEIA sp !
-
-endm
+    endm
diff --git a/portable/IAR/ARM_CA9/portASM.h b/portable/IAR/ARM_CA9/portASM.h
index 8c21efed5..e6df989da 100644
--- a/portable/IAR/ARM_CA9/portASM.h
+++ b/portable/IAR/ARM_CA9/portASM.h
@@ -1,160 +1,111 @@
-; /*
-   * ; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
-   * ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
-   * ; *
-   * ; * SPDX-License-Identifier: MIT
-   * ; *
-   * ; * Permission is hereby granted, free of charge, to any person obtaining a copy of
-   * ; * this software and associated documentation files (the "Software"), to deal in
-   * ; * the Software without restriction, including without limitation the rights to
-   * ; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
-   * ; * the Software, and to permit persons to whom the Software is furnished to do so,
-   * ; * subject to the following conditions:
-   * ; *
-   * ; * The above copyright notice and this permission notice shall be included in all
-   * ; * copies or substantial portions of the Software.
-   * ; *
-   * ; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-   * ; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-   * ; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-   * ; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-   * ; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-   * ; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-   * ; *
-   * ; * https://www.FreeRTOS.org
-   * ; * https://github.com/FreeRTOS
-   * ; *
-   * ; */
+;/*
+; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * SPDX-License-Identifier: MIT
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * https://www.FreeRTOS.org
+; * https://github.com/FreeRTOS
+; *
+; */
 
-EXTERN vTaskSwitchContext
-EXTERN ulCriticalNesting
-EXTERN pxCurrentTCB
-EXTERN ulPortTaskHasFPUContext
-EXTERN ulAsmAPIPriorityMask
+    EXTERN  vTaskSwitchContext
+    EXTERN  ulCriticalNesting
+    EXTERN  pxCurrentTCB
+    EXTERN  ulPortTaskHasFPUContext
+    EXTERN  ulAsmAPIPriorityMask
 
 portSAVE_CONTEXT macro
 
-;
-Save the LR and SPSR onto the system mode stack before switching to
-;
-system mode to save the remaining system mode registers
-SRSDB sp !, # SYS_MODE
-      CPS     # SYS_MODE
-      PUSH    {
-    R0 - R12, R14
-}
+    ; Save the LR and SPSR onto the system mode stack before switching to
+    ; system mode to save the remaining system mode registers
+    SRSDB   sp!, #SYS_MODE
+    CPS     #SYS_MODE
+    PUSH    {R0-R12, R14}
 
-;
-Push the critical nesting count
-LDR R2, = ulCriticalNesting
-          LDR R1, [ R2 ]
-PUSH    {
-    R1
-}
+    ; Push the critical nesting count
+    LDR     R2, =ulCriticalNesting
+    LDR     R1, [R2]
+    PUSH    {R1}
 
-;
-Does the task have a floating point context that needs saving ? If
-;
-ulPortTaskHasFPUContext is 0 then no.
-   LDR R2, = ulPortTaskHasFPUContext
-             LDR R3, [ R2 ]
-CMP R3, # 0
+    ; Does the task have a floating point context that needs saving?  If
+    ; ulPortTaskHasFPUContext is 0 then no.
+    LDR     R2, =ulPortTaskHasFPUContext
+    LDR     R3, [R2]
+    CMP     R3, #0
 
-;
-Save the floating point context,
+    ; Save the floating point context, if any
+    FMRXNE  R1,  FPSCR
+    VPUSHNE {D0-D15}
+    VPUSHNE {D16-D31}
+    PUSHNE  {R1}
 
-if any
-FMRXNE R1, FPSCR
-                        VPUSHNE {
-    D0 - D15
-}
+    ; Save ulPortTaskHasFPUContext itself
+    PUSH    {R3}
 
-VPUSHNE {
-    D16 - D31
-}
-PUSHNE  {
-    R1
-}
+    ; Save the stack pointer in the TCB
+    LDR     R0, =pxCurrentTCB
+    LDR     R1, [R0]
+    STR     SP, [R1]
 
-;
-Save ulPortTaskHasFPUContext itself
-    PUSH    {
-    R3
-}
-
-;
-Save the stack pointer in the TCB
-LDR R0, = pxCurrentTCB
-          LDR R1, [ R0 ]
-STR SP, [ R1 ]
-
-endm
+    endm
 
 ; /**********************************************************************/
 
 portRESTORE_CONTEXT macro
 
-;
-Set the SP to point to the stack of the task being restored.
-   LDR R0, = pxCurrentTCB
-             LDR R1, [ R0 ]
-LDR SP, [ R1 ]
+    ; Set the SP to point to the stack of the task being restored.
+    LDR     R0, =pxCurrentTCB
+    LDR     R1, [R0]
+    LDR     SP, [R1]
 
-;
-Is there a floating point context to restore ? If the restored
-;
-ulPortTaskHasFPUContext is zero then no.
-   LDR R0, = ulPortTaskHasFPUContext
-             POP     {
-    R1
-}
-STR R1, [ R0 ]
-CMP R1, # 0
+    ; Is there a floating point context to restore?  If the restored
+    ; ulPortTaskHasFPUContext is zero then no.
+    LDR     R0, =ulPortTaskHasFPUContext
+    POP     {R1}
+    STR     R1, [R0]
+    CMP     R1, #0
 
-;
-Restore the floating point context,
+    ; Restore the floating point context, if any
+    POPNE   {R0}
+    VPOPNE  {D16-D31}
+    VPOPNE  {D0-D15}
+    VMSRNE  FPSCR, R0
 
-if any
-                           POPNE   {
-    R0
-}
+    ; Restore the critical section nesting depth
+    LDR     R0, =ulCriticalNesting
+    POP     {R1}
+    STR     R1, [R0]
 
-VPOPNE  {
-    D16 - D31
-}
-VPOPNE  {
-    D0 - D15
-}
-VMSRNE FPSCR, R0
+    ; Ensure the priority mask is correct for the critical nesting depth
+    LDR     R2, =portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS
+    CMP     R1, #0
+    MOVEQ   R4, #255
+    LDRNE   R4, =( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT )
+    STR     R4, [r2]
 
-;
-Restore the critical section nesting depth
-LDR R0, = ulCriticalNesting
-          POP     {
-    R1
-}
-STR R1, [ R0 ]
+    ; Restore all system mode registers other than the SP (which is already
+    ; being used)
+    POP     {R0-R12, R14}
 
-;
-Ensure the priority mask is correct
+    ; Return to the task code, loading CPSR on the way.
+    RFEIA   sp!
 
-for the critical nesting depth
-LDR R2, = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS
-          CMP R1, # 0
-MOVEQ R4, # 255
-LDRNE R4, = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT )
-            STR R4, [ r2 ]
-
-;
-Restore all system mode registers other than the SP( which is already
-                                                     ;
-                                                     being used )
-POP
-{
-    R0 - R12, R14
-}
-
-Return to the task code, loading CPSR on the way.
-   RFEIA sp !
-
-endm
+    endm
diff --git a/portable/IAR/MSP430/portasm.h b/portable/IAR/MSP430/portasm.h
index a9d49b7ff..6b6f0563d 100644
--- a/portable/IAR/MSP430/portasm.h
+++ b/portable/IAR/MSP430/portasm.h
@@ -31,54 +31,54 @@
 
 portSAVE_CONTEXT macro
 
-IMPORT pxCurrentTCB
-IMPORT usCriticalNesting
+    IMPORT pxCurrentTCB
+    IMPORT usCriticalNesting
 
-/* Save the remaining registers. */
-push r4
-push r5
-push r6
-push r7
-push r8
-push r9
-push r10
-push r11
-push r12
-push r13
-push r14
-push r15
-mov.w &usCriticalNesting, r14
-push r14
-       mov.w &pxCurrentTCB, r12
-       mov.w r1, 0 ( r12 )
-endm
+    /* Save the remaining registers. */
+    push   r4
+    push   r5
+    push   r6
+    push   r7
+    push   r8
+    push   r9
+    push   r10
+    push   r11
+    push   r12
+    push   r13
+    push   r14
+    push   r15
+    mov.w  &usCriticalNesting, r14
+    push   r14
+    mov.w  &pxCurrentTCB, r12
+    mov.w  r1, 0(r12)
+    endm
 /*-----------------------------------------------------------*/
 
 portRESTORE_CONTEXT macro
-mov.w & pxCurrentTCB, r12
-mov.w @r12, r1
-pop r15
-mov.w r15, &usCriticalNesting
-pop r15
-pop r14
-pop r13
-pop r12
-pop r11
-pop r10
-pop r9
-pop r8
-pop r7
-pop r6
-pop r5
-pop r4
+    mov.w  &pxCurrentTCB, r12
+    mov.w  @r12, r1
+    pop    r15
+    mov.w  r15, &usCriticalNesting
+    pop    r15
+    pop    r14
+    pop    r13
+    pop    r12
+    pop    r11
+    pop    r10
+    pop    r9
+    pop    r8
+    pop    r7
+    pop    r6
+    pop    r5
+    pop    r4
 
-/* The last thing on the stack will be the status register.
- * Ensure the power down bits are clear ready for the next
- * time this power down register is popped from the stack. */
-bic.w   # 0xf0, 0 ( SP )
+    /* The last thing on the stack will be the status register.
+     * Ensure the power down bits are clear ready for the next
+     * time this power down register is popped from the stack. */
+    bic.w  #0xf0, 0(SP)
 
-reti
-endm
+    reti
+    endm
 /*-----------------------------------------------------------*/
 
 #endif /* ifndef PORTASM_H */

From 75c4044b7e58853065106078b5a1c46df8bef2a6 Mon Sep 17 00:00:00 2001
From: "dps.lwk" <dps.lwk@gmail.com>
Date: Wed, 3 Jan 2024 05:36:04 +0000
Subject: [PATCH 170/424] RP2040: Fix removal of idle_task_static_memory.c
 (#935)

Co-authored-by: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
---
 portable/CMakeLists.txt | 1 -
 1 file changed, 1 deletion(-)

diff --git a/portable/CMakeLists.txt b/portable/CMakeLists.txt
index b84b3018b..dea052d98 100644
--- a/portable/CMakeLists.txt
+++ b/portable/CMakeLists.txt
@@ -81,7 +81,6 @@ add_library(freertos_kernel_port STATIC
 
     # ARMv6-M / Cortex-M0 Raspberry PI RP2040 port for GCC
     $<$<STREQUAL:${FREERTOS_PORT},GCC_RP2040>:
-        ThirdParty/GCC/RP2040/idle_task_static_memory.c
         ThirdParty/GCC/RP2040/port.c>
 
     # ARMv7-M ports for GCC

From be880a1fc8ed4e9bc8110e85bbc827952a13a087 Mon Sep 17 00:00:00 2001
From: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Date: Wed, 3 Jan 2024 15:47:05 +0800
Subject: [PATCH 171/424] Fix portSET_INTERRUPT_MASK_FROM_ISR definition for
 atomic operation (#940)

* Introduce portHAS_NESTED_INTERRUPTS to identify if port has nested interrupt or not.
* Update atomic.h to use portHAS_NESTED_INTERRUPTS instead of portSET_INTERRUPT_MASK_FROM_ISR definition.

---------

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Co-authored-by: ActoryOu <jay2002824@gmail.com>
---
 .github/.cSpellWords.txt                      |  9 ++++++
 include/FreeRTOS.h                            | 28 +++++++++++++++++--
 include/atomic.h                              | 10 ++++++-
 portable/GCC/RISC-V/portmacro.h               |  3 --
 portable/IAR/RISC-V/portmacro.h               |  3 --
 .../ThirdParty/xClang/XCOREAI/portmacro.h     |  3 --
 6 files changed, 44 insertions(+), 12 deletions(-)

diff --git a/.github/.cSpellWords.txt b/.github/.cSpellWords.txt
index 9e0f6560b..49a91c351 100644
--- a/.github/.cSpellWords.txt
+++ b/.github/.cSpellWords.txt
@@ -59,6 +59,7 @@ brhi
 brne
 bswtrg
 BSWTRG
+Bytesto
 CANEN
 CANRX
 CANTX
@@ -89,13 +90,16 @@ CKGR
 CKLO
 CKPS
 CLDIV
+CLEARINTENA
 CLKA
 CLKB
+CLKDIS
 CLKEN
 clki
 CLKI
 CLKP
 CLKS
+CLKSOURCE
 CLKSTA
 CLRB
 CLRF
@@ -690,6 +694,7 @@ Rsvd
 RTAR
 RTCEN
 RTCSC
+RTICTL
 RTIE
 RTIF
 RTIFRC
@@ -713,6 +718,7 @@ RXRSM
 RXSETUP
 RXSUSP
 RXSYN
+RXTDIS
 RXTEN
 RXUBR
 SBYCR
@@ -726,6 +732,7 @@ SECU
 SENDA
 SETB
 SETEN
+SETINTENA
 SETPSW
 SETR
 setvect
@@ -849,6 +856,7 @@ TXVC
 TXVDIS
 UDCP
 uncrustify
+UNDADD
 UNRE
 unsuspended
 URAD
@@ -867,6 +875,7 @@ VDDCORE
 vect
 VECT
 VECTACTIVE
+VECTKEY
 visualisation
 vldmdbeq
 vldmia
diff --git a/include/FreeRTOS.h b/include/FreeRTOS.h
index 23526bb02..6eb498cd2 100644
--- a/include/FreeRTOS.h
+++ b/include/FreeRTOS.h
@@ -509,12 +509,36 @@
 
 #endif /* configUSE_TIMERS */
 
+#ifndef portHAS_NESTED_INTERRUPTS
+    #if defined( portSET_INTERRUPT_MASK_FROM_ISR ) && defined( portCLEAR_INTERRUPT_MASK_FROM_ISR )
+        #define portHAS_NESTED_INTERRUPTS    1
+    #else
+        #define portHAS_NESTED_INTERRUPTS    0
+    #endif
+#endif
+
 #ifndef portSET_INTERRUPT_MASK_FROM_ISR
-    #define portSET_INTERRUPT_MASK_FROM_ISR()    0
+    #if ( portHAS_NESTED_INTERRUPTS == 1 )
+        #error portSET_INTERRUPT_MASK_FROM_ISR must be defined for ports that support nested interrupts (i.e. portHAS_NESTED_INTERRUPTS is set to 1)
+    #else
+        #define portSET_INTERRUPT_MASK_FROM_ISR()    0
+    #endif
+#else
+    #if ( portHAS_NESTED_INTERRUPTS == 0 )
+        #error portSET_INTERRUPT_MASK_FROM_ISR must not be defined for ports that do not support nested interrupts (i.e. portHAS_NESTED_INTERRUPTS is set to 0)
+    #endif
 #endif
 
 #ifndef portCLEAR_INTERRUPT_MASK_FROM_ISR
-    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue )    ( void ) ( uxSavedStatusValue )
+    #if ( portHAS_NESTED_INTERRUPTS == 1 )
+        #error portCLEAR_INTERRUPT_MASK_FROM_ISR must be defined for ports that support nested interrupts  (i.e. portHAS_NESTED_INTERRUPTS is set to 1)
+    #else
+        #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue )    ( void ) ( uxSavedStatusValue )
+    #endif
+#else
+    #if ( portHAS_NESTED_INTERRUPTS == 0 )
+        #error portCLEAR_INTERRUPT_MASK_FROM_ISR must not be defined for ports that do not support nested interrupts (i.e. portHAS_NESTED_INTERRUPTS is set to 0)
+    #endif
 #endif
 
 #ifndef portCLEAN_UP_TCB
diff --git a/include/atomic.h b/include/atomic.h
index 8feb65250..ef487b4ab 100644
--- a/include/atomic.h
+++ b/include/atomic.h
@@ -33,6 +33,14 @@
  * This file implements atomic functions by disabling interrupts globally.
  * Implementations with architecture specific atomic instructions can be
  * provided under each compiler directory.
+ *
+ * The atomic interface can be used in FreeRTOS tasks on all FreeRTOS ports. It
+ * can also be used in Interrupt Service Routines (ISRs) on FreeRTOS ports that
+ * support nested interrupts (i.e. portHAS_NESTED_INTERRUPTS is set to 1). The
+ * atomic interface must not be used in ISRs on FreeRTOS ports that do not
+ * support nested interrupts (i.e. portHAS_NESTED_INTERRUPTS is set to 0)
+ * because ISRs on these ports cannot be interrupted and therefore, do not need
+ * atomics in ISRs.
  */
 
 #ifndef ATOMIC_H
@@ -59,7 +67,7 @@
  * ATOMIC_ENTER_CRITICAL().
  *
  */
-#if defined( portSET_INTERRUPT_MASK_FROM_ISR )
+#if ( portHAS_NESTED_INTERRUPTS == 1 )
 
 /* Nested interrupt scheme is supported in this port. */
     #define ATOMIC_ENTER_CRITICAL() \
diff --git a/portable/GCC/RISC-V/portmacro.h b/portable/GCC/RISC-V/portmacro.h
index e40af6639..05386c3d9 100644
--- a/portable/GCC/RISC-V/portmacro.h
+++ b/portable/GCC/RISC-V/portmacro.h
@@ -111,9 +111,6 @@ extern void vTaskSwitchContext( void );
 /* Critical section management. */
 #define portCRITICAL_NESTING_IN_TCB    0
 
-#define portSET_INTERRUPT_MASK_FROM_ISR()                          0
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue )    ( void ) uxSavedStatusValue
-
 #define portDISABLE_INTERRUPTS()                                   __asm volatile ( "csrc mstatus, 8" )
 #define portENABLE_INTERRUPTS()                                    __asm volatile ( "csrs mstatus, 8" )
 
diff --git a/portable/IAR/RISC-V/portmacro.h b/portable/IAR/RISC-V/portmacro.h
index eba9eb6f2..9a9141c58 100644
--- a/portable/IAR/RISC-V/portmacro.h
+++ b/portable/IAR/RISC-V/portmacro.h
@@ -113,9 +113,6 @@ extern void vTaskSwitchContext( void );
 /* Critical section management. */
 #define portCRITICAL_NESTING_IN_TCB    0
 
-#define portSET_INTERRUPT_MASK_FROM_ISR()                          0
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue )    ( void ) uxSavedStatusValue
-
 #define portDISABLE_INTERRUPTS()                                   __disable_interrupt()
 #define portENABLE_INTERRUPTS()                                    __enable_interrupt()
 
diff --git a/portable/ThirdParty/xClang/XCOREAI/portmacro.h b/portable/ThirdParty/xClang/XCOREAI/portmacro.h
index 06f2b75dc..82da95314 100644
--- a/portable/ThirdParty/xClang/XCOREAI/portmacro.h
+++ b/portable/ThirdParty/xClang/XCOREAI/portmacro.h
@@ -139,9 +139,6 @@
         #define portSET_INTERRUPT_MASK()                  rtos_interrupt_mask_all()
         #define portCLEAR_INTERRUPT_MASK( ulState )       rtos_interrupt_mask_set( ulState )
 
-        #define portSET_INTERRUPT_MASK_FROM_ISR()         ( 0 )
-        #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    ( ( void ) x )
-
 /*
  * Will enable interrupts if ulState is non-zero.
  */

From 4568507507f6d34c20beb2b2f7c462f042f8b3ca Mon Sep 17 00:00:00 2001
From: Eric Jackson <115876528+ericbj29@users.noreply.github.com>
Date: Wed, 3 Jan 2024 11:49:02 -0800
Subject: [PATCH 172/424] Fix documentation for xQueueTakeMutexRecursive (#943)

---
 include/queue.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/queue.h b/include/queue.h
index c6497b5b6..e892ed3d5 100644
--- a/include/queue.h
+++ b/include/queue.h
@@ -1522,8 +1522,8 @@ BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue,
 #endif
 
 /*
- * For internal use only.  Use xSemaphoreTakeMutexRecursive() or
- * xSemaphoreGiveMutexRecursive() instead of calling these functions directly.
+ * For internal use only.  Use xSemaphoreTakeRecursive() or
+ * xSemaphoreGiveRecursive() instead of calling these functions directly.
  */
 BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex,
                                      TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;

From 1947dd2f94419d368316052e92f4bd396bce5f55 Mon Sep 17 00:00:00 2001
From: Gabriele Monaco <32201227+glemco@users.noreply.github.com>
Date: Thu, 4 Jan 2024 22:43:34 +0300
Subject: [PATCH 173/424] Added ability to change task notification index for
 streambuffers (#939)

* Added possibility to change notification index for streambuffers

* Uncrustify: triggered by comment.

* Minor code review suggestions.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: GitHub Action <action@github.com>
Co-authored-by: Aniruddha Kanhere <60444055+AniruddhaKanhere@users.noreply.github.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 include/FreeRTOS.h      |  17 ++++
 include/stream_buffer.h |  51 +++++++++++
 stream_buffer.c         | 185 +++++++++++++++++++++++++---------------
 3 files changed, 183 insertions(+), 70 deletions(-)

diff --git a/include/FreeRTOS.h b/include/FreeRTOS.h
index 6eb498cd2..d7c458df2 100644
--- a/include/FreeRTOS.h
+++ b/include/FreeRTOS.h
@@ -2509,6 +2509,22 @@
     #define traceRETURN_xStreamBufferReceiveCompletedFromISR( xReturn )
 #endif
 
+#ifndef traceENTER_uxStreamBufferGetStreamBufferNotificationIndex
+    #define traceENTER_uxStreamBufferGetStreamBufferNotificationIndex( xStreamBuffer )
+#endif
+
+#ifndef traceRETURN_uxStreamBufferGetStreamBufferNotificationIndex
+    #define traceRETURN_uxStreamBufferGetStreamBufferNotificationIndex( uxNotificationIndex )
+#endif
+
+#ifndef traceENTER_vStreamBufferSetStreamBufferNotificationIndex
+    #define traceENTER_vStreamBufferSetStreamBufferNotificationIndex( xStreamBuffer, uxNotificationIndex )
+#endif
+
+#ifndef traceRETURN_vStreamBufferSetStreamBufferNotificationIndex
+    #define traceRETURN_vStreamBufferSetStreamBufferNotificationIndex()
+#endif
+
 #ifndef traceENTER_uxStreamBufferGetStreamBufferNumber
     #define traceENTER_uxStreamBufferGetStreamBufferNumber( xStreamBuffer )
 #endif
@@ -3271,6 +3287,7 @@ typedef struct xSTATIC_STREAM_BUFFER
     #if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
         void * pvDummy5[ 2 ];
     #endif
+    UBaseType_t uxDummy6;
 } StaticStreamBuffer_t;
 
 /* Message buffers are built on stream buffers. */
diff --git a/include/stream_buffer.h b/include/stream_buffer.h
index 68d12e08f..2ff584eaf 100644
--- a/include/stream_buffer.h
+++ b/include/stream_buffer.h
@@ -911,6 +911,57 @@ BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer
 BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer,
                                                  BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
 
+/**
+ * stream_buffer.h
+ *
+ * @code{c}
+ * UBaseType_t uxStreamBufferGetStreamBufferNotificationIndex( StreamBufferHandle_t xStreamBuffer );
+ * @endcode
+ *
+ * Get the task notification index used for the supplied stream buffer which can
+ * be set using vStreamBufferSetStreamBufferNotificationIndex. If the task
+ * notification index for the stream buffer is not changed using
+ * vStreamBufferSetStreamBufferNotificationIndex, this function returns the
+ * default value (tskDEFAULT_INDEX_TO_NOTIFY).
+ *
+ * @param xStreamBuffer The handle of the stream buffer for which the task
+ * notification index is retrieved.
+ *
+ * @return The task notification index for the stream buffer.
+ *
+ * \defgroup uxStreamBufferGetStreamBufferNotificationIndex uxStreamBufferGetStreamBufferNotificationIndex
+ * \ingroup StreamBufferManagement
+ */
+UBaseType_t uxStreamBufferGetStreamBufferNotificationIndex( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+ * @code{c}
+ * void vStreamBufferSetStreamBufferNotificationIndex ( StreamBuffer_t xStreamBuffer, UBaseType_t uxNotificationIndex );
+ * @endcode
+ *
+ * Set the task notification index used for the supplied stream buffer.
+ * Successive calls to stream buffer APIs (like xStreamBufferSend or
+ * xStreamBufferReceive) for this stream buffer will use this new index for
+ * their task notifications.
+ *
+ * If this function is not called, the default index (tskDEFAULT_INDEX_TO_NOTIFY)
+ * is used for task notifications. It is recommended to call this function
+ * before attempting to send or receive data from the stream buffer to avoid
+ * inconsistencies.
+ *
+ * @param xStreamBuffer The handle of the stream buffer for which the task
+ * notification index is set.
+ *
+ * @param uxNotificationIndex The task notification index to set.
+ *
+ * \defgroup vStreamBufferSetStreamBufferNotificationIndex vStreamBufferSetStreamBufferNotificationIndex
+ * \ingroup StreamBufferManagement
+ */
+void vStreamBufferSetStreamBufferNotificationIndex( StreamBufferHandle_t xStreamBuffer,
+                                                    UBaseType_t uxNotificationIndex ) PRIVILEGED_FUNCTION;
+
 /* Functions below here are not part of the public API. */
 StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes,
                                                  size_t xTriggerLevelBytes,
diff --git a/stream_buffer.c b/stream_buffer.c
index 3ea7baa4b..00306fa04 100644
--- a/stream_buffer.c
+++ b/stream_buffer.c
@@ -56,20 +56,21 @@
  * or #defined the notification macros away, then provide default implementations
  * that uses task notifications. */
 #ifndef sbRECEIVE_COMPLETED
-    #define sbRECEIVE_COMPLETED( pxStreamBuffer )                             \
-    do                                                                        \
-    {                                                                         \
-        vTaskSuspendAll();                                                    \
-        {                                                                     \
-            if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )              \
-            {                                                                 \
-                ( void ) xTaskNotify( ( pxStreamBuffer )->xTaskWaitingToSend, \
-                                      ( uint32_t ) 0,                         \
-                                      eNoAction );                            \
-                ( pxStreamBuffer )->xTaskWaitingToSend = NULL;                \
-            }                                                                 \
-        }                                                                     \
-        ( void ) xTaskResumeAll();                                            \
+    #define sbRECEIVE_COMPLETED( pxStreamBuffer )                                     \
+    do                                                                                \
+    {                                                                                 \
+        vTaskSuspendAll();                                                            \
+        {                                                                             \
+            if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )                      \
+            {                                                                         \
+                ( void ) xTaskNotifyIndexed( ( pxStreamBuffer )->xTaskWaitingToSend,  \
+                                             ( pxStreamBuffer )->uxNotificationIndex, \
+                                             ( uint32_t ) 0,                          \
+                                             eNoAction );                             \
+                ( pxStreamBuffer )->xTaskWaitingToSend = NULL;                        \
+            }                                                                         \
+        }                                                                             \
+        ( void ) xTaskResumeAll();                                                    \
     } while( 0 )
 #endif /* sbRECEIVE_COMPLETED */
 
@@ -93,23 +94,24 @@
 #endif /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */
 
 #ifndef sbRECEIVE_COMPLETED_FROM_ISR
-    #define sbRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer,                            \
-                                          pxHigherPriorityTaskWoken )                \
-    do {                                                                             \
-        UBaseType_t uxSavedInterruptStatus;                                          \
-                                                                                     \
-        uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();                      \
-        {                                                                            \
-            if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )                     \
-            {                                                                        \
-                ( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToSend, \
-                                             ( uint32_t ) 0,                         \
-                                             eNoAction,                              \
-                                             ( pxHigherPriorityTaskWoken ) );        \
-                ( pxStreamBuffer )->xTaskWaitingToSend = NULL;                       \
-            }                                                                        \
-        }                                                                            \
-        taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );                        \
+    #define sbRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer,                                    \
+                                          pxHigherPriorityTaskWoken )                        \
+    do {                                                                                     \
+        UBaseType_t uxSavedInterruptStatus;                                                  \
+                                                                                             \
+        uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();                              \
+        {                                                                                    \
+            if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )                             \
+            {                                                                                \
+                ( void ) xTaskNotifyIndexedFromISR( ( pxStreamBuffer )->xTaskWaitingToSend,  \
+                                                    ( pxStreamBuffer )->uxNotificationIndex, \
+                                                    ( uint32_t ) 0,                          \
+                                                    eNoAction,                               \
+                                                    ( pxHigherPriorityTaskWoken ) );         \
+                ( pxStreamBuffer )->xTaskWaitingToSend = NULL;                               \
+            }                                                                                \
+        }                                                                                    \
+        taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );                                \
     } while( 0 )
 #endif /* sbRECEIVE_COMPLETED_FROM_ISR */
 
@@ -136,17 +138,18 @@
  * implementation that uses task notifications.
  */
 #ifndef sbSEND_COMPLETED
-    #define sbSEND_COMPLETED( pxStreamBuffer )                               \
-    vTaskSuspendAll();                                                       \
-    {                                                                        \
-        if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )              \
-        {                                                                    \
-            ( void ) xTaskNotify( ( pxStreamBuffer )->xTaskWaitingToReceive, \
-                                  ( uint32_t ) 0,                            \
-                                  eNoAction );                               \
-            ( pxStreamBuffer )->xTaskWaitingToReceive = NULL;                \
-        }                                                                    \
-    }                                                                        \
+    #define sbSEND_COMPLETED( pxStreamBuffer )                                      \
+    vTaskSuspendAll();                                                              \
+    {                                                                               \
+        if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )                     \
+        {                                                                           \
+            ( void ) xTaskNotifyIndexed( ( pxStreamBuffer )->xTaskWaitingToReceive, \
+                                         ( pxStreamBuffer )->uxNotificationIndex,   \
+                                         ( uint32_t ) 0,                            \
+                                         eNoAction );                               \
+            ( pxStreamBuffer )->xTaskWaitingToReceive = NULL;                       \
+        }                                                                           \
+    }                                                                               \
     ( void ) xTaskResumeAll()
 #endif /* sbSEND_COMPLETED */
 
@@ -171,22 +174,23 @@
 
 
 #ifndef sbSEND_COMPLETE_FROM_ISR
-    #define sbSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken )       \
-    do {                                                                                \
-        UBaseType_t uxSavedInterruptStatus;                                             \
-                                                                                        \
-        uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();                         \
-        {                                                                               \
-            if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )                     \
-            {                                                                           \
-                ( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToReceive, \
-                                             ( uint32_t ) 0,                            \
-                                             eNoAction,                                 \
-                                             ( pxHigherPriorityTaskWoken ) );           \
-                ( pxStreamBuffer )->xTaskWaitingToReceive = NULL;                       \
-            }                                                                           \
-        }                                                                               \
-        taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );                           \
+    #define sbSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken )              \
+    do {                                                                                       \
+        UBaseType_t uxSavedInterruptStatus;                                                    \
+                                                                                               \
+        uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();                                \
+        {                                                                                      \
+            if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )                            \
+            {                                                                                  \
+                ( void ) xTaskNotifyIndexedFromISR( ( pxStreamBuffer )->xTaskWaitingToReceive, \
+                                                    ( pxStreamBuffer )->uxNotificationIndex,   \
+                                                    ( uint32_t ) 0,                            \
+                                                    eNoAction,                                 \
+                                                    ( pxHigherPriorityTaskWoken ) );           \
+                ( pxStreamBuffer )->xTaskWaitingToReceive = NULL;                              \
+            }                                                                                  \
+        }                                                                                      \
+        taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );                                  \
     } while( 0 )
 #endif /* sbSEND_COMPLETE_FROM_ISR */
 
@@ -237,6 +241,7 @@ typedef struct StreamBufferDef_t
         StreamBufferCallbackFunction_t pxSendCompletedCallback;    /* Optional callback called on send complete. sbSEND_COMPLETED is called if this is NULL. */
         StreamBufferCallbackFunction_t pxReceiveCompletedCallback; /* Optional callback called on receive complete.  sbRECEIVE_COMPLETED is called if this is NULL. */
     #endif
+    UBaseType_t uxNotificationIndex;                               /* The index we are using for notification, by default tskDEFAULT_INDEX_TO_NOTIFY. */
 } StreamBuffer_t;
 
 /*
@@ -790,7 +795,7 @@ size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
                 if( xSpace < xRequiredSpace )
                 {
                     /* Clear notification state as going to wait for space. */
-                    ( void ) xTaskNotifyStateClear( NULL );
+                    ( void ) xTaskNotifyStateClearIndexed( NULL, pxStreamBuffer->uxNotificationIndex );
 
                     /* Should only be one writer. */
                     configASSERT( pxStreamBuffer->xTaskWaitingToSend == NULL );
@@ -805,7 +810,7 @@ size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
             taskEXIT_CRITICAL();
 
             traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer );
-            ( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait );
+            ( void ) xTaskNotifyWaitIndexed( pxStreamBuffer->uxNotificationIndex, ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait );
             pxStreamBuffer->xTaskWaitingToSend = NULL;
         } while( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE );
     }
@@ -1001,7 +1006,7 @@ size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
             if( xBytesAvailable <= xBytesToStoreMessageLength )
             {
                 /* Clear notification state as going to wait for data. */
-                ( void ) xTaskNotifyStateClear( NULL );
+                ( void ) xTaskNotifyStateClearIndexed( NULL, pxStreamBuffer->uxNotificationIndex );
 
                 /* Should only be one reader. */
                 configASSERT( pxStreamBuffer->xTaskWaitingToReceive == NULL );
@@ -1018,7 +1023,7 @@ size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
         {
             /* Wait for data to be available. */
             traceBLOCKING_ON_STREAM_BUFFER_RECEIVE( xStreamBuffer );
-            ( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait );
+            ( void ) xTaskNotifyWaitIndexed( pxStreamBuffer->uxNotificationIndex, ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait );
             pxStreamBuffer->xTaskWaitingToReceive = NULL;
 
             /* Recheck the data available after blocking. */
@@ -1307,10 +1312,11 @@ BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer
     {
         if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )
         {
-            ( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToReceive,
-                                         ( uint32_t ) 0,
-                                         eNoAction,
-                                         pxHigherPriorityTaskWoken );
+            ( void ) xTaskNotifyIndexedFromISR( ( pxStreamBuffer )->xTaskWaitingToReceive,
+                                                ( pxStreamBuffer )->uxNotificationIndex,
+                                                ( uint32_t ) 0,
+                                                eNoAction,
+                                                pxHigherPriorityTaskWoken );
             ( pxStreamBuffer )->xTaskWaitingToReceive = NULL;
             xReturn = pdTRUE;
         }
@@ -1342,10 +1348,11 @@ BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuf
     {
         if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )
         {
-            ( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToSend,
-                                         ( uint32_t ) 0,
-                                         eNoAction,
-                                         pxHigherPriorityTaskWoken );
+            ( void ) xTaskNotifyIndexedFromISR( ( pxStreamBuffer )->xTaskWaitingToSend,
+                                                ( pxStreamBuffer )->uxNotificationIndex,
+                                                ( uint32_t ) 0,
+                                                eNoAction,
+                                                pxHigherPriorityTaskWoken );
             ( pxStreamBuffer )->xTaskWaitingToSend = NULL;
             xReturn = pdTRUE;
         }
@@ -1499,6 +1506,7 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
     pxStreamBuffer->xLength = xBufferSizeBytes;
     pxStreamBuffer->xTriggerLevelBytes = xTriggerLevelBytes;
     pxStreamBuffer->ucFlags = ucFlags;
+    pxStreamBuffer->uxNotificationIndex = tskDEFAULT_INDEX_TO_NOTIFY;
     #if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
     {
         pxStreamBuffer->pxSendCompletedCallback = pxSendCompletedCallback;
@@ -1518,6 +1526,43 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
     }
     #endif /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */
 }
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxStreamBufferGetStreamBufferNotificationIndex( StreamBufferHandle_t xStreamBuffer )
+{
+    StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+
+    traceENTER_uxStreamBufferGetStreamBufferNotificationIndex( xStreamBuffer );
+
+    configASSERT( pxStreamBuffer );
+
+    traceRETURN_uxStreamBufferGetStreamBufferNotificationIndex( pxStreamBuffer->uxNotificationIndex );
+
+    return pxStreamBuffer->uxNotificationIndex;
+}
+/*-----------------------------------------------------------*/
+
+void vStreamBufferSetStreamBufferNotificationIndex( StreamBufferHandle_t xStreamBuffer,
+                                                    UBaseType_t uxNotificationIndex )
+{
+    StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+
+    traceENTER_vStreamBufferSetStreamBufferNotificationIndex( xStreamBuffer, uxNotificationIndex );
+
+    configASSERT( pxStreamBuffer );
+
+    /* There should be no task waiting otherwise we'd never resume them. */
+    configASSERT( pxStreamBuffer->xTaskWaitingToReceive == NULL );
+    configASSERT( pxStreamBuffer->xTaskWaitingToSend == NULL );
+
+    /* Check that the task notification index is valid. */
+    configASSERT( uxNotificationIndex < configTASK_NOTIFICATION_ARRAY_ENTRIES );
+
+    pxStreamBuffer->uxNotificationIndex = uxNotificationIndex;
+
+    traceRETURN_vStreamBufferSetStreamBufferNotificationIndex();
+}
+/*-----------------------------------------------------------*/
 
 #if ( configUSE_TRACE_FACILITY == 1 )
 

From 460e953076b9ceff74fc5583e3da12140ca05690 Mon Sep 17 00:00:00 2001
From: Soren Ptak <ptaksoren@gmail.com>
Date: Mon, 8 Jan 2024 01:28:18 -0500
Subject: [PATCH 174/424] Add new common words to the cSpellWordList.txt (#946)

---
 .github/.cSpellWords.txt | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/.github/.cSpellWords.txt b/.github/.cSpellWords.txt
index 49a91c351..e2149d5e1 100644
--- a/.github/.cSpellWords.txt
+++ b/.github/.cSpellWords.txt
@@ -124,6 +124,7 @@ CODR
 comms
 COMPA
 CONFG
+coremqtt
 CORTUS
 coverity
 Coverity
@@ -156,6 +157,7 @@ crhook
 croutine
 CRTV
 CSAAT
+CSDK
 csrr
 csrs
 csrw
@@ -178,11 +180,15 @@ DATNB
 DATRDY
 DBGU
 DCDIC
+DCMOCK
 DCMR
 Dconfig
 DCOUNT
 decf
 decfsz
+decihours
+Decihours
+DECIHOURS
 DECNT
 DFPU
 DFREERTOS
@@ -315,6 +321,7 @@ FSR
 fwait
 GCACC
 GCTRL
+getpacketid
 getvect
 GIEH
 GIEL
@@ -375,6 +382,7 @@ ISRR
 ISR's
 ISRS
 ISRTICK
+isystem
 ITIF
 ITMC
 ITMK
@@ -517,6 +525,7 @@ MVTACHI
 MVTACLO
 MVTC
 MVTIPL
+mypy
 NCFGR
 NCPHA
 NEBP
@@ -526,6 +535,9 @@ NIOSII
 NIRQ
 NOGIC
 noheap
+nondet
+Nondet
+NONDET
 nostdint
 NPCS
 NRSTL
@@ -639,6 +651,9 @@ PUSHNE
 PUSHW
 pushx
 PWMC
+pylint
+pytest
+pyyaml
 RAMPZ
 RASR
 Rationalised
@@ -855,9 +870,16 @@ TXUBR
 TXVC
 TXVDIS
 UDCP
+UNACKED
 uncrustify
 UNDADD
+unpadded
+Unpadded
+UNPADDED
 UNRE
+UNSUB
+UNSUBACK
+unsubscriptions
 unsuspended
 URAD
 URAT
@@ -873,6 +895,7 @@ utilises
 utilising
 VDDCORE
 vect
+Vect
 VECT
 VECTACTIVE
 VECTKEY

From 94cb87ad30a638dfc22585954494becea19918e6 Mon Sep 17 00:00:00 2001
From: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Date: Tue, 9 Jan 2024 14:03:47 +0800
Subject: [PATCH 175/424] Assign idle task to each core before SMP scheduler
 start (#945)

Co-authored-by: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
---
 tasks.c | 38 ++++++++++++++------------------------
 1 file changed, 14 insertions(+), 24 deletions(-)

diff --git a/tasks.c b/tasks.c
index 279d4bdb3..93e9c02c4 100644
--- a/tasks.c
+++ b/tasks.c
@@ -2108,29 +2108,9 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
                     mtCOVERAGE_TEST_MARKER();
                 }
 
-                if( ( pxNewTCB->uxTaskAttributes & taskATTRIBUTE_IS_IDLE ) != 0U )
-                {
-                    BaseType_t xCoreID;
-
-                    /* Check if a core is free. */
-                    for( xCoreID = ( BaseType_t ) 0; xCoreID < ( BaseType_t ) configNUMBER_OF_CORES; xCoreID++ )
-                    {
-                        if( pxCurrentTCBs[ xCoreID ] == NULL )
-                        {
-                            pxNewTCB->xTaskRunState = xCoreID;
-                            pxCurrentTCBs[ xCoreID ] = pxNewTCB;
-                            break;
-                        }
-                        else
-                        {
-                            mtCOVERAGE_TEST_MARKER();
-                        }
-                    }
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
+                /* All the cores start with idle tasks before the SMP scheduler
+                 * is running. Idle tasks are assigned to cores when they are
+                 * created in prvCreateIdleTasks(). */
             }
 
             uxTaskNumber++;
@@ -3645,7 +3625,17 @@ static BaseType_t prvCreateIdleTasks( void )
         }
         else
         {
-            mtCOVERAGE_TEST_MARKER();
+            #if ( configNUMBER_OF_CORES == 1 )
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+            #else
+            {
+                /* Assign idle task to each core before SMP scheduler is running. */
+                xIdleTaskHandles[ xCoreID ]->xTaskRunState = xCoreID;
+                pxCurrentTCBs[ xCoreID ] = xIdleTaskHandles[ xCoreID ];
+            }
+            #endif
         }
     }
 

From 529de5606e08bedcf7c9a6b0ecbb27cdab73ce18 Mon Sep 17 00:00:00 2001
From: Soren Ptak <ptaksoren@gmail.com>
Date: Wed, 10 Jan 2024 09:58:45 -0500
Subject: [PATCH 176/424] Revert #768 on the XCC/Xtensa portable files (#948)

---
 portable/ThirdParty/XCC/Xtensa/port.c         |  67 ++-
 .../ThirdParty/XCC/Xtensa/portbenchmark.h     |   2 +-
 portable/ThirdParty/XCC/Xtensa/portclib.c     | 326 ++++++------
 portable/ThirdParty/XCC/Xtensa/portmacro.h    | 236 +++++----
 portable/ThirdParty/XCC/Xtensa/porttrace.h    |   6 +-
 portable/ThirdParty/XCC/Xtensa/xtensa_api.h   | 121 +++--
 .../ThirdParty/XCC/Xtensa/xtensa_config.h     | 212 ++++----
 .../ThirdParty/XCC/Xtensa/xtensa_context.h    | 478 +++++++++---------
 portable/ThirdParty/XCC/Xtensa/xtensa_init.c  |  42 +-
 portable/ThirdParty/XCC/Xtensa/xtensa_intr.c  | 141 +++---
 .../XCC/Xtensa/xtensa_overlay_os_hook.c       |  36 +-
 portable/ThirdParty/XCC/Xtensa/xtensa_rtos.h  | 232 ++++-----
 portable/ThirdParty/XCC/Xtensa/xtensa_timer.h | 162 +++---
 13 files changed, 1012 insertions(+), 1049 deletions(-)

diff --git a/portable/ThirdParty/XCC/Xtensa/port.c b/portable/ThirdParty/XCC/Xtensa/port.c
index a95784167..805a78401 100644
--- a/portable/ThirdParty/XCC/Xtensa/port.c
+++ b/portable/ThirdParty/XCC/Xtensa/port.c
@@ -37,39 +37,34 @@
 
 
 /* Defined in portasm.h */
-extern void _frxt_tick_timer_init( void );
+extern void _frxt_tick_timer_init(void);
 
 /* Defined in xtensa_context.S */
-extern void _xt_coproc_init( void );
+extern void _xt_coproc_init(void);
 
 
 /*-----------------------------------------------------------*/
 
 /* We require the address of the pxCurrentTCB variable, but don't want to know
- * any details of its type. */
+any details of its type. */
 typedef void TCB_t;
 extern volatile TCB_t * volatile pxCurrentTCB;
 
-unsigned port_xSchedulerRunning = 0; /* Duplicate of inaccessible xSchedulerRunning; needed at startup to avoid counting nesting */
-unsigned port_interruptNesting = 0;  /* Interrupt nesting level */
+unsigned port_xSchedulerRunning = 0; // Duplicate of inaccessible xSchedulerRunning; needed at startup to avoid counting nesting
+unsigned port_interruptNesting = 0;  // Interrupt nesting level
 
 /*-----------------------------------------------------------*/
 
-/* User exception dispatcher when exiting */
-void _xt_user_exit( void );
+// User exception dispatcher when exiting
+void _xt_user_exit(void);
 
 /*
  * Stack initialization
  */
 #if portUSING_MPU_WRAPPERS
-    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                         TaskFunction_t pxCode,
-                                         void * pvParameters,
-                                         BaseType_t xRunPrivileged )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged )
 #else
-    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                         TaskFunction_t pxCode,
-                                         void * pvParameters )
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
 #endif
 {
     StackType_t * sp;
@@ -134,18 +129,18 @@ void _xt_user_exit( void );
 void vPortEndScheduler( void )
 {
     /* It is unlikely that the Xtensa port will get stopped.  If required simply
-     * disable the tick interrupt here. */
+    disable the tick interrupt here. */
 }
 
 /*-----------------------------------------------------------*/
 
 BaseType_t xPortStartScheduler( void )
 {
-    /* Interrupts are disabled at this point and stack contains PS with enabled interrupts when task context is restored */
+    // Interrupts are disabled at this point and stack contains PS with enabled interrupts when task context is restored
 
     #if XCHAL_CP_NUM > 0
-        /* Initialize co-processor management for tasks. Leave CPENABLE alone. */
-        _xt_coproc_init();
+    /* Initialize co-processor management for tasks. Leave CPENABLE alone. */
+    _xt_coproc_init();
     #endif
 
     /* Init the tick divisor value */
@@ -155,14 +150,14 @@ BaseType_t xPortStartScheduler( void )
     _frxt_tick_timer_init();
 
     #if XT_USE_THREAD_SAFE_CLIB
-        /* Init C library */
-        vPortClibInit();
+    // Init C library
+    vPortClibInit();
     #endif
 
     port_xSchedulerRunning = 1;
 
-    /* Cannot be directly called from C; never returns */
-    __asm__ volatile ( "call0    _frxt_dispatch\n" );
+    // Cannot be directly called from C; never returns
+    __asm__ volatile ("call0    _frxt_dispatch\n");
 
     /* Should not get here. */
     return pdTRUE;
@@ -195,19 +190,19 @@ BaseType_t xPortSysTickHandler( void )
  * Used to set coprocessor area in stack. Current hack is to reuse MPU pointer for coprocessor area.
  */
 #if portUSING_MPU_WRAPPERS
-    void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
-                                    const struct xMEMORY_REGION * const xRegions,
-                                    StackType_t * pxBottomOfStack,
-                                    uint32_t ulStackDepth )
-    {
-        #if XCHAL_CP_NUM > 0
-            xMPUSettings->coproc_area = ( StackType_t * ) ( ( uint32_t ) ( pxBottomOfStack + ulStackDepth - 1 ) );
-            xMPUSettings->coproc_area = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) xMPUSettings->coproc_area ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) );
-            xMPUSettings->coproc_area = ( StackType_t * ) ( ( ( uint32_t ) xMPUSettings->coproc_area - XT_CP_SIZE ) & ~0xf );
+void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
+                                const struct xMEMORY_REGION * const xRegions,
+                                StackType_t * pxBottomOfStack,
+                                uint32_t ulStackDepth )
+{
+    #if XCHAL_CP_NUM > 0
+        xMPUSettings->coproc_area = ( StackType_t * ) ( ( uint32_t ) ( pxBottomOfStack + ulStackDepth - 1 ));
+        xMPUSettings->coproc_area = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) xMPUSettings->coproc_area ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) );
+        xMPUSettings->coproc_area = ( StackType_t * ) ( ( ( uint32_t ) xMPUSettings->coproc_area - XT_CP_SIZE ) & ~0xf );
 
-            /* NOTE: we cannot initialize the coprocessor save area here because FreeRTOS is going to
-             * clear the stack area after we return. This is done in pxPortInitialiseStack().
-             */
-        #endif
-    }
+        /* NOTE: we cannot initialize the coprocessor save area here because FreeRTOS is going to
+         * clear the stack area after we return. This is done in pxPortInitialiseStack().
+         */
+    #endif
+}
 #endif /* if portUSING_MPU_WRAPPERS */
diff --git a/portable/ThirdParty/XCC/Xtensa/portbenchmark.h b/portable/ThirdParty/XCC/Xtensa/portbenchmark.h
index deb1cd0d6..7778dd1a5 100644
--- a/portable/ThirdParty/XCC/Xtensa/portbenchmark.h
+++ b/portable/ThirdParty/XCC/Xtensa/portbenchmark.h
@@ -42,7 +42,7 @@
 #endif
 
 #define portbenchmarkINTERRUPT_DISABLE()
-#define portbenchmarkINTERRUPT_RESTORE( newstate )
+#define portbenchmarkINTERRUPT_RESTORE(newstate)
 #define portbenchmarkIntLatency()
 #define portbenchmarkIntWait()
 #define portbenchmarkReset()
diff --git a/portable/ThirdParty/XCC/Xtensa/portclib.c b/portable/ThirdParty/XCC/Xtensa/portclib.c
index bb415fbbe..3c87d6741 100644
--- a/portable/ThirdParty/XCC/Xtensa/portclib.c
+++ b/portable/ThirdParty/XCC/Xtensa/portclib.c
@@ -31,204 +31,200 @@
 
 #if XT_USE_THREAD_SAFE_CLIB
 
-    #if XSHAL_CLIB == XTHAL_CLIB_XCLIB
+#if XSHAL_CLIB == XTHAL_CLIB_XCLIB
 
-        #include <errno.h>
-        #include <sys/reent.h>
+#include <errno.h>
+#include <sys/reent.h>
 
-        #include "semphr.h"
+#include "semphr.h"
 
-        typedef SemaphoreHandle_t _Rmtx;
+typedef SemaphoreHandle_t       _Rmtx;
 
-/*----------------------------------------------------------------------------- */
-/*  Override this and set to nonzero to enable locking. */
-/*----------------------------------------------------------------------------- */
-        int32_t _xclib_use_mt = 1;
+//-----------------------------------------------------------------------------
+//  Override this and set to nonzero to enable locking.
+//-----------------------------------------------------------------------------
+int32_t _xclib_use_mt = 1;
 
 
-/*----------------------------------------------------------------------------- */
-/*  Init lock. */
-/*----------------------------------------------------------------------------- */
-        void _Mtxinit( _Rmtx * mtx )
-        {
-            *mtx = xSemaphoreCreateRecursiveMutex();
-        }
+//-----------------------------------------------------------------------------
+//  Init lock.
+//-----------------------------------------------------------------------------
+void
+_Mtxinit(_Rmtx * mtx)
+{
+    *mtx = xSemaphoreCreateRecursiveMutex();
+}
 
-/*----------------------------------------------------------------------------- */
-/*  Destroy lock. */
-/*----------------------------------------------------------------------------- */
-        void _Mtxdst( _Rmtx * mtx )
-        {
-            if( ( mtx != NULL ) && ( *mtx != NULL ) )
-            {
-                vSemaphoreDelete( *mtx );
-            }
-        }
+//-----------------------------------------------------------------------------
+//  Destroy lock.
+//-----------------------------------------------------------------------------
+void
+_Mtxdst(_Rmtx * mtx)
+{
+    if ((mtx != NULL) && (*mtx != NULL)) {
+        vSemaphoreDelete(*mtx);
+    }
+}
 
-/*----------------------------------------------------------------------------- */
-/*  Lock. */
-/*----------------------------------------------------------------------------- */
-        void _Mtxlock( _Rmtx * mtx )
-        {
-            if( ( mtx != NULL ) && ( *mtx != NULL ) )
-            {
-                xSemaphoreTakeRecursive( *mtx, portMAX_DELAY );
-            }
-        }
+//-----------------------------------------------------------------------------
+//  Lock.
+//-----------------------------------------------------------------------------
+void
+_Mtxlock(_Rmtx * mtx)
+{
+    if ((mtx != NULL) && (*mtx != NULL)) {
+        xSemaphoreTakeRecursive(*mtx, portMAX_DELAY);
+    }
+}
 
-/*----------------------------------------------------------------------------- */
-/*  Unlock. */
-/*----------------------------------------------------------------------------- */
-        void _Mtxunlock( _Rmtx * mtx )
-        {
-            if( ( mtx != NULL ) && ( *mtx != NULL ) )
-            {
-                xSemaphoreGiveRecursive( *mtx );
-            }
-        }
+//-----------------------------------------------------------------------------
+//  Unlock.
+//-----------------------------------------------------------------------------
+void
+_Mtxunlock(_Rmtx * mtx)
+{
+    if ((mtx != NULL) && (*mtx != NULL)) {
+        xSemaphoreGiveRecursive(*mtx);
+    }
+}
 
-/*----------------------------------------------------------------------------- */
-/*  Called by malloc() to allocate blocks of memory from the heap. */
-/*----------------------------------------------------------------------------- */
-        void * _sbrk_r( struct _reent * reent,
-                        int32_t incr )
-        {
-            extern char _end;
-            extern char _heap_sentry;
-            static char * _heap_sentry_ptr = &_heap_sentry;
-            static char * heap_ptr;
-            char * base;
+//-----------------------------------------------------------------------------
+//  Called by malloc() to allocate blocks of memory from the heap.
+//-----------------------------------------------------------------------------
+void *
+_sbrk_r (struct _reent * reent, int32_t incr)
+{
+    extern char _end;
+    extern char _heap_sentry;
+    static char * _heap_sentry_ptr = &_heap_sentry;
+    static char * heap_ptr;
+    char * base;
 
-            if( !heap_ptr )
-            {
-                heap_ptr = ( char * ) &_end;
-            }
+    if (!heap_ptr)
+        heap_ptr = (char *) &_end;
 
-            base = heap_ptr;
+    base = heap_ptr;
+    if (heap_ptr + incr >= _heap_sentry_ptr) {
+        reent->_errno = ENOMEM;
+        return (char *) -1;
+    }
 
-            if( heap_ptr + incr >= _heap_sentry_ptr )
-            {
-                reent->_errno = ENOMEM;
-                return ( char * ) -1;
-            }
+    heap_ptr += incr;
+    return base;
+}
 
-            heap_ptr += incr;
-            return base;
-        }
+//-----------------------------------------------------------------------------
+//  Global initialization for C library.
+//-----------------------------------------------------------------------------
+void
+vPortClibInit(void)
+{
+}
 
-/*----------------------------------------------------------------------------- */
-/*  Global initialization for C library. */
-/*----------------------------------------------------------------------------- */
-        void vPortClibInit( void )
-        {
-        }
+//-----------------------------------------------------------------------------
+//  Per-thread cleanup stub provided for linking, does nothing.
+//-----------------------------------------------------------------------------
+void
+_reclaim_reent(void * ptr)
+{
+}
 
-/*----------------------------------------------------------------------------- */
-/*  Per-thread cleanup stub provided for linking, does nothing. */
-/*----------------------------------------------------------------------------- */
-        void _reclaim_reent( void * ptr )
-        {
-        }
+#endif /* XSHAL_CLIB == XTHAL_CLIB_XCLIB */
 
-    #endif /* XSHAL_CLIB == XTHAL_CLIB_XCLIB */
+#if XSHAL_CLIB == XTHAL_CLIB_NEWLIB
 
-    #if XSHAL_CLIB == XTHAL_CLIB_NEWLIB
+#include <errno.h>
+#include <malloc.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
 
-        #include <errno.h>
-        #include <malloc.h>
-        #include <stdio.h>
-        #include <stdlib.h>
-        #include <string.h>
+#include "semphr.h"
 
-        #include "semphr.h"
+static SemaphoreHandle_t xClibMutex;
+static uint32_t  ulClibInitDone = 0;
 
-        static SemaphoreHandle_t xClibMutex;
-        static uint32_t ulClibInitDone = 0;
+//-----------------------------------------------------------------------------
+//  Get C library lock.
+//-----------------------------------------------------------------------------
+void
+__malloc_lock(struct _reent * ptr)
+{
+    if (!ulClibInitDone)
+        return;
 
-/*----------------------------------------------------------------------------- */
-/*  Get C library lock. */
-/*----------------------------------------------------------------------------- */
-        void __malloc_lock( struct _reent * ptr )
-        {
-            if( !ulClibInitDone )
-            {
-                return;
-            }
+    xSemaphoreTakeRecursive(xClibMutex, portMAX_DELAY);
+}
 
-            xSemaphoreTakeRecursive( xClibMutex, portMAX_DELAY );
-        }
+//-----------------------------------------------------------------------------
+//  Release C library lock.
+//-----------------------------------------------------------------------------
+void
+__malloc_unlock(struct _reent * ptr)
+{
+    if (!ulClibInitDone)
+        return;
 
-/*----------------------------------------------------------------------------- */
-/*  Release C library lock. */
-/*----------------------------------------------------------------------------- */
-        void __malloc_unlock( struct _reent * ptr )
-        {
-            if( !ulClibInitDone )
-            {
-                return;
-            }
+    xSemaphoreGiveRecursive(xClibMutex);
+}
 
-            xSemaphoreGiveRecursive( xClibMutex );
-        }
-
-/*----------------------------------------------------------------------------- */
-/*  Lock for environment. Since we have only one global lock we can just call */
-/*  the malloc() lock function. */
-/*----------------------------------------------------------------------------- */
-        void __env_lock( struct _reent * ptr )
-        {
-            __malloc_lock( ptr );
-        }
+//-----------------------------------------------------------------------------
+//  Lock for environment. Since we have only one global lock we can just call
+//  the malloc() lock function.
+//-----------------------------------------------------------------------------
+void
+__env_lock(struct _reent * ptr)
+{
+    __malloc_lock(ptr);
+}
 
 
-/*----------------------------------------------------------------------------- */
-/*  Unlock environment. */
-/*----------------------------------------------------------------------------- */
-        void __env_unlock( struct _reent * ptr )
-        {
-            __malloc_unlock( ptr );
-        }
+//-----------------------------------------------------------------------------
+//  Unlock environment.
+//-----------------------------------------------------------------------------
+void
+__env_unlock(struct _reent * ptr)
+{
+    __malloc_unlock(ptr);
+}
 
-/*----------------------------------------------------------------------------- */
-/*  Called by malloc() to allocate blocks of memory from the heap. */
-/*----------------------------------------------------------------------------- */
-        void * _sbrk_r( struct _reent * reent,
-                        int32_t incr )
-        {
-            extern char _end;
-            extern char _heap_sentry;
-            static char * _heap_sentry_ptr = &_heap_sentry;
-            static char * heap_ptr;
-            char * base;
+//-----------------------------------------------------------------------------
+//  Called by malloc() to allocate blocks of memory from the heap.
+//-----------------------------------------------------------------------------
+void *
+_sbrk_r (struct _reent * reent, int32_t incr)
+{
+    extern char _end;
+    extern char _heap_sentry;
+    static char * _heap_sentry_ptr = &_heap_sentry;
+    static char * heap_ptr;
+    char * base;
 
-            if( !heap_ptr )
-            {
-                heap_ptr = ( char * ) &_end;
-            }
+    if (!heap_ptr)
+        heap_ptr = (char *) &_end;
 
-            base = heap_ptr;
+    base = heap_ptr;
+    if (heap_ptr + incr >= _heap_sentry_ptr) {
+        reent->_errno = ENOMEM;
+        return (char *) -1;
+    }
 
-            if( heap_ptr + incr >= _heap_sentry_ptr )
-            {
-                reent->_errno = ENOMEM;
-                return ( char * ) -1;
-            }
+    heap_ptr += incr;
+    return base;
+}
 
-            heap_ptr += incr;
-            return base;
-        }
+//-----------------------------------------------------------------------------
+//  Global initialization for C library.
+//-----------------------------------------------------------------------------
+void
+vPortClibInit(void)
+{
+    configASSERT(!ulClibInitDone);
 
-/*----------------------------------------------------------------------------- */
-/*  Global initialization for C library. */
-/*----------------------------------------------------------------------------- */
-        void vPortClibInit( void )
-        {
-            configASSERT( !ulClibInitDone );
+    xClibMutex = xSemaphoreCreateRecursiveMutex();
+    ulClibInitDone  = 1;
+}
 
-            xClibMutex = xSemaphoreCreateRecursiveMutex();
-            ulClibInitDone = 1;
-        }
-
-    #endif /* XSHAL_CLIB == XTHAL_CLIB_NEWLIB */
+#endif /* XSHAL_CLIB == XTHAL_CLIB_NEWLIB */
 
 #endif /* XT_USE_THREAD_SAFE_CLIB */
diff --git a/portable/ThirdParty/XCC/Xtensa/portmacro.h b/portable/ThirdParty/XCC/Xtensa/portmacro.h
index 21d3e5384..f84e4335e 100644
--- a/portable/ThirdParty/XCC/Xtensa/portmacro.h
+++ b/portable/ThirdParty/XCC/Xtensa/portmacro.h
@@ -38,15 +38,15 @@
 
 #ifndef __ASSEMBLER__
 
-    #include <stdint.h>
+#include <stdint.h>
 
-    #include <xtensa/tie/xt_core.h>
-    #include <xtensa/hal.h>
-    #include <xtensa/config/core.h>
-    #include <xtensa/config/system.h> /* required for XSHAL_CLIB */
-    #include <xtensa/xtruntime.h>
+#include <xtensa/tie/xt_core.h>
+#include <xtensa/hal.h>
+#include <xtensa/config/core.h>
+#include <xtensa/config/system.h>   /* required for XSHAL_CLIB */
+#include <xtensa/xtruntime.h>
 
-/*#include "xtensa_context.h" */
+//#include "xtensa_context.h"
 
 /*-----------------------------------------------------------
  * Port specific definitions.
@@ -60,159 +60,149 @@
 
 /* Type definitions. */
 
-    #define portCHAR          int8_t
-    #define portFLOAT         float
-    #define portDOUBLE        double
-    #define portLONG          int32_t
-    #define portSHORT         int16_t
-    #define portSTACK_TYPE    uint32_t
-    #define portBASE_TYPE     int
+#define portCHAR        int8_t
+#define portFLOAT       float
+#define portDOUBLE      double
+#define portLONG        int32_t
+#define portSHORT       int16_t
+#define portSTACK_TYPE  uint32_t
+#define portBASE_TYPE   int
 
-    typedef portSTACK_TYPE           StackType_t;
-    typedef portBASE_TYPE            BaseType_t;
-    typedef unsigned portBASE_TYPE   UBaseType_t;
+typedef portSTACK_TYPE          StackType_t;
+typedef portBASE_TYPE           BaseType_t;
+typedef unsigned portBASE_TYPE  UBaseType_t;
 
-    #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-        typedef uint16_t             TickType_t;
-        #define portMAX_DELAY    ( TickType_t ) 0xffff
-    #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-        typedef uint32_t             TickType_t;
-        #define portMAX_DELAY    ( TickType_t ) 0xffffffffUL
-    #else
-        #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
-    #endif
+#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    typedef uint16_t TickType_t;
+    #define portMAX_DELAY ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+    typedef uint32_t TickType_t;
+    #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#else
+    #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+#endif
 /*-----------------------------------------------------------*/
 
-/* portbenchmark */
-    #include "portbenchmark.h"
+// portbenchmark
+#include "portbenchmark.h"
 
 /* Critical section management. NW-TODO: replace XTOS_SET_INTLEVEL with more efficient version, if any? */
-/* These cannot be nested. They should be used with a lot of care and cannot be called from interrupt level. */
-    #define portDISABLE_INTERRUPTS()    do { XTOS_SET_INTLEVEL( XCHAL_EXCM_LEVEL ); portbenchmarkINTERRUPT_DISABLE(); } while( 0 )
-    #define portENABLE_INTERRUPTS()     do { portbenchmarkINTERRUPT_RESTORE( 0 ); XTOS_SET_INTLEVEL( 0 ); } while( 0 )
+// These cannot be nested. They should be used with a lot of care and cannot be called from interrupt level.
+#define portDISABLE_INTERRUPTS()      do { XTOS_SET_INTLEVEL(XCHAL_EXCM_LEVEL); portbenchmarkINTERRUPT_DISABLE(); } while (0)
+#define portENABLE_INTERRUPTS()       do { portbenchmarkINTERRUPT_RESTORE(0); XTOS_SET_INTLEVEL(0); } while (0)
 
-/* These can be nested */
-    #define portCRITICAL_NESTING_IN_TCB    1 /* For now, let FreeRTOS' (tasks.c) manage critical nesting */
-    void vTaskEnterCritical( void );
-    void vTaskExitCritical( void );
-    #define portENTER_CRITICAL()    vTaskEnterCritical()
-    #define portEXIT_CRITICAL()     vTaskExitCritical()
+// These can be nested
+#define portCRITICAL_NESTING_IN_TCB 1  // For now, let FreeRTOS' (tasks.c) manage critical nesting
+void vTaskEnterCritical(void);
+void vTaskExitCritical(void);
+#define portENTER_CRITICAL()        vTaskEnterCritical()
+#define portEXIT_CRITICAL()         vTaskExitCritical()
 
-/* Cleaner and preferred solution allows nested interrupts disabling and restoring via local registers or stack. */
-/* They can be called from interrupts too. */
-    static inline unsigned portENTER_CRITICAL_NESTED()
-    {
-        unsigned state = XTOS_SET_INTLEVEL( XCHAL_EXCM_LEVEL );
+// Cleaner and preferred solution allows nested interrupts disabling and restoring via local registers or stack.
+// They can be called from interrupts too.
+static inline unsigned portENTER_CRITICAL_NESTED() { unsigned state = XTOS_SET_INTLEVEL(XCHAL_EXCM_LEVEL); portbenchmarkINTERRUPT_DISABLE(); return state; }
+#define portEXIT_CRITICAL_NESTED(state)   do { portbenchmarkINTERRUPT_RESTORE(state); XTOS_RESTORE_JUST_INTLEVEL(state); } while (0)
 
-        portbenchmarkINTERRUPT_DISABLE();
-        return state;
-    }
-    #define portEXIT_CRITICAL_NESTED( state )             do { portbenchmarkINTERRUPT_RESTORE( state ); XTOS_RESTORE_JUST_INTLEVEL( state ); } while( 0 )
-
-/* These FreeRTOS versions are similar to the nested versions above */
-    #define portSET_INTERRUPT_MASK_FROM_ISR()             portENTER_CRITICAL_NESTED()
-    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( state )    portEXIT_CRITICAL_NESTED( state )
+// These FreeRTOS versions are similar to the nested versions above
+#define portSET_INTERRUPT_MASK_FROM_ISR()            portENTER_CRITICAL_NESTED()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(state)     portEXIT_CRITICAL_NESTED(state)
 
 /*-----------------------------------------------------------*/
 
 /* Architecture specifics. */
-    #define portSTACK_GROWTH      ( -1 )
-    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-    #define portBYTE_ALIGNMENT    4
-    #define portNOP()    XT_NOP()
+#define portSTACK_GROWTH            ( -1 )
+#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT          4
+#define portNOP()                   XT_NOP()
 /*-----------------------------------------------------------*/
 
 /* Fine resolution time */
-    #define portGET_RUN_TIME_COUNTER_VALUE()    xthal_get_ccount()
+#define portGET_RUN_TIME_COUNTER_VALUE()  xthal_get_ccount()
 
 /* Kernel utilities. */
-    void vPortYield( void );
-    void _frxt_setup_switch( void );
-    #define portYIELD()    vPortYield()
-    #define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) \
-    if( ( xHigherPriorityTaskWoken ) != 0 ) {              \
-        _frxt_setup_switch();                              \
+void vPortYield( void );
+void _frxt_setup_switch( void );
+#define portYIELD()       vPortYield()
+#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken )  \
+    if ( ( xHigherPriorityTaskWoken ) != 0 ) {  \
+        _frxt_setup_switch();           \
     }
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
-    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
 
-/* When coprocessors are defined, we to maintain a pointer to coprocessors area. */
-/* We currently use a hack: redefine field xMPU_SETTINGS in TCB block as a structure that can hold: */
-/* MPU wrappers, coprocessor area pointer, trace code structure, and more if needed. */
-/* The field is normally used for memory protection. FreeRTOS should create another general purpose field. */
-    typedef struct
-    {
-        #if XCHAL_CP_NUM > 0
-            volatile StackType_t * coproc_area; /* Pointer to coprocessor save area; MUST BE FIRST */
-        #endif
-
-        #if portUSING_MPU_WRAPPERS
-            /* Define here mpu_settings, which is port dependent */
-            int mpu_setting; /* Just a dummy example here; MPU not ported to Xtensa yet */
-        #endif
-
-        #if configUSE_TRACE_FACILITY_2
-            struct
-            {
-                /* Cf. porttraceStamp() */
-                int taskstamp;      /* Stamp from inside task to see where we are */
-                int taskstampcount; /* A counter usually incremented when we restart the task's loop */
-            } porttrace;
-        #endif
-    } xMPU_SETTINGS;
-
-/* Main hack to use MPU_wrappers even when no MPU is defined (warning: mpu_setting should not be accessed; otherwise move this above xMPU_SETTINGS) */
-    #if ( XCHAL_CP_NUM > 0 || configUSE_TRACE_FACILITY_2 ) && !portUSING_MPU_WRAPPERS /* If MPU wrappers not used, we still need to allocate coproc area */
-        #undef portUSING_MPU_WRAPPERS
-        #define portUSING_MPU_WRAPPERS    1                                           /* Enable it to allocate coproc area */
-        #define MPU_WRAPPERS_H                                                        /* Override mpu_wrapper.h to disable unwanted code */
-        #define PRIVILEGED_FUNCTION
-        #define PRIVILEGED_DATA
+// When coprocessors are defined, we to maintain a pointer to coprocessors area.
+// We currently use a hack: redefine field xMPU_SETTINGS in TCB block as a structure that can hold:
+// MPU wrappers, coprocessor area pointer, trace code structure, and more if needed.
+// The field is normally used for memory protection. FreeRTOS should create another general purpose field.
+typedef struct {
+    #if XCHAL_CP_NUM > 0
+    volatile StackType_t* coproc_area; // Pointer to coprocessor save area; MUST BE FIRST
+    #endif
+
+    #if portUSING_MPU_WRAPPERS
+    // Define here mpu_settings, which is port dependent
+    int mpu_setting; // Just a dummy example here; MPU not ported to Xtensa yet
     #endif
 
-/* porttrace */
     #if configUSE_TRACE_FACILITY_2
-        #include "porttrace.h"
+    struct {
+        // Cf. porttraceStamp()
+        int taskstamp;        /* Stamp from inside task to see where we are */
+        int taskstampcount;   /* A counter usually incremented when we restart the task's loop */
+    } porttrace;
     #endif
+} xMPU_SETTINGS;
 
-/* configASSERT_2 if requested */
-    #if configASSERT_2
-        #include <stdio.h>
-        void exit( int );
-        #define configASSERT( x )    if( !( x ) ) { porttracePrint( -1 ); printf( "\nAssertion failed in %s:%d\n", __FILE__, __LINE__ ); exit( -1 ); }
-    #endif
+// Main hack to use MPU_wrappers even when no MPU is defined (warning: mpu_setting should not be accessed; otherwise move this above xMPU_SETTINGS)
+#if (XCHAL_CP_NUM > 0 || configUSE_TRACE_FACILITY_2) && !portUSING_MPU_WRAPPERS   // If MPU wrappers not used, we still need to allocate coproc area
+    #undef portUSING_MPU_WRAPPERS
+    #define portUSING_MPU_WRAPPERS 1   // Enable it to allocate coproc area
+    #define MPU_WRAPPERS_H             // Override mpu_wrapper.h to disable unwanted code
+    #define PRIVILEGED_FUNCTION
+    #define PRIVILEGED_DATA
+#endif
+
+// porttrace
+#if configUSE_TRACE_FACILITY_2
+#include "porttrace.h"
+#endif
+
+// configASSERT_2 if requested
+#if configASSERT_2
+#include <stdio.h>
+void exit(int);
+#define configASSERT( x )   if (!(x)) { porttracePrint(-1); printf("\nAssertion failed in %s:%d\n", __FILE__, __LINE__); exit(-1); }
+#endif
 
 
 /* C library support -- only XCLIB and NEWLIB are supported. */
 
 /* To enable thread-safe C library support, XT_USE_THREAD_SAFE_CLIB must be
- * defined to be > 0 somewhere above or on the command line. */
+   defined to be > 0 somewhere above or on the command line. */
 
-    #if ( XT_USE_THREAD_SAFE_CLIB > 0u ) && ( XSHAL_CLIB == XTHAL_CLIB_XCLIB )
-        extern void vPortClibInit( void );
-    #endif // XCLIB support
+#if (XT_USE_THREAD_SAFE_CLIB > 0u) && (XSHAL_CLIB == XTHAL_CLIB_XCLIB)
+extern void vPortClibInit(void);
+#endif // XCLIB support
 
-    #if ( XT_USE_THREAD_SAFE_CLIB > 0u ) && ( XSHAL_CLIB == XTHAL_CLIB_NEWLIB )
-        extern void vPortClibInit( void );
+#if (XT_USE_THREAD_SAFE_CLIB > 0u) && (XSHAL_CLIB == XTHAL_CLIB_NEWLIB)
+extern void vPortClibInit(void);
 
-/* This C library cleanup is not currently done by FreeRTOS when deleting a task */
-        #include <stdio.h>
-        #define portCLEAN_UP_TCB( pxTCB )    vPortCleanUpTcbClib( &( ( pxTCB )->xNewLib_reent ) )
-        static inline void vPortCleanUpTcbClib( struct _reent * ptr )
-        {
-            FILE * fp = &( ptr->__sf[ 0 ] );
-            int i;
-
-            for( i = 0; i < 3; ++i, ++fp )
-            {
-                fp->_close = NULL;
-            }
-        }
-    #endif // NEWLIB support
+// This C library cleanup is not currently done by FreeRTOS when deleting a task
+#include <stdio.h>
+#define portCLEAN_UP_TCB(pxTCB)   vPortCleanUpTcbClib(&((pxTCB)->xNewLib_reent))
+static inline void vPortCleanUpTcbClib(struct _reent *ptr)
+{
+    FILE * fp = &(ptr->__sf[0]);
+    int i;
+    for (i = 0; i < 3; ++i, ++fp) {
+        fp->_close = NULL;
+    }
+}
+#endif // NEWLIB support
 
 #endif // __ASSEMBLER__
 
diff --git a/portable/ThirdParty/XCC/Xtensa/porttrace.h b/portable/ThirdParty/XCC/Xtensa/porttrace.h
index 7a2ad1d53..9909ec3af 100644
--- a/portable/ThirdParty/XCC/Xtensa/porttrace.h
+++ b/portable/ThirdParty/XCC/Xtensa/porttrace.h
@@ -1,4 +1,4 @@
-/*
+ /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
@@ -43,7 +43,7 @@
     #error "You need to download the FreeRTOS_trace patch that overwrites this file"
 #endif
 
-#define porttracePrint( nelements )
-#define porttraceStamp( stamp, count_incr )
+#define porttracePrint(nelements)
+#define porttraceStamp(stamp, count_incr)
 
 #endif /* PORTTRACE_H */
diff --git a/portable/ThirdParty/XCC/Xtensa/xtensa_api.h b/portable/ThirdParty/XCC/Xtensa/xtensa_api.h
index bf2834f09..703449f2b 100644
--- a/portable/ThirdParty/XCC/Xtensa/xtensa_api.h
+++ b/portable/ThirdParty/XCC/Xtensa/xtensa_api.h
@@ -1,4 +1,4 @@
-/*
+ /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
@@ -40,90 +40,87 @@
 
 
 /* Typedef for C-callable interrupt handler function */
-typedef void (* xt_handler)( void * );
+typedef void (*xt_handler)(void *);
 
 /* Typedef for C-callable exception handler function */
-typedef void (* xt_exc_handler)( XtExcFrame * );
+typedef void (*xt_exc_handler)(XtExcFrame *);
 
 
 /*
- * -------------------------------------------------------------------------------
- * Call this function to set a handler for the specified exception.
- *
- *  n        - Exception number (type)
- *  f        - Handler function address, NULL to uninstall handler.
- *
- * The handler will be passed a pointer to the exception frame, which is created
- * on the stack of the thread that caused the exception.
- *
- * If the handler returns, the thread context will be restored and the faulting
- * instruction will be retried. Any values in the exception frame that are
- * modified by the handler will be restored as part of the context. For details
- * of the exception frame structure see xtensa_context.h.
- * -------------------------------------------------------------------------------
- */
-extern xt_exc_handler xt_set_exception_handler( int n,
-                                                xt_exc_handler f );
+-------------------------------------------------------------------------------
+  Call this function to set a handler for the specified exception.
+
+    n        - Exception number (type)
+    f        - Handler function address, NULL to uninstall handler.
+
+  The handler will be passed a pointer to the exception frame, which is created
+  on the stack of the thread that caused the exception.
+
+  If the handler returns, the thread context will be restored and the faulting
+  instruction will be retried. Any values in the exception frame that are
+  modified by the handler will be restored as part of the context. For details
+  of the exception frame structure see xtensa_context.h.
+-------------------------------------------------------------------------------
+*/
+extern xt_exc_handler xt_set_exception_handler(int n, xt_exc_handler f);
 
 
 /*
- * -------------------------------------------------------------------------------
- * Call this function to set a handler for the specified interrupt.
- *
- *  n        - Interrupt number.
- *  f        - Handler function address, NULL to uninstall handler.
- *  arg      - Argument to be passed to handler.
- * -------------------------------------------------------------------------------
- */
-extern xt_handler xt_set_interrupt_handler( int n,
-                                            xt_handler f,
-                                            void * arg );
+-------------------------------------------------------------------------------
+  Call this function to set a handler for the specified interrupt.
+
+    n        - Interrupt number.
+    f        - Handler function address, NULL to uninstall handler.
+    arg      - Argument to be passed to handler.
+-------------------------------------------------------------------------------
+*/
+extern xt_handler xt_set_interrupt_handler(int n, xt_handler f, void * arg);
 
 
 /*
- * -------------------------------------------------------------------------------
- * Call this function to enable the specified interrupts.
- *
- *  mask     - Bit mask of interrupts to be enabled.
- *
- * Returns the previous state of the interrupt enables.
- * -------------------------------------------------------------------------------
- */
-extern unsigned int xt_ints_on( unsigned int mask );
+-------------------------------------------------------------------------------
+  Call this function to enable the specified interrupts.
+
+    mask     - Bit mask of interrupts to be enabled.
+
+  Returns the previous state of the interrupt enables.
+-------------------------------------------------------------------------------
+*/
+extern unsigned int xt_ints_on(unsigned int mask);
 
 
 /*
- * -------------------------------------------------------------------------------
- * Call this function to disable the specified interrupts.
- *
- *  mask     - Bit mask of interrupts to be disabled.
- *
- * Returns the previous state of the interrupt enables.
- * -------------------------------------------------------------------------------
- */
-extern unsigned int xt_ints_off( unsigned int mask );
+-------------------------------------------------------------------------------
+  Call this function to disable the specified interrupts.
+
+    mask     - Bit mask of interrupts to be disabled.
+
+  Returns the previous state of the interrupt enables.
+-------------------------------------------------------------------------------
+*/
+extern unsigned int xt_ints_off(unsigned int mask);
 
 
 /*
- * -------------------------------------------------------------------------------
- * Call this function to set the specified (s/w) interrupt.
- * -------------------------------------------------------------------------------
- */
-static inline void xt_set_intset( unsigned int arg )
+-------------------------------------------------------------------------------
+  Call this function to set the specified (s/w) interrupt.
+-------------------------------------------------------------------------------
+*/
+static inline void xt_set_intset(unsigned int arg)
 {
-    xthal_set_intset( arg );
+    xthal_set_intset(arg);
 }
 
 
 /*
- * -------------------------------------------------------------------------------
- * Call this function to clear the specified (s/w or edge-triggered)
- * interrupt.
- * -------------------------------------------------------------------------------
- */
-static inline void xt_set_intclear( unsigned int arg )
+-------------------------------------------------------------------------------
+  Call this function to clear the specified (s/w or edge-triggered)
+  interrupt.
+-------------------------------------------------------------------------------
+*/
+static inline void xt_set_intclear(unsigned int arg)
 {
-    xthal_set_intclear( arg );
+    xthal_set_intclear(arg);
 }
 
 
diff --git a/portable/ThirdParty/XCC/Xtensa/xtensa_config.h b/portable/ThirdParty/XCC/Xtensa/xtensa_config.h
index cf80f8190..a5efcda58 100644
--- a/portable/ThirdParty/XCC/Xtensa/xtensa_config.h
+++ b/portable/ThirdParty/XCC/Xtensa/xtensa_config.h
@@ -1,4 +1,4 @@
-/*
+ /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
@@ -47,139 +47,139 @@
 
 #include <xtensa/hal.h>
 #include <xtensa/config/core.h>
-#include <xtensa/config/system.h> /* required for XSHAL_CLIB */
+#include <xtensa/config/system.h>   /* required for XSHAL_CLIB */
 
 #include "xtensa_context.h"
 
 
 /*-----------------------------------------------------------------------------
- *                                 STACK REQUIREMENTS
- *
- * This section defines the minimum stack size, and the extra space required to
- * be allocated for saving coprocessor state and/or C library state information
- * (if thread safety is enabled for the C library). The sizes are in bytes.
- *
- * Stack sizes for individual tasks should be derived from these minima based on
- * the maximum call depth of the task and the maximum level of interrupt nesting.
- * A minimum stack size is defined by XT_STACK_MIN_SIZE. This minimum is based
- * on the requirement for a task that calls nothing else but can be interrupted.
- * This assumes that interrupt handlers do not call more than a few levels deep.
- * If this is not true, i.e. one or more interrupt handlers make deep calls then
- * the minimum must be increased.
- *
- * If the Xtensa processor configuration includes coprocessors, then space is
- * allocated to save the coprocessor state on the stack.
- *
- * If thread safety is enabled for the C runtime library, (XT_USE_THREAD_SAFE_CLIB
- * is defined) then space is allocated to save the C library context in the TCB.
- *
- * Allocating insufficient stack space is a common source of hard-to-find errors.
- * During development, it is best to enable the FreeRTOS stack checking features.
- *
- * Usage:
- *
- * XT_USE_THREAD_SAFE_CLIB -- Define this to a nonzero value to enable thread-safe
- *                            use of the C library. This will require extra stack
- *                            space to be allocated for tasks that use the C library
- *                            reentrant functions. See below for more information.
- *
- * NOTE: The Xtensa toolchain supports multiple C libraries and not all of them
- * support thread safety. Check your core configuration to see which C library
- * was chosen for your system.
- *
- * XT_STACK_MIN_SIZE       -- The minimum stack size for any task. It is recommended
- *                            that you do not use a stack smaller than this for any
- *                            task. In case you want to use stacks smaller than this
- *                            size, you must verify that the smaller size(s) will work
- *                            under all operating conditions.
- *
- * XT_STACK_EXTRA          -- The amount of extra stack space to allocate for a task
- *                            that does not make C library reentrant calls. Add this
- *                            to the amount of stack space required by the task itself.
- *
- * XT_STACK_EXTRA_CLIB     -- The amount of space to allocate for C library state.
- *
- *  -----------------------------------------------------------------------------*/
+*                                 STACK REQUIREMENTS
+*
+* This section defines the minimum stack size, and the extra space required to
+* be allocated for saving coprocessor state and/or C library state information
+* (if thread safety is enabled for the C library). The sizes are in bytes.
+*
+* Stack sizes for individual tasks should be derived from these minima based on
+* the maximum call depth of the task and the maximum level of interrupt nesting.
+* A minimum stack size is defined by XT_STACK_MIN_SIZE. This minimum is based
+* on the requirement for a task that calls nothing else but can be interrupted.
+* This assumes that interrupt handlers do not call more than a few levels deep.
+* If this is not true, i.e. one or more interrupt handlers make deep calls then
+* the minimum must be increased.
+*
+* If the Xtensa processor configuration includes coprocessors, then space is
+* allocated to save the coprocessor state on the stack.
+*
+* If thread safety is enabled for the C runtime library, (XT_USE_THREAD_SAFE_CLIB
+* is defined) then space is allocated to save the C library context in the TCB.
+*
+* Allocating insufficient stack space is a common source of hard-to-find errors.
+* During development, it is best to enable the FreeRTOS stack checking features.
+*
+* Usage:
+*
+* XT_USE_THREAD_SAFE_CLIB -- Define this to a nonzero value to enable thread-safe
+*                            use of the C library. This will require extra stack
+*                            space to be allocated for tasks that use the C library
+*                            reentrant functions. See below for more information.
+*
+* NOTE: The Xtensa toolchain supports multiple C libraries and not all of them
+* support thread safety. Check your core configuration to see which C library
+* was chosen for your system.
+*
+* XT_STACK_MIN_SIZE       -- The minimum stack size for any task. It is recommended
+*                            that you do not use a stack smaller than this for any
+*                            task. In case you want to use stacks smaller than this
+*                            size, you must verify that the smaller size(s) will work
+*                            under all operating conditions.
+*
+* XT_STACK_EXTRA          -- The amount of extra stack space to allocate for a task
+*                            that does not make C library reentrant calls. Add this
+*                            to the amount of stack space required by the task itself.
+*
+* XT_STACK_EXTRA_CLIB     -- The amount of space to allocate for C library state.
+*
+-----------------------------------------------------------------------------*/
 
 /* Extra space required for interrupt/exception hooks. */
 #ifdef XT_INTEXC_HOOKS
-    #ifdef __XTENSA_CALL0_ABI__
-        #define STK_INTEXC_EXTRA    0x200
-    #else
-        #define STK_INTEXC_EXTRA    0x180
-    #endif
+  #ifdef __XTENSA_CALL0_ABI__
+    #define STK_INTEXC_EXTRA        0x200
+  #else
+    #define STK_INTEXC_EXTRA        0x180
+  #endif
 #else
-    #define STK_INTEXC_EXTRA        0
+  #define STK_INTEXC_EXTRA          0
 #endif
 
 /* Check C library thread safety support and compute size of C library save area.
- * For the supported libraries, we enable thread safety by default, and this can
- * be overridden from the compiler/make command line. */
-#if ( XSHAL_CLIB == XTHAL_CLIB_NEWLIB ) || ( XSHAL_CLIB == XTHAL_CLIB_XCLIB )
-    #ifndef XT_USE_THREAD_SAFE_CLIB
-        #define XT_USE_THREAD_SAFE_CLIB    1
-    #endif
+   For the supported libraries, we enable thread safety by default, and this can
+   be overridden from the compiler/make command line. */
+#if (XSHAL_CLIB == XTHAL_CLIB_NEWLIB) || (XSHAL_CLIB == XTHAL_CLIB_XCLIB)
+  #ifndef XT_USE_THREAD_SAFE_CLIB
+    #define XT_USE_THREAD_SAFE_CLIB         1
+  #endif
 #else
-    #define XT_USE_THREAD_SAFE_CLIB        0
+  #define XT_USE_THREAD_SAFE_CLIB           0
 #endif
 
 #if XT_USE_THREAD_SAFE_CLIB > 0u
-    #if XSHAL_CLIB == XTHAL_CLIB_XCLIB
-        #define XT_HAVE_THREAD_SAFE_CLIB         1
-        #if !defined __ASSEMBLER__
-            #include <sys/reent.h>
-            #define XT_CLIB_CONTEXT_AREA_SIZE    ( ( sizeof( struct _reent ) + 15 ) + ( -16 ) )
-            #define XT_CLIB_GLOBAL_PTR           _reent_ptr
-            #define _REENT_INIT_PTR              _init_reent
-            #define _impure_ptr                  _reent_ptr
+  #if XSHAL_CLIB == XTHAL_CLIB_XCLIB
+    #define XT_HAVE_THREAD_SAFE_CLIB        1
+    #if !defined __ASSEMBLER__
+      #include <sys/reent.h>
+      #define XT_CLIB_CONTEXT_AREA_SIZE     ((sizeof(struct _reent) + 15) + (-16))
+      #define XT_CLIB_GLOBAL_PTR            _reent_ptr
+      #define _REENT_INIT_PTR               _init_reent
+      #define _impure_ptr                   _reent_ptr
 
-            void _reclaim_reent( void * ptr );
-        #endif
-    #elif XSHAL_CLIB == XTHAL_CLIB_NEWLIB
-        #define XT_HAVE_THREAD_SAFE_CLIB         1
-        #if !defined __ASSEMBLER__
-            #include <sys/reent.h>
-            #define XT_CLIB_CONTEXT_AREA_SIZE    ( ( sizeof( struct _reent ) + 15 ) + ( -16 ) )
-            #define XT_CLIB_GLOBAL_PTR           _impure_ptr
-        #endif
-    #else /* if XSHAL_CLIB == XTHAL_CLIB_XCLIB */
-        #define XT_HAVE_THREAD_SAFE_CLIB         0
-        #error The selected C runtime library is not thread safe.
-    #endif /* if XSHAL_CLIB == XTHAL_CLIB_XCLIB */
-#else /* if XT_USE_THREAD_SAFE_CLIB > 0u */
-    #define XT_CLIB_CONTEXT_AREA_SIZE    0
-#endif /* if XT_USE_THREAD_SAFE_CLIB > 0u */
-
-/*------------------------------------------------------------------------------
- *  Extra size -- interrupt frame plus coprocessor save area plus hook space.
- *  NOTE: Make sure XT_INTEXC_HOOKS is undefined unless you really need the hooks.
- *  ------------------------------------------------------------------------------*/
-#ifdef __XTENSA_CALL0_ABI__
-    #define XT_XTRA_SIZE    ( XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x10 + XT_CP_SIZE )
+      void _reclaim_reent(void * ptr);
+    #endif
+  #elif XSHAL_CLIB == XTHAL_CLIB_NEWLIB
+    #define XT_HAVE_THREAD_SAFE_CLIB        1
+    #if !defined __ASSEMBLER__
+      #include <sys/reent.h>
+      #define XT_CLIB_CONTEXT_AREA_SIZE     ((sizeof(struct _reent) + 15) + (-16))
+      #define XT_CLIB_GLOBAL_PTR            _impure_ptr
+    #endif
+  #else
+    #define XT_HAVE_THREAD_SAFE_CLIB        0
+    #error The selected C runtime library is not thread safe.
+  #endif
 #else
-    #define XT_XTRA_SIZE    ( XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x20 + XT_CP_SIZE )
+  #define XT_CLIB_CONTEXT_AREA_SIZE         0
 #endif
 
 /*------------------------------------------------------------------------------
- *  Space allocated for user code -- function calls and local variables.
- *  NOTE: This number can be adjusted to suit your needs. You must verify that the
- *  amount of space you reserve is adequate for the worst-case conditions in your
- *  application.
- *  NOTE: The windowed ABI requires more stack, since space has to be reserved
- *  for spilling register windows.
- *  ------------------------------------------------------------------------------*/
+  Extra size -- interrupt frame plus coprocessor save area plus hook space.
+  NOTE: Make sure XT_INTEXC_HOOKS is undefined unless you really need the hooks.
+------------------------------------------------------------------------------*/
 #ifdef __XTENSA_CALL0_ABI__
-    #define XT_USER_SIZE    0x200
+  #define XT_XTRA_SIZE            (XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x10 + XT_CP_SIZE)
 #else
-    #define XT_USER_SIZE    0x400
+  #define XT_XTRA_SIZE            (XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x20 + XT_CP_SIZE)
+#endif
+
+/*------------------------------------------------------------------------------
+  Space allocated for user code -- function calls and local variables.
+  NOTE: This number can be adjusted to suit your needs. You must verify that the
+  amount of space you reserve is adequate for the worst-case conditions in your
+  application.
+  NOTE: The windowed ABI requires more stack, since space has to be reserved
+  for spilling register windows.
+------------------------------------------------------------------------------*/
+#ifdef __XTENSA_CALL0_ABI__
+  #define XT_USER_SIZE            0x200
+#else
+  #define XT_USER_SIZE            0x400
 #endif
 
 /* Minimum recommended stack size. */
-#define XT_STACK_MIN_SIZE      ( ( XT_XTRA_SIZE + XT_USER_SIZE ) / sizeof( unsigned char ) )
+#define XT_STACK_MIN_SIZE         ((XT_XTRA_SIZE + XT_USER_SIZE) / sizeof(unsigned char))
 
 /* OS overhead with and without C library thread context. */
-#define XT_STACK_EXTRA         ( XT_XTRA_SIZE )
-#define XT_STACK_EXTRA_CLIB    ( XT_XTRA_SIZE + XT_CLIB_CONTEXT_AREA_SIZE )
+#define XT_STACK_EXTRA              (XT_XTRA_SIZE)
+#define XT_STACK_EXTRA_CLIB         (XT_XTRA_SIZE + XT_CLIB_CONTEXT_AREA_SIZE)
 
 
 /* *INDENT-OFF* */
diff --git a/portable/ThirdParty/XCC/Xtensa/xtensa_context.h b/portable/ThirdParty/XCC/Xtensa/xtensa_context.h
index 5d243d3c0..579c62ea2 100644
--- a/portable/ThirdParty/XCC/Xtensa/xtensa_context.h
+++ b/portable/ThirdParty/XCC/Xtensa/xtensa_context.h
@@ -1,4 +1,4 @@
-/*
+ /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
@@ -44,7 +44,7 @@
 #define XTENSA_CONTEXT_H
 
 #ifdef __ASSEMBLER__
-    #include    <xtensa/coreasm.h>
+#include    <xtensa/coreasm.h>
 #endif
 
 #include    <xtensa/config/tie.h>
@@ -53,307 +53,303 @@
 
 
 /* Align a value up to nearest n-byte boundary, where n is a power of 2. */
-#define ALIGNUP( n, val )    ( ( ( val ) + ( n ) - 1 ) & -( n ) )
+#define ALIGNUP(n, val) (((val) + (n)-1) & -(n))
 
 
 /*
- * -------------------------------------------------------------------------------
- * Macros that help define structures for both C and assembler.
- * -------------------------------------------------------------------------------
- */
-#if defined( _ASMLANGUAGE ) || defined( __ASSEMBLER__ )
+-------------------------------------------------------------------------------
+  Macros that help define structures for both C and assembler.
+-------------------------------------------------------------------------------
+*/
+#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__)
 
-    #define STRUCT_BEGIN    .pushsection.text; .struct 0
-    #define STRUCT_FIELD( ctype, size, asname, name )        asname :.space size
-    #define STRUCT_AFIELD( ctype, size, asname, name, n )    asname :.space( size ) *( n )
-    #define STRUCT_END( sname )                              sname ## Size:; .popsection
+#define STRUCT_BEGIN            .pushsection .text; .struct 0
+#define STRUCT_FIELD(ctype,size,asname,name)    asname: .space  size
+#define STRUCT_AFIELD(ctype,size,asname,name,n) asname: .space  (size)*(n)
+#define STRUCT_END(sname)       sname##Size:; .popsection
 
 #else
 
-    #define STRUCT_BEGIN    typedef struct {
-    #define STRUCT_FIELD( ctype, size, asname, name )        ctype name;
-    #define STRUCT_AFIELD( ctype, size, asname, name, n )    ctype name[ n ];
-    #define STRUCT_END( sname ) \
-}                               \
-    sname;
+#define STRUCT_BEGIN            typedef struct {
+#define STRUCT_FIELD(ctype,size,asname,name)    ctype   name;
+#define STRUCT_AFIELD(ctype,size,asname,name,n) ctype   name[n];
+#define STRUCT_END(sname)       } sname;
 
 #endif //_ASMLANGUAGE || __ASSEMBLER__
 
 
 /*
- * -------------------------------------------------------------------------------
- * INTERRUPT/EXCEPTION STACK FRAME FOR A THREAD OR NESTED INTERRUPT
- *
- * A stack frame of this structure is allocated for any interrupt or exception.
- * It goes on the current stack. If the RTOS has a system stack for handling
- * interrupts, every thread stack must allow space for just one interrupt stack
- * frame, then nested interrupt stack frames go on the system stack.
- *
- * The frame includes basic registers (explicit) and "extra" registers introduced
- * by user TIE or the use of the MAC16 option in the user's Xtensa config.
- * The frame size is minimized by omitting regs not applicable to user's config.
- *
- * For Windowed ABI, this stack frame includes the interruptee's base save area,
- * another base save area to manage gcc nested functions, and a little temporary
- * space to help manage the spilling of the register windows.
- * -------------------------------------------------------------------------------
- */
+-------------------------------------------------------------------------------
+  INTERRUPT/EXCEPTION STACK FRAME FOR A THREAD OR NESTED INTERRUPT
 
-STRUCT_BEGIN STRUCT_FIELD( long,
-                           4,
-                           XT_STK_EXIT,
-                           exit )      /* exit point for dispatch */
-STRUCT_FIELD( long, 4, XT_STK_PC, pc ) /* return PC */
-STRUCT_FIELD( long, 4, XT_STK_PS, ps ) /* return PS */
-STRUCT_FIELD( long, 4, XT_STK_A0, a0 )
-STRUCT_FIELD( long, 4, XT_STK_A1, a1 ) /* stack pointer before interrupt */
-STRUCT_FIELD( long, 4, XT_STK_A2, a2 )
-STRUCT_FIELD( long, 4, XT_STK_A3, a3 )
-STRUCT_FIELD( long, 4, XT_STK_A4, a4 )
-STRUCT_FIELD( long, 4, XT_STK_A5, a5 )
-STRUCT_FIELD( long, 4, XT_STK_A6, a6 )
-STRUCT_FIELD( long, 4, XT_STK_A7, a7 )
-STRUCT_FIELD( long, 4, XT_STK_A8, a8 )
-STRUCT_FIELD( long, 4, XT_STK_A9, a9 )
-STRUCT_FIELD( long, 4, XT_STK_A10, a10 )
-STRUCT_FIELD( long, 4, XT_STK_A11, a11 )
-STRUCT_FIELD( long, 4, XT_STK_A12, a12 )
-STRUCT_FIELD( long, 4, XT_STK_A13, a13 )
-STRUCT_FIELD( long, 4, XT_STK_A14, a14 )
-STRUCT_FIELD( long, 4, XT_STK_A15, a15 )
-STRUCT_FIELD( long, 4, XT_STK_SAR, sar )
-STRUCT_FIELD( long, 4, XT_STK_EXCCAUSE, exccause )
-STRUCT_FIELD( long, 4, XT_STK_EXCVADDR, excvaddr )
+  A stack frame of this structure is allocated for any interrupt or exception.
+  It goes on the current stack. If the RTOS has a system stack for handling
+  interrupts, every thread stack must allow space for just one interrupt stack
+  frame, then nested interrupt stack frames go on the system stack.
+
+  The frame includes basic registers (explicit) and "extra" registers introduced
+  by user TIE or the use of the MAC16 option in the user's Xtensa config.
+  The frame size is minimized by omitting regs not applicable to user's config.
+
+  For Windowed ABI, this stack frame includes the interruptee's base save area,
+  another base save area to manage gcc nested functions, and a little temporary
+  space to help manage the spilling of the register windows.
+-------------------------------------------------------------------------------
+*/
+
+STRUCT_BEGIN
+STRUCT_FIELD (long, 4, XT_STK_EXIT,     exit) /* exit point for dispatch */
+STRUCT_FIELD (long, 4, XT_STK_PC,       pc)   /* return PC */
+STRUCT_FIELD (long, 4, XT_STK_PS,       ps)   /* return PS */
+STRUCT_FIELD (long, 4, XT_STK_A0,       a0)
+STRUCT_FIELD (long, 4, XT_STK_A1,       a1)   /* stack pointer before interrupt */
+STRUCT_FIELD (long, 4, XT_STK_A2,       a2)
+STRUCT_FIELD (long, 4, XT_STK_A3,       a3)
+STRUCT_FIELD (long, 4, XT_STK_A4,       a4)
+STRUCT_FIELD (long, 4, XT_STK_A5,       a5)
+STRUCT_FIELD (long, 4, XT_STK_A6,       a6)
+STRUCT_FIELD (long, 4, XT_STK_A7,       a7)
+STRUCT_FIELD (long, 4, XT_STK_A8,       a8)
+STRUCT_FIELD (long, 4, XT_STK_A9,       a9)
+STRUCT_FIELD (long, 4, XT_STK_A10,      a10)
+STRUCT_FIELD (long, 4, XT_STK_A11,      a11)
+STRUCT_FIELD (long, 4, XT_STK_A12,      a12)
+STRUCT_FIELD (long, 4, XT_STK_A13,      a13)
+STRUCT_FIELD (long, 4, XT_STK_A14,      a14)
+STRUCT_FIELD (long, 4, XT_STK_A15,      a15)
+STRUCT_FIELD (long, 4, XT_STK_SAR,      sar)
+STRUCT_FIELD (long, 4, XT_STK_EXCCAUSE, exccause)
+STRUCT_FIELD (long, 4, XT_STK_EXCVADDR, excvaddr)
 #if XCHAL_HAVE_LOOPS
-    STRUCT_FIELD( long, 4, XT_STK_LBEG, lbeg )
-    STRUCT_FIELD( long, 4, XT_STK_LEND, lend )
-    STRUCT_FIELD( long, 4, XT_STK_LCOUNT, lcount )
+STRUCT_FIELD (long, 4, XT_STK_LBEG,   lbeg)
+STRUCT_FIELD (long, 4, XT_STK_LEND,   lend)
+STRUCT_FIELD (long, 4, XT_STK_LCOUNT, lcount)
 #endif
 #ifndef __XTENSA_CALL0_ABI__
 /* Temporary space for saving stuff during window spill */
-    STRUCT_FIELD( long, 4, XT_STK_TMP0, tmp0 )
-    STRUCT_FIELD( long, 4, XT_STK_TMP1, tmp1 )
-    STRUCT_FIELD( long, 4, XT_STK_TMP2, tmp2 )
+STRUCT_FIELD (long, 4, XT_STK_TMP0,   tmp0)
+STRUCT_FIELD (long, 4, XT_STK_TMP1,   tmp1)
+STRUCT_FIELD (long, 4, XT_STK_TMP2,   tmp2)
 #endif
 #ifdef XT_USE_SWPRI
 /* Storage for virtual priority mask */
-    STRUCT_FIELD( long, 4, XT_STK_VPRI, vpri )
+STRUCT_FIELD (long, 4, XT_STK_VPRI,   vpri)
 #endif
 #ifdef XT_USE_OVLY
 /* Storage for overlay state */
-    STRUCT_FIELD( long, 4, XT_STK_OVLY, ovly )
+STRUCT_FIELD (long, 4, XT_STK_OVLY,   ovly)
 #endif
-STRUCT_END( XtExcFrame )
+STRUCT_END(XtExcFrame)
 
-#if defined( _ASMLANGUAGE ) || defined( __ASSEMBLER__ )
-#define XT_STK_NEXT1    XtExcFrameSize
+#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__)
+#define XT_STK_NEXT1      XtExcFrameSize
 #else
-#define XT_STK_NEXT1    sizeof( XtExcFrame )
+#define XT_STK_NEXT1      sizeof(XtExcFrame)
 #endif
 
 /* Allocate extra storage if needed */
 #if XCHAL_EXTRA_SA_SIZE != 0
 
-    #if XCHAL_EXTRA_SA_ALIGN <= 16
-#define XT_STK_EXTRA    ALIGNUP( XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1 )
-    #else
+#if XCHAL_EXTRA_SA_ALIGN <= 16
+#define XT_STK_EXTRA            ALIGNUP(XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1)
+#else
 /* If need more alignment than stack, add space for dynamic alignment */
-#define XT_STK_EXTRA    ( ALIGNUP( XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1 ) + XCHAL_EXTRA_SA_ALIGN )
-    #endif
-#define XT_STK_NEXT2    ( XT_STK_EXTRA + XCHAL_EXTRA_SA_SIZE )
+#define XT_STK_EXTRA            (ALIGNUP(XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1) + XCHAL_EXTRA_SA_ALIGN)
+#endif
+#define XT_STK_NEXT2            (XT_STK_EXTRA + XCHAL_EXTRA_SA_SIZE)
 
 #else
 
-#define XT_STK_NEXT2    XT_STK_NEXT1
+#define XT_STK_NEXT2            XT_STK_NEXT1
 
-#endif /* if XCHAL_EXTRA_SA_SIZE != 0 */
+#endif
 
 /*
- * -------------------------------------------------------------------------------
- * This is the frame size. Add space for 4 registers (interruptee's base save
- * area) and some space for gcc nested functions if any.
- * -------------------------------------------------------------------------------
- */
-#define XT_STK_FRMSZ    ( ALIGNUP( 0x10, XT_STK_NEXT2 ) + 0x20 )
+-------------------------------------------------------------------------------
+  This is the frame size. Add space for 4 registers (interruptee's base save
+  area) and some space for gcc nested functions if any.
+-------------------------------------------------------------------------------
+*/
+#define XT_STK_FRMSZ            (ALIGNUP(0x10, XT_STK_NEXT2) + 0x20)
 
 
 /*
- * -------------------------------------------------------------------------------
- * SOLICITED STACK FRAME FOR A THREAD
- *
- * A stack frame of this structure is allocated whenever a thread enters the
- * RTOS kernel intentionally (and synchronously) to submit to thread scheduling.
- * It goes on the current thread's stack.
- *
- * The solicited frame only includes registers that are required to be preserved
- * by the callee according to the compiler's ABI conventions, some space to save
- * the return address for returning to the caller, and the caller's PS register.
- *
- * For Windowed ABI, this stack frame includes the caller's base save area.
- *
- * Note on XT_SOL_EXIT field:
- *    It is necessary to distinguish a solicited from an interrupt stack frame.
- *    This field corresponds to XT_STK_EXIT in the interrupt stack frame and is
- *    always at the same offset (0). It can be written with a code (usually 0)
- *    to distinguish a solicted frame from an interrupt frame. An RTOS port may
- *    opt to ignore this field if it has another way of distinguishing frames.
- * -------------------------------------------------------------------------------
- */
+-------------------------------------------------------------------------------
+  SOLICITED STACK FRAME FOR A THREAD
+
+  A stack frame of this structure is allocated whenever a thread enters the
+  RTOS kernel intentionally (and synchronously) to submit to thread scheduling.
+  It goes on the current thread's stack.
+
+  The solicited frame only includes registers that are required to be preserved
+  by the callee according to the compiler's ABI conventions, some space to save
+  the return address for returning to the caller, and the caller's PS register.
+
+  For Windowed ABI, this stack frame includes the caller's base save area.
+
+  Note on XT_SOL_EXIT field:
+      It is necessary to distinguish a solicited from an interrupt stack frame.
+      This field corresponds to XT_STK_EXIT in the interrupt stack frame and is
+      always at the same offset (0). It can be written with a code (usually 0)
+      to distinguish a solicted frame from an interrupt frame. An RTOS port may
+      opt to ignore this field if it has another way of distinguishing frames.
+-------------------------------------------------------------------------------
+*/
 
 STRUCT_BEGIN
 #ifdef __XTENSA_CALL0_ABI__
-    STRUCT_FIELD( long, 4, XT_SOL_EXIT, exit )
-    STRUCT_FIELD( long, 4, XT_SOL_PC, pc )
-    STRUCT_FIELD( long, 4, XT_SOL_PS, ps )
-    STRUCT_FIELD( long, 4, XT_SOL_NEXT, next )
-    STRUCT_FIELD( long, 4, XT_SOL_A12, a12 ) /* should be on 16-byte alignment */
-    STRUCT_FIELD( long, 4, XT_SOL_A13, a13 )
-    STRUCT_FIELD( long, 4, XT_SOL_A14, a14 )
-    STRUCT_FIELD( long, 4, XT_SOL_A15, a15 )
+STRUCT_FIELD (long, 4, XT_SOL_EXIT, exit)
+STRUCT_FIELD (long, 4, XT_SOL_PC,   pc)
+STRUCT_FIELD (long, 4, XT_SOL_PS,   ps)
+STRUCT_FIELD (long, 4, XT_SOL_NEXT, next)
+STRUCT_FIELD (long, 4, XT_SOL_A12,  a12)    /* should be on 16-byte alignment */
+STRUCT_FIELD (long, 4, XT_SOL_A13,  a13)
+STRUCT_FIELD (long, 4, XT_SOL_A14,  a14)
+STRUCT_FIELD (long, 4, XT_SOL_A15,  a15)
 #else
-    STRUCT_FIELD( long, 4, XT_SOL_EXIT, exit )
-    STRUCT_FIELD( long, 4, XT_SOL_PC, pc )
-    STRUCT_FIELD( long, 4, XT_SOL_PS, ps )
-    STRUCT_FIELD( long, 4, XT_SOL_NEXT, next )
-    STRUCT_FIELD( long, 4, XT_SOL_A0, a0 ) /* should be on 16-byte alignment */
-    STRUCT_FIELD( long, 4, XT_SOL_A1, a1 )
-    STRUCT_FIELD( long, 4, XT_SOL_A2, a2 )
-    STRUCT_FIELD( long, 4, XT_SOL_A3, a3 )
-#endif /* ifdef __XTENSA_CALL0_ABI__ */
-STRUCT_END( XtSolFrame )
+STRUCT_FIELD (long, 4, XT_SOL_EXIT, exit)
+STRUCT_FIELD (long, 4, XT_SOL_PC,   pc)
+STRUCT_FIELD (long, 4, XT_SOL_PS,   ps)
+STRUCT_FIELD (long, 4, XT_SOL_NEXT, next)
+STRUCT_FIELD (long, 4, XT_SOL_A0,   a0)    /* should be on 16-byte alignment */
+STRUCT_FIELD (long, 4, XT_SOL_A1,   a1)
+STRUCT_FIELD (long, 4, XT_SOL_A2,   a2)
+STRUCT_FIELD (long, 4, XT_SOL_A3,   a3)
+#endif
+STRUCT_END(XtSolFrame)
 
 /* Size of solicited stack frame */
-#define XT_SOL_FRMSZ    ALIGNUP( 0x10, XtSolFrameSize )
+#define XT_SOL_FRMSZ            ALIGNUP(0x10, XtSolFrameSize)
 
 
 /*
- * -------------------------------------------------------------------------------
- * CO-PROCESSOR STATE SAVE AREA FOR A THREAD
- *
- * The RTOS must provide an area per thread to save the state of co-processors
- * when that thread does not have control. Co-processors are context-switched
- * lazily (on demand) only when a new thread uses a co-processor instruction,
- * otherwise a thread retains ownership of the co-processor even when it loses
- * control of the processor. An Xtensa co-processor exception is triggered when
- * any co-processor instruction is executed by a thread that is not the owner,
- * and the context switch of that co-processor is then peformed by the handler.
- * Ownership represents which thread's state is currently in the co-processor.
- *
- * Co-processors may not be used by interrupt or exception handlers. If an
- * co-processor instruction is executed by an interrupt or exception handler,
- * the co-processor exception handler will trigger a kernel panic and freeze.
- * This restriction is introduced to reduce the overhead of saving and restoring
- * co-processor state (which can be quite large) and in particular remove that
- * overhead from interrupt handlers.
- *
- * The co-processor state save area may be in any convenient per-thread location
- * such as in the thread control block or above the thread stack area. It need
- * not be in the interrupt stack frame since interrupts don't use co-processors.
- *
- * Along with the save area for each co-processor, two bitmasks with flags per
- * co-processor (laid out as in the CPENABLE reg) help manage context-switching
- * co-processors as efficiently as possible:
- *
- * XT_CPENABLE
- *  The contents of a non-running thread's CPENABLE register.
- *  It represents the co-processors owned (and whose state is still needed)
- *  by the thread. When a thread is preempted, its CPENABLE is saved here.
- *  When a thread solicits a context-swtich, its CPENABLE is cleared - the
- *  compiler has saved the (caller-saved) co-proc state if it needs to.
- *  When a non-running thread loses ownership of a CP, its bit is cleared.
- *  When a thread runs, it's XT_CPENABLE is loaded into the CPENABLE reg.
- *  Avoids co-processor exceptions when no change of ownership is needed.
- *
- * XT_CPSTORED
- *  A bitmask with the same layout as CPENABLE, a bit per co-processor.
- *  Indicates whether the state of each co-processor is saved in the state
- *  save area. When a thread enters the kernel, only the state of co-procs
- *  still enabled in CPENABLE is saved. When the co-processor exception
- *  handler assigns ownership of a co-processor to a thread, it restores
- *  the saved state only if this bit is set, and clears this bit.
- *
- * XT_CP_CS_ST
- *  A bitmask with the same layout as CPENABLE, a bit per co-processor.
- *  Indicates whether callee-saved state is saved in the state save area.
- *  Callee-saved state is saved by itself on a solicited context switch,
- *  and restored when needed by the coprocessor exception handler.
- *  Unsolicited switches will cause the entire coprocessor to be saved
- *  when necessary.
- *
- * XT_CP_ASA
- *  Pointer to the aligned save area.  Allows it to be aligned more than
- *  the overall save area (which might only be stack-aligned or TCB-aligned).
- *  Especially relevant for Xtensa cores configured with a very large data
- *  path that requires alignment greater than 16 bytes (ABI stack alignment).
- * -------------------------------------------------------------------------------
- */
+-------------------------------------------------------------------------------
+  CO-PROCESSOR STATE SAVE AREA FOR A THREAD
+
+  The RTOS must provide an area per thread to save the state of co-processors
+  when that thread does not have control. Co-processors are context-switched
+  lazily (on demand) only when a new thread uses a co-processor instruction,
+  otherwise a thread retains ownership of the co-processor even when it loses
+  control of the processor. An Xtensa co-processor exception is triggered when
+  any co-processor instruction is executed by a thread that is not the owner,
+  and the context switch of that co-processor is then peformed by the handler.
+  Ownership represents which thread's state is currently in the co-processor.
+
+  Co-processors may not be used by interrupt or exception handlers. If an
+  co-processor instruction is executed by an interrupt or exception handler,
+  the co-processor exception handler will trigger a kernel panic and freeze.
+  This restriction is introduced to reduce the overhead of saving and restoring
+  co-processor state (which can be quite large) and in particular remove that
+  overhead from interrupt handlers.
+
+  The co-processor state save area may be in any convenient per-thread location
+  such as in the thread control block or above the thread stack area. It need
+  not be in the interrupt stack frame since interrupts don't use co-processors.
+
+  Along with the save area for each co-processor, two bitmasks with flags per
+  co-processor (laid out as in the CPENABLE reg) help manage context-switching
+  co-processors as efficiently as possible:
+
+  XT_CPENABLE
+    The contents of a non-running thread's CPENABLE register.
+    It represents the co-processors owned (and whose state is still needed)
+    by the thread. When a thread is preempted, its CPENABLE is saved here.
+    When a thread solicits a context-swtich, its CPENABLE is cleared - the
+    compiler has saved the (caller-saved) co-proc state if it needs to.
+    When a non-running thread loses ownership of a CP, its bit is cleared.
+    When a thread runs, it's XT_CPENABLE is loaded into the CPENABLE reg.
+    Avoids co-processor exceptions when no change of ownership is needed.
+
+  XT_CPSTORED
+    A bitmask with the same layout as CPENABLE, a bit per co-processor.
+    Indicates whether the state of each co-processor is saved in the state
+    save area. When a thread enters the kernel, only the state of co-procs
+    still enabled in CPENABLE is saved. When the co-processor exception
+    handler assigns ownership of a co-processor to a thread, it restores
+    the saved state only if this bit is set, and clears this bit.
+
+  XT_CP_CS_ST
+    A bitmask with the same layout as CPENABLE, a bit per co-processor.
+    Indicates whether callee-saved state is saved in the state save area.
+    Callee-saved state is saved by itself on a solicited context switch,
+    and restored when needed by the coprocessor exception handler.
+    Unsolicited switches will cause the entire coprocessor to be saved
+    when necessary.
+
+  XT_CP_ASA
+    Pointer to the aligned save area.  Allows it to be aligned more than
+    the overall save area (which might only be stack-aligned or TCB-aligned).
+    Especially relevant for Xtensa cores configured with a very large data
+    path that requires alignment greater than 16 bytes (ABI stack alignment).
+-------------------------------------------------------------------------------
+*/
 
 #if XCHAL_CP_NUM > 0
 
 /*  Offsets of each coprocessor save area within the 'aligned save area':  */
-#define XT_CP0_SA        0
-#define XT_CP1_SA        ALIGNUP( XCHAL_CP1_SA_ALIGN, XT_CP0_SA + XCHAL_CP0_SA_SIZE )
-#define XT_CP2_SA        ALIGNUP( XCHAL_CP2_SA_ALIGN, XT_CP1_SA + XCHAL_CP1_SA_SIZE )
-#define XT_CP3_SA        ALIGNUP( XCHAL_CP3_SA_ALIGN, XT_CP2_SA + XCHAL_CP2_SA_SIZE )
-#define XT_CP4_SA        ALIGNUP( XCHAL_CP4_SA_ALIGN, XT_CP3_SA + XCHAL_CP3_SA_SIZE )
-#define XT_CP5_SA        ALIGNUP( XCHAL_CP5_SA_ALIGN, XT_CP4_SA + XCHAL_CP4_SA_SIZE )
-#define XT_CP6_SA        ALIGNUP( XCHAL_CP6_SA_ALIGN, XT_CP5_SA + XCHAL_CP5_SA_SIZE )
-#define XT_CP7_SA        ALIGNUP( XCHAL_CP7_SA_ALIGN, XT_CP6_SA + XCHAL_CP6_SA_SIZE )
-#define XT_CP_SA_SIZE    ALIGNUP( 16, XT_CP7_SA + XCHAL_CP7_SA_SIZE )
+#define XT_CP0_SA   0
+#define XT_CP1_SA   ALIGNUP(XCHAL_CP1_SA_ALIGN, XT_CP0_SA + XCHAL_CP0_SA_SIZE)
+#define XT_CP2_SA   ALIGNUP(XCHAL_CP2_SA_ALIGN, XT_CP1_SA + XCHAL_CP1_SA_SIZE)
+#define XT_CP3_SA   ALIGNUP(XCHAL_CP3_SA_ALIGN, XT_CP2_SA + XCHAL_CP2_SA_SIZE)
+#define XT_CP4_SA   ALIGNUP(XCHAL_CP4_SA_ALIGN, XT_CP3_SA + XCHAL_CP3_SA_SIZE)
+#define XT_CP5_SA   ALIGNUP(XCHAL_CP5_SA_ALIGN, XT_CP4_SA + XCHAL_CP4_SA_SIZE)
+#define XT_CP6_SA   ALIGNUP(XCHAL_CP6_SA_ALIGN, XT_CP5_SA + XCHAL_CP5_SA_SIZE)
+#define XT_CP7_SA   ALIGNUP(XCHAL_CP7_SA_ALIGN, XT_CP6_SA + XCHAL_CP6_SA_SIZE)
+#define XT_CP_SA_SIZE   ALIGNUP(16, XT_CP7_SA + XCHAL_CP7_SA_SIZE)
 
 /*  Offsets within the overall save area:  */
-#define XT_CPENABLE      0 /* (2 bytes) coprocessors active for this thread */
-#define XT_CPSTORED      2 /* (2 bytes) coprocessors saved for this thread */
-#define XT_CP_CS_ST      4 /* (2 bytes) coprocessor callee-saved regs stored for this thread */
-#define XT_CP_ASA        8 /* (4 bytes) ptr to aligned save area */
+#define XT_CPENABLE 0   /* (2 bytes) coprocessors active for this thread */
+#define XT_CPSTORED 2   /* (2 bytes) coprocessors saved for this thread */
+#define XT_CP_CS_ST 4   /* (2 bytes) coprocessor callee-saved regs stored for this thread */
+#define XT_CP_ASA   8   /* (4 bytes) ptr to aligned save area */
 /*  Overall size allows for dynamic alignment:  */
-#define XT_CP_SIZE       ( 12 + XT_CP_SA_SIZE + XCHAL_TOTAL_SA_ALIGN )
-#else /* if XCHAL_CP_NUM > 0 */
-#define XT_CP_SIZE       0
-#endif /* if XCHAL_CP_NUM > 0 */
+#define XT_CP_SIZE  (12 + XT_CP_SA_SIZE + XCHAL_TOTAL_SA_ALIGN)
+#else
+#define XT_CP_SIZE  0
+#endif
 
 
 /*
- * -------------------------------------------------------------------------------
- * MACROS TO HANDLE ABI SPECIFICS OF FUNCTION ENTRY AND RETURN
- *
- * Convenient where the frame size requirements are the same for both ABIs.
- *  ENTRY(sz), RET(sz) are for framed functions (have locals or make calls).
- *  ENTRY0,    RET0    are for frameless functions (no locals, no calls).
- *
- * where size = size of stack frame in bytes (must be >0 and aligned to 16).
- * For framed functions the frame is created and the return address saved at
- * base of frame (Call0 ABI) or as determined by hardware (Windowed ABI).
- * For frameless functions, there is no frame and return address remains in a0.
- * Note: Because CPP macros expand to a single line, macros requiring multi-line
- * expansions are implemented as assembler macros.
- * -------------------------------------------------------------------------------
- */
+-------------------------------------------------------------------------------
+  MACROS TO HANDLE ABI SPECIFICS OF FUNCTION ENTRY AND RETURN
+
+  Convenient where the frame size requirements are the same for both ABIs.
+    ENTRY(sz), RET(sz) are for framed functions (have locals or make calls).
+    ENTRY0,    RET0    are for frameless functions (no locals, no calls).
+
+  where size = size of stack frame in bytes (must be >0 and aligned to 16).
+  For framed functions the frame is created and the return address saved at
+  base of frame (Call0 ABI) or as determined by hardware (Windowed ABI).
+  For frameless functions, there is no frame and return address remains in a0.
+  Note: Because CPP macros expand to a single line, macros requiring multi-line
+  expansions are implemented as assembler macros.
+-------------------------------------------------------------------------------
+*/
 
 #ifdef __ASSEMBLER__
-    #ifdef __XTENSA_CALL0_ABI__
-        /* Call0 */
-#define ENTRY( sz )    entry1 sz
-           .macro entry1 size = 0x10
-                                addi sp, sp, -\ size
-        s32i a0, sp, 0
-           .endm
-#define ENTRY0
-#define RET( sz )    ret1 sz
-           .macro ret1 size = 0x10
-                              l32i a0, sp, 0
-        addi sp, sp, \ size
-        ret
-           .endm
-#define RET0    ret
-    #else /* ifdef __XTENSA_CALL0_ABI__ */
-        /* Windowed */
-#define ENTRY( sz )    entry sp, sz
-#define ENTRY0    entry sp, 0x10
-#define RET( sz )      retw
-#define RET0      retw
-    #endif /* ifdef __XTENSA_CALL0_ABI__ */
-#endif /* ifdef __ASSEMBLER__ */
+#ifdef __XTENSA_CALL0_ABI__
+  /* Call0 */
+  #define ENTRY(sz)     entry1  sz
+    .macro  entry1 size=0x10
+    addi    sp, sp, -\size
+    s32i    a0, sp, 0
+    .endm
+  #define ENTRY0
+  #define RET(sz)       ret1    sz
+    .macro  ret1 size=0x10
+    l32i    a0, sp, 0
+    addi    sp, sp, \size
+    ret
+    .endm
+  #define RET0          ret
+#else
+  /* Windowed */
+  #define ENTRY(sz)     entry   sp, sz
+  #define ENTRY0        entry   sp, 0x10
+  #define RET(sz)       retw
+  #define RET0          retw
+#endif
+#endif
 
 
 #endif /* XTENSA_CONTEXT_H */
diff --git a/portable/ThirdParty/XCC/Xtensa/xtensa_init.c b/portable/ThirdParty/XCC/Xtensa/xtensa_init.c
index 7ee6f3d63..c18520350 100644
--- a/portable/ThirdParty/XCC/Xtensa/xtensa_init.c
+++ b/portable/ThirdParty/XCC/Xtensa/xtensa_init.c
@@ -1,4 +1,4 @@
-/*
+ /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
@@ -36,31 +36,35 @@
 
 
 #ifdef XT_BOARD
-    #include    <xtensa/xtbsp.h>
+#include    <xtensa/xtbsp.h>
 #endif
 
 #include    "xtensa_rtos.h"
 
 #ifdef XT_RTOS_TIMER_INT
 
-    unsigned _xt_tick_divisor = 0; /* cached number of cycles per tick */
+unsigned _xt_tick_divisor = 0;  /* cached number of cycles per tick */
 
 /*
- * Compute and initialize at run-time the tick divisor (the number of
- * processor clock cycles in an RTOS tick, used to set the tick timer).
- * Called when the processor clock frequency is not known at compile-time.
- */
-    void _xt_tick_divisor_init( void )
-    {
-        #ifdef XT_CLOCK_FREQ
-            _xt_tick_divisor = ( XT_CLOCK_FREQ / XT_TICK_PER_SEC );
-        #else
-            #ifdef XT_BOARD
-                _xt_tick_divisor = xtbsp_clock_freq_hz() / XT_TICK_PER_SEC;
-            #else
-            #error "No way to obtain processor clock frequency"
-            #endif /* XT_BOARD */
-        #endif /* XT_CLOCK_FREQ */
-    }
+Compute and initialize at run-time the tick divisor (the number of
+processor clock cycles in an RTOS tick, used to set the tick timer).
+Called when the processor clock frequency is not known at compile-time.
+*/
+void _xt_tick_divisor_init(void)
+{
+#ifdef XT_CLOCK_FREQ
+
+    _xt_tick_divisor = (XT_CLOCK_FREQ / XT_TICK_PER_SEC);
+
+#else
+
+    #ifdef XT_BOARD
+    _xt_tick_divisor = xtbsp_clock_freq_hz() / XT_TICK_PER_SEC;
+    #else
+    #error "No way to obtain processor clock frequency"
+    #endif  /* XT_BOARD */
+
+#endif /* XT_CLOCK_FREQ */
+}
 
 #endif /* XT_RTOS_TIMER_INT */
diff --git a/portable/ThirdParty/XCC/Xtensa/xtensa_intr.c b/portable/ThirdParty/XCC/Xtensa/xtensa_intr.c
index 87bf63cb4..88ed191e3 100644
--- a/portable/ThirdParty/XCC/Xtensa/xtensa_intr.c
+++ b/portable/ThirdParty/XCC/Xtensa/xtensa_intr.c
@@ -1,4 +1,4 @@
-/*
+ /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
@@ -43,110 +43,95 @@
 
 /* Handler table is in xtensa_intr_asm.S */
 
-    extern xt_exc_handler _xt_exception_table[ XCHAL_EXCCAUSE_NUM ];
+extern xt_exc_handler _xt_exception_table[XCHAL_EXCCAUSE_NUM];
 
 
 /*
- * Default handler for unhandled exceptions.
- */
-    void xt_unhandled_exception( XtExcFrame * frame )
-    {
-        exit( -1 );
-    }
+  Default handler for unhandled exceptions.
+*/
+void xt_unhandled_exception(XtExcFrame *frame)
+{
+    exit(-1);
+}
 
 
 /*
- * This function registers a handler for the specified exception.
- * The function returns the address of the previous handler.
- * On error, it returns 0.
- */
-    xt_exc_handler xt_set_exception_handler( int n,
-                                             xt_exc_handler f )
-    {
-        xt_exc_handler old;
+  This function registers a handler for the specified exception.
+  The function returns the address of the previous handler.
+  On error, it returns 0.
+*/
+xt_exc_handler xt_set_exception_handler(int n, xt_exc_handler f)
+{
+    xt_exc_handler old;
 
-        if( ( n < 0 ) || ( n >= XCHAL_EXCCAUSE_NUM ) )
-        {
-            return 0; /* invalid exception number */
-        }
+    if( n < 0 || n >= XCHAL_EXCCAUSE_NUM )
+        return 0;       /* invalid exception number */
 
-        old = _xt_exception_table[ n ];
+    old = _xt_exception_table[n];
 
-        if( f )
-        {
-            _xt_exception_table[ n ] = f;
-        }
-        else
-        {
-            _xt_exception_table[ n ] = &xt_unhandled_exception;
-        }
-
-        return( ( old == &xt_unhandled_exception ) ? 0 : old );
+    if (f) {
+        _xt_exception_table[n] = f;
+    }
+    else {
+        _xt_exception_table[n] = &xt_unhandled_exception;
     }
 
-#endif /* if XCHAL_HAVE_EXCEPTIONS */
+    return ((old == &xt_unhandled_exception) ? 0 : old);
+}
+
+#endif
 
 #if XCHAL_HAVE_INTERRUPTS
 
 /* Handler table is in xtensa_intr_asm.S */
 
-    typedef struct xt_handler_table_entry
-    {
-        void * handler;
-        void * arg;
-    } xt_handler_table_entry;
+typedef struct xt_handler_table_entry {
+    void * handler;
+    void * arg;
+} xt_handler_table_entry;
 
-    extern xt_handler_table_entry _xt_interrupt_table[ XCHAL_NUM_INTERRUPTS ];
+extern xt_handler_table_entry _xt_interrupt_table[XCHAL_NUM_INTERRUPTS];
 
 
 /*
- * Default handler for unhandled interrupts.
- */
-    void xt_unhandled_interrupt( void * arg )
-    {
-        exit( -1 );
-    }
+  Default handler for unhandled interrupts.
+*/
+void xt_unhandled_interrupt(void * arg)
+{
+    exit(-1);
+}
 
 
 /*
- * This function registers a handler for the specified interrupt. The "arg"
- * parameter specifies the argument to be passed to the handler when it is
- * invoked. The function returns the address of the previous handler.
- * On error, it returns 0.
- */
-    xt_handler xt_set_interrupt_handler( int n,
-                                         xt_handler f,
-                                         void * arg )
-    {
-        xt_handler_table_entry * entry;
-        xt_handler old;
+  This function registers a handler for the specified interrupt. The "arg"
+  parameter specifies the argument to be passed to the handler when it is
+  invoked. The function returns the address of the previous handler.
+  On error, it returns 0.
+*/
+xt_handler xt_set_interrupt_handler(int n, xt_handler f, void * arg)
+{
+    xt_handler_table_entry * entry;
+    xt_handler               old;
 
-        if( ( n < 0 ) || ( n >= XCHAL_NUM_INTERRUPTS ) )
-        {
-            return 0; /* invalid interrupt number */
-        }
+    if( n < 0 || n >= XCHAL_NUM_INTERRUPTS )
+        return 0;       /* invalid interrupt number */
+    if( Xthal_intlevel[n] > XCHAL_EXCM_LEVEL )
+        return 0;       /* priority level too high to safely handle in C */
 
-        if( Xthal_intlevel[ n ] > XCHAL_EXCM_LEVEL )
-        {
-            return 0; /* priority level too high to safely handle in C */
-        }
+    entry = _xt_interrupt_table + n;
+    old   = entry->handler;
 
-        entry = _xt_interrupt_table + n;
-        old = entry->handler;
-
-        if( f )
-        {
-            entry->handler = f;
-            entry->arg = arg;
-        }
-        else
-        {
-            entry->handler = &xt_unhandled_interrupt;
-            entry->arg = ( void * ) n;
-        }
-
-        return( ( old == &xt_unhandled_interrupt ) ? 0 : old );
+    if (f) {
+        entry->handler = f;
+        entry->arg     = arg;
     }
+    else {
+        entry->handler = &xt_unhandled_interrupt;
+        entry->arg     = (void*)n;
+    }
+
+    return ((old == &xt_unhandled_interrupt) ? 0 : old);
+}
 
 
 #endif /* XCHAL_HAVE_INTERRUPTS */
diff --git a/portable/ThirdParty/XCC/Xtensa/xtensa_overlay_os_hook.c b/portable/ThirdParty/XCC/Xtensa/xtensa_overlay_os_hook.c
index fcbc57386..2a8506a01 100644
--- a/portable/ThirdParty/XCC/Xtensa/xtensa_overlay_os_hook.c
+++ b/portable/ThirdParty/XCC/Xtensa/xtensa_overlay_os_hook.c
@@ -1,4 +1,4 @@
-/*
+ /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
@@ -39,7 +39,7 @@
 /* Mutex object that controls access to the overlay. Currently only one
  * overlay region is supported so one mutex suffices.
  */
-    static SemaphoreHandle_t xt_overlay_mutex;
+static SemaphoreHandle_t xt_overlay_mutex;
 
 
 /* This function should be overridden to provide OS specific init such
@@ -47,30 +47,30 @@
  * Typically this mutex would be set up with priority inheritance. See
  * overlay manager documentation for more details.
  */
-    void xt_overlay_init_os( void )
-    {
-        /* Create the mutex for overlay access. Priority inheritance is
-         * required.
-         */
-        xt_overlay_mutex = xSemaphoreCreateMutex();
-    }
+void xt_overlay_init_os(void)
+{
+    /* Create the mutex for overlay access. Priority inheritance is
+     * required.
+     */
+    xt_overlay_mutex = xSemaphoreCreateMutex();
+}
 
 
 /* This function locks access to shared overlay resources, typically
  * by acquiring a mutex.
  */
-    void xt_overlay_lock( void )
-    {
-        xSemaphoreTake( xt_overlay_mutex, 0 );
-    }
+void xt_overlay_lock(void)
+{
+    xSemaphoreTake(xt_overlay_mutex, 0);
+}
 
 
 /* This function releases access to shared overlay resources, typically
  * by unlocking a mutex.
  */
-    void xt_overlay_unlock( void )
-    {
-        xSemaphoreGive( xt_overlay_mutex );
-    }
+void xt_overlay_unlock(void)
+{
+    xSemaphoreGive(xt_overlay_mutex);
+}
 
-#endif /* if configUSE_MUTEX */
+#endif
diff --git a/portable/ThirdParty/XCC/Xtensa/xtensa_rtos.h b/portable/ThirdParty/XCC/Xtensa/xtensa_rtos.h
index 54f4d0b7e..2c917c832 100644
--- a/portable/ThirdParty/XCC/Xtensa/xtensa_rtos.h
+++ b/portable/ThirdParty/XCC/Xtensa/xtensa_rtos.h
@@ -1,4 +1,4 @@
-/*
+ /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
@@ -49,9 +49,9 @@
 #define XTENSA_RTOS_H
 
 #ifdef __ASSEMBLER__
-    #include    <xtensa/coreasm.h>
+#include    <xtensa/coreasm.h>
 #else
-    #include    <xtensa/config/core.h>
+#include    <xtensa/config/core.h>
 #endif
 
 #include    <xtensa/corebits.h>
@@ -59,180 +59,180 @@
 #include    <xtensa/simcall.h>
 
 /*
- * Include any RTOS specific definitions that are needed by this header.
- */
+Include any RTOS specific definitions that are needed by this header.
+*/
 #include    <FreeRTOSConfig.h>
 
 /*
- * Convert FreeRTOSConfig definitions to XTENSA definitions.
- * However these can still be overridden from the command line.
- */
+Convert FreeRTOSConfig definitions to XTENSA definitions.
+However these can still be overridden from the command line.
+*/
 
 #ifndef XT_SIMULATOR
-    #if configXT_SIMULATOR
-        #define XT_SIMULATOR    1       /* Simulator mode */
-    #endif
+  #if configXT_SIMULATOR
+    #define XT_SIMULATOR             1  /* Simulator mode */
+  #endif
 #endif
 
 #ifndef XT_BOARD
-    #if configXT_BOARD
-        #define XT_BOARD    1           /* Board mode */
-    #endif
+  #if configXT_BOARD
+    #define XT_BOARD                 1  /* Board mode */
+  #endif
 #endif
 
 #ifndef XT_TIMER_INDEX
-    #if defined configXT_TIMER_INDEX
-        #define XT_TIMER_INDEX    configXT_TIMER_INDEX     /* Index of hardware timer to be used */
-    #endif
+  #if defined configXT_TIMER_INDEX
+    #define XT_TIMER_INDEX           configXT_TIMER_INDEX  /* Index of hardware timer to be used */
+  #endif
 #endif
 
 #ifndef XT_INTEXC_HOOKS
-    #if configXT_INTEXC_HOOKS
-        #define XT_INTEXC_HOOKS    1    /* Enables exception hooks */
-    #endif
+  #if configXT_INTEXC_HOOKS
+    #define XT_INTEXC_HOOKS          1  /* Enables exception hooks */
+  #endif
 #endif
 
-#if ( !XT_SIMULATOR ) && ( !XT_BOARD )
-    #error Either XT_SIMULATOR or XT_BOARD must be defined.
+#if (!XT_SIMULATOR) && (!XT_BOARD)
+  #error Either XT_SIMULATOR or XT_BOARD must be defined.
 #endif
 
 
 /*
- * Name of RTOS (for messages).
- */
+Name of RTOS (for messages).
+*/
 #define XT_RTOS_NAME    FreeRTOS
 
 /*
- * Check some Xtensa configuration requirements and report error if not met.
- * Error messages can be customize to the RTOS port.
- */
+Check some Xtensa configuration requirements and report error if not met.
+Error messages can be customize to the RTOS port.
+*/
 
 #if !XCHAL_HAVE_XEA2
-    #error "FreeRTOS/Xtensa requires XEA2 (exception architecture 2)."
+#error "FreeRTOS/Xtensa requires XEA2 (exception architecture 2)."
 #endif
 
 
 /*******************************************************************************
-*
-*  RTOS CALLOUT MACROS MAPPED TO RTOS PORT-SPECIFIC FUNCTIONS.
-*
-*  Define callout macros used in generic Xtensa code to interact with the RTOS.
-*  The macros are simply the function names for use in calls from assembler code.
-*  Some of these functions may call back to generic functions in xtensa_context.h .
-*
+
+RTOS CALLOUT MACROS MAPPED TO RTOS PORT-SPECIFIC FUNCTIONS.
+
+Define callout macros used in generic Xtensa code to interact with the RTOS.
+The macros are simply the function names for use in calls from assembler code.
+Some of these functions may call back to generic functions in xtensa_context.h .
+
 *******************************************************************************/
 
 /*
- * Inform RTOS of entry into an interrupt handler that will affect it.
- * Allows RTOS to manage switch to any system stack and count nesting level.
- * Called after minimal context has been saved, with interrupts disabled.
- * RTOS port can call0 _xt_context_save to save the rest of the context.
- * May only be called from assembly code by the 'call0' instruction.
- */
-/* void XT_RTOS_INT_ENTER(void) */
-#define XT_RTOS_INT_ENTER    _frxt_int_enter
+Inform RTOS of entry into an interrupt handler that will affect it.
+Allows RTOS to manage switch to any system stack and count nesting level.
+Called after minimal context has been saved, with interrupts disabled.
+RTOS port can call0 _xt_context_save to save the rest of the context.
+May only be called from assembly code by the 'call0' instruction.
+*/
+// void XT_RTOS_INT_ENTER(void)
+#define XT_RTOS_INT_ENTER   _frxt_int_enter
 
 /*
- * Inform RTOS of completion of an interrupt handler, and give control to
- * RTOS to perform thread/task scheduling, switch back from any system stack
- * and restore the context, and return to the exit dispatcher saved in the
- * stack frame at XT_STK_EXIT. RTOS port can call0 _xt_context_restore
- * to save the context saved in XT_RTOS_INT_ENTER via _xt_context_save,
- * leaving only a minimal part of the context to be restored by the exit
- * dispatcher. This function does not return to the place it was called from.
- * May only be called from assembly code by the 'call0' instruction.
- */
-/* void XT_RTOS_INT_EXIT(void) */
+Inform RTOS of completion of an interrupt handler, and give control to
+RTOS to perform thread/task scheduling, switch back from any system stack
+and restore the context, and return to the exit dispatcher saved in the
+stack frame at XT_STK_EXIT. RTOS port can call0 _xt_context_restore
+to save the context saved in XT_RTOS_INT_ENTER via _xt_context_save,
+leaving only a minimal part of the context to be restored by the exit
+dispatcher. This function does not return to the place it was called from.
+May only be called from assembly code by the 'call0' instruction.
+*/
+// void XT_RTOS_INT_EXIT(void)
 #define XT_RTOS_INT_EXIT    _frxt_int_exit
 
 /*
- * Inform RTOS of the occurrence of a tick timer interrupt.
- * If RTOS has no tick timer, leave XT_RTOS_TIMER_INT undefined.
- * May be coded in or called from C or assembly, per ABI conventions.
- * RTOS may optionally define XT_TICK_PER_SEC in its own way (eg. macro).
- */
-/* void XT_RTOS_TIMER_INT(void) */
-#define XT_RTOS_TIMER_INT    _frxt_timer_int
-#define XT_TICK_PER_SEC      configTICK_RATE_HZ
+Inform RTOS of the occurrence of a tick timer interrupt.
+If RTOS has no tick timer, leave XT_RTOS_TIMER_INT undefined.
+May be coded in or called from C or assembly, per ABI conventions.
+RTOS may optionally define XT_TICK_PER_SEC in its own way (eg. macro).
+*/
+// void XT_RTOS_TIMER_INT(void)
+#define XT_RTOS_TIMER_INT   _frxt_timer_int
+#define XT_TICK_PER_SEC     configTICK_RATE_HZ
 
 /*
- * Return in a15 the base address of the co-processor state save area for the
- * thread that triggered a co-processor exception, or 0 if no thread was running.
- * The state save area is structured as defined in xtensa_context.h and has size
- * XT_CP_SIZE. Co-processor instructions should only be used in thread code, never
- * in interrupt handlers or the RTOS kernel. May only be called from assembly code
- * and by the 'call0' instruction. A result of 0 indicates an unrecoverable error.
- * The implementation may use only a2-4, a15 (all other regs must be preserved).
- */
-/* void* XT_RTOS_CP_STATE(void) */
+Return in a15 the base address of the co-processor state save area for the
+thread that triggered a co-processor exception, or 0 if no thread was running.
+The state save area is structured as defined in xtensa_context.h and has size
+XT_CP_SIZE. Co-processor instructions should only be used in thread code, never
+in interrupt handlers or the RTOS kernel. May only be called from assembly code
+and by the 'call0' instruction. A result of 0 indicates an unrecoverable error.
+The implementation may use only a2-4, a15 (all other regs must be preserved).
+*/
+// void* XT_RTOS_CP_STATE(void)
 #define XT_RTOS_CP_STATE    _frxt_task_coproc_state
 
 
 /*******************************************************************************
-*
-*  HOOKS TO DYNAMICALLY INSTALL INTERRUPT AND EXCEPTION HANDLERS PER LEVEL.
-*
-*  This Xtensa RTOS port provides hooks for dynamically installing exception
-*  and interrupt handlers to facilitate automated testing where each test
-*  case can install its own handler for user exceptions and each interrupt
-*  priority (level). This consists of an array of function pointers indexed
-*  by interrupt priority, with index 0 being the user exception handler hook.
-*  Each entry in the array is initially 0, and may be replaced by a function
-*  pointer of type XT_INTEXC_HOOK. A handler may be uninstalled by installing 0.
-*
-*  The handler for low and medium priority obeys ABI conventions so may be coded
-*  in C. For the exception handler, the cause is the contents of the EXCCAUSE
-*  reg, and the result is -1 if handled, else the cause (still needs handling).
-*  For interrupt handlers, the cause is a mask of pending enabled interrupts at
-*  that level, and the result is the same mask with the bits for the handled
-*  interrupts cleared (those not cleared still need handling). This allows a test
-*  case to either pre-handle or override the default handling for the exception
-*  or interrupt level (see xtensa_vectors.S).
-*
-*  High priority handlers (including NMI) must be coded in assembly, are always
-*  called by 'call0' regardless of ABI, must preserve all registers except a0,
-*  and must not use or modify the interrupted stack. The hook argument 'cause'
-*  is not passed and the result is ignored, so as not to burden the caller with
-*  saving and restoring a2 (it assumes only one interrupt per level - see the
-*  discussion in high priority interrupts in xtensa_vectors.S). The handler
-*  therefore should be coded to prototype 'void h(void)' even though it plugs
-*  into an array of handlers of prototype 'unsigned h(unsigned)'.
-*
-*  To enable interrupt/exception hooks, compile the RTOS with '-DXT_INTEXC_HOOKS'.
-*
+
+HOOKS TO DYNAMICALLY INSTALL INTERRUPT AND EXCEPTION HANDLERS PER LEVEL.
+
+This Xtensa RTOS port provides hooks for dynamically installing exception
+and interrupt handlers to facilitate automated testing where each test
+case can install its own handler for user exceptions and each interrupt
+priority (level). This consists of an array of function pointers indexed
+by interrupt priority, with index 0 being the user exception handler hook.
+Each entry in the array is initially 0, and may be replaced by a function
+pointer of type XT_INTEXC_HOOK. A handler may be uninstalled by installing 0.
+
+The handler for low and medium priority obeys ABI conventions so may be coded
+in C. For the exception handler, the cause is the contents of the EXCCAUSE
+reg, and the result is -1 if handled, else the cause (still needs handling).
+For interrupt handlers, the cause is a mask of pending enabled interrupts at
+that level, and the result is the same mask with the bits for the handled
+interrupts cleared (those not cleared still need handling). This allows a test
+case to either pre-handle or override the default handling for the exception
+or interrupt level (see xtensa_vectors.S).
+
+High priority handlers (including NMI) must be coded in assembly, are always
+called by 'call0' regardless of ABI, must preserve all registers except a0,
+and must not use or modify the interrupted stack. The hook argument 'cause'
+is not passed and the result is ignored, so as not to burden the caller with
+saving and restoring a2 (it assumes only one interrupt per level - see the
+discussion in high priority interrupts in xtensa_vectors.S). The handler
+therefore should be coded to prototype 'void h(void)' even though it plugs
+into an array of handlers of prototype 'unsigned h(unsigned)'.
+
+To enable interrupt/exception hooks, compile the RTOS with '-DXT_INTEXC_HOOKS'.
+
 *******************************************************************************/
 
-#define XT_INTEXC_HOOK_NUM    ( 1 + XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI )
+#define XT_INTEXC_HOOK_NUM  (1 + XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI)
 
 #ifndef __ASSEMBLER__
-    typedef unsigned (* XT_INTEXC_HOOK)( unsigned cause );
-    extern volatile XT_INTEXC_HOOK _xt_intexc_hooks[ XT_INTEXC_HOOK_NUM ];
+typedef unsigned (*XT_INTEXC_HOOK)(unsigned cause);
+extern  volatile XT_INTEXC_HOOK _xt_intexc_hooks[XT_INTEXC_HOOK_NUM];
 #endif
 
 
 /*******************************************************************************
-*
-*  CONVENIENCE INCLUSIONS.
-*
-*  Ensures RTOS specific files need only include this one Xtensa-generic header.
-*  These headers are included last so they can use the RTOS definitions above.
-*
+
+CONVENIENCE INCLUSIONS.
+
+Ensures RTOS specific files need only include this one Xtensa-generic header.
+These headers are included last so they can use the RTOS definitions above.
+
 *******************************************************************************/
 
 #include    "xtensa_context.h"
 
 #ifdef XT_RTOS_TIMER_INT
-    #include    "xtensa_timer.h"
+#include    "xtensa_timer.h"
 #endif
 
 
 /*******************************************************************************
-*
-*  Xtensa Port Version.
-*
+
+Xtensa Port Version.
+
 *******************************************************************************/
 
-#define XTENSA_PORT_VERSION           1.7
-#define XTENSA_PORT_VERSION_STRING    "1.7"
+#define XTENSA_PORT_VERSION             1.7
+#define XTENSA_PORT_VERSION_STRING      "1.7"
 
 #endif /* XTENSA_RTOS_H */
diff --git a/portable/ThirdParty/XCC/Xtensa/xtensa_timer.h b/portable/ThirdParty/XCC/Xtensa/xtensa_timer.h
index ecaf3f4e9..cefac70f2 100644
--- a/portable/ThirdParty/XCC/Xtensa/xtensa_timer.h
+++ b/portable/ThirdParty/XCC/Xtensa/xtensa_timer.h
@@ -1,4 +1,4 @@
-/*
+ /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
@@ -47,118 +47,118 @@
 #define XTENSA_TIMER_H
 
 #ifdef __ASSEMBLER__
-    #include    <xtensa/coreasm.h>
+#include    <xtensa/coreasm.h>
 #endif
 
 #include    <xtensa/corebits.h>
 #include    <xtensa/config/system.h>
 
-#include    "xtensa_rtos.h" /* in case this wasn't included directly */
+#include    "xtensa_rtos.h"     /* in case this wasn't included directly */
 
 #include    <FreeRTOSConfig.h>
 
 /*
- * Select timer to use for periodic tick, and determine its interrupt number
- * and priority. User may specify a timer by defining XT_TIMER_INDEX with -D,
- * in which case its validity is checked (it must exist in this core and must
- * not be on a high priority interrupt - an error will be reported in invalid).
- * Otherwise select the first low or medium priority interrupt timer available.
- */
+Select timer to use for periodic tick, and determine its interrupt number
+and priority. User may specify a timer by defining XT_TIMER_INDEX with -D,
+in which case its validity is checked (it must exist in this core and must
+not be on a high priority interrupt - an error will be reported in invalid).
+Otherwise select the first low or medium priority interrupt timer available.
+*/
 #if XCHAL_NUM_TIMERS == 0
 
-    #error "This Xtensa configuration is unsupported, it has no timers."
+  #error "This Xtensa configuration is unsupported, it has no timers."
 
 #else
 
-    #ifndef XT_TIMER_INDEX
-        #if XCHAL_TIMER3_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
-            #if XCHAL_INT_LEVEL( XCHAL_TIMER3_INTERRUPT ) <= XCHAL_EXCM_LEVEL
-                #undef  XT_TIMER_INDEX
-                #define XT_TIMER_INDEX    3
-            #endif
-        #endif
-        #if XCHAL_TIMER2_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
-            #if XCHAL_INT_LEVEL( XCHAL_TIMER2_INTERRUPT ) <= XCHAL_EXCM_LEVEL
-                #undef  XT_TIMER_INDEX
-                #define XT_TIMER_INDEX    2
-            #endif
-        #endif
-        #if XCHAL_TIMER1_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
-            #if XCHAL_INT_LEVEL( XCHAL_TIMER1_INTERRUPT ) <= XCHAL_EXCM_LEVEL
-                #undef  XT_TIMER_INDEX
-                #define XT_TIMER_INDEX    1
-            #endif
-        #endif
-        #if XCHAL_TIMER0_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
-            #if XCHAL_INT_LEVEL( XCHAL_TIMER0_INTERRUPT ) <= XCHAL_EXCM_LEVEL
-                #undef  XT_TIMER_INDEX
-                #define XT_TIMER_INDEX    0
-            #endif
-        #endif
-    #endif /* ifndef XT_TIMER_INDEX */
-    #ifndef XT_TIMER_INDEX
-        #error "There is no suitable timer in this Xtensa configuration."
+#ifndef XT_TIMER_INDEX
+  #if XCHAL_TIMER3_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
+    #if XCHAL_INT_LEVEL(XCHAL_TIMER3_INTERRUPT) <= XCHAL_EXCM_LEVEL
+      #undef  XT_TIMER_INDEX
+      #define XT_TIMER_INDEX    3
     #endif
-
-    #define XT_CCOMPARE        ( CCOMPARE + XT_TIMER_INDEX )
-    #define XT_TIMER_INTNUM    XCHAL_TIMER_INTERRUPT( XT_TIMER_INDEX )
-    #define XT_TIMER_INTPRI    XCHAL_INT_LEVEL( XT_TIMER_INTNUM )
-    #define XT_TIMER_INTEN     ( 1 << XT_TIMER_INTNUM )
-
-    #if XT_TIMER_INTNUM == XTHAL_TIMER_UNCONFIGURED
-        #error "The timer selected by XT_TIMER_INDEX does not exist in this core."
-    #elif XT_TIMER_INTPRI > XCHAL_EXCM_LEVEL
-        #error "The timer interrupt cannot be high priority (use medium or low)."
+  #endif
+  #if XCHAL_TIMER2_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
+    #if XCHAL_INT_LEVEL(XCHAL_TIMER2_INTERRUPT) <= XCHAL_EXCM_LEVEL
+      #undef  XT_TIMER_INDEX
+      #define XT_TIMER_INDEX    2
     #endif
+  #endif
+  #if XCHAL_TIMER1_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
+    #if XCHAL_INT_LEVEL(XCHAL_TIMER1_INTERRUPT) <= XCHAL_EXCM_LEVEL
+      #undef  XT_TIMER_INDEX
+      #define XT_TIMER_INDEX    1
+    #endif
+  #endif
+  #if XCHAL_TIMER0_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
+    #if XCHAL_INT_LEVEL(XCHAL_TIMER0_INTERRUPT) <= XCHAL_EXCM_LEVEL
+      #undef  XT_TIMER_INDEX
+      #define XT_TIMER_INDEX    0
+    #endif
+  #endif
+#endif
+#ifndef XT_TIMER_INDEX
+  #error "There is no suitable timer in this Xtensa configuration."
+#endif
+
+#define XT_CCOMPARE             (CCOMPARE + XT_TIMER_INDEX)
+#define XT_TIMER_INTNUM         XCHAL_TIMER_INTERRUPT(XT_TIMER_INDEX)
+#define XT_TIMER_INTPRI         XCHAL_INT_LEVEL(XT_TIMER_INTNUM)
+#define XT_TIMER_INTEN          (1 << XT_TIMER_INTNUM)
+
+#if XT_TIMER_INTNUM == XTHAL_TIMER_UNCONFIGURED
+  #error "The timer selected by XT_TIMER_INDEX does not exist in this core."
+#elif XT_TIMER_INTPRI > XCHAL_EXCM_LEVEL
+  #error "The timer interrupt cannot be high priority (use medium or low)."
+#endif
 
 #endif /* XCHAL_NUM_TIMERS */
 
 /*
- * Set processor clock frequency, used to determine clock divisor for timer tick.
- * User should BE SURE TO ADJUST THIS for the Xtensa platform being used.
- * If using a supported board via the board-independent API defined in xtbsp.h,
- * this may be left undefined and frequency and tick divisor will be computed
- * and cached during run-time initialization.
- *
- * NOTE ON SIMULATOR:
- * Under the Xtensa instruction set simulator, the frequency can only be estimated
- * because it depends on the speed of the host and the version of the simulator.
- * Also because it runs much slower than hardware, it is not possible to achieve
- * real-time performance for most applications under the simulator. A frequency
- * too low does not allow enough time between timer interrupts, starving threads.
- * To obtain a more convenient but non-real-time tick duration on the simulator,
- * compile with xt-xcc option "-DXT_SIMULATOR".
- * Adjust this frequency to taste (it's not real-time anyway!).
- */
-#if defined( XT_SIMULATOR ) && !defined( XT_CLOCK_FREQ )
-    #define XT_CLOCK_FREQ    configCPU_CLOCK_HZ
+Set processor clock frequency, used to determine clock divisor for timer tick.
+User should BE SURE TO ADJUST THIS for the Xtensa platform being used.
+If using a supported board via the board-independent API defined in xtbsp.h,
+this may be left undefined and frequency and tick divisor will be computed
+and cached during run-time initialization.
+
+NOTE ON SIMULATOR:
+Under the Xtensa instruction set simulator, the frequency can only be estimated
+because it depends on the speed of the host and the version of the simulator.
+Also because it runs much slower than hardware, it is not possible to achieve
+real-time performance for most applications under the simulator. A frequency
+too low does not allow enough time between timer interrupts, starving threads.
+To obtain a more convenient but non-real-time tick duration on the simulator,
+compile with xt-xcc option "-DXT_SIMULATOR".
+Adjust this frequency to taste (it's not real-time anyway!).
+*/
+#if defined(XT_SIMULATOR) && !defined(XT_CLOCK_FREQ)
+#define XT_CLOCK_FREQ       configCPU_CLOCK_HZ
 #endif
 
-#if !defined( XT_CLOCK_FREQ ) && !defined( XT_BOARD )
-    #error "XT_CLOCK_FREQ must be defined for the target platform."
+#if !defined(XT_CLOCK_FREQ) && !defined(XT_BOARD)
+  #error "XT_CLOCK_FREQ must be defined for the target platform."
 #endif
 
 /*
- * Default number of timer "ticks" per second (default 100 for 10ms tick).
- * RTOS may define this in its own way (if applicable) in xtensa_rtos.h.
- * User may redefine this to an optimal value for the application, either by
- * editing this here or in xtensa_rtos.h, or compiling with xt-xcc option
- * "-DXT_TICK_PER_SEC=<value>" where <value> is a suitable number.
- */
+Default number of timer "ticks" per second (default 100 for 10ms tick).
+RTOS may define this in its own way (if applicable) in xtensa_rtos.h.
+User may redefine this to an optimal value for the application, either by
+editing this here or in xtensa_rtos.h, or compiling with xt-xcc option
+"-DXT_TICK_PER_SEC=<value>" where <value> is a suitable number.
+*/
 #ifndef XT_TICK_PER_SEC
-    #define XT_TICK_PER_SEC    configTICK_RATE_HZ    /* 10 ms tick = 100 ticks per second */
+#define XT_TICK_PER_SEC    configTICK_RATE_HZ        /* 10 ms tick = 100 ticks per second */
 #endif
 
 /*
- * Derivation of clock divisor for timer tick and interrupt (one per tick).
- */
+Derivation of clock divisor for timer tick and interrupt (one per tick).
+*/
 #ifdef XT_CLOCK_FREQ
-    #define XT_TICK_DIVISOR    ( XT_CLOCK_FREQ / XT_TICK_PER_SEC )
+#define XT_TICK_DIVISOR     (XT_CLOCK_FREQ / XT_TICK_PER_SEC)
 #endif
 
 #ifndef __ASSEMBLER__
-    extern unsigned _xt_tick_divisor;
-    extern void _xt_tick_divisor_init( void );
+extern unsigned _xt_tick_divisor;
+extern void     _xt_tick_divisor_init(void);
 #endif
 
-#endif /* XTENSA_TIMER_H */
+#endif  /* XTENSA_TIMER_H */

From ddc89fa9851a85b1d5dfe40bfa9b84b5c1e514df Mon Sep 17 00:00:00 2001
From: Chris Morgan <cmorgan@boston-engineering.com>
Date: Tue, 28 Nov 2023 07:40:11 -0500
Subject: [PATCH 177/424] POSIX - Switch from posix timers to a timer thread to
 fix signal handling with non-FreeRTOS pthreads

Improve upon the elegant approach of using signals to cause task/pthreads
suspension and scheduler execution by using directed signals.

This fixes:
- Deadlocks in non-FreeRTOS pthreads
- Multiple FreeRTOS tasks(pthreads) incorrectly running at the same time

By directing the signals using pthread_kill() the signal handler in the presently running
FreeRTOS task/pthread will be called, ensuring that the scheduler runs both in the context
of a FreeRTOS task/pthread and from the presently executing FreeRTOS task/pthread.

Details
==============

The POSIX port uses signals to preempt FreeRTOS tasks (implemented as pthreads), a very neat and elegant
approach to forcing tasks/pthreads to suspend and run the scheduler.

Signal handlers are process global.

Posix timers generate signals when the timer expires, and the signal is sent to the currently
running pthread.

In systems where there are pthreads that are NOT a result of creating FreeRTOS tasks, such as the
entry point thread that calls main(), or user created pthreads, this poses a serious issue.

While the POSIX port only allows a single FreeRTOS pthread to run at once, by causing all suspended
threads to not be scheduled due to their waiting on a pthread condition variable,
this isn't the case with non-FreeRTOS pthreads.

Thus it is possible that a non-FreeRTOS pthread is running when the timer expires and the signal
is generated. This results in the signal handler running in the non-FreeRTOS thread.

The sequence of events results in these events from signal handler context:
- vPortSystemTickHandler() being called
- The scheduler running
- Selecting another FreeRTOS task to run and switching the active task
- The newly selected task released from suspension by pthread_cond_signal()
- The presently active thread calling event_wait()
- The pthread calling pthread_cond_wait(), suspending the thread and allowing the host OS scheduler
  to schedule another thread to run.

If this occurs from a non-FreeRTOS thread this results in:
- The active FreeRTOS pthread (Task A/Thread A) continuing to run (as the signal handler that calls
  event_wait() ran instead in a non-FreeRTOS pthread.
- The pthread where the signal handler did run (Thread B) will call event_wait() and pthread_cond_wait(),
  but on the condition variable of the previously active FreeRTOS task, oops. This causes the
  non-FreeRTOS pthread to block unexpectedly relative to what the developer might have expected.
- The newly selected FreeRTOS Task (Task C/Thread C) will resume and start running.

At this point Task A/Thread A is running concurrently with Task C/Thread C. While this may not
necessarily be an issue, it does not replicate the expected behavior of a single Task running at
once.

Note that Thread B will resume if/when Task A/ThreadA is switched to. However, this could be delayed
by an arbitrary amount of time, or could never occur.

Also note that if there are multiple non-FreeRTOS pthreads that Thread D, E, F...etc could suffer the
same fate as Thread B, if the scheduler were to suspend Task C/Thread C and resume Task E/Thread E.

Implementation
==============

Timer details
-------------
A standalone pthread for the signal generation thread was chosen, rather than using
a posix timer_settime() handler function because the latter creates a temporary
pthread for each handler callback. This makes debugging much more difficult due to
gdb detecting the creation and destruction of these temporary threads.

Signal delivery
--------------
While signal handlers are per-thread, it is possible for pthreads to selectively block
signals, rather than using thread directed signals. However, the approach of blocking
signals in non-FreeRTOS pthreads adds complexity to each of these non-FreeRTOS pthreads
including ensuring that these signals are blocked at thread creation, prior to the thread
starting up. Directed signals removes the requirement for non-FreeRTOS pthreads to be aware
of and take action to protect against these signals, reducing complexity.
---
 portable/ThirdParty/GCC/Posix/port.c | 69 +++++++++++-----------------
 1 file changed, 27 insertions(+), 42 deletions(-)

diff --git a/portable/ThirdParty/GCC/Posix/port.c b/portable/ThirdParty/GCC/Posix/port.c
index 5dc3d73e2..d312aa48d 100644
--- a/portable/ThirdParty/GCC/Posix/port.c
+++ b/portable/ThirdParty/GCC/Posix/port.c
@@ -60,6 +60,7 @@
 #include <sys/time.h>
 #include <sys/times.h>
 #include <time.h>
+#include <unistd.h>
 
 #ifdef __APPLE__
     #include <mach/mach_vm.h>
@@ -103,6 +104,9 @@ static pthread_t hMainThread = ( pthread_t ) NULL;
 static volatile BaseType_t uxCriticalNesting;
 /*-----------------------------------------------------------*/
 
+static pthread_t hTimerTickThread;
+static bool xTimerTickThreadShouldRun;
+
 static BaseType_t xSchedulerEnd = pdFALSE;
 /*-----------------------------------------------------------*/
 
@@ -231,6 +235,10 @@ BaseType_t xPortStartScheduler( void )
         sigwait( &xSignals, &iSignal );
     }
 
+    /* asking timer thread to shut down */
+    xTimerTickThreadShouldRun = false;
+    pthread_join( hTimerTickThread, NULL );
+
     /* Cancel the Idle task and free its resources */
     #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
         vPortCancelThread( xTaskGetIdleTaskHandle() );
@@ -250,24 +258,8 @@ BaseType_t xPortStartScheduler( void )
 
 void vPortEndScheduler( void )
 {
-    struct itimerval itimer;
-    struct sigaction sigtick;
     Thread_t * xCurrentThread;
 
-    /* Stop the timer and ignore any pending SIGALRMs that would end
-     * up running on the main thread when it is resumed. */
-    itimer.it_value.tv_sec = 0;
-    itimer.it_value.tv_usec = 0;
-
-    itimer.it_interval.tv_sec = 0;
-    itimer.it_interval.tv_usec = 0;
-    ( void ) setitimer( ITIMER_REAL, &itimer, NULL );
-
-    sigtick.sa_flags = 0;
-    sigtick.sa_handler = SIG_IGN;
-    sigemptyset( &sigtick.sa_mask );
-    sigaction( SIGALRM, &sigtick, NULL );
-
     /* Signal the scheduler to exit its loop. */
     xSchedulerEnd = pdTRUE;
     ( void ) pthread_kill( hMainThread, SIG_RESUME );
@@ -366,38 +358,31 @@ static uint64_t prvStartTimeNs;
  * to adjust timing according to full demo requirements */
 /* static uint64_t prvTickCount; */
 
+static void* prvTimerTickHandler(void *arg)
+{
+    while( xTimerTickThreadShouldRun )
+    {
+        /*
+         * signal to the active task to cause tick handling or
+         * preemption (if enabled)
+         */
+        Thread_t * thread = prvGetThreadFromTask( xTaskGetCurrentTaskHandle() );
+        pthread_kill( thread->pthread, SIGALRM );
+
+        usleep( portTICK_RATE_MICROSECONDS );
+    }
+
+    return NULL;
+}
+
 /*
  * Setup the systick timer to generate the tick interrupts at the required
  * frequency.
  */
 void prvSetupTimerInterrupt( void )
 {
-    struct itimerval itimer;
-    int iRet;
-
-    /* Initialise the structure with the current timer information. */
-    iRet = getitimer( ITIMER_REAL, &itimer );
-
-    if( iRet == -1 )
-    {
-        prvFatalError( "getitimer", errno );
-    }
-
-    /* Set the interval between timer events. */
-    itimer.it_interval.tv_sec = 0;
-    itimer.it_interval.tv_usec = portTICK_RATE_MICROSECONDS;
-
-    /* Set the current count-down. */
-    itimer.it_value.tv_sec = 0;
-    itimer.it_value.tv_usec = portTICK_RATE_MICROSECONDS;
-
-    /* Set-up the timer interrupt. */
-    iRet = setitimer( ITIMER_REAL, &itimer, NULL );
-
-    if( iRet == -1 )
-    {
-        prvFatalError( "setitimer", errno );
-    }
+    xTimerTickThreadShouldRun = true;
+    pthread_create( &hTimerTickThread, NULL, prvTimerTickHandler, NULL );
 
     prvStartTimeNs = prvGetTimeNs();
 }

From 88d3540b54d837f1e06e9dd3837316ca5f425c14 Mon Sep 17 00:00:00 2001
From: Chris Morgan <cmorgan@boston-engineering.com>
Date: Tue, 28 Nov 2023 08:57:37 -0500
Subject: [PATCH 178/424] POSIX port - Cancel and join all FreeRTOS managed
 pthreads upon shutdown

For a clean shutdown where memory is freed, it is necessary for all pthreads to be joined
at shutdown.

Previously there was explicit cancellation of the idle task and timer daemon task, however
there may be a number of other tasks in the system, both system created and user created,
and those tasks/threads were being left at shutdown.

This change calls pthread_cancel()/pthread_join() on all FreeRTOS managed pthreads upon
shutdown.
---
 portable/ThirdParty/GCC/Posix/port.c | 41 ++++++++++++++++++++++------
 1 file changed, 33 insertions(+), 8 deletions(-)

diff --git a/portable/ThirdParty/GCC/Posix/port.c b/portable/ThirdParty/GCC/Posix/port.c
index d312aa48d..c5864f823 100644
--- a/portable/ThirdParty/GCC/Posix/port.c
+++ b/portable/ThirdParty/GCC/Posix/port.c
@@ -69,6 +69,7 @@
 /* Scheduler includes. */
 #include "FreeRTOS.h"
 #include "task.h"
+#include "list.h"
 #include "timers.h"
 #include "utils/wait_for_event.h"
 /*-----------------------------------------------------------*/
@@ -82,6 +83,7 @@ typedef struct THREAD
     void * pvParams;
     BaseType_t xDying;
     struct event * ev;
+    ListItem_t xThreadListItem;
 } Thread_t;
 
 /*
@@ -102,6 +104,7 @@ static sigset_t xAllSignals;
 static sigset_t xSchedulerOriginalSignalMask;
 static pthread_t hMainThread = ( pthread_t ) NULL;
 static volatile BaseType_t uxCriticalNesting;
+static List_t xThreadList;
 /*-----------------------------------------------------------*/
 
 static pthread_t hTimerTickThread;
@@ -178,6 +181,11 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
 
     thread->ev = event_create();
 
+    /* Add the new thread in xThreadList. */
+    vListInitialiseItem( &thread->xThreadListItem );
+    listSET_LIST_ITEM_OWNER( &thread->xThreadListItem, thread );
+    vListInsertEnd( &xThreadList, &thread->xThreadListItem );
+
     vPortEnterCritical();
 
     iRet = pthread_create( &thread->pthread, &xThreadAttributes,
@@ -210,6 +218,8 @@ BaseType_t xPortStartScheduler( void )
 {
     int iSignal;
     sigset_t xSignals;
+    ListItem_t * pxIterator;
+    const ListItem_t * pxEndMarker;
 
     hMainThread = pthread_self();
 
@@ -239,15 +249,23 @@ BaseType_t xPortStartScheduler( void )
     xTimerTickThreadShouldRun = false;
     pthread_join( hTimerTickThread, NULL );
 
-    /* Cancel the Idle task and free its resources */
-    #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
-        vPortCancelThread( xTaskGetIdleTaskHandle() );
-    #endif
+    /*
+     * cancel and join any remaining pthreads
+     * to ensure their resources are freed
+     *
+     * https://stackoverflow.com/a/5612424
+     */
+    pxEndMarker = listGET_END_MARKER( &xThreadList );
+    for( pxIterator = listGET_HEAD_ENTRY( &xThreadList ); pxIterator != pxEndMarker; pxIterator = listGET_NEXT( pxIterator ) )
+    {
+        Thread_t *pxThread = ( Thread_t * ) listGET_LIST_ITEM_OWNER( pxIterator );
 
-    #if ( configUSE_TIMERS == 1 )
-        /* Cancel the Timer task and free its resources */
-        vPortCancelThread( xTimerGetTimerDaemonTaskHandle() );
-    #endif /* configUSE_TIMERS */
+        pthread_cancel( pxThread->pthread );
+        event_signal( pxThread->ev );
+
+        pthread_join( pxThread->pthread, NULL );
+        event_delete( pxThread->ev );
+    }
 
     /* Restore original signal mask. */
     ( void ) pthread_sigmask( SIG_SETMASK, &xSchedulerOriginalSignalMask, NULL );
@@ -444,10 +462,14 @@ void vPortCancelThread( void * pxTaskToDelete )
 {
     Thread_t * pxThreadToCancel = prvGetThreadFromTask( pxTaskToDelete );
 
+    /* Remove the thread from xThreadList. */
+    uxListRemove( &pxThreadToCancel->xThreadListItem );
+
     /*
      * The thread has already been suspended so it can be safely cancelled.
      */
     pthread_cancel( pxThreadToCancel->pthread );
+    event_signal( pxThreadToCancel->ev );
     pthread_join( pxThreadToCancel->pthread, NULL );
     event_delete( pxThreadToCancel->ev );
 }
@@ -543,6 +565,9 @@ static void prvSetupSignalsAndSchedulerPolicy( void )
 
     hMainThread = pthread_self();
 
+    /* Setup thread list to record all the task which are not deleted. */
+    vListInitialise( &xThreadList );
+
     /* Initialise common signal masks. */
     sigfillset( &xAllSignals );
 

From 6b698ff6bc539a932b28aa5220fc978a3d585667 Mon Sep 17 00:00:00 2001
From: "Ching-Hsin,Lee" <chinglee@amazon.com>
Date: Wed, 10 Jan 2024 05:08:03 +0000
Subject: [PATCH 179/424] Fix potential race condition

---
 portable/ThirdParty/GCC/Posix/port.c | 41 +++++++++++++---------------
 1 file changed, 19 insertions(+), 22 deletions(-)

diff --git a/portable/ThirdParty/GCC/Posix/port.c b/portable/ThirdParty/GCC/Posix/port.c
index c5864f823..34293f01a 100644
--- a/portable/ThirdParty/GCC/Posix/port.c
+++ b/portable/ThirdParty/GCC/Posix/port.c
@@ -105,11 +105,7 @@ static sigset_t xSchedulerOriginalSignalMask;
 static pthread_t hMainThread = ( pthread_t ) NULL;
 static volatile BaseType_t uxCriticalNesting;
 static List_t xThreadList;
-/*-----------------------------------------------------------*/
-
 static pthread_t hTimerTickThread;
-static bool xTimerTickThreadShouldRun;
-
 static BaseType_t xSchedulerEnd = pdFALSE;
 /*-----------------------------------------------------------*/
 
@@ -181,13 +177,14 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
 
     thread->ev = event_create();
 
-    /* Add the new thread in xThreadList. */
     vListInitialiseItem( &thread->xThreadListItem );
     listSET_LIST_ITEM_OWNER( &thread->xThreadListItem, thread );
-    vListInsertEnd( &xThreadList, &thread->xThreadListItem );
 
     vPortEnterCritical();
 
+    /* Add the new thread in xThreadList. */
+    vListInsertEnd( &xThreadList, &thread->xThreadListItem );
+
     iRet = pthread_create( &thread->pthread, &xThreadAttributes,
                            prvWaitForStart, thread );
 
@@ -245,10 +242,6 @@ BaseType_t xPortStartScheduler( void )
         sigwait( &xSignals, &iSignal );
     }
 
-    /* asking timer thread to shut down */
-    xTimerTickThreadShouldRun = false;
-    pthread_join( hTimerTickThread, NULL );
-
     /*
      * cancel and join any remaining pthreads
      * to ensure their resources are freed
@@ -261,8 +254,6 @@ BaseType_t xPortStartScheduler( void )
         Thread_t *pxThread = ( Thread_t * ) listGET_LIST_ITEM_OWNER( pxIterator );
 
         pthread_cancel( pxThread->pthread );
-        event_signal( pxThread->ev );
-
         pthread_join( pxThread->pthread, NULL );
         event_delete( pxThread->ev );
     }
@@ -276,14 +267,15 @@ BaseType_t xPortStartScheduler( void )
 
 void vPortEndScheduler( void )
 {
-    Thread_t * xCurrentThread;
+    /* Stop the timer tick thread. */
+    pthread_cancel( hTimerTickThread );
+    pthread_join( hTimerTickThread, NULL );
 
     /* Signal the scheduler to exit its loop. */
     xSchedulerEnd = pdTRUE;
     ( void ) pthread_kill( hMainThread, SIG_RESUME );
 
-    xCurrentThread = prvGetThreadFromTask( xTaskGetCurrentTaskHandle() );
-    prvSuspendSelf( xCurrentThread );
+    pthread_exit( NULL );
 }
 /*-----------------------------------------------------------*/
 
@@ -378,19 +370,24 @@ static uint64_t prvStartTimeNs;
 
 static void* prvTimerTickHandler(void *arg)
 {
-    while( xTimerTickThreadShouldRun )
+    for(;;)
     {
         /*
          * signal to the active task to cause tick handling or
          * preemption (if enabled)
          */
-        Thread_t * thread = prvGetThreadFromTask( xTaskGetCurrentTaskHandle() );
-        pthread_kill( thread->pthread, SIGALRM );
+        TaskHandle_t hCurrentTask;
+        Thread_t * thread;
 
+        hCurrentTask = xTaskGetCurrentTaskHandle();
+        if( hCurrentTask != NULL )
+        {
+            thread = prvGetThreadFromTask( hCurrentTask );
+            pthread_kill( thread->pthread, SIGALRM );
+        }
         usleep( portTICK_RATE_MICROSECONDS );
+	pthread_testcancel();
     }
-
-    return NULL;
 }
 
 /*
@@ -399,7 +396,6 @@ static void* prvTimerTickHandler(void *arg)
  */
 void prvSetupTimerInterrupt( void )
 {
-    xTimerTickThreadShouldRun = true;
     pthread_create( &hTimerTickThread, NULL, prvTimerTickHandler, NULL );
 
     prvStartTimeNs = prvGetTimeNs();
@@ -463,13 +459,14 @@ void vPortCancelThread( void * pxTaskToDelete )
     Thread_t * pxThreadToCancel = prvGetThreadFromTask( pxTaskToDelete );
 
     /* Remove the thread from xThreadList. */
+    vPortEnterCritical();
     uxListRemove( &pxThreadToCancel->xThreadListItem );
+    vPortExitCritical();
 
     /*
      * The thread has already been suspended so it can be safely cancelled.
      */
     pthread_cancel( pxThreadToCancel->pthread );
-    event_signal( pxThreadToCancel->ev );
     pthread_join( pxThreadToCancel->pthread, NULL );
     event_delete( pxThreadToCancel->ev );
 }

From 7ba4124c785e400cb0e8c3c17a49f390e90ba77e Mon Sep 17 00:00:00 2001
From: Ching-Hsin Lee <chinglee@amazon.com>
Date: Wed, 10 Jan 2024 13:18:55 +0800
Subject: [PATCH 180/424] Add back the pthread stack fit

---
 portable/ThirdParty/GCC/Posix/port.c | 37 ++++++++++++++++++----------
 1 file changed, 24 insertions(+), 13 deletions(-)

diff --git a/portable/ThirdParty/GCC/Posix/port.c b/portable/ThirdParty/GCC/Posix/port.c
index 34293f01a..391abe4ff 100644
--- a/portable/ThirdParty/GCC/Posix/port.c
+++ b/portable/ThirdParty/GCC/Posix/port.c
@@ -60,7 +60,6 @@
 #include <sys/time.h>
 #include <sys/times.h>
 #include <time.h>
-#include <unistd.h>
 
 #ifdef __APPLE__
     #include <mach/mach_vm.h>
@@ -104,9 +103,10 @@ static sigset_t xAllSignals;
 static sigset_t xSchedulerOriginalSignalMask;
 static pthread_t hMainThread = ( pthread_t ) NULL;
 static volatile BaseType_t uxCriticalNesting;
-static List_t xThreadList;
-static pthread_t hTimerTickThread;
 static BaseType_t xSchedulerEnd = pdFALSE;
+static pthread_t hTimerTickThread;
+static uint64_t prvStartTimeNs;
+static List_t xThreadList;             /* The list to track all the pthreads which are not deleted. */
 /*-----------------------------------------------------------*/
 
 static void prvSetupSignalsAndSchedulerPolicy( void );
@@ -130,6 +130,7 @@ void prvFatalError( const char * pcCall,
     fprintf( stderr, "%s: %s\n", pcCall, strerror( iErrno ) );
     abort();
 }
+/*-----------------------------------------------------------*/
 
 /*
  * See header file for description.
@@ -166,13 +167,15 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
     thread->pvParams = pvParameters;
     thread->xDying = pdFALSE;
 
+    /* Ensure ulStackSize is at least PTHREAD_STACK_MIN */
+    ulStackSize = ( ulStackSize < PTHREAD_STACK_MIN ) ? PTHREAD_STACK_MIN : ulStackSize;
+
     pthread_attr_init( &xThreadAttributes );
-    iRet = pthread_attr_setstack( &xThreadAttributes, pxEndOfStack, ulStackSize );
+    iRet = pthread_attr_setstacksize( &xThreadAttributes, ulStackSize );
 
     if( iRet != 0 )
     {
-        fprintf( stderr, "[WARN] pthread_attr_setstack failed with return value: %d. Default stack will be used.\n", iRet );
-        fprintf( stderr, "[WARN] Increase the stack size to PTHREAD_STACK_MIN.\n" );
+        fprintf( stderr, "[WARN] pthread_attr_setstacksize failed with return value: %d. Default stack size will be used.\n", iRet );
     }
 
     thread->ev = event_create();
@@ -242,13 +245,9 @@ BaseType_t xPortStartScheduler( void )
         sigwait( &xSignals, &iSignal );
     }
 
-    /*
-     * cancel and join any remaining pthreads
-     * to ensure their resources are freed
-     *
-     * https://stackoverflow.com/a/5612424
-     */
+    /* Cancel all the running thread. */
     pxEndMarker = listGET_END_MARKER( &xThreadList );
+
     for( pxIterator = listGET_HEAD_ENTRY( &xThreadList ); pxIterator != pxEndMarker; pxIterator = listGET_NEXT( pxIterator ) )
     {
         Thread_t *pxThread = ( Thread_t * ) listGET_LIST_ITEM_OWNER( pxIterator );
@@ -258,6 +257,16 @@ BaseType_t xPortStartScheduler( void )
         event_delete( pxThread->ev );
     }
 
+    /*
+     * clear out the variable that is used to end the scheduler, otherwise
+     * subsequent scheduler restarts will end immediately.
+     */
+    xSchedulerEnd = pdFALSE;
+
+    /* Reset the pthread_once_t structure. This is required if the port
+     * starts the scheduler again. */
+    hSigSetupThread = PTHREAD_ONCE_INIT;
+
     /* Restore original signal mask. */
     ( void ) pthread_sigmask( SIG_SETMASK, &xSchedulerOriginalSignalMask, NULL );
 
@@ -362,7 +371,7 @@ static uint64_t prvGetTimeNs( void )
     return ( uint64_t ) t.tv_sec * ( uint64_t ) 1000000000UL + ( uint64_t ) t.tv_nsec;
 }
 
-static uint64_t prvStartTimeNs;
+/*-----------------------------------------------------------*/
 
 /* commented as part of the code below in vPortSystemTickHandler,
  * to adjust timing according to full demo requirements */
@@ -453,6 +462,7 @@ void vPortThreadDying( void * pxTaskToDelete,
 
     pxThread->xDying = pdTRUE;
 }
+/*-----------------------------------------------------------*/
 
 void vPortCancelThread( void * pxTaskToDelete )
 {
@@ -542,6 +552,7 @@ static void prvSuspendSelf( Thread_t * thread )
      * - A thread with all signals blocked with pthread_sigmask().
      */
     event_wait( thread->ev );
+    pthread_testcancel();
 }
 
 /*-----------------------------------------------------------*/

From 3dade5b5a5a1378ccab80718a1f501f7485a0fa1 Mon Sep 17 00:00:00 2001
From: "Ching-Hsin,Lee" <chinglee@amazon.com>
Date: Wed, 10 Jan 2024 05:20:51 +0000
Subject: [PATCH 181/424] UPdate format

---
 portable/ThirdParty/GCC/Posix/port.c | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/portable/ThirdParty/GCC/Posix/port.c b/portable/ThirdParty/GCC/Posix/port.c
index 391abe4ff..d91255796 100644
--- a/portable/ThirdParty/GCC/Posix/port.c
+++ b/portable/ThirdParty/GCC/Posix/port.c
@@ -106,7 +106,7 @@ static volatile BaseType_t uxCriticalNesting;
 static BaseType_t xSchedulerEnd = pdFALSE;
 static pthread_t hTimerTickThread;
 static uint64_t prvStartTimeNs;
-static List_t xThreadList;             /* The list to track all the pthreads which are not deleted. */
+static List_t xThreadList; /* The list to track all the pthreads which are not deleted. */
 /*-----------------------------------------------------------*/
 
 static void prvSetupSignalsAndSchedulerPolicy( void );
@@ -250,7 +250,7 @@ BaseType_t xPortStartScheduler( void )
 
     for( pxIterator = listGET_HEAD_ENTRY( &xThreadList ); pxIterator != pxEndMarker; pxIterator = listGET_NEXT( pxIterator ) )
     {
-        Thread_t *pxThread = ( Thread_t * ) listGET_LIST_ITEM_OWNER( pxIterator );
+        Thread_t * pxThread = ( Thread_t * ) listGET_LIST_ITEM_OWNER( pxIterator );
 
         pthread_cancel( pxThread->pthread );
         pthread_join( pxThread->pthread, NULL );
@@ -377,9 +377,9 @@ static uint64_t prvGetTimeNs( void )
  * to adjust timing according to full demo requirements */
 /* static uint64_t prvTickCount; */
 
-static void* prvTimerTickHandler(void *arg)
+static void * prvTimerTickHandler( void * arg )
 {
-    for(;;)
+    for( ; ; )
     {
         /*
          * signal to the active task to cause tick handling or
@@ -389,13 +389,15 @@ static void* prvTimerTickHandler(void *arg)
         Thread_t * thread;
 
         hCurrentTask = xTaskGetCurrentTaskHandle();
+
         if( hCurrentTask != NULL )
         {
             thread = prvGetThreadFromTask( hCurrentTask );
             pthread_kill( thread->pthread, SIGALRM );
         }
+
         usleep( portTICK_RATE_MICROSECONDS );
-	pthread_testcancel();
+        pthread_testcancel();
     }
 }
 

From 0fac0859af251a7bf33ebfc6c3f00f3fe0d7d6c5 Mon Sep 17 00:00:00 2001
From: "Ching-Hsin,Lee" <chinglee@amazon.com>
Date: Wed, 10 Jan 2024 05:32:14 +0000
Subject: [PATCH 182/424] Add back heap setup code

---
 portable/ThirdParty/GCC/Posix/port.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/portable/ThirdParty/GCC/Posix/port.c b/portable/ThirdParty/GCC/Posix/port.c
index d91255796..04f883119 100644
--- a/portable/ThirdParty/GCC/Posix/port.c
+++ b/portable/ThirdParty/GCC/Posix/port.c
@@ -105,8 +105,9 @@ static pthread_t hMainThread = ( pthread_t ) NULL;
 static volatile BaseType_t uxCriticalNesting;
 static BaseType_t xSchedulerEnd = pdFALSE;
 static pthread_t hTimerTickThread;
+static bool xTimerTickThreadShouldRun;
 static uint64_t prvStartTimeNs;
-static List_t xThreadList; /* The list to track all the pthreads which are not deleted. */
+static List_t xThreadList;
 /*-----------------------------------------------------------*/
 
 static void prvSetupSignalsAndSchedulerPolicy( void );
@@ -277,7 +278,7 @@ BaseType_t xPortStartScheduler( void )
 void vPortEndScheduler( void )
 {
     /* Stop the timer tick thread. */
-    pthread_cancel( hTimerTickThread );
+    xTimerTickThreadShouldRun = false;
     pthread_join( hTimerTickThread, NULL );
 
     /* Signal the scheduler to exit its loop. */
@@ -370,7 +371,6 @@ static uint64_t prvGetTimeNs( void )
 
     return ( uint64_t ) t.tv_sec * ( uint64_t ) 1000000000UL + ( uint64_t ) t.tv_nsec;
 }
-
 /*-----------------------------------------------------------*/
 
 /* commented as part of the code below in vPortSystemTickHandler,
@@ -379,7 +379,7 @@ static uint64_t prvGetTimeNs( void )
 
 static void * prvTimerTickHandler( void * arg )
 {
-    for( ; ; )
+    while( xTimerTickThreadShouldRun )
     {
         /*
          * signal to the active task to cause tick handling or
@@ -399,7 +399,10 @@ static void * prvTimerTickHandler( void * arg )
         usleep( portTICK_RATE_MICROSECONDS );
         pthread_testcancel();
     }
+
+    return NULL;
 }
+/*-----------------------------------------------------------*/
 
 /*
  * Setup the systick timer to generate the tick interrupts at the required
@@ -407,6 +410,7 @@ static void * prvTimerTickHandler( void * arg )
  */
 void prvSetupTimerInterrupt( void )
 {
+    xTimerTickThreadShouldRun = true;
     pthread_create( &hTimerTickThread, NULL, prvTimerTickHandler, NULL );
 
     prvStartTimeNs = prvGetTimeNs();

From a7d39c3e3a1390c3e0cde3eda87a35edfa3181f6 Mon Sep 17 00:00:00 2001
From: "Ching-Hsin,Lee" <chinglee@amazon.com>
Date: Wed, 10 Jan 2024 05:38:18 +0000
Subject: [PATCH 183/424] format and header file

---
 portable/ThirdParty/GCC/Posix/port.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/portable/ThirdParty/GCC/Posix/port.c b/portable/ThirdParty/GCC/Posix/port.c
index 04f883119..43fff7f5d 100644
--- a/portable/ThirdParty/GCC/Posix/port.c
+++ b/portable/ThirdParty/GCC/Posix/port.c
@@ -60,6 +60,7 @@
 #include <sys/time.h>
 #include <sys/times.h>
 #include <time.h>
+#include <unistd.h>
 
 #ifdef __APPLE__
     #include <mach/mach_vm.h>

From 14903c380ea276f2766a5a096353da285831b2b8 Mon Sep 17 00:00:00 2001
From: "Ching-Hsin,Lee" <chinglee@amazon.com>
Date: Wed, 10 Jan 2024 05:39:27 +0000
Subject: [PATCH 184/424] Remove redundent cancellation point

---
 portable/ThirdParty/GCC/Posix/port.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/portable/ThirdParty/GCC/Posix/port.c b/portable/ThirdParty/GCC/Posix/port.c
index 43fff7f5d..4c61ff544 100644
--- a/portable/ThirdParty/GCC/Posix/port.c
+++ b/portable/ThirdParty/GCC/Posix/port.c
@@ -398,7 +398,6 @@ static void * prvTimerTickHandler( void * arg )
         }
 
         usleep( portTICK_RATE_MICROSECONDS );
-        pthread_testcancel();
     }
 
     return NULL;

From 5ed9c7022b9c95c33ca72ebbab40397f9386f24f Mon Sep 17 00:00:00 2001
From: "Ching-Hsin,Lee" <chinglee@amazon.com>
Date: Wed, 10 Jan 2024 05:45:02 +0000
Subject: [PATCH 185/424] Add back event signal

---
 portable/ThirdParty/GCC/Posix/port.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/portable/ThirdParty/GCC/Posix/port.c b/portable/ThirdParty/GCC/Posix/port.c
index 4c61ff544..f1bf2365e 100644
--- a/portable/ThirdParty/GCC/Posix/port.c
+++ b/portable/ThirdParty/GCC/Posix/port.c
@@ -255,6 +255,7 @@ BaseType_t xPortStartScheduler( void )
         Thread_t * pxThread = ( Thread_t * ) listGET_LIST_ITEM_OWNER( pxIterator );
 
         pthread_cancel( pxThread->pthread );
+        event_signal( pxThread->pthread );
         pthread_join( pxThread->pthread, NULL );
         event_delete( pxThread->ev );
     }
@@ -483,6 +484,7 @@ void vPortCancelThread( void * pxTaskToDelete )
      * The thread has already been suspended so it can be safely cancelled.
      */
     pthread_cancel( pxThreadToCancel->pthread );
+    event_signal( pxThreadToCancel->ev );
     pthread_join( pxThreadToCancel->pthread, NULL );
     event_delete( pxThreadToCancel->ev );
 }

From b6c0c51cbe74429fffb0ba48551907f4bb94eed6 Mon Sep 17 00:00:00 2001
From: "Ching-Hsin,Lee" <chinglee@amazon.com>
Date: Wed, 10 Jan 2024 05:48:35 +0000
Subject: [PATCH 186/424] Revert timer tick function

---
 portable/ThirdParty/GCC/Posix/port.c | 15 +++------------
 1 file changed, 3 insertions(+), 12 deletions(-)

diff --git a/portable/ThirdParty/GCC/Posix/port.c b/portable/ThirdParty/GCC/Posix/port.c
index f1bf2365e..4653d6f19 100644
--- a/portable/ThirdParty/GCC/Posix/port.c
+++ b/portable/ThirdParty/GCC/Posix/port.c
@@ -255,7 +255,7 @@ BaseType_t xPortStartScheduler( void )
         Thread_t * pxThread = ( Thread_t * ) listGET_LIST_ITEM_OWNER( pxIterator );
 
         pthread_cancel( pxThread->pthread );
-        event_signal( pxThread->pthread );
+        event_signal( pxThread->ev );
         pthread_join( pxThread->pthread, NULL );
         event_delete( pxThread->ev );
     }
@@ -387,17 +387,8 @@ static void * prvTimerTickHandler( void * arg )
          * signal to the active task to cause tick handling or
          * preemption (if enabled)
          */
-        TaskHandle_t hCurrentTask;
-        Thread_t * thread;
-
-        hCurrentTask = xTaskGetCurrentTaskHandle();
-
-        if( hCurrentTask != NULL )
-        {
-            thread = prvGetThreadFromTask( hCurrentTask );
-            pthread_kill( thread->pthread, SIGALRM );
-        }
-
+        Thread_t * thread = prvGetThreadFromTask( xTaskGetCurrentTaskHandle() );
+        pthread_kill( thread->pthread, SIGALRM );
         usleep( portTICK_RATE_MICROSECONDS );
     }
 

From 62220666ba11b038cf0bd2f3f29f54123ba20566 Mon Sep 17 00:00:00 2001
From: Ching-Hsin Lee <chinglee@amazon.com>
Date: Wed, 10 Jan 2024 20:30:46 +0800
Subject: [PATCH 187/424] Revert pthread_attr_setstacksize

---
 portable/ThirdParty/GCC/Posix/port.c | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/portable/ThirdParty/GCC/Posix/port.c b/portable/ThirdParty/GCC/Posix/port.c
index 4653d6f19..51d62b6ff 100644
--- a/portable/ThirdParty/GCC/Posix/port.c
+++ b/portable/ThirdParty/GCC/Posix/port.c
@@ -169,15 +169,13 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
     thread->pvParams = pvParameters;
     thread->xDying = pdFALSE;
 
-    /* Ensure ulStackSize is at least PTHREAD_STACK_MIN */
-    ulStackSize = ( ulStackSize < PTHREAD_STACK_MIN ) ? PTHREAD_STACK_MIN : ulStackSize;
-
     pthread_attr_init( &xThreadAttributes );
-    iRet = pthread_attr_setstacksize( &xThreadAttributes, ulStackSize );
+    iRet = pthread_attr_setstack( &xThreadAttributes, pxEndOfStack, ulStackSize );
 
     if( iRet != 0 )
     {
-        fprintf( stderr, "[WARN] pthread_attr_setstacksize failed with return value: %d. Default stack size will be used.\n", iRet );
+        fprintf( stderr, "[WARN] pthread_attr_setstack failed with return value: %d. Default stack will be used.\n", iRet );
+        fprintf( stderr, "[WARN] Increase the stack size to PTHREAD_STACK_MIN.\n" );
     }
 
     thread->ev = event_create();

From 3baa3dd98bb98ab58337f137747559b4f2cd24db Mon Sep 17 00:00:00 2001
From: Chris Morgan <cmorgan@boston-engineering.com>
Date: Wed, 29 Nov 2023 08:15:50 -0500
Subject: [PATCH 188/424] POSIX port - Switch from allowing the user to specify
 the stack memory itself, to allowing them to specify the stack size

Change from pthread_attr_setstack() to pthread_attr_setstacksize(), and automatically adjust the stack size
to be at least PTHREAD_STACK_MIN if it wasn't already, removing the size warning.

This permits the user to increase the pthread stack size beyond the PTHREAD_STACK_MIN default of 16384 if
desired, without producing a warning in the typical case where stacks are minimized for RAM limited targets.

Continue to store thread paramters on the provided stack, for consistency with the MCU targets.

Previously pthread_attr_setstack() was used to enable user defined stacks.

Note that:

1. The stack size can still be specified by the user.

2. pxPortInitialiseStack(), and pthread_addr_setstack() was failing on stacks of typical size, as
   these are smaller than PTHREAD_STACK_MIN (16384) bytes, and printing out a series of warnings.
   Improve usability by having the posix port automatically increase the stack size to be
   at least PTHREAD_STACK_MIN as posix platforms have enough memory for this not to be a concern.

3. Reuse of stack memory will also result in valgrind 'invalid write' errors to what is demonstrably
   valid memory. Root cause is that Valgrind is tracking a stack pointer as the stack is used.
   Reuse of a stack buffer results in the stack being used at its start, in an area that Valgrind thinks
   is far away from the start of the stack. There are ways to notify Valgrind of these changes
   however this would require linking against and calling Valgrind functions from the FreeRTOS application using
   the posix port, https://valgrind.org/docs/manual/manual-core-adv.html#manual-core-adv.clientreq.

   Also, apparently it isn't permitted by posix to reuse stack memory once its been used in a pthread via pthread_attr_setstack(),
   see https://stackoverflow.com/a/5422134
---
 portable/ThirdParty/GCC/Posix/port.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/portable/ThirdParty/GCC/Posix/port.c b/portable/ThirdParty/GCC/Posix/port.c
index 51d62b6ff..d5296183a 100644
--- a/portable/ThirdParty/GCC/Posix/port.c
+++ b/portable/ThirdParty/GCC/Posix/port.c
@@ -169,13 +169,15 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
     thread->pvParams = pvParameters;
     thread->xDying = pdFALSE;
 
+    /* Ensure ulStackSize is at least PTHREAD_STACK_MIN */
+    ulStackSize = (ulStackSize < PTHREAD_STACK_MIN) ? PTHREAD_STACK_MIN : ulStackSize;
+
     pthread_attr_init( &xThreadAttributes );
-    iRet = pthread_attr_setstack( &xThreadAttributes, pxEndOfStack, ulStackSize );
+    iRet = pthread_attr_setstacksize( &xThreadAttributes, ulStackSize );
 
     if( iRet != 0 )
     {
-        fprintf( stderr, "[WARN] pthread_attr_setstack failed with return value: %d. Default stack will be used.\n", iRet );
-        fprintf( stderr, "[WARN] Increase the stack size to PTHREAD_STACK_MIN.\n" );
+        fprintf( stderr, "[WARN] pthread_attr_setstacksize failed with return value: %d. Default stack size will be used.\n", iRet );
     }
 
     thread->ev = event_create();

From c053ffeacc655a8d2610c63f388f2fc1210b096d Mon Sep 17 00:00:00 2001
From: Tony Josi <tonyjosi@amazon.com>
Date: Sat, 13 Jan 2024 21:43:05 +0530
Subject: [PATCH 189/424] Fix -Werror=unused-parameter in GCC posix
 prvTimerTickHandler() (#949)

---
 portable/ThirdParty/GCC/Posix/port.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/portable/ThirdParty/GCC/Posix/port.c b/portable/ThirdParty/GCC/Posix/port.c
index d5296183a..d0152169a 100644
--- a/portable/ThirdParty/GCC/Posix/port.c
+++ b/portable/ThirdParty/GCC/Posix/port.c
@@ -381,6 +381,8 @@ static uint64_t prvGetTimeNs( void )
 
 static void * prvTimerTickHandler( void * arg )
 {
+    ( void ) arg;
+    
     while( xTimerTickThreadShouldRun )
     {
         /*

From c083af972ab1172aa09938e910ed9451053a9fcf Mon Sep 17 00:00:00 2001
From: IsaacDynamo <61521674+IsaacDynamo@users.noreply.github.com>
Date: Wed, 17 Jan 2024 21:22:32 +0100
Subject: [PATCH 190/424] Add mpu_wrappers_v2_asm.c to MPU ports (#951)

Co-authored-by: Soren Ptak <ptaksoren@gmail.com>
---
 portable/CMakeLists.txt | 80 ++++++++++++++++++++++++++++-------------
 1 file changed, 55 insertions(+), 25 deletions(-)

diff --git a/portable/CMakeLists.txt b/portable/CMakeLists.txt
index dea052d98..9df221d21 100644
--- a/portable/CMakeLists.txt
+++ b/portable/CMakeLists.txt
@@ -88,11 +88,13 @@ add_library(freertos_kernel_port STATIC
         GCC/ARM_CM3/port.c>
 
     $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM3_MPU>:
-        GCC/ARM_CM3_MPU/port.c>
+        GCC/ARM_CM3_MPU/port.c
+        GCC/ARM_CM3_MPU/mpu_wrappers_v2_asm.c>
 
     # ARMv7E-M ports for GCC
     $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM4_MPU>:
-        GCC/ARM_CM4_MPU/port.c>
+        GCC/ARM_CM4_MPU/port.c
+        GCC/ARM_CM4_MPU/mpu_wrappers_v2_asm.c>
 
     $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM4F>:
         GCC/ARM_CM4F/port.c>
@@ -103,7 +105,8 @@ add_library(freertos_kernel_port STATIC
     # ARMv8-M ports for GCC
     $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM23_NONSECURE>:
         GCC/ARM_CM23/non_secure/port.c
-        GCC/ARM_CM23/non_secure/portasm.c>
+        GCC/ARM_CM23/non_secure/portasm.c
+        GCC/ARM_CM23/non_secure/mpu_wrappers_v2_asm.c>
 
     $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM23_SECURE>:
         GCC/ARM_CM23/secure/secure_context_port.c
@@ -113,11 +116,13 @@ add_library(freertos_kernel_port STATIC
 
     $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM23_NTZ_NONSECURE>:
         GCC/ARM_CM23_NTZ/non_secure/port.c
-        GCC/ARM_CM23_NTZ/non_secure/portasm.c>
+        GCC/ARM_CM23_NTZ/non_secure/portasm.c
+        GCC/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.c>
 
     $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM33_NONSECURE>:
         GCC/ARM_CM33/non_secure/port.c
-        GCC/ARM_CM33/non_secure/portasm.c>
+        GCC/ARM_CM33/non_secure/portasm.c
+        GCC/ARM_CM33/non_secure/mpu_wrappers_v2_asm.c>
 
     $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM33_SECURE>:
         GCC/ARM_CM33/secure/secure_context_port.c
@@ -127,16 +132,19 @@ add_library(freertos_kernel_port STATIC
 
     $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM33_NTZ_NONSECURE>:
         GCC/ARM_CM33_NTZ/non_secure/port.c
-        GCC/ARM_CM33_NTZ/non_secure/portasm.c>
+        GCC/ARM_CM33_NTZ/non_secure/portasm.c
+        GCC/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.c>
 
     $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM33_TFM>:
         GCC/ARM_CM33_NTZ/non_secure/port.c
         GCC/ARM_CM33_NTZ/non_secure/portasm.c
+        GCC/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.c
         ThirdParty/GCC/ARM_TFM/os_wrapper_freertos.c>
 
     $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM35P_NONSECURE>:
         GCC/ARM_CM35P/non_secure/port.c
-        GCC/ARM_CM35P/non_secure/portasm.c>
+        GCC/ARM_CM35P/non_secure/portasm.c
+        GCC/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.c>
 
     $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM35P_SECURE>:
         GCC/ARM_CM35P/secure/secure_context_port.c
@@ -146,12 +154,14 @@ add_library(freertos_kernel_port STATIC
 
     $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM35P_NTZ_NONSECURE>:
         GCC/ARM_CM35P_NTZ/non_secure/port.c
-        GCC/ARM_CM35P_NTZ/non_secure/portasm.c>
+        GCC/ARM_CM35P_NTZ/non_secure/portasm.c
+        GCC/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.c>
 
     # ARMv8.1-M ports for GCC
     $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM55_NONSECURE>:
         GCC/ARM_CM55/non_secure/port.c
-        GCC/ARM_CM55/non_secure/portasm.c>
+        GCC/ARM_CM55/non_secure/portasm.c
+        GCC/ARM_CM55/non_secure/mpu_wrappers_v2_asm.c>
 
     $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM55_SECURE>:
         GCC/ARM_CM55/secure/secure_context_port.c
@@ -161,16 +171,19 @@ add_library(freertos_kernel_port STATIC
 
     $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM55_NTZ_NONSECURE>:
         GCC/ARM_CM55_NTZ/non_secure/port.c
-        GCC/ARM_CM55_NTZ/non_secure/portasm.c>
+        GCC/ARM_CM55_NTZ/non_secure/portasm.c
+        GCC/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.c>
 
     $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM55_TFM>:
         GCC/ARM_CM55_NTZ/non_secure/port.c
         GCC/ARM_CM55_NTZ/non_secure/portasm.c
+        GCC/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.c
         ThirdParty/GCC/ARM_TFM/os_wrapper_freertos.c>
 
     $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM85_NONSECURE>:
         GCC/ARM_CM85/non_secure/port.c
-        GCC/ARM_CM85/non_secure/portasm.c>
+        GCC/ARM_CM85/non_secure/portasm.c
+        GCC/ARM_CM85/non_secure/mpu_wrappers_v2_asm.c>
 
     $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM85_SECURE>:
         GCC/ARM_CM85/secure/secure_context_port.c
@@ -180,11 +193,13 @@ add_library(freertos_kernel_port STATIC
 
     $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM85_NTZ_NONSECURE>:
         GCC/ARM_CM85_NTZ/non_secure/port.c
-        GCC/ARM_CM85_NTZ/non_secure/portasm.c>
+        GCC/ARM_CM85_NTZ/non_secure/portasm.c
+        GCC/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.c>
 
     $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM85_TFM>:
         GCC/ARM_CM85_NTZ/non_secure/port.c
         GCC/ARM_CM85_NTZ/non_secure/portasm.c
+        GCC/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.c
         ThirdParty/GCC/ARM_TFM/os_wrapper_freertos.c>
 
     # ARMv7-R ports for GCC
@@ -391,7 +406,8 @@ add_library(freertos_kernel_port STATIC
 
     $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM4F_MPU>:
         IAR/ARM_CM4F_MPU/port.c
-        IAR/ARM_CM4F_MPU/portasm.s>
+        IAR/ARM_CM4F_MPU/portasm.s
+        IAR/ARM_CM4F_MPU/mpu_wrappers_v2_asm.S>
 
     $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM7>:
         IAR/ARM_CM7/r0p1/port.c
@@ -400,7 +416,8 @@ add_library(freertos_kernel_port STATIC
     # ARMv8-M Ports for IAR EWARM
     $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM23_NONSECURE>:
         IAR/ARM_CM23/non_secure/port.c
-        IAR/ARM_CM23/non_secure/portasm.s>
+        IAR/ARM_CM23/non_secure/portasm.s
+        IAR/ARM_CM23/non_secure/mpu_wrappers_v2_asm.S>
 
     $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM23_SECURE>:
         IAR/ARM_CM23/secure/secure_context_port_asm.s
@@ -410,11 +427,13 @@ add_library(freertos_kernel_port STATIC
 
     $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM23_NTZ_NONSECURE>:
         IAR/ARM_CM23_NTZ/non_secure/port.c
-        IAR/ARM_CM23_NTZ/non_secure/portasm.s>
+        IAR/ARM_CM23_NTZ/non_secure/portasm.s
+        IAR/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.S>
 
     $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM33_NONSECURE>:
         IAR/ARM_CM33/non_secure/port.c
-        IAR/ARM_CM33/non_secure/portasm.s>
+        IAR/ARM_CM33/non_secure/portasm.s
+        IAR/ARM_CM33/non_secure/mpu_wrappers_v2_asm.S>
 
     $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM33_SECURE>:
         IAR/ARM_CM33/secure/secure_context_port_asm.s
@@ -424,11 +443,13 @@ add_library(freertos_kernel_port STATIC
 
     $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM33_NTZ_NONSECURE>:
         IAR/ARM_CM33_NTZ/non_secure/port.c
-        IAR/ARM_CM33_NTZ/non_secure/portasm.s>
+        IAR/ARM_CM33_NTZ/non_secure/portasm.s
+        IAR/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.S>
 
     $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM35P_NONSECURE>:
         IAR/ARM_CM35P/non_secure/port.c
-        IAR/ARM_CM35P/non_secure/portasm.s>
+        IAR/ARM_CM35P/non_secure/portasm.s
+        IAR/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.S>
 
     $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM35P_SECURE>:
         IAR/ARM_CM35P/secure/secure_context_port_asm.s
@@ -438,12 +459,14 @@ add_library(freertos_kernel_port STATIC
 
     $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM35P_NTZ_NONSECURE>:
         IAR/ARM_CM35P_NTZ/non_secure/port.c
-        IAR/ARM_CM35P_NTZ/non_secure/portasm.s>
+        IAR/ARM_CM35P_NTZ/non_secure/portasm.s
+        IAR/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.S>
 
     # ARMv8.1-M ports for IAR EWARM
     $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM55_NONSECURE>:
         IAR/ARM_CM55/non_secure/port.c
-        IAR/ARM_CM55/non_secure/portasm.s>
+        IAR/ARM_CM55/non_secure/portasm.s
+        IAR/ARM_CM55/non_secure/mpu_wrappers_v2_asm.S>
 
     $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM55_SECURE>:
         IAR/ARM_CM55/secure/secure_context_port_asm.s
@@ -453,11 +476,13 @@ add_library(freertos_kernel_port STATIC
 
     $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM55_NTZ_NONSECURE>:
         IAR/ARM_CM55_NTZ/non_secure/port.c
-        IAR/ARM_CM55_NTZ/non_secure/portasm.s>
+        IAR/ARM_CM55_NTZ/non_secure/portasm.s
+        IAR/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.S>
 
     $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM85_NONSECURE>:
         IAR/ARM_CM85/non_secure/port.c
-        IAR/ARM_CM85/non_secure/portasm.s>
+        IAR/ARM_CM85/non_secure/portasm.s
+        IAR/ARM_CM85/non_secure/mpu_wrappers_v2_asm.S>
 
     $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM85_SECURE>:
         IAR/ARM_CM85/secure/secure_context_port_asm.s
@@ -467,7 +492,8 @@ add_library(freertos_kernel_port STATIC
 
     $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM85_NTZ_NONSECURE>:
         IAR/ARM_CM85_NTZ/non_secure/port.c
-        IAR/ARM_CM85_NTZ/non_secure/portasm.s>
+        IAR/ARM_CM85_NTZ/non_secure/portasm.s
+        IAR/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.S>
 
     # ARMv7-R Ports for IAR EWARM
     $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CRX_NOGIC>:
@@ -659,7 +685,8 @@ add_library(freertos_kernel_port STATIC
 
     # ARMv7E-M ports for ARM RVDS / armcc
     $<$<STREQUAL:${FREERTOS_PORT},RVDS_ARM_CM4_MPU>:
-        RVDS/ARM_CM4_MPU/port.c>
+        RVDS/ARM_CM4_MPU/port.c
+        RVDS/ARM_CM4_MPU/mpu_wrappers_v2_asm.c>
 
     $<$<STREQUAL:${FREERTOS_PORT},RVDS_ARM_CM4F>:
         RVDS/ARM_CM4F/port.c>
@@ -723,7 +750,10 @@ if( FREERTOS_PORT MATCHES "GCC_ARM_CM(3|4)_MPU" OR
     FREERTOS_PORT MATCHES "IAR_ARM_CM(23|33|55|85)_NTZ_NONSECURE" OR
     FREERTOS_PORT MATCHES "IAR_ARM_CM(23|33|55|85)_NONSECURE"
 )
-    target_sources(freertos_kernel_port PRIVATE Common/mpu_wrappers.c)
+    target_sources(freertos_kernel_port PRIVATE
+        Common/mpu_wrappers.c
+        Common/mpu_wrappers_v2.c
+    )
 endif()
 
 target_include_directories(freertos_kernel_port PUBLIC

From aa07289c24dd631a7d3d55781a9c5fa9017d5db8 Mon Sep 17 00:00:00 2001
From: IsaacDynamo <61521674+IsaacDynamo@users.noreply.github.com>
Date: Thu, 18 Jan 2024 20:02:41 +0100
Subject: [PATCH 191/424] Make configSUPPORT_STATIC_ALLOCATION==1 an error for
 MPU ports (#953)

* Error when configSUPPORT_STATIC_ALLOCATION is set for MPU ports

* Uncrustify: triggered by comment.

---------

Co-authored-by: GitHub Action <action@github.com>
Co-authored-by: Soren Ptak <ptaksoren@gmail.com>
---
 tasks.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/tasks.c b/tasks.c
index 93e9c02c4..d00e96674 100644
--- a/tasks.c
+++ b/tasks.c
@@ -41,6 +41,13 @@
 #include "timers.h"
 #include "stack_macros.h"
 
+/* The default definitions are only available for non-MPU ports. The
+ * reason is that the stack alignment requirements vary for different
+ * architectures.*/
+#if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configKERNEL_PROVIDED_STATIC_MEMORY == 1 ) && ( portUSING_MPU_WRAPPERS != 0 ) )
+    #error configKERNEL_PROVIDED_STATIC_MEMORY cannot be set to 1 when using an MPU port. The vApplicationGet*TaskMemory() functions must be provided manually.
+#endif
+
 /* The MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
  * for the header files above, but not in this file, in order to generate the
  * correct privileged Vs unprivileged linkage and placement. */

From 52ab3d0f22bce9195bc965ebc56beec6d57a558b Mon Sep 17 00:00:00 2001
From: IsaacDynamo <61521674+IsaacDynamo@users.noreply.github.com>
Date: Thu, 18 Jan 2024 20:12:21 +0100
Subject: [PATCH 192/424] MPU assert for ARM_CM3_MPU (#952)

* Add runtime check to see if the target even has a MPU

* Add missing extern symbols for __ARMCC_VERSION support

* Add default for configTOTAL_MPU_REGIONS and change a runtime assert to compile time error

* Simplify check and link to reference documentation

Co-authored-by: Soren Ptak <ptaksoren@gmail.com>

---------

Co-authored-by: Soren Ptak <ptaksoren@gmail.com>
Co-authored-by: jasonpcarroll <23126711+jasonpcarroll@users.noreply.github.com>
---
 portable/GCC/ARM_CM3_MPU/port.c      | 48 ++++++++++++++++++++++------
 portable/GCC/ARM_CM3_MPU/portmacro.h |  9 ++++++
 2 files changed, 47 insertions(+), 10 deletions(-)

diff --git a/portable/GCC/ARM_CM3_MPU/port.c b/portable/GCC/ARM_CM3_MPU/port.c
index d8c18325c..fad62ff75 100644
--- a/portable/GCC/ARM_CM3_MPU/port.c
+++ b/portable/GCC/ARM_CM3_MPU/port.c
@@ -1095,12 +1095,28 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
 
 static void prvSetupMPU( void )
 {
-    extern uint32_t __privileged_functions_start__[];
-    extern uint32_t __privileged_functions_end__[];
-    extern uint32_t __FLASH_segment_start__[];
-    extern uint32_t __FLASH_segment_end__[];
-    extern uint32_t __privileged_data_start__[];
-    extern uint32_t __privileged_data_end__[];
+    #if defined( __ARMCC_VERSION )
+
+        /* Declaration when these variable are defined in code instead of being
+         * exported from linker scripts. */
+        extern uint32_t * __privileged_functions_start__;
+        extern uint32_t * __privileged_functions_end__;
+        extern uint32_t * __FLASH_segment_start__;
+        extern uint32_t * __FLASH_segment_end__;
+        extern uint32_t * __privileged_data_start__;
+        extern uint32_t * __privileged_data_end__;
+    #else
+        /* Declaration when these variable are exported from linker scripts. */
+        extern uint32_t __privileged_functions_start__[];
+        extern uint32_t __privileged_functions_end__[];
+        extern uint32_t __FLASH_segment_start__[];
+        extern uint32_t __FLASH_segment_end__[];
+        extern uint32_t __privileged_data_start__[];
+        extern uint32_t __privileged_data_end__[];
+    #endif /* if defined( __ARMCC_VERSION ) */
+
+    /* Ensure that the device has the expected MPU type */
+    configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
 
     /* Check the expected MPU is present. */
     if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
@@ -1229,10 +1245,22 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
                                 StackType_t * pxBottomOfStack,
                                 uint32_t ulStackDepth )
 {
-    extern uint32_t __SRAM_segment_start__[];
-    extern uint32_t __SRAM_segment_end__[];
-    extern uint32_t __privileged_data_start__[];
-    extern uint32_t __privileged_data_end__[];
+    #if defined( __ARMCC_VERSION )
+
+        /* Declaration when these variable are defined in code instead of being
+         * exported from linker scripts. */
+        extern uint32_t * __SRAM_segment_start__;
+        extern uint32_t * __SRAM_segment_end__;
+        extern uint32_t * __privileged_data_start__;
+        extern uint32_t * __privileged_data_end__;
+    #else
+        /* Declaration when these variable are exported from linker scripts. */
+        extern uint32_t __SRAM_segment_start__[];
+        extern uint32_t __SRAM_segment_end__[];
+        extern uint32_t __privileged_data_start__[];
+        extern uint32_t __privileged_data_end__[];
+    #endif /* if defined( __ARMCC_VERSION ) */
+
     int32_t lIndex;
     uint32_t ul;
 
diff --git a/portable/GCC/ARM_CM3_MPU/portmacro.h b/portable/GCC/ARM_CM3_MPU/portmacro.h
index 5983c7912..a6e2ae261 100644
--- a/portable/GCC/ARM_CM3_MPU/portmacro.h
+++ b/portable/GCC/ARM_CM3_MPU/portmacro.h
@@ -86,6 +86,15 @@ typedef unsigned long    UBaseType_t;
 #define portMPU_REGION_CACHEABLE_BUFFERABLE                      ( 0x07UL << 16UL )
 #define portMPU_REGION_EXECUTE_NEVER                             ( 0x01UL << 28UL )
 
+/* MPU settings that can be overriden in FreeRTOSConfig.h. */
+#ifndef configTOTAL_MPU_REGIONS
+    /* Define to 8 for backward compatibility. */
+    #define configTOTAL_MPU_REGIONS    ( 8UL )
+#elif( configTOTAL_MPU_REGIONS != 8UL )
+    /* The Cortex M3 only supports 8 MPU regions. For more information refer to:
+     * https://developer.arm.com/documentation/dui0552/a/cortex-m3-peripherals/optional-memory-protection-unit */
+    #error configTOTAL_MPU_REGIONS must be 8 for this port.
+#endif /* configTOTAL_MPU_REGIONS Check */
 #define portSTACK_REGION                                         ( 3UL )
 #define portGENERAL_PERIPHERALS_REGION                           ( 4UL )
 #define portUNPRIVILEGED_FLASH_REGION                            ( 5UL )

From e6f6d0ecf4a96bcd6e23e3334ac463056f939be8 Mon Sep 17 00:00:00 2001
From: Mikhail Paulyshka <me@mixaill.net>
Date: Thu, 18 Jan 2024 22:35:16 +0300
Subject: [PATCH 193/424] Posix port - set name for threads (#950)

Co-authored-by: jasonpcarroll <23126711+jasonpcarroll@users.noreply.github.com>
---
 portable/ThirdParty/GCC/Posix/port.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/portable/ThirdParty/GCC/Posix/port.c b/portable/ThirdParty/GCC/Posix/port.c
index d0152169a..f84517346 100644
--- a/portable/ThirdParty/GCC/Posix/port.c
+++ b/portable/ThirdParty/GCC/Posix/port.c
@@ -51,6 +51,10 @@
 *----------------------------------------------------------*/
 #include "portmacro.h"
 
+#ifdef __linux__
+    #define __USE_GNU
+#endif
+
 #include <errno.h>
 #include <pthread.h>
 #include <signal.h>
@@ -134,6 +138,16 @@ void prvFatalError( const char * pcCall,
 }
 /*-----------------------------------------------------------*/
 
+static void prvPortSetCurrentThreadName(char * pxThreadName)
+{
+#ifdef __APPLE__
+    pthread_setname_np(pxThreadName);
+#else
+    pthread_setname_np(pthread_self(), pxThreadName);
+#endif
+}
+/*-----------------------------------------------------------*/
+
 /*
  * See header file for description.
  */
@@ -224,6 +238,7 @@ BaseType_t xPortStartScheduler( void )
     const ListItem_t * pxEndMarker;
 
     hMainThread = pthread_self();
+    prvPortSetCurrentThreadName("Scheduler");
 
     /* Start the timer that generates the tick ISR(SIGALRM).
      * Interrupts are disabled here already. */
@@ -383,6 +398,8 @@ static void * prvTimerTickHandler( void * arg )
 {
     ( void ) arg;
     
+    prvPortSetCurrentThreadName("Scheduler timer");
+
     while( xTimerTickThreadShouldRun )
     {
         /*
@@ -493,6 +510,9 @@ static void * prvWaitForStart( void * pvParams )
     uxCriticalNesting = 0;
     vPortEnableInterrupts();
 
+    /* Set thread name */
+    prvPortSetCurrentThreadName(pcTaskGetName(xTaskGetCurrentTaskHandle()));
+
     /* Call the task's entry point. */
     pxThread->pxCode( pxThread->pvParams );
 

From cf2366c949735eec9c5eee83b5909bb913cd1679 Mon Sep 17 00:00:00 2001
From: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Date: Tue, 23 Jan 2024 17:02:15 +0800
Subject: [PATCH 194/424] Update unpaired critical section in vTaskDelete for
 readability (#958)

* Modify unpaired critical section for readability
* Move prvDeleteTCB out of critical section for SMP

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 tasks.c | 73 ++++++++++++++++++++++++++++-----------------------------
 1 file changed, 36 insertions(+), 37 deletions(-)

diff --git a/tasks.c b/tasks.c
index d00e96674..4a640d611 100644
--- a/tasks.c
+++ b/tasks.c
@@ -2190,6 +2190,7 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
     void vTaskDelete( TaskHandle_t xTaskToDelete )
     {
         TCB_t * pxTCB;
+        BaseType_t xDeleteTCBInIdleTask = pdFALSE;
 
         traceENTER_vTaskDelete( xTaskToDelete );
 
@@ -2247,6 +2248,9 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
                  * portPRE_TASK_DELETE_HOOK() does not return in the Win32 port. */
                 traceTASK_DELETE( pxTCB );
 
+                /* Delete the task TCB in idle task. */
+                xDeleteTCBInIdleTask = pdTRUE;
+
                 /* The pre-delete hook is primarily for the Windows simulator,
                  * in which Windows specific clean up operations are performed,
                  * after which it is not possible to yield away from this task -
@@ -2268,61 +2272,56 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
                 prvResetNextTaskUnblockTime();
             }
         }
+        taskEXIT_CRITICAL();
 
-        #if ( configNUMBER_OF_CORES == 1 )
+        /* If the task is not deleting itself, call prvDeleteTCB from outside of
+         * critical section. If a task deletes itself, prvDeleteTCB is called
+         * from prvCheckTasksWaitingTermination which is called from Idle task. */
+        if( xDeleteTCBInIdleTask != pdTRUE )
         {
-            taskEXIT_CRITICAL();
+            prvDeleteTCB( pxTCB );
+        }
 
-            /* If the task is not deleting itself, call prvDeleteTCB from outside of
-             * critical section. If a task deletes itself, prvDeleteTCB is called
-             * from prvCheckTasksWaitingTermination which is called from Idle task. */
-            if( pxTCB != pxCurrentTCB )
-            {
-                prvDeleteTCB( pxTCB );
-            }
-
-            /* Force a reschedule if it is the currently running task that has just
-             * been deleted. */
-            if( xSchedulerRunning != pdFALSE )
+        /* Force a reschedule if it is the currently running task that has just
+         * been deleted. */
+        if( xSchedulerRunning != pdFALSE )
+        {
+            #if ( configNUMBER_OF_CORES == 1 )
             {
                 if( pxTCB == pxCurrentTCB )
                 {
                     configASSERT( uxSchedulerSuspended == 0 );
-                    portYIELD_WITHIN_API();
+                    taskYIELD_WITHIN_API();
                 }
                 else
                 {
                     mtCOVERAGE_TEST_MARKER();
                 }
             }
-        }
-        #else /* #if ( configNUMBER_OF_CORES == 1 ) */
-        {
-            /* If a running task is not deleting itself, call prvDeleteTCB. If a running
-             * task deletes itself, prvDeleteTCB is called from prvCheckTasksWaitingTermination
-             * which is called from Idle task. */
-            if( pxTCB->xTaskRunState == taskTASK_NOT_RUNNING )
+            #else /* #if ( configNUMBER_OF_CORES == 1 ) */
             {
-                prvDeleteTCB( pxTCB );
-            }
-
-            /* Force a reschedule if the task that has just been deleted was running. */
-            if( ( xSchedulerRunning != pdFALSE ) && ( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE ) )
-            {
-                if( pxTCB->xTaskRunState == ( BaseType_t ) portGET_CORE_ID() )
+                /* It is important to use critical section here because
+                 * checking run state of a task must be done inside a
+                 * critical section. */
+                taskENTER_CRITICAL();
                 {
-                    configASSERT( uxSchedulerSuspended == 0 );
-                    vTaskYieldWithinAPI();
-                }
-                else
-                {
-                    prvYieldCore( pxTCB->xTaskRunState );
+                    if( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE )
+                    {
+                        if( pxTCB->xTaskRunState == ( BaseType_t ) portGET_CORE_ID() )
+                        {
+                            configASSERT( uxSchedulerSuspended == 0 );
+                            taskYIELD_WITHIN_API();
+                        }
+                        else
+                        {
+                            prvYieldCore( pxTCB->xTaskRunState );
+                        }
+                    }
                 }
+                taskEXIT_CRITICAL();
             }
-
-            taskEXIT_CRITICAL();
+            #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
         }
-        #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
 
         traceRETURN_vTaskDelete();
     }

From 4d9f6522e574410a20cb1430aaa1a667a564ec4b Mon Sep 17 00:00:00 2001
From: Soren Ptak <ptaksoren@gmail.com>
Date: Tue, 23 Jan 2024 14:48:20 -0500
Subject: [PATCH 195/424] Add check for if the scheduler is running to MPU
 ports (#954)

* In the ARM_CM3_MPU and ARM_CM4_MPU Port function xPortIsAuthorizedToAccessBuffer() grant access to the buffer if xSchedulerRunning is false.
---
 portable/GCC/ARM_CM3_MPU/port.c  | 10 +++++++++-
 portable/GCC/ARM_CM4_MPU/port.c  | 10 +++++++++-
 portable/IAR/ARM_CM4F_MPU/port.c | 10 +++++++++-
 portable/RVDS/ARM_CM4_MPU/port.c | 11 ++++++++++-
 4 files changed, 37 insertions(+), 4 deletions(-)

diff --git a/portable/GCC/ARM_CM3_MPU/port.c b/portable/GCC/ARM_CM3_MPU/port.c
index fad62ff75..521ceaec3 100644
--- a/portable/GCC/ARM_CM3_MPU/port.c
+++ b/portable/GCC/ARM_CM3_MPU/port.c
@@ -1380,7 +1380,15 @@ BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
     BaseType_t xAccessGranted = pdFALSE;
     const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
 
-    if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+    if( xSchedulerRunning == pdFALSE )
+    {
+        /* Grant access to all the kernel objects before the scheduler
+         * is started. It is necessary because there is no task running
+         * yet and therefore, we cannot use the permissions of any
+         * task. */
+        xAccessGranted = pdTRUE;
+    }
+    else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
     {
         xAccessGranted = pdTRUE;
     }
diff --git a/portable/GCC/ARM_CM4_MPU/port.c b/portable/GCC/ARM_CM4_MPU/port.c
index 0775cfbf8..ce234c455 100644
--- a/portable/GCC/ARM_CM4_MPU/port.c
+++ b/portable/GCC/ARM_CM4_MPU/port.c
@@ -1523,7 +1523,15 @@ BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
     BaseType_t xAccessGranted = pdFALSE;
     const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
 
-    if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+    if( xSchedulerRunning == pdFALSE )
+    {
+        /* Grant access to all the kernel objects before the scheduler
+         * is started. It is necessary because there is no task running
+         * yet and therefore, we cannot use the permissions of any
+         * task. */
+        xAccessGranted = pdTRUE;
+    }
+    else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
     {
         xAccessGranted = pdTRUE;
     }
diff --git a/portable/IAR/ARM_CM4F_MPU/port.c b/portable/IAR/ARM_CM4F_MPU/port.c
index c3bab2671..a682a9d87 100644
--- a/portable/IAR/ARM_CM4F_MPU/port.c
+++ b/portable/IAR/ARM_CM4F_MPU/port.c
@@ -1253,7 +1253,15 @@ BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
     BaseType_t xAccessGranted = pdFALSE;
     const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
 
-    if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+    if( xSchedulerRunning == pdFALSE )
+    {
+        /* Grant access to all the kernel objects before the scheduler
+         * is started. It is necessary because there is no task running
+         * yet and therefore, we cannot use the permissions of any
+         * task. */
+        xAccessGranted = pdTRUE;
+    }
+    else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
     {
         xAccessGranted = pdTRUE;
     }
diff --git a/portable/RVDS/ARM_CM4_MPU/port.c b/portable/RVDS/ARM_CM4_MPU/port.c
index af4ea632f..364370109 100644
--- a/portable/RVDS/ARM_CM4_MPU/port.c
+++ b/portable/RVDS/ARM_CM4_MPU/port.c
@@ -1508,7 +1508,16 @@ BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
     BaseType_t xAccessGranted = pdFALSE;
     const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
 
-    if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+    
+    if( xSchedulerRunning == pdFALSE )
+    {
+        /* Grant access to all the kernel objects before the scheduler
+         * is started. It is necessary because there is no task running
+         * yet and therefore, we cannot use the permissions of any
+         * task. */
+        xAccessGranted = pdTRUE;
+    }
+    else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
     {
         xAccessGranted = pdTRUE;
     }

From 72c7d862762425832d9fce2df7b03d2ad355cb1e Mon Sep 17 00:00:00 2001
From: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Date: Wed, 24 Jan 2024 19:48:31 +0800
Subject: [PATCH 196/424] Update for unpaired critical section in vTaskSuspend
 (#959)

* Move the taskEXIT_CRITICAL out of the configNUMBER_OF_CORES macro block to improve readability.
---
 tasks.c | 89 +++++++++++++++++++++++----------------------------------
 1 file changed, 36 insertions(+), 53 deletions(-)

diff --git a/tasks.c b/tasks.c
index 4a640d611..26a442637 100644
--- a/tasks.c
+++ b/tasks.c
@@ -3107,10 +3107,6 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
     {
         TCB_t * pxTCB;
 
-        #if ( configNUMBER_OF_CORES > 1 )
-            BaseType_t xTaskRunningOnCore;
-        #endif
-
         traceENTER_vTaskSuspend( xTaskToSuspend );
 
         taskENTER_CRITICAL();
@@ -3121,10 +3117,6 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
 
             traceTASK_SUSPEND( pxTCB );
 
-            #if ( configNUMBER_OF_CORES > 1 )
-                xTaskRunningOnCore = pxTCB->xTaskRunState;
-            #endif
-
             /* Remove task from the ready/delayed list and place in the
              * suspended list. */
             if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
@@ -3164,26 +3156,25 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
             }
             #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
         }
+        taskEXIT_CRITICAL();
+
+        if( xSchedulerRunning != pdFALSE )
+        {
+            /* Reset the next expected unblock time in case it referred to the
+             * task that is now in the Suspended state. */
+            taskENTER_CRITICAL();
+            {
+                prvResetNextTaskUnblockTime();
+            }
+            taskEXIT_CRITICAL();
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
 
         #if ( configNUMBER_OF_CORES == 1 )
         {
-            taskEXIT_CRITICAL();
-
-            if( xSchedulerRunning != pdFALSE )
-            {
-                /* Reset the next expected unblock time in case it referred to the
-                 * task that is now in the Suspended state. */
-                taskENTER_CRITICAL();
-                {
-                    prvResetNextTaskUnblockTime();
-                }
-                taskEXIT_CRITICAL();
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
-
             if( pxTCB == pxCurrentTCB )
             {
                 if( xSchedulerRunning != pdFALSE )
@@ -3218,47 +3209,39 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
         }
         #else /* #if ( configNUMBER_OF_CORES == 1 ) */
         {
-            if( xSchedulerRunning != pdFALSE )
+            /* Enter critical section here to check run state of a task. */
+            taskENTER_CRITICAL();
             {
-                /* Reset the next expected unblock time in case it referred to the
-                 * task that is now in the Suspended state. */
-                prvResetNextTaskUnblockTime();
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
-
-            if( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE )
-            {
-                if( xSchedulerRunning != pdFALSE )
+                if( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE )
                 {
-                    if( xTaskRunningOnCore == ( BaseType_t ) portGET_CORE_ID() )
+                    if( xSchedulerRunning != pdFALSE )
                     {
-                        /* The current task has just been suspended. */
-                        configASSERT( uxSchedulerSuspended == 0 );
-                        vTaskYieldWithinAPI();
+                        if( pxTCB->xTaskRunState == ( BaseType_t ) portGET_CORE_ID() )
+                        {
+                            /* The current task has just been suspended. */
+                            configASSERT( uxSchedulerSuspended == 0 );
+                            vTaskYieldWithinAPI();
+                        }
+                        else
+                        {
+                            prvYieldCore( pxTCB->xTaskRunState );
+                        }
                     }
                     else
                     {
-                        prvYieldCore( xTaskRunningOnCore );
+                        /* This code path is not possible because only Idle tasks are
+                         * assigned a core before the scheduler is started ( i.e.
+                         * taskTASK_IS_RUNNING is only true for idle tasks before
+                         * the scheduler is started ) and idle tasks cannot be
+                         * suspended. */
+                        mtCOVERAGE_TEST_MARKER();
                     }
                 }
                 else
                 {
-                    /* This code path is not possible because only Idle tasks are
-                     * assigned a core before the scheduler is started ( i.e.
-                     * taskTASK_IS_RUNNING is only true for idle tasks before
-                     * the scheduler is started ) and idle tasks cannot be
-                     * suspended. */
                     mtCOVERAGE_TEST_MARKER();
                 }
             }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
-
             taskEXIT_CRITICAL();
         }
         #endif /* #if ( configNUMBER_OF_CORES == 1 ) */

From 8e664fc9844e03cc839074aff933fc9b79842d9c Mon Sep 17 00:00:00 2001
From: Soren Ptak <ptaksoren@gmail.com>
Date: Wed, 24 Jan 2024 13:52:13 -0500
Subject: [PATCH 197/424] Add check for if the scheduler is running to ARMv8M
 MPU ports (#960)

* Allow access to any buffer in xPortIsAuthorizedToAccessBuffer if xSchedulerRunning is set to pdFALSE

* Allow access to any buffer in xPortIsAuthorizedToAccessBuffer if xSchedulerRunning is set to pdFALSE in the copied ARMv8M Port Files
---
 portable/ARMv8M/non_secure/port.c            | 10 +++++++++-
 portable/GCC/ARM_CM23/non_secure/port.c      | 10 +++++++++-
 portable/GCC/ARM_CM23_NTZ/non_secure/port.c  | 10 +++++++++-
 portable/GCC/ARM_CM33/non_secure/port.c      | 10 +++++++++-
 portable/GCC/ARM_CM33_NTZ/non_secure/port.c  | 10 +++++++++-
 portable/GCC/ARM_CM35P/non_secure/port.c     | 10 +++++++++-
 portable/GCC/ARM_CM35P_NTZ/non_secure/port.c | 10 +++++++++-
 portable/GCC/ARM_CM55/non_secure/port.c      | 10 +++++++++-
 portable/GCC/ARM_CM55_NTZ/non_secure/port.c  | 10 +++++++++-
 portable/GCC/ARM_CM85/non_secure/port.c      | 10 +++++++++-
 portable/GCC/ARM_CM85_NTZ/non_secure/port.c  | 10 +++++++++-
 portable/IAR/ARM_CM23/non_secure/port.c      | 10 +++++++++-
 portable/IAR/ARM_CM23_NTZ/non_secure/port.c  | 10 +++++++++-
 portable/IAR/ARM_CM33/non_secure/port.c      | 10 +++++++++-
 portable/IAR/ARM_CM33_NTZ/non_secure/port.c  | 10 +++++++++-
 portable/IAR/ARM_CM35P/non_secure/port.c     | 10 +++++++++-
 portable/IAR/ARM_CM35P_NTZ/non_secure/port.c | 10 +++++++++-
 portable/IAR/ARM_CM55/non_secure/port.c      | 10 +++++++++-
 portable/IAR/ARM_CM55_NTZ/non_secure/port.c  | 10 +++++++++-
 portable/IAR/ARM_CM85/non_secure/port.c      | 10 +++++++++-
 portable/IAR/ARM_CM85_NTZ/non_secure/port.c  | 10 +++++++++-
 21 files changed, 189 insertions(+), 21 deletions(-)

diff --git a/portable/ARMv8M/non_secure/port.c b/portable/ARMv8M/non_secure/port.c
index a5ed7004a..45f9e2820 100644
--- a/portable/ARMv8M/non_secure/port.c
+++ b/portable/ARMv8M/non_secure/port.c
@@ -1906,7 +1906,15 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
         BaseType_t xAccessGranted = pdFALSE;
         const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
 
-        if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+        if( xSchedulerRunning == pdFALSE )
+        {
+            /* Grant access to all the kernel objects before the scheduler
+            * is started. It is necessary because there is no task running
+            * yet and therefore, we cannot use the permissions of any
+            * task. */
+            xAccessGranted = pdTRUE;
+        }
+        else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
         {
             xAccessGranted = pdTRUE;
         }
diff --git a/portable/GCC/ARM_CM23/non_secure/port.c b/portable/GCC/ARM_CM23/non_secure/port.c
index a5ed7004a..45f9e2820 100644
--- a/portable/GCC/ARM_CM23/non_secure/port.c
+++ b/portable/GCC/ARM_CM23/non_secure/port.c
@@ -1906,7 +1906,15 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
         BaseType_t xAccessGranted = pdFALSE;
         const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
 
-        if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+        if( xSchedulerRunning == pdFALSE )
+        {
+            /* Grant access to all the kernel objects before the scheduler
+            * is started. It is necessary because there is no task running
+            * yet and therefore, we cannot use the permissions of any
+            * task. */
+            xAccessGranted = pdTRUE;
+        }
+        else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
         {
             xAccessGranted = pdTRUE;
         }
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
index a5ed7004a..45f9e2820 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
@@ -1906,7 +1906,15 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
         BaseType_t xAccessGranted = pdFALSE;
         const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
 
-        if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+        if( xSchedulerRunning == pdFALSE )
+        {
+            /* Grant access to all the kernel objects before the scheduler
+            * is started. It is necessary because there is no task running
+            * yet and therefore, we cannot use the permissions of any
+            * task. */
+            xAccessGranted = pdTRUE;
+        }
+        else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
         {
             xAccessGranted = pdTRUE;
         }
diff --git a/portable/GCC/ARM_CM33/non_secure/port.c b/portable/GCC/ARM_CM33/non_secure/port.c
index a5ed7004a..45f9e2820 100644
--- a/portable/GCC/ARM_CM33/non_secure/port.c
+++ b/portable/GCC/ARM_CM33/non_secure/port.c
@@ -1906,7 +1906,15 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
         BaseType_t xAccessGranted = pdFALSE;
         const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
 
-        if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+        if( xSchedulerRunning == pdFALSE )
+        {
+            /* Grant access to all the kernel objects before the scheduler
+            * is started. It is necessary because there is no task running
+            * yet and therefore, we cannot use the permissions of any
+            * task. */
+            xAccessGranted = pdTRUE;
+        }
+        else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
         {
             xAccessGranted = pdTRUE;
         }
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
index a5ed7004a..45f9e2820 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
@@ -1906,7 +1906,15 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
         BaseType_t xAccessGranted = pdFALSE;
         const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
 
-        if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+        if( xSchedulerRunning == pdFALSE )
+        {
+            /* Grant access to all the kernel objects before the scheduler
+            * is started. It is necessary because there is no task running
+            * yet and therefore, we cannot use the permissions of any
+            * task. */
+            xAccessGranted = pdTRUE;
+        }
+        else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
         {
             xAccessGranted = pdTRUE;
         }
diff --git a/portable/GCC/ARM_CM35P/non_secure/port.c b/portable/GCC/ARM_CM35P/non_secure/port.c
index a5ed7004a..45f9e2820 100644
--- a/portable/GCC/ARM_CM35P/non_secure/port.c
+++ b/portable/GCC/ARM_CM35P/non_secure/port.c
@@ -1906,7 +1906,15 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
         BaseType_t xAccessGranted = pdFALSE;
         const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
 
-        if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+        if( xSchedulerRunning == pdFALSE )
+        {
+            /* Grant access to all the kernel objects before the scheduler
+            * is started. It is necessary because there is no task running
+            * yet and therefore, we cannot use the permissions of any
+            * task. */
+            xAccessGranted = pdTRUE;
+        }
+        else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
         {
             xAccessGranted = pdTRUE;
         }
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c b/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
index a5ed7004a..45f9e2820 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
@@ -1906,7 +1906,15 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
         BaseType_t xAccessGranted = pdFALSE;
         const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
 
-        if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+        if( xSchedulerRunning == pdFALSE )
+        {
+            /* Grant access to all the kernel objects before the scheduler
+            * is started. It is necessary because there is no task running
+            * yet and therefore, we cannot use the permissions of any
+            * task. */
+            xAccessGranted = pdTRUE;
+        }
+        else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
         {
             xAccessGranted = pdTRUE;
         }
diff --git a/portable/GCC/ARM_CM55/non_secure/port.c b/portable/GCC/ARM_CM55/non_secure/port.c
index a5ed7004a..45f9e2820 100644
--- a/portable/GCC/ARM_CM55/non_secure/port.c
+++ b/portable/GCC/ARM_CM55/non_secure/port.c
@@ -1906,7 +1906,15 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
         BaseType_t xAccessGranted = pdFALSE;
         const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
 
-        if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+        if( xSchedulerRunning == pdFALSE )
+        {
+            /* Grant access to all the kernel objects before the scheduler
+            * is started. It is necessary because there is no task running
+            * yet and therefore, we cannot use the permissions of any
+            * task. */
+            xAccessGranted = pdTRUE;
+        }
+        else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
         {
             xAccessGranted = pdTRUE;
         }
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/port.c b/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
index a5ed7004a..45f9e2820 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
@@ -1906,7 +1906,15 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
         BaseType_t xAccessGranted = pdFALSE;
         const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
 
-        if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+        if( xSchedulerRunning == pdFALSE )
+        {
+            /* Grant access to all the kernel objects before the scheduler
+            * is started. It is necessary because there is no task running
+            * yet and therefore, we cannot use the permissions of any
+            * task. */
+            xAccessGranted = pdTRUE;
+        }
+        else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
         {
             xAccessGranted = pdTRUE;
         }
diff --git a/portable/GCC/ARM_CM85/non_secure/port.c b/portable/GCC/ARM_CM85/non_secure/port.c
index a5ed7004a..45f9e2820 100644
--- a/portable/GCC/ARM_CM85/non_secure/port.c
+++ b/portable/GCC/ARM_CM85/non_secure/port.c
@@ -1906,7 +1906,15 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
         BaseType_t xAccessGranted = pdFALSE;
         const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
 
-        if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+        if( xSchedulerRunning == pdFALSE )
+        {
+            /* Grant access to all the kernel objects before the scheduler
+            * is started. It is necessary because there is no task running
+            * yet and therefore, we cannot use the permissions of any
+            * task. */
+            xAccessGranted = pdTRUE;
+        }
+        else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
         {
             xAccessGranted = pdTRUE;
         }
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/port.c b/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
index a5ed7004a..45f9e2820 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
@@ -1906,7 +1906,15 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
         BaseType_t xAccessGranted = pdFALSE;
         const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
 
-        if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+        if( xSchedulerRunning == pdFALSE )
+        {
+            /* Grant access to all the kernel objects before the scheduler
+            * is started. It is necessary because there is no task running
+            * yet and therefore, we cannot use the permissions of any
+            * task. */
+            xAccessGranted = pdTRUE;
+        }
+        else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
         {
             xAccessGranted = pdTRUE;
         }
diff --git a/portable/IAR/ARM_CM23/non_secure/port.c b/portable/IAR/ARM_CM23/non_secure/port.c
index a5ed7004a..45f9e2820 100644
--- a/portable/IAR/ARM_CM23/non_secure/port.c
+++ b/portable/IAR/ARM_CM23/non_secure/port.c
@@ -1906,7 +1906,15 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
         BaseType_t xAccessGranted = pdFALSE;
         const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
 
-        if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+        if( xSchedulerRunning == pdFALSE )
+        {
+            /* Grant access to all the kernel objects before the scheduler
+            * is started. It is necessary because there is no task running
+            * yet and therefore, we cannot use the permissions of any
+            * task. */
+            xAccessGranted = pdTRUE;
+        }
+        else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
         {
             xAccessGranted = pdTRUE;
         }
diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
index a5ed7004a..45f9e2820 100644
--- a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
@@ -1906,7 +1906,15 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
         BaseType_t xAccessGranted = pdFALSE;
         const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
 
-        if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+        if( xSchedulerRunning == pdFALSE )
+        {
+            /* Grant access to all the kernel objects before the scheduler
+            * is started. It is necessary because there is no task running
+            * yet and therefore, we cannot use the permissions of any
+            * task. */
+            xAccessGranted = pdTRUE;
+        }
+        else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
         {
             xAccessGranted = pdTRUE;
         }
diff --git a/portable/IAR/ARM_CM33/non_secure/port.c b/portable/IAR/ARM_CM33/non_secure/port.c
index a5ed7004a..45f9e2820 100644
--- a/portable/IAR/ARM_CM33/non_secure/port.c
+++ b/portable/IAR/ARM_CM33/non_secure/port.c
@@ -1906,7 +1906,15 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
         BaseType_t xAccessGranted = pdFALSE;
         const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
 
-        if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+        if( xSchedulerRunning == pdFALSE )
+        {
+            /* Grant access to all the kernel objects before the scheduler
+            * is started. It is necessary because there is no task running
+            * yet and therefore, we cannot use the permissions of any
+            * task. */
+            xAccessGranted = pdTRUE;
+        }
+        else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
         {
             xAccessGranted = pdTRUE;
         }
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
index a5ed7004a..45f9e2820 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
@@ -1906,7 +1906,15 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
         BaseType_t xAccessGranted = pdFALSE;
         const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
 
-        if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+        if( xSchedulerRunning == pdFALSE )
+        {
+            /* Grant access to all the kernel objects before the scheduler
+            * is started. It is necessary because there is no task running
+            * yet and therefore, we cannot use the permissions of any
+            * task. */
+            xAccessGranted = pdTRUE;
+        }
+        else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
         {
             xAccessGranted = pdTRUE;
         }
diff --git a/portable/IAR/ARM_CM35P/non_secure/port.c b/portable/IAR/ARM_CM35P/non_secure/port.c
index a5ed7004a..45f9e2820 100644
--- a/portable/IAR/ARM_CM35P/non_secure/port.c
+++ b/portable/IAR/ARM_CM35P/non_secure/port.c
@@ -1906,7 +1906,15 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
         BaseType_t xAccessGranted = pdFALSE;
         const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
 
-        if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+        if( xSchedulerRunning == pdFALSE )
+        {
+            /* Grant access to all the kernel objects before the scheduler
+            * is started. It is necessary because there is no task running
+            * yet and therefore, we cannot use the permissions of any
+            * task. */
+            xAccessGranted = pdTRUE;
+        }
+        else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
         {
             xAccessGranted = pdTRUE;
         }
diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c b/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
index a5ed7004a..45f9e2820 100644
--- a/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
@@ -1906,7 +1906,15 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
         BaseType_t xAccessGranted = pdFALSE;
         const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
 
-        if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+        if( xSchedulerRunning == pdFALSE )
+        {
+            /* Grant access to all the kernel objects before the scheduler
+            * is started. It is necessary because there is no task running
+            * yet and therefore, we cannot use the permissions of any
+            * task. */
+            xAccessGranted = pdTRUE;
+        }
+        else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
         {
             xAccessGranted = pdTRUE;
         }
diff --git a/portable/IAR/ARM_CM55/non_secure/port.c b/portable/IAR/ARM_CM55/non_secure/port.c
index a5ed7004a..45f9e2820 100644
--- a/portable/IAR/ARM_CM55/non_secure/port.c
+++ b/portable/IAR/ARM_CM55/non_secure/port.c
@@ -1906,7 +1906,15 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
         BaseType_t xAccessGranted = pdFALSE;
         const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
 
-        if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+        if( xSchedulerRunning == pdFALSE )
+        {
+            /* Grant access to all the kernel objects before the scheduler
+            * is started. It is necessary because there is no task running
+            * yet and therefore, we cannot use the permissions of any
+            * task. */
+            xAccessGranted = pdTRUE;
+        }
+        else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
         {
             xAccessGranted = pdTRUE;
         }
diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/port.c b/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
index a5ed7004a..45f9e2820 100644
--- a/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
@@ -1906,7 +1906,15 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
         BaseType_t xAccessGranted = pdFALSE;
         const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
 
-        if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+        if( xSchedulerRunning == pdFALSE )
+        {
+            /* Grant access to all the kernel objects before the scheduler
+            * is started. It is necessary because there is no task running
+            * yet and therefore, we cannot use the permissions of any
+            * task. */
+            xAccessGranted = pdTRUE;
+        }
+        else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
         {
             xAccessGranted = pdTRUE;
         }
diff --git a/portable/IAR/ARM_CM85/non_secure/port.c b/portable/IAR/ARM_CM85/non_secure/port.c
index a5ed7004a..45f9e2820 100644
--- a/portable/IAR/ARM_CM85/non_secure/port.c
+++ b/portable/IAR/ARM_CM85/non_secure/port.c
@@ -1906,7 +1906,15 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
         BaseType_t xAccessGranted = pdFALSE;
         const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
 
-        if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+        if( xSchedulerRunning == pdFALSE )
+        {
+            /* Grant access to all the kernel objects before the scheduler
+            * is started. It is necessary because there is no task running
+            * yet and therefore, we cannot use the permissions of any
+            * task. */
+            xAccessGranted = pdTRUE;
+        }
+        else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
         {
             xAccessGranted = pdTRUE;
         }
diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/port.c b/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
index a5ed7004a..45f9e2820 100644
--- a/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
@@ -1906,7 +1906,15 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
         BaseType_t xAccessGranted = pdFALSE;
         const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
 
-        if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+        if( xSchedulerRunning == pdFALSE )
+        {
+            /* Grant access to all the kernel objects before the scheduler
+            * is started. It is necessary because there is no task running
+            * yet and therefore, we cannot use the permissions of any
+            * task. */
+            xAccessGranted = pdTRUE;
+        }
+        else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
         {
             xAccessGranted = pdTRUE;
         }

From 5040a6793947cd6b32475649e5fe07c88744fa43 Mon Sep 17 00:00:00 2001
From: Mubin Sayyed <mubin.usman.sayyed@xilinx.com>
Date: Fri, 26 Jan 2024 08:51:44 +0530
Subject: [PATCH 198/424]  Sync up MicroblazeV9 port with Xilinx tree (#220)

* MicroblazeV9: Add support for 64 bit microblaze
* MicroblazeV9: Add support for generation of run time task stats
* MicroblazeV9: Add default implementation for callback functions
---------
Signed-off-by: Mubin Usman Sayyed <mubin.usman.sayyed@xilinx.com>
---
 .github/.cSpellWords.txt                    |   1 +
 .github/workflows/kernel-demos.yml          |  95 +++-
 portable/GCC/MicroBlazeV9/port.c            | 103 +++--
 portable/GCC/MicroBlazeV9/port_exceptions.c |   5 +-
 portable/GCC/MicroBlazeV9/portasm.S         | 486 +++++++++++---------
 portable/GCC/MicroBlazeV9/portmacro.h       | 116 ++---
 6 files changed, 508 insertions(+), 298 deletions(-)

diff --git a/.github/.cSpellWords.txt b/.github/.cSpellWords.txt
index e2149d5e1..ba8abfdf8 100644
--- a/.github/.cSpellWords.txt
+++ b/.github/.cSpellWords.txt
@@ -54,6 +54,7 @@ bics
 BISR
 BODIEN
 BODSTS
+brealid
 BRGR
 brhi
 brne
diff --git a/.github/workflows/kernel-demos.yml b/.github/workflows/kernel-demos.yml
index bae32c966..b29209c10 100644
--- a/.github/workflows/kernel-demos.yml
+++ b/.github/workflows/kernel-demos.yml
@@ -1,6 +1,13 @@
 name: FreeRTOS-Kernel Demos
 on: [push, pull_request]
 
+env:
+  # The bash escape character is \033
+  bashPass:   \033[32;1mPASSED -
+  bashInfo:   \033[33;1mINFO -
+  bashFail:   \033[31;1mFAILED -
+  bashEnd:    \033[0m
+
 jobs:
   WIN32-MSVC:
     name: WIN32 MSVC
@@ -147,6 +154,92 @@ jobs:
         working-directory: FreeRTOS/Demo/msp430_GCC
         run: make -j
 
+  MicroBlaze-GCC:
+    name: GCC MicroBlaze Toolchain
+    runs-on: ubuntu-latest
+    steps:
+      - name: Checkout the FreeRTOS/FreeRTOS Repository
+        uses: actions/checkout@v3
+        with:
+          ref: main
+          repository: FreeRTOS/FreeRTOS
+          fetch-depth: 1
+
+      - env:
+          stepName: Fetch Community-Supported-Demos Submodule
+        shell: bash
+        run: |
+          # Fetch Community-Supported-Demos Submodule
+          echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}"
+          git submodule update --checkout --init --depth 1 FreeRTOS/Demo/ThirdParty/Community-Supported-Demos
+          # This repository contains the microblaze_instructions.h header file
+          git clone https://github.com/Xilinx/embeddedsw.git --branch xilinx_v2023.1
+          echo "::endgroup::"
+          echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }}"
+
+      # Checkout user pull request changes
+      - name: Checkout Pull Request
+        uses: actions/checkout@v3
+        with:
+          path: ./FreeRTOS/Source
+
+      - env:
+          stepName: Install Dependancies
+        shell: bash
+        run: |
+          # ${{ env.stepName }}
+          echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}"
+          sudo apt update -y
+          sudo apt upgrade -y
+          sudo apt install -y build-essential m4 debhelper bison texinfo dejagnu flex
+          sudo apt install -y autogen gawk libgmp-dev libmpc-dev libmpfr-dev
+          sudo apt install -y patchutils sharutils zlib1g-dev autoconf2.64
+
+          # Download the mb-gcc toolchain from github
+          curl -L -O https://github.com/mdednev/mb-gcc/releases/download/2021-0623%2B2/binutils-microblaze_2.35-2021-0623+1_amd64.deb;
+          curl -L -O https://github.com/mdednev/mb-gcc/releases/download/2021-0623%2B2/gcc-microblaze_10.2.0-2021-0623+2_amd64.deb;
+          curl -L -O https://github.com/mdednev/mb-gcc/releases/download/2021-0623%2B2/libnewlib-microblaze-dev_3.3.0-2021-0623+3_all.deb;
+          curl -L -O https://github.com/mdednev/mb-gcc/releases/download/2021-0623%2B2/libnewlib-microblaze-doc_3.3.0-2021-0623+3_all.deb;
+          curl -L -O https://github.com/mdednev/mb-gcc/releases/download/2021-0623%2B2/libnewlib-microblaze_3.3.0-2021-0623+3_all.deb;
+          curl -L -O https://github.com/mdednev/mb-gcc/releases/download/2021-0623%2B2/newlib-source_3.3.0-2021-0623+3_all.deb;
+
+          # Install the packages for the toolchain
+          sudo apt install -y ./binutils-microblaze*.deb;
+          sudo apt install -y ./gcc-microblaze*.deb;
+          sudo apt install -y ./libnewlib-microblaze-dev*.deb;
+          sudo apt install -y ./libnewlib-microblaze-doc*.deb;
+          sudo apt install -y ./libnewlib-microblaze*.deb;
+          sudo apt install -y ./newlib-source*.deb;
+
+          # Validate that the toolchain is in the path and can be called
+          which mb-gcc
+          mb-gcc --version
+
+          echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }}"
+
+      - env:
+          stepName: Compile Microblaze Port
+        shell: bash
+        run: |
+          # ${{ env.stepName }}
+          echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}"
+          # Compile MicroBlazeV9 Port files to validate they build
+          mb-gcc -mcpu=v9.5 -c \
+            FreeRTOS/Source/portable/GCC/MicroBlazeV9/port.c \
+            FreeRTOS/Source/portable/GCC/MicroBlazeV9/portasm.S \
+            FreeRTOS/Source/portable/GCC/MicroBlazeV9/port_exceptions.c \
+            FreeRTOS/Source/tasks.c \
+            FreeRTOS/Source/list.c \
+            -I embeddedsw/lib/bsp/standalone/src/microblaze \
+            -I FreeRTOS/Source/portable/GCC/MicroBlazeV9/ \
+            -I FreeRTOS/Source/include \
+            -I FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src \
+            -I FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src \
+            -I FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/include \
+            -I FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/intc_v3_5/src
+          echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }}"
+
+
   ARM-GCC:
     name: GNU ARM Toolchain
     runs-on: ubuntu-latest
@@ -164,7 +257,7 @@ jobs:
           # Fetch Community-Supported-Demos Submodule
           echo "::group::Fetch Community-Supported-Demos Submodule"
           git submodule update --checkout --init --depth 1 FreeRTOS/Demo/ThirdParty/Community-Supported-Demos
-          echo "::engdroup::"
+          echo "::endgroup::"
           if [ "$?" = "0" ]; then
             echo -e "\033[32;3mCloned the Community-Supported-Demos\033[0m"
           else
diff --git a/portable/GCC/MicroBlazeV9/port.c b/portable/GCC/MicroBlazeV9/port.c
index fd5de1527..25c9ac357 100644
--- a/portable/GCC/MicroBlazeV9/port.c
+++ b/portable/GCC/MicroBlazeV9/port.c
@@ -42,6 +42,7 @@
 #include <xintc_i.h>
 #include <xil_exception.h>
 #include <microblaze_exceptions_g.h>
+#include <microblaze_instructions.h>
 
 /* Tasks are started with a critical section nesting of 0 - however, prior to
  * the scheduler being commenced interrupts should not be enabled, so the critical
@@ -58,6 +59,13 @@
  * given to the FSR register when the initial context is set up for a task being
  * created. */
 #define portINITIAL_FSR              ( 0U )
+/*
+ * Global counter used for calculation of run time statistics of tasks.
+ * Defined only when the relevant option is turned on
+ */
+#if (configGENERATE_RUN_TIME_STATS==1)
+    volatile uint32_t ulHighFrequencyTimerTicks;
+#endif
 
 /*-----------------------------------------------------------*/
 
@@ -116,10 +124,11 @@ static XIntc xInterruptControllerInstance;
                                          void * pvParameters )
 #endif
 {
-    extern void * _SDA2_BASE_;
-    extern void * _SDA_BASE_;
-    const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_;
-    const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_;
+    extern void *_SDA2_BASE_;
+    extern void *_SDA_BASE_;
+    const UINTPTR ulR2 = ( UINTPTR ) &_SDA2_BASE_;
+    const UINTPTR ulR13 = ( UINTPTR ) &_SDA_BASE_;
+
     extern void _start1( void );
 
     /* Place a few bytes of known values on the bottom of the stack.
@@ -255,8 +264,8 @@ static XIntc xInterruptControllerInstance;
 
 BaseType_t xPortStartScheduler( void )
 {
-    extern void( vPortStartFirstTask )( void );
-    extern uint32_t _stack[];
+    extern void ( vPortStartFirstTask )( void );
+    extern UINTPTR _stack[];
 
     /* Setup the hardware to generate the tick.  Interrupts are disabled when
      * this function is called.
@@ -270,7 +279,7 @@ BaseType_t xPortStartScheduler( void )
     vApplicationSetupTimerInterrupt();
 
     /* Reuse the stack from main() as the stack for the interrupts/exceptions. */
-    pulISRStack = ( uint32_t * ) _stack;
+    pulISRStack = ( UINTPTR * ) _stack;
 
     /* Ensure there is enough space for the functions called from the interrupt
      * service routines to write back into the stack frame of the caller. */
@@ -304,13 +313,18 @@ void vPortYield( void )
      * not interrupted by the tick ISR.  It is not a problem to do this as
      * each task maintains its own interrupt status. */
     portENTER_CRITICAL();
-    {
-        /* Jump directly to the yield function to ensure there is no
-         * compiler generated prologue code. */
-        asm volatile ( "bralid r14, VPortYieldASM      \n\t" \
-                       "or r0, r0, r0                  \n\t" );
-    }
-    portEXIT_CRITICAL();
+	  {
+		    /* Jump directly to the yield function to ensure there is no
+		    * compiler generated prologue code. */
+        #ifdef __arch64__
+            asm volatile (	"brealid r14, VPortYieldASM		\n\t" \
+        		         				"or r0, r0, r0					      \n\t" );
+        #else
+         		asm volatile (	"bralid r14, VPortYieldASM		\n\t" \
+				                 		"or r0, r0, r0					      \n\t" );
+        #endif
+  	}
+	  portEXIT_CRITICAL();
 }
 /*-----------------------------------------------------------*/
 
@@ -434,22 +448,34 @@ void vPortTickISR( void * pvUnused )
 {
     extern void vApplicationClearTimerInterrupt( void );
 
-    /* Ensure the unused parameter does not generate a compiler warning. */
-    ( void ) pvUnused;
+	/* Ensure the unused parameter does not generate a compiler warning. */
+	( void ) pvUnused;
 
-    /* This port uses an application defined callback function to clear the tick
-     * interrupt because the kernel will run on lots of different MicroBlaze and
-     * FPGA configurations - not all of which will have the same timer peripherals
-     * defined or available.  An example definition of
-     * vApplicationClearTimerInterrupt() is provided in the official demo
-     * application that accompanies this port. */
-    vApplicationClearTimerInterrupt();
-
-    /* Increment the RTOS tick - this might cause a task to unblock. */
-    if( xTaskIncrementTick() != pdFALSE )
+    /* The Xilinx implementation of generating run time task stats uses the same timer used for generating
+	   * FreeRTOS ticks. In case user decides to generate run time stats the tick handler is called more
+	   * frequently (10 times faster). The timer    ick handler uses logic to handle the same. It handles
+	   * the FreeRTOS tick once per 10 interrupts.
+	   * For handling generation of run time stats, it increments a pre-defined counter every time the
+	   * interrupt handler executes. */
+#if (configGENERATE_RUN_TIME_STATS == 1)
+    ulHighFrequencyTimerTicks++;
+    if (!(ulHighFrequencyTimerTicks % 10))
+#endif
     {
-        /* Force vTaskSwitchContext() to be called as the interrupt exits. */
-        ulTaskSwitchRequested = 1;
+        /* This port uses an application defined callback function to clear the tick
+         * interrupt because the kernel will run on lots of different MicroBlaze and
+         * FPGA configurations - not all of which will have the same timer peripherals
+         * defined or available.  An example definition of
+         * vApplicationClearTimerInterrupt() is provided in the official demo
+         * application that accompanies this port. */
+        vApplicationClearTimerInterrupt();
+
+        /* Increment the RTOS tick - this might cause a task to unblock. */
+        if( xTaskIncrementTick() != pdFALSE )
+        {
+            /* Force vTaskSwitchContext() to be called as the interrupt exits. */
+            ulTaskSwitchRequested = 1;
+        }
     }
 }
 /*-----------------------------------------------------------*/
@@ -495,4 +521,25 @@ static int32_t prvInitialiseInterruptController( void )
 
     return lStatus;
 }
+
+#if( configGENERATE_RUN_TIME_STATS == 1 )
+/*
+ * For Xilinx implementation this is a dummy function that does a redundant operation
+ * of zeroing out the global counter.
+ * It is called by FreeRTOS kernel.
+ */
+void xCONFIGURE_TIMER_FOR_RUN_TIME_STATS (void)
+{
+	ulHighFrequencyTimerTicks = 0;
+}
+/*
+ * For Xilinx implementation this function returns the global counter used for
+ * run time task stats calculation.
+ * It is called by FreeRTOS kernel task handling logic.
+ */
+uint32_t xGET_RUN_TIME_COUNTER_VALUE (void)
+{
+	return ulHighFrequencyTimerTicks;
+}
+#endif
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/MicroBlazeV9/port_exceptions.c b/portable/GCC/MicroBlazeV9/port_exceptions.c
index e2347732d..f89e47b0a 100644
--- a/portable/GCC/MicroBlazeV9/port_exceptions.c
+++ b/portable/GCC/MicroBlazeV9/port_exceptions.c
@@ -67,7 +67,7 @@
 
 /* This variable is set in the exception entry code, before
  * vPortExceptionHandler is called. */
-    uint32_t * pulStackPointerOnFunctionEntry = NULL;
+    UINTPTR *pulStackPointerOnFunctionEntry = NULL;
 
 /* This is the structure that is filled with the MicroBlaze context as it
  * existed immediately prior to the exception occurrence.  A pointer to this
@@ -80,7 +80,6 @@
  * in portasm.S. */
     void vPortExceptionHandler( void * pvExceptionID );
     extern void vPortExceptionHandlerEntry( void * pvExceptionID );
-
 /*-----------------------------------------------------------*/
 
 /* vApplicationExceptionRegisterDump() is a callback function that the
@@ -149,7 +148,7 @@
         xRegisterDump.ulR29 = mfgpr( R29 );
         xRegisterDump.ulR30 = mfgpr( R30 );
         xRegisterDump.ulR31 = mfgpr( R31 );
-        xRegisterDump.ulR1_SP = ( ( uint32_t ) pulStackPointerOnFunctionEntry ) + portexASM_HANDLER_STACK_FRAME_SIZE;
+        xRegisterDump.ulR1_SP = ( ( UINTPTR ) pulStackPointerOnFunctionEntry ) + portexASM_HANDLER_STACK_FRAME_SIZE;
         xRegisterDump.ulEAR = mfear();
         xRegisterDump.ulESR = mfesr();
         xRegisterDump.ulEDR = mfedr();
diff --git a/portable/GCC/MicroBlazeV9/portasm.S b/portable/GCC/MicroBlazeV9/portasm.S
index 2114d00e8..0a5e658d9 100644
--- a/portable/GCC/MicroBlazeV9/portasm.S
+++ b/portable/GCC/MicroBlazeV9/portasm.S
@@ -33,63 +33,97 @@
 #include "microblaze_exceptions_g.h"
 #include "xparameters.h"
 
+#include "microblaze_instructions.h"
+/* The context is oversized to allow functions called from the ISR to write
+back into the caller stack. */
+#if defined (__arch64__)
+#if( XPAR_MICROBLAZE_USE_FPU != 0 )
+	#define portCONTEXT_SIZE 272
+	#define portMINUS_CONTEXT_SIZE -272
+#else
+	#define portCONTEXT_SIZE 264
+	#define portMINUS_CONTEXT_SIZE -264
+#endif
+#else
+#if( XPAR_MICROBLAZE_USE_FPU != 0 )
+	#define portCONTEXT_SIZE 136
+	#define portMINUS_CONTEXT_SIZE -136
+#else
+	#define portCONTEXT_SIZE 132
+	#define portMINUS_CONTEXT_SIZE -132
+#endif
+#endif
+
 /* Offsets from the stack pointer at which saved registers are placed. */
-#define portR31_OFFSET  4
-#define portR30_OFFSET  8
-#define portR29_OFFSET  12
-#define portR28_OFFSET  16
-#define portR27_OFFSET  20
-#define portR26_OFFSET  24
-#define portR25_OFFSET  28
-#define portR24_OFFSET  32
-#define portR23_OFFSET  36
-#define portR22_OFFSET  40
-#define portR21_OFFSET  44
-#define portR20_OFFSET  48
-#define portR19_OFFSET  52
-#define portR18_OFFSET  56
-#define portR17_OFFSET  60
-#define portR16_OFFSET  64
-#define portR15_OFFSET  68
-#define portR14_OFFSET  72
-#define portR13_OFFSET  76
-#define portR12_OFFSET  80
-#define portR11_OFFSET  84
-#define portR10_OFFSET  88
-#define portR9_OFFSET   92
-#define portR8_OFFSET   96
-#define portR7_OFFSET   100
-#define portR6_OFFSET   104
-#define portR5_OFFSET   108
-#define portR4_OFFSET   112
-#define portR3_OFFSET   116
-#define portR2_OFFSET   120
+#if defined (__arch64__)
+#define portR31_OFFSET	8
+#define portR30_OFFSET	16
+#define portR29_OFFSET	24
+#define portR28_OFFSET	32
+#define portR27_OFFSET	40
+#define portR26_OFFSET	48
+#define portR25_OFFSET	56
+#define portR24_OFFSET	64
+#define portR23_OFFSET	72
+#define portR22_OFFSET	80
+#define portR21_OFFSET	88
+#define portR20_OFFSET	96
+#define portR19_OFFSET	104
+#define portR18_OFFSET	112
+#define portR17_OFFSET	120
+#define portR16_OFFSET	128
+#define portR15_OFFSET	136
+#define portR14_OFFSET	144
+#define portR13_OFFSET	152
+#define portR12_OFFSET	160
+#define portR11_OFFSET	168
+#define portR10_OFFSET	176
+#define portR9_OFFSET	184
+#define portR8_OFFSET	192
+#define portR7_OFFSET	200
+#define portR6_OFFSET	208
+#define portR5_OFFSET	216
+#define portR4_OFFSET	224
+#define portR3_OFFSET	232
+#define portR2_OFFSET	240
+#define portCRITICAL_NESTING_OFFSET 248
+#define portMSR_OFFSET 256
+#define portFSR_OFFSET 264
+#else
+#define portR31_OFFSET	4
+#define portR30_OFFSET	8
+#define portR29_OFFSET	12
+#define portR28_OFFSET	16
+#define portR27_OFFSET	20
+#define portR26_OFFSET	24
+#define portR25_OFFSET	28
+#define portR24_OFFSET	32
+#define portR23_OFFSET	36
+#define portR22_OFFSET	40
+#define portR21_OFFSET	44
+#define portR20_OFFSET	48
+#define portR19_OFFSET	52
+#define portR18_OFFSET	56
+#define portR17_OFFSET	60
+#define portR16_OFFSET	64
+#define portR15_OFFSET	68
+#define portR14_OFFSET	72
+#define portR13_OFFSET	76
+#define portR12_OFFSET	80
+#define portR11_OFFSET	84
+#define portR10_OFFSET	88
+#define portR9_OFFSET	92
+#define portR8_OFFSET	96
+#define portR7_OFFSET	100
+#define portR6_OFFSET	104
+#define portR5_OFFSET	108
+#define portR4_OFFSET	112
+#define portR3_OFFSET	116
+#define portR2_OFFSET	120
 #define portCRITICAL_NESTING_OFFSET 124
 #define portMSR_OFFSET 128
+#define portFSR_OFFSET 132
 
-#if( XPAR_MICROBLAZE_USE_FPU != 0 )
-    #define portFSR_OFFSET 132
-    #if( XPAR_MICROBLAZE_USE_STACK_PROTECTION )
-        #define portSLR_OFFSET 136
-        #define portSHR_OFFSET 140
-
-        #define portCONTEXT_SIZE 144
-        #define portMINUS_CONTEXT_SIZE -144
-    #else
-        #define portCONTEXT_SIZE 136
-        #define portMINUS_CONTEXT_SIZE -136
-    #endif
-#else
-    #if( XPAR_MICROBLAZE_USE_STACK_PROTECTION )
-        #define portSLR_OFFSET 132
-        #define portSHR_OFFSET 136
-
-        #define portCONTEXT_SIZE 140
-        #define portMINUS_CONTEXT_SIZE -140
-    #else
-        #define portCONTEXT_SIZE 132
-        #define portMINUS_CONTEXT_SIZE -132
-    #endif
 #endif
 
     .extern pxCurrentTCB
@@ -109,54 +143,54 @@
 
 .macro portSAVE_CONTEXT
 
-    /* Make room for the context on the stack. */
-    addik r1, r1, portMINUS_CONTEXT_SIZE
+	/* Make room for the context on the stack. */
+	ADDLIK r1, r1, portMINUS_CONTEXT_SIZE
 
-    /* Stack general registers. */
-    swi r31, r1, portR31_OFFSET
-    swi r30, r1, portR30_OFFSET
-    swi r29, r1, portR29_OFFSET
-    swi r28, r1, portR28_OFFSET
-    swi r27, r1, portR27_OFFSET
-    swi r26, r1, portR26_OFFSET
-    swi r25, r1, portR25_OFFSET
-    swi r24, r1, portR24_OFFSET
-    swi r23, r1, portR23_OFFSET
-    swi r22, r1, portR22_OFFSET
-    swi r21, r1, portR21_OFFSET
-    swi r20, r1, portR20_OFFSET
-    swi r19, r1, portR19_OFFSET
-    swi r18, r1, portR18_OFFSET
-    swi r17, r1, portR17_OFFSET
-    swi r16, r1, portR16_OFFSET
-    swi r15, r1, portR15_OFFSET
-    /* R14 is saved later as it needs adjustment if a yield is performed. */
-    swi r13, r1, portR13_OFFSET
-    swi r12, r1, portR12_OFFSET
-    swi r11, r1, portR11_OFFSET
-    swi r10, r1, portR10_OFFSET
-    swi r9, r1, portR9_OFFSET
-    swi r8, r1, portR8_OFFSET
-    swi r7, r1, portR7_OFFSET
-    swi r6, r1, portR6_OFFSET
-    swi r5, r1, portR5_OFFSET
-    swi r4, r1, portR4_OFFSET
-    swi r3, r1, portR3_OFFSET
-    swi r2, r1, portR2_OFFSET
+	/* Stack general registers. */
+	SI r31, r1, portR31_OFFSET
+	SI r30, r1, portR30_OFFSET
+	SI r29, r1, portR29_OFFSET
+	SI r28, r1, portR28_OFFSET
+	SI r27, r1, portR27_OFFSET
+	SI r26, r1, portR26_OFFSET
+	SI r25, r1, portR25_OFFSET
+	SI r24, r1, portR24_OFFSET
+	SI r23, r1, portR23_OFFSET
+	SI r22, r1, portR22_OFFSET
+	SI r21, r1, portR21_OFFSET
+	SI r20, r1, portR20_OFFSET
+	SI r19, r1, portR19_OFFSET
+	SI r18, r1, portR18_OFFSET
+	SI r17, r1, portR17_OFFSET
+	SI r16, r1, portR16_OFFSET
+	SI r15, r1, portR15_OFFSET
+	/* R14 is saved later as it needs adjustment if a yield is performed. */
+	SI r13, r1, portR13_OFFSET
+	SI r12, r1, portR12_OFFSET
+	SI r11, r1, portR11_OFFSET
+	SI r10, r1, portR10_OFFSET
+	SI r9, r1, portR9_OFFSET
+	SI r8, r1, portR8_OFFSET
+	SI r7, r1, portR7_OFFSET
+	SI r6, r1, portR6_OFFSET
+	SI r5, r1, portR5_OFFSET
+	SI r4, r1, portR4_OFFSET
+	SI r3, r1, portR3_OFFSET
+	SI r2, r1, portR2_OFFSET
 
-    /* Stack the critical section nesting value. */
-    lwi r18, r0, uxCriticalNesting
-    swi r18, r1, portCRITICAL_NESTING_OFFSET
+	/* Stack the critical section nesting value. */
+	LI r18, r0, uxCriticalNesting
+	SI r18, r1, portCRITICAL_NESTING_OFFSET
 
-    /* Stack MSR. */
-    mfs r18, rmsr
-    swi r18, r1, portMSR_OFFSET
+	/* Stack MSR. */
+	mfs r18, rmsr
+	SI r18, r1, portMSR_OFFSET
 
-    #if( XPAR_MICROBLAZE_USE_FPU != 0 )
-        /* Stack FSR. */
-        mfs r18, rfsr
-        swi r18, r1, portFSR_OFFSET
-    #endif
+	#if( XPAR_MICROBLAZE_USE_FPU != 0 )
+		/* Stack FSR. */
+		mfs r18, rfsr
+		SI r18, r1, portFSR_OFFSET
+	#endif
 
 #if( XPAR_MICROBLAZE_USE_STACK_PROTECTION )
     /* Save the stack limits */
@@ -166,17 +200,17 @@
     swi r18, r1, portSHR_OFFSET
 #endif
 
-    /* Save the top of stack value to the TCB. */
-    lwi r3, r0, pxCurrentTCB
-    sw  r1, r0, r3
+	/* Save the top of stack value to the TCB. */
+	LI r3, r0, pxCurrentTCB
+	STORE	r1, r0, r3
 
     .endm
 
 .macro portRESTORE_CONTEXT
 
-    /* Load the top of stack value from the TCB. */
-    lwi r18, r0, pxCurrentTCB
-    lw  r1, r0, r18
+	/* Load the top of stack value from the TCB. */
+	LI r18, r0, pxCurrentTCB
+	LOAD	r1, r0, r18
 
 #if( XPAR_MICROBLAZE_USE_STACK_PROTECTION )
     /* Restore the stack limits -- must not load from r1 (Stack Pointer)
@@ -189,101 +223,112 @@
     mts rshr, r12
 #endif
 
-    /* Restore the general registers. */
-    lwi r31, r1, portR31_OFFSET
-    lwi r30, r1, portR30_OFFSET
-    lwi r29, r1, portR29_OFFSET
-    lwi r28, r1, portR28_OFFSET
-    lwi r27, r1, portR27_OFFSET
-    lwi r26, r1, portR26_OFFSET
-    lwi r25, r1, portR25_OFFSET
-    lwi r24, r1, portR24_OFFSET
-    lwi r23, r1, portR23_OFFSET
-    lwi r22, r1, portR22_OFFSET
-    lwi r21, r1, portR21_OFFSET
-    lwi r20, r1, portR20_OFFSET
-    lwi r19, r1, portR19_OFFSET
-    lwi r17, r1, portR17_OFFSET
-    lwi r16, r1, portR16_OFFSET
-    lwi r15, r1, portR15_OFFSET
-    lwi r14, r1, portR14_OFFSET
-    lwi r13, r1, portR13_OFFSET
-    lwi r12, r1, portR12_OFFSET
-    lwi r11, r1, portR11_OFFSET
-    lwi r10, r1, portR10_OFFSET
-    lwi r9, r1, portR9_OFFSET
-    lwi r8, r1, portR8_OFFSET
-    lwi r7, r1, portR7_OFFSET
-    lwi r6, r1, portR6_OFFSET
-    lwi r5, r1, portR5_OFFSET
-    lwi r4, r1, portR4_OFFSET
-    lwi r3, r1, portR3_OFFSET
-    lwi r2, r1, portR2_OFFSET
+	/* Restore the general registers. */
+	LI r31, r1, portR31_OFFSET
+	LI r30, r1, portR30_OFFSET
+	LI r29, r1, portR29_OFFSET
+	LI r28, r1, portR28_OFFSET
+	LI r27, r1, portR27_OFFSET
+	LI r26, r1, portR26_OFFSET
+	LI r25, r1, portR25_OFFSET
+	LI r24, r1, portR24_OFFSET
+	LI r23, r1, portR23_OFFSET
+	LI r22, r1, portR22_OFFSET
+	LI r21, r1, portR21_OFFSET
+	LI r20, r1, portR20_OFFSET
+	LI r19, r1, portR19_OFFSET
+	LI r17, r1, portR17_OFFSET
+	LI r16, r1, portR16_OFFSET
+	LI r15, r1, portR15_OFFSET
+	LI r14, r1, portR14_OFFSET
+	LI r13, r1, portR13_OFFSET
+	LI r12, r1, portR12_OFFSET
+	LI r11, r1, portR11_OFFSET
+	LI r10, r1, portR10_OFFSET
+	LI r9, r1, portR9_OFFSET
+	LI r8, r1, portR8_OFFSET
+	LI r7, r1, portR7_OFFSET
+	LI r6, r1, portR6_OFFSET
+	LI r5, r1, portR5_OFFSET
+	LI r4, r1, portR4_OFFSET
+	LI r3, r1, portR3_OFFSET
+	LI r2, r1, portR2_OFFSET
 
-    /* Reload the rmsr from the stack. */
-    lwi r18, r1, portMSR_OFFSET
-    mts rmsr, r18
+	/* Reload the rmsr from the stack. */
+	LI r18, r1, portMSR_OFFSET
+	mts rmsr, r18
 
-    #if( XPAR_MICROBLAZE_USE_FPU != 0 )
-        /* Reload the FSR from the stack. */
-        lwi r18, r1, portFSR_OFFSET
-        mts rfsr, r18
-    #endif
+	#if( XPAR_MICROBLAZE_USE_FPU != 0 )
+		/* Reload the FSR from the stack. */
+		LI r18, r1, portFSR_OFFSET
+		mts rfsr, r18
+	#endif
 
-    /* Load the critical nesting value. */
-    lwi r18, r1, portCRITICAL_NESTING_OFFSET
-    swi r18, r0, uxCriticalNesting
+	/* Load the critical nesting value. */
+	LI r18, r1, portCRITICAL_NESTING_OFFSET
+	SI r18, r0, uxCriticalNesting
 
-    /* Test the critical nesting value.  If it is non zero then the task last
-    exited the running state using a yield.  If it is zero, then the task
-    last exited the running state through an interrupt. */
-    xori r18, r18, 0
-    bnei r18, exit_from_yield
+	/* Test the critical nesting value.  If it is non zero then the task last
+	exited the running state using a yield.  If it is zero, then the task
+	last exited the running state through an interrupt. */
+	XORI r18, r18, 0
+	BNEI r18, exit_from_yield
 
-    /* r18 was being used as a temporary.  Now restore its true value from the
-    stack. */
-    lwi r18, r1, portR18_OFFSET
+	/* r18 was being used as a temporary.  Now restore its true value from the
+	stack. */
+	LI r18, r1, portR18_OFFSET
 
-    /* Remove the stack frame. */
-    addik r1, r1, portCONTEXT_SIZE
+	/* Remove the stack frame. */
+	ADDLIK r1, r1, portCONTEXT_SIZE
 
-    /* Return using rtid so interrupts are re-enabled as this function is
-    exited. */
-    rtid r14, 0
-    or r0, r0, r0
+	/* Return using rtid so interrupts are re-enabled as this function is
+	exited. */
+	rtid r14, 0
+	OR r0, r0, r0
 
-    .endm
+	.endm
 
 /* This function is used to exit portRESTORE_CONTEXT() if the task being
 returned to last left the Running state by calling taskYIELD() (rather than
 being preempted by an interrupt). */
-    .text
-    .align  4
+	.text
+#ifdef __arch64__
+	.align  8
+#else
+        .align  4
+#endif
+
 exit_from_yield:
 
-    /* r18 was being used as a temporary.  Now restore its true value from the
-    stack. */
-    lwi r18, r1, portR18_OFFSET
+	/* r18 was being used as a temporary.  Now restore its true value from the
+	stack. */
+	LI r18, r1, portR18_OFFSET
 
-    /* Remove the stack frame. */
-    addik r1, r1, portCONTEXT_SIZE
+	/* Remove the stack frame. */
+	ADDLIK r1, r1, portCONTEXT_SIZE
 
-    /* Return to the task. */
-    rtsd r14, 0
-    or r0, r0, r0
+	/* Return to the task. */
+	rtsd r14, 0
+	OR r0, r0, r0
 
 
-    .text
-    .align  4
+	.text
+
+#ifdef __arch64__
+	.align  8
+#else
+        .align  4
+#endif
+
 _interrupt_handler:
 
     portSAVE_CONTEXT
 
-    /* Stack the return address. */
-    swi r14, r1, portR14_OFFSET
+	/* Stack the return address. */
+	SI r14, r1, portR14_OFFSET
 
-    /* Switch to the ISR stack. */
-    lwi r1, r0, pulISRStack
+	/* Switch to the ISR stack. */
+	LI r1, r0, pulISRStack
 
 #if( XPAR_MICROBLAZE_USE_STACK_PROTECTION )
     ori r18, r0, _stack_end
@@ -292,29 +337,29 @@ _interrupt_handler:
     mts rshr, r18
 #endif
 
-    /* The parameter to the interrupt handler. */
-    ori r5, r0, configINTERRUPT_CONTROLLER_TO_USE
+	/* The parameter to the interrupt handler. */
+	ORI r5, r0, configINTERRUPT_CONTROLLER_TO_USE
 
-    /* Execute any pending interrupts. */
-    bralid r15, XIntc_DeviceInterruptHandler
-    or r0, r0, r0
+	/* Execute any pending interrupts. */
+	BRALID r15, XIntc_DeviceInterruptHandler
+	OR r0, r0, r0
 
-    /* See if a new task should be selected to execute. */
-    lwi r18, r0, ulTaskSwitchRequested
-    or r18, r18, r0
+	/* See if a new task should be selected to execute. */
+	LI r18, r0, ulTaskSwitchRequested
+	OR r18, r18, r0
 
-    /* If ulTaskSwitchRequested is already zero, then jump straight to
-    restoring the task that is already in the Running state. */
-    beqi r18, task_switch_not_requested
+	/* If ulTaskSwitchRequested is already zero, then jump straight to
+	restoring the task that is already in the Running state. */
+	BEQI r18, task_switch_not_requested
 
-    /* Set ulTaskSwitchRequested back to zero as a task switch is about to be
-    performed. */
-    swi r0, r0, ulTaskSwitchRequested
+	/* Set ulTaskSwitchRequested back to zero as a task switch is about to be
+	performed. */
+	SI r0, r0, ulTaskSwitchRequested
 
-    /* ulTaskSwitchRequested was not 0 when tested.  Select the next task to
-    execute. */
-    bralid r15, vTaskSwitchContext
-    or r0, r0, r0
+	/* ulTaskSwitchRequested was not 0 when tested.  Select the next task to
+	execute. */
+	BRALID r15, vTaskSwitchContext
+	OR r0, r0, r0
 
 task_switch_not_requested:
 
@@ -322,19 +367,24 @@ task_switch_not_requested:
     portRESTORE_CONTEXT
 
 
-    .text
-    .align  4
+	.text
+#ifdef __arch64__
+	.align  8
+#else
+        .align  4
+#endif
+
 VPortYieldASM:
 
     portSAVE_CONTEXT
 
-    /* Modify the return address so a return is done to the instruction after
-    the call to VPortYieldASM. */
-    addi r14, r14, 8
-    swi r14, r1, portR14_OFFSET
+	/* Modify the return address so a return is done to the instruction after
+	the call to VPortYieldASM. */
+	ADDI r14, r14, 8
+	SI r14, r1, portR14_OFFSET
 
-    /* Switch to use the ISR stack. */
-    lwi r1, r0, pulISRStack
+	/* Switch to use the ISR stack. */
+	LI r1, r0, pulISRStack
 
 #if( XPAR_MICROBLAZE_USE_STACK_PROTECTION )
     ori r18, r0, _stack_end
@@ -343,15 +393,20 @@ VPortYieldASM:
     mts rshr, r18
 #endif
 
-    /* Select the next task to execute. */
-    bralid r15, vTaskSwitchContext
-    or r0, r0, r0
+	/* Select the next task to execute. */
+	BRALID r15, vTaskSwitchContext
+	OR r0, r0, r0
 
     /* Restore the context of the next task scheduled to execute. */
     portRESTORE_CONTEXT
 
-    .text
-    .align  4
+	.text
+#ifdef __arch64__
+	.align  8
+#else
+        .align  4
+#endif
+
 vPortStartFirstTask:
 
     portRESTORE_CONTEXT
@@ -360,14 +415,19 @@ vPortStartFirstTask:
 
 #if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )
 
-    .text
-    .align 4
+	.text
+#ifdef __arch64__
+	.align 8
+#else
+        .align  4
+#endif
+
 vPortExceptionHandlerEntry:
 
-    /* Take a copy of the stack pointer before vPortExecptionHandler is called,
-    storing its value prior to the function stack frame being created. */
-    swi r1, r0, pulStackPointerOnFunctionEntry
-    bralid r15, vPortExceptionHandler
-    or r0, r0, r0
+	/* Take a copy of the stack pointer before vPortExecptionHandler is called,
+	storing its value prior to the function stack frame being created. */
+	SI r1, r0, pulStackPointerOnFunctionEntry
+	BRALID r15, vPortExceptionHandler
+	OR r0, r0, r0
 
 #endif /* ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) */
diff --git a/portable/GCC/MicroBlazeV9/portmacro.h b/portable/GCC/MicroBlazeV9/portmacro.h
index ccf98ed4c..497f9c514 100644
--- a/portable/GCC/MicroBlazeV9/portmacro.h
+++ b/portable/GCC/MicroBlazeV9/portmacro.h
@@ -50,20 +50,26 @@
  */
 
 /* Type definitions. */
-#define portCHAR          char
-#define portFLOAT         float
-#define portDOUBLE        double
-#define portLONG          long
-#define portSHORT         short
-#define portSTACK_TYPE    uint32_t
-#define portBASE_TYPE     long
+#define portCHAR              char
+#define portFLOAT             float
+#define portDOUBLE            double
+#define portLONG              long
+#define portSHORT             short
+#ifdef __arch64__
+    #define portSTACK_TYPE    size_t
+    typedef uint64_t        UBaseType_t;
+#else
+    #define portSTACK_TYPE    uint32_t
+    typedef unsigned long   UBaseType_t;
+#endif
+#define portBASE_TYPE         long
+
+typedef portSTACK_TYPE      StackType_t;
+typedef long                BaseType_t;
 
-typedef portSTACK_TYPE   StackType_t;
-typedef long             BaseType_t;
-typedef unsigned long    UBaseType_t;
 
 #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t     TickType_t;
+    typedef uint16_t        TickType_t;
     #define portMAX_DELAY              ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
     typedef uint32_t     TickType_t;
@@ -155,10 +161,14 @@ extern volatile uint32_t ulTaskSwitchRequested;
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */
-#define portBYTE_ALIGNMENT    4
-#define portSTACK_GROWTH      ( -1 )
-#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portNOP()               asm volatile ( "NOP" )
+#ifdef __arch64__
+    #define portBYTE_ALIGNMENT    8
+#else
+    #define portBYTE_ALIGNMENT    4
+#endif
+#define portSTACK_GROWTH          ( -1 )
+#define portTICK_PERIOD_MS        ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()    asm volatile ( "NOP" )
 #define portMEMORY_BARRIER()    asm volatile ( "" ::: "memory" )
 /*-----------------------------------------------------------*/
 
@@ -179,43 +189,43 @@ typedef struct PORT_REGISTER_DUMP
 {
     /* The following structure members hold the values of the MicroBlaze
      * registers at the time the exception was raised. */
-    uint32_t ulR1_SP;
-    uint32_t ulR2_small_data_area;
-    uint32_t ulR3;
-    uint32_t ulR4;
-    uint32_t ulR5;
-    uint32_t ulR6;
-    uint32_t ulR7;
-    uint32_t ulR8;
-    uint32_t ulR9;
-    uint32_t ulR10;
-    uint32_t ulR11;
-    uint32_t ulR12;
-    uint32_t ulR13_read_write_small_data_area;
-    uint32_t ulR14_return_address_from_interrupt;
-    uint32_t ulR15_return_address_from_subroutine;
-    uint32_t ulR16_return_address_from_trap;
-    uint32_t ulR17_return_address_from_exceptions; /* The exception entry code will copy the BTR into R17 if the exception occurred in the delay slot of a branch instruction. */
-    uint32_t ulR18;
-    uint32_t ulR19;
-    uint32_t ulR20;
-    uint32_t ulR21;
-    uint32_t ulR22;
-    uint32_t ulR23;
-    uint32_t ulR24;
-    uint32_t ulR25;
-    uint32_t ulR26;
-    uint32_t ulR27;
-    uint32_t ulR28;
-    uint32_t ulR29;
-    uint32_t ulR30;
-    uint32_t ulR31;
-    uint32_t ulPC;
-    uint32_t ulESR;
-    uint32_t ulMSR;
-    uint32_t ulEAR;
-    uint32_t ulFSR;
-    uint32_t ulEDR;
+    UINTPTR ulR1_SP;
+    UINTPTR ulR2_small_data_area;
+    UINTPTR ulR3;
+    UINTPTR ulR4;
+    UINTPTR ulR5;
+    UINTPTR ulR6;
+    UINTPTR ulR7;
+    UINTPTR ulR8;
+    UINTPTR ulR9;
+    UINTPTR ulR10;
+    UINTPTR ulR11;
+    UINTPTR ulR12;
+    UINTPTR ulR13_read_write_small_data_area;
+    UINTPTR ulR14_return_address_from_interrupt;
+    UINTPTR ulR15_return_address_from_subroutine;
+    UINTPTR ulR16_return_address_from_trap;
+    UINTPTR ulR17_return_address_from_exceptions; /* The exception entry code will copy the BTR into R17 if the exception occurred in the delay slot of a branch instruction. */
+    UINTPTR ulR18;
+    UINTPTR ulR19;
+    UINTPTR ulR20;
+    UINTPTR ulR21;
+    UINTPTR ulR22;
+    UINTPTR ulR23;
+    UINTPTR ulR24;
+    UINTPTR ulR25;
+    UINTPTR ulR26;
+    UINTPTR ulR27;
+    UINTPTR ulR28;
+    UINTPTR ulR29;
+    UINTPTR ulR30;
+    UINTPTR ulR31;
+    UINTPTR ulPC;
+    UINTPTR ulESR;
+    UINTPTR ulMSR;
+    UINTPTR ulEAR;
+    UINTPTR ulFSR;
+    UINTPTR ulEDR;
 
     /* A human readable description of the exception cause.  The strings used
      * are the same as the #define constant names found in the
@@ -384,4 +394,4 @@ void vApplicationExceptionRegisterDump( xPortRegisterDump * xRegisterDump );
 #endif
 /* *INDENT-ON* */
 
-#endif /* PORTMACRO_H */
+#endif /* PORTMACRO_H */
\ No newline at end of file

From 14dd5b503afc7d9ed88ee9483d586d88d71d20c0 Mon Sep 17 00:00:00 2001
From: Phillip Stevens <phillip.stevens@gmail.com>
Date: Sat, 27 Jan 2024 16:26:55 +1100
Subject: [PATCH 199/424] use configSTACK_DEPTH_TYPE consequently (updated for
 11.0.x) (#942)

* use configSTACK_DEPTH_TYPE consequently

* update default to uint32_t

* Update FreeRTOS.h

Revert for backwards compatibility

* Update portable.h

* configSTACK_DEPTH_TYPE - unify stack variable naming

* update lexicon.txt

* update typo lexicon.txt

* Update task.h

* Update timers.h

* fix merge typo

* fix stack type

* fix timer stack type

* fix timer stack more

* fix affinity set stack

* adjust ports to use configSTACK_DEPTH_TYPE

* fix vTaskListTasks

* set default stack depth type in portable.h

* fix History.txt

* update affinityset

* resolve reviewer comments

* fix prvTaskCheckFreeStackSpace for variable stack size type

* restore CoRoutine defines

* remove obsolete stack ttype casts

* fix (attempt) for format portable.h

* Formatting fixes

* prvTaskCheckFreeStackSpace make variable naming compliant

* Update portable/GCC/ARM_CM33/non_secure/port.c

Co-authored-by: Soren Ptak <ptaksoren@gmail.com>

* Update portable/GCC/ARM_CM23/non_secure/port.c

Co-authored-by: Soren Ptak <ptaksoren@gmail.com>

* Apply suggestions from code review

Update ulStackDepth to uxStackDepth

Co-authored-by: Soren Ptak <ptaksoren@gmail.com>

* Correct uxStackDepth in port.c

Also add uint32_t cast prvGetMPURegionSizeSetting.

* Update ARM CM3 MPU port.c

Revert casting of ( uint32_t ) pxBottomOfStack

* Code review suggestions

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Co-authored-by: Soren Ptak <ptaksoren@gmail.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 History.txt                                   |  3 +
 include/FreeRTOS.h                            |  8 +-
 include/mpu_prototypes.h                      |  4 +-
 include/portable.h                            |  6 +-
 include/task.h                                | 42 ++++-----
 include/timers.h                              |  6 +-
 portable/ARMv8M/non_secure/port.c             |  6 +-
 portable/Common/mpu_wrappers.c                | 12 +--
 portable/Common/mpu_wrappers_v2.c             |  8 +-
 portable/GCC/ARM_CM23/non_secure/port.c       |  6 +-
 portable/GCC/ARM_CM23_NTZ/non_secure/port.c   |  6 +-
 portable/GCC/ARM_CM33/non_secure/port.c       |  6 +-
 portable/GCC/ARM_CM33_NTZ/non_secure/port.c   |  6 +-
 portable/GCC/ARM_CM35P/non_secure/port.c      |  6 +-
 portable/GCC/ARM_CM35P_NTZ/non_secure/port.c  |  6 +-
 portable/GCC/ARM_CM3_MPU/port.c               |  8 +-
 portable/GCC/ARM_CM4_MPU/port.c               |  8 +-
 portable/GCC/ARM_CM55/non_secure/port.c       |  6 +-
 portable/GCC/ARM_CM55_NTZ/non_secure/port.c   |  6 +-
 portable/GCC/ARM_CM85/non_secure/port.c       |  6 +-
 portable/GCC/ARM_CM85_NTZ/non_secure/port.c   |  6 +-
 portable/IAR/ARM_CM23/non_secure/port.c       |  6 +-
 portable/IAR/ARM_CM23_NTZ/non_secure/port.c   |  6 +-
 portable/IAR/ARM_CM33/non_secure/port.c       |  6 +-
 portable/IAR/ARM_CM33_NTZ/non_secure/port.c   |  6 +-
 portable/IAR/ARM_CM35P/non_secure/port.c      |  6 +-
 portable/IAR/ARM_CM35P_NTZ/non_secure/port.c  |  6 +-
 portable/IAR/ARM_CM4F_MPU/port.c              |  8 +-
 portable/IAR/ARM_CM55/non_secure/port.c       |  6 +-
 portable/IAR/ARM_CM55_NTZ/non_secure/port.c   |  6 +-
 portable/IAR/ARM_CM85/non_secure/port.c       |  6 +-
 portable/IAR/ARM_CM85_NTZ/non_secure/port.c   |  6 +-
 portable/RVDS/ARM_CM4_MPU/port.c              | 10 +--
 .../GCC/Xtensa_ESP32/include/portmacro.h      |  2 +-
 portable/ThirdParty/GCC/Xtensa_ESP32/port.c   |  4 +-
 portable/ThirdParty/XCC/Xtensa/port.c         | 29 +++---
 tasks.c                                       | 90 +++++++++----------
 timers.c                                      | 12 +--
 38 files changed, 197 insertions(+), 189 deletions(-)

diff --git a/History.txt b/History.txt
index a8e5ac7ba..9feeb050a 100644
--- a/History.txt
+++ b/History.txt
@@ -1,5 +1,8 @@
 Documentation and download available at https://www.FreeRTOS.org/
 
+	+ Update all the APIs to use configSTACK_DEPTH_TYPE for stack type. If left
+	  undefined, configSTACK_DEPTH_TYPE defaults to StackType_t.
+
 Changes between FreeRTOS V11.0.0 and FreeRTOS V11.0.1 released December 21, 2023
 
     + Updated the SBOM file.
diff --git a/include/FreeRTOS.h b/include/FreeRTOS.h
index d7c458df2..a23b67169 100644
--- a/include/FreeRTOS.h
+++ b/include/FreeRTOS.h
@@ -1642,7 +1642,7 @@
 #endif
 
 #ifndef traceENTER_xTaskCreateStatic
-    #define traceENTER_xTaskCreateStatic( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer )
+    #define traceENTER_xTaskCreateStatic( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer )
 #endif
 
 #ifndef traceRETURN_xTaskCreateStatic
@@ -1650,7 +1650,7 @@
 #endif
 
 #ifndef traceENTER_xTaskCreateStaticAffinitySet
-    #define traceENTER_xTaskCreateStaticAffinitySet( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer, uxCoreAffinityMask )
+    #define traceENTER_xTaskCreateStaticAffinitySet( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer, uxCoreAffinityMask )
 #endif
 
 #ifndef traceRETURN_xTaskCreateStaticAffinitySet
@@ -1690,7 +1690,7 @@
 #endif
 
 #ifndef traceENTER_xTaskCreate
-    #define traceENTER_xTaskCreate( pxTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask )
+    #define traceENTER_xTaskCreate( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, pxCreatedTask )
 #endif
 
 #ifndef traceRETURN_xTaskCreate
@@ -1698,7 +1698,7 @@
 #endif
 
 #ifndef traceENTER_xTaskCreateAffinitySet
-    #define traceENTER_xTaskCreateAffinitySet( pxTaskCode, pcName, usStackDepth, pvParameters, uxPriority, uxCoreAffinityMask, pxCreatedTask )
+    #define traceENTER_xTaskCreateAffinitySet( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, uxCoreAffinityMask, pxCreatedTask )
 #endif
 
 #ifndef traceRETURN_xTaskCreateAffinitySet
diff --git a/include/mpu_prototypes.h b/include/mpu_prototypes.h
index 547320180..94ab59611 100644
--- a/include/mpu_prototypes.h
+++ b/include/mpu_prototypes.h
@@ -138,13 +138,13 @@ BaseType_t MPU_xTaskGetSchedulerState( void ) FREERTOS_SYSTEM_CALL;
  * with all the APIs. */
 BaseType_t MPU_xTaskCreate( TaskFunction_t pxTaskCode,
                             const char * const pcName,
-                            const uint16_t usStackDepth,
+                            const configSTACK_DEPTH_TYPE uxStackDepth,
                             void * const pvParameters,
                             UBaseType_t uxPriority,
                             TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION;
 TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode,
                                     const char * const pcName,
-                                    const uint32_t ulStackDepth,
+                                    const configSTACK_DEPTH_TYPE uxStackDepth,
                                     void * const pvParameters,
                                     UBaseType_t uxPriority,
                                     StackType_t * const puxStackBuffer,
diff --git a/include/portable.h b/include/portable.h
index ab8a26df0..c4b350abf 100644
--- a/include/portable.h
+++ b/include/portable.h
@@ -85,6 +85,10 @@
     #define portARCH_NAME    NULL
 #endif
 
+#ifndef configSTACK_DEPTH_TYPE
+    #define configSTACK_DEPTH_TYPE    StackType_t
+#endif
+
 #ifndef configSTACK_ALLOCATION_FROM_SEPARATE_HEAP
     /* Defaults to 0 for backward compatibility. */
     #define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP    0
@@ -228,7 +232,7 @@ void vPortEndScheduler( void ) PRIVILEGED_FUNCTION;
     void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
                                     const struct xMEMORY_REGION * const xRegions,
                                     StackType_t * pxBottomOfStack,
-                                    uint32_t ulStackDepth ) PRIVILEGED_FUNCTION;
+                                    configSTACK_DEPTH_TYPE uxStackDepth ) PRIVILEGED_FUNCTION;
 #endif
 
 /**
diff --git a/include/task.h b/include/task.h
index 5a845f0ef..7856b89d2 100644
--- a/include/task.h
+++ b/include/task.h
@@ -288,8 +288,8 @@ typedef enum
  * @code{c}
  * BaseType_t xTaskCreate(
  *                            TaskFunction_t pxTaskCode,
- *                            const char *pcName,
- *                            configSTACK_DEPTH_TYPE usStackDepth,
+ *                            const char * const pcName,
+ *                            const configSTACK_DEPTH_TYPE uxStackDepth,
  *                            void *pvParameters,
  *                            UBaseType_t uxPriority,
  *                            TaskHandle_t *pxCreatedTask
@@ -323,9 +323,9 @@ typedef enum
  * facilitate debugging.  Max length defined by configMAX_TASK_NAME_LEN - default
  * is 16.
  *
- * @param usStackDepth The size of the task stack specified as the number of
+ * @param uxStackDepth The size of the task stack specified as the number of
  * variables the stack can hold - not the number of bytes.  For example, if
- * the stack is 16 bits wide and usStackDepth is defined as 100, 200 bytes
+ * the stack is 16 bits wide and uxStackDepth is defined as 100, 200 bytes
  * will be allocated for stack storage.
  *
  * @param pvParameters Pointer that will be used as the parameter for the task
@@ -380,7 +380,7 @@ typedef enum
 #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
     BaseType_t xTaskCreate( TaskFunction_t pxTaskCode,
                             const char * const pcName,
-                            const configSTACK_DEPTH_TYPE usStackDepth,
+                            const configSTACK_DEPTH_TYPE uxStackDepth,
                             void * const pvParameters,
                             UBaseType_t uxPriority,
                             TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION;
@@ -389,7 +389,7 @@ typedef enum
 #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
     BaseType_t xTaskCreateAffinitySet( TaskFunction_t pxTaskCode,
                                        const char * const pcName,
-                                       const configSTACK_DEPTH_TYPE usStackDepth,
+                                       const configSTACK_DEPTH_TYPE uxStackDepth,
                                        void * const pvParameters,
                                        UBaseType_t uxPriority,
                                        UBaseType_t uxCoreAffinityMask,
@@ -400,8 +400,8 @@ typedef enum
  * task. h
  * @code{c}
  * TaskHandle_t xTaskCreateStatic( TaskFunction_t pxTaskCode,
- *                               const char *pcName,
- *                               uint32_t ulStackDepth,
+ *                               const char * const pcName,
+ *                               const configSTACK_DEPTH_TYPE uxStackDepth,
  *                               void *pvParameters,
  *                               UBaseType_t uxPriority,
  *                               StackType_t *puxStackBuffer,
@@ -427,9 +427,9 @@ typedef enum
  * facilitate debugging.  The maximum length of the string is defined by
  * configMAX_TASK_NAME_LEN in FreeRTOSConfig.h.
  *
- * @param ulStackDepth The size of the task stack specified as the number of
+ * @param uxStackDepth The size of the task stack specified as the number of
  * variables the stack can hold - not the number of bytes.  For example, if
- * the stack is 32-bits wide and ulStackDepth is defined as 100 then 400 bytes
+ * the stack is 32-bits wide and uxStackDepth is defined as 100 then 400 bytes
  * will be allocated for stack storage.
  *
  * @param pvParameters Pointer that will be used as the parameter for the task
@@ -438,7 +438,7 @@ typedef enum
  * @param uxPriority The priority at which the task will run.
  *
  * @param puxStackBuffer Must point to a StackType_t array that has at least
- * ulStackDepth indexes - the array will then be used as the task's stack,
+ * uxStackDepth indexes - the array will then be used as the task's stack,
  * removing the need for the stack to be allocated dynamically.
  *
  * @param pxTaskBuffer Must point to a variable of type StaticTask_t, which will
@@ -507,7 +507,7 @@ typedef enum
 #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
     TaskHandle_t xTaskCreateStatic( TaskFunction_t pxTaskCode,
                                     const char * const pcName,
-                                    const uint32_t ulStackDepth,
+                                    const configSTACK_DEPTH_TYPE uxStackDepth,
                                     void * const pvParameters,
                                     UBaseType_t uxPriority,
                                     StackType_t * const puxStackBuffer,
@@ -517,7 +517,7 @@ typedef enum
 #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
     TaskHandle_t xTaskCreateStaticAffinitySet( TaskFunction_t pxTaskCode,
                                                const char * const pcName,
-                                               const uint32_t ulStackDepth,
+                                               const configSTACK_DEPTH_TYPE uxStackDepth,
                                                void * const pvParameters,
                                                UBaseType_t uxPriority,
                                                StackType_t * const puxStackBuffer,
@@ -561,7 +561,7 @@ typedef enum
  * {
  *  vATask,     // pvTaskCode - the function that implements the task.
  *  "ATask",    // pcName - just a text name for the task to assist debugging.
- *  100,        // usStackDepth - the stack size DEFINED IN WORDS.
+ *  100,        // uxStackDepth - the stack size DEFINED IN WORDS.
  *  NULL,       // pvParameters - passed into the task function as the function parameters.
  *  ( 1UL | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.
  *  cStackBuffer,// puxStackBuffer - the buffer to be used as the task stack.
@@ -655,7 +655,7 @@ typedef enum
  * {
  *  vATask,     // pvTaskCode - the function that implements the task.
  *  "ATask",    // pcName - just a text name for the task to assist debugging.
- *  100,        // usStackDepth - the stack size DEFINED IN WORDS.
+ *  100,        // uxStackDepth - the stack size DEFINED IN WORDS.
  *  NULL,       // pvParameters - passed into the task function as the function parameters.
  *  ( 1UL | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.
  *  cStackBuffer,// puxStackBuffer - the buffer to be used as the task stack.
@@ -1987,7 +1987,7 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION;
 /**
  * task.h
  * @code{c}
- * void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, StackType_t ** ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize )
+ * void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, StackType_t ** ppxIdleTaskStackBuffer, configSTACK_DEPTH_TYPE * puxIdleTaskStackSize )
  * @endcode
  *
  * This function is used to provide a statically allocated block of memory to FreeRTOS to hold the Idle Task TCB.  This function is required when
@@ -1995,16 +1995,16 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION;
  *
  * @param ppxIdleTaskTCBBuffer A handle to a statically allocated TCB buffer
  * @param ppxIdleTaskStackBuffer A handle to a statically allocated Stack buffer for the idle task
- * @param pulIdleTaskStackSize A pointer to the number of elements that will fit in the allocated stack buffer
+ * @param puxIdleTaskStackSize A pointer to the number of elements that will fit in the allocated stack buffer
  */
     void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer,
                                         StackType_t ** ppxIdleTaskStackBuffer,
-                                        uint32_t * pulIdleTaskStackSize );
+                                        configSTACK_DEPTH_TYPE * puxIdleTaskStackSize );
 
 /**
  * task.h
  * @code{c}
- * void vApplicationGetPassiveIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, StackType_t ** ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize, BaseType_t xCoreID )
+ * void vApplicationGetPassiveIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, StackType_t ** ppxIdleTaskStackBuffer, configSTACK_DEPTH_TYPE * puxIdleTaskStackSize, BaseType_t xCoreID )
  * @endcode
  *
  * This function is used to provide a statically allocated block of memory to FreeRTOS to hold the Idle Tasks TCB.  This function is required when
@@ -2022,13 +2022,13 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION;
  *
  * @param ppxIdleTaskTCBBuffer A handle to a statically allocated TCB buffer
  * @param ppxIdleTaskStackBuffer A handle to a statically allocated Stack buffer for the idle task
- * @param pulIdleTaskStackSize A pointer to the number of elements that will fit in the allocated stack buffer
+ * @param puxIdleTaskStackSize A pointer to the number of elements that will fit in the allocated stack buffer
  * @param xPassiveIdleTaskIndex The passive idle task index of the idle task buffer
  */
     #if ( configNUMBER_OF_CORES > 1 )
         void vApplicationGetPassiveIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer,
                                                    StackType_t ** ppxIdleTaskStackBuffer,
-                                                   uint32_t * pulIdleTaskStackSize,
+                                                   configSTACK_DEPTH_TYPE * puxIdleTaskStackSize,
                                                    BaseType_t xPassiveIdleTaskIndex );
     #endif /* #if ( configNUMBER_OF_CORES > 1 ) */
 #endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
diff --git a/include/timers.h b/include/timers.h
index e874d2434..f526fdedd 100644
--- a/include/timers.h
+++ b/include/timers.h
@@ -1384,7 +1384,7 @@ BaseType_t xTimerGenericCommandFromISR( TimerHandle_t xTimer,
 /**
  * task.h
  * @code{c}
- * void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer, StackType_t ** ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize )
+ * void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer, StackType_t ** ppxTimerTaskStackBuffer, configSTACK_DEPTH_TYPE * puxTimerTaskStackSize )
  * @endcode
  *
  * This function is used to provide a statically allocated block of memory to FreeRTOS to hold the Timer Task TCB.  This function is required when
@@ -1392,11 +1392,11 @@ BaseType_t xTimerGenericCommandFromISR( TimerHandle_t xTimer,
  *
  * @param ppxTimerTaskTCBBuffer   A handle to a statically allocated TCB buffer
  * @param ppxTimerTaskStackBuffer A handle to a statically allocated Stack buffer for the idle task
- * @param pulTimerTaskStackSize   A pointer to the number of elements that will fit in the allocated stack buffer
+ * @param puxTimerTaskStackSize   A pointer to the number of elements that will fit in the allocated stack buffer
  */
     void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer,
                                          StackType_t ** ppxTimerTaskStackBuffer,
-                                         uint32_t * pulTimerTaskStackSize );
+                                         configSTACK_DEPTH_TYPE * puxTimerTaskStackSize );
 
 #endif
 
diff --git a/portable/ARMv8M/non_secure/port.c b/portable/ARMv8M/non_secure/port.c
index 45f9e2820..6d88b637f 100644
--- a/portable/ARMv8M/non_secure/port.c
+++ b/portable/ARMv8M/non_secure/port.c
@@ -1775,7 +1775,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
     void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
                                     const struct xMEMORY_REGION * const xRegions,
                                     StackType_t * pxBottomOfStack,
-                                    uint32_t ulStackDepth )
+                                    configSTACK_DEPTH_TYPE uxStackDepth )
     {
         uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
         int32_t lIndex = 0;
@@ -1800,10 +1800,10 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
          * which case the stack region parameters will be valid.  At all other
          * times the stack parameters will not be valid and it is assumed that
          * the stack region has already been configured. */
-        if( ulStackDepth > 0 )
+        if( uxStackDepth > 0 )
         {
             ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
-            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1;
 
             /* If the stack is within the privileged SRAM, do not protect it
              * using a separate MPU region. This is needed because privileged
diff --git a/portable/Common/mpu_wrappers.c b/portable/Common/mpu_wrappers.c
index 969bf2d3e..d25618c67 100644
--- a/portable/Common/mpu_wrappers.c
+++ b/portable/Common/mpu_wrappers.c
@@ -57,7 +57,7 @@
     #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
         BaseType_t MPU_xTaskCreate( TaskFunction_t pvTaskCode,
                                     const char * const pcName,
-                                    uint16_t usStackDepth,
+                                    const configSTACK_DEPTH_TYPE uxStackDepth,
                                     void * pvParameters,
                                     UBaseType_t uxPriority,
                                     TaskHandle_t * pxCreatedTask ) /* FREERTOS_SYSTEM_CALL */
@@ -72,7 +72,7 @@
                 uxPriority = uxPriority & ~( portPRIVILEGE_BIT );
                 portMEMORY_BARRIER();
 
-                xReturn = xTaskCreate( pvTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask );
+                xReturn = xTaskCreate( pvTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, pxCreatedTask );
                 portMEMORY_BARRIER();
 
                 portRESET_PRIVILEGE();
@@ -80,7 +80,7 @@
             }
             else
             {
-                xReturn = xTaskCreate( pvTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask );
+                xReturn = xTaskCreate( pvTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, pxCreatedTask );
             }
 
             return xReturn;
@@ -91,7 +91,7 @@
     #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
         TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode,
                                             const char * const pcName,
-                                            const uint32_t ulStackDepth,
+                                            const configSTACK_DEPTH_TYPE uxStackDepth,
                                             void * const pvParameters,
                                             UBaseType_t uxPriority,
                                             StackType_t * const puxStackBuffer,
@@ -107,7 +107,7 @@
                 uxPriority = uxPriority & ~( portPRIVILEGE_BIT );
                 portMEMORY_BARRIER();
 
-                xReturn = xTaskCreateStatic( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer );
+                xReturn = xTaskCreateStatic( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer );
                 portMEMORY_BARRIER();
 
                 portRESET_PRIVILEGE();
@@ -115,7 +115,7 @@
             }
             else
             {
-                xReturn = xTaskCreateStatic( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer );
+                xReturn = xTaskCreateStatic( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer );
             }
 
             return xReturn;
diff --git a/portable/Common/mpu_wrappers_v2.c b/portable/Common/mpu_wrappers_v2.c
index 832a7f844..e257b25c2 100644
--- a/portable/Common/mpu_wrappers_v2.c
+++ b/portable/Common/mpu_wrappers_v2.c
@@ -1541,7 +1541,7 @@
 
         BaseType_t MPU_xTaskCreate( TaskFunction_t pvTaskCode,
                                     const char * const pcName,
-                                    uint16_t usStackDepth,
+                                    const configSTACK_DEPTH_TYPE uxStackDepth,
                                     void * pvParameters,
                                     UBaseType_t uxPriority,
                                     TaskHandle_t * pxCreatedTask ) /* PRIVILEGED_FUNCTION */
@@ -1557,7 +1557,7 @@
                 /* xTaskCreate() can only be used to create privileged tasks in MPU port. */
                 if( ( uxPriority & portPRIVILEGE_BIT ) != 0 )
                 {
-                    xReturn = xTaskCreate( pvTaskCode, pcName, usStackDepth, pvParameters, uxPriority, &( xInternalTaskHandle ) );
+                    xReturn = xTaskCreate( pvTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, &( xInternalTaskHandle ) );
 
                     if( ( xReturn == pdPASS ) && ( xInternalTaskHandle != NULL ) )
                     {
@@ -1585,7 +1585,7 @@
 
         TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode,
                                             const char * const pcName,
-                                            const uint32_t ulStackDepth,
+                                            const configSTACK_DEPTH_TYPE uxStackDepth,
                                             void * const pvParameters,
                                             UBaseType_t uxPriority,
                                             StackType_t * const puxStackBuffer,
@@ -1599,7 +1599,7 @@
 
             if( lIndex != -1 )
             {
-                xInternalTaskHandle = xTaskCreateStatic( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer );
+                xInternalTaskHandle = xTaskCreateStatic( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer );
 
                 if( xInternalTaskHandle != NULL )
                 {
diff --git a/portable/GCC/ARM_CM23/non_secure/port.c b/portable/GCC/ARM_CM23/non_secure/port.c
index 45f9e2820..6d88b637f 100644
--- a/portable/GCC/ARM_CM23/non_secure/port.c
+++ b/portable/GCC/ARM_CM23/non_secure/port.c
@@ -1775,7 +1775,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
     void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
                                     const struct xMEMORY_REGION * const xRegions,
                                     StackType_t * pxBottomOfStack,
-                                    uint32_t ulStackDepth )
+                                    configSTACK_DEPTH_TYPE uxStackDepth )
     {
         uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
         int32_t lIndex = 0;
@@ -1800,10 +1800,10 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
          * which case the stack region parameters will be valid.  At all other
          * times the stack parameters will not be valid and it is assumed that
          * the stack region has already been configured. */
-        if( ulStackDepth > 0 )
+        if( uxStackDepth > 0 )
         {
             ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
-            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1;
 
             /* If the stack is within the privileged SRAM, do not protect it
              * using a separate MPU region. This is needed because privileged
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
index 45f9e2820..6d88b637f 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
@@ -1775,7 +1775,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
     void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
                                     const struct xMEMORY_REGION * const xRegions,
                                     StackType_t * pxBottomOfStack,
-                                    uint32_t ulStackDepth )
+                                    configSTACK_DEPTH_TYPE uxStackDepth )
     {
         uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
         int32_t lIndex = 0;
@@ -1800,10 +1800,10 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
          * which case the stack region parameters will be valid.  At all other
          * times the stack parameters will not be valid and it is assumed that
          * the stack region has already been configured. */
-        if( ulStackDepth > 0 )
+        if( uxStackDepth > 0 )
         {
             ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
-            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1;
 
             /* If the stack is within the privileged SRAM, do not protect it
              * using a separate MPU region. This is needed because privileged
diff --git a/portable/GCC/ARM_CM33/non_secure/port.c b/portable/GCC/ARM_CM33/non_secure/port.c
index 45f9e2820..6d88b637f 100644
--- a/portable/GCC/ARM_CM33/non_secure/port.c
+++ b/portable/GCC/ARM_CM33/non_secure/port.c
@@ -1775,7 +1775,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
     void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
                                     const struct xMEMORY_REGION * const xRegions,
                                     StackType_t * pxBottomOfStack,
-                                    uint32_t ulStackDepth )
+                                    configSTACK_DEPTH_TYPE uxStackDepth )
     {
         uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
         int32_t lIndex = 0;
@@ -1800,10 +1800,10 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
          * which case the stack region parameters will be valid.  At all other
          * times the stack parameters will not be valid and it is assumed that
          * the stack region has already been configured. */
-        if( ulStackDepth > 0 )
+        if( uxStackDepth > 0 )
         {
             ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
-            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1;
 
             /* If the stack is within the privileged SRAM, do not protect it
              * using a separate MPU region. This is needed because privileged
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
index 45f9e2820..6d88b637f 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
@@ -1775,7 +1775,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
     void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
                                     const struct xMEMORY_REGION * const xRegions,
                                     StackType_t * pxBottomOfStack,
-                                    uint32_t ulStackDepth )
+                                    configSTACK_DEPTH_TYPE uxStackDepth )
     {
         uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
         int32_t lIndex = 0;
@@ -1800,10 +1800,10 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
          * which case the stack region parameters will be valid.  At all other
          * times the stack parameters will not be valid and it is assumed that
          * the stack region has already been configured. */
-        if( ulStackDepth > 0 )
+        if( uxStackDepth > 0 )
         {
             ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
-            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1;
 
             /* If the stack is within the privileged SRAM, do not protect it
              * using a separate MPU region. This is needed because privileged
diff --git a/portable/GCC/ARM_CM35P/non_secure/port.c b/portable/GCC/ARM_CM35P/non_secure/port.c
index 45f9e2820..6d88b637f 100644
--- a/portable/GCC/ARM_CM35P/non_secure/port.c
+++ b/portable/GCC/ARM_CM35P/non_secure/port.c
@@ -1775,7 +1775,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
     void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
                                     const struct xMEMORY_REGION * const xRegions,
                                     StackType_t * pxBottomOfStack,
-                                    uint32_t ulStackDepth )
+                                    configSTACK_DEPTH_TYPE uxStackDepth )
     {
         uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
         int32_t lIndex = 0;
@@ -1800,10 +1800,10 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
          * which case the stack region parameters will be valid.  At all other
          * times the stack parameters will not be valid and it is assumed that
          * the stack region has already been configured. */
-        if( ulStackDepth > 0 )
+        if( uxStackDepth > 0 )
         {
             ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
-            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1;
 
             /* If the stack is within the privileged SRAM, do not protect it
              * using a separate MPU region. This is needed because privileged
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c b/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
index 45f9e2820..6d88b637f 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
@@ -1775,7 +1775,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
     void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
                                     const struct xMEMORY_REGION * const xRegions,
                                     StackType_t * pxBottomOfStack,
-                                    uint32_t ulStackDepth )
+                                    configSTACK_DEPTH_TYPE uxStackDepth )
     {
         uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
         int32_t lIndex = 0;
@@ -1800,10 +1800,10 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
          * which case the stack region parameters will be valid.  At all other
          * times the stack parameters will not be valid and it is assumed that
          * the stack region has already been configured. */
-        if( ulStackDepth > 0 )
+        if( uxStackDepth > 0 )
         {
             ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
-            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1;
 
             /* If the stack is within the privileged SRAM, do not protect it
              * using a separate MPU region. This is needed because privileged
diff --git a/portable/GCC/ARM_CM3_MPU/port.c b/portable/GCC/ARM_CM3_MPU/port.c
index 521ceaec3..a8a92402e 100644
--- a/portable/GCC/ARM_CM3_MPU/port.c
+++ b/portable/GCC/ARM_CM3_MPU/port.c
@@ -1243,7 +1243,7 @@ void vPortSwitchToUserMode( void )
 void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
                                 const struct xMEMORY_REGION * const xRegions,
                                 StackType_t * pxBottomOfStack,
-                                uint32_t ulStackDepth )
+                                configSTACK_DEPTH_TYPE uxStackDepth )
 {
     #if defined( __ARMCC_VERSION )
 
@@ -1300,7 +1300,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
          * which case the stack region parameters will be valid.  At all other
          * times the stack parameters will not be valid and it is assumed that the
          * stack region has already been configured. */
-        if( ulStackDepth > 0 )
+        if( uxStackDepth > 0 )
         {
             /* Define the region that allows access to the stack. */
             xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
@@ -1311,12 +1311,12 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
             xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
                 ( portMPU_REGION_READ_WRITE ) |
                 ( portMPU_REGION_EXECUTE_NEVER ) |
-                ( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |
+                ( prvGetMPURegionSizeSetting ( ( uint32_t ) ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) ) ) |
                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
                 ( portMPU_REGION_ENABLE );
             xMPUSettings->xRegionSettings[ 0 ].ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
             xMPUSettings->xRegionSettings[ 0 ].ulRegionEndAddress = ( uint32_t ) ( ( uint32_t ) ( pxBottomOfStack ) +
-                                                                                   ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1UL );
+                                                                                   ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1UL );
             xMPUSettings->xRegionSettings[ 0 ].ulRegionPermissions = ( tskMPU_READ_PERMISSION |
                                                                        tskMPU_WRITE_PERMISSION );
         }
diff --git a/portable/GCC/ARM_CM4_MPU/port.c b/portable/GCC/ARM_CM4_MPU/port.c
index ce234c455..f84ebd523 100644
--- a/portable/GCC/ARM_CM4_MPU/port.c
+++ b/portable/GCC/ARM_CM4_MPU/port.c
@@ -1385,7 +1385,7 @@ void vPortSwitchToUserMode( void )
 void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
                                 const struct xMEMORY_REGION * const xRegions,
                                 StackType_t * pxBottomOfStack,
-                                uint32_t ulStackDepth )
+                                configSTACK_DEPTH_TYPE uxStackDepth )
 {
     #if defined( __ARMCC_VERSION )
 
@@ -1442,7 +1442,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
          * which case the stack region parameters will be valid.  At all other
          * times the stack parameters will not be valid and it is assumed that the
          * stack region has already been configured. */
-        if( ulStackDepth > 0 )
+        if( uxStackDepth > 0 )
         {
             /* Define the region that allows access to the stack. */
             xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
@@ -1453,13 +1453,13 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
             xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
                 ( portMPU_REGION_READ_WRITE ) |
                 ( portMPU_REGION_EXECUTE_NEVER ) |
-                ( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |
+                ( prvGetMPURegionSizeSetting( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) ) |
                 ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
                 ( portMPU_REGION_ENABLE );
 
             xMPUSettings->xRegionSettings[ 0 ].ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
             xMPUSettings->xRegionSettings[ 0 ].ulRegionEndAddress = ( uint32_t ) ( ( uint32_t ) ( pxBottomOfStack ) +
-                                                                                   ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1UL );
+                                                                                   ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1UL );
             xMPUSettings->xRegionSettings[ 0 ].ulRegionPermissions = ( tskMPU_READ_PERMISSION |
                                                                        tskMPU_WRITE_PERMISSION );
         }
diff --git a/portable/GCC/ARM_CM55/non_secure/port.c b/portable/GCC/ARM_CM55/non_secure/port.c
index 45f9e2820..6d88b637f 100644
--- a/portable/GCC/ARM_CM55/non_secure/port.c
+++ b/portable/GCC/ARM_CM55/non_secure/port.c
@@ -1775,7 +1775,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
     void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
                                     const struct xMEMORY_REGION * const xRegions,
                                     StackType_t * pxBottomOfStack,
-                                    uint32_t ulStackDepth )
+                                    configSTACK_DEPTH_TYPE uxStackDepth )
     {
         uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
         int32_t lIndex = 0;
@@ -1800,10 +1800,10 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
          * which case the stack region parameters will be valid.  At all other
          * times the stack parameters will not be valid and it is assumed that
          * the stack region has already been configured. */
-        if( ulStackDepth > 0 )
+        if( uxStackDepth > 0 )
         {
             ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
-            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1;
 
             /* If the stack is within the privileged SRAM, do not protect it
              * using a separate MPU region. This is needed because privileged
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/port.c b/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
index 45f9e2820..6d88b637f 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
@@ -1775,7 +1775,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
     void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
                                     const struct xMEMORY_REGION * const xRegions,
                                     StackType_t * pxBottomOfStack,
-                                    uint32_t ulStackDepth )
+                                    configSTACK_DEPTH_TYPE uxStackDepth )
     {
         uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
         int32_t lIndex = 0;
@@ -1800,10 +1800,10 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
          * which case the stack region parameters will be valid.  At all other
          * times the stack parameters will not be valid and it is assumed that
          * the stack region has already been configured. */
-        if( ulStackDepth > 0 )
+        if( uxStackDepth > 0 )
         {
             ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
-            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1;
 
             /* If the stack is within the privileged SRAM, do not protect it
              * using a separate MPU region. This is needed because privileged
diff --git a/portable/GCC/ARM_CM85/non_secure/port.c b/portable/GCC/ARM_CM85/non_secure/port.c
index 45f9e2820..6d88b637f 100644
--- a/portable/GCC/ARM_CM85/non_secure/port.c
+++ b/portable/GCC/ARM_CM85/non_secure/port.c
@@ -1775,7 +1775,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
     void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
                                     const struct xMEMORY_REGION * const xRegions,
                                     StackType_t * pxBottomOfStack,
-                                    uint32_t ulStackDepth )
+                                    configSTACK_DEPTH_TYPE uxStackDepth )
     {
         uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
         int32_t lIndex = 0;
@@ -1800,10 +1800,10 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
          * which case the stack region parameters will be valid.  At all other
          * times the stack parameters will not be valid and it is assumed that
          * the stack region has already been configured. */
-        if( ulStackDepth > 0 )
+        if( uxStackDepth > 0 )
         {
             ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
-            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1;
 
             /* If the stack is within the privileged SRAM, do not protect it
              * using a separate MPU region. This is needed because privileged
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/port.c b/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
index 45f9e2820..6d88b637f 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
@@ -1775,7 +1775,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
     void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
                                     const struct xMEMORY_REGION * const xRegions,
                                     StackType_t * pxBottomOfStack,
-                                    uint32_t ulStackDepth )
+                                    configSTACK_DEPTH_TYPE uxStackDepth )
     {
         uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
         int32_t lIndex = 0;
@@ -1800,10 +1800,10 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
          * which case the stack region parameters will be valid.  At all other
          * times the stack parameters will not be valid and it is assumed that
          * the stack region has already been configured. */
-        if( ulStackDepth > 0 )
+        if( uxStackDepth > 0 )
         {
             ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
-            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1;
 
             /* If the stack is within the privileged SRAM, do not protect it
              * using a separate MPU region. This is needed because privileged
diff --git a/portable/IAR/ARM_CM23/non_secure/port.c b/portable/IAR/ARM_CM23/non_secure/port.c
index 45f9e2820..6d88b637f 100644
--- a/portable/IAR/ARM_CM23/non_secure/port.c
+++ b/portable/IAR/ARM_CM23/non_secure/port.c
@@ -1775,7 +1775,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
     void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
                                     const struct xMEMORY_REGION * const xRegions,
                                     StackType_t * pxBottomOfStack,
-                                    uint32_t ulStackDepth )
+                                    configSTACK_DEPTH_TYPE uxStackDepth )
     {
         uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
         int32_t lIndex = 0;
@@ -1800,10 +1800,10 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
          * which case the stack region parameters will be valid.  At all other
          * times the stack parameters will not be valid and it is assumed that
          * the stack region has already been configured. */
-        if( ulStackDepth > 0 )
+        if( uxStackDepth > 0 )
         {
             ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
-            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1;
 
             /* If the stack is within the privileged SRAM, do not protect it
              * using a separate MPU region. This is needed because privileged
diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
index 45f9e2820..6d88b637f 100644
--- a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
@@ -1775,7 +1775,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
     void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
                                     const struct xMEMORY_REGION * const xRegions,
                                     StackType_t * pxBottomOfStack,
-                                    uint32_t ulStackDepth )
+                                    configSTACK_DEPTH_TYPE uxStackDepth )
     {
         uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
         int32_t lIndex = 0;
@@ -1800,10 +1800,10 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
          * which case the stack region parameters will be valid.  At all other
          * times the stack parameters will not be valid and it is assumed that
          * the stack region has already been configured. */
-        if( ulStackDepth > 0 )
+        if( uxStackDepth > 0 )
         {
             ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
-            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1;
 
             /* If the stack is within the privileged SRAM, do not protect it
              * using a separate MPU region. This is needed because privileged
diff --git a/portable/IAR/ARM_CM33/non_secure/port.c b/portable/IAR/ARM_CM33/non_secure/port.c
index 45f9e2820..6d88b637f 100644
--- a/portable/IAR/ARM_CM33/non_secure/port.c
+++ b/portable/IAR/ARM_CM33/non_secure/port.c
@@ -1775,7 +1775,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
     void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
                                     const struct xMEMORY_REGION * const xRegions,
                                     StackType_t * pxBottomOfStack,
-                                    uint32_t ulStackDepth )
+                                    configSTACK_DEPTH_TYPE uxStackDepth )
     {
         uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
         int32_t lIndex = 0;
@@ -1800,10 +1800,10 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
          * which case the stack region parameters will be valid.  At all other
          * times the stack parameters will not be valid and it is assumed that
          * the stack region has already been configured. */
-        if( ulStackDepth > 0 )
+        if( uxStackDepth > 0 )
         {
             ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
-            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1;
 
             /* If the stack is within the privileged SRAM, do not protect it
              * using a separate MPU region. This is needed because privileged
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
index 45f9e2820..6d88b637f 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
@@ -1775,7 +1775,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
     void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
                                     const struct xMEMORY_REGION * const xRegions,
                                     StackType_t * pxBottomOfStack,
-                                    uint32_t ulStackDepth )
+                                    configSTACK_DEPTH_TYPE uxStackDepth )
     {
         uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
         int32_t lIndex = 0;
@@ -1800,10 +1800,10 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
          * which case the stack region parameters will be valid.  At all other
          * times the stack parameters will not be valid and it is assumed that
          * the stack region has already been configured. */
-        if( ulStackDepth > 0 )
+        if( uxStackDepth > 0 )
         {
             ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
-            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1;
 
             /* If the stack is within the privileged SRAM, do not protect it
              * using a separate MPU region. This is needed because privileged
diff --git a/portable/IAR/ARM_CM35P/non_secure/port.c b/portable/IAR/ARM_CM35P/non_secure/port.c
index 45f9e2820..6d88b637f 100644
--- a/portable/IAR/ARM_CM35P/non_secure/port.c
+++ b/portable/IAR/ARM_CM35P/non_secure/port.c
@@ -1775,7 +1775,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
     void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
                                     const struct xMEMORY_REGION * const xRegions,
                                     StackType_t * pxBottomOfStack,
-                                    uint32_t ulStackDepth )
+                                    configSTACK_DEPTH_TYPE uxStackDepth )
     {
         uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
         int32_t lIndex = 0;
@@ -1800,10 +1800,10 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
          * which case the stack region parameters will be valid.  At all other
          * times the stack parameters will not be valid and it is assumed that
          * the stack region has already been configured. */
-        if( ulStackDepth > 0 )
+        if( uxStackDepth > 0 )
         {
             ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
-            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1;
 
             /* If the stack is within the privileged SRAM, do not protect it
              * using a separate MPU region. This is needed because privileged
diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c b/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
index 45f9e2820..6d88b637f 100644
--- a/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
@@ -1775,7 +1775,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
     void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
                                     const struct xMEMORY_REGION * const xRegions,
                                     StackType_t * pxBottomOfStack,
-                                    uint32_t ulStackDepth )
+                                    configSTACK_DEPTH_TYPE uxStackDepth )
     {
         uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
         int32_t lIndex = 0;
@@ -1800,10 +1800,10 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
          * which case the stack region parameters will be valid.  At all other
          * times the stack parameters will not be valid and it is assumed that
          * the stack region has already been configured. */
-        if( ulStackDepth > 0 )
+        if( uxStackDepth > 0 )
         {
             ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
-            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1;
 
             /* If the stack is within the privileged SRAM, do not protect it
              * using a separate MPU region. This is needed because privileged
diff --git a/portable/IAR/ARM_CM4F_MPU/port.c b/portable/IAR/ARM_CM4F_MPU/port.c
index a682a9d87..b3db081f3 100644
--- a/portable/IAR/ARM_CM4F_MPU/port.c
+++ b/portable/IAR/ARM_CM4F_MPU/port.c
@@ -1127,7 +1127,7 @@ static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )
 void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
                                 const struct xMEMORY_REGION * const xRegions,
                                 StackType_t * pxBottomOfStack,
-                                uint32_t ulStackDepth )
+                                configSTACK_DEPTH_TYPE uxStackDepth )
 {
     extern uint32_t __SRAM_segment_start__[];
     extern uint32_t __SRAM_segment_end__[];
@@ -1172,7 +1172,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
          * which case the stack region parameters will be valid.  At all other
          * times the stack parameters will not be valid and it is assumed that the
          * stack region has already been configured. */
-        if( ulStackDepth > 0 )
+        if( uxStackDepth > 0 )
         {
             /* Define the region that allows access to the stack. */
             xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
@@ -1183,13 +1183,13 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
             xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
                 ( portMPU_REGION_READ_WRITE ) |
                 ( portMPU_REGION_EXECUTE_NEVER ) |
-                ( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |
+                ( prvGetMPURegionSizeSetting( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) ) |
                 ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
                 ( portMPU_REGION_ENABLE );
 
             xMPUSettings->xRegionSettings[ 0 ].ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
             xMPUSettings->xRegionSettings[ 0 ].ulRegionEndAddress = ( uint32_t ) ( ( uint32_t ) ( pxBottomOfStack ) +
-                                                                                   ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1UL );
+                                                                                   ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1UL );
             xMPUSettings->xRegionSettings[ 0 ].ulRegionPermissions = ( tskMPU_READ_PERMISSION |
                                                                        tskMPU_WRITE_PERMISSION );
         }
diff --git a/portable/IAR/ARM_CM55/non_secure/port.c b/portable/IAR/ARM_CM55/non_secure/port.c
index 45f9e2820..6d88b637f 100644
--- a/portable/IAR/ARM_CM55/non_secure/port.c
+++ b/portable/IAR/ARM_CM55/non_secure/port.c
@@ -1775,7 +1775,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
     void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
                                     const struct xMEMORY_REGION * const xRegions,
                                     StackType_t * pxBottomOfStack,
-                                    uint32_t ulStackDepth )
+                                    configSTACK_DEPTH_TYPE uxStackDepth )
     {
         uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
         int32_t lIndex = 0;
@@ -1800,10 +1800,10 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
          * which case the stack region parameters will be valid.  At all other
          * times the stack parameters will not be valid and it is assumed that
          * the stack region has already been configured. */
-        if( ulStackDepth > 0 )
+        if( uxStackDepth > 0 )
         {
             ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
-            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1;
 
             /* If the stack is within the privileged SRAM, do not protect it
              * using a separate MPU region. This is needed because privileged
diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/port.c b/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
index 45f9e2820..6d88b637f 100644
--- a/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
@@ -1775,7 +1775,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
     void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
                                     const struct xMEMORY_REGION * const xRegions,
                                     StackType_t * pxBottomOfStack,
-                                    uint32_t ulStackDepth )
+                                    configSTACK_DEPTH_TYPE uxStackDepth )
     {
         uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
         int32_t lIndex = 0;
@@ -1800,10 +1800,10 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
          * which case the stack region parameters will be valid.  At all other
          * times the stack parameters will not be valid and it is assumed that
          * the stack region has already been configured. */
-        if( ulStackDepth > 0 )
+        if( uxStackDepth > 0 )
         {
             ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
-            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1;
 
             /* If the stack is within the privileged SRAM, do not protect it
              * using a separate MPU region. This is needed because privileged
diff --git a/portable/IAR/ARM_CM85/non_secure/port.c b/portable/IAR/ARM_CM85/non_secure/port.c
index 45f9e2820..6d88b637f 100644
--- a/portable/IAR/ARM_CM85/non_secure/port.c
+++ b/portable/IAR/ARM_CM85/non_secure/port.c
@@ -1775,7 +1775,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
     void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
                                     const struct xMEMORY_REGION * const xRegions,
                                     StackType_t * pxBottomOfStack,
-                                    uint32_t ulStackDepth )
+                                    configSTACK_DEPTH_TYPE uxStackDepth )
     {
         uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
         int32_t lIndex = 0;
@@ -1800,10 +1800,10 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
          * which case the stack region parameters will be valid.  At all other
          * times the stack parameters will not be valid and it is assumed that
          * the stack region has already been configured. */
-        if( ulStackDepth > 0 )
+        if( uxStackDepth > 0 )
         {
             ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
-            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1;
 
             /* If the stack is within the privileged SRAM, do not protect it
              * using a separate MPU region. This is needed because privileged
diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/port.c b/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
index 45f9e2820..6d88b637f 100644
--- a/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
@@ -1775,7 +1775,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
     void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
                                     const struct xMEMORY_REGION * const xRegions,
                                     StackType_t * pxBottomOfStack,
-                                    uint32_t ulStackDepth )
+                                    configSTACK_DEPTH_TYPE uxStackDepth )
     {
         uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
         int32_t lIndex = 0;
@@ -1800,10 +1800,10 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
          * which case the stack region parameters will be valid.  At all other
          * times the stack parameters will not be valid and it is assumed that
          * the stack region has already been configured. */
-        if( ulStackDepth > 0 )
+        if( uxStackDepth > 0 )
         {
             ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
-            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1;
 
             /* If the stack is within the privileged SRAM, do not protect it
              * using a separate MPU region. This is needed because privileged
diff --git a/portable/RVDS/ARM_CM4_MPU/port.c b/portable/RVDS/ARM_CM4_MPU/port.c
index 364370109..016521cf2 100644
--- a/portable/RVDS/ARM_CM4_MPU/port.c
+++ b/portable/RVDS/ARM_CM4_MPU/port.c
@@ -1380,7 +1380,7 @@ void vPortSwitchToUserMode( void )
 void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
                                 const struct xMEMORY_REGION * const xRegions,
                                 StackType_t * pxBottomOfStack,
-                                uint32_t ulStackDepth )
+                                configSTACK_DEPTH_TYPE uxStackDepth )
 {
     extern uint32_t __SRAM_segment_start__;
     extern uint32_t __SRAM_segment_end__;
@@ -1427,7 +1427,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
          * which case the stack region parameters will be valid.  At all other
          * times the stack parameters will not be valid and it is assumed that the
          * stack region has already been configured. */
-        if( ulStackDepth > 0 )
+        if( uxStackDepth > 0 )
         {
             /* Define the region that allows access to the stack. */
             xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
@@ -1438,13 +1438,13 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
             xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
                 ( portMPU_REGION_READ_WRITE ) |
                 ( portMPU_REGION_EXECUTE_NEVER ) |
-                ( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |
+                ( prvGetMPURegionSizeSetting( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) ) |
                 ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
                 ( portMPU_REGION_ENABLE );
 
             xMPUSettings->xRegionSettings[ 0 ].ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
             xMPUSettings->xRegionSettings[ 0 ].ulRegionEndAddress = ( uint32_t ) ( ( uint32_t ) ( pxBottomOfStack ) +
-                                                                                   ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1UL );
+                                                                                   ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1UL );
             xMPUSettings->xRegionSettings[ 0 ].ulRegionPermissions = ( tskMPU_READ_PERMISSION |
                                                                        tskMPU_WRITE_PERMISSION );
         }
@@ -1508,7 +1508,7 @@ BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
     BaseType_t xAccessGranted = pdFALSE;
     const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
 
-    
+
     if( xSchedulerRunning == pdFALSE )
     {
         /* Grant access to all the kernel objects before the scheduler
diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/include/portmacro.h b/portable/ThirdParty/GCC/Xtensa_ESP32/include/portmacro.h
index c5981eaa5..d3635f13b 100644
--- a/portable/ThirdParty/GCC/Xtensa_ESP32/include/portmacro.h
+++ b/portable/ThirdParty/GCC/Xtensa_ESP32/include/portmacro.h
@@ -522,7 +522,7 @@
         void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
                                         const struct xMEMORY_REGION * const xRegions,
                                         StackType_t * pxBottomOfStack,
-                                        uint32_t usStackDepth ) PRIVILEGED_FUNCTION;
+                                        configSTACK_DEPTH_TYPE uxStackDepth ) PRIVILEGED_FUNCTION;
         void vPortReleaseTaskMPUSettings( xMPU_SETTINGS * xMPUSettings );
     #endif
 
diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/port.c b/portable/ThirdParty/GCC/Xtensa_ESP32/port.c
index 49139d71d..3f30592e7 100644
--- a/portable/ThirdParty/GCC/Xtensa_ESP32/port.c
+++ b/portable/ThirdParty/GCC/Xtensa_ESP32/port.c
@@ -308,10 +308,10 @@ void vPortYieldOtherCore( BaseType_t coreid )
     void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
                                     const struct xMEMORY_REGION * const xRegions,
                                     StackType_t * pxBottomOfStack,
-                                    uint32_t usStackDepth )
+                                    configSTACK_DEPTH_TYPE uxStackDepth )
     {
         #if XCHAL_CP_NUM > 0
-            xMPUSettings->coproc_area = ( StackType_t * ) ( ( uint32_t ) ( pxBottomOfStack + usStackDepth - 1 ) );
+            xMPUSettings->coproc_area = ( StackType_t * ) ( ( uint32_t ) ( pxBottomOfStack + uxStackDepth - 1 ) );
             xMPUSettings->coproc_area = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) xMPUSettings->coproc_area ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) );
             xMPUSettings->coproc_area = ( StackType_t * ) ( ( ( uint32_t ) xMPUSettings->coproc_area - XT_CP_SIZE ) & ~0xf );
 
diff --git a/portable/ThirdParty/XCC/Xtensa/port.c b/portable/ThirdParty/XCC/Xtensa/port.c
index 805a78401..70c2679b5 100644
--- a/portable/ThirdParty/XCC/Xtensa/port.c
+++ b/portable/ThirdParty/XCC/Xtensa/port.c
@@ -190,19 +190,20 @@ BaseType_t xPortSysTickHandler( void )
  * Used to set coprocessor area in stack. Current hack is to reuse MPU pointer for coprocessor area.
  */
 #if portUSING_MPU_WRAPPERS
-void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
-                                const struct xMEMORY_REGION * const xRegions,
-                                StackType_t * pxBottomOfStack,
-                                uint32_t ulStackDepth )
-{
-    #if XCHAL_CP_NUM > 0
-        xMPUSettings->coproc_area = ( StackType_t * ) ( ( uint32_t ) ( pxBottomOfStack + ulStackDepth - 1 ));
-        xMPUSettings->coproc_area = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) xMPUSettings->coproc_area ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) );
-        xMPUSettings->coproc_area = ( StackType_t * ) ( ( ( uint32_t ) xMPUSettings->coproc_area - XT_CP_SIZE ) & ~0xf );
 
-        /* NOTE: we cannot initialize the coprocessor save area here because FreeRTOS is going to
-         * clear the stack area after we return. This is done in pxPortInitialiseStack().
-         */
-    #endif
-}
+    void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
+                                    const struct xMEMORY_REGION * const xRegions,
+                                    StackType_t * pxBottomOfStack,
+                                    configSTACK_DEPTH_TYPE uxStackDepth )
+    {
+        #if XCHAL_CP_NUM > 0
+            xMPUSettings->coproc_area = ( StackType_t * ) ( ( uint32_t ) ( pxBottomOfStack + uxStackDepth - 1 ) );
+            xMPUSettings->coproc_area = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) xMPUSettings->coproc_area ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) );
+            xMPUSettings->coproc_area = ( StackType_t * ) ( ( ( uint32_t ) xMPUSettings->coproc_area - XT_CP_SIZE ) & ~0xf );
+
+            /* NOTE: we cannot initialize the coprocessor save area here because FreeRTOS is going to
+             * clear the stack area after we return. This is done in pxPortInitialiseStack().
+             */
+        #endif
+    }
 #endif /* if portUSING_MPU_WRAPPERS */
diff --git a/tasks.c b/tasks.c
index 26a442637..9f6c5f879 100644
--- a/tasks.c
+++ b/tasks.c
@@ -143,8 +143,8 @@
 #define tskSUSPENDED_CHAR    ( 'S' )
 
 /*
- * Some kernel aware debuggers require the data the debugger needs access to to
- * be global, rather than file scope.
+ * Some kernel aware debuggers require the data the debugger needs access to be
+ * global, rather than file scope.
  */
 #ifdef portREMOVE_STATIC_QUALIFIER
     #define static
@@ -698,7 +698,7 @@ static void prvResetNextTaskUnblockTime( void ) PRIVILEGED_FUNCTION;
  */
 static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
                                   const char * const pcName,
-                                  const uint32_t ulStackDepth,
+                                  const configSTACK_DEPTH_TYPE uxStackDepth,
                                   void * const pvParameters,
                                   UBaseType_t uxPriority,
                                   TaskHandle_t * const pxCreatedTask,
@@ -718,7 +718,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
 #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
     static TCB_t * prvCreateStaticTask( TaskFunction_t pxTaskCode,
                                         const char * const pcName,
-                                        const uint32_t ulStackDepth,
+                                        const configSTACK_DEPTH_TYPE uxStackDepth,
                                         void * const pvParameters,
                                         UBaseType_t uxPriority,
                                         StackType_t * const puxStackBuffer,
@@ -752,7 +752,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
 #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
     static TCB_t * prvCreateTask( TaskFunction_t pxTaskCode,
                                   const char * const pcName,
-                                  const configSTACK_DEPTH_TYPE usStackDepth,
+                                  const configSTACK_DEPTH_TYPE uxStackDepth,
                                   void * const pvParameters,
                                   UBaseType_t uxPriority,
                                   TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION;
@@ -1252,7 +1252,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
 
     static TCB_t * prvCreateStaticTask( TaskFunction_t pxTaskCode,
                                         const char * const pcName,
-                                        const uint32_t ulStackDepth,
+                                        const configSTACK_DEPTH_TYPE uxStackDepth,
                                         void * const pvParameters,
                                         UBaseType_t uxPriority,
                                         StackType_t * const puxStackBuffer,
@@ -1294,7 +1294,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
             }
             #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
 
-            prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL );
+            prvInitialiseNewTask( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL );
         }
         else
         {
@@ -1307,7 +1307,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
 
     TaskHandle_t xTaskCreateStatic( TaskFunction_t pxTaskCode,
                                     const char * const pcName,
-                                    const uint32_t ulStackDepth,
+                                    const configSTACK_DEPTH_TYPE uxStackDepth,
                                     void * const pvParameters,
                                     UBaseType_t uxPriority,
                                     StackType_t * const puxStackBuffer,
@@ -1316,9 +1316,9 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
         TaskHandle_t xReturn = NULL;
         TCB_t * pxNewTCB;
 
-        traceENTER_xTaskCreateStatic( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer );
+        traceENTER_xTaskCreateStatic( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer );
 
-        pxNewTCB = prvCreateStaticTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer, &xReturn );
+        pxNewTCB = prvCreateStaticTask( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer, &xReturn );
 
         if( pxNewTCB != NULL )
         {
@@ -1345,7 +1345,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
     #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
         TaskHandle_t xTaskCreateStaticAffinitySet( TaskFunction_t pxTaskCode,
                                                    const char * const pcName,
-                                                   const uint32_t ulStackDepth,
+                                                   const configSTACK_DEPTH_TYPE uxStackDepth,
                                                    void * const pvParameters,
                                                    UBaseType_t uxPriority,
                                                    StackType_t * const puxStackBuffer,
@@ -1355,9 +1355,9 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
             TaskHandle_t xReturn = NULL;
             TCB_t * pxNewTCB;
 
-            traceENTER_xTaskCreateStaticAffinitySet( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer, uxCoreAffinityMask );
+            traceENTER_xTaskCreateStaticAffinitySet( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer, uxCoreAffinityMask );
 
-            pxNewTCB = prvCreateStaticTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer, &xReturn );
+            pxNewTCB = prvCreateStaticTask( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer, &xReturn );
 
             if( pxNewTCB != NULL )
             {
@@ -1410,7 +1410,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
 
             prvInitialiseNewTask( pxTaskDefinition->pvTaskCode,
                                   pxTaskDefinition->pcName,
-                                  ( uint32_t ) pxTaskDefinition->usStackDepth,
+                                  pxTaskDefinition->usStackDepth,
                                   pxTaskDefinition->pvParameters,
                                   pxTaskDefinition->uxPriority,
                                   pxCreatedTask, pxNewTCB,
@@ -1529,7 +1529,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
 
                 prvInitialiseNewTask( pxTaskDefinition->pvTaskCode,
                                       pxTaskDefinition->pcName,
-                                      ( uint32_t ) pxTaskDefinition->usStackDepth,
+                                      pxTaskDefinition->usStackDepth,
                                       pxTaskDefinition->pvParameters,
                                       pxTaskDefinition->uxPriority,
                                       pxCreatedTask, pxNewTCB,
@@ -1618,7 +1618,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
 #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
     static TCB_t * prvCreateTask( TaskFunction_t pxTaskCode,
                                   const char * const pcName,
-                                  const configSTACK_DEPTH_TYPE usStackDepth,
+                                  const configSTACK_DEPTH_TYPE uxStackDepth,
                                   void * const pvParameters,
                                   UBaseType_t uxPriority,
                                   TaskHandle_t * const pxCreatedTask )
@@ -1648,7 +1648,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
                 /* MISRA Ref 11.5.1 [Malloc memory assignment] */
                 /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
                 /* coverity[misra_c_2012_rule_11_5_violation] */
-                pxNewTCB->pxStack = ( StackType_t * ) pvPortMallocStack( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) );
+                pxNewTCB->pxStack = ( StackType_t * ) pvPortMallocStack( ( ( ( size_t ) uxStackDepth ) * sizeof( StackType_t ) ) );
 
                 if( pxNewTCB->pxStack == NULL )
                 {
@@ -1666,7 +1666,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
             /* MISRA Ref 11.5.1 [Malloc memory assignment] */
             /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
             /* coverity[misra_c_2012_rule_11_5_violation] */
-            pxStack = pvPortMallocStack( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) );
+            pxStack = pvPortMallocStack( ( ( ( size_t ) uxStackDepth ) * sizeof( StackType_t ) ) );
 
             if( pxStack != NULL )
             {
@@ -1707,7 +1707,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
             }
             #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
 
-            prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL );
+            prvInitialiseNewTask( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL );
         }
 
         return pxNewTCB;
@@ -1716,7 +1716,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
 
     BaseType_t xTaskCreate( TaskFunction_t pxTaskCode,
                             const char * const pcName,
-                            const configSTACK_DEPTH_TYPE usStackDepth,
+                            const configSTACK_DEPTH_TYPE uxStackDepth,
                             void * const pvParameters,
                             UBaseType_t uxPriority,
                             TaskHandle_t * const pxCreatedTask )
@@ -1724,9 +1724,9 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
         TCB_t * pxNewTCB;
         BaseType_t xReturn;
 
-        traceENTER_xTaskCreate( pxTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask );
+        traceENTER_xTaskCreate( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, pxCreatedTask );
 
-        pxNewTCB = prvCreateTask( pxTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask );
+        pxNewTCB = prvCreateTask( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, pxCreatedTask );
 
         if( pxNewTCB != NULL )
         {
@@ -1754,7 +1754,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
     #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
         BaseType_t xTaskCreateAffinitySet( TaskFunction_t pxTaskCode,
                                            const char * const pcName,
-                                           const configSTACK_DEPTH_TYPE usStackDepth,
+                                           const configSTACK_DEPTH_TYPE uxStackDepth,
                                            void * const pvParameters,
                                            UBaseType_t uxPriority,
                                            UBaseType_t uxCoreAffinityMask,
@@ -1763,9 +1763,9 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
             TCB_t * pxNewTCB;
             BaseType_t xReturn;
 
-            traceENTER_xTaskCreateAffinitySet( pxTaskCode, pcName, usStackDepth, pvParameters, uxPriority, uxCoreAffinityMask, pxCreatedTask );
+            traceENTER_xTaskCreateAffinitySet( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, uxCoreAffinityMask, pxCreatedTask );
 
-            pxNewTCB = prvCreateTask( pxTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask );
+            pxNewTCB = prvCreateTask( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, pxCreatedTask );
 
             if( pxNewTCB != NULL )
             {
@@ -1791,7 +1791,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
 
 static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
                                   const char * const pcName,
-                                  const uint32_t ulStackDepth,
+                                  const configSTACK_DEPTH_TYPE uxStackDepth,
                                   void * const pvParameters,
                                   UBaseType_t uxPriority,
                                   TaskHandle_t * const pxCreatedTask,
@@ -1820,7 +1820,7 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
     #if ( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 )
     {
         /* Fill the stack with a known value to assist debugging. */
-        ( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) );
+        ( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) uxStackDepth * sizeof( StackType_t ) );
     }
     #endif /* tskSET_NEW_STACKS_TO_KNOWN_VALUE */
 
@@ -1830,7 +1830,7 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
      * by the port. */
     #if ( portSTACK_GROWTH < 0 )
     {
-        pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] );
+        pxTopOfStack = &( pxNewTCB->pxStack[ uxStackDepth - ( configSTACK_DEPTH_TYPE ) 1 ] );
         pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) );
 
         /* Check the alignment of the calculated top of stack is correct. */
@@ -1854,7 +1854,7 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
 
         /* The other extreme of the stack space is required if stack checking is
          * performed. */
-        pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 );
+        pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( uxStackDepth - ( configSTACK_DEPTH_TYPE ) 1 );
     }
     #endif /* portSTACK_GROWTH */
 
@@ -1919,7 +1919,7 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
 
     #if ( portUSING_MPU_WRAPPERS == 1 )
     {
-        vPortStoreTaskMPUSettings( &( pxNewTCB->xMPUSettings ), xRegions, pxNewTCB->pxStack, ulStackDepth );
+        vPortStoreTaskMPUSettings( &( pxNewTCB->xMPUSettings ), xRegions, pxNewTCB->pxStack, uxStackDepth );
     }
     #else
     {
@@ -3558,29 +3558,29 @@ static BaseType_t prvCreateIdleTasks( void )
         {
             StaticTask_t * pxIdleTaskTCBBuffer = NULL;
             StackType_t * pxIdleTaskStackBuffer = NULL;
-            uint32_t ulIdleTaskStackSize;
+            configSTACK_DEPTH_TYPE uxIdleTaskStackSize;
 
             /* The Idle task is created using user provided RAM - obtain the
              * address of the RAM then create the idle task. */
             #if ( configNUMBER_OF_CORES == 1 )
             {
-                vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize );
+                vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &uxIdleTaskStackSize );
             }
             #else
             {
                 if( xCoreID == 0 )
                 {
-                    vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize );
+                    vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &uxIdleTaskStackSize );
                 }
                 else
                 {
-                    vApplicationGetPassiveIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize, xCoreID - 1 );
+                    vApplicationGetPassiveIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &uxIdleTaskStackSize, xCoreID - 1 );
                 }
             }
             #endif /* if ( configNUMBER_OF_CORES == 1 ) */
             xIdleTaskHandles[ xCoreID ] = xTaskCreateStatic( pxIdleTaskFunction,
                                                              cIdleName,
-                                                             ulIdleTaskStackSize,
+                                                             uxIdleTaskStackSize,
                                                              ( void * ) NULL,
                                                              portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
                                                              pxIdleTaskStackBuffer,
@@ -6323,17 +6323,17 @@ static void prvCheckTasksWaitingTermination( void )
 
     static configSTACK_DEPTH_TYPE prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte )
     {
-        uint32_t ulCount = 0U;
+        configSTACK_DEPTH_TYPE uxCount = 0U;
 
         while( *pucStackByte == ( uint8_t ) tskSTACK_FILL_BYTE )
         {
             pucStackByte -= portSTACK_GROWTH;
-            ulCount++;
+            uxCount++;
         }
 
-        ulCount /= ( uint32_t ) sizeof( StackType_t );
+        uxCount /= ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t );
 
-        return ( configSTACK_DEPTH_TYPE ) ulCount;
+        return uxCount;
     }
 
 #endif /* ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) ) */
@@ -8623,21 +8623,21 @@ static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait,
  */
     void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer,
                                         StackType_t ** ppxIdleTaskStackBuffer,
-                                        uint32_t * pulIdleTaskStackSize )
+                                        configSTACK_DEPTH_TYPE * puxIdleTaskStackSize )
     {
         static StaticTask_t xIdleTaskTCB;
         static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ];
 
         *ppxIdleTaskTCBBuffer = &( xIdleTaskTCB );
         *ppxIdleTaskStackBuffer = &( uxIdleTaskStack[ 0 ] );
-        *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;
+        *puxIdleTaskStackSize = configMINIMAL_STACK_SIZE;
     }
 
     #if ( configNUMBER_OF_CORES > 1 )
 
         void vApplicationGetPassiveIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer,
                                                    StackType_t ** ppxIdleTaskStackBuffer,
-                                                   uint32_t * pulIdleTaskStackSize,
+                                                   configSTACK_DEPTH_TYPE * puxIdleTaskStackSize,
                                                    BaseType_t xPassiveIdleTaskIndex )
         {
             static StaticTask_t xIdleTaskTCBs[ configNUMBER_OF_CORES - 1 ];
@@ -8645,7 +8645,7 @@ static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait,
 
             *ppxIdleTaskTCBBuffer = &( xIdleTaskTCBs[ xPassiveIdleTaskIndex ] );
             *ppxIdleTaskStackBuffer = &( uxIdleTaskStacks[ xPassiveIdleTaskIndex ][ 0 ] );
-            *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;
+            *puxIdleTaskStackSize = configMINIMAL_STACK_SIZE;
         }
 
     #endif /* #if ( configNUMBER_OF_CORES > 1 ) */
@@ -8664,14 +8664,14 @@ static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait,
  */
     void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer,
                                          StackType_t ** ppxTimerTaskStackBuffer,
-                                         uint32_t * pulTimerTaskStackSize )
+                                         configSTACK_DEPTH_TYPE * puxTimerTaskStackSize )
     {
         static StaticTask_t xTimerTaskTCB;
         static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ];
 
         *ppxTimerTaskTCBBuffer = &( xTimerTaskTCB );
         *ppxTimerTaskStackBuffer = &( uxTimerTaskStack[ 0 ] );
-        *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH;
+        *puxTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH;
     }
 
 #endif /* #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configKERNEL_PROVIDED_STATIC_MEMORY == 1 ) && ( portUSING_MPU_WRAPPERS == 0 ) ) */
diff --git a/timers.c b/timers.c
index df7f442c3..a432e74c2 100644
--- a/timers.c
+++ b/timers.c
@@ -254,12 +254,12 @@
                 {
                     StaticTask_t * pxTimerTaskTCBBuffer = NULL;
                     StackType_t * pxTimerTaskStackBuffer = NULL;
-                    uint32_t ulTimerTaskStackSize;
+                    configSTACK_DEPTH_TYPE uxTimerTaskStackSize;
 
-                    vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize );
+                    vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &uxTimerTaskStackSize );
                     xTimerTaskHandle = xTaskCreateStaticAffinitySet( prvTimerTask,
                                                                      configTIMER_SERVICE_TASK_NAME,
-                                                                     ulTimerTaskStackSize,
+                                                                     uxTimerTaskStackSize,
                                                                      NULL,
                                                                      ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
                                                                      pxTimerTaskStackBuffer,
@@ -289,12 +289,12 @@
                 {
                     StaticTask_t * pxTimerTaskTCBBuffer = NULL;
                     StackType_t * pxTimerTaskStackBuffer = NULL;
-                    uint32_t ulTimerTaskStackSize;
+                    configSTACK_DEPTH_TYPE uxTimerTaskStackSize;
 
-                    vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize );
+                    vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &uxTimerTaskStackSize );
                     xTimerTaskHandle = xTaskCreateStatic( prvTimerTask,
                                                           configTIMER_SERVICE_TASK_NAME,
-                                                          ulTimerTaskStackSize,
+                                                          uxTimerTaskStackSize,
                                                           NULL,
                                                           ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
                                                           pxTimerTaskStackBuffer,

From b1ee2e6e149a74491b8f917e04c5448fe15fcfd1 Mon Sep 17 00:00:00 2001
From: Soren Ptak <ptaksoren@gmail.com>
Date: Sun, 28 Jan 2024 08:11:03 -0500
Subject: [PATCH 200/424] Fix MacOS Posix port (#957)

PR #914 caused Posix Port to fail to build on MacOS. This PR fixes
teh build failure.

This PR also adds a Matrix configuration to the GitHub kernel-demo
workflow to build the Posix Demos on MacOS.
---------

Co-authored-by: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
---
 .github/workflows/kernel-demos.yml   |  9 ++++++++-
 portable/ThirdParty/GCC/Posix/port.c | 14 ++++++++++----
 2 files changed, 18 insertions(+), 5 deletions(-)

diff --git a/.github/workflows/kernel-demos.yml b/.github/workflows/kernel-demos.yml
index b29209c10..9a74e3d00 100644
--- a/.github/workflows/kernel-demos.yml
+++ b/.github/workflows/kernel-demos.yml
@@ -65,7 +65,13 @@ jobs:
 
   POSIX-GCC:
     name: Native GCC
-    runs-on: ubuntu-latest
+    strategy:
+      fail-fast: false
+      matrix:
+        os:
+          - macos-latest
+          - ubuntu-latest
+    runs-on: ${{ matrix.os }}
     steps:
       - name: Checkout the FreeRTOS/FreeRTOS Repository
         uses: actions/checkout@v3
@@ -83,6 +89,7 @@ jobs:
 
       - name: Install GCC
         shell: bash
+        if: matrix.os == 'ubuntu-latest'
         run: |
           sudo apt-get -y update
           sudo apt-get -y install build-essential
diff --git a/portable/ThirdParty/GCC/Posix/port.c b/portable/ThirdParty/GCC/Posix/port.c
index f84517346..65ba54c7b 100644
--- a/portable/ThirdParty/GCC/Posix/port.c
+++ b/portable/ThirdParty/GCC/Posix/port.c
@@ -57,6 +57,7 @@
 
 #include <errno.h>
 #include <pthread.h>
+#include <limits.h>
 #include <signal.h>
 #include <stdio.h>
 #include <stdlib.h>
@@ -281,10 +282,15 @@ BaseType_t xPortStartScheduler( void )
      */
     xSchedulerEnd = pdFALSE;
 
-    /* Reset the pthread_once_t structure. This is required if the port
-     * starts the scheduler again. */
-    hSigSetupThread = PTHREAD_ONCE_INIT;
-
+    /* Reset pthread_once_t, needed to restart the scheduler again.
+     * memset the internal struct members for MacOS/Linux Compatability */
+    #if __APPLE__
+        hSigSetupThread.__sig = _PTHREAD_ONCE_SIG_init;
+        memset( ( void * ) &hSigSetupThread.__opaque, 0, sizeof(hSigSetupThread.__opaque));
+    #else /* Linux PTHREAD library*/
+        hSigSetupThread = PTHREAD_ONCE_INIT;
+    #endif /* __APPLE__*/
+    
     /* Restore original signal mask. */
     ( void ) pthread_sigmask( SIG_SETMASK, &xSchedulerOriginalSignalMask, NULL );
 

From 1860c9ad09b98102a621a546a259ab69169f6579 Mon Sep 17 00:00:00 2001
From: Forty-Bot <Forty-Bot@users.noreply.github.com>
Date: Mon, 29 Jan 2024 00:37:43 -0500
Subject: [PATCH 201/424] GCC: MSP430F449: Fix pxPortInitialiseStack on EABI
 (#947)

According to the MSP430 EABI [1] section 3.3,

Arguments are assigned, in declared order, to the first available
register single, pair, or quad from the following list into which it
fits (with the following special exceptions). For MSP430 and
MSP430X, the argument registers are: R12, R13, R14, R15

Therefore, pvParameters should be passed in R12, as it is the first
argument, not R15. Keep passing the parameter in R15 for the
MSP430 EABI, if anyone is still using it.

[1] https://www.ti.com/lit/an/slaa534a/slaa534a.pdf
---
 portable/GCC/MSP430F449/port.c | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/portable/GCC/MSP430F449/port.c b/portable/GCC/MSP430F449/port.c
index ca72b410b..488ad2d6f 100644
--- a/portable/GCC/MSP430F449/port.c
+++ b/portable/GCC/MSP430F449/port.c
@@ -183,16 +183,23 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
     pxTopOfStack--;
     *pxTopOfStack = ( StackType_t ) 0xbbbb;
     pxTopOfStack--;
+#ifdef __MSPGCC__
     *pxTopOfStack = ( StackType_t ) 0xcccc;
+#else
+    /* The MSP430 EABI expects the function parameter in R12. */
+    *pxTopOfStack = ( StackType_t ) pvParameters;
+#endif
     pxTopOfStack--;
     *pxTopOfStack = ( StackType_t ) 0xdddd;
     pxTopOfStack--;
     *pxTopOfStack = ( StackType_t ) 0xeeee;
     pxTopOfStack--;
-
-    /* When the task starts is will expect to find the function parameter in
-     * R15. */
+#ifdef __MSPGCC__
+    /* The mspgcc ABI expects the function parameter in R15. */
     *pxTopOfStack = ( StackType_t ) pvParameters;
+#else
+    *pxTopOfStack = ( StackType_t ) 0xffff;
+#endif
     pxTopOfStack--;
 
     /* The code generated by the mspgcc compiler does not maintain separate

From 722596eaae46a54b48b194d21541a9ef24d84388 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= <jose.simoes@eclo.solutions>
Date: Mon, 29 Jan 2024 06:35:10 +0000
Subject: [PATCH 202/424] Add code to allow building for x64 in MSVC (#924)

* Add code to allow building for x64 in MSVC

- Add code for x64 arch.
- Add initial value for local otherwise it won't get proper value in x64.

* Moving init local to portGET_HIGHEST_PRIORITY

- From code review.

* More changes following review

* Another style fix from review

* Update formatting

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Co-authored-by: Nikhil Kamath <110539926+amazonKamath@users.noreply.github.com>
Co-authored-by: Soren Ptak <ptaksoren@gmail.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 portable/MSVC-MingW/portmacro.h | 48 ++++++++++++++++++++++-----------
 1 file changed, 33 insertions(+), 15 deletions(-)

diff --git a/portable/MSVC-MingW/portmacro.h b/portable/MSVC-MingW/portmacro.h
index 48a8bf4b0..9e64b7343 100644
--- a/portable/MSVC-MingW/portmacro.h
+++ b/portable/MSVC-MingW/portmacro.h
@@ -121,32 +121,50 @@ void vPortExitCritical( void );
     #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
 #endif
 
+/*-----------------------------------------------------------*/
+
 #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
 
-/* Check the configuration. */
+    /* Check the configuration. */
     #if ( configMAX_PRIORITIES > 32 )
         #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
     #endif
 
-/* Store/clear the ready priorities in a bit map. */
-    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-
-
-/*-----------------------------------------------------------*/
+    /* Store/clear the ready priorities in a bit map. */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( ( ( UBaseType_t ) 1 ) << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( ( ( UBaseType_t ) 1 ) << ( uxPriority ) )
 
     #ifdef __GNUC__
-        #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) \
-    __asm volatile ( "bsr %1, %0\n\t"                                        \
-                     : "=r" ( uxTopPriority ) : "rm" ( uxReadyPriorities ) : "cc" )
-    #else
 
-/* BitScanReverse returns the bit position of the most significant '1'
- * in the word. */
-        #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    _BitScanReverse( ( DWORD * ) &( uxTopPriority ), ( uxReadyPriorities ) )
+        #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    \
+        __asm volatile ( "bsr %1, %0\n\t"                                       \
+                         : "=r" ( uxTopPriority )                               \
+                         : "rm" ( uxReadyPriorities )                           \
+                         : "cc" )
+
+    #else /* __GNUC__ */
+
+        /* BitScanReverse returns the bit position of the most significant '1'
+         * in the word. */
+        #if defined( __x86_64__ ) || defined( _M_X64 )
+
+            #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    \
+            do                                                                      \
+            {                                                                       \
+                DWORD ulTopPriority;                                                \
+                _BitScanReverse64( &ulTopPriority, ( uxReadyPriorities ) );         \
+                uxTopPriority = ulTopPriority;                                      \
+            } while( 0 )
+
+        #else /* #if defined( __x86_64__ ) || defined( _M_X64 ) */
+
+            #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    _BitScanReverse( ( DWORD * ) &( uxTopPriority ), ( uxReadyPriorities ) )
+
+        #endif /* #if defined( __x86_64__ ) || defined( _M_X64 ) */
+
     #endif /* __GNUC__ */
 
-#endif /* taskRECORD_READY_PRIORITY */
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 
 #ifndef __GNUC__
     __pragma( warning( disable:4211 ) ) /* Nonstandard extension used, as extern is only nonstandard to MSVC. */

From d63434493acd5f0943e34be763429ecb057432a0 Mon Sep 17 00:00:00 2001
From: Soren Ptak <ptaksoren@gmail.com>
Date: Mon, 29 Jan 2024 12:19:09 -0500
Subject: [PATCH 203/424] Add missing Task Notification IFDEF (#967)

Wrap the task notification check in vTaskGetInfo() in in a  #if ( configUSE_TASK_NOTIFICATIONS == 1 )
---
 tasks.c | 26 +++++++++++++++-----------
 1 file changed, 15 insertions(+), 11 deletions(-)

diff --git a/tasks.c b/tasks.c
index 9f6c5f879..b00d218bb 100644
--- a/tasks.c
+++ b/tasks.c
@@ -6212,21 +6212,25 @@ static void prvCheckTasksWaitingTermination( void )
                             }
                             else
                             {
-                                BaseType_t x;
-
-                                /* The task does not appear on the event list item of
-                                 * and of the RTOS objects, but could still be in the
-                                 * blocked state if it is waiting on its notification
-                                 * rather than waiting on an object.  If not, is
-                                 * suspended. */
-                                for( x = ( BaseType_t ) 0; x < ( BaseType_t ) configTASK_NOTIFICATION_ARRAY_ENTRIES; x++ )
+                                #if ( configUSE_TASK_NOTIFICATIONS == 1 )
                                 {
-                                    if( pxTCB->ucNotifyState[ x ] == taskWAITING_NOTIFICATION )
+                                    BaseType_t x;
+
+                                    /* The task does not appear on the event list item of
+                                     * and of the RTOS objects, but could still be in the
+                                     * blocked state if it is waiting on its notification
+                                     * rather than waiting on an object.  If not, is
+                                     * suspended. */
+                                    for( x = ( BaseType_t ) 0; x < ( BaseType_t ) configTASK_NOTIFICATION_ARRAY_ENTRIES; x++ )
                                     {
-                                        pxTaskStatus->eCurrentState = eBlocked;
-                                        break;
+                                        if( pxTCB->ucNotifyState[ x ] == taskWAITING_NOTIFICATION )
+                                        {
+                                            pxTaskStatus->eCurrentState = eBlocked;
+                                            break;
+                                        }
                                     }
                                 }
+                                #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
                             }
                         }
                         ( void ) xTaskResumeAll();

From 5a2237a1e26c23b40f45e0ad4f924b428fb6c094 Mon Sep 17 00:00:00 2001
From: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Date: Mon, 29 Jan 2024 23:59:18 +0530
Subject: [PATCH 204/424] Remove configTOTAL_MPU_REGIONS from M3 MPU port
 (#966)

The number of MPU regions is not configurable for Cortex-M3 port and
therefore, it is misleading to have configTOTAL_MPU_REGIONS in
portmacro.h.

It was added in PR #952.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 portable/GCC/ARM_CM3_MPU/portmacro.h | 9 ---------
 1 file changed, 9 deletions(-)

diff --git a/portable/GCC/ARM_CM3_MPU/portmacro.h b/portable/GCC/ARM_CM3_MPU/portmacro.h
index a6e2ae261..5983c7912 100644
--- a/portable/GCC/ARM_CM3_MPU/portmacro.h
+++ b/portable/GCC/ARM_CM3_MPU/portmacro.h
@@ -86,15 +86,6 @@ typedef unsigned long    UBaseType_t;
 #define portMPU_REGION_CACHEABLE_BUFFERABLE                      ( 0x07UL << 16UL )
 #define portMPU_REGION_EXECUTE_NEVER                             ( 0x01UL << 28UL )
 
-/* MPU settings that can be overriden in FreeRTOSConfig.h. */
-#ifndef configTOTAL_MPU_REGIONS
-    /* Define to 8 for backward compatibility. */
-    #define configTOTAL_MPU_REGIONS    ( 8UL )
-#elif( configTOTAL_MPU_REGIONS != 8UL )
-    /* The Cortex M3 only supports 8 MPU regions. For more information refer to:
-     * https://developer.arm.com/documentation/dui0552/a/cortex-m3-peripherals/optional-memory-protection-unit */
-    #error configTOTAL_MPU_REGIONS must be 8 for this port.
-#endif /* configTOTAL_MPU_REGIONS Check */
 #define portSTACK_REGION                                         ( 3UL )
 #define portGENERAL_PERIPHERALS_REGION                           ( 4UL )
 #define portUNPRIVILEGED_FLASH_REGION                            ( 5UL )

From 04cb022e4499cb55c37408b9a3a07e6d715f82a4 Mon Sep 17 00:00:00 2001
From: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Date: Tue, 30 Jan 2024 10:43:53 +0530
Subject: [PATCH 205/424] Add a check for configENABLE_MVE to M23, M33 ports
 (#968)

Add a check for configENABLE_MVE to M23, M33 ports

configENABLE_MVE is only applicable to Cortex-M55 and Cortex-M85 ports.
It must not be defined to 1 for other ARMv8_m ports.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 .../ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h    | 6 ++++++
 .../non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h       | 6 ++++++
 .../ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h    | 7 +++++++
 .../non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h       | 7 +++++++
 .../ARMv8M/non_secure/portable/GCC/ARM_CM35P/portmacro.h   | 7 +++++++
 .../ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h    | 6 ++++++
 .../non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h       | 6 ++++++
 .../ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h    | 7 +++++++
 .../non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h       | 7 +++++++
 .../ARMv8M/non_secure/portable/IAR/ARM_CM35P/portmacro.h   | 6 ++++++
 portable/GCC/ARM_CM23/non_secure/portmacro.h               | 6 ++++++
 portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h           | 6 ++++++
 portable/GCC/ARM_CM33/non_secure/portmacro.h               | 7 +++++++
 portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h           | 7 +++++++
 portable/GCC/ARM_CM35P/non_secure/portmacro.h              | 7 +++++++
 portable/GCC/ARM_CM35P_NTZ/non_secure/portmacro.h          | 7 +++++++
 portable/IAR/ARM_CM23/non_secure/portmacro.h               | 6 ++++++
 portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h           | 6 ++++++
 portable/IAR/ARM_CM33/non_secure/portmacro.h               | 7 +++++++
 portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h           | 7 +++++++
 portable/IAR/ARM_CM35P/non_secure/portmacro.h              | 6 ++++++
 portable/IAR/ARM_CM35P_NTZ/non_secure/portmacro.h          | 6 ++++++
 22 files changed, 143 insertions(+)

diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h
index 33d522488..d17f3eb28 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h
@@ -60,6 +60,12 @@
 #if ( configTOTAL_MPU_REGIONS == 16 )
     #error 16 MPU regions are not yet supported for this port.
 #endif
+
+#ifndef configENABLE_MVE
+    #define configENABLE_MVE    0
+#elif( configENABLE_MVE != 0 )
+    #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M23.
+#endif
 /*-----------------------------------------------------------*/
 
 /**
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h
index 33d522488..d17f3eb28 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h
@@ -60,6 +60,12 @@
 #if ( configTOTAL_MPU_REGIONS == 16 )
     #error 16 MPU regions are not yet supported for this port.
 #endif
+
+#ifndef configENABLE_MVE
+    #define configENABLE_MVE    0
+#elif( configENABLE_MVE != 0 )
+    #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M23.
+#endif
 /*-----------------------------------------------------------*/
 
 /**
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h
index 227327ac8..90448b6cc 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h
@@ -57,6 +57,13 @@
 #include "portmacrocommon.h"
 /*-----------------------------------------------------------*/
 
+#ifndef configENABLE_MVE
+    #define configENABLE_MVE    0
+#elif( configENABLE_MVE != 0 )
+    #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M33.
+#endif
+/*-----------------------------------------------------------*/
+
 /**
  * @brief Critical section management.
  */
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h
index 227327ac8..90448b6cc 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h
@@ -57,6 +57,13 @@
 #include "portmacrocommon.h"
 /*-----------------------------------------------------------*/
 
+#ifndef configENABLE_MVE
+    #define configENABLE_MVE    0
+#elif( configENABLE_MVE != 0 )
+    #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M33.
+#endif
+/*-----------------------------------------------------------*/
+
 /**
  * @brief Critical section management.
  */
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM35P/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM35P/portmacro.h
index 66fa2056d..11fc04273 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM35P/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM35P/portmacro.h
@@ -57,6 +57,13 @@
 #include "portmacrocommon.h"
 /*-----------------------------------------------------------*/
 
+#ifndef configENABLE_MVE
+    #define configENABLE_MVE    0
+#elif( configENABLE_MVE != 0 )
+    #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M35.
+#endif
+/*-----------------------------------------------------------*/
+
 /**
  * @brief Critical section management.
  */
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h
index e426f5b9a..56d7398f5 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h
@@ -60,6 +60,12 @@
 #if ( configTOTAL_MPU_REGIONS == 16 )
     #error 16 MPU regions are not yet supported for this port.
 #endif
+
+#ifndef configENABLE_MVE
+    #define configENABLE_MVE    0
+#elif( configENABLE_MVE != 0 )
+    #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M23.
+#endif
 /*-----------------------------------------------------------*/
 
 /**
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h
index e426f5b9a..56d7398f5 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h
@@ -60,6 +60,12 @@
 #if ( configTOTAL_MPU_REGIONS == 16 )
     #error 16 MPU regions are not yet supported for this port.
 #endif
+
+#ifndef configENABLE_MVE
+    #define configENABLE_MVE    0
+#elif( configENABLE_MVE != 0 )
+    #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M23.
+#endif
 /*-----------------------------------------------------------*/
 
 /**
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h
index a707fc658..890f3ea96 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h
@@ -62,6 +62,13 @@
 #include "portmacrocommon.h"
 /*-----------------------------------------------------------*/
 
+#ifndef configENABLE_MVE
+    #define configENABLE_MVE    0
+#elif( configENABLE_MVE != 0 )
+    #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M33.
+#endif
+/*-----------------------------------------------------------*/
+
 /**
  * @brief Critical section management.
  */
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h
index 64d39e3b9..59a44193f 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h
@@ -60,6 +60,13 @@
 #if ( configTOTAL_MPU_REGIONS == 16 )
     #error 16 MPU regions are not yet supported for this port.
 #endif
+
+#ifndef configENABLE_MVE
+    #define configENABLE_MVE    0
+#elif( configENABLE_MVE != 0 )
+    #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M33.
+#endif
+
 /*-----------------------------------------------------------*/
 
 /**
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM35P/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM35P/portmacro.h
index 82bfaeb79..468d14311 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM35P/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM35P/portmacro.h
@@ -60,6 +60,12 @@
 #if ( configTOTAL_MPU_REGIONS == 16 )
     #error 16 MPU regions are not yet supported for this port.
 #endif
+
+#ifndef configENABLE_MVE
+    #define configENABLE_MVE    0
+#elif( configENABLE_MVE != 0 )
+    #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M35.
+#endif
 /*-----------------------------------------------------------*/
 
 /**
diff --git a/portable/GCC/ARM_CM23/non_secure/portmacro.h b/portable/GCC/ARM_CM23/non_secure/portmacro.h
index 33d522488..d17f3eb28 100644
--- a/portable/GCC/ARM_CM23/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM23/non_secure/portmacro.h
@@ -60,6 +60,12 @@
 #if ( configTOTAL_MPU_REGIONS == 16 )
     #error 16 MPU regions are not yet supported for this port.
 #endif
+
+#ifndef configENABLE_MVE
+    #define configENABLE_MVE    0
+#elif( configENABLE_MVE != 0 )
+    #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M23.
+#endif
 /*-----------------------------------------------------------*/
 
 /**
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h b/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h
index 33d522488..d17f3eb28 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h
@@ -60,6 +60,12 @@
 #if ( configTOTAL_MPU_REGIONS == 16 )
     #error 16 MPU regions are not yet supported for this port.
 #endif
+
+#ifndef configENABLE_MVE
+    #define configENABLE_MVE    0
+#elif( configENABLE_MVE != 0 )
+    #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M23.
+#endif
 /*-----------------------------------------------------------*/
 
 /**
diff --git a/portable/GCC/ARM_CM33/non_secure/portmacro.h b/portable/GCC/ARM_CM33/non_secure/portmacro.h
index 227327ac8..90448b6cc 100644
--- a/portable/GCC/ARM_CM33/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM33/non_secure/portmacro.h
@@ -57,6 +57,13 @@
 #include "portmacrocommon.h"
 /*-----------------------------------------------------------*/
 
+#ifndef configENABLE_MVE
+    #define configENABLE_MVE    0
+#elif( configENABLE_MVE != 0 )
+    #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M33.
+#endif
+/*-----------------------------------------------------------*/
+
 /**
  * @brief Critical section management.
  */
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h b/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h
index 227327ac8..90448b6cc 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h
@@ -57,6 +57,13 @@
 #include "portmacrocommon.h"
 /*-----------------------------------------------------------*/
 
+#ifndef configENABLE_MVE
+    #define configENABLE_MVE    0
+#elif( configENABLE_MVE != 0 )
+    #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M33.
+#endif
+/*-----------------------------------------------------------*/
+
 /**
  * @brief Critical section management.
  */
diff --git a/portable/GCC/ARM_CM35P/non_secure/portmacro.h b/portable/GCC/ARM_CM35P/non_secure/portmacro.h
index 66fa2056d..11fc04273 100644
--- a/portable/GCC/ARM_CM35P/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM35P/non_secure/portmacro.h
@@ -57,6 +57,13 @@
 #include "portmacrocommon.h"
 /*-----------------------------------------------------------*/
 
+#ifndef configENABLE_MVE
+    #define configENABLE_MVE    0
+#elif( configENABLE_MVE != 0 )
+    #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M35.
+#endif
+/*-----------------------------------------------------------*/
+
 /**
  * @brief Critical section management.
  */
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacro.h b/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacro.h
index 66fa2056d..11fc04273 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacro.h
@@ -57,6 +57,13 @@
 #include "portmacrocommon.h"
 /*-----------------------------------------------------------*/
 
+#ifndef configENABLE_MVE
+    #define configENABLE_MVE    0
+#elif( configENABLE_MVE != 0 )
+    #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M35.
+#endif
+/*-----------------------------------------------------------*/
+
 /**
  * @brief Critical section management.
  */
diff --git a/portable/IAR/ARM_CM23/non_secure/portmacro.h b/portable/IAR/ARM_CM23/non_secure/portmacro.h
index e426f5b9a..56d7398f5 100644
--- a/portable/IAR/ARM_CM23/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM23/non_secure/portmacro.h
@@ -60,6 +60,12 @@
 #if ( configTOTAL_MPU_REGIONS == 16 )
     #error 16 MPU regions are not yet supported for this port.
 #endif
+
+#ifndef configENABLE_MVE
+    #define configENABLE_MVE    0
+#elif( configENABLE_MVE != 0 )
+    #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M23.
+#endif
 /*-----------------------------------------------------------*/
 
 /**
diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h b/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h
index e426f5b9a..56d7398f5 100644
--- a/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h
@@ -60,6 +60,12 @@
 #if ( configTOTAL_MPU_REGIONS == 16 )
     #error 16 MPU regions are not yet supported for this port.
 #endif
+
+#ifndef configENABLE_MVE
+    #define configENABLE_MVE    0
+#elif( configENABLE_MVE != 0 )
+    #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M23.
+#endif
 /*-----------------------------------------------------------*/
 
 /**
diff --git a/portable/IAR/ARM_CM33/non_secure/portmacro.h b/portable/IAR/ARM_CM33/non_secure/portmacro.h
index a707fc658..890f3ea96 100644
--- a/portable/IAR/ARM_CM33/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM33/non_secure/portmacro.h
@@ -62,6 +62,13 @@
 #include "portmacrocommon.h"
 /*-----------------------------------------------------------*/
 
+#ifndef configENABLE_MVE
+    #define configENABLE_MVE    0
+#elif( configENABLE_MVE != 0 )
+    #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M33.
+#endif
+/*-----------------------------------------------------------*/
+
 /**
  * @brief Critical section management.
  */
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h b/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h
index 64d39e3b9..59a44193f 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h
@@ -60,6 +60,13 @@
 #if ( configTOTAL_MPU_REGIONS == 16 )
     #error 16 MPU regions are not yet supported for this port.
 #endif
+
+#ifndef configENABLE_MVE
+    #define configENABLE_MVE    0
+#elif( configENABLE_MVE != 0 )
+    #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M33.
+#endif
+
 /*-----------------------------------------------------------*/
 
 /**
diff --git a/portable/IAR/ARM_CM35P/non_secure/portmacro.h b/portable/IAR/ARM_CM35P/non_secure/portmacro.h
index 82bfaeb79..468d14311 100644
--- a/portable/IAR/ARM_CM35P/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM35P/non_secure/portmacro.h
@@ -60,6 +60,12 @@
 #if ( configTOTAL_MPU_REGIONS == 16 )
     #error 16 MPU regions are not yet supported for this port.
 #endif
+
+#ifndef configENABLE_MVE
+    #define configENABLE_MVE    0
+#elif( configENABLE_MVE != 0 )
+    #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M35.
+#endif
 /*-----------------------------------------------------------*/
 
 /**
diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacro.h b/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacro.h
index 82bfaeb79..468d14311 100644
--- a/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacro.h
@@ -60,6 +60,12 @@
 #if ( configTOTAL_MPU_REGIONS == 16 )
     #error 16 MPU regions are not yet supported for this port.
 #endif
+
+#ifndef configENABLE_MVE
+    #define configENABLE_MVE    0
+#elif( configENABLE_MVE != 0 )
+    #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M35.
+#endif
 /*-----------------------------------------------------------*/
 
 /**

From 8622bd5f49f0b3e229b691556bc97fc927ba3dcb Mon Sep 17 00:00:00 2001
From: Phillip Stevens <phillip.stevens@gmail.com>
Date: Tue, 30 Jan 2024 16:42:20 +1100
Subject: [PATCH 206/424] Fix ThirdParty/GCC/ATmega formatting (#965)

Unnecessary white space was introduced in PR #768
which affected the formatting of assembly code. This PR
returns the correct formatting. No functional change.
---
 portable/ThirdParty/GCC/ATmega/port.c      | 40 +++++++++++-----------
 portable/ThirdParty/GCC/ATmega/portmacro.h | 22 ++++++------
 2 files changed, 31 insertions(+), 31 deletions(-)

diff --git a/portable/ThirdParty/GCC/ATmega/port.c b/portable/ThirdParty/GCC/ATmega/port.c
index fa71552b3..80308f2fa 100644
--- a/portable/ThirdParty/GCC/ATmega/port.c
+++ b/portable/ThirdParty/GCC/ATmega/port.c
@@ -100,11 +100,11 @@ extern volatile TCB_t * volatile pxCurrentTCB;
         {
             __asm__ __volatile__ (
                 "in __tmp_reg__,__SREG__"   "\n\t"
-                                            "cli"                       "\n\t"
-                                                                        "wdr"                       "\n\t"
-                                                                                                    "out %0, %1"                "\n\t"
-                                                                                                                                "out __SREG__,__tmp_reg__"  "\n\t"
-                                                                                                                                                            "out %0, %2"                "\n\t"
+                "cli"                       "\n\t"
+                "wdr"                       "\n\t"
+                "out %0, %1"                "\n\t"
+                "out __SREG__,__tmp_reg__"  "\n\t"
+                "out %0, %2"                "\n\t"
                 : /* no outputs */
                 : "I" ( _SFR_IO_ADDR( _WD_CONTROL_REG ) ),
                 "r" ( ( uint8_t ) ( _BV( _WD_CHANGE_BIT ) | _BV( WDE ) ) ),
@@ -117,11 +117,11 @@ extern volatile TCB_t * volatile pxCurrentTCB;
         {
             __asm__ __volatile__ (
                 "in __tmp_reg__,__SREG__"   "\n\t"
-                                            "cli"                       "\n\t"
-                                                                        "wdr"                       "\n\t"
-                                                                                                    "sts %0, %1"                "\n\t"
-                                                                                                                                "out __SREG__,__tmp_reg__"  "\n\t"
-                                                                                                                                                            "sts %0, %2"                "\n\t"
+                "cli"                       "\n\t"
+                "wdr"                       "\n\t"
+                "sts %0, %1"                "\n\t"
+                "out __SREG__,__tmp_reg__"  "\n\t"
+                "sts %0, %2"                "\n\t"
                 : /* no outputs */
                 : "n" ( _SFR_MEM_ADDR( _WD_CONTROL_REG ) ),
                 "r" ( ( uint8_t ) ( _BV( _WD_CHANGE_BIT ) | _BV( WDE ) ) ),
@@ -167,11 +167,11 @@ extern volatile TCB_t * volatile pxCurrentTCB;
         {
             __asm__ __volatile__ (
                 "in __tmp_reg__,__SREG__"   "\n\t"
-                                            "cli"                       "\n\t"
-                                                                        "wdr"                       "\n\t"
-                                                                                                    "out %0, %1"                "\n\t"
-                                                                                                                                "out __SREG__,__tmp_reg__"  "\n\t"
-                                                                                                                                                            "out %0, %2"                "\n\t"
+                "cli"                       "\n\t"
+                "wdr"                       "\n\t"
+                "out %0, %1"                "\n\t"
+                "out __SREG__,__tmp_reg__"  "\n\t"
+                "out %0, %2"                "\n\t"
                 : /* no outputs */
                 : "I" ( _SFR_IO_ADDR( _WD_CONTROL_REG ) ),
                 "r" ( ( uint8_t ) ( _BV( _WD_CHANGE_BIT ) | _BV( WDE ) ) ),
@@ -184,11 +184,11 @@ extern volatile TCB_t * volatile pxCurrentTCB;
         {
             __asm__ __volatile__ (
                 "in __tmp_reg__,__SREG__"   "\n\t"
-                                            "cli"                       "\n\t"
-                                                                        "wdr"                       "\n\t"
-                                                                                                    "sts %0, %1"                "\n\t"
-                                                                                                                                "out __SREG__,__tmp_reg__"  "\n\t"
-                                                                                                                                                            "sts %0, %2"                "\n\t"
+                "cli"                       "\n\t"
+                "wdr"                       "\n\t"
+                "sts %0, %1"                "\n\t"
+                "out __SREG__,__tmp_reg__"  "\n\t"
+                "sts %0, %2"                "\n\t"
                 : /* no outputs */
                 : "n" ( _SFR_MEM_ADDR( _WD_CONTROL_REG ) ),
                 "r" ( ( uint8_t ) ( _BV( _WD_CHANGE_BIT ) | _BV( WDE ) ) ),
diff --git a/portable/ThirdParty/GCC/ATmega/portmacro.h b/portable/ThirdParty/GCC/ATmega/portmacro.h
index 7f8205497..9d34c0776 100644
--- a/portable/ThirdParty/GCC/ATmega/portmacro.h
+++ b/portable/ThirdParty/GCC/ATmega/portmacro.h
@@ -73,20 +73,20 @@ typedef uint8_t        UBaseType_t;
 
 /* Critical section management. */
 
-#define portENTER_CRITICAL()                                                                                         \
-    __asm__ __volatile__ (                                                                                           \
-        "in __tmp_reg__, __SREG__"        "\n\t"                                                                     \
-                                          "cli"                             "\n\t"                                   \
-                                                                            "push __tmp_reg__"                "\n\t" \
-        ::: "memory"                                                                                                 \
+#define portENTER_CRITICAL()                        \
+    __asm__ __volatile__ (                          \
+        "in __tmp_reg__, __SREG__"        "\n\t"    \
+        "cli"                             "\n\t"    \
+        "push __tmp_reg__"                "\n\t"    \
+        ::: "memory"                                \
         )
 
 
-#define portEXIT_CRITICAL()                                                        \
-    __asm__ __volatile__ (                                                         \
-        "pop __tmp_reg__"                 "\n\t"                                   \
-                                          "out __SREG__, __tmp_reg__"       "\n\t" \
-        ::: "memory"                                                               \
+#define portEXIT_CRITICAL()                         \
+    __asm__ __volatile__ (                          \
+        "pop __tmp_reg__"                 "\n\t"    \
+        "out __SREG__, __tmp_reg__"       "\n\t"    \
+        ::: "memory"                                \
         )
 
 

From c565fd45c19c7c5b0d7a6cfa288039051a017b53 Mon Sep 17 00:00:00 2001
From: barnatahmed <101841699+barnatahmed@users.noreply.github.com>
Date: Tue, 30 Jan 2024 20:44:27 +0100
Subject: [PATCH 207/424] Cmake: Create a single static library including port

Modify portable/CMakeLists.txt to create only one static library containing both the common kernel code and kernel port.

Change the freertos_kernel_port target from a STATIC library to an OBJECT library and introduce a new freertos_kernel_port_headers  INTERFACE library target.

---------

Co-authored-by: ABARNAT <ahmed.barnat@actia-engineering.tn>
Co-authored-by: Soren Ptak <ptaksoren@gmail.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
---
 CMakeLists.txt          | 12 ++++++++----
 portable/CMakeLists.txt |  6 ++++--
 2 files changed, 12 insertions(+), 6 deletions(-)

diff --git a/CMakeLists.txt b/CMakeLists.txt
index 5323ec19b..07eeec471 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -217,16 +217,17 @@ elseif((FREERTOS_PORT STREQUAL "A_CUSTOM_PORT") AND (NOT TARGET freertos_kernel_
     "    port.c\n"
     "    portmacro.h\n"
     " Where FreeRTOSCustomPort/CMakeLists.txt is a modified version of:\n"
-    "   add_library(freertos_kernel_port STATIC)\n"
+    "   add_library(freertos_kernel_port OBJECT)\n"
     "   target_sources(freertos_kernel_port\n"
     "     PRIVATE\n"
     "       port.c\n"
     "       portmacro.h)\n"
-    "   target_include_directories(freertos_kernel_port\n"
-    "     PUBLIC\n"
+    "   add_library(freertos_kernel_port_headers INTERFACE)\n"
+    "     target_include_directories(freertos_kernel_port_headers INTERFACE \n"
     "      .)\n"
     "   target_link_libraries(freertos_kernel_port\n"
     "     PRIVATE\n"
+    "       freertos_kernel_port_headers\n"
     "       freertos_kernel_include)")
 endif()
 
@@ -257,8 +258,11 @@ endif()
 
 target_link_libraries(freertos_kernel
     PUBLIC
-        freertos_kernel_port
         freertos_kernel_include
+        freertos_kernel_port_headers
+    PRIVATE
+        freertos_kernel_port
+
 )
 
 ########################################################################
diff --git a/portable/CMakeLists.txt b/portable/CMakeLists.txt
index 9df221d21..98dcf8ed3 100644
--- a/portable/CMakeLists.txt
+++ b/portable/CMakeLists.txt
@@ -15,7 +15,7 @@ endif()
 
 # FreeRTOS internal cmake file. Do not use it in user top-level project
 
-add_library(freertos_kernel_port STATIC
+add_library(freertos_kernel_port OBJECT
     # TEMPLATE Port
     $<$<STREQUAL:${FREERTOS_PORT},TEMPLATE>:
         template/port.c>
@@ -755,8 +755,9 @@ if( FREERTOS_PORT MATCHES "GCC_ARM_CM(3|4)_MPU" OR
         Common/mpu_wrappers_v2.c
     )
 endif()
+add_library(freertos_kernel_port_headers INTERFACE)
 
-target_include_directories(freertos_kernel_port PUBLIC
+target_include_directories(freertos_kernel_port_headers INTERFACE
     # TEMPLATE Port
     $<$<STREQUAL:${FREERTOS_PORT},TEMPLATE>:${CMAKE_CURRENT_LIST_DIR}/template>
 
@@ -1094,6 +1095,7 @@ target_link_libraries(freertos_kernel_port
     PUBLIC
         $<$<STREQUAL:${FREERTOS_PORT},GCC_RP2040>:pico_base_headers>
         $<$<STREQUAL:${FREERTOS_PORT},GCC_XTENSA_ESP32>:idf::esp32>
+        freertos_kernel_port_headers
     PRIVATE
         freertos_kernel_include
         $<$<STREQUAL:${FREERTOS_PORT},GCC_POSIX>:Threads::Threads>

From ba1e2dad3cc6fcb4209e33093efba83d189aa836 Mon Sep 17 00:00:00 2001
From: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Date: Wed, 31 Jan 2024 12:25:56 +0530
Subject: [PATCH 208/424] Update ARMv8-M config definitions in template file
 (#970)

* Update ARMV8-M config definitions in template file

---------

Co-authored-by: GitHub Action <action@github.com>
---
 .../template_configuration/FreeRTOSConfig.h   | 32 +++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/examples/template_configuration/FreeRTOSConfig.h b/examples/template_configuration/FreeRTOSConfig.h
index a672600ff..14aa3b24b 100644
--- a/examples/template_configuration/FreeRTOSConfig.h
+++ b/examples/template_configuration/FreeRTOSConfig.h
@@ -531,6 +531,38 @@
  * setting configKERNEL_PROVIDED_STATIC_MEMORY to 0 or leaving it undefined. */
 #define configKERNEL_PROVIDED_STATIC_MEMORY    1
 
+/******************************************************************************/
+/* ARMv8-M port Specific Configuration definitions. ***************************/
+/******************************************************************************/
+
+/* Set configENABLE_TRUSTZONE to 1 when running FreeRTOS on the non-secure side
+ * to enable the TrustZone support in FreeRTOS ARMv8-M ports which allows the
+ * non-secure FreeRTOS tasks to call the (non-secure callable) functions
+ * exported from secure side. */
+#define configENABLE_TRUSTZONE            1
+
+/* If the application writer does not want to use TrustZone, but the hardware does
+ * not support disabling TrustZone then the entire application (including the FreeRTOS
+ * scheduler) can run on the secure side without ever branching to the non-secure side.
+ * To do that, in addition to setting configENABLE_TRUSTZONE to 0, also set
+ * configRUN_FREERTOS_SECURE_ONLY to 1. */
+#define configRUN_FREERTOS_SECURE_ONLY    1
+
+/* Set configENABLE_MPU to 1 to enable the Memory Protection Unit (MPU), or 0
+ * to leave the Memory Protection Unit disabled. */
+#define configENABLE_MPU                  1
+
+/* Set configENABLE_FPU to 1 to enable the Floating Point Unit (FPU), or 0
+ * to leave the Floating Point Unit disabled. */
+#define configENABLE_FPU                  1
+
+/* Set configENABLE_MVE to 1 to enable the M-Profile Vector Extension (MVE) support,
+ * or 0 to leave the MVE support disabled. This option is only applicable to Cortex-M55
+ * and Cortex-M85 ports as M-Profile Vector Extension (MVE) is available only on
+ * these architectures. configENABLE_MVE must be left undefined, or defined to 0
+ * for the Cortex-M23,Cortex-M33 and Cortex-M35P ports. */
+#define configENABLE_MVE                  1
+
 /******************************************************************************/
 /* Definitions that include or exclude functionality. *************************/
 /******************************************************************************/

From 1de764ba879a36fe3e155dece2d11b1116b64360 Mon Sep 17 00:00:00 2001
From: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Date: Thu, 1 Feb 2024 11:12:08 +0800
Subject: [PATCH 209/424] Delete kernel created task in vTaskEndScheduler
 (#962)

* Update vTaskDelete() to delete a task directly when scheduler is stopped instead of putting it on the xTasksWaitingTermination list.
* Delete the idle tasks and timer task in vTaskEndScheduler().
* Reclaim resources for all the tasks on the xTasksWaitingTermination list in vTaskEndScheduler().
* Update POSIX to no longer delete FreeRTOS tasks in the port.

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 portable/ThirdParty/GCC/Posix/port.c | 39 +++++-----------------------
 tasks.c                              | 30 ++++++++++++++++++++-
 2 files changed, 35 insertions(+), 34 deletions(-)

diff --git a/portable/ThirdParty/GCC/Posix/port.c b/portable/ThirdParty/GCC/Posix/port.c
index 65ba54c7b..fdb556d04 100644
--- a/portable/ThirdParty/GCC/Posix/port.c
+++ b/portable/ThirdParty/GCC/Posix/port.c
@@ -74,7 +74,6 @@
 /* Scheduler includes. */
 #include "FreeRTOS.h"
 #include "task.h"
-#include "list.h"
 #include "timers.h"
 #include "utils/wait_for_event.h"
 /*-----------------------------------------------------------*/
@@ -88,7 +87,6 @@ typedef struct THREAD
     void * pvParams;
     BaseType_t xDying;
     struct event * ev;
-    ListItem_t xThreadListItem;
 } Thread_t;
 
 /*
@@ -113,7 +111,6 @@ static BaseType_t xSchedulerEnd = pdFALSE;
 static pthread_t hTimerTickThread;
 static bool xTimerTickThreadShouldRun;
 static uint64_t prvStartTimeNs;
-static List_t xThreadList;
 /*-----------------------------------------------------------*/
 
 static void prvSetupSignalsAndSchedulerPolicy( void );
@@ -197,14 +194,8 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
 
     thread->ev = event_create();
 
-    vListInitialiseItem( &thread->xThreadListItem );
-    listSET_LIST_ITEM_OWNER( &thread->xThreadListItem, thread );
-
     vPortEnterCritical();
 
-    /* Add the new thread in xThreadList. */
-    vListInsertEnd( &xThreadList, &thread->xThreadListItem );
-
     iRet = pthread_create( &thread->pthread, &xThreadAttributes,
                            prvWaitForStart, thread );
 
@@ -235,8 +226,6 @@ BaseType_t xPortStartScheduler( void )
 {
     int iSignal;
     sigset_t xSignals;
-    ListItem_t * pxIterator;
-    const ListItem_t * pxEndMarker;
 
     hMainThread = pthread_self();
     prvPortSetCurrentThreadName("Scheduler");
@@ -263,19 +252,6 @@ BaseType_t xPortStartScheduler( void )
         sigwait( &xSignals, &iSignal );
     }
 
-    /* Cancel all the running thread. */
-    pxEndMarker = listGET_END_MARKER( &xThreadList );
-
-    for( pxIterator = listGET_HEAD_ENTRY( &xThreadList ); pxIterator != pxEndMarker; pxIterator = listGET_NEXT( pxIterator ) )
-    {
-        Thread_t * pxThread = ( Thread_t * ) listGET_LIST_ITEM_OWNER( pxIterator );
-
-        pthread_cancel( pxThread->pthread );
-        event_signal( pxThread->ev );
-        pthread_join( pxThread->pthread, NULL );
-        event_delete( pxThread->ev );
-    }
-
     /*
      * clear out the variable that is used to end the scheduler, otherwise
      * subsequent scheduler restarts will end immediately.
@@ -300,6 +276,8 @@ BaseType_t xPortStartScheduler( void )
 
 void vPortEndScheduler( void )
 {
+    Thread_t * pxCurrentThread;
+
     /* Stop the timer tick thread. */
     xTimerTickThreadShouldRun = false;
     pthread_join( hTimerTickThread, NULL );
@@ -308,7 +286,10 @@ void vPortEndScheduler( void )
     xSchedulerEnd = pdTRUE;
     ( void ) pthread_kill( hMainThread, SIG_RESUME );
 
-    pthread_exit( NULL );
+    /* Waiting to be deleted here. */
+    pxCurrentThread = prvGetThreadFromTask( xTaskGetCurrentTaskHandle() );
+    event_wait( pxCurrentThread->ev );
+    pthread_testcancel();
 }
 /*-----------------------------------------------------------*/
 
@@ -491,11 +472,6 @@ void vPortCancelThread( void * pxTaskToDelete )
 {
     Thread_t * pxThreadToCancel = prvGetThreadFromTask( pxTaskToDelete );
 
-    /* Remove the thread from xThreadList. */
-    vPortEnterCritical();
-    uxListRemove( &pxThreadToCancel->xThreadListItem );
-    vPortExitCritical();
-
     /*
      * The thread has already been suspended so it can be safely cancelled.
      */
@@ -600,9 +576,6 @@ static void prvSetupSignalsAndSchedulerPolicy( void )
 
     hMainThread = pthread_self();
 
-    /* Setup thread list to record all the task which are not deleted. */
-    vListInitialise( &xThreadList );
-
     /* Initialise common signal masks. */
     sigfillset( &xAllSignals );
 
diff --git a/tasks.c b/tasks.c
index b00d218bb..f07097eb0 100644
--- a/tasks.c
+++ b/tasks.c
@@ -2229,7 +2229,7 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
             /* If the task is running (or yielding), we must add it to the
              * termination list so that an idle task can delete it when it is
              * no longer running. */
-            if( taskTASK_IS_RUNNING_OR_SCHEDULED_TO_YIELD( pxTCB ) != pdFALSE )
+            if( ( xSchedulerRunning != pdFALSE ) && ( taskTASK_IS_RUNNING_OR_SCHEDULED_TO_YIELD( pxTCB ) != pdFALSE ) )
             {
                 /* A running task or a task which is scheduled to yield is being
                  * deleted. This cannot complete when the task is still running
@@ -3740,11 +3740,39 @@ void vTaskEndScheduler( void )
 {
     traceENTER_vTaskEndScheduler();
 
+    #if ( INCLUDE_vTaskDelete == 1 )
+    {
+        BaseType_t xCoreID;
+
+        #if ( configUSE_TIMERS == 1 )
+        {
+            /* Delete the timer task created by the kernel. */
+            vTaskDelete( xTimerGetTimerDaemonTaskHandle() );
+        }
+        #endif /* #if ( configUSE_TIMERS == 1 ) */
+
+        /* Delete Idle tasks created by the kernel.*/
+        for( xCoreID = 0; xCoreID < ( BaseType_t ) configNUMBER_OF_CORES; xCoreID++ )
+        {
+            vTaskDelete( xIdleTaskHandles[ xCoreID ] );
+        }
+
+        /* Idle task is responsible for reclaiming the resources of the tasks in
+         * xTasksWaitingTermination list. Since the idle task is now deleted and
+         * no longer going to run, we need to reclaim resources of all the tasks
+         * in the xTasksWaitingTermination list. */
+        prvCheckTasksWaitingTermination();
+    }
+    #endif /* #if ( INCLUDE_vTaskDelete == 1 ) */
+
     /* Stop the scheduler interrupts and call the portable scheduler end
      * routine so the original ISRs can be restored if necessary.  The port
      * layer must ensure interrupts enable  bit is left in the correct state. */
     portDISABLE_INTERRUPTS();
     xSchedulerRunning = pdFALSE;
+
+    /* This function must be called from a task and the application is
+     * responsible for deleting that task after the scheduler is stopped. */
     vPortEndScheduler();
 
     traceRETURN_vTaskEndScheduler();

From edd35e8f6e9835e8eb9e1ce26636a2be63595027 Mon Sep 17 00:00:00 2001
From: bradleysmith23 <74752142+bradleysmith23@users.noreply.github.com>
Date: Wed, 31 Jan 2024 23:06:56 -0800
Subject: [PATCH 210/424] Fix MISRA Rule 10.1 violations (#976)

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
---
 portable/Common/mpu_wrappers_v2.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/portable/Common/mpu_wrappers_v2.c b/portable/Common/mpu_wrappers_v2.c
index e257b25c2..3e25757e2 100644
--- a/portable/Common/mpu_wrappers_v2.c
+++ b/portable/Common/mpu_wrappers_v2.c
@@ -263,7 +263,7 @@
                 if( xKernelObjectPool[ i ].xInternalObjectHandle == NULL )
                 {
                     /* Mark this index as not free. */
-                    xKernelObjectPool[ i ].xInternalObjectHandle = ( OpaqueObjectHandle_t ) ( ~0 );
+                    xKernelObjectPool[ i ].xInternalObjectHandle = ( OpaqueObjectHandle_t ) ( ~0U );
                     lFreeIndex = i;
                     break;
                 }

From cd8c6c1f225a8298c97db7837c7c780c1c1c2d23 Mon Sep 17 00:00:00 2001
From: bradleysmith23 <74752142+bradleysmith23@users.noreply.github.com>
Date: Thu, 1 Feb 2024 01:01:53 -0800
Subject: [PATCH 211/424] Fix MISRA C 2012 Rule 9.3 violations (#973)

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
---
 portable/Common/mpu_wrappers_v2.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/portable/Common/mpu_wrappers_v2.c b/portable/Common/mpu_wrappers_v2.c
index 3e25757e2..4e296430f 100644
--- a/portable/Common/mpu_wrappers_v2.c
+++ b/portable/Common/mpu_wrappers_v2.c
@@ -245,7 +245,7 @@
 /**
  * @brief Kernel object pool.
  */
-    PRIVILEGED_DATA static KernelObject_t xKernelObjectPool[ configPROTECTED_KERNEL_OBJECT_POOL_SIZE ] = { NULL };
+    PRIVILEGED_DATA static KernelObject_t xKernelObjectPool[ configPROTECTED_KERNEL_OBJECT_POOL_SIZE ] = { 0 };
 /*-----------------------------------------------------------*/
 
     static int32_t MPU_GetFreeIndexInKernelObjectPool( void ) /* PRIVILEGED_FUNCTION */

From d94db2d11d4013b700fb8ee7d0e1a1910505cc12 Mon Sep 17 00:00:00 2001
From: bradleysmith23 <74752142+bradleysmith23@users.noreply.github.com>
Date: Thu, 1 Feb 2024 01:28:24 -0800
Subject: [PATCH 212/424] Fix MISRA C 2012 Rule 10.3 Violations (#974)

* Resolve violations for MISRA Rule 10.3-b2

* Formatting fix

---------

Co-authored-by: bjbsmith <bjbsmith@uafeb6a6bcdce55.ant.amazon.com>
Co-authored-by: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
---
 portable/Common/mpu_wrappers_v2.c |  2 +-
 queue.c                           |  8 ++++----
 tasks.c                           | 14 +++++++-------
 3 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/portable/Common/mpu_wrappers_v2.c b/portable/Common/mpu_wrappers_v2.c
index 4e296430f..39315a2d1 100644
--- a/portable/Common/mpu_wrappers_v2.c
+++ b/portable/Common/mpu_wrappers_v2.c
@@ -2964,7 +2964,7 @@
         QueueHandle_t xInternalQueueHandle = NULL;
         BaseType_t xReturn = pdFAIL;
 
-        lIndex = ( uint32_t ) xQueue;
+        lIndex = ( int32_t ) xQueue;
 
         if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
         {
diff --git a/queue.c b/queue.c
index 18618202c..daf8d2e9d 100644
--- a/queue.c
+++ b/queue.c
@@ -1190,7 +1190,7 @@ BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue,
      * read, instead return a flag to say whether a context switch is required or
      * not (i.e. has a task with a higher priority than us been woken by this
      * post). */
-    uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
+    uxSavedInterruptStatus = ( UBaseType_t ) taskENTER_CRITICAL_FROM_ISR();
     {
         if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
         {
@@ -1365,7 +1365,7 @@ BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue,
      * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
     portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
 
-    uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
+    uxSavedInterruptStatus = ( UBaseType_t ) taskENTER_CRITICAL_FROM_ISR();
     {
         const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
 
@@ -2055,7 +2055,7 @@ BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue,
      * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
     portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
 
-    uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
+    uxSavedInterruptStatus = ( UBaseType_t ) taskENTER_CRITICAL_FROM_ISR();
     {
         const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
 
@@ -2153,7 +2153,7 @@ BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue,
      * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
     portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
 
-    uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
+    uxSavedInterruptStatus = ( UBaseType_t ) taskENTER_CRITICAL_FROM_ISR();
     {
         /* Cannot block in an ISR, so check there is data available. */
         if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
diff --git a/tasks.c b/tasks.c
index f07097eb0..38a80e2de 100644
--- a/tasks.c
+++ b/tasks.c
@@ -2657,7 +2657,7 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
          * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
         portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
 
-        uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
+        uxSavedInterruptStatus = ( UBaseType_t ) taskENTER_CRITICAL_FROM_ISR();
         {
             /* If null is passed in here then it is the priority of the calling
              * task that is being queried. */
@@ -2728,7 +2728,7 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
          * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
         portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
 
-        uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
+        uxSavedInterruptStatus = ( UBaseType_t ) taskENTER_CRITICAL_FROM_ISR();
         {
             /* If null is passed in here then it is the base priority of the calling
              * task that is being queried. */
@@ -4657,7 +4657,7 @@ BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp )
                         /* This lets the task know it was forcibly removed from the
                          * blocked state so it should not re-evaluate its block time and
                          * then block again. */
-                        pxTCB->ucDelayAborted = pdTRUE;
+                        pxTCB->ucDelayAborted = ( uint8_t ) pdTRUE;
                     }
                     else
                     {
@@ -5598,7 +5598,7 @@ BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
             {
                 /* The delay was aborted, which is not the same as a time out,
                  * but has the same result. */
-                pxCurrentTCB->ucDelayAborted = pdFALSE;
+                pxCurrentTCB->ucDelayAborted = ( uint8_t ) pdFALSE;
                 xReturn = pdTRUE;
             }
             else
@@ -8064,7 +8064,7 @@ TickType_t uxTaskResetEventItemValue( void )
 
         pxTCB = xTaskToNotify;
 
-        uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
+        uxSavedInterruptStatus = ( UBaseType_t ) taskENTER_CRITICAL_FROM_ISR();
         {
             if( pulPreviousNotificationValue != NULL )
             {
@@ -8223,7 +8223,7 @@ TickType_t uxTaskResetEventItemValue( void )
 
         pxTCB = xTaskToNotify;
 
-        uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
+        uxSavedInterruptStatus = ( UBaseType_t ) taskENTER_CRITICAL_FROM_ISR();
         {
             ucOriginalNotifyState = pxTCB->ucNotifyState[ uxIndexToNotify ];
             pxTCB->ucNotifyState[ uxIndexToNotify ] = taskNOTIFICATION_RECEIVED;
@@ -8497,7 +8497,7 @@ static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait,
         /* About to enter a delayed list, so ensure the ucDelayAborted flag is
          * reset to pdFALSE so it can be detected as having been set to pdTRUE
          * when the task leaves the Blocked state. */
-        pxCurrentTCB->ucDelayAborted = pdFALSE;
+        pxCurrentTCB->ucDelayAborted = ( uint8_t ) pdFALSE;
     }
     #endif
 

From b4da9e301ff0d8f44ae74531e5c4e3407d932ecc Mon Sep 17 00:00:00 2001
From: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Date: Thu, 1 Feb 2024 17:38:24 +0530
Subject: [PATCH 213/424] Fix MISRA directive 4.7 warning (#977)

---
 portable/Common/mpu_wrappers_v2.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/portable/Common/mpu_wrappers_v2.c b/portable/Common/mpu_wrappers_v2.c
index 39315a2d1..cf2dcfbd9 100644
--- a/portable/Common/mpu_wrappers_v2.c
+++ b/portable/Common/mpu_wrappers_v2.c
@@ -269,7 +269,7 @@
                 }
             }
         }
-        xTaskResumeAll();
+        ( void ) xTaskResumeAll();
 
         return lFreeIndex;
     }

From 1189198a5e16ad7eaaf81eb8336e2fb268891596 Mon Sep 17 00:00:00 2001
From: bradleysmith23 <74752142+bradleysmith23@users.noreply.github.com>
Date: Thu, 1 Feb 2024 11:57:22 -0800
Subject: [PATCH 214/424] Fix MISRA C 2012 Rule 20.7 Violations (#971)

* Initial set of SA fixes

* Revert function parameter name changes

* Reverted parameter name for Static version of function by mistake

* Update mpu_wrappers_v2.c to only include 20.7 fixes

* Update queue.c to remove non-20.7 fixes

* Update tasks.c to remove non-20.7 fixes

---------

Co-authored-by: bjbsmith <bjbsmith@uafeb6a6bcdce55.ant.amazon.com>
Co-authored-by: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
---
 include/task.h                    |  4 ++--
 portable/Common/mpu_wrappers_v2.c | 38 +++++++++++++++----------------
 2 files changed, 21 insertions(+), 21 deletions(-)

diff --git a/include/task.h b/include/task.h
index 7856b89d2..de12f429d 100644
--- a/include/task.h
+++ b/include/task.h
@@ -2289,7 +2289,7 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION;
  * \defgroup vTaskList vTaskList
  * \ingroup TaskUtils
  */
-#define vTaskList( pcWriteBuffer )    vTaskListTasks( pcWriteBuffer, configSTATS_BUFFER_MAX_LENGTH )
+#define vTaskList( pcWriteBuffer )    vTaskListTasks( ( pcWriteBuffer ), configSTATS_BUFFER_MAX_LENGTH )
 
 /**
  * task. h
@@ -2412,7 +2412,7 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION;
  * \defgroup vTaskGetRunTimeStats vTaskGetRunTimeStats
  * \ingroup TaskUtils
  */
-#define vTaskGetRunTimeStats( pcWriteBuffer )    vTaskGetRunTimeStatistics( pcWriteBuffer, configSTATS_BUFFER_MAX_LENGTH )
+#define vTaskGetRunTimeStats( pcWriteBuffer )    vTaskGetRunTimeStatistics( ( pcWriteBuffer ), configSTATS_BUFFER_MAX_LENGTH )
 
 /**
  * task. h
diff --git a/portable/Common/mpu_wrappers_v2.c b/portable/Common/mpu_wrappers_v2.c
index cf2dcfbd9..4f876ab99 100644
--- a/portable/Common/mpu_wrappers_v2.c
+++ b/portable/Common/mpu_wrappers_v2.c
@@ -197,46 +197,46 @@
 /*
  * Wrappers to keep all the casting in one place.
  */
-    #define MPU_StoreQueueHandleAtIndex( lIndex, xHandle )                 MPU_StoreHandleAndDataAtIndex( lIndex, ( OpaqueObjectHandle_t ) xHandle, NULL, KERNEL_OBJECT_TYPE_QUEUE )
-    #define MPU_GetQueueHandleAtIndex( lIndex )                            ( QueueHandle_t ) MPU_GetHandleAtIndex( lIndex, KERNEL_OBJECT_TYPE_QUEUE )
+    #define MPU_StoreQueueHandleAtIndex( lIndex, xHandle )                 MPU_StoreHandleAndDataAtIndex( ( lIndex ), ( OpaqueObjectHandle_t ) ( xHandle ), NULL, KERNEL_OBJECT_TYPE_QUEUE )
+    #define MPU_GetQueueHandleAtIndex( lIndex )                            ( QueueHandle_t ) MPU_GetHandleAtIndex( ( lIndex ), KERNEL_OBJECT_TYPE_QUEUE )
 
     #if ( configUSE_QUEUE_SETS == 1 )
-        #define MPU_StoreQueueSetHandleAtIndex( lIndex, xHandle )          MPU_StoreHandleAndDataAtIndex( lIndex, ( OpaqueObjectHandle_t ) xHandle, NULL, KERNEL_OBJECT_TYPE_QUEUE )
-        #define MPU_GetQueueSetHandleAtIndex( lIndex )                     ( QueueSetHandle_t ) MPU_GetHandleAtIndex( lIndex, KERNEL_OBJECT_TYPE_QUEUE )
-        #define MPU_StoreQueueSetMemberHandleAtIndex( lIndex, xHandle )    MPU_StoreHandleAndDataAtIndex( lIndex, ( OpaqueObjectHandle_t ) xHandle, NULL, KERNEL_OBJECT_TYPE_QUEUE )
-        #define MPU_GetQueueSetMemberHandleAtIndex( lIndex )               ( QueueSetMemberHandle_t ) MPU_GetHandleAtIndex( lIndex, KERNEL_OBJECT_TYPE_QUEUE )
-        #define MPU_GetIndexForQueueSetMemberHandle( xHandle )             MPU_GetIndexForHandle( ( OpaqueObjectHandle_t ) xHandle, KERNEL_OBJECT_TYPE_QUEUE )
+        #define MPU_StoreQueueSetHandleAtIndex( lIndex, xHandle )          MPU_StoreHandleAndDataAtIndex( ( lIndex ), ( OpaqueObjectHandle_t ) ( xHandle ), NULL, KERNEL_OBJECT_TYPE_QUEUE )
+        #define MPU_GetQueueSetHandleAtIndex( lIndex )                     ( QueueSetHandle_t ) MPU_GetHandleAtIndex( ( lIndex ), KERNEL_OBJECT_TYPE_QUEUE )
+        #define MPU_StoreQueueSetMemberHandleAtIndex( lIndex, xHandle )    MPU_StoreHandleAndDataAtIndex( ( lIndex ), ( OpaqueObjectHandle_t ) ( xHandle ), NULL, KERNEL_OBJECT_TYPE_QUEUE )
+        #define MPU_GetQueueSetMemberHandleAtIndex( lIndex )               ( QueueSetMemberHandle_t ) MPU_GetHandleAtIndex( ( lIndex ), KERNEL_OBJECT_TYPE_QUEUE )
+        #define MPU_GetIndexForQueueSetMemberHandle( xHandle )             MPU_GetIndexForHandle( ( OpaqueObjectHandle_t ) ( xHandle ), KERNEL_OBJECT_TYPE_QUEUE )
     #endif
 
 /*
  * Wrappers to keep all the casting in one place for Task APIs.
  */
-    #define MPU_StoreTaskHandleAtIndex( lIndex, xHandle )            MPU_StoreHandleAndDataAtIndex( lIndex, ( OpaqueObjectHandle_t ) xHandle, NULL, KERNEL_OBJECT_TYPE_TASK )
-    #define MPU_GetTaskHandleAtIndex( lIndex )                       ( TaskHandle_t ) MPU_GetHandleAtIndex( lIndex, KERNEL_OBJECT_TYPE_TASK )
-    #define MPU_GetIndexForTaskHandle( xHandle )                     MPU_GetIndexForHandle( ( OpaqueObjectHandle_t ) xHandle, KERNEL_OBJECT_TYPE_TASK )
+    #define MPU_StoreTaskHandleAtIndex( lIndex, xHandle )            MPU_StoreHandleAndDataAtIndex( ( lIndex ), ( OpaqueObjectHandle_t ) ( xHandle ), NULL, KERNEL_OBJECT_TYPE_TASK )
+    #define MPU_GetTaskHandleAtIndex( lIndex )                       ( TaskHandle_t ) MPU_GetHandleAtIndex( ( lIndex ), KERNEL_OBJECT_TYPE_TASK )
+    #define MPU_GetIndexForTaskHandle( xHandle )                     MPU_GetIndexForHandle( ( OpaqueObjectHandle_t ) ( xHandle ), KERNEL_OBJECT_TYPE_TASK )
 
 /*
  * Wrappers to keep all the casting in one place for Event Group APIs.
  */
-    #define MPU_StoreEventGroupHandleAtIndex( lIndex, xHandle )      MPU_StoreHandleAndDataAtIndex( lIndex, ( OpaqueObjectHandle_t ) xHandle, NULL, KERNEL_OBJECT_TYPE_EVENT_GROUP )
-    #define MPU_GetEventGroupHandleAtIndex( lIndex )                 ( EventGroupHandle_t ) MPU_GetHandleAtIndex( lIndex, KERNEL_OBJECT_TYPE_EVENT_GROUP )
-    #define MPU_GetIndexForEventGroupHandle( xHandle )               MPU_GetIndexForHandle( ( OpaqueObjectHandle_t ) xHandle, KERNEL_OBJECT_TYPE_EVENT_GROUP )
+    #define MPU_StoreEventGroupHandleAtIndex( lIndex, xHandle )      MPU_StoreHandleAndDataAtIndex( ( lIndex ), ( OpaqueObjectHandle_t ) ( xHandle ), NULL, KERNEL_OBJECT_TYPE_EVENT_GROUP )
+    #define MPU_GetEventGroupHandleAtIndex( lIndex )                 ( EventGroupHandle_t ) MPU_GetHandleAtIndex( ( lIndex ), KERNEL_OBJECT_TYPE_EVENT_GROUP )
+    #define MPU_GetIndexForEventGroupHandle( xHandle )               MPU_GetIndexForHandle( ( OpaqueObjectHandle_t ) ( xHandle ), KERNEL_OBJECT_TYPE_EVENT_GROUP )
 
 /*
  * Wrappers to keep all the casting in one place for Stream Buffer APIs.
  */
-    #define MPU_StoreStreamBufferHandleAtIndex( lIndex, xHandle )    MPU_StoreHandleAndDataAtIndex( lIndex, ( OpaqueObjectHandle_t ) xHandle, NULL, KERNEL_OBJECT_TYPE_STREAM_BUFFER )
-    #define MPU_GetStreamBufferHandleAtIndex( lIndex )               ( StreamBufferHandle_t ) MPU_GetHandleAtIndex( lIndex, KERNEL_OBJECT_TYPE_STREAM_BUFFER )
-    #define MPU_GetIndexForStreamBufferHandle( xHandle )             MPU_GetIndexForHandle( ( OpaqueObjectHandle_t ) xHandle, KERNEL_OBJECT_TYPE_STREAM_BUFFER )
+    #define MPU_StoreStreamBufferHandleAtIndex( lIndex, xHandle )    MPU_StoreHandleAndDataAtIndex( ( lIndex ), ( OpaqueObjectHandle_t ) ( xHandle), NULL, KERNEL_OBJECT_TYPE_STREAM_BUFFER )
+    #define MPU_GetStreamBufferHandleAtIndex( lIndex )               ( StreamBufferHandle_t ) MPU_GetHandleAtIndex( ( lIndex ), KERNEL_OBJECT_TYPE_STREAM_BUFFER )
+    #define MPU_GetIndexForStreamBufferHandle( xHandle )             MPU_GetIndexForHandle( ( OpaqueObjectHandle_t ) ( xHandle ), KERNEL_OBJECT_TYPE_STREAM_BUFFER )
 
     #if ( configUSE_TIMERS == 1 )
 
 /*
  * Wrappers to keep all the casting in one place for Timer APIs.
  */
-        #define MPU_StoreTimerHandleAtIndex( lIndex, xHandle, pxApplicationCallback )    MPU_StoreHandleAndDataAtIndex( lIndex, ( OpaqueObjectHandle_t ) xHandle, ( void * ) pxApplicationCallback, KERNEL_OBJECT_TYPE_TIMER )
-        #define MPU_GetTimerHandleAtIndex( lIndex )                                      ( TimerHandle_t ) MPU_GetHandleAtIndex( lIndex, KERNEL_OBJECT_TYPE_TIMER )
-        #define MPU_GetIndexForTimerHandle( xHandle )                                    MPU_GetIndexForHandle( ( OpaqueObjectHandle_t ) xHandle, KERNEL_OBJECT_TYPE_TIMER )
+        #define MPU_StoreTimerHandleAtIndex( lIndex, xHandle, pxApplicationCallback )    MPU_StoreHandleAndDataAtIndex( ( lIndex ), ( OpaqueObjectHandle_t ) ( xHandle ), ( void * ) ( pxApplicationCallback ), KERNEL_OBJECT_TYPE_TIMER )
+        #define MPU_GetTimerHandleAtIndex( lIndex )                                      ( TimerHandle_t ) MPU_GetHandleAtIndex( ( lIndex ), KERNEL_OBJECT_TYPE_TIMER )
+        #define MPU_GetIndexForTimerHandle( xHandle )                                    MPU_GetIndexForHandle( ( OpaqueObjectHandle_t ) ( xHandle ), KERNEL_OBJECT_TYPE_TIMER )
 
     #endif /* #if ( configUSE_TIMERS == 1 ) */
 

From 1c35cb3bc90830fb58fbc15f76a16fa36adb7352 Mon Sep 17 00:00:00 2001
From: Darian <32921628+Dazza0@users.noreply.github.com>
Date: Sat, 3 Feb 2024 03:46:20 +0800
Subject: [PATCH 215/424] Enable xTaskGetCurrentTaskHandleForCore() for single
 core builds (#978)

Enable xTaskGetCurrentTaskHandleForCore() for single core builds

---------
Co-authored-by: Paul Bartell <pbartell@amazon.com>
Co-authored-by: Ching-Hsin Lee <chinglee@amazon.com>
---
 include/task.h |  4 +---
 tasks.c        | 36 ++++++++++++++++++++----------------
 2 files changed, 21 insertions(+), 19 deletions(-)

diff --git a/include/task.h b/include/task.h
index de12f429d..fa53f84d7 100644
--- a/include/task.h
+++ b/include/task.h
@@ -3574,9 +3574,7 @@ TaskHandle_t xTaskGetCurrentTaskHandle( void ) PRIVILEGED_FUNCTION;
 /*
  * Return the handle of the task running on specified core.
  */
-#if ( configNUMBER_OF_CORES > 1 )
-    TaskHandle_t xTaskGetCurrentTaskHandleForCore( BaseType_t xCoreID ) PRIVILEGED_FUNCTION;
-#endif
+TaskHandle_t xTaskGetCurrentTaskHandleForCore( BaseType_t xCoreID ) PRIVILEGED_FUNCTION;
 
 /*
  * Shortcut used by the queue implementation to prevent unnecessary call to
diff --git a/tasks.c b/tasks.c
index 38a80e2de..037ca2af9 100644
--- a/tasks.c
+++ b/tasks.c
@@ -6559,24 +6559,28 @@ static void prvResetNextTaskUnblockTime( void )
 
             return xReturn;
         }
-
-        TaskHandle_t xTaskGetCurrentTaskHandleForCore( BaseType_t xCoreID )
-        {
-            TaskHandle_t xReturn = NULL;
-
-            traceENTER_xTaskGetCurrentTaskHandleForCore( xCoreID );
-
-            if( taskVALID_CORE_ID( xCoreID ) != pdFALSE )
-            {
-                xReturn = pxCurrentTCBs[ xCoreID ];
-            }
-
-            traceRETURN_xTaskGetCurrentTaskHandleForCore( xReturn );
-
-            return xReturn;
-        }
     #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
 
+    TaskHandle_t xTaskGetCurrentTaskHandleForCore( BaseType_t xCoreID )
+    {
+        TaskHandle_t xReturn = NULL;
+
+        traceENTER_xTaskGetCurrentTaskHandleForCore( xCoreID );
+
+        if( taskVALID_CORE_ID( xCoreID ) != pdFALSE )
+        {
+            #if ( configNUMBER_OF_CORES == 1 )
+                xReturn = pxCurrentTCB;
+            #else /* #if ( configNUMBER_OF_CORES == 1 ) */
+                xReturn = pxCurrentTCBs[ xCoreID ];
+            #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
+        }
+
+        traceRETURN_xTaskGetCurrentTaskHandleForCore( xReturn );
+
+        return xReturn;
+    }
+
 #endif /* ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
 /*-----------------------------------------------------------*/
 

From c19b13cdfc326b55e4b7016333a58053400674c7 Mon Sep 17 00:00:00 2001
From: bradleysmith23 <74752142+bradleysmith23@users.noreply.github.com>
Date: Fri, 2 Feb 2024 14:28:43 -0800
Subject: [PATCH 216/424] Fix MISRA C 2012 Rule 14.4 Violations. (#975)

* Fix MISRA rule 14.4 violations.

* Use pdFALSE instead of 0 in comparison

Co-authored-by: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>

* Uncrustify: triggered by comment.

* Run Github Actions.

---------

Co-authored-by: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Co-authored-by: GitHub Action <action@github.com>
Co-authored-by: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
---
 tasks.c | 22 +++++++++++-----------
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/tasks.c b/tasks.c
index 037ca2af9..b0af5ffbe 100644
--- a/tasks.c
+++ b/tasks.c
@@ -175,17 +175,17 @@
 /*-----------------------------------------------------------*/
 
     #if ( configNUMBER_OF_CORES == 1 )
-        #define taskSELECT_HIGHEST_PRIORITY_TASK()                            \
-    do {                                                                      \
-        UBaseType_t uxTopPriority = uxTopReadyPriority;                       \
-                                                                              \
-        /* Find the highest priority queue that contains ready tasks. */      \
-        while( listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxTopPriority ] ) ) ) \
-        {                                                                     \
-            configASSERT( uxTopPriority );                                    \
-            --uxTopPriority;                                                  \
-        }                                                                     \
-                                                                              \
+        #define taskSELECT_HIGHEST_PRIORITY_TASK()                                       \
+    do {                                                                                 \
+        UBaseType_t uxTopPriority = uxTopReadyPriority;                                  \
+                                                                                         \
+        /* Find the highest priority queue that contains ready tasks. */                 \
+        while( listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxTopPriority ] ) ) != pdFALSE ) \
+        {                                                                                \
+            configASSERT( uxTopPriority );                                               \
+            --uxTopPriority;                                                             \
+        }                                                                                \
+                                                                                         \
         /* listGET_OWNER_OF_NEXT_ENTRY indexes through the list, so the tasks of \
          * the  same priority get an equal share of the processor time. */                    \
         listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) ); \

From 1065389c4e6356122b9642b1e23ff3835b3dfde9 Mon Sep 17 00:00:00 2001
From: bradleysmith23 <74752142+bradleysmith23@users.noreply.github.com>
Date: Mon, 5 Feb 2024 04:38:15 -0800
Subject: [PATCH 217/424] Fix MISRA C 2012 Rule 10.4 Violations (#972)

Fixes for violations of MISRA rule 10.4
---
 portable/Common/mpu_wrappers_v2.c | 38 +++++++++++++++----------------
 1 file changed, 19 insertions(+), 19 deletions(-)

diff --git a/portable/Common/mpu_wrappers_v2.c b/portable/Common/mpu_wrappers_v2.c
index 4f876ab99..af9e9f129 100644
--- a/portable/Common/mpu_wrappers_v2.c
+++ b/portable/Common/mpu_wrappers_v2.c
@@ -92,16 +92,16 @@
 /**
  * @brief Checks whether an external index is valid or not.
  */
-    #define IS_EXTERNAL_INDEX_VALID( lIndex ) \
-    ( ( ( lIndex ) >= INDEX_OFFSET ) &&       \
-      ( ( lIndex ) < ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE + INDEX_OFFSET ) ) )
+    #define IS_EXTERNAL_INDEX_VALID( lIndex )   \
+    ( ( ( ( lIndex ) >= INDEX_OFFSET ) &&       \
+        ( ( lIndex ) < ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE + INDEX_OFFSET ) ) ) ? pdTRUE : pdFALSE )
 
 /**
  * @brief Checks whether an internal index is valid or not.
  */
-    #define IS_INTERNAL_INDEX_VALID( lIndex ) \
-    ( ( ( lIndex ) >= 0 ) &&                  \
-      ( ( lIndex ) < ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE ) ) )
+    #define IS_INTERNAL_INDEX_VALID( lIndex )   \
+    ( ( ( ( lIndex ) >= 0 ) &&                  \
+        ( ( lIndex ) < ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE ) ) ) ? pdTRUE : pdFALSE )
 
 /**
  * @brief Converts an internal index into external.
@@ -2197,7 +2197,7 @@
                     if( ( !( ( pvItemToQueue == NULL ) && ( uxQueueItemSize != ( UBaseType_t ) 0U ) ) ) &&
                         ( !( ( xCopyPosition == queueOVERWRITE ) && ( uxQueueLength != ( UBaseType_t ) 1U ) ) )
                         #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
-                            && ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) )
+                            && ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0U ) ) )
                         #endif
                         )
                     {
@@ -2312,7 +2312,7 @@
 
                     if( ( !( ( ( pvBuffer ) == NULL ) && ( uxQueueItemSize != ( UBaseType_t ) 0U ) ) )
                         #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
-                            && ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) )
+                            && ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0U ) ) )
                         #endif
                         )
                     {
@@ -2364,7 +2364,7 @@
 
                     if( ( !( ( ( pvBuffer ) == NULL ) && ( uxQueueItemSize != ( UBaseType_t ) 0U ) ) )
                         #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
-                            && ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) )
+                            && ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0U ) ) )
                         #endif
                         )
                     {
@@ -2411,9 +2411,9 @@
                 {
                     uxQueueItemSize = uxQueueGetQueueItemSize( xInternalQueueHandle );
 
-                    if( ( uxQueueItemSize == 0 )
+                    if( ( uxQueueItemSize == 0U )
                         #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
-                            && ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) )
+                            && ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0U ) ) )
                         #endif
                         )
                     {
@@ -3906,10 +3906,10 @@
 
         if( xAreParamsReadable == pdTRUE )
         {
-            if( ( ( pxParams->uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 ) &&
-                ( pxParams->uxBitsToWaitFor != 0 )
+            if( ( ( pxParams->uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0U ) &&
+                ( pxParams->uxBitsToWaitFor != 0U )
                 #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
-                    && ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( pxParams->xTicksToWait != 0 ) ) )
+                    && ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( pxParams->xTicksToWait != 0U ) ) )
                 #endif
                 )
             {
@@ -3951,7 +3951,7 @@
         int32_t lIndex;
         BaseType_t xCallingTaskIsAuthorizedToAccessEventGroup = pdFALSE;
 
-        if( ( uxBitsToClear & eventEVENT_BITS_CONTROL_BYTES ) == 0 )
+        if( ( uxBitsToClear & eventEVENT_BITS_CONTROL_BYTES ) == 0U )
         {
             lIndex = ( int32_t ) xEventGroup;
 
@@ -3986,7 +3986,7 @@
         int32_t lIndex;
         BaseType_t xCallingTaskIsAuthorizedToAccessEventGroup = pdFALSE;
 
-        if( ( uxBitsToSet & eventEVENT_BITS_CONTROL_BYTES ) == 0 )
+        if( ( uxBitsToSet & eventEVENT_BITS_CONTROL_BYTES ) == 0U )
         {
             lIndex = ( int32_t ) xEventGroup;
 
@@ -4025,10 +4025,10 @@
         int32_t lIndex;
         BaseType_t xCallingTaskIsAuthorizedToAccessEventGroup = pdFALSE;
 
-        if( ( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 ) &&
-            ( uxBitsToWaitFor != 0 )
+        if( ( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0U ) &&
+            ( uxBitsToWaitFor != 0U )
             #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
-                && ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) )
+                && ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0U ) ) )
             #endif
             )
         {

From 938ec0f7bfb86ab70e49c23be625c99d760db4eb Mon Sep 17 00:00:00 2001
From: Eric Jackson <115876528+ericbj29@users.noreply.github.com>
Date: Mon, 5 Feb 2024 10:31:52 -0800
Subject: [PATCH 218/424] Correct ARM port folder capitalization (#981)

* Rename Arm_AARCH64 to ARM_AARCH64

* Rename Arm_AARCH64_SRE to ARM_AARCH64_SRE

* Update cmake for ARM port folder capitalization

* Update in portable/CmakeLists.txt
* Use capitalization name in port README.md

---------

Co-authored-by: Ching-Hsin Lee <chinglee@amazon.com>
---
 portable/CMakeLists.txt                                   | 8 ++++----
 portable/GCC/{Arm_AARCH64 => ARM_AARCH64}/README.md       | 4 ++--
 portable/GCC/{Arm_AARCH64 => ARM_AARCH64}/port.c          | 0
 portable/GCC/{Arm_AARCH64 => ARM_AARCH64}/portASM.S       | 0
 portable/GCC/{Arm_AARCH64 => ARM_AARCH64}/portmacro.h     | 0
 .../GCC/{Arm_AARCH64_SRE => ARM_AARCH64_SRE}/README.md    | 4 ++--
 portable/GCC/{Arm_AARCH64_SRE => ARM_AARCH64_SRE}/port.c  | 0
 .../GCC/{Arm_AARCH64_SRE => ARM_AARCH64_SRE}/portASM.S    | 0
 .../GCC/{Arm_AARCH64_SRE => ARM_AARCH64_SRE}/portmacro.h  | 0
 portable/GCC/ARM_CA53_64_BIT/README.md                    | 4 ++--
 portable/GCC/ARM_CA53_64_BIT_SRE/README.md                | 6 +++---
 11 files changed, 13 insertions(+), 13 deletions(-)
 rename portable/GCC/{Arm_AARCH64 => ARM_AARCH64}/README.md (96%)
 rename portable/GCC/{Arm_AARCH64 => ARM_AARCH64}/port.c (100%)
 rename portable/GCC/{Arm_AARCH64 => ARM_AARCH64}/portASM.S (100%)
 rename portable/GCC/{Arm_AARCH64 => ARM_AARCH64}/portmacro.h (100%)
 rename portable/GCC/{Arm_AARCH64_SRE => ARM_AARCH64_SRE}/README.md (95%)
 rename portable/GCC/{Arm_AARCH64_SRE => ARM_AARCH64_SRE}/port.c (100%)
 rename portable/GCC/{Arm_AARCH64_SRE => ARM_AARCH64_SRE}/portASM.S (100%)
 rename portable/GCC/{Arm_AARCH64_SRE => ARM_AARCH64_SRE}/portmacro.h (100%)

diff --git a/portable/CMakeLists.txt b/portable/CMakeLists.txt
index 98dcf8ed3..c067e9706 100644
--- a/portable/CMakeLists.txt
+++ b/portable/CMakeLists.txt
@@ -68,12 +68,12 @@ add_library(freertos_kernel_port OBJECT
 
     # ARMv8-A ports for GCC
     $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_AARCH64>:
-        GCC/Arm_AARCH64/port.c
-        GCC/Arm_AARCH64/portASM.S>
+        GCC/ARM_AARCH64/port.c
+        GCC/ARM_AARCH64/portASM.S>
 
     $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_AARCH64_SRE>:
-        GCC/Arm_AARCH64_SRE/port.c
-        GCC/Arm_AARCH64_SRE/portASM.S>
+        GCC/ARM_AARCH64_SRE/port.c
+        GCC/ARM_AARCH64_SRE/portASM.S>
 
     # ARMv6-M port for GCC
     $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM0>:
diff --git a/portable/GCC/Arm_AARCH64/README.md b/portable/GCC/ARM_AARCH64/README.md
similarity index 96%
rename from portable/GCC/Arm_AARCH64/README.md
rename to portable/GCC/ARM_AARCH64/README.md
index 70552c202..0bee96951 100644
--- a/portable/GCC/Arm_AARCH64/README.md
+++ b/portable/GCC/ARM_AARCH64/README.md
@@ -13,11 +13,11 @@ the T32 and A32 instruction sets. Follow the
 [link](https://developer.arm.com/Architectures/A-Profile%20Architecture)
 for more information.
 
-## Arm_AARCH64 port
+## ARM_AARCH64 port
 
 This port adds support for Armv8-A architecture AArch64 execution state.
 This port is generic and can be used as a starting point for Armv8-A
 application processors.
 
-* Arm_AARCH64
+* ARM_AARCH64
     * Memory mapped interace to access Arm GIC registers
diff --git a/portable/GCC/Arm_AARCH64/port.c b/portable/GCC/ARM_AARCH64/port.c
similarity index 100%
rename from portable/GCC/Arm_AARCH64/port.c
rename to portable/GCC/ARM_AARCH64/port.c
diff --git a/portable/GCC/Arm_AARCH64/portASM.S b/portable/GCC/ARM_AARCH64/portASM.S
similarity index 100%
rename from portable/GCC/Arm_AARCH64/portASM.S
rename to portable/GCC/ARM_AARCH64/portASM.S
diff --git a/portable/GCC/Arm_AARCH64/portmacro.h b/portable/GCC/ARM_AARCH64/portmacro.h
similarity index 100%
rename from portable/GCC/Arm_AARCH64/portmacro.h
rename to portable/GCC/ARM_AARCH64/portmacro.h
diff --git a/portable/GCC/Arm_AARCH64_SRE/README.md b/portable/GCC/ARM_AARCH64_SRE/README.md
similarity index 95%
rename from portable/GCC/Arm_AARCH64_SRE/README.md
rename to portable/GCC/ARM_AARCH64_SRE/README.md
index 0b2e0e485..4c9a55af0 100644
--- a/portable/GCC/Arm_AARCH64_SRE/README.md
+++ b/portable/GCC/ARM_AARCH64_SRE/README.md
@@ -13,11 +13,11 @@ the T32 and A32 instruction sets. Follow the
 [link](https://developer.arm.com/Architectures/A-Profile%20Architecture)
 for more information.
 
-## Arm_AARCH64_SRE port
+## ARM_AARCH64_SRE port
 
 This port adds support for Armv8-A architecture AArch64 execution state.
 This port is generic and can be used as a starting point for Armv8-A
 application processors.
 
-* Arm_AARCH64_SRE
+* ARM_AARCH64_SRE
     * System Register interace to access Arm GIC registers
diff --git a/portable/GCC/Arm_AARCH64_SRE/port.c b/portable/GCC/ARM_AARCH64_SRE/port.c
similarity index 100%
rename from portable/GCC/Arm_AARCH64_SRE/port.c
rename to portable/GCC/ARM_AARCH64_SRE/port.c
diff --git a/portable/GCC/Arm_AARCH64_SRE/portASM.S b/portable/GCC/ARM_AARCH64_SRE/portASM.S
similarity index 100%
rename from portable/GCC/Arm_AARCH64_SRE/portASM.S
rename to portable/GCC/ARM_AARCH64_SRE/portASM.S
diff --git a/portable/GCC/Arm_AARCH64_SRE/portmacro.h b/portable/GCC/ARM_AARCH64_SRE/portmacro.h
similarity index 100%
rename from portable/GCC/Arm_AARCH64_SRE/portmacro.h
rename to portable/GCC/ARM_AARCH64_SRE/portmacro.h
diff --git a/portable/GCC/ARM_CA53_64_BIT/README.md b/portable/GCC/ARM_CA53_64_BIT/README.md
index b3d56c040..a8df29e91 100644
--- a/portable/GCC/ARM_CA53_64_BIT/README.md
+++ b/portable/GCC/ARM_CA53_64_BIT/README.md
@@ -8,8 +8,8 @@ Arm Cortex-A53 processor.
 
 This port is generic and can be used as a starting point for other Armv8-A
 application processors. Therefore, the port `ARM_CA53_64_BIT` is renamed as
-`Arm_AARCH64`. The existing projects that use old port `ARM_CA53_64_BIT`,
-should migrate to renamed port `Arm_AARCH64`.
+`ARM_AARCH64`. The existing projects that use old port `ARM_CA53_64_BIT`,
+should migrate to renamed port `ARM_AARCH64`.
 
 **NOTE**
 
diff --git a/portable/GCC/ARM_CA53_64_BIT_SRE/README.md b/portable/GCC/ARM_CA53_64_BIT_SRE/README.md
index fb5d7936a..a5d415fc2 100644
--- a/portable/GCC/ARM_CA53_64_BIT_SRE/README.md
+++ b/portable/GCC/ARM_CA53_64_BIT_SRE/README.md
@@ -7,9 +7,9 @@ Arm Cortex-A53 processor.
     * System Register interace to access Arm GIC registers
 
 This port is generic and can be used as a starting point for other Armv8-A
-application processors. Therefore, the port `Arm_AARCH64_SRE` is renamed as
-`Arm_AARCH64_SRE`. The existing projects that use old port `Arm_AARCH64_SRE`,
-should migrate to renamed port `Arm_AARCH64_SRE`.
+application processors. Therefore, the port `ARM_AARCH64_SRE` is renamed as
+`ARM_AARCH64_SRE`. The existing projects that use old port `ARM_AARCH64_SRE`,
+should migrate to renamed port `ARM_AARCH64_SRE`.
 
 **NOTE**
 

From 23afc48fc370da20d4526a059807be95ba38ef74 Mon Sep 17 00:00:00 2001
From: Paul Bartell <pbartell@amazon.com>
Date: Tue, 6 Feb 2024 02:18:14 -0800
Subject: [PATCH 219/424] Update version number (#983)

* Update version number to 11.0.1+ in task.h

* Update Third Party Port version to <DEVELOPMENT BRANCH>

* Update version to 11.0.1 in manifest.yml
---
 include/task.h                                            | 8 ++++----
 manifest.yml                                              | 2 +-
 .../ThirdParty/GCC/RP2040/include/freertos_sdk_config.h   | 2 +-
 portable/ThirdParty/GCC/RP2040/include/portmacro.h        | 2 +-
 portable/ThirdParty/GCC/RP2040/include/rp2040_config.h    | 2 +-
 portable/ThirdParty/GCC/RP2040/port.c                     | 2 +-
 .../GCC/Xtensa_ESP32/include/FreeRTOSConfig_arch.h        | 2 +-
 portable/ThirdParty/GCC/Xtensa_ESP32/include/portmacro.h  | 2 +-
 portable/ThirdParty/GCC/Xtensa_ESP32/port.c               | 2 +-
 9 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/include/task.h b/include/task.h
index fa53f84d7..69d61a7b4 100644
--- a/include/task.h
+++ b/include/task.h
@@ -53,10 +53,10 @@
  * The tskKERNEL_VERSION_MAJOR, tskKERNEL_VERSION_MINOR, tskKERNEL_VERSION_BUILD
  * values will reflect the last released version number.
  */
-#define tskKERNEL_VERSION_NUMBER       "V10.4.4+"
-#define tskKERNEL_VERSION_MAJOR        10
-#define tskKERNEL_VERSION_MINOR        4
-#define tskKERNEL_VERSION_BUILD        4
+#define tskKERNEL_VERSION_NUMBER       "V11.0.1+"
+#define tskKERNEL_VERSION_MAJOR        11
+#define tskKERNEL_VERSION_MINOR        0
+#define tskKERNEL_VERSION_BUILD        1
 
 /* MPU region parameters passed in ulParameters
  * of MemoryRegion_t struct. */
diff --git a/manifest.yml b/manifest.yml
index 211e3c2ae..ac13cb60a 100644
--- a/manifest.yml
+++ b/manifest.yml
@@ -1,4 +1,4 @@
 name : "FreeRTOS-Kernel"
-version: "v10.5.1"
+version: "v11.0.1+"
 description: "FreeRTOS Kernel."
 license: "MIT"
diff --git a/portable/ThirdParty/GCC/RP2040/include/freertos_sdk_config.h b/portable/ThirdParty/GCC/RP2040/include/freertos_sdk_config.h
index bf9fdca5e..8d0676d95 100644
--- a/portable/ThirdParty/GCC/RP2040/include/freertos_sdk_config.h
+++ b/portable/ThirdParty/GCC/RP2040/include/freertos_sdk_config.h
@@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
diff --git a/portable/ThirdParty/GCC/RP2040/include/portmacro.h b/portable/ThirdParty/GCC/RP2040/include/portmacro.h
index 2b3f822b5..c9173fdea 100644
--- a/portable/ThirdParty/GCC/RP2040/include/portmacro.h
+++ b/portable/ThirdParty/GCC/RP2040/include/portmacro.h
@@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
diff --git a/portable/ThirdParty/GCC/RP2040/include/rp2040_config.h b/portable/ThirdParty/GCC/RP2040/include/rp2040_config.h
index a0f65c761..9fbbd15be 100644
--- a/portable/ThirdParty/GCC/RP2040/include/rp2040_config.h
+++ b/portable/ThirdParty/GCC/RP2040/include/rp2040_config.h
@@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
diff --git a/portable/ThirdParty/GCC/RP2040/port.c b/portable/ThirdParty/GCC/RP2040/port.c
index d022ca2fa..dda46f6f6 100644
--- a/portable/ThirdParty/GCC/RP2040/port.c
+++ b/portable/ThirdParty/GCC/RP2040/port.c
@@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/include/FreeRTOSConfig_arch.h b/portable/ThirdParty/GCC/Xtensa_ESP32/include/FreeRTOSConfig_arch.h
index 111c99f1a..f9c9630da 100644
--- a/portable/ThirdParty/GCC/Xtensa_ESP32/include/FreeRTOSConfig_arch.h
+++ b/portable/ThirdParty/GCC/Xtensa_ESP32/include/FreeRTOSConfig_arch.h
@@ -7,7 +7,7 @@
  */
 
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/include/portmacro.h b/portable/ThirdParty/GCC/Xtensa_ESP32/include/portmacro.h
index d3635f13b..e5e84efbc 100644
--- a/portable/ThirdParty/GCC/Xtensa_ESP32/include/portmacro.h
+++ b/portable/ThirdParty/GCC/Xtensa_ESP32/include/portmacro.h
@@ -8,7 +8,7 @@
  */
 
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/port.c b/portable/ThirdParty/GCC/Xtensa_ESP32/port.c
index 3f30592e7..f018bfd3f 100644
--- a/portable/ThirdParty/GCC/Xtensa_ESP32/port.c
+++ b/portable/ThirdParty/GCC/Xtensa_ESP32/port.c
@@ -8,7 +8,7 @@
  */
 
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of

From 57a5ed7f675e828fe020c33e636e094fa1354ea8 Mon Sep 17 00:00:00 2001
From: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Date: Tue, 6 Feb 2024 20:41:34 +0800
Subject: [PATCH 220/424] Fix SMP task self void run state change (#984)

* Request a task to yield after been suspended or deleted to prevent this task puts itself back to another list
* Fix volatile variable access order to ensure ensure compliance with MISRA C 2012 Rule 13.5

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 tasks.c | 167 ++++++++++++++++++++++++++++++--------------------------
 1 file changed, 89 insertions(+), 78 deletions(-)

diff --git a/tasks.c b/tasks.c
index b0af5ffbe..5cda6ec85 100644
--- a/tasks.c
+++ b/tasks.c
@@ -2191,6 +2191,7 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
     {
         TCB_t * pxTCB;
         BaseType_t xDeleteTCBInIdleTask = pdFALSE;
+        BaseType_t xTaskIsRunningOrYielding;
 
         traceENTER_vTaskDelete( xTaskToDelete );
 
@@ -2226,10 +2227,15 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
              * not return. */
             uxTaskNumber++;
 
+            /* Use temp variable as distinct sequence points for reading volatile
+             * variables prior to a logical operator to ensure compliance with
+             * MISRA C 2012 Rule 13.5. */
+            xTaskIsRunningOrYielding = taskTASK_IS_RUNNING_OR_SCHEDULED_TO_YIELD( pxTCB );
+
             /* If the task is running (or yielding), we must add it to the
              * termination list so that an idle task can delete it when it is
              * no longer running. */
-            if( ( xSchedulerRunning != pdFALSE ) && ( taskTASK_IS_RUNNING_OR_SCHEDULED_TO_YIELD( pxTCB ) != pdFALSE ) )
+            if( ( xSchedulerRunning != pdFALSE ) && ( xTaskIsRunningOrYielding != pdFALSE ) )
             {
                 /* A running task or a task which is scheduled to yield is being
                  * deleted. This cannot complete when the task is still running
@@ -2261,6 +2267,30 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
                 #else
                     portPRE_TASK_DELETE_HOOK( pxTCB, &( xYieldPendings[ pxTCB->xTaskRunState ] ) );
                 #endif
+
+                /* In the case of SMP, it is possible that the task being deleted
+                 * is running on another core. We must evict the task before
+                 * exiting the critical section to ensure that the task cannot
+                 * take an action which puts it back on ready/state/event list,
+                 * thereby nullifying the delete operation. Once evicted, the
+                 * task won't be scheduled ever as it will no longer be on the
+                 * ready list. */
+                #if ( configNUMBER_OF_CORES > 1 )
+                {
+                    if( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE )
+                    {
+                        if( pxTCB->xTaskRunState == ( BaseType_t ) portGET_CORE_ID() )
+                        {
+                            configASSERT( uxSchedulerSuspended == 0 );
+                            taskYIELD_WITHIN_API();
+                        }
+                        else
+                        {
+                            prvYieldCore( pxTCB->xTaskRunState );
+                        }
+                    }
+                }
+                #endif /* #if ( configNUMBER_OF_CORES > 1 ) */
             }
             else
             {
@@ -2284,9 +2314,9 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
 
         /* Force a reschedule if it is the currently running task that has just
          * been deleted. */
-        if( xSchedulerRunning != pdFALSE )
+        #if ( configNUMBER_OF_CORES == 1 )
         {
-            #if ( configNUMBER_OF_CORES == 1 )
+            if( xSchedulerRunning != pdFALSE )
             {
                 if( pxTCB == pxCurrentTCB )
                 {
@@ -2298,30 +2328,8 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
                     mtCOVERAGE_TEST_MARKER();
                 }
             }
-            #else /* #if ( configNUMBER_OF_CORES == 1 ) */
-            {
-                /* It is important to use critical section here because
-                 * checking run state of a task must be done inside a
-                 * critical section. */
-                taskENTER_CRITICAL();
-                {
-                    if( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE )
-                    {
-                        if( pxTCB->xTaskRunState == ( BaseType_t ) portGET_CORE_ID() )
-                        {
-                            configASSERT( uxSchedulerSuspended == 0 );
-                            taskYIELD_WITHIN_API();
-                        }
-                        else
-                        {
-                            prvYieldCore( pxTCB->xTaskRunState );
-                        }
-                    }
-                }
-                taskEXIT_CRITICAL();
-            }
-            #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
         }
+        #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
 
         traceRETURN_vTaskDelete();
     }
@@ -3155,26 +3163,66 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
                 }
             }
             #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+
+            /* In the case of SMP, it is possible that the task being suspended
+             * is running on another core. We must evict the task before
+             * exiting the critical section to ensure that the task cannot
+             * take an action which puts it back on ready/state/event list,
+             * thereby nullifying the suspend operation. Once evicted, the
+             * task won't be scheduled before it is resumed as it will no longer
+             * be on the ready list. */
+            #if ( configNUMBER_OF_CORES > 1 )
+            {
+                if( xSchedulerRunning != pdFALSE )
+                {
+                    /* Reset the next expected unblock time in case it referred to the
+                     * task that is now in the Suspended state. */
+                    prvResetNextTaskUnblockTime();
+
+                    if( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE )
+                    {
+                        if( pxTCB->xTaskRunState == ( BaseType_t ) portGET_CORE_ID() )
+                        {
+                            /* The current task has just been suspended. */
+                            configASSERT( uxSchedulerSuspended == 0 );
+                            vTaskYieldWithinAPI();
+                        }
+                        else
+                        {
+                            prvYieldCore( pxTCB->xTaskRunState );
+                        }
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            #endif /* #if ( configNUMBER_OF_CORES > 1 ) */
         }
         taskEXIT_CRITICAL();
 
-        if( xSchedulerRunning != pdFALSE )
-        {
-            /* Reset the next expected unblock time in case it referred to the
-             * task that is now in the Suspended state. */
-            taskENTER_CRITICAL();
-            {
-                prvResetNextTaskUnblockTime();
-            }
-            taskEXIT_CRITICAL();
-        }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
-        }
-
         #if ( configNUMBER_OF_CORES == 1 )
         {
+            if( xSchedulerRunning != pdFALSE )
+            {
+                /* Reset the next expected unblock time in case it referred to the
+                 * task that is now in the Suspended state. */
+                taskENTER_CRITICAL();
+                {
+                    prvResetNextTaskUnblockTime();
+                }
+                taskEXIT_CRITICAL();
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+
             if( pxTCB == pxCurrentTCB )
             {
                 if( xSchedulerRunning != pdFALSE )
@@ -3207,43 +3255,6 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
                 mtCOVERAGE_TEST_MARKER();
             }
         }
-        #else /* #if ( configNUMBER_OF_CORES == 1 ) */
-        {
-            /* Enter critical section here to check run state of a task. */
-            taskENTER_CRITICAL();
-            {
-                if( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE )
-                {
-                    if( xSchedulerRunning != pdFALSE )
-                    {
-                        if( pxTCB->xTaskRunState == ( BaseType_t ) portGET_CORE_ID() )
-                        {
-                            /* The current task has just been suspended. */
-                            configASSERT( uxSchedulerSuspended == 0 );
-                            vTaskYieldWithinAPI();
-                        }
-                        else
-                        {
-                            prvYieldCore( pxTCB->xTaskRunState );
-                        }
-                    }
-                    else
-                    {
-                        /* This code path is not possible because only Idle tasks are
-                         * assigned a core before the scheduler is started ( i.e.
-                         * taskTASK_IS_RUNNING is only true for idle tasks before
-                         * the scheduler is started ) and idle tasks cannot be
-                         * suspended. */
-                        mtCOVERAGE_TEST_MARKER();
-                    }
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
-            }
-            taskEXIT_CRITICAL();
-        }
         #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
 
         traceRETURN_vTaskSuspend();

From 7284d84dc88c5aaf2dc8337044177728b8bdae2d Mon Sep 17 00:00:00 2001
From: Darian <32921628+Dazza0@users.noreply.github.com>
Date: Wed, 7 Feb 2024 13:14:04 +0800
Subject: [PATCH 221/424] Update task notification scheduler suspension usage
 (#982)

* Update task notification scheduler suspension

Previously ulTaskGenericNotifyTake() and xTaskGenericNotifyWait() would suspend
the scheduler while inside a critical section.

This commit changes the order by wrapping the critical sections in a scheduler
suspension block. This logic is more inuitive and allows the SMP scheduler
suspension logic to be simplified.

* tasks.c: Fix typo

* Use a complete sentence in comment

* Check portGET_CRITICAL_NESTING_COUNT when scheduler is running

* Prevent potential NULL pointer access when scheduler is not running

---------

Co-authored-by: Paul Bartell <pbartell@amazon.com>
Co-authored-by: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Co-authored-by: Ching-Hsin Lee <chinglee@amazon.com>
---
 tasks.c | 211 +++++++++++++++++++++++---------------------------------
 1 file changed, 87 insertions(+), 124 deletions(-)

diff --git a/tasks.c b/tasks.c
index 5cda6ec85..d226a91de 100644
--- a/tasks.c
+++ b/tasks.c
@@ -3822,6 +3822,9 @@ void vTaskSuspendAll( void )
 
         if( xSchedulerRunning != pdFALSE )
         {
+            /* This must never be called from inside a critical section. */
+            configASSERT( portGET_CRITICAL_NESTING_COUNT() == 0 );
+
             /* Writes to uxSchedulerSuspended must be protected by both the task AND ISR locks.
              * We must disable interrupts before we grab the locks in the event that this task is
              * interrupted and switches context before incrementing uxSchedulerSuspended.
@@ -3840,14 +3843,7 @@ void vTaskSuspendAll( void )
              * it. */
             if( uxSchedulerSuspended == 0U )
             {
-                if( portGET_CRITICAL_NESTING_COUNT() == 0U )
-                {
-                    prvCheckForRunStateChange();
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
+                prvCheckForRunStateChange();
             }
             else
             {
@@ -7676,83 +7672,67 @@ TickType_t uxTaskResetEventItemValue( void )
                                       TickType_t xTicksToWait )
     {
         uint32_t ulReturn;
-        BaseType_t xAlreadyYielded;
+        BaseType_t xAlreadyYielded, xShouldBlock = pdFALSE;
 
         traceENTER_ulTaskGenericNotifyTake( uxIndexToWaitOn, xClearCountOnExit, xTicksToWait );
 
         configASSERT( uxIndexToWaitOn < configTASK_NOTIFICATION_ARRAY_ENTRIES );
 
-        taskENTER_CRITICAL();
-
-        /* Only block if the notification count is not already non-zero. */
-        if( pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ] == 0UL )
+        /* We suspend the scheduler here as prvAddCurrentTaskToDelayedList is a
+         * non-deterministic operation. */
+        vTaskSuspendAll();
         {
-            /* Mark this task as waiting for a notification. */
-            pxCurrentTCB->ucNotifyState[ uxIndexToWaitOn ] = taskWAITING_NOTIFICATION;
-
-            if( xTicksToWait > ( TickType_t ) 0 )
+            /* We MUST enter a critical section to atomically check if a notification
+             * has occurred and set the flag to indicate that we are waiting for
+             * a notification. If we do not do so, a notification sent from an ISR
+             * will get lost. */
+            taskENTER_CRITICAL();
             {
-                traceTASK_NOTIFY_TAKE_BLOCK( uxIndexToWaitOn );
-
-                /* We MUST suspend the scheduler before exiting the critical
-                 * section (i.e. before enabling interrupts).
-                 *
-                 * If we do not do so, a notification sent from an ISR, which
-                 * happens after exiting the critical section and before
-                 * suspending the scheduler, will get lost. The sequence of
-                 * events will be:
-                 * 1. Exit critical section.
-                 * 2. Interrupt - ISR calls xTaskNotifyFromISR which adds the
-                 *    task to the Ready list.
-                 * 3. Suspend scheduler.
-                 * 4. prvAddCurrentTaskToDelayedList moves the task to the
-                 *    delayed or suspended list.
-                 * 5. Resume scheduler does not touch the task (because it is
-                 *    not on the pendingReady list), effectively losing the
-                 *    notification from the ISR.
-                 *
-                 * The same does not happen when we suspend the scheduler before
-                 * exiting the critical section. The sequence of events in this
-                 * case will be:
-                 * 1. Suspend scheduler.
-                 * 2. Exit critical section.
-                 * 3. Interrupt - ISR calls xTaskNotifyFromISR which adds the
-                 *    task to the pendingReady list as the scheduler is
-                 *    suspended.
-                 * 4. prvAddCurrentTaskToDelayedList adds the task to delayed or
-                 *    suspended list. Note that this operation does not nullify
-                 *    the add to pendingReady list done in the above step because
-                 *    a different list item, namely xEventListItem, is used for
-                 *    adding the task to the pendingReady list. In other words,
-                 *    the task still remains on the pendingReady list.
-                 * 5. Resume scheduler moves the task from pendingReady list to
-                 *    the Ready list.
-                 */
-                vTaskSuspendAll();
+                /* Only block if the notification count is not already non-zero. */
+                if( pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ] == 0UL )
                 {
-                    taskEXIT_CRITICAL();
+                    /* Mark this task as waiting for a notification. */
+                    pxCurrentTCB->ucNotifyState[ uxIndexToWaitOn ] = taskWAITING_NOTIFICATION;
 
-                    prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
-                }
-                xAlreadyYielded = xTaskResumeAll();
-
-                if( xAlreadyYielded == pdFALSE )
-                {
-                    taskYIELD_WITHIN_API();
+                    if( xTicksToWait > ( TickType_t ) 0 )
+                    {
+                        xShouldBlock = pdTRUE;
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
                 }
                 else
                 {
                     mtCOVERAGE_TEST_MARKER();
                 }
             }
+            taskEXIT_CRITICAL();
+
+            /* We are now out of the critical section but the scheduler is still
+             * suspended, so we are safe to do non-deterministic operations such
+             * as prvAddCurrentTaskToDelayedList. */
+            if( xShouldBlock == pdTRUE )
+            {
+                traceTASK_NOTIFY_TAKE_BLOCK( uxIndexToWaitOn );
+                prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+            }
             else
             {
-                taskEXIT_CRITICAL();
+                mtCOVERAGE_TEST_MARKER();
             }
         }
+        xAlreadyYielded = xTaskResumeAll();
+
+        /* Force a reschedule if xTaskResumeAll has not already done so. */
+        if( ( xShouldBlock == pdTRUE ) && ( xAlreadyYielded == pdFALSE ) )
+        {
+            taskYIELD_WITHIN_API();
+        }
         else
         {
-            taskEXIT_CRITICAL();
+            mtCOVERAGE_TEST_MARKER();
         }
 
         taskENTER_CRITICAL();
@@ -7796,88 +7776,71 @@ TickType_t uxTaskResetEventItemValue( void )
                                        uint32_t * pulNotificationValue,
                                        TickType_t xTicksToWait )
     {
-        BaseType_t xReturn, xAlreadyYielded;
+        BaseType_t xReturn, xAlreadyYielded, xShouldBlock = pdFALSE;
 
         traceENTER_xTaskGenericNotifyWait( uxIndexToWaitOn, ulBitsToClearOnEntry, ulBitsToClearOnExit, pulNotificationValue, xTicksToWait );
 
         configASSERT( uxIndexToWaitOn < configTASK_NOTIFICATION_ARRAY_ENTRIES );
 
-        taskENTER_CRITICAL();
-
-        /* Only block if a notification is not already pending. */
-        if( pxCurrentTCB->ucNotifyState[ uxIndexToWaitOn ] != taskNOTIFICATION_RECEIVED )
+        /* We suspend the scheduler here as prvAddCurrentTaskToDelayedList is a
+         * non-deterministic operation. */
+        vTaskSuspendAll();
         {
-            /* Clear bits in the task's notification value as bits may get
-             * set  by the notifying task or interrupt.  This can be used to
-             * clear the value to zero. */
-            pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ] &= ~ulBitsToClearOnEntry;
-
-            /* Mark this task as waiting for a notification. */
-            pxCurrentTCB->ucNotifyState[ uxIndexToWaitOn ] = taskWAITING_NOTIFICATION;
-
-            if( xTicksToWait > ( TickType_t ) 0 )
+            /* We MUST enter a critical section to atomically check and update the
+             * task notification value. If we do not do so, a notification from
+             * an ISR will get lost. */
+            taskENTER_CRITICAL();
             {
-                traceTASK_NOTIFY_WAIT_BLOCK( uxIndexToWaitOn );
-
-                /* We MUST suspend the scheduler before exiting the critical
-                 * section (i.e. before enabling interrupts).
-                 *
-                 * If we do not do so, a notification sent from an ISR, which
-                 * happens after exiting the critical section and before
-                 * suspending the scheduler, will get lost. The sequence of
-                 * events will be:
-                 * 1. Exit critical section.
-                 * 2. Interrupt - ISR calls xTaskNotifyFromISR which adds the
-                 *    task to the Ready list.
-                 * 3. Suspend scheduler.
-                 * 4. prvAddCurrentTaskToDelayedList moves the task to the
-                 *    delayed or suspended list.
-                 * 5. Resume scheduler does not touch the task (because it is
-                 *    not on the pendingReady list), effectively losing the
-                 *    notification from the ISR.
-                 *
-                 * The same does not happen when we suspend the scheduler before
-                 * exiting the critical section. The sequence of events in this
-                 * case will be:
-                 * 1. Suspend scheduler.
-                 * 2. Exit critical section.
-                 * 3. Interrupt - ISR calls xTaskNotifyFromISR which adds the
-                 *    task to the pendingReady list as the scheduler is
-                 *    suspended.
-                 * 4. prvAddCurrentTaskToDelayedList adds the task to delayed or
-                 *    suspended list. Note that this operation does not nullify
-                 *    the add to pendingReady list done in the above step because
-                 *    a different list item, namely xEventListItem, is used for
-                 *    adding the task to the pendingReady list. In other words,
-                 *    the task still remains on the pendingReady list.
-                 * 5. Resume scheduler moves the task from pendingReady list to
-                 *    the Ready list.
-                 */
-                vTaskSuspendAll();
+                /* Only block if a notification is not already pending. */
+                if( pxCurrentTCB->ucNotifyState[ uxIndexToWaitOn ] != taskNOTIFICATION_RECEIVED )
                 {
-                    taskEXIT_CRITICAL();
+                    /* Clear bits in the task's notification value as bits may get
+                     * set by the notifying task or interrupt. This can be used
+                     * to clear the value to zero. */
+                    pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ] &= ~ulBitsToClearOnEntry;
 
-                    prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
-                }
-                xAlreadyYielded = xTaskResumeAll();
+                    /* Mark this task as waiting for a notification. */
+                    pxCurrentTCB->ucNotifyState[ uxIndexToWaitOn ] = taskWAITING_NOTIFICATION;
 
-                if( xAlreadyYielded == pdFALSE )
-                {
-                    taskYIELD_WITHIN_API();
+                    if( xTicksToWait > ( TickType_t ) 0 )
+                    {
+                        xShouldBlock = pdTRUE;
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
                 }
                 else
                 {
                     mtCOVERAGE_TEST_MARKER();
                 }
             }
+            taskEXIT_CRITICAL();
+
+            /* We are now out of the critical section but the scheduler is still
+             * suspended, so we are safe to do non-deterministic operations such
+             * as prvAddCurrentTaskToDelayedList. */
+            if( xShouldBlock == pdTRUE )
+            {
+                traceTASK_NOTIFY_WAIT_BLOCK( uxIndexToWaitOn );
+                prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+            }
             else
             {
-                taskEXIT_CRITICAL();
+                mtCOVERAGE_TEST_MARKER();
             }
         }
+        xAlreadyYielded = xTaskResumeAll();
+
+        /* Force a reschedule if xTaskResumeAll has not already done so. */
+        if( ( xShouldBlock == pdTRUE ) && ( xAlreadyYielded == pdFALSE ) )
+        {
+            taskYIELD_WITHIN_API();
+        }
         else
         {
-            taskEXIT_CRITICAL();
+            mtCOVERAGE_TEST_MARKER();
         }
 
         taskENTER_CRITICAL();

From bd652237fb76ab39b36215a2bd93fa8a14056f1f Mon Sep 17 00:00:00 2001
From: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Date: Tue, 13 Feb 2024 10:09:32 +0530
Subject: [PATCH 222/424] Update default value of configSTACK_DEPTH_TYPE in
 config file (#987)

---
 include/FreeRTOS.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/include/FreeRTOS.h b/include/FreeRTOS.h
index a23b67169..9ef6217cf 100644
--- a/include/FreeRTOS.h
+++ b/include/FreeRTOS.h
@@ -2799,9 +2799,9 @@
 
 #ifndef configSTACK_DEPTH_TYPE
 
-/* Defaults to uint16_t for backward compatibility, but can be overridden
- * in FreeRTOSConfig.h if uint16_t is too restrictive. */
-    #define configSTACK_DEPTH_TYPE    uint16_t
+/* Defaults to StackType_t for backward compatibility, but can be overridden
+ * in FreeRTOSConfig.h if StackType_t is too restrictive. */
+    #define configSTACK_DEPTH_TYPE    StackType_t
 #endif
 
 #ifndef configRUN_TIME_COUNTER_TYPE

From 8cfa7152f75c397e04eb779d2812c0edd26bd1c7 Mon Sep 17 00:00:00 2001
From: bradleysmith23 <74752142+bradleysmith23@users.noreply.github.com>
Date: Mon, 12 Feb 2024 21:11:30 -0800
Subject: [PATCH 223/424] Fix MISRA C 2012 Rule 13.2 Violations (#979)

* Fix violations of MISRA rule 13.2

* Fix typo in UBaseType_t

* Uncrustify: triggered by comment.

* Run Github Actions.

* Remove temp variable for uxCurrentNumberOfTasks

Co-authored-by: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>

* Declare uxCurrentListLength at top of function, update comment.

* Update location of uxCurrentListLength Declaration

* Uncrustify: triggered by comment.

* Run Github Actions

* Uncrustify: triggered by comment.

* Run Github Actions.

* Update comment explaining use of temp variable

---------

Co-authored-by: GitHub Action <action@github.com>
Co-authored-by: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Co-authored-by: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
---
 tasks.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/tasks.c b/tasks.c
index d226a91de..95f60b1fb 100644
--- a/tasks.c
+++ b/tasks.c
@@ -3208,6 +3208,8 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
 
         #if ( configNUMBER_OF_CORES == 1 )
         {
+            UBaseType_t uxCurrentListLength;
+
             if( xSchedulerRunning != pdFALSE )
             {
                 /* Reset the next expected unblock time in case it referred to the
@@ -3236,7 +3238,13 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
                     /* The scheduler is not running, but the task that was pointed
                      * to by pxCurrentTCB has just been suspended and pxCurrentTCB
                      * must be adjusted to point to a different task. */
-                    if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == uxCurrentNumberOfTasks )
+
+                    /* Use a temp variable as a distinct sequence point for reading
+                     * volatile variables prior to a comparison to ensure compliance
+                     * with MISRA C 2012 Rule 13.2. */
+                    uxCurrentListLength = listCURRENT_LIST_LENGTH( &xSuspendedTaskList );
+
+                    if( uxCurrentListLength == uxCurrentNumberOfTasks )
                     {
                         /* No other tasks are ready, so set pxCurrentTCB back to
                          * NULL so when the next task is created pxCurrentTCB will

From 8c10944575121038c532d23b2136c4c849b9d2a6 Mon Sep 17 00:00:00 2001
From: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Date: Tue, 13 Feb 2024 20:10:20 +0530
Subject: [PATCH 224/424] Remove PRIVILEGED FUNCTION from function definiton
 (#989)

---
 include/message_buffer.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/message_buffer.h b/include/message_buffer.h
index 74fab118f..d693d28cc 100644
--- a/include/message_buffer.h
+++ b/include/message_buffer.h
@@ -795,7 +795,7 @@ typedef StreamBufferHandle_t MessageBufferHandle_t;
  * \ingroup MessageBufferManagement
  */
 #define xMessageBufferNextLengthBytes( xMessageBuffer ) \
-    xStreamBufferNextMessageLengthBytes( xMessageBuffer ) PRIVILEGED_FUNCTION;
+    xStreamBufferNextMessageLengthBytes( xMessageBuffer )
 
 /**
  * message_buffer.h

From 4d34700bccbd8bcd09dca93e93ebabd692b2f185 Mon Sep 17 00:00:00 2001
From: bradleysmith23 <74752142+bradleysmith23@users.noreply.github.com>
Date: Tue, 13 Feb 2024 22:18:35 -0800
Subject: [PATCH 225/424] Fix MISRA C 2012 Rule 13.3 Violations (#988)

* MISRA Rule 13.3 Fixes

* Add semiicolons that were accidentally removed

* Add parentheses back around pxList->uxNumberOfItems where removed.

* Formatting fix

* Add Casts to UBaseType_t

---------

Co-authored-by: bjbsmith <bjbsmith@uafeb6a6bcdce55.ant.amazon.com>
Co-authored-by: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Co-authored-by: Soren Ptak <ptaksoren@gmail.com>
---
 include/list.h | 24 ++++++++++++------------
 list.c         |  9 ++++-----
 tasks.c        | 10 +++++-----
 3 files changed, 21 insertions(+), 22 deletions(-)

diff --git a/include/list.h b/include/list.h
index 7084834dc..9b96ab137 100644
--- a/include/list.h
+++ b/include/list.h
@@ -326,7 +326,7 @@ typedef struct xLIST
         }                                                                        \
                                                                                  \
         ( pxItemToRemove )->pxContainer = NULL;                                  \
-        ( pxList->uxNumberOfItems )--;                                           \
+        ( ( pxList )->uxNumberOfItems ) -= ( UBaseType_t ) 1U;                   \
     } while( 0 )
 
 /*
@@ -363,17 +363,17 @@ typedef struct xLIST
                                                                                 \
         /* Insert a new list item into ( pxList ), but rather than sort the list, \
          * makes the new list item the last item to be removed by a call to \
-         * listGET_OWNER_OF_NEXT_ENTRY(). */                 \
-        ( pxNewListItem )->pxNext = pxIndex;                 \
-        ( pxNewListItem )->pxPrevious = pxIndex->pxPrevious; \
-                                                             \
-        pxIndex->pxPrevious->pxNext = ( pxNewListItem );     \
-        pxIndex->pxPrevious = ( pxNewListItem );             \
-                                                             \
-        /* Remember which list the item is in. */            \
-        ( pxNewListItem )->pxContainer = ( pxList );         \
-                                                             \
-        ( ( pxList )->uxNumberOfItems )++;                   \
+         * listGET_OWNER_OF_NEXT_ENTRY(). */                   \
+        ( pxNewListItem )->pxNext = pxIndex;                   \
+        ( pxNewListItem )->pxPrevious = pxIndex->pxPrevious;   \
+                                                               \
+        pxIndex->pxPrevious->pxNext = ( pxNewListItem );       \
+        pxIndex->pxPrevious = ( pxNewListItem );               \
+                                                               \
+        /* Remember which list the item is in. */              \
+        ( pxNewListItem )->pxContainer = ( pxList );           \
+                                                               \
+        ( ( pxList )->uxNumberOfItems ) += ( UBaseType_t ) 1U; \
     } while( 0 )
 
 /*
diff --git a/list.c b/list.c
index 907300896..0ac5b04a0 100644
--- a/list.c
+++ b/list.c
@@ -130,7 +130,7 @@ void vListInsertEnd( List_t * const pxList,
     /* Remember which list the item is in. */
     pxNewListItem->pxContainer = pxList;
 
-    ( pxList->uxNumberOfItems )++;
+    ( pxList->uxNumberOfItems ) += ( UBaseType_t ) 1U;
 
     traceRETURN_vListInsertEnd();
 }
@@ -205,12 +205,13 @@ void vListInsert( List_t * const pxList,
      * item later. */
     pxNewListItem->pxContainer = pxList;
 
-    ( pxList->uxNumberOfItems )++;
+    ( pxList->uxNumberOfItems ) += ( UBaseType_t ) 1U;
 
     traceRETURN_vListInsert();
 }
 /*-----------------------------------------------------------*/
 
+
 UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )
 {
     /* The list item knows which list it is in.  Obtain the list from the list
@@ -219,8 +220,6 @@ UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )
 
     traceENTER_uxListRemove( pxItemToRemove );
 
-
-
     pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;
     pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;
 
@@ -238,7 +237,7 @@ UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )
     }
 
     pxItemToRemove->pxContainer = NULL;
-    ( pxList->uxNumberOfItems )--;
+    ( pxList->uxNumberOfItems ) -= ( UBaseType_t ) 1U;
 
     traceRETURN_uxListRemove( pxList->uxNumberOfItems );
 
diff --git a/tasks.c b/tasks.c
index 95f60b1fb..c51c155a7 100644
--- a/tasks.c
+++ b/tasks.c
@@ -255,7 +255,7 @@
         pxTemp = pxDelayedTaskList;                                               \
         pxDelayedTaskList = pxOverflowDelayedTaskList;                            \
         pxOverflowDelayedTaskList = pxTemp;                                       \
-        xNumOfOverflows++;                                                        \
+        xNumOfOverflows += ( BaseType_t ) 1;                                      \
         prvResetNextTaskUnblockTime();                                            \
     } while( 0 )
 
@@ -2021,7 +2021,7 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
          * updated. */
         taskENTER_CRITICAL();
         {
-            uxCurrentNumberOfTasks++;
+            uxCurrentNumberOfTasks += ( UBaseType_t ) 1U;
 
             if( pxCurrentTCB == NULL )
             {
@@ -3815,7 +3815,7 @@ void vTaskSuspendAll( void )
 
         /* The scheduler is suspended if uxSchedulerSuspended is non-zero.  An increment
          * is used to allow calls to vTaskSuspendAll() to nest. */
-        ++uxSchedulerSuspended;
+        uxSchedulerSuspended += ( UBaseType_t ) 1U;
 
         /* Enforces ordering for ports and optimised compilers that may otherwise place
          * the above increment elsewhere. */
@@ -3968,7 +3968,7 @@ BaseType_t xTaskResumeAll( void )
              * previous call to vTaskSuspendAll(). */
             configASSERT( uxSchedulerSuspended != 0U );
 
-            --uxSchedulerSuspended;
+            uxSchedulerSuspended -= ( UBaseType_t ) 1U;
             portRELEASE_TASK_LOCK();
 
             if( uxSchedulerSuspended == ( UBaseType_t ) 0U )
@@ -4968,7 +4968,7 @@ BaseType_t xTaskIncrementTick( void )
     }
     else
     {
-        ++xPendedTicks;
+        xPendedTicks += 1U;
 
         /* The tick hook gets called at regular intervals, even if the
          * scheduler is locked. */

From e68975fcf75c26363ded33de9b98f2a1ccf65b03 Mon Sep 17 00:00:00 2001
From: Christoph Seitz <go2sh@users.noreply.github.com>
Date: Fri, 16 Feb 2024 06:42:18 +0100
Subject: [PATCH 226/424] Add default core affinity config value. (#996)

* Add default core affinity config value.

---------

Co-authored-by: Anubhav Rawal <rawalexe@amazon.com>
---
 examples/template_configuration/FreeRTOSConfig.h | 9 +++++++++
 include/FreeRTOS.h                               | 6 ++++++
 tasks.c                                          | 8 ++++----
 3 files changed, 19 insertions(+), 4 deletions(-)

diff --git a/examples/template_configuration/FreeRTOSConfig.h b/examples/template_configuration/FreeRTOSConfig.h
index 14aa3b24b..2c807142c 100644
--- a/examples/template_configuration/FreeRTOSConfig.h
+++ b/examples/template_configuration/FreeRTOSConfig.h
@@ -496,6 +496,15 @@
  * run any task on any available core. */
 #define configUSE_CORE_AFFINITY                   0
 
+/* When using SMP with core affinity feature enabled, set
+ * configTASK_DEFAULT_CORE_AFFINITY to change the default core affinity mask for
+ * tasks created without an affinity mask specified. Setting the define to 1 would
+ * make such tasks run on core 0 and setting it to (1 << portGET_CORE_ID()) would
+ * make such tasks run on the current core. This config value is useful, if
+ * swapping tasks between cores is not supported (e.g. Tricore) or if legacy code
+ * should be controlled. Defaults to tskNO_AFFINITY if left undefined. */
+#define configTASK_DEFAULT_CORE_AFFINITY          tskNO_AFFINITY
+
 /* When using SMP (i.e. configNUMBER_OF_CORES is greater than one), if
  * configUSE_TASK_PREEMPTION_DISABLE is set to 1, individual tasks can be set to
  * either pre-emptive or co-operative mode using the vTaskPreemptionDisable and
diff --git a/include/FreeRTOS.h b/include/FreeRTOS.h
index 9ef6217cf..0c386cc4d 100644
--- a/include/FreeRTOS.h
+++ b/include/FreeRTOS.h
@@ -484,6 +484,12 @@
     #define configUSE_CORE_AFFINITY    0
 #endif /* configUSE_CORE_AFFINITY */
 
+#if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
+    #ifndef configTASK_DEFAULT_CORE_AFFINITY
+        #define configTASK_DEFAULT_CORE_AFFINITY    tskNO_AFFINITY
+    #endif
+#endif
+
 #ifndef configUSE_PASSIVE_IDLE_HOOK
     #define configUSE_PASSIVE_IDLE_HOOK    0
 #endif /* configUSE_PASSIVE_IDLE_HOOK */
diff --git a/tasks.c b/tasks.c
index c51c155a7..6c399dbf5 100644
--- a/tasks.c
+++ b/tasks.c
@@ -1325,7 +1325,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
             #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
             {
                 /* Set the task's affinity before scheduling it. */
-                pxNewTCB->uxCoreAffinityMask = tskNO_AFFINITY;
+                pxNewTCB->uxCoreAffinityMask = configTASK_DEFAULT_CORE_AFFINITY;
             }
             #endif
 
@@ -1442,7 +1442,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
             #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
             {
                 /* Set the task's affinity before scheduling it. */
-                pxNewTCB->uxCoreAffinityMask = tskNO_AFFINITY;
+                pxNewTCB->uxCoreAffinityMask = configTASK_DEFAULT_CORE_AFFINITY;
             }
             #endif
 
@@ -1560,7 +1560,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
             #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
             {
                 /* Set the task's affinity before scheduling it. */
-                pxNewTCB->uxCoreAffinityMask = tskNO_AFFINITY;
+                pxNewTCB->uxCoreAffinityMask = configTASK_DEFAULT_CORE_AFFINITY;
             }
             #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */
 
@@ -1733,7 +1733,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
             #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
             {
                 /* Set the task's affinity before scheduling it. */
-                pxNewTCB->uxCoreAffinityMask = tskNO_AFFINITY;
+                pxNewTCB->uxCoreAffinityMask = configTASK_DEFAULT_CORE_AFFINITY;
             }
             #endif
 

From 1a500f1a7418588c4b3f88edd221891ee99d27cd Mon Sep 17 00:00:00 2001
From: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Date: Mon, 19 Feb 2024 14:39:31 +0800
Subject: [PATCH 227/424] Support reset kernel state for restarting scheduler
 (#944)

* Adding the following functions to reset kernel state. These functions are only required for application which
needs to restart the scheduler.
 - void vTaskResetState( void )
 - void vTimerResetState( void )
 - void vPortHeapResetState( void )
 - void vCoRoutineResetState( void )

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Chris Morgan <cmorgan@boston-engineering.com>
Co-authored-by: Soren Ptak <ptaksoren@gmail.com>
Co-authored-by: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
---
 croutine.c                | 27 ++++++++++++++++--
 include/croutine.h        |  7 +++++
 include/portable.h        |  6 ++++
 include/task.h            | 14 ++++++++++
 include/timers.h          |  6 ++++
 portable/MemMang/heap_1.c | 15 +++++++++-
 portable/MemMang/heap_2.c | 17 +++++++++++-
 portable/MemMang/heap_3.c | 12 ++++++++
 portable/MemMang/heap_4.c | 24 +++++++++++++---
 portable/MemMang/heap_5.c | 29 +++++++++++++++++---
 tasks.c                   | 58 +++++++++++++++++++++++++++++++++++++++
 timers.c                  | 12 ++++++++
 12 files changed, 215 insertions(+), 12 deletions(-)

diff --git a/croutine.c b/croutine.c
index daa88275f..4d210b732 100644
--- a/croutine.c
+++ b/croutine.c
@@ -52,8 +52,10 @@
 
 /* Other file private variables. --------------------------------*/
     CRCB_t * pxCurrentCoRoutine = NULL;
-    static UBaseType_t uxTopCoRoutineReadyPriority = 0;
-    static TickType_t xCoRoutineTickCount = 0, xLastTickCount = 0, xPassedTicks = 0;
+    static UBaseType_t uxTopCoRoutineReadyPriority = ( UBaseType_t ) 0U;
+    static TickType_t xCoRoutineTickCount = ( TickType_t ) 0U;
+    static TickType_t xLastTickCount = ( TickType_t ) 0U;
+    static TickType_t xPassedTicks = ( TickType_t ) 0U;
 
 /* The initial state of the co-routine when it is created. */
     #define corINITIAL_STATE    ( 0 )
@@ -378,5 +380,26 @@
 
         return xReturn;
     }
+/*-----------------------------------------------------------*/
+
+/*
+ * Reset state in this file. This state is normally initialized at start up.
+ * This function must be called by the application before restarting the
+ * scheduler.
+ */
+    void vCoRoutineResetState( void )
+    {
+        /* Lists for ready and blocked co-routines. */
+        pxDelayedCoRoutineList = NULL;
+        pxOverflowDelayedCoRoutineList = NULL;
+
+        /* Other file private variables. */
+        pxCurrentCoRoutine = NULL;
+        uxTopCoRoutineReadyPriority = ( UBaseType_t ) 0U;
+        xCoRoutineTickCount = ( TickType_t ) 0U;
+        xLastTickCount = ( TickType_t ) 0U;
+        xPassedTicks = ( TickType_t ) 0U;
+    }
+/*-----------------------------------------------------------*/
 
 #endif /* configUSE_CO_ROUTINES == 0 */
diff --git a/include/croutine.h b/include/croutine.h
index 40ac9765b..7888863e5 100644
--- a/include/croutine.h
+++ b/include/croutine.h
@@ -746,6 +746,13 @@ void vCoRoutineAddToDelayedList( TickType_t xTicksToDelay,
  */
 BaseType_t xCoRoutineRemoveFromEventList( const List_t * pxEventList );
 
+
+/*
+ * This function resets the internal state of the coroutine module. It must be
+ * called by the application before restarting the scheduler.
+ */
+void vCoRoutineResetState( void ) PRIVILEGED_FUNCTION;
+
 /* *INDENT-OFF* */
 #ifdef __cplusplus
     }
diff --git a/include/portable.h b/include/portable.h
index c4b350abf..da1d7ad49 100644
--- a/include/portable.h
+++ b/include/portable.h
@@ -194,6 +194,12 @@ size_t xPortGetMinimumEverFreeHeapSize( void ) PRIVILEGED_FUNCTION;
     #define vPortFreeStack       vPortFree
 #endif
 
+/*
+ * This function resets the internal state of the heap module. It must be called
+ * by the application before restarting the scheduler.
+ */
+void vPortHeapResetState( void ) PRIVILEGED_FUNCTION;
+
 #if ( configUSE_MALLOC_FAILED_HOOK == 1 )
 
 /**
diff --git a/include/task.h b/include/task.h
index 69d61a7b4..33d9d4c07 100644
--- a/include/task.h
+++ b/include/task.h
@@ -3438,6 +3438,20 @@ BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
  */
 BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) PRIVILEGED_FUNCTION;
 
+/**
+ * task.h
+ * @code{c}
+ * void vTaskResetState( void );
+ * @endcode
+ *
+ * This function resets the internal state of the task. It must be called by the
+ * application before restarting the scheduler.
+ *
+ * \defgroup vTaskResetState vTaskResetState
+ * \ingroup SchedulerControl
+ */
+void vTaskResetState( void ) PRIVILEGED_FUNCTION;
+
 
 /*-----------------------------------------------------------
 * SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES
diff --git a/include/timers.h b/include/timers.h
index f526fdedd..34dc406e4 100644
--- a/include/timers.h
+++ b/include/timers.h
@@ -1417,6 +1417,12 @@ BaseType_t xTimerGenericCommandFromISR( TimerHandle_t xTimer,
 
 #endif
 
+/*
+ * This function resets the internal state of the timer module. It must be called
+ * by the application before restarting the scheduler.
+ */
+void vTimerResetState( void ) PRIVILEGED_FUNCTION;
+
 /* *INDENT-OFF* */
 #ifdef __cplusplus
     }
diff --git a/portable/MemMang/heap_1.c b/portable/MemMang/heap_1.c
index 19f695b20..93538362f 100644
--- a/portable/MemMang/heap_1.c
+++ b/portable/MemMang/heap_1.c
@@ -64,7 +64,7 @@
 #endif /* configAPPLICATION_ALLOCATED_HEAP */
 
 /* Index into the ucHeap array. */
-static size_t xNextFreeByte = ( size_t ) 0;
+static size_t xNextFreeByte = ( size_t ) 0U;
 
 /*-----------------------------------------------------------*/
 
@@ -150,3 +150,16 @@ size_t xPortGetFreeHeapSize( void )
 {
     return( configADJUSTED_HEAP_SIZE - xNextFreeByte );
 }
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Reset the state in this file. This state is normally initialized at start up.
+ * This function must be called by the application before restarting the
+ * scheduler.
+ */
+void vPortHeapResetState( void )
+{
+    xNextFreeByte = ( size_t ) 0U;
+}
+/*-----------------------------------------------------------*/
diff --git a/portable/MemMang/heap_2.c b/portable/MemMang/heap_2.c
index fffcb9ca3..6f77f0869 100644
--- a/portable/MemMang/heap_2.c
+++ b/portable/MemMang/heap_2.c
@@ -113,6 +113,9 @@ PRIVILEGED_DATA static BlockLink_t xStart, xEnd;
  * fragmentation. */
 PRIVILEGED_DATA static size_t xFreeBytesRemaining = configADJUSTED_HEAP_SIZE;
 
+/* Indicates whether the heap has been initialised or not. */
+PRIVILEGED_DATA static BaseType_t xHeapHasBeenInitialised = pdFALSE;
+
 /*-----------------------------------------------------------*/
 
 /*
@@ -155,7 +158,6 @@ void * pvPortMalloc( size_t xWantedSize )
     BlockLink_t * pxBlock;
     BlockLink_t * pxPreviousBlock;
     BlockLink_t * pxNewBlockLink;
-    PRIVILEGED_DATA static BaseType_t xHeapHasBeenInitialised = pdFALSE;
     void * pvReturn = NULL;
     size_t xAdditionalRequiredSize;
 
@@ -384,3 +386,16 @@ static void prvHeapInit( void ) /* PRIVILEGED_FUNCTION */
     pxFirstFreeBlock->pxNextFreeBlock = &xEnd;
 }
 /*-----------------------------------------------------------*/
+
+/*
+ * Reset the state in this file. This state is normally initialized at start up.
+ * This function must be called by the application before restarting the
+ * scheduler.
+ */
+void vPortHeapResetState( void )
+{
+    xFreeBytesRemaining = configADJUSTED_HEAP_SIZE;
+
+    xHeapHasBeenInitialised = pdFALSE;
+}
+/*-----------------------------------------------------------*/
diff --git a/portable/MemMang/heap_3.c b/portable/MemMang/heap_3.c
index d174a57e9..2240068e8 100644
--- a/portable/MemMang/heap_3.c
+++ b/portable/MemMang/heap_3.c
@@ -92,3 +92,15 @@ void vPortFree( void * pv )
         ( void ) xTaskResumeAll();
     }
 }
+/*-----------------------------------------------------------*/
+
+/*
+ * Reset the state in this file. This state is normally initialized at start up.
+ * This function must be called by the application before restarting the
+ * scheduler.
+ */
+void vPortHeapResetState( void )
+{
+    /* No state needs to be re-initialised in heap_3. */
+}
+/*-----------------------------------------------------------*/
diff --git a/portable/MemMang/heap_4.c b/portable/MemMang/heap_4.c
index 507bf48b9..ea1e422da 100644
--- a/portable/MemMang/heap_4.c
+++ b/portable/MemMang/heap_4.c
@@ -163,10 +163,10 @@ PRIVILEGED_DATA static BlockLink_t * pxEnd = NULL;
 
 /* Keeps track of the number of calls to allocate and free memory as well as the
  * number of free bytes remaining, but says nothing about fragmentation. */
-PRIVILEGED_DATA static size_t xFreeBytesRemaining = 0U;
-PRIVILEGED_DATA static size_t xMinimumEverFreeBytesRemaining = 0U;
-PRIVILEGED_DATA static size_t xNumberOfSuccessfulAllocations = 0;
-PRIVILEGED_DATA static size_t xNumberOfSuccessfulFrees = 0;
+PRIVILEGED_DATA static size_t xFreeBytesRemaining = ( size_t ) 0U;
+PRIVILEGED_DATA static size_t xMinimumEverFreeBytesRemaining = ( size_t ) 0U;
+PRIVILEGED_DATA static size_t xNumberOfSuccessfulAllocations = ( size_t ) 0U;
+PRIVILEGED_DATA static size_t xNumberOfSuccessfulFrees = ( size_t ) 0U;
 
 /*-----------------------------------------------------------*/
 
@@ -608,3 +608,19 @@ void vPortGetHeapStats( HeapStats_t * pxHeapStats )
     taskEXIT_CRITICAL();
 }
 /*-----------------------------------------------------------*/
+
+/*
+ * Reset the state in this file. This state is normally initialized at start up.
+ * This function must be called by the application before restarting the
+ * scheduler.
+ */
+void vPortHeapResetState( void )
+{
+    pxEnd = NULL;
+
+    xFreeBytesRemaining = ( size_t ) 0U;
+    xMinimumEverFreeBytesRemaining = ( size_t ) 0U;
+    xNumberOfSuccessfulAllocations = ( size_t ) 0U;
+    xNumberOfSuccessfulFrees = ( size_t ) 0U;
+}
+/*-----------------------------------------------------------*/
diff --git a/portable/MemMang/heap_5.c b/portable/MemMang/heap_5.c
index 18234626a..4e1437393 100644
--- a/portable/MemMang/heap_5.c
+++ b/portable/MemMang/heap_5.c
@@ -187,10 +187,10 @@ PRIVILEGED_DATA static BlockLink_t * pxEnd = NULL;
 
 /* Keeps track of the number of calls to allocate and free memory as well as the
  * number of free bytes remaining, but says nothing about fragmentation. */
-PRIVILEGED_DATA static size_t xFreeBytesRemaining = 0U;
-PRIVILEGED_DATA static size_t xMinimumEverFreeBytesRemaining = 0U;
-PRIVILEGED_DATA static size_t xNumberOfSuccessfulAllocations = 0;
-PRIVILEGED_DATA static size_t xNumberOfSuccessfulFrees = 0;
+PRIVILEGED_DATA static size_t xFreeBytesRemaining = ( size_t ) 0U;
+PRIVILEGED_DATA static size_t xMinimumEverFreeBytesRemaining = ( size_t ) 0U;
+PRIVILEGED_DATA static size_t xNumberOfSuccessfulAllocations = ( size_t ) 0U;
+PRIVILEGED_DATA static size_t xNumberOfSuccessfulFrees = ( size_t ) 0U;
 
 #if ( configENABLE_HEAP_PROTECTOR == 1 )
 
@@ -707,3 +707,24 @@ void vPortGetHeapStats( HeapStats_t * pxHeapStats )
     taskEXIT_CRITICAL();
 }
 /*-----------------------------------------------------------*/
+
+/*
+ * Reset the state in this file. This state is normally initialized at start up.
+ * This function must be called by the application before restarting the
+ * scheduler.
+ */
+void vPortHeapResetState( void )
+{
+    pxEnd = NULL;
+
+    xFreeBytesRemaining = ( size_t ) 0U;
+    xMinimumEverFreeBytesRemaining = ( size_t ) 0U;
+    xNumberOfSuccessfulAllocations = ( size_t ) 0U;
+    xNumberOfSuccessfulFrees = ( size_t ) 0U;
+
+    #if ( configENABLE_HEAP_PROTECTOR == 1 )
+        pucHeapHighAddress = NULL;
+        pucHeapLowAddress = NULL;
+    #endif /* #if ( configENABLE_HEAP_PROTECTOR == 1 ) */
+}
+/*-----------------------------------------------------------*/
diff --git a/tasks.c b/tasks.c
index 6c399dbf5..217cc6201 100644
--- a/tasks.c
+++ b/tasks.c
@@ -8694,3 +8694,61 @@ static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait,
 
 #endif /* #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configKERNEL_PROVIDED_STATIC_MEMORY == 1 ) && ( portUSING_MPU_WRAPPERS == 0 ) ) */
 /*-----------------------------------------------------------*/
+
+/*
+ * Reset the state in this file. This state is normally initialized at start up.
+ * This function must be called by the application before restarting the
+ * scheduler.
+ */
+void vTaskResetState( void )
+{
+    BaseType_t xCoreID;
+
+    /* Task control block. */
+    #if ( configNUMBER_OF_CORES == 1 )
+    {
+        pxCurrentTCB = NULL;
+    }
+    #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
+
+    #if ( INCLUDE_vTaskDelete == 1 )
+    {
+        uxDeletedTasksWaitingCleanUp = ( UBaseType_t ) 0U;
+    }
+    #endif /* #if ( INCLUDE_vTaskDelete == 1 ) */
+
+    #if ( configUSE_POSIX_ERRNO == 1 )
+    {
+        FreeRTOS_errno = 0;
+    }
+    #endif /* #if ( configUSE_POSIX_ERRNO == 1 ) */
+
+    /* Other file private variables. */
+    uxCurrentNumberOfTasks = ( UBaseType_t ) 0U;
+    xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT;
+    uxTopReadyPriority = tskIDLE_PRIORITY;
+    xSchedulerRunning = pdFALSE;
+    xPendedTicks = ( TickType_t ) 0U;
+
+    for( xCoreID = 0; xCoreID < configNUMBER_OF_CORES; xCoreID++ )
+    {
+        xYieldPendings[ xCoreID ] = pdFALSE;
+    }
+
+    xNumOfOverflows = ( BaseType_t ) 0;
+    uxTaskNumber = ( UBaseType_t ) 0U;
+    xNextTaskUnblockTime = ( TickType_t ) 0U;
+
+    uxSchedulerSuspended = ( UBaseType_t ) 0U;
+
+    #if ( configGENERATE_RUN_TIME_STATS == 1 )
+    {
+        for( xCoreID = 0; xCoreID < configNUMBER_OF_CORES; xCoreID++ )
+        {
+            ulTaskSwitchedInTime[ xCoreID ] = 0U;
+            ulTotalRunTime[ xCoreID ] = 0U;
+        }
+    }
+    #endif /* #if ( configGENERATE_RUN_TIME_STATS == 1 ) */
+}
+/*-----------------------------------------------------------*/
diff --git a/timers.c b/timers.c
index a432e74c2..a3d0d0abe 100644
--- a/timers.c
+++ b/timers.c
@@ -1322,6 +1322,18 @@
     #endif /* configUSE_TRACE_FACILITY */
 /*-----------------------------------------------------------*/
 
+/*
+ * Reset the state in this file. This state is normally initialized at start up.
+ * This function must be called by the application before restarting the
+ * scheduler.
+ */
+    void vTimerResetState( void )
+    {
+        xTimerQueue = NULL;
+        xTimerTaskHandle = NULL;
+    }
+/*-----------------------------------------------------------*/
+
 /* This entire source file will be skipped if the application is not configured
  * to include software timer functionality.  If you want to include software timer
  * functionality then ensure configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */

From 2fcb0f48b1b93674781b85d8039e5b5c9e43ccf7 Mon Sep 17 00:00:00 2001
From: Aniruddha Kanhere <60444055+AniruddhaKanhere@users.noreply.github.com>
Date: Tue, 20 Feb 2024 08:49:41 -0800
Subject: [PATCH 228/424] Fix small bugs in Kernel (#998)

* Fix small bugs

* Cast sizeof to BaseType_t

* Test removing assert to fix UT

* Revert change to tasks.c

Since configIDLE_TASK_NAME must be defined as a string according to
the documentation, the macro will always be NULL terminated. Which
means that the check `if( cIdleName[ xIdleTaskNameIndex ] == ( char ) 0x00 )`
will catch the end of string.

* Update coverity config; Add coverity version; Update pvPortMalloc declaration to match the definitions.

* Add port files to sed command

* Remove warnings about unused parameters in port code

---------

Co-authored-by: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
---
 MISRA.md                                  |  10 +--
 examples/coverity/CMakeLists.txt          |   9 +-
 examples/coverity/coverity_misra.config   | 102 ++++++++++------------
 include/FreeRTOS.h                        |   8 +-
 include/portable.h                        |   2 +-
 portable/ThirdParty/GCC/Posix/portmacro.h |   2 +-
 portable/template/port.c                  |   4 +
 7 files changed, 68 insertions(+), 69 deletions(-)

diff --git a/MISRA.md b/MISRA.md
index 8d501e0bd..ee518bc2c 100644
--- a/MISRA.md
+++ b/MISRA.md
@@ -2,11 +2,11 @@
 
 FreeRTOS-Kernel conforms to [MISRA C:2012](https://www.misra.org.uk/misra-c)
 guidelines, with the deviations listed below. Compliance is checked with
-Coverity static analysis. Since the FreeRTOS kernel is designed for
-small-embedded devices, it needs to have a very small memory footprint and
-has to be efficient. To achieve that and to increase the performance, it
-deviates from some MISRA rules. The specific deviations, suppressed inline,
-are listed below.
+Coverity static analysis version 2023.6.1. Since the FreeRTOS kernel is
+designed for small-embedded devices, it needs to have a very small memory
+footprint and has to be efficient. To achieve that and to increase the
+performance, it deviates from some MISRA rules. The specific deviations,
+suppressed inline, are listed below.
 
 Additionally, [MISRA configuration file](examples/coverity/coverity_misra.config)
 contains project wide deviations.
diff --git a/examples/coverity/CMakeLists.txt b/examples/coverity/CMakeLists.txt
index b4538655e..00332b5ac 100644
--- a/examples/coverity/CMakeLists.txt
+++ b/examples/coverity/CMakeLists.txt
@@ -2,8 +2,9 @@ cmake_minimum_required(VERSION 3.15)
 
 project(coverity)
 
-set(FREERTOS_KERNEL_PATH "../../")
-FILE(GLOB FREERTOS_KERNEL_SOURCE ${FREERTOS_KERNEL_PATH}*.c)
+set(FREERTOS_KERNEL_PATH "../..")
+FILE(GLOB FREERTOS_KERNEL_SOURCE ${FREERTOS_KERNEL_PATH}/*.c)
+FILE(GLOB FREERTOS_PORT_CODE ${FREERTOS_KERNEL_PATH}/portable/template/*.c)
 
 # Coverity incorrectly infers the type of pdTRUE and pdFALSE as boolean because
 # of their names. This generates multiple false positive warnings about type
@@ -12,8 +13,8 @@ FILE(GLOB FREERTOS_KERNEL_SOURCE ${FREERTOS_KERNEL_PATH}*.c)
 # fixes the issue of incorrectly inferring the type of pdTRUE and pdFALSE as
 # boolean.
 add_custom_target(fix_source ALL
-                  COMMAND sed -i -b -e 's/pdFALSE/pdFAIL/g' -e 's/pdTRUE/pdPASS/g' ${FREERTOS_KERNEL_SOURCE}
-                  DEPENDS ${FREERTOS_KERNEL_SOURCE})
+                  COMMAND sed -i -b -e 's/pdFALSE/pdFAIL/g' -e 's/pdTRUE/pdPASS/g' ${FREERTOS_KERNEL_SOURCE} ${FREERTOS_PORT_CODE}
+                  DEPENDS ${FREERTOS_KERNEL_SOURCE} ${FREERTOS_PORT_CODE})
 
 # Add the freertos_config for FreeRTOS-Kernel.
 add_library(freertos_config INTERFACE)
diff --git a/examples/coverity/coverity_misra.config b/examples/coverity/coverity_misra.config
index 101b20031..d80ddb553 100644
--- a/examples/coverity/coverity_misra.config
+++ b/examples/coverity/coverity_misra.config
@@ -1,97 +1,91 @@
-// MISRA C-2012 Rules
-
 {
-    version : "2.0",
-    standard : "c2012",
-    title: "Coverity MISRA Configuration",
-    deviations : [
-        // Disable the following rules.
+    "version" : "2.0",
+    "standard" : "c2012",
+    "title": "Coverity MISRA Configuration",
+    "deviations" : [
         {
-            deviation: "Rule 3.1",
-            reason: "We post HTTP links in code comments which contain // inside comments blocks."
+            "deviation": "Rule 3.1",
+            "reason": "We post HTTP links in code comments which contain // inside comments blocks."
         },
         {
-            deviation: "Rule 14.4",
-            reason: "do while( 0 ) pattern is used in macros to prevent extra semi-colon."
-        },
-
-        // Disable the following advisory rules and directives.
-        {
-            deviation: "Directive 4.4",
-            reason: "Code snippet is used in comment to help explanation."
+            "deviation": "Rule 14.4",
+            "reason": "do while( 0 ) pattern is used in macros to prevent extra semi-colon."
         },
         {
-            deviation: "Directive 4.5",
-            reason: "Allow names that MISRA considers ambiguous."
+            "deviation": "Directive 4.4",
+            "reason": "Code snippet is used in comment to help explanation."
         },
         {
-            deviation: "Directive 4.6",
-            reason: "Allow port to use primitive type with typedefs."
+            "deviation": "Directive 4.5",
+            "reason": "Allow names that MISRA considers ambiguous."
         },
         {
-            deviation: "Directive 4.8",
-            reason: "HeapRegion_t and HeapStats_t are used only in heap files but declared in portable.h which is included in multiple source files. As a result, these definitions appear in multiple source files where they are not used."
+            "deviation": "Directive 4.6",
+            "reason": "Allow port to use primitive type with typedefs."
         },
         {
-            deviation: "Directive 4.9",
-            reason: "FreeRTOS-Kernel is optimised to work on small micro-controllers. To achieve that, function-like macros are used."
+            "deviation": "Directive 4.8",
+            "reason": "HeapRegion_t and HeapStats_t are used only in heap files but declared in portable.h which is included in multiple source files. As a result, these definitions appear in multiple source files where they are not used."
         },
         {
-            deviation: "Rule 2.3",
-            reason: "FreeRTOS defines types which is used in application."
+            "deviation": "Directive 4.9",
+            "reason": "FreeRTOS-Kernel is optimised to work on small micro-controllers. To achieve that, function-like macros are used."
         },
         {
-            deviation: "Rule 2.4",
-            reason: "Allow to define unused tag."
+            "deviation": "Rule 2.3",
+            "reason": "FreeRTOS defines types which is used in application."
         },
         {
-            deviation: "Rule 2.5",
-            reason: "Allow to define unused macro."
+            "deviation": "Rule 2.4",
+            "reason": "Allow to define unused tag."
         },
         {
-            deviation: "Rule 5.9",
-            reason: "Allow to define identifier with the same name in structure and global variable."
+            "deviation": "Rule 2.5",
+            "reason": "Allow to define unused macro."
         },
         {
-            deviation: "Rule 8.7",
-            reason: "API functions are not used by the library outside of the files they are defined; however, they must be externally visible in order to be used by an application."
+            "deviation": "Rule 5.9",
+            "reason": "Allow to define identifier with the same name in structure and global variable."
         },
         {
-            deviation: "Rule 8.9",
-            reason: "Allow to object to be defined in wider scope for debug purpose."
+            "deviation": "Rule 8.7",
+            "reason": "API functions are not used by the library outside of the files they are defined; however, they must be externally visible in order to be used by an application."
         },
         {
-            deviation: "Rule 8.13",
-            reason: "Allow to not to use const-qualified type for callback function."
+            "deviation": "Rule 8.9",
+            "reason": "Allow to object to be defined in wider scope for debug purpose."
         },
         {
-            deviation: "Rule 11.4",
-            reason: "Allow to convert between a pointer to object and an interger type for stack alignment."
+            "deviation": "Rule 8.13",
+            "reason": "Allow to not to use const-qualified type for callback function."
         },
         {
-            deviation: "Rule 15.4",
-            reason: "Allow to use multiple break statements in a loop."
+            "deviation": "Rule 11.4",
+            "reason": "Allow to convert between a pointer to object and an interger type for stack alignment."
         },
         {
-            deviation: "Rule 15.5",
-            reason: "Allow to use multiple points of exit."
+            "deviation": "Rule 15.4",
+            "reason": "Allow to use multiple break statements in a loop."
         },
         {
-            deviation: "Rule 17.8",
-            reason: "Allow to update the parameters of a function."
+            "deviation": "Rule 15.5",
+            "reason": "Allow to use multiple points of exit."
         },
         {
-            deviation: "Rule 18.4",
-            reason: "Allow to use pointer arithmetic."
+            "deviation": "Rule 17.8",
+            "reason": "Allow to update the parameters of a function."
         },
         {
-            deviation: "Rule 19.2",
-            reason: "Allow to use union."
+            "deviation": "Rule 18.4",
+            "reason": "Allow to use pointer arithmetic."
         },
         {
-            deviation: "Rule 20.5",
-            reason: "Allow to use #undef for MPU wrappers."
+            "deviation": "Rule 19.2",
+            "reason": "Allow to use union."
+        },
+        {
+            "deviation": "Rule 20.5",
+            "reason": "Allow to use #undef for MPU wrappers."
         }
     ]
 }
-
diff --git a/include/FreeRTOS.h b/include/FreeRTOS.h
index 0c386cc4d..b993893e7 100644
--- a/include/FreeRTOS.h
+++ b/include/FreeRTOS.h
@@ -96,6 +96,10 @@
     #define configNUMBER_OF_CORES    1
 #endif
 
+#ifndef configUSE_MALLOC_FAILED_HOOK
+    #define configUSE_MALLOC_FAILED_HOOK    0
+#endif
+
 /* Basic FreeRTOS definitions. */
 #include "projdefs.h"
 
@@ -2649,10 +2653,6 @@
     #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS()
 #endif
 
-#ifndef configUSE_MALLOC_FAILED_HOOK
-    #define configUSE_MALLOC_FAILED_HOOK    0
-#endif
-
 #ifndef portPRIVILEGE_BIT
     #define portPRIVILEGE_BIT    ( ( UBaseType_t ) 0x00 )
 #endif
diff --git a/include/portable.h b/include/portable.h
index da1d7ad49..ee7b49350 100644
--- a/include/portable.h
+++ b/include/portable.h
@@ -178,7 +178,7 @@ void vPortGetHeapStats( HeapStats_t * pxHeapStats );
 /*
  * Map to the memory management routines required for the port.
  */
-void * pvPortMalloc( size_t xSize ) PRIVILEGED_FUNCTION;
+void * pvPortMalloc( size_t xWantedSize ) PRIVILEGED_FUNCTION;
 void * pvPortCalloc( size_t xNum,
                      size_t xSize ) PRIVILEGED_FUNCTION;
 void vPortFree( void * pv ) PRIVILEGED_FUNCTION;
diff --git a/portable/ThirdParty/GCC/Posix/portmacro.h b/portable/ThirdParty/GCC/Posix/portmacro.h
index 6de25da45..d1e35d125 100644
--- a/portable/ThirdParty/GCC/Posix/portmacro.h
+++ b/portable/ThirdParty/GCC/Posix/portmacro.h
@@ -64,7 +64,7 @@ typedef long             BaseType_t;
 typedef unsigned long    UBaseType_t;
 
 typedef unsigned long    TickType_t;
-#define portMAX_DELAY              ( TickType_t ) ULONG_MAX
+#define portMAX_DELAY              ( ( TickType_t ) ULONG_MAX )
 
 #define portTICK_TYPE_IS_ATOMIC    1
 
diff --git a/portable/template/port.c b/portable/template/port.c
index d4eb56eac..7cac1c991 100644
--- a/portable/template/port.c
+++ b/portable/template/port.c
@@ -19,6 +19,10 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
                                      TaskFunction_t pxCode,
                                      void * pvParameters )
 {
+    ( void ) pxTopOfStack;
+    ( void ) pvParameters;
+    ( void ) * pxCode;
+
     return NULL;
 }
 

From 839ccb719b91ecd1cd066dc852110d2bbbe78cde Mon Sep 17 00:00:00 2001
From: Soren Ptak <ptaksoren@gmail.com>
Date: Mon, 26 Feb 2024 12:26:42 -0500
Subject: [PATCH 229/424] Use Regex for Copyright Year in Header Check (#1002)

---
 .github/scripts/kernel_checker.py                         | 8 ++++++--
 croutine.c                                                | 2 +-
 event_groups.c                                            | 2 +-
 examples/cmake_example/main.c                             | 2 +-
 examples/coverity/FreeRTOSConfig.h                        | 2 +-
 examples/template_configuration/FreeRTOSConfig.h          | 2 +-
 include/FreeRTOS.h                                        | 2 +-
 include/StackMacros.h                                     | 2 +-
 include/atomic.h                                          | 2 +-
 include/croutine.h                                        | 2 +-
 include/deprecated_definitions.h                          | 2 +-
 include/event_groups.h                                    | 2 +-
 include/list.h                                            | 2 +-
 include/message_buffer.h                                  | 2 +-
 include/mpu_prototypes.h                                  | 2 +-
 include/mpu_syscall_numbers.h                             | 2 +-
 include/mpu_wrappers.h                                    | 2 +-
 include/newlib-freertos.h                                 | 2 +-
 include/picolibc-freertos.h                               | 2 +-
 include/portable.h                                        | 2 +-
 include/projdefs.h                                        | 2 +-
 include/queue.h                                           | 2 +-
 include/semphr.h                                          | 2 +-
 include/stack_macros.h                                    | 2 +-
 include/stdint.readme                                     | 2 +-
 include/stream_buffer.h                                   | 2 +-
 include/task.h                                            | 2 +-
 include/timers.h                                          | 2 +-
 list.c                                                    | 2 +-
 portable/ARMv8M/copy_files.py                             | 2 +-
 portable/ARMv8M/non_secure/port.c                         | 2 +-
 .../portable/GCC/ARM_CM23/mpu_wrappers_v2_asm.c           | 2 +-
 .../ARMv8M/non_secure/portable/GCC/ARM_CM23/portasm.c     | 2 +-
 .../ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h   | 2 +-
 .../portable/GCC/ARM_CM23_NTZ/mpu_wrappers_v2_asm.c       | 2 +-
 .../ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portasm.c | 2 +-
 .../non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h      | 2 +-
 .../portable/GCC/ARM_CM33/mpu_wrappers_v2_asm.c           | 2 +-
 .../ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c     | 2 +-
 .../ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h   | 2 +-
 .../portable/GCC/ARM_CM33_NTZ/mpu_wrappers_v2_asm.c       | 2 +-
 .../ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c | 2 +-
 .../non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h      | 2 +-
 .../ARMv8M/non_secure/portable/GCC/ARM_CM35P/portmacro.h  | 2 +-
 .../ARMv8M/non_secure/portable/GCC/ARM_CM55/portmacro.h   | 2 +-
 .../ARMv8M/non_secure/portable/GCC/ARM_CM85/portmacro.h   | 2 +-
 .../portable/IAR/ARM_CM23/mpu_wrappers_v2_asm.S           | 2 +-
 .../ARMv8M/non_secure/portable/IAR/ARM_CM23/portasm.s     | 2 +-
 .../ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h   | 2 +-
 .../portable/IAR/ARM_CM23_NTZ/mpu_wrappers_v2_asm.S       | 2 +-
 .../ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portasm.s | 2 +-
 .../non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h      | 2 +-
 .../portable/IAR/ARM_CM33/mpu_wrappers_v2_asm.S           | 2 +-
 .../ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s     | 2 +-
 .../ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h   | 2 +-
 .../portable/IAR/ARM_CM33_NTZ/mpu_wrappers_v2_asm.S       | 2 +-
 .../ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s | 2 +-
 .../non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h      | 2 +-
 .../ARMv8M/non_secure/portable/IAR/ARM_CM35P/portmacro.h  | 2 +-
 .../ARMv8M/non_secure/portable/IAR/ARM_CM55/portmacro.h   | 2 +-
 .../ARMv8M/non_secure/portable/IAR/ARM_CM85/portmacro.h   | 2 +-
 portable/ARMv8M/non_secure/portasm.h                      | 2 +-
 portable/ARMv8M/non_secure/portmacrocommon.h              | 2 +-
 .../context/portable/GCC/ARM_CM23/secure_context_port.c   | 2 +-
 .../context/portable/GCC/ARM_CM33/secure_context_port.c   | 2 +-
 .../portable/IAR/ARM_CM23/secure_context_port_asm.s       | 2 +-
 .../portable/IAR/ARM_CM33/secure_context_port_asm.s       | 2 +-
 portable/ARMv8M/secure/context/secure_context.c           | 2 +-
 portable/ARMv8M/secure/context/secure_context.h           | 2 +-
 portable/ARMv8M/secure/heap/secure_heap.c                 | 2 +-
 portable/ARMv8M/secure/heap/secure_heap.h                 | 2 +-
 portable/ARMv8M/secure/init/secure_init.c                 | 2 +-
 portable/ARMv8M/secure/init/secure_init.h                 | 2 +-
 portable/ARMv8M/secure/macros/secure_port_macros.h        | 2 +-
 portable/BCC/16BitDOS/Flsh186/port.c                      | 2 +-
 portable/BCC/16BitDOS/Flsh186/prtmacro.h                  | 2 +-
 portable/BCC/16BitDOS/PC/port.c                           | 2 +-
 portable/BCC/16BitDOS/PC/prtmacro.h                       | 2 +-
 portable/BCC/16BitDOS/common/portasm.h                    | 2 +-
 portable/BCC/16BitDOS/common/portcomn.c                   | 2 +-
 portable/CCS/ARM_CM3/port.c                               | 2 +-
 portable/CCS/ARM_CM3/portasm.asm                          | 2 +-
 portable/CCS/ARM_CM3/portmacro.h                          | 2 +-
 portable/CCS/ARM_CM4F/port.c                              | 2 +-
 portable/CCS/ARM_CM4F/portasm.asm                         | 2 +-
 portable/CCS/ARM_CM4F/portmacro.h                         | 2 +-
 portable/CCS/ARM_Cortex-R4/port.c                         | 2 +-
 portable/CCS/ARM_Cortex-R4/portASM.asm                    | 2 +-
 portable/CCS/ARM_Cortex-R4/portmacro.h                    | 2 +-
 portable/CCS/MSP430X/data_model.h                         | 2 +-
 portable/CCS/MSP430X/port.c                               | 2 +-
 portable/CCS/MSP430X/portext.asm                          | 2 +-
 portable/CCS/MSP430X/portmacro.h                          | 2 +-
 portable/CodeWarrior/ColdFire_V1/port.c                   | 2 +-
 portable/CodeWarrior/ColdFire_V1/portasm.S                | 2 +-
 portable/CodeWarrior/ColdFire_V1/portmacro.h              | 2 +-
 portable/CodeWarrior/ColdFire_V2/port.c                   | 2 +-
 portable/CodeWarrior/ColdFire_V2/portasm.S                | 2 +-
 portable/CodeWarrior/ColdFire_V2/portmacro.h              | 2 +-
 portable/CodeWarrior/HCS12/port.c                         | 2 +-
 portable/CodeWarrior/HCS12/portmacro.h                    | 2 +-
 portable/Common/mpu_wrappers.c                            | 2 +-
 portable/Common/mpu_wrappers_v2.c                         | 2 +-
 portable/GCC/ARM7_AT91FR40008/port.c                      | 2 +-
 portable/GCC/ARM7_AT91FR40008/portISR.c                   | 2 +-
 portable/GCC/ARM7_AT91FR40008/portmacro.h                 | 2 +-
 portable/GCC/ARM7_AT91SAM7S/port.c                        | 2 +-
 portable/GCC/ARM7_AT91SAM7S/portISR.c                     | 2 +-
 portable/GCC/ARM7_AT91SAM7S/portmacro.h                   | 2 +-
 portable/GCC/ARM7_LPC2000/port.c                          | 2 +-
 portable/GCC/ARM7_LPC2000/portISR.c                       | 2 +-
 portable/GCC/ARM7_LPC2000/portmacro.h                     | 2 +-
 portable/GCC/ARM7_LPC23xx/port.c                          | 2 +-
 portable/GCC/ARM7_LPC23xx/portISR.c                       | 2 +-
 portable/GCC/ARM7_LPC23xx/portmacro.h                     | 2 +-
 portable/GCC/ARM_AARCH64/port.c                           | 2 +-
 portable/GCC/ARM_AARCH64/portASM.S                        | 2 +-
 portable/GCC/ARM_AARCH64/portmacro.h                      | 2 +-
 portable/GCC/ARM_AARCH64_SRE/port.c                       | 2 +-
 portable/GCC/ARM_AARCH64_SRE/portASM.S                    | 2 +-
 portable/GCC/ARM_AARCH64_SRE/portmacro.h                  | 2 +-
 portable/GCC/ARM_CA9/port.c                               | 2 +-
 portable/GCC/ARM_CA9/portASM.S                            | 2 +-
 portable/GCC/ARM_CA9/portmacro.h                          | 2 +-
 portable/GCC/ARM_CM0/port.c                               | 2 +-
 portable/GCC/ARM_CM0/portmacro.h                          | 2 +-
 portable/GCC/ARM_CM23/non_secure/mpu_wrappers_v2_asm.c    | 2 +-
 portable/GCC/ARM_CM23/non_secure/port.c                   | 2 +-
 portable/GCC/ARM_CM23/non_secure/portasm.c                | 2 +-
 portable/GCC/ARM_CM23/non_secure/portasm.h                | 2 +-
 portable/GCC/ARM_CM23/non_secure/portmacro.h              | 2 +-
 portable/GCC/ARM_CM23/non_secure/portmacrocommon.h        | 2 +-
 portable/GCC/ARM_CM23/secure/secure_context.c             | 2 +-
 portable/GCC/ARM_CM23/secure/secure_context.h             | 2 +-
 portable/GCC/ARM_CM23/secure/secure_context_port.c        | 2 +-
 portable/GCC/ARM_CM23/secure/secure_heap.c                | 2 +-
 portable/GCC/ARM_CM23/secure/secure_heap.h                | 2 +-
 portable/GCC/ARM_CM23/secure/secure_init.c                | 2 +-
 portable/GCC/ARM_CM23/secure/secure_init.h                | 2 +-
 portable/GCC/ARM_CM23/secure/secure_port_macros.h         | 2 +-
 .../GCC/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.c     | 2 +-
 portable/GCC/ARM_CM23_NTZ/non_secure/port.c               | 2 +-
 portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c            | 2 +-
 portable/GCC/ARM_CM23_NTZ/non_secure/portasm.h            | 2 +-
 portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h          | 2 +-
 portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h    | 2 +-
 portable/GCC/ARM_CM3/port.c                               | 2 +-
 portable/GCC/ARM_CM3/portmacro.h                          | 2 +-
 portable/GCC/ARM_CM33/non_secure/mpu_wrappers_v2_asm.c    | 2 +-
 portable/GCC/ARM_CM33/non_secure/port.c                   | 2 +-
 portable/GCC/ARM_CM33/non_secure/portasm.c                | 2 +-
 portable/GCC/ARM_CM33/non_secure/portasm.h                | 2 +-
 portable/GCC/ARM_CM33/non_secure/portmacro.h              | 2 +-
 portable/GCC/ARM_CM33/non_secure/portmacrocommon.h        | 2 +-
 portable/GCC/ARM_CM33/secure/secure_context.c             | 2 +-
 portable/GCC/ARM_CM33/secure/secure_context.h             | 2 +-
 portable/GCC/ARM_CM33/secure/secure_context_port.c        | 2 +-
 portable/GCC/ARM_CM33/secure/secure_heap.c                | 2 +-
 portable/GCC/ARM_CM33/secure/secure_heap.h                | 2 +-
 portable/GCC/ARM_CM33/secure/secure_init.c                | 2 +-
 portable/GCC/ARM_CM33/secure/secure_init.h                | 2 +-
 portable/GCC/ARM_CM33/secure/secure_port_macros.h         | 2 +-
 .../GCC/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.c     | 2 +-
 portable/GCC/ARM_CM33_NTZ/non_secure/port.c               | 2 +-
 portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c            | 2 +-
 portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h            | 2 +-
 portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h          | 2 +-
 portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h    | 2 +-
 portable/GCC/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.c   | 2 +-
 portable/GCC/ARM_CM35P/non_secure/port.c                  | 2 +-
 portable/GCC/ARM_CM35P/non_secure/portasm.c               | 2 +-
 portable/GCC/ARM_CM35P/non_secure/portasm.h               | 2 +-
 portable/GCC/ARM_CM35P/non_secure/portmacro.h             | 2 +-
 portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h       | 2 +-
 portable/GCC/ARM_CM35P/secure/secure_context.c            | 2 +-
 portable/GCC/ARM_CM35P/secure/secure_context.h            | 2 +-
 portable/GCC/ARM_CM35P/secure/secure_context_port.c       | 2 +-
 portable/GCC/ARM_CM35P/secure/secure_heap.c               | 2 +-
 portable/GCC/ARM_CM35P/secure/secure_heap.h               | 2 +-
 portable/GCC/ARM_CM35P/secure/secure_init.c               | 2 +-
 portable/GCC/ARM_CM35P/secure/secure_init.h               | 2 +-
 portable/GCC/ARM_CM35P/secure/secure_port_macros.h        | 2 +-
 .../GCC/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.c    | 2 +-
 portable/GCC/ARM_CM35P_NTZ/non_secure/port.c              | 2 +-
 portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.c           | 2 +-
 portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.h           | 2 +-
 portable/GCC/ARM_CM35P_NTZ/non_secure/portmacro.h         | 2 +-
 portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h   | 2 +-
 portable/GCC/ARM_CM3_MPU/mpu_wrappers_v2_asm.c            | 2 +-
 portable/GCC/ARM_CM3_MPU/port.c                           | 2 +-
 portable/GCC/ARM_CM3_MPU/portmacro.h                      | 2 +-
 portable/GCC/ARM_CM4F/port.c                              | 2 +-
 portable/GCC/ARM_CM4F/portmacro.h                         | 2 +-
 portable/GCC/ARM_CM4_MPU/mpu_wrappers_v2_asm.c            | 2 +-
 portable/GCC/ARM_CM4_MPU/port.c                           | 2 +-
 portable/GCC/ARM_CM4_MPU/portmacro.h                      | 2 +-
 portable/GCC/ARM_CM55/non_secure/mpu_wrappers_v2_asm.c    | 2 +-
 portable/GCC/ARM_CM55/non_secure/port.c                   | 2 +-
 portable/GCC/ARM_CM55/non_secure/portasm.c                | 2 +-
 portable/GCC/ARM_CM55/non_secure/portasm.h                | 2 +-
 portable/GCC/ARM_CM55/non_secure/portmacro.h              | 2 +-
 portable/GCC/ARM_CM55/non_secure/portmacrocommon.h        | 2 +-
 portable/GCC/ARM_CM55/secure/secure_context.c             | 2 +-
 portable/GCC/ARM_CM55/secure/secure_context.h             | 2 +-
 portable/GCC/ARM_CM55/secure/secure_context_port.c        | 2 +-
 portable/GCC/ARM_CM55/secure/secure_heap.c                | 2 +-
 portable/GCC/ARM_CM55/secure/secure_heap.h                | 2 +-
 portable/GCC/ARM_CM55/secure/secure_init.c                | 2 +-
 portable/GCC/ARM_CM55/secure/secure_init.h                | 2 +-
 portable/GCC/ARM_CM55/secure/secure_port_macros.h         | 2 +-
 .../GCC/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.c     | 2 +-
 portable/GCC/ARM_CM55_NTZ/non_secure/port.c               | 2 +-
 portable/GCC/ARM_CM55_NTZ/non_secure/portasm.c            | 2 +-
 portable/GCC/ARM_CM55_NTZ/non_secure/portasm.h            | 2 +-
 portable/GCC/ARM_CM55_NTZ/non_secure/portmacro.h          | 2 +-
 portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h    | 2 +-
 portable/GCC/ARM_CM7/r0p1/port.c                          | 2 +-
 portable/GCC/ARM_CM7/r0p1/portmacro.h                     | 2 +-
 portable/GCC/ARM_CM85/non_secure/mpu_wrappers_v2_asm.c    | 2 +-
 portable/GCC/ARM_CM85/non_secure/port.c                   | 2 +-
 portable/GCC/ARM_CM85/non_secure/portasm.c                | 2 +-
 portable/GCC/ARM_CM85/non_secure/portasm.h                | 2 +-
 portable/GCC/ARM_CM85/non_secure/portmacro.h              | 2 +-
 portable/GCC/ARM_CM85/non_secure/portmacrocommon.h        | 2 +-
 portable/GCC/ARM_CM85/secure/secure_context.c             | 2 +-
 portable/GCC/ARM_CM85/secure/secure_context.h             | 2 +-
 portable/GCC/ARM_CM85/secure/secure_context_port.c        | 2 +-
 portable/GCC/ARM_CM85/secure/secure_heap.c                | 2 +-
 portable/GCC/ARM_CM85/secure/secure_heap.h                | 2 +-
 portable/GCC/ARM_CM85/secure/secure_init.c                | 2 +-
 portable/GCC/ARM_CM85/secure/secure_init.h                | 2 +-
 portable/GCC/ARM_CM85/secure/secure_port_macros.h         | 2 +-
 .../GCC/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.c     | 2 +-
 portable/GCC/ARM_CM85_NTZ/non_secure/port.c               | 2 +-
 portable/GCC/ARM_CM85_NTZ/non_secure/portasm.c            | 2 +-
 portable/GCC/ARM_CM85_NTZ/non_secure/portasm.h            | 2 +-
 portable/GCC/ARM_CM85_NTZ/non_secure/portmacro.h          | 2 +-
 portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h    | 2 +-
 portable/GCC/ARM_CR5/port.c                               | 2 +-
 portable/GCC/ARM_CR5/portASM.S                            | 2 +-
 portable/GCC/ARM_CR5/portmacro.h                          | 2 +-
 portable/GCC/ARM_CRx_No_GIC/port.c                        | 2 +-
 portable/GCC/ARM_CRx_No_GIC/portASM.S                     | 2 +-
 portable/GCC/ARM_CRx_No_GIC/portmacro.h                   | 2 +-
 portable/GCC/ATMega323/port.c                             | 2 +-
 portable/GCC/ATMega323/portmacro.h                        | 2 +-
 portable/GCC/AVR32_UC3/exception.S                        | 2 +-
 portable/GCC/AVR32_UC3/port.c                             | 2 +-
 portable/GCC/AVR32_UC3/portmacro.h                        | 2 +-
 portable/GCC/CORTUS_APS3/port.c                           | 2 +-
 portable/GCC/CORTUS_APS3/portmacro.h                      | 2 +-
 portable/GCC/ColdFire_V2/port.c                           | 2 +-
 portable/GCC/ColdFire_V2/portasm.S                        | 2 +-
 portable/GCC/ColdFire_V2/portmacro.h                      | 2 +-
 portable/GCC/H8S2329/port.c                               | 2 +-
 portable/GCC/H8S2329/portmacro.h                          | 2 +-
 portable/GCC/HCS12/port.c                                 | 2 +-
 portable/GCC/HCS12/portmacro.h                            | 2 +-
 portable/GCC/IA32_flat/ISR_Support.h                      | 2 +-
 portable/GCC/IA32_flat/port.c                             | 2 +-
 portable/GCC/IA32_flat/portASM.S                          | 2 +-
 portable/GCC/IA32_flat/portmacro.h                        | 2 +-
 portable/GCC/MSP430F449/port.c                            | 2 +-
 portable/GCC/MSP430F449/portmacro.h                       | 2 +-
 portable/GCC/MicroBlaze/port.c                            | 2 +-
 portable/GCC/MicroBlaze/portasm.s                         | 2 +-
 portable/GCC/MicroBlaze/portmacro.h                       | 2 +-
 portable/GCC/MicroBlazeV8/port.c                          | 2 +-
 portable/GCC/MicroBlazeV8/port_exceptions.c               | 2 +-
 portable/GCC/MicroBlazeV8/portasm.S                       | 2 +-
 portable/GCC/MicroBlazeV8/portmacro.h                     | 2 +-
 portable/GCC/MicroBlazeV9/port.c                          | 2 +-
 portable/GCC/MicroBlazeV9/port_exceptions.c               | 2 +-
 portable/GCC/MicroBlazeV9/portasm.S                       | 2 +-
 portable/GCC/MicroBlazeV9/portmacro.h                     | 2 +-
 portable/GCC/NiosII/port.c                                | 2 +-
 portable/GCC/NiosII/port_asm.S                            | 2 +-
 portable/GCC/NiosII/portmacro.h                           | 2 +-
 portable/GCC/PPC405_Xilinx/FPU_Macros.h                   | 2 +-
 portable/GCC/PPC405_Xilinx/port.c                         | 2 +-
 portable/GCC/PPC405_Xilinx/portasm.S                      | 2 +-
 portable/GCC/PPC405_Xilinx/portmacro.h                    | 2 +-
 portable/GCC/PPC440_Xilinx/FPU_Macros.h                   | 2 +-
 portable/GCC/PPC440_Xilinx/port.c                         | 2 +-
 portable/GCC/PPC440_Xilinx/portasm.S                      | 2 +-
 portable/GCC/PPC440_Xilinx/portmacro.h                    | 2 +-
 .../freertos_risc_v_chip_specific_extensions.h            | 2 +-
 .../freertos_risc_v_chip_specific_extensions.h            | 2 +-
 .../freertos_risc_v_chip_specific_extensions.h            | 2 +-
 .../freertos_risc_v_chip_specific_extensions.h            | 2 +-
 portable/GCC/RISC-V/port.c                                | 2 +-
 portable/GCC/RISC-V/portASM.S                             | 2 +-
 portable/GCC/RISC-V/portContext.h                         | 2 +-
 portable/GCC/RISC-V/portmacro.h                           | 2 +-
 portable/GCC/RL78/isr_support.h                           | 2 +-
 portable/GCC/RL78/port.c                                  | 2 +-
 portable/GCC/RL78/portasm.S                               | 2 +-
 portable/GCC/RL78/portmacro.h                             | 2 +-
 portable/GCC/RX100/port.c                                 | 2 +-
 portable/GCC/RX100/portmacro.h                            | 2 +-
 portable/GCC/RX200/port.c                                 | 2 +-
 portable/GCC/RX200/portmacro.h                            | 2 +-
 portable/GCC/RX600/port.c                                 | 2 +-
 portable/GCC/RX600/portmacro.h                            | 2 +-
 portable/GCC/RX600v2/port.c                               | 2 +-
 portable/GCC/RX600v2/portmacro.h                          | 2 +-
 portable/GCC/RX700v3_DPFPU/port.c                         | 2 +-
 portable/GCC/RX700v3_DPFPU/portmacro.h                    | 2 +-
 portable/GCC/STR75x/port.c                                | 2 +-
 portable/GCC/STR75x/portISR.c                             | 2 +-
 portable/GCC/STR75x/portmacro.h                           | 2 +-
 portable/GCC/TriCore_1782/port.c                          | 2 +-
 portable/GCC/TriCore_1782/portmacro.h                     | 2 +-
 portable/GCC/TriCore_1782/porttrap.c                      | 2 +-
 portable/IAR/78K0R/ISR_Support.h                          | 2 +-
 portable/IAR/78K0R/port.c                                 | 2 +-
 portable/IAR/78K0R/portasm.s26                            | 2 +-
 portable/IAR/78K0R/portmacro.h                            | 2 +-
 portable/IAR/ARM_CA5_No_GIC/port.c                        | 2 +-
 portable/IAR/ARM_CA5_No_GIC/portASM.h                     | 2 +-
 portable/IAR/ARM_CA5_No_GIC/portASM.s                     | 2 +-
 portable/IAR/ARM_CA5_No_GIC/portmacro.h                   | 2 +-
 portable/IAR/ARM_CA9/port.c                               | 2 +-
 portable/IAR/ARM_CA9/portASM.h                            | 2 +-
 portable/IAR/ARM_CA9/portASM.s                            | 2 +-
 portable/IAR/ARM_CA9/portmacro.h                          | 2 +-
 portable/IAR/ARM_CM0/port.c                               | 2 +-
 portable/IAR/ARM_CM0/portasm.s                            | 2 +-
 portable/IAR/ARM_CM0/portmacro.h                          | 2 +-
 portable/IAR/ARM_CM23/non_secure/mpu_wrappers_v2_asm.S    | 2 +-
 portable/IAR/ARM_CM23/non_secure/port.c                   | 2 +-
 portable/IAR/ARM_CM23/non_secure/portasm.h                | 2 +-
 portable/IAR/ARM_CM23/non_secure/portasm.s                | 2 +-
 portable/IAR/ARM_CM23/non_secure/portmacro.h              | 2 +-
 portable/IAR/ARM_CM23/non_secure/portmacrocommon.h        | 2 +-
 portable/IAR/ARM_CM23/secure/secure_context.c             | 2 +-
 portable/IAR/ARM_CM23/secure/secure_context.h             | 2 +-
 portable/IAR/ARM_CM23/secure/secure_context_port_asm.s    | 2 +-
 portable/IAR/ARM_CM23/secure/secure_heap.c                | 2 +-
 portable/IAR/ARM_CM23/secure/secure_heap.h                | 2 +-
 portable/IAR/ARM_CM23/secure/secure_init.c                | 2 +-
 portable/IAR/ARM_CM23/secure/secure_init.h                | 2 +-
 portable/IAR/ARM_CM23/secure/secure_port_macros.h         | 2 +-
 .../IAR/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.S     | 2 +-
 portable/IAR/ARM_CM23_NTZ/non_secure/port.c               | 2 +-
 portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h            | 2 +-
 portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s            | 2 +-
 portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h          | 2 +-
 portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h    | 2 +-
 portable/IAR/ARM_CM3/port.c                               | 2 +-
 portable/IAR/ARM_CM3/portasm.s                            | 2 +-
 portable/IAR/ARM_CM3/portmacro.h                          | 2 +-
 portable/IAR/ARM_CM33/non_secure/mpu_wrappers_v2_asm.S    | 2 +-
 portable/IAR/ARM_CM33/non_secure/port.c                   | 2 +-
 portable/IAR/ARM_CM33/non_secure/portasm.h                | 2 +-
 portable/IAR/ARM_CM33/non_secure/portasm.s                | 2 +-
 portable/IAR/ARM_CM33/non_secure/portmacro.h              | 2 +-
 portable/IAR/ARM_CM33/non_secure/portmacrocommon.h        | 2 +-
 portable/IAR/ARM_CM33/secure/secure_context.c             | 2 +-
 portable/IAR/ARM_CM33/secure/secure_context.h             | 2 +-
 portable/IAR/ARM_CM33/secure/secure_context_port_asm.s    | 2 +-
 portable/IAR/ARM_CM33/secure/secure_heap.c                | 2 +-
 portable/IAR/ARM_CM33/secure/secure_heap.h                | 2 +-
 portable/IAR/ARM_CM33/secure/secure_init.c                | 2 +-
 portable/IAR/ARM_CM33/secure/secure_init.h                | 2 +-
 portable/IAR/ARM_CM33/secure/secure_port_macros.h         | 2 +-
 .../IAR/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.S     | 2 +-
 portable/IAR/ARM_CM33_NTZ/non_secure/port.c               | 2 +-
 portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h            | 2 +-
 portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s            | 2 +-
 portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h          | 2 +-
 portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h    | 2 +-
 portable/IAR/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.S   | 2 +-
 portable/IAR/ARM_CM35P/non_secure/port.c                  | 2 +-
 portable/IAR/ARM_CM35P/non_secure/portasm.h               | 2 +-
 portable/IAR/ARM_CM35P/non_secure/portasm.s               | 2 +-
 portable/IAR/ARM_CM35P/non_secure/portmacro.h             | 2 +-
 portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h       | 2 +-
 portable/IAR/ARM_CM35P/secure/secure_context.c            | 2 +-
 portable/IAR/ARM_CM35P/secure/secure_context.h            | 2 +-
 portable/IAR/ARM_CM35P/secure/secure_context_port_asm.s   | 2 +-
 portable/IAR/ARM_CM35P/secure/secure_heap.c               | 2 +-
 portable/IAR/ARM_CM35P/secure/secure_heap.h               | 2 +-
 portable/IAR/ARM_CM35P/secure/secure_init.c               | 2 +-
 portable/IAR/ARM_CM35P/secure/secure_init.h               | 2 +-
 portable/IAR/ARM_CM35P/secure/secure_port_macros.h        | 2 +-
 .../IAR/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.S    | 2 +-
 portable/IAR/ARM_CM35P_NTZ/non_secure/port.c              | 2 +-
 portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.h           | 2 +-
 portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.s           | 2 +-
 portable/IAR/ARM_CM35P_NTZ/non_secure/portmacro.h         | 2 +-
 portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h   | 2 +-
 portable/IAR/ARM_CM4F/port.c                              | 2 +-
 portable/IAR/ARM_CM4F/portasm.s                           | 2 +-
 portable/IAR/ARM_CM4F/portmacro.h                         | 2 +-
 portable/IAR/ARM_CM4F_MPU/mpu_wrappers_v2_asm.S           | 2 +-
 portable/IAR/ARM_CM4F_MPU/port.c                          | 2 +-
 portable/IAR/ARM_CM4F_MPU/portasm.s                       | 2 +-
 portable/IAR/ARM_CM4F_MPU/portmacro.h                     | 2 +-
 portable/IAR/ARM_CM55/non_secure/mpu_wrappers_v2_asm.S    | 2 +-
 portable/IAR/ARM_CM55/non_secure/port.c                   | 2 +-
 portable/IAR/ARM_CM55/non_secure/portasm.h                | 2 +-
 portable/IAR/ARM_CM55/non_secure/portasm.s                | 2 +-
 portable/IAR/ARM_CM55/non_secure/portmacro.h              | 2 +-
 portable/IAR/ARM_CM55/non_secure/portmacrocommon.h        | 2 +-
 portable/IAR/ARM_CM55/secure/secure_context.c             | 2 +-
 portable/IAR/ARM_CM55/secure/secure_context.h             | 2 +-
 portable/IAR/ARM_CM55/secure/secure_context_port_asm.s    | 2 +-
 portable/IAR/ARM_CM55/secure/secure_heap.c                | 2 +-
 portable/IAR/ARM_CM55/secure/secure_heap.h                | 2 +-
 portable/IAR/ARM_CM55/secure/secure_init.c                | 2 +-
 portable/IAR/ARM_CM55/secure/secure_init.h                | 2 +-
 portable/IAR/ARM_CM55/secure/secure_port_macros.h         | 2 +-
 .../IAR/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.S     | 2 +-
 portable/IAR/ARM_CM55_NTZ/non_secure/port.c               | 2 +-
 portable/IAR/ARM_CM55_NTZ/non_secure/portasm.h            | 2 +-
 portable/IAR/ARM_CM55_NTZ/non_secure/portasm.s            | 2 +-
 portable/IAR/ARM_CM55_NTZ/non_secure/portmacro.h          | 2 +-
 portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h    | 2 +-
 portable/IAR/ARM_CM7/r0p1/port.c                          | 2 +-
 portable/IAR/ARM_CM7/r0p1/portasm.s                       | 2 +-
 portable/IAR/ARM_CM7/r0p1/portmacro.h                     | 2 +-
 portable/IAR/ARM_CM85/non_secure/mpu_wrappers_v2_asm.S    | 2 +-
 portable/IAR/ARM_CM85/non_secure/port.c                   | 2 +-
 portable/IAR/ARM_CM85/non_secure/portasm.h                | 2 +-
 portable/IAR/ARM_CM85/non_secure/portasm.s                | 2 +-
 portable/IAR/ARM_CM85/non_secure/portmacro.h              | 2 +-
 portable/IAR/ARM_CM85/non_secure/portmacrocommon.h        | 2 +-
 portable/IAR/ARM_CM85/secure/secure_context.c             | 2 +-
 portable/IAR/ARM_CM85/secure/secure_context.h             | 2 +-
 portable/IAR/ARM_CM85/secure/secure_context_port_asm.s    | 2 +-
 portable/IAR/ARM_CM85/secure/secure_heap.c                | 2 +-
 portable/IAR/ARM_CM85/secure/secure_heap.h                | 2 +-
 portable/IAR/ARM_CM85/secure/secure_init.c                | 2 +-
 portable/IAR/ARM_CM85/secure/secure_init.h                | 2 +-
 portable/IAR/ARM_CM85/secure/secure_port_macros.h         | 2 +-
 .../IAR/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.S     | 2 +-
 portable/IAR/ARM_CM85_NTZ/non_secure/port.c               | 2 +-
 portable/IAR/ARM_CM85_NTZ/non_secure/portasm.h            | 2 +-
 portable/IAR/ARM_CM85_NTZ/non_secure/portasm.s            | 2 +-
 portable/IAR/ARM_CM85_NTZ/non_secure/portmacro.h          | 2 +-
 portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h    | 2 +-
 portable/IAR/ARM_CRx_No_GIC/port.c                        | 2 +-
 portable/IAR/ARM_CRx_No_GIC/portASM.s                     | 2 +-
 portable/IAR/ARM_CRx_No_GIC/portmacro.h                   | 2 +-
 portable/IAR/ATMega323/port.c                             | 2 +-
 portable/IAR/ATMega323/portmacro.h                        | 2 +-
 portable/IAR/ATMega323/portmacro.s90                      | 2 +-
 portable/IAR/AVR32_UC3/exception.s82                      | 2 +-
 portable/IAR/AVR32_UC3/port.c                             | 2 +-
 portable/IAR/AVR32_UC3/portmacro.h                        | 2 +-
 portable/IAR/AVR32_UC3/read.c                             | 2 +-
 portable/IAR/AVR32_UC3/write.c                            | 2 +-
 portable/IAR/AVR_AVRDx/port.c                             | 2 +-
 portable/IAR/AVR_AVRDx/porthardware.h                     | 2 +-
 portable/IAR/AVR_AVRDx/portmacro.h                        | 2 +-
 portable/IAR/AVR_AVRDx/portmacro.s90                      | 2 +-
 portable/IAR/AVR_Mega0/port.c                             | 2 +-
 portable/IAR/AVR_Mega0/porthardware.h                     | 2 +-
 portable/IAR/AVR_Mega0/portmacro.h                        | 2 +-
 portable/IAR/AVR_Mega0/portmacro.s90                      | 2 +-
 portable/IAR/AtmelSAM7S64/ISR_Support.h                   | 2 +-
 portable/IAR/AtmelSAM7S64/port.c                          | 2 +-
 portable/IAR/AtmelSAM7S64/portasm.s79                     | 2 +-
 portable/IAR/AtmelSAM7S64/portmacro.h                     | 2 +-
 portable/IAR/AtmelSAM9XE/ISR_Support.h                    | 2 +-
 portable/IAR/AtmelSAM9XE/port.c                           | 2 +-
 portable/IAR/AtmelSAM9XE/portasm.s79                      | 2 +-
 portable/IAR/AtmelSAM9XE/portmacro.h                      | 2 +-
 portable/IAR/LPC2000/ISR_Support.h                        | 2 +-
 portable/IAR/LPC2000/port.c                               | 2 +-
 portable/IAR/LPC2000/portasm.s79                          | 2 +-
 portable/IAR/LPC2000/portmacro.h                          | 2 +-
 portable/IAR/MSP430/port.c                                | 2 +-
 portable/IAR/MSP430/portasm.h                             | 2 +-
 portable/IAR/MSP430/portext.s43                           | 2 +-
 portable/IAR/MSP430/portmacro.h                           | 2 +-
 portable/IAR/MSP430X/data_model.h                         | 2 +-
 portable/IAR/MSP430X/port.c                               | 2 +-
 portable/IAR/MSP430X/portext.s43                          | 2 +-
 portable/IAR/MSP430X/portmacro.h                          | 2 +-
 .../freertos_risc_v_chip_specific_extensions.h            | 2 +-
 portable/IAR/RISC-V/port.c                                | 2 +-
 portable/IAR/RISC-V/portASM.s                             | 2 +-
 portable/IAR/RISC-V/portContext.h                         | 2 +-
 portable/IAR/RISC-V/portmacro.h                           | 2 +-
 portable/IAR/RL78/port.c                                  | 2 +-
 portable/IAR/RL78/portasm.s                               | 2 +-
 portable/IAR/RL78/portmacro.h                             | 2 +-
 portable/IAR/RX100/port.c                                 | 2 +-
 portable/IAR/RX100/port_asm.s                             | 2 +-
 portable/IAR/RX100/portmacro.h                            | 2 +-
 portable/IAR/RX600/port.c                                 | 2 +-
 portable/IAR/RX600/port_asm.s                             | 2 +-
 portable/IAR/RX600/portmacro.h                            | 2 +-
 portable/IAR/RX700v3_DPFPU/port.c                         | 2 +-
 portable/IAR/RX700v3_DPFPU/portmacro.h                    | 2 +-
 portable/IAR/RXv2/port.c                                  | 2 +-
 portable/IAR/RXv2/port_asm.s                              | 2 +-
 portable/IAR/RXv2/portmacro.h                             | 2 +-
 portable/IAR/STR71x/ISR_Support.h                         | 2 +-
 portable/IAR/STR71x/port.c                                | 2 +-
 portable/IAR/STR71x/portasm.s79                           | 2 +-
 portable/IAR/STR71x/portmacro.h                           | 2 +-
 portable/IAR/STR75x/ISR_Support.h                         | 2 +-
 portable/IAR/STR75x/port.c                                | 2 +-
 portable/IAR/STR75x/portasm.s79                           | 2 +-
 portable/IAR/STR75x/portmacro.h                           | 2 +-
 portable/IAR/STR91x/ISR_Support.h                         | 2 +-
 portable/IAR/STR91x/port.c                                | 2 +-
 portable/IAR/STR91x/portasm.s79                           | 2 +-
 portable/IAR/STR91x/portmacro.h                           | 2 +-
 portable/IAR/V850ES/ISR_Support.h                         | 2 +-
 portable/IAR/V850ES/port.c                                | 2 +-
 portable/IAR/V850ES/portasm.s85                           | 2 +-
 portable/IAR/V850ES/portasm_Fx3.s85                       | 2 +-
 portable/IAR/V850ES/portasm_Hx2.s85                       | 2 +-
 portable/IAR/V850ES/portmacro.h                           | 2 +-
 portable/MPLAB/PIC18F/port.c                              | 2 +-
 portable/MPLAB/PIC18F/portmacro.h                         | 2 +-
 portable/MPLAB/PIC24_dsPIC/port.c                         | 2 +-
 portable/MPLAB/PIC24_dsPIC/portasm_PIC24.S                | 2 +-
 portable/MPLAB/PIC24_dsPIC/portasm_dsPIC.S                | 2 +-
 portable/MPLAB/PIC24_dsPIC/portmacro.h                    | 2 +-
 portable/MPLAB/PIC32MEC14xx/ISR_Support.h                 | 2 +-
 portable/MPLAB/PIC32MEC14xx/port.c                        | 2 +-
 portable/MPLAB/PIC32MEC14xx/port_asm.S                    | 2 +-
 portable/MPLAB/PIC32MEC14xx/portmacro.h                   | 2 +-
 portable/MPLAB/PIC32MX/ISR_Support.h                      | 2 +-
 portable/MPLAB/PIC32MX/port.c                             | 2 +-
 portable/MPLAB/PIC32MX/port_asm.S                         | 2 +-
 portable/MPLAB/PIC32MX/portmacro.h                        | 2 +-
 portable/MPLAB/PIC32MZ/ISR_Support.h                      | 2 +-
 portable/MPLAB/PIC32MZ/port.c                             | 2 +-
 portable/MPLAB/PIC32MZ/port_asm.S                         | 2 +-
 portable/MPLAB/PIC32MZ/portmacro.h                        | 2 +-
 portable/MSVC-MingW/port.c                                | 2 +-
 portable/MSVC-MingW/portmacro.h                           | 2 +-
 portable/MemMang/heap_1.c                                 | 2 +-
 portable/MemMang/heap_2.c                                 | 2 +-
 portable/MemMang/heap_3.c                                 | 2 +-
 portable/MemMang/heap_4.c                                 | 2 +-
 portable/MemMang/heap_5.c                                 | 2 +-
 portable/MikroC/ARM_CM4F/port.c                           | 2 +-
 portable/MikroC/ARM_CM4F/portmacro.h                      | 2 +-
 portable/Paradigm/Tern_EE/large_untested/port.c           | 2 +-
 portable/Paradigm/Tern_EE/large_untested/portasm.h        | 2 +-
 portable/Paradigm/Tern_EE/large_untested/portmacro.h      | 2 +-
 portable/Paradigm/Tern_EE/small/port.c                    | 2 +-
 portable/Paradigm/Tern_EE/small/portasm.h                 | 2 +-
 portable/Paradigm/Tern_EE/small/portmacro.h               | 2 +-
 portable/RVDS/ARM7_LPC21xx/port.c                         | 2 +-
 portable/RVDS/ARM7_LPC21xx/portASM.s                      | 2 +-
 portable/RVDS/ARM7_LPC21xx/portmacro.h                    | 2 +-
 portable/RVDS/ARM7_LPC21xx/portmacro.inc                  | 2 +-
 portable/RVDS/ARM_CA9/port.c                              | 2 +-
 portable/RVDS/ARM_CA9/portASM.s                           | 2 +-
 portable/RVDS/ARM_CA9/portmacro.h                         | 2 +-
 portable/RVDS/ARM_CA9/portmacro.inc                       | 2 +-
 portable/RVDS/ARM_CM0/port.c                              | 2 +-
 portable/RVDS/ARM_CM0/portmacro.h                         | 2 +-
 portable/RVDS/ARM_CM3/port.c                              | 2 +-
 portable/RVDS/ARM_CM3/portmacro.h                         | 2 +-
 portable/RVDS/ARM_CM4F/port.c                             | 2 +-
 portable/RVDS/ARM_CM4F/portmacro.h                        | 2 +-
 portable/RVDS/ARM_CM4_MPU/mpu_wrappers_v2_asm.c           | 2 +-
 portable/RVDS/ARM_CM4_MPU/port.c                          | 2 +-
 portable/RVDS/ARM_CM4_MPU/portmacro.h                     | 2 +-
 portable/RVDS/ARM_CM7/r0p1/port.c                         | 2 +-
 portable/RVDS/ARM_CM7/r0p1/portmacro.h                    | 2 +-
 portable/Renesas/RX100/port.c                             | 2 +-
 portable/Renesas/RX100/port_asm.src                       | 2 +-
 portable/Renesas/RX100/portmacro.h                        | 2 +-
 portable/Renesas/RX200/port.c                             | 2 +-
 portable/Renesas/RX200/port_asm.src                       | 2 +-
 portable/Renesas/RX200/portmacro.h                        | 2 +-
 portable/Renesas/RX600/port.c                             | 2 +-
 portable/Renesas/RX600/port_asm.src                       | 2 +-
 portable/Renesas/RX600/portmacro.h                        | 2 +-
 portable/Renesas/RX600v2/port.c                           | 2 +-
 portable/Renesas/RX600v2/port_asm.src                     | 2 +-
 portable/Renesas/RX600v2/portmacro.h                      | 2 +-
 portable/Renesas/RX700v3_DPFPU/port.c                     | 2 +-
 portable/Renesas/RX700v3_DPFPU/port_asm.src               | 2 +-
 portable/Renesas/RX700v3_DPFPU/portmacro.h                | 2 +-
 portable/Renesas/SH2A_FPU/ISR_Support.inc                 | 2 +-
 portable/Renesas/SH2A_FPU/port.c                          | 2 +-
 portable/Renesas/SH2A_FPU/portasm.src                     | 2 +-
 portable/Renesas/SH2A_FPU/portmacro.h                     | 2 +-
 portable/Rowley/MSP430F449/port.c                         | 2 +-
 portable/Rowley/MSP430F449/portasm.h                      | 2 +-
 portable/Rowley/MSP430F449/portext.asm                    | 2 +-
 portable/Rowley/MSP430F449/portmacro.h                    | 2 +-
 portable/SDCC/Cygnal/port.c                               | 2 +-
 portable/SDCC/Cygnal/portmacro.h                          | 2 +-
 portable/Softune/MB91460/__STD_LIB_sbrk.c                 | 2 +-
 portable/Softune/MB91460/port.c                           | 2 +-
 portable/Softune/MB91460/portmacro.h                      | 2 +-
 portable/Softune/MB96340/__STD_LIB_sbrk.c                 | 2 +-
 portable/Softune/MB96340/port.c                           | 2 +-
 portable/Softune/MB96340/portmacro.h                      | 2 +-
 portable/Tasking/ARM_CM4F/port.c                          | 2 +-
 portable/Tasking/ARM_CM4F/port_asm.asm                    | 2 +-
 portable/Tasking/ARM_CM4F/portmacro.h                     | 2 +-
 portable/ThirdParty/GCC/ATmega/port.c                     | 2 +-
 portable/ThirdParty/GCC/ATmega/portmacro.h                | 2 +-
 portable/ThirdParty/GCC/Posix/utils/wait_for_event.c      | 2 +-
 portable/ThirdParty/GCC/Posix/utils/wait_for_event.h      | 2 +-
 .../ThirdParty/GCC/RP2040/include/freertos_sdk_config.h   | 2 +-
 portable/ThirdParty/GCC/RP2040/include/portmacro.h        | 2 +-
 portable/ThirdParty/GCC/RP2040/include/rp2040_config.h    | 2 +-
 portable/ThirdParty/GCC/RP2040/port.c                     | 2 +-
 .../GCC/Xtensa_ESP32/include/FreeRTOSConfig_arch.h        | 2 +-
 portable/ThirdParty/GCC/Xtensa_ESP32/include/portmacro.h  | 2 +-
 portable/ThirdParty/GCC/Xtensa_ESP32/port.c               | 2 +-
 portable/ThirdParty/XCC/Xtensa/port.c                     | 2 +-
 portable/ThirdParty/XCC/Xtensa/portasm.S                  | 2 +-
 portable/ThirdParty/XCC/Xtensa/portbenchmark.h            | 2 +-
 portable/ThirdParty/XCC/Xtensa/portclib.c                 | 2 +-
 portable/ThirdParty/XCC/Xtensa/portmacro.h                | 2 +-
 portable/ThirdParty/XCC/Xtensa/porttrace.h                | 2 +-
 portable/ThirdParty/XCC/Xtensa/xtensa_api.h               | 2 +-
 portable/ThirdParty/XCC/Xtensa/xtensa_config.h            | 2 +-
 portable/ThirdParty/XCC/Xtensa/xtensa_context.S           | 2 +-
 portable/ThirdParty/XCC/Xtensa/xtensa_context.h           | 2 +-
 portable/ThirdParty/XCC/Xtensa/xtensa_init.c              | 2 +-
 portable/ThirdParty/XCC/Xtensa/xtensa_intr.c              | 2 +-
 portable/ThirdParty/XCC/Xtensa/xtensa_intr_asm.S          | 2 +-
 portable/ThirdParty/XCC/Xtensa/xtensa_overlay_os_hook.c   | 2 +-
 portable/ThirdParty/XCC/Xtensa/xtensa_rtos.h              | 2 +-
 portable/ThirdParty/XCC/Xtensa/xtensa_timer.h             | 2 +-
 portable/ThirdParty/XCC/Xtensa/xtensa_vectors.S           | 2 +-
 portable/WizC/PIC18/Drivers/Tick/Tick.c                   | 2 +-
 portable/WizC/PIC18/Drivers/Tick/isrTick.c                | 2 +-
 portable/WizC/PIC18/addFreeRTOS.h                         | 2 +-
 portable/WizC/PIC18/port.c                                | 2 +-
 portable/WizC/PIC18/portmacro.h                           | 2 +-
 portable/oWatcom/16BitDOS/Flsh186/port.c                  | 2 +-
 portable/oWatcom/16BitDOS/Flsh186/portmacro.h             | 2 +-
 portable/oWatcom/16BitDOS/PC/port.c                       | 2 +-
 portable/oWatcom/16BitDOS/PC/portmacro.h                  | 2 +-
 portable/oWatcom/16BitDOS/common/portasm.h                | 2 +-
 portable/oWatcom/16BitDOS/common/portcomn.c               | 2 +-
 queue.c                                                   | 2 +-
 stream_buffer.c                                           | 2 +-
 tasks.c                                                   | 2 +-
 timers.c                                                  | 2 +-
 647 files changed, 652 insertions(+), 648 deletions(-)

diff --git a/.github/scripts/kernel_checker.py b/.github/scripts/kernel_checker.py
index 0e8556350..130841abb 100755
--- a/.github/scripts/kernel_checker.py
+++ b/.github/scripts/kernel_checker.py
@@ -1,7 +1,7 @@
 #!/usr/bin/env python3
 #/*
 # * FreeRTOS Kernel <DEVELOPMENT BRANCH>
-# * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+# * Copyright (C) 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 # *
 # * SPDX-License-Identifier: MIT
 # *
@@ -108,7 +108,7 @@ KERNEL_THIRD_PARTY_PATTERNS = [
 KERNEL_HEADER = [
     '/*\n',
     ' * FreeRTOS Kernel <DEVELOPMENT BRANCH>\n',
-    ' * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n',
+    ' * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.\n',
     ' *\n',
     ' * SPDX-License-Identifier: MIT\n',
     ' *\n',
@@ -135,12 +135,16 @@ KERNEL_HEADER = [
     ' */\n',
 ]
 
+
+FREERTOS_COPYRIGHT_REGEX = r"^(;|#)?( *(\/\*|\*|#|\/\/))? Copyright \(C\) 20\d\d Amazon.com, Inc. or its affiliates. All Rights Reserved\.( \*\/)?$"
+
 def main():
     parser = HeaderChecker.configArgParser()
     args   = parser.parse_args()
 
     # Configure the checks then run
     checker = HeaderChecker(KERNEL_HEADER,
+                            copyright_regex=FREERTOS_COPYRIGHT_REGEX,
                             ignored_files=KERNEL_IGNORED_FILES,
                             ignored_ext=KERNEL_IGNORED_EXTENSIONS,
                             ignored_patterns=KERNEL_IGNORED_PATTERNS,
diff --git a/croutine.c b/croutine.c
index 4d210b732..86256bcd1 100644
--- a/croutine.c
+++ b/croutine.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/event_groups.c b/event_groups.c
index 3fac0d9c8..2118f0474 100644
--- a/event_groups.c
+++ b/event_groups.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/examples/cmake_example/main.c b/examples/cmake_example/main.c
index 4825f2d19..f357b2f91 100644
--- a/examples/cmake_example/main.c
+++ b/examples/cmake_example/main.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/examples/coverity/FreeRTOSConfig.h b/examples/coverity/FreeRTOSConfig.h
index 4d957872d..06b0f9a28 100644
--- a/examples/coverity/FreeRTOSConfig.h
+++ b/examples/coverity/FreeRTOSConfig.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/examples/template_configuration/FreeRTOSConfig.h b/examples/template_configuration/FreeRTOSConfig.h
index 2c807142c..d7203f2e6 100644
--- a/examples/template_configuration/FreeRTOSConfig.h
+++ b/examples/template_configuration/FreeRTOSConfig.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/include/FreeRTOS.h b/include/FreeRTOS.h
index b993893e7..ecf82dc5a 100644
--- a/include/FreeRTOS.h
+++ b/include/FreeRTOS.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/include/StackMacros.h b/include/StackMacros.h
index b8ed92e31..d0c624733 100644
--- a/include/StackMacros.h
+++ b/include/StackMacros.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/include/atomic.h b/include/atomic.h
index ef487b4ab..335a77fdf 100644
--- a/include/atomic.h
+++ b/include/atomic.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/include/croutine.h b/include/croutine.h
index 7888863e5..25f4caec8 100644
--- a/include/croutine.h
+++ b/include/croutine.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/include/deprecated_definitions.h b/include/deprecated_definitions.h
index b046711a6..edc0f2246 100644
--- a/include/deprecated_definitions.h
+++ b/include/deprecated_definitions.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/include/event_groups.h b/include/event_groups.h
index d66ab262c..f5652114e 100644
--- a/include/event_groups.h
+++ b/include/event_groups.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/include/list.h b/include/list.h
index 9b96ab137..a9aace44e 100644
--- a/include/list.h
+++ b/include/list.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/include/message_buffer.h b/include/message_buffer.h
index d693d28cc..fb5a6c04a 100644
--- a/include/message_buffer.h
+++ b/include/message_buffer.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/include/mpu_prototypes.h b/include/mpu_prototypes.h
index 94ab59611..d51f6e1d2 100644
--- a/include/mpu_prototypes.h
+++ b/include/mpu_prototypes.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/include/mpu_syscall_numbers.h b/include/mpu_syscall_numbers.h
index 47913c998..7c625a78d 100644
--- a/include/mpu_syscall_numbers.h
+++ b/include/mpu_syscall_numbers.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/include/mpu_wrappers.h b/include/mpu_wrappers.h
index 6117bbbcc..19c5e779f 100644
--- a/include/mpu_wrappers.h
+++ b/include/mpu_wrappers.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/include/newlib-freertos.h b/include/newlib-freertos.h
index a65e62e8e..4414d24ad 100644
--- a/include/newlib-freertos.h
+++ b/include/newlib-freertos.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/include/picolibc-freertos.h b/include/picolibc-freertos.h
index ef6b7570c..5cf01afa8 100644
--- a/include/picolibc-freertos.h
+++ b/include/picolibc-freertos.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/include/portable.h b/include/portable.h
index ee7b49350..a20a3daa3 100644
--- a/include/portable.h
+++ b/include/portable.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/include/projdefs.h b/include/projdefs.h
index 370285d30..04ec47fae 100644
--- a/include/projdefs.h
+++ b/include/projdefs.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/include/queue.h b/include/queue.h
index e892ed3d5..a2cd3ffe9 100644
--- a/include/queue.h
+++ b/include/queue.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/include/semphr.h b/include/semphr.h
index e93b708c5..8977acadb 100644
--- a/include/semphr.h
+++ b/include/semphr.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/include/stack_macros.h b/include/stack_macros.h
index bd9ec2770..c1018b68a 100644
--- a/include/stack_macros.h
+++ b/include/stack_macros.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/include/stdint.readme b/include/stdint.readme
index 5c9d192ec..bfe3bb6f8 100644
--- a/include/stdint.readme
+++ b/include/stdint.readme
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/include/stream_buffer.h b/include/stream_buffer.h
index 2ff584eaf..d3ed9aff4 100644
--- a/include/stream_buffer.h
+++ b/include/stream_buffer.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/include/task.h b/include/task.h
index 33d9d4c07..08452a9b2 100644
--- a/include/task.h
+++ b/include/task.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/include/timers.h b/include/timers.h
index 34dc406e4..19d55d535 100644
--- a/include/timers.h
+++ b/include/timers.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/list.c b/list.c
index 0ac5b04a0..87fa7aba3 100644
--- a/list.c
+++ b/list.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ARMv8M/copy_files.py b/portable/ARMv8M/copy_files.py
index 3609c67ef..023fb68e0 100644
--- a/portable/ARMv8M/copy_files.py
+++ b/portable/ARMv8M/copy_files.py
@@ -1,6 +1,6 @@
 #/*
 # * FreeRTOS Kernel <DEVELOPMENT BRANCH>
-# * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+# * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 # *
 # * SPDX-License-Identifier: MIT
 # *
diff --git a/portable/ARMv8M/non_secure/port.c b/portable/ARMv8M/non_secure/port.c
index 6d88b637f..7171a72bf 100644
--- a/portable/ARMv8M/non_secure/port.c
+++ b/portable/ARMv8M/non_secure/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/mpu_wrappers_v2_asm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/mpu_wrappers_v2_asm.c
index e67f3cbae..9c829b540 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/mpu_wrappers_v2_asm.c
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/mpu_wrappers_v2_asm.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portasm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portasm.c
index f8b37b691..8df9bfa7c 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portasm.c
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portasm.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h
index d17f3eb28..b08fa71b0 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/mpu_wrappers_v2_asm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/mpu_wrappers_v2_asm.c
index e67f3cbae..9c829b540 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/mpu_wrappers_v2_asm.c
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/mpu_wrappers_v2_asm.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portasm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portasm.c
index 5fde8342e..82bff509e 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portasm.c
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portasm.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h
index d17f3eb28..b08fa71b0 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/mpu_wrappers_v2_asm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/mpu_wrappers_v2_asm.c
index 4cb310afd..170d10fcc 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/mpu_wrappers_v2_asm.c
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/mpu_wrappers_v2_asm.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c
index 16c598ad7..1ee04b76d 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h
index 90448b6cc..8d3555bb4 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/mpu_wrappers_v2_asm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/mpu_wrappers_v2_asm.c
index 4cb310afd..170d10fcc 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/mpu_wrappers_v2_asm.c
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/mpu_wrappers_v2_asm.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c
index 76ba642a0..56866d6b6 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h
index 90448b6cc..8d3555bb4 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM35P/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM35P/portmacro.h
index 11fc04273..0eb0a6592 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM35P/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM35P/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM55/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM55/portmacro.h
index 7b011b5b5..2797dbd53 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM55/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM55/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM85/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM85/portmacro.h
index a6fda8a88..2d5cac90e 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM85/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM85/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/mpu_wrappers_v2_asm.S b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/mpu_wrappers_v2_asm.S
index 419df5b1e..8ea2f5c78 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/mpu_wrappers_v2_asm.S
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/mpu_wrappers_v2_asm.S
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portasm.s b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portasm.s
index 06c761090..6817abd7a 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portasm.s
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portasm.s
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h
index 56d7398f5..667b58151 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/mpu_wrappers_v2_asm.S b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/mpu_wrappers_v2_asm.S
index 419df5b1e..8ea2f5c78 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/mpu_wrappers_v2_asm.S
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/mpu_wrappers_v2_asm.S
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portasm.s b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portasm.s
index d4487dfac..bfe9eee4b 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portasm.s
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portasm.s
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h
index 56d7398f5..667b58151 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/mpu_wrappers_v2_asm.S b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/mpu_wrappers_v2_asm.S
index 80d5a1c63..a69845eda 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/mpu_wrappers_v2_asm.S
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/mpu_wrappers_v2_asm.S
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s
index d8f1b1d9a..418c5f887 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h
index 890f3ea96..eeb14d86f 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/mpu_wrappers_v2_asm.S b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/mpu_wrappers_v2_asm.S
index 80d5a1c63..a69845eda 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/mpu_wrappers_v2_asm.S
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/mpu_wrappers_v2_asm.S
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s
index 7cf467d22..44f662646 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h
index 59a44193f..acb4748a2 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM35P/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM35P/portmacro.h
index 468d14311..0dcac8d4d 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM35P/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM35P/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM55/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM55/portmacro.h
index 1338d25be..92dc75fd1 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM55/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM55/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM85/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM85/portmacro.h
index cffcb20d9..02f67453a 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM85/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM85/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ARMv8M/non_secure/portasm.h b/portable/ARMv8M/non_secure/portasm.h
index ecd86b97f..bd5a2bfca 100644
--- a/portable/ARMv8M/non_secure/portasm.h
+++ b/portable/ARMv8M/non_secure/portasm.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ARMv8M/non_secure/portmacrocommon.h b/portable/ARMv8M/non_secure/portmacrocommon.h
index 672b0dbdc..3cf65761f 100644
--- a/portable/ARMv8M/non_secure/portmacrocommon.h
+++ b/portable/ARMv8M/non_secure/portmacrocommon.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ARMv8M/secure/context/portable/GCC/ARM_CM23/secure_context_port.c b/portable/ARMv8M/secure/context/portable/GCC/ARM_CM23/secure_context_port.c
index 2d9eeeaf8..32559ad04 100644
--- a/portable/ARMv8M/secure/context/portable/GCC/ARM_CM23/secure_context_port.c
+++ b/portable/ARMv8M/secure/context/portable/GCC/ARM_CM23/secure_context_port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ARMv8M/secure/context/portable/GCC/ARM_CM33/secure_context_port.c b/portable/ARMv8M/secure/context/portable/GCC/ARM_CM33/secure_context_port.c
index 13520870b..2d3d9439d 100644
--- a/portable/ARMv8M/secure/context/portable/GCC/ARM_CM33/secure_context_port.c
+++ b/portable/ARMv8M/secure/context/portable/GCC/ARM_CM33/secure_context_port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ARMv8M/secure/context/portable/IAR/ARM_CM23/secure_context_port_asm.s b/portable/ARMv8M/secure/context/portable/IAR/ARM_CM23/secure_context_port_asm.s
index f7c5d19d2..f70e89115 100644
--- a/portable/ARMv8M/secure/context/portable/IAR/ARM_CM23/secure_context_port_asm.s
+++ b/portable/ARMv8M/secure/context/portable/IAR/ARM_CM23/secure_context_port_asm.s
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ARMv8M/secure/context/portable/IAR/ARM_CM33/secure_context_port_asm.s b/portable/ARMv8M/secure/context/portable/IAR/ARM_CM33/secure_context_port_asm.s
index 400bd0107..27a8f3933 100644
--- a/portable/ARMv8M/secure/context/portable/IAR/ARM_CM33/secure_context_port_asm.s
+++ b/portable/ARMv8M/secure/context/portable/IAR/ARM_CM33/secure_context_port_asm.s
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ARMv8M/secure/context/secure_context.c b/portable/ARMv8M/secure/context/secure_context.c
index 7d2171996..72fb3862c 100644
--- a/portable/ARMv8M/secure/context/secure_context.c
+++ b/portable/ARMv8M/secure/context/secure_context.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ARMv8M/secure/context/secure_context.h b/portable/ARMv8M/secure/context/secure_context.h
index 0bf776198..e36a8e430 100644
--- a/portable/ARMv8M/secure/context/secure_context.h
+++ b/portable/ARMv8M/secure/context/secure_context.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ARMv8M/secure/heap/secure_heap.c b/portable/ARMv8M/secure/heap/secure_heap.c
index 1ec3bdbdb..4fa6a2ffa 100644
--- a/portable/ARMv8M/secure/heap/secure_heap.c
+++ b/portable/ARMv8M/secure/heap/secure_heap.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ARMv8M/secure/heap/secure_heap.h b/portable/ARMv8M/secure/heap/secure_heap.h
index c13590f86..0e84a9d9d 100644
--- a/portable/ARMv8M/secure/heap/secure_heap.h
+++ b/portable/ARMv8M/secure/heap/secure_heap.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ARMv8M/secure/init/secure_init.c b/portable/ARMv8M/secure/init/secure_init.c
index b89c5f644..c50d37668 100644
--- a/portable/ARMv8M/secure/init/secure_init.c
+++ b/portable/ARMv8M/secure/init/secure_init.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ARMv8M/secure/init/secure_init.h b/portable/ARMv8M/secure/init/secure_init.h
index 21daeda6b..ebe04900f 100644
--- a/portable/ARMv8M/secure/init/secure_init.h
+++ b/portable/ARMv8M/secure/init/secure_init.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ARMv8M/secure/macros/secure_port_macros.h b/portable/ARMv8M/secure/macros/secure_port_macros.h
index 304913b8d..a70da2c65 100644
--- a/portable/ARMv8M/secure/macros/secure_port_macros.h
+++ b/portable/ARMv8M/secure/macros/secure_port_macros.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/BCC/16BitDOS/Flsh186/port.c b/portable/BCC/16BitDOS/Flsh186/port.c
index 66b8b7b7b..14b1f6f5a 100644
--- a/portable/BCC/16BitDOS/Flsh186/port.c
+++ b/portable/BCC/16BitDOS/Flsh186/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/BCC/16BitDOS/Flsh186/prtmacro.h b/portable/BCC/16BitDOS/Flsh186/prtmacro.h
index 295c0bc73..b1b5c26eb 100644
--- a/portable/BCC/16BitDOS/Flsh186/prtmacro.h
+++ b/portable/BCC/16BitDOS/Flsh186/prtmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/BCC/16BitDOS/PC/port.c b/portable/BCC/16BitDOS/PC/port.c
index 6940b1a67..0c1c0644e 100644
--- a/portable/BCC/16BitDOS/PC/port.c
+++ b/portable/BCC/16BitDOS/PC/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/BCC/16BitDOS/PC/prtmacro.h b/portable/BCC/16BitDOS/PC/prtmacro.h
index 5fb4ed6a4..d24431806 100644
--- a/portable/BCC/16BitDOS/PC/prtmacro.h
+++ b/portable/BCC/16BitDOS/PC/prtmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/BCC/16BitDOS/common/portasm.h b/portable/BCC/16BitDOS/common/portasm.h
index e53d257c8..3e3acf0bd 100644
--- a/portable/BCC/16BitDOS/common/portasm.h
+++ b/portable/BCC/16BitDOS/common/portasm.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/BCC/16BitDOS/common/portcomn.c b/portable/BCC/16BitDOS/common/portcomn.c
index 69ab45ba7..0e1bca1ab 100644
--- a/portable/BCC/16BitDOS/common/portcomn.c
+++ b/portable/BCC/16BitDOS/common/portcomn.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/CCS/ARM_CM3/port.c b/portable/CCS/ARM_CM3/port.c
index e8b0f0d74..5ed26c2d2 100644
--- a/portable/CCS/ARM_CM3/port.c
+++ b/portable/CCS/ARM_CM3/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/CCS/ARM_CM3/portasm.asm b/portable/CCS/ARM_CM3/portasm.asm
index 2773c6ca2..483a66b49 100644
--- a/portable/CCS/ARM_CM3/portasm.asm
+++ b/portable/CCS/ARM_CM3/portasm.asm
@@ -1,6 +1,6 @@
 ;/*
 ; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
-; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 ; *
 ; * SPDX-License-Identifier: MIT
 ; *
diff --git a/portable/CCS/ARM_CM3/portmacro.h b/portable/CCS/ARM_CM3/portmacro.h
index 29d9bc033..336a5ff1e 100644
--- a/portable/CCS/ARM_CM3/portmacro.h
+++ b/portable/CCS/ARM_CM3/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/CCS/ARM_CM4F/port.c b/portable/CCS/ARM_CM4F/port.c
index c3a9b0f4b..1ac7a59e6 100644
--- a/portable/CCS/ARM_CM4F/port.c
+++ b/portable/CCS/ARM_CM4F/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/CCS/ARM_CM4F/portasm.asm b/portable/CCS/ARM_CM4F/portasm.asm
index eb75533bd..81d0a71c2 100644
--- a/portable/CCS/ARM_CM4F/portasm.asm
+++ b/portable/CCS/ARM_CM4F/portasm.asm
@@ -1,6 +1,6 @@
 ;/*
 ; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
-; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 ; *
 ; * SPDX-License-Identifier: MIT
 ; *
diff --git a/portable/CCS/ARM_CM4F/portmacro.h b/portable/CCS/ARM_CM4F/portmacro.h
index f4405ab1b..47dcc5aba 100644
--- a/portable/CCS/ARM_CM4F/portmacro.h
+++ b/portable/CCS/ARM_CM4F/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/CCS/ARM_Cortex-R4/port.c b/portable/CCS/ARM_Cortex-R4/port.c
index 6c63a5a71..853248f40 100644
--- a/portable/CCS/ARM_Cortex-R4/port.c
+++ b/portable/CCS/ARM_Cortex-R4/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/CCS/ARM_Cortex-R4/portASM.asm b/portable/CCS/ARM_Cortex-R4/portASM.asm
index 927df85d4..f20af2941 100644
--- a/portable/CCS/ARM_Cortex-R4/portASM.asm
+++ b/portable/CCS/ARM_Cortex-R4/portASM.asm
@@ -1,6 +1,6 @@
 ;/*
 ; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
-; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 ; *
 ; * SPDX-License-Identifier: MIT
 ; *
diff --git a/portable/CCS/ARM_Cortex-R4/portmacro.h b/portable/CCS/ARM_Cortex-R4/portmacro.h
index 07c1827cb..644f13a3c 100644
--- a/portable/CCS/ARM_Cortex-R4/portmacro.h
+++ b/portable/CCS/ARM_Cortex-R4/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/CCS/MSP430X/data_model.h b/portable/CCS/MSP430X/data_model.h
index 186caa65d..b199175c0 100644
--- a/portable/CCS/MSP430X/data_model.h
+++ b/portable/CCS/MSP430X/data_model.h
@@ -1,6 +1,6 @@
 ;/*
 ; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
-; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 ; *
 ; * SPDX-License-Identifier: MIT
 ; *
diff --git a/portable/CCS/MSP430X/port.c b/portable/CCS/MSP430X/port.c
index c691b5d9f..186fb2cdd 100644
--- a/portable/CCS/MSP430X/port.c
+++ b/portable/CCS/MSP430X/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/CCS/MSP430X/portext.asm b/portable/CCS/MSP430X/portext.asm
index 9fe306e94..dbbcec0aa 100644
--- a/portable/CCS/MSP430X/portext.asm
+++ b/portable/CCS/MSP430X/portext.asm
@@ -1,6 +1,6 @@
 ;/*
 ; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
-; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 ; *
 ; * SPDX-License-Identifier: MIT
 ; *
diff --git a/portable/CCS/MSP430X/portmacro.h b/portable/CCS/MSP430X/portmacro.h
index 064b0503a..91e2b9c5b 100644
--- a/portable/CCS/MSP430X/portmacro.h
+++ b/portable/CCS/MSP430X/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/CodeWarrior/ColdFire_V1/port.c b/portable/CodeWarrior/ColdFire_V1/port.c
index d9831384e..520c62ac5 100644
--- a/portable/CodeWarrior/ColdFire_V1/port.c
+++ b/portable/CodeWarrior/ColdFire_V1/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/CodeWarrior/ColdFire_V1/portasm.S b/portable/CodeWarrior/ColdFire_V1/portasm.S
index 75f55f037..1f00348af 100644
--- a/portable/CodeWarrior/ColdFire_V1/portasm.S
+++ b/portable/CodeWarrior/ColdFire_V1/portasm.S
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/CodeWarrior/ColdFire_V1/portmacro.h b/portable/CodeWarrior/ColdFire_V1/portmacro.h
index a98093d72..2f224d30b 100644
--- a/portable/CodeWarrior/ColdFire_V1/portmacro.h
+++ b/portable/CodeWarrior/ColdFire_V1/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/CodeWarrior/ColdFire_V2/port.c b/portable/CodeWarrior/ColdFire_V2/port.c
index 5bca650fe..64b2d078b 100644
--- a/portable/CodeWarrior/ColdFire_V2/port.c
+++ b/portable/CodeWarrior/ColdFire_V2/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/CodeWarrior/ColdFire_V2/portasm.S b/portable/CodeWarrior/ColdFire_V2/portasm.S
index bdffce5e8..66f429259 100644
--- a/portable/CodeWarrior/ColdFire_V2/portasm.S
+++ b/portable/CodeWarrior/ColdFire_V2/portasm.S
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/CodeWarrior/ColdFire_V2/portmacro.h b/portable/CodeWarrior/ColdFire_V2/portmacro.h
index a59dff9dd..55b38ae3a 100644
--- a/portable/CodeWarrior/ColdFire_V2/portmacro.h
+++ b/portable/CodeWarrior/ColdFire_V2/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/CodeWarrior/HCS12/port.c b/portable/CodeWarrior/HCS12/port.c
index e4876125a..2d564cd66 100644
--- a/portable/CodeWarrior/HCS12/port.c
+++ b/portable/CodeWarrior/HCS12/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/CodeWarrior/HCS12/portmacro.h b/portable/CodeWarrior/HCS12/portmacro.h
index d0d0a140e..8e6eb1057 100644
--- a/portable/CodeWarrior/HCS12/portmacro.h
+++ b/portable/CodeWarrior/HCS12/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/Common/mpu_wrappers.c b/portable/Common/mpu_wrappers.c
index d25618c67..03ca77c68 100644
--- a/portable/Common/mpu_wrappers.c
+++ b/portable/Common/mpu_wrappers.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/Common/mpu_wrappers_v2.c b/portable/Common/mpu_wrappers_v2.c
index af9e9f129..99256e3fa 100644
--- a/portable/Common/mpu_wrappers_v2.c
+++ b/portable/Common/mpu_wrappers_v2.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM7_AT91FR40008/port.c b/portable/GCC/ARM7_AT91FR40008/port.c
index 86cc6e0f3..30bbb9f48 100644
--- a/portable/GCC/ARM7_AT91FR40008/port.c
+++ b/portable/GCC/ARM7_AT91FR40008/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM7_AT91FR40008/portISR.c b/portable/GCC/ARM7_AT91FR40008/portISR.c
index 9df08b0c9..b4ddcc06d 100644
--- a/portable/GCC/ARM7_AT91FR40008/portISR.c
+++ b/portable/GCC/ARM7_AT91FR40008/portISR.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM7_AT91FR40008/portmacro.h b/portable/GCC/ARM7_AT91FR40008/portmacro.h
index f0975cc3e..4dbadab3f 100644
--- a/portable/GCC/ARM7_AT91FR40008/portmacro.h
+++ b/portable/GCC/ARM7_AT91FR40008/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM7_AT91SAM7S/port.c b/portable/GCC/ARM7_AT91SAM7S/port.c
index f1afce707..6750c45ee 100644
--- a/portable/GCC/ARM7_AT91SAM7S/port.c
+++ b/portable/GCC/ARM7_AT91SAM7S/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM7_AT91SAM7S/portISR.c b/portable/GCC/ARM7_AT91SAM7S/portISR.c
index 917c67ddb..9e5ff6c98 100644
--- a/portable/GCC/ARM7_AT91SAM7S/portISR.c
+++ b/portable/GCC/ARM7_AT91SAM7S/portISR.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM7_AT91SAM7S/portmacro.h b/portable/GCC/ARM7_AT91SAM7S/portmacro.h
index 5b78481e3..3f2242fa9 100644
--- a/portable/GCC/ARM7_AT91SAM7S/portmacro.h
+++ b/portable/GCC/ARM7_AT91SAM7S/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM7_LPC2000/port.c b/portable/GCC/ARM7_LPC2000/port.c
index 53df1a534..2c8268af5 100644
--- a/portable/GCC/ARM7_LPC2000/port.c
+++ b/portable/GCC/ARM7_LPC2000/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM7_LPC2000/portISR.c b/portable/GCC/ARM7_LPC2000/portISR.c
index 704907f9d..4255df713 100644
--- a/portable/GCC/ARM7_LPC2000/portISR.c
+++ b/portable/GCC/ARM7_LPC2000/portISR.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM7_LPC2000/portmacro.h b/portable/GCC/ARM7_LPC2000/portmacro.h
index b96c6fa8b..8e82cc08e 100644
--- a/portable/GCC/ARM7_LPC2000/portmacro.h
+++ b/portable/GCC/ARM7_LPC2000/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM7_LPC23xx/port.c b/portable/GCC/ARM7_LPC23xx/port.c
index 4ec34eb3f..8ac1df709 100644
--- a/portable/GCC/ARM7_LPC23xx/port.c
+++ b/portable/GCC/ARM7_LPC23xx/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM7_LPC23xx/portISR.c b/portable/GCC/ARM7_LPC23xx/portISR.c
index 4fc549aca..1cf7c7dae 100644
--- a/portable/GCC/ARM7_LPC23xx/portISR.c
+++ b/portable/GCC/ARM7_LPC23xx/portISR.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM7_LPC23xx/portmacro.h b/portable/GCC/ARM7_LPC23xx/portmacro.h
index 5b78481e3..3f2242fa9 100644
--- a/portable/GCC/ARM7_LPC23xx/portmacro.h
+++ b/portable/GCC/ARM7_LPC23xx/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_AARCH64/port.c b/portable/GCC/ARM_AARCH64/port.c
index 8c2af2dc7..5b52dadda 100644
--- a/portable/GCC/ARM_AARCH64/port.c
+++ b/portable/GCC/ARM_AARCH64/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_AARCH64/portASM.S b/portable/GCC/ARM_AARCH64/portASM.S
index c98cadb11..e684755bf 100644
--- a/portable/GCC/ARM_AARCH64/portASM.S
+++ b/portable/GCC/ARM_AARCH64/portASM.S
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_AARCH64/portmacro.h b/portable/GCC/ARM_AARCH64/portmacro.h
index 2c9da1c60..04d34fc4f 100644
--- a/portable/GCC/ARM_AARCH64/portmacro.h
+++ b/portable/GCC/ARM_AARCH64/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_AARCH64_SRE/port.c b/portable/GCC/ARM_AARCH64_SRE/port.c
index 8731054bc..1c96c0efd 100644
--- a/portable/GCC/ARM_AARCH64_SRE/port.c
+++ b/portable/GCC/ARM_AARCH64_SRE/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_AARCH64_SRE/portASM.S b/portable/GCC/ARM_AARCH64_SRE/portASM.S
index d779890bc..ed3c031d0 100644
--- a/portable/GCC/ARM_AARCH64_SRE/portASM.S
+++ b/portable/GCC/ARM_AARCH64_SRE/portASM.S
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_AARCH64_SRE/portmacro.h b/portable/GCC/ARM_AARCH64_SRE/portmacro.h
index cbe0b54dd..efbcdfae6 100644
--- a/portable/GCC/ARM_AARCH64_SRE/portmacro.h
+++ b/portable/GCC/ARM_AARCH64_SRE/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CA9/port.c b/portable/GCC/ARM_CA9/port.c
index 4e4189d36..79b60a933 100644
--- a/portable/GCC/ARM_CA9/port.c
+++ b/portable/GCC/ARM_CA9/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CA9/portASM.S b/portable/GCC/ARM_CA9/portASM.S
index 55baabbd3..6efeaba77 100644
--- a/portable/GCC/ARM_CA9/portASM.S
+++ b/portable/GCC/ARM_CA9/portASM.S
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CA9/portmacro.h b/portable/GCC/ARM_CA9/portmacro.h
index bd9b36dd9..0e213cf5d 100644
--- a/portable/GCC/ARM_CA9/portmacro.h
+++ b/portable/GCC/ARM_CA9/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM0/port.c b/portable/GCC/ARM_CM0/port.c
index 53bc33a41..41b14fa3b 100644
--- a/portable/GCC/ARM_CM0/port.c
+++ b/portable/GCC/ARM_CM0/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM0/portmacro.h b/portable/GCC/ARM_CM0/portmacro.h
index 3c55b5d0c..6331020bd 100644
--- a/portable/GCC/ARM_CM0/portmacro.h
+++ b/portable/GCC/ARM_CM0/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM23/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM23/non_secure/mpu_wrappers_v2_asm.c
index e67f3cbae..9c829b540 100644
--- a/portable/GCC/ARM_CM23/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM23/non_secure/mpu_wrappers_v2_asm.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM23/non_secure/port.c b/portable/GCC/ARM_CM23/non_secure/port.c
index 6d88b637f..7171a72bf 100644
--- a/portable/GCC/ARM_CM23/non_secure/port.c
+++ b/portable/GCC/ARM_CM23/non_secure/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM23/non_secure/portasm.c b/portable/GCC/ARM_CM23/non_secure/portasm.c
index f8b37b691..8df9bfa7c 100644
--- a/portable/GCC/ARM_CM23/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM23/non_secure/portasm.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM23/non_secure/portasm.h b/portable/GCC/ARM_CM23/non_secure/portasm.h
index ecd86b97f..bd5a2bfca 100644
--- a/portable/GCC/ARM_CM23/non_secure/portasm.h
+++ b/portable/GCC/ARM_CM23/non_secure/portasm.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM23/non_secure/portmacro.h b/portable/GCC/ARM_CM23/non_secure/portmacro.h
index d17f3eb28..b08fa71b0 100644
--- a/portable/GCC/ARM_CM23/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM23/non_secure/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h
index 672b0dbdc..3cf65761f 100644
--- a/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM23/secure/secure_context.c b/portable/GCC/ARM_CM23/secure/secure_context.c
index 7d2171996..72fb3862c 100644
--- a/portable/GCC/ARM_CM23/secure/secure_context.c
+++ b/portable/GCC/ARM_CM23/secure/secure_context.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM23/secure/secure_context.h b/portable/GCC/ARM_CM23/secure/secure_context.h
index 0bf776198..e36a8e430 100644
--- a/portable/GCC/ARM_CM23/secure/secure_context.h
+++ b/portable/GCC/ARM_CM23/secure/secure_context.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM23/secure/secure_context_port.c b/portable/GCC/ARM_CM23/secure/secure_context_port.c
index 2d9eeeaf8..32559ad04 100644
--- a/portable/GCC/ARM_CM23/secure/secure_context_port.c
+++ b/portable/GCC/ARM_CM23/secure/secure_context_port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM23/secure/secure_heap.c b/portable/GCC/ARM_CM23/secure/secure_heap.c
index 1ec3bdbdb..4fa6a2ffa 100644
--- a/portable/GCC/ARM_CM23/secure/secure_heap.c
+++ b/portable/GCC/ARM_CM23/secure/secure_heap.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM23/secure/secure_heap.h b/portable/GCC/ARM_CM23/secure/secure_heap.h
index c13590f86..0e84a9d9d 100644
--- a/portable/GCC/ARM_CM23/secure/secure_heap.h
+++ b/portable/GCC/ARM_CM23/secure/secure_heap.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM23/secure/secure_init.c b/portable/GCC/ARM_CM23/secure/secure_init.c
index b89c5f644..c50d37668 100644
--- a/portable/GCC/ARM_CM23/secure/secure_init.c
+++ b/portable/GCC/ARM_CM23/secure/secure_init.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM23/secure/secure_init.h b/portable/GCC/ARM_CM23/secure/secure_init.h
index 21daeda6b..ebe04900f 100644
--- a/portable/GCC/ARM_CM23/secure/secure_init.h
+++ b/portable/GCC/ARM_CM23/secure/secure_init.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM23/secure/secure_port_macros.h b/portable/GCC/ARM_CM23/secure/secure_port_macros.h
index 304913b8d..a70da2c65 100644
--- a/portable/GCC/ARM_CM23/secure/secure_port_macros.h
+++ b/portable/GCC/ARM_CM23/secure/secure_port_macros.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.c
index e67f3cbae..9c829b540 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
index 6d88b637f..7171a72bf 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c b/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c
index 5fde8342e..82bff509e 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.h b/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.h
index ecd86b97f..bd5a2bfca 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.h
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h b/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h
index d17f3eb28..b08fa71b0 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h
index 672b0dbdc..3cf65761f 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM3/port.c b/portable/GCC/ARM_CM3/port.c
index 8ce6fa6c4..1a9c9b072 100644
--- a/portable/GCC/ARM_CM3/port.c
+++ b/portable/GCC/ARM_CM3/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM3/portmacro.h b/portable/GCC/ARM_CM3/portmacro.h
index 5d91d2139..757e44fd9 100644
--- a/portable/GCC/ARM_CM3/portmacro.h
+++ b/portable/GCC/ARM_CM3/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM33/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM33/non_secure/mpu_wrappers_v2_asm.c
index 4cb310afd..170d10fcc 100644
--- a/portable/GCC/ARM_CM33/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM33/non_secure/mpu_wrappers_v2_asm.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM33/non_secure/port.c b/portable/GCC/ARM_CM33/non_secure/port.c
index 6d88b637f..7171a72bf 100644
--- a/portable/GCC/ARM_CM33/non_secure/port.c
+++ b/portable/GCC/ARM_CM33/non_secure/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM33/non_secure/portasm.c b/portable/GCC/ARM_CM33/non_secure/portasm.c
index 16c598ad7..1ee04b76d 100644
--- a/portable/GCC/ARM_CM33/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM33/non_secure/portasm.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM33/non_secure/portasm.h b/portable/GCC/ARM_CM33/non_secure/portasm.h
index ecd86b97f..bd5a2bfca 100644
--- a/portable/GCC/ARM_CM33/non_secure/portasm.h
+++ b/portable/GCC/ARM_CM33/non_secure/portasm.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM33/non_secure/portmacro.h b/portable/GCC/ARM_CM33/non_secure/portmacro.h
index 90448b6cc..8d3555bb4 100644
--- a/portable/GCC/ARM_CM33/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM33/non_secure/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h
index 672b0dbdc..3cf65761f 100644
--- a/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM33/secure/secure_context.c b/portable/GCC/ARM_CM33/secure/secure_context.c
index 7d2171996..72fb3862c 100644
--- a/portable/GCC/ARM_CM33/secure/secure_context.c
+++ b/portable/GCC/ARM_CM33/secure/secure_context.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM33/secure/secure_context.h b/portable/GCC/ARM_CM33/secure/secure_context.h
index 0bf776198..e36a8e430 100644
--- a/portable/GCC/ARM_CM33/secure/secure_context.h
+++ b/portable/GCC/ARM_CM33/secure/secure_context.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM33/secure/secure_context_port.c b/portable/GCC/ARM_CM33/secure/secure_context_port.c
index 13520870b..2d3d9439d 100644
--- a/portable/GCC/ARM_CM33/secure/secure_context_port.c
+++ b/portable/GCC/ARM_CM33/secure/secure_context_port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM33/secure/secure_heap.c b/portable/GCC/ARM_CM33/secure/secure_heap.c
index 1ec3bdbdb..4fa6a2ffa 100644
--- a/portable/GCC/ARM_CM33/secure/secure_heap.c
+++ b/portable/GCC/ARM_CM33/secure/secure_heap.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM33/secure/secure_heap.h b/portable/GCC/ARM_CM33/secure/secure_heap.h
index c13590f86..0e84a9d9d 100644
--- a/portable/GCC/ARM_CM33/secure/secure_heap.h
+++ b/portable/GCC/ARM_CM33/secure/secure_heap.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM33/secure/secure_init.c b/portable/GCC/ARM_CM33/secure/secure_init.c
index b89c5f644..c50d37668 100644
--- a/portable/GCC/ARM_CM33/secure/secure_init.c
+++ b/portable/GCC/ARM_CM33/secure/secure_init.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM33/secure/secure_init.h b/portable/GCC/ARM_CM33/secure/secure_init.h
index 21daeda6b..ebe04900f 100644
--- a/portable/GCC/ARM_CM33/secure/secure_init.h
+++ b/portable/GCC/ARM_CM33/secure/secure_init.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM33/secure/secure_port_macros.h b/portable/GCC/ARM_CM33/secure/secure_port_macros.h
index 304913b8d..a70da2c65 100644
--- a/portable/GCC/ARM_CM33/secure/secure_port_macros.h
+++ b/portable/GCC/ARM_CM33/secure/secure_port_macros.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.c
index 4cb310afd..170d10fcc 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
index 6d88b637f..7171a72bf 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c b/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c
index 76ba642a0..56866d6b6 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h b/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h
index ecd86b97f..bd5a2bfca 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h b/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h
index 90448b6cc..8d3555bb4 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h
index 672b0dbdc..3cf65761f 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.c
index 4cb310afd..170d10fcc 100644
--- a/portable/GCC/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM35P/non_secure/port.c b/portable/GCC/ARM_CM35P/non_secure/port.c
index 6d88b637f..7171a72bf 100644
--- a/portable/GCC/ARM_CM35P/non_secure/port.c
+++ b/portable/GCC/ARM_CM35P/non_secure/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM35P/non_secure/portasm.c b/portable/GCC/ARM_CM35P/non_secure/portasm.c
index 16c598ad7..1ee04b76d 100644
--- a/portable/GCC/ARM_CM35P/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM35P/non_secure/portasm.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM35P/non_secure/portasm.h b/portable/GCC/ARM_CM35P/non_secure/portasm.h
index ecd86b97f..bd5a2bfca 100644
--- a/portable/GCC/ARM_CM35P/non_secure/portasm.h
+++ b/portable/GCC/ARM_CM35P/non_secure/portasm.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM35P/non_secure/portmacro.h b/portable/GCC/ARM_CM35P/non_secure/portmacro.h
index 11fc04273..0eb0a6592 100644
--- a/portable/GCC/ARM_CM35P/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM35P/non_secure/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h
index 672b0dbdc..3cf65761f 100644
--- a/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM35P/secure/secure_context.c b/portable/GCC/ARM_CM35P/secure/secure_context.c
index 7d2171996..72fb3862c 100644
--- a/portable/GCC/ARM_CM35P/secure/secure_context.c
+++ b/portable/GCC/ARM_CM35P/secure/secure_context.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM35P/secure/secure_context.h b/portable/GCC/ARM_CM35P/secure/secure_context.h
index 0bf776198..e36a8e430 100644
--- a/portable/GCC/ARM_CM35P/secure/secure_context.h
+++ b/portable/GCC/ARM_CM35P/secure/secure_context.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM35P/secure/secure_context_port.c b/portable/GCC/ARM_CM35P/secure/secure_context_port.c
index 13520870b..2d3d9439d 100644
--- a/portable/GCC/ARM_CM35P/secure/secure_context_port.c
+++ b/portable/GCC/ARM_CM35P/secure/secure_context_port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM35P/secure/secure_heap.c b/portable/GCC/ARM_CM35P/secure/secure_heap.c
index 1ec3bdbdb..4fa6a2ffa 100644
--- a/portable/GCC/ARM_CM35P/secure/secure_heap.c
+++ b/portable/GCC/ARM_CM35P/secure/secure_heap.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM35P/secure/secure_heap.h b/portable/GCC/ARM_CM35P/secure/secure_heap.h
index c13590f86..0e84a9d9d 100644
--- a/portable/GCC/ARM_CM35P/secure/secure_heap.h
+++ b/portable/GCC/ARM_CM35P/secure/secure_heap.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM35P/secure/secure_init.c b/portable/GCC/ARM_CM35P/secure/secure_init.c
index b89c5f644..c50d37668 100644
--- a/portable/GCC/ARM_CM35P/secure/secure_init.c
+++ b/portable/GCC/ARM_CM35P/secure/secure_init.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM35P/secure/secure_init.h b/portable/GCC/ARM_CM35P/secure/secure_init.h
index 21daeda6b..ebe04900f 100644
--- a/portable/GCC/ARM_CM35P/secure/secure_init.h
+++ b/portable/GCC/ARM_CM35P/secure/secure_init.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM35P/secure/secure_port_macros.h b/portable/GCC/ARM_CM35P/secure/secure_port_macros.h
index 304913b8d..a70da2c65 100644
--- a/portable/GCC/ARM_CM35P/secure/secure_port_macros.h
+++ b/portable/GCC/ARM_CM35P/secure/secure_port_macros.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.c
index 4cb310afd..170d10fcc 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c b/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
index 6d88b637f..7171a72bf 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.c b/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.c
index 76ba642a0..56866d6b6 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.h b/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.h
index ecd86b97f..bd5a2bfca 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.h
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacro.h b/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacro.h
index 11fc04273..0eb0a6592 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
index 672b0dbdc..3cf65761f 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM3_MPU/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM3_MPU/mpu_wrappers_v2_asm.c
index 6b76b376c..c95f72e8e 100644
--- a/portable/GCC/ARM_CM3_MPU/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM3_MPU/mpu_wrappers_v2_asm.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM3_MPU/port.c b/portable/GCC/ARM_CM3_MPU/port.c
index a8a92402e..fd7640017 100644
--- a/portable/GCC/ARM_CM3_MPU/port.c
+++ b/portable/GCC/ARM_CM3_MPU/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM3_MPU/portmacro.h b/portable/GCC/ARM_CM3_MPU/portmacro.h
index 5983c7912..7dd66e3ca 100644
--- a/portable/GCC/ARM_CM3_MPU/portmacro.h
+++ b/portable/GCC/ARM_CM3_MPU/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM4F/port.c b/portable/GCC/ARM_CM4F/port.c
index 3e5151bdc..ecd07f01c 100644
--- a/portable/GCC/ARM_CM4F/port.c
+++ b/portable/GCC/ARM_CM4F/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM4F/portmacro.h b/portable/GCC/ARM_CM4F/portmacro.h
index 40b2d03e9..6c97a1280 100644
--- a/portable/GCC/ARM_CM4F/portmacro.h
+++ b/portable/GCC/ARM_CM4F/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM4_MPU/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM4_MPU/mpu_wrappers_v2_asm.c
index 6b76b376c..c95f72e8e 100644
--- a/portable/GCC/ARM_CM4_MPU/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM4_MPU/mpu_wrappers_v2_asm.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM4_MPU/port.c b/portable/GCC/ARM_CM4_MPU/port.c
index f84ebd523..04ed7aa0e 100644
--- a/portable/GCC/ARM_CM4_MPU/port.c
+++ b/portable/GCC/ARM_CM4_MPU/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM4_MPU/portmacro.h b/portable/GCC/ARM_CM4_MPU/portmacro.h
index 4b941e6fa..d9677a72b 100644
--- a/portable/GCC/ARM_CM4_MPU/portmacro.h
+++ b/portable/GCC/ARM_CM4_MPU/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM55/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM55/non_secure/mpu_wrappers_v2_asm.c
index 4cb310afd..170d10fcc 100644
--- a/portable/GCC/ARM_CM55/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM55/non_secure/mpu_wrappers_v2_asm.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM55/non_secure/port.c b/portable/GCC/ARM_CM55/non_secure/port.c
index 6d88b637f..7171a72bf 100644
--- a/portable/GCC/ARM_CM55/non_secure/port.c
+++ b/portable/GCC/ARM_CM55/non_secure/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM55/non_secure/portasm.c b/portable/GCC/ARM_CM55/non_secure/portasm.c
index 16c598ad7..1ee04b76d 100644
--- a/portable/GCC/ARM_CM55/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM55/non_secure/portasm.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM55/non_secure/portasm.h b/portable/GCC/ARM_CM55/non_secure/portasm.h
index ecd86b97f..bd5a2bfca 100644
--- a/portable/GCC/ARM_CM55/non_secure/portasm.h
+++ b/portable/GCC/ARM_CM55/non_secure/portasm.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM55/non_secure/portmacro.h b/portable/GCC/ARM_CM55/non_secure/portmacro.h
index 7b011b5b5..2797dbd53 100644
--- a/portable/GCC/ARM_CM55/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM55/non_secure/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h
index 672b0dbdc..3cf65761f 100644
--- a/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM55/secure/secure_context.c b/portable/GCC/ARM_CM55/secure/secure_context.c
index 7d2171996..72fb3862c 100644
--- a/portable/GCC/ARM_CM55/secure/secure_context.c
+++ b/portable/GCC/ARM_CM55/secure/secure_context.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM55/secure/secure_context.h b/portable/GCC/ARM_CM55/secure/secure_context.h
index 0bf776198..e36a8e430 100644
--- a/portable/GCC/ARM_CM55/secure/secure_context.h
+++ b/portable/GCC/ARM_CM55/secure/secure_context.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM55/secure/secure_context_port.c b/portable/GCC/ARM_CM55/secure/secure_context_port.c
index 13520870b..2d3d9439d 100644
--- a/portable/GCC/ARM_CM55/secure/secure_context_port.c
+++ b/portable/GCC/ARM_CM55/secure/secure_context_port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM55/secure/secure_heap.c b/portable/GCC/ARM_CM55/secure/secure_heap.c
index 1ec3bdbdb..4fa6a2ffa 100644
--- a/portable/GCC/ARM_CM55/secure/secure_heap.c
+++ b/portable/GCC/ARM_CM55/secure/secure_heap.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM55/secure/secure_heap.h b/portable/GCC/ARM_CM55/secure/secure_heap.h
index c13590f86..0e84a9d9d 100644
--- a/portable/GCC/ARM_CM55/secure/secure_heap.h
+++ b/portable/GCC/ARM_CM55/secure/secure_heap.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM55/secure/secure_init.c b/portable/GCC/ARM_CM55/secure/secure_init.c
index b89c5f644..c50d37668 100644
--- a/portable/GCC/ARM_CM55/secure/secure_init.c
+++ b/portable/GCC/ARM_CM55/secure/secure_init.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM55/secure/secure_init.h b/portable/GCC/ARM_CM55/secure/secure_init.h
index 21daeda6b..ebe04900f 100644
--- a/portable/GCC/ARM_CM55/secure/secure_init.h
+++ b/portable/GCC/ARM_CM55/secure/secure_init.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM55/secure/secure_port_macros.h b/portable/GCC/ARM_CM55/secure/secure_port_macros.h
index 304913b8d..a70da2c65 100644
--- a/portable/GCC/ARM_CM55/secure/secure_port_macros.h
+++ b/portable/GCC/ARM_CM55/secure/secure_port_macros.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.c
index 4cb310afd..170d10fcc 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/port.c b/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
index 6d88b637f..7171a72bf 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.c b/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.c
index 76ba642a0..56866d6b6 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.h b/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.h
index ecd86b97f..bd5a2bfca 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.h
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/portmacro.h b/portable/GCC/ARM_CM55_NTZ/non_secure/portmacro.h
index 7b011b5b5..2797dbd53 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h
index 672b0dbdc..3cf65761f 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM7/r0p1/port.c b/portable/GCC/ARM_CM7/r0p1/port.c
index 3070445ab..220be503f 100644
--- a/portable/GCC/ARM_CM7/r0p1/port.c
+++ b/portable/GCC/ARM_CM7/r0p1/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM7/r0p1/portmacro.h b/portable/GCC/ARM_CM7/r0p1/portmacro.h
index aa2199c25..2d2edacdf 100644
--- a/portable/GCC/ARM_CM7/r0p1/portmacro.h
+++ b/portable/GCC/ARM_CM7/r0p1/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM85/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM85/non_secure/mpu_wrappers_v2_asm.c
index 4cb310afd..170d10fcc 100644
--- a/portable/GCC/ARM_CM85/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM85/non_secure/mpu_wrappers_v2_asm.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM85/non_secure/port.c b/portable/GCC/ARM_CM85/non_secure/port.c
index 6d88b637f..7171a72bf 100644
--- a/portable/GCC/ARM_CM85/non_secure/port.c
+++ b/portable/GCC/ARM_CM85/non_secure/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM85/non_secure/portasm.c b/portable/GCC/ARM_CM85/non_secure/portasm.c
index 16c598ad7..1ee04b76d 100644
--- a/portable/GCC/ARM_CM85/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM85/non_secure/portasm.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM85/non_secure/portasm.h b/portable/GCC/ARM_CM85/non_secure/portasm.h
index ecd86b97f..bd5a2bfca 100644
--- a/portable/GCC/ARM_CM85/non_secure/portasm.h
+++ b/portable/GCC/ARM_CM85/non_secure/portasm.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM85/non_secure/portmacro.h b/portable/GCC/ARM_CM85/non_secure/portmacro.h
index a6fda8a88..2d5cac90e 100644
--- a/portable/GCC/ARM_CM85/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM85/non_secure/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h
index 672b0dbdc..3cf65761f 100644
--- a/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM85/secure/secure_context.c b/portable/GCC/ARM_CM85/secure/secure_context.c
index 7d2171996..72fb3862c 100644
--- a/portable/GCC/ARM_CM85/secure/secure_context.c
+++ b/portable/GCC/ARM_CM85/secure/secure_context.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM85/secure/secure_context.h b/portable/GCC/ARM_CM85/secure/secure_context.h
index 0bf776198..e36a8e430 100644
--- a/portable/GCC/ARM_CM85/secure/secure_context.h
+++ b/portable/GCC/ARM_CM85/secure/secure_context.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM85/secure/secure_context_port.c b/portable/GCC/ARM_CM85/secure/secure_context_port.c
index 13520870b..2d3d9439d 100644
--- a/portable/GCC/ARM_CM85/secure/secure_context_port.c
+++ b/portable/GCC/ARM_CM85/secure/secure_context_port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM85/secure/secure_heap.c b/portable/GCC/ARM_CM85/secure/secure_heap.c
index 1ec3bdbdb..4fa6a2ffa 100644
--- a/portable/GCC/ARM_CM85/secure/secure_heap.c
+++ b/portable/GCC/ARM_CM85/secure/secure_heap.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM85/secure/secure_heap.h b/portable/GCC/ARM_CM85/secure/secure_heap.h
index c13590f86..0e84a9d9d 100644
--- a/portable/GCC/ARM_CM85/secure/secure_heap.h
+++ b/portable/GCC/ARM_CM85/secure/secure_heap.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM85/secure/secure_init.c b/portable/GCC/ARM_CM85/secure/secure_init.c
index b89c5f644..c50d37668 100644
--- a/portable/GCC/ARM_CM85/secure/secure_init.c
+++ b/portable/GCC/ARM_CM85/secure/secure_init.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM85/secure/secure_init.h b/portable/GCC/ARM_CM85/secure/secure_init.h
index 21daeda6b..ebe04900f 100644
--- a/portable/GCC/ARM_CM85/secure/secure_init.h
+++ b/portable/GCC/ARM_CM85/secure/secure_init.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM85/secure/secure_port_macros.h b/portable/GCC/ARM_CM85/secure/secure_port_macros.h
index 304913b8d..a70da2c65 100644
--- a/portable/GCC/ARM_CM85/secure/secure_port_macros.h
+++ b/portable/GCC/ARM_CM85/secure/secure_port_macros.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.c
index 4cb310afd..170d10fcc 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/port.c b/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
index 6d88b637f..7171a72bf 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.c b/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.c
index 76ba642a0..56866d6b6 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.h b/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.h
index ecd86b97f..bd5a2bfca 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.h
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/portmacro.h b/portable/GCC/ARM_CM85_NTZ/non_secure/portmacro.h
index a6fda8a88..2d5cac90e 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h
index 672b0dbdc..3cf65761f 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CR5/port.c b/portable/GCC/ARM_CR5/port.c
index 323ea916d..72658e8d7 100644
--- a/portable/GCC/ARM_CR5/port.c
+++ b/portable/GCC/ARM_CR5/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CR5/portASM.S b/portable/GCC/ARM_CR5/portASM.S
index c331057d6..e14cddd07 100644
--- a/portable/GCC/ARM_CR5/portASM.S
+++ b/portable/GCC/ARM_CR5/portASM.S
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CR5/portmacro.h b/portable/GCC/ARM_CR5/portmacro.h
index ff7337d15..568208a99 100644
--- a/portable/GCC/ARM_CR5/portmacro.h
+++ b/portable/GCC/ARM_CR5/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CRx_No_GIC/port.c b/portable/GCC/ARM_CRx_No_GIC/port.c
index ff2abf4ff..7294fb760 100644
--- a/portable/GCC/ARM_CRx_No_GIC/port.c
+++ b/portable/GCC/ARM_CRx_No_GIC/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CRx_No_GIC/portASM.S b/portable/GCC/ARM_CRx_No_GIC/portASM.S
index bfb15733a..960d46f7e 100644
--- a/portable/GCC/ARM_CRx_No_GIC/portASM.S
+++ b/portable/GCC/ARM_CRx_No_GIC/portASM.S
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ARM_CRx_No_GIC/portmacro.h b/portable/GCC/ARM_CRx_No_GIC/portmacro.h
index d88a0fd05..5a9ae265e 100644
--- a/portable/GCC/ARM_CRx_No_GIC/portmacro.h
+++ b/portable/GCC/ARM_CRx_No_GIC/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ATMega323/port.c b/portable/GCC/ATMega323/port.c
index 6d71a6da3..ff80a8b81 100644
--- a/portable/GCC/ATMega323/port.c
+++ b/portable/GCC/ATMega323/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ATMega323/portmacro.h b/portable/GCC/ATMega323/portmacro.h
index 275468b4c..6ed5e4295 100644
--- a/portable/GCC/ATMega323/portmacro.h
+++ b/portable/GCC/ATMega323/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/AVR32_UC3/exception.S b/portable/GCC/AVR32_UC3/exception.S
index 9d46489ae..4e1b29703 100644
--- a/portable/GCC/AVR32_UC3/exception.S
+++ b/portable/GCC/AVR32_UC3/exception.S
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT AND BSD-3-Clause
  *
diff --git a/portable/GCC/AVR32_UC3/port.c b/portable/GCC/AVR32_UC3/port.c
index 6e7257304..bd8b0bd2b 100644
--- a/portable/GCC/AVR32_UC3/port.c
+++ b/portable/GCC/AVR32_UC3/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT AND BSD-3-Clause
  *
diff --git a/portable/GCC/AVR32_UC3/portmacro.h b/portable/GCC/AVR32_UC3/portmacro.h
index 521c46397..d96a629b5 100644
--- a/portable/GCC/AVR32_UC3/portmacro.h
+++ b/portable/GCC/AVR32_UC3/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT AND BSD-3-Clause
  *
diff --git a/portable/GCC/CORTUS_APS3/port.c b/portable/GCC/CORTUS_APS3/port.c
index 30c3ca654..8ea06df16 100644
--- a/portable/GCC/CORTUS_APS3/port.c
+++ b/portable/GCC/CORTUS_APS3/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/CORTUS_APS3/portmacro.h b/portable/GCC/CORTUS_APS3/portmacro.h
index 91a18bc74..a18af0f6f 100644
--- a/portable/GCC/CORTUS_APS3/portmacro.h
+++ b/portable/GCC/CORTUS_APS3/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ColdFire_V2/port.c b/portable/GCC/ColdFire_V2/port.c
index f35126df8..e3bbb6b9e 100644
--- a/portable/GCC/ColdFire_V2/port.c
+++ b/portable/GCC/ColdFire_V2/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ColdFire_V2/portasm.S b/portable/GCC/ColdFire_V2/portasm.S
index a3c6aca05..4b746ca22 100644
--- a/portable/GCC/ColdFire_V2/portasm.S
+++ b/portable/GCC/ColdFire_V2/portasm.S
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/ColdFire_V2/portmacro.h b/portable/GCC/ColdFire_V2/portmacro.h
index 1a1b618d0..95381ab36 100644
--- a/portable/GCC/ColdFire_V2/portmacro.h
+++ b/portable/GCC/ColdFire_V2/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/H8S2329/port.c b/portable/GCC/H8S2329/port.c
index 7aec16f6c..f8693b37b 100644
--- a/portable/GCC/H8S2329/port.c
+++ b/portable/GCC/H8S2329/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/H8S2329/portmacro.h b/portable/GCC/H8S2329/portmacro.h
index 4b4e1cdac..a954d4335 100644
--- a/portable/GCC/H8S2329/portmacro.h
+++ b/portable/GCC/H8S2329/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/HCS12/port.c b/portable/GCC/HCS12/port.c
index e53a74a38..4355a3f11 100644
--- a/portable/GCC/HCS12/port.c
+++ b/portable/GCC/HCS12/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/HCS12/portmacro.h b/portable/GCC/HCS12/portmacro.h
index 37034a036..4d02ad54e 100644
--- a/portable/GCC/HCS12/portmacro.h
+++ b/portable/GCC/HCS12/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/IA32_flat/ISR_Support.h b/portable/GCC/IA32_flat/ISR_Support.h
index cecd6a152..545a8d236 100644
--- a/portable/GCC/IA32_flat/ISR_Support.h
+++ b/portable/GCC/IA32_flat/ISR_Support.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/IA32_flat/port.c b/portable/GCC/IA32_flat/port.c
index da1559416..207f6076b 100644
--- a/portable/GCC/IA32_flat/port.c
+++ b/portable/GCC/IA32_flat/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/IA32_flat/portASM.S b/portable/GCC/IA32_flat/portASM.S
index 4dac1af0b..c01b32bce 100644
--- a/portable/GCC/IA32_flat/portASM.S
+++ b/portable/GCC/IA32_flat/portASM.S
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/IA32_flat/portmacro.h b/portable/GCC/IA32_flat/portmacro.h
index fd07ee71d..085250e04 100644
--- a/portable/GCC/IA32_flat/portmacro.h
+++ b/portable/GCC/IA32_flat/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/MSP430F449/port.c b/portable/GCC/MSP430F449/port.c
index 488ad2d6f..48a1a7921 100644
--- a/portable/GCC/MSP430F449/port.c
+++ b/portable/GCC/MSP430F449/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/MSP430F449/portmacro.h b/portable/GCC/MSP430F449/portmacro.h
index f9470f096..de2014683 100644
--- a/portable/GCC/MSP430F449/portmacro.h
+++ b/portable/GCC/MSP430F449/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/MicroBlaze/port.c b/portable/GCC/MicroBlaze/port.c
index 2051e3e44..fb8b410be 100644
--- a/portable/GCC/MicroBlaze/port.c
+++ b/portable/GCC/MicroBlaze/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/MicroBlaze/portasm.s b/portable/GCC/MicroBlaze/portasm.s
index 344914893..b9c1dc8b3 100644
--- a/portable/GCC/MicroBlaze/portasm.s
+++ b/portable/GCC/MicroBlaze/portasm.s
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/MicroBlaze/portmacro.h b/portable/GCC/MicroBlaze/portmacro.h
index 8ddeb0ed0..a81e07cde 100644
--- a/portable/GCC/MicroBlaze/portmacro.h
+++ b/portable/GCC/MicroBlaze/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/MicroBlazeV8/port.c b/portable/GCC/MicroBlazeV8/port.c
index 5dced2b93..1557af645 100644
--- a/portable/GCC/MicroBlazeV8/port.c
+++ b/portable/GCC/MicroBlazeV8/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/MicroBlazeV8/port_exceptions.c b/portable/GCC/MicroBlazeV8/port_exceptions.c
index e2347732d..281a328b4 100644
--- a/portable/GCC/MicroBlazeV8/port_exceptions.c
+++ b/portable/GCC/MicroBlazeV8/port_exceptions.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/MicroBlazeV8/portasm.S b/portable/GCC/MicroBlazeV8/portasm.S
index d0e20515d..36829767d 100644
--- a/portable/GCC/MicroBlazeV8/portasm.S
+++ b/portable/GCC/MicroBlazeV8/portasm.S
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/MicroBlazeV8/portmacro.h b/portable/GCC/MicroBlazeV8/portmacro.h
index 7606850bc..d23214ea4 100644
--- a/portable/GCC/MicroBlazeV8/portmacro.h
+++ b/portable/GCC/MicroBlazeV8/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/MicroBlazeV9/port.c b/portable/GCC/MicroBlazeV9/port.c
index 25c9ac357..7a94ece00 100644
--- a/portable/GCC/MicroBlazeV9/port.c
+++ b/portable/GCC/MicroBlazeV9/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/MicroBlazeV9/port_exceptions.c b/portable/GCC/MicroBlazeV9/port_exceptions.c
index f89e47b0a..21dd28844 100644
--- a/portable/GCC/MicroBlazeV9/port_exceptions.c
+++ b/portable/GCC/MicroBlazeV9/port_exceptions.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/MicroBlazeV9/portasm.S b/portable/GCC/MicroBlazeV9/portasm.S
index 0a5e658d9..7480e76ed 100644
--- a/portable/GCC/MicroBlazeV9/portasm.S
+++ b/portable/GCC/MicroBlazeV9/portasm.S
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/MicroBlazeV9/portmacro.h b/portable/GCC/MicroBlazeV9/portmacro.h
index 497f9c514..1fb9c8259 100644
--- a/portable/GCC/MicroBlazeV9/portmacro.h
+++ b/portable/GCC/MicroBlazeV9/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/NiosII/port.c b/portable/GCC/NiosII/port.c
index e427b4fcc..974c7d121 100644
--- a/portable/GCC/NiosII/port.c
+++ b/portable/GCC/NiosII/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/NiosII/port_asm.S b/portable/GCC/NiosII/port_asm.S
index 80117e590..1485ab3fc 100644
--- a/portable/GCC/NiosII/port_asm.S
+++ b/portable/GCC/NiosII/port_asm.S
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/NiosII/portmacro.h b/portable/GCC/NiosII/portmacro.h
index b7b1d94a0..957f4db79 100644
--- a/portable/GCC/NiosII/portmacro.h
+++ b/portable/GCC/NiosII/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/PPC405_Xilinx/FPU_Macros.h b/portable/GCC/PPC405_Xilinx/FPU_Macros.h
index 9d7f96ff9..8446c9ae1 100644
--- a/portable/GCC/PPC405_Xilinx/FPU_Macros.h
+++ b/portable/GCC/PPC405_Xilinx/FPU_Macros.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/PPC405_Xilinx/port.c b/portable/GCC/PPC405_Xilinx/port.c
index a988dfc5e..c815cf265 100644
--- a/portable/GCC/PPC405_Xilinx/port.c
+++ b/portable/GCC/PPC405_Xilinx/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/PPC405_Xilinx/portasm.S b/portable/GCC/PPC405_Xilinx/portasm.S
index 49866e83e..db3e3b916 100644
--- a/portable/GCC/PPC405_Xilinx/portasm.S
+++ b/portable/GCC/PPC405_Xilinx/portasm.S
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/PPC405_Xilinx/portmacro.h b/portable/GCC/PPC405_Xilinx/portmacro.h
index fe0ca70cd..128d75c37 100644
--- a/portable/GCC/PPC405_Xilinx/portmacro.h
+++ b/portable/GCC/PPC405_Xilinx/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/PPC440_Xilinx/FPU_Macros.h b/portable/GCC/PPC440_Xilinx/FPU_Macros.h
index 9d7f96ff9..8446c9ae1 100644
--- a/portable/GCC/PPC440_Xilinx/FPU_Macros.h
+++ b/portable/GCC/PPC440_Xilinx/FPU_Macros.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/PPC440_Xilinx/port.c b/portable/GCC/PPC440_Xilinx/port.c
index d36e74300..a17c25918 100644
--- a/portable/GCC/PPC440_Xilinx/port.c
+++ b/portable/GCC/PPC440_Xilinx/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/PPC440_Xilinx/portasm.S b/portable/GCC/PPC440_Xilinx/portasm.S
index 49866e83e..db3e3b916 100644
--- a/portable/GCC/PPC440_Xilinx/portasm.S
+++ b/portable/GCC/PPC440_Xilinx/portasm.S
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/PPC440_Xilinx/portmacro.h b/portable/GCC/PPC440_Xilinx/portmacro.h
index fe0ca70cd..128d75c37 100644
--- a/portable/GCC/PPC440_Xilinx/portmacro.h
+++ b/portable/GCC/PPC440_Xilinx/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h b/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h
index df7be85fc..bbc231cf1 100644
--- a/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h
+++ b/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/RISC-V/chip_specific_extensions/RISCV_MTIME_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h b/portable/GCC/RISC-V/chip_specific_extensions/RISCV_MTIME_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h
index d4850841f..3be456cb4 100644
--- a/portable/GCC/RISC-V/chip_specific_extensions/RISCV_MTIME_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h
+++ b/portable/GCC/RISC-V/chip_specific_extensions/RISCV_MTIME_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/RISC-V/chip_specific_extensions/RISCV_no_extensions/freertos_risc_v_chip_specific_extensions.h b/portable/GCC/RISC-V/chip_specific_extensions/RISCV_no_extensions/freertos_risc_v_chip_specific_extensions.h
index 930e50354..9f93824bd 100644
--- a/portable/GCC/RISC-V/chip_specific_extensions/RISCV_no_extensions/freertos_risc_v_chip_specific_extensions.h
+++ b/portable/GCC/RISC-V/chip_specific_extensions/RISCV_no_extensions/freertos_risc_v_chip_specific_extensions.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h b/portable/GCC/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h
index bac15e4d8..d3e9ea992 100644
--- a/portable/GCC/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h
+++ b/portable/GCC/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/RISC-V/port.c b/portable/GCC/RISC-V/port.c
index e0648aa9c..0b7b336d7 100644
--- a/portable/GCC/RISC-V/port.c
+++ b/portable/GCC/RISC-V/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/RISC-V/portASM.S b/portable/GCC/RISC-V/portASM.S
index 9dde71f6a..12637b06f 100644
--- a/portable/GCC/RISC-V/portASM.S
+++ b/portable/GCC/RISC-V/portASM.S
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/RISC-V/portContext.h b/portable/GCC/RISC-V/portContext.h
index 7eb871a14..6baae753d 100644
--- a/portable/GCC/RISC-V/portContext.h
+++ b/portable/GCC/RISC-V/portContext.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/RISC-V/portmacro.h b/portable/GCC/RISC-V/portmacro.h
index 05386c3d9..a516a2467 100644
--- a/portable/GCC/RISC-V/portmacro.h
+++ b/portable/GCC/RISC-V/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/RL78/isr_support.h b/portable/GCC/RL78/isr_support.h
index 5f8e568bc..788718089 100644
--- a/portable/GCC/RL78/isr_support.h
+++ b/portable/GCC/RL78/isr_support.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/RL78/port.c b/portable/GCC/RL78/port.c
index 00ff398c8..7dad2b12b 100644
--- a/portable/GCC/RL78/port.c
+++ b/portable/GCC/RL78/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/RL78/portasm.S b/portable/GCC/RL78/portasm.S
index 18ac665ed..2f24db972 100644
--- a/portable/GCC/RL78/portasm.S
+++ b/portable/GCC/RL78/portasm.S
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/RL78/portmacro.h b/portable/GCC/RL78/portmacro.h
index eac8b1086..a91427257 100644
--- a/portable/GCC/RL78/portmacro.h
+++ b/portable/GCC/RL78/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/RX100/port.c b/portable/GCC/RX100/port.c
index e7f72bde6..854587d44 100644
--- a/portable/GCC/RX100/port.c
+++ b/portable/GCC/RX100/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/RX100/portmacro.h b/portable/GCC/RX100/portmacro.h
index 01bc3621b..c661c4c9c 100644
--- a/portable/GCC/RX100/portmacro.h
+++ b/portable/GCC/RX100/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/RX200/port.c b/portable/GCC/RX200/port.c
index 6261bc75c..e58c96d13 100644
--- a/portable/GCC/RX200/port.c
+++ b/portable/GCC/RX200/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/RX200/portmacro.h b/portable/GCC/RX200/portmacro.h
index aee4e4de3..a767299c5 100644
--- a/portable/GCC/RX200/portmacro.h
+++ b/portable/GCC/RX200/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/RX600/port.c b/portable/GCC/RX600/port.c
index 94747bdbe..9e6a7b443 100644
--- a/portable/GCC/RX600/port.c
+++ b/portable/GCC/RX600/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/RX600/portmacro.h b/portable/GCC/RX600/portmacro.h
index d441eb784..79559a989 100644
--- a/portable/GCC/RX600/portmacro.h
+++ b/portable/GCC/RX600/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/RX600v2/port.c b/portable/GCC/RX600v2/port.c
index 56212de9c..c31d2c65c 100644
--- a/portable/GCC/RX600v2/port.c
+++ b/portable/GCC/RX600v2/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/RX600v2/portmacro.h b/portable/GCC/RX600v2/portmacro.h
index d441eb784..79559a989 100644
--- a/portable/GCC/RX600v2/portmacro.h
+++ b/portable/GCC/RX600v2/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/RX700v3_DPFPU/port.c b/portable/GCC/RX700v3_DPFPU/port.c
index 7aa1e741c..8ed1bcfa4 100644
--- a/portable/GCC/RX700v3_DPFPU/port.c
+++ b/portable/GCC/RX700v3_DPFPU/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/RX700v3_DPFPU/portmacro.h b/portable/GCC/RX700v3_DPFPU/portmacro.h
index 4f9b8a087..68c65b45f 100644
--- a/portable/GCC/RX700v3_DPFPU/portmacro.h
+++ b/portable/GCC/RX700v3_DPFPU/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/STR75x/port.c b/portable/GCC/STR75x/port.c
index 09fab1897..941b72b5f 100644
--- a/portable/GCC/STR75x/port.c
+++ b/portable/GCC/STR75x/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/STR75x/portISR.c b/portable/GCC/STR75x/portISR.c
index 569a6c7d3..110c22a80 100644
--- a/portable/GCC/STR75x/portISR.c
+++ b/portable/GCC/STR75x/portISR.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/STR75x/portmacro.h b/portable/GCC/STR75x/portmacro.h
index b52d3a513..81a30dcb3 100644
--- a/portable/GCC/STR75x/portmacro.h
+++ b/portable/GCC/STR75x/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/TriCore_1782/port.c b/portable/GCC/TriCore_1782/port.c
index f8f54922a..1579d8e72 100644
--- a/portable/GCC/TriCore_1782/port.c
+++ b/portable/GCC/TriCore_1782/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/TriCore_1782/portmacro.h b/portable/GCC/TriCore_1782/portmacro.h
index 8c1a9c0eb..c1e0b14d5 100644
--- a/portable/GCC/TriCore_1782/portmacro.h
+++ b/portable/GCC/TriCore_1782/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/GCC/TriCore_1782/porttrap.c b/portable/GCC/TriCore_1782/porttrap.c
index 732a406b6..f0600d754 100644
--- a/portable/GCC/TriCore_1782/porttrap.c
+++ b/portable/GCC/TriCore_1782/porttrap.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/78K0R/ISR_Support.h b/portable/IAR/78K0R/ISR_Support.h
index 2fa110c70..b5a1f4d1d 100644
--- a/portable/IAR/78K0R/ISR_Support.h
+++ b/portable/IAR/78K0R/ISR_Support.h
@@ -1,6 +1,6 @@
 ; /*
    * ; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
-   * ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+   * ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
    * ; *
    * ; * SPDX-License-Identifier: MIT
    * ; *
diff --git a/portable/IAR/78K0R/port.c b/portable/IAR/78K0R/port.c
index 97d390300..3183b89ab 100644
--- a/portable/IAR/78K0R/port.c
+++ b/portable/IAR/78K0R/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/78K0R/portasm.s26 b/portable/IAR/78K0R/portasm.s26
index 6b6b76137..1cddc0caf 100644
--- a/portable/IAR/78K0R/portasm.s26
+++ b/portable/IAR/78K0R/portasm.s26
@@ -1,6 +1,6 @@
 ;/*
 ; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
-; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 ; *
 ; * SPDX-License-Identifier: MIT
 ; *
diff --git a/portable/IAR/78K0R/portmacro.h b/portable/IAR/78K0R/portmacro.h
index 206b82c22..e0ac8fb02 100644
--- a/portable/IAR/78K0R/portmacro.h
+++ b/portable/IAR/78K0R/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CA5_No_GIC/port.c b/portable/IAR/ARM_CA5_No_GIC/port.c
index 3cb7c0db2..31afbb567 100644
--- a/portable/IAR/ARM_CA5_No_GIC/port.c
+++ b/portable/IAR/ARM_CA5_No_GIC/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CA5_No_GIC/portASM.h b/portable/IAR/ARM_CA5_No_GIC/portASM.h
index 1a9006df3..c3f9978d2 100644
--- a/portable/IAR/ARM_CA5_No_GIC/portASM.h
+++ b/portable/IAR/ARM_CA5_No_GIC/portASM.h
@@ -1,6 +1,6 @@
 ;/*
 ; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
-; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 ; *
 ; * SPDX-License-Identifier: MIT
 ; *
diff --git a/portable/IAR/ARM_CA5_No_GIC/portASM.s b/portable/IAR/ARM_CA5_No_GIC/portASM.s
index 8edcb6c55..dcfaa6043 100644
--- a/portable/IAR/ARM_CA5_No_GIC/portASM.s
+++ b/portable/IAR/ARM_CA5_No_GIC/portASM.s
@@ -1,6 +1,6 @@
 ;/*
 ; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
-; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 ; *
 ; * SPDX-License-Identifier: MIT
 ; *
diff --git a/portable/IAR/ARM_CA5_No_GIC/portmacro.h b/portable/IAR/ARM_CA5_No_GIC/portmacro.h
index 82794345d..8d5caeb8a 100644
--- a/portable/IAR/ARM_CA5_No_GIC/portmacro.h
+++ b/portable/IAR/ARM_CA5_No_GIC/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CA9/port.c b/portable/IAR/ARM_CA9/port.c
index 3f87288ae..b558099af 100644
--- a/portable/IAR/ARM_CA9/port.c
+++ b/portable/IAR/ARM_CA9/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CA9/portASM.h b/portable/IAR/ARM_CA9/portASM.h
index e6df989da..181530b67 100644
--- a/portable/IAR/ARM_CA9/portASM.h
+++ b/portable/IAR/ARM_CA9/portASM.h
@@ -1,6 +1,6 @@
 ;/*
 ; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
-; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 ; *
 ; * SPDX-License-Identifier: MIT
 ; *
diff --git a/portable/IAR/ARM_CA9/portASM.s b/portable/IAR/ARM_CA9/portASM.s
index 56ec384c0..d7d07995f 100644
--- a/portable/IAR/ARM_CA9/portASM.s
+++ b/portable/IAR/ARM_CA9/portASM.s
@@ -1,6 +1,6 @@
 ;/*
 ; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
-; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 ; *
 ; * SPDX-License-Identifier: MIT
 ; *
diff --git a/portable/IAR/ARM_CA9/portmacro.h b/portable/IAR/ARM_CA9/portmacro.h
index 4782a5a66..c0954d895 100644
--- a/portable/IAR/ARM_CA9/portmacro.h
+++ b/portable/IAR/ARM_CA9/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM0/port.c b/portable/IAR/ARM_CM0/port.c
index 1b9caa13a..634833389 100644
--- a/portable/IAR/ARM_CM0/port.c
+++ b/portable/IAR/ARM_CM0/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM0/portasm.s b/portable/IAR/ARM_CM0/portasm.s
index ede492135..6c19a1749 100644
--- a/portable/IAR/ARM_CM0/portasm.s
+++ b/portable/IAR/ARM_CM0/portasm.s
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM0/portmacro.h b/portable/IAR/ARM_CM0/portmacro.h
index 88cba2016..a097db9df 100644
--- a/portable/IAR/ARM_CM0/portmacro.h
+++ b/portable/IAR/ARM_CM0/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM23/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM23/non_secure/mpu_wrappers_v2_asm.S
index 419df5b1e..8ea2f5c78 100644
--- a/portable/IAR/ARM_CM23/non_secure/mpu_wrappers_v2_asm.S
+++ b/portable/IAR/ARM_CM23/non_secure/mpu_wrappers_v2_asm.S
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM23/non_secure/port.c b/portable/IAR/ARM_CM23/non_secure/port.c
index 6d88b637f..7171a72bf 100644
--- a/portable/IAR/ARM_CM23/non_secure/port.c
+++ b/portable/IAR/ARM_CM23/non_secure/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM23/non_secure/portasm.h b/portable/IAR/ARM_CM23/non_secure/portasm.h
index ecd86b97f..bd5a2bfca 100644
--- a/portable/IAR/ARM_CM23/non_secure/portasm.h
+++ b/portable/IAR/ARM_CM23/non_secure/portasm.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM23/non_secure/portasm.s b/portable/IAR/ARM_CM23/non_secure/portasm.s
index 06c761090..6817abd7a 100644
--- a/portable/IAR/ARM_CM23/non_secure/portasm.s
+++ b/portable/IAR/ARM_CM23/non_secure/portasm.s
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM23/non_secure/portmacro.h b/portable/IAR/ARM_CM23/non_secure/portmacro.h
index 56d7398f5..667b58151 100644
--- a/portable/IAR/ARM_CM23/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM23/non_secure/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h
index 672b0dbdc..3cf65761f 100644
--- a/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM23/secure/secure_context.c b/portable/IAR/ARM_CM23/secure/secure_context.c
index 7d2171996..72fb3862c 100644
--- a/portable/IAR/ARM_CM23/secure/secure_context.c
+++ b/portable/IAR/ARM_CM23/secure/secure_context.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM23/secure/secure_context.h b/portable/IAR/ARM_CM23/secure/secure_context.h
index 0bf776198..e36a8e430 100644
--- a/portable/IAR/ARM_CM23/secure/secure_context.h
+++ b/portable/IAR/ARM_CM23/secure/secure_context.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM23/secure/secure_context_port_asm.s b/portable/IAR/ARM_CM23/secure/secure_context_port_asm.s
index f7c5d19d2..f70e89115 100644
--- a/portable/IAR/ARM_CM23/secure/secure_context_port_asm.s
+++ b/portable/IAR/ARM_CM23/secure/secure_context_port_asm.s
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM23/secure/secure_heap.c b/portable/IAR/ARM_CM23/secure/secure_heap.c
index 1ec3bdbdb..4fa6a2ffa 100644
--- a/portable/IAR/ARM_CM23/secure/secure_heap.c
+++ b/portable/IAR/ARM_CM23/secure/secure_heap.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM23/secure/secure_heap.h b/portable/IAR/ARM_CM23/secure/secure_heap.h
index c13590f86..0e84a9d9d 100644
--- a/portable/IAR/ARM_CM23/secure/secure_heap.h
+++ b/portable/IAR/ARM_CM23/secure/secure_heap.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM23/secure/secure_init.c b/portable/IAR/ARM_CM23/secure/secure_init.c
index b89c5f644..c50d37668 100644
--- a/portable/IAR/ARM_CM23/secure/secure_init.c
+++ b/portable/IAR/ARM_CM23/secure/secure_init.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM23/secure/secure_init.h b/portable/IAR/ARM_CM23/secure/secure_init.h
index 21daeda6b..ebe04900f 100644
--- a/portable/IAR/ARM_CM23/secure/secure_init.h
+++ b/portable/IAR/ARM_CM23/secure/secure_init.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM23/secure/secure_port_macros.h b/portable/IAR/ARM_CM23/secure/secure_port_macros.h
index 304913b8d..a70da2c65 100644
--- a/portable/IAR/ARM_CM23/secure/secure_port_macros.h
+++ b/portable/IAR/ARM_CM23/secure/secure_port_macros.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.S
index 419df5b1e..8ea2f5c78 100644
--- a/portable/IAR/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.S
+++ b/portable/IAR/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.S
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
index 6d88b637f..7171a72bf 100644
--- a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h b/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h
index ecd86b97f..bd5a2bfca 100644
--- a/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h
+++ b/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s b/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s
index d4487dfac..bfe9eee4b 100644
--- a/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s
+++ b/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h b/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h
index 56d7398f5..667b58151 100644
--- a/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h
index 672b0dbdc..3cf65761f 100644
--- a/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM3/port.c b/portable/IAR/ARM_CM3/port.c
index 460826872..d254dc255 100644
--- a/portable/IAR/ARM_CM3/port.c
+++ b/portable/IAR/ARM_CM3/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM3/portasm.s b/portable/IAR/ARM_CM3/portasm.s
index 0dbb43b00..7b2afde98 100644
--- a/portable/IAR/ARM_CM3/portasm.s
+++ b/portable/IAR/ARM_CM3/portasm.s
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM3/portmacro.h b/portable/IAR/ARM_CM3/portmacro.h
index c90a952e2..a64c4fb26 100644
--- a/portable/IAR/ARM_CM3/portmacro.h
+++ b/portable/IAR/ARM_CM3/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM33/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM33/non_secure/mpu_wrappers_v2_asm.S
index 80d5a1c63..a69845eda 100644
--- a/portable/IAR/ARM_CM33/non_secure/mpu_wrappers_v2_asm.S
+++ b/portable/IAR/ARM_CM33/non_secure/mpu_wrappers_v2_asm.S
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM33/non_secure/port.c b/portable/IAR/ARM_CM33/non_secure/port.c
index 6d88b637f..7171a72bf 100644
--- a/portable/IAR/ARM_CM33/non_secure/port.c
+++ b/portable/IAR/ARM_CM33/non_secure/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM33/non_secure/portasm.h b/portable/IAR/ARM_CM33/non_secure/portasm.h
index ecd86b97f..bd5a2bfca 100644
--- a/portable/IAR/ARM_CM33/non_secure/portasm.h
+++ b/portable/IAR/ARM_CM33/non_secure/portasm.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM33/non_secure/portasm.s b/portable/IAR/ARM_CM33/non_secure/portasm.s
index d8f1b1d9a..418c5f887 100644
--- a/portable/IAR/ARM_CM33/non_secure/portasm.s
+++ b/portable/IAR/ARM_CM33/non_secure/portasm.s
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM33/non_secure/portmacro.h b/portable/IAR/ARM_CM33/non_secure/portmacro.h
index 890f3ea96..eeb14d86f 100644
--- a/portable/IAR/ARM_CM33/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM33/non_secure/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h
index 672b0dbdc..3cf65761f 100644
--- a/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM33/secure/secure_context.c b/portable/IAR/ARM_CM33/secure/secure_context.c
index 7d2171996..72fb3862c 100644
--- a/portable/IAR/ARM_CM33/secure/secure_context.c
+++ b/portable/IAR/ARM_CM33/secure/secure_context.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM33/secure/secure_context.h b/portable/IAR/ARM_CM33/secure/secure_context.h
index 0bf776198..e36a8e430 100644
--- a/portable/IAR/ARM_CM33/secure/secure_context.h
+++ b/portable/IAR/ARM_CM33/secure/secure_context.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM33/secure/secure_context_port_asm.s b/portable/IAR/ARM_CM33/secure/secure_context_port_asm.s
index 400bd0107..27a8f3933 100644
--- a/portable/IAR/ARM_CM33/secure/secure_context_port_asm.s
+++ b/portable/IAR/ARM_CM33/secure/secure_context_port_asm.s
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM33/secure/secure_heap.c b/portable/IAR/ARM_CM33/secure/secure_heap.c
index 1ec3bdbdb..4fa6a2ffa 100644
--- a/portable/IAR/ARM_CM33/secure/secure_heap.c
+++ b/portable/IAR/ARM_CM33/secure/secure_heap.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM33/secure/secure_heap.h b/portable/IAR/ARM_CM33/secure/secure_heap.h
index c13590f86..0e84a9d9d 100644
--- a/portable/IAR/ARM_CM33/secure/secure_heap.h
+++ b/portable/IAR/ARM_CM33/secure/secure_heap.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM33/secure/secure_init.c b/portable/IAR/ARM_CM33/secure/secure_init.c
index b89c5f644..c50d37668 100644
--- a/portable/IAR/ARM_CM33/secure/secure_init.c
+++ b/portable/IAR/ARM_CM33/secure/secure_init.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM33/secure/secure_init.h b/portable/IAR/ARM_CM33/secure/secure_init.h
index 21daeda6b..ebe04900f 100644
--- a/portable/IAR/ARM_CM33/secure/secure_init.h
+++ b/portable/IAR/ARM_CM33/secure/secure_init.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM33/secure/secure_port_macros.h b/portable/IAR/ARM_CM33/secure/secure_port_macros.h
index 304913b8d..a70da2c65 100644
--- a/portable/IAR/ARM_CM33/secure/secure_port_macros.h
+++ b/portable/IAR/ARM_CM33/secure/secure_port_macros.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.S
index 80d5a1c63..a69845eda 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.S
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.S
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
index 6d88b637f..7171a72bf 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h b/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h
index ecd86b97f..bd5a2bfca 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s b/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s
index 7cf467d22..44f662646 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h b/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h
index 59a44193f..acb4748a2 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h
index 672b0dbdc..3cf65761f 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.S
index 80d5a1c63..a69845eda 100644
--- a/portable/IAR/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.S
+++ b/portable/IAR/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.S
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM35P/non_secure/port.c b/portable/IAR/ARM_CM35P/non_secure/port.c
index 6d88b637f..7171a72bf 100644
--- a/portable/IAR/ARM_CM35P/non_secure/port.c
+++ b/portable/IAR/ARM_CM35P/non_secure/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM35P/non_secure/portasm.h b/portable/IAR/ARM_CM35P/non_secure/portasm.h
index ecd86b97f..bd5a2bfca 100644
--- a/portable/IAR/ARM_CM35P/non_secure/portasm.h
+++ b/portable/IAR/ARM_CM35P/non_secure/portasm.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM35P/non_secure/portasm.s b/portable/IAR/ARM_CM35P/non_secure/portasm.s
index d8f1b1d9a..418c5f887 100644
--- a/portable/IAR/ARM_CM35P/non_secure/portasm.s
+++ b/portable/IAR/ARM_CM35P/non_secure/portasm.s
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM35P/non_secure/portmacro.h b/portable/IAR/ARM_CM35P/non_secure/portmacro.h
index 468d14311..0dcac8d4d 100644
--- a/portable/IAR/ARM_CM35P/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM35P/non_secure/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h
index 672b0dbdc..3cf65761f 100644
--- a/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM35P/secure/secure_context.c b/portable/IAR/ARM_CM35P/secure/secure_context.c
index 7d2171996..72fb3862c 100644
--- a/portable/IAR/ARM_CM35P/secure/secure_context.c
+++ b/portable/IAR/ARM_CM35P/secure/secure_context.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM35P/secure/secure_context.h b/portable/IAR/ARM_CM35P/secure/secure_context.h
index 0bf776198..e36a8e430 100644
--- a/portable/IAR/ARM_CM35P/secure/secure_context.h
+++ b/portable/IAR/ARM_CM35P/secure/secure_context.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM35P/secure/secure_context_port_asm.s b/portable/IAR/ARM_CM35P/secure/secure_context_port_asm.s
index 400bd0107..27a8f3933 100644
--- a/portable/IAR/ARM_CM35P/secure/secure_context_port_asm.s
+++ b/portable/IAR/ARM_CM35P/secure/secure_context_port_asm.s
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM35P/secure/secure_heap.c b/portable/IAR/ARM_CM35P/secure/secure_heap.c
index 1ec3bdbdb..4fa6a2ffa 100644
--- a/portable/IAR/ARM_CM35P/secure/secure_heap.c
+++ b/portable/IAR/ARM_CM35P/secure/secure_heap.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM35P/secure/secure_heap.h b/portable/IAR/ARM_CM35P/secure/secure_heap.h
index c13590f86..0e84a9d9d 100644
--- a/portable/IAR/ARM_CM35P/secure/secure_heap.h
+++ b/portable/IAR/ARM_CM35P/secure/secure_heap.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM35P/secure/secure_init.c b/portable/IAR/ARM_CM35P/secure/secure_init.c
index b89c5f644..c50d37668 100644
--- a/portable/IAR/ARM_CM35P/secure/secure_init.c
+++ b/portable/IAR/ARM_CM35P/secure/secure_init.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM35P/secure/secure_init.h b/portable/IAR/ARM_CM35P/secure/secure_init.h
index 21daeda6b..ebe04900f 100644
--- a/portable/IAR/ARM_CM35P/secure/secure_init.h
+++ b/portable/IAR/ARM_CM35P/secure/secure_init.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM35P/secure/secure_port_macros.h b/portable/IAR/ARM_CM35P/secure/secure_port_macros.h
index 304913b8d..a70da2c65 100644
--- a/portable/IAR/ARM_CM35P/secure/secure_port_macros.h
+++ b/portable/IAR/ARM_CM35P/secure/secure_port_macros.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.S
index 80d5a1c63..a69845eda 100644
--- a/portable/IAR/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.S
+++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.S
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c b/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
index 6d88b637f..7171a72bf 100644
--- a/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.h b/portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.h
index ecd86b97f..bd5a2bfca 100644
--- a/portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.h
+++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.s b/portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.s
index 7cf467d22..44f662646 100644
--- a/portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.s
+++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.s
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacro.h b/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacro.h
index 468d14311..0dcac8d4d 100644
--- a/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
index 672b0dbdc..3cf65761f 100644
--- a/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM4F/port.c b/portable/IAR/ARM_CM4F/port.c
index 763ff2a5c..18b433282 100644
--- a/portable/IAR/ARM_CM4F/port.c
+++ b/portable/IAR/ARM_CM4F/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM4F/portasm.s b/portable/IAR/ARM_CM4F/portasm.s
index f4caf80bf..a2e8c3009 100644
--- a/portable/IAR/ARM_CM4F/portasm.s
+++ b/portable/IAR/ARM_CM4F/portasm.s
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM4F/portmacro.h b/portable/IAR/ARM_CM4F/portmacro.h
index 20467efcb..93cfd555e 100644
--- a/portable/IAR/ARM_CM4F/portmacro.h
+++ b/portable/IAR/ARM_CM4F/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM4F_MPU/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM4F_MPU/mpu_wrappers_v2_asm.S
index d21dbaa7f..bf91e99c6 100644
--- a/portable/IAR/ARM_CM4F_MPU/mpu_wrappers_v2_asm.S
+++ b/portable/IAR/ARM_CM4F_MPU/mpu_wrappers_v2_asm.S
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM4F_MPU/port.c b/portable/IAR/ARM_CM4F_MPU/port.c
index b3db081f3..622af0f1e 100644
--- a/portable/IAR/ARM_CM4F_MPU/port.c
+++ b/portable/IAR/ARM_CM4F_MPU/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM4F_MPU/portasm.s b/portable/IAR/ARM_CM4F_MPU/portasm.s
index 7866d9ee9..9ce0e14d8 100644
--- a/portable/IAR/ARM_CM4F_MPU/portasm.s
+++ b/portable/IAR/ARM_CM4F_MPU/portasm.s
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM4F_MPU/portmacro.h b/portable/IAR/ARM_CM4F_MPU/portmacro.h
index 5b994cca9..f7f8b51f1 100644
--- a/portable/IAR/ARM_CM4F_MPU/portmacro.h
+++ b/portable/IAR/ARM_CM4F_MPU/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM55/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM55/non_secure/mpu_wrappers_v2_asm.S
index 80d5a1c63..a69845eda 100644
--- a/portable/IAR/ARM_CM55/non_secure/mpu_wrappers_v2_asm.S
+++ b/portable/IAR/ARM_CM55/non_secure/mpu_wrappers_v2_asm.S
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM55/non_secure/port.c b/portable/IAR/ARM_CM55/non_secure/port.c
index 6d88b637f..7171a72bf 100644
--- a/portable/IAR/ARM_CM55/non_secure/port.c
+++ b/portable/IAR/ARM_CM55/non_secure/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM55/non_secure/portasm.h b/portable/IAR/ARM_CM55/non_secure/portasm.h
index ecd86b97f..bd5a2bfca 100644
--- a/portable/IAR/ARM_CM55/non_secure/portasm.h
+++ b/portable/IAR/ARM_CM55/non_secure/portasm.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM55/non_secure/portasm.s b/portable/IAR/ARM_CM55/non_secure/portasm.s
index d8f1b1d9a..418c5f887 100644
--- a/portable/IAR/ARM_CM55/non_secure/portasm.s
+++ b/portable/IAR/ARM_CM55/non_secure/portasm.s
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM55/non_secure/portmacro.h b/portable/IAR/ARM_CM55/non_secure/portmacro.h
index 1338d25be..92dc75fd1 100644
--- a/portable/IAR/ARM_CM55/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM55/non_secure/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h
index 672b0dbdc..3cf65761f 100644
--- a/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM55/secure/secure_context.c b/portable/IAR/ARM_CM55/secure/secure_context.c
index 7d2171996..72fb3862c 100644
--- a/portable/IAR/ARM_CM55/secure/secure_context.c
+++ b/portable/IAR/ARM_CM55/secure/secure_context.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM55/secure/secure_context.h b/portable/IAR/ARM_CM55/secure/secure_context.h
index 0bf776198..e36a8e430 100644
--- a/portable/IAR/ARM_CM55/secure/secure_context.h
+++ b/portable/IAR/ARM_CM55/secure/secure_context.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM55/secure/secure_context_port_asm.s b/portable/IAR/ARM_CM55/secure/secure_context_port_asm.s
index 400bd0107..27a8f3933 100644
--- a/portable/IAR/ARM_CM55/secure/secure_context_port_asm.s
+++ b/portable/IAR/ARM_CM55/secure/secure_context_port_asm.s
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM55/secure/secure_heap.c b/portable/IAR/ARM_CM55/secure/secure_heap.c
index 1ec3bdbdb..4fa6a2ffa 100644
--- a/portable/IAR/ARM_CM55/secure/secure_heap.c
+++ b/portable/IAR/ARM_CM55/secure/secure_heap.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM55/secure/secure_heap.h b/portable/IAR/ARM_CM55/secure/secure_heap.h
index c13590f86..0e84a9d9d 100644
--- a/portable/IAR/ARM_CM55/secure/secure_heap.h
+++ b/portable/IAR/ARM_CM55/secure/secure_heap.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM55/secure/secure_init.c b/portable/IAR/ARM_CM55/secure/secure_init.c
index b89c5f644..c50d37668 100644
--- a/portable/IAR/ARM_CM55/secure/secure_init.c
+++ b/portable/IAR/ARM_CM55/secure/secure_init.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM55/secure/secure_init.h b/portable/IAR/ARM_CM55/secure/secure_init.h
index 21daeda6b..ebe04900f 100644
--- a/portable/IAR/ARM_CM55/secure/secure_init.h
+++ b/portable/IAR/ARM_CM55/secure/secure_init.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM55/secure/secure_port_macros.h b/portable/IAR/ARM_CM55/secure/secure_port_macros.h
index 304913b8d..a70da2c65 100644
--- a/portable/IAR/ARM_CM55/secure/secure_port_macros.h
+++ b/portable/IAR/ARM_CM55/secure/secure_port_macros.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.S
index 80d5a1c63..a69845eda 100644
--- a/portable/IAR/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.S
+++ b/portable/IAR/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.S
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/port.c b/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
index 6d88b637f..7171a72bf 100644
--- a/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.h b/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.h
index ecd86b97f..bd5a2bfca 100644
--- a/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.h
+++ b/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.s b/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.s
index 7cf467d22..44f662646 100644
--- a/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.s
+++ b/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.s
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/portmacro.h b/portable/IAR/ARM_CM55_NTZ/non_secure/portmacro.h
index 1338d25be..92dc75fd1 100644
--- a/portable/IAR/ARM_CM55_NTZ/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM55_NTZ/non_secure/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h
index 672b0dbdc..3cf65761f 100644
--- a/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM7/r0p1/port.c b/portable/IAR/ARM_CM7/r0p1/port.c
index 2790028f4..7def0060e 100644
--- a/portable/IAR/ARM_CM7/r0p1/port.c
+++ b/portable/IAR/ARM_CM7/r0p1/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM7/r0p1/portasm.s b/portable/IAR/ARM_CM7/r0p1/portasm.s
index 483178d96..56d4b3e04 100644
--- a/portable/IAR/ARM_CM7/r0p1/portasm.s
+++ b/portable/IAR/ARM_CM7/r0p1/portasm.s
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM7/r0p1/portmacro.h b/portable/IAR/ARM_CM7/r0p1/portmacro.h
index a6c377b6b..0165b2d91 100644
--- a/portable/IAR/ARM_CM7/r0p1/portmacro.h
+++ b/portable/IAR/ARM_CM7/r0p1/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM85/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM85/non_secure/mpu_wrappers_v2_asm.S
index 80d5a1c63..a69845eda 100644
--- a/portable/IAR/ARM_CM85/non_secure/mpu_wrappers_v2_asm.S
+++ b/portable/IAR/ARM_CM85/non_secure/mpu_wrappers_v2_asm.S
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM85/non_secure/port.c b/portable/IAR/ARM_CM85/non_secure/port.c
index 6d88b637f..7171a72bf 100644
--- a/portable/IAR/ARM_CM85/non_secure/port.c
+++ b/portable/IAR/ARM_CM85/non_secure/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM85/non_secure/portasm.h b/portable/IAR/ARM_CM85/non_secure/portasm.h
index ecd86b97f..bd5a2bfca 100644
--- a/portable/IAR/ARM_CM85/non_secure/portasm.h
+++ b/portable/IAR/ARM_CM85/non_secure/portasm.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM85/non_secure/portasm.s b/portable/IAR/ARM_CM85/non_secure/portasm.s
index d8f1b1d9a..418c5f887 100644
--- a/portable/IAR/ARM_CM85/non_secure/portasm.s
+++ b/portable/IAR/ARM_CM85/non_secure/portasm.s
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM85/non_secure/portmacro.h b/portable/IAR/ARM_CM85/non_secure/portmacro.h
index cffcb20d9..02f67453a 100644
--- a/portable/IAR/ARM_CM85/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM85/non_secure/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h
index 672b0dbdc..3cf65761f 100644
--- a/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM85/secure/secure_context.c b/portable/IAR/ARM_CM85/secure/secure_context.c
index 7d2171996..72fb3862c 100644
--- a/portable/IAR/ARM_CM85/secure/secure_context.c
+++ b/portable/IAR/ARM_CM85/secure/secure_context.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM85/secure/secure_context.h b/portable/IAR/ARM_CM85/secure/secure_context.h
index 0bf776198..e36a8e430 100644
--- a/portable/IAR/ARM_CM85/secure/secure_context.h
+++ b/portable/IAR/ARM_CM85/secure/secure_context.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM85/secure/secure_context_port_asm.s b/portable/IAR/ARM_CM85/secure/secure_context_port_asm.s
index 400bd0107..27a8f3933 100644
--- a/portable/IAR/ARM_CM85/secure/secure_context_port_asm.s
+++ b/portable/IAR/ARM_CM85/secure/secure_context_port_asm.s
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM85/secure/secure_heap.c b/portable/IAR/ARM_CM85/secure/secure_heap.c
index 1ec3bdbdb..4fa6a2ffa 100644
--- a/portable/IAR/ARM_CM85/secure/secure_heap.c
+++ b/portable/IAR/ARM_CM85/secure/secure_heap.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM85/secure/secure_heap.h b/portable/IAR/ARM_CM85/secure/secure_heap.h
index c13590f86..0e84a9d9d 100644
--- a/portable/IAR/ARM_CM85/secure/secure_heap.h
+++ b/portable/IAR/ARM_CM85/secure/secure_heap.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM85/secure/secure_init.c b/portable/IAR/ARM_CM85/secure/secure_init.c
index b89c5f644..c50d37668 100644
--- a/portable/IAR/ARM_CM85/secure/secure_init.c
+++ b/portable/IAR/ARM_CM85/secure/secure_init.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM85/secure/secure_init.h b/portable/IAR/ARM_CM85/secure/secure_init.h
index 21daeda6b..ebe04900f 100644
--- a/portable/IAR/ARM_CM85/secure/secure_init.h
+++ b/portable/IAR/ARM_CM85/secure/secure_init.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM85/secure/secure_port_macros.h b/portable/IAR/ARM_CM85/secure/secure_port_macros.h
index 304913b8d..a70da2c65 100644
--- a/portable/IAR/ARM_CM85/secure/secure_port_macros.h
+++ b/portable/IAR/ARM_CM85/secure/secure_port_macros.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.S
index 80d5a1c63..a69845eda 100644
--- a/portable/IAR/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.S
+++ b/portable/IAR/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.S
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/port.c b/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
index 6d88b637f..7171a72bf 100644
--- a/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.h b/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.h
index ecd86b97f..bd5a2bfca 100644
--- a/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.h
+++ b/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.s b/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.s
index 7cf467d22..44f662646 100644
--- a/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.s
+++ b/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.s
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/portmacro.h b/portable/IAR/ARM_CM85_NTZ/non_secure/portmacro.h
index cffcb20d9..02f67453a 100644
--- a/portable/IAR/ARM_CM85_NTZ/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM85_NTZ/non_secure/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h
index 672b0dbdc..3cf65761f 100644
--- a/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CRx_No_GIC/port.c b/portable/IAR/ARM_CRx_No_GIC/port.c
index 235585642..1b5c0fb8e 100644
--- a/portable/IAR/ARM_CRx_No_GIC/port.c
+++ b/portable/IAR/ARM_CRx_No_GIC/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ARM_CRx_No_GIC/portASM.s b/portable/IAR/ARM_CRx_No_GIC/portASM.s
index 6883cced4..fb2a797ac 100644
--- a/portable/IAR/ARM_CRx_No_GIC/portASM.s
+++ b/portable/IAR/ARM_CRx_No_GIC/portASM.s
@@ -1,6 +1,6 @@
 ;/*
 ; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
-; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 ; *
 ; * SPDX-License-Identifier: MIT
 ; *
diff --git a/portable/IAR/ARM_CRx_No_GIC/portmacro.h b/portable/IAR/ARM_CRx_No_GIC/portmacro.h
index d7c18b1f7..7707fcf02 100644
--- a/portable/IAR/ARM_CRx_No_GIC/portmacro.h
+++ b/portable/IAR/ARM_CRx_No_GIC/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ATMega323/port.c b/portable/IAR/ATMega323/port.c
index 991713789..980787990 100644
--- a/portable/IAR/ATMega323/port.c
+++ b/portable/IAR/ATMega323/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ATMega323/portmacro.h b/portable/IAR/ATMega323/portmacro.h
index 0a870ae21..e50d9f3d7 100644
--- a/portable/IAR/ATMega323/portmacro.h
+++ b/portable/IAR/ATMega323/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/ATMega323/portmacro.s90 b/portable/IAR/ATMega323/portmacro.s90
index 8c72f410f..029d0dbb6 100644
--- a/portable/IAR/ATMega323/portmacro.s90
+++ b/portable/IAR/ATMega323/portmacro.s90
@@ -1,6 +1,6 @@
 ;/*
 ; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
-; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 ; *
 ; * SPDX-License-Identifier: MIT
 ; *
diff --git a/portable/IAR/AVR32_UC3/exception.s82 b/portable/IAR/AVR32_UC3/exception.s82
index 12012e420..653600995 100644
--- a/portable/IAR/AVR32_UC3/exception.s82
+++ b/portable/IAR/AVR32_UC3/exception.s82
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT AND BSD-3-Clause
  *
diff --git a/portable/IAR/AVR32_UC3/port.c b/portable/IAR/AVR32_UC3/port.c
index 94fa1e37a..7a1cc640b 100644
--- a/portable/IAR/AVR32_UC3/port.c
+++ b/portable/IAR/AVR32_UC3/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT AND BSD-3-Clause
  *
diff --git a/portable/IAR/AVR32_UC3/portmacro.h b/portable/IAR/AVR32_UC3/portmacro.h
index 42f4bfe65..036833f8f 100644
--- a/portable/IAR/AVR32_UC3/portmacro.h
+++ b/portable/IAR/AVR32_UC3/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT AND BSD-3-Clause
  *
diff --git a/portable/IAR/AVR32_UC3/read.c b/portable/IAR/AVR32_UC3/read.c
index bbdc0781b..639d1f8f8 100644
--- a/portable/IAR/AVR32_UC3/read.c
+++ b/portable/IAR/AVR32_UC3/read.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT AND BSD-3-Clause
  *
diff --git a/portable/IAR/AVR32_UC3/write.c b/portable/IAR/AVR32_UC3/write.c
index 139f45277..5ac796332 100644
--- a/portable/IAR/AVR32_UC3/write.c
+++ b/portable/IAR/AVR32_UC3/write.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT AND BSD-3-Clause
  *
diff --git a/portable/IAR/AVR_AVRDx/port.c b/portable/IAR/AVR_AVRDx/port.c
index 8d8f22331..07269f0f6 100644
--- a/portable/IAR/AVR_AVRDx/port.c
+++ b/portable/IAR/AVR_AVRDx/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/AVR_AVRDx/porthardware.h b/portable/IAR/AVR_AVRDx/porthardware.h
index c313e0c69..f9176f96b 100644
--- a/portable/IAR/AVR_AVRDx/porthardware.h
+++ b/portable/IAR/AVR_AVRDx/porthardware.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/AVR_AVRDx/portmacro.h b/portable/IAR/AVR_AVRDx/portmacro.h
index 13c3f6e6b..829958dc0 100644
--- a/portable/IAR/AVR_AVRDx/portmacro.h
+++ b/portable/IAR/AVR_AVRDx/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/AVR_AVRDx/portmacro.s90 b/portable/IAR/AVR_AVRDx/portmacro.s90
index dc72ccf58..c518d3af9 100644
--- a/portable/IAR/AVR_AVRDx/portmacro.s90
+++ b/portable/IAR/AVR_AVRDx/portmacro.s90
@@ -1,6 +1,6 @@
 ;/*
 ; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
-; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 ; *
 ; * SPDX-License-Identifier: MIT
 ; *
diff --git a/portable/IAR/AVR_Mega0/port.c b/portable/IAR/AVR_Mega0/port.c
index 4dc8ab3c3..7d1d2f6e8 100644
--- a/portable/IAR/AVR_Mega0/port.c
+++ b/portable/IAR/AVR_Mega0/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/AVR_Mega0/porthardware.h b/portable/IAR/AVR_Mega0/porthardware.h
index c7341447c..d834a8e82 100644
--- a/portable/IAR/AVR_Mega0/porthardware.h
+++ b/portable/IAR/AVR_Mega0/porthardware.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/AVR_Mega0/portmacro.h b/portable/IAR/AVR_Mega0/portmacro.h
index 13c3f6e6b..829958dc0 100644
--- a/portable/IAR/AVR_Mega0/portmacro.h
+++ b/portable/IAR/AVR_Mega0/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/AVR_Mega0/portmacro.s90 b/portable/IAR/AVR_Mega0/portmacro.s90
index 2e5046325..c2789d48e 100644
--- a/portable/IAR/AVR_Mega0/portmacro.s90
+++ b/portable/IAR/AVR_Mega0/portmacro.s90
@@ -1,6 +1,6 @@
 ;/*
 ; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
-; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 ; *
 ; * SPDX-License-Identifier: MIT
 ; *
diff --git a/portable/IAR/AtmelSAM7S64/ISR_Support.h b/portable/IAR/AtmelSAM7S64/ISR_Support.h
index d63e908b9..273e95141 100644
--- a/portable/IAR/AtmelSAM7S64/ISR_Support.h
+++ b/portable/IAR/AtmelSAM7S64/ISR_Support.h
@@ -1,6 +1,6 @@
 ; /*
    * ; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
-   * ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+   * ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
    * ; *
    * ; * SPDX-License-Identifier: MIT
    * ; *
diff --git a/portable/IAR/AtmelSAM7S64/port.c b/portable/IAR/AtmelSAM7S64/port.c
index ba72aa804..5f5f7625f 100644
--- a/portable/IAR/AtmelSAM7S64/port.c
+++ b/portable/IAR/AtmelSAM7S64/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/AtmelSAM7S64/portasm.s79 b/portable/IAR/AtmelSAM7S64/portasm.s79
index b01bcf548..4f5f5c083 100644
--- a/portable/IAR/AtmelSAM7S64/portasm.s79
+++ b/portable/IAR/AtmelSAM7S64/portasm.s79
@@ -1,6 +1,6 @@
 ;/*
 ; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
-; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 ; *
 ; * SPDX-License-Identifier: MIT
 ; *
diff --git a/portable/IAR/AtmelSAM7S64/portmacro.h b/portable/IAR/AtmelSAM7S64/portmacro.h
index 337139712..75588d526 100644
--- a/portable/IAR/AtmelSAM7S64/portmacro.h
+++ b/portable/IAR/AtmelSAM7S64/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/AtmelSAM9XE/ISR_Support.h b/portable/IAR/AtmelSAM9XE/ISR_Support.h
index e22768d7d..ac73c7816 100644
--- a/portable/IAR/AtmelSAM9XE/ISR_Support.h
+++ b/portable/IAR/AtmelSAM9XE/ISR_Support.h
@@ -1,6 +1,6 @@
 ; /*
    * ; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
-   * ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+   * ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
    * ; *
    * ; * SPDX-License-Identifier: MIT
    * ; *
diff --git a/portable/IAR/AtmelSAM9XE/port.c b/portable/IAR/AtmelSAM9XE/port.c
index 20c59b71f..f2bd893fc 100644
--- a/portable/IAR/AtmelSAM9XE/port.c
+++ b/portable/IAR/AtmelSAM9XE/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/AtmelSAM9XE/portasm.s79 b/portable/IAR/AtmelSAM9XE/portasm.s79
index d3434ecca..37241da9c 100644
--- a/portable/IAR/AtmelSAM9XE/portasm.s79
+++ b/portable/IAR/AtmelSAM9XE/portasm.s79
@@ -1,6 +1,6 @@
 ;/*
 ; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
-; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 ; *
 ; * SPDX-License-Identifier: MIT
 ; *
diff --git a/portable/IAR/AtmelSAM9XE/portmacro.h b/portable/IAR/AtmelSAM9XE/portmacro.h
index 6a234933e..68e54c8d3 100644
--- a/portable/IAR/AtmelSAM9XE/portmacro.h
+++ b/portable/IAR/AtmelSAM9XE/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/LPC2000/ISR_Support.h b/portable/IAR/LPC2000/ISR_Support.h
index d63e908b9..273e95141 100644
--- a/portable/IAR/LPC2000/ISR_Support.h
+++ b/portable/IAR/LPC2000/ISR_Support.h
@@ -1,6 +1,6 @@
 ; /*
    * ; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
-   * ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+   * ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
    * ; *
    * ; * SPDX-License-Identifier: MIT
    * ; *
diff --git a/portable/IAR/LPC2000/port.c b/portable/IAR/LPC2000/port.c
index a8cf766ab..69d711d3b 100644
--- a/portable/IAR/LPC2000/port.c
+++ b/portable/IAR/LPC2000/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/LPC2000/portasm.s79 b/portable/IAR/LPC2000/portasm.s79
index eb1793315..2bd1ccc06 100644
--- a/portable/IAR/LPC2000/portasm.s79
+++ b/portable/IAR/LPC2000/portasm.s79
@@ -1,6 +1,6 @@
 ;/*
 ; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
-; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 ; *
 ; * SPDX-License-Identifier: MIT
 ; *
diff --git a/portable/IAR/LPC2000/portmacro.h b/portable/IAR/LPC2000/portmacro.h
index 40231e408..b44d307f3 100644
--- a/portable/IAR/LPC2000/portmacro.h
+++ b/portable/IAR/LPC2000/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/MSP430/port.c b/portable/IAR/MSP430/port.c
index 845943c7f..070f64bf0 100644
--- a/portable/IAR/MSP430/port.c
+++ b/portable/IAR/MSP430/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/MSP430/portasm.h b/portable/IAR/MSP430/portasm.h
index 6b6f0563d..0d8115034 100644
--- a/portable/IAR/MSP430/portasm.h
+++ b/portable/IAR/MSP430/portasm.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/MSP430/portext.s43 b/portable/IAR/MSP430/portext.s43
index 5360a9700..bfe6a190f 100644
--- a/portable/IAR/MSP430/portext.s43
+++ b/portable/IAR/MSP430/portext.s43
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/MSP430/portmacro.h b/portable/IAR/MSP430/portmacro.h
index 51b8aad1e..f87bfe589 100644
--- a/portable/IAR/MSP430/portmacro.h
+++ b/portable/IAR/MSP430/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/MSP430X/data_model.h b/portable/IAR/MSP430X/data_model.h
index 97931f3b5..0d5dcbdd4 100644
--- a/portable/IAR/MSP430X/data_model.h
+++ b/portable/IAR/MSP430X/data_model.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/MSP430X/port.c b/portable/IAR/MSP430X/port.c
index 920f0796f..a6f81580b 100644
--- a/portable/IAR/MSP430X/port.c
+++ b/portable/IAR/MSP430X/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/MSP430X/portext.s43 b/portable/IAR/MSP430X/portext.s43
index cc2f592a3..ccfd084c2 100644
--- a/portable/IAR/MSP430X/portext.s43
+++ b/portable/IAR/MSP430X/portext.s43
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/MSP430X/portmacro.h b/portable/IAR/MSP430X/portmacro.h
index bac91e8a4..e426154e8 100644
--- a/portable/IAR/MSP430X/portmacro.h
+++ b/portable/IAR/MSP430X/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h b/portable/IAR/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h
index 01100f0a9..364fd5773 100644
--- a/portable/IAR/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h
+++ b/portable/IAR/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/RISC-V/port.c b/portable/IAR/RISC-V/port.c
index ce0cbdf2f..eec69439f 100644
--- a/portable/IAR/RISC-V/port.c
+++ b/portable/IAR/RISC-V/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/RISC-V/portASM.s b/portable/IAR/RISC-V/portASM.s
index 005b0eb90..f32d9e7ac 100644
--- a/portable/IAR/RISC-V/portASM.s
+++ b/portable/IAR/RISC-V/portASM.s
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/RISC-V/portContext.h b/portable/IAR/RISC-V/portContext.h
index 35bca7fe5..7b3244e7b 100644
--- a/portable/IAR/RISC-V/portContext.h
+++ b/portable/IAR/RISC-V/portContext.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/RISC-V/portmacro.h b/portable/IAR/RISC-V/portmacro.h
index 9a9141c58..c7237b363 100644
--- a/portable/IAR/RISC-V/portmacro.h
+++ b/portable/IAR/RISC-V/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/RL78/port.c b/portable/IAR/RL78/port.c
index 55baa43e7..446cdfae5 100644
--- a/portable/IAR/RL78/port.c
+++ b/portable/IAR/RL78/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/RL78/portasm.s b/portable/IAR/RL78/portasm.s
index f328d1bec..7067cb1e4 100644
--- a/portable/IAR/RL78/portasm.s
+++ b/portable/IAR/RL78/portasm.s
@@ -1,6 +1,6 @@
 ;/*
 ; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
-; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 ; *
 ; * SPDX-License-Identifier: MIT
 ; *
diff --git a/portable/IAR/RL78/portmacro.h b/portable/IAR/RL78/portmacro.h
index 4bf61e88f..a52a6d273 100644
--- a/portable/IAR/RL78/portmacro.h
+++ b/portable/IAR/RL78/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/RX100/port.c b/portable/IAR/RX100/port.c
index 27e5d4b75..b63b23b48 100644
--- a/portable/IAR/RX100/port.c
+++ b/portable/IAR/RX100/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/RX100/port_asm.s b/portable/IAR/RX100/port_asm.s
index 224f4484a..5eb90f7d1 100644
--- a/portable/IAR/RX100/port_asm.s
+++ b/portable/IAR/RX100/port_asm.s
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/RX100/portmacro.h b/portable/IAR/RX100/portmacro.h
index 2ea18f97a..f6dd43865 100644
--- a/portable/IAR/RX100/portmacro.h
+++ b/portable/IAR/RX100/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/RX600/port.c b/portable/IAR/RX600/port.c
index f59725bbd..73ff96cff 100644
--- a/portable/IAR/RX600/port.c
+++ b/portable/IAR/RX600/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/RX600/port_asm.s b/portable/IAR/RX600/port_asm.s
index d6584264b..29698534d 100644
--- a/portable/IAR/RX600/port_asm.s
+++ b/portable/IAR/RX600/port_asm.s
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/RX600/portmacro.h b/portable/IAR/RX600/portmacro.h
index 0a3659c92..b40242185 100644
--- a/portable/IAR/RX600/portmacro.h
+++ b/portable/IAR/RX600/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/RX700v3_DPFPU/port.c b/portable/IAR/RX700v3_DPFPU/port.c
index 2a902f28e..d05835975 100644
--- a/portable/IAR/RX700v3_DPFPU/port.c
+++ b/portable/IAR/RX700v3_DPFPU/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/RX700v3_DPFPU/portmacro.h b/portable/IAR/RX700v3_DPFPU/portmacro.h
index 2819f62e5..a3b15f75c 100644
--- a/portable/IAR/RX700v3_DPFPU/portmacro.h
+++ b/portable/IAR/RX700v3_DPFPU/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/RXv2/port.c b/portable/IAR/RXv2/port.c
index 2c87ba5af..af21ae57a 100644
--- a/portable/IAR/RXv2/port.c
+++ b/portable/IAR/RXv2/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/RXv2/port_asm.s b/portable/IAR/RXv2/port_asm.s
index 6fe6c1d18..cbebcf31d 100644
--- a/portable/IAR/RXv2/port_asm.s
+++ b/portable/IAR/RXv2/port_asm.s
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/RXv2/portmacro.h b/portable/IAR/RXv2/portmacro.h
index 512a6e594..67295fd22 100644
--- a/portable/IAR/RXv2/portmacro.h
+++ b/portable/IAR/RXv2/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/STR71x/ISR_Support.h b/portable/IAR/STR71x/ISR_Support.h
index d63e908b9..273e95141 100644
--- a/portable/IAR/STR71x/ISR_Support.h
+++ b/portable/IAR/STR71x/ISR_Support.h
@@ -1,6 +1,6 @@
 ; /*
    * ; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
-   * ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+   * ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
    * ; *
    * ; * SPDX-License-Identifier: MIT
    * ; *
diff --git a/portable/IAR/STR71x/port.c b/portable/IAR/STR71x/port.c
index bed6278c8..8f0e78c0d 100644
--- a/portable/IAR/STR71x/port.c
+++ b/portable/IAR/STR71x/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/STR71x/portasm.s79 b/portable/IAR/STR71x/portasm.s79
index 88acc6823..87166f691 100644
--- a/portable/IAR/STR71x/portasm.s79
+++ b/portable/IAR/STR71x/portasm.s79
@@ -1,6 +1,6 @@
 ;/*
 ; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
-; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 ; *
 ; * SPDX-License-Identifier: MIT
 ; *
diff --git a/portable/IAR/STR71x/portmacro.h b/portable/IAR/STR71x/portmacro.h
index 7f5096c9d..e05c380ab 100644
--- a/portable/IAR/STR71x/portmacro.h
+++ b/portable/IAR/STR71x/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/STR75x/ISR_Support.h b/portable/IAR/STR75x/ISR_Support.h
index d63e908b9..273e95141 100644
--- a/portable/IAR/STR75x/ISR_Support.h
+++ b/portable/IAR/STR75x/ISR_Support.h
@@ -1,6 +1,6 @@
 ; /*
    * ; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
-   * ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+   * ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
    * ; *
    * ; * SPDX-License-Identifier: MIT
    * ; *
diff --git a/portable/IAR/STR75x/port.c b/portable/IAR/STR75x/port.c
index 756ba06f3..b4ec381a5 100644
--- a/portable/IAR/STR75x/port.c
+++ b/portable/IAR/STR75x/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/STR75x/portasm.s79 b/portable/IAR/STR75x/portasm.s79
index 9427da1d9..ad2aa1b5e 100644
--- a/portable/IAR/STR75x/portasm.s79
+++ b/portable/IAR/STR75x/portasm.s79
@@ -1,6 +1,6 @@
 ;/*
 ; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
-; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 ; *
 ; * SPDX-License-Identifier: MIT
 ; *
diff --git a/portable/IAR/STR75x/portmacro.h b/portable/IAR/STR75x/portmacro.h
index 8be4a1a44..1d5cdabbe 100644
--- a/portable/IAR/STR75x/portmacro.h
+++ b/portable/IAR/STR75x/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/STR91x/ISR_Support.h b/portable/IAR/STR91x/ISR_Support.h
index c206a495b..2e6973757 100644
--- a/portable/IAR/STR91x/ISR_Support.h
+++ b/portable/IAR/STR91x/ISR_Support.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/STR91x/port.c b/portable/IAR/STR91x/port.c
index 8dd208016..f706c946e 100644
--- a/portable/IAR/STR91x/port.c
+++ b/portable/IAR/STR91x/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/STR91x/portasm.s79 b/portable/IAR/STR91x/portasm.s79
index 575c35fb3..9b91475c7 100644
--- a/portable/IAR/STR91x/portasm.s79
+++ b/portable/IAR/STR91x/portasm.s79
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/STR91x/portmacro.h b/portable/IAR/STR91x/portmacro.h
index 853b80139..fde5b6dcb 100644
--- a/portable/IAR/STR91x/portmacro.h
+++ b/portable/IAR/STR91x/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/V850ES/ISR_Support.h b/portable/IAR/V850ES/ISR_Support.h
index 3f04591f4..b99126d0f 100644
--- a/portable/IAR/V850ES/ISR_Support.h
+++ b/portable/IAR/V850ES/ISR_Support.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/V850ES/port.c b/portable/IAR/V850ES/port.c
index 17c17b66a..d1d9d6a7d 100644
--- a/portable/IAR/V850ES/port.c
+++ b/portable/IAR/V850ES/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/IAR/V850ES/portasm.s85 b/portable/IAR/V850ES/portasm.s85
index 6f795acbd..b01753667 100644
--- a/portable/IAR/V850ES/portasm.s85
+++ b/portable/IAR/V850ES/portasm.s85
@@ -1,6 +1,6 @@
 ;/*
 ; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
-; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 ; *
 ; * SPDX-License-Identifier: MIT
 ; *
diff --git a/portable/IAR/V850ES/portasm_Fx3.s85 b/portable/IAR/V850ES/portasm_Fx3.s85
index 412077a63..12262b3af 100644
--- a/portable/IAR/V850ES/portasm_Fx3.s85
+++ b/portable/IAR/V850ES/portasm_Fx3.s85
@@ -1,6 +1,6 @@
 ;/*
 ; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
-; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 ; *
 ; * SPDX-License-Identifier: MIT
 ; *
diff --git a/portable/IAR/V850ES/portasm_Hx2.s85 b/portable/IAR/V850ES/portasm_Hx2.s85
index 373431f84..03c2e38ae 100644
--- a/portable/IAR/V850ES/portasm_Hx2.s85
+++ b/portable/IAR/V850ES/portasm_Hx2.s85
@@ -1,6 +1,6 @@
 ;/*
 ; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
-; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 ; *
 ; * SPDX-License-Identifier: MIT
 ; *
diff --git a/portable/IAR/V850ES/portmacro.h b/portable/IAR/V850ES/portmacro.h
index fa9f87eff..0f066a0fc 100644
--- a/portable/IAR/V850ES/portmacro.h
+++ b/portable/IAR/V850ES/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/MPLAB/PIC18F/port.c b/portable/MPLAB/PIC18F/port.c
index a26d97116..bb8451581 100644
--- a/portable/MPLAB/PIC18F/port.c
+++ b/portable/MPLAB/PIC18F/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/MPLAB/PIC18F/portmacro.h b/portable/MPLAB/PIC18F/portmacro.h
index 80e83ed9e..a0bfb44b5 100644
--- a/portable/MPLAB/PIC18F/portmacro.h
+++ b/portable/MPLAB/PIC18F/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/MPLAB/PIC24_dsPIC/port.c b/portable/MPLAB/PIC24_dsPIC/port.c
index 6f23fe8a2..0299ec0ee 100644
--- a/portable/MPLAB/PIC24_dsPIC/port.c
+++ b/portable/MPLAB/PIC24_dsPIC/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/MPLAB/PIC24_dsPIC/portasm_PIC24.S b/portable/MPLAB/PIC24_dsPIC/portasm_PIC24.S
index 0019d9b45..e2a7d6267 100644
--- a/portable/MPLAB/PIC24_dsPIC/portasm_PIC24.S
+++ b/portable/MPLAB/PIC24_dsPIC/portasm_PIC24.S
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/MPLAB/PIC24_dsPIC/portasm_dsPIC.S b/portable/MPLAB/PIC24_dsPIC/portasm_dsPIC.S
index ea46426f4..ec1f070a4 100644
--- a/portable/MPLAB/PIC24_dsPIC/portasm_dsPIC.S
+++ b/portable/MPLAB/PIC24_dsPIC/portasm_dsPIC.S
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/MPLAB/PIC24_dsPIC/portmacro.h b/portable/MPLAB/PIC24_dsPIC/portmacro.h
index f01ee9c9b..fbac471d5 100644
--- a/portable/MPLAB/PIC24_dsPIC/portmacro.h
+++ b/portable/MPLAB/PIC24_dsPIC/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/MPLAB/PIC32MEC14xx/ISR_Support.h b/portable/MPLAB/PIC32MEC14xx/ISR_Support.h
index d2fa5bb4d..ce7c4ad63 100644
--- a/portable/MPLAB/PIC32MEC14xx/ISR_Support.h
+++ b/portable/MPLAB/PIC32MEC14xx/ISR_Support.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/MPLAB/PIC32MEC14xx/port.c b/portable/MPLAB/PIC32MEC14xx/port.c
index ebe9bdb7c..1f0d9cc03 100644
--- a/portable/MPLAB/PIC32MEC14xx/port.c
+++ b/portable/MPLAB/PIC32MEC14xx/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/MPLAB/PIC32MEC14xx/port_asm.S b/portable/MPLAB/PIC32MEC14xx/port_asm.S
index cb5aff269..b2c37f2db 100644
--- a/portable/MPLAB/PIC32MEC14xx/port_asm.S
+++ b/portable/MPLAB/PIC32MEC14xx/port_asm.S
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/MPLAB/PIC32MEC14xx/portmacro.h b/portable/MPLAB/PIC32MEC14xx/portmacro.h
index d4d4f50dc..665634659 100644
--- a/portable/MPLAB/PIC32MEC14xx/portmacro.h
+++ b/portable/MPLAB/PIC32MEC14xx/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/MPLAB/PIC32MX/ISR_Support.h b/portable/MPLAB/PIC32MX/ISR_Support.h
index d594c7cc7..0bff08fe1 100644
--- a/portable/MPLAB/PIC32MX/ISR_Support.h
+++ b/portable/MPLAB/PIC32MX/ISR_Support.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/MPLAB/PIC32MX/port.c b/portable/MPLAB/PIC32MX/port.c
index 9f9140763..582a600a3 100644
--- a/portable/MPLAB/PIC32MX/port.c
+++ b/portable/MPLAB/PIC32MX/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/MPLAB/PIC32MX/port_asm.S b/portable/MPLAB/PIC32MX/port_asm.S
index bc1448dee..4e00324eb 100644
--- a/portable/MPLAB/PIC32MX/port_asm.S
+++ b/portable/MPLAB/PIC32MX/port_asm.S
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/MPLAB/PIC32MX/portmacro.h b/portable/MPLAB/PIC32MX/portmacro.h
index b481165e6..7fa73ab98 100644
--- a/portable/MPLAB/PIC32MX/portmacro.h
+++ b/portable/MPLAB/PIC32MX/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/MPLAB/PIC32MZ/ISR_Support.h b/portable/MPLAB/PIC32MZ/ISR_Support.h
index a9ddee0f4..292877f42 100644
--- a/portable/MPLAB/PIC32MZ/ISR_Support.h
+++ b/portable/MPLAB/PIC32MZ/ISR_Support.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/MPLAB/PIC32MZ/port.c b/portable/MPLAB/PIC32MZ/port.c
index b8b5708fe..034fc26d1 100644
--- a/portable/MPLAB/PIC32MZ/port.c
+++ b/portable/MPLAB/PIC32MZ/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/MPLAB/PIC32MZ/port_asm.S b/portable/MPLAB/PIC32MZ/port_asm.S
index 4e7f639c4..78cb14165 100644
--- a/portable/MPLAB/PIC32MZ/port_asm.S
+++ b/portable/MPLAB/PIC32MZ/port_asm.S
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/MPLAB/PIC32MZ/portmacro.h b/portable/MPLAB/PIC32MZ/portmacro.h
index e6a3f5508..532a0fdac 100644
--- a/portable/MPLAB/PIC32MZ/portmacro.h
+++ b/portable/MPLAB/PIC32MZ/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/MSVC-MingW/port.c b/portable/MSVC-MingW/port.c
index 0a0fba6a3..b0c26bdac 100644
--- a/portable/MSVC-MingW/port.c
+++ b/portable/MSVC-MingW/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/MSVC-MingW/portmacro.h b/portable/MSVC-MingW/portmacro.h
index 9e64b7343..a10ac6586 100644
--- a/portable/MSVC-MingW/portmacro.h
+++ b/portable/MSVC-MingW/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/MemMang/heap_1.c b/portable/MemMang/heap_1.c
index 93538362f..68f14bd37 100644
--- a/portable/MemMang/heap_1.c
+++ b/portable/MemMang/heap_1.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/MemMang/heap_2.c b/portable/MemMang/heap_2.c
index 6f77f0869..c1b35b911 100644
--- a/portable/MemMang/heap_2.c
+++ b/portable/MemMang/heap_2.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/MemMang/heap_3.c b/portable/MemMang/heap_3.c
index 2240068e8..5094390b5 100644
--- a/portable/MemMang/heap_3.c
+++ b/portable/MemMang/heap_3.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/MemMang/heap_4.c b/portable/MemMang/heap_4.c
index ea1e422da..71b6a9421 100644
--- a/portable/MemMang/heap_4.c
+++ b/portable/MemMang/heap_4.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/MemMang/heap_5.c b/portable/MemMang/heap_5.c
index 4e1437393..bb33bcfad 100644
--- a/portable/MemMang/heap_5.c
+++ b/portable/MemMang/heap_5.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/MikroC/ARM_CM4F/port.c b/portable/MikroC/ARM_CM4F/port.c
index eeeb6b70b..dd5f35361 100644
--- a/portable/MikroC/ARM_CM4F/port.c
+++ b/portable/MikroC/ARM_CM4F/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/MikroC/ARM_CM4F/portmacro.h b/portable/MikroC/ARM_CM4F/portmacro.h
index 3d00da05a..15e4d5614 100644
--- a/portable/MikroC/ARM_CM4F/portmacro.h
+++ b/portable/MikroC/ARM_CM4F/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/Paradigm/Tern_EE/large_untested/port.c b/portable/Paradigm/Tern_EE/large_untested/port.c
index 4ecffe01a..443104885 100644
--- a/portable/Paradigm/Tern_EE/large_untested/port.c
+++ b/portable/Paradigm/Tern_EE/large_untested/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/Paradigm/Tern_EE/large_untested/portasm.h b/portable/Paradigm/Tern_EE/large_untested/portasm.h
index c3c7456a3..cf9e711c8 100644
--- a/portable/Paradigm/Tern_EE/large_untested/portasm.h
+++ b/portable/Paradigm/Tern_EE/large_untested/portasm.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/Paradigm/Tern_EE/large_untested/portmacro.h b/portable/Paradigm/Tern_EE/large_untested/portmacro.h
index 292c9e260..1ea0c3176 100644
--- a/portable/Paradigm/Tern_EE/large_untested/portmacro.h
+++ b/portable/Paradigm/Tern_EE/large_untested/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/Paradigm/Tern_EE/small/port.c b/portable/Paradigm/Tern_EE/small/port.c
index 2a1c0d962..75273f225 100644
--- a/portable/Paradigm/Tern_EE/small/port.c
+++ b/portable/Paradigm/Tern_EE/small/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/Paradigm/Tern_EE/small/portasm.h b/portable/Paradigm/Tern_EE/small/portasm.h
index 930da20b0..88ef3ba99 100644
--- a/portable/Paradigm/Tern_EE/small/portasm.h
+++ b/portable/Paradigm/Tern_EE/small/portasm.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/Paradigm/Tern_EE/small/portmacro.h b/portable/Paradigm/Tern_EE/small/portmacro.h
index ff0b34b20..0ab083838 100644
--- a/portable/Paradigm/Tern_EE/small/portmacro.h
+++ b/portable/Paradigm/Tern_EE/small/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/RVDS/ARM7_LPC21xx/port.c b/portable/RVDS/ARM7_LPC21xx/port.c
index 2d890e19d..5476af8c9 100644
--- a/portable/RVDS/ARM7_LPC21xx/port.c
+++ b/portable/RVDS/ARM7_LPC21xx/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/RVDS/ARM7_LPC21xx/portASM.s b/portable/RVDS/ARM7_LPC21xx/portASM.s
index 4398ca128..c47a9a641 100644
--- a/portable/RVDS/ARM7_LPC21xx/portASM.s
+++ b/portable/RVDS/ARM7_LPC21xx/portASM.s
@@ -1,6 +1,6 @@
 ;/*
 ; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
-; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 ; *
 ; * SPDX-License-Identifier: MIT
 ; *
diff --git a/portable/RVDS/ARM7_LPC21xx/portmacro.h b/portable/RVDS/ARM7_LPC21xx/portmacro.h
index be0628b77..5535dcfef 100644
--- a/portable/RVDS/ARM7_LPC21xx/portmacro.h
+++ b/portable/RVDS/ARM7_LPC21xx/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/RVDS/ARM7_LPC21xx/portmacro.inc b/portable/RVDS/ARM7_LPC21xx/portmacro.inc
index 62b1a8731..ef84d1adf 100644
--- a/portable/RVDS/ARM7_LPC21xx/portmacro.inc
+++ b/portable/RVDS/ARM7_LPC21xx/portmacro.inc
@@ -1,6 +1,6 @@
 ;/*
 ; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
-; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 ; *
 ; * SPDX-License-Identifier: MIT
 ; *
diff --git a/portable/RVDS/ARM_CA9/port.c b/portable/RVDS/ARM_CA9/port.c
index d3870b8ed..88979f42a 100644
--- a/portable/RVDS/ARM_CA9/port.c
+++ b/portable/RVDS/ARM_CA9/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/RVDS/ARM_CA9/portASM.s b/portable/RVDS/ARM_CA9/portASM.s
index a5ac2fc0b..f099ef2aa 100644
--- a/portable/RVDS/ARM_CA9/portASM.s
+++ b/portable/RVDS/ARM_CA9/portASM.s
@@ -1,6 +1,6 @@
 ;/*
 ; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
-; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 ; *
 ; * SPDX-License-Identifier: MIT
 ; *
diff --git a/portable/RVDS/ARM_CA9/portmacro.h b/portable/RVDS/ARM_CA9/portmacro.h
index fbe3472da..8a69d4677 100644
--- a/portable/RVDS/ARM_CA9/portmacro.h
+++ b/portable/RVDS/ARM_CA9/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/RVDS/ARM_CA9/portmacro.inc b/portable/RVDS/ARM_CA9/portmacro.inc
index 93b8d8db6..68a73945f 100644
--- a/portable/RVDS/ARM_CA9/portmacro.inc
+++ b/portable/RVDS/ARM_CA9/portmacro.inc
@@ -1,6 +1,6 @@
 ;/*
 ; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
-; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 ; *
 ; * SPDX-License-Identifier: MIT
 ; *
diff --git a/portable/RVDS/ARM_CM0/port.c b/portable/RVDS/ARM_CM0/port.c
index 96947d215..ececb715a 100644
--- a/portable/RVDS/ARM_CM0/port.c
+++ b/portable/RVDS/ARM_CM0/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/RVDS/ARM_CM0/portmacro.h b/portable/RVDS/ARM_CM0/portmacro.h
index 1b5821a71..785138722 100644
--- a/portable/RVDS/ARM_CM0/portmacro.h
+++ b/portable/RVDS/ARM_CM0/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/RVDS/ARM_CM3/port.c b/portable/RVDS/ARM_CM3/port.c
index 9a6af5acc..b75f00f29 100644
--- a/portable/RVDS/ARM_CM3/port.c
+++ b/portable/RVDS/ARM_CM3/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/RVDS/ARM_CM3/portmacro.h b/portable/RVDS/ARM_CM3/portmacro.h
index 4b8fbdb99..f69f4c303 100644
--- a/portable/RVDS/ARM_CM3/portmacro.h
+++ b/portable/RVDS/ARM_CM3/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/RVDS/ARM_CM4F/port.c b/portable/RVDS/ARM_CM4F/port.c
index c6d825b82..dfbbf4e4d 100644
--- a/portable/RVDS/ARM_CM4F/port.c
+++ b/portable/RVDS/ARM_CM4F/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/RVDS/ARM_CM4F/portmacro.h b/portable/RVDS/ARM_CM4F/portmacro.h
index 03ea9e95a..9957328d0 100644
--- a/portable/RVDS/ARM_CM4F/portmacro.h
+++ b/portable/RVDS/ARM_CM4F/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/RVDS/ARM_CM4_MPU/mpu_wrappers_v2_asm.c b/portable/RVDS/ARM_CM4_MPU/mpu_wrappers_v2_asm.c
index d65876356..fb04f194d 100644
--- a/portable/RVDS/ARM_CM4_MPU/mpu_wrappers_v2_asm.c
+++ b/portable/RVDS/ARM_CM4_MPU/mpu_wrappers_v2_asm.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/RVDS/ARM_CM4_MPU/port.c b/portable/RVDS/ARM_CM4_MPU/port.c
index 016521cf2..af4bf5e33 100644
--- a/portable/RVDS/ARM_CM4_MPU/port.c
+++ b/portable/RVDS/ARM_CM4_MPU/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/RVDS/ARM_CM4_MPU/portmacro.h b/portable/RVDS/ARM_CM4_MPU/portmacro.h
index 455aa84cd..1faeffd27 100644
--- a/portable/RVDS/ARM_CM4_MPU/portmacro.h
+++ b/portable/RVDS/ARM_CM4_MPU/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/RVDS/ARM_CM7/r0p1/port.c b/portable/RVDS/ARM_CM7/r0p1/port.c
index 49310786c..464ac2e81 100644
--- a/portable/RVDS/ARM_CM7/r0p1/port.c
+++ b/portable/RVDS/ARM_CM7/r0p1/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/RVDS/ARM_CM7/r0p1/portmacro.h b/portable/RVDS/ARM_CM7/r0p1/portmacro.h
index 2fcf53dfa..5f3a05397 100644
--- a/portable/RVDS/ARM_CM7/r0p1/portmacro.h
+++ b/portable/RVDS/ARM_CM7/r0p1/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/Renesas/RX100/port.c b/portable/Renesas/RX100/port.c
index 9e8db4f04..a22da66cf 100644
--- a/portable/Renesas/RX100/port.c
+++ b/portable/Renesas/RX100/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/Renesas/RX100/port_asm.src b/portable/Renesas/RX100/port_asm.src
index b3e60a416..afe0aba5b 100644
--- a/portable/Renesas/RX100/port_asm.src
+++ b/portable/Renesas/RX100/port_asm.src
@@ -1,6 +1,6 @@
 ;/*
 ; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
-; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 ; *
 ; * SPDX-License-Identifier: MIT
 ; *
diff --git a/portable/Renesas/RX100/portmacro.h b/portable/Renesas/RX100/portmacro.h
index a954bb71c..a38b93f4a 100644
--- a/portable/Renesas/RX100/portmacro.h
+++ b/portable/Renesas/RX100/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/Renesas/RX200/port.c b/portable/Renesas/RX200/port.c
index d60ac8fff..fe05cf750 100644
--- a/portable/Renesas/RX200/port.c
+++ b/portable/Renesas/RX200/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/Renesas/RX200/port_asm.src b/portable/Renesas/RX200/port_asm.src
index b3e60a416..afe0aba5b 100644
--- a/portable/Renesas/RX200/port_asm.src
+++ b/portable/Renesas/RX200/port_asm.src
@@ -1,6 +1,6 @@
 ;/*
 ; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
-; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 ; *
 ; * SPDX-License-Identifier: MIT
 ; *
diff --git a/portable/Renesas/RX200/portmacro.h b/portable/Renesas/RX200/portmacro.h
index efb9d93c8..d67acc4bb 100644
--- a/portable/Renesas/RX200/portmacro.h
+++ b/portable/Renesas/RX200/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/Renesas/RX600/port.c b/portable/Renesas/RX600/port.c
index 5438f5764..95431adce 100644
--- a/portable/Renesas/RX600/port.c
+++ b/portable/Renesas/RX600/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/Renesas/RX600/port_asm.src b/portable/Renesas/RX600/port_asm.src
index b3e60a416..afe0aba5b 100644
--- a/portable/Renesas/RX600/port_asm.src
+++ b/portable/Renesas/RX600/port_asm.src
@@ -1,6 +1,6 @@
 ;/*
 ; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
-; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 ; *
 ; * SPDX-License-Identifier: MIT
 ; *
diff --git a/portable/Renesas/RX600/portmacro.h b/portable/Renesas/RX600/portmacro.h
index 5ba1c067b..98a7fede4 100644
--- a/portable/Renesas/RX600/portmacro.h
+++ b/portable/Renesas/RX600/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/Renesas/RX600v2/port.c b/portable/Renesas/RX600v2/port.c
index ee7da87e6..bae8fd623 100644
--- a/portable/Renesas/RX600v2/port.c
+++ b/portable/Renesas/RX600v2/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/Renesas/RX600v2/port_asm.src b/portable/Renesas/RX600v2/port_asm.src
index 6fdcef60d..8d5200b6c 100644
--- a/portable/Renesas/RX600v2/port_asm.src
+++ b/portable/Renesas/RX600v2/port_asm.src
@@ -1,6 +1,6 @@
 ;/*
 ; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
-; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 ; *
 ; * SPDX-License-Identifier: MIT
 ; *
diff --git a/portable/Renesas/RX600v2/portmacro.h b/portable/Renesas/RX600v2/portmacro.h
index 630a34eee..b3868c157 100644
--- a/portable/Renesas/RX600v2/portmacro.h
+++ b/portable/Renesas/RX600v2/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/Renesas/RX700v3_DPFPU/port.c b/portable/Renesas/RX700v3_DPFPU/port.c
index 26cb9f020..6fec50425 100644
--- a/portable/Renesas/RX700v3_DPFPU/port.c
+++ b/portable/Renesas/RX700v3_DPFPU/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/Renesas/RX700v3_DPFPU/port_asm.src b/portable/Renesas/RX700v3_DPFPU/port_asm.src
index 6fdcef60d..8d5200b6c 100644
--- a/portable/Renesas/RX700v3_DPFPU/port_asm.src
+++ b/portable/Renesas/RX700v3_DPFPU/port_asm.src
@@ -1,6 +1,6 @@
 ;/*
 ; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
-; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 ; *
 ; * SPDX-License-Identifier: MIT
 ; *
diff --git a/portable/Renesas/RX700v3_DPFPU/portmacro.h b/portable/Renesas/RX700v3_DPFPU/portmacro.h
index 891024a22..fc1bb531b 100644
--- a/portable/Renesas/RX700v3_DPFPU/portmacro.h
+++ b/portable/Renesas/RX700v3_DPFPU/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/Renesas/SH2A_FPU/ISR_Support.inc b/portable/Renesas/SH2A_FPU/ISR_Support.inc
index 3128c526e..33ad2de68 100644
--- a/portable/Renesas/SH2A_FPU/ISR_Support.inc
+++ b/portable/Renesas/SH2A_FPU/ISR_Support.inc
@@ -1,6 +1,6 @@
 ;/*
 ; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
-; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 ; *
 ; * SPDX-License-Identifier: MIT
 ; *
diff --git a/portable/Renesas/SH2A_FPU/port.c b/portable/Renesas/SH2A_FPU/port.c
index b5e97e9b1..c14a0a851 100644
--- a/portable/Renesas/SH2A_FPU/port.c
+++ b/portable/Renesas/SH2A_FPU/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/Renesas/SH2A_FPU/portasm.src b/portable/Renesas/SH2A_FPU/portasm.src
index 6164f7644..4cf7225aa 100644
--- a/portable/Renesas/SH2A_FPU/portasm.src
+++ b/portable/Renesas/SH2A_FPU/portasm.src
@@ -1,6 +1,6 @@
 ;/*
 ; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
-; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 ; *
 ; * SPDX-License-Identifier: MIT
 ; *
diff --git a/portable/Renesas/SH2A_FPU/portmacro.h b/portable/Renesas/SH2A_FPU/portmacro.h
index e4143e608..2229fd3f6 100644
--- a/portable/Renesas/SH2A_FPU/portmacro.h
+++ b/portable/Renesas/SH2A_FPU/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/Rowley/MSP430F449/port.c b/portable/Rowley/MSP430F449/port.c
index 992e3e763..392dadbdd 100644
--- a/portable/Rowley/MSP430F449/port.c
+++ b/portable/Rowley/MSP430F449/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/Rowley/MSP430F449/portasm.h b/portable/Rowley/MSP430F449/portasm.h
index 96c27cdac..18361cce3 100644
--- a/portable/Rowley/MSP430F449/portasm.h
+++ b/portable/Rowley/MSP430F449/portasm.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/Rowley/MSP430F449/portext.asm b/portable/Rowley/MSP430F449/portext.asm
index f66214134..80cdcef81 100644
--- a/portable/Rowley/MSP430F449/portext.asm
+++ b/portable/Rowley/MSP430F449/portext.asm
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/Rowley/MSP430F449/portmacro.h b/portable/Rowley/MSP430F449/portmacro.h
index 7137a6e09..38304fb03 100644
--- a/portable/Rowley/MSP430F449/portmacro.h
+++ b/portable/Rowley/MSP430F449/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/SDCC/Cygnal/port.c b/portable/SDCC/Cygnal/port.c
index 8bf739eb7..418a50430 100644
--- a/portable/SDCC/Cygnal/port.c
+++ b/portable/SDCC/Cygnal/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/SDCC/Cygnal/portmacro.h b/portable/SDCC/Cygnal/portmacro.h
index 04186381f..fe0340757 100644
--- a/portable/SDCC/Cygnal/portmacro.h
+++ b/portable/SDCC/Cygnal/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/Softune/MB91460/__STD_LIB_sbrk.c b/portable/Softune/MB91460/__STD_LIB_sbrk.c
index d328a65fc..4f986e804 100644
--- a/portable/Softune/MB91460/__STD_LIB_sbrk.c
+++ b/portable/Softune/MB91460/__STD_LIB_sbrk.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/Softune/MB91460/port.c b/portable/Softune/MB91460/port.c
index 08e197b06..4b87ba402 100644
--- a/portable/Softune/MB91460/port.c
+++ b/portable/Softune/MB91460/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/Softune/MB91460/portmacro.h b/portable/Softune/MB91460/portmacro.h
index 9ae6959c4..182a3057e 100644
--- a/portable/Softune/MB91460/portmacro.h
+++ b/portable/Softune/MB91460/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/Softune/MB96340/__STD_LIB_sbrk.c b/portable/Softune/MB96340/__STD_LIB_sbrk.c
index d328a65fc..4f986e804 100644
--- a/portable/Softune/MB96340/__STD_LIB_sbrk.c
+++ b/portable/Softune/MB96340/__STD_LIB_sbrk.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/Softune/MB96340/port.c b/portable/Softune/MB96340/port.c
index aef0d65a9..ec0d977bc 100644
--- a/portable/Softune/MB96340/port.c
+++ b/portable/Softune/MB96340/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/Softune/MB96340/portmacro.h b/portable/Softune/MB96340/portmacro.h
index 827874fde..ef4a1eb5a 100644
--- a/portable/Softune/MB96340/portmacro.h
+++ b/portable/Softune/MB96340/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/Tasking/ARM_CM4F/port.c b/portable/Tasking/ARM_CM4F/port.c
index df79a9ac0..43a892f1e 100644
--- a/portable/Tasking/ARM_CM4F/port.c
+++ b/portable/Tasking/ARM_CM4F/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/Tasking/ARM_CM4F/port_asm.asm b/portable/Tasking/ARM_CM4F/port_asm.asm
index 5a65fb756..8b6784e70 100644
--- a/portable/Tasking/ARM_CM4F/port_asm.asm
+++ b/portable/Tasking/ARM_CM4F/port_asm.asm
@@ -1,6 +1,6 @@
 ;/*
 ; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
-; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 ; *
 ; * SPDX-License-Identifier: MIT
 ; *
diff --git a/portable/Tasking/ARM_CM4F/portmacro.h b/portable/Tasking/ARM_CM4F/portmacro.h
index 243e6856b..3d16cd6da 100644
--- a/portable/Tasking/ARM_CM4F/portmacro.h
+++ b/portable/Tasking/ARM_CM4F/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ThirdParty/GCC/ATmega/port.c b/portable/ThirdParty/GCC/ATmega/port.c
index 80308f2fa..168bcdd94 100644
--- a/portable/ThirdParty/GCC/ATmega/port.c
+++ b/portable/ThirdParty/GCC/ATmega/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ThirdParty/GCC/ATmega/portmacro.h b/portable/ThirdParty/GCC/ATmega/portmacro.h
index 9d34c0776..0cc583479 100644
--- a/portable/ThirdParty/GCC/ATmega/portmacro.h
+++ b/portable/ThirdParty/GCC/ATmega/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ThirdParty/GCC/Posix/utils/wait_for_event.c b/portable/ThirdParty/GCC/Posix/utils/wait_for_event.c
index ead6cdb07..beca2b360 100644
--- a/portable/ThirdParty/GCC/Posix/utils/wait_for_event.c
+++ b/portable/ThirdParty/GCC/Posix/utils/wait_for_event.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ThirdParty/GCC/Posix/utils/wait_for_event.h b/portable/ThirdParty/GCC/Posix/utils/wait_for_event.h
index 6f6efa3ea..533db04f1 100644
--- a/portable/ThirdParty/GCC/Posix/utils/wait_for_event.h
+++ b/portable/ThirdParty/GCC/Posix/utils/wait_for_event.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ThirdParty/GCC/RP2040/include/freertos_sdk_config.h b/portable/ThirdParty/GCC/RP2040/include/freertos_sdk_config.h
index 8d0676d95..71ca3277e 100644
--- a/portable/ThirdParty/GCC/RP2040/include/freertos_sdk_config.h
+++ b/portable/ThirdParty/GCC/RP2040/include/freertos_sdk_config.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
diff --git a/portable/ThirdParty/GCC/RP2040/include/portmacro.h b/portable/ThirdParty/GCC/RP2040/include/portmacro.h
index c9173fdea..1fe5e412f 100644
--- a/portable/ThirdParty/GCC/RP2040/include/portmacro.h
+++ b/portable/ThirdParty/GCC/RP2040/include/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: MIT AND BSD-3-Clause
diff --git a/portable/ThirdParty/GCC/RP2040/include/rp2040_config.h b/portable/ThirdParty/GCC/RP2040/include/rp2040_config.h
index 9fbbd15be..b2159a94e 100644
--- a/portable/ThirdParty/GCC/RP2040/include/rp2040_config.h
+++ b/portable/ThirdParty/GCC/RP2040/include/rp2040_config.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: MIT AND BSD-3-Clause
diff --git a/portable/ThirdParty/GCC/RP2040/port.c b/portable/ThirdParty/GCC/RP2040/port.c
index dda46f6f6..6c5d0e513 100644
--- a/portable/ThirdParty/GCC/RP2040/port.c
+++ b/portable/ThirdParty/GCC/RP2040/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: MIT AND BSD-3-Clause
diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/include/FreeRTOSConfig_arch.h b/portable/ThirdParty/GCC/Xtensa_ESP32/include/FreeRTOSConfig_arch.h
index f9c9630da..fa942add3 100644
--- a/portable/ThirdParty/GCC/Xtensa_ESP32/include/FreeRTOSConfig_arch.h
+++ b/portable/ThirdParty/GCC/Xtensa_ESP32/include/FreeRTOSConfig_arch.h
@@ -8,7 +8,7 @@
 
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/include/portmacro.h b/portable/ThirdParty/GCC/Xtensa_ESP32/include/portmacro.h
index e5e84efbc..2f3fe55e0 100644
--- a/portable/ThirdParty/GCC/Xtensa_ESP32/include/portmacro.h
+++ b/portable/ThirdParty/GCC/Xtensa_ESP32/include/portmacro.h
@@ -9,7 +9,7 @@
 
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/port.c b/portable/ThirdParty/GCC/Xtensa_ESP32/port.c
index f018bfd3f..a89868baa 100644
--- a/portable/ThirdParty/GCC/Xtensa_ESP32/port.c
+++ b/portable/ThirdParty/GCC/Xtensa_ESP32/port.c
@@ -9,7 +9,7 @@
 
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
diff --git a/portable/ThirdParty/XCC/Xtensa/port.c b/portable/ThirdParty/XCC/Xtensa/port.c
index 70c2679b5..320b47af2 100644
--- a/portable/ThirdParty/XCC/Xtensa/port.c
+++ b/portable/ThirdParty/XCC/Xtensa/port.c
@@ -1,7 +1,7 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ThirdParty/XCC/Xtensa/portasm.S b/portable/ThirdParty/XCC/Xtensa/portasm.S
index 10754ecad..7475ba510 100644
--- a/portable/ThirdParty/XCC/Xtensa/portasm.S
+++ b/portable/ThirdParty/XCC/Xtensa/portasm.S
@@ -1,7 +1,7 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ThirdParty/XCC/Xtensa/portbenchmark.h b/portable/ThirdParty/XCC/Xtensa/portbenchmark.h
index 7778dd1a5..ddaad7ad2 100644
--- a/portable/ThirdParty/XCC/Xtensa/portbenchmark.h
+++ b/portable/ThirdParty/XCC/Xtensa/portbenchmark.h
@@ -1,7 +1,7 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ThirdParty/XCC/Xtensa/portclib.c b/portable/ThirdParty/XCC/Xtensa/portclib.c
index 3c87d6741..5a3b659f9 100644
--- a/portable/ThirdParty/XCC/Xtensa/portclib.c
+++ b/portable/ThirdParty/XCC/Xtensa/portclib.c
@@ -1,7 +1,7 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ThirdParty/XCC/Xtensa/portmacro.h b/portable/ThirdParty/XCC/Xtensa/portmacro.h
index f84e4335e..d6a79b9be 100644
--- a/portable/ThirdParty/XCC/Xtensa/portmacro.h
+++ b/portable/ThirdParty/XCC/Xtensa/portmacro.h
@@ -1,7 +1,7 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ThirdParty/XCC/Xtensa/porttrace.h b/portable/ThirdParty/XCC/Xtensa/porttrace.h
index 9909ec3af..b8319ca1b 100644
--- a/portable/ThirdParty/XCC/Xtensa/porttrace.h
+++ b/portable/ThirdParty/XCC/Xtensa/porttrace.h
@@ -1,7 +1,7 @@
  /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ThirdParty/XCC/Xtensa/xtensa_api.h b/portable/ThirdParty/XCC/Xtensa/xtensa_api.h
index 703449f2b..361dbdc9e 100644
--- a/portable/ThirdParty/XCC/Xtensa/xtensa_api.h
+++ b/portable/ThirdParty/XCC/Xtensa/xtensa_api.h
@@ -1,7 +1,7 @@
  /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ThirdParty/XCC/Xtensa/xtensa_config.h b/portable/ThirdParty/XCC/Xtensa/xtensa_config.h
index a5efcda58..e3b31c06c 100644
--- a/portable/ThirdParty/XCC/Xtensa/xtensa_config.h
+++ b/portable/ThirdParty/XCC/Xtensa/xtensa_config.h
@@ -1,7 +1,7 @@
  /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ThirdParty/XCC/Xtensa/xtensa_context.S b/portable/ThirdParty/XCC/Xtensa/xtensa_context.S
index 96507e1c8..33311c3bd 100644
--- a/portable/ThirdParty/XCC/Xtensa/xtensa_context.S
+++ b/portable/ThirdParty/XCC/Xtensa/xtensa_context.S
@@ -1,7 +1,7 @@
  /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ThirdParty/XCC/Xtensa/xtensa_context.h b/portable/ThirdParty/XCC/Xtensa/xtensa_context.h
index 579c62ea2..256e71568 100644
--- a/portable/ThirdParty/XCC/Xtensa/xtensa_context.h
+++ b/portable/ThirdParty/XCC/Xtensa/xtensa_context.h
@@ -1,7 +1,7 @@
  /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ThirdParty/XCC/Xtensa/xtensa_init.c b/portable/ThirdParty/XCC/Xtensa/xtensa_init.c
index c18520350..b401aa8a8 100644
--- a/portable/ThirdParty/XCC/Xtensa/xtensa_init.c
+++ b/portable/ThirdParty/XCC/Xtensa/xtensa_init.c
@@ -1,7 +1,7 @@
  /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ThirdParty/XCC/Xtensa/xtensa_intr.c b/portable/ThirdParty/XCC/Xtensa/xtensa_intr.c
index 88ed191e3..79fe315ee 100644
--- a/portable/ThirdParty/XCC/Xtensa/xtensa_intr.c
+++ b/portable/ThirdParty/XCC/Xtensa/xtensa_intr.c
@@ -1,7 +1,7 @@
  /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ThirdParty/XCC/Xtensa/xtensa_intr_asm.S b/portable/ThirdParty/XCC/Xtensa/xtensa_intr_asm.S
index ec5ac4c83..287ba3e8a 100644
--- a/portable/ThirdParty/XCC/Xtensa/xtensa_intr_asm.S
+++ b/portable/ThirdParty/XCC/Xtensa/xtensa_intr_asm.S
@@ -1,7 +1,7 @@
  /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ThirdParty/XCC/Xtensa/xtensa_overlay_os_hook.c b/portable/ThirdParty/XCC/Xtensa/xtensa_overlay_os_hook.c
index 2a8506a01..e8523cac3 100644
--- a/portable/ThirdParty/XCC/Xtensa/xtensa_overlay_os_hook.c
+++ b/portable/ThirdParty/XCC/Xtensa/xtensa_overlay_os_hook.c
@@ -1,7 +1,7 @@
  /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ThirdParty/XCC/Xtensa/xtensa_rtos.h b/portable/ThirdParty/XCC/Xtensa/xtensa_rtos.h
index 2c917c832..88bd147d2 100644
--- a/portable/ThirdParty/XCC/Xtensa/xtensa_rtos.h
+++ b/portable/ThirdParty/XCC/Xtensa/xtensa_rtos.h
@@ -1,7 +1,7 @@
  /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ThirdParty/XCC/Xtensa/xtensa_timer.h b/portable/ThirdParty/XCC/Xtensa/xtensa_timer.h
index cefac70f2..1cea00fb3 100644
--- a/portable/ThirdParty/XCC/Xtensa/xtensa_timer.h
+++ b/portable/ThirdParty/XCC/Xtensa/xtensa_timer.h
@@ -1,7 +1,7 @@
  /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/ThirdParty/XCC/Xtensa/xtensa_vectors.S b/portable/ThirdParty/XCC/Xtensa/xtensa_vectors.S
index 7b8e9fd58..de5ffe836 100644
--- a/portable/ThirdParty/XCC/Xtensa/xtensa_vectors.S
+++ b/portable/ThirdParty/XCC/Xtensa/xtensa_vectors.S
@@ -1,7 +1,7 @@
  /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/WizC/PIC18/Drivers/Tick/Tick.c b/portable/WizC/PIC18/Drivers/Tick/Tick.c
index 5dfa080b6..53c2dbcc7 100644
--- a/portable/WizC/PIC18/Drivers/Tick/Tick.c
+++ b/portable/WizC/PIC18/Drivers/Tick/Tick.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/WizC/PIC18/Drivers/Tick/isrTick.c b/portable/WizC/PIC18/Drivers/Tick/isrTick.c
index f61047dc1..d68f8431f 100644
--- a/portable/WizC/PIC18/Drivers/Tick/isrTick.c
+++ b/portable/WizC/PIC18/Drivers/Tick/isrTick.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/WizC/PIC18/addFreeRTOS.h b/portable/WizC/PIC18/addFreeRTOS.h
index 178ca1089..386ae9f7e 100644
--- a/portable/WizC/PIC18/addFreeRTOS.h
+++ b/portable/WizC/PIC18/addFreeRTOS.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/WizC/PIC18/port.c b/portable/WizC/PIC18/port.c
index edabae61d..6941ece4f 100644
--- a/portable/WizC/PIC18/port.c
+++ b/portable/WizC/PIC18/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/WizC/PIC18/portmacro.h b/portable/WizC/PIC18/portmacro.h
index 44d26592f..a976bbd99 100644
--- a/portable/WizC/PIC18/portmacro.h
+++ b/portable/WizC/PIC18/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/oWatcom/16BitDOS/Flsh186/port.c b/portable/oWatcom/16BitDOS/Flsh186/port.c
index cc8863d1d..4b900b6a8 100644
--- a/portable/oWatcom/16BitDOS/Flsh186/port.c
+++ b/portable/oWatcom/16BitDOS/Flsh186/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/oWatcom/16BitDOS/Flsh186/portmacro.h b/portable/oWatcom/16BitDOS/Flsh186/portmacro.h
index 952e3f680..efa43611b 100644
--- a/portable/oWatcom/16BitDOS/Flsh186/portmacro.h
+++ b/portable/oWatcom/16BitDOS/Flsh186/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/oWatcom/16BitDOS/PC/port.c b/portable/oWatcom/16BitDOS/PC/port.c
index 6cb2de9e8..bbee5ec68 100644
--- a/portable/oWatcom/16BitDOS/PC/port.c
+++ b/portable/oWatcom/16BitDOS/PC/port.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/oWatcom/16BitDOS/PC/portmacro.h b/portable/oWatcom/16BitDOS/PC/portmacro.h
index 2fb753411..99b29dbc7 100644
--- a/portable/oWatcom/16BitDOS/PC/portmacro.h
+++ b/portable/oWatcom/16BitDOS/PC/portmacro.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/oWatcom/16BitDOS/common/portasm.h b/portable/oWatcom/16BitDOS/common/portasm.h
index f77e2b553..dac4dc864 100644
--- a/portable/oWatcom/16BitDOS/common/portasm.h
+++ b/portable/oWatcom/16BitDOS/common/portasm.h
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/portable/oWatcom/16BitDOS/common/portcomn.c b/portable/oWatcom/16BitDOS/common/portcomn.c
index 2a7b66637..d05b1fd1f 100644
--- a/portable/oWatcom/16BitDOS/common/portcomn.c
+++ b/portable/oWatcom/16BitDOS/common/portcomn.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/queue.c b/queue.c
index daf8d2e9d..b3029c19d 100644
--- a/queue.c
+++ b/queue.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/stream_buffer.c b/stream_buffer.c
index 00306fa04..2c357c657 100644
--- a/stream_buffer.c
+++ b/stream_buffer.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/tasks.c b/tasks.c
index 217cc6201..767dff7b0 100644
--- a/tasks.c
+++ b/tasks.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
diff --git a/timers.c b/timers.c
index a3d0d0abe..4e2a9f61f 100644
--- a/timers.c
+++ b/timers.c
@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *

From 61111b14602530a6bcddda75329deb2b5ae31f49 Mon Sep 17 00:00:00 2001
From: Soren Ptak <ptaksoren@gmail.com>
Date: Mon, 26 Feb 2024 14:01:25 -0500
Subject: [PATCH 230/424] Add ARMv7-R MPU Port (#938)

* Apply git review patch created by @aggargr
* Add necessary changes to the CMakeLists.txt file to build the port
---
 .github/.cSpellWords.txt                      |  16 +
 .github/scripts/kernel_checker.py             |   3 +-
 .github/workflows/formatting.yml              |   2 +-
 CMakeLists.txt                                |   1 +
 portable/CMakeLists.txt                       |   6 +
 .../GCC/ARM_CRx_MPU/mpu_wrappers_v2_asm.S     | 854 ++++++++++++++++++
 portable/GCC/ARM_CRx_MPU/port.c               | 843 +++++++++++++++++
 portable/GCC/ARM_CRx_MPU/portASM.S            | 498 ++++++++++
 portable/GCC/ARM_CRx_MPU/portmacro.h          | 522 +++++++++++
 portable/GCC/ARM_CRx_MPU/portmacro_asm.h      | 279 ++++++
 10 files changed, 3022 insertions(+), 2 deletions(-)
 create mode 100644 portable/GCC/ARM_CRx_MPU/mpu_wrappers_v2_asm.S
 create mode 100644 portable/GCC/ARM_CRx_MPU/port.c
 create mode 100644 portable/GCC/ARM_CRx_MPU/portASM.S
 create mode 100644 portable/GCC/ARM_CRx_MPU/portmacro.h
 create mode 100644 portable/GCC/ARM_CRx_MPU/portmacro_asm.h

diff --git a/.github/.cSpellWords.txt b/.github/.cSpellWords.txt
index ba8abfdf8..c41a05015 100644
--- a/.github/.cSpellWords.txt
+++ b/.github/.cSpellWords.txt
@@ -549,6 +549,10 @@ NTRST
 NVIC
 ODAT
 ODSR
+OINC
+OIWBNOWA
+OIWBWA
+OIWTNOWA
 OPMOD
 optimisations
 OPTIMISED
@@ -795,6 +799,15 @@ SWRST
 SWTRG
 synchronise
 SYSC
+sysclk
+Sysclk
+SysClk
+SYSClk
+SYSCLK
+sysclock
+Sysclock
+SysClock
+SYSCLOCK
 TACCR
 TACCTL
 TACLR
@@ -877,6 +890,9 @@ UNDADD
 unpadded
 Unpadded
 UNPADDED
+unprotect
+Unprotect
+Unprotected
 UNRE
 UNSUB
 UNSUBACK
diff --git a/.github/scripts/kernel_checker.py b/.github/scripts/kernel_checker.py
index 130841abb..b57b7f527 100755
--- a/.github/scripts/kernel_checker.py
+++ b/.github/scripts/kernel_checker.py
@@ -37,7 +37,8 @@ KERNEL_IGNORED_FILES = [
     'FreeRTOS-openocd.c',
     'Makefile',
     '.DS_Store',
-    'cspell.config.yaml'
+    'cspell.config.yaml',
+    '.clang-format'
 ]
 
 KERNEL_IGNORED_EXTENSIONS = [
diff --git a/.github/workflows/formatting.yml b/.github/workflows/formatting.yml
index 14d41c9c0..2f369105a 100644
--- a/.github/workflows/formatting.yml
+++ b/.github/workflows/formatting.yml
@@ -19,7 +19,7 @@ jobs:
     runs-on: ubuntu-20.04
     steps:
     - name: Apply Formatting Fix
-      id: check-formatting  
+      id: check-formatting
       uses: FreeRTOS/CI-CD-Github-Actions/formatting-bot@main
       with:
         exclude-dirs: portable
diff --git a/CMakeLists.txt b/CMakeLists.txt
index 07eeec471..6fd1ff56b 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -85,6 +85,7 @@ if(NOT FREERTOS_PORT)
         " GCC_ARM_CM85_NTZ_NONSECURE       - Compiler: GCC           Target: ARM Cortex-M85 non-trustzone non-secure\n"
         " GCC_ARM_CM85_TFM                 - Compiler: GCC           Target: ARM Cortex-M85 non-secure for TF-M\n"
         " GCC_ARM_CR5                      - Compiler: GCC           Target: ARM Cortex-R5\n"
+        " GCC_ARM_CRX_MPU                  - Compiler: GCC           Target: ARM Cortex-Rx with MPU\n"
         " GCC_ARM_CRX_NOGIC                - Compiler: GCC           Target: ARM Cortex-Rx no GIC\n"
         " GCC_ARM7_AT91FR40008             - Compiler: GCC           Target: ARM7 Atmel AT91R40008\n"
         " GCC_ARM7_AT91SAM7S               - Compiler: GCC           Target: ARM7 Atmel AT91SAM7S\n"
diff --git a/portable/CMakeLists.txt b/portable/CMakeLists.txt
index c067e9706..af9321e9f 100644
--- a/portable/CMakeLists.txt
+++ b/portable/CMakeLists.txt
@@ -207,6 +207,11 @@ add_library(freertos_kernel_port OBJECT
         GCC/ARM_CR5/port.c
         GCC/ARM_CR5/portASM.S>
 
+    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CRX_MPU>:
+        GCC/ARM_CRx_MPU/port.c
+        GCC/ARM_CRx_MPU/portASM.S
+        GCC/ARM_CRx_MPU/mpu_wrappers_v2_asm.S>
+
     $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CRX_NOGIC>:
         GCC/ARM_CRx_No_GIC/port.c
         GCC/ARM_CRx_No_GIC/portASM.S>
@@ -836,6 +841,7 @@ target_include_directories(freertos_kernel_port_headers INTERFACE
 
     # ARMv7-R ports for GCC
     $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CR5>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CR5>
+    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CRX_MPU>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CRx_MPU>
     $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CRX_NOGIC>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CRx_No_GIC>
 
     # ARMv4T ARM7TDMI ports for GCC
diff --git a/portable/GCC/ARM_CRx_MPU/mpu_wrappers_v2_asm.S b/portable/GCC/ARM_CRx_MPU/mpu_wrappers_v2_asm.S
new file mode 100644
index 000000000..8d0f769bb
--- /dev/null
+++ b/portable/GCC/ARM_CRx_MPU/mpu_wrappers_v2_asm.S
@@ -0,0 +1,854 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* ----------------------------------------------------------------------------------- */
+
+    .arm
+    .syntax unified
+    .section freertos_system_calls
+
+#define FREERTOS_ASSEMBLY
+    #include "FreeRTOSConfig.h"
+    #include "portmacro_asm.h"
+    #include "mpu_syscall_numbers.h"
+#undef FREERTOS_ASSEMBLY
+
+/* ----------------------- Start of Port Specific System Calls ----------------------- */
+
+/*
+ * void vPortYield( void );
+ */
+.align 4
+.global vPortYield
+.type vPortYield, %function
+vPortYield:
+    SVC     #portSVC_YIELD
+    BX      LR
+
+/* ----------------------------------------------------------------------------------- */
+
+/*
+ * void vPortSystemCallExit( void );
+ */
+.align 4
+.global vPortSystemCallExit
+.type vPortSystemCallExit, %function
+vPortSystemCallExit:
+    SVC     #portSVC_SYSTEM_CALL_EXIT
+    BX      LR
+
+/* ----------------------------------------------------------------------------------- */
+
+/*
+ * BaseType_t xPortIsPrivileged( void );
+ *
+ * According to the Procedure Call Standard for the ARM Architecture (AAPCS):
+ * - Return value must be in R0.
+ */
+.align 4
+.global xPortIsPrivileged
+.type xPortIsPrivileged, %function
+xPortIsPrivileged:
+    MRS     R0, CPSR        /* R0 = CPSR. */
+    AND     R0, R0, #0x1F   /* R0 = R0 & 0x1F. Extract mode bits.*/
+    CMP     R0, #USER_MODE  /* If R0 == #USER_MODE. */
+    MOVEQ   R0, #0x0        /* Then, set R0 to 0 to indicate that the processer is not privileged. */
+    MOVNE   R0, #0x01       /* Otherwise, set R0 to 1 to indicate that the processer is privileged. */
+    BX      LR
+
+/* ----------------------------------------------------------------------------------- */
+
+/*
+ * UBaseType_t ulPortCountLeadingZeros( UBaseType_t ulBitmap );
+ *
+ * According to the Procedure Call Standard for the ARM Architecture (AAPCS):
+ * - Parameter ulBitmap is passed in R0.
+ * - Return value must be in R0.
+ */
+.align 4
+.weak ulPortCountLeadingZeros
+.type ulPortCountLeadingZeros, %function
+ulPortCountLeadingZeros:
+    CLZ     R0, R0
+    BX      LR
+
+/* ------------------- End of Port Specific System Calls ------------------- */
+
+.macro INVOKE_SYSTEM_CALL systemCallNumber, systemCallImpl
+    PUSH    {R0}
+    MRS     R0, CPSR
+    AND     R0, R0, #0x1F
+    CMP     R0, #USER_MODE
+    POP     {R0}
+    SVCEQ   \systemCallNumber
+    B       \systemCallImpl
+.endm
+
+/* ----------------------------------------------------------------------------------- */
+
+.extern MPU_xTaskGetTickCountImpl
+.align 4
+.global MPU_xTaskGetTickCount
+.type MPU_xTaskGetTickCount, function
+MPU_xTaskGetTickCount:
+    INVOKE_SYSTEM_CALL #SYSTEM_CALL_xTaskGetTickCount, MPU_xTaskGetTickCountImpl
+
+/* ----------------------------------------------------------------------------------- */
+
+.extern MPU_uxTaskGetNumberOfTasksImpl
+.align 4
+.global MPU_uxTaskGetNumberOfTasks
+.type MPU_uxTaskGetNumberOfTasks, function
+MPU_uxTaskGetNumberOfTasks:
+    INVOKE_SYSTEM_CALL #SYSTEM_CALL_uxTaskGetNumberOfTasks, MPU_uxTaskGetNumberOfTasksImpl
+
+/* ----------------------------------------------------------------------------------- */
+
+.extern MPU_vTaskSetTimeOutStateImpl
+.align 4
+.global MPU_vTaskSetTimeOutState
+.type MPU_vTaskSetTimeOutState, function
+MPU_vTaskSetTimeOutState:
+    INVOKE_SYSTEM_CALL #SYSTEM_CALL_vTaskSetTimeOutState, MPU_vTaskSetTimeOutStateImpl
+
+/* ----------------------------------------------------------------------------------- */
+
+.extern MPU_xTaskCheckForTimeOutImpl
+.align 4
+.global MPU_xTaskCheckForTimeOut
+.type MPU_xTaskCheckForTimeOut, function
+MPU_xTaskCheckForTimeOut:
+    INVOKE_SYSTEM_CALL #SYSTEM_CALL_xTaskCheckForTimeOut, MPU_xTaskCheckForTimeOutImpl
+
+/* ----------------------------------------------------------------------------------- */
+
+.extern MPU_xQueueGenericSendImpl
+.align 4
+.global MPU_xQueueGenericSend
+.type MPU_xQueueGenericSend, function
+MPU_xQueueGenericSend:
+    INVOKE_SYSTEM_CALL #SYSTEM_CALL_xQueueGenericSend, MPU_xQueueGenericSendImpl
+
+/* ----------------------------------------------------------------------------------- */
+
+.extern MPU_uxQueueMessagesWaitingImpl
+.align 4
+.global MPU_uxQueueMessagesWaiting
+.type MPU_uxQueueMessagesWaiting, function
+MPU_uxQueueMessagesWaiting:
+    INVOKE_SYSTEM_CALL #SYSTEM_CALL_uxQueueMessagesWaiting, MPU_uxQueueMessagesWaitingImpl
+
+/* ----------------------------------------------------------------------------------- */
+
+.extern MPU_uxQueueSpacesAvailableImpl
+.align 4
+.global MPU_uxQueueSpacesAvailable
+.type MPU_uxQueueSpacesAvailable, function
+MPU_uxQueueSpacesAvailable:
+    INVOKE_SYSTEM_CALL #SYSTEM_CALL_uxQueueSpacesAvailable, MPU_uxQueueSpacesAvailableImpl
+
+/* ----------------------------------------------------------------------------------- */
+
+.extern MPU_xQueueReceiveImpl
+.align 4
+.global MPU_xQueueReceive
+.type MPU_xQueueReceive, function
+MPU_xQueueReceive:
+    INVOKE_SYSTEM_CALL #SYSTEM_CALL_xQueueReceive, MPU_xQueueReceiveImpl
+
+/* ----------------------------------------------------------------------------------- */
+
+.extern MPU_xQueuePeekImpl
+.align 4
+.global MPU_xQueuePeek
+.type MPU_xQueuePeek, function
+MPU_xQueuePeek:
+    INVOKE_SYSTEM_CALL #SYSTEM_CALL_xQueuePeek, MPU_xQueuePeekImpl
+
+/* ----------------------------------------------------------------------------------- */
+
+.extern MPU_xQueueSemaphoreTakeImpl
+.align 4
+.global MPU_xQueueSemaphoreTake
+.type MPU_xQueueSemaphoreTake, function
+MPU_xQueueSemaphoreTake:
+    INVOKE_SYSTEM_CALL #SYSTEM_CALL_xQueueSemaphoreTake, MPU_xQueueSemaphoreTakeImpl
+
+/* ----------------------------------------------------------------------------------- */
+
+.extern MPU_xEventGroupWaitBitsImpl
+.align 4
+.global MPU_xEventGroupWaitBitsEntry
+.type MPU_xEventGroupWaitBitsEntry, function
+MPU_xEventGroupWaitBitsEntry:
+    INVOKE_SYSTEM_CALL #SYSTEM_CALL_xEventGroupWaitBits, MPU_xEventGroupWaitBitsImpl
+
+/* ----------------------------------------------------------------------------------- */
+
+.extern MPU_xEventGroupClearBitsImpl
+.align 4
+.global MPU_xEventGroupClearBits
+.type MPU_xEventGroupClearBits, function
+MPU_xEventGroupClearBits:
+    INVOKE_SYSTEM_CALL #SYSTEM_CALL_xEventGroupClearBits, MPU_xEventGroupClearBitsImpl
+
+/* ----------------------------------------------------------------------------------- */
+
+.extern MPU_xEventGroupSetBitsImpl
+.align 4
+.global MPU_xEventGroupSetBits
+.type MPU_xEventGroupSetBits, function
+MPU_xEventGroupSetBits:
+    INVOKE_SYSTEM_CALL #SYSTEM_CALL_xEventGroupSetBits, MPU_xEventGroupSetBitsImpl
+
+/* ----------------------------------------------------------------------------------- */
+
+.extern MPU_xEventGroupSyncImpl
+.align 4
+.global MPU_xEventGroupSync
+.type MPU_xEventGroupSync, function
+MPU_xEventGroupSync:
+    INVOKE_SYSTEM_CALL #SYSTEM_CALL_xEventGroupSync, MPU_xEventGroupSyncImpl
+
+/* ----------------------------------------------------------------------------------- */
+
+.extern MPU_xStreamBufferSendImpl
+.align 4
+.global MPU_xStreamBufferSend
+.type MPU_xStreamBufferSend, function
+MPU_xStreamBufferSend:
+    INVOKE_SYSTEM_CALL #SYSTEM_CALL_xStreamBufferSend, MPU_xStreamBufferSendImpl
+
+/* ----------------------------------------------------------------------------------- */
+
+.extern MPU_xStreamBufferReceiveImpl
+.align 4
+.global MPU_xStreamBufferReceive
+.type MPU_xStreamBufferReceive, function
+MPU_xStreamBufferReceive:
+    INVOKE_SYSTEM_CALL #SYSTEM_CALL_xStreamBufferReceive, MPU_xStreamBufferReceiveImpl
+
+/* ----------------------------------------------------------------------------------- */
+
+.extern MPU_xStreamBufferIsFullImpl
+.align 4
+.global MPU_xStreamBufferIsFull
+.type MPU_xStreamBufferIsFull, function
+MPU_xStreamBufferIsFull:
+    INVOKE_SYSTEM_CALL #SYSTEM_CALL_xStreamBufferIsFull, MPU_xStreamBufferIsFullImpl
+
+/* ----------------------------------------------------------------------------------- */
+
+.extern MPU_xStreamBufferIsEmptyImpl
+.align 4
+.global MPU_xStreamBufferIsEmpty
+.type MPU_xStreamBufferIsEmpty, function
+MPU_xStreamBufferIsEmpty:
+    INVOKE_SYSTEM_CALL #SYSTEM_CALL_xStreamBufferIsEmpty, MPU_xStreamBufferIsEmptyImpl
+
+/* ----------------------------------------------------------------------------------- */
+
+.extern MPU_xStreamBufferSpacesAvailableImpl
+.align 4
+.global MPU_xStreamBufferSpacesAvailable
+.type MPU_xStreamBufferSpacesAvailable, function
+MPU_xStreamBufferSpacesAvailable:
+    INVOKE_SYSTEM_CALL #SYSTEM_CALL_xStreamBufferSpacesAvailable, MPU_xStreamBufferSpacesAvailableImpl
+
+/* ----------------------------------------------------------------------------------- */
+
+.extern MPU_xStreamBufferBytesAvailableImpl
+.align 4
+.global MPU_xStreamBufferBytesAvailable
+.type MPU_xStreamBufferBytesAvailable, function
+MPU_xStreamBufferBytesAvailable:
+    INVOKE_SYSTEM_CALL #SYSTEM_CALL_xStreamBufferBytesAvailable, MPU_xStreamBufferBytesAvailableImpl
+
+/* ----------------------------------------------------------------------------------- */
+
+.extern MPU_xStreamBufferSetTriggerLevelImpl
+.align 4
+.global MPU_xStreamBufferSetTriggerLevel
+.type MPU_xStreamBufferSetTriggerLevel, function
+MPU_xStreamBufferSetTriggerLevel:
+    INVOKE_SYSTEM_CALL #SYSTEM_CALL_xStreamBufferSetTriggerLevel, MPU_xStreamBufferSetTriggerLevelImpl
+
+/* ----------------------------------------------------------------------------------- */
+
+.extern MPU_xStreamBufferNextMessageLengthBytesImpl
+.align 4
+.global MPU_xStreamBufferNextMessageLengthBytes
+.type MPU_xStreamBufferNextMessageLengthBytes, function
+MPU_xStreamBufferNextMessageLengthBytes:
+    INVOKE_SYSTEM_CALL #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes, MPU_xStreamBufferNextMessageLengthBytesImpl
+
+/* ----------------------------------------------------------------------------------- */
+
+#if ( ( INCLUDE_xTaskDelayUntil == 1 ) || ( INCLUDE_vTaskDelayUntil == 1 ) )
+
+    .extern MPU_xTaskDelayUntilImpl
+    .align 4
+    .global MPU_xTaskDelayUntil
+    .type MPU_xTaskDelayUntil, function
+    MPU_xTaskDelayUntil:
+        INVOKE_SYSTEM_CALL #SYSTEM_CALL_xTaskDelayUntil, MPU_xTaskDelayUntilImpl
+
+#endif /* if ( ( INCLUDE_xTaskDelayUntil == 1 ) || ( INCLUDE_vTaskDelayUntil == 1 ) ) */
+
+/* ----------------------------------------------------------------------------------- */
+
+#if ( INCLUDE_xTaskAbortDelay == 1 )
+
+    .extern MPU_xTaskAbortDelayImpl
+    .align 4
+    .global MPU_xTaskAbortDelay
+    .type MPU_xTaskAbortDelay, function
+    MPU_xTaskAbortDelay:
+        INVOKE_SYSTEM_CALL #SYSTEM_CALL_xTaskAbortDelay, MPU_xTaskAbortDelayImpl
+
+#endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */
+
+/* ------------------------------------------------------------------------------- */
+
+#if ( INCLUDE_vTaskDelay == 1 )
+
+    .extern MPU_vTaskDelayImpl
+    .align 4
+    .global MPU_vTaskDelay
+    .type MPU_vTaskDelay, function
+    MPU_vTaskDelay:
+        INVOKE_SYSTEM_CALL #SYSTEM_CALL_vTaskDelay, MPU_vTaskDelayImpl
+
+#endif /* if ( INCLUDE_vTaskDelay == 1 ) */
+
+/* ------------------------------------------------------------------------------- */
+
+#if ( INCLUDE_uxTaskPriorityGet == 1 )
+
+    .extern MPU_uxTaskPriorityGetImpl
+    .align 4
+    .global MPU_uxTaskPriorityGet
+    .type MPU_uxTaskPriorityGet, function
+    MPU_uxTaskPriorityGet:
+        INVOKE_SYSTEM_CALL #SYSTEM_CALL_uxTaskPriorityGet, MPU_uxTaskPriorityGetImpl
+
+#endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */
+
+/* ------------------------------------------------------------------------------- */
+
+#if ( INCLUDE_eTaskGetState == 1 )
+
+    .extern MPU_eTaskGetStateImpl
+    .align 4
+    .global MPU_eTaskGetState
+    .type MPU_eTaskGetState, function
+    MPU_eTaskGetState:
+        INVOKE_SYSTEM_CALL #SYSTEM_CALL_eTaskGetState, MPU_eTaskGetStateImpl
+
+#endif /* if ( INCLUDE_eTaskGetState == 1 ) */
+
+/* ------------------------------------------------------------------------------- */
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+    .extern MPU_vTaskGetInfoImpl
+    .align 4
+    .global MPU_vTaskGetInfo
+    .type MPU_vTaskGetInfo, function
+    MPU_vTaskGetInfo:
+        INVOKE_SYSTEM_CALL #SYSTEM_CALL_vTaskGetInfo, MPU_vTaskGetInfoImpl
+
+    /* ------------------------------------------------------------------------------- */
+
+    .extern MPU_uxTaskGetSystemStateImpl
+    .align 4
+    .global MPU_uxTaskGetSystemState
+    .type MPU_uxTaskGetSystemState, function
+    MPU_uxTaskGetSystemState:
+        INVOKE_SYSTEM_CALL #SYSTEM_CALL_uxTaskGetSystemState, MPU_uxTaskGetSystemStateImpl
+
+    /* ------------------------------------------------------------------------------- */
+
+    .extern MPU_uxEventGroupGetNumberImpl
+    .align 4
+    .global MPU_uxEventGroupGetNumber
+    .type MPU_uxEventGroupGetNumber, function
+    MPU_uxEventGroupGetNumber:
+    INVOKE_SYSTEM_CALL #SYSTEM_CALL_uxEventGroupGetNumber, MPU_uxEventGroupGetNumberImpl
+
+    /* ------------------------------------------------------------------------------- */
+
+    .extern MPU_vEventGroupSetNumberImpl
+    .align 4
+    .global MPU_vEventGroupSetNumber
+    .type MPU_vEventGroupSetNumber, function
+    MPU_vEventGroupSetNumber:
+        INVOKE_SYSTEM_CALL #SYSTEM_CALL_vEventGroupSetNumber, MPU_vEventGroupSetNumberImpl
+
+    /* ------------------------------------------------------------------------------- */
+
+#endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
+
+/* ------------------------------------------------------------------------------- */
+
+#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
+
+    .extern MPU_xTaskGetIdleTaskHandleImpl
+    .align 4
+    .global MPU_xTaskGetIdleTaskHandle
+    .type MPU_xTaskGetIdleTaskHandle, function
+    MPU_xTaskGetIdleTaskHandle:
+        INVOKE_SYSTEM_CALL #SYSTEM_CALL_xTaskGetIdleTaskHandle, MPU_xTaskGetIdleTaskHandleImpl
+
+
+#endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */
+
+/* ------------------------------------------------------------------------------- */
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+    .extern MPU_vTaskSuspendImpl
+    .align 4
+    .global MPU_vTaskSuspend
+    .type MPU_vTaskSuspend, function
+    MPU_vTaskSuspend:
+        INVOKE_SYSTEM_CALL #SYSTEM_CALL_vTaskSuspend, MPU_vTaskSuspendImpl
+
+    /* ------------------------------------------------------------------------------- */
+
+    .extern MPU_vTaskResumeImpl
+    .align 4
+    .global MPU_vTaskResume
+    .type MPU_vTaskResume, function
+    MPU_vTaskResume:
+        INVOKE_SYSTEM_CALL #SYSTEM_CALL_vTaskResume, MPU_vTaskResumeImpl
+
+    /* ------------------------------------------------------------------------------- */
+
+#endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
+
+/* ------------------------------------------------------------------------------- */
+
+#if ( configGENERATE_RUN_TIME_STATS == 1 )
+
+    .extern MPU_ulTaskGetRunTimeCounterImpl
+    .align 4
+    .global MPU_ulTaskGetRunTimeCounter
+    .type MPU_ulTaskGetRunTimeCounter, function
+    MPU_ulTaskGetRunTimeCounter:
+        INVOKE_SYSTEM_CALL #SYSTEM_CALL_ulTaskGetRunTimeCounter, MPU_ulTaskGetRunTimeCounterImpl
+
+    /* ------------------------------------------------------------------------------- */
+
+    .extern MPU_ulTaskGetRunTimePercentImpl
+    .align 4
+    .global MPU_ulTaskGetRunTimePercent
+    .type MPU_ulTaskGetRunTimePercent, function
+    MPU_ulTaskGetRunTimePercent:
+        INVOKE_SYSTEM_CALL #SYSTEM_CALL_ulTaskGetRunTimePercent, MPU_ulTaskGetRunTimePercentImpl
+
+    /* ------------------------------------------------------------------------------- */
+
+    #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
+
+        .extern MPU_ulTaskGetIdleRunTimePercentImpl
+        .align 4
+        .global MPU_ulTaskGetIdleRunTimePercent
+        .type MPU_ulTaskGetIdleRunTimePercent, function
+        MPU_ulTaskGetIdleRunTimePercent:
+            INVOKE_SYSTEM_CALL #SYSTEM_CALL_ulTaskGetIdleRunTimePercent, MPU_ulTaskGetIdleRunTimePercentImpl
+
+        /* --------------------------------------------------------------------------- */
+
+        .extern MPU_ulTaskGetIdleRunTimeCounterImpl
+        .align 4
+        .global MPU_ulTaskGetIdleRunTimeCounter
+        .type MPU_ulTaskGetIdleRunTimeCounter, function
+        MPU_ulTaskGetIdleRunTimeCounter:
+            INVOKE_SYSTEM_CALL #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter, MPU_ulTaskGetIdleRunTimeCounterImpl
+
+        /* --------------------------------------------------------------------------- */
+
+    #endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */
+
+#endif /* if ( configGENERATE_RUN_TIME_STATS == 1 )*/
+
+/* --------------------------------------------------------------------------- */
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+    .extern MPU_vTaskSetApplicationTaskTagImpl
+    .align 4
+    .global MPU_vTaskSetApplicationTaskTag
+    .type MPU_vTaskSetApplicationTaskTag, function
+    MPU_vTaskSetApplicationTaskTag:
+        INVOKE_SYSTEM_CALL #SYSTEM_CALL_vTaskSetApplicationTaskTag, MPU_vTaskSetApplicationTaskTagImpl
+
+    /* ------------------------------------------------------------------------------- */
+
+    .extern MPU_xTaskGetApplicationTaskTagImpl
+    .align 4
+    .global MPU_xTaskGetApplicationTaskTag
+    .type MPU_xTaskGetApplicationTaskTag, function
+    MPU_xTaskGetApplicationTaskTag:
+        INVOKE_SYSTEM_CALL #SYSTEM_CALL_xTaskGetApplicationTaskTag, MPU_xTaskGetApplicationTaskTagImpl
+
+    /* ------------------------------------------------------------------------------- */
+
+#endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
+
+/* ------------------------------------------------------------------------------- */
+
+#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+
+    .extern MPU_vTaskSetThreadLocalStoragePointerImpl
+    .align 4
+    .global MPU_vTaskSetThreadLocalStoragePointer
+    .type MPU_vTaskSetThreadLocalStoragePointer, function
+    MPU_vTaskSetThreadLocalStoragePointer:
+        INVOKE_SYSTEM_CALL #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer, MPU_vTaskSetThreadLocalStoragePointerImpl
+
+    /* ------------------------------------------------------------------------------- */
+
+    .extern MPU_pvTaskGetThreadLocalStoragePointerImpl
+    .align 4
+    .global MPU_pvTaskGetThreadLocalStoragePointer
+    .type MPU_pvTaskGetThreadLocalStoragePointer, function
+    MPU_pvTaskGetThreadLocalStoragePointer:
+        INVOKE_SYSTEM_CALL #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer, MPU_pvTaskGetThreadLocalStoragePointerImpl
+
+    /* ------------------------------------------------------------------------------- */
+
+#endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
+
+/* ------------------------------------------------------------------------------- */
+
+#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
+
+    .extern MPU_uxTaskGetStackHighWaterMarkImpl
+    .align 4
+    .global MPU_uxTaskGetStackHighWaterMark
+    .type MPU_uxTaskGetStackHighWaterMark, function
+    MPU_uxTaskGetStackHighWaterMark:
+        INVOKE_SYSTEM_CALL #SYSTEM_CALL_uxTaskGetStackHighWaterMark, MPU_uxTaskGetStackHighWaterMarkImpl
+
+#endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */
+
+/* ------------------------------------------------------------------------------- */
+
+#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
+
+    .extern MPU_uxTaskGetStackHighWaterMark2Impl
+    .align 4
+    .global MPU_uxTaskGetStackHighWaterMark2
+    .type MPU_uxTaskGetStackHighWaterMark2, function
+    MPU_uxTaskGetStackHighWaterMark2:
+        INVOKE_SYSTEM_CALL #SYSTEM_CALL_uxTaskGetStackHighWaterMark2, MPU_uxTaskGetStackHighWaterMark2Impl
+
+#endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */
+
+/* ------------------------------------------------------------------------------- */
+
+#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
+
+    .extern MPU_xTaskGetCurrentTaskHandleImpl
+    .align 4
+    .global MPU_xTaskGetCurrentTaskHandle
+    .type MPU_xTaskGetCurrentTaskHandle, function
+    MPU_xTaskGetCurrentTaskHandle:
+        INVOKE_SYSTEM_CALL #SYSTEM_CALL_xTaskGetCurrentTaskHandle, MPU_xTaskGetCurrentTaskHandleImpl
+
+#endif /* if( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
+
+/* ------------------------------------------------------------------------------- */
+
+#if ( INCLUDE_xTaskGetSchedulerState == 1 )
+
+    .extern MPU_xTaskGetSchedulerStateImpl
+    .align 4
+    .global MPU_xTaskGetSchedulerState
+    .type MPU_xTaskGetSchedulerState, function
+    MPU_xTaskGetSchedulerState:
+        INVOKE_SYSTEM_CALL #SYSTEM_CALL_xTaskGetSchedulerState, MPU_xTaskGetSchedulerStateImpl
+
+
+#endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */
+
+/* ------------------------------------------------------------------------------- */
+
+#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+
+    .extern MPU_xQueueGetMutexHolderImpl
+    .align 4
+    .global MPU_xQueueGetMutexHolder
+    .type MPU_xQueueGetMutexHolder, function
+    MPU_xQueueGetMutexHolder:
+        INVOKE_SYSTEM_CALL #SYSTEM_CALL_xQueueGetMutexHolder, MPU_xQueueGetMutexHolderImpl
+
+#endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */
+
+/* ------------------------------------------------------------------------------- */
+
+#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+
+    .extern MPU_xQueueTakeMutexRecursiveImpl
+    .align 4
+    .global MPU_xQueueTakeMutexRecursive
+    .type MPU_xQueueTakeMutexRecursive, function
+    MPU_xQueueTakeMutexRecursive:
+        INVOKE_SYSTEM_CALL #SYSTEM_CALL_xQueueTakeMutexRecursive, MPU_xQueueTakeMutexRecursiveImpl
+
+    /* ------------------------------------------------------------------------------- */
+
+    .extern MPU_xQueueGiveMutexRecursiveImpl
+    .align 4
+    .global MPU_xQueueGiveMutexRecursive
+    .type MPU_xQueueGiveMutexRecursive, function
+    MPU_xQueueGiveMutexRecursive:
+        INVOKE_SYSTEM_CALL #SYSTEM_CALL_xQueueGiveMutexRecursive, MPU_xQueueGiveMutexRecursiveImpl
+
+    /* ------------------------------------------------------------------------------- */
+
+#endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+
+/* ------------------------------------------------------------------------------- */
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+    .extern MPU_xQueueSelectFromSetImpl
+    .align 4
+    .global MPU_xQueueSelectFromSet
+    .type MPU_xQueueSelectFromSet, function
+    MPU_xQueueSelectFromSet:
+        INVOKE_SYSTEM_CALL #SYSTEM_CALL_xQueueSelectFromSet, MPU_xQueueSelectFromSetImpl
+
+    /* ------------------------------------------------------------------------------- */
+
+    .extern MPU_xQueueAddToSetImpl
+    .align 4
+    .global MPU_xQueueAddToSet
+    .type MPU_xQueueAddToSet, function
+    MPU_xQueueAddToSet:
+        INVOKE_SYSTEM_CALL #SYSTEM_CALL_xQueueAddToSet, MPU_xQueueAddToSetImpl
+
+    /* ------------------------------------------------------------------------------- */
+
+#endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+
+/* ------------------------------------------------------------------------------- */
+
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+    .extern MPU_vQueueAddToRegistryImpl
+    .align 4
+    .global MPU_vQueueAddToRegistry
+    .type MPU_vQueueAddToRegistry, function
+    MPU_vQueueAddToRegistry:
+        INVOKE_SYSTEM_CALL #SYSTEM_CALL_vQueueAddToRegistry, MPU_vQueueAddToRegistryImpl
+
+    /* ------------------------------------------------------------------------------- */
+
+    .extern MPU_vQueueUnregisterQueueImpl
+    .align 4
+    .global MPU_vQueueUnregisterQueue
+    .type MPU_vQueueUnregisterQueue, function
+    MPU_vQueueUnregisterQueue:
+        INVOKE_SYSTEM_CALL #SYSTEM_CALL_vQueueUnregisterQueue, MPU_vQueueUnregisterQueueImpl
+
+    /* ------------------------------------------------------------------------------- */
+
+    .extern MPU_pcQueueGetNameImpl
+    .align 4
+    .global MPU_pcQueueGetName
+    .type MPU_pcQueueGetName, function
+    MPU_pcQueueGetName:
+        INVOKE_SYSTEM_CALL #SYSTEM_CALL_pcQueueGetName, MPU_pcQueueGetNameImpl
+
+    /* ------------------------------------------------------------------------------- */
+
+#endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+
+/* ------------------------------------------------------------------------------- */
+
+#if ( configUSE_TIMERS == 1 )
+
+    .extern MPU_pvTimerGetTimerIDImpl
+    .align 4
+    .global MPU_pvTimerGetTimerID
+    .type MPU_pvTimerGetTimerID, function
+    MPU_pvTimerGetTimerID:
+        INVOKE_SYSTEM_CALL #SYSTEM_CALL_pvTimerGetTimerID, MPU_pvTimerGetTimerIDImpl
+
+    /* ------------------------------------------------------------------------------- */
+
+    .extern MPU_vTimerSetTimerIDImpl
+    .align 4
+    .global MPU_vTimerSetTimerID
+    .type MPU_vTimerSetTimerID, function
+    MPU_vTimerSetTimerID:
+        INVOKE_SYSTEM_CALL #SYSTEM_CALL_vTimerSetTimerID, MPU_vTimerSetTimerIDImpl
+
+    /* ------------------------------------------------------------------------------- */
+
+    .extern MPU_xTimerIsTimerActiveImpl
+    .align 4
+    .global MPU_xTimerIsTimerActive
+    .type MPU_xTimerIsTimerActive, function
+    MPU_xTimerIsTimerActive:
+        INVOKE_SYSTEM_CALL #SYSTEM_CALL_xTimerIsTimerActive, MPU_xTimerIsTimerActiveImpl
+
+    /* ------------------------------------------------------------------------------- */
+
+    .extern MPU_xTimerGetTimerDaemonTaskHandleImpl
+    .align 4
+    .global MPU_xTimerGetTimerDaemonTaskHandle
+    .type MPU_xTimerGetTimerDaemonTaskHandle, function
+    MPU_xTimerGetTimerDaemonTaskHandle:
+        INVOKE_SYSTEM_CALL #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle, MPU_xTimerGetTimerDaemonTaskHandleImpl
+
+    /* ------------------------------------------------------------------------------- */
+
+    .extern MPU_xTimerGenericCommandFromTaskImpl
+    .align 4
+    .global MPU_xTimerGenericCommandFromTaskEntry
+    .type MPU_xTimerGenericCommandFromTaskEntry, function
+    MPU_xTimerGenericCommandFromTaskEntry:
+        INVOKE_SYSTEM_CALL #SYSTEM_CALL_xTimerGenericCommandFromTask, MPU_xTimerGenericCommandFromTaskImpl
+
+    /* ------------------------------------------------------------------------------- */
+
+    .extern MPU_pcTimerGetNameImpl
+    .align 4
+    .global MPU_pcTimerGetName
+    .type MPU_pcTimerGetName, function
+    MPU_pcTimerGetName:
+        INVOKE_SYSTEM_CALL #SYSTEM_CALL_pcTimerGetName, MPU_pcTimerGetNameImpl
+
+    /* ------------------------------------------------------------------------------- */
+
+    .extern MPU_vTimerSetReloadModeImpl
+    .align 4
+    .global MPU_vTimerSetReloadMode
+    .type MPU_vTimerSetReloadMode, function
+    MPU_vTimerSetReloadMode:
+        INVOKE_SYSTEM_CALL #SYSTEM_CALL_vTimerSetReloadMode, MPU_vTimerSetReloadModeImpl
+
+    /* ------------------------------------------------------------------------------- */
+
+    .extern MPU_xTimerGetReloadModeImpl
+    .align 4
+    .global MPU_xTimerGetReloadMode
+    .type MPU_xTimerGetReloadMode, function
+    MPU_xTimerGetReloadMode:
+        INVOKE_SYSTEM_CALL #SYSTEM_CALL_xTimerGetReloadMode, MPU_xTimerGetReloadModeImpl
+
+    /* ------------------------------------------------------------------------------- */
+
+    .extern MPU_uxTimerGetReloadModeImpl
+    .align 4
+    .global MPU_uxTimerGetReloadMode
+    .type MPU_uxTimerGetReloadMode, function
+    MPU_uxTimerGetReloadMode:
+        INVOKE_SYSTEM_CALL #SYSTEM_CALL_uxTimerGetReloadMode, MPU_uxTimerGetReloadModeImpl
+
+    /* ------------------------------------------------------------------------------- */
+
+    .extern MPU_xTimerGetPeriodImpl
+    .align 4
+    .global MPU_xTimerGetPeriod
+    .type MPU_xTimerGetPeriod, function
+    MPU_xTimerGetPeriod:
+        INVOKE_SYSTEM_CALL #SYSTEM_CALL_xTimerGetPeriod, MPU_xTimerGetPeriodImpl
+
+    /* ------------------------------------------------------------------------------- */
+
+    .extern MPU_xTimerGetExpiryTimeImpl
+    .align 4
+    .global MPU_xTimerGetExpiryTime
+    .type MPU_xTimerGetExpiryTime, function
+    MPU_xTimerGetExpiryTime:
+        INVOKE_SYSTEM_CALL #SYSTEM_CALL_xTimerGetExpiryTime, MPU_xTimerGetExpiryTimeImpl
+
+    /* ------------------------------------------------------------------------------- */
+
+#endif /* if ( configUSE_TIMERS == 1 ) */
+
+/* ------------------------------------------------------------------------------- */
+
+#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+
+    .extern MPU_xTaskGenericNotifyImpl
+    .align 4
+    .global MPU_xTaskGenericNotifyEntry
+    .type MPU_xTaskGenericNotifyEntry, function
+    MPU_xTaskGenericNotifyEntry:
+        INVOKE_SYSTEM_CALL #SYSTEM_CALL_xTaskGenericNotify, MPU_xTaskGenericNotifyImpl
+
+    /* ------------------------------------------------------------------------------- */
+
+    .extern MPU_xTaskGenericNotifyWaitImpl
+    .align 4
+    .global MPU_xTaskGenericNotifyWaitEntry
+    .type MPU_xTaskGenericNotifyWaitEntry, function
+    MPU_xTaskGenericNotifyWaitEntry:
+        INVOKE_SYSTEM_CALL #SYSTEM_CALL_xTaskGenericNotifyWait, MPU_xTaskGenericNotifyWaitImpl
+
+    /* ------------------------------------------------------------------------------- */
+
+    .extern MPU_ulTaskGenericNotifyTakeImpl
+    .align 4
+    .global MPU_ulTaskGenericNotifyTake
+    .type MPU_ulTaskGenericNotifyTake, function
+    MPU_ulTaskGenericNotifyTake:
+        INVOKE_SYSTEM_CALL #SYSTEM_CALL_ulTaskGenericNotifyTake, MPU_ulTaskGenericNotifyTakeImpl
+
+    /* ------------------------------------------------------------------------------- */
+
+    .extern MPU_xTaskGenericNotifyStateClearImpl
+    .align 4
+    .global MPU_xTaskGenericNotifyStateClear
+    .type MPU_xTaskGenericNotifyStateClear, function
+    MPU_xTaskGenericNotifyStateClear:
+        INVOKE_SYSTEM_CALL #SYSTEM_CALL_xTaskGenericNotifyStateClear, MPU_xTaskGenericNotifyStateClearImpl
+
+    /* ------------------------------------------------------------------------------- */
+
+    .extern MPU_ulTaskGenericNotifyValueClearImpl
+    .align 4
+    .global MPU_ulTaskGenericNotifyValueClear
+    .type MPU_ulTaskGenericNotifyValueClear, function
+    MPU_ulTaskGenericNotifyValueClear:
+        INVOKE_SYSTEM_CALL #SYSTEM_CALL_ulTaskGenericNotifyValueClear, MPU_ulTaskGenericNotifyValueClearImpl
+
+    /* ------------------------------------------------------------------------------- */
+
+#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+
+/* ------------------------------------------------------------------------------- */
+
+.end
diff --git a/portable/GCC/ARM_CRx_MPU/port.c b/portable/GCC/ARM_CRx_MPU/port.c
new file mode 100644
index 000000000..bef3a7854
--- /dev/null
+++ b/portable/GCC/ARM_CRx_MPU/port.c
@@ -0,0 +1,843 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers. That should only be done when
+ * task.h is included from an application file. */
+#ifndef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+    #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+#endif /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "portmacro.h"
+#include "task.h"
+#include "mpu_syscall_numbers.h"
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Max value that fits in a uint32_t type. */
+#define portUINT32_MAX    ( ~( ( uint32_t ) 0 ) )
+
+/* Check if adding a and b will result in overflow. */
+#define portADD_UINT32_WILL_OVERFLOW( a, b )    ( ( a ) > ( portUINT32_MAX - ( b ) ) )
+/* ----------------------------------------------------------------------------------- */
+
+/**
+ * @brief Variable used to keep track of critical section nesting.
+ *
+ * @ingroup Critical Sections
+ *
+ * This variable is stored as part of the task context and must be initialised
+ * to a non zero value to ensure interrupts don't inadvertently become unmasked
+ * before the scheduler starts. As it is stored as part of the task context, it
+ * will be set to 0 when the first task is started.
+ */
+PRIVILEGED_DATA volatile UBaseType_t ulCriticalNesting = 0xFFFF;
+
+/**
+ * @brief Set to 1 to pend a context switch from an ISR.
+ *
+ * @ingroup Interrupt Management
+ */
+PRIVILEGED_DATA volatile UBaseType_t ulPortYieldRequired = pdFALSE;
+
+/**
+ * @brief Interrupt nesting depth, used to count the number of interrupts to unwind.
+ *
+ * @ingroup Interrupt Management
+ */
+PRIVILEGED_DATA volatile UBaseType_t ulPortInterruptNesting = 0UL;
+
+/**
+ * @brief Variable to track whether or not the scheduler has been started.
+ *
+ * @ingroup Scheduler
+ *
+ * This is the port specific version of the xSchedulerRunning in tasks.c.
+ */
+PRIVILEGED_DATA static BaseType_t prvPortSchedulerRunning = pdFALSE;
+
+/* -------------------------- Private Function Declarations -------------------------- */
+
+/**
+ * @brief Determine if the given MPU region settings authorizes the requested
+ * access to the given buffer.
+ *
+ * @ingroup Task Context
+ * @ingroup MPU Control
+ *
+ * @param xTaskMPURegion MPU region settings.
+ * @param ulBufferStart Start address of the given buffer.
+ * @param ulBufferLength Length of the given buffer.
+ * @param ulAccessRequested Access requested.
+ *
+ * @return pdTRUE if MPU region settins authorizes the requested access to the
+ * given buffer, pdFALSE otherwise.
+ */
+PRIVILEGED_FUNCTION static BaseType_t prvMPURegionAuthorizesBuffer( const xMPU_REGION_REGISTERS * xTaskMPURegion,
+                                                                    const uint32_t ulBufferStart,
+                                                                    const uint32_t ulBufferLength,
+                                                                    const uint32_t ulAccessRequested );
+
+/**
+ * @brief Determine the smallest MPU Region Size Encoding for the given MPU
+ * region size.
+ *
+ * @ingroup MPU Control
+ *
+ * @param ulActualMPURegionSize MPU region size in bytes.
+ *
+ * @return The smallest MPU Region Size Encoding for the given MPU region size.
+ */
+PRIVILEGED_FUNCTION static uint32_t prvGetMPURegionSizeEncoding( uint32_t ulActualMPURegionSize );
+
+/**
+ * @brief Set up MPU.
+ *
+ * @ingroup MPU Control
+ */
+PRIVILEGED_FUNCTION static void prvSetupMPU( void );
+
+/* -------------------------- Exported Function Declarations -------------------------- */
+
+/**
+ * @brief Enter critical section.
+ *
+ * @ingroup Critical Section
+ */
+PRIVILEGED_FUNCTION void vPortEnterCritical( void );
+
+/**
+ * @brief Exit critical section.
+ *
+ * @ingroup Critical Section
+ */
+PRIVILEGED_FUNCTION void vPortExitCritical( void );
+
+/* ----------------------------------------------------------------------------------- */
+
+/**
+ * @brief Setup a FreeRTOS task's initial context.
+ *
+ * @ingroup Task Context
+ *
+ * @param pxTopOfStack Top of stack.
+ * @param pxCode The task function.
+ * @param pvParameters Argument passed to the task function.
+ * @param xRunPrivileged Marks if the task is privileged.
+ * @param xMPUSettings MPU settings of the task.
+ *
+ * @return Location where to restore the task's context from.
+ */
+/* PRIVILEGED_FUNCTION */
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters,
+                                     BaseType_t xRunPrivileged,
+                                     xMPU_SETTINGS * xMPUSettings )
+{
+    /* Setup the initial context of the task. The context is set exactly as
+     * expected by the portRESTORE_CONTEXT() macro. */
+    UBaseType_t ulIndex = CONTEXT_SIZE - 1U;
+
+    xSYSTEM_CALL_STACK_INFO * xSysCallInfo = NULL;
+
+    if( xRunPrivileged == pdTRUE )
+    {
+        xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
+        /* Current Program Status Register (CPSR). */
+        xMPUSettings->ulContext[ ulIndex ] = SYS_MODE;
+    }
+    else
+    {
+        xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
+        /* Current Program Status Register (CPSR). */
+        xMPUSettings->ulContext[ ulIndex ] = USER_MODE;
+    }
+
+    if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x0UL )
+    {
+        /* The task will cause the processor to start in THUMB state, set the
+         * Thumb state bit in the CPSR. */
+        xMPUSettings->ulContext[ ulIndex ] |= portTHUMB_MODE_BIT;
+    }
+
+    ulIndex--;
+
+    xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) pxCode; /* PC. */
+    ulIndex--;
+
+    xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
+    ulIndex--;
+
+    xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) pxTopOfStack; /* SP. */
+    ulIndex--;
+
+    /* General Purpose Registers. */
+    xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0x12121212; /* R12. */
+    ulIndex--;
+    xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0x11111111; /* R11. */
+    ulIndex--;
+    xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0x10101010; /* R10. */
+    ulIndex--;
+    xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0x09090909; /* R9. */
+    ulIndex--;
+    xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0x08080808; /* R8. */
+    ulIndex--;
+    xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0x07070707; /* R7. */
+    ulIndex--;
+    xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0x06060606; /* R6. */
+    ulIndex--;
+    xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0x05050505; /* R5. */
+    ulIndex--;
+    xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0x04040404; /* R4. */
+    ulIndex--;
+    xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0x03030303; /* R3. */
+    ulIndex--;
+    xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0x02020202; /* R2. */
+    ulIndex--;
+    xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0x01010101; /* R1. */
+    ulIndex--;
+    xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) pvParameters; /* R0. */
+    ulIndex--;
+
+    #if( portENABLE_FPU == 1 )
+    {
+        xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD0000015; /* S31. */
+        ulIndex--;
+        xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD1500000; /* S30. */
+        ulIndex--;
+        xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD0000014; /* S29. */
+        ulIndex--;
+        xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD1400000; /* S28. */
+        ulIndex--;
+        xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD0000013; /* S27. */
+        ulIndex--;
+        xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD1300000; /* S26. */
+        ulIndex--;
+        xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD0000012; /* S25. */
+        ulIndex--;
+        xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD1200000; /* S24. */
+        ulIndex--;
+        xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD0000011; /* S23. */
+        ulIndex--;
+        xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD1100000; /* S22. */
+        ulIndex--;
+        xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD0000010; /* S21. */
+        ulIndex--;
+        xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD1000000; /* S20. */
+        ulIndex--;
+        xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD0000009; /* S19. */
+        ulIndex--;
+        xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD9000000; /* S18. */
+        ulIndex--;
+        xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD0000008; /* S17. */
+        ulIndex--;
+        xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD8000000; /* S16. */
+        ulIndex--;
+        xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD0000007; /* S15. */
+        ulIndex--;
+        xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD7000000; /* S14. */
+        ulIndex--;
+        xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD0000006; /* S13. */
+        ulIndex--;
+        xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD6000000; /* S12. */
+        ulIndex--;
+        xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD0000005; /* S11. */
+        ulIndex--;
+        xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD5000000; /* S10. */
+        ulIndex--;
+        xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD0000004; /* S9. */
+        ulIndex--;
+        xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD4000000; /* S8. */
+        ulIndex--;
+        xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD0000003; /* S7. */
+        ulIndex--;
+        xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD3000000; /* S6. */
+        ulIndex--;
+        xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD0000002; /* S5. */
+        ulIndex--;
+        xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD2000000; /* S4. */
+        ulIndex--;
+        xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD0000001; /* S3. */
+        ulIndex--;
+        xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD1000000; /* S2. */
+        ulIndex--;
+        xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD0000000; /* S1. */
+        ulIndex--;
+        xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD0000000; /* S0. */
+        ulIndex--;
+
+        xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0x00000000; /* FPSR. */
+        ulIndex--;
+    }
+    #endif /* portENABLE_FPU */
+
+    /* The task will start with a critical nesting count of 0. */
+    xMPUSettings->ulContext[ ulIndex ] = portNO_CRITICAL_NESTING;
+
+    /* Ensure that the system call stack is double word aligned. */
+    xSysCallInfo = &( xMPUSettings->xSystemCallStackInfo );
+    xSysCallInfo->pulSystemCallStackPointer = &( xSysCallInfo->ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1U ] );
+    xSysCallInfo->pulSystemCallStackPointer = ( uint32_t * ) ( ( ( uint32_t ) ( xSysCallInfo->pulSystemCallStackPointer ) ) &
+                                                               ( ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ) );
+
+    /* This is not NULL only for the duration of a system call. */
+    xSysCallInfo->pulTaskStackPointer = NULL;
+
+    /* Set the System Call to return to vPortSystemCallExit. */
+    xSysCallInfo->pulSystemCallExitAddress = ( uint32_t * ) ( &vPortSystemCallExit );
+
+    /* Return the address where this task's context should be restored from. */
+    return &( xMPUSettings->ulContext[ ulIndex ] );
+}
+
+/* ----------------------------------------------------------------------------------- */
+
+/**
+ * @brief Store a FreeRTOS task's MPU settings in its TCB.
+ *
+ * @ingroup Task Context
+ * @ingroup MPU Control
+ *
+ * @param xMPUSettings The MPU settings in TCB.
+ * @param xRegions The updated MPU settings requested by the task.
+ * @param pxBottomOfStack The base address of the task's Stack.
+ * @param ulStackDepth The length of the task's stack.
+ */
+/* PRIVILEGED_FUNCTION */
+void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
+                                const struct xMEMORY_REGION * const xRegions,
+                                StackType_t * pxBottomOfStack,
+                                uint32_t ulStackDepth )
+{
+    #if defined( __ARMCC_VERSION )
+        /* Declaration when these variable are defined in code instead of being
+         * exported from linker scripts. */
+        extern uint32_t * __SRAM_segment_start__;
+        extern uint32_t * __SRAM_segment_end__;
+    #else
+        /* Declaration when these variable are exported from linker scripts. */
+        extern uint32_t __SRAM_segment_start__[];
+        extern uint32_t __SRAM_segment_end__[];
+    #endif /* if defined( __ARMCC_VERSION ) */
+
+    uint32_t ulIndex = 0x0;
+    uint32_t ulRegionLength;
+    uint32_t ulRegionLengthEncoded;
+    uint32_t ulRegionLengthDecoded;
+
+    if( xRegions == NULL )
+    {
+        /* No MPU regions are specified so allow access to all of the RAM. */
+        ulRegionLength = ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__;
+        ulRegionLengthEncoded = prvGetMPURegionSizeEncoding( ulRegionLength );
+        ulRegionLength |= portMPU_REGION_ENABLE;
+
+        /* MPU Settings is zero'd out in the TCB before this function is called.
+         * We, therefore, do not need to explicitly zero out unused MPU regions
+         * in xMPUSettings. */
+        ulIndex = portSTACK_REGION;
+
+        xMPUSettings->xRegion[ ulIndex ].ulRegionBaseAddress = ( uint32_t ) __SRAM_segment_start__;
+        xMPUSettings->xRegion[ ulIndex ].ulRegionSize = ( ulRegionLengthEncoded |
+                                                          portMPU_REGION_ENABLE );
+        xMPUSettings->xRegion[ ulIndex ].ulRegionAttribute = ( portMPU_REGION_PRIV_RW_USER_RW_NOEXEC |
+                                                               portMPU_REGION_NORMAL_OIWTNOWA_SHARED );
+    }
+    else
+    {
+        for( ulIndex = 0UL; ulIndex < portNUM_CONFIGURABLE_REGIONS; ulIndex++ )
+        {
+            /* If a length has been provided, the region is in use. */
+            if( ( xRegions[ ulIndex ] ).ulLengthInBytes > 0UL )
+            {
+                ulRegionLength = xRegions[ ulIndex ].ulLengthInBytes;
+                ulRegionLengthEncoded = prvGetMPURegionSizeEncoding( ulRegionLength );
+
+                /* MPU region base address must be aligned to the region size
+                 * boundary. */
+                ulRegionLengthDecoded = 2UL << ( ulRegionLengthEncoded >> 1UL );
+                configASSERT( ( ( ( uint32_t ) xRegions[ ulIndex ].pvBaseAddress ) % ( ulRegionLengthDecoded ) ) == 0UL );
+
+                xMPUSettings->xRegion[ ulIndex ].ulRegionBaseAddress = ( uint32_t ) xRegions[ ulIndex ].pvBaseAddress;
+                xMPUSettings->xRegion[ ulIndex ].ulRegionSize = ( ulRegionLengthEncoded |
+                                                                  portMPU_REGION_ENABLE );
+                xMPUSettings->xRegion[ ulIndex ].ulRegionAttribute = xRegions[ ulIndex ].ulParameters;
+            }
+            else
+            {
+                xMPUSettings->xRegion[ ulIndex ].ulRegionBaseAddress = 0x0UL;
+                xMPUSettings->xRegion[ ulIndex ].ulRegionSize = 0x0UL;
+                xMPUSettings->xRegion[ ulIndex ].ulRegionAttribute = 0x0UL;
+            }
+        }
+
+        /* This function is called automatically when the task is created - in
+         * which case the stack region parameters will be valid. At all other
+         * times the stack parameters will not be valid and it is assumed that the
+         * stack region has already been configured. */
+        if( ulStackDepth != 0x0UL )
+        {
+            ulRegionLengthEncoded = prvGetMPURegionSizeEncoding( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) );
+
+            /* MPU region base address must be aligned to the region size
+             * boundary. */
+            ulRegionLengthDecoded = 2UL << ( ulRegionLengthEncoded >> 1UL );
+            configASSERT( ( ( uint32_t ) pxBottomOfStack % ( ulRegionLengthDecoded ) ) == 0U );
+
+            ulIndex = portSTACK_REGION;
+            xMPUSettings->xRegion[ ulIndex ].ulRegionBaseAddress = ( uint32_t ) pxBottomOfStack;
+            xMPUSettings->xRegion[ ulIndex ].ulRegionSize = ( ulRegionLengthEncoded |
+                                                              portMPU_REGION_ENABLE );;
+            xMPUSettings->xRegion[ ulIndex ].ulRegionAttribute = ( portMPU_REGION_PRIV_RW_USER_RW_NOEXEC |
+                                                                   portMPU_REGION_NORMAL_OIWTNOWA_SHARED );
+        }
+    }
+}
+
+/* ----------------------------------------------------------------------------------- */
+
+/* PRIVILEGED_FUNCTION */
+BaseType_t xPortIsTaskPrivileged( void )
+{
+    BaseType_t xTaskIsPrivileged = pdFALSE;
+
+    /* Calling task's MPU settings. */
+    const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL );
+
+    if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+    {
+        xTaskIsPrivileged = pdTRUE;
+    }
+
+    return xTaskIsPrivileged;
+}
+
+/* ----------------------------------------------------------------------------------- */
+
+/* PRIVILEGED_FUNCTION */
+BaseType_t xPortStartScheduler( void )
+{
+    /* Start the timer that generates the tick ISR. */
+    configSETUP_TICK_INTERRUPT();
+
+    /* Configure MPU regions that are common to all tasks. */
+    prvSetupMPU();
+
+    prvPortSchedulerRunning = pdTRUE;
+
+    /* Load the context of the first task. */
+    vPortStartFirstTask();
+
+    /* Will only get here if vTaskStartScheduler() was called with the CPU in
+     * a non-privileged mode or the binary point register was not set to its lowest
+     * possible value. prvTaskExitError() is referenced to prevent a compiler
+     * warning about it being defined but not referenced in the case that the user
+     * defines their own exit address. */
+    ( void ) prvTaskExitError();
+    return pdFALSE;
+}
+
+/* ----------------------------------------------------------------------------------- */
+
+/* PRIVILEGED_FUNCTION */
+static uint32_t prvGetMPURegionSizeEncoding( uint32_t ulActualMPURegionSize )
+{
+    uint32_t ulRegionSize, ulReturnValue = 4U;
+
+    /* 32 bytes is the smallest valid region for Cortex R4 and R5 CPUs. */
+    for( ulRegionSize = 0x20UL; ulReturnValue < 0x1FUL; ( ulRegionSize <<= 1UL ) )
+    {
+        if( ulActualMPURegionSize <= ulRegionSize )
+        {
+            break;
+        }
+        else
+        {
+            ulReturnValue++;
+        }
+    }
+
+    /* Shift the code by one before returning so it can be written directly
+     * into the the correct bit position of the attribute register. */
+    return ulReturnValue << 1UL;
+}
+
+/* ----------------------------------------------------------------------------------- */
+
+/* PRIVILEGED_FUNCTION */
+static void prvSetupMPU( void )
+{
+#if defined( __ARMCC_VERSION )
+    /* Declaration when these variable are defined in code. */
+    /* Sections used for FLASH. */
+    extern uint32_t * __FLASH_segment_start__;
+    extern uint32_t * __FLASH_segment_end__;
+    extern uint32_t * __privileged_functions_start__;
+    extern uint32_t * __privileged_functions_end__;
+
+    /* Sections used for RAM. */
+    extern uint32_t * __SRAM_segment_start__;
+    extern uint32_t * __SRAM_segment_end__;
+    extern uint32_t * __privileged_data_start__;
+    extern uint32_t * __privileged_data_end__;
+#else
+    /* Declaration when these variable are exported from linker scripts. */
+    /* Sections used for FLASH. */
+    extern uint32_t __FLASH_segment_start__[];
+    extern uint32_t __FLASH_segment_end__[];
+    extern uint32_t __privileged_functions_start__[];
+    extern uint32_t __privileged_functions_end__[];
+
+    /* Sections used for RAM. */
+    extern uint32_t __SRAM_segment_start__[];
+    extern uint32_t __SRAM_segment_end__[];
+    extern uint32_t __privileged_data_start__[];
+    extern uint32_t __privileged_data_end__[];
+#endif /* if defined( __ARMCC_VERSION ) */
+
+    uint32_t ulRegionLength;
+    uint32_t ulRegionLengthEncoded;
+
+    /* Disable the MPU before programming it. */
+    vMPUDisable();
+
+    /* Priv: RX, Unpriv: RX for entire Flash. */
+    ulRegionLength = ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__;
+    ulRegionLengthEncoded = prvGetMPURegionSizeEncoding( ulRegionLength );
+    vMPUSetRegion( portUNPRIVILEGED_FLASH_REGION,
+                   ( uint32_t ) __FLASH_segment_start__,
+                   ( ulRegionLengthEncoded | portMPU_REGION_ENABLE ),
+                   ( portMPU_REGION_PRIV_RO_USER_RO_EXEC |
+                     portMPU_REGION_NORMAL_OIWTNOWA_SHARED ) );
+
+    /* Priv: RX, Unpriv: No access for privileged functions. */
+    ulRegionLength = ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __privileged_functions_start__;
+    ulRegionLengthEncoded = prvGetMPURegionSizeEncoding( ulRegionLength );
+    vMPUSetRegion( portPRIVILEGED_FLASH_REGION,
+                   ( uint32_t ) __privileged_functions_start__,
+                   ( ulRegionLengthEncoded | portMPU_REGION_ENABLE ),
+                   ( portMPU_REGION_PRIV_RO_USER_NA_EXEC |
+                     portMPU_REGION_NORMAL_OIWTNOWA_SHARED ) );
+
+    /* Priv: RW, Unpriv: No Access for privileged data. */
+    ulRegionLength = ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__;
+    ulRegionLengthEncoded = prvGetMPURegionSizeEncoding( ulRegionLength );
+    vMPUSetRegion( portPRIVILEGED_RAM_REGION,
+                   ( uint32_t ) __privileged_data_start__,
+                   ( ulRegionLengthEncoded | portMPU_REGION_ENABLE ),
+                   ( portMPU_REGION_PRIV_RW_USER_NA_NOEXEC |
+                     portMPU_REGION_PRIV_RW_USER_NA_NOEXEC ) );
+
+    /* Enable the MPU background region - it allows privileged operating modes
+     * access to unmapped regions of memory without generating a fault. */
+    vMPUEnableBackgroundRegion();
+
+    /* After setting default regions, enable the MPU. */
+    vMPUEnable();
+}
+
+/* ----------------------------------------------------------------------------------- */
+
+/* PRIVILEGED_FUNCTION */
+static BaseType_t prvMPURegionAuthorizesBuffer( const xMPU_REGION_REGISTERS * xTaskMPURegion,
+                                                const uint32_t ulBufferStart,
+                                                const uint32_t ulBufferLength,
+                                                const uint32_t ulAccessRequested )
+{
+    BaseType_t xAccessGranted = pdFALSE;
+    uint32_t ulBufferEnd;
+    uint32_t ulMPURegionLength;
+    uint32_t ulMPURegionStart;
+    uint32_t ulMPURegionEnd;
+    uint32_t ulMPURegionAccessPermissions;
+
+    if( portADD_UINT32_WILL_OVERFLOW( ulBufferStart, ( ulBufferLength - 1UL ) ) == pdFALSE )
+    {
+        ulBufferEnd = ulBufferStart + ulBufferLength - 1UL;
+        ulMPURegionLength = 2UL << ( xTaskMPURegion->ulRegionSize >> 1UL );
+        ulMPURegionStart = xTaskMPURegion->ulRegionBaseAddress;
+        ulMPURegionEnd = xTaskMPURegion->ulRegionBaseAddress + ulMPURegionLength - 1UL;
+
+        if( ( ulBufferStart >= ulMPURegionStart ) &&
+            ( ulBufferEnd <= ulMPURegionEnd ) &&
+            ( ulBufferStart <= ulBufferEnd ) )
+        {
+            ulMPURegionAccessPermissions = xTaskMPURegion->ulRegionAttribute & portMPU_REGION_AP_BITMASK;
+
+            if( ulAccessRequested == tskMPU_READ_PERMISSION ) /* RO. */
+            {
+                if( ( ulMPURegionAccessPermissions == portMPU_REGION_PRIV_RW_USER_RO ) ||
+                    ( ulMPURegionAccessPermissions == portMPU_REGION_PRIV_RO_USER_RO ) )
+                {
+                    xAccessGranted = pdTRUE;
+                }
+            }
+            else if( ( ulAccessRequested & tskMPU_WRITE_PERMISSION ) != 0UL ) /* W or RW. */
+            {
+                if( ulMPURegionAccessPermissions == portMPU_REGION_PRIV_RW_USER_RW )
+                {
+                    xAccessGranted = pdTRUE;
+                }
+            }
+        }
+    }
+
+    return xAccessGranted;
+}
+
+/* ----------------------------------------------------------------------------------- */
+
+/* PRIVILEGED_FUNCTION */
+BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
+                                            uint32_t ulBufferLength,
+                                            uint32_t ulAccessRequested )
+{
+    BaseType_t xAccessGranted = pdFALSE;
+    uint32_t ulRegionIndex;
+    xMPU_SETTINGS * xTaskMPUSettings = NULL;
+
+    if( prvPortSchedulerRunning == pdFALSE )
+    {
+        /* Grant access to all the memory before the scheduler is started. It is
+         * necessary because there is no task running yet and therefore, we
+         * cannot use the permissions of any task. */
+        xAccessGranted = pdTRUE;
+    }
+    else
+    {
+        /* Calling task's MPU settings. */
+        xTaskMPUSettings = xTaskGetMPUSettings( NULL );
+
+        if( ( xTaskMPUSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+        {
+            /* Privileged tasks have access to all the memory. */
+            xAccessGranted = pdTRUE;
+        }
+        else
+        {
+            for( ulRegionIndex = 0x0UL; ulRegionIndex < portTOTAL_NUM_REGIONS_IN_TCB; ulRegionIndex++ )
+            {
+                xAccessGranted = prvMPURegionAuthorizesBuffer( &( xTaskMPUSettings->xRegion[ ulRegionIndex ] ),
+                                                               ( uint32_t ) pvBuffer,
+                                                               ulBufferLength,
+                                                               ulAccessRequested );
+
+                if( xAccessGranted == pdTRUE )
+                {
+                    break;
+                }
+            }
+        }
+    }
+
+    return xAccessGranted;
+}
+
+/* ----------------------------------------------------------------------------------- */
+
+#if( configENABLE_ACCESS_CONTROL_LIST == 1 )
+
+/* PRIVILEGED_FUNCTION */
+BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject )
+{
+    uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+    BaseType_t xAccessGranted = pdFALSE;
+    const xMPU_SETTINGS * xTaskMpuSettings;
+
+    if( prvPortSchedulerRunning == pdFALSE )
+    {
+        /* Grant access to all the kernel objects before the scheduler
+         * is started. It is necessary because there is no task running
+         * yet and therefore, we cannot use the permissions of any
+         * task. */
+        xAccessGranted = pdTRUE;
+    }
+    else
+    {
+        /* Calling task's MPU settings. */
+        xTaskMpuSettings = xTaskGetMPUSettings( NULL );
+
+        ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject
+                                          / portACL_ENTRY_SIZE_BITS );
+        ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject
+                                        % portACL_ENTRY_SIZE_BITS );
+
+        if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+        {
+            xAccessGranted = pdTRUE;
+        }
+        else
+        {
+            if( ( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] ) &
+                  ( 1U << ulAccessControlListEntryBit ) ) != 0UL )
+            {
+                xAccessGranted = pdTRUE;
+            }
+        }
+    }
+
+    return xAccessGranted;
+}
+
+#else
+
+/* PRIVILEGED_FUNCTION */
+BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject )
+{
+    ( void ) lInternalIndexOfKernelObject;
+
+    /* If Access Control List feature is not used, all the tasks have
+     * access to all the kernel objects. */
+    return pdTRUE;
+}
+
+#endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+/* ----------------------------------------------------------------------------------- */
+
+#if( configENABLE_ACCESS_CONTROL_LIST == 1 )
+
+/* PRIVILEGED_FUNCTION */
+void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+                                     int32_t lInternalIndexOfKernelObject )
+{
+    uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+    xMPU_SETTINGS * xTaskMpuSettings;
+
+    ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject
+                                      / portACL_ENTRY_SIZE_BITS );
+    ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject
+                                    % portACL_ENTRY_SIZE_BITS );
+
+    xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+    xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit );
+}
+
+#endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+/* ----------------------------------------------------------------------------------- */
+
+#if( configENABLE_ACCESS_CONTROL_LIST == 1 )
+
+/* PRIVILEGED_FUNCTION */
+void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+                                      int32_t lInternalIndexOfKernelObject )
+{
+    uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+    xMPU_SETTINGS * xTaskMpuSettings;
+
+    ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject
+                                      / portACL_ENTRY_SIZE_BITS );
+    ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject
+                                    % portACL_ENTRY_SIZE_BITS );
+
+    xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+    xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit );
+}
+
+#endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+/* ----------------------------------------------------------------------------------- */
+
+void prvTaskExitError( void )
+{
+    /* A function that implements a task must not exit or attempt to return to
+     * its caller as there is nothing to return to. If a task wants to exit it
+     * should instead call vTaskDelete( NULL ).
+     *
+     * Artificially force an assert() to be triggered if configASSERT() is
+     * defined, then stop here so application writers can catch the error. */
+    configASSERT( ulPortInterruptNesting == ~0UL );
+
+    for( ;; )
+    {
+    }
+}
+
+/* ----------------------------------------------------------------------------------- */
+
+void vPortEndScheduler( void )
+{
+    prvPortSchedulerRunning = pdFALSE;
+
+    /* Not implemented in this port. Artificially force an assert. */
+    configASSERT( prvPortSchedulerRunning == pdTRUE );
+}
+
+/* ----------------------------------------------------------------------------------- */
+
+/* PRIVILEGED_FUNCTION */
+void vPortEnterCritical( void )
+{
+    portDISABLE_INTERRUPTS();
+
+    /* Now that interrupts are disabled, ulCriticalNesting can be accessed
+     * directly.  Increment ulCriticalNesting to keep a count of how many times
+     * portENTER_CRITICAL() has been called. */
+    ulCriticalNesting++;
+
+    /* This is not the interrupt safe version of the enter critical function so
+     * assert() if it is being called from an interrupt context.  Only API
+     * functions that end in "FromISR" can be used in an interrupt.  Only assert
+     * if the critical nesting count is 1 to protect against recursive calls if
+     * the assert function also uses a critical section. */
+    if( ulCriticalNesting == 1 )
+    {
+        configASSERT( ulPortInterruptNesting == 0 );
+    }
+}
+/* ----------------------------------------------------------------------------------- */
+
+/* PRIVILEGED_FUNCTION */
+void vPortExitCritical( void )
+{
+    if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+    {
+        /* Decrement the nesting count as the critical section is being
+         * exited. */
+        ulCriticalNesting--;
+
+        /* If the nesting level has reached zero then all interrupt
+         * priorities must be re-enabled. */
+        if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+        {
+            /* Critical nesting has reached zero so all interrupt priorities
+             * should be unmasked. */
+            portENABLE_INTERRUPTS();
+        }
+    }
+}
+/* ----------------------------------------------------------------------------------- */
diff --git a/portable/GCC/ARM_CRx_MPU/portASM.S b/portable/GCC/ARM_CRx_MPU/portASM.S
new file mode 100644
index 000000000..cac0fc406
--- /dev/null
+++ b/portable/GCC/ARM_CRx_MPU/portASM.S
@@ -0,0 +1,498 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+    .arm
+    .syntax unified
+    .section privileged_functions
+
+#define FREERTOS_ASSEMBLY
+    #include "portmacro_asm.h"
+    #include "mpu_syscall_numbers.h"
+#undef FREERTOS_ASSEMBLY
+
+    /* External FreeRTOS-Kernel variables. */
+    .extern pxCurrentTCB
+    .extern uxSystemCallImplementations
+    .extern ulPortInterruptNesting
+    .extern ulPortYieldRequired
+
+    /* External Llnker script variables. */
+    .extern __syscalls_flash_start__
+    .extern __syscalls_flash_end__
+
+    /* External FreeRTOS-Kernel functions. */
+    .extern vTaskSwitchContext
+    .extern vApplicationIRQHandler
+
+/* ----------------------------------------------------------------------------------- */
+
+/* Save the context of a FreeRTOS Task. */
+.macro portSAVE_CONTEXT
+    DSB
+    ISB
+    /* Push R0 and LR to the stack for current mode. */
+    PUSH    { R0, LR }
+
+    LDR     LR, =pxCurrentTCB   /* LR = &( pxCurrentTCB ). */
+    LDR     LR, [LR]            /* LR = pxCurrentTCB. */
+    LDR     LR, [LR]            /* LR = pxTopOfStack i.e. the address where to store the task context. */
+
+    LDR     R0, =ulCriticalNesting  /* R0 = &( ulCriticalNesting ). */
+    LDR     R0, [R0]                /* R0 = ulCriticalNesting. */
+    STM     LR!, { R0 }             /* Store ulCriticalNesting. ! increments LR after storing. */
+
+#if ( portENABLE_FPU == 1 )
+    VMRS    R0, FPSCR       /* R0 = FPSCR. */
+    STM     LR!, { R0 }     /* Store FPSCR. */
+    VSTM    LR!, { D0-D15 } /* Store D0-D15. */
+#endif /* ( portENABLE_FPU == 1 ) */
+
+    POP     { R0 }  /* Restore R0 to pre-exception value. */
+    /* STM (user registers) - In a PL1 mode other than System mode, STM (user
+     * registers) instruction stores multiple User mode registers to
+     * consecutive memory locations using an address from a base register. The
+     * processor reads the base register value normally, using the current mode
+     * to determine the correct Banked version of the register. This instruction
+     * cannot writeback to the base register.
+     *
+     * The following can be derived from the above description:
+     * - The macro portSAVE_CONTEXT MUST be called from a PL1 mode other than
+     *   the System mode.
+     * - Base register LR of the current mode will be used which contains the
+     *   location to store the context.
+     * - It will store R0-R14 of User mode i.e. pre-exception SP(R13) and LR(R14)
+     *   will be stored. */
+    STM     LR, { R0-R14 }^
+    ADD     LR, LR, #60 /* R0-R14 - Total 155 register, each 4 byte wide. */
+
+    POP     { R0 }          /* Pre-exception PC is in R0. */
+    MRS     R1, SPSR        /* R1 = Pre-exception CPSR. */
+    STM     LR!, { R0-R1 }  /* Store pre-exception PC and CPSR. */
+
+.endm
+
+/* ----------------------------------------------------------------------------------- */
+
+/* Restore the context of a FreeRTOS Task. */
+.macro portRESTORE_CONTEXT
+    /* Load the pointer to the current task's Task Control Block (TCB). */
+    LDR     LR, =pxCurrentTCB   /* LR = &( pxCurrentTCB ). */
+    LDR     LR, [LR]            /* LR = pxCurrentTCB. */
+    ADD     R1, LR, #0x4        /* R1 now points to the xMPUSettings in TCB. */
+    LDR     LR, [LR]            /* LR = pxTopOfStack i.e. the address where to restore the task context from. */
+
+    /* When creating a loop label in a macro it has to be a numeric label.
+     * for( R5 = portFIRST_CONFIGURABLE_REGION ; R5 <= portNUM_CONFIGURABLE_REGIONS ; R5++ ) */
+    MOV     R5, #portFIRST_CONFIGURABLE_REGION
+    123:
+        LDMIA   R1!, { R2-R4 }  /* R2 = ulRegionSize, R3 = ulRegionAttribute, R4 = ulRegionBaseAddress. */
+
+        MCR     p15, #0, R5, c6, c2, #0 /* MPU Region Number Register. */
+        MCR     p15, #0, R4, c6, c1, #0 /* MPU Region Base Address Register. */
+        MCR     p15, #0, R3, c6, c1, #4 /* MPU Region Access Control Register. */
+        MCR     p15, #0, R2, c6, c1, #2 /* MPU Region Size and Enable Register. */
+
+        ADD     R5, R5, #1
+        CMP     R5, #portNUM_CONFIGURABLE_REGIONS
+        BLE     123b
+
+    LDR     R1, =ulCriticalNesting /* R1 = &( ulCriticalNesting ). */
+    LDM     LR!, { R2 }            /* R2 = Stored ulCriticalNesting. */
+    STR     R2, [R1]               /* Restore ulCriticalNesting. */
+
+#if ( portENABLE_FPU == 1 )
+    LDM     LR!, { R1 }     /* R1 = Stored FPSCR.  */
+    VMSR    FPSCR, R1       /* Restore FPSCR. */
+    VLDM   LR!, { D0-D15 }  /* Restore D0-D15. */
+#endif /* portENABLE_FPU*/
+
+    /* LDM (User registers) - In a PL1 mode other than System mode, LDM (User
+     * registers) loads multiple User mode registers from consecutive memory
+     * locations using an address from a base register. The registers loaded
+     * cannot include the PC. The processor reads the base register value
+     * normally, using the current mode to determine the correct Banked version
+     * of the register. This instruction cannot writeback to the base register.
+     *
+     *  The following can be derived from the above description:
+     * - The macro portRESTORE_CONTEXT MUST be called from a PL1 mode other than
+     *   the System mode.
+     * - Base register LR of the current mode will be used which contains the
+     *   location to restore the context from.
+     * - It will restore R0-R14 of User mode i.e. SP(R13) and LR(R14) of User
+     *   mode will be restored.
+     */
+    LDM     LR, { R0-R14 }^
+    ADD     LR, LR, #60 /* R0-R14 - Total 155 register, each 4 byte wide. */
+
+    RFE     LR  /* Restore PC and CPSR from the context. */
+
+.endm
+
+/* ----------------------------------------------------------------------------------- */
+
+/*
+ * void vPortStartFirstTask( void );
+ */
+.align 4
+.global vPortStartFirstTask
+.type vPortStartFirstTask, %function
+vPortStartFirstTask:
+    /* This function is called from System Mode to start the FreeRTOS-Kernel.
+     * As described in the portRESTORE_CONTEXT macro, portRESTORE_CONTEXT cannot
+     * be called from the System mode. We, therefore, switch to the Supervisor
+     * mode before calling portRESTORE_CONTEXT. */
+    CPS #SVC_MODE
+    portRESTORE_CONTEXT
+
+/* ----------------------------------------------------------------------------------- */
+
+.align 4
+.global FreeRTOS_SVC_Handler
+.type FreeRTOS_SVC_Handler, %function
+FreeRTOS_SVC_Handler:
+    PUSH    { R11-R12 }
+
+    /* ------------------------- Caller Flash Location Check ------------------------- */
+
+    LDR     R11, =__syscalls_flash_start__
+    LDR     R12, =__syscalls_flash_end__
+    CMP     LR, R11 /* If SVC instruction address is less than __syscalls_flash_start__, exit. */
+    BLT     svcHandlerExit
+    CMP     LR, R12 /* If SVC instruction address is greater than __syscalls_flash_end__, exit. */
+    BGT     svcHandlerExit
+
+    /* ---------------------------- Get Caller SVC Number ---------------------------- */
+
+    MRS     R11, SPSR               /* LR = CPSR at the time of SVC. */
+    TST     R11, #0x20              /* Check Thumb bit (5) in CPSR. */
+    LDRHNE  R11, [LR, #-0x2]        /* If Thumb, load halfword. */
+    BICNE   R11, R11, #0xFF00       /* And extract immidiate field (i.e. SVC number). */
+    LDREQ   R11, [LR, #-0x4]        /* If ARM, load word. */
+    BICEQ   R11, R11, #0xFF000000   /* And extract immidiate field (i.e. SVC number). */
+
+    /* --------------------------------- SVC Routing --------------------------------- */
+
+    /* If SVC Number < #NUM_SYSTEM_CALLS, go to svcSystemCallEnter. */
+    CMP     R11, #NUM_SYSTEM_CALLS
+    BLT     svcSystemCallEnter
+
+    /* If SVC Number == #portSVC_SYSTEM_CALL_EXIT, go to svcSystemCallExit. */
+    CMP     R11, #portSVC_SYSTEM_CALL_EXIT
+    BEQ     svcSystemCallExit
+
+    /* If SVC Number == #portSVC_YIELD, go to svcPortYield. */
+    CMP     R11, #portSVC_YIELD
+    BEQ     svcPortYield
+
+svcHandlerExit:
+    POP     { R11-R12 }
+    MOVS    PC, LR /* Copies the SPSR into the CPSR, performing the mode swap. */
+
+svcPortYield:
+    POP     { R11-R12 }
+    portSAVE_CONTEXT
+    BL      vTaskSwitchContext
+    portRESTORE_CONTEXT
+
+svcSystemCallExit:
+    LDR     R11, =pxCurrentTCB /* R11 = &( pxCurrentTCB ). */
+    LDR     R11, [R11]         /* R11 = pxCurrentTCB. */
+    ADD     R11, R11, #portSYSTEM_CALL_INFO_OFFSET /* R11 now points to xSystemCallStackInfo in TCB. */
+
+    /* Restore the user mode SP and LR. */
+    LDM   R11, { R13-R14 }^
+
+    AND     R12, R12, #0x0      /* R12 = 0. */
+    STR     R12, [R11]          /* xSystemCallStackInfo.pulTaskStackPointer = NULL. */
+    STR     R12, [R11, #0x4]    /* xSystemCallStackInfo.pulLinkRegisterAtSystemCallEntry = NULL. */
+
+    LDMDB   R11, { R12 }        /* R12 = ulTaskFlags. */
+
+    TST     R12, #portTASK_IS_PRIVILEGED_FLAG
+    /* If the task is privileged, we can exit now. */
+    BNE     svcHandlerExit
+    /* Otherwise, we need to switch back to User mode. */
+    MRS     R12, SPSR
+    BIC     R12, R12, #0x0F
+    MSR     SPSR_cxsf, R12
+
+    B   svcHandlerExit
+
+svcSystemCallEnter:
+    LDR     R12, =uxSystemCallImplementations /* R12 = uxSystemCallImplementations. */
+    /* R12 = uxSystemCallImplementations[ R12 + ( R11 << 2 ) ].
+     * R12 now contains the address of the system call impl function. */
+    LDR     R12, [R12, R11, lsl #2]
+
+    /* If R12 == NULL, exit. */
+    CMP     R12, #0x0
+    BEQ     svcHandlerExit
+
+    /* It is okay to clobber LR here because we do not need to return to the
+     * SVC enter location anymore. LR now contains the address of the system
+     * call impl function. */
+    MOV     LR, R12
+
+    LDR     R11, =pxCurrentTCB  /* R11 = &( pxCurrentTCB ). */
+    LDR     R11, [R11]          /* R11 = pxCurrentTCB. */
+    ADD     R11, R11, #portSYSTEM_CALL_INFO_OFFSET  /* R11 now points to xSystemCallStackInfo in TCB. */
+
+    /* Store User mode SP and LR in xSystemCallStackInfo.pulTaskStackPointer and
+     * xSystemCallStackInfo.pulLinkRegisterAtSystemCallEntry. */
+    STM     R11, { R13-R14 }^
+    ADD     R11, R11, 0x8
+
+    /* Load User mode SP an LR with xSystemCallStackInfo.pulSystemCallStackPointer
+     * and xSystemCallStackInfo.pulSystemCallExitAddress. */
+    LDM     R11, { R13-R14 }^
+
+    /* Change to SYS_MODE for the System Call. */
+    MRS     R12, SPSR
+    ORR     R12, R12, #SYS_MODE
+    MSR     SPSR_cxsf, R12
+
+    B       svcHandlerExit
+
+/* ----------------------------------------------------------------------------------- */
+
+/*
+ * void vPortDisableInterrupts( void );
+ */
+.align 4
+.global vPortDisableInterrupts
+.type vPortDisableInterrupts, %function
+vPortDisableInterrupts:
+    CPSID    I
+    BX      LR
+
+/* ----------------------------------------------------------------------------------- */
+
+/*
+ * void vPortEnableInterrupts( void );
+ */
+.align 4
+.global vPortEnableInterrupts
+.type vPortEnableInterrupts, %function
+vPortEnableInterrupts:
+    CPSIE   I
+    BX      LR
+
+/* ----------------------------------------------------------------------------------- */
+
+/*
+ * void vMPUSetRegion( uint32_t ulRegionNumber,
+ *                     uint32_t ulBaseAddress,
+ *                     uint32_t ulRegionSize,
+ *                     uint32_t ulRegionPermissions );
+ *
+ * According to the Procedure Call Standard for the ARM Architecture (AAPCS),
+ * paramters are passed in the following registers:
+ * R0 = ulRegionNumber.
+ * R1 = ulBaseAddress.
+ * R2 = ulRegionSize.
+ * R3 = ulRegionPermissions.
+ */
+.align 4
+.global vMPUSetRegion
+.type vMPUSetRegion, %function
+vMPUSetRegion:
+    AND     R0,  R0, #0x0F    /* R0 = R0 & 0x0F. Max possible region number is 15. */
+
+    MCR     p15, #0, R0, c6, c2, #0 /* MPU Region Number Register. */
+    MCR     p15, #0, R1, c6, c1, #0 /* MPU Region Base Address Register. */
+    MCR     p15, #0, R3, c6, c1, #4 /* MPU Region Access Control Register. */
+    MCR     p15, #0, R2, c6, c1, #2 /* MPU Region Size and Enable Register. */
+
+    BX      LR
+
+/* ----------------------------------------------------------------------------------- */
+
+/*
+ * void vMPUEnable( void );
+ */
+.align 4
+.global vMPUEnable
+.type vMPUEnable, %function
+vMPUEnable:
+    PUSH    { R0 }
+
+    MRC     p15, #0, R0, c1, c0, #0 /* R0 = System Control Register (SCTLR). */
+    ORR     R0,  R0, #0x1 /* R0 = R0 | 0x1. Set the M bit in SCTLR. */
+    DSB
+    MCR     p15, #0, R0, c1, c0, #0 /* SCTLR = R0. */
+    ISB
+
+    POP     { R0 }
+    BX      LR
+
+/* ----------------------------------------------------------------------------------- */
+
+/*
+ * void vMPUDisable( void );
+ */
+.align 4
+.global vMPUDisable
+.type vMPUDisable, %function
+vMPUDisable:
+    PUSH    { R0 }
+
+    MRC     p15, #0, R0, c1, c0, #0 /* R0 = System Control Register (SCTLR). */
+    BIC     R0,  R0, #1 /* R0 = R0 & ~0x1. Clear the M bit in SCTLR. */
+    /* Wait for all pending data accesses to complete. */
+    DSB
+    MCR     p15, #0, R0, c1, c0, #0 /* SCTLR = R0. */
+    /* Flush the pipeline and prefetch buffer(s) in the processor to ensure that
+    *  all following instructions are fetched from cache or memory. */
+    ISB
+
+    POP     { R0 }
+    BX      LR
+
+/* ----------------------------------------------------------------------------------- */
+
+/*
+ * void vMPUEnableBackgroundRegion( void );
+ */
+.align 4
+.global vMPUEnableBackgroundRegion
+.type vMPUEnableBackgroundRegion, %function
+vMPUEnableBackgroundRegion:
+    PUSH    { R0 }
+
+    MRC     p15, #0, R0, c1, c0, #0 /* R0 = System Control Register (SCTLR). */
+    ORR     R0, R0, #0x20000 /* R0 = R0 | 0x20000. Set the BR bit in SCTLR. */
+    MCR     p15, #0, R0, c1, c0, #0 /* SCTLR = R0. */
+
+    POP     { R0 }
+    BX      LR
+
+/* ----------------------------------------------------------------------------------- */
+
+/*
+ * void vMPUDisableBackgroundRegion( void );
+ */
+.align 4
+.global vMPUDisableBackgroundRegion
+.type vMPUDisableBackgroundRegion, %function
+vMPUDisableBackgroundRegion:
+    PUSH    { R0 }
+
+    MRC     p15, 0, R0, c1, c0, 0 /* R0 = System Control Register (SCTLR). */
+    BIC     R0, R0, #0x20000 /* R0 = R0 & ~0x20000. Clear the BR bit in SCTLR. */
+    MCR     p15, 0, R0, c1, c0, 0 /* SCTLR = R0. */
+
+    POP     { R0 }
+    BX      LR
+
+/* ----------------------------------------------------------------------------------- */
+
+.align 4
+.global FreeRTOS_IRQ_Handler
+.type FreeRTOS_IRQ_Handler, %function
+FreeRTOS_IRQ_Handler:
+    SUB     LR, LR, #4 /* Return to the interrupted instruction. */
+    SRSDB   SP!, #IRQ_MODE /* Save return state (i.e. SPSR_irq and LR_irq) to the IRQ stack. */
+
+    /* Change to supervisor mode to allow reentry. It is necessary to ensure
+     * that a BL instruction within the interrupt handler code does not
+     * overwrite LR_irq. */
+    CPS     #SVC_MODE
+
+    PUSH    { R0-R3, R12 } /* Push AAPCS callee saved registers. */
+
+    /* Update interrupt nesting count. */
+    LDR     R0, =ulPortInterruptNesting /* R0 = &( ulPortInterruptNesting ). */
+    LDR     R1, [R0] /* R1 = ulPortInterruptNesting. */
+    ADD     R2, R1, #1 /* R2 = R1 + 1. */
+    STR     R2, [R0] /* Store the updated nesting count. */
+
+    /* Call the application provided IRQ handler. */
+    PUSH    { R0-R3, LR }
+    BL      vApplicationIRQHandler
+    POP     { R0-R3, LR }
+
+    /* Disable IRQs incase vApplicationIRQHandler enabled them for re-entry. */
+    CPSID   I
+    DSB
+    ISB
+
+    /* Restore the old interrupt nesting count. R0 holds the address of
+     * ulPortInterruptNesting and R1 holds original value of
+     * ulPortInterruptNesting. */
+    STR     R1, [R0]
+
+    /* Context swtich is only performed when interrupt nesting count is 0. */
+    CMP     R1, #0
+    BNE     exit_without_switch
+
+    /* Check ulPortInterruptNesting to see if the interrupt requested a context
+     * switch. */
+    LDR     R1, =ulPortYieldRequired /* R1 = &( ulPortYieldRequired ). */
+    LDR     R0, [R1] /* R0 = ulPortYieldRequired. */
+    /* If ulPortYieldRequired != 0, goto switch_before_exit. */
+    CMP     R0, #0
+    BNE     switch_before_exit
+
+exit_without_switch:
+    POP     { R0-R3, R12 } /* Restore AAPCS callee saved registers. */
+    CPS     #IRQ_MODE
+    RFE     SP!
+
+switch_before_exit:
+    /* A context swtich is to be performed. Clear ulPortYieldRequired. R1 holds
+     * the address of ulPortYieldRequired. */
+    MOV     R0, #0
+    STR     R0, [R1]
+
+    /* Restore AAPCS callee saved registers, SPSR_irq and LR_irq before saving
+     * the task context. */
+    POP     { R0-R3, R12 }
+    CPS     #IRQ_MODE
+    /* The contents of the IRQ stack at this point is the following:
+     *       +----------+
+     *  SP+4 | SPSR_irq |
+     *       +----------+
+     *    SP |  LR_irq  |
+     *       +----------+
+     */
+    LDMIB   SP!, { LR }
+    MSR     SPSR_cxsf, LR
+    LDMDB   SP, { LR }
+    ADD     SP, SP, 0x4
+    portSAVE_CONTEXT
+
+    /* Call the function that selects the new task to execute. */
+    BLX     vTaskSwitchContext
+
+    /* Restore the context of, and branch to, the task selected to execute
+     * next. */
+    portRESTORE_CONTEXT
+
+/* ----------------------------------------------------------------------------------- */
+
+.end
diff --git a/portable/GCC/ARM_CRx_MPU/portmacro.h b/portable/GCC/ARM_CRx_MPU/portmacro.h
new file mode 100644
index 000000000..4ca649f6e
--- /dev/null
+++ b/portable/GCC/ARM_CRx_MPU/portmacro.h
@@ -0,0 +1,522 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/**
+ * @brief Functions, Defines, and Structs for use in the ARM_CRx_MPU FreeRTOS-Port
+ * @file portmacro.h
+ * @note The settings in this file configure FreeRTOS correctly for the given
+ *  hardware and compiler. These settings should not be altered.
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Include stdint for integer types of specific bit widths. */
+#include <stdint.h>
+
+/* ------------------------------ FreeRTOS Config Check ------------------------------ */
+
+#ifndef configSYSTEM_CALL_STACK_SIZE
+    #error "Define configSYSTEM_CALL_STACK_SIZE to a length, in bytes, " \
+            "to use when an unprivileged task makes a FreeRTOS Kernel call. "
+#endif /* configSYSTEM_CALL_STACK_SIZE */
+
+#if( configUSE_MPU_WRAPPERS_V1 == 1 )
+    #error This port is usable with MPU wrappers V2 only.
+#endif /* configUSE_MPU_WRAPPERS_V1 */
+
+#ifndef configSETUP_TICK_INTERRUPT
+    #error "configSETUP_TICK_INTERRUPT() must be defined in FreeRTOSConfig.h " \
+           "to call the function that sets up the tick interrupt."
+#endif /* configSETUP_TICK_INTERRUPT */
+
+/* ----------------------------------------------------------------------------------- */
+
+#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+
+    /* Check the configuration. */
+    #if( configMAX_PRIORITIES > 32 )
+        #error "configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when " \
+                "configMAX_PRIORITIES is less than or equal to 32. " \
+                "It is very rare that a system requires more than 10 to 15 difference " \
+                "priorities as tasks that share a priority will time slice."
+    #endif /* ( configMAX_PRIORITIES > 32 ) */
+
+    /**
+     * @brief Mark that a task of the given priority is ready.
+     *
+     * @ingroup Scheduler
+     *
+     * @param[in] uxPriority Priority of the task that is ready.
+     * @param[in] uxTopReadyPriority Bitmap of the ready tasks priorities.
+     */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxTopReadyPriority ) \
+        ( uxTopReadyPriority ) |= ( 1UL << ( uxPriority ) )
+
+    /**
+     * @brief Mark that a task of the given priority is no longer ready.
+     *
+     * @ingroup Scheduler
+     *
+     * @param[in] uxPriority Priority of the task that is no longer ready.
+     * @param[in] uxTopReadyPriority Bitmap of the ready tasks priorities.
+     */
+    #define portRESET_READY_PRIORITY( uxPriority, uxTopReadyPriority ) \
+        ( uxTopReadyPriority ) &= ~( 1UL << ( uxPriority ) )
+
+    /**
+     * @brief Determine the highest priority ready task's priority.
+     *
+     * @ingroup Scheduler
+     *
+     * @param[in] uxTopReadyPriority Bitmap of the ready tasks priorities.
+     * @param[in] uxTopPriority The highest priority ready task's priority.
+     */
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxTopReadyPriority ) \
+        ( uxTopPriority ) = ( 31UL - ulPortCountLeadingZeros( ( uxTopReadyPriority ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/* ------------------------------ Port Type Definitions ------------------------------ */
+
+#include "portmacro_asm.h"
+
+/**
+ * @brief Critical section nesting value.
+ *
+ * @ingroup Critical Sections
+ *
+ * @note A task exits critical section and enables IRQs when its nesting count
+ * reaches this value.
+ */
+#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0x0 )
+
+/**
+ * @brief Bit in Current Program Status Register (CPSR) to indicate that CPU is
+ * in Thumb State.
+ *
+ * @ingroup Task Context
+ */
+#define portTHUMB_MODE_BIT      ( ( StackType_t ) 0x20 )
+
+/**
+ * @brief Bitmask to check if an address is of Thumb Code.
+ *
+ * @ingroup Task Context
+ */
+#define portTHUMB_MODE_ADDRESS  ( 0x01UL )
+
+/**
+ * @brief Data type used to represent a stack word.
+ *
+ * @ingroup Port Interface Specifications
+ */
+typedef uint32_t StackType_t;
+
+/**
+ * @brief Signed data type equal to the data word operating size of the CPU.
+ *
+ * @ingroup Port Interface Specifications
+ */
+typedef int32_t BaseType_t;
+
+/**
+ * @brief Unsigned data type equal to the data word operating size of the CPU.
+ *
+ * @ingroup Port Interface Specifications
+ */
+typedef uint32_t UBaseType_t;
+
+/**
+ * @brief Data type used for the FreeRTOS Tick Counter.
+ *
+ * @note Using 32-bit tick type on a 32-bit architecture ensures that reads of
+ * the tick count do not need to be guarded with a critical section.
+ */
+typedef uint32_t TickType_t;
+
+/**
+ * @brief Marks the direction the stack grows on the targeted CPU.
+ *
+ * @ingroup Port Interface Specifications
+ */
+#define portSTACK_GROWTH   ( -1 )
+
+/**
+ * @brief Specifies stack pointer alignment requirements of the target CPU.
+ *
+ * @ingroup Port Interface Specifications
+ */
+#define portBYTE_ALIGNMENT 8U
+
+/**
+ * @brief Task function prototype macro as described on FreeRTOS.org.
+ *
+ * @ingroup Port Interface Specifications
+ *
+ * @note This is not required for this port but included in case common demo
+ * code uses it.
+ */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) \
+    void vFunction( void * pvParameters )
+
+/**
+ * @brief Task function prototype macro as described on FreeRTOS.org.
+ *
+ * @ingroup Port Interface Specifications
+ *
+ * @note This is not required for this port but included in case common demo
+ * code uses it.
+ */
+#define portTASK_FUNCTION( vFunction, pvParameters ) \
+    void vFunction( void * pvParameters )
+
+/**
+ * @brief The no-op ARM assembly instruction.
+ *
+ * @ingroup Port Interface Specifications
+ */
+#define portNOP()                                    __asm volatile( "NOP" )
+
+/**
+ * @brief The inline GCC label.
+ *
+ * @ingroup Port Interface Specifications
+ */
+#define portINLINE                                   __inline
+
+/**
+ * @brief The memory access synchronization barrier.
+ *
+ * @ingroup Port Interface Specifications
+ */
+#define portMEMORY_BARRIER()                         __asm volatile( "" ::: "memory" )
+
+/**
+ * @brief Defines if the tick count can be accessed atomically.
+ *
+ * @ingroup System Clock
+ */
+#define portTICK_TYPE_IS_ATOMIC                      1
+
+/**
+ * @brief The number of miliseconds between system ticks.
+ *
+ * @ingroup System Clock
+ */
+#define portTICK_PERIOD_MS                           ( ( TickType_t ) 1000UL / configTICK_RATE_HZ )
+
+/**
+ * @brief The largest possible delay value for any FreeRTOS API.
+ *
+ * @ingroup System Clock
+ */
+#define portMAX_DELAY                                ( TickType_t ) 0xFFFFFFFFUL
+
+/* ----------------------------- Port Assembly Functions ----------------------------- */
+
+/**
+ * @brief FreeRTOS Supervisor Call (SVC) Handler.
+ *
+ * @ingroup Scheduler
+ */
+void FreeRTOS_SVC_Handler( void );
+
+/**
+ * @brief FreeRTOS Interrupt Handler.
+ *
+ * @ingroup Scheduler
+ */
+void FreeRTOS_IRQ_Handler( void );
+
+/**
+ * @brief Yield the CPU.
+ *
+ * @ingroup Scheduler
+ */
+void vPortYield( void );
+
+#define portYIELD() vPortYield()
+
+/**
+ * @brief Enable interrupts.
+ *
+ * @ingroup Interrupt Management
+ */
+void vPortEnableInterrupts( void );
+
+#define portENABLE_INTERRUPTS() vPortEnableInterrupts()
+
+/**
+ * @brief Disable interrupts.
+ *
+ * @ingroup Interrupt Management
+ */
+void vPortDisableInterrupts( void );
+
+#define portDISABLE_INTERRUPTS() vPortDisableInterrupts()
+
+/**
+ * @brief Exit from a FreeRTO System Call.
+ *
+ * @ingroup Port Privilege
+ */
+void vPortSystemCallExit( void );
+
+/**
+ * @brief Start executing first task.
+ *
+ * @ingroup Scheduler
+ */
+void vPortStartFirstTask( void );
+
+/**
+ * @brief Enable the onboard MPU.
+ *
+ * @ingroup MPU Control
+ */
+void vMPUEnable( void );
+
+/**
+ * @brief Disable the onboard MPU.
+ *
+ * @ingroup MPU Control
+ */
+void vMPUDisable( void );
+
+/**
+ * @brief Enable the MPU Background Region.
+ *
+ * @ingroup MPU Control
+ */
+void vMPUEnableBackgroundRegion( void );
+
+/**
+ * @brief Disable the MPU Background Region.
+ *
+ * @ingroup MPU Control
+ */
+void vMPUDisableBackgroundRegion( void );
+
+/**
+ * @brief Set permissions for an MPU Region.
+ *
+ * @ingroup MPU Control
+ *
+ * @param[in] ulRegionNumber The MPU Region Number to set permissions for.
+ * @param[in] ulBaseAddress The base address of the MPU Region.
+ * @param[in] ulRegionSize The size of the MPU Region in bytes.
+ * @param[in] ulRegionPermissions The permissions associated with the MPU Region.
+ *
+ * @note This is an internal function and assumes that the inputs to this
+ * function are checked before calling this function.
+ */
+void vMPUSetRegion( uint32_t ulRegionNumber,
+                    uint32_t ulBaseAddress,
+                    uint32_t ulRegionSize,
+                    uint32_t ulRegionPermissions );
+
+/* ------------------------------- Port.c Declarations ------------------------------- */
+
+/**
+ * @brief Enter critical section.
+ *
+ * @ingroup Critical Section
+ */
+void vPortEnterCritical( void );
+
+#define portENTER_CRITICAL() vPortEnterCritical()
+
+/**
+ * @brief Exit critical section.
+ *
+ * @ingroup Critical Section
+ */
+void vPortExitCritical( void );
+
+#define portEXIT_CRITICAL() vPortExitCritical()
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @ingroup Port Privilege
+ *
+ * @note The processor privilege level is determined by checking the
+ * mode bits [4:0] of the Current Program Status Register (CPSR).
+ *
+ * @return pdTRUE, if the processer is privileged, pdFALSE otherwise.
+ */
+BaseType_t xPortIsPrivileged( void );
+
+#define portIS_PRIVILEGED() xPortIsPrivileged()
+
+/**
+ * @brief Checks whether or not a task is privileged.
+ *
+ * @ingroup Port Privilege
+ *
+ * @note A task's privilege level is associated with the task and is different from
+ * the processor's privilege level returned by xPortIsPrivileged. For example,
+ * the processor is privileged when an unprivileged task executes a system call.
+ *
+ * @return pdTRUE if the task is privileged, pdFALSE otherwise.
+ */
+BaseType_t xPortIsTaskPrivileged( void );
+
+#define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged()
+
+/**
+ * @brief Default return address for tasks.
+ *
+ * @ingroup Task Context
+ *
+ * @note This function is used as the default return address for tasks if
+ * configTASK_RETURN_ADDRESS is not defined in FreeRTOSConfig.h.
+ */
+void prvTaskExitError( void );
+
+#ifdef configTASK_RETURN_ADDRESS
+    #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
+#else
+    #define portTASK_RETURN_ADDRESS prvTaskExitError
+#endif /* configTASK_RETURN_ADDRESS */
+
+/**
+ * @brief Returns the number of leading zeros in a 32 bit variable.
+ *
+ * @param[in] ulBitmap 32-Bit number to count leading zeros in.
+ *
+ * @return The number of leading zeros in ulBitmap.
+ */
+UBaseType_t ulPortCountLeadingZeros( UBaseType_t ulBitmap );
+
+/**
+ * @brief End the FreeRTOS scheduler.
+ *
+ * Not implemented on this port.
+ *
+ * @ingroup Scheduler
+ */
+void vPortEndScheduler( void );
+
+/* --------------------------------- MPU Definitions --------------------------------- */
+
+/**
+ * @brief Mark that this port utilizes the onboard ARM MPU.
+ *
+ * @ingroup MPU Control
+ */
+#define portUSING_MPU_WRAPPERS     1
+
+/**
+ * @brief Used to mark if a task should be created as a privileged task.
+ *
+ * @ingroup Task Context
+ * @ingroup MPU Control
+ *
+ * @note A privileged task is created by performing a bitwise OR of this value and
+ * the task priority. For example, to create a privileged task at priority 2, the
+ * uxPriority parameter should be set to ( 2 | portPRIVILEGE_BIT ).
+ */
+#define portPRIVILEGE_BIT          ( 0x80000000UL )
+
+/**
+ * @brief Size of an Access Control List (ACL) entry in bits.
+ */
+#define portACL_ENTRY_SIZE_BITS    ( 32UL )
+
+/**
+ * @brief Structure to hold the MPU Register Values.
+ *
+ * @struct xMPU_REGION_REGISTERS
+ *
+ * @ingroup MPU Control
+ *
+ * @note The ordering of this struct MUST be in sync with the ordering in
+ * portRESTORE_CONTEXT.
+ */
+typedef struct MPU_REGION_REGISTERS
+{
+    uint32_t ulRegionSize;        /* Information for MPU Region Size and Enable Register. */
+    uint32_t ulRegionAttribute;   /* Information for MPU Region Access Control Register. */
+    uint32_t ulRegionBaseAddress; /* Information for MPU Region Base Address Register. */
+} xMPU_REGION_REGISTERS;
+
+/**
+ * @brief Structure to hold per-task System Call Stack information.
+ *
+ * @struct xSYSTEM_CALL_STACK_INFO
+ *
+ * @ingroup Port Privilege
+ *
+ * @note The ordering of this structure MUST be in sync with the assembly code
+ * of the port.
+ */
+typedef struct SYSTEM_CALL_STACK_INFO
+{
+    uint32_t * pulTaskStackPointer; /**< Stack Pointer of the task when it made a FreeRTOS System Call. */
+    uint32_t * pulLinkRegisterAtSystemCallEntry; /**< Link Register of the task when it made a FreeRTOS System Call. */
+    uint32_t * pulSystemCallStackPointer; /**< Stack Pointer to use for executing a FreeRTOS System Call. */
+    uint32_t * pulSystemCallExitAddress; /**< System call exit address. */
+    uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ]; /**< Buffer to be used as stack when performing a FreeRTOS System Call. */
+} xSYSTEM_CALL_STACK_INFO;
+
+/**
+ * @brief Per-Task MPU settings structure stored in the TCB.
+ * @struct xMPU_SETTINGS
+ *
+ * @ingroup MPU Control
+ * @ingroup Task Context
+ * @ingroup Port Privilege
+ *
+ * @note The ordering of this structure MUST be in sync with the assembly code
+ * of the port.
+ */
+typedef struct MPU_SETTINGS
+{
+    xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS_IN_TCB ];
+    uint32_t ulTaskFlags;
+    xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
+    uint32_t ulContext[ CONTEXT_SIZE ]; /**< Buffer used to store task context. */
+
+    #if( configENABLE_ACCESS_CONTROL_LIST == 1 )
+        uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE
+                                        / portACL_ENTRY_SIZE_BITS )
+                                      + 1UL ];
+    #endif
+} xMPU_SETTINGS;
+
+#ifdef __cplusplus
+} /* extern C */
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/portable/GCC/ARM_CRx_MPU/portmacro_asm.h b/portable/GCC/ARM_CRx_MPU/portmacro_asm.h
new file mode 100644
index 000000000..a113ac02d
--- /dev/null
+++ b/portable/GCC/ARM_CRx_MPU/portmacro_asm.h
@@ -0,0 +1,279 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTMACRO_ASM_H
+#define PORTMACRO_ASM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "FreeRTOSConfig.h"
+
+#ifndef configTOTAL_MPU_REGIONS
+    #error "Set configTOTAL_MPU_REGIONS to the humber of MPU regions in FreeRTOSConfig.h"
+#elif( configTOTAL_MPU_REGIONS == 12 )
+    #define portMPU_TOTAL_REGIONS ( 12UL )
+#elif( configTOTAL_MPU_REGIONS == 16 )
+    #define portMPU_TOTAL_REGIONS ( 16UL )
+#else
+    #error "Set configTOTAL_MPU_REGIONS to the number of MPU regions in FreeRTOSConfig.h"
+#endif /* configTOTAL_MPU_REGIONS */
+
+/*
+ * The application write can disable Floating Point Unit (FPU) support by
+ * setting configENABLE_FPU to 0. Floating point context stored in TCB
+ * comprises of 32 floating point registers (D0-D31) and FPSCR register.
+ * Disabling FPU, therefore, reduces the per-task RAM usage by
+ * ( 32 + 1 ) * 4 = 132 bytes per task.
+ *
+ * BE CAREFUL DISABLING THIS: Certain standard library APIs try to optimize
+ * themselves by using the floating point registers. If the FPU support is
+ * disabled, the use of such APIs may result in memory corruption.
+ */
+#ifndef configENABLE_FPU
+    #define configENABLE_FPU    1
+#endif /* configENABLE_FPU */
+
+#define portENABLE_FPU configENABLE_FPU
+
+/* On the ArmV7-R Architecture the Operating mode of the Processor is set
+ * using the Current Program Status Register (CPSR) Mode bits, [4:0]. The only
+ * unprivileged mode is User Mode.
+ *
+ * Additional information about the Processor Modes can be found here:
+ * https://developer.arm.com/documentation/ddi0406/cb/System-Level-Architecture/The-System-Level-Programmers--Model/ARM-processor-modes-and-ARM-core-registers/ARM-processor-modes?lang=en
+ *
+ */
+
+/**
+ * @brief CPSR bits for various processor modes.
+ *
+ * @ingroup Port Privilege
+ */
+#define USER_MODE   0x10U
+#define FIQ_MODE    0x11U
+#define IRQ_MODE    0x12U
+#define SVC_MODE    0x13U
+#define MON_MODE    0x16U
+#define ABT_MODE    0x17U
+#define HYP_MODE    0x1AU
+#define UND_MODE    0x1BU
+#define SYS_MODE    0x1FU
+
+/**
+ * @brief Flag used to mark that a FreeRTOS Task is privileged.
+ *
+ * @ingroup Port Privilege
+ */
+#define portTASK_IS_PRIVILEGED_FLAG   ( 1UL << 1UL )
+
+/**
+ * @brief SVC numbers for various scheduler operations.
+ *
+ * @ingroup Scheduler
+ *
+ * @note These value must not be used in mpu_syscall_numbers.h.
+ */
+#define portSVC_YIELD                 0x0100U
+#define portSVC_SYSTEM_CALL_EXIT      0x0104U
+
+/**
+ * @brief Macros required to manipulate MPU.
+ *
+ * Further information about MPU can be found in Arm's documentation
+ * https://developer.arm.com/documentation/ddi0363/g/System-Control/Register-descriptions/c6--MPU-memory-region-programming-registers
+ *
+ */
+
+/* MPU sub-region disable settings. This information is encoded in the MPU
+ * Region Size and Enable Register. */
+#define portMPU_SUBREGION_0_DISABLE   ( 0x1UL << 8UL )
+#define portMPU_SUBREGION_1_DISABLE   ( 0x1UL << 9UL )
+#define portMPU_SUBREGION_2_DISABLE   ( 0x1UL << 10UL )
+#define portMPU_SUBREGION_3_DISABLE   ( 0x1UL << 11UL )
+#define portMPU_SUBREGION_4_DISABLE   ( 0x1UL << 12UL )
+#define portMPU_SUBREGION_5_DISABLE   ( 0x1UL << 13UL )
+#define portMPU_SUBREGION_6_DISABLE   ( 0x1UL << 14UL )
+#define portMPU_SUBREGION_7_DISABLE   ( 0x1UL << 15UL )
+
+/* Default MPU regions. */
+#define portFIRST_CONFIGURABLE_REGION ( 0 )
+#define portLAST_CONFIGURABLE_REGION  ( portMPU_TOTAL_REGIONS - 5UL )
+#define portSTACK_REGION              ( portMPU_TOTAL_REGIONS - 4UL )
+#define portUNPRIVILEGED_FLASH_REGION ( portMPU_TOTAL_REGIONS - 3UL )
+#define portPRIVILEGED_FLASH_REGION   ( portMPU_TOTAL_REGIONS - 2UL )
+#define portPRIVILEGED_RAM_REGION     ( portMPU_TOTAL_REGIONS - 1UL )
+#define portNUM_CONFIGURABLE_REGIONS \
+    ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1UL )
+/* Plus one to make space for the stack region. */
+#define portTOTAL_NUM_REGIONS_IN_TCB        ( portNUM_CONFIGURABLE_REGIONS + 1UL )
+
+/* MPU region sizes. This information is encoded in the MPU Region Size and
+ * Enable Register. */
+#define portMPU_REGION_SIZE_32B             ( 0x04UL << 1UL )
+#define portMPU_REGION_SIZE_64B             ( 0x05UL << 1UL )
+#define portMPU_REGION_SIZE_128B            ( 0x06UL << 1UL )
+#define portMPU_REGION_SIZE_256B            ( 0x07UL << 1UL )
+#define portMPU_REGION_SIZE_512B            ( 0x08UL << 1UL )
+#define portMPU_REGION_SIZE_1KB             ( 0x09UL << 1UL )
+#define portMPU_REGION_SIZE_2KB             ( 0x0AUL << 1UL )
+#define portMPU_REGION_SIZE_4KB             ( 0x0BUL << 1UL )
+#define portMPU_REGION_SIZE_8KB             ( 0x0CUL << 1UL )
+#define portMPU_REGION_SIZE_16KB            ( 0x0DUL << 1UL )
+#define portMPU_REGION_SIZE_32KB            ( 0x0EUL << 1UL )
+#define portMPU_REGION_SIZE_64KB            ( 0x0FUL << 1UL )
+#define portMPU_REGION_SIZE_128KB           ( 0x10UL << 1UL )
+#define portMPU_REGION_SIZE_256KB           ( 0x11UL << 1UL )
+#define portMPU_REGION_SIZE_512KB           ( 0x12UL << 1UL )
+#define portMPU_REGION_SIZE_1MB             ( 0x13UL << 1UL )
+#define portMPU_REGION_SIZE_2MB             ( 0x14UL << 1UL )
+#define portMPU_REGION_SIZE_4MB             ( 0x15UL << 1UL )
+#define portMPU_REGION_SIZE_8MB             ( 0x16UL << 1UL )
+#define portMPU_REGION_SIZE_16MB            ( 0x17UL << 1UL )
+#define portMPU_REGION_SIZE_32MB            ( 0x18UL << 1UL )
+#define portMPU_REGION_SIZE_64MB            ( 0x19UL << 1UL )
+#define portMPU_REGION_SIZE_128MB           ( 0x1AUL << 1UL )
+#define portMPU_REGION_SIZE_256MB           ( 0x1BUL << 1UL )
+#define portMPU_REGION_SIZE_512MB           ( 0x1CUL << 1UL )
+#define portMPU_REGION_SIZE_1GB             ( 0x1DUL << 1UL )
+#define portMPU_REGION_SIZE_2GB             ( 0x1EUL << 1UL )
+#define portMPU_REGION_SIZE_4GB             ( 0x1FUL << 1UL )
+
+/* MPU memory types. This information is encoded in the TEX, S, C and B bits
+ * of the MPU Region Access Control Register. */
+#define portMPU_REGION_STRONGLY_ORDERED_SHAREABLE  ( 0x00UL ) /* TEX=000, S=NA, C=0, B=0. */
+#define portMPU_REGION_DEVICE_SHAREABLE            ( 0x01UL ) /* TEX=000, S=NA, C=0, B=1. */
+#define portMPU_REGION_NORMAL_OIWTNOWA_NONSHARED   ( 0x02UL ) /* TEX=000, S=0, C=1, B=0. */
+#define portMPU_REGION_NORMAL_OIWTNOWA_SHARED      ( 0x06UL ) /* TEX=000, S=1, C=1, B=0. */
+#define portMPU_REGION_NORMAL_OIWBNOWA_NONSHARED   ( 0x03UL ) /* TEX=000, S=0, C=1, B=1. */
+#define portMPU_REGION_NORMAL_OIWBNOWA_SHARED      ( 0x07UL ) /* TEX=000, S=1, C=1, B=1. */
+#define portMPU_REGION_NORMAL_OINC_NONSHARED       ( 0x08UL ) /* TEX=001, S=0, C=0, B=0. */
+#define portMPU_REGION_NORMAL_OINC_SHARED          ( 0x0CUL ) /* TEX=001, S=1, C=0, B=0. */
+#define portMPU_REGION_NORMAL_OIWBWA_NONSHARED     ( 0x0BUL ) /* TEX=001, S=0, C=1, B=1. */
+#define portMPU_REGION_NORMAL_OIWBWA_SHARED        ( 0x0FUL ) /* TEX=001, S=1, C=1, B=1. */
+#define portMPU_REGION_DEVICE_NONSHAREABLE         ( 0x10UL ) /* TEX=010, S=NA, C=0, B=0. */
+
+/* MPU access permissions. This information is encoded in the XN and AP bits of
+ * the MPU Region Access Control Register. */
+#define portMPU_REGION_AP_BITMASK                  ( 0x07UL << 8UL )
+#define portMPU_REGION_XN_BITMASK                  ( 0x01UL << 12UL )
+
+#define portMPU_REGION_PRIV_NA_USER_NA             ( 0x00UL << 8UL )
+#define portMPU_REGION_PRIV_NA_USER_NA_EXEC        ( portMPU_REGION_PRIV_NA_USER_NA ) /* Priv: X, Unpriv: X. */
+#define portMPU_REGION_PRIV_NA_USER_NA_NOEXEC      ( portMPU_REGION_PRIV_NA_USER_NA | \
+                                                     portMPU_REGION_XN_BITMASK ) /* Priv: No Access, Unpriv: No Access. */
+
+#define portMPU_REGION_PRIV_RW_USER_NA             ( 0x01UL << 8UL )
+#define portMPU_REGION_PRIV_RW_USER_NA_EXEC        ( portMPU_REGION_PRIV_RW_USER_NA ) /* Priv: RWX, Unpriv: X. */
+#define portMPU_REGION_PRIV_RW_USER_NA_NOEXEC      ( portMPU_REGION_PRIV_RW_USER_NA | \
+                                                     portMPU_REGION_XN_BITMASK ) /* Priv: RW, Unpriv: No access. */
+
+#define portMPU_REGION_PRIV_RW_USER_RO             ( 0x02UL << 8UL )
+#define portMPU_REGION_PRIV_RW_USER_RO_EXEC        ( portMPU_REGION_PRIV_RW_USER_RO ) /* Priv: RWX, Unpriv: RX. */
+#define portMPU_REGION_PRIV_RW_USER_RO_NOEXEC      ( portMPU_REGION_PRIV_RW_USER_RO | \
+                                                     portMPU_REGION_XN_BITMASK ) /* Priv: RW, Unpriv: R. */
+
+#define portMPU_REGION_PRIV_RW_USER_RW             ( 0x03UL << 8UL )
+#define portMPU_REGION_PRIV_RW_USER_RW_EXEC        ( portMPU_REGION_PRIV_RW_USER_RW ) /* Priv: RWX, Unpriv: RWX. */
+#define portMPU_REGION_PRIV_RW_USER_RW_NOEXEC      ( portMPU_REGION_PRIV_RW_USER_RW | \
+                                                     portMPU_REGION_XN_BITMASK ) /* Priv: RW, Unpriv: RW. */
+
+#define portMPU_REGION_PRIV_RO_USER_NA             ( 0x05UL << 8UL )
+#define portMPU_REGION_PRIV_RO_USER_NA_EXEC        ( portMPU_REGION_PRIV_RO_USER_NA ) /* Priv: RX, Unpriv: X. */
+#define portMPU_REGION_PRIV_RO_USER_NA_NOEXEC      ( portMPU_REGION_PRIV_RO_USER_NA | \
+                                                     portMPU_REGION_XN_BITMASK ) /* Priv: R, Unpriv: No access. */
+
+#define portMPU_REGION_PRIV_RO_USER_RO             ( 0x06UL << 8UL )
+#define portMPU_REGION_PRIV_RO_USER_RO_EXEC        ( portMPU_REGION_PRIV_RO_USER_RO ) /* Priv: RX, Unpriv: RX. */
+#define portMPU_REGION_PRIV_RO_USER_RO_NOEXEC      ( portMPU_REGION_PRIV_RO_USER_RO | \
+                                                     portMPU_REGION_XN_BITMASK ) /* Priv: R, Unpriv: R. */
+
+/* MPU region management. */
+#define portMPU_REGION_EXECUTE_NEVER               ( 0x01UL << 12UL )
+#define portMPU_REGION_ENABLE                      ( 0x01UL )
+
+/**
+ * @brief The size (in words) of a task context.
+ *
+ * An array of this size is allocated in TCB where a task's context is saved
+ * when it is switched out.
+ *
+ * Information about Floating Point Unit (FPU):
+ * https://developer.arm.com/documentation/den0042/a/Floating-Point
+ *
+ * Additional information related to the Cortex R4-F's FPU Implementation:
+ * https://developer.arm.com/documentation/ddi0363/e/fpu-programmer-s-model
+ *
+ * Additional information related to the Cortex R5-F's FPU Implementation:
+ * https://developer.arm.com/documentation/ddi0460/d/FPU-Programmers-Model
+ *
+ * Additional information related to the ArmV7-R CPSR:
+ * https://developer.arm.com/documentation/ddi0406/cb/Application-Level-Architecture/Application-Level-Programmers--Model/The-Application-Program-Status-Register--APSR-?lang=en
+ *
+ * Additional information related to the GPRs:
+ * https://developer.arm.com/documentation/ddi0406/cb/System-Level-Architecture/The-System-Level-Programmers--Model/ARM-processor-modes-and-ARM-core-registers/ARM-core-registers?lang=en
+ *
+ */
+
+#if( portENABLE_FPU == 1 )
+    /*
+     * +-------------------+-------+----------+--------+----------+----------+----------+------+
+     * | ulCriticalNesting | FPSCR |  S0-S31  | R0-R12 | SP (R13) | LR (R14) | PC (R15) | CPSR |
+     * +-------------------+-------+----------+--------+----------+----------+----------+------+
+     *
+     * <------------------><------><---------><--------><---------><--------><----------><----->
+     *           1            1        32         13         1         1          1        1
+     */
+    #define CONTEXT_SIZE 51U
+#else
+    /*
+     * +-------------------+--------+----------+----------+----------+------+
+     * | ulCriticalNesting | R0-R12 | SP (R13) | LR (R14) | PC (R15) | CPSR |
+     * +-------------------+--------+----------+----------+----------+------+
+     *
+     * <------------------><--------><---------><--------><----------><----->
+     *           1             13         1         1          1        1
+     */
+    #define CONTEXT_SIZE 18U
+#endif /* CONTEXT_SIZE */
+
+/**
+ * @brief Offset of xSystemCallStackInfo from the start of a TCB.
+ */
+#define portSYSTEM_CALL_INFO_OFFSET             \
+    ( ( 1U /* pxTopOfStack. */ +                \
+        ( portTOTAL_NUM_REGIONS_IN_TCB * 3U ) + \
+        1U /* ulTaskFlags. */                   \
+      ) * 4U )
+
+#ifdef __cplusplus
+} /* extern C */
+#endif
+
+#endif /* PORTMACRO_ASM_H */

From 83b5b2495045d4ad43ea0510f946b70d298d3d70 Mon Sep 17 00:00:00 2001
From: Asmeili <51125377+Asmeili@users.noreply.github.com>
Date: Wed, 28 Feb 2024 12:21:29 +0100
Subject: [PATCH 231/424] Fix typo in croutine.c (#1004)

---
 croutine.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/croutine.c b/croutine.c
index 86256bcd1..84e1b99bd 100644
--- a/croutine.c
+++ b/croutine.c
@@ -30,7 +30,7 @@
 #include "task.h"
 #include "croutine.h"
 
-/* Remove the whole file is co-routines are not being used. */
+/* Remove the whole file if co-routines are not being used. */
 #if ( configUSE_CO_ROUTINES != 0 )
 
 /*

From cff947acd05cc4f6e8c7838701bdc58f8cdf282d Mon Sep 17 00:00:00 2001
From: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Date: Mon, 4 Mar 2024 10:48:05 +0530
Subject: [PATCH 232/424] Update comment in template FreeRTOSConfig.h (#1007)

Update the comment for configKERNEL_INTERRUPT_PRIORITY in the template
FreeRTOSConfig.h.

It was reported here - https://forums.freertos.org/t/migration-from-v10-5-1-to-v11-0-1-fails-with-new-freertosconfig-h-file/19276/

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 examples/template_configuration/FreeRTOSConfig.h | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/examples/template_configuration/FreeRTOSConfig.h b/examples/template_configuration/FreeRTOSConfig.h
index d7203f2e6..74b7cea96 100644
--- a/examples/template_configuration/FreeRTOSConfig.h
+++ b/examples/template_configuration/FreeRTOSConfig.h
@@ -283,10 +283,9 @@
 /******************************************************************************/
 
 /* configKERNEL_INTERRUPT_PRIORITY sets the priority of the tick and context
- * switch performing interrupts.  The default value is set to the highest interrupt
- * priority (0).  Not supported by all FreeRTOS ports.  See
- * https://www.freertos.org/RTOS-Cortex-M3-M4.html for information specific to ARM
- * Cortex-M devices. */
+ * switch performing interrupts.  Not supported by all FreeRTOS ports.  See
+ * https://www.freertos.org/RTOS-Cortex-M3-M4.html for information specific to
+ * ARM Cortex-M devices. */
 #define configKERNEL_INTERRUPT_PRIORITY          0
 
 /* configMAX_SYSCALL_INTERRUPT_PRIORITY sets the interrupt priority above which

From 30f6061f48e2d54625d31e72ada6f5c474fba99f Mon Sep 17 00:00:00 2001
From: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Date: Wed, 6 Mar 2024 15:34:21 +0800
Subject: [PATCH 233/424] Not using pxIndex to iterate ready list in trace
 utility (#1000)

* pxIndex should only be used when selecting next task. Altering pxIndex
  of a ready list will cause the scheduler to be unable to select the
  right task to run. Using a for loop if traversing the list for trace
  utility is required.
* Not defining listGET_OWNER_OF_NEXT_ENTRY when using SMP scheduler

---------

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
---
 include/list.h |  10 ++-
 tasks.c        | 190 +++++++++++++++----------------------------------
 2 files changed, 65 insertions(+), 135 deletions(-)

diff --git a/include/list.h b/include/list.h
index a9aace44e..091553dd1 100644
--- a/include/list.h
+++ b/include/list.h
@@ -282,7 +282,8 @@ typedef struct xLIST
  * \page listGET_OWNER_OF_NEXT_ENTRY listGET_OWNER_OF_NEXT_ENTRY
  * \ingroup LinkedList
  */
-#define listGET_OWNER_OF_NEXT_ENTRY( pxTCB, pxList )                                           \
+#if ( configNUMBER_OF_CORES == 1 )
+    #define listGET_OWNER_OF_NEXT_ENTRY( pxTCB, pxList )                                       \
     do {                                                                                       \
         List_t * const pxConstList = ( pxList );                                               \
         /* Increment the index to the next item and return the item, ensuring */               \
@@ -294,6 +295,13 @@ typedef struct xLIST
         }                                                                                      \
         ( pxTCB ) = ( pxConstList )->pxIndex->pvOwner;                                         \
     } while( 0 )
+#else /* #if ( configNUMBER_OF_CORES == 1 ) */
+
+/* This function is not required in SMP. FreeRTOS SMP scheduler doesn't use
+ * pxIndex and it should always point to the xListEnd. Not defining this macro
+ * here to prevent updating pxIndex.
+ */
+#endif /* #if ( configNUMBER_OF_CORES == 1 ) */
 
 /*
  * Version of uxListRemove() that does not return a value.  Provided as a slight
diff --git a/tasks.c b/tasks.c
index 767dff7b0..e0db3f9e7 100644
--- a/tasks.c
+++ b/tasks.c
@@ -4177,147 +4177,72 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery )
 /*-----------------------------------------------------------*/
 
 #if ( INCLUDE_xTaskGetHandle == 1 )
+    static TCB_t * prvSearchForNameWithinSingleList( List_t * pxList,
+                                                     const char pcNameToQuery[] )
+    {
+        TCB_t * pxReturn = NULL;
+        UBaseType_t x;
+        char cNextChar;
+        BaseType_t xBreakLoop;
+        const ListItem_t * pxEndMarker = listGET_END_MARKER( pxList );
+        ListItem_t * pxIterator;
 
-    #if ( configNUMBER_OF_CORES == 1 )
-        static TCB_t * prvSearchForNameWithinSingleList( List_t * pxList,
-                                                         const char pcNameToQuery[] )
+        /* This function is called with the scheduler suspended. */
+
+        if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )
         {
-            TCB_t * pxNextTCB;
-            TCB_t * pxFirstTCB;
-            TCB_t * pxReturn = NULL;
-            UBaseType_t x;
-            char cNextChar;
-            BaseType_t xBreakLoop;
-
-            /* This function is called with the scheduler suspended. */
-
-            if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )
+            for( pxIterator = listGET_HEAD_ENTRY( pxList ); pxIterator != pxEndMarker; pxIterator = listGET_NEXT( pxIterator ) )
             {
                 /* MISRA Ref 11.5.3 [Void pointer assignment] */
                 /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
                 /* coverity[misra_c_2012_rule_11_5_violation] */
-                listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList );
+                TCB_t * pxTCB = listGET_LIST_ITEM_OWNER( pxIterator );
 
-                do
+                /* Check each character in the name looking for a match or
+                 * mismatch. */
+                xBreakLoop = pdFALSE;
+
+                for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
                 {
-                    /* MISRA Ref 11.5.3 [Void pointer assignment] */
-                    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
-                    /* coverity[misra_c_2012_rule_11_5_violation] */
-                    listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList );
+                    cNextChar = pxTCB->pcTaskName[ x ];
 
-                    /* Check each character in the name looking for a match or
-                     * mismatch. */
-                    xBreakLoop = pdFALSE;
-
-                    for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
+                    if( cNextChar != pcNameToQuery[ x ] )
                     {
-                        cNextChar = pxNextTCB->pcTaskName[ x ];
-
-                        if( cNextChar != pcNameToQuery[ x ] )
-                        {
-                            /* Characters didn't match. */
-                            xBreakLoop = pdTRUE;
-                        }
-                        else if( cNextChar == ( char ) 0x00 )
-                        {
-                            /* Both strings terminated, a match must have been
-                             * found. */
-                            pxReturn = pxNextTCB;
-                            xBreakLoop = pdTRUE;
-                        }
-                        else
-                        {
-                            mtCOVERAGE_TEST_MARKER();
-                        }
-
-                        if( xBreakLoop != pdFALSE )
-                        {
-                            break;
-                        }
+                        /* Characters didn't match. */
+                        xBreakLoop = pdTRUE;
+                    }
+                    else if( cNextChar == ( char ) 0x00 )
+                    {
+                        /* Both strings terminated, a match must have been
+                         * found. */
+                        pxReturn = pxTCB;
+                        xBreakLoop = pdTRUE;
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
                     }
 
-                    if( pxReturn != NULL )
+                    if( xBreakLoop != pdFALSE )
                     {
-                        /* The handle has been found. */
-                        break;
-                    }
-                } while( pxNextTCB != pxFirstTCB );
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
-
-            return pxReturn;
-        }
-    #else /* if ( configNUMBER_OF_CORES == 1 ) */
-        static TCB_t * prvSearchForNameWithinSingleList( List_t * pxList,
-                                                         const char pcNameToQuery[] )
-        {
-            TCB_t * pxReturn = NULL;
-            UBaseType_t x;
-            char cNextChar;
-            BaseType_t xBreakLoop;
-            const ListItem_t * pxEndMarker = listGET_END_MARKER( pxList );
-            ListItem_t * pxIterator;
-
-            /* This function is called with the scheduler suspended. */
-
-            if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )
-            {
-                for( pxIterator = listGET_HEAD_ENTRY( pxList ); pxIterator != pxEndMarker; pxIterator = listGET_NEXT( pxIterator ) )
-                {
-                    /* MISRA Ref 11.5.3 [Void pointer assignment] */
-                    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
-                    /* coverity[misra_c_2012_rule_11_5_violation] */
-                    TCB_t * pxTCB = listGET_LIST_ITEM_OWNER( pxIterator );
-
-                    /* Check each character in the name looking for a match or
-                     * mismatch. */
-                    xBreakLoop = pdFALSE;
-
-                    for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
-                    {
-                        cNextChar = pxTCB->pcTaskName[ x ];
-
-                        if( cNextChar != pcNameToQuery[ x ] )
-                        {
-                            /* Characters didn't match. */
-                            xBreakLoop = pdTRUE;
-                        }
-                        else if( cNextChar == ( char ) 0x00 )
-                        {
-                            /* Both strings terminated, a match must have been
-                             * found. */
-                            pxReturn = pxTCB;
-                            xBreakLoop = pdTRUE;
-                        }
-                        else
-                        {
-                            mtCOVERAGE_TEST_MARKER();
-                        }
-
-                        if( xBreakLoop != pdFALSE )
-                        {
-                            break;
-                        }
-                    }
-
-                    if( pxReturn != NULL )
-                    {
-                        /* The handle has been found. */
                         break;
                     }
                 }
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
 
-            return pxReturn;
+                if( pxReturn != NULL )
+                {
+                    /* The handle has been found. */
+                    break;
+                }
+            }
         }
-    #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        return pxReturn;
+    }
 
 #endif /* INCLUDE_xTaskGetHandle */
 /*-----------------------------------------------------------*/
@@ -6330,30 +6255,27 @@ static void prvCheckTasksWaitingTermination( void )
                                                      List_t * pxList,
                                                      eTaskState eState )
     {
-        configLIST_VOLATILE TCB_t * pxNextTCB;
-        configLIST_VOLATILE TCB_t * pxFirstTCB;
+        configLIST_VOLATILE TCB_t * pxTCB;
         UBaseType_t uxTask = 0;
+        const ListItem_t * pxEndMarker = listGET_END_MARKER( pxList );
+        ListItem_t * pxIterator;
 
         if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )
         {
-            /* MISRA Ref 11.5.3 [Void pointer assignment] */
-            /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
-            /* coverity[misra_c_2012_rule_11_5_violation] */
-            listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList );
-
             /* Populate an TaskStatus_t structure within the
              * pxTaskStatusArray array for each task that is referenced from
              * pxList.  See the definition of TaskStatus_t in task.h for the
              * meaning of each TaskStatus_t structure member. */
-            do
+            for( pxIterator = listGET_HEAD_ENTRY( pxList ); pxIterator != pxEndMarker; pxIterator = listGET_NEXT( pxIterator ) )
             {
                 /* MISRA Ref 11.5.3 [Void pointer assignment] */
                 /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
                 /* coverity[misra_c_2012_rule_11_5_violation] */
-                listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList );
-                vTaskGetInfo( ( TaskHandle_t ) pxNextTCB, &( pxTaskStatusArray[ uxTask ] ), pdTRUE, eState );
+                pxTCB = listGET_LIST_ITEM_OWNER( pxIterator );
+
+                vTaskGetInfo( ( TaskHandle_t ) pxTCB, &( pxTaskStatusArray[ uxTask ] ), pdTRUE, eState );
                 uxTask++;
-            } while( pxNextTCB != pxFirstTCB );
+            }
         }
         else
         {

From d95451d92443895b9bc3d3169de9551eec859afe Mon Sep 17 00:00:00 2001
From: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Date: Wed, 6 Mar 2024 16:24:19 +0800
Subject: [PATCH 234/424] Define portNOP in RP2040 port (#1003)

---
 portable/ThirdParty/GCC/RP2040/include/portmacro.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/portable/ThirdParty/GCC/RP2040/include/portmacro.h b/portable/ThirdParty/GCC/RP2040/include/portmacro.h
index 1fe5e412f..bf91eda36 100644
--- a/portable/ThirdParty/GCC/RP2040/include/portmacro.h
+++ b/portable/ThirdParty/GCC/RP2040/include/portmacro.h
@@ -278,7 +278,7 @@ static inline void vPortRecursiveLock( uint32_t ulLockNum,
 #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
 #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
-#define portNOP()
+#define portNOP()               __asm volatile ( "nop" )
 
 #define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
 

From 4732b96dba05e2eeaeaec795977ab0a054cce065 Mon Sep 17 00:00:00 2001
From: RichardBarry <3073890+RichardBarry@users.noreply.github.com>
Date: Wed, 6 Mar 2024 23:08:15 -0800
Subject: [PATCH 235/424] Add daemon task startup hook / timer task creation
 consistency check (#1009)

Add a compile time check that emits a helpful error message if the user
attempts to create a daemon task startup hook without also creating the
timer/daemon task.

The timer/daemon task startup hook runs in the context of the timer/daemon
task.  Therefore, it won't run even if configUSE_DAEMON_TASK_STARTUP_HOOK
is set to 1 if the timer task isn't created.  The timer task is only created if
configUSE_TIMERS is not equal to 0.
---
 include/FreeRTOS.h | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/include/FreeRTOS.h b/include/FreeRTOS.h
index ecf82dc5a..8dcb407f4 100644
--- a/include/FreeRTOS.h
+++ b/include/FreeRTOS.h
@@ -298,10 +298,6 @@
     #endif
 #endif
 
-#ifndef configUSE_DAEMON_TASK_STARTUP_HOOK
-    #define configUSE_DAEMON_TASK_STARTUP_HOOK    0
-#endif
-
 #ifndef configUSE_APPLICATION_TASK_TAG
     #define configUSE_APPLICATION_TASK_TAG    0
 #endif
@@ -322,6 +318,16 @@
     #define configUSE_TIMERS    0
 #endif
 
+#ifndef configUSE_DAEMON_TASK_STARTUP_HOOK
+    #define configUSE_DAEMON_TASK_STARTUP_HOOK    0
+#endif
+
+#if ( configUSE_DAEMON_TASK_STARTUP_HOOK != 0 )
+    #if ( configUSE_TIMERS == 0 )
+        #error configUSE_DAEMON_TASK_STARTUP_HOOK is set, but the daemon task is not created because configUSE_TIMERS is 0.
+    #endif
+#endif
+
 #ifndef configUSE_COUNTING_SEMAPHORES
     #define configUSE_COUNTING_SEMAPHORES    0
 #endif

From 6dcce924907bc86a4732be67a2f9e33567d7f563 Mon Sep 17 00:00:00 2001
From: wat <78684666+watsk@users.noreply.github.com>
Date: Mon, 18 Mar 2024 15:09:49 +0900
Subject: [PATCH 236/424] Improvement for 64bit Windows port (#1011)

* 64bit TickType_t is supported on Windows port.(MSVC and MinGW)
Especially it is introduced for 64bit compiler.(x64 platform on MSVC and MinGW-w64)

* Unnecessary compiler warning for the cast operation is disabled locally.(MinGW-w64 only)

* Modify the condition for ignoring compiler warning for the cast operation.

Before modification: Compiler warning was ignored only on MinGW64
After modification: Compiler warning is ignored on MinGW32 and MinGW64
Reason of modification: The cast warning here is unavoidable not only on MinGW64 but also on MinGW32.
"__GNUC__" macro is used because MSVC does not recognize this #pragma directive.
---
 portable/MSVC-MingW/port.c      | 11 +++++++++++
 portable/MSVC-MingW/portmacro.h | 11 ++++++++++-
 2 files changed, 21 insertions(+), 1 deletion(-)

diff --git a/portable/MSVC-MingW/port.c b/portable/MSVC-MingW/port.c
index b0c26bdac..d489746f5 100644
--- a/portable/MSVC-MingW/port.c
+++ b/portable/MSVC-MingW/port.c
@@ -246,8 +246,19 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
                                                FALSE,  /* Start not signalled. */
                                                NULL ); /* No name. */
 
+
+#ifdef __GNUC__
+    /* GCC reports the warning for the cast operation from TaskFunction_t to LPTHREAD_START_ROUTINE. */
+    /* Disable this warning here by the #pragma option. */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wcast-function-type"
+#endif
     /* Create the thread itself. */
     pxThreadState->pvThread = CreateThread( NULL, xStackSize, ( LPTHREAD_START_ROUTINE ) pxCode, pvParameters, CREATE_SUSPENDED | STACK_SIZE_PARAM_IS_A_RESERVATION, NULL );
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
     configASSERT( pxThreadState->pvThread ); /* See comment where TerminateThread() is called. */
     SetThreadAffinityMask( pxThreadState->pvThread, 0x01 );
     SetThreadPriorityBoost( pxThreadState->pvThread, TRUE );
diff --git a/portable/MSVC-MingW/portmacro.h b/portable/MSVC-MingW/portmacro.h
index a10ac6586..c2b07fa19 100644
--- a/portable/MSVC-MingW/portmacro.h
+++ b/portable/MSVC-MingW/portmacro.h
@@ -72,9 +72,18 @@ typedef portSTACK_TYPE           StackType_t;
     typedef uint32_t             TickType_t;
     #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-/* 32/64-bit tick type on a 32/64-bit architecture, so reads of the tick
+/* 32-bit tick type on a 32/64-bit architecture, so reads of the tick
  * count do not need to be guarded with a critical section. */
     #define portTICK_TYPE_IS_ATOMIC    1
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_64_BITS )
+    typedef uint64_t             TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffffffffffffffffULL
+
+#if defined( __x86_64__ ) || defined( _M_X64 )
+/* 64-bit tick type on a 64-bit architecture, so reads of the tick
+ * count do not need to be guarded with a critical section. */
+    #define portTICK_TYPE_IS_ATOMIC    1
+#endif
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif

From 625b24a104dd901d86759668b6b272590d154308 Mon Sep 17 00:00:00 2001
From: Soren Ptak <ptaksoren@gmail.com>
Date: Mon, 18 Mar 2024 03:51:21 -0700
Subject: [PATCH 237/424] Remove duplicate pop from MPU Wrappers ASM Files
 (#1008)

* Remove duplicate pop instruction from portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/mpu_wrappers_v2_asm.c

* Remove duplicate pop instruction from portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/mpu_wrappers_v2_asm.c

* Remove duplicate pop instruction from portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/mpu_wrappers_v2_asm.c

* Remove duplicate pop instruction from portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/mpu_wrappers_v2_asm.c

* Remove duplicate pop instruction from portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/mpu_wrappers_v2_asm.S

* Remove duplicate pop instruction from portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/mpu_wrappers_v2_asm.S

* Remove duplicate pop instruction from portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/mpu_wrappers_v2_asm.S

* Remove duplicate pop instruction from portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/mpu_wrappers_v2_asm.S

* Run the copy_files.py script to update the ARMv8M ports to remove the duplicate pop instruction in mpu_wrappers_v2_asm

* Remove duplicate pop instruction from portable/GCC/ARM_CM3_MPU/mpu_wrappers_v2_asm.c

* Remove duplicate pop instruction from portable/GCC/ARM_CM4_MPU/mpu_wrappers_v2_asm.c

* Remove duplicate pop instruction from portable/IAR/ARM_CM4F_MPU/mpu_wrappers_v2_asm.S

* Remove duplicate pop instruction from portable/RVDS/ARM_CM4_MPU/mpu_wrappers_v2_asm.c

---------

Co-authored-by: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
---
 .../GCC/ARM_CM23/mpu_wrappers_v2_asm.c        | 236 ++++++------------
 .../GCC/ARM_CM23_NTZ/mpu_wrappers_v2_asm.c    | 236 ++++++------------
 .../GCC/ARM_CM33/mpu_wrappers_v2_asm.c        | 234 ++++++-----------
 .../GCC/ARM_CM33_NTZ/mpu_wrappers_v2_asm.c    | 234 ++++++-----------
 .../IAR/ARM_CM23/mpu_wrappers_v2_asm.S        | 210 ++++++----------
 .../IAR/ARM_CM23_NTZ/mpu_wrappers_v2_asm.S    | 210 ++++++----------
 .../IAR/ARM_CM33/mpu_wrappers_v2_asm.S        | 210 ++++++----------
 .../IAR/ARM_CM33_NTZ/mpu_wrappers_v2_asm.S    | 210 ++++++----------
 .../ARM_CM23/non_secure/mpu_wrappers_v2_asm.c | 236 ++++++------------
 .../non_secure/mpu_wrappers_v2_asm.c          | 236 ++++++------------
 .../ARM_CM33/non_secure/mpu_wrappers_v2_asm.c | 234 ++++++-----------
 .../non_secure/mpu_wrappers_v2_asm.c          | 234 ++++++-----------
 .../non_secure/mpu_wrappers_v2_asm.c          | 234 ++++++-----------
 .../non_secure/mpu_wrappers_v2_asm.c          | 234 ++++++-----------
 .../GCC/ARM_CM3_MPU/mpu_wrappers_v2_asm.c     | 234 ++++++-----------
 .../GCC/ARM_CM4_MPU/mpu_wrappers_v2_asm.c     | 234 ++++++-----------
 .../ARM_CM55/non_secure/mpu_wrappers_v2_asm.c | 234 ++++++-----------
 .../non_secure/mpu_wrappers_v2_asm.c          | 234 ++++++-----------
 .../ARM_CM85/non_secure/mpu_wrappers_v2_asm.c | 234 ++++++-----------
 .../non_secure/mpu_wrappers_v2_asm.c          | 234 ++++++-----------
 .../ARM_CM23/non_secure/mpu_wrappers_v2_asm.S | 210 ++++++----------
 .../non_secure/mpu_wrappers_v2_asm.S          | 210 ++++++----------
 .../ARM_CM33/non_secure/mpu_wrappers_v2_asm.S | 210 ++++++----------
 .../non_secure/mpu_wrappers_v2_asm.S          | 210 ++++++----------
 .../non_secure/mpu_wrappers_v2_asm.S          | 210 ++++++----------
 .../non_secure/mpu_wrappers_v2_asm.S          | 210 ++++++----------
 .../IAR/ARM_CM4F_MPU/mpu_wrappers_v2_asm.S    | 210 ++++++----------
 .../ARM_CM55/non_secure/mpu_wrappers_v2_asm.S | 210 ++++++----------
 .../non_secure/mpu_wrappers_v2_asm.S          | 210 ++++++----------
 .../ARM_CM85/non_secure/mpu_wrappers_v2_asm.S | 210 ++++++----------
 .../non_secure/mpu_wrappers_v2_asm.S          | 210 ++++++----------
 .../RVDS/ARM_CM4_MPU/mpu_wrappers_v2_asm.c    | 210 ++++++----------
 32 files changed, 2436 insertions(+), 4676 deletions(-)

diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/mpu_wrappers_v2_asm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/mpu_wrappers_v2_asm.c
index 9c829b540..fb167a699 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/mpu_wrappers_v2_asm.c
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/mpu_wrappers_v2_asm.c
@@ -63,12 +63,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xTaskDelayUntil_Unpriv                        \n"
                 " MPU_xTaskDelayUntil_Priv:                             \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xTaskDelayUntilImpl                         \n"
                 " MPU_xTaskDelayUntil_Unpriv:                           \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory"
@@ -93,12 +92,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xTaskAbortDelay_Unpriv                        \n"
                 " MPU_xTaskAbortDelay_Priv:                             \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xTaskAbortDelayImpl                         \n"
                 " MPU_xTaskAbortDelay_Unpriv:                           \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory"
@@ -123,12 +121,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_vTaskDelay_Unpriv                             \n"
                 " MPU_vTaskDelay_Priv:                                  \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_vTaskDelayImpl                              \n"
                 " MPU_vTaskDelay_Unpriv:                                \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory"
@@ -153,12 +150,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_uxTaskPriorityGet_Unpriv                      \n"
                 " MPU_uxTaskPriorityGet_Priv:                           \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_uxTaskPriorityGetImpl                       \n"
                 " MPU_uxTaskPriorityGet_Unpriv:                         \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory"
@@ -183,12 +179,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_eTaskGetState_Unpriv                          \n"
                 " MPU_eTaskGetState_Priv:                               \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_eTaskGetStateImpl                           \n"
                 " MPU_eTaskGetState_Unpriv:                             \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory"
@@ -219,12 +214,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_vTaskGetInfo_Unpriv                           \n"
                 " MPU_vTaskGetInfo_Priv:                                \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_vTaskGetInfoImpl                            \n"
                 " MPU_vTaskGetInfo_Unpriv:                              \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory"
@@ -249,12 +243,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xTaskGetIdleTaskHandle_Unpriv                 \n"
                 " MPU_xTaskGetIdleTaskHandle_Priv:                      \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xTaskGetIdleTaskHandleImpl                  \n"
                 " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory"
@@ -279,12 +272,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_vTaskSuspend_Unpriv                           \n"
                 " MPU_vTaskSuspend_Priv:                                \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_vTaskSuspendImpl                            \n"
                 " MPU_vTaskSuspend_Unpriv:                              \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory"
@@ -309,12 +301,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_vTaskResume_Unpriv                            \n"
                 " MPU_vTaskResume_Priv:                                 \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_vTaskResumeImpl                             \n"
                 " MPU_vTaskResume_Unpriv:                               \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskResume ) : "memory"
@@ -337,12 +328,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xTaskGetTickCount_Unpriv                      \n"
             " MPU_xTaskGetTickCount_Priv:                           \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xTaskGetTickCountImpl                       \n"
             " MPU_xTaskGetTickCount_Unpriv:                         \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory"
@@ -363,12 +353,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_uxTaskGetNumberOfTasks_Unpriv                 \n"
             " MPU_uxTaskGetNumberOfTasks_Priv:                      \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_uxTaskGetNumberOfTasksImpl                  \n"
             " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory"
@@ -391,12 +380,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_ulTaskGetRunTimeCounter_Unpriv                \n"
                 " MPU_ulTaskGetRunTimeCounter_Priv:                     \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_ulTaskGetRunTimeCounterImpl                 \n"
                 " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory"
@@ -421,12 +409,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_ulTaskGetRunTimePercent_Unpriv                \n"
                 " MPU_ulTaskGetRunTimePercent_Priv:                     \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_ulTaskGetRunTimePercentImpl                 \n"
                 " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory"
@@ -451,12 +438,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv            \n"
                 " MPU_ulTaskGetIdleRunTimePercent_Priv:                 \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_ulTaskGetIdleRunTimePercentImpl             \n"
                 " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory"
@@ -481,12 +467,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv            \n"
                 " MPU_ulTaskGetIdleRunTimeCounter_Priv:                 \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_ulTaskGetIdleRunTimeCounterImpl             \n"
                 " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory"
@@ -513,12 +498,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_vTaskSetApplicationTaskTag_Unpriv             \n"
                 " MPU_vTaskSetApplicationTaskTag_Priv:                  \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_vTaskSetApplicationTaskTagImpl              \n"
                 " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory"
@@ -543,12 +527,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xTaskGetApplicationTaskTag_Unpriv             \n"
                 " MPU_xTaskGetApplicationTaskTag_Priv:                  \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xTaskGetApplicationTaskTagImpl              \n"
                 " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory"
@@ -577,12 +560,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv      \n"
                 " MPU_vTaskSetThreadLocalStoragePointer_Priv:           \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_vTaskSetThreadLocalStoragePointerImpl       \n"
                 " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory"
@@ -609,12 +591,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv     \n"
                 " MPU_pvTaskGetThreadLocalStoragePointer_Priv:          \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_pvTaskGetThreadLocalStoragePointerImpl      \n"
                 " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory"
@@ -643,12 +624,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_uxTaskGetSystemState_Unpriv                   \n"
                 " MPU_uxTaskGetSystemState_Priv:                        \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_uxTaskGetSystemStateImpl                    \n"
                 " MPU_uxTaskGetSystemState_Unpriv:                      \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory"
@@ -673,12 +653,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_uxTaskGetStackHighWaterMark_Unpriv            \n"
                 " MPU_uxTaskGetStackHighWaterMark_Priv:                 \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_uxTaskGetStackHighWaterMarkImpl             \n"
                 " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory"
@@ -703,12 +682,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv           \n"
                 " MPU_uxTaskGetStackHighWaterMark2_Priv:                \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_uxTaskGetStackHighWaterMark2Impl            \n"
                 " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory"
@@ -733,12 +711,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xTaskGetCurrentTaskHandle_Unpriv              \n"
                 " MPU_xTaskGetCurrentTaskHandle_Priv:                   \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xTaskGetCurrentTaskHandleImpl               \n"
                 " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory"
@@ -763,12 +740,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xTaskGetSchedulerState_Unpriv                 \n"
                 " MPU_xTaskGetSchedulerState_Priv:                      \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xTaskGetSchedulerStateImpl                  \n"
                 " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory"
@@ -791,12 +767,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_vTaskSetTimeOutState_Unpriv                   \n"
             " MPU_vTaskSetTimeOutState_Priv:                        \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_vTaskSetTimeOutStateImpl                    \n"
             " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory"
@@ -819,12 +794,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xTaskCheckForTimeOut_Unpriv                   \n"
             " MPU_xTaskCheckForTimeOut_Priv:                        \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xTaskCheckForTimeOutImpl                    \n"
             " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory"
@@ -847,12 +821,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xTaskGenericNotify_Unpriv                     \n"
                 " MPU_xTaskGenericNotify_Priv:                          \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xTaskGenericNotifyImpl                      \n"
                 " MPU_xTaskGenericNotify_Unpriv:                        \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory"
@@ -877,12 +850,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xTaskGenericNotifyWait_Unpriv                 \n"
                 " MPU_xTaskGenericNotifyWait_Priv:                      \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xTaskGenericNotifyWaitImpl                  \n"
                 " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory"
@@ -911,12 +883,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_ulTaskGenericNotifyTake_Unpriv                \n"
                 " MPU_ulTaskGenericNotifyTake_Priv:                     \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_ulTaskGenericNotifyTakeImpl                 \n"
                 " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory"
@@ -943,12 +914,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xTaskGenericNotifyStateClear_Unpriv           \n"
                 " MPU_xTaskGenericNotifyStateClear_Priv:                \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xTaskGenericNotifyStateClearImpl            \n"
                 " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory"
@@ -977,12 +947,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_ulTaskGenericNotifyValueClear_Unpriv          \n"
                 " MPU_ulTaskGenericNotifyValueClear_Priv:               \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_ulTaskGenericNotifyValueClearImpl           \n"
                 " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory"
@@ -1011,12 +980,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xQueueGenericSend_Unpriv                      \n"
             " MPU_xQueueGenericSend_Priv:                           \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xQueueGenericSendImpl                       \n"
             " MPU_xQueueGenericSend_Unpriv:                         \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory"
@@ -1037,12 +1005,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_uxQueueMessagesWaiting_Unpriv                 \n"
             " MPU_uxQueueMessagesWaiting_Priv:                      \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_uxQueueMessagesWaitingImpl                  \n"
             " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory"
@@ -1063,12 +1030,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_uxQueueSpacesAvailable_Unpriv                 \n"
             " MPU_uxQueueSpacesAvailable_Priv:                      \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_uxQueueSpacesAvailableImpl                  \n"
             " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory"
@@ -1093,12 +1059,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xQueueReceive_Unpriv                          \n"
             " MPU_xQueueReceive_Priv:                               \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xQueueReceiveImpl                           \n"
             " MPU_xQueueReceive_Unpriv:                             \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory"
@@ -1123,12 +1088,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xQueuePeek_Unpriv                             \n"
             " MPU_xQueuePeek_Priv:                                  \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xQueuePeekImpl                              \n"
             " MPU_xQueuePeek_Unpriv:                                \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory"
@@ -1151,12 +1115,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xQueueSemaphoreTake_Unpriv                    \n"
             " MPU_xQueueSemaphoreTake_Priv:                         \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xQueueSemaphoreTakeImpl                     \n"
             " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory"
@@ -1179,12 +1142,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xQueueGetMutexHolder_Unpriv                   \n"
                 " MPU_xQueueGetMutexHolder_Priv:                        \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xQueueGetMutexHolderImpl                    \n"
                 " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory"
@@ -1211,12 +1173,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xQueueTakeMutexRecursive_Unpriv               \n"
                 " MPU_xQueueTakeMutexRecursive_Priv:                    \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xQueueTakeMutexRecursiveImpl                \n"
                 " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory"
@@ -1241,12 +1202,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xQueueGiveMutexRecursive_Unpriv               \n"
                 " MPU_xQueueGiveMutexRecursive_Priv:                    \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xQueueGiveMutexRecursiveImpl                \n"
                 " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory"
@@ -1273,12 +1233,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xQueueSelectFromSet_Unpriv                    \n"
                 " MPU_xQueueSelectFromSet_Priv:                         \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xQueueSelectFromSetImpl                     \n"
                 " MPU_xQueueSelectFromSet_Unpriv:                       \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory"
@@ -1305,12 +1264,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xQueueAddToSet_Unpriv                         \n"
                 " MPU_xQueueAddToSet_Priv:                              \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xQueueAddToSetImpl                          \n"
                 " MPU_xQueueAddToSet_Unpriv:                            \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory"
@@ -1337,12 +1295,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_vQueueAddToRegistry_Unpriv                    \n"
                 " MPU_vQueueAddToRegistry_Priv:                         \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_vQueueAddToRegistryImpl                     \n"
                 " MPU_vQueueAddToRegistry_Unpriv:                       \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory"
@@ -1367,12 +1324,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_vQueueUnregisterQueue_Unpriv                  \n"
                 " MPU_vQueueUnregisterQueue_Priv:                       \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_vQueueUnregisterQueueImpl                   \n"
                 " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory"
@@ -1397,12 +1353,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_pcQueueGetName_Unpriv                         \n"
                 " MPU_pcQueueGetName_Priv:                              \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_pcQueueGetNameImpl                          \n"
                 " MPU_pcQueueGetName_Unpriv:                            \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory"
@@ -1427,12 +1382,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_pvTimerGetTimerID_Unpriv                      \n"
                 " MPU_pvTimerGetTimerID_Priv:                           \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_pvTimerGetTimerIDImpl                       \n"
                 " MPU_pvTimerGetTimerID_Unpriv:                         \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory"
@@ -1459,12 +1413,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_vTimerSetTimerID_Unpriv                       \n"
                 " MPU_vTimerSetTimerID_Priv:                            \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_vTimerSetTimerIDImpl                        \n"
                 " MPU_vTimerSetTimerID_Unpriv:                          \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory"
@@ -1489,12 +1442,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xTimerIsTimerActive_Unpriv                    \n"
                 " MPU_xTimerIsTimerActive_Priv:                         \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xTimerIsTimerActiveImpl                     \n"
                 " MPU_xTimerIsTimerActive_Unpriv:                       \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory"
@@ -1519,12 +1471,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv         \n"
                 " MPU_xTimerGetTimerDaemonTaskHandle_Priv:              \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xTimerGetTimerDaemonTaskHandleImpl          \n"
                 " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory"
@@ -1542,21 +1493,20 @@
         {
             __asm volatile
             (
-                " .syntax unified                                               \n"
-                " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
-                "                                                               \n"
-                " push {r0, r1}                                                 \n"
-                " mrs r0, control                                               \n"
-                " movs r1, #1                                                   \n"
-                " tst r0, r1                                                    \n"
-                " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
-                " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
-                "     pop {r0, r1}                                              \n"
-                "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
-                " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
-                "     pop {r0, r1}                                              \n"
-                "     svc %0                                                    \n"
-                "                                                               \n"
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGenericCommandFromTaskImpl          \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xTimerGenericCommandFromTask_Unpriv           \n"
+                " MPU_xTimerGenericCommandFromTask_Priv:                \n"
+                "     b MPU_xTimerGenericCommandFromTaskImpl            \n"
+                " MPU_xTimerGenericCommandFromTask_Unpriv:              \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory"
             );
         }
@@ -1579,12 +1529,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_pcTimerGetName_Unpriv                         \n"
                 " MPU_pcTimerGetName_Priv:                              \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_pcTimerGetNameImpl                          \n"
                 " MPU_pcTimerGetName_Unpriv:                            \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory"
@@ -1611,12 +1560,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_vTimerSetReloadMode_Unpriv                    \n"
                 " MPU_vTimerSetReloadMode_Priv:                         \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_vTimerSetReloadModeImpl                     \n"
                 " MPU_vTimerSetReloadMode_Unpriv:                       \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory"
@@ -1641,12 +1589,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xTimerGetReloadMode_Unpriv                    \n"
                 " MPU_xTimerGetReloadMode_Priv:                         \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xTimerGetReloadModeImpl                     \n"
                 " MPU_xTimerGetReloadMode_Unpriv:                       \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory"
@@ -1671,12 +1618,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_uxTimerGetReloadMode_Unpriv                   \n"
                 " MPU_uxTimerGetReloadMode_Priv:                        \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_uxTimerGetReloadModeImpl                    \n"
                 " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory"
@@ -1701,12 +1647,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xTimerGetPeriod_Unpriv                        \n"
                 " MPU_xTimerGetPeriod_Priv:                             \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xTimerGetPeriodImpl                         \n"
                 " MPU_xTimerGetPeriod_Unpriv:                           \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory"
@@ -1731,12 +1676,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xTimerGetExpiryTime_Unpriv                    \n"
                 " MPU_xTimerGetExpiryTime_Priv:                         \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xTimerGetExpiryTimeImpl                     \n"
                 " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory"
@@ -1759,12 +1703,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
             " MPU_xEventGroupWaitBits_Priv:                         \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xEventGroupWaitBitsImpl                     \n"
             " MPU_xEventGroupWaitBits_Unpriv:                       \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
@@ -1787,12 +1730,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xEventGroupClearBits_Unpriv                   \n"
             " MPU_xEventGroupClearBits_Priv:                        \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xEventGroupClearBitsImpl                    \n"
             " MPU_xEventGroupClearBits_Unpriv:                      \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
@@ -1815,12 +1757,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xEventGroupSetBits_Unpriv                     \n"
             " MPU_xEventGroupSetBits_Priv:                          \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xEventGroupSetBitsImpl                      \n"
             " MPU_xEventGroupSetBits_Unpriv:                        \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
@@ -1847,12 +1788,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xEventGroupSync_Unpriv                        \n"
             " MPU_xEventGroupSync_Priv:                             \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xEventGroupSyncImpl                         \n"
             " MPU_xEventGroupSync_Unpriv:                           \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
@@ -1875,12 +1815,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_uxEventGroupGetNumber_Unpriv                  \n"
                 " MPU_uxEventGroupGetNumber_Priv:                       \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_uxEventGroupGetNumberImpl                   \n"
                 " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory"
@@ -1907,12 +1846,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_vEventGroupSetNumber_Unpriv                   \n"
                 " MPU_vEventGroupSetNumber_Priv:                        \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_vEventGroupSetNumberImpl                    \n"
                 " MPU_vEventGroupSetNumber_Unpriv:                      \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory"
@@ -1941,12 +1879,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xStreamBufferSend_Unpriv                      \n"
             " MPU_xStreamBufferSend_Priv:                           \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xStreamBufferSendImpl                       \n"
             " MPU_xStreamBufferSend_Unpriv:                         \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
@@ -1973,12 +1910,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xStreamBufferReceive_Unpriv                   \n"
             " MPU_xStreamBufferReceive_Priv:                        \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xStreamBufferReceiveImpl                    \n"
             " MPU_xStreamBufferReceive_Unpriv:                      \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
@@ -1999,12 +1935,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
             " MPU_xStreamBufferIsFull_Priv:                         \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xStreamBufferIsFullImpl                     \n"
             " MPU_xStreamBufferIsFull_Unpriv:                       \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
@@ -2025,12 +1960,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
             " MPU_xStreamBufferIsEmpty_Priv:                        \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xStreamBufferIsEmptyImpl                    \n"
             " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
@@ -2051,12 +1985,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
             " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
             " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
@@ -2077,12 +2010,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
             " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xStreamBufferBytesAvailableImpl             \n"
             " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
@@ -2105,12 +2037,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
             " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
             " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
@@ -2131,12 +2062,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
             " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
             " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/mpu_wrappers_v2_asm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/mpu_wrappers_v2_asm.c
index 9c829b540..fb167a699 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/mpu_wrappers_v2_asm.c
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/mpu_wrappers_v2_asm.c
@@ -63,12 +63,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xTaskDelayUntil_Unpriv                        \n"
                 " MPU_xTaskDelayUntil_Priv:                             \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xTaskDelayUntilImpl                         \n"
                 " MPU_xTaskDelayUntil_Unpriv:                           \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory"
@@ -93,12 +92,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xTaskAbortDelay_Unpriv                        \n"
                 " MPU_xTaskAbortDelay_Priv:                             \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xTaskAbortDelayImpl                         \n"
                 " MPU_xTaskAbortDelay_Unpriv:                           \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory"
@@ -123,12 +121,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_vTaskDelay_Unpriv                             \n"
                 " MPU_vTaskDelay_Priv:                                  \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_vTaskDelayImpl                              \n"
                 " MPU_vTaskDelay_Unpriv:                                \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory"
@@ -153,12 +150,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_uxTaskPriorityGet_Unpriv                      \n"
                 " MPU_uxTaskPriorityGet_Priv:                           \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_uxTaskPriorityGetImpl                       \n"
                 " MPU_uxTaskPriorityGet_Unpriv:                         \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory"
@@ -183,12 +179,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_eTaskGetState_Unpriv                          \n"
                 " MPU_eTaskGetState_Priv:                               \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_eTaskGetStateImpl                           \n"
                 " MPU_eTaskGetState_Unpriv:                             \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory"
@@ -219,12 +214,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_vTaskGetInfo_Unpriv                           \n"
                 " MPU_vTaskGetInfo_Priv:                                \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_vTaskGetInfoImpl                            \n"
                 " MPU_vTaskGetInfo_Unpriv:                              \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory"
@@ -249,12 +243,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xTaskGetIdleTaskHandle_Unpriv                 \n"
                 " MPU_xTaskGetIdleTaskHandle_Priv:                      \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xTaskGetIdleTaskHandleImpl                  \n"
                 " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory"
@@ -279,12 +272,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_vTaskSuspend_Unpriv                           \n"
                 " MPU_vTaskSuspend_Priv:                                \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_vTaskSuspendImpl                            \n"
                 " MPU_vTaskSuspend_Unpriv:                              \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory"
@@ -309,12 +301,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_vTaskResume_Unpriv                            \n"
                 " MPU_vTaskResume_Priv:                                 \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_vTaskResumeImpl                             \n"
                 " MPU_vTaskResume_Unpriv:                               \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskResume ) : "memory"
@@ -337,12 +328,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xTaskGetTickCount_Unpriv                      \n"
             " MPU_xTaskGetTickCount_Priv:                           \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xTaskGetTickCountImpl                       \n"
             " MPU_xTaskGetTickCount_Unpriv:                         \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory"
@@ -363,12 +353,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_uxTaskGetNumberOfTasks_Unpriv                 \n"
             " MPU_uxTaskGetNumberOfTasks_Priv:                      \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_uxTaskGetNumberOfTasksImpl                  \n"
             " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory"
@@ -391,12 +380,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_ulTaskGetRunTimeCounter_Unpriv                \n"
                 " MPU_ulTaskGetRunTimeCounter_Priv:                     \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_ulTaskGetRunTimeCounterImpl                 \n"
                 " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory"
@@ -421,12 +409,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_ulTaskGetRunTimePercent_Unpriv                \n"
                 " MPU_ulTaskGetRunTimePercent_Priv:                     \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_ulTaskGetRunTimePercentImpl                 \n"
                 " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory"
@@ -451,12 +438,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv            \n"
                 " MPU_ulTaskGetIdleRunTimePercent_Priv:                 \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_ulTaskGetIdleRunTimePercentImpl             \n"
                 " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory"
@@ -481,12 +467,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv            \n"
                 " MPU_ulTaskGetIdleRunTimeCounter_Priv:                 \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_ulTaskGetIdleRunTimeCounterImpl             \n"
                 " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory"
@@ -513,12 +498,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_vTaskSetApplicationTaskTag_Unpriv             \n"
                 " MPU_vTaskSetApplicationTaskTag_Priv:                  \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_vTaskSetApplicationTaskTagImpl              \n"
                 " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory"
@@ -543,12 +527,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xTaskGetApplicationTaskTag_Unpriv             \n"
                 " MPU_xTaskGetApplicationTaskTag_Priv:                  \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xTaskGetApplicationTaskTagImpl              \n"
                 " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory"
@@ -577,12 +560,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv      \n"
                 " MPU_vTaskSetThreadLocalStoragePointer_Priv:           \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_vTaskSetThreadLocalStoragePointerImpl       \n"
                 " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory"
@@ -609,12 +591,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv     \n"
                 " MPU_pvTaskGetThreadLocalStoragePointer_Priv:          \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_pvTaskGetThreadLocalStoragePointerImpl      \n"
                 " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory"
@@ -643,12 +624,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_uxTaskGetSystemState_Unpriv                   \n"
                 " MPU_uxTaskGetSystemState_Priv:                        \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_uxTaskGetSystemStateImpl                    \n"
                 " MPU_uxTaskGetSystemState_Unpriv:                      \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory"
@@ -673,12 +653,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_uxTaskGetStackHighWaterMark_Unpriv            \n"
                 " MPU_uxTaskGetStackHighWaterMark_Priv:                 \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_uxTaskGetStackHighWaterMarkImpl             \n"
                 " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory"
@@ -703,12 +682,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv           \n"
                 " MPU_uxTaskGetStackHighWaterMark2_Priv:                \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_uxTaskGetStackHighWaterMark2Impl            \n"
                 " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory"
@@ -733,12 +711,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xTaskGetCurrentTaskHandle_Unpriv              \n"
                 " MPU_xTaskGetCurrentTaskHandle_Priv:                   \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xTaskGetCurrentTaskHandleImpl               \n"
                 " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory"
@@ -763,12 +740,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xTaskGetSchedulerState_Unpriv                 \n"
                 " MPU_xTaskGetSchedulerState_Priv:                      \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xTaskGetSchedulerStateImpl                  \n"
                 " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory"
@@ -791,12 +767,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_vTaskSetTimeOutState_Unpriv                   \n"
             " MPU_vTaskSetTimeOutState_Priv:                        \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_vTaskSetTimeOutStateImpl                    \n"
             " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory"
@@ -819,12 +794,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xTaskCheckForTimeOut_Unpriv                   \n"
             " MPU_xTaskCheckForTimeOut_Priv:                        \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xTaskCheckForTimeOutImpl                    \n"
             " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory"
@@ -847,12 +821,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xTaskGenericNotify_Unpriv                     \n"
                 " MPU_xTaskGenericNotify_Priv:                          \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xTaskGenericNotifyImpl                      \n"
                 " MPU_xTaskGenericNotify_Unpriv:                        \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory"
@@ -877,12 +850,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xTaskGenericNotifyWait_Unpriv                 \n"
                 " MPU_xTaskGenericNotifyWait_Priv:                      \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xTaskGenericNotifyWaitImpl                  \n"
                 " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory"
@@ -911,12 +883,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_ulTaskGenericNotifyTake_Unpriv                \n"
                 " MPU_ulTaskGenericNotifyTake_Priv:                     \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_ulTaskGenericNotifyTakeImpl                 \n"
                 " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory"
@@ -943,12 +914,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xTaskGenericNotifyStateClear_Unpriv           \n"
                 " MPU_xTaskGenericNotifyStateClear_Priv:                \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xTaskGenericNotifyStateClearImpl            \n"
                 " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory"
@@ -977,12 +947,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_ulTaskGenericNotifyValueClear_Unpriv          \n"
                 " MPU_ulTaskGenericNotifyValueClear_Priv:               \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_ulTaskGenericNotifyValueClearImpl           \n"
                 " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory"
@@ -1011,12 +980,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xQueueGenericSend_Unpriv                      \n"
             " MPU_xQueueGenericSend_Priv:                           \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xQueueGenericSendImpl                       \n"
             " MPU_xQueueGenericSend_Unpriv:                         \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory"
@@ -1037,12 +1005,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_uxQueueMessagesWaiting_Unpriv                 \n"
             " MPU_uxQueueMessagesWaiting_Priv:                      \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_uxQueueMessagesWaitingImpl                  \n"
             " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory"
@@ -1063,12 +1030,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_uxQueueSpacesAvailable_Unpriv                 \n"
             " MPU_uxQueueSpacesAvailable_Priv:                      \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_uxQueueSpacesAvailableImpl                  \n"
             " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory"
@@ -1093,12 +1059,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xQueueReceive_Unpriv                          \n"
             " MPU_xQueueReceive_Priv:                               \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xQueueReceiveImpl                           \n"
             " MPU_xQueueReceive_Unpriv:                             \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory"
@@ -1123,12 +1088,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xQueuePeek_Unpriv                             \n"
             " MPU_xQueuePeek_Priv:                                  \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xQueuePeekImpl                              \n"
             " MPU_xQueuePeek_Unpriv:                                \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory"
@@ -1151,12 +1115,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xQueueSemaphoreTake_Unpriv                    \n"
             " MPU_xQueueSemaphoreTake_Priv:                         \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xQueueSemaphoreTakeImpl                     \n"
             " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory"
@@ -1179,12 +1142,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xQueueGetMutexHolder_Unpriv                   \n"
                 " MPU_xQueueGetMutexHolder_Priv:                        \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xQueueGetMutexHolderImpl                    \n"
                 " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory"
@@ -1211,12 +1173,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xQueueTakeMutexRecursive_Unpriv               \n"
                 " MPU_xQueueTakeMutexRecursive_Priv:                    \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xQueueTakeMutexRecursiveImpl                \n"
                 " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory"
@@ -1241,12 +1202,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xQueueGiveMutexRecursive_Unpriv               \n"
                 " MPU_xQueueGiveMutexRecursive_Priv:                    \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xQueueGiveMutexRecursiveImpl                \n"
                 " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory"
@@ -1273,12 +1233,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xQueueSelectFromSet_Unpriv                    \n"
                 " MPU_xQueueSelectFromSet_Priv:                         \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xQueueSelectFromSetImpl                     \n"
                 " MPU_xQueueSelectFromSet_Unpriv:                       \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory"
@@ -1305,12 +1264,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xQueueAddToSet_Unpriv                         \n"
                 " MPU_xQueueAddToSet_Priv:                              \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xQueueAddToSetImpl                          \n"
                 " MPU_xQueueAddToSet_Unpriv:                            \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory"
@@ -1337,12 +1295,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_vQueueAddToRegistry_Unpriv                    \n"
                 " MPU_vQueueAddToRegistry_Priv:                         \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_vQueueAddToRegistryImpl                     \n"
                 " MPU_vQueueAddToRegistry_Unpriv:                       \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory"
@@ -1367,12 +1324,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_vQueueUnregisterQueue_Unpriv                  \n"
                 " MPU_vQueueUnregisterQueue_Priv:                       \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_vQueueUnregisterQueueImpl                   \n"
                 " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory"
@@ -1397,12 +1353,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_pcQueueGetName_Unpriv                         \n"
                 " MPU_pcQueueGetName_Priv:                              \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_pcQueueGetNameImpl                          \n"
                 " MPU_pcQueueGetName_Unpriv:                            \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory"
@@ -1427,12 +1382,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_pvTimerGetTimerID_Unpriv                      \n"
                 " MPU_pvTimerGetTimerID_Priv:                           \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_pvTimerGetTimerIDImpl                       \n"
                 " MPU_pvTimerGetTimerID_Unpriv:                         \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory"
@@ -1459,12 +1413,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_vTimerSetTimerID_Unpriv                       \n"
                 " MPU_vTimerSetTimerID_Priv:                            \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_vTimerSetTimerIDImpl                        \n"
                 " MPU_vTimerSetTimerID_Unpriv:                          \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory"
@@ -1489,12 +1442,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xTimerIsTimerActive_Unpriv                    \n"
                 " MPU_xTimerIsTimerActive_Priv:                         \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xTimerIsTimerActiveImpl                     \n"
                 " MPU_xTimerIsTimerActive_Unpriv:                       \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory"
@@ -1519,12 +1471,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv         \n"
                 " MPU_xTimerGetTimerDaemonTaskHandle_Priv:              \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xTimerGetTimerDaemonTaskHandleImpl          \n"
                 " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory"
@@ -1542,21 +1493,20 @@
         {
             __asm volatile
             (
-                " .syntax unified                                               \n"
-                " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
-                "                                                               \n"
-                " push {r0, r1}                                                 \n"
-                " mrs r0, control                                               \n"
-                " movs r1, #1                                                   \n"
-                " tst r0, r1                                                    \n"
-                " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
-                " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
-                "     pop {r0, r1}                                              \n"
-                "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
-                " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
-                "     pop {r0, r1}                                              \n"
-                "     svc %0                                                    \n"
-                "                                                               \n"
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGenericCommandFromTaskImpl          \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xTimerGenericCommandFromTask_Unpriv           \n"
+                " MPU_xTimerGenericCommandFromTask_Priv:                \n"
+                "     b MPU_xTimerGenericCommandFromTaskImpl            \n"
+                " MPU_xTimerGenericCommandFromTask_Unpriv:              \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory"
             );
         }
@@ -1579,12 +1529,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_pcTimerGetName_Unpriv                         \n"
                 " MPU_pcTimerGetName_Priv:                              \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_pcTimerGetNameImpl                          \n"
                 " MPU_pcTimerGetName_Unpriv:                            \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory"
@@ -1611,12 +1560,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_vTimerSetReloadMode_Unpriv                    \n"
                 " MPU_vTimerSetReloadMode_Priv:                         \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_vTimerSetReloadModeImpl                     \n"
                 " MPU_vTimerSetReloadMode_Unpriv:                       \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory"
@@ -1641,12 +1589,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xTimerGetReloadMode_Unpriv                    \n"
                 " MPU_xTimerGetReloadMode_Priv:                         \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xTimerGetReloadModeImpl                     \n"
                 " MPU_xTimerGetReloadMode_Unpriv:                       \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory"
@@ -1671,12 +1618,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_uxTimerGetReloadMode_Unpriv                   \n"
                 " MPU_uxTimerGetReloadMode_Priv:                        \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_uxTimerGetReloadModeImpl                    \n"
                 " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory"
@@ -1701,12 +1647,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xTimerGetPeriod_Unpriv                        \n"
                 " MPU_xTimerGetPeriod_Priv:                             \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xTimerGetPeriodImpl                         \n"
                 " MPU_xTimerGetPeriod_Unpriv:                           \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory"
@@ -1731,12 +1676,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xTimerGetExpiryTime_Unpriv                    \n"
                 " MPU_xTimerGetExpiryTime_Priv:                         \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xTimerGetExpiryTimeImpl                     \n"
                 " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory"
@@ -1759,12 +1703,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
             " MPU_xEventGroupWaitBits_Priv:                         \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xEventGroupWaitBitsImpl                     \n"
             " MPU_xEventGroupWaitBits_Unpriv:                       \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
@@ -1787,12 +1730,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xEventGroupClearBits_Unpriv                   \n"
             " MPU_xEventGroupClearBits_Priv:                        \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xEventGroupClearBitsImpl                    \n"
             " MPU_xEventGroupClearBits_Unpriv:                      \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
@@ -1815,12 +1757,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xEventGroupSetBits_Unpriv                     \n"
             " MPU_xEventGroupSetBits_Priv:                          \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xEventGroupSetBitsImpl                      \n"
             " MPU_xEventGroupSetBits_Unpriv:                        \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
@@ -1847,12 +1788,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xEventGroupSync_Unpriv                        \n"
             " MPU_xEventGroupSync_Priv:                             \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xEventGroupSyncImpl                         \n"
             " MPU_xEventGroupSync_Unpriv:                           \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
@@ -1875,12 +1815,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_uxEventGroupGetNumber_Unpriv                  \n"
                 " MPU_uxEventGroupGetNumber_Priv:                       \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_uxEventGroupGetNumberImpl                   \n"
                 " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory"
@@ -1907,12 +1846,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_vEventGroupSetNumber_Unpriv                   \n"
                 " MPU_vEventGroupSetNumber_Priv:                        \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_vEventGroupSetNumberImpl                    \n"
                 " MPU_vEventGroupSetNumber_Unpriv:                      \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory"
@@ -1941,12 +1879,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xStreamBufferSend_Unpriv                      \n"
             " MPU_xStreamBufferSend_Priv:                           \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xStreamBufferSendImpl                       \n"
             " MPU_xStreamBufferSend_Unpriv:                         \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
@@ -1973,12 +1910,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xStreamBufferReceive_Unpriv                   \n"
             " MPU_xStreamBufferReceive_Priv:                        \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xStreamBufferReceiveImpl                    \n"
             " MPU_xStreamBufferReceive_Unpriv:                      \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
@@ -1999,12 +1935,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
             " MPU_xStreamBufferIsFull_Priv:                         \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xStreamBufferIsFullImpl                     \n"
             " MPU_xStreamBufferIsFull_Unpriv:                       \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
@@ -2025,12 +1960,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
             " MPU_xStreamBufferIsEmpty_Priv:                        \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xStreamBufferIsEmptyImpl                    \n"
             " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
@@ -2051,12 +1985,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
             " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
             " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
@@ -2077,12 +2010,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
             " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xStreamBufferBytesAvailableImpl             \n"
             " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
@@ -2105,12 +2037,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
             " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
             " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
@@ -2131,12 +2062,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
             " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
             " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/mpu_wrappers_v2_asm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/mpu_wrappers_v2_asm.c
index 170d10fcc..4f66448f9 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/mpu_wrappers_v2_asm.c
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/mpu_wrappers_v2_asm.c
@@ -62,12 +62,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskDelayUntil_Unpriv                        \n"
                 " MPU_xTaskDelayUntil_Priv:                             \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskDelayUntilImpl                         \n"
                 " MPU_xTaskDelayUntil_Unpriv:                           \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory"
@@ -91,12 +90,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskAbortDelay_Unpriv                        \n"
                 " MPU_xTaskAbortDelay_Priv:                             \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskAbortDelayImpl                         \n"
                 " MPU_xTaskAbortDelay_Unpriv:                           \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory"
@@ -120,12 +118,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskDelay_Unpriv                             \n"
                 " MPU_vTaskDelay_Priv:                                  \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskDelayImpl                              \n"
                 " MPU_vTaskDelay_Unpriv:                                \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory"
@@ -149,12 +146,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxTaskPriorityGet_Unpriv                      \n"
                 " MPU_uxTaskPriorityGet_Priv:                           \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxTaskPriorityGetImpl                       \n"
                 " MPU_uxTaskPriorityGet_Unpriv:                         \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory"
@@ -178,12 +174,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_eTaskGetState_Unpriv                          \n"
                 " MPU_eTaskGetState_Priv:                               \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_eTaskGetStateImpl                           \n"
                 " MPU_eTaskGetState_Unpriv:                             \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory"
@@ -213,12 +208,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskGetInfo_Unpriv                           \n"
                 " MPU_vTaskGetInfo_Priv:                                \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskGetInfoImpl                            \n"
                 " MPU_vTaskGetInfo_Unpriv:                              \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory"
@@ -242,12 +236,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGetIdleTaskHandle_Unpriv                 \n"
                 " MPU_xTaskGetIdleTaskHandle_Priv:                      \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGetIdleTaskHandleImpl                  \n"
                 " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory"
@@ -271,12 +264,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskSuspend_Unpriv                           \n"
                 " MPU_vTaskSuspend_Priv:                                \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskSuspendImpl                            \n"
                 " MPU_vTaskSuspend_Unpriv:                              \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory"
@@ -300,12 +292,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskResume_Unpriv                            \n"
                 " MPU_vTaskResume_Priv:                                 \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskResumeImpl                             \n"
                 " MPU_vTaskResume_Unpriv:                               \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskResume ) : "memory"
@@ -327,12 +318,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xTaskGetTickCount_Unpriv                      \n"
             " MPU_xTaskGetTickCount_Priv:                           \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xTaskGetTickCountImpl                       \n"
             " MPU_xTaskGetTickCount_Unpriv:                         \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory"
@@ -352,12 +342,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_uxTaskGetNumberOfTasks_Unpriv                 \n"
             " MPU_uxTaskGetNumberOfTasks_Priv:                      \n"
-            "     pop {r0}                                          \n"
             "     b MPU_uxTaskGetNumberOfTasksImpl                  \n"
             " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory"
@@ -379,12 +368,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGetRunTimeCounter_Unpriv                \n"
                 " MPU_ulTaskGetRunTimeCounter_Priv:                     \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGetRunTimeCounterImpl                 \n"
                 " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory"
@@ -408,12 +396,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGetRunTimePercent_Unpriv                \n"
                 " MPU_ulTaskGetRunTimePercent_Priv:                     \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGetRunTimePercentImpl                 \n"
                 " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory"
@@ -437,12 +424,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv            \n"
                 " MPU_ulTaskGetIdleRunTimePercent_Priv:                 \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGetIdleRunTimePercentImpl             \n"
                 " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory"
@@ -466,12 +452,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv            \n"
                 " MPU_ulTaskGetIdleRunTimeCounter_Priv:                 \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGetIdleRunTimeCounterImpl             \n"
                 " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory"
@@ -497,12 +482,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskSetApplicationTaskTag_Unpriv             \n"
                 " MPU_vTaskSetApplicationTaskTag_Priv:                  \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskSetApplicationTaskTagImpl              \n"
                 " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory"
@@ -526,12 +510,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGetApplicationTaskTag_Unpriv             \n"
                 " MPU_xTaskGetApplicationTaskTag_Priv:                  \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGetApplicationTaskTagImpl              \n"
                 " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory"
@@ -559,12 +542,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv      \n"
                 " MPU_vTaskSetThreadLocalStoragePointer_Priv:           \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskSetThreadLocalStoragePointerImpl       \n"
                 " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory"
@@ -590,12 +572,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv     \n"
                 " MPU_pvTaskGetThreadLocalStoragePointer_Priv:          \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_pvTaskGetThreadLocalStoragePointerImpl      \n"
                 " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory"
@@ -623,12 +604,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxTaskGetSystemState_Unpriv                   \n"
                 " MPU_uxTaskGetSystemState_Priv:                        \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxTaskGetSystemStateImpl                    \n"
                 " MPU_uxTaskGetSystemState_Unpriv:                      \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory"
@@ -652,12 +632,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxTaskGetStackHighWaterMark_Unpriv            \n"
                 " MPU_uxTaskGetStackHighWaterMark_Priv:                 \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxTaskGetStackHighWaterMarkImpl             \n"
                 " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory"
@@ -681,12 +660,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv           \n"
                 " MPU_uxTaskGetStackHighWaterMark2_Priv:                \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxTaskGetStackHighWaterMark2Impl            \n"
                 " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory"
@@ -710,12 +688,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGetCurrentTaskHandle_Unpriv              \n"
                 " MPU_xTaskGetCurrentTaskHandle_Priv:                   \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGetCurrentTaskHandleImpl               \n"
                 " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory"
@@ -739,12 +716,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGetSchedulerState_Unpriv                 \n"
                 " MPU_xTaskGetSchedulerState_Priv:                      \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGetSchedulerStateImpl                  \n"
                 " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory"
@@ -766,12 +742,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_vTaskSetTimeOutState_Unpriv                   \n"
             " MPU_vTaskSetTimeOutState_Priv:                        \n"
-            "     pop {r0}                                          \n"
             "     b MPU_vTaskSetTimeOutStateImpl                    \n"
             " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory"
@@ -793,12 +768,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xTaskCheckForTimeOut_Unpriv                   \n"
             " MPU_xTaskCheckForTimeOut_Priv:                        \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xTaskCheckForTimeOutImpl                    \n"
             " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory"
@@ -820,12 +794,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGenericNotify_Unpriv                     \n"
                 " MPU_xTaskGenericNotify_Priv:                          \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGenericNotifyImpl                      \n"
                 " MPU_xTaskGenericNotify_Unpriv:                        \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory"
@@ -849,12 +822,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGenericNotifyWait_Unpriv                 \n"
                 " MPU_xTaskGenericNotifyWait_Priv:                      \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGenericNotifyWaitImpl                  \n"
                 " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory"
@@ -882,12 +854,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGenericNotifyTake_Unpriv                \n"
                 " MPU_ulTaskGenericNotifyTake_Priv:                     \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGenericNotifyTakeImpl                 \n"
                 " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory"
@@ -913,12 +884,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGenericNotifyStateClear_Unpriv           \n"
                 " MPU_xTaskGenericNotifyStateClear_Priv:                \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGenericNotifyStateClearImpl            \n"
                 " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory"
@@ -946,12 +916,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGenericNotifyValueClear_Unpriv          \n"
                 " MPU_ulTaskGenericNotifyValueClear_Priv:               \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGenericNotifyValueClearImpl           \n"
                 " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory"
@@ -979,12 +948,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xQueueGenericSend_Unpriv                      \n"
             " MPU_xQueueGenericSend_Priv:                           \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xQueueGenericSendImpl                       \n"
             " MPU_xQueueGenericSend_Unpriv:                         \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory"
@@ -1004,12 +972,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_uxQueueMessagesWaiting_Unpriv                 \n"
             " MPU_uxQueueMessagesWaiting_Priv:                      \n"
-            "     pop {r0}                                          \n"
             "     b MPU_uxQueueMessagesWaitingImpl                  \n"
             " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory"
@@ -1029,12 +996,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_uxQueueSpacesAvailable_Unpriv                 \n"
             " MPU_uxQueueSpacesAvailable_Priv:                      \n"
-            "     pop {r0}                                          \n"
             "     b MPU_uxQueueSpacesAvailableImpl                  \n"
             " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory"
@@ -1058,12 +1024,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xQueueReceive_Unpriv                          \n"
             " MPU_xQueueReceive_Priv:                               \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xQueueReceiveImpl                           \n"
             " MPU_xQueueReceive_Unpriv:                             \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory"
@@ -1087,12 +1052,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xQueuePeek_Unpriv                             \n"
             " MPU_xQueuePeek_Priv:                                  \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xQueuePeekImpl                              \n"
             " MPU_xQueuePeek_Unpriv:                                \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory"
@@ -1114,12 +1078,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xQueueSemaphoreTake_Unpriv                    \n"
             " MPU_xQueueSemaphoreTake_Priv:                         \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xQueueSemaphoreTakeImpl                     \n"
             " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory"
@@ -1141,12 +1104,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xQueueGetMutexHolder_Unpriv                   \n"
                 " MPU_xQueueGetMutexHolder_Priv:                        \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xQueueGetMutexHolderImpl                    \n"
                 " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory"
@@ -1172,12 +1134,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xQueueTakeMutexRecursive_Unpriv               \n"
                 " MPU_xQueueTakeMutexRecursive_Priv:                    \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xQueueTakeMutexRecursiveImpl                \n"
                 " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory"
@@ -1201,12 +1162,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xQueueGiveMutexRecursive_Unpriv               \n"
                 " MPU_xQueueGiveMutexRecursive_Priv:                    \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xQueueGiveMutexRecursiveImpl                \n"
                 " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory"
@@ -1232,12 +1192,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xQueueSelectFromSet_Unpriv                    \n"
                 " MPU_xQueueSelectFromSet_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xQueueSelectFromSetImpl                     \n"
                 " MPU_xQueueSelectFromSet_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory"
@@ -1263,12 +1222,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xQueueAddToSet_Unpriv                         \n"
                 " MPU_xQueueAddToSet_Priv:                              \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xQueueAddToSetImpl                          \n"
                 " MPU_xQueueAddToSet_Unpriv:                            \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory"
@@ -1294,12 +1252,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vQueueAddToRegistry_Unpriv                    \n"
                 " MPU_vQueueAddToRegistry_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vQueueAddToRegistryImpl                     \n"
                 " MPU_vQueueAddToRegistry_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory"
@@ -1323,12 +1280,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vQueueUnregisterQueue_Unpriv                  \n"
                 " MPU_vQueueUnregisterQueue_Priv:                       \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vQueueUnregisterQueueImpl                   \n"
                 " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory"
@@ -1352,12 +1308,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_pcQueueGetName_Unpriv                         \n"
                 " MPU_pcQueueGetName_Priv:                              \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_pcQueueGetNameImpl                          \n"
                 " MPU_pcQueueGetName_Unpriv:                            \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory"
@@ -1381,12 +1336,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_pvTimerGetTimerID_Unpriv                      \n"
                 " MPU_pvTimerGetTimerID_Priv:                           \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_pvTimerGetTimerIDImpl                       \n"
                 " MPU_pvTimerGetTimerID_Unpriv:                         \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory"
@@ -1412,12 +1366,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTimerSetTimerID_Unpriv                       \n"
                 " MPU_vTimerSetTimerID_Priv:                            \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTimerSetTimerIDImpl                        \n"
                 " MPU_vTimerSetTimerID_Unpriv:                          \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory"
@@ -1441,12 +1394,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTimerIsTimerActive_Unpriv                    \n"
                 " MPU_xTimerIsTimerActive_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTimerIsTimerActiveImpl                     \n"
                 " MPU_xTimerIsTimerActive_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory"
@@ -1470,12 +1422,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv         \n"
                 " MPU_xTimerGetTimerDaemonTaskHandle_Priv:              \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTimerGetTimerDaemonTaskHandleImpl          \n"
                 " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory"
@@ -1493,20 +1444,19 @@
         {
             __asm volatile
             (
-                " .syntax unified                                               \n"
-                " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
-                "                                                               \n"
-                " push {r0}                                                     \n"
-                " mrs r0, control                                               \n"
-                " tst r0, #1                                                    \n"
-                " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
-                " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
-                "     pop {r0}                                                  \n"
-                "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
-                " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
-                "     pop {r0}                                                  \n"
-                "     svc %0                                                    \n"
-                "                                                               \n"
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGenericCommandFromTaskImpl          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xTimerGenericCommandFromTask_Unpriv           \n"
+                " MPU_xTimerGenericCommandFromTask_Priv:                \n"
+                "     b MPU_xTimerGenericCommandFromTaskImpl            \n"
+                " MPU_xTimerGenericCommandFromTask_Unpriv:              \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory"
             );
         }
@@ -1528,12 +1478,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_pcTimerGetName_Unpriv                         \n"
                 " MPU_pcTimerGetName_Priv:                              \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_pcTimerGetNameImpl                          \n"
                 " MPU_pcTimerGetName_Unpriv:                            \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory"
@@ -1559,12 +1508,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTimerSetReloadMode_Unpriv                    \n"
                 " MPU_vTimerSetReloadMode_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTimerSetReloadModeImpl                     \n"
                 " MPU_vTimerSetReloadMode_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory"
@@ -1588,12 +1536,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTimerGetReloadMode_Unpriv                    \n"
                 " MPU_xTimerGetReloadMode_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTimerGetReloadModeImpl                     \n"
                 " MPU_xTimerGetReloadMode_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory"
@@ -1617,12 +1564,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxTimerGetReloadMode_Unpriv                   \n"
                 " MPU_uxTimerGetReloadMode_Priv:                        \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxTimerGetReloadModeImpl                    \n"
                 " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory"
@@ -1646,12 +1592,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTimerGetPeriod_Unpriv                        \n"
                 " MPU_xTimerGetPeriod_Priv:                             \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTimerGetPeriodImpl                         \n"
                 " MPU_xTimerGetPeriod_Unpriv:                           \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory"
@@ -1675,12 +1620,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTimerGetExpiryTime_Unpriv                    \n"
                 " MPU_xTimerGetExpiryTime_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTimerGetExpiryTimeImpl                     \n"
                 " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory"
@@ -1702,12 +1646,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
             " MPU_xEventGroupWaitBits_Priv:                         \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xEventGroupWaitBitsImpl                     \n"
             " MPU_xEventGroupWaitBits_Unpriv:                       \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
@@ -1729,12 +1672,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xEventGroupClearBits_Unpriv                   \n"
             " MPU_xEventGroupClearBits_Priv:                        \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xEventGroupClearBitsImpl                    \n"
             " MPU_xEventGroupClearBits_Unpriv:                      \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
@@ -1756,12 +1698,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xEventGroupSetBits_Unpriv                     \n"
             " MPU_xEventGroupSetBits_Priv:                          \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xEventGroupSetBitsImpl                      \n"
             " MPU_xEventGroupSetBits_Unpriv:                        \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
@@ -1787,12 +1728,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xEventGroupSync_Unpriv                        \n"
             " MPU_xEventGroupSync_Priv:                             \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xEventGroupSyncImpl                         \n"
             " MPU_xEventGroupSync_Unpriv:                           \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
@@ -1814,12 +1754,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxEventGroupGetNumber_Unpriv                  \n"
                 " MPU_uxEventGroupGetNumber_Priv:                       \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxEventGroupGetNumberImpl                   \n"
                 " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory"
@@ -1845,12 +1784,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vEventGroupSetNumber_Unpriv                   \n"
                 " MPU_vEventGroupSetNumber_Priv:                        \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vEventGroupSetNumberImpl                    \n"
                 " MPU_vEventGroupSetNumber_Unpriv:                      \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory"
@@ -1878,12 +1816,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferSend_Unpriv                      \n"
             " MPU_xStreamBufferSend_Priv:                           \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferSendImpl                       \n"
             " MPU_xStreamBufferSend_Unpriv:                         \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
@@ -1909,12 +1846,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferReceive_Unpriv                   \n"
             " MPU_xStreamBufferReceive_Priv:                        \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferReceiveImpl                    \n"
             " MPU_xStreamBufferReceive_Unpriv:                      \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
@@ -1934,12 +1870,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
             " MPU_xStreamBufferIsFull_Priv:                         \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferIsFullImpl                     \n"
             " MPU_xStreamBufferIsFull_Unpriv:                       \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
@@ -1959,12 +1894,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
             " MPU_xStreamBufferIsEmpty_Priv:                        \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferIsEmptyImpl                    \n"
             " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
@@ -1984,12 +1918,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
             " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
             " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
@@ -2009,12 +1942,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
             " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferBytesAvailableImpl             \n"
             " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
@@ -2036,12 +1968,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
             " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
             " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
@@ -2061,12 +1992,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
             " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
             " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/mpu_wrappers_v2_asm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/mpu_wrappers_v2_asm.c
index 170d10fcc..4f66448f9 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/mpu_wrappers_v2_asm.c
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/mpu_wrappers_v2_asm.c
@@ -62,12 +62,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskDelayUntil_Unpriv                        \n"
                 " MPU_xTaskDelayUntil_Priv:                             \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskDelayUntilImpl                         \n"
                 " MPU_xTaskDelayUntil_Unpriv:                           \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory"
@@ -91,12 +90,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskAbortDelay_Unpriv                        \n"
                 " MPU_xTaskAbortDelay_Priv:                             \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskAbortDelayImpl                         \n"
                 " MPU_xTaskAbortDelay_Unpriv:                           \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory"
@@ -120,12 +118,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskDelay_Unpriv                             \n"
                 " MPU_vTaskDelay_Priv:                                  \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskDelayImpl                              \n"
                 " MPU_vTaskDelay_Unpriv:                                \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory"
@@ -149,12 +146,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxTaskPriorityGet_Unpriv                      \n"
                 " MPU_uxTaskPriorityGet_Priv:                           \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxTaskPriorityGetImpl                       \n"
                 " MPU_uxTaskPriorityGet_Unpriv:                         \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory"
@@ -178,12 +174,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_eTaskGetState_Unpriv                          \n"
                 " MPU_eTaskGetState_Priv:                               \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_eTaskGetStateImpl                           \n"
                 " MPU_eTaskGetState_Unpriv:                             \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory"
@@ -213,12 +208,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskGetInfo_Unpriv                           \n"
                 " MPU_vTaskGetInfo_Priv:                                \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskGetInfoImpl                            \n"
                 " MPU_vTaskGetInfo_Unpriv:                              \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory"
@@ -242,12 +236,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGetIdleTaskHandle_Unpriv                 \n"
                 " MPU_xTaskGetIdleTaskHandle_Priv:                      \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGetIdleTaskHandleImpl                  \n"
                 " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory"
@@ -271,12 +264,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskSuspend_Unpriv                           \n"
                 " MPU_vTaskSuspend_Priv:                                \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskSuspendImpl                            \n"
                 " MPU_vTaskSuspend_Unpriv:                              \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory"
@@ -300,12 +292,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskResume_Unpriv                            \n"
                 " MPU_vTaskResume_Priv:                                 \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskResumeImpl                             \n"
                 " MPU_vTaskResume_Unpriv:                               \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskResume ) : "memory"
@@ -327,12 +318,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xTaskGetTickCount_Unpriv                      \n"
             " MPU_xTaskGetTickCount_Priv:                           \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xTaskGetTickCountImpl                       \n"
             " MPU_xTaskGetTickCount_Unpriv:                         \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory"
@@ -352,12 +342,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_uxTaskGetNumberOfTasks_Unpriv                 \n"
             " MPU_uxTaskGetNumberOfTasks_Priv:                      \n"
-            "     pop {r0}                                          \n"
             "     b MPU_uxTaskGetNumberOfTasksImpl                  \n"
             " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory"
@@ -379,12 +368,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGetRunTimeCounter_Unpriv                \n"
                 " MPU_ulTaskGetRunTimeCounter_Priv:                     \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGetRunTimeCounterImpl                 \n"
                 " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory"
@@ -408,12 +396,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGetRunTimePercent_Unpriv                \n"
                 " MPU_ulTaskGetRunTimePercent_Priv:                     \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGetRunTimePercentImpl                 \n"
                 " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory"
@@ -437,12 +424,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv            \n"
                 " MPU_ulTaskGetIdleRunTimePercent_Priv:                 \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGetIdleRunTimePercentImpl             \n"
                 " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory"
@@ -466,12 +452,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv            \n"
                 " MPU_ulTaskGetIdleRunTimeCounter_Priv:                 \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGetIdleRunTimeCounterImpl             \n"
                 " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory"
@@ -497,12 +482,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskSetApplicationTaskTag_Unpriv             \n"
                 " MPU_vTaskSetApplicationTaskTag_Priv:                  \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskSetApplicationTaskTagImpl              \n"
                 " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory"
@@ -526,12 +510,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGetApplicationTaskTag_Unpriv             \n"
                 " MPU_xTaskGetApplicationTaskTag_Priv:                  \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGetApplicationTaskTagImpl              \n"
                 " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory"
@@ -559,12 +542,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv      \n"
                 " MPU_vTaskSetThreadLocalStoragePointer_Priv:           \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskSetThreadLocalStoragePointerImpl       \n"
                 " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory"
@@ -590,12 +572,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv     \n"
                 " MPU_pvTaskGetThreadLocalStoragePointer_Priv:          \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_pvTaskGetThreadLocalStoragePointerImpl      \n"
                 " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory"
@@ -623,12 +604,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxTaskGetSystemState_Unpriv                   \n"
                 " MPU_uxTaskGetSystemState_Priv:                        \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxTaskGetSystemStateImpl                    \n"
                 " MPU_uxTaskGetSystemState_Unpriv:                      \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory"
@@ -652,12 +632,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxTaskGetStackHighWaterMark_Unpriv            \n"
                 " MPU_uxTaskGetStackHighWaterMark_Priv:                 \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxTaskGetStackHighWaterMarkImpl             \n"
                 " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory"
@@ -681,12 +660,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv           \n"
                 " MPU_uxTaskGetStackHighWaterMark2_Priv:                \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxTaskGetStackHighWaterMark2Impl            \n"
                 " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory"
@@ -710,12 +688,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGetCurrentTaskHandle_Unpriv              \n"
                 " MPU_xTaskGetCurrentTaskHandle_Priv:                   \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGetCurrentTaskHandleImpl               \n"
                 " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory"
@@ -739,12 +716,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGetSchedulerState_Unpriv                 \n"
                 " MPU_xTaskGetSchedulerState_Priv:                      \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGetSchedulerStateImpl                  \n"
                 " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory"
@@ -766,12 +742,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_vTaskSetTimeOutState_Unpriv                   \n"
             " MPU_vTaskSetTimeOutState_Priv:                        \n"
-            "     pop {r0}                                          \n"
             "     b MPU_vTaskSetTimeOutStateImpl                    \n"
             " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory"
@@ -793,12 +768,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xTaskCheckForTimeOut_Unpriv                   \n"
             " MPU_xTaskCheckForTimeOut_Priv:                        \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xTaskCheckForTimeOutImpl                    \n"
             " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory"
@@ -820,12 +794,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGenericNotify_Unpriv                     \n"
                 " MPU_xTaskGenericNotify_Priv:                          \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGenericNotifyImpl                      \n"
                 " MPU_xTaskGenericNotify_Unpriv:                        \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory"
@@ -849,12 +822,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGenericNotifyWait_Unpriv                 \n"
                 " MPU_xTaskGenericNotifyWait_Priv:                      \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGenericNotifyWaitImpl                  \n"
                 " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory"
@@ -882,12 +854,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGenericNotifyTake_Unpriv                \n"
                 " MPU_ulTaskGenericNotifyTake_Priv:                     \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGenericNotifyTakeImpl                 \n"
                 " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory"
@@ -913,12 +884,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGenericNotifyStateClear_Unpriv           \n"
                 " MPU_xTaskGenericNotifyStateClear_Priv:                \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGenericNotifyStateClearImpl            \n"
                 " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory"
@@ -946,12 +916,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGenericNotifyValueClear_Unpriv          \n"
                 " MPU_ulTaskGenericNotifyValueClear_Priv:               \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGenericNotifyValueClearImpl           \n"
                 " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory"
@@ -979,12 +948,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xQueueGenericSend_Unpriv                      \n"
             " MPU_xQueueGenericSend_Priv:                           \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xQueueGenericSendImpl                       \n"
             " MPU_xQueueGenericSend_Unpriv:                         \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory"
@@ -1004,12 +972,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_uxQueueMessagesWaiting_Unpriv                 \n"
             " MPU_uxQueueMessagesWaiting_Priv:                      \n"
-            "     pop {r0}                                          \n"
             "     b MPU_uxQueueMessagesWaitingImpl                  \n"
             " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory"
@@ -1029,12 +996,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_uxQueueSpacesAvailable_Unpriv                 \n"
             " MPU_uxQueueSpacesAvailable_Priv:                      \n"
-            "     pop {r0}                                          \n"
             "     b MPU_uxQueueSpacesAvailableImpl                  \n"
             " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory"
@@ -1058,12 +1024,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xQueueReceive_Unpriv                          \n"
             " MPU_xQueueReceive_Priv:                               \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xQueueReceiveImpl                           \n"
             " MPU_xQueueReceive_Unpriv:                             \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory"
@@ -1087,12 +1052,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xQueuePeek_Unpriv                             \n"
             " MPU_xQueuePeek_Priv:                                  \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xQueuePeekImpl                              \n"
             " MPU_xQueuePeek_Unpriv:                                \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory"
@@ -1114,12 +1078,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xQueueSemaphoreTake_Unpriv                    \n"
             " MPU_xQueueSemaphoreTake_Priv:                         \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xQueueSemaphoreTakeImpl                     \n"
             " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory"
@@ -1141,12 +1104,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xQueueGetMutexHolder_Unpriv                   \n"
                 " MPU_xQueueGetMutexHolder_Priv:                        \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xQueueGetMutexHolderImpl                    \n"
                 " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory"
@@ -1172,12 +1134,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xQueueTakeMutexRecursive_Unpriv               \n"
                 " MPU_xQueueTakeMutexRecursive_Priv:                    \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xQueueTakeMutexRecursiveImpl                \n"
                 " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory"
@@ -1201,12 +1162,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xQueueGiveMutexRecursive_Unpriv               \n"
                 " MPU_xQueueGiveMutexRecursive_Priv:                    \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xQueueGiveMutexRecursiveImpl                \n"
                 " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory"
@@ -1232,12 +1192,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xQueueSelectFromSet_Unpriv                    \n"
                 " MPU_xQueueSelectFromSet_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xQueueSelectFromSetImpl                     \n"
                 " MPU_xQueueSelectFromSet_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory"
@@ -1263,12 +1222,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xQueueAddToSet_Unpriv                         \n"
                 " MPU_xQueueAddToSet_Priv:                              \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xQueueAddToSetImpl                          \n"
                 " MPU_xQueueAddToSet_Unpriv:                            \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory"
@@ -1294,12 +1252,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vQueueAddToRegistry_Unpriv                    \n"
                 " MPU_vQueueAddToRegistry_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vQueueAddToRegistryImpl                     \n"
                 " MPU_vQueueAddToRegistry_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory"
@@ -1323,12 +1280,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vQueueUnregisterQueue_Unpriv                  \n"
                 " MPU_vQueueUnregisterQueue_Priv:                       \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vQueueUnregisterQueueImpl                   \n"
                 " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory"
@@ -1352,12 +1308,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_pcQueueGetName_Unpriv                         \n"
                 " MPU_pcQueueGetName_Priv:                              \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_pcQueueGetNameImpl                          \n"
                 " MPU_pcQueueGetName_Unpriv:                            \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory"
@@ -1381,12 +1336,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_pvTimerGetTimerID_Unpriv                      \n"
                 " MPU_pvTimerGetTimerID_Priv:                           \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_pvTimerGetTimerIDImpl                       \n"
                 " MPU_pvTimerGetTimerID_Unpriv:                         \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory"
@@ -1412,12 +1366,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTimerSetTimerID_Unpriv                       \n"
                 " MPU_vTimerSetTimerID_Priv:                            \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTimerSetTimerIDImpl                        \n"
                 " MPU_vTimerSetTimerID_Unpriv:                          \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory"
@@ -1441,12 +1394,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTimerIsTimerActive_Unpriv                    \n"
                 " MPU_xTimerIsTimerActive_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTimerIsTimerActiveImpl                     \n"
                 " MPU_xTimerIsTimerActive_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory"
@@ -1470,12 +1422,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv         \n"
                 " MPU_xTimerGetTimerDaemonTaskHandle_Priv:              \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTimerGetTimerDaemonTaskHandleImpl          \n"
                 " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory"
@@ -1493,20 +1444,19 @@
         {
             __asm volatile
             (
-                " .syntax unified                                               \n"
-                " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
-                "                                                               \n"
-                " push {r0}                                                     \n"
-                " mrs r0, control                                               \n"
-                " tst r0, #1                                                    \n"
-                " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
-                " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
-                "     pop {r0}                                                  \n"
-                "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
-                " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
-                "     pop {r0}                                                  \n"
-                "     svc %0                                                    \n"
-                "                                                               \n"
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGenericCommandFromTaskImpl          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xTimerGenericCommandFromTask_Unpriv           \n"
+                " MPU_xTimerGenericCommandFromTask_Priv:                \n"
+                "     b MPU_xTimerGenericCommandFromTaskImpl            \n"
+                " MPU_xTimerGenericCommandFromTask_Unpriv:              \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory"
             );
         }
@@ -1528,12 +1478,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_pcTimerGetName_Unpriv                         \n"
                 " MPU_pcTimerGetName_Priv:                              \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_pcTimerGetNameImpl                          \n"
                 " MPU_pcTimerGetName_Unpriv:                            \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory"
@@ -1559,12 +1508,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTimerSetReloadMode_Unpriv                    \n"
                 " MPU_vTimerSetReloadMode_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTimerSetReloadModeImpl                     \n"
                 " MPU_vTimerSetReloadMode_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory"
@@ -1588,12 +1536,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTimerGetReloadMode_Unpriv                    \n"
                 " MPU_xTimerGetReloadMode_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTimerGetReloadModeImpl                     \n"
                 " MPU_xTimerGetReloadMode_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory"
@@ -1617,12 +1564,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxTimerGetReloadMode_Unpriv                   \n"
                 " MPU_uxTimerGetReloadMode_Priv:                        \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxTimerGetReloadModeImpl                    \n"
                 " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory"
@@ -1646,12 +1592,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTimerGetPeriod_Unpriv                        \n"
                 " MPU_xTimerGetPeriod_Priv:                             \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTimerGetPeriodImpl                         \n"
                 " MPU_xTimerGetPeriod_Unpriv:                           \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory"
@@ -1675,12 +1620,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTimerGetExpiryTime_Unpriv                    \n"
                 " MPU_xTimerGetExpiryTime_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTimerGetExpiryTimeImpl                     \n"
                 " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory"
@@ -1702,12 +1646,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
             " MPU_xEventGroupWaitBits_Priv:                         \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xEventGroupWaitBitsImpl                     \n"
             " MPU_xEventGroupWaitBits_Unpriv:                       \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
@@ -1729,12 +1672,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xEventGroupClearBits_Unpriv                   \n"
             " MPU_xEventGroupClearBits_Priv:                        \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xEventGroupClearBitsImpl                    \n"
             " MPU_xEventGroupClearBits_Unpriv:                      \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
@@ -1756,12 +1698,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xEventGroupSetBits_Unpriv                     \n"
             " MPU_xEventGroupSetBits_Priv:                          \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xEventGroupSetBitsImpl                      \n"
             " MPU_xEventGroupSetBits_Unpriv:                        \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
@@ -1787,12 +1728,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xEventGroupSync_Unpriv                        \n"
             " MPU_xEventGroupSync_Priv:                             \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xEventGroupSyncImpl                         \n"
             " MPU_xEventGroupSync_Unpriv:                           \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
@@ -1814,12 +1754,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxEventGroupGetNumber_Unpriv                  \n"
                 " MPU_uxEventGroupGetNumber_Priv:                       \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxEventGroupGetNumberImpl                   \n"
                 " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory"
@@ -1845,12 +1784,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vEventGroupSetNumber_Unpriv                   \n"
                 " MPU_vEventGroupSetNumber_Priv:                        \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vEventGroupSetNumberImpl                    \n"
                 " MPU_vEventGroupSetNumber_Unpriv:                      \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory"
@@ -1878,12 +1816,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferSend_Unpriv                      \n"
             " MPU_xStreamBufferSend_Priv:                           \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferSendImpl                       \n"
             " MPU_xStreamBufferSend_Unpriv:                         \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
@@ -1909,12 +1846,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferReceive_Unpriv                   \n"
             " MPU_xStreamBufferReceive_Priv:                        \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferReceiveImpl                    \n"
             " MPU_xStreamBufferReceive_Unpriv:                      \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
@@ -1934,12 +1870,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
             " MPU_xStreamBufferIsFull_Priv:                         \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferIsFullImpl                     \n"
             " MPU_xStreamBufferIsFull_Unpriv:                       \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
@@ -1959,12 +1894,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
             " MPU_xStreamBufferIsEmpty_Priv:                        \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferIsEmptyImpl                    \n"
             " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
@@ -1984,12 +1918,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
             " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
             " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
@@ -2009,12 +1942,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
             " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferBytesAvailableImpl             \n"
             " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
@@ -2036,12 +1968,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
             " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
             " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
@@ -2061,12 +1992,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
             " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
             " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/mpu_wrappers_v2_asm.S b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/mpu_wrappers_v2_asm.S
index 8ea2f5c78..9289bcbc2 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/mpu_wrappers_v2_asm.S
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/mpu_wrappers_v2_asm.S
@@ -48,12 +48,11 @@ MPU_xTaskDelayUntil:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTaskDelayUntil_Unpriv
     MPU_xTaskDelayUntil_Priv:
-        pop {r0, r1}
         b MPU_xTaskDelayUntilImpl
     MPU_xTaskDelayUntil_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTaskDelayUntil
 /*-----------------------------------------------------------*/
 
@@ -63,12 +62,11 @@ MPU_xTaskAbortDelay:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTaskAbortDelay_Unpriv
     MPU_xTaskAbortDelay_Priv:
-        pop {r0, r1}
         b MPU_xTaskAbortDelayImpl
     MPU_xTaskAbortDelay_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTaskAbortDelay
 /*-----------------------------------------------------------*/
 
@@ -78,12 +76,11 @@ MPU_vTaskDelay:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_vTaskDelay_Unpriv
     MPU_vTaskDelay_Priv:
-        pop {r0, r1}
         b MPU_vTaskDelayImpl
     MPU_vTaskDelay_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_vTaskDelay
 /*-----------------------------------------------------------*/
 
@@ -93,12 +90,11 @@ MPU_uxTaskPriorityGet:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_uxTaskPriorityGet_Unpriv
     MPU_uxTaskPriorityGet_Priv:
-        pop {r0, r1}
         b MPU_uxTaskPriorityGetImpl
     MPU_uxTaskPriorityGet_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_uxTaskPriorityGet
 /*-----------------------------------------------------------*/
 
@@ -108,12 +104,11 @@ MPU_eTaskGetState:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_eTaskGetState_Unpriv
     MPU_eTaskGetState_Priv:
-        pop {r0, r1}
         b MPU_eTaskGetStateImpl
     MPU_eTaskGetState_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_eTaskGetState
 /*-----------------------------------------------------------*/
 
@@ -123,12 +118,11 @@ MPU_vTaskGetInfo:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_vTaskGetInfo_Unpriv
     MPU_vTaskGetInfo_Priv:
-        pop {r0, r1}
         b MPU_vTaskGetInfoImpl
     MPU_vTaskGetInfo_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_vTaskGetInfo
 /*-----------------------------------------------------------*/
 
@@ -138,12 +132,11 @@ MPU_xTaskGetIdleTaskHandle:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTaskGetIdleTaskHandle_Unpriv
     MPU_xTaskGetIdleTaskHandle_Priv:
-        pop {r0, r1}
         b MPU_xTaskGetIdleTaskHandleImpl
     MPU_xTaskGetIdleTaskHandle_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTaskGetIdleTaskHandle
 /*-----------------------------------------------------------*/
 
@@ -153,12 +146,11 @@ MPU_vTaskSuspend:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_vTaskSuspend_Unpriv
     MPU_vTaskSuspend_Priv:
-        pop {r0, r1}
         b MPU_vTaskSuspendImpl
     MPU_vTaskSuspend_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_vTaskSuspend
 /*-----------------------------------------------------------*/
 
@@ -168,12 +160,11 @@ MPU_vTaskResume:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_vTaskResume_Unpriv
     MPU_vTaskResume_Priv:
-        pop {r0, r1}
         b MPU_vTaskResumeImpl
     MPU_vTaskResume_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_vTaskResume
 /*-----------------------------------------------------------*/
 
@@ -183,12 +174,11 @@ MPU_xTaskGetTickCount:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTaskGetTickCount_Unpriv
     MPU_xTaskGetTickCount_Priv:
-        pop {r0, r1}
         b MPU_xTaskGetTickCountImpl
     MPU_xTaskGetTickCount_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTaskGetTickCount
 /*-----------------------------------------------------------*/
 
@@ -198,12 +188,11 @@ MPU_uxTaskGetNumberOfTasks:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_uxTaskGetNumberOfTasks_Unpriv
     MPU_uxTaskGetNumberOfTasks_Priv:
-        pop {r0, r1}
         b MPU_uxTaskGetNumberOfTasksImpl
     MPU_uxTaskGetNumberOfTasks_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_uxTaskGetNumberOfTasks
 /*-----------------------------------------------------------*/
 
@@ -213,12 +202,11 @@ MPU_ulTaskGetRunTimeCounter:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_ulTaskGetRunTimeCounter_Unpriv
     MPU_ulTaskGetRunTimeCounter_Priv:
-        pop {r0, r1}
         b MPU_ulTaskGetRunTimeCounterImpl
     MPU_ulTaskGetRunTimeCounter_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_ulTaskGetRunTimeCounter
 /*-----------------------------------------------------------*/
 
@@ -228,12 +216,11 @@ MPU_ulTaskGetRunTimePercent:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_ulTaskGetRunTimePercent_Unpriv
     MPU_ulTaskGetRunTimePercent_Priv:
-        pop {r0, r1}
         b MPU_ulTaskGetRunTimePercentImpl
     MPU_ulTaskGetRunTimePercent_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_ulTaskGetRunTimePercent
 /*-----------------------------------------------------------*/
 
@@ -243,12 +230,11 @@ MPU_ulTaskGetIdleRunTimePercent:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_ulTaskGetIdleRunTimePercent_Unpriv
     MPU_ulTaskGetIdleRunTimePercent_Priv:
-        pop {r0, r1}
         b MPU_ulTaskGetIdleRunTimePercentImpl
     MPU_ulTaskGetIdleRunTimePercent_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent
 /*-----------------------------------------------------------*/
 
@@ -258,12 +244,11 @@ MPU_ulTaskGetIdleRunTimeCounter:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv
     MPU_ulTaskGetIdleRunTimeCounter_Priv:
-        pop {r0, r1}
         b MPU_ulTaskGetIdleRunTimeCounterImpl
     MPU_ulTaskGetIdleRunTimeCounter_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter
 /*-----------------------------------------------------------*/
 
@@ -273,12 +258,11 @@ MPU_vTaskSetApplicationTaskTag:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_vTaskSetApplicationTaskTag_Unpriv
     MPU_vTaskSetApplicationTaskTag_Priv:
-        pop {r0, r1}
         b MPU_vTaskSetApplicationTaskTagImpl
     MPU_vTaskSetApplicationTaskTag_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_vTaskSetApplicationTaskTag
 /*-----------------------------------------------------------*/
 
@@ -288,12 +272,11 @@ MPU_xTaskGetApplicationTaskTag:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTaskGetApplicationTaskTag_Unpriv
     MPU_xTaskGetApplicationTaskTag_Priv:
-        pop {r0, r1}
         b MPU_xTaskGetApplicationTaskTagImpl
     MPU_xTaskGetApplicationTaskTag_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTaskGetApplicationTaskTag
 /*-----------------------------------------------------------*/
 
@@ -303,12 +286,11 @@ MPU_vTaskSetThreadLocalStoragePointer:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv
     MPU_vTaskSetThreadLocalStoragePointer_Priv:
-        pop {r0, r1}
         b MPU_vTaskSetThreadLocalStoragePointerImpl
     MPU_vTaskSetThreadLocalStoragePointer_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer
 /*-----------------------------------------------------------*/
 
@@ -318,12 +300,11 @@ MPU_pvTaskGetThreadLocalStoragePointer:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv
     MPU_pvTaskGetThreadLocalStoragePointer_Priv:
-        pop {r0, r1}
         b MPU_pvTaskGetThreadLocalStoragePointerImpl
     MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer
 /*-----------------------------------------------------------*/
 
@@ -333,12 +314,11 @@ MPU_uxTaskGetSystemState:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_uxTaskGetSystemState_Unpriv
     MPU_uxTaskGetSystemState_Priv:
-        pop {r0, r1}
         b MPU_uxTaskGetSystemStateImpl
     MPU_uxTaskGetSystemState_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_uxTaskGetSystemState
 /*-----------------------------------------------------------*/
 
@@ -348,12 +328,11 @@ MPU_uxTaskGetStackHighWaterMark:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_uxTaskGetStackHighWaterMark_Unpriv
     MPU_uxTaskGetStackHighWaterMark_Priv:
-        pop {r0, r1}
         b MPU_uxTaskGetStackHighWaterMarkImpl
     MPU_uxTaskGetStackHighWaterMark_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark
 /*-----------------------------------------------------------*/
 
@@ -363,12 +342,11 @@ MPU_uxTaskGetStackHighWaterMark2:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_uxTaskGetStackHighWaterMark2_Unpriv
     MPU_uxTaskGetStackHighWaterMark2_Priv:
-        pop {r0, r1}
         b MPU_uxTaskGetStackHighWaterMark2Impl
     MPU_uxTaskGetStackHighWaterMark2_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2
 /*-----------------------------------------------------------*/
 
@@ -378,12 +356,11 @@ MPU_xTaskGetCurrentTaskHandle:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTaskGetCurrentTaskHandle_Unpriv
     MPU_xTaskGetCurrentTaskHandle_Priv:
-        pop {r0, r1}
         b MPU_xTaskGetCurrentTaskHandleImpl
     MPU_xTaskGetCurrentTaskHandle_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle
 /*-----------------------------------------------------------*/
 
@@ -393,12 +370,11 @@ MPU_xTaskGetSchedulerState:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTaskGetSchedulerState_Unpriv
     MPU_xTaskGetSchedulerState_Priv:
-        pop {r0, r1}
         b MPU_xTaskGetSchedulerStateImpl
     MPU_xTaskGetSchedulerState_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTaskGetSchedulerState
 /*-----------------------------------------------------------*/
 
@@ -408,12 +384,11 @@ MPU_vTaskSetTimeOutState:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_vTaskSetTimeOutState_Unpriv
     MPU_vTaskSetTimeOutState_Priv:
-        pop {r0, r1}
         b MPU_vTaskSetTimeOutStateImpl
     MPU_vTaskSetTimeOutState_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_vTaskSetTimeOutState
 /*-----------------------------------------------------------*/
 
@@ -423,12 +398,11 @@ MPU_xTaskCheckForTimeOut:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTaskCheckForTimeOut_Unpriv
     MPU_xTaskCheckForTimeOut_Priv:
-        pop {r0, r1}
         b MPU_xTaskCheckForTimeOutImpl
     MPU_xTaskCheckForTimeOut_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTaskCheckForTimeOut
 /*-----------------------------------------------------------*/
 
@@ -438,12 +412,11 @@ MPU_xTaskGenericNotifyEntry:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTaskGenericNotify_Unpriv
     MPU_xTaskGenericNotify_Priv:
-        pop {r0, r1}
         b MPU_xTaskGenericNotifyImpl
     MPU_xTaskGenericNotify_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTaskGenericNotify
 /*-----------------------------------------------------------*/
 
@@ -453,12 +426,11 @@ MPU_xTaskGenericNotifyWaitEntry:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTaskGenericNotifyWait_Unpriv
     MPU_xTaskGenericNotifyWait_Priv:
-        pop {r0, r1}
         b MPU_xTaskGenericNotifyWaitImpl
     MPU_xTaskGenericNotifyWait_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTaskGenericNotifyWait
 /*-----------------------------------------------------------*/
 
@@ -468,12 +440,11 @@ MPU_ulTaskGenericNotifyTake:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_ulTaskGenericNotifyTake_Unpriv
     MPU_ulTaskGenericNotifyTake_Priv:
-        pop {r0, r1}
         b MPU_ulTaskGenericNotifyTakeImpl
     MPU_ulTaskGenericNotifyTake_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_ulTaskGenericNotifyTake
 /*-----------------------------------------------------------*/
 
@@ -483,12 +454,11 @@ MPU_xTaskGenericNotifyStateClear:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTaskGenericNotifyStateClear_Unpriv
     MPU_xTaskGenericNotifyStateClear_Priv:
-        pop {r0, r1}
         b MPU_xTaskGenericNotifyStateClearImpl
     MPU_xTaskGenericNotifyStateClear_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTaskGenericNotifyStateClear
 /*-----------------------------------------------------------*/
 
@@ -498,12 +468,11 @@ MPU_ulTaskGenericNotifyValueClear:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_ulTaskGenericNotifyValueClear_Unpriv
     MPU_ulTaskGenericNotifyValueClear_Priv:
-        pop {r0, r1}
         b MPU_ulTaskGenericNotifyValueClearImpl
     MPU_ulTaskGenericNotifyValueClear_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear
 /*-----------------------------------------------------------*/
 
@@ -513,12 +482,11 @@ MPU_xQueueGenericSend:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xQueueGenericSend_Unpriv
     MPU_xQueueGenericSend_Priv:
-        pop {r0, r1}
         b MPU_xQueueGenericSendImpl
     MPU_xQueueGenericSend_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xQueueGenericSend
 /*-----------------------------------------------------------*/
 
@@ -528,12 +496,11 @@ MPU_uxQueueMessagesWaiting:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_uxQueueMessagesWaiting_Unpriv
     MPU_uxQueueMessagesWaiting_Priv:
-        pop {r0, r1}
         b MPU_uxQueueMessagesWaitingImpl
     MPU_uxQueueMessagesWaiting_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_uxQueueMessagesWaiting
 /*-----------------------------------------------------------*/
 
@@ -543,12 +510,11 @@ MPU_uxQueueSpacesAvailable:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_uxQueueSpacesAvailable_Unpriv
     MPU_uxQueueSpacesAvailable_Priv:
-        pop {r0, r1}
         b MPU_uxQueueSpacesAvailableImpl
     MPU_uxQueueSpacesAvailable_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_uxQueueSpacesAvailable
 /*-----------------------------------------------------------*/
 
@@ -558,12 +524,11 @@ MPU_xQueueReceive:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xQueueReceive_Unpriv
     MPU_xQueueReceive_Priv:
-        pop {r0, r1}
         b MPU_xQueueReceiveImpl
     MPU_xQueueReceive_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xQueueReceive
 /*-----------------------------------------------------------*/
 
@@ -573,12 +538,11 @@ MPU_xQueuePeek:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xQueuePeek_Unpriv
     MPU_xQueuePeek_Priv:
-        pop {r0, r1}
         b MPU_xQueuePeekImpl
     MPU_xQueuePeek_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xQueuePeek
 /*-----------------------------------------------------------*/
 
@@ -588,12 +552,11 @@ MPU_xQueueSemaphoreTake:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xQueueSemaphoreTake_Unpriv
     MPU_xQueueSemaphoreTake_Priv:
-        pop {r0, r1}
         b MPU_xQueueSemaphoreTakeImpl
     MPU_xQueueSemaphoreTake_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xQueueSemaphoreTake
 /*-----------------------------------------------------------*/
 
@@ -603,12 +566,11 @@ MPU_xQueueGetMutexHolder:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xQueueGetMutexHolder_Unpriv
     MPU_xQueueGetMutexHolder_Priv:
-        pop {r0, r1}
         b MPU_xQueueGetMutexHolderImpl
     MPU_xQueueGetMutexHolder_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xQueueGetMutexHolder
 /*-----------------------------------------------------------*/
 
@@ -618,12 +580,11 @@ MPU_xQueueTakeMutexRecursive:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xQueueTakeMutexRecursive_Unpriv
     MPU_xQueueTakeMutexRecursive_Priv:
-        pop {r0, r1}
         b MPU_xQueueTakeMutexRecursiveImpl
     MPU_xQueueTakeMutexRecursive_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xQueueTakeMutexRecursive
 /*-----------------------------------------------------------*/
 
@@ -633,12 +594,11 @@ MPU_xQueueGiveMutexRecursive:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xQueueGiveMutexRecursive_Unpriv
     MPU_xQueueGiveMutexRecursive_Priv:
-        pop {r0, r1}
         b MPU_xQueueGiveMutexRecursiveImpl
     MPU_xQueueGiveMutexRecursive_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xQueueGiveMutexRecursive
 /*-----------------------------------------------------------*/
 
@@ -648,12 +608,11 @@ MPU_xQueueSelectFromSet:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xQueueSelectFromSet_Unpriv
     MPU_xQueueSelectFromSet_Priv:
-        pop {r0, r1}
         b MPU_xQueueSelectFromSetImpl
     MPU_xQueueSelectFromSet_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xQueueSelectFromSet
 /*-----------------------------------------------------------*/
 
@@ -663,12 +622,11 @@ MPU_xQueueAddToSet:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xQueueAddToSet_Unpriv
     MPU_xQueueAddToSet_Priv:
-        pop {r0, r1}
         b MPU_xQueueAddToSetImpl
     MPU_xQueueAddToSet_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xQueueAddToSet
 /*-----------------------------------------------------------*/
 
@@ -678,12 +636,11 @@ MPU_vQueueAddToRegistry:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_vQueueAddToRegistry_Unpriv
     MPU_vQueueAddToRegistry_Priv:
-        pop {r0, r1}
         b MPU_vQueueAddToRegistryImpl
     MPU_vQueueAddToRegistry_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_vQueueAddToRegistry
 /*-----------------------------------------------------------*/
 
@@ -693,12 +650,11 @@ MPU_vQueueUnregisterQueue:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_vQueueUnregisterQueue_Unpriv
     MPU_vQueueUnregisterQueue_Priv:
-        pop {r0, r1}
         b MPU_vQueueUnregisterQueueImpl
     MPU_vQueueUnregisterQueue_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_vQueueUnregisterQueue
 /*-----------------------------------------------------------*/
 
@@ -708,12 +664,11 @@ MPU_pcQueueGetName:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_pcQueueGetName_Unpriv
     MPU_pcQueueGetName_Priv:
-        pop {r0, r1}
         b MPU_pcQueueGetNameImpl
     MPU_pcQueueGetName_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_pcQueueGetName
 /*-----------------------------------------------------------*/
 
@@ -723,12 +678,11 @@ MPU_pvTimerGetTimerID:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_pvTimerGetTimerID_Unpriv
     MPU_pvTimerGetTimerID_Priv:
-        pop {r0, r1}
         b MPU_pvTimerGetTimerIDImpl
     MPU_pvTimerGetTimerID_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_pvTimerGetTimerID
 /*-----------------------------------------------------------*/
 
@@ -738,12 +692,11 @@ MPU_vTimerSetTimerID:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_vTimerSetTimerID_Unpriv
     MPU_vTimerSetTimerID_Priv:
-        pop {r0, r1}
         b MPU_vTimerSetTimerIDImpl
     MPU_vTimerSetTimerID_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_vTimerSetTimerID
 /*-----------------------------------------------------------*/
 
@@ -753,12 +706,11 @@ MPU_xTimerIsTimerActive:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTimerIsTimerActive_Unpriv
     MPU_xTimerIsTimerActive_Priv:
-        pop {r0, r1}
         b MPU_xTimerIsTimerActiveImpl
     MPU_xTimerIsTimerActive_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTimerIsTimerActive
 /*-----------------------------------------------------------*/
 
@@ -768,12 +720,11 @@ MPU_xTimerGetTimerDaemonTaskHandle:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv
     MPU_xTimerGetTimerDaemonTaskHandle_Priv:
-        pop {r0, r1}
         b MPU_xTimerGetTimerDaemonTaskHandleImpl
     MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle
 /*-----------------------------------------------------------*/
 
@@ -783,12 +734,11 @@ MPU_xTimerGenericCommandFromTaskEntry:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTimerGenericCommandFromTask_Unpriv
     MPU_xTimerGenericCommandFromTask_Priv:
-        pop {r0, r1}
         b MPU_xTimerGenericCommandFromTaskImpl
     MPU_xTimerGenericCommandFromTask_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTimerGenericCommandFromTask
 /*-----------------------------------------------------------*/
 
@@ -798,12 +748,11 @@ MPU_pcTimerGetName:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_pcTimerGetName_Unpriv
     MPU_pcTimerGetName_Priv:
-        pop {r0, r1}
         b MPU_pcTimerGetNameImpl
     MPU_pcTimerGetName_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_pcTimerGetName
 /*-----------------------------------------------------------*/
 
@@ -813,12 +762,11 @@ MPU_vTimerSetReloadMode:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_vTimerSetReloadMode_Unpriv
     MPU_vTimerSetReloadMode_Priv:
-        pop {r0, r1}
         b MPU_vTimerSetReloadModeImpl
     MPU_vTimerSetReloadMode_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_vTimerSetReloadMode
 /*-----------------------------------------------------------*/
 
@@ -828,12 +776,11 @@ MPU_xTimerGetReloadMode:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTimerGetReloadMode_Unpriv
     MPU_xTimerGetReloadMode_Priv:
-        pop {r0, r1}
         b MPU_xTimerGetReloadModeImpl
     MPU_xTimerGetReloadMode_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTimerGetReloadMode
 /*-----------------------------------------------------------*/
 
@@ -843,12 +790,11 @@ MPU_uxTimerGetReloadMode:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_uxTimerGetReloadMode_Unpriv
     MPU_uxTimerGetReloadMode_Priv:
-        pop {r0, r1}
         b MPU_uxTimerGetReloadModeImpl
     MPU_uxTimerGetReloadMode_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_uxTimerGetReloadMode
 /*-----------------------------------------------------------*/
 
@@ -858,12 +804,11 @@ MPU_xTimerGetPeriod:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTimerGetPeriod_Unpriv
     MPU_xTimerGetPeriod_Priv:
-        pop {r0, r1}
         b MPU_xTimerGetPeriodImpl
     MPU_xTimerGetPeriod_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTimerGetPeriod
 /*-----------------------------------------------------------*/
 
@@ -873,12 +818,11 @@ MPU_xTimerGetExpiryTime:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTimerGetExpiryTime_Unpriv
     MPU_xTimerGetExpiryTime_Priv:
-        pop {r0, r1}
         b MPU_xTimerGetExpiryTimeImpl
     MPU_xTimerGetExpiryTime_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTimerGetExpiryTime
 /*-----------------------------------------------------------*/
 
@@ -888,12 +832,11 @@ MPU_xEventGroupWaitBitsEntry:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xEventGroupWaitBits_Unpriv
     MPU_xEventGroupWaitBits_Priv:
-        pop {r0, r1}
         b MPU_xEventGroupWaitBitsImpl
     MPU_xEventGroupWaitBits_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xEventGroupWaitBits
 /*-----------------------------------------------------------*/
 
@@ -903,12 +846,11 @@ MPU_xEventGroupClearBits:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xEventGroupClearBits_Unpriv
     MPU_xEventGroupClearBits_Priv:
-        pop {r0, r1}
         b MPU_xEventGroupClearBitsImpl
     MPU_xEventGroupClearBits_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xEventGroupClearBits
 /*-----------------------------------------------------------*/
 
@@ -918,12 +860,11 @@ MPU_xEventGroupSetBits:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xEventGroupSetBits_Unpriv
     MPU_xEventGroupSetBits_Priv:
-        pop {r0, r1}
         b MPU_xEventGroupSetBitsImpl
     MPU_xEventGroupSetBits_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xEventGroupSetBits
 /*-----------------------------------------------------------*/
 
@@ -933,12 +874,11 @@ MPU_xEventGroupSync:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xEventGroupSync_Unpriv
     MPU_xEventGroupSync_Priv:
-        pop {r0, r1}
         b MPU_xEventGroupSyncImpl
     MPU_xEventGroupSync_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xEventGroupSync
 /*-----------------------------------------------------------*/
 
@@ -948,12 +888,11 @@ MPU_uxEventGroupGetNumber:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_uxEventGroupGetNumber_Unpriv
     MPU_uxEventGroupGetNumber_Priv:
-        pop {r0, r1}
         b MPU_uxEventGroupGetNumberImpl
     MPU_uxEventGroupGetNumber_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_uxEventGroupGetNumber
 /*-----------------------------------------------------------*/
 
@@ -963,12 +902,11 @@ MPU_vEventGroupSetNumber:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_vEventGroupSetNumber_Unpriv
     MPU_vEventGroupSetNumber_Priv:
-        pop {r0, r1}
         b MPU_vEventGroupSetNumberImpl
     MPU_vEventGroupSetNumber_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_vEventGroupSetNumber
 /*-----------------------------------------------------------*/
 
@@ -978,12 +916,11 @@ MPU_xStreamBufferSend:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xStreamBufferSend_Unpriv
     MPU_xStreamBufferSend_Priv:
-        pop {r0, r1}
         b MPU_xStreamBufferSendImpl
     MPU_xStreamBufferSend_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xStreamBufferSend
 /*-----------------------------------------------------------*/
 
@@ -993,12 +930,11 @@ MPU_xStreamBufferReceive:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xStreamBufferReceive_Unpriv
     MPU_xStreamBufferReceive_Priv:
-        pop {r0, r1}
         b MPU_xStreamBufferReceiveImpl
     MPU_xStreamBufferReceive_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xStreamBufferReceive
 /*-----------------------------------------------------------*/
 
@@ -1008,12 +944,11 @@ MPU_xStreamBufferIsFull:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xStreamBufferIsFull_Unpriv
     MPU_xStreamBufferIsFull_Priv:
-        pop {r0, r1}
         b MPU_xStreamBufferIsFullImpl
     MPU_xStreamBufferIsFull_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xStreamBufferIsFull
 /*-----------------------------------------------------------*/
 
@@ -1023,12 +958,11 @@ MPU_xStreamBufferIsEmpty:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xStreamBufferIsEmpty_Unpriv
     MPU_xStreamBufferIsEmpty_Priv:
-        pop {r0, r1}
         b MPU_xStreamBufferIsEmptyImpl
     MPU_xStreamBufferIsEmpty_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xStreamBufferIsEmpty
 /*-----------------------------------------------------------*/
 
@@ -1038,12 +972,11 @@ MPU_xStreamBufferSpacesAvailable:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xStreamBufferSpacesAvailable_Unpriv
     MPU_xStreamBufferSpacesAvailable_Priv:
-        pop {r0, r1}
         b MPU_xStreamBufferSpacesAvailableImpl
     MPU_xStreamBufferSpacesAvailable_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xStreamBufferSpacesAvailable
 /*-----------------------------------------------------------*/
 
@@ -1053,12 +986,11 @@ MPU_xStreamBufferBytesAvailable:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xStreamBufferBytesAvailable_Unpriv
     MPU_xStreamBufferBytesAvailable_Priv:
-        pop {r0, r1}
         b MPU_xStreamBufferBytesAvailableImpl
     MPU_xStreamBufferBytesAvailable_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xStreamBufferBytesAvailable
 /*-----------------------------------------------------------*/
 
@@ -1068,12 +1000,11 @@ MPU_xStreamBufferSetTriggerLevel:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xStreamBufferSetTriggerLevel_Unpriv
     MPU_xStreamBufferSetTriggerLevel_Priv:
-        pop {r0, r1}
         b MPU_xStreamBufferSetTriggerLevelImpl
     MPU_xStreamBufferSetTriggerLevel_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel
 /*-----------------------------------------------------------*/
 
@@ -1083,12 +1014,11 @@ MPU_xStreamBufferNextMessageLengthBytes:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv
     MPU_xStreamBufferNextMessageLengthBytes_Priv:
-        pop {r0, r1}
         b MPU_xStreamBufferNextMessageLengthBytesImpl
     MPU_xStreamBufferNextMessageLengthBytes_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes
 /*-----------------------------------------------------------*/
 
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/mpu_wrappers_v2_asm.S b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/mpu_wrappers_v2_asm.S
index 8ea2f5c78..9289bcbc2 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/mpu_wrappers_v2_asm.S
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/mpu_wrappers_v2_asm.S
@@ -48,12 +48,11 @@ MPU_xTaskDelayUntil:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTaskDelayUntil_Unpriv
     MPU_xTaskDelayUntil_Priv:
-        pop {r0, r1}
         b MPU_xTaskDelayUntilImpl
     MPU_xTaskDelayUntil_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTaskDelayUntil
 /*-----------------------------------------------------------*/
 
@@ -63,12 +62,11 @@ MPU_xTaskAbortDelay:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTaskAbortDelay_Unpriv
     MPU_xTaskAbortDelay_Priv:
-        pop {r0, r1}
         b MPU_xTaskAbortDelayImpl
     MPU_xTaskAbortDelay_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTaskAbortDelay
 /*-----------------------------------------------------------*/
 
@@ -78,12 +76,11 @@ MPU_vTaskDelay:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_vTaskDelay_Unpriv
     MPU_vTaskDelay_Priv:
-        pop {r0, r1}
         b MPU_vTaskDelayImpl
     MPU_vTaskDelay_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_vTaskDelay
 /*-----------------------------------------------------------*/
 
@@ -93,12 +90,11 @@ MPU_uxTaskPriorityGet:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_uxTaskPriorityGet_Unpriv
     MPU_uxTaskPriorityGet_Priv:
-        pop {r0, r1}
         b MPU_uxTaskPriorityGetImpl
     MPU_uxTaskPriorityGet_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_uxTaskPriorityGet
 /*-----------------------------------------------------------*/
 
@@ -108,12 +104,11 @@ MPU_eTaskGetState:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_eTaskGetState_Unpriv
     MPU_eTaskGetState_Priv:
-        pop {r0, r1}
         b MPU_eTaskGetStateImpl
     MPU_eTaskGetState_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_eTaskGetState
 /*-----------------------------------------------------------*/
 
@@ -123,12 +118,11 @@ MPU_vTaskGetInfo:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_vTaskGetInfo_Unpriv
     MPU_vTaskGetInfo_Priv:
-        pop {r0, r1}
         b MPU_vTaskGetInfoImpl
     MPU_vTaskGetInfo_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_vTaskGetInfo
 /*-----------------------------------------------------------*/
 
@@ -138,12 +132,11 @@ MPU_xTaskGetIdleTaskHandle:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTaskGetIdleTaskHandle_Unpriv
     MPU_xTaskGetIdleTaskHandle_Priv:
-        pop {r0, r1}
         b MPU_xTaskGetIdleTaskHandleImpl
     MPU_xTaskGetIdleTaskHandle_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTaskGetIdleTaskHandle
 /*-----------------------------------------------------------*/
 
@@ -153,12 +146,11 @@ MPU_vTaskSuspend:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_vTaskSuspend_Unpriv
     MPU_vTaskSuspend_Priv:
-        pop {r0, r1}
         b MPU_vTaskSuspendImpl
     MPU_vTaskSuspend_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_vTaskSuspend
 /*-----------------------------------------------------------*/
 
@@ -168,12 +160,11 @@ MPU_vTaskResume:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_vTaskResume_Unpriv
     MPU_vTaskResume_Priv:
-        pop {r0, r1}
         b MPU_vTaskResumeImpl
     MPU_vTaskResume_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_vTaskResume
 /*-----------------------------------------------------------*/
 
@@ -183,12 +174,11 @@ MPU_xTaskGetTickCount:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTaskGetTickCount_Unpriv
     MPU_xTaskGetTickCount_Priv:
-        pop {r0, r1}
         b MPU_xTaskGetTickCountImpl
     MPU_xTaskGetTickCount_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTaskGetTickCount
 /*-----------------------------------------------------------*/
 
@@ -198,12 +188,11 @@ MPU_uxTaskGetNumberOfTasks:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_uxTaskGetNumberOfTasks_Unpriv
     MPU_uxTaskGetNumberOfTasks_Priv:
-        pop {r0, r1}
         b MPU_uxTaskGetNumberOfTasksImpl
     MPU_uxTaskGetNumberOfTasks_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_uxTaskGetNumberOfTasks
 /*-----------------------------------------------------------*/
 
@@ -213,12 +202,11 @@ MPU_ulTaskGetRunTimeCounter:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_ulTaskGetRunTimeCounter_Unpriv
     MPU_ulTaskGetRunTimeCounter_Priv:
-        pop {r0, r1}
         b MPU_ulTaskGetRunTimeCounterImpl
     MPU_ulTaskGetRunTimeCounter_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_ulTaskGetRunTimeCounter
 /*-----------------------------------------------------------*/
 
@@ -228,12 +216,11 @@ MPU_ulTaskGetRunTimePercent:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_ulTaskGetRunTimePercent_Unpriv
     MPU_ulTaskGetRunTimePercent_Priv:
-        pop {r0, r1}
         b MPU_ulTaskGetRunTimePercentImpl
     MPU_ulTaskGetRunTimePercent_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_ulTaskGetRunTimePercent
 /*-----------------------------------------------------------*/
 
@@ -243,12 +230,11 @@ MPU_ulTaskGetIdleRunTimePercent:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_ulTaskGetIdleRunTimePercent_Unpriv
     MPU_ulTaskGetIdleRunTimePercent_Priv:
-        pop {r0, r1}
         b MPU_ulTaskGetIdleRunTimePercentImpl
     MPU_ulTaskGetIdleRunTimePercent_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent
 /*-----------------------------------------------------------*/
 
@@ -258,12 +244,11 @@ MPU_ulTaskGetIdleRunTimeCounter:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv
     MPU_ulTaskGetIdleRunTimeCounter_Priv:
-        pop {r0, r1}
         b MPU_ulTaskGetIdleRunTimeCounterImpl
     MPU_ulTaskGetIdleRunTimeCounter_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter
 /*-----------------------------------------------------------*/
 
@@ -273,12 +258,11 @@ MPU_vTaskSetApplicationTaskTag:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_vTaskSetApplicationTaskTag_Unpriv
     MPU_vTaskSetApplicationTaskTag_Priv:
-        pop {r0, r1}
         b MPU_vTaskSetApplicationTaskTagImpl
     MPU_vTaskSetApplicationTaskTag_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_vTaskSetApplicationTaskTag
 /*-----------------------------------------------------------*/
 
@@ -288,12 +272,11 @@ MPU_xTaskGetApplicationTaskTag:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTaskGetApplicationTaskTag_Unpriv
     MPU_xTaskGetApplicationTaskTag_Priv:
-        pop {r0, r1}
         b MPU_xTaskGetApplicationTaskTagImpl
     MPU_xTaskGetApplicationTaskTag_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTaskGetApplicationTaskTag
 /*-----------------------------------------------------------*/
 
@@ -303,12 +286,11 @@ MPU_vTaskSetThreadLocalStoragePointer:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv
     MPU_vTaskSetThreadLocalStoragePointer_Priv:
-        pop {r0, r1}
         b MPU_vTaskSetThreadLocalStoragePointerImpl
     MPU_vTaskSetThreadLocalStoragePointer_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer
 /*-----------------------------------------------------------*/
 
@@ -318,12 +300,11 @@ MPU_pvTaskGetThreadLocalStoragePointer:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv
     MPU_pvTaskGetThreadLocalStoragePointer_Priv:
-        pop {r0, r1}
         b MPU_pvTaskGetThreadLocalStoragePointerImpl
     MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer
 /*-----------------------------------------------------------*/
 
@@ -333,12 +314,11 @@ MPU_uxTaskGetSystemState:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_uxTaskGetSystemState_Unpriv
     MPU_uxTaskGetSystemState_Priv:
-        pop {r0, r1}
         b MPU_uxTaskGetSystemStateImpl
     MPU_uxTaskGetSystemState_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_uxTaskGetSystemState
 /*-----------------------------------------------------------*/
 
@@ -348,12 +328,11 @@ MPU_uxTaskGetStackHighWaterMark:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_uxTaskGetStackHighWaterMark_Unpriv
     MPU_uxTaskGetStackHighWaterMark_Priv:
-        pop {r0, r1}
         b MPU_uxTaskGetStackHighWaterMarkImpl
     MPU_uxTaskGetStackHighWaterMark_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark
 /*-----------------------------------------------------------*/
 
@@ -363,12 +342,11 @@ MPU_uxTaskGetStackHighWaterMark2:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_uxTaskGetStackHighWaterMark2_Unpriv
     MPU_uxTaskGetStackHighWaterMark2_Priv:
-        pop {r0, r1}
         b MPU_uxTaskGetStackHighWaterMark2Impl
     MPU_uxTaskGetStackHighWaterMark2_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2
 /*-----------------------------------------------------------*/
 
@@ -378,12 +356,11 @@ MPU_xTaskGetCurrentTaskHandle:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTaskGetCurrentTaskHandle_Unpriv
     MPU_xTaskGetCurrentTaskHandle_Priv:
-        pop {r0, r1}
         b MPU_xTaskGetCurrentTaskHandleImpl
     MPU_xTaskGetCurrentTaskHandle_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle
 /*-----------------------------------------------------------*/
 
@@ -393,12 +370,11 @@ MPU_xTaskGetSchedulerState:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTaskGetSchedulerState_Unpriv
     MPU_xTaskGetSchedulerState_Priv:
-        pop {r0, r1}
         b MPU_xTaskGetSchedulerStateImpl
     MPU_xTaskGetSchedulerState_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTaskGetSchedulerState
 /*-----------------------------------------------------------*/
 
@@ -408,12 +384,11 @@ MPU_vTaskSetTimeOutState:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_vTaskSetTimeOutState_Unpriv
     MPU_vTaskSetTimeOutState_Priv:
-        pop {r0, r1}
         b MPU_vTaskSetTimeOutStateImpl
     MPU_vTaskSetTimeOutState_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_vTaskSetTimeOutState
 /*-----------------------------------------------------------*/
 
@@ -423,12 +398,11 @@ MPU_xTaskCheckForTimeOut:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTaskCheckForTimeOut_Unpriv
     MPU_xTaskCheckForTimeOut_Priv:
-        pop {r0, r1}
         b MPU_xTaskCheckForTimeOutImpl
     MPU_xTaskCheckForTimeOut_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTaskCheckForTimeOut
 /*-----------------------------------------------------------*/
 
@@ -438,12 +412,11 @@ MPU_xTaskGenericNotifyEntry:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTaskGenericNotify_Unpriv
     MPU_xTaskGenericNotify_Priv:
-        pop {r0, r1}
         b MPU_xTaskGenericNotifyImpl
     MPU_xTaskGenericNotify_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTaskGenericNotify
 /*-----------------------------------------------------------*/
 
@@ -453,12 +426,11 @@ MPU_xTaskGenericNotifyWaitEntry:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTaskGenericNotifyWait_Unpriv
     MPU_xTaskGenericNotifyWait_Priv:
-        pop {r0, r1}
         b MPU_xTaskGenericNotifyWaitImpl
     MPU_xTaskGenericNotifyWait_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTaskGenericNotifyWait
 /*-----------------------------------------------------------*/
 
@@ -468,12 +440,11 @@ MPU_ulTaskGenericNotifyTake:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_ulTaskGenericNotifyTake_Unpriv
     MPU_ulTaskGenericNotifyTake_Priv:
-        pop {r0, r1}
         b MPU_ulTaskGenericNotifyTakeImpl
     MPU_ulTaskGenericNotifyTake_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_ulTaskGenericNotifyTake
 /*-----------------------------------------------------------*/
 
@@ -483,12 +454,11 @@ MPU_xTaskGenericNotifyStateClear:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTaskGenericNotifyStateClear_Unpriv
     MPU_xTaskGenericNotifyStateClear_Priv:
-        pop {r0, r1}
         b MPU_xTaskGenericNotifyStateClearImpl
     MPU_xTaskGenericNotifyStateClear_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTaskGenericNotifyStateClear
 /*-----------------------------------------------------------*/
 
@@ -498,12 +468,11 @@ MPU_ulTaskGenericNotifyValueClear:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_ulTaskGenericNotifyValueClear_Unpriv
     MPU_ulTaskGenericNotifyValueClear_Priv:
-        pop {r0, r1}
         b MPU_ulTaskGenericNotifyValueClearImpl
     MPU_ulTaskGenericNotifyValueClear_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear
 /*-----------------------------------------------------------*/
 
@@ -513,12 +482,11 @@ MPU_xQueueGenericSend:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xQueueGenericSend_Unpriv
     MPU_xQueueGenericSend_Priv:
-        pop {r0, r1}
         b MPU_xQueueGenericSendImpl
     MPU_xQueueGenericSend_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xQueueGenericSend
 /*-----------------------------------------------------------*/
 
@@ -528,12 +496,11 @@ MPU_uxQueueMessagesWaiting:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_uxQueueMessagesWaiting_Unpriv
     MPU_uxQueueMessagesWaiting_Priv:
-        pop {r0, r1}
         b MPU_uxQueueMessagesWaitingImpl
     MPU_uxQueueMessagesWaiting_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_uxQueueMessagesWaiting
 /*-----------------------------------------------------------*/
 
@@ -543,12 +510,11 @@ MPU_uxQueueSpacesAvailable:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_uxQueueSpacesAvailable_Unpriv
     MPU_uxQueueSpacesAvailable_Priv:
-        pop {r0, r1}
         b MPU_uxQueueSpacesAvailableImpl
     MPU_uxQueueSpacesAvailable_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_uxQueueSpacesAvailable
 /*-----------------------------------------------------------*/
 
@@ -558,12 +524,11 @@ MPU_xQueueReceive:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xQueueReceive_Unpriv
     MPU_xQueueReceive_Priv:
-        pop {r0, r1}
         b MPU_xQueueReceiveImpl
     MPU_xQueueReceive_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xQueueReceive
 /*-----------------------------------------------------------*/
 
@@ -573,12 +538,11 @@ MPU_xQueuePeek:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xQueuePeek_Unpriv
     MPU_xQueuePeek_Priv:
-        pop {r0, r1}
         b MPU_xQueuePeekImpl
     MPU_xQueuePeek_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xQueuePeek
 /*-----------------------------------------------------------*/
 
@@ -588,12 +552,11 @@ MPU_xQueueSemaphoreTake:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xQueueSemaphoreTake_Unpriv
     MPU_xQueueSemaphoreTake_Priv:
-        pop {r0, r1}
         b MPU_xQueueSemaphoreTakeImpl
     MPU_xQueueSemaphoreTake_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xQueueSemaphoreTake
 /*-----------------------------------------------------------*/
 
@@ -603,12 +566,11 @@ MPU_xQueueGetMutexHolder:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xQueueGetMutexHolder_Unpriv
     MPU_xQueueGetMutexHolder_Priv:
-        pop {r0, r1}
         b MPU_xQueueGetMutexHolderImpl
     MPU_xQueueGetMutexHolder_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xQueueGetMutexHolder
 /*-----------------------------------------------------------*/
 
@@ -618,12 +580,11 @@ MPU_xQueueTakeMutexRecursive:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xQueueTakeMutexRecursive_Unpriv
     MPU_xQueueTakeMutexRecursive_Priv:
-        pop {r0, r1}
         b MPU_xQueueTakeMutexRecursiveImpl
     MPU_xQueueTakeMutexRecursive_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xQueueTakeMutexRecursive
 /*-----------------------------------------------------------*/
 
@@ -633,12 +594,11 @@ MPU_xQueueGiveMutexRecursive:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xQueueGiveMutexRecursive_Unpriv
     MPU_xQueueGiveMutexRecursive_Priv:
-        pop {r0, r1}
         b MPU_xQueueGiveMutexRecursiveImpl
     MPU_xQueueGiveMutexRecursive_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xQueueGiveMutexRecursive
 /*-----------------------------------------------------------*/
 
@@ -648,12 +608,11 @@ MPU_xQueueSelectFromSet:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xQueueSelectFromSet_Unpriv
     MPU_xQueueSelectFromSet_Priv:
-        pop {r0, r1}
         b MPU_xQueueSelectFromSetImpl
     MPU_xQueueSelectFromSet_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xQueueSelectFromSet
 /*-----------------------------------------------------------*/
 
@@ -663,12 +622,11 @@ MPU_xQueueAddToSet:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xQueueAddToSet_Unpriv
     MPU_xQueueAddToSet_Priv:
-        pop {r0, r1}
         b MPU_xQueueAddToSetImpl
     MPU_xQueueAddToSet_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xQueueAddToSet
 /*-----------------------------------------------------------*/
 
@@ -678,12 +636,11 @@ MPU_vQueueAddToRegistry:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_vQueueAddToRegistry_Unpriv
     MPU_vQueueAddToRegistry_Priv:
-        pop {r0, r1}
         b MPU_vQueueAddToRegistryImpl
     MPU_vQueueAddToRegistry_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_vQueueAddToRegistry
 /*-----------------------------------------------------------*/
 
@@ -693,12 +650,11 @@ MPU_vQueueUnregisterQueue:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_vQueueUnregisterQueue_Unpriv
     MPU_vQueueUnregisterQueue_Priv:
-        pop {r0, r1}
         b MPU_vQueueUnregisterQueueImpl
     MPU_vQueueUnregisterQueue_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_vQueueUnregisterQueue
 /*-----------------------------------------------------------*/
 
@@ -708,12 +664,11 @@ MPU_pcQueueGetName:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_pcQueueGetName_Unpriv
     MPU_pcQueueGetName_Priv:
-        pop {r0, r1}
         b MPU_pcQueueGetNameImpl
     MPU_pcQueueGetName_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_pcQueueGetName
 /*-----------------------------------------------------------*/
 
@@ -723,12 +678,11 @@ MPU_pvTimerGetTimerID:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_pvTimerGetTimerID_Unpriv
     MPU_pvTimerGetTimerID_Priv:
-        pop {r0, r1}
         b MPU_pvTimerGetTimerIDImpl
     MPU_pvTimerGetTimerID_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_pvTimerGetTimerID
 /*-----------------------------------------------------------*/
 
@@ -738,12 +692,11 @@ MPU_vTimerSetTimerID:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_vTimerSetTimerID_Unpriv
     MPU_vTimerSetTimerID_Priv:
-        pop {r0, r1}
         b MPU_vTimerSetTimerIDImpl
     MPU_vTimerSetTimerID_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_vTimerSetTimerID
 /*-----------------------------------------------------------*/
 
@@ -753,12 +706,11 @@ MPU_xTimerIsTimerActive:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTimerIsTimerActive_Unpriv
     MPU_xTimerIsTimerActive_Priv:
-        pop {r0, r1}
         b MPU_xTimerIsTimerActiveImpl
     MPU_xTimerIsTimerActive_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTimerIsTimerActive
 /*-----------------------------------------------------------*/
 
@@ -768,12 +720,11 @@ MPU_xTimerGetTimerDaemonTaskHandle:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv
     MPU_xTimerGetTimerDaemonTaskHandle_Priv:
-        pop {r0, r1}
         b MPU_xTimerGetTimerDaemonTaskHandleImpl
     MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle
 /*-----------------------------------------------------------*/
 
@@ -783,12 +734,11 @@ MPU_xTimerGenericCommandFromTaskEntry:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTimerGenericCommandFromTask_Unpriv
     MPU_xTimerGenericCommandFromTask_Priv:
-        pop {r0, r1}
         b MPU_xTimerGenericCommandFromTaskImpl
     MPU_xTimerGenericCommandFromTask_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTimerGenericCommandFromTask
 /*-----------------------------------------------------------*/
 
@@ -798,12 +748,11 @@ MPU_pcTimerGetName:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_pcTimerGetName_Unpriv
     MPU_pcTimerGetName_Priv:
-        pop {r0, r1}
         b MPU_pcTimerGetNameImpl
     MPU_pcTimerGetName_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_pcTimerGetName
 /*-----------------------------------------------------------*/
 
@@ -813,12 +762,11 @@ MPU_vTimerSetReloadMode:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_vTimerSetReloadMode_Unpriv
     MPU_vTimerSetReloadMode_Priv:
-        pop {r0, r1}
         b MPU_vTimerSetReloadModeImpl
     MPU_vTimerSetReloadMode_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_vTimerSetReloadMode
 /*-----------------------------------------------------------*/
 
@@ -828,12 +776,11 @@ MPU_xTimerGetReloadMode:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTimerGetReloadMode_Unpriv
     MPU_xTimerGetReloadMode_Priv:
-        pop {r0, r1}
         b MPU_xTimerGetReloadModeImpl
     MPU_xTimerGetReloadMode_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTimerGetReloadMode
 /*-----------------------------------------------------------*/
 
@@ -843,12 +790,11 @@ MPU_uxTimerGetReloadMode:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_uxTimerGetReloadMode_Unpriv
     MPU_uxTimerGetReloadMode_Priv:
-        pop {r0, r1}
         b MPU_uxTimerGetReloadModeImpl
     MPU_uxTimerGetReloadMode_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_uxTimerGetReloadMode
 /*-----------------------------------------------------------*/
 
@@ -858,12 +804,11 @@ MPU_xTimerGetPeriod:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTimerGetPeriod_Unpriv
     MPU_xTimerGetPeriod_Priv:
-        pop {r0, r1}
         b MPU_xTimerGetPeriodImpl
     MPU_xTimerGetPeriod_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTimerGetPeriod
 /*-----------------------------------------------------------*/
 
@@ -873,12 +818,11 @@ MPU_xTimerGetExpiryTime:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTimerGetExpiryTime_Unpriv
     MPU_xTimerGetExpiryTime_Priv:
-        pop {r0, r1}
         b MPU_xTimerGetExpiryTimeImpl
     MPU_xTimerGetExpiryTime_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTimerGetExpiryTime
 /*-----------------------------------------------------------*/
 
@@ -888,12 +832,11 @@ MPU_xEventGroupWaitBitsEntry:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xEventGroupWaitBits_Unpriv
     MPU_xEventGroupWaitBits_Priv:
-        pop {r0, r1}
         b MPU_xEventGroupWaitBitsImpl
     MPU_xEventGroupWaitBits_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xEventGroupWaitBits
 /*-----------------------------------------------------------*/
 
@@ -903,12 +846,11 @@ MPU_xEventGroupClearBits:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xEventGroupClearBits_Unpriv
     MPU_xEventGroupClearBits_Priv:
-        pop {r0, r1}
         b MPU_xEventGroupClearBitsImpl
     MPU_xEventGroupClearBits_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xEventGroupClearBits
 /*-----------------------------------------------------------*/
 
@@ -918,12 +860,11 @@ MPU_xEventGroupSetBits:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xEventGroupSetBits_Unpriv
     MPU_xEventGroupSetBits_Priv:
-        pop {r0, r1}
         b MPU_xEventGroupSetBitsImpl
     MPU_xEventGroupSetBits_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xEventGroupSetBits
 /*-----------------------------------------------------------*/
 
@@ -933,12 +874,11 @@ MPU_xEventGroupSync:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xEventGroupSync_Unpriv
     MPU_xEventGroupSync_Priv:
-        pop {r0, r1}
         b MPU_xEventGroupSyncImpl
     MPU_xEventGroupSync_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xEventGroupSync
 /*-----------------------------------------------------------*/
 
@@ -948,12 +888,11 @@ MPU_uxEventGroupGetNumber:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_uxEventGroupGetNumber_Unpriv
     MPU_uxEventGroupGetNumber_Priv:
-        pop {r0, r1}
         b MPU_uxEventGroupGetNumberImpl
     MPU_uxEventGroupGetNumber_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_uxEventGroupGetNumber
 /*-----------------------------------------------------------*/
 
@@ -963,12 +902,11 @@ MPU_vEventGroupSetNumber:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_vEventGroupSetNumber_Unpriv
     MPU_vEventGroupSetNumber_Priv:
-        pop {r0, r1}
         b MPU_vEventGroupSetNumberImpl
     MPU_vEventGroupSetNumber_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_vEventGroupSetNumber
 /*-----------------------------------------------------------*/
 
@@ -978,12 +916,11 @@ MPU_xStreamBufferSend:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xStreamBufferSend_Unpriv
     MPU_xStreamBufferSend_Priv:
-        pop {r0, r1}
         b MPU_xStreamBufferSendImpl
     MPU_xStreamBufferSend_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xStreamBufferSend
 /*-----------------------------------------------------------*/
 
@@ -993,12 +930,11 @@ MPU_xStreamBufferReceive:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xStreamBufferReceive_Unpriv
     MPU_xStreamBufferReceive_Priv:
-        pop {r0, r1}
         b MPU_xStreamBufferReceiveImpl
     MPU_xStreamBufferReceive_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xStreamBufferReceive
 /*-----------------------------------------------------------*/
 
@@ -1008,12 +944,11 @@ MPU_xStreamBufferIsFull:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xStreamBufferIsFull_Unpriv
     MPU_xStreamBufferIsFull_Priv:
-        pop {r0, r1}
         b MPU_xStreamBufferIsFullImpl
     MPU_xStreamBufferIsFull_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xStreamBufferIsFull
 /*-----------------------------------------------------------*/
 
@@ -1023,12 +958,11 @@ MPU_xStreamBufferIsEmpty:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xStreamBufferIsEmpty_Unpriv
     MPU_xStreamBufferIsEmpty_Priv:
-        pop {r0, r1}
         b MPU_xStreamBufferIsEmptyImpl
     MPU_xStreamBufferIsEmpty_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xStreamBufferIsEmpty
 /*-----------------------------------------------------------*/
 
@@ -1038,12 +972,11 @@ MPU_xStreamBufferSpacesAvailable:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xStreamBufferSpacesAvailable_Unpriv
     MPU_xStreamBufferSpacesAvailable_Priv:
-        pop {r0, r1}
         b MPU_xStreamBufferSpacesAvailableImpl
     MPU_xStreamBufferSpacesAvailable_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xStreamBufferSpacesAvailable
 /*-----------------------------------------------------------*/
 
@@ -1053,12 +986,11 @@ MPU_xStreamBufferBytesAvailable:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xStreamBufferBytesAvailable_Unpriv
     MPU_xStreamBufferBytesAvailable_Priv:
-        pop {r0, r1}
         b MPU_xStreamBufferBytesAvailableImpl
     MPU_xStreamBufferBytesAvailable_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xStreamBufferBytesAvailable
 /*-----------------------------------------------------------*/
 
@@ -1068,12 +1000,11 @@ MPU_xStreamBufferSetTriggerLevel:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xStreamBufferSetTriggerLevel_Unpriv
     MPU_xStreamBufferSetTriggerLevel_Priv:
-        pop {r0, r1}
         b MPU_xStreamBufferSetTriggerLevelImpl
     MPU_xStreamBufferSetTriggerLevel_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel
 /*-----------------------------------------------------------*/
 
@@ -1083,12 +1014,11 @@ MPU_xStreamBufferNextMessageLengthBytes:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv
     MPU_xStreamBufferNextMessageLengthBytes_Priv:
-        pop {r0, r1}
         b MPU_xStreamBufferNextMessageLengthBytesImpl
     MPU_xStreamBufferNextMessageLengthBytes_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes
 /*-----------------------------------------------------------*/
 
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/mpu_wrappers_v2_asm.S b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/mpu_wrappers_v2_asm.S
index a69845eda..d2cb78e92 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/mpu_wrappers_v2_asm.S
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/mpu_wrappers_v2_asm.S
@@ -47,12 +47,11 @@ MPU_xTaskDelayUntil:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskDelayUntil_Unpriv
     MPU_xTaskDelayUntil_Priv:
-        pop {r0}
         b MPU_xTaskDelayUntilImpl
     MPU_xTaskDelayUntil_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskDelayUntil
 /*-----------------------------------------------------------*/
 
@@ -61,12 +60,11 @@ MPU_xTaskAbortDelay:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskAbortDelay_Unpriv
     MPU_xTaskAbortDelay_Priv:
-        pop {r0}
         b MPU_xTaskAbortDelayImpl
     MPU_xTaskAbortDelay_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskAbortDelay
 /*-----------------------------------------------------------*/
 
@@ -75,12 +73,11 @@ MPU_vTaskDelay:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskDelay_Unpriv
     MPU_vTaskDelay_Priv:
-        pop {r0}
         b MPU_vTaskDelayImpl
     MPU_vTaskDelay_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskDelay
 /*-----------------------------------------------------------*/
 
@@ -89,12 +86,11 @@ MPU_uxTaskPriorityGet:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTaskPriorityGet_Unpriv
     MPU_uxTaskPriorityGet_Priv:
-        pop {r0}
         b MPU_uxTaskPriorityGetImpl
     MPU_uxTaskPriorityGet_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTaskPriorityGet
 /*-----------------------------------------------------------*/
 
@@ -103,12 +99,11 @@ MPU_eTaskGetState:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_eTaskGetState_Unpriv
     MPU_eTaskGetState_Priv:
-        pop {r0}
         b MPU_eTaskGetStateImpl
     MPU_eTaskGetState_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_eTaskGetState
 /*-----------------------------------------------------------*/
 
@@ -117,12 +112,11 @@ MPU_vTaskGetInfo:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskGetInfo_Unpriv
     MPU_vTaskGetInfo_Priv:
-        pop {r0}
         b MPU_vTaskGetInfoImpl
     MPU_vTaskGetInfo_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskGetInfo
 /*-----------------------------------------------------------*/
 
@@ -131,12 +125,11 @@ MPU_xTaskGetIdleTaskHandle:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGetIdleTaskHandle_Unpriv
     MPU_xTaskGetIdleTaskHandle_Priv:
-        pop {r0}
         b MPU_xTaskGetIdleTaskHandleImpl
     MPU_xTaskGetIdleTaskHandle_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGetIdleTaskHandle
 /*-----------------------------------------------------------*/
 
@@ -145,12 +138,11 @@ MPU_vTaskSuspend:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskSuspend_Unpriv
     MPU_vTaskSuspend_Priv:
-        pop {r0}
         b MPU_vTaskSuspendImpl
     MPU_vTaskSuspend_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskSuspend
 /*-----------------------------------------------------------*/
 
@@ -159,12 +151,11 @@ MPU_vTaskResume:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskResume_Unpriv
     MPU_vTaskResume_Priv:
-        pop {r0}
         b MPU_vTaskResumeImpl
     MPU_vTaskResume_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskResume
 /*-----------------------------------------------------------*/
 
@@ -173,12 +164,11 @@ MPU_xTaskGetTickCount:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGetTickCount_Unpriv
     MPU_xTaskGetTickCount_Priv:
-        pop {r0}
         b MPU_xTaskGetTickCountImpl
     MPU_xTaskGetTickCount_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGetTickCount
 /*-----------------------------------------------------------*/
 
@@ -187,12 +177,11 @@ MPU_uxTaskGetNumberOfTasks:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTaskGetNumberOfTasks_Unpriv
     MPU_uxTaskGetNumberOfTasks_Priv:
-        pop {r0}
         b MPU_uxTaskGetNumberOfTasksImpl
     MPU_uxTaskGetNumberOfTasks_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTaskGetNumberOfTasks
 /*-----------------------------------------------------------*/
 
@@ -201,12 +190,11 @@ MPU_ulTaskGetRunTimeCounter:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGetRunTimeCounter_Unpriv
     MPU_ulTaskGetRunTimeCounter_Priv:
-        pop {r0}
         b MPU_ulTaskGetRunTimeCounterImpl
     MPU_ulTaskGetRunTimeCounter_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGetRunTimeCounter
 /*-----------------------------------------------------------*/
 
@@ -215,12 +203,11 @@ MPU_ulTaskGetRunTimePercent:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGetRunTimePercent_Unpriv
     MPU_ulTaskGetRunTimePercent_Priv:
-        pop {r0}
         b MPU_ulTaskGetRunTimePercentImpl
     MPU_ulTaskGetRunTimePercent_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGetRunTimePercent
 /*-----------------------------------------------------------*/
 
@@ -229,12 +216,11 @@ MPU_ulTaskGetIdleRunTimePercent:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGetIdleRunTimePercent_Unpriv
     MPU_ulTaskGetIdleRunTimePercent_Priv:
-        pop {r0}
         b MPU_ulTaskGetIdleRunTimePercentImpl
     MPU_ulTaskGetIdleRunTimePercent_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent
 /*-----------------------------------------------------------*/
 
@@ -243,12 +229,11 @@ MPU_ulTaskGetIdleRunTimeCounter:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv
     MPU_ulTaskGetIdleRunTimeCounter_Priv:
-        pop {r0}
         b MPU_ulTaskGetIdleRunTimeCounterImpl
     MPU_ulTaskGetIdleRunTimeCounter_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter
 /*-----------------------------------------------------------*/
 
@@ -257,12 +242,11 @@ MPU_vTaskSetApplicationTaskTag:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskSetApplicationTaskTag_Unpriv
     MPU_vTaskSetApplicationTaskTag_Priv:
-        pop {r0}
         b MPU_vTaskSetApplicationTaskTagImpl
     MPU_vTaskSetApplicationTaskTag_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskSetApplicationTaskTag
 /*-----------------------------------------------------------*/
 
@@ -271,12 +255,11 @@ MPU_xTaskGetApplicationTaskTag:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGetApplicationTaskTag_Unpriv
     MPU_xTaskGetApplicationTaskTag_Priv:
-        pop {r0}
         b MPU_xTaskGetApplicationTaskTagImpl
     MPU_xTaskGetApplicationTaskTag_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGetApplicationTaskTag
 /*-----------------------------------------------------------*/
 
@@ -285,12 +268,11 @@ MPU_vTaskSetThreadLocalStoragePointer:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv
     MPU_vTaskSetThreadLocalStoragePointer_Priv:
-        pop {r0}
         b MPU_vTaskSetThreadLocalStoragePointerImpl
     MPU_vTaskSetThreadLocalStoragePointer_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer
 /*-----------------------------------------------------------*/
 
@@ -299,12 +281,11 @@ MPU_pvTaskGetThreadLocalStoragePointer:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv
     MPU_pvTaskGetThreadLocalStoragePointer_Priv:
-        pop {r0}
         b MPU_pvTaskGetThreadLocalStoragePointerImpl
     MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer
 /*-----------------------------------------------------------*/
 
@@ -313,12 +294,11 @@ MPU_uxTaskGetSystemState:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTaskGetSystemState_Unpriv
     MPU_uxTaskGetSystemState_Priv:
-        pop {r0}
         b MPU_uxTaskGetSystemStateImpl
     MPU_uxTaskGetSystemState_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTaskGetSystemState
 /*-----------------------------------------------------------*/
 
@@ -327,12 +307,11 @@ MPU_uxTaskGetStackHighWaterMark:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTaskGetStackHighWaterMark_Unpriv
     MPU_uxTaskGetStackHighWaterMark_Priv:
-        pop {r0}
         b MPU_uxTaskGetStackHighWaterMarkImpl
     MPU_uxTaskGetStackHighWaterMark_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark
 /*-----------------------------------------------------------*/
 
@@ -341,12 +320,11 @@ MPU_uxTaskGetStackHighWaterMark2:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTaskGetStackHighWaterMark2_Unpriv
     MPU_uxTaskGetStackHighWaterMark2_Priv:
-        pop {r0}
         b MPU_uxTaskGetStackHighWaterMark2Impl
     MPU_uxTaskGetStackHighWaterMark2_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2
 /*-----------------------------------------------------------*/
 
@@ -355,12 +333,11 @@ MPU_xTaskGetCurrentTaskHandle:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGetCurrentTaskHandle_Unpriv
     MPU_xTaskGetCurrentTaskHandle_Priv:
-        pop {r0}
         b MPU_xTaskGetCurrentTaskHandleImpl
     MPU_xTaskGetCurrentTaskHandle_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle
 /*-----------------------------------------------------------*/
 
@@ -369,12 +346,11 @@ MPU_xTaskGetSchedulerState:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGetSchedulerState_Unpriv
     MPU_xTaskGetSchedulerState_Priv:
-        pop {r0}
         b MPU_xTaskGetSchedulerStateImpl
     MPU_xTaskGetSchedulerState_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGetSchedulerState
 /*-----------------------------------------------------------*/
 
@@ -383,12 +359,11 @@ MPU_vTaskSetTimeOutState:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskSetTimeOutState_Unpriv
     MPU_vTaskSetTimeOutState_Priv:
-        pop {r0}
         b MPU_vTaskSetTimeOutStateImpl
     MPU_vTaskSetTimeOutState_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskSetTimeOutState
 /*-----------------------------------------------------------*/
 
@@ -397,12 +372,11 @@ MPU_xTaskCheckForTimeOut:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskCheckForTimeOut_Unpriv
     MPU_xTaskCheckForTimeOut_Priv:
-        pop {r0}
         b MPU_xTaskCheckForTimeOutImpl
     MPU_xTaskCheckForTimeOut_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskCheckForTimeOut
 /*-----------------------------------------------------------*/
 
@@ -411,12 +385,11 @@ MPU_xTaskGenericNotifyEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGenericNotify_Unpriv
     MPU_xTaskGenericNotify_Priv:
-        pop {r0}
         b MPU_xTaskGenericNotifyImpl
     MPU_xTaskGenericNotify_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGenericNotify
 /*-----------------------------------------------------------*/
 
@@ -425,12 +398,11 @@ MPU_xTaskGenericNotifyWaitEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGenericNotifyWait_Unpriv
     MPU_xTaskGenericNotifyWait_Priv:
-        pop {r0}
         b MPU_xTaskGenericNotifyWaitImpl
     MPU_xTaskGenericNotifyWait_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGenericNotifyWait
 /*-----------------------------------------------------------*/
 
@@ -439,12 +411,11 @@ MPU_ulTaskGenericNotifyTake:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGenericNotifyTake_Unpriv
     MPU_ulTaskGenericNotifyTake_Priv:
-        pop {r0}
         b MPU_ulTaskGenericNotifyTakeImpl
     MPU_ulTaskGenericNotifyTake_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGenericNotifyTake
 /*-----------------------------------------------------------*/
 
@@ -453,12 +424,11 @@ MPU_xTaskGenericNotifyStateClear:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGenericNotifyStateClear_Unpriv
     MPU_xTaskGenericNotifyStateClear_Priv:
-        pop {r0}
         b MPU_xTaskGenericNotifyStateClearImpl
     MPU_xTaskGenericNotifyStateClear_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGenericNotifyStateClear
 /*-----------------------------------------------------------*/
 
@@ -467,12 +437,11 @@ MPU_ulTaskGenericNotifyValueClear:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGenericNotifyValueClear_Unpriv
     MPU_ulTaskGenericNotifyValueClear_Priv:
-        pop {r0}
         b MPU_ulTaskGenericNotifyValueClearImpl
     MPU_ulTaskGenericNotifyValueClear_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear
 /*-----------------------------------------------------------*/
 
@@ -481,12 +450,11 @@ MPU_xQueueGenericSend:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueGenericSend_Unpriv
     MPU_xQueueGenericSend_Priv:
-        pop {r0}
         b MPU_xQueueGenericSendImpl
     MPU_xQueueGenericSend_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueGenericSend
 /*-----------------------------------------------------------*/
 
@@ -495,12 +463,11 @@ MPU_uxQueueMessagesWaiting:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxQueueMessagesWaiting_Unpriv
     MPU_uxQueueMessagesWaiting_Priv:
-        pop {r0}
         b MPU_uxQueueMessagesWaitingImpl
     MPU_uxQueueMessagesWaiting_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxQueueMessagesWaiting
 /*-----------------------------------------------------------*/
 
@@ -509,12 +476,11 @@ MPU_uxQueueSpacesAvailable:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxQueueSpacesAvailable_Unpriv
     MPU_uxQueueSpacesAvailable_Priv:
-        pop {r0}
         b MPU_uxQueueSpacesAvailableImpl
     MPU_uxQueueSpacesAvailable_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxQueueSpacesAvailable
 /*-----------------------------------------------------------*/
 
@@ -523,12 +489,11 @@ MPU_xQueueReceive:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueReceive_Unpriv
     MPU_xQueueReceive_Priv:
-        pop {r0}
         b MPU_xQueueReceiveImpl
     MPU_xQueueReceive_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueReceive
 /*-----------------------------------------------------------*/
 
@@ -537,12 +502,11 @@ MPU_xQueuePeek:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueuePeek_Unpriv
     MPU_xQueuePeek_Priv:
-        pop {r0}
         b MPU_xQueuePeekImpl
     MPU_xQueuePeek_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueuePeek
 /*-----------------------------------------------------------*/
 
@@ -551,12 +515,11 @@ MPU_xQueueSemaphoreTake:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueSemaphoreTake_Unpriv
     MPU_xQueueSemaphoreTake_Priv:
-        pop {r0}
         b MPU_xQueueSemaphoreTakeImpl
     MPU_xQueueSemaphoreTake_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueSemaphoreTake
 /*-----------------------------------------------------------*/
 
@@ -565,12 +528,11 @@ MPU_xQueueGetMutexHolder:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueGetMutexHolder_Unpriv
     MPU_xQueueGetMutexHolder_Priv:
-        pop {r0}
         b MPU_xQueueGetMutexHolderImpl
     MPU_xQueueGetMutexHolder_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueGetMutexHolder
 /*-----------------------------------------------------------*/
 
@@ -579,12 +541,11 @@ MPU_xQueueTakeMutexRecursive:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueTakeMutexRecursive_Unpriv
     MPU_xQueueTakeMutexRecursive_Priv:
-        pop {r0}
         b MPU_xQueueTakeMutexRecursiveImpl
     MPU_xQueueTakeMutexRecursive_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueTakeMutexRecursive
 /*-----------------------------------------------------------*/
 
@@ -593,12 +554,11 @@ MPU_xQueueGiveMutexRecursive:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueGiveMutexRecursive_Unpriv
     MPU_xQueueGiveMutexRecursive_Priv:
-        pop {r0}
         b MPU_xQueueGiveMutexRecursiveImpl
     MPU_xQueueGiveMutexRecursive_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueGiveMutexRecursive
 /*-----------------------------------------------------------*/
 
@@ -607,12 +567,11 @@ MPU_xQueueSelectFromSet:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueSelectFromSet_Unpriv
     MPU_xQueueSelectFromSet_Priv:
-        pop {r0}
         b MPU_xQueueSelectFromSetImpl
     MPU_xQueueSelectFromSet_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueSelectFromSet
 /*-----------------------------------------------------------*/
 
@@ -621,12 +580,11 @@ MPU_xQueueAddToSet:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueAddToSet_Unpriv
     MPU_xQueueAddToSet_Priv:
-        pop {r0}
         b MPU_xQueueAddToSetImpl
     MPU_xQueueAddToSet_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueAddToSet
 /*-----------------------------------------------------------*/
 
@@ -635,12 +593,11 @@ MPU_vQueueAddToRegistry:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vQueueAddToRegistry_Unpriv
     MPU_vQueueAddToRegistry_Priv:
-        pop {r0}
         b MPU_vQueueAddToRegistryImpl
     MPU_vQueueAddToRegistry_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vQueueAddToRegistry
 /*-----------------------------------------------------------*/
 
@@ -649,12 +606,11 @@ MPU_vQueueUnregisterQueue:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vQueueUnregisterQueue_Unpriv
     MPU_vQueueUnregisterQueue_Priv:
-        pop {r0}
         b MPU_vQueueUnregisterQueueImpl
     MPU_vQueueUnregisterQueue_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vQueueUnregisterQueue
 /*-----------------------------------------------------------*/
 
@@ -663,12 +619,11 @@ MPU_pcQueueGetName:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_pcQueueGetName_Unpriv
     MPU_pcQueueGetName_Priv:
-        pop {r0}
         b MPU_pcQueueGetNameImpl
     MPU_pcQueueGetName_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_pcQueueGetName
 /*-----------------------------------------------------------*/
 
@@ -677,12 +632,11 @@ MPU_pvTimerGetTimerID:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_pvTimerGetTimerID_Unpriv
     MPU_pvTimerGetTimerID_Priv:
-        pop {r0}
         b MPU_pvTimerGetTimerIDImpl
     MPU_pvTimerGetTimerID_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_pvTimerGetTimerID
 /*-----------------------------------------------------------*/
 
@@ -691,12 +645,11 @@ MPU_vTimerSetTimerID:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTimerSetTimerID_Unpriv
     MPU_vTimerSetTimerID_Priv:
-        pop {r0}
         b MPU_vTimerSetTimerIDImpl
     MPU_vTimerSetTimerID_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTimerSetTimerID
 /*-----------------------------------------------------------*/
 
@@ -705,12 +658,11 @@ MPU_xTimerIsTimerActive:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerIsTimerActive_Unpriv
     MPU_xTimerIsTimerActive_Priv:
-        pop {r0}
         b MPU_xTimerIsTimerActiveImpl
     MPU_xTimerIsTimerActive_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerIsTimerActive
 /*-----------------------------------------------------------*/
 
@@ -719,12 +671,11 @@ MPU_xTimerGetTimerDaemonTaskHandle:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv
     MPU_xTimerGetTimerDaemonTaskHandle_Priv:
-        pop {r0}
         b MPU_xTimerGetTimerDaemonTaskHandleImpl
     MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle
 /*-----------------------------------------------------------*/
 
@@ -733,12 +684,11 @@ MPU_xTimerGenericCommandFromTaskEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerGenericCommandFromTask_Unpriv
     MPU_xTimerGenericCommandFromTask_Priv:
-        pop {r0}
         b MPU_xTimerGenericCommandFromTaskImpl
     MPU_xTimerGenericCommandFromTask_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerGenericCommandFromTask
 /*-----------------------------------------------------------*/
 
@@ -747,12 +697,11 @@ MPU_pcTimerGetName:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_pcTimerGetName_Unpriv
     MPU_pcTimerGetName_Priv:
-        pop {r0}
         b MPU_pcTimerGetNameImpl
     MPU_pcTimerGetName_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_pcTimerGetName
 /*-----------------------------------------------------------*/
 
@@ -761,12 +710,11 @@ MPU_vTimerSetReloadMode:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTimerSetReloadMode_Unpriv
     MPU_vTimerSetReloadMode_Priv:
-        pop {r0}
         b MPU_vTimerSetReloadModeImpl
     MPU_vTimerSetReloadMode_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTimerSetReloadMode
 /*-----------------------------------------------------------*/
 
@@ -775,12 +723,11 @@ MPU_xTimerGetReloadMode:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerGetReloadMode_Unpriv
     MPU_xTimerGetReloadMode_Priv:
-        pop {r0}
         b MPU_xTimerGetReloadModeImpl
     MPU_xTimerGetReloadMode_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerGetReloadMode
 /*-----------------------------------------------------------*/
 
@@ -789,12 +736,11 @@ MPU_uxTimerGetReloadMode:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTimerGetReloadMode_Unpriv
     MPU_uxTimerGetReloadMode_Priv:
-        pop {r0}
         b MPU_uxTimerGetReloadModeImpl
     MPU_uxTimerGetReloadMode_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTimerGetReloadMode
 /*-----------------------------------------------------------*/
 
@@ -803,12 +749,11 @@ MPU_xTimerGetPeriod:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerGetPeriod_Unpriv
     MPU_xTimerGetPeriod_Priv:
-        pop {r0}
         b MPU_xTimerGetPeriodImpl
     MPU_xTimerGetPeriod_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerGetPeriod
 /*-----------------------------------------------------------*/
 
@@ -817,12 +762,11 @@ MPU_xTimerGetExpiryTime:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerGetExpiryTime_Unpriv
     MPU_xTimerGetExpiryTime_Priv:
-        pop {r0}
         b MPU_xTimerGetExpiryTimeImpl
     MPU_xTimerGetExpiryTime_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerGetExpiryTime
 /*-----------------------------------------------------------*/
 
@@ -831,12 +775,11 @@ MPU_xEventGroupWaitBitsEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xEventGroupWaitBits_Unpriv
     MPU_xEventGroupWaitBits_Priv:
-        pop {r0}
         b MPU_xEventGroupWaitBitsImpl
     MPU_xEventGroupWaitBits_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xEventGroupWaitBits
 /*-----------------------------------------------------------*/
 
@@ -845,12 +788,11 @@ MPU_xEventGroupClearBits:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xEventGroupClearBits_Unpriv
     MPU_xEventGroupClearBits_Priv:
-        pop {r0}
         b MPU_xEventGroupClearBitsImpl
     MPU_xEventGroupClearBits_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xEventGroupClearBits
 /*-----------------------------------------------------------*/
 
@@ -859,12 +801,11 @@ MPU_xEventGroupSetBits:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xEventGroupSetBits_Unpriv
     MPU_xEventGroupSetBits_Priv:
-        pop {r0}
         b MPU_xEventGroupSetBitsImpl
     MPU_xEventGroupSetBits_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xEventGroupSetBits
 /*-----------------------------------------------------------*/
 
@@ -873,12 +814,11 @@ MPU_xEventGroupSync:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xEventGroupSync_Unpriv
     MPU_xEventGroupSync_Priv:
-        pop {r0}
         b MPU_xEventGroupSyncImpl
     MPU_xEventGroupSync_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xEventGroupSync
 /*-----------------------------------------------------------*/
 
@@ -887,12 +827,11 @@ MPU_uxEventGroupGetNumber:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxEventGroupGetNumber_Unpriv
     MPU_uxEventGroupGetNumber_Priv:
-        pop {r0}
         b MPU_uxEventGroupGetNumberImpl
     MPU_uxEventGroupGetNumber_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxEventGroupGetNumber
 /*-----------------------------------------------------------*/
 
@@ -901,12 +840,11 @@ MPU_vEventGroupSetNumber:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vEventGroupSetNumber_Unpriv
     MPU_vEventGroupSetNumber_Priv:
-        pop {r0}
         b MPU_vEventGroupSetNumberImpl
     MPU_vEventGroupSetNumber_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vEventGroupSetNumber
 /*-----------------------------------------------------------*/
 
@@ -915,12 +853,11 @@ MPU_xStreamBufferSend:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferSend_Unpriv
     MPU_xStreamBufferSend_Priv:
-        pop {r0}
         b MPU_xStreamBufferSendImpl
     MPU_xStreamBufferSend_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferSend
 /*-----------------------------------------------------------*/
 
@@ -929,12 +866,11 @@ MPU_xStreamBufferReceive:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferReceive_Unpriv
     MPU_xStreamBufferReceive_Priv:
-        pop {r0}
         b MPU_xStreamBufferReceiveImpl
     MPU_xStreamBufferReceive_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferReceive
 /*-----------------------------------------------------------*/
 
@@ -943,12 +879,11 @@ MPU_xStreamBufferIsFull:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferIsFull_Unpriv
     MPU_xStreamBufferIsFull_Priv:
-        pop {r0}
         b MPU_xStreamBufferIsFullImpl
     MPU_xStreamBufferIsFull_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferIsFull
 /*-----------------------------------------------------------*/
 
@@ -957,12 +892,11 @@ MPU_xStreamBufferIsEmpty:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferIsEmpty_Unpriv
     MPU_xStreamBufferIsEmpty_Priv:
-        pop {r0}
         b MPU_xStreamBufferIsEmptyImpl
     MPU_xStreamBufferIsEmpty_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferIsEmpty
 /*-----------------------------------------------------------*/
 
@@ -971,12 +905,11 @@ MPU_xStreamBufferSpacesAvailable:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferSpacesAvailable_Unpriv
     MPU_xStreamBufferSpacesAvailable_Priv:
-        pop {r0}
         b MPU_xStreamBufferSpacesAvailableImpl
     MPU_xStreamBufferSpacesAvailable_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferSpacesAvailable
 /*-----------------------------------------------------------*/
 
@@ -985,12 +918,11 @@ MPU_xStreamBufferBytesAvailable:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferBytesAvailable_Unpriv
     MPU_xStreamBufferBytesAvailable_Priv:
-        pop {r0}
         b MPU_xStreamBufferBytesAvailableImpl
     MPU_xStreamBufferBytesAvailable_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferBytesAvailable
 /*-----------------------------------------------------------*/
 
@@ -999,12 +931,11 @@ MPU_xStreamBufferSetTriggerLevel:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferSetTriggerLevel_Unpriv
     MPU_xStreamBufferSetTriggerLevel_Priv:
-        pop {r0}
         b MPU_xStreamBufferSetTriggerLevelImpl
     MPU_xStreamBufferSetTriggerLevel_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel
 /*-----------------------------------------------------------*/
 
@@ -1013,12 +944,11 @@ MPU_xStreamBufferNextMessageLengthBytes:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv
     MPU_xStreamBufferNextMessageLengthBytes_Priv:
-        pop {r0}
         b MPU_xStreamBufferNextMessageLengthBytesImpl
     MPU_xStreamBufferNextMessageLengthBytes_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes
 /*-----------------------------------------------------------*/
 
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/mpu_wrappers_v2_asm.S b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/mpu_wrappers_v2_asm.S
index a69845eda..d2cb78e92 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/mpu_wrappers_v2_asm.S
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/mpu_wrappers_v2_asm.S
@@ -47,12 +47,11 @@ MPU_xTaskDelayUntil:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskDelayUntil_Unpriv
     MPU_xTaskDelayUntil_Priv:
-        pop {r0}
         b MPU_xTaskDelayUntilImpl
     MPU_xTaskDelayUntil_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskDelayUntil
 /*-----------------------------------------------------------*/
 
@@ -61,12 +60,11 @@ MPU_xTaskAbortDelay:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskAbortDelay_Unpriv
     MPU_xTaskAbortDelay_Priv:
-        pop {r0}
         b MPU_xTaskAbortDelayImpl
     MPU_xTaskAbortDelay_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskAbortDelay
 /*-----------------------------------------------------------*/
 
@@ -75,12 +73,11 @@ MPU_vTaskDelay:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskDelay_Unpriv
     MPU_vTaskDelay_Priv:
-        pop {r0}
         b MPU_vTaskDelayImpl
     MPU_vTaskDelay_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskDelay
 /*-----------------------------------------------------------*/
 
@@ -89,12 +86,11 @@ MPU_uxTaskPriorityGet:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTaskPriorityGet_Unpriv
     MPU_uxTaskPriorityGet_Priv:
-        pop {r0}
         b MPU_uxTaskPriorityGetImpl
     MPU_uxTaskPriorityGet_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTaskPriorityGet
 /*-----------------------------------------------------------*/
 
@@ -103,12 +99,11 @@ MPU_eTaskGetState:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_eTaskGetState_Unpriv
     MPU_eTaskGetState_Priv:
-        pop {r0}
         b MPU_eTaskGetStateImpl
     MPU_eTaskGetState_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_eTaskGetState
 /*-----------------------------------------------------------*/
 
@@ -117,12 +112,11 @@ MPU_vTaskGetInfo:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskGetInfo_Unpriv
     MPU_vTaskGetInfo_Priv:
-        pop {r0}
         b MPU_vTaskGetInfoImpl
     MPU_vTaskGetInfo_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskGetInfo
 /*-----------------------------------------------------------*/
 
@@ -131,12 +125,11 @@ MPU_xTaskGetIdleTaskHandle:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGetIdleTaskHandle_Unpriv
     MPU_xTaskGetIdleTaskHandle_Priv:
-        pop {r0}
         b MPU_xTaskGetIdleTaskHandleImpl
     MPU_xTaskGetIdleTaskHandle_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGetIdleTaskHandle
 /*-----------------------------------------------------------*/
 
@@ -145,12 +138,11 @@ MPU_vTaskSuspend:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskSuspend_Unpriv
     MPU_vTaskSuspend_Priv:
-        pop {r0}
         b MPU_vTaskSuspendImpl
     MPU_vTaskSuspend_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskSuspend
 /*-----------------------------------------------------------*/
 
@@ -159,12 +151,11 @@ MPU_vTaskResume:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskResume_Unpriv
     MPU_vTaskResume_Priv:
-        pop {r0}
         b MPU_vTaskResumeImpl
     MPU_vTaskResume_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskResume
 /*-----------------------------------------------------------*/
 
@@ -173,12 +164,11 @@ MPU_xTaskGetTickCount:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGetTickCount_Unpriv
     MPU_xTaskGetTickCount_Priv:
-        pop {r0}
         b MPU_xTaskGetTickCountImpl
     MPU_xTaskGetTickCount_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGetTickCount
 /*-----------------------------------------------------------*/
 
@@ -187,12 +177,11 @@ MPU_uxTaskGetNumberOfTasks:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTaskGetNumberOfTasks_Unpriv
     MPU_uxTaskGetNumberOfTasks_Priv:
-        pop {r0}
         b MPU_uxTaskGetNumberOfTasksImpl
     MPU_uxTaskGetNumberOfTasks_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTaskGetNumberOfTasks
 /*-----------------------------------------------------------*/
 
@@ -201,12 +190,11 @@ MPU_ulTaskGetRunTimeCounter:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGetRunTimeCounter_Unpriv
     MPU_ulTaskGetRunTimeCounter_Priv:
-        pop {r0}
         b MPU_ulTaskGetRunTimeCounterImpl
     MPU_ulTaskGetRunTimeCounter_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGetRunTimeCounter
 /*-----------------------------------------------------------*/
 
@@ -215,12 +203,11 @@ MPU_ulTaskGetRunTimePercent:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGetRunTimePercent_Unpriv
     MPU_ulTaskGetRunTimePercent_Priv:
-        pop {r0}
         b MPU_ulTaskGetRunTimePercentImpl
     MPU_ulTaskGetRunTimePercent_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGetRunTimePercent
 /*-----------------------------------------------------------*/
 
@@ -229,12 +216,11 @@ MPU_ulTaskGetIdleRunTimePercent:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGetIdleRunTimePercent_Unpriv
     MPU_ulTaskGetIdleRunTimePercent_Priv:
-        pop {r0}
         b MPU_ulTaskGetIdleRunTimePercentImpl
     MPU_ulTaskGetIdleRunTimePercent_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent
 /*-----------------------------------------------------------*/
 
@@ -243,12 +229,11 @@ MPU_ulTaskGetIdleRunTimeCounter:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv
     MPU_ulTaskGetIdleRunTimeCounter_Priv:
-        pop {r0}
         b MPU_ulTaskGetIdleRunTimeCounterImpl
     MPU_ulTaskGetIdleRunTimeCounter_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter
 /*-----------------------------------------------------------*/
 
@@ -257,12 +242,11 @@ MPU_vTaskSetApplicationTaskTag:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskSetApplicationTaskTag_Unpriv
     MPU_vTaskSetApplicationTaskTag_Priv:
-        pop {r0}
         b MPU_vTaskSetApplicationTaskTagImpl
     MPU_vTaskSetApplicationTaskTag_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskSetApplicationTaskTag
 /*-----------------------------------------------------------*/
 
@@ -271,12 +255,11 @@ MPU_xTaskGetApplicationTaskTag:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGetApplicationTaskTag_Unpriv
     MPU_xTaskGetApplicationTaskTag_Priv:
-        pop {r0}
         b MPU_xTaskGetApplicationTaskTagImpl
     MPU_xTaskGetApplicationTaskTag_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGetApplicationTaskTag
 /*-----------------------------------------------------------*/
 
@@ -285,12 +268,11 @@ MPU_vTaskSetThreadLocalStoragePointer:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv
     MPU_vTaskSetThreadLocalStoragePointer_Priv:
-        pop {r0}
         b MPU_vTaskSetThreadLocalStoragePointerImpl
     MPU_vTaskSetThreadLocalStoragePointer_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer
 /*-----------------------------------------------------------*/
 
@@ -299,12 +281,11 @@ MPU_pvTaskGetThreadLocalStoragePointer:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv
     MPU_pvTaskGetThreadLocalStoragePointer_Priv:
-        pop {r0}
         b MPU_pvTaskGetThreadLocalStoragePointerImpl
     MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer
 /*-----------------------------------------------------------*/
 
@@ -313,12 +294,11 @@ MPU_uxTaskGetSystemState:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTaskGetSystemState_Unpriv
     MPU_uxTaskGetSystemState_Priv:
-        pop {r0}
         b MPU_uxTaskGetSystemStateImpl
     MPU_uxTaskGetSystemState_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTaskGetSystemState
 /*-----------------------------------------------------------*/
 
@@ -327,12 +307,11 @@ MPU_uxTaskGetStackHighWaterMark:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTaskGetStackHighWaterMark_Unpriv
     MPU_uxTaskGetStackHighWaterMark_Priv:
-        pop {r0}
         b MPU_uxTaskGetStackHighWaterMarkImpl
     MPU_uxTaskGetStackHighWaterMark_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark
 /*-----------------------------------------------------------*/
 
@@ -341,12 +320,11 @@ MPU_uxTaskGetStackHighWaterMark2:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTaskGetStackHighWaterMark2_Unpriv
     MPU_uxTaskGetStackHighWaterMark2_Priv:
-        pop {r0}
         b MPU_uxTaskGetStackHighWaterMark2Impl
     MPU_uxTaskGetStackHighWaterMark2_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2
 /*-----------------------------------------------------------*/
 
@@ -355,12 +333,11 @@ MPU_xTaskGetCurrentTaskHandle:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGetCurrentTaskHandle_Unpriv
     MPU_xTaskGetCurrentTaskHandle_Priv:
-        pop {r0}
         b MPU_xTaskGetCurrentTaskHandleImpl
     MPU_xTaskGetCurrentTaskHandle_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle
 /*-----------------------------------------------------------*/
 
@@ -369,12 +346,11 @@ MPU_xTaskGetSchedulerState:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGetSchedulerState_Unpriv
     MPU_xTaskGetSchedulerState_Priv:
-        pop {r0}
         b MPU_xTaskGetSchedulerStateImpl
     MPU_xTaskGetSchedulerState_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGetSchedulerState
 /*-----------------------------------------------------------*/
 
@@ -383,12 +359,11 @@ MPU_vTaskSetTimeOutState:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskSetTimeOutState_Unpriv
     MPU_vTaskSetTimeOutState_Priv:
-        pop {r0}
         b MPU_vTaskSetTimeOutStateImpl
     MPU_vTaskSetTimeOutState_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskSetTimeOutState
 /*-----------------------------------------------------------*/
 
@@ -397,12 +372,11 @@ MPU_xTaskCheckForTimeOut:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskCheckForTimeOut_Unpriv
     MPU_xTaskCheckForTimeOut_Priv:
-        pop {r0}
         b MPU_xTaskCheckForTimeOutImpl
     MPU_xTaskCheckForTimeOut_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskCheckForTimeOut
 /*-----------------------------------------------------------*/
 
@@ -411,12 +385,11 @@ MPU_xTaskGenericNotifyEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGenericNotify_Unpriv
     MPU_xTaskGenericNotify_Priv:
-        pop {r0}
         b MPU_xTaskGenericNotifyImpl
     MPU_xTaskGenericNotify_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGenericNotify
 /*-----------------------------------------------------------*/
 
@@ -425,12 +398,11 @@ MPU_xTaskGenericNotifyWaitEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGenericNotifyWait_Unpriv
     MPU_xTaskGenericNotifyWait_Priv:
-        pop {r0}
         b MPU_xTaskGenericNotifyWaitImpl
     MPU_xTaskGenericNotifyWait_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGenericNotifyWait
 /*-----------------------------------------------------------*/
 
@@ -439,12 +411,11 @@ MPU_ulTaskGenericNotifyTake:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGenericNotifyTake_Unpriv
     MPU_ulTaskGenericNotifyTake_Priv:
-        pop {r0}
         b MPU_ulTaskGenericNotifyTakeImpl
     MPU_ulTaskGenericNotifyTake_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGenericNotifyTake
 /*-----------------------------------------------------------*/
 
@@ -453,12 +424,11 @@ MPU_xTaskGenericNotifyStateClear:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGenericNotifyStateClear_Unpriv
     MPU_xTaskGenericNotifyStateClear_Priv:
-        pop {r0}
         b MPU_xTaskGenericNotifyStateClearImpl
     MPU_xTaskGenericNotifyStateClear_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGenericNotifyStateClear
 /*-----------------------------------------------------------*/
 
@@ -467,12 +437,11 @@ MPU_ulTaskGenericNotifyValueClear:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGenericNotifyValueClear_Unpriv
     MPU_ulTaskGenericNotifyValueClear_Priv:
-        pop {r0}
         b MPU_ulTaskGenericNotifyValueClearImpl
     MPU_ulTaskGenericNotifyValueClear_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear
 /*-----------------------------------------------------------*/
 
@@ -481,12 +450,11 @@ MPU_xQueueGenericSend:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueGenericSend_Unpriv
     MPU_xQueueGenericSend_Priv:
-        pop {r0}
         b MPU_xQueueGenericSendImpl
     MPU_xQueueGenericSend_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueGenericSend
 /*-----------------------------------------------------------*/
 
@@ -495,12 +463,11 @@ MPU_uxQueueMessagesWaiting:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxQueueMessagesWaiting_Unpriv
     MPU_uxQueueMessagesWaiting_Priv:
-        pop {r0}
         b MPU_uxQueueMessagesWaitingImpl
     MPU_uxQueueMessagesWaiting_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxQueueMessagesWaiting
 /*-----------------------------------------------------------*/
 
@@ -509,12 +476,11 @@ MPU_uxQueueSpacesAvailable:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxQueueSpacesAvailable_Unpriv
     MPU_uxQueueSpacesAvailable_Priv:
-        pop {r0}
         b MPU_uxQueueSpacesAvailableImpl
     MPU_uxQueueSpacesAvailable_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxQueueSpacesAvailable
 /*-----------------------------------------------------------*/
 
@@ -523,12 +489,11 @@ MPU_xQueueReceive:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueReceive_Unpriv
     MPU_xQueueReceive_Priv:
-        pop {r0}
         b MPU_xQueueReceiveImpl
     MPU_xQueueReceive_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueReceive
 /*-----------------------------------------------------------*/
 
@@ -537,12 +502,11 @@ MPU_xQueuePeek:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueuePeek_Unpriv
     MPU_xQueuePeek_Priv:
-        pop {r0}
         b MPU_xQueuePeekImpl
     MPU_xQueuePeek_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueuePeek
 /*-----------------------------------------------------------*/
 
@@ -551,12 +515,11 @@ MPU_xQueueSemaphoreTake:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueSemaphoreTake_Unpriv
     MPU_xQueueSemaphoreTake_Priv:
-        pop {r0}
         b MPU_xQueueSemaphoreTakeImpl
     MPU_xQueueSemaphoreTake_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueSemaphoreTake
 /*-----------------------------------------------------------*/
 
@@ -565,12 +528,11 @@ MPU_xQueueGetMutexHolder:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueGetMutexHolder_Unpriv
     MPU_xQueueGetMutexHolder_Priv:
-        pop {r0}
         b MPU_xQueueGetMutexHolderImpl
     MPU_xQueueGetMutexHolder_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueGetMutexHolder
 /*-----------------------------------------------------------*/
 
@@ -579,12 +541,11 @@ MPU_xQueueTakeMutexRecursive:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueTakeMutexRecursive_Unpriv
     MPU_xQueueTakeMutexRecursive_Priv:
-        pop {r0}
         b MPU_xQueueTakeMutexRecursiveImpl
     MPU_xQueueTakeMutexRecursive_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueTakeMutexRecursive
 /*-----------------------------------------------------------*/
 
@@ -593,12 +554,11 @@ MPU_xQueueGiveMutexRecursive:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueGiveMutexRecursive_Unpriv
     MPU_xQueueGiveMutexRecursive_Priv:
-        pop {r0}
         b MPU_xQueueGiveMutexRecursiveImpl
     MPU_xQueueGiveMutexRecursive_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueGiveMutexRecursive
 /*-----------------------------------------------------------*/
 
@@ -607,12 +567,11 @@ MPU_xQueueSelectFromSet:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueSelectFromSet_Unpriv
     MPU_xQueueSelectFromSet_Priv:
-        pop {r0}
         b MPU_xQueueSelectFromSetImpl
     MPU_xQueueSelectFromSet_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueSelectFromSet
 /*-----------------------------------------------------------*/
 
@@ -621,12 +580,11 @@ MPU_xQueueAddToSet:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueAddToSet_Unpriv
     MPU_xQueueAddToSet_Priv:
-        pop {r0}
         b MPU_xQueueAddToSetImpl
     MPU_xQueueAddToSet_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueAddToSet
 /*-----------------------------------------------------------*/
 
@@ -635,12 +593,11 @@ MPU_vQueueAddToRegistry:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vQueueAddToRegistry_Unpriv
     MPU_vQueueAddToRegistry_Priv:
-        pop {r0}
         b MPU_vQueueAddToRegistryImpl
     MPU_vQueueAddToRegistry_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vQueueAddToRegistry
 /*-----------------------------------------------------------*/
 
@@ -649,12 +606,11 @@ MPU_vQueueUnregisterQueue:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vQueueUnregisterQueue_Unpriv
     MPU_vQueueUnregisterQueue_Priv:
-        pop {r0}
         b MPU_vQueueUnregisterQueueImpl
     MPU_vQueueUnregisterQueue_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vQueueUnregisterQueue
 /*-----------------------------------------------------------*/
 
@@ -663,12 +619,11 @@ MPU_pcQueueGetName:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_pcQueueGetName_Unpriv
     MPU_pcQueueGetName_Priv:
-        pop {r0}
         b MPU_pcQueueGetNameImpl
     MPU_pcQueueGetName_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_pcQueueGetName
 /*-----------------------------------------------------------*/
 
@@ -677,12 +632,11 @@ MPU_pvTimerGetTimerID:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_pvTimerGetTimerID_Unpriv
     MPU_pvTimerGetTimerID_Priv:
-        pop {r0}
         b MPU_pvTimerGetTimerIDImpl
     MPU_pvTimerGetTimerID_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_pvTimerGetTimerID
 /*-----------------------------------------------------------*/
 
@@ -691,12 +645,11 @@ MPU_vTimerSetTimerID:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTimerSetTimerID_Unpriv
     MPU_vTimerSetTimerID_Priv:
-        pop {r0}
         b MPU_vTimerSetTimerIDImpl
     MPU_vTimerSetTimerID_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTimerSetTimerID
 /*-----------------------------------------------------------*/
 
@@ -705,12 +658,11 @@ MPU_xTimerIsTimerActive:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerIsTimerActive_Unpriv
     MPU_xTimerIsTimerActive_Priv:
-        pop {r0}
         b MPU_xTimerIsTimerActiveImpl
     MPU_xTimerIsTimerActive_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerIsTimerActive
 /*-----------------------------------------------------------*/
 
@@ -719,12 +671,11 @@ MPU_xTimerGetTimerDaemonTaskHandle:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv
     MPU_xTimerGetTimerDaemonTaskHandle_Priv:
-        pop {r0}
         b MPU_xTimerGetTimerDaemonTaskHandleImpl
     MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle
 /*-----------------------------------------------------------*/
 
@@ -733,12 +684,11 @@ MPU_xTimerGenericCommandFromTaskEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerGenericCommandFromTask_Unpriv
     MPU_xTimerGenericCommandFromTask_Priv:
-        pop {r0}
         b MPU_xTimerGenericCommandFromTaskImpl
     MPU_xTimerGenericCommandFromTask_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerGenericCommandFromTask
 /*-----------------------------------------------------------*/
 
@@ -747,12 +697,11 @@ MPU_pcTimerGetName:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_pcTimerGetName_Unpriv
     MPU_pcTimerGetName_Priv:
-        pop {r0}
         b MPU_pcTimerGetNameImpl
     MPU_pcTimerGetName_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_pcTimerGetName
 /*-----------------------------------------------------------*/
 
@@ -761,12 +710,11 @@ MPU_vTimerSetReloadMode:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTimerSetReloadMode_Unpriv
     MPU_vTimerSetReloadMode_Priv:
-        pop {r0}
         b MPU_vTimerSetReloadModeImpl
     MPU_vTimerSetReloadMode_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTimerSetReloadMode
 /*-----------------------------------------------------------*/
 
@@ -775,12 +723,11 @@ MPU_xTimerGetReloadMode:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerGetReloadMode_Unpriv
     MPU_xTimerGetReloadMode_Priv:
-        pop {r0}
         b MPU_xTimerGetReloadModeImpl
     MPU_xTimerGetReloadMode_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerGetReloadMode
 /*-----------------------------------------------------------*/
 
@@ -789,12 +736,11 @@ MPU_uxTimerGetReloadMode:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTimerGetReloadMode_Unpriv
     MPU_uxTimerGetReloadMode_Priv:
-        pop {r0}
         b MPU_uxTimerGetReloadModeImpl
     MPU_uxTimerGetReloadMode_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTimerGetReloadMode
 /*-----------------------------------------------------------*/
 
@@ -803,12 +749,11 @@ MPU_xTimerGetPeriod:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerGetPeriod_Unpriv
     MPU_xTimerGetPeriod_Priv:
-        pop {r0}
         b MPU_xTimerGetPeriodImpl
     MPU_xTimerGetPeriod_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerGetPeriod
 /*-----------------------------------------------------------*/
 
@@ -817,12 +762,11 @@ MPU_xTimerGetExpiryTime:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerGetExpiryTime_Unpriv
     MPU_xTimerGetExpiryTime_Priv:
-        pop {r0}
         b MPU_xTimerGetExpiryTimeImpl
     MPU_xTimerGetExpiryTime_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerGetExpiryTime
 /*-----------------------------------------------------------*/
 
@@ -831,12 +775,11 @@ MPU_xEventGroupWaitBitsEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xEventGroupWaitBits_Unpriv
     MPU_xEventGroupWaitBits_Priv:
-        pop {r0}
         b MPU_xEventGroupWaitBitsImpl
     MPU_xEventGroupWaitBits_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xEventGroupWaitBits
 /*-----------------------------------------------------------*/
 
@@ -845,12 +788,11 @@ MPU_xEventGroupClearBits:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xEventGroupClearBits_Unpriv
     MPU_xEventGroupClearBits_Priv:
-        pop {r0}
         b MPU_xEventGroupClearBitsImpl
     MPU_xEventGroupClearBits_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xEventGroupClearBits
 /*-----------------------------------------------------------*/
 
@@ -859,12 +801,11 @@ MPU_xEventGroupSetBits:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xEventGroupSetBits_Unpriv
     MPU_xEventGroupSetBits_Priv:
-        pop {r0}
         b MPU_xEventGroupSetBitsImpl
     MPU_xEventGroupSetBits_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xEventGroupSetBits
 /*-----------------------------------------------------------*/
 
@@ -873,12 +814,11 @@ MPU_xEventGroupSync:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xEventGroupSync_Unpriv
     MPU_xEventGroupSync_Priv:
-        pop {r0}
         b MPU_xEventGroupSyncImpl
     MPU_xEventGroupSync_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xEventGroupSync
 /*-----------------------------------------------------------*/
 
@@ -887,12 +827,11 @@ MPU_uxEventGroupGetNumber:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxEventGroupGetNumber_Unpriv
     MPU_uxEventGroupGetNumber_Priv:
-        pop {r0}
         b MPU_uxEventGroupGetNumberImpl
     MPU_uxEventGroupGetNumber_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxEventGroupGetNumber
 /*-----------------------------------------------------------*/
 
@@ -901,12 +840,11 @@ MPU_vEventGroupSetNumber:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vEventGroupSetNumber_Unpriv
     MPU_vEventGroupSetNumber_Priv:
-        pop {r0}
         b MPU_vEventGroupSetNumberImpl
     MPU_vEventGroupSetNumber_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vEventGroupSetNumber
 /*-----------------------------------------------------------*/
 
@@ -915,12 +853,11 @@ MPU_xStreamBufferSend:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferSend_Unpriv
     MPU_xStreamBufferSend_Priv:
-        pop {r0}
         b MPU_xStreamBufferSendImpl
     MPU_xStreamBufferSend_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferSend
 /*-----------------------------------------------------------*/
 
@@ -929,12 +866,11 @@ MPU_xStreamBufferReceive:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferReceive_Unpriv
     MPU_xStreamBufferReceive_Priv:
-        pop {r0}
         b MPU_xStreamBufferReceiveImpl
     MPU_xStreamBufferReceive_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferReceive
 /*-----------------------------------------------------------*/
 
@@ -943,12 +879,11 @@ MPU_xStreamBufferIsFull:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferIsFull_Unpriv
     MPU_xStreamBufferIsFull_Priv:
-        pop {r0}
         b MPU_xStreamBufferIsFullImpl
     MPU_xStreamBufferIsFull_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferIsFull
 /*-----------------------------------------------------------*/
 
@@ -957,12 +892,11 @@ MPU_xStreamBufferIsEmpty:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferIsEmpty_Unpriv
     MPU_xStreamBufferIsEmpty_Priv:
-        pop {r0}
         b MPU_xStreamBufferIsEmptyImpl
     MPU_xStreamBufferIsEmpty_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferIsEmpty
 /*-----------------------------------------------------------*/
 
@@ -971,12 +905,11 @@ MPU_xStreamBufferSpacesAvailable:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferSpacesAvailable_Unpriv
     MPU_xStreamBufferSpacesAvailable_Priv:
-        pop {r0}
         b MPU_xStreamBufferSpacesAvailableImpl
     MPU_xStreamBufferSpacesAvailable_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferSpacesAvailable
 /*-----------------------------------------------------------*/
 
@@ -985,12 +918,11 @@ MPU_xStreamBufferBytesAvailable:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferBytesAvailable_Unpriv
     MPU_xStreamBufferBytesAvailable_Priv:
-        pop {r0}
         b MPU_xStreamBufferBytesAvailableImpl
     MPU_xStreamBufferBytesAvailable_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferBytesAvailable
 /*-----------------------------------------------------------*/
 
@@ -999,12 +931,11 @@ MPU_xStreamBufferSetTriggerLevel:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferSetTriggerLevel_Unpriv
     MPU_xStreamBufferSetTriggerLevel_Priv:
-        pop {r0}
         b MPU_xStreamBufferSetTriggerLevelImpl
     MPU_xStreamBufferSetTriggerLevel_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel
 /*-----------------------------------------------------------*/
 
@@ -1013,12 +944,11 @@ MPU_xStreamBufferNextMessageLengthBytes:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv
     MPU_xStreamBufferNextMessageLengthBytes_Priv:
-        pop {r0}
         b MPU_xStreamBufferNextMessageLengthBytesImpl
     MPU_xStreamBufferNextMessageLengthBytes_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes
 /*-----------------------------------------------------------*/
 
diff --git a/portable/GCC/ARM_CM23/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM23/non_secure/mpu_wrappers_v2_asm.c
index 9c829b540..fb167a699 100644
--- a/portable/GCC/ARM_CM23/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM23/non_secure/mpu_wrappers_v2_asm.c
@@ -63,12 +63,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xTaskDelayUntil_Unpriv                        \n"
                 " MPU_xTaskDelayUntil_Priv:                             \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xTaskDelayUntilImpl                         \n"
                 " MPU_xTaskDelayUntil_Unpriv:                           \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory"
@@ -93,12 +92,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xTaskAbortDelay_Unpriv                        \n"
                 " MPU_xTaskAbortDelay_Priv:                             \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xTaskAbortDelayImpl                         \n"
                 " MPU_xTaskAbortDelay_Unpriv:                           \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory"
@@ -123,12 +121,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_vTaskDelay_Unpriv                             \n"
                 " MPU_vTaskDelay_Priv:                                  \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_vTaskDelayImpl                              \n"
                 " MPU_vTaskDelay_Unpriv:                                \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory"
@@ -153,12 +150,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_uxTaskPriorityGet_Unpriv                      \n"
                 " MPU_uxTaskPriorityGet_Priv:                           \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_uxTaskPriorityGetImpl                       \n"
                 " MPU_uxTaskPriorityGet_Unpriv:                         \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory"
@@ -183,12 +179,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_eTaskGetState_Unpriv                          \n"
                 " MPU_eTaskGetState_Priv:                               \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_eTaskGetStateImpl                           \n"
                 " MPU_eTaskGetState_Unpriv:                             \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory"
@@ -219,12 +214,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_vTaskGetInfo_Unpriv                           \n"
                 " MPU_vTaskGetInfo_Priv:                                \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_vTaskGetInfoImpl                            \n"
                 " MPU_vTaskGetInfo_Unpriv:                              \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory"
@@ -249,12 +243,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xTaskGetIdleTaskHandle_Unpriv                 \n"
                 " MPU_xTaskGetIdleTaskHandle_Priv:                      \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xTaskGetIdleTaskHandleImpl                  \n"
                 " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory"
@@ -279,12 +272,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_vTaskSuspend_Unpriv                           \n"
                 " MPU_vTaskSuspend_Priv:                                \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_vTaskSuspendImpl                            \n"
                 " MPU_vTaskSuspend_Unpriv:                              \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory"
@@ -309,12 +301,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_vTaskResume_Unpriv                            \n"
                 " MPU_vTaskResume_Priv:                                 \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_vTaskResumeImpl                             \n"
                 " MPU_vTaskResume_Unpriv:                               \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskResume ) : "memory"
@@ -337,12 +328,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xTaskGetTickCount_Unpriv                      \n"
             " MPU_xTaskGetTickCount_Priv:                           \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xTaskGetTickCountImpl                       \n"
             " MPU_xTaskGetTickCount_Unpriv:                         \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory"
@@ -363,12 +353,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_uxTaskGetNumberOfTasks_Unpriv                 \n"
             " MPU_uxTaskGetNumberOfTasks_Priv:                      \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_uxTaskGetNumberOfTasksImpl                  \n"
             " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory"
@@ -391,12 +380,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_ulTaskGetRunTimeCounter_Unpriv                \n"
                 " MPU_ulTaskGetRunTimeCounter_Priv:                     \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_ulTaskGetRunTimeCounterImpl                 \n"
                 " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory"
@@ -421,12 +409,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_ulTaskGetRunTimePercent_Unpriv                \n"
                 " MPU_ulTaskGetRunTimePercent_Priv:                     \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_ulTaskGetRunTimePercentImpl                 \n"
                 " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory"
@@ -451,12 +438,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv            \n"
                 " MPU_ulTaskGetIdleRunTimePercent_Priv:                 \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_ulTaskGetIdleRunTimePercentImpl             \n"
                 " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory"
@@ -481,12 +467,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv            \n"
                 " MPU_ulTaskGetIdleRunTimeCounter_Priv:                 \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_ulTaskGetIdleRunTimeCounterImpl             \n"
                 " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory"
@@ -513,12 +498,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_vTaskSetApplicationTaskTag_Unpriv             \n"
                 " MPU_vTaskSetApplicationTaskTag_Priv:                  \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_vTaskSetApplicationTaskTagImpl              \n"
                 " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory"
@@ -543,12 +527,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xTaskGetApplicationTaskTag_Unpriv             \n"
                 " MPU_xTaskGetApplicationTaskTag_Priv:                  \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xTaskGetApplicationTaskTagImpl              \n"
                 " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory"
@@ -577,12 +560,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv      \n"
                 " MPU_vTaskSetThreadLocalStoragePointer_Priv:           \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_vTaskSetThreadLocalStoragePointerImpl       \n"
                 " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory"
@@ -609,12 +591,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv     \n"
                 " MPU_pvTaskGetThreadLocalStoragePointer_Priv:          \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_pvTaskGetThreadLocalStoragePointerImpl      \n"
                 " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory"
@@ -643,12 +624,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_uxTaskGetSystemState_Unpriv                   \n"
                 " MPU_uxTaskGetSystemState_Priv:                        \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_uxTaskGetSystemStateImpl                    \n"
                 " MPU_uxTaskGetSystemState_Unpriv:                      \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory"
@@ -673,12 +653,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_uxTaskGetStackHighWaterMark_Unpriv            \n"
                 " MPU_uxTaskGetStackHighWaterMark_Priv:                 \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_uxTaskGetStackHighWaterMarkImpl             \n"
                 " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory"
@@ -703,12 +682,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv           \n"
                 " MPU_uxTaskGetStackHighWaterMark2_Priv:                \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_uxTaskGetStackHighWaterMark2Impl            \n"
                 " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory"
@@ -733,12 +711,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xTaskGetCurrentTaskHandle_Unpriv              \n"
                 " MPU_xTaskGetCurrentTaskHandle_Priv:                   \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xTaskGetCurrentTaskHandleImpl               \n"
                 " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory"
@@ -763,12 +740,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xTaskGetSchedulerState_Unpriv                 \n"
                 " MPU_xTaskGetSchedulerState_Priv:                      \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xTaskGetSchedulerStateImpl                  \n"
                 " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory"
@@ -791,12 +767,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_vTaskSetTimeOutState_Unpriv                   \n"
             " MPU_vTaskSetTimeOutState_Priv:                        \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_vTaskSetTimeOutStateImpl                    \n"
             " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory"
@@ -819,12 +794,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xTaskCheckForTimeOut_Unpriv                   \n"
             " MPU_xTaskCheckForTimeOut_Priv:                        \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xTaskCheckForTimeOutImpl                    \n"
             " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory"
@@ -847,12 +821,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xTaskGenericNotify_Unpriv                     \n"
                 " MPU_xTaskGenericNotify_Priv:                          \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xTaskGenericNotifyImpl                      \n"
                 " MPU_xTaskGenericNotify_Unpriv:                        \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory"
@@ -877,12 +850,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xTaskGenericNotifyWait_Unpriv                 \n"
                 " MPU_xTaskGenericNotifyWait_Priv:                      \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xTaskGenericNotifyWaitImpl                  \n"
                 " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory"
@@ -911,12 +883,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_ulTaskGenericNotifyTake_Unpriv                \n"
                 " MPU_ulTaskGenericNotifyTake_Priv:                     \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_ulTaskGenericNotifyTakeImpl                 \n"
                 " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory"
@@ -943,12 +914,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xTaskGenericNotifyStateClear_Unpriv           \n"
                 " MPU_xTaskGenericNotifyStateClear_Priv:                \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xTaskGenericNotifyStateClearImpl            \n"
                 " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory"
@@ -977,12 +947,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_ulTaskGenericNotifyValueClear_Unpriv          \n"
                 " MPU_ulTaskGenericNotifyValueClear_Priv:               \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_ulTaskGenericNotifyValueClearImpl           \n"
                 " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory"
@@ -1011,12 +980,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xQueueGenericSend_Unpriv                      \n"
             " MPU_xQueueGenericSend_Priv:                           \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xQueueGenericSendImpl                       \n"
             " MPU_xQueueGenericSend_Unpriv:                         \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory"
@@ -1037,12 +1005,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_uxQueueMessagesWaiting_Unpriv                 \n"
             " MPU_uxQueueMessagesWaiting_Priv:                      \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_uxQueueMessagesWaitingImpl                  \n"
             " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory"
@@ -1063,12 +1030,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_uxQueueSpacesAvailable_Unpriv                 \n"
             " MPU_uxQueueSpacesAvailable_Priv:                      \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_uxQueueSpacesAvailableImpl                  \n"
             " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory"
@@ -1093,12 +1059,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xQueueReceive_Unpriv                          \n"
             " MPU_xQueueReceive_Priv:                               \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xQueueReceiveImpl                           \n"
             " MPU_xQueueReceive_Unpriv:                             \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory"
@@ -1123,12 +1088,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xQueuePeek_Unpriv                             \n"
             " MPU_xQueuePeek_Priv:                                  \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xQueuePeekImpl                              \n"
             " MPU_xQueuePeek_Unpriv:                                \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory"
@@ -1151,12 +1115,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xQueueSemaphoreTake_Unpriv                    \n"
             " MPU_xQueueSemaphoreTake_Priv:                         \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xQueueSemaphoreTakeImpl                     \n"
             " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory"
@@ -1179,12 +1142,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xQueueGetMutexHolder_Unpriv                   \n"
                 " MPU_xQueueGetMutexHolder_Priv:                        \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xQueueGetMutexHolderImpl                    \n"
                 " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory"
@@ -1211,12 +1173,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xQueueTakeMutexRecursive_Unpriv               \n"
                 " MPU_xQueueTakeMutexRecursive_Priv:                    \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xQueueTakeMutexRecursiveImpl                \n"
                 " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory"
@@ -1241,12 +1202,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xQueueGiveMutexRecursive_Unpriv               \n"
                 " MPU_xQueueGiveMutexRecursive_Priv:                    \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xQueueGiveMutexRecursiveImpl                \n"
                 " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory"
@@ -1273,12 +1233,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xQueueSelectFromSet_Unpriv                    \n"
                 " MPU_xQueueSelectFromSet_Priv:                         \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xQueueSelectFromSetImpl                     \n"
                 " MPU_xQueueSelectFromSet_Unpriv:                       \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory"
@@ -1305,12 +1264,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xQueueAddToSet_Unpriv                         \n"
                 " MPU_xQueueAddToSet_Priv:                              \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xQueueAddToSetImpl                          \n"
                 " MPU_xQueueAddToSet_Unpriv:                            \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory"
@@ -1337,12 +1295,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_vQueueAddToRegistry_Unpriv                    \n"
                 " MPU_vQueueAddToRegistry_Priv:                         \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_vQueueAddToRegistryImpl                     \n"
                 " MPU_vQueueAddToRegistry_Unpriv:                       \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory"
@@ -1367,12 +1324,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_vQueueUnregisterQueue_Unpriv                  \n"
                 " MPU_vQueueUnregisterQueue_Priv:                       \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_vQueueUnregisterQueueImpl                   \n"
                 " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory"
@@ -1397,12 +1353,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_pcQueueGetName_Unpriv                         \n"
                 " MPU_pcQueueGetName_Priv:                              \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_pcQueueGetNameImpl                          \n"
                 " MPU_pcQueueGetName_Unpriv:                            \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory"
@@ -1427,12 +1382,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_pvTimerGetTimerID_Unpriv                      \n"
                 " MPU_pvTimerGetTimerID_Priv:                           \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_pvTimerGetTimerIDImpl                       \n"
                 " MPU_pvTimerGetTimerID_Unpriv:                         \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory"
@@ -1459,12 +1413,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_vTimerSetTimerID_Unpriv                       \n"
                 " MPU_vTimerSetTimerID_Priv:                            \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_vTimerSetTimerIDImpl                        \n"
                 " MPU_vTimerSetTimerID_Unpriv:                          \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory"
@@ -1489,12 +1442,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xTimerIsTimerActive_Unpriv                    \n"
                 " MPU_xTimerIsTimerActive_Priv:                         \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xTimerIsTimerActiveImpl                     \n"
                 " MPU_xTimerIsTimerActive_Unpriv:                       \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory"
@@ -1519,12 +1471,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv         \n"
                 " MPU_xTimerGetTimerDaemonTaskHandle_Priv:              \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xTimerGetTimerDaemonTaskHandleImpl          \n"
                 " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory"
@@ -1542,21 +1493,20 @@
         {
             __asm volatile
             (
-                " .syntax unified                                               \n"
-                " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
-                "                                                               \n"
-                " push {r0, r1}                                                 \n"
-                " mrs r0, control                                               \n"
-                " movs r1, #1                                                   \n"
-                " tst r0, r1                                                    \n"
-                " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
-                " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
-                "     pop {r0, r1}                                              \n"
-                "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
-                " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
-                "     pop {r0, r1}                                              \n"
-                "     svc %0                                                    \n"
-                "                                                               \n"
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGenericCommandFromTaskImpl          \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xTimerGenericCommandFromTask_Unpriv           \n"
+                " MPU_xTimerGenericCommandFromTask_Priv:                \n"
+                "     b MPU_xTimerGenericCommandFromTaskImpl            \n"
+                " MPU_xTimerGenericCommandFromTask_Unpriv:              \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory"
             );
         }
@@ -1579,12 +1529,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_pcTimerGetName_Unpriv                         \n"
                 " MPU_pcTimerGetName_Priv:                              \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_pcTimerGetNameImpl                          \n"
                 " MPU_pcTimerGetName_Unpriv:                            \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory"
@@ -1611,12 +1560,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_vTimerSetReloadMode_Unpriv                    \n"
                 " MPU_vTimerSetReloadMode_Priv:                         \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_vTimerSetReloadModeImpl                     \n"
                 " MPU_vTimerSetReloadMode_Unpriv:                       \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory"
@@ -1641,12 +1589,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xTimerGetReloadMode_Unpriv                    \n"
                 " MPU_xTimerGetReloadMode_Priv:                         \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xTimerGetReloadModeImpl                     \n"
                 " MPU_xTimerGetReloadMode_Unpriv:                       \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory"
@@ -1671,12 +1618,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_uxTimerGetReloadMode_Unpriv                   \n"
                 " MPU_uxTimerGetReloadMode_Priv:                        \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_uxTimerGetReloadModeImpl                    \n"
                 " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory"
@@ -1701,12 +1647,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xTimerGetPeriod_Unpriv                        \n"
                 " MPU_xTimerGetPeriod_Priv:                             \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xTimerGetPeriodImpl                         \n"
                 " MPU_xTimerGetPeriod_Unpriv:                           \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory"
@@ -1731,12 +1676,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xTimerGetExpiryTime_Unpriv                    \n"
                 " MPU_xTimerGetExpiryTime_Priv:                         \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xTimerGetExpiryTimeImpl                     \n"
                 " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory"
@@ -1759,12 +1703,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
             " MPU_xEventGroupWaitBits_Priv:                         \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xEventGroupWaitBitsImpl                     \n"
             " MPU_xEventGroupWaitBits_Unpriv:                       \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
@@ -1787,12 +1730,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xEventGroupClearBits_Unpriv                   \n"
             " MPU_xEventGroupClearBits_Priv:                        \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xEventGroupClearBitsImpl                    \n"
             " MPU_xEventGroupClearBits_Unpriv:                      \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
@@ -1815,12 +1757,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xEventGroupSetBits_Unpriv                     \n"
             " MPU_xEventGroupSetBits_Priv:                          \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xEventGroupSetBitsImpl                      \n"
             " MPU_xEventGroupSetBits_Unpriv:                        \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
@@ -1847,12 +1788,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xEventGroupSync_Unpriv                        \n"
             " MPU_xEventGroupSync_Priv:                             \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xEventGroupSyncImpl                         \n"
             " MPU_xEventGroupSync_Unpriv:                           \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
@@ -1875,12 +1815,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_uxEventGroupGetNumber_Unpriv                  \n"
                 " MPU_uxEventGroupGetNumber_Priv:                       \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_uxEventGroupGetNumberImpl                   \n"
                 " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory"
@@ -1907,12 +1846,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_vEventGroupSetNumber_Unpriv                   \n"
                 " MPU_vEventGroupSetNumber_Priv:                        \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_vEventGroupSetNumberImpl                    \n"
                 " MPU_vEventGroupSetNumber_Unpriv:                      \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory"
@@ -1941,12 +1879,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xStreamBufferSend_Unpriv                      \n"
             " MPU_xStreamBufferSend_Priv:                           \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xStreamBufferSendImpl                       \n"
             " MPU_xStreamBufferSend_Unpriv:                         \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
@@ -1973,12 +1910,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xStreamBufferReceive_Unpriv                   \n"
             " MPU_xStreamBufferReceive_Priv:                        \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xStreamBufferReceiveImpl                    \n"
             " MPU_xStreamBufferReceive_Unpriv:                      \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
@@ -1999,12 +1935,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
             " MPU_xStreamBufferIsFull_Priv:                         \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xStreamBufferIsFullImpl                     \n"
             " MPU_xStreamBufferIsFull_Unpriv:                       \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
@@ -2025,12 +1960,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
             " MPU_xStreamBufferIsEmpty_Priv:                        \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xStreamBufferIsEmptyImpl                    \n"
             " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
@@ -2051,12 +1985,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
             " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
             " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
@@ -2077,12 +2010,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
             " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xStreamBufferBytesAvailableImpl             \n"
             " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
@@ -2105,12 +2037,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
             " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
             " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
@@ -2131,12 +2062,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
             " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
             " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.c
index 9c829b540..fb167a699 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.c
@@ -63,12 +63,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xTaskDelayUntil_Unpriv                        \n"
                 " MPU_xTaskDelayUntil_Priv:                             \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xTaskDelayUntilImpl                         \n"
                 " MPU_xTaskDelayUntil_Unpriv:                           \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory"
@@ -93,12 +92,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xTaskAbortDelay_Unpriv                        \n"
                 " MPU_xTaskAbortDelay_Priv:                             \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xTaskAbortDelayImpl                         \n"
                 " MPU_xTaskAbortDelay_Unpriv:                           \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory"
@@ -123,12 +121,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_vTaskDelay_Unpriv                             \n"
                 " MPU_vTaskDelay_Priv:                                  \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_vTaskDelayImpl                              \n"
                 " MPU_vTaskDelay_Unpriv:                                \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory"
@@ -153,12 +150,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_uxTaskPriorityGet_Unpriv                      \n"
                 " MPU_uxTaskPriorityGet_Priv:                           \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_uxTaskPriorityGetImpl                       \n"
                 " MPU_uxTaskPriorityGet_Unpriv:                         \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory"
@@ -183,12 +179,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_eTaskGetState_Unpriv                          \n"
                 " MPU_eTaskGetState_Priv:                               \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_eTaskGetStateImpl                           \n"
                 " MPU_eTaskGetState_Unpriv:                             \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory"
@@ -219,12 +214,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_vTaskGetInfo_Unpriv                           \n"
                 " MPU_vTaskGetInfo_Priv:                                \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_vTaskGetInfoImpl                            \n"
                 " MPU_vTaskGetInfo_Unpriv:                              \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory"
@@ -249,12 +243,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xTaskGetIdleTaskHandle_Unpriv                 \n"
                 " MPU_xTaskGetIdleTaskHandle_Priv:                      \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xTaskGetIdleTaskHandleImpl                  \n"
                 " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory"
@@ -279,12 +272,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_vTaskSuspend_Unpriv                           \n"
                 " MPU_vTaskSuspend_Priv:                                \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_vTaskSuspendImpl                            \n"
                 " MPU_vTaskSuspend_Unpriv:                              \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory"
@@ -309,12 +301,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_vTaskResume_Unpriv                            \n"
                 " MPU_vTaskResume_Priv:                                 \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_vTaskResumeImpl                             \n"
                 " MPU_vTaskResume_Unpriv:                               \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskResume ) : "memory"
@@ -337,12 +328,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xTaskGetTickCount_Unpriv                      \n"
             " MPU_xTaskGetTickCount_Priv:                           \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xTaskGetTickCountImpl                       \n"
             " MPU_xTaskGetTickCount_Unpriv:                         \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory"
@@ -363,12 +353,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_uxTaskGetNumberOfTasks_Unpriv                 \n"
             " MPU_uxTaskGetNumberOfTasks_Priv:                      \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_uxTaskGetNumberOfTasksImpl                  \n"
             " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory"
@@ -391,12 +380,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_ulTaskGetRunTimeCounter_Unpriv                \n"
                 " MPU_ulTaskGetRunTimeCounter_Priv:                     \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_ulTaskGetRunTimeCounterImpl                 \n"
                 " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory"
@@ -421,12 +409,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_ulTaskGetRunTimePercent_Unpriv                \n"
                 " MPU_ulTaskGetRunTimePercent_Priv:                     \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_ulTaskGetRunTimePercentImpl                 \n"
                 " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory"
@@ -451,12 +438,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv            \n"
                 " MPU_ulTaskGetIdleRunTimePercent_Priv:                 \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_ulTaskGetIdleRunTimePercentImpl             \n"
                 " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory"
@@ -481,12 +467,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv            \n"
                 " MPU_ulTaskGetIdleRunTimeCounter_Priv:                 \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_ulTaskGetIdleRunTimeCounterImpl             \n"
                 " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory"
@@ -513,12 +498,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_vTaskSetApplicationTaskTag_Unpriv             \n"
                 " MPU_vTaskSetApplicationTaskTag_Priv:                  \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_vTaskSetApplicationTaskTagImpl              \n"
                 " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory"
@@ -543,12 +527,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xTaskGetApplicationTaskTag_Unpriv             \n"
                 " MPU_xTaskGetApplicationTaskTag_Priv:                  \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xTaskGetApplicationTaskTagImpl              \n"
                 " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory"
@@ -577,12 +560,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv      \n"
                 " MPU_vTaskSetThreadLocalStoragePointer_Priv:           \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_vTaskSetThreadLocalStoragePointerImpl       \n"
                 " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory"
@@ -609,12 +591,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv     \n"
                 " MPU_pvTaskGetThreadLocalStoragePointer_Priv:          \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_pvTaskGetThreadLocalStoragePointerImpl      \n"
                 " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory"
@@ -643,12 +624,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_uxTaskGetSystemState_Unpriv                   \n"
                 " MPU_uxTaskGetSystemState_Priv:                        \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_uxTaskGetSystemStateImpl                    \n"
                 " MPU_uxTaskGetSystemState_Unpriv:                      \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory"
@@ -673,12 +653,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_uxTaskGetStackHighWaterMark_Unpriv            \n"
                 " MPU_uxTaskGetStackHighWaterMark_Priv:                 \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_uxTaskGetStackHighWaterMarkImpl             \n"
                 " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory"
@@ -703,12 +682,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv           \n"
                 " MPU_uxTaskGetStackHighWaterMark2_Priv:                \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_uxTaskGetStackHighWaterMark2Impl            \n"
                 " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory"
@@ -733,12 +711,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xTaskGetCurrentTaskHandle_Unpriv              \n"
                 " MPU_xTaskGetCurrentTaskHandle_Priv:                   \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xTaskGetCurrentTaskHandleImpl               \n"
                 " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory"
@@ -763,12 +740,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xTaskGetSchedulerState_Unpriv                 \n"
                 " MPU_xTaskGetSchedulerState_Priv:                      \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xTaskGetSchedulerStateImpl                  \n"
                 " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory"
@@ -791,12 +767,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_vTaskSetTimeOutState_Unpriv                   \n"
             " MPU_vTaskSetTimeOutState_Priv:                        \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_vTaskSetTimeOutStateImpl                    \n"
             " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory"
@@ -819,12 +794,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xTaskCheckForTimeOut_Unpriv                   \n"
             " MPU_xTaskCheckForTimeOut_Priv:                        \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xTaskCheckForTimeOutImpl                    \n"
             " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory"
@@ -847,12 +821,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xTaskGenericNotify_Unpriv                     \n"
                 " MPU_xTaskGenericNotify_Priv:                          \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xTaskGenericNotifyImpl                      \n"
                 " MPU_xTaskGenericNotify_Unpriv:                        \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory"
@@ -877,12 +850,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xTaskGenericNotifyWait_Unpriv                 \n"
                 " MPU_xTaskGenericNotifyWait_Priv:                      \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xTaskGenericNotifyWaitImpl                  \n"
                 " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory"
@@ -911,12 +883,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_ulTaskGenericNotifyTake_Unpriv                \n"
                 " MPU_ulTaskGenericNotifyTake_Priv:                     \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_ulTaskGenericNotifyTakeImpl                 \n"
                 " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory"
@@ -943,12 +914,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xTaskGenericNotifyStateClear_Unpriv           \n"
                 " MPU_xTaskGenericNotifyStateClear_Priv:                \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xTaskGenericNotifyStateClearImpl            \n"
                 " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory"
@@ -977,12 +947,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_ulTaskGenericNotifyValueClear_Unpriv          \n"
                 " MPU_ulTaskGenericNotifyValueClear_Priv:               \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_ulTaskGenericNotifyValueClearImpl           \n"
                 " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory"
@@ -1011,12 +980,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xQueueGenericSend_Unpriv                      \n"
             " MPU_xQueueGenericSend_Priv:                           \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xQueueGenericSendImpl                       \n"
             " MPU_xQueueGenericSend_Unpriv:                         \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory"
@@ -1037,12 +1005,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_uxQueueMessagesWaiting_Unpriv                 \n"
             " MPU_uxQueueMessagesWaiting_Priv:                      \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_uxQueueMessagesWaitingImpl                  \n"
             " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory"
@@ -1063,12 +1030,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_uxQueueSpacesAvailable_Unpriv                 \n"
             " MPU_uxQueueSpacesAvailable_Priv:                      \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_uxQueueSpacesAvailableImpl                  \n"
             " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory"
@@ -1093,12 +1059,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xQueueReceive_Unpriv                          \n"
             " MPU_xQueueReceive_Priv:                               \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xQueueReceiveImpl                           \n"
             " MPU_xQueueReceive_Unpriv:                             \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory"
@@ -1123,12 +1088,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xQueuePeek_Unpriv                             \n"
             " MPU_xQueuePeek_Priv:                                  \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xQueuePeekImpl                              \n"
             " MPU_xQueuePeek_Unpriv:                                \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory"
@@ -1151,12 +1115,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xQueueSemaphoreTake_Unpriv                    \n"
             " MPU_xQueueSemaphoreTake_Priv:                         \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xQueueSemaphoreTakeImpl                     \n"
             " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory"
@@ -1179,12 +1142,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xQueueGetMutexHolder_Unpriv                   \n"
                 " MPU_xQueueGetMutexHolder_Priv:                        \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xQueueGetMutexHolderImpl                    \n"
                 " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory"
@@ -1211,12 +1173,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xQueueTakeMutexRecursive_Unpriv               \n"
                 " MPU_xQueueTakeMutexRecursive_Priv:                    \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xQueueTakeMutexRecursiveImpl                \n"
                 " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory"
@@ -1241,12 +1202,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xQueueGiveMutexRecursive_Unpriv               \n"
                 " MPU_xQueueGiveMutexRecursive_Priv:                    \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xQueueGiveMutexRecursiveImpl                \n"
                 " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory"
@@ -1273,12 +1233,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xQueueSelectFromSet_Unpriv                    \n"
                 " MPU_xQueueSelectFromSet_Priv:                         \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xQueueSelectFromSetImpl                     \n"
                 " MPU_xQueueSelectFromSet_Unpriv:                       \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory"
@@ -1305,12 +1264,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xQueueAddToSet_Unpriv                         \n"
                 " MPU_xQueueAddToSet_Priv:                              \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xQueueAddToSetImpl                          \n"
                 " MPU_xQueueAddToSet_Unpriv:                            \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory"
@@ -1337,12 +1295,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_vQueueAddToRegistry_Unpriv                    \n"
                 " MPU_vQueueAddToRegistry_Priv:                         \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_vQueueAddToRegistryImpl                     \n"
                 " MPU_vQueueAddToRegistry_Unpriv:                       \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory"
@@ -1367,12 +1324,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_vQueueUnregisterQueue_Unpriv                  \n"
                 " MPU_vQueueUnregisterQueue_Priv:                       \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_vQueueUnregisterQueueImpl                   \n"
                 " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory"
@@ -1397,12 +1353,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_pcQueueGetName_Unpriv                         \n"
                 " MPU_pcQueueGetName_Priv:                              \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_pcQueueGetNameImpl                          \n"
                 " MPU_pcQueueGetName_Unpriv:                            \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory"
@@ -1427,12 +1382,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_pvTimerGetTimerID_Unpriv                      \n"
                 " MPU_pvTimerGetTimerID_Priv:                           \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_pvTimerGetTimerIDImpl                       \n"
                 " MPU_pvTimerGetTimerID_Unpriv:                         \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory"
@@ -1459,12 +1413,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_vTimerSetTimerID_Unpriv                       \n"
                 " MPU_vTimerSetTimerID_Priv:                            \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_vTimerSetTimerIDImpl                        \n"
                 " MPU_vTimerSetTimerID_Unpriv:                          \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory"
@@ -1489,12 +1442,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xTimerIsTimerActive_Unpriv                    \n"
                 " MPU_xTimerIsTimerActive_Priv:                         \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xTimerIsTimerActiveImpl                     \n"
                 " MPU_xTimerIsTimerActive_Unpriv:                       \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory"
@@ -1519,12 +1471,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv         \n"
                 " MPU_xTimerGetTimerDaemonTaskHandle_Priv:              \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xTimerGetTimerDaemonTaskHandleImpl          \n"
                 " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory"
@@ -1542,21 +1493,20 @@
         {
             __asm volatile
             (
-                " .syntax unified                                               \n"
-                " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
-                "                                                               \n"
-                " push {r0, r1}                                                 \n"
-                " mrs r0, control                                               \n"
-                " movs r1, #1                                                   \n"
-                " tst r0, r1                                                    \n"
-                " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
-                " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
-                "     pop {r0, r1}                                              \n"
-                "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
-                " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
-                "     pop {r0, r1}                                              \n"
-                "     svc %0                                                    \n"
-                "                                                               \n"
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGenericCommandFromTaskImpl          \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xTimerGenericCommandFromTask_Unpriv           \n"
+                " MPU_xTimerGenericCommandFromTask_Priv:                \n"
+                "     b MPU_xTimerGenericCommandFromTaskImpl            \n"
+                " MPU_xTimerGenericCommandFromTask_Unpriv:              \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory"
             );
         }
@@ -1579,12 +1529,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_pcTimerGetName_Unpriv                         \n"
                 " MPU_pcTimerGetName_Priv:                              \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_pcTimerGetNameImpl                          \n"
                 " MPU_pcTimerGetName_Unpriv:                            \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory"
@@ -1611,12 +1560,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_vTimerSetReloadMode_Unpriv                    \n"
                 " MPU_vTimerSetReloadMode_Priv:                         \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_vTimerSetReloadModeImpl                     \n"
                 " MPU_vTimerSetReloadMode_Unpriv:                       \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory"
@@ -1641,12 +1589,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xTimerGetReloadMode_Unpriv                    \n"
                 " MPU_xTimerGetReloadMode_Priv:                         \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xTimerGetReloadModeImpl                     \n"
                 " MPU_xTimerGetReloadMode_Unpriv:                       \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory"
@@ -1671,12 +1618,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_uxTimerGetReloadMode_Unpriv                   \n"
                 " MPU_uxTimerGetReloadMode_Priv:                        \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_uxTimerGetReloadModeImpl                    \n"
                 " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory"
@@ -1701,12 +1647,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xTimerGetPeriod_Unpriv                        \n"
                 " MPU_xTimerGetPeriod_Priv:                             \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xTimerGetPeriodImpl                         \n"
                 " MPU_xTimerGetPeriod_Unpriv:                           \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory"
@@ -1731,12 +1676,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_xTimerGetExpiryTime_Unpriv                    \n"
                 " MPU_xTimerGetExpiryTime_Priv:                         \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_xTimerGetExpiryTimeImpl                     \n"
                 " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory"
@@ -1759,12 +1703,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
             " MPU_xEventGroupWaitBits_Priv:                         \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xEventGroupWaitBitsImpl                     \n"
             " MPU_xEventGroupWaitBits_Unpriv:                       \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
@@ -1787,12 +1730,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xEventGroupClearBits_Unpriv                   \n"
             " MPU_xEventGroupClearBits_Priv:                        \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xEventGroupClearBitsImpl                    \n"
             " MPU_xEventGroupClearBits_Unpriv:                      \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
@@ -1815,12 +1757,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xEventGroupSetBits_Unpriv                     \n"
             " MPU_xEventGroupSetBits_Priv:                          \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xEventGroupSetBitsImpl                      \n"
             " MPU_xEventGroupSetBits_Unpriv:                        \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
@@ -1847,12 +1788,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xEventGroupSync_Unpriv                        \n"
             " MPU_xEventGroupSync_Priv:                             \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xEventGroupSyncImpl                         \n"
             " MPU_xEventGroupSync_Unpriv:                           \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
@@ -1875,12 +1815,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_uxEventGroupGetNumber_Unpriv                  \n"
                 " MPU_uxEventGroupGetNumber_Priv:                       \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_uxEventGroupGetNumberImpl                   \n"
                 " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory"
@@ -1907,12 +1846,11 @@
                 " mrs r0, control                                       \n"
                 " movs r1, #1                                           \n"
                 " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
                 " bne MPU_vEventGroupSetNumber_Unpriv                   \n"
                 " MPU_vEventGroupSetNumber_Priv:                        \n"
-                "     pop {r0, r1}                                      \n"
                 "     b MPU_vEventGroupSetNumberImpl                    \n"
                 " MPU_vEventGroupSetNumber_Unpriv:                      \n"
-                "     pop {r0, r1}                                      \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory"
@@ -1941,12 +1879,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xStreamBufferSend_Unpriv                      \n"
             " MPU_xStreamBufferSend_Priv:                           \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xStreamBufferSendImpl                       \n"
             " MPU_xStreamBufferSend_Unpriv:                         \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
@@ -1973,12 +1910,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xStreamBufferReceive_Unpriv                   \n"
             " MPU_xStreamBufferReceive_Priv:                        \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xStreamBufferReceiveImpl                    \n"
             " MPU_xStreamBufferReceive_Unpriv:                      \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
@@ -1999,12 +1935,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
             " MPU_xStreamBufferIsFull_Priv:                         \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xStreamBufferIsFullImpl                     \n"
             " MPU_xStreamBufferIsFull_Unpriv:                       \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
@@ -2025,12 +1960,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
             " MPU_xStreamBufferIsEmpty_Priv:                        \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xStreamBufferIsEmptyImpl                    \n"
             " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
@@ -2051,12 +1985,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
             " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
             " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
@@ -2077,12 +2010,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
             " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xStreamBufferBytesAvailableImpl             \n"
             " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
@@ -2105,12 +2037,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
             " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
             " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
@@ -2131,12 +2062,11 @@
             " mrs r0, control                                       \n"
             " movs r1, #1                                           \n"
             " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
             " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
             " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
-            "     pop {r0, r1}                                      \n"
             "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
             " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
-            "     pop {r0, r1}                                      \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
diff --git a/portable/GCC/ARM_CM33/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM33/non_secure/mpu_wrappers_v2_asm.c
index 170d10fcc..4f66448f9 100644
--- a/portable/GCC/ARM_CM33/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM33/non_secure/mpu_wrappers_v2_asm.c
@@ -62,12 +62,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskDelayUntil_Unpriv                        \n"
                 " MPU_xTaskDelayUntil_Priv:                             \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskDelayUntilImpl                         \n"
                 " MPU_xTaskDelayUntil_Unpriv:                           \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory"
@@ -91,12 +90,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskAbortDelay_Unpriv                        \n"
                 " MPU_xTaskAbortDelay_Priv:                             \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskAbortDelayImpl                         \n"
                 " MPU_xTaskAbortDelay_Unpriv:                           \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory"
@@ -120,12 +118,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskDelay_Unpriv                             \n"
                 " MPU_vTaskDelay_Priv:                                  \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskDelayImpl                              \n"
                 " MPU_vTaskDelay_Unpriv:                                \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory"
@@ -149,12 +146,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxTaskPriorityGet_Unpriv                      \n"
                 " MPU_uxTaskPriorityGet_Priv:                           \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxTaskPriorityGetImpl                       \n"
                 " MPU_uxTaskPriorityGet_Unpriv:                         \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory"
@@ -178,12 +174,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_eTaskGetState_Unpriv                          \n"
                 " MPU_eTaskGetState_Priv:                               \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_eTaskGetStateImpl                           \n"
                 " MPU_eTaskGetState_Unpriv:                             \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory"
@@ -213,12 +208,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskGetInfo_Unpriv                           \n"
                 " MPU_vTaskGetInfo_Priv:                                \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskGetInfoImpl                            \n"
                 " MPU_vTaskGetInfo_Unpriv:                              \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory"
@@ -242,12 +236,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGetIdleTaskHandle_Unpriv                 \n"
                 " MPU_xTaskGetIdleTaskHandle_Priv:                      \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGetIdleTaskHandleImpl                  \n"
                 " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory"
@@ -271,12 +264,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskSuspend_Unpriv                           \n"
                 " MPU_vTaskSuspend_Priv:                                \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskSuspendImpl                            \n"
                 " MPU_vTaskSuspend_Unpriv:                              \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory"
@@ -300,12 +292,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskResume_Unpriv                            \n"
                 " MPU_vTaskResume_Priv:                                 \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskResumeImpl                             \n"
                 " MPU_vTaskResume_Unpriv:                               \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskResume ) : "memory"
@@ -327,12 +318,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xTaskGetTickCount_Unpriv                      \n"
             " MPU_xTaskGetTickCount_Priv:                           \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xTaskGetTickCountImpl                       \n"
             " MPU_xTaskGetTickCount_Unpriv:                         \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory"
@@ -352,12 +342,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_uxTaskGetNumberOfTasks_Unpriv                 \n"
             " MPU_uxTaskGetNumberOfTasks_Priv:                      \n"
-            "     pop {r0}                                          \n"
             "     b MPU_uxTaskGetNumberOfTasksImpl                  \n"
             " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory"
@@ -379,12 +368,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGetRunTimeCounter_Unpriv                \n"
                 " MPU_ulTaskGetRunTimeCounter_Priv:                     \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGetRunTimeCounterImpl                 \n"
                 " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory"
@@ -408,12 +396,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGetRunTimePercent_Unpriv                \n"
                 " MPU_ulTaskGetRunTimePercent_Priv:                     \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGetRunTimePercentImpl                 \n"
                 " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory"
@@ -437,12 +424,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv            \n"
                 " MPU_ulTaskGetIdleRunTimePercent_Priv:                 \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGetIdleRunTimePercentImpl             \n"
                 " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory"
@@ -466,12 +452,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv            \n"
                 " MPU_ulTaskGetIdleRunTimeCounter_Priv:                 \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGetIdleRunTimeCounterImpl             \n"
                 " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory"
@@ -497,12 +482,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskSetApplicationTaskTag_Unpriv             \n"
                 " MPU_vTaskSetApplicationTaskTag_Priv:                  \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskSetApplicationTaskTagImpl              \n"
                 " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory"
@@ -526,12 +510,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGetApplicationTaskTag_Unpriv             \n"
                 " MPU_xTaskGetApplicationTaskTag_Priv:                  \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGetApplicationTaskTagImpl              \n"
                 " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory"
@@ -559,12 +542,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv      \n"
                 " MPU_vTaskSetThreadLocalStoragePointer_Priv:           \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskSetThreadLocalStoragePointerImpl       \n"
                 " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory"
@@ -590,12 +572,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv     \n"
                 " MPU_pvTaskGetThreadLocalStoragePointer_Priv:          \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_pvTaskGetThreadLocalStoragePointerImpl      \n"
                 " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory"
@@ -623,12 +604,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxTaskGetSystemState_Unpriv                   \n"
                 " MPU_uxTaskGetSystemState_Priv:                        \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxTaskGetSystemStateImpl                    \n"
                 " MPU_uxTaskGetSystemState_Unpriv:                      \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory"
@@ -652,12 +632,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxTaskGetStackHighWaterMark_Unpriv            \n"
                 " MPU_uxTaskGetStackHighWaterMark_Priv:                 \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxTaskGetStackHighWaterMarkImpl             \n"
                 " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory"
@@ -681,12 +660,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv           \n"
                 " MPU_uxTaskGetStackHighWaterMark2_Priv:                \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxTaskGetStackHighWaterMark2Impl            \n"
                 " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory"
@@ -710,12 +688,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGetCurrentTaskHandle_Unpriv              \n"
                 " MPU_xTaskGetCurrentTaskHandle_Priv:                   \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGetCurrentTaskHandleImpl               \n"
                 " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory"
@@ -739,12 +716,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGetSchedulerState_Unpriv                 \n"
                 " MPU_xTaskGetSchedulerState_Priv:                      \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGetSchedulerStateImpl                  \n"
                 " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory"
@@ -766,12 +742,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_vTaskSetTimeOutState_Unpriv                   \n"
             " MPU_vTaskSetTimeOutState_Priv:                        \n"
-            "     pop {r0}                                          \n"
             "     b MPU_vTaskSetTimeOutStateImpl                    \n"
             " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory"
@@ -793,12 +768,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xTaskCheckForTimeOut_Unpriv                   \n"
             " MPU_xTaskCheckForTimeOut_Priv:                        \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xTaskCheckForTimeOutImpl                    \n"
             " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory"
@@ -820,12 +794,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGenericNotify_Unpriv                     \n"
                 " MPU_xTaskGenericNotify_Priv:                          \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGenericNotifyImpl                      \n"
                 " MPU_xTaskGenericNotify_Unpriv:                        \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory"
@@ -849,12 +822,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGenericNotifyWait_Unpriv                 \n"
                 " MPU_xTaskGenericNotifyWait_Priv:                      \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGenericNotifyWaitImpl                  \n"
                 " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory"
@@ -882,12 +854,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGenericNotifyTake_Unpriv                \n"
                 " MPU_ulTaskGenericNotifyTake_Priv:                     \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGenericNotifyTakeImpl                 \n"
                 " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory"
@@ -913,12 +884,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGenericNotifyStateClear_Unpriv           \n"
                 " MPU_xTaskGenericNotifyStateClear_Priv:                \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGenericNotifyStateClearImpl            \n"
                 " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory"
@@ -946,12 +916,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGenericNotifyValueClear_Unpriv          \n"
                 " MPU_ulTaskGenericNotifyValueClear_Priv:               \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGenericNotifyValueClearImpl           \n"
                 " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory"
@@ -979,12 +948,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xQueueGenericSend_Unpriv                      \n"
             " MPU_xQueueGenericSend_Priv:                           \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xQueueGenericSendImpl                       \n"
             " MPU_xQueueGenericSend_Unpriv:                         \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory"
@@ -1004,12 +972,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_uxQueueMessagesWaiting_Unpriv                 \n"
             " MPU_uxQueueMessagesWaiting_Priv:                      \n"
-            "     pop {r0}                                          \n"
             "     b MPU_uxQueueMessagesWaitingImpl                  \n"
             " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory"
@@ -1029,12 +996,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_uxQueueSpacesAvailable_Unpriv                 \n"
             " MPU_uxQueueSpacesAvailable_Priv:                      \n"
-            "     pop {r0}                                          \n"
             "     b MPU_uxQueueSpacesAvailableImpl                  \n"
             " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory"
@@ -1058,12 +1024,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xQueueReceive_Unpriv                          \n"
             " MPU_xQueueReceive_Priv:                               \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xQueueReceiveImpl                           \n"
             " MPU_xQueueReceive_Unpriv:                             \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory"
@@ -1087,12 +1052,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xQueuePeek_Unpriv                             \n"
             " MPU_xQueuePeek_Priv:                                  \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xQueuePeekImpl                              \n"
             " MPU_xQueuePeek_Unpriv:                                \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory"
@@ -1114,12 +1078,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xQueueSemaphoreTake_Unpriv                    \n"
             " MPU_xQueueSemaphoreTake_Priv:                         \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xQueueSemaphoreTakeImpl                     \n"
             " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory"
@@ -1141,12 +1104,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xQueueGetMutexHolder_Unpriv                   \n"
                 " MPU_xQueueGetMutexHolder_Priv:                        \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xQueueGetMutexHolderImpl                    \n"
                 " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory"
@@ -1172,12 +1134,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xQueueTakeMutexRecursive_Unpriv               \n"
                 " MPU_xQueueTakeMutexRecursive_Priv:                    \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xQueueTakeMutexRecursiveImpl                \n"
                 " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory"
@@ -1201,12 +1162,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xQueueGiveMutexRecursive_Unpriv               \n"
                 " MPU_xQueueGiveMutexRecursive_Priv:                    \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xQueueGiveMutexRecursiveImpl                \n"
                 " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory"
@@ -1232,12 +1192,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xQueueSelectFromSet_Unpriv                    \n"
                 " MPU_xQueueSelectFromSet_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xQueueSelectFromSetImpl                     \n"
                 " MPU_xQueueSelectFromSet_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory"
@@ -1263,12 +1222,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xQueueAddToSet_Unpriv                         \n"
                 " MPU_xQueueAddToSet_Priv:                              \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xQueueAddToSetImpl                          \n"
                 " MPU_xQueueAddToSet_Unpriv:                            \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory"
@@ -1294,12 +1252,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vQueueAddToRegistry_Unpriv                    \n"
                 " MPU_vQueueAddToRegistry_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vQueueAddToRegistryImpl                     \n"
                 " MPU_vQueueAddToRegistry_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory"
@@ -1323,12 +1280,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vQueueUnregisterQueue_Unpriv                  \n"
                 " MPU_vQueueUnregisterQueue_Priv:                       \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vQueueUnregisterQueueImpl                   \n"
                 " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory"
@@ -1352,12 +1308,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_pcQueueGetName_Unpriv                         \n"
                 " MPU_pcQueueGetName_Priv:                              \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_pcQueueGetNameImpl                          \n"
                 " MPU_pcQueueGetName_Unpriv:                            \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory"
@@ -1381,12 +1336,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_pvTimerGetTimerID_Unpriv                      \n"
                 " MPU_pvTimerGetTimerID_Priv:                           \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_pvTimerGetTimerIDImpl                       \n"
                 " MPU_pvTimerGetTimerID_Unpriv:                         \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory"
@@ -1412,12 +1366,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTimerSetTimerID_Unpriv                       \n"
                 " MPU_vTimerSetTimerID_Priv:                            \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTimerSetTimerIDImpl                        \n"
                 " MPU_vTimerSetTimerID_Unpriv:                          \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory"
@@ -1441,12 +1394,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTimerIsTimerActive_Unpriv                    \n"
                 " MPU_xTimerIsTimerActive_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTimerIsTimerActiveImpl                     \n"
                 " MPU_xTimerIsTimerActive_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory"
@@ -1470,12 +1422,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv         \n"
                 " MPU_xTimerGetTimerDaemonTaskHandle_Priv:              \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTimerGetTimerDaemonTaskHandleImpl          \n"
                 " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory"
@@ -1493,20 +1444,19 @@
         {
             __asm volatile
             (
-                " .syntax unified                                               \n"
-                " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
-                "                                                               \n"
-                " push {r0}                                                     \n"
-                " mrs r0, control                                               \n"
-                " tst r0, #1                                                    \n"
-                " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
-                " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
-                "     pop {r0}                                                  \n"
-                "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
-                " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
-                "     pop {r0}                                                  \n"
-                "     svc %0                                                    \n"
-                "                                                               \n"
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGenericCommandFromTaskImpl          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xTimerGenericCommandFromTask_Unpriv           \n"
+                " MPU_xTimerGenericCommandFromTask_Priv:                \n"
+                "     b MPU_xTimerGenericCommandFromTaskImpl            \n"
+                " MPU_xTimerGenericCommandFromTask_Unpriv:              \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory"
             );
         }
@@ -1528,12 +1478,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_pcTimerGetName_Unpriv                         \n"
                 " MPU_pcTimerGetName_Priv:                              \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_pcTimerGetNameImpl                          \n"
                 " MPU_pcTimerGetName_Unpriv:                            \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory"
@@ -1559,12 +1508,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTimerSetReloadMode_Unpriv                    \n"
                 " MPU_vTimerSetReloadMode_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTimerSetReloadModeImpl                     \n"
                 " MPU_vTimerSetReloadMode_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory"
@@ -1588,12 +1536,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTimerGetReloadMode_Unpriv                    \n"
                 " MPU_xTimerGetReloadMode_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTimerGetReloadModeImpl                     \n"
                 " MPU_xTimerGetReloadMode_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory"
@@ -1617,12 +1564,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxTimerGetReloadMode_Unpriv                   \n"
                 " MPU_uxTimerGetReloadMode_Priv:                        \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxTimerGetReloadModeImpl                    \n"
                 " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory"
@@ -1646,12 +1592,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTimerGetPeriod_Unpriv                        \n"
                 " MPU_xTimerGetPeriod_Priv:                             \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTimerGetPeriodImpl                         \n"
                 " MPU_xTimerGetPeriod_Unpriv:                           \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory"
@@ -1675,12 +1620,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTimerGetExpiryTime_Unpriv                    \n"
                 " MPU_xTimerGetExpiryTime_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTimerGetExpiryTimeImpl                     \n"
                 " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory"
@@ -1702,12 +1646,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
             " MPU_xEventGroupWaitBits_Priv:                         \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xEventGroupWaitBitsImpl                     \n"
             " MPU_xEventGroupWaitBits_Unpriv:                       \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
@@ -1729,12 +1672,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xEventGroupClearBits_Unpriv                   \n"
             " MPU_xEventGroupClearBits_Priv:                        \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xEventGroupClearBitsImpl                    \n"
             " MPU_xEventGroupClearBits_Unpriv:                      \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
@@ -1756,12 +1698,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xEventGroupSetBits_Unpriv                     \n"
             " MPU_xEventGroupSetBits_Priv:                          \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xEventGroupSetBitsImpl                      \n"
             " MPU_xEventGroupSetBits_Unpriv:                        \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
@@ -1787,12 +1728,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xEventGroupSync_Unpriv                        \n"
             " MPU_xEventGroupSync_Priv:                             \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xEventGroupSyncImpl                         \n"
             " MPU_xEventGroupSync_Unpriv:                           \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
@@ -1814,12 +1754,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxEventGroupGetNumber_Unpriv                  \n"
                 " MPU_uxEventGroupGetNumber_Priv:                       \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxEventGroupGetNumberImpl                   \n"
                 " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory"
@@ -1845,12 +1784,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vEventGroupSetNumber_Unpriv                   \n"
                 " MPU_vEventGroupSetNumber_Priv:                        \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vEventGroupSetNumberImpl                    \n"
                 " MPU_vEventGroupSetNumber_Unpriv:                      \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory"
@@ -1878,12 +1816,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferSend_Unpriv                      \n"
             " MPU_xStreamBufferSend_Priv:                           \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferSendImpl                       \n"
             " MPU_xStreamBufferSend_Unpriv:                         \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
@@ -1909,12 +1846,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferReceive_Unpriv                   \n"
             " MPU_xStreamBufferReceive_Priv:                        \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferReceiveImpl                    \n"
             " MPU_xStreamBufferReceive_Unpriv:                      \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
@@ -1934,12 +1870,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
             " MPU_xStreamBufferIsFull_Priv:                         \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferIsFullImpl                     \n"
             " MPU_xStreamBufferIsFull_Unpriv:                       \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
@@ -1959,12 +1894,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
             " MPU_xStreamBufferIsEmpty_Priv:                        \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferIsEmptyImpl                    \n"
             " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
@@ -1984,12 +1918,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
             " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
             " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
@@ -2009,12 +1942,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
             " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferBytesAvailableImpl             \n"
             " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
@@ -2036,12 +1968,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
             " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
             " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
@@ -2061,12 +1992,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
             " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
             " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.c
index 170d10fcc..4f66448f9 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.c
@@ -62,12 +62,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskDelayUntil_Unpriv                        \n"
                 " MPU_xTaskDelayUntil_Priv:                             \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskDelayUntilImpl                         \n"
                 " MPU_xTaskDelayUntil_Unpriv:                           \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory"
@@ -91,12 +90,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskAbortDelay_Unpriv                        \n"
                 " MPU_xTaskAbortDelay_Priv:                             \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskAbortDelayImpl                         \n"
                 " MPU_xTaskAbortDelay_Unpriv:                           \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory"
@@ -120,12 +118,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskDelay_Unpriv                             \n"
                 " MPU_vTaskDelay_Priv:                                  \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskDelayImpl                              \n"
                 " MPU_vTaskDelay_Unpriv:                                \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory"
@@ -149,12 +146,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxTaskPriorityGet_Unpriv                      \n"
                 " MPU_uxTaskPriorityGet_Priv:                           \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxTaskPriorityGetImpl                       \n"
                 " MPU_uxTaskPriorityGet_Unpriv:                         \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory"
@@ -178,12 +174,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_eTaskGetState_Unpriv                          \n"
                 " MPU_eTaskGetState_Priv:                               \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_eTaskGetStateImpl                           \n"
                 " MPU_eTaskGetState_Unpriv:                             \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory"
@@ -213,12 +208,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskGetInfo_Unpriv                           \n"
                 " MPU_vTaskGetInfo_Priv:                                \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskGetInfoImpl                            \n"
                 " MPU_vTaskGetInfo_Unpriv:                              \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory"
@@ -242,12 +236,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGetIdleTaskHandle_Unpriv                 \n"
                 " MPU_xTaskGetIdleTaskHandle_Priv:                      \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGetIdleTaskHandleImpl                  \n"
                 " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory"
@@ -271,12 +264,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskSuspend_Unpriv                           \n"
                 " MPU_vTaskSuspend_Priv:                                \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskSuspendImpl                            \n"
                 " MPU_vTaskSuspend_Unpriv:                              \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory"
@@ -300,12 +292,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskResume_Unpriv                            \n"
                 " MPU_vTaskResume_Priv:                                 \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskResumeImpl                             \n"
                 " MPU_vTaskResume_Unpriv:                               \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskResume ) : "memory"
@@ -327,12 +318,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xTaskGetTickCount_Unpriv                      \n"
             " MPU_xTaskGetTickCount_Priv:                           \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xTaskGetTickCountImpl                       \n"
             " MPU_xTaskGetTickCount_Unpriv:                         \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory"
@@ -352,12 +342,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_uxTaskGetNumberOfTasks_Unpriv                 \n"
             " MPU_uxTaskGetNumberOfTasks_Priv:                      \n"
-            "     pop {r0}                                          \n"
             "     b MPU_uxTaskGetNumberOfTasksImpl                  \n"
             " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory"
@@ -379,12 +368,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGetRunTimeCounter_Unpriv                \n"
                 " MPU_ulTaskGetRunTimeCounter_Priv:                     \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGetRunTimeCounterImpl                 \n"
                 " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory"
@@ -408,12 +396,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGetRunTimePercent_Unpriv                \n"
                 " MPU_ulTaskGetRunTimePercent_Priv:                     \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGetRunTimePercentImpl                 \n"
                 " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory"
@@ -437,12 +424,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv            \n"
                 " MPU_ulTaskGetIdleRunTimePercent_Priv:                 \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGetIdleRunTimePercentImpl             \n"
                 " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory"
@@ -466,12 +452,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv            \n"
                 " MPU_ulTaskGetIdleRunTimeCounter_Priv:                 \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGetIdleRunTimeCounterImpl             \n"
                 " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory"
@@ -497,12 +482,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskSetApplicationTaskTag_Unpriv             \n"
                 " MPU_vTaskSetApplicationTaskTag_Priv:                  \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskSetApplicationTaskTagImpl              \n"
                 " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory"
@@ -526,12 +510,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGetApplicationTaskTag_Unpriv             \n"
                 " MPU_xTaskGetApplicationTaskTag_Priv:                  \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGetApplicationTaskTagImpl              \n"
                 " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory"
@@ -559,12 +542,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv      \n"
                 " MPU_vTaskSetThreadLocalStoragePointer_Priv:           \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskSetThreadLocalStoragePointerImpl       \n"
                 " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory"
@@ -590,12 +572,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv     \n"
                 " MPU_pvTaskGetThreadLocalStoragePointer_Priv:          \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_pvTaskGetThreadLocalStoragePointerImpl      \n"
                 " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory"
@@ -623,12 +604,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxTaskGetSystemState_Unpriv                   \n"
                 " MPU_uxTaskGetSystemState_Priv:                        \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxTaskGetSystemStateImpl                    \n"
                 " MPU_uxTaskGetSystemState_Unpriv:                      \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory"
@@ -652,12 +632,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxTaskGetStackHighWaterMark_Unpriv            \n"
                 " MPU_uxTaskGetStackHighWaterMark_Priv:                 \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxTaskGetStackHighWaterMarkImpl             \n"
                 " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory"
@@ -681,12 +660,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv           \n"
                 " MPU_uxTaskGetStackHighWaterMark2_Priv:                \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxTaskGetStackHighWaterMark2Impl            \n"
                 " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory"
@@ -710,12 +688,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGetCurrentTaskHandle_Unpriv              \n"
                 " MPU_xTaskGetCurrentTaskHandle_Priv:                   \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGetCurrentTaskHandleImpl               \n"
                 " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory"
@@ -739,12 +716,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGetSchedulerState_Unpriv                 \n"
                 " MPU_xTaskGetSchedulerState_Priv:                      \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGetSchedulerStateImpl                  \n"
                 " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory"
@@ -766,12 +742,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_vTaskSetTimeOutState_Unpriv                   \n"
             " MPU_vTaskSetTimeOutState_Priv:                        \n"
-            "     pop {r0}                                          \n"
             "     b MPU_vTaskSetTimeOutStateImpl                    \n"
             " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory"
@@ -793,12 +768,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xTaskCheckForTimeOut_Unpriv                   \n"
             " MPU_xTaskCheckForTimeOut_Priv:                        \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xTaskCheckForTimeOutImpl                    \n"
             " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory"
@@ -820,12 +794,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGenericNotify_Unpriv                     \n"
                 " MPU_xTaskGenericNotify_Priv:                          \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGenericNotifyImpl                      \n"
                 " MPU_xTaskGenericNotify_Unpriv:                        \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory"
@@ -849,12 +822,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGenericNotifyWait_Unpriv                 \n"
                 " MPU_xTaskGenericNotifyWait_Priv:                      \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGenericNotifyWaitImpl                  \n"
                 " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory"
@@ -882,12 +854,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGenericNotifyTake_Unpriv                \n"
                 " MPU_ulTaskGenericNotifyTake_Priv:                     \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGenericNotifyTakeImpl                 \n"
                 " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory"
@@ -913,12 +884,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGenericNotifyStateClear_Unpriv           \n"
                 " MPU_xTaskGenericNotifyStateClear_Priv:                \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGenericNotifyStateClearImpl            \n"
                 " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory"
@@ -946,12 +916,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGenericNotifyValueClear_Unpriv          \n"
                 " MPU_ulTaskGenericNotifyValueClear_Priv:               \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGenericNotifyValueClearImpl           \n"
                 " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory"
@@ -979,12 +948,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xQueueGenericSend_Unpriv                      \n"
             " MPU_xQueueGenericSend_Priv:                           \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xQueueGenericSendImpl                       \n"
             " MPU_xQueueGenericSend_Unpriv:                         \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory"
@@ -1004,12 +972,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_uxQueueMessagesWaiting_Unpriv                 \n"
             " MPU_uxQueueMessagesWaiting_Priv:                      \n"
-            "     pop {r0}                                          \n"
             "     b MPU_uxQueueMessagesWaitingImpl                  \n"
             " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory"
@@ -1029,12 +996,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_uxQueueSpacesAvailable_Unpriv                 \n"
             " MPU_uxQueueSpacesAvailable_Priv:                      \n"
-            "     pop {r0}                                          \n"
             "     b MPU_uxQueueSpacesAvailableImpl                  \n"
             " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory"
@@ -1058,12 +1024,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xQueueReceive_Unpriv                          \n"
             " MPU_xQueueReceive_Priv:                               \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xQueueReceiveImpl                           \n"
             " MPU_xQueueReceive_Unpriv:                             \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory"
@@ -1087,12 +1052,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xQueuePeek_Unpriv                             \n"
             " MPU_xQueuePeek_Priv:                                  \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xQueuePeekImpl                              \n"
             " MPU_xQueuePeek_Unpriv:                                \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory"
@@ -1114,12 +1078,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xQueueSemaphoreTake_Unpriv                    \n"
             " MPU_xQueueSemaphoreTake_Priv:                         \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xQueueSemaphoreTakeImpl                     \n"
             " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory"
@@ -1141,12 +1104,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xQueueGetMutexHolder_Unpriv                   \n"
                 " MPU_xQueueGetMutexHolder_Priv:                        \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xQueueGetMutexHolderImpl                    \n"
                 " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory"
@@ -1172,12 +1134,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xQueueTakeMutexRecursive_Unpriv               \n"
                 " MPU_xQueueTakeMutexRecursive_Priv:                    \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xQueueTakeMutexRecursiveImpl                \n"
                 " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory"
@@ -1201,12 +1162,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xQueueGiveMutexRecursive_Unpriv               \n"
                 " MPU_xQueueGiveMutexRecursive_Priv:                    \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xQueueGiveMutexRecursiveImpl                \n"
                 " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory"
@@ -1232,12 +1192,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xQueueSelectFromSet_Unpriv                    \n"
                 " MPU_xQueueSelectFromSet_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xQueueSelectFromSetImpl                     \n"
                 " MPU_xQueueSelectFromSet_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory"
@@ -1263,12 +1222,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xQueueAddToSet_Unpriv                         \n"
                 " MPU_xQueueAddToSet_Priv:                              \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xQueueAddToSetImpl                          \n"
                 " MPU_xQueueAddToSet_Unpriv:                            \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory"
@@ -1294,12 +1252,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vQueueAddToRegistry_Unpriv                    \n"
                 " MPU_vQueueAddToRegistry_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vQueueAddToRegistryImpl                     \n"
                 " MPU_vQueueAddToRegistry_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory"
@@ -1323,12 +1280,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vQueueUnregisterQueue_Unpriv                  \n"
                 " MPU_vQueueUnregisterQueue_Priv:                       \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vQueueUnregisterQueueImpl                   \n"
                 " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory"
@@ -1352,12 +1308,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_pcQueueGetName_Unpriv                         \n"
                 " MPU_pcQueueGetName_Priv:                              \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_pcQueueGetNameImpl                          \n"
                 " MPU_pcQueueGetName_Unpriv:                            \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory"
@@ -1381,12 +1336,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_pvTimerGetTimerID_Unpriv                      \n"
                 " MPU_pvTimerGetTimerID_Priv:                           \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_pvTimerGetTimerIDImpl                       \n"
                 " MPU_pvTimerGetTimerID_Unpriv:                         \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory"
@@ -1412,12 +1366,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTimerSetTimerID_Unpriv                       \n"
                 " MPU_vTimerSetTimerID_Priv:                            \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTimerSetTimerIDImpl                        \n"
                 " MPU_vTimerSetTimerID_Unpriv:                          \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory"
@@ -1441,12 +1394,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTimerIsTimerActive_Unpriv                    \n"
                 " MPU_xTimerIsTimerActive_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTimerIsTimerActiveImpl                     \n"
                 " MPU_xTimerIsTimerActive_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory"
@@ -1470,12 +1422,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv         \n"
                 " MPU_xTimerGetTimerDaemonTaskHandle_Priv:              \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTimerGetTimerDaemonTaskHandleImpl          \n"
                 " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory"
@@ -1493,20 +1444,19 @@
         {
             __asm volatile
             (
-                " .syntax unified                                               \n"
-                " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
-                "                                                               \n"
-                " push {r0}                                                     \n"
-                " mrs r0, control                                               \n"
-                " tst r0, #1                                                    \n"
-                " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
-                " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
-                "     pop {r0}                                                  \n"
-                "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
-                " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
-                "     pop {r0}                                                  \n"
-                "     svc %0                                                    \n"
-                "                                                               \n"
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGenericCommandFromTaskImpl          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xTimerGenericCommandFromTask_Unpriv           \n"
+                " MPU_xTimerGenericCommandFromTask_Priv:                \n"
+                "     b MPU_xTimerGenericCommandFromTaskImpl            \n"
+                " MPU_xTimerGenericCommandFromTask_Unpriv:              \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory"
             );
         }
@@ -1528,12 +1478,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_pcTimerGetName_Unpriv                         \n"
                 " MPU_pcTimerGetName_Priv:                              \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_pcTimerGetNameImpl                          \n"
                 " MPU_pcTimerGetName_Unpriv:                            \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory"
@@ -1559,12 +1508,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTimerSetReloadMode_Unpriv                    \n"
                 " MPU_vTimerSetReloadMode_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTimerSetReloadModeImpl                     \n"
                 " MPU_vTimerSetReloadMode_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory"
@@ -1588,12 +1536,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTimerGetReloadMode_Unpriv                    \n"
                 " MPU_xTimerGetReloadMode_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTimerGetReloadModeImpl                     \n"
                 " MPU_xTimerGetReloadMode_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory"
@@ -1617,12 +1564,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxTimerGetReloadMode_Unpriv                   \n"
                 " MPU_uxTimerGetReloadMode_Priv:                        \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxTimerGetReloadModeImpl                    \n"
                 " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory"
@@ -1646,12 +1592,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTimerGetPeriod_Unpriv                        \n"
                 " MPU_xTimerGetPeriod_Priv:                             \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTimerGetPeriodImpl                         \n"
                 " MPU_xTimerGetPeriod_Unpriv:                           \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory"
@@ -1675,12 +1620,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTimerGetExpiryTime_Unpriv                    \n"
                 " MPU_xTimerGetExpiryTime_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTimerGetExpiryTimeImpl                     \n"
                 " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory"
@@ -1702,12 +1646,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
             " MPU_xEventGroupWaitBits_Priv:                         \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xEventGroupWaitBitsImpl                     \n"
             " MPU_xEventGroupWaitBits_Unpriv:                       \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
@@ -1729,12 +1672,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xEventGroupClearBits_Unpriv                   \n"
             " MPU_xEventGroupClearBits_Priv:                        \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xEventGroupClearBitsImpl                    \n"
             " MPU_xEventGroupClearBits_Unpriv:                      \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
@@ -1756,12 +1698,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xEventGroupSetBits_Unpriv                     \n"
             " MPU_xEventGroupSetBits_Priv:                          \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xEventGroupSetBitsImpl                      \n"
             " MPU_xEventGroupSetBits_Unpriv:                        \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
@@ -1787,12 +1728,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xEventGroupSync_Unpriv                        \n"
             " MPU_xEventGroupSync_Priv:                             \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xEventGroupSyncImpl                         \n"
             " MPU_xEventGroupSync_Unpriv:                           \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
@@ -1814,12 +1754,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxEventGroupGetNumber_Unpriv                  \n"
                 " MPU_uxEventGroupGetNumber_Priv:                       \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxEventGroupGetNumberImpl                   \n"
                 " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory"
@@ -1845,12 +1784,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vEventGroupSetNumber_Unpriv                   \n"
                 " MPU_vEventGroupSetNumber_Priv:                        \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vEventGroupSetNumberImpl                    \n"
                 " MPU_vEventGroupSetNumber_Unpriv:                      \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory"
@@ -1878,12 +1816,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferSend_Unpriv                      \n"
             " MPU_xStreamBufferSend_Priv:                           \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferSendImpl                       \n"
             " MPU_xStreamBufferSend_Unpriv:                         \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
@@ -1909,12 +1846,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferReceive_Unpriv                   \n"
             " MPU_xStreamBufferReceive_Priv:                        \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferReceiveImpl                    \n"
             " MPU_xStreamBufferReceive_Unpriv:                      \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
@@ -1934,12 +1870,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
             " MPU_xStreamBufferIsFull_Priv:                         \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferIsFullImpl                     \n"
             " MPU_xStreamBufferIsFull_Unpriv:                       \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
@@ -1959,12 +1894,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
             " MPU_xStreamBufferIsEmpty_Priv:                        \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferIsEmptyImpl                    \n"
             " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
@@ -1984,12 +1918,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
             " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
             " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
@@ -2009,12 +1942,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
             " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferBytesAvailableImpl             \n"
             " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
@@ -2036,12 +1968,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
             " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
             " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
@@ -2061,12 +1992,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
             " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
             " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
diff --git a/portable/GCC/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.c
index 170d10fcc..4f66448f9 100644
--- a/portable/GCC/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.c
@@ -62,12 +62,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskDelayUntil_Unpriv                        \n"
                 " MPU_xTaskDelayUntil_Priv:                             \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskDelayUntilImpl                         \n"
                 " MPU_xTaskDelayUntil_Unpriv:                           \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory"
@@ -91,12 +90,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskAbortDelay_Unpriv                        \n"
                 " MPU_xTaskAbortDelay_Priv:                             \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskAbortDelayImpl                         \n"
                 " MPU_xTaskAbortDelay_Unpriv:                           \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory"
@@ -120,12 +118,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskDelay_Unpriv                             \n"
                 " MPU_vTaskDelay_Priv:                                  \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskDelayImpl                              \n"
                 " MPU_vTaskDelay_Unpriv:                                \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory"
@@ -149,12 +146,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxTaskPriorityGet_Unpriv                      \n"
                 " MPU_uxTaskPriorityGet_Priv:                           \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxTaskPriorityGetImpl                       \n"
                 " MPU_uxTaskPriorityGet_Unpriv:                         \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory"
@@ -178,12 +174,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_eTaskGetState_Unpriv                          \n"
                 " MPU_eTaskGetState_Priv:                               \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_eTaskGetStateImpl                           \n"
                 " MPU_eTaskGetState_Unpriv:                             \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory"
@@ -213,12 +208,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskGetInfo_Unpriv                           \n"
                 " MPU_vTaskGetInfo_Priv:                                \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskGetInfoImpl                            \n"
                 " MPU_vTaskGetInfo_Unpriv:                              \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory"
@@ -242,12 +236,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGetIdleTaskHandle_Unpriv                 \n"
                 " MPU_xTaskGetIdleTaskHandle_Priv:                      \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGetIdleTaskHandleImpl                  \n"
                 " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory"
@@ -271,12 +264,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskSuspend_Unpriv                           \n"
                 " MPU_vTaskSuspend_Priv:                                \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskSuspendImpl                            \n"
                 " MPU_vTaskSuspend_Unpriv:                              \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory"
@@ -300,12 +292,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskResume_Unpriv                            \n"
                 " MPU_vTaskResume_Priv:                                 \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskResumeImpl                             \n"
                 " MPU_vTaskResume_Unpriv:                               \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskResume ) : "memory"
@@ -327,12 +318,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xTaskGetTickCount_Unpriv                      \n"
             " MPU_xTaskGetTickCount_Priv:                           \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xTaskGetTickCountImpl                       \n"
             " MPU_xTaskGetTickCount_Unpriv:                         \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory"
@@ -352,12 +342,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_uxTaskGetNumberOfTasks_Unpriv                 \n"
             " MPU_uxTaskGetNumberOfTasks_Priv:                      \n"
-            "     pop {r0}                                          \n"
             "     b MPU_uxTaskGetNumberOfTasksImpl                  \n"
             " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory"
@@ -379,12 +368,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGetRunTimeCounter_Unpriv                \n"
                 " MPU_ulTaskGetRunTimeCounter_Priv:                     \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGetRunTimeCounterImpl                 \n"
                 " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory"
@@ -408,12 +396,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGetRunTimePercent_Unpriv                \n"
                 " MPU_ulTaskGetRunTimePercent_Priv:                     \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGetRunTimePercentImpl                 \n"
                 " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory"
@@ -437,12 +424,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv            \n"
                 " MPU_ulTaskGetIdleRunTimePercent_Priv:                 \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGetIdleRunTimePercentImpl             \n"
                 " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory"
@@ -466,12 +452,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv            \n"
                 " MPU_ulTaskGetIdleRunTimeCounter_Priv:                 \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGetIdleRunTimeCounterImpl             \n"
                 " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory"
@@ -497,12 +482,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskSetApplicationTaskTag_Unpriv             \n"
                 " MPU_vTaskSetApplicationTaskTag_Priv:                  \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskSetApplicationTaskTagImpl              \n"
                 " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory"
@@ -526,12 +510,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGetApplicationTaskTag_Unpriv             \n"
                 " MPU_xTaskGetApplicationTaskTag_Priv:                  \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGetApplicationTaskTagImpl              \n"
                 " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory"
@@ -559,12 +542,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv      \n"
                 " MPU_vTaskSetThreadLocalStoragePointer_Priv:           \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskSetThreadLocalStoragePointerImpl       \n"
                 " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory"
@@ -590,12 +572,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv     \n"
                 " MPU_pvTaskGetThreadLocalStoragePointer_Priv:          \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_pvTaskGetThreadLocalStoragePointerImpl      \n"
                 " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory"
@@ -623,12 +604,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxTaskGetSystemState_Unpriv                   \n"
                 " MPU_uxTaskGetSystemState_Priv:                        \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxTaskGetSystemStateImpl                    \n"
                 " MPU_uxTaskGetSystemState_Unpriv:                      \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory"
@@ -652,12 +632,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxTaskGetStackHighWaterMark_Unpriv            \n"
                 " MPU_uxTaskGetStackHighWaterMark_Priv:                 \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxTaskGetStackHighWaterMarkImpl             \n"
                 " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory"
@@ -681,12 +660,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv           \n"
                 " MPU_uxTaskGetStackHighWaterMark2_Priv:                \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxTaskGetStackHighWaterMark2Impl            \n"
                 " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory"
@@ -710,12 +688,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGetCurrentTaskHandle_Unpriv              \n"
                 " MPU_xTaskGetCurrentTaskHandle_Priv:                   \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGetCurrentTaskHandleImpl               \n"
                 " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory"
@@ -739,12 +716,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGetSchedulerState_Unpriv                 \n"
                 " MPU_xTaskGetSchedulerState_Priv:                      \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGetSchedulerStateImpl                  \n"
                 " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory"
@@ -766,12 +742,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_vTaskSetTimeOutState_Unpriv                   \n"
             " MPU_vTaskSetTimeOutState_Priv:                        \n"
-            "     pop {r0}                                          \n"
             "     b MPU_vTaskSetTimeOutStateImpl                    \n"
             " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory"
@@ -793,12 +768,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xTaskCheckForTimeOut_Unpriv                   \n"
             " MPU_xTaskCheckForTimeOut_Priv:                        \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xTaskCheckForTimeOutImpl                    \n"
             " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory"
@@ -820,12 +794,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGenericNotify_Unpriv                     \n"
                 " MPU_xTaskGenericNotify_Priv:                          \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGenericNotifyImpl                      \n"
                 " MPU_xTaskGenericNotify_Unpriv:                        \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory"
@@ -849,12 +822,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGenericNotifyWait_Unpriv                 \n"
                 " MPU_xTaskGenericNotifyWait_Priv:                      \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGenericNotifyWaitImpl                  \n"
                 " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory"
@@ -882,12 +854,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGenericNotifyTake_Unpriv                \n"
                 " MPU_ulTaskGenericNotifyTake_Priv:                     \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGenericNotifyTakeImpl                 \n"
                 " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory"
@@ -913,12 +884,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGenericNotifyStateClear_Unpriv           \n"
                 " MPU_xTaskGenericNotifyStateClear_Priv:                \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGenericNotifyStateClearImpl            \n"
                 " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory"
@@ -946,12 +916,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGenericNotifyValueClear_Unpriv          \n"
                 " MPU_ulTaskGenericNotifyValueClear_Priv:               \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGenericNotifyValueClearImpl           \n"
                 " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory"
@@ -979,12 +948,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xQueueGenericSend_Unpriv                      \n"
             " MPU_xQueueGenericSend_Priv:                           \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xQueueGenericSendImpl                       \n"
             " MPU_xQueueGenericSend_Unpriv:                         \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory"
@@ -1004,12 +972,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_uxQueueMessagesWaiting_Unpriv                 \n"
             " MPU_uxQueueMessagesWaiting_Priv:                      \n"
-            "     pop {r0}                                          \n"
             "     b MPU_uxQueueMessagesWaitingImpl                  \n"
             " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory"
@@ -1029,12 +996,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_uxQueueSpacesAvailable_Unpriv                 \n"
             " MPU_uxQueueSpacesAvailable_Priv:                      \n"
-            "     pop {r0}                                          \n"
             "     b MPU_uxQueueSpacesAvailableImpl                  \n"
             " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory"
@@ -1058,12 +1024,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xQueueReceive_Unpriv                          \n"
             " MPU_xQueueReceive_Priv:                               \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xQueueReceiveImpl                           \n"
             " MPU_xQueueReceive_Unpriv:                             \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory"
@@ -1087,12 +1052,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xQueuePeek_Unpriv                             \n"
             " MPU_xQueuePeek_Priv:                                  \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xQueuePeekImpl                              \n"
             " MPU_xQueuePeek_Unpriv:                                \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory"
@@ -1114,12 +1078,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xQueueSemaphoreTake_Unpriv                    \n"
             " MPU_xQueueSemaphoreTake_Priv:                         \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xQueueSemaphoreTakeImpl                     \n"
             " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory"
@@ -1141,12 +1104,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xQueueGetMutexHolder_Unpriv                   \n"
                 " MPU_xQueueGetMutexHolder_Priv:                        \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xQueueGetMutexHolderImpl                    \n"
                 " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory"
@@ -1172,12 +1134,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xQueueTakeMutexRecursive_Unpriv               \n"
                 " MPU_xQueueTakeMutexRecursive_Priv:                    \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xQueueTakeMutexRecursiveImpl                \n"
                 " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory"
@@ -1201,12 +1162,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xQueueGiveMutexRecursive_Unpriv               \n"
                 " MPU_xQueueGiveMutexRecursive_Priv:                    \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xQueueGiveMutexRecursiveImpl                \n"
                 " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory"
@@ -1232,12 +1192,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xQueueSelectFromSet_Unpriv                    \n"
                 " MPU_xQueueSelectFromSet_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xQueueSelectFromSetImpl                     \n"
                 " MPU_xQueueSelectFromSet_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory"
@@ -1263,12 +1222,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xQueueAddToSet_Unpriv                         \n"
                 " MPU_xQueueAddToSet_Priv:                              \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xQueueAddToSetImpl                          \n"
                 " MPU_xQueueAddToSet_Unpriv:                            \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory"
@@ -1294,12 +1252,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vQueueAddToRegistry_Unpriv                    \n"
                 " MPU_vQueueAddToRegistry_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vQueueAddToRegistryImpl                     \n"
                 " MPU_vQueueAddToRegistry_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory"
@@ -1323,12 +1280,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vQueueUnregisterQueue_Unpriv                  \n"
                 " MPU_vQueueUnregisterQueue_Priv:                       \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vQueueUnregisterQueueImpl                   \n"
                 " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory"
@@ -1352,12 +1308,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_pcQueueGetName_Unpriv                         \n"
                 " MPU_pcQueueGetName_Priv:                              \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_pcQueueGetNameImpl                          \n"
                 " MPU_pcQueueGetName_Unpriv:                            \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory"
@@ -1381,12 +1336,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_pvTimerGetTimerID_Unpriv                      \n"
                 " MPU_pvTimerGetTimerID_Priv:                           \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_pvTimerGetTimerIDImpl                       \n"
                 " MPU_pvTimerGetTimerID_Unpriv:                         \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory"
@@ -1412,12 +1366,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTimerSetTimerID_Unpriv                       \n"
                 " MPU_vTimerSetTimerID_Priv:                            \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTimerSetTimerIDImpl                        \n"
                 " MPU_vTimerSetTimerID_Unpriv:                          \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory"
@@ -1441,12 +1394,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTimerIsTimerActive_Unpriv                    \n"
                 " MPU_xTimerIsTimerActive_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTimerIsTimerActiveImpl                     \n"
                 " MPU_xTimerIsTimerActive_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory"
@@ -1470,12 +1422,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv         \n"
                 " MPU_xTimerGetTimerDaemonTaskHandle_Priv:              \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTimerGetTimerDaemonTaskHandleImpl          \n"
                 " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory"
@@ -1493,20 +1444,19 @@
         {
             __asm volatile
             (
-                " .syntax unified                                               \n"
-                " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
-                "                                                               \n"
-                " push {r0}                                                     \n"
-                " mrs r0, control                                               \n"
-                " tst r0, #1                                                    \n"
-                " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
-                " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
-                "     pop {r0}                                                  \n"
-                "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
-                " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
-                "     pop {r0}                                                  \n"
-                "     svc %0                                                    \n"
-                "                                                               \n"
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGenericCommandFromTaskImpl          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xTimerGenericCommandFromTask_Unpriv           \n"
+                " MPU_xTimerGenericCommandFromTask_Priv:                \n"
+                "     b MPU_xTimerGenericCommandFromTaskImpl            \n"
+                " MPU_xTimerGenericCommandFromTask_Unpriv:              \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory"
             );
         }
@@ -1528,12 +1478,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_pcTimerGetName_Unpriv                         \n"
                 " MPU_pcTimerGetName_Priv:                              \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_pcTimerGetNameImpl                          \n"
                 " MPU_pcTimerGetName_Unpriv:                            \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory"
@@ -1559,12 +1508,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTimerSetReloadMode_Unpriv                    \n"
                 " MPU_vTimerSetReloadMode_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTimerSetReloadModeImpl                     \n"
                 " MPU_vTimerSetReloadMode_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory"
@@ -1588,12 +1536,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTimerGetReloadMode_Unpriv                    \n"
                 " MPU_xTimerGetReloadMode_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTimerGetReloadModeImpl                     \n"
                 " MPU_xTimerGetReloadMode_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory"
@@ -1617,12 +1564,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxTimerGetReloadMode_Unpriv                   \n"
                 " MPU_uxTimerGetReloadMode_Priv:                        \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxTimerGetReloadModeImpl                    \n"
                 " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory"
@@ -1646,12 +1592,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTimerGetPeriod_Unpriv                        \n"
                 " MPU_xTimerGetPeriod_Priv:                             \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTimerGetPeriodImpl                         \n"
                 " MPU_xTimerGetPeriod_Unpriv:                           \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory"
@@ -1675,12 +1620,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTimerGetExpiryTime_Unpriv                    \n"
                 " MPU_xTimerGetExpiryTime_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTimerGetExpiryTimeImpl                     \n"
                 " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory"
@@ -1702,12 +1646,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
             " MPU_xEventGroupWaitBits_Priv:                         \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xEventGroupWaitBitsImpl                     \n"
             " MPU_xEventGroupWaitBits_Unpriv:                       \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
@@ -1729,12 +1672,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xEventGroupClearBits_Unpriv                   \n"
             " MPU_xEventGroupClearBits_Priv:                        \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xEventGroupClearBitsImpl                    \n"
             " MPU_xEventGroupClearBits_Unpriv:                      \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
@@ -1756,12 +1698,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xEventGroupSetBits_Unpriv                     \n"
             " MPU_xEventGroupSetBits_Priv:                          \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xEventGroupSetBitsImpl                      \n"
             " MPU_xEventGroupSetBits_Unpriv:                        \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
@@ -1787,12 +1728,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xEventGroupSync_Unpriv                        \n"
             " MPU_xEventGroupSync_Priv:                             \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xEventGroupSyncImpl                         \n"
             " MPU_xEventGroupSync_Unpriv:                           \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
@@ -1814,12 +1754,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxEventGroupGetNumber_Unpriv                  \n"
                 " MPU_uxEventGroupGetNumber_Priv:                       \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxEventGroupGetNumberImpl                   \n"
                 " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory"
@@ -1845,12 +1784,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vEventGroupSetNumber_Unpriv                   \n"
                 " MPU_vEventGroupSetNumber_Priv:                        \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vEventGroupSetNumberImpl                    \n"
                 " MPU_vEventGroupSetNumber_Unpriv:                      \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory"
@@ -1878,12 +1816,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferSend_Unpriv                      \n"
             " MPU_xStreamBufferSend_Priv:                           \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferSendImpl                       \n"
             " MPU_xStreamBufferSend_Unpriv:                         \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
@@ -1909,12 +1846,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferReceive_Unpriv                   \n"
             " MPU_xStreamBufferReceive_Priv:                        \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferReceiveImpl                    \n"
             " MPU_xStreamBufferReceive_Unpriv:                      \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
@@ -1934,12 +1870,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
             " MPU_xStreamBufferIsFull_Priv:                         \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferIsFullImpl                     \n"
             " MPU_xStreamBufferIsFull_Unpriv:                       \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
@@ -1959,12 +1894,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
             " MPU_xStreamBufferIsEmpty_Priv:                        \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferIsEmptyImpl                    \n"
             " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
@@ -1984,12 +1918,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
             " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
             " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
@@ -2009,12 +1942,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
             " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferBytesAvailableImpl             \n"
             " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
@@ -2036,12 +1968,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
             " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
             " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
@@ -2061,12 +1992,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
             " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
             " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.c
index 170d10fcc..4f66448f9 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.c
@@ -62,12 +62,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskDelayUntil_Unpriv                        \n"
                 " MPU_xTaskDelayUntil_Priv:                             \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskDelayUntilImpl                         \n"
                 " MPU_xTaskDelayUntil_Unpriv:                           \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory"
@@ -91,12 +90,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskAbortDelay_Unpriv                        \n"
                 " MPU_xTaskAbortDelay_Priv:                             \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskAbortDelayImpl                         \n"
                 " MPU_xTaskAbortDelay_Unpriv:                           \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory"
@@ -120,12 +118,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskDelay_Unpriv                             \n"
                 " MPU_vTaskDelay_Priv:                                  \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskDelayImpl                              \n"
                 " MPU_vTaskDelay_Unpriv:                                \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory"
@@ -149,12 +146,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxTaskPriorityGet_Unpriv                      \n"
                 " MPU_uxTaskPriorityGet_Priv:                           \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxTaskPriorityGetImpl                       \n"
                 " MPU_uxTaskPriorityGet_Unpriv:                         \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory"
@@ -178,12 +174,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_eTaskGetState_Unpriv                          \n"
                 " MPU_eTaskGetState_Priv:                               \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_eTaskGetStateImpl                           \n"
                 " MPU_eTaskGetState_Unpriv:                             \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory"
@@ -213,12 +208,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskGetInfo_Unpriv                           \n"
                 " MPU_vTaskGetInfo_Priv:                                \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskGetInfoImpl                            \n"
                 " MPU_vTaskGetInfo_Unpriv:                              \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory"
@@ -242,12 +236,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGetIdleTaskHandle_Unpriv                 \n"
                 " MPU_xTaskGetIdleTaskHandle_Priv:                      \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGetIdleTaskHandleImpl                  \n"
                 " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory"
@@ -271,12 +264,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskSuspend_Unpriv                           \n"
                 " MPU_vTaskSuspend_Priv:                                \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskSuspendImpl                            \n"
                 " MPU_vTaskSuspend_Unpriv:                              \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory"
@@ -300,12 +292,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskResume_Unpriv                            \n"
                 " MPU_vTaskResume_Priv:                                 \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskResumeImpl                             \n"
                 " MPU_vTaskResume_Unpriv:                               \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskResume ) : "memory"
@@ -327,12 +318,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xTaskGetTickCount_Unpriv                      \n"
             " MPU_xTaskGetTickCount_Priv:                           \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xTaskGetTickCountImpl                       \n"
             " MPU_xTaskGetTickCount_Unpriv:                         \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory"
@@ -352,12 +342,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_uxTaskGetNumberOfTasks_Unpriv                 \n"
             " MPU_uxTaskGetNumberOfTasks_Priv:                      \n"
-            "     pop {r0}                                          \n"
             "     b MPU_uxTaskGetNumberOfTasksImpl                  \n"
             " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory"
@@ -379,12 +368,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGetRunTimeCounter_Unpriv                \n"
                 " MPU_ulTaskGetRunTimeCounter_Priv:                     \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGetRunTimeCounterImpl                 \n"
                 " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory"
@@ -408,12 +396,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGetRunTimePercent_Unpriv                \n"
                 " MPU_ulTaskGetRunTimePercent_Priv:                     \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGetRunTimePercentImpl                 \n"
                 " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory"
@@ -437,12 +424,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv            \n"
                 " MPU_ulTaskGetIdleRunTimePercent_Priv:                 \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGetIdleRunTimePercentImpl             \n"
                 " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory"
@@ -466,12 +452,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv            \n"
                 " MPU_ulTaskGetIdleRunTimeCounter_Priv:                 \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGetIdleRunTimeCounterImpl             \n"
                 " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory"
@@ -497,12 +482,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskSetApplicationTaskTag_Unpriv             \n"
                 " MPU_vTaskSetApplicationTaskTag_Priv:                  \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskSetApplicationTaskTagImpl              \n"
                 " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory"
@@ -526,12 +510,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGetApplicationTaskTag_Unpriv             \n"
                 " MPU_xTaskGetApplicationTaskTag_Priv:                  \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGetApplicationTaskTagImpl              \n"
                 " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory"
@@ -559,12 +542,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv      \n"
                 " MPU_vTaskSetThreadLocalStoragePointer_Priv:           \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskSetThreadLocalStoragePointerImpl       \n"
                 " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory"
@@ -590,12 +572,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv     \n"
                 " MPU_pvTaskGetThreadLocalStoragePointer_Priv:          \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_pvTaskGetThreadLocalStoragePointerImpl      \n"
                 " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory"
@@ -623,12 +604,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxTaskGetSystemState_Unpriv                   \n"
                 " MPU_uxTaskGetSystemState_Priv:                        \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxTaskGetSystemStateImpl                    \n"
                 " MPU_uxTaskGetSystemState_Unpriv:                      \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory"
@@ -652,12 +632,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxTaskGetStackHighWaterMark_Unpriv            \n"
                 " MPU_uxTaskGetStackHighWaterMark_Priv:                 \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxTaskGetStackHighWaterMarkImpl             \n"
                 " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory"
@@ -681,12 +660,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv           \n"
                 " MPU_uxTaskGetStackHighWaterMark2_Priv:                \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxTaskGetStackHighWaterMark2Impl            \n"
                 " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory"
@@ -710,12 +688,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGetCurrentTaskHandle_Unpriv              \n"
                 " MPU_xTaskGetCurrentTaskHandle_Priv:                   \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGetCurrentTaskHandleImpl               \n"
                 " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory"
@@ -739,12 +716,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGetSchedulerState_Unpriv                 \n"
                 " MPU_xTaskGetSchedulerState_Priv:                      \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGetSchedulerStateImpl                  \n"
                 " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory"
@@ -766,12 +742,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_vTaskSetTimeOutState_Unpriv                   \n"
             " MPU_vTaskSetTimeOutState_Priv:                        \n"
-            "     pop {r0}                                          \n"
             "     b MPU_vTaskSetTimeOutStateImpl                    \n"
             " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory"
@@ -793,12 +768,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xTaskCheckForTimeOut_Unpriv                   \n"
             " MPU_xTaskCheckForTimeOut_Priv:                        \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xTaskCheckForTimeOutImpl                    \n"
             " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory"
@@ -820,12 +794,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGenericNotify_Unpriv                     \n"
                 " MPU_xTaskGenericNotify_Priv:                          \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGenericNotifyImpl                      \n"
                 " MPU_xTaskGenericNotify_Unpriv:                        \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory"
@@ -849,12 +822,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGenericNotifyWait_Unpriv                 \n"
                 " MPU_xTaskGenericNotifyWait_Priv:                      \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGenericNotifyWaitImpl                  \n"
                 " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory"
@@ -882,12 +854,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGenericNotifyTake_Unpriv                \n"
                 " MPU_ulTaskGenericNotifyTake_Priv:                     \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGenericNotifyTakeImpl                 \n"
                 " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory"
@@ -913,12 +884,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGenericNotifyStateClear_Unpriv           \n"
                 " MPU_xTaskGenericNotifyStateClear_Priv:                \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGenericNotifyStateClearImpl            \n"
                 " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory"
@@ -946,12 +916,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGenericNotifyValueClear_Unpriv          \n"
                 " MPU_ulTaskGenericNotifyValueClear_Priv:               \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGenericNotifyValueClearImpl           \n"
                 " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory"
@@ -979,12 +948,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xQueueGenericSend_Unpriv                      \n"
             " MPU_xQueueGenericSend_Priv:                           \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xQueueGenericSendImpl                       \n"
             " MPU_xQueueGenericSend_Unpriv:                         \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory"
@@ -1004,12 +972,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_uxQueueMessagesWaiting_Unpriv                 \n"
             " MPU_uxQueueMessagesWaiting_Priv:                      \n"
-            "     pop {r0}                                          \n"
             "     b MPU_uxQueueMessagesWaitingImpl                  \n"
             " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory"
@@ -1029,12 +996,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_uxQueueSpacesAvailable_Unpriv                 \n"
             " MPU_uxQueueSpacesAvailable_Priv:                      \n"
-            "     pop {r0}                                          \n"
             "     b MPU_uxQueueSpacesAvailableImpl                  \n"
             " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory"
@@ -1058,12 +1024,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xQueueReceive_Unpriv                          \n"
             " MPU_xQueueReceive_Priv:                               \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xQueueReceiveImpl                           \n"
             " MPU_xQueueReceive_Unpriv:                             \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory"
@@ -1087,12 +1052,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xQueuePeek_Unpriv                             \n"
             " MPU_xQueuePeek_Priv:                                  \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xQueuePeekImpl                              \n"
             " MPU_xQueuePeek_Unpriv:                                \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory"
@@ -1114,12 +1078,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xQueueSemaphoreTake_Unpriv                    \n"
             " MPU_xQueueSemaphoreTake_Priv:                         \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xQueueSemaphoreTakeImpl                     \n"
             " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory"
@@ -1141,12 +1104,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xQueueGetMutexHolder_Unpriv                   \n"
                 " MPU_xQueueGetMutexHolder_Priv:                        \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xQueueGetMutexHolderImpl                    \n"
                 " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory"
@@ -1172,12 +1134,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xQueueTakeMutexRecursive_Unpriv               \n"
                 " MPU_xQueueTakeMutexRecursive_Priv:                    \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xQueueTakeMutexRecursiveImpl                \n"
                 " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory"
@@ -1201,12 +1162,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xQueueGiveMutexRecursive_Unpriv               \n"
                 " MPU_xQueueGiveMutexRecursive_Priv:                    \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xQueueGiveMutexRecursiveImpl                \n"
                 " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory"
@@ -1232,12 +1192,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xQueueSelectFromSet_Unpriv                    \n"
                 " MPU_xQueueSelectFromSet_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xQueueSelectFromSetImpl                     \n"
                 " MPU_xQueueSelectFromSet_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory"
@@ -1263,12 +1222,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xQueueAddToSet_Unpriv                         \n"
                 " MPU_xQueueAddToSet_Priv:                              \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xQueueAddToSetImpl                          \n"
                 " MPU_xQueueAddToSet_Unpriv:                            \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory"
@@ -1294,12 +1252,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vQueueAddToRegistry_Unpriv                    \n"
                 " MPU_vQueueAddToRegistry_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vQueueAddToRegistryImpl                     \n"
                 " MPU_vQueueAddToRegistry_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory"
@@ -1323,12 +1280,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vQueueUnregisterQueue_Unpriv                  \n"
                 " MPU_vQueueUnregisterQueue_Priv:                       \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vQueueUnregisterQueueImpl                   \n"
                 " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory"
@@ -1352,12 +1308,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_pcQueueGetName_Unpriv                         \n"
                 " MPU_pcQueueGetName_Priv:                              \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_pcQueueGetNameImpl                          \n"
                 " MPU_pcQueueGetName_Unpriv:                            \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory"
@@ -1381,12 +1336,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_pvTimerGetTimerID_Unpriv                      \n"
                 " MPU_pvTimerGetTimerID_Priv:                           \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_pvTimerGetTimerIDImpl                       \n"
                 " MPU_pvTimerGetTimerID_Unpriv:                         \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory"
@@ -1412,12 +1366,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTimerSetTimerID_Unpriv                       \n"
                 " MPU_vTimerSetTimerID_Priv:                            \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTimerSetTimerIDImpl                        \n"
                 " MPU_vTimerSetTimerID_Unpriv:                          \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory"
@@ -1441,12 +1394,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTimerIsTimerActive_Unpriv                    \n"
                 " MPU_xTimerIsTimerActive_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTimerIsTimerActiveImpl                     \n"
                 " MPU_xTimerIsTimerActive_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory"
@@ -1470,12 +1422,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv         \n"
                 " MPU_xTimerGetTimerDaemonTaskHandle_Priv:              \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTimerGetTimerDaemonTaskHandleImpl          \n"
                 " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory"
@@ -1493,20 +1444,19 @@
         {
             __asm volatile
             (
-                " .syntax unified                                               \n"
-                " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
-                "                                                               \n"
-                " push {r0}                                                     \n"
-                " mrs r0, control                                               \n"
-                " tst r0, #1                                                    \n"
-                " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
-                " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
-                "     pop {r0}                                                  \n"
-                "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
-                " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
-                "     pop {r0}                                                  \n"
-                "     svc %0                                                    \n"
-                "                                                               \n"
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGenericCommandFromTaskImpl          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xTimerGenericCommandFromTask_Unpriv           \n"
+                " MPU_xTimerGenericCommandFromTask_Priv:                \n"
+                "     b MPU_xTimerGenericCommandFromTaskImpl            \n"
+                " MPU_xTimerGenericCommandFromTask_Unpriv:              \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory"
             );
         }
@@ -1528,12 +1478,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_pcTimerGetName_Unpriv                         \n"
                 " MPU_pcTimerGetName_Priv:                              \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_pcTimerGetNameImpl                          \n"
                 " MPU_pcTimerGetName_Unpriv:                            \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory"
@@ -1559,12 +1508,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTimerSetReloadMode_Unpriv                    \n"
                 " MPU_vTimerSetReloadMode_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTimerSetReloadModeImpl                     \n"
                 " MPU_vTimerSetReloadMode_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory"
@@ -1588,12 +1536,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTimerGetReloadMode_Unpriv                    \n"
                 " MPU_xTimerGetReloadMode_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTimerGetReloadModeImpl                     \n"
                 " MPU_xTimerGetReloadMode_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory"
@@ -1617,12 +1564,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxTimerGetReloadMode_Unpriv                   \n"
                 " MPU_uxTimerGetReloadMode_Priv:                        \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxTimerGetReloadModeImpl                    \n"
                 " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory"
@@ -1646,12 +1592,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTimerGetPeriod_Unpriv                        \n"
                 " MPU_xTimerGetPeriod_Priv:                             \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTimerGetPeriodImpl                         \n"
                 " MPU_xTimerGetPeriod_Unpriv:                           \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory"
@@ -1675,12 +1620,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTimerGetExpiryTime_Unpriv                    \n"
                 " MPU_xTimerGetExpiryTime_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTimerGetExpiryTimeImpl                     \n"
                 " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory"
@@ -1702,12 +1646,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
             " MPU_xEventGroupWaitBits_Priv:                         \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xEventGroupWaitBitsImpl                     \n"
             " MPU_xEventGroupWaitBits_Unpriv:                       \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
@@ -1729,12 +1672,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xEventGroupClearBits_Unpriv                   \n"
             " MPU_xEventGroupClearBits_Priv:                        \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xEventGroupClearBitsImpl                    \n"
             " MPU_xEventGroupClearBits_Unpriv:                      \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
@@ -1756,12 +1698,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xEventGroupSetBits_Unpriv                     \n"
             " MPU_xEventGroupSetBits_Priv:                          \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xEventGroupSetBitsImpl                      \n"
             " MPU_xEventGroupSetBits_Unpriv:                        \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
@@ -1787,12 +1728,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xEventGroupSync_Unpriv                        \n"
             " MPU_xEventGroupSync_Priv:                             \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xEventGroupSyncImpl                         \n"
             " MPU_xEventGroupSync_Unpriv:                           \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
@@ -1814,12 +1754,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxEventGroupGetNumber_Unpriv                  \n"
                 " MPU_uxEventGroupGetNumber_Priv:                       \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxEventGroupGetNumberImpl                   \n"
                 " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory"
@@ -1845,12 +1784,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vEventGroupSetNumber_Unpriv                   \n"
                 " MPU_vEventGroupSetNumber_Priv:                        \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vEventGroupSetNumberImpl                    \n"
                 " MPU_vEventGroupSetNumber_Unpriv:                      \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory"
@@ -1878,12 +1816,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferSend_Unpriv                      \n"
             " MPU_xStreamBufferSend_Priv:                           \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferSendImpl                       \n"
             " MPU_xStreamBufferSend_Unpriv:                         \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
@@ -1909,12 +1846,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferReceive_Unpriv                   \n"
             " MPU_xStreamBufferReceive_Priv:                        \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferReceiveImpl                    \n"
             " MPU_xStreamBufferReceive_Unpriv:                      \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
@@ -1934,12 +1870,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
             " MPU_xStreamBufferIsFull_Priv:                         \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferIsFullImpl                     \n"
             " MPU_xStreamBufferIsFull_Unpriv:                       \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
@@ -1959,12 +1894,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
             " MPU_xStreamBufferIsEmpty_Priv:                        \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferIsEmptyImpl                    \n"
             " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
@@ -1984,12 +1918,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
             " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
             " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
@@ -2009,12 +1942,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
             " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferBytesAvailableImpl             \n"
             " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
@@ -2036,12 +1968,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
             " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
             " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
@@ -2061,12 +1992,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
             " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
             " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
diff --git a/portable/GCC/ARM_CM3_MPU/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM3_MPU/mpu_wrappers_v2_asm.c
index c95f72e8e..feb3e3426 100644
--- a/portable/GCC/ARM_CM3_MPU/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM3_MPU/mpu_wrappers_v2_asm.c
@@ -62,12 +62,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskDelayUntil_Unpriv                        \n"
                 " MPU_xTaskDelayUntil_Priv:                             \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskDelayUntilImpl                         \n"
                 " MPU_xTaskDelayUntil_Unpriv:                           \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory"
@@ -91,12 +90,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskAbortDelay_Unpriv                        \n"
                 " MPU_xTaskAbortDelay_Priv:                             \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskAbortDelayImpl                         \n"
                 " MPU_xTaskAbortDelay_Unpriv:                           \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory"
@@ -120,12 +118,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskDelay_Unpriv                             \n"
                 " MPU_vTaskDelay_Priv:                                  \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskDelayImpl                              \n"
                 " MPU_vTaskDelay_Unpriv:                                \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory"
@@ -149,12 +146,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxTaskPriorityGet_Unpriv                      \n"
                 " MPU_uxTaskPriorityGet_Priv:                           \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxTaskPriorityGetImpl                       \n"
                 " MPU_uxTaskPriorityGet_Unpriv:                         \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory"
@@ -178,12 +174,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_eTaskGetState_Unpriv                          \n"
                 " MPU_eTaskGetState_Priv:                               \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_eTaskGetStateImpl                           \n"
                 " MPU_eTaskGetState_Unpriv:                             \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory"
@@ -213,12 +208,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskGetInfo_Unpriv                           \n"
                 " MPU_vTaskGetInfo_Priv:                                \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskGetInfoImpl                            \n"
                 " MPU_vTaskGetInfo_Unpriv:                              \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory"
@@ -242,12 +236,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGetIdleTaskHandle_Unpriv                 \n"
                 " MPU_xTaskGetIdleTaskHandle_Priv:                      \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGetIdleTaskHandleImpl                  \n"
                 " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory"
@@ -271,12 +264,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskSuspend_Unpriv                           \n"
                 " MPU_vTaskSuspend_Priv:                                \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskSuspendImpl                            \n"
                 " MPU_vTaskSuspend_Unpriv:                              \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory"
@@ -300,12 +292,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskResume_Unpriv                            \n"
                 " MPU_vTaskResume_Priv:                                 \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskResumeImpl                             \n"
                 " MPU_vTaskResume_Unpriv:                               \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskResume ) : "memory"
@@ -327,12 +318,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xTaskGetTickCount_Unpriv                      \n"
             " MPU_xTaskGetTickCount_Priv:                           \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xTaskGetTickCountImpl                       \n"
             " MPU_xTaskGetTickCount_Unpriv:                         \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory"
@@ -352,12 +342,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_uxTaskGetNumberOfTasks_Unpriv                 \n"
             " MPU_uxTaskGetNumberOfTasks_Priv:                      \n"
-            "     pop {r0}                                          \n"
             "     b MPU_uxTaskGetNumberOfTasksImpl                  \n"
             " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory"
@@ -379,12 +368,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGetRunTimeCounter_Unpriv                \n"
                 " MPU_ulTaskGetRunTimeCounter_Priv:                     \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGetRunTimeCounterImpl                 \n"
                 " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory"
@@ -408,12 +396,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGetRunTimePercent_Unpriv                \n"
                 " MPU_ulTaskGetRunTimePercent_Priv:                     \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGetRunTimePercentImpl                 \n"
                 " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory"
@@ -437,12 +424,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv            \n"
                 " MPU_ulTaskGetIdleRunTimePercent_Priv:                 \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGetIdleRunTimePercentImpl             \n"
                 " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory"
@@ -466,12 +452,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv            \n"
                 " MPU_ulTaskGetIdleRunTimeCounter_Priv:                 \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGetIdleRunTimeCounterImpl             \n"
                 " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory"
@@ -497,12 +482,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskSetApplicationTaskTag_Unpriv             \n"
                 " MPU_vTaskSetApplicationTaskTag_Priv:                  \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskSetApplicationTaskTagImpl              \n"
                 " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory"
@@ -526,12 +510,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGetApplicationTaskTag_Unpriv             \n"
                 " MPU_xTaskGetApplicationTaskTag_Priv:                  \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGetApplicationTaskTagImpl              \n"
                 " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory"
@@ -559,12 +542,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv      \n"
                 " MPU_vTaskSetThreadLocalStoragePointer_Priv:           \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskSetThreadLocalStoragePointerImpl       \n"
                 " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory"
@@ -590,12 +572,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv     \n"
                 " MPU_pvTaskGetThreadLocalStoragePointer_Priv:          \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_pvTaskGetThreadLocalStoragePointerImpl      \n"
                 " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory"
@@ -623,12 +604,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxTaskGetSystemState_Unpriv                   \n"
                 " MPU_uxTaskGetSystemState_Priv:                        \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxTaskGetSystemStateImpl                    \n"
                 " MPU_uxTaskGetSystemState_Unpriv:                      \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory"
@@ -652,12 +632,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxTaskGetStackHighWaterMark_Unpriv            \n"
                 " MPU_uxTaskGetStackHighWaterMark_Priv:                 \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxTaskGetStackHighWaterMarkImpl             \n"
                 " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory"
@@ -681,12 +660,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv           \n"
                 " MPU_uxTaskGetStackHighWaterMark2_Priv:                \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxTaskGetStackHighWaterMark2Impl            \n"
                 " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory"
@@ -710,12 +688,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGetCurrentTaskHandle_Unpriv              \n"
                 " MPU_xTaskGetCurrentTaskHandle_Priv:                   \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGetCurrentTaskHandleImpl               \n"
                 " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory"
@@ -739,12 +716,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGetSchedulerState_Unpriv                 \n"
                 " MPU_xTaskGetSchedulerState_Priv:                      \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGetSchedulerStateImpl                  \n"
                 " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory"
@@ -766,12 +742,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_vTaskSetTimeOutState_Unpriv                   \n"
             " MPU_vTaskSetTimeOutState_Priv:                        \n"
-            "     pop {r0}                                          \n"
             "     b MPU_vTaskSetTimeOutStateImpl                    \n"
             " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory"
@@ -793,12 +768,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xTaskCheckForTimeOut_Unpriv                   \n"
             " MPU_xTaskCheckForTimeOut_Priv:                        \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xTaskCheckForTimeOutImpl                    \n"
             " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory"
@@ -820,12 +794,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGenericNotify_Unpriv                     \n"
                 " MPU_xTaskGenericNotify_Priv:                          \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGenericNotifyImpl                      \n"
                 " MPU_xTaskGenericNotify_Unpriv:                        \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory"
@@ -849,12 +822,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGenericNotifyWait_Unpriv                 \n"
                 " MPU_xTaskGenericNotifyWait_Priv:                      \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGenericNotifyWaitImpl                  \n"
                 " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory"
@@ -882,12 +854,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGenericNotifyTake_Unpriv                \n"
                 " MPU_ulTaskGenericNotifyTake_Priv:                     \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGenericNotifyTakeImpl                 \n"
                 " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory"
@@ -913,12 +884,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGenericNotifyStateClear_Unpriv           \n"
                 " MPU_xTaskGenericNotifyStateClear_Priv:                \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGenericNotifyStateClearImpl            \n"
                 " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory"
@@ -946,12 +916,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGenericNotifyValueClear_Unpriv          \n"
                 " MPU_ulTaskGenericNotifyValueClear_Priv:               \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGenericNotifyValueClearImpl           \n"
                 " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory"
@@ -979,12 +948,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xQueueGenericSend_Unpriv                      \n"
             " MPU_xQueueGenericSend_Priv:                           \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xQueueGenericSendImpl                       \n"
             " MPU_xQueueGenericSend_Unpriv:                         \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory"
@@ -1004,12 +972,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_uxQueueMessagesWaiting_Unpriv                 \n"
             " MPU_uxQueueMessagesWaiting_Priv:                      \n"
-            "     pop {r0}                                          \n"
             "     b MPU_uxQueueMessagesWaitingImpl                  \n"
             " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory"
@@ -1029,12 +996,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_uxQueueSpacesAvailable_Unpriv                 \n"
             " MPU_uxQueueSpacesAvailable_Priv:                      \n"
-            "     pop {r0}                                          \n"
             "     b MPU_uxQueueSpacesAvailableImpl                  \n"
             " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory"
@@ -1058,12 +1024,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xQueueReceive_Unpriv                          \n"
             " MPU_xQueueReceive_Priv:                               \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xQueueReceiveImpl                           \n"
             " MPU_xQueueReceive_Unpriv:                             \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory"
@@ -1087,12 +1052,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xQueuePeek_Unpriv                             \n"
             " MPU_xQueuePeek_Priv:                                  \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xQueuePeekImpl                              \n"
             " MPU_xQueuePeek_Unpriv:                                \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory"
@@ -1114,12 +1078,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xQueueSemaphoreTake_Unpriv                    \n"
             " MPU_xQueueSemaphoreTake_Priv:                         \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xQueueSemaphoreTakeImpl                     \n"
             " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory"
@@ -1141,12 +1104,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xQueueGetMutexHolder_Unpriv                   \n"
                 " MPU_xQueueGetMutexHolder_Priv:                        \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xQueueGetMutexHolderImpl                    \n"
                 " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory"
@@ -1172,12 +1134,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xQueueTakeMutexRecursive_Unpriv               \n"
                 " MPU_xQueueTakeMutexRecursive_Priv:                    \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xQueueTakeMutexRecursiveImpl                \n"
                 " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory"
@@ -1201,12 +1162,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xQueueGiveMutexRecursive_Unpriv               \n"
                 " MPU_xQueueGiveMutexRecursive_Priv:                    \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xQueueGiveMutexRecursiveImpl                \n"
                 " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory"
@@ -1232,12 +1192,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xQueueSelectFromSet_Unpriv                    \n"
                 " MPU_xQueueSelectFromSet_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xQueueSelectFromSetImpl                     \n"
                 " MPU_xQueueSelectFromSet_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory"
@@ -1263,12 +1222,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xQueueAddToSet_Unpriv                         \n"
                 " MPU_xQueueAddToSet_Priv:                              \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xQueueAddToSetImpl                          \n"
                 " MPU_xQueueAddToSet_Unpriv:                            \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory"
@@ -1294,12 +1252,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vQueueAddToRegistry_Unpriv                    \n"
                 " MPU_vQueueAddToRegistry_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vQueueAddToRegistryImpl                     \n"
                 " MPU_vQueueAddToRegistry_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory"
@@ -1323,12 +1280,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vQueueUnregisterQueue_Unpriv                  \n"
                 " MPU_vQueueUnregisterQueue_Priv:                       \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vQueueUnregisterQueueImpl                   \n"
                 " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory"
@@ -1352,12 +1308,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_pcQueueGetName_Unpriv                         \n"
                 " MPU_pcQueueGetName_Priv:                              \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_pcQueueGetNameImpl                          \n"
                 " MPU_pcQueueGetName_Unpriv:                            \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory"
@@ -1381,12 +1336,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_pvTimerGetTimerID_Unpriv                      \n"
                 " MPU_pvTimerGetTimerID_Priv:                           \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_pvTimerGetTimerIDImpl                       \n"
                 " MPU_pvTimerGetTimerID_Unpriv:                         \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory"
@@ -1412,12 +1366,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTimerSetTimerID_Unpriv                       \n"
                 " MPU_vTimerSetTimerID_Priv:                            \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTimerSetTimerIDImpl                        \n"
                 " MPU_vTimerSetTimerID_Unpriv:                          \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory"
@@ -1441,12 +1394,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTimerIsTimerActive_Unpriv                    \n"
                 " MPU_xTimerIsTimerActive_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTimerIsTimerActiveImpl                     \n"
                 " MPU_xTimerIsTimerActive_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory"
@@ -1470,12 +1422,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv         \n"
                 " MPU_xTimerGetTimerDaemonTaskHandle_Priv:              \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTimerGetTimerDaemonTaskHandleImpl          \n"
                 " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory"
@@ -1493,20 +1444,19 @@
         {
             __asm volatile
             (
-                " .syntax unified                                               \n"
-                " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
-                "                                                               \n"
-                " push {r0}                                                     \n"
-                " mrs r0, control                                               \n"
-                " tst r0, #1                                                    \n"
-                " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
-                " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
-                "     pop {r0}                                                  \n"
-                "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
-                " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
-                "     pop {r0}                                                  \n"
-                "     svc %0                                                    \n"
-                "                                                               \n"
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGenericCommandFromTaskImpl          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xTimerGenericCommandFromTask_Unpriv           \n"
+                " MPU_xTimerGenericCommandFromTask_Priv:                \n"
+                "     b MPU_xTimerGenericCommandFromTaskImpl            \n"
+                " MPU_xTimerGenericCommandFromTask_Unpriv:              \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory"
             );
         }
@@ -1528,12 +1478,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_pcTimerGetName_Unpriv                         \n"
                 " MPU_pcTimerGetName_Priv:                              \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_pcTimerGetNameImpl                          \n"
                 " MPU_pcTimerGetName_Unpriv:                            \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory"
@@ -1559,12 +1508,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTimerSetReloadMode_Unpriv                    \n"
                 " MPU_vTimerSetReloadMode_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTimerSetReloadModeImpl                     \n"
                 " MPU_vTimerSetReloadMode_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory"
@@ -1588,12 +1536,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTimerGetReloadMode_Unpriv                    \n"
                 " MPU_xTimerGetReloadMode_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTimerGetReloadModeImpl                     \n"
                 " MPU_xTimerGetReloadMode_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory"
@@ -1617,12 +1564,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxTimerGetReloadMode_Unpriv                   \n"
                 " MPU_uxTimerGetReloadMode_Priv:                        \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxTimerGetReloadModeImpl                    \n"
                 " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory"
@@ -1646,12 +1592,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTimerGetPeriod_Unpriv                        \n"
                 " MPU_xTimerGetPeriod_Priv:                             \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTimerGetPeriodImpl                         \n"
                 " MPU_xTimerGetPeriod_Unpriv:                           \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory"
@@ -1675,12 +1620,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTimerGetExpiryTime_Unpriv                    \n"
                 " MPU_xTimerGetExpiryTime_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTimerGetExpiryTimeImpl                     \n"
                 " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory"
@@ -1702,12 +1646,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
             " MPU_xEventGroupWaitBits_Priv:                         \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xEventGroupWaitBitsImpl                     \n"
             " MPU_xEventGroupWaitBits_Unpriv:                       \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
@@ -1729,12 +1672,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xEventGroupClearBits_Unpriv                   \n"
             " MPU_xEventGroupClearBits_Priv:                        \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xEventGroupClearBitsImpl                    \n"
             " MPU_xEventGroupClearBits_Unpriv:                      \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
@@ -1756,12 +1698,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xEventGroupSetBits_Unpriv                     \n"
             " MPU_xEventGroupSetBits_Priv:                          \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xEventGroupSetBitsImpl                      \n"
             " MPU_xEventGroupSetBits_Unpriv:                        \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
@@ -1787,12 +1728,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xEventGroupSync_Unpriv                        \n"
             " MPU_xEventGroupSync_Priv:                             \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xEventGroupSyncImpl                         \n"
             " MPU_xEventGroupSync_Unpriv:                           \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
@@ -1814,12 +1754,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxEventGroupGetNumber_Unpriv                  \n"
                 " MPU_uxEventGroupGetNumber_Priv:                       \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxEventGroupGetNumberImpl                   \n"
                 " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory"
@@ -1845,12 +1784,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vEventGroupSetNumber_Unpriv                   \n"
                 " MPU_vEventGroupSetNumber_Priv:                        \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vEventGroupSetNumberImpl                    \n"
                 " MPU_vEventGroupSetNumber_Unpriv:                      \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory"
@@ -1878,12 +1816,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferSend_Unpriv                      \n"
             " MPU_xStreamBufferSend_Priv:                           \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferSendImpl                       \n"
             " MPU_xStreamBufferSend_Unpriv:                         \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
@@ -1909,12 +1846,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferReceive_Unpriv                   \n"
             " MPU_xStreamBufferReceive_Priv:                        \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferReceiveImpl                    \n"
             " MPU_xStreamBufferReceive_Unpriv:                      \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
@@ -1934,12 +1870,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
             " MPU_xStreamBufferIsFull_Priv:                         \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferIsFullImpl                     \n"
             " MPU_xStreamBufferIsFull_Unpriv:                       \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
@@ -1959,12 +1894,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
             " MPU_xStreamBufferIsEmpty_Priv:                        \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferIsEmptyImpl                    \n"
             " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
@@ -1984,12 +1918,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
             " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
             " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
@@ -2009,12 +1942,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
             " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferBytesAvailableImpl             \n"
             " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
@@ -2036,12 +1968,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
             " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
             " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
@@ -2061,12 +1992,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
             " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
             " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
diff --git a/portable/GCC/ARM_CM4_MPU/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM4_MPU/mpu_wrappers_v2_asm.c
index c95f72e8e..feb3e3426 100644
--- a/portable/GCC/ARM_CM4_MPU/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM4_MPU/mpu_wrappers_v2_asm.c
@@ -62,12 +62,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskDelayUntil_Unpriv                        \n"
                 " MPU_xTaskDelayUntil_Priv:                             \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskDelayUntilImpl                         \n"
                 " MPU_xTaskDelayUntil_Unpriv:                           \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory"
@@ -91,12 +90,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskAbortDelay_Unpriv                        \n"
                 " MPU_xTaskAbortDelay_Priv:                             \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskAbortDelayImpl                         \n"
                 " MPU_xTaskAbortDelay_Unpriv:                           \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory"
@@ -120,12 +118,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskDelay_Unpriv                             \n"
                 " MPU_vTaskDelay_Priv:                                  \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskDelayImpl                              \n"
                 " MPU_vTaskDelay_Unpriv:                                \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory"
@@ -149,12 +146,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxTaskPriorityGet_Unpriv                      \n"
                 " MPU_uxTaskPriorityGet_Priv:                           \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxTaskPriorityGetImpl                       \n"
                 " MPU_uxTaskPriorityGet_Unpriv:                         \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory"
@@ -178,12 +174,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_eTaskGetState_Unpriv                          \n"
                 " MPU_eTaskGetState_Priv:                               \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_eTaskGetStateImpl                           \n"
                 " MPU_eTaskGetState_Unpriv:                             \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory"
@@ -213,12 +208,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskGetInfo_Unpriv                           \n"
                 " MPU_vTaskGetInfo_Priv:                                \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskGetInfoImpl                            \n"
                 " MPU_vTaskGetInfo_Unpriv:                              \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory"
@@ -242,12 +236,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGetIdleTaskHandle_Unpriv                 \n"
                 " MPU_xTaskGetIdleTaskHandle_Priv:                      \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGetIdleTaskHandleImpl                  \n"
                 " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory"
@@ -271,12 +264,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskSuspend_Unpriv                           \n"
                 " MPU_vTaskSuspend_Priv:                                \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskSuspendImpl                            \n"
                 " MPU_vTaskSuspend_Unpriv:                              \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory"
@@ -300,12 +292,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskResume_Unpriv                            \n"
                 " MPU_vTaskResume_Priv:                                 \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskResumeImpl                             \n"
                 " MPU_vTaskResume_Unpriv:                               \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskResume ) : "memory"
@@ -327,12 +318,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xTaskGetTickCount_Unpriv                      \n"
             " MPU_xTaskGetTickCount_Priv:                           \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xTaskGetTickCountImpl                       \n"
             " MPU_xTaskGetTickCount_Unpriv:                         \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory"
@@ -352,12 +342,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_uxTaskGetNumberOfTasks_Unpriv                 \n"
             " MPU_uxTaskGetNumberOfTasks_Priv:                      \n"
-            "     pop {r0}                                          \n"
             "     b MPU_uxTaskGetNumberOfTasksImpl                  \n"
             " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory"
@@ -379,12 +368,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGetRunTimeCounter_Unpriv                \n"
                 " MPU_ulTaskGetRunTimeCounter_Priv:                     \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGetRunTimeCounterImpl                 \n"
                 " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory"
@@ -408,12 +396,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGetRunTimePercent_Unpriv                \n"
                 " MPU_ulTaskGetRunTimePercent_Priv:                     \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGetRunTimePercentImpl                 \n"
                 " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory"
@@ -437,12 +424,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv            \n"
                 " MPU_ulTaskGetIdleRunTimePercent_Priv:                 \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGetIdleRunTimePercentImpl             \n"
                 " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory"
@@ -466,12 +452,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv            \n"
                 " MPU_ulTaskGetIdleRunTimeCounter_Priv:                 \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGetIdleRunTimeCounterImpl             \n"
                 " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory"
@@ -497,12 +482,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskSetApplicationTaskTag_Unpriv             \n"
                 " MPU_vTaskSetApplicationTaskTag_Priv:                  \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskSetApplicationTaskTagImpl              \n"
                 " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory"
@@ -526,12 +510,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGetApplicationTaskTag_Unpriv             \n"
                 " MPU_xTaskGetApplicationTaskTag_Priv:                  \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGetApplicationTaskTagImpl              \n"
                 " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory"
@@ -559,12 +542,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv      \n"
                 " MPU_vTaskSetThreadLocalStoragePointer_Priv:           \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskSetThreadLocalStoragePointerImpl       \n"
                 " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory"
@@ -590,12 +572,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv     \n"
                 " MPU_pvTaskGetThreadLocalStoragePointer_Priv:          \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_pvTaskGetThreadLocalStoragePointerImpl      \n"
                 " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory"
@@ -623,12 +604,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxTaskGetSystemState_Unpriv                   \n"
                 " MPU_uxTaskGetSystemState_Priv:                        \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxTaskGetSystemStateImpl                    \n"
                 " MPU_uxTaskGetSystemState_Unpriv:                      \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory"
@@ -652,12 +632,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxTaskGetStackHighWaterMark_Unpriv            \n"
                 " MPU_uxTaskGetStackHighWaterMark_Priv:                 \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxTaskGetStackHighWaterMarkImpl             \n"
                 " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory"
@@ -681,12 +660,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv           \n"
                 " MPU_uxTaskGetStackHighWaterMark2_Priv:                \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxTaskGetStackHighWaterMark2Impl            \n"
                 " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory"
@@ -710,12 +688,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGetCurrentTaskHandle_Unpriv              \n"
                 " MPU_xTaskGetCurrentTaskHandle_Priv:                   \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGetCurrentTaskHandleImpl               \n"
                 " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory"
@@ -739,12 +716,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGetSchedulerState_Unpriv                 \n"
                 " MPU_xTaskGetSchedulerState_Priv:                      \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGetSchedulerStateImpl                  \n"
                 " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory"
@@ -766,12 +742,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_vTaskSetTimeOutState_Unpriv                   \n"
             " MPU_vTaskSetTimeOutState_Priv:                        \n"
-            "     pop {r0}                                          \n"
             "     b MPU_vTaskSetTimeOutStateImpl                    \n"
             " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory"
@@ -793,12 +768,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xTaskCheckForTimeOut_Unpriv                   \n"
             " MPU_xTaskCheckForTimeOut_Priv:                        \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xTaskCheckForTimeOutImpl                    \n"
             " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory"
@@ -820,12 +794,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGenericNotify_Unpriv                     \n"
                 " MPU_xTaskGenericNotify_Priv:                          \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGenericNotifyImpl                      \n"
                 " MPU_xTaskGenericNotify_Unpriv:                        \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory"
@@ -849,12 +822,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGenericNotifyWait_Unpriv                 \n"
                 " MPU_xTaskGenericNotifyWait_Priv:                      \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGenericNotifyWaitImpl                  \n"
                 " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory"
@@ -882,12 +854,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGenericNotifyTake_Unpriv                \n"
                 " MPU_ulTaskGenericNotifyTake_Priv:                     \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGenericNotifyTakeImpl                 \n"
                 " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory"
@@ -913,12 +884,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGenericNotifyStateClear_Unpriv           \n"
                 " MPU_xTaskGenericNotifyStateClear_Priv:                \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGenericNotifyStateClearImpl            \n"
                 " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory"
@@ -946,12 +916,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGenericNotifyValueClear_Unpriv          \n"
                 " MPU_ulTaskGenericNotifyValueClear_Priv:               \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGenericNotifyValueClearImpl           \n"
                 " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory"
@@ -979,12 +948,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xQueueGenericSend_Unpriv                      \n"
             " MPU_xQueueGenericSend_Priv:                           \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xQueueGenericSendImpl                       \n"
             " MPU_xQueueGenericSend_Unpriv:                         \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory"
@@ -1004,12 +972,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_uxQueueMessagesWaiting_Unpriv                 \n"
             " MPU_uxQueueMessagesWaiting_Priv:                      \n"
-            "     pop {r0}                                          \n"
             "     b MPU_uxQueueMessagesWaitingImpl                  \n"
             " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory"
@@ -1029,12 +996,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_uxQueueSpacesAvailable_Unpriv                 \n"
             " MPU_uxQueueSpacesAvailable_Priv:                      \n"
-            "     pop {r0}                                          \n"
             "     b MPU_uxQueueSpacesAvailableImpl                  \n"
             " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory"
@@ -1058,12 +1024,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xQueueReceive_Unpriv                          \n"
             " MPU_xQueueReceive_Priv:                               \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xQueueReceiveImpl                           \n"
             " MPU_xQueueReceive_Unpriv:                             \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory"
@@ -1087,12 +1052,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xQueuePeek_Unpriv                             \n"
             " MPU_xQueuePeek_Priv:                                  \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xQueuePeekImpl                              \n"
             " MPU_xQueuePeek_Unpriv:                                \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory"
@@ -1114,12 +1078,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xQueueSemaphoreTake_Unpriv                    \n"
             " MPU_xQueueSemaphoreTake_Priv:                         \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xQueueSemaphoreTakeImpl                     \n"
             " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory"
@@ -1141,12 +1104,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xQueueGetMutexHolder_Unpriv                   \n"
                 " MPU_xQueueGetMutexHolder_Priv:                        \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xQueueGetMutexHolderImpl                    \n"
                 " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory"
@@ -1172,12 +1134,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xQueueTakeMutexRecursive_Unpriv               \n"
                 " MPU_xQueueTakeMutexRecursive_Priv:                    \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xQueueTakeMutexRecursiveImpl                \n"
                 " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory"
@@ -1201,12 +1162,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xQueueGiveMutexRecursive_Unpriv               \n"
                 " MPU_xQueueGiveMutexRecursive_Priv:                    \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xQueueGiveMutexRecursiveImpl                \n"
                 " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory"
@@ -1232,12 +1192,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xQueueSelectFromSet_Unpriv                    \n"
                 " MPU_xQueueSelectFromSet_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xQueueSelectFromSetImpl                     \n"
                 " MPU_xQueueSelectFromSet_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory"
@@ -1263,12 +1222,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xQueueAddToSet_Unpriv                         \n"
                 " MPU_xQueueAddToSet_Priv:                              \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xQueueAddToSetImpl                          \n"
                 " MPU_xQueueAddToSet_Unpriv:                            \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory"
@@ -1294,12 +1252,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vQueueAddToRegistry_Unpriv                    \n"
                 " MPU_vQueueAddToRegistry_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vQueueAddToRegistryImpl                     \n"
                 " MPU_vQueueAddToRegistry_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory"
@@ -1323,12 +1280,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vQueueUnregisterQueue_Unpriv                  \n"
                 " MPU_vQueueUnregisterQueue_Priv:                       \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vQueueUnregisterQueueImpl                   \n"
                 " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory"
@@ -1352,12 +1308,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_pcQueueGetName_Unpriv                         \n"
                 " MPU_pcQueueGetName_Priv:                              \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_pcQueueGetNameImpl                          \n"
                 " MPU_pcQueueGetName_Unpriv:                            \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory"
@@ -1381,12 +1336,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_pvTimerGetTimerID_Unpriv                      \n"
                 " MPU_pvTimerGetTimerID_Priv:                           \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_pvTimerGetTimerIDImpl                       \n"
                 " MPU_pvTimerGetTimerID_Unpriv:                         \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory"
@@ -1412,12 +1366,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTimerSetTimerID_Unpriv                       \n"
                 " MPU_vTimerSetTimerID_Priv:                            \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTimerSetTimerIDImpl                        \n"
                 " MPU_vTimerSetTimerID_Unpriv:                          \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory"
@@ -1441,12 +1394,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTimerIsTimerActive_Unpriv                    \n"
                 " MPU_xTimerIsTimerActive_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTimerIsTimerActiveImpl                     \n"
                 " MPU_xTimerIsTimerActive_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory"
@@ -1470,12 +1422,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv         \n"
                 " MPU_xTimerGetTimerDaemonTaskHandle_Priv:              \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTimerGetTimerDaemonTaskHandleImpl          \n"
                 " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory"
@@ -1493,20 +1444,19 @@
         {
             __asm volatile
             (
-                " .syntax unified                                               \n"
-                " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
-                "                                                               \n"
-                " push {r0}                                                     \n"
-                " mrs r0, control                                               \n"
-                " tst r0, #1                                                    \n"
-                " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
-                " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
-                "     pop {r0}                                                  \n"
-                "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
-                " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
-                "     pop {r0}                                                  \n"
-                "     svc %0                                                    \n"
-                "                                                               \n"
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGenericCommandFromTaskImpl          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xTimerGenericCommandFromTask_Unpriv           \n"
+                " MPU_xTimerGenericCommandFromTask_Priv:                \n"
+                "     b MPU_xTimerGenericCommandFromTaskImpl            \n"
+                " MPU_xTimerGenericCommandFromTask_Unpriv:              \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory"
             );
         }
@@ -1528,12 +1478,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_pcTimerGetName_Unpriv                         \n"
                 " MPU_pcTimerGetName_Priv:                              \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_pcTimerGetNameImpl                          \n"
                 " MPU_pcTimerGetName_Unpriv:                            \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory"
@@ -1559,12 +1508,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTimerSetReloadMode_Unpriv                    \n"
                 " MPU_vTimerSetReloadMode_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTimerSetReloadModeImpl                     \n"
                 " MPU_vTimerSetReloadMode_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory"
@@ -1588,12 +1536,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTimerGetReloadMode_Unpriv                    \n"
                 " MPU_xTimerGetReloadMode_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTimerGetReloadModeImpl                     \n"
                 " MPU_xTimerGetReloadMode_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory"
@@ -1617,12 +1564,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxTimerGetReloadMode_Unpriv                   \n"
                 " MPU_uxTimerGetReloadMode_Priv:                        \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxTimerGetReloadModeImpl                    \n"
                 " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory"
@@ -1646,12 +1592,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTimerGetPeriod_Unpriv                        \n"
                 " MPU_xTimerGetPeriod_Priv:                             \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTimerGetPeriodImpl                         \n"
                 " MPU_xTimerGetPeriod_Unpriv:                           \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory"
@@ -1675,12 +1620,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTimerGetExpiryTime_Unpriv                    \n"
                 " MPU_xTimerGetExpiryTime_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTimerGetExpiryTimeImpl                     \n"
                 " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory"
@@ -1702,12 +1646,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
             " MPU_xEventGroupWaitBits_Priv:                         \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xEventGroupWaitBitsImpl                     \n"
             " MPU_xEventGroupWaitBits_Unpriv:                       \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
@@ -1729,12 +1672,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xEventGroupClearBits_Unpriv                   \n"
             " MPU_xEventGroupClearBits_Priv:                        \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xEventGroupClearBitsImpl                    \n"
             " MPU_xEventGroupClearBits_Unpriv:                      \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
@@ -1756,12 +1698,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xEventGroupSetBits_Unpriv                     \n"
             " MPU_xEventGroupSetBits_Priv:                          \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xEventGroupSetBitsImpl                      \n"
             " MPU_xEventGroupSetBits_Unpriv:                        \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
@@ -1787,12 +1728,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xEventGroupSync_Unpriv                        \n"
             " MPU_xEventGroupSync_Priv:                             \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xEventGroupSyncImpl                         \n"
             " MPU_xEventGroupSync_Unpriv:                           \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
@@ -1814,12 +1754,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxEventGroupGetNumber_Unpriv                  \n"
                 " MPU_uxEventGroupGetNumber_Priv:                       \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxEventGroupGetNumberImpl                   \n"
                 " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory"
@@ -1845,12 +1784,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vEventGroupSetNumber_Unpriv                   \n"
                 " MPU_vEventGroupSetNumber_Priv:                        \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vEventGroupSetNumberImpl                    \n"
                 " MPU_vEventGroupSetNumber_Unpriv:                      \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory"
@@ -1878,12 +1816,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferSend_Unpriv                      \n"
             " MPU_xStreamBufferSend_Priv:                           \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferSendImpl                       \n"
             " MPU_xStreamBufferSend_Unpriv:                         \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
@@ -1909,12 +1846,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferReceive_Unpriv                   \n"
             " MPU_xStreamBufferReceive_Priv:                        \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferReceiveImpl                    \n"
             " MPU_xStreamBufferReceive_Unpriv:                      \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
@@ -1934,12 +1870,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
             " MPU_xStreamBufferIsFull_Priv:                         \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferIsFullImpl                     \n"
             " MPU_xStreamBufferIsFull_Unpriv:                       \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
@@ -1959,12 +1894,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
             " MPU_xStreamBufferIsEmpty_Priv:                        \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferIsEmptyImpl                    \n"
             " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
@@ -1984,12 +1918,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
             " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
             " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
@@ -2009,12 +1942,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
             " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferBytesAvailableImpl             \n"
             " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
@@ -2036,12 +1968,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
             " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
             " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
@@ -2061,12 +1992,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
             " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
             " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
diff --git a/portable/GCC/ARM_CM55/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM55/non_secure/mpu_wrappers_v2_asm.c
index 170d10fcc..4f66448f9 100644
--- a/portable/GCC/ARM_CM55/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM55/non_secure/mpu_wrappers_v2_asm.c
@@ -62,12 +62,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskDelayUntil_Unpriv                        \n"
                 " MPU_xTaskDelayUntil_Priv:                             \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskDelayUntilImpl                         \n"
                 " MPU_xTaskDelayUntil_Unpriv:                           \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory"
@@ -91,12 +90,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskAbortDelay_Unpriv                        \n"
                 " MPU_xTaskAbortDelay_Priv:                             \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskAbortDelayImpl                         \n"
                 " MPU_xTaskAbortDelay_Unpriv:                           \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory"
@@ -120,12 +118,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskDelay_Unpriv                             \n"
                 " MPU_vTaskDelay_Priv:                                  \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskDelayImpl                              \n"
                 " MPU_vTaskDelay_Unpriv:                                \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory"
@@ -149,12 +146,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxTaskPriorityGet_Unpriv                      \n"
                 " MPU_uxTaskPriorityGet_Priv:                           \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxTaskPriorityGetImpl                       \n"
                 " MPU_uxTaskPriorityGet_Unpriv:                         \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory"
@@ -178,12 +174,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_eTaskGetState_Unpriv                          \n"
                 " MPU_eTaskGetState_Priv:                               \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_eTaskGetStateImpl                           \n"
                 " MPU_eTaskGetState_Unpriv:                             \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory"
@@ -213,12 +208,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskGetInfo_Unpriv                           \n"
                 " MPU_vTaskGetInfo_Priv:                                \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskGetInfoImpl                            \n"
                 " MPU_vTaskGetInfo_Unpriv:                              \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory"
@@ -242,12 +236,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGetIdleTaskHandle_Unpriv                 \n"
                 " MPU_xTaskGetIdleTaskHandle_Priv:                      \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGetIdleTaskHandleImpl                  \n"
                 " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory"
@@ -271,12 +264,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskSuspend_Unpriv                           \n"
                 " MPU_vTaskSuspend_Priv:                                \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskSuspendImpl                            \n"
                 " MPU_vTaskSuspend_Unpriv:                              \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory"
@@ -300,12 +292,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskResume_Unpriv                            \n"
                 " MPU_vTaskResume_Priv:                                 \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskResumeImpl                             \n"
                 " MPU_vTaskResume_Unpriv:                               \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskResume ) : "memory"
@@ -327,12 +318,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xTaskGetTickCount_Unpriv                      \n"
             " MPU_xTaskGetTickCount_Priv:                           \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xTaskGetTickCountImpl                       \n"
             " MPU_xTaskGetTickCount_Unpriv:                         \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory"
@@ -352,12 +342,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_uxTaskGetNumberOfTasks_Unpriv                 \n"
             " MPU_uxTaskGetNumberOfTasks_Priv:                      \n"
-            "     pop {r0}                                          \n"
             "     b MPU_uxTaskGetNumberOfTasksImpl                  \n"
             " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory"
@@ -379,12 +368,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGetRunTimeCounter_Unpriv                \n"
                 " MPU_ulTaskGetRunTimeCounter_Priv:                     \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGetRunTimeCounterImpl                 \n"
                 " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory"
@@ -408,12 +396,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGetRunTimePercent_Unpriv                \n"
                 " MPU_ulTaskGetRunTimePercent_Priv:                     \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGetRunTimePercentImpl                 \n"
                 " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory"
@@ -437,12 +424,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv            \n"
                 " MPU_ulTaskGetIdleRunTimePercent_Priv:                 \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGetIdleRunTimePercentImpl             \n"
                 " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory"
@@ -466,12 +452,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv            \n"
                 " MPU_ulTaskGetIdleRunTimeCounter_Priv:                 \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGetIdleRunTimeCounterImpl             \n"
                 " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory"
@@ -497,12 +482,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskSetApplicationTaskTag_Unpriv             \n"
                 " MPU_vTaskSetApplicationTaskTag_Priv:                  \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskSetApplicationTaskTagImpl              \n"
                 " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory"
@@ -526,12 +510,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGetApplicationTaskTag_Unpriv             \n"
                 " MPU_xTaskGetApplicationTaskTag_Priv:                  \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGetApplicationTaskTagImpl              \n"
                 " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory"
@@ -559,12 +542,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv      \n"
                 " MPU_vTaskSetThreadLocalStoragePointer_Priv:           \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskSetThreadLocalStoragePointerImpl       \n"
                 " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory"
@@ -590,12 +572,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv     \n"
                 " MPU_pvTaskGetThreadLocalStoragePointer_Priv:          \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_pvTaskGetThreadLocalStoragePointerImpl      \n"
                 " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory"
@@ -623,12 +604,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxTaskGetSystemState_Unpriv                   \n"
                 " MPU_uxTaskGetSystemState_Priv:                        \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxTaskGetSystemStateImpl                    \n"
                 " MPU_uxTaskGetSystemState_Unpriv:                      \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory"
@@ -652,12 +632,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxTaskGetStackHighWaterMark_Unpriv            \n"
                 " MPU_uxTaskGetStackHighWaterMark_Priv:                 \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxTaskGetStackHighWaterMarkImpl             \n"
                 " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory"
@@ -681,12 +660,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv           \n"
                 " MPU_uxTaskGetStackHighWaterMark2_Priv:                \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxTaskGetStackHighWaterMark2Impl            \n"
                 " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory"
@@ -710,12 +688,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGetCurrentTaskHandle_Unpriv              \n"
                 " MPU_xTaskGetCurrentTaskHandle_Priv:                   \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGetCurrentTaskHandleImpl               \n"
                 " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory"
@@ -739,12 +716,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGetSchedulerState_Unpriv                 \n"
                 " MPU_xTaskGetSchedulerState_Priv:                      \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGetSchedulerStateImpl                  \n"
                 " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory"
@@ -766,12 +742,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_vTaskSetTimeOutState_Unpriv                   \n"
             " MPU_vTaskSetTimeOutState_Priv:                        \n"
-            "     pop {r0}                                          \n"
             "     b MPU_vTaskSetTimeOutStateImpl                    \n"
             " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory"
@@ -793,12 +768,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xTaskCheckForTimeOut_Unpriv                   \n"
             " MPU_xTaskCheckForTimeOut_Priv:                        \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xTaskCheckForTimeOutImpl                    \n"
             " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory"
@@ -820,12 +794,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGenericNotify_Unpriv                     \n"
                 " MPU_xTaskGenericNotify_Priv:                          \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGenericNotifyImpl                      \n"
                 " MPU_xTaskGenericNotify_Unpriv:                        \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory"
@@ -849,12 +822,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGenericNotifyWait_Unpriv                 \n"
                 " MPU_xTaskGenericNotifyWait_Priv:                      \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGenericNotifyWaitImpl                  \n"
                 " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory"
@@ -882,12 +854,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGenericNotifyTake_Unpriv                \n"
                 " MPU_ulTaskGenericNotifyTake_Priv:                     \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGenericNotifyTakeImpl                 \n"
                 " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory"
@@ -913,12 +884,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGenericNotifyStateClear_Unpriv           \n"
                 " MPU_xTaskGenericNotifyStateClear_Priv:                \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGenericNotifyStateClearImpl            \n"
                 " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory"
@@ -946,12 +916,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGenericNotifyValueClear_Unpriv          \n"
                 " MPU_ulTaskGenericNotifyValueClear_Priv:               \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGenericNotifyValueClearImpl           \n"
                 " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory"
@@ -979,12 +948,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xQueueGenericSend_Unpriv                      \n"
             " MPU_xQueueGenericSend_Priv:                           \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xQueueGenericSendImpl                       \n"
             " MPU_xQueueGenericSend_Unpriv:                         \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory"
@@ -1004,12 +972,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_uxQueueMessagesWaiting_Unpriv                 \n"
             " MPU_uxQueueMessagesWaiting_Priv:                      \n"
-            "     pop {r0}                                          \n"
             "     b MPU_uxQueueMessagesWaitingImpl                  \n"
             " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory"
@@ -1029,12 +996,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_uxQueueSpacesAvailable_Unpriv                 \n"
             " MPU_uxQueueSpacesAvailable_Priv:                      \n"
-            "     pop {r0}                                          \n"
             "     b MPU_uxQueueSpacesAvailableImpl                  \n"
             " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory"
@@ -1058,12 +1024,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xQueueReceive_Unpriv                          \n"
             " MPU_xQueueReceive_Priv:                               \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xQueueReceiveImpl                           \n"
             " MPU_xQueueReceive_Unpriv:                             \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory"
@@ -1087,12 +1052,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xQueuePeek_Unpriv                             \n"
             " MPU_xQueuePeek_Priv:                                  \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xQueuePeekImpl                              \n"
             " MPU_xQueuePeek_Unpriv:                                \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory"
@@ -1114,12 +1078,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xQueueSemaphoreTake_Unpriv                    \n"
             " MPU_xQueueSemaphoreTake_Priv:                         \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xQueueSemaphoreTakeImpl                     \n"
             " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory"
@@ -1141,12 +1104,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xQueueGetMutexHolder_Unpriv                   \n"
                 " MPU_xQueueGetMutexHolder_Priv:                        \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xQueueGetMutexHolderImpl                    \n"
                 " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory"
@@ -1172,12 +1134,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xQueueTakeMutexRecursive_Unpriv               \n"
                 " MPU_xQueueTakeMutexRecursive_Priv:                    \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xQueueTakeMutexRecursiveImpl                \n"
                 " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory"
@@ -1201,12 +1162,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xQueueGiveMutexRecursive_Unpriv               \n"
                 " MPU_xQueueGiveMutexRecursive_Priv:                    \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xQueueGiveMutexRecursiveImpl                \n"
                 " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory"
@@ -1232,12 +1192,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xQueueSelectFromSet_Unpriv                    \n"
                 " MPU_xQueueSelectFromSet_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xQueueSelectFromSetImpl                     \n"
                 " MPU_xQueueSelectFromSet_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory"
@@ -1263,12 +1222,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xQueueAddToSet_Unpriv                         \n"
                 " MPU_xQueueAddToSet_Priv:                              \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xQueueAddToSetImpl                          \n"
                 " MPU_xQueueAddToSet_Unpriv:                            \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory"
@@ -1294,12 +1252,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vQueueAddToRegistry_Unpriv                    \n"
                 " MPU_vQueueAddToRegistry_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vQueueAddToRegistryImpl                     \n"
                 " MPU_vQueueAddToRegistry_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory"
@@ -1323,12 +1280,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vQueueUnregisterQueue_Unpriv                  \n"
                 " MPU_vQueueUnregisterQueue_Priv:                       \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vQueueUnregisterQueueImpl                   \n"
                 " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory"
@@ -1352,12 +1308,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_pcQueueGetName_Unpriv                         \n"
                 " MPU_pcQueueGetName_Priv:                              \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_pcQueueGetNameImpl                          \n"
                 " MPU_pcQueueGetName_Unpriv:                            \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory"
@@ -1381,12 +1336,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_pvTimerGetTimerID_Unpriv                      \n"
                 " MPU_pvTimerGetTimerID_Priv:                           \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_pvTimerGetTimerIDImpl                       \n"
                 " MPU_pvTimerGetTimerID_Unpriv:                         \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory"
@@ -1412,12 +1366,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTimerSetTimerID_Unpriv                       \n"
                 " MPU_vTimerSetTimerID_Priv:                            \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTimerSetTimerIDImpl                        \n"
                 " MPU_vTimerSetTimerID_Unpriv:                          \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory"
@@ -1441,12 +1394,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTimerIsTimerActive_Unpriv                    \n"
                 " MPU_xTimerIsTimerActive_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTimerIsTimerActiveImpl                     \n"
                 " MPU_xTimerIsTimerActive_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory"
@@ -1470,12 +1422,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv         \n"
                 " MPU_xTimerGetTimerDaemonTaskHandle_Priv:              \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTimerGetTimerDaemonTaskHandleImpl          \n"
                 " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory"
@@ -1493,20 +1444,19 @@
         {
             __asm volatile
             (
-                " .syntax unified                                               \n"
-                " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
-                "                                                               \n"
-                " push {r0}                                                     \n"
-                " mrs r0, control                                               \n"
-                " tst r0, #1                                                    \n"
-                " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
-                " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
-                "     pop {r0}                                                  \n"
-                "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
-                " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
-                "     pop {r0}                                                  \n"
-                "     svc %0                                                    \n"
-                "                                                               \n"
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGenericCommandFromTaskImpl          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xTimerGenericCommandFromTask_Unpriv           \n"
+                " MPU_xTimerGenericCommandFromTask_Priv:                \n"
+                "     b MPU_xTimerGenericCommandFromTaskImpl            \n"
+                " MPU_xTimerGenericCommandFromTask_Unpriv:              \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory"
             );
         }
@@ -1528,12 +1478,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_pcTimerGetName_Unpriv                         \n"
                 " MPU_pcTimerGetName_Priv:                              \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_pcTimerGetNameImpl                          \n"
                 " MPU_pcTimerGetName_Unpriv:                            \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory"
@@ -1559,12 +1508,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTimerSetReloadMode_Unpriv                    \n"
                 " MPU_vTimerSetReloadMode_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTimerSetReloadModeImpl                     \n"
                 " MPU_vTimerSetReloadMode_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory"
@@ -1588,12 +1536,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTimerGetReloadMode_Unpriv                    \n"
                 " MPU_xTimerGetReloadMode_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTimerGetReloadModeImpl                     \n"
                 " MPU_xTimerGetReloadMode_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory"
@@ -1617,12 +1564,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxTimerGetReloadMode_Unpriv                   \n"
                 " MPU_uxTimerGetReloadMode_Priv:                        \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxTimerGetReloadModeImpl                    \n"
                 " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory"
@@ -1646,12 +1592,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTimerGetPeriod_Unpriv                        \n"
                 " MPU_xTimerGetPeriod_Priv:                             \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTimerGetPeriodImpl                         \n"
                 " MPU_xTimerGetPeriod_Unpriv:                           \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory"
@@ -1675,12 +1620,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTimerGetExpiryTime_Unpriv                    \n"
                 " MPU_xTimerGetExpiryTime_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTimerGetExpiryTimeImpl                     \n"
                 " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory"
@@ -1702,12 +1646,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
             " MPU_xEventGroupWaitBits_Priv:                         \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xEventGroupWaitBitsImpl                     \n"
             " MPU_xEventGroupWaitBits_Unpriv:                       \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
@@ -1729,12 +1672,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xEventGroupClearBits_Unpriv                   \n"
             " MPU_xEventGroupClearBits_Priv:                        \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xEventGroupClearBitsImpl                    \n"
             " MPU_xEventGroupClearBits_Unpriv:                      \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
@@ -1756,12 +1698,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xEventGroupSetBits_Unpriv                     \n"
             " MPU_xEventGroupSetBits_Priv:                          \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xEventGroupSetBitsImpl                      \n"
             " MPU_xEventGroupSetBits_Unpriv:                        \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
@@ -1787,12 +1728,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xEventGroupSync_Unpriv                        \n"
             " MPU_xEventGroupSync_Priv:                             \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xEventGroupSyncImpl                         \n"
             " MPU_xEventGroupSync_Unpriv:                           \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
@@ -1814,12 +1754,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxEventGroupGetNumber_Unpriv                  \n"
                 " MPU_uxEventGroupGetNumber_Priv:                       \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxEventGroupGetNumberImpl                   \n"
                 " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory"
@@ -1845,12 +1784,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vEventGroupSetNumber_Unpriv                   \n"
                 " MPU_vEventGroupSetNumber_Priv:                        \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vEventGroupSetNumberImpl                    \n"
                 " MPU_vEventGroupSetNumber_Unpriv:                      \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory"
@@ -1878,12 +1816,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferSend_Unpriv                      \n"
             " MPU_xStreamBufferSend_Priv:                           \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferSendImpl                       \n"
             " MPU_xStreamBufferSend_Unpriv:                         \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
@@ -1909,12 +1846,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferReceive_Unpriv                   \n"
             " MPU_xStreamBufferReceive_Priv:                        \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferReceiveImpl                    \n"
             " MPU_xStreamBufferReceive_Unpriv:                      \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
@@ -1934,12 +1870,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
             " MPU_xStreamBufferIsFull_Priv:                         \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferIsFullImpl                     \n"
             " MPU_xStreamBufferIsFull_Unpriv:                       \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
@@ -1959,12 +1894,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
             " MPU_xStreamBufferIsEmpty_Priv:                        \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferIsEmptyImpl                    \n"
             " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
@@ -1984,12 +1918,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
             " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
             " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
@@ -2009,12 +1942,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
             " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferBytesAvailableImpl             \n"
             " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
@@ -2036,12 +1968,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
             " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
             " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
@@ -2061,12 +1992,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
             " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
             " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.c
index 170d10fcc..4f66448f9 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.c
@@ -62,12 +62,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskDelayUntil_Unpriv                        \n"
                 " MPU_xTaskDelayUntil_Priv:                             \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskDelayUntilImpl                         \n"
                 " MPU_xTaskDelayUntil_Unpriv:                           \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory"
@@ -91,12 +90,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskAbortDelay_Unpriv                        \n"
                 " MPU_xTaskAbortDelay_Priv:                             \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskAbortDelayImpl                         \n"
                 " MPU_xTaskAbortDelay_Unpriv:                           \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory"
@@ -120,12 +118,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskDelay_Unpriv                             \n"
                 " MPU_vTaskDelay_Priv:                                  \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskDelayImpl                              \n"
                 " MPU_vTaskDelay_Unpriv:                                \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory"
@@ -149,12 +146,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxTaskPriorityGet_Unpriv                      \n"
                 " MPU_uxTaskPriorityGet_Priv:                           \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxTaskPriorityGetImpl                       \n"
                 " MPU_uxTaskPriorityGet_Unpriv:                         \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory"
@@ -178,12 +174,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_eTaskGetState_Unpriv                          \n"
                 " MPU_eTaskGetState_Priv:                               \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_eTaskGetStateImpl                           \n"
                 " MPU_eTaskGetState_Unpriv:                             \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory"
@@ -213,12 +208,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskGetInfo_Unpriv                           \n"
                 " MPU_vTaskGetInfo_Priv:                                \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskGetInfoImpl                            \n"
                 " MPU_vTaskGetInfo_Unpriv:                              \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory"
@@ -242,12 +236,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGetIdleTaskHandle_Unpriv                 \n"
                 " MPU_xTaskGetIdleTaskHandle_Priv:                      \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGetIdleTaskHandleImpl                  \n"
                 " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory"
@@ -271,12 +264,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskSuspend_Unpriv                           \n"
                 " MPU_vTaskSuspend_Priv:                                \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskSuspendImpl                            \n"
                 " MPU_vTaskSuspend_Unpriv:                              \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory"
@@ -300,12 +292,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskResume_Unpriv                            \n"
                 " MPU_vTaskResume_Priv:                                 \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskResumeImpl                             \n"
                 " MPU_vTaskResume_Unpriv:                               \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskResume ) : "memory"
@@ -327,12 +318,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xTaskGetTickCount_Unpriv                      \n"
             " MPU_xTaskGetTickCount_Priv:                           \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xTaskGetTickCountImpl                       \n"
             " MPU_xTaskGetTickCount_Unpriv:                         \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory"
@@ -352,12 +342,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_uxTaskGetNumberOfTasks_Unpriv                 \n"
             " MPU_uxTaskGetNumberOfTasks_Priv:                      \n"
-            "     pop {r0}                                          \n"
             "     b MPU_uxTaskGetNumberOfTasksImpl                  \n"
             " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory"
@@ -379,12 +368,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGetRunTimeCounter_Unpriv                \n"
                 " MPU_ulTaskGetRunTimeCounter_Priv:                     \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGetRunTimeCounterImpl                 \n"
                 " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory"
@@ -408,12 +396,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGetRunTimePercent_Unpriv                \n"
                 " MPU_ulTaskGetRunTimePercent_Priv:                     \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGetRunTimePercentImpl                 \n"
                 " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory"
@@ -437,12 +424,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv            \n"
                 " MPU_ulTaskGetIdleRunTimePercent_Priv:                 \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGetIdleRunTimePercentImpl             \n"
                 " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory"
@@ -466,12 +452,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv            \n"
                 " MPU_ulTaskGetIdleRunTimeCounter_Priv:                 \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGetIdleRunTimeCounterImpl             \n"
                 " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory"
@@ -497,12 +482,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskSetApplicationTaskTag_Unpriv             \n"
                 " MPU_vTaskSetApplicationTaskTag_Priv:                  \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskSetApplicationTaskTagImpl              \n"
                 " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory"
@@ -526,12 +510,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGetApplicationTaskTag_Unpriv             \n"
                 " MPU_xTaskGetApplicationTaskTag_Priv:                  \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGetApplicationTaskTagImpl              \n"
                 " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory"
@@ -559,12 +542,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv      \n"
                 " MPU_vTaskSetThreadLocalStoragePointer_Priv:           \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskSetThreadLocalStoragePointerImpl       \n"
                 " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory"
@@ -590,12 +572,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv     \n"
                 " MPU_pvTaskGetThreadLocalStoragePointer_Priv:          \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_pvTaskGetThreadLocalStoragePointerImpl      \n"
                 " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory"
@@ -623,12 +604,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxTaskGetSystemState_Unpriv                   \n"
                 " MPU_uxTaskGetSystemState_Priv:                        \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxTaskGetSystemStateImpl                    \n"
                 " MPU_uxTaskGetSystemState_Unpriv:                      \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory"
@@ -652,12 +632,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxTaskGetStackHighWaterMark_Unpriv            \n"
                 " MPU_uxTaskGetStackHighWaterMark_Priv:                 \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxTaskGetStackHighWaterMarkImpl             \n"
                 " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory"
@@ -681,12 +660,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv           \n"
                 " MPU_uxTaskGetStackHighWaterMark2_Priv:                \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxTaskGetStackHighWaterMark2Impl            \n"
                 " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory"
@@ -710,12 +688,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGetCurrentTaskHandle_Unpriv              \n"
                 " MPU_xTaskGetCurrentTaskHandle_Priv:                   \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGetCurrentTaskHandleImpl               \n"
                 " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory"
@@ -739,12 +716,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGetSchedulerState_Unpriv                 \n"
                 " MPU_xTaskGetSchedulerState_Priv:                      \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGetSchedulerStateImpl                  \n"
                 " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory"
@@ -766,12 +742,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_vTaskSetTimeOutState_Unpriv                   \n"
             " MPU_vTaskSetTimeOutState_Priv:                        \n"
-            "     pop {r0}                                          \n"
             "     b MPU_vTaskSetTimeOutStateImpl                    \n"
             " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory"
@@ -793,12 +768,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xTaskCheckForTimeOut_Unpriv                   \n"
             " MPU_xTaskCheckForTimeOut_Priv:                        \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xTaskCheckForTimeOutImpl                    \n"
             " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory"
@@ -820,12 +794,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGenericNotify_Unpriv                     \n"
                 " MPU_xTaskGenericNotify_Priv:                          \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGenericNotifyImpl                      \n"
                 " MPU_xTaskGenericNotify_Unpriv:                        \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory"
@@ -849,12 +822,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGenericNotifyWait_Unpriv                 \n"
                 " MPU_xTaskGenericNotifyWait_Priv:                      \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGenericNotifyWaitImpl                  \n"
                 " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory"
@@ -882,12 +854,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGenericNotifyTake_Unpriv                \n"
                 " MPU_ulTaskGenericNotifyTake_Priv:                     \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGenericNotifyTakeImpl                 \n"
                 " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory"
@@ -913,12 +884,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGenericNotifyStateClear_Unpriv           \n"
                 " MPU_xTaskGenericNotifyStateClear_Priv:                \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGenericNotifyStateClearImpl            \n"
                 " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory"
@@ -946,12 +916,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGenericNotifyValueClear_Unpriv          \n"
                 " MPU_ulTaskGenericNotifyValueClear_Priv:               \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGenericNotifyValueClearImpl           \n"
                 " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory"
@@ -979,12 +948,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xQueueGenericSend_Unpriv                      \n"
             " MPU_xQueueGenericSend_Priv:                           \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xQueueGenericSendImpl                       \n"
             " MPU_xQueueGenericSend_Unpriv:                         \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory"
@@ -1004,12 +972,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_uxQueueMessagesWaiting_Unpriv                 \n"
             " MPU_uxQueueMessagesWaiting_Priv:                      \n"
-            "     pop {r0}                                          \n"
             "     b MPU_uxQueueMessagesWaitingImpl                  \n"
             " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory"
@@ -1029,12 +996,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_uxQueueSpacesAvailable_Unpriv                 \n"
             " MPU_uxQueueSpacesAvailable_Priv:                      \n"
-            "     pop {r0}                                          \n"
             "     b MPU_uxQueueSpacesAvailableImpl                  \n"
             " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory"
@@ -1058,12 +1024,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xQueueReceive_Unpriv                          \n"
             " MPU_xQueueReceive_Priv:                               \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xQueueReceiveImpl                           \n"
             " MPU_xQueueReceive_Unpriv:                             \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory"
@@ -1087,12 +1052,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xQueuePeek_Unpriv                             \n"
             " MPU_xQueuePeek_Priv:                                  \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xQueuePeekImpl                              \n"
             " MPU_xQueuePeek_Unpriv:                                \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory"
@@ -1114,12 +1078,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xQueueSemaphoreTake_Unpriv                    \n"
             " MPU_xQueueSemaphoreTake_Priv:                         \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xQueueSemaphoreTakeImpl                     \n"
             " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory"
@@ -1141,12 +1104,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xQueueGetMutexHolder_Unpriv                   \n"
                 " MPU_xQueueGetMutexHolder_Priv:                        \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xQueueGetMutexHolderImpl                    \n"
                 " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory"
@@ -1172,12 +1134,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xQueueTakeMutexRecursive_Unpriv               \n"
                 " MPU_xQueueTakeMutexRecursive_Priv:                    \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xQueueTakeMutexRecursiveImpl                \n"
                 " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory"
@@ -1201,12 +1162,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xQueueGiveMutexRecursive_Unpriv               \n"
                 " MPU_xQueueGiveMutexRecursive_Priv:                    \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xQueueGiveMutexRecursiveImpl                \n"
                 " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory"
@@ -1232,12 +1192,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xQueueSelectFromSet_Unpriv                    \n"
                 " MPU_xQueueSelectFromSet_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xQueueSelectFromSetImpl                     \n"
                 " MPU_xQueueSelectFromSet_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory"
@@ -1263,12 +1222,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xQueueAddToSet_Unpriv                         \n"
                 " MPU_xQueueAddToSet_Priv:                              \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xQueueAddToSetImpl                          \n"
                 " MPU_xQueueAddToSet_Unpriv:                            \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory"
@@ -1294,12 +1252,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vQueueAddToRegistry_Unpriv                    \n"
                 " MPU_vQueueAddToRegistry_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vQueueAddToRegistryImpl                     \n"
                 " MPU_vQueueAddToRegistry_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory"
@@ -1323,12 +1280,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vQueueUnregisterQueue_Unpriv                  \n"
                 " MPU_vQueueUnregisterQueue_Priv:                       \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vQueueUnregisterQueueImpl                   \n"
                 " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory"
@@ -1352,12 +1308,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_pcQueueGetName_Unpriv                         \n"
                 " MPU_pcQueueGetName_Priv:                              \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_pcQueueGetNameImpl                          \n"
                 " MPU_pcQueueGetName_Unpriv:                            \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory"
@@ -1381,12 +1336,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_pvTimerGetTimerID_Unpriv                      \n"
                 " MPU_pvTimerGetTimerID_Priv:                           \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_pvTimerGetTimerIDImpl                       \n"
                 " MPU_pvTimerGetTimerID_Unpriv:                         \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory"
@@ -1412,12 +1366,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTimerSetTimerID_Unpriv                       \n"
                 " MPU_vTimerSetTimerID_Priv:                            \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTimerSetTimerIDImpl                        \n"
                 " MPU_vTimerSetTimerID_Unpriv:                          \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory"
@@ -1441,12 +1394,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTimerIsTimerActive_Unpriv                    \n"
                 " MPU_xTimerIsTimerActive_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTimerIsTimerActiveImpl                     \n"
                 " MPU_xTimerIsTimerActive_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory"
@@ -1470,12 +1422,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv         \n"
                 " MPU_xTimerGetTimerDaemonTaskHandle_Priv:              \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTimerGetTimerDaemonTaskHandleImpl          \n"
                 " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory"
@@ -1493,20 +1444,19 @@
         {
             __asm volatile
             (
-                " .syntax unified                                               \n"
-                " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
-                "                                                               \n"
-                " push {r0}                                                     \n"
-                " mrs r0, control                                               \n"
-                " tst r0, #1                                                    \n"
-                " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
-                " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
-                "     pop {r0}                                                  \n"
-                "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
-                " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
-                "     pop {r0}                                                  \n"
-                "     svc %0                                                    \n"
-                "                                                               \n"
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGenericCommandFromTaskImpl          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xTimerGenericCommandFromTask_Unpriv           \n"
+                " MPU_xTimerGenericCommandFromTask_Priv:                \n"
+                "     b MPU_xTimerGenericCommandFromTaskImpl            \n"
+                " MPU_xTimerGenericCommandFromTask_Unpriv:              \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory"
             );
         }
@@ -1528,12 +1478,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_pcTimerGetName_Unpriv                         \n"
                 " MPU_pcTimerGetName_Priv:                              \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_pcTimerGetNameImpl                          \n"
                 " MPU_pcTimerGetName_Unpriv:                            \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory"
@@ -1559,12 +1508,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTimerSetReloadMode_Unpriv                    \n"
                 " MPU_vTimerSetReloadMode_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTimerSetReloadModeImpl                     \n"
                 " MPU_vTimerSetReloadMode_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory"
@@ -1588,12 +1536,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTimerGetReloadMode_Unpriv                    \n"
                 " MPU_xTimerGetReloadMode_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTimerGetReloadModeImpl                     \n"
                 " MPU_xTimerGetReloadMode_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory"
@@ -1617,12 +1564,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxTimerGetReloadMode_Unpriv                   \n"
                 " MPU_uxTimerGetReloadMode_Priv:                        \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxTimerGetReloadModeImpl                    \n"
                 " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory"
@@ -1646,12 +1592,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTimerGetPeriod_Unpriv                        \n"
                 " MPU_xTimerGetPeriod_Priv:                             \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTimerGetPeriodImpl                         \n"
                 " MPU_xTimerGetPeriod_Unpriv:                           \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory"
@@ -1675,12 +1620,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTimerGetExpiryTime_Unpriv                    \n"
                 " MPU_xTimerGetExpiryTime_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTimerGetExpiryTimeImpl                     \n"
                 " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory"
@@ -1702,12 +1646,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
             " MPU_xEventGroupWaitBits_Priv:                         \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xEventGroupWaitBitsImpl                     \n"
             " MPU_xEventGroupWaitBits_Unpriv:                       \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
@@ -1729,12 +1672,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xEventGroupClearBits_Unpriv                   \n"
             " MPU_xEventGroupClearBits_Priv:                        \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xEventGroupClearBitsImpl                    \n"
             " MPU_xEventGroupClearBits_Unpriv:                      \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
@@ -1756,12 +1698,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xEventGroupSetBits_Unpriv                     \n"
             " MPU_xEventGroupSetBits_Priv:                          \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xEventGroupSetBitsImpl                      \n"
             " MPU_xEventGroupSetBits_Unpriv:                        \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
@@ -1787,12 +1728,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xEventGroupSync_Unpriv                        \n"
             " MPU_xEventGroupSync_Priv:                             \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xEventGroupSyncImpl                         \n"
             " MPU_xEventGroupSync_Unpriv:                           \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
@@ -1814,12 +1754,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxEventGroupGetNumber_Unpriv                  \n"
                 " MPU_uxEventGroupGetNumber_Priv:                       \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxEventGroupGetNumberImpl                   \n"
                 " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory"
@@ -1845,12 +1784,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vEventGroupSetNumber_Unpriv                   \n"
                 " MPU_vEventGroupSetNumber_Priv:                        \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vEventGroupSetNumberImpl                    \n"
                 " MPU_vEventGroupSetNumber_Unpriv:                      \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory"
@@ -1878,12 +1816,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferSend_Unpriv                      \n"
             " MPU_xStreamBufferSend_Priv:                           \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferSendImpl                       \n"
             " MPU_xStreamBufferSend_Unpriv:                         \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
@@ -1909,12 +1846,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferReceive_Unpriv                   \n"
             " MPU_xStreamBufferReceive_Priv:                        \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferReceiveImpl                    \n"
             " MPU_xStreamBufferReceive_Unpriv:                      \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
@@ -1934,12 +1870,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
             " MPU_xStreamBufferIsFull_Priv:                         \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferIsFullImpl                     \n"
             " MPU_xStreamBufferIsFull_Unpriv:                       \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
@@ -1959,12 +1894,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
             " MPU_xStreamBufferIsEmpty_Priv:                        \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferIsEmptyImpl                    \n"
             " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
@@ -1984,12 +1918,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
             " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
             " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
@@ -2009,12 +1942,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
             " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferBytesAvailableImpl             \n"
             " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
@@ -2036,12 +1968,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
             " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
             " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
@@ -2061,12 +1992,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
             " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
             " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
diff --git a/portable/GCC/ARM_CM85/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM85/non_secure/mpu_wrappers_v2_asm.c
index 170d10fcc..4f66448f9 100644
--- a/portable/GCC/ARM_CM85/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM85/non_secure/mpu_wrappers_v2_asm.c
@@ -62,12 +62,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskDelayUntil_Unpriv                        \n"
                 " MPU_xTaskDelayUntil_Priv:                             \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskDelayUntilImpl                         \n"
                 " MPU_xTaskDelayUntil_Unpriv:                           \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory"
@@ -91,12 +90,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskAbortDelay_Unpriv                        \n"
                 " MPU_xTaskAbortDelay_Priv:                             \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskAbortDelayImpl                         \n"
                 " MPU_xTaskAbortDelay_Unpriv:                           \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory"
@@ -120,12 +118,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskDelay_Unpriv                             \n"
                 " MPU_vTaskDelay_Priv:                                  \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskDelayImpl                              \n"
                 " MPU_vTaskDelay_Unpriv:                                \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory"
@@ -149,12 +146,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxTaskPriorityGet_Unpriv                      \n"
                 " MPU_uxTaskPriorityGet_Priv:                           \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxTaskPriorityGetImpl                       \n"
                 " MPU_uxTaskPriorityGet_Unpriv:                         \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory"
@@ -178,12 +174,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_eTaskGetState_Unpriv                          \n"
                 " MPU_eTaskGetState_Priv:                               \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_eTaskGetStateImpl                           \n"
                 " MPU_eTaskGetState_Unpriv:                             \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory"
@@ -213,12 +208,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskGetInfo_Unpriv                           \n"
                 " MPU_vTaskGetInfo_Priv:                                \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskGetInfoImpl                            \n"
                 " MPU_vTaskGetInfo_Unpriv:                              \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory"
@@ -242,12 +236,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGetIdleTaskHandle_Unpriv                 \n"
                 " MPU_xTaskGetIdleTaskHandle_Priv:                      \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGetIdleTaskHandleImpl                  \n"
                 " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory"
@@ -271,12 +264,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskSuspend_Unpriv                           \n"
                 " MPU_vTaskSuspend_Priv:                                \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskSuspendImpl                            \n"
                 " MPU_vTaskSuspend_Unpriv:                              \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory"
@@ -300,12 +292,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskResume_Unpriv                            \n"
                 " MPU_vTaskResume_Priv:                                 \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskResumeImpl                             \n"
                 " MPU_vTaskResume_Unpriv:                               \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskResume ) : "memory"
@@ -327,12 +318,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xTaskGetTickCount_Unpriv                      \n"
             " MPU_xTaskGetTickCount_Priv:                           \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xTaskGetTickCountImpl                       \n"
             " MPU_xTaskGetTickCount_Unpriv:                         \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory"
@@ -352,12 +342,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_uxTaskGetNumberOfTasks_Unpriv                 \n"
             " MPU_uxTaskGetNumberOfTasks_Priv:                      \n"
-            "     pop {r0}                                          \n"
             "     b MPU_uxTaskGetNumberOfTasksImpl                  \n"
             " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory"
@@ -379,12 +368,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGetRunTimeCounter_Unpriv                \n"
                 " MPU_ulTaskGetRunTimeCounter_Priv:                     \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGetRunTimeCounterImpl                 \n"
                 " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory"
@@ -408,12 +396,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGetRunTimePercent_Unpriv                \n"
                 " MPU_ulTaskGetRunTimePercent_Priv:                     \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGetRunTimePercentImpl                 \n"
                 " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory"
@@ -437,12 +424,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv            \n"
                 " MPU_ulTaskGetIdleRunTimePercent_Priv:                 \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGetIdleRunTimePercentImpl             \n"
                 " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory"
@@ -466,12 +452,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv            \n"
                 " MPU_ulTaskGetIdleRunTimeCounter_Priv:                 \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGetIdleRunTimeCounterImpl             \n"
                 " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory"
@@ -497,12 +482,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskSetApplicationTaskTag_Unpriv             \n"
                 " MPU_vTaskSetApplicationTaskTag_Priv:                  \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskSetApplicationTaskTagImpl              \n"
                 " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory"
@@ -526,12 +510,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGetApplicationTaskTag_Unpriv             \n"
                 " MPU_xTaskGetApplicationTaskTag_Priv:                  \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGetApplicationTaskTagImpl              \n"
                 " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory"
@@ -559,12 +542,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv      \n"
                 " MPU_vTaskSetThreadLocalStoragePointer_Priv:           \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskSetThreadLocalStoragePointerImpl       \n"
                 " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory"
@@ -590,12 +572,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv     \n"
                 " MPU_pvTaskGetThreadLocalStoragePointer_Priv:          \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_pvTaskGetThreadLocalStoragePointerImpl      \n"
                 " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory"
@@ -623,12 +604,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxTaskGetSystemState_Unpriv                   \n"
                 " MPU_uxTaskGetSystemState_Priv:                        \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxTaskGetSystemStateImpl                    \n"
                 " MPU_uxTaskGetSystemState_Unpriv:                      \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory"
@@ -652,12 +632,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxTaskGetStackHighWaterMark_Unpriv            \n"
                 " MPU_uxTaskGetStackHighWaterMark_Priv:                 \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxTaskGetStackHighWaterMarkImpl             \n"
                 " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory"
@@ -681,12 +660,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv           \n"
                 " MPU_uxTaskGetStackHighWaterMark2_Priv:                \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxTaskGetStackHighWaterMark2Impl            \n"
                 " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory"
@@ -710,12 +688,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGetCurrentTaskHandle_Unpriv              \n"
                 " MPU_xTaskGetCurrentTaskHandle_Priv:                   \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGetCurrentTaskHandleImpl               \n"
                 " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory"
@@ -739,12 +716,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGetSchedulerState_Unpriv                 \n"
                 " MPU_xTaskGetSchedulerState_Priv:                      \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGetSchedulerStateImpl                  \n"
                 " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory"
@@ -766,12 +742,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_vTaskSetTimeOutState_Unpriv                   \n"
             " MPU_vTaskSetTimeOutState_Priv:                        \n"
-            "     pop {r0}                                          \n"
             "     b MPU_vTaskSetTimeOutStateImpl                    \n"
             " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory"
@@ -793,12 +768,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xTaskCheckForTimeOut_Unpriv                   \n"
             " MPU_xTaskCheckForTimeOut_Priv:                        \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xTaskCheckForTimeOutImpl                    \n"
             " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory"
@@ -820,12 +794,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGenericNotify_Unpriv                     \n"
                 " MPU_xTaskGenericNotify_Priv:                          \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGenericNotifyImpl                      \n"
                 " MPU_xTaskGenericNotify_Unpriv:                        \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory"
@@ -849,12 +822,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGenericNotifyWait_Unpriv                 \n"
                 " MPU_xTaskGenericNotifyWait_Priv:                      \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGenericNotifyWaitImpl                  \n"
                 " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory"
@@ -882,12 +854,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGenericNotifyTake_Unpriv                \n"
                 " MPU_ulTaskGenericNotifyTake_Priv:                     \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGenericNotifyTakeImpl                 \n"
                 " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory"
@@ -913,12 +884,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGenericNotifyStateClear_Unpriv           \n"
                 " MPU_xTaskGenericNotifyStateClear_Priv:                \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGenericNotifyStateClearImpl            \n"
                 " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory"
@@ -946,12 +916,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGenericNotifyValueClear_Unpriv          \n"
                 " MPU_ulTaskGenericNotifyValueClear_Priv:               \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGenericNotifyValueClearImpl           \n"
                 " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory"
@@ -979,12 +948,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xQueueGenericSend_Unpriv                      \n"
             " MPU_xQueueGenericSend_Priv:                           \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xQueueGenericSendImpl                       \n"
             " MPU_xQueueGenericSend_Unpriv:                         \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory"
@@ -1004,12 +972,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_uxQueueMessagesWaiting_Unpriv                 \n"
             " MPU_uxQueueMessagesWaiting_Priv:                      \n"
-            "     pop {r0}                                          \n"
             "     b MPU_uxQueueMessagesWaitingImpl                  \n"
             " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory"
@@ -1029,12 +996,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_uxQueueSpacesAvailable_Unpriv                 \n"
             " MPU_uxQueueSpacesAvailable_Priv:                      \n"
-            "     pop {r0}                                          \n"
             "     b MPU_uxQueueSpacesAvailableImpl                  \n"
             " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory"
@@ -1058,12 +1024,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xQueueReceive_Unpriv                          \n"
             " MPU_xQueueReceive_Priv:                               \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xQueueReceiveImpl                           \n"
             " MPU_xQueueReceive_Unpriv:                             \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory"
@@ -1087,12 +1052,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xQueuePeek_Unpriv                             \n"
             " MPU_xQueuePeek_Priv:                                  \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xQueuePeekImpl                              \n"
             " MPU_xQueuePeek_Unpriv:                                \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory"
@@ -1114,12 +1078,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xQueueSemaphoreTake_Unpriv                    \n"
             " MPU_xQueueSemaphoreTake_Priv:                         \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xQueueSemaphoreTakeImpl                     \n"
             " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory"
@@ -1141,12 +1104,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xQueueGetMutexHolder_Unpriv                   \n"
                 " MPU_xQueueGetMutexHolder_Priv:                        \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xQueueGetMutexHolderImpl                    \n"
                 " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory"
@@ -1172,12 +1134,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xQueueTakeMutexRecursive_Unpriv               \n"
                 " MPU_xQueueTakeMutexRecursive_Priv:                    \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xQueueTakeMutexRecursiveImpl                \n"
                 " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory"
@@ -1201,12 +1162,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xQueueGiveMutexRecursive_Unpriv               \n"
                 " MPU_xQueueGiveMutexRecursive_Priv:                    \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xQueueGiveMutexRecursiveImpl                \n"
                 " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory"
@@ -1232,12 +1192,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xQueueSelectFromSet_Unpriv                    \n"
                 " MPU_xQueueSelectFromSet_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xQueueSelectFromSetImpl                     \n"
                 " MPU_xQueueSelectFromSet_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory"
@@ -1263,12 +1222,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xQueueAddToSet_Unpriv                         \n"
                 " MPU_xQueueAddToSet_Priv:                              \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xQueueAddToSetImpl                          \n"
                 " MPU_xQueueAddToSet_Unpriv:                            \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory"
@@ -1294,12 +1252,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vQueueAddToRegistry_Unpriv                    \n"
                 " MPU_vQueueAddToRegistry_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vQueueAddToRegistryImpl                     \n"
                 " MPU_vQueueAddToRegistry_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory"
@@ -1323,12 +1280,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vQueueUnregisterQueue_Unpriv                  \n"
                 " MPU_vQueueUnregisterQueue_Priv:                       \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vQueueUnregisterQueueImpl                   \n"
                 " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory"
@@ -1352,12 +1308,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_pcQueueGetName_Unpriv                         \n"
                 " MPU_pcQueueGetName_Priv:                              \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_pcQueueGetNameImpl                          \n"
                 " MPU_pcQueueGetName_Unpriv:                            \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory"
@@ -1381,12 +1336,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_pvTimerGetTimerID_Unpriv                      \n"
                 " MPU_pvTimerGetTimerID_Priv:                           \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_pvTimerGetTimerIDImpl                       \n"
                 " MPU_pvTimerGetTimerID_Unpriv:                         \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory"
@@ -1412,12 +1366,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTimerSetTimerID_Unpriv                       \n"
                 " MPU_vTimerSetTimerID_Priv:                            \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTimerSetTimerIDImpl                        \n"
                 " MPU_vTimerSetTimerID_Unpriv:                          \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory"
@@ -1441,12 +1394,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTimerIsTimerActive_Unpriv                    \n"
                 " MPU_xTimerIsTimerActive_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTimerIsTimerActiveImpl                     \n"
                 " MPU_xTimerIsTimerActive_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory"
@@ -1470,12 +1422,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv         \n"
                 " MPU_xTimerGetTimerDaemonTaskHandle_Priv:              \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTimerGetTimerDaemonTaskHandleImpl          \n"
                 " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory"
@@ -1493,20 +1444,19 @@
         {
             __asm volatile
             (
-                " .syntax unified                                               \n"
-                " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
-                "                                                               \n"
-                " push {r0}                                                     \n"
-                " mrs r0, control                                               \n"
-                " tst r0, #1                                                    \n"
-                " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
-                " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
-                "     pop {r0}                                                  \n"
-                "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
-                " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
-                "     pop {r0}                                                  \n"
-                "     svc %0                                                    \n"
-                "                                                               \n"
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGenericCommandFromTaskImpl          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xTimerGenericCommandFromTask_Unpriv           \n"
+                " MPU_xTimerGenericCommandFromTask_Priv:                \n"
+                "     b MPU_xTimerGenericCommandFromTaskImpl            \n"
+                " MPU_xTimerGenericCommandFromTask_Unpriv:              \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory"
             );
         }
@@ -1528,12 +1478,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_pcTimerGetName_Unpriv                         \n"
                 " MPU_pcTimerGetName_Priv:                              \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_pcTimerGetNameImpl                          \n"
                 " MPU_pcTimerGetName_Unpriv:                            \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory"
@@ -1559,12 +1508,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTimerSetReloadMode_Unpriv                    \n"
                 " MPU_vTimerSetReloadMode_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTimerSetReloadModeImpl                     \n"
                 " MPU_vTimerSetReloadMode_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory"
@@ -1588,12 +1536,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTimerGetReloadMode_Unpriv                    \n"
                 " MPU_xTimerGetReloadMode_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTimerGetReloadModeImpl                     \n"
                 " MPU_xTimerGetReloadMode_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory"
@@ -1617,12 +1564,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxTimerGetReloadMode_Unpriv                   \n"
                 " MPU_uxTimerGetReloadMode_Priv:                        \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxTimerGetReloadModeImpl                    \n"
                 " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory"
@@ -1646,12 +1592,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTimerGetPeriod_Unpriv                        \n"
                 " MPU_xTimerGetPeriod_Priv:                             \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTimerGetPeriodImpl                         \n"
                 " MPU_xTimerGetPeriod_Unpriv:                           \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory"
@@ -1675,12 +1620,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTimerGetExpiryTime_Unpriv                    \n"
                 " MPU_xTimerGetExpiryTime_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTimerGetExpiryTimeImpl                     \n"
                 " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory"
@@ -1702,12 +1646,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
             " MPU_xEventGroupWaitBits_Priv:                         \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xEventGroupWaitBitsImpl                     \n"
             " MPU_xEventGroupWaitBits_Unpriv:                       \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
@@ -1729,12 +1672,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xEventGroupClearBits_Unpriv                   \n"
             " MPU_xEventGroupClearBits_Priv:                        \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xEventGroupClearBitsImpl                    \n"
             " MPU_xEventGroupClearBits_Unpriv:                      \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
@@ -1756,12 +1698,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xEventGroupSetBits_Unpriv                     \n"
             " MPU_xEventGroupSetBits_Priv:                          \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xEventGroupSetBitsImpl                      \n"
             " MPU_xEventGroupSetBits_Unpriv:                        \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
@@ -1787,12 +1728,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xEventGroupSync_Unpriv                        \n"
             " MPU_xEventGroupSync_Priv:                             \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xEventGroupSyncImpl                         \n"
             " MPU_xEventGroupSync_Unpriv:                           \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
@@ -1814,12 +1754,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxEventGroupGetNumber_Unpriv                  \n"
                 " MPU_uxEventGroupGetNumber_Priv:                       \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxEventGroupGetNumberImpl                   \n"
                 " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory"
@@ -1845,12 +1784,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vEventGroupSetNumber_Unpriv                   \n"
                 " MPU_vEventGroupSetNumber_Priv:                        \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vEventGroupSetNumberImpl                    \n"
                 " MPU_vEventGroupSetNumber_Unpriv:                      \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory"
@@ -1878,12 +1816,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferSend_Unpriv                      \n"
             " MPU_xStreamBufferSend_Priv:                           \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferSendImpl                       \n"
             " MPU_xStreamBufferSend_Unpriv:                         \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
@@ -1909,12 +1846,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferReceive_Unpriv                   \n"
             " MPU_xStreamBufferReceive_Priv:                        \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferReceiveImpl                    \n"
             " MPU_xStreamBufferReceive_Unpriv:                      \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
@@ -1934,12 +1870,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
             " MPU_xStreamBufferIsFull_Priv:                         \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferIsFullImpl                     \n"
             " MPU_xStreamBufferIsFull_Unpriv:                       \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
@@ -1959,12 +1894,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
             " MPU_xStreamBufferIsEmpty_Priv:                        \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferIsEmptyImpl                    \n"
             " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
@@ -1984,12 +1918,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
             " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
             " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
@@ -2009,12 +1942,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
             " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferBytesAvailableImpl             \n"
             " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
@@ -2036,12 +1968,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
             " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
             " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
@@ -2061,12 +1992,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
             " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
             " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.c
index 170d10fcc..4f66448f9 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.c
@@ -62,12 +62,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskDelayUntil_Unpriv                        \n"
                 " MPU_xTaskDelayUntil_Priv:                             \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskDelayUntilImpl                         \n"
                 " MPU_xTaskDelayUntil_Unpriv:                           \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory"
@@ -91,12 +90,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskAbortDelay_Unpriv                        \n"
                 " MPU_xTaskAbortDelay_Priv:                             \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskAbortDelayImpl                         \n"
                 " MPU_xTaskAbortDelay_Unpriv:                           \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory"
@@ -120,12 +118,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskDelay_Unpriv                             \n"
                 " MPU_vTaskDelay_Priv:                                  \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskDelayImpl                              \n"
                 " MPU_vTaskDelay_Unpriv:                                \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory"
@@ -149,12 +146,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxTaskPriorityGet_Unpriv                      \n"
                 " MPU_uxTaskPriorityGet_Priv:                           \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxTaskPriorityGetImpl                       \n"
                 " MPU_uxTaskPriorityGet_Unpriv:                         \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory"
@@ -178,12 +174,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_eTaskGetState_Unpriv                          \n"
                 " MPU_eTaskGetState_Priv:                               \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_eTaskGetStateImpl                           \n"
                 " MPU_eTaskGetState_Unpriv:                             \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory"
@@ -213,12 +208,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskGetInfo_Unpriv                           \n"
                 " MPU_vTaskGetInfo_Priv:                                \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskGetInfoImpl                            \n"
                 " MPU_vTaskGetInfo_Unpriv:                              \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory"
@@ -242,12 +236,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGetIdleTaskHandle_Unpriv                 \n"
                 " MPU_xTaskGetIdleTaskHandle_Priv:                      \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGetIdleTaskHandleImpl                  \n"
                 " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory"
@@ -271,12 +264,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskSuspend_Unpriv                           \n"
                 " MPU_vTaskSuspend_Priv:                                \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskSuspendImpl                            \n"
                 " MPU_vTaskSuspend_Unpriv:                              \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory"
@@ -300,12 +292,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskResume_Unpriv                            \n"
                 " MPU_vTaskResume_Priv:                                 \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskResumeImpl                             \n"
                 " MPU_vTaskResume_Unpriv:                               \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskResume ) : "memory"
@@ -327,12 +318,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xTaskGetTickCount_Unpriv                      \n"
             " MPU_xTaskGetTickCount_Priv:                           \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xTaskGetTickCountImpl                       \n"
             " MPU_xTaskGetTickCount_Unpriv:                         \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory"
@@ -352,12 +342,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_uxTaskGetNumberOfTasks_Unpriv                 \n"
             " MPU_uxTaskGetNumberOfTasks_Priv:                      \n"
-            "     pop {r0}                                          \n"
             "     b MPU_uxTaskGetNumberOfTasksImpl                  \n"
             " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory"
@@ -379,12 +368,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGetRunTimeCounter_Unpriv                \n"
                 " MPU_ulTaskGetRunTimeCounter_Priv:                     \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGetRunTimeCounterImpl                 \n"
                 " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory"
@@ -408,12 +396,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGetRunTimePercent_Unpriv                \n"
                 " MPU_ulTaskGetRunTimePercent_Priv:                     \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGetRunTimePercentImpl                 \n"
                 " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory"
@@ -437,12 +424,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv            \n"
                 " MPU_ulTaskGetIdleRunTimePercent_Priv:                 \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGetIdleRunTimePercentImpl             \n"
                 " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory"
@@ -466,12 +452,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv            \n"
                 " MPU_ulTaskGetIdleRunTimeCounter_Priv:                 \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGetIdleRunTimeCounterImpl             \n"
                 " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory"
@@ -497,12 +482,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskSetApplicationTaskTag_Unpriv             \n"
                 " MPU_vTaskSetApplicationTaskTag_Priv:                  \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskSetApplicationTaskTagImpl              \n"
                 " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory"
@@ -526,12 +510,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGetApplicationTaskTag_Unpriv             \n"
                 " MPU_xTaskGetApplicationTaskTag_Priv:                  \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGetApplicationTaskTagImpl              \n"
                 " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory"
@@ -559,12 +542,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv      \n"
                 " MPU_vTaskSetThreadLocalStoragePointer_Priv:           \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTaskSetThreadLocalStoragePointerImpl       \n"
                 " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory"
@@ -590,12 +572,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv     \n"
                 " MPU_pvTaskGetThreadLocalStoragePointer_Priv:          \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_pvTaskGetThreadLocalStoragePointerImpl      \n"
                 " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory"
@@ -623,12 +604,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxTaskGetSystemState_Unpriv                   \n"
                 " MPU_uxTaskGetSystemState_Priv:                        \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxTaskGetSystemStateImpl                    \n"
                 " MPU_uxTaskGetSystemState_Unpriv:                      \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory"
@@ -652,12 +632,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxTaskGetStackHighWaterMark_Unpriv            \n"
                 " MPU_uxTaskGetStackHighWaterMark_Priv:                 \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxTaskGetStackHighWaterMarkImpl             \n"
                 " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory"
@@ -681,12 +660,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv           \n"
                 " MPU_uxTaskGetStackHighWaterMark2_Priv:                \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxTaskGetStackHighWaterMark2Impl            \n"
                 " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory"
@@ -710,12 +688,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGetCurrentTaskHandle_Unpriv              \n"
                 " MPU_xTaskGetCurrentTaskHandle_Priv:                   \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGetCurrentTaskHandleImpl               \n"
                 " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory"
@@ -739,12 +716,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGetSchedulerState_Unpriv                 \n"
                 " MPU_xTaskGetSchedulerState_Priv:                      \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGetSchedulerStateImpl                  \n"
                 " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory"
@@ -766,12 +742,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_vTaskSetTimeOutState_Unpriv                   \n"
             " MPU_vTaskSetTimeOutState_Priv:                        \n"
-            "     pop {r0}                                          \n"
             "     b MPU_vTaskSetTimeOutStateImpl                    \n"
             " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory"
@@ -793,12 +768,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xTaskCheckForTimeOut_Unpriv                   \n"
             " MPU_xTaskCheckForTimeOut_Priv:                        \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xTaskCheckForTimeOutImpl                    \n"
             " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory"
@@ -820,12 +794,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGenericNotify_Unpriv                     \n"
                 " MPU_xTaskGenericNotify_Priv:                          \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGenericNotifyImpl                      \n"
                 " MPU_xTaskGenericNotify_Unpriv:                        \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory"
@@ -849,12 +822,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGenericNotifyWait_Unpriv                 \n"
                 " MPU_xTaskGenericNotifyWait_Priv:                      \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGenericNotifyWaitImpl                  \n"
                 " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory"
@@ -882,12 +854,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGenericNotifyTake_Unpriv                \n"
                 " MPU_ulTaskGenericNotifyTake_Priv:                     \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGenericNotifyTakeImpl                 \n"
                 " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory"
@@ -913,12 +884,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTaskGenericNotifyStateClear_Unpriv           \n"
                 " MPU_xTaskGenericNotifyStateClear_Priv:                \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTaskGenericNotifyStateClearImpl            \n"
                 " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory"
@@ -946,12 +916,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_ulTaskGenericNotifyValueClear_Unpriv          \n"
                 " MPU_ulTaskGenericNotifyValueClear_Priv:               \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_ulTaskGenericNotifyValueClearImpl           \n"
                 " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory"
@@ -979,12 +948,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xQueueGenericSend_Unpriv                      \n"
             " MPU_xQueueGenericSend_Priv:                           \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xQueueGenericSendImpl                       \n"
             " MPU_xQueueGenericSend_Unpriv:                         \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory"
@@ -1004,12 +972,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_uxQueueMessagesWaiting_Unpriv                 \n"
             " MPU_uxQueueMessagesWaiting_Priv:                      \n"
-            "     pop {r0}                                          \n"
             "     b MPU_uxQueueMessagesWaitingImpl                  \n"
             " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory"
@@ -1029,12 +996,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_uxQueueSpacesAvailable_Unpriv                 \n"
             " MPU_uxQueueSpacesAvailable_Priv:                      \n"
-            "     pop {r0}                                          \n"
             "     b MPU_uxQueueSpacesAvailableImpl                  \n"
             " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory"
@@ -1058,12 +1024,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xQueueReceive_Unpriv                          \n"
             " MPU_xQueueReceive_Priv:                               \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xQueueReceiveImpl                           \n"
             " MPU_xQueueReceive_Unpriv:                             \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory"
@@ -1087,12 +1052,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xQueuePeek_Unpriv                             \n"
             " MPU_xQueuePeek_Priv:                                  \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xQueuePeekImpl                              \n"
             " MPU_xQueuePeek_Unpriv:                                \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory"
@@ -1114,12 +1078,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xQueueSemaphoreTake_Unpriv                    \n"
             " MPU_xQueueSemaphoreTake_Priv:                         \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xQueueSemaphoreTakeImpl                     \n"
             " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory"
@@ -1141,12 +1104,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xQueueGetMutexHolder_Unpriv                   \n"
                 " MPU_xQueueGetMutexHolder_Priv:                        \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xQueueGetMutexHolderImpl                    \n"
                 " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory"
@@ -1172,12 +1134,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xQueueTakeMutexRecursive_Unpriv               \n"
                 " MPU_xQueueTakeMutexRecursive_Priv:                    \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xQueueTakeMutexRecursiveImpl                \n"
                 " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory"
@@ -1201,12 +1162,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xQueueGiveMutexRecursive_Unpriv               \n"
                 " MPU_xQueueGiveMutexRecursive_Priv:                    \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xQueueGiveMutexRecursiveImpl                \n"
                 " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory"
@@ -1232,12 +1192,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xQueueSelectFromSet_Unpriv                    \n"
                 " MPU_xQueueSelectFromSet_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xQueueSelectFromSetImpl                     \n"
                 " MPU_xQueueSelectFromSet_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory"
@@ -1263,12 +1222,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xQueueAddToSet_Unpriv                         \n"
                 " MPU_xQueueAddToSet_Priv:                              \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xQueueAddToSetImpl                          \n"
                 " MPU_xQueueAddToSet_Unpriv:                            \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory"
@@ -1294,12 +1252,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vQueueAddToRegistry_Unpriv                    \n"
                 " MPU_vQueueAddToRegistry_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vQueueAddToRegistryImpl                     \n"
                 " MPU_vQueueAddToRegistry_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory"
@@ -1323,12 +1280,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vQueueUnregisterQueue_Unpriv                  \n"
                 " MPU_vQueueUnregisterQueue_Priv:                       \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vQueueUnregisterQueueImpl                   \n"
                 " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory"
@@ -1352,12 +1308,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_pcQueueGetName_Unpriv                         \n"
                 " MPU_pcQueueGetName_Priv:                              \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_pcQueueGetNameImpl                          \n"
                 " MPU_pcQueueGetName_Unpriv:                            \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory"
@@ -1381,12 +1336,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_pvTimerGetTimerID_Unpriv                      \n"
                 " MPU_pvTimerGetTimerID_Priv:                           \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_pvTimerGetTimerIDImpl                       \n"
                 " MPU_pvTimerGetTimerID_Unpriv:                         \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory"
@@ -1412,12 +1366,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTimerSetTimerID_Unpriv                       \n"
                 " MPU_vTimerSetTimerID_Priv:                            \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTimerSetTimerIDImpl                        \n"
                 " MPU_vTimerSetTimerID_Unpriv:                          \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory"
@@ -1441,12 +1394,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTimerIsTimerActive_Unpriv                    \n"
                 " MPU_xTimerIsTimerActive_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTimerIsTimerActiveImpl                     \n"
                 " MPU_xTimerIsTimerActive_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory"
@@ -1470,12 +1422,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv         \n"
                 " MPU_xTimerGetTimerDaemonTaskHandle_Priv:              \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTimerGetTimerDaemonTaskHandleImpl          \n"
                 " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory"
@@ -1493,20 +1444,19 @@
         {
             __asm volatile
             (
-                " .syntax unified                                               \n"
-                " .extern MPU_xTimerGenericCommandFromTaskImpl                  \n"
-                "                                                               \n"
-                " push {r0}                                                     \n"
-                " mrs r0, control                                               \n"
-                " tst r0, #1                                                    \n"
-                " bne MPU_xTimerGenericCommandFromTask_Unpriv                   \n"
-                " MPU_xTimerGenericCommandFromTask_Priv:                        \n"
-                "     pop {r0}                                                  \n"
-                "     b MPU_xTimerGenericCommandFromTaskImpl                    \n"
-                " MPU_xTimerGenericCommandFromTask_Unpriv:                      \n"
-                "     pop {r0}                                                  \n"
-                "     svc %0                                                    \n"
-                "                                                               \n"
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGenericCommandFromTaskImpl          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xTimerGenericCommandFromTask_Unpriv           \n"
+                " MPU_xTimerGenericCommandFromTask_Priv:                \n"
+                "     b MPU_xTimerGenericCommandFromTaskImpl            \n"
+                " MPU_xTimerGenericCommandFromTask_Unpriv:              \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory"
             );
         }
@@ -1528,12 +1478,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_pcTimerGetName_Unpriv                         \n"
                 " MPU_pcTimerGetName_Priv:                              \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_pcTimerGetNameImpl                          \n"
                 " MPU_pcTimerGetName_Unpriv:                            \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory"
@@ -1559,12 +1508,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vTimerSetReloadMode_Unpriv                    \n"
                 " MPU_vTimerSetReloadMode_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vTimerSetReloadModeImpl                     \n"
                 " MPU_vTimerSetReloadMode_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory"
@@ -1588,12 +1536,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTimerGetReloadMode_Unpriv                    \n"
                 " MPU_xTimerGetReloadMode_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTimerGetReloadModeImpl                     \n"
                 " MPU_xTimerGetReloadMode_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory"
@@ -1617,12 +1564,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxTimerGetReloadMode_Unpriv                   \n"
                 " MPU_uxTimerGetReloadMode_Priv:                        \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxTimerGetReloadModeImpl                    \n"
                 " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory"
@@ -1646,12 +1592,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTimerGetPeriod_Unpriv                        \n"
                 " MPU_xTimerGetPeriod_Priv:                             \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTimerGetPeriodImpl                         \n"
                 " MPU_xTimerGetPeriod_Unpriv:                           \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory"
@@ -1675,12 +1620,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_xTimerGetExpiryTime_Unpriv                    \n"
                 " MPU_xTimerGetExpiryTime_Priv:                         \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_xTimerGetExpiryTimeImpl                     \n"
                 " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory"
@@ -1702,12 +1646,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
             " MPU_xEventGroupWaitBits_Priv:                         \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xEventGroupWaitBitsImpl                     \n"
             " MPU_xEventGroupWaitBits_Unpriv:                       \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
@@ -1729,12 +1672,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xEventGroupClearBits_Unpriv                   \n"
             " MPU_xEventGroupClearBits_Priv:                        \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xEventGroupClearBitsImpl                    \n"
             " MPU_xEventGroupClearBits_Unpriv:                      \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
@@ -1756,12 +1698,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xEventGroupSetBits_Unpriv                     \n"
             " MPU_xEventGroupSetBits_Priv:                          \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xEventGroupSetBitsImpl                      \n"
             " MPU_xEventGroupSetBits_Unpriv:                        \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
@@ -1787,12 +1728,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xEventGroupSync_Unpriv                        \n"
             " MPU_xEventGroupSync_Priv:                             \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xEventGroupSyncImpl                         \n"
             " MPU_xEventGroupSync_Unpriv:                           \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
@@ -1814,12 +1754,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_uxEventGroupGetNumber_Unpriv                  \n"
                 " MPU_uxEventGroupGetNumber_Priv:                       \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_uxEventGroupGetNumberImpl                   \n"
                 " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory"
@@ -1845,12 +1784,11 @@
                 " push {r0}                                             \n"
                 " mrs r0, control                                       \n"
                 " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
                 " bne MPU_vEventGroupSetNumber_Unpriv                   \n"
                 " MPU_vEventGroupSetNumber_Priv:                        \n"
-                "     pop {r0}                                          \n"
                 "     b MPU_vEventGroupSetNumberImpl                    \n"
                 " MPU_vEventGroupSetNumber_Unpriv:                      \n"
-                "     pop {r0}                                          \n"
                 "     svc %0                                            \n"
                 "                                                       \n"
                 : : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory"
@@ -1878,12 +1816,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferSend_Unpriv                      \n"
             " MPU_xStreamBufferSend_Priv:                           \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferSendImpl                       \n"
             " MPU_xStreamBufferSend_Unpriv:                         \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
@@ -1909,12 +1846,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferReceive_Unpriv                   \n"
             " MPU_xStreamBufferReceive_Priv:                        \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferReceiveImpl                    \n"
             " MPU_xStreamBufferReceive_Unpriv:                      \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
@@ -1934,12 +1870,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
             " MPU_xStreamBufferIsFull_Priv:                         \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferIsFullImpl                     \n"
             " MPU_xStreamBufferIsFull_Unpriv:                       \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
@@ -1959,12 +1894,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
             " MPU_xStreamBufferIsEmpty_Priv:                        \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferIsEmptyImpl                    \n"
             " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
@@ -1984,12 +1918,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
             " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
             " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
@@ -2009,12 +1942,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
             " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferBytesAvailableImpl             \n"
             " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
@@ -2036,12 +1968,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
             " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
             " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
@@ -2061,12 +1992,11 @@
             " push {r0}                                             \n"
             " mrs r0, control                                       \n"
             " tst r0, #1                                            \n"
+            " pop {r0}                                              \n"
             " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
             " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
-            "     pop {r0}                                          \n"
             "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
             " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
-            "     pop {r0}                                          \n"
             "     svc %0                                            \n"
             "                                                       \n"
             : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
diff --git a/portable/IAR/ARM_CM23/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM23/non_secure/mpu_wrappers_v2_asm.S
index 8ea2f5c78..9289bcbc2 100644
--- a/portable/IAR/ARM_CM23/non_secure/mpu_wrappers_v2_asm.S
+++ b/portable/IAR/ARM_CM23/non_secure/mpu_wrappers_v2_asm.S
@@ -48,12 +48,11 @@ MPU_xTaskDelayUntil:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTaskDelayUntil_Unpriv
     MPU_xTaskDelayUntil_Priv:
-        pop {r0, r1}
         b MPU_xTaskDelayUntilImpl
     MPU_xTaskDelayUntil_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTaskDelayUntil
 /*-----------------------------------------------------------*/
 
@@ -63,12 +62,11 @@ MPU_xTaskAbortDelay:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTaskAbortDelay_Unpriv
     MPU_xTaskAbortDelay_Priv:
-        pop {r0, r1}
         b MPU_xTaskAbortDelayImpl
     MPU_xTaskAbortDelay_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTaskAbortDelay
 /*-----------------------------------------------------------*/
 
@@ -78,12 +76,11 @@ MPU_vTaskDelay:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_vTaskDelay_Unpriv
     MPU_vTaskDelay_Priv:
-        pop {r0, r1}
         b MPU_vTaskDelayImpl
     MPU_vTaskDelay_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_vTaskDelay
 /*-----------------------------------------------------------*/
 
@@ -93,12 +90,11 @@ MPU_uxTaskPriorityGet:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_uxTaskPriorityGet_Unpriv
     MPU_uxTaskPriorityGet_Priv:
-        pop {r0, r1}
         b MPU_uxTaskPriorityGetImpl
     MPU_uxTaskPriorityGet_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_uxTaskPriorityGet
 /*-----------------------------------------------------------*/
 
@@ -108,12 +104,11 @@ MPU_eTaskGetState:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_eTaskGetState_Unpriv
     MPU_eTaskGetState_Priv:
-        pop {r0, r1}
         b MPU_eTaskGetStateImpl
     MPU_eTaskGetState_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_eTaskGetState
 /*-----------------------------------------------------------*/
 
@@ -123,12 +118,11 @@ MPU_vTaskGetInfo:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_vTaskGetInfo_Unpriv
     MPU_vTaskGetInfo_Priv:
-        pop {r0, r1}
         b MPU_vTaskGetInfoImpl
     MPU_vTaskGetInfo_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_vTaskGetInfo
 /*-----------------------------------------------------------*/
 
@@ -138,12 +132,11 @@ MPU_xTaskGetIdleTaskHandle:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTaskGetIdleTaskHandle_Unpriv
     MPU_xTaskGetIdleTaskHandle_Priv:
-        pop {r0, r1}
         b MPU_xTaskGetIdleTaskHandleImpl
     MPU_xTaskGetIdleTaskHandle_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTaskGetIdleTaskHandle
 /*-----------------------------------------------------------*/
 
@@ -153,12 +146,11 @@ MPU_vTaskSuspend:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_vTaskSuspend_Unpriv
     MPU_vTaskSuspend_Priv:
-        pop {r0, r1}
         b MPU_vTaskSuspendImpl
     MPU_vTaskSuspend_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_vTaskSuspend
 /*-----------------------------------------------------------*/
 
@@ -168,12 +160,11 @@ MPU_vTaskResume:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_vTaskResume_Unpriv
     MPU_vTaskResume_Priv:
-        pop {r0, r1}
         b MPU_vTaskResumeImpl
     MPU_vTaskResume_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_vTaskResume
 /*-----------------------------------------------------------*/
 
@@ -183,12 +174,11 @@ MPU_xTaskGetTickCount:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTaskGetTickCount_Unpriv
     MPU_xTaskGetTickCount_Priv:
-        pop {r0, r1}
         b MPU_xTaskGetTickCountImpl
     MPU_xTaskGetTickCount_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTaskGetTickCount
 /*-----------------------------------------------------------*/
 
@@ -198,12 +188,11 @@ MPU_uxTaskGetNumberOfTasks:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_uxTaskGetNumberOfTasks_Unpriv
     MPU_uxTaskGetNumberOfTasks_Priv:
-        pop {r0, r1}
         b MPU_uxTaskGetNumberOfTasksImpl
     MPU_uxTaskGetNumberOfTasks_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_uxTaskGetNumberOfTasks
 /*-----------------------------------------------------------*/
 
@@ -213,12 +202,11 @@ MPU_ulTaskGetRunTimeCounter:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_ulTaskGetRunTimeCounter_Unpriv
     MPU_ulTaskGetRunTimeCounter_Priv:
-        pop {r0, r1}
         b MPU_ulTaskGetRunTimeCounterImpl
     MPU_ulTaskGetRunTimeCounter_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_ulTaskGetRunTimeCounter
 /*-----------------------------------------------------------*/
 
@@ -228,12 +216,11 @@ MPU_ulTaskGetRunTimePercent:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_ulTaskGetRunTimePercent_Unpriv
     MPU_ulTaskGetRunTimePercent_Priv:
-        pop {r0, r1}
         b MPU_ulTaskGetRunTimePercentImpl
     MPU_ulTaskGetRunTimePercent_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_ulTaskGetRunTimePercent
 /*-----------------------------------------------------------*/
 
@@ -243,12 +230,11 @@ MPU_ulTaskGetIdleRunTimePercent:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_ulTaskGetIdleRunTimePercent_Unpriv
     MPU_ulTaskGetIdleRunTimePercent_Priv:
-        pop {r0, r1}
         b MPU_ulTaskGetIdleRunTimePercentImpl
     MPU_ulTaskGetIdleRunTimePercent_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent
 /*-----------------------------------------------------------*/
 
@@ -258,12 +244,11 @@ MPU_ulTaskGetIdleRunTimeCounter:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv
     MPU_ulTaskGetIdleRunTimeCounter_Priv:
-        pop {r0, r1}
         b MPU_ulTaskGetIdleRunTimeCounterImpl
     MPU_ulTaskGetIdleRunTimeCounter_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter
 /*-----------------------------------------------------------*/
 
@@ -273,12 +258,11 @@ MPU_vTaskSetApplicationTaskTag:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_vTaskSetApplicationTaskTag_Unpriv
     MPU_vTaskSetApplicationTaskTag_Priv:
-        pop {r0, r1}
         b MPU_vTaskSetApplicationTaskTagImpl
     MPU_vTaskSetApplicationTaskTag_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_vTaskSetApplicationTaskTag
 /*-----------------------------------------------------------*/
 
@@ -288,12 +272,11 @@ MPU_xTaskGetApplicationTaskTag:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTaskGetApplicationTaskTag_Unpriv
     MPU_xTaskGetApplicationTaskTag_Priv:
-        pop {r0, r1}
         b MPU_xTaskGetApplicationTaskTagImpl
     MPU_xTaskGetApplicationTaskTag_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTaskGetApplicationTaskTag
 /*-----------------------------------------------------------*/
 
@@ -303,12 +286,11 @@ MPU_vTaskSetThreadLocalStoragePointer:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv
     MPU_vTaskSetThreadLocalStoragePointer_Priv:
-        pop {r0, r1}
         b MPU_vTaskSetThreadLocalStoragePointerImpl
     MPU_vTaskSetThreadLocalStoragePointer_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer
 /*-----------------------------------------------------------*/
 
@@ -318,12 +300,11 @@ MPU_pvTaskGetThreadLocalStoragePointer:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv
     MPU_pvTaskGetThreadLocalStoragePointer_Priv:
-        pop {r0, r1}
         b MPU_pvTaskGetThreadLocalStoragePointerImpl
     MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer
 /*-----------------------------------------------------------*/
 
@@ -333,12 +314,11 @@ MPU_uxTaskGetSystemState:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_uxTaskGetSystemState_Unpriv
     MPU_uxTaskGetSystemState_Priv:
-        pop {r0, r1}
         b MPU_uxTaskGetSystemStateImpl
     MPU_uxTaskGetSystemState_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_uxTaskGetSystemState
 /*-----------------------------------------------------------*/
 
@@ -348,12 +328,11 @@ MPU_uxTaskGetStackHighWaterMark:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_uxTaskGetStackHighWaterMark_Unpriv
     MPU_uxTaskGetStackHighWaterMark_Priv:
-        pop {r0, r1}
         b MPU_uxTaskGetStackHighWaterMarkImpl
     MPU_uxTaskGetStackHighWaterMark_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark
 /*-----------------------------------------------------------*/
 
@@ -363,12 +342,11 @@ MPU_uxTaskGetStackHighWaterMark2:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_uxTaskGetStackHighWaterMark2_Unpriv
     MPU_uxTaskGetStackHighWaterMark2_Priv:
-        pop {r0, r1}
         b MPU_uxTaskGetStackHighWaterMark2Impl
     MPU_uxTaskGetStackHighWaterMark2_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2
 /*-----------------------------------------------------------*/
 
@@ -378,12 +356,11 @@ MPU_xTaskGetCurrentTaskHandle:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTaskGetCurrentTaskHandle_Unpriv
     MPU_xTaskGetCurrentTaskHandle_Priv:
-        pop {r0, r1}
         b MPU_xTaskGetCurrentTaskHandleImpl
     MPU_xTaskGetCurrentTaskHandle_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle
 /*-----------------------------------------------------------*/
 
@@ -393,12 +370,11 @@ MPU_xTaskGetSchedulerState:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTaskGetSchedulerState_Unpriv
     MPU_xTaskGetSchedulerState_Priv:
-        pop {r0, r1}
         b MPU_xTaskGetSchedulerStateImpl
     MPU_xTaskGetSchedulerState_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTaskGetSchedulerState
 /*-----------------------------------------------------------*/
 
@@ -408,12 +384,11 @@ MPU_vTaskSetTimeOutState:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_vTaskSetTimeOutState_Unpriv
     MPU_vTaskSetTimeOutState_Priv:
-        pop {r0, r1}
         b MPU_vTaskSetTimeOutStateImpl
     MPU_vTaskSetTimeOutState_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_vTaskSetTimeOutState
 /*-----------------------------------------------------------*/
 
@@ -423,12 +398,11 @@ MPU_xTaskCheckForTimeOut:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTaskCheckForTimeOut_Unpriv
     MPU_xTaskCheckForTimeOut_Priv:
-        pop {r0, r1}
         b MPU_xTaskCheckForTimeOutImpl
     MPU_xTaskCheckForTimeOut_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTaskCheckForTimeOut
 /*-----------------------------------------------------------*/
 
@@ -438,12 +412,11 @@ MPU_xTaskGenericNotifyEntry:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTaskGenericNotify_Unpriv
     MPU_xTaskGenericNotify_Priv:
-        pop {r0, r1}
         b MPU_xTaskGenericNotifyImpl
     MPU_xTaskGenericNotify_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTaskGenericNotify
 /*-----------------------------------------------------------*/
 
@@ -453,12 +426,11 @@ MPU_xTaskGenericNotifyWaitEntry:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTaskGenericNotifyWait_Unpriv
     MPU_xTaskGenericNotifyWait_Priv:
-        pop {r0, r1}
         b MPU_xTaskGenericNotifyWaitImpl
     MPU_xTaskGenericNotifyWait_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTaskGenericNotifyWait
 /*-----------------------------------------------------------*/
 
@@ -468,12 +440,11 @@ MPU_ulTaskGenericNotifyTake:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_ulTaskGenericNotifyTake_Unpriv
     MPU_ulTaskGenericNotifyTake_Priv:
-        pop {r0, r1}
         b MPU_ulTaskGenericNotifyTakeImpl
     MPU_ulTaskGenericNotifyTake_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_ulTaskGenericNotifyTake
 /*-----------------------------------------------------------*/
 
@@ -483,12 +454,11 @@ MPU_xTaskGenericNotifyStateClear:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTaskGenericNotifyStateClear_Unpriv
     MPU_xTaskGenericNotifyStateClear_Priv:
-        pop {r0, r1}
         b MPU_xTaskGenericNotifyStateClearImpl
     MPU_xTaskGenericNotifyStateClear_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTaskGenericNotifyStateClear
 /*-----------------------------------------------------------*/
 
@@ -498,12 +468,11 @@ MPU_ulTaskGenericNotifyValueClear:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_ulTaskGenericNotifyValueClear_Unpriv
     MPU_ulTaskGenericNotifyValueClear_Priv:
-        pop {r0, r1}
         b MPU_ulTaskGenericNotifyValueClearImpl
     MPU_ulTaskGenericNotifyValueClear_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear
 /*-----------------------------------------------------------*/
 
@@ -513,12 +482,11 @@ MPU_xQueueGenericSend:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xQueueGenericSend_Unpriv
     MPU_xQueueGenericSend_Priv:
-        pop {r0, r1}
         b MPU_xQueueGenericSendImpl
     MPU_xQueueGenericSend_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xQueueGenericSend
 /*-----------------------------------------------------------*/
 
@@ -528,12 +496,11 @@ MPU_uxQueueMessagesWaiting:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_uxQueueMessagesWaiting_Unpriv
     MPU_uxQueueMessagesWaiting_Priv:
-        pop {r0, r1}
         b MPU_uxQueueMessagesWaitingImpl
     MPU_uxQueueMessagesWaiting_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_uxQueueMessagesWaiting
 /*-----------------------------------------------------------*/
 
@@ -543,12 +510,11 @@ MPU_uxQueueSpacesAvailable:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_uxQueueSpacesAvailable_Unpriv
     MPU_uxQueueSpacesAvailable_Priv:
-        pop {r0, r1}
         b MPU_uxQueueSpacesAvailableImpl
     MPU_uxQueueSpacesAvailable_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_uxQueueSpacesAvailable
 /*-----------------------------------------------------------*/
 
@@ -558,12 +524,11 @@ MPU_xQueueReceive:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xQueueReceive_Unpriv
     MPU_xQueueReceive_Priv:
-        pop {r0, r1}
         b MPU_xQueueReceiveImpl
     MPU_xQueueReceive_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xQueueReceive
 /*-----------------------------------------------------------*/
 
@@ -573,12 +538,11 @@ MPU_xQueuePeek:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xQueuePeek_Unpriv
     MPU_xQueuePeek_Priv:
-        pop {r0, r1}
         b MPU_xQueuePeekImpl
     MPU_xQueuePeek_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xQueuePeek
 /*-----------------------------------------------------------*/
 
@@ -588,12 +552,11 @@ MPU_xQueueSemaphoreTake:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xQueueSemaphoreTake_Unpriv
     MPU_xQueueSemaphoreTake_Priv:
-        pop {r0, r1}
         b MPU_xQueueSemaphoreTakeImpl
     MPU_xQueueSemaphoreTake_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xQueueSemaphoreTake
 /*-----------------------------------------------------------*/
 
@@ -603,12 +566,11 @@ MPU_xQueueGetMutexHolder:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xQueueGetMutexHolder_Unpriv
     MPU_xQueueGetMutexHolder_Priv:
-        pop {r0, r1}
         b MPU_xQueueGetMutexHolderImpl
     MPU_xQueueGetMutexHolder_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xQueueGetMutexHolder
 /*-----------------------------------------------------------*/
 
@@ -618,12 +580,11 @@ MPU_xQueueTakeMutexRecursive:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xQueueTakeMutexRecursive_Unpriv
     MPU_xQueueTakeMutexRecursive_Priv:
-        pop {r0, r1}
         b MPU_xQueueTakeMutexRecursiveImpl
     MPU_xQueueTakeMutexRecursive_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xQueueTakeMutexRecursive
 /*-----------------------------------------------------------*/
 
@@ -633,12 +594,11 @@ MPU_xQueueGiveMutexRecursive:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xQueueGiveMutexRecursive_Unpriv
     MPU_xQueueGiveMutexRecursive_Priv:
-        pop {r0, r1}
         b MPU_xQueueGiveMutexRecursiveImpl
     MPU_xQueueGiveMutexRecursive_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xQueueGiveMutexRecursive
 /*-----------------------------------------------------------*/
 
@@ -648,12 +608,11 @@ MPU_xQueueSelectFromSet:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xQueueSelectFromSet_Unpriv
     MPU_xQueueSelectFromSet_Priv:
-        pop {r0, r1}
         b MPU_xQueueSelectFromSetImpl
     MPU_xQueueSelectFromSet_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xQueueSelectFromSet
 /*-----------------------------------------------------------*/
 
@@ -663,12 +622,11 @@ MPU_xQueueAddToSet:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xQueueAddToSet_Unpriv
     MPU_xQueueAddToSet_Priv:
-        pop {r0, r1}
         b MPU_xQueueAddToSetImpl
     MPU_xQueueAddToSet_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xQueueAddToSet
 /*-----------------------------------------------------------*/
 
@@ -678,12 +636,11 @@ MPU_vQueueAddToRegistry:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_vQueueAddToRegistry_Unpriv
     MPU_vQueueAddToRegistry_Priv:
-        pop {r0, r1}
         b MPU_vQueueAddToRegistryImpl
     MPU_vQueueAddToRegistry_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_vQueueAddToRegistry
 /*-----------------------------------------------------------*/
 
@@ -693,12 +650,11 @@ MPU_vQueueUnregisterQueue:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_vQueueUnregisterQueue_Unpriv
     MPU_vQueueUnregisterQueue_Priv:
-        pop {r0, r1}
         b MPU_vQueueUnregisterQueueImpl
     MPU_vQueueUnregisterQueue_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_vQueueUnregisterQueue
 /*-----------------------------------------------------------*/
 
@@ -708,12 +664,11 @@ MPU_pcQueueGetName:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_pcQueueGetName_Unpriv
     MPU_pcQueueGetName_Priv:
-        pop {r0, r1}
         b MPU_pcQueueGetNameImpl
     MPU_pcQueueGetName_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_pcQueueGetName
 /*-----------------------------------------------------------*/
 
@@ -723,12 +678,11 @@ MPU_pvTimerGetTimerID:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_pvTimerGetTimerID_Unpriv
     MPU_pvTimerGetTimerID_Priv:
-        pop {r0, r1}
         b MPU_pvTimerGetTimerIDImpl
     MPU_pvTimerGetTimerID_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_pvTimerGetTimerID
 /*-----------------------------------------------------------*/
 
@@ -738,12 +692,11 @@ MPU_vTimerSetTimerID:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_vTimerSetTimerID_Unpriv
     MPU_vTimerSetTimerID_Priv:
-        pop {r0, r1}
         b MPU_vTimerSetTimerIDImpl
     MPU_vTimerSetTimerID_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_vTimerSetTimerID
 /*-----------------------------------------------------------*/
 
@@ -753,12 +706,11 @@ MPU_xTimerIsTimerActive:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTimerIsTimerActive_Unpriv
     MPU_xTimerIsTimerActive_Priv:
-        pop {r0, r1}
         b MPU_xTimerIsTimerActiveImpl
     MPU_xTimerIsTimerActive_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTimerIsTimerActive
 /*-----------------------------------------------------------*/
 
@@ -768,12 +720,11 @@ MPU_xTimerGetTimerDaemonTaskHandle:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv
     MPU_xTimerGetTimerDaemonTaskHandle_Priv:
-        pop {r0, r1}
         b MPU_xTimerGetTimerDaemonTaskHandleImpl
     MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle
 /*-----------------------------------------------------------*/
 
@@ -783,12 +734,11 @@ MPU_xTimerGenericCommandFromTaskEntry:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTimerGenericCommandFromTask_Unpriv
     MPU_xTimerGenericCommandFromTask_Priv:
-        pop {r0, r1}
         b MPU_xTimerGenericCommandFromTaskImpl
     MPU_xTimerGenericCommandFromTask_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTimerGenericCommandFromTask
 /*-----------------------------------------------------------*/
 
@@ -798,12 +748,11 @@ MPU_pcTimerGetName:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_pcTimerGetName_Unpriv
     MPU_pcTimerGetName_Priv:
-        pop {r0, r1}
         b MPU_pcTimerGetNameImpl
     MPU_pcTimerGetName_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_pcTimerGetName
 /*-----------------------------------------------------------*/
 
@@ -813,12 +762,11 @@ MPU_vTimerSetReloadMode:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_vTimerSetReloadMode_Unpriv
     MPU_vTimerSetReloadMode_Priv:
-        pop {r0, r1}
         b MPU_vTimerSetReloadModeImpl
     MPU_vTimerSetReloadMode_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_vTimerSetReloadMode
 /*-----------------------------------------------------------*/
 
@@ -828,12 +776,11 @@ MPU_xTimerGetReloadMode:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTimerGetReloadMode_Unpriv
     MPU_xTimerGetReloadMode_Priv:
-        pop {r0, r1}
         b MPU_xTimerGetReloadModeImpl
     MPU_xTimerGetReloadMode_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTimerGetReloadMode
 /*-----------------------------------------------------------*/
 
@@ -843,12 +790,11 @@ MPU_uxTimerGetReloadMode:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_uxTimerGetReloadMode_Unpriv
     MPU_uxTimerGetReloadMode_Priv:
-        pop {r0, r1}
         b MPU_uxTimerGetReloadModeImpl
     MPU_uxTimerGetReloadMode_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_uxTimerGetReloadMode
 /*-----------------------------------------------------------*/
 
@@ -858,12 +804,11 @@ MPU_xTimerGetPeriod:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTimerGetPeriod_Unpriv
     MPU_xTimerGetPeriod_Priv:
-        pop {r0, r1}
         b MPU_xTimerGetPeriodImpl
     MPU_xTimerGetPeriod_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTimerGetPeriod
 /*-----------------------------------------------------------*/
 
@@ -873,12 +818,11 @@ MPU_xTimerGetExpiryTime:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTimerGetExpiryTime_Unpriv
     MPU_xTimerGetExpiryTime_Priv:
-        pop {r0, r1}
         b MPU_xTimerGetExpiryTimeImpl
     MPU_xTimerGetExpiryTime_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTimerGetExpiryTime
 /*-----------------------------------------------------------*/
 
@@ -888,12 +832,11 @@ MPU_xEventGroupWaitBitsEntry:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xEventGroupWaitBits_Unpriv
     MPU_xEventGroupWaitBits_Priv:
-        pop {r0, r1}
         b MPU_xEventGroupWaitBitsImpl
     MPU_xEventGroupWaitBits_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xEventGroupWaitBits
 /*-----------------------------------------------------------*/
 
@@ -903,12 +846,11 @@ MPU_xEventGroupClearBits:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xEventGroupClearBits_Unpriv
     MPU_xEventGroupClearBits_Priv:
-        pop {r0, r1}
         b MPU_xEventGroupClearBitsImpl
     MPU_xEventGroupClearBits_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xEventGroupClearBits
 /*-----------------------------------------------------------*/
 
@@ -918,12 +860,11 @@ MPU_xEventGroupSetBits:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xEventGroupSetBits_Unpriv
     MPU_xEventGroupSetBits_Priv:
-        pop {r0, r1}
         b MPU_xEventGroupSetBitsImpl
     MPU_xEventGroupSetBits_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xEventGroupSetBits
 /*-----------------------------------------------------------*/
 
@@ -933,12 +874,11 @@ MPU_xEventGroupSync:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xEventGroupSync_Unpriv
     MPU_xEventGroupSync_Priv:
-        pop {r0, r1}
         b MPU_xEventGroupSyncImpl
     MPU_xEventGroupSync_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xEventGroupSync
 /*-----------------------------------------------------------*/
 
@@ -948,12 +888,11 @@ MPU_uxEventGroupGetNumber:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_uxEventGroupGetNumber_Unpriv
     MPU_uxEventGroupGetNumber_Priv:
-        pop {r0, r1}
         b MPU_uxEventGroupGetNumberImpl
     MPU_uxEventGroupGetNumber_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_uxEventGroupGetNumber
 /*-----------------------------------------------------------*/
 
@@ -963,12 +902,11 @@ MPU_vEventGroupSetNumber:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_vEventGroupSetNumber_Unpriv
     MPU_vEventGroupSetNumber_Priv:
-        pop {r0, r1}
         b MPU_vEventGroupSetNumberImpl
     MPU_vEventGroupSetNumber_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_vEventGroupSetNumber
 /*-----------------------------------------------------------*/
 
@@ -978,12 +916,11 @@ MPU_xStreamBufferSend:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xStreamBufferSend_Unpriv
     MPU_xStreamBufferSend_Priv:
-        pop {r0, r1}
         b MPU_xStreamBufferSendImpl
     MPU_xStreamBufferSend_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xStreamBufferSend
 /*-----------------------------------------------------------*/
 
@@ -993,12 +930,11 @@ MPU_xStreamBufferReceive:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xStreamBufferReceive_Unpriv
     MPU_xStreamBufferReceive_Priv:
-        pop {r0, r1}
         b MPU_xStreamBufferReceiveImpl
     MPU_xStreamBufferReceive_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xStreamBufferReceive
 /*-----------------------------------------------------------*/
 
@@ -1008,12 +944,11 @@ MPU_xStreamBufferIsFull:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xStreamBufferIsFull_Unpriv
     MPU_xStreamBufferIsFull_Priv:
-        pop {r0, r1}
         b MPU_xStreamBufferIsFullImpl
     MPU_xStreamBufferIsFull_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xStreamBufferIsFull
 /*-----------------------------------------------------------*/
 
@@ -1023,12 +958,11 @@ MPU_xStreamBufferIsEmpty:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xStreamBufferIsEmpty_Unpriv
     MPU_xStreamBufferIsEmpty_Priv:
-        pop {r0, r1}
         b MPU_xStreamBufferIsEmptyImpl
     MPU_xStreamBufferIsEmpty_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xStreamBufferIsEmpty
 /*-----------------------------------------------------------*/
 
@@ -1038,12 +972,11 @@ MPU_xStreamBufferSpacesAvailable:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xStreamBufferSpacesAvailable_Unpriv
     MPU_xStreamBufferSpacesAvailable_Priv:
-        pop {r0, r1}
         b MPU_xStreamBufferSpacesAvailableImpl
     MPU_xStreamBufferSpacesAvailable_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xStreamBufferSpacesAvailable
 /*-----------------------------------------------------------*/
 
@@ -1053,12 +986,11 @@ MPU_xStreamBufferBytesAvailable:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xStreamBufferBytesAvailable_Unpriv
     MPU_xStreamBufferBytesAvailable_Priv:
-        pop {r0, r1}
         b MPU_xStreamBufferBytesAvailableImpl
     MPU_xStreamBufferBytesAvailable_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xStreamBufferBytesAvailable
 /*-----------------------------------------------------------*/
 
@@ -1068,12 +1000,11 @@ MPU_xStreamBufferSetTriggerLevel:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xStreamBufferSetTriggerLevel_Unpriv
     MPU_xStreamBufferSetTriggerLevel_Priv:
-        pop {r0, r1}
         b MPU_xStreamBufferSetTriggerLevelImpl
     MPU_xStreamBufferSetTriggerLevel_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel
 /*-----------------------------------------------------------*/
 
@@ -1083,12 +1014,11 @@ MPU_xStreamBufferNextMessageLengthBytes:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv
     MPU_xStreamBufferNextMessageLengthBytes_Priv:
-        pop {r0, r1}
         b MPU_xStreamBufferNextMessageLengthBytesImpl
     MPU_xStreamBufferNextMessageLengthBytes_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.S
index 8ea2f5c78..9289bcbc2 100644
--- a/portable/IAR/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.S
+++ b/portable/IAR/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.S
@@ -48,12 +48,11 @@ MPU_xTaskDelayUntil:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTaskDelayUntil_Unpriv
     MPU_xTaskDelayUntil_Priv:
-        pop {r0, r1}
         b MPU_xTaskDelayUntilImpl
     MPU_xTaskDelayUntil_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTaskDelayUntil
 /*-----------------------------------------------------------*/
 
@@ -63,12 +62,11 @@ MPU_xTaskAbortDelay:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTaskAbortDelay_Unpriv
     MPU_xTaskAbortDelay_Priv:
-        pop {r0, r1}
         b MPU_xTaskAbortDelayImpl
     MPU_xTaskAbortDelay_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTaskAbortDelay
 /*-----------------------------------------------------------*/
 
@@ -78,12 +76,11 @@ MPU_vTaskDelay:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_vTaskDelay_Unpriv
     MPU_vTaskDelay_Priv:
-        pop {r0, r1}
         b MPU_vTaskDelayImpl
     MPU_vTaskDelay_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_vTaskDelay
 /*-----------------------------------------------------------*/
 
@@ -93,12 +90,11 @@ MPU_uxTaskPriorityGet:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_uxTaskPriorityGet_Unpriv
     MPU_uxTaskPriorityGet_Priv:
-        pop {r0, r1}
         b MPU_uxTaskPriorityGetImpl
     MPU_uxTaskPriorityGet_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_uxTaskPriorityGet
 /*-----------------------------------------------------------*/
 
@@ -108,12 +104,11 @@ MPU_eTaskGetState:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_eTaskGetState_Unpriv
     MPU_eTaskGetState_Priv:
-        pop {r0, r1}
         b MPU_eTaskGetStateImpl
     MPU_eTaskGetState_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_eTaskGetState
 /*-----------------------------------------------------------*/
 
@@ -123,12 +118,11 @@ MPU_vTaskGetInfo:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_vTaskGetInfo_Unpriv
     MPU_vTaskGetInfo_Priv:
-        pop {r0, r1}
         b MPU_vTaskGetInfoImpl
     MPU_vTaskGetInfo_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_vTaskGetInfo
 /*-----------------------------------------------------------*/
 
@@ -138,12 +132,11 @@ MPU_xTaskGetIdleTaskHandle:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTaskGetIdleTaskHandle_Unpriv
     MPU_xTaskGetIdleTaskHandle_Priv:
-        pop {r0, r1}
         b MPU_xTaskGetIdleTaskHandleImpl
     MPU_xTaskGetIdleTaskHandle_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTaskGetIdleTaskHandle
 /*-----------------------------------------------------------*/
 
@@ -153,12 +146,11 @@ MPU_vTaskSuspend:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_vTaskSuspend_Unpriv
     MPU_vTaskSuspend_Priv:
-        pop {r0, r1}
         b MPU_vTaskSuspendImpl
     MPU_vTaskSuspend_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_vTaskSuspend
 /*-----------------------------------------------------------*/
 
@@ -168,12 +160,11 @@ MPU_vTaskResume:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_vTaskResume_Unpriv
     MPU_vTaskResume_Priv:
-        pop {r0, r1}
         b MPU_vTaskResumeImpl
     MPU_vTaskResume_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_vTaskResume
 /*-----------------------------------------------------------*/
 
@@ -183,12 +174,11 @@ MPU_xTaskGetTickCount:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTaskGetTickCount_Unpriv
     MPU_xTaskGetTickCount_Priv:
-        pop {r0, r1}
         b MPU_xTaskGetTickCountImpl
     MPU_xTaskGetTickCount_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTaskGetTickCount
 /*-----------------------------------------------------------*/
 
@@ -198,12 +188,11 @@ MPU_uxTaskGetNumberOfTasks:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_uxTaskGetNumberOfTasks_Unpriv
     MPU_uxTaskGetNumberOfTasks_Priv:
-        pop {r0, r1}
         b MPU_uxTaskGetNumberOfTasksImpl
     MPU_uxTaskGetNumberOfTasks_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_uxTaskGetNumberOfTasks
 /*-----------------------------------------------------------*/
 
@@ -213,12 +202,11 @@ MPU_ulTaskGetRunTimeCounter:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_ulTaskGetRunTimeCounter_Unpriv
     MPU_ulTaskGetRunTimeCounter_Priv:
-        pop {r0, r1}
         b MPU_ulTaskGetRunTimeCounterImpl
     MPU_ulTaskGetRunTimeCounter_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_ulTaskGetRunTimeCounter
 /*-----------------------------------------------------------*/
 
@@ -228,12 +216,11 @@ MPU_ulTaskGetRunTimePercent:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_ulTaskGetRunTimePercent_Unpriv
     MPU_ulTaskGetRunTimePercent_Priv:
-        pop {r0, r1}
         b MPU_ulTaskGetRunTimePercentImpl
     MPU_ulTaskGetRunTimePercent_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_ulTaskGetRunTimePercent
 /*-----------------------------------------------------------*/
 
@@ -243,12 +230,11 @@ MPU_ulTaskGetIdleRunTimePercent:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_ulTaskGetIdleRunTimePercent_Unpriv
     MPU_ulTaskGetIdleRunTimePercent_Priv:
-        pop {r0, r1}
         b MPU_ulTaskGetIdleRunTimePercentImpl
     MPU_ulTaskGetIdleRunTimePercent_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent
 /*-----------------------------------------------------------*/
 
@@ -258,12 +244,11 @@ MPU_ulTaskGetIdleRunTimeCounter:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv
     MPU_ulTaskGetIdleRunTimeCounter_Priv:
-        pop {r0, r1}
         b MPU_ulTaskGetIdleRunTimeCounterImpl
     MPU_ulTaskGetIdleRunTimeCounter_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter
 /*-----------------------------------------------------------*/
 
@@ -273,12 +258,11 @@ MPU_vTaskSetApplicationTaskTag:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_vTaskSetApplicationTaskTag_Unpriv
     MPU_vTaskSetApplicationTaskTag_Priv:
-        pop {r0, r1}
         b MPU_vTaskSetApplicationTaskTagImpl
     MPU_vTaskSetApplicationTaskTag_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_vTaskSetApplicationTaskTag
 /*-----------------------------------------------------------*/
 
@@ -288,12 +272,11 @@ MPU_xTaskGetApplicationTaskTag:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTaskGetApplicationTaskTag_Unpriv
     MPU_xTaskGetApplicationTaskTag_Priv:
-        pop {r0, r1}
         b MPU_xTaskGetApplicationTaskTagImpl
     MPU_xTaskGetApplicationTaskTag_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTaskGetApplicationTaskTag
 /*-----------------------------------------------------------*/
 
@@ -303,12 +286,11 @@ MPU_vTaskSetThreadLocalStoragePointer:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv
     MPU_vTaskSetThreadLocalStoragePointer_Priv:
-        pop {r0, r1}
         b MPU_vTaskSetThreadLocalStoragePointerImpl
     MPU_vTaskSetThreadLocalStoragePointer_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer
 /*-----------------------------------------------------------*/
 
@@ -318,12 +300,11 @@ MPU_pvTaskGetThreadLocalStoragePointer:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv
     MPU_pvTaskGetThreadLocalStoragePointer_Priv:
-        pop {r0, r1}
         b MPU_pvTaskGetThreadLocalStoragePointerImpl
     MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer
 /*-----------------------------------------------------------*/
 
@@ -333,12 +314,11 @@ MPU_uxTaskGetSystemState:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_uxTaskGetSystemState_Unpriv
     MPU_uxTaskGetSystemState_Priv:
-        pop {r0, r1}
         b MPU_uxTaskGetSystemStateImpl
     MPU_uxTaskGetSystemState_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_uxTaskGetSystemState
 /*-----------------------------------------------------------*/
 
@@ -348,12 +328,11 @@ MPU_uxTaskGetStackHighWaterMark:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_uxTaskGetStackHighWaterMark_Unpriv
     MPU_uxTaskGetStackHighWaterMark_Priv:
-        pop {r0, r1}
         b MPU_uxTaskGetStackHighWaterMarkImpl
     MPU_uxTaskGetStackHighWaterMark_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark
 /*-----------------------------------------------------------*/
 
@@ -363,12 +342,11 @@ MPU_uxTaskGetStackHighWaterMark2:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_uxTaskGetStackHighWaterMark2_Unpriv
     MPU_uxTaskGetStackHighWaterMark2_Priv:
-        pop {r0, r1}
         b MPU_uxTaskGetStackHighWaterMark2Impl
     MPU_uxTaskGetStackHighWaterMark2_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2
 /*-----------------------------------------------------------*/
 
@@ -378,12 +356,11 @@ MPU_xTaskGetCurrentTaskHandle:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTaskGetCurrentTaskHandle_Unpriv
     MPU_xTaskGetCurrentTaskHandle_Priv:
-        pop {r0, r1}
         b MPU_xTaskGetCurrentTaskHandleImpl
     MPU_xTaskGetCurrentTaskHandle_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle
 /*-----------------------------------------------------------*/
 
@@ -393,12 +370,11 @@ MPU_xTaskGetSchedulerState:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTaskGetSchedulerState_Unpriv
     MPU_xTaskGetSchedulerState_Priv:
-        pop {r0, r1}
         b MPU_xTaskGetSchedulerStateImpl
     MPU_xTaskGetSchedulerState_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTaskGetSchedulerState
 /*-----------------------------------------------------------*/
 
@@ -408,12 +384,11 @@ MPU_vTaskSetTimeOutState:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_vTaskSetTimeOutState_Unpriv
     MPU_vTaskSetTimeOutState_Priv:
-        pop {r0, r1}
         b MPU_vTaskSetTimeOutStateImpl
     MPU_vTaskSetTimeOutState_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_vTaskSetTimeOutState
 /*-----------------------------------------------------------*/
 
@@ -423,12 +398,11 @@ MPU_xTaskCheckForTimeOut:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTaskCheckForTimeOut_Unpriv
     MPU_xTaskCheckForTimeOut_Priv:
-        pop {r0, r1}
         b MPU_xTaskCheckForTimeOutImpl
     MPU_xTaskCheckForTimeOut_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTaskCheckForTimeOut
 /*-----------------------------------------------------------*/
 
@@ -438,12 +412,11 @@ MPU_xTaskGenericNotifyEntry:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTaskGenericNotify_Unpriv
     MPU_xTaskGenericNotify_Priv:
-        pop {r0, r1}
         b MPU_xTaskGenericNotifyImpl
     MPU_xTaskGenericNotify_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTaskGenericNotify
 /*-----------------------------------------------------------*/
 
@@ -453,12 +426,11 @@ MPU_xTaskGenericNotifyWaitEntry:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTaskGenericNotifyWait_Unpriv
     MPU_xTaskGenericNotifyWait_Priv:
-        pop {r0, r1}
         b MPU_xTaskGenericNotifyWaitImpl
     MPU_xTaskGenericNotifyWait_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTaskGenericNotifyWait
 /*-----------------------------------------------------------*/
 
@@ -468,12 +440,11 @@ MPU_ulTaskGenericNotifyTake:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_ulTaskGenericNotifyTake_Unpriv
     MPU_ulTaskGenericNotifyTake_Priv:
-        pop {r0, r1}
         b MPU_ulTaskGenericNotifyTakeImpl
     MPU_ulTaskGenericNotifyTake_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_ulTaskGenericNotifyTake
 /*-----------------------------------------------------------*/
 
@@ -483,12 +454,11 @@ MPU_xTaskGenericNotifyStateClear:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTaskGenericNotifyStateClear_Unpriv
     MPU_xTaskGenericNotifyStateClear_Priv:
-        pop {r0, r1}
         b MPU_xTaskGenericNotifyStateClearImpl
     MPU_xTaskGenericNotifyStateClear_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTaskGenericNotifyStateClear
 /*-----------------------------------------------------------*/
 
@@ -498,12 +468,11 @@ MPU_ulTaskGenericNotifyValueClear:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_ulTaskGenericNotifyValueClear_Unpriv
     MPU_ulTaskGenericNotifyValueClear_Priv:
-        pop {r0, r1}
         b MPU_ulTaskGenericNotifyValueClearImpl
     MPU_ulTaskGenericNotifyValueClear_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear
 /*-----------------------------------------------------------*/
 
@@ -513,12 +482,11 @@ MPU_xQueueGenericSend:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xQueueGenericSend_Unpriv
     MPU_xQueueGenericSend_Priv:
-        pop {r0, r1}
         b MPU_xQueueGenericSendImpl
     MPU_xQueueGenericSend_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xQueueGenericSend
 /*-----------------------------------------------------------*/
 
@@ -528,12 +496,11 @@ MPU_uxQueueMessagesWaiting:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_uxQueueMessagesWaiting_Unpriv
     MPU_uxQueueMessagesWaiting_Priv:
-        pop {r0, r1}
         b MPU_uxQueueMessagesWaitingImpl
     MPU_uxQueueMessagesWaiting_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_uxQueueMessagesWaiting
 /*-----------------------------------------------------------*/
 
@@ -543,12 +510,11 @@ MPU_uxQueueSpacesAvailable:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_uxQueueSpacesAvailable_Unpriv
     MPU_uxQueueSpacesAvailable_Priv:
-        pop {r0, r1}
         b MPU_uxQueueSpacesAvailableImpl
     MPU_uxQueueSpacesAvailable_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_uxQueueSpacesAvailable
 /*-----------------------------------------------------------*/
 
@@ -558,12 +524,11 @@ MPU_xQueueReceive:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xQueueReceive_Unpriv
     MPU_xQueueReceive_Priv:
-        pop {r0, r1}
         b MPU_xQueueReceiveImpl
     MPU_xQueueReceive_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xQueueReceive
 /*-----------------------------------------------------------*/
 
@@ -573,12 +538,11 @@ MPU_xQueuePeek:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xQueuePeek_Unpriv
     MPU_xQueuePeek_Priv:
-        pop {r0, r1}
         b MPU_xQueuePeekImpl
     MPU_xQueuePeek_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xQueuePeek
 /*-----------------------------------------------------------*/
 
@@ -588,12 +552,11 @@ MPU_xQueueSemaphoreTake:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xQueueSemaphoreTake_Unpriv
     MPU_xQueueSemaphoreTake_Priv:
-        pop {r0, r1}
         b MPU_xQueueSemaphoreTakeImpl
     MPU_xQueueSemaphoreTake_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xQueueSemaphoreTake
 /*-----------------------------------------------------------*/
 
@@ -603,12 +566,11 @@ MPU_xQueueGetMutexHolder:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xQueueGetMutexHolder_Unpriv
     MPU_xQueueGetMutexHolder_Priv:
-        pop {r0, r1}
         b MPU_xQueueGetMutexHolderImpl
     MPU_xQueueGetMutexHolder_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xQueueGetMutexHolder
 /*-----------------------------------------------------------*/
 
@@ -618,12 +580,11 @@ MPU_xQueueTakeMutexRecursive:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xQueueTakeMutexRecursive_Unpriv
     MPU_xQueueTakeMutexRecursive_Priv:
-        pop {r0, r1}
         b MPU_xQueueTakeMutexRecursiveImpl
     MPU_xQueueTakeMutexRecursive_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xQueueTakeMutexRecursive
 /*-----------------------------------------------------------*/
 
@@ -633,12 +594,11 @@ MPU_xQueueGiveMutexRecursive:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xQueueGiveMutexRecursive_Unpriv
     MPU_xQueueGiveMutexRecursive_Priv:
-        pop {r0, r1}
         b MPU_xQueueGiveMutexRecursiveImpl
     MPU_xQueueGiveMutexRecursive_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xQueueGiveMutexRecursive
 /*-----------------------------------------------------------*/
 
@@ -648,12 +608,11 @@ MPU_xQueueSelectFromSet:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xQueueSelectFromSet_Unpriv
     MPU_xQueueSelectFromSet_Priv:
-        pop {r0, r1}
         b MPU_xQueueSelectFromSetImpl
     MPU_xQueueSelectFromSet_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xQueueSelectFromSet
 /*-----------------------------------------------------------*/
 
@@ -663,12 +622,11 @@ MPU_xQueueAddToSet:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xQueueAddToSet_Unpriv
     MPU_xQueueAddToSet_Priv:
-        pop {r0, r1}
         b MPU_xQueueAddToSetImpl
     MPU_xQueueAddToSet_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xQueueAddToSet
 /*-----------------------------------------------------------*/
 
@@ -678,12 +636,11 @@ MPU_vQueueAddToRegistry:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_vQueueAddToRegistry_Unpriv
     MPU_vQueueAddToRegistry_Priv:
-        pop {r0, r1}
         b MPU_vQueueAddToRegistryImpl
     MPU_vQueueAddToRegistry_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_vQueueAddToRegistry
 /*-----------------------------------------------------------*/
 
@@ -693,12 +650,11 @@ MPU_vQueueUnregisterQueue:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_vQueueUnregisterQueue_Unpriv
     MPU_vQueueUnregisterQueue_Priv:
-        pop {r0, r1}
         b MPU_vQueueUnregisterQueueImpl
     MPU_vQueueUnregisterQueue_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_vQueueUnregisterQueue
 /*-----------------------------------------------------------*/
 
@@ -708,12 +664,11 @@ MPU_pcQueueGetName:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_pcQueueGetName_Unpriv
     MPU_pcQueueGetName_Priv:
-        pop {r0, r1}
         b MPU_pcQueueGetNameImpl
     MPU_pcQueueGetName_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_pcQueueGetName
 /*-----------------------------------------------------------*/
 
@@ -723,12 +678,11 @@ MPU_pvTimerGetTimerID:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_pvTimerGetTimerID_Unpriv
     MPU_pvTimerGetTimerID_Priv:
-        pop {r0, r1}
         b MPU_pvTimerGetTimerIDImpl
     MPU_pvTimerGetTimerID_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_pvTimerGetTimerID
 /*-----------------------------------------------------------*/
 
@@ -738,12 +692,11 @@ MPU_vTimerSetTimerID:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_vTimerSetTimerID_Unpriv
     MPU_vTimerSetTimerID_Priv:
-        pop {r0, r1}
         b MPU_vTimerSetTimerIDImpl
     MPU_vTimerSetTimerID_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_vTimerSetTimerID
 /*-----------------------------------------------------------*/
 
@@ -753,12 +706,11 @@ MPU_xTimerIsTimerActive:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTimerIsTimerActive_Unpriv
     MPU_xTimerIsTimerActive_Priv:
-        pop {r0, r1}
         b MPU_xTimerIsTimerActiveImpl
     MPU_xTimerIsTimerActive_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTimerIsTimerActive
 /*-----------------------------------------------------------*/
 
@@ -768,12 +720,11 @@ MPU_xTimerGetTimerDaemonTaskHandle:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv
     MPU_xTimerGetTimerDaemonTaskHandle_Priv:
-        pop {r0, r1}
         b MPU_xTimerGetTimerDaemonTaskHandleImpl
     MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle
 /*-----------------------------------------------------------*/
 
@@ -783,12 +734,11 @@ MPU_xTimerGenericCommandFromTaskEntry:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTimerGenericCommandFromTask_Unpriv
     MPU_xTimerGenericCommandFromTask_Priv:
-        pop {r0, r1}
         b MPU_xTimerGenericCommandFromTaskImpl
     MPU_xTimerGenericCommandFromTask_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTimerGenericCommandFromTask
 /*-----------------------------------------------------------*/
 
@@ -798,12 +748,11 @@ MPU_pcTimerGetName:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_pcTimerGetName_Unpriv
     MPU_pcTimerGetName_Priv:
-        pop {r0, r1}
         b MPU_pcTimerGetNameImpl
     MPU_pcTimerGetName_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_pcTimerGetName
 /*-----------------------------------------------------------*/
 
@@ -813,12 +762,11 @@ MPU_vTimerSetReloadMode:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_vTimerSetReloadMode_Unpriv
     MPU_vTimerSetReloadMode_Priv:
-        pop {r0, r1}
         b MPU_vTimerSetReloadModeImpl
     MPU_vTimerSetReloadMode_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_vTimerSetReloadMode
 /*-----------------------------------------------------------*/
 
@@ -828,12 +776,11 @@ MPU_xTimerGetReloadMode:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTimerGetReloadMode_Unpriv
     MPU_xTimerGetReloadMode_Priv:
-        pop {r0, r1}
         b MPU_xTimerGetReloadModeImpl
     MPU_xTimerGetReloadMode_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTimerGetReloadMode
 /*-----------------------------------------------------------*/
 
@@ -843,12 +790,11 @@ MPU_uxTimerGetReloadMode:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_uxTimerGetReloadMode_Unpriv
     MPU_uxTimerGetReloadMode_Priv:
-        pop {r0, r1}
         b MPU_uxTimerGetReloadModeImpl
     MPU_uxTimerGetReloadMode_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_uxTimerGetReloadMode
 /*-----------------------------------------------------------*/
 
@@ -858,12 +804,11 @@ MPU_xTimerGetPeriod:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTimerGetPeriod_Unpriv
     MPU_xTimerGetPeriod_Priv:
-        pop {r0, r1}
         b MPU_xTimerGetPeriodImpl
     MPU_xTimerGetPeriod_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTimerGetPeriod
 /*-----------------------------------------------------------*/
 
@@ -873,12 +818,11 @@ MPU_xTimerGetExpiryTime:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xTimerGetExpiryTime_Unpriv
     MPU_xTimerGetExpiryTime_Priv:
-        pop {r0, r1}
         b MPU_xTimerGetExpiryTimeImpl
     MPU_xTimerGetExpiryTime_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xTimerGetExpiryTime
 /*-----------------------------------------------------------*/
 
@@ -888,12 +832,11 @@ MPU_xEventGroupWaitBitsEntry:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xEventGroupWaitBits_Unpriv
     MPU_xEventGroupWaitBits_Priv:
-        pop {r0, r1}
         b MPU_xEventGroupWaitBitsImpl
     MPU_xEventGroupWaitBits_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xEventGroupWaitBits
 /*-----------------------------------------------------------*/
 
@@ -903,12 +846,11 @@ MPU_xEventGroupClearBits:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xEventGroupClearBits_Unpriv
     MPU_xEventGroupClearBits_Priv:
-        pop {r0, r1}
         b MPU_xEventGroupClearBitsImpl
     MPU_xEventGroupClearBits_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xEventGroupClearBits
 /*-----------------------------------------------------------*/
 
@@ -918,12 +860,11 @@ MPU_xEventGroupSetBits:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xEventGroupSetBits_Unpriv
     MPU_xEventGroupSetBits_Priv:
-        pop {r0, r1}
         b MPU_xEventGroupSetBitsImpl
     MPU_xEventGroupSetBits_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xEventGroupSetBits
 /*-----------------------------------------------------------*/
 
@@ -933,12 +874,11 @@ MPU_xEventGroupSync:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xEventGroupSync_Unpriv
     MPU_xEventGroupSync_Priv:
-        pop {r0, r1}
         b MPU_xEventGroupSyncImpl
     MPU_xEventGroupSync_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xEventGroupSync
 /*-----------------------------------------------------------*/
 
@@ -948,12 +888,11 @@ MPU_uxEventGroupGetNumber:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_uxEventGroupGetNumber_Unpriv
     MPU_uxEventGroupGetNumber_Priv:
-        pop {r0, r1}
         b MPU_uxEventGroupGetNumberImpl
     MPU_uxEventGroupGetNumber_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_uxEventGroupGetNumber
 /*-----------------------------------------------------------*/
 
@@ -963,12 +902,11 @@ MPU_vEventGroupSetNumber:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_vEventGroupSetNumber_Unpriv
     MPU_vEventGroupSetNumber_Priv:
-        pop {r0, r1}
         b MPU_vEventGroupSetNumberImpl
     MPU_vEventGroupSetNumber_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_vEventGroupSetNumber
 /*-----------------------------------------------------------*/
 
@@ -978,12 +916,11 @@ MPU_xStreamBufferSend:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xStreamBufferSend_Unpriv
     MPU_xStreamBufferSend_Priv:
-        pop {r0, r1}
         b MPU_xStreamBufferSendImpl
     MPU_xStreamBufferSend_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xStreamBufferSend
 /*-----------------------------------------------------------*/
 
@@ -993,12 +930,11 @@ MPU_xStreamBufferReceive:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xStreamBufferReceive_Unpriv
     MPU_xStreamBufferReceive_Priv:
-        pop {r0, r1}
         b MPU_xStreamBufferReceiveImpl
     MPU_xStreamBufferReceive_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xStreamBufferReceive
 /*-----------------------------------------------------------*/
 
@@ -1008,12 +944,11 @@ MPU_xStreamBufferIsFull:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xStreamBufferIsFull_Unpriv
     MPU_xStreamBufferIsFull_Priv:
-        pop {r0, r1}
         b MPU_xStreamBufferIsFullImpl
     MPU_xStreamBufferIsFull_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xStreamBufferIsFull
 /*-----------------------------------------------------------*/
 
@@ -1023,12 +958,11 @@ MPU_xStreamBufferIsEmpty:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xStreamBufferIsEmpty_Unpriv
     MPU_xStreamBufferIsEmpty_Priv:
-        pop {r0, r1}
         b MPU_xStreamBufferIsEmptyImpl
     MPU_xStreamBufferIsEmpty_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xStreamBufferIsEmpty
 /*-----------------------------------------------------------*/
 
@@ -1038,12 +972,11 @@ MPU_xStreamBufferSpacesAvailable:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xStreamBufferSpacesAvailable_Unpriv
     MPU_xStreamBufferSpacesAvailable_Priv:
-        pop {r0, r1}
         b MPU_xStreamBufferSpacesAvailableImpl
     MPU_xStreamBufferSpacesAvailable_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xStreamBufferSpacesAvailable
 /*-----------------------------------------------------------*/
 
@@ -1053,12 +986,11 @@ MPU_xStreamBufferBytesAvailable:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xStreamBufferBytesAvailable_Unpriv
     MPU_xStreamBufferBytesAvailable_Priv:
-        pop {r0, r1}
         b MPU_xStreamBufferBytesAvailableImpl
     MPU_xStreamBufferBytesAvailable_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xStreamBufferBytesAvailable
 /*-----------------------------------------------------------*/
 
@@ -1068,12 +1000,11 @@ MPU_xStreamBufferSetTriggerLevel:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xStreamBufferSetTriggerLevel_Unpriv
     MPU_xStreamBufferSetTriggerLevel_Priv:
-        pop {r0, r1}
         b MPU_xStreamBufferSetTriggerLevelImpl
     MPU_xStreamBufferSetTriggerLevel_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel
 /*-----------------------------------------------------------*/
 
@@ -1083,12 +1014,11 @@ MPU_xStreamBufferNextMessageLengthBytes:
     mrs r0, control
     movs r1, #1
     tst r0, r1
+    pop {r0, r1}
     bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv
     MPU_xStreamBufferNextMessageLengthBytes_Priv:
-        pop {r0, r1}
         b MPU_xStreamBufferNextMessageLengthBytesImpl
     MPU_xStreamBufferNextMessageLengthBytes_Unpriv:
-        pop {r0, r1}
         svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM33/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM33/non_secure/mpu_wrappers_v2_asm.S
index a69845eda..d2cb78e92 100644
--- a/portable/IAR/ARM_CM33/non_secure/mpu_wrappers_v2_asm.S
+++ b/portable/IAR/ARM_CM33/non_secure/mpu_wrappers_v2_asm.S
@@ -47,12 +47,11 @@ MPU_xTaskDelayUntil:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskDelayUntil_Unpriv
     MPU_xTaskDelayUntil_Priv:
-        pop {r0}
         b MPU_xTaskDelayUntilImpl
     MPU_xTaskDelayUntil_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskDelayUntil
 /*-----------------------------------------------------------*/
 
@@ -61,12 +60,11 @@ MPU_xTaskAbortDelay:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskAbortDelay_Unpriv
     MPU_xTaskAbortDelay_Priv:
-        pop {r0}
         b MPU_xTaskAbortDelayImpl
     MPU_xTaskAbortDelay_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskAbortDelay
 /*-----------------------------------------------------------*/
 
@@ -75,12 +73,11 @@ MPU_vTaskDelay:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskDelay_Unpriv
     MPU_vTaskDelay_Priv:
-        pop {r0}
         b MPU_vTaskDelayImpl
     MPU_vTaskDelay_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskDelay
 /*-----------------------------------------------------------*/
 
@@ -89,12 +86,11 @@ MPU_uxTaskPriorityGet:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTaskPriorityGet_Unpriv
     MPU_uxTaskPriorityGet_Priv:
-        pop {r0}
         b MPU_uxTaskPriorityGetImpl
     MPU_uxTaskPriorityGet_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTaskPriorityGet
 /*-----------------------------------------------------------*/
 
@@ -103,12 +99,11 @@ MPU_eTaskGetState:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_eTaskGetState_Unpriv
     MPU_eTaskGetState_Priv:
-        pop {r0}
         b MPU_eTaskGetStateImpl
     MPU_eTaskGetState_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_eTaskGetState
 /*-----------------------------------------------------------*/
 
@@ -117,12 +112,11 @@ MPU_vTaskGetInfo:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskGetInfo_Unpriv
     MPU_vTaskGetInfo_Priv:
-        pop {r0}
         b MPU_vTaskGetInfoImpl
     MPU_vTaskGetInfo_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskGetInfo
 /*-----------------------------------------------------------*/
 
@@ -131,12 +125,11 @@ MPU_xTaskGetIdleTaskHandle:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGetIdleTaskHandle_Unpriv
     MPU_xTaskGetIdleTaskHandle_Priv:
-        pop {r0}
         b MPU_xTaskGetIdleTaskHandleImpl
     MPU_xTaskGetIdleTaskHandle_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGetIdleTaskHandle
 /*-----------------------------------------------------------*/
 
@@ -145,12 +138,11 @@ MPU_vTaskSuspend:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskSuspend_Unpriv
     MPU_vTaskSuspend_Priv:
-        pop {r0}
         b MPU_vTaskSuspendImpl
     MPU_vTaskSuspend_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskSuspend
 /*-----------------------------------------------------------*/
 
@@ -159,12 +151,11 @@ MPU_vTaskResume:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskResume_Unpriv
     MPU_vTaskResume_Priv:
-        pop {r0}
         b MPU_vTaskResumeImpl
     MPU_vTaskResume_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskResume
 /*-----------------------------------------------------------*/
 
@@ -173,12 +164,11 @@ MPU_xTaskGetTickCount:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGetTickCount_Unpriv
     MPU_xTaskGetTickCount_Priv:
-        pop {r0}
         b MPU_xTaskGetTickCountImpl
     MPU_xTaskGetTickCount_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGetTickCount
 /*-----------------------------------------------------------*/
 
@@ -187,12 +177,11 @@ MPU_uxTaskGetNumberOfTasks:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTaskGetNumberOfTasks_Unpriv
     MPU_uxTaskGetNumberOfTasks_Priv:
-        pop {r0}
         b MPU_uxTaskGetNumberOfTasksImpl
     MPU_uxTaskGetNumberOfTasks_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTaskGetNumberOfTasks
 /*-----------------------------------------------------------*/
 
@@ -201,12 +190,11 @@ MPU_ulTaskGetRunTimeCounter:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGetRunTimeCounter_Unpriv
     MPU_ulTaskGetRunTimeCounter_Priv:
-        pop {r0}
         b MPU_ulTaskGetRunTimeCounterImpl
     MPU_ulTaskGetRunTimeCounter_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGetRunTimeCounter
 /*-----------------------------------------------------------*/
 
@@ -215,12 +203,11 @@ MPU_ulTaskGetRunTimePercent:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGetRunTimePercent_Unpriv
     MPU_ulTaskGetRunTimePercent_Priv:
-        pop {r0}
         b MPU_ulTaskGetRunTimePercentImpl
     MPU_ulTaskGetRunTimePercent_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGetRunTimePercent
 /*-----------------------------------------------------------*/
 
@@ -229,12 +216,11 @@ MPU_ulTaskGetIdleRunTimePercent:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGetIdleRunTimePercent_Unpriv
     MPU_ulTaskGetIdleRunTimePercent_Priv:
-        pop {r0}
         b MPU_ulTaskGetIdleRunTimePercentImpl
     MPU_ulTaskGetIdleRunTimePercent_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent
 /*-----------------------------------------------------------*/
 
@@ -243,12 +229,11 @@ MPU_ulTaskGetIdleRunTimeCounter:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv
     MPU_ulTaskGetIdleRunTimeCounter_Priv:
-        pop {r0}
         b MPU_ulTaskGetIdleRunTimeCounterImpl
     MPU_ulTaskGetIdleRunTimeCounter_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter
 /*-----------------------------------------------------------*/
 
@@ -257,12 +242,11 @@ MPU_vTaskSetApplicationTaskTag:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskSetApplicationTaskTag_Unpriv
     MPU_vTaskSetApplicationTaskTag_Priv:
-        pop {r0}
         b MPU_vTaskSetApplicationTaskTagImpl
     MPU_vTaskSetApplicationTaskTag_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskSetApplicationTaskTag
 /*-----------------------------------------------------------*/
 
@@ -271,12 +255,11 @@ MPU_xTaskGetApplicationTaskTag:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGetApplicationTaskTag_Unpriv
     MPU_xTaskGetApplicationTaskTag_Priv:
-        pop {r0}
         b MPU_xTaskGetApplicationTaskTagImpl
     MPU_xTaskGetApplicationTaskTag_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGetApplicationTaskTag
 /*-----------------------------------------------------------*/
 
@@ -285,12 +268,11 @@ MPU_vTaskSetThreadLocalStoragePointer:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv
     MPU_vTaskSetThreadLocalStoragePointer_Priv:
-        pop {r0}
         b MPU_vTaskSetThreadLocalStoragePointerImpl
     MPU_vTaskSetThreadLocalStoragePointer_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer
 /*-----------------------------------------------------------*/
 
@@ -299,12 +281,11 @@ MPU_pvTaskGetThreadLocalStoragePointer:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv
     MPU_pvTaskGetThreadLocalStoragePointer_Priv:
-        pop {r0}
         b MPU_pvTaskGetThreadLocalStoragePointerImpl
     MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer
 /*-----------------------------------------------------------*/
 
@@ -313,12 +294,11 @@ MPU_uxTaskGetSystemState:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTaskGetSystemState_Unpriv
     MPU_uxTaskGetSystemState_Priv:
-        pop {r0}
         b MPU_uxTaskGetSystemStateImpl
     MPU_uxTaskGetSystemState_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTaskGetSystemState
 /*-----------------------------------------------------------*/
 
@@ -327,12 +307,11 @@ MPU_uxTaskGetStackHighWaterMark:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTaskGetStackHighWaterMark_Unpriv
     MPU_uxTaskGetStackHighWaterMark_Priv:
-        pop {r0}
         b MPU_uxTaskGetStackHighWaterMarkImpl
     MPU_uxTaskGetStackHighWaterMark_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark
 /*-----------------------------------------------------------*/
 
@@ -341,12 +320,11 @@ MPU_uxTaskGetStackHighWaterMark2:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTaskGetStackHighWaterMark2_Unpriv
     MPU_uxTaskGetStackHighWaterMark2_Priv:
-        pop {r0}
         b MPU_uxTaskGetStackHighWaterMark2Impl
     MPU_uxTaskGetStackHighWaterMark2_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2
 /*-----------------------------------------------------------*/
 
@@ -355,12 +333,11 @@ MPU_xTaskGetCurrentTaskHandle:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGetCurrentTaskHandle_Unpriv
     MPU_xTaskGetCurrentTaskHandle_Priv:
-        pop {r0}
         b MPU_xTaskGetCurrentTaskHandleImpl
     MPU_xTaskGetCurrentTaskHandle_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle
 /*-----------------------------------------------------------*/
 
@@ -369,12 +346,11 @@ MPU_xTaskGetSchedulerState:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGetSchedulerState_Unpriv
     MPU_xTaskGetSchedulerState_Priv:
-        pop {r0}
         b MPU_xTaskGetSchedulerStateImpl
     MPU_xTaskGetSchedulerState_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGetSchedulerState
 /*-----------------------------------------------------------*/
 
@@ -383,12 +359,11 @@ MPU_vTaskSetTimeOutState:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskSetTimeOutState_Unpriv
     MPU_vTaskSetTimeOutState_Priv:
-        pop {r0}
         b MPU_vTaskSetTimeOutStateImpl
     MPU_vTaskSetTimeOutState_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskSetTimeOutState
 /*-----------------------------------------------------------*/
 
@@ -397,12 +372,11 @@ MPU_xTaskCheckForTimeOut:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskCheckForTimeOut_Unpriv
     MPU_xTaskCheckForTimeOut_Priv:
-        pop {r0}
         b MPU_xTaskCheckForTimeOutImpl
     MPU_xTaskCheckForTimeOut_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskCheckForTimeOut
 /*-----------------------------------------------------------*/
 
@@ -411,12 +385,11 @@ MPU_xTaskGenericNotifyEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGenericNotify_Unpriv
     MPU_xTaskGenericNotify_Priv:
-        pop {r0}
         b MPU_xTaskGenericNotifyImpl
     MPU_xTaskGenericNotify_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGenericNotify
 /*-----------------------------------------------------------*/
 
@@ -425,12 +398,11 @@ MPU_xTaskGenericNotifyWaitEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGenericNotifyWait_Unpriv
     MPU_xTaskGenericNotifyWait_Priv:
-        pop {r0}
         b MPU_xTaskGenericNotifyWaitImpl
     MPU_xTaskGenericNotifyWait_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGenericNotifyWait
 /*-----------------------------------------------------------*/
 
@@ -439,12 +411,11 @@ MPU_ulTaskGenericNotifyTake:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGenericNotifyTake_Unpriv
     MPU_ulTaskGenericNotifyTake_Priv:
-        pop {r0}
         b MPU_ulTaskGenericNotifyTakeImpl
     MPU_ulTaskGenericNotifyTake_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGenericNotifyTake
 /*-----------------------------------------------------------*/
 
@@ -453,12 +424,11 @@ MPU_xTaskGenericNotifyStateClear:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGenericNotifyStateClear_Unpriv
     MPU_xTaskGenericNotifyStateClear_Priv:
-        pop {r0}
         b MPU_xTaskGenericNotifyStateClearImpl
     MPU_xTaskGenericNotifyStateClear_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGenericNotifyStateClear
 /*-----------------------------------------------------------*/
 
@@ -467,12 +437,11 @@ MPU_ulTaskGenericNotifyValueClear:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGenericNotifyValueClear_Unpriv
     MPU_ulTaskGenericNotifyValueClear_Priv:
-        pop {r0}
         b MPU_ulTaskGenericNotifyValueClearImpl
     MPU_ulTaskGenericNotifyValueClear_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear
 /*-----------------------------------------------------------*/
 
@@ -481,12 +450,11 @@ MPU_xQueueGenericSend:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueGenericSend_Unpriv
     MPU_xQueueGenericSend_Priv:
-        pop {r0}
         b MPU_xQueueGenericSendImpl
     MPU_xQueueGenericSend_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueGenericSend
 /*-----------------------------------------------------------*/
 
@@ -495,12 +463,11 @@ MPU_uxQueueMessagesWaiting:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxQueueMessagesWaiting_Unpriv
     MPU_uxQueueMessagesWaiting_Priv:
-        pop {r0}
         b MPU_uxQueueMessagesWaitingImpl
     MPU_uxQueueMessagesWaiting_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxQueueMessagesWaiting
 /*-----------------------------------------------------------*/
 
@@ -509,12 +476,11 @@ MPU_uxQueueSpacesAvailable:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxQueueSpacesAvailable_Unpriv
     MPU_uxQueueSpacesAvailable_Priv:
-        pop {r0}
         b MPU_uxQueueSpacesAvailableImpl
     MPU_uxQueueSpacesAvailable_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxQueueSpacesAvailable
 /*-----------------------------------------------------------*/
 
@@ -523,12 +489,11 @@ MPU_xQueueReceive:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueReceive_Unpriv
     MPU_xQueueReceive_Priv:
-        pop {r0}
         b MPU_xQueueReceiveImpl
     MPU_xQueueReceive_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueReceive
 /*-----------------------------------------------------------*/
 
@@ -537,12 +502,11 @@ MPU_xQueuePeek:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueuePeek_Unpriv
     MPU_xQueuePeek_Priv:
-        pop {r0}
         b MPU_xQueuePeekImpl
     MPU_xQueuePeek_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueuePeek
 /*-----------------------------------------------------------*/
 
@@ -551,12 +515,11 @@ MPU_xQueueSemaphoreTake:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueSemaphoreTake_Unpriv
     MPU_xQueueSemaphoreTake_Priv:
-        pop {r0}
         b MPU_xQueueSemaphoreTakeImpl
     MPU_xQueueSemaphoreTake_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueSemaphoreTake
 /*-----------------------------------------------------------*/
 
@@ -565,12 +528,11 @@ MPU_xQueueGetMutexHolder:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueGetMutexHolder_Unpriv
     MPU_xQueueGetMutexHolder_Priv:
-        pop {r0}
         b MPU_xQueueGetMutexHolderImpl
     MPU_xQueueGetMutexHolder_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueGetMutexHolder
 /*-----------------------------------------------------------*/
 
@@ -579,12 +541,11 @@ MPU_xQueueTakeMutexRecursive:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueTakeMutexRecursive_Unpriv
     MPU_xQueueTakeMutexRecursive_Priv:
-        pop {r0}
         b MPU_xQueueTakeMutexRecursiveImpl
     MPU_xQueueTakeMutexRecursive_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueTakeMutexRecursive
 /*-----------------------------------------------------------*/
 
@@ -593,12 +554,11 @@ MPU_xQueueGiveMutexRecursive:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueGiveMutexRecursive_Unpriv
     MPU_xQueueGiveMutexRecursive_Priv:
-        pop {r0}
         b MPU_xQueueGiveMutexRecursiveImpl
     MPU_xQueueGiveMutexRecursive_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueGiveMutexRecursive
 /*-----------------------------------------------------------*/
 
@@ -607,12 +567,11 @@ MPU_xQueueSelectFromSet:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueSelectFromSet_Unpriv
     MPU_xQueueSelectFromSet_Priv:
-        pop {r0}
         b MPU_xQueueSelectFromSetImpl
     MPU_xQueueSelectFromSet_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueSelectFromSet
 /*-----------------------------------------------------------*/
 
@@ -621,12 +580,11 @@ MPU_xQueueAddToSet:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueAddToSet_Unpriv
     MPU_xQueueAddToSet_Priv:
-        pop {r0}
         b MPU_xQueueAddToSetImpl
     MPU_xQueueAddToSet_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueAddToSet
 /*-----------------------------------------------------------*/
 
@@ -635,12 +593,11 @@ MPU_vQueueAddToRegistry:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vQueueAddToRegistry_Unpriv
     MPU_vQueueAddToRegistry_Priv:
-        pop {r0}
         b MPU_vQueueAddToRegistryImpl
     MPU_vQueueAddToRegistry_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vQueueAddToRegistry
 /*-----------------------------------------------------------*/
 
@@ -649,12 +606,11 @@ MPU_vQueueUnregisterQueue:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vQueueUnregisterQueue_Unpriv
     MPU_vQueueUnregisterQueue_Priv:
-        pop {r0}
         b MPU_vQueueUnregisterQueueImpl
     MPU_vQueueUnregisterQueue_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vQueueUnregisterQueue
 /*-----------------------------------------------------------*/
 
@@ -663,12 +619,11 @@ MPU_pcQueueGetName:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_pcQueueGetName_Unpriv
     MPU_pcQueueGetName_Priv:
-        pop {r0}
         b MPU_pcQueueGetNameImpl
     MPU_pcQueueGetName_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_pcQueueGetName
 /*-----------------------------------------------------------*/
 
@@ -677,12 +632,11 @@ MPU_pvTimerGetTimerID:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_pvTimerGetTimerID_Unpriv
     MPU_pvTimerGetTimerID_Priv:
-        pop {r0}
         b MPU_pvTimerGetTimerIDImpl
     MPU_pvTimerGetTimerID_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_pvTimerGetTimerID
 /*-----------------------------------------------------------*/
 
@@ -691,12 +645,11 @@ MPU_vTimerSetTimerID:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTimerSetTimerID_Unpriv
     MPU_vTimerSetTimerID_Priv:
-        pop {r0}
         b MPU_vTimerSetTimerIDImpl
     MPU_vTimerSetTimerID_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTimerSetTimerID
 /*-----------------------------------------------------------*/
 
@@ -705,12 +658,11 @@ MPU_xTimerIsTimerActive:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerIsTimerActive_Unpriv
     MPU_xTimerIsTimerActive_Priv:
-        pop {r0}
         b MPU_xTimerIsTimerActiveImpl
     MPU_xTimerIsTimerActive_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerIsTimerActive
 /*-----------------------------------------------------------*/
 
@@ -719,12 +671,11 @@ MPU_xTimerGetTimerDaemonTaskHandle:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv
     MPU_xTimerGetTimerDaemonTaskHandle_Priv:
-        pop {r0}
         b MPU_xTimerGetTimerDaemonTaskHandleImpl
     MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle
 /*-----------------------------------------------------------*/
 
@@ -733,12 +684,11 @@ MPU_xTimerGenericCommandFromTaskEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerGenericCommandFromTask_Unpriv
     MPU_xTimerGenericCommandFromTask_Priv:
-        pop {r0}
         b MPU_xTimerGenericCommandFromTaskImpl
     MPU_xTimerGenericCommandFromTask_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerGenericCommandFromTask
 /*-----------------------------------------------------------*/
 
@@ -747,12 +697,11 @@ MPU_pcTimerGetName:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_pcTimerGetName_Unpriv
     MPU_pcTimerGetName_Priv:
-        pop {r0}
         b MPU_pcTimerGetNameImpl
     MPU_pcTimerGetName_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_pcTimerGetName
 /*-----------------------------------------------------------*/
 
@@ -761,12 +710,11 @@ MPU_vTimerSetReloadMode:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTimerSetReloadMode_Unpriv
     MPU_vTimerSetReloadMode_Priv:
-        pop {r0}
         b MPU_vTimerSetReloadModeImpl
     MPU_vTimerSetReloadMode_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTimerSetReloadMode
 /*-----------------------------------------------------------*/
 
@@ -775,12 +723,11 @@ MPU_xTimerGetReloadMode:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerGetReloadMode_Unpriv
     MPU_xTimerGetReloadMode_Priv:
-        pop {r0}
         b MPU_xTimerGetReloadModeImpl
     MPU_xTimerGetReloadMode_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerGetReloadMode
 /*-----------------------------------------------------------*/
 
@@ -789,12 +736,11 @@ MPU_uxTimerGetReloadMode:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTimerGetReloadMode_Unpriv
     MPU_uxTimerGetReloadMode_Priv:
-        pop {r0}
         b MPU_uxTimerGetReloadModeImpl
     MPU_uxTimerGetReloadMode_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTimerGetReloadMode
 /*-----------------------------------------------------------*/
 
@@ -803,12 +749,11 @@ MPU_xTimerGetPeriod:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerGetPeriod_Unpriv
     MPU_xTimerGetPeriod_Priv:
-        pop {r0}
         b MPU_xTimerGetPeriodImpl
     MPU_xTimerGetPeriod_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerGetPeriod
 /*-----------------------------------------------------------*/
 
@@ -817,12 +762,11 @@ MPU_xTimerGetExpiryTime:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerGetExpiryTime_Unpriv
     MPU_xTimerGetExpiryTime_Priv:
-        pop {r0}
         b MPU_xTimerGetExpiryTimeImpl
     MPU_xTimerGetExpiryTime_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerGetExpiryTime
 /*-----------------------------------------------------------*/
 
@@ -831,12 +775,11 @@ MPU_xEventGroupWaitBitsEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xEventGroupWaitBits_Unpriv
     MPU_xEventGroupWaitBits_Priv:
-        pop {r0}
         b MPU_xEventGroupWaitBitsImpl
     MPU_xEventGroupWaitBits_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xEventGroupWaitBits
 /*-----------------------------------------------------------*/
 
@@ -845,12 +788,11 @@ MPU_xEventGroupClearBits:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xEventGroupClearBits_Unpriv
     MPU_xEventGroupClearBits_Priv:
-        pop {r0}
         b MPU_xEventGroupClearBitsImpl
     MPU_xEventGroupClearBits_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xEventGroupClearBits
 /*-----------------------------------------------------------*/
 
@@ -859,12 +801,11 @@ MPU_xEventGroupSetBits:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xEventGroupSetBits_Unpriv
     MPU_xEventGroupSetBits_Priv:
-        pop {r0}
         b MPU_xEventGroupSetBitsImpl
     MPU_xEventGroupSetBits_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xEventGroupSetBits
 /*-----------------------------------------------------------*/
 
@@ -873,12 +814,11 @@ MPU_xEventGroupSync:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xEventGroupSync_Unpriv
     MPU_xEventGroupSync_Priv:
-        pop {r0}
         b MPU_xEventGroupSyncImpl
     MPU_xEventGroupSync_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xEventGroupSync
 /*-----------------------------------------------------------*/
 
@@ -887,12 +827,11 @@ MPU_uxEventGroupGetNumber:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxEventGroupGetNumber_Unpriv
     MPU_uxEventGroupGetNumber_Priv:
-        pop {r0}
         b MPU_uxEventGroupGetNumberImpl
     MPU_uxEventGroupGetNumber_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxEventGroupGetNumber
 /*-----------------------------------------------------------*/
 
@@ -901,12 +840,11 @@ MPU_vEventGroupSetNumber:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vEventGroupSetNumber_Unpriv
     MPU_vEventGroupSetNumber_Priv:
-        pop {r0}
         b MPU_vEventGroupSetNumberImpl
     MPU_vEventGroupSetNumber_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vEventGroupSetNumber
 /*-----------------------------------------------------------*/
 
@@ -915,12 +853,11 @@ MPU_xStreamBufferSend:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferSend_Unpriv
     MPU_xStreamBufferSend_Priv:
-        pop {r0}
         b MPU_xStreamBufferSendImpl
     MPU_xStreamBufferSend_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferSend
 /*-----------------------------------------------------------*/
 
@@ -929,12 +866,11 @@ MPU_xStreamBufferReceive:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferReceive_Unpriv
     MPU_xStreamBufferReceive_Priv:
-        pop {r0}
         b MPU_xStreamBufferReceiveImpl
     MPU_xStreamBufferReceive_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferReceive
 /*-----------------------------------------------------------*/
 
@@ -943,12 +879,11 @@ MPU_xStreamBufferIsFull:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferIsFull_Unpriv
     MPU_xStreamBufferIsFull_Priv:
-        pop {r0}
         b MPU_xStreamBufferIsFullImpl
     MPU_xStreamBufferIsFull_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferIsFull
 /*-----------------------------------------------------------*/
 
@@ -957,12 +892,11 @@ MPU_xStreamBufferIsEmpty:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferIsEmpty_Unpriv
     MPU_xStreamBufferIsEmpty_Priv:
-        pop {r0}
         b MPU_xStreamBufferIsEmptyImpl
     MPU_xStreamBufferIsEmpty_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferIsEmpty
 /*-----------------------------------------------------------*/
 
@@ -971,12 +905,11 @@ MPU_xStreamBufferSpacesAvailable:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferSpacesAvailable_Unpriv
     MPU_xStreamBufferSpacesAvailable_Priv:
-        pop {r0}
         b MPU_xStreamBufferSpacesAvailableImpl
     MPU_xStreamBufferSpacesAvailable_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferSpacesAvailable
 /*-----------------------------------------------------------*/
 
@@ -985,12 +918,11 @@ MPU_xStreamBufferBytesAvailable:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferBytesAvailable_Unpriv
     MPU_xStreamBufferBytesAvailable_Priv:
-        pop {r0}
         b MPU_xStreamBufferBytesAvailableImpl
     MPU_xStreamBufferBytesAvailable_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferBytesAvailable
 /*-----------------------------------------------------------*/
 
@@ -999,12 +931,11 @@ MPU_xStreamBufferSetTriggerLevel:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferSetTriggerLevel_Unpriv
     MPU_xStreamBufferSetTriggerLevel_Priv:
-        pop {r0}
         b MPU_xStreamBufferSetTriggerLevelImpl
     MPU_xStreamBufferSetTriggerLevel_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel
 /*-----------------------------------------------------------*/
 
@@ -1013,12 +944,11 @@ MPU_xStreamBufferNextMessageLengthBytes:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv
     MPU_xStreamBufferNextMessageLengthBytes_Priv:
-        pop {r0}
         b MPU_xStreamBufferNextMessageLengthBytesImpl
     MPU_xStreamBufferNextMessageLengthBytes_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.S
index a69845eda..d2cb78e92 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.S
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.S
@@ -47,12 +47,11 @@ MPU_xTaskDelayUntil:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskDelayUntil_Unpriv
     MPU_xTaskDelayUntil_Priv:
-        pop {r0}
         b MPU_xTaskDelayUntilImpl
     MPU_xTaskDelayUntil_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskDelayUntil
 /*-----------------------------------------------------------*/
 
@@ -61,12 +60,11 @@ MPU_xTaskAbortDelay:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskAbortDelay_Unpriv
     MPU_xTaskAbortDelay_Priv:
-        pop {r0}
         b MPU_xTaskAbortDelayImpl
     MPU_xTaskAbortDelay_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskAbortDelay
 /*-----------------------------------------------------------*/
 
@@ -75,12 +73,11 @@ MPU_vTaskDelay:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskDelay_Unpriv
     MPU_vTaskDelay_Priv:
-        pop {r0}
         b MPU_vTaskDelayImpl
     MPU_vTaskDelay_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskDelay
 /*-----------------------------------------------------------*/
 
@@ -89,12 +86,11 @@ MPU_uxTaskPriorityGet:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTaskPriorityGet_Unpriv
     MPU_uxTaskPriorityGet_Priv:
-        pop {r0}
         b MPU_uxTaskPriorityGetImpl
     MPU_uxTaskPriorityGet_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTaskPriorityGet
 /*-----------------------------------------------------------*/
 
@@ -103,12 +99,11 @@ MPU_eTaskGetState:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_eTaskGetState_Unpriv
     MPU_eTaskGetState_Priv:
-        pop {r0}
         b MPU_eTaskGetStateImpl
     MPU_eTaskGetState_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_eTaskGetState
 /*-----------------------------------------------------------*/
 
@@ -117,12 +112,11 @@ MPU_vTaskGetInfo:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskGetInfo_Unpriv
     MPU_vTaskGetInfo_Priv:
-        pop {r0}
         b MPU_vTaskGetInfoImpl
     MPU_vTaskGetInfo_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskGetInfo
 /*-----------------------------------------------------------*/
 
@@ -131,12 +125,11 @@ MPU_xTaskGetIdleTaskHandle:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGetIdleTaskHandle_Unpriv
     MPU_xTaskGetIdleTaskHandle_Priv:
-        pop {r0}
         b MPU_xTaskGetIdleTaskHandleImpl
     MPU_xTaskGetIdleTaskHandle_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGetIdleTaskHandle
 /*-----------------------------------------------------------*/
 
@@ -145,12 +138,11 @@ MPU_vTaskSuspend:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskSuspend_Unpriv
     MPU_vTaskSuspend_Priv:
-        pop {r0}
         b MPU_vTaskSuspendImpl
     MPU_vTaskSuspend_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskSuspend
 /*-----------------------------------------------------------*/
 
@@ -159,12 +151,11 @@ MPU_vTaskResume:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskResume_Unpriv
     MPU_vTaskResume_Priv:
-        pop {r0}
         b MPU_vTaskResumeImpl
     MPU_vTaskResume_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskResume
 /*-----------------------------------------------------------*/
 
@@ -173,12 +164,11 @@ MPU_xTaskGetTickCount:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGetTickCount_Unpriv
     MPU_xTaskGetTickCount_Priv:
-        pop {r0}
         b MPU_xTaskGetTickCountImpl
     MPU_xTaskGetTickCount_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGetTickCount
 /*-----------------------------------------------------------*/
 
@@ -187,12 +177,11 @@ MPU_uxTaskGetNumberOfTasks:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTaskGetNumberOfTasks_Unpriv
     MPU_uxTaskGetNumberOfTasks_Priv:
-        pop {r0}
         b MPU_uxTaskGetNumberOfTasksImpl
     MPU_uxTaskGetNumberOfTasks_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTaskGetNumberOfTasks
 /*-----------------------------------------------------------*/
 
@@ -201,12 +190,11 @@ MPU_ulTaskGetRunTimeCounter:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGetRunTimeCounter_Unpriv
     MPU_ulTaskGetRunTimeCounter_Priv:
-        pop {r0}
         b MPU_ulTaskGetRunTimeCounterImpl
     MPU_ulTaskGetRunTimeCounter_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGetRunTimeCounter
 /*-----------------------------------------------------------*/
 
@@ -215,12 +203,11 @@ MPU_ulTaskGetRunTimePercent:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGetRunTimePercent_Unpriv
     MPU_ulTaskGetRunTimePercent_Priv:
-        pop {r0}
         b MPU_ulTaskGetRunTimePercentImpl
     MPU_ulTaskGetRunTimePercent_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGetRunTimePercent
 /*-----------------------------------------------------------*/
 
@@ -229,12 +216,11 @@ MPU_ulTaskGetIdleRunTimePercent:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGetIdleRunTimePercent_Unpriv
     MPU_ulTaskGetIdleRunTimePercent_Priv:
-        pop {r0}
         b MPU_ulTaskGetIdleRunTimePercentImpl
     MPU_ulTaskGetIdleRunTimePercent_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent
 /*-----------------------------------------------------------*/
 
@@ -243,12 +229,11 @@ MPU_ulTaskGetIdleRunTimeCounter:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv
     MPU_ulTaskGetIdleRunTimeCounter_Priv:
-        pop {r0}
         b MPU_ulTaskGetIdleRunTimeCounterImpl
     MPU_ulTaskGetIdleRunTimeCounter_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter
 /*-----------------------------------------------------------*/
 
@@ -257,12 +242,11 @@ MPU_vTaskSetApplicationTaskTag:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskSetApplicationTaskTag_Unpriv
     MPU_vTaskSetApplicationTaskTag_Priv:
-        pop {r0}
         b MPU_vTaskSetApplicationTaskTagImpl
     MPU_vTaskSetApplicationTaskTag_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskSetApplicationTaskTag
 /*-----------------------------------------------------------*/
 
@@ -271,12 +255,11 @@ MPU_xTaskGetApplicationTaskTag:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGetApplicationTaskTag_Unpriv
     MPU_xTaskGetApplicationTaskTag_Priv:
-        pop {r0}
         b MPU_xTaskGetApplicationTaskTagImpl
     MPU_xTaskGetApplicationTaskTag_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGetApplicationTaskTag
 /*-----------------------------------------------------------*/
 
@@ -285,12 +268,11 @@ MPU_vTaskSetThreadLocalStoragePointer:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv
     MPU_vTaskSetThreadLocalStoragePointer_Priv:
-        pop {r0}
         b MPU_vTaskSetThreadLocalStoragePointerImpl
     MPU_vTaskSetThreadLocalStoragePointer_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer
 /*-----------------------------------------------------------*/
 
@@ -299,12 +281,11 @@ MPU_pvTaskGetThreadLocalStoragePointer:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv
     MPU_pvTaskGetThreadLocalStoragePointer_Priv:
-        pop {r0}
         b MPU_pvTaskGetThreadLocalStoragePointerImpl
     MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer
 /*-----------------------------------------------------------*/
 
@@ -313,12 +294,11 @@ MPU_uxTaskGetSystemState:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTaskGetSystemState_Unpriv
     MPU_uxTaskGetSystemState_Priv:
-        pop {r0}
         b MPU_uxTaskGetSystemStateImpl
     MPU_uxTaskGetSystemState_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTaskGetSystemState
 /*-----------------------------------------------------------*/
 
@@ -327,12 +307,11 @@ MPU_uxTaskGetStackHighWaterMark:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTaskGetStackHighWaterMark_Unpriv
     MPU_uxTaskGetStackHighWaterMark_Priv:
-        pop {r0}
         b MPU_uxTaskGetStackHighWaterMarkImpl
     MPU_uxTaskGetStackHighWaterMark_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark
 /*-----------------------------------------------------------*/
 
@@ -341,12 +320,11 @@ MPU_uxTaskGetStackHighWaterMark2:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTaskGetStackHighWaterMark2_Unpriv
     MPU_uxTaskGetStackHighWaterMark2_Priv:
-        pop {r0}
         b MPU_uxTaskGetStackHighWaterMark2Impl
     MPU_uxTaskGetStackHighWaterMark2_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2
 /*-----------------------------------------------------------*/
 
@@ -355,12 +333,11 @@ MPU_xTaskGetCurrentTaskHandle:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGetCurrentTaskHandle_Unpriv
     MPU_xTaskGetCurrentTaskHandle_Priv:
-        pop {r0}
         b MPU_xTaskGetCurrentTaskHandleImpl
     MPU_xTaskGetCurrentTaskHandle_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle
 /*-----------------------------------------------------------*/
 
@@ -369,12 +346,11 @@ MPU_xTaskGetSchedulerState:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGetSchedulerState_Unpriv
     MPU_xTaskGetSchedulerState_Priv:
-        pop {r0}
         b MPU_xTaskGetSchedulerStateImpl
     MPU_xTaskGetSchedulerState_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGetSchedulerState
 /*-----------------------------------------------------------*/
 
@@ -383,12 +359,11 @@ MPU_vTaskSetTimeOutState:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskSetTimeOutState_Unpriv
     MPU_vTaskSetTimeOutState_Priv:
-        pop {r0}
         b MPU_vTaskSetTimeOutStateImpl
     MPU_vTaskSetTimeOutState_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskSetTimeOutState
 /*-----------------------------------------------------------*/
 
@@ -397,12 +372,11 @@ MPU_xTaskCheckForTimeOut:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskCheckForTimeOut_Unpriv
     MPU_xTaskCheckForTimeOut_Priv:
-        pop {r0}
         b MPU_xTaskCheckForTimeOutImpl
     MPU_xTaskCheckForTimeOut_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskCheckForTimeOut
 /*-----------------------------------------------------------*/
 
@@ -411,12 +385,11 @@ MPU_xTaskGenericNotifyEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGenericNotify_Unpriv
     MPU_xTaskGenericNotify_Priv:
-        pop {r0}
         b MPU_xTaskGenericNotifyImpl
     MPU_xTaskGenericNotify_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGenericNotify
 /*-----------------------------------------------------------*/
 
@@ -425,12 +398,11 @@ MPU_xTaskGenericNotifyWaitEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGenericNotifyWait_Unpriv
     MPU_xTaskGenericNotifyWait_Priv:
-        pop {r0}
         b MPU_xTaskGenericNotifyWaitImpl
     MPU_xTaskGenericNotifyWait_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGenericNotifyWait
 /*-----------------------------------------------------------*/
 
@@ -439,12 +411,11 @@ MPU_ulTaskGenericNotifyTake:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGenericNotifyTake_Unpriv
     MPU_ulTaskGenericNotifyTake_Priv:
-        pop {r0}
         b MPU_ulTaskGenericNotifyTakeImpl
     MPU_ulTaskGenericNotifyTake_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGenericNotifyTake
 /*-----------------------------------------------------------*/
 
@@ -453,12 +424,11 @@ MPU_xTaskGenericNotifyStateClear:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGenericNotifyStateClear_Unpriv
     MPU_xTaskGenericNotifyStateClear_Priv:
-        pop {r0}
         b MPU_xTaskGenericNotifyStateClearImpl
     MPU_xTaskGenericNotifyStateClear_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGenericNotifyStateClear
 /*-----------------------------------------------------------*/
 
@@ -467,12 +437,11 @@ MPU_ulTaskGenericNotifyValueClear:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGenericNotifyValueClear_Unpriv
     MPU_ulTaskGenericNotifyValueClear_Priv:
-        pop {r0}
         b MPU_ulTaskGenericNotifyValueClearImpl
     MPU_ulTaskGenericNotifyValueClear_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear
 /*-----------------------------------------------------------*/
 
@@ -481,12 +450,11 @@ MPU_xQueueGenericSend:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueGenericSend_Unpriv
     MPU_xQueueGenericSend_Priv:
-        pop {r0}
         b MPU_xQueueGenericSendImpl
     MPU_xQueueGenericSend_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueGenericSend
 /*-----------------------------------------------------------*/
 
@@ -495,12 +463,11 @@ MPU_uxQueueMessagesWaiting:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxQueueMessagesWaiting_Unpriv
     MPU_uxQueueMessagesWaiting_Priv:
-        pop {r0}
         b MPU_uxQueueMessagesWaitingImpl
     MPU_uxQueueMessagesWaiting_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxQueueMessagesWaiting
 /*-----------------------------------------------------------*/
 
@@ -509,12 +476,11 @@ MPU_uxQueueSpacesAvailable:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxQueueSpacesAvailable_Unpriv
     MPU_uxQueueSpacesAvailable_Priv:
-        pop {r0}
         b MPU_uxQueueSpacesAvailableImpl
     MPU_uxQueueSpacesAvailable_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxQueueSpacesAvailable
 /*-----------------------------------------------------------*/
 
@@ -523,12 +489,11 @@ MPU_xQueueReceive:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueReceive_Unpriv
     MPU_xQueueReceive_Priv:
-        pop {r0}
         b MPU_xQueueReceiveImpl
     MPU_xQueueReceive_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueReceive
 /*-----------------------------------------------------------*/
 
@@ -537,12 +502,11 @@ MPU_xQueuePeek:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueuePeek_Unpriv
     MPU_xQueuePeek_Priv:
-        pop {r0}
         b MPU_xQueuePeekImpl
     MPU_xQueuePeek_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueuePeek
 /*-----------------------------------------------------------*/
 
@@ -551,12 +515,11 @@ MPU_xQueueSemaphoreTake:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueSemaphoreTake_Unpriv
     MPU_xQueueSemaphoreTake_Priv:
-        pop {r0}
         b MPU_xQueueSemaphoreTakeImpl
     MPU_xQueueSemaphoreTake_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueSemaphoreTake
 /*-----------------------------------------------------------*/
 
@@ -565,12 +528,11 @@ MPU_xQueueGetMutexHolder:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueGetMutexHolder_Unpriv
     MPU_xQueueGetMutexHolder_Priv:
-        pop {r0}
         b MPU_xQueueGetMutexHolderImpl
     MPU_xQueueGetMutexHolder_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueGetMutexHolder
 /*-----------------------------------------------------------*/
 
@@ -579,12 +541,11 @@ MPU_xQueueTakeMutexRecursive:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueTakeMutexRecursive_Unpriv
     MPU_xQueueTakeMutexRecursive_Priv:
-        pop {r0}
         b MPU_xQueueTakeMutexRecursiveImpl
     MPU_xQueueTakeMutexRecursive_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueTakeMutexRecursive
 /*-----------------------------------------------------------*/
 
@@ -593,12 +554,11 @@ MPU_xQueueGiveMutexRecursive:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueGiveMutexRecursive_Unpriv
     MPU_xQueueGiveMutexRecursive_Priv:
-        pop {r0}
         b MPU_xQueueGiveMutexRecursiveImpl
     MPU_xQueueGiveMutexRecursive_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueGiveMutexRecursive
 /*-----------------------------------------------------------*/
 
@@ -607,12 +567,11 @@ MPU_xQueueSelectFromSet:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueSelectFromSet_Unpriv
     MPU_xQueueSelectFromSet_Priv:
-        pop {r0}
         b MPU_xQueueSelectFromSetImpl
     MPU_xQueueSelectFromSet_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueSelectFromSet
 /*-----------------------------------------------------------*/
 
@@ -621,12 +580,11 @@ MPU_xQueueAddToSet:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueAddToSet_Unpriv
     MPU_xQueueAddToSet_Priv:
-        pop {r0}
         b MPU_xQueueAddToSetImpl
     MPU_xQueueAddToSet_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueAddToSet
 /*-----------------------------------------------------------*/
 
@@ -635,12 +593,11 @@ MPU_vQueueAddToRegistry:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vQueueAddToRegistry_Unpriv
     MPU_vQueueAddToRegistry_Priv:
-        pop {r0}
         b MPU_vQueueAddToRegistryImpl
     MPU_vQueueAddToRegistry_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vQueueAddToRegistry
 /*-----------------------------------------------------------*/
 
@@ -649,12 +606,11 @@ MPU_vQueueUnregisterQueue:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vQueueUnregisterQueue_Unpriv
     MPU_vQueueUnregisterQueue_Priv:
-        pop {r0}
         b MPU_vQueueUnregisterQueueImpl
     MPU_vQueueUnregisterQueue_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vQueueUnregisterQueue
 /*-----------------------------------------------------------*/
 
@@ -663,12 +619,11 @@ MPU_pcQueueGetName:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_pcQueueGetName_Unpriv
     MPU_pcQueueGetName_Priv:
-        pop {r0}
         b MPU_pcQueueGetNameImpl
     MPU_pcQueueGetName_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_pcQueueGetName
 /*-----------------------------------------------------------*/
 
@@ -677,12 +632,11 @@ MPU_pvTimerGetTimerID:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_pvTimerGetTimerID_Unpriv
     MPU_pvTimerGetTimerID_Priv:
-        pop {r0}
         b MPU_pvTimerGetTimerIDImpl
     MPU_pvTimerGetTimerID_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_pvTimerGetTimerID
 /*-----------------------------------------------------------*/
 
@@ -691,12 +645,11 @@ MPU_vTimerSetTimerID:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTimerSetTimerID_Unpriv
     MPU_vTimerSetTimerID_Priv:
-        pop {r0}
         b MPU_vTimerSetTimerIDImpl
     MPU_vTimerSetTimerID_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTimerSetTimerID
 /*-----------------------------------------------------------*/
 
@@ -705,12 +658,11 @@ MPU_xTimerIsTimerActive:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerIsTimerActive_Unpriv
     MPU_xTimerIsTimerActive_Priv:
-        pop {r0}
         b MPU_xTimerIsTimerActiveImpl
     MPU_xTimerIsTimerActive_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerIsTimerActive
 /*-----------------------------------------------------------*/
 
@@ -719,12 +671,11 @@ MPU_xTimerGetTimerDaemonTaskHandle:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv
     MPU_xTimerGetTimerDaemonTaskHandle_Priv:
-        pop {r0}
         b MPU_xTimerGetTimerDaemonTaskHandleImpl
     MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle
 /*-----------------------------------------------------------*/
 
@@ -733,12 +684,11 @@ MPU_xTimerGenericCommandFromTaskEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerGenericCommandFromTask_Unpriv
     MPU_xTimerGenericCommandFromTask_Priv:
-        pop {r0}
         b MPU_xTimerGenericCommandFromTaskImpl
     MPU_xTimerGenericCommandFromTask_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerGenericCommandFromTask
 /*-----------------------------------------------------------*/
 
@@ -747,12 +697,11 @@ MPU_pcTimerGetName:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_pcTimerGetName_Unpriv
     MPU_pcTimerGetName_Priv:
-        pop {r0}
         b MPU_pcTimerGetNameImpl
     MPU_pcTimerGetName_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_pcTimerGetName
 /*-----------------------------------------------------------*/
 
@@ -761,12 +710,11 @@ MPU_vTimerSetReloadMode:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTimerSetReloadMode_Unpriv
     MPU_vTimerSetReloadMode_Priv:
-        pop {r0}
         b MPU_vTimerSetReloadModeImpl
     MPU_vTimerSetReloadMode_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTimerSetReloadMode
 /*-----------------------------------------------------------*/
 
@@ -775,12 +723,11 @@ MPU_xTimerGetReloadMode:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerGetReloadMode_Unpriv
     MPU_xTimerGetReloadMode_Priv:
-        pop {r0}
         b MPU_xTimerGetReloadModeImpl
     MPU_xTimerGetReloadMode_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerGetReloadMode
 /*-----------------------------------------------------------*/
 
@@ -789,12 +736,11 @@ MPU_uxTimerGetReloadMode:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTimerGetReloadMode_Unpriv
     MPU_uxTimerGetReloadMode_Priv:
-        pop {r0}
         b MPU_uxTimerGetReloadModeImpl
     MPU_uxTimerGetReloadMode_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTimerGetReloadMode
 /*-----------------------------------------------------------*/
 
@@ -803,12 +749,11 @@ MPU_xTimerGetPeriod:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerGetPeriod_Unpriv
     MPU_xTimerGetPeriod_Priv:
-        pop {r0}
         b MPU_xTimerGetPeriodImpl
     MPU_xTimerGetPeriod_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerGetPeriod
 /*-----------------------------------------------------------*/
 
@@ -817,12 +762,11 @@ MPU_xTimerGetExpiryTime:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerGetExpiryTime_Unpriv
     MPU_xTimerGetExpiryTime_Priv:
-        pop {r0}
         b MPU_xTimerGetExpiryTimeImpl
     MPU_xTimerGetExpiryTime_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerGetExpiryTime
 /*-----------------------------------------------------------*/
 
@@ -831,12 +775,11 @@ MPU_xEventGroupWaitBitsEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xEventGroupWaitBits_Unpriv
     MPU_xEventGroupWaitBits_Priv:
-        pop {r0}
         b MPU_xEventGroupWaitBitsImpl
     MPU_xEventGroupWaitBits_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xEventGroupWaitBits
 /*-----------------------------------------------------------*/
 
@@ -845,12 +788,11 @@ MPU_xEventGroupClearBits:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xEventGroupClearBits_Unpriv
     MPU_xEventGroupClearBits_Priv:
-        pop {r0}
         b MPU_xEventGroupClearBitsImpl
     MPU_xEventGroupClearBits_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xEventGroupClearBits
 /*-----------------------------------------------------------*/
 
@@ -859,12 +801,11 @@ MPU_xEventGroupSetBits:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xEventGroupSetBits_Unpriv
     MPU_xEventGroupSetBits_Priv:
-        pop {r0}
         b MPU_xEventGroupSetBitsImpl
     MPU_xEventGroupSetBits_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xEventGroupSetBits
 /*-----------------------------------------------------------*/
 
@@ -873,12 +814,11 @@ MPU_xEventGroupSync:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xEventGroupSync_Unpriv
     MPU_xEventGroupSync_Priv:
-        pop {r0}
         b MPU_xEventGroupSyncImpl
     MPU_xEventGroupSync_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xEventGroupSync
 /*-----------------------------------------------------------*/
 
@@ -887,12 +827,11 @@ MPU_uxEventGroupGetNumber:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxEventGroupGetNumber_Unpriv
     MPU_uxEventGroupGetNumber_Priv:
-        pop {r0}
         b MPU_uxEventGroupGetNumberImpl
     MPU_uxEventGroupGetNumber_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxEventGroupGetNumber
 /*-----------------------------------------------------------*/
 
@@ -901,12 +840,11 @@ MPU_vEventGroupSetNumber:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vEventGroupSetNumber_Unpriv
     MPU_vEventGroupSetNumber_Priv:
-        pop {r0}
         b MPU_vEventGroupSetNumberImpl
     MPU_vEventGroupSetNumber_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vEventGroupSetNumber
 /*-----------------------------------------------------------*/
 
@@ -915,12 +853,11 @@ MPU_xStreamBufferSend:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferSend_Unpriv
     MPU_xStreamBufferSend_Priv:
-        pop {r0}
         b MPU_xStreamBufferSendImpl
     MPU_xStreamBufferSend_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferSend
 /*-----------------------------------------------------------*/
 
@@ -929,12 +866,11 @@ MPU_xStreamBufferReceive:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferReceive_Unpriv
     MPU_xStreamBufferReceive_Priv:
-        pop {r0}
         b MPU_xStreamBufferReceiveImpl
     MPU_xStreamBufferReceive_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferReceive
 /*-----------------------------------------------------------*/
 
@@ -943,12 +879,11 @@ MPU_xStreamBufferIsFull:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferIsFull_Unpriv
     MPU_xStreamBufferIsFull_Priv:
-        pop {r0}
         b MPU_xStreamBufferIsFullImpl
     MPU_xStreamBufferIsFull_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferIsFull
 /*-----------------------------------------------------------*/
 
@@ -957,12 +892,11 @@ MPU_xStreamBufferIsEmpty:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferIsEmpty_Unpriv
     MPU_xStreamBufferIsEmpty_Priv:
-        pop {r0}
         b MPU_xStreamBufferIsEmptyImpl
     MPU_xStreamBufferIsEmpty_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferIsEmpty
 /*-----------------------------------------------------------*/
 
@@ -971,12 +905,11 @@ MPU_xStreamBufferSpacesAvailable:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferSpacesAvailable_Unpriv
     MPU_xStreamBufferSpacesAvailable_Priv:
-        pop {r0}
         b MPU_xStreamBufferSpacesAvailableImpl
     MPU_xStreamBufferSpacesAvailable_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferSpacesAvailable
 /*-----------------------------------------------------------*/
 
@@ -985,12 +918,11 @@ MPU_xStreamBufferBytesAvailable:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferBytesAvailable_Unpriv
     MPU_xStreamBufferBytesAvailable_Priv:
-        pop {r0}
         b MPU_xStreamBufferBytesAvailableImpl
     MPU_xStreamBufferBytesAvailable_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferBytesAvailable
 /*-----------------------------------------------------------*/
 
@@ -999,12 +931,11 @@ MPU_xStreamBufferSetTriggerLevel:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferSetTriggerLevel_Unpriv
     MPU_xStreamBufferSetTriggerLevel_Priv:
-        pop {r0}
         b MPU_xStreamBufferSetTriggerLevelImpl
     MPU_xStreamBufferSetTriggerLevel_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel
 /*-----------------------------------------------------------*/
 
@@ -1013,12 +944,11 @@ MPU_xStreamBufferNextMessageLengthBytes:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv
     MPU_xStreamBufferNextMessageLengthBytes_Priv:
-        pop {r0}
         b MPU_xStreamBufferNextMessageLengthBytesImpl
     MPU_xStreamBufferNextMessageLengthBytes_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.S
index a69845eda..d2cb78e92 100644
--- a/portable/IAR/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.S
+++ b/portable/IAR/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.S
@@ -47,12 +47,11 @@ MPU_xTaskDelayUntil:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskDelayUntil_Unpriv
     MPU_xTaskDelayUntil_Priv:
-        pop {r0}
         b MPU_xTaskDelayUntilImpl
     MPU_xTaskDelayUntil_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskDelayUntil
 /*-----------------------------------------------------------*/
 
@@ -61,12 +60,11 @@ MPU_xTaskAbortDelay:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskAbortDelay_Unpriv
     MPU_xTaskAbortDelay_Priv:
-        pop {r0}
         b MPU_xTaskAbortDelayImpl
     MPU_xTaskAbortDelay_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskAbortDelay
 /*-----------------------------------------------------------*/
 
@@ -75,12 +73,11 @@ MPU_vTaskDelay:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskDelay_Unpriv
     MPU_vTaskDelay_Priv:
-        pop {r0}
         b MPU_vTaskDelayImpl
     MPU_vTaskDelay_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskDelay
 /*-----------------------------------------------------------*/
 
@@ -89,12 +86,11 @@ MPU_uxTaskPriorityGet:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTaskPriorityGet_Unpriv
     MPU_uxTaskPriorityGet_Priv:
-        pop {r0}
         b MPU_uxTaskPriorityGetImpl
     MPU_uxTaskPriorityGet_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTaskPriorityGet
 /*-----------------------------------------------------------*/
 
@@ -103,12 +99,11 @@ MPU_eTaskGetState:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_eTaskGetState_Unpriv
     MPU_eTaskGetState_Priv:
-        pop {r0}
         b MPU_eTaskGetStateImpl
     MPU_eTaskGetState_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_eTaskGetState
 /*-----------------------------------------------------------*/
 
@@ -117,12 +112,11 @@ MPU_vTaskGetInfo:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskGetInfo_Unpriv
     MPU_vTaskGetInfo_Priv:
-        pop {r0}
         b MPU_vTaskGetInfoImpl
     MPU_vTaskGetInfo_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskGetInfo
 /*-----------------------------------------------------------*/
 
@@ -131,12 +125,11 @@ MPU_xTaskGetIdleTaskHandle:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGetIdleTaskHandle_Unpriv
     MPU_xTaskGetIdleTaskHandle_Priv:
-        pop {r0}
         b MPU_xTaskGetIdleTaskHandleImpl
     MPU_xTaskGetIdleTaskHandle_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGetIdleTaskHandle
 /*-----------------------------------------------------------*/
 
@@ -145,12 +138,11 @@ MPU_vTaskSuspend:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskSuspend_Unpriv
     MPU_vTaskSuspend_Priv:
-        pop {r0}
         b MPU_vTaskSuspendImpl
     MPU_vTaskSuspend_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskSuspend
 /*-----------------------------------------------------------*/
 
@@ -159,12 +151,11 @@ MPU_vTaskResume:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskResume_Unpriv
     MPU_vTaskResume_Priv:
-        pop {r0}
         b MPU_vTaskResumeImpl
     MPU_vTaskResume_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskResume
 /*-----------------------------------------------------------*/
 
@@ -173,12 +164,11 @@ MPU_xTaskGetTickCount:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGetTickCount_Unpriv
     MPU_xTaskGetTickCount_Priv:
-        pop {r0}
         b MPU_xTaskGetTickCountImpl
     MPU_xTaskGetTickCount_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGetTickCount
 /*-----------------------------------------------------------*/
 
@@ -187,12 +177,11 @@ MPU_uxTaskGetNumberOfTasks:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTaskGetNumberOfTasks_Unpriv
     MPU_uxTaskGetNumberOfTasks_Priv:
-        pop {r0}
         b MPU_uxTaskGetNumberOfTasksImpl
     MPU_uxTaskGetNumberOfTasks_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTaskGetNumberOfTasks
 /*-----------------------------------------------------------*/
 
@@ -201,12 +190,11 @@ MPU_ulTaskGetRunTimeCounter:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGetRunTimeCounter_Unpriv
     MPU_ulTaskGetRunTimeCounter_Priv:
-        pop {r0}
         b MPU_ulTaskGetRunTimeCounterImpl
     MPU_ulTaskGetRunTimeCounter_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGetRunTimeCounter
 /*-----------------------------------------------------------*/
 
@@ -215,12 +203,11 @@ MPU_ulTaskGetRunTimePercent:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGetRunTimePercent_Unpriv
     MPU_ulTaskGetRunTimePercent_Priv:
-        pop {r0}
         b MPU_ulTaskGetRunTimePercentImpl
     MPU_ulTaskGetRunTimePercent_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGetRunTimePercent
 /*-----------------------------------------------------------*/
 
@@ -229,12 +216,11 @@ MPU_ulTaskGetIdleRunTimePercent:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGetIdleRunTimePercent_Unpriv
     MPU_ulTaskGetIdleRunTimePercent_Priv:
-        pop {r0}
         b MPU_ulTaskGetIdleRunTimePercentImpl
     MPU_ulTaskGetIdleRunTimePercent_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent
 /*-----------------------------------------------------------*/
 
@@ -243,12 +229,11 @@ MPU_ulTaskGetIdleRunTimeCounter:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv
     MPU_ulTaskGetIdleRunTimeCounter_Priv:
-        pop {r0}
         b MPU_ulTaskGetIdleRunTimeCounterImpl
     MPU_ulTaskGetIdleRunTimeCounter_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter
 /*-----------------------------------------------------------*/
 
@@ -257,12 +242,11 @@ MPU_vTaskSetApplicationTaskTag:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskSetApplicationTaskTag_Unpriv
     MPU_vTaskSetApplicationTaskTag_Priv:
-        pop {r0}
         b MPU_vTaskSetApplicationTaskTagImpl
     MPU_vTaskSetApplicationTaskTag_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskSetApplicationTaskTag
 /*-----------------------------------------------------------*/
 
@@ -271,12 +255,11 @@ MPU_xTaskGetApplicationTaskTag:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGetApplicationTaskTag_Unpriv
     MPU_xTaskGetApplicationTaskTag_Priv:
-        pop {r0}
         b MPU_xTaskGetApplicationTaskTagImpl
     MPU_xTaskGetApplicationTaskTag_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGetApplicationTaskTag
 /*-----------------------------------------------------------*/
 
@@ -285,12 +268,11 @@ MPU_vTaskSetThreadLocalStoragePointer:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv
     MPU_vTaskSetThreadLocalStoragePointer_Priv:
-        pop {r0}
         b MPU_vTaskSetThreadLocalStoragePointerImpl
     MPU_vTaskSetThreadLocalStoragePointer_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer
 /*-----------------------------------------------------------*/
 
@@ -299,12 +281,11 @@ MPU_pvTaskGetThreadLocalStoragePointer:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv
     MPU_pvTaskGetThreadLocalStoragePointer_Priv:
-        pop {r0}
         b MPU_pvTaskGetThreadLocalStoragePointerImpl
     MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer
 /*-----------------------------------------------------------*/
 
@@ -313,12 +294,11 @@ MPU_uxTaskGetSystemState:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTaskGetSystemState_Unpriv
     MPU_uxTaskGetSystemState_Priv:
-        pop {r0}
         b MPU_uxTaskGetSystemStateImpl
     MPU_uxTaskGetSystemState_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTaskGetSystemState
 /*-----------------------------------------------------------*/
 
@@ -327,12 +307,11 @@ MPU_uxTaskGetStackHighWaterMark:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTaskGetStackHighWaterMark_Unpriv
     MPU_uxTaskGetStackHighWaterMark_Priv:
-        pop {r0}
         b MPU_uxTaskGetStackHighWaterMarkImpl
     MPU_uxTaskGetStackHighWaterMark_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark
 /*-----------------------------------------------------------*/
 
@@ -341,12 +320,11 @@ MPU_uxTaskGetStackHighWaterMark2:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTaskGetStackHighWaterMark2_Unpriv
     MPU_uxTaskGetStackHighWaterMark2_Priv:
-        pop {r0}
         b MPU_uxTaskGetStackHighWaterMark2Impl
     MPU_uxTaskGetStackHighWaterMark2_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2
 /*-----------------------------------------------------------*/
 
@@ -355,12 +333,11 @@ MPU_xTaskGetCurrentTaskHandle:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGetCurrentTaskHandle_Unpriv
     MPU_xTaskGetCurrentTaskHandle_Priv:
-        pop {r0}
         b MPU_xTaskGetCurrentTaskHandleImpl
     MPU_xTaskGetCurrentTaskHandle_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle
 /*-----------------------------------------------------------*/
 
@@ -369,12 +346,11 @@ MPU_xTaskGetSchedulerState:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGetSchedulerState_Unpriv
     MPU_xTaskGetSchedulerState_Priv:
-        pop {r0}
         b MPU_xTaskGetSchedulerStateImpl
     MPU_xTaskGetSchedulerState_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGetSchedulerState
 /*-----------------------------------------------------------*/
 
@@ -383,12 +359,11 @@ MPU_vTaskSetTimeOutState:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskSetTimeOutState_Unpriv
     MPU_vTaskSetTimeOutState_Priv:
-        pop {r0}
         b MPU_vTaskSetTimeOutStateImpl
     MPU_vTaskSetTimeOutState_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskSetTimeOutState
 /*-----------------------------------------------------------*/
 
@@ -397,12 +372,11 @@ MPU_xTaskCheckForTimeOut:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskCheckForTimeOut_Unpriv
     MPU_xTaskCheckForTimeOut_Priv:
-        pop {r0}
         b MPU_xTaskCheckForTimeOutImpl
     MPU_xTaskCheckForTimeOut_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskCheckForTimeOut
 /*-----------------------------------------------------------*/
 
@@ -411,12 +385,11 @@ MPU_xTaskGenericNotifyEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGenericNotify_Unpriv
     MPU_xTaskGenericNotify_Priv:
-        pop {r0}
         b MPU_xTaskGenericNotifyImpl
     MPU_xTaskGenericNotify_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGenericNotify
 /*-----------------------------------------------------------*/
 
@@ -425,12 +398,11 @@ MPU_xTaskGenericNotifyWaitEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGenericNotifyWait_Unpriv
     MPU_xTaskGenericNotifyWait_Priv:
-        pop {r0}
         b MPU_xTaskGenericNotifyWaitImpl
     MPU_xTaskGenericNotifyWait_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGenericNotifyWait
 /*-----------------------------------------------------------*/
 
@@ -439,12 +411,11 @@ MPU_ulTaskGenericNotifyTake:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGenericNotifyTake_Unpriv
     MPU_ulTaskGenericNotifyTake_Priv:
-        pop {r0}
         b MPU_ulTaskGenericNotifyTakeImpl
     MPU_ulTaskGenericNotifyTake_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGenericNotifyTake
 /*-----------------------------------------------------------*/
 
@@ -453,12 +424,11 @@ MPU_xTaskGenericNotifyStateClear:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGenericNotifyStateClear_Unpriv
     MPU_xTaskGenericNotifyStateClear_Priv:
-        pop {r0}
         b MPU_xTaskGenericNotifyStateClearImpl
     MPU_xTaskGenericNotifyStateClear_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGenericNotifyStateClear
 /*-----------------------------------------------------------*/
 
@@ -467,12 +437,11 @@ MPU_ulTaskGenericNotifyValueClear:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGenericNotifyValueClear_Unpriv
     MPU_ulTaskGenericNotifyValueClear_Priv:
-        pop {r0}
         b MPU_ulTaskGenericNotifyValueClearImpl
     MPU_ulTaskGenericNotifyValueClear_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear
 /*-----------------------------------------------------------*/
 
@@ -481,12 +450,11 @@ MPU_xQueueGenericSend:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueGenericSend_Unpriv
     MPU_xQueueGenericSend_Priv:
-        pop {r0}
         b MPU_xQueueGenericSendImpl
     MPU_xQueueGenericSend_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueGenericSend
 /*-----------------------------------------------------------*/
 
@@ -495,12 +463,11 @@ MPU_uxQueueMessagesWaiting:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxQueueMessagesWaiting_Unpriv
     MPU_uxQueueMessagesWaiting_Priv:
-        pop {r0}
         b MPU_uxQueueMessagesWaitingImpl
     MPU_uxQueueMessagesWaiting_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxQueueMessagesWaiting
 /*-----------------------------------------------------------*/
 
@@ -509,12 +476,11 @@ MPU_uxQueueSpacesAvailable:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxQueueSpacesAvailable_Unpriv
     MPU_uxQueueSpacesAvailable_Priv:
-        pop {r0}
         b MPU_uxQueueSpacesAvailableImpl
     MPU_uxQueueSpacesAvailable_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxQueueSpacesAvailable
 /*-----------------------------------------------------------*/
 
@@ -523,12 +489,11 @@ MPU_xQueueReceive:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueReceive_Unpriv
     MPU_xQueueReceive_Priv:
-        pop {r0}
         b MPU_xQueueReceiveImpl
     MPU_xQueueReceive_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueReceive
 /*-----------------------------------------------------------*/
 
@@ -537,12 +502,11 @@ MPU_xQueuePeek:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueuePeek_Unpriv
     MPU_xQueuePeek_Priv:
-        pop {r0}
         b MPU_xQueuePeekImpl
     MPU_xQueuePeek_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueuePeek
 /*-----------------------------------------------------------*/
 
@@ -551,12 +515,11 @@ MPU_xQueueSemaphoreTake:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueSemaphoreTake_Unpriv
     MPU_xQueueSemaphoreTake_Priv:
-        pop {r0}
         b MPU_xQueueSemaphoreTakeImpl
     MPU_xQueueSemaphoreTake_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueSemaphoreTake
 /*-----------------------------------------------------------*/
 
@@ -565,12 +528,11 @@ MPU_xQueueGetMutexHolder:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueGetMutexHolder_Unpriv
     MPU_xQueueGetMutexHolder_Priv:
-        pop {r0}
         b MPU_xQueueGetMutexHolderImpl
     MPU_xQueueGetMutexHolder_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueGetMutexHolder
 /*-----------------------------------------------------------*/
 
@@ -579,12 +541,11 @@ MPU_xQueueTakeMutexRecursive:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueTakeMutexRecursive_Unpriv
     MPU_xQueueTakeMutexRecursive_Priv:
-        pop {r0}
         b MPU_xQueueTakeMutexRecursiveImpl
     MPU_xQueueTakeMutexRecursive_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueTakeMutexRecursive
 /*-----------------------------------------------------------*/
 
@@ -593,12 +554,11 @@ MPU_xQueueGiveMutexRecursive:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueGiveMutexRecursive_Unpriv
     MPU_xQueueGiveMutexRecursive_Priv:
-        pop {r0}
         b MPU_xQueueGiveMutexRecursiveImpl
     MPU_xQueueGiveMutexRecursive_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueGiveMutexRecursive
 /*-----------------------------------------------------------*/
 
@@ -607,12 +567,11 @@ MPU_xQueueSelectFromSet:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueSelectFromSet_Unpriv
     MPU_xQueueSelectFromSet_Priv:
-        pop {r0}
         b MPU_xQueueSelectFromSetImpl
     MPU_xQueueSelectFromSet_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueSelectFromSet
 /*-----------------------------------------------------------*/
 
@@ -621,12 +580,11 @@ MPU_xQueueAddToSet:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueAddToSet_Unpriv
     MPU_xQueueAddToSet_Priv:
-        pop {r0}
         b MPU_xQueueAddToSetImpl
     MPU_xQueueAddToSet_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueAddToSet
 /*-----------------------------------------------------------*/
 
@@ -635,12 +593,11 @@ MPU_vQueueAddToRegistry:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vQueueAddToRegistry_Unpriv
     MPU_vQueueAddToRegistry_Priv:
-        pop {r0}
         b MPU_vQueueAddToRegistryImpl
     MPU_vQueueAddToRegistry_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vQueueAddToRegistry
 /*-----------------------------------------------------------*/
 
@@ -649,12 +606,11 @@ MPU_vQueueUnregisterQueue:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vQueueUnregisterQueue_Unpriv
     MPU_vQueueUnregisterQueue_Priv:
-        pop {r0}
         b MPU_vQueueUnregisterQueueImpl
     MPU_vQueueUnregisterQueue_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vQueueUnregisterQueue
 /*-----------------------------------------------------------*/
 
@@ -663,12 +619,11 @@ MPU_pcQueueGetName:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_pcQueueGetName_Unpriv
     MPU_pcQueueGetName_Priv:
-        pop {r0}
         b MPU_pcQueueGetNameImpl
     MPU_pcQueueGetName_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_pcQueueGetName
 /*-----------------------------------------------------------*/
 
@@ -677,12 +632,11 @@ MPU_pvTimerGetTimerID:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_pvTimerGetTimerID_Unpriv
     MPU_pvTimerGetTimerID_Priv:
-        pop {r0}
         b MPU_pvTimerGetTimerIDImpl
     MPU_pvTimerGetTimerID_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_pvTimerGetTimerID
 /*-----------------------------------------------------------*/
 
@@ -691,12 +645,11 @@ MPU_vTimerSetTimerID:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTimerSetTimerID_Unpriv
     MPU_vTimerSetTimerID_Priv:
-        pop {r0}
         b MPU_vTimerSetTimerIDImpl
     MPU_vTimerSetTimerID_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTimerSetTimerID
 /*-----------------------------------------------------------*/
 
@@ -705,12 +658,11 @@ MPU_xTimerIsTimerActive:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerIsTimerActive_Unpriv
     MPU_xTimerIsTimerActive_Priv:
-        pop {r0}
         b MPU_xTimerIsTimerActiveImpl
     MPU_xTimerIsTimerActive_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerIsTimerActive
 /*-----------------------------------------------------------*/
 
@@ -719,12 +671,11 @@ MPU_xTimerGetTimerDaemonTaskHandle:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv
     MPU_xTimerGetTimerDaemonTaskHandle_Priv:
-        pop {r0}
         b MPU_xTimerGetTimerDaemonTaskHandleImpl
     MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle
 /*-----------------------------------------------------------*/
 
@@ -733,12 +684,11 @@ MPU_xTimerGenericCommandFromTaskEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerGenericCommandFromTask_Unpriv
     MPU_xTimerGenericCommandFromTask_Priv:
-        pop {r0}
         b MPU_xTimerGenericCommandFromTaskImpl
     MPU_xTimerGenericCommandFromTask_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerGenericCommandFromTask
 /*-----------------------------------------------------------*/
 
@@ -747,12 +697,11 @@ MPU_pcTimerGetName:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_pcTimerGetName_Unpriv
     MPU_pcTimerGetName_Priv:
-        pop {r0}
         b MPU_pcTimerGetNameImpl
     MPU_pcTimerGetName_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_pcTimerGetName
 /*-----------------------------------------------------------*/
 
@@ -761,12 +710,11 @@ MPU_vTimerSetReloadMode:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTimerSetReloadMode_Unpriv
     MPU_vTimerSetReloadMode_Priv:
-        pop {r0}
         b MPU_vTimerSetReloadModeImpl
     MPU_vTimerSetReloadMode_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTimerSetReloadMode
 /*-----------------------------------------------------------*/
 
@@ -775,12 +723,11 @@ MPU_xTimerGetReloadMode:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerGetReloadMode_Unpriv
     MPU_xTimerGetReloadMode_Priv:
-        pop {r0}
         b MPU_xTimerGetReloadModeImpl
     MPU_xTimerGetReloadMode_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerGetReloadMode
 /*-----------------------------------------------------------*/
 
@@ -789,12 +736,11 @@ MPU_uxTimerGetReloadMode:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTimerGetReloadMode_Unpriv
     MPU_uxTimerGetReloadMode_Priv:
-        pop {r0}
         b MPU_uxTimerGetReloadModeImpl
     MPU_uxTimerGetReloadMode_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTimerGetReloadMode
 /*-----------------------------------------------------------*/
 
@@ -803,12 +749,11 @@ MPU_xTimerGetPeriod:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerGetPeriod_Unpriv
     MPU_xTimerGetPeriod_Priv:
-        pop {r0}
         b MPU_xTimerGetPeriodImpl
     MPU_xTimerGetPeriod_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerGetPeriod
 /*-----------------------------------------------------------*/
 
@@ -817,12 +762,11 @@ MPU_xTimerGetExpiryTime:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerGetExpiryTime_Unpriv
     MPU_xTimerGetExpiryTime_Priv:
-        pop {r0}
         b MPU_xTimerGetExpiryTimeImpl
     MPU_xTimerGetExpiryTime_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerGetExpiryTime
 /*-----------------------------------------------------------*/
 
@@ -831,12 +775,11 @@ MPU_xEventGroupWaitBitsEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xEventGroupWaitBits_Unpriv
     MPU_xEventGroupWaitBits_Priv:
-        pop {r0}
         b MPU_xEventGroupWaitBitsImpl
     MPU_xEventGroupWaitBits_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xEventGroupWaitBits
 /*-----------------------------------------------------------*/
 
@@ -845,12 +788,11 @@ MPU_xEventGroupClearBits:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xEventGroupClearBits_Unpriv
     MPU_xEventGroupClearBits_Priv:
-        pop {r0}
         b MPU_xEventGroupClearBitsImpl
     MPU_xEventGroupClearBits_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xEventGroupClearBits
 /*-----------------------------------------------------------*/
 
@@ -859,12 +801,11 @@ MPU_xEventGroupSetBits:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xEventGroupSetBits_Unpriv
     MPU_xEventGroupSetBits_Priv:
-        pop {r0}
         b MPU_xEventGroupSetBitsImpl
     MPU_xEventGroupSetBits_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xEventGroupSetBits
 /*-----------------------------------------------------------*/
 
@@ -873,12 +814,11 @@ MPU_xEventGroupSync:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xEventGroupSync_Unpriv
     MPU_xEventGroupSync_Priv:
-        pop {r0}
         b MPU_xEventGroupSyncImpl
     MPU_xEventGroupSync_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xEventGroupSync
 /*-----------------------------------------------------------*/
 
@@ -887,12 +827,11 @@ MPU_uxEventGroupGetNumber:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxEventGroupGetNumber_Unpriv
     MPU_uxEventGroupGetNumber_Priv:
-        pop {r0}
         b MPU_uxEventGroupGetNumberImpl
     MPU_uxEventGroupGetNumber_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxEventGroupGetNumber
 /*-----------------------------------------------------------*/
 
@@ -901,12 +840,11 @@ MPU_vEventGroupSetNumber:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vEventGroupSetNumber_Unpriv
     MPU_vEventGroupSetNumber_Priv:
-        pop {r0}
         b MPU_vEventGroupSetNumberImpl
     MPU_vEventGroupSetNumber_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vEventGroupSetNumber
 /*-----------------------------------------------------------*/
 
@@ -915,12 +853,11 @@ MPU_xStreamBufferSend:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferSend_Unpriv
     MPU_xStreamBufferSend_Priv:
-        pop {r0}
         b MPU_xStreamBufferSendImpl
     MPU_xStreamBufferSend_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferSend
 /*-----------------------------------------------------------*/
 
@@ -929,12 +866,11 @@ MPU_xStreamBufferReceive:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferReceive_Unpriv
     MPU_xStreamBufferReceive_Priv:
-        pop {r0}
         b MPU_xStreamBufferReceiveImpl
     MPU_xStreamBufferReceive_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferReceive
 /*-----------------------------------------------------------*/
 
@@ -943,12 +879,11 @@ MPU_xStreamBufferIsFull:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferIsFull_Unpriv
     MPU_xStreamBufferIsFull_Priv:
-        pop {r0}
         b MPU_xStreamBufferIsFullImpl
     MPU_xStreamBufferIsFull_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferIsFull
 /*-----------------------------------------------------------*/
 
@@ -957,12 +892,11 @@ MPU_xStreamBufferIsEmpty:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferIsEmpty_Unpriv
     MPU_xStreamBufferIsEmpty_Priv:
-        pop {r0}
         b MPU_xStreamBufferIsEmptyImpl
     MPU_xStreamBufferIsEmpty_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferIsEmpty
 /*-----------------------------------------------------------*/
 
@@ -971,12 +905,11 @@ MPU_xStreamBufferSpacesAvailable:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferSpacesAvailable_Unpriv
     MPU_xStreamBufferSpacesAvailable_Priv:
-        pop {r0}
         b MPU_xStreamBufferSpacesAvailableImpl
     MPU_xStreamBufferSpacesAvailable_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferSpacesAvailable
 /*-----------------------------------------------------------*/
 
@@ -985,12 +918,11 @@ MPU_xStreamBufferBytesAvailable:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferBytesAvailable_Unpriv
     MPU_xStreamBufferBytesAvailable_Priv:
-        pop {r0}
         b MPU_xStreamBufferBytesAvailableImpl
     MPU_xStreamBufferBytesAvailable_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferBytesAvailable
 /*-----------------------------------------------------------*/
 
@@ -999,12 +931,11 @@ MPU_xStreamBufferSetTriggerLevel:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferSetTriggerLevel_Unpriv
     MPU_xStreamBufferSetTriggerLevel_Priv:
-        pop {r0}
         b MPU_xStreamBufferSetTriggerLevelImpl
     MPU_xStreamBufferSetTriggerLevel_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel
 /*-----------------------------------------------------------*/
 
@@ -1013,12 +944,11 @@ MPU_xStreamBufferNextMessageLengthBytes:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv
     MPU_xStreamBufferNextMessageLengthBytes_Priv:
-        pop {r0}
         b MPU_xStreamBufferNextMessageLengthBytesImpl
     MPU_xStreamBufferNextMessageLengthBytes_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.S
index a69845eda..d2cb78e92 100644
--- a/portable/IAR/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.S
+++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.S
@@ -47,12 +47,11 @@ MPU_xTaskDelayUntil:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskDelayUntil_Unpriv
     MPU_xTaskDelayUntil_Priv:
-        pop {r0}
         b MPU_xTaskDelayUntilImpl
     MPU_xTaskDelayUntil_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskDelayUntil
 /*-----------------------------------------------------------*/
 
@@ -61,12 +60,11 @@ MPU_xTaskAbortDelay:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskAbortDelay_Unpriv
     MPU_xTaskAbortDelay_Priv:
-        pop {r0}
         b MPU_xTaskAbortDelayImpl
     MPU_xTaskAbortDelay_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskAbortDelay
 /*-----------------------------------------------------------*/
 
@@ -75,12 +73,11 @@ MPU_vTaskDelay:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskDelay_Unpriv
     MPU_vTaskDelay_Priv:
-        pop {r0}
         b MPU_vTaskDelayImpl
     MPU_vTaskDelay_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskDelay
 /*-----------------------------------------------------------*/
 
@@ -89,12 +86,11 @@ MPU_uxTaskPriorityGet:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTaskPriorityGet_Unpriv
     MPU_uxTaskPriorityGet_Priv:
-        pop {r0}
         b MPU_uxTaskPriorityGetImpl
     MPU_uxTaskPriorityGet_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTaskPriorityGet
 /*-----------------------------------------------------------*/
 
@@ -103,12 +99,11 @@ MPU_eTaskGetState:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_eTaskGetState_Unpriv
     MPU_eTaskGetState_Priv:
-        pop {r0}
         b MPU_eTaskGetStateImpl
     MPU_eTaskGetState_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_eTaskGetState
 /*-----------------------------------------------------------*/
 
@@ -117,12 +112,11 @@ MPU_vTaskGetInfo:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskGetInfo_Unpriv
     MPU_vTaskGetInfo_Priv:
-        pop {r0}
         b MPU_vTaskGetInfoImpl
     MPU_vTaskGetInfo_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskGetInfo
 /*-----------------------------------------------------------*/
 
@@ -131,12 +125,11 @@ MPU_xTaskGetIdleTaskHandle:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGetIdleTaskHandle_Unpriv
     MPU_xTaskGetIdleTaskHandle_Priv:
-        pop {r0}
         b MPU_xTaskGetIdleTaskHandleImpl
     MPU_xTaskGetIdleTaskHandle_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGetIdleTaskHandle
 /*-----------------------------------------------------------*/
 
@@ -145,12 +138,11 @@ MPU_vTaskSuspend:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskSuspend_Unpriv
     MPU_vTaskSuspend_Priv:
-        pop {r0}
         b MPU_vTaskSuspendImpl
     MPU_vTaskSuspend_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskSuspend
 /*-----------------------------------------------------------*/
 
@@ -159,12 +151,11 @@ MPU_vTaskResume:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskResume_Unpriv
     MPU_vTaskResume_Priv:
-        pop {r0}
         b MPU_vTaskResumeImpl
     MPU_vTaskResume_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskResume
 /*-----------------------------------------------------------*/
 
@@ -173,12 +164,11 @@ MPU_xTaskGetTickCount:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGetTickCount_Unpriv
     MPU_xTaskGetTickCount_Priv:
-        pop {r0}
         b MPU_xTaskGetTickCountImpl
     MPU_xTaskGetTickCount_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGetTickCount
 /*-----------------------------------------------------------*/
 
@@ -187,12 +177,11 @@ MPU_uxTaskGetNumberOfTasks:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTaskGetNumberOfTasks_Unpriv
     MPU_uxTaskGetNumberOfTasks_Priv:
-        pop {r0}
         b MPU_uxTaskGetNumberOfTasksImpl
     MPU_uxTaskGetNumberOfTasks_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTaskGetNumberOfTasks
 /*-----------------------------------------------------------*/
 
@@ -201,12 +190,11 @@ MPU_ulTaskGetRunTimeCounter:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGetRunTimeCounter_Unpriv
     MPU_ulTaskGetRunTimeCounter_Priv:
-        pop {r0}
         b MPU_ulTaskGetRunTimeCounterImpl
     MPU_ulTaskGetRunTimeCounter_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGetRunTimeCounter
 /*-----------------------------------------------------------*/
 
@@ -215,12 +203,11 @@ MPU_ulTaskGetRunTimePercent:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGetRunTimePercent_Unpriv
     MPU_ulTaskGetRunTimePercent_Priv:
-        pop {r0}
         b MPU_ulTaskGetRunTimePercentImpl
     MPU_ulTaskGetRunTimePercent_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGetRunTimePercent
 /*-----------------------------------------------------------*/
 
@@ -229,12 +216,11 @@ MPU_ulTaskGetIdleRunTimePercent:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGetIdleRunTimePercent_Unpriv
     MPU_ulTaskGetIdleRunTimePercent_Priv:
-        pop {r0}
         b MPU_ulTaskGetIdleRunTimePercentImpl
     MPU_ulTaskGetIdleRunTimePercent_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent
 /*-----------------------------------------------------------*/
 
@@ -243,12 +229,11 @@ MPU_ulTaskGetIdleRunTimeCounter:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv
     MPU_ulTaskGetIdleRunTimeCounter_Priv:
-        pop {r0}
         b MPU_ulTaskGetIdleRunTimeCounterImpl
     MPU_ulTaskGetIdleRunTimeCounter_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter
 /*-----------------------------------------------------------*/
 
@@ -257,12 +242,11 @@ MPU_vTaskSetApplicationTaskTag:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskSetApplicationTaskTag_Unpriv
     MPU_vTaskSetApplicationTaskTag_Priv:
-        pop {r0}
         b MPU_vTaskSetApplicationTaskTagImpl
     MPU_vTaskSetApplicationTaskTag_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskSetApplicationTaskTag
 /*-----------------------------------------------------------*/
 
@@ -271,12 +255,11 @@ MPU_xTaskGetApplicationTaskTag:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGetApplicationTaskTag_Unpriv
     MPU_xTaskGetApplicationTaskTag_Priv:
-        pop {r0}
         b MPU_xTaskGetApplicationTaskTagImpl
     MPU_xTaskGetApplicationTaskTag_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGetApplicationTaskTag
 /*-----------------------------------------------------------*/
 
@@ -285,12 +268,11 @@ MPU_vTaskSetThreadLocalStoragePointer:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv
     MPU_vTaskSetThreadLocalStoragePointer_Priv:
-        pop {r0}
         b MPU_vTaskSetThreadLocalStoragePointerImpl
     MPU_vTaskSetThreadLocalStoragePointer_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer
 /*-----------------------------------------------------------*/
 
@@ -299,12 +281,11 @@ MPU_pvTaskGetThreadLocalStoragePointer:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv
     MPU_pvTaskGetThreadLocalStoragePointer_Priv:
-        pop {r0}
         b MPU_pvTaskGetThreadLocalStoragePointerImpl
     MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer
 /*-----------------------------------------------------------*/
 
@@ -313,12 +294,11 @@ MPU_uxTaskGetSystemState:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTaskGetSystemState_Unpriv
     MPU_uxTaskGetSystemState_Priv:
-        pop {r0}
         b MPU_uxTaskGetSystemStateImpl
     MPU_uxTaskGetSystemState_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTaskGetSystemState
 /*-----------------------------------------------------------*/
 
@@ -327,12 +307,11 @@ MPU_uxTaskGetStackHighWaterMark:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTaskGetStackHighWaterMark_Unpriv
     MPU_uxTaskGetStackHighWaterMark_Priv:
-        pop {r0}
         b MPU_uxTaskGetStackHighWaterMarkImpl
     MPU_uxTaskGetStackHighWaterMark_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark
 /*-----------------------------------------------------------*/
 
@@ -341,12 +320,11 @@ MPU_uxTaskGetStackHighWaterMark2:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTaskGetStackHighWaterMark2_Unpriv
     MPU_uxTaskGetStackHighWaterMark2_Priv:
-        pop {r0}
         b MPU_uxTaskGetStackHighWaterMark2Impl
     MPU_uxTaskGetStackHighWaterMark2_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2
 /*-----------------------------------------------------------*/
 
@@ -355,12 +333,11 @@ MPU_xTaskGetCurrentTaskHandle:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGetCurrentTaskHandle_Unpriv
     MPU_xTaskGetCurrentTaskHandle_Priv:
-        pop {r0}
         b MPU_xTaskGetCurrentTaskHandleImpl
     MPU_xTaskGetCurrentTaskHandle_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle
 /*-----------------------------------------------------------*/
 
@@ -369,12 +346,11 @@ MPU_xTaskGetSchedulerState:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGetSchedulerState_Unpriv
     MPU_xTaskGetSchedulerState_Priv:
-        pop {r0}
         b MPU_xTaskGetSchedulerStateImpl
     MPU_xTaskGetSchedulerState_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGetSchedulerState
 /*-----------------------------------------------------------*/
 
@@ -383,12 +359,11 @@ MPU_vTaskSetTimeOutState:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskSetTimeOutState_Unpriv
     MPU_vTaskSetTimeOutState_Priv:
-        pop {r0}
         b MPU_vTaskSetTimeOutStateImpl
     MPU_vTaskSetTimeOutState_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskSetTimeOutState
 /*-----------------------------------------------------------*/
 
@@ -397,12 +372,11 @@ MPU_xTaskCheckForTimeOut:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskCheckForTimeOut_Unpriv
     MPU_xTaskCheckForTimeOut_Priv:
-        pop {r0}
         b MPU_xTaskCheckForTimeOutImpl
     MPU_xTaskCheckForTimeOut_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskCheckForTimeOut
 /*-----------------------------------------------------------*/
 
@@ -411,12 +385,11 @@ MPU_xTaskGenericNotifyEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGenericNotify_Unpriv
     MPU_xTaskGenericNotify_Priv:
-        pop {r0}
         b MPU_xTaskGenericNotifyImpl
     MPU_xTaskGenericNotify_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGenericNotify
 /*-----------------------------------------------------------*/
 
@@ -425,12 +398,11 @@ MPU_xTaskGenericNotifyWaitEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGenericNotifyWait_Unpriv
     MPU_xTaskGenericNotifyWait_Priv:
-        pop {r0}
         b MPU_xTaskGenericNotifyWaitImpl
     MPU_xTaskGenericNotifyWait_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGenericNotifyWait
 /*-----------------------------------------------------------*/
 
@@ -439,12 +411,11 @@ MPU_ulTaskGenericNotifyTake:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGenericNotifyTake_Unpriv
     MPU_ulTaskGenericNotifyTake_Priv:
-        pop {r0}
         b MPU_ulTaskGenericNotifyTakeImpl
     MPU_ulTaskGenericNotifyTake_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGenericNotifyTake
 /*-----------------------------------------------------------*/
 
@@ -453,12 +424,11 @@ MPU_xTaskGenericNotifyStateClear:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGenericNotifyStateClear_Unpriv
     MPU_xTaskGenericNotifyStateClear_Priv:
-        pop {r0}
         b MPU_xTaskGenericNotifyStateClearImpl
     MPU_xTaskGenericNotifyStateClear_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGenericNotifyStateClear
 /*-----------------------------------------------------------*/
 
@@ -467,12 +437,11 @@ MPU_ulTaskGenericNotifyValueClear:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGenericNotifyValueClear_Unpriv
     MPU_ulTaskGenericNotifyValueClear_Priv:
-        pop {r0}
         b MPU_ulTaskGenericNotifyValueClearImpl
     MPU_ulTaskGenericNotifyValueClear_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear
 /*-----------------------------------------------------------*/
 
@@ -481,12 +450,11 @@ MPU_xQueueGenericSend:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueGenericSend_Unpriv
     MPU_xQueueGenericSend_Priv:
-        pop {r0}
         b MPU_xQueueGenericSendImpl
     MPU_xQueueGenericSend_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueGenericSend
 /*-----------------------------------------------------------*/
 
@@ -495,12 +463,11 @@ MPU_uxQueueMessagesWaiting:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxQueueMessagesWaiting_Unpriv
     MPU_uxQueueMessagesWaiting_Priv:
-        pop {r0}
         b MPU_uxQueueMessagesWaitingImpl
     MPU_uxQueueMessagesWaiting_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxQueueMessagesWaiting
 /*-----------------------------------------------------------*/
 
@@ -509,12 +476,11 @@ MPU_uxQueueSpacesAvailable:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxQueueSpacesAvailable_Unpriv
     MPU_uxQueueSpacesAvailable_Priv:
-        pop {r0}
         b MPU_uxQueueSpacesAvailableImpl
     MPU_uxQueueSpacesAvailable_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxQueueSpacesAvailable
 /*-----------------------------------------------------------*/
 
@@ -523,12 +489,11 @@ MPU_xQueueReceive:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueReceive_Unpriv
     MPU_xQueueReceive_Priv:
-        pop {r0}
         b MPU_xQueueReceiveImpl
     MPU_xQueueReceive_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueReceive
 /*-----------------------------------------------------------*/
 
@@ -537,12 +502,11 @@ MPU_xQueuePeek:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueuePeek_Unpriv
     MPU_xQueuePeek_Priv:
-        pop {r0}
         b MPU_xQueuePeekImpl
     MPU_xQueuePeek_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueuePeek
 /*-----------------------------------------------------------*/
 
@@ -551,12 +515,11 @@ MPU_xQueueSemaphoreTake:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueSemaphoreTake_Unpriv
     MPU_xQueueSemaphoreTake_Priv:
-        pop {r0}
         b MPU_xQueueSemaphoreTakeImpl
     MPU_xQueueSemaphoreTake_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueSemaphoreTake
 /*-----------------------------------------------------------*/
 
@@ -565,12 +528,11 @@ MPU_xQueueGetMutexHolder:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueGetMutexHolder_Unpriv
     MPU_xQueueGetMutexHolder_Priv:
-        pop {r0}
         b MPU_xQueueGetMutexHolderImpl
     MPU_xQueueGetMutexHolder_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueGetMutexHolder
 /*-----------------------------------------------------------*/
 
@@ -579,12 +541,11 @@ MPU_xQueueTakeMutexRecursive:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueTakeMutexRecursive_Unpriv
     MPU_xQueueTakeMutexRecursive_Priv:
-        pop {r0}
         b MPU_xQueueTakeMutexRecursiveImpl
     MPU_xQueueTakeMutexRecursive_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueTakeMutexRecursive
 /*-----------------------------------------------------------*/
 
@@ -593,12 +554,11 @@ MPU_xQueueGiveMutexRecursive:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueGiveMutexRecursive_Unpriv
     MPU_xQueueGiveMutexRecursive_Priv:
-        pop {r0}
         b MPU_xQueueGiveMutexRecursiveImpl
     MPU_xQueueGiveMutexRecursive_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueGiveMutexRecursive
 /*-----------------------------------------------------------*/
 
@@ -607,12 +567,11 @@ MPU_xQueueSelectFromSet:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueSelectFromSet_Unpriv
     MPU_xQueueSelectFromSet_Priv:
-        pop {r0}
         b MPU_xQueueSelectFromSetImpl
     MPU_xQueueSelectFromSet_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueSelectFromSet
 /*-----------------------------------------------------------*/
 
@@ -621,12 +580,11 @@ MPU_xQueueAddToSet:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueAddToSet_Unpriv
     MPU_xQueueAddToSet_Priv:
-        pop {r0}
         b MPU_xQueueAddToSetImpl
     MPU_xQueueAddToSet_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueAddToSet
 /*-----------------------------------------------------------*/
 
@@ -635,12 +593,11 @@ MPU_vQueueAddToRegistry:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vQueueAddToRegistry_Unpriv
     MPU_vQueueAddToRegistry_Priv:
-        pop {r0}
         b MPU_vQueueAddToRegistryImpl
     MPU_vQueueAddToRegistry_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vQueueAddToRegistry
 /*-----------------------------------------------------------*/
 
@@ -649,12 +606,11 @@ MPU_vQueueUnregisterQueue:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vQueueUnregisterQueue_Unpriv
     MPU_vQueueUnregisterQueue_Priv:
-        pop {r0}
         b MPU_vQueueUnregisterQueueImpl
     MPU_vQueueUnregisterQueue_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vQueueUnregisterQueue
 /*-----------------------------------------------------------*/
 
@@ -663,12 +619,11 @@ MPU_pcQueueGetName:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_pcQueueGetName_Unpriv
     MPU_pcQueueGetName_Priv:
-        pop {r0}
         b MPU_pcQueueGetNameImpl
     MPU_pcQueueGetName_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_pcQueueGetName
 /*-----------------------------------------------------------*/
 
@@ -677,12 +632,11 @@ MPU_pvTimerGetTimerID:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_pvTimerGetTimerID_Unpriv
     MPU_pvTimerGetTimerID_Priv:
-        pop {r0}
         b MPU_pvTimerGetTimerIDImpl
     MPU_pvTimerGetTimerID_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_pvTimerGetTimerID
 /*-----------------------------------------------------------*/
 
@@ -691,12 +645,11 @@ MPU_vTimerSetTimerID:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTimerSetTimerID_Unpriv
     MPU_vTimerSetTimerID_Priv:
-        pop {r0}
         b MPU_vTimerSetTimerIDImpl
     MPU_vTimerSetTimerID_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTimerSetTimerID
 /*-----------------------------------------------------------*/
 
@@ -705,12 +658,11 @@ MPU_xTimerIsTimerActive:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerIsTimerActive_Unpriv
     MPU_xTimerIsTimerActive_Priv:
-        pop {r0}
         b MPU_xTimerIsTimerActiveImpl
     MPU_xTimerIsTimerActive_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerIsTimerActive
 /*-----------------------------------------------------------*/
 
@@ -719,12 +671,11 @@ MPU_xTimerGetTimerDaemonTaskHandle:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv
     MPU_xTimerGetTimerDaemonTaskHandle_Priv:
-        pop {r0}
         b MPU_xTimerGetTimerDaemonTaskHandleImpl
     MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle
 /*-----------------------------------------------------------*/
 
@@ -733,12 +684,11 @@ MPU_xTimerGenericCommandFromTaskEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerGenericCommandFromTask_Unpriv
     MPU_xTimerGenericCommandFromTask_Priv:
-        pop {r0}
         b MPU_xTimerGenericCommandFromTaskImpl
     MPU_xTimerGenericCommandFromTask_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerGenericCommandFromTask
 /*-----------------------------------------------------------*/
 
@@ -747,12 +697,11 @@ MPU_pcTimerGetName:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_pcTimerGetName_Unpriv
     MPU_pcTimerGetName_Priv:
-        pop {r0}
         b MPU_pcTimerGetNameImpl
     MPU_pcTimerGetName_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_pcTimerGetName
 /*-----------------------------------------------------------*/
 
@@ -761,12 +710,11 @@ MPU_vTimerSetReloadMode:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTimerSetReloadMode_Unpriv
     MPU_vTimerSetReloadMode_Priv:
-        pop {r0}
         b MPU_vTimerSetReloadModeImpl
     MPU_vTimerSetReloadMode_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTimerSetReloadMode
 /*-----------------------------------------------------------*/
 
@@ -775,12 +723,11 @@ MPU_xTimerGetReloadMode:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerGetReloadMode_Unpriv
     MPU_xTimerGetReloadMode_Priv:
-        pop {r0}
         b MPU_xTimerGetReloadModeImpl
     MPU_xTimerGetReloadMode_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerGetReloadMode
 /*-----------------------------------------------------------*/
 
@@ -789,12 +736,11 @@ MPU_uxTimerGetReloadMode:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTimerGetReloadMode_Unpriv
     MPU_uxTimerGetReloadMode_Priv:
-        pop {r0}
         b MPU_uxTimerGetReloadModeImpl
     MPU_uxTimerGetReloadMode_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTimerGetReloadMode
 /*-----------------------------------------------------------*/
 
@@ -803,12 +749,11 @@ MPU_xTimerGetPeriod:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerGetPeriod_Unpriv
     MPU_xTimerGetPeriod_Priv:
-        pop {r0}
         b MPU_xTimerGetPeriodImpl
     MPU_xTimerGetPeriod_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerGetPeriod
 /*-----------------------------------------------------------*/
 
@@ -817,12 +762,11 @@ MPU_xTimerGetExpiryTime:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerGetExpiryTime_Unpriv
     MPU_xTimerGetExpiryTime_Priv:
-        pop {r0}
         b MPU_xTimerGetExpiryTimeImpl
     MPU_xTimerGetExpiryTime_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerGetExpiryTime
 /*-----------------------------------------------------------*/
 
@@ -831,12 +775,11 @@ MPU_xEventGroupWaitBitsEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xEventGroupWaitBits_Unpriv
     MPU_xEventGroupWaitBits_Priv:
-        pop {r0}
         b MPU_xEventGroupWaitBitsImpl
     MPU_xEventGroupWaitBits_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xEventGroupWaitBits
 /*-----------------------------------------------------------*/
 
@@ -845,12 +788,11 @@ MPU_xEventGroupClearBits:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xEventGroupClearBits_Unpriv
     MPU_xEventGroupClearBits_Priv:
-        pop {r0}
         b MPU_xEventGroupClearBitsImpl
     MPU_xEventGroupClearBits_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xEventGroupClearBits
 /*-----------------------------------------------------------*/
 
@@ -859,12 +801,11 @@ MPU_xEventGroupSetBits:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xEventGroupSetBits_Unpriv
     MPU_xEventGroupSetBits_Priv:
-        pop {r0}
         b MPU_xEventGroupSetBitsImpl
     MPU_xEventGroupSetBits_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xEventGroupSetBits
 /*-----------------------------------------------------------*/
 
@@ -873,12 +814,11 @@ MPU_xEventGroupSync:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xEventGroupSync_Unpriv
     MPU_xEventGroupSync_Priv:
-        pop {r0}
         b MPU_xEventGroupSyncImpl
     MPU_xEventGroupSync_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xEventGroupSync
 /*-----------------------------------------------------------*/
 
@@ -887,12 +827,11 @@ MPU_uxEventGroupGetNumber:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxEventGroupGetNumber_Unpriv
     MPU_uxEventGroupGetNumber_Priv:
-        pop {r0}
         b MPU_uxEventGroupGetNumberImpl
     MPU_uxEventGroupGetNumber_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxEventGroupGetNumber
 /*-----------------------------------------------------------*/
 
@@ -901,12 +840,11 @@ MPU_vEventGroupSetNumber:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vEventGroupSetNumber_Unpriv
     MPU_vEventGroupSetNumber_Priv:
-        pop {r0}
         b MPU_vEventGroupSetNumberImpl
     MPU_vEventGroupSetNumber_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vEventGroupSetNumber
 /*-----------------------------------------------------------*/
 
@@ -915,12 +853,11 @@ MPU_xStreamBufferSend:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferSend_Unpriv
     MPU_xStreamBufferSend_Priv:
-        pop {r0}
         b MPU_xStreamBufferSendImpl
     MPU_xStreamBufferSend_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferSend
 /*-----------------------------------------------------------*/
 
@@ -929,12 +866,11 @@ MPU_xStreamBufferReceive:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferReceive_Unpriv
     MPU_xStreamBufferReceive_Priv:
-        pop {r0}
         b MPU_xStreamBufferReceiveImpl
     MPU_xStreamBufferReceive_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferReceive
 /*-----------------------------------------------------------*/
 
@@ -943,12 +879,11 @@ MPU_xStreamBufferIsFull:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferIsFull_Unpriv
     MPU_xStreamBufferIsFull_Priv:
-        pop {r0}
         b MPU_xStreamBufferIsFullImpl
     MPU_xStreamBufferIsFull_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferIsFull
 /*-----------------------------------------------------------*/
 
@@ -957,12 +892,11 @@ MPU_xStreamBufferIsEmpty:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferIsEmpty_Unpriv
     MPU_xStreamBufferIsEmpty_Priv:
-        pop {r0}
         b MPU_xStreamBufferIsEmptyImpl
     MPU_xStreamBufferIsEmpty_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferIsEmpty
 /*-----------------------------------------------------------*/
 
@@ -971,12 +905,11 @@ MPU_xStreamBufferSpacesAvailable:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferSpacesAvailable_Unpriv
     MPU_xStreamBufferSpacesAvailable_Priv:
-        pop {r0}
         b MPU_xStreamBufferSpacesAvailableImpl
     MPU_xStreamBufferSpacesAvailable_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferSpacesAvailable
 /*-----------------------------------------------------------*/
 
@@ -985,12 +918,11 @@ MPU_xStreamBufferBytesAvailable:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferBytesAvailable_Unpriv
     MPU_xStreamBufferBytesAvailable_Priv:
-        pop {r0}
         b MPU_xStreamBufferBytesAvailableImpl
     MPU_xStreamBufferBytesAvailable_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferBytesAvailable
 /*-----------------------------------------------------------*/
 
@@ -999,12 +931,11 @@ MPU_xStreamBufferSetTriggerLevel:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferSetTriggerLevel_Unpriv
     MPU_xStreamBufferSetTriggerLevel_Priv:
-        pop {r0}
         b MPU_xStreamBufferSetTriggerLevelImpl
     MPU_xStreamBufferSetTriggerLevel_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel
 /*-----------------------------------------------------------*/
 
@@ -1013,12 +944,11 @@ MPU_xStreamBufferNextMessageLengthBytes:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv
     MPU_xStreamBufferNextMessageLengthBytes_Priv:
-        pop {r0}
         b MPU_xStreamBufferNextMessageLengthBytesImpl
     MPU_xStreamBufferNextMessageLengthBytes_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM4F_MPU/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM4F_MPU/mpu_wrappers_v2_asm.S
index bf91e99c6..f01c01d42 100644
--- a/portable/IAR/ARM_CM4F_MPU/mpu_wrappers_v2_asm.S
+++ b/portable/IAR/ARM_CM4F_MPU/mpu_wrappers_v2_asm.S
@@ -51,12 +51,11 @@ MPU_xTaskDelayUntil:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskDelayUntil_Unpriv
     MPU_xTaskDelayUntil_Priv:
-        pop {r0}
         b MPU_xTaskDelayUntilImpl
     MPU_xTaskDelayUntil_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskDelayUntil
 /*-----------------------------------------------------------*/
 
@@ -65,12 +64,11 @@ MPU_xTaskAbortDelay:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskAbortDelay_Unpriv
     MPU_xTaskAbortDelay_Priv:
-        pop {r0}
         b MPU_xTaskAbortDelayImpl
     MPU_xTaskAbortDelay_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskAbortDelay
 /*-----------------------------------------------------------*/
 
@@ -79,12 +77,11 @@ MPU_vTaskDelay:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskDelay_Unpriv
     MPU_vTaskDelay_Priv:
-        pop {r0}
         b MPU_vTaskDelayImpl
     MPU_vTaskDelay_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskDelay
 /*-----------------------------------------------------------*/
 
@@ -93,12 +90,11 @@ MPU_uxTaskPriorityGet:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTaskPriorityGet_Unpriv
     MPU_uxTaskPriorityGet_Priv:
-        pop {r0}
         b MPU_uxTaskPriorityGetImpl
     MPU_uxTaskPriorityGet_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTaskPriorityGet
 /*-----------------------------------------------------------*/
 
@@ -107,12 +103,11 @@ MPU_eTaskGetState:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_eTaskGetState_Unpriv
     MPU_eTaskGetState_Priv:
-        pop {r0}
         b MPU_eTaskGetStateImpl
     MPU_eTaskGetState_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_eTaskGetState
 /*-----------------------------------------------------------*/
 
@@ -121,12 +116,11 @@ MPU_vTaskGetInfo:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskGetInfo_Unpriv
     MPU_vTaskGetInfo_Priv:
-        pop {r0}
         b MPU_vTaskGetInfoImpl
     MPU_vTaskGetInfo_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskGetInfo
 /*-----------------------------------------------------------*/
 
@@ -135,12 +129,11 @@ MPU_xTaskGetIdleTaskHandle:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGetIdleTaskHandle_Unpriv
     MPU_xTaskGetIdleTaskHandle_Priv:
-        pop {r0}
         b MPU_xTaskGetIdleTaskHandleImpl
     MPU_xTaskGetIdleTaskHandle_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGetIdleTaskHandle
 /*-----------------------------------------------------------*/
 
@@ -149,12 +142,11 @@ MPU_vTaskSuspend:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskSuspend_Unpriv
     MPU_vTaskSuspend_Priv:
-        pop {r0}
         b MPU_vTaskSuspendImpl
     MPU_vTaskSuspend_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskSuspend
 /*-----------------------------------------------------------*/
 
@@ -163,12 +155,11 @@ MPU_vTaskResume:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskResume_Unpriv
     MPU_vTaskResume_Priv:
-        pop {r0}
         b MPU_vTaskResumeImpl
     MPU_vTaskResume_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskResume
 /*-----------------------------------------------------------*/
 
@@ -177,12 +168,11 @@ MPU_xTaskGetTickCount:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGetTickCount_Unpriv
     MPU_xTaskGetTickCount_Priv:
-        pop {r0}
         b MPU_xTaskGetTickCountImpl
     MPU_xTaskGetTickCount_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGetTickCount
 /*-----------------------------------------------------------*/
 
@@ -191,12 +181,11 @@ MPU_uxTaskGetNumberOfTasks:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTaskGetNumberOfTasks_Unpriv
     MPU_uxTaskGetNumberOfTasks_Priv:
-        pop {r0}
         b MPU_uxTaskGetNumberOfTasksImpl
     MPU_uxTaskGetNumberOfTasks_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTaskGetNumberOfTasks
 /*-----------------------------------------------------------*/
 
@@ -205,12 +194,11 @@ MPU_ulTaskGetRunTimeCounter:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGetRunTimeCounter_Unpriv
     MPU_ulTaskGetRunTimeCounter_Priv:
-        pop {r0}
         b MPU_ulTaskGetRunTimeCounterImpl
     MPU_ulTaskGetRunTimeCounter_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGetRunTimeCounter
 /*-----------------------------------------------------------*/
 
@@ -219,12 +207,11 @@ MPU_ulTaskGetRunTimePercent:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGetRunTimePercent_Unpriv
     MPU_ulTaskGetRunTimePercent_Priv:
-        pop {r0}
         b MPU_ulTaskGetRunTimePercentImpl
     MPU_ulTaskGetRunTimePercent_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGetRunTimePercent
 /*-----------------------------------------------------------*/
 
@@ -233,12 +220,11 @@ MPU_ulTaskGetIdleRunTimePercent:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGetIdleRunTimePercent_Unpriv
     MPU_ulTaskGetIdleRunTimePercent_Priv:
-        pop {r0}
         b MPU_ulTaskGetIdleRunTimePercentImpl
     MPU_ulTaskGetIdleRunTimePercent_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent
 /*-----------------------------------------------------------*/
 
@@ -247,12 +233,11 @@ MPU_ulTaskGetIdleRunTimeCounter:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv
     MPU_ulTaskGetIdleRunTimeCounter_Priv:
-        pop {r0}
         b MPU_ulTaskGetIdleRunTimeCounterImpl
     MPU_ulTaskGetIdleRunTimeCounter_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter
 /*-----------------------------------------------------------*/
 
@@ -261,12 +246,11 @@ MPU_vTaskSetApplicationTaskTag:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskSetApplicationTaskTag_Unpriv
     MPU_vTaskSetApplicationTaskTag_Priv:
-        pop {r0}
         b MPU_vTaskSetApplicationTaskTagImpl
     MPU_vTaskSetApplicationTaskTag_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskSetApplicationTaskTag
 /*-----------------------------------------------------------*/
 
@@ -275,12 +259,11 @@ MPU_xTaskGetApplicationTaskTag:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGetApplicationTaskTag_Unpriv
     MPU_xTaskGetApplicationTaskTag_Priv:
-        pop {r0}
         b MPU_xTaskGetApplicationTaskTagImpl
     MPU_xTaskGetApplicationTaskTag_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGetApplicationTaskTag
 /*-----------------------------------------------------------*/
 
@@ -289,12 +272,11 @@ MPU_vTaskSetThreadLocalStoragePointer:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv
     MPU_vTaskSetThreadLocalStoragePointer_Priv:
-        pop {r0}
         b MPU_vTaskSetThreadLocalStoragePointerImpl
     MPU_vTaskSetThreadLocalStoragePointer_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer
 /*-----------------------------------------------------------*/
 
@@ -303,12 +285,11 @@ MPU_pvTaskGetThreadLocalStoragePointer:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv
     MPU_pvTaskGetThreadLocalStoragePointer_Priv:
-        pop {r0}
         b MPU_pvTaskGetThreadLocalStoragePointerImpl
     MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer
 /*-----------------------------------------------------------*/
 
@@ -317,12 +298,11 @@ MPU_uxTaskGetSystemState:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTaskGetSystemState_Unpriv
     MPU_uxTaskGetSystemState_Priv:
-        pop {r0}
         b MPU_uxTaskGetSystemStateImpl
     MPU_uxTaskGetSystemState_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTaskGetSystemState
 /*-----------------------------------------------------------*/
 
@@ -331,12 +311,11 @@ MPU_uxTaskGetStackHighWaterMark:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTaskGetStackHighWaterMark_Unpriv
     MPU_uxTaskGetStackHighWaterMark_Priv:
-        pop {r0}
         b MPU_uxTaskGetStackHighWaterMarkImpl
     MPU_uxTaskGetStackHighWaterMark_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark
 /*-----------------------------------------------------------*/
 
@@ -345,12 +324,11 @@ MPU_uxTaskGetStackHighWaterMark2:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTaskGetStackHighWaterMark2_Unpriv
     MPU_uxTaskGetStackHighWaterMark2_Priv:
-        pop {r0}
         b MPU_uxTaskGetStackHighWaterMark2Impl
     MPU_uxTaskGetStackHighWaterMark2_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2
 /*-----------------------------------------------------------*/
 
@@ -359,12 +337,11 @@ MPU_xTaskGetCurrentTaskHandle:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGetCurrentTaskHandle_Unpriv
     MPU_xTaskGetCurrentTaskHandle_Priv:
-        pop {r0}
         b MPU_xTaskGetCurrentTaskHandleImpl
     MPU_xTaskGetCurrentTaskHandle_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle
 /*-----------------------------------------------------------*/
 
@@ -373,12 +350,11 @@ MPU_xTaskGetSchedulerState:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGetSchedulerState_Unpriv
     MPU_xTaskGetSchedulerState_Priv:
-        pop {r0}
         b MPU_xTaskGetSchedulerStateImpl
     MPU_xTaskGetSchedulerState_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGetSchedulerState
 /*-----------------------------------------------------------*/
 
@@ -387,12 +363,11 @@ MPU_vTaskSetTimeOutState:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskSetTimeOutState_Unpriv
     MPU_vTaskSetTimeOutState_Priv:
-        pop {r0}
         b MPU_vTaskSetTimeOutStateImpl
     MPU_vTaskSetTimeOutState_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskSetTimeOutState
 /*-----------------------------------------------------------*/
 
@@ -401,12 +376,11 @@ MPU_xTaskCheckForTimeOut:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskCheckForTimeOut_Unpriv
     MPU_xTaskCheckForTimeOut_Priv:
-        pop {r0}
         b MPU_xTaskCheckForTimeOutImpl
     MPU_xTaskCheckForTimeOut_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskCheckForTimeOut
 /*-----------------------------------------------------------*/
 
@@ -415,12 +389,11 @@ MPU_xTaskGenericNotifyEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGenericNotify_Unpriv
     MPU_xTaskGenericNotify_Priv:
-        pop {r0}
         b MPU_xTaskGenericNotifyImpl
     MPU_xTaskGenericNotify_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGenericNotify
 /*-----------------------------------------------------------*/
 
@@ -429,12 +402,11 @@ MPU_xTaskGenericNotifyWaitEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGenericNotifyWait_Unpriv
     MPU_xTaskGenericNotifyWait_Priv:
-        pop {r0}
         b MPU_xTaskGenericNotifyWaitImpl
     MPU_xTaskGenericNotifyWait_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGenericNotifyWait
 /*-----------------------------------------------------------*/
 
@@ -443,12 +415,11 @@ MPU_ulTaskGenericNotifyTake:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGenericNotifyTake_Unpriv
     MPU_ulTaskGenericNotifyTake_Priv:
-        pop {r0}
         b MPU_ulTaskGenericNotifyTakeImpl
     MPU_ulTaskGenericNotifyTake_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGenericNotifyTake
 /*-----------------------------------------------------------*/
 
@@ -457,12 +428,11 @@ MPU_xTaskGenericNotifyStateClear:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGenericNotifyStateClear_Unpriv
     MPU_xTaskGenericNotifyStateClear_Priv:
-        pop {r0}
         b MPU_xTaskGenericNotifyStateClearImpl
     MPU_xTaskGenericNotifyStateClear_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGenericNotifyStateClear
 /*-----------------------------------------------------------*/
 
@@ -471,12 +441,11 @@ MPU_ulTaskGenericNotifyValueClear:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGenericNotifyValueClear_Unpriv
     MPU_ulTaskGenericNotifyValueClear_Priv:
-        pop {r0}
         b MPU_ulTaskGenericNotifyValueClearImpl
     MPU_ulTaskGenericNotifyValueClear_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear
 /*-----------------------------------------------------------*/
 
@@ -485,12 +454,11 @@ MPU_xQueueGenericSend:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueGenericSend_Unpriv
     MPU_xQueueGenericSend_Priv:
-        pop {r0}
         b MPU_xQueueGenericSendImpl
     MPU_xQueueGenericSend_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueGenericSend
 /*-----------------------------------------------------------*/
 
@@ -499,12 +467,11 @@ MPU_uxQueueMessagesWaiting:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxQueueMessagesWaiting_Unpriv
     MPU_uxQueueMessagesWaiting_Priv:
-        pop {r0}
         b MPU_uxQueueMessagesWaitingImpl
     MPU_uxQueueMessagesWaiting_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxQueueMessagesWaiting
 /*-----------------------------------------------------------*/
 
@@ -513,12 +480,11 @@ MPU_uxQueueSpacesAvailable:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxQueueSpacesAvailable_Unpriv
     MPU_uxQueueSpacesAvailable_Priv:
-        pop {r0}
         b MPU_uxQueueSpacesAvailableImpl
     MPU_uxQueueSpacesAvailable_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxQueueSpacesAvailable
 /*-----------------------------------------------------------*/
 
@@ -527,12 +493,11 @@ MPU_xQueueReceive:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueReceive_Unpriv
     MPU_xQueueReceive_Priv:
-        pop {r0}
         b MPU_xQueueReceiveImpl
     MPU_xQueueReceive_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueReceive
 /*-----------------------------------------------------------*/
 
@@ -541,12 +506,11 @@ MPU_xQueuePeek:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueuePeek_Unpriv
     MPU_xQueuePeek_Priv:
-        pop {r0}
         b MPU_xQueuePeekImpl
     MPU_xQueuePeek_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueuePeek
 /*-----------------------------------------------------------*/
 
@@ -555,12 +519,11 @@ MPU_xQueueSemaphoreTake:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueSemaphoreTake_Unpriv
     MPU_xQueueSemaphoreTake_Priv:
-        pop {r0}
         b MPU_xQueueSemaphoreTakeImpl
     MPU_xQueueSemaphoreTake_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueSemaphoreTake
 /*-----------------------------------------------------------*/
 
@@ -569,12 +532,11 @@ MPU_xQueueGetMutexHolder:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueGetMutexHolder_Unpriv
     MPU_xQueueGetMutexHolder_Priv:
-        pop {r0}
         b MPU_xQueueGetMutexHolderImpl
     MPU_xQueueGetMutexHolder_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueGetMutexHolder
 /*-----------------------------------------------------------*/
 
@@ -583,12 +545,11 @@ MPU_xQueueTakeMutexRecursive:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueTakeMutexRecursive_Unpriv
     MPU_xQueueTakeMutexRecursive_Priv:
-        pop {r0}
         b MPU_xQueueTakeMutexRecursiveImpl
     MPU_xQueueTakeMutexRecursive_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueTakeMutexRecursive
 /*-----------------------------------------------------------*/
 
@@ -597,12 +558,11 @@ MPU_xQueueGiveMutexRecursive:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueGiveMutexRecursive_Unpriv
     MPU_xQueueGiveMutexRecursive_Priv:
-        pop {r0}
         b MPU_xQueueGiveMutexRecursiveImpl
     MPU_xQueueGiveMutexRecursive_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueGiveMutexRecursive
 /*-----------------------------------------------------------*/
 
@@ -611,12 +571,11 @@ MPU_xQueueSelectFromSet:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueSelectFromSet_Unpriv
     MPU_xQueueSelectFromSet_Priv:
-        pop {r0}
         b MPU_xQueueSelectFromSetImpl
     MPU_xQueueSelectFromSet_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueSelectFromSet
 /*-----------------------------------------------------------*/
 
@@ -625,12 +584,11 @@ MPU_xQueueAddToSet:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueAddToSet_Unpriv
     MPU_xQueueAddToSet_Priv:
-        pop {r0}
         b MPU_xQueueAddToSetImpl
     MPU_xQueueAddToSet_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueAddToSet
 /*-----------------------------------------------------------*/
 
@@ -639,12 +597,11 @@ MPU_vQueueAddToRegistry:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vQueueAddToRegistry_Unpriv
     MPU_vQueueAddToRegistry_Priv:
-        pop {r0}
         b MPU_vQueueAddToRegistryImpl
     MPU_vQueueAddToRegistry_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vQueueAddToRegistry
 /*-----------------------------------------------------------*/
 
@@ -653,12 +610,11 @@ MPU_vQueueUnregisterQueue:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vQueueUnregisterQueue_Unpriv
     MPU_vQueueUnregisterQueue_Priv:
-        pop {r0}
         b MPU_vQueueUnregisterQueueImpl
     MPU_vQueueUnregisterQueue_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vQueueUnregisterQueue
 /*-----------------------------------------------------------*/
 
@@ -667,12 +623,11 @@ MPU_pcQueueGetName:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_pcQueueGetName_Unpriv
     MPU_pcQueueGetName_Priv:
-        pop {r0}
         b MPU_pcQueueGetNameImpl
     MPU_pcQueueGetName_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_pcQueueGetName
 /*-----------------------------------------------------------*/
 
@@ -681,12 +636,11 @@ MPU_pvTimerGetTimerID:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_pvTimerGetTimerID_Unpriv
     MPU_pvTimerGetTimerID_Priv:
-        pop {r0}
         b MPU_pvTimerGetTimerIDImpl
     MPU_pvTimerGetTimerID_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_pvTimerGetTimerID
 /*-----------------------------------------------------------*/
 
@@ -695,12 +649,11 @@ MPU_vTimerSetTimerID:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTimerSetTimerID_Unpriv
     MPU_vTimerSetTimerID_Priv:
-        pop {r0}
         b MPU_vTimerSetTimerIDImpl
     MPU_vTimerSetTimerID_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTimerSetTimerID
 /*-----------------------------------------------------------*/
 
@@ -709,12 +662,11 @@ MPU_xTimerIsTimerActive:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerIsTimerActive_Unpriv
     MPU_xTimerIsTimerActive_Priv:
-        pop {r0}
         b MPU_xTimerIsTimerActiveImpl
     MPU_xTimerIsTimerActive_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerIsTimerActive
 /*-----------------------------------------------------------*/
 
@@ -723,12 +675,11 @@ MPU_xTimerGetTimerDaemonTaskHandle:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv
     MPU_xTimerGetTimerDaemonTaskHandle_Priv:
-        pop {r0}
         b MPU_xTimerGetTimerDaemonTaskHandleImpl
     MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle
 /*-----------------------------------------------------------*/
 
@@ -737,12 +688,11 @@ MPU_xTimerGenericCommandFromTaskEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerGenericCommandFromTask_Unpriv
     MPU_xTimerGenericCommandFromTask_Priv:
-        pop {r0}
         b MPU_xTimerGenericCommandFromTaskImpl
     MPU_xTimerGenericCommandFromTask_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerGenericCommandFromTask
 /*-----------------------------------------------------------*/
 
@@ -751,12 +701,11 @@ MPU_pcTimerGetName:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_pcTimerGetName_Unpriv
     MPU_pcTimerGetName_Priv:
-        pop {r0}
         b MPU_pcTimerGetNameImpl
     MPU_pcTimerGetName_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_pcTimerGetName
 /*-----------------------------------------------------------*/
 
@@ -765,12 +714,11 @@ MPU_vTimerSetReloadMode:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTimerSetReloadMode_Unpriv
     MPU_vTimerSetReloadMode_Priv:
-        pop {r0}
         b MPU_vTimerSetReloadModeImpl
     MPU_vTimerSetReloadMode_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTimerSetReloadMode
 /*-----------------------------------------------------------*/
 
@@ -779,12 +727,11 @@ MPU_xTimerGetReloadMode:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerGetReloadMode_Unpriv
     MPU_xTimerGetReloadMode_Priv:
-        pop {r0}
         b MPU_xTimerGetReloadModeImpl
     MPU_xTimerGetReloadMode_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerGetReloadMode
 /*-----------------------------------------------------------*/
 
@@ -793,12 +740,11 @@ MPU_uxTimerGetReloadMode:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTimerGetReloadMode_Unpriv
     MPU_uxTimerGetReloadMode_Priv:
-        pop {r0}
         b MPU_uxTimerGetReloadModeImpl
     MPU_uxTimerGetReloadMode_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTimerGetReloadMode
 /*-----------------------------------------------------------*/
 
@@ -807,12 +753,11 @@ MPU_xTimerGetPeriod:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerGetPeriod_Unpriv
     MPU_xTimerGetPeriod_Priv:
-        pop {r0}
         b MPU_xTimerGetPeriodImpl
     MPU_xTimerGetPeriod_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerGetPeriod
 /*-----------------------------------------------------------*/
 
@@ -821,12 +766,11 @@ MPU_xTimerGetExpiryTime:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerGetExpiryTime_Unpriv
     MPU_xTimerGetExpiryTime_Priv:
-        pop {r0}
         b MPU_xTimerGetExpiryTimeImpl
     MPU_xTimerGetExpiryTime_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerGetExpiryTime
 /*-----------------------------------------------------------*/
 
@@ -835,12 +779,11 @@ MPU_xEventGroupWaitBitsEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xEventGroupWaitBits_Unpriv
     MPU_xEventGroupWaitBits_Priv:
-        pop {r0}
         b MPU_xEventGroupWaitBitsImpl
     MPU_xEventGroupWaitBits_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xEventGroupWaitBits
 /*-----------------------------------------------------------*/
 
@@ -849,12 +792,11 @@ MPU_xEventGroupClearBits:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xEventGroupClearBits_Unpriv
     MPU_xEventGroupClearBits_Priv:
-        pop {r0}
         b MPU_xEventGroupClearBitsImpl
     MPU_xEventGroupClearBits_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xEventGroupClearBits
 /*-----------------------------------------------------------*/
 
@@ -863,12 +805,11 @@ MPU_xEventGroupSetBits:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xEventGroupSetBits_Unpriv
     MPU_xEventGroupSetBits_Priv:
-        pop {r0}
         b MPU_xEventGroupSetBitsImpl
     MPU_xEventGroupSetBits_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xEventGroupSetBits
 /*-----------------------------------------------------------*/
 
@@ -877,12 +818,11 @@ MPU_xEventGroupSync:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xEventGroupSync_Unpriv
     MPU_xEventGroupSync_Priv:
-        pop {r0}
         b MPU_xEventGroupSyncImpl
     MPU_xEventGroupSync_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xEventGroupSync
 /*-----------------------------------------------------------*/
 
@@ -891,12 +831,11 @@ MPU_uxEventGroupGetNumber:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxEventGroupGetNumber_Unpriv
     MPU_uxEventGroupGetNumber_Priv:
-        pop {r0}
         b MPU_uxEventGroupGetNumberImpl
     MPU_uxEventGroupGetNumber_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxEventGroupGetNumber
 /*-----------------------------------------------------------*/
 
@@ -905,12 +844,11 @@ MPU_vEventGroupSetNumber:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vEventGroupSetNumber_Unpriv
     MPU_vEventGroupSetNumber_Priv:
-        pop {r0}
         b MPU_vEventGroupSetNumberImpl
     MPU_vEventGroupSetNumber_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vEventGroupSetNumber
 /*-----------------------------------------------------------*/
 
@@ -919,12 +857,11 @@ MPU_xStreamBufferSend:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferSend_Unpriv
     MPU_xStreamBufferSend_Priv:
-        pop {r0}
         b MPU_xStreamBufferSendImpl
     MPU_xStreamBufferSend_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferSend
 /*-----------------------------------------------------------*/
 
@@ -933,12 +870,11 @@ MPU_xStreamBufferReceive:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferReceive_Unpriv
     MPU_xStreamBufferReceive_Priv:
-        pop {r0}
         b MPU_xStreamBufferReceiveImpl
     MPU_xStreamBufferReceive_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferReceive
 /*-----------------------------------------------------------*/
 
@@ -947,12 +883,11 @@ MPU_xStreamBufferIsFull:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferIsFull_Unpriv
     MPU_xStreamBufferIsFull_Priv:
-        pop {r0}
         b MPU_xStreamBufferIsFullImpl
     MPU_xStreamBufferIsFull_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferIsFull
 /*-----------------------------------------------------------*/
 
@@ -961,12 +896,11 @@ MPU_xStreamBufferIsEmpty:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferIsEmpty_Unpriv
     MPU_xStreamBufferIsEmpty_Priv:
-        pop {r0}
         b MPU_xStreamBufferIsEmptyImpl
     MPU_xStreamBufferIsEmpty_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferIsEmpty
 /*-----------------------------------------------------------*/
 
@@ -975,12 +909,11 @@ MPU_xStreamBufferSpacesAvailable:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferSpacesAvailable_Unpriv
     MPU_xStreamBufferSpacesAvailable_Priv:
-        pop {r0}
         b MPU_xStreamBufferSpacesAvailableImpl
     MPU_xStreamBufferSpacesAvailable_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferSpacesAvailable
 /*-----------------------------------------------------------*/
 
@@ -989,12 +922,11 @@ MPU_xStreamBufferBytesAvailable:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferBytesAvailable_Unpriv
     MPU_xStreamBufferBytesAvailable_Priv:
-        pop {r0}
         b MPU_xStreamBufferBytesAvailableImpl
     MPU_xStreamBufferBytesAvailable_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferBytesAvailable
 /*-----------------------------------------------------------*/
 
@@ -1003,12 +935,11 @@ MPU_xStreamBufferSetTriggerLevel:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferSetTriggerLevel_Unpriv
     MPU_xStreamBufferSetTriggerLevel_Priv:
-        pop {r0}
         b MPU_xStreamBufferSetTriggerLevelImpl
     MPU_xStreamBufferSetTriggerLevel_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel
 /*-----------------------------------------------------------*/
 
@@ -1017,12 +948,11 @@ MPU_xStreamBufferNextMessageLengthBytes:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv
     MPU_xStreamBufferNextMessageLengthBytes_Priv:
-        pop {r0}
         b MPU_xStreamBufferNextMessageLengthBytesImpl
     MPU_xStreamBufferNextMessageLengthBytes_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM55/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM55/non_secure/mpu_wrappers_v2_asm.S
index a69845eda..d2cb78e92 100644
--- a/portable/IAR/ARM_CM55/non_secure/mpu_wrappers_v2_asm.S
+++ b/portable/IAR/ARM_CM55/non_secure/mpu_wrappers_v2_asm.S
@@ -47,12 +47,11 @@ MPU_xTaskDelayUntil:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskDelayUntil_Unpriv
     MPU_xTaskDelayUntil_Priv:
-        pop {r0}
         b MPU_xTaskDelayUntilImpl
     MPU_xTaskDelayUntil_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskDelayUntil
 /*-----------------------------------------------------------*/
 
@@ -61,12 +60,11 @@ MPU_xTaskAbortDelay:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskAbortDelay_Unpriv
     MPU_xTaskAbortDelay_Priv:
-        pop {r0}
         b MPU_xTaskAbortDelayImpl
     MPU_xTaskAbortDelay_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskAbortDelay
 /*-----------------------------------------------------------*/
 
@@ -75,12 +73,11 @@ MPU_vTaskDelay:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskDelay_Unpriv
     MPU_vTaskDelay_Priv:
-        pop {r0}
         b MPU_vTaskDelayImpl
     MPU_vTaskDelay_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskDelay
 /*-----------------------------------------------------------*/
 
@@ -89,12 +86,11 @@ MPU_uxTaskPriorityGet:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTaskPriorityGet_Unpriv
     MPU_uxTaskPriorityGet_Priv:
-        pop {r0}
         b MPU_uxTaskPriorityGetImpl
     MPU_uxTaskPriorityGet_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTaskPriorityGet
 /*-----------------------------------------------------------*/
 
@@ -103,12 +99,11 @@ MPU_eTaskGetState:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_eTaskGetState_Unpriv
     MPU_eTaskGetState_Priv:
-        pop {r0}
         b MPU_eTaskGetStateImpl
     MPU_eTaskGetState_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_eTaskGetState
 /*-----------------------------------------------------------*/
 
@@ -117,12 +112,11 @@ MPU_vTaskGetInfo:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskGetInfo_Unpriv
     MPU_vTaskGetInfo_Priv:
-        pop {r0}
         b MPU_vTaskGetInfoImpl
     MPU_vTaskGetInfo_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskGetInfo
 /*-----------------------------------------------------------*/
 
@@ -131,12 +125,11 @@ MPU_xTaskGetIdleTaskHandle:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGetIdleTaskHandle_Unpriv
     MPU_xTaskGetIdleTaskHandle_Priv:
-        pop {r0}
         b MPU_xTaskGetIdleTaskHandleImpl
     MPU_xTaskGetIdleTaskHandle_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGetIdleTaskHandle
 /*-----------------------------------------------------------*/
 
@@ -145,12 +138,11 @@ MPU_vTaskSuspend:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskSuspend_Unpriv
     MPU_vTaskSuspend_Priv:
-        pop {r0}
         b MPU_vTaskSuspendImpl
     MPU_vTaskSuspend_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskSuspend
 /*-----------------------------------------------------------*/
 
@@ -159,12 +151,11 @@ MPU_vTaskResume:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskResume_Unpriv
     MPU_vTaskResume_Priv:
-        pop {r0}
         b MPU_vTaskResumeImpl
     MPU_vTaskResume_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskResume
 /*-----------------------------------------------------------*/
 
@@ -173,12 +164,11 @@ MPU_xTaskGetTickCount:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGetTickCount_Unpriv
     MPU_xTaskGetTickCount_Priv:
-        pop {r0}
         b MPU_xTaskGetTickCountImpl
     MPU_xTaskGetTickCount_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGetTickCount
 /*-----------------------------------------------------------*/
 
@@ -187,12 +177,11 @@ MPU_uxTaskGetNumberOfTasks:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTaskGetNumberOfTasks_Unpriv
     MPU_uxTaskGetNumberOfTasks_Priv:
-        pop {r0}
         b MPU_uxTaskGetNumberOfTasksImpl
     MPU_uxTaskGetNumberOfTasks_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTaskGetNumberOfTasks
 /*-----------------------------------------------------------*/
 
@@ -201,12 +190,11 @@ MPU_ulTaskGetRunTimeCounter:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGetRunTimeCounter_Unpriv
     MPU_ulTaskGetRunTimeCounter_Priv:
-        pop {r0}
         b MPU_ulTaskGetRunTimeCounterImpl
     MPU_ulTaskGetRunTimeCounter_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGetRunTimeCounter
 /*-----------------------------------------------------------*/
 
@@ -215,12 +203,11 @@ MPU_ulTaskGetRunTimePercent:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGetRunTimePercent_Unpriv
     MPU_ulTaskGetRunTimePercent_Priv:
-        pop {r0}
         b MPU_ulTaskGetRunTimePercentImpl
     MPU_ulTaskGetRunTimePercent_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGetRunTimePercent
 /*-----------------------------------------------------------*/
 
@@ -229,12 +216,11 @@ MPU_ulTaskGetIdleRunTimePercent:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGetIdleRunTimePercent_Unpriv
     MPU_ulTaskGetIdleRunTimePercent_Priv:
-        pop {r0}
         b MPU_ulTaskGetIdleRunTimePercentImpl
     MPU_ulTaskGetIdleRunTimePercent_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent
 /*-----------------------------------------------------------*/
 
@@ -243,12 +229,11 @@ MPU_ulTaskGetIdleRunTimeCounter:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv
     MPU_ulTaskGetIdleRunTimeCounter_Priv:
-        pop {r0}
         b MPU_ulTaskGetIdleRunTimeCounterImpl
     MPU_ulTaskGetIdleRunTimeCounter_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter
 /*-----------------------------------------------------------*/
 
@@ -257,12 +242,11 @@ MPU_vTaskSetApplicationTaskTag:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskSetApplicationTaskTag_Unpriv
     MPU_vTaskSetApplicationTaskTag_Priv:
-        pop {r0}
         b MPU_vTaskSetApplicationTaskTagImpl
     MPU_vTaskSetApplicationTaskTag_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskSetApplicationTaskTag
 /*-----------------------------------------------------------*/
 
@@ -271,12 +255,11 @@ MPU_xTaskGetApplicationTaskTag:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGetApplicationTaskTag_Unpriv
     MPU_xTaskGetApplicationTaskTag_Priv:
-        pop {r0}
         b MPU_xTaskGetApplicationTaskTagImpl
     MPU_xTaskGetApplicationTaskTag_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGetApplicationTaskTag
 /*-----------------------------------------------------------*/
 
@@ -285,12 +268,11 @@ MPU_vTaskSetThreadLocalStoragePointer:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv
     MPU_vTaskSetThreadLocalStoragePointer_Priv:
-        pop {r0}
         b MPU_vTaskSetThreadLocalStoragePointerImpl
     MPU_vTaskSetThreadLocalStoragePointer_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer
 /*-----------------------------------------------------------*/
 
@@ -299,12 +281,11 @@ MPU_pvTaskGetThreadLocalStoragePointer:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv
     MPU_pvTaskGetThreadLocalStoragePointer_Priv:
-        pop {r0}
         b MPU_pvTaskGetThreadLocalStoragePointerImpl
     MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer
 /*-----------------------------------------------------------*/
 
@@ -313,12 +294,11 @@ MPU_uxTaskGetSystemState:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTaskGetSystemState_Unpriv
     MPU_uxTaskGetSystemState_Priv:
-        pop {r0}
         b MPU_uxTaskGetSystemStateImpl
     MPU_uxTaskGetSystemState_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTaskGetSystemState
 /*-----------------------------------------------------------*/
 
@@ -327,12 +307,11 @@ MPU_uxTaskGetStackHighWaterMark:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTaskGetStackHighWaterMark_Unpriv
     MPU_uxTaskGetStackHighWaterMark_Priv:
-        pop {r0}
         b MPU_uxTaskGetStackHighWaterMarkImpl
     MPU_uxTaskGetStackHighWaterMark_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark
 /*-----------------------------------------------------------*/
 
@@ -341,12 +320,11 @@ MPU_uxTaskGetStackHighWaterMark2:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTaskGetStackHighWaterMark2_Unpriv
     MPU_uxTaskGetStackHighWaterMark2_Priv:
-        pop {r0}
         b MPU_uxTaskGetStackHighWaterMark2Impl
     MPU_uxTaskGetStackHighWaterMark2_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2
 /*-----------------------------------------------------------*/
 
@@ -355,12 +333,11 @@ MPU_xTaskGetCurrentTaskHandle:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGetCurrentTaskHandle_Unpriv
     MPU_xTaskGetCurrentTaskHandle_Priv:
-        pop {r0}
         b MPU_xTaskGetCurrentTaskHandleImpl
     MPU_xTaskGetCurrentTaskHandle_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle
 /*-----------------------------------------------------------*/
 
@@ -369,12 +346,11 @@ MPU_xTaskGetSchedulerState:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGetSchedulerState_Unpriv
     MPU_xTaskGetSchedulerState_Priv:
-        pop {r0}
         b MPU_xTaskGetSchedulerStateImpl
     MPU_xTaskGetSchedulerState_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGetSchedulerState
 /*-----------------------------------------------------------*/
 
@@ -383,12 +359,11 @@ MPU_vTaskSetTimeOutState:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskSetTimeOutState_Unpriv
     MPU_vTaskSetTimeOutState_Priv:
-        pop {r0}
         b MPU_vTaskSetTimeOutStateImpl
     MPU_vTaskSetTimeOutState_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskSetTimeOutState
 /*-----------------------------------------------------------*/
 
@@ -397,12 +372,11 @@ MPU_xTaskCheckForTimeOut:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskCheckForTimeOut_Unpriv
     MPU_xTaskCheckForTimeOut_Priv:
-        pop {r0}
         b MPU_xTaskCheckForTimeOutImpl
     MPU_xTaskCheckForTimeOut_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskCheckForTimeOut
 /*-----------------------------------------------------------*/
 
@@ -411,12 +385,11 @@ MPU_xTaskGenericNotifyEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGenericNotify_Unpriv
     MPU_xTaskGenericNotify_Priv:
-        pop {r0}
         b MPU_xTaskGenericNotifyImpl
     MPU_xTaskGenericNotify_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGenericNotify
 /*-----------------------------------------------------------*/
 
@@ -425,12 +398,11 @@ MPU_xTaskGenericNotifyWaitEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGenericNotifyWait_Unpriv
     MPU_xTaskGenericNotifyWait_Priv:
-        pop {r0}
         b MPU_xTaskGenericNotifyWaitImpl
     MPU_xTaskGenericNotifyWait_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGenericNotifyWait
 /*-----------------------------------------------------------*/
 
@@ -439,12 +411,11 @@ MPU_ulTaskGenericNotifyTake:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGenericNotifyTake_Unpriv
     MPU_ulTaskGenericNotifyTake_Priv:
-        pop {r0}
         b MPU_ulTaskGenericNotifyTakeImpl
     MPU_ulTaskGenericNotifyTake_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGenericNotifyTake
 /*-----------------------------------------------------------*/
 
@@ -453,12 +424,11 @@ MPU_xTaskGenericNotifyStateClear:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGenericNotifyStateClear_Unpriv
     MPU_xTaskGenericNotifyStateClear_Priv:
-        pop {r0}
         b MPU_xTaskGenericNotifyStateClearImpl
     MPU_xTaskGenericNotifyStateClear_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGenericNotifyStateClear
 /*-----------------------------------------------------------*/
 
@@ -467,12 +437,11 @@ MPU_ulTaskGenericNotifyValueClear:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGenericNotifyValueClear_Unpriv
     MPU_ulTaskGenericNotifyValueClear_Priv:
-        pop {r0}
         b MPU_ulTaskGenericNotifyValueClearImpl
     MPU_ulTaskGenericNotifyValueClear_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear
 /*-----------------------------------------------------------*/
 
@@ -481,12 +450,11 @@ MPU_xQueueGenericSend:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueGenericSend_Unpriv
     MPU_xQueueGenericSend_Priv:
-        pop {r0}
         b MPU_xQueueGenericSendImpl
     MPU_xQueueGenericSend_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueGenericSend
 /*-----------------------------------------------------------*/
 
@@ -495,12 +463,11 @@ MPU_uxQueueMessagesWaiting:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxQueueMessagesWaiting_Unpriv
     MPU_uxQueueMessagesWaiting_Priv:
-        pop {r0}
         b MPU_uxQueueMessagesWaitingImpl
     MPU_uxQueueMessagesWaiting_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxQueueMessagesWaiting
 /*-----------------------------------------------------------*/
 
@@ -509,12 +476,11 @@ MPU_uxQueueSpacesAvailable:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxQueueSpacesAvailable_Unpriv
     MPU_uxQueueSpacesAvailable_Priv:
-        pop {r0}
         b MPU_uxQueueSpacesAvailableImpl
     MPU_uxQueueSpacesAvailable_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxQueueSpacesAvailable
 /*-----------------------------------------------------------*/
 
@@ -523,12 +489,11 @@ MPU_xQueueReceive:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueReceive_Unpriv
     MPU_xQueueReceive_Priv:
-        pop {r0}
         b MPU_xQueueReceiveImpl
     MPU_xQueueReceive_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueReceive
 /*-----------------------------------------------------------*/
 
@@ -537,12 +502,11 @@ MPU_xQueuePeek:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueuePeek_Unpriv
     MPU_xQueuePeek_Priv:
-        pop {r0}
         b MPU_xQueuePeekImpl
     MPU_xQueuePeek_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueuePeek
 /*-----------------------------------------------------------*/
 
@@ -551,12 +515,11 @@ MPU_xQueueSemaphoreTake:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueSemaphoreTake_Unpriv
     MPU_xQueueSemaphoreTake_Priv:
-        pop {r0}
         b MPU_xQueueSemaphoreTakeImpl
     MPU_xQueueSemaphoreTake_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueSemaphoreTake
 /*-----------------------------------------------------------*/
 
@@ -565,12 +528,11 @@ MPU_xQueueGetMutexHolder:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueGetMutexHolder_Unpriv
     MPU_xQueueGetMutexHolder_Priv:
-        pop {r0}
         b MPU_xQueueGetMutexHolderImpl
     MPU_xQueueGetMutexHolder_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueGetMutexHolder
 /*-----------------------------------------------------------*/
 
@@ -579,12 +541,11 @@ MPU_xQueueTakeMutexRecursive:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueTakeMutexRecursive_Unpriv
     MPU_xQueueTakeMutexRecursive_Priv:
-        pop {r0}
         b MPU_xQueueTakeMutexRecursiveImpl
     MPU_xQueueTakeMutexRecursive_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueTakeMutexRecursive
 /*-----------------------------------------------------------*/
 
@@ -593,12 +554,11 @@ MPU_xQueueGiveMutexRecursive:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueGiveMutexRecursive_Unpriv
     MPU_xQueueGiveMutexRecursive_Priv:
-        pop {r0}
         b MPU_xQueueGiveMutexRecursiveImpl
     MPU_xQueueGiveMutexRecursive_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueGiveMutexRecursive
 /*-----------------------------------------------------------*/
 
@@ -607,12 +567,11 @@ MPU_xQueueSelectFromSet:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueSelectFromSet_Unpriv
     MPU_xQueueSelectFromSet_Priv:
-        pop {r0}
         b MPU_xQueueSelectFromSetImpl
     MPU_xQueueSelectFromSet_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueSelectFromSet
 /*-----------------------------------------------------------*/
 
@@ -621,12 +580,11 @@ MPU_xQueueAddToSet:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueAddToSet_Unpriv
     MPU_xQueueAddToSet_Priv:
-        pop {r0}
         b MPU_xQueueAddToSetImpl
     MPU_xQueueAddToSet_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueAddToSet
 /*-----------------------------------------------------------*/
 
@@ -635,12 +593,11 @@ MPU_vQueueAddToRegistry:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vQueueAddToRegistry_Unpriv
     MPU_vQueueAddToRegistry_Priv:
-        pop {r0}
         b MPU_vQueueAddToRegistryImpl
     MPU_vQueueAddToRegistry_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vQueueAddToRegistry
 /*-----------------------------------------------------------*/
 
@@ -649,12 +606,11 @@ MPU_vQueueUnregisterQueue:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vQueueUnregisterQueue_Unpriv
     MPU_vQueueUnregisterQueue_Priv:
-        pop {r0}
         b MPU_vQueueUnregisterQueueImpl
     MPU_vQueueUnregisterQueue_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vQueueUnregisterQueue
 /*-----------------------------------------------------------*/
 
@@ -663,12 +619,11 @@ MPU_pcQueueGetName:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_pcQueueGetName_Unpriv
     MPU_pcQueueGetName_Priv:
-        pop {r0}
         b MPU_pcQueueGetNameImpl
     MPU_pcQueueGetName_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_pcQueueGetName
 /*-----------------------------------------------------------*/
 
@@ -677,12 +632,11 @@ MPU_pvTimerGetTimerID:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_pvTimerGetTimerID_Unpriv
     MPU_pvTimerGetTimerID_Priv:
-        pop {r0}
         b MPU_pvTimerGetTimerIDImpl
     MPU_pvTimerGetTimerID_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_pvTimerGetTimerID
 /*-----------------------------------------------------------*/
 
@@ -691,12 +645,11 @@ MPU_vTimerSetTimerID:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTimerSetTimerID_Unpriv
     MPU_vTimerSetTimerID_Priv:
-        pop {r0}
         b MPU_vTimerSetTimerIDImpl
     MPU_vTimerSetTimerID_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTimerSetTimerID
 /*-----------------------------------------------------------*/
 
@@ -705,12 +658,11 @@ MPU_xTimerIsTimerActive:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerIsTimerActive_Unpriv
     MPU_xTimerIsTimerActive_Priv:
-        pop {r0}
         b MPU_xTimerIsTimerActiveImpl
     MPU_xTimerIsTimerActive_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerIsTimerActive
 /*-----------------------------------------------------------*/
 
@@ -719,12 +671,11 @@ MPU_xTimerGetTimerDaemonTaskHandle:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv
     MPU_xTimerGetTimerDaemonTaskHandle_Priv:
-        pop {r0}
         b MPU_xTimerGetTimerDaemonTaskHandleImpl
     MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle
 /*-----------------------------------------------------------*/
 
@@ -733,12 +684,11 @@ MPU_xTimerGenericCommandFromTaskEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerGenericCommandFromTask_Unpriv
     MPU_xTimerGenericCommandFromTask_Priv:
-        pop {r0}
         b MPU_xTimerGenericCommandFromTaskImpl
     MPU_xTimerGenericCommandFromTask_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerGenericCommandFromTask
 /*-----------------------------------------------------------*/
 
@@ -747,12 +697,11 @@ MPU_pcTimerGetName:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_pcTimerGetName_Unpriv
     MPU_pcTimerGetName_Priv:
-        pop {r0}
         b MPU_pcTimerGetNameImpl
     MPU_pcTimerGetName_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_pcTimerGetName
 /*-----------------------------------------------------------*/
 
@@ -761,12 +710,11 @@ MPU_vTimerSetReloadMode:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTimerSetReloadMode_Unpriv
     MPU_vTimerSetReloadMode_Priv:
-        pop {r0}
         b MPU_vTimerSetReloadModeImpl
     MPU_vTimerSetReloadMode_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTimerSetReloadMode
 /*-----------------------------------------------------------*/
 
@@ -775,12 +723,11 @@ MPU_xTimerGetReloadMode:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerGetReloadMode_Unpriv
     MPU_xTimerGetReloadMode_Priv:
-        pop {r0}
         b MPU_xTimerGetReloadModeImpl
     MPU_xTimerGetReloadMode_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerGetReloadMode
 /*-----------------------------------------------------------*/
 
@@ -789,12 +736,11 @@ MPU_uxTimerGetReloadMode:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTimerGetReloadMode_Unpriv
     MPU_uxTimerGetReloadMode_Priv:
-        pop {r0}
         b MPU_uxTimerGetReloadModeImpl
     MPU_uxTimerGetReloadMode_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTimerGetReloadMode
 /*-----------------------------------------------------------*/
 
@@ -803,12 +749,11 @@ MPU_xTimerGetPeriod:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerGetPeriod_Unpriv
     MPU_xTimerGetPeriod_Priv:
-        pop {r0}
         b MPU_xTimerGetPeriodImpl
     MPU_xTimerGetPeriod_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerGetPeriod
 /*-----------------------------------------------------------*/
 
@@ -817,12 +762,11 @@ MPU_xTimerGetExpiryTime:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerGetExpiryTime_Unpriv
     MPU_xTimerGetExpiryTime_Priv:
-        pop {r0}
         b MPU_xTimerGetExpiryTimeImpl
     MPU_xTimerGetExpiryTime_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerGetExpiryTime
 /*-----------------------------------------------------------*/
 
@@ -831,12 +775,11 @@ MPU_xEventGroupWaitBitsEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xEventGroupWaitBits_Unpriv
     MPU_xEventGroupWaitBits_Priv:
-        pop {r0}
         b MPU_xEventGroupWaitBitsImpl
     MPU_xEventGroupWaitBits_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xEventGroupWaitBits
 /*-----------------------------------------------------------*/
 
@@ -845,12 +788,11 @@ MPU_xEventGroupClearBits:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xEventGroupClearBits_Unpriv
     MPU_xEventGroupClearBits_Priv:
-        pop {r0}
         b MPU_xEventGroupClearBitsImpl
     MPU_xEventGroupClearBits_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xEventGroupClearBits
 /*-----------------------------------------------------------*/
 
@@ -859,12 +801,11 @@ MPU_xEventGroupSetBits:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xEventGroupSetBits_Unpriv
     MPU_xEventGroupSetBits_Priv:
-        pop {r0}
         b MPU_xEventGroupSetBitsImpl
     MPU_xEventGroupSetBits_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xEventGroupSetBits
 /*-----------------------------------------------------------*/
 
@@ -873,12 +814,11 @@ MPU_xEventGroupSync:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xEventGroupSync_Unpriv
     MPU_xEventGroupSync_Priv:
-        pop {r0}
         b MPU_xEventGroupSyncImpl
     MPU_xEventGroupSync_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xEventGroupSync
 /*-----------------------------------------------------------*/
 
@@ -887,12 +827,11 @@ MPU_uxEventGroupGetNumber:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxEventGroupGetNumber_Unpriv
     MPU_uxEventGroupGetNumber_Priv:
-        pop {r0}
         b MPU_uxEventGroupGetNumberImpl
     MPU_uxEventGroupGetNumber_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxEventGroupGetNumber
 /*-----------------------------------------------------------*/
 
@@ -901,12 +840,11 @@ MPU_vEventGroupSetNumber:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vEventGroupSetNumber_Unpriv
     MPU_vEventGroupSetNumber_Priv:
-        pop {r0}
         b MPU_vEventGroupSetNumberImpl
     MPU_vEventGroupSetNumber_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vEventGroupSetNumber
 /*-----------------------------------------------------------*/
 
@@ -915,12 +853,11 @@ MPU_xStreamBufferSend:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferSend_Unpriv
     MPU_xStreamBufferSend_Priv:
-        pop {r0}
         b MPU_xStreamBufferSendImpl
     MPU_xStreamBufferSend_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferSend
 /*-----------------------------------------------------------*/
 
@@ -929,12 +866,11 @@ MPU_xStreamBufferReceive:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferReceive_Unpriv
     MPU_xStreamBufferReceive_Priv:
-        pop {r0}
         b MPU_xStreamBufferReceiveImpl
     MPU_xStreamBufferReceive_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferReceive
 /*-----------------------------------------------------------*/
 
@@ -943,12 +879,11 @@ MPU_xStreamBufferIsFull:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferIsFull_Unpriv
     MPU_xStreamBufferIsFull_Priv:
-        pop {r0}
         b MPU_xStreamBufferIsFullImpl
     MPU_xStreamBufferIsFull_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferIsFull
 /*-----------------------------------------------------------*/
 
@@ -957,12 +892,11 @@ MPU_xStreamBufferIsEmpty:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferIsEmpty_Unpriv
     MPU_xStreamBufferIsEmpty_Priv:
-        pop {r0}
         b MPU_xStreamBufferIsEmptyImpl
     MPU_xStreamBufferIsEmpty_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferIsEmpty
 /*-----------------------------------------------------------*/
 
@@ -971,12 +905,11 @@ MPU_xStreamBufferSpacesAvailable:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferSpacesAvailable_Unpriv
     MPU_xStreamBufferSpacesAvailable_Priv:
-        pop {r0}
         b MPU_xStreamBufferSpacesAvailableImpl
     MPU_xStreamBufferSpacesAvailable_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferSpacesAvailable
 /*-----------------------------------------------------------*/
 
@@ -985,12 +918,11 @@ MPU_xStreamBufferBytesAvailable:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferBytesAvailable_Unpriv
     MPU_xStreamBufferBytesAvailable_Priv:
-        pop {r0}
         b MPU_xStreamBufferBytesAvailableImpl
     MPU_xStreamBufferBytesAvailable_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferBytesAvailable
 /*-----------------------------------------------------------*/
 
@@ -999,12 +931,11 @@ MPU_xStreamBufferSetTriggerLevel:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferSetTriggerLevel_Unpriv
     MPU_xStreamBufferSetTriggerLevel_Priv:
-        pop {r0}
         b MPU_xStreamBufferSetTriggerLevelImpl
     MPU_xStreamBufferSetTriggerLevel_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel
 /*-----------------------------------------------------------*/
 
@@ -1013,12 +944,11 @@ MPU_xStreamBufferNextMessageLengthBytes:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv
     MPU_xStreamBufferNextMessageLengthBytes_Priv:
-        pop {r0}
         b MPU_xStreamBufferNextMessageLengthBytesImpl
     MPU_xStreamBufferNextMessageLengthBytes_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.S
index a69845eda..d2cb78e92 100644
--- a/portable/IAR/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.S
+++ b/portable/IAR/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.S
@@ -47,12 +47,11 @@ MPU_xTaskDelayUntil:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskDelayUntil_Unpriv
     MPU_xTaskDelayUntil_Priv:
-        pop {r0}
         b MPU_xTaskDelayUntilImpl
     MPU_xTaskDelayUntil_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskDelayUntil
 /*-----------------------------------------------------------*/
 
@@ -61,12 +60,11 @@ MPU_xTaskAbortDelay:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskAbortDelay_Unpriv
     MPU_xTaskAbortDelay_Priv:
-        pop {r0}
         b MPU_xTaskAbortDelayImpl
     MPU_xTaskAbortDelay_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskAbortDelay
 /*-----------------------------------------------------------*/
 
@@ -75,12 +73,11 @@ MPU_vTaskDelay:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskDelay_Unpriv
     MPU_vTaskDelay_Priv:
-        pop {r0}
         b MPU_vTaskDelayImpl
     MPU_vTaskDelay_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskDelay
 /*-----------------------------------------------------------*/
 
@@ -89,12 +86,11 @@ MPU_uxTaskPriorityGet:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTaskPriorityGet_Unpriv
     MPU_uxTaskPriorityGet_Priv:
-        pop {r0}
         b MPU_uxTaskPriorityGetImpl
     MPU_uxTaskPriorityGet_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTaskPriorityGet
 /*-----------------------------------------------------------*/
 
@@ -103,12 +99,11 @@ MPU_eTaskGetState:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_eTaskGetState_Unpriv
     MPU_eTaskGetState_Priv:
-        pop {r0}
         b MPU_eTaskGetStateImpl
     MPU_eTaskGetState_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_eTaskGetState
 /*-----------------------------------------------------------*/
 
@@ -117,12 +112,11 @@ MPU_vTaskGetInfo:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskGetInfo_Unpriv
     MPU_vTaskGetInfo_Priv:
-        pop {r0}
         b MPU_vTaskGetInfoImpl
     MPU_vTaskGetInfo_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskGetInfo
 /*-----------------------------------------------------------*/
 
@@ -131,12 +125,11 @@ MPU_xTaskGetIdleTaskHandle:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGetIdleTaskHandle_Unpriv
     MPU_xTaskGetIdleTaskHandle_Priv:
-        pop {r0}
         b MPU_xTaskGetIdleTaskHandleImpl
     MPU_xTaskGetIdleTaskHandle_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGetIdleTaskHandle
 /*-----------------------------------------------------------*/
 
@@ -145,12 +138,11 @@ MPU_vTaskSuspend:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskSuspend_Unpriv
     MPU_vTaskSuspend_Priv:
-        pop {r0}
         b MPU_vTaskSuspendImpl
     MPU_vTaskSuspend_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskSuspend
 /*-----------------------------------------------------------*/
 
@@ -159,12 +151,11 @@ MPU_vTaskResume:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskResume_Unpriv
     MPU_vTaskResume_Priv:
-        pop {r0}
         b MPU_vTaskResumeImpl
     MPU_vTaskResume_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskResume
 /*-----------------------------------------------------------*/
 
@@ -173,12 +164,11 @@ MPU_xTaskGetTickCount:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGetTickCount_Unpriv
     MPU_xTaskGetTickCount_Priv:
-        pop {r0}
         b MPU_xTaskGetTickCountImpl
     MPU_xTaskGetTickCount_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGetTickCount
 /*-----------------------------------------------------------*/
 
@@ -187,12 +177,11 @@ MPU_uxTaskGetNumberOfTasks:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTaskGetNumberOfTasks_Unpriv
     MPU_uxTaskGetNumberOfTasks_Priv:
-        pop {r0}
         b MPU_uxTaskGetNumberOfTasksImpl
     MPU_uxTaskGetNumberOfTasks_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTaskGetNumberOfTasks
 /*-----------------------------------------------------------*/
 
@@ -201,12 +190,11 @@ MPU_ulTaskGetRunTimeCounter:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGetRunTimeCounter_Unpriv
     MPU_ulTaskGetRunTimeCounter_Priv:
-        pop {r0}
         b MPU_ulTaskGetRunTimeCounterImpl
     MPU_ulTaskGetRunTimeCounter_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGetRunTimeCounter
 /*-----------------------------------------------------------*/
 
@@ -215,12 +203,11 @@ MPU_ulTaskGetRunTimePercent:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGetRunTimePercent_Unpriv
     MPU_ulTaskGetRunTimePercent_Priv:
-        pop {r0}
         b MPU_ulTaskGetRunTimePercentImpl
     MPU_ulTaskGetRunTimePercent_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGetRunTimePercent
 /*-----------------------------------------------------------*/
 
@@ -229,12 +216,11 @@ MPU_ulTaskGetIdleRunTimePercent:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGetIdleRunTimePercent_Unpriv
     MPU_ulTaskGetIdleRunTimePercent_Priv:
-        pop {r0}
         b MPU_ulTaskGetIdleRunTimePercentImpl
     MPU_ulTaskGetIdleRunTimePercent_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent
 /*-----------------------------------------------------------*/
 
@@ -243,12 +229,11 @@ MPU_ulTaskGetIdleRunTimeCounter:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv
     MPU_ulTaskGetIdleRunTimeCounter_Priv:
-        pop {r0}
         b MPU_ulTaskGetIdleRunTimeCounterImpl
     MPU_ulTaskGetIdleRunTimeCounter_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter
 /*-----------------------------------------------------------*/
 
@@ -257,12 +242,11 @@ MPU_vTaskSetApplicationTaskTag:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskSetApplicationTaskTag_Unpriv
     MPU_vTaskSetApplicationTaskTag_Priv:
-        pop {r0}
         b MPU_vTaskSetApplicationTaskTagImpl
     MPU_vTaskSetApplicationTaskTag_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskSetApplicationTaskTag
 /*-----------------------------------------------------------*/
 
@@ -271,12 +255,11 @@ MPU_xTaskGetApplicationTaskTag:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGetApplicationTaskTag_Unpriv
     MPU_xTaskGetApplicationTaskTag_Priv:
-        pop {r0}
         b MPU_xTaskGetApplicationTaskTagImpl
     MPU_xTaskGetApplicationTaskTag_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGetApplicationTaskTag
 /*-----------------------------------------------------------*/
 
@@ -285,12 +268,11 @@ MPU_vTaskSetThreadLocalStoragePointer:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv
     MPU_vTaskSetThreadLocalStoragePointer_Priv:
-        pop {r0}
         b MPU_vTaskSetThreadLocalStoragePointerImpl
     MPU_vTaskSetThreadLocalStoragePointer_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer
 /*-----------------------------------------------------------*/
 
@@ -299,12 +281,11 @@ MPU_pvTaskGetThreadLocalStoragePointer:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv
     MPU_pvTaskGetThreadLocalStoragePointer_Priv:
-        pop {r0}
         b MPU_pvTaskGetThreadLocalStoragePointerImpl
     MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer
 /*-----------------------------------------------------------*/
 
@@ -313,12 +294,11 @@ MPU_uxTaskGetSystemState:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTaskGetSystemState_Unpriv
     MPU_uxTaskGetSystemState_Priv:
-        pop {r0}
         b MPU_uxTaskGetSystemStateImpl
     MPU_uxTaskGetSystemState_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTaskGetSystemState
 /*-----------------------------------------------------------*/
 
@@ -327,12 +307,11 @@ MPU_uxTaskGetStackHighWaterMark:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTaskGetStackHighWaterMark_Unpriv
     MPU_uxTaskGetStackHighWaterMark_Priv:
-        pop {r0}
         b MPU_uxTaskGetStackHighWaterMarkImpl
     MPU_uxTaskGetStackHighWaterMark_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark
 /*-----------------------------------------------------------*/
 
@@ -341,12 +320,11 @@ MPU_uxTaskGetStackHighWaterMark2:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTaskGetStackHighWaterMark2_Unpriv
     MPU_uxTaskGetStackHighWaterMark2_Priv:
-        pop {r0}
         b MPU_uxTaskGetStackHighWaterMark2Impl
     MPU_uxTaskGetStackHighWaterMark2_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2
 /*-----------------------------------------------------------*/
 
@@ -355,12 +333,11 @@ MPU_xTaskGetCurrentTaskHandle:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGetCurrentTaskHandle_Unpriv
     MPU_xTaskGetCurrentTaskHandle_Priv:
-        pop {r0}
         b MPU_xTaskGetCurrentTaskHandleImpl
     MPU_xTaskGetCurrentTaskHandle_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle
 /*-----------------------------------------------------------*/
 
@@ -369,12 +346,11 @@ MPU_xTaskGetSchedulerState:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGetSchedulerState_Unpriv
     MPU_xTaskGetSchedulerState_Priv:
-        pop {r0}
         b MPU_xTaskGetSchedulerStateImpl
     MPU_xTaskGetSchedulerState_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGetSchedulerState
 /*-----------------------------------------------------------*/
 
@@ -383,12 +359,11 @@ MPU_vTaskSetTimeOutState:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskSetTimeOutState_Unpriv
     MPU_vTaskSetTimeOutState_Priv:
-        pop {r0}
         b MPU_vTaskSetTimeOutStateImpl
     MPU_vTaskSetTimeOutState_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskSetTimeOutState
 /*-----------------------------------------------------------*/
 
@@ -397,12 +372,11 @@ MPU_xTaskCheckForTimeOut:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskCheckForTimeOut_Unpriv
     MPU_xTaskCheckForTimeOut_Priv:
-        pop {r0}
         b MPU_xTaskCheckForTimeOutImpl
     MPU_xTaskCheckForTimeOut_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskCheckForTimeOut
 /*-----------------------------------------------------------*/
 
@@ -411,12 +385,11 @@ MPU_xTaskGenericNotifyEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGenericNotify_Unpriv
     MPU_xTaskGenericNotify_Priv:
-        pop {r0}
         b MPU_xTaskGenericNotifyImpl
     MPU_xTaskGenericNotify_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGenericNotify
 /*-----------------------------------------------------------*/
 
@@ -425,12 +398,11 @@ MPU_xTaskGenericNotifyWaitEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGenericNotifyWait_Unpriv
     MPU_xTaskGenericNotifyWait_Priv:
-        pop {r0}
         b MPU_xTaskGenericNotifyWaitImpl
     MPU_xTaskGenericNotifyWait_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGenericNotifyWait
 /*-----------------------------------------------------------*/
 
@@ -439,12 +411,11 @@ MPU_ulTaskGenericNotifyTake:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGenericNotifyTake_Unpriv
     MPU_ulTaskGenericNotifyTake_Priv:
-        pop {r0}
         b MPU_ulTaskGenericNotifyTakeImpl
     MPU_ulTaskGenericNotifyTake_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGenericNotifyTake
 /*-----------------------------------------------------------*/
 
@@ -453,12 +424,11 @@ MPU_xTaskGenericNotifyStateClear:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGenericNotifyStateClear_Unpriv
     MPU_xTaskGenericNotifyStateClear_Priv:
-        pop {r0}
         b MPU_xTaskGenericNotifyStateClearImpl
     MPU_xTaskGenericNotifyStateClear_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGenericNotifyStateClear
 /*-----------------------------------------------------------*/
 
@@ -467,12 +437,11 @@ MPU_ulTaskGenericNotifyValueClear:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGenericNotifyValueClear_Unpriv
     MPU_ulTaskGenericNotifyValueClear_Priv:
-        pop {r0}
         b MPU_ulTaskGenericNotifyValueClearImpl
     MPU_ulTaskGenericNotifyValueClear_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear
 /*-----------------------------------------------------------*/
 
@@ -481,12 +450,11 @@ MPU_xQueueGenericSend:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueGenericSend_Unpriv
     MPU_xQueueGenericSend_Priv:
-        pop {r0}
         b MPU_xQueueGenericSendImpl
     MPU_xQueueGenericSend_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueGenericSend
 /*-----------------------------------------------------------*/
 
@@ -495,12 +463,11 @@ MPU_uxQueueMessagesWaiting:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxQueueMessagesWaiting_Unpriv
     MPU_uxQueueMessagesWaiting_Priv:
-        pop {r0}
         b MPU_uxQueueMessagesWaitingImpl
     MPU_uxQueueMessagesWaiting_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxQueueMessagesWaiting
 /*-----------------------------------------------------------*/
 
@@ -509,12 +476,11 @@ MPU_uxQueueSpacesAvailable:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxQueueSpacesAvailable_Unpriv
     MPU_uxQueueSpacesAvailable_Priv:
-        pop {r0}
         b MPU_uxQueueSpacesAvailableImpl
     MPU_uxQueueSpacesAvailable_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxQueueSpacesAvailable
 /*-----------------------------------------------------------*/
 
@@ -523,12 +489,11 @@ MPU_xQueueReceive:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueReceive_Unpriv
     MPU_xQueueReceive_Priv:
-        pop {r0}
         b MPU_xQueueReceiveImpl
     MPU_xQueueReceive_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueReceive
 /*-----------------------------------------------------------*/
 
@@ -537,12 +502,11 @@ MPU_xQueuePeek:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueuePeek_Unpriv
     MPU_xQueuePeek_Priv:
-        pop {r0}
         b MPU_xQueuePeekImpl
     MPU_xQueuePeek_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueuePeek
 /*-----------------------------------------------------------*/
 
@@ -551,12 +515,11 @@ MPU_xQueueSemaphoreTake:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueSemaphoreTake_Unpriv
     MPU_xQueueSemaphoreTake_Priv:
-        pop {r0}
         b MPU_xQueueSemaphoreTakeImpl
     MPU_xQueueSemaphoreTake_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueSemaphoreTake
 /*-----------------------------------------------------------*/
 
@@ -565,12 +528,11 @@ MPU_xQueueGetMutexHolder:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueGetMutexHolder_Unpriv
     MPU_xQueueGetMutexHolder_Priv:
-        pop {r0}
         b MPU_xQueueGetMutexHolderImpl
     MPU_xQueueGetMutexHolder_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueGetMutexHolder
 /*-----------------------------------------------------------*/
 
@@ -579,12 +541,11 @@ MPU_xQueueTakeMutexRecursive:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueTakeMutexRecursive_Unpriv
     MPU_xQueueTakeMutexRecursive_Priv:
-        pop {r0}
         b MPU_xQueueTakeMutexRecursiveImpl
     MPU_xQueueTakeMutexRecursive_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueTakeMutexRecursive
 /*-----------------------------------------------------------*/
 
@@ -593,12 +554,11 @@ MPU_xQueueGiveMutexRecursive:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueGiveMutexRecursive_Unpriv
     MPU_xQueueGiveMutexRecursive_Priv:
-        pop {r0}
         b MPU_xQueueGiveMutexRecursiveImpl
     MPU_xQueueGiveMutexRecursive_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueGiveMutexRecursive
 /*-----------------------------------------------------------*/
 
@@ -607,12 +567,11 @@ MPU_xQueueSelectFromSet:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueSelectFromSet_Unpriv
     MPU_xQueueSelectFromSet_Priv:
-        pop {r0}
         b MPU_xQueueSelectFromSetImpl
     MPU_xQueueSelectFromSet_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueSelectFromSet
 /*-----------------------------------------------------------*/
 
@@ -621,12 +580,11 @@ MPU_xQueueAddToSet:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueAddToSet_Unpriv
     MPU_xQueueAddToSet_Priv:
-        pop {r0}
         b MPU_xQueueAddToSetImpl
     MPU_xQueueAddToSet_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueAddToSet
 /*-----------------------------------------------------------*/
 
@@ -635,12 +593,11 @@ MPU_vQueueAddToRegistry:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vQueueAddToRegistry_Unpriv
     MPU_vQueueAddToRegistry_Priv:
-        pop {r0}
         b MPU_vQueueAddToRegistryImpl
     MPU_vQueueAddToRegistry_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vQueueAddToRegistry
 /*-----------------------------------------------------------*/
 
@@ -649,12 +606,11 @@ MPU_vQueueUnregisterQueue:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vQueueUnregisterQueue_Unpriv
     MPU_vQueueUnregisterQueue_Priv:
-        pop {r0}
         b MPU_vQueueUnregisterQueueImpl
     MPU_vQueueUnregisterQueue_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vQueueUnregisterQueue
 /*-----------------------------------------------------------*/
 
@@ -663,12 +619,11 @@ MPU_pcQueueGetName:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_pcQueueGetName_Unpriv
     MPU_pcQueueGetName_Priv:
-        pop {r0}
         b MPU_pcQueueGetNameImpl
     MPU_pcQueueGetName_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_pcQueueGetName
 /*-----------------------------------------------------------*/
 
@@ -677,12 +632,11 @@ MPU_pvTimerGetTimerID:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_pvTimerGetTimerID_Unpriv
     MPU_pvTimerGetTimerID_Priv:
-        pop {r0}
         b MPU_pvTimerGetTimerIDImpl
     MPU_pvTimerGetTimerID_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_pvTimerGetTimerID
 /*-----------------------------------------------------------*/
 
@@ -691,12 +645,11 @@ MPU_vTimerSetTimerID:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTimerSetTimerID_Unpriv
     MPU_vTimerSetTimerID_Priv:
-        pop {r0}
         b MPU_vTimerSetTimerIDImpl
     MPU_vTimerSetTimerID_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTimerSetTimerID
 /*-----------------------------------------------------------*/
 
@@ -705,12 +658,11 @@ MPU_xTimerIsTimerActive:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerIsTimerActive_Unpriv
     MPU_xTimerIsTimerActive_Priv:
-        pop {r0}
         b MPU_xTimerIsTimerActiveImpl
     MPU_xTimerIsTimerActive_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerIsTimerActive
 /*-----------------------------------------------------------*/
 
@@ -719,12 +671,11 @@ MPU_xTimerGetTimerDaemonTaskHandle:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv
     MPU_xTimerGetTimerDaemonTaskHandle_Priv:
-        pop {r0}
         b MPU_xTimerGetTimerDaemonTaskHandleImpl
     MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle
 /*-----------------------------------------------------------*/
 
@@ -733,12 +684,11 @@ MPU_xTimerGenericCommandFromTaskEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerGenericCommandFromTask_Unpriv
     MPU_xTimerGenericCommandFromTask_Priv:
-        pop {r0}
         b MPU_xTimerGenericCommandFromTaskImpl
     MPU_xTimerGenericCommandFromTask_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerGenericCommandFromTask
 /*-----------------------------------------------------------*/
 
@@ -747,12 +697,11 @@ MPU_pcTimerGetName:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_pcTimerGetName_Unpriv
     MPU_pcTimerGetName_Priv:
-        pop {r0}
         b MPU_pcTimerGetNameImpl
     MPU_pcTimerGetName_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_pcTimerGetName
 /*-----------------------------------------------------------*/
 
@@ -761,12 +710,11 @@ MPU_vTimerSetReloadMode:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTimerSetReloadMode_Unpriv
     MPU_vTimerSetReloadMode_Priv:
-        pop {r0}
         b MPU_vTimerSetReloadModeImpl
     MPU_vTimerSetReloadMode_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTimerSetReloadMode
 /*-----------------------------------------------------------*/
 
@@ -775,12 +723,11 @@ MPU_xTimerGetReloadMode:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerGetReloadMode_Unpriv
     MPU_xTimerGetReloadMode_Priv:
-        pop {r0}
         b MPU_xTimerGetReloadModeImpl
     MPU_xTimerGetReloadMode_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerGetReloadMode
 /*-----------------------------------------------------------*/
 
@@ -789,12 +736,11 @@ MPU_uxTimerGetReloadMode:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTimerGetReloadMode_Unpriv
     MPU_uxTimerGetReloadMode_Priv:
-        pop {r0}
         b MPU_uxTimerGetReloadModeImpl
     MPU_uxTimerGetReloadMode_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTimerGetReloadMode
 /*-----------------------------------------------------------*/
 
@@ -803,12 +749,11 @@ MPU_xTimerGetPeriod:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerGetPeriod_Unpriv
     MPU_xTimerGetPeriod_Priv:
-        pop {r0}
         b MPU_xTimerGetPeriodImpl
     MPU_xTimerGetPeriod_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerGetPeriod
 /*-----------------------------------------------------------*/
 
@@ -817,12 +762,11 @@ MPU_xTimerGetExpiryTime:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerGetExpiryTime_Unpriv
     MPU_xTimerGetExpiryTime_Priv:
-        pop {r0}
         b MPU_xTimerGetExpiryTimeImpl
     MPU_xTimerGetExpiryTime_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerGetExpiryTime
 /*-----------------------------------------------------------*/
 
@@ -831,12 +775,11 @@ MPU_xEventGroupWaitBitsEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xEventGroupWaitBits_Unpriv
     MPU_xEventGroupWaitBits_Priv:
-        pop {r0}
         b MPU_xEventGroupWaitBitsImpl
     MPU_xEventGroupWaitBits_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xEventGroupWaitBits
 /*-----------------------------------------------------------*/
 
@@ -845,12 +788,11 @@ MPU_xEventGroupClearBits:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xEventGroupClearBits_Unpriv
     MPU_xEventGroupClearBits_Priv:
-        pop {r0}
         b MPU_xEventGroupClearBitsImpl
     MPU_xEventGroupClearBits_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xEventGroupClearBits
 /*-----------------------------------------------------------*/
 
@@ -859,12 +801,11 @@ MPU_xEventGroupSetBits:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xEventGroupSetBits_Unpriv
     MPU_xEventGroupSetBits_Priv:
-        pop {r0}
         b MPU_xEventGroupSetBitsImpl
     MPU_xEventGroupSetBits_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xEventGroupSetBits
 /*-----------------------------------------------------------*/
 
@@ -873,12 +814,11 @@ MPU_xEventGroupSync:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xEventGroupSync_Unpriv
     MPU_xEventGroupSync_Priv:
-        pop {r0}
         b MPU_xEventGroupSyncImpl
     MPU_xEventGroupSync_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xEventGroupSync
 /*-----------------------------------------------------------*/
 
@@ -887,12 +827,11 @@ MPU_uxEventGroupGetNumber:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxEventGroupGetNumber_Unpriv
     MPU_uxEventGroupGetNumber_Priv:
-        pop {r0}
         b MPU_uxEventGroupGetNumberImpl
     MPU_uxEventGroupGetNumber_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxEventGroupGetNumber
 /*-----------------------------------------------------------*/
 
@@ -901,12 +840,11 @@ MPU_vEventGroupSetNumber:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vEventGroupSetNumber_Unpriv
     MPU_vEventGroupSetNumber_Priv:
-        pop {r0}
         b MPU_vEventGroupSetNumberImpl
     MPU_vEventGroupSetNumber_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vEventGroupSetNumber
 /*-----------------------------------------------------------*/
 
@@ -915,12 +853,11 @@ MPU_xStreamBufferSend:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferSend_Unpriv
     MPU_xStreamBufferSend_Priv:
-        pop {r0}
         b MPU_xStreamBufferSendImpl
     MPU_xStreamBufferSend_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferSend
 /*-----------------------------------------------------------*/
 
@@ -929,12 +866,11 @@ MPU_xStreamBufferReceive:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferReceive_Unpriv
     MPU_xStreamBufferReceive_Priv:
-        pop {r0}
         b MPU_xStreamBufferReceiveImpl
     MPU_xStreamBufferReceive_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferReceive
 /*-----------------------------------------------------------*/
 
@@ -943,12 +879,11 @@ MPU_xStreamBufferIsFull:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferIsFull_Unpriv
     MPU_xStreamBufferIsFull_Priv:
-        pop {r0}
         b MPU_xStreamBufferIsFullImpl
     MPU_xStreamBufferIsFull_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferIsFull
 /*-----------------------------------------------------------*/
 
@@ -957,12 +892,11 @@ MPU_xStreamBufferIsEmpty:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferIsEmpty_Unpriv
     MPU_xStreamBufferIsEmpty_Priv:
-        pop {r0}
         b MPU_xStreamBufferIsEmptyImpl
     MPU_xStreamBufferIsEmpty_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferIsEmpty
 /*-----------------------------------------------------------*/
 
@@ -971,12 +905,11 @@ MPU_xStreamBufferSpacesAvailable:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferSpacesAvailable_Unpriv
     MPU_xStreamBufferSpacesAvailable_Priv:
-        pop {r0}
         b MPU_xStreamBufferSpacesAvailableImpl
     MPU_xStreamBufferSpacesAvailable_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferSpacesAvailable
 /*-----------------------------------------------------------*/
 
@@ -985,12 +918,11 @@ MPU_xStreamBufferBytesAvailable:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferBytesAvailable_Unpriv
     MPU_xStreamBufferBytesAvailable_Priv:
-        pop {r0}
         b MPU_xStreamBufferBytesAvailableImpl
     MPU_xStreamBufferBytesAvailable_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferBytesAvailable
 /*-----------------------------------------------------------*/
 
@@ -999,12 +931,11 @@ MPU_xStreamBufferSetTriggerLevel:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferSetTriggerLevel_Unpriv
     MPU_xStreamBufferSetTriggerLevel_Priv:
-        pop {r0}
         b MPU_xStreamBufferSetTriggerLevelImpl
     MPU_xStreamBufferSetTriggerLevel_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel
 /*-----------------------------------------------------------*/
 
@@ -1013,12 +944,11 @@ MPU_xStreamBufferNextMessageLengthBytes:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv
     MPU_xStreamBufferNextMessageLengthBytes_Priv:
-        pop {r0}
         b MPU_xStreamBufferNextMessageLengthBytesImpl
     MPU_xStreamBufferNextMessageLengthBytes_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM85/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM85/non_secure/mpu_wrappers_v2_asm.S
index a69845eda..d2cb78e92 100644
--- a/portable/IAR/ARM_CM85/non_secure/mpu_wrappers_v2_asm.S
+++ b/portable/IAR/ARM_CM85/non_secure/mpu_wrappers_v2_asm.S
@@ -47,12 +47,11 @@ MPU_xTaskDelayUntil:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskDelayUntil_Unpriv
     MPU_xTaskDelayUntil_Priv:
-        pop {r0}
         b MPU_xTaskDelayUntilImpl
     MPU_xTaskDelayUntil_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskDelayUntil
 /*-----------------------------------------------------------*/
 
@@ -61,12 +60,11 @@ MPU_xTaskAbortDelay:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskAbortDelay_Unpriv
     MPU_xTaskAbortDelay_Priv:
-        pop {r0}
         b MPU_xTaskAbortDelayImpl
     MPU_xTaskAbortDelay_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskAbortDelay
 /*-----------------------------------------------------------*/
 
@@ -75,12 +73,11 @@ MPU_vTaskDelay:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskDelay_Unpriv
     MPU_vTaskDelay_Priv:
-        pop {r0}
         b MPU_vTaskDelayImpl
     MPU_vTaskDelay_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskDelay
 /*-----------------------------------------------------------*/
 
@@ -89,12 +86,11 @@ MPU_uxTaskPriorityGet:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTaskPriorityGet_Unpriv
     MPU_uxTaskPriorityGet_Priv:
-        pop {r0}
         b MPU_uxTaskPriorityGetImpl
     MPU_uxTaskPriorityGet_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTaskPriorityGet
 /*-----------------------------------------------------------*/
 
@@ -103,12 +99,11 @@ MPU_eTaskGetState:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_eTaskGetState_Unpriv
     MPU_eTaskGetState_Priv:
-        pop {r0}
         b MPU_eTaskGetStateImpl
     MPU_eTaskGetState_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_eTaskGetState
 /*-----------------------------------------------------------*/
 
@@ -117,12 +112,11 @@ MPU_vTaskGetInfo:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskGetInfo_Unpriv
     MPU_vTaskGetInfo_Priv:
-        pop {r0}
         b MPU_vTaskGetInfoImpl
     MPU_vTaskGetInfo_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskGetInfo
 /*-----------------------------------------------------------*/
 
@@ -131,12 +125,11 @@ MPU_xTaskGetIdleTaskHandle:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGetIdleTaskHandle_Unpriv
     MPU_xTaskGetIdleTaskHandle_Priv:
-        pop {r0}
         b MPU_xTaskGetIdleTaskHandleImpl
     MPU_xTaskGetIdleTaskHandle_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGetIdleTaskHandle
 /*-----------------------------------------------------------*/
 
@@ -145,12 +138,11 @@ MPU_vTaskSuspend:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskSuspend_Unpriv
     MPU_vTaskSuspend_Priv:
-        pop {r0}
         b MPU_vTaskSuspendImpl
     MPU_vTaskSuspend_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskSuspend
 /*-----------------------------------------------------------*/
 
@@ -159,12 +151,11 @@ MPU_vTaskResume:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskResume_Unpriv
     MPU_vTaskResume_Priv:
-        pop {r0}
         b MPU_vTaskResumeImpl
     MPU_vTaskResume_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskResume
 /*-----------------------------------------------------------*/
 
@@ -173,12 +164,11 @@ MPU_xTaskGetTickCount:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGetTickCount_Unpriv
     MPU_xTaskGetTickCount_Priv:
-        pop {r0}
         b MPU_xTaskGetTickCountImpl
     MPU_xTaskGetTickCount_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGetTickCount
 /*-----------------------------------------------------------*/
 
@@ -187,12 +177,11 @@ MPU_uxTaskGetNumberOfTasks:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTaskGetNumberOfTasks_Unpriv
     MPU_uxTaskGetNumberOfTasks_Priv:
-        pop {r0}
         b MPU_uxTaskGetNumberOfTasksImpl
     MPU_uxTaskGetNumberOfTasks_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTaskGetNumberOfTasks
 /*-----------------------------------------------------------*/
 
@@ -201,12 +190,11 @@ MPU_ulTaskGetRunTimeCounter:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGetRunTimeCounter_Unpriv
     MPU_ulTaskGetRunTimeCounter_Priv:
-        pop {r0}
         b MPU_ulTaskGetRunTimeCounterImpl
     MPU_ulTaskGetRunTimeCounter_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGetRunTimeCounter
 /*-----------------------------------------------------------*/
 
@@ -215,12 +203,11 @@ MPU_ulTaskGetRunTimePercent:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGetRunTimePercent_Unpriv
     MPU_ulTaskGetRunTimePercent_Priv:
-        pop {r0}
         b MPU_ulTaskGetRunTimePercentImpl
     MPU_ulTaskGetRunTimePercent_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGetRunTimePercent
 /*-----------------------------------------------------------*/
 
@@ -229,12 +216,11 @@ MPU_ulTaskGetIdleRunTimePercent:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGetIdleRunTimePercent_Unpriv
     MPU_ulTaskGetIdleRunTimePercent_Priv:
-        pop {r0}
         b MPU_ulTaskGetIdleRunTimePercentImpl
     MPU_ulTaskGetIdleRunTimePercent_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent
 /*-----------------------------------------------------------*/
 
@@ -243,12 +229,11 @@ MPU_ulTaskGetIdleRunTimeCounter:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv
     MPU_ulTaskGetIdleRunTimeCounter_Priv:
-        pop {r0}
         b MPU_ulTaskGetIdleRunTimeCounterImpl
     MPU_ulTaskGetIdleRunTimeCounter_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter
 /*-----------------------------------------------------------*/
 
@@ -257,12 +242,11 @@ MPU_vTaskSetApplicationTaskTag:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskSetApplicationTaskTag_Unpriv
     MPU_vTaskSetApplicationTaskTag_Priv:
-        pop {r0}
         b MPU_vTaskSetApplicationTaskTagImpl
     MPU_vTaskSetApplicationTaskTag_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskSetApplicationTaskTag
 /*-----------------------------------------------------------*/
 
@@ -271,12 +255,11 @@ MPU_xTaskGetApplicationTaskTag:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGetApplicationTaskTag_Unpriv
     MPU_xTaskGetApplicationTaskTag_Priv:
-        pop {r0}
         b MPU_xTaskGetApplicationTaskTagImpl
     MPU_xTaskGetApplicationTaskTag_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGetApplicationTaskTag
 /*-----------------------------------------------------------*/
 
@@ -285,12 +268,11 @@ MPU_vTaskSetThreadLocalStoragePointer:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv
     MPU_vTaskSetThreadLocalStoragePointer_Priv:
-        pop {r0}
         b MPU_vTaskSetThreadLocalStoragePointerImpl
     MPU_vTaskSetThreadLocalStoragePointer_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer
 /*-----------------------------------------------------------*/
 
@@ -299,12 +281,11 @@ MPU_pvTaskGetThreadLocalStoragePointer:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv
     MPU_pvTaskGetThreadLocalStoragePointer_Priv:
-        pop {r0}
         b MPU_pvTaskGetThreadLocalStoragePointerImpl
     MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer
 /*-----------------------------------------------------------*/
 
@@ -313,12 +294,11 @@ MPU_uxTaskGetSystemState:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTaskGetSystemState_Unpriv
     MPU_uxTaskGetSystemState_Priv:
-        pop {r0}
         b MPU_uxTaskGetSystemStateImpl
     MPU_uxTaskGetSystemState_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTaskGetSystemState
 /*-----------------------------------------------------------*/
 
@@ -327,12 +307,11 @@ MPU_uxTaskGetStackHighWaterMark:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTaskGetStackHighWaterMark_Unpriv
     MPU_uxTaskGetStackHighWaterMark_Priv:
-        pop {r0}
         b MPU_uxTaskGetStackHighWaterMarkImpl
     MPU_uxTaskGetStackHighWaterMark_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark
 /*-----------------------------------------------------------*/
 
@@ -341,12 +320,11 @@ MPU_uxTaskGetStackHighWaterMark2:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTaskGetStackHighWaterMark2_Unpriv
     MPU_uxTaskGetStackHighWaterMark2_Priv:
-        pop {r0}
         b MPU_uxTaskGetStackHighWaterMark2Impl
     MPU_uxTaskGetStackHighWaterMark2_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2
 /*-----------------------------------------------------------*/
 
@@ -355,12 +333,11 @@ MPU_xTaskGetCurrentTaskHandle:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGetCurrentTaskHandle_Unpriv
     MPU_xTaskGetCurrentTaskHandle_Priv:
-        pop {r0}
         b MPU_xTaskGetCurrentTaskHandleImpl
     MPU_xTaskGetCurrentTaskHandle_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle
 /*-----------------------------------------------------------*/
 
@@ -369,12 +346,11 @@ MPU_xTaskGetSchedulerState:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGetSchedulerState_Unpriv
     MPU_xTaskGetSchedulerState_Priv:
-        pop {r0}
         b MPU_xTaskGetSchedulerStateImpl
     MPU_xTaskGetSchedulerState_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGetSchedulerState
 /*-----------------------------------------------------------*/
 
@@ -383,12 +359,11 @@ MPU_vTaskSetTimeOutState:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskSetTimeOutState_Unpriv
     MPU_vTaskSetTimeOutState_Priv:
-        pop {r0}
         b MPU_vTaskSetTimeOutStateImpl
     MPU_vTaskSetTimeOutState_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskSetTimeOutState
 /*-----------------------------------------------------------*/
 
@@ -397,12 +372,11 @@ MPU_xTaskCheckForTimeOut:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskCheckForTimeOut_Unpriv
     MPU_xTaskCheckForTimeOut_Priv:
-        pop {r0}
         b MPU_xTaskCheckForTimeOutImpl
     MPU_xTaskCheckForTimeOut_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskCheckForTimeOut
 /*-----------------------------------------------------------*/
 
@@ -411,12 +385,11 @@ MPU_xTaskGenericNotifyEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGenericNotify_Unpriv
     MPU_xTaskGenericNotify_Priv:
-        pop {r0}
         b MPU_xTaskGenericNotifyImpl
     MPU_xTaskGenericNotify_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGenericNotify
 /*-----------------------------------------------------------*/
 
@@ -425,12 +398,11 @@ MPU_xTaskGenericNotifyWaitEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGenericNotifyWait_Unpriv
     MPU_xTaskGenericNotifyWait_Priv:
-        pop {r0}
         b MPU_xTaskGenericNotifyWaitImpl
     MPU_xTaskGenericNotifyWait_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGenericNotifyWait
 /*-----------------------------------------------------------*/
 
@@ -439,12 +411,11 @@ MPU_ulTaskGenericNotifyTake:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGenericNotifyTake_Unpriv
     MPU_ulTaskGenericNotifyTake_Priv:
-        pop {r0}
         b MPU_ulTaskGenericNotifyTakeImpl
     MPU_ulTaskGenericNotifyTake_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGenericNotifyTake
 /*-----------------------------------------------------------*/
 
@@ -453,12 +424,11 @@ MPU_xTaskGenericNotifyStateClear:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGenericNotifyStateClear_Unpriv
     MPU_xTaskGenericNotifyStateClear_Priv:
-        pop {r0}
         b MPU_xTaskGenericNotifyStateClearImpl
     MPU_xTaskGenericNotifyStateClear_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGenericNotifyStateClear
 /*-----------------------------------------------------------*/
 
@@ -467,12 +437,11 @@ MPU_ulTaskGenericNotifyValueClear:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGenericNotifyValueClear_Unpriv
     MPU_ulTaskGenericNotifyValueClear_Priv:
-        pop {r0}
         b MPU_ulTaskGenericNotifyValueClearImpl
     MPU_ulTaskGenericNotifyValueClear_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear
 /*-----------------------------------------------------------*/
 
@@ -481,12 +450,11 @@ MPU_xQueueGenericSend:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueGenericSend_Unpriv
     MPU_xQueueGenericSend_Priv:
-        pop {r0}
         b MPU_xQueueGenericSendImpl
     MPU_xQueueGenericSend_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueGenericSend
 /*-----------------------------------------------------------*/
 
@@ -495,12 +463,11 @@ MPU_uxQueueMessagesWaiting:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxQueueMessagesWaiting_Unpriv
     MPU_uxQueueMessagesWaiting_Priv:
-        pop {r0}
         b MPU_uxQueueMessagesWaitingImpl
     MPU_uxQueueMessagesWaiting_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxQueueMessagesWaiting
 /*-----------------------------------------------------------*/
 
@@ -509,12 +476,11 @@ MPU_uxQueueSpacesAvailable:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxQueueSpacesAvailable_Unpriv
     MPU_uxQueueSpacesAvailable_Priv:
-        pop {r0}
         b MPU_uxQueueSpacesAvailableImpl
     MPU_uxQueueSpacesAvailable_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxQueueSpacesAvailable
 /*-----------------------------------------------------------*/
 
@@ -523,12 +489,11 @@ MPU_xQueueReceive:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueReceive_Unpriv
     MPU_xQueueReceive_Priv:
-        pop {r0}
         b MPU_xQueueReceiveImpl
     MPU_xQueueReceive_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueReceive
 /*-----------------------------------------------------------*/
 
@@ -537,12 +502,11 @@ MPU_xQueuePeek:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueuePeek_Unpriv
     MPU_xQueuePeek_Priv:
-        pop {r0}
         b MPU_xQueuePeekImpl
     MPU_xQueuePeek_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueuePeek
 /*-----------------------------------------------------------*/
 
@@ -551,12 +515,11 @@ MPU_xQueueSemaphoreTake:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueSemaphoreTake_Unpriv
     MPU_xQueueSemaphoreTake_Priv:
-        pop {r0}
         b MPU_xQueueSemaphoreTakeImpl
     MPU_xQueueSemaphoreTake_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueSemaphoreTake
 /*-----------------------------------------------------------*/
 
@@ -565,12 +528,11 @@ MPU_xQueueGetMutexHolder:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueGetMutexHolder_Unpriv
     MPU_xQueueGetMutexHolder_Priv:
-        pop {r0}
         b MPU_xQueueGetMutexHolderImpl
     MPU_xQueueGetMutexHolder_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueGetMutexHolder
 /*-----------------------------------------------------------*/
 
@@ -579,12 +541,11 @@ MPU_xQueueTakeMutexRecursive:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueTakeMutexRecursive_Unpriv
     MPU_xQueueTakeMutexRecursive_Priv:
-        pop {r0}
         b MPU_xQueueTakeMutexRecursiveImpl
     MPU_xQueueTakeMutexRecursive_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueTakeMutexRecursive
 /*-----------------------------------------------------------*/
 
@@ -593,12 +554,11 @@ MPU_xQueueGiveMutexRecursive:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueGiveMutexRecursive_Unpriv
     MPU_xQueueGiveMutexRecursive_Priv:
-        pop {r0}
         b MPU_xQueueGiveMutexRecursiveImpl
     MPU_xQueueGiveMutexRecursive_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueGiveMutexRecursive
 /*-----------------------------------------------------------*/
 
@@ -607,12 +567,11 @@ MPU_xQueueSelectFromSet:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueSelectFromSet_Unpriv
     MPU_xQueueSelectFromSet_Priv:
-        pop {r0}
         b MPU_xQueueSelectFromSetImpl
     MPU_xQueueSelectFromSet_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueSelectFromSet
 /*-----------------------------------------------------------*/
 
@@ -621,12 +580,11 @@ MPU_xQueueAddToSet:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueAddToSet_Unpriv
     MPU_xQueueAddToSet_Priv:
-        pop {r0}
         b MPU_xQueueAddToSetImpl
     MPU_xQueueAddToSet_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueAddToSet
 /*-----------------------------------------------------------*/
 
@@ -635,12 +593,11 @@ MPU_vQueueAddToRegistry:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vQueueAddToRegistry_Unpriv
     MPU_vQueueAddToRegistry_Priv:
-        pop {r0}
         b MPU_vQueueAddToRegistryImpl
     MPU_vQueueAddToRegistry_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vQueueAddToRegistry
 /*-----------------------------------------------------------*/
 
@@ -649,12 +606,11 @@ MPU_vQueueUnregisterQueue:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vQueueUnregisterQueue_Unpriv
     MPU_vQueueUnregisterQueue_Priv:
-        pop {r0}
         b MPU_vQueueUnregisterQueueImpl
     MPU_vQueueUnregisterQueue_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vQueueUnregisterQueue
 /*-----------------------------------------------------------*/
 
@@ -663,12 +619,11 @@ MPU_pcQueueGetName:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_pcQueueGetName_Unpriv
     MPU_pcQueueGetName_Priv:
-        pop {r0}
         b MPU_pcQueueGetNameImpl
     MPU_pcQueueGetName_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_pcQueueGetName
 /*-----------------------------------------------------------*/
 
@@ -677,12 +632,11 @@ MPU_pvTimerGetTimerID:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_pvTimerGetTimerID_Unpriv
     MPU_pvTimerGetTimerID_Priv:
-        pop {r0}
         b MPU_pvTimerGetTimerIDImpl
     MPU_pvTimerGetTimerID_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_pvTimerGetTimerID
 /*-----------------------------------------------------------*/
 
@@ -691,12 +645,11 @@ MPU_vTimerSetTimerID:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTimerSetTimerID_Unpriv
     MPU_vTimerSetTimerID_Priv:
-        pop {r0}
         b MPU_vTimerSetTimerIDImpl
     MPU_vTimerSetTimerID_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTimerSetTimerID
 /*-----------------------------------------------------------*/
 
@@ -705,12 +658,11 @@ MPU_xTimerIsTimerActive:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerIsTimerActive_Unpriv
     MPU_xTimerIsTimerActive_Priv:
-        pop {r0}
         b MPU_xTimerIsTimerActiveImpl
     MPU_xTimerIsTimerActive_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerIsTimerActive
 /*-----------------------------------------------------------*/
 
@@ -719,12 +671,11 @@ MPU_xTimerGetTimerDaemonTaskHandle:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv
     MPU_xTimerGetTimerDaemonTaskHandle_Priv:
-        pop {r0}
         b MPU_xTimerGetTimerDaemonTaskHandleImpl
     MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle
 /*-----------------------------------------------------------*/
 
@@ -733,12 +684,11 @@ MPU_xTimerGenericCommandFromTaskEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerGenericCommandFromTask_Unpriv
     MPU_xTimerGenericCommandFromTask_Priv:
-        pop {r0}
         b MPU_xTimerGenericCommandFromTaskImpl
     MPU_xTimerGenericCommandFromTask_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerGenericCommandFromTask
 /*-----------------------------------------------------------*/
 
@@ -747,12 +697,11 @@ MPU_pcTimerGetName:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_pcTimerGetName_Unpriv
     MPU_pcTimerGetName_Priv:
-        pop {r0}
         b MPU_pcTimerGetNameImpl
     MPU_pcTimerGetName_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_pcTimerGetName
 /*-----------------------------------------------------------*/
 
@@ -761,12 +710,11 @@ MPU_vTimerSetReloadMode:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTimerSetReloadMode_Unpriv
     MPU_vTimerSetReloadMode_Priv:
-        pop {r0}
         b MPU_vTimerSetReloadModeImpl
     MPU_vTimerSetReloadMode_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTimerSetReloadMode
 /*-----------------------------------------------------------*/
 
@@ -775,12 +723,11 @@ MPU_xTimerGetReloadMode:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerGetReloadMode_Unpriv
     MPU_xTimerGetReloadMode_Priv:
-        pop {r0}
         b MPU_xTimerGetReloadModeImpl
     MPU_xTimerGetReloadMode_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerGetReloadMode
 /*-----------------------------------------------------------*/
 
@@ -789,12 +736,11 @@ MPU_uxTimerGetReloadMode:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTimerGetReloadMode_Unpriv
     MPU_uxTimerGetReloadMode_Priv:
-        pop {r0}
         b MPU_uxTimerGetReloadModeImpl
     MPU_uxTimerGetReloadMode_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTimerGetReloadMode
 /*-----------------------------------------------------------*/
 
@@ -803,12 +749,11 @@ MPU_xTimerGetPeriod:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerGetPeriod_Unpriv
     MPU_xTimerGetPeriod_Priv:
-        pop {r0}
         b MPU_xTimerGetPeriodImpl
     MPU_xTimerGetPeriod_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerGetPeriod
 /*-----------------------------------------------------------*/
 
@@ -817,12 +762,11 @@ MPU_xTimerGetExpiryTime:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerGetExpiryTime_Unpriv
     MPU_xTimerGetExpiryTime_Priv:
-        pop {r0}
         b MPU_xTimerGetExpiryTimeImpl
     MPU_xTimerGetExpiryTime_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerGetExpiryTime
 /*-----------------------------------------------------------*/
 
@@ -831,12 +775,11 @@ MPU_xEventGroupWaitBitsEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xEventGroupWaitBits_Unpriv
     MPU_xEventGroupWaitBits_Priv:
-        pop {r0}
         b MPU_xEventGroupWaitBitsImpl
     MPU_xEventGroupWaitBits_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xEventGroupWaitBits
 /*-----------------------------------------------------------*/
 
@@ -845,12 +788,11 @@ MPU_xEventGroupClearBits:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xEventGroupClearBits_Unpriv
     MPU_xEventGroupClearBits_Priv:
-        pop {r0}
         b MPU_xEventGroupClearBitsImpl
     MPU_xEventGroupClearBits_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xEventGroupClearBits
 /*-----------------------------------------------------------*/
 
@@ -859,12 +801,11 @@ MPU_xEventGroupSetBits:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xEventGroupSetBits_Unpriv
     MPU_xEventGroupSetBits_Priv:
-        pop {r0}
         b MPU_xEventGroupSetBitsImpl
     MPU_xEventGroupSetBits_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xEventGroupSetBits
 /*-----------------------------------------------------------*/
 
@@ -873,12 +814,11 @@ MPU_xEventGroupSync:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xEventGroupSync_Unpriv
     MPU_xEventGroupSync_Priv:
-        pop {r0}
         b MPU_xEventGroupSyncImpl
     MPU_xEventGroupSync_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xEventGroupSync
 /*-----------------------------------------------------------*/
 
@@ -887,12 +827,11 @@ MPU_uxEventGroupGetNumber:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxEventGroupGetNumber_Unpriv
     MPU_uxEventGroupGetNumber_Priv:
-        pop {r0}
         b MPU_uxEventGroupGetNumberImpl
     MPU_uxEventGroupGetNumber_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxEventGroupGetNumber
 /*-----------------------------------------------------------*/
 
@@ -901,12 +840,11 @@ MPU_vEventGroupSetNumber:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vEventGroupSetNumber_Unpriv
     MPU_vEventGroupSetNumber_Priv:
-        pop {r0}
         b MPU_vEventGroupSetNumberImpl
     MPU_vEventGroupSetNumber_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vEventGroupSetNumber
 /*-----------------------------------------------------------*/
 
@@ -915,12 +853,11 @@ MPU_xStreamBufferSend:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferSend_Unpriv
     MPU_xStreamBufferSend_Priv:
-        pop {r0}
         b MPU_xStreamBufferSendImpl
     MPU_xStreamBufferSend_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferSend
 /*-----------------------------------------------------------*/
 
@@ -929,12 +866,11 @@ MPU_xStreamBufferReceive:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferReceive_Unpriv
     MPU_xStreamBufferReceive_Priv:
-        pop {r0}
         b MPU_xStreamBufferReceiveImpl
     MPU_xStreamBufferReceive_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferReceive
 /*-----------------------------------------------------------*/
 
@@ -943,12 +879,11 @@ MPU_xStreamBufferIsFull:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferIsFull_Unpriv
     MPU_xStreamBufferIsFull_Priv:
-        pop {r0}
         b MPU_xStreamBufferIsFullImpl
     MPU_xStreamBufferIsFull_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferIsFull
 /*-----------------------------------------------------------*/
 
@@ -957,12 +892,11 @@ MPU_xStreamBufferIsEmpty:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferIsEmpty_Unpriv
     MPU_xStreamBufferIsEmpty_Priv:
-        pop {r0}
         b MPU_xStreamBufferIsEmptyImpl
     MPU_xStreamBufferIsEmpty_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferIsEmpty
 /*-----------------------------------------------------------*/
 
@@ -971,12 +905,11 @@ MPU_xStreamBufferSpacesAvailable:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferSpacesAvailable_Unpriv
     MPU_xStreamBufferSpacesAvailable_Priv:
-        pop {r0}
         b MPU_xStreamBufferSpacesAvailableImpl
     MPU_xStreamBufferSpacesAvailable_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferSpacesAvailable
 /*-----------------------------------------------------------*/
 
@@ -985,12 +918,11 @@ MPU_xStreamBufferBytesAvailable:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferBytesAvailable_Unpriv
     MPU_xStreamBufferBytesAvailable_Priv:
-        pop {r0}
         b MPU_xStreamBufferBytesAvailableImpl
     MPU_xStreamBufferBytesAvailable_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferBytesAvailable
 /*-----------------------------------------------------------*/
 
@@ -999,12 +931,11 @@ MPU_xStreamBufferSetTriggerLevel:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferSetTriggerLevel_Unpriv
     MPU_xStreamBufferSetTriggerLevel_Priv:
-        pop {r0}
         b MPU_xStreamBufferSetTriggerLevelImpl
     MPU_xStreamBufferSetTriggerLevel_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel
 /*-----------------------------------------------------------*/
 
@@ -1013,12 +944,11 @@ MPU_xStreamBufferNextMessageLengthBytes:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv
     MPU_xStreamBufferNextMessageLengthBytes_Priv:
-        pop {r0}
         b MPU_xStreamBufferNextMessageLengthBytesImpl
     MPU_xStreamBufferNextMessageLengthBytes_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.S
index a69845eda..d2cb78e92 100644
--- a/portable/IAR/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.S
+++ b/portable/IAR/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.S
@@ -47,12 +47,11 @@ MPU_xTaskDelayUntil:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskDelayUntil_Unpriv
     MPU_xTaskDelayUntil_Priv:
-        pop {r0}
         b MPU_xTaskDelayUntilImpl
     MPU_xTaskDelayUntil_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskDelayUntil
 /*-----------------------------------------------------------*/
 
@@ -61,12 +60,11 @@ MPU_xTaskAbortDelay:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskAbortDelay_Unpriv
     MPU_xTaskAbortDelay_Priv:
-        pop {r0}
         b MPU_xTaskAbortDelayImpl
     MPU_xTaskAbortDelay_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskAbortDelay
 /*-----------------------------------------------------------*/
 
@@ -75,12 +73,11 @@ MPU_vTaskDelay:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskDelay_Unpriv
     MPU_vTaskDelay_Priv:
-        pop {r0}
         b MPU_vTaskDelayImpl
     MPU_vTaskDelay_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskDelay
 /*-----------------------------------------------------------*/
 
@@ -89,12 +86,11 @@ MPU_uxTaskPriorityGet:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTaskPriorityGet_Unpriv
     MPU_uxTaskPriorityGet_Priv:
-        pop {r0}
         b MPU_uxTaskPriorityGetImpl
     MPU_uxTaskPriorityGet_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTaskPriorityGet
 /*-----------------------------------------------------------*/
 
@@ -103,12 +99,11 @@ MPU_eTaskGetState:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_eTaskGetState_Unpriv
     MPU_eTaskGetState_Priv:
-        pop {r0}
         b MPU_eTaskGetStateImpl
     MPU_eTaskGetState_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_eTaskGetState
 /*-----------------------------------------------------------*/
 
@@ -117,12 +112,11 @@ MPU_vTaskGetInfo:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskGetInfo_Unpriv
     MPU_vTaskGetInfo_Priv:
-        pop {r0}
         b MPU_vTaskGetInfoImpl
     MPU_vTaskGetInfo_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskGetInfo
 /*-----------------------------------------------------------*/
 
@@ -131,12 +125,11 @@ MPU_xTaskGetIdleTaskHandle:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGetIdleTaskHandle_Unpriv
     MPU_xTaskGetIdleTaskHandle_Priv:
-        pop {r0}
         b MPU_xTaskGetIdleTaskHandleImpl
     MPU_xTaskGetIdleTaskHandle_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGetIdleTaskHandle
 /*-----------------------------------------------------------*/
 
@@ -145,12 +138,11 @@ MPU_vTaskSuspend:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskSuspend_Unpriv
     MPU_vTaskSuspend_Priv:
-        pop {r0}
         b MPU_vTaskSuspendImpl
     MPU_vTaskSuspend_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskSuspend
 /*-----------------------------------------------------------*/
 
@@ -159,12 +151,11 @@ MPU_vTaskResume:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskResume_Unpriv
     MPU_vTaskResume_Priv:
-        pop {r0}
         b MPU_vTaskResumeImpl
     MPU_vTaskResume_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskResume
 /*-----------------------------------------------------------*/
 
@@ -173,12 +164,11 @@ MPU_xTaskGetTickCount:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGetTickCount_Unpriv
     MPU_xTaskGetTickCount_Priv:
-        pop {r0}
         b MPU_xTaskGetTickCountImpl
     MPU_xTaskGetTickCount_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGetTickCount
 /*-----------------------------------------------------------*/
 
@@ -187,12 +177,11 @@ MPU_uxTaskGetNumberOfTasks:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTaskGetNumberOfTasks_Unpriv
     MPU_uxTaskGetNumberOfTasks_Priv:
-        pop {r0}
         b MPU_uxTaskGetNumberOfTasksImpl
     MPU_uxTaskGetNumberOfTasks_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTaskGetNumberOfTasks
 /*-----------------------------------------------------------*/
 
@@ -201,12 +190,11 @@ MPU_ulTaskGetRunTimeCounter:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGetRunTimeCounter_Unpriv
     MPU_ulTaskGetRunTimeCounter_Priv:
-        pop {r0}
         b MPU_ulTaskGetRunTimeCounterImpl
     MPU_ulTaskGetRunTimeCounter_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGetRunTimeCounter
 /*-----------------------------------------------------------*/
 
@@ -215,12 +203,11 @@ MPU_ulTaskGetRunTimePercent:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGetRunTimePercent_Unpriv
     MPU_ulTaskGetRunTimePercent_Priv:
-        pop {r0}
         b MPU_ulTaskGetRunTimePercentImpl
     MPU_ulTaskGetRunTimePercent_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGetRunTimePercent
 /*-----------------------------------------------------------*/
 
@@ -229,12 +216,11 @@ MPU_ulTaskGetIdleRunTimePercent:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGetIdleRunTimePercent_Unpriv
     MPU_ulTaskGetIdleRunTimePercent_Priv:
-        pop {r0}
         b MPU_ulTaskGetIdleRunTimePercentImpl
     MPU_ulTaskGetIdleRunTimePercent_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent
 /*-----------------------------------------------------------*/
 
@@ -243,12 +229,11 @@ MPU_ulTaskGetIdleRunTimeCounter:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv
     MPU_ulTaskGetIdleRunTimeCounter_Priv:
-        pop {r0}
         b MPU_ulTaskGetIdleRunTimeCounterImpl
     MPU_ulTaskGetIdleRunTimeCounter_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter
 /*-----------------------------------------------------------*/
 
@@ -257,12 +242,11 @@ MPU_vTaskSetApplicationTaskTag:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskSetApplicationTaskTag_Unpriv
     MPU_vTaskSetApplicationTaskTag_Priv:
-        pop {r0}
         b MPU_vTaskSetApplicationTaskTagImpl
     MPU_vTaskSetApplicationTaskTag_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskSetApplicationTaskTag
 /*-----------------------------------------------------------*/
 
@@ -271,12 +255,11 @@ MPU_xTaskGetApplicationTaskTag:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGetApplicationTaskTag_Unpriv
     MPU_xTaskGetApplicationTaskTag_Priv:
-        pop {r0}
         b MPU_xTaskGetApplicationTaskTagImpl
     MPU_xTaskGetApplicationTaskTag_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGetApplicationTaskTag
 /*-----------------------------------------------------------*/
 
@@ -285,12 +268,11 @@ MPU_vTaskSetThreadLocalStoragePointer:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv
     MPU_vTaskSetThreadLocalStoragePointer_Priv:
-        pop {r0}
         b MPU_vTaskSetThreadLocalStoragePointerImpl
     MPU_vTaskSetThreadLocalStoragePointer_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer
 /*-----------------------------------------------------------*/
 
@@ -299,12 +281,11 @@ MPU_pvTaskGetThreadLocalStoragePointer:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv
     MPU_pvTaskGetThreadLocalStoragePointer_Priv:
-        pop {r0}
         b MPU_pvTaskGetThreadLocalStoragePointerImpl
     MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer
 /*-----------------------------------------------------------*/
 
@@ -313,12 +294,11 @@ MPU_uxTaskGetSystemState:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTaskGetSystemState_Unpriv
     MPU_uxTaskGetSystemState_Priv:
-        pop {r0}
         b MPU_uxTaskGetSystemStateImpl
     MPU_uxTaskGetSystemState_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTaskGetSystemState
 /*-----------------------------------------------------------*/
 
@@ -327,12 +307,11 @@ MPU_uxTaskGetStackHighWaterMark:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTaskGetStackHighWaterMark_Unpriv
     MPU_uxTaskGetStackHighWaterMark_Priv:
-        pop {r0}
         b MPU_uxTaskGetStackHighWaterMarkImpl
     MPU_uxTaskGetStackHighWaterMark_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark
 /*-----------------------------------------------------------*/
 
@@ -341,12 +320,11 @@ MPU_uxTaskGetStackHighWaterMark2:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTaskGetStackHighWaterMark2_Unpriv
     MPU_uxTaskGetStackHighWaterMark2_Priv:
-        pop {r0}
         b MPU_uxTaskGetStackHighWaterMark2Impl
     MPU_uxTaskGetStackHighWaterMark2_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2
 /*-----------------------------------------------------------*/
 
@@ -355,12 +333,11 @@ MPU_xTaskGetCurrentTaskHandle:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGetCurrentTaskHandle_Unpriv
     MPU_xTaskGetCurrentTaskHandle_Priv:
-        pop {r0}
         b MPU_xTaskGetCurrentTaskHandleImpl
     MPU_xTaskGetCurrentTaskHandle_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle
 /*-----------------------------------------------------------*/
 
@@ -369,12 +346,11 @@ MPU_xTaskGetSchedulerState:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGetSchedulerState_Unpriv
     MPU_xTaskGetSchedulerState_Priv:
-        pop {r0}
         b MPU_xTaskGetSchedulerStateImpl
     MPU_xTaskGetSchedulerState_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGetSchedulerState
 /*-----------------------------------------------------------*/
 
@@ -383,12 +359,11 @@ MPU_vTaskSetTimeOutState:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskSetTimeOutState_Unpriv
     MPU_vTaskSetTimeOutState_Priv:
-        pop {r0}
         b MPU_vTaskSetTimeOutStateImpl
     MPU_vTaskSetTimeOutState_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTaskSetTimeOutState
 /*-----------------------------------------------------------*/
 
@@ -397,12 +372,11 @@ MPU_xTaskCheckForTimeOut:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskCheckForTimeOut_Unpriv
     MPU_xTaskCheckForTimeOut_Priv:
-        pop {r0}
         b MPU_xTaskCheckForTimeOutImpl
     MPU_xTaskCheckForTimeOut_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskCheckForTimeOut
 /*-----------------------------------------------------------*/
 
@@ -411,12 +385,11 @@ MPU_xTaskGenericNotifyEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGenericNotify_Unpriv
     MPU_xTaskGenericNotify_Priv:
-        pop {r0}
         b MPU_xTaskGenericNotifyImpl
     MPU_xTaskGenericNotify_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGenericNotify
 /*-----------------------------------------------------------*/
 
@@ -425,12 +398,11 @@ MPU_xTaskGenericNotifyWaitEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGenericNotifyWait_Unpriv
     MPU_xTaskGenericNotifyWait_Priv:
-        pop {r0}
         b MPU_xTaskGenericNotifyWaitImpl
     MPU_xTaskGenericNotifyWait_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGenericNotifyWait
 /*-----------------------------------------------------------*/
 
@@ -439,12 +411,11 @@ MPU_ulTaskGenericNotifyTake:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGenericNotifyTake_Unpriv
     MPU_ulTaskGenericNotifyTake_Priv:
-        pop {r0}
         b MPU_ulTaskGenericNotifyTakeImpl
     MPU_ulTaskGenericNotifyTake_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGenericNotifyTake
 /*-----------------------------------------------------------*/
 
@@ -453,12 +424,11 @@ MPU_xTaskGenericNotifyStateClear:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGenericNotifyStateClear_Unpriv
     MPU_xTaskGenericNotifyStateClear_Priv:
-        pop {r0}
         b MPU_xTaskGenericNotifyStateClearImpl
     MPU_xTaskGenericNotifyStateClear_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGenericNotifyStateClear
 /*-----------------------------------------------------------*/
 
@@ -467,12 +437,11 @@ MPU_ulTaskGenericNotifyValueClear:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGenericNotifyValueClear_Unpriv
     MPU_ulTaskGenericNotifyValueClear_Priv:
-        pop {r0}
         b MPU_ulTaskGenericNotifyValueClearImpl
     MPU_ulTaskGenericNotifyValueClear_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear
 /*-----------------------------------------------------------*/
 
@@ -481,12 +450,11 @@ MPU_xQueueGenericSend:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueGenericSend_Unpriv
     MPU_xQueueGenericSend_Priv:
-        pop {r0}
         b MPU_xQueueGenericSendImpl
     MPU_xQueueGenericSend_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueGenericSend
 /*-----------------------------------------------------------*/
 
@@ -495,12 +463,11 @@ MPU_uxQueueMessagesWaiting:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxQueueMessagesWaiting_Unpriv
     MPU_uxQueueMessagesWaiting_Priv:
-        pop {r0}
         b MPU_uxQueueMessagesWaitingImpl
     MPU_uxQueueMessagesWaiting_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxQueueMessagesWaiting
 /*-----------------------------------------------------------*/
 
@@ -509,12 +476,11 @@ MPU_uxQueueSpacesAvailable:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxQueueSpacesAvailable_Unpriv
     MPU_uxQueueSpacesAvailable_Priv:
-        pop {r0}
         b MPU_uxQueueSpacesAvailableImpl
     MPU_uxQueueSpacesAvailable_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxQueueSpacesAvailable
 /*-----------------------------------------------------------*/
 
@@ -523,12 +489,11 @@ MPU_xQueueReceive:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueReceive_Unpriv
     MPU_xQueueReceive_Priv:
-        pop {r0}
         b MPU_xQueueReceiveImpl
     MPU_xQueueReceive_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueReceive
 /*-----------------------------------------------------------*/
 
@@ -537,12 +502,11 @@ MPU_xQueuePeek:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueuePeek_Unpriv
     MPU_xQueuePeek_Priv:
-        pop {r0}
         b MPU_xQueuePeekImpl
     MPU_xQueuePeek_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueuePeek
 /*-----------------------------------------------------------*/
 
@@ -551,12 +515,11 @@ MPU_xQueueSemaphoreTake:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueSemaphoreTake_Unpriv
     MPU_xQueueSemaphoreTake_Priv:
-        pop {r0}
         b MPU_xQueueSemaphoreTakeImpl
     MPU_xQueueSemaphoreTake_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueSemaphoreTake
 /*-----------------------------------------------------------*/
 
@@ -565,12 +528,11 @@ MPU_xQueueGetMutexHolder:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueGetMutexHolder_Unpriv
     MPU_xQueueGetMutexHolder_Priv:
-        pop {r0}
         b MPU_xQueueGetMutexHolderImpl
     MPU_xQueueGetMutexHolder_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueGetMutexHolder
 /*-----------------------------------------------------------*/
 
@@ -579,12 +541,11 @@ MPU_xQueueTakeMutexRecursive:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueTakeMutexRecursive_Unpriv
     MPU_xQueueTakeMutexRecursive_Priv:
-        pop {r0}
         b MPU_xQueueTakeMutexRecursiveImpl
     MPU_xQueueTakeMutexRecursive_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueTakeMutexRecursive
 /*-----------------------------------------------------------*/
 
@@ -593,12 +554,11 @@ MPU_xQueueGiveMutexRecursive:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueGiveMutexRecursive_Unpriv
     MPU_xQueueGiveMutexRecursive_Priv:
-        pop {r0}
         b MPU_xQueueGiveMutexRecursiveImpl
     MPU_xQueueGiveMutexRecursive_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueGiveMutexRecursive
 /*-----------------------------------------------------------*/
 
@@ -607,12 +567,11 @@ MPU_xQueueSelectFromSet:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueSelectFromSet_Unpriv
     MPU_xQueueSelectFromSet_Priv:
-        pop {r0}
         b MPU_xQueueSelectFromSetImpl
     MPU_xQueueSelectFromSet_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueSelectFromSet
 /*-----------------------------------------------------------*/
 
@@ -621,12 +580,11 @@ MPU_xQueueAddToSet:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueAddToSet_Unpriv
     MPU_xQueueAddToSet_Priv:
-        pop {r0}
         b MPU_xQueueAddToSetImpl
     MPU_xQueueAddToSet_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xQueueAddToSet
 /*-----------------------------------------------------------*/
 
@@ -635,12 +593,11 @@ MPU_vQueueAddToRegistry:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vQueueAddToRegistry_Unpriv
     MPU_vQueueAddToRegistry_Priv:
-        pop {r0}
         b MPU_vQueueAddToRegistryImpl
     MPU_vQueueAddToRegistry_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vQueueAddToRegistry
 /*-----------------------------------------------------------*/
 
@@ -649,12 +606,11 @@ MPU_vQueueUnregisterQueue:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vQueueUnregisterQueue_Unpriv
     MPU_vQueueUnregisterQueue_Priv:
-        pop {r0}
         b MPU_vQueueUnregisterQueueImpl
     MPU_vQueueUnregisterQueue_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vQueueUnregisterQueue
 /*-----------------------------------------------------------*/
 
@@ -663,12 +619,11 @@ MPU_pcQueueGetName:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_pcQueueGetName_Unpriv
     MPU_pcQueueGetName_Priv:
-        pop {r0}
         b MPU_pcQueueGetNameImpl
     MPU_pcQueueGetName_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_pcQueueGetName
 /*-----------------------------------------------------------*/
 
@@ -677,12 +632,11 @@ MPU_pvTimerGetTimerID:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_pvTimerGetTimerID_Unpriv
     MPU_pvTimerGetTimerID_Priv:
-        pop {r0}
         b MPU_pvTimerGetTimerIDImpl
     MPU_pvTimerGetTimerID_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_pvTimerGetTimerID
 /*-----------------------------------------------------------*/
 
@@ -691,12 +645,11 @@ MPU_vTimerSetTimerID:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTimerSetTimerID_Unpriv
     MPU_vTimerSetTimerID_Priv:
-        pop {r0}
         b MPU_vTimerSetTimerIDImpl
     MPU_vTimerSetTimerID_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTimerSetTimerID
 /*-----------------------------------------------------------*/
 
@@ -705,12 +658,11 @@ MPU_xTimerIsTimerActive:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerIsTimerActive_Unpriv
     MPU_xTimerIsTimerActive_Priv:
-        pop {r0}
         b MPU_xTimerIsTimerActiveImpl
     MPU_xTimerIsTimerActive_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerIsTimerActive
 /*-----------------------------------------------------------*/
 
@@ -719,12 +671,11 @@ MPU_xTimerGetTimerDaemonTaskHandle:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv
     MPU_xTimerGetTimerDaemonTaskHandle_Priv:
-        pop {r0}
         b MPU_xTimerGetTimerDaemonTaskHandleImpl
     MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle
 /*-----------------------------------------------------------*/
 
@@ -733,12 +684,11 @@ MPU_xTimerGenericCommandFromTaskEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerGenericCommandFromTask_Unpriv
     MPU_xTimerGenericCommandFromTask_Priv:
-        pop {r0}
         b MPU_xTimerGenericCommandFromTaskImpl
     MPU_xTimerGenericCommandFromTask_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerGenericCommandFromTask
 /*-----------------------------------------------------------*/
 
@@ -747,12 +697,11 @@ MPU_pcTimerGetName:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_pcTimerGetName_Unpriv
     MPU_pcTimerGetName_Priv:
-        pop {r0}
         b MPU_pcTimerGetNameImpl
     MPU_pcTimerGetName_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_pcTimerGetName
 /*-----------------------------------------------------------*/
 
@@ -761,12 +710,11 @@ MPU_vTimerSetReloadMode:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTimerSetReloadMode_Unpriv
     MPU_vTimerSetReloadMode_Priv:
-        pop {r0}
         b MPU_vTimerSetReloadModeImpl
     MPU_vTimerSetReloadMode_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vTimerSetReloadMode
 /*-----------------------------------------------------------*/
 
@@ -775,12 +723,11 @@ MPU_xTimerGetReloadMode:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerGetReloadMode_Unpriv
     MPU_xTimerGetReloadMode_Priv:
-        pop {r0}
         b MPU_xTimerGetReloadModeImpl
     MPU_xTimerGetReloadMode_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerGetReloadMode
 /*-----------------------------------------------------------*/
 
@@ -789,12 +736,11 @@ MPU_uxTimerGetReloadMode:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTimerGetReloadMode_Unpriv
     MPU_uxTimerGetReloadMode_Priv:
-        pop {r0}
         b MPU_uxTimerGetReloadModeImpl
     MPU_uxTimerGetReloadMode_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxTimerGetReloadMode
 /*-----------------------------------------------------------*/
 
@@ -803,12 +749,11 @@ MPU_xTimerGetPeriod:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerGetPeriod_Unpriv
     MPU_xTimerGetPeriod_Priv:
-        pop {r0}
         b MPU_xTimerGetPeriodImpl
     MPU_xTimerGetPeriod_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerGetPeriod
 /*-----------------------------------------------------------*/
 
@@ -817,12 +762,11 @@ MPU_xTimerGetExpiryTime:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerGetExpiryTime_Unpriv
     MPU_xTimerGetExpiryTime_Priv:
-        pop {r0}
         b MPU_xTimerGetExpiryTimeImpl
     MPU_xTimerGetExpiryTime_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xTimerGetExpiryTime
 /*-----------------------------------------------------------*/
 
@@ -831,12 +775,11 @@ MPU_xEventGroupWaitBitsEntry:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xEventGroupWaitBits_Unpriv
     MPU_xEventGroupWaitBits_Priv:
-        pop {r0}
         b MPU_xEventGroupWaitBitsImpl
     MPU_xEventGroupWaitBits_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xEventGroupWaitBits
 /*-----------------------------------------------------------*/
 
@@ -845,12 +788,11 @@ MPU_xEventGroupClearBits:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xEventGroupClearBits_Unpriv
     MPU_xEventGroupClearBits_Priv:
-        pop {r0}
         b MPU_xEventGroupClearBitsImpl
     MPU_xEventGroupClearBits_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xEventGroupClearBits
 /*-----------------------------------------------------------*/
 
@@ -859,12 +801,11 @@ MPU_xEventGroupSetBits:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xEventGroupSetBits_Unpriv
     MPU_xEventGroupSetBits_Priv:
-        pop {r0}
         b MPU_xEventGroupSetBitsImpl
     MPU_xEventGroupSetBits_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xEventGroupSetBits
 /*-----------------------------------------------------------*/
 
@@ -873,12 +814,11 @@ MPU_xEventGroupSync:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xEventGroupSync_Unpriv
     MPU_xEventGroupSync_Priv:
-        pop {r0}
         b MPU_xEventGroupSyncImpl
     MPU_xEventGroupSync_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xEventGroupSync
 /*-----------------------------------------------------------*/
 
@@ -887,12 +827,11 @@ MPU_uxEventGroupGetNumber:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxEventGroupGetNumber_Unpriv
     MPU_uxEventGroupGetNumber_Priv:
-        pop {r0}
         b MPU_uxEventGroupGetNumberImpl
     MPU_uxEventGroupGetNumber_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_uxEventGroupGetNumber
 /*-----------------------------------------------------------*/
 
@@ -901,12 +840,11 @@ MPU_vEventGroupSetNumber:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vEventGroupSetNumber_Unpriv
     MPU_vEventGroupSetNumber_Priv:
-        pop {r0}
         b MPU_vEventGroupSetNumberImpl
     MPU_vEventGroupSetNumber_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_vEventGroupSetNumber
 /*-----------------------------------------------------------*/
 
@@ -915,12 +853,11 @@ MPU_xStreamBufferSend:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferSend_Unpriv
     MPU_xStreamBufferSend_Priv:
-        pop {r0}
         b MPU_xStreamBufferSendImpl
     MPU_xStreamBufferSend_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferSend
 /*-----------------------------------------------------------*/
 
@@ -929,12 +866,11 @@ MPU_xStreamBufferReceive:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferReceive_Unpriv
     MPU_xStreamBufferReceive_Priv:
-        pop {r0}
         b MPU_xStreamBufferReceiveImpl
     MPU_xStreamBufferReceive_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferReceive
 /*-----------------------------------------------------------*/
 
@@ -943,12 +879,11 @@ MPU_xStreamBufferIsFull:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferIsFull_Unpriv
     MPU_xStreamBufferIsFull_Priv:
-        pop {r0}
         b MPU_xStreamBufferIsFullImpl
     MPU_xStreamBufferIsFull_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferIsFull
 /*-----------------------------------------------------------*/
 
@@ -957,12 +892,11 @@ MPU_xStreamBufferIsEmpty:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferIsEmpty_Unpriv
     MPU_xStreamBufferIsEmpty_Priv:
-        pop {r0}
         b MPU_xStreamBufferIsEmptyImpl
     MPU_xStreamBufferIsEmpty_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferIsEmpty
 /*-----------------------------------------------------------*/
 
@@ -971,12 +905,11 @@ MPU_xStreamBufferSpacesAvailable:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferSpacesAvailable_Unpriv
     MPU_xStreamBufferSpacesAvailable_Priv:
-        pop {r0}
         b MPU_xStreamBufferSpacesAvailableImpl
     MPU_xStreamBufferSpacesAvailable_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferSpacesAvailable
 /*-----------------------------------------------------------*/
 
@@ -985,12 +918,11 @@ MPU_xStreamBufferBytesAvailable:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferBytesAvailable_Unpriv
     MPU_xStreamBufferBytesAvailable_Priv:
-        pop {r0}
         b MPU_xStreamBufferBytesAvailableImpl
     MPU_xStreamBufferBytesAvailable_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferBytesAvailable
 /*-----------------------------------------------------------*/
 
@@ -999,12 +931,11 @@ MPU_xStreamBufferSetTriggerLevel:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferSetTriggerLevel_Unpriv
     MPU_xStreamBufferSetTriggerLevel_Priv:
-        pop {r0}
         b MPU_xStreamBufferSetTriggerLevelImpl
     MPU_xStreamBufferSetTriggerLevel_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel
 /*-----------------------------------------------------------*/
 
@@ -1013,12 +944,11 @@ MPU_xStreamBufferNextMessageLengthBytes:
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv
     MPU_xStreamBufferNextMessageLengthBytes_Priv:
-        pop {r0}
         b MPU_xStreamBufferNextMessageLengthBytesImpl
     MPU_xStreamBufferNextMessageLengthBytes_Unpriv:
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes
 /*-----------------------------------------------------------*/
 
diff --git a/portable/RVDS/ARM_CM4_MPU/mpu_wrappers_v2_asm.c b/portable/RVDS/ARM_CM4_MPU/mpu_wrappers_v2_asm.c
index fb04f194d..3a41d8d31 100644
--- a/portable/RVDS/ARM_CM4_MPU/mpu_wrappers_v2_asm.c
+++ b/portable/RVDS/ARM_CM4_MPU/mpu_wrappers_v2_asm.c
@@ -60,12 +60,11 @@ __asm BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskDelayUntil_Unpriv
 MPU_xTaskDelayUntil_Priv
-        pop {r0}
         b MPU_xTaskDelayUntilImpl
 MPU_xTaskDelayUntil_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_xTaskDelayUntil
 }
 
@@ -84,12 +83,11 @@ __asm BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CA
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskAbortDelay_Unpriv
 MPU_xTaskAbortDelay_Priv
-        pop {r0}
         b MPU_xTaskAbortDelayImpl
 MPU_xTaskAbortDelay_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_xTaskAbortDelay
 }
 
@@ -108,12 +106,11 @@ __asm void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* FREERTOS_SYSTEM_C
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskDelay_Unpriv
 MPU_vTaskDelay_Priv
-        pop {r0}
         b MPU_vTaskDelayImpl
 MPU_vTaskDelay_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_vTaskDelay
 }
 
@@ -132,12 +129,11 @@ __asm UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* FREERTOS_
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTaskPriorityGet_Unpriv
 MPU_uxTaskPriorityGet_Priv
-        pop {r0}
         b MPU_uxTaskPriorityGetImpl
 MPU_uxTaskPriorityGet_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_uxTaskPriorityGet
 }
 
@@ -156,12 +152,11 @@ __asm eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_eTaskGetState_Unpriv
 MPU_eTaskGetState_Priv
-        pop {r0}
         b MPU_eTaskGetStateImpl
 MPU_eTaskGetState_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_eTaskGetState
 }
 
@@ -186,12 +181,11 @@ __asm void MPU_vTaskGetInfo( TaskHandle_t xTask,
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskGetInfo_Unpriv
 MPU_vTaskGetInfo_Priv
-        pop {r0}
         b MPU_vTaskGetInfoImpl
 MPU_vTaskGetInfo_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_vTaskGetInfo
 }
 
@@ -210,12 +204,11 @@ __asm TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* FREERTOS_SYSTEM_CALL */
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGetIdleTaskHandle_Unpriv
 MPU_xTaskGetIdleTaskHandle_Priv
-        pop {r0}
         b MPU_xTaskGetIdleTaskHandleImpl
 MPU_xTaskGetIdleTaskHandle_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGetIdleTaskHandle
 }
 
@@ -234,12 +227,11 @@ __asm void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* FREERTOS_SYSTEM_CA
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskSuspend_Unpriv
 MPU_vTaskSuspend_Priv
-        pop {r0}
         b MPU_vTaskSuspendImpl
 MPU_vTaskSuspend_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_vTaskSuspend
 }
 
@@ -258,12 +250,11 @@ __asm void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* FREERTOS_SYSTEM_CALL
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskResume_Unpriv
 MPU_vTaskResume_Priv
-        pop {r0}
         b MPU_vTaskResumeImpl
 MPU_vTaskResume_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_vTaskResume
 }
 
@@ -280,12 +271,11 @@ __asm TickType_t MPU_xTaskGetTickCount( void ) /* FREERTOS_SYSTEM_CALL */
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGetTickCount_Unpriv
 MPU_xTaskGetTickCount_Priv
-        pop {r0}
         b MPU_xTaskGetTickCountImpl
 MPU_xTaskGetTickCount_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGetTickCount
 }
 /*-----------------------------------------------------------*/
@@ -300,12 +290,11 @@ __asm UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* FREERTOS_SYSTEM_CALL */
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTaskGetNumberOfTasks_Unpriv
 MPU_uxTaskGetNumberOfTasks_Priv
-        pop {r0}
         b MPU_uxTaskGetNumberOfTasksImpl
 MPU_uxTaskGetNumberOfTasks_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_uxTaskGetNumberOfTasks
 }
 /*-----------------------------------------------------------*/
@@ -322,12 +311,11 @@ __asm configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGetRunTimeCounter_Unpriv
 MPU_ulTaskGetRunTimeCounter_Priv
-        pop {r0}
         b MPU_ulTaskGetRunTimeCounterImpl
 MPU_ulTaskGetRunTimeCounter_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGetRunTimeCounter
 }
 
@@ -346,12 +334,11 @@ __asm configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGetRunTimePercent_Unpriv
 MPU_ulTaskGetRunTimePercent_Priv
-        pop {r0}
         b MPU_ulTaskGetRunTimePercentImpl
 MPU_ulTaskGetRunTimePercent_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGetRunTimePercent
 }
 
@@ -370,12 +357,11 @@ __asm configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* FRE
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGetIdleRunTimePercent_Unpriv
 MPU_ulTaskGetIdleRunTimePercent_Priv
-        pop {r0}
         b MPU_ulTaskGetIdleRunTimePercentImpl
 MPU_ulTaskGetIdleRunTimePercent_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent
 }
 
@@ -394,12 +380,11 @@ __asm configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* FRE
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv
 MPU_ulTaskGetIdleRunTimeCounter_Priv
-        pop {r0}
         b MPU_ulTaskGetIdleRunTimeCounterImpl
 MPU_ulTaskGetIdleRunTimeCounter_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter
 }
 
@@ -420,12 +405,11 @@ __asm void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskSetApplicationTaskTag_Unpriv
 MPU_vTaskSetApplicationTaskTag_Priv
-        pop {r0}
         b MPU_vTaskSetApplicationTaskTagImpl
 MPU_vTaskSetApplicationTaskTag_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_vTaskSetApplicationTaskTag
 }
 
@@ -444,12 +428,11 @@ __asm TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /*
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGetApplicationTaskTag_Unpriv
 MPU_xTaskGetApplicationTaskTag_Priv
-        pop {r0}
         b MPU_xTaskGetApplicationTaskTagImpl
 MPU_xTaskGetApplicationTaskTag_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGetApplicationTaskTag
 }
 
@@ -472,12 +455,11 @@ __asm void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv
 MPU_vTaskSetThreadLocalStoragePointer_Priv
-        pop {r0}
         b MPU_vTaskSetThreadLocalStoragePointerImpl
 MPU_vTaskSetThreadLocalStoragePointer_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer
 }
 
@@ -498,12 +480,11 @@ __asm void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv
 MPU_pvTaskGetThreadLocalStoragePointer_Priv
-        pop {r0}
         b MPU_pvTaskGetThreadLocalStoragePointerImpl
 MPU_pvTaskGetThreadLocalStoragePointer_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer
 }
 
@@ -526,12 +507,11 @@ __asm UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArr
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTaskGetSystemState_Unpriv
 MPU_uxTaskGetSystemState_Priv
-        pop {r0}
         b MPU_uxTaskGetSystemStateImpl
 MPU_uxTaskGetSystemState_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_uxTaskGetSystemState
 }
 
@@ -550,12 +530,11 @@ __asm UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* FREER
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTaskGetStackHighWaterMark_Unpriv
 MPU_uxTaskGetStackHighWaterMark_Priv
-        pop {r0}
         b MPU_uxTaskGetStackHighWaterMarkImpl
 MPU_uxTaskGetStackHighWaterMark_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark
 }
 
@@ -574,12 +553,11 @@ __asm configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTas
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTaskGetStackHighWaterMark2_Unpriv
 MPU_uxTaskGetStackHighWaterMark2_Priv
-        pop {r0}
         b MPU_uxTaskGetStackHighWaterMark2Impl
 MPU_uxTaskGetStackHighWaterMark2_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2
 }
 
@@ -598,12 +576,11 @@ __asm TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* FREERTOS_SYSTEM_CALL
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGetCurrentTaskHandle_Unpriv
 MPU_xTaskGetCurrentTaskHandle_Priv
-        pop {r0}
         b MPU_xTaskGetCurrentTaskHandleImpl
 MPU_xTaskGetCurrentTaskHandle_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle
 }
 
@@ -622,12 +599,11 @@ __asm BaseType_t MPU_xTaskGetSchedulerState( void ) /* FREERTOS_SYSTEM_CALL */
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGetSchedulerState_Unpriv
 MPU_xTaskGetSchedulerState_Priv
-        pop {r0}
         b MPU_xTaskGetSchedulerStateImpl
 MPU_xTaskGetSchedulerState_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGetSchedulerState
 }
 
@@ -644,12 +620,11 @@ __asm void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* FREERTOS_S
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTaskSetTimeOutState_Unpriv
 MPU_vTaskSetTimeOutState_Priv
-        pop {r0}
         b MPU_vTaskSetTimeOutStateImpl
 MPU_vTaskSetTimeOutState_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_vTaskSetTimeOutState
 }
 /*-----------------------------------------------------------*/
@@ -666,12 +641,11 @@ __asm BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskCheckForTimeOut_Unpriv
 MPU_xTaskCheckForTimeOut_Priv
-        pop {r0}
         b MPU_xTaskCheckForTimeOutImpl
 MPU_xTaskCheckForTimeOut_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_xTaskCheckForTimeOut
 }
 /*-----------------------------------------------------------*/
@@ -688,12 +662,11 @@ __asm BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t *
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGenericNotify_Unpriv
 MPU_xTaskGenericNotify_Priv
-        pop {r0}
         b MPU_xTaskGenericNotifyImpl
 MPU_xTaskGenericNotify_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGenericNotify
 }
 
@@ -712,12 +685,11 @@ __asm BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitPa
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGenericNotifyWait_Unpriv
 MPU_xTaskGenericNotifyWait_Priv
-        pop {r0}
         b MPU_xTaskGenericNotifyWaitImpl
 MPU_xTaskGenericNotifyWait_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGenericNotifyWait
 }
 
@@ -740,12 +712,11 @@ __asm uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGenericNotifyTake_Unpriv
 MPU_ulTaskGenericNotifyTake_Priv
-        pop {r0}
         b MPU_ulTaskGenericNotifyTakeImpl
 MPU_ulTaskGenericNotifyTake_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGenericNotifyTake
 }
 
@@ -766,12 +737,11 @@ __asm BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTaskGenericNotifyStateClear_Unpriv
 MPU_xTaskGenericNotifyStateClear_Priv
-        pop {r0}
         b MPU_xTaskGenericNotifyStateClearImpl
 MPU_xTaskGenericNotifyStateClear_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_xTaskGenericNotifyStateClear
 }
 
@@ -794,12 +764,11 @@ __asm uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_ulTaskGenericNotifyValueClear_Unpriv
 MPU_ulTaskGenericNotifyValueClear_Priv
-        pop {r0}
         b MPU_ulTaskGenericNotifyValueClearImpl
 MPU_ulTaskGenericNotifyValueClear_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear
 }
 
@@ -822,12 +791,11 @@ __asm BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueGenericSend_Unpriv
 MPU_xQueueGenericSend_Priv
-        pop {r0}
         b MPU_xQueueGenericSendImpl
 MPU_xQueueGenericSend_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_xQueueGenericSend
 }
 /*-----------------------------------------------------------*/
@@ -842,12 +810,11 @@ __asm UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* FR
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxQueueMessagesWaiting_Unpriv
 MPU_uxQueueMessagesWaiting_Priv
-        pop {r0}
         b MPU_uxQueueMessagesWaitingImpl
 MPU_uxQueueMessagesWaiting_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_uxQueueMessagesWaiting
 }
 /*-----------------------------------------------------------*/
@@ -862,12 +829,11 @@ __asm UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* FR
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxQueueSpacesAvailable_Unpriv
 MPU_uxQueueSpacesAvailable_Priv
-        pop {r0}
         b MPU_uxQueueSpacesAvailableImpl
 MPU_uxQueueSpacesAvailable_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_uxQueueSpacesAvailable
 }
 /*-----------------------------------------------------------*/
@@ -886,12 +852,11 @@ __asm BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueReceive_Unpriv
 MPU_xQueueReceive_Priv
-        pop {r0}
         b MPU_xQueueReceiveImpl
 MPU_xQueueReceive_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_xQueueReceive
 }
 /*-----------------------------------------------------------*/
@@ -910,12 +875,11 @@ __asm BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueuePeek_Unpriv
 MPU_xQueuePeek_Priv
-        pop {r0}
         b MPU_xQueuePeekImpl
 MPU_xQueuePeek_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_xQueuePeek
 }
 /*-----------------------------------------------------------*/
@@ -932,12 +896,11 @@ __asm BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueSemaphoreTake_Unpriv
 MPU_xQueueSemaphoreTake_Priv
-        pop {r0}
         b MPU_xQueueSemaphoreTakeImpl
 MPU_xQueueSemaphoreTake_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_xQueueSemaphoreTake
 }
 /*-----------------------------------------------------------*/
@@ -954,12 +917,11 @@ __asm TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* FREER
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueGetMutexHolder_Unpriv
 MPU_xQueueGetMutexHolder_Priv
-        pop {r0}
         b MPU_xQueueGetMutexHolderImpl
 MPU_xQueueGetMutexHolder_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_xQueueGetMutexHolder
 }
 
@@ -980,12 +942,11 @@ __asm BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueTakeMutexRecursive_Unpriv
 MPU_xQueueTakeMutexRecursive_Priv
-        pop {r0}
         b MPU_xQueueTakeMutexRecursiveImpl
 MPU_xQueueTakeMutexRecursive_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_xQueueTakeMutexRecursive
 }
 
@@ -1004,12 +965,11 @@ __asm BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* FREERT
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueGiveMutexRecursive_Unpriv
 MPU_xQueueGiveMutexRecursive_Priv
-        pop {r0}
         b MPU_xQueueGiveMutexRecursiveImpl
 MPU_xQueueGiveMutexRecursive_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_xQueueGiveMutexRecursive
 }
 
@@ -1030,12 +990,11 @@ __asm QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueSelectFromSet_Unpriv
 MPU_xQueueSelectFromSet_Priv
-        pop {r0}
         b MPU_xQueueSelectFromSetImpl
 MPU_xQueueSelectFromSet_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_xQueueSelectFromSet
 }
 
@@ -1056,12 +1015,11 @@ __asm BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xQueueAddToSet_Unpriv
 MPU_xQueueAddToSet_Priv
-        pop {r0}
         b MPU_xQueueAddToSetImpl
 MPU_xQueueAddToSet_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_xQueueAddToSet
 }
 
@@ -1082,12 +1040,11 @@ __asm void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vQueueAddToRegistry_Unpriv
 MPU_vQueueAddToRegistry_Priv
-        pop {r0}
         b MPU_vQueueAddToRegistryImpl
 MPU_vQueueAddToRegistry_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_vQueueAddToRegistry
 }
 
@@ -1106,12 +1063,11 @@ __asm void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vQueueUnregisterQueue_Unpriv
 MPU_vQueueUnregisterQueue_Priv
-        pop {r0}
         b MPU_vQueueUnregisterQueueImpl
 MPU_vQueueUnregisterQueue_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_vQueueUnregisterQueue
 }
 
@@ -1130,12 +1086,11 @@ __asm const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* FREERTOS_SYSTEM
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_pcQueueGetName_Unpriv
 MPU_pcQueueGetName_Priv
-        pop {r0}
         b MPU_pcQueueGetNameImpl
 MPU_pcQueueGetName_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_pcQueueGetName
 }
 
@@ -1154,12 +1109,11 @@ __asm void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* FREERTOS_SYS
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_pvTimerGetTimerID_Unpriv
 MPU_pvTimerGetTimerID_Priv
-        pop {r0}
         b MPU_pvTimerGetTimerIDImpl
 MPU_pvTimerGetTimerID_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_pvTimerGetTimerID
 }
 
@@ -1180,12 +1134,11 @@ __asm void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTimerSetTimerID_Unpriv
 MPU_vTimerSetTimerID_Priv
-        pop {r0}
         b MPU_vTimerSetTimerIDImpl
 MPU_vTimerSetTimerID_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_vTimerSetTimerID
 }
 
@@ -1204,12 +1157,11 @@ __asm BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* FREERTOS_SYS
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerIsTimerActive_Unpriv
 MPU_xTimerIsTimerActive_Priv
-        pop {r0}
         b MPU_xTimerIsTimerActiveImpl
 MPU_xTimerIsTimerActive_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_xTimerIsTimerActive
 }
 
@@ -1228,12 +1180,11 @@ __asm TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* FREERTOS_SYSTEM
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv
 MPU_xTimerGetTimerDaemonTaskHandle_Priv
-        pop {r0}
         b MPU_xTimerGetTimerDaemonTaskHandleImpl
 MPU_xTimerGetTimerDaemonTaskHandle_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle
 }
 
@@ -1252,12 +1203,11 @@ __asm BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericComma
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerGenericCommandFromTask_Unpriv
 MPU_xTimerGenericCommandFromTask_Priv
-        pop {r0}
         b MPU_xTimerGenericCommandFromTaskImpl
 MPU_xTimerGenericCommandFromTask_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_xTimerGenericCommandFromTask
 }
 
@@ -1276,12 +1226,11 @@ __asm const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_pcTimerGetName_Unpriv
 MPU_pcTimerGetName_Priv
-        pop {r0}
         b MPU_pcTimerGetNameImpl
 MPU_pcTimerGetName_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_pcTimerGetName
 }
 
@@ -1302,12 +1251,11 @@ __asm void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vTimerSetReloadMode_Unpriv
 MPU_vTimerSetReloadMode_Priv
-        pop {r0}
         b MPU_vTimerSetReloadModeImpl
 MPU_vTimerSetReloadMode_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_vTimerSetReloadMode
 }
 
@@ -1326,12 +1274,11 @@ __asm BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* FREERTOS_SYS
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerGetReloadMode_Unpriv
 MPU_xTimerGetReloadMode_Priv
-        pop {r0}
         b MPU_xTimerGetReloadModeImpl
 MPU_xTimerGetReloadMode_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_xTimerGetReloadMode
 }
 
@@ -1350,12 +1297,11 @@ __asm UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* FREERTOS_S
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxTimerGetReloadMode_Unpriv
 MPU_uxTimerGetReloadMode_Priv
-        pop {r0}
         b MPU_uxTimerGetReloadModeImpl
 MPU_uxTimerGetReloadMode_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_uxTimerGetReloadMode
 }
 
@@ -1374,12 +1320,11 @@ __asm TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerGetPeriod_Unpriv
 MPU_xTimerGetPeriod_Priv
-        pop {r0}
         b MPU_xTimerGetPeriodImpl
 MPU_xTimerGetPeriod_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_xTimerGetPeriod
 }
 
@@ -1398,12 +1343,11 @@ __asm TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* FREERTOS_SYS
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xTimerGetExpiryTime_Unpriv
 MPU_xTimerGetExpiryTime_Priv
-        pop {r0}
         b MPU_xTimerGetExpiryTimeImpl
 MPU_xTimerGetExpiryTime_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_xTimerGetExpiryTime
 }
 
@@ -1420,12 +1364,11 @@ __asm EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xEventGroupWaitBits_Unpriv
 MPU_xEventGroupWaitBits_Priv
-        pop {r0}
         b MPU_xEventGroupWaitBitsImpl
 MPU_xEventGroupWaitBits_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_xEventGroupWaitBits
 }
 /*-----------------------------------------------------------*/
@@ -1442,12 +1385,11 @@ __asm EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xEventGroupClearBits_Unpriv
 MPU_xEventGroupClearBits_Priv
-        pop {r0}
         b MPU_xEventGroupClearBitsImpl
 MPU_xEventGroupClearBits_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_xEventGroupClearBits
 }
 /*-----------------------------------------------------------*/
@@ -1464,12 +1406,11 @@ __asm EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xEventGroupSetBits_Unpriv
 MPU_xEventGroupSetBits_Priv
-        pop {r0}
         b MPU_xEventGroupSetBitsImpl
 MPU_xEventGroupSetBits_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_xEventGroupSetBits
 }
 /*-----------------------------------------------------------*/
@@ -1490,12 +1431,11 @@ __asm EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xEventGroupSync_Unpriv
 MPU_xEventGroupSync_Priv
-        pop {r0}
         b MPU_xEventGroupSyncImpl
 MPU_xEventGroupSync_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_xEventGroupSync
 }
 /*-----------------------------------------------------------*/
@@ -1512,12 +1452,11 @@ __asm UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* FREERTOS_SY
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_uxEventGroupGetNumber_Unpriv
 MPU_uxEventGroupGetNumber_Priv
-        pop {r0}
         b MPU_uxEventGroupGetNumberImpl
 MPU_uxEventGroupGetNumber_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_uxEventGroupGetNumber
 }
 
@@ -1538,12 +1477,11 @@ __asm void MPU_vEventGroupSetNumber( void * xEventGroup,
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_vEventGroupSetNumber_Unpriv
 MPU_vEventGroupSetNumber_Priv
-        pop {r0}
         b MPU_vEventGroupSetNumberImpl
 MPU_vEventGroupSetNumber_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_vEventGroupSetNumber
 }
 
@@ -1566,12 +1504,11 @@ __asm size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferSend_Unpriv
 MPU_xStreamBufferSend_Priv
-        pop {r0}
         b MPU_xStreamBufferSendImpl
 MPU_xStreamBufferSend_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferSend
 }
 /*-----------------------------------------------------------*/
@@ -1592,12 +1529,11 @@ __asm size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferReceive_Unpriv
 MPU_xStreamBufferReceive_Priv
-        pop {r0}
         b MPU_xStreamBufferReceiveImpl
 MPU_xStreamBufferReceive_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferReceive
 }
 /*-----------------------------------------------------------*/
@@ -1612,12 +1548,11 @@ __asm BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferIsFull_Unpriv
 MPU_xStreamBufferIsFull_Priv
-        pop {r0}
         b MPU_xStreamBufferIsFullImpl
 MPU_xStreamBufferIsFull_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferIsFull
 }
 /*-----------------------------------------------------------*/
@@ -1632,12 +1567,11 @@ __asm BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer )
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferIsEmpty_Unpriv
 MPU_xStreamBufferIsEmpty_Priv
-        pop {r0}
         b MPU_xStreamBufferIsEmptyImpl
 MPU_xStreamBufferIsEmpty_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferIsEmpty
 }
 /*-----------------------------------------------------------*/
@@ -1652,12 +1586,11 @@ __asm size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffe
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferSpacesAvailable_Unpriv
 MPU_xStreamBufferSpacesAvailable_Priv
-        pop {r0}
         b MPU_xStreamBufferSpacesAvailableImpl
 MPU_xStreamBufferSpacesAvailable_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferSpacesAvailable
 }
 /*-----------------------------------------------------------*/
@@ -1672,12 +1605,11 @@ __asm size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferBytesAvailable_Unpriv
 MPU_xStreamBufferBytesAvailable_Priv
-        pop {r0}
         b MPU_xStreamBufferBytesAvailableImpl
 MPU_xStreamBufferBytesAvailable_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferBytesAvailable
 }
 /*-----------------------------------------------------------*/
@@ -1694,12 +1626,11 @@ __asm BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamB
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferSetTriggerLevel_Unpriv
 MPU_xStreamBufferSetTriggerLevel_Priv
-        pop {r0}
         b MPU_xStreamBufferSetTriggerLevelImpl
 MPU_xStreamBufferSetTriggerLevel_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel
 }
 /*-----------------------------------------------------------*/
@@ -1714,12 +1645,11 @@ __asm size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStre
     push {r0}
     mrs r0, control
     tst r0, #1
+    pop {r0}
     bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv
 MPU_xStreamBufferNextMessageLengthBytes_Priv
-        pop {r0}
         b MPU_xStreamBufferNextMessageLengthBytesImpl
 MPU_xStreamBufferNextMessageLengthBytes_Unpriv
-        pop {r0}
         svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes
 }
 /*-----------------------------------------------------------*/

From 345a86d49bca4f278ecb38516f675f3732255267 Mon Sep 17 00:00:00 2001
From: Soren Ptak <ptaksoren@gmail.com>
Date: Tue, 26 Mar 2024 13:25:07 -0700
Subject: [PATCH 238/424] ARM CM0+ MPU Port (#1005)

* Add MPU Support to the ARM CM0+ GCC Port.
* Co-authored by @aggarg
---
 .github/.cSpellWords.txt                   |    1 +
 portable/GCC/ARM_CM0/mpu_wrappers_v2_asm.c | 2217 ++++++++++++++++++++
 portable/GCC/ARM_CM0/port.c                | 1694 +++++++++++----
 portable/GCC/ARM_CM0/portasm.c             |  523 +++++
 portable/GCC/ARM_CM0/portasm.h             |   99 +
 portable/GCC/ARM_CM0/portmacro.h           |  343 ++-
 6 files changed, 4458 insertions(+), 419 deletions(-)
 create mode 100644 portable/GCC/ARM_CM0/mpu_wrappers_v2_asm.c
 create mode 100644 portable/GCC/ARM_CM0/portasm.c
 create mode 100644 portable/GCC/ARM_CM0/portasm.h

diff --git a/.github/.cSpellWords.txt b/.github/.cSpellWords.txt
index c41a05015..0ba0be7c5 100644
--- a/.github/.cSpellWords.txt
+++ b/.github/.cSpellWords.txt
@@ -634,6 +634,7 @@ PREB
 PRIA
 Prioritised
 PRIS
+PRIVDEFENA
 PROCDLY
 PRODH
 PRODL
diff --git a/portable/GCC/ARM_CM0/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM0/mpu_wrappers_v2_asm.c
new file mode 100644
index 000000000..cd7be632b
--- /dev/null
+++ b/portable/GCC/ARM_CM0/mpu_wrappers_v2_asm.c
@@ -0,0 +1,2217 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers.  That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+#include "timers.h"
+#include "event_groups.h"
+#include "stream_buffer.h"
+#include "mpu_prototypes.h"
+#include "mpu_syscall_numbers.h"
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+    #if ( INCLUDE_xTaskDelayUntil == 1 )
+
+        BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
+                                        const TickType_t xTimeIncrement ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
+                                        const TickType_t xTimeIncrement ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskDelayUntilImpl                       \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xTaskDelayUntil_Unpriv                        \n"
+                " MPU_xTaskDelayUntil_Priv:                             \n"
+                "     push {lr}                                         \n"
+                "     blx MPU_xTaskDelayUntilImpl                       \n"
+                "     pop {pc}                                          \n"
+                " MPU_xTaskDelayUntil_Unpriv:                           \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory"
+            );
+        }
+
+    #endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( INCLUDE_xTaskAbortDelay == 1 )
+
+        BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskAbortDelayImpl                       \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xTaskAbortDelay_Unpriv                        \n"
+                " MPU_xTaskAbortDelay_Priv:                             \n"
+                "     push {lr}                                         \n"
+                "     blx MPU_xTaskAbortDelayImpl                       \n"
+                "     pop {pc}                                          \n"
+                " MPU_xTaskAbortDelay_Unpriv:                           \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory"
+            );
+        }
+
+    #endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( INCLUDE_vTaskDelay == 1 )
+
+        void MPU_vTaskDelay( const TickType_t xTicksToDelay ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskDelayImpl                            \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_vTaskDelay_Unpriv                             \n"
+                " MPU_vTaskDelay_Priv:                                  \n"
+                "     push {lr}                                         \n"
+                "     blx MPU_vTaskDelayImpl                            \n"
+                "     pop {pc}                                          \n"
+                " MPU_vTaskDelay_Unpriv:                                \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory"
+            );
+        }
+
+    #endif /* if ( INCLUDE_vTaskDelay == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( INCLUDE_uxTaskPriorityGet == 1 )
+
+        UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskPriorityGetImpl                     \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_uxTaskPriorityGet_Unpriv                      \n"
+                " MPU_uxTaskPriorityGet_Priv:                           \n"
+                "     push {lr}                                         \n"
+                "     blx MPU_uxTaskPriorityGetImpl                     \n"
+                "     pop {pc}                                          \n"
+                " MPU_uxTaskPriorityGet_Unpriv:                         \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory"
+            );
+        }
+
+    #endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( INCLUDE_eTaskGetState == 1 )
+
+        eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_eTaskGetStateImpl                         \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_eTaskGetState_Unpriv                          \n"
+                " MPU_eTaskGetState_Priv:                               \n"
+                "     push {lr}                                         \n"
+                "     blx MPU_eTaskGetStateImpl                         \n"
+                "     pop {pc}                                          \n"
+                " MPU_eTaskGetState_Unpriv:                             \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory"
+            );
+        }
+
+    #endif /* if ( INCLUDE_eTaskGetState == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TRACE_FACILITY == 1 )
+
+        void MPU_vTaskGetInfo( TaskHandle_t xTask,
+                               TaskStatus_t * pxTaskStatus,
+                               BaseType_t xGetFreeStackSpace,
+                               eTaskState eState ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vTaskGetInfo( TaskHandle_t xTask,
+                               TaskStatus_t * pxTaskStatus,
+                               BaseType_t xGetFreeStackSpace,
+                               eTaskState eState ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskGetInfoImpl                          \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_vTaskGetInfo_Unpriv                           \n"
+                " MPU_vTaskGetInfo_Priv:                                \n"
+                "     push {lr}                                         \n"
+                "     blx MPU_vTaskGetInfoImpl                          \n"
+                "     pop {pc}                                          \n"
+                " MPU_vTaskGetInfo_Unpriv:                              \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
+
+        TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetIdleTaskHandleImpl                \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xTaskGetIdleTaskHandle_Unpriv                 \n"
+                " MPU_xTaskGetIdleTaskHandle_Priv:                      \n"
+                "     push {lr}                                         \n"
+                "     blx MPU_xTaskGetIdleTaskHandleImpl                \n"
+                "     pop {pc}                                          \n"
+                " MPU_xTaskGetIdleTaskHandle_Unpriv:                    \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory"
+            );
+        }
+
+    #endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( INCLUDE_vTaskSuspend == 1 )
+
+        void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskSuspendImpl                          \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_vTaskSuspend_Unpriv                           \n"
+                " MPU_vTaskSuspend_Priv:                                \n"
+                "     push {lr}                                         \n"
+                "     blx MPU_vTaskSuspendImpl                          \n"
+                "     pop {pc}                                          \n"
+                " MPU_vTaskSuspend_Unpriv:                              \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory"
+            );
+        }
+
+    #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( INCLUDE_vTaskSuspend == 1 )
+
+        void MPU_vTaskResume( TaskHandle_t xTaskToResume ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskResumeImpl                           \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_vTaskResume_Unpriv                            \n"
+                " MPU_vTaskResume_Priv:                                 \n"
+                "     push {lr}                                         \n"
+                "     blx MPU_vTaskResumeImpl                           \n"
+                "     pop {pc}                                          \n"
+                " MPU_vTaskResume_Unpriv:                               \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_vTaskResume ) : "memory"
+            );
+        }
+
+    #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
+/*-----------------------------------------------------------*/
+
+    TickType_t MPU_xTaskGetTickCount( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+    TickType_t MPU_xTaskGetTickCount( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xTaskGetTickCountImpl                     \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
+            " bne MPU_xTaskGetTickCount_Unpriv                      \n"
+            " MPU_xTaskGetTickCount_Priv:                           \n"
+            "     push {lr}                                         \n"
+            "     blx MPU_xTaskGetTickCountImpl                     \n"
+            "     pop {pc}                                          \n"
+            " MPU_xTaskGetTickCount_Unpriv:                         \n"
+            "     svc %0                                            \n"
+            "                                                       \n"
+            : : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory"
+        );
+    }
+/*-----------------------------------------------------------*/
+
+    UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+    UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_uxTaskGetNumberOfTasksImpl                \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
+            " bne MPU_uxTaskGetNumberOfTasks_Unpriv                 \n"
+            " MPU_uxTaskGetNumberOfTasks_Priv:                      \n"
+            "     push {lr}                                         \n"
+            "     blx MPU_uxTaskGetNumberOfTasksImpl                \n"
+            "     pop {pc}                                          \n"
+            " MPU_uxTaskGetNumberOfTasks_Unpriv:                    \n"
+            "     svc %0                                            \n"
+            "                                                       \n"
+            : : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory"
+        );
+    }
+/*-----------------------------------------------------------*/
+
+    #if ( configGENERATE_RUN_TIME_STATS == 1 )
+
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetRunTimeCounterImpl               \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_ulTaskGetRunTimeCounter_Unpriv                \n"
+                " MPU_ulTaskGetRunTimeCounter_Priv:                     \n"
+                "     push {lr}                                         \n"
+                "     blx MPU_ulTaskGetRunTimeCounterImpl               \n"
+                "     pop {pc}                                          \n"
+                " MPU_ulTaskGetRunTimeCounter_Unpriv:                   \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory"
+            );
+        }
+
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configGENERATE_RUN_TIME_STATS == 1 )
+
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetRunTimePercentImpl               \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_ulTaskGetRunTimePercent_Unpriv                \n"
+                " MPU_ulTaskGetRunTimePercent_Priv:                     \n"
+                "     push {lr}                                         \n"
+                "     blx MPU_ulTaskGetRunTimePercentImpl               \n"
+                "     pop {pc}                                          \n"
+                " MPU_ulTaskGetRunTimePercent_Unpriv:                   \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory"
+            );
+        }
+
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetIdleRunTimePercentImpl           \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv            \n"
+                " MPU_ulTaskGetIdleRunTimePercent_Priv:                 \n"
+                "     push {lr}                                         \n"
+                "     blx MPU_ulTaskGetIdleRunTimePercentImpl           \n"
+                "     pop {pc}                                          \n"
+                " MPU_ulTaskGetIdleRunTimePercent_Unpriv:               \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory"
+            );
+        }
+
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+    #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGetIdleRunTimeCounterImpl           \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv            \n"
+                " MPU_ulTaskGetIdleRunTimeCounter_Priv:                 \n"
+                "     push {lr}                                         \n"
+                "     blx MPU_ulTaskGetIdleRunTimeCounterImpl           \n"
+                "     pop {pc}                                          \n"
+                " MPU_ulTaskGetIdleRunTimeCounter_Unpriv:               \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory"
+            );
+        }
+
+    #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+        void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
+                                             TaskHookFunction_t pxHookFunction ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
+                                             TaskHookFunction_t pxHookFunction ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskSetApplicationTaskTagImpl            \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_vTaskSetApplicationTaskTag_Unpriv             \n"
+                " MPU_vTaskSetApplicationTaskTag_Priv:                  \n"
+                "     push {lr}                                         \n"
+                "     blx MPU_vTaskSetApplicationTaskTagImpl            \n"
+                "     pop {pc}                                          \n"
+                " MPU_vTaskSetApplicationTaskTag_Unpriv:                \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+        TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetApplicationTaskTagImpl            \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xTaskGetApplicationTaskTag_Unpriv             \n"
+                " MPU_xTaskGetApplicationTaskTag_Priv:                  \n"
+                "     push {lr}                                         \n"
+                "     blx MPU_xTaskGetApplicationTaskTagImpl            \n"
+                "     pop {pc}                                          \n"
+                " MPU_xTaskGetApplicationTaskTag_Unpriv:                \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+
+        void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
+                                                    BaseType_t xIndex,
+                                                    void * pvValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
+                                                    BaseType_t xIndex,
+                                                    void * pvValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTaskSetThreadLocalStoragePointerImpl     \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv      \n"
+                " MPU_vTaskSetThreadLocalStoragePointer_Priv:           \n"
+                "     push {lr}                                         \n"
+                "     blx MPU_vTaskSetThreadLocalStoragePointerImpl     \n"
+                "     pop {pc}                                          \n"
+                " MPU_vTaskSetThreadLocalStoragePointer_Unpriv:         \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory"
+            );
+        }
+
+    #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+
+        void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
+                                                       BaseType_t xIndex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
+                                                       BaseType_t xIndex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pvTaskGetThreadLocalStoragePointerImpl    \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv     \n"
+                " MPU_pvTaskGetThreadLocalStoragePointer_Priv:          \n"
+                "     push {lr}                                         \n"
+                "     blx MPU_pvTaskGetThreadLocalStoragePointerImpl    \n"
+                "     pop {pc}                                          \n"
+                " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:        \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory"
+            );
+        }
+
+    #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TRACE_FACILITY == 1 )
+
+        UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
+                                              const UBaseType_t uxArraySize,
+                                              configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
+                                              const UBaseType_t uxArraySize,
+                                              configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskGetSystemStateImpl                  \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_uxTaskGetSystemState_Unpriv                   \n"
+                " MPU_uxTaskGetSystemState_Priv:                        \n"
+                "     push {lr}                                         \n"
+                "     blx MPU_uxTaskGetSystemStateImpl                  \n"
+                "     pop {pc}                                          \n"
+                " MPU_uxTaskGetSystemState_Unpriv:                      \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
+
+        UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskGetStackHighWaterMarkImpl           \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_uxTaskGetStackHighWaterMark_Unpriv            \n"
+                " MPU_uxTaskGetStackHighWaterMark_Priv:                 \n"
+                "     push {lr}                                         \n"
+                "     blx MPU_uxTaskGetStackHighWaterMarkImpl           \n"
+                "     pop {pc}                                          \n"
+                " MPU_uxTaskGetStackHighWaterMark_Unpriv:               \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory"
+            );
+        }
+
+    #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
+
+        configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTaskGetStackHighWaterMark2Impl          \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv           \n"
+                " MPU_uxTaskGetStackHighWaterMark2_Priv:                \n"
+                "     push {lr}                                         \n"
+                "     blx MPU_uxTaskGetStackHighWaterMark2Impl          \n"
+                "     pop {pc}                                          \n"
+                " MPU_uxTaskGetStackHighWaterMark2_Unpriv:              \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory"
+            );
+        }
+
+    #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
+
+        TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetCurrentTaskHandleImpl             \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xTaskGetCurrentTaskHandle_Unpriv              \n"
+                " MPU_xTaskGetCurrentTaskHandle_Priv:                   \n"
+                "     push {lr}                                         \n"
+                "     blx MPU_xTaskGetCurrentTaskHandleImpl             \n"
+                "     pop {pc}                                          \n"
+                " MPU_xTaskGetCurrentTaskHandle_Unpriv:                 \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory"
+            );
+        }
+
+    #endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+    #if ( INCLUDE_xTaskGetSchedulerState == 1 )
+
+        BaseType_t MPU_xTaskGetSchedulerState( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTaskGetSchedulerState( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGetSchedulerStateImpl                \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xTaskGetSchedulerState_Unpriv                 \n"
+                " MPU_xTaskGetSchedulerState_Priv:                      \n"
+                "     push {lr}                                         \n"
+                "     blx MPU_xTaskGetSchedulerStateImpl                \n"
+                "     pop {pc}                                          \n"
+                " MPU_xTaskGetSchedulerState_Unpriv:                    \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory"
+            );
+        }
+
+    #endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */
+/*-----------------------------------------------------------*/
+
+    void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+    void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_vTaskSetTimeOutStateImpl                  \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
+            " bne MPU_vTaskSetTimeOutState_Unpriv                   \n"
+            " MPU_vTaskSetTimeOutState_Priv:                        \n"
+            "     push {lr}                                         \n"
+            "     blx MPU_vTaskSetTimeOutStateImpl                  \n"
+            "     pop {pc}                                          \n"
+            " MPU_vTaskSetTimeOutState_Unpriv:                      \n"
+            "     svc %0                                            \n"
+            "                                                       \n"
+            : : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory"
+        );
+    }
+/*-----------------------------------------------------------*/
+
+    BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
+                                         TickType_t * const pxTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+    BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
+                                         TickType_t * const pxTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xTaskCheckForTimeOutImpl                  \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
+            " bne MPU_xTaskCheckForTimeOut_Unpriv                   \n"
+            " MPU_xTaskCheckForTimeOut_Priv:                        \n"
+            "     push {lr}                                         \n"
+            "     blx MPU_xTaskCheckForTimeOutImpl                  \n"
+            "     pop {pc}                                          \n"
+            " MPU_xTaskCheckForTimeOut_Unpriv:                      \n"
+            "     svc %0                                            \n"
+            "                                                       \n"
+            : : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory"
+        );
+    }
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
+
+        BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGenericNotifyImpl                    \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xTaskGenericNotify_Unpriv                     \n"
+                " MPU_xTaskGenericNotify_Priv:                          \n"
+                "     push {lr}                                         \n"
+                "     blx MPU_xTaskGenericNotifyImpl                    \n"
+                "     pop {pc}                                          \n"
+                " MPU_xTaskGenericNotify_Unpriv:                        \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
+
+        BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGenericNotifyWaitImpl                \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xTaskGenericNotifyWait_Unpriv                 \n"
+                " MPU_xTaskGenericNotifyWait_Priv:                      \n"
+                "     push {lr}                                         \n"
+                "     blx MPU_xTaskGenericNotifyWaitImpl                \n"
+                "     pop {pc}                                          \n"
+                " MPU_xTaskGenericNotifyWait_Unpriv:                    \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
+
+        uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
+                                              BaseType_t xClearCountOnExit,
+                                              TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
+                                              BaseType_t xClearCountOnExit,
+                                              TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGenericNotifyTakeImpl               \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_ulTaskGenericNotifyTake_Unpriv                \n"
+                " MPU_ulTaskGenericNotifyTake_Priv:                     \n"
+                "     push {lr}                                         \n"
+                "     blx MPU_ulTaskGenericNotifyTakeImpl               \n"
+                "     pop {pc}                                          \n"
+                " MPU_ulTaskGenericNotifyTake_Unpriv:                   \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
+
+        BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
+                                                     UBaseType_t uxIndexToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
+                                                     UBaseType_t uxIndexToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTaskGenericNotifyStateClearImpl          \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xTaskGenericNotifyStateClear_Unpriv           \n"
+                " MPU_xTaskGenericNotifyStateClear_Priv:                \n"
+                "     push {lr}                                         \n"
+                "     blx MPU_xTaskGenericNotifyStateClearImpl          \n"
+                "     pop {pc}                                          \n"
+                " MPU_xTaskGenericNotifyStateClear_Unpriv:              \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
+
+        uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
+                                                    UBaseType_t uxIndexToClear,
+                                                    uint32_t ulBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
+                                                    UBaseType_t uxIndexToClear,
+                                                    uint32_t ulBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_ulTaskGenericNotifyValueClearImpl         \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_ulTaskGenericNotifyValueClear_Unpriv          \n"
+                " MPU_ulTaskGenericNotifyValueClear_Priv:               \n"
+                "     push {lr}                                         \n"
+                "     blx MPU_ulTaskGenericNotifyValueClearImpl         \n"
+                "     pop {pc}                                          \n"
+                " MPU_ulTaskGenericNotifyValueClear_Unpriv:             \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
+                                      const void * const pvItemToQueue,
+                                      TickType_t xTicksToWait,
+                                      const BaseType_t xCopyPosition ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+    BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
+                                      const void * const pvItemToQueue,
+                                      TickType_t xTicksToWait,
+                                      const BaseType_t xCopyPosition ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueueGenericSendImpl                     \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
+            " bne MPU_xQueueGenericSend_Unpriv                      \n"
+            " MPU_xQueueGenericSend_Priv:                           \n"
+            "     push {lr}                                         \n"
+            "     blx MPU_xQueueGenericSendImpl                     \n"
+            "     pop {pc}                                          \n"
+            " MPU_xQueueGenericSend_Unpriv:                         \n"
+            "     svc %0                                            \n"
+            "                                                       \n"
+            : : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory"
+        );
+    }
+/*-----------------------------------------------------------*/
+
+    UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+    UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_uxQueueMessagesWaitingImpl                \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
+            " bne MPU_uxQueueMessagesWaiting_Unpriv                 \n"
+            " MPU_uxQueueMessagesWaiting_Priv:                      \n"
+            "     push {lr}                                         \n"
+            "     blx MPU_uxQueueMessagesWaitingImpl                \n"
+            "     pop {pc}                                          \n"
+            " MPU_uxQueueMessagesWaiting_Unpriv:                    \n"
+            "     svc %0                                            \n"
+            "                                                       \n"
+            : : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory"
+        );
+    }
+/*-----------------------------------------------------------*/
+
+    UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+    UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_uxQueueSpacesAvailableImpl                \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
+            " bne MPU_uxQueueSpacesAvailable_Unpriv                 \n"
+            " MPU_uxQueueSpacesAvailable_Priv:                      \n"
+            "     push {lr}                                         \n"
+            "     blx MPU_uxQueueSpacesAvailableImpl                \n"
+            "     pop {pc}                                          \n"
+            " MPU_uxQueueSpacesAvailable_Unpriv:                    \n"
+            "     svc %0                                            \n"
+            "                                                       \n"
+            : : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory"
+        );
+    }
+/*-----------------------------------------------------------*/
+
+    BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
+                                  void * const pvBuffer,
+                                  TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+    BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
+                                  void * const pvBuffer,
+                                  TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueueReceiveImpl                         \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
+            " bne MPU_xQueueReceive_Unpriv                          \n"
+            " MPU_xQueueReceive_Priv:                               \n"
+            "     push {lr}                                         \n"
+            "     blx MPU_xQueueReceiveImpl                         \n"
+            "     pop {pc}                                          \n"
+            " MPU_xQueueReceive_Unpriv:                             \n"
+            "     svc %0                                            \n"
+            "                                                       \n"
+            : : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory"
+        );
+    }
+/*-----------------------------------------------------------*/
+
+    BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
+                               void * const pvBuffer,
+                               TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+    BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
+                               void * const pvBuffer,
+                               TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueuePeekImpl                            \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
+            " bne MPU_xQueuePeek_Unpriv                             \n"
+            " MPU_xQueuePeek_Priv:                                  \n"
+            "     push {lr}                                         \n"
+            "     blx MPU_xQueuePeekImpl                            \n"
+            "     pop {pc}                                          \n"
+            " MPU_xQueuePeek_Unpriv:                                \n"
+            "     svc %0                                            \n"
+            "                                                       \n"
+            : : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory"
+        );
+    }
+/*-----------------------------------------------------------*/
+
+    BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
+                                        TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+    BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
+                                        TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xQueueSemaphoreTakeImpl                   \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
+            " bne MPU_xQueueSemaphoreTake_Unpriv                    \n"
+            " MPU_xQueueSemaphoreTake_Priv:                         \n"
+            "     push {lr}                                         \n"
+            "     blx MPU_xQueueSemaphoreTakeImpl                   \n"
+            "     pop {pc}                                          \n"
+            " MPU_xQueueSemaphoreTake_Unpriv:                       \n"
+            "     svc %0                                            \n"
+            "                                                       \n"
+            : : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory"
+        );
+    }
+/*-----------------------------------------------------------*/
+
+    #if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+
+        TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueGetMutexHolderImpl                  \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xQueueGetMutexHolder_Unpriv                   \n"
+                " MPU_xQueueGetMutexHolder_Priv:                        \n"
+                "     push {lr}                                         \n"
+                "     blx MPU_xQueueGetMutexHolderImpl                  \n"
+                "     pop {pc}                                          \n"
+                " MPU_xQueueGetMutexHolder_Unpriv:                      \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory"
+            );
+        }
+
+    #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_RECURSIVE_MUTEXES == 1 )
+
+        BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+                                                 TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+                                                 TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueTakeMutexRecursiveImpl              \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xQueueTakeMutexRecursive_Unpriv               \n"
+                " MPU_xQueueTakeMutexRecursive_Priv:                    \n"
+                "     push {lr}                                         \n"
+                "     blx MPU_xQueueTakeMutexRecursiveImpl              \n"
+                "     pop {pc}                                          \n"
+                " MPU_xQueueTakeMutexRecursive_Unpriv:                  \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_RECURSIVE_MUTEXES == 1 )
+
+        BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueGiveMutexRecursiveImpl              \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xQueueGiveMutexRecursive_Unpriv               \n"
+                " MPU_xQueueGiveMutexRecursive_Priv:                    \n"
+                "     push {lr}                                         \n"
+                "     blx MPU_xQueueGiveMutexRecursiveImpl              \n"
+                "     pop {pc}                                          \n"
+                " MPU_xQueueGiveMutexRecursive_Unpriv:                  \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_QUEUE_SETS == 1 )
+
+        QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
+                                                        const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
+                                                        const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueSelectFromSetImpl                   \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xQueueSelectFromSet_Unpriv                    \n"
+                " MPU_xQueueSelectFromSet_Priv:                         \n"
+                "     push {lr}                                         \n"
+                "     blx MPU_xQueueSelectFromSetImpl                   \n"
+                "     pop {pc}                                          \n"
+                " MPU_xQueueSelectFromSet_Unpriv:                       \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_QUEUE_SETS == 1 )
+
+        BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                                       QueueSetHandle_t xQueueSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                                       QueueSetHandle_t xQueueSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xQueueAddToSetImpl                        \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xQueueAddToSet_Unpriv                         \n"
+                " MPU_xQueueAddToSet_Priv:                              \n"
+                "     push {lr}                                         \n"
+                "     blx MPU_xQueueAddToSetImpl                        \n"
+                "     pop {pc}                                          \n"
+                " MPU_xQueueAddToSet_Unpriv:                            \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+        void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
+                                      const char * pcName ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
+                                      const char * pcName ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vQueueAddToRegistryImpl                   \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_vQueueAddToRegistry_Unpriv                    \n"
+                " MPU_vQueueAddToRegistry_Priv:                         \n"
+                "     push {lr}                                         \n"
+                "     blx MPU_vQueueAddToRegistryImpl                   \n"
+                "     pop {pc}                                          \n"
+                " MPU_vQueueAddToRegistry_Unpriv:                       \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory"
+            );
+        }
+
+    #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+        void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vQueueUnregisterQueueImpl                 \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_vQueueUnregisterQueue_Unpriv                  \n"
+                " MPU_vQueueUnregisterQueue_Priv:                       \n"
+                "     push {lr}                                         \n"
+                "     blx MPU_vQueueUnregisterQueueImpl                 \n"
+                "     pop {pc}                                          \n"
+                " MPU_vQueueUnregisterQueue_Unpriv:                     \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory"
+            );
+        }
+
+    #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+        const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pcQueueGetNameImpl                        \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_pcQueueGetName_Unpriv                         \n"
+                " MPU_pcQueueGetName_Priv:                              \n"
+                "     push {lr}                                         \n"
+                "     blx MPU_pcQueueGetNameImpl                        \n"
+                "     pop {pc}                                          \n"
+                " MPU_pcQueueGetName_Unpriv:                            \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory"
+            );
+        }
+
+    #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pvTimerGetTimerIDImpl                     \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_pvTimerGetTimerID_Unpriv                      \n"
+                " MPU_pvTimerGetTimerID_Priv:                           \n"
+                "     push {lr}                                         \n"
+                "     blx MPU_pvTimerGetTimerIDImpl                     \n"
+                "     pop {pc}                                          \n"
+                " MPU_pvTimerGetTimerID_Unpriv:                         \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
+                                   void * pvNewID ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
+                                   void * pvNewID ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTimerSetTimerIDImpl                      \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_vTimerSetTimerID_Unpriv                       \n"
+                " MPU_vTimerSetTimerID_Priv:                            \n"
+                "     push {lr}                                         \n"
+                "     blx MPU_vTimerSetTimerIDImpl                      \n"
+                "     pop {pc}                                          \n"
+                " MPU_vTimerSetTimerID_Unpriv:                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerIsTimerActiveImpl                   \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xTimerIsTimerActive_Unpriv                    \n"
+                " MPU_xTimerIsTimerActive_Priv:                         \n"
+                "     push {lr}                                         \n"
+                "     blx MPU_xTimerIsTimerActiveImpl                   \n"
+                "     pop {pc}                                          \n"
+                " MPU_xTimerIsTimerActive_Unpriv:                       \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetTimerDaemonTaskHandleImpl        \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv         \n"
+                " MPU_xTimerGetTimerDaemonTaskHandle_Priv:              \n"
+                "     push {lr}                                         \n"
+                "     blx MPU_xTimerGetTimerDaemonTaskHandleImpl        \n"
+                "     pop {pc}                                          \n"
+                " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:            \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGenericCommandFromTaskImpl          \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xTimerGenericCommandFromTask_Unpriv           \n"
+                " MPU_xTimerGenericCommandFromTask_Priv:                \n"
+                "     push {lr}                                         \n"
+                "     blx MPU_xTimerGenericCommandFromTaskImpl          \n"
+                "     pop {pc}                                          \n"
+                " MPU_xTimerGenericCommandFromTask_Unpriv:              \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_pcTimerGetNameImpl                        \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_pcTimerGetName_Unpriv                         \n"
+                " MPU_pcTimerGetName_Priv:                              \n"
+                "     push {lr}                                         \n"
+                "     blx MPU_pcTimerGetNameImpl                        \n"
+                "     pop {pc}                                          \n"
+                " MPU_pcTimerGetName_Unpriv:                            \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
+                                      const BaseType_t uxAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
+                                      const BaseType_t uxAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vTimerSetReloadModeImpl                   \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_vTimerSetReloadMode_Unpriv                    \n"
+                " MPU_vTimerSetReloadMode_Priv:                         \n"
+                "     push {lr}                                         \n"
+                "     blx MPU_vTimerSetReloadModeImpl                   \n"
+                "     pop {pc}                                          \n"
+                " MPU_vTimerSetReloadMode_Unpriv:                       \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetReloadModeImpl                   \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xTimerGetReloadMode_Unpriv                    \n"
+                " MPU_xTimerGetReloadMode_Priv:                         \n"
+                "     push {lr}                                         \n"
+                "     blx MPU_xTimerGetReloadModeImpl                   \n"
+                "     pop {pc}                                          \n"
+                " MPU_xTimerGetReloadMode_Unpriv:                       \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxTimerGetReloadModeImpl                  \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_uxTimerGetReloadMode_Unpriv                   \n"
+                " MPU_uxTimerGetReloadMode_Priv:                        \n"
+                "     push {lr}                                         \n"
+                "     blx MPU_uxTimerGetReloadModeImpl                  \n"
+                "     pop {pc}                                          \n"
+                " MPU_uxTimerGetReloadMode_Unpriv:                      \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetPeriodImpl                       \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xTimerGetPeriod_Unpriv                        \n"
+                " MPU_xTimerGetPeriod_Priv:                             \n"
+                "     push {lr}                                         \n"
+                "     blx MPU_xTimerGetPeriodImpl                       \n"
+                "     pop {pc}                                          \n"
+                " MPU_xTimerGetPeriod_Unpriv:                           \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TIMERS == 1 )
+
+        TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xTimerGetExpiryTimeImpl                   \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xTimerGetExpiryTime_Unpriv                    \n"
+                " MPU_xTimerGetExpiryTime_Priv:                         \n"
+                "     push {lr}                                         \n"
+                "     blx MPU_xTimerGetExpiryTimeImpl                   \n"
+                "     pop {pc}                                          \n"
+                " MPU_xTimerGetExpiryTime_Unpriv:                       \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory"
+            );
+        }
+
+    #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupWaitBitsImpl                   \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
+            " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
+            " MPU_xEventGroupWaitBits_Priv:                         \n"
+            "     push {lr}                                         \n"
+            "     blx MPU_xEventGroupWaitBitsImpl                   \n"
+            "     pop {pc}                                          \n"
+            " MPU_xEventGroupWaitBits_Unpriv:                       \n"
+            "     svc %0                                            \n"
+            "                                                       \n"
+            : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
+        );
+    }
+/*-----------------------------------------------------------*/
+
+    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                          const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                          const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupClearBitsImpl                  \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
+            " bne MPU_xEventGroupClearBits_Unpriv                   \n"
+            " MPU_xEventGroupClearBits_Priv:                        \n"
+            "     push {lr}                                         \n"
+            "     blx MPU_xEventGroupClearBitsImpl                  \n"
+            "     pop {pc}                                          \n"
+            " MPU_xEventGroupClearBits_Unpriv:                      \n"
+            "     svc %0                                            \n"
+            "                                                       \n"
+            : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
+        );
+    }
+/*-----------------------------------------------------------*/
+
+    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                        const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                        const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupSetBitsImpl                    \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
+            " bne MPU_xEventGroupSetBits_Unpriv                     \n"
+            " MPU_xEventGroupSetBits_Priv:                          \n"
+            "     push {lr}                                         \n"
+            "     blx MPU_xEventGroupSetBitsImpl                    \n"
+            "     pop {pc}                                          \n"
+            " MPU_xEventGroupSetBits_Unpriv:                        \n"
+            "     svc %0                                            \n"
+            "                                                       \n"
+            : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
+        );
+    }
+/*-----------------------------------------------------------*/
+
+    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                     const EventBits_t uxBitsToSet,
+                                     const EventBits_t uxBitsToWaitFor,
+                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                     const EventBits_t uxBitsToSet,
+                                     const EventBits_t uxBitsToWaitFor,
+                                     TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xEventGroupSyncImpl                       \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
+            " bne MPU_xEventGroupSync_Unpriv                        \n"
+            " MPU_xEventGroupSync_Priv:                             \n"
+            "     push {lr}                                         \n"
+            "     blx MPU_xEventGroupSyncImpl                       \n"
+            "     pop {pc}                                          \n"
+            " MPU_xEventGroupSync_Unpriv:                           \n"
+            "     svc %0                                            \n"
+            "                                                       \n"
+            : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
+        );
+    }
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TRACE_FACILITY == 1 )
+
+        UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_uxEventGroupGetNumberImpl                 \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_uxEventGroupGetNumber_Unpriv                  \n"
+                " MPU_uxEventGroupGetNumber_Priv:                       \n"
+                "     push {lr}                                         \n"
+                "     blx MPU_uxEventGroupGetNumberImpl                 \n"
+                "     pop {pc}                                          \n"
+                " MPU_uxEventGroupGetNumber_Unpriv:                     \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory"
+            );
+        }
+
+    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TRACE_FACILITY == 1 )
+
+        void MPU_vEventGroupSetNumber( void * xEventGroup,
+                                       UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        void MPU_vEventGroupSetNumber( void * xEventGroup,
+                                       UBaseType_t uxEventGroupNumber ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_vEventGroupSetNumberImpl                  \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_vEventGroupSetNumber_Unpriv                   \n"
+                " MPU_vEventGroupSetNumber_Priv:                        \n"
+                "     push {lr}                                         \n"
+                "     blx MPU_vEventGroupSetNumberImpl                  \n"
+                "     pop {pc}                                          \n"
+                " MPU_vEventGroupSetNumber_Unpriv:                      \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory"
+            );
+        }
+
+    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+/*-----------------------------------------------------------*/
+
+    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                  const void * pvTxData,
+                                  size_t xDataLengthBytes,
+                                  TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                  const void * pvTxData,
+                                  size_t xDataLengthBytes,
+                                  TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferSendImpl                     \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
+            " bne MPU_xStreamBufferSend_Unpriv                      \n"
+            " MPU_xStreamBufferSend_Priv:                           \n"
+            "     push {lr}                                         \n"
+            "     blx MPU_xStreamBufferSendImpl                     \n"
+            "     pop {pc}                                          \n"
+            " MPU_xStreamBufferSend_Unpriv:                         \n"
+            "     svc %0                                            \n"
+            "                                                       \n"
+            : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
+        );
+    }
+/*-----------------------------------------------------------*/
+
+    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                     void * pvRxData,
+                                     size_t xBufferLengthBytes,
+                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                     void * pvRxData,
+                                     size_t xBufferLengthBytes,
+                                     TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferReceiveImpl                  \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
+            " bne MPU_xStreamBufferReceive_Unpriv                   \n"
+            " MPU_xStreamBufferReceive_Priv:                        \n"
+            "     push {lr}                                         \n"
+            "     blx MPU_xStreamBufferReceiveImpl                  \n"
+            "     pop {pc}                                          \n"
+            " MPU_xStreamBufferReceive_Unpriv:                      \n"
+            "     svc %0                                            \n"
+            "                                                       \n"
+            : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
+        );
+    }
+/*-----------------------------------------------------------*/
+
+    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferIsFullImpl                   \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
+            " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
+            " MPU_xStreamBufferIsFull_Priv:                         \n"
+            "     push {lr}                                         \n"
+            "     blx MPU_xStreamBufferIsFullImpl                   \n"
+            "     pop {pc}                                          \n"
+            " MPU_xStreamBufferIsFull_Unpriv:                       \n"
+            "     svc %0                                            \n"
+            "                                                       \n"
+            : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
+        );
+    }
+/*-----------------------------------------------------------*/
+
+    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
+            " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
+            " MPU_xStreamBufferIsEmpty_Priv:                        \n"
+            "     push {lr}                                         \n"
+            "     blx MPU_xStreamBufferIsEmptyImpl                  \n"
+            "     pop {pc}                                          \n"
+            " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
+            "     svc %0                                            \n"
+            "                                                       \n"
+            : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
+        );
+    }
+/*-----------------------------------------------------------*/
+
+    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
+            " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
+            " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
+            "     push {lr}                                         \n"
+            "     blx MPU_xStreamBufferSpacesAvailableImpl          \n"
+            "     pop {pc}                                          \n"
+            " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
+            "     svc %0                                            \n"
+            "                                                       \n"
+            : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
+        );
+    }
+/*-----------------------------------------------------------*/
+
+    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
+            " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
+            " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
+            "     push {lr}                                         \n"
+            "     blx MPU_xStreamBufferBytesAvailableImpl           \n"
+            "     pop {pc}                                          \n"
+            " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
+            "     svc %0                                            \n"
+            "                                                       \n"
+            : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
+        );
+    }
+/*-----------------------------------------------------------*/
+
+    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                 size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                 size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
+            " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
+            " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
+            "     push {lr}                                         \n"
+            "     blx MPU_xStreamBufferSetTriggerLevelImpl          \n"
+            "     pop {pc}                                          \n"
+            " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
+            "     svc %0                                            \n"
+            "                                                       \n"
+            : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
+        );
+    }
+/*-----------------------------------------------------------*/
+
+    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                       \n"
+            " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
+            "                                                       \n"
+            " push {r0, r1}                                         \n"
+            " mrs r0, control                                       \n"
+            " movs r1, #1                                           \n"
+            " tst r0, r1                                            \n"
+            " pop {r0, r1}                                          \n"
+            " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
+            " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
+            "     push {lr}                                         \n"
+            "     blx MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
+            "     pop {pc}                                          \n"
+            " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
+            "     svc %0                                            \n"
+            "                                                       \n"
+            : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
+        );
+    }
+/*-----------------------------------------------------------*/
+
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
diff --git a/portable/GCC/ARM_CM0/port.c b/portable/GCC/ARM_CM0/port.c
index 41b14fa3b..4ee1d9494 100644
--- a/portable/GCC/ARM_CM0/port.c
+++ b/portable/GCC/ARM_CM0/port.c
@@ -26,54 +26,195 @@
  *
  */
 
-/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the ARM CM0 port.
-*----------------------------------------------------------*/
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers. That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
 
 /* Scheduler includes. */
 #include "FreeRTOS.h"
 #include "task.h"
 
-/* Prototype of all Interrupt Service Routines (ISRs). */
+/* MPU includes. */
+#include "mpu_wrappers.h"
+#include "mpu_syscall_numbers.h"
+
+/* Portasm includes. */
+#include "portasm.h"
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Prototype of all Interrupt Service Routines (ISRs).
+ */
 typedef void ( * portISR_t )( void );
 
-/* Constants required to manipulate the NVIC. */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the NVIC.
+ */
 #define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )
 #define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )
 #define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )
-#define portNVIC_INT_CTRL_REG                 ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
-#define portNVIC_SYSTICK_CLK_BIT              ( 1UL << 2UL )
-#define portNVIC_SYSTICK_INT_BIT              ( 1UL << 1UL )
+#define portNVIC_SHPR2_REG                    ( *( ( volatile uint32_t * ) 0xe000ed1c ) )
 #define portNVIC_SYSTICK_ENABLE_BIT           ( 1UL << 0UL )
+#define portNVIC_SYSTICK_INT_BIT              ( 1UL << 1UL )
+#define portNVIC_SYSTICK_CLK_BIT              ( 1UL << 2UL )
 #define portNVIC_SYSTICK_COUNT_FLAG_BIT       ( 1UL << 16UL )
-#define portNVIC_PENDSVSET_BIT                ( 1UL << 28UL )
-#define portNVIC_PEND_SYSTICK_SET_BIT         ( 1UL << 26UL )
 #define portNVIC_PEND_SYSTICK_CLEAR_BIT       ( 1UL << 25UL )
+#define portNVIC_PEND_SYSTICK_SET_BIT         ( 1UL << 26UL )
 #define portMIN_INTERRUPT_PRIORITY            ( 255UL )
 #define portNVIC_PENDSV_PRI                   ( portMIN_INTERRUPT_PRIORITY << 16UL )
 #define portNVIC_SYSTICK_PRI                  ( portMIN_INTERRUPT_PRIORITY << 24UL )
 
-/* Constants used to check the installation of the FreeRTOS interrupt handlers. */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
 #define portSCB_VTOR_REG                      ( *( ( portISR_t ** ) 0xe000ed08 ) )
-#define portVECTOR_INDEX_PENDSV               ( 14 )
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
+#define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )
 
-/* Constants required to set up the initial stack. */
-#define portINITIAL_XPSR                      ( 0x01000000 )
+/*-----------------------------------------------------------*/
 
-/* The systick is a 24-bit counter. */
-#define portMAX_24_BIT_NUMBER                 ( 0xffffffUL )
+/**
+ * @brief Constants used to check the installation of the FreeRTOS interrupt handlers.
+ */
+#define portVECTOR_INDEX_SVC       ( 11 )
+#define portVECTOR_INDEX_PENDSV    ( 14 )
 
-/* A fiddle factor to estimate the number of SysTick counts that would have
- * occurred while the SysTick counter is stopped during tickless idle
- * calculations. */
-#ifndef portMISSED_COUNTS_FACTOR
-    #define portMISSED_COUNTS_FACTOR    ( 94UL )
-#endif
+/*-----------------------------------------------------------*/
 
-/* Let the user override the default SysTick clock rate.  If defined by the
+/**
+ * @brief Constants used during system call enter and exit.
+ */
+#define portPSR_STACK_PADDING_MASK              ( 1UL << 9UL )
+#define portEXC_RETURN_STACK_FRAME_TYPE_MASK    ( 1UL << 4UL )
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Offsets in the stack to the parameters when inside the SVC handler.
+ */
+#define portOFFSET_TO_LR     ( 5 )
+#define portOFFSET_TO_PC     ( 6 )
+#define portOFFSET_TO_PSR    ( 7 )
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the MPU.
+ */
+#define portMPU_TYPE_REG                            ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                            ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+
+#define portMPU_RBAR_REG                            ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RASR_REG                            ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+
+/* MPU Region Attribute and Size Register (RASR) bitmasks. */
+#define portMPU_RASR_AP_BITMASK                     ( 0x7UL << 24UL )
+#define portMPU_RASR_S_C_B_BITMASK                  ( 0x7UL )
+#define portMPU_RASR_S_C_B_LOCATION                 ( 16UL )
+#define portMPU_RASR_SIZE_BITMASK                   ( 0x1FUL << 1UL )
+#define portMPU_RASR_REGION_ENABLE_BITMASK          ( 0x1UL )
+
+/* MPU Region Base Address Register (RBAR) bitmasks. */
+#define portMPU_RBAR_ADDRESS_BITMASK                ( 0xFFFFFF00UL )
+#define portMPU_RBAR_REGION_NUMBER_VALID_BITMASK    ( 0x1UL << 4UL )
+#define portMPU_RBAR_REGION_NUMBER_BITMASK          ( 0x0000000FUL )
+
+/* MPU Control Register (MPU_CTRL) bitmasks. */
+#define portMPU_CTRL_ENABLE_BITMASK                 ( 0x1UL )
+#define portMPU_CTRL_PRIV_BACKGROUND_ENABLE_BITMASK ( 0x1UL << 2UL ) /* PRIVDEFENA bit. */
+
+/* Expected value of the portMPU_TYPE register. */
+#define portEXPECTED_MPU_TYPE_VALUE                 ( 0x8UL << 8UL ) /* 8 DREGION unified. */
+
+/* Extract first address of the MPU region as encoded in the
+ * RBAR (Region Base Address Register) value. */
+#define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \
+    ( ( rbar ) & portMPU_RBAR_ADDRESS_BITMASK )
+
+/* Extract size of the MPU region as encoded in the
+ * RASR (Region Attribute and Size Register) value. */
+#define portEXTRACT_REGION_SIZE_FROM_RASR( rasr ) \
+    ( 1 << ( ( ( ( rasr ) & portMPU_RASR_SIZE_BITMASK ) >> 1 )+ 1 ) )
+
+/* Does addr lies within [start, end] address range? */
+#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \
+    ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) )
+
+/* Is the access request satisfied by the available permissions? */
+#define portIS_AUTHORIZED( accessRequest, permissions ) \
+    ( ( ( permissions ) & ( accessRequest ) ) == accessRequest )
+
+/* Max value that fits in a uint32_t type. */
+#define portUINT32_MAX    ( ~( ( uint32_t ) 0 ) )
+
+/* Check if adding a and b will result in overflow. */
+#define portADD_UINT32_WILL_OVERFLOW( a, b )    ( ( a ) > ( portUINT32_MAX - ( b ) ) )
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief The maximum 24-bit number.
+ *
+ * It is needed because the systick is a 24-bit counter.
+ */
+#define portMAX_24_BIT_NUMBER       ( 0xffffffUL )
+
+/**
+ * @brief A fiddle factor to estimate the number of SysTick counts that would
+ * have occurred while the SysTick counter is stopped during tickless idle
+ * calculations.
+ */
+#define portMISSED_COUNTS_FACTOR    ( 94UL )
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to set up the initial stack.
+ */
+#define portINITIAL_XPSR    ( 0x01000000 )
+
+/**
+ * @brief Initial EXC_RETURN value.
+ *
+ *     FF         FF         FF         FD
+ * 1111 1111  1111 1111  1111 1111  1111 1101
+ *
+ * Bit[3] - 1 --> Return to the Thread mode.
+ * Bit[2] - 1 --> Restore registers from the process stack.
+ * Bit[1] - 0 --> Reserved, 0.
+ * Bit[0] - 0 --> Reserved, 1.
+ */
+#define portINITIAL_EXC_RETURN    ( 0xfffffffdUL )
+
+/**
+ * @brief CONTROL register privileged bit mask.
+ *
+ * Bit[0] in CONTROL register tells the privilege:
+ *  Bit[0] = 0 ==> The task is privileged.
+ *  Bit[0] = 1 ==> The task is not privileged.
+ */
+#define portCONTROL_PRIVILEGED_MASK         ( 1UL << 0UL )
+
+/**
+ * @brief Initial CONTROL register values.
+ */
+#define portINITIAL_CONTROL_UNPRIVILEGED    ( 0x3 )
+#define portINITIAL_CONTROL_PRIVILEGED      ( 0x2 )
+
+/**
+ * @brief Let the user override the default SysTick clock rate.  If defined by the
  * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the
- * configuration register. */
+ * configuration register.
+ */
 #ifndef configSYSTICK_CLOCK_HZ
     #define configSYSTICK_CLOCK_HZ             ( configCPU_CLOCK_HZ )
     /* Ensure the SysTick is clocked at the same frequency as the core. */
@@ -83,381 +224,169 @@ typedef void ( * portISR_t )( void );
     #define portNVIC_SYSTICK_CLK_BIT_CONFIG    ( 0 )
 #endif
 
-/* Let the user override the pre-loading of the initial LR with the address of
- * prvTaskExitError() in case it messes up unwinding of the stack in the
- * debugger. */
+/**
+ * @brief Let the user override the pre-loading of the initial LR with the
+ * address of prvTaskExitError() in case it messes up unwinding of the stack
+ * in the debugger.
+ */
 #ifdef configTASK_RETURN_ADDRESS
     #define portTASK_RETURN_ADDRESS    configTASK_RETURN_ADDRESS
 #else
     #define portTASK_RETURN_ADDRESS    prvTaskExitError
 #endif
 
-/*
- * Setup the timer to generate the tick interrupts.  The implementation in this
- * file is weak to allow application writers to change the timer used to
- * generate the tick interrupt.
+/**
+ * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
+ * when a task is created. This helps in debugging at the cost of code size.
  */
-void vPortSetupTimerInterrupt( void );
+#define portPRELOAD_REGISTERS    1
 
-/*
- * Exception handlers.
- */
-void xPortPendSVHandler( void ) __attribute__( ( naked ) );
-void xPortSysTickHandler( void );
-void vPortSVCHandler( void );
+/*-----------------------------------------------------------*/
 
-/*
- * Start first task is a separate function so it can be tested in isolation.
- */
-static void vPortStartFirstTask( void ) __attribute__( ( naked ) );
-
-/*
- * Used to catch tasks that attempt to return from their implementing function.
+/**
+ * @brief Used to catch tasks that attempt to return from their implementing
+ * function.
  */
 static void prvTaskExitError( void );
 
-/*-----------------------------------------------------------*/
+#if ( configENABLE_MPU == 1 )
 
-/* Each task maintains its own interrupt status in the critical nesting
- * variable. */
-static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+    /**
+     * @brief Setup the Memory Protection Unit (MPU).
+     */
+    static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
 
-/*-----------------------------------------------------------*/
+#endif /* configENABLE_MPU */
 
-/*
- * The number of SysTick increments that make up one tick period.
+/**
+ * @brief Setup the timer to generate the tick interrupts.
+ *
+ * The implementation in this file is weak to allow application writers to
+ * change the timer used to generate the tick interrupt.
  */
-#if ( configUSE_TICKLESS_IDLE == 1 )
-    static uint32_t ulTimerCountsForOneTick = 0;
-#endif /* configUSE_TICKLESS_IDLE */
+void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
 
-/*
- * The maximum number of tick periods that can be suppressed is limited by the
- * 24 bit resolution of the SysTick timer.
+/**
+ * @brief Checks whether the current execution context is interrupt.
+ *
+ * @return pdTRUE if the current execution context is interrupt, pdFALSE
+ * otherwise.
  */
-#if ( configUSE_TICKLESS_IDLE == 1 )
-    static uint32_t xMaximumPossibleSuppressedTicks = 0;
-#endif /* configUSE_TICKLESS_IDLE */
+BaseType_t xPortIsInsideInterrupt( void );
 
-/*
- * Compensate for the CPU cycles that pass while the SysTick is stopped (low
- * power functionality only.
+/**
+ * @brief Yield the processor.
  */
-#if ( configUSE_TICKLESS_IDLE == 1 )
-    static uint32_t ulStoppedTimerCompensation = 0;
-#endif /* configUSE_TICKLESS_IDLE */
+void vPortYield( void ) PRIVILEGED_FUNCTION;
 
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
+/**
+ * @brief Enter critical section.
  */
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters )
-{
-    /* Simulate the stack frame as it would be created by a context switch
-     * interrupt. */
-    pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-    *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR */
-    pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC */
-    pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
-    pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
-    *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */
-    pxTopOfStack -= 8;                                       /* R11..R4. */
+void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
 
-    return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
+/**
+ * @brief Exit from critical section.
+ */
+void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
 
-static void prvTaskExitError( void )
-{
-    volatile uint32_t ulDummy = 0UL;
+/**
+ * @brief SysTick handler.
+ */
+void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
 
-    /* A function that implements a task must not exit or attempt to return to
-     * its caller as there is nothing to return to.  If a task wants to exit it
-     * should instead call vTaskDelete( NULL ).
+/**
+ * @brief C part of SVC handler.
+ */
+portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION;
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+    /**
+     * @brief Sets up the system call stack so that upon returning from
+     * SVC, the system call stack is used.
      *
-     * Artificially force an assert() to be triggered if configASSERT() is
-     * defined, then stop here so application writers can catch the error. */
-    configASSERT( uxCriticalNesting == ~0UL );
-    portDISABLE_INTERRUPTS();
+     * @param pulTaskStack The current SP when the SVC was raised.
+     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+     * @param ucSystemCallNumber The system call number of the system call.
+     */
+    void vSystemCallEnter( uint32_t * pulTaskStack,
+                           uint32_t ulLR,
+                           uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION;
 
-    while( ulDummy == 0 )
-    {
-        /* This file calls prvTaskExitError() after the scheduler has been
-         * started to remove a compiler warning about the function being defined
-         * but never called.  ulDummy is used purely to quieten other warnings
-         * about code appearing after this function is called - making ulDummy
-         * volatile makes the compiler think the function could return and
-         * therefore not output an 'unreachable code' warning for code that appears
-         * after it. */
-    }
-}
-/*-----------------------------------------------------------*/
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
-void vPortSVCHandler( void )
-{
-    /* This function is no longer used, but retained for backward
-     * compatibility. */
-}
-/*-----------------------------------------------------------*/
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vPortStartFirstTask( void )
-{
-    /* Don't reset the MSP stack as is done on CM3/4 devices. The vector table
-     * in some CM0 devices cannot be modified and thus may not hold the
-     * application's initial MSP value. */
-    __asm volatile (
-        "   .syntax unified             \n"
-        "   ldr  r2, pxCurrentTCBConst2 \n"     /* Obtain location of pxCurrentTCB. */
-        "   ldr  r3, [r2]               \n"
-        "   ldr  r0, [r3]               \n"     /* The first item in pxCurrentTCB is the task top of stack. */
-        "   adds r0, #32                \n"     /* Discard everything up to r0. */
-        "   msr  psp, r0                \n"     /* This is now the new top of stack to use in the task. */
-        "   movs r0, #2                 \n"     /* Switch to the psp stack. */
-        "   msr  CONTROL, r0            \n"
-        "   isb                         \n"
-        "   pop  {r0-r5}                \n"     /* Pop the registers that are saved automatically. */
-        "   mov  lr, r5                 \n"     /* lr is now in r5. */
-        "   pop  {r3}                   \n"     /* Return address is now in r3. */
-        "   pop  {r2}                   \n"     /* Pop and discard XPSR. */
-        "   cpsie i                     \n"     /* The first task has its context and interrupts can be enabled. */
-        "   bx   r3                     \n"     /* Finally, jump to the user defined task code. */
-        "                               \n"
-        "   .align 4                    \n"
-        "pxCurrentTCBConst2: .word pxCurrentTCB   "
-        );
-}
-/*-----------------------------------------------------------*/
+    /**
+     * @brief Raise SVC for exiting from a system call.
+     */
+    void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
 
-/*
- * See header file for description.
- */
-BaseType_t xPortStartScheduler( void )
-{
-    /* An application can install FreeRTOS interrupt handlers in one of the
-     * folllowing ways:
-     * 1. Direct Routing - Install the function xPortPendSVHandler for PendSV
-     *    interrupt.
-     * 2. Indirect Routing - Install separate handler for PendSV interrupt and
-     *    route program control from that handler to xPortPendSVHandler function.
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+    /**
+     * @brief Sets up the task stack so that upon returning from
+     * SVC, the task stack is used again.
      *
-     * Applications that use Indirect Routing must set
-     * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
-     * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
-     * is 1, should be preferred when possible. */
-    #if ( configCHECK_HANDLER_INSTALLATION == 1 )
-    {
-        /* Point pxVectorTable to the interrupt vector table. Systems without
-         * a VTOR register provide the value zero in the VTOR register and
-         * the vector table itself is located at the address 0x00000000. */
-        const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+     * @param pulSystemCallStack The current SP when the SVC was raised.
+     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+     */
+    void vSystemCallExit( uint32_t * pulSystemCallStack,
+                          uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
-        /* Validate that the application has correctly installed the FreeRTOS
-         * handler for PendSV interrupt. We do not check the installation of the
-         * SysTick handler because the application may choose to drive the RTOS
-         * tick using a timer other than the SysTick timer by overriding the
-         * weak function vPortSetupTimerInterrupt().
-         *
-         * Assertion failures here indicate incorrect installation of the
-         * FreeRTOS handler. For help installing the FreeRTOS handler, see
-         * https://www.FreeRTOS.org/FAQHelp.html.
-         *
-         * Systems with a configurable address for the interrupt vector table
-         * can also encounter assertion failures or even system faults here if
-         * VTOR is not set correctly to point to the application's vector table. */
-        configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == xPortPendSVHandler );
-    }
-    #endif /* configCHECK_HANDLER_INSTALLATION */
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
-    /* Make PendSV and SysTick the lowest priority interrupts. */
-    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
-    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+#if ( configENABLE_MPU == 1 )
 
-    /* Start the timer that generates the tick ISR.  Interrupts are disabled
-     * here already. */
-    vPortSetupTimerInterrupt();
+    /**
+     * @brief Checks whether or not the calling task is privileged.
+     *
+     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+     */
+    BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
 
-    /* Initialise the critical nesting count ready for the first task. */
-    uxCriticalNesting = 0;
+#endif /* configENABLE_MPU == 1 */
 
-    /* Start the first task. */
-    vPortStartFirstTask();
-
-    /* Should never get here as the tasks will now be executing!  Call the task
-     * exit error function to prevent compiler warnings about a static function
-     * not being called in the case that the application writer overrides this
-     * functionality by defining configTASK_RETURN_ADDRESS.  Call
-     * vTaskSwitchContext() so link time optimisation does not remove the
-     * symbol. */
-    vTaskSwitchContext();
-    prvTaskExitError();
-
-    /* Should not get here! */
-    return 0;
-}
 /*-----------------------------------------------------------*/
 
-void vPortEndScheduler( void )
-{
-    /* Not implemented in ports where there is nothing to return to.
-     * Artificially force an assert. */
-    configASSERT( uxCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void vPortYield( void )
-{
-    /* Set a PendSV to request a context switch. */
-    portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+    /**
+     * @brief This variable is set to pdTRUE when the scheduler is started.
+     */
+    PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
 
-    /* Barriers are normally not required but do ensure the code is completely
-     * within the specified behaviour for the architecture. */
-    __asm volatile ( "dsb" ::: "memory" );
-    __asm volatile ( "isb" );
-}
-/*-----------------------------------------------------------*/
+#endif
 
-void vPortEnterCritical( void )
-{
-    portDISABLE_INTERRUPTS();
-    uxCriticalNesting++;
-    __asm volatile ( "dsb" ::: "memory" );
-    __asm volatile ( "isb" );
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void )
-{
-    configASSERT( uxCriticalNesting );
-    uxCriticalNesting--;
-
-    if( uxCriticalNesting == 0 )
-    {
-        portENABLE_INTERRUPTS();
-    }
-}
-/*-----------------------------------------------------------*/
-
-uint32_t ulSetInterruptMaskFromISR( void )
-{
-    __asm volatile (
-        " mrs r0, PRIMASK   \n"
-        " cpsid i           \n"
-        " bx lr               "
-        ::: "memory"
-        );
-}
-/*-----------------------------------------------------------*/
-
-void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask )
-{
-    __asm volatile (
-        " msr PRIMASK, r0   \n"
-        " bx lr               "
-        ::: "memory"
-        );
-}
-/*-----------------------------------------------------------*/
-
-void xPortPendSVHandler( void )
-{
-    /* This is a naked function. */
-
-    __asm volatile
-    (
-        "   .syntax unified                     \n"
-        "   mrs r0, psp                         \n"
-        "                                       \n"
-        "   ldr r3, pxCurrentTCBConst           \n" /* Get the location of the current TCB. */
-        "   ldr r2, [r3]                        \n"
-        "                                       \n"
-        "   subs r0, r0, #32                    \n" /* Make space for the remaining low registers. */
-        "   str r0, [r2]                        \n" /* Save the new top of stack. */
-        "   stmia r0!, {r4-r7}                  \n" /* Store the low registers that are not saved automatically. */
-        "   mov r4, r8                          \n" /* Store the high registers. */
-        "   mov r5, r9                          \n"
-        "   mov r6, r10                         \n"
-        "   mov r7, r11                         \n"
-        "   stmia r0!, {r4-r7}                  \n"
-        "                                       \n"
-        "   push {r3, r14}                      \n"
-        "   cpsid i                             \n"
-        "   bl vTaskSwitchContext               \n"
-        "   cpsie i                             \n"
-        "   pop {r2, r3}                        \n" /* lr goes in r3. r2 now holds tcb pointer. */
-        "                                       \n"
-        "   ldr r1, [r2]                        \n"
-        "   ldr r0, [r1]                        \n" /* The first item in pxCurrentTCB is the task top of stack. */
-        "   adds r0, r0, #16                    \n" /* Move to the high registers. */
-        "   ldmia r0!, {r4-r7}                  \n" /* Pop the high registers. */
-        "   mov r8, r4                          \n"
-        "   mov r9, r5                          \n"
-        "   mov r10, r6                         \n"
-        "   mov r11, r7                         \n"
-        "                                       \n"
-        "   msr psp, r0                         \n" /* Remember the new top of stack for the task. */
-        "                                       \n"
-        "   subs r0, r0, #32                    \n" /* Go back for the low registers that are not automatically restored. */
-        "   ldmia r0!, {r4-r7}                  \n" /* Pop low registers.  */
-        "                                       \n"
-        "   bx r3                               \n"
-        "                                       \n"
-        "   .align 4                            \n"
-        "pxCurrentTCBConst: .word pxCurrentTCB    "
-    );
-}
-/*-----------------------------------------------------------*/
-
-void xPortSysTickHandler( void )
-{
-    uint32_t ulPreviousMask;
-
-    ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
-    traceISR_ENTER();
-    {
-        /* Increment the RTOS tick. */
-        if( xTaskIncrementTick() != pdFALSE )
-        {
-            traceISR_EXIT_TO_SCHEDULER();
-            /* Pend a context switch. */
-            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
-        }
-        else
-        {
-            traceISR_EXIT();
-        }
-    }
-    portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Setup the systick timer to generate the tick interrupts at the required
- * frequency.
+/**
+ * @brief Each task maintains its own interrupt status in the critical nesting
+ * variable.
  */
-__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
-{
-    /* Calculate the constants required to configure the tick interrupt. */
-    #if ( configUSE_TICKLESS_IDLE == 1 )
-    {
-        ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
-        xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
-        ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
-    }
-    #endif /* configUSE_TICKLESS_IDLE */
+PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 
-    /* Stop and reset the SysTick. */
-    portNVIC_SYSTICK_CTRL_REG = 0UL;
-    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+#if ( configUSE_TICKLESS_IDLE == 1 )
+
+    /**
+     * @brief The number of SysTick increments that make up one tick period.
+     */
+    PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0;
+
+    /**
+     * @brief The maximum number of tick periods that can be suppressed is
+     * limited by the 24 bit resolution of the SysTick timer.
+     */
+    PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0;
+
+    /**
+     * @brief Compensate for the CPU cycles that pass while the SysTick is
+     * stopped (low power functionality only).
+     */
+    PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0;
+
+#endif /* configUSE_TICKLESS_IDLE */
 
-    /* Configure SysTick to interrupt at the requested rate. */
-    portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
-    portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
-}
 /*-----------------------------------------------------------*/
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
@@ -679,3 +608,1058 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
     }
 
 #endif /* configUSE_TICKLESS_IDLE */
+
+/*-----------------------------------------------------------*/
+
+__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
+{
+    /* Calculate the constants required to configure the tick interrupt. */
+    #if ( configUSE_TICKLESS_IDLE == 1 )
+    {
+        ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+        xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+        ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+    }
+    #endif /* configUSE_TICKLESS_IDLE */
+
+    /* Stop and reset SysTick.
+     *
+     * QEMU versions older than 7.0.0 contain a bug which causes an error if we
+     * enable SysTick without first selecting a valid clock source. We trigger
+     * the bug if we change clock sources from a clock with a zero clock period
+     * to one with a nonzero clock period and enable Systick at the same time.
+     * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit.
+     * This workaround avoids the bug in QEMU versions older than 7.0.0. */
+    portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG;
+    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+    /* Configure SysTick to interrupt at the requested rate. */
+    portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+    portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+}
+
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+    volatile uint32_t ulDummy = 0UL;
+
+    /* A function that implements a task must not exit or attempt to return to
+     * its caller as there is nothing to return to. If a task wants to exit it
+     * should instead call vTaskDelete( NULL ). Artificially force an assert()
+     * to be triggered if configASSERT() is defined, then stop here so
+     * application writers can catch the error. */
+    configASSERT( ulCriticalNesting == ~0UL );
+    portDISABLE_INTERRUPTS();
+
+    while( ulDummy == 0 )
+    {
+        /* This file calls prvTaskExitError() after the scheduler has been
+         * started to remove a compiler warning about the function being
+         * defined but never called.  ulDummy is used purely to quieten other
+         * warnings about code appearing after this function is called - making
+         * ulDummy volatile makes the compiler think the function could return
+         * and therefore not output an 'unreachable code' warning for code that
+         * appears after it. */
+    }
+}
+
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+
+    static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )
+    {
+        uint32_t ulRegionSize, ulReturnValue = 7UL;
+
+        /* 256 is the smallest region size, 31 is the largest valid value for
+         * ulReturnValue. */
+        for( ulRegionSize = 256UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )
+        {
+            if( ulActualSizeInBytes <= ulRegionSize )
+            {
+                break;
+            }
+            else
+            {
+                ulReturnValue++;
+            }
+        }
+
+        /* Shift the code by one before returning so it can be written directly
+         * into the the correct bit position of the attribute register. */
+        return( ulReturnValue << 1UL );
+    }
+
+#endif /* configENABLE_MPU */
+
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+
+    static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
+    {
+        #if defined( __ARMCC_VERSION )
+
+            /* Declaration when these variable are defined in code instead of being
+            * exported from linker scripts. */
+            extern uint32_t * __privileged_functions_start__;
+            extern uint32_t * __privileged_functions_end__;
+            extern uint32_t * __FLASH_segment_start__;
+            extern uint32_t * __FLASH_segment_end__;
+            extern uint32_t * __privileged_sram_start__;
+            extern uint32_t * __privileged_sram_end__;
+
+        #else /* if defined( __ARMCC_VERSION ) */
+
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __privileged_functions_start__[];
+            extern uint32_t __privileged_functions_end__[];
+            extern uint32_t __FLASH_segment_start__[];
+            extern uint32_t __FLASH_segment_end__[];
+            extern uint32_t __privileged_sram_start__[];
+            extern uint32_t __privileged_sram_end__[];
+
+        #endif /* defined( __ARMCC_VERSION ) */
+
+        /* Ensure that the MPU is present. */
+        configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
+
+        /* Check that the MPU is present. */
+        if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
+        {
+            /* Setup privileged flash as Read Only so that privileged tasks can
+             * read it but not modify. */
+            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) | /* Base address. */
+                                 ( portMPU_RBAR_REGION_NUMBER_VALID_BITMASK ) |
+                                 ( portPRIVILEGED_FLASH_REGION ) );
+
+            portMPU_RASR_REG = ( ( portMPU_REGION_PRIV_RO_UNPRIV_NA ) |
+                                 ( ( configS_C_B_FLASH & portMPU_RASR_S_C_B_BITMASK ) << portMPU_RASR_S_C_B_LOCATION ) |
+                                 ( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __privileged_functions_start__ ) ) |
+                                 ( portMPU_RASR_REGION_ENABLE_BITMASK ) );
+
+            /* Setup unprivileged flash as Read Only by both privileged and
+             * unprivileged tasks. All tasks can read it but no-one can modify. */
+            portMPU_RBAR_REG = ( ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
+                                 ( portMPU_RBAR_REGION_NUMBER_VALID_BITMASK ) |
+                                 ( portUNPRIVILEGED_FLASH_REGION ) );
+
+            portMPU_RASR_REG = ( ( portMPU_REGION_PRIV_RO_UNPRIV_RO ) |
+                                 ( ( configS_C_B_FLASH & portMPU_RASR_S_C_B_BITMASK ) << portMPU_RASR_S_C_B_LOCATION ) |
+                                 ( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
+                                 ( portMPU_RASR_REGION_ENABLE_BITMASK ) );
+
+            /* Setup RAM containing kernel data for privileged access only. */
+            portMPU_RBAR_REG = ( ( uint32_t ) __privileged_sram_start__ ) | /* Base address. */
+                                 ( portMPU_RBAR_REGION_NUMBER_VALID_BITMASK ) |
+                                 ( portPRIVILEGED_RAM_REGION );
+
+            portMPU_RASR_REG = ( ( portMPU_REGION_PRIV_RW_UNPRIV_NA ) |
+                                 ( portMPU_REGION_EXECUTE_NEVER ) |
+                                 ( ( configS_C_B_SRAM & portMPU_RASR_S_C_B_BITMASK ) << portMPU_RASR_S_C_B_LOCATION ) |
+                                 prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_sram_end__ - ( uint32_t ) __privileged_sram_start__ ) |
+                                 ( portMPU_RASR_REGION_ENABLE_BITMASK ) );
+
+            /* Enable MPU with privileged background access i.e. unmapped
+             * regions have privileged access. */
+            portMPU_CTRL_REG |= ( portMPU_CTRL_PRIV_BACKGROUND_ENABLE_BITMASK |
+                                  portMPU_CTRL_ENABLE_BITMASK );
+        }
+    }
+
+#endif /* configENABLE_MPU */
+
+/*-----------------------------------------------------------*/
+
+void vPortYield( void ) /* PRIVILEGED_FUNCTION */
+{
+    /* Set a PendSV to request a context switch. */
+    portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+
+    /* Barriers are normally not required but do ensure the code is
+     * completely within the specified behaviour for the architecture. */
+    __asm volatile ( "dsb" ::: "memory" );
+    __asm volatile ( "isb" );
+}
+
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+    portDISABLE_INTERRUPTS();
+    ulCriticalNesting++;
+
+    /* Barriers are normally not required but do ensure the code is
+     * completely within the specified behaviour for the architecture. */
+    __asm volatile ( "dsb" ::: "memory" );
+    __asm volatile ( "isb" );
+}
+
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+    configASSERT( ulCriticalNesting );
+    ulCriticalNesting--;
+
+    if( ulCriticalNesting == 0 )
+    {
+        portENABLE_INTERRUPTS();
+    }
+}
+
+/*-----------------------------------------------------------*/
+
+void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
+{
+    uint32_t ulPreviousMask;
+
+    ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+
+    traceISR_ENTER();
+    {
+        /* Increment the RTOS tick. */
+        if( xTaskIncrementTick() != pdFALSE )
+        {
+            traceISR_EXIT_TO_SCHEDULER();
+            /* Pend a context switch. */
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+        }
+        else
+        {
+            traceISR_EXIT();
+        }
+    }
+
+    portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
+}
+
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */
+{
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+
+        #if defined( __ARMCC_VERSION )
+
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+
+        #else
+
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+
+        #endif /* defined( __ARMCC_VERSION ) */
+
+    #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+
+    uint32_t ulPC;
+    uint8_t ucSVCNumber;
+
+    /* Register are stored on the stack in the following order - R0, R1, R2, R3,
+     * R12, LR, PC, xPSR. */
+    ulPC = pulCallerStackAddress[ portOFFSET_TO_PC ];
+    ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];
+
+    switch( ucSVCNumber )
+    {
+        case portSVC_START_SCHEDULER:
+            /* Setup the context of the first task so that the first task starts
+             * executing. */
+            vRestoreContextOfFirstTask();
+            break;
+
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+
+        case portSVC_RAISE_PRIVILEGE:
+            /* Only raise the privilege, if the svc was raised from any of
+             * the system calls. */
+            if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+                ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+            {
+                vRaisePrivilege();
+            }
+            break;
+
+    #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+
+    #if ( configENABLE_MPU == 1 )
+
+        case portSVC_YIELD:
+            vPortYield();
+            break;
+
+    #endif /* configENABLE_MPU == 1 */
+
+        default:
+            /* Incorrect SVC call. */
+            configASSERT( pdFALSE );
+    }
+}
+
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+    void vSystemCallEnter( uint32_t * pulTaskStack,
+                           uint32_t ulLR,
+                           uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */
+    {
+        extern TaskHandle_t pxCurrentTCB;
+        extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ];
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulSystemCallStack;
+        uint32_t ulSystemCallLocation, i;
+        const uint32_t ulStackFrameSize = 8;
+
+        #if defined( __ARMCC_VERSION )
+
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+
+        #else
+
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+
+        /* Checks:
+         * 1. SVC is raised from the system call section (i.e. application is
+         *    not raising SVC directly).
+         * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as
+         *    it is non-NULL only during the execution of a system call (i.e.
+         *    between system call enter and exit).
+         * 3. System call is not for a kernel API disabled by the configuration
+         *    in FreeRTOSConfig.h.
+         * 4. We do not need to check that ucSystemCallNumber is within range
+         *    because the assembly SVC handler checks that before calling
+         *    this function.
+         */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) &&
+            ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) &&
+            ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) )
+        {
+            pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+
+            /* Make space on the system call stack for the stack frame. */
+            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulSystemCallStack[ i ] = pulTaskStack[ i ];
+            }
+
+            /* Store the value of the Link Register before the SVC was raised.
+             * It contains the address of the caller of the System Call entry
+             * point (i.e. the caller of the MPU_<API>). We need to restore it
+             * when we exit from the system call. */
+            pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+
+            /* Use the pulSystemCallStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
+
+            /* Start executing the system call upon returning from this handler. */
+            pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
+
+            /* Raise a request to exit from the system call upon finishing the
+             * system call. */
+            pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit;
+
+            /* Remember the location where we should copy the stack frame when we exit from
+             * the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+
+            /* Record if the hardware used padding to force the stack pointer
+             * to be double word aligned. */
+            if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
+            {
+                pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
+            }
+            else
+            {
+                pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
+            }
+
+            /* We ensure in pxPortInitialiseStack that the system call stack is
+             * double word aligned and therefore, there is no need of padding.
+             * Clear the bit[9] of stacked xPSR. */
+            pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
+
+            /* Raise the privilege for the duration of the system call. */
+            __asm volatile
+            (
+                " .syntax unified     \n"
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " bics r0, r1         \n" /* Clear nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+            );
+        }
+    }
+
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+    void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" );
+    }
+
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+    void vSystemCallExit( uint32_t * pulSystemCallStack,
+                          uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
+    {
+        extern TaskHandle_t pxCurrentTCB;
+        xMPU_SETTINGS * pxMpuSettings;
+        uint32_t * pulTaskStack;
+        uint32_t ulSystemCallLocation, i;
+        const uint32_t ulStackFrameSize = 8;
+
+        #if defined( __ARMCC_VERSION )
+
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __privileged_functions_start__;
+            extern uint32_t * __privileged_functions_end__;
+
+        #else
+
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __privileged_functions_start__[];
+            extern uint32_t __privileged_functions_end__[];
+
+        #endif /* #if defined( __ARMCC_VERSION ) */
+
+        ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
+        pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+
+        /* Checks:
+         * 1. SVC is raised from the privileged code (i.e. application is not
+         *    raising SVC directly). This SVC is only raised from
+         *    vRequestSystemCallExit which is in the privileged code section.
+         * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL -
+         *    this means that we previously entered a system call and the
+         *    application is not attempting to exit without entering a system
+         *    call.
+         */
+        if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) &&
+            ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) &&
+            ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) )
+        {
+            pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
+
+            /* Make space on the task stack for the stack frame. */
+            pulTaskStack = pulTaskStack - ulStackFrameSize;
+
+            /* Copy the stack frame. */
+            for( i = 0; i < ulStackFrameSize; i++ )
+            {
+                pulTaskStack[ i ] = pulSystemCallStack[ i ];
+            }
+
+            /* Use the pulTaskStack in thread mode. */
+            __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
+
+            /* Return to the caller of the System Call entry point (i.e. the
+             * caller of the MPU_<API>). */
+            pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+
+            /* Ensure that LR has a valid value.*/
+            pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+
+            /* If the hardware used padding to force the stack pointer
+             * to be double word aligned, set the stacked xPSR bit[9],
+             * otherwise clear it. */
+            if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG )
+            {
+                pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK;
+            }
+            else
+            {
+                pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
+            }
+
+            /* This is not NULL only for the duration of the system call. */
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
+
+            /* Drop the privilege before returning to the thread mode. */
+            __asm volatile
+            (
+                " .syntax unified     \n"
+                " mrs r0, control     \n" /* Obtain current control value. */
+                " movs r1, #1         \n" /* r1 = 1. */
+                " orrs r0, r1         \n" /* Set nPRIV bit. */
+                " msr control, r0     \n" /* Write back new control value. */
+                ::: "r0", "r1", "memory"
+            );
+        }
+    }
+
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+
+    BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */
+    {
+        BaseType_t xTaskIsPrivileged = pdFALSE;
+        const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+        if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+        {
+            xTaskIsPrivileged = pdTRUE;
+        }
+
+        return xTaskIsPrivileged;
+    }
+
+#endif /* configENABLE_MPU == 1 */
+
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters,
+                                         BaseType_t xRunPrivileged,
+                                         xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
+    {
+        xMPUSettings->ulContext[ 0 ] = 0x04040404; /* r4. */
+        xMPUSettings->ulContext[ 1 ] = 0x05050505; /* r5. */
+        xMPUSettings->ulContext[ 2 ] = 0x06060606; /* r6. */
+        xMPUSettings->ulContext[ 3 ] = 0x07070707; /* r7. */
+        xMPUSettings->ulContext[ 4 ] = 0x08080808; /* r8. */
+        xMPUSettings->ulContext[ 5 ] = 0x09090909; /* r9. */
+        xMPUSettings->ulContext[ 6 ] = 0x10101010; /* r10. */
+        xMPUSettings->ulContext[ 7 ] = 0x11111111; /* r11. */
+
+        xMPUSettings->ulContext[ 8 ] = ( uint32_t ) pvParameters;            /* r0. */
+        xMPUSettings->ulContext[ 9 ] = 0x01010101;                           /* r1. */
+        xMPUSettings->ulContext[ 10 ] = 0x02020202;                           /* r2. */
+        xMPUSettings->ulContext[ 11 ] = 0x03030303;                           /* r3. */
+        xMPUSettings->ulContext[ 12 ] = 0x12121212;                           /* r12. */
+        xMPUSettings->ulContext[ 13 ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
+        xMPUSettings->ulContext[ 14 ] = ( uint32_t ) pxCode;                  /* PC. */
+        xMPUSettings->ulContext[ 15 ] = portINITIAL_XPSR;                     /* xPSR. */
+
+        xMPUSettings->ulContext[ 16 ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
+        if( xRunPrivileged == pdTRUE )
+        {
+            xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
+            xMPUSettings->ulContext[ 17 ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+        }
+        else
+        {
+            xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
+            xMPUSettings->ulContext[ 17 ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+        }
+        xMPUSettings->ulContext[ 18 ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
+
+        #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+        {
+            /* Ensure that the system call stack is double word aligned. */
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] );
+            xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) &
+                                                                                     ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
+
+            /* This is not NULL only for the duration of a system call. */
+            xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL;
+        }
+        #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
+
+        return &( xMPUSettings->ulContext[ 19 ] );
+    }
+
+#else /* configENABLE_MPU */
+
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters ) /* PRIVILEGED_FUNCTION */
+    {
+        /* Simulate the stack frame as it would be created by a context switch
+         * interrupt. */
+        #if ( portPRELOAD_REGISTERS == 0 )
+        {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
+            pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
+            *pxTopOfStack = portINITIAL_EXC_RETURN;
+        }
+        #else /* portPRELOAD_REGISTERS */
+        {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
+            pxTopOfStack--;
+            *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
+        }
+        #endif /* portPRELOAD_REGISTERS */
+
+        return pxTopOfStack;
+    }
+
+#endif /* configENABLE_MPU */
+
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+    /* An application can install FreeRTOS interrupt handlers in one of the
+     * folllowing ways:
+     * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
+     *    for SVCall and PendSV interrupts respectively.
+     * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+     *    interrupts and route program control from those handlers to
+     *    SVC_Handler and PendSV_Handler functions.
+     *
+     * Applications that use Indirect Routing must set
+     * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+     * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+     * is 1, should be preferred when possible. */
+    #if ( configCHECK_HANDLER_INSTALLATION == 1 )
+    {
+        const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+        /* Validate that the application has correctly installed the FreeRTOS
+         * handlers for SVCall and PendSV interrupts. We do not check the
+         * installation of the SysTick handler because the application may
+         * choose to drive the RTOS tick using a timer other than the SysTick
+         * timer by overriding the weak function vPortSetupTimerInterrupt().
+         *
+         * Assertion failures here indicate incorrect installation of the
+         * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+         * https://www.FreeRTOS.org/FAQHelp.html.
+         *
+         * Systems with a configurable address for the interrupt vector table
+         * can also encounter assertion failures or even system faults here if
+         * VTOR is not set correctly to point to the application's vector table. */
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler );
+        configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler );
+    }
+    #endif /* configCHECK_HANDLER_INSTALLATION */
+
+    /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
+     * the highest priority. */
+    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
+    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+    portNVIC_SHPR2_REG = 0;
+
+    #if ( configENABLE_MPU == 1 )
+    {
+        /* Setup the Memory Protection Unit (MPU). */
+        prvSetupMPU();
+    }
+    #endif /* configENABLE_MPU */
+
+    /* Start the timer that generates the tick ISR. Interrupts are disabled
+     * here already. */
+    vPortSetupTimerInterrupt();
+
+    /* Initialize the critical nesting count ready for the first task. */
+    ulCriticalNesting = 0;
+
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+    {
+        xSchedulerRunning = pdTRUE;
+    }
+    #endif
+
+    /* Start the first task. */
+    vStartFirstTask();
+
+    /* Should never get here as the tasks will now be executing. Call the task
+     * exit error function to prevent compiler warnings about a static function
+     * not being called in the case that the application writer overrides this
+     * functionality by defining configTASK_RETURN_ADDRESS. Call
+     * vTaskSwitchContext() so link time optimization does not remove the
+     * symbol. */
+    vTaskSwitchContext();
+    prvTaskExitError();
+
+    /* Should not get here. */
+    return 0;
+}
+
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+    /* Not implemented in ports where there is nothing to return to.
+     * Artificially force an assert. */
+    configASSERT( ulCriticalNesting == 1000UL );
+}
+
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+
+    void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
+                                    const struct xMEMORY_REGION * const xRegions,
+                                    StackType_t * pxBottomOfStack,
+                                    configSTACK_DEPTH_TYPE uxStackDepth )
+    {
+        #if defined( __ARMCC_VERSION )
+
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __SRAM_segment_start__;
+            extern uint32_t * __SRAM_segment_end__;
+            extern uint32_t * __privileged_sram_start__;
+            extern uint32_t * __privileged_sram_end__;
+
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __SRAM_segment_start__[];
+            extern uint32_t __SRAM_segment_end__[];
+            extern uint32_t __privileged_sram_start__[];
+            extern uint32_t __privileged_sram_end__[];
+
+        #endif /* defined( __ARMCC_VERSION ) */
+
+        int32_t lIndex;
+        uint32_t ul;
+
+        if( xRegions == NULL )
+        {
+            /* No MPU regions are specified so allow access to all RAM. */
+            xMPUSettings->xRegionsSettings[ 0 ].ulRBAR =
+                ( ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */
+                  ( portMPU_RBAR_REGION_NUMBER_VALID_BITMASK ) |
+                  ( portSTACK_REGION ) );                   /* Region number. */
+
+            xMPUSettings->xRegionsSettings[ 0 ].ulRASR =
+                ( ( portMPU_REGION_PRIV_RW_UNPRIV_RW ) |
+                  ( portMPU_REGION_EXECUTE_NEVER ) |
+                  ( ( configS_C_B_SRAM & portMPU_RASR_S_C_B_BITMASK ) << portMPU_RASR_S_C_B_LOCATION ) |
+                  ( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |
+                  ( portMPU_RASR_REGION_ENABLE_BITMASK ) );
+
+
+            /* Invalidate user configurable regions. */
+            for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
+            {
+                xMPUSettings->xRegionsSettings[ ul ].ulRBAR = ( ( ul - 1UL ) | portMPU_RBAR_REGION_NUMBER_VALID_BITMASK );
+                xMPUSettings->xRegionsSettings[ ul ].ulRASR = 0UL;
+            }
+        }
+        else
+        {
+            /* This function is called automatically when the task is created - in
+             * which case the stack region parameters will be valid.  At all other
+             * times the stack parameters will not be valid and it is assumed that the
+             * stack region has already been configured. */
+            if( uxStackDepth > 0 )
+            {
+                /* Define the region that allows access to the stack. */
+                xMPUSettings->xRegionsSettings[ 0 ].ulRBAR =
+                    ( ( ( uint32_t ) pxBottomOfStack ) |
+                      ( portMPU_RBAR_REGION_NUMBER_VALID_BITMASK ) |
+                      ( portSTACK_REGION ) ); /* Region number. */
+
+                xMPUSettings->xRegionsSettings[ 0 ].ulRASR =
+                    ( ( portMPU_REGION_PRIV_RW_UNPRIV_RW ) |
+                      ( portMPU_REGION_EXECUTE_NEVER ) |
+                      ( prvGetMPURegionSizeSetting( uxStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |
+                      ( ( configS_C_B_SRAM & portMPU_RASR_S_C_B_BITMASK ) << portMPU_RASR_S_C_B_LOCATION ) |
+                      ( portMPU_RASR_REGION_ENABLE_BITMASK ) );
+            }
+
+            lIndex = 0;
+
+            for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
+            {
+                if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )
+                {
+                    /* Translate the generic region definition contained in
+                     * xRegions into the CM0+ specific MPU settings that are then
+                     * stored in xMPUSettings. */
+                    xMPUSettings->xRegionsSettings[ ul ].ulRBAR =
+                        ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |
+                        ( portMPU_RBAR_REGION_NUMBER_VALID_BITMASK ) |
+                        ( ul - 1UL ); /* Region number. */
+
+                    xMPUSettings->xRegionsSettings[ ul ].ulRASR =
+                        ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |
+                        ( xRegions[ lIndex ].ulParameters ) |
+                        ( portMPU_RASR_REGION_ENABLE_BITMASK );
+                }
+                else
+                {
+                    /* Invalidate the region. */
+                    xMPUSettings->xRegionsSettings[ ul ].ulRBAR = ( ( ul - 1UL ) | portMPU_RBAR_REGION_NUMBER_VALID_BITMASK );
+                    xMPUSettings->xRegionsSettings[ ul ].ulRASR = 0UL;
+                }
+
+            lIndex++;
+        }
+    }
+}
+
+#endif /* configENABLE_MPU */
+
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+    BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
+                                                uint32_t ulBufferLength,
+                                                uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
+
+    {
+        uint32_t i, ulBufferStartAddress, ulBufferEndAddress;
+        uint32_t ulRegionStart, ulRegionSize, ulRegionEnd;
+        uint32_t ulMPURegionAccessPermissions;
+        BaseType_t xAccessGranted = pdFALSE;
+        const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+        if( xSchedulerRunning == pdFALSE )
+        {
+            /* Grant access to all the kernel objects before the scheduler
+             * is started. It is necessary because there is no task running
+             * yet and therefore, we cannot use the permissions of any
+             * task. */
+            xAccessGranted = pdTRUE;
+        }
+        else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+        {
+            xAccessGranted = pdTRUE;
+        }
+        else
+        {
+            if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE )
+            {
+                ulBufferStartAddress = ( uint32_t ) pvBuffer;
+                ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL );
+
+                for( i = 0; i < portTOTAL_NUM_REGIONS; i++ )
+                {
+                    /* Is the MPU region enabled? */
+                    if( ( xTaskMpuSettings->xRegionsSettings[ i ].ulRASR &
+                          portMPU_RASR_REGION_ENABLE_BITMASK ) == portMPU_RASR_REGION_ENABLE_BITMASK )
+                    {
+                        ulRegionStart = portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR );
+                        ulRegionSize = portEXTRACT_REGION_SIZE_FROM_RASR( xTaskMpuSettings->xRegionsSettings[ i ].ulRASR );
+                        ulRegionEnd = ulRegionStart + ulRegionSize;
+
+                        if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress,
+                                                         ulRegionStart,
+                                                         ulRegionEnd ) &&
+                            portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress,
+                                                         ulRegionStart,
+                                                         ulRegionEnd ) )
+                        {
+                            ulMPURegionAccessPermissions = xTaskMpuSettings->xRegionsSettings[ i ].ulRASR &
+                                                           portMPU_RASR_AP_BITMASK;
+
+                            if( ulAccessRequested == tskMPU_READ_PERMISSION ) /* RO. */
+                            {
+                                if( ( ulMPURegionAccessPermissions == portMPU_REGION_PRIV_RW_UNPRIV_RO ) ||
+                                    ( ulMPURegionAccessPermissions == portMPU_REGION_PRIV_RO_UNPRIV_RO ) ||
+                                    ( ulMPURegionAccessPermissions == portMPU_REGION_PRIV_RW_UNPRIV_RW ) )
+                                {
+                                    xAccessGranted = pdTRUE;
+                                    break;
+                                }
+                            }
+                            else if( ( ulAccessRequested & tskMPU_WRITE_PERMISSION ) != 0UL ) /* W or RW. */
+                            {
+                                if( ulMPURegionAccessPermissions == portMPU_REGION_PRIV_RW_UNPRIV_RW )
+                                {
+                                    xAccessGranted = pdTRUE;
+                                    break;
+                                }
+                            }
+                        }
+                    }
+                }
+            }
+        }
+
+        return xAccessGranted;
+    }
+
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
+
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortIsInsideInterrupt( void )
+{
+    uint32_t ulCurrentInterrupt;
+    BaseType_t xReturn;
+
+    /* Obtain the number of the currently executing interrupt. Interrupt Program
+     * Status Register (IPSR) holds the exception number of the currently-executing
+     * exception or zero for Thread mode.*/
+    __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+    if( ulCurrentInterrupt == 0 )
+    {
+        xReturn = pdFALSE;
+    }
+    else
+    {
+        xReturn = pdTRUE;
+    }
+
+    return xReturn;
+}
+
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+    void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+                                         int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+    {
+        uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+        xMPU_SETTINGS * xTaskMpuSettings;
+
+        ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+        ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+        xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+        xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit );
+    }
+
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+    void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+                                          int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+    {
+        uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+        xMPU_SETTINGS * xTaskMpuSettings;
+
+        ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+        ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+        xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+        xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit );
+    }
+
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+    #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+
+        BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+        {
+            uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+            BaseType_t xAccessGranted = pdFALSE;
+            const xMPU_SETTINGS * xTaskMpuSettings;
+
+            if( xSchedulerRunning == pdFALSE )
+            {
+                /* Grant access to all the kernel objects before the scheduler
+                 * is started. It is necessary because there is no task running
+                 * yet and therefore, we cannot use the permissions of any
+                 * task. */
+                xAccessGranted = pdTRUE;
+            }
+            else
+            {
+                xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+                ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+                ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+                if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+                {
+                    xAccessGranted = pdTRUE;
+                }
+                else
+                {
+                    if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+                    {
+                        xAccessGranted = pdTRUE;
+                    }
+                }
+            }
+
+            return xAccessGranted;
+        }
+
+    #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+        BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+        {
+            ( void ) lInternalIndexOfKernelObject;
+
+            /* If Access Control List feature is not used, all the tasks have
+             * access to all the kernel objects. */
+            return pdTRUE;
+        }
+
+    #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
+
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM0/portasm.c b/portable/GCC/ARM_CM0/portasm.c
new file mode 100644
index 000000000..be1500ef0
--- /dev/null
+++ b/portable/GCC/ARM_CM0/portasm.c
@@ -0,0 +1,523 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
+ * is defined correctly and privileged functions are placed in correct sections. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Portasm includes. */
+#include "portasm.h"
+
+/* System call numbers includes. */
+#include "mpu_syscall_numbers.h"
+
+/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
+ * header files. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#if ( configENABLE_MPU == 1 )
+
+    void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            " .extern pxCurrentTCB                            \n"
+            " .syntax unified                                 \n"
+            "                                                 \n"
+            " program_mpu_first_task:                         \n"
+            "                                                 \n"
+            "    ldr r3, =pxCurrentTCB                        \n" /* r3 = &pxCurrentTCB. */
+            "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB.*/
+            "    adds r0, #4                                  \n" /* r0 = Second item in the TCB which is xMPUSettings. */
+            "                                                 \n"
+            "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
+            "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
+            "    movs r3, #1                                  \n" /* r3 = 1. */
+            "    bics r2, r3                                  \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
+            "    str r2, [r1]                                 \n" /* Disable MPU. */
+            "                                                 \n"
+            "    ldr r1, =0xe000ed9c                          \n" /* r1 = 0xe000ed9c [Location of RBAR]. */
+            "    ldr r2, =0xe000eda0                          \n" /* r2 = 0xe000eda0 [Location of RASR]. */
+            "                                                 \n"
+            "    ldmia r0!, {r3-r4}                           \n" /* Read first set of RBAR/RASR registers from TCB. */
+            "    str r3, [r1]                                 \n" /* Program RBAR. */
+            "    str r4, [r2]                                 \n" /* Program RASR. */
+            "                                                 \n"
+            "    ldmia r0!, {r3-r4}                           \n" /* Read second set of RBAR/RASR registers from TCB. */
+            "    str r3, [r1]                                 \n" /* Program RBAR. */
+            "    str r4, [r2]                                 \n" /* Program RASR. */
+            "                                                 \n"
+            "    ldmia r0!, {r3-r4}                           \n" /* Read third set of RBAR/RASR registers from TCB. */
+            "    str r3, [r1]                                 \n" /* Program RBAR. */
+            "    str r4, [r2]                                 \n" /* Program RASR. */
+            "                                                 \n"
+            "    ldmia r0!, {r3-r4}                           \n" /* Read fourth set of RBAR/RASR registers from TCB. */
+            "    str r3, [r1]                                 \n" /* Program RBAR. */
+            "    str r4, [r2]                                 \n" /* Program RASR. */
+            "                                                 \n"
+            "    ldmia r0!, {r3-r4}                           \n" /* Read fifth set of RBAR/RASR registers from TCB. */
+            "    str r3, [r1]                                 \n" /* Program RBAR. */
+            "    str r4, [r2]                                 \n" /* Program RASR. */
+            "                                                 \n"
+            "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
+            "    movs r3, #1                                  \n" /* r3 = 1. */
+            "    orrs r2, r3                                  \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
+            "    str r2, [r1]                                 \n" /* Enable MPU. */
+            "    dsb                                          \n" /* Force memory writes before continuing. */
+            "                                                 \n"
+            " restore_context_first_task:                     \n"
+            "    ldr r2, =pxCurrentTCB                        \n" /* r2 = &pxCurrentTCB. */
+            "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB.*/
+            "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
+            "                                                 \n"
+            " restore_special_regs_first_task:                \n"
+            "    subs r1, #12                                 \n"
+            "    ldmia r1!, {r2-r4}                           \n" /* r2 = original PSP, r3 = CONTROL, r4 = LR. */
+            "    subs r1, #12                                 \n"
+            "    msr psp, r2                                  \n"
+            "    msr control, r3                              \n"
+            "    mov lr, r4                                   \n"
+            "                                                 \n"
+            " restore_general_regs_first_task:                \n"
+            "    subs r1, #32                                 \n"
+            "    ldmia r1!, {r4-r7}                           \n" /* r4-r7 contain half of the hardware saved context. */
+            "    stmia r2!, {r4-r7}                           \n" /* Copy half of the the hardware saved context on the task stack. */
+            "    ldmia r1!, {r4-r7}                           \n" /* r4-r7 contain rest half of the hardware saved context. */
+            "    stmia r2!, {r4-r7}                           \n" /* Copy rest half of the the hardware saved context on the task stack. */
+            "    subs r1, #48                                 \n"
+            "    ldmia r1!, {r4-r7}                           \n" /* Restore r8-r11. */
+            "    mov r8, r4                                   \n" /* r8 = r4. */
+            "    mov r9, r5                                   \n" /* r9 = r5. */
+            "    mov r10, r6                                  \n" /* r10 = r6. */
+            "    mov r11, r7                                  \n" /* r11 = r7. */
+            "    subs r1, #32                                 \n"
+            "    ldmia r1!, {r4-r7}                           \n" /* Restore r4-r7. */
+            "    subs r1, #16                                 \n"
+            "                                                 \n"
+            " restore_context_done_first_task:                \n"
+            "    str r1, [r0]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
+            "    bx lr                                        \n"
+            "                                                 \n"
+            " .align 4                                        \n"
+            ::"i" ( portSVC_START_SCHEDULER ) : "memory"
+        );
+    }
+
+#else /* configENABLE_MPU */
+
+    void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            " .extern pxCurrentTCB                            \n"
+            " .syntax unified                                 \n"
+            "                                                 \n"
+            " ldr  r2, =pxCurrentTCB                          \n" /* r2 = &pxCurrentTCB. */
+            " ldr  r1, [r2]                                   \n" /* r1 = pxCurrentTCB.*/
+            " ldr  r0, [r1]                                   \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+            "                                                 \n"
+            " ldm  r0!, {r2}                                  \n" /* Read from stack - r2 = EXC_RETURN. */
+            " movs r1, #2                                     \n" /* r1 = 2. */
+            " msr  CONTROL, r1                                \n" /* Switch to use PSP in the thread mode. */
+            " adds r0, #32                                    \n" /* Discard everything up to r0. */
+            " msr  psp, r0                                    \n" /* This is now the new top of stack to use in the task. */
+            " isb                                             \n"
+            " bx   r2                                         \n" /* Finally, branch to EXC_RETURN. */
+            "                                                 \n"
+            " .align 4                                        \n"
+        );
+    }
+
+#endif /* configENABLE_MPU */
+
+/*-----------------------------------------------------------*/
+
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
+{
+    __asm volatile
+    (
+        " .syntax unified                                 \n"
+        "                                                 \n"
+        " mrs r0, control                                 \n" /* r0 = CONTROL. */
+        " movs r1, #1                                     \n" /* r1 = 1. */
+        " tst r0, r1                                      \n" /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
+        " beq running_privileged                          \n" /* If the result of previous AND operation was 0, branch. */
+        " movs r0, #0                                     \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+        " bx lr                                           \n" /* Return. */
+        " running_privileged:                             \n"
+        "    movs r0, #1                                  \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+        "    bx lr                                        \n" /* Return. */
+        "                                                 \n"
+        " .align 4                                        \n"
+        ::: "r0", "r1", "memory"
+    );
+}
+
+/*-----------------------------------------------------------*/
+
+void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        " .syntax unified                                 \n"
+        "                                                 \n"
+        " mrs  r0, control                                \n" /* Read the CONTROL register. */
+        " movs r1, #1                                     \n" /* r1 = 1. */
+        " bics r0, r1                                     \n" /* Clear the bit 0. */
+        " msr  control, r0                                \n" /* Write back the new CONTROL value. */
+        " bx lr                                           \n" /* Return to the caller. */
+        ::: "r0", "r1", "memory"
+    );
+}
+
+/*-----------------------------------------------------------*/
+
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */
+{
+    __asm volatile
+    (
+        " .syntax unified                                 \n"
+        "                                                 \n"
+        " mrs r0, control                                 \n" /* r0 = CONTROL. */
+        " movs r1, #1                                     \n" /* r1 = 1. */
+        " orrs r0, r1                                     \n" /* r0 = r0 | r1. */
+        " msr control, r0                                 \n" /* CONTROL = r0. */
+        " bx lr                                           \n" /* Return to the caller. */
+        ::: "r0", "r1", "memory"
+    );
+}
+
+/*-----------------------------------------------------------*/
+
+void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    /* Don't reset the MSP stack as is done on CM3/4 devices. The reason is that
+     * the Vector Table Offset Register (VTOR) is optional in CM0+ architecture
+     * and therefore, may not be available on all the devices. */
+    __asm volatile
+    (
+        " .syntax unified                                 \n"
+        " cpsie i                                         \n" /* Globally enable interrupts. */
+        " dsb                                             \n"
+        " isb                                             \n"
+        " svc %0                                          \n" /* System call to start the first task. */
+        " nop                                             \n"
+        "                                                 \n"
+        " .align 4                                        \n"
+        ::"i" ( portSVC_START_SCHEDULER ) : "memory"
+    );
+}
+
+/*-----------------------------------------------------------*/
+
+uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        " .syntax unified                                 \n"
+        "                                                 \n"
+        " mrs r0, PRIMASK                                 \n"
+        " cpsid i                                         \n"
+        " bx lr                                           \n"
+        ::: "memory"
+    );
+}
+
+/*-----------------------------------------------------------*/
+
+void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        " .syntax unified                                 \n"
+        "                                                 \n"
+        " msr PRIMASK, r0                                 \n"
+        " bx lr                                           \n"
+        ::: "memory"
+    );
+}
+
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+
+    void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            " .extern pxCurrentTCB                            \n"
+            " .syntax unified                                 \n"
+            "                                                 \n"
+            " ldr r2, =pxCurrentTCB                           \n" /* r2 = &( pxCurrentTCB ). */
+            " ldr r0, [r2]                                    \n" /* r0 = pxCurrentTCB. */
+            " ldr r1, [r0]                                    \n" /* r1 = Location in TCB where the context should be saved. */
+            " mrs r2, psp                                     \n" /* r2 = PSP. */
+            "                                                 \n"
+            " save_general_regs:                              \n"
+            "    stmia r1!, {r4-r7}                           \n" /* Store r4-r7. */
+            "    mov r4, r8                                   \n" /* r4 = r8. */
+            "    mov r5, r9                                   \n" /* r5 = r9. */
+            "    mov r6, r10                                  \n" /* r6 = r10. */
+            "    mov r7, r11                                  \n" /* r7 = r11. */
+            "    stmia r1!, {r4-r7}                           \n" /* Store r8-r11. */
+            "    ldmia r2!, {r4-r7}                           \n" /* Copy half of the  hardware saved context into r4-r7. */
+            "    stmia r1!, {r4-r7}                           \n" /* Store the hardware saved context. */
+            "    ldmia r2!, {r4-r7}                           \n" /* Copy rest half of the  hardware saved context into r4-r7. */
+            "    stmia r1!, {r4-r7}                           \n" /* Store the hardware saved context. */
+            "                                                 \n"
+            " save_special_regs:                              \n"
+            "    mrs r2, psp                                  \n" /* r2 = PSP. */
+            "    mrs r3, control                              \n" /* r3 = CONTROL. */
+            "    mov r4, lr                                   \n" /* r4 = LR. */
+            "    stmia r1!, {r2-r4}                           \n" /* Store original PSP (after hardware has saved context), CONTROL and LR. */
+            "    str r1, [r0]                                 \n" /* Save the location from where the context should be restored as the first member of TCB. */
+            "                                                 \n"
+            " select_next_task:                               \n"
+            "    cpsid i                                      \n"
+            "    bl vTaskSwitchContext                        \n"
+            "    cpsie i                                      \n"
+            "                                                 \n"
+            " program_mpu:                                    \n"
+            "                                                 \n"
+            "    ldr r2, =pxCurrentTCB                        \n" /* r2 = &( pxCurrentTCB ). */
+            "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB. */
+            "    adds r0, #4                                  \n" /* r0 = Second item in the TCB which is xMPUSettings. */
+            "                                                 \n"
+            "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
+            "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
+            "    movs r3, #1                                  \n" /* r3 = 1. */
+            "    bics r2, r3                                  \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
+            "    str r2, [r1]                                 \n" /* Disable MPU */
+            "                                                 \n"
+            "    ldr r1, =0xe000ed9c                          \n" /* r1 = 0xe000ed9c [Location of RBAR]. */
+            "    ldr r2, =0xe000eda0                          \n" /* r2 = 0xe000eda0 [Location of RASR]. */
+            "                                                 \n"
+            "    ldmia r0!, {r3-r4}                           \n" /* Read first set of RBAR/RASR registers from TCB. */
+            "    str r3, [r1]                                 \n" /* Program RBAR. */
+            "    str r4, [r2]                                 \n" /* Program RASR. */
+            "                                                 \n"
+            "    ldmia r0!, {r3-r4}                           \n" /* Read second set of RBAR/RASR registers from TCB. */
+            "    str r3, [r1]                                 \n" /* Program RBAR. */
+            "    str r4, [r2]                                 \n" /* Program RASR. */
+            "                                                 \n"
+            "    ldmia r0!, {r3-r4}                           \n" /* Read third set of RBAR/RASR registers from TCB. */
+            "    str r3, [r1]                                 \n" /* Program RBAR. */
+            "    str r4, [r2]                                 \n" /* Program RASR. */
+            "                                                 \n"
+            "    ldmia r0!, {r3-r4}                           \n" /* Read fourth set of RBAR/RASR registers from TCB. */
+            "    str r3, [r1]                                 \n" /* Program RBAR. */
+            "    str r4, [r2]                                 \n" /* Program RASR. */
+            "                                                 \n"
+            "    ldmia r0!, {r3-r4}                           \n" /* Read fifth set of RBAR/RASR registers from TCB. */
+            "    str r3, [r1]                                 \n" /* Program RBAR. */
+            "    str r4, [r2]                                 \n" /* Program RASR. */
+            "                                                 \n"
+            "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
+            "    movs r3, #1                                  \n" /* r3 = 1. */
+            "    orrs r2, r3                                  \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
+            "    str r2, [r1]                                 \n" /* Enable MPU. */
+            "    dsb                                          \n" /* Force memory writes before continuing. */
+            "                                                 \n"
+            " restore_context:                                \n"
+            "    ldr r2, =pxCurrentTCB                        \n" /* r2 = &pxCurrentTCB. */
+            "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB.*/
+            "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
+            "                                                 \n"
+            " restore_special_regs:                           \n"
+            "    subs r1, #12                                 \n"
+            "    ldmia r1!, {r2-r4}                           \n" /* r2 = original PSP, r3 = CONTROL, r4 = LR. */
+            "    subs r1, #12                                 \n"
+            "    msr psp, r2                                  \n"
+            "    msr control, r3                              \n"
+            "    mov lr, r4                                   \n"
+            "                                                 \n"
+            " restore_general_regs:                           \n"
+            "    subs r1, #32                                 \n"
+            "    ldmia r1!, {r4-r7}                           \n" /* r4-r7 contain half of the hardware saved context. */
+            "    stmia r2!, {r4-r7}                           \n" /* Copy half of the the hardware saved context on the task stack. */
+            "    ldmia r1!, {r4-r7}                           \n" /* r4-r7 contain rest half of the hardware saved context. */
+            "    stmia r2!, {r4-r7}                           \n" /* Copy rest half of the the hardware saved context on the task stack. */
+            "    subs r1, #48                                 \n"
+            "    ldmia r1!, {r4-r7}                           \n" /* Restore r8-r11. */
+            "    mov r8, r4                                   \n" /* r8 = r4. */
+            "    mov r9, r5                                   \n" /* r9 = r5. */
+            "    mov r10, r6                                  \n" /* r10 = r6. */
+            "    mov r11, r7                                  \n" /* r11 = r7. */
+            "    subs r1, #32                                 \n"
+            "    ldmia r1!, {r4-r7}                           \n" /* Restore r4-r7. */
+            "    subs r1, #16                                 \n"
+            "                                                 \n"
+            " restore_context_done:                           \n"
+            "    str r1, [r0]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
+            "    bx lr                                        \n"
+            "                                                 \n"
+            " .align 4                                        \n"
+        );
+    }
+
+#else /* configENABLE_MPU */
+
+    void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            " .extern pxCurrentTCB                            \n"
+            " .syntax unified                                 \n"
+            "                                                 \n"
+            " mrs r0, psp                                     \n" /* Read PSP in r0. */
+            " ldr r2, =pxCurrentTCB                           \n" /* r2 = &( pxCurrentTCB ). */
+            " ldr r1, [r2]                                    \n" /* r1 = pxCurrentTCB. */
+            " subs r0, r0, #36                                \n" /* Make space for LR and the remaining registers on the stack. */
+            " str r0, [r1]                                    \n" /* Save the new top of stack in TCB. */
+            "                                                 \n"
+            " mov r3, lr                                      \n" /* r3 = LR/EXC_RETURN. */
+            " stmia r0!, {r3-r7}                              \n" /* Store on the stack - LR and low registers that are not automatically saved. */
+            " mov r4, r8                                      \n" /* r4 = r8. */
+            " mov r5, r9                                      \n" /* r5 = r9. */
+            " mov r6, r10                                     \n" /* r6 = r10. */
+            " mov r7, r11                                     \n" /* r7 = r11. */
+            " stmia r0!, {r4-r7}                              \n" /* Store the high registers that are not saved automatically. */
+            "                                                 \n"
+            " cpsid i                                         \n"
+            " bl vTaskSwitchContext                           \n"
+            " cpsie i                                         \n"
+            "                                                 \n"
+            " ldr r2, =pxCurrentTCB                           \n" /* r2 = &( pxCurrentTCB ). */
+            " ldr r1, [r2]                                    \n" /* r1 = pxCurrentTCB. */
+            " ldr r0, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
+            "                                                 \n"
+            " adds r0, r0, #20                                \n" /* Move to the high registers. */
+            " ldmia r0!, {r4-r7}                              \n" /* Restore the high registers that are not automatically restored. */
+            " mov r8, r4                                      \n" /* r8 = r4. */
+            " mov r9, r5                                      \n" /* r9 = r5. */
+            " mov r10, r6                                     \n" /* r10 = r6. */
+            " mov r11, r7                                     \n" /* r11 = r7. */
+            " msr psp, r0                                     \n" /* Remember the new top of stack for the task. */
+            " subs r0, r0, #36                                \n" /* Move to the starting of the saved context. */
+            " ldmia r0!, {r3-r7}                              \n" /* Read from stack - r3 = LR and r4-r7 restored. */
+            " bx r3                                           \n"
+            "                                                 \n"
+            " .align 4                                        \n"
+        );
+    }
+
+#endif /* configENABLE_MPU */
+
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+    void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            " .syntax unified                \n"
+            " .extern vPortSVCHandler_C      \n"
+            " .extern vSystemCallEnter       \n"
+            " .extern vSystemCallExit        \n"
+            " .extern pxCurrentTCB           \n"
+            "                                \n"
+            " movs r0, #4                    \n"
+            " mov r1, lr                     \n"
+            " tst r0, r1                     \n"
+            " beq stack_on_msp               \n"
+            "                                \n"
+            " stack_on_psp:                  \n"
+            "     mrs r0, psp                \n"
+            "     b route_svc                \n"
+            "                                \n"
+            " stack_on_msp:                  \n"
+            "     mrs r0, msp                \n"
+            "     b route_svc                \n"
+            "                                \n"
+            " route_svc:                     \n"
+            "     ldr r3, [r0, #24]          \n"
+            "     subs r3, #2                \n"
+            "     ldrb r2, [r3, #0]          \n"
+            "     ldr r3, =%0                \n"
+            "     cmp r2, r3                 \n"
+            "     blt system_call_enter      \n"
+            "     ldr r3, =%1                \n"
+            "     cmp r2, r3                 \n"
+            "     beq system_call_exit       \n"
+            "     b vPortSVCHandler_C        \n"
+            "                                \n"
+            " system_call_enter:             \n"
+            "    push {lr}                   \n"
+            "    bl vSystemCallEnter         \n"
+            "    pop {pc}                    \n"
+            "                                \n"
+            " system_call_exit:              \n"
+            "    push {lr}                   \n"
+            "    bl vSystemCallExit          \n"
+            "    pop {pc}                    \n"
+            "                                \n"
+            " .align 4                       \n"
+            "                                \n"
+            : /* No outputs. */
+            : "i" ( NUM_SYSTEM_CALLS ), "i" ( portSVC_SYSTEM_CALL_EXIT )
+            : "r0", "r1", "r2", "r3", "memory"
+        );
+    }
+
+#else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+
+    void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            " .syntax unified                \n"
+            " .extern vPortSVCHandler_C      \n"
+            "                                \n"
+            " movs r0, #4                    \n"
+            " mov r1, lr                     \n"
+            " tst r0, r1                     \n"
+            " beq stacking_used_msp          \n"
+            "                                \n"
+            " stacking_used_psp:             \n"
+            "    mrs r0, psp                 \n"
+            "    b vPortSVCHandler_C         \n"
+            "                                \n"
+            " stacking_used_msp:             \n"
+            "    mrs r0, msp                 \n"
+            "    b vPortSVCHandler_C         \n"
+            "                                \n"
+            " .align 4                       \n"
+        );
+    }
+
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM0/portasm.h b/portable/GCC/ARM_CM0/portasm.h
new file mode 100644
index 000000000..77e87b132
--- /dev/null
+++ b/portable/GCC/ARM_CM0/portasm.h
@@ -0,0 +1,99 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef __PORT_ASM_H__
+#define __PORT_ASM_H__
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/**
+ * @brief Restore the context of the first task so that the first task starts
+ * executing.
+ */
+void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
+
+/**
+ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
+ * register.
+ *
+ * @note This is a privileged function and should only be called from the kenrel
+ * code.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void ) __attribute__( ( naked ) );
+
+/**
+ * @brief Starts the first task.
+ */
+void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Disables interrupts.
+ */
+uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enables interrupts.
+ */
+void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief PendSV Exception handler.
+ */
+void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SVC Handler.
+ */
+void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+#endif /* __PORT_ASM_H__ */
diff --git a/portable/GCC/ARM_CM0/portmacro.h b/portable/GCC/ARM_CM0/portmacro.h
index 6331020bd..5acb2dcd2 100644
--- a/portable/GCC/ARM_CM0/portmacro.h
+++ b/portable/GCC/ARM_CM0/portmacro.h
@@ -26,7 +26,6 @@
  *
  */
 
-
 #ifndef PORTMACRO_H
 #define PORTMACRO_H
 
@@ -36,17 +35,25 @@
 #endif
 /* *INDENT-ON* */
 
-/*-----------------------------------------------------------
+/*------------------------------------------------------------------------------
  * Port specific definitions.
  *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
  *
  * These settings should not be altered.
- *-----------------------------------------------------------
+ *------------------------------------------------------------------------------
  */
 
-/* Type definitions. */
+#ifndef configENABLE_MPU
+    #error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
 #define portCHAR          char
 #define portFLOAT         float
 #define portDOUBLE        double
@@ -60,33 +67,223 @@ typedef long             BaseType_t;
 typedef unsigned long    UBaseType_t;
 
 #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t     TickType_t;
-    #define portMAX_DELAY              ( TickType_t ) 0xffff
+    typedef uint16_t        TickType_t;
+    #define portMAX_DELAY   ( TickType_t ) 0xffff
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t     TickType_t;
-    #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+    typedef uint32_t        TickType_t;
+    #define portMAX_DELAY   ( TickType_t ) 0xffffffffUL
 
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
+    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+     * not need to be guarded with a critical section. */
     #define portTICK_TYPE_IS_ATOMIC    1
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
 /*-----------------------------------------------------------*/
 
-/* Architecture specifics. */
-#define portSTACK_GROWTH      ( -1 )
-#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT    8
-#define portDONT_DISCARD      __attribute__( ( used ) )
+/**
+ * Architecture specifics.
+ */
+#define portARCH_NAME                      "Cortex-M0+"
+#define portSTACK_GROWTH                   ( -1 )
+#define portTICK_PERIOD_MS                 ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT                 8
+#define portNOP()
+#define portINLINE                         __inline
+#ifndef portFORCE_INLINE
+    #define portFORCE_INLINE               inline __attribute__( ( always_inline ) )
+#endif
+#define portDONT_DISCARD                   __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
+/**
+ * @brief Extern declarations.
+ */
+extern BaseType_t xPortIsInsideInterrupt( void );
+
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+#if ( configENABLE_MPU == 1 )
+    extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+    extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+#if ( configENABLE_MPU == 1 )
+    #define portUSING_MPU_WRAPPERS          1
+    #define portPRIVILEGE_BIT               ( 0x80000000UL )
+#else
+    #define portPRIVILEGE_BIT               ( 0x0UL )
+#endif /* configENABLE_MPU */
+
+/* Shareable (S), Cacheable (C) and Bufferable (B) bits for flash region. */
+#ifndef configS_C_B_FLASH
+    #define configS_C_B_FLASH               ( 0x07UL )
+#endif
+
+/* Shareable (S), Cacheable (C) and Bufferable (B) bits for RAM region. */
+#ifndef configS_C_B_SRAM
+    #define configS_C_B_SRAM                ( 0x07UL )
+#endif
+
+/* MPU regions. */
+#define portPRIVILEGED_RAM_REGION           ( 7UL )
+#define portPRIVILEGED_FLASH_REGION         ( 6UL )
+#define portUNPRIVILEGED_FLASH_REGION       ( 5UL )
+#define portSTACK_REGION                    ( 4UL )
+#define portFIRST_CONFIGURABLE_REGION       ( 0UL )
+#define portLAST_CONFIGURABLE_REGION        ( 3UL )
+#define portNUM_CONFIGURABLE_REGIONS        ( 4UL )
+#define portTOTAL_NUM_REGIONS               ( portNUM_CONFIGURABLE_REGIONS + 1UL ) /* Plus one to make space for the stack region. */
+
+/* MPU region sizes. This information is encoded in the SIZE bits of the MPU
+ * Region Attribute and Size Register (RASR). */
+#define portMPU_REGION_SIZE_256B            ( 0x07UL << 1UL )
+#define portMPU_REGION_SIZE_512B            ( 0x08UL << 1UL )
+#define portMPU_REGION_SIZE_1KB             ( 0x09UL << 1UL )
+#define portMPU_REGION_SIZE_2KB             ( 0x0AUL << 1UL )
+#define portMPU_REGION_SIZE_4KB             ( 0x0BUL << 1UL )
+#define portMPU_REGION_SIZE_8KB             ( 0x0CUL << 1UL )
+#define portMPU_REGION_SIZE_16KB            ( 0x0DUL << 1UL )
+#define portMPU_REGION_SIZE_32KB            ( 0x0EUL << 1UL )
+#define portMPU_REGION_SIZE_64KB            ( 0x0FUL << 1UL )
+#define portMPU_REGION_SIZE_128KB           ( 0x10UL << 1UL )
+#define portMPU_REGION_SIZE_256KB           ( 0x11UL << 1UL )
+#define portMPU_REGION_SIZE_512KB           ( 0x12UL << 1UL )
+#define portMPU_REGION_SIZE_1MB             ( 0x13UL << 1UL )
+#define portMPU_REGION_SIZE_2MB             ( 0x14UL << 1UL )
+#define portMPU_REGION_SIZE_4MB             ( 0x15UL << 1UL )
+#define portMPU_REGION_SIZE_8MB             ( 0x16UL << 1UL )
+#define portMPU_REGION_SIZE_16MB            ( 0x17UL << 1UL )
+#define portMPU_REGION_SIZE_32MB            ( 0x18UL << 1UL )
+#define portMPU_REGION_SIZE_64MB            ( 0x19UL << 1UL )
+#define portMPU_REGION_SIZE_128MB           ( 0x1AUL << 1UL )
+#define portMPU_REGION_SIZE_256MB           ( 0x1BUL << 1UL )
+#define portMPU_REGION_SIZE_512MB           ( 0x1CUL << 1UL )
+#define portMPU_REGION_SIZE_1GB             ( 0x1DUL << 1UL )
+#define portMPU_REGION_SIZE_2GB             ( 0x1EUL << 1UL )
+#define portMPU_REGION_SIZE_4GB             ( 0x1FUL << 1UL )
+
+/* MPU memory types. This information is encoded in the S ( Shareable), C
+ * (Cacheable) and B (Bufferable) bits of the MPU Region Attribute and Size
+ * Register (RASR). */
+#define portMPU_REGION_STRONGLY_ORDERED_SHAREABLE   ( 0x0UL << 16UL ) /* S=NA, C=0, B=0. */
+#define portMPU_REGION_DEVICE_SHAREABLE             ( 0x1UL << 16UL ) /* S=NA, C=0, B=1. */
+#define portMPU_REGION_NORMAL_OIWTNOWA_NONSHARED    ( 0x2UL << 16UL ) /* S=0, C=1, B=0. */
+#define portMPU_REGION_NORMAL_OIWTNOWA_SHARED       ( 0x6UL << 16UL ) /* S=1, C=1, B=0. */
+#define portMPU_REGION_NORMAL_OIWBNOWA_NONSHARED    ( 0x3UL << 16UL ) /* S=0, C=1, B=1.*/
+#define portMPU_REGION_NORMAL_OIWBNOWA_SHARED       ( 0x7UL << 16UL ) /* S=1, C=1, B=1.*/
+
+/* MPU access permissions. This information is encoded in the AP and XN bits of
+ * the MPU Region Attribute and Size Register (RASR). */
+#define portMPU_REGION_PRIV_NA_UNPRIV_NA            ( 0x0UL << 24UL )
+#define portMPU_REGION_PRIV_RW_UNPRIV_NA            ( 0x1UL << 24UL )
+#define portMPU_REGION_PRIV_RW_UNPRIV_RO            ( 0x2UL << 24UL )
+#define portMPU_REGION_PRIV_RW_UNPRIV_RW            ( 0x3UL << 24UL )
+#define portMPU_REGION_PRIV_RO_UNPRIV_NA            ( 0x5UL << 24UL )
+#define portMPU_REGION_PRIV_RO_UNPRIV_RO            ( 0x6UL << 24UL )
+#define portMPU_REGION_EXECUTE_NEVER                ( 0x1UL << 28UL )
+
+#if ( configENABLE_MPU == 1 )
+
+    /**
+     * @brief Settings to define an MPU region.
+     */
+    typedef struct MPURegionSettings
+    {
+        uint32_t ulRBAR; /**< MPU Region Base Address Register (RBAR) for the region. */
+        uint32_t ulRASR; /**< MPU Region Attribute and Size Register (RASR) for the region. */
+    } MPURegionSettings_t;
+
+    #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+
+        #ifndef configSYSTEM_CALL_STACK_SIZE
+            #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
+        #endif
+
+        /**
+         * @brief System call stack.
+         */
+        typedef struct SYSTEM_CALL_STACK_INFO
+        {
+            uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ];
+            uint32_t * pulSystemCallStack;
+            uint32_t * pulTaskStack;
+            uint32_t ulLinkRegisterAtSystemCallEntry;
+        } xSYSTEM_CALL_STACK_INFO;
+
+    #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
+
+    /**
+     * @brief MPU settings as stored in the TCB.
+     */
+
+    /*
+     * +----------+-----------------+---------------+-----+
+     * |  r4-r11  | r0-r3, r12, LR, | PSP, CONTROL  |     |
+     * |          | PC, xPSR        | EXC_RETURN    |     |
+     * +----------+-----------------+---------------+-----+
+     *
+     * <---------><----------------><---------------><---->
+     *     8               8                3          1
+     */
+    #define CONTEXT_SIZE    20
+
+    /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
+    #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
+    #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
+
+    /* Size of an Access Control List (ACL) entry in bits. */
+    #define portACL_ENTRY_SIZE_BITS             ( 32U )
+
+    typedef struct MPU_SETTINGS
+    {
+        MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+        uint32_t ulContext[ CONTEXT_SIZE ];
+        uint32_t ulTaskFlags;
+
+        #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+            xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
+            #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ];
+            #endif
+        #endif
+    } xMPU_SETTINGS;
+
+#endif /* configENABLE_MPU == 1 */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief SVC numbers.
+ */
+#define portSVC_START_SCHEDULER            100
+#define portSVC_RAISE_PRIVILEGE            101
+#define portSVC_SYSTEM_CALL_EXIT           102
+#define portSVC_YIELD                      103
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+#if ( configENABLE_MPU == 1 )
+    #define portYIELD()               __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" )
+    #define portYIELD_WITHIN_API()    vPortYield()
+#else
+    #define portYIELD()               vPortYield()
+    #define portYIELD_WITHIN_API()    vPortYield()
+#endif
 
-/* Scheduler utilities. */
-extern void vPortYield( void );
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-#define portYIELD()                vPortYield()
 #define portEND_SWITCHING_ISR( xSwitchRequired )            \
     do                                                      \
     {                                                       \
@@ -103,66 +300,84 @@ extern void vPortYield( void );
 #define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
-
-/* Critical section management. */
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-extern uint32_t ulSetInterruptMaskFromISR( void ) __attribute__( ( naked ) );
-extern void vClearInterruptMaskFromISR( uint32_t ulMask )  __attribute__( ( naked ) );
-
-#define portSET_INTERRUPT_MASK_FROM_ISR()         ulSetInterruptMaskFromISR()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vClearInterruptMaskFromISR( x )
-#define portDISABLE_INTERRUPTS()                  __asm volatile ( " cpsid i " ::: "memory" )
-#define portENABLE_INTERRUPTS()                   __asm volatile ( " cpsie i " ::: "memory" )
-#define portENTER_CRITICAL()                      vPortEnterCritical()
-#define portEXIT_CRITICAL()                       vPortExitCritical()
-
+/**
+ * @brief Critical section management.
+ */
+#define portSET_INTERRUPT_MASK_FROM_ISR()       ulSetInterruptMask()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )  vClearInterruptMask( x )
+#define portDISABLE_INTERRUPTS()                __asm volatile ( " cpsid i " ::: "memory" )
+#define portENABLE_INTERRUPTS()                 __asm volatile ( " cpsie i " ::: "memory" )
+#define portENTER_CRITICAL()                    vPortEnterCritical()
+#define portEXIT_CRITICAL()                     vPortExitCritical()
 /*-----------------------------------------------------------*/
 
-/* Tickless idle/low power functionality. */
+/**
+ * @brief Tickless idle/low power functionality.
+ */
 #ifndef portSUPPRESS_TICKS_AND_SLEEP
     extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
     #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
 #endif
 /*-----------------------------------------------------------*/
 
-/* Task function macros as described on the FreeRTOS.org WEB site. */
+/**
+ * @brief Task function macros as described on the FreeRTOS.org website.
+ */
 #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
 #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
-
-#define portNOP()
-
-#define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
-
-
-#define portINLINE              __inline
-
-#ifndef portFORCE_INLINE
-    #define portFORCE_INLINE    inline __attribute__( ( always_inline ) )
-#endif
-
 /*-----------------------------------------------------------*/
 
-portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
-{
-    uint32_t ulCurrentInterrupt;
-    BaseType_t xReturn;
+#if ( configENABLE_MPU == 1 )
 
-    /* Obtain the number of the currently executing interrupt. */
-    __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+    /**
+     * @brief Checks whether or not the processor is privileged.
+     *
+     * @return 1 if the processor is already privileged, 0 otherwise.
+     */
+    #define portIS_PRIVILEGED()      xIsPrivileged()
 
-    if( ulCurrentInterrupt == 0 )
-    {
-        xReturn = pdFALSE;
-    }
-    else
-    {
-        xReturn = pdTRUE;
-    }
+    /**
+     * @brief Raise an SVC request to raise privilege.
+     *
+     * The SVC handler checks that the SVC was raised from a system call and only
+     * then it raises the privilege. If this is called from any other place,
+     * the privilege is not raised.
+     */
+    #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
 
-    return xReturn;
-}
+    /**
+     * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+     * register.
+     */
+    #define portRESET_PRIVILEGE()    vResetPrivilege()
 
+#else
+
+    #define portIS_PRIVILEGED()
+    #define portRAISE_PRIVILEGE()
+    #define portRESET_PRIVILEGE()
+
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+
+    extern BaseType_t xPortIsTaskPrivileged( void );
+
+    /**
+     * @brief Checks whether or not the calling task is privileged.
+     *
+     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+     */
+    #define portIS_TASK_PRIVILEGED()    xPortIsTaskPrivileged()
+
+#endif /* configENABLE_MPU == 1 */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+#define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
 /*-----------------------------------------------------------*/
 
 /* *INDENT-OFF* */

From a455b86bd3713707d9b762539c63fb798f2205a0 Mon Sep 17 00:00:00 2001
From: Soren Ptak <ptaksoren@gmail.com>
Date: Tue, 26 Mar 2024 22:07:11 -0700
Subject: [PATCH 239/424] Add removed unprivileged access check to ARM_CRx_MPU
 xPortIsAuthorizedToAccessBuffer() (#1016)

* Add in a removed check for if a task is attempting to read a variable from a location it has write access to in xPortIsAuthorizedToAccessBuffer.

* Add in a portDONT_DISCARD symbol as well.
---
 portable/GCC/ARM_CRx_MPU/port.c      | 4 +++-
 portable/GCC/ARM_CRx_MPU/portmacro.h | 7 +++++++
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/portable/GCC/ARM_CRx_MPU/port.c b/portable/GCC/ARM_CRx_MPU/port.c
index bef3a7854..e4904e58d 100644
--- a/portable/GCC/ARM_CRx_MPU/port.c
+++ b/portable/GCC/ARM_CRx_MPU/port.c
@@ -598,7 +598,9 @@ static BaseType_t prvMPURegionAuthorizesBuffer( const xMPU_REGION_REGISTERS * xT
             if( ulAccessRequested == tskMPU_READ_PERMISSION ) /* RO. */
             {
                 if( ( ulMPURegionAccessPermissions == portMPU_REGION_PRIV_RW_USER_RO ) ||
-                    ( ulMPURegionAccessPermissions == portMPU_REGION_PRIV_RO_USER_RO ) )
+                    ( ulMPURegionAccessPermissions == portMPU_REGION_PRIV_RO_USER_RO ) ||
+                    ( ulMPURegionAccessPermissions == portMPU_REGION_PRIV_RW_USER_RW ) )
+
                 {
                     xAccessGranted = pdTRUE;
                 }
diff --git a/portable/GCC/ARM_CRx_MPU/portmacro.h b/portable/GCC/ARM_CRx_MPU/portmacro.h
index 4ca649f6e..7e80f093e 100644
--- a/portable/GCC/ARM_CRx_MPU/portmacro.h
+++ b/portable/GCC/ARM_CRx_MPU/portmacro.h
@@ -221,6 +221,13 @@ typedef uint32_t TickType_t;
  */
 #define portMEMORY_BARRIER()                         __asm volatile( "" ::: "memory" )
 
+/**
+ * @brief Ensure a symbol isn't removed from the compilation unit.
+ *
+ * @ingroup Port Interface Specifications
+ */
+#define portDONT_DISCARD                             __attribute__( ( used ) )
+
 /**
  * @brief Defines if the tick count can be accessed atomically.
  *

From 39dbff72045bec24965df5c784a1cd84d41ce387 Mon Sep 17 00:00:00 2001
From: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Date: Wed, 27 Mar 2024 14:05:20 +0530
Subject: [PATCH 240/424] Allow xPortIsAuthorizedToAccessBuffer() API call only
 from mpu_wrappers_v2 (#992)

* Add support to call xPortxPortIsAuthorizedToAccessBuffer function only when using latest MPU wrappers

* Fix build issue in ARM CM3 MPU port

* Code review suggestions

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Soren Ptak <ptaksoren@gmail.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
---
 portable/ARMv8M/non_secure/port.c            | 24 ++++--
 portable/GCC/ARM_CM23/non_secure/port.c      | 24 ++++--
 portable/GCC/ARM_CM23_NTZ/non_secure/port.c  | 24 ++++--
 portable/GCC/ARM_CM33/non_secure/port.c      | 24 ++++--
 portable/GCC/ARM_CM33_NTZ/non_secure/port.c  | 24 ++++--
 portable/GCC/ARM_CM35P/non_secure/port.c     | 24 ++++--
 portable/GCC/ARM_CM35P_NTZ/non_secure/port.c | 24 ++++--
 portable/GCC/ARM_CM3_MPU/port.c              | 84 ++++++++++---------
 portable/GCC/ARM_CM4_MPU/port.c              | 84 ++++++++++---------
 portable/GCC/ARM_CM55/non_secure/port.c      | 24 ++++--
 portable/GCC/ARM_CM55_NTZ/non_secure/port.c  | 24 ++++--
 portable/GCC/ARM_CM85/non_secure/port.c      | 24 ++++--
 portable/GCC/ARM_CM85_NTZ/non_secure/port.c  | 24 ++++--
 portable/IAR/ARM_CM23/non_secure/port.c      | 24 ++++--
 portable/IAR/ARM_CM23_NTZ/non_secure/port.c  | 24 ++++--
 portable/IAR/ARM_CM33/non_secure/port.c      | 24 ++++--
 portable/IAR/ARM_CM33_NTZ/non_secure/port.c  | 24 ++++--
 portable/IAR/ARM_CM35P/non_secure/port.c     | 24 ++++--
 portable/IAR/ARM_CM35P_NTZ/non_secure/port.c | 24 ++++--
 portable/IAR/ARM_CM4F_MPU/port.c             | 84 ++++++++++---------
 portable/IAR/ARM_CM55/non_secure/port.c      | 24 ++++--
 portable/IAR/ARM_CM55_NTZ/non_secure/port.c  | 24 ++++--
 portable/IAR/ARM_CM85/non_secure/port.c      | 24 ++++--
 portable/IAR/ARM_CM85_NTZ/non_secure/port.c  | 24 ++++--
 portable/RVDS/ARM_CM4_MPU/port.c             | 86 ++++++++++----------
 25 files changed, 555 insertions(+), 287 deletions(-)

diff --git a/portable/ARMv8M/non_secure/port.c b/portable/ARMv8M/non_secure/port.c
index 7171a72bf..329de05d7 100644
--- a/portable/ARMv8M/non_secure/port.c
+++ b/portable/ARMv8M/non_secure/port.c
@@ -496,14 +496,14 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
-#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
  * @brief This variable is set to pdTRUE when the scheduler is started.
  */
     PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
 
-#endif
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 /**
  * @brief Each task maintains its own interrupt status in the critical nesting
@@ -555,6 +555,7 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 /*-----------------------------------------------------------*/
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
+
     __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
     {
         uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
@@ -770,6 +771,7 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
             __asm volatile ( "cpsie i" ::: "memory" );
         }
     }
+
 #endif /* configUSE_TICKLESS_IDLE */
 /*-----------------------------------------------------------*/
 
@@ -827,6 +829,7 @@ static void prvTaskExitError( void )
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
     {
         uint32_t ulAccessPermissions = 0;
@@ -843,10 +846,12 @@ static void prvTaskExitError( void )
 
         return ulAccessPermissions;
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
     {
         #if defined( __ARMCC_VERSION )
@@ -935,10 +940,12 @@ static void prvTaskExitError( void )
             portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
         }
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_FPU == 1 )
+
     static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
     {
         #if ( configENABLE_TRUSTZONE == 1 )
@@ -960,6 +967,7 @@ static void prvTaskExitError( void )
          * LSPEN = 1 ==> Enable lazy context save of FP state. */
         *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
     }
+
 #endif /* configENABLE_FPU */
 /*-----------------------------------------------------------*/
 
@@ -1740,11 +1748,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     /* Initialize the critical nesting count ready for the first task. */
     ulCriticalNesting = 0;
 
-    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
     {
         xSchedulerRunning = pdTRUE;
     }
-    #endif
+    #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 
     /* Start the first task. */
     vStartFirstTask();
@@ -1772,6 +1780,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
                                     const struct xMEMORY_REGION * const xRegions,
                                     StackType_t * pxBottomOfStack,
@@ -1893,10 +1902,12 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
             lIndex++;
         }
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
     BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
                                                 uint32_t ulBufferLength,
                                                 uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
@@ -1949,7 +1960,8 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         return xAccessGranted;
     }
-#endif /* configENABLE_MPU */
+
+#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 BaseType_t xPortIsInsideInterrupt( void )
diff --git a/portable/GCC/ARM_CM23/non_secure/port.c b/portable/GCC/ARM_CM23/non_secure/port.c
index 7171a72bf..329de05d7 100644
--- a/portable/GCC/ARM_CM23/non_secure/port.c
+++ b/portable/GCC/ARM_CM23/non_secure/port.c
@@ -496,14 +496,14 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
-#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
  * @brief This variable is set to pdTRUE when the scheduler is started.
  */
     PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
 
-#endif
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 /**
  * @brief Each task maintains its own interrupt status in the critical nesting
@@ -555,6 +555,7 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 /*-----------------------------------------------------------*/
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
+
     __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
     {
         uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
@@ -770,6 +771,7 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
             __asm volatile ( "cpsie i" ::: "memory" );
         }
     }
+
 #endif /* configUSE_TICKLESS_IDLE */
 /*-----------------------------------------------------------*/
 
@@ -827,6 +829,7 @@ static void prvTaskExitError( void )
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
     {
         uint32_t ulAccessPermissions = 0;
@@ -843,10 +846,12 @@ static void prvTaskExitError( void )
 
         return ulAccessPermissions;
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
     {
         #if defined( __ARMCC_VERSION )
@@ -935,10 +940,12 @@ static void prvTaskExitError( void )
             portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
         }
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_FPU == 1 )
+
     static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
     {
         #if ( configENABLE_TRUSTZONE == 1 )
@@ -960,6 +967,7 @@ static void prvTaskExitError( void )
          * LSPEN = 1 ==> Enable lazy context save of FP state. */
         *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
     }
+
 #endif /* configENABLE_FPU */
 /*-----------------------------------------------------------*/
 
@@ -1740,11 +1748,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     /* Initialize the critical nesting count ready for the first task. */
     ulCriticalNesting = 0;
 
-    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
     {
         xSchedulerRunning = pdTRUE;
     }
-    #endif
+    #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 
     /* Start the first task. */
     vStartFirstTask();
@@ -1772,6 +1780,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
                                     const struct xMEMORY_REGION * const xRegions,
                                     StackType_t * pxBottomOfStack,
@@ -1893,10 +1902,12 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
             lIndex++;
         }
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
     BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
                                                 uint32_t ulBufferLength,
                                                 uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
@@ -1949,7 +1960,8 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         return xAccessGranted;
     }
-#endif /* configENABLE_MPU */
+
+#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 BaseType_t xPortIsInsideInterrupt( void )
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
index 7171a72bf..329de05d7 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
@@ -496,14 +496,14 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
-#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
  * @brief This variable is set to pdTRUE when the scheduler is started.
  */
     PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
 
-#endif
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 /**
  * @brief Each task maintains its own interrupt status in the critical nesting
@@ -555,6 +555,7 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 /*-----------------------------------------------------------*/
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
+
     __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
     {
         uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
@@ -770,6 +771,7 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
             __asm volatile ( "cpsie i" ::: "memory" );
         }
     }
+
 #endif /* configUSE_TICKLESS_IDLE */
 /*-----------------------------------------------------------*/
 
@@ -827,6 +829,7 @@ static void prvTaskExitError( void )
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
     {
         uint32_t ulAccessPermissions = 0;
@@ -843,10 +846,12 @@ static void prvTaskExitError( void )
 
         return ulAccessPermissions;
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
     {
         #if defined( __ARMCC_VERSION )
@@ -935,10 +940,12 @@ static void prvTaskExitError( void )
             portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
         }
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_FPU == 1 )
+
     static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
     {
         #if ( configENABLE_TRUSTZONE == 1 )
@@ -960,6 +967,7 @@ static void prvTaskExitError( void )
          * LSPEN = 1 ==> Enable lazy context save of FP state. */
         *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
     }
+
 #endif /* configENABLE_FPU */
 /*-----------------------------------------------------------*/
 
@@ -1740,11 +1748,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     /* Initialize the critical nesting count ready for the first task. */
     ulCriticalNesting = 0;
 
-    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
     {
         xSchedulerRunning = pdTRUE;
     }
-    #endif
+    #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 
     /* Start the first task. */
     vStartFirstTask();
@@ -1772,6 +1780,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
                                     const struct xMEMORY_REGION * const xRegions,
                                     StackType_t * pxBottomOfStack,
@@ -1893,10 +1902,12 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
             lIndex++;
         }
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
     BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
                                                 uint32_t ulBufferLength,
                                                 uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
@@ -1949,7 +1960,8 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         return xAccessGranted;
     }
-#endif /* configENABLE_MPU */
+
+#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 BaseType_t xPortIsInsideInterrupt( void )
diff --git a/portable/GCC/ARM_CM33/non_secure/port.c b/portable/GCC/ARM_CM33/non_secure/port.c
index 7171a72bf..329de05d7 100644
--- a/portable/GCC/ARM_CM33/non_secure/port.c
+++ b/portable/GCC/ARM_CM33/non_secure/port.c
@@ -496,14 +496,14 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
-#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
  * @brief This variable is set to pdTRUE when the scheduler is started.
  */
     PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
 
-#endif
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 /**
  * @brief Each task maintains its own interrupt status in the critical nesting
@@ -555,6 +555,7 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 /*-----------------------------------------------------------*/
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
+
     __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
     {
         uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
@@ -770,6 +771,7 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
             __asm volatile ( "cpsie i" ::: "memory" );
         }
     }
+
 #endif /* configUSE_TICKLESS_IDLE */
 /*-----------------------------------------------------------*/
 
@@ -827,6 +829,7 @@ static void prvTaskExitError( void )
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
     {
         uint32_t ulAccessPermissions = 0;
@@ -843,10 +846,12 @@ static void prvTaskExitError( void )
 
         return ulAccessPermissions;
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
     {
         #if defined( __ARMCC_VERSION )
@@ -935,10 +940,12 @@ static void prvTaskExitError( void )
             portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
         }
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_FPU == 1 )
+
     static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
     {
         #if ( configENABLE_TRUSTZONE == 1 )
@@ -960,6 +967,7 @@ static void prvTaskExitError( void )
          * LSPEN = 1 ==> Enable lazy context save of FP state. */
         *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
     }
+
 #endif /* configENABLE_FPU */
 /*-----------------------------------------------------------*/
 
@@ -1740,11 +1748,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     /* Initialize the critical nesting count ready for the first task. */
     ulCriticalNesting = 0;
 
-    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
     {
         xSchedulerRunning = pdTRUE;
     }
-    #endif
+    #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 
     /* Start the first task. */
     vStartFirstTask();
@@ -1772,6 +1780,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
                                     const struct xMEMORY_REGION * const xRegions,
                                     StackType_t * pxBottomOfStack,
@@ -1893,10 +1902,12 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
             lIndex++;
         }
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
     BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
                                                 uint32_t ulBufferLength,
                                                 uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
@@ -1949,7 +1960,8 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         return xAccessGranted;
     }
-#endif /* configENABLE_MPU */
+
+#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 BaseType_t xPortIsInsideInterrupt( void )
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
index 7171a72bf..329de05d7 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
@@ -496,14 +496,14 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
-#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
  * @brief This variable is set to pdTRUE when the scheduler is started.
  */
     PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
 
-#endif
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 /**
  * @brief Each task maintains its own interrupt status in the critical nesting
@@ -555,6 +555,7 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 /*-----------------------------------------------------------*/
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
+
     __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
     {
         uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
@@ -770,6 +771,7 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
             __asm volatile ( "cpsie i" ::: "memory" );
         }
     }
+
 #endif /* configUSE_TICKLESS_IDLE */
 /*-----------------------------------------------------------*/
 
@@ -827,6 +829,7 @@ static void prvTaskExitError( void )
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
     {
         uint32_t ulAccessPermissions = 0;
@@ -843,10 +846,12 @@ static void prvTaskExitError( void )
 
         return ulAccessPermissions;
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
     {
         #if defined( __ARMCC_VERSION )
@@ -935,10 +940,12 @@ static void prvTaskExitError( void )
             portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
         }
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_FPU == 1 )
+
     static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
     {
         #if ( configENABLE_TRUSTZONE == 1 )
@@ -960,6 +967,7 @@ static void prvTaskExitError( void )
          * LSPEN = 1 ==> Enable lazy context save of FP state. */
         *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
     }
+
 #endif /* configENABLE_FPU */
 /*-----------------------------------------------------------*/
 
@@ -1740,11 +1748,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     /* Initialize the critical nesting count ready for the first task. */
     ulCriticalNesting = 0;
 
-    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
     {
         xSchedulerRunning = pdTRUE;
     }
-    #endif
+    #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 
     /* Start the first task. */
     vStartFirstTask();
@@ -1772,6 +1780,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
                                     const struct xMEMORY_REGION * const xRegions,
                                     StackType_t * pxBottomOfStack,
@@ -1893,10 +1902,12 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
             lIndex++;
         }
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
     BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
                                                 uint32_t ulBufferLength,
                                                 uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
@@ -1949,7 +1960,8 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         return xAccessGranted;
     }
-#endif /* configENABLE_MPU */
+
+#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 BaseType_t xPortIsInsideInterrupt( void )
diff --git a/portable/GCC/ARM_CM35P/non_secure/port.c b/portable/GCC/ARM_CM35P/non_secure/port.c
index 7171a72bf..329de05d7 100644
--- a/portable/GCC/ARM_CM35P/non_secure/port.c
+++ b/portable/GCC/ARM_CM35P/non_secure/port.c
@@ -496,14 +496,14 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
-#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
  * @brief This variable is set to pdTRUE when the scheduler is started.
  */
     PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
 
-#endif
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 /**
  * @brief Each task maintains its own interrupt status in the critical nesting
@@ -555,6 +555,7 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 /*-----------------------------------------------------------*/
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
+
     __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
     {
         uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
@@ -770,6 +771,7 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
             __asm volatile ( "cpsie i" ::: "memory" );
         }
     }
+
 #endif /* configUSE_TICKLESS_IDLE */
 /*-----------------------------------------------------------*/
 
@@ -827,6 +829,7 @@ static void prvTaskExitError( void )
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
     {
         uint32_t ulAccessPermissions = 0;
@@ -843,10 +846,12 @@ static void prvTaskExitError( void )
 
         return ulAccessPermissions;
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
     {
         #if defined( __ARMCC_VERSION )
@@ -935,10 +940,12 @@ static void prvTaskExitError( void )
             portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
         }
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_FPU == 1 )
+
     static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
     {
         #if ( configENABLE_TRUSTZONE == 1 )
@@ -960,6 +967,7 @@ static void prvTaskExitError( void )
          * LSPEN = 1 ==> Enable lazy context save of FP state. */
         *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
     }
+
 #endif /* configENABLE_FPU */
 /*-----------------------------------------------------------*/
 
@@ -1740,11 +1748,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     /* Initialize the critical nesting count ready for the first task. */
     ulCriticalNesting = 0;
 
-    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
     {
         xSchedulerRunning = pdTRUE;
     }
-    #endif
+    #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 
     /* Start the first task. */
     vStartFirstTask();
@@ -1772,6 +1780,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
                                     const struct xMEMORY_REGION * const xRegions,
                                     StackType_t * pxBottomOfStack,
@@ -1893,10 +1902,12 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
             lIndex++;
         }
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
     BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
                                                 uint32_t ulBufferLength,
                                                 uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
@@ -1949,7 +1960,8 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         return xAccessGranted;
     }
-#endif /* configENABLE_MPU */
+
+#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 BaseType_t xPortIsInsideInterrupt( void )
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c b/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
index 7171a72bf..329de05d7 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
@@ -496,14 +496,14 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
-#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
  * @brief This variable is set to pdTRUE when the scheduler is started.
  */
     PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
 
-#endif
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 /**
  * @brief Each task maintains its own interrupt status in the critical nesting
@@ -555,6 +555,7 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 /*-----------------------------------------------------------*/
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
+
     __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
     {
         uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
@@ -770,6 +771,7 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
             __asm volatile ( "cpsie i" ::: "memory" );
         }
     }
+
 #endif /* configUSE_TICKLESS_IDLE */
 /*-----------------------------------------------------------*/
 
@@ -827,6 +829,7 @@ static void prvTaskExitError( void )
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
     {
         uint32_t ulAccessPermissions = 0;
@@ -843,10 +846,12 @@ static void prvTaskExitError( void )
 
         return ulAccessPermissions;
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
     {
         #if defined( __ARMCC_VERSION )
@@ -935,10 +940,12 @@ static void prvTaskExitError( void )
             portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
         }
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_FPU == 1 )
+
     static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
     {
         #if ( configENABLE_TRUSTZONE == 1 )
@@ -960,6 +967,7 @@ static void prvTaskExitError( void )
          * LSPEN = 1 ==> Enable lazy context save of FP state. */
         *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
     }
+
 #endif /* configENABLE_FPU */
 /*-----------------------------------------------------------*/
 
@@ -1740,11 +1748,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     /* Initialize the critical nesting count ready for the first task. */
     ulCriticalNesting = 0;
 
-    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
     {
         xSchedulerRunning = pdTRUE;
     }
-    #endif
+    #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 
     /* Start the first task. */
     vStartFirstTask();
@@ -1772,6 +1780,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
                                     const struct xMEMORY_REGION * const xRegions,
                                     StackType_t * pxBottomOfStack,
@@ -1893,10 +1902,12 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
             lIndex++;
         }
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
     BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
                                                 uint32_t ulBufferLength,
                                                 uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
@@ -1949,7 +1960,8 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         return xAccessGranted;
     }
-#endif /* configENABLE_MPU */
+
+#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 BaseType_t xPortIsInsideInterrupt( void )
diff --git a/portable/GCC/ARM_CM3_MPU/port.c b/portable/GCC/ARM_CM3_MPU/port.c
index fd7640017..872882d77 100644
--- a/portable/GCC/ARM_CM3_MPU/port.c
+++ b/portable/GCC/ARM_CM3_MPU/port.c
@@ -264,14 +264,14 @@ BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
  * switches can only occur when uxCriticalNesting is zero. */
 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
 
-#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
 
 /*
  * This variable is set to pdTRUE when the scheduler is started.
  */
     PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
 
-#endif
+#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 /*
  * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
@@ -878,11 +878,11 @@ BaseType_t xPortStartScheduler( void )
     /* Initialise the critical nesting count ready for the first task. */
     uxCriticalNesting = 0;
 
-    #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+    #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
     {
         xSchedulerRunning = pdTRUE;
     }
-    #endif
+    #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
     /* Start the first task. */
     __asm volatile (
@@ -1371,53 +1371,57 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
 }
 /*-----------------------------------------------------------*/
 
-BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
-                                            uint32_t ulBufferLength,
-                                            uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
+#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
 
-{
-    uint32_t i, ulBufferStartAddress, ulBufferEndAddress;
-    BaseType_t xAccessGranted = pdFALSE;
-    const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+    BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
+                                                uint32_t ulBufferLength,
+                                                uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
 
-    if( xSchedulerRunning == pdFALSE )
     {
-        /* Grant access to all the kernel objects before the scheduler
-         * is started. It is necessary because there is no task running
-         * yet and therefore, we cannot use the permissions of any
-         * task. */
-        xAccessGranted = pdTRUE;
-    }
-    else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
-    {
-        xAccessGranted = pdTRUE;
-    }
-    else
-    {
-        if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE )
+        uint32_t i, ulBufferStartAddress, ulBufferEndAddress;
+        BaseType_t xAccessGranted = pdFALSE;
+        const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+        if( xSchedulerRunning == pdFALSE )
         {
-            ulBufferStartAddress = ( uint32_t ) pvBuffer;
-            ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL );
-
-            for( i = 0; i < portTOTAL_NUM_REGIONS_IN_TCB; i++ )
+            /* Grant access to all the kernel objects before the scheduler
+             * is started. It is necessary because there is no task running
+             * yet and therefore, we cannot use the permissions of any
+             * task. */
+            xAccessGranted = pdTRUE;
+        }
+        else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+        {
+            xAccessGranted = pdTRUE;
+        }
+        else
+        {
+            if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE )
             {
-                if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress,
-                                                 xTaskMpuSettings->xRegionSettings[ i ].ulRegionStartAddress,
-                                                 xTaskMpuSettings->xRegionSettings[ i ].ulRegionEndAddress ) &&
-                    portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress,
-                                                 xTaskMpuSettings->xRegionSettings[ i ].ulRegionStartAddress,
-                                                 xTaskMpuSettings->xRegionSettings[ i ].ulRegionEndAddress ) &&
-                    portIS_AUTHORIZED( ulAccessRequested, xTaskMpuSettings->xRegionSettings[ i ].ulRegionPermissions ) )
+                ulBufferStartAddress = ( uint32_t ) pvBuffer;
+                ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL );
+
+                for( i = 0; i < portTOTAL_NUM_REGIONS_IN_TCB; i++ )
                 {
-                    xAccessGranted = pdTRUE;
-                    break;
+                    if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress,
+                                                     xTaskMpuSettings->xRegionSettings[ i ].ulRegionStartAddress,
+                                                     xTaskMpuSettings->xRegionSettings[ i ].ulRegionEndAddress ) &&
+                        portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress,
+                                                     xTaskMpuSettings->xRegionSettings[ i ].ulRegionStartAddress,
+                                                     xTaskMpuSettings->xRegionSettings[ i ].ulRegionEndAddress ) &&
+                        portIS_AUTHORIZED( ulAccessRequested, xTaskMpuSettings->xRegionSettings[ i ].ulRegionPermissions ) )
+                    {
+                        xAccessGranted = pdTRUE;
+                        break;
+                    }
                 }
             }
         }
+
+        return xAccessGranted;
     }
 
-    return xAccessGranted;
-}
+#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( configASSERT_DEFINED == 1 )
diff --git a/portable/GCC/ARM_CM4_MPU/port.c b/portable/GCC/ARM_CM4_MPU/port.c
index 04ed7aa0e..210165544 100644
--- a/portable/GCC/ARM_CM4_MPU/port.c
+++ b/portable/GCC/ARM_CM4_MPU/port.c
@@ -289,14 +289,14 @@ BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
  * switches can only occur when uxCriticalNesting is zero. */
 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
 
-#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
 
 /*
  * This variable is set to pdTRUE when the scheduler is started.
  */
     PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
 
-#endif
+#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 /*
  * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
@@ -963,11 +963,11 @@ BaseType_t xPortStartScheduler( void )
     /* Initialise the critical nesting count ready for the first task. */
     uxCriticalNesting = 0;
 
-    #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+    #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
     {
         xSchedulerRunning = pdTRUE;
     }
-    #endif
+    #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
     /* Ensure the VFP is enabled - it should be anyway. */
     vPortEnableVFP();
@@ -1514,53 +1514,57 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
 }
 /*-----------------------------------------------------------*/
 
-BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
-                                            uint32_t ulBufferLength,
-                                            uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
+#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
 
-{
-    uint32_t i, ulBufferStartAddress, ulBufferEndAddress;
-    BaseType_t xAccessGranted = pdFALSE;
-    const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+    BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
+                                                uint32_t ulBufferLength,
+                                                uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
 
-    if( xSchedulerRunning == pdFALSE )
     {
-        /* Grant access to all the kernel objects before the scheduler
-         * is started. It is necessary because there is no task running
-         * yet and therefore, we cannot use the permissions of any
-         * task. */
-        xAccessGranted = pdTRUE;
-    }
-    else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
-    {
-        xAccessGranted = pdTRUE;
-    }
-    else
-    {
-        if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE )
+        uint32_t i, ulBufferStartAddress, ulBufferEndAddress;
+        BaseType_t xAccessGranted = pdFALSE;
+        const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+        if( xSchedulerRunning == pdFALSE )
         {
-            ulBufferStartAddress = ( uint32_t ) pvBuffer;
-            ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL );
-
-            for( i = 0; i < portTOTAL_NUM_REGIONS_IN_TCB; i++ )
+            /* Grant access to all the kernel objects before the scheduler
+             * is started. It is necessary because there is no task running
+             * yet and therefore, we cannot use the permissions of any
+             * task. */
+            xAccessGranted = pdTRUE;
+        }
+        else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+        {
+            xAccessGranted = pdTRUE;
+        }
+        else
+        {
+            if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE )
             {
-                if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress,
-                                                 xTaskMpuSettings->xRegionSettings[ i ].ulRegionStartAddress,
-                                                 xTaskMpuSettings->xRegionSettings[ i ].ulRegionEndAddress ) &&
-                    portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress,
-                                                 xTaskMpuSettings->xRegionSettings[ i ].ulRegionStartAddress,
-                                                 xTaskMpuSettings->xRegionSettings[ i ].ulRegionEndAddress ) &&
-                    portIS_AUTHORIZED( ulAccessRequested, xTaskMpuSettings->xRegionSettings[ i ].ulRegionPermissions ) )
+                ulBufferStartAddress = ( uint32_t ) pvBuffer;
+                ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL );
+
+                for( i = 0; i < portTOTAL_NUM_REGIONS_IN_TCB; i++ )
                 {
-                    xAccessGranted = pdTRUE;
-                    break;
+                    if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress,
+                                                     xTaskMpuSettings->xRegionSettings[ i ].ulRegionStartAddress,
+                                                     xTaskMpuSettings->xRegionSettings[ i ].ulRegionEndAddress ) &&
+                        portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress,
+                                                     xTaskMpuSettings->xRegionSettings[ i ].ulRegionStartAddress,
+                                                     xTaskMpuSettings->xRegionSettings[ i ].ulRegionEndAddress ) &&
+                        portIS_AUTHORIZED( ulAccessRequested, xTaskMpuSettings->xRegionSettings[ i ].ulRegionPermissions ) )
+                    {
+                        xAccessGranted = pdTRUE;
+                        break;
+                    }
                 }
             }
         }
+
+        return xAccessGranted;
     }
 
-    return xAccessGranted;
-}
+#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 #if ( configASSERT_DEFINED == 1 )
diff --git a/portable/GCC/ARM_CM55/non_secure/port.c b/portable/GCC/ARM_CM55/non_secure/port.c
index 7171a72bf..329de05d7 100644
--- a/portable/GCC/ARM_CM55/non_secure/port.c
+++ b/portable/GCC/ARM_CM55/non_secure/port.c
@@ -496,14 +496,14 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
-#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
  * @brief This variable is set to pdTRUE when the scheduler is started.
  */
     PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
 
-#endif
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 /**
  * @brief Each task maintains its own interrupt status in the critical nesting
@@ -555,6 +555,7 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 /*-----------------------------------------------------------*/
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
+
     __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
     {
         uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
@@ -770,6 +771,7 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
             __asm volatile ( "cpsie i" ::: "memory" );
         }
     }
+
 #endif /* configUSE_TICKLESS_IDLE */
 /*-----------------------------------------------------------*/
 
@@ -827,6 +829,7 @@ static void prvTaskExitError( void )
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
     {
         uint32_t ulAccessPermissions = 0;
@@ -843,10 +846,12 @@ static void prvTaskExitError( void )
 
         return ulAccessPermissions;
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
     {
         #if defined( __ARMCC_VERSION )
@@ -935,10 +940,12 @@ static void prvTaskExitError( void )
             portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
         }
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_FPU == 1 )
+
     static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
     {
         #if ( configENABLE_TRUSTZONE == 1 )
@@ -960,6 +967,7 @@ static void prvTaskExitError( void )
          * LSPEN = 1 ==> Enable lazy context save of FP state. */
         *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
     }
+
 #endif /* configENABLE_FPU */
 /*-----------------------------------------------------------*/
 
@@ -1740,11 +1748,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     /* Initialize the critical nesting count ready for the first task. */
     ulCriticalNesting = 0;
 
-    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
     {
         xSchedulerRunning = pdTRUE;
     }
-    #endif
+    #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 
     /* Start the first task. */
     vStartFirstTask();
@@ -1772,6 +1780,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
                                     const struct xMEMORY_REGION * const xRegions,
                                     StackType_t * pxBottomOfStack,
@@ -1893,10 +1902,12 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
             lIndex++;
         }
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
     BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
                                                 uint32_t ulBufferLength,
                                                 uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
@@ -1949,7 +1960,8 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         return xAccessGranted;
     }
-#endif /* configENABLE_MPU */
+
+#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 BaseType_t xPortIsInsideInterrupt( void )
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/port.c b/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
index 7171a72bf..329de05d7 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
@@ -496,14 +496,14 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
-#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
  * @brief This variable is set to pdTRUE when the scheduler is started.
  */
     PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
 
-#endif
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 /**
  * @brief Each task maintains its own interrupt status in the critical nesting
@@ -555,6 +555,7 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 /*-----------------------------------------------------------*/
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
+
     __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
     {
         uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
@@ -770,6 +771,7 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
             __asm volatile ( "cpsie i" ::: "memory" );
         }
     }
+
 #endif /* configUSE_TICKLESS_IDLE */
 /*-----------------------------------------------------------*/
 
@@ -827,6 +829,7 @@ static void prvTaskExitError( void )
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
     {
         uint32_t ulAccessPermissions = 0;
@@ -843,10 +846,12 @@ static void prvTaskExitError( void )
 
         return ulAccessPermissions;
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
     {
         #if defined( __ARMCC_VERSION )
@@ -935,10 +940,12 @@ static void prvTaskExitError( void )
             portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
         }
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_FPU == 1 )
+
     static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
     {
         #if ( configENABLE_TRUSTZONE == 1 )
@@ -960,6 +967,7 @@ static void prvTaskExitError( void )
          * LSPEN = 1 ==> Enable lazy context save of FP state. */
         *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
     }
+
 #endif /* configENABLE_FPU */
 /*-----------------------------------------------------------*/
 
@@ -1740,11 +1748,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     /* Initialize the critical nesting count ready for the first task. */
     ulCriticalNesting = 0;
 
-    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
     {
         xSchedulerRunning = pdTRUE;
     }
-    #endif
+    #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 
     /* Start the first task. */
     vStartFirstTask();
@@ -1772,6 +1780,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
                                     const struct xMEMORY_REGION * const xRegions,
                                     StackType_t * pxBottomOfStack,
@@ -1893,10 +1902,12 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
             lIndex++;
         }
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
     BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
                                                 uint32_t ulBufferLength,
                                                 uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
@@ -1949,7 +1960,8 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         return xAccessGranted;
     }
-#endif /* configENABLE_MPU */
+
+#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 BaseType_t xPortIsInsideInterrupt( void )
diff --git a/portable/GCC/ARM_CM85/non_secure/port.c b/portable/GCC/ARM_CM85/non_secure/port.c
index 7171a72bf..329de05d7 100644
--- a/portable/GCC/ARM_CM85/non_secure/port.c
+++ b/portable/GCC/ARM_CM85/non_secure/port.c
@@ -496,14 +496,14 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
-#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
  * @brief This variable is set to pdTRUE when the scheduler is started.
  */
     PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
 
-#endif
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 /**
  * @brief Each task maintains its own interrupt status in the critical nesting
@@ -555,6 +555,7 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 /*-----------------------------------------------------------*/
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
+
     __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
     {
         uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
@@ -770,6 +771,7 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
             __asm volatile ( "cpsie i" ::: "memory" );
         }
     }
+
 #endif /* configUSE_TICKLESS_IDLE */
 /*-----------------------------------------------------------*/
 
@@ -827,6 +829,7 @@ static void prvTaskExitError( void )
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
     {
         uint32_t ulAccessPermissions = 0;
@@ -843,10 +846,12 @@ static void prvTaskExitError( void )
 
         return ulAccessPermissions;
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
     {
         #if defined( __ARMCC_VERSION )
@@ -935,10 +940,12 @@ static void prvTaskExitError( void )
             portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
         }
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_FPU == 1 )
+
     static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
     {
         #if ( configENABLE_TRUSTZONE == 1 )
@@ -960,6 +967,7 @@ static void prvTaskExitError( void )
          * LSPEN = 1 ==> Enable lazy context save of FP state. */
         *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
     }
+
 #endif /* configENABLE_FPU */
 /*-----------------------------------------------------------*/
 
@@ -1740,11 +1748,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     /* Initialize the critical nesting count ready for the first task. */
     ulCriticalNesting = 0;
 
-    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
     {
         xSchedulerRunning = pdTRUE;
     }
-    #endif
+    #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 
     /* Start the first task. */
     vStartFirstTask();
@@ -1772,6 +1780,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
                                     const struct xMEMORY_REGION * const xRegions,
                                     StackType_t * pxBottomOfStack,
@@ -1893,10 +1902,12 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
             lIndex++;
         }
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
     BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
                                                 uint32_t ulBufferLength,
                                                 uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
@@ -1949,7 +1960,8 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         return xAccessGranted;
     }
-#endif /* configENABLE_MPU */
+
+#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 BaseType_t xPortIsInsideInterrupt( void )
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/port.c b/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
index 7171a72bf..329de05d7 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
@@ -496,14 +496,14 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
-#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
  * @brief This variable is set to pdTRUE when the scheduler is started.
  */
     PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
 
-#endif
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 /**
  * @brief Each task maintains its own interrupt status in the critical nesting
@@ -555,6 +555,7 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 /*-----------------------------------------------------------*/
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
+
     __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
     {
         uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
@@ -770,6 +771,7 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
             __asm volatile ( "cpsie i" ::: "memory" );
         }
     }
+
 #endif /* configUSE_TICKLESS_IDLE */
 /*-----------------------------------------------------------*/
 
@@ -827,6 +829,7 @@ static void prvTaskExitError( void )
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
     {
         uint32_t ulAccessPermissions = 0;
@@ -843,10 +846,12 @@ static void prvTaskExitError( void )
 
         return ulAccessPermissions;
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
     {
         #if defined( __ARMCC_VERSION )
@@ -935,10 +940,12 @@ static void prvTaskExitError( void )
             portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
         }
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_FPU == 1 )
+
     static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
     {
         #if ( configENABLE_TRUSTZONE == 1 )
@@ -960,6 +967,7 @@ static void prvTaskExitError( void )
          * LSPEN = 1 ==> Enable lazy context save of FP state. */
         *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
     }
+
 #endif /* configENABLE_FPU */
 /*-----------------------------------------------------------*/
 
@@ -1740,11 +1748,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     /* Initialize the critical nesting count ready for the first task. */
     ulCriticalNesting = 0;
 
-    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
     {
         xSchedulerRunning = pdTRUE;
     }
-    #endif
+    #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 
     /* Start the first task. */
     vStartFirstTask();
@@ -1772,6 +1780,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
                                     const struct xMEMORY_REGION * const xRegions,
                                     StackType_t * pxBottomOfStack,
@@ -1893,10 +1902,12 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
             lIndex++;
         }
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
     BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
                                                 uint32_t ulBufferLength,
                                                 uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
@@ -1949,7 +1960,8 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         return xAccessGranted;
     }
-#endif /* configENABLE_MPU */
+
+#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 BaseType_t xPortIsInsideInterrupt( void )
diff --git a/portable/IAR/ARM_CM23/non_secure/port.c b/portable/IAR/ARM_CM23/non_secure/port.c
index 7171a72bf..329de05d7 100644
--- a/portable/IAR/ARM_CM23/non_secure/port.c
+++ b/portable/IAR/ARM_CM23/non_secure/port.c
@@ -496,14 +496,14 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
-#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
  * @brief This variable is set to pdTRUE when the scheduler is started.
  */
     PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
 
-#endif
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 /**
  * @brief Each task maintains its own interrupt status in the critical nesting
@@ -555,6 +555,7 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 /*-----------------------------------------------------------*/
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
+
     __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
     {
         uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
@@ -770,6 +771,7 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
             __asm volatile ( "cpsie i" ::: "memory" );
         }
     }
+
 #endif /* configUSE_TICKLESS_IDLE */
 /*-----------------------------------------------------------*/
 
@@ -827,6 +829,7 @@ static void prvTaskExitError( void )
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
     {
         uint32_t ulAccessPermissions = 0;
@@ -843,10 +846,12 @@ static void prvTaskExitError( void )
 
         return ulAccessPermissions;
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
     {
         #if defined( __ARMCC_VERSION )
@@ -935,10 +940,12 @@ static void prvTaskExitError( void )
             portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
         }
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_FPU == 1 )
+
     static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
     {
         #if ( configENABLE_TRUSTZONE == 1 )
@@ -960,6 +967,7 @@ static void prvTaskExitError( void )
          * LSPEN = 1 ==> Enable lazy context save of FP state. */
         *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
     }
+
 #endif /* configENABLE_FPU */
 /*-----------------------------------------------------------*/
 
@@ -1740,11 +1748,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     /* Initialize the critical nesting count ready for the first task. */
     ulCriticalNesting = 0;
 
-    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
     {
         xSchedulerRunning = pdTRUE;
     }
-    #endif
+    #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 
     /* Start the first task. */
     vStartFirstTask();
@@ -1772,6 +1780,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
                                     const struct xMEMORY_REGION * const xRegions,
                                     StackType_t * pxBottomOfStack,
@@ -1893,10 +1902,12 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
             lIndex++;
         }
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
     BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
                                                 uint32_t ulBufferLength,
                                                 uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
@@ -1949,7 +1960,8 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         return xAccessGranted;
     }
-#endif /* configENABLE_MPU */
+
+#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 BaseType_t xPortIsInsideInterrupt( void )
diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
index 7171a72bf..329de05d7 100644
--- a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
@@ -496,14 +496,14 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
-#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
  * @brief This variable is set to pdTRUE when the scheduler is started.
  */
     PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
 
-#endif
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 /**
  * @brief Each task maintains its own interrupt status in the critical nesting
@@ -555,6 +555,7 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 /*-----------------------------------------------------------*/
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
+
     __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
     {
         uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
@@ -770,6 +771,7 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
             __asm volatile ( "cpsie i" ::: "memory" );
         }
     }
+
 #endif /* configUSE_TICKLESS_IDLE */
 /*-----------------------------------------------------------*/
 
@@ -827,6 +829,7 @@ static void prvTaskExitError( void )
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
     {
         uint32_t ulAccessPermissions = 0;
@@ -843,10 +846,12 @@ static void prvTaskExitError( void )
 
         return ulAccessPermissions;
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
     {
         #if defined( __ARMCC_VERSION )
@@ -935,10 +940,12 @@ static void prvTaskExitError( void )
             portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
         }
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_FPU == 1 )
+
     static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
     {
         #if ( configENABLE_TRUSTZONE == 1 )
@@ -960,6 +967,7 @@ static void prvTaskExitError( void )
          * LSPEN = 1 ==> Enable lazy context save of FP state. */
         *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
     }
+
 #endif /* configENABLE_FPU */
 /*-----------------------------------------------------------*/
 
@@ -1740,11 +1748,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     /* Initialize the critical nesting count ready for the first task. */
     ulCriticalNesting = 0;
 
-    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
     {
         xSchedulerRunning = pdTRUE;
     }
-    #endif
+    #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 
     /* Start the first task. */
     vStartFirstTask();
@@ -1772,6 +1780,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
                                     const struct xMEMORY_REGION * const xRegions,
                                     StackType_t * pxBottomOfStack,
@@ -1893,10 +1902,12 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
             lIndex++;
         }
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
     BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
                                                 uint32_t ulBufferLength,
                                                 uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
@@ -1949,7 +1960,8 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         return xAccessGranted;
     }
-#endif /* configENABLE_MPU */
+
+#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 BaseType_t xPortIsInsideInterrupt( void )
diff --git a/portable/IAR/ARM_CM33/non_secure/port.c b/portable/IAR/ARM_CM33/non_secure/port.c
index 7171a72bf..329de05d7 100644
--- a/portable/IAR/ARM_CM33/non_secure/port.c
+++ b/portable/IAR/ARM_CM33/non_secure/port.c
@@ -496,14 +496,14 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
-#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
  * @brief This variable is set to pdTRUE when the scheduler is started.
  */
     PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
 
-#endif
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 /**
  * @brief Each task maintains its own interrupt status in the critical nesting
@@ -555,6 +555,7 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 /*-----------------------------------------------------------*/
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
+
     __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
     {
         uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
@@ -770,6 +771,7 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
             __asm volatile ( "cpsie i" ::: "memory" );
         }
     }
+
 #endif /* configUSE_TICKLESS_IDLE */
 /*-----------------------------------------------------------*/
 
@@ -827,6 +829,7 @@ static void prvTaskExitError( void )
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
     {
         uint32_t ulAccessPermissions = 0;
@@ -843,10 +846,12 @@ static void prvTaskExitError( void )
 
         return ulAccessPermissions;
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
     {
         #if defined( __ARMCC_VERSION )
@@ -935,10 +940,12 @@ static void prvTaskExitError( void )
             portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
         }
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_FPU == 1 )
+
     static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
     {
         #if ( configENABLE_TRUSTZONE == 1 )
@@ -960,6 +967,7 @@ static void prvTaskExitError( void )
          * LSPEN = 1 ==> Enable lazy context save of FP state. */
         *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
     }
+
 #endif /* configENABLE_FPU */
 /*-----------------------------------------------------------*/
 
@@ -1740,11 +1748,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     /* Initialize the critical nesting count ready for the first task. */
     ulCriticalNesting = 0;
 
-    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
     {
         xSchedulerRunning = pdTRUE;
     }
-    #endif
+    #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 
     /* Start the first task. */
     vStartFirstTask();
@@ -1772,6 +1780,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
                                     const struct xMEMORY_REGION * const xRegions,
                                     StackType_t * pxBottomOfStack,
@@ -1893,10 +1902,12 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
             lIndex++;
         }
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
     BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
                                                 uint32_t ulBufferLength,
                                                 uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
@@ -1949,7 +1960,8 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         return xAccessGranted;
     }
-#endif /* configENABLE_MPU */
+
+#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 BaseType_t xPortIsInsideInterrupt( void )
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
index 7171a72bf..329de05d7 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
@@ -496,14 +496,14 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
-#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
  * @brief This variable is set to pdTRUE when the scheduler is started.
  */
     PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
 
-#endif
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 /**
  * @brief Each task maintains its own interrupt status in the critical nesting
@@ -555,6 +555,7 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 /*-----------------------------------------------------------*/
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
+
     __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
     {
         uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
@@ -770,6 +771,7 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
             __asm volatile ( "cpsie i" ::: "memory" );
         }
     }
+
 #endif /* configUSE_TICKLESS_IDLE */
 /*-----------------------------------------------------------*/
 
@@ -827,6 +829,7 @@ static void prvTaskExitError( void )
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
     {
         uint32_t ulAccessPermissions = 0;
@@ -843,10 +846,12 @@ static void prvTaskExitError( void )
 
         return ulAccessPermissions;
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
     {
         #if defined( __ARMCC_VERSION )
@@ -935,10 +940,12 @@ static void prvTaskExitError( void )
             portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
         }
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_FPU == 1 )
+
     static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
     {
         #if ( configENABLE_TRUSTZONE == 1 )
@@ -960,6 +967,7 @@ static void prvTaskExitError( void )
          * LSPEN = 1 ==> Enable lazy context save of FP state. */
         *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
     }
+
 #endif /* configENABLE_FPU */
 /*-----------------------------------------------------------*/
 
@@ -1740,11 +1748,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     /* Initialize the critical nesting count ready for the first task. */
     ulCriticalNesting = 0;
 
-    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
     {
         xSchedulerRunning = pdTRUE;
     }
-    #endif
+    #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 
     /* Start the first task. */
     vStartFirstTask();
@@ -1772,6 +1780,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
                                     const struct xMEMORY_REGION * const xRegions,
                                     StackType_t * pxBottomOfStack,
@@ -1893,10 +1902,12 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
             lIndex++;
         }
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
     BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
                                                 uint32_t ulBufferLength,
                                                 uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
@@ -1949,7 +1960,8 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         return xAccessGranted;
     }
-#endif /* configENABLE_MPU */
+
+#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 BaseType_t xPortIsInsideInterrupt( void )
diff --git a/portable/IAR/ARM_CM35P/non_secure/port.c b/portable/IAR/ARM_CM35P/non_secure/port.c
index 7171a72bf..329de05d7 100644
--- a/portable/IAR/ARM_CM35P/non_secure/port.c
+++ b/portable/IAR/ARM_CM35P/non_secure/port.c
@@ -496,14 +496,14 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
-#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
  * @brief This variable is set to pdTRUE when the scheduler is started.
  */
     PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
 
-#endif
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 /**
  * @brief Each task maintains its own interrupt status in the critical nesting
@@ -555,6 +555,7 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 /*-----------------------------------------------------------*/
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
+
     __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
     {
         uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
@@ -770,6 +771,7 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
             __asm volatile ( "cpsie i" ::: "memory" );
         }
     }
+
 #endif /* configUSE_TICKLESS_IDLE */
 /*-----------------------------------------------------------*/
 
@@ -827,6 +829,7 @@ static void prvTaskExitError( void )
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
     {
         uint32_t ulAccessPermissions = 0;
@@ -843,10 +846,12 @@ static void prvTaskExitError( void )
 
         return ulAccessPermissions;
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
     {
         #if defined( __ARMCC_VERSION )
@@ -935,10 +940,12 @@ static void prvTaskExitError( void )
             portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
         }
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_FPU == 1 )
+
     static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
     {
         #if ( configENABLE_TRUSTZONE == 1 )
@@ -960,6 +967,7 @@ static void prvTaskExitError( void )
          * LSPEN = 1 ==> Enable lazy context save of FP state. */
         *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
     }
+
 #endif /* configENABLE_FPU */
 /*-----------------------------------------------------------*/
 
@@ -1740,11 +1748,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     /* Initialize the critical nesting count ready for the first task. */
     ulCriticalNesting = 0;
 
-    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
     {
         xSchedulerRunning = pdTRUE;
     }
-    #endif
+    #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 
     /* Start the first task. */
     vStartFirstTask();
@@ -1772,6 +1780,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
                                     const struct xMEMORY_REGION * const xRegions,
                                     StackType_t * pxBottomOfStack,
@@ -1893,10 +1902,12 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
             lIndex++;
         }
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
     BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
                                                 uint32_t ulBufferLength,
                                                 uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
@@ -1949,7 +1960,8 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         return xAccessGranted;
     }
-#endif /* configENABLE_MPU */
+
+#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 BaseType_t xPortIsInsideInterrupt( void )
diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c b/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
index 7171a72bf..329de05d7 100644
--- a/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
@@ -496,14 +496,14 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
-#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
  * @brief This variable is set to pdTRUE when the scheduler is started.
  */
     PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
 
-#endif
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 /**
  * @brief Each task maintains its own interrupt status in the critical nesting
@@ -555,6 +555,7 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 /*-----------------------------------------------------------*/
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
+
     __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
     {
         uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
@@ -770,6 +771,7 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
             __asm volatile ( "cpsie i" ::: "memory" );
         }
     }
+
 #endif /* configUSE_TICKLESS_IDLE */
 /*-----------------------------------------------------------*/
 
@@ -827,6 +829,7 @@ static void prvTaskExitError( void )
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
     {
         uint32_t ulAccessPermissions = 0;
@@ -843,10 +846,12 @@ static void prvTaskExitError( void )
 
         return ulAccessPermissions;
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
     {
         #if defined( __ARMCC_VERSION )
@@ -935,10 +940,12 @@ static void prvTaskExitError( void )
             portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
         }
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_FPU == 1 )
+
     static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
     {
         #if ( configENABLE_TRUSTZONE == 1 )
@@ -960,6 +967,7 @@ static void prvTaskExitError( void )
          * LSPEN = 1 ==> Enable lazy context save of FP state. */
         *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
     }
+
 #endif /* configENABLE_FPU */
 /*-----------------------------------------------------------*/
 
@@ -1740,11 +1748,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     /* Initialize the critical nesting count ready for the first task. */
     ulCriticalNesting = 0;
 
-    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
     {
         xSchedulerRunning = pdTRUE;
     }
-    #endif
+    #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 
     /* Start the first task. */
     vStartFirstTask();
@@ -1772,6 +1780,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
                                     const struct xMEMORY_REGION * const xRegions,
                                     StackType_t * pxBottomOfStack,
@@ -1893,10 +1902,12 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
             lIndex++;
         }
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
     BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
                                                 uint32_t ulBufferLength,
                                                 uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
@@ -1949,7 +1960,8 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         return xAccessGranted;
     }
-#endif /* configENABLE_MPU */
+
+#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 BaseType_t xPortIsInsideInterrupt( void )
diff --git a/portable/IAR/ARM_CM4F_MPU/port.c b/portable/IAR/ARM_CM4F_MPU/port.c
index 622af0f1e..f5772c1d8 100644
--- a/portable/IAR/ARM_CM4F_MPU/port.c
+++ b/portable/IAR/ARM_CM4F_MPU/port.c
@@ -300,14 +300,14 @@ extern void xPortPendSVHandler( void ) PRIVILEGED_FUNCTION;
  * variable. */
 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
 
-#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
 
 /*
  * This variable is set to pdTRUE when the scheduler is started.
  */
     PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
 
-#endif
+#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 /*
  * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
@@ -858,11 +858,11 @@ BaseType_t xPortStartScheduler( void )
     /* Initialise the critical nesting count ready for the first task. */
     uxCriticalNesting = 0;
 
-    #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+    #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
     {
         xSchedulerRunning = pdTRUE;
     }
-    #endif
+    #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
     /* Ensure the VFP is enabled - it should be anyway. */
     vPortEnableVFP();
@@ -1244,53 +1244,57 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
 }
 /*-----------------------------------------------------------*/
 
-BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
-                                            uint32_t ulBufferLength,
-                                            uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
+#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
 
-{
-    uint32_t i, ulBufferStartAddress, ulBufferEndAddress;
-    BaseType_t xAccessGranted = pdFALSE;
-    const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+    BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
+                                                uint32_t ulBufferLength,
+                                                uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
 
-    if( xSchedulerRunning == pdFALSE )
     {
-        /* Grant access to all the kernel objects before the scheduler
-         * is started. It is necessary because there is no task running
-         * yet and therefore, we cannot use the permissions of any
-         * task. */
-        xAccessGranted = pdTRUE;
-    }
-    else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
-    {
-        xAccessGranted = pdTRUE;
-    }
-    else
-    {
-        if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE )
+        uint32_t i, ulBufferStartAddress, ulBufferEndAddress;
+        BaseType_t xAccessGranted = pdFALSE;
+        const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+        if( xSchedulerRunning == pdFALSE )
         {
-            ulBufferStartAddress = ( uint32_t ) pvBuffer;
-            ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL );
-
-            for( i = 0; i < portTOTAL_NUM_REGIONS_IN_TCB; i++ )
+            /* Grant access to all the kernel objects before the scheduler
+             * is started. It is necessary because there is no task running
+             * yet and therefore, we cannot use the permissions of any
+             * task. */
+            xAccessGranted = pdTRUE;
+        }
+        else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+        {
+            xAccessGranted = pdTRUE;
+        }
+        else
+        {
+            if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE )
             {
-                if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress,
-                                                 xTaskMpuSettings->xRegionSettings[ i ].ulRegionStartAddress,
-                                                 xTaskMpuSettings->xRegionSettings[ i ].ulRegionEndAddress ) &&
-                    portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress,
-                                                 xTaskMpuSettings->xRegionSettings[ i ].ulRegionStartAddress,
-                                                 xTaskMpuSettings->xRegionSettings[ i ].ulRegionEndAddress ) &&
-                    portIS_AUTHORIZED( ulAccessRequested, xTaskMpuSettings->xRegionSettings[ i ].ulRegionPermissions ) )
+                ulBufferStartAddress = ( uint32_t ) pvBuffer;
+                ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL );
+
+                for( i = 0; i < portTOTAL_NUM_REGIONS_IN_TCB; i++ )
                 {
-                    xAccessGranted = pdTRUE;
-                    break;
+                    if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress,
+                                                     xTaskMpuSettings->xRegionSettings[ i ].ulRegionStartAddress,
+                                                     xTaskMpuSettings->xRegionSettings[ i ].ulRegionEndAddress ) &&
+                        portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress,
+                                                     xTaskMpuSettings->xRegionSettings[ i ].ulRegionStartAddress,
+                                                     xTaskMpuSettings->xRegionSettings[ i ].ulRegionEndAddress ) &&
+                        portIS_AUTHORIZED( ulAccessRequested, xTaskMpuSettings->xRegionSettings[ i ].ulRegionPermissions ) )
+                    {
+                        xAccessGranted = pdTRUE;
+                        break;
+                    }
                 }
             }
         }
+
+        return xAccessGranted;
     }
 
-    return xAccessGranted;
-}
+#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 
diff --git a/portable/IAR/ARM_CM55/non_secure/port.c b/portable/IAR/ARM_CM55/non_secure/port.c
index 7171a72bf..329de05d7 100644
--- a/portable/IAR/ARM_CM55/non_secure/port.c
+++ b/portable/IAR/ARM_CM55/non_secure/port.c
@@ -496,14 +496,14 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
-#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
  * @brief This variable is set to pdTRUE when the scheduler is started.
  */
     PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
 
-#endif
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 /**
  * @brief Each task maintains its own interrupt status in the critical nesting
@@ -555,6 +555,7 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 /*-----------------------------------------------------------*/
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
+
     __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
     {
         uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
@@ -770,6 +771,7 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
             __asm volatile ( "cpsie i" ::: "memory" );
         }
     }
+
 #endif /* configUSE_TICKLESS_IDLE */
 /*-----------------------------------------------------------*/
 
@@ -827,6 +829,7 @@ static void prvTaskExitError( void )
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
     {
         uint32_t ulAccessPermissions = 0;
@@ -843,10 +846,12 @@ static void prvTaskExitError( void )
 
         return ulAccessPermissions;
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
     {
         #if defined( __ARMCC_VERSION )
@@ -935,10 +940,12 @@ static void prvTaskExitError( void )
             portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
         }
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_FPU == 1 )
+
     static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
     {
         #if ( configENABLE_TRUSTZONE == 1 )
@@ -960,6 +967,7 @@ static void prvTaskExitError( void )
          * LSPEN = 1 ==> Enable lazy context save of FP state. */
         *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
     }
+
 #endif /* configENABLE_FPU */
 /*-----------------------------------------------------------*/
 
@@ -1740,11 +1748,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     /* Initialize the critical nesting count ready for the first task. */
     ulCriticalNesting = 0;
 
-    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
     {
         xSchedulerRunning = pdTRUE;
     }
-    #endif
+    #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 
     /* Start the first task. */
     vStartFirstTask();
@@ -1772,6 +1780,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
                                     const struct xMEMORY_REGION * const xRegions,
                                     StackType_t * pxBottomOfStack,
@@ -1893,10 +1902,12 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
             lIndex++;
         }
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
     BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
                                                 uint32_t ulBufferLength,
                                                 uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
@@ -1949,7 +1960,8 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         return xAccessGranted;
     }
-#endif /* configENABLE_MPU */
+
+#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 BaseType_t xPortIsInsideInterrupt( void )
diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/port.c b/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
index 7171a72bf..329de05d7 100644
--- a/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
@@ -496,14 +496,14 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
-#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
  * @brief This variable is set to pdTRUE when the scheduler is started.
  */
     PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
 
-#endif
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 /**
  * @brief Each task maintains its own interrupt status in the critical nesting
@@ -555,6 +555,7 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 /*-----------------------------------------------------------*/
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
+
     __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
     {
         uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
@@ -770,6 +771,7 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
             __asm volatile ( "cpsie i" ::: "memory" );
         }
     }
+
 #endif /* configUSE_TICKLESS_IDLE */
 /*-----------------------------------------------------------*/
 
@@ -827,6 +829,7 @@ static void prvTaskExitError( void )
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
     {
         uint32_t ulAccessPermissions = 0;
@@ -843,10 +846,12 @@ static void prvTaskExitError( void )
 
         return ulAccessPermissions;
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
     {
         #if defined( __ARMCC_VERSION )
@@ -935,10 +940,12 @@ static void prvTaskExitError( void )
             portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
         }
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_FPU == 1 )
+
     static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
     {
         #if ( configENABLE_TRUSTZONE == 1 )
@@ -960,6 +967,7 @@ static void prvTaskExitError( void )
          * LSPEN = 1 ==> Enable lazy context save of FP state. */
         *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
     }
+
 #endif /* configENABLE_FPU */
 /*-----------------------------------------------------------*/
 
@@ -1740,11 +1748,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     /* Initialize the critical nesting count ready for the first task. */
     ulCriticalNesting = 0;
 
-    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
     {
         xSchedulerRunning = pdTRUE;
     }
-    #endif
+    #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 
     /* Start the first task. */
     vStartFirstTask();
@@ -1772,6 +1780,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
                                     const struct xMEMORY_REGION * const xRegions,
                                     StackType_t * pxBottomOfStack,
@@ -1893,10 +1902,12 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
             lIndex++;
         }
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
     BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
                                                 uint32_t ulBufferLength,
                                                 uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
@@ -1949,7 +1960,8 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         return xAccessGranted;
     }
-#endif /* configENABLE_MPU */
+
+#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 BaseType_t xPortIsInsideInterrupt( void )
diff --git a/portable/IAR/ARM_CM85/non_secure/port.c b/portable/IAR/ARM_CM85/non_secure/port.c
index 7171a72bf..329de05d7 100644
--- a/portable/IAR/ARM_CM85/non_secure/port.c
+++ b/portable/IAR/ARM_CM85/non_secure/port.c
@@ -496,14 +496,14 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
-#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
  * @brief This variable is set to pdTRUE when the scheduler is started.
  */
     PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
 
-#endif
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 /**
  * @brief Each task maintains its own interrupt status in the critical nesting
@@ -555,6 +555,7 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 /*-----------------------------------------------------------*/
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
+
     __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
     {
         uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
@@ -770,6 +771,7 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
             __asm volatile ( "cpsie i" ::: "memory" );
         }
     }
+
 #endif /* configUSE_TICKLESS_IDLE */
 /*-----------------------------------------------------------*/
 
@@ -827,6 +829,7 @@ static void prvTaskExitError( void )
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
     {
         uint32_t ulAccessPermissions = 0;
@@ -843,10 +846,12 @@ static void prvTaskExitError( void )
 
         return ulAccessPermissions;
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
     {
         #if defined( __ARMCC_VERSION )
@@ -935,10 +940,12 @@ static void prvTaskExitError( void )
             portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
         }
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_FPU == 1 )
+
     static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
     {
         #if ( configENABLE_TRUSTZONE == 1 )
@@ -960,6 +967,7 @@ static void prvTaskExitError( void )
          * LSPEN = 1 ==> Enable lazy context save of FP state. */
         *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
     }
+
 #endif /* configENABLE_FPU */
 /*-----------------------------------------------------------*/
 
@@ -1740,11 +1748,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     /* Initialize the critical nesting count ready for the first task. */
     ulCriticalNesting = 0;
 
-    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
     {
         xSchedulerRunning = pdTRUE;
     }
-    #endif
+    #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 
     /* Start the first task. */
     vStartFirstTask();
@@ -1772,6 +1780,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
                                     const struct xMEMORY_REGION * const xRegions,
                                     StackType_t * pxBottomOfStack,
@@ -1893,10 +1902,12 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
             lIndex++;
         }
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
     BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
                                                 uint32_t ulBufferLength,
                                                 uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
@@ -1949,7 +1960,8 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         return xAccessGranted;
     }
-#endif /* configENABLE_MPU */
+
+#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 BaseType_t xPortIsInsideInterrupt( void )
diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/port.c b/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
index 7171a72bf..329de05d7 100644
--- a/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
@@ -496,14 +496,14 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
 
-#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
  * @brief This variable is set to pdTRUE when the scheduler is started.
  */
     PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
 
-#endif
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 /**
  * @brief Each task maintains its own interrupt status in the critical nesting
@@ -555,6 +555,7 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 /*-----------------------------------------------------------*/
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
+
     __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
     {
         uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
@@ -770,6 +771,7 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
             __asm volatile ( "cpsie i" ::: "memory" );
         }
     }
+
 #endif /* configUSE_TICKLESS_IDLE */
 /*-----------------------------------------------------------*/
 
@@ -827,6 +829,7 @@ static void prvTaskExitError( void )
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
     {
         uint32_t ulAccessPermissions = 0;
@@ -843,10 +846,12 @@ static void prvTaskExitError( void )
 
         return ulAccessPermissions;
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
     {
         #if defined( __ARMCC_VERSION )
@@ -935,10 +940,12 @@ static void prvTaskExitError( void )
             portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
         }
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_FPU == 1 )
+
     static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
     {
         #if ( configENABLE_TRUSTZONE == 1 )
@@ -960,6 +967,7 @@ static void prvTaskExitError( void )
          * LSPEN = 1 ==> Enable lazy context save of FP state. */
         *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
     }
+
 #endif /* configENABLE_FPU */
 /*-----------------------------------------------------------*/
 
@@ -1740,11 +1748,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     /* Initialize the critical nesting count ready for the first task. */
     ulCriticalNesting = 0;
 
-    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
     {
         xSchedulerRunning = pdTRUE;
     }
-    #endif
+    #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 
     /* Start the first task. */
     vStartFirstTask();
@@ -1772,6 +1780,7 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
+
     void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
                                     const struct xMEMORY_REGION * const xRegions,
                                     StackType_t * pxBottomOfStack,
@@ -1893,10 +1902,12 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
             lIndex++;
         }
     }
+
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
     BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
                                                 uint32_t ulBufferLength,
                                                 uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
@@ -1949,7 +1960,8 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
 
         return xAccessGranted;
     }
-#endif /* configENABLE_MPU */
+
+#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 BaseType_t xPortIsInsideInterrupt( void )
diff --git a/portable/RVDS/ARM_CM4_MPU/port.c b/portable/RVDS/ARM_CM4_MPU/port.c
index af4bf5e33..37d13e8b8 100644
--- a/portable/RVDS/ARM_CM4_MPU/port.c
+++ b/portable/RVDS/ARM_CM4_MPU/port.c
@@ -149,14 +149,14 @@ typedef void ( * portISR_t )( void );
  * switches can only occur when uxCriticalNesting is zero. */
 PRIVILEGED_DATA static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
 
-#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
 
 /*
  * This variable is set to pdTRUE when the scheduler is started.
  */
     PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
 
-#endif
+#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 /*
  * Setup the timer to generate the tick interrupts.
@@ -963,11 +963,11 @@ BaseType_t xPortStartScheduler( void )
     /* Initialise the critical nesting count ready for the first task. */
     uxCriticalNesting = 0;
 
-    #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+    #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
     {
         xSchedulerRunning = pdTRUE;
     }
-    #endif
+    #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
     /* Ensure the VFP is enabled - it should be anyway. */
     vPortEnableVFP();
@@ -1499,54 +1499,58 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
 }
 /*-----------------------------------------------------------*/
 
-BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
-                                            uint32_t ulBufferLength,
-                                            uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
+#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
 
-{
-    uint32_t i, ulBufferStartAddress, ulBufferEndAddress;
-    BaseType_t xAccessGranted = pdFALSE;
-    const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+    BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
+                                                uint32_t ulBufferLength,
+                                                uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
+
+    {
+        uint32_t i, ulBufferStartAddress, ulBufferEndAddress;
+        BaseType_t xAccessGranted = pdFALSE;
+        const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
 
 
-    if( xSchedulerRunning == pdFALSE )
-    {
-        /* Grant access to all the kernel objects before the scheduler
-         * is started. It is necessary because there is no task running
-         * yet and therefore, we cannot use the permissions of any
-         * task. */
-        xAccessGranted = pdTRUE;
-    }
-    else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
-    {
-        xAccessGranted = pdTRUE;
-    }
-    else
-    {
-        if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE )
+        if( xSchedulerRunning == pdFALSE )
         {
-            ulBufferStartAddress = ( uint32_t ) pvBuffer;
-            ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL );
-
-            for( i = 0; i < portTOTAL_NUM_REGIONS_IN_TCB; i++ )
+            /* Grant access to all the kernel objects before the scheduler
+             * is started. It is necessary because there is no task running
+             * yet and therefore, we cannot use the permissions of any
+             * task. */
+            xAccessGranted = pdTRUE;
+        }
+        else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+        {
+            xAccessGranted = pdTRUE;
+        }
+        else
+        {
+            if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE )
             {
-                if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress,
-                                                 xTaskMpuSettings->xRegionSettings[ i ].ulRegionStartAddress,
-                                                 xTaskMpuSettings->xRegionSettings[ i ].ulRegionEndAddress ) &&
-                    portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress,
-                                                 xTaskMpuSettings->xRegionSettings[ i ].ulRegionStartAddress,
-                                                 xTaskMpuSettings->xRegionSettings[ i ].ulRegionEndAddress ) &&
-                    portIS_AUTHORIZED( ulAccessRequested, xTaskMpuSettings->xRegionSettings[ i ].ulRegionPermissions ) )
+                ulBufferStartAddress = ( uint32_t ) pvBuffer;
+                ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL );
+
+                for( i = 0; i < portTOTAL_NUM_REGIONS_IN_TCB; i++ )
                 {
-                    xAccessGranted = pdTRUE;
-                    break;
+                    if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress,
+                                                     xTaskMpuSettings->xRegionSettings[ i ].ulRegionStartAddress,
+                                                     xTaskMpuSettings->xRegionSettings[ i ].ulRegionEndAddress ) &&
+                        portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress,
+                                                     xTaskMpuSettings->xRegionSettings[ i ].ulRegionStartAddress,
+                                                     xTaskMpuSettings->xRegionSettings[ i ].ulRegionEndAddress ) &&
+                        portIS_AUTHORIZED( ulAccessRequested, xTaskMpuSettings->xRegionSettings[ i ].ulRegionPermissions ) )
+                    {
+                        xAccessGranted = pdTRUE;
+                        break;
+                    }
                 }
             }
         }
+
+        return xAccessGranted;
     }
 
-    return xAccessGranted;
-}
+#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
 
 __asm uint32_t prvPortGetIPSR( void )

From e8289dfee6e00660b5ad028e9f931ffb76c95840 Mon Sep 17 00:00:00 2001
From: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Date: Wed, 27 Mar 2024 14:49:47 +0530
Subject: [PATCH 241/424] Add config option for event groups and stream buffers
 (#994)

* Add configUSE_EVENT_GROUPS in source files

* Add configUSE_EVENT_GROUPS macro in MPU wrapper files

* Add configUSE_EVENT_GROUPS macro in MPU port files for GCC and RVDS compilers

* Fix Formatting

* Add configUSE_STREAM_BUFFERS in source files

* Add configUSE_STREAM_BUFFERS  macro in MPU wrapper files

* Add configUSE_STREAM_BUFFERS macro in MPU port files for GCC and RVDS compilers

* Update FreeRTOS.h post latest commit

* Update the ARM_CRx_MPU Port to account for the new configuration changes

* Formatting suggestions

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Code review suggestions

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: joshzarr <joshzarr@amazon.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Soren Ptak <ptaksoren@gmail.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
---
 event_groups.c                                | 1399 +++++++++--------
 include/FreeRTOS.h                            |    8 +
 include/event_groups.h                        |   30 +
 include/message_buffer.h                      |   72 +-
 include/stream_buffer.h                       |   84 +-
 .../GCC/ARM_CM23/mpu_wrappers_v2_asm.c        |  632 ++++----
 .../GCC/ARM_CM23_NTZ/mpu_wrappers_v2_asm.c    |  632 ++++----
 .../GCC/ARM_CM33/mpu_wrappers_v2_asm.c        |  609 +++----
 .../GCC/ARM_CM33_NTZ/mpu_wrappers_v2_asm.c    |  608 +++----
 portable/Common/mpu_wrappers.c                |  632 ++++----
 portable/Common/mpu_wrappers_v2.c             |  943 ++++++-----
 .../ARM_CM23/non_secure/mpu_wrappers_v2_asm.c |  632 ++++----
 .../non_secure/mpu_wrappers_v2_asm.c          |  632 ++++----
 .../ARM_CM33/non_secure/mpu_wrappers_v2_asm.c |  608 +++----
 .../non_secure/mpu_wrappers_v2_asm.c          |  608 +++----
 .../non_secure/mpu_wrappers_v2_asm.c          |  609 +++----
 .../non_secure/mpu_wrappers_v2_asm.c          |  608 +++----
 .../GCC/ARM_CM3_MPU/mpu_wrappers_v2_asm.c     |  620 ++++----
 .../GCC/ARM_CM4_MPU/mpu_wrappers_v2_asm.c     |  620 ++++----
 .../ARM_CM55/non_secure/mpu_wrappers_v2_asm.c |  609 +++----
 .../non_secure/mpu_wrappers_v2_asm.c          |  608 +++----
 .../ARM_CM85/non_secure/mpu_wrappers_v2_asm.c |  609 +++----
 .../non_secure/mpu_wrappers_v2_asm.c          |  608 +++----
 .../GCC/ARM_CRx_MPU/mpu_wrappers_v2_asm.S     |  189 +--
 .../RVDS/ARM_CM4_MPU/mpu_wrappers_v2_asm.c    |   56 +-
 stream_buffer.c                               |  114 +-
 26 files changed, 7266 insertions(+), 6113 deletions(-)

diff --git a/event_groups.c b/event_groups.c
index 2118f0474..1c0b48760 100644
--- a/event_groups.c
+++ b/event_groups.c
@@ -30,7 +30,7 @@
 #include <stdlib.h>
 
 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
- * all the API functions to use the MPU wrappers.  That should only be done when
+ * all the API functions to use the MPU wrappers. That should only be done when
  * task.h is included from an application file. */
 #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
 
@@ -45,19 +45,25 @@
  * correct privileged Vs unprivileged linkage and placement. */
 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
 
-typedef struct EventGroupDef_t
-{
-    EventBits_t uxEventBits;
-    List_t xTasksWaitingForBits; /**< List of tasks waiting for a bit to be set. */
+/* This entire source file will be skipped if the application is not configured
+ * to include event groups functionality. This #if is closed at the very bottom
+ * of this file. If you want to include event groups then ensure
+ * configUSE_EVENT_GROUPS is set to 1 in FreeRTOSConfig.h. */
+#if ( configUSE_EVENT_GROUPS == 1 )
 
-    #if ( configUSE_TRACE_FACILITY == 1 )
-        UBaseType_t uxEventGroupNumber;
-    #endif
+    typedef struct EventGroupDef_t
+    {
+        EventBits_t uxEventBits;
+        List_t xTasksWaitingForBits; /**< List of tasks waiting for a bit to be set. */
 
-    #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
-        uint8_t ucStaticallyAllocated; /**< Set to pdTRUE if the event group is statically allocated to ensure no attempt is made to free the memory. */
-    #endif
-} EventGroup_t;
+        #if ( configUSE_TRACE_FACILITY == 1 )
+            UBaseType_t uxEventGroupNumber;
+        #endif
+
+        #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+            uint8_t ucStaticallyAllocated; /**< Set to pdTRUE if the event group is statically allocated to ensure no attempt is made to free the memory. */
+        #endif
+    } EventGroup_t;
 
 /*-----------------------------------------------------------*/
 
@@ -69,363 +75,207 @@ typedef struct EventGroupDef_t
  * wait condition is met if any of the bits set in uxBitsToWait for are also set
  * in uxCurrentEventBits.
  */
-static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits,
-                                        const EventBits_t uxBitsToWaitFor,
-                                        const BaseType_t xWaitForAllBits ) PRIVILEGED_FUNCTION;
+    static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits,
+                                            const EventBits_t uxBitsToWaitFor,
+                                            const BaseType_t xWaitForAllBits ) PRIVILEGED_FUNCTION;
 
 /*-----------------------------------------------------------*/
 
-#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+    #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
 
-    EventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t * pxEventGroupBuffer )
-    {
-        EventGroup_t * pxEventBits;
-
-        traceENTER_xEventGroupCreateStatic( pxEventGroupBuffer );
-
-        /* A StaticEventGroup_t object must be provided. */
-        configASSERT( pxEventGroupBuffer );
-
-        #if ( configASSERT_DEFINED == 1 )
+        EventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t * pxEventGroupBuffer )
         {
-            /* Sanity check that the size of the structure used to declare a
-             * variable of type StaticEventGroup_t equals the size of the real
-             * event group structure. */
-            volatile size_t xSize = sizeof( StaticEventGroup_t );
-            configASSERT( xSize == sizeof( EventGroup_t ) );
-        }
-        #endif /* configASSERT_DEFINED */
+            EventGroup_t * pxEventBits;
 
-        /* The user has provided a statically allocated event group - use it. */
-        /* MISRA Ref 11.3.1 [Misaligned access] */
-        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */
-        /* coverity[misra_c_2012_rule_11_3_violation] */
-        pxEventBits = ( EventGroup_t * ) pxEventGroupBuffer;
+            traceENTER_xEventGroupCreateStatic( pxEventGroupBuffer );
 
-        if( pxEventBits != NULL )
-        {
-            pxEventBits->uxEventBits = 0;
-            vListInitialise( &( pxEventBits->xTasksWaitingForBits ) );
+            /* A StaticEventGroup_t object must be provided. */
+            configASSERT( pxEventGroupBuffer );
 
-            #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+            #if ( configASSERT_DEFINED == 1 )
             {
-                /* Both static and dynamic allocation can be used, so note that
-                 * this event group was created statically in case the event group
-                 * is later deleted. */
-                pxEventBits->ucStaticallyAllocated = pdTRUE;
+                /* Sanity check that the size of the structure used to declare a
+                 * variable of type StaticEventGroup_t equals the size of the real
+                 * event group structure. */
+                volatile size_t xSize = sizeof( StaticEventGroup_t );
+                configASSERT( xSize == sizeof( EventGroup_t ) );
             }
-            #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+            #endif /* configASSERT_DEFINED */
 
-            traceEVENT_GROUP_CREATE( pxEventBits );
-        }
-        else
-        {
-            /* xEventGroupCreateStatic should only ever be called with
-             * pxEventGroupBuffer pointing to a pre-allocated (compile time
-             * allocated) StaticEventGroup_t variable. */
-            traceEVENT_GROUP_CREATE_FAILED();
-        }
+            /* The user has provided a statically allocated event group - use it. */
+            /* MISRA Ref 11.3.1 [Misaligned access] */
+            /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */
+            /* coverity[misra_c_2012_rule_11_3_violation] */
+            pxEventBits = ( EventGroup_t * ) pxEventGroupBuffer;
 
-        traceRETURN_xEventGroupCreateStatic( pxEventBits );
-
-        return pxEventBits;
-    }
-
-#endif /* configSUPPORT_STATIC_ALLOCATION */
-/*-----------------------------------------------------------*/
-
-#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-
-    EventGroupHandle_t xEventGroupCreate( void )
-    {
-        EventGroup_t * pxEventBits;
-
-        traceENTER_xEventGroupCreate();
-
-        /* MISRA Ref 11.5.1 [Malloc memory assignment] */
-        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
-        /* coverity[misra_c_2012_rule_11_5_violation] */
-        pxEventBits = ( EventGroup_t * ) pvPortMalloc( sizeof( EventGroup_t ) );
-
-        if( pxEventBits != NULL )
-        {
-            pxEventBits->uxEventBits = 0;
-            vListInitialise( &( pxEventBits->xTasksWaitingForBits ) );
-
-            #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+            if( pxEventBits != NULL )
             {
-                /* Both static and dynamic allocation can be used, so note this
-                 * event group was allocated statically in case the event group is
-                 * later deleted. */
-                pxEventBits->ucStaticallyAllocated = pdFALSE;
-            }
-            #endif /* configSUPPORT_STATIC_ALLOCATION */
+                pxEventBits->uxEventBits = 0;
+                vListInitialise( &( pxEventBits->xTasksWaitingForBits ) );
 
-            traceEVENT_GROUP_CREATE( pxEventBits );
-        }
-        else
-        {
-            traceEVENT_GROUP_CREATE_FAILED();
-        }
+                #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+                {
+                    /* Both static and dynamic allocation can be used, so note that
+                     * this event group was created statically in case the event group
+                     * is later deleted. */
+                    pxEventBits->ucStaticallyAllocated = pdTRUE;
+                }
+                #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
 
-        traceRETURN_xEventGroupCreate( pxEventBits );
-
-        return pxEventBits;
-    }
-
-#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
-/*-----------------------------------------------------------*/
-
-EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup,
-                             const EventBits_t uxBitsToSet,
-                             const EventBits_t uxBitsToWaitFor,
-                             TickType_t xTicksToWait )
-{
-    EventBits_t uxOriginalBitValue, uxReturn;
-    EventGroup_t * pxEventBits = xEventGroup;
-    BaseType_t xAlreadyYielded;
-    BaseType_t xTimeoutOccurred = pdFALSE;
-
-    traceENTER_xEventGroupSync( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTicksToWait );
-
-    configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
-    configASSERT( uxBitsToWaitFor != 0 );
-    #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
-    {
-        configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
-    }
-    #endif
-
-    vTaskSuspendAll();
-    {
-        uxOriginalBitValue = pxEventBits->uxEventBits;
-
-        ( void ) xEventGroupSetBits( xEventGroup, uxBitsToSet );
-
-        if( ( ( uxOriginalBitValue | uxBitsToSet ) & uxBitsToWaitFor ) == uxBitsToWaitFor )
-        {
-            /* All the rendezvous bits are now set - no need to block. */
-            uxReturn = ( uxOriginalBitValue | uxBitsToSet );
-
-            /* Rendezvous always clear the bits.  They will have been cleared
-             * already unless this is the only task in the rendezvous. */
-            pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
-
-            xTicksToWait = 0;
-        }
-        else
-        {
-            if( xTicksToWait != ( TickType_t ) 0 )
-            {
-                traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor );
-
-                /* Store the bits that the calling task is waiting for in the
-                 * task's event list item so the kernel knows when a match is
-                 * found.  Then enter the blocked state. */
-                vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | eventCLEAR_EVENTS_ON_EXIT_BIT | eventWAIT_FOR_ALL_BITS ), xTicksToWait );
-
-                /* This assignment is obsolete as uxReturn will get set after
-                 * the task unblocks, but some compilers mistakenly generate a
-                 * warning about uxReturn being returned without being set if the
-                 * assignment is omitted. */
-                uxReturn = 0;
+                traceEVENT_GROUP_CREATE( pxEventBits );
             }
             else
             {
-                /* The rendezvous bits were not set, but no block time was
-                 * specified - just return the current event bit value. */
-                uxReturn = pxEventBits->uxEventBits;
-                xTimeoutOccurred = pdTRUE;
+                /* xEventGroupCreateStatic should only ever be called with
+                 * pxEventGroupBuffer pointing to a pre-allocated (compile time
+                 * allocated) StaticEventGroup_t variable. */
+                traceEVENT_GROUP_CREATE_FAILED();
             }
-        }
-    }
-    xAlreadyYielded = xTaskResumeAll();
 
-    if( xTicksToWait != ( TickType_t ) 0 )
-    {
-        if( xAlreadyYielded == pdFALSE )
-        {
-            taskYIELD_WITHIN_API();
-        }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
+            traceRETURN_xEventGroupCreateStatic( pxEventBits );
+
+            return pxEventBits;
         }
 
-        /* The task blocked to wait for its required bits to be set - at this
-         * point either the required bits were set or the block time expired.  If
-         * the required bits were set they will have been stored in the task's
-         * event list item, and they should now be retrieved then cleared. */
-        uxReturn = uxTaskResetEventItemValue();
+    #endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
 
-        if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 )
+    #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+        EventGroupHandle_t xEventGroupCreate( void )
         {
-            /* The task timed out, just return the current event bit value. */
-            taskENTER_CRITICAL();
+            EventGroup_t * pxEventBits;
+
+            traceENTER_xEventGroupCreate();
+
+            /* MISRA Ref 11.5.1 [Malloc memory assignment] */
+            /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+            /* coverity[misra_c_2012_rule_11_5_violation] */
+            pxEventBits = ( EventGroup_t * ) pvPortMalloc( sizeof( EventGroup_t ) );
+
+            if( pxEventBits != NULL )
             {
-                uxReturn = pxEventBits->uxEventBits;
+                pxEventBits->uxEventBits = 0;
+                vListInitialise( &( pxEventBits->xTasksWaitingForBits ) );
 
-                /* Although the task got here because it timed out before the
-                 * bits it was waiting for were set, it is possible that since it
-                 * unblocked another task has set the bits.  If this is the case
-                 * then it needs to clear the bits before exiting. */
-                if( ( uxReturn & uxBitsToWaitFor ) == uxBitsToWaitFor )
+                #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
                 {
-                    pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
+                    /* Both static and dynamic allocation can be used, so note this
+                     * event group was allocated statically in case the event group is
+                     * later deleted. */
+                    pxEventBits->ucStaticallyAllocated = pdFALSE;
+                }
+                #endif /* configSUPPORT_STATIC_ALLOCATION */
+
+                traceEVENT_GROUP_CREATE( pxEventBits );
+            }
+            else
+            {
+                traceEVENT_GROUP_CREATE_FAILED();
+            }
+
+            traceRETURN_xEventGroupCreate( pxEventBits );
+
+            return pxEventBits;
+        }
+
+    #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+    EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                 const EventBits_t uxBitsToSet,
+                                 const EventBits_t uxBitsToWaitFor,
+                                 TickType_t xTicksToWait )
+    {
+        EventBits_t uxOriginalBitValue, uxReturn;
+        EventGroup_t * pxEventBits = xEventGroup;
+        BaseType_t xAlreadyYielded;
+        BaseType_t xTimeoutOccurred = pdFALSE;
+
+        traceENTER_xEventGroupSync( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTicksToWait );
+
+        configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
+        configASSERT( uxBitsToWaitFor != 0 );
+        #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+        {
+            configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+        }
+        #endif
+
+        vTaskSuspendAll();
+        {
+            uxOriginalBitValue = pxEventBits->uxEventBits;
+
+            ( void ) xEventGroupSetBits( xEventGroup, uxBitsToSet );
+
+            if( ( ( uxOriginalBitValue | uxBitsToSet ) & uxBitsToWaitFor ) == uxBitsToWaitFor )
+            {
+                /* All the rendezvous bits are now set - no need to block. */
+                uxReturn = ( uxOriginalBitValue | uxBitsToSet );
+
+                /* Rendezvous always clear the bits.  They will have been cleared
+                 * already unless this is the only task in the rendezvous. */
+                pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
+
+                xTicksToWait = 0;
+            }
+            else
+            {
+                if( xTicksToWait != ( TickType_t ) 0 )
+                {
+                    traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor );
+
+                    /* Store the bits that the calling task is waiting for in the
+                     * task's event list item so the kernel knows when a match is
+                     * found.  Then enter the blocked state. */
+                    vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | eventCLEAR_EVENTS_ON_EXIT_BIT | eventWAIT_FOR_ALL_BITS ), xTicksToWait );
+
+                    /* This assignment is obsolete as uxReturn will get set after
+                     * the task unblocks, but some compilers mistakenly generate a
+                     * warning about uxReturn being returned without being set if the
+                     * assignment is omitted. */
+                    uxReturn = 0;
                 }
                 else
                 {
-                    mtCOVERAGE_TEST_MARKER();
+                    /* The rendezvous bits were not set, but no block time was
+                     * specified - just return the current event bit value. */
+                    uxReturn = pxEventBits->uxEventBits;
+                    xTimeoutOccurred = pdTRUE;
                 }
             }
-            taskEXIT_CRITICAL();
-
-            xTimeoutOccurred = pdTRUE;
         }
-        else
+        xAlreadyYielded = xTaskResumeAll();
+
+        if( xTicksToWait != ( TickType_t ) 0 )
         {
-            /* The task unblocked because the bits were set. */
-        }
-
-        /* Control bits might be set as the task had blocked should not be
-         * returned. */
-        uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES;
-    }
-
-    traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred );
-
-    /* Prevent compiler warnings when trace macros are not used. */
-    ( void ) xTimeoutOccurred;
-
-    traceRETURN_xEventGroupSync( uxReturn );
-
-    return uxReturn;
-}
-/*-----------------------------------------------------------*/
-
-EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
-                                 const EventBits_t uxBitsToWaitFor,
-                                 const BaseType_t xClearOnExit,
-                                 const BaseType_t xWaitForAllBits,
-                                 TickType_t xTicksToWait )
-{
-    EventGroup_t * pxEventBits = xEventGroup;
-    EventBits_t uxReturn, uxControlBits = 0;
-    BaseType_t xWaitConditionMet, xAlreadyYielded;
-    BaseType_t xTimeoutOccurred = pdFALSE;
-
-    traceENTER_xEventGroupWaitBits( xEventGroup, uxBitsToWaitFor, xClearOnExit, xWaitForAllBits, xTicksToWait );
-
-    /* Check the user is not attempting to wait on the bits used by the kernel
-     * itself, and that at least one bit is being requested. */
-    configASSERT( xEventGroup );
-    configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
-    configASSERT( uxBitsToWaitFor != 0 );
-    #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
-    {
-        configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
-    }
-    #endif
-
-    vTaskSuspendAll();
-    {
-        const EventBits_t uxCurrentEventBits = pxEventBits->uxEventBits;
-
-        /* Check to see if the wait condition is already met or not. */
-        xWaitConditionMet = prvTestWaitCondition( uxCurrentEventBits, uxBitsToWaitFor, xWaitForAllBits );
-
-        if( xWaitConditionMet != pdFALSE )
-        {
-            /* The wait condition has already been met so there is no need to
-             * block. */
-            uxReturn = uxCurrentEventBits;
-            xTicksToWait = ( TickType_t ) 0;
-
-            /* Clear the wait bits if requested to do so. */
-            if( xClearOnExit != pdFALSE )
+            if( xAlreadyYielded == pdFALSE )
             {
-                pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
-        }
-        else if( xTicksToWait == ( TickType_t ) 0 )
-        {
-            /* The wait condition has not been met, but no block time was
-             * specified, so just return the current value. */
-            uxReturn = uxCurrentEventBits;
-            xTimeoutOccurred = pdTRUE;
-        }
-        else
-        {
-            /* The task is going to block to wait for its required bits to be
-             * set.  uxControlBits are used to remember the specified behaviour of
-             * this call to xEventGroupWaitBits() - for use when the event bits
-             * unblock the task. */
-            if( xClearOnExit != pdFALSE )
-            {
-                uxControlBits |= eventCLEAR_EVENTS_ON_EXIT_BIT;
+                taskYIELD_WITHIN_API();
             }
             else
             {
                 mtCOVERAGE_TEST_MARKER();
             }
 
-            if( xWaitForAllBits != pdFALSE )
-            {
-                uxControlBits |= eventWAIT_FOR_ALL_BITS;
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
+            /* The task blocked to wait for its required bits to be set - at this
+             * point either the required bits were set or the block time expired.  If
+             * the required bits were set they will have been stored in the task's
+             * event list item, and they should now be retrieved then cleared. */
+            uxReturn = uxTaskResetEventItemValue();
 
-            /* Store the bits that the calling task is waiting for in the
-             * task's event list item so the kernel knows when a match is
-             * found.  Then enter the blocked state. */
-            vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | uxControlBits ), xTicksToWait );
-
-            /* This is obsolete as it will get set after the task unblocks, but
-             * some compilers mistakenly generate a warning about the variable
-             * being returned without being set if it is not done. */
-            uxReturn = 0;
-
-            traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor );
-        }
-    }
-    xAlreadyYielded = xTaskResumeAll();
-
-    if( xTicksToWait != ( TickType_t ) 0 )
-    {
-        if( xAlreadyYielded == pdFALSE )
-        {
-            taskYIELD_WITHIN_API();
-        }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
-        }
-
-        /* The task blocked to wait for its required bits to be set - at this
-         * point either the required bits were set or the block time expired.  If
-         * the required bits were set they will have been stored in the task's
-         * event list item, and they should now be retrieved then cleared. */
-        uxReturn = uxTaskResetEventItemValue();
-
-        if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 )
-        {
-            taskENTER_CRITICAL();
+            if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 )
             {
                 /* The task timed out, just return the current event bit value. */
-                uxReturn = pxEventBits->uxEventBits;
-
-                /* It is possible that the event bits were updated between this
-                 * task leaving the Blocked state and running again. */
-                if( prvTestWaitCondition( uxReturn, uxBitsToWaitFor, xWaitForAllBits ) != pdFALSE )
+                taskENTER_CRITICAL();
                 {
-                    if( xClearOnExit != pdFALSE )
+                    uxReturn = pxEventBits->uxEventBits;
+
+                    /* Although the task got here because it timed out before the
+                     * bits it was waiting for were set, it is possible that since it
+                     * unblocked another task has set the bits.  If this is the case
+                     * then it needs to clear the bits before exiting. */
+                    if( ( uxReturn & uxBitsToWaitFor ) == uxBitsToWaitFor )
                     {
                         pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
                     }
@@ -434,437 +284,598 @@ EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
                         mtCOVERAGE_TEST_MARKER();
                     }
                 }
+                taskEXIT_CRITICAL();
+
+                xTimeoutOccurred = pdTRUE;
+            }
+            else
+            {
+                /* The task unblocked because the bits were set. */
+            }
+
+            /* Control bits might be set as the task had blocked should not be
+             * returned. */
+            uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES;
+        }
+
+        traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred );
+
+        /* Prevent compiler warnings when trace macros are not used. */
+        ( void ) xTimeoutOccurred;
+
+        traceRETURN_xEventGroupSync( uxReturn );
+
+        return uxReturn;
+    }
+/*-----------------------------------------------------------*/
+
+    EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+                                     const EventBits_t uxBitsToWaitFor,
+                                     const BaseType_t xClearOnExit,
+                                     const BaseType_t xWaitForAllBits,
+                                     TickType_t xTicksToWait )
+    {
+        EventGroup_t * pxEventBits = xEventGroup;
+        EventBits_t uxReturn, uxControlBits = 0;
+        BaseType_t xWaitConditionMet, xAlreadyYielded;
+        BaseType_t xTimeoutOccurred = pdFALSE;
+
+        traceENTER_xEventGroupWaitBits( xEventGroup, uxBitsToWaitFor, xClearOnExit, xWaitForAllBits, xTicksToWait );
+
+        /* Check the user is not attempting to wait on the bits used by the kernel
+         * itself, and that at least one bit is being requested. */
+        configASSERT( xEventGroup );
+        configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
+        configASSERT( uxBitsToWaitFor != 0 );
+        #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+        {
+            configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+        }
+        #endif
+
+        vTaskSuspendAll();
+        {
+            const EventBits_t uxCurrentEventBits = pxEventBits->uxEventBits;
+
+            /* Check to see if the wait condition is already met or not. */
+            xWaitConditionMet = prvTestWaitCondition( uxCurrentEventBits, uxBitsToWaitFor, xWaitForAllBits );
+
+            if( xWaitConditionMet != pdFALSE )
+            {
+                /* The wait condition has already been met so there is no need to
+                 * block. */
+                uxReturn = uxCurrentEventBits;
+                xTicksToWait = ( TickType_t ) 0;
+
+                /* Clear the wait bits if requested to do so. */
+                if( xClearOnExit != pdFALSE )
+                {
+                    pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            else if( xTicksToWait == ( TickType_t ) 0 )
+            {
+                /* The wait condition has not been met, but no block time was
+                 * specified, so just return the current value. */
+                uxReturn = uxCurrentEventBits;
+                xTimeoutOccurred = pdTRUE;
+            }
+            else
+            {
+                /* The task is going to block to wait for its required bits to be
+                 * set.  uxControlBits are used to remember the specified behaviour of
+                 * this call to xEventGroupWaitBits() - for use when the event bits
+                 * unblock the task. */
+                if( xClearOnExit != pdFALSE )
+                {
+                    uxControlBits |= eventCLEAR_EVENTS_ON_EXIT_BIT;
+                }
                 else
                 {
                     mtCOVERAGE_TEST_MARKER();
                 }
 
-                xTimeoutOccurred = pdTRUE;
-            }
-            taskEXIT_CRITICAL();
-        }
-        else
-        {
-            /* The task unblocked because the bits were set. */
-        }
-
-        /* The task blocked so control bits may have been set. */
-        uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES;
-    }
-
-    traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred );
-
-    /* Prevent compiler warnings when trace macros are not used. */
-    ( void ) xTimeoutOccurred;
-
-    traceRETURN_xEventGroupWaitBits( uxReturn );
-
-    return uxReturn;
-}
-/*-----------------------------------------------------------*/
-
-EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                  const EventBits_t uxBitsToClear )
-{
-    EventGroup_t * pxEventBits = xEventGroup;
-    EventBits_t uxReturn;
-
-    traceENTER_xEventGroupClearBits( xEventGroup, uxBitsToClear );
-
-    /* Check the user is not attempting to clear the bits used by the kernel
-     * itself. */
-    configASSERT( xEventGroup );
-    configASSERT( ( uxBitsToClear & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
-
-    taskENTER_CRITICAL();
-    {
-        traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear );
-
-        /* The value returned is the event group value prior to the bits being
-         * cleared. */
-        uxReturn = pxEventBits->uxEventBits;
-
-        /* Clear the bits. */
-        pxEventBits->uxEventBits &= ~uxBitsToClear;
-    }
-    taskEXIT_CRITICAL();
-
-    traceRETURN_xEventGroupClearBits( uxReturn );
-
-    return uxReturn;
-}
-/*-----------------------------------------------------------*/
-
-#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
-
-    BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup,
-                                            const EventBits_t uxBitsToClear )
-    {
-        BaseType_t xReturn;
-
-        traceENTER_xEventGroupClearBitsFromISR( xEventGroup, uxBitsToClear );
-
-        traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear );
-        xReturn = xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL );
-
-        traceRETURN_xEventGroupClearBitsFromISR( xReturn );
-
-        return xReturn;
-    }
-
-#endif /* if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) */
-/*-----------------------------------------------------------*/
-
-EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup )
-{
-    UBaseType_t uxSavedInterruptStatus;
-    EventGroup_t const * const pxEventBits = xEventGroup;
-    EventBits_t uxReturn;
-
-    traceENTER_xEventGroupGetBitsFromISR( xEventGroup );
-
-    uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
-    {
-        uxReturn = pxEventBits->uxEventBits;
-    }
-    taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
-
-    traceRETURN_xEventGroupGetBitsFromISR( uxReturn );
-
-    return uxReturn;
-}
-/*-----------------------------------------------------------*/
-
-EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                const EventBits_t uxBitsToSet )
-{
-    ListItem_t * pxListItem;
-    ListItem_t * pxNext;
-    ListItem_t const * pxListEnd;
-    List_t const * pxList;
-    EventBits_t uxBitsToClear = 0, uxBitsWaitedFor, uxControlBits;
-    EventGroup_t * pxEventBits = xEventGroup;
-    BaseType_t xMatchFound = pdFALSE;
-
-    traceENTER_xEventGroupSetBits( xEventGroup, uxBitsToSet );
-
-    /* Check the user is not attempting to set the bits used by the kernel
-     * itself. */
-    configASSERT( xEventGroup );
-    configASSERT( ( uxBitsToSet & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
-
-    pxList = &( pxEventBits->xTasksWaitingForBits );
-    pxListEnd = listGET_END_MARKER( pxList );
-    vTaskSuspendAll();
-    {
-        traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet );
-
-        pxListItem = listGET_HEAD_ENTRY( pxList );
-
-        /* Set the bits. */
-        pxEventBits->uxEventBits |= uxBitsToSet;
-
-        /* See if the new bit value should unblock any tasks. */
-        while( pxListItem != pxListEnd )
-        {
-            pxNext = listGET_NEXT( pxListItem );
-            uxBitsWaitedFor = listGET_LIST_ITEM_VALUE( pxListItem );
-            xMatchFound = pdFALSE;
-
-            /* Split the bits waited for from the control bits. */
-            uxControlBits = uxBitsWaitedFor & eventEVENT_BITS_CONTROL_BYTES;
-            uxBitsWaitedFor &= ~eventEVENT_BITS_CONTROL_BYTES;
-
-            if( ( uxControlBits & eventWAIT_FOR_ALL_BITS ) == ( EventBits_t ) 0 )
-            {
-                /* Just looking for single bit being set. */
-                if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) != ( EventBits_t ) 0 )
+                if( xWaitForAllBits != pdFALSE )
                 {
+                    uxControlBits |= eventWAIT_FOR_ALL_BITS;
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+
+                /* Store the bits that the calling task is waiting for in the
+                 * task's event list item so the kernel knows when a match is
+                 * found.  Then enter the blocked state. */
+                vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | uxControlBits ), xTicksToWait );
+
+                /* This is obsolete as it will get set after the task unblocks, but
+                 * some compilers mistakenly generate a warning about the variable
+                 * being returned without being set if it is not done. */
+                uxReturn = 0;
+
+                traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor );
+            }
+        }
+        xAlreadyYielded = xTaskResumeAll();
+
+        if( xTicksToWait != ( TickType_t ) 0 )
+        {
+            if( xAlreadyYielded == pdFALSE )
+            {
+                taskYIELD_WITHIN_API();
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+
+            /* The task blocked to wait for its required bits to be set - at this
+             * point either the required bits were set or the block time expired.  If
+             * the required bits were set they will have been stored in the task's
+             * event list item, and they should now be retrieved then cleared. */
+            uxReturn = uxTaskResetEventItemValue();
+
+            if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 )
+            {
+                taskENTER_CRITICAL();
+                {
+                    /* The task timed out, just return the current event bit value. */
+                    uxReturn = pxEventBits->uxEventBits;
+
+                    /* It is possible that the event bits were updated between this
+                     * task leaving the Blocked state and running again. */
+                    if( prvTestWaitCondition( uxReturn, uxBitsToWaitFor, xWaitForAllBits ) != pdFALSE )
+                    {
+                        if( xClearOnExit != pdFALSE )
+                        {
+                            pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
+                        }
+                        else
+                        {
+                            mtCOVERAGE_TEST_MARKER();
+                        }
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+
+                    xTimeoutOccurred = pdTRUE;
+                }
+                taskEXIT_CRITICAL();
+            }
+            else
+            {
+                /* The task unblocked because the bits were set. */
+            }
+
+            /* The task blocked so control bits may have been set. */
+            uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES;
+        }
+
+        traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred );
+
+        /* Prevent compiler warnings when trace macros are not used. */
+        ( void ) xTimeoutOccurred;
+
+        traceRETURN_xEventGroupWaitBits( uxReturn );
+
+        return uxReturn;
+    }
+/*-----------------------------------------------------------*/
+
+    EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                      const EventBits_t uxBitsToClear )
+    {
+        EventGroup_t * pxEventBits = xEventGroup;
+        EventBits_t uxReturn;
+
+        traceENTER_xEventGroupClearBits( xEventGroup, uxBitsToClear );
+
+        /* Check the user is not attempting to clear the bits used by the kernel
+         * itself. */
+        configASSERT( xEventGroup );
+        configASSERT( ( uxBitsToClear & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
+
+        taskENTER_CRITICAL();
+        {
+            traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear );
+
+            /* The value returned is the event group value prior to the bits being
+             * cleared. */
+            uxReturn = pxEventBits->uxEventBits;
+
+            /* Clear the bits. */
+            pxEventBits->uxEventBits &= ~uxBitsToClear;
+        }
+        taskEXIT_CRITICAL();
+
+        traceRETURN_xEventGroupClearBits( uxReturn );
+
+        return uxReturn;
+    }
+/*-----------------------------------------------------------*/
+
+    #if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
+
+        BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup,
+                                                const EventBits_t uxBitsToClear )
+        {
+            BaseType_t xReturn;
+
+            traceENTER_xEventGroupClearBitsFromISR( xEventGroup, uxBitsToClear );
+
+            traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear );
+            xReturn = xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL );
+
+            traceRETURN_xEventGroupClearBitsFromISR( xReturn );
+
+            return xReturn;
+        }
+
+    #endif /* if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+    EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup )
+    {
+        UBaseType_t uxSavedInterruptStatus;
+        EventGroup_t const * const pxEventBits = xEventGroup;
+        EventBits_t uxReturn;
+
+        traceENTER_xEventGroupGetBitsFromISR( xEventGroup );
+
+        uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
+        {
+            uxReturn = pxEventBits->uxEventBits;
+        }
+        taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
+
+        traceRETURN_xEventGroupGetBitsFromISR( uxReturn );
+
+        return uxReturn;
+    }
+/*-----------------------------------------------------------*/
+
+    EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                    const EventBits_t uxBitsToSet )
+    {
+        ListItem_t * pxListItem;
+        ListItem_t * pxNext;
+        ListItem_t const * pxListEnd;
+        List_t const * pxList;
+        EventBits_t uxBitsToClear = 0, uxBitsWaitedFor, uxControlBits;
+        EventGroup_t * pxEventBits = xEventGroup;
+        BaseType_t xMatchFound = pdFALSE;
+
+        traceENTER_xEventGroupSetBits( xEventGroup, uxBitsToSet );
+
+        /* Check the user is not attempting to set the bits used by the kernel
+         * itself. */
+        configASSERT( xEventGroup );
+        configASSERT( ( uxBitsToSet & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
+
+        pxList = &( pxEventBits->xTasksWaitingForBits );
+        pxListEnd = listGET_END_MARKER( pxList );
+        vTaskSuspendAll();
+        {
+            traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet );
+
+            pxListItem = listGET_HEAD_ENTRY( pxList );
+
+            /* Set the bits. */
+            pxEventBits->uxEventBits |= uxBitsToSet;
+
+            /* See if the new bit value should unblock any tasks. */
+            while( pxListItem != pxListEnd )
+            {
+                pxNext = listGET_NEXT( pxListItem );
+                uxBitsWaitedFor = listGET_LIST_ITEM_VALUE( pxListItem );
+                xMatchFound = pdFALSE;
+
+                /* Split the bits waited for from the control bits. */
+                uxControlBits = uxBitsWaitedFor & eventEVENT_BITS_CONTROL_BYTES;
+                uxBitsWaitedFor &= ~eventEVENT_BITS_CONTROL_BYTES;
+
+                if( ( uxControlBits & eventWAIT_FOR_ALL_BITS ) == ( EventBits_t ) 0 )
+                {
+                    /* Just looking for single bit being set. */
+                    if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) != ( EventBits_t ) 0 )
+                    {
+                        xMatchFound = pdTRUE;
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+                }
+                else if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) == uxBitsWaitedFor )
+                {
+                    /* All bits are set. */
                     xMatchFound = pdTRUE;
                 }
                 else
                 {
-                    mtCOVERAGE_TEST_MARKER();
+                    /* Need all bits to be set, but not all the bits were set. */
                 }
+
+                if( xMatchFound != pdFALSE )
+                {
+                    /* The bits match.  Should the bits be cleared on exit? */
+                    if( ( uxControlBits & eventCLEAR_EVENTS_ON_EXIT_BIT ) != ( EventBits_t ) 0 )
+                    {
+                        uxBitsToClear |= uxBitsWaitedFor;
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+
+                    /* Store the actual event flag value in the task's event list
+                     * item before removing the task from the event list.  The
+                     * eventUNBLOCKED_DUE_TO_BIT_SET bit is set so the task knows
+                     * that is was unblocked due to its required bits matching, rather
+                     * than because it timed out. */
+                    vTaskRemoveFromUnorderedEventList( pxListItem, pxEventBits->uxEventBits | eventUNBLOCKED_DUE_TO_BIT_SET );
+                }
+
+                /* Move onto the next list item.  Note pxListItem->pxNext is not
+                 * used here as the list item may have been removed from the event list
+                 * and inserted into the ready/pending reading list. */
+                pxListItem = pxNext;
             }
-            else if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) == uxBitsWaitedFor )
+
+            /* Clear any bits that matched when the eventCLEAR_EVENTS_ON_EXIT_BIT
+             * bit was set in the control word. */
+            pxEventBits->uxEventBits &= ~uxBitsToClear;
+        }
+        ( void ) xTaskResumeAll();
+
+        traceRETURN_xEventGroupSetBits( pxEventBits->uxEventBits );
+
+        return pxEventBits->uxEventBits;
+    }
+/*-----------------------------------------------------------*/
+
+    void vEventGroupDelete( EventGroupHandle_t xEventGroup )
+    {
+        EventGroup_t * pxEventBits = xEventGroup;
+        const List_t * pxTasksWaitingForBits;
+
+        traceENTER_vEventGroupDelete( xEventGroup );
+
+        configASSERT( pxEventBits );
+
+        pxTasksWaitingForBits = &( pxEventBits->xTasksWaitingForBits );
+
+        vTaskSuspendAll();
+        {
+            traceEVENT_GROUP_DELETE( xEventGroup );
+
+            while( listCURRENT_LIST_LENGTH( pxTasksWaitingForBits ) > ( UBaseType_t ) 0 )
             {
-                /* All bits are set. */
-                xMatchFound = pdTRUE;
+                /* Unblock the task, returning 0 as the event list is being deleted
+                 * and cannot therefore have any bits set. */
+                configASSERT( pxTasksWaitingForBits->xListEnd.pxNext != ( const ListItem_t * ) &( pxTasksWaitingForBits->xListEnd ) );
+                vTaskRemoveFromUnorderedEventList( pxTasksWaitingForBits->xListEnd.pxNext, eventUNBLOCKED_DUE_TO_BIT_SET );
+            }
+        }
+        ( void ) xTaskResumeAll();
+
+        #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) )
+        {
+            /* The event group can only have been allocated dynamically - free
+             * it again. */
+            vPortFree( pxEventBits );
+        }
+        #elif ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+        {
+            /* The event group could have been allocated statically or
+             * dynamically, so check before attempting to free the memory. */
+            if( pxEventBits->ucStaticallyAllocated == ( uint8_t ) pdFALSE )
+            {
+                vPortFree( pxEventBits );
             }
             else
             {
-                /* Need all bits to be set, but not all the bits were set. */
+                mtCOVERAGE_TEST_MARKER();
             }
+        }
+        #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
 
-            if( xMatchFound != pdFALSE )
+        traceRETURN_vEventGroupDelete();
+    }
+/*-----------------------------------------------------------*/
+
+    #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+        BaseType_t xEventGroupGetStaticBuffer( EventGroupHandle_t xEventGroup,
+                                               StaticEventGroup_t ** ppxEventGroupBuffer )
+        {
+            BaseType_t xReturn;
+            EventGroup_t * pxEventBits = xEventGroup;
+
+            traceENTER_xEventGroupGetStaticBuffer( xEventGroup, ppxEventGroupBuffer );
+
+            configASSERT( pxEventBits );
+            configASSERT( ppxEventGroupBuffer );
+
+            #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
             {
-                /* The bits match.  Should the bits be cleared on exit? */
-                if( ( uxControlBits & eventCLEAR_EVENTS_ON_EXIT_BIT ) != ( EventBits_t ) 0 )
+                /* Check if the event group was statically allocated. */
+                if( pxEventBits->ucStaticallyAllocated == ( uint8_t ) pdTRUE )
                 {
-                    uxBitsToClear |= uxBitsWaitedFor;
+                    /* MISRA Ref 11.3.1 [Misaligned access] */
+                    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */
+                    /* coverity[misra_c_2012_rule_11_3_violation] */
+                    *ppxEventGroupBuffer = ( StaticEventGroup_t * ) pxEventBits;
+                    xReturn = pdTRUE;
                 }
                 else
                 {
-                    mtCOVERAGE_TEST_MARKER();
+                    xReturn = pdFALSE;
                 }
-
-                /* Store the actual event flag value in the task's event list
-                 * item before removing the task from the event list.  The
-                 * eventUNBLOCKED_DUE_TO_BIT_SET bit is set so the task knows
-                 * that is was unblocked due to its required bits matching, rather
-                 * than because it timed out. */
-                vTaskRemoveFromUnorderedEventList( pxListItem, pxEventBits->uxEventBits | eventUNBLOCKED_DUE_TO_BIT_SET );
             }
-
-            /* Move onto the next list item.  Note pxListItem->pxNext is not
-             * used here as the list item may have been removed from the event list
-             * and inserted into the ready/pending reading list. */
-            pxListItem = pxNext;
-        }
-
-        /* Clear any bits that matched when the eventCLEAR_EVENTS_ON_EXIT_BIT
-         * bit was set in the control word. */
-        pxEventBits->uxEventBits &= ~uxBitsToClear;
-    }
-    ( void ) xTaskResumeAll();
-
-    traceRETURN_xEventGroupSetBits( pxEventBits->uxEventBits );
-
-    return pxEventBits->uxEventBits;
-}
-/*-----------------------------------------------------------*/
-
-void vEventGroupDelete( EventGroupHandle_t xEventGroup )
-{
-    EventGroup_t * pxEventBits = xEventGroup;
-    const List_t * pxTasksWaitingForBits;
-
-    traceENTER_vEventGroupDelete( xEventGroup );
-
-    configASSERT( pxEventBits );
-
-    pxTasksWaitingForBits = &( pxEventBits->xTasksWaitingForBits );
-
-    vTaskSuspendAll();
-    {
-        traceEVENT_GROUP_DELETE( xEventGroup );
-
-        while( listCURRENT_LIST_LENGTH( pxTasksWaitingForBits ) > ( UBaseType_t ) 0 )
-        {
-            /* Unblock the task, returning 0 as the event list is being deleted
-             * and cannot therefore have any bits set. */
-            configASSERT( pxTasksWaitingForBits->xListEnd.pxNext != ( const ListItem_t * ) &( pxTasksWaitingForBits->xListEnd ) );
-            vTaskRemoveFromUnorderedEventList( pxTasksWaitingForBits->xListEnd.pxNext, eventUNBLOCKED_DUE_TO_BIT_SET );
-        }
-    }
-    ( void ) xTaskResumeAll();
-
-    #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) )
-    {
-        /* The event group can only have been allocated dynamically - free
-         * it again. */
-        vPortFree( pxEventBits );
-    }
-    #elif ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
-    {
-        /* The event group could have been allocated statically or
-         * dynamically, so check before attempting to free the memory. */
-        if( pxEventBits->ucStaticallyAllocated == ( uint8_t ) pdFALSE )
-        {
-            vPortFree( pxEventBits );
-        }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
-        }
-    }
-    #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
-
-    traceRETURN_vEventGroupDelete();
-}
-/*-----------------------------------------------------------*/
-
-#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
-    BaseType_t xEventGroupGetStaticBuffer( EventGroupHandle_t xEventGroup,
-                                           StaticEventGroup_t ** ppxEventGroupBuffer )
-    {
-        BaseType_t xReturn;
-        EventGroup_t * pxEventBits = xEventGroup;
-
-        traceENTER_xEventGroupGetStaticBuffer( xEventGroup, ppxEventGroupBuffer );
-
-        configASSERT( pxEventBits );
-        configASSERT( ppxEventGroupBuffer );
-
-        #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-        {
-            /* Check if the event group was statically allocated. */
-            if( pxEventBits->ucStaticallyAllocated == ( uint8_t ) pdTRUE )
+            #else /* configSUPPORT_DYNAMIC_ALLOCATION */
             {
+                /* Event group must have been statically allocated. */
                 /* MISRA Ref 11.3.1 [Misaligned access] */
                 /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */
                 /* coverity[misra_c_2012_rule_11_3_violation] */
                 *ppxEventGroupBuffer = ( StaticEventGroup_t * ) pxEventBits;
                 xReturn = pdTRUE;
             }
-            else
-            {
-                xReturn = pdFALSE;
-            }
-        }
-        #else /* configSUPPORT_DYNAMIC_ALLOCATION */
-        {
-            /* Event group must have been statically allocated. */
-            /* MISRA Ref 11.3.1 [Misaligned access] */
-            /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */
-            /* coverity[misra_c_2012_rule_11_3_violation] */
-            *ppxEventGroupBuffer = ( StaticEventGroup_t * ) pxEventBits;
-            xReturn = pdTRUE;
-        }
-        #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+            #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
 
-        traceRETURN_xEventGroupGetStaticBuffer( xReturn );
+            traceRETURN_xEventGroupGetStaticBuffer( xReturn );
 
-        return xReturn;
-    }
-#endif /* configSUPPORT_STATIC_ALLOCATION */
+            return xReturn;
+        }
+    #endif /* configSUPPORT_STATIC_ALLOCATION */
 /*-----------------------------------------------------------*/
 
 /* For internal use only - execute a 'set bits' command that was pended from
  * an interrupt. */
-void vEventGroupSetBitsCallback( void * pvEventGroup,
-                                 uint32_t ulBitsToSet )
-{
-    traceENTER_vEventGroupSetBitsCallback( pvEventGroup, ulBitsToSet );
+    void vEventGroupSetBitsCallback( void * pvEventGroup,
+                                     uint32_t ulBitsToSet )
+    {
+        traceENTER_vEventGroupSetBitsCallback( pvEventGroup, ulBitsToSet );
 
-    /* MISRA Ref 11.5.4 [Callback function parameter] */
-    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
-    /* coverity[misra_c_2012_rule_11_5_violation] */
-    ( void ) xEventGroupSetBits( pvEventGroup, ( EventBits_t ) ulBitsToSet );
+        /* MISRA Ref 11.5.4 [Callback function parameter] */
+        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+        /* coverity[misra_c_2012_rule_11_5_violation] */
+        ( void ) xEventGroupSetBits( pvEventGroup, ( EventBits_t ) ulBitsToSet );
 
-    traceRETURN_vEventGroupSetBitsCallback();
-}
+        traceRETURN_vEventGroupSetBitsCallback();
+    }
 /*-----------------------------------------------------------*/
 
 /* For internal use only - execute a 'clear bits' command that was pended from
  * an interrupt. */
-void vEventGroupClearBitsCallback( void * pvEventGroup,
-                                   uint32_t ulBitsToClear )
-{
-    traceENTER_vEventGroupClearBitsCallback( pvEventGroup, ulBitsToClear );
-
-    /* MISRA Ref 11.5.4 [Callback function parameter] */
-    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
-    /* coverity[misra_c_2012_rule_11_5_violation] */
-    ( void ) xEventGroupClearBits( pvEventGroup, ( EventBits_t ) ulBitsToClear );
-
-    traceRETURN_vEventGroupClearBitsCallback();
-}
-/*-----------------------------------------------------------*/
-
-static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits,
-                                        const EventBits_t uxBitsToWaitFor,
-                                        const BaseType_t xWaitForAllBits )
-{
-    BaseType_t xWaitConditionMet = pdFALSE;
-
-    if( xWaitForAllBits == pdFALSE )
+    void vEventGroupClearBitsCallback( void * pvEventGroup,
+                                       uint32_t ulBitsToClear )
     {
-        /* Task only has to wait for one bit within uxBitsToWaitFor to be
-         * set.  Is one already set? */
-        if( ( uxCurrentEventBits & uxBitsToWaitFor ) != ( EventBits_t ) 0 )
-        {
-            xWaitConditionMet = pdTRUE;
-        }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
-        }
-    }
-    else
-    {
-        /* Task has to wait for all the bits in uxBitsToWaitFor to be set.
-         * Are they set already? */
-        if( ( uxCurrentEventBits & uxBitsToWaitFor ) == uxBitsToWaitFor )
-        {
-            xWaitConditionMet = pdTRUE;
-        }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
-        }
-    }
+        traceENTER_vEventGroupClearBitsCallback( pvEventGroup, ulBitsToClear );
 
-    return xWaitConditionMet;
-}
-/*-----------------------------------------------------------*/
-
-#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
-
-    BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup,
-                                          const EventBits_t uxBitsToSet,
-                                          BaseType_t * pxHigherPriorityTaskWoken )
-    {
-        BaseType_t xReturn;
-
-        traceENTER_xEventGroupSetBitsFromISR( xEventGroup, uxBitsToSet, pxHigherPriorityTaskWoken );
-
-        traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet );
-        xReturn = xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken );
-
-        traceRETURN_xEventGroupSetBitsFromISR( xReturn );
-
-        return xReturn;
-    }
-
-#endif /* if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TRACE_FACILITY == 1 )
-
-    UBaseType_t uxEventGroupGetNumber( void * xEventGroup )
-    {
-        UBaseType_t xReturn;
-
-        /* MISRA Ref 11.5.2 [Opaque pointer] */
+        /* MISRA Ref 11.5.4 [Callback function parameter] */
         /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
         /* coverity[misra_c_2012_rule_11_5_violation] */
-        EventGroup_t const * pxEventBits = ( EventGroup_t * ) xEventGroup;
+        ( void ) xEventGroupClearBits( pvEventGroup, ( EventBits_t ) ulBitsToClear );
 
-        traceENTER_uxEventGroupGetNumber( xEventGroup );
+        traceRETURN_vEventGroupClearBitsCallback();
+    }
+/*-----------------------------------------------------------*/
 
-        if( xEventGroup == NULL )
+    static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits,
+                                            const EventBits_t uxBitsToWaitFor,
+                                            const BaseType_t xWaitForAllBits )
+    {
+        BaseType_t xWaitConditionMet = pdFALSE;
+
+        if( xWaitForAllBits == pdFALSE )
         {
-            xReturn = 0;
+            /* Task only has to wait for one bit within uxBitsToWaitFor to be
+             * set.  Is one already set? */
+            if( ( uxCurrentEventBits & uxBitsToWaitFor ) != ( EventBits_t ) 0 )
+            {
+                xWaitConditionMet = pdTRUE;
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
         }
         else
         {
-            xReturn = pxEventBits->uxEventGroupNumber;
+            /* Task has to wait for all the bits in uxBitsToWaitFor to be set.
+             * Are they set already? */
+            if( ( uxCurrentEventBits & uxBitsToWaitFor ) == uxBitsToWaitFor )
+            {
+                xWaitConditionMet = pdTRUE;
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
         }
 
-        traceRETURN_uxEventGroupGetNumber( xReturn );
-
-        return xReturn;
+        return xWaitConditionMet;
     }
-
-#endif /* configUSE_TRACE_FACILITY */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
 
-    void vEventGroupSetNumber( void * xEventGroup,
-                               UBaseType_t uxEventGroupNumber )
-    {
-        traceENTER_vEventGroupSetNumber( xEventGroup, uxEventGroupNumber );
+        BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup,
+                                              const EventBits_t uxBitsToSet,
+                                              BaseType_t * pxHigherPriorityTaskWoken )
+        {
+            BaseType_t xReturn;
 
-        /* MISRA Ref 11.5.2 [Opaque pointer] */
-        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
-        /* coverity[misra_c_2012_rule_11_5_violation] */
-        ( ( EventGroup_t * ) xEventGroup )->uxEventGroupNumber = uxEventGroupNumber;
+            traceENTER_xEventGroupSetBitsFromISR( xEventGroup, uxBitsToSet, pxHigherPriorityTaskWoken );
 
-        traceRETURN_vEventGroupSetNumber();
-    }
+            traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet );
+            xReturn = xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken );
 
-#endif /* configUSE_TRACE_FACILITY */
+            traceRETURN_xEventGroupSetBitsFromISR( xReturn );
+
+            return xReturn;
+        }
+
+    #endif /* if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) */
 /*-----------------------------------------------------------*/
+
+    #if ( configUSE_TRACE_FACILITY == 1 )
+
+        UBaseType_t uxEventGroupGetNumber( void * xEventGroup )
+        {
+            UBaseType_t xReturn;
+
+            /* MISRA Ref 11.5.2 [Opaque pointer] */
+            /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+            /* coverity[misra_c_2012_rule_11_5_violation] */
+            EventGroup_t const * pxEventBits = ( EventGroup_t * ) xEventGroup;
+
+            traceENTER_uxEventGroupGetNumber( xEventGroup );
+
+            if( xEventGroup == NULL )
+            {
+                xReturn = 0;
+            }
+            else
+            {
+                xReturn = pxEventBits->uxEventGroupNumber;
+            }
+
+            traceRETURN_uxEventGroupGetNumber( xReturn );
+
+            return xReturn;
+        }
+
+    #endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TRACE_FACILITY == 1 )
+
+        void vEventGroupSetNumber( void * xEventGroup,
+                                   UBaseType_t uxEventGroupNumber )
+        {
+            traceENTER_vEventGroupSetNumber( xEventGroup, uxEventGroupNumber );
+
+            /* MISRA Ref 11.5.2 [Opaque pointer] */
+            /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+            /* coverity[misra_c_2012_rule_11_5_violation] */
+            ( ( EventGroup_t * ) xEventGroup )->uxEventGroupNumber = uxEventGroupNumber;
+
+            traceRETURN_vEventGroupSetNumber();
+        }
+
+    #endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+/* This entire source file will be skipped if the application is not configured
+ * to include event groups functionality. If you want to include event groups
+ * then ensure configUSE_EVENT_GROUPS is set to 1 in FreeRTOSConfig.h. */
+#endif /* configUSE_EVENT_GROUPS == 1 */
diff --git a/include/FreeRTOS.h b/include/FreeRTOS.h
index 8dcb407f4..69611842a 100644
--- a/include/FreeRTOS.h
+++ b/include/FreeRTOS.h
@@ -318,6 +318,14 @@
     #define configUSE_TIMERS    0
 #endif
 
+#ifndef configUSE_EVENT_GROUPS
+    #define configUSE_EVENT_GROUPS    1
+#endif
+
+#ifndef configUSE_STREAM_BUFFERS
+    #define configUSE_STREAM_BUFFERS    1
+#endif
+
 #ifndef configUSE_DAEMON_TASK_STARTUP_HOOK
     #define configUSE_DAEMON_TASK_STARTUP_HOOK    0
 #endif
diff --git a/include/event_groups.h b/include/event_groups.h
index f5652114e..8ff26799b 100644
--- a/include/event_groups.h
+++ b/include/event_groups.h
@@ -139,6 +139,9 @@ typedef TickType_t               EventBits_t;
  * each event group has 56 usable bits (bit 0 to bit 53). The EventBits_t type
  * is used to store event bits within an event group.
  *
+ * The configUSE_EVENT_GROUPS configuration constant must be set to 1 for xEventGroupCreate()
+ * to be available.
+ *
  * @return If the event group was created then a handle to the event group is
  * returned.  If there was insufficient FreeRTOS heap available to create the
  * event group then NULL is returned.  See https://www.FreeRTOS.org/a00111.html
@@ -196,6 +199,9 @@ typedef TickType_t               EventBits_t;
  * each event group has 56 usable bits (bit 0 to bit 53).  The EventBits_t type
  * is used to store event bits within an event group.
  *
+ * The configUSE_EVENT_GROUPS configuration constant must be set to 1 for xEventGroupCreateStatic()
+ * to be available.
+ *
  * @param pxEventGroupBuffer pxEventGroupBuffer must point to a variable of type
  * StaticEventGroup_t, which will be then be used to hold the event group's data
  * structures, removing the need for the memory to be allocated dynamically.
@@ -238,6 +244,9 @@ typedef TickType_t               EventBits_t;
  *
  * This function cannot be called from an interrupt.
  *
+ * The configUSE_EVENT_GROUPS configuration constant must be set to 1 for xEventGroupWaitBits()
+ * to be available.
+ *
  * @param xEventGroup The event group in which the bits are being tested.  The
  * event group must have previously been created using a call to
  * xEventGroupCreate().
@@ -331,6 +340,9 @@ EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
  * Clear bits within an event group.  This function cannot be called from an
  * interrupt.
  *
+ * The configUSE_EVENT_GROUPS configuration constant must be set to 1 for xEventGroupClearBits()
+ * to be available.
+ *
  * @param xEventGroup The event group in which the bits are to be cleared.
  *
  * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear
@@ -461,6 +473,9 @@ EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup,
  * Setting bits in an event group will automatically unblock tasks that are
  * blocked waiting for the bits.
  *
+ * The configUSE_EVENT_GROUPS configuration constant must be set to 1 for xEventGroupSetBits()
+ * to be available.
+ *
  * @param xEventGroup The event group in which the bits are to be set.
  *
  * @param uxBitsToSet A bitwise value that indicates the bit or bits to set.
@@ -625,6 +640,9 @@ EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup,
  * this case all the bits specified by uxBitsToWait will be automatically
  * cleared before the function returns.
  *
+ * The configUSE_EVENT_GROUPS configuration constant must be set to 1 for xEventGroupSync()
+ * to be available.
+ *
  * @param xEventGroup The event group in which the bits are being tested.  The
  * event group must have previously been created using a call to
  * xEventGroupCreate().
@@ -743,6 +761,9 @@ EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup,
  * Returns the current value of the bits in an event group.  This function
  * cannot be used from an interrupt.
  *
+ * The configUSE_EVENT_GROUPS configuration constant must be set to 1 for xEventGroupGetBits()
+ * to be available.
+ *
  * @param xEventGroup The event group being queried.
  *
  * @return The event group bits at the time xEventGroupGetBits() was called.
@@ -760,6 +781,9 @@ EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup,
  *
  * A version of xEventGroupGetBits() that can be called from an ISR.
  *
+ * The configUSE_EVENT_GROUPS configuration constant must be set to 1 for xEventGroupGetBitsFromISR()
+ * to be available.
+ *
  * @param xEventGroup The event group being queried.
  *
  * @return The event group bits at the time xEventGroupGetBitsFromISR() was called.
@@ -779,6 +803,9 @@ EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ) PRIVILEG
  * xEventGroupCreate().  Tasks that are blocked on the event group will be
  * unblocked and obtain 0 as the event group's value.
  *
+ * The configUSE_EVENT_GROUPS configuration constant must be set to 1 for vEventGroupDelete()
+ * to be available.
+ *
  * @param xEventGroup The event group being deleted.
  */
 void vEventGroupDelete( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION;
@@ -793,6 +820,9 @@ void vEventGroupDelete( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION;
  * Retrieve a pointer to a statically created event groups's data structure
  * buffer. It is the same buffer that is supplied at the time of creation.
  *
+ * The configUSE_EVENT_GROUPS configuration constant must be set to 1 for xEventGroupGetStaticBuffer()
+ * to be available.
+ *
  * @param xEventGroup The event group for which to retrieve the buffer.
  *
  * @param ppxEventGroupBuffer Used to return a pointer to the event groups's
diff --git a/include/message_buffer.h b/include/message_buffer.h
index fb5a6c04a..1b1356ca4 100644
--- a/include/message_buffer.h
+++ b/include/message_buffer.h
@@ -100,6 +100,8 @@ typedef StreamBufferHandle_t MessageBufferHandle_t;
  *
  * configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in
  * FreeRTOSConfig.h for xMessageBufferCreate() to be available.
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xMessageBufferCreate() to be available.
  *
  * @param xBufferSizeBytes The total number of bytes (not messages) the message
  * buffer will be able to hold at any one time.  When a message is written to
@@ -168,12 +170,15 @@ typedef StreamBufferHandle_t MessageBufferHandle_t;
  *
  * @code{c}
  * MessageBufferHandle_t xMessageBufferCreateStatic( size_t xBufferSizeBytes,
- *                                                uint8_t *pucMessageBufferStorageArea,
- *                                                StaticMessageBuffer_t *pxStaticMessageBuffer );
+ *                                                   uint8_t *pucMessageBufferStorageArea,
+ *                                                   StaticMessageBuffer_t *pxStaticMessageBuffer );
  * @endcode
  * Creates a new message buffer using statically allocated memory.  See
  * xMessageBufferCreate() for a version that uses dynamically allocated memory.
  *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xMessageBufferCreateStatic() to be available.
+ *
  * @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the
  * pucMessageBufferStorageArea parameter.  When a message is written to the
  * message buffer an additional sizeof( size_t ) bytes are also written to store
@@ -258,6 +263,9 @@ typedef StreamBufferHandle_t MessageBufferHandle_t;
  * buffer and storage area buffer. These are the same buffers that are supplied
  * at the time of creation.
  *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xMessageBufferGetStaticBuffers() to be available.
+ *
  * @param xMessageBuffer The message buffer for which to retrieve the buffers.
  *
  * @param ppucMessageBufferStorageArea Used to return a pointer to the
@@ -281,9 +289,9 @@ typedef StreamBufferHandle_t MessageBufferHandle_t;
  *
  * @code{c}
  * size_t xMessageBufferSend( MessageBufferHandle_t xMessageBuffer,
- *                         const void *pvTxData,
- *                         size_t xDataLengthBytes,
- *                         TickType_t xTicksToWait );
+ *                            const void *pvTxData,
+ *                            size_t xDataLengthBytes,
+ *                            TickType_t xTicksToWait );
  * @endcode
  *
  * Sends a discrete message to the message buffer.  The message can be any
@@ -309,6 +317,9 @@ typedef StreamBufferHandle_t MessageBufferHandle_t;
  * xMessageBufferSendFromISR() to write to a message buffer from an interrupt
  * service routine (ISR).
  *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xMessageBufferSend() to be available.
+ *
  * @param xMessageBuffer The handle of the message buffer to which a message is
  * being sent.
  *
@@ -381,9 +392,9 @@ typedef StreamBufferHandle_t MessageBufferHandle_t;
  *
  * @code{c}
  * size_t xMessageBufferSendFromISR( MessageBufferHandle_t xMessageBuffer,
- *                                const void *pvTxData,
- *                                size_t xDataLengthBytes,
- *                                BaseType_t *pxHigherPriorityTaskWoken );
+ *                                   const void *pvTxData,
+ *                                   size_t xDataLengthBytes,
+ *                                   BaseType_t *pxHigherPriorityTaskWoken );
  * @endcode
  *
  * Interrupt safe version of the API function that sends a discrete message to
@@ -409,6 +420,9 @@ typedef StreamBufferHandle_t MessageBufferHandle_t;
  * xMessageBufferSendFromISR() to write to a message buffer from an interrupt
  * service routine (ISR).
  *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xMessageBufferSendFromISR() to be available.
+ *
  * @param xMessageBuffer The handle of the message buffer to which a message is
  * being sent.
  *
@@ -486,9 +500,9 @@ typedef StreamBufferHandle_t MessageBufferHandle_t;
  *
  * @code{c}
  * size_t xMessageBufferReceive( MessageBufferHandle_t xMessageBuffer,
- *                            void *pvRxData,
- *                            size_t xBufferLengthBytes,
- *                            TickType_t xTicksToWait );
+ *                               void *pvRxData,
+ *                               size_t xBufferLengthBytes,
+ *                               TickType_t xTicksToWait );
  * @endcode
  *
  * Receives a discrete message from a message buffer.  Messages can be of
@@ -513,6 +527,9 @@ typedef StreamBufferHandle_t MessageBufferHandle_t;
  * xMessageBufferReceiveFromISR() to read from a message buffer from an
  * interrupt service routine (ISR).
  *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xMessageBufferReceive() to be available.
+ *
  * @param xMessageBuffer The handle of the message buffer from which a message
  * is being received.
  *
@@ -576,9 +593,9 @@ typedef StreamBufferHandle_t MessageBufferHandle_t;
  *
  * @code{c}
  * size_t xMessageBufferReceiveFromISR( MessageBufferHandle_t xMessageBuffer,
- *                                   void *pvRxData,
- *                                   size_t xBufferLengthBytes,
- *                                   BaseType_t *pxHigherPriorityTaskWoken );
+ *                                      void *pvRxData,
+ *                                      size_t xBufferLengthBytes,
+ *                                      BaseType_t *pxHigherPriorityTaskWoken );
  * @endcode
  *
  * An interrupt safe version of the API function that receives a discrete
@@ -604,6 +621,9 @@ typedef StreamBufferHandle_t MessageBufferHandle_t;
  * xMessageBufferReceiveFromISR() to read from a message buffer from an
  * interrupt service routine (ISR).
  *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xMessageBufferReceiveFromISR() to be available.
+ *
  * @param xMessageBuffer The handle of the message buffer from which a message
  * is being received.
  *
@@ -687,6 +707,9 @@ typedef StreamBufferHandle_t MessageBufferHandle_t;
  * A message buffer handle must not be used after the message buffer has been
  * deleted.
  *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * vMessageBufferDelete() to be available.
+ *
  * @param xMessageBuffer The handle of the message buffer to be deleted.
  *
  */
@@ -703,6 +726,9 @@ typedef StreamBufferHandle_t MessageBufferHandle_t;
  * cannot accept any more messages, of any size, until space is made available
  * by a message being removed from the message buffer.
  *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xMessageBufferIsFull() to be available.
+ *
  * @param xMessageBuffer The handle of the message buffer being queried.
  *
  * @return If the message buffer referenced by xMessageBuffer is full then
@@ -719,6 +745,9 @@ typedef StreamBufferHandle_t MessageBufferHandle_t;
  *
  * Tests to see if a message buffer is empty (does not contain any messages).
  *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xMessageBufferIsEmpty() to be available.
+ *
  * @param xMessageBuffer The handle of the message buffer being queried.
  *
  * @return If the message buffer referenced by xMessageBuffer is empty then
@@ -739,6 +768,9 @@ typedef StreamBufferHandle_t MessageBufferHandle_t;
  *
  * A message buffer can only be reset if there are no tasks blocked on it.
  *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xMessageBufferReset() to be available.
+ *
  * @param xMessageBuffer The handle of the message buffer being reset.
  *
  * @return If the message buffer was reset then pdPASS is returned.  If the
@@ -760,6 +792,9 @@ typedef StreamBufferHandle_t MessageBufferHandle_t;
  * @endcode
  * Returns the number of bytes of free space in the message buffer.
  *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xMessageBufferSpaceAvailable() to be available.
+ *
  * @param xMessageBuffer The handle of the message buffer being queried.
  *
  * @return The number of bytes that can be written to the message buffer before
@@ -786,6 +821,9 @@ typedef StreamBufferHandle_t MessageBufferHandle_t;
  * Useful if xMessageBufferReceive() returned 0 because the size of the buffer
  * passed into xMessageBufferReceive() was too small to hold the next message.
  *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xMessageBufferNextLengthBytes() to be available.
+ *
  * @param xMessageBuffer The handle of the message buffer being queried.
  *
  * @return The length (in bytes) of the next message in the message buffer, or 0
@@ -817,6 +855,9 @@ typedef StreamBufferHandle_t MessageBufferHandle_t;
  * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
  * additional information.
  *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xMessageBufferSendCompletedFromISR() to be available.
+ *
  * @param xMessageBuffer The handle of the stream buffer to which data was
  * written.
  *
@@ -858,6 +899,9 @@ typedef StreamBufferHandle_t MessageBufferHandle_t;
  * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
  * additional information.
  *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xMessageBufferReceiveCompletedFromISR() to be available.
+ *
  * @param xMessageBuffer The handle of the stream buffer from which data was
  * read.
  *
diff --git a/include/stream_buffer.h b/include/stream_buffer.h
index d3ed9aff4..94a0e0cd7 100644
--- a/include/stream_buffer.h
+++ b/include/stream_buffer.h
@@ -91,6 +91,8 @@ typedef void (* StreamBufferCallbackFunction_t)( StreamBufferHandle_t xStreamBuf
  *
  * configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in
  * FreeRTOSConfig.h for xStreamBufferCreate() to be available.
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xStreamBufferCreate() to be available.
  *
  * @param xBufferSizeBytes The total number of bytes the stream buffer will be
  * able to hold at any one time.
@@ -167,15 +169,17 @@ typedef void (* StreamBufferCallbackFunction_t)( StreamBufferHandle_t xStreamBuf
  *
  * @code{c}
  * StreamBufferHandle_t xStreamBufferCreateStatic( size_t xBufferSizeBytes,
- *                                              size_t xTriggerLevelBytes,
- *                                              uint8_t *pucStreamBufferStorageArea,
- *                                              StaticStreamBuffer_t *pxStaticStreamBuffer );
+ *                                                 size_t xTriggerLevelBytes,
+ *                                                 uint8_t *pucStreamBufferStorageArea,
+ *                                                 StaticStreamBuffer_t *pxStaticStreamBuffer );
  * @endcode
  * Creates a new stream buffer using statically allocated memory.  See
  * xStreamBufferCreate() for a version that uses dynamically allocated memory.
  *
  * configSUPPORT_STATIC_ALLOCATION must be set to 1 in FreeRTOSConfig.h for
- * xStreamBufferCreateStatic() to be available.
+ * xStreamBufferCreateStatic() to be available. configUSE_STREAM_BUFFERS must be
+ * set to 1 in for FreeRTOSConfig.h for xStreamBufferCreateStatic() to be
+ * available.
  *
  * @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the
  * pucStreamBufferStorageArea parameter.
@@ -273,6 +277,9 @@ typedef void (* StreamBufferCallbackFunction_t)( StreamBufferHandle_t xStreamBuf
  * buffer and storage area buffer. These are the same buffers that are supplied
  * at the time of creation.
  *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xStreamBufferGetStaticBuffers() to be available.
+ *
  * @param xStreamBuffer The stream buffer for which to retrieve the buffers.
  *
  * @param ppucStreamBufferStorageArea Used to return a pointer to the stream
@@ -297,9 +304,9 @@ typedef void (* StreamBufferCallbackFunction_t)( StreamBufferHandle_t xStreamBuf
  *
  * @code{c}
  * size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
- *                        const void *pvTxData,
- *                        size_t xDataLengthBytes,
- *                        TickType_t xTicksToWait );
+ *                           const void *pvTxData,
+ *                           size_t xDataLengthBytes,
+ *                           TickType_t xTicksToWait );
  * @endcode
  *
  * Sends bytes to a stream buffer.  The bytes are copied into the stream buffer.
@@ -323,6 +330,9 @@ typedef void (* StreamBufferCallbackFunction_t)( StreamBufferHandle_t xStreamBuf
  * xStreamBufferSendFromISR() to write to a stream buffer from an interrupt
  * service routine (ISR).
  *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xStreamBufferSend() to be available.
+ *
  * @param xStreamBuffer The handle of the stream buffer to which a stream is
  * being sent.
  *
@@ -394,9 +404,9 @@ size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
  *
  * @code{c}
  * size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
- *                               const void *pvTxData,
- *                               size_t xDataLengthBytes,
- *                               BaseType_t *pxHigherPriorityTaskWoken );
+ *                                  const void *pvTxData,
+ *                                  size_t xDataLengthBytes,
+ *                                  BaseType_t *pxHigherPriorityTaskWoken );
  * @endcode
  *
  * Interrupt safe version of the API function that sends a stream of bytes to
@@ -421,6 +431,9 @@ size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
  * xStreamBufferSendFromISR() to write to a stream buffer from an interrupt
  * service routine (ISR).
  *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xStreamBufferSendFromISR() to be available.
+ *
  * @param xStreamBuffer The handle of the stream buffer to which a stream is
  * being sent.
  *
@@ -495,9 +508,9 @@ size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
  *
  * @code{c}
  * size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
- *                           void *pvRxData,
- *                           size_t xBufferLengthBytes,
- *                           TickType_t xTicksToWait );
+ *                              void *pvRxData,
+ *                              size_t xBufferLengthBytes,
+ *                              TickType_t xTicksToWait );
  * @endcode
  *
  * Receives bytes from a stream buffer.
@@ -521,6 +534,9 @@ size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
  * xStreamBufferReceiveFromISR() to read from a stream buffer from an
  * interrupt service routine (ISR).
  *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xStreamBufferReceive() to be available.
+ *
  * @param xStreamBuffer The handle of the stream buffer from which bytes are to
  * be received.
  *
@@ -584,9 +600,9 @@ size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
  *
  * @code{c}
  * size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
- *                                  void *pvRxData,
- *                                  size_t xBufferLengthBytes,
- *                                  BaseType_t *pxHigherPriorityTaskWoken );
+ *                                     void *pvRxData,
+ *                                     size_t xBufferLengthBytes,
+ *                                     BaseType_t *pxHigherPriorityTaskWoken );
  * @endcode
  *
  * An interrupt safe version of the API function that receives bytes from a
@@ -596,6 +612,9 @@ size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
  * Use xStreamBufferReceiveFromISR() to read bytes from a stream buffer from an
  * interrupt service routine (ISR).
  *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xStreamBufferReceiveFromISR() to be available.
+ *
  * @param xStreamBuffer The handle of the stream buffer from which a stream
  * is being received.
  *
@@ -680,6 +699,9 @@ size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
  * A stream buffer handle must not be used after the stream buffer has been
  * deleted.
  *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * vStreamBufferDelete() to be available.
+ *
  * @param xStreamBuffer The handle of the stream buffer to be deleted.
  *
  * \defgroup vStreamBufferDelete vStreamBufferDelete
@@ -697,6 +719,9 @@ void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTI
  * Queries a stream buffer to see if it is full.  A stream buffer is full if it
  * does not have any free space, and therefore cannot accept any more data.
  *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xStreamBufferIsFull() to be available.
+ *
  * @param xStreamBuffer The handle of the stream buffer being queried.
  *
  * @return If the stream buffer is full then pdTRUE is returned.  Otherwise
@@ -717,6 +742,9 @@ BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_
  * Queries a stream buffer to see if it is empty.  A stream buffer is empty if
  * it does not contain any data.
  *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xStreamBufferIsEmpty() to be available.
+ *
  * @param xStreamBuffer The handle of the stream buffer being queried.
  *
  * @return If the stream buffer is empty then pdTRUE is returned.  Otherwise
@@ -739,6 +767,9 @@ BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED
  * are no tasks blocked waiting to either send to or receive from the stream
  * buffer.
  *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xStreamBufferReset() to be available.
+ *
  * @param xStreamBuffer The handle of the stream buffer being reset.
  *
  * @return If the stream buffer is reset then pdPASS is returned.  If there was
@@ -761,6 +792,9 @@ BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_F
  * equal to the amount of data that can be sent to the stream buffer before it
  * is full.
  *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xStreamBufferSpacesAvailable() to be available.
+ *
  * @param xStreamBuffer The handle of the stream buffer being queried.
  *
  * @return The number of bytes that can be written to the stream buffer before
@@ -782,6 +816,9 @@ size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) PRIVIL
  * the number of bytes that can be read from the stream buffer before the stream
  * buffer would be empty.
  *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xStreamBufferBytesAvailable() to be available.
+ *
  * @param xStreamBuffer The handle of the stream buffer being queried.
  *
  * @return The number of bytes that can be read from the stream buffer before
@@ -816,6 +853,9 @@ size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) PRIVILE
  * A trigger level is set when the stream buffer is created, and can be modified
  * using xStreamBufferSetTriggerLevel().
  *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xStreamBufferSetTriggerLevel() to be available.
+ *
  * @param xStreamBuffer The handle of the stream buffer being updated.
  *
  * @param xTriggerLevel The new trigger level for the stream buffer.
@@ -850,6 +890,9 @@ BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
  * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
  * additional information.
  *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xStreamBufferSendCompletedFromISR() to be available.
+ *
  * @param xStreamBuffer The handle of the stream buffer to which data was
  * written.
  *
@@ -891,6 +934,9 @@ BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer
  * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
  * additional information.
  *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xStreamBufferReceiveCompletedFromISR() to be available.
+ *
  * @param xStreamBuffer The handle of the stream buffer from which data was
  * read.
  *
@@ -924,6 +970,9 @@ BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuf
  * vStreamBufferSetStreamBufferNotificationIndex, this function returns the
  * default value (tskDEFAULT_INDEX_TO_NOTIFY).
  *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * uxStreamBufferGetStreamBufferNotificationIndex() to be available.
+ *
  * @param xStreamBuffer The handle of the stream buffer for which the task
  * notification index is retrieved.
  *
@@ -951,6 +1000,9 @@ UBaseType_t uxStreamBufferGetStreamBufferNotificationIndex( StreamBufferHandle_t
  * before attempting to send or receive data from the stream buffer to avoid
  * inconsistencies.
  *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * vStreamBufferSetStreamBufferNotificationIndex() to be available.
+ *
  * @param xStreamBuffer The handle of the stream buffer for which the task
  * notification index is set.
  *
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/mpu_wrappers_v2_asm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/mpu_wrappers_v2_asm.c
index fb167a699..1fb67891d 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/mpu_wrappers_v2_asm.c
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/mpu_wrappers_v2_asm.c
@@ -1690,117 +1690,133 @@
     #endif /* if ( configUSE_TIMERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupWaitBitsImpl                   \n"
-            "                                                       \n"
-            " push {r0, r1}                                         \n"
-            " mrs r0, control                                       \n"
-            " movs r1, #1                                           \n"
-            " tst r0, r1                                            \n"
-            " pop {r0, r1}                                          \n"
-            " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
-            " MPU_xEventGroupWaitBits_Priv:                         \n"
-            "     b MPU_xEventGroupWaitBitsImpl                     \n"
-            " MPU_xEventGroupWaitBits_Unpriv:                       \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
-        );
-    }
+        EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupWaitBitsImpl                   \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
+                " MPU_xEventGroupWaitBits_Priv:                         \n"
+                "     b MPU_xEventGroupWaitBitsImpl                     \n"
+                " MPU_xEventGroupWaitBits_Unpriv:                       \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                          const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                          const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupClearBitsImpl                  \n"
-            "                                                       \n"
-            " push {r0, r1}                                         \n"
-            " mrs r0, control                                       \n"
-            " movs r1, #1                                           \n"
-            " tst r0, r1                                            \n"
-            " pop {r0, r1}                                          \n"
-            " bne MPU_xEventGroupClearBits_Unpriv                   \n"
-            " MPU_xEventGroupClearBits_Priv:                        \n"
-            "     b MPU_xEventGroupClearBitsImpl                    \n"
-            " MPU_xEventGroupClearBits_Unpriv:                      \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
-        );
-    }
+        EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                              const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                              const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupClearBitsImpl                  \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xEventGroupClearBits_Unpriv                   \n"
+                " MPU_xEventGroupClearBits_Priv:                        \n"
+                "     b MPU_xEventGroupClearBitsImpl                    \n"
+                " MPU_xEventGroupClearBits_Unpriv:                      \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                        const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                        const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupSetBitsImpl                    \n"
-            "                                                       \n"
-            " push {r0, r1}                                         \n"
-            " mrs r0, control                                       \n"
-            " movs r1, #1                                           \n"
-            " tst r0, r1                                            \n"
-            " pop {r0, r1}                                          \n"
-            " bne MPU_xEventGroupSetBits_Unpriv                     \n"
-            " MPU_xEventGroupSetBits_Priv:                          \n"
-            "     b MPU_xEventGroupSetBitsImpl                      \n"
-            " MPU_xEventGroupSetBits_Unpriv:                        \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
-        );
-    }
+        EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                            const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                            const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupSetBitsImpl                    \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xEventGroupSetBits_Unpriv                     \n"
+                " MPU_xEventGroupSetBits_Priv:                          \n"
+                "     b MPU_xEventGroupSetBitsImpl                      \n"
+                " MPU_xEventGroupSetBits_Unpriv:                        \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                     const EventBits_t uxBitsToSet,
-                                     const EventBits_t uxBitsToWaitFor,
-                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                     const EventBits_t uxBitsToSet,
-                                     const EventBits_t uxBitsToWaitFor,
-                                     TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupSyncImpl                       \n"
-            "                                                       \n"
-            " push {r0, r1}                                         \n"
-            " mrs r0, control                                       \n"
-            " movs r1, #1                                           \n"
-            " tst r0, r1                                            \n"
-            " pop {r0, r1}                                          \n"
-            " bne MPU_xEventGroupSync_Unpriv                        \n"
-            " MPU_xEventGroupSync_Priv:                             \n"
-            "     b MPU_xEventGroupSyncImpl                         \n"
-            " MPU_xEventGroupSync_Unpriv:                           \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
-        );
-    }
+        EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToSet,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToSet,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupSyncImpl                       \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xEventGroupSync_Unpriv                        \n"
+                " MPU_xEventGroupSync_Priv:                             \n"
+                "     b MPU_xEventGroupSyncImpl                         \n"
+                " MPU_xEventGroupSync_Unpriv:                           \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    #if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
 
         UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
@@ -1826,10 +1842,10 @@
             );
         }
 
-    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-    #if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
 
         void MPU_vEventGroupSetNumber( void * xEventGroup,
                                        UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
@@ -1857,221 +1873,253 @@
             );
         }
 
-    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                                  const void * pvTxData,
-                                  size_t xDataLengthBytes,
-                                  TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                                  const void * pvTxData,
-                                  size_t xDataLengthBytes,
-                                  TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferSendImpl                     \n"
-            "                                                       \n"
-            " push {r0, r1}                                         \n"
-            " mrs r0, control                                       \n"
-            " movs r1, #1                                           \n"
-            " tst r0, r1                                            \n"
-            " pop {r0, r1}                                          \n"
-            " bne MPU_xStreamBufferSend_Unpriv                      \n"
-            " MPU_xStreamBufferSend_Priv:                           \n"
-            "     b MPU_xStreamBufferSendImpl                       \n"
-            " MPU_xStreamBufferSend_Unpriv:                         \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                      const void * pvTxData,
+                                      size_t xDataLengthBytes,
+                                      TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                      const void * pvTxData,
+                                      size_t xDataLengthBytes,
+                                      TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferSendImpl                     \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xStreamBufferSend_Unpriv                      \n"
+                " MPU_xStreamBufferSend_Priv:                           \n"
+                "     b MPU_xStreamBufferSendImpl                       \n"
+                " MPU_xStreamBufferSend_Unpriv:                         \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                     void * pvRxData,
-                                     size_t xBufferLengthBytes,
-                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                     void * pvRxData,
-                                     size_t xBufferLengthBytes,
-                                     TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferReceiveImpl                  \n"
-            "                                                       \n"
-            " push {r0, r1}                                         \n"
-            " mrs r0, control                                       \n"
-            " movs r1, #1                                           \n"
-            " tst r0, r1                                            \n"
-            " pop {r0, r1}                                          \n"
-            " bne MPU_xStreamBufferReceive_Unpriv                   \n"
-            " MPU_xStreamBufferReceive_Priv:                        \n"
-            "     b MPU_xStreamBufferReceiveImpl                    \n"
-            " MPU_xStreamBufferReceive_Unpriv:                      \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                         void * pvRxData,
+                                         size_t xBufferLengthBytes,
+                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                         void * pvRxData,
+                                         size_t xBufferLengthBytes,
+                                         TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferReceiveImpl                  \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xStreamBufferReceive_Unpriv                   \n"
+                " MPU_xStreamBufferReceive_Priv:                        \n"
+                "     b MPU_xStreamBufferReceiveImpl                    \n"
+                " MPU_xStreamBufferReceive_Unpriv:                      \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferIsFullImpl                   \n"
-            "                                                       \n"
-            " push {r0, r1}                                         \n"
-            " mrs r0, control                                       \n"
-            " movs r1, #1                                           \n"
-            " tst r0, r1                                            \n"
-            " pop {r0, r1}                                          \n"
-            " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
-            " MPU_xStreamBufferIsFull_Priv:                         \n"
-            "     b MPU_xStreamBufferIsFullImpl                     \n"
-            " MPU_xStreamBufferIsFull_Unpriv:                       \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
-        );
-    }
+        BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferIsFullImpl                   \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
+                " MPU_xStreamBufferIsFull_Priv:                         \n"
+                "     b MPU_xStreamBufferIsFullImpl                     \n"
+                " MPU_xStreamBufferIsFull_Unpriv:                       \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
-            "                                                       \n"
-            " push {r0, r1}                                         \n"
-            " mrs r0, control                                       \n"
-            " movs r1, #1                                           \n"
-            " tst r0, r1                                            \n"
-            " pop {r0, r1}                                          \n"
-            " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
-            " MPU_xStreamBufferIsEmpty_Priv:                        \n"
-            "     b MPU_xStreamBufferIsEmptyImpl                    \n"
-            " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
-        );
-    }
+        BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
+                " MPU_xStreamBufferIsEmpty_Priv:                        \n"
+                "     b MPU_xStreamBufferIsEmptyImpl                    \n"
+                " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
-            "                                                       \n"
-            " push {r0, r1}                                         \n"
-            " mrs r0, control                                       \n"
-            " movs r1, #1                                           \n"
-            " tst r0, r1                                            \n"
-            " pop {r0, r1}                                          \n"
-            " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
-            " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
-            "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
-            " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
+                " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
+                "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
+                " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
-            "                                                       \n"
-            " push {r0, r1}                                         \n"
-            " mrs r0, control                                       \n"
-            " movs r1, #1                                           \n"
-            " tst r0, r1                                            \n"
-            " pop {r0, r1}                                          \n"
-            " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
-            " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
-            "     b MPU_xStreamBufferBytesAvailableImpl             \n"
-            " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
+                " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
+                "     b MPU_xStreamBufferBytesAvailableImpl             \n"
+                " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                                 size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                                 size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
-            "                                                       \n"
-            " push {r0, r1}                                         \n"
-            " mrs r0, control                                       \n"
-            " movs r1, #1                                           \n"
-            " tst r0, r1                                            \n"
-            " pop {r0, r1}                                          \n"
-            " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
-            " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
-            "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
-            " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
-        );
-    }
+        BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                     size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                     size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
+                " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
+                "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
+                " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
-            "                                                       \n"
-            " push {r0, r1}                                         \n"
-            " mrs r0, control                                       \n"
-            " movs r1, #1                                           \n"
-            " tst r0, r1                                            \n"
-            " pop {r0, r1}                                          \n"
-            " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
-            " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
-            "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
-            " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
+                " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
+                "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
+                " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/mpu_wrappers_v2_asm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/mpu_wrappers_v2_asm.c
index fb167a699..1fb67891d 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/mpu_wrappers_v2_asm.c
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/mpu_wrappers_v2_asm.c
@@ -1690,117 +1690,133 @@
     #endif /* if ( configUSE_TIMERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupWaitBitsImpl                   \n"
-            "                                                       \n"
-            " push {r0, r1}                                         \n"
-            " mrs r0, control                                       \n"
-            " movs r1, #1                                           \n"
-            " tst r0, r1                                            \n"
-            " pop {r0, r1}                                          \n"
-            " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
-            " MPU_xEventGroupWaitBits_Priv:                         \n"
-            "     b MPU_xEventGroupWaitBitsImpl                     \n"
-            " MPU_xEventGroupWaitBits_Unpriv:                       \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
-        );
-    }
+        EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupWaitBitsImpl                   \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
+                " MPU_xEventGroupWaitBits_Priv:                         \n"
+                "     b MPU_xEventGroupWaitBitsImpl                     \n"
+                " MPU_xEventGroupWaitBits_Unpriv:                       \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                          const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                          const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupClearBitsImpl                  \n"
-            "                                                       \n"
-            " push {r0, r1}                                         \n"
-            " mrs r0, control                                       \n"
-            " movs r1, #1                                           \n"
-            " tst r0, r1                                            \n"
-            " pop {r0, r1}                                          \n"
-            " bne MPU_xEventGroupClearBits_Unpriv                   \n"
-            " MPU_xEventGroupClearBits_Priv:                        \n"
-            "     b MPU_xEventGroupClearBitsImpl                    \n"
-            " MPU_xEventGroupClearBits_Unpriv:                      \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
-        );
-    }
+        EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                              const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                              const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupClearBitsImpl                  \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xEventGroupClearBits_Unpriv                   \n"
+                " MPU_xEventGroupClearBits_Priv:                        \n"
+                "     b MPU_xEventGroupClearBitsImpl                    \n"
+                " MPU_xEventGroupClearBits_Unpriv:                      \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                        const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                        const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupSetBitsImpl                    \n"
-            "                                                       \n"
-            " push {r0, r1}                                         \n"
-            " mrs r0, control                                       \n"
-            " movs r1, #1                                           \n"
-            " tst r0, r1                                            \n"
-            " pop {r0, r1}                                          \n"
-            " bne MPU_xEventGroupSetBits_Unpriv                     \n"
-            " MPU_xEventGroupSetBits_Priv:                          \n"
-            "     b MPU_xEventGroupSetBitsImpl                      \n"
-            " MPU_xEventGroupSetBits_Unpriv:                        \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
-        );
-    }
+        EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                            const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                            const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupSetBitsImpl                    \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xEventGroupSetBits_Unpriv                     \n"
+                " MPU_xEventGroupSetBits_Priv:                          \n"
+                "     b MPU_xEventGroupSetBitsImpl                      \n"
+                " MPU_xEventGroupSetBits_Unpriv:                        \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                     const EventBits_t uxBitsToSet,
-                                     const EventBits_t uxBitsToWaitFor,
-                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                     const EventBits_t uxBitsToSet,
-                                     const EventBits_t uxBitsToWaitFor,
-                                     TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupSyncImpl                       \n"
-            "                                                       \n"
-            " push {r0, r1}                                         \n"
-            " mrs r0, control                                       \n"
-            " movs r1, #1                                           \n"
-            " tst r0, r1                                            \n"
-            " pop {r0, r1}                                          \n"
-            " bne MPU_xEventGroupSync_Unpriv                        \n"
-            " MPU_xEventGroupSync_Priv:                             \n"
-            "     b MPU_xEventGroupSyncImpl                         \n"
-            " MPU_xEventGroupSync_Unpriv:                           \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
-        );
-    }
+        EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToSet,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToSet,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupSyncImpl                       \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xEventGroupSync_Unpriv                        \n"
+                " MPU_xEventGroupSync_Priv:                             \n"
+                "     b MPU_xEventGroupSyncImpl                         \n"
+                " MPU_xEventGroupSync_Unpriv:                           \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    #if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
 
         UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
@@ -1826,10 +1842,10 @@
             );
         }
 
-    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-    #if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
 
         void MPU_vEventGroupSetNumber( void * xEventGroup,
                                        UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
@@ -1857,221 +1873,253 @@
             );
         }
 
-    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                                  const void * pvTxData,
-                                  size_t xDataLengthBytes,
-                                  TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                                  const void * pvTxData,
-                                  size_t xDataLengthBytes,
-                                  TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferSendImpl                     \n"
-            "                                                       \n"
-            " push {r0, r1}                                         \n"
-            " mrs r0, control                                       \n"
-            " movs r1, #1                                           \n"
-            " tst r0, r1                                            \n"
-            " pop {r0, r1}                                          \n"
-            " bne MPU_xStreamBufferSend_Unpriv                      \n"
-            " MPU_xStreamBufferSend_Priv:                           \n"
-            "     b MPU_xStreamBufferSendImpl                       \n"
-            " MPU_xStreamBufferSend_Unpriv:                         \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                      const void * pvTxData,
+                                      size_t xDataLengthBytes,
+                                      TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                      const void * pvTxData,
+                                      size_t xDataLengthBytes,
+                                      TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferSendImpl                     \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xStreamBufferSend_Unpriv                      \n"
+                " MPU_xStreamBufferSend_Priv:                           \n"
+                "     b MPU_xStreamBufferSendImpl                       \n"
+                " MPU_xStreamBufferSend_Unpriv:                         \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                     void * pvRxData,
-                                     size_t xBufferLengthBytes,
-                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                     void * pvRxData,
-                                     size_t xBufferLengthBytes,
-                                     TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferReceiveImpl                  \n"
-            "                                                       \n"
-            " push {r0, r1}                                         \n"
-            " mrs r0, control                                       \n"
-            " movs r1, #1                                           \n"
-            " tst r0, r1                                            \n"
-            " pop {r0, r1}                                          \n"
-            " bne MPU_xStreamBufferReceive_Unpriv                   \n"
-            " MPU_xStreamBufferReceive_Priv:                        \n"
-            "     b MPU_xStreamBufferReceiveImpl                    \n"
-            " MPU_xStreamBufferReceive_Unpriv:                      \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                         void * pvRxData,
+                                         size_t xBufferLengthBytes,
+                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                         void * pvRxData,
+                                         size_t xBufferLengthBytes,
+                                         TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferReceiveImpl                  \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xStreamBufferReceive_Unpriv                   \n"
+                " MPU_xStreamBufferReceive_Priv:                        \n"
+                "     b MPU_xStreamBufferReceiveImpl                    \n"
+                " MPU_xStreamBufferReceive_Unpriv:                      \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferIsFullImpl                   \n"
-            "                                                       \n"
-            " push {r0, r1}                                         \n"
-            " mrs r0, control                                       \n"
-            " movs r1, #1                                           \n"
-            " tst r0, r1                                            \n"
-            " pop {r0, r1}                                          \n"
-            " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
-            " MPU_xStreamBufferIsFull_Priv:                         \n"
-            "     b MPU_xStreamBufferIsFullImpl                     \n"
-            " MPU_xStreamBufferIsFull_Unpriv:                       \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
-        );
-    }
+        BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferIsFullImpl                   \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
+                " MPU_xStreamBufferIsFull_Priv:                         \n"
+                "     b MPU_xStreamBufferIsFullImpl                     \n"
+                " MPU_xStreamBufferIsFull_Unpriv:                       \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
-            "                                                       \n"
-            " push {r0, r1}                                         \n"
-            " mrs r0, control                                       \n"
-            " movs r1, #1                                           \n"
-            " tst r0, r1                                            \n"
-            " pop {r0, r1}                                          \n"
-            " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
-            " MPU_xStreamBufferIsEmpty_Priv:                        \n"
-            "     b MPU_xStreamBufferIsEmptyImpl                    \n"
-            " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
-        );
-    }
+        BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
+                " MPU_xStreamBufferIsEmpty_Priv:                        \n"
+                "     b MPU_xStreamBufferIsEmptyImpl                    \n"
+                " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
-            "                                                       \n"
-            " push {r0, r1}                                         \n"
-            " mrs r0, control                                       \n"
-            " movs r1, #1                                           \n"
-            " tst r0, r1                                            \n"
-            " pop {r0, r1}                                          \n"
-            " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
-            " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
-            "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
-            " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
+                " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
+                "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
+                " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
-            "                                                       \n"
-            " push {r0, r1}                                         \n"
-            " mrs r0, control                                       \n"
-            " movs r1, #1                                           \n"
-            " tst r0, r1                                            \n"
-            " pop {r0, r1}                                          \n"
-            " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
-            " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
-            "     b MPU_xStreamBufferBytesAvailableImpl             \n"
-            " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
+                " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
+                "     b MPU_xStreamBufferBytesAvailableImpl             \n"
+                " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                                 size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                                 size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
-            "                                                       \n"
-            " push {r0, r1}                                         \n"
-            " mrs r0, control                                       \n"
-            " movs r1, #1                                           \n"
-            " tst r0, r1                                            \n"
-            " pop {r0, r1}                                          \n"
-            " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
-            " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
-            "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
-            " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
-        );
-    }
+        BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                     size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                     size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
+                " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
+                "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
+                " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
-            "                                                       \n"
-            " push {r0, r1}                                         \n"
-            " mrs r0, control                                       \n"
-            " movs r1, #1                                           \n"
-            " tst r0, r1                                            \n"
-            " pop {r0, r1}                                          \n"
-            " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
-            " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
-            "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
-            " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
+                " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
+                "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
+                " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/mpu_wrappers_v2_asm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/mpu_wrappers_v2_asm.c
index 4f66448f9..02229d964 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/mpu_wrappers_v2_asm.c
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/mpu_wrappers_v2_asm.c
@@ -1634,113 +1634,130 @@
     #endif /* if ( configUSE_TIMERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupWaitBitsImpl                   \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
-            " MPU_xEventGroupWaitBits_Priv:                         \n"
-            "     b MPU_xEventGroupWaitBitsImpl                     \n"
-            " MPU_xEventGroupWaitBits_Unpriv:                       \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
-        );
-    }
+        EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupWaitBitsImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
+                " MPU_xEventGroupWaitBits_Priv:                         \n"
+                "     b MPU_xEventGroupWaitBitsImpl                     \n"
+                " MPU_xEventGroupWaitBits_Unpriv:                       \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                          const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                          const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupClearBitsImpl                  \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xEventGroupClearBits_Unpriv                   \n"
-            " MPU_xEventGroupClearBits_Priv:                        \n"
-            "     b MPU_xEventGroupClearBitsImpl                    \n"
-            " MPU_xEventGroupClearBits_Unpriv:                      \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
-        );
-    }
+        EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                              const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                              const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupClearBitsImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xEventGroupClearBits_Unpriv                   \n"
+                " MPU_xEventGroupClearBits_Priv:                        \n"
+                "     b MPU_xEventGroupClearBitsImpl                    \n"
+                " MPU_xEventGroupClearBits_Unpriv:                      \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                        const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
+
+        EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                            const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                            const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupSetBitsImpl                    \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xEventGroupSetBits_Unpriv                     \n"
+                " MPU_xEventGroupSetBits_Priv:                          \n"
+                "     b MPU_xEventGroupSetBitsImpl                      \n"
+                " MPU_xEventGroupSetBits_Unpriv:                        \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 
-    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                        const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupSetBitsImpl                    \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xEventGroupSetBits_Unpriv                     \n"
-            " MPU_xEventGroupSetBits_Priv:                          \n"
-            "     b MPU_xEventGroupSetBitsImpl                      \n"
-            " MPU_xEventGroupSetBits_Unpriv:                        \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
-        );
-    }
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                     const EventBits_t uxBitsToSet,
-                                     const EventBits_t uxBitsToWaitFor,
-                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                     const EventBits_t uxBitsToSet,
-                                     const EventBits_t uxBitsToWaitFor,
-                                     TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupSyncImpl                       \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xEventGroupSync_Unpriv                        \n"
-            " MPU_xEventGroupSync_Priv:                             \n"
-            "     b MPU_xEventGroupSyncImpl                         \n"
-            " MPU_xEventGroupSync_Unpriv:                           \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
-        );
-    }
+        EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToSet,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToSet,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupSyncImpl                       \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xEventGroupSync_Unpriv                        \n"
+                " MPU_xEventGroupSync_Priv:                             \n"
+                "     b MPU_xEventGroupSyncImpl                         \n"
+                " MPU_xEventGroupSync_Unpriv:                           \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    #if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
 
         UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
@@ -1765,10 +1782,10 @@
             );
         }
 
-    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-    #if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
 
         void MPU_vEventGroupSetNumber( void * xEventGroup,
                                        UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
@@ -1795,213 +1812,245 @@
             );
         }
 
-    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                                  const void * pvTxData,
-                                  size_t xDataLengthBytes,
-                                  TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                                  const void * pvTxData,
-                                  size_t xDataLengthBytes,
-                                  TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferSendImpl                     \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferSend_Unpriv                      \n"
-            " MPU_xStreamBufferSend_Priv:                           \n"
-            "     b MPU_xStreamBufferSendImpl                       \n"
-            " MPU_xStreamBufferSend_Unpriv:                         \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                      const void * pvTxData,
+                                      size_t xDataLengthBytes,
+                                      TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                      const void * pvTxData,
+                                      size_t xDataLengthBytes,
+                                      TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferSendImpl                     \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferSend_Unpriv                      \n"
+                " MPU_xStreamBufferSend_Priv:                           \n"
+                "     b MPU_xStreamBufferSendImpl                       \n"
+                " MPU_xStreamBufferSend_Unpriv:                         \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                     void * pvRxData,
-                                     size_t xBufferLengthBytes,
-                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                     void * pvRxData,
-                                     size_t xBufferLengthBytes,
-                                     TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferReceiveImpl                  \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferReceive_Unpriv                   \n"
-            " MPU_xStreamBufferReceive_Priv:                        \n"
-            "     b MPU_xStreamBufferReceiveImpl                    \n"
-            " MPU_xStreamBufferReceive_Unpriv:                      \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                         void * pvRxData,
+                                         size_t xBufferLengthBytes,
+                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                         void * pvRxData,
+                                         size_t xBufferLengthBytes,
+                                         TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferReceiveImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferReceive_Unpriv                   \n"
+                " MPU_xStreamBufferReceive_Priv:                        \n"
+                "     b MPU_xStreamBufferReceiveImpl                    \n"
+                " MPU_xStreamBufferReceive_Unpriv:                      \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferIsFullImpl                   \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
-            " MPU_xStreamBufferIsFull_Priv:                         \n"
-            "     b MPU_xStreamBufferIsFullImpl                     \n"
-            " MPU_xStreamBufferIsFull_Unpriv:                       \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
-        );
-    }
+        BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferIsFullImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
+                " MPU_xStreamBufferIsFull_Priv:                         \n"
+                "     b MPU_xStreamBufferIsFullImpl                     \n"
+                " MPU_xStreamBufferIsFull_Unpriv:                       \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
-            " MPU_xStreamBufferIsEmpty_Priv:                        \n"
-            "     b MPU_xStreamBufferIsEmptyImpl                    \n"
-            " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
-        );
-    }
+        BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
+                " MPU_xStreamBufferIsEmpty_Priv:                        \n"
+                "     b MPU_xStreamBufferIsEmptyImpl                    \n"
+                " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
-            " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
-            "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
-            " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
+                " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
+                "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
+                " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
-            " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
-            "     b MPU_xStreamBufferBytesAvailableImpl             \n"
-            " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
+                " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
+                "     b MPU_xStreamBufferBytesAvailableImpl             \n"
+                " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                                 size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                                 size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
-            " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
-            "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
-            " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
-        );
-    }
+        BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                     size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                     size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
+                " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
+                "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
+                " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
-            " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
-            "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
-            " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
+                " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
+                "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
+                " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/mpu_wrappers_v2_asm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/mpu_wrappers_v2_asm.c
index 4f66448f9..6642c9e20 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/mpu_wrappers_v2_asm.c
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/mpu_wrappers_v2_asm.c
@@ -1634,113 +1634,129 @@
     #endif /* if ( configUSE_TIMERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupWaitBitsImpl                   \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
-            " MPU_xEventGroupWaitBits_Priv:                         \n"
-            "     b MPU_xEventGroupWaitBitsImpl                     \n"
-            " MPU_xEventGroupWaitBits_Unpriv:                       \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
-        );
-    }
+        EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupWaitBitsImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
+                " MPU_xEventGroupWaitBits_Priv:                         \n"
+                "     b MPU_xEventGroupWaitBitsImpl                     \n"
+                " MPU_xEventGroupWaitBits_Unpriv:                       \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                          const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                          const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupClearBitsImpl                  \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xEventGroupClearBits_Unpriv                   \n"
-            " MPU_xEventGroupClearBits_Priv:                        \n"
-            "     b MPU_xEventGroupClearBitsImpl                    \n"
-            " MPU_xEventGroupClearBits_Unpriv:                      \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
-        );
-    }
+        EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                              const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                              const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupClearBitsImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xEventGroupClearBits_Unpriv                   \n"
+                " MPU_xEventGroupClearBits_Priv:                        \n"
+                "     b MPU_xEventGroupClearBitsImpl                    \n"
+                " MPU_xEventGroupClearBits_Unpriv:                      \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                        const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                        const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupSetBitsImpl                    \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xEventGroupSetBits_Unpriv                     \n"
-            " MPU_xEventGroupSetBits_Priv:                          \n"
-            "     b MPU_xEventGroupSetBitsImpl                      \n"
-            " MPU_xEventGroupSetBits_Unpriv:                        \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
-        );
-    }
+        EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                            const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                            const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupSetBitsImpl                    \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xEventGroupSetBits_Unpriv                     \n"
+                " MPU_xEventGroupSetBits_Priv:                          \n"
+                "     b MPU_xEventGroupSetBitsImpl                      \n"
+                " MPU_xEventGroupSetBits_Unpriv:                        \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                     const EventBits_t uxBitsToSet,
-                                     const EventBits_t uxBitsToWaitFor,
-                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                     const EventBits_t uxBitsToSet,
-                                     const EventBits_t uxBitsToWaitFor,
-                                     TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupSyncImpl                       \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xEventGroupSync_Unpriv                        \n"
-            " MPU_xEventGroupSync_Priv:                             \n"
-            "     b MPU_xEventGroupSyncImpl                         \n"
-            " MPU_xEventGroupSync_Unpriv:                           \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
-        );
-    }
+        EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToSet,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToSet,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupSyncImpl                       \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xEventGroupSync_Unpriv                        \n"
+                " MPU_xEventGroupSync_Priv:                             \n"
+                "     b MPU_xEventGroupSyncImpl                         \n"
+                " MPU_xEventGroupSync_Unpriv:                           \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    #if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
 
         UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
@@ -1765,10 +1781,10 @@
             );
         }
 
-    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-    #if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
 
         void MPU_vEventGroupSetNumber( void * xEventGroup,
                                        UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
@@ -1795,213 +1811,245 @@
             );
         }
 
-    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                                  const void * pvTxData,
-                                  size_t xDataLengthBytes,
-                                  TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                                  const void * pvTxData,
-                                  size_t xDataLengthBytes,
-                                  TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferSendImpl                     \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferSend_Unpriv                      \n"
-            " MPU_xStreamBufferSend_Priv:                           \n"
-            "     b MPU_xStreamBufferSendImpl                       \n"
-            " MPU_xStreamBufferSend_Unpriv:                         \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                      const void * pvTxData,
+                                      size_t xDataLengthBytes,
+                                      TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                      const void * pvTxData,
+                                      size_t xDataLengthBytes,
+                                      TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferSendImpl                     \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferSend_Unpriv                      \n"
+                " MPU_xStreamBufferSend_Priv:                           \n"
+                "     b MPU_xStreamBufferSendImpl                       \n"
+                " MPU_xStreamBufferSend_Unpriv:                         \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                     void * pvRxData,
-                                     size_t xBufferLengthBytes,
-                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                     void * pvRxData,
-                                     size_t xBufferLengthBytes,
-                                     TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferReceiveImpl                  \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferReceive_Unpriv                   \n"
-            " MPU_xStreamBufferReceive_Priv:                        \n"
-            "     b MPU_xStreamBufferReceiveImpl                    \n"
-            " MPU_xStreamBufferReceive_Unpriv:                      \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                         void * pvRxData,
+                                         size_t xBufferLengthBytes,
+                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                         void * pvRxData,
+                                         size_t xBufferLengthBytes,
+                                         TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferReceiveImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferReceive_Unpriv                   \n"
+                " MPU_xStreamBufferReceive_Priv:                        \n"
+                "     b MPU_xStreamBufferReceiveImpl                    \n"
+                " MPU_xStreamBufferReceive_Unpriv:                      \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferIsFullImpl                   \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
-            " MPU_xStreamBufferIsFull_Priv:                         \n"
-            "     b MPU_xStreamBufferIsFullImpl                     \n"
-            " MPU_xStreamBufferIsFull_Unpriv:                       \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
-        );
-    }
+        BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferIsFullImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
+                " MPU_xStreamBufferIsFull_Priv:                         \n"
+                "     b MPU_xStreamBufferIsFullImpl                     \n"
+                " MPU_xStreamBufferIsFull_Unpriv:                       \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
-            " MPU_xStreamBufferIsEmpty_Priv:                        \n"
-            "     b MPU_xStreamBufferIsEmptyImpl                    \n"
-            " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
-        );
-    }
+        BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
+                " MPU_xStreamBufferIsEmpty_Priv:                        \n"
+                "     b MPU_xStreamBufferIsEmptyImpl                    \n"
+                " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
-            " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
-            "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
-            " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
+                " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
+                "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
+                " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
-            " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
-            "     b MPU_xStreamBufferBytesAvailableImpl             \n"
-            " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
+                " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
+                "     b MPU_xStreamBufferBytesAvailableImpl             \n"
+                " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                                 size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                                 size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
-            " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
-            "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
-            " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
-        );
-    }
+        BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                     size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                     size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
+                " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
+                "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
+                " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
-            " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
-            "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
-            " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
+                " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
+                "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
+                " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
diff --git a/portable/Common/mpu_wrappers.c b/portable/Common/mpu_wrappers.c
index 03ca77c68..85facbd79 100644
--- a/portable/Common/mpu_wrappers.c
+++ b/portable/Common/mpu_wrappers.c
@@ -1952,7 +1952,7 @@
     #endif /* if ( configUSE_TIMERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+    #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_EVENT_GROUPS == 1 ) )
         EventGroupHandle_t MPU_xEventGroupCreate( void ) /* FREERTOS_SYSTEM_CALL */
         {
             EventGroupHandle_t xReturn;
@@ -1975,10 +1975,10 @@
 
             return xReturn;
         }
-    #endif /* if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) */
+    #endif /* #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_EVENT_GROUPS == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-    #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+    #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_EVENT_GROUPS == 1 ) )
         EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t * pxEventGroupBuffer ) /* FREERTOS_SYSTEM_CALL */
         {
             EventGroupHandle_t xReturn;
@@ -2001,377 +2001,407 @@
 
             return xReturn;
         }
-    #endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+    #endif /* #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_EVENT_GROUPS == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+    #if ( configUSE_EVENT_GROUPS == 1 )
+        EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+                                             const EventBits_t uxBitsToWaitFor,
+                                             const BaseType_t xClearOnExit,
+                                             const BaseType_t xWaitForAllBits,
+                                             TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+        {
+            EventBits_t xReturn;
+
+            if( portIS_PRIVILEGED() == pdFALSE )
+            {
+                portRAISE_PRIVILEGE();
+                portMEMORY_BARRIER();
+
+                xReturn = xEventGroupWaitBits( xEventGroup, uxBitsToWaitFor, xClearOnExit, xWaitForAllBits, xTicksToWait );
+                portMEMORY_BARRIER();
+
+                portRESET_PRIVILEGE();
+                portMEMORY_BARRIER();
+            }
+            else
+            {
+                xReturn = xEventGroupWaitBits( xEventGroup, uxBitsToWaitFor, xClearOnExit, xWaitForAllBits, xTicksToWait );
+            }
+
+            return xReturn;
+        }
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_EVENT_GROUPS == 1 )
+        EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                              const EventBits_t uxBitsToClear ) /* FREERTOS_SYSTEM_CALL */
+        {
+            EventBits_t xReturn;
+
+            if( portIS_PRIVILEGED() == pdFALSE )
+            {
+                portRAISE_PRIVILEGE();
+                portMEMORY_BARRIER();
+
+                xReturn = xEventGroupClearBits( xEventGroup, uxBitsToClear );
+                portMEMORY_BARRIER();
+
+                portRESET_PRIVILEGE();
+                portMEMORY_BARRIER();
+            }
+            else
+            {
+                xReturn = xEventGroupClearBits( xEventGroup, uxBitsToClear );
+            }
+
+            return xReturn;
+        }
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_EVENT_GROUPS == 1 )
+        EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                            const EventBits_t uxBitsToSet ) /* FREERTOS_SYSTEM_CALL */
+        {
+            EventBits_t xReturn;
+
+            if( portIS_PRIVILEGED() == pdFALSE )
+            {
+                portRAISE_PRIVILEGE();
+                portMEMORY_BARRIER();
+
+                xReturn = xEventGroupSetBits( xEventGroup, uxBitsToSet );
+                portMEMORY_BARRIER();
+
+                portRESET_PRIVILEGE();
+                portMEMORY_BARRIER();
+            }
+            else
+            {
+                xReturn = xEventGroupSetBits( xEventGroup, uxBitsToSet );
+            }
+
+            return xReturn;
+        }
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_EVENT_GROUPS == 1 )
+        EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToSet,
                                          const EventBits_t uxBitsToWaitFor,
-                                         const BaseType_t xClearOnExit,
-                                         const BaseType_t xWaitForAllBits,
                                          TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-    {
-        EventBits_t xReturn;
-
-        if( portIS_PRIVILEGED() == pdFALSE )
         {
-            portRAISE_PRIVILEGE();
-            portMEMORY_BARRIER();
+            EventBits_t xReturn;
 
-            xReturn = xEventGroupWaitBits( xEventGroup, uxBitsToWaitFor, xClearOnExit, xWaitForAllBits, xTicksToWait );
-            portMEMORY_BARRIER();
+            if( portIS_PRIVILEGED() == pdFALSE )
+            {
+                portRAISE_PRIVILEGE();
+                portMEMORY_BARRIER();
 
-            portRESET_PRIVILEGE();
-            portMEMORY_BARRIER();
+                xReturn = xEventGroupSync( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTicksToWait );
+                portMEMORY_BARRIER();
+
+                portRESET_PRIVILEGE();
+                portMEMORY_BARRIER();
+            }
+            else
+            {
+                xReturn = xEventGroupSync( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTicksToWait );
+            }
+
+            return xReturn;
         }
-        else
-        {
-            xReturn = xEventGroupWaitBits( xEventGroup, uxBitsToWaitFor, xClearOnExit, xWaitForAllBits, xTicksToWait );
-        }
-
-        return xReturn;
-    }
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                          const EventBits_t uxBitsToClear ) /* FREERTOS_SYSTEM_CALL */
-    {
-        EventBits_t xReturn;
-
-        if( portIS_PRIVILEGED() == pdFALSE )
+    #if ( configUSE_EVENT_GROUPS == 1 )
+        void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) /* FREERTOS_SYSTEM_CALL */
         {
-            portRAISE_PRIVILEGE();
-            portMEMORY_BARRIER();
+            if( portIS_PRIVILEGED() == pdFALSE )
+            {
+                portRAISE_PRIVILEGE();
+                portMEMORY_BARRIER();
 
-            xReturn = xEventGroupClearBits( xEventGroup, uxBitsToClear );
-            portMEMORY_BARRIER();
+                vEventGroupDelete( xEventGroup );
+                portMEMORY_BARRIER();
 
-            portRESET_PRIVILEGE();
-            portMEMORY_BARRIER();
+                portRESET_PRIVILEGE();
+                portMEMORY_BARRIER();
+            }
+            else
+            {
+                vEventGroupDelete( xEventGroup );
+            }
         }
-        else
-        {
-            xReturn = xEventGroupClearBits( xEventGroup, uxBitsToClear );
-        }
-
-        return xReturn;
-    }
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                        const EventBits_t uxBitsToSet ) /* FREERTOS_SYSTEM_CALL */
-    {
-        EventBits_t xReturn;
-
-        if( portIS_PRIVILEGED() == pdFALSE )
+    #if ( configUSE_STREAM_BUFFERS == 1 )
+        size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                      const void * pvTxData,
+                                      size_t xDataLengthBytes,
+                                      TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
         {
-            portRAISE_PRIVILEGE();
-            portMEMORY_BARRIER();
+            size_t xReturn;
 
-            xReturn = xEventGroupSetBits( xEventGroup, uxBitsToSet );
-            portMEMORY_BARRIER();
+            if( portIS_PRIVILEGED() == pdFALSE )
+            {
+                portRAISE_PRIVILEGE();
+                portMEMORY_BARRIER();
 
-            portRESET_PRIVILEGE();
-            portMEMORY_BARRIER();
+                xReturn = xStreamBufferSend( xStreamBuffer, pvTxData, xDataLengthBytes, xTicksToWait );
+                portMEMORY_BARRIER();
+
+                portRESET_PRIVILEGE();
+                portMEMORY_BARRIER();
+            }
+            else
+            {
+                xReturn = xStreamBufferSend( xStreamBuffer, pvTxData, xDataLengthBytes, xTicksToWait );
+            }
+
+            return xReturn;
         }
-        else
-        {
-            xReturn = xEventGroupSetBits( xEventGroup, uxBitsToSet );
-        }
-
-        return xReturn;
-    }
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                     const EventBits_t uxBitsToSet,
-                                     const EventBits_t uxBitsToWaitFor,
-                                     TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-    {
-        EventBits_t xReturn;
-
-        if( portIS_PRIVILEGED() == pdFALSE )
+    #if ( configUSE_STREAM_BUFFERS == 1 )
+        size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
         {
-            portRAISE_PRIVILEGE();
-            portMEMORY_BARRIER();
+            size_t xReturn;
 
-            xReturn = xEventGroupSync( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTicksToWait );
-            portMEMORY_BARRIER();
+            if( portIS_PRIVILEGED() == pdFALSE )
+            {
+                portRAISE_PRIVILEGE();
+                portMEMORY_BARRIER();
 
-            portRESET_PRIVILEGE();
-            portMEMORY_BARRIER();
+                xReturn = xStreamBufferNextMessageLengthBytes( xStreamBuffer );
+                portMEMORY_BARRIER();
+
+                portRESET_PRIVILEGE();
+                portMEMORY_BARRIER();
+            }
+            else
+            {
+                xReturn = xStreamBufferNextMessageLengthBytes( xStreamBuffer );
+            }
+
+            return xReturn;
         }
-        else
-        {
-            xReturn = xEventGroupSync( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTicksToWait );
-        }
-
-        return xReturn;
-    }
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) /* FREERTOS_SYSTEM_CALL */
-    {
-        if( portIS_PRIVILEGED() == pdFALSE )
+    #if ( configUSE_STREAM_BUFFERS == 1 )
+        size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                         void * pvRxData,
+                                         size_t xBufferLengthBytes,
+                                         TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
         {
-            portRAISE_PRIVILEGE();
-            portMEMORY_BARRIER();
+            size_t xReturn;
 
-            vEventGroupDelete( xEventGroup );
-            portMEMORY_BARRIER();
+            if( portIS_PRIVILEGED() == pdFALSE )
+            {
+                portRAISE_PRIVILEGE();
+                portMEMORY_BARRIER();
 
-            portRESET_PRIVILEGE();
-            portMEMORY_BARRIER();
+                xReturn = xStreamBufferReceive( xStreamBuffer, pvRxData, xBufferLengthBytes, xTicksToWait );
+                portMEMORY_BARRIER();
+
+                portRESET_PRIVILEGE();
+                portMEMORY_BARRIER();
+            }
+            else
+            {
+                xReturn = xStreamBufferReceive( xStreamBuffer, pvRxData, xBufferLengthBytes, xTicksToWait );
+            }
+
+            return xReturn;
         }
-        else
-        {
-            vEventGroupDelete( xEventGroup );
-        }
-    }
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                                  const void * pvTxData,
-                                  size_t xDataLengthBytes,
-                                  TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-    {
-        size_t xReturn;
-
-        if( portIS_PRIVILEGED() == pdFALSE )
+    #if ( configUSE_STREAM_BUFFERS == 1 )
+        void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
         {
-            portRAISE_PRIVILEGE();
-            portMEMORY_BARRIER();
+            if( portIS_PRIVILEGED() == pdFALSE )
+            {
+                portRAISE_PRIVILEGE();
+                portMEMORY_BARRIER();
 
-            xReturn = xStreamBufferSend( xStreamBuffer, pvTxData, xDataLengthBytes, xTicksToWait );
-            portMEMORY_BARRIER();
+                vStreamBufferDelete( xStreamBuffer );
+                portMEMORY_BARRIER();
 
-            portRESET_PRIVILEGE();
-            portMEMORY_BARRIER();
+                portRESET_PRIVILEGE();
+                portMEMORY_BARRIER();
+            }
+            else
+            {
+                vStreamBufferDelete( xStreamBuffer );
+            }
         }
-        else
-        {
-            xReturn = xStreamBufferSend( xStreamBuffer, pvTxData, xDataLengthBytes, xTicksToWait );
-        }
-
-        return xReturn;
-    }
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
-    {
-        size_t xReturn;
-
-        if( portIS_PRIVILEGED() == pdFALSE )
+    #if ( configUSE_STREAM_BUFFERS == 1 )
+        BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
         {
-            portRAISE_PRIVILEGE();
-            portMEMORY_BARRIER();
+            BaseType_t xReturn;
 
-            xReturn = xStreamBufferNextMessageLengthBytes( xStreamBuffer );
-            portMEMORY_BARRIER();
+            if( portIS_PRIVILEGED() == pdFALSE )
+            {
+                portRAISE_PRIVILEGE();
+                portMEMORY_BARRIER();
 
-            portRESET_PRIVILEGE();
-            portMEMORY_BARRIER();
+                xReturn = xStreamBufferIsFull( xStreamBuffer );
+                portMEMORY_BARRIER();
+
+                portRESET_PRIVILEGE();
+                portMEMORY_BARRIER();
+            }
+            else
+            {
+                xReturn = xStreamBufferIsFull( xStreamBuffer );
+            }
+
+            return xReturn;
         }
-        else
-        {
-            xReturn = xStreamBufferNextMessageLengthBytes( xStreamBuffer );
-        }
-
-        return xReturn;
-    }
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                     void * pvRxData,
-                                     size_t xBufferLengthBytes,
-                                     TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-    {
-        size_t xReturn;
-
-        if( portIS_PRIVILEGED() == pdFALSE )
+    #if ( configUSE_STREAM_BUFFERS == 1 )
+        BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
         {
-            portRAISE_PRIVILEGE();
-            portMEMORY_BARRIER();
+            BaseType_t xReturn;
 
-            xReturn = xStreamBufferReceive( xStreamBuffer, pvRxData, xBufferLengthBytes, xTicksToWait );
-            portMEMORY_BARRIER();
+            if( portIS_PRIVILEGED() == pdFALSE )
+            {
+                portRAISE_PRIVILEGE();
+                portMEMORY_BARRIER();
 
-            portRESET_PRIVILEGE();
-            portMEMORY_BARRIER();
+                xReturn = xStreamBufferIsEmpty( xStreamBuffer );
+                portMEMORY_BARRIER();
+
+                portRESET_PRIVILEGE();
+                portMEMORY_BARRIER();
+            }
+            else
+            {
+                xReturn = xStreamBufferIsEmpty( xStreamBuffer );
+            }
+
+            return xReturn;
         }
-        else
-        {
-            xReturn = xStreamBufferReceive( xStreamBuffer, pvRxData, xBufferLengthBytes, xTicksToWait );
-        }
-
-        return xReturn;
-    }
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
-    {
-        if( portIS_PRIVILEGED() == pdFALSE )
+    #if ( configUSE_STREAM_BUFFERS == 1 )
+        BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
         {
-            portRAISE_PRIVILEGE();
-            portMEMORY_BARRIER();
+            BaseType_t xReturn;
 
-            vStreamBufferDelete( xStreamBuffer );
-            portMEMORY_BARRIER();
+            if( portIS_PRIVILEGED() == pdFALSE )
+            {
+                portRAISE_PRIVILEGE();
+                portMEMORY_BARRIER();
 
-            portRESET_PRIVILEGE();
-            portMEMORY_BARRIER();
+                xReturn = xStreamBufferReset( xStreamBuffer );
+                portMEMORY_BARRIER();
+
+                portRESET_PRIVILEGE();
+                portMEMORY_BARRIER();
+            }
+            else
+            {
+                xReturn = xStreamBufferReset( xStreamBuffer );
+            }
+
+            return xReturn;
         }
-        else
-        {
-            vStreamBufferDelete( xStreamBuffer );
-        }
-    }
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
-    {
-        BaseType_t xReturn;
-
-        if( portIS_PRIVILEGED() == pdFALSE )
+    #if ( configUSE_STREAM_BUFFERS == 1 )
+        size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
         {
-            portRAISE_PRIVILEGE();
-            portMEMORY_BARRIER();
+            size_t xReturn;
 
-            xReturn = xStreamBufferIsFull( xStreamBuffer );
-            portMEMORY_BARRIER();
+            if( portIS_PRIVILEGED() == pdFALSE )
+            {
+                portRAISE_PRIVILEGE();
+                portMEMORY_BARRIER();
+                xReturn = xStreamBufferSpacesAvailable( xStreamBuffer );
+                portMEMORY_BARRIER();
 
-            portRESET_PRIVILEGE();
-            portMEMORY_BARRIER();
+                portRESET_PRIVILEGE();
+                portMEMORY_BARRIER();
+            }
+            else
+            {
+                xReturn = xStreamBufferSpacesAvailable( xStreamBuffer );
+            }
+
+            return xReturn;
         }
-        else
-        {
-            xReturn = xStreamBufferIsFull( xStreamBuffer );
-        }
-
-        return xReturn;
-    }
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
-    {
-        BaseType_t xReturn;
-
-        if( portIS_PRIVILEGED() == pdFALSE )
+    #if ( configUSE_STREAM_BUFFERS == 1 )
+        size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
         {
-            portRAISE_PRIVILEGE();
-            portMEMORY_BARRIER();
+            size_t xReturn;
 
-            xReturn = xStreamBufferIsEmpty( xStreamBuffer );
-            portMEMORY_BARRIER();
+            if( portIS_PRIVILEGED() == pdFALSE )
+            {
+                portRAISE_PRIVILEGE();
+                portMEMORY_BARRIER();
 
-            portRESET_PRIVILEGE();
-            portMEMORY_BARRIER();
+                xReturn = xStreamBufferBytesAvailable( xStreamBuffer );
+                portMEMORY_BARRIER();
+
+                portRESET_PRIVILEGE();
+                portMEMORY_BARRIER();
+            }
+            else
+            {
+                xReturn = xStreamBufferBytesAvailable( xStreamBuffer );
+            }
+
+            return xReturn;
         }
-        else
-        {
-            xReturn = xStreamBufferIsEmpty( xStreamBuffer );
-        }
-
-        return xReturn;
-    }
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
-    {
-        BaseType_t xReturn;
-
-        if( portIS_PRIVILEGED() == pdFALSE )
+    #if ( configUSE_STREAM_BUFFERS == 1 )
+        BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                     size_t xTriggerLevel ) /* FREERTOS_SYSTEM_CALL */
         {
-            portRAISE_PRIVILEGE();
-            portMEMORY_BARRIER();
+            BaseType_t xReturn;
 
-            xReturn = xStreamBufferReset( xStreamBuffer );
-            portMEMORY_BARRIER();
+            if( portIS_PRIVILEGED() == pdFALSE )
+            {
+                portRAISE_PRIVILEGE();
+                portMEMORY_BARRIER();
 
-            portRESET_PRIVILEGE();
-            portMEMORY_BARRIER();
+                xReturn = xStreamBufferSetTriggerLevel( xStreamBuffer, xTriggerLevel );
+                portMEMORY_BARRIER();
+
+                portRESET_PRIVILEGE();
+                portMEMORY_BARRIER();
+            }
+            else
+            {
+                xReturn = xStreamBufferSetTriggerLevel( xStreamBuffer, xTriggerLevel );
+            }
+
+            return xReturn;
         }
-        else
-        {
-            xReturn = xStreamBufferReset( xStreamBuffer );
-        }
-
-        return xReturn;
-    }
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
-    {
-        size_t xReturn;
-
-        if( portIS_PRIVILEGED() == pdFALSE )
-        {
-            portRAISE_PRIVILEGE();
-            portMEMORY_BARRIER();
-            xReturn = xStreamBufferSpacesAvailable( xStreamBuffer );
-            portMEMORY_BARRIER();
-
-            portRESET_PRIVILEGE();
-            portMEMORY_BARRIER();
-        }
-        else
-        {
-            xReturn = xStreamBufferSpacesAvailable( xStreamBuffer );
-        }
-
-        return xReturn;
-    }
-/*-----------------------------------------------------------*/
-
-    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
-    {
-        size_t xReturn;
-
-        if( portIS_PRIVILEGED() == pdFALSE )
-        {
-            portRAISE_PRIVILEGE();
-            portMEMORY_BARRIER();
-
-            xReturn = xStreamBufferBytesAvailable( xStreamBuffer );
-            portMEMORY_BARRIER();
-
-            portRESET_PRIVILEGE();
-            portMEMORY_BARRIER();
-        }
-        else
-        {
-            xReturn = xStreamBufferBytesAvailable( xStreamBuffer );
-        }
-
-        return xReturn;
-    }
-/*-----------------------------------------------------------*/
-
-    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                                 size_t xTriggerLevel ) /* FREERTOS_SYSTEM_CALL */
-    {
-        BaseType_t xReturn;
-
-        if( portIS_PRIVILEGED() == pdFALSE )
-        {
-            portRAISE_PRIVILEGE();
-            portMEMORY_BARRIER();
-
-            xReturn = xStreamBufferSetTriggerLevel( xStreamBuffer, xTriggerLevel );
-            portMEMORY_BARRIER();
-
-            portRESET_PRIVILEGE();
-            portMEMORY_BARRIER();
-        }
-        else
-        {
-            xReturn = xStreamBufferSetTriggerLevel( xStreamBuffer, xTriggerLevel );
-        }
-
-        return xReturn;
-    }
-/*-----------------------------------------------------------*/
-
-    #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+    #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_STREAM_BUFFERS == 1 ) )
         StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes,
                                                              size_t xTriggerLevelBytes,
                                                              BaseType_t xIsMessageBuffer,
@@ -2422,10 +2452,10 @@
 
             return xReturn;
         }
-    #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+    #endif /* #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_STREAM_BUFFERS == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-    #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+    #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_STREAM_BUFFERS == 1 ) )
         StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
                                                                    size_t xTriggerLevelBytes,
                                                                    BaseType_t xIsMessageBuffer,
@@ -2482,7 +2512,7 @@
 
             return xReturn;
         }
-    #endif /* configSUPPORT_STATIC_ALLOCATION */
+    #endif /* #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_STREAM_BUFFERS == 1 ) ) */
 /*-----------------------------------------------------------*/
 
 
diff --git a/portable/Common/mpu_wrappers_v2.c b/portable/Common/mpu_wrappers_v2.c
index 99256e3fa..a7ab6669a 100644
--- a/portable/Common/mpu_wrappers_v2.c
+++ b/portable/Common/mpu_wrappers_v2.c
@@ -215,22 +215,27 @@
     #define MPU_GetTaskHandleAtIndex( lIndex )                       ( TaskHandle_t ) MPU_GetHandleAtIndex( ( lIndex ), KERNEL_OBJECT_TYPE_TASK )
     #define MPU_GetIndexForTaskHandle( xHandle )                     MPU_GetIndexForHandle( ( OpaqueObjectHandle_t ) ( xHandle ), KERNEL_OBJECT_TYPE_TASK )
 
+    #if ( configUSE_EVENT_GROUPS == 1 )
 /*
  * Wrappers to keep all the casting in one place for Event Group APIs.
  */
-    #define MPU_StoreEventGroupHandleAtIndex( lIndex, xHandle )      MPU_StoreHandleAndDataAtIndex( ( lIndex ), ( OpaqueObjectHandle_t ) ( xHandle ), NULL, KERNEL_OBJECT_TYPE_EVENT_GROUP )
-    #define MPU_GetEventGroupHandleAtIndex( lIndex )                 ( EventGroupHandle_t ) MPU_GetHandleAtIndex( ( lIndex ), KERNEL_OBJECT_TYPE_EVENT_GROUP )
-    #define MPU_GetIndexForEventGroupHandle( xHandle )               MPU_GetIndexForHandle( ( OpaqueObjectHandle_t ) ( xHandle ), KERNEL_OBJECT_TYPE_EVENT_GROUP )
+        #define MPU_StoreEventGroupHandleAtIndex( lIndex, xHandle )      MPU_StoreHandleAndDataAtIndex( ( lIndex ), ( OpaqueObjectHandle_t ) ( xHandle ), NULL, KERNEL_OBJECT_TYPE_EVENT_GROUP )
+        #define MPU_GetEventGroupHandleAtIndex( lIndex )                 ( EventGroupHandle_t ) MPU_GetHandleAtIndex( ( lIndex ), KERNEL_OBJECT_TYPE_EVENT_GROUP )
+        #define MPU_GetIndexForEventGroupHandle( xHandle )               MPU_GetIndexForHandle( ( OpaqueObjectHandle_t ) ( xHandle ), KERNEL_OBJECT_TYPE_EVENT_GROUP )
 
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
+
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 /*
  * Wrappers to keep all the casting in one place for Stream Buffer APIs.
  */
-    #define MPU_StoreStreamBufferHandleAtIndex( lIndex, xHandle )    MPU_StoreHandleAndDataAtIndex( ( lIndex ), ( OpaqueObjectHandle_t ) ( xHandle), NULL, KERNEL_OBJECT_TYPE_STREAM_BUFFER )
-    #define MPU_GetStreamBufferHandleAtIndex( lIndex )               ( StreamBufferHandle_t ) MPU_GetHandleAtIndex( ( lIndex ), KERNEL_OBJECT_TYPE_STREAM_BUFFER )
-    #define MPU_GetIndexForStreamBufferHandle( xHandle )             MPU_GetIndexForHandle( ( OpaqueObjectHandle_t ) ( xHandle ), KERNEL_OBJECT_TYPE_STREAM_BUFFER )
+        #define MPU_StoreStreamBufferHandleAtIndex( lIndex, xHandle )    MPU_StoreHandleAndDataAtIndex( ( lIndex ), ( OpaqueObjectHandle_t ) ( xHandle), NULL, KERNEL_OBJECT_TYPE_STREAM_BUFFER )
+        #define MPU_GetStreamBufferHandleAtIndex( lIndex )               ( StreamBufferHandle_t ) MPU_GetHandleAtIndex( ( lIndex ), KERNEL_OBJECT_TYPE_STREAM_BUFFER )
+        #define MPU_GetIndexForStreamBufferHandle( xHandle )             MPU_GetIndexForHandle( ( OpaqueObjectHandle_t ) ( xHandle ), KERNEL_OBJECT_TYPE_STREAM_BUFFER )
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 
     #if ( configUSE_TIMERS == 1 )
-
 /*
  * Wrappers to keep all the casting in one place for Timer APIs.
  */
@@ -3867,53 +3872,99 @@
 /*           MPU wrappers for event group APIs.              */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
-                                         const EventBits_t uxBitsToWaitFor,
-                                         const BaseType_t xClearOnExit,
-                                         const BaseType_t xWaitForAllBits,
-                                         TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-    {
-        EventBits_t xReturn = 0;
-        xEventGroupWaitBitsParams_t xParams;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-        xParams.xEventGroup = xEventGroup;
-        xParams.uxBitsToWaitFor = uxBitsToWaitFor;
-        xParams.xClearOnExit = xClearOnExit;
-        xParams.xWaitForAllBits = xWaitForAllBits;
-        xParams.xTicksToWait = xTicksToWait;
-
-        xReturn = MPU_xEventGroupWaitBitsEntry( &( xParams ) );
-
-        return xReturn;
-    }
-
-    EventBits_t MPU_xEventGroupWaitBitsImpl( const xEventGroupWaitBitsParams_t * pxParams ) PRIVILEGED_FUNCTION;
-
-    EventBits_t MPU_xEventGroupWaitBitsImpl( const xEventGroupWaitBitsParams_t * pxParams ) /* PRIVILEGED_FUNCTION */
-    {
-        EventBits_t xReturn = 0;
-        EventGroupHandle_t xInternalEventGroupHandle = NULL;
-        int32_t lIndex;
-        BaseType_t xCallingTaskIsAuthorizedToAccessEventGroup = pdFALSE;
-        BaseType_t xAreParamsReadable = pdFALSE;
-
-        if( pxParams != NULL )
+        EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+                                             const EventBits_t uxBitsToWaitFor,
+                                             const BaseType_t xClearOnExit,
+                                             const BaseType_t xWaitForAllBits,
+                                             TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
         {
-            xAreParamsReadable = xPortIsAuthorizedToAccessBuffer( pxParams,
-                                                                  sizeof( xEventGroupWaitBitsParams_t ),
-                                                                  tskMPU_READ_PERMISSION );
+            EventBits_t xReturn = 0;
+            xEventGroupWaitBitsParams_t xParams;
+
+            xParams.xEventGroup = xEventGroup;
+            xParams.uxBitsToWaitFor = uxBitsToWaitFor;
+            xParams.xClearOnExit = xClearOnExit;
+            xParams.xWaitForAllBits = xWaitForAllBits;
+            xParams.xTicksToWait = xTicksToWait;
+
+            xReturn = MPU_xEventGroupWaitBitsEntry( &( xParams ) );
+
+            return xReturn;
         }
 
-        if( xAreParamsReadable == pdTRUE )
+        EventBits_t MPU_xEventGroupWaitBitsImpl( const xEventGroupWaitBitsParams_t * pxParams ) PRIVILEGED_FUNCTION;
+
+        EventBits_t MPU_xEventGroupWaitBitsImpl( const xEventGroupWaitBitsParams_t * pxParams ) /* PRIVILEGED_FUNCTION */
         {
-            if( ( ( pxParams->uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0U ) &&
-                ( pxParams->uxBitsToWaitFor != 0U )
-                #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
-                    && ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( pxParams->xTicksToWait != 0U ) ) )
-                #endif
-                )
+            EventBits_t xReturn = 0;
+            EventGroupHandle_t xInternalEventGroupHandle = NULL;
+            int32_t lIndex;
+            BaseType_t xCallingTaskIsAuthorizedToAccessEventGroup = pdFALSE;
+            BaseType_t xAreParamsReadable = pdFALSE;
+
+            if( pxParams != NULL )
             {
-                lIndex = ( int32_t ) ( pxParams->xEventGroup );
+                xAreParamsReadable = xPortIsAuthorizedToAccessBuffer( pxParams,
+                                                                      sizeof( xEventGroupWaitBitsParams_t ),
+                                                                      tskMPU_READ_PERMISSION );
+            }
+
+            if( xAreParamsReadable == pdTRUE )
+            {
+                if( ( ( pxParams->uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0U ) &&
+                    ( pxParams->uxBitsToWaitFor != 0U )
+                    #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+                        && ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( pxParams->xTicksToWait != 0U ) ) )
+                    #endif
+                    )
+                {
+                    lIndex = ( int32_t ) ( pxParams->xEventGroup );
+
+                    if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+                    {
+                        xCallingTaskIsAuthorizedToAccessEventGroup = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                        if( xCallingTaskIsAuthorizedToAccessEventGroup == pdTRUE )
+                        {
+                            xInternalEventGroupHandle = MPU_GetEventGroupHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                            if( xInternalEventGroupHandle != NULL )
+                            {
+                                xReturn = xEventGroupWaitBits( xInternalEventGroupHandle,
+                                                               pxParams->uxBitsToWaitFor,
+                                                               pxParams->xClearOnExit,
+                                                               pxParams->xWaitForAllBits,
+                                                               pxParams->xTicksToWait );
+                            }
+                        }
+                    }
+                }
+            }
+
+            return xReturn;
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_EVENT_GROUPS == 1 )
+
+        EventBits_t MPU_xEventGroupClearBitsImpl( EventGroupHandle_t xEventGroup,
+                                                  const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION;
+
+        EventBits_t MPU_xEventGroupClearBitsImpl( EventGroupHandle_t xEventGroup,
+                                                  const EventBits_t uxBitsToClear ) /* PRIVILEGED_FUNCTION */
+        {
+            EventBits_t xReturn = 0;
+            EventGroupHandle_t xInternalEventGroupHandle = NULL;
+            int32_t lIndex;
+            BaseType_t xCallingTaskIsAuthorizedToAccessEventGroup = pdFALSE;
+
+            if( ( uxBitsToClear & eventEVENT_BITS_CONTROL_BYTES ) == 0U )
+            {
+                lIndex = ( int32_t ) xEventGroup;
 
                 if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
                 {
@@ -3925,136 +3976,106 @@
 
                         if( xInternalEventGroupHandle != NULL )
                         {
-                            xReturn = xEventGroupWaitBits( xInternalEventGroupHandle,
-                                                           pxParams->uxBitsToWaitFor,
-                                                           pxParams->xClearOnExit,
-                                                           pxParams->xWaitForAllBits,
-                                                           pxParams->xTicksToWait );
+                            xReturn = xEventGroupClearBits( xInternalEventGroupHandle, uxBitsToClear );
                         }
                     }
                 }
             }
+
+            return xReturn;
         }
 
-        return xReturn;
-    }
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupClearBitsImpl( EventGroupHandle_t xEventGroup,
-                                              const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-    EventBits_t MPU_xEventGroupClearBitsImpl( EventGroupHandle_t xEventGroup,
-                                              const EventBits_t uxBitsToClear ) /* PRIVILEGED_FUNCTION */
-    {
-        EventBits_t xReturn = 0;
-        EventGroupHandle_t xInternalEventGroupHandle = NULL;
-        int32_t lIndex;
-        BaseType_t xCallingTaskIsAuthorizedToAccessEventGroup = pdFALSE;
+        EventBits_t MPU_xEventGroupSetBitsImpl( EventGroupHandle_t xEventGroup,
+                                                const EventBits_t uxBitsToSet ) PRIVILEGED_FUNCTION;
 
-        if( ( uxBitsToClear & eventEVENT_BITS_CONTROL_BYTES ) == 0U )
+        EventBits_t MPU_xEventGroupSetBitsImpl( EventGroupHandle_t xEventGroup,
+                                                const EventBits_t uxBitsToSet ) /* PRIVILEGED_FUNCTION */
         {
-            lIndex = ( int32_t ) xEventGroup;
+            EventBits_t xReturn = 0;
+            EventGroupHandle_t xInternalEventGroupHandle = NULL;
+            int32_t lIndex;
+            BaseType_t xCallingTaskIsAuthorizedToAccessEventGroup = pdFALSE;
 
-            if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+            if( ( uxBitsToSet & eventEVENT_BITS_CONTROL_BYTES ) == 0U )
             {
-                xCallingTaskIsAuthorizedToAccessEventGroup = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                lIndex = ( int32_t ) xEventGroup;
 
-                if( xCallingTaskIsAuthorizedToAccessEventGroup == pdTRUE )
+                if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
                 {
-                    xInternalEventGroupHandle = MPU_GetEventGroupHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                    xCallingTaskIsAuthorizedToAccessEventGroup = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-                    if( xInternalEventGroupHandle != NULL )
+                    if( xCallingTaskIsAuthorizedToAccessEventGroup == pdTRUE )
                     {
-                        xReturn = xEventGroupClearBits( xInternalEventGroupHandle, uxBitsToClear );
+                        xInternalEventGroupHandle = MPU_GetEventGroupHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                        if( xInternalEventGroupHandle != NULL )
+                        {
+                            xReturn = xEventGroupSetBits( xInternalEventGroupHandle, uxBitsToSet );
+                        }
                     }
                 }
             }
+
+            return xReturn;
         }
 
-        return xReturn;
-    }
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupSetBitsImpl( EventGroupHandle_t xEventGroup,
-                                            const EventBits_t uxBitsToSet ) PRIVILEGED_FUNCTION;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-    EventBits_t MPU_xEventGroupSetBitsImpl( EventGroupHandle_t xEventGroup,
-                                            const EventBits_t uxBitsToSet ) /* PRIVILEGED_FUNCTION */
-    {
-        EventBits_t xReturn = 0;
-        EventGroupHandle_t xInternalEventGroupHandle = NULL;
-        int32_t lIndex;
-        BaseType_t xCallingTaskIsAuthorizedToAccessEventGroup = pdFALSE;
+        EventBits_t MPU_xEventGroupSyncImpl( EventGroupHandle_t xEventGroup,
+                                             const EventBits_t uxBitsToSet,
+                                             const EventBits_t uxBitsToWaitFor,
+                                             TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
 
-        if( ( uxBitsToSet & eventEVENT_BITS_CONTROL_BYTES ) == 0U )
+        EventBits_t MPU_xEventGroupSyncImpl( EventGroupHandle_t xEventGroup,
+                                             const EventBits_t uxBitsToSet,
+                                             const EventBits_t uxBitsToWaitFor,
+                                             TickType_t xTicksToWait ) /* PRIVILEGED_FUNCTION */
         {
-            lIndex = ( int32_t ) xEventGroup;
+            EventBits_t xReturn = 0;
+            EventGroupHandle_t xInternalEventGroupHandle = NULL;
+            int32_t lIndex;
+            BaseType_t xCallingTaskIsAuthorizedToAccessEventGroup = pdFALSE;
 
-            if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+            if( ( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0U ) &&
+                ( uxBitsToWaitFor != 0U )
+                #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+                    && ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0U ) ) )
+                #endif
+                )
             {
-                xCallingTaskIsAuthorizedToAccessEventGroup = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                lIndex = ( int32_t ) xEventGroup;
 
-                if( xCallingTaskIsAuthorizedToAccessEventGroup == pdTRUE )
+                if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
                 {
-                    xInternalEventGroupHandle = MPU_GetEventGroupHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                    xCallingTaskIsAuthorizedToAccessEventGroup = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-                    if( xInternalEventGroupHandle != NULL )
+                    if( xCallingTaskIsAuthorizedToAccessEventGroup == pdTRUE )
                     {
-                        xReturn = xEventGroupSetBits( xInternalEventGroupHandle, uxBitsToSet );
+                        xInternalEventGroupHandle = MPU_GetEventGroupHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                        if( xInternalEventGroupHandle != NULL )
+                        {
+                            xReturn = xEventGroupSync( xInternalEventGroupHandle, uxBitsToSet, uxBitsToWaitFor, xTicksToWait );
+                        }
                     }
                 }
             }
+
+            return xReturn;
         }
 
-        return xReturn;
-    }
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupSyncImpl( EventGroupHandle_t xEventGroup,
-                                         const EventBits_t uxBitsToSet,
-                                         const EventBits_t uxBitsToWaitFor,
-                                         TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
-
-    EventBits_t MPU_xEventGroupSyncImpl( EventGroupHandle_t xEventGroup,
-                                         const EventBits_t uxBitsToSet,
-                                         const EventBits_t uxBitsToWaitFor,
-                                         TickType_t xTicksToWait ) /* PRIVILEGED_FUNCTION */
-    {
-        EventBits_t xReturn = 0;
-        EventGroupHandle_t xInternalEventGroupHandle = NULL;
-        int32_t lIndex;
-        BaseType_t xCallingTaskIsAuthorizedToAccessEventGroup = pdFALSE;
-
-        if( ( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0U ) &&
-            ( uxBitsToWaitFor != 0U )
-            #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
-                && ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0U ) ) )
-            #endif
-            )
-        {
-            lIndex = ( int32_t ) xEventGroup;
-
-            if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
-            {
-                xCallingTaskIsAuthorizedToAccessEventGroup = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
-
-                if( xCallingTaskIsAuthorizedToAccessEventGroup == pdTRUE )
-                {
-                    xInternalEventGroupHandle = MPU_GetEventGroupHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
-
-                    if( xInternalEventGroupHandle != NULL )
-                    {
-                        xReturn = xEventGroupSync( xInternalEventGroupHandle, uxBitsToSet, uxBitsToWaitFor, xTicksToWait );
-                    }
-                }
-            }
-        }
-
-        return xReturn;
-    }
-/*-----------------------------------------------------------*/
-
-    #if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
 
         UBaseType_t MPU_uxEventGroupGetNumberImpl( void * xEventGroup ) PRIVILEGED_FUNCTION;
 
@@ -4085,10 +4106,10 @@
             return xReturn;
         }
 
-    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-    #if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
 
         void MPU_vEventGroupSetNumberImpl( void * xEventGroup,
                                            UBaseType_t uxEventGroupNumber ) PRIVILEGED_FUNCTION;
@@ -4118,7 +4139,7 @@
             }
         }
 
-    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
 /*-----------------------------------------------------------*/
 
 /* Privileged only wrappers for Event Group APIs. These are needed so that
@@ -4126,7 +4147,7 @@
  * with all the APIs. */
 /*-----------------------------------------------------------*/
 
-    #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+    #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_EVENT_GROUPS == 1 ) )
 
         EventGroupHandle_t MPU_xEventGroupCreate( void ) /* PRIVILEGED_FUNCTION */
         {
@@ -4154,10 +4175,10 @@
             return xExternalEventGroupHandle;
         }
 
-    #endif /* if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) */
+    #endif /* #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_EVENT_GROUPS == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-    #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+    #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_EVENT_GROUPS == 1 ) )
 
         EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t * pxEventGroupBuffer ) /* PRIVILEGED_FUNCTION */
         {
@@ -4185,30 +4206,34 @@
             return xExternalEventGroupHandle;
         }
 
-    #endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+    #endif /* #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_EVENT_GROUPS == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-    void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) /* PRIVILEGED_FUNCTION */
-    {
-        EventGroupHandle_t xInternalEventGroupHandle = NULL;
-        int32_t lIndex;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-        lIndex = ( int32_t ) xEventGroup;
-
-        if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+        void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) /* PRIVILEGED_FUNCTION */
         {
-            xInternalEventGroupHandle = MPU_GetEventGroupHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+            EventGroupHandle_t xInternalEventGroupHandle = NULL;
+            int32_t lIndex;
 
-            if( xInternalEventGroupHandle != NULL )
+            lIndex = ( int32_t ) xEventGroup;
+
+            if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
             {
-                vEventGroupDelete( xInternalEventGroupHandle );
-                MPU_SetIndexFreeInKernelObjectPool( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                xInternalEventGroupHandle = MPU_GetEventGroupHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                if( xInternalEventGroupHandle != NULL )
+                {
+                    vEventGroupDelete( xInternalEventGroupHandle );
+                    MPU_SetIndexFreeInKernelObjectPool( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                }
             }
         }
-    }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+    #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_EVENT_GROUPS == 1 ) )
 
         BaseType_t MPU_xEventGroupGetStaticBuffer( EventGroupHandle_t xEventGroup,
                                                    StaticEventGroup_t ** ppxEventGroupBuffer ) /* PRIVILEGED_FUNCTION */
@@ -4232,10 +4257,10 @@
             return xReturn;
         }
 
-    #endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+    #endif /* #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_EVENT_GROUPS == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-    #if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
+    #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
 
         BaseType_t MPU_xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup,
                                                     const EventBits_t uxBitsToClear ) /* PRIVILEGED_FUNCTION */
@@ -4259,10 +4284,10 @@
             return xReturn;
         }
 
-    #endif /* #if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) */
+    #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-    #if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
+    #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
 
         BaseType_t MPU_xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup,
                                                   const EventBits_t uxBitsToSet,
@@ -4287,309 +4312,345 @@
             return xReturn;
         }
 
-    #endif /* #if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) */
+    #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ) /* PRIVILEGED_FUNCTION */
-    {
-        EventBits_t xReturn = 0;
-        EventGroupHandle_t xInternalEventGroupHandle = NULL;
-        int32_t lIndex;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-        lIndex = ( int32_t ) xEventGroup;
-
-        if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+        EventBits_t MPU_xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ) /* PRIVILEGED_FUNCTION */
         {
-            xInternalEventGroupHandle = MPU_GetEventGroupHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+            EventBits_t xReturn = 0;
+            EventGroupHandle_t xInternalEventGroupHandle = NULL;
+            int32_t lIndex;
 
-            if( xInternalEventGroupHandle != NULL )
+            lIndex = ( int32_t ) xEventGroup;
+
+            if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
             {
-                xReturn = xEventGroupGetBitsFromISR( xInternalEventGroupHandle );
+                xInternalEventGroupHandle = MPU_GetEventGroupHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                if( xInternalEventGroupHandle != NULL )
+                {
+                    xReturn = xEventGroupGetBitsFromISR( xInternalEventGroupHandle );
+                }
             }
+
+            return xReturn;
         }
 
-        return xReturn;
-    }
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
 /*-----------------------------------------------------------*/
 /*           MPU wrappers for stream buffer APIs.            */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferSendImpl( StreamBufferHandle_t xStreamBuffer,
-                                      const void * pvTxData,
-                                      size_t xDataLengthBytes,
-                                      TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferSendImpl( StreamBufferHandle_t xStreamBuffer,
-                                      const void * pvTxData,
-                                      size_t xDataLengthBytes,
-                                      TickType_t xTicksToWait ) /* PRIVILEGED_FUNCTION */
-    {
-        size_t xReturn = 0;
-        StreamBufferHandle_t xInternalStreamBufferHandle = NULL;
-        int32_t lIndex;
-        BaseType_t xIsTxDataBufferReadable = pdFALSE;
-        BaseType_t xCallingTaskIsAuthorizedToAccessStreamBuffer = pdFALSE;
+        size_t MPU_xStreamBufferSendImpl( StreamBufferHandle_t xStreamBuffer,
+                                          const void * pvTxData,
+                                          size_t xDataLengthBytes,
+                                          TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
 
-        if( pvTxData != NULL )
+        size_t MPU_xStreamBufferSendImpl( StreamBufferHandle_t xStreamBuffer,
+                                          const void * pvTxData,
+                                          size_t xDataLengthBytes,
+                                          TickType_t xTicksToWait ) /* PRIVILEGED_FUNCTION */
         {
-            xIsTxDataBufferReadable = xPortIsAuthorizedToAccessBuffer( pvTxData,
-                                                                       xDataLengthBytes,
-                                                                       tskMPU_READ_PERMISSION );
+            size_t xReturn = 0;
+            StreamBufferHandle_t xInternalStreamBufferHandle = NULL;
+            int32_t lIndex;
+            BaseType_t xIsTxDataBufferReadable = pdFALSE;
+            BaseType_t xCallingTaskIsAuthorizedToAccessStreamBuffer = pdFALSE;
 
-            if( xIsTxDataBufferReadable == pdTRUE )
+            if( pvTxData != NULL )
             {
-                lIndex = ( int32_t ) xStreamBuffer;
+                xIsTxDataBufferReadable = xPortIsAuthorizedToAccessBuffer( pvTxData,
+                                                                           xDataLengthBytes,
+                                                                           tskMPU_READ_PERMISSION );
 
-                if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+                if( xIsTxDataBufferReadable == pdTRUE )
                 {
-                    xCallingTaskIsAuthorizedToAccessStreamBuffer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                    lIndex = ( int32_t ) xStreamBuffer;
 
-                    if( xCallingTaskIsAuthorizedToAccessStreamBuffer == pdTRUE )
+                    if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
                     {
-                        xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                        xCallingTaskIsAuthorizedToAccessStreamBuffer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-                        if( xInternalStreamBufferHandle != NULL )
+                        if( xCallingTaskIsAuthorizedToAccessStreamBuffer == pdTRUE )
                         {
-                            xReturn = xStreamBufferSend( xInternalStreamBufferHandle, pvTxData, xDataLengthBytes, xTicksToWait );
+                            xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                            if( xInternalStreamBufferHandle != NULL )
+                            {
+                                xReturn = xStreamBufferSend( xInternalStreamBufferHandle, pvTxData, xDataLengthBytes, xTicksToWait );
+                            }
                         }
                     }
                 }
             }
+
+            return xReturn;
         }
 
-        return xReturn;
-    }
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferReceiveImpl( StreamBufferHandle_t xStreamBuffer,
-                                         void * pvRxData,
-                                         size_t xBufferLengthBytes,
-                                         TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferReceiveImpl( StreamBufferHandle_t xStreamBuffer,
-                                         void * pvRxData,
-                                         size_t xBufferLengthBytes,
-                                         TickType_t xTicksToWait ) /* PRIVILEGED_FUNCTION */
-    {
-        size_t xReturn = 0;
-        StreamBufferHandle_t xInternalStreamBufferHandle = NULL;
-        int32_t lIndex;
-        BaseType_t xIsRxDataBufferWriteable = pdFALSE;
-        BaseType_t xCallingTaskIsAuthorizedToAccessStreamBuffer = pdFALSE;
+        size_t MPU_xStreamBufferReceiveImpl( StreamBufferHandle_t xStreamBuffer,
+                                             void * pvRxData,
+                                             size_t xBufferLengthBytes,
+                                             TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
 
-        if( pvRxData != NULL )
+        size_t MPU_xStreamBufferReceiveImpl( StreamBufferHandle_t xStreamBuffer,
+                                             void * pvRxData,
+                                             size_t xBufferLengthBytes,
+                                             TickType_t xTicksToWait ) /* PRIVILEGED_FUNCTION */
         {
-            xIsRxDataBufferWriteable = xPortIsAuthorizedToAccessBuffer( pvRxData,
-                                                                        xBufferLengthBytes,
-                                                                        tskMPU_WRITE_PERMISSION );
+            size_t xReturn = 0;
+            StreamBufferHandle_t xInternalStreamBufferHandle = NULL;
+            int32_t lIndex;
+            BaseType_t xIsRxDataBufferWriteable = pdFALSE;
+            BaseType_t xCallingTaskIsAuthorizedToAccessStreamBuffer = pdFALSE;
 
-            if( xIsRxDataBufferWriteable == pdTRUE )
+            if( pvRxData != NULL )
             {
-                lIndex = ( int32_t ) xStreamBuffer;
+                xIsRxDataBufferWriteable = xPortIsAuthorizedToAccessBuffer( pvRxData,
+                                                                            xBufferLengthBytes,
+                                                                            tskMPU_WRITE_PERMISSION );
 
-                if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+                if( xIsRxDataBufferWriteable == pdTRUE )
                 {
-                    xCallingTaskIsAuthorizedToAccessStreamBuffer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                    lIndex = ( int32_t ) xStreamBuffer;
 
-                    if( xCallingTaskIsAuthorizedToAccessStreamBuffer == pdTRUE )
+                    if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
                     {
-                        xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                        xCallingTaskIsAuthorizedToAccessStreamBuffer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-                        if( xInternalStreamBufferHandle != NULL )
+                        if( xCallingTaskIsAuthorizedToAccessStreamBuffer == pdTRUE )
                         {
-                            xReturn = xStreamBufferReceive( xInternalStreamBufferHandle, pvRxData, xBufferLengthBytes, xTicksToWait );
+                            xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                            if( xInternalStreamBufferHandle != NULL )
+                            {
+                                xReturn = xStreamBufferReceive( xInternalStreamBufferHandle, pvRxData, xBufferLengthBytes, xTicksToWait );
+                            }
                         }
                     }
                 }
             }
+
+            return xReturn;
         }
 
-        return xReturn;
-    }
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xStreamBufferIsFullImpl( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    BaseType_t MPU_xStreamBufferIsFullImpl( StreamBufferHandle_t xStreamBuffer ) /* PRIVILEGED_FUNCTION */
-    {
-        BaseType_t xReturn = pdFALSE;
-        StreamBufferHandle_t xInternalStreamBufferHandle = NULL;
-        int32_t lIndex;
-        BaseType_t xCallingTaskIsAuthorizedToAccessStreamBuffer = pdFALSE;
+        BaseType_t MPU_xStreamBufferIsFullImpl( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
 
-        lIndex = ( int32_t ) xStreamBuffer;
-
-        if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+        BaseType_t MPU_xStreamBufferIsFullImpl( StreamBufferHandle_t xStreamBuffer ) /* PRIVILEGED_FUNCTION */
         {
-            xCallingTaskIsAuthorizedToAccessStreamBuffer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+            BaseType_t xReturn = pdFALSE;
+            StreamBufferHandle_t xInternalStreamBufferHandle = NULL;
+            int32_t lIndex;
+            BaseType_t xCallingTaskIsAuthorizedToAccessStreamBuffer = pdFALSE;
 
-            if( xCallingTaskIsAuthorizedToAccessStreamBuffer == pdTRUE )
+            lIndex = ( int32_t ) xStreamBuffer;
+
+            if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
             {
-                xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                xCallingTaskIsAuthorizedToAccessStreamBuffer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-                if( xInternalStreamBufferHandle != NULL )
+                if( xCallingTaskIsAuthorizedToAccessStreamBuffer == pdTRUE )
                 {
-                    xReturn = xStreamBufferIsFull( xInternalStreamBufferHandle );
+                    xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                    if( xInternalStreamBufferHandle != NULL )
+                    {
+                        xReturn = xStreamBufferIsFull( xInternalStreamBufferHandle );
+                    }
                 }
             }
+
+            return xReturn;
         }
 
-        return xReturn;
-    }
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xStreamBufferIsEmptyImpl( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    BaseType_t MPU_xStreamBufferIsEmptyImpl( StreamBufferHandle_t xStreamBuffer ) /* PRIVILEGED_FUNCTION */
-    {
-        BaseType_t xReturn = pdFALSE;
-        StreamBufferHandle_t xInternalStreamBufferHandle = NULL;
-        int32_t lIndex;
-        BaseType_t xCallingTaskIsAuthorizedToAccessStreamBuffer = pdFALSE;
+        BaseType_t MPU_xStreamBufferIsEmptyImpl( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
 
-        lIndex = ( int32_t ) xStreamBuffer;
-
-        if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+        BaseType_t MPU_xStreamBufferIsEmptyImpl( StreamBufferHandle_t xStreamBuffer ) /* PRIVILEGED_FUNCTION */
         {
-            xCallingTaskIsAuthorizedToAccessStreamBuffer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+            BaseType_t xReturn = pdFALSE;
+            StreamBufferHandle_t xInternalStreamBufferHandle = NULL;
+            int32_t lIndex;
+            BaseType_t xCallingTaskIsAuthorizedToAccessStreamBuffer = pdFALSE;
 
-            if( xCallingTaskIsAuthorizedToAccessStreamBuffer == pdTRUE )
+            lIndex = ( int32_t ) xStreamBuffer;
+
+            if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
             {
-                xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                xCallingTaskIsAuthorizedToAccessStreamBuffer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-                if( xInternalStreamBufferHandle != NULL )
+                if( xCallingTaskIsAuthorizedToAccessStreamBuffer == pdTRUE )
                 {
-                    xReturn = xStreamBufferIsEmpty( xInternalStreamBufferHandle );
+                    xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                    if( xInternalStreamBufferHandle != NULL )
+                    {
+                        xReturn = xStreamBufferIsEmpty( xInternalStreamBufferHandle );
+                    }
                 }
             }
+
+            return xReturn;
         }
 
-        return xReturn;
-    }
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferSpacesAvailableImpl( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferSpacesAvailableImpl( StreamBufferHandle_t xStreamBuffer ) /* PRIVILEGED_FUNCTION */
-    {
-        size_t xReturn = 0;
-        StreamBufferHandle_t xInternalStreamBufferHandle = NULL;
-        int32_t lIndex;
-        BaseType_t xCallingTaskIsAuthorizedToAccessStreamBuffer = pdFALSE;
+        size_t MPU_xStreamBufferSpacesAvailableImpl( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
 
-        lIndex = ( int32_t ) xStreamBuffer;
-
-        if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+        size_t MPU_xStreamBufferSpacesAvailableImpl( StreamBufferHandle_t xStreamBuffer ) /* PRIVILEGED_FUNCTION */
         {
-            xCallingTaskIsAuthorizedToAccessStreamBuffer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+            size_t xReturn = 0;
+            StreamBufferHandle_t xInternalStreamBufferHandle = NULL;
+            int32_t lIndex;
+            BaseType_t xCallingTaskIsAuthorizedToAccessStreamBuffer = pdFALSE;
 
-            if( xCallingTaskIsAuthorizedToAccessStreamBuffer == pdTRUE )
+            lIndex = ( int32_t ) xStreamBuffer;
+
+            if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
             {
-                xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                xCallingTaskIsAuthorizedToAccessStreamBuffer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-                if( xInternalStreamBufferHandle != NULL )
+                if( xCallingTaskIsAuthorizedToAccessStreamBuffer == pdTRUE )
                 {
-                    xReturn = xStreamBufferSpacesAvailable( xInternalStreamBufferHandle );
+                    xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                    if( xInternalStreamBufferHandle != NULL )
+                    {
+                        xReturn = xStreamBufferSpacesAvailable( xInternalStreamBufferHandle );
+                    }
                 }
             }
+
+            return xReturn;
         }
 
-        return xReturn;
-    }
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferBytesAvailableImpl( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferBytesAvailableImpl( StreamBufferHandle_t xStreamBuffer ) /* PRIVILEGED_FUNCTION */
-    {
-        size_t xReturn = 0;
-        StreamBufferHandle_t xInternalStreamBufferHandle = NULL;
-        int32_t lIndex;
-        BaseType_t xCallingTaskIsAuthorizedToAccessStreamBuffer = pdFALSE;
+        size_t MPU_xStreamBufferBytesAvailableImpl( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
 
-        lIndex = ( int32_t ) xStreamBuffer;
-
-        if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+        size_t MPU_xStreamBufferBytesAvailableImpl( StreamBufferHandle_t xStreamBuffer ) /* PRIVILEGED_FUNCTION */
         {
-            xCallingTaskIsAuthorizedToAccessStreamBuffer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+            size_t xReturn = 0;
+            StreamBufferHandle_t xInternalStreamBufferHandle = NULL;
+            int32_t lIndex;
+            BaseType_t xCallingTaskIsAuthorizedToAccessStreamBuffer = pdFALSE;
 
-            if( xCallingTaskIsAuthorizedToAccessStreamBuffer == pdTRUE )
+            lIndex = ( int32_t ) xStreamBuffer;
+
+            if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
             {
-                xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                xCallingTaskIsAuthorizedToAccessStreamBuffer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-                if( xInternalStreamBufferHandle != NULL )
+                if( xCallingTaskIsAuthorizedToAccessStreamBuffer == pdTRUE )
                 {
-                    xReturn = xStreamBufferBytesAvailable( xInternalStreamBufferHandle );
+                    xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                    if( xInternalStreamBufferHandle != NULL )
+                    {
+                        xReturn = xStreamBufferBytesAvailable( xInternalStreamBufferHandle );
+                    }
                 }
             }
+
+            return xReturn;
         }
 
-        return xReturn;
-    }
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xStreamBufferSetTriggerLevelImpl( StreamBufferHandle_t xStreamBuffer,
-                                                     size_t xTriggerLevel ) PRIVILEGED_FUNCTION;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    BaseType_t MPU_xStreamBufferSetTriggerLevelImpl( StreamBufferHandle_t xStreamBuffer,
-                                                     size_t xTriggerLevel ) /* PRIVILEGED_FUNCTION */
-    {
-        BaseType_t xReturn = pdFALSE;
-        StreamBufferHandle_t xInternalStreamBufferHandle = NULL;
-        int32_t lIndex;
-        BaseType_t xCallingTaskIsAuthorizedToAccessStreamBuffer = pdFALSE;
+        BaseType_t MPU_xStreamBufferSetTriggerLevelImpl( StreamBufferHandle_t xStreamBuffer,
+                                                         size_t xTriggerLevel ) PRIVILEGED_FUNCTION;
 
-        lIndex = ( int32_t ) xStreamBuffer;
-
-        if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+        BaseType_t MPU_xStreamBufferSetTriggerLevelImpl( StreamBufferHandle_t xStreamBuffer,
+                                                         size_t xTriggerLevel ) /* PRIVILEGED_FUNCTION */
         {
-            xCallingTaskIsAuthorizedToAccessStreamBuffer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+            BaseType_t xReturn = pdFALSE;
+            StreamBufferHandle_t xInternalStreamBufferHandle = NULL;
+            int32_t lIndex;
+            BaseType_t xCallingTaskIsAuthorizedToAccessStreamBuffer = pdFALSE;
 
-            if( xCallingTaskIsAuthorizedToAccessStreamBuffer == pdTRUE )
+            lIndex = ( int32_t ) xStreamBuffer;
+
+            if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
             {
-                xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                xCallingTaskIsAuthorizedToAccessStreamBuffer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-                if( xInternalStreamBufferHandle != NULL )
+                if( xCallingTaskIsAuthorizedToAccessStreamBuffer == pdTRUE )
                 {
-                    xReturn = xStreamBufferSetTriggerLevel( xInternalStreamBufferHandle, xTriggerLevel );
+                    xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                    if( xInternalStreamBufferHandle != NULL )
+                    {
+                        xReturn = xStreamBufferSetTriggerLevel( xInternalStreamBufferHandle, xTriggerLevel );
+                    }
                 }
             }
+
+            return xReturn;
         }
 
-        return xReturn;
-    }
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferNextMessageLengthBytesImpl( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferNextMessageLengthBytesImpl( StreamBufferHandle_t xStreamBuffer ) /* PRIVILEGED_FUNCTION */
-    {
-        size_t xReturn = 0;
-        StreamBufferHandle_t xInternalStreamBufferHandle = NULL;
-        int32_t lIndex;
-        BaseType_t xCallingTaskIsAuthorizedToAccessStreamBuffer = pdFALSE;
+        size_t MPU_xStreamBufferNextMessageLengthBytesImpl( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
 
-        lIndex = ( int32_t ) xStreamBuffer;
-
-        if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+        size_t MPU_xStreamBufferNextMessageLengthBytesImpl( StreamBufferHandle_t xStreamBuffer ) /* PRIVILEGED_FUNCTION */
         {
-            xCallingTaskIsAuthorizedToAccessStreamBuffer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+            size_t xReturn = 0;
+            StreamBufferHandle_t xInternalStreamBufferHandle = NULL;
+            int32_t lIndex;
+            BaseType_t xCallingTaskIsAuthorizedToAccessStreamBuffer = pdFALSE;
 
-            if( xCallingTaskIsAuthorizedToAccessStreamBuffer == pdTRUE )
+            lIndex = ( int32_t ) xStreamBuffer;
+
+            if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
             {
-                xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+                xCallingTaskIsAuthorizedToAccessStreamBuffer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-                if( xInternalStreamBufferHandle != NULL )
+                if( xCallingTaskIsAuthorizedToAccessStreamBuffer == pdTRUE )
                 {
-                    xReturn = xStreamBufferNextMessageLengthBytes( xInternalStreamBufferHandle );
+                    xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                    if( xInternalStreamBufferHandle != NULL )
+                    {
+                        xReturn = xStreamBufferNextMessageLengthBytes( xInternalStreamBufferHandle );
+                    }
                 }
             }
+
+            return xReturn;
         }
 
-        return xReturn;
-    }
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
 /* Privileged only wrappers for Stream Buffer APIs. These are needed so that
@@ -4597,7 +4658,7 @@
  * with all the APIs. */
 /*-----------------------------------------------------------*/
 
-    #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+    #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_STREAM_BUFFERS == 1 ) )
 
         StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes,
                                                              size_t xTriggerLevelBytes,
@@ -4649,10 +4710,10 @@
             return xExternalStreamBufferHandle;
         }
 
-    #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+    #endif /* #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_STREAM_BUFFERS == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-    #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+    #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_STREAM_BUFFERS == 1 ) )
 
         StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
                                                                    size_t xTriggerLevelBytes,
@@ -4708,53 +4769,61 @@
             return xExternalStreamBufferHandle;
         }
 
-    #endif /* configSUPPORT_STATIC_ALLOCATION */
+    #endif /* #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_STREAM_BUFFERS == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-    void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) /* PRIVILEGED_FUNCTION */
-    {
-        StreamBufferHandle_t xInternalStreamBufferHandle = NULL;
-        int32_t lIndex;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-        lIndex = ( int32_t ) xStreamBuffer;
-
-        if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+        void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) /* PRIVILEGED_FUNCTION */
         {
-            xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+            StreamBufferHandle_t xInternalStreamBufferHandle = NULL;
+            int32_t lIndex;
 
-            if( xInternalStreamBufferHandle != NULL )
+            lIndex = ( int32_t ) xStreamBuffer;
+
+            if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
             {
-                vStreamBufferDelete( xInternalStreamBufferHandle );
-            }
+                xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-            MPU_SetIndexFreeInKernelObjectPool( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
-        }
-    }
-/*-----------------------------------------------------------*/
+                if( xInternalStreamBufferHandle != NULL )
+                {
+                    vStreamBufferDelete( xInternalStreamBufferHandle );
+                }
 
-    BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) /* PRIVILEGED_FUNCTION */
-    {
-        BaseType_t xReturn = pdFALSE;
-        StreamBufferHandle_t xInternalStreamBufferHandle = NULL;
-        int32_t lIndex;
-
-        lIndex = ( int32_t ) xStreamBuffer;
-
-        if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
-        {
-            xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
-
-            if( xInternalStreamBufferHandle != NULL )
-            {
-                xReturn = xStreamBufferReset( xInternalStreamBufferHandle );
+                MPU_SetIndexFreeInKernelObjectPool( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
             }
         }
 
-        return xReturn;
-    }
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+    #if ( configUSE_STREAM_BUFFERS == 1 )
+
+        BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) /* PRIVILEGED_FUNCTION */
+        {
+            BaseType_t xReturn = pdFALSE;
+            StreamBufferHandle_t xInternalStreamBufferHandle = NULL;
+            int32_t lIndex;
+
+            lIndex = ( int32_t ) xStreamBuffer;
+
+            if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+            {
+                xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                if( xInternalStreamBufferHandle != NULL )
+                {
+                    xReturn = xStreamBufferReset( xInternalStreamBufferHandle );
+                }
+            }
+
+            return xReturn;
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+    #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_STREAM_BUFFERS == 1 ) )
 
         BaseType_t MPU_xStreamBufferGetStaticBuffers( StreamBufferHandle_t xStreamBuffers,
                                                       uint8_t * ppucStreamBufferStorageArea,
@@ -4779,9 +4848,11 @@
             return xReturn;
         }
 
-    #endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+    #endif /* #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_STREAM_BUFFERS == 1 ) ) */
 /*-----------------------------------------------------------*/
 
+    #if ( configUSE_STREAM_BUFFERS == 1 )
+
     size_t MPU_xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
                                          const void * pvTxData,
                                          size_t xDataLengthBytes,
@@ -4805,8 +4876,12 @@
 
         return xReturn;
     }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
+    #if ( configUSE_STREAM_BUFFERS == 1 )
+
     size_t MPU_xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
                                             void * pvRxData,
                                             size_t xBufferLengthBytes,
@@ -4830,52 +4905,62 @@
 
         return xReturn;
     }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer,
-                                                      BaseType_t * pxHigherPriorityTaskWoken ) /* PRIVILEGED_FUNCTION */
-    {
-        BaseType_t xReturn = pdFALSE;
-        StreamBufferHandle_t xInternalStreamBufferHandle = NULL;
-        int32_t lIndex;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-        lIndex = ( int32_t ) xStreamBuffer;
-
-        if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+        BaseType_t MPU_xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer,
+                                                          BaseType_t * pxHigherPriorityTaskWoken ) /* PRIVILEGED_FUNCTION */
         {
-            xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+            BaseType_t xReturn = pdFALSE;
+            StreamBufferHandle_t xInternalStreamBufferHandle = NULL;
+            int32_t lIndex;
 
-            if( xInternalStreamBufferHandle != NULL )
+            lIndex = ( int32_t ) xStreamBuffer;
+
+            if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
             {
-                xReturn = xStreamBufferSendCompletedFromISR( xInternalStreamBufferHandle, pxHigherPriorityTaskWoken );
+                xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                if( xInternalStreamBufferHandle != NULL )
+                {
+                    xReturn = xStreamBufferSendCompletedFromISR( xInternalStreamBufferHandle, pxHigherPriorityTaskWoken );
+                }
             }
+
+            return xReturn;
         }
 
-        return xReturn;
-    }
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer,
-                                                         BaseType_t * pxHigherPriorityTaskWoken ) /*PRIVILEGED_FUNCTION */
-    {
-        BaseType_t xReturn = pdFALSE;
-        StreamBufferHandle_t xInternalStreamBufferHandle = NULL;
-        int32_t lIndex;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-        lIndex = ( int32_t ) xStreamBuffer;
-
-        if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+        BaseType_t MPU_xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer,
+                                                             BaseType_t * pxHigherPriorityTaskWoken ) /*PRIVILEGED_FUNCTION */
         {
-            xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+            BaseType_t xReturn = pdFALSE;
+            StreamBufferHandle_t xInternalStreamBufferHandle = NULL;
+            int32_t lIndex;
 
-            if( xInternalStreamBufferHandle != NULL )
+            lIndex = ( int32_t ) xStreamBuffer;
+
+            if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
             {
-                xReturn = xStreamBufferReceiveCompletedFromISR( xInternalStreamBufferHandle, pxHigherPriorityTaskWoken );
+                xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                if( xInternalStreamBufferHandle != NULL )
+                {
+                    xReturn = xStreamBufferReceiveCompletedFromISR( xInternalStreamBufferHandle, pxHigherPriorityTaskWoken );
+                }
             }
+
+            return xReturn;
         }
 
-        return xReturn;
-    }
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 
 /*-----------------------------------------------------------*/
 
@@ -4909,7 +4994,11 @@
             ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_xTimerGenericCommandFromTask. */
         #endif
 
-        ( UBaseType_t ) MPU_xEventGroupWaitBitsImpl,                        /* SYSTEM_CALL_xEventGroupWaitBits. */
+        #if ( configUSE_EVENT_GROUPS == 1 )
+            ( UBaseType_t ) MPU_xEventGroupWaitBitsImpl,                    /* SYSTEM_CALL_xEventGroupWaitBits. */
+        #else
+            ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_xEventGroupWaitBits. */
+        #endif
 
         /* The system calls above this line take 5 parameters. */
 
@@ -5104,26 +5193,46 @@
             ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_xTimerGetExpiryTime. */
         #endif
 
-        ( UBaseType_t ) MPU_xEventGroupClearBitsImpl,                       /* SYSTEM_CALL_xEventGroupClearBits. */
-        ( UBaseType_t ) MPU_xEventGroupSetBitsImpl,                         /* SYSTEM_CALL_xEventGroupSetBits. */
-        ( UBaseType_t ) MPU_xEventGroupSyncImpl,                            /* SYSTEM_CALL_xEventGroupSync. */
+        #if ( configUSE_EVENT_GROUPS == 1 )
+            ( UBaseType_t ) MPU_xEventGroupClearBitsImpl,                   /* SYSTEM_CALL_xEventGroupClearBits. */
+            ( UBaseType_t ) MPU_xEventGroupSetBitsImpl,                     /* SYSTEM_CALL_xEventGroupSetBits. */
+            ( UBaseType_t ) MPU_xEventGroupSyncImpl,                        /* SYSTEM_CALL_xEventGroupSync. */
 
-        #if ( configUSE_TRACE_FACILITY == 1 )
-            ( UBaseType_t ) MPU_uxEventGroupGetNumberImpl,                  /* SYSTEM_CALL_uxEventGroupGetNumber. */
-            ( UBaseType_t ) MPU_vEventGroupSetNumberImpl,                   /* SYSTEM_CALL_vEventGroupSetNumber. */
+            #if ( configUSE_TRACE_FACILITY == 1 )
+                ( UBaseType_t ) MPU_uxEventGroupGetNumberImpl,              /* SYSTEM_CALL_uxEventGroupGetNumber. */
+                ( UBaseType_t ) MPU_vEventGroupSetNumberImpl,               /* SYSTEM_CALL_vEventGroupSetNumber. */
+            #else
+                ( UBaseType_t ) 0,                                          /* SYSTEM_CALL_uxEventGroupGetNumber. */
+                ( UBaseType_t ) 0,                                          /* SYSTEM_CALL_vEventGroupSetNumber. */
+            #endif
         #else
+            ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_xEventGroupClearBits. */
+            ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_xEventGroupSetBits. */
+            ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_xEventGroupSync. */
             ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_uxEventGroupGetNumber. */
             ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_vEventGroupSetNumber. */
         #endif
 
-        ( UBaseType_t ) MPU_xStreamBufferSendImpl,                          /* SYSTEM_CALL_xStreamBufferSend. */
-        ( UBaseType_t ) MPU_xStreamBufferReceiveImpl,                       /* SYSTEM_CALL_xStreamBufferReceive. */
-        ( UBaseType_t ) MPU_xStreamBufferIsFullImpl,                        /* SYSTEM_CALL_xStreamBufferIsFull. */
-        ( UBaseType_t ) MPU_xStreamBufferIsEmptyImpl,                       /* SYSTEM_CALL_xStreamBufferIsEmpty. */
-        ( UBaseType_t ) MPU_xStreamBufferSpacesAvailableImpl,               /* SYSTEM_CALL_xStreamBufferSpacesAvailable. */
-        ( UBaseType_t ) MPU_xStreamBufferBytesAvailableImpl,                /* SYSTEM_CALL_xStreamBufferBytesAvailable. */
-        ( UBaseType_t ) MPU_xStreamBufferSetTriggerLevelImpl,               /* SYSTEM_CALL_xStreamBufferSetTriggerLevel. */
-        ( UBaseType_t ) MPU_xStreamBufferNextMessageLengthBytesImpl         /* SYSTEM_CALL_xStreamBufferNextMessageLengthBytes. */
+        #if ( configUSE_STREAM_BUFFERS == 1 )
+            ( UBaseType_t ) MPU_xStreamBufferSendImpl,                      /* SYSTEM_CALL_xStreamBufferSend. */
+            ( UBaseType_t ) MPU_xStreamBufferReceiveImpl,                   /* SYSTEM_CALL_xStreamBufferReceive. */
+            ( UBaseType_t ) MPU_xStreamBufferIsFullImpl,                    /* SYSTEM_CALL_xStreamBufferIsFull. */
+            ( UBaseType_t ) MPU_xStreamBufferIsEmptyImpl,                   /* SYSTEM_CALL_xStreamBufferIsEmpty. */
+            ( UBaseType_t ) MPU_xStreamBufferSpacesAvailableImpl,           /* SYSTEM_CALL_xStreamBufferSpacesAvailable. */
+            ( UBaseType_t ) MPU_xStreamBufferBytesAvailableImpl,            /* SYSTEM_CALL_xStreamBufferBytesAvailable. */
+            ( UBaseType_t ) MPU_xStreamBufferSetTriggerLevelImpl,           /* SYSTEM_CALL_xStreamBufferSetTriggerLevel. */
+            ( UBaseType_t ) MPU_xStreamBufferNextMessageLengthBytesImpl     /* SYSTEM_CALL_xStreamBufferNextMessageLengthBytes. */
+        #else
+            ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_xStreamBufferSend. */
+            ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_xStreamBufferReceive. */
+            ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_xStreamBufferIsFull. */
+            ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_xStreamBufferIsEmpty. */
+            ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_xStreamBufferSpacesAvailable. */
+            ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_xStreamBufferBytesAvailable. */
+            ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_xStreamBufferSetTriggerLevel. */
+            ( UBaseType_t ) 0,                                              /* SYSTEM_CALL_xStreamBufferNextMessageLengthBytes. */
+        #endif
+
     };
 /*-----------------------------------------------------------*/
 
diff --git a/portable/GCC/ARM_CM23/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM23/non_secure/mpu_wrappers_v2_asm.c
index fb167a699..1fb67891d 100644
--- a/portable/GCC/ARM_CM23/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM23/non_secure/mpu_wrappers_v2_asm.c
@@ -1690,117 +1690,133 @@
     #endif /* if ( configUSE_TIMERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupWaitBitsImpl                   \n"
-            "                                                       \n"
-            " push {r0, r1}                                         \n"
-            " mrs r0, control                                       \n"
-            " movs r1, #1                                           \n"
-            " tst r0, r1                                            \n"
-            " pop {r0, r1}                                          \n"
-            " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
-            " MPU_xEventGroupWaitBits_Priv:                         \n"
-            "     b MPU_xEventGroupWaitBitsImpl                     \n"
-            " MPU_xEventGroupWaitBits_Unpriv:                       \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
-        );
-    }
+        EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupWaitBitsImpl                   \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
+                " MPU_xEventGroupWaitBits_Priv:                         \n"
+                "     b MPU_xEventGroupWaitBitsImpl                     \n"
+                " MPU_xEventGroupWaitBits_Unpriv:                       \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                          const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                          const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupClearBitsImpl                  \n"
-            "                                                       \n"
-            " push {r0, r1}                                         \n"
-            " mrs r0, control                                       \n"
-            " movs r1, #1                                           \n"
-            " tst r0, r1                                            \n"
-            " pop {r0, r1}                                          \n"
-            " bne MPU_xEventGroupClearBits_Unpriv                   \n"
-            " MPU_xEventGroupClearBits_Priv:                        \n"
-            "     b MPU_xEventGroupClearBitsImpl                    \n"
-            " MPU_xEventGroupClearBits_Unpriv:                      \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
-        );
-    }
+        EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                              const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                              const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupClearBitsImpl                  \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xEventGroupClearBits_Unpriv                   \n"
+                " MPU_xEventGroupClearBits_Priv:                        \n"
+                "     b MPU_xEventGroupClearBitsImpl                    \n"
+                " MPU_xEventGroupClearBits_Unpriv:                      \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                        const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                        const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupSetBitsImpl                    \n"
-            "                                                       \n"
-            " push {r0, r1}                                         \n"
-            " mrs r0, control                                       \n"
-            " movs r1, #1                                           \n"
-            " tst r0, r1                                            \n"
-            " pop {r0, r1}                                          \n"
-            " bne MPU_xEventGroupSetBits_Unpriv                     \n"
-            " MPU_xEventGroupSetBits_Priv:                          \n"
-            "     b MPU_xEventGroupSetBitsImpl                      \n"
-            " MPU_xEventGroupSetBits_Unpriv:                        \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
-        );
-    }
+        EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                            const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                            const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupSetBitsImpl                    \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xEventGroupSetBits_Unpriv                     \n"
+                " MPU_xEventGroupSetBits_Priv:                          \n"
+                "     b MPU_xEventGroupSetBitsImpl                      \n"
+                " MPU_xEventGroupSetBits_Unpriv:                        \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                     const EventBits_t uxBitsToSet,
-                                     const EventBits_t uxBitsToWaitFor,
-                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                     const EventBits_t uxBitsToSet,
-                                     const EventBits_t uxBitsToWaitFor,
-                                     TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupSyncImpl                       \n"
-            "                                                       \n"
-            " push {r0, r1}                                         \n"
-            " mrs r0, control                                       \n"
-            " movs r1, #1                                           \n"
-            " tst r0, r1                                            \n"
-            " pop {r0, r1}                                          \n"
-            " bne MPU_xEventGroupSync_Unpriv                        \n"
-            " MPU_xEventGroupSync_Priv:                             \n"
-            "     b MPU_xEventGroupSyncImpl                         \n"
-            " MPU_xEventGroupSync_Unpriv:                           \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
-        );
-    }
+        EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToSet,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToSet,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupSyncImpl                       \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xEventGroupSync_Unpriv                        \n"
+                " MPU_xEventGroupSync_Priv:                             \n"
+                "     b MPU_xEventGroupSyncImpl                         \n"
+                " MPU_xEventGroupSync_Unpriv:                           \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    #if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
 
         UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
@@ -1826,10 +1842,10 @@
             );
         }
 
-    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-    #if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
 
         void MPU_vEventGroupSetNumber( void * xEventGroup,
                                        UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
@@ -1857,221 +1873,253 @@
             );
         }
 
-    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                                  const void * pvTxData,
-                                  size_t xDataLengthBytes,
-                                  TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                                  const void * pvTxData,
-                                  size_t xDataLengthBytes,
-                                  TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferSendImpl                     \n"
-            "                                                       \n"
-            " push {r0, r1}                                         \n"
-            " mrs r0, control                                       \n"
-            " movs r1, #1                                           \n"
-            " tst r0, r1                                            \n"
-            " pop {r0, r1}                                          \n"
-            " bne MPU_xStreamBufferSend_Unpriv                      \n"
-            " MPU_xStreamBufferSend_Priv:                           \n"
-            "     b MPU_xStreamBufferSendImpl                       \n"
-            " MPU_xStreamBufferSend_Unpriv:                         \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                      const void * pvTxData,
+                                      size_t xDataLengthBytes,
+                                      TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                      const void * pvTxData,
+                                      size_t xDataLengthBytes,
+                                      TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferSendImpl                     \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xStreamBufferSend_Unpriv                      \n"
+                " MPU_xStreamBufferSend_Priv:                           \n"
+                "     b MPU_xStreamBufferSendImpl                       \n"
+                " MPU_xStreamBufferSend_Unpriv:                         \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                     void * pvRxData,
-                                     size_t xBufferLengthBytes,
-                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                     void * pvRxData,
-                                     size_t xBufferLengthBytes,
-                                     TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferReceiveImpl                  \n"
-            "                                                       \n"
-            " push {r0, r1}                                         \n"
-            " mrs r0, control                                       \n"
-            " movs r1, #1                                           \n"
-            " tst r0, r1                                            \n"
-            " pop {r0, r1}                                          \n"
-            " bne MPU_xStreamBufferReceive_Unpriv                   \n"
-            " MPU_xStreamBufferReceive_Priv:                        \n"
-            "     b MPU_xStreamBufferReceiveImpl                    \n"
-            " MPU_xStreamBufferReceive_Unpriv:                      \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                         void * pvRxData,
+                                         size_t xBufferLengthBytes,
+                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                         void * pvRxData,
+                                         size_t xBufferLengthBytes,
+                                         TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferReceiveImpl                  \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xStreamBufferReceive_Unpriv                   \n"
+                " MPU_xStreamBufferReceive_Priv:                        \n"
+                "     b MPU_xStreamBufferReceiveImpl                    \n"
+                " MPU_xStreamBufferReceive_Unpriv:                      \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferIsFullImpl                   \n"
-            "                                                       \n"
-            " push {r0, r1}                                         \n"
-            " mrs r0, control                                       \n"
-            " movs r1, #1                                           \n"
-            " tst r0, r1                                            \n"
-            " pop {r0, r1}                                          \n"
-            " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
-            " MPU_xStreamBufferIsFull_Priv:                         \n"
-            "     b MPU_xStreamBufferIsFullImpl                     \n"
-            " MPU_xStreamBufferIsFull_Unpriv:                       \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
-        );
-    }
+        BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferIsFullImpl                   \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
+                " MPU_xStreamBufferIsFull_Priv:                         \n"
+                "     b MPU_xStreamBufferIsFullImpl                     \n"
+                " MPU_xStreamBufferIsFull_Unpriv:                       \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
-            "                                                       \n"
-            " push {r0, r1}                                         \n"
-            " mrs r0, control                                       \n"
-            " movs r1, #1                                           \n"
-            " tst r0, r1                                            \n"
-            " pop {r0, r1}                                          \n"
-            " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
-            " MPU_xStreamBufferIsEmpty_Priv:                        \n"
-            "     b MPU_xStreamBufferIsEmptyImpl                    \n"
-            " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
-        );
-    }
+        BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
+                " MPU_xStreamBufferIsEmpty_Priv:                        \n"
+                "     b MPU_xStreamBufferIsEmptyImpl                    \n"
+                " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
-            "                                                       \n"
-            " push {r0, r1}                                         \n"
-            " mrs r0, control                                       \n"
-            " movs r1, #1                                           \n"
-            " tst r0, r1                                            \n"
-            " pop {r0, r1}                                          \n"
-            " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
-            " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
-            "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
-            " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
+                " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
+                "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
+                " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
-            "                                                       \n"
-            " push {r0, r1}                                         \n"
-            " mrs r0, control                                       \n"
-            " movs r1, #1                                           \n"
-            " tst r0, r1                                            \n"
-            " pop {r0, r1}                                          \n"
-            " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
-            " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
-            "     b MPU_xStreamBufferBytesAvailableImpl             \n"
-            " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
+                " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
+                "     b MPU_xStreamBufferBytesAvailableImpl             \n"
+                " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                                 size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                                 size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
-            "                                                       \n"
-            " push {r0, r1}                                         \n"
-            " mrs r0, control                                       \n"
-            " movs r1, #1                                           \n"
-            " tst r0, r1                                            \n"
-            " pop {r0, r1}                                          \n"
-            " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
-            " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
-            "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
-            " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
-        );
-    }
+        BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                     size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                     size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
+                " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
+                "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
+                " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
-            "                                                       \n"
-            " push {r0, r1}                                         \n"
-            " mrs r0, control                                       \n"
-            " movs r1, #1                                           \n"
-            " tst r0, r1                                            \n"
-            " pop {r0, r1}                                          \n"
-            " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
-            " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
-            "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
-            " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
+                " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
+                "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
+                " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.c
index fb167a699..1fb67891d 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.c
@@ -1690,117 +1690,133 @@
     #endif /* if ( configUSE_TIMERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupWaitBitsImpl                   \n"
-            "                                                       \n"
-            " push {r0, r1}                                         \n"
-            " mrs r0, control                                       \n"
-            " movs r1, #1                                           \n"
-            " tst r0, r1                                            \n"
-            " pop {r0, r1}                                          \n"
-            " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
-            " MPU_xEventGroupWaitBits_Priv:                         \n"
-            "     b MPU_xEventGroupWaitBitsImpl                     \n"
-            " MPU_xEventGroupWaitBits_Unpriv:                       \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
-        );
-    }
+        EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupWaitBitsImpl                   \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
+                " MPU_xEventGroupWaitBits_Priv:                         \n"
+                "     b MPU_xEventGroupWaitBitsImpl                     \n"
+                " MPU_xEventGroupWaitBits_Unpriv:                       \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                          const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                          const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupClearBitsImpl                  \n"
-            "                                                       \n"
-            " push {r0, r1}                                         \n"
-            " mrs r0, control                                       \n"
-            " movs r1, #1                                           \n"
-            " tst r0, r1                                            \n"
-            " pop {r0, r1}                                          \n"
-            " bne MPU_xEventGroupClearBits_Unpriv                   \n"
-            " MPU_xEventGroupClearBits_Priv:                        \n"
-            "     b MPU_xEventGroupClearBitsImpl                    \n"
-            " MPU_xEventGroupClearBits_Unpriv:                      \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
-        );
-    }
+        EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                              const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                              const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupClearBitsImpl                  \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xEventGroupClearBits_Unpriv                   \n"
+                " MPU_xEventGroupClearBits_Priv:                        \n"
+                "     b MPU_xEventGroupClearBitsImpl                    \n"
+                " MPU_xEventGroupClearBits_Unpriv:                      \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                        const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                        const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupSetBitsImpl                    \n"
-            "                                                       \n"
-            " push {r0, r1}                                         \n"
-            " mrs r0, control                                       \n"
-            " movs r1, #1                                           \n"
-            " tst r0, r1                                            \n"
-            " pop {r0, r1}                                          \n"
-            " bne MPU_xEventGroupSetBits_Unpriv                     \n"
-            " MPU_xEventGroupSetBits_Priv:                          \n"
-            "     b MPU_xEventGroupSetBitsImpl                      \n"
-            " MPU_xEventGroupSetBits_Unpriv:                        \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
-        );
-    }
+        EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                            const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                            const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupSetBitsImpl                    \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xEventGroupSetBits_Unpriv                     \n"
+                " MPU_xEventGroupSetBits_Priv:                          \n"
+                "     b MPU_xEventGroupSetBitsImpl                      \n"
+                " MPU_xEventGroupSetBits_Unpriv:                        \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                     const EventBits_t uxBitsToSet,
-                                     const EventBits_t uxBitsToWaitFor,
-                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                     const EventBits_t uxBitsToSet,
-                                     const EventBits_t uxBitsToWaitFor,
-                                     TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupSyncImpl                       \n"
-            "                                                       \n"
-            " push {r0, r1}                                         \n"
-            " mrs r0, control                                       \n"
-            " movs r1, #1                                           \n"
-            " tst r0, r1                                            \n"
-            " pop {r0, r1}                                          \n"
-            " bne MPU_xEventGroupSync_Unpriv                        \n"
-            " MPU_xEventGroupSync_Priv:                             \n"
-            "     b MPU_xEventGroupSyncImpl                         \n"
-            " MPU_xEventGroupSync_Unpriv:                           \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
-        );
-    }
+        EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToSet,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToSet,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupSyncImpl                       \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xEventGroupSync_Unpriv                        \n"
+                " MPU_xEventGroupSync_Priv:                             \n"
+                "     b MPU_xEventGroupSyncImpl                         \n"
+                " MPU_xEventGroupSync_Unpriv:                           \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    #if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
 
         UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
@@ -1826,10 +1842,10 @@
             );
         }
 
-    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-    #if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
 
         void MPU_vEventGroupSetNumber( void * xEventGroup,
                                        UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
@@ -1857,221 +1873,253 @@
             );
         }
 
-    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                                  const void * pvTxData,
-                                  size_t xDataLengthBytes,
-                                  TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                                  const void * pvTxData,
-                                  size_t xDataLengthBytes,
-                                  TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferSendImpl                     \n"
-            "                                                       \n"
-            " push {r0, r1}                                         \n"
-            " mrs r0, control                                       \n"
-            " movs r1, #1                                           \n"
-            " tst r0, r1                                            \n"
-            " pop {r0, r1}                                          \n"
-            " bne MPU_xStreamBufferSend_Unpriv                      \n"
-            " MPU_xStreamBufferSend_Priv:                           \n"
-            "     b MPU_xStreamBufferSendImpl                       \n"
-            " MPU_xStreamBufferSend_Unpriv:                         \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                      const void * pvTxData,
+                                      size_t xDataLengthBytes,
+                                      TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                      const void * pvTxData,
+                                      size_t xDataLengthBytes,
+                                      TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferSendImpl                     \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xStreamBufferSend_Unpriv                      \n"
+                " MPU_xStreamBufferSend_Priv:                           \n"
+                "     b MPU_xStreamBufferSendImpl                       \n"
+                " MPU_xStreamBufferSend_Unpriv:                         \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                     void * pvRxData,
-                                     size_t xBufferLengthBytes,
-                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                     void * pvRxData,
-                                     size_t xBufferLengthBytes,
-                                     TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferReceiveImpl                  \n"
-            "                                                       \n"
-            " push {r0, r1}                                         \n"
-            " mrs r0, control                                       \n"
-            " movs r1, #1                                           \n"
-            " tst r0, r1                                            \n"
-            " pop {r0, r1}                                          \n"
-            " bne MPU_xStreamBufferReceive_Unpriv                   \n"
-            " MPU_xStreamBufferReceive_Priv:                        \n"
-            "     b MPU_xStreamBufferReceiveImpl                    \n"
-            " MPU_xStreamBufferReceive_Unpriv:                      \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                         void * pvRxData,
+                                         size_t xBufferLengthBytes,
+                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                         void * pvRxData,
+                                         size_t xBufferLengthBytes,
+                                         TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferReceiveImpl                  \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xStreamBufferReceive_Unpriv                   \n"
+                " MPU_xStreamBufferReceive_Priv:                        \n"
+                "     b MPU_xStreamBufferReceiveImpl                    \n"
+                " MPU_xStreamBufferReceive_Unpriv:                      \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferIsFullImpl                   \n"
-            "                                                       \n"
-            " push {r0, r1}                                         \n"
-            " mrs r0, control                                       \n"
-            " movs r1, #1                                           \n"
-            " tst r0, r1                                            \n"
-            " pop {r0, r1}                                          \n"
-            " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
-            " MPU_xStreamBufferIsFull_Priv:                         \n"
-            "     b MPU_xStreamBufferIsFullImpl                     \n"
-            " MPU_xStreamBufferIsFull_Unpriv:                       \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
-        );
-    }
+        BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferIsFullImpl                   \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
+                " MPU_xStreamBufferIsFull_Priv:                         \n"
+                "     b MPU_xStreamBufferIsFullImpl                     \n"
+                " MPU_xStreamBufferIsFull_Unpriv:                       \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
-            "                                                       \n"
-            " push {r0, r1}                                         \n"
-            " mrs r0, control                                       \n"
-            " movs r1, #1                                           \n"
-            " tst r0, r1                                            \n"
-            " pop {r0, r1}                                          \n"
-            " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
-            " MPU_xStreamBufferIsEmpty_Priv:                        \n"
-            "     b MPU_xStreamBufferIsEmptyImpl                    \n"
-            " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
-        );
-    }
+        BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
+                " MPU_xStreamBufferIsEmpty_Priv:                        \n"
+                "     b MPU_xStreamBufferIsEmptyImpl                    \n"
+                " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
-            "                                                       \n"
-            " push {r0, r1}                                         \n"
-            " mrs r0, control                                       \n"
-            " movs r1, #1                                           \n"
-            " tst r0, r1                                            \n"
-            " pop {r0, r1}                                          \n"
-            " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
-            " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
-            "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
-            " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
+                " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
+                "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
+                " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
-            "                                                       \n"
-            " push {r0, r1}                                         \n"
-            " mrs r0, control                                       \n"
-            " movs r1, #1                                           \n"
-            " tst r0, r1                                            \n"
-            " pop {r0, r1}                                          \n"
-            " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
-            " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
-            "     b MPU_xStreamBufferBytesAvailableImpl             \n"
-            " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
+                " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
+                "     b MPU_xStreamBufferBytesAvailableImpl             \n"
+                " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                                 size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                                 size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
-            "                                                       \n"
-            " push {r0, r1}                                         \n"
-            " mrs r0, control                                       \n"
-            " movs r1, #1                                           \n"
-            " tst r0, r1                                            \n"
-            " pop {r0, r1}                                          \n"
-            " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
-            " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
-            "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
-            " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
-        );
-    }
+        BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                     size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                     size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
+                " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
+                "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
+                " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
-            "                                                       \n"
-            " push {r0, r1}                                         \n"
-            " mrs r0, control                                       \n"
-            " movs r1, #1                                           \n"
-            " tst r0, r1                                            \n"
-            " pop {r0, r1}                                          \n"
-            " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
-            " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
-            "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
-            " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
+                "                                                       \n"
+                " push {r0, r1}                                         \n"
+                " mrs r0, control                                       \n"
+                " movs r1, #1                                           \n"
+                " tst r0, r1                                            \n"
+                " pop {r0, r1}                                          \n"
+                " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
+                " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
+                "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
+                " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
diff --git a/portable/GCC/ARM_CM33/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM33/non_secure/mpu_wrappers_v2_asm.c
index 4f66448f9..6642c9e20 100644
--- a/portable/GCC/ARM_CM33/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM33/non_secure/mpu_wrappers_v2_asm.c
@@ -1634,113 +1634,129 @@
     #endif /* if ( configUSE_TIMERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupWaitBitsImpl                   \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
-            " MPU_xEventGroupWaitBits_Priv:                         \n"
-            "     b MPU_xEventGroupWaitBitsImpl                     \n"
-            " MPU_xEventGroupWaitBits_Unpriv:                       \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
-        );
-    }
+        EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupWaitBitsImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
+                " MPU_xEventGroupWaitBits_Priv:                         \n"
+                "     b MPU_xEventGroupWaitBitsImpl                     \n"
+                " MPU_xEventGroupWaitBits_Unpriv:                       \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                          const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                          const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupClearBitsImpl                  \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xEventGroupClearBits_Unpriv                   \n"
-            " MPU_xEventGroupClearBits_Priv:                        \n"
-            "     b MPU_xEventGroupClearBitsImpl                    \n"
-            " MPU_xEventGroupClearBits_Unpriv:                      \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
-        );
-    }
+        EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                              const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                              const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupClearBitsImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xEventGroupClearBits_Unpriv                   \n"
+                " MPU_xEventGroupClearBits_Priv:                        \n"
+                "     b MPU_xEventGroupClearBitsImpl                    \n"
+                " MPU_xEventGroupClearBits_Unpriv:                      \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                        const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                        const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupSetBitsImpl                    \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xEventGroupSetBits_Unpriv                     \n"
-            " MPU_xEventGroupSetBits_Priv:                          \n"
-            "     b MPU_xEventGroupSetBitsImpl                      \n"
-            " MPU_xEventGroupSetBits_Unpriv:                        \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
-        );
-    }
+        EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                            const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                            const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupSetBitsImpl                    \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xEventGroupSetBits_Unpriv                     \n"
+                " MPU_xEventGroupSetBits_Priv:                          \n"
+                "     b MPU_xEventGroupSetBitsImpl                      \n"
+                " MPU_xEventGroupSetBits_Unpriv:                        \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                     const EventBits_t uxBitsToSet,
-                                     const EventBits_t uxBitsToWaitFor,
-                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                     const EventBits_t uxBitsToSet,
-                                     const EventBits_t uxBitsToWaitFor,
-                                     TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupSyncImpl                       \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xEventGroupSync_Unpriv                        \n"
-            " MPU_xEventGroupSync_Priv:                             \n"
-            "     b MPU_xEventGroupSyncImpl                         \n"
-            " MPU_xEventGroupSync_Unpriv:                           \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
-        );
-    }
+        EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToSet,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToSet,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupSyncImpl                       \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xEventGroupSync_Unpriv                        \n"
+                " MPU_xEventGroupSync_Priv:                             \n"
+                "     b MPU_xEventGroupSyncImpl                         \n"
+                " MPU_xEventGroupSync_Unpriv:                           \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    #if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
 
         UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
@@ -1765,10 +1781,10 @@
             );
         }
 
-    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-    #if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
 
         void MPU_vEventGroupSetNumber( void * xEventGroup,
                                        UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
@@ -1795,213 +1811,245 @@
             );
         }
 
-    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                                  const void * pvTxData,
-                                  size_t xDataLengthBytes,
-                                  TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                                  const void * pvTxData,
-                                  size_t xDataLengthBytes,
-                                  TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferSendImpl                     \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferSend_Unpriv                      \n"
-            " MPU_xStreamBufferSend_Priv:                           \n"
-            "     b MPU_xStreamBufferSendImpl                       \n"
-            " MPU_xStreamBufferSend_Unpriv:                         \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                      const void * pvTxData,
+                                      size_t xDataLengthBytes,
+                                      TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                      const void * pvTxData,
+                                      size_t xDataLengthBytes,
+                                      TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferSendImpl                     \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferSend_Unpriv                      \n"
+                " MPU_xStreamBufferSend_Priv:                           \n"
+                "     b MPU_xStreamBufferSendImpl                       \n"
+                " MPU_xStreamBufferSend_Unpriv:                         \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                     void * pvRxData,
-                                     size_t xBufferLengthBytes,
-                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                     void * pvRxData,
-                                     size_t xBufferLengthBytes,
-                                     TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferReceiveImpl                  \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferReceive_Unpriv                   \n"
-            " MPU_xStreamBufferReceive_Priv:                        \n"
-            "     b MPU_xStreamBufferReceiveImpl                    \n"
-            " MPU_xStreamBufferReceive_Unpriv:                      \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                         void * pvRxData,
+                                         size_t xBufferLengthBytes,
+                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                         void * pvRxData,
+                                         size_t xBufferLengthBytes,
+                                         TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferReceiveImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferReceive_Unpriv                   \n"
+                " MPU_xStreamBufferReceive_Priv:                        \n"
+                "     b MPU_xStreamBufferReceiveImpl                    \n"
+                " MPU_xStreamBufferReceive_Unpriv:                      \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferIsFullImpl                   \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
-            " MPU_xStreamBufferIsFull_Priv:                         \n"
-            "     b MPU_xStreamBufferIsFullImpl                     \n"
-            " MPU_xStreamBufferIsFull_Unpriv:                       \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
-        );
-    }
+        BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferIsFullImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
+                " MPU_xStreamBufferIsFull_Priv:                         \n"
+                "     b MPU_xStreamBufferIsFullImpl                     \n"
+                " MPU_xStreamBufferIsFull_Unpriv:                       \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
-            " MPU_xStreamBufferIsEmpty_Priv:                        \n"
-            "     b MPU_xStreamBufferIsEmptyImpl                    \n"
-            " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
-        );
-    }
+        BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
+                " MPU_xStreamBufferIsEmpty_Priv:                        \n"
+                "     b MPU_xStreamBufferIsEmptyImpl                    \n"
+                " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
-            " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
-            "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
-            " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
+                " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
+                "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
+                " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
-            " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
-            "     b MPU_xStreamBufferBytesAvailableImpl             \n"
-            " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
+                " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
+                "     b MPU_xStreamBufferBytesAvailableImpl             \n"
+                " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                                 size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                                 size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
-            " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
-            "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
-            " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
-        );
-    }
+        BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                     size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                     size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
+                " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
+                "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
+                " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
-            " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
-            "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
-            " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
+                " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
+                "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
+                " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.c
index 4f66448f9..6642c9e20 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.c
@@ -1634,113 +1634,129 @@
     #endif /* if ( configUSE_TIMERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupWaitBitsImpl                   \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
-            " MPU_xEventGroupWaitBits_Priv:                         \n"
-            "     b MPU_xEventGroupWaitBitsImpl                     \n"
-            " MPU_xEventGroupWaitBits_Unpriv:                       \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
-        );
-    }
+        EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupWaitBitsImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
+                " MPU_xEventGroupWaitBits_Priv:                         \n"
+                "     b MPU_xEventGroupWaitBitsImpl                     \n"
+                " MPU_xEventGroupWaitBits_Unpriv:                       \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                          const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                          const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupClearBitsImpl                  \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xEventGroupClearBits_Unpriv                   \n"
-            " MPU_xEventGroupClearBits_Priv:                        \n"
-            "     b MPU_xEventGroupClearBitsImpl                    \n"
-            " MPU_xEventGroupClearBits_Unpriv:                      \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
-        );
-    }
+        EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                              const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                              const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupClearBitsImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xEventGroupClearBits_Unpriv                   \n"
+                " MPU_xEventGroupClearBits_Priv:                        \n"
+                "     b MPU_xEventGroupClearBitsImpl                    \n"
+                " MPU_xEventGroupClearBits_Unpriv:                      \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                        const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                        const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupSetBitsImpl                    \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xEventGroupSetBits_Unpriv                     \n"
-            " MPU_xEventGroupSetBits_Priv:                          \n"
-            "     b MPU_xEventGroupSetBitsImpl                      \n"
-            " MPU_xEventGroupSetBits_Unpriv:                        \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
-        );
-    }
+        EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                            const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                            const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupSetBitsImpl                    \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xEventGroupSetBits_Unpriv                     \n"
+                " MPU_xEventGroupSetBits_Priv:                          \n"
+                "     b MPU_xEventGroupSetBitsImpl                      \n"
+                " MPU_xEventGroupSetBits_Unpriv:                        \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                     const EventBits_t uxBitsToSet,
-                                     const EventBits_t uxBitsToWaitFor,
-                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                     const EventBits_t uxBitsToSet,
-                                     const EventBits_t uxBitsToWaitFor,
-                                     TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupSyncImpl                       \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xEventGroupSync_Unpriv                        \n"
-            " MPU_xEventGroupSync_Priv:                             \n"
-            "     b MPU_xEventGroupSyncImpl                         \n"
-            " MPU_xEventGroupSync_Unpriv:                           \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
-        );
-    }
+        EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToSet,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToSet,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupSyncImpl                       \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xEventGroupSync_Unpriv                        \n"
+                " MPU_xEventGroupSync_Priv:                             \n"
+                "     b MPU_xEventGroupSyncImpl                         \n"
+                " MPU_xEventGroupSync_Unpriv:                           \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    #if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
 
         UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
@@ -1765,10 +1781,10 @@
             );
         }
 
-    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-    #if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
 
         void MPU_vEventGroupSetNumber( void * xEventGroup,
                                        UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
@@ -1795,213 +1811,245 @@
             );
         }
 
-    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                                  const void * pvTxData,
-                                  size_t xDataLengthBytes,
-                                  TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                                  const void * pvTxData,
-                                  size_t xDataLengthBytes,
-                                  TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferSendImpl                     \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferSend_Unpriv                      \n"
-            " MPU_xStreamBufferSend_Priv:                           \n"
-            "     b MPU_xStreamBufferSendImpl                       \n"
-            " MPU_xStreamBufferSend_Unpriv:                         \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                      const void * pvTxData,
+                                      size_t xDataLengthBytes,
+                                      TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                      const void * pvTxData,
+                                      size_t xDataLengthBytes,
+                                      TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferSendImpl                     \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferSend_Unpriv                      \n"
+                " MPU_xStreamBufferSend_Priv:                           \n"
+                "     b MPU_xStreamBufferSendImpl                       \n"
+                " MPU_xStreamBufferSend_Unpriv:                         \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                     void * pvRxData,
-                                     size_t xBufferLengthBytes,
-                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                     void * pvRxData,
-                                     size_t xBufferLengthBytes,
-                                     TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferReceiveImpl                  \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferReceive_Unpriv                   \n"
-            " MPU_xStreamBufferReceive_Priv:                        \n"
-            "     b MPU_xStreamBufferReceiveImpl                    \n"
-            " MPU_xStreamBufferReceive_Unpriv:                      \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                         void * pvRxData,
+                                         size_t xBufferLengthBytes,
+                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                         void * pvRxData,
+                                         size_t xBufferLengthBytes,
+                                         TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferReceiveImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferReceive_Unpriv                   \n"
+                " MPU_xStreamBufferReceive_Priv:                        \n"
+                "     b MPU_xStreamBufferReceiveImpl                    \n"
+                " MPU_xStreamBufferReceive_Unpriv:                      \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferIsFullImpl                   \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
-            " MPU_xStreamBufferIsFull_Priv:                         \n"
-            "     b MPU_xStreamBufferIsFullImpl                     \n"
-            " MPU_xStreamBufferIsFull_Unpriv:                       \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
-        );
-    }
+        BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferIsFullImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
+                " MPU_xStreamBufferIsFull_Priv:                         \n"
+                "     b MPU_xStreamBufferIsFullImpl                     \n"
+                " MPU_xStreamBufferIsFull_Unpriv:                       \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
-            " MPU_xStreamBufferIsEmpty_Priv:                        \n"
-            "     b MPU_xStreamBufferIsEmptyImpl                    \n"
-            " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
-        );
-    }
+        BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
+                " MPU_xStreamBufferIsEmpty_Priv:                        \n"
+                "     b MPU_xStreamBufferIsEmptyImpl                    \n"
+                " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
-            " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
-            "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
-            " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
+                " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
+                "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
+                " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
-            " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
-            "     b MPU_xStreamBufferBytesAvailableImpl             \n"
-            " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
+                " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
+                "     b MPU_xStreamBufferBytesAvailableImpl             \n"
+                " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                                 size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                                 size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
-            " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
-            "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
-            " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
-        );
-    }
+        BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                     size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                     size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
+                " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
+                "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
+                " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
-            " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
-            "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
-            " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
+                " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
+                "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
+                " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
diff --git a/portable/GCC/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.c
index 4f66448f9..02229d964 100644
--- a/portable/GCC/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.c
@@ -1634,113 +1634,130 @@
     #endif /* if ( configUSE_TIMERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupWaitBitsImpl                   \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
-            " MPU_xEventGroupWaitBits_Priv:                         \n"
-            "     b MPU_xEventGroupWaitBitsImpl                     \n"
-            " MPU_xEventGroupWaitBits_Unpriv:                       \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
-        );
-    }
+        EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupWaitBitsImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
+                " MPU_xEventGroupWaitBits_Priv:                         \n"
+                "     b MPU_xEventGroupWaitBitsImpl                     \n"
+                " MPU_xEventGroupWaitBits_Unpriv:                       \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                          const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                          const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupClearBitsImpl                  \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xEventGroupClearBits_Unpriv                   \n"
-            " MPU_xEventGroupClearBits_Priv:                        \n"
-            "     b MPU_xEventGroupClearBitsImpl                    \n"
-            " MPU_xEventGroupClearBits_Unpriv:                      \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
-        );
-    }
+        EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                              const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                              const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupClearBitsImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xEventGroupClearBits_Unpriv                   \n"
+                " MPU_xEventGroupClearBits_Priv:                        \n"
+                "     b MPU_xEventGroupClearBitsImpl                    \n"
+                " MPU_xEventGroupClearBits_Unpriv:                      \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                        const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
+
+        EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                            const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                            const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupSetBitsImpl                    \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xEventGroupSetBits_Unpriv                     \n"
+                " MPU_xEventGroupSetBits_Priv:                          \n"
+                "     b MPU_xEventGroupSetBitsImpl                      \n"
+                " MPU_xEventGroupSetBits_Unpriv:                        \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 
-    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                        const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupSetBitsImpl                    \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xEventGroupSetBits_Unpriv                     \n"
-            " MPU_xEventGroupSetBits_Priv:                          \n"
-            "     b MPU_xEventGroupSetBitsImpl                      \n"
-            " MPU_xEventGroupSetBits_Unpriv:                        \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
-        );
-    }
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                     const EventBits_t uxBitsToSet,
-                                     const EventBits_t uxBitsToWaitFor,
-                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                     const EventBits_t uxBitsToSet,
-                                     const EventBits_t uxBitsToWaitFor,
-                                     TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupSyncImpl                       \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xEventGroupSync_Unpriv                        \n"
-            " MPU_xEventGroupSync_Priv:                             \n"
-            "     b MPU_xEventGroupSyncImpl                         \n"
-            " MPU_xEventGroupSync_Unpriv:                           \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
-        );
-    }
+        EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToSet,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToSet,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupSyncImpl                       \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xEventGroupSync_Unpriv                        \n"
+                " MPU_xEventGroupSync_Priv:                             \n"
+                "     b MPU_xEventGroupSyncImpl                         \n"
+                " MPU_xEventGroupSync_Unpriv:                           \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    #if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
 
         UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
@@ -1765,10 +1782,10 @@
             );
         }
 
-    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-    #if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
 
         void MPU_vEventGroupSetNumber( void * xEventGroup,
                                        UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
@@ -1795,213 +1812,245 @@
             );
         }
 
-    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                                  const void * pvTxData,
-                                  size_t xDataLengthBytes,
-                                  TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                                  const void * pvTxData,
-                                  size_t xDataLengthBytes,
-                                  TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferSendImpl                     \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferSend_Unpriv                      \n"
-            " MPU_xStreamBufferSend_Priv:                           \n"
-            "     b MPU_xStreamBufferSendImpl                       \n"
-            " MPU_xStreamBufferSend_Unpriv:                         \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                      const void * pvTxData,
+                                      size_t xDataLengthBytes,
+                                      TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                      const void * pvTxData,
+                                      size_t xDataLengthBytes,
+                                      TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferSendImpl                     \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferSend_Unpriv                      \n"
+                " MPU_xStreamBufferSend_Priv:                           \n"
+                "     b MPU_xStreamBufferSendImpl                       \n"
+                " MPU_xStreamBufferSend_Unpriv:                         \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                     void * pvRxData,
-                                     size_t xBufferLengthBytes,
-                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                     void * pvRxData,
-                                     size_t xBufferLengthBytes,
-                                     TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferReceiveImpl                  \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferReceive_Unpriv                   \n"
-            " MPU_xStreamBufferReceive_Priv:                        \n"
-            "     b MPU_xStreamBufferReceiveImpl                    \n"
-            " MPU_xStreamBufferReceive_Unpriv:                      \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                         void * pvRxData,
+                                         size_t xBufferLengthBytes,
+                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                         void * pvRxData,
+                                         size_t xBufferLengthBytes,
+                                         TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferReceiveImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferReceive_Unpriv                   \n"
+                " MPU_xStreamBufferReceive_Priv:                        \n"
+                "     b MPU_xStreamBufferReceiveImpl                    \n"
+                " MPU_xStreamBufferReceive_Unpriv:                      \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferIsFullImpl                   \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
-            " MPU_xStreamBufferIsFull_Priv:                         \n"
-            "     b MPU_xStreamBufferIsFullImpl                     \n"
-            " MPU_xStreamBufferIsFull_Unpriv:                       \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
-        );
-    }
+        BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferIsFullImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
+                " MPU_xStreamBufferIsFull_Priv:                         \n"
+                "     b MPU_xStreamBufferIsFullImpl                     \n"
+                " MPU_xStreamBufferIsFull_Unpriv:                       \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
-            " MPU_xStreamBufferIsEmpty_Priv:                        \n"
-            "     b MPU_xStreamBufferIsEmptyImpl                    \n"
-            " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
-        );
-    }
+        BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
+                " MPU_xStreamBufferIsEmpty_Priv:                        \n"
+                "     b MPU_xStreamBufferIsEmptyImpl                    \n"
+                " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
-            " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
-            "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
-            " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
+                " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
+                "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
+                " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
-            " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
-            "     b MPU_xStreamBufferBytesAvailableImpl             \n"
-            " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
+                " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
+                "     b MPU_xStreamBufferBytesAvailableImpl             \n"
+                " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                                 size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                                 size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
-            " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
-            "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
-            " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
-        );
-    }
+        BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                     size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                     size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
+                " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
+                "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
+                " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
-            " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
-            "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
-            " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
+                " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
+                "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
+                " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.c
index 4f66448f9..6642c9e20 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.c
@@ -1634,113 +1634,129 @@
     #endif /* if ( configUSE_TIMERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupWaitBitsImpl                   \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
-            " MPU_xEventGroupWaitBits_Priv:                         \n"
-            "     b MPU_xEventGroupWaitBitsImpl                     \n"
-            " MPU_xEventGroupWaitBits_Unpriv:                       \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
-        );
-    }
+        EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupWaitBitsImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
+                " MPU_xEventGroupWaitBits_Priv:                         \n"
+                "     b MPU_xEventGroupWaitBitsImpl                     \n"
+                " MPU_xEventGroupWaitBits_Unpriv:                       \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                          const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                          const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupClearBitsImpl                  \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xEventGroupClearBits_Unpriv                   \n"
-            " MPU_xEventGroupClearBits_Priv:                        \n"
-            "     b MPU_xEventGroupClearBitsImpl                    \n"
-            " MPU_xEventGroupClearBits_Unpriv:                      \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
-        );
-    }
+        EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                              const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                              const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupClearBitsImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xEventGroupClearBits_Unpriv                   \n"
+                " MPU_xEventGroupClearBits_Priv:                        \n"
+                "     b MPU_xEventGroupClearBitsImpl                    \n"
+                " MPU_xEventGroupClearBits_Unpriv:                      \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                        const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                        const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupSetBitsImpl                    \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xEventGroupSetBits_Unpriv                     \n"
-            " MPU_xEventGroupSetBits_Priv:                          \n"
-            "     b MPU_xEventGroupSetBitsImpl                      \n"
-            " MPU_xEventGroupSetBits_Unpriv:                        \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
-        );
-    }
+        EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                            const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                            const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupSetBitsImpl                    \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xEventGroupSetBits_Unpriv                     \n"
+                " MPU_xEventGroupSetBits_Priv:                          \n"
+                "     b MPU_xEventGroupSetBitsImpl                      \n"
+                " MPU_xEventGroupSetBits_Unpriv:                        \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                     const EventBits_t uxBitsToSet,
-                                     const EventBits_t uxBitsToWaitFor,
-                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                     const EventBits_t uxBitsToSet,
-                                     const EventBits_t uxBitsToWaitFor,
-                                     TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupSyncImpl                       \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xEventGroupSync_Unpriv                        \n"
-            " MPU_xEventGroupSync_Priv:                             \n"
-            "     b MPU_xEventGroupSyncImpl                         \n"
-            " MPU_xEventGroupSync_Unpriv:                           \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
-        );
-    }
+        EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToSet,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToSet,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupSyncImpl                       \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xEventGroupSync_Unpriv                        \n"
+                " MPU_xEventGroupSync_Priv:                             \n"
+                "     b MPU_xEventGroupSyncImpl                         \n"
+                " MPU_xEventGroupSync_Unpriv:                           \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    #if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
 
         UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
@@ -1765,10 +1781,10 @@
             );
         }
 
-    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-    #if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
 
         void MPU_vEventGroupSetNumber( void * xEventGroup,
                                        UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
@@ -1795,213 +1811,245 @@
             );
         }
 
-    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                                  const void * pvTxData,
-                                  size_t xDataLengthBytes,
-                                  TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                                  const void * pvTxData,
-                                  size_t xDataLengthBytes,
-                                  TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferSendImpl                     \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferSend_Unpriv                      \n"
-            " MPU_xStreamBufferSend_Priv:                           \n"
-            "     b MPU_xStreamBufferSendImpl                       \n"
-            " MPU_xStreamBufferSend_Unpriv:                         \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                      const void * pvTxData,
+                                      size_t xDataLengthBytes,
+                                      TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                      const void * pvTxData,
+                                      size_t xDataLengthBytes,
+                                      TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferSendImpl                     \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferSend_Unpriv                      \n"
+                " MPU_xStreamBufferSend_Priv:                           \n"
+                "     b MPU_xStreamBufferSendImpl                       \n"
+                " MPU_xStreamBufferSend_Unpriv:                         \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                     void * pvRxData,
-                                     size_t xBufferLengthBytes,
-                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                     void * pvRxData,
-                                     size_t xBufferLengthBytes,
-                                     TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferReceiveImpl                  \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferReceive_Unpriv                   \n"
-            " MPU_xStreamBufferReceive_Priv:                        \n"
-            "     b MPU_xStreamBufferReceiveImpl                    \n"
-            " MPU_xStreamBufferReceive_Unpriv:                      \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                         void * pvRxData,
+                                         size_t xBufferLengthBytes,
+                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                         void * pvRxData,
+                                         size_t xBufferLengthBytes,
+                                         TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferReceiveImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferReceive_Unpriv                   \n"
+                " MPU_xStreamBufferReceive_Priv:                        \n"
+                "     b MPU_xStreamBufferReceiveImpl                    \n"
+                " MPU_xStreamBufferReceive_Unpriv:                      \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferIsFullImpl                   \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
-            " MPU_xStreamBufferIsFull_Priv:                         \n"
-            "     b MPU_xStreamBufferIsFullImpl                     \n"
-            " MPU_xStreamBufferIsFull_Unpriv:                       \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
-        );
-    }
+        BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferIsFullImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
+                " MPU_xStreamBufferIsFull_Priv:                         \n"
+                "     b MPU_xStreamBufferIsFullImpl                     \n"
+                " MPU_xStreamBufferIsFull_Unpriv:                       \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
-            " MPU_xStreamBufferIsEmpty_Priv:                        \n"
-            "     b MPU_xStreamBufferIsEmptyImpl                    \n"
-            " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
-        );
-    }
+        BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
+                " MPU_xStreamBufferIsEmpty_Priv:                        \n"
+                "     b MPU_xStreamBufferIsEmptyImpl                    \n"
+                " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
-            " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
-            "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
-            " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
+                " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
+                "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
+                " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
-            " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
-            "     b MPU_xStreamBufferBytesAvailableImpl             \n"
-            " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
+                " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
+                "     b MPU_xStreamBufferBytesAvailableImpl             \n"
+                " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                                 size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                                 size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
-            " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
-            "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
-            " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
-        );
-    }
+        BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                     size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                     size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
+                " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
+                "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
+                " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
-            " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
-            "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
-            " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
+                " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
+                "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
+                " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
diff --git a/portable/GCC/ARM_CM3_MPU/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM3_MPU/mpu_wrappers_v2_asm.c
index feb3e3426..71bb6602e 100644
--- a/portable/GCC/ARM_CM3_MPU/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM3_MPU/mpu_wrappers_v2_asm.c
@@ -1634,113 +1634,133 @@
     #endif /* if ( configUSE_TIMERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupWaitBitsImpl                   \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
-            " MPU_xEventGroupWaitBits_Priv:                         \n"
-            "     b MPU_xEventGroupWaitBitsImpl                     \n"
-            " MPU_xEventGroupWaitBits_Unpriv:                       \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
-        );
-    }
+        EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupWaitBitsImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
+                " MPU_xEventGroupWaitBits_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xEventGroupWaitBitsImpl                     \n"
+                " MPU_xEventGroupWaitBits_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                          const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                          const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupClearBitsImpl                  \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xEventGroupClearBits_Unpriv                   \n"
-            " MPU_xEventGroupClearBits_Priv:                        \n"
-            "     b MPU_xEventGroupClearBitsImpl                    \n"
-            " MPU_xEventGroupClearBits_Unpriv:                      \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
-        );
-    }
+        EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                              const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                              const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupClearBitsImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xEventGroupClearBits_Unpriv                   \n"
+                " MPU_xEventGroupClearBits_Priv:                        \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xEventGroupClearBitsImpl                    \n"
+                " MPU_xEventGroupClearBits_Unpriv:                      \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                        const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                        const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupSetBitsImpl                    \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xEventGroupSetBits_Unpriv                     \n"
-            " MPU_xEventGroupSetBits_Priv:                          \n"
-            "     b MPU_xEventGroupSetBitsImpl                      \n"
-            " MPU_xEventGroupSetBits_Unpriv:                        \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
-        );
-    }
+        EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                            const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                            const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupSetBitsImpl                    \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xEventGroupSetBits_Unpriv                     \n"
+                " MPU_xEventGroupSetBits_Priv:                          \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xEventGroupSetBitsImpl                      \n"
+                " MPU_xEventGroupSetBits_Unpriv:                        \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                     const EventBits_t uxBitsToSet,
-                                     const EventBits_t uxBitsToWaitFor,
-                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                     const EventBits_t uxBitsToSet,
-                                     const EventBits_t uxBitsToWaitFor,
-                                     TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupSyncImpl                       \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xEventGroupSync_Unpriv                        \n"
-            " MPU_xEventGroupSync_Priv:                             \n"
-            "     b MPU_xEventGroupSyncImpl                         \n"
-            " MPU_xEventGroupSync_Unpriv:                           \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
-        );
-    }
+        EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToSet,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToSet,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupSyncImpl                       \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xEventGroupSync_Unpriv                        \n"
+                " MPU_xEventGroupSync_Priv:                             \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xEventGroupSyncImpl                         \n"
+                " MPU_xEventGroupSync_Unpriv:                           \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    #if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
 
         UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
@@ -1765,10 +1785,10 @@
             );
         }
 
-    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-    #if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
 
         void MPU_vEventGroupSetNumber( void * xEventGroup,
                                        UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
@@ -1795,213 +1815,253 @@
             );
         }
 
-    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                                  const void * pvTxData,
-                                  size_t xDataLengthBytes,
-                                  TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                                  const void * pvTxData,
-                                  size_t xDataLengthBytes,
-                                  TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferSendImpl                     \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferSend_Unpriv                      \n"
-            " MPU_xStreamBufferSend_Priv:                           \n"
-            "     b MPU_xStreamBufferSendImpl                       \n"
-            " MPU_xStreamBufferSend_Unpriv:                         \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                      const void * pvTxData,
+                                      size_t xDataLengthBytes,
+                                      TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                      const void * pvTxData,
+                                      size_t xDataLengthBytes,
+                                      TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferSendImpl                     \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xStreamBufferSend_Unpriv                      \n"
+                " MPU_xStreamBufferSend_Priv:                           \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xStreamBufferSendImpl                       \n"
+                " MPU_xStreamBufferSend_Unpriv:                         \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                     void * pvRxData,
-                                     size_t xBufferLengthBytes,
-                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                     void * pvRxData,
-                                     size_t xBufferLengthBytes,
-                                     TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferReceiveImpl                  \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferReceive_Unpriv                   \n"
-            " MPU_xStreamBufferReceive_Priv:                        \n"
-            "     b MPU_xStreamBufferReceiveImpl                    \n"
-            " MPU_xStreamBufferReceive_Unpriv:                      \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                         void * pvRxData,
+                                         size_t xBufferLengthBytes,
+                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                         void * pvRxData,
+                                         size_t xBufferLengthBytes,
+                                         TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferReceiveImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xStreamBufferReceive_Unpriv                   \n"
+                " MPU_xStreamBufferReceive_Priv:                        \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xStreamBufferReceiveImpl                    \n"
+                " MPU_xStreamBufferReceive_Unpriv:                      \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferIsFullImpl                   \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
-            " MPU_xStreamBufferIsFull_Priv:                         \n"
-            "     b MPU_xStreamBufferIsFullImpl                     \n"
-            " MPU_xStreamBufferIsFull_Unpriv:                       \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
-        );
-    }
+        BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferIsFullImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
+                " MPU_xStreamBufferIsFull_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xStreamBufferIsFullImpl                     \n"
+                " MPU_xStreamBufferIsFull_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
-            " MPU_xStreamBufferIsEmpty_Priv:                        \n"
-            "     b MPU_xStreamBufferIsEmptyImpl                    \n"
-            " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
-        );
-    }
+        BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
+                " MPU_xStreamBufferIsEmpty_Priv:                        \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xStreamBufferIsEmptyImpl                    \n"
+                " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
-            " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
-            "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
-            " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
+                " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
+                " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
-            " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
-            "     b MPU_xStreamBufferBytesAvailableImpl             \n"
-            " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
+                " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xStreamBufferBytesAvailableImpl             \n"
+                " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                                 size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                                 size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
-            " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
-            "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
-            " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
-        );
-    }
+        BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                     size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                     size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
+                " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
+                " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
-            " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
-            "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
-            " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
+                " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
+                " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
 #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
diff --git a/portable/GCC/ARM_CM4_MPU/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM4_MPU/mpu_wrappers_v2_asm.c
index feb3e3426..71bb6602e 100644
--- a/portable/GCC/ARM_CM4_MPU/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM4_MPU/mpu_wrappers_v2_asm.c
@@ -1634,113 +1634,133 @@
     #endif /* if ( configUSE_TIMERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupWaitBitsImpl                   \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
-            " MPU_xEventGroupWaitBits_Priv:                         \n"
-            "     b MPU_xEventGroupWaitBitsImpl                     \n"
-            " MPU_xEventGroupWaitBits_Unpriv:                       \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
-        );
-    }
+        EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupWaitBitsImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
+                " MPU_xEventGroupWaitBits_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xEventGroupWaitBitsImpl                     \n"
+                " MPU_xEventGroupWaitBits_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                          const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                          const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupClearBitsImpl                  \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xEventGroupClearBits_Unpriv                   \n"
-            " MPU_xEventGroupClearBits_Priv:                        \n"
-            "     b MPU_xEventGroupClearBitsImpl                    \n"
-            " MPU_xEventGroupClearBits_Unpriv:                      \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
-        );
-    }
+        EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                              const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                              const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupClearBitsImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xEventGroupClearBits_Unpriv                   \n"
+                " MPU_xEventGroupClearBits_Priv:                        \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xEventGroupClearBitsImpl                    \n"
+                " MPU_xEventGroupClearBits_Unpriv:                      \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                        const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                        const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupSetBitsImpl                    \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xEventGroupSetBits_Unpriv                     \n"
-            " MPU_xEventGroupSetBits_Priv:                          \n"
-            "     b MPU_xEventGroupSetBitsImpl                      \n"
-            " MPU_xEventGroupSetBits_Unpriv:                        \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
-        );
-    }
+        EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                            const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                            const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupSetBitsImpl                    \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xEventGroupSetBits_Unpriv                     \n"
+                " MPU_xEventGroupSetBits_Priv:                          \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xEventGroupSetBitsImpl                      \n"
+                " MPU_xEventGroupSetBits_Unpriv:                        \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                     const EventBits_t uxBitsToSet,
-                                     const EventBits_t uxBitsToWaitFor,
-                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                     const EventBits_t uxBitsToSet,
-                                     const EventBits_t uxBitsToWaitFor,
-                                     TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupSyncImpl                       \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xEventGroupSync_Unpriv                        \n"
-            " MPU_xEventGroupSync_Priv:                             \n"
-            "     b MPU_xEventGroupSyncImpl                         \n"
-            " MPU_xEventGroupSync_Unpriv:                           \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
-        );
-    }
+        EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToSet,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToSet,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupSyncImpl                       \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xEventGroupSync_Unpriv                        \n"
+                " MPU_xEventGroupSync_Priv:                             \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xEventGroupSyncImpl                         \n"
+                " MPU_xEventGroupSync_Unpriv:                           \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    #if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
 
         UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
@@ -1765,10 +1785,10 @@
             );
         }
 
-    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-    #if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
 
         void MPU_vEventGroupSetNumber( void * xEventGroup,
                                        UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
@@ -1795,213 +1815,253 @@
             );
         }
 
-    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                                  const void * pvTxData,
-                                  size_t xDataLengthBytes,
-                                  TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                                  const void * pvTxData,
-                                  size_t xDataLengthBytes,
-                                  TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferSendImpl                     \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferSend_Unpriv                      \n"
-            " MPU_xStreamBufferSend_Priv:                           \n"
-            "     b MPU_xStreamBufferSendImpl                       \n"
-            " MPU_xStreamBufferSend_Unpriv:                         \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                      const void * pvTxData,
+                                      size_t xDataLengthBytes,
+                                      TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                      const void * pvTxData,
+                                      size_t xDataLengthBytes,
+                                      TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferSendImpl                     \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xStreamBufferSend_Unpriv                      \n"
+                " MPU_xStreamBufferSend_Priv:                           \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xStreamBufferSendImpl                       \n"
+                " MPU_xStreamBufferSend_Unpriv:                         \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                     void * pvRxData,
-                                     size_t xBufferLengthBytes,
-                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                     void * pvRxData,
-                                     size_t xBufferLengthBytes,
-                                     TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferReceiveImpl                  \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferReceive_Unpriv                   \n"
-            " MPU_xStreamBufferReceive_Priv:                        \n"
-            "     b MPU_xStreamBufferReceiveImpl                    \n"
-            " MPU_xStreamBufferReceive_Unpriv:                      \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                         void * pvRxData,
+                                         size_t xBufferLengthBytes,
+                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                         void * pvRxData,
+                                         size_t xBufferLengthBytes,
+                                         TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferReceiveImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xStreamBufferReceive_Unpriv                   \n"
+                " MPU_xStreamBufferReceive_Priv:                        \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xStreamBufferReceiveImpl                    \n"
+                " MPU_xStreamBufferReceive_Unpriv:                      \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferIsFullImpl                   \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
-            " MPU_xStreamBufferIsFull_Priv:                         \n"
-            "     b MPU_xStreamBufferIsFullImpl                     \n"
-            " MPU_xStreamBufferIsFull_Unpriv:                       \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
-        );
-    }
+        BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferIsFullImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
+                " MPU_xStreamBufferIsFull_Priv:                         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xStreamBufferIsFullImpl                     \n"
+                " MPU_xStreamBufferIsFull_Unpriv:                       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
-            " MPU_xStreamBufferIsEmpty_Priv:                        \n"
-            "     b MPU_xStreamBufferIsEmptyImpl                    \n"
-            " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
-        );
-    }
+        BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
+                " MPU_xStreamBufferIsEmpty_Priv:                        \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xStreamBufferIsEmptyImpl                    \n"
+                " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
-            " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
-            "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
-            " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
+                " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
+                " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
-            " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
-            "     b MPU_xStreamBufferBytesAvailableImpl             \n"
-            " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
+                " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xStreamBufferBytesAvailableImpl             \n"
+                " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                                 size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                                 size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
-            " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
-            "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
-            " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
-        );
-    }
+        BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                     size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                     size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
+                " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
+                " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
-            " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
-            "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
-            " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
+                " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
+                "     pop {r0}                                          \n"
+                "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
+                " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
+                "     pop {r0}                                          \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
 #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
diff --git a/portable/GCC/ARM_CM55/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM55/non_secure/mpu_wrappers_v2_asm.c
index 4f66448f9..02229d964 100644
--- a/portable/GCC/ARM_CM55/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM55/non_secure/mpu_wrappers_v2_asm.c
@@ -1634,113 +1634,130 @@
     #endif /* if ( configUSE_TIMERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupWaitBitsImpl                   \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
-            " MPU_xEventGroupWaitBits_Priv:                         \n"
-            "     b MPU_xEventGroupWaitBitsImpl                     \n"
-            " MPU_xEventGroupWaitBits_Unpriv:                       \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
-        );
-    }
+        EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupWaitBitsImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
+                " MPU_xEventGroupWaitBits_Priv:                         \n"
+                "     b MPU_xEventGroupWaitBitsImpl                     \n"
+                " MPU_xEventGroupWaitBits_Unpriv:                       \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                          const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                          const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupClearBitsImpl                  \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xEventGroupClearBits_Unpriv                   \n"
-            " MPU_xEventGroupClearBits_Priv:                        \n"
-            "     b MPU_xEventGroupClearBitsImpl                    \n"
-            " MPU_xEventGroupClearBits_Unpriv:                      \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
-        );
-    }
+        EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                              const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                              const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupClearBitsImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xEventGroupClearBits_Unpriv                   \n"
+                " MPU_xEventGroupClearBits_Priv:                        \n"
+                "     b MPU_xEventGroupClearBitsImpl                    \n"
+                " MPU_xEventGroupClearBits_Unpriv:                      \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                        const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
+
+        EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                            const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                            const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupSetBitsImpl                    \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xEventGroupSetBits_Unpriv                     \n"
+                " MPU_xEventGroupSetBits_Priv:                          \n"
+                "     b MPU_xEventGroupSetBitsImpl                      \n"
+                " MPU_xEventGroupSetBits_Unpriv:                        \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 
-    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                        const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupSetBitsImpl                    \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xEventGroupSetBits_Unpriv                     \n"
-            " MPU_xEventGroupSetBits_Priv:                          \n"
-            "     b MPU_xEventGroupSetBitsImpl                      \n"
-            " MPU_xEventGroupSetBits_Unpriv:                        \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
-        );
-    }
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                     const EventBits_t uxBitsToSet,
-                                     const EventBits_t uxBitsToWaitFor,
-                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                     const EventBits_t uxBitsToSet,
-                                     const EventBits_t uxBitsToWaitFor,
-                                     TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupSyncImpl                       \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xEventGroupSync_Unpriv                        \n"
-            " MPU_xEventGroupSync_Priv:                             \n"
-            "     b MPU_xEventGroupSyncImpl                         \n"
-            " MPU_xEventGroupSync_Unpriv:                           \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
-        );
-    }
+        EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToSet,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToSet,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupSyncImpl                       \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xEventGroupSync_Unpriv                        \n"
+                " MPU_xEventGroupSync_Priv:                             \n"
+                "     b MPU_xEventGroupSyncImpl                         \n"
+                " MPU_xEventGroupSync_Unpriv:                           \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    #if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
 
         UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
@@ -1765,10 +1782,10 @@
             );
         }
 
-    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-    #if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
 
         void MPU_vEventGroupSetNumber( void * xEventGroup,
                                        UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
@@ -1795,213 +1812,245 @@
             );
         }
 
-    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                                  const void * pvTxData,
-                                  size_t xDataLengthBytes,
-                                  TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                                  const void * pvTxData,
-                                  size_t xDataLengthBytes,
-                                  TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferSendImpl                     \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferSend_Unpriv                      \n"
-            " MPU_xStreamBufferSend_Priv:                           \n"
-            "     b MPU_xStreamBufferSendImpl                       \n"
-            " MPU_xStreamBufferSend_Unpriv:                         \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                      const void * pvTxData,
+                                      size_t xDataLengthBytes,
+                                      TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                      const void * pvTxData,
+                                      size_t xDataLengthBytes,
+                                      TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferSendImpl                     \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferSend_Unpriv                      \n"
+                " MPU_xStreamBufferSend_Priv:                           \n"
+                "     b MPU_xStreamBufferSendImpl                       \n"
+                " MPU_xStreamBufferSend_Unpriv:                         \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                     void * pvRxData,
-                                     size_t xBufferLengthBytes,
-                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                     void * pvRxData,
-                                     size_t xBufferLengthBytes,
-                                     TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferReceiveImpl                  \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferReceive_Unpriv                   \n"
-            " MPU_xStreamBufferReceive_Priv:                        \n"
-            "     b MPU_xStreamBufferReceiveImpl                    \n"
-            " MPU_xStreamBufferReceive_Unpriv:                      \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                         void * pvRxData,
+                                         size_t xBufferLengthBytes,
+                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                         void * pvRxData,
+                                         size_t xBufferLengthBytes,
+                                         TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferReceiveImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferReceive_Unpriv                   \n"
+                " MPU_xStreamBufferReceive_Priv:                        \n"
+                "     b MPU_xStreamBufferReceiveImpl                    \n"
+                " MPU_xStreamBufferReceive_Unpriv:                      \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferIsFullImpl                   \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
-            " MPU_xStreamBufferIsFull_Priv:                         \n"
-            "     b MPU_xStreamBufferIsFullImpl                     \n"
-            " MPU_xStreamBufferIsFull_Unpriv:                       \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
-        );
-    }
+        BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferIsFullImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
+                " MPU_xStreamBufferIsFull_Priv:                         \n"
+                "     b MPU_xStreamBufferIsFullImpl                     \n"
+                " MPU_xStreamBufferIsFull_Unpriv:                       \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
-            " MPU_xStreamBufferIsEmpty_Priv:                        \n"
-            "     b MPU_xStreamBufferIsEmptyImpl                    \n"
-            " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
-        );
-    }
+        BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
+                " MPU_xStreamBufferIsEmpty_Priv:                        \n"
+                "     b MPU_xStreamBufferIsEmptyImpl                    \n"
+                " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
-            " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
-            "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
-            " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
+                " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
+                "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
+                " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
-            " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
-            "     b MPU_xStreamBufferBytesAvailableImpl             \n"
-            " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
+                " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
+                "     b MPU_xStreamBufferBytesAvailableImpl             \n"
+                " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                                 size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                                 size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
-            " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
-            "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
-            " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
-        );
-    }
+        BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                     size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                     size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
+                " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
+                "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
+                " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
-            " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
-            "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
-            " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
+                " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
+                "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
+                " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.c
index 4f66448f9..6642c9e20 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.c
@@ -1634,113 +1634,129 @@
     #endif /* if ( configUSE_TIMERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupWaitBitsImpl                   \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
-            " MPU_xEventGroupWaitBits_Priv:                         \n"
-            "     b MPU_xEventGroupWaitBitsImpl                     \n"
-            " MPU_xEventGroupWaitBits_Unpriv:                       \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
-        );
-    }
+        EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupWaitBitsImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
+                " MPU_xEventGroupWaitBits_Priv:                         \n"
+                "     b MPU_xEventGroupWaitBitsImpl                     \n"
+                " MPU_xEventGroupWaitBits_Unpriv:                       \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                          const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                          const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupClearBitsImpl                  \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xEventGroupClearBits_Unpriv                   \n"
-            " MPU_xEventGroupClearBits_Priv:                        \n"
-            "     b MPU_xEventGroupClearBitsImpl                    \n"
-            " MPU_xEventGroupClearBits_Unpriv:                      \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
-        );
-    }
+        EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                              const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                              const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupClearBitsImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xEventGroupClearBits_Unpriv                   \n"
+                " MPU_xEventGroupClearBits_Priv:                        \n"
+                "     b MPU_xEventGroupClearBitsImpl                    \n"
+                " MPU_xEventGroupClearBits_Unpriv:                      \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                        const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                        const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupSetBitsImpl                    \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xEventGroupSetBits_Unpriv                     \n"
-            " MPU_xEventGroupSetBits_Priv:                          \n"
-            "     b MPU_xEventGroupSetBitsImpl                      \n"
-            " MPU_xEventGroupSetBits_Unpriv:                        \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
-        );
-    }
+        EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                            const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                            const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupSetBitsImpl                    \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xEventGroupSetBits_Unpriv                     \n"
+                " MPU_xEventGroupSetBits_Priv:                          \n"
+                "     b MPU_xEventGroupSetBitsImpl                      \n"
+                " MPU_xEventGroupSetBits_Unpriv:                        \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                     const EventBits_t uxBitsToSet,
-                                     const EventBits_t uxBitsToWaitFor,
-                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                     const EventBits_t uxBitsToSet,
-                                     const EventBits_t uxBitsToWaitFor,
-                                     TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupSyncImpl                       \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xEventGroupSync_Unpriv                        \n"
-            " MPU_xEventGroupSync_Priv:                             \n"
-            "     b MPU_xEventGroupSyncImpl                         \n"
-            " MPU_xEventGroupSync_Unpriv:                           \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
-        );
-    }
+        EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToSet,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToSet,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupSyncImpl                       \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xEventGroupSync_Unpriv                        \n"
+                " MPU_xEventGroupSync_Priv:                             \n"
+                "     b MPU_xEventGroupSyncImpl                         \n"
+                " MPU_xEventGroupSync_Unpriv:                           \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    #if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
 
         UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
@@ -1765,10 +1781,10 @@
             );
         }
 
-    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-    #if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
 
         void MPU_vEventGroupSetNumber( void * xEventGroup,
                                        UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
@@ -1795,213 +1811,245 @@
             );
         }
 
-    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                                  const void * pvTxData,
-                                  size_t xDataLengthBytes,
-                                  TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                                  const void * pvTxData,
-                                  size_t xDataLengthBytes,
-                                  TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferSendImpl                     \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferSend_Unpriv                      \n"
-            " MPU_xStreamBufferSend_Priv:                           \n"
-            "     b MPU_xStreamBufferSendImpl                       \n"
-            " MPU_xStreamBufferSend_Unpriv:                         \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                      const void * pvTxData,
+                                      size_t xDataLengthBytes,
+                                      TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                      const void * pvTxData,
+                                      size_t xDataLengthBytes,
+                                      TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferSendImpl                     \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferSend_Unpriv                      \n"
+                " MPU_xStreamBufferSend_Priv:                           \n"
+                "     b MPU_xStreamBufferSendImpl                       \n"
+                " MPU_xStreamBufferSend_Unpriv:                         \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                     void * pvRxData,
-                                     size_t xBufferLengthBytes,
-                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                     void * pvRxData,
-                                     size_t xBufferLengthBytes,
-                                     TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferReceiveImpl                  \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferReceive_Unpriv                   \n"
-            " MPU_xStreamBufferReceive_Priv:                        \n"
-            "     b MPU_xStreamBufferReceiveImpl                    \n"
-            " MPU_xStreamBufferReceive_Unpriv:                      \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                         void * pvRxData,
+                                         size_t xBufferLengthBytes,
+                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                         void * pvRxData,
+                                         size_t xBufferLengthBytes,
+                                         TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferReceiveImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferReceive_Unpriv                   \n"
+                " MPU_xStreamBufferReceive_Priv:                        \n"
+                "     b MPU_xStreamBufferReceiveImpl                    \n"
+                " MPU_xStreamBufferReceive_Unpriv:                      \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferIsFullImpl                   \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
-            " MPU_xStreamBufferIsFull_Priv:                         \n"
-            "     b MPU_xStreamBufferIsFullImpl                     \n"
-            " MPU_xStreamBufferIsFull_Unpriv:                       \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
-        );
-    }
+        BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferIsFullImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
+                " MPU_xStreamBufferIsFull_Priv:                         \n"
+                "     b MPU_xStreamBufferIsFullImpl                     \n"
+                " MPU_xStreamBufferIsFull_Unpriv:                       \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
-            " MPU_xStreamBufferIsEmpty_Priv:                        \n"
-            "     b MPU_xStreamBufferIsEmptyImpl                    \n"
-            " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
-        );
-    }
+        BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
+                " MPU_xStreamBufferIsEmpty_Priv:                        \n"
+                "     b MPU_xStreamBufferIsEmptyImpl                    \n"
+                " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
-            " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
-            "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
-            " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
+                " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
+                "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
+                " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
-            " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
-            "     b MPU_xStreamBufferBytesAvailableImpl             \n"
-            " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
+                " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
+                "     b MPU_xStreamBufferBytesAvailableImpl             \n"
+                " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                                 size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                                 size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
-            " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
-            "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
-            " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
-        );
-    }
+        BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                     size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                     size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
+                " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
+                "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
+                " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
-            " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
-            "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
-            " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
+                " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
+                "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
+                " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
diff --git a/portable/GCC/ARM_CM85/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM85/non_secure/mpu_wrappers_v2_asm.c
index 4f66448f9..02229d964 100644
--- a/portable/GCC/ARM_CM85/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM85/non_secure/mpu_wrappers_v2_asm.c
@@ -1634,113 +1634,130 @@
     #endif /* if ( configUSE_TIMERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupWaitBitsImpl                   \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
-            " MPU_xEventGroupWaitBits_Priv:                         \n"
-            "     b MPU_xEventGroupWaitBitsImpl                     \n"
-            " MPU_xEventGroupWaitBits_Unpriv:                       \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
-        );
-    }
+        EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupWaitBitsImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
+                " MPU_xEventGroupWaitBits_Priv:                         \n"
+                "     b MPU_xEventGroupWaitBitsImpl                     \n"
+                " MPU_xEventGroupWaitBits_Unpriv:                       \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                          const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                          const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupClearBitsImpl                  \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xEventGroupClearBits_Unpriv                   \n"
-            " MPU_xEventGroupClearBits_Priv:                        \n"
-            "     b MPU_xEventGroupClearBitsImpl                    \n"
-            " MPU_xEventGroupClearBits_Unpriv:                      \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
-        );
-    }
+        EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                              const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                              const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupClearBitsImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xEventGroupClearBits_Unpriv                   \n"
+                " MPU_xEventGroupClearBits_Priv:                        \n"
+                "     b MPU_xEventGroupClearBitsImpl                    \n"
+                " MPU_xEventGroupClearBits_Unpriv:                      \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                        const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
+
+        EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                            const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                            const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupSetBitsImpl                    \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xEventGroupSetBits_Unpriv                     \n"
+                " MPU_xEventGroupSetBits_Priv:                          \n"
+                "     b MPU_xEventGroupSetBitsImpl                      \n"
+                " MPU_xEventGroupSetBits_Unpriv:                        \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 
-    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                        const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupSetBitsImpl                    \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xEventGroupSetBits_Unpriv                     \n"
-            " MPU_xEventGroupSetBits_Priv:                          \n"
-            "     b MPU_xEventGroupSetBitsImpl                      \n"
-            " MPU_xEventGroupSetBits_Unpriv:                        \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
-        );
-    }
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                     const EventBits_t uxBitsToSet,
-                                     const EventBits_t uxBitsToWaitFor,
-                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                     const EventBits_t uxBitsToSet,
-                                     const EventBits_t uxBitsToWaitFor,
-                                     TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupSyncImpl                       \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xEventGroupSync_Unpriv                        \n"
-            " MPU_xEventGroupSync_Priv:                             \n"
-            "     b MPU_xEventGroupSyncImpl                         \n"
-            " MPU_xEventGroupSync_Unpriv:                           \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
-        );
-    }
+        EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToSet,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToSet,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupSyncImpl                       \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xEventGroupSync_Unpriv                        \n"
+                " MPU_xEventGroupSync_Priv:                             \n"
+                "     b MPU_xEventGroupSyncImpl                         \n"
+                " MPU_xEventGroupSync_Unpriv:                           \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    #if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
 
         UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
@@ -1765,10 +1782,10 @@
             );
         }
 
-    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-    #if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
 
         void MPU_vEventGroupSetNumber( void * xEventGroup,
                                        UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
@@ -1795,213 +1812,245 @@
             );
         }
 
-    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                                  const void * pvTxData,
-                                  size_t xDataLengthBytes,
-                                  TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                                  const void * pvTxData,
-                                  size_t xDataLengthBytes,
-                                  TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferSendImpl                     \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferSend_Unpriv                      \n"
-            " MPU_xStreamBufferSend_Priv:                           \n"
-            "     b MPU_xStreamBufferSendImpl                       \n"
-            " MPU_xStreamBufferSend_Unpriv:                         \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                      const void * pvTxData,
+                                      size_t xDataLengthBytes,
+                                      TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                      const void * pvTxData,
+                                      size_t xDataLengthBytes,
+                                      TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferSendImpl                     \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferSend_Unpriv                      \n"
+                " MPU_xStreamBufferSend_Priv:                           \n"
+                "     b MPU_xStreamBufferSendImpl                       \n"
+                " MPU_xStreamBufferSend_Unpriv:                         \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                     void * pvRxData,
-                                     size_t xBufferLengthBytes,
-                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                     void * pvRxData,
-                                     size_t xBufferLengthBytes,
-                                     TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferReceiveImpl                  \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferReceive_Unpriv                   \n"
-            " MPU_xStreamBufferReceive_Priv:                        \n"
-            "     b MPU_xStreamBufferReceiveImpl                    \n"
-            " MPU_xStreamBufferReceive_Unpriv:                      \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                         void * pvRxData,
+                                         size_t xBufferLengthBytes,
+                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                         void * pvRxData,
+                                         size_t xBufferLengthBytes,
+                                         TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferReceiveImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferReceive_Unpriv                   \n"
+                " MPU_xStreamBufferReceive_Priv:                        \n"
+                "     b MPU_xStreamBufferReceiveImpl                    \n"
+                " MPU_xStreamBufferReceive_Unpriv:                      \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferIsFullImpl                   \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
-            " MPU_xStreamBufferIsFull_Priv:                         \n"
-            "     b MPU_xStreamBufferIsFullImpl                     \n"
-            " MPU_xStreamBufferIsFull_Unpriv:                       \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
-        );
-    }
+        BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferIsFullImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
+                " MPU_xStreamBufferIsFull_Priv:                         \n"
+                "     b MPU_xStreamBufferIsFullImpl                     \n"
+                " MPU_xStreamBufferIsFull_Unpriv:                       \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
-            " MPU_xStreamBufferIsEmpty_Priv:                        \n"
-            "     b MPU_xStreamBufferIsEmptyImpl                    \n"
-            " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
-        );
-    }
+        BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
+                " MPU_xStreamBufferIsEmpty_Priv:                        \n"
+                "     b MPU_xStreamBufferIsEmptyImpl                    \n"
+                " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
-            " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
-            "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
-            " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
+                " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
+                "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
+                " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
-            " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
-            "     b MPU_xStreamBufferBytesAvailableImpl             \n"
-            " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
+                " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
+                "     b MPU_xStreamBufferBytesAvailableImpl             \n"
+                " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                                 size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                                 size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
-            " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
-            "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
-            " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
-        );
-    }
+        BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                     size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                     size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
+                " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
+                "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
+                " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
-            " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
-            "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
-            " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
+                " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
+                "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
+                " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.c
index 4f66448f9..6642c9e20 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.c
@@ -1634,113 +1634,129 @@
     #endif /* if ( configUSE_TIMERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-    EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupWaitBitsImpl                   \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
-            " MPU_xEventGroupWaitBits_Priv:                         \n"
-            "     b MPU_xEventGroupWaitBitsImpl                     \n"
-            " MPU_xEventGroupWaitBits_Unpriv:                       \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
-        );
-    }
+        EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupWaitBitsImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xEventGroupWaitBits_Unpriv                    \n"
+                " MPU_xEventGroupWaitBits_Priv:                         \n"
+                "     b MPU_xEventGroupWaitBitsImpl                     \n"
+                " MPU_xEventGroupWaitBits_Unpriv:                       \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                          const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-    EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
-                                          const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupClearBitsImpl                  \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xEventGroupClearBits_Unpriv                   \n"
-            " MPU_xEventGroupClearBits_Priv:                        \n"
-            "     b MPU_xEventGroupClearBitsImpl                    \n"
-            " MPU_xEventGroupClearBits_Unpriv:                      \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
-        );
-    }
+        EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                              const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                              const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupClearBitsImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xEventGroupClearBits_Unpriv                   \n"
+                " MPU_xEventGroupClearBits_Priv:                        \n"
+                "     b MPU_xEventGroupClearBitsImpl                    \n"
+                " MPU_xEventGroupClearBits_Unpriv:                      \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                        const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-    EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
-                                        const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupSetBitsImpl                    \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xEventGroupSetBits_Unpriv                     \n"
-            " MPU_xEventGroupSetBits_Priv:                          \n"
-            "     b MPU_xEventGroupSetBitsImpl                      \n"
-            " MPU_xEventGroupSetBits_Unpriv:                        \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
-        );
-    }
+        EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                            const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                            const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupSetBitsImpl                    \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xEventGroupSetBits_Unpriv                     \n"
+                " MPU_xEventGroupSetBits_Priv:                          \n"
+                "     b MPU_xEventGroupSetBitsImpl                      \n"
+                " MPU_xEventGroupSetBits_Unpriv:                        \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                     const EventBits_t uxBitsToSet,
-                                     const EventBits_t uxBitsToWaitFor,
-                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_EVENT_GROUPS == 1 )
 
-    EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
-                                     const EventBits_t uxBitsToSet,
-                                     const EventBits_t uxBitsToWaitFor,
-                                     TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xEventGroupSyncImpl                       \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xEventGroupSync_Unpriv                        \n"
-            " MPU_xEventGroupSync_Priv:                             \n"
-            "     b MPU_xEventGroupSyncImpl                         \n"
-            " MPU_xEventGroupSync_Unpriv:                           \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
-        );
-    }
+        EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToSet,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                         const EventBits_t uxBitsToSet,
+                                         const EventBits_t uxBitsToWaitFor,
+                                         TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xEventGroupSyncImpl                       \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xEventGroupSync_Unpriv                        \n"
+                " MPU_xEventGroupSync_Priv:                             \n"
+                "     b MPU_xEventGroupSyncImpl                         \n"
+                " MPU_xEventGroupSync_Unpriv:                           \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    #if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
 
         UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
@@ -1765,10 +1781,10 @@
             );
         }
 
-    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-    #if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
 
         void MPU_vEventGroupSetNumber( void * xEventGroup,
                                        UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
@@ -1795,213 +1811,245 @@
             );
         }
 
-    #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+    #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                                  const void * pvTxData,
-                                  size_t xDataLengthBytes,
-                                  TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                                  const void * pvTxData,
-                                  size_t xDataLengthBytes,
-                                  TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferSendImpl                     \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferSend_Unpriv                      \n"
-            " MPU_xStreamBufferSend_Priv:                           \n"
-            "     b MPU_xStreamBufferSendImpl                       \n"
-            " MPU_xStreamBufferSend_Unpriv:                         \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                      const void * pvTxData,
+                                      size_t xDataLengthBytes,
+                                      TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                                      const void * pvTxData,
+                                      size_t xDataLengthBytes,
+                                      TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferSendImpl                     \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferSend_Unpriv                      \n"
+                " MPU_xStreamBufferSend_Priv:                           \n"
+                "     b MPU_xStreamBufferSendImpl                       \n"
+                " MPU_xStreamBufferSend_Unpriv:                         \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                     void * pvRxData,
-                                     size_t xBufferLengthBytes,
-                                     TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                                     void * pvRxData,
-                                     size_t xBufferLengthBytes,
-                                     TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferReceiveImpl                  \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferReceive_Unpriv                   \n"
-            " MPU_xStreamBufferReceive_Priv:                        \n"
-            "     b MPU_xStreamBufferReceiveImpl                    \n"
-            " MPU_xStreamBufferReceive_Unpriv:                      \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                         void * pvRxData,
+                                         size_t xBufferLengthBytes,
+                                         TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                         void * pvRxData,
+                                         size_t xBufferLengthBytes,
+                                         TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferReceiveImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferReceive_Unpriv                   \n"
+                " MPU_xStreamBufferReceive_Priv:                        \n"
+                "     b MPU_xStreamBufferReceiveImpl                    \n"
+                " MPU_xStreamBufferReceive_Unpriv:                      \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferIsFullImpl                   \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
-            " MPU_xStreamBufferIsFull_Priv:                         \n"
-            "     b MPU_xStreamBufferIsFullImpl                     \n"
-            " MPU_xStreamBufferIsFull_Unpriv:                       \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
-        );
-    }
+        BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferIsFullImpl                   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferIsFull_Unpriv                    \n"
+                " MPU_xStreamBufferIsFull_Priv:                         \n"
+                "     b MPU_xStreamBufferIsFullImpl                     \n"
+                " MPU_xStreamBufferIsFull_Unpriv:                       \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
-            " MPU_xStreamBufferIsEmpty_Priv:                        \n"
-            "     b MPU_xStreamBufferIsEmptyImpl                    \n"
-            " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
-        );
-    }
+        BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferIsEmptyImpl                  \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferIsEmpty_Unpriv                   \n"
+                " MPU_xStreamBufferIsEmpty_Priv:                        \n"
+                "     b MPU_xStreamBufferIsEmptyImpl                    \n"
+                " MPU_xStreamBufferIsEmpty_Unpriv:                      \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
-            " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
-            "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
-            " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferSpacesAvailableImpl          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferSpacesAvailable_Unpriv           \n"
+                " MPU_xStreamBufferSpacesAvailable_Priv:                \n"
+                "     b MPU_xStreamBufferSpacesAvailableImpl            \n"
+                " MPU_xStreamBufferSpacesAvailable_Unpriv:              \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
-            " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
-            "     b MPU_xStreamBufferBytesAvailableImpl             \n"
-            " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferBytesAvailableImpl           \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferBytesAvailable_Unpriv            \n"
+                " MPU_xStreamBufferBytesAvailable_Priv:                 \n"
+                "     b MPU_xStreamBufferBytesAvailableImpl             \n"
+                " MPU_xStreamBufferBytesAvailable_Unpriv:               \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                                 size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
-                                                 size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
-            " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
-            "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
-            " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
-        );
-    }
+        BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                     size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                                     size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferSetTriggerLevelImpl          \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferSetTriggerLevel_Unpriv           \n"
+                " MPU_xStreamBufferSetTriggerLevel_Priv:                \n"
+                "     b MPU_xStreamBufferSetTriggerLevelImpl            \n"
+                " MPU_xStreamBufferSetTriggerLevel_Unpriv:              \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
-    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+    #if ( configUSE_STREAM_BUFFERS == 1 )
 
-    size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
-    {
-        __asm volatile
-        (
-            " .syntax unified                                       \n"
-            " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
-            "                                                       \n"
-            " push {r0}                                             \n"
-            " mrs r0, control                                       \n"
-            " tst r0, #1                                            \n"
-            " pop {r0}                                              \n"
-            " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
-            " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
-            "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
-            " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
-            "     svc %0                                            \n"
-            "                                                       \n"
-            : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
-        );
-    }
+        size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+        size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+        {
+            __asm volatile
+            (
+                " .syntax unified                                       \n"
+                " .extern MPU_xStreamBufferNextMessageLengthBytesImpl   \n"
+                "                                                       \n"
+                " push {r0}                                             \n"
+                " mrs r0, control                                       \n"
+                " tst r0, #1                                            \n"
+                " pop {r0}                                              \n"
+                " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv    \n"
+                " MPU_xStreamBufferNextMessageLengthBytes_Priv:         \n"
+                "     b MPU_xStreamBufferNextMessageLengthBytesImpl     \n"
+                " MPU_xStreamBufferNextMessageLengthBytes_Unpriv:       \n"
+                "     svc %0                                            \n"
+                "                                                       \n"
+                : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
+            );
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
diff --git a/portable/GCC/ARM_CRx_MPU/mpu_wrappers_v2_asm.S b/portable/GCC/ARM_CRx_MPU/mpu_wrappers_v2_asm.S
index 8d0f769bb..142486adf 100644
--- a/portable/GCC/ARM_CRx_MPU/mpu_wrappers_v2_asm.S
+++ b/portable/GCC/ARM_CRx_MPU/mpu_wrappers_v2_asm.S
@@ -201,111 +201,119 @@ MPU_xQueueSemaphoreTake:
 
 /* ----------------------------------------------------------------------------------- */
 
-.extern MPU_xEventGroupWaitBitsImpl
-.align 4
-.global MPU_xEventGroupWaitBitsEntry
-.type MPU_xEventGroupWaitBitsEntry, function
-MPU_xEventGroupWaitBitsEntry:
-    INVOKE_SYSTEM_CALL #SYSTEM_CALL_xEventGroupWaitBits, MPU_xEventGroupWaitBitsImpl
+#if ( configUSE_EVENT_GROUPS == 1 )
+
+    .extern MPU_xEventGroupWaitBitsImpl
+    .align 4
+    .global MPU_xEventGroupWaitBitsEntry
+    .type MPU_xEventGroupWaitBitsEntry, function
+    MPU_xEventGroupWaitBitsEntry:
+        INVOKE_SYSTEM_CALL #SYSTEM_CALL_xEventGroupWaitBits, MPU_xEventGroupWaitBitsImpl
+
+    /* ----------------------------------------------------------------------------------- */
+
+    .extern MPU_xEventGroupClearBitsImpl
+    .align 4
+    .global MPU_xEventGroupClearBits
+    .type MPU_xEventGroupClearBits, function
+    MPU_xEventGroupClearBits:
+        INVOKE_SYSTEM_CALL #SYSTEM_CALL_xEventGroupClearBits, MPU_xEventGroupClearBitsImpl
+
+    /* ----------------------------------------------------------------------------------- */
+
+    .extern MPU_xEventGroupSetBitsImpl
+    .align 4
+    .global MPU_xEventGroupSetBits
+    .type MPU_xEventGroupSetBits, function
+    MPU_xEventGroupSetBits:
+        INVOKE_SYSTEM_CALL #SYSTEM_CALL_xEventGroupSetBits, MPU_xEventGroupSetBitsImpl
+
+    /* ----------------------------------------------------------------------------------- */
+
+    .extern MPU_xEventGroupSyncImpl
+    .align 4
+    .global MPU_xEventGroupSync
+    .type MPU_xEventGroupSync, function
+    MPU_xEventGroupSync:
+        INVOKE_SYSTEM_CALL #SYSTEM_CALL_xEventGroupSync, MPU_xEventGroupSyncImpl
+
+#endif /* if ( configUSE_EVENT_GROUPS == 1 ) */
 
 /* ----------------------------------------------------------------------------------- */
 
-.extern MPU_xEventGroupClearBitsImpl
-.align 4
-.global MPU_xEventGroupClearBits
-.type MPU_xEventGroupClearBits, function
-MPU_xEventGroupClearBits:
-    INVOKE_SYSTEM_CALL #SYSTEM_CALL_xEventGroupClearBits, MPU_xEventGroupClearBitsImpl
+#if ( configUSE_STREAM_BUFFERS == 1 )
 
-/* ----------------------------------------------------------------------------------- */
+    .extern MPU_xStreamBufferSendImpl
+    .align 4
+    .global MPU_xStreamBufferSend
+    .type MPU_xStreamBufferSend, function
+    MPU_xStreamBufferSend:
+        INVOKE_SYSTEM_CALL #SYSTEM_CALL_xStreamBufferSend, MPU_xStreamBufferSendImpl
 
-.extern MPU_xEventGroupSetBitsImpl
-.align 4
-.global MPU_xEventGroupSetBits
-.type MPU_xEventGroupSetBits, function
-MPU_xEventGroupSetBits:
-    INVOKE_SYSTEM_CALL #SYSTEM_CALL_xEventGroupSetBits, MPU_xEventGroupSetBitsImpl
+    /* ----------------------------------------------------------------------------------- */
 
-/* ----------------------------------------------------------------------------------- */
+    .extern MPU_xStreamBufferReceiveImpl
+    .align 4
+    .global MPU_xStreamBufferReceive
+    .type MPU_xStreamBufferReceive, function
+    MPU_xStreamBufferReceive:
+        INVOKE_SYSTEM_CALL #SYSTEM_CALL_xStreamBufferReceive, MPU_xStreamBufferReceiveImpl
 
-.extern MPU_xEventGroupSyncImpl
-.align 4
-.global MPU_xEventGroupSync
-.type MPU_xEventGroupSync, function
-MPU_xEventGroupSync:
-    INVOKE_SYSTEM_CALL #SYSTEM_CALL_xEventGroupSync, MPU_xEventGroupSyncImpl
+    /* ----------------------------------------------------------------------------------- */
 
-/* ----------------------------------------------------------------------------------- */
+    .extern MPU_xStreamBufferIsFullImpl
+    .align 4
+    .global MPU_xStreamBufferIsFull
+    .type MPU_xStreamBufferIsFull, function
+    MPU_xStreamBufferIsFull:
+        INVOKE_SYSTEM_CALL #SYSTEM_CALL_xStreamBufferIsFull, MPU_xStreamBufferIsFullImpl
 
-.extern MPU_xStreamBufferSendImpl
-.align 4
-.global MPU_xStreamBufferSend
-.type MPU_xStreamBufferSend, function
-MPU_xStreamBufferSend:
-    INVOKE_SYSTEM_CALL #SYSTEM_CALL_xStreamBufferSend, MPU_xStreamBufferSendImpl
+    /* ----------------------------------------------------------------------------------- */
 
-/* ----------------------------------------------------------------------------------- */
+    .extern MPU_xStreamBufferIsEmptyImpl
+    .align 4
+    .global MPU_xStreamBufferIsEmpty
+    .type MPU_xStreamBufferIsEmpty, function
+    MPU_xStreamBufferIsEmpty:
+        INVOKE_SYSTEM_CALL #SYSTEM_CALL_xStreamBufferIsEmpty, MPU_xStreamBufferIsEmptyImpl
 
-.extern MPU_xStreamBufferReceiveImpl
-.align 4
-.global MPU_xStreamBufferReceive
-.type MPU_xStreamBufferReceive, function
-MPU_xStreamBufferReceive:
-    INVOKE_SYSTEM_CALL #SYSTEM_CALL_xStreamBufferReceive, MPU_xStreamBufferReceiveImpl
+    /* ----------------------------------------------------------------------------------- */
 
-/* ----------------------------------------------------------------------------------- */
+    .extern MPU_xStreamBufferSpacesAvailableImpl
+    .align 4
+    .global MPU_xStreamBufferSpacesAvailable
+    .type MPU_xStreamBufferSpacesAvailable, function
+    MPU_xStreamBufferSpacesAvailable:
+        INVOKE_SYSTEM_CALL #SYSTEM_CALL_xStreamBufferSpacesAvailable, MPU_xStreamBufferSpacesAvailableImpl
 
-.extern MPU_xStreamBufferIsFullImpl
-.align 4
-.global MPU_xStreamBufferIsFull
-.type MPU_xStreamBufferIsFull, function
-MPU_xStreamBufferIsFull:
-    INVOKE_SYSTEM_CALL #SYSTEM_CALL_xStreamBufferIsFull, MPU_xStreamBufferIsFullImpl
+    /* ----------------------------------------------------------------------------------- */
 
-/* ----------------------------------------------------------------------------------- */
+    .extern MPU_xStreamBufferBytesAvailableImpl
+    .align 4
+    .global MPU_xStreamBufferBytesAvailable
+    .type MPU_xStreamBufferBytesAvailable, function
+    MPU_xStreamBufferBytesAvailable:
+        INVOKE_SYSTEM_CALL #SYSTEM_CALL_xStreamBufferBytesAvailable, MPU_xStreamBufferBytesAvailableImpl
 
-.extern MPU_xStreamBufferIsEmptyImpl
-.align 4
-.global MPU_xStreamBufferIsEmpty
-.type MPU_xStreamBufferIsEmpty, function
-MPU_xStreamBufferIsEmpty:
-    INVOKE_SYSTEM_CALL #SYSTEM_CALL_xStreamBufferIsEmpty, MPU_xStreamBufferIsEmptyImpl
+    /* ----------------------------------------------------------------------------------- */
 
-/* ----------------------------------------------------------------------------------- */
+    .extern MPU_xStreamBufferSetTriggerLevelImpl
+    .align 4
+    .global MPU_xStreamBufferSetTriggerLevel
+    .type MPU_xStreamBufferSetTriggerLevel, function
+    MPU_xStreamBufferSetTriggerLevel:
+        INVOKE_SYSTEM_CALL #SYSTEM_CALL_xStreamBufferSetTriggerLevel, MPU_xStreamBufferSetTriggerLevelImpl
 
-.extern MPU_xStreamBufferSpacesAvailableImpl
-.align 4
-.global MPU_xStreamBufferSpacesAvailable
-.type MPU_xStreamBufferSpacesAvailable, function
-MPU_xStreamBufferSpacesAvailable:
-    INVOKE_SYSTEM_CALL #SYSTEM_CALL_xStreamBufferSpacesAvailable, MPU_xStreamBufferSpacesAvailableImpl
+    /* ----------------------------------------------------------------------------------- */
 
-/* ----------------------------------------------------------------------------------- */
+    .extern MPU_xStreamBufferNextMessageLengthBytesImpl
+    .align 4
+    .global MPU_xStreamBufferNextMessageLengthBytes
+    .type MPU_xStreamBufferNextMessageLengthBytes, function
+    MPU_xStreamBufferNextMessageLengthBytes:
+        INVOKE_SYSTEM_CALL #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes, MPU_xStreamBufferNextMessageLengthBytesImpl
 
-.extern MPU_xStreamBufferBytesAvailableImpl
-.align 4
-.global MPU_xStreamBufferBytesAvailable
-.type MPU_xStreamBufferBytesAvailable, function
-MPU_xStreamBufferBytesAvailable:
-    INVOKE_SYSTEM_CALL #SYSTEM_CALL_xStreamBufferBytesAvailable, MPU_xStreamBufferBytesAvailableImpl
-
-/* ----------------------------------------------------------------------------------- */
-
-.extern MPU_xStreamBufferSetTriggerLevelImpl
-.align 4
-.global MPU_xStreamBufferSetTriggerLevel
-.type MPU_xStreamBufferSetTriggerLevel, function
-MPU_xStreamBufferSetTriggerLevel:
-    INVOKE_SYSTEM_CALL #SYSTEM_CALL_xStreamBufferSetTriggerLevel, MPU_xStreamBufferSetTriggerLevelImpl
-
-/* ----------------------------------------------------------------------------------- */
-
-.extern MPU_xStreamBufferNextMessageLengthBytesImpl
-.align 4
-.global MPU_xStreamBufferNextMessageLengthBytes
-.type MPU_xStreamBufferNextMessageLengthBytes, function
-MPU_xStreamBufferNextMessageLengthBytes:
-    INVOKE_SYSTEM_CALL #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes, MPU_xStreamBufferNextMessageLengthBytesImpl
+#endif /* if ( configUSE_STREAM_BUFFERS == 1 ) */
 
 /* ----------------------------------------------------------------------------------- */
 
@@ -392,8 +400,11 @@ MPU_xStreamBufferNextMessageLengthBytes:
     MPU_uxTaskGetSystemState:
         INVOKE_SYSTEM_CALL #SYSTEM_CALL_uxTaskGetSystemState, MPU_uxTaskGetSystemStateImpl
 
-    /* ------------------------------------------------------------------------------- */
+#endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
 
+/* ------------------------------------------------------------------------------- */
+
+#if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
     .extern MPU_uxEventGroupGetNumberImpl
     .align 4
     .global MPU_uxEventGroupGetNumber
@@ -403,6 +414,8 @@ MPU_xStreamBufferNextMessageLengthBytes:
 
     /* ------------------------------------------------------------------------------- */
 
+
+
     .extern MPU_vEventGroupSetNumberImpl
     .align 4
     .global MPU_vEventGroupSetNumber
@@ -412,7 +425,7 @@ MPU_xStreamBufferNextMessageLengthBytes:
 
     /* ------------------------------------------------------------------------------- */
 
-#endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
+#endif /* if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
 
 /* ------------------------------------------------------------------------------- */
 
diff --git a/portable/RVDS/ARM_CM4_MPU/mpu_wrappers_v2_asm.c b/portable/RVDS/ARM_CM4_MPU/mpu_wrappers_v2_asm.c
index 3a41d8d31..82dd5f40d 100644
--- a/portable/RVDS/ARM_CM4_MPU/mpu_wrappers_v2_asm.c
+++ b/portable/RVDS/ARM_CM4_MPU/mpu_wrappers_v2_asm.c
@@ -1354,6 +1354,8 @@ MPU_xTimerGetExpiryTime_Unpriv
 #endif /* if ( configUSE_TIMERS == 1 ) */
 /*-----------------------------------------------------------*/
 
+#if ( configUSE_EVENT_GROUPS == 1 )
+
 EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) FREERTOS_SYSTEM_CALL;
 
 __asm EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* FREERTOS_SYSTEM_CALL */
@@ -1371,8 +1373,12 @@ MPU_xEventGroupWaitBits_Priv
 MPU_xEventGroupWaitBits_Unpriv
         svc #SYSTEM_CALL_xEventGroupWaitBits
 }
+
+#endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
+#if ( configUSE_EVENT_GROUPS == 1 )
+
 EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
                                       const EventBits_t uxBitsToClear ) FREERTOS_SYSTEM_CALL;
 
@@ -1392,8 +1398,12 @@ MPU_xEventGroupClearBits_Priv
 MPU_xEventGroupClearBits_Unpriv
         svc #SYSTEM_CALL_xEventGroupClearBits
 }
+
+#endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
+#if ( configUSE_EVENT_GROUPS == 1 )
+
 EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
                                     const EventBits_t uxBitsToSet ) FREERTOS_SYSTEM_CALL;
 
@@ -1413,8 +1423,12 @@ MPU_xEventGroupSetBits_Priv
 MPU_xEventGroupSetBits_Unpriv
         svc #SYSTEM_CALL_xEventGroupSetBits
 }
+
+#endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
+#if ( configUSE_EVENT_GROUPS == 1 )
+
 EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
                                  const EventBits_t uxBitsToSet,
                                  const EventBits_t uxBitsToWaitFor,
@@ -1438,9 +1452,11 @@ MPU_xEventGroupSync_Priv
 MPU_xEventGroupSync_Unpriv
         svc #SYSTEM_CALL_xEventGroupSync
 }
+
+#endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+#if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
 
 UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) FREERTOS_SYSTEM_CALL;
 
@@ -1460,10 +1476,10 @@ MPU_uxEventGroupGetNumber_Unpriv
         svc #SYSTEM_CALL_uxEventGroupGetNumber
 }
 
-#endif /*( configUSE_TRACE_FACILITY == 1 )*/
+#endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+#if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
 
 void MPU_vEventGroupSetNumber( void * xEventGroup,
                                UBaseType_t uxEventGroupNumber ) FREERTOS_SYSTEM_CALL;
@@ -1485,9 +1501,11 @@ MPU_vEventGroupSetNumber_Unpriv
         svc #SYSTEM_CALL_vEventGroupSetNumber
 }
 
-#endif /*( configUSE_TRACE_FACILITY == 1 )*/
+#endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
 /*-----------------------------------------------------------*/
 
+#if ( configUSE_STREAM_BUFFERS == 1 )
+
 size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
                               const void * pvTxData,
                               size_t xDataLengthBytes,
@@ -1511,8 +1529,12 @@ MPU_xStreamBufferSend_Priv
 MPU_xStreamBufferSend_Unpriv
         svc #SYSTEM_CALL_xStreamBufferSend
 }
+
+#endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
+#if ( configUSE_STREAM_BUFFERS == 1 )
+
 size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
                                  void * pvRxData,
                                  size_t xBufferLengthBytes,
@@ -1536,8 +1558,12 @@ MPU_xStreamBufferReceive_Priv
 MPU_xStreamBufferReceive_Unpriv
         svc #SYSTEM_CALL_xStreamBufferReceive
 }
+
+#endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
+#if ( configUSE_STREAM_BUFFERS == 1 )
+
 BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
 
 __asm BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
@@ -1555,8 +1581,12 @@ MPU_xStreamBufferIsFull_Priv
 MPU_xStreamBufferIsFull_Unpriv
         svc #SYSTEM_CALL_xStreamBufferIsFull
 }
+
+#endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
+#if ( configUSE_STREAM_BUFFERS == 1 )
+
 BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
 
 __asm BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
@@ -1574,8 +1604,12 @@ MPU_xStreamBufferIsEmpty_Priv
 MPU_xStreamBufferIsEmpty_Unpriv
         svc #SYSTEM_CALL_xStreamBufferIsEmpty
 }
+
+#endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
+#if ( configUSE_STREAM_BUFFERS == 1 )
+
 size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
 
 __asm size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
@@ -1593,8 +1627,12 @@ MPU_xStreamBufferSpacesAvailable_Priv
 MPU_xStreamBufferSpacesAvailable_Unpriv
         svc #SYSTEM_CALL_xStreamBufferSpacesAvailable
 }
+
+#endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
+#if ( configUSE_STREAM_BUFFERS == 1 )
+
 size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
 
 __asm size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
@@ -1612,8 +1650,12 @@ MPU_xStreamBufferBytesAvailable_Priv
 MPU_xStreamBufferBytesAvailable_Unpriv
         svc #SYSTEM_CALL_xStreamBufferBytesAvailable
 }
+
+#endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
+#if ( configUSE_STREAM_BUFFERS == 1 )
+
 BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
                                              size_t xTriggerLevel ) FREERTOS_SYSTEM_CALL;
 
@@ -1633,8 +1675,12 @@ MPU_xStreamBufferSetTriggerLevel_Priv
 MPU_xStreamBufferSetTriggerLevel_Unpriv
         svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel
 }
+
+#endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
+#if ( configUSE_STREAM_BUFFERS == 1 )
+
 size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
 
 __asm size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
@@ -1652,6 +1698,8 @@ MPU_xStreamBufferNextMessageLengthBytes_Priv
 MPU_xStreamBufferNextMessageLengthBytes_Unpriv
         svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes
 }
+
+#endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 /*-----------------------------------------------------------*/
 
 #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
diff --git a/stream_buffer.c b/stream_buffer.c
index 2c357c657..44354fba3 100644
--- a/stream_buffer.c
+++ b/stream_buffer.c
@@ -52,11 +52,17 @@
  * correct privileged Vs unprivileged linkage and placement. */
 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
 
+/* This entire source file will be skipped if the application is not configured
+ * to include stream buffer functionality. This #if is closed at the very bottom
+ * of this file. If you want to include stream buffers then ensure
+ * configUSE_STREAM_BUFFERS is set to 1 in FreeRTOSConfig.h. */
+#if ( configUSE_STREAM_BUFFERS == 1 )
+
 /* If the user has not provided application specific Rx notification macros,
  * or #defined the notification macros away, then provide default implementations
  * that uses task notifications. */
-#ifndef sbRECEIVE_COMPLETED
-    #define sbRECEIVE_COMPLETED( pxStreamBuffer )                                     \
+    #ifndef sbRECEIVE_COMPLETED
+        #define sbRECEIVE_COMPLETED( pxStreamBuffer )                                 \
     do                                                                                \
     {                                                                                 \
         vTaskSuspendAll();                                                            \
@@ -72,13 +78,13 @@
         }                                                                             \
         ( void ) xTaskResumeAll();                                                    \
     } while( 0 )
-#endif /* sbRECEIVE_COMPLETED */
+    #endif /* sbRECEIVE_COMPLETED */
 
 /* If user has provided a per-instance receive complete callback, then
  * invoke the callback else use the receive complete macro which is provided by default for all instances.
  */
-#if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
-    #define prvRECEIVE_COMPLETED( pxStreamBuffer )                                               \
+    #if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
+        #define prvRECEIVE_COMPLETED( pxStreamBuffer )                                           \
     do {                                                                                         \
         if( ( pxStreamBuffer )->pxReceiveCompletedCallback != NULL )                             \
         {                                                                                        \
@@ -89,13 +95,13 @@
             sbRECEIVE_COMPLETED( ( pxStreamBuffer ) );                                           \
         }                                                                                        \
     } while( 0 )
-#else /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */
-    #define prvRECEIVE_COMPLETED( pxStreamBuffer )    sbRECEIVE_COMPLETED( ( pxStreamBuffer ) )
-#endif /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */
+    #else /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */
+        #define prvRECEIVE_COMPLETED( pxStreamBuffer )    sbRECEIVE_COMPLETED( ( pxStreamBuffer ) )
+    #endif /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */
 
-#ifndef sbRECEIVE_COMPLETED_FROM_ISR
-    #define sbRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer,                                    \
-                                          pxHigherPriorityTaskWoken )                        \
+    #ifndef sbRECEIVE_COMPLETED_FROM_ISR
+        #define sbRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer,                                \
+                                              pxHigherPriorityTaskWoken )                    \
     do {                                                                                     \
         UBaseType_t uxSavedInterruptStatus;                                                  \
                                                                                              \
@@ -113,11 +119,11 @@
         }                                                                                    \
         taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );                                \
     } while( 0 )
-#endif /* sbRECEIVE_COMPLETED_FROM_ISR */
+    #endif /* sbRECEIVE_COMPLETED_FROM_ISR */
 
-#if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
-    #define prvRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer,                                                               \
-                                           pxHigherPriorityTaskWoken )                                                   \
+    #if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
+        #define prvRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer,                                                           \
+                                               pxHigherPriorityTaskWoken )                                               \
     do {                                                                                                                 \
         if( ( pxStreamBuffer )->pxReceiveCompletedCallback != NULL )                                                     \
         {                                                                                                                \
@@ -128,17 +134,17 @@
             sbRECEIVE_COMPLETED_FROM_ISR( ( pxStreamBuffer ), ( pxHigherPriorityTaskWoken ) );                           \
         }                                                                                                                \
     } while( 0 )
-#else /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */
-    #define prvRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken ) \
+    #else /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */
+        #define prvRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken ) \
     sbRECEIVE_COMPLETED_FROM_ISR( ( pxStreamBuffer ), ( pxHigherPriorityTaskWoken ) )
-#endif /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */
+    #endif /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */
 
 /* If the user has not provided an application specific Tx notification macro,
  * or #defined the notification macro away, then provide a default
  * implementation that uses task notifications.
  */
-#ifndef sbSEND_COMPLETED
-    #define sbSEND_COMPLETED( pxStreamBuffer )                                      \
+    #ifndef sbSEND_COMPLETED
+        #define sbSEND_COMPLETED( pxStreamBuffer )                                  \
     vTaskSuspendAll();                                                              \
     {                                                                               \
         if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )                     \
@@ -151,13 +157,13 @@
         }                                                                           \
     }                                                                               \
     ( void ) xTaskResumeAll()
-#endif /* sbSEND_COMPLETED */
+    #endif /* sbSEND_COMPLETED */
 
 /* If user has provided a per-instance send completed callback, then
  * invoke the callback else use the send complete macro which is provided by default for all instances.
  */
-#if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
-    #define prvSEND_COMPLETED( pxStreamBuffer )                                               \
+    #if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
+        #define prvSEND_COMPLETED( pxStreamBuffer )                                           \
     do {                                                                                      \
         if( ( pxStreamBuffer )->pxSendCompletedCallback != NULL )                             \
         {                                                                                     \
@@ -168,13 +174,13 @@
             sbSEND_COMPLETED( ( pxStreamBuffer ) );                                           \
         }                                                                                     \
     } while( 0 )
-#else /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */
-    #define prvSEND_COMPLETED( pxStreamBuffer )    sbSEND_COMPLETED( ( pxStreamBuffer ) )
-#endif /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */
+    #else /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */
+        #define prvSEND_COMPLETED( pxStreamBuffer )    sbSEND_COMPLETED( ( pxStreamBuffer ) )
+    #endif /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */
 
 
-#ifndef sbSEND_COMPLETE_FROM_ISR
-    #define sbSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken )              \
+    #ifndef sbSEND_COMPLETE_FROM_ISR
+        #define sbSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken )          \
     do {                                                                                       \
         UBaseType_t uxSavedInterruptStatus;                                                    \
                                                                                                \
@@ -192,11 +198,11 @@
         }                                                                                      \
         taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );                                  \
     } while( 0 )
-#endif /* sbSEND_COMPLETE_FROM_ISR */
+    #endif /* sbSEND_COMPLETE_FROM_ISR */
 
 
-#if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
-    #define prvSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken )                                    \
+    #if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
+        #define prvSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken )                                \
     do {                                                                                                              \
         if( ( pxStreamBuffer )->pxSendCompletedCallback != NULL )                                                     \
         {                                                                                                             \
@@ -207,17 +213,17 @@
             sbSEND_COMPLETE_FROM_ISR( ( pxStreamBuffer ), ( pxHigherPriorityTaskWoken ) );                            \
         }                                                                                                             \
     } while( 0 )
-#else /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */
-    #define prvSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken ) \
+    #else /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */
+        #define prvSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken ) \
     sbSEND_COMPLETE_FROM_ISR( ( pxStreamBuffer ), ( pxHigherPriorityTaskWoken ) )
-#endif /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */
+    #endif /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */
 
 /* The number of bytes used to hold the length of a message in the buffer. */
-#define sbBYTES_TO_STORE_MESSAGE_LENGTH    ( sizeof( configMESSAGE_BUFFER_LENGTH_TYPE ) )
+    #define sbBYTES_TO_STORE_MESSAGE_LENGTH    ( sizeof( configMESSAGE_BUFFER_LENGTH_TYPE ) )
 
 /* Bits stored in the ucFlags field of the stream buffer. */
-#define sbFLAGS_IS_MESSAGE_BUFFER          ( ( uint8_t ) 1 ) /* Set if the stream buffer was created as a message buffer, in which case it holds discrete messages rather than a stream. */
-#define sbFLAGS_IS_STATICALLY_ALLOCATED    ( ( uint8_t ) 2 ) /* Set if the stream buffer was created using statically allocated memory. */
+    #define sbFLAGS_IS_MESSAGE_BUFFER          ( ( uint8_t ) 1 ) /* Set if the stream buffer was created as a message buffer, in which case it holds discrete messages rather than a stream. */
+    #define sbFLAGS_IS_STATICALLY_ALLOCATED    ( ( uint8_t ) 2 ) /* Set if the stream buffer was created using statically allocated memory. */
 
 /*-----------------------------------------------------------*/
 
@@ -320,7 +326,7 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
                                           StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) PRIVILEGED_FUNCTION;
 
 /*-----------------------------------------------------------*/
-#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+    #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
     StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes,
                                                      size_t xTriggerLevelBytes,
                                                      BaseType_t xIsMessageBuffer,
@@ -406,10 +412,10 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
         /* coverity[misra_c_2012_rule_11_5_violation] */
         return ( StreamBufferHandle_t ) pvAllocatedMemory;
     }
-#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+    #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
 /*-----------------------------------------------------------*/
 
-#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+    #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
 
     StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
                                                            size_t xTriggerLevelBytes,
@@ -497,10 +503,10 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
 
         return xReturn;
     }
-#endif /* ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+    #endif /* ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+    #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
     BaseType_t xStreamBufferGetStaticBuffers( StreamBufferHandle_t xStreamBuffer,
                                               uint8_t ** ppucStreamBufferStorageArea,
                                               StaticStreamBuffer_t ** ppxStaticStreamBuffer )
@@ -532,7 +538,7 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
 
         return xReturn;
     }
-#endif /* configSUPPORT_STATIC_ALLOCATION */
+    #endif /* configSUPPORT_STATIC_ALLOCATION */
 /*-----------------------------------------------------------*/
 
 void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer )
@@ -1461,7 +1467,7 @@ static size_t prvReadBytesFromBuffer( StreamBuffer_t * pxStreamBuffer,
 
 static size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer )
 {
-/* Returns the distance between xTail and xHead. */
+    /* Returns the distance between xTail and xHead. */
     size_t xCount;
 
     xCount = pxStreamBuffer->xLength + pxStreamBuffer->xHead;
@@ -1496,7 +1502,7 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
         /* The value written just has to be identifiable when looking at the
          * memory.  Don't use 0xA5 as that is the stack fill value and could
          * result in confusion as to what is actually being observed. */
-    #define STREAM_BUFFER_BUFFER_WRITE_VALUE    ( 0x55 )
+        #define STREAM_BUFFER_BUFFER_WRITE_VALUE    ( 0x55 )
         configASSERT( memset( pucBuffer, ( int ) STREAM_BUFFER_BUFFER_WRITE_VALUE, xBufferSizeBytes ) == pucBuffer );
     }
     #endif
@@ -1564,7 +1570,7 @@ void vStreamBufferSetStreamBufferNotificationIndex( StreamBufferHandle_t xStream
 }
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
     UBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer )
     {
@@ -1575,10 +1581,10 @@ void vStreamBufferSetStreamBufferNotificationIndex( StreamBufferHandle_t xStream
         return xStreamBuffer->uxStreamBufferNumber;
     }
 
-#endif /* configUSE_TRACE_FACILITY */
+    #endif /* configUSE_TRACE_FACILITY */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
     void vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer,
                                              UBaseType_t uxStreamBufferNumber )
@@ -1590,10 +1596,10 @@ void vStreamBufferSetStreamBufferNotificationIndex( StreamBufferHandle_t xStream
         traceRETURN_vStreamBufferSetStreamBufferNumber();
     }
 
-#endif /* configUSE_TRACE_FACILITY */
+    #endif /* configUSE_TRACE_FACILITY */
 /*-----------------------------------------------------------*/
 
-#if ( configUSE_TRACE_FACILITY == 1 )
+    #if ( configUSE_TRACE_FACILITY == 1 )
 
     uint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer )
     {
@@ -1604,5 +1610,11 @@ void vStreamBufferSetStreamBufferNotificationIndex( StreamBufferHandle_t xStream
         return( ( uint8_t ) ( xStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) );
     }
 
-#endif /* configUSE_TRACE_FACILITY */
+    #endif /* configUSE_TRACE_FACILITY */
 /*-----------------------------------------------------------*/
+
+/* This entire source file will be skipped if the application is not configured
+ * to include stream buffer functionality. This #if is closed at the very bottom
+ * of this file. If you want to include stream buffers then ensure
+ * configUSE_STREAM_BUFFERS is set to 1 in FreeRTOSConfig.h. */
+#endif /* configUSE_STREAM_BUFFERS == 1 */

From 7c910499ecf13bc3f5d881814f319704279b5c13 Mon Sep 17 00:00:00 2001
From: Soren Ptak <ptaksoren@gmail.com>
Date: Thu, 28 Mar 2024 10:47:34 -0700
Subject: [PATCH 242/424] Update checkout action used in workflow files (#1017)

* Use the latest tagged release of the checkout action.
* Cleanup some of the echo group prints in the workflow files
---
 .github/workflows/auto-release.yml  |  4 +--
 .github/workflows/ci.yml            |  8 +++---
 .github/workflows/coverity_scan.yml |  2 +-
 .github/workflows/git-secrets.yml   |  4 +--
 .github/workflows/kernel-checks.yml |  4 +--
 .github/workflows/kernel-demos.yml  | 43 +++++++++++++----------------
 .github/workflows/unit-tests.yml    |  4 +--
 7 files changed, 32 insertions(+), 37 deletions(-)

diff --git a/.github/workflows/auto-release.yml b/.github/workflows/auto-release.yml
index 73ec92cf0..bad7a9bce 100644
--- a/.github/workflows/auto-release.yml
+++ b/.github/workflows/auto-release.yml
@@ -31,14 +31,14 @@ jobs:
 
       # Currently FreeRTOS/.github/scripts houses the release script. Download it for upcoming usage
       - name: Checkout FreeRTOS Release Tools
-        uses: actions/checkout@v3
+        uses: actions/checkout@v4.1.1
         with:
           repository: FreeRTOS/FreeRTOS
           path: tools
 
       # Simpler git auth if we use checkout action and forward the repo to release script
       - name: Checkout FreeRTOS Kernel
-        uses: actions/checkout@v3
+        uses: actions/checkout@v4.1.1
         with:
           path: local_kernel
           fetch-depth: 0
diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
index bc6d8802b..1ba874850 100644
--- a/.github/workflows/ci.yml
+++ b/.github/workflows/ci.yml
@@ -9,7 +9,7 @@ jobs:
   formatting:
     runs-on: ubuntu-20.04
     steps:
-      - uses: actions/checkout@v3
+      - uses: actions/checkout@v4.1.1
       - name: Check Formatting of FreeRTOS-Kernel Files
         uses: FreeRTOS/CI-CD-Github-Actions/formatting@main
         with:
@@ -19,7 +19,7 @@ jobs:
       runs-on: ubuntu-latest
       steps:
         - name: Clone This Repo
-          uses: actions/checkout@v3
+          uses: actions/checkout@v4.1.1
         - name: Run spellings check
           uses: FreeRTOS/CI-CD-Github-Actions/spellings@main
           with:
@@ -30,14 +30,14 @@ jobs:
     runs-on: ubuntu-latest
     steps:
       - name: Clone This Repo
-        uses: actions/checkout@v3
+        uses: actions/checkout@v4.1.1
       - name: Link Verification
         uses: FreeRTOS/CI-CD-Github-Actions/link-verifier@main
 
   verify-manifest:
     runs-on: ubuntu-latest
     steps:
-      - uses: actions/checkout@v3
+      - uses: actions/checkout@v4.1.1
         with:
           submodules: true
           fetch-depth: 0
diff --git a/.github/workflows/coverity_scan.yml b/.github/workflows/coverity_scan.yml
index 85db51800..14f5366b4 100644
--- a/.github/workflows/coverity_scan.yml
+++ b/.github/workflows/coverity_scan.yml
@@ -19,7 +19,7 @@ jobs:
     runs-on: ubuntu-latest
     steps:
       - name: Checkout the Repository
-        uses: actions/checkout@v3
+        uses: actions/checkout@v4.1.1
 
       - env:
           stepName: Install Build Essentials
diff --git a/.github/workflows/git-secrets.yml b/.github/workflows/git-secrets.yml
index 2b88ce0a7..81b929cd3 100644
--- a/.github/workflows/git-secrets.yml
+++ b/.github/workflows/git-secrets.yml
@@ -7,11 +7,11 @@ jobs:
   git-secrets:
     runs-on: ubuntu-latest
     steps:
-      - uses: actions/checkout@v3
+      - uses: actions/checkout@v4.1.1
         with:
           submodules: recursive
       - name: Checkout awslabs/git-secrets
-        uses: actions/checkout@v3
+        uses: actions/checkout@v4.1.1
         with:
           repository: awslabs/git-secrets
           ref: master
diff --git a/.github/workflows/kernel-checks.yml b/.github/workflows/kernel-checks.yml
index cfaec5b12..ad3096f0d 100644
--- a/.github/workflows/kernel-checks.yml
+++ b/.github/workflows/kernel-checks.yml
@@ -15,7 +15,7 @@ jobs:
 
       # There is shared code, hosted by FreeRTOS/FreeRTOS, with deps needed by header checker
       - name: Checkout FreeRTOS Tools
-        uses: actions/checkout@v3
+        uses: actions/checkout@v4.1.1
         with:
           repository: FreeRTOS/FreeRTOS
           sparse-checkout: '.github'
@@ -24,7 +24,7 @@ jobs:
 
       # Checkout user pull request changes
       - name: Checkout Pull Request
-        uses: actions/checkout@v3
+        uses: actions/checkout@v4.1.1
         with:
           path: inspect
 
diff --git a/.github/workflows/kernel-demos.yml b/.github/workflows/kernel-demos.yml
index 9a74e3d00..556613ad7 100644
--- a/.github/workflows/kernel-demos.yml
+++ b/.github/workflows/kernel-demos.yml
@@ -14,7 +14,7 @@ jobs:
     runs-on: windows-latest
     steps:
       - name: Checkout the FreeRTOS/FreeRTOS Repository
-        uses: actions/checkout@v3
+        uses: actions/checkout@v4.1.1
         with:
           ref: main
           repository: FreeRTOS/FreeRTOS
@@ -23,7 +23,7 @@ jobs:
 
       # Checkout user pull request changes
       - name: Checkout Pull Request
-        uses: actions/checkout@v3
+        uses: actions/checkout@v4.1.1
         with:
           path: ./FreeRTOS/Source
 
@@ -43,7 +43,7 @@ jobs:
     runs-on: windows-latest
     steps:
       - name: Checkout the FreeRTOS/FreeRTOS Repository
-        uses: actions/checkout@v3
+        uses: actions/checkout@v4.1.1
         with:
           ref: main
           repository: FreeRTOS/FreeRTOS
@@ -52,7 +52,7 @@ jobs:
 
       # Checkout user pull request changes
       - name: Checkout Pull Request
-        uses: actions/checkout@v3
+        uses: actions/checkout@v4.1.1
         with:
           path: ./FreeRTOS/Source
 
@@ -74,7 +74,7 @@ jobs:
     runs-on: ${{ matrix.os }}
     steps:
       - name: Checkout the FreeRTOS/FreeRTOS Repository
-        uses: actions/checkout@v3
+        uses: actions/checkout@v4.1.1
         with:
           ref: main
           repository: FreeRTOS/FreeRTOS
@@ -83,7 +83,7 @@ jobs:
 
       # Checkout user pull request changes
       - name: Checkout Pull Request
-        uses: actions/checkout@v3
+        uses: actions/checkout@v4.1.1
         with:
           path: ./FreeRTOS/Source
 
@@ -110,7 +110,7 @@ jobs:
     steps:
       # Checkout user pull request changes
       - name: Checkout Repository
-        uses: actions/checkout@v3
+        uses: actions/checkout@v4.1.1
 
       - name: Install GCC
         shell: bash
@@ -137,7 +137,7 @@ jobs:
     runs-on: ubuntu-latest
     steps:
       - name: Checkout the FreeRTOS/FreeRTOS Repository
-        uses: actions/checkout@v3
+        uses: actions/checkout@v4.1.1
         with:
           ref: main
           repository: FreeRTOS/FreeRTOS
@@ -146,7 +146,7 @@ jobs:
 
       # Checkout user pull request changes
       - name: Checkout Pull Request
-        uses: actions/checkout@v3
+        uses: actions/checkout@v4.1.1
         with:
           path: ./FreeRTOS/Source
 
@@ -166,7 +166,7 @@ jobs:
     runs-on: ubuntu-latest
     steps:
       - name: Checkout the FreeRTOS/FreeRTOS Repository
-        uses: actions/checkout@v3
+        uses: actions/checkout@v4.1.1
         with:
           ref: main
           repository: FreeRTOS/FreeRTOS
@@ -176,7 +176,7 @@ jobs:
           stepName: Fetch Community-Supported-Demos Submodule
         shell: bash
         run: |
-          # Fetch Community-Supported-Demos Submodule
+          # ${{ env.stepName }}
           echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}"
           git submodule update --checkout --init --depth 1 FreeRTOS/Demo/ThirdParty/Community-Supported-Demos
           # This repository contains the microblaze_instructions.h header file
@@ -186,7 +186,7 @@ jobs:
 
       # Checkout user pull request changes
       - name: Checkout Pull Request
-        uses: actions/checkout@v3
+        uses: actions/checkout@v4.1.1
         with:
           path: ./FreeRTOS/Source
 
@@ -252,29 +252,24 @@ jobs:
     runs-on: ubuntu-latest
     steps:
       - name: Checkout the FreeRTOS/FreeRTOS Repository
-        uses: actions/checkout@v3
+        uses: actions/checkout@v4.1.1
         with:
           ref: main
           repository: FreeRTOS/FreeRTOS
           fetch-depth: 1
 
-      - name: Fetch Community-Supported-Demos Submodule
+      - env:
+          stepName: Fetch Community-Supported-Demos Submodule
         shell: bash
         run: |
-          # Fetch Community-Supported-Demos Submodule
-          echo "::group::Fetch Community-Supported-Demos Submodule"
+          # ${{ env.stepName }}
+          echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}"
           git submodule update --checkout --init --depth 1 FreeRTOS/Demo/ThirdParty/Community-Supported-Demos
-          echo "::endgroup::"
-          if [ "$?" = "0" ]; then
-            echo -e "\033[32;3mCloned the Community-Supported-Demos\033[0m"
-          else
-            echo -e "\033[32;31mCommunity-Supported-Demos Clone Failed...\033[0m"
-            exit 1
-          fi
+          echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }}"
 
       # Checkout user pull request changes
       - name: Checkout Pull Request
-        uses: actions/checkout@v3
+        uses: actions/checkout@v4.1.1
         with:
           path: ./FreeRTOS/Source
 
diff --git a/.github/workflows/unit-tests.yml b/.github/workflows/unit-tests.yml
index c154750b4..b6d2960b6 100644
--- a/.github/workflows/unit-tests.yml
+++ b/.github/workflows/unit-tests.yml
@@ -6,7 +6,7 @@ jobs:
     runs-on: ubuntu-20.04
     steps:
     - name: Checkout Parent Repository
-      uses: actions/checkout@v3
+      uses: actions/checkout@v4.1.1
       with:
         ref: main
         repository: FreeRTOS/FreeRTOS
@@ -15,7 +15,7 @@ jobs:
 
     # Checkout user pull request changes
     - name: Checkout Pull Request
-      uses: actions/checkout@v3
+      uses: actions/checkout@v4.1.1
       with:
         path: ./FreeRTOS/Source
 

From 52ee9faa72f2f67f04752c9d89b7b48c804bfa66 Mon Sep 17 00:00:00 2001
From: Soren Ptak <ptaksoren@gmail.com>
Date: Thu, 28 Mar 2024 22:37:38 -0700
Subject: [PATCH 243/424] Add in CI-CD builds of the Cortex-Rx MPU Demos
 (#1018)

---
 .github/workflows/kernel-demos.yml | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/.github/workflows/kernel-demos.yml b/.github/workflows/kernel-demos.yml
index 556613ad7..94d5c73e2 100644
--- a/.github/workflows/kernel-demos.yml
+++ b/.github/workflows/kernel-demos.yml
@@ -284,6 +284,16 @@ jobs:
         working-directory: FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC
         run: make -j
 
+      - name: Build CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC Demo
+        shell: bash
+        working-directory: FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC
+        run: cmake -S . -B build && make -j -C build all
+
+      - name: Build CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC Demo
+        shell: bash
+        working-directory: FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC
+        run: cmake -S . -B build && make -j -C build all
+
       - name: Build CORTEX_LM3S102_GCC Demo
         shell: bash
         working-directory: FreeRTOS/Demo/CORTEX_LM3S102_GCC

From ccbbf04e5b25b4824429d989f72c4a78c99020d7 Mon Sep 17 00:00:00 2001
From: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Date: Thu, 4 Apr 2024 14:29:36 +0800
Subject: [PATCH 244/424] Update coverity example README (#1020)

* Update coverity example README

* Update main.c for comment

---------

Co-authored-by: Ubuntu <ubuntu@ip-172-31-34-245.ap-northeast-1.compute.internal>
---
 examples/cmake_example/main.c | 44 +++++++++++++++++++++--------------
 examples/coverity/README.md   |  7 +++---
 2 files changed, 30 insertions(+), 21 deletions(-)

diff --git a/examples/cmake_example/main.c b/examples/cmake_example/main.c
index f357b2f91..00c5405b3 100644
--- a/examples/cmake_example/main.c
+++ b/examples/cmake_example/main.c
@@ -43,7 +43,13 @@
 /* Standard includes. */
 #include <stdio.h>
 
-void exampleTask( void * parameters )
+/*-----------------------------------------------------------*/
+
+static void exampleTask( void * parameters );
+
+/*-----------------------------------------------------------*/
+
+static void exampleTask( void * parameters )
 {
     /* Unused parameters. */
     ( void ) parameters;
@@ -61,15 +67,15 @@ void main( void )
     static StaticTask_t exampleTaskTCB;
     static StackType_t exampleTaskStack[ configMINIMAL_STACK_SIZE ];
 
-    printf( "Example FreeRTOS Project\n" );
+    ( void ) printf( "Example FreeRTOS Project\n" );
 
-    xTaskCreateStatic( exampleTask,
-                       "example",
-                       configMINIMAL_STACK_SIZE,
-                       NULL,
-                       configMAX_PRIORITIES - 1,
-                       &( exampleTaskStack[ 0 ] ),
-                       &( exampleTaskTCB ) );
+    ( void ) xTaskCreateStatic( exampleTask,
+                                "example",
+                                configMINIMAL_STACK_SIZE,
+                                NULL,
+                                configMAX_PRIORITIES - 1U,
+                                &( exampleTaskStack[ 0 ] ),
+                                &( exampleTaskTCB ) );
 
     /* Start the scheduler. */
     vTaskStartScheduler();
@@ -81,12 +87,16 @@ void main( void )
 }
 /*-----------------------------------------------------------*/
 
-void vApplicationStackOverflowHook( TaskHandle_t xTask,
-                                    char * pcTaskName )
-{
-    /* Check pcTaskName for the name of the offending task,
-     * or pxCurrentTCB if pcTaskName has itself been corrupted. */
-    ( void ) xTask;
-    ( void ) pcTaskName;
-}
+#if ( configCHECK_FOR_STACK_OVERFLOW > 0 )
+
+    void vApplicationStackOverflowHook( TaskHandle_t xTask,
+                                        char * pcTaskName )
+    {
+        /* Check pcTaskName for the name of the offending task,
+         * or pxCurrentTCB if pcTaskName has itself been corrupted. */
+        ( void ) xTask;
+        ( void ) pcTaskName;
+    }
+
+#endif /* #if ( configCHECK_FOR_STACK_OVERFLOW > 0 ) */
 /*-----------------------------------------------------------*/
diff --git a/examples/coverity/README.md b/examples/coverity/README.md
index 0daed7b22..6055e7133 100644
--- a/examples/coverity/README.md
+++ b/examples/coverity/README.md
@@ -4,7 +4,7 @@ run [Synopsys Coverity](https://www.synopsys.com/software-integrity/security-tes
 for checking MISRA compliance.
 
 > **Note**
-Coverity version 2022.6.1 incorrectly infers the type of `pdTRUE` and `pdFALSE`
+Coverity version 2023.6.1 incorrectly infers the type of `pdTRUE` and `pdFALSE`
 as boolean because of their names, resulting in multiple false positive warnings
 about type mismatch. We replace `pdTRUE` with `pdPASS` and `pdFALSE` with
 `pdFAIL` to avoid these false positive warnings. This workaround will not be
@@ -40,15 +40,14 @@ commands in a terminal:
 3. Build the (pseudo) application:
   ~~~
   cd build/
-  cov-build --emit-complementary-info --dir cov-out make
+  cov-build --emit-complementary-info --dir cov-out make coverity
   ~~~
 4. Go to the Coverity output directory (`cov-out`) and begin Coverity static
    analysis:
   ~~~
-  cd cov-out/
   cov-analyze --dir ./cov-out \
     --coding-standard-config ../examples/coverity/coverity_misra.config \
-    --tu-pattern "file('.*/FreeRTOS/Source/[A-Za-z_]*\.c')
+    --tu-pattern "file('[A-Za-z_]+\.c')"
   ~~~
 5. Generate the HTML report:
   ~~~

From 8c49c54987bc5f1d69cdb48a33d327f43c5f3668 Mon Sep 17 00:00:00 2001
From: Kody Stribrny <89810515+kstribrnAmzn@users.noreply.github.com>
Date: Thu, 4 Apr 2024 22:10:43 -0700
Subject: [PATCH 245/424] Fix TFM about link (#1021)

This page does not look to
exist anymore which is
failing our link verifier
check.
---
 portable/ThirdParty/GCC/ARM_TFM/README.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/portable/ThirdParty/GCC/ARM_TFM/README.md b/portable/ThirdParty/GCC/ARM_TFM/README.md
index b1d49fd71..ae2962447 100644
--- a/portable/ThirdParty/GCC/ARM_TFM/README.md
+++ b/portable/ThirdParty/GCC/ARM_TFM/README.md
@@ -10,7 +10,7 @@ to design security into a device from the ground up. PSA is made up of four key
 stages: analyze, architect, implement, and certify. See [PSA Resource Page](https://developer.arm.com/architectures/security-architectures/platform-security-architecture).
 
 TF-M is an open source project. It provides a reference implementation of PSA
-for Arm M-profile architecture. Please get the details from this [link](https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/about/).
+for Arm M-profile architecture. Please get the details from this [link](https://www.trustedfirmware.org/about/).
 
 # Derivation of the source code
 

From 8afb3a5b824b53847bbc99124ba4e4e94ebe80aa Mon Sep 17 00:00:00 2001
From: Florian La Roche <florian.laroche@gmail.com>
Date: Tue, 9 Apr 2024 02:50:55 +0200
Subject: [PATCH 246/424] fix typos in comments: interace -> interface, swtich
 -> switch (#1022)

Fix typos in comments: interace -> interface, swtich -> switch.

Signed-off-by: Florian La Roche <Florian.LaRoche@gmail.com>
---
 portable/GCC/ARM_AARCH64/README.md              | 2 +-
 portable/GCC/ARM_AARCH64_SRE/README.md          | 2 +-
 portable/GCC/ARM_CA53_64_BIT/README.md          | 4 ++--
 portable/GCC/ARM_CA53_64_BIT_SRE/README.md      | 4 ++--
 portable/GCC/ARM_CA9/portASM.S                  | 2 +-
 portable/GCC/ARM_CR5/portASM.S                  | 2 +-
 portable/GCC/ARM_CRx_MPU/portASM.S              | 4 ++--
 portable/GCC/ARM_CRx_No_GIC/portASM.S           | 2 +-
 portable/IAR/ARM_CRx_No_GIC/portASM.s           | 2 +-
 portable/RVDS/ARM_CA9/portASM.s                 | 2 +-
 portable/ThirdParty/CDK/T-HEAD_CK802/port.c     | 2 +-
 portable/ThirdParty/XCC/Xtensa/xtensa_context.h | 2 +-
 12 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/portable/GCC/ARM_AARCH64/README.md b/portable/GCC/ARM_AARCH64/README.md
index 0bee96951..60f670177 100644
--- a/portable/GCC/ARM_AARCH64/README.md
+++ b/portable/GCC/ARM_AARCH64/README.md
@@ -20,4 +20,4 @@ This port is generic and can be used as a starting point for Armv8-A
 application processors.
 
 * ARM_AARCH64
-    * Memory mapped interace to access Arm GIC registers
+    * Memory mapped interface to access Arm GIC registers
diff --git a/portable/GCC/ARM_AARCH64_SRE/README.md b/portable/GCC/ARM_AARCH64_SRE/README.md
index 4c9a55af0..129b0e3ec 100644
--- a/portable/GCC/ARM_AARCH64_SRE/README.md
+++ b/portable/GCC/ARM_AARCH64_SRE/README.md
@@ -20,4 +20,4 @@ This port is generic and can be used as a starting point for Armv8-A
 application processors.
 
 * ARM_AARCH64_SRE
-    * System Register interace to access Arm GIC registers
+    * System Register interface to access Arm GIC registers
diff --git a/portable/GCC/ARM_CA53_64_BIT/README.md b/portable/GCC/ARM_CA53_64_BIT/README.md
index a8df29e91..578b475d9 100644
--- a/portable/GCC/ARM_CA53_64_BIT/README.md
+++ b/portable/GCC/ARM_CA53_64_BIT/README.md
@@ -4,7 +4,7 @@ Initial port to support Armv8-A architecture in FreeRTOS kernel was written for
 Arm Cortex-A53 processor.
 
 * ARM_CA53_64_BIT
-    * Memory mapped interace to access Arm GIC registers
+    * Memory mapped interface to access Arm GIC registers
 
 This port is generic and can be used as a starting point for other Armv8-A
 application processors. Therefore, the port `ARM_CA53_64_BIT` is renamed as
@@ -13,4 +13,4 @@ should migrate to renamed port `ARM_AARCH64`.
 
 **NOTE**
 
-This port uses memory mapped interace to access Arm GIC registers.
+This port uses memory mapped interface to access Arm GIC registers.
diff --git a/portable/GCC/ARM_CA53_64_BIT_SRE/README.md b/portable/GCC/ARM_CA53_64_BIT_SRE/README.md
index a5d415fc2..9951f81c8 100644
--- a/portable/GCC/ARM_CA53_64_BIT_SRE/README.md
+++ b/portable/GCC/ARM_CA53_64_BIT_SRE/README.md
@@ -4,7 +4,7 @@ Initial port to support Armv8-A architecture in FreeRTOS kernel was written for
 Arm Cortex-A53 processor.
 
 * ARM_CA53_64_BIT_SRE
-    * System Register interace to access Arm GIC registers
+    * System Register interface to access Arm GIC registers
 
 This port is generic and can be used as a starting point for other Armv8-A
 application processors. Therefore, the port `ARM_AARCH64_SRE` is renamed as
@@ -13,4 +13,4 @@ should migrate to renamed port `ARM_AARCH64_SRE`.
 
 **NOTE**
 
-This port uses System Register interace to access Arm GIC registers.
+This port uses System Register interface to access Arm GIC registers.
diff --git a/portable/GCC/ARM_CA9/portASM.S b/portable/GCC/ARM_CA9/portASM.S
index 6efeaba77..5e4b870b9 100644
--- a/portable/GCC/ARM_CA9/portASM.S
+++ b/portable/GCC/ARM_CA9/portASM.S
@@ -246,7 +246,7 @@ exit_without_switch:
     MOVS    PC, LR
 
 switch_before_exit:
-    /* A context swtich is to be performed.  Clear the context switch pending
+    /* A context switch is to be performed.  Clear the context switch pending
     flag. */
     MOV     r0, #0
     STR     r0, [r1]
diff --git a/portable/GCC/ARM_CR5/portASM.S b/portable/GCC/ARM_CR5/portASM.S
index e14cddd07..1590ee4e8 100644
--- a/portable/GCC/ARM_CR5/portASM.S
+++ b/portable/GCC/ARM_CR5/portASM.S
@@ -242,7 +242,7 @@ exit_without_switch:
     MOVS    PC, LR
 
 switch_before_exit:
-    /* A context swtich is to be performed.  Clear the context switch pending
+    /* A context switch is to be performed.  Clear the context switch pending
     flag. */
     MOV     r0, #0
     STR     r0, [r1]
diff --git a/portable/GCC/ARM_CRx_MPU/portASM.S b/portable/GCC/ARM_CRx_MPU/portASM.S
index cac0fc406..bc0345a80 100644
--- a/portable/GCC/ARM_CRx_MPU/portASM.S
+++ b/portable/GCC/ARM_CRx_MPU/portASM.S
@@ -446,7 +446,7 @@ FreeRTOS_IRQ_Handler:
      * ulPortInterruptNesting. */
     STR     R1, [R0]
 
-    /* Context swtich is only performed when interrupt nesting count is 0. */
+    /* Context switch is only performed when interrupt nesting count is 0. */
     CMP     R1, #0
     BNE     exit_without_switch
 
@@ -464,7 +464,7 @@ exit_without_switch:
     RFE     SP!
 
 switch_before_exit:
-    /* A context swtich is to be performed. Clear ulPortYieldRequired. R1 holds
+    /* A context switch is to be performed. Clear ulPortYieldRequired. R1 holds
      * the address of ulPortYieldRequired. */
     MOV     R0, #0
     STR     R0, [R1]
diff --git a/portable/GCC/ARM_CRx_No_GIC/portASM.S b/portable/GCC/ARM_CRx_No_GIC/portASM.S
index 960d46f7e..349a940d9 100644
--- a/portable/GCC/ARM_CRx_No_GIC/portASM.S
+++ b/portable/GCC/ARM_CRx_No_GIC/portASM.S
@@ -223,7 +223,7 @@ exit_without_switch:
     MOVS    PC, LR
 
 switch_before_exit:
-    /* A context swtich is to be performed.  Clear the context switch pending
+    /* A context switch is to be performed.  Clear the context switch pending
     flag. */
     MOV     r0, #0
     STR     r0, [r1]
diff --git a/portable/IAR/ARM_CRx_No_GIC/portASM.s b/portable/IAR/ARM_CRx_No_GIC/portASM.s
index fb2a797ac..f37ad570b 100644
--- a/portable/IAR/ARM_CRx_No_GIC/portASM.s
+++ b/portable/IAR/ARM_CRx_No_GIC/portASM.s
@@ -215,7 +215,7 @@ exit_without_switch:
     MOVS    PC, LR
 
 switch_before_exit:
-    /* A context swtich is to be performed.  Clear the context switch pending
+    /* A context switch is to be performed.  Clear the context switch pending
     flag. */
     MOV     r0, #0
     STR     r0, [r1]
diff --git a/portable/RVDS/ARM_CA9/portASM.s b/portable/RVDS/ARM_CA9/portASM.s
index f099ef2aa..771b140da 100644
--- a/portable/RVDS/ARM_CA9/portASM.s
+++ b/portable/RVDS/ARM_CA9/portASM.s
@@ -143,7 +143,7 @@ exit_without_switch
     MOVS    PC, LR
 
 switch_before_exit
-    ; A context swtich is to be performed.  Clear the context switch pending
+    ; A context switch is to be performed.  Clear the context switch pending
     ; flag.
     MOV     r0, #0
     STR     r0, [r1]
diff --git a/portable/ThirdParty/CDK/T-HEAD_CK802/port.c b/portable/ThirdParty/CDK/T-HEAD_CK802/port.c
index 6e953a0cb..8f5ab7d26 100644
--- a/portable/ThirdParty/CDK/T-HEAD_CK802/port.c
+++ b/portable/ThirdParty/CDK/T-HEAD_CK802/port.c
@@ -32,7 +32,7 @@ extern void vPortStartTask( void );
  * will be set to 0 prior to the first task being started. */
 portLONG ulCriticalNesting = 0x9999UL;
 
-/* Used to record one tack want to swtich task after enter critical area, we need know it
+/* Used to record one tack want to switch task after enter critical area, we need know it
  * and implement task switch after exit critical area */
 portLONG pendsvflag = 0;
 
diff --git a/portable/ThirdParty/XCC/Xtensa/xtensa_context.h b/portable/ThirdParty/XCC/Xtensa/xtensa_context.h
index 256e71568..8756213ea 100644
--- a/portable/ThirdParty/XCC/Xtensa/xtensa_context.h
+++ b/portable/ThirdParty/XCC/Xtensa/xtensa_context.h
@@ -254,7 +254,7 @@ STRUCT_END(XtSolFrame)
     The contents of a non-running thread's CPENABLE register.
     It represents the co-processors owned (and whose state is still needed)
     by the thread. When a thread is preempted, its CPENABLE is saved here.
-    When a thread solicits a context-swtich, its CPENABLE is cleared - the
+    When a thread solicits a context-switch, its CPENABLE is cleared - the
     compiler has saved the (caller-saved) co-proc state if it needs to.
     When a non-running thread loses ownership of a CP, its bit is cleared.
     When a thread runs, it's XT_CPENABLE is loaded into the CPENABLE reg.

From f0ff3834bc6db8d515fb43d9bb5bf66c42dcf4bf Mon Sep 17 00:00:00 2001
From: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Date: Tue, 9 Apr 2024 10:00:23 +0530
Subject: [PATCH 247/424] Fix spelling in comment (#1024)

Co-authored-by: ActoryOu <jay2002824@gmail.com>
---
 portable/ARMv8M/non_secure/port.c            | 2 +-
 portable/GCC/ARM_CM0/port.c                  | 2 +-
 portable/GCC/ARM_CM23/non_secure/port.c      | 2 +-
 portable/GCC/ARM_CM23_NTZ/non_secure/port.c  | 2 +-
 portable/GCC/ARM_CM3/port.c                  | 2 +-
 portable/GCC/ARM_CM33/non_secure/port.c      | 2 +-
 portable/GCC/ARM_CM33_NTZ/non_secure/port.c  | 2 +-
 portable/GCC/ARM_CM35P/non_secure/port.c     | 2 +-
 portable/GCC/ARM_CM35P_NTZ/non_secure/port.c | 2 +-
 portable/GCC/ARM_CM3_MPU/port.c              | 2 +-
 portable/GCC/ARM_CM4F/port.c                 | 2 +-
 portable/GCC/ARM_CM4_MPU/port.c              | 2 +-
 portable/GCC/ARM_CM55/non_secure/port.c      | 2 +-
 portable/GCC/ARM_CM55_NTZ/non_secure/port.c  | 2 +-
 portable/GCC/ARM_CM7/r0p1/port.c             | 2 +-
 portable/GCC/ARM_CM85/non_secure/port.c      | 2 +-
 portable/GCC/ARM_CM85_NTZ/non_secure/port.c  | 2 +-
 portable/IAR/ARM_CM0/port.c                  | 2 +-
 portable/IAR/ARM_CM23/non_secure/port.c      | 2 +-
 portable/IAR/ARM_CM23_NTZ/non_secure/port.c  | 2 +-
 portable/IAR/ARM_CM3/port.c                  | 2 +-
 portable/IAR/ARM_CM33/non_secure/port.c      | 2 +-
 portable/IAR/ARM_CM33_NTZ/non_secure/port.c  | 2 +-
 portable/IAR/ARM_CM35P/non_secure/port.c     | 2 +-
 portable/IAR/ARM_CM35P_NTZ/non_secure/port.c | 2 +-
 portable/IAR/ARM_CM4F/port.c                 | 2 +-
 portable/IAR/ARM_CM4F_MPU/port.c             | 2 +-
 portable/IAR/ARM_CM55/non_secure/port.c      | 2 +-
 portable/IAR/ARM_CM55_NTZ/non_secure/port.c  | 2 +-
 portable/IAR/ARM_CM7/r0p1/port.c             | 2 +-
 portable/IAR/ARM_CM85/non_secure/port.c      | 2 +-
 portable/IAR/ARM_CM85_NTZ/non_secure/port.c  | 2 +-
 portable/RVDS/ARM_CM4_MPU/port.c             | 2 +-
 33 files changed, 33 insertions(+), 33 deletions(-)

diff --git a/portable/ARMv8M/non_secure/port.c b/portable/ARMv8M/non_secure/port.c
index 329de05d7..99e1e148b 100644
--- a/portable/ARMv8M/non_secure/port.c
+++ b/portable/ARMv8M/non_secure/port.c
@@ -1621,7 +1621,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
     /* An application can install FreeRTOS interrupt handlers in one of the
-     * folllowing ways:
+     * following ways:
      * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
      *    for SVCall and PendSV interrupts respectively.
      * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
diff --git a/portable/GCC/ARM_CM0/port.c b/portable/GCC/ARM_CM0/port.c
index 4ee1d9494..608afa5de 100644
--- a/portable/GCC/ARM_CM0/port.c
+++ b/portable/GCC/ARM_CM0/port.c
@@ -1265,7 +1265,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
     /* An application can install FreeRTOS interrupt handlers in one of the
-     * folllowing ways:
+     * following ways:
      * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
      *    for SVCall and PendSV interrupts respectively.
      * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
diff --git a/portable/GCC/ARM_CM23/non_secure/port.c b/portable/GCC/ARM_CM23/non_secure/port.c
index 329de05d7..99e1e148b 100644
--- a/portable/GCC/ARM_CM23/non_secure/port.c
+++ b/portable/GCC/ARM_CM23/non_secure/port.c
@@ -1621,7 +1621,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
     /* An application can install FreeRTOS interrupt handlers in one of the
-     * folllowing ways:
+     * following ways:
      * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
      *    for SVCall and PendSV interrupts respectively.
      * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
index 329de05d7..99e1e148b 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
@@ -1621,7 +1621,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
     /* An application can install FreeRTOS interrupt handlers in one of the
-     * folllowing ways:
+     * following ways:
      * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
      *    for SVCall and PendSV interrupts respectively.
      * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
diff --git a/portable/GCC/ARM_CM3/port.c b/portable/GCC/ARM_CM3/port.c
index 1a9c9b072..5adf39bd7 100644
--- a/portable/GCC/ARM_CM3/port.c
+++ b/portable/GCC/ARM_CM3/port.c
@@ -269,7 +269,7 @@ static void prvPortStartFirstTask( void )
 BaseType_t xPortStartScheduler( void )
 {
     /* An application can install FreeRTOS interrupt handlers in one of the
-     * folllowing ways:
+     * following ways:
      * 1. Direct Routing - Install the functions vPortSVCHandler and
      *    xPortPendSVHandler for SVCall and PendSV interrupts respectively.
      * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
diff --git a/portable/GCC/ARM_CM33/non_secure/port.c b/portable/GCC/ARM_CM33/non_secure/port.c
index 329de05d7..99e1e148b 100644
--- a/portable/GCC/ARM_CM33/non_secure/port.c
+++ b/portable/GCC/ARM_CM33/non_secure/port.c
@@ -1621,7 +1621,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
     /* An application can install FreeRTOS interrupt handlers in one of the
-     * folllowing ways:
+     * following ways:
      * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
      *    for SVCall and PendSV interrupts respectively.
      * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
index 329de05d7..99e1e148b 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
@@ -1621,7 +1621,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
     /* An application can install FreeRTOS interrupt handlers in one of the
-     * folllowing ways:
+     * following ways:
      * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
      *    for SVCall and PendSV interrupts respectively.
      * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
diff --git a/portable/GCC/ARM_CM35P/non_secure/port.c b/portable/GCC/ARM_CM35P/non_secure/port.c
index 329de05d7..99e1e148b 100644
--- a/portable/GCC/ARM_CM35P/non_secure/port.c
+++ b/portable/GCC/ARM_CM35P/non_secure/port.c
@@ -1621,7 +1621,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
     /* An application can install FreeRTOS interrupt handlers in one of the
-     * folllowing ways:
+     * following ways:
      * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
      *    for SVCall and PendSV interrupts respectively.
      * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c b/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
index 329de05d7..99e1e148b 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
@@ -1621,7 +1621,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
     /* An application can install FreeRTOS interrupt handlers in one of the
-     * folllowing ways:
+     * following ways:
      * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
      *    for SVCall and PendSV interrupts respectively.
      * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
diff --git a/portable/GCC/ARM_CM3_MPU/port.c b/portable/GCC/ARM_CM3_MPU/port.c
index 872882d77..6a36f1a88 100644
--- a/portable/GCC/ARM_CM3_MPU/port.c
+++ b/portable/GCC/ARM_CM3_MPU/port.c
@@ -744,7 +744,7 @@ static void prvRestoreContextOfFirstTask( void )
 BaseType_t xPortStartScheduler( void )
 {
     /* An application can install FreeRTOS interrupt handlers in one of the
-     * folllowing ways:
+     * following ways:
      * 1. Direct Routing - Install the functions vPortSVCHandler and
      *    xPortPendSVHandler for SVCall and PendSV interrupts respectively.
      * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
diff --git a/portable/GCC/ARM_CM4F/port.c b/portable/GCC/ARM_CM4F/port.c
index ecd07f01c..c836999ec 100644
--- a/portable/GCC/ARM_CM4F/port.c
+++ b/portable/GCC/ARM_CM4F/port.c
@@ -312,7 +312,7 @@ BaseType_t xPortStartScheduler( void )
     configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
 
     /* An application can install FreeRTOS interrupt handlers in one of the
-     * folllowing ways:
+     * following ways:
      * 1. Direct Routing - Install the functions vPortSVCHandler and
      *    xPortPendSVHandler for SVCall and PendSV interrupts respectively.
      * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
diff --git a/portable/GCC/ARM_CM4_MPU/port.c b/portable/GCC/ARM_CM4_MPU/port.c
index 210165544..6e6f9de75 100644
--- a/portable/GCC/ARM_CM4_MPU/port.c
+++ b/portable/GCC/ARM_CM4_MPU/port.c
@@ -830,7 +830,7 @@ BaseType_t xPortStartScheduler( void )
     #endif
 
     /* An application can install FreeRTOS interrupt handlers in one of the
-     * folllowing ways:
+     * following ways:
      * 1. Direct Routing - Install the functions vPortSVCHandler and
      *    xPortPendSVHandler for SVCall and PendSV interrupts respectively.
      * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
diff --git a/portable/GCC/ARM_CM55/non_secure/port.c b/portable/GCC/ARM_CM55/non_secure/port.c
index 329de05d7..99e1e148b 100644
--- a/portable/GCC/ARM_CM55/non_secure/port.c
+++ b/portable/GCC/ARM_CM55/non_secure/port.c
@@ -1621,7 +1621,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
     /* An application can install FreeRTOS interrupt handlers in one of the
-     * folllowing ways:
+     * following ways:
      * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
      *    for SVCall and PendSV interrupts respectively.
      * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/port.c b/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
index 329de05d7..99e1e148b 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
@@ -1621,7 +1621,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
     /* An application can install FreeRTOS interrupt handlers in one of the
-     * folllowing ways:
+     * following ways:
      * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
      *    for SVCall and PendSV interrupts respectively.
      * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
diff --git a/portable/GCC/ARM_CM7/r0p1/port.c b/portable/GCC/ARM_CM7/r0p1/port.c
index 220be503f..aaac2a7cb 100644
--- a/portable/GCC/ARM_CM7/r0p1/port.c
+++ b/portable/GCC/ARM_CM7/r0p1/port.c
@@ -300,7 +300,7 @@ static void prvPortStartFirstTask( void )
 BaseType_t xPortStartScheduler( void )
 {
     /* An application can install FreeRTOS interrupt handlers in one of the
-     * folllowing ways:
+     * following ways:
      * 1. Direct Routing - Install the functions vPortSVCHandler and
      *    xPortPendSVHandler for SVCall and PendSV interrupts respectively.
      * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
diff --git a/portable/GCC/ARM_CM85/non_secure/port.c b/portable/GCC/ARM_CM85/non_secure/port.c
index 329de05d7..99e1e148b 100644
--- a/portable/GCC/ARM_CM85/non_secure/port.c
+++ b/portable/GCC/ARM_CM85/non_secure/port.c
@@ -1621,7 +1621,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
     /* An application can install FreeRTOS interrupt handlers in one of the
-     * folllowing ways:
+     * following ways:
      * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
      *    for SVCall and PendSV interrupts respectively.
      * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/port.c b/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
index 329de05d7..99e1e148b 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
@@ -1621,7 +1621,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
     /* An application can install FreeRTOS interrupt handlers in one of the
-     * folllowing ways:
+     * following ways:
      * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
      *    for SVCall and PendSV interrupts respectively.
      * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
diff --git a/portable/IAR/ARM_CM0/port.c b/portable/IAR/ARM_CM0/port.c
index 634833389..809b6c417 100644
--- a/portable/IAR/ARM_CM0/port.c
+++ b/portable/IAR/ARM_CM0/port.c
@@ -180,7 +180,7 @@ static void prvTaskExitError( void )
 BaseType_t xPortStartScheduler( void )
 {
     /* An application can install FreeRTOS interrupt handlers in one of the
-     * folllowing ways:
+     * following ways:
      * 1. Direct Routing - Install the function xPortPendSVHandler for PendSV
      *    interrupt.
      * 2. Indirect Routing - Install separate handler for PendSV interrupt and
diff --git a/portable/IAR/ARM_CM23/non_secure/port.c b/portable/IAR/ARM_CM23/non_secure/port.c
index 329de05d7..99e1e148b 100644
--- a/portable/IAR/ARM_CM23/non_secure/port.c
+++ b/portable/IAR/ARM_CM23/non_secure/port.c
@@ -1621,7 +1621,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
     /* An application can install FreeRTOS interrupt handlers in one of the
-     * folllowing ways:
+     * following ways:
      * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
      *    for SVCall and PendSV interrupts respectively.
      * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
index 329de05d7..99e1e148b 100644
--- a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
@@ -1621,7 +1621,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
     /* An application can install FreeRTOS interrupt handlers in one of the
-     * folllowing ways:
+     * following ways:
      * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
      *    for SVCall and PendSV interrupts respectively.
      * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
diff --git a/portable/IAR/ARM_CM3/port.c b/portable/IAR/ARM_CM3/port.c
index d254dc255..5d0d5aab5 100644
--- a/portable/IAR/ARM_CM3/port.c
+++ b/portable/IAR/ARM_CM3/port.c
@@ -223,7 +223,7 @@ static void prvTaskExitError( void )
 BaseType_t xPortStartScheduler( void )
 {
     /* An application can install FreeRTOS interrupt handlers in one of the
-     * folllowing ways:
+     * following ways:
      * 1. Direct Routing - Install the functions vPortSVCHandler and
      *    xPortPendSVHandler for SVCall and PendSV interrupts respectively.
      * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
diff --git a/portable/IAR/ARM_CM33/non_secure/port.c b/portable/IAR/ARM_CM33/non_secure/port.c
index 329de05d7..99e1e148b 100644
--- a/portable/IAR/ARM_CM33/non_secure/port.c
+++ b/portable/IAR/ARM_CM33/non_secure/port.c
@@ -1621,7 +1621,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
     /* An application can install FreeRTOS interrupt handlers in one of the
-     * folllowing ways:
+     * following ways:
      * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
      *    for SVCall and PendSV interrupts respectively.
      * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
index 329de05d7..99e1e148b 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
@@ -1621,7 +1621,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
     /* An application can install FreeRTOS interrupt handlers in one of the
-     * folllowing ways:
+     * following ways:
      * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
      *    for SVCall and PendSV interrupts respectively.
      * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
diff --git a/portable/IAR/ARM_CM35P/non_secure/port.c b/portable/IAR/ARM_CM35P/non_secure/port.c
index 329de05d7..99e1e148b 100644
--- a/portable/IAR/ARM_CM35P/non_secure/port.c
+++ b/portable/IAR/ARM_CM35P/non_secure/port.c
@@ -1621,7 +1621,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
     /* An application can install FreeRTOS interrupt handlers in one of the
-     * folllowing ways:
+     * following ways:
      * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
      *    for SVCall and PendSV interrupts respectively.
      * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c b/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
index 329de05d7..99e1e148b 100644
--- a/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
@@ -1621,7 +1621,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
     /* An application can install FreeRTOS interrupt handlers in one of the
-     * folllowing ways:
+     * following ways:
      * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
      *    for SVCall and PendSV interrupts respectively.
      * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
diff --git a/portable/IAR/ARM_CM4F/port.c b/portable/IAR/ARM_CM4F/port.c
index 18b433282..a4e2193b2 100644
--- a/portable/IAR/ARM_CM4F/port.c
+++ b/portable/IAR/ARM_CM4F/port.c
@@ -261,7 +261,7 @@ BaseType_t xPortStartScheduler( void )
     configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
 
     /* An application can install FreeRTOS interrupt handlers in one of the
-     * folllowing ways:
+     * following ways:
      * 1. Direct Routing - Install the functions vPortSVCHandler and
      *    xPortPendSVHandler for SVCall and PendSV interrupts respectively.
      * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
diff --git a/portable/IAR/ARM_CM4F_MPU/port.c b/portable/IAR/ARM_CM4F_MPU/port.c
index f5772c1d8..da070c56a 100644
--- a/portable/IAR/ARM_CM4F_MPU/port.c
+++ b/portable/IAR/ARM_CM4F_MPU/port.c
@@ -725,7 +725,7 @@ BaseType_t xPortStartScheduler( void )
     #endif
 
     /* An application can install FreeRTOS interrupt handlers in one of the
-     * folllowing ways:
+     * following ways:
      * 1. Direct Routing - Install the functions vPortSVCHandler and
      *    xPortPendSVHandler for SVCall and PendSV interrupts respectively.
      * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
diff --git a/portable/IAR/ARM_CM55/non_secure/port.c b/portable/IAR/ARM_CM55/non_secure/port.c
index 329de05d7..99e1e148b 100644
--- a/portable/IAR/ARM_CM55/non_secure/port.c
+++ b/portable/IAR/ARM_CM55/non_secure/port.c
@@ -1621,7 +1621,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
     /* An application can install FreeRTOS interrupt handlers in one of the
-     * folllowing ways:
+     * following ways:
      * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
      *    for SVCall and PendSV interrupts respectively.
      * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/port.c b/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
index 329de05d7..99e1e148b 100644
--- a/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
@@ -1621,7 +1621,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
     /* An application can install FreeRTOS interrupt handlers in one of the
-     * folllowing ways:
+     * following ways:
      * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
      *    for SVCall and PendSV interrupts respectively.
      * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
diff --git a/portable/IAR/ARM_CM7/r0p1/port.c b/portable/IAR/ARM_CM7/r0p1/port.c
index 7def0060e..35a5b0b1b 100644
--- a/portable/IAR/ARM_CM7/r0p1/port.c
+++ b/portable/IAR/ARM_CM7/r0p1/port.c
@@ -249,7 +249,7 @@ static void prvTaskExitError( void )
 BaseType_t xPortStartScheduler( void )
 {
     /* An application can install FreeRTOS interrupt handlers in one of the
-     * folllowing ways:
+     * following ways:
      * 1. Direct Routing - Install the functions vPortSVCHandler and
      *    xPortPendSVHandler for SVCall and PendSV interrupts respectively.
      * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
diff --git a/portable/IAR/ARM_CM85/non_secure/port.c b/portable/IAR/ARM_CM85/non_secure/port.c
index 329de05d7..99e1e148b 100644
--- a/portable/IAR/ARM_CM85/non_secure/port.c
+++ b/portable/IAR/ARM_CM85/non_secure/port.c
@@ -1621,7 +1621,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
     /* An application can install FreeRTOS interrupt handlers in one of the
-     * folllowing ways:
+     * following ways:
      * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
      *    for SVCall and PendSV interrupts respectively.
      * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/port.c b/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
index 329de05d7..99e1e148b 100644
--- a/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
@@ -1621,7 +1621,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 {
     /* An application can install FreeRTOS interrupt handlers in one of the
-     * folllowing ways:
+     * following ways:
      * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
      *    for SVCall and PendSV interrupts respectively.
      * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
diff --git a/portable/RVDS/ARM_CM4_MPU/port.c b/portable/RVDS/ARM_CM4_MPU/port.c
index 37d13e8b8..87af70e3d 100644
--- a/portable/RVDS/ARM_CM4_MPU/port.c
+++ b/portable/RVDS/ARM_CM4_MPU/port.c
@@ -829,7 +829,7 @@ BaseType_t xPortStartScheduler( void )
     #endif
 
     /* An application can install FreeRTOS interrupt handlers in one of the
-     * folllowing ways:
+     * following ways:
      * 1. Direct Routing - Install the functions vPortSVCHandler and
      *    xPortPendSVHandler for SVCall and PendSV interrupts respectively.
      * 2. Indirect Routing - Install separate handlers for SVCall and PendSV

From 5da55ba8ade5f752104a3138609013d6d086ef31 Mon Sep 17 00:00:00 2001
From: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Date: Tue, 9 Apr 2024 10:31:53 +0530
Subject: [PATCH 248/424] Add configCHECK_HANDLER_INSTALLATION description in
 template file (#1025)

Add configconfigCHECK_HANDLER_INSTALLATION description in template
configuration file
---
 .../template_configuration/FreeRTOSConfig.h    | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/examples/template_configuration/FreeRTOSConfig.h b/examples/template_configuration/FreeRTOSConfig.h
index 74b7cea96..ed3a430f1 100644
--- a/examples/template_configuration/FreeRTOSConfig.h
+++ b/examples/template_configuration/FreeRTOSConfig.h
@@ -571,6 +571,24 @@
  * for the Cortex-M23,Cortex-M33 and Cortex-M35P ports. */
 #define configENABLE_MVE                  1
 
+/******************************************************************************/
+/* ARMv7-M and ARMv8-M port Specific Configuration definitions. ***************/
+/******************************************************************************/
+
+/* Set configCHECK_HANDLER_INSTALLATION to 1 to enable additional asserts to verify
+ * that the application has correctly installed FreeRTOS interrupt handlers.
+ *
+ * An application can install FreeRTOS interrupt handlers in one of the following ways:
+ *   1. Direct Routing  -  Install the functions vPortSVCHandler and xPortPendSVHandler
+ *                         for SVC call and PendSV interrupts respectively.
+ *   2. Indirect Routing - Install separate handlers for SVC call and PendSV
+ *                         interrupts and route program control from those handlers
+ *                         to vPortSVCHandler and xPortPendSVHandler functions.
+ * The applications that use Indirect Routing must set configCHECK_HANDLER_INSTALLATION to 0.
+ *
+ * Defaults to 1 if left undefined. */
+#define configCHECK_HANDLER_INSTALLATION    1
+
 /******************************************************************************/
 /* Definitions that include or exclude functionality. *************************/
 /******************************************************************************/

From 6270e2aebfb24caead2dc928f31043cccd6b62fd Mon Sep 17 00:00:00 2001
From: Florian La Roche <florian.laroche@gmail.com>
Date: Tue, 9 Apr 2024 07:21:12 +0200
Subject: [PATCH 249/424] Update the memory alignment within the Cortex-R5 port
 asm code (#1023)

Update alignment in ARM_CR5 port.

This is the same patch as 553caa18ced4906cf5060823ada7a10e73c7b535
provided by Richard Barry for issue #426 (ARM_CA9).

Signed-off-by: Florian La Roche <Florian.LaRoche@gmail.com>
---
 portable/GCC/ARM_CR5/portASM.S | 16 ++++++++++++++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/portable/GCC/ARM_CR5/portASM.S b/portable/GCC/ARM_CR5/portASM.S
index 1590ee4e8..3c39ef1b6 100644
--- a/portable/GCC/ARM_CR5/portASM.S
+++ b/portable/GCC/ARM_CR5/portASM.S
@@ -76,8 +76,8 @@
 
         /* Save the floating point context, if any. */
         FMRXNE  R1,  FPSCR
-        VPUSHNE {D0-D15}
         PUSHNE  {R1}
+        VPUSHNE {D0-D15}
 
         /* Save ulPortTaskHasFPUContext itself. */
         PUSH    {R3}
@@ -110,8 +110,8 @@
         CMP     R1, #0
 
         /* Restore the floating point context, if any. */
-        POPNE   {R0}
         VPOPNE  {D0-D15}
+        POPNE   {R0}
         VMSRNE  FPSCR, R0
     #endif /* __ARM_FP */
 
@@ -147,8 +147,15 @@
 FreeRTOS_SWI_Handler:
     /* Save the context of the current task and select a new task to run. */
     portSAVE_CONTEXT
+
+    /* Ensure bit 2 of the stack pointer is clear. */
+    MOV     r2, sp
+    AND     r2, r2, #4
+    SUB     sp, sp, r2
+
     LDR R0, vTaskSwitchContextConst
     BLX R0
+
     portRESTORE_CONTEXT
 
 
@@ -256,6 +263,11 @@ switch_before_exit:
     POP     {LR}
     portSAVE_CONTEXT
 
+    /* Ensure bit 2 of the stack pointer is clear. */
+    MOV     r2, sp
+    AND     r2, r2, #4
+    SUB     sp, sp, r2
+
     /* Call the function that selects the new task to execute.
     vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD
     instructions, or 8 byte aligned stack allocated data.  LR does not need

From 030c1aa64634d4c8db65c6cd13391890dd10c46a Mon Sep 17 00:00:00 2001
From: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Date: Tue, 9 Apr 2024 15:26:34 +0530
Subject: [PATCH 250/424] Add event group and stream buffer config option in
 template (#1026)

* Add config descriptions in template configuration file

---------

Co-authored-by: GitHub Action <action@github.com>
---
 .../template_configuration/FreeRTOSConfig.h   | 24 ++++++++++++++++++-
 1 file changed, 23 insertions(+), 1 deletion(-)

diff --git a/examples/template_configuration/FreeRTOSConfig.h b/examples/template_configuration/FreeRTOSConfig.h
index ed3a430f1..c1c05966a 100644
--- a/examples/template_configuration/FreeRTOSConfig.h
+++ b/examples/template_configuration/FreeRTOSConfig.h
@@ -236,6 +236,28 @@
  * if configUSE_TIMERS is set to 1. */
 #define configTIMER_QUEUE_LENGTH        10
 
+/******************************************************************************/
+/* Event Group related definitions. *******************************************/
+/******************************************************************************/
+
+/* Set configUSE_EVENT_GROUPS to 1 to include event group functionality in the
+ * build. Set to 0 to exclude event group functionality from the build. The
+ * FreeRTOS/source/event_groups.c source file must be included in the build if
+ * configUSE_EVENT_GROUPS is set to 1. Defaults to 1 if left undefined. */
+
+#define configUSE_EVENT_GROUPS    1
+
+/******************************************************************************/
+/* Stream Buffer related definitions. *****************************************/
+/******************************************************************************/
+
+/* Set configUSE_STREAM_BUFFERS to 1 to include stream buffer functionality in
+ * the build. Set to 0 to exclude event group functionality from the build. The
+ * FreeRTOS/source/stream_buffer.c source file must be included in the build if
+ * configUSE_STREAM_BUFFERS is set to 1. Defaults to 1 if left undefined. */
+
+#define configUSE_STREAM_BUFFERS    1
+
 /******************************************************************************/
 /* Memory allocation related definitions. *************************************/
 /******************************************************************************/
@@ -431,7 +453,7 @@
 #define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY               1
 
 /* Set configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS to 1 to allow unprivileged
- * tasks enter critical sections (effectively mask interrupts).  Set to 0 to
+ * tasks enter critical sections (effectively mask interrupts). Set to 0 to
  * prevent unprivileged tasks entering critical sections.  Defaults to 1 if left
  * undefined.  Only used by the FreeRTOS Cortex-M MPU ports, not the standard
  * ARMv7-M Cortex-M port. */

From 2829f3eccc30f41f85d0989ea0b5a4354244880e Mon Sep 17 00:00:00 2001
From: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Date: Wed, 10 Apr 2024 20:58:48 +0530
Subject: [PATCH 251/424] Replace volatile with configLIST_VOLATILE (#1027)

---
 include/list.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/list.h b/include/list.h
index 091553dd1..0de51bb5a 100644
--- a/include/list.h
+++ b/include/list.h
@@ -172,7 +172,7 @@ typedef struct xLIST_ITEM ListItem_t;
 typedef struct xLIST
 {
     listFIRST_LIST_INTEGRITY_CHECK_VALUE      /**< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
-    volatile UBaseType_t uxNumberOfItems;
+    configLIST_VOLATILE UBaseType_t uxNumberOfItems;
     ListItem_t * configLIST_VOLATILE pxIndex; /**< Used to walk through the list.  Points to the last item returned by a call to listGET_OWNER_OF_NEXT_ENTRY (). */
     MiniListItem_t xListEnd;                  /**< List item that contains the maximum possible item value meaning it is always at the end of the list and is therefore used as a marker. */
     listSECOND_LIST_INTEGRITY_CHECK_VALUE     /**< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */

From 73851fb6da6fdc639824246638e5347d25844d10 Mon Sep 17 00:00:00 2001
From: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Date: Thu, 11 Apr 2024 11:30:29 +0530
Subject: [PATCH 252/424] Remove unwanted volatile keyword (#1028)

* Remove unwanted volatile keyword

* Declare variable initially
---
 tasks.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/tasks.c b/tasks.c
index e0db3f9e7..b02616026 100644
--- a/tasks.c
+++ b/tasks.c
@@ -985,6 +985,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
         UBaseType_t uxCurrentPriority = uxTopReadyPriority;
         BaseType_t xTaskScheduled = pdFALSE;
         BaseType_t xDecrementTopPriority = pdTRUE;
+        TCB_t * pxTCB = NULL;
 
         #if ( configUSE_CORE_AFFINITY == 1 )
             const TCB_t * pxPreviousTCB = NULL;
@@ -1043,7 +1044,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
                     /* MISRA Ref 11.5.3 [Void pointer assignment] */
                     /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
                     /* coverity[misra_c_2012_rule_11_5_violation] */
-                    TCB_t * pxTCB = ( TCB_t * ) listGET_LIST_ITEM_OWNER( pxIterator );
+                    pxTCB = ( TCB_t * ) listGET_LIST_ITEM_OWNER( pxIterator );
 
                     #if ( configRUN_MULTIPLE_PRIORITIES == 0 )
                     {
@@ -4181,6 +4182,7 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery )
                                                      const char pcNameToQuery[] )
     {
         TCB_t * pxReturn = NULL;
+        TCB_t * pxTCB = NULL;
         UBaseType_t x;
         char cNextChar;
         BaseType_t xBreakLoop;
@@ -4196,7 +4198,7 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery )
                 /* MISRA Ref 11.5.3 [Void pointer assignment] */
                 /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
                 /* coverity[misra_c_2012_rule_11_5_violation] */
-                TCB_t * pxTCB = listGET_LIST_ITEM_OWNER( pxIterator );
+                pxTCB = listGET_LIST_ITEM_OWNER( pxIterator );
 
                 /* Check each character in the name looking for a match or
                  * mismatch. */
@@ -6255,10 +6257,10 @@ static void prvCheckTasksWaitingTermination( void )
                                                      List_t * pxList,
                                                      eTaskState eState )
     {
-        configLIST_VOLATILE TCB_t * pxTCB;
         UBaseType_t uxTask = 0;
         const ListItem_t * pxEndMarker = listGET_END_MARKER( pxList );
         ListItem_t * pxIterator;
+        TCB_t * pxTCB = NULL;
 
         if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )
         {

From 4d4f8d0d50bedc37e1d07c96aded7d2bc20f0d6c Mon Sep 17 00:00:00 2001
From: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Date: Thu, 11 Apr 2024 15:12:03 +0800
Subject: [PATCH 253/424] Fix vTaskSuspendAll assert for critical nesting count
 (#1029)

* Accessing the critical nesting count in current task's TCB is performed with interrupt disabled to ensure atomicity.
---
 tasks.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/tasks.c b/tasks.c
index b02616026..5cec846d0 100644
--- a/tasks.c
+++ b/tasks.c
@@ -3831,9 +3831,6 @@ void vTaskSuspendAll( void )
 
         if( xSchedulerRunning != pdFALSE )
         {
-            /* This must never be called from inside a critical section. */
-            configASSERT( portGET_CRITICAL_NESTING_COUNT() == 0 );
-
             /* Writes to uxSchedulerSuspended must be protected by both the task AND ISR locks.
              * We must disable interrupts before we grab the locks in the event that this task is
              * interrupted and switches context before incrementing uxSchedulerSuspended.
@@ -3841,6 +3838,9 @@ void vTaskSuspendAll( void )
              * uxSchedulerSuspended since that will prevent context switches. */
             ulState = portSET_INTERRUPT_MASK();
 
+            /* This must never be called from inside a critical section. */
+            configASSERT( portGET_CRITICAL_NESTING_COUNT() == 0 );
+
             /* portSOFRWARE_BARRIER() is only implemented for emulated/simulated ports that
              * do not otherwise exhibit real time behaviour. */
             portSOFTWARE_BARRIER();

From 6de0d7a73703e225637ee19030ed981624b1bc49 Mon Sep 17 00:00:00 2001
From: Soren Ptak <ptaksoren@gmail.com>
Date: Mon, 15 Apr 2024 00:40:10 -0400
Subject: [PATCH 254/424] Fix the pxTopcOfStack typo in the RISC-V ports.
 (#1030)

* Fix the pxTopcOfStack typo in the RISC-V ports.

* Add a missing o to to
---
 portable/GCC/RISC-V/portASM.S | 4 ++--
 portable/IAR/RISC-V/portASM.s | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/portable/GCC/RISC-V/portASM.S b/portable/GCC/RISC-V/portASM.S
index 12637b06f..b5f054777 100644
--- a/portable/GCC/RISC-V/portASM.S
+++ b/portable/GCC/RISC-V/portASM.S
@@ -138,7 +138,7 @@ definitions. */
  * for the function is as per the other ports:
  * StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters );
  *
- * As per the standard RISC-V ABI pxTopcOfStack is passed in in a0, pxCode in
+ * As per the standard RISC-V ABI pxTopOfStack is passed in in a0, pxCode in
  * a1, and pvParameters in a2.  The new top of stack is passed out in a0.
  *
  * RISC-V maps registers to ABI names as follows (X1 to X31 integer registers
@@ -158,7 +158,7 @@ definitions. */
  * x18-27        s2-11       Saved registers                   Callee
  * x28-31        t3-6        Temporaries                       Caller
  *
- * The RISC-V context is saved t FreeRTOS tasks in the following stack frame,
+ * The RISC-V context is saved to FreeRTOS tasks in the following stack frame,
  * where the global and thread pointers are currently assumed to be constant so
  * are not saved:
  *
diff --git a/portable/IAR/RISC-V/portASM.s b/portable/IAR/RISC-V/portASM.s
index f32d9e7ac..12a2a6154 100644
--- a/portable/IAR/RISC-V/portASM.s
+++ b/portable/IAR/RISC-V/portASM.s
@@ -147,7 +147,7 @@ portUPDATE_MTIMER_COMPARE_REGISTER MACRO
  * for the function is as per the other ports:
  * StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters );
  *
- * As per the standard RISC-V ABI pxTopcOfStack is passed in in a0, pxCode in
+ * As per the standard RISC-V ABI pxTopOfStack is passed in in a0, pxCode in
  * a1, and pvParameters in a2.  The new top of stack is passed out in a0.
  *
  * RISC-V maps registers to ABI names as follows (X1 to X31 integer registers
@@ -167,7 +167,7 @@ portUPDATE_MTIMER_COMPARE_REGISTER MACRO
  * x18-27        s2-11       Saved registers                   Callee
  * x28-31        t3-6        Temporaries                       Caller
  *
- * The RISC-V context is saved t FreeRTOS tasks in the following stack frame,
+ * The RISC-V context is saved to FreeRTOS tasks in the following stack frame,
  * where the global and thread pointers are currently assumed to be constant so
  * are not saved:
  *

From 1ed681cc43e77b187ae4a8a1fe31a8820f8a473d Mon Sep 17 00:00:00 2001
From: Aniruddha Kanhere <60444055+AniruddhaKanhere@users.noreply.github.com>
Date: Mon, 15 Apr 2024 21:41:50 -0700
Subject: [PATCH 255/424] Add readme to example directory (#1032)

* Add readme to example directory

* Add readme to example directory

* Add readme to example directory

* Add readme to example directory

* remove whitespace

* Update wording

* Update examples/README.md

Co-authored-by: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>

* Add Coverity webpage link

---------

Co-authored-by: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
---
 examples/README.md | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)
 create mode 100644 examples/README.md

diff --git a/examples/README.md b/examples/README.md
new file mode 100644
index 000000000..3b36b607e
--- /dev/null
+++ b/examples/README.md
@@ -0,0 +1,17 @@
+# README for FreeRTOS-Kernel/examples
+
+The easiest way to use FreeRTOS is to start with one of the pre-configured demo application projects.
+See [FreeRTOS/FreeRTOS/Demo](https://github.com/FreeRTOS/FreeRTOS/tree/main/FreeRTOS/Demo) to find a list of pre-configured demos on multiple platforms which demonstrate the working of the FreeRTOS-Kernel.
+This directory aims to further facilitate the beginners in building their first FreeRTOS project.
+
+
+## Directory Structure:
+
+* The [cmake_example](./cmake_example) directory contains a minimal FreeRTOS example project, which uses the configuration file in the template_configuration directory listed below. This will provide you with a starting point for building your applications using FreeRTOS-Kernel.
+* The [coverity](./coverity) directory contains a project to run [Synopsys Coverity](https://www.synopsys.com/software-integrity/static-analysis-tools-sast/coverity.html) for checking MISRA compliance. This directory contains further readme files and links to documentation.
+* The [template_configuration](./template_configuration) directory contains a sample configuration file FreeRTOSConfig.h which helps you in preparing your application configuration
+
+
+## Additional examples
+
+Additional examples of the kernel being used in real life applications in tandem with many other libraries (i.e. FreeRTOS+TCP, coreMQTT, coreHTTP etc.) can be found [here](https://github.com/FreeRTOS/FreeRTOS/tree/main/FreeRTOS-Plus/Demo).

From 9bfd0abb55e660a7040c6f38cd31f27b51ab23f5 Mon Sep 17 00:00:00 2001
From: HagaiMoshe <121489522+HagaiMoshe@users.noreply.github.com>
Date: Wed, 17 Apr 2024 01:41:55 +0300
Subject: [PATCH 256/424] Add IRQ safe API for message buffer reset (#1033)

* Add API xStreamBufferResetFromISR

Allow reseting the stream buffer from ISR context

Signed-off-by: hagai.moshe <hagaimoshe@outlook.com>
Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: hagai.moshe <hagai.moshe@tandemg.com>
Co-authored-by: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Co-authored-by: kar-rahul-aws <karahulx@amazon.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 include/FreeRTOS.h       | 12 ++++++++
 include/message_buffer.h | 36 +++++++++++++++++++++++
 include/stream_buffer.h  | 36 +++++++++++++++++++++++
 stream_buffer.c          | 62 ++++++++++++++++++++++++++++++++++++++++
 4 files changed, 146 insertions(+)

diff --git a/include/FreeRTOS.h b/include/FreeRTOS.h
index 69611842a..662c5ea15 100644
--- a/include/FreeRTOS.h
+++ b/include/FreeRTOS.h
@@ -1001,6 +1001,10 @@
     #define traceSTREAM_BUFFER_RESET( xStreamBuffer )
 #endif
 
+#ifndef traceSTREAM_BUFFER_RESET_FROM_ISR
+    #define traceSTREAM_BUFFER_RESET_FROM_ISR( xStreamBuffer )
+#endif
+
 #ifndef traceBLOCKING_ON_STREAM_BUFFER_SEND
     #define traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer )
 #endif
@@ -2437,6 +2441,14 @@
     #define traceRETURN_xStreamBufferReset( xReturn )
 #endif
 
+#ifndef traceENTER_xStreamBufferResetFromISR
+    #define traceENTER_xStreamBufferResetFromISR( xStreamBuffer )
+#endif
+
+#ifndef traceRETURN_xStreamBufferResetFromISR
+    #define traceRETURN_xStreamBufferResetFromISR( xReturn )
+#endif
+
 #ifndef traceENTER_xStreamBufferSetTriggerLevel
     #define traceENTER_xStreamBufferSetTriggerLevel( xStreamBuffer, xTriggerLevel )
 #endif
diff --git a/include/message_buffer.h b/include/message_buffer.h
index 1b1356ca4..b58f33f47 100644
--- a/include/message_buffer.h
+++ b/include/message_buffer.h
@@ -768,6 +768,10 @@ typedef StreamBufferHandle_t MessageBufferHandle_t;
  *
  * A message buffer can only be reset if there are no tasks blocked on it.
  *
+ * Use xMessageBufferReset() to reset a message buffer from a task.
+ * Use xMessageBufferResetFromISR() to reset a message buffer from an
+ * interrupt service routine (ISR).
+ *
  * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
  * xMessageBufferReset() to be available.
  *
@@ -785,6 +789,38 @@ typedef StreamBufferHandle_t MessageBufferHandle_t;
     xStreamBufferReset( xMessageBuffer )
 
 
+/**
+ * message_buffer.h
+ * @code{c}
+ * BaseType_t xMessageBufferResetFromISR( MessageBufferHandle_t xMessageBuffer );
+ * @endcode
+ *
+ * An interrupt safe version of the API function that resets the message buffer.
+ * Resets a message buffer to its initial empty state, discarding any message it
+ * contained.
+ *
+ * A message buffer can only be reset if there are no tasks blocked on it.
+ *
+ * Use xMessageBufferReset() to reset a message buffer from a task.
+ * Use xMessageBufferResetFromISR() to reset a message buffer from an
+ * interrupt service routine (ISR).
+ *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xMessageBufferResetFromISR() to be available.
+ *
+ * @param xMessageBuffer The handle of the message buffer being reset.
+ *
+ * @return If the message buffer was reset then pdPASS is returned.  If the
+ * message buffer could not be reset because either there was a task blocked on
+ * the message queue to wait for space to become available, or to wait for a
+ * a message to be available, then pdFAIL is returned.
+ *
+ * \defgroup xMessageBufferResetFromISR xMessageBufferResetFromISR
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferResetFromISR( xMessageBuffer ) \
+    xStreamBufferResetFromISR( xMessageBuffer )
+
 /**
  * message_buffer.h
  * @code{c}
diff --git a/include/stream_buffer.h b/include/stream_buffer.h
index 94a0e0cd7..dca9851a5 100644
--- a/include/stream_buffer.h
+++ b/include/stream_buffer.h
@@ -767,6 +767,10 @@ BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED
  * are no tasks blocked waiting to either send to or receive from the stream
  * buffer.
  *
+ * Use xStreamBufferReset() to reset a stream buffer from a task.
+ * Use xStreamBufferResetFromISR() to reset a stream buffer from an
+ * interrupt service routine (ISR).
+ *
  * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
  * xStreamBufferReset() to be available.
  *
@@ -781,6 +785,38 @@ BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED
  */
 BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
 
+/**
+ * stream_buffer.h
+ *
+ * @code{c}
+ * BaseType_t xStreamBufferResetFromISR( StreamBufferHandle_t xStreamBuffer );
+ * @endcode
+ *
+ * An interrupt safe version of the API function that resets the stream buffer.
+ *
+ * Resets a stream buffer to its initial, empty, state.  Any data that was in
+ * the stream buffer is discarded.  A stream buffer can only be reset if there
+ * are no tasks blocked waiting to either send to or receive from the stream
+ * buffer.
+ *
+ * Use xStreamBufferReset() to reset a stream buffer from a task.
+ * Use xStreamBufferResetFromISR() to reset a stream buffer from an
+ * interrupt service routine (ISR).
+ *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xStreamBufferResetFromISR() to be available.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being reset.
+ *
+ * @return If the stream buffer is reset then pdPASS is returned.  If there was
+ * a task blocked waiting to send to or read from the stream buffer then the
+ * stream buffer is not reset and pdFAIL is returned.
+ *
+ * \defgroup xStreamBufferResetFromISR xStreamBufferResetFromISR
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferResetFromISR( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
 /**
  * stream_buffer.h
  *
diff --git a/stream_buffer.c b/stream_buffer.c
index 44354fba3..17a898d45 100644
--- a/stream_buffer.c
+++ b/stream_buffer.c
@@ -639,6 +639,68 @@ BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer )
 }
 /*-----------------------------------------------------------*/
 
+BaseType_t xStreamBufferResetFromISR( StreamBufferHandle_t xStreamBuffer )
+{
+    StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+    BaseType_t xReturn = pdFAIL;
+    StreamBufferCallbackFunction_t pxSendCallback = NULL, pxReceiveCallback = NULL;
+    UBaseType_t uxSavedInterruptStatus;
+
+    #if ( configUSE_TRACE_FACILITY == 1 )
+        UBaseType_t uxStreamBufferNumber;
+    #endif
+
+    traceENTER_xStreamBufferResetFromISR( xStreamBuffer );
+
+    configASSERT( pxStreamBuffer );
+
+    #if ( configUSE_TRACE_FACILITY == 1 )
+    {
+        /* Store the stream buffer number so it can be restored after the
+         * reset. */
+        uxStreamBufferNumber = pxStreamBuffer->uxStreamBufferNumber;
+    }
+    #endif
+
+    /* Can only reset a message buffer if there are no tasks blocked on it. */
+    uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
+    {
+        if( ( pxStreamBuffer->xTaskWaitingToReceive == NULL ) && ( pxStreamBuffer->xTaskWaitingToSend == NULL ) )
+        {
+            #if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
+            {
+                pxSendCallback = pxStreamBuffer->pxSendCompletedCallback;
+                pxReceiveCallback = pxStreamBuffer->pxReceiveCompletedCallback;
+            }
+            #endif
+
+            prvInitialiseNewStreamBuffer( pxStreamBuffer,
+                                          pxStreamBuffer->pucBuffer,
+                                          pxStreamBuffer->xLength,
+                                          pxStreamBuffer->xTriggerLevelBytes,
+                                          pxStreamBuffer->ucFlags,
+                                          pxSendCallback,
+                                          pxReceiveCallback );
+
+            #if ( configUSE_TRACE_FACILITY == 1 )
+            {
+                pxStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber;
+            }
+            #endif
+
+            traceSTREAM_BUFFER_RESET_FROM_ISR( xStreamBuffer );
+
+            xReturn = pdPASS;
+        }
+    }
+    taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
+
+    traceRETURN_xStreamBufferResetFromISR( xReturn );
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
 BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
                                          size_t xTriggerLevel )
 {

From 5a72344c9a57306d175c20e117b2b82b16fa332e Mon Sep 17 00:00:00 2001
From: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Date: Wed, 17 Apr 2024 14:27:58 +0530
Subject: [PATCH 257/424] Add MPU wrapper from xStreamBufferResetFromISR
 (#1034)

* Add MPU wrapper from xStreamBufferResetFromISR in V10.6.x

* Code review suggestions

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 include/mpu_prototypes.h          |  1 +
 include/mpu_wrappers.h            |  1 +
 portable/Common/mpu_wrappers_v2.c | 27 +++++++++++++++++++++++++++
 3 files changed, 29 insertions(+)

diff --git a/include/mpu_prototypes.h b/include/mpu_prototypes.h
index d51f6e1d2..10da35bf8 100644
--- a/include/mpu_prototypes.h
+++ b/include/mpu_prototypes.h
@@ -384,5 +384,6 @@ BaseType_t MPU_xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBu
                                                   BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
 BaseType_t MPU_xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer,
                                                      BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+BaseType_t MPU_xStreamBufferResetFromISR( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
 
 #endif /* MPU_PROTOTYPES_H */
diff --git a/include/mpu_wrappers.h b/include/mpu_wrappers.h
index 19c5e779f..dea7c0d2a 100644
--- a/include/mpu_wrappers.h
+++ b/include/mpu_wrappers.h
@@ -227,6 +227,7 @@
             #define xStreamBufferReceiveFromISR             MPU_xStreamBufferReceiveFromISR
             #define xStreamBufferSendCompletedFromISR       MPU_xStreamBufferSendCompletedFromISR
             #define xStreamBufferReceiveCompletedFromISR    MPU_xStreamBufferReceiveCompletedFromISR
+            #define xStreamBufferResetFromISR               MPU_xStreamBufferResetFromISR
         #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
         #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
diff --git a/portable/Common/mpu_wrappers_v2.c b/portable/Common/mpu_wrappers_v2.c
index a7ab6669a..f8d14b1df 100644
--- a/portable/Common/mpu_wrappers_v2.c
+++ b/portable/Common/mpu_wrappers_v2.c
@@ -4962,6 +4962,33 @@
 
     #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
 
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_STREAM_BUFFERS == 1 )
+
+        BaseType_t MPU_xStreamBufferResetFromISR( StreamBufferHandle_t xStreamBuffer ) /*PRIVILEGED_FUNCTION */
+        {
+            BaseType_t xReturn = pdFAIL;
+            StreamBufferHandle_t xInternalStreamBufferHandle = NULL;
+            int32_t lIndex;
+
+            lIndex = ( int32_t ) xStreamBuffer;
+
+            if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+            {
+                xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+                if( xInternalStreamBufferHandle != NULL )
+                {
+                    xReturn = xStreamBufferResetFromISR( xInternalStreamBufferHandle );
+                }
+            }
+
+            return xReturn;
+        }
+
+    #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
+
 /*-----------------------------------------------------------*/
 
 /* Functions that the application writer wants to execute in privileged mode

From f69b1db45c294444306f9cc840feef2ead1bca03 Mon Sep 17 00:00:00 2001
From: Caleb Perkinson <60443297+cperkulator@users.noreply.github.com>
Date: Wed, 17 Apr 2024 10:54:00 -0400
Subject: [PATCH 258/424] Add Stream Batching Buffer (#916)

The difference between a stream buffer and a stream batching buffer is when
a task performs read on a non-empty buffer:
- The task reading from a non-empty stream buffer returns immediately
   regardless of the amount of data in the buffer.
- The task reading from a non-empty steam batching buffer blocks until the
   amount of data in the buffer exceeds the trigger level or the block time
   expires.
---
 include/FreeRTOS.h                |  10 +-
 include/message_buffer.h          |   8 +-
 include/mpu_prototypes.h          |   4 +-
 include/stream_buffer.h           | 207 +++++++++++++++++++++++++++++-
 portable/Common/mpu_wrappers.c    |  20 +--
 portable/Common/mpu_wrappers_v2.c |  12 +-
 stream_buffer.c                   |  43 +++++--
 7 files changed, 260 insertions(+), 44 deletions(-)

diff --git a/include/FreeRTOS.h b/include/FreeRTOS.h
index 662c5ea15..f7a59a765 100644
--- a/include/FreeRTOS.h
+++ b/include/FreeRTOS.h
@@ -982,15 +982,15 @@
 #endif
 
 #ifndef traceSTREAM_BUFFER_CREATE_FAILED
-    #define traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer )
+    #define traceSTREAM_BUFFER_CREATE_FAILED( xStreamBufferType )
 #endif
 
 #ifndef traceSTREAM_BUFFER_CREATE_STATIC_FAILED
-    #define traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer )
+    #define traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xStreamBufferType )
 #endif
 
 #ifndef traceSTREAM_BUFFER_CREATE
-    #define traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xIsMessageBuffer )
+    #define traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xStreamBufferType )
 #endif
 
 #ifndef traceSTREAM_BUFFER_DELETE
@@ -2402,7 +2402,7 @@
 #endif
 
 #ifndef traceENTER_xStreamBufferGenericCreate
-    #define traceENTER_xStreamBufferGenericCreate( xBufferSizeBytes, xTriggerLevelBytes, xIsMessageBuffer, pxSendCompletedCallback, pxReceiveCompletedCallback )
+    #define traceENTER_xStreamBufferGenericCreate( xBufferSizeBytes, xTriggerLevelBytes, xStreamBufferType, pxSendCompletedCallback, pxReceiveCompletedCallback )
 #endif
 
 #ifndef traceRETURN_xStreamBufferGenericCreate
@@ -2410,7 +2410,7 @@
 #endif
 
 #ifndef traceENTER_xStreamBufferGenericCreateStatic
-    #define traceENTER_xStreamBufferGenericCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, xIsMessageBuffer, pucStreamBufferStorageArea, pxStaticStreamBuffer, pxSendCompletedCallback, pxReceiveCompletedCallback )
+    #define traceENTER_xStreamBufferGenericCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, xStreamBufferType, pucStreamBufferStorageArea, pxStaticStreamBuffer, pxSendCompletedCallback, pxReceiveCompletedCallback )
 #endif
 
 #ifndef traceRETURN_xStreamBufferGenericCreateStatic
diff --git a/include/message_buffer.h b/include/message_buffer.h
index b58f33f47..975a7e343 100644
--- a/include/message_buffer.h
+++ b/include/message_buffer.h
@@ -158,11 +158,11 @@ typedef StreamBufferHandle_t MessageBufferHandle_t;
  * \ingroup MessageBufferManagement
  */
 #define xMessageBufferCreate( xBufferSizeBytes ) \
-    xStreamBufferGenericCreate( ( xBufferSizeBytes ), ( size_t ) 0, pdTRUE, NULL, NULL )
+    xStreamBufferGenericCreate( ( xBufferSizeBytes ), ( size_t ) 0, sbTYPE_MESSAGE_BUFFER, NULL, NULL )
 
 #if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
     #define xMessageBufferCreateWithCallback( xBufferSizeBytes, pxSendCompletedCallback, pxReceiveCompletedCallback ) \
-    xStreamBufferGenericCreate( ( xBufferSizeBytes ), ( size_t ) 0, pdTRUE, ( pxSendCompletedCallback ), ( pxReceiveCompletedCallback ) )
+    xStreamBufferGenericCreate( ( xBufferSizeBytes ), ( size_t ) 0, sbTYPE_MESSAGE_BUFFER, ( pxSendCompletedCallback ), ( pxReceiveCompletedCallback ) )
 #endif
 
 /**
@@ -243,11 +243,11 @@ typedef StreamBufferHandle_t MessageBufferHandle_t;
  * \ingroup MessageBufferManagement
  */
 #define xMessageBufferCreateStatic( xBufferSizeBytes, pucMessageBufferStorageArea, pxStaticMessageBuffer ) \
-    xStreamBufferGenericCreateStatic( ( xBufferSizeBytes ), 0, pdTRUE, ( pucMessageBufferStorageArea ), ( pxStaticMessageBuffer ), NULL, NULL )
+    xStreamBufferGenericCreateStatic( ( xBufferSizeBytes ), 0, sbTYPE_MESSAGE_BUFFER, ( pucMessageBufferStorageArea ), ( pxStaticMessageBuffer ), NULL, NULL )
 
 #if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
     #define xMessageBufferCreateStaticWithCallback( xBufferSizeBytes, pucMessageBufferStorageArea, pxStaticMessageBuffer, pxSendCompletedCallback, pxReceiveCompletedCallback ) \
-    xStreamBufferGenericCreateStatic( ( xBufferSizeBytes ), 0, pdTRUE, ( pucMessageBufferStorageArea ), ( pxStaticMessageBuffer ), ( pxSendCompletedCallback ), ( pxReceiveCompletedCallback ) )
+    xStreamBufferGenericCreateStatic( ( xBufferSizeBytes ), 0, sbTYPE_MESSAGE_BUFFER, ( pucMessageBufferStorageArea ), ( pxStaticMessageBuffer ), ( pxSendCompletedCallback ), ( pxReceiveCompletedCallback ) )
 #endif
 
 /**
diff --git a/include/mpu_prototypes.h b/include/mpu_prototypes.h
index 10da35bf8..d51547cd6 100644
--- a/include/mpu_prototypes.h
+++ b/include/mpu_prototypes.h
@@ -357,12 +357,12 @@ size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuff
  * with all the APIs. */
 StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes,
                                                      size_t xTriggerLevelBytes,
-                                                     BaseType_t xIsMessageBuffer,
+                                                     BaseType_t xStreamBufferType,
                                                      StreamBufferCallbackFunction_t pxSendCompletedCallback,
                                                      StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) PRIVILEGED_FUNCTION;
 StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
                                                            size_t xTriggerLevelBytes,
-                                                           BaseType_t xIsMessageBuffer,
+                                                           BaseType_t xStreamBufferType,
                                                            uint8_t * const pucStreamBufferStorageArea,
                                                            StaticStreamBuffer_t * const pxStaticStreamBuffer,
                                                            StreamBufferCallbackFunction_t pxSendCompletedCallback,
diff --git a/include/stream_buffer.h b/include/stream_buffer.h
index dca9851a5..9b15c8aff 100644
--- a/include/stream_buffer.h
+++ b/include/stream_buffer.h
@@ -62,6 +62,13 @@
 #endif
 /* *INDENT-ON* */
 
+/**
+ * Type of stream buffer. For internal use only.
+ */
+#define sbTYPE_STREAM_BUFFER             ( ( BaseType_t ) 0 )
+#define sbTYPE_MESSAGE_BUFFER            ( ( BaseType_t ) 1 )
+#define sbTYPE_STREAM_BATCHING_BUFFER    ( ( BaseType_t ) 2 )
+
 /**
  * Type by which stream buffers are referenced.  For example, a call to
  * xStreamBufferCreate() returns an StreamBufferHandle_t variable that can
@@ -157,11 +164,11 @@ typedef void (* StreamBufferCallbackFunction_t)( StreamBufferHandle_t xStreamBuf
  */
 
 #define xStreamBufferCreate( xBufferSizeBytes, xTriggerLevelBytes ) \
-    xStreamBufferGenericCreate( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), pdFALSE, NULL, NULL )
+    xStreamBufferGenericCreate( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), sbTYPE_STREAM_BUFFER, NULL, NULL )
 
 #if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
     #define xStreamBufferCreateWithCallback( xBufferSizeBytes, xTriggerLevelBytes, pxSendCompletedCallback, pxReceiveCompletedCallback ) \
-    xStreamBufferGenericCreate( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), pdFALSE, ( pxSendCompletedCallback ), ( pxReceiveCompletedCallback ) )
+    xStreamBufferGenericCreate( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), sbTYPE_STREAM_BUFFER, ( pxSendCompletedCallback ), ( pxReceiveCompletedCallback ) )
 #endif
 
 /**
@@ -257,11 +264,199 @@ typedef void (* StreamBufferCallbackFunction_t)( StreamBufferHandle_t xStreamBuf
  */
 
 #define xStreamBufferCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pucStreamBufferStorageArea, pxStaticStreamBuffer ) \
-    xStreamBufferGenericCreateStatic( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), pdFALSE, ( pucStreamBufferStorageArea ), ( pxStaticStreamBuffer ), NULL, NULL )
+    xStreamBufferGenericCreateStatic( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), sbTYPE_STREAM_BUFFER, ( pucStreamBufferStorageArea ), ( pxStaticStreamBuffer ), NULL, NULL )
 
 #if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
     #define xStreamBufferCreateStaticWithCallback( xBufferSizeBytes, xTriggerLevelBytes, pucStreamBufferStorageArea, pxStaticStreamBuffer, pxSendCompletedCallback, pxReceiveCompletedCallback ) \
-    xStreamBufferGenericCreateStatic( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), pdFALSE, ( pucStreamBufferStorageArea ), ( pxStaticStreamBuffer ), ( pxSendCompletedCallback ), ( pxReceiveCompletedCallback ) )
+    xStreamBufferGenericCreateStatic( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), sbTYPE_STREAM_BUFFER, ( pucStreamBufferStorageArea ), ( pxStaticStreamBuffer ), ( pxSendCompletedCallback ), ( pxReceiveCompletedCallback ) )
+#endif
+
+/**
+ * stream_buffer.h
+ *
+ * @code{c}
+ * StreamBufferHandle_t xStreamBatchingBufferCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes );
+ * @endcode
+ *
+ * Creates a new stream batching buffer using dynamically allocated memory.  See
+ * xStreamBatchingBufferCreateStatic() for a version that uses statically
+ * allocated memory (memory that is allocated at compile time).
+ *
+ * configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in
+ * FreeRTOSConfig.h for xStreamBatchingBufferCreate() to be available.
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xStreamBatchingBufferCreate() to be available.
+ *
+ * The difference between a stream buffer and a stream batching buffer is when
+ * a task performs read on a non-empty buffer:
+ * - The task reading from a non-empty stream buffer returns immediately
+ *   regardless of the amount of data in the buffer.
+ * - The task reading from a non-empty steam batching buffer blocks until the
+ *   amount of data in the buffer exceeds the trigger level or the block time
+ *   expires.
+ *
+ * @param xBufferSizeBytes The total number of bytes the stream batching buffer
+ * will be able to hold at any one time.
+ *
+ * @param xTriggerLevelBytes The number of bytes that must be in the stream
+ * batching buffer to unblock a task calling xStreamBufferReceive before the
+ * block time expires.
+ *
+ * @param pxSendCompletedCallback Callback invoked when number of bytes at least
+ * equal to trigger level is sent to the stream batching buffer. If the
+ * parameter is NULL, it will use the default implementation provided by
+ * sbSEND_COMPLETED macro. To enable the callback, configUSE_SB_COMPLETED_CALLBACK
+ * must be set to 1 in FreeRTOSConfig.h.
+ *
+ * @param pxReceiveCompletedCallback Callback invoked when more than zero bytes
+ * are read from a stream batching buffer. If the parameter is NULL, it will use
+ * the default implementation provided by sbRECEIVE_COMPLETED macro. To enable
+ * the callback, configUSE_SB_COMPLETED_CALLBACK must be set to 1 in
+ * FreeRTOSConfig.h.
+ *
+ * @return If NULL is returned, then the stream batching buffer cannot be created
+ * because there is insufficient heap memory available for FreeRTOS to allocate
+ * the stream batching buffer data structures and storage area.  A non-NULL value
+ * being returned indicates that the stream batching buffer has been created
+ * successfully - the returned value should be stored as the handle to the
+ * created stream batching buffer.
+ *
+ * Example use:
+ * @code{c}
+ *
+ * void vAFunction( void )
+ * {
+ * StreamBufferHandle_t xStreamBatchingBuffer;
+ * const size_t xStreamBufferSizeBytes = 100, xTriggerLevel = 10;
+ *
+ *  // Create a stream batching buffer that can hold 100 bytes.  The memory used
+ *  // to hold both the stream batching buffer structure and the data in the stream
+ *  // batching buffer is allocated dynamically.
+ *  xStreamBatchingBuffer = xStreamBatchingBufferCreate( xStreamBufferSizeBytes, xTriggerLevel );
+ *
+ *  if( xStreamBatchingBuffer == NULL )
+ *  {
+ *      // There was not enough heap memory space available to create the
+ *      // stream batching buffer.
+ *  }
+ *  else
+ *  {
+ *      // The stream batching buffer was created successfully and can now be used.
+ *  }
+ * }
+ * @endcode
+ * \defgroup xStreamBatchingBufferCreate xStreamBatchingBufferCreate
+ * \ingroup StreamBatchingBufferManagement
+ */
+
+#define xStreamBatchingBufferCreate( xBufferSizeBytes, xTriggerLevelBytes ) \
+    xStreamBufferGenericCreate( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), sbTYPE_STREAM_BATCHING_BUFFER, NULL, NULL )
+
+#if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
+    #define xStreamBatchingBufferCreateWithCallback( xBufferSizeBytes, xTriggerLevelBytes, pxSendCompletedCallback, pxReceiveCompletedCallback ) \
+    xStreamBufferGenericCreate( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), sbTYPE_STREAM_BATCHING_BUFFER, ( pxSendCompletedCallback ), ( pxReceiveCompletedCallback ) )
+#endif
+
+/**
+ * stream_buffer.h
+ *
+ * @code{c}
+ * StreamBufferHandle_t xStreamBatchingBufferCreateStatic( size_t xBufferSizeBytes,
+ *                                                         size_t xTriggerLevelBytes,
+ *                                                         uint8_t *pucStreamBufferStorageArea,
+ *                                                         StaticStreamBuffer_t *pxStaticStreamBuffer );
+ * @endcode
+ * Creates a new stream batching buffer using statically allocated memory.  See
+ * xStreamBatchingBufferCreate() for a version that uses dynamically allocated
+ * memory.
+ *
+ * configSUPPORT_STATIC_ALLOCATION must be set to 1 in FreeRTOSConfig.h for
+ * xStreamBatchingBufferCreateStatic() to be available. configUSE_STREAM_BUFFERS
+ * must be set to 1 in for FreeRTOSConfig.h for xStreamBatchingBufferCreateStatic()
+ * to be available.
+ *
+ * The difference between a stream buffer and a stream batching buffer is when
+ * a task performs read on a non-empty buffer:
+ * - The task reading from a non-empty stream buffer returns immediately
+ *   regardless of the amount of data in the buffer.
+ * - The task reading from a non-empty steam batching buffer blocks until the
+ *   amount of data in the buffer exceeds the trigger level or the block time
+ *   expires.
+ *
+ * @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the
+ * pucStreamBufferStorageArea parameter.
+ *
+ * @param xTriggerLevelBytes The number of bytes that must be in the stream
+ * batching buffer to unblock a task calling xStreamBufferReceive before the
+ * block time expires.
+ *
+ * @param pucStreamBufferStorageArea Must point to a uint8_t array that is at
+ * least xBufferSizeBytes big.  This is the array to which streams are
+ * copied when they are written to the stream batching buffer.
+ *
+ * @param pxStaticStreamBuffer Must point to a variable of type
+ * StaticStreamBuffer_t, which will be used to hold the stream batching buffer's
+ * data structure.
+ *
+ * @param pxSendCompletedCallback Callback invoked when number of bytes at least
+ * equal to trigger level is sent to the stream batching buffer. If the parameter
+ * is NULL, it will use the default implementation provided by sbSEND_COMPLETED
+ * macro. To enable the callback, configUSE_SB_COMPLETED_CALLBACK must be set to
+ * 1 in FreeRTOSConfig.h.
+ *
+ * @param pxReceiveCompletedCallback Callback invoked when more than zero bytes
+ * are read from a stream batching buffer. If the parameter is NULL, it will use
+ * the default implementation provided by sbRECEIVE_COMPLETED macro. To enable
+ * the callback, configUSE_SB_COMPLETED_CALLBACK must be set to 1 in
+ * FreeRTOSConfig.h.
+ *
+ * @return If the stream batching buffer is created successfully then a handle
+ * to the created stream batching buffer is returned. If either pucStreamBufferStorageArea
+ * or pxStaticstreamBuffer are NULL then NULL is returned.
+ *
+ * Example use:
+ * @code{c}
+ *
+ * // Used to dimension the array used to hold the streams.  The available space
+ * // will actually be one less than this, so 999.
+ * #define STORAGE_SIZE_BYTES 1000
+ *
+ * // Defines the memory that will actually hold the streams within the stream
+ * // batching buffer.
+ * static uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ];
+ *
+ * // The variable used to hold the stream batching buffer structure.
+ * StaticStreamBuffer_t xStreamBufferStruct;
+ *
+ * void MyFunction( void )
+ * {
+ * StreamBufferHandle_t xStreamBatchingBuffer;
+ * const size_t xTriggerLevel = 1;
+ *
+ *  xStreamBatchingBuffer = xStreamBatchingBufferCreateStatic( sizeof( ucStorageBuffer ),
+ *                                                             xTriggerLevel,
+ *                                                             ucStorageBuffer,
+ *                                                             &xStreamBufferStruct );
+ *
+ *  // As neither the pucStreamBufferStorageArea or pxStaticStreamBuffer
+ *  // parameters were NULL, xStreamBatchingBuffer will not be NULL, and can be
+ *  // used to reference the created stream batching buffer in other stream
+ *  // buffer API calls.
+ *
+ *  // Other code that uses the stream batching buffer can go here.
+ * }
+ *
+ * @endcode
+ * \defgroup xStreamBatchingBufferCreateStatic xStreamBatchingBufferCreateStatic
+ * \ingroup StreamBatchingBufferManagement
+ */
+
+#define xStreamBatchingBufferCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pucStreamBufferStorageArea, pxStaticStreamBuffer ) \
+    xStreamBufferGenericCreateStatic( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), sbTYPE_STREAM_BATCHING_BUFFER, ( pucStreamBufferStorageArea ), ( pxStaticStreamBuffer ), NULL, NULL )
+
+#if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
+    #define xStreamBatchingBufferCreateStaticWithCallback( xBufferSizeBytes, xTriggerLevelBytes, pucStreamBufferStorageArea, pxStaticStreamBuffer, pxSendCompletedCallback, pxReceiveCompletedCallback ) \
+    xStreamBufferGenericCreateStatic( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), sbTYPE_STREAM_BATCHING_BUFFER, ( pucStreamBufferStorageArea ), ( pxStaticStreamBuffer ), ( pxSendCompletedCallback ), ( pxReceiveCompletedCallback ) )
 #endif
 
 /**
@@ -1053,14 +1248,14 @@ void vStreamBufferSetStreamBufferNotificationIndex( StreamBufferHandle_t xStream
 /* Functions below here are not part of the public API. */
 StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes,
                                                  size_t xTriggerLevelBytes,
-                                                 BaseType_t xIsMessageBuffer,
+                                                 BaseType_t xStreamBufferType,
                                                  StreamBufferCallbackFunction_t pxSendCompletedCallback,
                                                  StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) PRIVILEGED_FUNCTION;
 
 #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
     StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
                                                            size_t xTriggerLevelBytes,
-                                                           BaseType_t xIsMessageBuffer,
+                                                           BaseType_t xStreamBufferType,
                                                            uint8_t * const pucStreamBufferStorageArea,
                                                            StaticStreamBuffer_t * const pxStaticStreamBuffer,
                                                            StreamBufferCallbackFunction_t pxSendCompletedCallback,
diff --git a/portable/Common/mpu_wrappers.c b/portable/Common/mpu_wrappers.c
index 85facbd79..be1a9954d 100644
--- a/portable/Common/mpu_wrappers.c
+++ b/portable/Common/mpu_wrappers.c
@@ -2404,14 +2404,14 @@
     #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_STREAM_BUFFERS == 1 ) )
         StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes,
                                                              size_t xTriggerLevelBytes,
-                                                             BaseType_t xIsMessageBuffer,
+                                                             BaseType_t xStreamBufferType,
                                                              StreamBufferCallbackFunction_t pxSendCompletedCallback,
                                                              StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) /* FREERTOS_SYSTEM_CALL */
         {
             StreamBufferHandle_t xReturn;
 
             /**
-             * Streambuffer application level callback functionality is disabled for MPU
+             * Stream buffer application level callback functionality is disabled for MPU
              * enabled ports.
              */
             configASSERT( ( pxSendCompletedCallback == NULL ) &&
@@ -2427,7 +2427,7 @@
 
                     xReturn = xStreamBufferGenericCreate( xBufferSizeBytes,
                                                           xTriggerLevelBytes,
-                                                          xIsMessageBuffer,
+                                                          xStreamBufferType,
                                                           NULL,
                                                           NULL );
                     portMEMORY_BARRIER();
@@ -2439,14 +2439,14 @@
                 {
                     xReturn = xStreamBufferGenericCreate( xBufferSizeBytes,
                                                           xTriggerLevelBytes,
-                                                          xIsMessageBuffer,
+                                                          xStreamBufferType,
                                                           NULL,
                                                           NULL );
                 }
             }
             else
             {
-                traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer );
+                traceSTREAM_BUFFER_CREATE_FAILED( xStreamBufferType );
                 xReturn = NULL;
             }
 
@@ -2458,7 +2458,7 @@
     #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_STREAM_BUFFERS == 1 ) )
         StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
                                                                    size_t xTriggerLevelBytes,
-                                                                   BaseType_t xIsMessageBuffer,
+                                                                   BaseType_t xStreamBufferType,
                                                                    uint8_t * const pucStreamBufferStorageArea,
                                                                    StaticStreamBuffer_t * const pxStaticStreamBuffer,
                                                                    StreamBufferCallbackFunction_t pxSendCompletedCallback,
@@ -2467,7 +2467,7 @@
             StreamBufferHandle_t xReturn;
 
             /**
-             * Streambuffer application level callback functionality is disabled for MPU
+             * Stream buffer application level callback functionality is disabled for MPU
              * enabled ports.
              */
             configASSERT( ( pxSendCompletedCallback == NULL ) &&
@@ -2483,7 +2483,7 @@
 
                     xReturn = xStreamBufferGenericCreateStatic( xBufferSizeBytes,
                                                                 xTriggerLevelBytes,
-                                                                xIsMessageBuffer,
+                                                                xStreamBufferType,
                                                                 pucStreamBufferStorageArea,
                                                                 pxStaticStreamBuffer,
                                                                 NULL,
@@ -2497,7 +2497,7 @@
                 {
                     xReturn = xStreamBufferGenericCreateStatic( xBufferSizeBytes,
                                                                 xTriggerLevelBytes,
-                                                                xIsMessageBuffer,
+                                                                xStreamBufferType,
                                                                 pucStreamBufferStorageArea,
                                                                 pxStaticStreamBuffer,
                                                                 NULL,
@@ -2506,7 +2506,7 @@
             }
             else
             {
-                traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer );
+                traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xStreamBufferType );
                 xReturn = NULL;
             }
 
diff --git a/portable/Common/mpu_wrappers_v2.c b/portable/Common/mpu_wrappers_v2.c
index f8d14b1df..2dc36b33b 100644
--- a/portable/Common/mpu_wrappers_v2.c
+++ b/portable/Common/mpu_wrappers_v2.c
@@ -4662,7 +4662,7 @@
 
         StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes,
                                                              size_t xTriggerLevelBytes,
-                                                             BaseType_t xIsMessageBuffer,
+                                                             BaseType_t xStreamBufferType,
                                                              StreamBufferCallbackFunction_t pxSendCompletedCallback,
                                                              StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) /* PRIVILEGED_FUNCTION */
         {
@@ -4686,7 +4686,7 @@
                 {
                     xInternalStreamBufferHandle = xStreamBufferGenericCreate( xBufferSizeBytes,
                                                                               xTriggerLevelBytes,
-                                                                              xIsMessageBuffer,
+                                                                              xStreamBufferType,
                                                                               NULL,
                                                                               NULL );
 
@@ -4703,7 +4703,7 @@
             }
             else
             {
-                traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer );
+                traceSTREAM_BUFFER_CREATE_FAILED( xStreamBufferType );
                 xExternalStreamBufferHandle = NULL;
             }
 
@@ -4717,7 +4717,7 @@
 
         StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
                                                                    size_t xTriggerLevelBytes,
-                                                                   BaseType_t xIsMessageBuffer,
+                                                                   BaseType_t xStreamBufferType,
                                                                    uint8_t * const pucStreamBufferStorageArea,
                                                                    StaticStreamBuffer_t * const pxStaticStreamBuffer,
                                                                    StreamBufferCallbackFunction_t pxSendCompletedCallback,
@@ -4743,7 +4743,7 @@
                 {
                     xInternalStreamBufferHandle = xStreamBufferGenericCreateStatic( xBufferSizeBytes,
                                                                                     xTriggerLevelBytes,
-                                                                                    xIsMessageBuffer,
+                                                                                    xStreamBufferType,
                                                                                     pucStreamBufferStorageArea,
                                                                                     pxStaticStreamBuffer,
                                                                                     NULL,
@@ -4762,7 +4762,7 @@
             }
             else
             {
-                traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer );
+                traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xStreamBufferType );
                 xExternalStreamBufferHandle = NULL;
             }
 
diff --git a/stream_buffer.c b/stream_buffer.c
index 17a898d45..4471b4f3c 100644
--- a/stream_buffer.c
+++ b/stream_buffer.c
@@ -224,6 +224,7 @@
 /* Bits stored in the ucFlags field of the stream buffer. */
     #define sbFLAGS_IS_MESSAGE_BUFFER          ( ( uint8_t ) 1 ) /* Set if the stream buffer was created as a message buffer, in which case it holds discrete messages rather than a stream. */
     #define sbFLAGS_IS_STATICALLY_ALLOCATED    ( ( uint8_t ) 2 ) /* Set if the stream buffer was created using statically allocated memory. */
+    #define sbFLAGS_IS_BATCHING_BUFFER         ( ( uint8_t ) 4 ) /* Set if the stream buffer was created as a batching buffer, meaning the receiver task will only unblock when the trigger level exceededs. */
 
 /*-----------------------------------------------------------*/
 
@@ -329,25 +330,31 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
     #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
     StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes,
                                                      size_t xTriggerLevelBytes,
-                                                     BaseType_t xIsMessageBuffer,
+                                                     BaseType_t xStreamBufferType,
                                                      StreamBufferCallbackFunction_t pxSendCompletedCallback,
                                                      StreamBufferCallbackFunction_t pxReceiveCompletedCallback )
     {
         void * pvAllocatedMemory;
         uint8_t ucFlags;
 
-        traceENTER_xStreamBufferGenericCreate( xBufferSizeBytes, xTriggerLevelBytes, xIsMessageBuffer, pxSendCompletedCallback, pxReceiveCompletedCallback );
+        traceENTER_xStreamBufferGenericCreate( xBufferSizeBytes, xTriggerLevelBytes, xStreamBufferType, pxSendCompletedCallback, pxReceiveCompletedCallback );
 
         /* In case the stream buffer is going to be used as a message buffer
          * (that is, it will hold discrete messages with a little meta data that
          * says how big the next message is) check the buffer will be large enough
          * to hold at least one message. */
-        if( xIsMessageBuffer == pdTRUE )
+        if( xStreamBufferType == sbTYPE_MESSAGE_BUFFER )
         {
             /* Is a message buffer but not statically allocated. */
             ucFlags = sbFLAGS_IS_MESSAGE_BUFFER;
             configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH );
         }
+        else if( xStreamBufferType == sbTYPE_STREAM_BATCHING_BUFFER )
+        {
+            /* Is a batching buffer but not statically allocated. */
+            ucFlags = sbFLAGS_IS_BATCHING_BUFFER;
+            configASSERT( xBufferSizeBytes > 0 );
+        }
         else
         {
             /* Not a message buffer and not statically allocated. */
@@ -398,11 +405,11 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
                                           pxSendCompletedCallback,
                                           pxReceiveCompletedCallback );
 
-            traceSTREAM_BUFFER_CREATE( ( ( StreamBuffer_t * ) pvAllocatedMemory ), xIsMessageBuffer );
+            traceSTREAM_BUFFER_CREATE( ( ( StreamBuffer_t * ) pvAllocatedMemory ), xStreamBufferType );
         }
         else
         {
-            traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer );
+            traceSTREAM_BUFFER_CREATE_FAILED( xStreamBufferType );
         }
 
         traceRETURN_xStreamBufferGenericCreate( pvAllocatedMemory );
@@ -419,7 +426,7 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
 
     StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
                                                            size_t xTriggerLevelBytes,
-                                                           BaseType_t xIsMessageBuffer,
+                                                           BaseType_t xStreamBufferType,
                                                            uint8_t * const pucStreamBufferStorageArea,
                                                            StaticStreamBuffer_t * const pxStaticStreamBuffer,
                                                            StreamBufferCallbackFunction_t pxSendCompletedCallback,
@@ -432,7 +439,7 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
         StreamBufferHandle_t xReturn;
         uint8_t ucFlags;
 
-        traceENTER_xStreamBufferGenericCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, xIsMessageBuffer, pucStreamBufferStorageArea, pxStaticStreamBuffer, pxSendCompletedCallback, pxReceiveCompletedCallback );
+        traceENTER_xStreamBufferGenericCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, xStreamBufferType, pucStreamBufferStorageArea, pxStaticStreamBuffer, pxSendCompletedCallback, pxReceiveCompletedCallback );
 
         configASSERT( pucStreamBufferStorageArea );
         configASSERT( pxStaticStreamBuffer );
@@ -450,12 +457,18 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
          * says how big the next message is) check the buffer will be large enough
          * to hold at least one message. */
 
-        if( xIsMessageBuffer != pdFALSE )
+        if( xStreamBufferType == sbTYPE_MESSAGE_BUFFER )
         {
             /* Statically allocated message buffer. */
             ucFlags = sbFLAGS_IS_MESSAGE_BUFFER | sbFLAGS_IS_STATICALLY_ALLOCATED;
             configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH );
         }
+        else if( xStreamBufferType == sbTYPE_STREAM_BATCHING_BUFFER )
+        {
+            /* Statically allocated batching buffer. */
+            ucFlags = sbFLAGS_IS_BATCHING_BUFFER | sbFLAGS_IS_STATICALLY_ALLOCATED;
+            configASSERT( xBufferSizeBytes > 0 );
+        }
         else
         {
             /* Statically allocated stream buffer. */
@@ -486,7 +499,7 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
              * again. */
             pxStreamBuffer->ucFlags |= sbFLAGS_IS_STATICALLY_ALLOCATED;
 
-            traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xIsMessageBuffer );
+            traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xStreamBufferType );
 
             /* MISRA Ref 11.3.1 [Misaligned access] */
             /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */
@@ -496,7 +509,7 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
         else
         {
             xReturn = NULL;
-            traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer );
+            traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xStreamBufferType );
         }
 
         traceRETURN_xStreamBufferGenericCreateStatic( xReturn );
@@ -1053,6 +1066,12 @@ size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
     {
         xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;
     }
+    else if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_BATCHING_BUFFER ) != ( uint8_t ) 0 )
+    {
+        /* Force task to block if the batching buffer contains less bytes than
+         * the trigger level. */
+        xBytesToStoreMessageLength = pxStreamBuffer->xTriggerLevelBytes;
+    }
     else
     {
         xBytesToStoreMessageLength = 0;
@@ -1070,7 +1089,9 @@ size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
              * xBytesToStoreMessageLength holds the number of bytes used to hold
              * the length of the next discrete message.  If this function was
              * invoked by a stream buffer read then xBytesToStoreMessageLength will
-             * be 0. */
+             * be 0. If this function was invoked by a stream batch buffer read
+             * then xBytesToStoreMessageLength will be xTriggerLevelBytes value
+             * for the buffer.*/
             if( xBytesAvailable <= xBytesToStoreMessageLength )
             {
                 /* Clear notification state as going to wait for data. */

From c6487d94726e204b09c8bd98aba2e1ce9fd6011e Mon Sep 17 00:00:00 2001
From: Tony Josi <tonyjosi@amazon.com>
Date: Thu, 18 Apr 2024 14:42:53 +0530
Subject: [PATCH 259/424] Fix build with C90 (#1036)

* Fix build with C90

* Fix formatting
---
 include/task.h | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/include/task.h b/include/task.h
index 08452a9b2..f98d84cf2 100644
--- a/include/task.h
+++ b/include/task.h
@@ -180,9 +180,10 @@ typedef struct xTASK_STATUS
 /* Possible return values for eTaskConfirmSleepModeStatus(). */
 typedef enum
 {
-    eAbortSleep = 0,           /* A task has been made ready or a context switch pended since portSUPPRESS_TICKS_AND_SLEEP() was called - abort entering a sleep mode. */
-    eStandardSleep,            /* Enter a sleep mode that will not last any longer than the expected idle time. */
+    eAbortSleep = 0, /* A task has been made ready or a context switch pended since portSUPPRESS_TICKS_AND_SLEEP() was called - abort entering a sleep mode. */
+    eStandardSleep   /* Enter a sleep mode that will not last any longer than the expected idle time. */
     #if ( INCLUDE_vTaskSuspend == 1 )
+        ,
         eNoTasksWaitingTimeout /* No tasks are waiting for a timeout so it is safe to enter a sleep mode that can only be exited by an external interrupt. */
     #endif /* INCLUDE_vTaskSuspend */
 } eSleepModeStatus;

From e143832ad41bcee55cb8103aa82944534225fd3a Mon Sep 17 00:00:00 2001
From: Devaraj Ranganna <devaraj.ranganna@arm.com>
Date: Thu, 18 Apr 2024 13:25:14 +0100
Subject: [PATCH 260/424] tf-m: Update tf-m to TF-Mv2.0.0 release (#1038)

The `portable/ThirdParty/GCC/ARM_TFM/README.md` and
`portable/ThirdParty/GCC/ARM_TFM/os_wrapper_freertos.c` are updated to
support `TF-Mv2.0.0` of trusted-firmware-m release.

Signed-off-by: Devaraj Ranganna <devaraj.ranganna@arm.com>
---
 portable/ThirdParty/GCC/ARM_TFM/README.md     | 38 +++++++++----------
 .../GCC/ARM_TFM/os_wrapper_freertos.c         |  6 +--
 2 files changed, 22 insertions(+), 22 deletions(-)

diff --git a/portable/ThirdParty/GCC/ARM_TFM/README.md b/portable/ThirdParty/GCC/ARM_TFM/README.md
index ae2962447..7df149f54 100644
--- a/portable/ThirdParty/GCC/ARM_TFM/README.md
+++ b/portable/ThirdParty/GCC/ARM_TFM/README.md
@@ -7,16 +7,17 @@ platform.
 
 The Platform Security Architecture (PSA) makes it quicker, easier and cheaper
 to design security into a device from the ground up. PSA is made up of four key
-stages: analyze, architect, implement, and certify. See [PSA Resource Page](https://developer.arm.com/architectures/security-architectures/platform-security-architecture).
+stages: analyze, architect, implement, and certify. See [PSA Resource Page](https://www.arm.com/architecture/security-features/platform-security).
 
 TF-M is an open source project. It provides a reference implementation of PSA
-for Arm M-profile architecture. Please get the details from this [link](https://www.trustedfirmware.org/about/).
+for Arm M-profile architecture. Please get the details from this [link](https://www.trustedfirmware.org/projects/tf-m/).
 
 # Derivation of the source code
 
-* ```os_wrapper_freertos.c```
-  The implementation of APIs which are defined in ```\ns_interface\os_wrapper\mutex.h``` by tf-m-tests
-  (tag: TF-Mv1.5.0 & TF-Mv1.6.0). The implementation is based on FreeRTOS mutex type semaphore.
+* `os_wrapper_freertos.c`
+  The implementation of APIs which are defined in `/interface/include/os_wrapper/mutex.h`
+  in trusted-firmware-m (tag: TF-Mv2.0.0). The implementation is based on
+  FreeRTOS mutex type semaphore.
 
 # Usage notes
 
@@ -28,53 +29,52 @@ To build a project based on this port:
 
 ### Get the TF-M source code
 
-See the [link](https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/) to get the source code. This port is supported by TF-M version **tag: TF-Mv1.5.0** & **tag: TF-Mv1.6.0**.
+See the [link](https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/) to get the source code. This port is supported by TF-M version **tag: TF-Mv2.0.0**.
 
 ### Build TF-M
 
-Please refer to this [link](https://developer.nordicsemi.com/nRF_Connect_SDK/doc/latest/tfm/building/tfm_build_instruction.html) to build the secure side.
-_**Note:** ```TFM_NS_MANAGE_NSID``` must be configured as "OFF" when building TF-M_.
+Please refer to this [link](https://trustedfirmware-m.readthedocs.io/en/latest/getting_started/) to build the secure side.
+_**Note:** `TFM_NS_MANAGE_NSID` must be configured as "OFF" when building TF-M_.
 
 ## Build the Non-Secure Side
 
-Please copy all the files in ```freertos_kernel\portable\GCC\ARM_CM[23|33|55|85]_NTZ``` into the ```freertos_kernel\portable\ThirdParty\GCC\ARM_TFM``` folder before using this port. Note that TrustZone is enabled in this port. The TF-M runs in the Secure Side.
+Please copy all the files in `freertos_kernel/portable/GCC/ARM_CM[23|33|55|85]_NTZ` into the `freertos_kernel/portable/ThirdParty/GCC/ARM_TFM` folder before using this port. Note that TrustZone is enabled in this port. The TF-M runs in the Secure Side.
 
-Please call the API ```tfm_ns_interface_init()``` which is defined in ```\app\tfm_ns_interface.c``` by tf-m-tests
-(tag: TF-Mv1.5.0 & TF-Mv1.6.0) at the very beginning of your application. Otherwise, it will always fail when calling a TF-M service in the Nonsecure Side.
+Please call the API `tfm_ns_interface_init()` which is defined in `/interface/src/os_wrapper/tfm_ns_interface_rtos.c` by trusted-firmware-m (tag: TF-Mv2.0.0) at the very beginning of your application. Otherwise, it will always fail when calling a TF-M service in the Nonsecure Side.
 
 ### Configuration in FreeRTOS kernel
 
-* ```configRUN_FREERTOS_SECURE_ONLY```
+* `configRUN_FREERTOS_SECURE_ONLY`
 This macro should be configured as 0. In this port, TF-M runs in the Secure Side while FreeRTOS
 Kernel runs in the Non-Secure Side.
 
-* ```configENABLE_FPU```
+* `configENABLE_FPU`
 The setting of this macro is decided by the setting in Secure Side which is platform-specific.
 If the Secure Side enables Non-Secure access to FPU, then this macro can be configured as 0 or 1. Otherwise, this macro can only be configured as 0.
 Please note that Cortex-M23 does not support FPU.
 Please refer to [TF-M documentation](https://tf-m-user-guide.trustedfirmware.org/integration_guide/tfm_fpu_support.html) for FPU usage on the Non-Secure side.
 
-* ```configENABLE_MVE```
+* `configENABLE_MVE`
 The setting of this macro is decided by the setting in Secure Side which is platform-specific.
 If the Secure Side enables Non-Secure access to MVE, then this macro can be configured as 0 or 1. Otherwise, this macro can only be configured as 0.
 Please note that only Cortex-M55 and Cortex-M85 support MVE.
 Please refer to [TF-M documentation](https://tf-m-user-guide.trustedfirmware.org/integration_guide/tfm_fpu_support.html) for MVE usage on the Non-Secure side.
 
-* ```configENABLE_TRUSTZONE```
+* `configENABLE_TRUSTZONE`
 This macro should be configured as 0 because TF-M doesn't use the secure context management function of FreeRTOS. New secure context management might be introduced when TF-M supports multiple secure context.
 
 
 ### Integrate TF-M Non-Secure interface with FreeRTOS project
 
 To enable calling TF-M services by the Non-Secure Side, the files below should be included in the FreeRTOS project and built together.
-* files in ```trusted-firmware-m\build\install\interface\src```
+* files in `trusted-firmware-m/build/api_ns/interface/src`
   These files contain the implementation of PSA Functional Developer APIs which can be called by Non-Secure Side directly and PSA Firmware Framework APIs in the IPC model. These files should be taken as part of the Non-Secure source code.
-* files in ```trusted-firmware-m\build\install\interface\include```
+* files in `trusted-firmware-m/build/api_ns/interface/include`
   These files are the necessary header files to call TF-M services.
-* ```trusted-firmware-m\build\install\interface\lib\s_veneers.o```
+* `trusted-firmware-m/build/api_ns/interface/lib/s_veneers.o`
   This object file contains all the Non-Secure callable functions exported by
   TF-M and it should be linked when generating the Non-Secure image.
 
 
 
-*Copyright (c) 2020-2022, Arm Limited. All rights reserved.*
+*Copyright (c) 2020-2024, Arm Limited. All rights reserved.*
diff --git a/portable/ThirdParty/GCC/ARM_TFM/os_wrapper_freertos.c b/portable/ThirdParty/GCC/ARM_TFM/os_wrapper_freertos.c
index 8eb453930..35add2b5a 100644
--- a/portable/ThirdParty/GCC/ARM_TFM/os_wrapper_freertos.c
+++ b/portable/ThirdParty/GCC/ARM_TFM/os_wrapper_freertos.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2020, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2024, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -24,8 +24,8 @@
 
 /*
  * This file contains the implementation of APIs which are defined in
- * os_wrapper/mutex.h by TF-M(tag: TF-Mv1.1). The implementation is based
- * on FreeRTOS mutex type semaphore.
+ * \interface/include/os_wrapper/mutex.h by TF-M(tag: TF-Mv2.0.0).
+ * The implementation is based on FreeRTOS mutex type semaphore.
  */
 
 #include "os_wrapper/mutex.h"

From bbc058967be6446f5e4cf486cad736856b53dd69 Mon Sep 17 00:00:00 2001
From: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Date: Thu, 18 Apr 2024 19:08:51 +0530
Subject: [PATCH 261/424] Fix cmake example errors (#1037)

Add typecasts to prevent compiler warnings. Remove ULL suffix to adhere
to C90.
---
 examples/cmake_example/CMakeLists.txt |  3 +-
 include/event_groups.h                | 24 +++++++-------
 include/list.h                        | 48 +++++++++++++--------------
 list.c                                |  6 ++--
 portable/template/portmacro.h         |  2 +-
 tasks.c                               | 18 +++++-----
 6 files changed, 51 insertions(+), 50 deletions(-)

diff --git a/examples/cmake_example/CMakeLists.txt b/examples/cmake_example/CMakeLists.txt
index bff9317de..7b31cc52a 100644
--- a/examples/cmake_example/CMakeLists.txt
+++ b/examples/cmake_example/CMakeLists.txt
@@ -1,5 +1,4 @@
 cmake_minimum_required(VERSION 3.15)
-
 project(example)
 
 set(FREERTOS_KERNEL_PATH "../../")
@@ -71,3 +70,5 @@ add_executable(${PROJECT_NAME}
 )
 
 target_link_libraries(${PROJECT_NAME} freertos_kernel freertos_config)
+
+set_property(TARGET freertos_kernel PROPERTY C_STANDARD 90)
\ No newline at end of file
diff --git a/include/event_groups.h b/include/event_groups.h
index 8ff26799b..09a5ab53a 100644
--- a/include/event_groups.h
+++ b/include/event_groups.h
@@ -40,20 +40,20 @@
  * item value.  It is important they don't clash with the
  * taskEVENT_LIST_ITEM_VALUE_IN_USE definition. */
 #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    #define eventCLEAR_EVENTS_ON_EXIT_BIT    ( ( uint16_t ) 0x0100U )
-    #define eventUNBLOCKED_DUE_TO_BIT_SET    ( ( uint16_t ) 0x0200U )
-    #define eventWAIT_FOR_ALL_BITS           ( ( uint16_t ) 0x0400U )
-    #define eventEVENT_BITS_CONTROL_BYTES    ( ( uint16_t ) 0xff00U )
+    #define eventCLEAR_EVENTS_ON_EXIT_BIT    ( ( uint16_t ) 0x0100 )
+    #define eventUNBLOCKED_DUE_TO_BIT_SET    ( ( uint16_t ) 0x0200 )
+    #define eventWAIT_FOR_ALL_BITS           ( ( uint16_t ) 0x0400 )
+    #define eventEVENT_BITS_CONTROL_BYTES    ( ( uint16_t ) 0xff00 )
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    #define eventCLEAR_EVENTS_ON_EXIT_BIT    ( ( uint32_t ) 0x01000000UL )
-    #define eventUNBLOCKED_DUE_TO_BIT_SET    ( ( uint32_t ) 0x02000000UL )
-    #define eventWAIT_FOR_ALL_BITS           ( ( uint32_t ) 0x04000000UL )
-    #define eventEVENT_BITS_CONTROL_BYTES    ( ( uint32_t ) 0xff000000UL )
+    #define eventCLEAR_EVENTS_ON_EXIT_BIT    ( ( uint32_t ) 0x01000000 )
+    #define eventUNBLOCKED_DUE_TO_BIT_SET    ( ( uint32_t ) 0x02000000 )
+    #define eventWAIT_FOR_ALL_BITS           ( ( uint32_t ) 0x04000000 )
+    #define eventEVENT_BITS_CONTROL_BYTES    ( ( uint32_t ) 0xff000000 )
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_64_BITS )
-    #define eventCLEAR_EVENTS_ON_EXIT_BIT    ( ( uint64_t ) 0x0100000000000000ULL )
-    #define eventUNBLOCKED_DUE_TO_BIT_SET    ( ( uint64_t ) 0x0200000000000000ULL )
-    #define eventWAIT_FOR_ALL_BITS           ( ( uint64_t ) 0x0400000000000000ULL )
-    #define eventEVENT_BITS_CONTROL_BYTES    ( ( uint64_t ) 0xff00000000000000ULL )
+    #define eventCLEAR_EVENTS_ON_EXIT_BIT    ( ( uint64_t ) 0x0100000000000000 )
+    #define eventUNBLOCKED_DUE_TO_BIT_SET    ( ( uint64_t ) 0x0200000000000000 )
+    #define eventWAIT_FOR_ALL_BITS           ( ( uint64_t ) 0x0400000000000000 )
+    #define eventEVENT_BITS_CONTROL_BYTES    ( ( uint64_t ) 0xff00000000000000 )
 #endif /* if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) */
 
 /* *INDENT-OFF* */
diff --git a/include/list.h b/include/list.h
index 0de51bb5a..b64450c72 100644
--- a/include/list.h
+++ b/include/list.h
@@ -322,19 +322,19 @@ typedef struct xLIST
 #define listREMOVE_ITEM( pxItemToRemove ) \
     do {                                  \
         /* The list item knows which list it is in.  Obtain the list from the list \
-         * item. */                                                              \
-        List_t * const pxList = ( pxItemToRemove )->pxContainer;                 \
-                                                                                 \
-        ( pxItemToRemove )->pxNext->pxPrevious = ( pxItemToRemove )->pxPrevious; \
-        ( pxItemToRemove )->pxPrevious->pxNext = ( pxItemToRemove )->pxNext;     \
-        /* Make sure the index is left pointing to a valid item. */              \
-        if( pxList->pxIndex == ( pxItemToRemove ) )                              \
-        {                                                                        \
-            pxList->pxIndex = ( pxItemToRemove )->pxPrevious;                    \
-        }                                                                        \
-                                                                                 \
-        ( pxItemToRemove )->pxContainer = NULL;                                  \
-        ( ( pxList )->uxNumberOfItems ) -= ( UBaseType_t ) 1U;                   \
+         * item. */                                                                                 \
+        List_t * const pxList = ( pxItemToRemove )->pxContainer;                                    \
+                                                                                                    \
+        ( pxItemToRemove )->pxNext->pxPrevious = ( pxItemToRemove )->pxPrevious;                    \
+        ( pxItemToRemove )->pxPrevious->pxNext = ( pxItemToRemove )->pxNext;                        \
+        /* Make sure the index is left pointing to a valid item. */                                 \
+        if( pxList->pxIndex == ( pxItemToRemove ) )                                                 \
+        {                                                                                           \
+            pxList->pxIndex = ( pxItemToRemove )->pxPrevious;                                       \
+        }                                                                                           \
+                                                                                                    \
+        ( pxItemToRemove )->pxContainer = NULL;                                                     \
+        ( ( pxList )->uxNumberOfItems ) = ( UBaseType_t ) ( ( ( pxList )->uxNumberOfItems ) - 1U ); \
     } while( 0 )
 
 /*
@@ -371,17 +371,17 @@ typedef struct xLIST
                                                                                 \
         /* Insert a new list item into ( pxList ), but rather than sort the list, \
          * makes the new list item the last item to be removed by a call to \
-         * listGET_OWNER_OF_NEXT_ENTRY(). */                   \
-        ( pxNewListItem )->pxNext = pxIndex;                   \
-        ( pxNewListItem )->pxPrevious = pxIndex->pxPrevious;   \
-                                                               \
-        pxIndex->pxPrevious->pxNext = ( pxNewListItem );       \
-        pxIndex->pxPrevious = ( pxNewListItem );               \
-                                                               \
-        /* Remember which list the item is in. */              \
-        ( pxNewListItem )->pxContainer = ( pxList );           \
-                                                               \
-        ( ( pxList )->uxNumberOfItems ) += ( UBaseType_t ) 1U; \
+         * listGET_OWNER_OF_NEXT_ENTRY(). */                                                        \
+        ( pxNewListItem )->pxNext = pxIndex;                                                        \
+        ( pxNewListItem )->pxPrevious = pxIndex->pxPrevious;                                        \
+                                                                                                    \
+        pxIndex->pxPrevious->pxNext = ( pxNewListItem );                                            \
+        pxIndex->pxPrevious = ( pxNewListItem );                                                    \
+                                                                                                    \
+        /* Remember which list the item is in. */                                                   \
+        ( pxNewListItem )->pxContainer = ( pxList );                                                \
+                                                                                                    \
+        ( ( pxList )->uxNumberOfItems ) = ( UBaseType_t ) ( ( ( pxList )->uxNumberOfItems ) + 1U ); \
     } while( 0 )
 
 /*
diff --git a/list.c b/list.c
index 87fa7aba3..fc99538b2 100644
--- a/list.c
+++ b/list.c
@@ -130,7 +130,7 @@ void vListInsertEnd( List_t * const pxList,
     /* Remember which list the item is in. */
     pxNewListItem->pxContainer = pxList;
 
-    ( pxList->uxNumberOfItems ) += ( UBaseType_t ) 1U;
+    ( pxList->uxNumberOfItems ) = ( UBaseType_t ) ( pxList->uxNumberOfItems + 1U );
 
     traceRETURN_vListInsertEnd();
 }
@@ -205,7 +205,7 @@ void vListInsert( List_t * const pxList,
      * item later. */
     pxNewListItem->pxContainer = pxList;
 
-    ( pxList->uxNumberOfItems ) += ( UBaseType_t ) 1U;
+    ( pxList->uxNumberOfItems ) = ( UBaseType_t ) ( pxList->uxNumberOfItems + 1U );
 
     traceRETURN_vListInsert();
 }
@@ -237,7 +237,7 @@ UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )
     }
 
     pxItemToRemove->pxContainer = NULL;
-    ( pxList->uxNumberOfItems ) -= ( UBaseType_t ) 1U;
+    ( pxList->uxNumberOfItems ) = ( UBaseType_t ) ( pxList->uxNumberOfItems - 1U );
 
     traceRETURN_uxListRemove( pxList->uxNumberOfItems );
 
diff --git a/portable/template/portmacro.h b/portable/template/portmacro.h
index 199053208..3b5da0dd2 100644
--- a/portable/template/portmacro.h
+++ b/portable/template/portmacro.h
@@ -40,7 +40,7 @@ typedef unsigned char    UBaseType_t;
     #define portMAX_DELAY    ( TickType_t ) 0xffffffffUL
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_64_BITS )
     typedef uint64_t     TickType_t;
-    #define portMAX_DELAY    ( TickType_t ) 0xffffffffffffffffULL
+    #define portMAX_DELAY    ( TickType_t ) 0xffffffffffffffff
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
diff --git a/tasks.c b/tasks.c
index 5cec846d0..7f808cc4f 100644
--- a/tasks.c
+++ b/tasks.c
@@ -255,7 +255,7 @@
         pxTemp = pxDelayedTaskList;                                               \
         pxDelayedTaskList = pxOverflowDelayedTaskList;                            \
         pxOverflowDelayedTaskList = pxTemp;                                       \
-        xNumOfOverflows += ( BaseType_t ) 1;                                      \
+        xNumOfOverflows = ( BaseType_t ) ( xNumOfOverflows + 1 );                 \
         prvResetNextTaskUnblockTime();                                            \
     } while( 0 )
 
@@ -291,11 +291,11 @@
  * responsibility of whichever module is using the value to ensure it gets set back
  * to its original value when it is released. */
 #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    #define taskEVENT_LIST_ITEM_VALUE_IN_USE    ( ( uint16_t ) 0x8000U )
+    #define taskEVENT_LIST_ITEM_VALUE_IN_USE    ( ( uint16_t ) 0x8000 )
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    #define taskEVENT_LIST_ITEM_VALUE_IN_USE    ( ( uint32_t ) 0x80000000UL )
+    #define taskEVENT_LIST_ITEM_VALUE_IN_USE    ( ( uint32_t ) 0x80000000 )
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_64_BITS )
-    #define taskEVENT_LIST_ITEM_VALUE_IN_USE    ( ( uint64_t ) 0x8000000000000000ULL )
+    #define taskEVENT_LIST_ITEM_VALUE_IN_USE    ( ( uint64_t ) 0x8000000000000000 )
 #endif
 
 /* Indicates that the task is not actively running on any core. */
@@ -903,7 +903,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
                 /* System idle tasks are being assigned a priority of tskIDLE_PRIORITY - 1 here. */
                 if( ( pxCurrentTCBs[ xCoreID ]->uxTaskAttributes & taskATTRIBUTE_IS_IDLE ) != 0U )
                 {
-                    xCurrentCoreTaskPriority = xCurrentCoreTaskPriority - 1;
+                    xCurrentCoreTaskPriority = ( BaseType_t ) ( xCurrentCoreTaskPriority - 1 );
                 }
 
                 if( ( taskTASK_IS_RUNNING( pxCurrentTCBs[ xCoreID ] ) != pdFALSE ) && ( xYieldPendings[ xCoreID ] == pdFALSE ) )
@@ -2022,7 +2022,7 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
          * updated. */
         taskENTER_CRITICAL();
         {
-            uxCurrentNumberOfTasks += ( UBaseType_t ) 1U;
+            uxCurrentNumberOfTasks = ( UBaseType_t ) ( uxCurrentNumberOfTasks + 1U );
 
             if( pxCurrentTCB == NULL )
             {
@@ -3594,7 +3594,7 @@ static BaseType_t prvCreateIdleTasks( void )
                 }
                 else
                 {
-                    vApplicationGetPassiveIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &uxIdleTaskStackSize, xCoreID - 1 );
+                    vApplicationGetPassiveIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &uxIdleTaskStackSize, ( BaseType_t ) ( xCoreID - 1 ) );
                 }
             }
             #endif /* if ( configNUMBER_OF_CORES == 1 ) */
@@ -3816,7 +3816,7 @@ void vTaskSuspendAll( void )
 
         /* The scheduler is suspended if uxSchedulerSuspended is non-zero.  An increment
          * is used to allow calls to vTaskSuspendAll() to nest. */
-        uxSchedulerSuspended += ( UBaseType_t ) 1U;
+        uxSchedulerSuspended = ( UBaseType_t ) ( uxSchedulerSuspended + 1U );
 
         /* Enforces ordering for ports and optimised compilers that may otherwise place
          * the above increment elsewhere. */
@@ -3969,7 +3969,7 @@ BaseType_t xTaskResumeAll( void )
              * previous call to vTaskSuspendAll(). */
             configASSERT( uxSchedulerSuspended != 0U );
 
-            uxSchedulerSuspended -= ( UBaseType_t ) 1U;
+            uxSchedulerSuspended = ( UBaseType_t ) ( uxSchedulerSuspended - 1U );
             portRELEASE_TASK_LOCK();
 
             if( uxSchedulerSuspended == ( UBaseType_t ) 0U )

From 8d280217cde3462373cfd7e361988f566b26cbc4 Mon Sep 17 00:00:00 2001
From: Devaraj Ranganna <devaraj.ranganna@arm.com>
Date: Thu, 18 Apr 2024 19:45:04 +0100
Subject: [PATCH 262/424] armv8-m: Remove redundant constant pools (#1035)

Currently in Armv8-M GCC/ArmClang ports, constant pool is used to
define literals needed for `ldr` instructions. However, those
constant pools are defined with `.align 4` which increases code size.
Instead of defining the constant pool with `.align 4`, let the
compiler hanlde the constant pool and the required alignment.

Signed-off-by: Devaraj Ranganna <devaraj.ranganna@arm.com>
Co-authored-by: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
---
 .../portable/GCC/ARM_CM23/portasm.c           | 104 ++++++------------
 .../portable/GCC/ARM_CM23_NTZ/portasm.c       |  82 +++++---------
 .../portable/GCC/ARM_CM33/portasm.c           |  89 +++++----------
 .../portable/GCC/ARM_CM33_NTZ/portasm.c       |  68 ++++--------
 portable/GCC/ARM_CM23/non_secure/portasm.c    | 104 ++++++------------
 .../GCC/ARM_CM23_NTZ/non_secure/portasm.c     |  82 +++++---------
 .../ARM_CM33/non_secure/mpu_wrappers_v2_asm.c |   1 +
 portable/GCC/ARM_CM33/non_secure/portasm.c    |  89 +++++----------
 .../GCC/ARM_CM33_NTZ/non_secure/portasm.c     |  68 ++++--------
 portable/GCC/ARM_CM35P/non_secure/portasm.c   |  89 +++++----------
 .../GCC/ARM_CM35P_NTZ/non_secure/portasm.c    |  68 ++++--------
 portable/GCC/ARM_CM55/non_secure/portasm.c    |  89 +++++----------
 .../GCC/ARM_CM55_NTZ/non_secure/portasm.c     |  68 ++++--------
 portable/GCC/ARM_CM85/non_secure/portasm.c    |  89 +++++----------
 .../GCC/ARM_CM85_NTZ/non_secure/portasm.c     |  68 ++++--------
 15 files changed, 372 insertions(+), 786 deletions(-)

diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portasm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portasm.c
index 8df9bfa7c..978d35259 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portasm.c
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portasm.c
@@ -56,11 +56,11 @@
             " .syntax unified                                 \n"
             "                                                 \n"
             " program_mpu_first_task:                         \n"
-            "    ldr r3, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r3, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB.*/
             "                                                 \n"
             "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-            "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
             "    movs r3, #1                                  \n" /* r3 = 1. */
             "    bics r2, r3                                  \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
@@ -68,34 +68,34 @@
             "                                                 \n"
             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
             "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-            "    ldr r2, xMAIR0Const2                         \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    ldr r2, =0xe000edc0                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
             "    str r1, [r2]                                 \n" /* Program MAIR0. */
             "                                                 \n"
             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-            "    ldr r1, xRNRConst2                           \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "    ldr r1, =0xe000ed98                          \n" /* r1 = 0xe000ed98 [Location of RNR]. */
             "                                                 \n"
             "    movs r3, #4                                  \n" /* r3 = 4. */
             "    str r3, [r1]                                 \n" /* Program RNR = 4. */
             "    ldmia r0!, {r4-r5}                           \n" /* Read first set of RBAR/RLAR registers from TCB. */
-            "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
             "    stmia r2!, {r4-r5}                           \n" /* Write first set of RBAR/RLAR registers. */
             "    movs r3, #5                                  \n" /* r3 = 5. */
             "    str r3, [r1]                                 \n" /* Program RNR = 5. */
             "    ldmia r0!, {r4-r5}                           \n" /* Read second set of RBAR/RLAR registers from TCB. */
-            "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
             "    stmia r2!, {r4-r5}                           \n" /* Write second set of RBAR/RLAR registers. */
             "    movs r3, #6                                  \n" /* r3 = 6. */
             "    str r3, [r1]                                 \n" /* Program RNR = 6. */
             "    ldmia r0!, {r4-r5}                           \n" /* Read third set of RBAR/RLAR registers from TCB. */
-            "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
             "    stmia r2!, {r4-r5}                           \n" /* Write third set of RBAR/RLAR registers. */
             "    movs r3, #7                                  \n" /* r3 = 6. */
             "    str r3, [r1]                                 \n" /* Program RNR = 7. */
             "    ldmia r0!, {r4-r5}                           \n" /* Read fourth set of RBAR/RLAR registers from TCB. */
-            "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
             "    stmia r2!, {r4-r5}                           \n" /* Write fourth set of RBAR/RLAR registers. */
             "                                                 \n"
-            "   ldr r1, xMPUCTRLConst2                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "   ldr r1, =0xe000ed94                           \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
             "   movs r3, #1                                   \n" /* r3 = 1. */
             "   orrs r2, r3                                   \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
@@ -103,7 +103,7 @@
             "   dsb                                           \n" /* Force memory writes before continuing. */
             "                                                 \n"
             " restore_context_first_task:                     \n"
-            "    ldr r3, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r3, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "    ldr r1, [r3]                                 \n" /* r1 = pxCurrentTCB.*/
             "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
             "                                                 \n"
@@ -114,7 +114,7 @@
             "    msr psp, r3                                  \n"
             "    msr control, r5                              \n"
             "    mov lr, r6                                   \n"
-            "    ldr r4, xSecureContextConst2                 \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "    ldr r4, =xSecureContext                      \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
             "    str r0, [r4]                                 \n" /* Restore xSecureContext. */
             "                                                 \n"
             " restore_general_regs_first_task:                \n"
@@ -136,14 +136,6 @@
             " restore_context_done_first_task:                \n"
             "    str r2, [r1]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
             "    bx lr                                        \n"
-            "                                                 \n"
-            " .align 4                                        \n"
-            " pxCurrentTCBConst2: .word pxCurrentTCB          \n"
-            " xSecureContextConst2: .word xSecureContext      \n"
-            " xMPUCTRLConst2: .word 0xe000ed94                \n"
-            " xMAIR0Const2: .word 0xe000edc0                  \n"
-            " xRNRConst2: .word 0xe000ed98                    \n"
-            " xRBARConst2: .word 0xe000ed9c                   \n"
         );
     }
 
@@ -155,12 +147,12 @@
         (
             "   .syntax unified                                 \n"
             "                                                   \n"
-            "   ldr  r2, pxCurrentTCBConst2                     \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr  r2, =pxCurrentTCB                          \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr  r3, [r2]                                   \n" /* Read pxCurrentTCB. */
             "   ldr  r0, [r3]                                   \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
             "                                                   \n"
             "   ldm  r0!, {r1-r3}                               \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
-            "   ldr  r4, xSecureContextConst2                   \n"
+            "   ldr  r4, =xSecureContext                        \n"
             "   str  r1, [r4]                                   \n" /* Set xSecureContext to this task's value for the same. */
             "   movs r1, #2                                     \n" /* r1 = 2. */
             "   msr  CONTROL, r1                                \n" /* Switch to use PSP in the thread mode. */
@@ -168,10 +160,6 @@
             "   msr  psp, r0                                    \n" /* This is now the new top of stack to use in the task. */
             "   isb                                             \n"
             "   bx   r3                                         \n" /* Finally, branch to EXC_RETURN. */
-            "                                                   \n"
-            "   .align 4                                        \n"
-            "pxCurrentTCBConst2: .word pxCurrentTCB             \n"
-            "xSecureContextConst2: .word xSecureContext         \n"
         );
     }
 
@@ -193,8 +181,6 @@ BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
         " running_privileged:                               \n"
         "   movs r0, #1                                     \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
         "   bx lr                                           \n" /* Return. */
-        "                                                   \n"
-        "   .align 4                                        \n"
         ::: "r0", "r1", "memory"
     );
 }
@@ -238,7 +224,7 @@ void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   ldr r0, xVTORConst                              \n" /* Use the NVIC offset register to locate the stack. */
+        "   ldr r0, =0xe000ed08                             \n" /* Use the NVIC offset register to locate the stack. */
         "   ldr r0, [r0]                                    \n" /* Read the VTOR register which gives the address of vector table. */
         "   ldr r0, [r0]                                    \n" /* The first entry in vector table is stack pointer. */
         "   msr msp, r0                                     \n" /* Set the MSP back to the start of the stack. */
@@ -247,9 +233,6 @@ void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
         "   isb                                             \n"
         "   svc %0                                          \n" /* System call to start the first task. */
         "   nop                                             \n"
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "xVTORConst: .word 0xe000ed08                       \n"
         ::"i" ( portSVC_START_SCHEDULER ) : "memory"
     );
 }
@@ -292,9 +275,9 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             " .extern SecureContext_SaveContext               \n"
             " .extern SecureContext_LoadContext               \n"
             "                                                 \n"
-            " ldr r3, xSecureContextConst                     \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            " ldr r3, =xSecureContext                         \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
             " ldr r0, [r3]                                    \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
-            " ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            " ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             " ldr r1, [r3]                                    \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later.*/
             " ldr r2, [r1]                                    \n" /* r2 = Location in TCB where the context should be saved. */
             "                                                 \n"
@@ -337,11 +320,11 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    cpsie i                                      \n"
             "                                                 \n"
             " program_mpu:                                    \n"
-            "    ldr r3, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r3, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB.*/
             "                                                 \n"
             "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-            "    ldr r1, xMPUCTRLConst                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
             "    movs r3, #1                                  \n" /* r3 = 1. */
             "    bics r2, r3                                  \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
@@ -349,34 +332,34 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "                                                 \n"
             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
             "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-            "    ldr r2, xMAIR0Const                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    ldr r2, =0xe000edc0                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
             "    str r1, [r2]                                 \n" /* Program MAIR0. */
             "                                                 \n"
             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-            "    ldr r1, xRNRConst                            \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "    ldr r1, =0xe000ed98                          \n" /* r1 = 0xe000ed98 [Location of RNR]. */
             "                                                 \n"
             "    movs r3, #4                                  \n" /* r3 = 4. */
             "    str r3, [r1]                                 \n" /* Program RNR = 4. */
             "    ldmia r0!, {r4-r5}                           \n" /* Read first set of RBAR/RLAR registers from TCB. */
-            "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
             "    stmia r2!, {r4-r5}                           \n" /* Write first set of RBAR/RLAR registers. */
             "    movs r3, #5                                  \n" /* r3 = 5. */
             "    str r3, [r1]                                 \n" /* Program RNR = 5. */
             "    ldmia r0!, {r4-r5}                           \n" /* Read second set of RBAR/RLAR registers from TCB. */
-            "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
             "    stmia r2!, {r4-r5}                           \n" /* Write second set of RBAR/RLAR registers. */
             "    movs r3, #6                                  \n" /* r3 = 6. */
             "    str r3, [r1]                                 \n" /* Program RNR = 6. */
             "    ldmia r0!, {r4-r5}                           \n" /* Read third set of RBAR/RLAR registers from TCB. */
-            "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
             "    stmia r2!, {r4-r5}                           \n" /* Write third set of RBAR/RLAR registers. */
             "    movs r3, #7                                  \n" /* r3 = 6. */
             "    str r3, [r1]                                 \n" /* Program RNR = 7. */
             "    ldmia r0!, {r4-r5}                           \n" /* Read fourth set of RBAR/RLAR registers from TCB. */
-            "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
             "    stmia r2!, {r4-r5}                           \n" /* Write fourth set of RBAR/RLAR registers. */
             "                                                 \n"
-            "    ldr r1, xMPUCTRLConst                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
             "    movs r3, #1                                  \n" /* r3 = 1. */
             "    orrs r2, r3                                  \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
@@ -384,7 +367,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    dsb                                          \n" /* Force memory writes before continuing. */
             "                                                 \n"
             " restore_context:                                \n"
-            "    ldr r3, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r3, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "    ldr r1, [r3]                                 \n" /* r1 = pxCurrentTCB.*/
             "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
             "                                                 \n"
@@ -395,7 +378,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    msr psp, r3                                  \n"
             "    msr control, r5                              \n"
             "    mov lr, r6                                   \n"
-            "    ldr r4, xSecureContextConst                  \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "    ldr r4, =xSecureContext                      \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
             "    str r0, [r4]                                 \n" /* Restore xSecureContext. */
             "    cbz r0, restore_ns_context                   \n" /* No secure context to restore. */
             "                                                 \n"
@@ -429,14 +412,6 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             " restore_context_done:                           \n"
             "    str r2, [r1]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
             "    bx lr                                        \n"
-            "                                                 \n"
-            " .align 4                                        \n"
-            " pxCurrentTCBConst: .word pxCurrentTCB           \n"
-            " xSecureContextConst: .word xSecureContext       \n"
-            " xMPUCTRLConst: .word 0xe000ed94                 \n"
-            " xMAIR0Const: .word 0xe000edc0                   \n"
-            " xRNRConst: .word 0xe000ed98                     \n"
-            " xRBARConst: .word 0xe000ed9c                    \n"
         );
     }
 
@@ -450,9 +425,9 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   .extern SecureContext_SaveContext               \n"
             "   .extern SecureContext_LoadContext               \n"
             "                                                   \n"
-            "   ldr r3, xSecureContextConst                     \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "   ldr r3, =xSecureContext                         \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
             "   ldr r0, [r3]                                    \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
-            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later.*/
             "   mrs r2, psp                                     \n" /* Read PSP in r2. */
             "                                                   \n"
@@ -463,7 +438,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   mov lr, r3                                      \n" /* LR = r3. */
             "   lsls r1, r3, #25                                \n" /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
             "   bpl save_ns_context                             \n" /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
             "   subs r2, r2, #12                                \n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */
             "   str r2, [r1]                                    \n" /* Save the new top of stack in TCB. */
@@ -473,7 +448,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   b select_next_task                              \n"
             "                                                   \n"
             " save_ns_context:                                  \n"
-            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
             "   subs r2, r2, #44                                \n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
             "   str r2, [r1]                                    \n" /* Save the new top of stack in TCB. */
@@ -491,16 +466,16 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   bl vTaskSwitchContext                           \n"
             "   cpsie i                                         \n"
             "                                                   \n"
-            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
             "   ldr r2, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
             "                                                   \n"
             "   ldmia r2!, {r0, r1, r4}                         \n" /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
             "   mov lr, r4                                      \n" /* LR = r4. */
-            "   ldr r3, xSecureContextConst                     \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "   ldr r3, =xSecureContext                         \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
             "   str r0, [r3]                                    \n" /* Restore the task's xSecureContext. */
             "   cbz r0, restore_ns_context                      \n" /* If there is no secure context for the task, restore the non-secure context. */
-            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
             "   push {r2, r4}                                   \n"
             "   bl SecureContext_LoadContext                    \n" /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
@@ -522,10 +497,6 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   subs r2, r2, #32                                \n" /* Go back to the low registers. */
             "   ldmia r2!, {r4-r7}                              \n" /* Restore the low registers that are not automatically restored. */
             "   bx lr                                           \n"
-            "                                                   \n"
-            "   .align 4                                        \n"
-            "pxCurrentTCBConst: .word pxCurrentTCB              \n"
-            "xSecureContextConst: .word xSecureContext          \n"
         );
     }
 
@@ -588,15 +559,12 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   tst r0, r1                                      \n"
             "   beq stacking_used_msp                           \n"
             "   mrs r0, psp                                     \n"
-            "   ldr r2, svchandler_address_const                \n"
+            "   ldr r2, =vPortSVCHandler_C                      \n"
             "   bx r2                                           \n"
             " stacking_used_msp:                                \n"
             "   mrs r0, msp                                     \n"
-            "   ldr r2, svchandler_address_const                \n"
+            "   ldr r2, =vPortSVCHandler_C                      \n"
             "   bx r2                                           \n"
-            "                                                   \n"
-            "   .align 4                                        \n"
-            "svchandler_address_const: .word vPortSVCHandler_C  \n"
         );
     }
 
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portasm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portasm.c
index 82bff509e..d215f8f73 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portasm.c
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portasm.c
@@ -56,11 +56,11 @@
             " .syntax unified                                 \n"
             "                                                 \n"
             " program_mpu_first_task:                         \n"
-            "    ldr r3, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r3, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB.*/
             "                                                 \n"
             "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-            "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
             "    movs r3, #1                                  \n" /* r3 = 1. */
             "    bics r2, r3                                  \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
@@ -68,34 +68,34 @@
             "                                                 \n"
             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
             "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-            "    ldr r2, xMAIR0Const2                         \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    ldr r2, =0xe000edc0                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
             "    str r1, [r2]                                 \n" /* Program MAIR0. */
             "                                                 \n"
             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-            "    ldr r1, xRNRConst2                           \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "    ldr r1, =0xe000ed98                          \n" /* r1 = 0xe000ed98 [Location of RNR]. */
             "                                                 \n"
             "    movs r3, #4                                  \n" /* r3 = 4. */
             "    str r3, [r1]                                 \n" /* Program RNR = 4. */
             "    ldmia r0!, {r4-r5}                           \n" /* Read first set of RBAR/RLAR registers from TCB. */
-            "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
             "    stmia r2!, {r4-r5}                           \n" /* Write first set of RBAR/RLAR registers. */
             "    movs r3, #5                                  \n" /* r3 = 5. */
             "    str r3, [r1]                                 \n" /* Program RNR = 5. */
             "    ldmia r0!, {r4-r5}                           \n" /* Read second set of RBAR/RLAR registers from TCB. */
-            "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
             "    stmia r2!, {r4-r5}                           \n" /* Write second set of RBAR/RLAR registers. */
             "    movs r3, #6                                  \n" /* r3 = 6. */
             "    str r3, [r1]                                 \n" /* Program RNR = 6. */
             "    ldmia r0!, {r4-r5}                           \n" /* Read third set of RBAR/RLAR registers from TCB. */
-            "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
             "    stmia r2!, {r4-r5}                           \n" /* Write third set of RBAR/RLAR registers. */
             "    movs r3, #7                                  \n" /* r3 = 6. */
             "    str r3, [r1]                                 \n" /* Program RNR = 7. */
             "    ldmia r0!, {r4-r5}                           \n" /* Read fourth set of RBAR/RLAR registers from TCB. */
-            "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
             "    stmia r2!, {r4-r5}                           \n" /* Write fourth set of RBAR/RLAR registers. */
             "                                                 \n"
-            "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
             "    movs r3, #1                                  \n" /* r3 = 1. */
             "    orrs r2, r3                                  \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
@@ -103,7 +103,7 @@
             "    dsb                                          \n" /* Force memory writes before continuing. */
             "                                                 \n"
             " restore_context_first_task:                     \n"
-            "    ldr r2, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r2, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB.*/
             "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
             "                                                 \n"
@@ -137,13 +137,6 @@
             " restore_context_done_first_task:                \n"
             "    str r1, [r0]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
             "    bx lr                                        \n"
-            "                                                 \n"
-            " .align 4                                        \n"
-            " pxCurrentTCBConst2: .word pxCurrentTCB          \n"
-            " xMPUCTRLConst2: .word 0xe000ed94                \n"
-            " xMAIR0Const2: .word 0xe000edc0                  \n"
-            " xRNRConst2: .word 0xe000ed98                    \n"
-            " xRBARConst2: .word 0xe000ed9c                   \n"
         );
     }
 
@@ -155,7 +148,7 @@
         (
             "   .syntax unified                                 \n"
             "                                                   \n"
-            "   ldr  r2, pxCurrentTCBConst2                     \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr  r2, =pxCurrentTCB                          \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr  r1, [r2]                                   \n" /* Read pxCurrentTCB. */
             "   ldr  r0, [r1]                                   \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
             "                                                   \n"
@@ -169,9 +162,6 @@
             "   msr  psp, r0                                    \n" /* This is now the new top of stack to use in the task. */
             "   isb                                             \n"
             "   bx   r2                                         \n" /* Finally, branch to EXC_RETURN. */
-            "                                                   \n"
-            "   .align 4                                        \n"
-            "pxCurrentTCBConst2: .word pxCurrentTCB             \n"
         );
     }
 
@@ -193,8 +183,6 @@ BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
         " running_privileged:                               \n"
         "   movs r0, #1                                     \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
         "   bx lr                                           \n" /* Return. */
-        "                                                   \n"
-        "   .align 4                                        \n"
         ::: "r0", "r1", "memory"
     );
 }
@@ -238,7 +226,7 @@ void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   ldr r0, xVTORConst                              \n" /* Use the NVIC offset register to locate the stack. */
+        "   ldr r0, =0xe000ed08                             \n" /* Use the NVIC offset register to locate the stack. */
         "   ldr r0, [r0]                                    \n" /* Read the VTOR register which gives the address of vector table. */
         "   ldr r0, [r0]                                    \n" /* The first entry in vector table is stack pointer. */
         "   msr msp, r0                                     \n" /* Set the MSP back to the start of the stack. */
@@ -247,9 +235,6 @@ void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
         "   isb                                             \n"
         "   svc %0                                          \n" /* System call to start the first task. */
         "   nop                                             \n"
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "xVTORConst: .word 0xe000ed08                       \n"
         ::"i" ( portSVC_START_SCHEDULER ) : "memory"
     );
 }
@@ -290,7 +275,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
         (
             " .syntax unified                                 \n"
             "                                                 \n"
-            " ldr r2, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            " ldr r2, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             " ldr r0, [r2]                                    \n" /* r0 = pxCurrentTCB. */
             " ldr r1, [r0]                                    \n" /* r1 = Location in TCB where the context should be saved. */
             " mrs r2, psp                                     \n" /* r2 = PSP. */
@@ -325,11 +310,11 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    cpsie i                                      \n"
             "                                                 \n"
             " program_mpu:                                    \n"
-            "    ldr r3, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r3, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB.*/
             "                                                 \n"
             "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-            "    ldr r1, xMPUCTRLConst                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
             "    movs r3, #1                                  \n" /* r3 = 1. */
             "    bics r2, r3                                  \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
@@ -337,34 +322,34 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "                                                 \n"
             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
             "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-            "    ldr r2, xMAIR0Const                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    ldr r2, =0xe000edc0                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
             "    str r1, [r2]                                 \n" /* Program MAIR0. */
             "                                                 \n"
             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-            "    ldr r1, xRNRConst                            \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "    ldr r1, =0xe000ed98                          \n" /* r1 = 0xe000ed98 [Location of RNR]. */
             "                                                 \n"
             "    movs r3, #4                                  \n" /* r3 = 4. */
             "    str r3, [r1]                                 \n" /* Program RNR = 4. */
             "    ldmia r0!, {r4-r5}                           \n" /* Read first set of RBAR/RLAR registers from TCB. */
-            "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
             "    stmia r2!, {r4-r5}                           \n" /* Write first set of RBAR/RLAR registers. */
             "    movs r3, #5                                  \n" /* r3 = 5. */
             "    str r3, [r1]                                 \n" /* Program RNR = 5. */
             "    ldmia r0!, {r4-r5}                           \n" /* Read second set of RBAR/RLAR registers from TCB. */
-            "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
             "    stmia r2!, {r4-r5}                           \n" /* Write second set of RBAR/RLAR registers. */
             "    movs r3, #6                                  \n" /* r3 = 6. */
             "    str r3, [r1]                                 \n" /* Program RNR = 6. */
             "    ldmia r0!, {r4-r5}                           \n" /* Read third set of RBAR/RLAR registers from TCB. */
-            "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
             "    stmia r2!, {r4-r5}                           \n" /* Write third set of RBAR/RLAR registers. */
             "    movs r3, #7                                  \n" /* r3 = 6. */
             "    str r3, [r1]                                 \n" /* Program RNR = 7. */
             "    ldmia r0!, {r4-r5}                           \n" /* Read fourth set of RBAR/RLAR registers from TCB. */
-            "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
             "    stmia r2!, {r4-r5}                           \n" /* Write fourth set of RBAR/RLAR registers. */
             "                                                 \n"
-            "    ldr r1, xMPUCTRLConst                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
             "    movs r3, #1                                  \n" /* r3 = 1. */
             "    orrs r2, r3                                  \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
@@ -372,7 +357,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    dsb                                          \n" /* Force memory writes before continuing. */
             "                                                 \n"
             " restore_context:                                \n"
-            "    ldr r2, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r2, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB.*/
             "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
             "                                                 \n"
@@ -406,13 +391,6 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             " restore_context_done:                           \n"
             "    str r1, [r0]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
             "    bx lr                                        \n"
-            "                                                 \n"
-            " .align 4                                        \n"
-            " pxCurrentTCBConst: .word pxCurrentTCB           \n"
-            " xMPUCTRLConst: .word 0xe000ed94                 \n"
-            " xMAIR0Const: .word 0xe000edc0                   \n"
-            " xRNRConst: .word 0xe000ed98                     \n"
-            " xRBARConst: .word 0xe000ed9c                    \n"
         );
     }
 
@@ -425,7 +403,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   .syntax unified                                 \n"
             "                                                   \n"
             "   mrs r0, psp                                     \n" /* Read PSP in r0. */
-            "   ldr r2, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r2, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr r1, [r2]                                    \n" /* Read pxCurrentTCB. */
             "   subs r0, r0, #40                                \n" /* Make space for PSPLIM, LR and the remaining registers on the stack. */
             "   str r0, [r1]                                    \n" /* Save the new top of stack in TCB. */
@@ -446,7 +424,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   bl vTaskSwitchContext                           \n"
             "   cpsie i                                         \n"
             "                                                   \n"
-            "   ldr r2, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r2, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr r1, [r2]                                    \n" /* Read pxCurrentTCB. */
             "   ldr r0, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
             "                                                   \n"
@@ -463,9 +441,6 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
                 "   msr psplim, r2                              \n" /* Restore the PSPLIM register value for the task. */
             #endif
             "   bx r3                                           \n"
-            "                                                   \n"
-            "   .align 4                                        \n"
-            "pxCurrentTCBConst: .word pxCurrentTCB              \n"
         );
     }
 
@@ -528,15 +503,12 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   tst r0, r1                                      \n"
             "   beq stacking_used_msp                           \n"
             "   mrs r0, psp                                     \n"
-            "   ldr r2, svchandler_address_const                \n"
+            "   ldr r2, =vPortSVCHandler_C                      \n"
             "   bx r2                                           \n"
             " stacking_used_msp:                                \n"
             "   mrs r0, msp                                     \n"
-            "   ldr r2, svchandler_address_const                \n"
+            "   ldr r2, =vPortSVCHandler_C                      \n"
             "   bx r2                                           \n"
-            "                                                   \n"
-            "   .align 4                                        \n"
-            "svchandler_address_const: .word vPortSVCHandler_C  \n"
         );
     }
 
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c
index 1ee04b76d..aa9379fdf 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c
@@ -52,23 +52,23 @@
             " .syntax unified                                 \n"
             "                                                 \n"
             " program_mpu_first_task:                         \n"
-            "    ldr r3, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r3, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB. */
             "                                                 \n"
             "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-            "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
             "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
             "    str r2, [r1]                                 \n" /* Disable MPU. */
             "                                                 \n"
             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
             "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-            "    ldr r2, xMAIR0Const2                         \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    ldr r2, =0xe000edc0                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
             "    str r1, [r2]                                 \n" /* Program MAIR0. */
             "                                                 \n"
             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-            "    ldr r1, xRNRConst2                           \n" /* r1 = 0xe000ed98 [Location of RNR]. */
-            "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    ldr r1, =0xe000ed98                          \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
             "                                                 \n"
             "    movs r3, #4                                  \n" /* r3 = 4. */
             "    str r3, [r1]                                 \n" /* Program RNR = 4. */
@@ -86,14 +86,14 @@
                 "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
             #endif /* configTOTAL_MPU_REGIONS == 16 */
             "                                                 \n"
-            "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
             "    orr r2, #1                                   \n" /* r2 = r1 | 1 i.e. Set the bit 0 in r2. */
             "    str r2, [r1]                                 \n" /* Enable MPU. */
             "    dsb                                          \n" /* Force memory writes before continuing. */
             "                                                 \n"
             " restore_context_first_task:                     \n"
-            "    ldr r3, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r3, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "    ldr r1, [r3]                                 \n" /* r1 = pxCurrentTCB.*/
             "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
             "                                                 \n"
@@ -102,7 +102,7 @@
             "    msr psp, r3                                  \n"
             "    msr psplim, r4                               \n"
             "    msr control, r5                              \n"
-            "    ldr r4, xSecureContextConst2                 \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "    ldr r4, =xSecureContext                      \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
             "    str r0, [r4]                                 \n" /* Restore xSecureContext. */
             "                                                 \n"
             " restore_general_regs_first_task:                \n"
@@ -115,14 +115,6 @@
             "    mov r0, #0                                   \n"
             "    msr basepri, r0                              \n" /* Ensure that interrupts are enabled when the first task starts. */
             "    bx lr                                        \n"
-            "                                                 \n"
-            " .align 4                                        \n"
-            " pxCurrentTCBConst2: .word pxCurrentTCB          \n"
-            " xSecureContextConst2: .word xSecureContext      \n"
-            " xMPUCTRLConst2: .word 0xe000ed94                \n"
-            " xMAIR0Const2: .word 0xe000edc0                  \n"
-            " xRNRConst2: .word 0xe000ed98                    \n"
-            " xRBARConst2: .word 0xe000ed9c                   \n"
         );
     }
 
@@ -134,12 +126,12 @@
         (
             "   .syntax unified                                 \n"
             "                                                   \n"
-            "   ldr  r2, pxCurrentTCBConst2                     \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr  r2, =pxCurrentTCB                          \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr  r3, [r2]                                   \n" /* Read pxCurrentTCB. */
             "   ldr  r0, [r3]                                   \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
             "                                                   \n"
             "   ldm  r0!, {r1-r3}                               \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
-            "   ldr  r4, xSecureContextConst2                   \n"
+            "   ldr  r4, =xSecureContext                        \n"
             "   str  r1, [r4]                                   \n" /* Set xSecureContext to this task's value for the same. */
             "   msr  psplim, r2                                 \n" /* Set this task's PSPLIM value. */
             "   movs r1, #2                                     \n" /* r1 = 2. */
@@ -150,9 +142,6 @@
             "   mov  r0, #0                                     \n"
             "   msr  basepri, r0                                \n" /* Ensure that interrupts are enabled when the first task starts. */
             "   bx   r3                                         \n" /* Finally, branch to EXC_RETURN. */
-            "   .align 4                                        \n"
-            "pxCurrentTCBConst2: .word pxCurrentTCB             \n"
-            "xSecureContextConst2: .word xSecureContext         \n"
         );
     }
 
@@ -171,8 +160,6 @@ BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
         "   movne r0, #0                                    \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
         "   moveq r0, #1                                    \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
         "   bx lr                                           \n" /* Return. */
-        "                                                   \n"
-        "   .align 4                                        \n"
         ::: "r0", "memory"
     );
 }
@@ -214,7 +201,7 @@ void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   ldr r0, xVTORConst                              \n" /* Use the NVIC offset register to locate the stack. */
+        "   ldr r0, =0xe000ed08                             \n" /* Use the NVIC offset register to locate the stack. */
         "   ldr r0, [r0]                                    \n" /* Read the VTOR register which gives the address of vector table. */
         "   ldr r0, [r0]                                    \n" /* The first entry in vector table is stack pointer. */
         "   msr msp, r0                                     \n" /* Set the MSP back to the start of the stack. */
@@ -224,9 +211,6 @@ void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
         "   isb                                             \n"
         "   svc %0                                          \n" /* System call to start the first task. */
         "   nop                                             \n"
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "xVTORConst: .word 0xe000ed08                       \n"
         ::"i" ( portSVC_START_SCHEDULER ) : "memory"
     );
 }
@@ -274,9 +258,9 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             " .extern SecureContext_SaveContext               \n"
             " .extern SecureContext_LoadContext               \n"
             "                                                 \n"
-            " ldr r3, xSecureContextConst                     \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            " ldr r3, =xSecureContext                         \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
             " ldr r0, [r3]                                    \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
-            " ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            " ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             " ldr r1, [r3]                                    \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
             " ldr r2, [r1]                                    \n" /* r2 = Location in TCB where the context should be saved. */
             "                                                 \n"
@@ -325,23 +309,23 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    msr basepri, r0                              \n" /* Enable interrupts. */
             "                                                 \n"
             " program_mpu:                                    \n"
-            "    ldr r3, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r3, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB.*/
             "                                                 \n"
             "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-            "    ldr r1, xMPUCTRLConst                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
             "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
             "    str r2, [r1]                                 \n" /* Disable MPU. */
             "                                                 \n"
             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
             "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-            "    ldr r2, xMAIR0Const                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    ldr r2, =0xe000edc0                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
             "    str r1, [r2]                                 \n" /* Program MAIR0. */
             "                                                 \n"
             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-            "    ldr r1, xRNRConst                            \n" /* r1 = 0xe000ed98 [Location of RNR]. */
-            "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    ldr r1, =0xe000ed98                          \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
             "                                                 \n"
             "    movs r3, #4                                  \n" /* r3 = 4. */
             "    str r3, [r1]                                 \n" /* Program RNR = 4. */
@@ -359,14 +343,14 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
                 "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
             #endif /* configTOTAL_MPU_REGIONS == 16 */
             "                                                 \n"
-            "   ldr r1, xMPUCTRLConst                         \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "   ldr r1, =0xe000ed94                           \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
             "   orr r2, #1                                    \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
             "   str r2, [r1]                                  \n" /* Enable MPU. */
             "   dsb                                           \n" /* Force memory writes before continuing. */
             "                                                 \n"
             " restore_context:                                \n"
-            "    ldr r3, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r3, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "    ldr r1, [r3]                                 \n" /* r1 = pxCurrentTCB.*/
             "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
             "                                                 \n"
@@ -375,7 +359,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    msr psp, r3                                  \n"
             "    msr psplim, r4                               \n"
             "    msr control, r5                              \n"
-            "    ldr r4, xSecureContextConst                  \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "    ldr r4, =xSecureContext                      \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
             "    str r0, [r4]                                 \n" /* Restore xSecureContext. */
             "    cbz r0, restore_ns_context                   \n" /* No secure context to restore. */
             "                                                 \n"
@@ -404,14 +388,6 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             " restore_context_done:                           \n"
             "    str r2, [r1]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
             "    bx lr                                        \n"
-            "                                                 \n"
-            " .align 4                                        \n"
-            " pxCurrentTCBConst: .word pxCurrentTCB           \n"
-            " xSecureContextConst: .word xSecureContext       \n"
-            " xMPUCTRLConst: .word 0xe000ed94                 \n"
-            " xMAIR0Const: .word 0xe000edc0                   \n"
-            " xRNRConst: .word 0xe000ed98                     \n"
-            " xRBARConst: .word 0xe000ed9c                    \n"
             ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
         );
     }
@@ -426,9 +402,9 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   .extern SecureContext_SaveContext               \n"
             "   .extern SecureContext_LoadContext               \n"
             "                                                   \n"
-            "   ldr r3, xSecureContextConst                     \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "   ldr r3, =xSecureContext                         \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
             "   ldr r0, [r3]                                    \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
-            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
             "   mrs r2, psp                                     \n" /* Read PSP in r2. */
             "                                                   \n"
@@ -440,7 +416,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   lsls r1, r3, #25                                \n" /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
             "   bpl save_ns_context                             \n" /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
             "                                                   \n"
-            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB.*/
             "   subs r2, r2, #12                                \n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */
             "   str r2, [r1]                                    \n" /* Save the new top of stack in TCB. */
@@ -450,7 +426,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   b select_next_task                              \n"
             "                                                   \n"
             " save_ns_context:                                  \n"
-            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
                 "   tst lr, #0x10                               \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
@@ -475,17 +451,17 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   mov r0, #0                                      \n" /* r0 = 0. */
             "   msr basepri, r0                                 \n" /* Enable interrupts. */
             "                                                   \n"
-            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
             "   ldr r2, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
             "                                                   \n"
             "   ldmia r2!, {r0, r1, r4}                         \n" /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
             "   msr psplim, r1                                  \n" /* Restore the PSPLIM register value for the task. */
             "   mov lr, r4                                      \n" /* LR = r4. */
-            "   ldr r3, xSecureContextConst                     \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "   ldr r3, =xSecureContext                         \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
             "   str r0, [r3]                                    \n" /* Restore the task's xSecureContext. */
             "   cbz r0, restore_ns_context                      \n" /* If there is no secure context for the task, restore the non-secure context. */
-            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
             "   push {r2, r4}                                   \n"
             "   bl SecureContext_LoadContext                    \n" /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
@@ -505,10 +481,6 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             #endif /* configENABLE_FPU || configENABLE_MVE */
             "   msr psp, r2                                     \n" /* Remember the new top of stack for the task. */
             "   bx lr                                           \n"
-            "                                                   \n"
-            "   .align 4                                        \n"
-            "pxCurrentTCBConst: .word pxCurrentTCB              \n"
-            "xSecureContextConst: .word xSecureContext          \n"
             ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
         );
     }
@@ -566,11 +538,8 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   ite eq                                          \n"
             "   mrseq r0, msp                                   \n"
             "   mrsne r0, psp                                   \n"
-            "   ldr r1, svchandler_address_const                \n"
+            "   ldr r1, =vPortSVCHandler_C                      \n"
             "   bx r1                                           \n"
-            "                                                   \n"
-            "   .align 4                                        \n"
-            "svchandler_address_const: .word vPortSVCHandler_C  \n"
         );
     }
 
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c
index 56866d6b6..cdb2632c5 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c
@@ -52,23 +52,23 @@
             " .syntax unified                                 \n"
             "                                                 \n"
             " program_mpu_first_task:                         \n"
-            "    ldr r2, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r2, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB. */
             "                                                 \n"
             "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-            "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
             "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
             "    str r2, [r1]                                 \n" /* Disable MPU. */
             "                                                 \n"
             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
             "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-            "    ldr r2, xMAIR0Const2                         \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    ldr r2, =0xe000edc0                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
             "    str r1, [r2]                                 \n" /* Program MAIR0. */
             "                                                 \n"
             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-            "    ldr r1, xRNRConst2                           \n" /* r1 = 0xe000ed98 [Location of RNR]. */
-            "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    ldr r1, =0xe000ed98                          \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
             "                                                 \n"
             "    movs r3, #4                                  \n" /* r3 = 4. */
             "    str r3, [r1]                                 \n" /* Program RNR = 4. */
@@ -86,14 +86,14 @@
                 "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
             #endif /* configTOTAL_MPU_REGIONS == 16 */
             "                                                 \n"
-            "   ldr r1, xMPUCTRLConst2                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "   ldr r1, =0xe000ed94                           \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
             "   orr r2, #1                                    \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
             "   str r2, [r1]                                  \n" /* Enable MPU. */
             "   dsb                                           \n" /* Force memory writes before continuing. */
             "                                                 \n"
             " restore_context_first_task:                     \n"
-            "    ldr r2, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r2, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB.*/
             "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
             "                                                 \n"
@@ -113,13 +113,6 @@
             "    mov r0, #0                                   \n"
             "    msr basepri, r0                              \n" /* Ensure that interrupts are enabled when the first task starts. */
             "    bx lr                                        \n"
-            "                                                 \n"
-            " .align 4                                        \n"
-            " pxCurrentTCBConst2: .word pxCurrentTCB          \n"
-            " xMPUCTRLConst2: .word 0xe000ed94                \n"
-            " xMAIR0Const2: .word 0xe000edc0                  \n"
-            " xRNRConst2: .word 0xe000ed98                    \n"
-            " xRBARConst2: .word 0xe000ed9c                   \n"
         );
     }
 
@@ -131,7 +124,7 @@
         (
             "   .syntax unified                                 \n"
             "                                                   \n"
-            "   ldr  r2, pxCurrentTCBConst2                     \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr  r2, =pxCurrentTCB                          \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr  r1, [r2]                                   \n" /* Read pxCurrentTCB. */
             "   ldr  r0, [r1]                                   \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
             "                                                   \n"
@@ -145,9 +138,6 @@
             "   mov  r0, #0                                     \n"
             "   msr  basepri, r0                                \n" /* Ensure that interrupts are enabled when the first task starts. */
             "   bx   r2                                         \n" /* Finally, branch to EXC_RETURN. */
-            "                                                   \n"
-            "   .align 4                                        \n"
-            "pxCurrentTCBConst2: .word pxCurrentTCB             \n"
         );
     }
 
@@ -166,8 +156,6 @@ BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
         "   movne r0, #0                                    \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
         "   moveq r0, #1                                    \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
         "   bx lr                                           \n" /* Return. */
-        "                                                   \n"
-        "   .align 4                                        \n"
         ::: "r0", "memory"
     );
 }
@@ -209,7 +197,7 @@ void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   ldr r0, xVTORConst                              \n" /* Use the NVIC offset register to locate the stack. */
+        "   ldr r0, =0xe000ed08                             \n" /* Use the NVIC offset register to locate the stack. */
         "   ldr r0, [r0]                                    \n" /* Read the VTOR register which gives the address of vector table. */
         "   ldr r0, [r0]                                    \n" /* The first entry in vector table is stack pointer. */
         "   msr msp, r0                                     \n" /* Set the MSP back to the start of the stack. */
@@ -219,9 +207,6 @@ void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
         "   isb                                             \n"
         "   svc %0                                          \n" /* System call to start the first task. */
         "   nop                                             \n"
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "xVTORConst: .word 0xe000ed08                       \n"
         ::"i" ( portSVC_START_SCHEDULER ) : "memory"
     );
 }
@@ -267,7 +252,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
         (
             " .syntax unified                                 \n"
             "                                                 \n"
-            " ldr r2, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            " ldr r2, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             " ldr r0, [r2]                                    \n" /* r0 = pxCurrentTCB. */
             " ldr r1, [r0]                                    \n" /* r1 = Location in TCB where the context should be saved. */
             " mrs r2, psp                                     \n" /* r2 = PSP. */
@@ -303,23 +288,23 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    msr basepri, r0                              \n" /* Enable interrupts. */
             "                                                 \n"
             " program_mpu:                                    \n"
-            "    ldr r2, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r2, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB. */
             "                                                 \n"
             "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-            "    ldr r1, xMPUCTRLConst                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
             "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
             "    str r2, [r1]                                 \n" /* Disable MPU. */
             "                                                 \n"
             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
             "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-            "    ldr r2, xMAIR0Const                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    ldr r2, =0xe000edc0                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
             "    str r1, [r2]                                 \n" /* Program MAIR0. */
             "                                                 \n"
             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-            "    ldr r1, xRNRConst                            \n" /* r1 = 0xe000ed98 [Location of RNR]. */
-            "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    ldr r1, =0xe000ed98                          \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
             "                                                 \n"
             "    movs r3, #4                                  \n" /* r3 = 4. */
             "    str r3, [r1]                                 \n" /* Program RNR = 4. */
@@ -337,14 +322,14 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
                 "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
             #endif /* configTOTAL_MPU_REGIONS == 16 */
             "                                                 \n"
-            "   ldr r1, xMPUCTRLConst                         \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "   ldr r1, =0xe000ed94                           \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
             "   orr r2, #1                                    \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
             "   str r2, [r1]                                  \n" /* Enable MPU. */
             "   dsb                                           \n" /* Force memory writes before continuing. */
             "                                                 \n"
             " restore_context:                                \n"
-            "    ldr r2, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r2, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB.*/
             "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
             "                                                 \n"
@@ -369,13 +354,6 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             " restore_context_done:                           \n"
             "    str r1, [r0]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
             "    bx lr                                        \n"
-            "                                                 \n"
-            " .align 4                                        \n"
-            " pxCurrentTCBConst: .word pxCurrentTCB           \n"
-            " xMPUCTRLConst: .word 0xe000ed94                 \n"
-            " xMAIR0Const: .word 0xe000edc0                   \n"
-            " xRNRConst: .word 0xe000ed98                     \n"
-            " xRBARConst: .word 0xe000ed9c                    \n"
             ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
         );
     }
@@ -400,7 +378,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   mov r3, lr                                      \n" /* r3 = LR/EXC_RETURN. */
             "   stmdb r0!, {r2-r11}                             \n" /* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */
             "                                                   \n"
-            "   ldr r2, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r2, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr r1, [r2]                                    \n" /* Read pxCurrentTCB. */
             "   str r0, [r1]                                    \n" /* Save the new top of stack in TCB. */
             "                                                   \n"
@@ -412,7 +390,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   mov r0, #0                                      \n" /* r0 = 0. */
             "   msr basepri, r0                                 \n" /* Enable interrupts. */
             "                                                   \n"
-            "   ldr r2, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r2, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr r1, [r2]                                    \n" /* Read pxCurrentTCB. */
             "   ldr r0, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
             "                                                   \n"
@@ -427,9 +405,6 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   msr psplim, r2                                  \n" /* Restore the PSPLIM register value for the task. */
             "   msr psp, r0                                     \n" /* Remember the new top of stack for the task. */
             "   bx r3                                           \n"
-            "                                                   \n"
-            "   .align 4                                        \n"
-            "pxCurrentTCBConst: .word pxCurrentTCB              \n"
             ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
         );
     }
@@ -487,11 +462,8 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   ite eq                                          \n"
             "   mrseq r0, msp                                   \n"
             "   mrsne r0, psp                                   \n"
-            "   ldr r1, svchandler_address_const                \n"
+            "   ldr r1, =vPortSVCHandler_C                      \n"
             "   bx r1                                           \n"
-            "                                                   \n"
-            "   .align 4                                        \n"
-            "svchandler_address_const: .word vPortSVCHandler_C  \n"
         );
     }
 
diff --git a/portable/GCC/ARM_CM23/non_secure/portasm.c b/portable/GCC/ARM_CM23/non_secure/portasm.c
index 8df9bfa7c..978d35259 100644
--- a/portable/GCC/ARM_CM23/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM23/non_secure/portasm.c
@@ -56,11 +56,11 @@
             " .syntax unified                                 \n"
             "                                                 \n"
             " program_mpu_first_task:                         \n"
-            "    ldr r3, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r3, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB.*/
             "                                                 \n"
             "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-            "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
             "    movs r3, #1                                  \n" /* r3 = 1. */
             "    bics r2, r3                                  \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
@@ -68,34 +68,34 @@
             "                                                 \n"
             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
             "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-            "    ldr r2, xMAIR0Const2                         \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    ldr r2, =0xe000edc0                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
             "    str r1, [r2]                                 \n" /* Program MAIR0. */
             "                                                 \n"
             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-            "    ldr r1, xRNRConst2                           \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "    ldr r1, =0xe000ed98                          \n" /* r1 = 0xe000ed98 [Location of RNR]. */
             "                                                 \n"
             "    movs r3, #4                                  \n" /* r3 = 4. */
             "    str r3, [r1]                                 \n" /* Program RNR = 4. */
             "    ldmia r0!, {r4-r5}                           \n" /* Read first set of RBAR/RLAR registers from TCB. */
-            "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
             "    stmia r2!, {r4-r5}                           \n" /* Write first set of RBAR/RLAR registers. */
             "    movs r3, #5                                  \n" /* r3 = 5. */
             "    str r3, [r1]                                 \n" /* Program RNR = 5. */
             "    ldmia r0!, {r4-r5}                           \n" /* Read second set of RBAR/RLAR registers from TCB. */
-            "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
             "    stmia r2!, {r4-r5}                           \n" /* Write second set of RBAR/RLAR registers. */
             "    movs r3, #6                                  \n" /* r3 = 6. */
             "    str r3, [r1]                                 \n" /* Program RNR = 6. */
             "    ldmia r0!, {r4-r5}                           \n" /* Read third set of RBAR/RLAR registers from TCB. */
-            "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
             "    stmia r2!, {r4-r5}                           \n" /* Write third set of RBAR/RLAR registers. */
             "    movs r3, #7                                  \n" /* r3 = 6. */
             "    str r3, [r1]                                 \n" /* Program RNR = 7. */
             "    ldmia r0!, {r4-r5}                           \n" /* Read fourth set of RBAR/RLAR registers from TCB. */
-            "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
             "    stmia r2!, {r4-r5}                           \n" /* Write fourth set of RBAR/RLAR registers. */
             "                                                 \n"
-            "   ldr r1, xMPUCTRLConst2                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "   ldr r1, =0xe000ed94                           \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
             "   movs r3, #1                                   \n" /* r3 = 1. */
             "   orrs r2, r3                                   \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
@@ -103,7 +103,7 @@
             "   dsb                                           \n" /* Force memory writes before continuing. */
             "                                                 \n"
             " restore_context_first_task:                     \n"
-            "    ldr r3, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r3, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "    ldr r1, [r3]                                 \n" /* r1 = pxCurrentTCB.*/
             "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
             "                                                 \n"
@@ -114,7 +114,7 @@
             "    msr psp, r3                                  \n"
             "    msr control, r5                              \n"
             "    mov lr, r6                                   \n"
-            "    ldr r4, xSecureContextConst2                 \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "    ldr r4, =xSecureContext                      \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
             "    str r0, [r4]                                 \n" /* Restore xSecureContext. */
             "                                                 \n"
             " restore_general_regs_first_task:                \n"
@@ -136,14 +136,6 @@
             " restore_context_done_first_task:                \n"
             "    str r2, [r1]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
             "    bx lr                                        \n"
-            "                                                 \n"
-            " .align 4                                        \n"
-            " pxCurrentTCBConst2: .word pxCurrentTCB          \n"
-            " xSecureContextConst2: .word xSecureContext      \n"
-            " xMPUCTRLConst2: .word 0xe000ed94                \n"
-            " xMAIR0Const2: .word 0xe000edc0                  \n"
-            " xRNRConst2: .word 0xe000ed98                    \n"
-            " xRBARConst2: .word 0xe000ed9c                   \n"
         );
     }
 
@@ -155,12 +147,12 @@
         (
             "   .syntax unified                                 \n"
             "                                                   \n"
-            "   ldr  r2, pxCurrentTCBConst2                     \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr  r2, =pxCurrentTCB                          \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr  r3, [r2]                                   \n" /* Read pxCurrentTCB. */
             "   ldr  r0, [r3]                                   \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
             "                                                   \n"
             "   ldm  r0!, {r1-r3}                               \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
-            "   ldr  r4, xSecureContextConst2                   \n"
+            "   ldr  r4, =xSecureContext                        \n"
             "   str  r1, [r4]                                   \n" /* Set xSecureContext to this task's value for the same. */
             "   movs r1, #2                                     \n" /* r1 = 2. */
             "   msr  CONTROL, r1                                \n" /* Switch to use PSP in the thread mode. */
@@ -168,10 +160,6 @@
             "   msr  psp, r0                                    \n" /* This is now the new top of stack to use in the task. */
             "   isb                                             \n"
             "   bx   r3                                         \n" /* Finally, branch to EXC_RETURN. */
-            "                                                   \n"
-            "   .align 4                                        \n"
-            "pxCurrentTCBConst2: .word pxCurrentTCB             \n"
-            "xSecureContextConst2: .word xSecureContext         \n"
         );
     }
 
@@ -193,8 +181,6 @@ BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
         " running_privileged:                               \n"
         "   movs r0, #1                                     \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
         "   bx lr                                           \n" /* Return. */
-        "                                                   \n"
-        "   .align 4                                        \n"
         ::: "r0", "r1", "memory"
     );
 }
@@ -238,7 +224,7 @@ void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   ldr r0, xVTORConst                              \n" /* Use the NVIC offset register to locate the stack. */
+        "   ldr r0, =0xe000ed08                             \n" /* Use the NVIC offset register to locate the stack. */
         "   ldr r0, [r0]                                    \n" /* Read the VTOR register which gives the address of vector table. */
         "   ldr r0, [r0]                                    \n" /* The first entry in vector table is stack pointer. */
         "   msr msp, r0                                     \n" /* Set the MSP back to the start of the stack. */
@@ -247,9 +233,6 @@ void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
         "   isb                                             \n"
         "   svc %0                                          \n" /* System call to start the first task. */
         "   nop                                             \n"
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "xVTORConst: .word 0xe000ed08                       \n"
         ::"i" ( portSVC_START_SCHEDULER ) : "memory"
     );
 }
@@ -292,9 +275,9 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             " .extern SecureContext_SaveContext               \n"
             " .extern SecureContext_LoadContext               \n"
             "                                                 \n"
-            " ldr r3, xSecureContextConst                     \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            " ldr r3, =xSecureContext                         \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
             " ldr r0, [r3]                                    \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
-            " ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            " ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             " ldr r1, [r3]                                    \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later.*/
             " ldr r2, [r1]                                    \n" /* r2 = Location in TCB where the context should be saved. */
             "                                                 \n"
@@ -337,11 +320,11 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    cpsie i                                      \n"
             "                                                 \n"
             " program_mpu:                                    \n"
-            "    ldr r3, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r3, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB.*/
             "                                                 \n"
             "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-            "    ldr r1, xMPUCTRLConst                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
             "    movs r3, #1                                  \n" /* r3 = 1. */
             "    bics r2, r3                                  \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
@@ -349,34 +332,34 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "                                                 \n"
             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
             "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-            "    ldr r2, xMAIR0Const                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    ldr r2, =0xe000edc0                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
             "    str r1, [r2]                                 \n" /* Program MAIR0. */
             "                                                 \n"
             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-            "    ldr r1, xRNRConst                            \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "    ldr r1, =0xe000ed98                          \n" /* r1 = 0xe000ed98 [Location of RNR]. */
             "                                                 \n"
             "    movs r3, #4                                  \n" /* r3 = 4. */
             "    str r3, [r1]                                 \n" /* Program RNR = 4. */
             "    ldmia r0!, {r4-r5}                           \n" /* Read first set of RBAR/RLAR registers from TCB. */
-            "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
             "    stmia r2!, {r4-r5}                           \n" /* Write first set of RBAR/RLAR registers. */
             "    movs r3, #5                                  \n" /* r3 = 5. */
             "    str r3, [r1]                                 \n" /* Program RNR = 5. */
             "    ldmia r0!, {r4-r5}                           \n" /* Read second set of RBAR/RLAR registers from TCB. */
-            "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
             "    stmia r2!, {r4-r5}                           \n" /* Write second set of RBAR/RLAR registers. */
             "    movs r3, #6                                  \n" /* r3 = 6. */
             "    str r3, [r1]                                 \n" /* Program RNR = 6. */
             "    ldmia r0!, {r4-r5}                           \n" /* Read third set of RBAR/RLAR registers from TCB. */
-            "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
             "    stmia r2!, {r4-r5}                           \n" /* Write third set of RBAR/RLAR registers. */
             "    movs r3, #7                                  \n" /* r3 = 6. */
             "    str r3, [r1]                                 \n" /* Program RNR = 7. */
             "    ldmia r0!, {r4-r5}                           \n" /* Read fourth set of RBAR/RLAR registers from TCB. */
-            "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
             "    stmia r2!, {r4-r5}                           \n" /* Write fourth set of RBAR/RLAR registers. */
             "                                                 \n"
-            "    ldr r1, xMPUCTRLConst                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
             "    movs r3, #1                                  \n" /* r3 = 1. */
             "    orrs r2, r3                                  \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
@@ -384,7 +367,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    dsb                                          \n" /* Force memory writes before continuing. */
             "                                                 \n"
             " restore_context:                                \n"
-            "    ldr r3, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r3, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "    ldr r1, [r3]                                 \n" /* r1 = pxCurrentTCB.*/
             "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
             "                                                 \n"
@@ -395,7 +378,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    msr psp, r3                                  \n"
             "    msr control, r5                              \n"
             "    mov lr, r6                                   \n"
-            "    ldr r4, xSecureContextConst                  \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "    ldr r4, =xSecureContext                      \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
             "    str r0, [r4]                                 \n" /* Restore xSecureContext. */
             "    cbz r0, restore_ns_context                   \n" /* No secure context to restore. */
             "                                                 \n"
@@ -429,14 +412,6 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             " restore_context_done:                           \n"
             "    str r2, [r1]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
             "    bx lr                                        \n"
-            "                                                 \n"
-            " .align 4                                        \n"
-            " pxCurrentTCBConst: .word pxCurrentTCB           \n"
-            " xSecureContextConst: .word xSecureContext       \n"
-            " xMPUCTRLConst: .word 0xe000ed94                 \n"
-            " xMAIR0Const: .word 0xe000edc0                   \n"
-            " xRNRConst: .word 0xe000ed98                     \n"
-            " xRBARConst: .word 0xe000ed9c                    \n"
         );
     }
 
@@ -450,9 +425,9 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   .extern SecureContext_SaveContext               \n"
             "   .extern SecureContext_LoadContext               \n"
             "                                                   \n"
-            "   ldr r3, xSecureContextConst                     \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "   ldr r3, =xSecureContext                         \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
             "   ldr r0, [r3]                                    \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
-            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later.*/
             "   mrs r2, psp                                     \n" /* Read PSP in r2. */
             "                                                   \n"
@@ -463,7 +438,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   mov lr, r3                                      \n" /* LR = r3. */
             "   lsls r1, r3, #25                                \n" /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
             "   bpl save_ns_context                             \n" /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
             "   subs r2, r2, #12                                \n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */
             "   str r2, [r1]                                    \n" /* Save the new top of stack in TCB. */
@@ -473,7 +448,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   b select_next_task                              \n"
             "                                                   \n"
             " save_ns_context:                                  \n"
-            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
             "   subs r2, r2, #44                                \n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
             "   str r2, [r1]                                    \n" /* Save the new top of stack in TCB. */
@@ -491,16 +466,16 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   bl vTaskSwitchContext                           \n"
             "   cpsie i                                         \n"
             "                                                   \n"
-            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
             "   ldr r2, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
             "                                                   \n"
             "   ldmia r2!, {r0, r1, r4}                         \n" /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
             "   mov lr, r4                                      \n" /* LR = r4. */
-            "   ldr r3, xSecureContextConst                     \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "   ldr r3, =xSecureContext                         \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
             "   str r0, [r3]                                    \n" /* Restore the task's xSecureContext. */
             "   cbz r0, restore_ns_context                      \n" /* If there is no secure context for the task, restore the non-secure context. */
-            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
             "   push {r2, r4}                                   \n"
             "   bl SecureContext_LoadContext                    \n" /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
@@ -522,10 +497,6 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   subs r2, r2, #32                                \n" /* Go back to the low registers. */
             "   ldmia r2!, {r4-r7}                              \n" /* Restore the low registers that are not automatically restored. */
             "   bx lr                                           \n"
-            "                                                   \n"
-            "   .align 4                                        \n"
-            "pxCurrentTCBConst: .word pxCurrentTCB              \n"
-            "xSecureContextConst: .word xSecureContext          \n"
         );
     }
 
@@ -588,15 +559,12 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   tst r0, r1                                      \n"
             "   beq stacking_used_msp                           \n"
             "   mrs r0, psp                                     \n"
-            "   ldr r2, svchandler_address_const                \n"
+            "   ldr r2, =vPortSVCHandler_C                      \n"
             "   bx r2                                           \n"
             " stacking_used_msp:                                \n"
             "   mrs r0, msp                                     \n"
-            "   ldr r2, svchandler_address_const                \n"
+            "   ldr r2, =vPortSVCHandler_C                      \n"
             "   bx r2                                           \n"
-            "                                                   \n"
-            "   .align 4                                        \n"
-            "svchandler_address_const: .word vPortSVCHandler_C  \n"
         );
     }
 
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c b/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c
index 82bff509e..d215f8f73 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c
@@ -56,11 +56,11 @@
             " .syntax unified                                 \n"
             "                                                 \n"
             " program_mpu_first_task:                         \n"
-            "    ldr r3, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r3, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB.*/
             "                                                 \n"
             "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-            "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
             "    movs r3, #1                                  \n" /* r3 = 1. */
             "    bics r2, r3                                  \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
@@ -68,34 +68,34 @@
             "                                                 \n"
             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
             "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-            "    ldr r2, xMAIR0Const2                         \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    ldr r2, =0xe000edc0                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
             "    str r1, [r2]                                 \n" /* Program MAIR0. */
             "                                                 \n"
             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-            "    ldr r1, xRNRConst2                           \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "    ldr r1, =0xe000ed98                          \n" /* r1 = 0xe000ed98 [Location of RNR]. */
             "                                                 \n"
             "    movs r3, #4                                  \n" /* r3 = 4. */
             "    str r3, [r1]                                 \n" /* Program RNR = 4. */
             "    ldmia r0!, {r4-r5}                           \n" /* Read first set of RBAR/RLAR registers from TCB. */
-            "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
             "    stmia r2!, {r4-r5}                           \n" /* Write first set of RBAR/RLAR registers. */
             "    movs r3, #5                                  \n" /* r3 = 5. */
             "    str r3, [r1]                                 \n" /* Program RNR = 5. */
             "    ldmia r0!, {r4-r5}                           \n" /* Read second set of RBAR/RLAR registers from TCB. */
-            "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
             "    stmia r2!, {r4-r5}                           \n" /* Write second set of RBAR/RLAR registers. */
             "    movs r3, #6                                  \n" /* r3 = 6. */
             "    str r3, [r1]                                 \n" /* Program RNR = 6. */
             "    ldmia r0!, {r4-r5}                           \n" /* Read third set of RBAR/RLAR registers from TCB. */
-            "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
             "    stmia r2!, {r4-r5}                           \n" /* Write third set of RBAR/RLAR registers. */
             "    movs r3, #7                                  \n" /* r3 = 6. */
             "    str r3, [r1]                                 \n" /* Program RNR = 7. */
             "    ldmia r0!, {r4-r5}                           \n" /* Read fourth set of RBAR/RLAR registers from TCB. */
-            "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
             "    stmia r2!, {r4-r5}                           \n" /* Write fourth set of RBAR/RLAR registers. */
             "                                                 \n"
-            "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
             "    movs r3, #1                                  \n" /* r3 = 1. */
             "    orrs r2, r3                                  \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
@@ -103,7 +103,7 @@
             "    dsb                                          \n" /* Force memory writes before continuing. */
             "                                                 \n"
             " restore_context_first_task:                     \n"
-            "    ldr r2, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r2, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB.*/
             "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
             "                                                 \n"
@@ -137,13 +137,6 @@
             " restore_context_done_first_task:                \n"
             "    str r1, [r0]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
             "    bx lr                                        \n"
-            "                                                 \n"
-            " .align 4                                        \n"
-            " pxCurrentTCBConst2: .word pxCurrentTCB          \n"
-            " xMPUCTRLConst2: .word 0xe000ed94                \n"
-            " xMAIR0Const2: .word 0xe000edc0                  \n"
-            " xRNRConst2: .word 0xe000ed98                    \n"
-            " xRBARConst2: .word 0xe000ed9c                   \n"
         );
     }
 
@@ -155,7 +148,7 @@
         (
             "   .syntax unified                                 \n"
             "                                                   \n"
-            "   ldr  r2, pxCurrentTCBConst2                     \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr  r2, =pxCurrentTCB                          \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr  r1, [r2]                                   \n" /* Read pxCurrentTCB. */
             "   ldr  r0, [r1]                                   \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
             "                                                   \n"
@@ -169,9 +162,6 @@
             "   msr  psp, r0                                    \n" /* This is now the new top of stack to use in the task. */
             "   isb                                             \n"
             "   bx   r2                                         \n" /* Finally, branch to EXC_RETURN. */
-            "                                                   \n"
-            "   .align 4                                        \n"
-            "pxCurrentTCBConst2: .word pxCurrentTCB             \n"
         );
     }
 
@@ -193,8 +183,6 @@ BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
         " running_privileged:                               \n"
         "   movs r0, #1                                     \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
         "   bx lr                                           \n" /* Return. */
-        "                                                   \n"
-        "   .align 4                                        \n"
         ::: "r0", "r1", "memory"
     );
 }
@@ -238,7 +226,7 @@ void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   ldr r0, xVTORConst                              \n" /* Use the NVIC offset register to locate the stack. */
+        "   ldr r0, =0xe000ed08                             \n" /* Use the NVIC offset register to locate the stack. */
         "   ldr r0, [r0]                                    \n" /* Read the VTOR register which gives the address of vector table. */
         "   ldr r0, [r0]                                    \n" /* The first entry in vector table is stack pointer. */
         "   msr msp, r0                                     \n" /* Set the MSP back to the start of the stack. */
@@ -247,9 +235,6 @@ void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
         "   isb                                             \n"
         "   svc %0                                          \n" /* System call to start the first task. */
         "   nop                                             \n"
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "xVTORConst: .word 0xe000ed08                       \n"
         ::"i" ( portSVC_START_SCHEDULER ) : "memory"
     );
 }
@@ -290,7 +275,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
         (
             " .syntax unified                                 \n"
             "                                                 \n"
-            " ldr r2, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            " ldr r2, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             " ldr r0, [r2]                                    \n" /* r0 = pxCurrentTCB. */
             " ldr r1, [r0]                                    \n" /* r1 = Location in TCB where the context should be saved. */
             " mrs r2, psp                                     \n" /* r2 = PSP. */
@@ -325,11 +310,11 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    cpsie i                                      \n"
             "                                                 \n"
             " program_mpu:                                    \n"
-            "    ldr r3, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r3, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB.*/
             "                                                 \n"
             "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-            "    ldr r1, xMPUCTRLConst                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
             "    movs r3, #1                                  \n" /* r3 = 1. */
             "    bics r2, r3                                  \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
@@ -337,34 +322,34 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "                                                 \n"
             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
             "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-            "    ldr r2, xMAIR0Const                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    ldr r2, =0xe000edc0                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
             "    str r1, [r2]                                 \n" /* Program MAIR0. */
             "                                                 \n"
             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-            "    ldr r1, xRNRConst                            \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "    ldr r1, =0xe000ed98                          \n" /* r1 = 0xe000ed98 [Location of RNR]. */
             "                                                 \n"
             "    movs r3, #4                                  \n" /* r3 = 4. */
             "    str r3, [r1]                                 \n" /* Program RNR = 4. */
             "    ldmia r0!, {r4-r5}                           \n" /* Read first set of RBAR/RLAR registers from TCB. */
-            "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
             "    stmia r2!, {r4-r5}                           \n" /* Write first set of RBAR/RLAR registers. */
             "    movs r3, #5                                  \n" /* r3 = 5. */
             "    str r3, [r1]                                 \n" /* Program RNR = 5. */
             "    ldmia r0!, {r4-r5}                           \n" /* Read second set of RBAR/RLAR registers from TCB. */
-            "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
             "    stmia r2!, {r4-r5}                           \n" /* Write second set of RBAR/RLAR registers. */
             "    movs r3, #6                                  \n" /* r3 = 6. */
             "    str r3, [r1]                                 \n" /* Program RNR = 6. */
             "    ldmia r0!, {r4-r5}                           \n" /* Read third set of RBAR/RLAR registers from TCB. */
-            "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
             "    stmia r2!, {r4-r5}                           \n" /* Write third set of RBAR/RLAR registers. */
             "    movs r3, #7                                  \n" /* r3 = 6. */
             "    str r3, [r1]                                 \n" /* Program RNR = 7. */
             "    ldmia r0!, {r4-r5}                           \n" /* Read fourth set of RBAR/RLAR registers from TCB. */
-            "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
             "    stmia r2!, {r4-r5}                           \n" /* Write fourth set of RBAR/RLAR registers. */
             "                                                 \n"
-            "    ldr r1, xMPUCTRLConst                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
             "    movs r3, #1                                  \n" /* r3 = 1. */
             "    orrs r2, r3                                  \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
@@ -372,7 +357,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    dsb                                          \n" /* Force memory writes before continuing. */
             "                                                 \n"
             " restore_context:                                \n"
-            "    ldr r2, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r2, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB.*/
             "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
             "                                                 \n"
@@ -406,13 +391,6 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             " restore_context_done:                           \n"
             "    str r1, [r0]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
             "    bx lr                                        \n"
-            "                                                 \n"
-            " .align 4                                        \n"
-            " pxCurrentTCBConst: .word pxCurrentTCB           \n"
-            " xMPUCTRLConst: .word 0xe000ed94                 \n"
-            " xMAIR0Const: .word 0xe000edc0                   \n"
-            " xRNRConst: .word 0xe000ed98                     \n"
-            " xRBARConst: .word 0xe000ed9c                    \n"
         );
     }
 
@@ -425,7 +403,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   .syntax unified                                 \n"
             "                                                   \n"
             "   mrs r0, psp                                     \n" /* Read PSP in r0. */
-            "   ldr r2, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r2, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr r1, [r2]                                    \n" /* Read pxCurrentTCB. */
             "   subs r0, r0, #40                                \n" /* Make space for PSPLIM, LR and the remaining registers on the stack. */
             "   str r0, [r1]                                    \n" /* Save the new top of stack in TCB. */
@@ -446,7 +424,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   bl vTaskSwitchContext                           \n"
             "   cpsie i                                         \n"
             "                                                   \n"
-            "   ldr r2, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r2, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr r1, [r2]                                    \n" /* Read pxCurrentTCB. */
             "   ldr r0, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
             "                                                   \n"
@@ -463,9 +441,6 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
                 "   msr psplim, r2                              \n" /* Restore the PSPLIM register value for the task. */
             #endif
             "   bx r3                                           \n"
-            "                                                   \n"
-            "   .align 4                                        \n"
-            "pxCurrentTCBConst: .word pxCurrentTCB              \n"
         );
     }
 
@@ -528,15 +503,12 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   tst r0, r1                                      \n"
             "   beq stacking_used_msp                           \n"
             "   mrs r0, psp                                     \n"
-            "   ldr r2, svchandler_address_const                \n"
+            "   ldr r2, =vPortSVCHandler_C                      \n"
             "   bx r2                                           \n"
             " stacking_used_msp:                                \n"
             "   mrs r0, msp                                     \n"
-            "   ldr r2, svchandler_address_const                \n"
+            "   ldr r2, =vPortSVCHandler_C                      \n"
             "   bx r2                                           \n"
-            "                                                   \n"
-            "   .align 4                                        \n"
-            "svchandler_address_const: .word vPortSVCHandler_C  \n"
         );
     }
 
diff --git a/portable/GCC/ARM_CM33/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM33/non_secure/mpu_wrappers_v2_asm.c
index 6642c9e20..02229d964 100644
--- a/portable/GCC/ARM_CM33/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM33/non_secure/mpu_wrappers_v2_asm.c
@@ -1720,6 +1720,7 @@
         }
 
     #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
+
 /*-----------------------------------------------------------*/
 
     #if ( configUSE_EVENT_GROUPS == 1 )
diff --git a/portable/GCC/ARM_CM33/non_secure/portasm.c b/portable/GCC/ARM_CM33/non_secure/portasm.c
index 1ee04b76d..aa9379fdf 100644
--- a/portable/GCC/ARM_CM33/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM33/non_secure/portasm.c
@@ -52,23 +52,23 @@
             " .syntax unified                                 \n"
             "                                                 \n"
             " program_mpu_first_task:                         \n"
-            "    ldr r3, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r3, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB. */
             "                                                 \n"
             "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-            "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
             "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
             "    str r2, [r1]                                 \n" /* Disable MPU. */
             "                                                 \n"
             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
             "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-            "    ldr r2, xMAIR0Const2                         \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    ldr r2, =0xe000edc0                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
             "    str r1, [r2]                                 \n" /* Program MAIR0. */
             "                                                 \n"
             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-            "    ldr r1, xRNRConst2                           \n" /* r1 = 0xe000ed98 [Location of RNR]. */
-            "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    ldr r1, =0xe000ed98                          \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
             "                                                 \n"
             "    movs r3, #4                                  \n" /* r3 = 4. */
             "    str r3, [r1]                                 \n" /* Program RNR = 4. */
@@ -86,14 +86,14 @@
                 "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
             #endif /* configTOTAL_MPU_REGIONS == 16 */
             "                                                 \n"
-            "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
             "    orr r2, #1                                   \n" /* r2 = r1 | 1 i.e. Set the bit 0 in r2. */
             "    str r2, [r1]                                 \n" /* Enable MPU. */
             "    dsb                                          \n" /* Force memory writes before continuing. */
             "                                                 \n"
             " restore_context_first_task:                     \n"
-            "    ldr r3, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r3, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "    ldr r1, [r3]                                 \n" /* r1 = pxCurrentTCB.*/
             "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
             "                                                 \n"
@@ -102,7 +102,7 @@
             "    msr psp, r3                                  \n"
             "    msr psplim, r4                               \n"
             "    msr control, r5                              \n"
-            "    ldr r4, xSecureContextConst2                 \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "    ldr r4, =xSecureContext                      \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
             "    str r0, [r4]                                 \n" /* Restore xSecureContext. */
             "                                                 \n"
             " restore_general_regs_first_task:                \n"
@@ -115,14 +115,6 @@
             "    mov r0, #0                                   \n"
             "    msr basepri, r0                              \n" /* Ensure that interrupts are enabled when the first task starts. */
             "    bx lr                                        \n"
-            "                                                 \n"
-            " .align 4                                        \n"
-            " pxCurrentTCBConst2: .word pxCurrentTCB          \n"
-            " xSecureContextConst2: .word xSecureContext      \n"
-            " xMPUCTRLConst2: .word 0xe000ed94                \n"
-            " xMAIR0Const2: .word 0xe000edc0                  \n"
-            " xRNRConst2: .word 0xe000ed98                    \n"
-            " xRBARConst2: .word 0xe000ed9c                   \n"
         );
     }
 
@@ -134,12 +126,12 @@
         (
             "   .syntax unified                                 \n"
             "                                                   \n"
-            "   ldr  r2, pxCurrentTCBConst2                     \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr  r2, =pxCurrentTCB                          \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr  r3, [r2]                                   \n" /* Read pxCurrentTCB. */
             "   ldr  r0, [r3]                                   \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
             "                                                   \n"
             "   ldm  r0!, {r1-r3}                               \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
-            "   ldr  r4, xSecureContextConst2                   \n"
+            "   ldr  r4, =xSecureContext                        \n"
             "   str  r1, [r4]                                   \n" /* Set xSecureContext to this task's value for the same. */
             "   msr  psplim, r2                                 \n" /* Set this task's PSPLIM value. */
             "   movs r1, #2                                     \n" /* r1 = 2. */
@@ -150,9 +142,6 @@
             "   mov  r0, #0                                     \n"
             "   msr  basepri, r0                                \n" /* Ensure that interrupts are enabled when the first task starts. */
             "   bx   r3                                         \n" /* Finally, branch to EXC_RETURN. */
-            "   .align 4                                        \n"
-            "pxCurrentTCBConst2: .word pxCurrentTCB             \n"
-            "xSecureContextConst2: .word xSecureContext         \n"
         );
     }
 
@@ -171,8 +160,6 @@ BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
         "   movne r0, #0                                    \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
         "   moveq r0, #1                                    \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
         "   bx lr                                           \n" /* Return. */
-        "                                                   \n"
-        "   .align 4                                        \n"
         ::: "r0", "memory"
     );
 }
@@ -214,7 +201,7 @@ void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   ldr r0, xVTORConst                              \n" /* Use the NVIC offset register to locate the stack. */
+        "   ldr r0, =0xe000ed08                             \n" /* Use the NVIC offset register to locate the stack. */
         "   ldr r0, [r0]                                    \n" /* Read the VTOR register which gives the address of vector table. */
         "   ldr r0, [r0]                                    \n" /* The first entry in vector table is stack pointer. */
         "   msr msp, r0                                     \n" /* Set the MSP back to the start of the stack. */
@@ -224,9 +211,6 @@ void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
         "   isb                                             \n"
         "   svc %0                                          \n" /* System call to start the first task. */
         "   nop                                             \n"
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "xVTORConst: .word 0xe000ed08                       \n"
         ::"i" ( portSVC_START_SCHEDULER ) : "memory"
     );
 }
@@ -274,9 +258,9 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             " .extern SecureContext_SaveContext               \n"
             " .extern SecureContext_LoadContext               \n"
             "                                                 \n"
-            " ldr r3, xSecureContextConst                     \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            " ldr r3, =xSecureContext                         \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
             " ldr r0, [r3]                                    \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
-            " ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            " ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             " ldr r1, [r3]                                    \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
             " ldr r2, [r1]                                    \n" /* r2 = Location in TCB where the context should be saved. */
             "                                                 \n"
@@ -325,23 +309,23 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    msr basepri, r0                              \n" /* Enable interrupts. */
             "                                                 \n"
             " program_mpu:                                    \n"
-            "    ldr r3, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r3, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB.*/
             "                                                 \n"
             "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-            "    ldr r1, xMPUCTRLConst                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
             "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
             "    str r2, [r1]                                 \n" /* Disable MPU. */
             "                                                 \n"
             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
             "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-            "    ldr r2, xMAIR0Const                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    ldr r2, =0xe000edc0                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
             "    str r1, [r2]                                 \n" /* Program MAIR0. */
             "                                                 \n"
             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-            "    ldr r1, xRNRConst                            \n" /* r1 = 0xe000ed98 [Location of RNR]. */
-            "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    ldr r1, =0xe000ed98                          \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
             "                                                 \n"
             "    movs r3, #4                                  \n" /* r3 = 4. */
             "    str r3, [r1]                                 \n" /* Program RNR = 4. */
@@ -359,14 +343,14 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
                 "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
             #endif /* configTOTAL_MPU_REGIONS == 16 */
             "                                                 \n"
-            "   ldr r1, xMPUCTRLConst                         \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "   ldr r1, =0xe000ed94                           \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
             "   orr r2, #1                                    \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
             "   str r2, [r1]                                  \n" /* Enable MPU. */
             "   dsb                                           \n" /* Force memory writes before continuing. */
             "                                                 \n"
             " restore_context:                                \n"
-            "    ldr r3, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r3, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "    ldr r1, [r3]                                 \n" /* r1 = pxCurrentTCB.*/
             "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
             "                                                 \n"
@@ -375,7 +359,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    msr psp, r3                                  \n"
             "    msr psplim, r4                               \n"
             "    msr control, r5                              \n"
-            "    ldr r4, xSecureContextConst                  \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "    ldr r4, =xSecureContext                      \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
             "    str r0, [r4]                                 \n" /* Restore xSecureContext. */
             "    cbz r0, restore_ns_context                   \n" /* No secure context to restore. */
             "                                                 \n"
@@ -404,14 +388,6 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             " restore_context_done:                           \n"
             "    str r2, [r1]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
             "    bx lr                                        \n"
-            "                                                 \n"
-            " .align 4                                        \n"
-            " pxCurrentTCBConst: .word pxCurrentTCB           \n"
-            " xSecureContextConst: .word xSecureContext       \n"
-            " xMPUCTRLConst: .word 0xe000ed94                 \n"
-            " xMAIR0Const: .word 0xe000edc0                   \n"
-            " xRNRConst: .word 0xe000ed98                     \n"
-            " xRBARConst: .word 0xe000ed9c                    \n"
             ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
         );
     }
@@ -426,9 +402,9 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   .extern SecureContext_SaveContext               \n"
             "   .extern SecureContext_LoadContext               \n"
             "                                                   \n"
-            "   ldr r3, xSecureContextConst                     \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "   ldr r3, =xSecureContext                         \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
             "   ldr r0, [r3]                                    \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
-            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
             "   mrs r2, psp                                     \n" /* Read PSP in r2. */
             "                                                   \n"
@@ -440,7 +416,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   lsls r1, r3, #25                                \n" /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
             "   bpl save_ns_context                             \n" /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
             "                                                   \n"
-            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB.*/
             "   subs r2, r2, #12                                \n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */
             "   str r2, [r1]                                    \n" /* Save the new top of stack in TCB. */
@@ -450,7 +426,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   b select_next_task                              \n"
             "                                                   \n"
             " save_ns_context:                                  \n"
-            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
                 "   tst lr, #0x10                               \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
@@ -475,17 +451,17 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   mov r0, #0                                      \n" /* r0 = 0. */
             "   msr basepri, r0                                 \n" /* Enable interrupts. */
             "                                                   \n"
-            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
             "   ldr r2, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
             "                                                   \n"
             "   ldmia r2!, {r0, r1, r4}                         \n" /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
             "   msr psplim, r1                                  \n" /* Restore the PSPLIM register value for the task. */
             "   mov lr, r4                                      \n" /* LR = r4. */
-            "   ldr r3, xSecureContextConst                     \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "   ldr r3, =xSecureContext                         \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
             "   str r0, [r3]                                    \n" /* Restore the task's xSecureContext. */
             "   cbz r0, restore_ns_context                      \n" /* If there is no secure context for the task, restore the non-secure context. */
-            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
             "   push {r2, r4}                                   \n"
             "   bl SecureContext_LoadContext                    \n" /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
@@ -505,10 +481,6 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             #endif /* configENABLE_FPU || configENABLE_MVE */
             "   msr psp, r2                                     \n" /* Remember the new top of stack for the task. */
             "   bx lr                                           \n"
-            "                                                   \n"
-            "   .align 4                                        \n"
-            "pxCurrentTCBConst: .word pxCurrentTCB              \n"
-            "xSecureContextConst: .word xSecureContext          \n"
             ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
         );
     }
@@ -566,11 +538,8 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   ite eq                                          \n"
             "   mrseq r0, msp                                   \n"
             "   mrsne r0, psp                                   \n"
-            "   ldr r1, svchandler_address_const                \n"
+            "   ldr r1, =vPortSVCHandler_C                      \n"
             "   bx r1                                           \n"
-            "                                                   \n"
-            "   .align 4                                        \n"
-            "svchandler_address_const: .word vPortSVCHandler_C  \n"
         );
     }
 
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c b/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c
index 56866d6b6..cdb2632c5 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c
@@ -52,23 +52,23 @@
             " .syntax unified                                 \n"
             "                                                 \n"
             " program_mpu_first_task:                         \n"
-            "    ldr r2, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r2, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB. */
             "                                                 \n"
             "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-            "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
             "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
             "    str r2, [r1]                                 \n" /* Disable MPU. */
             "                                                 \n"
             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
             "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-            "    ldr r2, xMAIR0Const2                         \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    ldr r2, =0xe000edc0                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
             "    str r1, [r2]                                 \n" /* Program MAIR0. */
             "                                                 \n"
             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-            "    ldr r1, xRNRConst2                           \n" /* r1 = 0xe000ed98 [Location of RNR]. */
-            "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    ldr r1, =0xe000ed98                          \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
             "                                                 \n"
             "    movs r3, #4                                  \n" /* r3 = 4. */
             "    str r3, [r1]                                 \n" /* Program RNR = 4. */
@@ -86,14 +86,14 @@
                 "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
             #endif /* configTOTAL_MPU_REGIONS == 16 */
             "                                                 \n"
-            "   ldr r1, xMPUCTRLConst2                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "   ldr r1, =0xe000ed94                           \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
             "   orr r2, #1                                    \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
             "   str r2, [r1]                                  \n" /* Enable MPU. */
             "   dsb                                           \n" /* Force memory writes before continuing. */
             "                                                 \n"
             " restore_context_first_task:                     \n"
-            "    ldr r2, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r2, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB.*/
             "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
             "                                                 \n"
@@ -113,13 +113,6 @@
             "    mov r0, #0                                   \n"
             "    msr basepri, r0                              \n" /* Ensure that interrupts are enabled when the first task starts. */
             "    bx lr                                        \n"
-            "                                                 \n"
-            " .align 4                                        \n"
-            " pxCurrentTCBConst2: .word pxCurrentTCB          \n"
-            " xMPUCTRLConst2: .word 0xe000ed94                \n"
-            " xMAIR0Const2: .word 0xe000edc0                  \n"
-            " xRNRConst2: .word 0xe000ed98                    \n"
-            " xRBARConst2: .word 0xe000ed9c                   \n"
         );
     }
 
@@ -131,7 +124,7 @@
         (
             "   .syntax unified                                 \n"
             "                                                   \n"
-            "   ldr  r2, pxCurrentTCBConst2                     \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr  r2, =pxCurrentTCB                          \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr  r1, [r2]                                   \n" /* Read pxCurrentTCB. */
             "   ldr  r0, [r1]                                   \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
             "                                                   \n"
@@ -145,9 +138,6 @@
             "   mov  r0, #0                                     \n"
             "   msr  basepri, r0                                \n" /* Ensure that interrupts are enabled when the first task starts. */
             "   bx   r2                                         \n" /* Finally, branch to EXC_RETURN. */
-            "                                                   \n"
-            "   .align 4                                        \n"
-            "pxCurrentTCBConst2: .word pxCurrentTCB             \n"
         );
     }
 
@@ -166,8 +156,6 @@ BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
         "   movne r0, #0                                    \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
         "   moveq r0, #1                                    \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
         "   bx lr                                           \n" /* Return. */
-        "                                                   \n"
-        "   .align 4                                        \n"
         ::: "r0", "memory"
     );
 }
@@ -209,7 +197,7 @@ void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   ldr r0, xVTORConst                              \n" /* Use the NVIC offset register to locate the stack. */
+        "   ldr r0, =0xe000ed08                             \n" /* Use the NVIC offset register to locate the stack. */
         "   ldr r0, [r0]                                    \n" /* Read the VTOR register which gives the address of vector table. */
         "   ldr r0, [r0]                                    \n" /* The first entry in vector table is stack pointer. */
         "   msr msp, r0                                     \n" /* Set the MSP back to the start of the stack. */
@@ -219,9 +207,6 @@ void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
         "   isb                                             \n"
         "   svc %0                                          \n" /* System call to start the first task. */
         "   nop                                             \n"
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "xVTORConst: .word 0xe000ed08                       \n"
         ::"i" ( portSVC_START_SCHEDULER ) : "memory"
     );
 }
@@ -267,7 +252,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
         (
             " .syntax unified                                 \n"
             "                                                 \n"
-            " ldr r2, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            " ldr r2, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             " ldr r0, [r2]                                    \n" /* r0 = pxCurrentTCB. */
             " ldr r1, [r0]                                    \n" /* r1 = Location in TCB where the context should be saved. */
             " mrs r2, psp                                     \n" /* r2 = PSP. */
@@ -303,23 +288,23 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    msr basepri, r0                              \n" /* Enable interrupts. */
             "                                                 \n"
             " program_mpu:                                    \n"
-            "    ldr r2, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r2, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB. */
             "                                                 \n"
             "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-            "    ldr r1, xMPUCTRLConst                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
             "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
             "    str r2, [r1]                                 \n" /* Disable MPU. */
             "                                                 \n"
             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
             "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-            "    ldr r2, xMAIR0Const                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    ldr r2, =0xe000edc0                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
             "    str r1, [r2]                                 \n" /* Program MAIR0. */
             "                                                 \n"
             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-            "    ldr r1, xRNRConst                            \n" /* r1 = 0xe000ed98 [Location of RNR]. */
-            "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    ldr r1, =0xe000ed98                          \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
             "                                                 \n"
             "    movs r3, #4                                  \n" /* r3 = 4. */
             "    str r3, [r1]                                 \n" /* Program RNR = 4. */
@@ -337,14 +322,14 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
                 "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
             #endif /* configTOTAL_MPU_REGIONS == 16 */
             "                                                 \n"
-            "   ldr r1, xMPUCTRLConst                         \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "   ldr r1, =0xe000ed94                           \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
             "   orr r2, #1                                    \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
             "   str r2, [r1]                                  \n" /* Enable MPU. */
             "   dsb                                           \n" /* Force memory writes before continuing. */
             "                                                 \n"
             " restore_context:                                \n"
-            "    ldr r2, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r2, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB.*/
             "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
             "                                                 \n"
@@ -369,13 +354,6 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             " restore_context_done:                           \n"
             "    str r1, [r0]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
             "    bx lr                                        \n"
-            "                                                 \n"
-            " .align 4                                        \n"
-            " pxCurrentTCBConst: .word pxCurrentTCB           \n"
-            " xMPUCTRLConst: .word 0xe000ed94                 \n"
-            " xMAIR0Const: .word 0xe000edc0                   \n"
-            " xRNRConst: .word 0xe000ed98                     \n"
-            " xRBARConst: .word 0xe000ed9c                    \n"
             ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
         );
     }
@@ -400,7 +378,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   mov r3, lr                                      \n" /* r3 = LR/EXC_RETURN. */
             "   stmdb r0!, {r2-r11}                             \n" /* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */
             "                                                   \n"
-            "   ldr r2, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r2, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr r1, [r2]                                    \n" /* Read pxCurrentTCB. */
             "   str r0, [r1]                                    \n" /* Save the new top of stack in TCB. */
             "                                                   \n"
@@ -412,7 +390,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   mov r0, #0                                      \n" /* r0 = 0. */
             "   msr basepri, r0                                 \n" /* Enable interrupts. */
             "                                                   \n"
-            "   ldr r2, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r2, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr r1, [r2]                                    \n" /* Read pxCurrentTCB. */
             "   ldr r0, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
             "                                                   \n"
@@ -427,9 +405,6 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   msr psplim, r2                                  \n" /* Restore the PSPLIM register value for the task. */
             "   msr psp, r0                                     \n" /* Remember the new top of stack for the task. */
             "   bx r3                                           \n"
-            "                                                   \n"
-            "   .align 4                                        \n"
-            "pxCurrentTCBConst: .word pxCurrentTCB              \n"
             ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
         );
     }
@@ -487,11 +462,8 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   ite eq                                          \n"
             "   mrseq r0, msp                                   \n"
             "   mrsne r0, psp                                   \n"
-            "   ldr r1, svchandler_address_const                \n"
+            "   ldr r1, =vPortSVCHandler_C                      \n"
             "   bx r1                                           \n"
-            "                                                   \n"
-            "   .align 4                                        \n"
-            "svchandler_address_const: .word vPortSVCHandler_C  \n"
         );
     }
 
diff --git a/portable/GCC/ARM_CM35P/non_secure/portasm.c b/portable/GCC/ARM_CM35P/non_secure/portasm.c
index 1ee04b76d..aa9379fdf 100644
--- a/portable/GCC/ARM_CM35P/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM35P/non_secure/portasm.c
@@ -52,23 +52,23 @@
             " .syntax unified                                 \n"
             "                                                 \n"
             " program_mpu_first_task:                         \n"
-            "    ldr r3, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r3, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB. */
             "                                                 \n"
             "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-            "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
             "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
             "    str r2, [r1]                                 \n" /* Disable MPU. */
             "                                                 \n"
             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
             "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-            "    ldr r2, xMAIR0Const2                         \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    ldr r2, =0xe000edc0                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
             "    str r1, [r2]                                 \n" /* Program MAIR0. */
             "                                                 \n"
             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-            "    ldr r1, xRNRConst2                           \n" /* r1 = 0xe000ed98 [Location of RNR]. */
-            "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    ldr r1, =0xe000ed98                          \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
             "                                                 \n"
             "    movs r3, #4                                  \n" /* r3 = 4. */
             "    str r3, [r1]                                 \n" /* Program RNR = 4. */
@@ -86,14 +86,14 @@
                 "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
             #endif /* configTOTAL_MPU_REGIONS == 16 */
             "                                                 \n"
-            "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
             "    orr r2, #1                                   \n" /* r2 = r1 | 1 i.e. Set the bit 0 in r2. */
             "    str r2, [r1]                                 \n" /* Enable MPU. */
             "    dsb                                          \n" /* Force memory writes before continuing. */
             "                                                 \n"
             " restore_context_first_task:                     \n"
-            "    ldr r3, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r3, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "    ldr r1, [r3]                                 \n" /* r1 = pxCurrentTCB.*/
             "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
             "                                                 \n"
@@ -102,7 +102,7 @@
             "    msr psp, r3                                  \n"
             "    msr psplim, r4                               \n"
             "    msr control, r5                              \n"
-            "    ldr r4, xSecureContextConst2                 \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "    ldr r4, =xSecureContext                      \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
             "    str r0, [r4]                                 \n" /* Restore xSecureContext. */
             "                                                 \n"
             " restore_general_regs_first_task:                \n"
@@ -115,14 +115,6 @@
             "    mov r0, #0                                   \n"
             "    msr basepri, r0                              \n" /* Ensure that interrupts are enabled when the first task starts. */
             "    bx lr                                        \n"
-            "                                                 \n"
-            " .align 4                                        \n"
-            " pxCurrentTCBConst2: .word pxCurrentTCB          \n"
-            " xSecureContextConst2: .word xSecureContext      \n"
-            " xMPUCTRLConst2: .word 0xe000ed94                \n"
-            " xMAIR0Const2: .word 0xe000edc0                  \n"
-            " xRNRConst2: .word 0xe000ed98                    \n"
-            " xRBARConst2: .word 0xe000ed9c                   \n"
         );
     }
 
@@ -134,12 +126,12 @@
         (
             "   .syntax unified                                 \n"
             "                                                   \n"
-            "   ldr  r2, pxCurrentTCBConst2                     \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr  r2, =pxCurrentTCB                          \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr  r3, [r2]                                   \n" /* Read pxCurrentTCB. */
             "   ldr  r0, [r3]                                   \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
             "                                                   \n"
             "   ldm  r0!, {r1-r3}                               \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
-            "   ldr  r4, xSecureContextConst2                   \n"
+            "   ldr  r4, =xSecureContext                        \n"
             "   str  r1, [r4]                                   \n" /* Set xSecureContext to this task's value for the same. */
             "   msr  psplim, r2                                 \n" /* Set this task's PSPLIM value. */
             "   movs r1, #2                                     \n" /* r1 = 2. */
@@ -150,9 +142,6 @@
             "   mov  r0, #0                                     \n"
             "   msr  basepri, r0                                \n" /* Ensure that interrupts are enabled when the first task starts. */
             "   bx   r3                                         \n" /* Finally, branch to EXC_RETURN. */
-            "   .align 4                                        \n"
-            "pxCurrentTCBConst2: .word pxCurrentTCB             \n"
-            "xSecureContextConst2: .word xSecureContext         \n"
         );
     }
 
@@ -171,8 +160,6 @@ BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
         "   movne r0, #0                                    \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
         "   moveq r0, #1                                    \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
         "   bx lr                                           \n" /* Return. */
-        "                                                   \n"
-        "   .align 4                                        \n"
         ::: "r0", "memory"
     );
 }
@@ -214,7 +201,7 @@ void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   ldr r0, xVTORConst                              \n" /* Use the NVIC offset register to locate the stack. */
+        "   ldr r0, =0xe000ed08                             \n" /* Use the NVIC offset register to locate the stack. */
         "   ldr r0, [r0]                                    \n" /* Read the VTOR register which gives the address of vector table. */
         "   ldr r0, [r0]                                    \n" /* The first entry in vector table is stack pointer. */
         "   msr msp, r0                                     \n" /* Set the MSP back to the start of the stack. */
@@ -224,9 +211,6 @@ void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
         "   isb                                             \n"
         "   svc %0                                          \n" /* System call to start the first task. */
         "   nop                                             \n"
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "xVTORConst: .word 0xe000ed08                       \n"
         ::"i" ( portSVC_START_SCHEDULER ) : "memory"
     );
 }
@@ -274,9 +258,9 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             " .extern SecureContext_SaveContext               \n"
             " .extern SecureContext_LoadContext               \n"
             "                                                 \n"
-            " ldr r3, xSecureContextConst                     \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            " ldr r3, =xSecureContext                         \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
             " ldr r0, [r3]                                    \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
-            " ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            " ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             " ldr r1, [r3]                                    \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
             " ldr r2, [r1]                                    \n" /* r2 = Location in TCB where the context should be saved. */
             "                                                 \n"
@@ -325,23 +309,23 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    msr basepri, r0                              \n" /* Enable interrupts. */
             "                                                 \n"
             " program_mpu:                                    \n"
-            "    ldr r3, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r3, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB.*/
             "                                                 \n"
             "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-            "    ldr r1, xMPUCTRLConst                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
             "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
             "    str r2, [r1]                                 \n" /* Disable MPU. */
             "                                                 \n"
             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
             "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-            "    ldr r2, xMAIR0Const                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    ldr r2, =0xe000edc0                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
             "    str r1, [r2]                                 \n" /* Program MAIR0. */
             "                                                 \n"
             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-            "    ldr r1, xRNRConst                            \n" /* r1 = 0xe000ed98 [Location of RNR]. */
-            "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    ldr r1, =0xe000ed98                          \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
             "                                                 \n"
             "    movs r3, #4                                  \n" /* r3 = 4. */
             "    str r3, [r1]                                 \n" /* Program RNR = 4. */
@@ -359,14 +343,14 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
                 "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
             #endif /* configTOTAL_MPU_REGIONS == 16 */
             "                                                 \n"
-            "   ldr r1, xMPUCTRLConst                         \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "   ldr r1, =0xe000ed94                           \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
             "   orr r2, #1                                    \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
             "   str r2, [r1]                                  \n" /* Enable MPU. */
             "   dsb                                           \n" /* Force memory writes before continuing. */
             "                                                 \n"
             " restore_context:                                \n"
-            "    ldr r3, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r3, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "    ldr r1, [r3]                                 \n" /* r1 = pxCurrentTCB.*/
             "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
             "                                                 \n"
@@ -375,7 +359,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    msr psp, r3                                  \n"
             "    msr psplim, r4                               \n"
             "    msr control, r5                              \n"
-            "    ldr r4, xSecureContextConst                  \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "    ldr r4, =xSecureContext                      \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
             "    str r0, [r4]                                 \n" /* Restore xSecureContext. */
             "    cbz r0, restore_ns_context                   \n" /* No secure context to restore. */
             "                                                 \n"
@@ -404,14 +388,6 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             " restore_context_done:                           \n"
             "    str r2, [r1]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
             "    bx lr                                        \n"
-            "                                                 \n"
-            " .align 4                                        \n"
-            " pxCurrentTCBConst: .word pxCurrentTCB           \n"
-            " xSecureContextConst: .word xSecureContext       \n"
-            " xMPUCTRLConst: .word 0xe000ed94                 \n"
-            " xMAIR0Const: .word 0xe000edc0                   \n"
-            " xRNRConst: .word 0xe000ed98                     \n"
-            " xRBARConst: .word 0xe000ed9c                    \n"
             ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
         );
     }
@@ -426,9 +402,9 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   .extern SecureContext_SaveContext               \n"
             "   .extern SecureContext_LoadContext               \n"
             "                                                   \n"
-            "   ldr r3, xSecureContextConst                     \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "   ldr r3, =xSecureContext                         \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
             "   ldr r0, [r3]                                    \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
-            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
             "   mrs r2, psp                                     \n" /* Read PSP in r2. */
             "                                                   \n"
@@ -440,7 +416,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   lsls r1, r3, #25                                \n" /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
             "   bpl save_ns_context                             \n" /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
             "                                                   \n"
-            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB.*/
             "   subs r2, r2, #12                                \n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */
             "   str r2, [r1]                                    \n" /* Save the new top of stack in TCB. */
@@ -450,7 +426,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   b select_next_task                              \n"
             "                                                   \n"
             " save_ns_context:                                  \n"
-            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
                 "   tst lr, #0x10                               \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
@@ -475,17 +451,17 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   mov r0, #0                                      \n" /* r0 = 0. */
             "   msr basepri, r0                                 \n" /* Enable interrupts. */
             "                                                   \n"
-            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
             "   ldr r2, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
             "                                                   \n"
             "   ldmia r2!, {r0, r1, r4}                         \n" /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
             "   msr psplim, r1                                  \n" /* Restore the PSPLIM register value for the task. */
             "   mov lr, r4                                      \n" /* LR = r4. */
-            "   ldr r3, xSecureContextConst                     \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "   ldr r3, =xSecureContext                         \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
             "   str r0, [r3]                                    \n" /* Restore the task's xSecureContext. */
             "   cbz r0, restore_ns_context                      \n" /* If there is no secure context for the task, restore the non-secure context. */
-            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
             "   push {r2, r4}                                   \n"
             "   bl SecureContext_LoadContext                    \n" /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
@@ -505,10 +481,6 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             #endif /* configENABLE_FPU || configENABLE_MVE */
             "   msr psp, r2                                     \n" /* Remember the new top of stack for the task. */
             "   bx lr                                           \n"
-            "                                                   \n"
-            "   .align 4                                        \n"
-            "pxCurrentTCBConst: .word pxCurrentTCB              \n"
-            "xSecureContextConst: .word xSecureContext          \n"
             ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
         );
     }
@@ -566,11 +538,8 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   ite eq                                          \n"
             "   mrseq r0, msp                                   \n"
             "   mrsne r0, psp                                   \n"
-            "   ldr r1, svchandler_address_const                \n"
+            "   ldr r1, =vPortSVCHandler_C                      \n"
             "   bx r1                                           \n"
-            "                                                   \n"
-            "   .align 4                                        \n"
-            "svchandler_address_const: .word vPortSVCHandler_C  \n"
         );
     }
 
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.c b/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.c
index 56866d6b6..cdb2632c5 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.c
@@ -52,23 +52,23 @@
             " .syntax unified                                 \n"
             "                                                 \n"
             " program_mpu_first_task:                         \n"
-            "    ldr r2, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r2, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB. */
             "                                                 \n"
             "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-            "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
             "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
             "    str r2, [r1]                                 \n" /* Disable MPU. */
             "                                                 \n"
             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
             "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-            "    ldr r2, xMAIR0Const2                         \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    ldr r2, =0xe000edc0                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
             "    str r1, [r2]                                 \n" /* Program MAIR0. */
             "                                                 \n"
             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-            "    ldr r1, xRNRConst2                           \n" /* r1 = 0xe000ed98 [Location of RNR]. */
-            "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    ldr r1, =0xe000ed98                          \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
             "                                                 \n"
             "    movs r3, #4                                  \n" /* r3 = 4. */
             "    str r3, [r1]                                 \n" /* Program RNR = 4. */
@@ -86,14 +86,14 @@
                 "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
             #endif /* configTOTAL_MPU_REGIONS == 16 */
             "                                                 \n"
-            "   ldr r1, xMPUCTRLConst2                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "   ldr r1, =0xe000ed94                           \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
             "   orr r2, #1                                    \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
             "   str r2, [r1]                                  \n" /* Enable MPU. */
             "   dsb                                           \n" /* Force memory writes before continuing. */
             "                                                 \n"
             " restore_context_first_task:                     \n"
-            "    ldr r2, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r2, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB.*/
             "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
             "                                                 \n"
@@ -113,13 +113,6 @@
             "    mov r0, #0                                   \n"
             "    msr basepri, r0                              \n" /* Ensure that interrupts are enabled when the first task starts. */
             "    bx lr                                        \n"
-            "                                                 \n"
-            " .align 4                                        \n"
-            " pxCurrentTCBConst2: .word pxCurrentTCB          \n"
-            " xMPUCTRLConst2: .word 0xe000ed94                \n"
-            " xMAIR0Const2: .word 0xe000edc0                  \n"
-            " xRNRConst2: .word 0xe000ed98                    \n"
-            " xRBARConst2: .word 0xe000ed9c                   \n"
         );
     }
 
@@ -131,7 +124,7 @@
         (
             "   .syntax unified                                 \n"
             "                                                   \n"
-            "   ldr  r2, pxCurrentTCBConst2                     \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr  r2, =pxCurrentTCB                          \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr  r1, [r2]                                   \n" /* Read pxCurrentTCB. */
             "   ldr  r0, [r1]                                   \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
             "                                                   \n"
@@ -145,9 +138,6 @@
             "   mov  r0, #0                                     \n"
             "   msr  basepri, r0                                \n" /* Ensure that interrupts are enabled when the first task starts. */
             "   bx   r2                                         \n" /* Finally, branch to EXC_RETURN. */
-            "                                                   \n"
-            "   .align 4                                        \n"
-            "pxCurrentTCBConst2: .word pxCurrentTCB             \n"
         );
     }
 
@@ -166,8 +156,6 @@ BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
         "   movne r0, #0                                    \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
         "   moveq r0, #1                                    \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
         "   bx lr                                           \n" /* Return. */
-        "                                                   \n"
-        "   .align 4                                        \n"
         ::: "r0", "memory"
     );
 }
@@ -209,7 +197,7 @@ void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   ldr r0, xVTORConst                              \n" /* Use the NVIC offset register to locate the stack. */
+        "   ldr r0, =0xe000ed08                             \n" /* Use the NVIC offset register to locate the stack. */
         "   ldr r0, [r0]                                    \n" /* Read the VTOR register which gives the address of vector table. */
         "   ldr r0, [r0]                                    \n" /* The first entry in vector table is stack pointer. */
         "   msr msp, r0                                     \n" /* Set the MSP back to the start of the stack. */
@@ -219,9 +207,6 @@ void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
         "   isb                                             \n"
         "   svc %0                                          \n" /* System call to start the first task. */
         "   nop                                             \n"
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "xVTORConst: .word 0xe000ed08                       \n"
         ::"i" ( portSVC_START_SCHEDULER ) : "memory"
     );
 }
@@ -267,7 +252,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
         (
             " .syntax unified                                 \n"
             "                                                 \n"
-            " ldr r2, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            " ldr r2, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             " ldr r0, [r2]                                    \n" /* r0 = pxCurrentTCB. */
             " ldr r1, [r0]                                    \n" /* r1 = Location in TCB where the context should be saved. */
             " mrs r2, psp                                     \n" /* r2 = PSP. */
@@ -303,23 +288,23 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    msr basepri, r0                              \n" /* Enable interrupts. */
             "                                                 \n"
             " program_mpu:                                    \n"
-            "    ldr r2, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r2, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB. */
             "                                                 \n"
             "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-            "    ldr r1, xMPUCTRLConst                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
             "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
             "    str r2, [r1]                                 \n" /* Disable MPU. */
             "                                                 \n"
             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
             "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-            "    ldr r2, xMAIR0Const                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    ldr r2, =0xe000edc0                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
             "    str r1, [r2]                                 \n" /* Program MAIR0. */
             "                                                 \n"
             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-            "    ldr r1, xRNRConst                            \n" /* r1 = 0xe000ed98 [Location of RNR]. */
-            "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    ldr r1, =0xe000ed98                          \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
             "                                                 \n"
             "    movs r3, #4                                  \n" /* r3 = 4. */
             "    str r3, [r1]                                 \n" /* Program RNR = 4. */
@@ -337,14 +322,14 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
                 "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
             #endif /* configTOTAL_MPU_REGIONS == 16 */
             "                                                 \n"
-            "   ldr r1, xMPUCTRLConst                         \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "   ldr r1, =0xe000ed94                           \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
             "   orr r2, #1                                    \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
             "   str r2, [r1]                                  \n" /* Enable MPU. */
             "   dsb                                           \n" /* Force memory writes before continuing. */
             "                                                 \n"
             " restore_context:                                \n"
-            "    ldr r2, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r2, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB.*/
             "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
             "                                                 \n"
@@ -369,13 +354,6 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             " restore_context_done:                           \n"
             "    str r1, [r0]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
             "    bx lr                                        \n"
-            "                                                 \n"
-            " .align 4                                        \n"
-            " pxCurrentTCBConst: .word pxCurrentTCB           \n"
-            " xMPUCTRLConst: .word 0xe000ed94                 \n"
-            " xMAIR0Const: .word 0xe000edc0                   \n"
-            " xRNRConst: .word 0xe000ed98                     \n"
-            " xRBARConst: .word 0xe000ed9c                    \n"
             ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
         );
     }
@@ -400,7 +378,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   mov r3, lr                                      \n" /* r3 = LR/EXC_RETURN. */
             "   stmdb r0!, {r2-r11}                             \n" /* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */
             "                                                   \n"
-            "   ldr r2, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r2, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr r1, [r2]                                    \n" /* Read pxCurrentTCB. */
             "   str r0, [r1]                                    \n" /* Save the new top of stack in TCB. */
             "                                                   \n"
@@ -412,7 +390,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   mov r0, #0                                      \n" /* r0 = 0. */
             "   msr basepri, r0                                 \n" /* Enable interrupts. */
             "                                                   \n"
-            "   ldr r2, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r2, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr r1, [r2]                                    \n" /* Read pxCurrentTCB. */
             "   ldr r0, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
             "                                                   \n"
@@ -427,9 +405,6 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   msr psplim, r2                                  \n" /* Restore the PSPLIM register value for the task. */
             "   msr psp, r0                                     \n" /* Remember the new top of stack for the task. */
             "   bx r3                                           \n"
-            "                                                   \n"
-            "   .align 4                                        \n"
-            "pxCurrentTCBConst: .word pxCurrentTCB              \n"
             ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
         );
     }
@@ -487,11 +462,8 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   ite eq                                          \n"
             "   mrseq r0, msp                                   \n"
             "   mrsne r0, psp                                   \n"
-            "   ldr r1, svchandler_address_const                \n"
+            "   ldr r1, =vPortSVCHandler_C                      \n"
             "   bx r1                                           \n"
-            "                                                   \n"
-            "   .align 4                                        \n"
-            "svchandler_address_const: .word vPortSVCHandler_C  \n"
         );
     }
 
diff --git a/portable/GCC/ARM_CM55/non_secure/portasm.c b/portable/GCC/ARM_CM55/non_secure/portasm.c
index 1ee04b76d..aa9379fdf 100644
--- a/portable/GCC/ARM_CM55/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM55/non_secure/portasm.c
@@ -52,23 +52,23 @@
             " .syntax unified                                 \n"
             "                                                 \n"
             " program_mpu_first_task:                         \n"
-            "    ldr r3, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r3, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB. */
             "                                                 \n"
             "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-            "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
             "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
             "    str r2, [r1]                                 \n" /* Disable MPU. */
             "                                                 \n"
             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
             "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-            "    ldr r2, xMAIR0Const2                         \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    ldr r2, =0xe000edc0                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
             "    str r1, [r2]                                 \n" /* Program MAIR0. */
             "                                                 \n"
             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-            "    ldr r1, xRNRConst2                           \n" /* r1 = 0xe000ed98 [Location of RNR]. */
-            "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    ldr r1, =0xe000ed98                          \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
             "                                                 \n"
             "    movs r3, #4                                  \n" /* r3 = 4. */
             "    str r3, [r1]                                 \n" /* Program RNR = 4. */
@@ -86,14 +86,14 @@
                 "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
             #endif /* configTOTAL_MPU_REGIONS == 16 */
             "                                                 \n"
-            "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
             "    orr r2, #1                                   \n" /* r2 = r1 | 1 i.e. Set the bit 0 in r2. */
             "    str r2, [r1]                                 \n" /* Enable MPU. */
             "    dsb                                          \n" /* Force memory writes before continuing. */
             "                                                 \n"
             " restore_context_first_task:                     \n"
-            "    ldr r3, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r3, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "    ldr r1, [r3]                                 \n" /* r1 = pxCurrentTCB.*/
             "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
             "                                                 \n"
@@ -102,7 +102,7 @@
             "    msr psp, r3                                  \n"
             "    msr psplim, r4                               \n"
             "    msr control, r5                              \n"
-            "    ldr r4, xSecureContextConst2                 \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "    ldr r4, =xSecureContext                      \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
             "    str r0, [r4]                                 \n" /* Restore xSecureContext. */
             "                                                 \n"
             " restore_general_regs_first_task:                \n"
@@ -115,14 +115,6 @@
             "    mov r0, #0                                   \n"
             "    msr basepri, r0                              \n" /* Ensure that interrupts are enabled when the first task starts. */
             "    bx lr                                        \n"
-            "                                                 \n"
-            " .align 4                                        \n"
-            " pxCurrentTCBConst2: .word pxCurrentTCB          \n"
-            " xSecureContextConst2: .word xSecureContext      \n"
-            " xMPUCTRLConst2: .word 0xe000ed94                \n"
-            " xMAIR0Const2: .word 0xe000edc0                  \n"
-            " xRNRConst2: .word 0xe000ed98                    \n"
-            " xRBARConst2: .word 0xe000ed9c                   \n"
         );
     }
 
@@ -134,12 +126,12 @@
         (
             "   .syntax unified                                 \n"
             "                                                   \n"
-            "   ldr  r2, pxCurrentTCBConst2                     \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr  r2, =pxCurrentTCB                          \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr  r3, [r2]                                   \n" /* Read pxCurrentTCB. */
             "   ldr  r0, [r3]                                   \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
             "                                                   \n"
             "   ldm  r0!, {r1-r3}                               \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
-            "   ldr  r4, xSecureContextConst2                   \n"
+            "   ldr  r4, =xSecureContext                        \n"
             "   str  r1, [r4]                                   \n" /* Set xSecureContext to this task's value for the same. */
             "   msr  psplim, r2                                 \n" /* Set this task's PSPLIM value. */
             "   movs r1, #2                                     \n" /* r1 = 2. */
@@ -150,9 +142,6 @@
             "   mov  r0, #0                                     \n"
             "   msr  basepri, r0                                \n" /* Ensure that interrupts are enabled when the first task starts. */
             "   bx   r3                                         \n" /* Finally, branch to EXC_RETURN. */
-            "   .align 4                                        \n"
-            "pxCurrentTCBConst2: .word pxCurrentTCB             \n"
-            "xSecureContextConst2: .word xSecureContext         \n"
         );
     }
 
@@ -171,8 +160,6 @@ BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
         "   movne r0, #0                                    \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
         "   moveq r0, #1                                    \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
         "   bx lr                                           \n" /* Return. */
-        "                                                   \n"
-        "   .align 4                                        \n"
         ::: "r0", "memory"
     );
 }
@@ -214,7 +201,7 @@ void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   ldr r0, xVTORConst                              \n" /* Use the NVIC offset register to locate the stack. */
+        "   ldr r0, =0xe000ed08                             \n" /* Use the NVIC offset register to locate the stack. */
         "   ldr r0, [r0]                                    \n" /* Read the VTOR register which gives the address of vector table. */
         "   ldr r0, [r0]                                    \n" /* The first entry in vector table is stack pointer. */
         "   msr msp, r0                                     \n" /* Set the MSP back to the start of the stack. */
@@ -224,9 +211,6 @@ void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
         "   isb                                             \n"
         "   svc %0                                          \n" /* System call to start the first task. */
         "   nop                                             \n"
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "xVTORConst: .word 0xe000ed08                       \n"
         ::"i" ( portSVC_START_SCHEDULER ) : "memory"
     );
 }
@@ -274,9 +258,9 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             " .extern SecureContext_SaveContext               \n"
             " .extern SecureContext_LoadContext               \n"
             "                                                 \n"
-            " ldr r3, xSecureContextConst                     \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            " ldr r3, =xSecureContext                         \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
             " ldr r0, [r3]                                    \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
-            " ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            " ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             " ldr r1, [r3]                                    \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
             " ldr r2, [r1]                                    \n" /* r2 = Location in TCB where the context should be saved. */
             "                                                 \n"
@@ -325,23 +309,23 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    msr basepri, r0                              \n" /* Enable interrupts. */
             "                                                 \n"
             " program_mpu:                                    \n"
-            "    ldr r3, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r3, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB.*/
             "                                                 \n"
             "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-            "    ldr r1, xMPUCTRLConst                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
             "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
             "    str r2, [r1]                                 \n" /* Disable MPU. */
             "                                                 \n"
             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
             "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-            "    ldr r2, xMAIR0Const                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    ldr r2, =0xe000edc0                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
             "    str r1, [r2]                                 \n" /* Program MAIR0. */
             "                                                 \n"
             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-            "    ldr r1, xRNRConst                            \n" /* r1 = 0xe000ed98 [Location of RNR]. */
-            "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    ldr r1, =0xe000ed98                          \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
             "                                                 \n"
             "    movs r3, #4                                  \n" /* r3 = 4. */
             "    str r3, [r1]                                 \n" /* Program RNR = 4. */
@@ -359,14 +343,14 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
                 "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
             #endif /* configTOTAL_MPU_REGIONS == 16 */
             "                                                 \n"
-            "   ldr r1, xMPUCTRLConst                         \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "   ldr r1, =0xe000ed94                           \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
             "   orr r2, #1                                    \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
             "   str r2, [r1]                                  \n" /* Enable MPU. */
             "   dsb                                           \n" /* Force memory writes before continuing. */
             "                                                 \n"
             " restore_context:                                \n"
-            "    ldr r3, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r3, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "    ldr r1, [r3]                                 \n" /* r1 = pxCurrentTCB.*/
             "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
             "                                                 \n"
@@ -375,7 +359,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    msr psp, r3                                  \n"
             "    msr psplim, r4                               \n"
             "    msr control, r5                              \n"
-            "    ldr r4, xSecureContextConst                  \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "    ldr r4, =xSecureContext                      \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
             "    str r0, [r4]                                 \n" /* Restore xSecureContext. */
             "    cbz r0, restore_ns_context                   \n" /* No secure context to restore. */
             "                                                 \n"
@@ -404,14 +388,6 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             " restore_context_done:                           \n"
             "    str r2, [r1]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
             "    bx lr                                        \n"
-            "                                                 \n"
-            " .align 4                                        \n"
-            " pxCurrentTCBConst: .word pxCurrentTCB           \n"
-            " xSecureContextConst: .word xSecureContext       \n"
-            " xMPUCTRLConst: .word 0xe000ed94                 \n"
-            " xMAIR0Const: .word 0xe000edc0                   \n"
-            " xRNRConst: .word 0xe000ed98                     \n"
-            " xRBARConst: .word 0xe000ed9c                    \n"
             ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
         );
     }
@@ -426,9 +402,9 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   .extern SecureContext_SaveContext               \n"
             "   .extern SecureContext_LoadContext               \n"
             "                                                   \n"
-            "   ldr r3, xSecureContextConst                     \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "   ldr r3, =xSecureContext                         \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
             "   ldr r0, [r3]                                    \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
-            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
             "   mrs r2, psp                                     \n" /* Read PSP in r2. */
             "                                                   \n"
@@ -440,7 +416,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   lsls r1, r3, #25                                \n" /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
             "   bpl save_ns_context                             \n" /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
             "                                                   \n"
-            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB.*/
             "   subs r2, r2, #12                                \n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */
             "   str r2, [r1]                                    \n" /* Save the new top of stack in TCB. */
@@ -450,7 +426,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   b select_next_task                              \n"
             "                                                   \n"
             " save_ns_context:                                  \n"
-            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
                 "   tst lr, #0x10                               \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
@@ -475,17 +451,17 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   mov r0, #0                                      \n" /* r0 = 0. */
             "   msr basepri, r0                                 \n" /* Enable interrupts. */
             "                                                   \n"
-            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
             "   ldr r2, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
             "                                                   \n"
             "   ldmia r2!, {r0, r1, r4}                         \n" /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
             "   msr psplim, r1                                  \n" /* Restore the PSPLIM register value for the task. */
             "   mov lr, r4                                      \n" /* LR = r4. */
-            "   ldr r3, xSecureContextConst                     \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "   ldr r3, =xSecureContext                         \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
             "   str r0, [r3]                                    \n" /* Restore the task's xSecureContext. */
             "   cbz r0, restore_ns_context                      \n" /* If there is no secure context for the task, restore the non-secure context. */
-            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
             "   push {r2, r4}                                   \n"
             "   bl SecureContext_LoadContext                    \n" /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
@@ -505,10 +481,6 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             #endif /* configENABLE_FPU || configENABLE_MVE */
             "   msr psp, r2                                     \n" /* Remember the new top of stack for the task. */
             "   bx lr                                           \n"
-            "                                                   \n"
-            "   .align 4                                        \n"
-            "pxCurrentTCBConst: .word pxCurrentTCB              \n"
-            "xSecureContextConst: .word xSecureContext          \n"
             ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
         );
     }
@@ -566,11 +538,8 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   ite eq                                          \n"
             "   mrseq r0, msp                                   \n"
             "   mrsne r0, psp                                   \n"
-            "   ldr r1, svchandler_address_const                \n"
+            "   ldr r1, =vPortSVCHandler_C                      \n"
             "   bx r1                                           \n"
-            "                                                   \n"
-            "   .align 4                                        \n"
-            "svchandler_address_const: .word vPortSVCHandler_C  \n"
         );
     }
 
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.c b/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.c
index 56866d6b6..cdb2632c5 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.c
@@ -52,23 +52,23 @@
             " .syntax unified                                 \n"
             "                                                 \n"
             " program_mpu_first_task:                         \n"
-            "    ldr r2, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r2, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB. */
             "                                                 \n"
             "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-            "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
             "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
             "    str r2, [r1]                                 \n" /* Disable MPU. */
             "                                                 \n"
             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
             "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-            "    ldr r2, xMAIR0Const2                         \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    ldr r2, =0xe000edc0                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
             "    str r1, [r2]                                 \n" /* Program MAIR0. */
             "                                                 \n"
             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-            "    ldr r1, xRNRConst2                           \n" /* r1 = 0xe000ed98 [Location of RNR]. */
-            "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    ldr r1, =0xe000ed98                          \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
             "                                                 \n"
             "    movs r3, #4                                  \n" /* r3 = 4. */
             "    str r3, [r1]                                 \n" /* Program RNR = 4. */
@@ -86,14 +86,14 @@
                 "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
             #endif /* configTOTAL_MPU_REGIONS == 16 */
             "                                                 \n"
-            "   ldr r1, xMPUCTRLConst2                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "   ldr r1, =0xe000ed94                           \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
             "   orr r2, #1                                    \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
             "   str r2, [r1]                                  \n" /* Enable MPU. */
             "   dsb                                           \n" /* Force memory writes before continuing. */
             "                                                 \n"
             " restore_context_first_task:                     \n"
-            "    ldr r2, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r2, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB.*/
             "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
             "                                                 \n"
@@ -113,13 +113,6 @@
             "    mov r0, #0                                   \n"
             "    msr basepri, r0                              \n" /* Ensure that interrupts are enabled when the first task starts. */
             "    bx lr                                        \n"
-            "                                                 \n"
-            " .align 4                                        \n"
-            " pxCurrentTCBConst2: .word pxCurrentTCB          \n"
-            " xMPUCTRLConst2: .word 0xe000ed94                \n"
-            " xMAIR0Const2: .word 0xe000edc0                  \n"
-            " xRNRConst2: .word 0xe000ed98                    \n"
-            " xRBARConst2: .word 0xe000ed9c                   \n"
         );
     }
 
@@ -131,7 +124,7 @@
         (
             "   .syntax unified                                 \n"
             "                                                   \n"
-            "   ldr  r2, pxCurrentTCBConst2                     \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr  r2, =pxCurrentTCB                          \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr  r1, [r2]                                   \n" /* Read pxCurrentTCB. */
             "   ldr  r0, [r1]                                   \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
             "                                                   \n"
@@ -145,9 +138,6 @@
             "   mov  r0, #0                                     \n"
             "   msr  basepri, r0                                \n" /* Ensure that interrupts are enabled when the first task starts. */
             "   bx   r2                                         \n" /* Finally, branch to EXC_RETURN. */
-            "                                                   \n"
-            "   .align 4                                        \n"
-            "pxCurrentTCBConst2: .word pxCurrentTCB             \n"
         );
     }
 
@@ -166,8 +156,6 @@ BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
         "   movne r0, #0                                    \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
         "   moveq r0, #1                                    \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
         "   bx lr                                           \n" /* Return. */
-        "                                                   \n"
-        "   .align 4                                        \n"
         ::: "r0", "memory"
     );
 }
@@ -209,7 +197,7 @@ void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   ldr r0, xVTORConst                              \n" /* Use the NVIC offset register to locate the stack. */
+        "   ldr r0, =0xe000ed08                             \n" /* Use the NVIC offset register to locate the stack. */
         "   ldr r0, [r0]                                    \n" /* Read the VTOR register which gives the address of vector table. */
         "   ldr r0, [r0]                                    \n" /* The first entry in vector table is stack pointer. */
         "   msr msp, r0                                     \n" /* Set the MSP back to the start of the stack. */
@@ -219,9 +207,6 @@ void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
         "   isb                                             \n"
         "   svc %0                                          \n" /* System call to start the first task. */
         "   nop                                             \n"
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "xVTORConst: .word 0xe000ed08                       \n"
         ::"i" ( portSVC_START_SCHEDULER ) : "memory"
     );
 }
@@ -267,7 +252,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
         (
             " .syntax unified                                 \n"
             "                                                 \n"
-            " ldr r2, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            " ldr r2, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             " ldr r0, [r2]                                    \n" /* r0 = pxCurrentTCB. */
             " ldr r1, [r0]                                    \n" /* r1 = Location in TCB where the context should be saved. */
             " mrs r2, psp                                     \n" /* r2 = PSP. */
@@ -303,23 +288,23 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    msr basepri, r0                              \n" /* Enable interrupts. */
             "                                                 \n"
             " program_mpu:                                    \n"
-            "    ldr r2, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r2, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB. */
             "                                                 \n"
             "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-            "    ldr r1, xMPUCTRLConst                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
             "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
             "    str r2, [r1]                                 \n" /* Disable MPU. */
             "                                                 \n"
             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
             "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-            "    ldr r2, xMAIR0Const                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    ldr r2, =0xe000edc0                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
             "    str r1, [r2]                                 \n" /* Program MAIR0. */
             "                                                 \n"
             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-            "    ldr r1, xRNRConst                            \n" /* r1 = 0xe000ed98 [Location of RNR]. */
-            "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    ldr r1, =0xe000ed98                          \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
             "                                                 \n"
             "    movs r3, #4                                  \n" /* r3 = 4. */
             "    str r3, [r1]                                 \n" /* Program RNR = 4. */
@@ -337,14 +322,14 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
                 "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
             #endif /* configTOTAL_MPU_REGIONS == 16 */
             "                                                 \n"
-            "   ldr r1, xMPUCTRLConst                         \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "   ldr r1, =0xe000ed94                           \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
             "   orr r2, #1                                    \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
             "   str r2, [r1]                                  \n" /* Enable MPU. */
             "   dsb                                           \n" /* Force memory writes before continuing. */
             "                                                 \n"
             " restore_context:                                \n"
-            "    ldr r2, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r2, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB.*/
             "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
             "                                                 \n"
@@ -369,13 +354,6 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             " restore_context_done:                           \n"
             "    str r1, [r0]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
             "    bx lr                                        \n"
-            "                                                 \n"
-            " .align 4                                        \n"
-            " pxCurrentTCBConst: .word pxCurrentTCB           \n"
-            " xMPUCTRLConst: .word 0xe000ed94                 \n"
-            " xMAIR0Const: .word 0xe000edc0                   \n"
-            " xRNRConst: .word 0xe000ed98                     \n"
-            " xRBARConst: .word 0xe000ed9c                    \n"
             ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
         );
     }
@@ -400,7 +378,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   mov r3, lr                                      \n" /* r3 = LR/EXC_RETURN. */
             "   stmdb r0!, {r2-r11}                             \n" /* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */
             "                                                   \n"
-            "   ldr r2, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r2, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr r1, [r2]                                    \n" /* Read pxCurrentTCB. */
             "   str r0, [r1]                                    \n" /* Save the new top of stack in TCB. */
             "                                                   \n"
@@ -412,7 +390,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   mov r0, #0                                      \n" /* r0 = 0. */
             "   msr basepri, r0                                 \n" /* Enable interrupts. */
             "                                                   \n"
-            "   ldr r2, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r2, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr r1, [r2]                                    \n" /* Read pxCurrentTCB. */
             "   ldr r0, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
             "                                                   \n"
@@ -427,9 +405,6 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   msr psplim, r2                                  \n" /* Restore the PSPLIM register value for the task. */
             "   msr psp, r0                                     \n" /* Remember the new top of stack for the task. */
             "   bx r3                                           \n"
-            "                                                   \n"
-            "   .align 4                                        \n"
-            "pxCurrentTCBConst: .word pxCurrentTCB              \n"
             ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
         );
     }
@@ -487,11 +462,8 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   ite eq                                          \n"
             "   mrseq r0, msp                                   \n"
             "   mrsne r0, psp                                   \n"
-            "   ldr r1, svchandler_address_const                \n"
+            "   ldr r1, =vPortSVCHandler_C                      \n"
             "   bx r1                                           \n"
-            "                                                   \n"
-            "   .align 4                                        \n"
-            "svchandler_address_const: .word vPortSVCHandler_C  \n"
         );
     }
 
diff --git a/portable/GCC/ARM_CM85/non_secure/portasm.c b/portable/GCC/ARM_CM85/non_secure/portasm.c
index 1ee04b76d..aa9379fdf 100644
--- a/portable/GCC/ARM_CM85/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM85/non_secure/portasm.c
@@ -52,23 +52,23 @@
             " .syntax unified                                 \n"
             "                                                 \n"
             " program_mpu_first_task:                         \n"
-            "    ldr r3, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r3, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB. */
             "                                                 \n"
             "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-            "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
             "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
             "    str r2, [r1]                                 \n" /* Disable MPU. */
             "                                                 \n"
             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
             "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-            "    ldr r2, xMAIR0Const2                         \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    ldr r2, =0xe000edc0                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
             "    str r1, [r2]                                 \n" /* Program MAIR0. */
             "                                                 \n"
             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-            "    ldr r1, xRNRConst2                           \n" /* r1 = 0xe000ed98 [Location of RNR]. */
-            "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    ldr r1, =0xe000ed98                          \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
             "                                                 \n"
             "    movs r3, #4                                  \n" /* r3 = 4. */
             "    str r3, [r1]                                 \n" /* Program RNR = 4. */
@@ -86,14 +86,14 @@
                 "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
             #endif /* configTOTAL_MPU_REGIONS == 16 */
             "                                                 \n"
-            "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
             "    orr r2, #1                                   \n" /* r2 = r1 | 1 i.e. Set the bit 0 in r2. */
             "    str r2, [r1]                                 \n" /* Enable MPU. */
             "    dsb                                          \n" /* Force memory writes before continuing. */
             "                                                 \n"
             " restore_context_first_task:                     \n"
-            "    ldr r3, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r3, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "    ldr r1, [r3]                                 \n" /* r1 = pxCurrentTCB.*/
             "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
             "                                                 \n"
@@ -102,7 +102,7 @@
             "    msr psp, r3                                  \n"
             "    msr psplim, r4                               \n"
             "    msr control, r5                              \n"
-            "    ldr r4, xSecureContextConst2                 \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "    ldr r4, =xSecureContext                      \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
             "    str r0, [r4]                                 \n" /* Restore xSecureContext. */
             "                                                 \n"
             " restore_general_regs_first_task:                \n"
@@ -115,14 +115,6 @@
             "    mov r0, #0                                   \n"
             "    msr basepri, r0                              \n" /* Ensure that interrupts are enabled when the first task starts. */
             "    bx lr                                        \n"
-            "                                                 \n"
-            " .align 4                                        \n"
-            " pxCurrentTCBConst2: .word pxCurrentTCB          \n"
-            " xSecureContextConst2: .word xSecureContext      \n"
-            " xMPUCTRLConst2: .word 0xe000ed94                \n"
-            " xMAIR0Const2: .word 0xe000edc0                  \n"
-            " xRNRConst2: .word 0xe000ed98                    \n"
-            " xRBARConst2: .word 0xe000ed9c                   \n"
         );
     }
 
@@ -134,12 +126,12 @@
         (
             "   .syntax unified                                 \n"
             "                                                   \n"
-            "   ldr  r2, pxCurrentTCBConst2                     \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr  r2, =pxCurrentTCB                          \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr  r3, [r2]                                   \n" /* Read pxCurrentTCB. */
             "   ldr  r0, [r3]                                   \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
             "                                                   \n"
             "   ldm  r0!, {r1-r3}                               \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
-            "   ldr  r4, xSecureContextConst2                   \n"
+            "   ldr  r4, =xSecureContext                        \n"
             "   str  r1, [r4]                                   \n" /* Set xSecureContext to this task's value for the same. */
             "   msr  psplim, r2                                 \n" /* Set this task's PSPLIM value. */
             "   movs r1, #2                                     \n" /* r1 = 2. */
@@ -150,9 +142,6 @@
             "   mov  r0, #0                                     \n"
             "   msr  basepri, r0                                \n" /* Ensure that interrupts are enabled when the first task starts. */
             "   bx   r3                                         \n" /* Finally, branch to EXC_RETURN. */
-            "   .align 4                                        \n"
-            "pxCurrentTCBConst2: .word pxCurrentTCB             \n"
-            "xSecureContextConst2: .word xSecureContext         \n"
         );
     }
 
@@ -171,8 +160,6 @@ BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
         "   movne r0, #0                                    \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
         "   moveq r0, #1                                    \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
         "   bx lr                                           \n" /* Return. */
-        "                                                   \n"
-        "   .align 4                                        \n"
         ::: "r0", "memory"
     );
 }
@@ -214,7 +201,7 @@ void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   ldr r0, xVTORConst                              \n" /* Use the NVIC offset register to locate the stack. */
+        "   ldr r0, =0xe000ed08                             \n" /* Use the NVIC offset register to locate the stack. */
         "   ldr r0, [r0]                                    \n" /* Read the VTOR register which gives the address of vector table. */
         "   ldr r0, [r0]                                    \n" /* The first entry in vector table is stack pointer. */
         "   msr msp, r0                                     \n" /* Set the MSP back to the start of the stack. */
@@ -224,9 +211,6 @@ void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
         "   isb                                             \n"
         "   svc %0                                          \n" /* System call to start the first task. */
         "   nop                                             \n"
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "xVTORConst: .word 0xe000ed08                       \n"
         ::"i" ( portSVC_START_SCHEDULER ) : "memory"
     );
 }
@@ -274,9 +258,9 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             " .extern SecureContext_SaveContext               \n"
             " .extern SecureContext_LoadContext               \n"
             "                                                 \n"
-            " ldr r3, xSecureContextConst                     \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            " ldr r3, =xSecureContext                         \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
             " ldr r0, [r3]                                    \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
-            " ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            " ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             " ldr r1, [r3]                                    \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
             " ldr r2, [r1]                                    \n" /* r2 = Location in TCB where the context should be saved. */
             "                                                 \n"
@@ -325,23 +309,23 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    msr basepri, r0                              \n" /* Enable interrupts. */
             "                                                 \n"
             " program_mpu:                                    \n"
-            "    ldr r3, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r3, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB.*/
             "                                                 \n"
             "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-            "    ldr r1, xMPUCTRLConst                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
             "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
             "    str r2, [r1]                                 \n" /* Disable MPU. */
             "                                                 \n"
             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
             "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-            "    ldr r2, xMAIR0Const                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    ldr r2, =0xe000edc0                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
             "    str r1, [r2]                                 \n" /* Program MAIR0. */
             "                                                 \n"
             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-            "    ldr r1, xRNRConst                            \n" /* r1 = 0xe000ed98 [Location of RNR]. */
-            "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    ldr r1, =0xe000ed98                          \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
             "                                                 \n"
             "    movs r3, #4                                  \n" /* r3 = 4. */
             "    str r3, [r1]                                 \n" /* Program RNR = 4. */
@@ -359,14 +343,14 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
                 "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
             #endif /* configTOTAL_MPU_REGIONS == 16 */
             "                                                 \n"
-            "   ldr r1, xMPUCTRLConst                         \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "   ldr r1, =0xe000ed94                           \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
             "   orr r2, #1                                    \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
             "   str r2, [r1]                                  \n" /* Enable MPU. */
             "   dsb                                           \n" /* Force memory writes before continuing. */
             "                                                 \n"
             " restore_context:                                \n"
-            "    ldr r3, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r3, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "    ldr r1, [r3]                                 \n" /* r1 = pxCurrentTCB.*/
             "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
             "                                                 \n"
@@ -375,7 +359,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    msr psp, r3                                  \n"
             "    msr psplim, r4                               \n"
             "    msr control, r5                              \n"
-            "    ldr r4, xSecureContextConst                  \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "    ldr r4, =xSecureContext                      \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
             "    str r0, [r4]                                 \n" /* Restore xSecureContext. */
             "    cbz r0, restore_ns_context                   \n" /* No secure context to restore. */
             "                                                 \n"
@@ -404,14 +388,6 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             " restore_context_done:                           \n"
             "    str r2, [r1]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
             "    bx lr                                        \n"
-            "                                                 \n"
-            " .align 4                                        \n"
-            " pxCurrentTCBConst: .word pxCurrentTCB           \n"
-            " xSecureContextConst: .word xSecureContext       \n"
-            " xMPUCTRLConst: .word 0xe000ed94                 \n"
-            " xMAIR0Const: .word 0xe000edc0                   \n"
-            " xRNRConst: .word 0xe000ed98                     \n"
-            " xRBARConst: .word 0xe000ed9c                    \n"
             ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
         );
     }
@@ -426,9 +402,9 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   .extern SecureContext_SaveContext               \n"
             "   .extern SecureContext_LoadContext               \n"
             "                                                   \n"
-            "   ldr r3, xSecureContextConst                     \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "   ldr r3, =xSecureContext                         \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
             "   ldr r0, [r3]                                    \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
-            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
             "   mrs r2, psp                                     \n" /* Read PSP in r2. */
             "                                                   \n"
@@ -440,7 +416,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   lsls r1, r3, #25                                \n" /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
             "   bpl save_ns_context                             \n" /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
             "                                                   \n"
-            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB.*/
             "   subs r2, r2, #12                                \n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */
             "   str r2, [r1]                                    \n" /* Save the new top of stack in TCB. */
@@ -450,7 +426,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   b select_next_task                              \n"
             "                                                   \n"
             " save_ns_context:                                  \n"
-            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
                 "   tst lr, #0x10                               \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
@@ -475,17 +451,17 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   mov r0, #0                                      \n" /* r0 = 0. */
             "   msr basepri, r0                                 \n" /* Enable interrupts. */
             "                                                   \n"
-            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
             "   ldr r2, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
             "                                                   \n"
             "   ldmia r2!, {r0, r1, r4}                         \n" /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
             "   msr psplim, r1                                  \n" /* Restore the PSPLIM register value for the task. */
             "   mov lr, r4                                      \n" /* LR = r4. */
-            "   ldr r3, xSecureContextConst                     \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "   ldr r3, =xSecureContext                         \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
             "   str r0, [r3]                                    \n" /* Restore the task's xSecureContext. */
             "   cbz r0, restore_ns_context                      \n" /* If there is no secure context for the task, restore the non-secure context. */
-            "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
             "   push {r2, r4}                                   \n"
             "   bl SecureContext_LoadContext                    \n" /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
@@ -505,10 +481,6 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             #endif /* configENABLE_FPU || configENABLE_MVE */
             "   msr psp, r2                                     \n" /* Remember the new top of stack for the task. */
             "   bx lr                                           \n"
-            "                                                   \n"
-            "   .align 4                                        \n"
-            "pxCurrentTCBConst: .word pxCurrentTCB              \n"
-            "xSecureContextConst: .word xSecureContext          \n"
             ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
         );
     }
@@ -566,11 +538,8 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   ite eq                                          \n"
             "   mrseq r0, msp                                   \n"
             "   mrsne r0, psp                                   \n"
-            "   ldr r1, svchandler_address_const                \n"
+            "   ldr r1, =vPortSVCHandler_C                      \n"
             "   bx r1                                           \n"
-            "                                                   \n"
-            "   .align 4                                        \n"
-            "svchandler_address_const: .word vPortSVCHandler_C  \n"
         );
     }
 
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.c b/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.c
index 56866d6b6..cdb2632c5 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.c
@@ -52,23 +52,23 @@
             " .syntax unified                                 \n"
             "                                                 \n"
             " program_mpu_first_task:                         \n"
-            "    ldr r2, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r2, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB. */
             "                                                 \n"
             "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-            "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
             "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
             "    str r2, [r1]                                 \n" /* Disable MPU. */
             "                                                 \n"
             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
             "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-            "    ldr r2, xMAIR0Const2                         \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    ldr r2, =0xe000edc0                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
             "    str r1, [r2]                                 \n" /* Program MAIR0. */
             "                                                 \n"
             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-            "    ldr r1, xRNRConst2                           \n" /* r1 = 0xe000ed98 [Location of RNR]. */
-            "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    ldr r1, =0xe000ed98                          \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
             "                                                 \n"
             "    movs r3, #4                                  \n" /* r3 = 4. */
             "    str r3, [r1]                                 \n" /* Program RNR = 4. */
@@ -86,14 +86,14 @@
                 "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
             #endif /* configTOTAL_MPU_REGIONS == 16 */
             "                                                 \n"
-            "   ldr r1, xMPUCTRLConst2                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "   ldr r1, =0xe000ed94                           \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
             "   orr r2, #1                                    \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
             "   str r2, [r1]                                  \n" /* Enable MPU. */
             "   dsb                                           \n" /* Force memory writes before continuing. */
             "                                                 \n"
             " restore_context_first_task:                     \n"
-            "    ldr r2, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r2, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB.*/
             "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
             "                                                 \n"
@@ -113,13 +113,6 @@
             "    mov r0, #0                                   \n"
             "    msr basepri, r0                              \n" /* Ensure that interrupts are enabled when the first task starts. */
             "    bx lr                                        \n"
-            "                                                 \n"
-            " .align 4                                        \n"
-            " pxCurrentTCBConst2: .word pxCurrentTCB          \n"
-            " xMPUCTRLConst2: .word 0xe000ed94                \n"
-            " xMAIR0Const2: .word 0xe000edc0                  \n"
-            " xRNRConst2: .word 0xe000ed98                    \n"
-            " xRBARConst2: .word 0xe000ed9c                   \n"
         );
     }
 
@@ -131,7 +124,7 @@
         (
             "   .syntax unified                                 \n"
             "                                                   \n"
-            "   ldr  r2, pxCurrentTCBConst2                     \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr  r2, =pxCurrentTCB                          \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr  r1, [r2]                                   \n" /* Read pxCurrentTCB. */
             "   ldr  r0, [r1]                                   \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
             "                                                   \n"
@@ -145,9 +138,6 @@
             "   mov  r0, #0                                     \n"
             "   msr  basepri, r0                                \n" /* Ensure that interrupts are enabled when the first task starts. */
             "   bx   r2                                         \n" /* Finally, branch to EXC_RETURN. */
-            "                                                   \n"
-            "   .align 4                                        \n"
-            "pxCurrentTCBConst2: .word pxCurrentTCB             \n"
         );
     }
 
@@ -166,8 +156,6 @@ BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
         "   movne r0, #0                                    \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
         "   moveq r0, #1                                    \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
         "   bx lr                                           \n" /* Return. */
-        "                                                   \n"
-        "   .align 4                                        \n"
         ::: "r0", "memory"
     );
 }
@@ -209,7 +197,7 @@ void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   ldr r0, xVTORConst                              \n" /* Use the NVIC offset register to locate the stack. */
+        "   ldr r0, =0xe000ed08                             \n" /* Use the NVIC offset register to locate the stack. */
         "   ldr r0, [r0]                                    \n" /* Read the VTOR register which gives the address of vector table. */
         "   ldr r0, [r0]                                    \n" /* The first entry in vector table is stack pointer. */
         "   msr msp, r0                                     \n" /* Set the MSP back to the start of the stack. */
@@ -219,9 +207,6 @@ void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
         "   isb                                             \n"
         "   svc %0                                          \n" /* System call to start the first task. */
         "   nop                                             \n"
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "xVTORConst: .word 0xe000ed08                       \n"
         ::"i" ( portSVC_START_SCHEDULER ) : "memory"
     );
 }
@@ -267,7 +252,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
         (
             " .syntax unified                                 \n"
             "                                                 \n"
-            " ldr r2, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            " ldr r2, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             " ldr r0, [r2]                                    \n" /* r0 = pxCurrentTCB. */
             " ldr r1, [r0]                                    \n" /* r1 = Location in TCB where the context should be saved. */
             " mrs r2, psp                                     \n" /* r2 = PSP. */
@@ -303,23 +288,23 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    msr basepri, r0                              \n" /* Enable interrupts. */
             "                                                 \n"
             " program_mpu:                                    \n"
-            "    ldr r2, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r2, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB. */
             "                                                 \n"
             "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-            "    ldr r1, xMPUCTRLConst                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
             "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
             "    str r2, [r1]                                 \n" /* Disable MPU. */
             "                                                 \n"
             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
             "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-            "    ldr r2, xMAIR0Const                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    ldr r2, =0xe000edc0                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
             "    str r1, [r2]                                 \n" /* Program MAIR0. */
             "                                                 \n"
             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-            "    ldr r1, xRNRConst                            \n" /* r1 = 0xe000ed98 [Location of RNR]. */
-            "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    ldr r1, =0xe000ed98                          \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
             "                                                 \n"
             "    movs r3, #4                                  \n" /* r3 = 4. */
             "    str r3, [r1]                                 \n" /* Program RNR = 4. */
@@ -337,14 +322,14 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
                 "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
             #endif /* configTOTAL_MPU_REGIONS == 16 */
             "                                                 \n"
-            "   ldr r1, xMPUCTRLConst                         \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "   ldr r1, =0xe000ed94                           \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
             "   orr r2, #1                                    \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
             "   str r2, [r1]                                  \n" /* Enable MPU. */
             "   dsb                                           \n" /* Force memory writes before continuing. */
             "                                                 \n"
             " restore_context:                                \n"
-            "    ldr r2, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r2, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB.*/
             "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
             "                                                 \n"
@@ -369,13 +354,6 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             " restore_context_done:                           \n"
             "    str r1, [r0]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
             "    bx lr                                        \n"
-            "                                                 \n"
-            " .align 4                                        \n"
-            " pxCurrentTCBConst: .word pxCurrentTCB           \n"
-            " xMPUCTRLConst: .word 0xe000ed94                 \n"
-            " xMAIR0Const: .word 0xe000edc0                   \n"
-            " xRNRConst: .word 0xe000ed98                     \n"
-            " xRBARConst: .word 0xe000ed9c                    \n"
             ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
         );
     }
@@ -400,7 +378,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   mov r3, lr                                      \n" /* r3 = LR/EXC_RETURN. */
             "   stmdb r0!, {r2-r11}                             \n" /* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */
             "                                                   \n"
-            "   ldr r2, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r2, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr r1, [r2]                                    \n" /* Read pxCurrentTCB. */
             "   str r0, [r1]                                    \n" /* Save the new top of stack in TCB. */
             "                                                   \n"
@@ -412,7 +390,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   mov r0, #0                                      \n" /* r0 = 0. */
             "   msr basepri, r0                                 \n" /* Enable interrupts. */
             "                                                   \n"
-            "   ldr r2, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r2, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr r1, [r2]                                    \n" /* Read pxCurrentTCB. */
             "   ldr r0, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
             "                                                   \n"
@@ -427,9 +405,6 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   msr psplim, r2                                  \n" /* Restore the PSPLIM register value for the task. */
             "   msr psp, r0                                     \n" /* Remember the new top of stack for the task. */
             "   bx r3                                           \n"
-            "                                                   \n"
-            "   .align 4                                        \n"
-            "pxCurrentTCBConst: .word pxCurrentTCB              \n"
             ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
         );
     }
@@ -487,11 +462,8 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   ite eq                                          \n"
             "   mrseq r0, msp                                   \n"
             "   mrsne r0, psp                                   \n"
-            "   ldr r1, svchandler_address_const                \n"
+            "   ldr r1, =vPortSVCHandler_C                      \n"
             "   bx r1                                           \n"
-            "                                                   \n"
-            "   .align 4                                        \n"
-            "svchandler_address_const: .word vPortSVCHandler_C  \n"
         );
     }
 

From 2a014ce0b3647de41a41bc84754f86c73cef33ba Mon Sep 17 00:00:00 2001
From: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Date: Fri, 19 Apr 2024 12:39:36 +0800
Subject: [PATCH 263/424] Update submodule pointer (#1040)

---
 portable/ThirdParty/Community-Supported-Ports | 2 +-
 portable/ThirdParty/Partner-Supported-Ports   | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/portable/ThirdParty/Community-Supported-Ports b/portable/ThirdParty/Community-Supported-Ports
index f051e9bff..9c5bad7b2 160000
--- a/portable/ThirdParty/Community-Supported-Ports
+++ b/portable/ThirdParty/Community-Supported-Ports
@@ -1 +1 @@
-Subproject commit f051e9bff812aa3c10c5417e064671a1c4eeb314
+Subproject commit 9c5bad7b2f42b4e8420f12290b9bc085d3309e8b
diff --git a/portable/ThirdParty/Partner-Supported-Ports b/portable/ThirdParty/Partner-Supported-Ports
index da0185fbf..dc3afc6e8 160000
--- a/portable/ThirdParty/Partner-Supported-Ports
+++ b/portable/ThirdParty/Partner-Supported-Ports
@@ -1 +1 @@
-Subproject commit da0185fbf1215706af66d020a67edf912193979a
+Subproject commit dc3afc6e837426b4bda81bbb6cf45bfb6f34c7e9

From fdf4695c1ed6460b4f4c086ea0ccc7236554fb4a Mon Sep 17 00:00:00 2001
From: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Date: Fri, 19 Apr 2024 12:48:00 +0800
Subject: [PATCH 264/424] Adding SMP coverity example (#1039)

* Adding SMP coverity example

* Add coverity scan flow

* Fix format

* Update README.md

* Code review suggestions

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Ubuntu <ubuntu@ip-172-31-34-245.ap-northeast-1.compute.internal>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 .github/workflows/coverity_scan.yml | 39 +++++++++++++++++++++++++++++
 MISRA.md                            |  8 ++++++
 event_groups.c                      |  3 +++
 examples/coverity/CMakeLists.txt    |  6 +++++
 examples/coverity/README.md         |  9 ++++++-
 queue.c                             | 12 +++++++++
 stream_buffer.c                     | 15 +++++++++++
 tasks.c                             | 18 +++++++++++++
 8 files changed, 109 insertions(+), 1 deletion(-)

diff --git a/.github/workflows/coverity_scan.yml b/.github/workflows/coverity_scan.yml
index 14f5366b4..803a29ba8 100644
--- a/.github/workflows/coverity_scan.yml
+++ b/.github/workflows/coverity_scan.yml
@@ -86,3 +86,42 @@ jobs:
           echo "::endgroup::"
           echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }} "
           echo "${COV_SCAN_UPLOAD_STATUS}" | grep -q -e 'Build successfully submitted' || echo >&2 "Error submitting build for analysis: ${COV_SCAN_UPLOAD_STATUS}"
+
+      - env:
+            stepName: Coverity Build for SMP FreeRTOS
+            COVERITY_TOKEN: ${{ secrets.COVERITY_SCAN_TOKEN }}
+            COVERITY_EMAIL: ${{ secrets.COVERITY_SCAN_EMAIL }}
+        shell: bash
+        run: |
+            # ${{ env.stepName }}
+            echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}"
+  
+            export PATH="$PATH:${{env.cov_scan_path}}"
+            cmake -S ./examples/cmake_example/ -B build -DFREERTOS_SMP_EXAMPLE=1
+            cd build
+            cov-build --dir cov-int make -j
+            # Move the report out of the build directory
+            tar czvf ../gcc_freertos_kernel_smp_sample_build.tgz cov-int
+  
+            echo "::endgroup::"
+            echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }} "
+
+      - env:
+            stepName: Upload FreeRTOS SMP Coverity Report for Scan
+            COVERITY_TOKEN: ${{ secrets.COVERITY_SCAN_TOKEN }}
+            COVERITY_EMAIL: ${{ secrets.COVERITY_SCAN_EMAIL }}
+        shell: bash
+        run: |
+            # ${{ env.stepName }}
+            echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}"
+  
+            COV_SCAN_UPLOAD_STATUS=$(curl --form token=${COVERITY_TOKEN} \
+              --form email=${COVERITY_EMAIL} \
+              --form file=@gcc_freertos_kernel_smp_sample_build.tgz \
+              --form version="Mainline" \
+              --form description="FreeRTOS Kernel SMP Commit Scan" \
+              https://scan.coverity.com/builds?project=FreeRTOS-Kernel)
+  
+            echo "::endgroup::"
+            echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }} "
+            echo "${COV_SCAN_UPLOAD_STATUS}" | grep -q -e 'Build successfully submitted' || echo >&2 "Error submitting build for analysis: ${COV_SCAN_UPLOAD_STATUS}"
diff --git a/MISRA.md b/MISRA.md
index ee518bc2c..4355ec678 100644
--- a/MISRA.md
+++ b/MISRA.md
@@ -18,6 +18,14 @@ with ( Assuming rule 8.4 violation; with justification in point 1 ):
 grep 'MISRA Ref 8.4.1' . -rI
 ```
 
+#### Dir 4.7
+MISRA C:2012 Dir 4.7: If a function returns error information, then that error
+information shall be tested.
+
+_Ref 4.7.1_
+ - `taskENTER_CRITICAL_FROM_ISR` returns the interrupt mask and not any error
+    information. Therefore, there is no need test the return value.
+
 #### Rule 8.4
 
 MISRA C:2012 Rule 8.4: A compatible declaration shall be visible when an
diff --git a/event_groups.c b/event_groups.c
index 1c0b48760..f54a37a8f 100644
--- a/event_groups.c
+++ b/event_groups.c
@@ -529,6 +529,9 @@
 
         traceENTER_xEventGroupGetBitsFromISR( xEventGroup );
 
+        /* MISRA Ref 4.7.1 [Return value shall be checked] */
+        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
+        /* coverity[misra_c_2012_directive_4_7_violation] */
         uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
         {
             uxReturn = pxEventBits->uxEventBits;
diff --git a/examples/coverity/CMakeLists.txt b/examples/coverity/CMakeLists.txt
index 00332b5ac..3c0f4e452 100644
--- a/examples/coverity/CMakeLists.txt
+++ b/examples/coverity/CMakeLists.txt
@@ -23,6 +23,12 @@ target_include_directories(freertos_config
                            INTERFACE
                            ./)
 
+if (DEFINED FREERTOS_SMP_EXAMPLE AND FREERTOS_SMP_EXAMPLE STREQUAL "1")
+    message(STATUS "Build FreeRTOS SMP example")
+    # Adding the following configurations to build SMP template port
+    add_compile_options( -DconfigNUMBER_OF_CORES=2 -DconfigUSE_PASSIVE_IDLE_HOOK=0 )
+endif()
+
 # Select the heap. Values between 1-5 will pick a heap.
 set(FREERTOS_HEAP "3" CACHE STRING "" FORCE)
 
diff --git a/examples/coverity/README.md b/examples/coverity/README.md
index 6055e7133..967f33dca 100644
--- a/examples/coverity/README.md
+++ b/examples/coverity/README.md
@@ -34,9 +34,16 @@ commands in a terminal:
   cov-configure --force --compiler cc --comptype gcc
   ~~~
 2. Create the build files using CMake in a `build` directory:
+
+Singe core FreeRTOS:
   ~~~
   cmake -B build -S examples/coverity
   ~~~
+
+SMP FreeRTOS:
+  ~~~
+  cmake -B build -S examples/coverity -DFREERTOS_SMP_EXAMPLE=1
+  ~~~
 3. Build the (pseudo) application:
   ~~~
   cd build/
@@ -47,7 +54,7 @@ commands in a terminal:
   ~~~
   cov-analyze --dir ./cov-out \
     --coding-standard-config ../examples/coverity/coverity_misra.config \
-    --tu-pattern "file('[A-Za-z_]+\.c')"
+    --tu-pattern "file('[A-Za-z_]+\.c') && ( ! file('main.c') ) && ( ! file('port.c') )"
   ~~~
 5. Generate the HTML report:
   ~~~
diff --git a/queue.c b/queue.c
index b3029c19d..dd302c908 100644
--- a/queue.c
+++ b/queue.c
@@ -1190,6 +1190,9 @@ BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue,
      * read, instead return a flag to say whether a context switch is required or
      * not (i.e. has a task with a higher priority than us been woken by this
      * post). */
+    /* MISRA Ref 4.7.1 [Return value shall be checked] */
+    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
+    /* coverity[misra_c_2012_directive_4_7_violation] */
     uxSavedInterruptStatus = ( UBaseType_t ) taskENTER_CRITICAL_FROM_ISR();
     {
         if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
@@ -1365,6 +1368,9 @@ BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue,
      * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
     portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
 
+    /* MISRA Ref 4.7.1 [Return value shall be checked] */
+    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
+    /* coverity[misra_c_2012_directive_4_7_violation] */
     uxSavedInterruptStatus = ( UBaseType_t ) taskENTER_CRITICAL_FROM_ISR();
     {
         const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
@@ -2055,6 +2061,9 @@ BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue,
      * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
     portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
 
+    /* MISRA Ref 4.7.1 [Return value shall be checked] */
+    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
+    /* coverity[misra_c_2012_directive_4_7_violation] */
     uxSavedInterruptStatus = ( UBaseType_t ) taskENTER_CRITICAL_FROM_ISR();
     {
         const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
@@ -2153,6 +2162,9 @@ BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue,
      * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
     portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
 
+    /* MISRA Ref 4.7.1 [Return value shall be checked] */
+    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
+    /* coverity[misra_c_2012_directive_4_7_violation] */
     uxSavedInterruptStatus = ( UBaseType_t ) taskENTER_CRITICAL_FROM_ISR();
     {
         /* Cannot block in an ISR, so check there is data available. */
diff --git a/stream_buffer.c b/stream_buffer.c
index 4471b4f3c..aeca81a4a 100644
--- a/stream_buffer.c
+++ b/stream_buffer.c
@@ -676,6 +676,9 @@ BaseType_t xStreamBufferResetFromISR( StreamBufferHandle_t xStreamBuffer )
     #endif
 
     /* Can only reset a message buffer if there are no tasks blocked on it. */
+    /* MISRA Ref 4.7.1 [Return value shall be checked] */
+    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
+    /* coverity[misra_c_2012_directive_4_7_violation] */
     uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
     {
         if( ( pxStreamBuffer->xTaskWaitingToReceive == NULL ) && ( pxStreamBuffer->xTaskWaitingToSend == NULL ) )
@@ -972,6 +975,9 @@ size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
         /* Was a task waiting for the data? */
         if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes )
         {
+            /* MISRA Ref 4.7.1 [Return value shall be checked] */
+            /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
+            /* coverity[misra_c_2012_directive_4_7_violation] */
             prvSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken );
         }
         else
@@ -1245,6 +1251,9 @@ size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
         /* Was a task waiting for space in the buffer? */
         if( xReceivedLength != ( size_t ) 0 )
         {
+            /* MISRA Ref 4.7.1 [Return value shall be checked] */
+            /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
+            /* coverity[misra_c_2012_directive_4_7_violation] */
             prvRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken );
         }
         else
@@ -1397,6 +1406,9 @@ BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer
 
     configASSERT( pxStreamBuffer );
 
+    /* MISRA Ref 4.7.1 [Return value shall be checked] */
+    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
+    /* coverity[misra_c_2012_directive_4_7_violation] */
     uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
     {
         if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )
@@ -1433,6 +1445,9 @@ BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuf
 
     configASSERT( pxStreamBuffer );
 
+    /* MISRA Ref 4.7.1 [Return value shall be checked] */
+    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
+    /* coverity[misra_c_2012_directive_4_7_violation] */
     uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
     {
         if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )
diff --git a/tasks.c b/tasks.c
index 7f808cc4f..8d2daf736 100644
--- a/tasks.c
+++ b/tasks.c
@@ -2666,6 +2666,9 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
          * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
         portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
 
+        /* MISRA Ref 4.7.1 [Return value shall be checked] */
+        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
+        /* coverity[misra_c_2012_directive_4_7_violation] */
         uxSavedInterruptStatus = ( UBaseType_t ) taskENTER_CRITICAL_FROM_ISR();
         {
             /* If null is passed in here then it is the priority of the calling
@@ -2737,6 +2740,9 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
          * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
         portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
 
+        /* MISRA Ref 4.7.1 [Return value shall be checked] */
+        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
+        /* coverity[misra_c_2012_directive_4_7_violation] */
         uxSavedInterruptStatus = ( UBaseType_t ) taskENTER_CRITICAL_FROM_ISR();
         {
             /* If null is passed in here then it is the base priority of the calling
@@ -3433,6 +3439,9 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
          * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
         portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
 
+        /* MISRA Ref 4.7.1 [Return value shall be checked] */
+        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
+        /* coverity[misra_c_2012_directive_4_7_violation] */
         uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
         {
             if( prvTaskIsTaskSuspended( pxTCB ) != pdFALSE )
@@ -4989,6 +4998,9 @@ BaseType_t xTaskIncrementTick( void )
 
         /* Save the hook function in the TCB.  A critical section is required as
          * the value can be accessed from an interrupt. */
+        /* MISRA Ref 4.7.1 [Return value shall be checked] */
+        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
+        /* coverity[misra_c_2012_directive_4_7_violation] */
         uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
         {
             xReturn = pxTCB->pxTaskTag;
@@ -7974,6 +7986,9 @@ TickType_t uxTaskResetEventItemValue( void )
 
         pxTCB = xTaskToNotify;
 
+        /* MISRA Ref 4.7.1 [Return value shall be checked] */
+        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
+        /* coverity[misra_c_2012_directive_4_7_violation] */
         uxSavedInterruptStatus = ( UBaseType_t ) taskENTER_CRITICAL_FROM_ISR();
         {
             if( pulPreviousNotificationValue != NULL )
@@ -8133,6 +8148,9 @@ TickType_t uxTaskResetEventItemValue( void )
 
         pxTCB = xTaskToNotify;
 
+        /* MISRA Ref 4.7.1 [Return value shall be checked] */
+        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
+        /* coverity[misra_c_2012_directive_4_7_violation] */
         uxSavedInterruptStatus = ( UBaseType_t ) taskENTER_CRITICAL_FROM_ISR();
         {
             ucOriginalNotifyState = pxTCB->ucNotifyState[ uxIndexToNotify ];

From c02a347880a912ebd479228beb599f4d67a5cf8d Mon Sep 17 00:00:00 2001
From: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Date: Fri, 19 Apr 2024 17:11:16 +0800
Subject: [PATCH 265/424] Use suffix "U" for unsigned constant (#1041)

* Fix the constant suffix to U

* Fix more unsigned contant suffix

---------

Co-authored-by: Ubuntu <ubuntu@ip-172-31-34-245.ap-northeast-1.compute.internal>
---
 include/event_groups.h        | 24 ++++++++++++------------
 include/queue.h               |  8 ++++----
 include/task.h                | 26 +++++++++++++-------------
 portable/template/portmacro.h |  6 +++---
 tasks.c                       | 30 +++++++++++++++---------------
 5 files changed, 47 insertions(+), 47 deletions(-)

diff --git a/include/event_groups.h b/include/event_groups.h
index 09a5ab53a..1461a1113 100644
--- a/include/event_groups.h
+++ b/include/event_groups.h
@@ -40,20 +40,20 @@
  * item value.  It is important they don't clash with the
  * taskEVENT_LIST_ITEM_VALUE_IN_USE definition. */
 #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    #define eventCLEAR_EVENTS_ON_EXIT_BIT    ( ( uint16_t ) 0x0100 )
-    #define eventUNBLOCKED_DUE_TO_BIT_SET    ( ( uint16_t ) 0x0200 )
-    #define eventWAIT_FOR_ALL_BITS           ( ( uint16_t ) 0x0400 )
-    #define eventEVENT_BITS_CONTROL_BYTES    ( ( uint16_t ) 0xff00 )
+    #define eventCLEAR_EVENTS_ON_EXIT_BIT    ( ( uint16_t ) 0x0100U )
+    #define eventUNBLOCKED_DUE_TO_BIT_SET    ( ( uint16_t ) 0x0200U )
+    #define eventWAIT_FOR_ALL_BITS           ( ( uint16_t ) 0x0400U )
+    #define eventEVENT_BITS_CONTROL_BYTES    ( ( uint16_t ) 0xff00U )
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    #define eventCLEAR_EVENTS_ON_EXIT_BIT    ( ( uint32_t ) 0x01000000 )
-    #define eventUNBLOCKED_DUE_TO_BIT_SET    ( ( uint32_t ) 0x02000000 )
-    #define eventWAIT_FOR_ALL_BITS           ( ( uint32_t ) 0x04000000 )
-    #define eventEVENT_BITS_CONTROL_BYTES    ( ( uint32_t ) 0xff000000 )
+    #define eventCLEAR_EVENTS_ON_EXIT_BIT    ( ( uint32_t ) 0x01000000U )
+    #define eventUNBLOCKED_DUE_TO_BIT_SET    ( ( uint32_t ) 0x02000000U )
+    #define eventWAIT_FOR_ALL_BITS           ( ( uint32_t ) 0x04000000U )
+    #define eventEVENT_BITS_CONTROL_BYTES    ( ( uint32_t ) 0xff000000U )
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_64_BITS )
-    #define eventCLEAR_EVENTS_ON_EXIT_BIT    ( ( uint64_t ) 0x0100000000000000 )
-    #define eventUNBLOCKED_DUE_TO_BIT_SET    ( ( uint64_t ) 0x0200000000000000 )
-    #define eventWAIT_FOR_ALL_BITS           ( ( uint64_t ) 0x0400000000000000 )
-    #define eventEVENT_BITS_CONTROL_BYTES    ( ( uint64_t ) 0xff00000000000000 )
+    #define eventCLEAR_EVENTS_ON_EXIT_BIT    ( ( uint64_t ) 0x0100000000000000U )
+    #define eventUNBLOCKED_DUE_TO_BIT_SET    ( ( uint64_t ) 0x0200000000000000U )
+    #define eventWAIT_FOR_ALL_BITS           ( ( uint64_t ) 0x0400000000000000U )
+    #define eventEVENT_BITS_CONTROL_BYTES    ( ( uint64_t ) 0xff00000000000000U )
 #endif /* if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) */
 
 /* *INDENT-OFF* */
diff --git a/include/queue.h b/include/queue.h
index a2cd3ffe9..5704ea768 100644
--- a/include/queue.h
+++ b/include/queue.h
@@ -302,7 +302,7 @@ typedef struct QueueDefinition   * QueueSetMemberHandle_t;
  *  char ucData[ 20 ];
  * } xMessage;
  *
- * uint32_t ulVar = 10UL;
+ * uint32_t ulVar = 10U;
  *
  * void vATask( void *pvParameters )
  * {
@@ -385,7 +385,7 @@ typedef struct QueueDefinition   * QueueSetMemberHandle_t;
  *  char ucData[ 20 ];
  * } xMessage;
  *
- * uint32_t ulVar = 10UL;
+ * uint32_t ulVar = 10U;
  *
  * void vATask( void *pvParameters )
  * {
@@ -470,7 +470,7 @@ typedef struct QueueDefinition   * QueueSetMemberHandle_t;
  *  char ucData[ 20 ];
  * } xMessage;
  *
- * uint32_t ulVar = 10UL;
+ * uint32_t ulVar = 10U;
  *
  * void vATask( void *pvParameters )
  * {
@@ -643,7 +643,7 @@ typedef struct QueueDefinition   * QueueSetMemberHandle_t;
  *  char ucData[ 20 ];
  * } xMessage;
  *
- * uint32_t ulVar = 10UL;
+ * uint32_t ulVar = 10U;
  *
  * void vATask( void *pvParameters )
  * {
diff --git a/include/task.h b/include/task.h
index f98d84cf2..6193e58e0 100644
--- a/include/task.h
+++ b/include/task.h
@@ -60,16 +60,16 @@
 
 /* MPU region parameters passed in ulParameters
  * of MemoryRegion_t struct. */
-#define tskMPU_REGION_READ_ONLY        ( 1UL << 0UL )
-#define tskMPU_REGION_READ_WRITE       ( 1UL << 1UL )
-#define tskMPU_REGION_EXECUTE_NEVER    ( 1UL << 2UL )
-#define tskMPU_REGION_NORMAL_MEMORY    ( 1UL << 3UL )
-#define tskMPU_REGION_DEVICE_MEMORY    ( 1UL << 4UL )
+#define tskMPU_REGION_READ_ONLY        ( 1U << 0U )
+#define tskMPU_REGION_READ_WRITE       ( 1U << 1U )
+#define tskMPU_REGION_EXECUTE_NEVER    ( 1U << 2U )
+#define tskMPU_REGION_NORMAL_MEMORY    ( 1U << 3U )
+#define tskMPU_REGION_DEVICE_MEMORY    ( 1U << 4U )
 
 /* MPU region permissions stored in MPU settings to
  * authorize access requests. */
-#define tskMPU_READ_PERMISSION         ( 1UL << 0UL )
-#define tskMPU_WRITE_PERMISSION        ( 1UL << 1UL )
+#define tskMPU_READ_PERMISSION         ( 1U << 0U )
+#define tskMPU_WRITE_PERMISSION        ( 1U << 1U )
 
 /* The direct to task notification feature used to have only a single notification
  * per task.  Now there is an array of notifications per task that is dimensioned by
@@ -473,7 +473,7 @@ typedef enum
  *  {
  *      // The parameter value is expected to be 1 as 1 is passed in the
  *      // pvParameters value in the call to xTaskCreateStatic().
- *      configASSERT( ( uint32_t ) pvParameters == 1UL );
+ *      configASSERT( ( uint32_t ) pvParameters == 1U );
  *
  *      for( ;; )
  *      {
@@ -564,7 +564,7 @@ typedef enum
  *  "ATask",    // pcName - just a text name for the task to assist debugging.
  *  100,        // uxStackDepth - the stack size DEFINED IN WORDS.
  *  NULL,       // pvParameters - passed into the task function as the function parameters.
- *  ( 1UL | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.
+ *  ( 1U | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.
  *  cStackBuffer,// puxStackBuffer - the buffer to be used as the task stack.
  *
  *  // xRegions - Allocate up to three separate memory regions for access by
@@ -658,7 +658,7 @@ typedef enum
  *  "ATask",    // pcName - just a text name for the task to assist debugging.
  *  100,        // uxStackDepth - the stack size DEFINED IN WORDS.
  *  NULL,       // pvParameters - passed into the task function as the function parameters.
- *  ( 1UL | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.
+ *  ( 1U | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.
  *  cStackBuffer,// puxStackBuffer - the buffer to be used as the task stack.
  *
  *  // xRegions - Allocate up to three separate memory regions for access by
@@ -2139,7 +2139,7 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION;
  *          uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalRunTime );
  *
  *          // For percentage calculations.
- *          ulTotalRunTime /= 100UL;
+ *          ulTotalRunTime /= 100U;
  *
  *          // Avoid divide by zero errors.
  *          if( ulTotalRunTime > 0 )
@@ -2153,7 +2153,7 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION;
  *                  // ulTotalRunTimeDiv100 has already been divided by 100.
  *                  ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalRunTime;
  *
- *                  if( ulStatsAsPercentage > 0UL )
+ *                  if( ulStatsAsPercentage > 0U )
  *                  {
  *                      sprintf( pcWriteBuffer, "%s\t\t%lu\t\t%lu%%\r\n", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage );
  *                  }
@@ -2863,7 +2863,7 @@ BaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify,
  * will be cleared in the calling task's notification value before the task
  * checks to see if any notifications are pending, and optionally blocks if no
  * notifications are pending.  Setting ulBitsToClearOnEntry to ULONG_MAX (if
- * limits.h is included) or 0xffffffffUL (if limits.h is not included) will have
+ * limits.h is included) or 0xffffffffU (if limits.h is not included) will have
  * the effect of resetting the task's notification value to 0.  Setting
  * ulBitsToClearOnEntry to 0 will leave the task's notification value unchanged.
  *
diff --git a/portable/template/portmacro.h b/portable/template/portmacro.h
index 3b5da0dd2..90668043c 100644
--- a/portable/template/portmacro.h
+++ b/portable/template/portmacro.h
@@ -34,13 +34,13 @@ typedef unsigned char    UBaseType_t;
 
 #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
     typedef uint16_t     TickType_t;
-    #define portMAX_DELAY    ( TickType_t ) 0xffff
+    #define portMAX_DELAY    ( TickType_t ) 0xffffU
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
     typedef uint32_t     TickType_t;
-    #define portMAX_DELAY    ( TickType_t ) 0xffffffffUL
+    #define portMAX_DELAY    ( TickType_t ) 0xffffffffU
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_64_BITS )
     typedef uint64_t     TickType_t;
-    #define portMAX_DELAY    ( TickType_t ) 0xffffffffffffffff
+    #define portMAX_DELAY    ( TickType_t ) 0xffffffffffffffffU
 #else
     #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
 #endif
diff --git a/tasks.c b/tasks.c
index 8d2daf736..3423becd4 100644
--- a/tasks.c
+++ b/tasks.c
@@ -291,11 +291,11 @@
  * responsibility of whichever module is using the value to ensure it gets set back
  * to its original value when it is released. */
 #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    #define taskEVENT_LIST_ITEM_VALUE_IN_USE    ( ( uint16_t ) 0x8000 )
+    #define taskEVENT_LIST_ITEM_VALUE_IN_USE    ( ( uint16_t ) 0x8000U )
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    #define taskEVENT_LIST_ITEM_VALUE_IN_USE    ( ( uint32_t ) 0x80000000 )
+    #define taskEVENT_LIST_ITEM_VALUE_IN_USE    ( ( uint32_t ) 0x80000000U )
 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_64_BITS )
-    #define taskEVENT_LIST_ITEM_VALUE_IN_USE    ( ( uint64_t ) 0x8000000000000000 )
+    #define taskEVENT_LIST_ITEM_VALUE_IN_USE    ( ( uint64_t ) 0x8000000000000000U )
 #endif
 
 /* Indicates that the task is not actively running on any core. */
@@ -314,7 +314,7 @@
 #endif
 
 /* Indicates that the task is an Idle task. */
-#define taskATTRIBUTE_IS_IDLE    ( UBaseType_t ) ( 1UL << 0UL )
+#define taskATTRIBUTE_IS_IDLE    ( UBaseType_t ) ( 1U << 0U )
 
 #if ( ( configNUMBER_OF_CORES > 1 ) && ( portCRITICAL_NESTING_IN_TCB == 1 ) )
     #define portGET_CRITICAL_NESTING_COUNT()          ( pxCurrentTCBs[ portGET_CORE_ID() ]->uxCriticalNesting )
@@ -1835,7 +1835,7 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
         pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) );
 
         /* Check the alignment of the calculated top of stack is correct. */
-        configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
+        configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0U ) );
 
         #if ( configRECORD_STACK_HIGH_ADDRESS == 1 )
         {
@@ -1851,7 +1851,7 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
         pxTopOfStack = ( StackType_t * ) ( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) + portBYTE_ALIGNMENT_MASK ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) );
 
         /* Check the alignment of the calculated top of stack is correct. */
-        configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
+        configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0U ) );
 
         /* The other extreme of the stack space is required if stack checking is
          * performed. */
@@ -2891,7 +2891,7 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
 
                 /* Only reset the event list item value if the value is not
                  * being used for anything else. */
-                if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == ( ( TickType_t ) 0UL ) )
+                if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == ( ( TickType_t ) 0U ) )
                 {
                     listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxNewPriority ) );
                 }
@@ -6596,7 +6596,7 @@ static void prvResetNextTaskUnblockTime( void )
                 /* Adjust the mutex holder state to account for its new
                  * priority.  Only reset the event list item value if the value is
                  * not being used for anything else. */
-                if( ( listGET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == ( ( TickType_t ) 0UL ) )
+                if( ( listGET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == ( ( TickType_t ) 0U ) )
                 {
                     listSET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority );
                 }
@@ -6825,7 +6825,7 @@ static void prvResetNextTaskUnblockTime( void )
 
                     /* Only reset the event list item value if the value is not
                      * being used for anything else. */
-                    if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == ( ( TickType_t ) 0UL ) )
+                    if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == ( ( TickType_t ) 0U ) )
                     {
                         listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriorityToUse );
                     }
@@ -7440,10 +7440,10 @@ static void prvResetNextTaskUnblockTime( void )
             uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalTime );
 
             /* For percentage calculations. */
-            ulTotalTime /= ( ( configRUN_TIME_COUNTER_TYPE ) 100UL );
+            ulTotalTime /= ( ( configRUN_TIME_COUNTER_TYPE ) 100U );
 
             /* Avoid divide by zero errors. */
-            if( ulTotalTime > 0UL )
+            if( ulTotalTime > 0U )
             {
                 /* Create a human readable table from the binary data. */
                 for( x = 0; x < uxArraySize; x++ )
@@ -7469,7 +7469,7 @@ static void prvResetNextTaskUnblockTime( void )
                          * character. */
                         if( uxConsumedBufferLength < ( uxBufferLength - 1U ) )
                         {
-                            if( ulStatsAsPercentage > 0UL )
+                            if( ulStatsAsPercentage > 0U )
                             {
                                 #ifdef portLU_PRINTF_SPECIFIER_REQUIRED
                                 {
@@ -7633,7 +7633,7 @@ TickType_t uxTaskResetEventItemValue( void )
             taskENTER_CRITICAL();
             {
                 /* Only block if the notification count is not already non-zero. */
-                if( pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ] == 0UL )
+                if( pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ] == 0U )
                 {
                     /* Mark this task as waiting for a notification. */
                     pxCurrentTCB->ucNotifyState[ uxIndexToWaitOn ] = taskWAITING_NOTIFICATION;
@@ -7684,11 +7684,11 @@ TickType_t uxTaskResetEventItemValue( void )
             traceTASK_NOTIFY_TAKE( uxIndexToWaitOn );
             ulReturn = pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ];
 
-            if( ulReturn != 0UL )
+            if( ulReturn != 0U )
             {
                 if( xClearCountOnExit != pdFALSE )
                 {
-                    pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ] = ( uint32_t ) 0UL;
+                    pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ] = ( uint32_t ) 0U;
                 }
                 else
                 {

From 111e7750606f25321c849e94888fcfa7be92896f Mon Sep 17 00:00:00 2001
From: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Date: Mon, 22 Apr 2024 15:35:18 +0800
Subject: [PATCH 266/424] Update History.txt for V11.1.0 (#1042)

---
 History.txt | 78 +++++++++++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 76 insertions(+), 2 deletions(-)

diff --git a/History.txt b/History.txt
index 9feeb050a..d5293b90b 100644
--- a/History.txt
+++ b/History.txt
@@ -1,7 +1,81 @@
 Documentation and download available at https://www.FreeRTOS.org/
 
-	+ Update all the APIs to use configSTACK_DEPTH_TYPE for stack type. If left
-	  undefined, configSTACK_DEPTH_TYPE defaults to StackType_t.
+Changes between FreeRTOS V11.0.1 and FreeRTOS V11.1.0 released April 22, 2024
+
+    + Add ARMv7-R port with Memory Protection Unit (MPU) support.
+    + Add Memory Protection Unit (MPU) support to the Cortex-M0 port.
+    + Add stream batching buffer. A stream batching buffer differs from a stream
+      buffer when a task reads from a non-empty buffer:
+      - The task reading from a non-empty stream buffer returns immediately
+        regardless of the amount of data in the buffer.
+      - The task reading from a non-empty steam batching buffer blocks until the
+        amount of data in the buffer exceeds the trigger level or the block time
+        expires.
+      We thank @cperkulator for their contribution.
+    + Add the ability to change task notification index for stream buffers. We
+      thank @glemco for their contribution.
+    + Add xStreamBufferResetFromISR and xMessageBufferResetFromISR APIs to reset
+      stream buffer and message buffer from an Interrupt Service Routine (ISR).
+      We thank @HagaiMoshe for their contribution.
+    + Update all the FreeRTOS APIs to use configSTACK_DEPTH_TYPE for stack type.
+      We thank @feilipu for their contribution.
+    + Update vTaskEndScheduler to delete the timer and idle tasks,
+      once the scheduler is stopped.
+    + Make xTaskGetCurrentTaskHandleForCore() available to the single core
+      scheduler. We thank @Dazza0 for their contribution.
+    + Update uxTaskGetSystemState to not use the pxIndex member of the List_t
+      structure while iterating ready tasks list. The reason is that pxIndex
+      member must only used to select next ready task to run. We thank
+      @gemarcano for their inputs.
+    + Add a config option to the FreeRTOS SMP Kernel to set the default core
+      affinity mask for tasks created without an affinity mask. We thank @go2sh
+      for their contribution.
+    + Add configUSE_EVENT_GROUPS and configUSE_STREAM_BUFFERS configuration
+      constants to control the inclusion of event group and stream buffer
+      functionalities.
+    + Code changes to comply with MISRA C 2012.
+    + Add 64-bit support to the FreeRTOS Windows Simulator port. We thank @watsk
+      and @josesimoes for their contributions.
+    + Add support for 64-bit Microblaze processor to the MicroblazeV9 port. We
+      thank @mubinsyed for their contribution.
+    + Add support for MSP430 Embedded Application Binary Interface (EABI) to
+      the MSP430F449 port to make it work with both MSP430 GCC and MSPGCC
+      compilers. We thank @Forty-Bot for their contribution.
+    + Update xPortIsAuthorizedToAccessBuffer() on FreeRTOS ports with MPU
+      support to grant an unprivileged task access to all the memory before the
+      scheduler is started.
+    + Update the POSIX port to pass the FreeRTOS task name to pthread for
+      readable output in debuggers. We thank @Mixaill for their contribution.
+    + Update the POSIX port to ignore the user specified stack memory and only
+      pass the stack size to the pthread API to avoid errors caused when stack size
+      is smaller than the minimum. We thank @cmorgnaBE for their
+      contribution.
+    + Update the POSIX port to use a timer thread for tick interrupts instead of
+      POSIX timers to address issues with signal handling in non-FreeRTOS
+      pthreads. We thank @cmorgnaBE for their contribution.
+    + Update ARM_TFM port to support TF-Mv2.0.0 release of trusted-firmware-m.
+      We thanks @urutva for their contribution.
+    + Remove redundant constant pools in ARMv8 ports. We thank @urutva for their
+      contribution.
+    + Add APIs to reset the internal state of kernel modules. These APIs are
+      primarily intended to be used in the testing frameworks that restart the
+      scheduler.
+    + Use kernel provided implementations of vApplicationGetIdleTaskMemory() and
+      vApplicationGetTimerTaskMemory() in the RP2040 port. We thank @dpslwk for
+      their contribution.
+    + Fix atomic enter/exit critical section macro definitions in atomic.h for
+      ports that support nested interrupts. We thank @sebunger for their
+      contribution.
+    + Fix compiler warnings in the MSP430F449 port when compiled with the
+      MSP430 GCC compiler. We thank @Forty-Bot for their contribution.
+    + Update the scheduler suspension usage in ulTaskGenericNotifyTake and
+      xTaskGenericNotifyWait() to enhance code readability. We thank @Dazza0 for
+      their contribution.
+    + Add support for latest version of MPU wrappers( mpu_wrappers_v2) in CMake.
+      We thank @IsaacDynamo for their contribution.
+    + Update CMake support to create only one static library containing both the
+      kernel common code and the kernel port code. We thank @barnatahmed for
+      their contribution.
 
 Changes between FreeRTOS V11.0.0 and FreeRTOS V11.0.1 released December 21, 2023
 

From 8e07366994f81354a2d4556ca1da9f73dab781e6 Mon Sep 17 00:00:00 2001
From: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Date: Mon, 22 Apr 2024 17:48:45 +0800
Subject: [PATCH 267/424] Update kernel version v11.1.0+ in tasks.h (#1043)

---
 include/task.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/include/task.h b/include/task.h
index 6193e58e0..b638bddd2 100644
--- a/include/task.h
+++ b/include/task.h
@@ -53,10 +53,10 @@
  * The tskKERNEL_VERSION_MAJOR, tskKERNEL_VERSION_MINOR, tskKERNEL_VERSION_BUILD
  * values will reflect the last released version number.
  */
-#define tskKERNEL_VERSION_NUMBER       "V11.0.1+"
+#define tskKERNEL_VERSION_NUMBER       "V11.1.0+"
 #define tskKERNEL_VERSION_MAJOR        11
-#define tskKERNEL_VERSION_MINOR        0
-#define tskKERNEL_VERSION_BUILD        1
+#define tskKERNEL_VERSION_MINOR        1
+#define tskKERNEL_VERSION_BUILD        0
 
 /* MPU region parameters passed in ulParameters
  * of MemoryRegion_t struct. */

From 30afc1a2c05157fcac1a46dc773b0125bd680b82 Mon Sep 17 00:00:00 2001
From: 0mhu <mario.huettel@gmx.net>
Date: Mon, 29 Apr 2024 17:21:35 +0200
Subject: [PATCH 268/424] Fix wrong source file list in CMake of GCC_ARM_CM0
 port. (#1045)

Add GCC/ARM_CM0/mpu_wrappers_v2_asm.c and GCC/ARM_CM0/portasm.c as source files to 'freertos_kernel_port' library.
This fixes the FREERTOS_PORT "GCC_ARM_CM0" CMake configuration.
---
 portable/CMakeLists.txt | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/portable/CMakeLists.txt b/portable/CMakeLists.txt
index af9321e9f..819e2c116 100644
--- a/portable/CMakeLists.txt
+++ b/portable/CMakeLists.txt
@@ -77,7 +77,9 @@ add_library(freertos_kernel_port OBJECT
 
     # ARMv6-M port for GCC
     $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM0>:
-        GCC/ARM_CM0/port.c>
+        GCC/ARM_CM0/port.c
+        GCC/ARM_CM0/portasm.c
+        GCC/ARM_CM0/mpu_wrappers_v2_asm.c>
 
     # ARMv6-M / Cortex-M0 Raspberry PI RP2040 port for GCC
     $<$<STREQUAL:${FREERTOS_PORT},GCC_RP2040>:

From 2eb2d653bff44addcc03ee8f72b2d3bdc33a787f Mon Sep 17 00:00:00 2001
From: Holden <68555040+HTRamsey@users.noreply.github.com>
Date: Mon, 6 May 2024 17:24:05 -0700
Subject: [PATCH 269/424] Move header includes before extern c (#1047)

---
 include/FreeRTOS.h | 12 ++++++------
 include/portable.h |  4 ++--
 include/queue.h    |  4 ++--
 3 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/include/FreeRTOS.h b/include/FreeRTOS.h
index f7a59a765..b972ffd10 100644
--- a/include/FreeRTOS.h
+++ b/include/FreeRTOS.h
@@ -49,12 +49,6 @@
  */
 #include <stdint.h> /* READ COMMENT ABOVE. */
 
-/* *INDENT-OFF* */
-#ifdef __cplusplus
-    extern "C" {
-#endif
-/* *INDENT-ON* */
-
 /* Acceptable values for configTICK_TYPE_WIDTH_IN_BITS. */
 #define TICK_TYPE_WIDTH_16_BITS    0
 #define TICK_TYPE_WIDTH_32_BITS    1
@@ -129,6 +123,12 @@
 
 #endif /* if ( configUSE_PICOLIBC_TLS == 1 ) */
 
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    extern "C" {
+#endif
+/* *INDENT-ON* */
+
 #ifndef configUSE_C_RUNTIME_TLS_SUPPORT
     #define configUSE_C_RUNTIME_TLS_SUPPORT    0
 #endif
diff --git a/include/portable.h b/include/portable.h
index a20a3daa3..f7afb6979 100644
--- a/include/portable.h
+++ b/include/portable.h
@@ -94,14 +94,14 @@
     #define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP    0
 #endif
 
+#include "mpu_wrappers.h"
+
 /* *INDENT-OFF* */
 #ifdef __cplusplus
     extern "C" {
 #endif
 /* *INDENT-ON* */
 
-#include "mpu_wrappers.h"
-
 /*
  * Setup the stack of a new task so it is ready to be placed under the
  * scheduler control.  The registers have to be placed on the stack in
diff --git a/include/queue.h b/include/queue.h
index 5704ea768..1e56c35f1 100644
--- a/include/queue.h
+++ b/include/queue.h
@@ -34,14 +34,14 @@
     #error "include FreeRTOS.h" must appear in source files before "include queue.h"
 #endif
 
+#include "task.h"
+
 /* *INDENT-OFF* */
 #ifdef __cplusplus
     extern "C" {
 #endif
 /* *INDENT-ON* */
 
-#include "task.h"
-
 /**
  * Type by which queues are referenced.  For example, a call to xQueueCreate()
  * returns an QueueHandle_t variable that can then be used as a parameter to

From 78c8bbde0e7cbcca40ba3ed97ea1fd2b34e255be Mon Sep 17 00:00:00 2001
From: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Date: Tue, 7 May 2024 20:47:14 +0530
Subject: [PATCH 270/424] Update xPortRunning before resuming first task
 (#1049)

The variable `xPortRunning` is now updated before starting the first
task.

It fixes the following issue -
https://forums.freertos.org/t/possible-bug-in-the-way-prvtimertask-thread-function-is-started-in-win32-port/19959/

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 portable/MSVC-MingW/port.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/portable/MSVC-MingW/port.c b/portable/MSVC-MingW/port.c
index d489746f5..66c9a53ea 100644
--- a/portable/MSVC-MingW/port.c
+++ b/portable/MSVC-MingW/port.c
@@ -353,12 +353,12 @@ BaseType_t xPortStartScheduler( void )
         pxThreadState = ( ThreadState_t * ) *( ( size_t * ) pxCurrentTCB );
         ulCriticalNesting = portNO_CRITICAL_NESTING;
 
-        /* Start the first task. */
-        ResumeThread( pxThreadState->pvThread );
-
         /* The scheduler is now running. */
         xPortRunning = pdTRUE;
 
+        /* Start the first task. */
+        ResumeThread( pxThreadState->pvThread );
+
         /* Handle all simulated interrupts - including yield requests and
          * simulated ticks. */
         prvProcessSimulatedInterrupts();

From 067d04e44e00f9970f43a44d3325f0c4e035523e Mon Sep 17 00:00:00 2001
From: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Date: Wed, 8 May 2024 14:33:11 +0800
Subject: [PATCH 271/424] Add vPortGenerateSimulatedInterruptFromWindowsThread
 in MSVC port (#1044)

Add vPortGenerateSimulatedInterruptFromWindowsThread  in MSVC port
to enable native windows threads to notify FreeRTOS tasks.
---
 portable/MSVC-MingW/port.c      | 49 ++++++++++++++++++---------------
 portable/MSVC-MingW/portmacro.h | 13 +++++++--
 2 files changed, 38 insertions(+), 24 deletions(-)

diff --git a/portable/MSVC-MingW/port.c b/portable/MSVC-MingW/port.c
index 66c9a53ea..8b8289b8f 100644
--- a/portable/MSVC-MingW/port.c
+++ b/portable/MSVC-MingW/port.c
@@ -177,28 +177,7 @@ static DWORD WINAPI prvSimulatedPeripheralTimer( LPVOID lpParameter )
             Sleep( portTICK_PERIOD_MS );
         }
 
-        if( xPortRunning == pdTRUE )
-        {
-            configASSERT( xPortRunning );
-
-            /* Can't proceed if in a critical section as pvInterruptEventMutex won't
-             * be available. */
-            WaitForSingleObject( pvInterruptEventMutex, INFINITE );
-
-            /* The timer has expired, generate the simulated tick event. */
-            ulPendingInterrupts |= ( 1 << portINTERRUPT_TICK );
-
-            /* The interrupt is now pending - notify the simulated interrupt
-             * handler thread.  Must be outside of a critical section to get here so
-             * the handler thread can execute immediately pvInterruptEventMutex is
-             * released. */
-            configASSERT( ulCriticalNesting == 0UL );
-            SetEvent( pvInterruptEvent );
-
-            /* Give back the mutex so the simulated interrupt handler unblocks
-             * and can access the interrupt handler variables. */
-            ReleaseMutex( pvInterruptEventMutex );
-        }
+        vPortGenerateSimulatedInterruptFromWindowsThread( portINTERRUPT_TICK );
     }
 
     return 0;
@@ -636,6 +615,32 @@ void vPortGenerateSimulatedInterrupt( uint32_t ulInterruptNumber )
 }
 /*-----------------------------------------------------------*/
 
+void vPortGenerateSimulatedInterruptFromWindowsThread( uint32_t ulInterruptNumber )
+{
+    if( xPortRunning == pdTRUE )
+    {
+        /* Can't proceed if in a critical section as pvInterruptEventMutex won't
+         * be available. */
+        WaitForSingleObject( pvInterruptEventMutex, INFINITE );
+
+        /* Pending a user defined interrupt to be handled in simulated interrupt
+         * handler thread. */
+        ulPendingInterrupts |= ( 1 << ulInterruptNumber );
+
+        /* The interrupt is now pending - notify the simulated interrupt
+         * handler thread.  Must be outside of a critical section to get here so
+         * the handler thread can execute immediately pvInterruptEventMutex is
+         * released. */
+        configASSERT( ulCriticalNesting == 0UL );
+        SetEvent( pvInterruptEvent );
+
+        /* Give back the mutex so the simulated interrupt handler unblocks
+         * and can access the interrupt handler variables. */
+        ReleaseMutex( pvInterruptEventMutex );
+    }
+}
+/*-----------------------------------------------------------*/
+
 void vPortSetInterruptHandler( uint32_t ulInterruptNumber,
                                uint32_t ( * pvHandler )( void ) )
 {
diff --git a/portable/MSVC-MingW/portmacro.h b/portable/MSVC-MingW/portmacro.h
index c2b07fa19..d3db1eb62 100644
--- a/portable/MSVC-MingW/portmacro.h
+++ b/portable/MSVC-MingW/portmacro.h
@@ -184,8 +184,9 @@ void vPortExitCritical( void );
 #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
 #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
-#define portINTERRUPT_YIELD    ( 0UL )
-#define portINTERRUPT_TICK     ( 1UL )
+#define portINTERRUPT_YIELD                        ( 0UL )
+#define portINTERRUPT_TICK                         ( 1UL )
+#define portINTERRUPT_APPLICATION_DEFINED_START    ( 2UL )
 
 /*
  * Raise a simulated interrupt represented by the bit mask in ulInterruptMask.
@@ -194,6 +195,14 @@ void vPortExitCritical( void );
  */
 void vPortGenerateSimulatedInterrupt( uint32_t ulInterruptNumber );
 
+/*
+ * Raise a simulated interrupt represented by the bit mask in ulInterruptMask.
+ * Each bit can be used to represent an individual interrupt - with the first
+ * two bits being used for the Yield and Tick interrupts respectively. This function
+ * can be called in a windows thread.
+ */
+void vPortGenerateSimulatedInterruptFromWindowsThread( uint32_t ulInterruptNumber );
+
 /*
  * Install an interrupt handler to be called by the simulated interrupt handler
  * thread.  The interrupt number must be above any used by the kernel itself

From 55eceb2203742042714a8dfedd3a8e48908d10c0 Mon Sep 17 00:00:00 2001
From: StefanBalt <79701944+StefanBalt@users.noreply.github.com>
Date: Wed, 8 May 2024 13:37:52 +0200
Subject: [PATCH 272/424] Add configUSE_TASK_FPU_SUPPORT to AARCH64 port
 (#1048)

* Add configUSE_TASK_FPU_SUPPORT to AARCH64 port

NEON SIMD is required by standard AARCH64 and its registers are
frequently utilized by standard functions such as memcpy().
This means that even simple tasks that do not use any floating point
arithmetics may still alter the contents of the FPU registers.

For this reason it makes sense to add support for
configUSE_TASK_FPU_SUPPORT to be able to enforce FPU register saving and
restoring globally.

The implementation was largely adopted from the ARM_CA9 port. However,
the FPU registers must be placed on the stack before the critical
nesting count to match the AARCH64 portASM.S.
---
 portable/GCC/ARM_AARCH64/port.c      | 70 ++++++++++++++++++++--------
 portable/GCC/ARM_AARCH64/portmacro.h | 15 ++++--
 2 files changed, 63 insertions(+), 22 deletions(-)

diff --git a/portable/GCC/ARM_AARCH64/port.c b/portable/GCC/ARM_AARCH64/port.c
index 5b52dadda..238874edc 100644
--- a/portable/GCC/ARM_AARCH64/port.c
+++ b/portable/GCC/ARM_AARCH64/port.c
@@ -133,6 +133,10 @@
 #define portMAX_8_BIT_VALUE                       ( ( uint8_t ) 0xff )
 #define portBIT_0_SET                             ( ( uint8_t ) 0x01 )
 
+/* The space on the stack required to hold the FPU registers.
+ * There are 32 128-bit registers.*/
+#define portFPU_REGISTER_WORDS     ( 32 * 2 )
+
 /*-----------------------------------------------------------*/
 
 /*
@@ -244,23 +248,47 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
     *pxTopOfStack = ( StackType_t ) 0x00;         /* XZR - has no effect, used so there are an even number of registers. */
     pxTopOfStack--;
     *pxTopOfStack = ( StackType_t ) 0x00;         /* R30 - procedure call link register. */
-    pxTopOfStack--;
 
+    pxTopOfStack--;
     *pxTopOfStack = portINITIAL_PSTATE;
-    pxTopOfStack--;
 
+    pxTopOfStack--;
     *pxTopOfStack = ( StackType_t ) pxCode; /* Exception return address. */
-    pxTopOfStack--;
 
-    /* The task will start with a critical nesting count of 0 as interrupts are
-     * enabled. */
-    *pxTopOfStack = portNO_CRITICAL_NESTING;
-    pxTopOfStack--;
+    #if ( configUSE_TASK_FPU_SUPPORT == 1 )
+    {
+        /* The task will start with a critical nesting count of 0 as interrupts are
+        * enabled. */
+        pxTopOfStack--;
+        *pxTopOfStack = portNO_CRITICAL_NESTING;
 
-    /* The task will start without a floating point context.  A task that uses
-     * the floating point hardware must call vPortTaskUsesFPU() before executing
-     * any floating point instructions. */
-    *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
+        /* The task will start without a floating point context.  A task that
+         * uses the floating point hardware must call vPortTaskUsesFPU() before
+         * executing any floating point instructions. */
+        pxTopOfStack--;
+        *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
+    }
+    #elif ( configUSE_TASK_FPU_SUPPORT == 2 )
+    {
+        /* The task will start with a floating point context.  Leave enough
+         * space for the registers - and ensure they are initialised to 0. */
+        pxTopOfStack -= portFPU_REGISTER_WORDS;
+        memset( pxTopOfStack, 0x00, portFPU_REGISTER_WORDS * sizeof( StackType_t ) );
+
+        /* The task will start with a critical nesting count of 0 as interrupts are
+        * enabled. */
+        pxTopOfStack--;
+        *pxTopOfStack = portNO_CRITICAL_NESTING;
+
+        pxTopOfStack--;
+        *pxTopOfStack = pdTRUE;
+        ullPortTaskHasFPUContext = pdTRUE;
+    }
+    #else /* if ( configUSE_TASK_FPU_SUPPORT == 1 ) */
+    {
+        #error "Invalid configUSE_TASK_FPU_SUPPORT setting - configUSE_TASK_FPU_SUPPORT must be set to 1, 2, or left undefined."
+    }
+    #endif /* if ( configUSE_TASK_FPU_SUPPORT == 1 ) */
 
     return pxTopOfStack;
 }
@@ -440,15 +468,19 @@ void FreeRTOS_Tick_Handler( void )
 }
 /*-----------------------------------------------------------*/
 
-void vPortTaskUsesFPU( void )
-{
-    /* A task is registering the fact that it needs an FPU context.  Set the
-     * FPU flag (which is saved as part of the task context). */
-    ullPortTaskHasFPUContext = pdTRUE;
+#if ( configUSE_TASK_FPU_SUPPORT != 2 )
 
-    /* Consider initialising the FPSR here - but probably not necessary in
-     * AArch64. */
-}
+    void vPortTaskUsesFPU( void )
+    {
+        /* A task is registering the fact that it needs an FPU context.  Set the
+         * FPU flag (which is saved as part of the task context). */
+        ullPortTaskHasFPUContext = pdTRUE;
+
+        /* Consider initialising the FPSR here - but probably not necessary in
+         * AArch64. */
+    }
+
+#endif /* configUSE_TASK_FPU_SUPPORT */
 /*-----------------------------------------------------------*/
 
 void vPortClearInterruptMask( UBaseType_t uxNewMaskValue )
diff --git a/portable/GCC/ARM_AARCH64/portmacro.h b/portable/GCC/ARM_AARCH64/portmacro.h
index 04d34fc4f..e89abb661 100644
--- a/portable/GCC/ARM_AARCH64/portmacro.h
+++ b/portable/GCC/ARM_AARCH64/portmacro.h
@@ -135,9 +135,18 @@ extern void vPortInstallFreeRTOSVectorTable( void );
  * handler for whichever peripheral is used to generate the RTOS tick. */
 void FreeRTOS_Tick_Handler( void );
 
-/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
- * before any floating point instructions are executed. */
-void vPortTaskUsesFPU( void );
+/* If configUSE_TASK_FPU_SUPPORT is set to 1 (or left undefined) then tasks are
+ * created without an FPU context and must call vPortTaskUsesFPU() to give
+ * themselves an FPU context before using any FPU instructions.  If
+ * configUSE_TASK_FPU_SUPPORT is set to 2 then all tasks will have an FPU context
+ * by default. */
+#if ( configUSE_TASK_FPU_SUPPORT != 2 )
+    void vPortTaskUsesFPU( void );
+#else
+    /* Each task has an FPU context already, so define this function away to
+     * nothing to prevent it from being called accidentally. */
+    #define vPortTaskUsesFPU()
+#endif
 #define portTASK_USES_FLOATING_POINT()    vPortTaskUsesFPU()
 
 #define portLOWEST_INTERRUPT_PRIORITY           ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )

From 29b202a41e0e2810272b5765805d9fa4af247736 Mon Sep 17 00:00:00 2001
From: Gabriel Staples <ercaguy@gmail.com>
Date: Mon, 13 May 2024 04:19:50 -0700
Subject: [PATCH 273/424] list.c: improve code comments to point to official
 documentation about problems which may cause code to get stuck inside of
 list.c (#1051)

list.c: improve documentation about initializing binary semaphores
---
 list.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/list.c b/list.c
index fc99538b2..e6dbaaa3a 100644
--- a/list.c
+++ b/list.c
@@ -184,7 +184,14 @@ void vListInsert( List_t * const pxList,
         *   4) Using a queue or semaphore before it has been initialised or
         *      before the scheduler has been started (are interrupts firing
         *      before vTaskStartScheduler() has been called?).
-        *   5) If the FreeRTOS port supports interrupt nesting then ensure that
+        *   5) Attempting to 'take' binary semaphores created using
+        *      `xSemaphoreCreateBinary()` or `xSemaphoreCreateBinaryStatic()`
+        *      APIs, before 'giving' them. Binary semaphores created using
+        *      `xSemaphoreCreateBinary()` or `xSemaphoreCreateBinaryStatic()`,
+        *      are created in a state such that the semaphore must first be
+        *      'given' using xSemaphoreGive() API before it can be 'taken' using
+        *      xSemaphoreTake() API.
+        *   6) If the FreeRTOS port supports interrupt nesting then ensure that
         *      the priority of the tick interrupt is at or below
         *      configMAX_SYSCALL_INTERRUPT_PRIORITY.
         **********************************************************************/
@@ -192,7 +199,9 @@ void vListInsert( List_t * const pxList,
         for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext )
         {
             /* There is nothing to do here, just iterating to the wanted
-             * insertion position. */
+             * insertion position.
+             * IF YOU FIND YOUR CODE STUCK HERE, SEE THE NOTE JUST ABOVE.
+             */
         }
     }
 

From 2e0c623351f03f2fb94c5aab151b78e8315edb19 Mon Sep 17 00:00:00 2001
From: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Date: Tue, 14 May 2024 16:15:54 +0530
Subject: [PATCH 274/424] Fix race in prvProcessSimulatedInterrupts (#1055)

Earlier the code was suspending the current thread after calling
vTaskSwitchContext. This left a gap where the current thread could
access incorrect pxCurrentTCB after it was changed by
vTaskSwitchContext.

This commit addresses the problem by suspending the current thread
before calling vTaskSwitchContext.

It was reported here - https://github.com/FreeRTOS/FreeRTOS-Kernel/issues/1054.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 portable/MSVC-MingW/port.c | 55 +++++++++++++-------------------------
 1 file changed, 19 insertions(+), 36 deletions(-)

diff --git a/portable/MSVC-MingW/port.c b/portable/MSVC-MingW/port.c
index 8b8289b8f..7c34aabd6 100644
--- a/portable/MSVC-MingW/port.c
+++ b/portable/MSVC-MingW/port.c
@@ -435,48 +435,31 @@ static void prvProcessSimulatedInterrupts( void )
 
             if( ulSwitchRequired != pdFALSE )
             {
-                void * pvOldCurrentTCB;
+                /* Suspend the old thread. */
+                pxThreadState = ( ThreadState_t * ) *( ( size_t * ) pxCurrentTCB );
+                SuspendThread( pxThreadState->pvThread );
 
-                pvOldCurrentTCB = pxCurrentTCB;
+                /* Ensure the thread is actually suspended by performing a
+                 * synchronous operation that can only complete when the thread
+                 * is actually suspended. The below code asks for dummy register
+                 * data. Experimentation shows that these two lines don't appear
+                 * to do anything now, but according to
+                 * https://devblogs.microsoft.com/oldnewthing/20150205-00/?p=44743
+                 * they do - so as they do not harm (slight run-time hit). */
+                xContext.ContextFlags = CONTEXT_INTEGER;
+                ( void ) GetThreadContext( pxThreadState->pvThread, &xContext );
 
                 /* Select the next task to run. */
                 vTaskSwitchContext();
 
-                /* If the task selected to enter the running state is not the task
-                 * that is already in the running state. */
-                if( pvOldCurrentTCB != pxCurrentTCB )
-                {
-                    /* Suspend the old thread.  In the cases where the (simulated)
-                     * interrupt is asynchronous (tick event swapping a task out rather
-                     * than a task blocking or yielding) it doesn't matter if the
-                     * 'suspend' operation doesn't take effect immediately - if it
-                     * doesn't it would just be like the interrupt occurring slightly
-                     * later.  In cases where the yield was caused by a task blocking
-                     * or yielding then the task will block on a yield event after the
-                     * yield operation in case the 'suspend' operation doesn't take
-                     * effect immediately.  */
-                    pxThreadState = ( ThreadState_t * ) *( ( size_t * ) pvOldCurrentTCB );
-                    SuspendThread( pxThreadState->pvThread );
+                /* Obtain the state of the task now selected to enter the
+                 * Running state. */
+                pxThreadState = ( ThreadState_t * ) ( *( size_t * ) pxCurrentTCB );
 
-                    /* Ensure the thread is actually suspended by performing a
-                     *  synchronous operation that can only complete when the thread is
-                     *  actually suspended.  The below code asks for dummy register
-                     *  data.  Experimentation shows that these two lines don't appear
-                     *  to do anything now, but according to
-                     *  https://devblogs.microsoft.com/oldnewthing/20150205-00/?p=44743
-                     *  they do - so as they do not harm (slight run-time hit). */
-                    xContext.ContextFlags = CONTEXT_INTEGER;
-                    ( void ) GetThreadContext( pxThreadState->pvThread, &xContext );
-
-                    /* Obtain the state of the task now selected to enter the
-                     * Running state. */
-                    pxThreadState = ( ThreadState_t * ) ( *( size_t * ) pxCurrentTCB );
-
-                    /* pxThreadState->pvThread can be NULL if the task deleted
-                     * itself - but a deleted task should never be resumed here. */
-                    configASSERT( pxThreadState->pvThread != NULL );
-                    ResumeThread( pxThreadState->pvThread );
-                }
+                /* pxThreadState->pvThread can be NULL if the task deleted
+                 * itself - but a deleted task should never be resumed here. */
+                configASSERT( pxThreadState->pvThread != NULL );
+                ResumeThread( pxThreadState->pvThread );
             }
 
             /* If the thread that is about to be resumed stopped running

From a8376dbe816b230985db09d9b9203c33cdf4fc66 Mon Sep 17 00:00:00 2001
From: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Date: Tue, 14 May 2024 16:24:49 +0530
Subject: [PATCH 275/424] Revert the change introduced in PR #1051 (#1056)

As pointed out by Jeff Tenney, the comment introduced in the PR is not
accurate.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 list.c | 9 +--------
 1 file changed, 1 insertion(+), 8 deletions(-)

diff --git a/list.c b/list.c
index e6dbaaa3a..eb9efbd2d 100644
--- a/list.c
+++ b/list.c
@@ -184,14 +184,7 @@ void vListInsert( List_t * const pxList,
         *   4) Using a queue or semaphore before it has been initialised or
         *      before the scheduler has been started (are interrupts firing
         *      before vTaskStartScheduler() has been called?).
-        *   5) Attempting to 'take' binary semaphores created using
-        *      `xSemaphoreCreateBinary()` or `xSemaphoreCreateBinaryStatic()`
-        *      APIs, before 'giving' them. Binary semaphores created using
-        *      `xSemaphoreCreateBinary()` or `xSemaphoreCreateBinaryStatic()`,
-        *      are created in a state such that the semaphore must first be
-        *      'given' using xSemaphoreGive() API before it can be 'taken' using
-        *      xSemaphoreTake() API.
-        *   6) If the FreeRTOS port supports interrupt nesting then ensure that
+        *   5) If the FreeRTOS port supports interrupt nesting then ensure that
         *      the priority of the tick interrupt is at or below
         *      configMAX_SYSCALL_INTERRUPT_PRIORITY.
         **********************************************************************/

From c9e3949f02f0350986f7a7df273e8bf2e9311d04 Mon Sep 17 00:00:00 2001
From: Joseph Julicher <jjulicher@mac.com>
Date: Tue, 14 May 2024 20:58:41 -0700
Subject: [PATCH 276/424] added configUSE_POSIX_ERRNO to the template
 FreeRTOSConfig.h (#1052)

* added a reference to configUSE_POSIX_ERRNO

* fixed formatting

* format changes from PR check
---
 .../template_configuration/FreeRTOSConfig.h   | 327 +++++++++---------
 1 file changed, 173 insertions(+), 154 deletions(-)

diff --git a/examples/template_configuration/FreeRTOSConfig.h b/examples/template_configuration/FreeRTOSConfig.h
index c1c05966a..c35630bd1 100644
--- a/examples/template_configuration/FreeRTOSConfig.h
+++ b/examples/template_configuration/FreeRTOSConfig.h
@@ -4,22 +4,23 @@
  *
  * SPDX-License-Identifier: MIT
  *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
  *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
  *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
  *
  * https://www.FreeRTOS.org
  * https://github.com/FreeRTOS
@@ -47,10 +48,11 @@
 /******************************************************************************/
 
 /* In most cases, configCPU_CLOCK_HZ must be set to the frequency of the clock
- * that drives the peripheral used to generate the kernels periodic tick interrupt.
- * The default value is set to 20MHz and matches the QEMU demo settings.  Your
- * application will certainly need a different value so set this correctly.
- * This is very often, but not always, equal to the main system clock frequency. */
+ * that drives the peripheral used to generate the kernels periodic tick
+ * interrupt. The default value is set to 20MHz and matches the QEMU demo
+ * settings.  Your application will certainly need a different value so set this
+ * correctly. This is very often, but not always, equal to the main system clock
+ * frequency. */
 #define configCPU_CLOCK_HZ    ( ( unsigned long ) 20000000 )
 
 /* configSYSTICK_CLOCK_HZ is an optional parameter for ARM Cortex-M ports only.
@@ -59,11 +61,11 @@
  * Cortex-M SysTick timer. Most Cortex-M MCUs run the SysTick timer at the same
  * frequency as the MCU itself - when that is the case configSYSTICK_CLOCK_HZ is
  * not needed and should be left undefined. If the SysTick timer is clocked at a
- * different frequency to the MCU core then set configCPU_CLOCK_HZ to the MCU clock
- * frequency, as normal, and configSYSTICK_CLOCK_HZ to the SysTick clock
+ * different frequency to the MCU core then set configCPU_CLOCK_HZ to the MCU
+ * clock frequency, as normal, and configSYSTICK_CLOCK_HZ to the SysTick clock
  * frequency.  Not used if left undefined.
- * The default value is undefined (commented out).  If you need this value bring it
- * back and set it to a suitable value. */
+ * The default value is undefined (commented out).  If you need this value bring
+ * it back and set it to a suitable value. */
 
 /*
  #define configSYSTICK_CLOCK_HZ                  [Platform specific]
@@ -90,28 +92,29 @@
 #define configUSE_TIME_SLICING                     0
 
 /* Set configUSE_PORT_OPTIMISED_TASK_SELECTION to 1 to select the next task to
- * run using an algorithm optimised to the instruction set of the target hardware -
- * normally using a count leading zeros assembly instruction.  Set to 0 to select
- * the next task to run using a generic C algorithm that works for all FreeRTOS
- * ports.  Not all FreeRTOS ports have this option.  Defaults to 0 if left
- * undefined. */
+ * run using an algorithm optimised to the instruction set of the target
+ * hardware - normally using a count leading zeros assembly instruction.  Set to
+ * 0 to select the next task to run using a generic C algorithm that works for
+ * all FreeRTOS ports.  Not all FreeRTOS ports have this option.  Defaults to 0
+ * if left undefined. */
 #define configUSE_PORT_OPTIMISED_TASK_SELECTION    0
 
 /* Set configUSE_TICKLESS_IDLE to 1 to use the low power tickless mode.  Set to
  * 0 to keep the tick interrupt running at all times.  Not all FreeRTOS ports
- * support tickless mode. See https://www.freertos.org/low-power-tickless-rtos.html
- * Defaults to 0 if left undefined. */
+ * support tickless mode. See
+ * https://www.freertos.org/low-power-tickless-rtos.html Defaults to 0 if left
+ * undefined. */
 #define configUSE_TICKLESS_IDLE                    0
 
 /* configMAX_PRIORITIES Sets the number of available task priorities.  Tasks can
- * be assigned priorities of 0 to (configMAX_PRIORITIES - 1).  Zero is the lowest
- * priority. */
+ * be assigned priorities of 0 to (configMAX_PRIORITIES - 1).  Zero is the
+ * lowest priority. */
 #define configMAX_PRIORITIES                       5
 
 /* configMINIMAL_STACK_SIZE defines the size of the stack used by the Idle task
- * (in words, not in bytes!).  The kernel does not use this constant for any other
- * purpose.  Demo applications use the constant to make the demos somewhat portable
- * across hardware architectures. */
+ * (in words, not in bytes!).  The kernel does not use this constant for any
+ * other purpose.  Demo applications use the constant to make the demos somewhat
+ * portable across hardware architectures. */
 #define configMINIMAL_STACK_SIZE                   128
 
 /* configMAX_TASK_NAME_LEN sets the maximum length (in characters) of a task's
@@ -122,7 +125,8 @@
  * has executed since the RTOS kernel was started.
  * The tick count is held in a variable of type TickType_t.
  *
- * configTICK_TYPE_WIDTH_IN_BITS controls the type (and therefore bit-width) of TickType_t:
+ * configTICK_TYPE_WIDTH_IN_BITS controls the type (and therefore bit-width) of
+ * TickType_t:
  *
  * Defining configTICK_TYPE_WIDTH_IN_BITS as TICK_TYPE_WIDTH_16_BITS causes
  * TickType_t to be defined (typedef'ed) as an unsigned 16-bit type.
@@ -135,15 +139,15 @@
 #define configTICK_TYPE_WIDTH_IN_BITS              TICK_TYPE_WIDTH_64_BITS
 
 /* Set configIDLE_SHOULD_YIELD to 1 to have the Idle task yield to an
- * application task if there is an Idle priority (priority 0) application task that
- * can run.  Set to 0 to have the Idle task use all of its timeslice.  Default to 1
- * if left undefined. */
+ * application task if there is an Idle priority (priority 0) application task
+ * that can run.  Set to 0 to have the Idle task use all of its timeslice.
+ * Default to 1 if left undefined. */
 #define configIDLE_SHOULD_YIELD                    1
 
 /* Each task has an array of task notifications.
- * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the array.
- * See https://www.freertos.org/RTOS-task-notifications.html  Defaults to 1 if
- * left undefined. */
+ * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the
+ * array. See https://www.freertos.org/RTOS-task-notifications.html  Defaults to
+ * 1 if left undefined. */
 #define configTASK_NOTIFICATION_ARRAY_ENTRIES      1
 
 /* configQUEUE_REGISTRY_SIZE sets the maximum number of queues and semaphores
@@ -152,21 +156,22 @@
 #define configQUEUE_REGISTRY_SIZE                  0
 
 /* Set configENABLE_BACKWARD_COMPATIBILITY to 1 to map function names and
- * datatypes from old version of FreeRTOS to their latest equivalent.  Defaults to
- * 1 if left undefined. */
+ * datatypes from old version of FreeRTOS to their latest equivalent.  Defaults
+ * to 1 if left undefined. */
 #define configENABLE_BACKWARD_COMPATIBILITY        0
 
 /* Each task has its own array of pointers that can be used as thread local
- * storage.  configNUM_THREAD_LOCAL_STORAGE_POINTERS set the number of indexes in
- * the array.  See https://www.freertos.org/thread-local-storage-pointers.html
- * Defaults to 0 if left undefined. */
+ * storage.  configNUM_THREAD_LOCAL_STORAGE_POINTERS set the number of indexes
+ * in the array.  See
+ * https://www.freertos.org/thread-local-storage-pointers.html Defaults to 0 if
+ * left undefined. */
 #define configNUM_THREAD_LOCAL_STORAGE_POINTERS    0
 
 /* When configUSE_MINI_LIST_ITEM is set to 0, MiniListItem_t and ListItem_t are
- * both the same. When configUSE_MINI_LIST_ITEM is set to 1, MiniListItem_t contains
- * 3 fewer fields than ListItem_t which saves some RAM at the cost of violating
- * strict aliasing rules which some compilers depend on for optimization. Defaults
- * to 1 if left undefined. */
+ * both the same. When configUSE_MINI_LIST_ITEM is set to 1, MiniListItem_t
+ * contains 3 fewer fields than ListItem_t which saves some RAM at the cost of
+ * violating strict aliasing rules which some compilers depend on for
+ * optimization. Defaults to 1 if left undefined. */
 #define configUSE_MINI_LIST_ITEM                   1
 
 /* Sets the type used by the parameter to xTaskCreate() that specifies the stack
@@ -176,22 +181,22 @@
 #define configSTACK_DEPTH_TYPE                     size_t
 
 /* configMESSAGE_BUFFER_LENGTH_TYPE sets the type used to store the length of
- * each message written to a FreeRTOS message buffer (the length is also written to
- * the message buffer.  Defaults to size_t if left undefined - but that may waste
- * space if messages never go above a length that could be held in a uint8_t. */
+ * each message written to a FreeRTOS message buffer (the length is also written
+ * to the message buffer.  Defaults to size_t if left undefined - but that may
+ * waste space if messages never go above a length that could be held in a
+ * uint8_t. */
 #define configMESSAGE_BUFFER_LENGTH_TYPE           size_t
 
-/* If configHEAP_CLEAR_MEMORY_ON_FREE is set to 1, then blocks of memory allocated
- * using pvPortMalloc() will be cleared (i.e. set to zero) when freed using
- * vPortFree(). Defaults to 0 if left undefined. */
+/* If configHEAP_CLEAR_MEMORY_ON_FREE is set to 1, then blocks of memory
+ * allocated using pvPortMalloc() will be cleared (i.e. set to zero) when freed
+ * using vPortFree(). Defaults to 0 if left undefined. */
 #define configHEAP_CLEAR_MEMORY_ON_FREE            1
 
-/* vTaskList and vTaskGetRunTimeStats APIs take a buffer as a parameter and assume
- * that the length of the buffer is configSTATS_BUFFER_MAX_LENGTH. Defaults to
- * 0xFFFF if left undefined.
- * New applications are recommended to use vTaskListTasks and
- * vTaskGetRunTimeStatistics APIs instead and supply the length of the buffer
- * explicitly to avoid memory corruption. */
+/* vTaskList and vTaskGetRunTimeStats APIs take a buffer as a parameter and
+ * assume that the length of the buffer is configSTATS_BUFFER_MAX_LENGTH.
+ * Defaults to 0xFFFF if left undefined. New applications are recommended to use
+ * vTaskListTasks and vTaskGetRunTimeStatistics APIs instead and supply the
+ * length of the buffer explicitly to avoid memory corruption. */
 #define configSTATS_BUFFER_MAX_LENGTH              0xFFFF
 
 /* Set configUSE_NEWLIB_REENTRANT to 1 to have a newlib reent structure
@@ -199,11 +204,11 @@
  * Default to 0 if left undefined.
  *
  * Note Newlib support has been included by popular demand, but is not used or
- * tested by the FreeRTOS maintainers themselves. FreeRTOS is not responsible for
- * resulting newlib operation. User must be familiar with newlib and must provide
- * system-wide implementations of the necessary stubs. Note that (at the time of
- * writing) the current newlib design implements a system-wide malloc() that must
- * be provided with locks. */
+ * tested by the FreeRTOS maintainers themselves. FreeRTOS is not responsible
+ * for resulting newlib operation. User must be familiar with newlib and must
+ * provide system-wide implementations of the necessary stubs. Note that (at the
+ * time of writing) the current newlib design implements a system-wide malloc()
+ * that must be provided with locks. */
 #define configUSE_NEWLIB_REENTRANT                 0
 
 /******************************************************************************/
@@ -220,20 +225,21 @@
 /* configTIMER_TASK_PRIORITY sets the priority used by the timer task.  Only
  * used if configUSE_TIMERS is set to 1.  The timer task is a standard FreeRTOS
  * task, so its priority is set like any other task.  See
- * https://www.freertos.org/RTOS-software-timer-service-daemon-task.html  Only used
- * if configUSE_TIMERS is set to 1. */
+ * https://www.freertos.org/RTOS-software-timer-service-daemon-task.html  Only
+ * used if configUSE_TIMERS is set to 1. */
 #define configTIMER_TASK_PRIORITY       ( configMAX_PRIORITIES - 1 )
 
 /* configTIMER_TASK_STACK_DEPTH sets the size of the stack allocated to the
  * timer task (in words, not in bytes!).  The timer task is a standard FreeRTOS
- * task.  See https://www.freertos.org/RTOS-software-timer-service-daemon-task.html
- * Only used if configUSE_TIMERS is set to 1. */
+ * task.  See
+ * https://www.freertos.org/RTOS-software-timer-service-daemon-task.html Only
+ * used if configUSE_TIMERS is set to 1. */
 #define configTIMER_TASK_STACK_DEPTH    configMINIMAL_STACK_SIZE
 
 /* configTIMER_QUEUE_LENGTH sets the length of the queue (the number of discrete
  * items the queue can hold) used to send commands to the timer task.  See
- * https://www.freertos.org/RTOS-software-timer-service-daemon-task.html  Only used
- * if configUSE_TIMERS is set to 1. */
+ * https://www.freertos.org/RTOS-software-timer-service-daemon-task.html  Only
+ * used if configUSE_TIMERS is set to 1. */
 #define configTIMER_QUEUE_LENGTH        10
 
 /******************************************************************************/
@@ -270,21 +276,22 @@
 #define configSUPPORT_STATIC_ALLOCATION              1
 
 /* Set configSUPPORT_DYNAMIC_ALLOCATION to 1 to include FreeRTOS API functions
- * that create FreeRTOS objects (tasks, queues, etc.) using dynamically allocated
- * memory in the build.  Set to 0 to exclude the ability to create dynamically
- * allocated objects from the build.  Defaults to 1 if left undefined.  See
+ * that create FreeRTOS objects (tasks, queues, etc.) using dynamically
+ * allocated memory in the build.  Set to 0 to exclude the ability to create
+ * dynamically allocated objects from the build.  Defaults to 1 if left
+ * undefined.  See
  * https://www.freertos.org/Static_Vs_Dynamic_Memory_Allocation.html. */
 #define configSUPPORT_DYNAMIC_ALLOCATION             1
 
 /* Sets the total size of the FreeRTOS heap, in bytes, when heap_1.c, heap_2.c
- * or heap_4.c are included in the build.  This value is defaulted to 4096 bytes but
- * it must be tailored to each application.  Note the heap will appear in the .bss
- * section.  See https://www.freertos.org/a00111.html. */
+ * or heap_4.c are included in the build.  This value is defaulted to 4096 bytes
+ * but it must be tailored to each application.  Note the heap will appear in
+ * the .bss section.  See https://www.freertos.org/a00111.html. */
 #define configTOTAL_HEAP_SIZE                        4096
 
 /* Set configAPPLICATION_ALLOCATED_HEAP to 1 to have the application allocate
- * the array used as the FreeRTOS heap.  Set to 0 to have the linker allocate the
- * array used as the FreeRTOS heap.  Defaults to 0 if left undefined. */
+ * the array used as the FreeRTOS heap.  Set to 0 to have the linker allocate
+ * the array used as the FreeRTOS heap.  Defaults to 0 if left undefined. */
 #define configAPPLICATION_ALLOCATED_HEAP             0
 
 /* Set configSTACK_ALLOCATION_FROM_SEPARATE_HEAP to 1 to have task stacks
@@ -295,9 +302,9 @@
  * Defaults to 0 if left undefined. */
 #define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP    0
 
-/* Set configENABLE_HEAP_PROTECTOR to 1 to enable bounds checking and obfuscation
- * to internal heap block pointers in heap_4.c and heap_5.c to help catch pointer
- * corruptions. Defaults to 0 if left undefined. */
+/* Set configENABLE_HEAP_PROTECTOR to 1 to enable bounds checking and
+ * obfuscation to internal heap block pointers in heap_4.c and heap_5.c to help
+ * catch pointer corruptions. Defaults to 0 if left undefined. */
 #define configENABLE_HEAP_PROTECTOR                  0
 
 /******************************************************************************/
@@ -311,11 +318,11 @@
 #define configKERNEL_INTERRUPT_PRIORITY          0
 
 /* configMAX_SYSCALL_INTERRUPT_PRIORITY sets the interrupt priority above which
- * FreeRTOS API calls must not be made.  Interrupts above this priority are never
- * disabled, so never delayed by RTOS activity.  The default value is set to the
- * highest interrupt priority (0).  Not supported by all FreeRTOS ports.
- * See https://www.freertos.org/RTOS-Cortex-M3-M4.html for information specific to
- * ARM Cortex-M devices. */
+ * FreeRTOS API calls must not be made.  Interrupts above this priority are
+ * never disabled, so never delayed by RTOS activity.  The default value is set
+ * to the highest interrupt priority (0).  Not supported by all FreeRTOS ports.
+ * See https://www.freertos.org/RTOS-Cortex-M3-M4.html for information specific
+ * to ARM Cortex-M devices. */
 #define configMAX_SYSCALL_INTERRUPT_PRIORITY     0
 
 /* Another name for configMAX_SYSCALL_INTERRUPT_PRIORITY - the name used depends
@@ -327,9 +334,9 @@
 /******************************************************************************/
 
 /* Set the following configUSE_* constants to 1 to include the named hook
- * functionality in the build.  Set to 0 to exclude the hook functionality from the
- * build.  The application writer is responsible for providing the hook function
- * for any set to 1.  See https://www.freertos.org/a00016.html. */
+ * functionality in the build.  Set to 0 to exclude the hook functionality from
+ * the build.  The application writer is responsible for providing the hook
+ * function for any set to 1.  See https://www.freertos.org/a00016.html. */
 #define configUSE_IDLE_HOOK                   0
 #define configUSE_TICK_HOOK                   0
 #define configUSE_MALLOC_FAILED_HOOK          0
@@ -346,14 +353,15 @@
 /* Set configCHECK_FOR_STACK_OVERFLOW to 1 or 2 for FreeRTOS to check for a
  * stack overflow at the time of a context switch.  Set to 0 to not look for a
  * stack overflow.  If configCHECK_FOR_STACK_OVERFLOW is 1 then the check only
- * looks for the stack pointer being out of bounds when a task's context is saved
- * to its stack - this is fast but somewhat ineffective.  If
- * configCHECK_FOR_STACK_OVERFLOW is 2 then the check looks for a pattern written
- * to the end of a task's stack having been overwritten.  This is slower, but will
- * catch most (but not all) stack overflows.  The application writer must provide
- * the stack overflow callback when configCHECK_FOR_STACK_OVERFLOW is set to 1.
- * See https://www.freertos.org/Stacks-and-stack-overflow-checking.html  Defaults
- * to 0 if left undefined. */
+ * looks for the stack pointer being out of bounds when a task's context is
+ * saved to its stack - this is fast but somewhat ineffective.  If
+ * configCHECK_FOR_STACK_OVERFLOW is 2 then the check looks for a pattern
+ * written to the end of a task's stack having been overwritten.  This is
+ * slower, but will catch most (but not all) stack overflows.  The application
+ * writer must provide the stack overflow callback when
+ * configCHECK_FOR_STACK_OVERFLOW is set to 1. See
+ * https://www.freertos.org/Stacks-and-stack-overflow-checking.html  Defaults to
+ * 0 if left undefined. */
 #define configCHECK_FOR_STACK_OVERFLOW        2
 
 /******************************************************************************/
@@ -362,8 +370,9 @@
 
 /* Set configGENERATE_RUN_TIME_STATS to 1 to have FreeRTOS collect data on the
  * processing time used by each task.  Set to 0 to not collect the data.  The
- * application writer needs to provide a clock source if set to 1.  Defaults to 0
- * if left undefined.  See https://www.freertos.org/rtos-run-time-stats.html. */
+ * application writer needs to provide a clock source if set to 1.  Defaults to
+ * 0 if left undefined.  See https://www.freertos.org/rtos-run-time-stats.html.
+ */
 #define configGENERATE_RUN_TIME_STATS           0
 
 /* Set configUSE_TRACE_FACILITY to include additional task structure members
@@ -385,8 +394,8 @@
 
 /* Set configUSE_CO_ROUTINES to 1 to include co-routine functionality in the
  * build, or 0 to omit co-routine functionality from the build. To include
- * co-routines, croutine.c must be included in the project. Defaults to 0 if left
- * undefined. */
+ * co-routines, croutine.c must be included in the project. Defaults to 0 if
+ * left undefined. */
 #define configUSE_CO_ROUTINES              0
 
 /* configMAX_CO_ROUTINE_PRIORITIES defines the number of priorities available
@@ -403,9 +412,9 @@
  * at all (i.e. comment out or delete the definitions) to completely remove
  * assertions.  configASSERT() can be defined to anything you want, for example
  * you can call a function if an assert fails that passes the filename and line
- * number of the failing assert (for example, "vAssertCalled( __FILE__, __LINE__ )"
- * or it can simple disable interrupts and sit in a loop to halt all execution
- * on the failing line for viewing in a debugger. */
+ * number of the failing assert (for example, "vAssertCalled( __FILE__, __LINE__
+ * )" or it can simple disable interrupts and sit in a loop to halt all
+ * execution on the failing line for viewing in a debugger. */
 #define configASSERT( x )         \
     if( ( x ) == 0 )              \
     {                             \
@@ -420,9 +429,10 @@
 
 /* If configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS is set to 1 then
  * the application writer can provide functions that execute in privileged mode.
- * See: https://www.freertos.org/a00110.html#configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS
- * Defaults to 0 if left undefined.  Only used by the FreeRTOS Cortex-M MPU ports,
- * not the standard ARMv7-M Cortex-M port. */
+ * See:
+ * https://www.freertos.org/a00110.html#configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS
+ * Defaults to 0 if left undefined.  Only used by the FreeRTOS Cortex-M MPU
+ * ports, not the standard ARMv7-M Cortex-M port. */
 #define configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS    0
 
 /* Set configTOTAL_MPU_REGIONS to the number of MPU regions implemented on your
@@ -432,24 +442,24 @@
 #define configTOTAL_MPU_REGIONS                                   8
 
 /* configTEX_S_C_B_FLASH allows application writers to override the default
- * values for the for TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for
- * the MPU region covering Flash.  Defaults to 0x07UL (which means TEX=000, S=1,
- * C=1, B=1) if left undefined.  Only used by the FreeRTOS Cortex-M MPU ports, not
- * the standard ARMv7-M Cortex-M port. */
+ * values for the for TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits
+ * for the MPU region covering Flash.  Defaults to 0x07UL (which means TEX=000,
+ * S=1, C=1, B=1) if left undefined.  Only used by the FreeRTOS Cortex-M MPU
+ * ports, not the standard ARMv7-M Cortex-M port. */
 #define configTEX_S_C_B_FLASH                                     0x07UL
 
 /* configTEX_S_C_B_SRAM allows application writers to override the default
- * values for the for TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for
- * the MPU region covering RAM. Defaults to 0x07UL (which means TEX=000, S=1, C=1,
- * B=1) if left undefined.  Only used by the FreeRTOS Cortex-M MPU ports, not
- * the standard ARMv7-M Cortex-M port. */
+ * values for the for TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits
+ * for the MPU region covering RAM. Defaults to 0x07UL (which means TEX=000,
+ * S=1, C=1, B=1) if left undefined.  Only used by the FreeRTOS Cortex-M MPU
+ * ports, not the standard ARMv7-M Cortex-M port. */
 #define configTEX_S_C_B_SRAM                                      0x07UL
 
 /* Set configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY to 0 to prevent any privilege
  * escalations originating from outside of the kernel code itself.  Set to 1 to
  * allow application tasks to raise privilege.  Defaults to 1 if left undefined.
- * Only used by the FreeRTOS Cortex-M MPU ports, not the standard ARMv7-M Cortex-M
- * port. */
+ * Only used by the FreeRTOS Cortex-M MPU ports, not the standard ARMv7-M
+ * Cortex-M port. */
 #define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY               1
 
 /* Set configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS to 1 to allow unprivileged
@@ -493,8 +503,8 @@
 /* SMP( Symmetric MultiProcessing ) Specific Configuration definitions. *******/
 /******************************************************************************/
 
-/* Set configNUMBER_OF_CORES to the number of available processor cores. Defaults
- * to 1 if left undefined. */
+/* Set configNUMBER_OF_CORES to the number of available processor cores.
+ * Defaults to 1 if left undefined. */
 
 /*
  #define configNUMBER_OF_CORES                     [Num of available cores]
@@ -511,19 +521,20 @@
 
 /* When using SMP (i.e. configNUMBER_OF_CORES is greater than one), set
  * configUSE_CORE_AFFINITY to 1 to enable core affinity feature. When core
- * affinity feature is enabled, the vTaskCoreAffinitySet and vTaskCoreAffinityGet
- * APIs can be used to set and retrieve which cores a task can run on. If
- * configUSE_CORE_AFFINITY is set to 0 then the FreeRTOS scheduler is free to
- * run any task on any available core. */
+ * affinity feature is enabled, the vTaskCoreAffinitySet and
+ * vTaskCoreAffinityGet APIs can be used to set and retrieve which cores a task
+ * can run on. If configUSE_CORE_AFFINITY is set to 0 then the FreeRTOS
+ * scheduler is free to run any task on any available core. */
 #define configUSE_CORE_AFFINITY                   0
 
 /* When using SMP with core affinity feature enabled, set
  * configTASK_DEFAULT_CORE_AFFINITY to change the default core affinity mask for
- * tasks created without an affinity mask specified. Setting the define to 1 would
- * make such tasks run on core 0 and setting it to (1 << portGET_CORE_ID()) would
- * make such tasks run on the current core. This config value is useful, if
- * swapping tasks between cores is not supported (e.g. Tricore) or if legacy code
- * should be controlled. Defaults to tskNO_AFFINITY if left undefined. */
+ * tasks created without an affinity mask specified. Setting the define to 1
+ * would make such tasks run on core 0 and setting it to (1 <<
+ * portGET_CORE_ID()) would make such tasks run on the current core. This config
+ * value is useful, if swapping tasks between cores is not supported (e.g.
+ * Tricore) or if legacy code should be controlled. Defaults to tskNO_AFFINITY
+ * if left undefined. */
 #define configTASK_DEFAULT_CORE_AFFINITY          tskNO_AFFINITY
 
 /* When using SMP (i.e. configNUMBER_OF_CORES is greater than one), if
@@ -534,8 +545,8 @@
 
 /* When using SMP (i.e. configNUMBER_OF_CORES is greater than one), set
  * configUSE_PASSIVE_IDLE_HOOK to 1 to allow the application writer to use
- * the passive idle task hook to add background functionality without the overhead
- * of a separate task. Defaults to 0 if left undefined. */
+ * the passive idle task hook to add background functionality without the
+ * overhead of a separate task. Defaults to 0 if left undefined. */
 #define configUSE_PASSIVE_IDLE_HOOK               0
 
 /* When using SMP (i.e. configNUMBER_OF_CORES is greater than one),
@@ -544,19 +555,19 @@
  * tskNO_AFFINITY if left undefined. */
 #define configTIMER_SERVICE_TASK_CORE_AFFINITY    tskNO_AFFINITY
 
-
 /******************************************************************************/
 /* ARMv8-M secure side port related definitions. ******************************/
 /******************************************************************************/
 
 /* secureconfigMAX_SECURE_CONTEXTS define the maximum number of tasks that can
- *  call into the secure side of an ARMv8-M chip.  Not used by any other ports. */
+ *  call into the secure side of an ARMv8-M chip.  Not used by any other ports.
+ */
 #define secureconfigMAX_SECURE_CONTEXTS        5
 
 /* Defines the kernel provided implementation of
  * vApplicationGetIdleTaskMemory() and vApplicationGetTimerTaskMemory()
- * to provide the memory that is used by the Idle task and Timer task respectively.
- * The application can provide it's own implementation of
+ * to provide the memory that is used by the Idle task and Timer task
+ * respectively. The application can provide it's own implementation of
  * vApplicationGetIdleTaskMemory() and vApplicationGetTimerTaskMemory() by
  * setting configKERNEL_PROVIDED_STATIC_MEMORY to 0 or leaving it undefined. */
 #define configKERNEL_PROVIDED_STATIC_MEMORY    1
@@ -571,11 +582,11 @@
  * exported from secure side. */
 #define configENABLE_TRUSTZONE            1
 
-/* If the application writer does not want to use TrustZone, but the hardware does
- * not support disabling TrustZone then the entire application (including the FreeRTOS
- * scheduler) can run on the secure side without ever branching to the non-secure side.
- * To do that, in addition to setting configENABLE_TRUSTZONE to 0, also set
- * configRUN_FREERTOS_SECURE_ONLY to 1. */
+/* If the application writer does not want to use TrustZone, but the hardware
+ * does not support disabling TrustZone then the entire application (including
+ * the FreeRTOS scheduler) can run on the secure side without ever branching to
+ * the non-secure side. To do that, in addition to setting
+ * configENABLE_TRUSTZONE to 0, also set configRUN_FREERTOS_SECURE_ONLY to 1. */
 #define configRUN_FREERTOS_SECURE_ONLY    1
 
 /* Set configENABLE_MPU to 1 to enable the Memory Protection Unit (MPU), or 0
@@ -586,27 +597,31 @@
  * to leave the Floating Point Unit disabled. */
 #define configENABLE_FPU                  1
 
-/* Set configENABLE_MVE to 1 to enable the M-Profile Vector Extension (MVE) support,
- * or 0 to leave the MVE support disabled. This option is only applicable to Cortex-M55
- * and Cortex-M85 ports as M-Profile Vector Extension (MVE) is available only on
- * these architectures. configENABLE_MVE must be left undefined, or defined to 0
- * for the Cortex-M23,Cortex-M33 and Cortex-M35P ports. */
+/* Set configENABLE_MVE to 1 to enable the M-Profile Vector Extension (MVE)
+ * support, or 0 to leave the MVE support disabled. This option is only
+ * applicable to Cortex-M55 and Cortex-M85 ports as M-Profile Vector Extension
+ * (MVE) is available only on these architectures. configENABLE_MVE must be left
+ * undefined, or defined to 0 for the Cortex-M23,Cortex-M33 and Cortex-M35P
+ * ports. */
 #define configENABLE_MVE                  1
 
 /******************************************************************************/
 /* ARMv7-M and ARMv8-M port Specific Configuration definitions. ***************/
 /******************************************************************************/
 
-/* Set configCHECK_HANDLER_INSTALLATION to 1 to enable additional asserts to verify
- * that the application has correctly installed FreeRTOS interrupt handlers.
+/* Set configCHECK_HANDLER_INSTALLATION to 1 to enable additional asserts to
+ * verify that the application has correctly installed FreeRTOS interrupt
+ * handlers.
  *
- * An application can install FreeRTOS interrupt handlers in one of the following ways:
- *   1. Direct Routing  -  Install the functions vPortSVCHandler and xPortPendSVHandler
- *                         for SVC call and PendSV interrupts respectively.
+ * An application can install FreeRTOS interrupt handlers in one of the
+ * following ways:
+ *   1. Direct Routing  -  Install the functions vPortSVCHandler and
+ * xPortPendSVHandler for SVC call and PendSV interrupts respectively.
  *   2. Indirect Routing - Install separate handlers for SVC call and PendSV
- *                         interrupts and route program control from those handlers
- *                         to vPortSVCHandler and xPortPendSVHandler functions.
- * The applications that use Indirect Routing must set configCHECK_HANDLER_INSTALLATION to 0.
+ *                         interrupts and route program control from those
+ * handlers to vPortSVCHandler and xPortPendSVHandler functions. The
+ * applications that use Indirect Routing must set
+ * configCHECK_HANDLER_INSTALLATION to 0.
  *
  * Defaults to 1 if left undefined. */
 #define configCHECK_HANDLER_INSTALLATION    1
@@ -624,6 +639,10 @@
 #define configUSE_QUEUE_SETS                   0
 #define configUSE_APPLICATION_TASK_TAG         0
 
+/* USE_POSIX_ERRNO enables the task global FreeRTOS_errno variable which will
+ * containthe most recent error for that task. */
+#define configUSE_POSIX_ERRNO                  0
+
 /* Set the following INCLUDE_* constants to 1 to incldue the named API function,
  * or 0 to exclude the named API function.  Most linkers will remove unused
  * functions even when the constant is 1. */

From 0801c91bc6c7a6cfd6e248a07d952619fc144653 Mon Sep 17 00:00:00 2001
From: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Date: Thu, 16 May 2024 21:11:05 +0530
Subject: [PATCH 277/424] Add Noreturn attribute in template port for static
 analysis (#1060)

* Add _Noreturn attribute in the template function to fix MISRA 17.11 advisory warnings

* Add _Noreturn attribute in function declaration

* Code review suggestions
---
 examples/cmake_example/main.c | 6 ++++--
 portable/template/portmacro.h | 2 +-
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/examples/cmake_example/main.c b/examples/cmake_example/main.c
index 00c5405b3..b7ced4dd9 100644
--- a/examples/cmake_example/main.c
+++ b/examples/cmake_example/main.c
@@ -45,7 +45,7 @@
 
 /*-----------------------------------------------------------*/
 
-static void exampleTask( void * parameters );
+static void exampleTask( void * parameters ) __attribute__( ( noreturn ) );
 
 /*-----------------------------------------------------------*/
 
@@ -62,7 +62,7 @@ static void exampleTask( void * parameters )
 }
 /*-----------------------------------------------------------*/
 
-void main( void )
+int main( void )
 {
     static StaticTask_t exampleTaskTCB;
     static StackType_t exampleTaskStack[ configMINIMAL_STACK_SIZE ];
@@ -84,6 +84,8 @@ void main( void )
     {
         /* Should not reach here. */
     }
+
+    return 0;
 }
 /*-----------------------------------------------------------*/
 
diff --git a/portable/template/portmacro.h b/portable/template/portmacro.h
index 90668043c..4a4a5876c 100644
--- a/portable/template/portmacro.h
+++ b/portable/template/portmacro.h
@@ -105,7 +105,7 @@ extern void vPortYield( void );
 #define portYIELD()                                           vPortYield()
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters ) __attribute__( ( noreturn ) )
 #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 
 #if ( configNUMBER_OF_CORES > 1 )

From 9697f8c9b0ac155093751d9654f39c39b417abff Mon Sep 17 00:00:00 2001
From: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Date: Mon, 20 May 2024 14:24:54 +0530
Subject: [PATCH 278/424] Update documentation of prvGetExpectedIdleTime
 (#1061)

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 tasks.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/tasks.c b/tasks.c
index 3423becd4..db158f655 100644
--- a/tasks.c
+++ b/tasks.c
@@ -662,7 +662,8 @@ static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait,
 
 /*
  * Return the amount of time, in ticks, that will pass before the kernel will
- * next move a task from the Blocked state to the Running state.
+ * next move a task from the Blocked state to the Running state or before the
+ * tick count overflows (whichever is earlier).
  *
  * This conditional compilation should use inequality to 0, not equality to 1.
  * This is to ensure portSUPPRESS_TICKS_AND_SLEEP() can be called when user

From 27c4feff665a0bdcb447735d6c3d60664f2cc3f0 Mon Sep 17 00:00:00 2001
From: Florian La Roche <florian.laroche@gmail.com>
Date: Thu, 23 May 2024 11:51:29 +0200
Subject: [PATCH 279/424] typo: add space to
 examples/template_configuration/FreeRTOSConfig.h (#1069)

Signed-off-by: Florian La Roche <Florian.LaRoche@gmail.com>
---
 examples/template_configuration/FreeRTOSConfig.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/examples/template_configuration/FreeRTOSConfig.h b/examples/template_configuration/FreeRTOSConfig.h
index c35630bd1..fe21f1108 100644
--- a/examples/template_configuration/FreeRTOSConfig.h
+++ b/examples/template_configuration/FreeRTOSConfig.h
@@ -640,7 +640,7 @@
 #define configUSE_APPLICATION_TASK_TAG         0
 
 /* USE_POSIX_ERRNO enables the task global FreeRTOS_errno variable which will
- * containthe most recent error for that task. */
+ * contain the most recent error for that task. */
 #define configUSE_POSIX_ERRNO                  0
 
 /* Set the following INCLUDE_* constants to 1 to incldue the named API function,

From ef22228bdae4fbeedd9b6baec484053755d9bee0 Mon Sep 17 00:00:00 2001
From: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Date: Fri, 24 May 2024 12:53:54 +0530
Subject: [PATCH 280/424] Change UBaseType_t to BaseType_t for a boolean
 variable (#1072)

---
 tasks.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/tasks.c b/tasks.c
index db158f655..a049d64fe 100644
--- a/tasks.c
+++ b/tasks.c
@@ -3895,9 +3895,9 @@ void vTaskSuspendAll( void )
     static TickType_t prvGetExpectedIdleTime( void )
     {
         TickType_t xReturn;
-        UBaseType_t uxHigherPriorityReadyTasks = pdFALSE;
+        BaseType_t xHigherPriorityReadyTasks = pdFALSE;
 
-        /* uxHigherPriorityReadyTasks takes care of the case where
+        /* xHigherPriorityReadyTasks takes care of the case where
          * configUSE_PREEMPTION is 0, so there may be tasks above the idle priority
          * task that are in the Ready state, even though the idle task is
          * running. */
@@ -3905,7 +3905,7 @@ void vTaskSuspendAll( void )
         {
             if( uxTopReadyPriority > tskIDLE_PRIORITY )
             {
-                uxHigherPriorityReadyTasks = pdTRUE;
+                xHigherPriorityReadyTasks = pdTRUE;
             }
         }
         #else
@@ -3919,7 +3919,7 @@ void vTaskSuspendAll( void )
              * care of the case where the co-operative scheduler is in use. */
             if( uxTopReadyPriority > uxLeastSignificantBit )
             {
-                uxHigherPriorityReadyTasks = pdTRUE;
+                xHigherPriorityReadyTasks = pdTRUE;
             }
         }
         #endif /* if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 ) */
@@ -3935,7 +3935,7 @@ void vTaskSuspendAll( void )
              * processed. */
             xReturn = 0;
         }
-        else if( uxHigherPriorityReadyTasks != pdFALSE )
+        else if( xHigherPriorityReadyTasks != pdFALSE )
         {
             /* There are tasks in the Ready state that have a priority above the
              * idle priority.  This path can only be reached if

From 9f22177c02b03df2fc563482f11df4e710604287 Mon Sep 17 00:00:00 2001
From: wdfk-prog <1425075683@qq.com>
Date: Thu, 30 May 2024 02:13:07 +0800
Subject: [PATCH 281/424] Readability enhancements in heap_1.c (#1074)

* Remove  that Heap_1.c unnecessary judgment and code logic

* Remove useless alignment calculations and increase heap usage size

* Revert "Remove useless alignment calculations and increase heap usage size"

This reverts commit 7832a4bc118661676c4aaa377e412c35ec0b728c.

* Readability improvements

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: huangly <huangly@milesight.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 portable/MemMang/heap_1.c | 33 +++++++++++++++++++++++----------
 1 file changed, 23 insertions(+), 10 deletions(-)

diff --git a/portable/MemMang/heap_1.c b/portable/MemMang/heap_1.c
index 68f14bd37..0f7661356 100644
--- a/portable/MemMang/heap_1.c
+++ b/portable/MemMang/heap_1.c
@@ -51,7 +51,15 @@
 #endif
 
 /* A few bytes might be lost to byte aligning the heap start address. */
-#define configADJUSTED_HEAP_SIZE    ( configTOTAL_HEAP_SIZE - portBYTE_ALIGNMENT )
+#define configADJUSTED_HEAP_SIZE        ( configTOTAL_HEAP_SIZE - portBYTE_ALIGNMENT )
+
+/* Max value that fits in a size_t type. */
+#define heapSIZE_MAX                    ( ~( ( size_t ) 0 ) )
+
+/* Check if adding a and b will result in overflow. */
+#define heapADD_WILL_OVERFLOW( a, b )   ( ( a ) > ( heapSIZE_MAX - ( b ) ) )
+
+/*-----------------------------------------------------------*/
 
 /* Allocate the memory for the heap. */
 #if ( configAPPLICATION_ALLOCATED_HEAP == 1 )
@@ -76,12 +84,16 @@ void * pvPortMalloc( size_t xWantedSize )
     /* Ensure that blocks are always aligned. */
     #if ( portBYTE_ALIGNMENT != 1 )
     {
-        if( xWantedSize & portBYTE_ALIGNMENT_MASK )
+        size_t xAdditionalRequiredSize;
+
+        if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
         {
-            /* Byte alignment required. Check for overflow. */
-            if( ( xWantedSize + ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) ) ) > xWantedSize )
+            /* Byte alignment required. */
+            xAdditionalRequiredSize = portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK );
+
+            if( heapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 )
             {
-                xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
+                xWantedSize += xAdditionalRequiredSize;
             }
             else
             {
@@ -96,13 +108,14 @@ void * pvPortMalloc( size_t xWantedSize )
         if( pucAlignedHeap == NULL )
         {
             /* Ensure the heap starts on a correctly aligned boundary. */
-            pucAlignedHeap = ( uint8_t * ) ( ( ( portPOINTER_SIZE_TYPE ) & ucHeap[ portBYTE_ALIGNMENT - 1 ] ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) );
+            pucAlignedHeap = ( uint8_t * ) ( ( ( portPOINTER_SIZE_TYPE ) &( ucHeap[ portBYTE_ALIGNMENT - 1 ] ) ) &
+                                             ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) );
         }
 
-        /* Check there is enough room left for the allocation and. */
-        if( ( xWantedSize > 0 ) &&                                /* valid size */
-            ( ( xNextFreeByte + xWantedSize ) < configADJUSTED_HEAP_SIZE ) &&
-            ( ( xNextFreeByte + xWantedSize ) > xNextFreeByte ) ) /* Check for overflow. */
+        /* Check there is enough room left for the allocation. */
+        if( ( xWantedSize > 0 ) &&
+            ( heapADD_WILL_OVERFLOW( xNextFreeByte, xWantedSize ) == 0 ) &&
+            ( ( xNextFreeByte + xWantedSize ) < configADJUSTED_HEAP_SIZE ) )
         {
             /* Return the next free byte then increment the index past this
              * block. */

From 65e6297b68aca587eb22b145aee23e479e1af8b3 Mon Sep 17 00:00:00 2001
From: Ethan Slattery <9755578+CrustyAuklet@users.noreply.github.com>
Date: Sun, 19 May 2024 19:03:30 -0700
Subject: [PATCH 282/424] Add missing Extern "C" to MSVC portmacro.h

---
 portable/MSVC-MingW/portmacro.h | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/portable/MSVC-MingW/portmacro.h b/portable/MSVC-MingW/portmacro.h
index d3db1eb62..288b7b037 100644
--- a/portable/MSVC-MingW/portmacro.h
+++ b/portable/MSVC-MingW/portmacro.h
@@ -40,6 +40,10 @@
 #include <mmsystem.h>
 #include <winbase.h>
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /******************************************************************************
 *   Defines
 ******************************************************************************/
@@ -215,4 +219,8 @@ void vPortGenerateSimulatedInterruptFromWindowsThread( uint32_t ulInterruptNumbe
 void vPortSetInterruptHandler( uint32_t ulInterruptNumber,
                                uint32_t ( * pvHandler )( void ) );
 
+#ifdef __cplusplus
+}
+#endif
+
 #endif /* ifndef PORTMACRO_H */

From 69e1b7c64a09ac9901634b2feac2ab324ec9328f Mon Sep 17 00:00:00 2001
From: Philipp Schilk <schilk.philipp@gmail.com>
Date: Thu, 6 Jun 2024 06:53:34 +0200
Subject: [PATCH 283/424] Clarify documentation of xTaskNumber in TaskStatus_t.
 (#1081)

Discussed here: https://forums.freertos.org/t/tracing-improvements/20097

Adds a note to the (confusingly named) xTaskNumber member of TaskStatus_t
explaining that the value is different to the TaskNumber that can be
accessed using the vTaskSetTaskNumber and vTaskGetTaskNumber functions.

The value returned is actually the value of uxTCBNumber in the TCB.
---
 include/task.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/task.h b/include/task.h
index b638bddd2..1ca800585 100644
--- a/include/task.h
+++ b/include/task.h
@@ -161,7 +161,7 @@ typedef struct xTASK_STATUS
 {
     TaskHandle_t xHandle;                         /* The handle of the task to which the rest of the information in the structure relates. */
     const char * pcTaskName;                      /* A pointer to the task's name.  This value will be invalid if the task was deleted since the structure was populated! */
-    UBaseType_t xTaskNumber;                      /* A number unique to the task. */
+    UBaseType_t xTaskNumber;                      /* A number unique to the task. Note that this is not the task number that may be modified using vTaskSetTaskNumber() and uxTaskGetTaskNumber(), but a separate TCB-specific and unique identifier automatically assigned on task generation. */
     eTaskState eCurrentState;                     /* The state in which the task existed when the structure was populated. */
     UBaseType_t uxCurrentPriority;                /* The priority at which the task was running (may be inherited) when the structure was populated. */
     UBaseType_t uxBasePriority;                   /* The priority to which the task will return if the task's current priority has been inherited to avoid unbounded priority inversion when obtaining a mutex.  Only valid if configUSE_MUTEXES is defined as 1 in FreeRTOSConfig.h. */

From 5a0898288d27be8db53e1eb156cf0578502e1676 Mon Sep 17 00:00:00 2001
From: Philipp Schilk <schilk.philipp@gmail.com>
Date: Thu, 6 Jun 2024 17:36:09 +0200
Subject: [PATCH 284/424] Give queue set queues a unique type number. (#1083)

Discussed here: https://forums.freertos.org/t/tracing-improvements/20097

Changes the value of queueQUEUE_TYPE_SET to a unique value (5) to allow
tracers to differentiate between normal queues and queue sets.

Co-authored-by: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
---
 include/queue.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/queue.h b/include/queue.h
index 1e56c35f1..62d095a8e 100644
--- a/include/queue.h
+++ b/include/queue.h
@@ -71,11 +71,11 @@ typedef struct QueueDefinition   * QueueSetMemberHandle_t;
 
 /* For internal use only.  These definitions *must* match those in queue.c. */
 #define queueQUEUE_TYPE_BASE                  ( ( uint8_t ) 0U )
-#define queueQUEUE_TYPE_SET                   ( ( uint8_t ) 0U )
 #define queueQUEUE_TYPE_MUTEX                 ( ( uint8_t ) 1U )
 #define queueQUEUE_TYPE_COUNTING_SEMAPHORE    ( ( uint8_t ) 2U )
 #define queueQUEUE_TYPE_BINARY_SEMAPHORE      ( ( uint8_t ) 3U )
 #define queueQUEUE_TYPE_RECURSIVE_MUTEX       ( ( uint8_t ) 4U )
+#define queueQUEUE_TYPE_SET                   ( ( uint8_t ) 5U )
 
 /**
  * queue. h

From 11174fb860ae4aaca544b2ad12df040b81a132e3 Mon Sep 17 00:00:00 2001
From: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Date: Fri, 7 Jun 2024 11:50:56 +0530
Subject: [PATCH 285/424] Add a list of third party tools (#1080)

* Add a list of third party tools

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 .github/third_party_tools.md | 14 ++++++++++++++
 README.md                    |  4 ++++
 2 files changed, 18 insertions(+)
 create mode 100644 .github/third_party_tools.md

diff --git a/.github/third_party_tools.md b/.github/third_party_tools.md
new file mode 100644
index 000000000..6d5d02fa5
--- /dev/null
+++ b/.github/third_party_tools.md
@@ -0,0 +1,14 @@
+Note that these tools are provided by different vendors and not by the FreeRTOS
+team.
+
+## Tracing Tools
+| Tool | Website | Getting Started |
+|------|---------|-----------------|
+| Tracelyzer | [Link](https://percepio.com/tracealyzer/freertostrace/) | [Link](https://percepio.com/getstarted/latest/html/freertos.html) |
+| SystemView | [Link](https://www.segger.com/products/development-tools/systemview/) | [Link](https://wiki.segger.com/FreeRTOS_with_SystemView) |
+
+## Static Code Analysis Tools
+| Tool | Website | Getting Started |
+|------|---------|-----------------|
+| Code Sonar | [Link](https://codesecure.com/our-products/codesonar/) | [Link](https://github.com/CodeSecure-SE/FreeRTOS-Kernel) |
+| Coverity | [Link](https://www.synopsys.com/software-integrity/security-testing/static-analysis-sast.html) | [Link](../examples/coverity/README.md) |
diff --git a/README.md b/README.md
index 7a60f3594..ce34d56ab 100644
--- a/README.md
+++ b/README.md
@@ -180,3 +180,7 @@ then sort the list, which can be done by running the bash command:
 Note that only the FreeRTOS-Kernel Source Files, [include](include),
 [portable/MemMang](portable/MemMang), and [portable/Common](portable/Common)
 files are checked for proper spelling, and formatting at this time.
+
+## Third Party Tools
+Visit [this link](.github/third_party_tools.md) for detailed information about
+third-party tools with FreeRTOS support.

From c431b358c802e1ec207ecbf3f68c34e9b2a17f46 Mon Sep 17 00:00:00 2001
From: Florian La Roche <florian.laroche@gmail.com>
Date: Fri, 7 Jun 2024 10:17:13 +0200
Subject: [PATCH 286/424] event_create(): check malloc() return value to be
 non-NULL (#1084)

* event_create(): check malloc() to be non-NULL

Check malloc() to return non-NULL before writing data
in the function event_create().

Signed-off-by: Florian La Roche <Florian.LaRoche@gmail.com>

* Code review suggestion

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Florian La Roche <Florian.LaRoche@gmail.com>
Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 portable/ThirdParty/GCC/Posix/utils/wait_for_event.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/portable/ThirdParty/GCC/Posix/utils/wait_for_event.c b/portable/ThirdParty/GCC/Posix/utils/wait_for_event.c
index beca2b360..bf744e27f 100644
--- a/portable/ThirdParty/GCC/Posix/utils/wait_for_event.c
+++ b/portable/ThirdParty/GCC/Posix/utils/wait_for_event.c
@@ -43,9 +43,13 @@ struct event * event_create( void )
 {
     struct event * ev = malloc( sizeof( struct event ) );
 
-    ev->event_triggered = false;
-    pthread_mutex_init( &ev->mutex, NULL );
-    pthread_cond_init( &ev->cond, NULL );
+    if( ev != NULL )
+    {
+        ev->event_triggered = false;
+        pthread_mutex_init( &ev->mutex, NULL );
+        pthread_cond_init( &ev->cond, NULL );
+    }
+
     return ev;
 }
 

From bee9037c464d3ba4c1ef0684daee8c1b11efbc9a Mon Sep 17 00:00:00 2001
From: maxiao <maxiao@dreame.tech>
Date: Mon, 10 Jun 2024 18:32:04 +0800
Subject: [PATCH 287/424] Fix compilation warning about undelcared
 pthread_setname_np (#1079)

Use _GNU_SOURCE macro instead of __USE_GNU and define it before
including portmacro.h. The reason is that portmacro.h includes limits.h
which in-turn includes features.h - this results in __USE_GNU getting
incorrectly undefined.
---
 portable/ThirdParty/GCC/Posix/port.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/portable/ThirdParty/GCC/Posix/port.c b/portable/ThirdParty/GCC/Posix/port.c
index fdb556d04..05f08cf7c 100644
--- a/portable/ThirdParty/GCC/Posix/port.c
+++ b/portable/ThirdParty/GCC/Posix/port.c
@@ -49,12 +49,10 @@
 * only or serialized with a FreeRTOS primitive such as a binary
 * semaphore or mutex.
 *----------------------------------------------------------*/
-#include "portmacro.h"
-
 #ifdef __linux__
-    #define __USE_GNU
+    #define _GNU_SOURCE
 #endif
-
+#include "portmacro.h"
 #include <errno.h>
 #include <pthread.h>
 #include <limits.h>

From e64d1e06b3d9be7b1e14c169affaa9c9674e801c Mon Sep 17 00:00:00 2001
From: Philipp Schilk <schilk.philipp@gmail.com>
Date: Mon, 10 Jun 2024 19:44:10 +0200
Subject: [PATCH 288/424] Add traceSTARTING_SCHEDULER tracing hook. (#1082)

* Add traceSTARTING_SCHEDULER tracing hook.

Discussed here: https://forums.freertos.org/t/tracing-improvements/20097

This hook enables tracers to run code on startup after all RTOS
resources are created and to detect that the scheduler is starting without
relying on traceENTER/traceEXIT macros.

It also provides tracers access to the task handle of all IDLE tasks,
allowing them to be identified unambiguously and without relying on
INCLUDE_xTaskGetIdleTaskHandle.
---
 include/FreeRTOS.h | 7 +++++++
 tasks.c            | 2 ++
 2 files changed, 9 insertions(+)

diff --git a/include/FreeRTOS.h b/include/FreeRTOS.h
index b972ffd10..4b59512c9 100644
--- a/include/FreeRTOS.h
+++ b/include/FreeRTOS.h
@@ -621,6 +621,13 @@
     #define traceTASK_SWITCHED_IN()
 #endif
 
+#ifndef traceSTARTING_SCHEDULER
+
+/* Called after all idle tasks and timer task (if enabled) have been created
+ * successfully, just before the scheduler is started. */
+    #define traceSTARTING_SCHEDULER( xIdleTaskHandles )
+#endif
+
 #ifndef traceINCREASE_TICK_COUNT
 
 /* Called before stepping the tick count after waking from tickless idle
diff --git a/tasks.c b/tasks.c
index a049d64fe..f8740257c 100644
--- a/tasks.c
+++ b/tasks.c
@@ -3732,6 +3732,8 @@ void vTaskStartScheduler( void )
 
         traceTASK_SWITCHED_IN();
 
+        traceSTARTING_SCHEDULER( xIdleTaskHandles );
+
         /* Setting up the timer tick is hardware specific and thus in the
          * portable interface. */
 

From 28b6a141eab7c352d981b40150e58664394e6c67 Mon Sep 17 00:00:00 2001
From: haydenridd <haydenridd@gmail.com>
Date: Mon, 10 Jun 2024 22:00:08 -0700
Subject: [PATCH 289/424] - Changed macro __VFP_FP__ to __ARM_FP for ports
 GCC/ARM_CM7, GCC/ARM_CM4_MPU, and GCC/ARM_CM4F to accurately reflect if
 floating point hardware support is enabled (#1088)

Co-authored-by: Hayden Riddiford <hayden@terrakaffe.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
---
 portable/GCC/ARM_CM4F/port.c     | 2 +-
 portable/GCC/ARM_CM4_MPU/port.c  | 2 +-
 portable/GCC/ARM_CM7/r0p1/port.c | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/portable/GCC/ARM_CM4F/port.c b/portable/GCC/ARM_CM4F/port.c
index c836999ec..532bbce88 100644
--- a/portable/GCC/ARM_CM4F/port.c
+++ b/portable/GCC/ARM_CM4F/port.c
@@ -34,7 +34,7 @@
 #include "FreeRTOS.h"
 #include "task.h"
 
-#ifndef __VFP_FP__
+#ifndef __ARM_FP
     #error This port can only be used when the project options are configured to enable hardware floating point support.
 #endif
 
diff --git a/portable/GCC/ARM_CM4_MPU/port.c b/portable/GCC/ARM_CM4_MPU/port.c
index 6e6f9de75..68b2ab13f 100644
--- a/portable/GCC/ARM_CM4_MPU/port.c
+++ b/portable/GCC/ARM_CM4_MPU/port.c
@@ -40,7 +40,7 @@
 #include "task.h"
 #include "mpu_syscall_numbers.h"
 
-#ifndef __VFP_FP__
+#ifndef __ARM_FP
     #error This port can only be used when the project options are configured to enable hardware floating point support.
 #endif
 
diff --git a/portable/GCC/ARM_CM7/r0p1/port.c b/portable/GCC/ARM_CM7/r0p1/port.c
index aaac2a7cb..ac067274d 100644
--- a/portable/GCC/ARM_CM7/r0p1/port.c
+++ b/portable/GCC/ARM_CM7/r0p1/port.c
@@ -34,7 +34,7 @@
 #include "FreeRTOS.h"
 #include "task.h"
 
-#ifndef __VFP_FP__
+#ifndef __ARM_FP
     #error This port can only be used when the project options are configured to enable hardware floating point support.
 #endif
 

From 663eaad1b2ce493bae866188554564d4a41d5463 Mon Sep 17 00:00:00 2001
From: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Date: Wed, 12 Jun 2024 13:43:43 +0530
Subject: [PATCH 290/424] Update link in third_party_tools.md (#1090)

Update the link to the getting started guide for Code Sonar.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
---
 .github/third_party_tools.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.github/third_party_tools.md b/.github/third_party_tools.md
index 6d5d02fa5..afe84b257 100644
--- a/.github/third_party_tools.md
+++ b/.github/third_party_tools.md
@@ -10,5 +10,5 @@ team.
 ## Static Code Analysis Tools
 | Tool | Website | Getting Started |
 |------|---------|-----------------|
-| Code Sonar | [Link](https://codesecure.com/our-products/codesonar/) | [Link](https://github.com/CodeSecure-SE/FreeRTOS-Kernel) |
+| Code Sonar | [Link](https://codesecure.com/our-products/codesonar/) | [Link](https://github.com/CodeSecure-SE/FreeRTOS-Kernel/blob/main/examples/codesonar/README.md) |
 | Coverity | [Link](https://www.synopsys.com/software-integrity/security-testing/static-analysis-sast.html) | [Link](../examples/coverity/README.md) |

From 76eb44382178237197a2c4982f9d99e8d64c9599 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=E8=80=80=E7=9C=BC=E7=9A=84=E5=A4=A7=E7=A5=9E?=
 <31402964+DazzlingOkami@users.noreply.github.com>
Date: Thu, 13 Jun 2024 13:25:54 +0800
Subject: [PATCH 291/424] Fix traceMALLOC() allocated bytes (#1089)

* Fix traceMALLOC() memory count is inaccurate. (#1078)

Modify xWantedSize to the size of a free block when not split blocks.

Ensure that the sizes within traceMALLOC() and traceFREE() macros are equal.

* Create a new variable xAllocatedBlockSize for traceMALLOC()

---------

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
---
 portable/ARMv8M/secure/heap/secure_heap.c   | 8 +++++++-
 portable/GCC/ARM_CM23/secure/secure_heap.c  | 8 +++++++-
 portable/GCC/ARM_CM33/secure/secure_heap.c  | 8 +++++++-
 portable/GCC/ARM_CM35P/secure/secure_heap.c | 8 +++++++-
 portable/GCC/ARM_CM55/secure/secure_heap.c  | 8 +++++++-
 portable/GCC/ARM_CM85/secure/secure_heap.c  | 8 +++++++-
 portable/IAR/ARM_CM23/secure/secure_heap.c  | 8 +++++++-
 portable/IAR/ARM_CM33/secure/secure_heap.c  | 8 +++++++-
 portable/IAR/ARM_CM35P/secure/secure_heap.c | 8 +++++++-
 portable/IAR/ARM_CM55/secure/secure_heap.c  | 8 +++++++-
 portable/IAR/ARM_CM85/secure/secure_heap.c  | 8 +++++++-
 portable/MemMang/heap_2.c                   | 8 +++++++-
 portable/MemMang/heap_4.c                   | 8 +++++++-
 portable/MemMang/heap_5.c                   | 8 +++++++-
 14 files changed, 98 insertions(+), 14 deletions(-)

diff --git a/portable/ARMv8M/secure/heap/secure_heap.c b/portable/ARMv8M/secure/heap/secure_heap.c
index 4fa6a2ffa..55722d4e7 100644
--- a/portable/ARMv8M/secure/heap/secure_heap.c
+++ b/portable/ARMv8M/secure/heap/secure_heap.c
@@ -256,6 +256,7 @@ void * pvPortMalloc( size_t xWantedSize )
     BlockLink_t * pxNewBlockLink;
     void * pvReturn = NULL;
     size_t xAdditionalRequiredSize;
+    size_t xAllocatedBlockSize = 0;
 
     /* If this is the first call to malloc then the heap will require
      * initialisation to setup the list of free blocks. */
@@ -374,6 +375,8 @@ void * pvPortMalloc( size_t xWantedSize )
                     mtCOVERAGE_TEST_MARKER();
                 }
 
+                xAllocatedBlockSize = pxBlock->xBlockSize;
+
                 /* The block is being returned - it is allocated and owned by
                  * the application and has no "next" block. */
                 secureheapALLOCATE_BLOCK( pxBlock );
@@ -394,7 +397,10 @@ void * pvPortMalloc( size_t xWantedSize )
         mtCOVERAGE_TEST_MARKER();
     }
 
-    traceMALLOC( pvReturn, xWantedSize );
+    traceMALLOC( pvReturn, xAllocatedBlockSize );
+
+    /* Prevent compiler warnings when trace macros are not used. */
+    ( void ) xAllocatedBlockSize;
 
     #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
     {
diff --git a/portable/GCC/ARM_CM23/secure/secure_heap.c b/portable/GCC/ARM_CM23/secure/secure_heap.c
index 4fa6a2ffa..55722d4e7 100644
--- a/portable/GCC/ARM_CM23/secure/secure_heap.c
+++ b/portable/GCC/ARM_CM23/secure/secure_heap.c
@@ -256,6 +256,7 @@ void * pvPortMalloc( size_t xWantedSize )
     BlockLink_t * pxNewBlockLink;
     void * pvReturn = NULL;
     size_t xAdditionalRequiredSize;
+    size_t xAllocatedBlockSize = 0;
 
     /* If this is the first call to malloc then the heap will require
      * initialisation to setup the list of free blocks. */
@@ -374,6 +375,8 @@ void * pvPortMalloc( size_t xWantedSize )
                     mtCOVERAGE_TEST_MARKER();
                 }
 
+                xAllocatedBlockSize = pxBlock->xBlockSize;
+
                 /* The block is being returned - it is allocated and owned by
                  * the application and has no "next" block. */
                 secureheapALLOCATE_BLOCK( pxBlock );
@@ -394,7 +397,10 @@ void * pvPortMalloc( size_t xWantedSize )
         mtCOVERAGE_TEST_MARKER();
     }
 
-    traceMALLOC( pvReturn, xWantedSize );
+    traceMALLOC( pvReturn, xAllocatedBlockSize );
+
+    /* Prevent compiler warnings when trace macros are not used. */
+    ( void ) xAllocatedBlockSize;
 
     #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
     {
diff --git a/portable/GCC/ARM_CM33/secure/secure_heap.c b/portable/GCC/ARM_CM33/secure/secure_heap.c
index 4fa6a2ffa..55722d4e7 100644
--- a/portable/GCC/ARM_CM33/secure/secure_heap.c
+++ b/portable/GCC/ARM_CM33/secure/secure_heap.c
@@ -256,6 +256,7 @@ void * pvPortMalloc( size_t xWantedSize )
     BlockLink_t * pxNewBlockLink;
     void * pvReturn = NULL;
     size_t xAdditionalRequiredSize;
+    size_t xAllocatedBlockSize = 0;
 
     /* If this is the first call to malloc then the heap will require
      * initialisation to setup the list of free blocks. */
@@ -374,6 +375,8 @@ void * pvPortMalloc( size_t xWantedSize )
                     mtCOVERAGE_TEST_MARKER();
                 }
 
+                xAllocatedBlockSize = pxBlock->xBlockSize;
+
                 /* The block is being returned - it is allocated and owned by
                  * the application and has no "next" block. */
                 secureheapALLOCATE_BLOCK( pxBlock );
@@ -394,7 +397,10 @@ void * pvPortMalloc( size_t xWantedSize )
         mtCOVERAGE_TEST_MARKER();
     }
 
-    traceMALLOC( pvReturn, xWantedSize );
+    traceMALLOC( pvReturn, xAllocatedBlockSize );
+
+    /* Prevent compiler warnings when trace macros are not used. */
+    ( void ) xAllocatedBlockSize;
 
     #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
     {
diff --git a/portable/GCC/ARM_CM35P/secure/secure_heap.c b/portable/GCC/ARM_CM35P/secure/secure_heap.c
index 4fa6a2ffa..55722d4e7 100644
--- a/portable/GCC/ARM_CM35P/secure/secure_heap.c
+++ b/portable/GCC/ARM_CM35P/secure/secure_heap.c
@@ -256,6 +256,7 @@ void * pvPortMalloc( size_t xWantedSize )
     BlockLink_t * pxNewBlockLink;
     void * pvReturn = NULL;
     size_t xAdditionalRequiredSize;
+    size_t xAllocatedBlockSize = 0;
 
     /* If this is the first call to malloc then the heap will require
      * initialisation to setup the list of free blocks. */
@@ -374,6 +375,8 @@ void * pvPortMalloc( size_t xWantedSize )
                     mtCOVERAGE_TEST_MARKER();
                 }
 
+                xAllocatedBlockSize = pxBlock->xBlockSize;
+
                 /* The block is being returned - it is allocated and owned by
                  * the application and has no "next" block. */
                 secureheapALLOCATE_BLOCK( pxBlock );
@@ -394,7 +397,10 @@ void * pvPortMalloc( size_t xWantedSize )
         mtCOVERAGE_TEST_MARKER();
     }
 
-    traceMALLOC( pvReturn, xWantedSize );
+    traceMALLOC( pvReturn, xAllocatedBlockSize );
+
+    /* Prevent compiler warnings when trace macros are not used. */
+    ( void ) xAllocatedBlockSize;
 
     #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
     {
diff --git a/portable/GCC/ARM_CM55/secure/secure_heap.c b/portable/GCC/ARM_CM55/secure/secure_heap.c
index 4fa6a2ffa..55722d4e7 100644
--- a/portable/GCC/ARM_CM55/secure/secure_heap.c
+++ b/portable/GCC/ARM_CM55/secure/secure_heap.c
@@ -256,6 +256,7 @@ void * pvPortMalloc( size_t xWantedSize )
     BlockLink_t * pxNewBlockLink;
     void * pvReturn = NULL;
     size_t xAdditionalRequiredSize;
+    size_t xAllocatedBlockSize = 0;
 
     /* If this is the first call to malloc then the heap will require
      * initialisation to setup the list of free blocks. */
@@ -374,6 +375,8 @@ void * pvPortMalloc( size_t xWantedSize )
                     mtCOVERAGE_TEST_MARKER();
                 }
 
+                xAllocatedBlockSize = pxBlock->xBlockSize;
+
                 /* The block is being returned - it is allocated and owned by
                  * the application and has no "next" block. */
                 secureheapALLOCATE_BLOCK( pxBlock );
@@ -394,7 +397,10 @@ void * pvPortMalloc( size_t xWantedSize )
         mtCOVERAGE_TEST_MARKER();
     }
 
-    traceMALLOC( pvReturn, xWantedSize );
+    traceMALLOC( pvReturn, xAllocatedBlockSize );
+
+    /* Prevent compiler warnings when trace macros are not used. */
+    ( void ) xAllocatedBlockSize;
 
     #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
     {
diff --git a/portable/GCC/ARM_CM85/secure/secure_heap.c b/portable/GCC/ARM_CM85/secure/secure_heap.c
index 4fa6a2ffa..55722d4e7 100644
--- a/portable/GCC/ARM_CM85/secure/secure_heap.c
+++ b/portable/GCC/ARM_CM85/secure/secure_heap.c
@@ -256,6 +256,7 @@ void * pvPortMalloc( size_t xWantedSize )
     BlockLink_t * pxNewBlockLink;
     void * pvReturn = NULL;
     size_t xAdditionalRequiredSize;
+    size_t xAllocatedBlockSize = 0;
 
     /* If this is the first call to malloc then the heap will require
      * initialisation to setup the list of free blocks. */
@@ -374,6 +375,8 @@ void * pvPortMalloc( size_t xWantedSize )
                     mtCOVERAGE_TEST_MARKER();
                 }
 
+                xAllocatedBlockSize = pxBlock->xBlockSize;
+
                 /* The block is being returned - it is allocated and owned by
                  * the application and has no "next" block. */
                 secureheapALLOCATE_BLOCK( pxBlock );
@@ -394,7 +397,10 @@ void * pvPortMalloc( size_t xWantedSize )
         mtCOVERAGE_TEST_MARKER();
     }
 
-    traceMALLOC( pvReturn, xWantedSize );
+    traceMALLOC( pvReturn, xAllocatedBlockSize );
+
+    /* Prevent compiler warnings when trace macros are not used. */
+    ( void ) xAllocatedBlockSize;
 
     #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
     {
diff --git a/portable/IAR/ARM_CM23/secure/secure_heap.c b/portable/IAR/ARM_CM23/secure/secure_heap.c
index 4fa6a2ffa..55722d4e7 100644
--- a/portable/IAR/ARM_CM23/secure/secure_heap.c
+++ b/portable/IAR/ARM_CM23/secure/secure_heap.c
@@ -256,6 +256,7 @@ void * pvPortMalloc( size_t xWantedSize )
     BlockLink_t * pxNewBlockLink;
     void * pvReturn = NULL;
     size_t xAdditionalRequiredSize;
+    size_t xAllocatedBlockSize = 0;
 
     /* If this is the first call to malloc then the heap will require
      * initialisation to setup the list of free blocks. */
@@ -374,6 +375,8 @@ void * pvPortMalloc( size_t xWantedSize )
                     mtCOVERAGE_TEST_MARKER();
                 }
 
+                xAllocatedBlockSize = pxBlock->xBlockSize;
+
                 /* The block is being returned - it is allocated and owned by
                  * the application and has no "next" block. */
                 secureheapALLOCATE_BLOCK( pxBlock );
@@ -394,7 +397,10 @@ void * pvPortMalloc( size_t xWantedSize )
         mtCOVERAGE_TEST_MARKER();
     }
 
-    traceMALLOC( pvReturn, xWantedSize );
+    traceMALLOC( pvReturn, xAllocatedBlockSize );
+
+    /* Prevent compiler warnings when trace macros are not used. */
+    ( void ) xAllocatedBlockSize;
 
     #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
     {
diff --git a/portable/IAR/ARM_CM33/secure/secure_heap.c b/portable/IAR/ARM_CM33/secure/secure_heap.c
index 4fa6a2ffa..55722d4e7 100644
--- a/portable/IAR/ARM_CM33/secure/secure_heap.c
+++ b/portable/IAR/ARM_CM33/secure/secure_heap.c
@@ -256,6 +256,7 @@ void * pvPortMalloc( size_t xWantedSize )
     BlockLink_t * pxNewBlockLink;
     void * pvReturn = NULL;
     size_t xAdditionalRequiredSize;
+    size_t xAllocatedBlockSize = 0;
 
     /* If this is the first call to malloc then the heap will require
      * initialisation to setup the list of free blocks. */
@@ -374,6 +375,8 @@ void * pvPortMalloc( size_t xWantedSize )
                     mtCOVERAGE_TEST_MARKER();
                 }
 
+                xAllocatedBlockSize = pxBlock->xBlockSize;
+
                 /* The block is being returned - it is allocated and owned by
                  * the application and has no "next" block. */
                 secureheapALLOCATE_BLOCK( pxBlock );
@@ -394,7 +397,10 @@ void * pvPortMalloc( size_t xWantedSize )
         mtCOVERAGE_TEST_MARKER();
     }
 
-    traceMALLOC( pvReturn, xWantedSize );
+    traceMALLOC( pvReturn, xAllocatedBlockSize );
+
+    /* Prevent compiler warnings when trace macros are not used. */
+    ( void ) xAllocatedBlockSize;
 
     #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
     {
diff --git a/portable/IAR/ARM_CM35P/secure/secure_heap.c b/portable/IAR/ARM_CM35P/secure/secure_heap.c
index 4fa6a2ffa..55722d4e7 100644
--- a/portable/IAR/ARM_CM35P/secure/secure_heap.c
+++ b/portable/IAR/ARM_CM35P/secure/secure_heap.c
@@ -256,6 +256,7 @@ void * pvPortMalloc( size_t xWantedSize )
     BlockLink_t * pxNewBlockLink;
     void * pvReturn = NULL;
     size_t xAdditionalRequiredSize;
+    size_t xAllocatedBlockSize = 0;
 
     /* If this is the first call to malloc then the heap will require
      * initialisation to setup the list of free blocks. */
@@ -374,6 +375,8 @@ void * pvPortMalloc( size_t xWantedSize )
                     mtCOVERAGE_TEST_MARKER();
                 }
 
+                xAllocatedBlockSize = pxBlock->xBlockSize;
+
                 /* The block is being returned - it is allocated and owned by
                  * the application and has no "next" block. */
                 secureheapALLOCATE_BLOCK( pxBlock );
@@ -394,7 +397,10 @@ void * pvPortMalloc( size_t xWantedSize )
         mtCOVERAGE_TEST_MARKER();
     }
 
-    traceMALLOC( pvReturn, xWantedSize );
+    traceMALLOC( pvReturn, xAllocatedBlockSize );
+
+    /* Prevent compiler warnings when trace macros are not used. */
+    ( void ) xAllocatedBlockSize;
 
     #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
     {
diff --git a/portable/IAR/ARM_CM55/secure/secure_heap.c b/portable/IAR/ARM_CM55/secure/secure_heap.c
index 4fa6a2ffa..55722d4e7 100644
--- a/portable/IAR/ARM_CM55/secure/secure_heap.c
+++ b/portable/IAR/ARM_CM55/secure/secure_heap.c
@@ -256,6 +256,7 @@ void * pvPortMalloc( size_t xWantedSize )
     BlockLink_t * pxNewBlockLink;
     void * pvReturn = NULL;
     size_t xAdditionalRequiredSize;
+    size_t xAllocatedBlockSize = 0;
 
     /* If this is the first call to malloc then the heap will require
      * initialisation to setup the list of free blocks. */
@@ -374,6 +375,8 @@ void * pvPortMalloc( size_t xWantedSize )
                     mtCOVERAGE_TEST_MARKER();
                 }
 
+                xAllocatedBlockSize = pxBlock->xBlockSize;
+
                 /* The block is being returned - it is allocated and owned by
                  * the application and has no "next" block. */
                 secureheapALLOCATE_BLOCK( pxBlock );
@@ -394,7 +397,10 @@ void * pvPortMalloc( size_t xWantedSize )
         mtCOVERAGE_TEST_MARKER();
     }
 
-    traceMALLOC( pvReturn, xWantedSize );
+    traceMALLOC( pvReturn, xAllocatedBlockSize );
+
+    /* Prevent compiler warnings when trace macros are not used. */
+    ( void ) xAllocatedBlockSize;
 
     #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
     {
diff --git a/portable/IAR/ARM_CM85/secure/secure_heap.c b/portable/IAR/ARM_CM85/secure/secure_heap.c
index 4fa6a2ffa..55722d4e7 100644
--- a/portable/IAR/ARM_CM85/secure/secure_heap.c
+++ b/portable/IAR/ARM_CM85/secure/secure_heap.c
@@ -256,6 +256,7 @@ void * pvPortMalloc( size_t xWantedSize )
     BlockLink_t * pxNewBlockLink;
     void * pvReturn = NULL;
     size_t xAdditionalRequiredSize;
+    size_t xAllocatedBlockSize = 0;
 
     /* If this is the first call to malloc then the heap will require
      * initialisation to setup the list of free blocks. */
@@ -374,6 +375,8 @@ void * pvPortMalloc( size_t xWantedSize )
                     mtCOVERAGE_TEST_MARKER();
                 }
 
+                xAllocatedBlockSize = pxBlock->xBlockSize;
+
                 /* The block is being returned - it is allocated and owned by
                  * the application and has no "next" block. */
                 secureheapALLOCATE_BLOCK( pxBlock );
@@ -394,7 +397,10 @@ void * pvPortMalloc( size_t xWantedSize )
         mtCOVERAGE_TEST_MARKER();
     }
 
-    traceMALLOC( pvReturn, xWantedSize );
+    traceMALLOC( pvReturn, xAllocatedBlockSize );
+
+    /* Prevent compiler warnings when trace macros are not used. */
+    ( void ) xAllocatedBlockSize;
 
     #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
     {
diff --git a/portable/MemMang/heap_2.c b/portable/MemMang/heap_2.c
index c1b35b911..a99a74d76 100644
--- a/portable/MemMang/heap_2.c
+++ b/portable/MemMang/heap_2.c
@@ -160,6 +160,7 @@ void * pvPortMalloc( size_t xWantedSize )
     BlockLink_t * pxNewBlockLink;
     void * pvReturn = NULL;
     size_t xAdditionalRequiredSize;
+    size_t xAllocatedBlockSize = 0;
 
     if( xWantedSize > 0 )
     {
@@ -261,6 +262,8 @@ void * pvPortMalloc( size_t xWantedSize )
 
                     xFreeBytesRemaining -= pxBlock->xBlockSize;
 
+                    xAllocatedBlockSize = pxBlock->xBlockSize;
+
                     /* The block is being returned - it is allocated and owned
                      * by the application and has no "next" block. */
                     heapALLOCATE_BLOCK( pxBlock );
@@ -269,7 +272,10 @@ void * pvPortMalloc( size_t xWantedSize )
             }
         }
 
-        traceMALLOC( pvReturn, xWantedSize );
+        traceMALLOC( pvReturn, xAllocatedBlockSize );
+
+        /* Prevent compiler warnings when trace macros are not used. */
+        ( void ) xAllocatedBlockSize;
     }
     ( void ) xTaskResumeAll();
 
diff --git a/portable/MemMang/heap_4.c b/portable/MemMang/heap_4.c
index 71b6a9421..fe15654ed 100644
--- a/portable/MemMang/heap_4.c
+++ b/portable/MemMang/heap_4.c
@@ -177,6 +177,7 @@ void * pvPortMalloc( size_t xWantedSize )
     BlockLink_t * pxNewBlockLink;
     void * pvReturn = NULL;
     size_t xAdditionalRequiredSize;
+    size_t xAllocatedBlockSize = 0;
 
     if( xWantedSize > 0 )
     {
@@ -302,6 +303,8 @@ void * pvPortMalloc( size_t xWantedSize )
                         mtCOVERAGE_TEST_MARKER();
                     }
 
+                    xAllocatedBlockSize = pxBlock->xBlockSize;
+
                     /* The block is being returned - it is allocated and owned
                      * by the application and has no "next" block. */
                     heapALLOCATE_BLOCK( pxBlock );
@@ -323,7 +326,10 @@ void * pvPortMalloc( size_t xWantedSize )
             mtCOVERAGE_TEST_MARKER();
         }
 
-        traceMALLOC( pvReturn, xWantedSize );
+        traceMALLOC( pvReturn, xAllocatedBlockSize );
+
+        /* Prevent compiler warnings when trace macros are not used. */
+        ( void ) xAllocatedBlockSize;
     }
     ( void ) xTaskResumeAll();
 
diff --git a/portable/MemMang/heap_5.c b/portable/MemMang/heap_5.c
index bb33bcfad..e0c566640 100644
--- a/portable/MemMang/heap_5.c
+++ b/portable/MemMang/heap_5.c
@@ -212,6 +212,7 @@ void * pvPortMalloc( size_t xWantedSize )
     BlockLink_t * pxNewBlockLink;
     void * pvReturn = NULL;
     size_t xAdditionalRequiredSize;
+    size_t xAllocatedBlockSize = 0;
 
     /* The heap must be initialised before the first call to
      * pvPortMalloc(). */
@@ -330,6 +331,8 @@ void * pvPortMalloc( size_t xWantedSize )
                         mtCOVERAGE_TEST_MARKER();
                     }
 
+                    xAllocatedBlockSize = pxBlock->xBlockSize;
+
                     /* The block is being returned - it is allocated and owned
                      * by the application and has no "next" block. */
                     heapALLOCATE_BLOCK( pxBlock );
@@ -351,7 +354,10 @@ void * pvPortMalloc( size_t xWantedSize )
             mtCOVERAGE_TEST_MARKER();
         }
 
-        traceMALLOC( pvReturn, xWantedSize );
+        traceMALLOC( pvReturn, xAllocatedBlockSize );
+
+        /* Prevent compiler warnings when trace macros are not used. */
+        ( void ) xAllocatedBlockSize;
     }
     ( void ) xTaskResumeAll();
 

From 0c79e74eaa00a528604b14b9eb212b912d629f66 Mon Sep 17 00:00:00 2001
From: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Date: Wed, 19 Jun 2024 18:29:04 +0800
Subject: [PATCH 292/424] Remove run state assertion in
 prvCheckForRunStateChange (#1093)

In `prvCheckForRunStateChange()`, enabling interrupts should cause this core to immediately service the pending interrupt and yield. Upon the next scheduling of the task, the assertion `configASSERT(pxThisTCB->xTaskRunState != taskTASK_SCHEDULED_TO_YIELD);` may not be true, as other cores could have requested a yield for this task before it evaluates its run state within the assertion. To address this, the task re-evaluates its run state in critical section within a loop until it is eligible for execution, which is the current implementation. Consequently, this assertion should be removed to ensure correct behavior.
---
 tasks.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/tasks.c b/tasks.c
index f8740257c..7a65e7ba5 100644
--- a/tasks.c
+++ b/tasks.c
@@ -845,10 +845,11 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
 
             portENABLE_INTERRUPTS();
 
-            /* Enabling interrupts should cause this core to immediately
-             * service the pending interrupt and yield. If the run state is still
-             * yielding here then that is a problem. */
-            configASSERT( pxThisTCB->xTaskRunState != taskTASK_SCHEDULED_TO_YIELD );
+            /* Enabling interrupts should cause this core to immediately service
+             * the pending interrupt and yield. After servicing the pending interrupt,
+             * the task needs to re-evaluate its run state within this loop, as
+             * other cores may have requested this task to yield, potentially altering
+             * its run state. */
 
             portDISABLE_INTERRUPTS();
             portGET_TASK_LOCK();

From 31419bfceec515e19f77b88ff4b71be108afe015 Mon Sep 17 00:00:00 2001
From: Ahmed Ismail <64546783+AhmedIsmail02@users.noreply.github.com>
Date: Wed, 19 Jun 2024 16:12:50 +0100
Subject: [PATCH 293/424] FreeRTOS MPU: Add Privileged eXecute Never MPU
 attribute support (#1092)

FreeRTOS MPU: Add privileged execute never MPU attribute

A new MPU region attribute Privileged eXecute Never (PXN)
is introduced in Armv8.1-M architecture, where if an MPU
region has PXN attribute set and the processor attempts
to execute the code inside with privileged level,
the Memory Management Fault exception would be triggered,
with IACCVIOL bit in MemManage Fault State Register set
to 1. The PXN feature allows privileged software to ensure
specific application tasks (threads) to execute in
unprivileged level only.

Signed-off-by: Ahmed Ismail <Ahmed.Ismail@arm.com>
---
 include/task.h                                |  27 +++--
 portable/ARMv8M/non_secure/port.c             | 104 ++++++++++--------
 .../portable/GCC/ARM_CM23/portmacro.h         |   1 +
 .../portable/GCC/ARM_CM23_NTZ/portmacro.h     |   1 +
 .../portable/GCC/ARM_CM33/portmacro.h         |   1 +
 .../portable/GCC/ARM_CM33_NTZ/portmacro.h     |   1 +
 .../portable/GCC/ARM_CM35P/portmacro.h        |   1 +
 .../portable/GCC/ARM_CM55/portmacro.h         |   1 +
 .../portable/GCC/ARM_CM85/portmacro.h         |   1 +
 .../portable/IAR/ARM_CM23/portmacro.h         |   1 +
 .../portable/IAR/ARM_CM23_NTZ/portmacro.h     |   1 +
 .../portable/IAR/ARM_CM33/portmacro.h         |   1 +
 .../portable/IAR/ARM_CM33_NTZ/portmacro.h     |   1 +
 .../portable/IAR/ARM_CM35P/portmacro.h        |   1 +
 .../portable/IAR/ARM_CM55/portmacro.h         |   1 +
 .../portable/IAR/ARM_CM85/portmacro.h         |   1 +
 portable/GCC/ARM_CM23/non_secure/port.c       | 104 ++++++++++--------
 portable/GCC/ARM_CM23/non_secure/portmacro.h  |   1 +
 portable/GCC/ARM_CM23_NTZ/non_secure/port.c   | 104 ++++++++++--------
 .../GCC/ARM_CM23_NTZ/non_secure/portmacro.h   |   1 +
 portable/GCC/ARM_CM33/non_secure/port.c       | 104 ++++++++++--------
 portable/GCC/ARM_CM33/non_secure/portmacro.h  |   1 +
 portable/GCC/ARM_CM33_NTZ/non_secure/port.c   | 104 ++++++++++--------
 .../GCC/ARM_CM33_NTZ/non_secure/portmacro.h   |   1 +
 portable/GCC/ARM_CM35P/non_secure/port.c      | 104 ++++++++++--------
 portable/GCC/ARM_CM35P/non_secure/portmacro.h |   1 +
 portable/GCC/ARM_CM35P_NTZ/non_secure/port.c  | 104 ++++++++++--------
 .../GCC/ARM_CM35P_NTZ/non_secure/portmacro.h  |   1 +
 portable/GCC/ARM_CM55/non_secure/port.c       | 104 ++++++++++--------
 portable/GCC/ARM_CM55/non_secure/portmacro.h  |   1 +
 portable/GCC/ARM_CM55_NTZ/non_secure/port.c   | 104 ++++++++++--------
 .../GCC/ARM_CM55_NTZ/non_secure/portmacro.h   |   1 +
 portable/GCC/ARM_CM85/non_secure/port.c       | 104 ++++++++++--------
 portable/GCC/ARM_CM85/non_secure/portmacro.h  |   1 +
 portable/GCC/ARM_CM85_NTZ/non_secure/port.c   | 104 ++++++++++--------
 .../GCC/ARM_CM85_NTZ/non_secure/portmacro.h   |   1 +
 portable/IAR/ARM_CM23/non_secure/port.c       | 104 ++++++++++--------
 portable/IAR/ARM_CM23/non_secure/portmacro.h  |   1 +
 portable/IAR/ARM_CM23_NTZ/non_secure/port.c   | 104 ++++++++++--------
 .../IAR/ARM_CM23_NTZ/non_secure/portmacro.h   |   1 +
 portable/IAR/ARM_CM33/non_secure/port.c       | 104 ++++++++++--------
 portable/IAR/ARM_CM33/non_secure/portmacro.h  |   1 +
 portable/IAR/ARM_CM33_NTZ/non_secure/port.c   | 104 ++++++++++--------
 .../IAR/ARM_CM33_NTZ/non_secure/portmacro.h   |   1 +
 portable/IAR/ARM_CM35P/non_secure/port.c      | 104 ++++++++++--------
 portable/IAR/ARM_CM35P/non_secure/portmacro.h |   1 +
 portable/IAR/ARM_CM35P_NTZ/non_secure/port.c  | 104 ++++++++++--------
 .../IAR/ARM_CM35P_NTZ/non_secure/portmacro.h  |   1 +
 portable/IAR/ARM_CM55/non_secure/port.c       | 104 ++++++++++--------
 portable/IAR/ARM_CM55/non_secure/portmacro.h  |   1 +
 portable/IAR/ARM_CM55_NTZ/non_secure/port.c   | 104 ++++++++++--------
 .../IAR/ARM_CM55_NTZ/non_secure/portmacro.h   |   1 +
 portable/IAR/ARM_CM85/non_secure/port.c       | 104 ++++++++++--------
 portable/IAR/ARM_CM85/non_secure/portmacro.h  |   1 +
 portable/IAR/ARM_CM85_NTZ/non_secure/port.c   | 104 ++++++++++--------
 .../IAR/ARM_CM85_NTZ/non_secure/portmacro.h   |   1 +
 56 files changed, 1309 insertions(+), 936 deletions(-)

diff --git a/include/task.h b/include/task.h
index 1ca800585..f3e0d496b 100644
--- a/include/task.h
+++ b/include/task.h
@@ -53,30 +53,33 @@
  * The tskKERNEL_VERSION_MAJOR, tskKERNEL_VERSION_MINOR, tskKERNEL_VERSION_BUILD
  * values will reflect the last released version number.
  */
-#define tskKERNEL_VERSION_NUMBER       "V11.1.0+"
-#define tskKERNEL_VERSION_MAJOR        11
-#define tskKERNEL_VERSION_MINOR        1
-#define tskKERNEL_VERSION_BUILD        0
+#define tskKERNEL_VERSION_NUMBER                      "V11.1.0+"
+#define tskKERNEL_VERSION_MAJOR                       11
+#define tskKERNEL_VERSION_MINOR                       1
+#define tskKERNEL_VERSION_BUILD                       0
 
 /* MPU region parameters passed in ulParameters
  * of MemoryRegion_t struct. */
-#define tskMPU_REGION_READ_ONLY        ( 1U << 0U )
-#define tskMPU_REGION_READ_WRITE       ( 1U << 1U )
-#define tskMPU_REGION_EXECUTE_NEVER    ( 1U << 2U )
-#define tskMPU_REGION_NORMAL_MEMORY    ( 1U << 3U )
-#define tskMPU_REGION_DEVICE_MEMORY    ( 1U << 4U )
+#define tskMPU_REGION_READ_ONLY                       ( 1U << 0U )
+#define tskMPU_REGION_READ_WRITE                      ( 1U << 1U )
+#define tskMPU_REGION_EXECUTE_NEVER                   ( 1U << 2U )
+#define tskMPU_REGION_NORMAL_MEMORY                   ( 1U << 3U )
+#define tskMPU_REGION_DEVICE_MEMORY                   ( 1U << 4U )
+#if ( portARMV8M_MINOR_VERSION >= 1 )
+    #define tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER    ( 1U << 5U )
+#endif /* portARMV8M_MINOR_VERSION >= 1 */
 
 /* MPU region permissions stored in MPU settings to
  * authorize access requests. */
-#define tskMPU_READ_PERMISSION         ( 1U << 0U )
-#define tskMPU_WRITE_PERMISSION        ( 1U << 1U )
+#define tskMPU_READ_PERMISSION        ( 1U << 0U )
+#define tskMPU_WRITE_PERMISSION       ( 1U << 1U )
 
 /* The direct to task notification feature used to have only a single notification
  * per task.  Now there is an array of notifications per task that is dimensioned by
  * configTASK_NOTIFICATION_ARRAY_ENTRIES.  For backward compatibility, any use of the
  * original direct to task notification defaults to using the first index in the
  * array. */
-#define tskDEFAULT_INDEX_TO_NOTIFY     ( 0 )
+#define tskDEFAULT_INDEX_TO_NOTIFY    ( 0 )
 
 /**
  * task. h
diff --git a/portable/ARMv8M/non_secure/port.c b/portable/ARMv8M/non_secure/port.c
index 99e1e148b..c9b596d12 100644
--- a/portable/ARMv8M/non_secure/port.c
+++ b/portable/ARMv8M/non_secure/port.c
@@ -166,73 +166,79 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                            ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                            ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                             ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                            ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                            ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                           ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                           ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK        ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                      ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                     ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                      ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                     ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                      ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                     ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                      ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                     ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                      ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                     ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                      ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                     ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                      ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                     ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                      ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                     ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                    ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                    ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                    ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                    ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                    ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                    ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                    ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                    ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE                  ( 1UL )
+
+#if ( portARMV8M_MINOR_VERSION >= 1 )
+    /* Enable Privileged eXecute Never MPU attribute for the selected memory
+     * region. */
+    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER   ( 1UL << 4UL )
+#endif /* portARMV8M_MINOR_VERSION >= 1 */
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT      ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT          ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                      ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                          ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE             ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE                 ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -1880,6 +1886,16 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
                 xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
                                                                           ( portMPU_RLAR_REGION_ENABLE );
 
+                /* PXN. */
+                #if ( portARMV8M_MINOR_VERSION >= 1 )
+                {
+                    if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
+                    {
+                        xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
+                    }
+                }
+                #endif /* portARMV8M_MINOR_VERSION >= 1 */
+
                 /* Normal memory/ Device memory. */
                 if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
                 {
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h
index b08fa71b0..a7f9db767 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h
@@ -50,6 +50,7 @@
  */
 #define portARCH_NAME                    "Cortex-M23"
 #define portHAS_ARMV8M_MAIN_EXTENSION    0
+#define portARMV8M_MINOR_VERSION         0
 #define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h
index b08fa71b0..a7f9db767 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h
@@ -50,6 +50,7 @@
  */
 #define portARCH_NAME                    "Cortex-M23"
 #define portHAS_ARMV8M_MAIN_EXTENSION    0
+#define portARMV8M_MINOR_VERSION         0
 #define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h
index 8d3555bb4..0fc61f23c 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h
@@ -50,6 +50,7 @@
  */
 #define portARCH_NAME                    "Cortex-M33"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portARMV8M_MINOR_VERSION         0
 #define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h
index 8d3555bb4..0fc61f23c 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h
@@ -50,6 +50,7 @@
  */
 #define portARCH_NAME                    "Cortex-M33"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portARMV8M_MINOR_VERSION         0
 #define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM35P/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM35P/portmacro.h
index 0eb0a6592..4db6e6d4a 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM35P/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM35P/portmacro.h
@@ -50,6 +50,7 @@
  */
 #define portARCH_NAME                    "Cortex-M35P"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portARMV8M_MINOR_VERSION         0
 #define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM55/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM55/portmacro.h
index 2797dbd53..c6a179c52 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM55/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM55/portmacro.h
@@ -55,6 +55,7 @@
  */
 #define portARCH_NAME                    "Cortex-M55"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portARMV8M_MINOR_VERSION         1
 #define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM85/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM85/portmacro.h
index 2d5cac90e..7e14f2696 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM85/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM85/portmacro.h
@@ -55,6 +55,7 @@
  */
 #define portARCH_NAME                    "Cortex-M85"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portARMV8M_MINOR_VERSION         1
 #define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h
index 667b58151..9dfcc9132 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h
@@ -50,6 +50,7 @@
  */
 #define portARCH_NAME                    "Cortex-M23"
 #define portHAS_ARMV8M_MAIN_EXTENSION    0
+#define portARMV8M_MINOR_VERSION         0
 #define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h
index 667b58151..9dfcc9132 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h
@@ -50,6 +50,7 @@
  */
 #define portARCH_NAME                    "Cortex-M23"
 #define portHAS_ARMV8M_MAIN_EXTENSION    0
+#define portARMV8M_MINOR_VERSION         0
 #define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h
index eeb14d86f..a2a301f00 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h
@@ -50,6 +50,7 @@
  */
 #define portARCH_NAME                    "Cortex-M33"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portARMV8M_MINOR_VERSION         0
 #define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h
index acb4748a2..f0d5f2b9c 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h
@@ -50,6 +50,7 @@
  */
 #define portARCH_NAME                    "Cortex-M33"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portARMV8M_MINOR_VERSION         0
 #define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM35P/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM35P/portmacro.h
index 0dcac8d4d..633da3a6d 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM35P/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM35P/portmacro.h
@@ -50,6 +50,7 @@
  */
 #define portARCH_NAME                    "Cortex-M35P"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portARMV8M_MINOR_VERSION         0
 #define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM55/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM55/portmacro.h
index 92dc75fd1..95b179413 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM55/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM55/portmacro.h
@@ -55,6 +55,7 @@
  */
 #define portARCH_NAME                    "Cortex-M55"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portARMV8M_MINOR_VERSION         1
 #define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM85/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM85/portmacro.h
index 02f67453a..efde68dc2 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM85/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM85/portmacro.h
@@ -55,6 +55,7 @@
  */
 #define portARCH_NAME                    "Cortex-M85"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portARMV8M_MINOR_VERSION         1
 #define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
diff --git a/portable/GCC/ARM_CM23/non_secure/port.c b/portable/GCC/ARM_CM23/non_secure/port.c
index 99e1e148b..c9b596d12 100644
--- a/portable/GCC/ARM_CM23/non_secure/port.c
+++ b/portable/GCC/ARM_CM23/non_secure/port.c
@@ -166,73 +166,79 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                            ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                            ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                             ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                            ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                            ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                           ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                           ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK        ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                      ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                     ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                      ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                     ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                      ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                     ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                      ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                     ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                      ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                     ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                      ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                     ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                      ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                     ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                      ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                     ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                    ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                    ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                    ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                    ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                    ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                    ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                    ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                    ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE                  ( 1UL )
+
+#if ( portARMV8M_MINOR_VERSION >= 1 )
+    /* Enable Privileged eXecute Never MPU attribute for the selected memory
+     * region. */
+    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER   ( 1UL << 4UL )
+#endif /* portARMV8M_MINOR_VERSION >= 1 */
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT      ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT          ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                      ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                          ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE             ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE                 ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -1880,6 +1886,16 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
                 xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
                                                                           ( portMPU_RLAR_REGION_ENABLE );
 
+                /* PXN. */
+                #if ( portARMV8M_MINOR_VERSION >= 1 )
+                {
+                    if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
+                    {
+                        xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
+                    }
+                }
+                #endif /* portARMV8M_MINOR_VERSION >= 1 */
+
                 /* Normal memory/ Device memory. */
                 if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
                 {
diff --git a/portable/GCC/ARM_CM23/non_secure/portmacro.h b/portable/GCC/ARM_CM23/non_secure/portmacro.h
index b08fa71b0..a7f9db767 100644
--- a/portable/GCC/ARM_CM23/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM23/non_secure/portmacro.h
@@ -50,6 +50,7 @@
  */
 #define portARCH_NAME                    "Cortex-M23"
 #define portHAS_ARMV8M_MAIN_EXTENSION    0
+#define portARMV8M_MINOR_VERSION         0
 #define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
index 99e1e148b..c9b596d12 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
@@ -166,73 +166,79 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                            ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                            ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                             ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                            ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                            ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                           ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                           ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK        ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                      ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                     ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                      ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                     ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                      ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                     ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                      ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                     ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                      ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                     ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                      ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                     ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                      ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                     ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                      ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                     ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                    ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                    ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                    ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                    ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                    ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                    ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                    ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                    ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE                  ( 1UL )
+
+#if ( portARMV8M_MINOR_VERSION >= 1 )
+    /* Enable Privileged eXecute Never MPU attribute for the selected memory
+     * region. */
+    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER   ( 1UL << 4UL )
+#endif /* portARMV8M_MINOR_VERSION >= 1 */
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT      ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT          ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                      ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                          ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE             ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE                 ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -1880,6 +1886,16 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
                 xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
                                                                           ( portMPU_RLAR_REGION_ENABLE );
 
+                /* PXN. */
+                #if ( portARMV8M_MINOR_VERSION >= 1 )
+                {
+                    if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
+                    {
+                        xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
+                    }
+                }
+                #endif /* portARMV8M_MINOR_VERSION >= 1 */
+
                 /* Normal memory/ Device memory. */
                 if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
                 {
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h b/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h
index b08fa71b0..a7f9db767 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h
@@ -50,6 +50,7 @@
  */
 #define portARCH_NAME                    "Cortex-M23"
 #define portHAS_ARMV8M_MAIN_EXTENSION    0
+#define portARMV8M_MINOR_VERSION         0
 #define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/GCC/ARM_CM33/non_secure/port.c b/portable/GCC/ARM_CM33/non_secure/port.c
index 99e1e148b..c9b596d12 100644
--- a/portable/GCC/ARM_CM33/non_secure/port.c
+++ b/portable/GCC/ARM_CM33/non_secure/port.c
@@ -166,73 +166,79 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                            ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                            ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                             ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                            ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                            ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                           ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                           ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK        ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                      ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                     ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                      ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                     ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                      ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                     ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                      ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                     ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                      ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                     ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                      ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                     ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                      ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                     ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                      ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                     ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                    ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                    ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                    ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                    ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                    ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                    ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                    ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                    ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE                  ( 1UL )
+
+#if ( portARMV8M_MINOR_VERSION >= 1 )
+    /* Enable Privileged eXecute Never MPU attribute for the selected memory
+     * region. */
+    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER   ( 1UL << 4UL )
+#endif /* portARMV8M_MINOR_VERSION >= 1 */
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT      ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT          ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                      ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                          ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE             ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE                 ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -1880,6 +1886,16 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
                 xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
                                                                           ( portMPU_RLAR_REGION_ENABLE );
 
+                /* PXN. */
+                #if ( portARMV8M_MINOR_VERSION >= 1 )
+                {
+                    if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
+                    {
+                        xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
+                    }
+                }
+                #endif /* portARMV8M_MINOR_VERSION >= 1 */
+
                 /* Normal memory/ Device memory. */
                 if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
                 {
diff --git a/portable/GCC/ARM_CM33/non_secure/portmacro.h b/portable/GCC/ARM_CM33/non_secure/portmacro.h
index 8d3555bb4..0fc61f23c 100644
--- a/portable/GCC/ARM_CM33/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM33/non_secure/portmacro.h
@@ -50,6 +50,7 @@
  */
 #define portARCH_NAME                    "Cortex-M33"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portARMV8M_MINOR_VERSION         0
 #define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
index 99e1e148b..c9b596d12 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
@@ -166,73 +166,79 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                            ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                            ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                             ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                            ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                            ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                           ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                           ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK        ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                      ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                     ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                      ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                     ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                      ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                     ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                      ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                     ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                      ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                     ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                      ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                     ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                      ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                     ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                      ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                     ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                    ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                    ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                    ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                    ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                    ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                    ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                    ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                    ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE                  ( 1UL )
+
+#if ( portARMV8M_MINOR_VERSION >= 1 )
+    /* Enable Privileged eXecute Never MPU attribute for the selected memory
+     * region. */
+    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER   ( 1UL << 4UL )
+#endif /* portARMV8M_MINOR_VERSION >= 1 */
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT      ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT          ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                      ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                          ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE             ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE                 ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -1880,6 +1886,16 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
                 xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
                                                                           ( portMPU_RLAR_REGION_ENABLE );
 
+                /* PXN. */
+                #if ( portARMV8M_MINOR_VERSION >= 1 )
+                {
+                    if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
+                    {
+                        xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
+                    }
+                }
+                #endif /* portARMV8M_MINOR_VERSION >= 1 */
+
                 /* Normal memory/ Device memory. */
                 if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
                 {
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h b/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h
index 8d3555bb4..0fc61f23c 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h
@@ -50,6 +50,7 @@
  */
 #define portARCH_NAME                    "Cortex-M33"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portARMV8M_MINOR_VERSION         0
 #define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/GCC/ARM_CM35P/non_secure/port.c b/portable/GCC/ARM_CM35P/non_secure/port.c
index 99e1e148b..c9b596d12 100644
--- a/portable/GCC/ARM_CM35P/non_secure/port.c
+++ b/portable/GCC/ARM_CM35P/non_secure/port.c
@@ -166,73 +166,79 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                            ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                            ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                             ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                            ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                            ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                           ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                           ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK        ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                      ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                     ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                      ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                     ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                      ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                     ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                      ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                     ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                      ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                     ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                      ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                     ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                      ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                     ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                      ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                     ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                    ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                    ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                    ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                    ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                    ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                    ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                    ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                    ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE                  ( 1UL )
+
+#if ( portARMV8M_MINOR_VERSION >= 1 )
+    /* Enable Privileged eXecute Never MPU attribute for the selected memory
+     * region. */
+    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER   ( 1UL << 4UL )
+#endif /* portARMV8M_MINOR_VERSION >= 1 */
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT      ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT          ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                      ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                          ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE             ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE                 ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -1880,6 +1886,16 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
                 xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
                                                                           ( portMPU_RLAR_REGION_ENABLE );
 
+                /* PXN. */
+                #if ( portARMV8M_MINOR_VERSION >= 1 )
+                {
+                    if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
+                    {
+                        xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
+                    }
+                }
+                #endif /* portARMV8M_MINOR_VERSION >= 1 */
+
                 /* Normal memory/ Device memory. */
                 if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
                 {
diff --git a/portable/GCC/ARM_CM35P/non_secure/portmacro.h b/portable/GCC/ARM_CM35P/non_secure/portmacro.h
index 0eb0a6592..4db6e6d4a 100644
--- a/portable/GCC/ARM_CM35P/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM35P/non_secure/portmacro.h
@@ -50,6 +50,7 @@
  */
 #define portARCH_NAME                    "Cortex-M35P"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portARMV8M_MINOR_VERSION         0
 #define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c b/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
index 99e1e148b..c9b596d12 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
@@ -166,73 +166,79 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                            ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                            ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                             ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                            ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                            ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                           ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                           ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK        ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                      ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                     ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                      ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                     ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                      ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                     ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                      ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                     ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                      ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                     ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                      ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                     ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                      ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                     ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                      ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                     ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                    ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                    ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                    ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                    ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                    ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                    ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                    ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                    ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE                  ( 1UL )
+
+#if ( portARMV8M_MINOR_VERSION >= 1 )
+    /* Enable Privileged eXecute Never MPU attribute for the selected memory
+     * region. */
+    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER   ( 1UL << 4UL )
+#endif /* portARMV8M_MINOR_VERSION >= 1 */
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT      ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT          ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                      ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                          ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE             ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE                 ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -1880,6 +1886,16 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
                 xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
                                                                           ( portMPU_RLAR_REGION_ENABLE );
 
+                /* PXN. */
+                #if ( portARMV8M_MINOR_VERSION >= 1 )
+                {
+                    if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
+                    {
+                        xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
+                    }
+                }
+                #endif /* portARMV8M_MINOR_VERSION >= 1 */
+
                 /* Normal memory/ Device memory. */
                 if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
                 {
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacro.h b/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacro.h
index 0eb0a6592..4db6e6d4a 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacro.h
@@ -50,6 +50,7 @@
  */
 #define portARCH_NAME                    "Cortex-M35P"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portARMV8M_MINOR_VERSION         0
 #define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/GCC/ARM_CM55/non_secure/port.c b/portable/GCC/ARM_CM55/non_secure/port.c
index 99e1e148b..c9b596d12 100644
--- a/portable/GCC/ARM_CM55/non_secure/port.c
+++ b/portable/GCC/ARM_CM55/non_secure/port.c
@@ -166,73 +166,79 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                            ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                            ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                             ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                            ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                            ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                           ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                           ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK        ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                      ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                     ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                      ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                     ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                      ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                     ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                      ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                     ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                      ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                     ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                      ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                     ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                      ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                     ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                      ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                     ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                    ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                    ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                    ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                    ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                    ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                    ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                    ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                    ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE                  ( 1UL )
+
+#if ( portARMV8M_MINOR_VERSION >= 1 )
+    /* Enable Privileged eXecute Never MPU attribute for the selected memory
+     * region. */
+    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER   ( 1UL << 4UL )
+#endif /* portARMV8M_MINOR_VERSION >= 1 */
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT      ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT          ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                      ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                          ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE             ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE                 ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -1880,6 +1886,16 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
                 xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
                                                                           ( portMPU_RLAR_REGION_ENABLE );
 
+                /* PXN. */
+                #if ( portARMV8M_MINOR_VERSION >= 1 )
+                {
+                    if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
+                    {
+                        xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
+                    }
+                }
+                #endif /* portARMV8M_MINOR_VERSION >= 1 */
+
                 /* Normal memory/ Device memory. */
                 if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
                 {
diff --git a/portable/GCC/ARM_CM55/non_secure/portmacro.h b/portable/GCC/ARM_CM55/non_secure/portmacro.h
index 2797dbd53..c6a179c52 100644
--- a/portable/GCC/ARM_CM55/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM55/non_secure/portmacro.h
@@ -55,6 +55,7 @@
  */
 #define portARCH_NAME                    "Cortex-M55"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portARMV8M_MINOR_VERSION         1
 #define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/port.c b/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
index 99e1e148b..c9b596d12 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
@@ -166,73 +166,79 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                            ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                            ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                             ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                            ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                            ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                           ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                           ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK        ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                      ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                     ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                      ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                     ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                      ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                     ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                      ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                     ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                      ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                     ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                      ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                     ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                      ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                     ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                      ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                     ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                    ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                    ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                    ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                    ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                    ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                    ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                    ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                    ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE                  ( 1UL )
+
+#if ( portARMV8M_MINOR_VERSION >= 1 )
+    /* Enable Privileged eXecute Never MPU attribute for the selected memory
+     * region. */
+    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER   ( 1UL << 4UL )
+#endif /* portARMV8M_MINOR_VERSION >= 1 */
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT      ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT          ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                      ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                          ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE             ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE                 ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -1880,6 +1886,16 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
                 xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
                                                                           ( portMPU_RLAR_REGION_ENABLE );
 
+                /* PXN. */
+                #if ( portARMV8M_MINOR_VERSION >= 1 )
+                {
+                    if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
+                    {
+                        xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
+                    }
+                }
+                #endif /* portARMV8M_MINOR_VERSION >= 1 */
+
                 /* Normal memory/ Device memory. */
                 if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
                 {
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/portmacro.h b/portable/GCC/ARM_CM55_NTZ/non_secure/portmacro.h
index 2797dbd53..c6a179c52 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/portmacro.h
@@ -55,6 +55,7 @@
  */
 #define portARCH_NAME                    "Cortex-M55"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portARMV8M_MINOR_VERSION         1
 #define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/GCC/ARM_CM85/non_secure/port.c b/portable/GCC/ARM_CM85/non_secure/port.c
index 99e1e148b..c9b596d12 100644
--- a/portable/GCC/ARM_CM85/non_secure/port.c
+++ b/portable/GCC/ARM_CM85/non_secure/port.c
@@ -166,73 +166,79 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                            ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                            ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                             ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                            ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                            ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                           ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                           ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK        ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                      ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                     ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                      ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                     ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                      ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                     ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                      ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                     ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                      ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                     ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                      ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                     ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                      ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                     ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                      ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                     ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                    ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                    ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                    ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                    ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                    ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                    ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                    ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                    ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE                  ( 1UL )
+
+#if ( portARMV8M_MINOR_VERSION >= 1 )
+    /* Enable Privileged eXecute Never MPU attribute for the selected memory
+     * region. */
+    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER   ( 1UL << 4UL )
+#endif /* portARMV8M_MINOR_VERSION >= 1 */
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT      ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT          ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                      ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                          ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE             ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE                 ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -1880,6 +1886,16 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
                 xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
                                                                           ( portMPU_RLAR_REGION_ENABLE );
 
+                /* PXN. */
+                #if ( portARMV8M_MINOR_VERSION >= 1 )
+                {
+                    if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
+                    {
+                        xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
+                    }
+                }
+                #endif /* portARMV8M_MINOR_VERSION >= 1 */
+
                 /* Normal memory/ Device memory. */
                 if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
                 {
diff --git a/portable/GCC/ARM_CM85/non_secure/portmacro.h b/portable/GCC/ARM_CM85/non_secure/portmacro.h
index 2d5cac90e..7e14f2696 100644
--- a/portable/GCC/ARM_CM85/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM85/non_secure/portmacro.h
@@ -55,6 +55,7 @@
  */
 #define portARCH_NAME                    "Cortex-M85"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portARMV8M_MINOR_VERSION         1
 #define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/port.c b/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
index 99e1e148b..c9b596d12 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
@@ -166,73 +166,79 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                            ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                            ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                             ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                            ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                            ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                           ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                           ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK        ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                      ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                     ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                      ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                     ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                      ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                     ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                      ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                     ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                      ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                     ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                      ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                     ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                      ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                     ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                      ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                     ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                    ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                    ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                    ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                    ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                    ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                    ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                    ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                    ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE                  ( 1UL )
+
+#if ( portARMV8M_MINOR_VERSION >= 1 )
+    /* Enable Privileged eXecute Never MPU attribute for the selected memory
+     * region. */
+    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER   ( 1UL << 4UL )
+#endif /* portARMV8M_MINOR_VERSION >= 1 */
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT      ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT          ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                      ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                          ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE             ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE                 ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -1880,6 +1886,16 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
                 xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
                                                                           ( portMPU_RLAR_REGION_ENABLE );
 
+                /* PXN. */
+                #if ( portARMV8M_MINOR_VERSION >= 1 )
+                {
+                    if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
+                    {
+                        xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
+                    }
+                }
+                #endif /* portARMV8M_MINOR_VERSION >= 1 */
+
                 /* Normal memory/ Device memory. */
                 if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
                 {
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/portmacro.h b/portable/GCC/ARM_CM85_NTZ/non_secure/portmacro.h
index 2d5cac90e..7e14f2696 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/portmacro.h
@@ -55,6 +55,7 @@
  */
 #define portARCH_NAME                    "Cortex-M85"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portARMV8M_MINOR_VERSION         1
 #define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM23/non_secure/port.c b/portable/IAR/ARM_CM23/non_secure/port.c
index 99e1e148b..c9b596d12 100644
--- a/portable/IAR/ARM_CM23/non_secure/port.c
+++ b/portable/IAR/ARM_CM23/non_secure/port.c
@@ -166,73 +166,79 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                            ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                            ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                             ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                            ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                            ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                           ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                           ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK        ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                      ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                     ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                      ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                     ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                      ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                     ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                      ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                     ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                      ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                     ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                      ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                     ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                      ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                     ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                      ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                     ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                    ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                    ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                    ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                    ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                    ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                    ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                    ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                    ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE                  ( 1UL )
+
+#if ( portARMV8M_MINOR_VERSION >= 1 )
+    /* Enable Privileged eXecute Never MPU attribute for the selected memory
+     * region. */
+    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER   ( 1UL << 4UL )
+#endif /* portARMV8M_MINOR_VERSION >= 1 */
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT      ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT          ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                      ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                          ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE             ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE                 ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -1880,6 +1886,16 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
                 xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
                                                                           ( portMPU_RLAR_REGION_ENABLE );
 
+                /* PXN. */
+                #if ( portARMV8M_MINOR_VERSION >= 1 )
+                {
+                    if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
+                    {
+                        xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
+                    }
+                }
+                #endif /* portARMV8M_MINOR_VERSION >= 1 */
+
                 /* Normal memory/ Device memory. */
                 if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
                 {
diff --git a/portable/IAR/ARM_CM23/non_secure/portmacro.h b/portable/IAR/ARM_CM23/non_secure/portmacro.h
index 667b58151..9dfcc9132 100644
--- a/portable/IAR/ARM_CM23/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM23/non_secure/portmacro.h
@@ -50,6 +50,7 @@
  */
 #define portARCH_NAME                    "Cortex-M23"
 #define portHAS_ARMV8M_MAIN_EXTENSION    0
+#define portARMV8M_MINOR_VERSION         0
 #define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
index 99e1e148b..c9b596d12 100644
--- a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
@@ -166,73 +166,79 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                            ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                            ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                             ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                            ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                            ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                           ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                           ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK        ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                      ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                     ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                      ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                     ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                      ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                     ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                      ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                     ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                      ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                     ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                      ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                     ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                      ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                     ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                      ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                     ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                    ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                    ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                    ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                    ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                    ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                    ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                    ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                    ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE                  ( 1UL )
+
+#if ( portARMV8M_MINOR_VERSION >= 1 )
+    /* Enable Privileged eXecute Never MPU attribute for the selected memory
+     * region. */
+    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER   ( 1UL << 4UL )
+#endif /* portARMV8M_MINOR_VERSION >= 1 */
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT      ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT          ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                      ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                          ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE             ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE                 ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -1880,6 +1886,16 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
                 xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
                                                                           ( portMPU_RLAR_REGION_ENABLE );
 
+                /* PXN. */
+                #if ( portARMV8M_MINOR_VERSION >= 1 )
+                {
+                    if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
+                    {
+                        xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
+                    }
+                }
+                #endif /* portARMV8M_MINOR_VERSION >= 1 */
+
                 /* Normal memory/ Device memory. */
                 if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
                 {
diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h b/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h
index 667b58151..9dfcc9132 100644
--- a/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h
@@ -50,6 +50,7 @@
  */
 #define portARCH_NAME                    "Cortex-M23"
 #define portHAS_ARMV8M_MAIN_EXTENSION    0
+#define portARMV8M_MINOR_VERSION         0
 #define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM33/non_secure/port.c b/portable/IAR/ARM_CM33/non_secure/port.c
index 99e1e148b..c9b596d12 100644
--- a/portable/IAR/ARM_CM33/non_secure/port.c
+++ b/portable/IAR/ARM_CM33/non_secure/port.c
@@ -166,73 +166,79 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                            ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                            ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                             ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                            ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                            ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                           ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                           ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK        ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                      ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                     ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                      ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                     ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                      ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                     ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                      ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                     ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                      ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                     ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                      ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                     ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                      ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                     ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                      ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                     ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                    ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                    ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                    ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                    ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                    ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                    ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                    ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                    ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE                  ( 1UL )
+
+#if ( portARMV8M_MINOR_VERSION >= 1 )
+    /* Enable Privileged eXecute Never MPU attribute for the selected memory
+     * region. */
+    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER   ( 1UL << 4UL )
+#endif /* portARMV8M_MINOR_VERSION >= 1 */
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT      ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT          ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                      ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                          ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE             ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE                 ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -1880,6 +1886,16 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
                 xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
                                                                           ( portMPU_RLAR_REGION_ENABLE );
 
+                /* PXN. */
+                #if ( portARMV8M_MINOR_VERSION >= 1 )
+                {
+                    if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
+                    {
+                        xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
+                    }
+                }
+                #endif /* portARMV8M_MINOR_VERSION >= 1 */
+
                 /* Normal memory/ Device memory. */
                 if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
                 {
diff --git a/portable/IAR/ARM_CM33/non_secure/portmacro.h b/portable/IAR/ARM_CM33/non_secure/portmacro.h
index eeb14d86f..a2a301f00 100644
--- a/portable/IAR/ARM_CM33/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM33/non_secure/portmacro.h
@@ -50,6 +50,7 @@
  */
 #define portARCH_NAME                    "Cortex-M33"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portARMV8M_MINOR_VERSION         0
 #define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
index 99e1e148b..c9b596d12 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
@@ -166,73 +166,79 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                            ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                            ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                             ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                            ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                            ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                           ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                           ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK        ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                      ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                     ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                      ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                     ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                      ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                     ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                      ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                     ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                      ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                     ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                      ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                     ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                      ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                     ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                      ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                     ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                    ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                    ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                    ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                    ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                    ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                    ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                    ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                    ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE                  ( 1UL )
+
+#if ( portARMV8M_MINOR_VERSION >= 1 )
+    /* Enable Privileged eXecute Never MPU attribute for the selected memory
+     * region. */
+    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER   ( 1UL << 4UL )
+#endif /* portARMV8M_MINOR_VERSION >= 1 */
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT      ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT          ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                      ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                          ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE             ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE                 ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -1880,6 +1886,16 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
                 xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
                                                                           ( portMPU_RLAR_REGION_ENABLE );
 
+                /* PXN. */
+                #if ( portARMV8M_MINOR_VERSION >= 1 )
+                {
+                    if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
+                    {
+                        xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
+                    }
+                }
+                #endif /* portARMV8M_MINOR_VERSION >= 1 */
+
                 /* Normal memory/ Device memory. */
                 if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
                 {
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h b/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h
index acb4748a2..f0d5f2b9c 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h
@@ -50,6 +50,7 @@
  */
 #define portARCH_NAME                    "Cortex-M33"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portARMV8M_MINOR_VERSION         0
 #define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM35P/non_secure/port.c b/portable/IAR/ARM_CM35P/non_secure/port.c
index 99e1e148b..c9b596d12 100644
--- a/portable/IAR/ARM_CM35P/non_secure/port.c
+++ b/portable/IAR/ARM_CM35P/non_secure/port.c
@@ -166,73 +166,79 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                            ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                            ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                             ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                            ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                            ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                           ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                           ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK        ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                      ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                     ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                      ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                     ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                      ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                     ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                      ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                     ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                      ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                     ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                      ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                     ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                      ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                     ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                      ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                     ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                    ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                    ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                    ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                    ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                    ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                    ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                    ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                    ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE                  ( 1UL )
+
+#if ( portARMV8M_MINOR_VERSION >= 1 )
+    /* Enable Privileged eXecute Never MPU attribute for the selected memory
+     * region. */
+    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER   ( 1UL << 4UL )
+#endif /* portARMV8M_MINOR_VERSION >= 1 */
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT      ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT          ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                      ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                          ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE             ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE                 ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -1880,6 +1886,16 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
                 xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
                                                                           ( portMPU_RLAR_REGION_ENABLE );
 
+                /* PXN. */
+                #if ( portARMV8M_MINOR_VERSION >= 1 )
+                {
+                    if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
+                    {
+                        xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
+                    }
+                }
+                #endif /* portARMV8M_MINOR_VERSION >= 1 */
+
                 /* Normal memory/ Device memory. */
                 if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
                 {
diff --git a/portable/IAR/ARM_CM35P/non_secure/portmacro.h b/portable/IAR/ARM_CM35P/non_secure/portmacro.h
index 0dcac8d4d..633da3a6d 100644
--- a/portable/IAR/ARM_CM35P/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM35P/non_secure/portmacro.h
@@ -50,6 +50,7 @@
  */
 #define portARCH_NAME                    "Cortex-M35P"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portARMV8M_MINOR_VERSION         0
 #define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c b/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
index 99e1e148b..c9b596d12 100644
--- a/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
@@ -166,73 +166,79 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                            ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                            ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                             ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                            ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                            ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                           ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                           ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK        ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                      ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                     ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                      ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                     ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                      ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                     ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                      ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                     ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                      ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                     ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                      ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                     ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                      ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                     ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                      ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                     ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                    ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                    ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                    ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                    ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                    ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                    ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                    ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                    ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE                  ( 1UL )
+
+#if ( portARMV8M_MINOR_VERSION >= 1 )
+    /* Enable Privileged eXecute Never MPU attribute for the selected memory
+     * region. */
+    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER   ( 1UL << 4UL )
+#endif /* portARMV8M_MINOR_VERSION >= 1 */
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT      ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT          ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                      ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                          ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE             ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE                 ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -1880,6 +1886,16 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
                 xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
                                                                           ( portMPU_RLAR_REGION_ENABLE );
 
+                /* PXN. */
+                #if ( portARMV8M_MINOR_VERSION >= 1 )
+                {
+                    if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
+                    {
+                        xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
+                    }
+                }
+                #endif /* portARMV8M_MINOR_VERSION >= 1 */
+
                 /* Normal memory/ Device memory. */
                 if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
                 {
diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacro.h b/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacro.h
index 0dcac8d4d..633da3a6d 100644
--- a/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacro.h
@@ -50,6 +50,7 @@
  */
 #define portARCH_NAME                    "Cortex-M35P"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portARMV8M_MINOR_VERSION         0
 #define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM55/non_secure/port.c b/portable/IAR/ARM_CM55/non_secure/port.c
index 99e1e148b..c9b596d12 100644
--- a/portable/IAR/ARM_CM55/non_secure/port.c
+++ b/portable/IAR/ARM_CM55/non_secure/port.c
@@ -166,73 +166,79 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                            ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                            ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                             ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                            ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                            ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                           ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                           ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK        ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                      ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                     ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                      ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                     ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                      ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                     ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                      ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                     ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                      ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                     ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                      ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                     ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                      ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                     ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                      ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                     ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                    ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                    ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                    ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                    ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                    ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                    ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                    ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                    ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE                  ( 1UL )
+
+#if ( portARMV8M_MINOR_VERSION >= 1 )
+    /* Enable Privileged eXecute Never MPU attribute for the selected memory
+     * region. */
+    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER   ( 1UL << 4UL )
+#endif /* portARMV8M_MINOR_VERSION >= 1 */
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT      ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT          ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                      ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                          ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE             ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE                 ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -1880,6 +1886,16 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
                 xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
                                                                           ( portMPU_RLAR_REGION_ENABLE );
 
+                /* PXN. */
+                #if ( portARMV8M_MINOR_VERSION >= 1 )
+                {
+                    if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
+                    {
+                        xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
+                    }
+                }
+                #endif /* portARMV8M_MINOR_VERSION >= 1 */
+
                 /* Normal memory/ Device memory. */
                 if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
                 {
diff --git a/portable/IAR/ARM_CM55/non_secure/portmacro.h b/portable/IAR/ARM_CM55/non_secure/portmacro.h
index 92dc75fd1..95b179413 100644
--- a/portable/IAR/ARM_CM55/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM55/non_secure/portmacro.h
@@ -55,6 +55,7 @@
  */
 #define portARCH_NAME                    "Cortex-M55"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portARMV8M_MINOR_VERSION         1
 #define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/port.c b/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
index 99e1e148b..c9b596d12 100644
--- a/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
@@ -166,73 +166,79 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                            ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                            ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                             ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                            ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                            ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                           ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                           ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK        ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                      ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                     ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                      ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                     ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                      ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                     ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                      ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                     ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                      ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                     ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                      ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                     ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                      ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                     ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                      ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                     ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                    ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                    ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                    ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                    ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                    ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                    ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                    ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                    ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE                  ( 1UL )
+
+#if ( portARMV8M_MINOR_VERSION >= 1 )
+    /* Enable Privileged eXecute Never MPU attribute for the selected memory
+     * region. */
+    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER   ( 1UL << 4UL )
+#endif /* portARMV8M_MINOR_VERSION >= 1 */
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT      ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT          ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                      ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                          ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE             ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE                 ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -1880,6 +1886,16 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
                 xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
                                                                           ( portMPU_RLAR_REGION_ENABLE );
 
+                /* PXN. */
+                #if ( portARMV8M_MINOR_VERSION >= 1 )
+                {
+                    if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
+                    {
+                        xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
+                    }
+                }
+                #endif /* portARMV8M_MINOR_VERSION >= 1 */
+
                 /* Normal memory/ Device memory. */
                 if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
                 {
diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/portmacro.h b/portable/IAR/ARM_CM55_NTZ/non_secure/portmacro.h
index 92dc75fd1..95b179413 100644
--- a/portable/IAR/ARM_CM55_NTZ/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM55_NTZ/non_secure/portmacro.h
@@ -55,6 +55,7 @@
  */
 #define portARCH_NAME                    "Cortex-M55"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portARMV8M_MINOR_VERSION         1
 #define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM85/non_secure/port.c b/portable/IAR/ARM_CM85/non_secure/port.c
index 99e1e148b..c9b596d12 100644
--- a/portable/IAR/ARM_CM85/non_secure/port.c
+++ b/portable/IAR/ARM_CM85/non_secure/port.c
@@ -166,73 +166,79 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                            ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                            ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                             ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                            ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                            ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                           ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                           ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK        ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                      ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                     ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                      ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                     ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                      ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                     ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                      ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                     ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                      ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                     ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                      ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                     ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                      ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                     ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                      ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                     ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                    ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                    ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                    ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                    ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                    ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                    ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                    ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                    ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE                  ( 1UL )
+
+#if ( portARMV8M_MINOR_VERSION >= 1 )
+    /* Enable Privileged eXecute Never MPU attribute for the selected memory
+     * region. */
+    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER   ( 1UL << 4UL )
+#endif /* portARMV8M_MINOR_VERSION >= 1 */
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT      ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT          ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                      ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                          ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE             ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE                 ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -1880,6 +1886,16 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
                 xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
                                                                           ( portMPU_RLAR_REGION_ENABLE );
 
+                /* PXN. */
+                #if ( portARMV8M_MINOR_VERSION >= 1 )
+                {
+                    if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
+                    {
+                        xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
+                    }
+                }
+                #endif /* portARMV8M_MINOR_VERSION >= 1 */
+
                 /* Normal memory/ Device memory. */
                 if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
                 {
diff --git a/portable/IAR/ARM_CM85/non_secure/portmacro.h b/portable/IAR/ARM_CM85/non_secure/portmacro.h
index 02f67453a..efde68dc2 100644
--- a/portable/IAR/ARM_CM85/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM85/non_secure/portmacro.h
@@ -55,6 +55,7 @@
  */
 #define portARCH_NAME                    "Cortex-M85"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portARMV8M_MINOR_VERSION         1
 #define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/port.c b/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
index 99e1e148b..c9b596d12 100644
--- a/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
@@ -166,73 +166,79 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                            ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                            ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                             ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                            ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                            ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                           ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                           ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK        ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                      ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                     ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                      ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                     ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                      ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                     ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                      ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                     ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                      ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                     ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                      ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                     ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                      ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                     ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                      ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                     ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                    ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                    ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                    ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                    ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                    ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                    ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                    ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                    ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE                  ( 1UL )
+
+#if ( portARMV8M_MINOR_VERSION >= 1 )
+    /* Enable Privileged eXecute Never MPU attribute for the selected memory
+     * region. */
+    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER   ( 1UL << 4UL )
+#endif /* portARMV8M_MINOR_VERSION >= 1 */
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT      ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT          ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                      ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                          ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE             ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE                 ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -1880,6 +1886,16 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
                 xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
                                                                           ( portMPU_RLAR_REGION_ENABLE );
 
+                /* PXN. */
+                #if ( portARMV8M_MINOR_VERSION >= 1 )
+                {
+                    if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
+                    {
+                        xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
+                    }
+                }
+                #endif /* portARMV8M_MINOR_VERSION >= 1 */
+
                 /* Normal memory/ Device memory. */
                 if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
                 {
diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/portmacro.h b/portable/IAR/ARM_CM85_NTZ/non_secure/portmacro.h
index 02f67453a..efde68dc2 100644
--- a/portable/IAR/ARM_CM85_NTZ/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM85_NTZ/non_secure/portmacro.h
@@ -55,6 +55,7 @@
  */
 #define portARCH_NAME                    "Cortex-M85"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portARMV8M_MINOR_VERSION         1
 #define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 

From 9e838293c20f2ac09bd0f3599ac43057d11db924 Mon Sep 17 00:00:00 2001
From: Eric Dawe <eric.github@redocrehtona.dev>
Date: Mon, 24 Jun 2024 12:40:51 +0100
Subject: [PATCH 294/424] Update README.md (#1094)

Fix spelling of the word 'the' ('thw') in line 29
---
 portable/ThirdParty/GCC/RP2040/README.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/portable/ThirdParty/GCC/RP2040/README.md b/portable/ThirdParty/GCC/RP2040/README.md
index bd521d53f..5db8702c5 100644
--- a/portable/ThirdParty/GCC/RP2040/README.md
+++ b/portable/ThirdParty/GCC/RP2040/README.md
@@ -26,7 +26,7 @@ This will locate the FreeRTOS kernel if it is a direct sub-module of your projec
 version, you can include the FreeRTOS-Kernel support later in your CMake build (possibly in a subdirectory) and the
 FreeRTOS-Kernel support will only apply to those targets which explicitly include FreeRTOS support.
 
-As an alternative to the `import` statement above, you can just add this directory directly via thw following (with
+As an alternative to the `import` statement above, you can just add this directory directly via the following (with
 the same placement restrictions related to the Raspberry Pi Pico SDK version above):
 
 ```cmake

From 17dfd0f808c297955cc8d6d596b9d7b34ce83b29 Mon Sep 17 00:00:00 2001
From: Angel Cascarino <angel.cascarino@googlemail.com>
Date: Thu, 27 Jun 2024 23:49:53 +0100
Subject: [PATCH 295/424] Update XMOS xcore.ai port to be compatible with v11.x
 (#1096)

* Fix kexcept function

* Create dummy pxCurrentTCBs for xcore.ai port

* Additional commentary

* Add a layer of indirection to cope with singlecore

* Clarify use of _DoException
---
 portable/ThirdParty/xClang/XCOREAI/port.c    | 35 ++++++++++++++++++--
 portable/ThirdParty/xClang/XCOREAI/portasm.S |  9 ++---
 2 files changed, 36 insertions(+), 8 deletions(-)

diff --git a/portable/ThirdParty/xClang/XCOREAI/port.c b/portable/ThirdParty/xClang/XCOREAI/port.c
index ba4598b6b..ac12aa31a 100644
--- a/portable/ThirdParty/xClang/XCOREAI/port.c
+++ b/portable/ThirdParty/xClang/XCOREAI/port.c
@@ -12,6 +12,15 @@ static hwtimer_t xKernelTimer;
 
 uint32_t ulPortYieldRequired[ portMAX_CORE_COUNT ] = { pdFALSE };
 
+/* When this port was designed, it was assumed that pxCurrentTCBs would always
+   exist and that it would always be an array containing pointers to the current
+   TCBs for each core. In v11, this is not the case; if we are only running one
+   core, the symbol is pxCurrentTCB instead. Therefore, this port adds a layer
+   of indirection - we populate this pointer-to-pointer in the RTOS kernel entry
+   function below. This makes this port agnostic to whether it is running on SMP
+   or singlecore RTOS. */
+void ** xcorePvtTCBContainer;
+
 /*-----------------------------------------------------------*/
 
 void vIntercoreInterruptISR( void )
@@ -140,6 +149,28 @@ DEFINE_RTOS_KERNEL_ENTRY( void, vPortStartSchedulerOnCore, void )
     }
     #endif
 
+    /* Populate the TCBContainer depending on whether we're singlecore or SMP */
+    #if ( configNUMBER_OF_CORES == 1 )
+    {
+        asm volatile (
+            "ldaw %0, dp[pxCurrentTCB]\n\t"
+            : "=r"(xcorePvtTCBContainer)
+            : /* no inputs */
+            : /* no clobbers */
+            );
+    }
+    #else
+    {
+        asm volatile (
+            "ldaw %0, dp[pxCurrentTCBs]\n\t"
+            : "=r"(xcorePvtTCBContainer)
+            : /* no inputs */
+            : /* no clobbers */
+            );
+    }
+
+    #endif
+
     debug_printf( "FreeRTOS Core %d initialized\n", xCoreID );
 
     /*
@@ -147,8 +178,8 @@ DEFINE_RTOS_KERNEL_ENTRY( void, vPortStartSchedulerOnCore, void )
      * to run and jump into it.
      */
     asm volatile (
-        "mov r6, %0\n\t"                 /* R6 must be the FreeRTOS core ID*/
-        "ldaw r5, dp[pxCurrentTCBs]\n\t" /* R5 must be the TCB list which is indexed by R6 */
+        "mov r6, %0\n\t"                       /* R6 must be the FreeRTOS core ID. In singlecore this is always 0. */
+        "ldw r5, dp[xcorePvtTCBContainer]\n\t" /* R5 must be the TCB list which is indexed by R6 */
         "bu _freertos_restore_ctx\n\t"
         :                                /* no outputs */
         : "r" ( xCoreID )
diff --git a/portable/ThirdParty/xClang/XCOREAI/portasm.S b/portable/ThirdParty/xClang/XCOREAI/portasm.S
index 7445672a0..64b7b9d9a 100644
--- a/portable/ThirdParty/xClang/XCOREAI/portasm.S
+++ b/portable/ThirdParty/xClang/XCOREAI/portasm.S
@@ -14,11 +14,8 @@ rest of the ISR callback functions. */
 .issue_mode dual
 .cc_top kexcept.function, kexcept
 kexcept:
-  ldc r11, 0x0008
-  shl r11, r11, 16
-  ldc r9, 0x0080
-  or  r11, r11, r9
-  bau r11 //_TrapHandler is at 0x00080080. TODO: Is it always? Why can't I access the symbol _TrapHandler?
+  bu _DoException       /* This symbol is generated by the toolchain and */
+                        /* provides graceful exception handling */
 
 _yield:
  {set    sp,     r4                  /* Restore the task's SP to save the rest of its context. */
@@ -123,7 +120,7 @@ _yield_continue:
   ldaw   r11,    sp[37]}
   vstc   r11[0]
 #endif
-  ldaw   r5,     dp[pxCurrentTCBs] /* Get the current TCB array into r5. */
+  ldw    r5,     dp[xcorePvtTCBContainer]
   ldw    r1,     r5[r0]            /* Get this core's current TCB pointer into r1. */
   stw    r4,     r1[0x0]           /* Save the current task's SP to the first */
                                    /* word (top of stack) in the current TCB. */

From 646881e7f9708327b159f5df4b771cc28af76f0a Mon Sep 17 00:00:00 2001
From: Florian La Roche <florian.laroche@gmail.com>
Date: Sat, 29 Jun 2024 08:07:15 +0200
Subject: [PATCH 296/424] fix typo gab -> gap and adjust indentation level
 (#1097)

Signed-off-by: Florian La Roche <Florian.LaRoche@gmail.com>
---
 portable/ARMv8M/secure/heap/secure_heap.c   | 2 +-
 portable/GCC/ARM_CM23/secure/secure_heap.c  | 2 +-
 portable/GCC/ARM_CM33/secure/secure_heap.c  | 2 +-
 portable/GCC/ARM_CM35P/secure/secure_heap.c | 2 +-
 portable/GCC/ARM_CM55/secure/secure_heap.c  | 2 +-
 portable/GCC/ARM_CM85/secure/secure_heap.c  | 2 +-
 portable/IAR/ARM_CM23/secure/secure_heap.c  | 2 +-
 portable/IAR/ARM_CM33/secure/secure_heap.c  | 2 +-
 portable/IAR/ARM_CM35P/secure/secure_heap.c | 2 +-
 portable/IAR/ARM_CM55/secure/secure_heap.c  | 2 +-
 portable/IAR/ARM_CM85/secure/secure_heap.c  | 2 +-
 portable/MemMang/heap_1.c                   | 2 +-
 portable/MemMang/heap_2.c                   | 2 +-
 portable/MemMang/heap_4.c                   | 4 ++--
 14 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/portable/ARMv8M/secure/heap/secure_heap.c b/portable/ARMv8M/secure/heap/secure_heap.c
index 55722d4e7..f77320ed2 100644
--- a/portable/ARMv8M/secure/heap/secure_heap.c
+++ b/portable/ARMv8M/secure/heap/secure_heap.c
@@ -234,7 +234,7 @@ static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert )
         pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
     }
 
-    /* If the block being inserted plugged a gab, so was merged with the block
+    /* If the block being inserted plugged a gap, so was merged with the block
      * before and the block after, then it's pxNextFreeBlock pointer will have
      * already been set, and should not be set here as that would make it point
      * to itself. */
diff --git a/portable/GCC/ARM_CM23/secure/secure_heap.c b/portable/GCC/ARM_CM23/secure/secure_heap.c
index 55722d4e7..f77320ed2 100644
--- a/portable/GCC/ARM_CM23/secure/secure_heap.c
+++ b/portable/GCC/ARM_CM23/secure/secure_heap.c
@@ -234,7 +234,7 @@ static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert )
         pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
     }
 
-    /* If the block being inserted plugged a gab, so was merged with the block
+    /* If the block being inserted plugged a gap, so was merged with the block
      * before and the block after, then it's pxNextFreeBlock pointer will have
      * already been set, and should not be set here as that would make it point
      * to itself. */
diff --git a/portable/GCC/ARM_CM33/secure/secure_heap.c b/portable/GCC/ARM_CM33/secure/secure_heap.c
index 55722d4e7..f77320ed2 100644
--- a/portable/GCC/ARM_CM33/secure/secure_heap.c
+++ b/portable/GCC/ARM_CM33/secure/secure_heap.c
@@ -234,7 +234,7 @@ static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert )
         pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
     }
 
-    /* If the block being inserted plugged a gab, so was merged with the block
+    /* If the block being inserted plugged a gap, so was merged with the block
      * before and the block after, then it's pxNextFreeBlock pointer will have
      * already been set, and should not be set here as that would make it point
      * to itself. */
diff --git a/portable/GCC/ARM_CM35P/secure/secure_heap.c b/portable/GCC/ARM_CM35P/secure/secure_heap.c
index 55722d4e7..f77320ed2 100644
--- a/portable/GCC/ARM_CM35P/secure/secure_heap.c
+++ b/portable/GCC/ARM_CM35P/secure/secure_heap.c
@@ -234,7 +234,7 @@ static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert )
         pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
     }
 
-    /* If the block being inserted plugged a gab, so was merged with the block
+    /* If the block being inserted plugged a gap, so was merged with the block
      * before and the block after, then it's pxNextFreeBlock pointer will have
      * already been set, and should not be set here as that would make it point
      * to itself. */
diff --git a/portable/GCC/ARM_CM55/secure/secure_heap.c b/portable/GCC/ARM_CM55/secure/secure_heap.c
index 55722d4e7..f77320ed2 100644
--- a/portable/GCC/ARM_CM55/secure/secure_heap.c
+++ b/portable/GCC/ARM_CM55/secure/secure_heap.c
@@ -234,7 +234,7 @@ static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert )
         pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
     }
 
-    /* If the block being inserted plugged a gab, so was merged with the block
+    /* If the block being inserted plugged a gap, so was merged with the block
      * before and the block after, then it's pxNextFreeBlock pointer will have
      * already been set, and should not be set here as that would make it point
      * to itself. */
diff --git a/portable/GCC/ARM_CM85/secure/secure_heap.c b/portable/GCC/ARM_CM85/secure/secure_heap.c
index 55722d4e7..f77320ed2 100644
--- a/portable/GCC/ARM_CM85/secure/secure_heap.c
+++ b/portable/GCC/ARM_CM85/secure/secure_heap.c
@@ -234,7 +234,7 @@ static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert )
         pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
     }
 
-    /* If the block being inserted plugged a gab, so was merged with the block
+    /* If the block being inserted plugged a gap, so was merged with the block
      * before and the block after, then it's pxNextFreeBlock pointer will have
      * already been set, and should not be set here as that would make it point
      * to itself. */
diff --git a/portable/IAR/ARM_CM23/secure/secure_heap.c b/portable/IAR/ARM_CM23/secure/secure_heap.c
index 55722d4e7..f77320ed2 100644
--- a/portable/IAR/ARM_CM23/secure/secure_heap.c
+++ b/portable/IAR/ARM_CM23/secure/secure_heap.c
@@ -234,7 +234,7 @@ static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert )
         pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
     }
 
-    /* If the block being inserted plugged a gab, so was merged with the block
+    /* If the block being inserted plugged a gap, so was merged with the block
      * before and the block after, then it's pxNextFreeBlock pointer will have
      * already been set, and should not be set here as that would make it point
      * to itself. */
diff --git a/portable/IAR/ARM_CM33/secure/secure_heap.c b/portable/IAR/ARM_CM33/secure/secure_heap.c
index 55722d4e7..f77320ed2 100644
--- a/portable/IAR/ARM_CM33/secure/secure_heap.c
+++ b/portable/IAR/ARM_CM33/secure/secure_heap.c
@@ -234,7 +234,7 @@ static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert )
         pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
     }
 
-    /* If the block being inserted plugged a gab, so was merged with the block
+    /* If the block being inserted plugged a gap, so was merged with the block
      * before and the block after, then it's pxNextFreeBlock pointer will have
      * already been set, and should not be set here as that would make it point
      * to itself. */
diff --git a/portable/IAR/ARM_CM35P/secure/secure_heap.c b/portable/IAR/ARM_CM35P/secure/secure_heap.c
index 55722d4e7..f77320ed2 100644
--- a/portable/IAR/ARM_CM35P/secure/secure_heap.c
+++ b/portable/IAR/ARM_CM35P/secure/secure_heap.c
@@ -234,7 +234,7 @@ static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert )
         pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
     }
 
-    /* If the block being inserted plugged a gab, so was merged with the block
+    /* If the block being inserted plugged a gap, so was merged with the block
      * before and the block after, then it's pxNextFreeBlock pointer will have
      * already been set, and should not be set here as that would make it point
      * to itself. */
diff --git a/portable/IAR/ARM_CM55/secure/secure_heap.c b/portable/IAR/ARM_CM55/secure/secure_heap.c
index 55722d4e7..f77320ed2 100644
--- a/portable/IAR/ARM_CM55/secure/secure_heap.c
+++ b/portable/IAR/ARM_CM55/secure/secure_heap.c
@@ -234,7 +234,7 @@ static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert )
         pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
     }
 
-    /* If the block being inserted plugged a gab, so was merged with the block
+    /* If the block being inserted plugged a gap, so was merged with the block
      * before and the block after, then it's pxNextFreeBlock pointer will have
      * already been set, and should not be set here as that would make it point
      * to itself. */
diff --git a/portable/IAR/ARM_CM85/secure/secure_heap.c b/portable/IAR/ARM_CM85/secure/secure_heap.c
index 55722d4e7..f77320ed2 100644
--- a/portable/IAR/ARM_CM85/secure/secure_heap.c
+++ b/portable/IAR/ARM_CM85/secure/secure_heap.c
@@ -234,7 +234,7 @@ static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert )
         pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
     }
 
-    /* If the block being inserted plugged a gab, so was merged with the block
+    /* If the block being inserted plugged a gap, so was merged with the block
      * before and the block after, then it's pxNextFreeBlock pointer will have
      * already been set, and should not be set here as that would make it point
      * to itself. */
diff --git a/portable/MemMang/heap_1.c b/portable/MemMang/heap_1.c
index 0f7661356..f697c907c 100644
--- a/portable/MemMang/heap_1.c
+++ b/portable/MemMang/heap_1.c
@@ -65,7 +65,7 @@
 #if ( configAPPLICATION_ALLOCATED_HEAP == 1 )
 
 /* The application writer has already defined the array used for the RTOS
-* heap - probably so it can be placed in a special segment or address. */
+ * heap - probably so it can be placed in a special segment or address. */
     extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
 #else
     static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
diff --git a/portable/MemMang/heap_2.c b/portable/MemMang/heap_2.c
index a99a74d76..fa6ea9d9b 100644
--- a/portable/MemMang/heap_2.c
+++ b/portable/MemMang/heap_2.c
@@ -87,7 +87,7 @@
 #if ( configAPPLICATION_ALLOCATED_HEAP == 1 )
 
 /* The application writer has already defined the array used for the RTOS
-* heap - probably so it can be placed in a special segment or address. */
+ * heap - probably so it can be placed in a special segment or address. */
     extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
 #else
     PRIVILEGED_DATA static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
diff --git a/portable/MemMang/heap_4.c b/portable/MemMang/heap_4.c
index fe15654ed..d1021ea09 100644
--- a/portable/MemMang/heap_4.c
+++ b/portable/MemMang/heap_4.c
@@ -89,7 +89,7 @@
 #if ( configAPPLICATION_ALLOCATED_HEAP == 1 )
 
 /* The application writer has already defined the array used for the RTOS
-* heap - probably so it can be placed in a special segment or address. */
+ * heap - probably so it can be placed in a special segment or address. */
     extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
 #else
     PRIVILEGED_DATA static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
@@ -548,7 +548,7 @@ static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) /* PRIVI
         pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
     }
 
-    /* If the block being inserted plugged a gab, so was merged with the block
+    /* If the block being inserted plugged a gap, so was merged with the block
      * before and the block after, then it's pxNextFreeBlock pointer will have
      * already been set, and should not be set here as that would make it point
      * to itself. */

From f4f2e1596b08f70ab1e193771c0f38e2ee351091 Mon Sep 17 00:00:00 2001
From: Florian La Roche <florian.laroche@gmail.com>
Date: Sat, 29 Jun 2024 17:20:45 +0200
Subject: [PATCH 297/424] Fix gcc warning in posix port (#1098)

Fix warning from "gcc -Wsign-compare" in the file
portable/ThirdParty/GCC/Posix/port.c since PTHREAD_STACK_MIN
is used from system headers.

Signed-off-by: Florian La Roche <Florian.LaRoche@gmail.com>
Co-authored-by: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
---
 portable/ThirdParty/GCC/Posix/port.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/portable/ThirdParty/GCC/Posix/port.c b/portable/ThirdParty/GCC/Posix/port.c
index 05f08cf7c..0b18da4df 100644
--- a/portable/ThirdParty/GCC/Posix/port.c
+++ b/portable/ThirdParty/GCC/Posix/port.c
@@ -180,7 +180,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
     thread->xDying = pdFALSE;
 
     /* Ensure ulStackSize is at least PTHREAD_STACK_MIN */
-    ulStackSize = (ulStackSize < PTHREAD_STACK_MIN) ? PTHREAD_STACK_MIN : ulStackSize;
+    ulStackSize = (ulStackSize < ( size_t ) ( PTHREAD_STACK_MIN ) ) ? ( size_t ) ( PTHREAD_STACK_MIN ) : ulStackSize;
 
     pthread_attr_init( &xThreadAttributes );
     iRet = pthread_attr_setstacksize( &xThreadAttributes, ulStackSize );

From 0452603a943e13d27e7117f7112c4dd000748705 Mon Sep 17 00:00:00 2001
From: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Date: Mon, 1 Jul 2024 17:02:00 +0800
Subject: [PATCH 298/424] Update LTS 202406 information (#1099)

---
 README.md | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/README.md b/README.md
index ce34d56ab..b574bad55 100644
--- a/README.md
+++ b/README.md
@@ -24,6 +24,12 @@ and [API Reference](https://www.FreeRTOS.org/a00106.html).
 Also for contributing and creating a Pull Request please refer to
 [the instructions here](.github/CONTRIBUTING.md#contributing-via-pull-request).
 
+**FreeRTOS-Kernel V11.1.0
+[source code](https://github.com/FreeRTOS/FreeRTOS-Kernel/tree/V11.1.0) is part
+of the
+[FreeRTOS 202406.00 LTS](https://github.com/FreeRTOS/FreeRTOS-LTS/tree/202406-LTS)
+release.**
+
 ### Getting help
 
 If you have any questions or need assistance troubleshooting your FreeRTOS project,

From 5588ae68c8c78e5903e3ed030998238534606b5c Mon Sep 17 00:00:00 2001
From: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Date: Mon, 22 Jul 2024 21:05:17 +0530
Subject: [PATCH 299/424] Update ARM_CRx_No_GIC port (#1101)

This PR makes the following improvements to the ARM_CRx_No_GIC port-

1. Remove inline assembly and move all the assembly code to the portASM.S
    file.

2. Add support for configUSE_TASK_FPU_SUPPORT -
   - When configUSE_TASK_FPU_SUPPORT is defined to 1, tasks are created
      without floating point context. Tasks that want to use floating point, need
      to call portTASK_USES_FLOATING_POINT(). This is the current behavior.
   - When configUSE_TASK_FPU_SUPPORT is defined to 2, each task is created
      with a floating point context.
  If left undefined, configUSE_TASK_FPU_SUPPORT defaults to 1 for backward compatibility.

3. The application writer can now implement vApplicationSVCHandler to handle the
    SVC calls raised within the application. SVC 0 is used for the yield kernel operation
    and the application can use all the SVC calls other than 0.

Signed-off-by: kar-rahul-aws <karahulx@amazon.com>
---
 portable/GCC/ARM_CRx_No_GIC/port.c      |  67 ++++--
 portable/GCC/ARM_CRx_No_GIC/portASM.S   | 303 +++++++++++++++++-------
 portable/GCC/ARM_CRx_No_GIC/portmacro.h |  86 ++++---
 3 files changed, 308 insertions(+), 148 deletions(-)

diff --git a/portable/GCC/ARM_CRx_No_GIC/port.c b/portable/GCC/ARM_CRx_No_GIC/port.c
index 7294fb760..bd5a19a49 100644
--- a/portable/GCC/ARM_CRx_No_GIC/port.c
+++ b/portable/GCC/ARM_CRx_No_GIC/port.c
@@ -28,6 +28,7 @@
 
 /* Standard includes. */
 #include <stdlib.h>
+#include <string.h>
 
 /* Scheduler includes. */
 #include "FreeRTOS.h"
@@ -80,13 +81,22 @@
     #define portTASK_RETURN_ADDRESS    prvTaskExitError
 #endif
 
+/* The space on the stack required to hold the FPU registers. */
+#if ( configFPU_D32 == 1 )
+    #define portFPU_REGISTER_WORDS     ( ( 32 * 2 ) + 1 ) /* D0-D31 and FPSCR. */
+#else
+    #define portFPU_REGISTER_WORDS     ( ( 16 * 2 ) + 1 ) /* D0-D15 and FPSCR. */
+#endif /* configFPU_D32 */
+
 /*-----------------------------------------------------------*/
 
 /*
- * Starts the first task executing.  This function is necessarily written in
- * assembly code so is implemented in portASM.s.
+ * These functions are necessarily written in assembly code, so are implemented
+ * in portASM.S.
  */
 extern void vPortRestoreTaskContext( void );
+extern void vPortInitialiseFPSCR( void );
+extern uint32_t ulReadAPSR( void );
 
 /*
  * Used to catch tasks that attempt to return from their implementing function.
@@ -184,12 +194,33 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
     /* The task will start with a critical nesting count of 0 as interrupts are
      * enabled. */
     *pxTopOfStack = portNO_CRITICAL_NESTING;
-    pxTopOfStack--;
 
-    /* The task will start without a floating point context.  A task that uses
-     * the floating point hardware must call vPortTaskUsesFPU() before executing
-     * any floating point instructions. */
-    *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
+    #if ( configUSE_TASK_FPU_SUPPORT == 1 )
+    {
+        /* The task will start without a floating point context.  A task that uses
+         * the floating point hardware must call vPortTaskUsesFPU() before executing
+         * any floating point instructions. */
+        pxTopOfStack--;
+        *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
+    }
+    #elif ( configUSE_TASK_FPU_SUPPORT == 2 )
+    {
+        /* The task will start with a floating point context.  Leave enough
+         * space for the registers - and ensure they are initialised to 0. */
+        pxTopOfStack -= portFPU_REGISTER_WORDS;
+        memset( pxTopOfStack, 0x00, portFPU_REGISTER_WORDS * sizeof( StackType_t ) );
+
+        /* Initialise the slot containing ulPortTaskHasFPUContext to true as
+         * the task starts with a floating point context. */
+        pxTopOfStack--;
+        *pxTopOfStack = pdTRUE;
+        ulPortTaskHasFPUContext = pdTRUE;
+    }
+    #else
+    {
+        #error "Invalid configUSE_TASK_FPU_SUPPORT value - configUSE_TASK_FPU_SUPPORT must be set to 1, 2, or left undefined."
+    }
+    #endif /* if ( configUSE_TASK_FPU_SUPPORT == 1 ) */
 
     return pxTopOfStack;
 }
@@ -218,7 +249,7 @@ BaseType_t xPortStartScheduler( void )
 
     /* Only continue if the CPU is not in User mode.  The CPU must be in a
      * Privileged mode for the scheduler to start. */
-    __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR )::"memory" );
+    ulAPSR = ulReadAPSR();
 
     ulAPSR &= portAPSR_MODE_BITS_MASK;
     configASSERT( ulAPSR != portAPSR_USER_MODE );
@@ -310,15 +341,17 @@ void FreeRTOS_Tick_Handler( void )
 }
 /*-----------------------------------------------------------*/
 
-void vPortTaskUsesFPU( void )
-{
-    uint32_t ulInitialFPSCR = 0;
+#if ( configUSE_TASK_FPU_SUPPORT != 2 )
 
-    /* A task is registering the fact that it needs an FPU context.  Set the
-     * FPU flag (which is saved as part of the task context). */
-    ulPortTaskHasFPUContext = pdTRUE;
+    void vPortTaskUsesFPU( void )
+    {
+        /* A task is registering the fact that it needs an FPU context.  Set the
+         * FPU flag (which is saved as part of the task context). */
+        ulPortTaskHasFPUContext = pdTRUE;
 
-    /* Initialise the floating point status register. */
-    __asm volatile ( "FMXR  FPSCR, %0" ::"r" ( ulInitialFPSCR ) : "memory" );
-}
+        /* Initialise the floating point status register. */
+        vPortInitialiseFPSCR();
+    }
+
+#endif /* configUSE_TASK_FPU_SUPPORT */
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CRx_No_GIC/portASM.S b/portable/GCC/ARM_CRx_No_GIC/portASM.S
index 349a940d9..9945fc2d9 100644
--- a/portable/GCC/ARM_CRx_No_GIC/portASM.S
+++ b/portable/GCC/ARM_CRx_No_GIC/portASM.S
@@ -28,14 +28,14 @@
 
     .text
     .arm
+    .syntax unified
 
-    .set SYS_MODE,  0x1f
-    .set SVC_MODE,  0x13
-    .set IRQ_MODE,  0x12
+    .set SYS_MODE,   0x1f
+    .set SVC_MODE,   0x13
+    .set IRQ_MODE,   0x12
+    .set CPSR_I_BIT, 0x80
 
     /* Variables and functions. */
-    .extern ulMaxAPIPriorityMask
-    .extern _freertos_vector_table
     .extern pxCurrentTCB
     .extern vTaskSwitchContext
     .extern vApplicationIRQHandler
@@ -47,29 +47,38 @@
     .global FreeRTOS_IRQ_Handler
     .global FreeRTOS_SVC_Handler
     .global vPortRestoreTaskContext
+    .global vPortInitialiseFPSCR
+    .global ulReadAPSR
+    .global vPortYield
+    .global vPortEnableInterrupts
+    .global vPortDisableInterrupts
+    .global ulPortSetInterruptMaskFromISR
+    .global ulPortCountLeadingZeros
 
+    .weak   vApplicationSVCHandler
+/*-----------------------------------------------------------*/
 
 .macro portSAVE_CONTEXT
 
     /* Save the LR and SPSR onto the system mode stack before switching to
-    system mode to save the remaining system mode registers. */
-    SRSDB   sp!, #SYS_MODE
+     * system mode to save the remaining system mode registers. */
+    SRSDB   SP!, #SYS_MODE
     CPS     #SYS_MODE
     PUSH    {R0-R12, R14}
 
     /* Push the critical nesting count. */
-    LDR     R2, ulCriticalNestingConst
+    LDR     R2, =ulCriticalNesting
     LDR     R1, [R2]
     PUSH    {R1}
 
     /* Does the task have a floating point context that needs saving?  If
-    ulPortTaskHasFPUContext is 0 then no. */
-    LDR     R2, ulPortTaskHasFPUContextConst
+     * ulPortTaskHasFPUContext is 0 then no. */
+    LDR     R2, =ulPortTaskHasFPUContext
     LDR     R3, [R2]
     CMP     R3, #0
 
     /* Save the floating point context, if any. */
-    FMRXNE  R1,  FPSCR
+    VMRSNE  R1,  FPSCR
     VPUSHNE {D0-D15}
 #if configFPU_D32 == 1
     VPUSHNE {D16-D31}
@@ -80,24 +89,24 @@
     PUSH    {R3}
 
     /* Save the stack pointer in the TCB. */
-    LDR     R0, pxCurrentTCBConst
+    LDR     R0, =pxCurrentTCB
     LDR     R1, [R0]
     STR     SP, [R1]
 
     .endm
 
-; /**********************************************************************/
+/*-----------------------------------------------------------*/
 
 .macro portRESTORE_CONTEXT
 
     /* Set the SP to point to the stack of the task being restored. */
-    LDR     R0, pxCurrentTCBConst
+    LDR     R0, =pxCurrentTCB
     LDR     R1, [R0]
     LDR     SP, [R1]
 
     /* Is there a floating point context to restore?  If the restored
-    ulPortTaskHasFPUContext is zero then no. */
-    LDR     R0, ulPortTaskHasFPUContextConst
+     * ulPortTaskHasFPUContext is zero then no. */
+    LDR     R0, =ulPortTaskHasFPUContext
     POP     {R1}
     STR     R1, [R0]
     CMP     R1, #0
@@ -111,7 +120,7 @@
     VMSRNE  FPSCR, R0
 
     /* Restore the critical section nesting depth. */
-    LDR     R0, ulCriticalNestingConst
+    LDR     R0, =ulCriticalNesting
     POP     {R1}
     STR     R1, [R0]
 
@@ -120,29 +129,17 @@
     POP     {R0-R12, R14}
 
     /* Return to the task code, loading CPSR on the way. */
-    RFEIA   sp!
+    RFEIA   SP!
 
     .endm
 
+/*-----------------------------------------------------------*/
 
-
-
-/******************************************************************************
- * SVC handler is used to yield.
- *****************************************************************************/
-.align 4
-.type FreeRTOS_SVC_Handler, %function
-FreeRTOS_SVC_Handler:
-    /* Save the context of the current task and select a new task to run. */
-    portSAVE_CONTEXT
-    LDR R0, vTaskSwitchContextConst
-    BLX R0
-    portRESTORE_CONTEXT
-
-
-/******************************************************************************
+/*
+ * void vPortRestoreTaskContext( void );
+ *
  * vPortRestoreTaskContext is used to start the scheduler.
- *****************************************************************************/
+ */
 .align 4
 .type vPortRestoreTaskContext, %function
 vPortRestoreTaskContext:
@@ -150,72 +147,212 @@ vPortRestoreTaskContext:
     CPS     #SYS_MODE
     portRESTORE_CONTEXT
 
+/*-----------------------------------------------------------*/
+
+/*
+ * void vPortInitialiseFPSCR( void );
+ *
+ * vPortInitialiseFPSCR is used to initialize the FPSCR register.
+ */
+.align 4
+.type vPortInitialiseFPSCR, %function
+vPortInitialiseFPSCR:
+    MOV     R0, #0
+    VMSR    FPSCR, R0
+    BX      LR
+
+/*-----------------------------------------------------------*/
+
+/*
+ * uint32_t ulReadAPSR( void );
+ *
+ * ulReadAPSR is used to read the value of APSR context.
+ */
+.align 4
+.type ulReadAPSR, %function
+ulReadAPSR:
+    MRS R0, APSR
+    BX  LR
+
+/*-----------------------------------------------------------*/
+
+/*
+ * void vPortYield( void );
+ */
+.align 4
+.type vPortYield, %function
+vPortYield:
+    SVC 0
+    ISB
+    BX  LR
+
+/*-----------------------------------------------------------*/
+
+/*
+ * void vPortEnableInterrupts( void );
+ */
+.align 4
+.type vPortEnableInterrupts, %function
+vPortEnableInterrupts:
+    CPSIE   I
+    BX      LR
+
+/*-----------------------------------------------------------*/
+
+/*
+ * void vPortDisableInterrupts( void );
+ */
+.align 4
+.type vPortDisableInterrupts, %function
+vPortDisableInterrupts:
+    CPSID    I
+    DSB
+    ISB
+    BX      LR
+
+/*-----------------------------------------------------------*/
+
+/*
+ * uint32_t ulPortSetInterruptMaskFromISR( void );
+ */
+.align 4
+.type ulPortSetInterruptMaskFromISR, %function
+ulPortSetInterruptMaskFromISR:
+    MRS     R0, CPSR
+    AND     R0, R0, #CPSR_I_BIT
+    CPSID   I
+    DSB
+    ISB
+    BX      LR
+
+/*-----------------------------------------------------------*/
+
+/*
+ * void vApplicationSVCHandler( uint32_t ulSvcNumber );
+ */
+.align 4
+.type vApplicationSVCHandler, %function
+vApplicationSVCHandler:
+    B vApplicationSVCHandler
+
+/*-----------------------------------------------------------*/
+
+/*
+ * UBaseType_t ulPortCountLeadingZeros( UBaseType_t ulBitmap );
+ *
+ * According to the Procedure Call Standard for the ARM Architecture (AAPCS):
+ * - Parameter ulBitmap is passed in R0.
+ * - Return value must be in R0.
+ */
+.align 4
+.type ulPortCountLeadingZeros, %function
+ulPortCountLeadingZeros:
+    CLZ     R0, R0
+    BX      LR
+
+/*-----------------------------------------------------------*/
+
+/*
+ * SVC handler is used to yield.
+ */
+.align 4
+.type FreeRTOS_SVC_Handler, %function
+FreeRTOS_SVC_Handler:
+    PUSH    { R0-R1 }
+
+    /* ---------------------------- Get Caller SVC Number ---------------------------- */
+    MRS     R0, SPSR               /* R0 = CPSR at the time of SVC. */
+    TST     R0, #0x20              /* Check Thumb bit (5) in CPSR. */
+    LDRHNE  R0, [LR, #-0x2]        /* If Thumb, load halfword. */
+    BICNE   R0, R0, #0xFF00        /* And extract immidiate field (i.e. SVC number). */
+    LDREQ   R0, [LR, #-0x4]        /* If ARM, load word. */
+    BICEQ   R0, R0, #0xFF000000    /* And extract immidiate field (i.e. SVC number). */
+
+    /* --------------------------------- SVC Routing --------------------------------- */
+    CMP     R0, #0
+    BEQ     svcPortYield
+    BNE     svcApplicationCall
+
+svcPortYield:
+    POP     { R0-R1 }
+    portSAVE_CONTEXT
+    BLX     vTaskSwitchContext
+    portRESTORE_CONTEXT
+
+svcApplicationCall:
+    POP     { R0-R1 }
+    portSAVE_CONTEXT
+    BLX     vApplicationSVCHandler
+    portRESTORE_CONTEXT
+
+/*-----------------------------------------------------------*/
+
 .align 4
 .type FreeRTOS_IRQ_Handler, %function
 FreeRTOS_IRQ_Handler:
     /* Return to the interrupted instruction. */
-    SUB     lr, lr, #4
+    SUB     LR, LR, #4
 
     /* Push the return address and SPSR. */
-    PUSH    {lr}
-    MRS     lr, SPSR
-    PUSH    {lr}
+    PUSH    {LR}
+    MRS     LR, SPSR
+    PUSH    {LR}
 
     /* Change to supervisor mode to allow reentry. */
-    CPS     #0x13
+    CPS     #SVC_MODE
 
     /* Push used registers. */
-    PUSH    {r0-r3, r12}
+    PUSH    {R0-R3, R12}
 
     /* Increment nesting count.  r3 holds the address of ulPortInterruptNesting
-    for future use.  r1 holds the original ulPortInterruptNesting value for
-    future use. */
-    LDR     r3, ulPortInterruptNestingConst
-    LDR     r1, [r3]
-    ADD     r0, r1, #1
-    STR     r0, [r3]
+     * for future use.  r1 holds the original ulPortInterruptNesting value for
+     * future use. */
+    LDR     R3, =ulPortInterruptNesting
+    LDR     R1, [R3]
+    ADD     R0, R1, #1
+    STR     R0, [R3]
 
     /* Ensure bit 2 of the stack pointer is clear.  r2 holds the bit 2 value for
-    future use. */
-    MOV     r0, sp
-    AND     r2, r0, #4
-    SUB     sp, sp, r2
+     * future use. */
+    MOV     R0, SP
+    AND     R2, R0, #4
+    SUB     SP, SP, R2
 
     /* Call the interrupt handler. */
-    PUSH    {r0-r3, lr}
-    LDR     r1, vApplicationIRQHandlerConst
-    BLX     r1
-    POP     {r0-r3, lr}
-    ADD     sp, sp, r2
+    PUSH    {R0-R3, LR}
+    BLX     vApplicationIRQHandler
+    POP     {R0-R3, LR}
+    ADD     SP, SP, R2
 
+    /* Disable IRQs incase vApplicationIRQHandler enabled them for re-entry. */
     CPSID   i
     DSB
     ISB
 
     /* Write to the EOI register. */
-    LDR     r0, ulICCEOIRConst
-    LDR     r2, [r0]
-    STR     r0, [r2]
+    LDR     R0, =ulICCEOIR
+    LDR     R2, [R0]
+    STR     R0, [R2]
 
     /* Restore the old nesting count. */
-    STR     r1, [r3]
+    STR     R1, [R3]
 
     /* A context switch is never performed if the nesting count is not 0. */
-    CMP     r1, #0
+    CMP     R1, #0
     BNE     exit_without_switch
 
     /* Did the interrupt request a context switch?  r1 holds the address of
-    ulPortYieldRequired and r0 the value of ulPortYieldRequired for future
-    use. */
-    LDR     r1, ulPortYieldRequiredConst
-    LDR     r0, [r1]
-    CMP     r0, #0
+     * ulPortYieldRequired and r0 the value of ulPortYieldRequired for future
+     * use. */
+    LDR     R1, =ulPortYieldRequired
+    LDR     R0, [R1]
+    CMP     R0, #0
     BNE     switch_before_exit
 
 exit_without_switch:
     /* No context switch.  Restore used registers, LR_irq and SPSR before
-    returning. */
-    POP     {r0-r3, r12}
+     * returning. */
+    POP     {R0-R3, R12}
     CPS     #IRQ_MODE
     POP     {LR}
     MSR     SPSR_cxsf, LR
@@ -224,13 +361,13 @@ exit_without_switch:
 
 switch_before_exit:
     /* A context switch is to be performed.  Clear the context switch pending
-    flag. */
-    MOV     r0, #0
-    STR     r0, [r1]
+     * flag. */
+    MOV     R0, #0
+    STR     R0, [R1]
 
     /* Restore used registers, LR-irq and SPSR before saving the context
-    to the task stack. */
-    POP     {r0-r3, r12}
+     * to the task stack. */
+    POP     {R0-R3, R12}
     CPS     #IRQ_MODE
     POP     {LR}
     MSR     SPSR_cxsf, LR
@@ -238,23 +375,15 @@ switch_before_exit:
     portSAVE_CONTEXT
 
     /* Call the function that selects the new task to execute.
-    vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD
-    instructions, or 8 byte aligned stack allocated data.  LR does not need
-    saving as a new LR will be loaded by portRESTORE_CONTEXT anyway. */
-    LDR     R0, vTaskSwitchContextConst
-    BLX     R0
+     * vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD
+     * instructions, or 8 byte aligned stack allocated data.  LR does not need
+     * saving as a new LR will be loaded by portRESTORE_CONTEXT anyway. */
+    BLX     vTaskSwitchContext
 
     /* Restore the context of, and branch to, the task selected to execute
-    next. */
+     * next. */
     portRESTORE_CONTEXT
 
-ulICCEOIRConst: .word ulICCEOIR
-pxCurrentTCBConst: .word pxCurrentTCB
-ulCriticalNestingConst: .word ulCriticalNesting
-ulPortTaskHasFPUContextConst: .word ulPortTaskHasFPUContext
-vTaskSwitchContextConst: .word vTaskSwitchContext
-vApplicationIRQHandlerConst: .word vApplicationIRQHandler
-ulPortInterruptNestingConst: .word ulPortInterruptNesting
-ulPortYieldRequiredConst: .word ulPortYieldRequired
+/*-----------------------------------------------------------*/
 
 .end
diff --git a/portable/GCC/ARM_CRx_No_GIC/portmacro.h b/portable/GCC/ARM_CRx_No_GIC/portmacro.h
index 5a9ae265e..b29bd9be1 100644
--- a/portable/GCC/ARM_CRx_No_GIC/portmacro.h
+++ b/portable/GCC/ARM_CRx_No_GIC/portmacro.h
@@ -59,7 +59,7 @@ typedef long             BaseType_t;
 typedef unsigned long    UBaseType_t;
 
 typedef uint32_t         TickType_t;
-#define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+#define portMAX_DELAY    ( TickType_t ) 0xffffffffUL
 
 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
  * not need to be guarded with a critical section. */
@@ -88,47 +88,31 @@ typedef uint32_t         TickType_t;
     }
 
 #define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
-#define portYIELD()                 \
-    __asm volatile ( "SWI 0     \n" \
-                     "ISB         " ::: "memory" );
 
+void vPortYield( void );
 
-/*-----------------------------------------------------------
-* Critical section control
-*----------------------------------------------------------*/
+#define portYIELD()     vPortYield();
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Critical section management.
+ */
 
 extern void vPortEnterCritical( void );
 extern void vPortExitCritical( void );
-extern uint32_t ulPortSetInterruptMask( void );
-extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
-extern void vPortInstallFreeRTOSVectorTable( void );
-
-/* The I bit within the CPSR. */
-#define portINTERRUPT_ENABLE_BIT    ( 1 << 7 )
+extern void vPortEnableInterrupts( void );
+extern void vPortDisableInterrupts( void );
+extern uint32_t ulPortSetInterruptMaskFromISR( void );
 
 /* In the absence of a priority mask register, these functions and macros
  * globally enable and disable interrupts. */
-#define portENTER_CRITICAL()       vPortEnterCritical();
-#define portEXIT_CRITICAL()        vPortExitCritical();
-#define portENABLE_INTERRUPTS()    __asm volatile ( "CPSIE i   \n" ::: "memory" );
-#define portDISABLE_INTERRUPTS()    \
-    __asm volatile ( "CPSID i   \n" \
-                     "DSB       \n" \
-                     "ISB         " ::: "memory" );
-
-__attribute__( ( always_inline ) ) static __inline uint32_t portINLINE_SET_INTERRUPT_MASK_FROM_ISR( void )
-{
-    volatile uint32_t ulCPSR;
-
-    __asm volatile ( "MRS %0, CPSR" : "=r" ( ulCPSR )::"memory" );
-
-    ulCPSR &= portINTERRUPT_ENABLE_BIT;
-    portDISABLE_INTERRUPTS();
-    return ulCPSR;
-}
-
-#define portSET_INTERRUPT_MASK_FROM_ISR()         portINLINE_SET_INTERRUPT_MASK_FROM_ISR()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    do { if( x == 0 ) portENABLE_INTERRUPTS( ); } while( 0 )
+#define portENTER_CRITICAL()                    vPortEnterCritical();
+#define portEXIT_CRITICAL()                     vPortExitCritical();
+#define portENABLE_INTERRUPTS()                 vPortEnableInterrupts();
+#define portDISABLE_INTERRUPTS()                vPortDisableInterrupts();
+#define portSET_INTERRUPT_MASK_FROM_ISR()       ulPortSetInterruptMaskFromISR();
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )  do { if( x == 0 ) portENABLE_INTERRUPTS(); } while( 0 )
 
 /*-----------------------------------------------------------*/
 
@@ -148,9 +132,27 @@ __attribute__( ( always_inline ) ) static __inline uint32_t portINLINE_SET_INTER
  * handler for whichever peripheral is used to generate the RTOS tick. */
 void FreeRTOS_Tick_Handler( void );
 
-/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
- * before any floating point instructions are executed. */
-void vPortTaskUsesFPU( void );
+/**
+ * @brief Returns the number of leading zeros in a 32 bit variable.
+ *
+ * @param[in] ulBitmap 32-Bit number to count leading zeros in.
+ *
+ * @return The number of leading zeros in ulBitmap.
+ */
+UBaseType_t ulPortCountLeadingZeros( UBaseType_t ulBitmap );
+
+/* If configUSE_TASK_FPU_SUPPORT is set to 1 (or left undefined) then tasks are
+ * created without an FPU context and must call vPortTaskUsesFPU() to give
+ * themselves an FPU context before using any FPU instructions.  If
+ * configUSE_TASK_FPU_SUPPORT is set to 2 then all tasks will have an FPU
+ * context by default. */
+#if ( configUSE_TASK_FPU_SUPPORT != 2 )
+    void vPortTaskUsesFPU( void );
+#else
+    /* Each task has an FPU context already, so define this function as a
+     * no-op. */
+    #define vPortTaskUsesFPU()
+#endif
 #define portTASK_USES_FLOATING_POINT()    vPortTaskUsesFPU()
 
 #define portLOWEST_INTERRUPT_PRIORITY           ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
@@ -163,19 +165,15 @@ void vPortTaskUsesFPU( void );
 
 #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
 
-/* Store/clear the ready priorities in a bit map. */
+    /* Store, clear and get the ready priorities in a bit map. */
     #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
     #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-
-/*-----------------------------------------------------------*/
-
-    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ( uint32_t ) __builtin_clz( uxReadyPriorities ) )
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )  uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxTopReadyPriority ) ) )
 
 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 
 #define portNOP()               __asm volatile ( "NOP" )
-#define portINLINE    __inline
-
+#define portINLINE              __inline
 #define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
 
 /* *INDENT-OFF* */

From d844312131a35dfb205ebfda82a55d4d84d4ee1f Mon Sep 17 00:00:00 2001
From: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Date: Fri, 26 Jul 2024 10:42:33 +0530
Subject: [PATCH 300/424] Fix POSIX port to respect configUSE_TIME_SLICING
 (#1103)

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 portable/ThirdParty/GCC/Posix/port.c | 29 ++++++----------------------
 1 file changed, 6 insertions(+), 23 deletions(-)

diff --git a/portable/ThirdParty/GCC/Posix/port.c b/portable/ThirdParty/GCC/Posix/port.c
index 0b18da4df..94e80cc4d 100644
--- a/portable/ThirdParty/GCC/Posix/port.c
+++ b/portable/ThirdParty/GCC/Posix/port.c
@@ -264,7 +264,7 @@ BaseType_t xPortStartScheduler( void )
     #else /* Linux PTHREAD library*/
         hSigSetupThread = PTHREAD_ONCE_INIT;
     #endif /* __APPLE__*/
-    
+
     /* Restore original signal mask. */
     ( void ) pthread_sigmask( SIG_SETMASK, &xSchedulerOriginalSignalMask, NULL );
 
@@ -382,7 +382,7 @@ static uint64_t prvGetTimeNs( void )
 static void * prvTimerTickHandler( void * arg )
 {
     ( void ) arg;
-    
+
     prvPortSetCurrentThreadName("Scheduler timer");
 
     while( xTimerTickThreadShouldRun )
@@ -420,36 +420,19 @@ static void vPortSystemTickHandler( int sig )
 
     ( void ) sig;
 
-/* uint64_t xExpectedTicks; */
-
     uxCriticalNesting++; /* Signals are blocked in this signal handler. */
 
-    #if ( configUSE_PREEMPTION == 1 )
-        pxThreadToSuspend = prvGetThreadFromTask( xTaskGetCurrentTaskHandle() );
-    #endif
+    pxThreadToSuspend = prvGetThreadFromTask( xTaskGetCurrentTaskHandle() );
 
-    /* Tick Increment, accounting for any lost signals or drift in
-     * the timer. */
-
-/*
- *      Comment code to adjust timing according to full demo requirements
- *      xExpectedTicks = (prvGetTimeNs() - prvStartTimeNs)
- *        / (portTICK_RATE_MICROSECONDS * 1000);
- * do { */
-    xTaskIncrementTick();
-
-/*        prvTickCount++;
- *    } while (prvTickCount < xExpectedTicks);
- */
-
-    #if ( configUSE_PREEMPTION == 1 )
+    if( xTaskIncrementTick() != pdFALSE )
+    {
         /* Select Next Task. */
         vTaskSwitchContext();
 
         pxThreadToResume = prvGetThreadFromTask( xTaskGetCurrentTaskHandle() );
 
         prvSwitchThread( pxThreadToResume, pxThreadToSuspend );
-    #endif
+    }
 
     uxCriticalNesting--;
 }

From fffed5e8096b1f56e97ac7ab27392a7920e6d431 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Bj=C3=B6rn=20Sch=C3=A4pers?= <github@hazardy.de>
Date: Fri, 26 Jul 2024 08:48:35 +0200
Subject: [PATCH 301/424] Define vApplicationGetTimerTaskMemory only when
 configUSE_TIMERS is set (#1104)

Otherwise it is very reasonable that config_TIMER_TASK_STACK_DEPTH is
undefined.
---
 tasks.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/tasks.c b/tasks.c
index 7a65e7ba5..b5ab5ad59 100644
--- a/tasks.c
+++ b/tasks.c
@@ -8617,7 +8617,7 @@ static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait,
 #endif /* #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configKERNEL_PROVIDED_STATIC_MEMORY == 1 ) && ( portUSING_MPU_WRAPPERS == 0 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configKERNEL_PROVIDED_STATIC_MEMORY == 1 ) && ( portUSING_MPU_WRAPPERS == 0 ) )
+#if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configKERNEL_PROVIDED_STATIC_MEMORY == 1 ) && ( portUSING_MPU_WRAPPERS == 0 ) && ( configUSE_TIMERS == 1 ) )
 
 /*
  * This is the kernel provided implementation of vApplicationGetTimerTaskMemory()
@@ -8638,7 +8638,7 @@ static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait,
         *puxTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH;
     }
 
-#endif /* #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configKERNEL_PROVIDED_STATIC_MEMORY == 1 ) && ( portUSING_MPU_WRAPPERS == 0 ) ) */
+#endif /* #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configKERNEL_PROVIDED_STATIC_MEMORY == 1 ) && ( portUSING_MPU_WRAPPERS == 0 ) && ( configUSE_TIMERS == 1 ) ) */
 /*-----------------------------------------------------------*/
 
 /*

From 3d935e86d9d67af25a0abbb7b83435e73d0b9797 Mon Sep 17 00:00:00 2001
From: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Date: Mon, 5 Aug 2024 16:00:47 +0530
Subject: [PATCH 302/424] Update broken links in readme and comments (#1110)

Update broken links in readme and comments
---
 README.md                                    |  6 ++---
 examples/cmake_example/main.c                |  2 +-
 include/queue.h                              |  4 +--
 list.c                                       |  2 +-
 portable/ARMv8M/non_secure/port.c            |  4 +--
 portable/CCS/ARM_CM3/port.c                  |  2 +-
 portable/CCS/ARM_CM4F/port.c                 |  2 +-
 portable/GCC/ARM_CM0/port.c                  |  2 +-
 portable/GCC/ARM_CM23/non_secure/port.c      |  4 +--
 portable/GCC/ARM_CM23_NTZ/non_secure/port.c  |  4 +--
 portable/GCC/ARM_CM3/port.c                  |  4 +--
 portable/GCC/ARM_CM33/non_secure/port.c      |  4 +--
 portable/GCC/ARM_CM33_NTZ/non_secure/port.c  |  4 +--
 portable/GCC/ARM_CM35P/non_secure/port.c     |  4 +--
 portable/GCC/ARM_CM35P_NTZ/non_secure/port.c |  4 +--
 portable/GCC/ARM_CM3_MPU/port.c              |  4 +--
 portable/GCC/ARM_CM4F/port.c                 |  4 +--
 portable/GCC/ARM_CM4_MPU/port.c              |  4 +--
 portable/GCC/ARM_CM55/non_secure/port.c      |  4 +--
 portable/GCC/ARM_CM55_NTZ/non_secure/port.c  |  4 +--
 portable/GCC/ARM_CM7/r0p1/port.c             |  4 +--
 portable/GCC/ARM_CM85/non_secure/port.c      |  4 +--
 portable/GCC/ARM_CM85_NTZ/non_secure/port.c  |  4 +--
 portable/IAR/ARM_CA9/port.c                  |  2 +-
 portable/IAR/ARM_CM0/port.c                  |  2 +-
 portable/IAR/ARM_CM23/non_secure/port.c      |  4 +--
 portable/IAR/ARM_CM23_NTZ/non_secure/port.c  |  4 +--
 portable/IAR/ARM_CM3/port.c                  |  4 +--
 portable/IAR/ARM_CM33/non_secure/port.c      |  4 +--
 portable/IAR/ARM_CM33_NTZ/non_secure/port.c  |  4 +--
 portable/IAR/ARM_CM35P/non_secure/port.c     |  4 +--
 portable/IAR/ARM_CM35P_NTZ/non_secure/port.c |  4 +--
 portable/IAR/ARM_CM4F/port.c                 |  4 +--
 portable/IAR/ARM_CM4F_MPU/port.c             |  4 +--
 portable/IAR/ARM_CM55/non_secure/port.c      |  4 +--
 portable/IAR/ARM_CM55_NTZ/non_secure/port.c  |  4 +--
 portable/IAR/ARM_CM7/r0p1/port.c             |  4 +--
 portable/IAR/ARM_CM85/non_secure/port.c      |  4 +--
 portable/IAR/ARM_CM85_NTZ/non_secure/port.c  |  4 +--
 portable/MikroC/ARM_CM4F/port.c              |  2 +-
 portable/RVDS/ARM_CA9/port.c                 |  2 +-
 portable/RVDS/ARM_CM3/port.c                 |  2 +-
 portable/RVDS/ARM_CM4F/port.c                |  2 +-
 portable/RVDS/ARM_CM4_MPU/port.c             |  4 +--
 portable/RVDS/ARM_CM7/r0p1/port.c            |  2 +-
 tasks.c                                      | 27 +++++++++++++++++---
 46 files changed, 103 insertions(+), 82 deletions(-)

diff --git a/README.md b/README.md
index b574bad55..a6d383add 100644
--- a/README.md
+++ b/README.md
@@ -14,12 +14,12 @@ application projects.  That way you will have the correct FreeRTOS source files
 included, and the correct include paths configured. Once a demo application is
 building and executing you can remove the demo application files, and start to
 add in your own application source files.  See the
-[FreeRTOS Kernel Quick Start Guide](https://www.FreeRTOS.org/FreeRTOS-quick-start-guide.html)
+[FreeRTOS Kernel Quick Start Guide](https://www.freertos.org/Documentation/01-FreeRTOS-quick-start/01-Beginners-guide/02-Quick-start-guide)
 for detailed instructions and other useful links.
 
 Additionally, for FreeRTOS kernel feature information refer to the
-[Developer Documentation](https://www.FreeRTOS.org/features.html),
-and [API Reference](https://www.FreeRTOS.org/a00106.html).
+[Developer Documentation](https://www.freertos.org/Documentation/02-Kernel/02-Kernel-features/00-Developer-docs),
+and [API Reference](https://www.freertos.org/Documentation/02-Kernel/04-API-references/01-Task-creation/00-TaskHandle).
 
 Also for contributing and creating a Pull Request please refer to
 [the instructions here](.github/CONTRIBUTING.md#contributing-via-pull-request).
diff --git a/examples/cmake_example/main.c b/examples/cmake_example/main.c
index b7ced4dd9..96a2abfe1 100644
--- a/examples/cmake_example/main.c
+++ b/examples/cmake_example/main.c
@@ -30,7 +30,7 @@
  * This is a simple main that will start the FreeRTOS-Kernel and run a periodic task
  * that only delays if compiled with the template port, this project will do nothing.
  * For more information on getting started please look here:
- * https://freertos.org/FreeRTOS-quick-start-guide.html
+ * https://www.freertos.org/Documentation/01-FreeRTOS-quick-start/01-Beginners-guide/02-Quick-start-guide
  */
 
 /* FreeRTOS includes. */
diff --git a/include/queue.h b/include/queue.h
index 62d095a8e..80345b9f0 100644
--- a/include/queue.h
+++ b/include/queue.h
@@ -1645,7 +1645,7 @@ BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex ) PRIVILEGED_FUNCTION;
  * or semaphores contained in the set is in a state where a queue read or
  * semaphore take operation would be successful.
  *
- * Note 1:  See the documentation on https://www.FreeRTOS.org/RTOS-queue-sets.html
+ * Note 1:  See the documentation on https://www.freertos.org/Documentation/02-Kernel/04-API-references/07-Queue-sets/00-RTOS-queue-sets
  * for reasons why queue sets are very rarely needed in practice as there are
  * simpler methods of blocking on multiple objects.
  *
@@ -1742,7 +1742,7 @@ BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex ) PRIVILEGED_FUNCTION;
  * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
  * function.
  *
- * Note 1:  See the documentation on https://www.FreeRTOS.org/RTOS-queue-sets.html
+ * Note 1:  See the documentation on https://www.freertos.org/Documentation/02-Kernel/04-API-references/07-Queue-sets/00-RTOS-queue-sets
  * for reasons why queue sets are very rarely needed in practice as there are
  * simpler methods of blocking on multiple objects.
  *
diff --git a/list.c b/list.c
index eb9efbd2d..0c0f3676e 100644
--- a/list.c
+++ b/list.c
@@ -166,7 +166,7 @@ void vListInsert( List_t * const pxList,
     {
         /* *** NOTE ***********************************************************
         *  If you find your application is crashing here then likely causes are
-        *  listed below.  In addition see https://www.FreeRTOS.org/FAQHelp.html for
+        *  listed below.  In addition see https://www.freertos.org/Why-FreeRTOS/FAQs for
         *  more tips, and ensure configASSERT() is defined!
         *  https://www.FreeRTOS.org/a00110.html#configASSERT
         *
diff --git a/portable/ARMv8M/non_secure/port.c b/portable/ARMv8M/non_secure/port.c
index c9b596d12..75e9ea9dd 100644
--- a/portable/ARMv8M/non_secure/port.c
+++ b/portable/ARMv8M/non_secure/port.c
@@ -1650,7 +1650,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          *
          * Assertion failures here indicate incorrect installation of the
          * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
-         * https://www.FreeRTOS.org/FAQHelp.html.
+         * https://www.freertos.org/Why-FreeRTOS/FAQs.
          *
          * Systems with a configurable address for the interrupt vector table
          * can also encounter assertion failures or even system faults here if
@@ -2041,7 +2041,7 @@ BaseType_t xPortIsInsideInterrupt( void )
              *
              * The following links provide detailed information:
              * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
-             * https://www.FreeRTOS.org/FAQHelp.html */
+             * https://www.freertos.org/Why-FreeRTOS/FAQs */
             configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
         }
 
diff --git a/portable/CCS/ARM_CM3/port.c b/portable/CCS/ARM_CM3/port.c
index 5ed26c2d2..8373c14c0 100644
--- a/portable/CCS/ARM_CM3/port.c
+++ b/portable/CCS/ARM_CM3/port.c
@@ -669,7 +669,7 @@ void vPortSetupTimerInterrupt( void )
              *
              * The following links provide detailed information:
              * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
-             * https://www.FreeRTOS.org/FAQHelp.html */
+             * https://www.freertos.org/Why-FreeRTOS/FAQs */
             configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
         }
 
diff --git a/portable/CCS/ARM_CM4F/port.c b/portable/CCS/ARM_CM4F/port.c
index 1ac7a59e6..1ad05077d 100644
--- a/portable/CCS/ARM_CM4F/port.c
+++ b/portable/CCS/ARM_CM4F/port.c
@@ -694,7 +694,7 @@ void vPortSetupTimerInterrupt( void )
              *
              * The following links provide detailed information:
              * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
-             * https://www.FreeRTOS.org/FAQHelp.html */
+             * https://www.freertos.org/Why-FreeRTOS/FAQs */
             configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
         }
 
diff --git a/portable/GCC/ARM_CM0/port.c b/portable/GCC/ARM_CM0/port.c
index 608afa5de..c3053c543 100644
--- a/portable/GCC/ARM_CM0/port.c
+++ b/portable/GCC/ARM_CM0/port.c
@@ -1288,7 +1288,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          *
          * Assertion failures here indicate incorrect installation of the
          * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
-         * https://www.FreeRTOS.org/FAQHelp.html.
+         * https://www.freertos.org/Why-FreeRTOS/FAQs.
          *
          * Systems with a configurable address for the interrupt vector table
          * can also encounter assertion failures or even system faults here if
diff --git a/portable/GCC/ARM_CM23/non_secure/port.c b/portable/GCC/ARM_CM23/non_secure/port.c
index c9b596d12..75e9ea9dd 100644
--- a/portable/GCC/ARM_CM23/non_secure/port.c
+++ b/portable/GCC/ARM_CM23/non_secure/port.c
@@ -1650,7 +1650,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          *
          * Assertion failures here indicate incorrect installation of the
          * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
-         * https://www.FreeRTOS.org/FAQHelp.html.
+         * https://www.freertos.org/Why-FreeRTOS/FAQs.
          *
          * Systems with a configurable address for the interrupt vector table
          * can also encounter assertion failures or even system faults here if
@@ -2041,7 +2041,7 @@ BaseType_t xPortIsInsideInterrupt( void )
              *
              * The following links provide detailed information:
              * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
-             * https://www.FreeRTOS.org/FAQHelp.html */
+             * https://www.freertos.org/Why-FreeRTOS/FAQs */
             configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
         }
 
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
index c9b596d12..75e9ea9dd 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
@@ -1650,7 +1650,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          *
          * Assertion failures here indicate incorrect installation of the
          * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
-         * https://www.FreeRTOS.org/FAQHelp.html.
+         * https://www.freertos.org/Why-FreeRTOS/FAQs.
          *
          * Systems with a configurable address for the interrupt vector table
          * can also encounter assertion failures or even system faults here if
@@ -2041,7 +2041,7 @@ BaseType_t xPortIsInsideInterrupt( void )
              *
              * The following links provide detailed information:
              * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
-             * https://www.FreeRTOS.org/FAQHelp.html */
+             * https://www.freertos.org/Why-FreeRTOS/FAQs */
             configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
         }
 
diff --git a/portable/GCC/ARM_CM3/port.c b/portable/GCC/ARM_CM3/port.c
index 5adf39bd7..ba7a718ab 100644
--- a/portable/GCC/ARM_CM3/port.c
+++ b/portable/GCC/ARM_CM3/port.c
@@ -292,7 +292,7 @@ BaseType_t xPortStartScheduler( void )
          *
          * Assertion failures here indicate incorrect installation of the
          * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
-         * https://www.FreeRTOS.org/FAQHelp.html.
+         * https://www.freertos.org/Why-FreeRTOS/FAQs.
          *
          * Systems with a configurable address for the interrupt vector table
          * can also encounter assertion failures or even system faults here if
@@ -801,7 +801,7 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
              *
              * The following links provide detailed information:
              * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
-             * https://www.FreeRTOS.org/FAQHelp.html */
+             * https://www.freertos.org/Why-FreeRTOS/FAQs */
             configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
         }
 
diff --git a/portable/GCC/ARM_CM33/non_secure/port.c b/portable/GCC/ARM_CM33/non_secure/port.c
index c9b596d12..75e9ea9dd 100644
--- a/portable/GCC/ARM_CM33/non_secure/port.c
+++ b/portable/GCC/ARM_CM33/non_secure/port.c
@@ -1650,7 +1650,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          *
          * Assertion failures here indicate incorrect installation of the
          * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
-         * https://www.FreeRTOS.org/FAQHelp.html.
+         * https://www.freertos.org/Why-FreeRTOS/FAQs.
          *
          * Systems with a configurable address for the interrupt vector table
          * can also encounter assertion failures or even system faults here if
@@ -2041,7 +2041,7 @@ BaseType_t xPortIsInsideInterrupt( void )
              *
              * The following links provide detailed information:
              * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
-             * https://www.FreeRTOS.org/FAQHelp.html */
+             * https://www.freertos.org/Why-FreeRTOS/FAQs */
             configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
         }
 
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
index c9b596d12..75e9ea9dd 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
@@ -1650,7 +1650,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          *
          * Assertion failures here indicate incorrect installation of the
          * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
-         * https://www.FreeRTOS.org/FAQHelp.html.
+         * https://www.freertos.org/Why-FreeRTOS/FAQs.
          *
          * Systems with a configurable address for the interrupt vector table
          * can also encounter assertion failures or even system faults here if
@@ -2041,7 +2041,7 @@ BaseType_t xPortIsInsideInterrupt( void )
              *
              * The following links provide detailed information:
              * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
-             * https://www.FreeRTOS.org/FAQHelp.html */
+             * https://www.freertos.org/Why-FreeRTOS/FAQs */
             configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
         }
 
diff --git a/portable/GCC/ARM_CM35P/non_secure/port.c b/portable/GCC/ARM_CM35P/non_secure/port.c
index c9b596d12..75e9ea9dd 100644
--- a/portable/GCC/ARM_CM35P/non_secure/port.c
+++ b/portable/GCC/ARM_CM35P/non_secure/port.c
@@ -1650,7 +1650,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          *
          * Assertion failures here indicate incorrect installation of the
          * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
-         * https://www.FreeRTOS.org/FAQHelp.html.
+         * https://www.freertos.org/Why-FreeRTOS/FAQs.
          *
          * Systems with a configurable address for the interrupt vector table
          * can also encounter assertion failures or even system faults here if
@@ -2041,7 +2041,7 @@ BaseType_t xPortIsInsideInterrupt( void )
              *
              * The following links provide detailed information:
              * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
-             * https://www.FreeRTOS.org/FAQHelp.html */
+             * https://www.freertos.org/Why-FreeRTOS/FAQs */
             configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
         }
 
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c b/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
index c9b596d12..75e9ea9dd 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
@@ -1650,7 +1650,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          *
          * Assertion failures here indicate incorrect installation of the
          * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
-         * https://www.FreeRTOS.org/FAQHelp.html.
+         * https://www.freertos.org/Why-FreeRTOS/FAQs.
          *
          * Systems with a configurable address for the interrupt vector table
          * can also encounter assertion failures or even system faults here if
@@ -2041,7 +2041,7 @@ BaseType_t xPortIsInsideInterrupt( void )
              *
              * The following links provide detailed information:
              * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
-             * https://www.FreeRTOS.org/FAQHelp.html */
+             * https://www.freertos.org/Why-FreeRTOS/FAQs */
             configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
         }
 
diff --git a/portable/GCC/ARM_CM3_MPU/port.c b/portable/GCC/ARM_CM3_MPU/port.c
index 6a36f1a88..bbe00b61f 100644
--- a/portable/GCC/ARM_CM3_MPU/port.c
+++ b/portable/GCC/ARM_CM3_MPU/port.c
@@ -767,7 +767,7 @@ BaseType_t xPortStartScheduler( void )
          *
          * Assertion failures here indicate incorrect installation of the
          * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
-         * https://www.FreeRTOS.org/FAQHelp.html.
+         * https://www.freertos.org/Why-FreeRTOS/FAQs.
          *
          * Systems with a configurable address for the interrupt vector table
          * can also encounter assertion failures or even system faults here if
@@ -1462,7 +1462,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
              *
              * The following links provide detailed information:
              * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
-             * https://www.FreeRTOS.org/FAQHelp.html */
+             * https://www.freertos.org/Why-FreeRTOS/FAQs */
             configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
         }
 
diff --git a/portable/GCC/ARM_CM4F/port.c b/portable/GCC/ARM_CM4F/port.c
index 532bbce88..c4194f767 100644
--- a/portable/GCC/ARM_CM4F/port.c
+++ b/portable/GCC/ARM_CM4F/port.c
@@ -335,7 +335,7 @@ BaseType_t xPortStartScheduler( void )
          *
          * Assertion failures here indicate incorrect installation of the
          * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
-         * https://www.FreeRTOS.org/FAQHelp.html.
+         * https://www.freertos.org/Why-FreeRTOS/FAQs.
          *
          * Systems with a configurable address for the interrupt vector table
          * can also encounter assertion failures or even system faults here if
@@ -886,7 +886,7 @@ static void vPortEnableVFP( void )
              *
              * The following links provide detailed information:
              * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
-             * https://www.FreeRTOS.org/FAQHelp.html */
+             * https://www.freertos.org/Why-FreeRTOS/FAQs */
             configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
         }
 
diff --git a/portable/GCC/ARM_CM4_MPU/port.c b/portable/GCC/ARM_CM4_MPU/port.c
index 68b2ab13f..30a65c423 100644
--- a/portable/GCC/ARM_CM4_MPU/port.c
+++ b/portable/GCC/ARM_CM4_MPU/port.c
@@ -853,7 +853,7 @@ BaseType_t xPortStartScheduler( void )
          *
          * Assertion failures here indicate incorrect installation of the
          * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
-         * https://www.FreeRTOS.org/FAQHelp.html.
+         * https://www.freertos.org/Why-FreeRTOS/FAQs.
          *
          * Systems with a configurable address for the interrupt vector table
          * can also encounter assertion failures or even system faults here if
@@ -1605,7 +1605,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
              *
              * The following links provide detailed information:
              * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
-             * https://www.FreeRTOS.org/FAQHelp.html */
+             * https://www.freertos.org/Why-FreeRTOS/FAQs */
             configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
         }
 
diff --git a/portable/GCC/ARM_CM55/non_secure/port.c b/portable/GCC/ARM_CM55/non_secure/port.c
index c9b596d12..75e9ea9dd 100644
--- a/portable/GCC/ARM_CM55/non_secure/port.c
+++ b/portable/GCC/ARM_CM55/non_secure/port.c
@@ -1650,7 +1650,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          *
          * Assertion failures here indicate incorrect installation of the
          * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
-         * https://www.FreeRTOS.org/FAQHelp.html.
+         * https://www.freertos.org/Why-FreeRTOS/FAQs.
          *
          * Systems with a configurable address for the interrupt vector table
          * can also encounter assertion failures or even system faults here if
@@ -2041,7 +2041,7 @@ BaseType_t xPortIsInsideInterrupt( void )
              *
              * The following links provide detailed information:
              * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
-             * https://www.FreeRTOS.org/FAQHelp.html */
+             * https://www.freertos.org/Why-FreeRTOS/FAQs */
             configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
         }
 
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/port.c b/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
index c9b596d12..75e9ea9dd 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
@@ -1650,7 +1650,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          *
          * Assertion failures here indicate incorrect installation of the
          * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
-         * https://www.FreeRTOS.org/FAQHelp.html.
+         * https://www.freertos.org/Why-FreeRTOS/FAQs.
          *
          * Systems with a configurable address for the interrupt vector table
          * can also encounter assertion failures or even system faults here if
@@ -2041,7 +2041,7 @@ BaseType_t xPortIsInsideInterrupt( void )
              *
              * The following links provide detailed information:
              * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
-             * https://www.FreeRTOS.org/FAQHelp.html */
+             * https://www.freertos.org/Why-FreeRTOS/FAQs */
             configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
         }
 
diff --git a/portable/GCC/ARM_CM7/r0p1/port.c b/portable/GCC/ARM_CM7/r0p1/port.c
index ac067274d..766f0242d 100644
--- a/portable/GCC/ARM_CM7/r0p1/port.c
+++ b/portable/GCC/ARM_CM7/r0p1/port.c
@@ -323,7 +323,7 @@ BaseType_t xPortStartScheduler( void )
          *
          * Assertion failures here indicate incorrect installation of the
          * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
-         * https://www.FreeRTOS.org/FAQHelp.html.
+         * https://www.freertos.org/Why-FreeRTOS/FAQs.
          *
          * Systems with a configurable address for the interrupt vector table
          * can also encounter assertion failures or even system faults here if
@@ -876,7 +876,7 @@ static void vPortEnableVFP( void )
              *
              * The following links provide detailed information:
              * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
-             * https://www.FreeRTOS.org/FAQHelp.html */
+             * https://www.freertos.org/Why-FreeRTOS/FAQs */
             configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
         }
 
diff --git a/portable/GCC/ARM_CM85/non_secure/port.c b/portable/GCC/ARM_CM85/non_secure/port.c
index c9b596d12..75e9ea9dd 100644
--- a/portable/GCC/ARM_CM85/non_secure/port.c
+++ b/portable/GCC/ARM_CM85/non_secure/port.c
@@ -1650,7 +1650,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          *
          * Assertion failures here indicate incorrect installation of the
          * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
-         * https://www.FreeRTOS.org/FAQHelp.html.
+         * https://www.freertos.org/Why-FreeRTOS/FAQs.
          *
          * Systems with a configurable address for the interrupt vector table
          * can also encounter assertion failures or even system faults here if
@@ -2041,7 +2041,7 @@ BaseType_t xPortIsInsideInterrupt( void )
              *
              * The following links provide detailed information:
              * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
-             * https://www.FreeRTOS.org/FAQHelp.html */
+             * https://www.freertos.org/Why-FreeRTOS/FAQs */
             configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
         }
 
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/port.c b/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
index c9b596d12..75e9ea9dd 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
@@ -1650,7 +1650,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          *
          * Assertion failures here indicate incorrect installation of the
          * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
-         * https://www.FreeRTOS.org/FAQHelp.html.
+         * https://www.freertos.org/Why-FreeRTOS/FAQs.
          *
          * Systems with a configurable address for the interrupt vector table
          * can also encounter assertion failures or even system faults here if
@@ -2041,7 +2041,7 @@ BaseType_t xPortIsInsideInterrupt( void )
              *
              * The following links provide detailed information:
              * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
-             * https://www.FreeRTOS.org/FAQHelp.html */
+             * https://www.freertos.org/Why-FreeRTOS/FAQs */
             configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
         }
 
diff --git a/portable/IAR/ARM_CA9/port.c b/portable/IAR/ARM_CA9/port.c
index b558099af..f26ae3790 100644
--- a/portable/IAR/ARM_CA9/port.c
+++ b/portable/IAR/ARM_CA9/port.c
@@ -427,7 +427,7 @@ uint32_t ulPortSetInterruptMask( void )
          *
          * The following links provide detailed information:
          * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
-         * https://www.FreeRTOS.org/FAQHelp.html */
+         * https://www.freertos.org/Why-FreeRTOS/FAQs */
         configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
 
         /* Priority grouping:  The interrupt controller (GIC) allows the bits
diff --git a/portable/IAR/ARM_CM0/port.c b/portable/IAR/ARM_CM0/port.c
index 809b6c417..6f5ec0ad5 100644
--- a/portable/IAR/ARM_CM0/port.c
+++ b/portable/IAR/ARM_CM0/port.c
@@ -205,7 +205,7 @@ BaseType_t xPortStartScheduler( void )
          *
          * Assertion failures here indicate incorrect installation of the
          * FreeRTOS handler. For help installing the FreeRTOS handler, see
-         * https://www.FreeRTOS.org/FAQHelp.html.
+         * https://www.freertos.org/Why-FreeRTOS/FAQs.
          *
          * Systems with a configurable address for the interrupt vector table
          * can also encounter assertion failures or even system faults here if
diff --git a/portable/IAR/ARM_CM23/non_secure/port.c b/portable/IAR/ARM_CM23/non_secure/port.c
index c9b596d12..75e9ea9dd 100644
--- a/portable/IAR/ARM_CM23/non_secure/port.c
+++ b/portable/IAR/ARM_CM23/non_secure/port.c
@@ -1650,7 +1650,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          *
          * Assertion failures here indicate incorrect installation of the
          * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
-         * https://www.FreeRTOS.org/FAQHelp.html.
+         * https://www.freertos.org/Why-FreeRTOS/FAQs.
          *
          * Systems with a configurable address for the interrupt vector table
          * can also encounter assertion failures or even system faults here if
@@ -2041,7 +2041,7 @@ BaseType_t xPortIsInsideInterrupt( void )
              *
              * The following links provide detailed information:
              * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
-             * https://www.FreeRTOS.org/FAQHelp.html */
+             * https://www.freertos.org/Why-FreeRTOS/FAQs */
             configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
         }
 
diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
index c9b596d12..75e9ea9dd 100644
--- a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
@@ -1650,7 +1650,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          *
          * Assertion failures here indicate incorrect installation of the
          * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
-         * https://www.FreeRTOS.org/FAQHelp.html.
+         * https://www.freertos.org/Why-FreeRTOS/FAQs.
          *
          * Systems with a configurable address for the interrupt vector table
          * can also encounter assertion failures or even system faults here if
@@ -2041,7 +2041,7 @@ BaseType_t xPortIsInsideInterrupt( void )
              *
              * The following links provide detailed information:
              * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
-             * https://www.FreeRTOS.org/FAQHelp.html */
+             * https://www.freertos.org/Why-FreeRTOS/FAQs */
             configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
         }
 
diff --git a/portable/IAR/ARM_CM3/port.c b/portable/IAR/ARM_CM3/port.c
index 5d0d5aab5..ef590cf95 100644
--- a/portable/IAR/ARM_CM3/port.c
+++ b/portable/IAR/ARM_CM3/port.c
@@ -246,7 +246,7 @@ BaseType_t xPortStartScheduler( void )
          *
          * Assertion failures here indicate incorrect installation of the
          * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
-         * https://www.FreeRTOS.org/FAQHelp.html.
+         * https://www.freertos.org/Why-FreeRTOS/FAQs.
          *
          * Systems with a configurable address for the interrupt vector table
          * can also encounter assertion failures or even system faults here if
@@ -709,7 +709,7 @@ __weak void vPortSetupTimerInterrupt( void )
              *
              * The following links provide detailed information:
              * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
-             * https://www.FreeRTOS.org/FAQHelp.html */
+             * https://www.freertos.org/Why-FreeRTOS/FAQs */
             configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
         }
 
diff --git a/portable/IAR/ARM_CM33/non_secure/port.c b/portable/IAR/ARM_CM33/non_secure/port.c
index c9b596d12..75e9ea9dd 100644
--- a/portable/IAR/ARM_CM33/non_secure/port.c
+++ b/portable/IAR/ARM_CM33/non_secure/port.c
@@ -1650,7 +1650,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          *
          * Assertion failures here indicate incorrect installation of the
          * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
-         * https://www.FreeRTOS.org/FAQHelp.html.
+         * https://www.freertos.org/Why-FreeRTOS/FAQs.
          *
          * Systems with a configurable address for the interrupt vector table
          * can also encounter assertion failures or even system faults here if
@@ -2041,7 +2041,7 @@ BaseType_t xPortIsInsideInterrupt( void )
              *
              * The following links provide detailed information:
              * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
-             * https://www.FreeRTOS.org/FAQHelp.html */
+             * https://www.freertos.org/Why-FreeRTOS/FAQs */
             configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
         }
 
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
index c9b596d12..75e9ea9dd 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
@@ -1650,7 +1650,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          *
          * Assertion failures here indicate incorrect installation of the
          * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
-         * https://www.FreeRTOS.org/FAQHelp.html.
+         * https://www.freertos.org/Why-FreeRTOS/FAQs.
          *
          * Systems with a configurable address for the interrupt vector table
          * can also encounter assertion failures or even system faults here if
@@ -2041,7 +2041,7 @@ BaseType_t xPortIsInsideInterrupt( void )
              *
              * The following links provide detailed information:
              * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
-             * https://www.FreeRTOS.org/FAQHelp.html */
+             * https://www.freertos.org/Why-FreeRTOS/FAQs */
             configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
         }
 
diff --git a/portable/IAR/ARM_CM35P/non_secure/port.c b/portable/IAR/ARM_CM35P/non_secure/port.c
index c9b596d12..75e9ea9dd 100644
--- a/portable/IAR/ARM_CM35P/non_secure/port.c
+++ b/portable/IAR/ARM_CM35P/non_secure/port.c
@@ -1650,7 +1650,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          *
          * Assertion failures here indicate incorrect installation of the
          * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
-         * https://www.FreeRTOS.org/FAQHelp.html.
+         * https://www.freertos.org/Why-FreeRTOS/FAQs.
          *
          * Systems with a configurable address for the interrupt vector table
          * can also encounter assertion failures or even system faults here if
@@ -2041,7 +2041,7 @@ BaseType_t xPortIsInsideInterrupt( void )
              *
              * The following links provide detailed information:
              * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
-             * https://www.FreeRTOS.org/FAQHelp.html */
+             * https://www.freertos.org/Why-FreeRTOS/FAQs */
             configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
         }
 
diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c b/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
index c9b596d12..75e9ea9dd 100644
--- a/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
@@ -1650,7 +1650,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          *
          * Assertion failures here indicate incorrect installation of the
          * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
-         * https://www.FreeRTOS.org/FAQHelp.html.
+         * https://www.freertos.org/Why-FreeRTOS/FAQs.
          *
          * Systems with a configurable address for the interrupt vector table
          * can also encounter assertion failures or even system faults here if
@@ -2041,7 +2041,7 @@ BaseType_t xPortIsInsideInterrupt( void )
              *
              * The following links provide detailed information:
              * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
-             * https://www.FreeRTOS.org/FAQHelp.html */
+             * https://www.freertos.org/Why-FreeRTOS/FAQs */
             configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
         }
 
diff --git a/portable/IAR/ARM_CM4F/port.c b/portable/IAR/ARM_CM4F/port.c
index a4e2193b2..b96329a05 100644
--- a/portable/IAR/ARM_CM4F/port.c
+++ b/portable/IAR/ARM_CM4F/port.c
@@ -284,7 +284,7 @@ BaseType_t xPortStartScheduler( void )
          *
          * Assertion failures here indicate incorrect installation of the
          * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
-         * https://www.FreeRTOS.org/FAQHelp.html.
+         * https://www.freertos.org/Why-FreeRTOS/FAQs.
          *
          * Systems with a configurable address for the interrupt vector table
          * can also encounter assertion failures or even system faults here if
@@ -753,7 +753,7 @@ __weak void vPortSetupTimerInterrupt( void )
              *
              * The following links provide detailed information:
              * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
-             * https://www.FreeRTOS.org/FAQHelp.html */
+             * https://www.freertos.org/Why-FreeRTOS/FAQs */
             configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
         }
 
diff --git a/portable/IAR/ARM_CM4F_MPU/port.c b/portable/IAR/ARM_CM4F_MPU/port.c
index da070c56a..66092df01 100644
--- a/portable/IAR/ARM_CM4F_MPU/port.c
+++ b/portable/IAR/ARM_CM4F_MPU/port.c
@@ -748,7 +748,7 @@ BaseType_t xPortStartScheduler( void )
          *
          * Assertion failures here indicate incorrect installation of the
          * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
-         * https://www.FreeRTOS.org/FAQHelp.html.
+         * https://www.freertos.org/Why-FreeRTOS/FAQs.
          *
          * Systems with a configurable address for the interrupt vector table
          * can also encounter assertion failures or even system faults here if
@@ -1336,7 +1336,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
              *
              * The following links provide detailed information:
              * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
-             * https://www.FreeRTOS.org/FAQHelp.html */
+             * https://www.freertos.org/Why-FreeRTOS/FAQs */
             configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
         }
 
diff --git a/portable/IAR/ARM_CM55/non_secure/port.c b/portable/IAR/ARM_CM55/non_secure/port.c
index c9b596d12..75e9ea9dd 100644
--- a/portable/IAR/ARM_CM55/non_secure/port.c
+++ b/portable/IAR/ARM_CM55/non_secure/port.c
@@ -1650,7 +1650,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          *
          * Assertion failures here indicate incorrect installation of the
          * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
-         * https://www.FreeRTOS.org/FAQHelp.html.
+         * https://www.freertos.org/Why-FreeRTOS/FAQs.
          *
          * Systems with a configurable address for the interrupt vector table
          * can also encounter assertion failures or even system faults here if
@@ -2041,7 +2041,7 @@ BaseType_t xPortIsInsideInterrupt( void )
              *
              * The following links provide detailed information:
              * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
-             * https://www.FreeRTOS.org/FAQHelp.html */
+             * https://www.freertos.org/Why-FreeRTOS/FAQs */
             configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
         }
 
diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/port.c b/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
index c9b596d12..75e9ea9dd 100644
--- a/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
@@ -1650,7 +1650,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          *
          * Assertion failures here indicate incorrect installation of the
          * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
-         * https://www.FreeRTOS.org/FAQHelp.html.
+         * https://www.freertos.org/Why-FreeRTOS/FAQs.
          *
          * Systems with a configurable address for the interrupt vector table
          * can also encounter assertion failures or even system faults here if
@@ -2041,7 +2041,7 @@ BaseType_t xPortIsInsideInterrupt( void )
              *
              * The following links provide detailed information:
              * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
-             * https://www.FreeRTOS.org/FAQHelp.html */
+             * https://www.freertos.org/Why-FreeRTOS/FAQs */
             configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
         }
 
diff --git a/portable/IAR/ARM_CM7/r0p1/port.c b/portable/IAR/ARM_CM7/r0p1/port.c
index 35a5b0b1b..723389633 100644
--- a/portable/IAR/ARM_CM7/r0p1/port.c
+++ b/portable/IAR/ARM_CM7/r0p1/port.c
@@ -272,7 +272,7 @@ BaseType_t xPortStartScheduler( void )
          *
          * Assertion failures here indicate incorrect installation of the
          * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
-         * https://www.FreeRTOS.org/FAQHelp.html.
+         * https://www.freertos.org/Why-FreeRTOS/FAQs.
          *
          * Systems with a configurable address for the interrupt vector table
          * can also encounter assertion failures or even system faults here if
@@ -741,7 +741,7 @@ __weak void vPortSetupTimerInterrupt( void )
              *
              * The following links provide detailed information:
              * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
-             * https://www.FreeRTOS.org/FAQHelp.html */
+             * https://www.freertos.org/Why-FreeRTOS/FAQs */
             configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
         }
 
diff --git a/portable/IAR/ARM_CM85/non_secure/port.c b/portable/IAR/ARM_CM85/non_secure/port.c
index c9b596d12..75e9ea9dd 100644
--- a/portable/IAR/ARM_CM85/non_secure/port.c
+++ b/portable/IAR/ARM_CM85/non_secure/port.c
@@ -1650,7 +1650,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          *
          * Assertion failures here indicate incorrect installation of the
          * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
-         * https://www.FreeRTOS.org/FAQHelp.html.
+         * https://www.freertos.org/Why-FreeRTOS/FAQs.
          *
          * Systems with a configurable address for the interrupt vector table
          * can also encounter assertion failures or even system faults here if
@@ -2041,7 +2041,7 @@ BaseType_t xPortIsInsideInterrupt( void )
              *
              * The following links provide detailed information:
              * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
-             * https://www.FreeRTOS.org/FAQHelp.html */
+             * https://www.freertos.org/Why-FreeRTOS/FAQs */
             configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
         }
 
diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/port.c b/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
index c9b596d12..75e9ea9dd 100644
--- a/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
@@ -1650,7 +1650,7 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          *
          * Assertion failures here indicate incorrect installation of the
          * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
-         * https://www.FreeRTOS.org/FAQHelp.html.
+         * https://www.freertos.org/Why-FreeRTOS/FAQs.
          *
          * Systems with a configurable address for the interrupt vector table
          * can also encounter assertion failures or even system faults here if
@@ -2041,7 +2041,7 @@ BaseType_t xPortIsInsideInterrupt( void )
              *
              * The following links provide detailed information:
              * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
-             * https://www.FreeRTOS.org/FAQHelp.html */
+             * https://www.freertos.org/Why-FreeRTOS/FAQs */
             configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
         }
 
diff --git a/portable/MikroC/ARM_CM4F/port.c b/portable/MikroC/ARM_CM4F/port.c
index dd5f35361..a167f8588 100644
--- a/portable/MikroC/ARM_CM4F/port.c
+++ b/portable/MikroC/ARM_CM4F/port.c
@@ -892,7 +892,7 @@ BaseType_t xPortIsInsideInterrupt( void )
              *
              * The following links provide detailed information:
              * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
-             * https://www.FreeRTOS.org/FAQHelp.html */
+             * https://www.freertos.org/Why-FreeRTOS/FAQs */
             configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
         }
 
diff --git a/portable/RVDS/ARM_CA9/port.c b/portable/RVDS/ARM_CA9/port.c
index 88979f42a..c89232644 100644
--- a/portable/RVDS/ARM_CA9/port.c
+++ b/portable/RVDS/ARM_CA9/port.c
@@ -465,7 +465,7 @@ uint32_t ulPortSetInterruptMask( void )
          *
          * The following links provide detailed information:
          * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
-         * https://www.FreeRTOS.org/FAQHelp.html */
+         * https://www.freertos.org/Why-FreeRTOS/FAQs */
         configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
 
         /* Priority grouping:  The interrupt controller (GIC) allows the bits
diff --git a/portable/RVDS/ARM_CM3/port.c b/portable/RVDS/ARM_CM3/port.c
index b75f00f29..725127193 100644
--- a/portable/RVDS/ARM_CM3/port.c
+++ b/portable/RVDS/ARM_CM3/port.c
@@ -770,7 +770,7 @@ __asm uint32_t vPortGetIPSR( void )
              *
              * The following links provide detailed information:
              * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
-             * https://www.FreeRTOS.org/FAQHelp.html */
+             * https://www.freertos.org/Why-FreeRTOS/FAQs */
             configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
         }
 
diff --git a/portable/RVDS/ARM_CM4F/port.c b/portable/RVDS/ARM_CM4F/port.c
index dfbbf4e4d..8d21daffb 100644
--- a/portable/RVDS/ARM_CM4F/port.c
+++ b/portable/RVDS/ARM_CM4F/port.c
@@ -866,7 +866,7 @@ __asm uint32_t vPortGetIPSR( void )
              *
              * The following links provide detailed information:
              * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
-             * https://www.FreeRTOS.org/FAQHelp.html */
+             * https://www.freertos.org/Why-FreeRTOS/FAQs */
             configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
         }
 
diff --git a/portable/RVDS/ARM_CM4_MPU/port.c b/portable/RVDS/ARM_CM4_MPU/port.c
index 87af70e3d..307ae6d02 100644
--- a/portable/RVDS/ARM_CM4_MPU/port.c
+++ b/portable/RVDS/ARM_CM4_MPU/port.c
@@ -852,7 +852,7 @@ BaseType_t xPortStartScheduler( void )
          *
          * Assertion failures here indicate incorrect installation of the
          * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
-         * https://www.FreeRTOS.org/FAQHelp.html.
+         * https://www.freertos.org/Why-FreeRTOS/FAQs.
          *
          * Systems with a configurable address for the interrupt vector table
          * can also encounter assertion failures or even system faults here if
@@ -1602,7 +1602,7 @@ __asm uint32_t prvPortGetIPSR( void )
              *
              * The following links provide detailed information:
              * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
-             * https://www.FreeRTOS.org/FAQHelp.html */
+             * https://www.freertos.org/Why-FreeRTOS/FAQs */
             configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
         }
 
diff --git a/portable/RVDS/ARM_CM7/r0p1/port.c b/portable/RVDS/ARM_CM7/r0p1/port.c
index 464ac2e81..33fa80266 100644
--- a/portable/RVDS/ARM_CM7/r0p1/port.c
+++ b/portable/RVDS/ARM_CM7/r0p1/port.c
@@ -852,7 +852,7 @@ __asm uint32_t vPortGetIPSR( void )
              *
              * The following links provide detailed information:
              * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
-             * https://www.FreeRTOS.org/FAQHelp.html */
+             * https://www.freertos.org/Why-FreeRTOS/FAQs */
             configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
         }
 
diff --git a/tasks.c b/tasks.c
index b5ab5ad59..d76bc33e5 100644
--- a/tasks.c
+++ b/tasks.c
@@ -3819,9 +3819,30 @@ void vTaskSuspendAll( void )
     #if ( configNUMBER_OF_CORES == 1 )
     {
         /* A critical section is not required as the variable is of type
-         * BaseType_t.  Please read Richard Barry's reply in the following link to a
-         * post in the FreeRTOS support forum before reporting this as a bug! -
-         * https://goo.gl/wu4acr */
+         * BaseType_t. Each task maintains its own context, and a context switch
+         * cannot occur if the variable is non zero. So, as long as the writing
+         * from the register back into the memory is atomic, it is not a
+         * problem.
+         *
+         * Consider the following scenario, which starts with
+         * uxSchedulerSuspended at zero.
+         *
+         * 1. load uxSchedulerSuspended into register.
+         * 2. Now a context switch causes another task to run, and the other
+         *    task uses the same variable. The other task will see the variable
+         *    as zero because the variable has not yet been updated by the
+         *    original task. Eventually the original task runs again. **That can
+         *    only happen when uxSchedulerSuspended is once again zero**. When
+         *    the original task runs again, the contents of the CPU registers
+         *    are restored to exactly how they were when it was switched out -
+         *    therefore the value it read into the register still matches the
+         *    value of the uxSchedulerSuspended variable.
+         *
+         * 3. increment register.
+         * 4. store register into uxSchedulerSuspended. The value restored to
+         *    uxSchedulerSuspended will be the correct value of 1, even though
+         *    the variable was used by other tasks in the mean time.
+         */
 
         /* portSOFTWARE_BARRIER() is only implemented for emulated/simulated ports that
          * do not otherwise exhibit real time behaviour. */

From d750173b76b605b0a3e93683afb3f7cf51d80e2a Mon Sep 17 00:00:00 2001
From: Daniel Otte <39625575+d-otte@users.noreply.github.com>
Date: Mon, 5 Aug 2024 12:41:33 +0200
Subject: [PATCH 303/424] Only check for stream buffer dependencies, if
 configUSE_STREAM_BUFFERS==1. (#1109)

Signed-off-by: Daniel Otte <d.otte@wut.de>
---
 stream_buffer.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/stream_buffer.c b/stream_buffer.c
index aeca81a4a..b1f9c0d57 100644
--- a/stream_buffer.c
+++ b/stream_buffer.c
@@ -39,14 +39,6 @@
 #include "task.h"
 #include "stream_buffer.h"
 
-#if ( configUSE_TASK_NOTIFICATIONS != 1 )
-    #error configUSE_TASK_NOTIFICATIONS must be set to 1 to build stream_buffer.c
-#endif
-
-#if ( INCLUDE_xTaskGetCurrentTaskHandle != 1 )
-    #error INCLUDE_xTaskGetCurrentTaskHandle must be set to 1 to build stream_buffer.c
-#endif
-
 /* The MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
  * for the header files above, but not in this file, in order to generate the
  * correct privileged Vs unprivileged linkage and placement. */
@@ -58,6 +50,14 @@
  * configUSE_STREAM_BUFFERS is set to 1 in FreeRTOSConfig.h. */
 #if ( configUSE_STREAM_BUFFERS == 1 )
 
+    #if ( configUSE_TASK_NOTIFICATIONS != 1 )
+        #error configUSE_TASK_NOTIFICATIONS must be set to 1 to build stream_buffer.c
+    #endif
+
+    #if ( INCLUDE_xTaskGetCurrentTaskHandle != 1 )
+        #error INCLUDE_xTaskGetCurrentTaskHandle must be set to 1 to build stream_buffer.c
+    #endif
+
 /* If the user has not provided application specific Rx notification macros,
  * or #defined the notification macros away, then provide default implementations
  * that uses task notifications. */

From 53c7e7c46f20dbd941d3f17116725d8fda9e6b90 Mon Sep 17 00:00:00 2001
From: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Date: Tue, 6 Aug 2024 10:49:48 +0530
Subject: [PATCH 304/424] Reset xNextTaskUnblockTime in task notify FromISR
 APIs (#1111)

* Reset xNextTaskUnblockTime in task notify FromISR APIs

If a task is blocked waiting for a notification then
xNextTaskUnblockTime might be set to the blocked task's timeout time. If
the task is unblocked for a reason other than a timeout
xNextTaskUnblockTime is normally left unchanged, because it will
automatically get reset to a new value when the tick count equals
xNextTaskUnblockTime. However if tickless idle is used it is important
to enter sleep mode at the earliest possible time - so reset
xNextTaskUnblockTime here to ensure it is updated at the earliest
possible time.

This was reported here -
https://forums.freertos.org/t/the-vtaskgenericnotifygivefromisr-function-need-call-prvresetnexttaskunblocktime/21090

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 tasks.c | 32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/tasks.c b/tasks.c
index d76bc33e5..3382954b8 100644
--- a/tasks.c
+++ b/tasks.c
@@ -8080,6 +8080,22 @@ TickType_t uxTaskResetEventItemValue( void )
                 {
                     listREMOVE_ITEM( &( pxTCB->xStateListItem ) );
                     prvAddTaskToReadyList( pxTCB );
+
+                    #if ( configUSE_TICKLESS_IDLE != 0 )
+                    {
+                        /* If a task is blocked waiting for a notification then
+                         * xNextTaskUnblockTime might be set to the blocked task's time
+                         * out time.  If the task is unblocked for a reason other than
+                         * a timeout xNextTaskUnblockTime is normally left unchanged,
+                         * because it will automatically get reset to a new value when
+                         * the tick count equals xNextTaskUnblockTime.  However if
+                         * tickless idling is used it might be more important to enter
+                         * sleep mode at the earliest possible time - so reset
+                         * xNextTaskUnblockTime here to ensure it is updated at the
+                         * earliest possible time. */
+                        prvResetNextTaskUnblockTime();
+                    }
+                    #endif
                 }
                 else
                 {
@@ -8198,6 +8214,22 @@ TickType_t uxTaskResetEventItemValue( void )
                 {
                     listREMOVE_ITEM( &( pxTCB->xStateListItem ) );
                     prvAddTaskToReadyList( pxTCB );
+
+                    #if ( configUSE_TICKLESS_IDLE != 0 )
+                    {
+                        /* If a task is blocked waiting for a notification then
+                         * xNextTaskUnblockTime might be set to the blocked task's time
+                         * out time.  If the task is unblocked for a reason other than
+                         * a timeout xNextTaskUnblockTime is normally left unchanged,
+                         * because it will automatically get reset to a new value when
+                         * the tick count equals xNextTaskUnblockTime.  However if
+                         * tickless idling is used it might be more important to enter
+                         * sleep mode at the earliest possible time - so reset
+                         * xNextTaskUnblockTime here to ensure it is updated at the
+                         * earliest possible time. */
+                        prvResetNextTaskUnblockTime();
+                    }
+                    #endif
                 }
                 else
                 {

From c963d2400159acc2d06ff8c066a2b8c1738b3a35 Mon Sep 17 00:00:00 2001
From: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Date: Thu, 8 Aug 2024 21:07:11 +0530
Subject: [PATCH 305/424] Add support for vApplicationFPUSafeIRQHandler (#1113)

This PR adds support for vApplicationFPUSafeIRQHandler. The application
writer needs to name their IRQ handler as:
1. vApplicationIRQHandler if the IRQ handler does not use FPU registers.
2. vApplicationFPUSafeIRQHandler is the IRQ handler uses FPU registers.

When the application uses vApplicationFPUSafeIRQHandler, a default
implementation of vApplicationIRQHandler is used which stores FPU
registers and then calls vApplicationFPUSafeIRQHandler.
---
 portable/GCC/ARM_CRx_No_GIC/portASM.S | 45 +++++++++++++++++++++++++++
 1 file changed, 45 insertions(+)

diff --git a/portable/GCC/ARM_CRx_No_GIC/portASM.S b/portable/GCC/ARM_CRx_No_GIC/portASM.S
index 9945fc2d9..de9845e0f 100644
--- a/portable/GCC/ARM_CRx_No_GIC/portASM.S
+++ b/portable/GCC/ARM_CRx_No_GIC/portASM.S
@@ -39,6 +39,7 @@
     .extern pxCurrentTCB
     .extern vTaskSwitchContext
     .extern vApplicationIRQHandler
+    .extern vApplicationFPUSafeIRQHandler
     .extern ulPortInterruptNesting
     .extern ulPortTaskHasFPUContext
     .extern ulICCEOIR
@@ -237,6 +238,50 @@ vApplicationSVCHandler:
 
 /*-----------------------------------------------------------*/
 
+/* If the application provides an implementation of vApplicationIRQHandler(),
+ * then it will get called directly without saving the FPU registers on
+ * interrupt entry, and this weak implementation of vApplicationIRQHandler()
+ * will not get called.
+ *
+ * If the application provides its own implementation of
+ * vApplicationFPUSafeIRQHandler() then this implementation of
+ * vApplicationIRQHandler() will be called, save the FPU registers, and then
+ * call vApplicationFPUSafeIRQHandler().
+ *
+ * Therefore, if the application writer wants FPU registers to be saved on
+ * interrupt entry, their IRQ handler must be called
+ * vApplicationFPUSafeIRQHandler(), and if the application writer does not want
+ * FPU registers to be saved on interrupt entry their IRQ handler must be
+ * called vApplicationIRQHandler().
+ */
+.align 4
+.weak vApplicationIRQHandler
+.type vApplicationIRQHandler, %function
+vApplicationIRQHandler:
+    PUSH    {LR}
+
+    VMRS    R1, FPSCR
+    VPUSH   {D0-D7}
+    PUSH    {R1}
+
+    BLX     vApplicationFPUSafeIRQHandler
+
+    POP     {R0}
+    VPOP    {D0-D7}
+    VMSR    FPSCR, R0
+
+    POP     {PC}
+
+/*-----------------------------------------------------------*/
+
+.align 4
+.weak vApplicationFPUSafeIRQHandler
+.type vApplicationFPUSafeIRQHandler, %function
+vApplicationFPUSafeIRQHandler:
+    B       vApplicationFPUSafeIRQHandler
+
+/*-----------------------------------------------------------*/
+
 /*
  * UBaseType_t ulPortCountLeadingZeros( UBaseType_t ulBitmap );
  *

From da3c35aa4832b94774b3f6890e5a2b4627bfc8f8 Mon Sep 17 00:00:00 2001
From: Trong Nguyen <147012384+TrongNguyenR@users.noreply.github.com>
Date: Fri, 9 Aug 2024 12:51:21 +0700
Subject: [PATCH 306/424] Add CC-RH port for Renesas F1Kx devices (#1100)

Add CC-RH port for Renesas F1Kx devices
---
 .github/.cSpellWords.txt       |  18 +-
 portable/CCRH/F1Kx/README.md   |  46 +++
 portable/CCRH/F1Kx/port.c      | 734 +++++++++++++++++++++++++++++++++
 portable/CCRH/F1Kx/portasm.s   | 325 +++++++++++++++
 portable/CCRH/F1Kx/portmacro.h | 193 +++++++++
 5 files changed, 1315 insertions(+), 1 deletion(-)
 create mode 100644 portable/CCRH/F1Kx/README.md
 create mode 100644 portable/CCRH/F1Kx/port.c
 create mode 100644 portable/CCRH/F1Kx/portasm.s
 create mode 100644 portable/CCRH/F1Kx/portmacro.h

diff --git a/.github/.cSpellWords.txt b/.github/.cSpellWords.txt
index 0ba0be7c5..42f9196d7 100644
--- a/.github/.cSpellWords.txt
+++ b/.github/.cSpellWords.txt
@@ -75,6 +75,7 @@ CCNT
 CCNTR
 CCPN
 CCPR
+CCRH
 CDTY
 CDTYR
 CFBS
@@ -86,6 +87,7 @@ CHSR
 CICR
 CISR
 CKDIV
+CKDIVMD
 CKEY
 CKGR
 CKLO
@@ -125,6 +127,7 @@ CODR
 comms
 COMPA
 CONFG
+coreid
 coremqtt
 CORTUS
 coverity
@@ -149,6 +152,7 @@ CPRE
 cpsid
 cpsie
 CPSR
+CPUCLK
 CPUID
 CRCB
 crflash
@@ -164,6 +168,8 @@ csrs
 csrw
 CTCR
 ctest
+CTPC
+CTPSW
 CTRLA
 CTSIC
 CUPD
@@ -227,6 +233,7 @@ DTREN
 DTXD
 DUNITY
 DVAR
+Dxxx
 EABI
 ecall
 ECIT
@@ -237,6 +244,7 @@ EEVT
 eevtedg
 EEVTEDG
 EFRHD
+EIIC
 EINT
 EIPC
 EIPSW
@@ -310,6 +318,7 @@ FNTR
 FOSC
 FPCCR
 FPCSR
+FPEPC
 FPSW
 FPUL
 FRDY
@@ -338,6 +347,7 @@ GPTA
 HCLK
 Hitach
 HRESP
+HTCFG
 HWHSH
 HWORD
 HWRD
@@ -353,6 +363,7 @@ ICCR
 ICCRPR
 ICCRX
 ICERST
+ICIPI
 ICSR
 IDCR
 IECR
@@ -372,6 +383,7 @@ INTTM
 IODEFINE
 IORLW
 IPEN
+IPIR
 IPLB
 ipsr
 IPSR
@@ -380,8 +392,8 @@ IRET
 IRXFCS
 ISRAM
 ISRR
-ISR's
 ISRS
+ISR's
 ISRTICK
 isystem
 ITIF
@@ -564,6 +576,7 @@ OSCEN
 OSCOFF
 OSCOUNT
 OSMC
+OSTM
 outpw
 OVLY
 OVRE
@@ -584,6 +597,7 @@ PCLKSEL
 PCSR
 PCXI
 PDSR
+PEID
 PEIE
 PENDSV
 PENDSVCLEAR
@@ -799,6 +813,8 @@ SWINTR
 SWRST
 SWTRG
 synchronise
+SYNCM
+syncm
 SYSC
 sysclk
 Sysclk
diff --git a/portable/CCRH/F1Kx/README.md b/portable/CCRH/F1Kx/README.md
new file mode 100644
index 000000000..7583c67af
--- /dev/null
+++ b/portable/CCRH/F1Kx/README.md
@@ -0,0 +1,46 @@
+# RH850/F1K and F1Kx FreeRTOS Port with CC-RH Compiler
+
+## Introduction
+
+This repository contains the port of FreeRTOS for Renesas RH850/F1K and F1Kx microcontrollers using the CC-RH compiler. The following sections provide instructions on how to use this port, a link to the test project, and other relevant information.
+
+## Prerequisites
+- Compiler: CC-RH
+- FreeRTOS version 11.1.0
+
+| Device   | FPU | SMP |
+|----------|-----|-----|
+| F1K      | Yes | No  |
+| F1KM-S1  | Yes | No  |
+| F1KM-S2  | Yes | No  |
+| F1KM-S4  | Yes | No  |
+| F1KH-D8  | Yes | Yes |
+
+## Link to Test Project
+
+The test project can be found [here](https://github.com/FreeRTOS/FreeRTOS-Community-Supported-Demos) (`RH850_F1Kx_CCRH`). This project contains example tasks and configurations to help you get started with FreeRTOS on the RH850/F1K and F1Kx.
+
+## Note
+   1. Configure IPIR Interrupt: Ensure that the bit specifying the destination for binding (requesting) an interrupt is enabled (e.g: IBDxxx register of F1KH-D8) (1)
+   2. `Channel 0` and address `0xFFFEEC00` are used as default configuration for configIPIR_CHANNEL and configEXCLUSIVE_ADDRESS, in case of resource confliction other channel/address can be used. (2)
+   3. The minimal stack size (configMINIMAL_STACK_SIZE) must be included the reserved memory for nested interrupt. This formula can be referred: `(task_context_size) * (1 + configMAX_INT_NESTING) + Stack_depth_of_taskcode`
+   In which, `task_context_size` is calculated as `36*4bytes = 144bytes` (when FPU enabled) or `34*4bytes = 136` (when FPU disabled), configMAX_INT_NESTING is 02 as default.
+   4. `configTIMER_PRESCALE`: This value is required in order to correctly configure clock for `CPUCLK_L`. Refer to Hardware Manual at `Table 44.22` for `option byte`: If the user sets the option byte `CKDIVMD to 1`, then `configTIMER_PRESCALE = 4`. Otherwise, if `CKDIVMD is set to 0`, then `configTIMER_PRESCALE = 2`.
+
+(1)  This is applicable for F1KH-D8 with SMP only.
+
+(2) This is optional and applicable for SMP only.
+
+## Other Relevant Information
+
+- **Documentation:**
+  - Refer to the official [FreeRTOS documentation](https://www.freertos.org/Documentation/RTOS_book.html) for detailed information on configuring and using FreeRTOS.
+  - Consult the [RH850 F1K group user manual hardware manual](https://www.renesas.com/us/en/document/mah/rh850f1k-group-users-manual-hardware?r=1170166) for specific details about the microcontroller.
+  - For more information about Renesas RH850/F1K and F1Kx, please visit [this website](https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rh850-automotive-mcus)
+  - The CC-RH compiler can be downloaded [here](https://www.renesas.com/us/en/software-tool/c-compiler-package-rh850-family#downloads)
+
+- **Support:**
+  - If you encounter any issues or have questions about this port, please open an issue in this repository or contact the maintainer.
+
+- **Contributing:**
+  - Contributions to improve this port are welcome. Please fork the repository, make your changes, and submit a pull request.
\ No newline at end of file
diff --git a/portable/CCRH/F1Kx/port.c b/portable/CCRH/F1Kx/port.c
new file mode 100644
index 000000000..e3d71929d
--- /dev/null
+++ b/portable/CCRH/F1Kx/port.c
@@ -0,0 +1,734 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* This port uses xTaskGetCurrentTaskHandle to get TCB stack, it is required to
+ * enable this API. */
+#if ( ( INCLUDE_xTaskGetCurrentTaskHandle != 1 ) && ( configNUMBER_OF_CORES == 1 ) )
+    #error INCLUDE_xTaskGetCurrentTaskHandle must be set to 1 in single core.
+#endif
+
+/***********************************************************
+* Macro definitions
+***********************************************************/
+
+/* Hardware specific macros */
+#define portPSW_REGISTER_ID          ( 5 )
+#define portFPSR_REGISTER_ID         ( 6 )
+
+/* PSW.EBV and PSW.CUx bits are kept as current status */
+#define portINITIAL_PSW_MASK         ( 0x000f8000 )
+#define portCURRENT_PSW_VALUE        ( portSTSR( portPSW_REGISTER_ID ) )
+#define portCURRENT_SR_ZERO_VALUE    ( ( StackType_t ) 0x00000000 )
+#define portCURRENT_FPSR_VALUE       ( portSTSR( portFPSR_REGISTER_ID ) )
+
+/* Mask for FPU configuration bits (FN, PEM, RM, FS) */
+#define portINITIAL_FPSR_MASK        ( 0x00ae0000 )
+#define portPSW_ID_MASK              ( 0x00000020 )
+
+/* Define necessary hardware IO for OSTM timer. OSTM0 is used by default as
+ * it is common for almost device variants. If it conflicts with application,
+ * the application shall implement another timer.*/
+#define portOSTM_EIC_ADDR            ( 0xFFFFB0A8 )
+#define portOSTM0CMP_ADDR            ( 0xFFD70000 )
+#define portOSTM0CTL_ADDR            ( 0xFFD70020 )
+#define portOSTM0TS_ADDR             ( 0xFFD70014 )
+
+#if ( configNUMBER_OF_CORES > 1 )
+
+/* IPIR  base address, the peripheral is used for Inter-Processor communication
+ * Hardware supports 4 channels which is offset by 0x0, 0x4, 0x8, 0xC bytes from
+ * base address. By default, channel 0 is selected. */
+    #ifdef configIPIR_CHANNEL
+        #define portIPIR_BASE_ADDR    ( ( 0xFFFEEC80 ) + ( configIPIR_CHANNEL << 2 ) )
+    #else
+        #define portIPIR_BASE_ADDR    ( 0xFFFEEC80 )
+    #endif
+
+/*  Address used for exclusive control for variable shared between PEs
+ * (common resources), each CPU cores have independent access path to
+ * this address. By default, G0MEV0 register is selected*/
+    #ifdef configEXCLUSIVE_ADDRESS
+        #define portMEV_BASE_ADDR    configEXCLUSIVE_ADDRESS
+    #else
+        #define portMEV_BASE_ADDR    ( 0xFFFEEC00 )
+    #endif
+#endif /* if ( configNUMBER_OF_CORES > 1 ) */
+
+/* Macros required to set up the initial stack. */
+#define portSTACK_INITIAL_VALUE_R1     ( ( StackType_t ) 0x01010101 )
+#define portSTACK_INITIAL_VALUE_R2     ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x02 )
+#define portSTACK_INITIAL_VALUE_R3     ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x03 )
+#define portSTACK_INITIAL_VALUE_R4     ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x04 )
+#define portSTACK_INITIAL_VALUE_R5     ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x05 )
+#define portSTACK_INITIAL_VALUE_R6     ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x06 )
+#define portSTACK_INITIAL_VALUE_R7     ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x07 )
+#define portSTACK_INITIAL_VALUE_R8     ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x08 )
+#define portSTACK_INITIAL_VALUE_R9     ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x09 )
+#define portSTACK_INITIAL_VALUE_R10    ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x10 )
+#define portSTACK_INITIAL_VALUE_R11    ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x11 )
+#define portSTACK_INITIAL_VALUE_R12    ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x12 )
+#define portSTACK_INITIAL_VALUE_R13    ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x13 )
+#define portSTACK_INITIAL_VALUE_R14    ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x14 )
+#define portSTACK_INITIAL_VALUE_R15    ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x15 )
+#define portSTACK_INITIAL_VALUE_R16    ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x16 )
+#define portSTACK_INITIAL_VALUE_R17    ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x17 )
+#define portSTACK_INITIAL_VALUE_R18    ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x18 )
+#define portSTACK_INITIAL_VALUE_R19    ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x19 )
+#define portSTACK_INITIAL_VALUE_R20    ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x20 )
+#define portSTACK_INITIAL_VALUE_R21    ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x21 )
+#define portSTACK_INITIAL_VALUE_R22    ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x22 )
+#define portSTACK_INITIAL_VALUE_R23    ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x23 )
+#define portSTACK_INITIAL_VALUE_R24    ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x24 )
+#define portSTACK_INITIAL_VALUE_R25    ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x25 )
+#define portSTACK_INITIAL_VALUE_R26    ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x26 )
+#define portSTACK_INITIAL_VALUE_R27    ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x27 )
+#define portSTACK_INITIAL_VALUE_R28    ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x28 )
+#define portSTACK_INITIAL_VALUE_R29    ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x29 )
+#define portSTACK_INITIAL_VALUE_R30    ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x30 )
+
+/***********************************************************
+* Typedef definitions
+***********************************************************/
+
+/* OSTM Count Start Trigger Register (OSTMnTS) */
+#define portOSTM_COUNTER_START              ( 0x01U ) /* Starts the counter */
+
+/* OSTM Count Stop Trigger Register (OSTMnTT) */
+#define portOSTM_COUNTER_STOP               ( 0x01U ) /* Stops the counter */
+
+/* OSTM Control Register (OSTMnCTL) */
+#define portOSTM_MODE_INTERVAL_TIMER        ( 0x00U )
+#define portOSTM_MODE_FREE_RUNNING          ( 0x02U )
+
+/* Disables or Enable the interrupts when counting starts */
+#define portOSTM_START_INTERRUPT_DISABLE    ( 0x00U )
+#define portOSTM_START_INTERRUPT_ENABLE     ( 0x01U )
+
+/* Interrupt vector method select (TBxxx) */
+#define portINT_DIRECT_VECTOR               ( 0x0U )
+#define portINT_TABLE_VECTOR                ( 0x1U )
+
+/* Interrupt mask (MKxxx) */
+#define portINT_PROCESSING_ENABLED          ( 0x0U )
+#define portINT_PROCESSING_DISABLED         ( 0x1U )
+
+/* Specify 16 interrupt priority levels */
+#define portINT_PRIORITY_HIGHEST            ( 0x0000U ) /* Level 0 (highest) */
+#define portINT_PRIORITY_LEVEL1             ( 0x0001U ) /* Level 1 */
+#define portINT_PRIORITY_LEVEL2             ( 0x0002U ) /* Level 2 */
+#define portINT_PRIORITY_LEVEL3             ( 0x0003U ) /* Level 3 */
+#define portINT_PRIORITY_LEVEL4             ( 0x0004U ) /* Level 4 */
+#define portINT_PRIORITY_LEVEL5             ( 0x0005U ) /* Level 5 */
+#define portINT_PRIORITY_LEVEL6             ( 0x0006U ) /* Level 6 */
+#define portINT_PRIORITY_LEVEL7             ( 0x0007U ) /* Level 7 */
+#define portINT_PRIORITY_LEVEL8             ( 0x0008U ) /* Level 8 */
+#define portINT_PRIORITY_LEVEL9             ( 0x0009U ) /* Level 9 */
+#define portINT_PRIORITY_LEVEL10            ( 0x000AU ) /* Level 10 */
+#define portINT_PRIORITY_LEVEL11            ( 0x000BU ) /* Level 11 */
+#define portINT_PRIORITY_LEVEL12            ( 0x000CU ) /* Level 12 */
+#define portINT_PRIORITY_LEVEL13            ( 0x000DU ) /* Level 13 */
+#define portINT_PRIORITY_LEVEL14            ( 0x000EU ) /* Level 14 */
+#define portINT_PRIORITY_LOWEST             ( 0x000FU ) /* Level 15 (lowest) */
+
+/* Macros indicating status of scheduler request */
+#define PORT_SCHEDULER_NOREQUEST            0UL
+#define PORT_SCHEDULER_TASKSWITCH           1UL       /* Do not modify */
+#define PORT_SCHEDULER_STARTFIRSTTASK       2UL       /* Do not modify */
+
+#ifndef configSETUP_TICK_INTERRUPT
+
+/* The user has not provided their own tick interrupt configuration so use
+ * the definition in this file (which uses the interval timer). */
+    #define configSETUP_TICK_INTERRUPT()    prvSetupTimerInterrupt()
+#endif /* configSETUP_TICK_INTERRUPT */
+
+#ifndef configMAX_INT_NESTING
+
+/* Set the default value for depth of nested interrupt. In theory, the
+ * microcontroller have mechanism to limit number of nested level of interrupt
+ * by priority (maximum 16 levels). However, the large stack memory should be
+ * prepared for each task to save resource in interrupt handler. Therefore, it
+ * is necessary to limit depth of nesting interrupt to optimize memory usage.
+ * In addition, the execution time of interrupt handler should be very short
+ * (typically not exceed 20us), this constraint does not impact to system.
+ */
+    #define configMAX_INT_NESTING    2UL
+#endif
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*
+ * Sets up the periodic ISR used for the RTOS tick using the OSTM.
+ * The application writer can define configSETUP_TICK_INTERRUPT() (in
+ * FreeRTOSConfig.h) such that their own tick interrupt configuration is used
+ * in place of prvSetupTimerInterrupt().
+ */
+static void prvSetupTimerInterrupt( void );
+
+#if ( configNUMBER_OF_CORES > 1 )
+
+/*
+ * Functions implement spin-lock between cores by atomic accesses to Exclusive
+ * Control Register (G0MEVm). There are separated access path between CPU cores,
+ * but they should wait if access to same register
+ */
+    static void prvExclusiveLock( BaseType_t xFromIsr );
+    static void prvExclusiveRelease( BaseType_t xFromIsr );
+
+#endif
+
+/*
+ * Function to start the first task executing
+ */
+extern void vPortStartFirstTask( void );
+
+/* Scheduler request on each cores which are starting first task and switching
+ * context */
+volatile BaseType_t xPortScheduleStatus[ configNUMBER_OF_CORES ] = { 0 };
+
+/* Counts the interrupt nesting depth. A context switch is only performed if
+ * the nesting depth is 0. In addition, the interrupt shares same stack
+ * allocated for each tasks. With supporting nesting interrupt, the stack
+ * may be overflowed.
+ * It is necessary to control maximum stack depth.
+ */
+volatile UBaseType_t uxInterruptNesting[ configNUMBER_OF_CORES ] = { 0 };
+volatile const UBaseType_t uxPortMaxInterruptDepth = configMAX_INT_NESTING - 1;
+
+/* Count number of nested locks by same cores. The lock is completely released
+ * only if this count is decreased to 0, the lock is separated for task
+ * and isr */
+UBaseType_t uxLockNesting[ configNUMBER_OF_CORES ][ 2 ] = { 0 };
+
+#if ( configNUMBER_OF_CORES > 1 )
+
+/* Pointer to exclusive access memory */
+    volatile BaseType_t * pxPortExclusiveReg = ( volatile BaseType_t * ) ( portMEV_BASE_ADDR );
+#endif
+
+/* Interrupt handler for OSTM timer which handling tick increment and resulting
+ * to switch context. */
+void vPortTickISR( void );
+
+#if ( configNUMBER_OF_CORES > 1 )
+
+/* Yield specific cores by send inter-processor interrupt */
+    void vPortYieldCore( uint32_t xCoreID );
+
+/*
+ * Inter-processor interrupt handler. The interrupt is triggered by
+ * portYIELD_CORE().
+ */
+    void vPortIPIHander( void );
+
+/* These functions below implement recursive spinlock for exclusive access among
+ * cores. The core will wait until lock will be available, whilst the core which
+ * already had lock can acquire lock without waiting. This function could be
+ * call from task and interrupt context, the critical section is called
+ * as in ISR */
+    void vPortRecursiveLockAcquire( BaseType_t xFromIsr );
+    void vPortRecursiveLockRelease( BaseType_t xFromIsr );
+
+#endif /* (configNUMBER_OF_CORES > 1) */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * These below functions implement interrupt mask from interrupt. They are not
+ * called in nesting, it is protected by FreeRTOS kernel.
+ */
+portLONG xPortSetInterruptMask( void )
+{
+    portLONG ulPSWValue = portSTSR( portPSW_REGISTER_ID );
+
+    portDISABLE_INTERRUPTS();
+
+    /* It returns current value of Program Status Word register */
+    return ulPSWValue;
+}
+
+/*-----------------------------------------------------------*/
+
+void vPortClearInterruptMask( portLONG uxSavedInterruptStatus )
+{
+    portLONG ulPSWValue = portSTSR( portPSW_REGISTER_ID );
+
+    /* Interrupt Disable status is indicates by bit#5 of PSW
+    * (1: Interrupt is disabled; 0: Interrupt is enabled) */
+
+    /* Revert to the status before interrupt mask. */
+    ulPSWValue &= ( ~( portPSW_ID_MASK ) );
+    ulPSWValue |= ( portPSW_ID_MASK & uxSavedInterruptStatus );
+    portLDSR( portPSW_REGISTER_ID, ulPSWValue );
+}
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Using CC-RH intrinsic function to get HTCFG0 (regID, selID) = (0,2)
+ * Core ID is indicates by bit HTCFG0.PEID located at bit 18 to 16
+ * Bit 31 to 19 are read only and always be read as 0. HTCFG0.PEID is 1 and 2
+ * corresponding to core 0 (PE1) and core 1 (PE2). It is adjusted to 0 and 1.
+ */
+BaseType_t xPortGET_CORE_ID( void )
+{
+    #if ( configNUMBER_OF_CORES > 1 )
+        return ( portSTSR_CCRH( 0, 2 ) >> 16 ) - 1;
+    #else
+
+        /* In single core, xPortGET_CORE_ID is used in this port only.
+         * The dummy core ID could be controlled inside this port. */
+        return 0;
+    #endif
+}
+
+/*-----------------------------------------------------------*/
+
+/*
+ * This port supports both multi-cores and single-core, whilst TCB stack
+ * variables are different which are respectively pxCurrentTCB (single-core)
+ * and pxCurrentTCBs[] (multiple-cores). This function is defined to obtains
+ * TCBs of current cores. Also, the C function could switch to corresponding
+ * pointer by pre-compile conditions.
+ */
+void * pvPortGetCurrentTCB( void )
+{
+    void * pvCurrentTCB = ( void * ) xTaskGetCurrentTaskHandle();
+
+    configASSERT( pvCurrentTCB != NULL );
+
+    return pvCurrentTCB;
+}
+
+/*-----------------------------------------------------------*/
+
+/*
+ * This function checks if a context switch is required and, if so, updates
+ * the scheduler status for the core on which the function is called. The
+ * scheduler status is set to indicate that a task switch should occur.
+ */
+void vPortSetSwitch( BaseType_t xSwitchRequired )
+{
+    if( xSwitchRequired != pdFALSE )
+    {
+        xPortScheduleStatus[ xPortGET_CORE_ID() ] = PORT_SCHEDULER_TASKSWITCH;
+    }
+}
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the stack of a new task so it is ready to be placed under the
+ * scheduler control. The registers have to be placed on the stack in the
+ * order that the port expects to find them.
+ *
+ * @param[in]  pxTopOfStack  Pointer to top of this task's stack
+ * @param[in]  pxCode        Task function, stored as initial PC for the task
+ * @param[in]  pvParameters  Parameters for task
+ */
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
+{
+    /* Simulate the stack frame as it would be created by
+     * a context switch interrupt. */
+    *pxTopOfStack = ( StackType_t ) prvTaskExitError;            /* R31 (LP) */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R5;  /* R5 (TP)  */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) pvParameters;                /* R6       */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R7;  /* R7       */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R8;  /* R8       */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R9;  /* R9       */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R10; /* R10      */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R11; /* R11      */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R12; /* R12      */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R13; /* R13      */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R14; /* R14      */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R15; /* R15      */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R16; /* R16      */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R17; /* R17      */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R18; /* R18      */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R19; /* R19      */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R20; /* R20      */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R21; /* R21      */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R22; /* R22      */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R23; /* R23      */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R24; /* R24      */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R25; /* R25      */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R26; /* R26      */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R27; /* R27      */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R28; /* R28      */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R29; /* R29      */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R30; /* R30 (EP) */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R1;  /* R1        */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R2;  /* R2        */
+
+    pxTopOfStack--;
+
+    /* Keep System pre-configuration (HV, CUx, EBV) as current setting in
+     * PSW register */
+    *pxTopOfStack = ( StackType_t ) ( portCURRENT_PSW_VALUE & portINITIAL_PSW_MASK ); /* EIPSW */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) pxCode;                                           /* EIPC */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) portCURRENT_SR_ZERO_VALUE;                        /* EIIC */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) ( portCURRENT_PSW_VALUE & portINITIAL_PSW_MASK ); /* CTPSW */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) portCURRENT_SR_ZERO_VALUE;                        /* CTPC */
+
+/* __FPU is defined by CCRH compiler if FPU is enabled */
+    #if ( configENABLE_FPU == 1 )
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) ( portCURRENT_FPSR_VALUE & portINITIAL_FPSR_MASK ); /* FPSR */
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) portCURRENT_SR_ZERO_VALUE;                          /* FPEPC */
+    #endif /* (configENABLE_FPU == 1) */
+
+    return pxTopOfStack;
+}
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Configures the tick frequency and starts the first task.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+    #if ( configNUMBER_OF_CORES > 1 )
+        BaseType_t xCurrentCore = xPortGET_CORE_ID();
+    #endif
+
+    /* Prevent interrupt by timer interrupt during starting first task.
+     * The interrupt shall be enabled automatically by being restored from
+     * task stack */
+    portDISABLE_INTERRUPTS();
+
+    /* Setup the tick interrupt */
+    configSETUP_TICK_INTERRUPT();
+
+    #if ( configNUMBER_OF_CORES > 1 )
+        /* Start scheduler on other cores */
+        for( uint16_t xCoreID = 0; xCoreID < configNUMBER_OF_CORES; xCoreID++ )
+        {
+            if( xCoreID != xCurrentCore )
+            {
+                /* Send yielding request to other cores with flag to start
+                 * first task. TaskContextSwitch is not executed */
+                xPortScheduleStatus[ xCoreID ] = PORT_SCHEDULER_STARTFIRSTTASK;
+                vPortYieldCore( xCoreID );
+            }
+            else
+            {
+                /* Nothing to do. The first task is started in this call by
+                 * below vPortStartFirstTask() */
+                xPortScheduleStatus[ xCoreID ] = PORT_SCHEDULER_NOREQUEST;
+            }
+        }
+    #endif /* if ( configNUMBER_OF_CORES > 1 ) */
+
+    /* Start first task in primary core */
+    vPortStartFirstTask();
+
+    /* Should never get here as the tasks will now be executing! */
+    prvTaskExitError();
+
+    /* To prevent compiler warnings in the case that the application writer
+     * overrides this functionality by defining configTASK_RETURN_ADDRESS.
+     * Call vTaskSwitchContext() so link time optimization does not remove
+     * the symbol. */
+    vTaskSwitchContext(
+        #if ( configNUMBER_OF_CORES > 1 )
+            xCurrentCore
+        #endif
+        );
+
+    return pdFALSE;
+}
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void )
+{
+    /* A function that implements a task must not exit or attempt to return to
+     * its caller as there is nothing to return to.  If a task wants to exit it
+     * should instead call vTaskDelete( NULL ).
+     *
+     * Artificially force an assert() to be triggered if configASSERT() is
+     * defined, then stop here so application writers can catch the error. */
+
+    /* This statement will always fail, triggering the assert */
+    configASSERT( pdFALSE );
+
+    /*
+     * The following statement may be unreachable because configASSERT(pdFALSE)
+     * always triggers an assertion failure, which typically halts program
+     * execution.
+     * The warning may be reported to indicate to indicate that the compiler
+     * detects the subsequent code will not be executed.
+     * The warning is acceptable to ensure program is halt regardless of
+     * configASSERT(pdFALSE) implementation
+     */
+    portDISABLE_INTERRUPTS();
+
+    for( ; ; )
+    {
+        /* Infinite loop to ensure the function does not return. */
+    }
+}
+
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+    /* Not implemented in ports where there is nothing to return to.
+     * Artificially force an assert. */
+    configASSERT( pdFALSE );
+}
+
+/*-----------------------------------------------------------*/
+
+#if ( configNUMBER_OF_CORES > 1 )
+
+    void vPortYieldCore( uint32_t xCoreID )
+    {
+        /* Check if we need to yield on a different core */
+        if( xCoreID != xPortGET_CORE_ID() )
+        {
+            volatile uint32_t * pulIPIRReg;
+
+            /* Determine the IPI register based on the target core ID */
+            pulIPIRReg = ( volatile uint32_t * ) ( portIPIR_BASE_ADDR );
+
+            /*Inter-processor interrupt generates an interrupt request by
+             * writing 1 to applicable bits of target cores. The interrupt
+             * should be enabled by application in  corresponding cores
+             * including PSW.ID (EI instruction) and interrupt control setting
+             * for ICIPIRn channel (interrupt mask, vector method)
+             */
+            *pulIPIRReg = ( 1 << xCoreID );
+        }
+        else
+        {
+            /* Yielding current core */
+            vPortYield();
+        }
+    }
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Handler for inter-processor interrupt in second cores. The interrupt is
+ * triggered by portYIELD_CORE(). vTaskSwitchContext() is invoked to
+ * switch tasks
+ */
+    void vPortIPIHander( void )
+    {
+        BaseType_t xCurrentCore = xPortGET_CORE_ID();
+
+        /* 1st execution starts 1st task, TaskSwitchContext is not executed */
+        if( PORT_SCHEDULER_STARTFIRSTTASK != xPortScheduleStatus[ xCurrentCore ] )
+        {
+            xPortScheduleStatus[ xCurrentCore ] = PORT_SCHEDULER_TASKSWITCH;
+        }
+    }
+
+/*-----------------------------------------------------------*/
+
+#endif /* (configNUMBER_OF_CORES > 1) */
+
+void vPortTickISR( void )
+{
+    /* In case of multicores with SMP,  xTaskIncrementTick is required to
+     * called in critical section to avoid conflict resource as this function
+     * could be called by xTaskResumeAll() from any cores. */
+    #if ( configNUMBER_OF_CORES > 1 )
+        BaseType_t xSavedInterruptStatus;
+
+        xSavedInterruptStatus = portENTER_CRITICAL_FROM_ISR();
+    #endif
+    {
+        /* Increment the RTOS tick. */
+        if( xTaskIncrementTick() != pdFALSE )
+        {
+            /* Pend a context switch. */
+            xPortScheduleStatus[ xPortGET_CORE_ID() ] = PORT_SCHEDULER_TASKSWITCH;
+        }
+    }
+    #if ( configNUMBER_OF_CORES > 1 )
+        portEXIT_CRITICAL_FROM_ISR( xSavedInterruptStatus );
+    #endif
+}
+
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void )
+{
+    volatile uint32_t * pulOSTMIntReg;
+
+    /* Interrupt configuration for OSTM Timer
+     * By default, the second lowest priority is set for timer interrupt to
+     * avoid blocking other interrupt. Normally, user could set the lowest
+     * priority for non-critical event. It try to keep timer on time.
+     * In addition, direct vector table is used by default.
+     */
+    pulOSTMIntReg = ( volatile uint32_t * ) portOSTM_EIC_ADDR;
+    *pulOSTMIntReg = ( portINT_PROCESSING_ENABLED | portINT_DIRECT_VECTOR | portINT_PRIORITY_LEVEL14 );
+
+    /* Set OSTM0 control setting */
+    *( ( volatile uint32_t * ) portOSTM0CTL_ADDR ) =
+        ( portOSTM_MODE_INTERVAL_TIMER | portOSTM_START_INTERRUPT_DISABLE );
+    *( ( volatile uint32_t * ) portOSTM0CMP_ADDR ) =
+        ( ( configCPU_CLOCK_HZ / configTIMER_PRESCALE ) / configTICK_RATE_HZ ) - 1;
+
+    /* Enable OSTM0 operation */
+    *( ( volatile uint32_t * ) portOSTM0TS_ADDR ) = portOSTM_COUNTER_START;
+}
+
+/*-----------------------------------------------------------*/
+
+#if ( configNUMBER_OF_CORES > 1 )
+
+/*
+ * These functions implement spin-lock mechanism among cores using hardware
+ * exclusive control with atomic access by CLR1 and SET1 instruction.
+ * Nesting calls to these APIs are possible.
+ */
+    #pragma inline_asm prvExclusiveLock
+    static void prvExclusiveLock( BaseType_t xBitPosition )
+    {
+        /* No problem with r19, CCRH does not required to restore same value
+         * before and after function call. */
+        mov     # _pxPortExclusiveReg, r19
+        ld.w    0[ r19 ], r19
+
+prvExclusiveLock_Lock:
+
+        /* r6 is xBitPosition */
+        set1 r6, [ r19 ]
+        bz prvExclusiveLock_Lock_success
+        snooze
+        br prvExclusiveLock_Lock
+
+prvExclusiveLock_Lock_success:
+    }
+
+/*-----------------------------------------------------------*/
+
+    #pragma inline_asm prvExclusiveRelease
+    static void prvExclusiveRelease( BaseType_t xBitPosition )
+    {
+        mov     # _pxPortExclusiveReg, r19
+        ld.w    0[ r19 ], r19
+
+        /* r6 is xBitPosition */
+        clr1 r6, [ r19 ]
+    }
+
+/*-----------------------------------------------------------*/
+    void vPortRecursiveLockAcquire( BaseType_t xFromIsr )
+    {
+        BaseType_t xSavedInterruptStatus;
+        BaseType_t xCoreID = xPortGET_CORE_ID();
+        BaseType_t xBitPosition = ( xFromIsr == pdTRUE );
+
+        xSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+
+        if( uxLockNesting[ xCoreID ][ xBitPosition ] == 0 )
+        {
+            prvExclusiveLock( xBitPosition );
+        }
+
+        uxLockNesting[ xCoreID ][ xBitPosition ]++;
+        portCLEAR_INTERRUPT_MASK_FROM_ISR( xSavedInterruptStatus );
+    }
+
+    void vPortRecursiveLockRelease( BaseType_t xFromIsr )
+    {
+        BaseType_t xSavedInterruptStatus;
+        BaseType_t xCoreID = xPortGET_CORE_ID();
+        BaseType_t xBitPosition = ( xFromIsr == pdTRUE );
+
+        xSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+
+        /* Sync memory */
+        portSYNCM();
+
+        /* Error check whether vPortRecursiveLockRelease() is not called in
+         * pair with vPortRecursiveLockAcquire() */
+        configASSERT( ( uxLockNesting[ xCoreID ][ xBitPosition ] > 0 ) );
+        uxLockNesting[ xCoreID ][ xBitPosition ]--;
+
+        if( uxLockNesting[ xCoreID ][ xBitPosition ] == 0 )
+        {
+            prvExclusiveRelease( xBitPosition );
+        }
+
+        portCLEAR_INTERRUPT_MASK_FROM_ISR( xSavedInterruptStatus );
+    }
+
+/*-----------------------------------------------------------*/
+
+#endif /* (configNUMBER_OF_CORES > 1) */
diff --git a/portable/CCRH/F1Kx/portasm.s b/portable/CCRH/F1Kx/portasm.s
new file mode 100644
index 000000000..4e56f4493
--- /dev/null
+++ b/portable/CCRH/F1Kx/portasm.s
@@ -0,0 +1,325 @@
+;/*
+; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+; *
+; * SPDX-License-Identifier: MIT
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * https://www.FreeRTOS.org
+; * https://github.com/FreeRTOS
+; *
+; */
+
+;------------------------------------------------------------------------------
+; Extern symbols
+;------------------------------------------------------------------------------
+.extern _uxInterruptNesting
+.extern _uxPortMaxInterruptDepth
+.extern _xPortScheduleStatus
+.extern _vTaskSwitchContext
+.extern _pvPortGetCurrentTCB
+.extern _vCommonISRHandler
+.extern _xPortGET_CORE_ID
+
+.public _vIrq_Handler
+.public _vPortStartFirstTask
+.public _vPortYield
+.public _vTRAP0_Handler
+;------------------------------------------------------------------------------
+; Macro definitions
+;------------------------------------------------------------------------------
+EIPC  .set 0
+EIPSW .set 1
+PSW   .set 5
+FPSR  .set 6
+FPEPC .set 7
+EIIC  .set 13
+CTPC  .set 16
+CTPSW .set 17
+EIIC_MSK .set 0x00000FFF
+FPU_MSK  .set 0x00010000
+;------------------------------------------------------------------------------
+; portSAVE_CONTEXT
+; Context saving
+;------------------------------------------------------------------------------
+portSAVE_CONTEXT .macro
+    prepare lp, 0
+
+    ; Save general-purpose registers and EIPSW, EIPC, EIIC, CTPSW, CTPC into stack.
+    pushsp  r5, r30
+    $nowarning
+    pushsp  r1, r2
+    $warning
+
+    stsr    EIPSW, r15
+    stsr    EIPC, r16
+    stsr    EIIC, r17
+    stsr    CTPSW, r18
+    stsr    CTPC, r19
+    pushsp  r15, r19
+
+    ; Save FPU registers to stack if FPU is enabled
+    mov     FPU_MSK, r19
+    tst     r15, r19
+
+    ; Jump over next 3 instructions: stsr (4 bytes)*2 + pushsp (4 bytes)
+    bz      12
+    stsr    FPSR, r18
+    stsr    FPEPC, r19
+    pushsp  r18, r19
+
+    ; Get current TCB, the return value is stored in r10 (CCRH compiler)
+    jarl    _pvPortGetCurrentTCB, lp
+    st.w    sp, 0[r10]
+
+.endm
+
+;------------------------------------------------------------------------------
+; portRESTORE_CONTEXT
+; Context restoring
+;------------------------------------------------------------------------------
+portRESTORE_CONTEXT .macro
+    ; Current TCB is returned by r10 (CCRH compiler)
+    jarl    _pvPortGetCurrentTCB, lp
+    ld.w    0[r10], sp                  ; Restore the stack pointer from the TCB
+
+    ; Restore FPU registers if FPU is enabled
+    mov     FPU_MSK, r19
+    stsr    PSW, r18
+    tst     r18, r19
+
+     ; Jump over next 3 instructions: stsr (4 bytes)*2 + popsp (4 bytes)
+    bz      12
+    popsp   r18, r19
+    ldsr    r18, FPEPC
+    ldsr    r19, FPSR
+
+    ;Restore general-purpose registers and EIPSW, EIPC, EIIC, CTPSW, CTPC
+    popsp   r15, r19
+    ldsr    r19, CTPC
+    ldsr    r18, CTPSW
+    ldsr    r17, EIIC
+    ldsr    r16, EIPC
+    ldsr    r15, EIPSW
+
+    $nowarning
+    popsp   r1, r2
+    $warning
+    popsp   r5, r30
+
+    dispose 0, lp
+.endm
+
+;------------------------------------------------------------------------------
+; Save used registers
+;------------------------------------------------------------------------------
+SAVE_REGISTER .macro
+    ; Save general-purpose registers and EIPSW, EIPC, EIIC, CTPSW, CTPC into stack.
+    ; Callee-Save registers (r20 to r30) are not used in interrupt handler and
+    ; guaranteed no change after function call. So, don't need to save register
+    ; to optimize the used stack memory.
+    pushsp  r5, r19
+    $nowarning
+    pushsp  r1, r2
+    $warning
+
+    stsr    EIPSW, r19
+    stsr    EIPC, r18
+    stsr    EIIC, r17
+    mov     lp, r16
+    mov     ep, r15
+    stsr    CTPSW, r14
+    stsr    CTPC, r13
+    pushsp  r13, r19
+
+    mov     FPU_MSK, r16
+    tst     r16, r19
+    bz      12
+    stsr    FPSR, r18
+    stsr    FPEPC, r19
+    pushsp  r18, r19
+
+.endm
+;------------------------------------------------------------------------------
+; Restore used registers
+;------------------------------------------------------------------------------
+RESTORE_REGISTER .macro
+
+    mov     FPU_MSK, r16
+    stsr    PSW, r18
+    tst     r18, r19
+    bz      12
+    popsp   r18, r19
+    ldsr    r18, FPEPC
+    ldsr    r19, FPSR
+
+    popsp   r13, r19
+    ldsr    r13, CTPC
+    ldsr    r14, CTPSW
+    mov     r15, ep
+    mov     r16, lp
+    ldsr    r17, EIIC
+    ldsr    r18, EIPC
+    ldsr    r19, EIPSW
+
+    $nowarning
+    popsp   r1, r2
+    $warning
+    popsp   r5, r19
+.endm
+
+;------------------------------------------------------------------------------
+; Start the first task.
+;------------------------------------------------------------------------------
+_vPortStartFirstTask:
+    portRESTORE_CONTEXT
+    eiret
+
+;------------------------------------------------------------------------------
+; _vPortYield
+;------------------------------------------------------------------------------
+_vPortYield:
+    trap    0
+    jmp     [lp]                        ; Return to caller function
+
+;------------------------------------------------------------------------------
+; PortYield handler. This is installed as the TRAP exception handler.
+;------------------------------------------------------------------------------
+_vTRAP0_Handler:
+    ;Save the context of the current task.
+    portSAVE_CONTEXT
+
+    ; The use case that portYield() is called from interrupt context as nested interrupt.
+    ; Context switch should be executed at the most outer of interrupt tree.
+    ; In that case, set xPortScheduleStatus to flag context switch in interrupt handler.
+    jarl    _xPortGET_CORE_ID, lp ; return value is contained in r10 (CCRH compiler)
+    mov     r10, r11
+    shl     2, r11
+    mov     #_uxInterruptNesting, r19
+    add     r11, r19
+    ld.w    0[r19], r18
+    cmp     r0, r18
+    be      _vTRAP0_Handler_ContextSwitch
+
+    mov     #_xPortScheduleStatus, r19
+    add     r11, r19
+
+    ; Set xPortScheduleStatus[coreID]=PORT_SCHEDULER_TASKSWITCH
+    mov     1, r17
+    st.w    r17, 0[r19]
+    br      _vTRAP0_Handler_Exit
+
+_vTRAP0_Handler_ContextSwitch:
+    ; Pass coreID (r10) as parameter by r6 (CCRH compiler) in SMP support.
+    mov     r10, r6
+    ; Call the scheduler to select the next task.
+    ; vPortYeild may be called to current core again at the end of vTaskSwitchContext.
+    ; This may case nested interrupt, however, it is not necessary to set
+    ; uxInterruptNesting (currently 0) for nested trap0 exception. The user interrupt
+    ; (EI level interrupt) is not accepted inside of trap0 exception.
+    jarl    _vTaskSwitchContext, lp
+
+_vTRAP0_Handler_Exit:
+    ; Restore the context of the next task to run.
+    portRESTORE_CONTEXT
+    eiret
+
+;------------------------------------------------------------------------------
+; _Irq_Handler
+; Handler interrupt service routine (ISR).
+;------------------------------------------------------------------------------
+_vIrq_Handler:
+    ; Save used registers.
+    SAVE_REGISTER
+
+    ; Get core ID by HTCFG0, thread configuration register.
+    ; Then, increase nesting count for current core.
+    jarl    _xPortGET_CORE_ID, lp ; return value is contained in r10 (CCRH compiler)
+    shl     2, r10
+    mov     r10, r17
+
+    mov     #_uxInterruptNesting, r19
+    add     r17, r19
+    ld.w    0[r19], r18
+    addi    0x1, r18, r16
+    st.w    r16, 0[r19]
+
+    pushsp  r17, r19
+
+    ;Call the interrupt handler.
+    stsr    EIIC, r6
+    andi    EIIC_MSK, r6, r6
+
+    ; Do not enable interrupt for nesting. Stackover flow may occurs if the
+    ; depth of nesting interrupt is exceeded.
+    mov     #_uxPortMaxInterruptDepth, r15
+    cmp     r16, r15
+    be      4                                 ; Jump over ei instruction
+    ei
+    jarl    _vCommonISRHandler, lp
+    di
+    synce
+
+    popsp   r17, r19
+    st.w    r18, 0[r19]                  ; Restore the old nesting count.
+
+    ; A context switch if no nesting interrupt.
+    cmp     0x0, r18
+    bne     _vIrq_Handler_NotSwitchContext
+
+    ; Check if context switch is requested.
+    mov     #_xPortScheduleStatus, r19
+    add     r17, r19
+    ld.w    0[r19], r18
+    cmp     r0, r18
+    bne     _vIrq_Handler_SwitchContext
+
+_vIrq_Handler_NotSwitchContext:
+    ; No context switch.  Restore used registers
+    RESTORE_REGISTER
+    eiret
+
+;This sequence is executed for primary core only to switch context
+_vIrq_Handler_SwitchContext:
+    ; Clear the context switch pending flag.
+    st.w r0, 0[r19]
+
+    add     -1, r18
+    bnz     _vIrq_Handler_StartFirstTask
+    ; Restore used registers before saving the context to the task stack.
+    RESTORE_REGISTER
+    portSAVE_CONTEXT
+
+    ; Get Core ID and pass to vTaskSwitchContext as parameter (CCRH compiler)
+    ; The parameter is  unused in single core, no problem with this redudant setting
+    jarl    _xPortGET_CORE_ID, lp ; return value is contained in r10 (CCRH compiler)
+    mov     r10, r6
+
+    ; vPortYeild may be called to current core again at the end of vTaskSwitchContext.
+    ; This may case nested interrupt, however, it is not necessary to set
+    ; uxInterruptNesting (currently 0) for  trap0 exception. The user interrupt
+    ; (EI level interrupt) is not accepted inside of trap0 exception.
+    jarl    _vTaskSwitchContext, lp    ;
+    portRESTORE_CONTEXT
+    eiret
+
+_vIrq_Handler_StartFirstTask:
+    RESTORE_REGISTER
+    jr _vPortStartFirstTask
+
diff --git a/portable/CCRH/F1Kx/portmacro.h b/portable/CCRH/F1Kx/portmacro.h
new file mode 100644
index 000000000..e2b41f264
--- /dev/null
+++ b/portable/CCRH/F1Kx/portmacro.h
@@ -0,0 +1,193 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTMACRO_H
+    #define PORTMACRO_H
+
+    #ifdef __cplusplus
+        extern "C"
+        {
+    #endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions - These are a bit legacy and not really used now, other
+ * than portSTACK_TYPE and portBASE_TYPE. */
+    #define portCHAR          char
+    #define portFLOAT         float
+    #define portDOUBLE        double
+    #define portLONG          long
+    #define portSHORT         short
+    #define portSTACK_TYPE    uint32_t
+    #define portBASE_TYPE     long
+
+    typedef portSTACK_TYPE   StackType_t;
+    typedef long             BaseType_t;
+    typedef unsigned long    UBaseType_t;
+
+/* Defines the maximum time when using a wait command in a task */
+    #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+        typedef uint16_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffff
+    #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+        typedef uint32_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+        #define portTICK_TYPE_IS_ATOMIC    1
+    #else
+        #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+    #endif
+
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics */
+
+    #define portSTSR( reg )              __stsr( ( reg ) )
+    #define portLDSR( reg, val )         __ldsr( ( reg ), ( val ) )
+    #define portSTSR_CCRH( reg, sel )    __stsr_rh( ( reg ), ( sel ) )
+    #define portSYNCM()                  __syncm()
+
+/* Determine the descending of the stack from high address to address */
+    #define portSTACK_GROWTH      ( -1 )
+
+/* Determine the time (in milliseconds) corresponding to each tick */
+    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+
+/* It is a multiple of 4 (the two lower-order bits of the address = 0),
+ * otherwise it will cause MAE (Misaligned Exception) according to the manual */
+    #define portBYTE_ALIGNMENT    ( 4 )
+
+/* Interrupt control macros. */
+
+    #define portENABLE_INTERRUPTS()     __EI() /* Macro to enable all maskable interrupts. */
+    #define portDISABLE_INTERRUPTS()    __DI() /* Macro to disable all maskable interrupts. */
+    #define taskENABLE_INTERRUPTS()     portENABLE_INTERRUPTS()
+    #define taskDISABLE_INTERRUPTS()    portDISABLE_INTERRUPTS()
+
+/* SMP build which means configNUM_CORES is relevant */
+    #define portSUPPORT_SMP              1
+
+    #define portMAX_CORE_COUNT           2
+    #ifndef configNUMBER_OF_CORES
+        #define configNUMBER_OF_CORES    1
+    #endif
+
+/*-----------------------------------------------------------*/
+/* Scheduler utilities */
+
+/* Called at the end of an ISR that can cause a context switch */
+    extern void vPortSetSwitch( BaseType_t vPortSetSwitch );
+
+    #define portEND_SWITCHING_ISR( xSwitchRequired )    vPortSetSwitch( vPortSetSwitch )
+
+    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+
+/* Use to transfer control from one task to perform other tasks of
+ * higher priority */
+    extern void vPortYield( void );
+
+    #define portYIELD()    vPortYield()
+    #if ( configNUMBER_OF_CORES > 1 )
+
+/* Return the core ID on which the code is running. */
+        extern BaseType_t xPortGET_CORE_ID();
+
+        #define portGET_CORE_ID()    xPortGET_CORE_ID()
+        #define coreid    xPortGET_CORE_ID()
+
+/* Request the core ID x to yield. */
+        extern void vPortYieldCore( unsigned int coreID );
+
+        #define portYIELD_CORE( x )                vPortYieldCore( x )
+
+        #define portENTER_CRITICAL_FROM_ISR()      vTaskEnterCriticalFromISR()
+        #define portEXIT_CRITICAL_FROM_ISR( x )    vTaskExitCriticalFromISR( x )
+
+    #endif /* if ( configNUMBER_OF_CORES > 1 ) */
+
+    #if ( configNUMBER_OF_CORES == 1 )
+        #define portGET_ISR_LOCK()
+        #define portRELEASE_ISR_LOCK()
+        #define portGET_TASK_LOCK()
+        #define portRELEASE_TASK_LOCK()
+    #else
+        extern void vPortRecursiveLockAcquire( BaseType_t xFromIsr );
+        extern void vPortRecursiveLockRelease( BaseType_t xFromIsr );
+
+        #define portGET_ISR_LOCK()         vPortRecursiveLockAcquire( pdTRUE )
+        #define portRELEASE_ISR_LOCK()     vPortRecursiveLockRelease( pdTRUE )
+        #define portGET_TASK_LOCK()        vPortRecursiveLockAcquire( pdFALSE )
+        #define portRELEASE_TASK_LOCK()    vPortRecursiveLockRelease( pdFALSE )
+    #endif /* if ( configNUMBER_OF_CORES == 1 ) */
+
+/*-----------------------------------------------------------*/
+/* Critical section management. */
+
+/* The critical nesting functions defined within tasks.c */
+
+    extern void vTaskEnterCritical( void );
+    extern void vTaskExitCritical( void );
+
+/* Macro to mark the start of a critical code region */
+    #define portENTER_CRITICAL()    vTaskEnterCritical()
+
+/* Macro to mark the end of a critical code region */
+    #define portEXIT_CRITICAL()     vTaskExitCritical()
+
+/*-----------------------------------------------------------*/
+/* Macros to set and clear the interrupt mask. */
+    portLONG xPortSetInterruptMask();
+    void vPortClearInterruptMask( portLONG );
+
+    #define portSET_INTERRUPT_MASK()                  xPortSetInterruptMask()
+    #define portCLEAR_INTERRUPT_MASK( x )             vPortClearInterruptMask( ( x ) )
+    #define portSET_INTERRUPT_MASK_FROM_ISR()         xPortSetInterruptMask()
+    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vPortClearInterruptMask( ( x ) )
+
+/*-----------------------------------------------------------*/
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+
+    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+
+/*-----------------------------------------------------------*/
+
+    #ifdef __cplusplus
+}
+    #endif
+#endif /* PORTMACRO_H */

From 190906aeaf7ee0a7a35d6e4b83d2b0fd34b14163 Mon Sep 17 00:00:00 2001
From: superroc <liuqp@126.com>
Date: Mon, 12 Aug 2024 19:36:47 +0800
Subject: [PATCH 307/424] Add portMEMORY_BARRIER defination to fix
 over-optimization in xTaskResumeAll. (#1116)

Co-authored-by: owen <owen@freqchip.com>
---
 portable/ThirdParty/XCC/Xtensa/portmacro.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/portable/ThirdParty/XCC/Xtensa/portmacro.h b/portable/ThirdParty/XCC/Xtensa/portmacro.h
index d6a79b9be..dced2382c 100644
--- a/portable/ThirdParty/XCC/Xtensa/portmacro.h
+++ b/portable/ThirdParty/XCC/Xtensa/portmacro.h
@@ -114,6 +114,7 @@ static inline unsigned portENTER_CRITICAL_NESTED() { unsigned state = XTOS_SET_I
 #define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
 #define portBYTE_ALIGNMENT          4
 #define portNOP()                   XT_NOP()
+#define portMEMORY_BARRIER()        XT_MEMW()
 /*-----------------------------------------------------------*/
 
 /* Fine resolution time */

From 40dbccf1421e0af28a9525129e25fa6e15ac954b Mon Sep 17 00:00:00 2001
From: xuelix <33909469+xuelix@users.noreply.github.com>
Date: Mon, 12 Aug 2024 15:47:30 -0700
Subject: [PATCH 308/424] =?UTF-8?q?Updated=20the=20return=20values=20for?=
 =?UTF-8?q?=20functions=20in=20queue.c=20based=20on=20the=20actua=E2=80=A6?=
 =?UTF-8?q?=20(#1117)?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

* Updated the return values for functions in queue.c based on the actual code.
---
 include/queue.h | 38 +++++++++++++++++++-------------------
 1 file changed, 19 insertions(+), 19 deletions(-)

diff --git a/include/queue.h b/include/queue.h
index 80345b9f0..963904bb3 100644
--- a/include/queue.h
+++ b/include/queue.h
@@ -109,7 +109,7 @@ typedef struct QueueDefinition   * QueueSetMemberHandle_t;
  * the same size.
  *
  * @return If the queue is successfully create then a handle to the newly
- * created queue is returned.  If the queue cannot be created then 0 is
+ * created queue is returned.  If the queue cannot be created then NULL is
  * returned.
  *
  * Example usage:
@@ -126,7 +126,7 @@ typedef struct QueueDefinition   * QueueSetMemberHandle_t;
  *
  *  // Create a queue capable of containing 10 uint32_t values.
  *  xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
- *  if( xQueue1 == 0 )
+ *  if( xQueue1 == NULL )
  *  {
  *      // Queue was not created and must not be used.
  *  }
@@ -134,7 +134,7 @@ typedef struct QueueDefinition   * QueueSetMemberHandle_t;
  *  // Create a queue capable of containing 10 pointers to AMessage structures.
  *  // These should be passed by pointer as they contain a lot of data.
  *  xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
- *  if( xQueue2 == 0 )
+ *  if( xQueue2 == NULL )
  *  {
  *      // Queue was not created and must not be used.
  *  }
@@ -292,7 +292,7 @@ typedef struct QueueDefinition   * QueueSetMemberHandle_t;
  * queue is full.  The time is defined in tick periods so the constant
  * portTICK_PERIOD_MS should be used to convert to real time if this is required.
  *
- * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ * @return pdPASS if the item was successfully posted, otherwise errQUEUE_FULL.
  *
  * Example usage:
  * @code{c}
@@ -375,7 +375,7 @@ typedef struct QueueDefinition   * QueueSetMemberHandle_t;
  * is full.  The  time is defined in tick periods so the constant
  * portTICK_PERIOD_MS should be used to convert to real time if this is required.
  *
- * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ * @return pdPASS if the item was successfully posted, otherwise errQUEUE_FULL.
  *
  * Example usage:
  * @code{c}
@@ -460,7 +460,7 @@ typedef struct QueueDefinition   * QueueSetMemberHandle_t;
  * queue is full.  The time is defined in tick periods so the constant
  * portTICK_PERIOD_MS should be used to convert to real time if this is required.
  *
- * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ * @return pdPASS if the item was successfully posted, otherwise errQUEUE_FULL.
  *
  * Example usage:
  * @code{c}
@@ -633,7 +633,7 @@ typedef struct QueueDefinition   * QueueSetMemberHandle_t;
  * item at the back of the queue, or queueSEND_TO_FRONT to place the item
  * at the front of the queue (for high priority messages).
  *
- * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ * @return pdPASS if the item was successfully posted, otherwise errQUEUE_FULL.
  *
  * Example usage:
  * @code{c}
@@ -723,8 +723,8 @@ BaseType_t xQueueGenericSend( QueueHandle_t xQueue,
  * xQueuePeek() will return immediately if xTicksToWait is 0 and the queue
  * is empty.
  *
- * @return pdTRUE if an item was successfully received from the queue,
- * otherwise pdFALSE.
+ * @return pdPASS if an item was successfully received from the queue,
+ * otherwise errQUEUE_EMPTY.
  *
  * Example usage:
  * @code{c}
@@ -811,8 +811,8 @@ BaseType_t xQueuePeek( QueueHandle_t xQueue,
  * @param pvBuffer Pointer to the buffer into which the received item will
  * be copied.
  *
- * @return pdTRUE if an item was successfully received from the queue,
- * otherwise pdFALSE.
+ * @return pdPASS if an item was successfully received from the queue,
+ * otherwise pdFAIL.
  *
  * \defgroup xQueuePeekFromISR xQueuePeekFromISR
  * \ingroup QueueManagement
@@ -852,8 +852,8 @@ BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue,
  * constant portTICK_PERIOD_MS should be used to convert to real time if this is
  * required.
  *
- * @return pdTRUE if an item was successfully received from the queue,
- * otherwise pdFALSE.
+ * @return pdPASS if an item was successfully received from the queue,
+ * otherwise errQUEUE_EMPTY.
  *
  * Example usage:
  * @code{c}
@@ -998,7 +998,7 @@ void vQueueDelete( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
  * running task.  If xQueueSendToFrontFromISR() sets this value to pdTRUE then
  * a context switch should be requested before the interrupt is exited.
  *
- * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * @return pdPASS if the data was successfully sent to the queue, otherwise
  * errQUEUE_FULL.
  *
  * Example usage for buffered IO (where the ISR can obtain more than one value
@@ -1070,7 +1070,7 @@ void vQueueDelete( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
  * running task.  If xQueueSendToBackFromISR() sets this value to pdTRUE then
  * a context switch should be requested before the interrupt is exited.
  *
- * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * @return pdPASS if the data was successfully sent to the queue, otherwise
  * errQUEUE_FULL.
  *
  * Example usage for buffered IO (where the ISR can obtain more than one value
@@ -1235,7 +1235,7 @@ void vQueueDelete( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
  * running task.  If xQueueSendFromISR() sets this value to pdTRUE then
  * a context switch should be requested before the interrupt is exited.
  *
- * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * @return pdPASS if the data was successfully sent to the queue, otherwise
  * errQUEUE_FULL.
  *
  * Example usage for buffered IO (where the ISR can obtain more than one value
@@ -1318,7 +1318,7 @@ void vQueueDelete( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
  * item at the back of the queue, or queueSEND_TO_FRONT to place the item
  * at the front of the queue (for high priority messages).
  *
- * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * @return pdPASS if the data was successfully sent to the queue, otherwise
  * errQUEUE_FULL.
  *
  * Example usage for buffered IO (where the ISR can obtain more than one value
@@ -1389,8 +1389,8 @@ BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue,
  * to unblock *pxTaskWoken will get set to pdTRUE, otherwise *pxTaskWoken will
  * remain unchanged.
  *
- * @return pdTRUE if an item was successfully received from the queue,
- * otherwise pdFALSE.
+ * @return pdPASS if an item was successfully received from the queue,
+ * otherwise pdFAIL.
  *
  * Example usage:
  * @code{c}

From a936c10e2c2eab24e625ce6b8d27b6d88c22808a Mon Sep 17 00:00:00 2001
From: xuelix <33909469+xuelix@users.noreply.github.com>
Date: Wed, 14 Aug 2024 11:08:32 -0700
Subject: [PATCH 309/424] Modify the name of a private function to reflect what
 it actually does (#1119)

---
 queue.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/queue.c b/queue.c
index dd302c908..1a14c743d 100644
--- a/queue.c
+++ b/queue.c
@@ -247,7 +247,7 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength,
  * other tasks that are waiting for the same mutex.  This function returns
  * that priority.
  */
-    static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;
+    static UBaseType_t prvGetHighestPriorityOfWaitToReceiveList( const Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;
 #endif
 /*-----------------------------------------------------------*/
 
@@ -1844,13 +1844,13 @@ BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue,
                              * has timed out the priority should be disinherited
                              * again, but only as low as the next highest priority
                              * task that is waiting for the same mutex. */
-                            uxHighestWaitingPriority = prvGetDisinheritPriorityAfterTimeout( pxQueue );
+                            uxHighestWaitingPriority = prvGetHighestPriorityOfWaitToReceiveList( pxQueue );
 
                             /* vTaskPriorityDisinheritAfterTimeout uses the uxHighestWaitingPriority
                              * parameter to index pxReadyTasksLists when adding the task holding
                              * mutex to the ready list for its new priority. Coverity thinks that
                              * it can result in out-of-bounds access which is not true because
-                             * uxHighestWaitingPriority, as returned by prvGetDisinheritPriorityAfterTimeout,
+                             * uxHighestWaitingPriority, as returned by prvGetHighestPriorityOfWaitToReceiveList,
                              * is capped at ( configMAX_PRIORITIES - 1 ). */
                             /* coverity[overrun] */
                             vTaskPriorityDisinheritAfterTimeout( pxQueue->u.xSemaphore.xMutexHolder, uxHighestWaitingPriority );
@@ -2362,7 +2362,7 @@ UBaseType_t uxQueueGetQueueLength( QueueHandle_t xQueue ) /* PRIVILEGED_FUNCTION
 
 #if ( configUSE_MUTEXES == 1 )
 
-    static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue )
+    static UBaseType_t prvGetHighestPriorityOfWaitToReceiveList( const Queue_t * const pxQueue )
     {
         UBaseType_t uxHighestPriorityOfWaitingTasks;
 

From 294569e495515e238dc890a8b4613d01260d1f06 Mon Sep 17 00:00:00 2001
From: Chen YM <cymb103u@cs.ccu.edu.tw>
Date: Mon, 19 Aug 2024 13:04:33 +0800
Subject: [PATCH 310/424] Optimize xTaskIncrementTick for configNUMBER_OF_CORES
 > 1 (#1118)

The original implementation only initializes the first
variable. After executing xTaskIncrementTick, the schedule
might not behave as expected.

When configUSE_PREEMPTION == 1 & configUSE_TIME_SLICING == 1,
replace setting xYieldRequiredForCore[ xCoreID ] with setting
xYieldPendings[ xCoreID ].

And when configUSE_PREEMPTION == 1, simplify the check
condition to only check xYieldPendings[ xCoreID ].

Signed-off-by: cymzier <cymb103u@cs.ccu.edu.tw>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
---
 tasks.c | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/tasks.c b/tasks.c
index 3382954b8..cb3c190b9 100644
--- a/tasks.c
+++ b/tasks.c
@@ -4698,10 +4698,6 @@ BaseType_t xTaskIncrementTick( void )
     TickType_t xItemValue;
     BaseType_t xSwitchRequired = pdFALSE;
 
-    #if ( configUSE_PREEMPTION == 1 ) && ( configNUMBER_OF_CORES > 1 )
-    BaseType_t xYieldRequiredForCore[ configNUMBER_OF_CORES ] = { pdFALSE };
-    #endif /* #if ( configUSE_PREEMPTION == 1 ) && ( configNUMBER_OF_CORES > 1 ) */
-
     traceENTER_xTaskIncrementTick();
 
     /* Called by the portable layer each time a tick interrupt occurs.
@@ -4853,7 +4849,7 @@ BaseType_t xTaskIncrementTick( void )
                 {
                     if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCBs[ xCoreID ]->uxPriority ] ) ) > 1U )
                     {
-                        xYieldRequiredForCore[ xCoreID ] = pdTRUE;
+                        xYieldPendings[ xCoreID ] = pdTRUE;
                     }
                     else
                     {
@@ -4905,7 +4901,7 @@ BaseType_t xTaskIncrementTick( void )
                         if( pxCurrentTCBs[ xCoreID ]->xPreemptionDisable == pdFALSE )
                     #endif
                     {
-                        if( ( xYieldRequiredForCore[ xCoreID ] != pdFALSE ) || ( xYieldPendings[ xCoreID ] != pdFALSE ) )
+                        if( xYieldPendings[ xCoreID ] != pdFALSE )
                         {
                             if( xCoreID == xCurrentCoreID )
                             {

From 49e88310bec6f54f7cfe9db94edf3fb97e7d4ccc Mon Sep 17 00:00:00 2001
From: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Date: Mon, 19 Aug 2024 05:37:24 +0000
Subject: [PATCH 311/424] Fix compilation issue of IA32_flat port (#1122)

* Fix compilation issue of IAR32 port

* Add new line at EOF

* Fix header check

---------

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
---
 portable/GCC/IA32_flat/ISR_Support.h | 145 +++++++++++++--------------
 1 file changed, 71 insertions(+), 74 deletions(-)

diff --git a/portable/GCC/IA32_flat/ISR_Support.h b/portable/GCC/IA32_flat/ISR_Support.h
index 545a8d236..18e10bf91 100644
--- a/portable/GCC/IA32_flat/ISR_Support.h
+++ b/portable/GCC/IA32_flat/ISR_Support.h
@@ -26,106 +26,103 @@
  *
  */
 
-.extern ulTopOfSystemStack
-   .extern ulInterruptNesting
+    .extern ulTopOfSystemStack
+    .extern ulInterruptNesting
 
 /*-----------------------------------------------------------*/
 
-   .macro portFREERTOS_INTERRUPT_ENTRY
+.macro portFREERTOS_INTERRUPT_ENTRY
 
-/* Save general purpose registers. */
-pusha
+    /* Save general purpose registers. */
+    pusha
 
-/* If ulInterruptNesting is zero the rest of the task context will need
- * saving and a stack switch might be required. */
-movl ulInterruptNesting, % eax
-test % eax, % eax
-jne     2f
+    /* If ulInterruptNesting is zero the rest of the task context will need
+    saving and a stack switch might be required. */
+    movl    ulInterruptNesting, %eax
+    test    %eax, %eax
+    jne     2f
 
-/* Interrupts are not nested, so save the rest of the task context. */
-   .
+    /* Interrupts are not nested, so save the rest of the task context. */
+    .if configSUPPORT_FPU == 1
 
-   if configSUPPORT_FPU == 1
+        /* If the task has a buffer allocated to save the FPU context then
+        save the FPU context now. */
+        movl    pucPortTaskFPUContextBuffer, %eax
+        test    %eax, %eax
+        je      1f
+        fnsave  ( %eax ) /* Save FLOP context into ucTempFPUBuffer array. */
+        fwait
 
-/* If the task has a buffer allocated to save the FPU context then
- * save the FPU context now. */
-movl pucPortTaskFPUContextBuffer, % eax
-test % eax, % eax
-je      1f
-fnsave( % eax ) /* Save FLOP context into ucTempFPUBuffer array. */
-fwait
+        1:
+        /* Save the address of the FPU context, if any. */
+        push    pucPortTaskFPUContextBuffer
 
-1 :
-/* Save the address of the FPU context, if any. */
-push pucPortTaskFPUContextBuffer
+    .endif /* configSUPPORT_FPU */
 
-   .endif /* configSUPPORT_FPU */
+    /* Find the TCB. */
+    movl    pxCurrentTCB, %eax
 
-/* Find the TCB. */
-movl pxCurrentTCB, % eax
+    /* Stack location is first item in the TCB. */
+    movl    %esp, (%eax)
 
-/* Stack location is first item in the TCB. */
-     movl % esp, ( % eax )
+    /* Switch stacks. */
+    movl    ulTopOfSystemStack, %esp
+    movl    %esp, %ebp
 
-/* Switch stacks. */
-movl ulTopOfSystemStack, % esp
-movl % esp, % ebp
+    2:
+    /* Increment nesting count. */
+    add     $1, ulInterruptNesting
 
-2 :
-/* Increment nesting count. */
-add $1, ulInterruptNesting
-
-   .endm
+.endm
 /*-----------------------------------------------------------*/
 
-   .macro portINTERRUPT_EPILOGUE
+.macro portINTERRUPT_EPILOGUE
 
-cli
-sub $1, ulInterruptNesting
+    cli
+    sub     $1, ulInterruptNesting
 
-/* If the nesting has unwound to zero. */
-movl ulInterruptNesting, % eax
-     test % eax, % eax
-     jne     2f
+    /* If the nesting has unwound to zero. */
+    movl    ulInterruptNesting, %eax
+    test    %eax, %eax
+    jne     2f
 
-/* If a yield was requested then select a new TCB now. */
-movl ulPortYieldPending, % eax
-     test % eax, % eax
-     je      1f
-movl $0, ulPortYieldPending
-call vTaskSwitchContext
+    /* If a yield was requested then select a new TCB now. */
+    movl    ulPortYieldPending, %eax
+    test    %eax, %eax
+    je      1f
+    movl    $0, ulPortYieldPending
+    call    vTaskSwitchContext
 
-1 :
-/* Stack location is first item in the TCB. */
-movl pxCurrentTCB, % eax movl( % eax ), % esp
+    1:
+    /* Stack location is first item in the TCB. */
+    movl    pxCurrentTCB, %eax
+    movl    (%eax), %esp
 
-   .
+    .if configSUPPORT_FPU == 1
 
-   if configSUPPORT_FPU == 1
+        /* Restore address of task's FPU context buffer. */
+        pop     pucPortTaskFPUContextBuffer
 
-/* Restore address of task's FPU context buffer. */
-pop pucPortTaskFPUContextBuffer
+        /* If the task has a buffer allocated in which its FPU context is saved,
+        then restore it now. */
+        movl    pucPortTaskFPUContextBuffer, %eax
+        test    %eax, %eax
+        je      1f
+        frstor  ( %eax )
+        1:
+    .endif
 
-/* If the task has a buffer allocated in which its FPU context is saved,
- * then restore it now. */
-movl pucPortTaskFPUContextBuffer, % eax
-test % eax, % eax
-je      1f
-frstor( % eax )
-1 :
-.endif
+    2:
+    popa
 
-2 :
-popa
-
-   .endm
+.endm
 /*-----------------------------------------------------------*/
 
-   .macro portFREERTOS_INTERRUPT_EXIT
+.macro portFREERTOS_INTERRUPT_EXIT
 
-portINTERRUPT_EPILOGUE
-/* EOI. */
-movl $0x00, ( 0xFEE000B0 )
-iret
+    portINTERRUPT_EPILOGUE
+    /* EOI. */
+    movl    $0x00, (0xFEE000B0)
+    iret
 
-   .endm
+.endm

From 2faa8bc1541355b20f25ef4d47d1c1e48c81810a Mon Sep 17 00:00:00 2001
From: mayl <192939+mayl@users.noreply.github.com>
Date: Mon, 19 Aug 2024 02:01:30 -0400
Subject: [PATCH 312/424] Remove hardware dependence in portmacros.h (#1112)

* Remove hardware dependence in portmacros.h

The IAR MSP430X port `#include "msp430.h"` which pulls all the hardware
register definitions into anything which `#include "FreeRTOS.h"`.  This
removes that hardware dependency "leak" by removing the header file
and re-defining the `portDISABLE_INTERRUPTS()` and
`portENABLE_INTERRUPTS()` macros in terms of `__asm`.

* Code review suggestions

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 portable/CCS/MSP430X/port.c      | 3 +++
 portable/CCS/MSP430X/portmacro.h | 9 +++------
 portable/IAR/MSP430X/port.c      | 3 +++
 portable/IAR/MSP430X/portmacro.h | 9 +++------
 4 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/portable/CCS/MSP430X/port.c b/portable/CCS/MSP430X/port.c
index 186fb2cdd..2097a2931 100644
--- a/portable/CCS/MSP430X/port.c
+++ b/portable/CCS/MSP430X/port.c
@@ -26,6 +26,9 @@
  *
  */
 
+/* Hardware includes. */
+#include "msp430.h"
+
 /* Scheduler includes. */
 #include "FreeRTOS.h"
 #include "task.h"
diff --git a/portable/CCS/MSP430X/portmacro.h b/portable/CCS/MSP430X/portmacro.h
index 91e2b9c5b..c00c5a902 100644
--- a/portable/CCS/MSP430X/portmacro.h
+++ b/portable/CCS/MSP430X/portmacro.h
@@ -39,9 +39,6 @@
  *-----------------------------------------------------------
  */
 
-/* Hardware includes. */
-#include "msp430.h"
-
 /* Type definitions. */
 #define portCHAR        char
 #define portFLOAT       float
@@ -75,8 +72,8 @@ typedef unsigned short UBaseType_t;
 /*-----------------------------------------------------------*/
 
 /* Interrupt control macros. */
-#define portDISABLE_INTERRUPTS()    _disable_interrupt(); _nop()
-#define portENABLE_INTERRUPTS()     _enable_interrupt(); _nop()
+#define portDISABLE_INTERRUPTS()    __asm volatile ( " DINT\n" " NOP" )
+#define portENABLE_INTERRUPTS()     __asm volatile ( " NOP\n" " EINT\n" " NOP" )
 /*-----------------------------------------------------------*/
 
 /* Critical section control macros. */
@@ -126,7 +123,7 @@ extern void vPortYield( void );
 #define portBYTE_ALIGNMENT          2
 #define portSTACK_GROWTH            ( -1 )
 #define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portNOP()                   __no_operation()
+#define portNOP()                   __asm volatile ( " NOP" )
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */
diff --git a/portable/IAR/MSP430X/port.c b/portable/IAR/MSP430X/port.c
index a6f81580b..6c5b21c3a 100644
--- a/portable/IAR/MSP430X/port.c
+++ b/portable/IAR/MSP430X/port.c
@@ -30,6 +30,9 @@
 #include "FreeRTOS.h"
 #include "task.h"
 
+/* Hardware includes. */
+#include "msp430.h"
+
 /*-----------------------------------------------------------
 * Implementation of functions defined in portable.h for the MSP430X port.
 *----------------------------------------------------------*/
diff --git a/portable/IAR/MSP430X/portmacro.h b/portable/IAR/MSP430X/portmacro.h
index e426154e8..b428f8d40 100644
--- a/portable/IAR/MSP430X/portmacro.h
+++ b/portable/IAR/MSP430X/portmacro.h
@@ -39,9 +39,6 @@
  *-----------------------------------------------------------
  */
 
-/* Hardware includes. */
-#include "msp430.h"
-
 /* Type definitions. */
 #define portCHAR         char
 #define portFLOAT        float
@@ -75,8 +72,8 @@ typedef unsigned short   UBaseType_t;
 /*-----------------------------------------------------------*/
 
 /* Interrupt control macros. */
-#define portDISABLE_INTERRUPTS()    _DINT(); _NOP()
-#define portENABLE_INTERRUPTS()     _EINT(); _NOP()
+#define portDISABLE_INTERRUPTS()    __asm volatile ( "DINT\n" "NOP" )
+#define portENABLE_INTERRUPTS()     __asm volatile ( "NOP\n" "EINT\n" "NOP" )
 /*-----------------------------------------------------------*/
 
 /* Critical section control macros. */
@@ -126,7 +123,7 @@ extern void vPortYield( void );
 #define portBYTE_ALIGNMENT    2
 #define portSTACK_GROWTH      ( -1 )
 #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portNOP()    __no_operation()
+#define portNOP()             __asm volatile ( "NOP" )
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site. */

From e43553af1e3d19a1eec27593c332f97e986cbd1c Mon Sep 17 00:00:00 2001
From: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Date: Tue, 20 Aug 2024 12:34:01 +0800
Subject: [PATCH 313/424] Yield for task when core affinity of a ready task is
 changed (#1123)

* The SMP scheduler should re-select a core to yield when the core
  affinity of a ready task is changed.
---
 tasks.c | 25 ++++++++-----------------
 1 file changed, 8 insertions(+), 17 deletions(-)

diff --git a/tasks.c b/tasks.c
index cb3c190b9..8002d316a 100644
--- a/tasks.c
+++ b/tasks.c
@@ -2982,11 +2982,6 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
     {
         TCB_t * pxTCB;
         BaseType_t xCoreID;
-        UBaseType_t uxPrevCoreAffinityMask;
-
-        #if ( configUSE_PREEMPTION == 1 )
-            UBaseType_t uxPrevNotAllowedCores;
-        #endif
 
         traceENTER_vTaskCoreAffinitySet( xTask, uxCoreAffinityMask );
 
@@ -2994,7 +2989,6 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
         {
             pxTCB = prvGetTCBFromHandle( xTask );
 
-            uxPrevCoreAffinityMask = pxTCB->uxCoreAffinityMask;
             pxTCB->uxCoreAffinityMask = uxCoreAffinityMask;
 
             if( xSchedulerRunning != pdFALSE )
@@ -3014,17 +3008,14 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
                 {
                     #if ( configUSE_PREEMPTION == 1 )
                     {
-                        /* Calculate the cores on which this task was not allowed to
-                         * run previously. */
-                        uxPrevNotAllowedCores = ( ~uxPrevCoreAffinityMask ) & ( ( 1U << configNUMBER_OF_CORES ) - 1U );
-
-                        /* Does the new core mask enables this task to run on any of the
-                         * previously not allowed cores? If yes, check if this task can be
-                         * scheduled on any of those cores. */
-                        if( ( uxPrevNotAllowedCores & uxCoreAffinityMask ) != 0U )
-                        {
-                            prvYieldForTask( pxTCB );
-                        }
+                        /* The SMP scheduler requests a core to yield when a ready
+                         * task is able to run. It is possible that the core affinity
+                         * of the ready task is changed before the requested core
+                         * can select it to run. In that case, the task may not be
+                         * selected by the previously requested core due to core affinity
+                         * constraint and the SMP scheduler must select a new core to
+                         * yield for the task. */
+                        prvYieldForTask( xTask );
                     }
                     #else /* #if( configUSE_PREEMPTION == 1 ) */
                     {

From 18a168bcd2603354bcc5f8a408b2562d86709dd1 Mon Sep 17 00:00:00 2001
From: Saiiijchan <49641410+Saiiijchan@users.noreply.github.com>
Date: Tue, 20 Aug 2024 21:04:43 +0800
Subject: [PATCH 314/424] Add heap protector to allocted heap blocks (#1125)

When validate those allocated heap block structure, the canary is not used.
Do xor with canary when allocating a new block.

Signed-off-by: wangfei_chen <wangfei_chen@realsil.com.cn>
Co-authored-by: wangfei_chen <wangfei_chen@realsil.com.cn>
---
 portable/MemMang/heap_4.c | 6 +++---
 portable/MemMang/heap_5.c | 6 +++---
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/portable/MemMang/heap_4.c b/portable/MemMang/heap_4.c
index d1021ea09..f3cab000d 100644
--- a/portable/MemMang/heap_4.c
+++ b/portable/MemMang/heap_4.c
@@ -308,7 +308,7 @@ void * pvPortMalloc( size_t xWantedSize )
                     /* The block is being returned - it is allocated and owned
                      * by the application and has no "next" block. */
                     heapALLOCATE_BLOCK( pxBlock );
-                    pxBlock->pxNextFreeBlock = NULL;
+                    pxBlock->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( NULL );
                     xNumberOfSuccessfulAllocations++;
                 }
                 else
@@ -367,11 +367,11 @@ void vPortFree( void * pv )
 
         heapVALIDATE_BLOCK_POINTER( pxLink );
         configASSERT( heapBLOCK_IS_ALLOCATED( pxLink ) != 0 );
-        configASSERT( pxLink->pxNextFreeBlock == NULL );
+        configASSERT( pxLink->pxNextFreeBlock == heapPROTECT_BLOCK_POINTER( NULL ) );
 
         if( heapBLOCK_IS_ALLOCATED( pxLink ) != 0 )
         {
-            if( pxLink->pxNextFreeBlock == NULL )
+            if( pxLink->pxNextFreeBlock == heapPROTECT_BLOCK_POINTER( NULL ) )
             {
                 /* The block is being returned to the heap - it is no longer
                  * allocated. */
diff --git a/portable/MemMang/heap_5.c b/portable/MemMang/heap_5.c
index e0c566640..fccf79825 100644
--- a/portable/MemMang/heap_5.c
+++ b/portable/MemMang/heap_5.c
@@ -336,7 +336,7 @@ void * pvPortMalloc( size_t xWantedSize )
                     /* The block is being returned - it is allocated and owned
                      * by the application and has no "next" block. */
                     heapALLOCATE_BLOCK( pxBlock );
-                    pxBlock->pxNextFreeBlock = NULL;
+                    pxBlock->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( NULL );
                     xNumberOfSuccessfulAllocations++;
                 }
                 else
@@ -395,11 +395,11 @@ void vPortFree( void * pv )
 
         heapVALIDATE_BLOCK_POINTER( pxLink );
         configASSERT( heapBLOCK_IS_ALLOCATED( pxLink ) != 0 );
-        configASSERT( pxLink->pxNextFreeBlock == NULL );
+        configASSERT( pxLink->pxNextFreeBlock == heapPROTECT_BLOCK_POINTER( NULL ) );
 
         if( heapBLOCK_IS_ALLOCATED( pxLink ) != 0 )
         {
-            if( pxLink->pxNextFreeBlock == NULL )
+            if( pxLink->pxNextFreeBlock == heapPROTECT_BLOCK_POINTER( NULL ) )
             {
                 /* The block is being returned to the heap - it is no longer
                  * allocated. */

From 0b904a553adc5f4fdbe0d1df168358579e8788b4 Mon Sep 17 00:00:00 2001
From: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Date: Wed, 21 Aug 2024 09:54:46 +0000
Subject: [PATCH 315/424] Remove access check from ISR function (#1127)

---
 portable/Common/mpu_wrappers_v2.c | 23 ++++++-----------------
 1 file changed, 6 insertions(+), 17 deletions(-)

diff --git a/portable/Common/mpu_wrappers_v2.c b/portable/Common/mpu_wrappers_v2.c
index 2dc36b33b..96f7734f1 100644
--- a/portable/Common/mpu_wrappers_v2.c
+++ b/portable/Common/mpu_wrappers_v2.c
@@ -3838,27 +3838,16 @@
             BaseType_t xReturn = pdFALSE;
             TimerHandle_t xInternalTimerHandle = NULL;
             int32_t lIndex;
-            BaseType_t xIsHigherPriorityTaskWokenWriteable = pdFALSE;
 
-            if( pxHigherPriorityTaskWoken != NULL )
+            lIndex = ( int32_t ) xTimer;
+
+            if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
             {
-                xIsHigherPriorityTaskWokenWriteable = xPortIsAuthorizedToAccessBuffer( pxHigherPriorityTaskWoken,
-                                                                                       sizeof( BaseType_t ),
-                                                                                       tskMPU_WRITE_PERMISSION );
-            }
+                xInternalTimerHandle = MPU_GetTimerHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
 
-            if( ( pxHigherPriorityTaskWoken == NULL ) || ( xIsHigherPriorityTaskWokenWriteable == pdTRUE ) )
-            {
-                lIndex = ( int32_t ) xTimer;
-
-                if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+                if( xInternalTimerHandle != NULL )
                 {
-                    xInternalTimerHandle = MPU_GetTimerHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
-
-                    if( xInternalTimerHandle != NULL )
-                    {
-                        xReturn = xTimerGenericCommandFromISR( xInternalTimerHandle, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait );
-                    }
+                    xReturn = xTimerGenericCommandFromISR( xInternalTimerHandle, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait );
                 }
             }
 

From 23cfd114d314b0e2dc5e53a3540b0647fc0a1b5b Mon Sep 17 00:00:00 2001
From: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Date: Thu, 22 Aug 2024 04:33:58 +0000
Subject: [PATCH 316/424] Update CMakeLists.txt to proper name for the ports
 (#1129)

---
 portable/CMakeLists.txt | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/portable/CMakeLists.txt b/portable/CMakeLists.txt
index 819e2c116..553397589 100644
--- a/portable/CMakeLists.txt
+++ b/portable/CMakeLists.txt
@@ -798,8 +798,8 @@ target_include_directories(freertos_kernel_port_headers INTERFACE
     $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CA9>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CA9>
 
     # ARMv8-A ports for GCC
-    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_AARCH64>:${CMAKE_CURRENT_LIST_DIR}/GCC/Arm_AARCH64>
-    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_AARCH64_SRE>:${CMAKE_CURRENT_LIST_DIR}/GCC/Arm_AARCH64_SRE>
+    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_AARCH64>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_AARCH64>
+    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_AARCH64_SRE>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_AARCH64_SRE>
 
     # ARMv6-M port for GCC
     $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM0>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM0>

From e6d8308fde19860e4b86c2dfd7a404ff0304a237 Mon Sep 17 00:00:00 2001
From: Tomas Galbicka <151615323+TomasGalbickaNXP@users.noreply.github.com>
Date: Thu, 29 Aug 2024 10:36:33 +0200
Subject: [PATCH 317/424] GCC: ARM_CM0: Fix L6286E error on Keil MDK (#1131)

Change the .b instruction to .bx with higher range to solve error
reported by MDK descibed bellow.

Fix:
Error: L6286E: Relocation #REL:0 in portasm.o(.text.SVC_Handler) with respect to vPortSVCHandler_C. Value(0x1a04) out of range(-0x800 - 0x7fe) for (R_ARM_THM_JUMP11)

Compiler: Keil MDK ARMClang 6.22.0

https://developer.arm.com/documentation/ka002847/latest/
https://developer.arm.com/documentation/dui0496/m/Linker-Errors-and-Warnings/List-of-the-armlink-error-and-warning-messages

Signed-off-by: Tomas Galbicka <tomas.galbicka@nxp.com>
---
 portable/GCC/ARM_CM0/portasm.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/portable/GCC/ARM_CM0/portasm.c b/portable/GCC/ARM_CM0/portasm.c
index be1500ef0..179a71546 100644
--- a/portable/GCC/ARM_CM0/portasm.c
+++ b/portable/GCC/ARM_CM0/portasm.c
@@ -472,7 +472,8 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "     ldr r3, =%1                \n"
             "     cmp r2, r3                 \n"
             "     beq system_call_exit       \n"
-            "     b vPortSVCHandler_C        \n"
+            "     ldr r3, =vPortSVCHandler_C \n"
+            "     bx r3                      \n"
             "                                \n"
             " system_call_enter:             \n"
             "    push {lr}                   \n"
@@ -508,11 +509,13 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "                                \n"
             " stacking_used_psp:             \n"
             "    mrs r0, psp                 \n"
-            "    b vPortSVCHandler_C         \n"
+            "    ldr r3, =vPortSVCHandler_C  \n"
+            "    bx r3                       \n"
             "                                \n"
             " stacking_used_msp:             \n"
             "    mrs r0, msp                 \n"
-            "    b vPortSVCHandler_C         \n"
+            "    ldr r3, =vPortSVCHandler_C  \n"
+            "    bx r3                       \n"
             "                                \n"
             " .align 4                       \n"
         );

From 6dab25ae4e2d4212b76dec01737fcdb2d257af50 Mon Sep 17 00:00:00 2001
From: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Date: Thu, 29 Aug 2024 21:21:35 +0530
Subject: [PATCH 318/424] Pend a yield in portPRE_TASK_DELETE_HOOK (#1132)

When a task deletes itself, it calls portPRE_TASK_DELETE_HOOK which
translates to vPortCloseRunningThread on the Windows port.
vPortCloseRunningThread never returns and as a result,
taskYIELD_WITHIN_API in vTaskDelete does not get called. As a result,
the next task is not scheduled when configUSE_PREEMPTION is set to 0.

This change records that a yield is pending so that the next tick
interrupt switches out the task that was deleted.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 portable/MSVC-MingW/port.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/portable/MSVC-MingW/port.c b/portable/MSVC-MingW/port.c
index 7c34aabd6..c6ee941c8 100644
--- a/portable/MSVC-MingW/port.c
+++ b/portable/MSVC-MingW/port.c
@@ -547,6 +547,20 @@ void vPortCloseRunningThread( void * pvTaskToDelete,
     /* This is called from a critical section, which must be exited before the
      * thread stops. */
     taskEXIT_CRITICAL();
+
+    /* Record that a yield is pending so that the next tick interrupt switches
+     * out this thread regardless of the value of configUSE_PREEMPTION. This is
+     * needed when a task deletes itself - the taskYIELD_WITHIN_API within
+     * vTaskDelete does not get called because this function never returns. If
+     * we do not pend portINTERRUPT_YIELD here, the next task is not scheduled
+     * when configUSE_PREEMPTION is set to 0. */
+    if( pvInterruptEventMutex != NULL )
+    {
+        WaitForSingleObject( pvInterruptEventMutex, INFINITE );
+        ulPendingInterrupts |= ( 1 << portINTERRUPT_YIELD );
+        ReleaseMutex( pvInterruptEventMutex );
+    }
+
     CloseHandle( pxThreadState->pvYieldEvent );
     ExitThread( 0 );
 }

From 4a3c9204ff47c80ab64181e6a06ea62a90083d7d Mon Sep 17 00:00:00 2001
From: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Date: Mon, 2 Sep 2024 15:46:23 +0000
Subject: [PATCH 319/424] Update comment in the example for declaration of
 xTimerReset (#1133)

* Update comment in the example for declaration of xTimerReset

* Fix formatting
---
 include/timers.h | 23 +++++++++++++----------
 1 file changed, 13 insertions(+), 10 deletions(-)

diff --git a/include/timers.h b/include/timers.h
index 19d55d535..7d99d3536 100644
--- a/include/timers.h
+++ b/include/timers.h
@@ -737,14 +737,18 @@ TaskHandle_t xTimerGetTimerDaemonTaskHandle( void ) PRIVILEGED_FUNCTION;
  * // The key press event handler.
  * void vKeyPressEventHandler( char cKey )
  * {
- *     // Ensure the LCD back-light is on, then reset the timer that is
- *     // responsible for turning the back-light off after 5 seconds of
- *     // key inactivity.  Wait 10 ticks for the command to be successfully sent
- *     // if it cannot be sent immediately.
- *     vSetBacklightState( BACKLIGHT_ON );
- *     if( xTimerReset( xBacklightTimer, 100 ) != pdPASS )
+ *     // Reset the timer that is responsible for turning the back-light off after
+ *     // 5 seconds of key inactivity. Wait 10 ticks for the command to be
+ *     // successfully sent if it cannot be sent immediately.
+ *     if( xTimerReset( xBacklightTimer, 10 ) == pdPASS )
  *     {
- *         // The reset command was not executed successfully.  Take appropriate
+ *        // Turn on the LCD back-light. It will be turned off in the
+ *        // vBacklightTimerCallback after 5 seconds of key inactivity.
+ *        vSetBacklightState( BACKLIGHT_ON );
+ *      }
+ *     else
+ *     {
+ *         // The reset command was not executed successfully. Take appropriate
  *         // action here.
  *     }
  *
@@ -753,16 +757,15 @@ TaskHandle_t xTimerGetTimerDaemonTaskHandle( void ) PRIVILEGED_FUNCTION;
  *
  * void main( void )
  * {
- * int32_t x;
  *
  *     // Create then start the one-shot timer that is responsible for turning
  *     // the back-light off if no keys are pressed within a 5 second period.
  *     xBacklightTimer = xTimerCreate( "BacklightTimer",           // Just a text name, not used by the kernel.
- *                                     ( 5000 / portTICK_PERIOD_MS), // The timer period in ticks.
+ *                                     pdMS_TO_TICKS( 5000 ),      // The timer period in ticks.
  *                                     pdFALSE,                    // The timer is a one-shot timer.
  *                                     0,                          // The id is not used by the callback so can take any value.
  *                                     vBacklightTimerCallback     // The callback function that switches the LCD back-light off.
- *                                   );
+ *                                    );
  *
  *     if( xBacklightTimer == NULL )
  *     {

From a045081f73533ca972f0d9f8e23bf3ea61709b7d Mon Sep 17 00:00:00 2001
From: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Date: Wed, 4 Sep 2024 09:31:42 +0000
Subject: [PATCH 320/424] Update config macro for xTaskGetCurrentTaskHandle
 (#1136)

---
 portable/Common/mpu_wrappers.c    | 4 ++--
 portable/Common/mpu_wrappers_v2.c | 4 ++--
 tasks.c                           | 4 ++--
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/portable/Common/mpu_wrappers.c b/portable/Common/mpu_wrappers.c
index be1a9954d..43c7da475 100644
--- a/portable/Common/mpu_wrappers.c
+++ b/portable/Common/mpu_wrappers.c
@@ -834,7 +834,7 @@
     #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */
 /*-----------------------------------------------------------*/
 
-    #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
+    #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_RECURSIVE_MUTEXES == 1 ) )
         TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* FREERTOS_SYSTEM_CALL */
         {
             TaskHandle_t xReturn;
@@ -856,7 +856,7 @@
 
             return xReturn;
         }
-    #endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
+    #endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_RECURSIVE_MUTEXES == 1 ) ) */
 /*-----------------------------------------------------------*/
 
     #if ( INCLUDE_xTaskGetSchedulerState == 1 )
diff --git a/portable/Common/mpu_wrappers_v2.c b/portable/Common/mpu_wrappers_v2.c
index 96f7734f1..c5bbdc318 100644
--- a/portable/Common/mpu_wrappers_v2.c
+++ b/portable/Common/mpu_wrappers_v2.c
@@ -1172,7 +1172,7 @@
     #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */
 /*-----------------------------------------------------------*/
 
-    #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
+    #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_RECURSIVE_MUTEXES == 1 ) )
 
         TaskHandle_t MPU_xTaskGetCurrentTaskHandleImpl( void ) PRIVILEGED_FUNCTION;
 
@@ -1197,7 +1197,7 @@
             return xExternalTaskHandle;
         }
 
-    #endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
+    #endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_RECURSIVE_MUTEXES == 1 ) ) */
 /*-----------------------------------------------------------*/
 
     #if ( INCLUDE_xTaskGetSchedulerState == 1 )
diff --git a/tasks.c b/tasks.c
index 8002d316a..483ad29e6 100644
--- a/tasks.c
+++ b/tasks.c
@@ -6486,7 +6486,7 @@ static void prvResetNextTaskUnblockTime( void )
 }
 /*-----------------------------------------------------------*/
 
-#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) || ( configNUMBER_OF_CORES > 1 )
+#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_RECURSIVE_MUTEXES == 1 ) ) || ( configNUMBER_OF_CORES > 1 )
 
     #if ( configNUMBER_OF_CORES == 1 )
         TaskHandle_t xTaskGetCurrentTaskHandle( void )
@@ -6544,7 +6544,7 @@ static void prvResetNextTaskUnblockTime( void )
         return xReturn;
     }
 
-#endif /* ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
+#endif /* ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_RECURSIVE_MUTEXES == 1 ) ) */
 /*-----------------------------------------------------------*/
 
 #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )

From 93e8199078fdde7785582d2458aec672ef4e9be2 Mon Sep 17 00:00:00 2001
From: Ryzee119 <wendland@live.com.au>
Date: Mon, 9 Sep 2024 16:54:38 +0930
Subject: [PATCH 321/424] Fix IA32 compilation with common IRQ entry disabled
 (#1137)

---
 portable/GCC/IA32_flat/port.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/portable/GCC/IA32_flat/port.c b/portable/GCC/IA32_flat/port.c
index 207f6076b..682cce951 100644
--- a/portable/GCC/IA32_flat/port.c
+++ b/portable/GCC/IA32_flat/port.c
@@ -666,11 +666,13 @@ static BaseType_t prvCheckValidityOfVectorNumber( uint32_t ulVectorNumber )
         /* In use by FreeRTOS. */
         xReturn = pdFAIL;
     }
+#if ( configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1 )
     else if( xInterruptHandlerTable[ ulVectorNumber ] != NULL )
     {
         /* Already in use by the application. */
         xReturn = pdFAIL;
     }
+#endif  /* configUSE_COMMON_INTERRUPT_ENTRY_POINT */
     else
     {
         xReturn = pdPASS;

From 310ace5dd0a7391124448d56a309e7e1b6926f10 Mon Sep 17 00:00:00 2001
From: Oliver Mueller <olstyle@gmx.de>
Date: Tue, 10 Sep 2024 07:46:40 +0200
Subject: [PATCH 322/424] Add configuration include to secure_heap.c (#1141)

Add configuration include to secure_heap.c

Enables actually changing the size of the secure heal
---
 portable/ARMv8M/secure/heap/secure_heap.c   | 3 +++
 portable/GCC/ARM_CM23/secure/secure_heap.c  | 3 +++
 portable/GCC/ARM_CM33/secure/secure_heap.c  | 3 +++
 portable/GCC/ARM_CM35P/secure/secure_heap.c | 3 +++
 portable/GCC/ARM_CM55/secure/secure_heap.c  | 3 +++
 portable/GCC/ARM_CM85/secure/secure_heap.c  | 3 +++
 portable/IAR/ARM_CM23/secure/secure_heap.c  | 3 +++
 portable/IAR/ARM_CM33/secure/secure_heap.c  | 3 +++
 portable/IAR/ARM_CM35P/secure/secure_heap.c | 3 +++
 portable/IAR/ARM_CM55/secure/secure_heap.c  | 3 +++
 portable/IAR/ARM_CM85/secure/secure_heap.c  | 3 +++
 11 files changed, 33 insertions(+)

diff --git a/portable/ARMv8M/secure/heap/secure_heap.c b/portable/ARMv8M/secure/heap/secure_heap.c
index f77320ed2..896b53e2d 100644
--- a/portable/ARMv8M/secure/heap/secure_heap.c
+++ b/portable/ARMv8M/secure/heap/secure_heap.c
@@ -29,6 +29,9 @@
 /* Standard includes. */
 #include <stdint.h>
 
+/* Configuration includes. */
+#include "FreeRTOSConfig.h"
+
 /* Secure context heap includes. */
 #include "secure_heap.h"
 
diff --git a/portable/GCC/ARM_CM23/secure/secure_heap.c b/portable/GCC/ARM_CM23/secure/secure_heap.c
index f77320ed2..896b53e2d 100644
--- a/portable/GCC/ARM_CM23/secure/secure_heap.c
+++ b/portable/GCC/ARM_CM23/secure/secure_heap.c
@@ -29,6 +29,9 @@
 /* Standard includes. */
 #include <stdint.h>
 
+/* Configuration includes. */
+#include "FreeRTOSConfig.h"
+
 /* Secure context heap includes. */
 #include "secure_heap.h"
 
diff --git a/portable/GCC/ARM_CM33/secure/secure_heap.c b/portable/GCC/ARM_CM33/secure/secure_heap.c
index f77320ed2..896b53e2d 100644
--- a/portable/GCC/ARM_CM33/secure/secure_heap.c
+++ b/portable/GCC/ARM_CM33/secure/secure_heap.c
@@ -29,6 +29,9 @@
 /* Standard includes. */
 #include <stdint.h>
 
+/* Configuration includes. */
+#include "FreeRTOSConfig.h"
+
 /* Secure context heap includes. */
 #include "secure_heap.h"
 
diff --git a/portable/GCC/ARM_CM35P/secure/secure_heap.c b/portable/GCC/ARM_CM35P/secure/secure_heap.c
index f77320ed2..896b53e2d 100644
--- a/portable/GCC/ARM_CM35P/secure/secure_heap.c
+++ b/portable/GCC/ARM_CM35P/secure/secure_heap.c
@@ -29,6 +29,9 @@
 /* Standard includes. */
 #include <stdint.h>
 
+/* Configuration includes. */
+#include "FreeRTOSConfig.h"
+
 /* Secure context heap includes. */
 #include "secure_heap.h"
 
diff --git a/portable/GCC/ARM_CM55/secure/secure_heap.c b/portable/GCC/ARM_CM55/secure/secure_heap.c
index f77320ed2..896b53e2d 100644
--- a/portable/GCC/ARM_CM55/secure/secure_heap.c
+++ b/portable/GCC/ARM_CM55/secure/secure_heap.c
@@ -29,6 +29,9 @@
 /* Standard includes. */
 #include <stdint.h>
 
+/* Configuration includes. */
+#include "FreeRTOSConfig.h"
+
 /* Secure context heap includes. */
 #include "secure_heap.h"
 
diff --git a/portable/GCC/ARM_CM85/secure/secure_heap.c b/portable/GCC/ARM_CM85/secure/secure_heap.c
index f77320ed2..896b53e2d 100644
--- a/portable/GCC/ARM_CM85/secure/secure_heap.c
+++ b/portable/GCC/ARM_CM85/secure/secure_heap.c
@@ -29,6 +29,9 @@
 /* Standard includes. */
 #include <stdint.h>
 
+/* Configuration includes. */
+#include "FreeRTOSConfig.h"
+
 /* Secure context heap includes. */
 #include "secure_heap.h"
 
diff --git a/portable/IAR/ARM_CM23/secure/secure_heap.c b/portable/IAR/ARM_CM23/secure/secure_heap.c
index f77320ed2..896b53e2d 100644
--- a/portable/IAR/ARM_CM23/secure/secure_heap.c
+++ b/portable/IAR/ARM_CM23/secure/secure_heap.c
@@ -29,6 +29,9 @@
 /* Standard includes. */
 #include <stdint.h>
 
+/* Configuration includes. */
+#include "FreeRTOSConfig.h"
+
 /* Secure context heap includes. */
 #include "secure_heap.h"
 
diff --git a/portable/IAR/ARM_CM33/secure/secure_heap.c b/portable/IAR/ARM_CM33/secure/secure_heap.c
index f77320ed2..896b53e2d 100644
--- a/portable/IAR/ARM_CM33/secure/secure_heap.c
+++ b/portable/IAR/ARM_CM33/secure/secure_heap.c
@@ -29,6 +29,9 @@
 /* Standard includes. */
 #include <stdint.h>
 
+/* Configuration includes. */
+#include "FreeRTOSConfig.h"
+
 /* Secure context heap includes. */
 #include "secure_heap.h"
 
diff --git a/portable/IAR/ARM_CM35P/secure/secure_heap.c b/portable/IAR/ARM_CM35P/secure/secure_heap.c
index f77320ed2..896b53e2d 100644
--- a/portable/IAR/ARM_CM35P/secure/secure_heap.c
+++ b/portable/IAR/ARM_CM35P/secure/secure_heap.c
@@ -29,6 +29,9 @@
 /* Standard includes. */
 #include <stdint.h>
 
+/* Configuration includes. */
+#include "FreeRTOSConfig.h"
+
 /* Secure context heap includes. */
 #include "secure_heap.h"
 
diff --git a/portable/IAR/ARM_CM55/secure/secure_heap.c b/portable/IAR/ARM_CM55/secure/secure_heap.c
index f77320ed2..896b53e2d 100644
--- a/portable/IAR/ARM_CM55/secure/secure_heap.c
+++ b/portable/IAR/ARM_CM55/secure/secure_heap.c
@@ -29,6 +29,9 @@
 /* Standard includes. */
 #include <stdint.h>
 
+/* Configuration includes. */
+#include "FreeRTOSConfig.h"
+
 /* Secure context heap includes. */
 #include "secure_heap.h"
 
diff --git a/portable/IAR/ARM_CM85/secure/secure_heap.c b/portable/IAR/ARM_CM85/secure/secure_heap.c
index f77320ed2..896b53e2d 100644
--- a/portable/IAR/ARM_CM85/secure/secure_heap.c
+++ b/portable/IAR/ARM_CM85/secure/secure_heap.c
@@ -29,6 +29,9 @@
 /* Standard includes. */
 #include <stdint.h>
 
+/* Configuration includes. */
+#include "FreeRTOSConfig.h"
+
 /* Secure context heap includes. */
 #include "secure_heap.h"
 

From 40031cfc4ce5e6ead4276a30c687aa9d73b84398 Mon Sep 17 00:00:00 2001
From: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Date: Wed, 11 Sep 2024 11:36:58 +0530
Subject: [PATCH 323/424] Update upload-artifact GH action's version (#1145)

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 .github/workflows/unit-tests.yml | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/.github/workflows/unit-tests.yml b/.github/workflows/unit-tests.yml
index b6d2960b6..3591436a4 100644
--- a/.github/workflows/unit-tests.yml
+++ b/.github/workflows/unit-tests.yml
@@ -45,12 +45,12 @@ jobs:
         fail_ci_if_error: false
         verbose: false
     - name: Archive code coverage data
-      uses: actions/upload-artifact@v2
+      uses: actions/upload-artifact@v4
       with:
         name: coverage-data
         path: FreeRTOS/Test/CMock/build/cmock_test*
     - name: Archive code coverage html report
-      uses: actions/upload-artifact@v2
+      uses: actions/upload-artifact@v4
       with:
         name: coverage-report
         path: FreeRTOS/Test/CMock/build/coverage

From d806240dfe6b9951ff33f9c83b79d299108ac960 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=E3=81=82=E3=81=8F?= <alleteam@gmail.com>
Date: Wed, 11 Sep 2024 14:56:16 +0100
Subject: [PATCH 324/424] Task: fix compiler warning for architectures that
 does not define portARMV8M_MINOR_VERSION (#1144)

---
 include/task.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/task.h b/include/task.h
index f3e0d496b..60535254c 100644
--- a/include/task.h
+++ b/include/task.h
@@ -65,7 +65,7 @@
 #define tskMPU_REGION_EXECUTE_NEVER                   ( 1U << 2U )
 #define tskMPU_REGION_NORMAL_MEMORY                   ( 1U << 3U )
 #define tskMPU_REGION_DEVICE_MEMORY                   ( 1U << 4U )
-#if ( portARMV8M_MINOR_VERSION >= 1 )
+#if defined( portARMV8M_MINOR_VERSION ) && ( portARMV8M_MINOR_VERSION >= 1 )
     #define tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER    ( 1U << 5U )
 #endif /* portARMV8M_MINOR_VERSION >= 1 */
 

From d3052f1f50c416ba30e8036410ee79765d5fd4a5 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=E3=81=82=E3=81=8F?= <alleteam@gmail.com>
Date: Wed, 11 Sep 2024 18:37:08 +0100
Subject: [PATCH 325/424] Event Groups: snapshot xEventGroupSetBits returning
 value while in vTaskSuspendAll (#1143)

Event Groups: snapshot xEventGroupSetBits returning value while in
vTaskSuspendAll. Fixes uxEventBits dereference after event group
deleted by higher priority thread.
---
 event_groups.c         |  9 ++++++---
 include/event_groups.h | 13 +++++--------
 2 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/event_groups.c b/event_groups.c
index f54a37a8f..6a2ba0761 100644
--- a/event_groups.c
+++ b/event_groups.c
@@ -551,7 +551,7 @@
         ListItem_t * pxNext;
         ListItem_t const * pxListEnd;
         List_t const * pxList;
-        EventBits_t uxBitsToClear = 0, uxBitsWaitedFor, uxControlBits;
+        EventBits_t uxBitsToClear = 0, uxBitsWaitedFor, uxControlBits, uxReturnBits;
         EventGroup_t * pxEventBits = xEventGroup;
         BaseType_t xMatchFound = pdFALSE;
 
@@ -635,12 +635,15 @@
             /* Clear any bits that matched when the eventCLEAR_EVENTS_ON_EXIT_BIT
              * bit was set in the control word. */
             pxEventBits->uxEventBits &= ~uxBitsToClear;
+
+            /* Snapshot resulting bits. */
+            uxReturnBits = pxEventBits->uxEventBits;
         }
         ( void ) xTaskResumeAll();
 
-        traceRETURN_xEventGroupSetBits( pxEventBits->uxEventBits );
+        traceRETURN_xEventGroupSetBits( uxReturnBits );
 
-        return pxEventBits->uxEventBits;
+        return uxReturnBits;
     }
 /*-----------------------------------------------------------*/
 
diff --git a/include/event_groups.h b/include/event_groups.h
index 1461a1113..9e6348687 100644
--- a/include/event_groups.h
+++ b/include/event_groups.h
@@ -483,14 +483,11 @@ EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup,
  * and bit 0 set uxBitsToSet to 0x09.
  *
  * @return The value of the event group at the time the call to
- * xEventGroupSetBits() returns.  There are two reasons why the returned value
- * might have the bits specified by the uxBitsToSet parameter cleared.  First,
- * if setting a bit results in a task that was waiting for the bit leaving the
- * blocked state then it is possible the bit will be cleared automatically
- * (see the xClearBitOnExit parameter of xEventGroupWaitBits()).  Second, any
- * unblocked (or otherwise Ready state) task that has a priority above that of
- * the task that called xEventGroupSetBits() will execute and may change the
- * event group value before the call to xEventGroupSetBits() returns.
+ * xEventGroupSetBits() returns.  Returned value might have the bits specified
+ * by the uxBitsToSet parameter cleared if setting a bit results in a task
+ * that was waiting for the bit leaving the blocked state then it is possible
+ * the bit will be cleared automatically (see the xClearBitOnExit parameter
+ * of xEventGroupWaitBits()).
  *
  * Example usage:
  * @code{c}

From 61440fc664894c96e757aabc415e6dbd55fd836b Mon Sep 17 00:00:00 2001
From: Saiiijchan <49641410+Saiiijchan@users.noreply.github.com>
Date: Thu, 19 Sep 2024 13:06:52 +0800
Subject: [PATCH 326/424] Refine heap_5 heap protector (#1146)

Add configVALIDATE_HEAP_BLOCK_POINTER on heap_5

heap_5 is used for multiple separated memory spaces. In the
previous implementation, it only verifies the highest and
lowest addresses. A pointer may not be within heap regions,
but is still located between the highest and lowest addressed.

Add maco configVALIDATE_HEAP_BLOCK_POINTER to provide
customized heap block pointers detection based on the settings
of heap regions.

Signed-off-by: wangfei_chen <wangfei_chen@realsil.com.cn>
---
 portable/MemMang/heap_5.c | 19 +++++++++++++------
 1 file changed, 13 insertions(+), 6 deletions(-)

diff --git a/portable/MemMang/heap_5.c b/portable/MemMang/heap_5.c
index fccf79825..0d9598cf1 100644
--- a/portable/MemMang/heap_5.c
+++ b/portable/MemMang/heap_5.c
@@ -129,12 +129,19 @@
  * heapVALIDATE_BLOCK_POINTER assert. */
     #define heapPROTECT_BLOCK_POINTER( pxBlock )    ( ( BlockLink_t * ) ( ( ( portPOINTER_SIZE_TYPE ) ( pxBlock ) ) ^ xHeapCanary ) )
 
-/* Assert that a heap block pointer is within the heap bounds. */
-    #define heapVALIDATE_BLOCK_POINTER( pxBlock )                       \
-    configASSERT( ( pucHeapHighAddress != NULL ) &&                     \
-                  ( pucHeapLowAddress != NULL ) &&                      \
-                  ( ( uint8_t * ) ( pxBlock ) >= pucHeapLowAddress ) && \
-                  ( ( uint8_t * ) ( pxBlock ) < pucHeapHighAddress ) )
+/* Assert that a heap block pointer is within the heap bounds.
+ * Setting configVALIDATE_HEAP_BLOCK_POINTER to 1 enables customized heap block pointers
+ * protection on heap_5. */
+    #ifndef configVALIDATE_HEAP_BLOCK_POINTER
+        #define heapVALIDATE_BLOCK_POINTER( pxBlock )                           \
+            configASSERT( ( pucHeapHighAddress != NULL ) &&                     \
+                          ( pucHeapLowAddress != NULL ) &&                      \
+                          ( ( uint8_t * ) ( pxBlock ) >= pucHeapLowAddress ) && \
+                          ( ( uint8_t * ) ( pxBlock ) < pucHeapHighAddress ) )
+    #else /* ifndef configVALIDATE_HEAP_BLOCK_POINTER */
+        #define heapVALIDATE_BLOCK_POINTER( pxBlock )                           \
+            configVALIDATE_HEAP_BLOCK_POINTER( pxBlock )
+    #endif /* configVALIDATE_HEAP_BLOCK_POINTER */
 
 #else /* if ( configENABLE_HEAP_PROTECTOR == 1 ) */
 

From 9788e7e46a2739ff88f345822d736898b5d1c0cc Mon Sep 17 00:00:00 2001
From: Florian La Roche <florian.laroche@gmail.com>
Date: Fri, 20 Sep 2024 19:19:09 +0200
Subject: [PATCH 327/424] modernize ARM assembler syntax (#1148)

modernize ARM assembler syntax

Signed-off-by: Florian La Roche <Florian.LaRoche@gmail.com>
---
 portable/GCC/ARM_CM3/port.c      | 12 +++++-------
 portable/GCC/ARM_CM3_MPU/port.c  | 16 +++++-----------
 portable/GCC/ARM_CM4F/port.c     | 12 +++++-------
 portable/GCC/ARM_CM4_MPU/port.c  | 16 +++++-----------
 portable/GCC/ARM_CM7/r0p1/port.c | 12 +++++-------
 5 files changed, 25 insertions(+), 43 deletions(-)

diff --git a/portable/GCC/ARM_CM3/port.c b/portable/GCC/ARM_CM3/port.c
index ba7a718ab..f2a6a1e83 100644
--- a/portable/GCC/ARM_CM3/port.c
+++ b/portable/GCC/ARM_CM3/port.c
@@ -228,8 +228,8 @@ static void prvTaskExitError( void )
 void vPortSVCHandler( void )
 {
     __asm volatile (
-        "   ldr r3, pxCurrentTCBConst2      \n" /* Restore the context. */
-        "   ldr r1, [r3]                    \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
+        "   ldr r3, =pxCurrentTCB           \n" /* Restore the context. */
+        "   ldr r1, [r3]                    \n" /* Get the pxCurrentTCB address. */
         "   ldr r0, [r1]                    \n" /* The first item in pxCurrentTCB is the task top of stack. */
         "   ldmia r0!, {r4-r11}             \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
         "   msr psp, r0                     \n" /* Restore the task stack pointer. */
@@ -239,8 +239,7 @@ void vPortSVCHandler( void )
         "   orr r14, #0xd                   \n"
         "   bx r14                          \n"
         "                                   \n"
-        "   .align 4                        \n"
-        "pxCurrentTCBConst2: .word pxCurrentTCB             \n"
+        "   .ltorg                          \n"
         );
 }
 /*-----------------------------------------------------------*/
@@ -462,7 +461,7 @@ void xPortPendSVHandler( void )
         "   mrs r0, psp                         \n"
         "   isb                                 \n"
         "                                       \n"
-        "   ldr r3, pxCurrentTCBConst           \n" /* Get the location of the current TCB. */
+        "   ldr r3, =pxCurrentTCB               \n" /* Get the location of the current TCB. */
         "   ldr r2, [r3]                        \n"
         "                                       \n"
         "   stmdb r0!, {r4-r11}                 \n" /* Save the remaining registers. */
@@ -483,8 +482,7 @@ void xPortPendSVHandler( void )
         "   isb                                 \n"
         "   bx r14                              \n"
         "                                       \n"
-        "   .align 4                            \n"
-        "pxCurrentTCBConst: .word pxCurrentTCB  \n"
+        "   .ltorg                              \n"
         ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
     );
 }
diff --git a/portable/GCC/ARM_CM3_MPU/port.c b/portable/GCC/ARM_CM3_MPU/port.c
index bbe00b61f..cc91c5611 100644
--- a/portable/GCC/ARM_CM3_MPU/port.c
+++ b/portable/GCC/ARM_CM3_MPU/port.c
@@ -695,7 +695,7 @@ static void prvRestoreContextOfFirstTask( void )
         " msr msp, r0                           \n" /* Set the msp back to the start of the stack. */
         "                                       \n"
         /*------------ Program MPU. ------------ */
-        " ldr r3, pxCurrentTCBConst2            \n" /* r3 = pxCurrentTCBConst2. */
+        " ldr r3, =pxCurrentTCB                 \n" /* r3 = =pxCurrentTCB. */
         " ldr r2, [r3]                          \n" /* r2 = pxCurrentTCB. */
         " add r2, r2, #4                        \n" /* r2 = Second item in the TCB which is xMPUSettings. */
         "                                       \n"
@@ -716,7 +716,7 @@ static void prvRestoreContextOfFirstTask( void )
         " dsb                                   \n" /* Force memory writes before continuing. */
         "                                       \n"
         /*---------- Restore Context. ---------- */
-        " ldr r3, pxCurrentTCBConst2            \n" /* r3 = pxCurrentTCBConst2. */
+        " ldr r3, =pxCurrentTCB                 \n" /* r3 = =pxCurrentTCB. */
         " ldr r2, [r3]                          \n" /* r2 = pxCurrentTCB. */
         " ldr r1, [r2]                          \n" /* r1 = Location of saved context in TCB. */
         "                                       \n"
@@ -732,8 +732,6 @@ static void prvRestoreContextOfFirstTask( void )
         " bx lr                                 \n"
         "                                       \n"
         " .ltorg                                \n" /* Assemble current literal pool to avoid offset-out-of-bound errors with lto. */
-        " .align 4                              \n"
-        "pxCurrentTCBConst2: .word pxCurrentTCB \n"
     );
 }
 /*-----------------------------------------------------------*/
@@ -988,7 +986,7 @@ void xPortPendSVHandler( void )
 
     __asm volatile
     (
-        " ldr r3, pxCurrentTCBConst             \n" /* r3 = pxCurrentTCBConst. */
+        " ldr r3, =pxCurrentTCB                 \n" /* r3 = =pxCurrentTCB. */
         " ldr r2, [r3]                          \n" /* r2 = pxCurrentTCB. */
         " ldr r1, [r2]                          \n" /* r1 = Location where the context should be saved. */
         "                                       \n"
@@ -1012,7 +1010,7 @@ void xPortPendSVHandler( void )
         " msr basepri, r0                       \n"
         "                                       \n"
         /*------------ Program MPU. ------------ */
-        " ldr r3, pxCurrentTCBConst             \n" /* r3 = pxCurrentTCBConst. */
+        " ldr r3, =pxCurrentTCB                 \n" /* r3 = =pxCurrentTCB. */
         " ldr r2, [r3]                          \n" /* r2 = pxCurrentTCB. */
         " add r2, r2, #4                        \n" /* r2 = Second item in the TCB which is xMPUSettings. */
         "                                       \n"
@@ -1033,7 +1031,7 @@ void xPortPendSVHandler( void )
         " dsb                                   \n" /* Force memory writes before continuing. */
         "                                       \n"
         /*---------- Restore Context. ---------- */
-        " ldr r3, pxCurrentTCBConst             \n" /* r3 = pxCurrentTCBConst. */
+        " ldr r3, =pxCurrentTCB                 \n" /* r3 = =pxCurrentTCB. */
         " ldr r2, [r3]                          \n" /* r2 = pxCurrentTCB. */
         " ldr r1, [r2]                          \n" /* r1 = Location of saved context in TCB. */
         "                                       \n"
@@ -1047,8 +1045,6 @@ void xPortPendSVHandler( void )
         " bx lr                                 \n"
         "                                       \n"
         " .ltorg                                \n" /* Assemble current literal pool to avoid offset-out-of-bound errors with lto. */
-        " .align 4                              \n"
-        "pxCurrentTCBConst: .word pxCurrentTCB  \n"
         ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
     );
 }
@@ -1207,8 +1203,6 @@ BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
         "   movne r0, #0                            \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
         "   moveq r0, #1                            \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
         "   bx lr                                   \n" /* Return. */
-        "                                           \n"
-        "   .align 4                                \n"
         ::: "r0", "memory"
     );
 }
diff --git a/portable/GCC/ARM_CM4F/port.c b/portable/GCC/ARM_CM4F/port.c
index c4194f767..e6b481b1d 100644
--- a/portable/GCC/ARM_CM4F/port.c
+++ b/portable/GCC/ARM_CM4F/port.c
@@ -260,8 +260,8 @@ static void prvTaskExitError( void )
 void vPortSVCHandler( void )
 {
     __asm volatile (
-        "   ldr r3, pxCurrentTCBConst2      \n" /* Restore the context. */
-        "   ldr r1, [r3]                    \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
+        "   ldr r3, =pxCurrentTCB           \n" /* Restore the context. */
+        "   ldr r1, [r3]                    \n" /* Get the pxCurrentTCB address. */
         "   ldr r0, [r1]                    \n" /* The first item in pxCurrentTCB is the task top of stack. */
         "   ldmia r0!, {r4-r11, r14}        \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
         "   msr psp, r0                     \n" /* Restore the task stack pointer. */
@@ -270,8 +270,7 @@ void vPortSVCHandler( void )
         "   msr basepri, r0                 \n"
         "   bx r14                          \n"
         "                                   \n"
-        "   .align 4                        \n"
-        "pxCurrentTCBConst2: .word pxCurrentTCB             \n"
+        "   .ltorg                          \n"
         );
 }
 /*-----------------------------------------------------------*/
@@ -511,7 +510,7 @@ void xPortPendSVHandler( void )
         "   mrs r0, psp                         \n"
         "   isb                                 \n"
         "                                       \n"
-        "   ldr r3, pxCurrentTCBConst           \n" /* Get the location of the current TCB. */
+        "   ldr r3, =pxCurrentTCB               \n" /* Get the location of the current TCB. */
         "   ldr r2, [r3]                        \n"
         "                                       \n"
         "   tst r14, #0x10                      \n" /* Is the task using the FPU context?  If so, push high vfp registers. */
@@ -552,8 +551,7 @@ void xPortPendSVHandler( void )
         "                                       \n"
         "   bx r14                              \n"
         "                                       \n"
-        "   .align 4                            \n"
-        "pxCurrentTCBConst: .word pxCurrentTCB  \n"
+        "   .ltorg                              \n"
         ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
     );
 }
diff --git a/portable/GCC/ARM_CM4_MPU/port.c b/portable/GCC/ARM_CM4_MPU/port.c
index 30a65c423..d6a4931b5 100644
--- a/portable/GCC/ARM_CM4_MPU/port.c
+++ b/portable/GCC/ARM_CM4_MPU/port.c
@@ -761,7 +761,7 @@ static void prvRestoreContextOfFirstTask( void )
         " msr msp, r0                           \n" /* Set the msp back to the start of the stack. */
         "                                       \n"
         /*------------ Program MPU. ------------ */
-        " ldr r3, pxCurrentTCBConst2            \n" /* r3 = pxCurrentTCBConst2. */
+        " ldr r3, =pxCurrentTCB                 \n" /* r3 = =pxCurrentTCB. */
         " ldr r2, [r3]                          \n" /* r2 = pxCurrentTCB. */
         " add r2, r2, #4                        \n" /* r2 = Second item in the TCB which is xMPUSettings. */
         "                                       \n"
@@ -789,7 +789,7 @@ static void prvRestoreContextOfFirstTask( void )
         " dsb                                   \n" /* Force memory writes before continuing. */
         "                                       \n"
         /*---------- Restore Context. ---------- */
-        " ldr r3, pxCurrentTCBConst2            \n" /* r3 = pxCurrentTCBConst2. */
+        " ldr r3, =pxCurrentTCB                 \n" /* r3 = =pxCurrentTCB. */
         " ldr r2, [r3]                          \n" /* r2 = pxCurrentTCB. */
         " ldr r1, [r2]                          \n" /* r1 = Location of saved context in TCB. */
         "                                       \n"
@@ -805,8 +805,6 @@ static void prvRestoreContextOfFirstTask( void )
         " bx lr                                 \n"
         "                                       \n"
         " .ltorg                                \n" /* Assemble current literal pool to avoid offset-out-of-bound errors with lto. */
-        " .align 4                              \n"
-        " pxCurrentTCBConst2: .word pxCurrentTCB\n"
     );
 }
 /*-----------------------------------------------------------*/
@@ -1084,7 +1082,7 @@ void xPortPendSVHandler( void )
 
     __asm volatile
     (
-        " ldr r3, pxCurrentTCBConst             \n" /* r3 = pxCurrentTCBConst. */
+        " ldr r3, =pxCurrentTCB                 \n" /* r3 = =pxCurrentTCB. */
         " ldr r2, [r3]                          \n" /* r2 = pxCurrentTCB. */
         " ldr r1, [r2]                          \n" /* r1 = Location where the context should be saved. */
         "                                       \n"
@@ -1122,7 +1120,7 @@ void xPortPendSVHandler( void )
         " msr basepri, r0                       \n"
         "                                       \n"
         /*------------ Program MPU. ------------ */
-        " ldr r3, pxCurrentTCBConst             \n" /* r3 = pxCurrentTCBConst. */
+        " ldr r3, =pxCurrentTCB                 \n" /* r3 = =pxCurrentTCB. */
         " ldr r2, [r3]                          \n" /* r2 = pxCurrentTCB. */
         " add r2, r2, #4                        \n" /* r2 = Second item in the TCB which is xMPUSettings. */
         "                                       \n"
@@ -1150,7 +1148,7 @@ void xPortPendSVHandler( void )
         " dsb                                   \n" /* Force memory writes before continuing. */
         "                                       \n"
         /*---------- Restore Context. ---------- */
-        " ldr r3, pxCurrentTCBConst             \n" /* r3 = pxCurrentTCBConst. */
+        " ldr r3, =pxCurrentTCB                 \n" /* r3 = =pxCurrentTCB. */
         " ldr r2, [r3]                          \n" /* r2 = pxCurrentTCB. */
         " ldr r1, [r2]                          \n" /* r1 = Location of saved context in TCB. */
         "                                       \n"
@@ -1170,8 +1168,6 @@ void xPortPendSVHandler( void )
         " bx lr                                 \n"
         "                                       \n"
         " .ltorg                                \n" /* Assemble the current literal pool to avoid offset-out-of-bound errors with lto. */
-        " .align 4                              \n"
-        " pxCurrentTCBConst: .word pxCurrentTCB \n"
         ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
     );
 }
@@ -1349,8 +1345,6 @@ BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
         "   movne r0, #0                            \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
         "   moveq r0, #1                            \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
         "   bx lr                                   \n" /* Return. */
-        "                                           \n"
-        "   .align 4                                \n"
         ::: "r0", "memory"
     );
 }
diff --git a/portable/GCC/ARM_CM7/r0p1/port.c b/portable/GCC/ARM_CM7/r0p1/port.c
index 766f0242d..6586980f4 100644
--- a/portable/GCC/ARM_CM7/r0p1/port.c
+++ b/portable/GCC/ARM_CM7/r0p1/port.c
@@ -254,8 +254,8 @@ static void prvTaskExitError( void )
 void vPortSVCHandler( void )
 {
     __asm volatile (
-        "   ldr r3, pxCurrentTCBConst2      \n" /* Restore the context. */
-        "   ldr r1, [r3]                    \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
+        "   ldr r3, =pxCurrentTCB           \n" /* Restore the context. */
+        "   ldr r1, [r3]                    \n" /* Get the pxCurrentTCB address. */
         "   ldr r0, [r1]                    \n" /* The first item in pxCurrentTCB is the task top of stack. */
         "   ldmia r0!, {r4-r11, r14}        \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
         "   msr psp, r0                     \n" /* Restore the task stack pointer. */
@@ -264,8 +264,7 @@ void vPortSVCHandler( void )
         "   msr basepri, r0                 \n"
         "   bx r14                          \n"
         "                                   \n"
-        "   .align 4                        \n"
-        "pxCurrentTCBConst2: .word pxCurrentTCB             \n"
+        "   .ltorg                          \n"
         );
 }
 /*-----------------------------------------------------------*/
@@ -499,7 +498,7 @@ void xPortPendSVHandler( void )
         "   mrs r0, psp                         \n"
         "   isb                                 \n"
         "                                       \n"
-        "   ldr r3, pxCurrentTCBConst           \n" /* Get the location of the current TCB. */
+        "   ldr r3, =pxCurrentTCB               \n" /* Get the location of the current TCB. */
         "   ldr r2, [r3]                        \n"
         "                                       \n"
         "   tst r14, #0x10                      \n" /* Is the task using the FPU context?  If so, push high vfp registers. */
@@ -542,8 +541,7 @@ void xPortPendSVHandler( void )
         "                                       \n"
         "   bx r14                              \n"
         "                                       \n"
-        "   .align 4                            \n"
-        "pxCurrentTCBConst: .word pxCurrentTCB  \n"
+        "   .ltorg                              \n"
         ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
     );
 }

From c0bfbb96924f76285b147bd970cfbdea55d83e96 Mon Sep 17 00:00:00 2001
From: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Date: Mon, 23 Sep 2024 10:39:29 +0530
Subject: [PATCH 328/424] Remove error for 16 MPU resgion from IAR ports
 (#1149)

Support for 16 MPU regions was added to Cortex-M33, M35P, M55 and M85
ports was added but the compile time error check was not removed. This
results in compilation error when 16 MPU regions are used. This PR
removes the not needed compile time error check.

It was reported here - https://forums.freertos.org/t/cortex-m55-and-16-region-mpu-support/21470.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h | 5 -----
 .../ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h  | 5 -----
 .../ARMv8M/non_secure/portable/IAR/ARM_CM35P/portmacro.h     | 4 ----
 portable/ARMv8M/non_secure/portable/IAR/ARM_CM55/portmacro.h | 5 -----
 portable/ARMv8M/non_secure/portable/IAR/ARM_CM85/portmacro.h | 5 -----
 portable/IAR/ARM_CM33/non_secure/portmacro.h                 | 5 -----
 portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h             | 5 -----
 portable/IAR/ARM_CM35P/non_secure/portmacro.h                | 4 ----
 portable/IAR/ARM_CM35P_NTZ/non_secure/portmacro.h            | 4 ----
 portable/IAR/ARM_CM55/non_secure/portmacro.h                 | 5 -----
 portable/IAR/ARM_CM55_NTZ/non_secure/portmacro.h             | 5 -----
 portable/IAR/ARM_CM85/non_secure/portmacro.h                 | 5 -----
 portable/IAR/ARM_CM85_NTZ/non_secure/portmacro.h             | 5 -----
 13 files changed, 62 deletions(-)

diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h
index a2a301f00..0f7d100df 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h
@@ -54,11 +54,6 @@
 #define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
-#if ( configTOTAL_MPU_REGIONS == 16 )
-    #error 16 MPU regions are not yet supported for this port.
-#endif
-/*-----------------------------------------------------------*/
-
 /* ARMv8-M common port configurations. */
 #include "portmacrocommon.h"
 /*-----------------------------------------------------------*/
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h
index f0d5f2b9c..0f7d100df 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h
@@ -58,16 +58,11 @@
 #include "portmacrocommon.h"
 /*-----------------------------------------------------------*/
 
-#if ( configTOTAL_MPU_REGIONS == 16 )
-    #error 16 MPU regions are not yet supported for this port.
-#endif
-
 #ifndef configENABLE_MVE
     #define configENABLE_MVE    0
 #elif( configENABLE_MVE != 0 )
     #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M33.
 #endif
-
 /*-----------------------------------------------------------*/
 
 /**
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM35P/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM35P/portmacro.h
index 633da3a6d..0ad1009b6 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM35P/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM35P/portmacro.h
@@ -58,10 +58,6 @@
 #include "portmacrocommon.h"
 /*-----------------------------------------------------------*/
 
-#if ( configTOTAL_MPU_REGIONS == 16 )
-    #error 16 MPU regions are not yet supported for this port.
-#endif
-
 #ifndef configENABLE_MVE
     #define configENABLE_MVE    0
 #elif( configENABLE_MVE != 0 )
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM55/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM55/portmacro.h
index 95b179413..597af66fa 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM55/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM55/portmacro.h
@@ -63,11 +63,6 @@
 #include "portmacrocommon.h"
 /*-----------------------------------------------------------*/
 
-#if ( configTOTAL_MPU_REGIONS == 16 )
-    #error 16 MPU regions are not yet supported for this port.
-#endif
-/*-----------------------------------------------------------*/
-
 /**
  * @brief Critical section management.
  */
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM85/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM85/portmacro.h
index efde68dc2..ff5c9895d 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM85/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM85/portmacro.h
@@ -63,11 +63,6 @@
 #include "portmacrocommon.h"
 /*-----------------------------------------------------------*/
 
-#if ( configTOTAL_MPU_REGIONS == 16 )
-    #error 16 MPU regions are not yet supported for this port.
-#endif
-/*-----------------------------------------------------------*/
-
 /**
  * @brief Critical section management.
  */
diff --git a/portable/IAR/ARM_CM33/non_secure/portmacro.h b/portable/IAR/ARM_CM33/non_secure/portmacro.h
index a2a301f00..0f7d100df 100644
--- a/portable/IAR/ARM_CM33/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM33/non_secure/portmacro.h
@@ -54,11 +54,6 @@
 #define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
-#if ( configTOTAL_MPU_REGIONS == 16 )
-    #error 16 MPU regions are not yet supported for this port.
-#endif
-/*-----------------------------------------------------------*/
-
 /* ARMv8-M common port configurations. */
 #include "portmacrocommon.h"
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h b/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h
index f0d5f2b9c..0f7d100df 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h
@@ -58,16 +58,11 @@
 #include "portmacrocommon.h"
 /*-----------------------------------------------------------*/
 
-#if ( configTOTAL_MPU_REGIONS == 16 )
-    #error 16 MPU regions are not yet supported for this port.
-#endif
-
 #ifndef configENABLE_MVE
     #define configENABLE_MVE    0
 #elif( configENABLE_MVE != 0 )
     #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M33.
 #endif
-
 /*-----------------------------------------------------------*/
 
 /**
diff --git a/portable/IAR/ARM_CM35P/non_secure/portmacro.h b/portable/IAR/ARM_CM35P/non_secure/portmacro.h
index 633da3a6d..0ad1009b6 100644
--- a/portable/IAR/ARM_CM35P/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM35P/non_secure/portmacro.h
@@ -58,10 +58,6 @@
 #include "portmacrocommon.h"
 /*-----------------------------------------------------------*/
 
-#if ( configTOTAL_MPU_REGIONS == 16 )
-    #error 16 MPU regions are not yet supported for this port.
-#endif
-
 #ifndef configENABLE_MVE
     #define configENABLE_MVE    0
 #elif( configENABLE_MVE != 0 )
diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacro.h b/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacro.h
index 633da3a6d..0ad1009b6 100644
--- a/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacro.h
@@ -58,10 +58,6 @@
 #include "portmacrocommon.h"
 /*-----------------------------------------------------------*/
 
-#if ( configTOTAL_MPU_REGIONS == 16 )
-    #error 16 MPU regions are not yet supported for this port.
-#endif
-
 #ifndef configENABLE_MVE
     #define configENABLE_MVE    0
 #elif( configENABLE_MVE != 0 )
diff --git a/portable/IAR/ARM_CM55/non_secure/portmacro.h b/portable/IAR/ARM_CM55/non_secure/portmacro.h
index 95b179413..597af66fa 100644
--- a/portable/IAR/ARM_CM55/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM55/non_secure/portmacro.h
@@ -63,11 +63,6 @@
 #include "portmacrocommon.h"
 /*-----------------------------------------------------------*/
 
-#if ( configTOTAL_MPU_REGIONS == 16 )
-    #error 16 MPU regions are not yet supported for this port.
-#endif
-/*-----------------------------------------------------------*/
-
 /**
  * @brief Critical section management.
  */
diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/portmacro.h b/portable/IAR/ARM_CM55_NTZ/non_secure/portmacro.h
index 95b179413..597af66fa 100644
--- a/portable/IAR/ARM_CM55_NTZ/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM55_NTZ/non_secure/portmacro.h
@@ -63,11 +63,6 @@
 #include "portmacrocommon.h"
 /*-----------------------------------------------------------*/
 
-#if ( configTOTAL_MPU_REGIONS == 16 )
-    #error 16 MPU regions are not yet supported for this port.
-#endif
-/*-----------------------------------------------------------*/
-
 /**
  * @brief Critical section management.
  */
diff --git a/portable/IAR/ARM_CM85/non_secure/portmacro.h b/portable/IAR/ARM_CM85/non_secure/portmacro.h
index efde68dc2..ff5c9895d 100644
--- a/portable/IAR/ARM_CM85/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM85/non_secure/portmacro.h
@@ -63,11 +63,6 @@
 #include "portmacrocommon.h"
 /*-----------------------------------------------------------*/
 
-#if ( configTOTAL_MPU_REGIONS == 16 )
-    #error 16 MPU regions are not yet supported for this port.
-#endif
-/*-----------------------------------------------------------*/
-
 /**
  * @brief Critical section management.
  */
diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/portmacro.h b/portable/IAR/ARM_CM85_NTZ/non_secure/portmacro.h
index efde68dc2..ff5c9895d 100644
--- a/portable/IAR/ARM_CM85_NTZ/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM85_NTZ/non_secure/portmacro.h
@@ -63,11 +63,6 @@
 #include "portmacrocommon.h"
 /*-----------------------------------------------------------*/
 
-#if ( configTOTAL_MPU_REGIONS == 16 )
-    #error 16 MPU regions are not yet supported for this port.
-#endif
-/*-----------------------------------------------------------*/
-
 /**
  * @brief Critical section management.
  */

From de7c014e92ec3dd07c91ac741ddd17a63d4c4676 Mon Sep 17 00:00:00 2001
From: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Date: Mon, 30 Sep 2024 11:20:04 +0530
Subject: [PATCH 329/424] Change the cast from UBaseType_t to size_t (#1153)

This was causing problem for 8-bit ports.

This was reported here - https://github.com/FreeRTOS/FreeRTOS-Kernel/issues/1151

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 queue.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/queue.c b/queue.c
index 1a14c743d..34cf17ba6 100644
--- a/queue.c
+++ b/queue.c
@@ -513,7 +513,7 @@ BaseType_t xQueueGenericReset( QueueHandle_t xQueue,
             /* Check for multiplication overflow. */
             ( ( SIZE_MAX / uxQueueLength ) >= uxItemSize ) &&
             /* Check for addition overflow. */
-            ( ( UBaseType_t ) ( SIZE_MAX - sizeof( Queue_t ) ) >= ( uxQueueLength * uxItemSize ) ) )
+            ( ( SIZE_MAX - sizeof( Queue_t ) ) >= ( size_t ) ( uxQueueLength * uxItemSize ) ) )
         {
             /* Allocate enough space to hold the maximum number of items that
              * can be in the queue at any time.  It is valid for uxItemSize to be

From 1cb80429612506952f4d2ac5b3b70273c41cb7a5 Mon Sep 17 00:00:00 2001
From: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Date: Mon, 30 Sep 2024 11:41:52 +0530
Subject: [PATCH 330/424] Update MPU prototypes (#1150)

Add missing MPU prototypes

This commit address the following issues with MPU prototypes:
1. Fix the decorator according to which MPU wrapper is used.
2. Add the missing prototypes for v1.
3. Add the corresponding mapping to mpu_wrappers.h.
4. Update MPU v1 wrappers for vTaskList and vTaskGetRunTimeStats.

This was reported here - https://forums.freertos.org/t/cortex-m55-and-16-region-mpu-support/21470/5.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 include/mpu_prototypes.h       | 215 ++++++++++++++++++++++++---------
 include/mpu_wrappers.h         |  17 ++-
 portable/Common/mpu_wrappers.c |  14 ++-
 3 files changed, 180 insertions(+), 66 deletions(-)

diff --git a/include/mpu_prototypes.h b/include/mpu_prototypes.h
index d51547cd6..cacadc6c6 100644
--- a/include/mpu_prototypes.h
+++ b/include/mpu_prototypes.h
@@ -136,25 +136,59 @@ BaseType_t MPU_xTaskGetSchedulerState( void ) FREERTOS_SYSTEM_CALL;
 /* Privileged only wrappers for Task APIs. These are needed so that
  * the application can use opaque handles maintained in mpu_wrappers.c
  * with all the APIs. */
-BaseType_t MPU_xTaskCreate( TaskFunction_t pxTaskCode,
-                            const char * const pcName,
-                            const configSTACK_DEPTH_TYPE uxStackDepth,
-                            void * const pvParameters,
-                            UBaseType_t uxPriority,
-                            TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION;
-TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode,
-                                    const char * const pcName,
-                                    const configSTACK_DEPTH_TYPE uxStackDepth,
-                                    void * const pvParameters,
-                                    UBaseType_t uxPriority,
-                                    StackType_t * const puxStackBuffer,
-                                    StaticTask_t * const pxTaskBuffer ) PRIVILEGED_FUNCTION;
-void MPU_vTaskDelete( TaskHandle_t xTaskToDelete ) PRIVILEGED_FUNCTION;
-void MPU_vTaskPrioritySet( TaskHandle_t xTask,
-                           UBaseType_t uxNewPriority ) PRIVILEGED_FUNCTION;
-TaskHandle_t MPU_xTaskGetHandle( const char * pcNameToQuery ) PRIVILEGED_FUNCTION;
-BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask,
-                                             void * pvParameter ) PRIVILEGED_FUNCTION;
+#if ( configUSE_MPU_WRAPPERS_V1 == 1 )
+
+    BaseType_t MPU_xTaskCreate( TaskFunction_t pxTaskCode,
+                                const char * const pcName,
+                                const configSTACK_DEPTH_TYPE uxStackDepth,
+                                void * const pvParameters,
+                                UBaseType_t uxPriority,
+                                TaskHandle_t * const pxCreatedTask ) FREERTOS_SYSTEM_CALL;
+    TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode,
+                                        const char * const pcName,
+                                        const configSTACK_DEPTH_TYPE uxStackDepth,
+                                        void * const pvParameters,
+                                        UBaseType_t uxPriority,
+                                        StackType_t * const puxStackBuffer,
+                                        StaticTask_t * const pxTaskBuffer ) FREERTOS_SYSTEM_CALL;
+    void MPU_vTaskDelete( TaskHandle_t xTaskToDelete ) FREERTOS_SYSTEM_CALL;
+    void MPU_vTaskPrioritySet( TaskHandle_t xTask,
+                               UBaseType_t uxNewPriority ) FREERTOS_SYSTEM_CALL;
+    TaskHandle_t MPU_xTaskGetHandle( const char * pcNameToQuery ) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask,
+                                                 void * pvParameter ) FREERTOS_SYSTEM_CALL;
+    void MPU_vTaskGetRunTimeStatistics( char * pcWriteBuffer,
+                                        size_t uxBufferLength ) FREERTOS_SYSTEM_CALL;
+    void MPU_vTaskListTasks( char * pcWriteBuffer,
+                             size_t uxBufferLength ) FREERTOS_SYSTEM_CALL;
+    void MPU_vTaskSuspendAll( void ) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xTaskResumeAll( void ) FREERTOS_SYSTEM_CALL;
+
+#else /* #if ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+
+    BaseType_t MPU_xTaskCreate( TaskFunction_t pxTaskCode,
+                                const char * const pcName,
+                                const configSTACK_DEPTH_TYPE uxStackDepth,
+                                void * const pvParameters,
+                                UBaseType_t uxPriority,
+                                TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION;
+    TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode,
+                                        const char * const pcName,
+                                        const configSTACK_DEPTH_TYPE uxStackDepth,
+                                        void * const pvParameters,
+                                        UBaseType_t uxPriority,
+                                        StackType_t * const puxStackBuffer,
+                                        StaticTask_t * const pxTaskBuffer ) PRIVILEGED_FUNCTION;
+    void MPU_vTaskDelete( TaskHandle_t xTaskToDelete ) PRIVILEGED_FUNCTION;
+    void MPU_vTaskPrioritySet( TaskHandle_t xTask,
+                               UBaseType_t uxNewPriority ) PRIVILEGED_FUNCTION;
+    TaskHandle_t MPU_xTaskGetHandle( const char * pcNameToQuery ) PRIVILEGED_FUNCTION;
+    BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask,
+                                                 void * pvParameter ) PRIVILEGED_FUNCTION;
+
+#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+
 char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION;
 BaseType_t MPU_xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition,
                                       TaskHandle_t * pxCreatedTask ) PRIVILEGED_FUNCTION;
@@ -215,28 +249,58 @@ uint8_t MPU_ucQueueGetQueueType( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
 /* Privileged only wrappers for Queue APIs. These are needed so that
  * the application can use opaque handles maintained in mpu_wrappers.c
  * with all the APIs. */
-void MPU_vQueueDelete( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
-QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
-QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType,
-                                           StaticQueue_t * pxStaticQueue ) PRIVILEGED_FUNCTION;
-QueueHandle_t MPU_xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount,
-                                                 const UBaseType_t uxInitialCount ) PRIVILEGED_FUNCTION;
-QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount,
-                                                       const UBaseType_t uxInitialCount,
-                                                       StaticQueue_t * pxStaticQueue ) PRIVILEGED_FUNCTION;
-QueueHandle_t MPU_xQueueGenericCreate( const UBaseType_t uxQueueLength,
-                                       const UBaseType_t uxItemSize,
-                                       const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
-QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength,
-                                             const UBaseType_t uxItemSize,
-                                             uint8_t * pucQueueStorage,
-                                             StaticQueue_t * pxStaticQueue,
-                                             const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
-QueueSetHandle_t MPU_xQueueCreateSet( const UBaseType_t uxEventQueueLength ) PRIVILEGED_FUNCTION;
-BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore,
-                                    QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
-BaseType_t MPU_xQueueGenericReset( QueueHandle_t xQueue,
-                                   BaseType_t xNewQueue ) PRIVILEGED_FUNCTION;
+#if ( configUSE_MPU_WRAPPERS_V1 == 1 )
+
+    void MPU_vQueueDelete( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+    QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
+    QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType,
+                                               StaticQueue_t * pxStaticQueue ) FREERTOS_SYSTEM_CALL;
+    QueueHandle_t MPU_xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount,
+                                                     const UBaseType_t uxInitialCount ) FREERTOS_SYSTEM_CALL;
+    QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount,
+                                                           const UBaseType_t uxInitialCount,
+                                                           StaticQueue_t * pxStaticQueue ) FREERTOS_SYSTEM_CALL;
+    QueueHandle_t MPU_xQueueGenericCreate( const UBaseType_t uxQueueLength,
+                                           const UBaseType_t uxItemSize,
+                                           const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
+    QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength,
+                                                 const UBaseType_t uxItemSize,
+                                                 uint8_t * pucQueueStorage,
+                                                 StaticQueue_t * pxStaticQueue,
+                                                 const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
+    QueueSetHandle_t MPU_xQueueCreateSet( const UBaseType_t uxEventQueueLength ) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                                        QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueueGenericReset( QueueHandle_t xQueue,
+                                       BaseType_t xNewQueue ) FREERTOS_SYSTEM_CALL;
+
+#else /* #if ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+
+    void MPU_vQueueDelete( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+    QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
+    QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType,
+                                               StaticQueue_t * pxStaticQueue ) PRIVILEGED_FUNCTION;
+    QueueHandle_t MPU_xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount,
+                                                     const UBaseType_t uxInitialCount ) PRIVILEGED_FUNCTION;
+    QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount,
+                                                           const UBaseType_t uxInitialCount,
+                                                           StaticQueue_t * pxStaticQueue ) PRIVILEGED_FUNCTION;
+    QueueHandle_t MPU_xQueueGenericCreate( const UBaseType_t uxQueueLength,
+                                           const UBaseType_t uxItemSize,
+                                           const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
+    QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength,
+                                                 const UBaseType_t uxItemSize,
+                                                 uint8_t * pucQueueStorage,
+                                                 StaticQueue_t * pxStaticQueue,
+                                                 const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
+    QueueSetHandle_t MPU_xQueueCreateSet( const UBaseType_t uxEventQueueLength ) PRIVILEGED_FUNCTION;
+    BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                                        QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+    BaseType_t MPU_xQueueGenericReset( QueueHandle_t xQueue,
+                                       BaseType_t xNewQueue ) PRIVILEGED_FUNCTION;
+
+#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+
 BaseType_t MPU_xQueueGenericGetStaticBuffers( QueueHandle_t xQueue,
                                               uint8_t ** ppucQueueStorage,
                                               StaticQueue_t ** ppxStaticQueue ) PRIVILEGED_FUNCTION;
@@ -318,14 +382,25 @@ EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
     UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) FREERTOS_SYSTEM_CALL;
     void MPU_vEventGroupSetNumber( void * xEventGroup,
                                    UBaseType_t uxEventGroupNumber ) FREERTOS_SYSTEM_CALL;
-#endif /* ( configUSE_TRACE_FACILITY == 1 )*/
+#endif /* #if ( configUSE_TRACE_FACILITY == 1 ) */
 
 /* Privileged only wrappers for Event Group APIs. These are needed so that
  * the application can use opaque handles maintained in mpu_wrappers.c
  * with all the APIs. */
-EventGroupHandle_t MPU_xEventGroupCreate( void ) PRIVILEGED_FUNCTION;
-EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t * pxEventGroupBuffer ) PRIVILEGED_FUNCTION;
-void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION;
+#if ( configUSE_MPU_WRAPPERS_V1 == 1 )
+
+    EventGroupHandle_t MPU_xEventGroupCreate( void ) FREERTOS_SYSTEM_CALL;
+    EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t * pxEventGroupBuffer ) FREERTOS_SYSTEM_CALL;
+    void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) FREERTOS_SYSTEM_CALL;
+
+#else /* #if ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+
+    EventGroupHandle_t MPU_xEventGroupCreate( void ) PRIVILEGED_FUNCTION;
+    EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t * pxEventGroupBuffer ) PRIVILEGED_FUNCTION;
+    void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION;
+
+#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+
 BaseType_t MPU_xEventGroupGetStaticBuffer( EventGroupHandle_t xEventGroup,
                                            StaticEventGroup_t ** ppxEventGroupBuffer ) PRIVILEGED_FUNCTION;
 BaseType_t MPU_xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup,
@@ -355,20 +430,42 @@ size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuff
 /* Privileged only wrappers for Stream Buffer APIs. These are needed so that
  * the application can use opaque handles maintained in mpu_wrappers.c
  * with all the APIs. */
-StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes,
-                                                     size_t xTriggerLevelBytes,
-                                                     BaseType_t xStreamBufferType,
-                                                     StreamBufferCallbackFunction_t pxSendCompletedCallback,
-                                                     StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) PRIVILEGED_FUNCTION;
-StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
-                                                           size_t xTriggerLevelBytes,
-                                                           BaseType_t xStreamBufferType,
-                                                           uint8_t * const pucStreamBufferStorageArea,
-                                                           StaticStreamBuffer_t * const pxStaticStreamBuffer,
-                                                           StreamBufferCallbackFunction_t pxSendCompletedCallback,
-                                                           StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) PRIVILEGED_FUNCTION;
-void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
-BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+#if ( configUSE_MPU_WRAPPERS_V1 == 1 )
+
+    StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes,
+                                                         size_t xTriggerLevelBytes,
+                                                         BaseType_t xStreamBufferType,
+                                                         StreamBufferCallbackFunction_t pxSendCompletedCallback,
+                                                         StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) FREERTOS_SYSTEM_CALL;
+    StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
+                                                               size_t xTriggerLevelBytes,
+                                                               BaseType_t xStreamBufferType,
+                                                               uint8_t * const pucStreamBufferStorageArea,
+                                                               StaticStreamBuffer_t * const pxStaticStreamBuffer,
+                                                               StreamBufferCallbackFunction_t pxSendCompletedCallback,
+                                                               StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) FREERTOS_SYSTEM_CALL;
+    void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+
+#else /* #if ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+
+    StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes,
+                                                         size_t xTriggerLevelBytes,
+                                                         BaseType_t xStreamBufferType,
+                                                         StreamBufferCallbackFunction_t pxSendCompletedCallback,
+                                                         StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) PRIVILEGED_FUNCTION;
+    StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
+                                                               size_t xTriggerLevelBytes,
+                                                               BaseType_t xStreamBufferType,
+                                                               uint8_t * const pucStreamBufferStorageArea,
+                                                               StaticStreamBuffer_t * const pxStaticStreamBuffer,
+                                                               StreamBufferCallbackFunction_t pxSendCompletedCallback,
+                                                               StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) PRIVILEGED_FUNCTION;
+    void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+    BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+
 BaseType_t MPU_xStreamBufferGetStaticBuffers( StreamBufferHandle_t xStreamBuffers,
                                               uint8_t * ppucStreamBufferStorageArea,
                                               StaticStreamBuffer_t * ppxStaticStreamBuffer ) PRIVILEGED_FUNCTION;
diff --git a/include/mpu_wrappers.h b/include/mpu_wrappers.h
index dea7c0d2a..4513ca996 100644
--- a/include/mpu_wrappers.h
+++ b/include/mpu_wrappers.h
@@ -85,6 +85,18 @@
 /* Privileged only wrappers for Task APIs. These are needed so that
  * the application can use opaque handles maintained in mpu_wrappers.c
  * with all the APIs. */
+        #if ( configUSE_MPU_WRAPPERS_V1 == 1 )
+
+/* These are not needed in v2 because they do not take a task
+ * handle and therefore, no lookup is needed. Needed in v1 because
+ * these are available as system calls in v1. */
+            #define vTaskGetRunTimeStatistics            MPU_vTaskGetRunTimeStatistics
+            #define vTaskListTasks                       MPU_vTaskListTasks
+            #define vTaskSuspendAll                      MPU_vTaskSuspendAll
+            #define xTaskCatchUpTicks                    MPU_xTaskCatchUpTicks
+            #define xTaskResumeAll                       MPU_xTaskResumeAll
+        #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+
         #define xTaskCreate                              MPU_xTaskCreate
         #define xTaskCreateStatic                        MPU_xTaskCreateStatic
         #define vTaskDelete                              MPU_vTaskDelete
@@ -165,11 +177,14 @@
         #define xTimerGetPeriod                   MPU_xTimerGetPeriod
         #define xTimerGetExpiryTime               MPU_xTimerGetExpiryTime
 
+        #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+            #define xTimerGetReloadMode           MPU_xTimerGetReloadMode
+        #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+
 /* Privileged only wrappers for Timer APIs. These are needed so that
  * the application can use opaque handles maintained in mpu_wrappers.c
  * with all the APIs. */
         #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
-            #define xTimerGetReloadMode            MPU_xTimerGetReloadMode
             #define xTimerCreate                   MPU_xTimerCreate
             #define xTimerCreateStatic             MPU_xTimerCreateStatic
             #define xTimerGetStaticBuffer          MPU_xTimerGetStaticBuffer
diff --git a/portable/Common/mpu_wrappers.c b/portable/Common/mpu_wrappers.c
index 43c7da475..e9a890585 100644
--- a/portable/Common/mpu_wrappers.c
+++ b/portable/Common/mpu_wrappers.c
@@ -508,14 +508,15 @@
 /*-----------------------------------------------------------*/
 
     #if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
-        void MPU_vTaskList( char * pcWriteBuffer ) /* FREERTOS_SYSTEM_CALL */
+        void MPU_vTaskListTasks( char * pcWriteBuffer,
+                                 size_t uxBufferLength ) /* FREERTOS_SYSTEM_CALL */
         {
             if( portIS_PRIVILEGED() == pdFALSE )
             {
                 portRAISE_PRIVILEGE();
                 portMEMORY_BARRIER();
 
-                vTaskList( pcWriteBuffer );
+                vTaskListTasks( pcWriteBuffer, uxBufferLength );
                 portMEMORY_BARRIER();
 
                 portRESET_PRIVILEGE();
@@ -523,21 +524,22 @@
             }
             else
             {
-                vTaskList( pcWriteBuffer );
+                vTaskListTasks( pcWriteBuffer, uxBufferLength );
             }
         }
     #endif /* if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
 /*-----------------------------------------------------------*/
 
     #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
-        void MPU_vTaskGetRunTimeStats( char * pcWriteBuffer ) /* FREERTOS_SYSTEM_CALL */
+        void MPU_vTaskGetRunTimeStatistics( char * pcWriteBuffer,
+                                            size_t uxBufferLength ) /* FREERTOS_SYSTEM_CALL */
         {
             if( portIS_PRIVILEGED() == pdFALSE )
             {
                 portRAISE_PRIVILEGE();
                 portMEMORY_BARRIER();
 
-                vTaskGetRunTimeStats( pcWriteBuffer );
+                vTaskGetRunTimeStatistics( pcWriteBuffer, uxBufferLength );
                 portMEMORY_BARRIER();
 
                 portRESET_PRIVILEGE();
@@ -545,7 +547,7 @@
             }
             else
             {
-                vTaskGetRunTimeStats( pcWriteBuffer );
+                vTaskGetRunTimeStatistics( pcWriteBuffer, uxBufferLength );
             }
         }
     #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */

From e81ad46b0e0934142ab31dff4eddcf6b531c1a1d Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Guilherme=20Gi=C3=A1como=20Sim=C3=B5es?=
 <49237332+GuilhermeGiacomoSimoes@users.noreply.github.com>
Date: Mon, 7 Oct 2024 02:07:50 -0300
Subject: [PATCH 331/424] refactor: change methods ENTER|EXIT critical (#1140)

refactor: change methods ENTER|EXIT critical

The read and write of BaseType_t are atomic for a number of ports
and therefore, do not require taskENTER_CRITICAL/taskEXIT_CRITICAL.
This PR introduces portBASE_TYPE_ENTER_CRITICAL and
portBASE_TYPE_EXIT_CRITICAL which default to  taskENTER_CRITICAL
and taskEXIT_CRITICAL. The APIs that read/write BaseType_t are updated
to use these new macros.

The next change would to be to define portBASE_TYPE_ENTER_CRITICAL and
portBASE_TYPE_EXIT_CRITICAL to nothing for ports where BaseType_t
read and write are atomic.

Signed-off-by: guilherme giacomo simoes <trintaeoitogc@gmail.com>
---
 .github/third_party_tools.md |  2 +-
 examples/coverity/README.md  |  2 +-
 include/portable.h           |  8 ++++++++
 queue.c                      |  8 ++++----
 tasks.c                      | 12 ++++++------
 timers.c                     |  8 ++++----
 6 files changed, 24 insertions(+), 16 deletions(-)

diff --git a/.github/third_party_tools.md b/.github/third_party_tools.md
index afe84b257..09bd6d62c 100644
--- a/.github/third_party_tools.md
+++ b/.github/third_party_tools.md
@@ -11,4 +11,4 @@ team.
 | Tool | Website | Getting Started |
 |------|---------|-----------------|
 | Code Sonar | [Link](https://codesecure.com/our-products/codesonar/) | [Link](https://github.com/CodeSecure-SE/FreeRTOS-Kernel/blob/main/examples/codesonar/README.md) |
-| Coverity | [Link](https://www.synopsys.com/software-integrity/security-testing/static-analysis-sast.html) | [Link](../examples/coverity/README.md) |
+| Coverity | [Link](https://www.blackduck.com/static-analysis-tools-sast/coverity.html) | [Link](../examples/coverity/README.md) |
diff --git a/examples/coverity/README.md b/examples/coverity/README.md
index 967f33dca..367c1d6e8 100644
--- a/examples/coverity/README.md
+++ b/examples/coverity/README.md
@@ -1,6 +1,6 @@
 # MISRA Compliance for FreeRTOS-Kernel
 FreeRTOS-Kernel is MISRA C:2012 compliant. This directory contains a project to
-run [Synopsys Coverity](https://www.synopsys.com/software-integrity/security-testing/static-analysis-sast.html)
+run [Synopsys Coverity](https://www.blackduck.com/static-analysis-tools-sast/coverity.html)
 for checking MISRA compliance.
 
 > **Note**
diff --git a/include/portable.h b/include/portable.h
index f7afb6979..1b088b427 100644
--- a/include/portable.h
+++ b/include/portable.h
@@ -85,6 +85,14 @@
     #define portARCH_NAME    NULL
 #endif
 
+#ifndef portBASE_TYPE_ENTER_CRITICAL
+    #define portBASE_TYPE_ENTER_CRITICAL()    taskENTER_CRITICAL()
+#endif
+
+#ifndef portBASE_TYPE_EXIT_CRITICAL
+    #define portBASE_TYPE_EXIT_CRITICAL()    taskEXIT_CRITICAL()
+#endif
+
 #ifndef configSTACK_DEPTH_TYPE
     #define configSTACK_DEPTH_TYPE    StackType_t
 #endif
diff --git a/queue.c b/queue.c
index 34cf17ba6..fd62489f5 100644
--- a/queue.c
+++ b/queue.c
@@ -2202,11 +2202,11 @@ UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue )
 
     configASSERT( xQueue );
 
-    taskENTER_CRITICAL();
+    portBASE_TYPE_ENTER_CRITICAL();
     {
         uxReturn = ( ( Queue_t * ) xQueue )->uxMessagesWaiting;
     }
-    taskEXIT_CRITICAL();
+    portBASE_TYPE_EXIT_CRITICAL();
 
     traceRETURN_uxQueueMessagesWaiting( uxReturn );
 
@@ -2223,11 +2223,11 @@ UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue )
 
     configASSERT( pxQueue );
 
-    taskENTER_CRITICAL();
+    portBASE_TYPE_ENTER_CRITICAL();
     {
         uxReturn = ( UBaseType_t ) ( pxQueue->uxLength - pxQueue->uxMessagesWaiting );
     }
-    taskEXIT_CRITICAL();
+    portBASE_TYPE_EXIT_CRITICAL();
 
     traceRETURN_uxQueueSpacesAvailable( uxReturn );
 
diff --git a/tasks.c b/tasks.c
index 483ad29e6..1be3fca91 100644
--- a/tasks.c
+++ b/tasks.c
@@ -2623,14 +2623,14 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
 
         traceENTER_uxTaskPriorityGet( xTask );
 
-        taskENTER_CRITICAL();
+        portBASE_TYPE_ENTER_CRITICAL();
         {
             /* If null is passed in here then it is the priority of the task
              * that called uxTaskPriorityGet() that is being queried. */
             pxTCB = prvGetTCBFromHandle( xTask );
             uxReturn = pxTCB->uxPriority;
         }
-        taskEXIT_CRITICAL();
+        portBASE_TYPE_EXIT_CRITICAL();
 
         traceRETURN_uxTaskPriorityGet( uxReturn );
 
@@ -2697,14 +2697,14 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
 
         traceENTER_uxTaskBasePriorityGet( xTask );
 
-        taskENTER_CRITICAL();
+        portBASE_TYPE_ENTER_CRITICAL();
         {
             /* If null is passed in here then it is the base priority of the task
              * that called uxTaskBasePriorityGet() that is being queried. */
             pxTCB = prvGetTCBFromHandle( xTask );
             uxReturn = pxTCB->uxBasePriority;
         }
-        taskEXIT_CRITICAL();
+        portBASE_TYPE_EXIT_CRITICAL();
 
         traceRETURN_uxTaskBasePriorityGet( uxReturn );
 
@@ -3040,12 +3040,12 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
 
         traceENTER_vTaskCoreAffinityGet( xTask );
 
-        taskENTER_CRITICAL();
+        portBASE_TYPE_ENTER_CRITICAL();
         {
             pxTCB = prvGetTCBFromHandle( xTask );
             uxCoreAffinityMask = pxTCB->uxCoreAffinityMask;
         }
-        taskEXIT_CRITICAL();
+        portBASE_TYPE_EXIT_CRITICAL();
 
         traceRETURN_vTaskCoreAffinityGet( uxCoreAffinityMask );
 
diff --git a/timers.c b/timers.c
index 4e2a9f61f..03765fe7b 100644
--- a/timers.c
+++ b/timers.c
@@ -601,7 +601,7 @@
         traceENTER_xTimerGetReloadMode( xTimer );
 
         configASSERT( xTimer );
-        taskENTER_CRITICAL();
+        portBASE_TYPE_ENTER_CRITICAL();
         {
             if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) == 0U )
             {
@@ -614,7 +614,7 @@
                 xReturn = pdTRUE;
             }
         }
-        taskEXIT_CRITICAL();
+        portBASE_TYPE_EXIT_CRITICAL();
 
         traceRETURN_xTimerGetReloadMode( xReturn );
 
@@ -1169,7 +1169,7 @@
         configASSERT( xTimer );
 
         /* Is the timer in the list of active timers? */
-        taskENTER_CRITICAL();
+        portBASE_TYPE_ENTER_CRITICAL();
         {
             if( ( pxTimer->ucStatus & tmrSTATUS_IS_ACTIVE ) == 0U )
             {
@@ -1180,7 +1180,7 @@
                 xReturn = pdTRUE;
             }
         }
-        taskEXIT_CRITICAL();
+        portBASE_TYPE_EXIT_CRITICAL();
 
         traceRETURN_xTimerIsTimerActive( xReturn );
 

From f5cf45d86ea161dbc93e1b694690a44048b5c635 Mon Sep 17 00:00:00 2001
From: "K.Kashi" <41608629+KeitaKashima@users.noreply.github.com>
Date: Tue, 15 Oct 2024 14:39:45 +0900
Subject: [PATCH 332/424] [Fixed the Issue] Fixed the Issue#1102 of RL78 of the
 Context switch issue. https://github.com/FreeRTOS/FreeRTOS-Kernel/issues/1102
 (#1157)

---
 portable/GCC/RL78/portmacro.h | 13 ++++++++++++-
 portable/IAR/RL78/portmacro.h | 13 ++++++++++++-
 2 files changed, 24 insertions(+), 2 deletions(-)

diff --git a/portable/GCC/RL78/portmacro.h b/portable/GCC/RL78/portmacro.h
index a91427257..730cf50a3 100644
--- a/portable/GCC/RL78/portmacro.h
+++ b/portable/GCC/RL78/portmacro.h
@@ -106,7 +106,18 @@ typedef unsigned short   UBaseType_t;
 
 /* Task utilities. */
 #define portYIELD()                                       __asm volatile ( "BRK" )
-#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken )    do { if( xHigherPriorityTaskWoken ) vTaskSwitchContext( ); } while( 0 )
+#ifndef configREQUIRE_ASM_ISR_WRAPPER
+    #define configREQUIRE_ASM_ISR_WRAPPER    1
+#endif
+#if( configREQUIRE_ASM_ISR_WRAPPER == 1 )
+    /* You must implement an assembly ISR wrapper (see the below for details) if you need an ISR to cause a context switch.
+     * https://www.freertos.org/Documentation/02-Kernel/03-Supported-devices/04-Demos/Renesas/RTOS_RL78_IAR_Demos#writing-interrupt-service-routines */
+    #define portYIELD_FROM_ISR( xHigherPriorityTaskWoken )    do { if( xHigherPriorityTaskWoken != pdFALSE ) vTaskSwitchContext(); } while( 0 )
+#else
+    /* You must not implement an assembly ISR wrapper even if you need an ISR to cause a context switch.
+     * The portYIELD, which is similar to role of an assembly ISR wrapper, runs only when a context switch is required. */
+    #define portYIELD_FROM_ISR( xHigherPriorityTaskWoken )    do { if( xHigherPriorityTaskWoken != pdFALSE ) portYIELD(); } while( 0 )
+#endif
 #define portNOP()                                         __asm volatile ( "NOP" )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/RL78/portmacro.h b/portable/IAR/RL78/portmacro.h
index a52a6d273..544e76e9e 100644
--- a/portable/IAR/RL78/portmacro.h
+++ b/portable/IAR/RL78/portmacro.h
@@ -130,7 +130,18 @@
 /* Task utilities. */
     #define portNOP()                                         __asm( "NOP" )
     #define portYIELD()                                       __asm( "BRK" )
-    #define portYIELD_FROM_ISR( xHigherPriorityTaskWoken )    do { if( xHigherPriorityTaskWoken ) vTaskSwitchContext( ); } while( 0 )
+    #ifndef configREQUIRE_ASM_ISR_WRAPPER
+        #define configREQUIRE_ASM_ISR_WRAPPER    1
+    #endif
+    #if( configREQUIRE_ASM_ISR_WRAPPER == 1 )
+        /* You must implement an assembly ISR wrapper (see the below for details) if you need an ISR to cause a context switch.
+         * https://www.freertos.org/Documentation/02-Kernel/03-Supported-devices/04-Demos/Renesas/RTOS_RL78_IAR_Demos#writing-interrupt-service-routines */
+        #define portYIELD_FROM_ISR( xHigherPriorityTaskWoken )    do { if( xHigherPriorityTaskWoken != pdFALSE ) vTaskSwitchContext(); } while( 0 )
+    #else
+        /* You must not implement an assembly ISR wrapper even if you need an ISR to cause a context switch.
+         * The portYIELD, which is similar to role of an assembly ISR wrapper, runs only when a context switch is required. */
+        #define portYIELD_FROM_ISR( xHigherPriorityTaskWoken )    do { if( xHigherPriorityTaskWoken != pdFALSE ) portYIELD(); } while( 0 )
+    #endif
 /*-----------------------------------------------------------*/
 
 /* Hardware specifics. */

From 5f3bab1a3242640c6e031d9cfb1be756bd76fb3c Mon Sep 17 00:00:00 2001
From: Ian Thompson <101299961+ianstcdns@users.noreply.github.com>
Date: Tue, 15 Oct 2024 09:02:11 -0700
Subject: [PATCH 333/424] Xtensa support updated and moved to Partner-Supported
 submodules (#1156)

* Xtensa support moved to Partner-Supported ports

Removing legacy Xtensa port; leave README with pointer to latest code

* Updated submodule ThirdParty/FreeRTOS-Kernel-Partner-Supported-Ports
---
 portable/ThirdParty/Partner-Supported-Ports   |    2 +-
 portable/ThirdParty/XCC/Xtensa/Makefile       |   97 -
 portable/ThirdParty/XCC/Xtensa/port.c         |  209 --
 portable/ThirdParty/XCC/Xtensa/portasm.S      |  600 -----
 .../ThirdParty/XCC/Xtensa/portbenchmark.h     |   51 -
 portable/ThirdParty/XCC/Xtensa/portclib.c     |  230 --
 portable/ThirdParty/XCC/Xtensa/portmacro.h    |  216 --
 portable/ThirdParty/XCC/Xtensa/porttrace.h    |   49 -
 .../ThirdParty/XCC/Xtensa/readme_xtensa.txt   |  764 +------
 portable/ThirdParty/XCC/Xtensa/xtensa_api.h   |  127 --
 .../ThirdParty/XCC/Xtensa/xtensa_config.h     |  191 --
 .../ThirdParty/XCC/Xtensa/xtensa_context.S    |  630 ------
 .../ThirdParty/XCC/Xtensa/xtensa_context.h    |  355 ---
 portable/ThirdParty/XCC/Xtensa/xtensa_init.c  |   70 -
 portable/ThirdParty/XCC/Xtensa/xtensa_intr.c  |  137 --
 .../ThirdParty/XCC/Xtensa/xtensa_intr_asm.S   |  183 --
 .../XCC/Xtensa/xtensa_overlay_os_hook.c       |   76 -
 portable/ThirdParty/XCC/Xtensa/xtensa_rtos.h  |  238 --
 portable/ThirdParty/XCC/Xtensa/xtensa_timer.h |  164 --
 .../ThirdParty/XCC/Xtensa/xtensa_vectors.S    | 1924 -----------------
 20 files changed, 7 insertions(+), 6306 deletions(-)
 delete mode 100644 portable/ThirdParty/XCC/Xtensa/Makefile
 delete mode 100644 portable/ThirdParty/XCC/Xtensa/port.c
 delete mode 100644 portable/ThirdParty/XCC/Xtensa/portasm.S
 delete mode 100644 portable/ThirdParty/XCC/Xtensa/portbenchmark.h
 delete mode 100644 portable/ThirdParty/XCC/Xtensa/portclib.c
 delete mode 100644 portable/ThirdParty/XCC/Xtensa/portmacro.h
 delete mode 100644 portable/ThirdParty/XCC/Xtensa/porttrace.h
 delete mode 100644 portable/ThirdParty/XCC/Xtensa/xtensa_api.h
 delete mode 100644 portable/ThirdParty/XCC/Xtensa/xtensa_config.h
 delete mode 100644 portable/ThirdParty/XCC/Xtensa/xtensa_context.S
 delete mode 100644 portable/ThirdParty/XCC/Xtensa/xtensa_context.h
 delete mode 100644 portable/ThirdParty/XCC/Xtensa/xtensa_init.c
 delete mode 100644 portable/ThirdParty/XCC/Xtensa/xtensa_intr.c
 delete mode 100644 portable/ThirdParty/XCC/Xtensa/xtensa_intr_asm.S
 delete mode 100644 portable/ThirdParty/XCC/Xtensa/xtensa_overlay_os_hook.c
 delete mode 100644 portable/ThirdParty/XCC/Xtensa/xtensa_rtos.h
 delete mode 100644 portable/ThirdParty/XCC/Xtensa/xtensa_timer.h
 delete mode 100644 portable/ThirdParty/XCC/Xtensa/xtensa_vectors.S

diff --git a/portable/ThirdParty/Partner-Supported-Ports b/portable/ThirdParty/Partner-Supported-Ports
index dc3afc6e8..abc22103e 160000
--- a/portable/ThirdParty/Partner-Supported-Ports
+++ b/portable/ThirdParty/Partner-Supported-Ports
@@ -1 +1 @@
-Subproject commit dc3afc6e837426b4bda81bbb6cf45bfb6f34c7e9
+Subproject commit abc22103e1e6634b33457d4127bff1ab62f27f90
diff --git a/portable/ThirdParty/XCC/Xtensa/Makefile b/portable/ThirdParty/XCC/Xtensa/Makefile
deleted file mode 100644
index 909cbd2c2..000000000
--- a/portable/ThirdParty/XCC/Xtensa/Makefile
+++ /dev/null
@@ -1,97 +0,0 @@
-### Makefile to build the FreeRTOS library ###
-
-# Build target (options: sim, board)
-
-TARGET      = sim
-SMALL       =
-
-# Tools
-
-CC          = xt-xcc
-AS          = xt-xcc
-AR          = xt-ar
-XT_CORE     = $(patsubst %-params,%,$(notdir $(shell xt-xcc --show-config=core)))
-CONFIGDIR   = $(shell xt-xcc --show-config=config)
-
-# For platform-specific commands
-
-include $(CONFIGDIR)/misc/hostenv.mk
-
-# Source code and build locations
-
-SRCROOT     = $(subst /,$(S),$(CURDIR))
-TSTROOT     = $(abspath $(SRCROOT)$(S)..$(S)..$(S)..$(S)..$(S)..$(S)demos$(S)cadence$(S)sim$(SMALL))
-BLDROOT     = $(TSTROOT)$(S)build
-BLDDIR      = $(BLDROOT)$(S)$(XT_CORE)
-
-FR_SRCDIR   = $(abspath $(SRCROOT)$(S)..$(S)..$(S)..)
-FR_SRCDIR2  = $(FR_SRCDIR)$(S)portable$(S)MemMang
-XT_SRCDIR   = $(SRCROOT)
-
-vpath %.c $(FR_SRCDIR) $(FR_SRCDIR2) $(XT_SRCDIR)
-vpath %.S $(XT_SRCDIR)
-
-# File lists
-
-FR_C_FILES  = $(notdir $(wildcard $(FR_SRCDIR)/*.c)) $(notdir $(wildcard $(FR_SRCDIR2)/*.c))
-XT_C_FILES  = $(notdir $(wildcard $(XT_SRCDIR)/*.c))
-XT_S_FILES  = $(notdir $(wildcard $(XT_SRCDIR)/*.S))
-
-# List of all .o files that will go into the library
-
-LIB_C_O     = $(patsubst %.c,%.o,$(XT_C_FILES) $(FR_C_FILES))
-LIB_S_O     = $(patsubst %.S,%.o,$(XT_S_FILES))
-LIB_O_LIST  = $(addprefix $(BLDDIR)/,$(LIB_C_O) $(LIB_S_O))
-
-# Output files
-
-OSLIB       = $(BLDDIR)$(S)libfreertos.a
-
-# Build options
-
-ifeq ($(TARGET),sim)
-DFLAGS      = -DXT_SIMULATOR
-endif
-ifeq ($(TARGET),board)
-DFLAGS      = -DXT_BOARD
-endif
-
-IFLAGS      = \
-  -I$(FR_SRCDIR)$(S)..$(S)include -I$(FR_SRCDIR)$(S)..$(S)include$(S)private \
-  -I$(XT_SRCDIR) -I$(TSTROOT)$(S)common$(S)config_files -I$(BLDDIR)
-
-CFLAGS      = -O2 -g
-CCFLAGS     = $(CFLAGS) -Wall -mno-coproc -mlongcalls -ffunction-sections -mno-l32r-flix $(DFLAGS)
-ASFLAGS     = $(CCFLAGS)
-
-# Include dependency rules (generated using -MD)
-
--include $(wildcard $(BLDDIR)/*.d)
-
-# Targets
-
-all : mkdir $(OSLIB)
-
-mkdir : $(BLDDIR)/.mkdir
-
-$(BLDDIR)/.mkdir :
-	@$(MKPATH) $(BLDDIR)
-	@echo "" > $@
-	-$(CP) $(CONFIGDIR)/xtensa-elf/include/sys/reent.h $(BLDDIR)/reent.h
-
-$(OSLIB) : $(LIB_O_LIST)
-	$(AR) -rs $@ $^
-
-$(BLDDIR)/%.o : %.c
-	$(CC) $(CCFLAGS) $(IFLAGS) -MD -MF $(subst .o,.d,$@) -c -o $@ $<
-
-$(BLDDIR)/%.o : %.S
-	$(CC) $(ASFLAGS) $(IFLAGS) -MD -MF $(subst .o,.d,$@) -c -o $@ $<
-
-clean :
-	$(RM_R) $(BLDDIR)
-
-clean_all :
-	$(RM_R) $(BLDROOT)
-
-.PHONY : all mkdir clean clean_all
diff --git a/portable/ThirdParty/XCC/Xtensa/port.c b/portable/ThirdParty/XCC/Xtensa/port.c
deleted file mode 100644
index 320b47af2..000000000
--- a/portable/ThirdParty/XCC/Xtensa/port.c
+++ /dev/null
@@ -1,209 +0,0 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-#include <stdlib.h>
-#include <xtensa/config/core.h>
-
-#include "xtensa_rtos.h"
-
-#include "FreeRTOS.h"
-#include "task.h"
-
-
-/* Defined in portasm.h */
-extern void _frxt_tick_timer_init(void);
-
-/* Defined in xtensa_context.S */
-extern void _xt_coproc_init(void);
-
-
-/*-----------------------------------------------------------*/
-
-/* We require the address of the pxCurrentTCB variable, but don't want to know
-any details of its type. */
-typedef void TCB_t;
-extern volatile TCB_t * volatile pxCurrentTCB;
-
-unsigned port_xSchedulerRunning = 0; // Duplicate of inaccessible xSchedulerRunning; needed at startup to avoid counting nesting
-unsigned port_interruptNesting = 0;  // Interrupt nesting level
-
-/*-----------------------------------------------------------*/
-
-// User exception dispatcher when exiting
-void _xt_user_exit(void);
-
-/*
- * Stack initialization
- */
-#if portUSING_MPU_WRAPPERS
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged )
-#else
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-#endif
-{
-    StackType_t * sp;
-    StackType_t * tp;
-    XtExcFrame * frame;
-
-    #if XCHAL_CP_NUM > 0
-        uint32_t * p;
-    #endif
-
-    /* Create interrupt stack frame aligned to 16 byte boundary */
-    sp = ( StackType_t * ) ( ( ( UBaseType_t ) pxTopOfStack - XT_CP_SIZE - XT_STK_FRMSZ ) & ~0xf );
-
-    /* Clear the entire frame (do not use memset() because we don't depend on C library) */
-    for( tp = sp; tp <= pxTopOfStack; ++tp )
-    {
-        *tp = 0;
-    }
-
-    frame = ( XtExcFrame * ) sp;
-
-    /* Explicitly initialize certain saved registers */
-    frame->pc = ( UBaseType_t ) pxCode;             /* task entrypoint                */
-    frame->a0 = 0;                                  /* to terminate GDB backtrace     */
-    frame->a1 = ( UBaseType_t ) sp + XT_STK_FRMSZ;  /* physical top of stack frame    */
-    frame->exit = ( UBaseType_t ) _xt_user_exit;    /* user exception exit dispatcher */
-
-    /* Set initial PS to int level 0, EXCM disabled ('rfe' will enable), user mode. */
-    /* Also set entry point argument parameter. */
-    #ifdef __XTENSA_CALL0_ABI__
-        frame->a2 = ( UBaseType_t ) pvParameters;
-        frame->ps = PS_UM | PS_EXCM;
-    #else
-        /* + for windowed ABI also set WOE and CALLINC (pretend task was 'call4'd). */
-        frame->a6 = ( UBaseType_t ) pvParameters;
-        frame->ps = PS_UM | PS_EXCM | PS_WOE | PS_CALLINC( 1 );
-    #endif
-
-    #ifdef XT_USE_SWPRI
-        /* Set the initial virtual priority mask value to all 1's. */
-        frame->vpri = 0xFFFFFFFF;
-    #endif
-
-    #if XCHAL_CP_NUM > 0
-        /* Init the coprocessor save area (see xtensa_context.h) */
-
-        /* No access to TCB here, so derive indirectly. Stack growth is top to bottom.
-         * //p = (uint32_t *) xMPUSettings->coproc_area;
-         */
-        p = ( uint32_t * ) ( ( ( uint32_t ) pxTopOfStack - XT_CP_SIZE ) & ~0xf );
-        configASSERT( ( uint32_t ) p >= frame->a1 );
-        p[ 0 ] = 0;
-        p[ 1 ] = 0;
-        p[ 2 ] = ( ( ( uint32_t ) p ) + 12 + XCHAL_TOTAL_SA_ALIGN - 1 ) & -XCHAL_TOTAL_SA_ALIGN;
-    #endif
-
-    return sp;
-}
-
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-    /* It is unlikely that the Xtensa port will get stopped.  If required simply
-    disable the tick interrupt here. */
-}
-
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-    // Interrupts are disabled at this point and stack contains PS with enabled interrupts when task context is restored
-
-    #if XCHAL_CP_NUM > 0
-    /* Initialize co-processor management for tasks. Leave CPENABLE alone. */
-    _xt_coproc_init();
-    #endif
-
-    /* Init the tick divisor value */
-    _xt_tick_divisor_init();
-
-    /* Setup the hardware to generate the tick. */
-    _frxt_tick_timer_init();
-
-    #if XT_USE_THREAD_SAFE_CLIB
-    // Init C library
-    vPortClibInit();
-    #endif
-
-    port_xSchedulerRunning = 1;
-
-    // Cannot be directly called from C; never returns
-    __asm__ volatile ("call0    _frxt_dispatch\n");
-
-    /* Should not get here. */
-    return pdTRUE;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortSysTickHandler( void )
-{
-    BaseType_t ret;
-    uint32_t interruptMask;
-
-    portbenchmarkIntLatency();
-
-    /* Interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY must be
-     * disabled before calling xTaskIncrementTick as it access the
-     * kernel lists. */
-    interruptMask = portSET_INTERRUPT_MASK_FROM_ISR();
-    {
-        ret = xTaskIncrementTick();
-    }
-    portCLEAR_INTERRUPT_MASK_FROM_ISR( interruptMask );
-
-    portYIELD_FROM_ISR( ret );
-
-    return ret;
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Used to set coprocessor area in stack. Current hack is to reuse MPU pointer for coprocessor area.
- */
-#if portUSING_MPU_WRAPPERS
-
-    void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
-                                    const struct xMEMORY_REGION * const xRegions,
-                                    StackType_t * pxBottomOfStack,
-                                    configSTACK_DEPTH_TYPE uxStackDepth )
-    {
-        #if XCHAL_CP_NUM > 0
-            xMPUSettings->coproc_area = ( StackType_t * ) ( ( uint32_t ) ( pxBottomOfStack + uxStackDepth - 1 ) );
-            xMPUSettings->coproc_area = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) xMPUSettings->coproc_area ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) );
-            xMPUSettings->coproc_area = ( StackType_t * ) ( ( ( uint32_t ) xMPUSettings->coproc_area - XT_CP_SIZE ) & ~0xf );
-
-            /* NOTE: we cannot initialize the coprocessor save area here because FreeRTOS is going to
-             * clear the stack area after we return. This is done in pxPortInitialiseStack().
-             */
-        #endif
-    }
-#endif /* if portUSING_MPU_WRAPPERS */
diff --git a/portable/ThirdParty/XCC/Xtensa/portasm.S b/portable/ThirdParty/XCC/Xtensa/portasm.S
deleted file mode 100644
index 7475ba510..000000000
--- a/portable/ThirdParty/XCC/Xtensa/portasm.S
+++ /dev/null
@@ -1,600 +0,0 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-#include "xtensa_rtos.h"
-
-#define TOPOFSTACK_OFFS                 0x00    /* StackType_t *pxTopOfStack */
-#define CP_TOPOFSTACK_OFFS              0x04    /* xMPU_SETTINGS.coproc_area */
-
-.extern pxCurrentTCB
-
-
-/*
-*******************************************************************************
-* Interrupt stack. The size of the interrupt stack is determined by the config
-* parameter "configISR_STACK_SIZE" in FreeRTOSConfig.h
-*******************************************************************************
-*/
-    .data
-    .align      16
-    .global     port_IntStack
-port_IntStack:
-    .space      configISR_STACK_SIZE
-port_IntStackTop:
-    .word       0
-port_switch_flag:
-    .word       0
-
-    .text
-/*
-*******************************************************************************
-* _frxt_setup_switch
-* void _frxt_setup_switch(void);
-*
-* Sets an internal flag indicating that a task switch is required on return
-* from interrupt handling.
-*
-*******************************************************************************
-*/
-    .global     _frxt_setup_switch
-    .type       _frxt_setup_switch,@function
-    .align      4
-_frxt_setup_switch:
-
-    ENTRY(16)
-
-    movi    a2, port_switch_flag
-    movi    a3, 1
-    s32i    a3, a2, 0
-
-    RET(16)
-
-/*
-*******************************************************************************
-*                                            _frxt_int_enter
-*                                       void _frxt_int_enter(void)
-*
-* Implements the Xtensa RTOS porting layer's XT_RTOS_INT_ENTER function for
-* freeRTOS. Saves the rest of the interrupt context (not already saved).
-* May only be called from assembly code by the 'call0' instruction, with
-* interrupts disabled.
-* See the detailed description of the XT_RTOS_ENTER macro in xtensa_rtos.h.
-*
-*******************************************************************************
-*/
-    .globl  _frxt_int_enter
-    .type   _frxt_int_enter,@function
-    .align  4
-_frxt_int_enter:
-
-    /* Save a12-13 in the stack frame as required by _xt_context_save. */
-    s32i    a12, a1, XT_STK_A12
-    s32i    a13, a1, XT_STK_A13
-
-    /* Save return address in a safe place (free a0). */
-    mov     a12, a0
-
-    /* Save the rest of the interrupted context (preserves A12-13). */
-    call0   _xt_context_save
-
-    /*
-    Save interrupted task's SP in TCB only if not nesting.
-    Manage nesting directly rather than call the generic IntEnter()
-    (in windowed ABI we can't call a C function here anyway because PS.EXCM is still set).
-    */
-    movi    a2,  port_xSchedulerRunning
-    movi    a3,  port_interruptNesting
-    l32i    a2,  a2, 0                  /* a2 = port_xSchedulerRunning     */
-    beqz    a2,  1f                     /* scheduler not running, no tasks */
-    l32i    a2,  a3, 0                  /* a2 = port_interruptNesting      */
-    addi    a2,  a2, 1                  /* increment nesting count         */
-    s32i    a2,  a3, 0                  /* save nesting count              */
-    bnei    a2,  1, .Lnested            /* !=0 before incr, so nested      */
-
-    movi    a2,  pxCurrentTCB
-    l32i    a2,  a2, 0                  /* a2 = current TCB                */
-    beqz    a2,  1f
-    s32i    a1,  a2, TOPOFSTACK_OFFS    /* pxCurrentTCB->pxTopOfStack = SP */
-    movi    a1,  port_IntStackTop       /* a1 = top of intr stack          */
-
-.Lnested:
-1:
-    mov     a0,  a12                    /* restore return addr and return  */
-    ret
-
-/*
-*******************************************************************************
-*                                            _frxt_int_exit
-*                                       void _frxt_int_exit(void)
-*
-* Implements the Xtensa RTOS porting layer's XT_RTOS_INT_EXIT function for
-* FreeRTOS. If required, calls vPortYieldFromInt() to perform task context
-* switching, restore the (possibly) new task's context, and return to the
-* exit dispatcher saved in the task's stack frame at XT_STK_EXIT.
-* May only be called from assembly code by the 'call0' instruction. Does not
-* return to caller.
-* See the description of the XT_RTOS_ENTER macro in xtensa_rtos.h.
-*
-*******************************************************************************
-*/
-    .globl  _frxt_int_exit
-    .type   _frxt_int_exit,@function
-    .align  4
-_frxt_int_exit:
-
-    movi    a2,  port_xSchedulerRunning
-    movi    a3,  port_interruptNesting
-    rsil    a0,  XCHAL_EXCM_LEVEL       /* lock out interrupts             */
-    l32i    a2,  a2, 0                  /* a2 = port_xSchedulerRunning     */
-    beqz    a2,  .Lnoswitch             /* scheduler not running, no tasks */
-    l32i    a2,  a3, 0                  /* a2 = port_interruptNesting      */
-    addi    a2,  a2, -1                 /* decrement nesting count         */
-    s32i    a2,  a3, 0                  /* save nesting count              */
-    bnez    a2,  .Lnesting              /* !=0 after decr so still nested  */
-
-    movi    a2,  pxCurrentTCB
-    l32i    a2,  a2, 0                  /* a2 = current TCB                */
-    beqz    a2,  1f                     /* no task ? go to dispatcher      */
-    l32i    a1,  a2, TOPOFSTACK_OFFS    /* SP = pxCurrentTCB->pxTopOfStack */
-
-    movi    a2,  port_switch_flag       /* address of switch flag          */
-    l32i    a3,  a2, 0                  /* a3 = port_switch_flag           */
-    beqz    a3,  .Lnoswitch             /* flag = 0 means no switch reqd   */
-    movi    a3,  0
-    s32i    a3,  a2, 0                  /* zero out the flag for next time */
-
-1:
-    /*
-    Call0 ABI callee-saved regs a12-15 need to be saved before possible preemption.
-    However a12-13 were already saved by _frxt_int_enter().
-    */
-    #ifdef __XTENSA_CALL0_ABI__
-    s32i    a14, a1, XT_STK_A14
-    s32i    a15, a1, XT_STK_A15
-    #endif
-
-    #ifdef __XTENSA_CALL0_ABI__
-    call0   vPortYieldFromInt       /* call dispatch inside the function; never returns */
-    #else
-    call4   vPortYieldFromInt       /* this one returns */
-    call0   _frxt_dispatch          /* tail-call dispatcher */
-    /* Never returns here. */
-    #endif
-
-.Lnoswitch:
-    /*
-    If we came here then about to resume the interrupted task.
-    */
-
-.Lnesting:
-    /*
-    We come here only if there was no context switch, that is if this
-    is a nested interrupt, or the interrupted task was not preempted.
-    In either case there's no need to load the SP.
-    */
-
-    /* Restore full context from interrupt stack frame */
-    call0   _xt_context_restore
-
-    /*
-    Must return via the exit dispatcher corresponding to the entrypoint from which
-    this was called. Interruptee's A0, A1, PS, PC are restored and the interrupt
-    stack frame is deallocated in the exit dispatcher.
-    */
-    l32i    a0,  a1, XT_STK_EXIT
-    ret
-
-
-/*
-**********************************************************************************************************
-*                                           _frxt_timer_int
-*                                      void _frxt_timer_int(void)
-*
-* Implements the Xtensa RTOS porting layer's XT_RTOS_TIMER_INT function for FreeRTOS.
-* Called every timer interrupt.
-* Manages the tick timer and calls xPortSysTickHandler() every tick.
-* See the detailed description of the XT_RTOS_ENTER macro in xtensa_rtos.h.
-*
-* Callable from C (obeys ABI conventions). Implemented in assmebly code for performance.
-*
-**********************************************************************************************************
-*/
-    .globl  _frxt_timer_int
-    .type   _frxt_timer_int,@function
-    .align  4
-_frxt_timer_int:
-
-    /*
-    Xtensa timers work by comparing a cycle counter with a preset value.  Once the match occurs
-    an interrupt is generated, and the handler has to set a new cycle count into the comparator.
-    To avoid clock drift due to interrupt latency, the new cycle count is computed from the old,
-    not the time the interrupt was serviced. However if a timer interrupt is ever serviced more
-    than one tick late, it is necessary to process multiple ticks until the new cycle count is
-    in the future, otherwise the next timer interrupt would not occur until after the cycle
-    counter had wrapped (2^32 cycles later).
-
-    do {
-        ticks++;
-        old_ccompare = read_ccompare_i();
-        write_ccompare_i( old_ccompare + divisor );
-        service one tick;
-        diff = read_ccount() - old_ccompare;
-    } while ( diff > divisor );
-    */
-
-    ENTRY(16)
-
-.L_xt_timer_int_catchup:
-
-    /* Update the timer comparator for the next tick. */
-    #ifdef XT_CLOCK_FREQ
-    movi    a2, XT_TICK_DIVISOR         /* a2 = comparator increment          */
-    #else
-    movi    a3, _xt_tick_divisor
-    l32i    a2, a3, 0                   /* a2 = comparator increment          */
-    #endif
-    rsr     a3, XT_CCOMPARE             /* a3 = old comparator value          */
-    add     a4, a3, a2                  /* a4 = new comparator value          */
-    wsr     a4, XT_CCOMPARE             /* update comp. and clear interrupt   */
-    esync
-
-    #ifdef __XTENSA_CALL0_ABI__
-    /* Preserve a2 and a3 across C calls. */
-    s32i    a2, sp, 4
-    s32i    a3, sp, 8
-    #endif
-
-    /* Call the FreeRTOS tick handler (see port.c). */
-    #ifdef __XTENSA_CALL0_ABI__
-    call0   xPortSysTickHandler
-    #else
-    call4   xPortSysTickHandler
-    #endif
-
-    #ifdef __XTENSA_CALL0_ABI__
-    /* Restore a2 and a3. */
-    l32i    a2, sp, 4
-    l32i    a3, sp, 8
-    #endif
-
-    /* Check if we need to process more ticks to catch up. */
-    esync                               /* ensure comparator update complete  */
-    rsr     a4, CCOUNT                  /* a4 = cycle count                   */
-    sub     a4, a4, a3                  /* diff = ccount - old comparator     */
-    blt     a2, a4, .L_xt_timer_int_catchup  /* repeat while diff > divisor */
-
-    RET(16)
-
-    /*
-**********************************************************************************************************
-*                                           _frxt_tick_timer_init
-*                                      void _frxt_tick_timer_init(void)
-*
-* Initialize timer and timer interrrupt handler (_xt_tick_divisor_init() has already been been called).
-* Callable from C (obeys ABI conventions on entry).
-*
-**********************************************************************************************************
-*/
-    .globl  _frxt_tick_timer_init
-    .type   _frxt_tick_timer_init,@function
-    .align  4
-_frxt_tick_timer_init:
-
-    ENTRY(16)
-
-    /* Set up the periodic tick timer (assume enough time to complete init). */
-    #ifdef XT_CLOCK_FREQ
-    movi    a3, XT_TICK_DIVISOR
-    #else
-    movi    a2, _xt_tick_divisor
-    l32i    a3, a2, 0
-    #endif
-    rsr     a2, CCOUNT              /* current cycle count */
-    add     a2, a2, a3              /* time of first timer interrupt */
-    wsr     a2, XT_CCOMPARE         /* set the comparator */
-
-    /*
-    Enable the timer interrupt at the device level. Don't write directly
-    to the INTENABLE register because it may be virtualized.
-    */
-    #ifdef __XTENSA_CALL0_ABI__
-    movi    a2, XT_TIMER_INTEN
-    call0   xt_ints_on
-    #else
-    movi    a6, XT_TIMER_INTEN
-    call4   xt_ints_on
-    #endif
-
-    RET(16)
-
-/*
-**********************************************************************************************************
-*                                    DISPATCH THE HIGH READY TASK
-*                                     void _frxt_dispatch(void)
-*
-* Switch context to the highest priority ready task, restore its state and dispatch control to it.
-*
-* This is a common dispatcher that acts as a shared exit path for all the context switch functions
-* including vPortYield() and vPortYieldFromInt(), all of which tail-call this dispatcher
-* (for windowed ABI vPortYieldFromInt() calls it indirectly via _frxt_int_exit() ).
-*
-* The Xtensa port uses different stack frames for solicited and unsolicited task suspension (see
-* comments on stack frames in xtensa_context.h). This function restores the state accordingly.
-* If restoring a task that solicited entry, restores the minimal state and leaves CPENABLE clear.
-* If restoring a task that was preempted, restores all state including the task's CPENABLE.
-*
-* Entry:
-*   pxCurrentTCB  points to the TCB of the task to suspend,
-*   Because it is tail-called without a true function entrypoint, it needs no 'entry' instruction.
-*
-* Exit:
-*   If incoming task called vPortYield() (solicited), this function returns as if from vPortYield().
-*   If incoming task was preempted by an interrupt, this function jumps to exit dispatcher.
-*
-**********************************************************************************************************
-*/
-    .globl  _frxt_dispatch
-    .type   _frxt_dispatch,@function
-    .align  4
-_frxt_dispatch:
-
-    #ifdef __XTENSA_CALL0_ABI__
-    call0   vTaskSwitchContext  // Get next TCB to resume
-    movi    a2, pxCurrentTCB
-    #else
-    movi    a2, pxCurrentTCB
-    call4   vTaskSwitchContext  // Get next TCB to resume
-    #endif
-    l32i    a3,  a2, 0
-    l32i    sp,  a3, TOPOFSTACK_OFFS     /* SP = next_TCB->pxTopOfStack;  */
-    s32i    a3,  a2, 0
-
-    /* Determine the type of stack frame. */
-    l32i    a2,  sp, XT_STK_EXIT        /* exit dispatcher or solicited flag */
-    bnez    a2,  .L_frxt_dispatch_stk
-
-.L_frxt_dispatch_sol:
-
-    /* Solicited stack frame. Restore minimal context and return from vPortYield(). */
-    l32i    a3,  sp, XT_SOL_PS
-    #ifdef __XTENSA_CALL0_ABI__
-    l32i    a12, sp, XT_SOL_A12
-    l32i    a13, sp, XT_SOL_A13
-    l32i    a14, sp, XT_SOL_A14
-    l32i    a15, sp, XT_SOL_A15
-    #endif
-    l32i    a0,  sp, XT_SOL_PC
-    #if XCHAL_CP_NUM > 0
-    /* Ensure wsr.CPENABLE is complete (should be, it was cleared on entry). */
-    rsync
-    #endif
-    /* As soons as PS is restored, interrupts can happen. No need to sync PS. */
-    wsr     a3,  PS
-    #ifdef __XTENSA_CALL0_ABI__
-    addi    sp,  sp, XT_SOL_FRMSZ
-    ret
-    #else
-    retw
-    #endif
-
-.L_frxt_dispatch_stk:
-
-    #if XCHAL_CP_NUM > 0
-    /* Restore CPENABLE from task's co-processor save area. */
-    movi    a3, pxCurrentTCB            /* cp_state =                       */
-    l32i    a3, a3, 0
-    l32i    a2, a3, CP_TOPOFSTACK_OFFS     /* StackType_t                       *pxStack; */
-    l16ui    a3, a2, XT_CPENABLE         /* CPENABLE = cp_state->cpenable;   */
-    wsr     a3, CPENABLE
-    #endif
-
-    /* Interrupt stack frame. Restore full context and return to exit dispatcher. */
-    call0   _xt_context_restore
-
-    /* In Call0 ABI, restore callee-saved regs (A12, A13 already restored). */
-    #ifdef __XTENSA_CALL0_ABI__
-    l32i    a14, sp, XT_STK_A14
-    l32i    a15, sp, XT_STK_A15
-    #endif
-
-    #if XCHAL_CP_NUM > 0
-    /* Ensure wsr.CPENABLE has completed. */
-    rsync
-    #endif
-
-    /*
-    Must return via the exit dispatcher corresponding to the entrypoint from which
-    this was called. Interruptee's A0, A1, PS, PC are restored and the interrupt
-    stack frame is deallocated in the exit dispatcher.
-    */
-    l32i    a0, sp, XT_STK_EXIT
-    ret
-
-
-/*
-**********************************************************************************************************
-*                            PERFORM A SOLICTED CONTEXT SWITCH (from a task)
-*                                        void vPortYield(void)
-*
-* This function saves the minimal state needed for a solicited task suspension, clears CPENABLE,
-* then tail-calls the dispatcher _frxt_dispatch() to perform the actual context switch
-*
-* At Entry:
-*   pxCurrentTCB  points to the TCB of the task to suspend
-*   Callable from C (obeys ABI conventions on entry).
-*
-* Does not return to caller.
-*
-**********************************************************************************************************
-*/
-    .globl  vPortYield
-    .type   vPortYield,@function
-    .align  4
-vPortYield:
-
-    #ifdef __XTENSA_CALL0_ABI__
-    addi    sp,  sp, -XT_SOL_FRMSZ
-    #else
-    entry   sp,  XT_SOL_FRMSZ
-    #endif
-
-    rsr     a2,  PS
-    s32i    a0,  sp, XT_SOL_PC
-    s32i    a2,  sp, XT_SOL_PS
-    #ifdef __XTENSA_CALL0_ABI__
-    s32i    a12, sp, XT_SOL_A12         /* save callee-saved registers      */
-    s32i    a13, sp, XT_SOL_A13
-    s32i    a14, sp, XT_SOL_A14
-    s32i    a15, sp, XT_SOL_A15
-    #else
-    /* Spill register windows. Calling xthal_window_spill() causes extra    */
-    /* spills and reloads, so we will set things up to call the _nw version */
-    /* instead to save cycles.                                              */
-    movi    a6,  ~(PS_WOE_MASK|PS_INTLEVEL_MASK)  /* spills a4-a7 if needed */
-    and     a2,  a2, a6                           /* clear WOE, INTLEVEL    */
-    addi    a2,  a2, XCHAL_EXCM_LEVEL             /* set INTLEVEL           */
-    wsr     a2,  PS
-    rsync
-    call0   xthal_window_spill_nw
-    l32i    a2,  sp, XT_SOL_PS                    /* restore PS             */
-    wsr     a2,  PS
-    #endif
-
-    rsil    a2,  XCHAL_EXCM_LEVEL       /* disable low/med interrupts       */
-
-    #if XCHAL_CP_NUM > 0
-    /* Save coprocessor callee-saved state (if any). At this point CPENABLE */
-    /* should still reflect which CPs were in use (enabled).                */
-    call0   _xt_coproc_savecs
-    #endif
-
-    movi    a2,  pxCurrentTCB
-    movi    a3,  0
-    l32i    a2,  a2, 0                  /* a2 = pxCurrentTCB                */
-    s32i    a3,  sp, XT_SOL_EXIT        /* 0 to flag as solicited frame     */
-    s32i    sp,  a2, TOPOFSTACK_OFFS    /* pxCurrentTCB->pxTopOfStack = SP  */
-
-    #if XCHAL_CP_NUM > 0
-    /* Clear CPENABLE, also in task's co-processor state save area. */
-    l32i    a2,  a2, CP_TOPOFSTACK_OFFS /* a2 = pxCurrentTCB->cp_state      */
-    movi    a3,  0
-    wsr     a3,  CPENABLE
-    beqz    a2,  1f
-    s16i     a3,  a2, XT_CPENABLE        /* clear saved cpenable             */
-1:
-    #endif
-
-    /* Tail-call dispatcher. */
-    call0   _frxt_dispatch
-    /* Never reaches here. */
-
-
-/*
-**********************************************************************************************************
-*                         PERFORM AN UNSOLICITED CONTEXT SWITCH (from an interrupt)
-*                                        void vPortYieldFromInt(void)
-*
-* This calls the context switch hook (removed), saves and clears CPENABLE, then tail-calls the dispatcher
-* _frxt_dispatch() to perform the actual context switch.
-*
-* At Entry:
-*   Interrupted task context has been saved in an interrupt stack frame at pxCurrentTCB->pxTopOfStack.
-*   pxCurrentTCB  points to the TCB of the task to suspend,
-*   Callable from C (obeys ABI conventions on entry).
-*
-* At Exit:
-*   Windowed ABI defers the actual context switch until the stack is unwound to interrupt entry.
-*   Call0 ABI tail-calls the dispatcher directly (no need to unwind) so does not return to caller.
-*
-**********************************************************************************************************
-*/
-    .globl  vPortYieldFromInt
-    .type   vPortYieldFromInt,@function
-    .align  4
-vPortYieldFromInt:
-
-    ENTRY(16)
-
-    #if XCHAL_CP_NUM > 0
-    /* Save CPENABLE in task's co-processor save area, and clear CPENABLE.  */
-    movi    a3, pxCurrentTCB            /* cp_state =                       */
-    l32i    a3, a3, 0
-    l32i    a2, a3, CP_TOPOFSTACK_OFFS
-
-    rsr     a3, CPENABLE
-    s16i     a3, a2, XT_CPENABLE         /* cp_state->cpenable = CPENABLE;   */
-    movi    a3, 0
-    wsr     a3, CPENABLE                /* disable all co-processors        */
-    #endif
-
-    #ifdef __XTENSA_CALL0_ABI__
-    /* Tail-call dispatcher. */
-    call0   _frxt_dispatch
-    /* Never reaches here. */
-    #else
-    RET(16)
-    #endif
-
-/*
-**********************************************************************************************************
-*                                        _frxt_task_coproc_state
-*                                   void _frxt_task_coproc_state(void)
-*
-* Implements the Xtensa RTOS porting layer's XT_RTOS_CP_STATE function for FreeRTOS.
-*
-* May only be called when a task is running, not within an interrupt handler (returns 0 in that case).
-* May only be called from assembly code by the 'call0' instruction. Does NOT obey ABI conventions.
-* Returns in A15 a pointer to the base of the co-processor state save area for the current task.
-* See the detailed description of the XT_RTOS_ENTER macro in xtensa_rtos.h.
-*
-**********************************************************************************************************
-*/
-#if XCHAL_CP_NUM > 0
-
-    .globl  _frxt_task_coproc_state
-    .type   _frxt_task_coproc_state,@function
-    .align  4
-_frxt_task_coproc_state:
-
-    movi    a15, port_xSchedulerRunning /* if (port_xSchedulerRunning              */
-    l32i    a15, a15, 0
-    beqz    a15, 1f
-    movi    a15, port_interruptNesting  /* && port_interruptNesting == 0           */
-    l32i    a15, a15, 0
-    bnez    a15, 1f
-    movi    a15, pxCurrentTCB
-    l32i    a15, a15, 0                 /* && pxCurrentTCB != 0) {                 */
-    beqz    a15, 2f
-    l32i    a15, a15, CP_TOPOFSTACK_OFFS
-    ret
-
-1:  movi    a15, 0
-2:  ret
-
-#endif /* XCHAL_CP_NUM > 0 */
diff --git a/portable/ThirdParty/XCC/Xtensa/portbenchmark.h b/portable/ThirdParty/XCC/Xtensa/portbenchmark.h
deleted file mode 100644
index ddaad7ad2..000000000
--- a/portable/ThirdParty/XCC/Xtensa/portbenchmark.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/*
- * This utility helps benchmarking interrupt latency and context switches.
- * In order to enable it, set configBENCHMARK to 1 in FreeRTOSConfig.h.
- * You will also need to download the FreeRTOS_trace patch that contains
- * portbenchmark.c and the complete version of portbenchmark.h
- */
-
-#ifndef PORTBENCHMARK_H
-#define PORTBENCHMARK_H
-
-#if configBENCHMARK
-    #error "You need to download the FreeRTOS_trace patch that overwrites this file"
-#endif
-
-#define portbenchmarkINTERRUPT_DISABLE()
-#define portbenchmarkINTERRUPT_RESTORE(newstate)
-#define portbenchmarkIntLatency()
-#define portbenchmarkIntWait()
-#define portbenchmarkReset()
-#define portbenchmarkPrint()
-
-#endif /* PORTBENCHMARK */
diff --git a/portable/ThirdParty/XCC/Xtensa/portclib.c b/portable/ThirdParty/XCC/Xtensa/portclib.c
deleted file mode 100644
index 5a3b659f9..000000000
--- a/portable/ThirdParty/XCC/Xtensa/portclib.c
+++ /dev/null
@@ -1,230 +0,0 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-#include "FreeRTOS.h"
-
-#if XT_USE_THREAD_SAFE_CLIB
-
-#if XSHAL_CLIB == XTHAL_CLIB_XCLIB
-
-#include <errno.h>
-#include <sys/reent.h>
-
-#include "semphr.h"
-
-typedef SemaphoreHandle_t       _Rmtx;
-
-//-----------------------------------------------------------------------------
-//  Override this and set to nonzero to enable locking.
-//-----------------------------------------------------------------------------
-int32_t _xclib_use_mt = 1;
-
-
-//-----------------------------------------------------------------------------
-//  Init lock.
-//-----------------------------------------------------------------------------
-void
-_Mtxinit(_Rmtx * mtx)
-{
-    *mtx = xSemaphoreCreateRecursiveMutex();
-}
-
-//-----------------------------------------------------------------------------
-//  Destroy lock.
-//-----------------------------------------------------------------------------
-void
-_Mtxdst(_Rmtx * mtx)
-{
-    if ((mtx != NULL) && (*mtx != NULL)) {
-        vSemaphoreDelete(*mtx);
-    }
-}
-
-//-----------------------------------------------------------------------------
-//  Lock.
-//-----------------------------------------------------------------------------
-void
-_Mtxlock(_Rmtx * mtx)
-{
-    if ((mtx != NULL) && (*mtx != NULL)) {
-        xSemaphoreTakeRecursive(*mtx, portMAX_DELAY);
-    }
-}
-
-//-----------------------------------------------------------------------------
-//  Unlock.
-//-----------------------------------------------------------------------------
-void
-_Mtxunlock(_Rmtx * mtx)
-{
-    if ((mtx != NULL) && (*mtx != NULL)) {
-        xSemaphoreGiveRecursive(*mtx);
-    }
-}
-
-//-----------------------------------------------------------------------------
-//  Called by malloc() to allocate blocks of memory from the heap.
-//-----------------------------------------------------------------------------
-void *
-_sbrk_r (struct _reent * reent, int32_t incr)
-{
-    extern char _end;
-    extern char _heap_sentry;
-    static char * _heap_sentry_ptr = &_heap_sentry;
-    static char * heap_ptr;
-    char * base;
-
-    if (!heap_ptr)
-        heap_ptr = (char *) &_end;
-
-    base = heap_ptr;
-    if (heap_ptr + incr >= _heap_sentry_ptr) {
-        reent->_errno = ENOMEM;
-        return (char *) -1;
-    }
-
-    heap_ptr += incr;
-    return base;
-}
-
-//-----------------------------------------------------------------------------
-//  Global initialization for C library.
-//-----------------------------------------------------------------------------
-void
-vPortClibInit(void)
-{
-}
-
-//-----------------------------------------------------------------------------
-//  Per-thread cleanup stub provided for linking, does nothing.
-//-----------------------------------------------------------------------------
-void
-_reclaim_reent(void * ptr)
-{
-}
-
-#endif /* XSHAL_CLIB == XTHAL_CLIB_XCLIB */
-
-#if XSHAL_CLIB == XTHAL_CLIB_NEWLIB
-
-#include <errno.h>
-#include <malloc.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include "semphr.h"
-
-static SemaphoreHandle_t xClibMutex;
-static uint32_t  ulClibInitDone = 0;
-
-//-----------------------------------------------------------------------------
-//  Get C library lock.
-//-----------------------------------------------------------------------------
-void
-__malloc_lock(struct _reent * ptr)
-{
-    if (!ulClibInitDone)
-        return;
-
-    xSemaphoreTakeRecursive(xClibMutex, portMAX_DELAY);
-}
-
-//-----------------------------------------------------------------------------
-//  Release C library lock.
-//-----------------------------------------------------------------------------
-void
-__malloc_unlock(struct _reent * ptr)
-{
-    if (!ulClibInitDone)
-        return;
-
-    xSemaphoreGiveRecursive(xClibMutex);
-}
-
-//-----------------------------------------------------------------------------
-//  Lock for environment. Since we have only one global lock we can just call
-//  the malloc() lock function.
-//-----------------------------------------------------------------------------
-void
-__env_lock(struct _reent * ptr)
-{
-    __malloc_lock(ptr);
-}
-
-
-//-----------------------------------------------------------------------------
-//  Unlock environment.
-//-----------------------------------------------------------------------------
-void
-__env_unlock(struct _reent * ptr)
-{
-    __malloc_unlock(ptr);
-}
-
-//-----------------------------------------------------------------------------
-//  Called by malloc() to allocate blocks of memory from the heap.
-//-----------------------------------------------------------------------------
-void *
-_sbrk_r (struct _reent * reent, int32_t incr)
-{
-    extern char _end;
-    extern char _heap_sentry;
-    static char * _heap_sentry_ptr = &_heap_sentry;
-    static char * heap_ptr;
-    char * base;
-
-    if (!heap_ptr)
-        heap_ptr = (char *) &_end;
-
-    base = heap_ptr;
-    if (heap_ptr + incr >= _heap_sentry_ptr) {
-        reent->_errno = ENOMEM;
-        return (char *) -1;
-    }
-
-    heap_ptr += incr;
-    return base;
-}
-
-//-----------------------------------------------------------------------------
-//  Global initialization for C library.
-//-----------------------------------------------------------------------------
-void
-vPortClibInit(void)
-{
-    configASSERT(!ulClibInitDone);
-
-    xClibMutex = xSemaphoreCreateRecursiveMutex();
-    ulClibInitDone  = 1;
-}
-
-#endif /* XSHAL_CLIB == XTHAL_CLIB_NEWLIB */
-
-#endif /* XT_USE_THREAD_SAFE_CLIB */
diff --git a/portable/ThirdParty/XCC/Xtensa/portmacro.h b/portable/ThirdParty/XCC/Xtensa/portmacro.h
deleted file mode 100644
index dced2382c..000000000
--- a/portable/ThirdParty/XCC/Xtensa/portmacro.h
+++ /dev/null
@@ -1,216 +0,0 @@
-/*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
-    extern "C" {
-#endif
-/* *INDENT-ON* */
-
-#ifndef __ASSEMBLER__
-
-#include <stdint.h>
-
-#include <xtensa/tie/xt_core.h>
-#include <xtensa/hal.h>
-#include <xtensa/config/core.h>
-#include <xtensa/config/system.h>   /* required for XSHAL_CLIB */
-#include <xtensa/xtruntime.h>
-
-//#include "xtensa_context.h"
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-
-#define portCHAR        int8_t
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        int32_t
-#define portSHORT       int16_t
-#define portSTACK_TYPE  uint32_t
-#define portBASE_TYPE   int
-
-typedef portSTACK_TYPE          StackType_t;
-typedef portBASE_TYPE           BaseType_t;
-typedef unsigned portBASE_TYPE  UBaseType_t;
-
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
-#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#else
-    #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
-#endif
-/*-----------------------------------------------------------*/
-
-// portbenchmark
-#include "portbenchmark.h"
-
-/* Critical section management. NW-TODO: replace XTOS_SET_INTLEVEL with more efficient version, if any? */
-// These cannot be nested. They should be used with a lot of care and cannot be called from interrupt level.
-#define portDISABLE_INTERRUPTS()      do { XTOS_SET_INTLEVEL(XCHAL_EXCM_LEVEL); portbenchmarkINTERRUPT_DISABLE(); } while (0)
-#define portENABLE_INTERRUPTS()       do { portbenchmarkINTERRUPT_RESTORE(0); XTOS_SET_INTLEVEL(0); } while (0)
-
-// These can be nested
-#define portCRITICAL_NESTING_IN_TCB 1  // For now, let FreeRTOS' (tasks.c) manage critical nesting
-void vTaskEnterCritical(void);
-void vTaskExitCritical(void);
-#define portENTER_CRITICAL()        vTaskEnterCritical()
-#define portEXIT_CRITICAL()         vTaskExitCritical()
-
-// Cleaner and preferred solution allows nested interrupts disabling and restoring via local registers or stack.
-// They can be called from interrupts too.
-static inline unsigned portENTER_CRITICAL_NESTED() { unsigned state = XTOS_SET_INTLEVEL(XCHAL_EXCM_LEVEL); portbenchmarkINTERRUPT_DISABLE(); return state; }
-#define portEXIT_CRITICAL_NESTED(state)   do { portbenchmarkINTERRUPT_RESTORE(state); XTOS_RESTORE_JUST_INTLEVEL(state); } while (0)
-
-// These FreeRTOS versions are similar to the nested versions above
-#define portSET_INTERRUPT_MASK_FROM_ISR()            portENTER_CRITICAL_NESTED()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(state)     portEXIT_CRITICAL_NESTED(state)
-
-/*-----------------------------------------------------------*/
-
-/* Architecture specifics. */
-#define portSTACK_GROWTH            ( -1 )
-#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT          4
-#define portNOP()                   XT_NOP()
-#define portMEMORY_BARRIER()        XT_MEMW()
-/*-----------------------------------------------------------*/
-
-/* Fine resolution time */
-#define portGET_RUN_TIME_COUNTER_VALUE()  xthal_get_ccount()
-
-/* Kernel utilities. */
-void vPortYield( void );
-void _frxt_setup_switch( void );
-#define portYIELD()       vPortYield()
-#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken )  \
-    if ( ( xHigherPriorityTaskWoken ) != 0 ) {  \
-        _frxt_setup_switch();           \
-    }
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-// When coprocessors are defined, we to maintain a pointer to coprocessors area.
-// We currently use a hack: redefine field xMPU_SETTINGS in TCB block as a structure that can hold:
-// MPU wrappers, coprocessor area pointer, trace code structure, and more if needed.
-// The field is normally used for memory protection. FreeRTOS should create another general purpose field.
-typedef struct {
-    #if XCHAL_CP_NUM > 0
-    volatile StackType_t* coproc_area; // Pointer to coprocessor save area; MUST BE FIRST
-    #endif
-
-    #if portUSING_MPU_WRAPPERS
-    // Define here mpu_settings, which is port dependent
-    int mpu_setting; // Just a dummy example here; MPU not ported to Xtensa yet
-    #endif
-
-    #if configUSE_TRACE_FACILITY_2
-    struct {
-        // Cf. porttraceStamp()
-        int taskstamp;        /* Stamp from inside task to see where we are */
-        int taskstampcount;   /* A counter usually incremented when we restart the task's loop */
-    } porttrace;
-    #endif
-} xMPU_SETTINGS;
-
-// Main hack to use MPU_wrappers even when no MPU is defined (warning: mpu_setting should not be accessed; otherwise move this above xMPU_SETTINGS)
-#if (XCHAL_CP_NUM > 0 || configUSE_TRACE_FACILITY_2) && !portUSING_MPU_WRAPPERS   // If MPU wrappers not used, we still need to allocate coproc area
-    #undef portUSING_MPU_WRAPPERS
-    #define portUSING_MPU_WRAPPERS 1   // Enable it to allocate coproc area
-    #define MPU_WRAPPERS_H             // Override mpu_wrapper.h to disable unwanted code
-    #define PRIVILEGED_FUNCTION
-    #define PRIVILEGED_DATA
-#endif
-
-// porttrace
-#if configUSE_TRACE_FACILITY_2
-#include "porttrace.h"
-#endif
-
-// configASSERT_2 if requested
-#if configASSERT_2
-#include <stdio.h>
-void exit(int);
-#define configASSERT( x )   if (!(x)) { porttracePrint(-1); printf("\nAssertion failed in %s:%d\n", __FILE__, __LINE__); exit(-1); }
-#endif
-
-
-/* C library support -- only XCLIB and NEWLIB are supported. */
-
-/* To enable thread-safe C library support, XT_USE_THREAD_SAFE_CLIB must be
-   defined to be > 0 somewhere above or on the command line. */
-
-#if (XT_USE_THREAD_SAFE_CLIB > 0u) && (XSHAL_CLIB == XTHAL_CLIB_XCLIB)
-extern void vPortClibInit(void);
-#endif // XCLIB support
-
-#if (XT_USE_THREAD_SAFE_CLIB > 0u) && (XSHAL_CLIB == XTHAL_CLIB_NEWLIB)
-extern void vPortClibInit(void);
-
-// This C library cleanup is not currently done by FreeRTOS when deleting a task
-#include <stdio.h>
-#define portCLEAN_UP_TCB(pxTCB)   vPortCleanUpTcbClib(&((pxTCB)->xNewLib_reent))
-static inline void vPortCleanUpTcbClib(struct _reent *ptr)
-{
-    FILE * fp = &(ptr->__sf[0]);
-    int i;
-    for (i = 0; i < 3; ++i, ++fp) {
-        fp->_close = NULL;
-    }
-}
-#endif // NEWLIB support
-
-#endif // __ASSEMBLER__
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
-    }
-#endif
-/* *INDENT-ON* */
-
-#endif /* PORTMACRO_H */
diff --git a/portable/ThirdParty/XCC/Xtensa/porttrace.h b/portable/ThirdParty/XCC/Xtensa/porttrace.h
deleted file mode 100644
index b8319ca1b..000000000
--- a/portable/ThirdParty/XCC/Xtensa/porttrace.h
+++ /dev/null
@@ -1,49 +0,0 @@
- /*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/*
- * This utility helps tracing the entering and exiting from tasks.
- * It maintains a circular buffer of tasks in the order they execute,
- * and their execution time. To enable it, set configUSE_TRACE_FACILITY_2
- * to 1 in FreeRTOSConfig.h. You will also need to download the
- * FreeRTOS_trace patch that contains porttrace.c and the complete version
- * of porttrace.h.
- */
-
-#ifndef PORTTRACE_H
-#define PORTTRACE_H
-
-#if configUSE_TRACE_FACILITY_2
-    #error "You need to download the FreeRTOS_trace patch that overwrites this file"
-#endif
-
-#define porttracePrint(nelements)
-#define porttraceStamp(stamp, count_incr)
-
-#endif /* PORTTRACE_H */
diff --git a/portable/ThirdParty/XCC/Xtensa/readme_xtensa.txt b/portable/ThirdParty/XCC/Xtensa/readme_xtensa.txt
index 56dcc6965..e2ee4307c 100644
--- a/portable/ThirdParty/XCC/Xtensa/readme_xtensa.txt
+++ b/portable/ThirdParty/XCC/Xtensa/readme_xtensa.txt
@@ -1,763 +1,11 @@
-    FreeRTOS Port for Xtensa Configurable and Diamond Processors
-    ============================================================
+    FreeRTOS Port for Xtensa Configurable Processors
+    ================================================
 
-                FreeRTOS Kernel Version 10.0.0
+The Xtensa FreeRTOS port has moved and can be found in the 
+"FreeRTOS-Kernel-Partner-Supported-Ports" submodule of FreeRTOS-Kernel:
 
+FreeRTOS/Source/portable/ThirdParty/Partner-Supported-Ports/Cadence/Xtensa
 
-Introduction
-------------
-
-This document describes the Xtensa port for FreeRTOS multitasking RTOS.
-For an introduction to FreeRTOS itself, please refer to FreeRTOS
-documentation.
-
-This port currently works with FreeRTOS kernel version 10.0.0.
-
-
-Xtensa Configuration Requirements and Restrictions
---------------------------------------------------
-
-The Xtensa configurable architecture supports a vast space of processor
-features. This port supports all of them, including custom processor
-extensions defined in the TIE language, with certain minimum
-requirements. You must use Xtensa Tools to compile and link FreeRTOS and
-your application for your Xtensa configuration. The port uses the Xtensa
-Hardware Abstraction Layer (HAL) to adapt to your Xtensa configuration.
-NOTE: It may be possible to build and run this with the open-source
-xtensa-linux tools provided you have the correct overlay for your Xtensa
-configuration. However, this has not been tested and is currently not
-supported by Cadence.
-
-This port includes optional reentrancy support for the 'newlib' and
-'xclib' C runtime libraries distributed with Xtensa Tools, providing
-thread-safety on a per task basis (for use in tasks only, not interrupt
-handlers).
-
-NOTE: At this time only 'newlib' and 'xclib' C libraries are supported
-for thread safety. The 'uclibc' library is not reentrant and does not
-provide thread safety at this time. However, if you are not concerned
-with reentrancy then you can use any of these libraries.
-
-This port also includes a simple example application that may run on
-a supported board or the Xtensa instruction set simulator (ISS). There
-are also a couple of test programs used in maintaining the port, which
-serve as additional examples.
-
-FreeRTOS for Xtensa configurable processors requires the following minimum
-processor configuration options:
-- Timer interrupt option with at least one interruptible timer.
-- Interrupt option (implied by the timer interrupt option).
-- Exception Architecture 2 (XEA2). Please note that XEA1 is NOT supported.
-  All 'Diamond', 'Xtensa 6', 'Xtensa LX' and 'Xtensa LX2' processors and
-  most 'Xtensa T1050' processors are configured with XEA2.
-All Diamond processor cores meet these requirements and are supported.
-
-Minimal support for certain evaluation boards is provided via a board
-independent XTBSP API implemented by a board specific library distributed
-with the Xtensa Tools. This provides the board clock frequency and basic
-polled drivers for the display and console device. Note that XTBSP
-is not a tradtional RTOS "board support package" with RTOS specific
-interrupt-driven drivers - it is not specific to any RTOS. Note that
-FreeRTOS can run on any Xtensa or Diamond board without this board support
-(a "raw" platform), but you will have to provide the clock frequency
-and drivers for any on-board devices you want to use.
-
-
-Installation
-------------
-
-The Xtensa port of FreeRTOS is available at this location:
-
-    https://github.com/foss-xtensa/amazon-freertos
-
-This download includes the core FreeRTOS source and include files needed
-to build the port. You can also download the official release of FreeRTOS
-version 1.0.0 or later from this location:
-
-    https://github.com/aws/amazon-freertos
-
-The Xtensa port files are currently not included in the official package.
-
-All source is provided along with a Makefile that works for any host
-platform supported by Xtensa Tools (Windows, Linux). These instructions
-are written for Windows users, but can easily be understood and adapted
-to other host platforms.
-
-First install the FreeRTOS common package in a directory of your choosing.
-The structure of that package will look like this:
-
-<install directory>
-|-- demos
-|   `-- cadence
-|       `-- sim
-|           |-- common
-|           |   |-- application_code
-|           |   |   `-- cadence_code
-|           |   `-- config_files
-|           `-- xplorer
-`-- lib
-    |-- FreeRTOS
-    |   `-- portable
-    |       |-- Common
-    |       |-- MemMang
-    |       `-- XCC
-    |           `-- Xtensa
-    `-- include
-        `-- private
-
-The Xtensa Tools are available from Cadence as part of a processor
-license. Be sure you have installed the Xtensa Tools and your processor
-configuration.
-
-
-Building FreeRTOS for Xtensa
-----------------------------
-
-To build the FreeRTOS library and the example programs, go into the
-directory 'demos/cadence/sim' and use the makefile in that directory.
-"make all" will build all the examples. There is another makefile in
-the 'lib/FreeRTOS/portable/XCC/Xtensa' directory that builds just the
-FreeRTOS library.
-
-By default, you will build for the Xtensa instruction set simulator. If
-you have a supported emulation board, you can build to run on that. You
-can also build to run on a raw Xtensa core with no board support, a
-good starting point for supporting your own target platform. Cadence
-recommends doing functional development on the simulator because it
-is easier to debug with, then move to a board if/when you need to test
-hardware drivers or real-time performance.
-
-The provided makefile simplifies building FreeRTOS and the example
-for your Xtensa configuration and platform (ISS, board, etc.). There
-are detailed instructions in the comments at the top of the makefile.
-
-The makefiles work on Windows and Linux and support incremental builds.
-The build for each Xtensa configuration and target platform is placed in
-a subdirectory so several core and platform builds can co-exist even with
-incremental rebuilds. You may specify the root of the build area (if tou
-want it to be elsewhere than under the source tree) by defining BLDROOT
-either in the make command or your shell environment.
-
-
-Building the FreeRTOS Library
------------------------------
-
-First, be sure you have installed Xtensa Tools and your processor
-configuration, and be sure that Xtensa Tools are in your search path.
-You can use xt-make, which comes with the Xtensa Tools, to run the
-makefiles.
-
-Change directories to the Xtensa port directory:
-
-> cd lib/FreeRTOS/portable/XCC/Xtensa
-
-Now build the FreeRTOS RTOS as a library (libfreertos.a) as follows:
-
-> xt-make
-
-which by default builds for the simulator (TARGET=sim), or:
-
-> xt-make TARGET=board
-
-which builds for a supported board. Note that the board type does not
-need to be specified when building the FreeRTOS library.
-
-If you are building for an Xtensa processor configuration that is not the
-default you selected when you installed Xtensa Tools, you need to define the
-environment variable XTENSA_CORE. If your configuration is not in the
-default registry you selected when you installed Xtensa Tools, you also
-need to define the environment variable XTENSA_SYSTEM. See tools manuals.
-You can avoid defining these in your environment if you pass the variables
-you need to redefine into xt-make as follows:
-
-> xt-make XTENSA_CORE=<your_config_name> XTENSA_SYSTEM=<your_registry> ...
-
-There are more details about build options in the comment in the Makefile.
-
-After the library has been built, you must link your application with this
-library in order to use FreeRTOS.
-
-
-Building the FreeRTOS Examples
-------------------------------
-
-The provided examples are designed to run on the Xtensa instruction set
-simulator (ISS) or a supported evaluation board programmed with your
-Xtensa processor configuration.
-
-To build the examples for the default platform (simulator):
-
-> cd demos/cadence/sim
-
-> xt-make all
-
-which is the same as
-
-> xt-make all TARGET=sim
-
-The boards currently supported are the Xilinx ML605 and KC705 FPGA
-development boards. To target these boards, type
-
-> xt-make all TARGET=ml605
-
-or
-
-> xt-make all TARGET=kc705
-
-To build in a location other than the default, specify the new location
-using the BLDROOT variable. Note that this makefile will invoke the
-FreeRTOS library build makefile automatically, passing on the relevant
-parameters based on what you specified.
-
-You can override the default compilation options by specifying the new
-options via CFLAGS. For example:
-
-> xt-make all TARGET=sim CFLAGS="-O2 -Os -g"
-
-This compiles the examples and links them with the FreeRTOS library
-libfreertos.a and the appropriate linker-support package (LSP) for your
-target platform (you can override the LSP by adding LSP=<lsp> to the
-xt-make command line). The resulting ELF files can be downloaded and
-executed on the target. The example binaries appear in the platform
-specific subdirectory described earlier.
-
-To build your application with thread-safe C library support, you
-need to make certain modifications to the application to plug in and
-invoke the reentrancy support. This allows each task to use the library
-without interference with other tasks (it is not safe for interrupt
-handlers to call the C library).
-
-First, you must define
-
-    XT_USE_THREAD_SAFE_CLIB
-
-to a nonzero value either in xtensa_config.h or on the compiler's command
-line. Note that the default xtensa_config.h provided with this port does
-define this to 1 if either newlib or xclib is detected.
-
-Then, you must also make sure to allocate extra space on the stack for
-each task that will use the C library reentrant functions. This extra
-space is to be allocated over and above the actual stack space required
-by the task itself. The define
-
-    XT_STACK_EXTRA_CLIB
-
-specifies the amount of extra space to be added on to the stack to allow
-saving the context for the C library as well as the coprocessors if any.
-E.g. if your task requires 2000 bytes of stack space, you must allocate
-(2000 + XT_STACK_EXTRA_CLIB) bytes for the stack.
-
-
-IMPORTANT NOTE
---------------
-
-The header file FreeRTOS.h, which is a part of the core FreeRTOS sources,
-includes <reent.h> if thread safety for the C libraries is enabled. For
-xclib, this file exists in <sys/reent.h> and so is reported as missing.
-To work around this, the makefiles supplied with this port will copy the
-reent.h header into the build directory during the build process. If you
-use a different build process, then you must make sure to copy this file
-to a location that is included in the list of include paths. This can be
-the build directory or the directory that contains the Xtensa port source
-files.
-
-
-Running or Debugging an Application
------------------------------------
-
-To execute the example application on the simulator:
-
-> xt-run [--turbo] example.exe
-
-The option --turbo provides much faster, but non-cycle-accurate simulation
-(the --turbo option is only available with Xtensa Tools version 7 or later).
-
-
-To execute on the simulator using the Xplorer GUI based debugger:
-
-> xplorer --debug example.exe
-
-
-To execute on a supported evaluation board, download example.exe per
-instructions in the tools manuals. Be sure the board has been programmed
-with the correct configuration and is set up to boot from RAM and debug
-a downloaded program!  Optionally you may connect a terminal or terminal
-emulator to the serial port on the board with settings as described in
-the board user manual, and see the output of printf on the terminal.
-
-To obtain I/O on a "raw" platform such as an unsupported board, you need
-to provide low level I/O drivers (eg. inbyte() and outbyte() for character
-I/O if you want to use printf etc.).  You can run "raw" executables on
-any Xtensa platform, including simulator and any board, but you will not
-see any behavior specific to the platform (eg. display, printed output,
-stopping simulation at end of program). You can, while debugging, use a
-debugger mechanism called GDBIO to obtain basic I/O. To use GDBIO, link
-with the gdbio LSP. Refer to Xtensa tools documentation for details.
-
-
-Task Stack Sizes
-----------------
-
-The application must ensure that every task has enough space for its
-stack. Each task needs enough space for its own use, its own interrupt
-stack frame (defined in xtensa_context.h) and space to save coprocessor
-state, if any. Several factors influence the size of the stack required,
-including the compiler optimization level and the use of the C library.
-Calls to standard output functions such as printf() can use up a lot of
-stack space. The tool xt-stack-usage is helpful in determining safe stack
-sizes for your application.
-
-Some macros are provided in xtensa_config.h to help determine the stack
-size for tasks that do and do not use the C library. Use these as the
-basis for each task's stack size. They are minimum requirements taking
-into account your configuration and use of the C library. In particular,
-the define
-
-    XT_STACK_MIN_SIZE
-
-defines the minimum stack size for any task. Be very careful if you try
-to use a stack size smaller than this minimum. Stack overruns can cause
-all kinds of hard-to-debug errors. It is recommended that you enable the
-FreeRTOS stack checking features during development.
-
-WARNING: The newlib printf() function uses a lot of stack space. Be very
-careful in using it. Optionally you can use the 'libxtutil' library for
-output - it implements a subset of printf() that has smaller code size
-and uses far less stack space. More information about this library is in
-the Xtensa Tools documentation.
-
-
-Interrupt Stack
----------------
-
-Beginning with port version 1.2, the port uses a separate interrupt stack
-for handling interrupts. Thus, it is no longer necessary for each task to
-reserve space on its stack to handle interrupts. The size of the interrupt
-stack is controlled by the parameter "configISR_STACK_SIZE" defined in
-FreeRTOSConfig.h. Define this carefully to match your system requirements.
-
-
-Assembler / Compiler Switches
------------------------------
-
-The following are compiler switches are used by the provided
-Makefile in building the FreeRTOS library and example application.
-These can be modified by editing the Makefile or by overriding the
-CFLAGS variable in the make command line, for example:
-
-> xt-make CFLAGS="-O2 -DXT_USE_THREAD_SAFE_CLIB"
-
-    -g                      Specifies debug information.
-    -c                      Specifies object code generation.
-    -On                     Sets compiler optimization level n (default -O0).
-    -mlongcalls             Allows assembler and linker to convert call
-                            instructions to longer indirect call sequences
-                            when target is out of range.
-    -x assembler-with-cpp   Passes .s and .S files through C preprocessor.
-    -Dmacro                 Define a preprocessor macro with no value.
-    -Dmacro=value           Define a preprocessor macro with a value.
-
-See the compiler / linker documentation for a full list of switches and
-their use.
-
-Many definitions can be provided at compile-time via the -D option
-without editing the source code. Here are some of the more useful ones:
-
-    XT_USE_THREAD_SAFE_CLIB Enable support for the reentrancy to provide
-                            thread-safety for the newlib and xclib libraries
-                            supplied with Xtensa Tools. Default ON.
-
-    Note, the follwing defines are unique to the Xtensa port so have names
-    beginning with "XT_".
-
-    XT_SIMULATOR            Set this if building to run on the simulator.
-                            Takes advantage of certain simulator control
-                            and reporting facilities, and adjusts timing
-                            of periodic tick to provide a more acceptable
-                            performance in simulation (see XT_CLOCK_FREQ).
-                            Set by default unless PLATFORM is overridden.
-
-    XT_BOARD                Set this if building for a supported board.
-                            Be sure to specify the correct LSP for the
-                            board. See the example makefile for usage.
-
-    XT_CLOCK_FREQ=freq      Specifies the target processor's clock
-                            frequency in Hz. Used primarily to set the
-                            timer that generates the periodic interrupt.
-                            Defaults are provided and may be edited in
-                            xtensa_timer.h (see comments there also).
-                            Default for simulator provides more acceptable
-                            performance, but cannot provide real-time
-                            performance due to variation in simulation
-                            speed per host platform and insufficient
-                            cycles between interrupts to process them.
-                            Supported board platforms by default leave
-                            this undefined and compute the clock frequency
-                            at initialization unless this is explicitly
-                            defined.
-
-    XT_TICK_PER_SEC=n       Specifies the frequency of the periodic tick.
-
-    XT_TIMER_INDEX=n        Specifies which timer to use for periodic tick.
-                            Set this if your Xtensa processor configuration
-                            provides more than one suitable timer and you
-                            want to override the default. See xtensa_timer.h .
-
-    XT_INTEXC_HOOKS         Enables hooks in interrupt vector handlers
-                            to support dynamic installation of exception
-                            and interrupt handlers. Disabled by default.
-
-    XT_USE_OVLY             Enable code overlay support. It uses a mutex,
-                            hence configUSE_MUTEX must be enabled. This
-                            option is currently unsupported.
-
-    XT_USE_SWPRI            Enable software prioritization of interrupts.
-                            Enabling this will prioritize interrupts with
-                            higher bit numbers over those with lower bit
-                            numbers at the same level. This works only for
-                            low and medium priority interrupts that can be
-                            dispatched to C handlers.
-
-
-Register Usage and Stack Frames
--------------------------------
-
-The Xtensa architecture specifies two ABIs that determine how the general
-purpose registers a0-a15 are used: the standard windowed ABI use with
-the Xtensa windowed register file architecture, and the optional and
-more conventional Call0 ABI (required for Xtensa configurations without
-a windowed register file).
-
-Xtensa processors may have other special registers (including co-processor
-registers and other TIE "states") that are independent of this choice
-of ABI. See Xtensa documentation for more details.
-
-In the windowed ABI the registers of the current window are used as follows:
-    a0      = return address
-    a1      = stack pointer (alias sp)
-    a2      = first argument and result of call (in simple cases)
-    a3-7    = second through sixth arguments of call (in simple cases).
-              Note that complex or large arguments are passed on the
-              stack. Details are in the Xtensa Tools manuals.
-    a8-a15  = available for use as temporaries.
-There are no callee-save registers. The windowed hardware automatically
-saves registers a0-a3 on a call4, a0-a8 on a call8, a0-a12 on a call12,
-by rotating the register window. Hardware triggers window overflow and
-underflow exceptions as necessary when registers outside the current
-window need to be spilled to preallocated space in the stack frame, or
-restored. Complete details are in the Xtensa manuals. The entire windowed
-register file is saved and restored on interrupt or task context switch.
-
-The Call0 ABI does not make use of register windows, relying instead
-on a fixed set of 16 registers without window rotation.
-The Call0 ABI is more conventional and uses registers as follows:
-    a0      = return address
-    a1      = stack pointer (alias sp)
-    a2      = first argument and result of call (in simple cases)
-    a3-7    = second through sixth arguments of call (in simple cases).
-              Note that complex or large arguments are passed on the
-              stack. Details are in the Xtensa Tools manuals.
-    a8-a11  = scratch.
-    a12-a15 = callee-save (a function must preserve these for its caller).
-On a FreeRTOS API call, callee-save registers are saved only when a task
-context switch occurs, and other registers are not saved at all (the caller
-does not expect them to be preserved). On an interrupt, callee-saved
-registers might only be saved and restored when a task context-switch
-occurs, but all other registers are always saved and restored.
-
-An Xtensa processor has other special registers independent of the ABI,
-depending on the configuration (including co-processor registers and other
-TIE state) that are part of the task context. FreeRTOS preserves all such
-registers over an unsolicited context-switch triggered by an interrupt.
-However it does NOT preserve these over a solicited context-switch during
-a FreeRTOS API call. This bears some explanation. These special registers
-are either ignored by the compiler or treated as caller-saved, meaning
-that if kept "live" over a function call (ie. need to be preserved)
-they must be saved and restored by the caller. Since solicited entry to
-FreeRTOS is always made by a function call, FreeRTOS assumes the caller
-has saved any of these registers that are "live". FreeRTOS avoids a lot
-of overhead by not having to save and restore every special register
-(there can be many) on every solicited context switch.
-
-As a consequence, the application developer should NOT assume that special
-registers are preserved over a FreeRTOS API call such as vTaskDelay().
-If multiple tasks use a register, the caller must save and restore it.
-
-The saved context stack frames for context switches that occur as
-a result of interrupt handling (interrupt frame) or from task-level
-API calls (solicited frame) are described in human readable form in
-xtensa_context.h .  All suspended tasks have one of these two types
-of stack frames. The top of the suspended task's stack is pointed to
-by pxCurrentTCB->pxTopOfStack. A special location common to both stack
-frames differentiates solicited and interrupt stack frames.
-
-
-Improving Performance, Footprint, or Ease of Debugging
-------------------------------------------------------
-
-By default FreeRTOS for Xtensa is built with debug (-g) and without
-compiler optimizations (-O0). This makes debugging easier. Of course,
--O0 costs performance and usually also increases stack usage. To make
-FreeRTOS run faster you can change the Makefile to enable the desired
-optimizations or set a predefined optimization level (-O<level>) .
-
-Maximum performance is achieved with -O3 -ipa, but that might increase
-the footprint substantially. A good compromise is -O2. See the compiler
-manual for details.
-
-Minimal footprint is achieved by optimizing for space with -Os, at the
-cost of some performance. See the compiler manual for details.
-
-The Xtensa architecture port-specific assembly files are coded with no
-file-scope labels inside functions (all labels inside functions begin with
-".L"). This allows a profiler to accurately associate an address with a
-function, and also allows the debugger's stack trace to show the correct
-function wherever the program counter is within that function. However
-there are some tradeoffs in debugging. Local (".L") labels are not
-visible to the debugger, so the following limitations may be observed
-during debugging:
-- You cannot set a breakpoint on a local label inside a function.
-- Disassembly will show the entire function, but will get out of sync and
-  show incorrect opcodes if it crosses any padding before an aligned local
-  branch target (".L" label, not ".Ln"). Restart disassembly specifying an
-  address range explicitly between points where there is padding.
-Since FreeRTOS is provided in source form, it is not difficult to remove
-the ".L" and ".Ln" prefixes from local labels if you want them visible.
-They can also be made visible by passing the '-L' option to the assembler
-and linker (see the assembler and linker manuals for details).
-
-
-Interrupt and Exception Handling
---------------------------------
-
-FreeRTOS provides a complete set of efficient exception and first-level
-interrupt handlers installed at the appropriate exception and interrupt
-vector locations. The Xtensa architecture supports several different
-classes of exceptions and interrupts. Being a configurable architecture,
-many of these are optional, and the vector locations are determined by
-your processor configuration. (Note that Diamond cores are pre-configured
-with specific vector locations.) The handlers provided use conditional
-compilation to adapt to your processor configuration and include only
-the code that is needed.
-
-Xtensa vector locations may reside almost anywhere, including in ROM.
-The amount of code space available at each of these locations is
-often very small (e.g. due to following vectors). A small stub of
-code installed at the vector jumps to the corresponding handler,
-usually in RAM. The exception and interrupt handlers are defined in
-xtensa_vectors.S. They are not specific to FreeRTOS, but call into
-FreeRTOS where appropriate via macros defined in xtensa_rtos.h .
-
-The handlers provided for low and medium priority interrupts are just
-dispatchers that save relevant state and call user-definable handlers.
-See the files xtensa_vectors.S and xtensa_api.h for more details of how
-to create and install application-specific user interrupt handlers.
-Similarly, user-defined handlers can be installed for exceptions (other
-than a few which are always handled by the OS).
-
-The high priority interrupt handlers provided may be considered templates
-into which the application adds code to service specific interrupts.
-The places where application handlers should be inserted are tagged with
-the comment "USER_EDIT" in xtensa_vectors.S.
-
-This FreeRTOS port supports strict priority-based nesting of interrupts.
-An interrupt may only nest on top of one of strictly lower priority.
-Equal priority interrupts concurrently pending are handled in an
-application-defined sequence before any lower priority interrupts
-are handled. During interrupt and exception handling, the processor's
-interrupt level (PS.INTLEVEL) is used to control the interrupt priority
-level that can be accepted; interrupt sources are not controlled
-individually by FreeRTOS (the application is free to access the INTENABLE
-register directly to enable/disable individual interrupts, eg. using
-Xtensa HAL services). This approach provides the most deterministic
-bounds on interrupt latency (for a given priority) and stack depth.
-
-Software prioritization of interrupts at the same priority is controlled
-by the definition of XT_USE_SWPRI. See above for a description of this
-parameter.
-
-The following subsections describe the handling of each class of exception
-and interrupt in more detail. Many have nothing to do with FreeRTOS but
-are mentioned because there is code to handle them in xtensa_vectors.S.
-
-User Exception and Interrupt Handler (Low/Medium Priority):
-
-    All Xtensa 'general exceptions' come to the user, kernel, or double
-    exception vector.  The exception type is identified by the EXCCAUSE
-    special register (level 1 interrupts are one particular cause of a
-    general exception). This port sets up PS to direct all such exceptions
-    to the user vector. Exceptions taken at the other two vectors usually
-    indicate a kernel or application bug.
-
-    Level 1 interrupts are identified at the beginning of the handler
-    and are dispatched to a dedicated handler. Then, syscall and alloca
-    exceptions are identified and dispatched to special handlers described
-    below. After this, coprocessor exceptions are identified and dispatched
-    to the coprocessor handler.
-
-    Any remaining exceptions are processed as follows:
-
-    Having allocated the exception stack frame, the user exception handler
-    saves the current task state and sets up a C environment and enables
-    the high-priority class of interrupts (which do not interact with
-    FreeRTOS), then reads EXCCAUSE and uses the cause (number) to index
-    into a table of user-specified handlers. The correct handler is then
-    called. If the handler returns, the context is restored and control is
-    returned to the code that caused the exception. The user-defined handler
-    may alter the saved context, or any other system state, that allows the
-    faulting instruction to be retried.
-
-    If the cause is a level 1 (low-priority) or medium-priority interrupt,
-    the handler enables all interrupts above that priority level after
-    saving the task context. It then sets up the environment for C code
-    and then calls the handler (found in the handler table) for the
-    interrupt number. If the user has not specified a handler, then the
-    default handler will be called, which will terminate the program.
-
-    If the interrupt is for the system timer, it calls a special interrupt
-    handler for the system timer tick, which calls _frxt_timer_int then
-    clears its bit from the mask. This interrupt cannot be hooked by the
-    user-defined handler.
-
-    Finally, the handler calls _frxt_int_exit to allow FreeRTOS to perform
-    any scheduling necessary and return either to the interrupted task
-    or another.
-
-    If software prioritization is enabled, the handler will re-enable all
-    interrupts at the same level that are numerically higher than the current
-    one, before calling the user handler. This allows a higher priority
-    interrupt to pre-empt the lower priority handler.
-
-Medium Priority Interrupt Handlers:
-
-    Medium priority interrupts are those at levels 2 up to XCHAL_EXCM_LEVEL,
-    a configuration-specific maximum interrupt level affected by the global
-    'exception mode' bit in the processor status word (PS.EXCM).
-    Interrupt levels above XCHAL_EXCM_LEVEL are of the high-priority class.
-    The Xtensa hardware documentation considers medium priority interrupts
-    to be a special case of high-priority interrupts, but from a software
-    perspective they are very different.
-
-    Dispatch of medium-priority interrupts is discussed in the section
-    above.
-
-High Priority Interrupt Handlers:
-
-    High priority interrupts are those strictly above XCHAL_EXCM_LEVEL,
-    a configuration-specific maximum interrupt level affected by the
-    global 'exception mode' bit in the processor status word (PS.EXCM).
-    High priority handlers may not directly interact with FreeRTOS at all,
-    and are described here only for the sake of completeness. They must
-    be coded in assembler (may not be coded in C) and are intended to be
-    used for handling extremely high frequency hardware events that need
-    to be handled in only a few cycles. A high priority interrupt handler
-    may trigger a software interrupt at a medium or low priority level to
-    occasionally signal FreeRTOS. Please see Xtensa documentation.
-
-    There is a separate vector and a few special registers for each high
-    priority interrupt, providing for fast dispatch and efficient nesting
-    on top of lower priority interrupts. Handlers are templates included
-    only for the vectors that exist in your Xtensa processor configuration.
-    These templates are written for only one interrupt per high priority
-    level to minimize latency servicing very fast time-critical interrupts.
-    The vector code jumps to the corresponding first-level interrupt handler,
-    which then executes application-provided assembler code before returning
-    quickly to the interrupted task or lower priority handler.
-
-Kernel Exception Handler:
-
-    Kernel mode is not used in this port of FreeRTOS, and therefore kernel
-    exceptions should not happen. A stub is provided for the vector that
-    triggers the debugger (if connected) or calls _xt_panic to freeze the
-    processor should a kernel exception occur.
-
-Alloca Exception Handler:
-
-    Alloca exceptions are generated by the 'movsp' instruction, which
-    is used only in the windowed ABI. Its purpose is to allocate some
-    space on top of the stack. Because the window hardware may have
-    spilled some registers to the 16 byte "base save" area below the
-    stack pointer, it is necessary to protect those values. The alloca
-    handler accomplishes this quickly without setting up an interrupt
-    frame or entering FreeRTOS, by emulating a register underflow and
-    re-executing 'movsp'.
-
-Syscall Exception Handler:
-
-    Syscall exceptions are generated by a 'syscall' instruction.
-    The windowed ABI specifies that executing this instruction with
-    a value of zero in register a2 must spill any unsaved registers
-    in the windowed register file to their pre-determined locations
-    on the caller's stack. The handler does exactly that, and skips
-    over the 'syscall' instruction before returning to the caller.
-    If a2 is non-zero, the handler returns a2 == -1 to the caller.
-
-Co-Processor Exception Handler:
-
-    A co-processor exception is generated when a task accesses a
-    co-processor that it does not "own". Ownership represents which
-    task's state is currently in the co-processor. Co-processors are
-    context-switched "lazily" (on demand) only when a non-owning task
-    uses a co-processor instruction, otherwise a task retains ownership
-    even when it is preempted from the main processor. The co-processor
-    exception handler performs the context-switch and manages ownership.
-
-    Co-processors may not be used by any code outside the context of a
-    task. A co-processor exception triggered by code that is not part
-    of a running task is a fatal error and FreeRTOS for Xtensa will panic.
-    This restriction is intended to reduce the overhead of saving and
-    restoring co-processor state (which can be quite large) and in
-    particular remove that overhead from interrupt handlers.
-
-Debug Exception Handler:
-
-    A debug exception is caused as a result of running code, such as by
-    a 'break' instruction or hardware breakpoints and watchpoints, or
-    as a result of an external debug interrupt, such as from an OCD based
-    debugger or multiprocessor debug events ("breakin/breakout"). If the
-    processor is running in OCD mode under control of an OCD-based debugger,
-    the trigger event immediately halts the processor and gives control to
-    the OCD debugger. Otherwise control is transferred to the debug vector.
-    The debug vector handler calls the simulator if running on the ISS,
-    which then takes control and interacts with any attached debugger.
-    If running on hardware and not in OCD mode, debug exceptions are not
-    expected, so the debug handler calls _xt_panic to freeze the processor.
-
-Double Exception Handler:
-
-    A double exception is a general exception that happens while the
-    processor is in exception mode (PS.EXCM set), and thus indicates a
-    bug in kernel code. The double exception vector handler triggers
-    the debugger (if connected) or calls _xt_panic to freeze the
-    processor.
-
-Window Overflow and Underflow Exception Handlers:
-
-    Window overflow and underflow handlers are required for use of the
-    windowed ABI. Each has its own dedicated vector and highly optimized
-    code that is independent of OS. See Xtensa documentation for details.
-
-Hooks for Dynamic Installation of Handlers:
-
-    Optional hooks are provided in the user exception and low level
-    interrupt handler and all medium and high priority interrupt handlers,
-    to dynamically install a handler function (which may be coded in C,
-    unless in a high-priority interrupt handler). These hooks are enabled
-    and used by automatic regression tests, they are not part of a normal
-    FreeRTOS build. However an application is free to take advantage of
-    them. The interrupt/exception hooks are described in xtensa_rtos.h .
-
-    It is recommended that the application not make use of these hooks, but
-    rather use xt_set_interrupt_handler() and xt_set_exception_handler()
-    to install application-specific handlers. This method is more convenient
-    and allows arguments to be passed to the handlers. Software prioritization
-    of interrupts works only with this method. See xtensa_api.h for details.
-
-Overlay Support
-
-    Code overlays are currently not supported for FreeRTOS. This will be
-    supported in a future release. Make sure that the option XT_USE_OVLY is
-    never defined when building.
-
+Please see the Xtensa-specific README in this location for more details.
 
 -End-
diff --git a/portable/ThirdParty/XCC/Xtensa/xtensa_api.h b/portable/ThirdParty/XCC/Xtensa/xtensa_api.h
deleted file mode 100644
index 361dbdc9e..000000000
--- a/portable/ThirdParty/XCC/Xtensa/xtensa_api.h
+++ /dev/null
@@ -1,127 +0,0 @@
- /*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/*
- * Xtensa-specific API for RTOS ports.
- */
-
-#ifndef __XTENSA_API_H__
-#define __XTENSA_API_H__
-
-#include <xtensa/hal.h>
-
-#include "xtensa_context.h"
-
-
-/* Typedef for C-callable interrupt handler function */
-typedef void (*xt_handler)(void *);
-
-/* Typedef for C-callable exception handler function */
-typedef void (*xt_exc_handler)(XtExcFrame *);
-
-
-/*
--------------------------------------------------------------------------------
-  Call this function to set a handler for the specified exception.
-
-    n        - Exception number (type)
-    f        - Handler function address, NULL to uninstall handler.
-
-  The handler will be passed a pointer to the exception frame, which is created
-  on the stack of the thread that caused the exception.
-
-  If the handler returns, the thread context will be restored and the faulting
-  instruction will be retried. Any values in the exception frame that are
-  modified by the handler will be restored as part of the context. For details
-  of the exception frame structure see xtensa_context.h.
--------------------------------------------------------------------------------
-*/
-extern xt_exc_handler xt_set_exception_handler(int n, xt_exc_handler f);
-
-
-/*
--------------------------------------------------------------------------------
-  Call this function to set a handler for the specified interrupt.
-
-    n        - Interrupt number.
-    f        - Handler function address, NULL to uninstall handler.
-    arg      - Argument to be passed to handler.
--------------------------------------------------------------------------------
-*/
-extern xt_handler xt_set_interrupt_handler(int n, xt_handler f, void * arg);
-
-
-/*
--------------------------------------------------------------------------------
-  Call this function to enable the specified interrupts.
-
-    mask     - Bit mask of interrupts to be enabled.
-
-  Returns the previous state of the interrupt enables.
--------------------------------------------------------------------------------
-*/
-extern unsigned int xt_ints_on(unsigned int mask);
-
-
-/*
--------------------------------------------------------------------------------
-  Call this function to disable the specified interrupts.
-
-    mask     - Bit mask of interrupts to be disabled.
-
-  Returns the previous state of the interrupt enables.
--------------------------------------------------------------------------------
-*/
-extern unsigned int xt_ints_off(unsigned int mask);
-
-
-/*
--------------------------------------------------------------------------------
-  Call this function to set the specified (s/w) interrupt.
--------------------------------------------------------------------------------
-*/
-static inline void xt_set_intset(unsigned int arg)
-{
-    xthal_set_intset(arg);
-}
-
-
-/*
--------------------------------------------------------------------------------
-  Call this function to clear the specified (s/w or edge-triggered)
-  interrupt.
--------------------------------------------------------------------------------
-*/
-static inline void xt_set_intclear(unsigned int arg)
-{
-    xthal_set_intclear(arg);
-}
-
-
-#endif /* __XTENSA_API_H__ */
diff --git a/portable/ThirdParty/XCC/Xtensa/xtensa_config.h b/portable/ThirdParty/XCC/Xtensa/xtensa_config.h
deleted file mode 100644
index e3b31c06c..000000000
--- a/portable/ThirdParty/XCC/Xtensa/xtensa_config.h
+++ /dev/null
@@ -1,191 +0,0 @@
- /*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/*
- * Configuration-specific information for Xtensa build. This file must be
- * included in FreeRTOSConfig.h to properly set up the config-dependent
- * parameters correctly.
- *
- * NOTE: To enable thread-safe C library support, XT_USE_THREAD_SAFE_CLIB must
- * be defined to be > 0 somewhere above or on the command line.
- */
-
-#ifndef XTENSA_CONFIG_H
-#define XTENSA_CONFIG_H
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
-    extern "C" {
-#endif
-/* *INDENT-ON* */
-
-#include <xtensa/hal.h>
-#include <xtensa/config/core.h>
-#include <xtensa/config/system.h>   /* required for XSHAL_CLIB */
-
-#include "xtensa_context.h"
-
-
-/*-----------------------------------------------------------------------------
-*                                 STACK REQUIREMENTS
-*
-* This section defines the minimum stack size, and the extra space required to
-* be allocated for saving coprocessor state and/or C library state information
-* (if thread safety is enabled for the C library). The sizes are in bytes.
-*
-* Stack sizes for individual tasks should be derived from these minima based on
-* the maximum call depth of the task and the maximum level of interrupt nesting.
-* A minimum stack size is defined by XT_STACK_MIN_SIZE. This minimum is based
-* on the requirement for a task that calls nothing else but can be interrupted.
-* This assumes that interrupt handlers do not call more than a few levels deep.
-* If this is not true, i.e. one or more interrupt handlers make deep calls then
-* the minimum must be increased.
-*
-* If the Xtensa processor configuration includes coprocessors, then space is
-* allocated to save the coprocessor state on the stack.
-*
-* If thread safety is enabled for the C runtime library, (XT_USE_THREAD_SAFE_CLIB
-* is defined) then space is allocated to save the C library context in the TCB.
-*
-* Allocating insufficient stack space is a common source of hard-to-find errors.
-* During development, it is best to enable the FreeRTOS stack checking features.
-*
-* Usage:
-*
-* XT_USE_THREAD_SAFE_CLIB -- Define this to a nonzero value to enable thread-safe
-*                            use of the C library. This will require extra stack
-*                            space to be allocated for tasks that use the C library
-*                            reentrant functions. See below for more information.
-*
-* NOTE: The Xtensa toolchain supports multiple C libraries and not all of them
-* support thread safety. Check your core configuration to see which C library
-* was chosen for your system.
-*
-* XT_STACK_MIN_SIZE       -- The minimum stack size for any task. It is recommended
-*                            that you do not use a stack smaller than this for any
-*                            task. In case you want to use stacks smaller than this
-*                            size, you must verify that the smaller size(s) will work
-*                            under all operating conditions.
-*
-* XT_STACK_EXTRA          -- The amount of extra stack space to allocate for a task
-*                            that does not make C library reentrant calls. Add this
-*                            to the amount of stack space required by the task itself.
-*
-* XT_STACK_EXTRA_CLIB     -- The amount of space to allocate for C library state.
-*
------------------------------------------------------------------------------*/
-
-/* Extra space required for interrupt/exception hooks. */
-#ifdef XT_INTEXC_HOOKS
-  #ifdef __XTENSA_CALL0_ABI__
-    #define STK_INTEXC_EXTRA        0x200
-  #else
-    #define STK_INTEXC_EXTRA        0x180
-  #endif
-#else
-  #define STK_INTEXC_EXTRA          0
-#endif
-
-/* Check C library thread safety support and compute size of C library save area.
-   For the supported libraries, we enable thread safety by default, and this can
-   be overridden from the compiler/make command line. */
-#if (XSHAL_CLIB == XTHAL_CLIB_NEWLIB) || (XSHAL_CLIB == XTHAL_CLIB_XCLIB)
-  #ifndef XT_USE_THREAD_SAFE_CLIB
-    #define XT_USE_THREAD_SAFE_CLIB         1
-  #endif
-#else
-  #define XT_USE_THREAD_SAFE_CLIB           0
-#endif
-
-#if XT_USE_THREAD_SAFE_CLIB > 0u
-  #if XSHAL_CLIB == XTHAL_CLIB_XCLIB
-    #define XT_HAVE_THREAD_SAFE_CLIB        1
-    #if !defined __ASSEMBLER__
-      #include <sys/reent.h>
-      #define XT_CLIB_CONTEXT_AREA_SIZE     ((sizeof(struct _reent) + 15) + (-16))
-      #define XT_CLIB_GLOBAL_PTR            _reent_ptr
-      #define _REENT_INIT_PTR               _init_reent
-      #define _impure_ptr                   _reent_ptr
-
-      void _reclaim_reent(void * ptr);
-    #endif
-  #elif XSHAL_CLIB == XTHAL_CLIB_NEWLIB
-    #define XT_HAVE_THREAD_SAFE_CLIB        1
-    #if !defined __ASSEMBLER__
-      #include <sys/reent.h>
-      #define XT_CLIB_CONTEXT_AREA_SIZE     ((sizeof(struct _reent) + 15) + (-16))
-      #define XT_CLIB_GLOBAL_PTR            _impure_ptr
-    #endif
-  #else
-    #define XT_HAVE_THREAD_SAFE_CLIB        0
-    #error The selected C runtime library is not thread safe.
-  #endif
-#else
-  #define XT_CLIB_CONTEXT_AREA_SIZE         0
-#endif
-
-/*------------------------------------------------------------------------------
-  Extra size -- interrupt frame plus coprocessor save area plus hook space.
-  NOTE: Make sure XT_INTEXC_HOOKS is undefined unless you really need the hooks.
-------------------------------------------------------------------------------*/
-#ifdef __XTENSA_CALL0_ABI__
-  #define XT_XTRA_SIZE            (XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x10 + XT_CP_SIZE)
-#else
-  #define XT_XTRA_SIZE            (XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x20 + XT_CP_SIZE)
-#endif
-
-/*------------------------------------------------------------------------------
-  Space allocated for user code -- function calls and local variables.
-  NOTE: This number can be adjusted to suit your needs. You must verify that the
-  amount of space you reserve is adequate for the worst-case conditions in your
-  application.
-  NOTE: The windowed ABI requires more stack, since space has to be reserved
-  for spilling register windows.
-------------------------------------------------------------------------------*/
-#ifdef __XTENSA_CALL0_ABI__
-  #define XT_USER_SIZE            0x200
-#else
-  #define XT_USER_SIZE            0x400
-#endif
-
-/* Minimum recommended stack size. */
-#define XT_STACK_MIN_SIZE         ((XT_XTRA_SIZE + XT_USER_SIZE) / sizeof(unsigned char))
-
-/* OS overhead with and without C library thread context. */
-#define XT_STACK_EXTRA              (XT_XTRA_SIZE)
-#define XT_STACK_EXTRA_CLIB         (XT_XTRA_SIZE + XT_CLIB_CONTEXT_AREA_SIZE)
-
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
-    }
-#endif
-/* *INDENT-ON* */
-
-#endif /* XTENSA_CONFIG_H */
diff --git a/portable/ThirdParty/XCC/Xtensa/xtensa_context.S b/portable/ThirdParty/XCC/Xtensa/xtensa_context.S
deleted file mode 100644
index 33311c3bd..000000000
--- a/portable/ThirdParty/XCC/Xtensa/xtensa_context.S
+++ /dev/null
@@ -1,630 +0,0 @@
- /*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/*
- * XTENSA CONTEXT SAVE AND RESTORE ROUTINES
- *
- * Low-level Call0 functions for handling generic context save and restore of
- * registers not specifically addressed by the interrupt vectors and handlers.
- * Those registers (not handled by these functions) are PC, PS, A0, A1 (SP).
- * Except for the calls to RTOS functions, this code is generic to Xtensa.
- *
- * Note that in Call0 ABI, interrupt handlers are expected to preserve the callee-
- * save regs (A12-A15), which is always the case if the handlers are coded in C.
- * However A12, A13 are made available as scratch registers for interrupt dispatch
- * code, so are presumed saved anyway, and are always restored even in Call0 ABI.
- * Only A14, A15 are truly handled as callee-save regs.
- *
- * Because Xtensa is a configurable architecture, this port supports all user
- * generated configurations (except restrictions stated in the release notes).
- * This is accomplished by conditional compilation using macros and functions
- * defined in the Xtensa HAL (hardware adaptation layer) for your configuration.
- * Only the processor state included in your configuration is saved and restored,
- * including any processor state added by user configuration options or TIE.
- */
-
-/*  Warn nicely if this file gets named with a lowercase .s instead of .S:  */
-#define NOERROR #
-NOERROR: .error "C preprocessor needed for this file: make sure its filename\
- ends in uppercase .S, or use xt-xcc's -x assembler-with-cpp option."
-
-
-#include "xtensa_rtos.h"
-
-#ifdef XT_USE_OVLY
-#include <xtensa/overlay_os_asm.h>
-#endif
-
-    .text
-    .literal_position
-
-/*******************************************************************************
-
-_xt_context_save
-
-    !! MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION !!
-
-Saves all Xtensa processor state except PC, PS, A0, A1 (SP), A12, A13, in the
-interrupt stack frame defined in xtensa_rtos.h.
-Its counterpart is _xt_context_restore (which also restores A12, A13).
-
-Caller is expected to have saved PC, PS, A0, A1 (SP), A12, A13 in the frame.
-This function preserves A12 & A13 in order to provide the caller with 2 scratch
-regs that need not be saved over the call to this function. The choice of which
-2 regs to provide is governed by xthal_window_spill_nw and xthal_save_extra_nw,
-to avoid moving data more than necessary. Caller can assign regs accordingly.
-
-Entry Conditions:
-    A0  = Return address in caller.
-    A1  = Stack pointer of interrupted thread or handler ("interruptee").
-    Original A12, A13 have already been saved in the interrupt stack frame.
-    Other processor state except PC, PS, A0, A1 (SP), A12, A13, is as at the
-    point of interruption.
-    If windowed ABI, PS.EXCM = 1 (exceptions disabled).
-
-Exit conditions:
-    A0  = Return address in caller.
-    A1  = Stack pointer of interrupted thread or handler ("interruptee").
-    A12, A13 as at entry (preserved).
-    If windowed ABI, PS.EXCM = 1 (exceptions disabled).
-
-*******************************************************************************/
-
-    .global _xt_context_save
-    .type   _xt_context_save,@function
-    .align  4
-_xt_context_save:
-
-    s32i    a2,  sp, XT_STK_A2
-    s32i    a3,  sp, XT_STK_A3
-    s32i    a4,  sp, XT_STK_A4
-    s32i    a5,  sp, XT_STK_A5
-    s32i    a6,  sp, XT_STK_A6
-    s32i    a7,  sp, XT_STK_A7
-    s32i    a8,  sp, XT_STK_A8
-    s32i    a9,  sp, XT_STK_A9
-    s32i    a10, sp, XT_STK_A10
-    s32i    a11, sp, XT_STK_A11
-
-    /*
-    Call0 ABI callee-saved regs a12-15 do not need to be saved here.
-    a12-13 are the caller's responsibility so it can use them as scratch.
-    So only need to save a14-a15 here for Windowed ABI (not Call0).
-    */
-    #ifndef __XTENSA_CALL0_ABI__
-    s32i    a14, sp, XT_STK_A14
-    s32i    a15, sp, XT_STK_A15
-    #endif
-
-    rsr     a3,  SAR
-    s32i    a3,  sp, XT_STK_SAR
-
-    #if XCHAL_HAVE_LOOPS
-    rsr     a3,  LBEG
-    s32i    a3,  sp, XT_STK_LBEG
-    rsr     a3,  LEND
-    s32i    a3,  sp, XT_STK_LEND
-    rsr     a3,  LCOUNT
-    s32i    a3,  sp, XT_STK_LCOUNT
-    #endif
-
-    #if XT_USE_SWPRI
-    /* Save virtual priority mask */
-    movi    a3,  _xt_vpri_mask
-    l32i    a3,  a3, 0
-    s32i    a3,  sp, XT_STK_VPRI
-    #endif
-
-    #if XCHAL_EXTRA_SA_SIZE > 0 || !defined(__XTENSA_CALL0_ABI__)
-    mov     a9,  a0                     /* preserve ret addr */
-    #endif
-
-    #ifndef __XTENSA_CALL0_ABI__
-    /*
-    To spill the reg windows, temp. need pre-interrupt stack ptr and a4-15.
-    Need to save a9,12,13 temporarily (in frame temps) and recover originals.
-    Interrupts need to be disabled below XCHAL_EXCM_LEVEL and window overflow
-    and underflow exceptions disabled (assured by PS.EXCM == 1).
-    */
-    s32i    a12, sp, XT_STK_TMP0        /* temp. save stuff in stack frame */
-    s32i    a13, sp, XT_STK_TMP1
-    s32i    a9,  sp, XT_STK_TMP2
-
-    /*
-    Save the overlay state if we are supporting overlays. Since we just saved
-    three registers, we can conveniently use them here. Note that as of now,
-    overlays only work for windowed calling ABI.
-    */
-    #ifdef XT_USE_OVLY
-    l32i    a9,  sp, XT_STK_PC          /* recover saved PC */
-    _xt_overlay_get_state    a9, a12, a13
-    s32i    a9,  sp, XT_STK_OVLY        /* save overlay state */
-    #endif
-
-    l32i    a12, sp, XT_STK_A12         /* recover original a9,12,13 */
-    l32i    a13, sp, XT_STK_A13
-    l32i    a9,  sp, XT_STK_A9
-    addi    sp,  sp, XT_STK_FRMSZ       /* restore the interruptee's SP */
-    call0   xthal_window_spill_nw       /* preserves only a4,5,8,9,12,13 */
-    addi    sp,  sp, -XT_STK_FRMSZ
-    l32i    a12, sp, XT_STK_TMP0        /* recover stuff from stack frame */
-    l32i    a13, sp, XT_STK_TMP1
-    l32i    a9,  sp, XT_STK_TMP2
-    #endif
-
-    #if XCHAL_EXTRA_SA_SIZE > 0
-    /*
-    NOTE: Normally the xthal_save_extra_nw macro only affects address
-    registers a2-a5. It is theoretically possible for Xtensa processor
-    designers to write TIE that causes more address registers to be
-    affected, but it is generally unlikely. If that ever happens,
-    more registers need to be saved/restored around this macro invocation.
-    Here we assume a9,12,13 are preserved.
-    Future Xtensa tools releases might limit the regs that can be affected.
-    */
-    addi    a2,  sp, XT_STK_EXTRA       /* where to save it */
-    # if XCHAL_EXTRA_SA_ALIGN > 16
-    movi    a3, -XCHAL_EXTRA_SA_ALIGN
-    and     a2, a2, a3                  /* align dynamically >16 bytes */
-    # endif
-    call0   xthal_save_extra_nw         /* destroys a0,2,3,4,5 */
-    #endif
-
-    #if XCHAL_EXTRA_SA_SIZE > 0 || !defined(__XTENSA_CALL0_ABI__)
-    mov     a0, a9                      /* retrieve ret addr */
-    #endif
-
-    ret
-
-/*******************************************************************************
-
-_xt_context_restore
-
-    !! MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION !!
-
-Restores all Xtensa processor state except PC, PS, A0, A1 (SP) (and in Call0
-ABI, A14, A15 which are preserved by all interrupt handlers) from an interrupt
-stack frame defined in xtensa_rtos.h .
-Its counterpart is _xt_context_save (whose caller saved A12, A13).
-
-Caller is responsible to restore PC, PS, A0, A1 (SP).
-
-Entry Conditions:
-    A0  = Return address in caller.
-    A1  = Stack pointer of interrupted thread or handler ("interruptee").
-
-Exit conditions:
-    A0  = Return address in caller.
-    A1  = Stack pointer of interrupted thread or handler ("interruptee").
-    Other processor state except PC, PS, A0, A1 (SP), is as at the point
-    of interruption.
-
-*******************************************************************************/
-
-    .global _xt_context_restore
-    .type   _xt_context_restore,@function
-    .align  4
-_xt_context_restore:
-
-    #if XCHAL_EXTRA_SA_SIZE > 0
-    /*
-    NOTE: Normally the xthal_restore_extra_nw macro only affects address
-    registers a2-a5. It is theoretically possible for Xtensa processor
-    designers to write TIE that causes more address registers to be
-    affected, but it is generally unlikely. If that ever happens,
-    more registers need to be saved/restored around this macro invocation.
-    Here we only assume a13 is preserved.
-    Future Xtensa tools releases might limit the regs that can be affected.
-    */
-    mov     a13, a0                     /* preserve ret addr */
-    addi    a2,  sp, XT_STK_EXTRA       /* where to find it */
-    # if XCHAL_EXTRA_SA_ALIGN > 16
-    movi    a3, -XCHAL_EXTRA_SA_ALIGN
-    and     a2, a2, a3                  /* align dynamically >16 bytes */
-    # endif
-    call0   xthal_restore_extra_nw      /* destroys a0,2,3,4,5 */
-    mov     a0,  a13                    /* retrieve ret addr */
-    #endif
-
-    #if XCHAL_HAVE_LOOPS
-    l32i    a2,  sp, XT_STK_LBEG
-    l32i    a3,  sp, XT_STK_LEND
-    wsr     a2,  LBEG
-    l32i    a2,  sp, XT_STK_LCOUNT
-    wsr     a3,  LEND
-    wsr     a2,  LCOUNT
-    #endif
-
-    #ifdef XT_USE_OVLY
-    /*
-    If we are using overlays, this is a good spot to check if we need
-    to restore an overlay for the incoming task. Here we have a bunch
-    of registers to spare. Note that this step is going to use a few
-    bytes of storage below SP (SP-20 to SP-32) if an overlay is going
-    to be restored.
-    */
-    l32i    a2,  sp, XT_STK_PC          /* retrieve PC */
-    l32i    a3,  sp, XT_STK_PS          /* retrieve PS */
-    l32i    a4,  sp, XT_STK_OVLY        /* retrieve overlay state */
-    l32i    a5,  sp, XT_STK_A1          /* retrieve stack ptr */
-    _xt_overlay_check_map    a2, a3, a4, a5, a6
-    s32i    a2,  sp, XT_STK_PC          /* save updated PC */
-    s32i    a3,  sp, XT_STK_PS          /* save updated PS */
-    #endif
-
-    #ifdef XT_USE_SWPRI
-    /* Restore virtual interrupt priority and interrupt enable */
-    movi    a3,  _xt_intdata
-    l32i    a4,  a3, 0                  /* a4 = _xt_intenable */
-    l32i    a5,  sp, XT_STK_VPRI        /* a5 = saved _xt_vpri_mask */
-    and     a4,  a4, a5
-    wsr     a4,  INTENABLE              /* update INTENABLE */
-    s32i    a5,  a3, 4                  /* restore _xt_vpri_mask */
-    #endif
-
-    l32i    a3,  sp, XT_STK_SAR
-    l32i    a2,  sp, XT_STK_A2
-    wsr     a3,  SAR
-    l32i    a3,  sp, XT_STK_A3
-    l32i    a4,  sp, XT_STK_A4
-    l32i    a5,  sp, XT_STK_A5
-    l32i    a6,  sp, XT_STK_A6
-    l32i    a7,  sp, XT_STK_A7
-    l32i    a8,  sp, XT_STK_A8
-    l32i    a9,  sp, XT_STK_A9
-    l32i    a10, sp, XT_STK_A10
-    l32i    a11, sp, XT_STK_A11
-
-    /*
-    Call0 ABI callee-saved regs a12-15 do not need to be restored here.
-    However a12-13 were saved for scratch before XT_RTOS_INT_ENTER(),
-    so need to be restored anyway, despite being callee-saved in Call0.
-    */
-    l32i    a12, sp, XT_STK_A12
-    l32i    a13, sp, XT_STK_A13
-    #ifndef __XTENSA_CALL0_ABI__
-    l32i    a14, sp, XT_STK_A14
-    l32i    a15, sp, XT_STK_A15
-    #endif
-
-    ret
-
-
-/*******************************************************************************
-
-_xt_coproc_init
-
-Initializes global co-processor management data, setting all co-processors
-to "unowned". Leaves CPENABLE as it found it (does NOT clear it).
-
-Called during initialization of the RTOS, before any threads run.
-
-This may be called from normal Xtensa single-threaded application code which
-might use co-processors. The Xtensa run-time initialization enables all
-co-processors. They must remain enabled here, else a co-processor exception
-might occur outside of a thread, which the exception handler doesn't expect.
-
-Entry Conditions:
-    Xtensa single-threaded run-time environment is in effect.
-    No thread is yet running.
-
-Exit conditions:
-    None.
-
-Obeys ABI conventions per prototype:
-    void _xt_coproc_init(void)
-
-*******************************************************************************/
-
-#if XCHAL_CP_NUM > 0
-
-    .global _xt_coproc_init
-    .type   _xt_coproc_init,@function
-    .align  4
-_xt_coproc_init:
-    ENTRY0
-
-    /* Initialize thread co-processor ownerships to 0 (unowned). */
-    movi    a2, _xt_coproc_owner_sa         /* a2 = base of owner array */
-    addi    a3, a2, XCHAL_CP_MAX << 2       /* a3 = top+1 of owner array */
-    movi    a4, 0                           /* a4 = 0 (unowned) */
-1:  s32i    a4, a2, 0
-    addi    a2, a2, 4
-    bltu    a2, a3, 1b
-
-    RET0
-
-#endif
-
-
-/*******************************************************************************
-
-_xt_coproc_release
-
-Releases any and all co-processors owned by a given thread. The thread is
-identified by it's co-processor state save area defined in xtensa_context.h .
-
-Must be called before a thread's co-proc save area is deleted to avoid
-memory corruption when the exception handler tries to save the state.
-May be called when a thread terminates or completes but does not delete
-the co-proc save area, to avoid the exception handler having to save the
-thread's co-proc state before another thread can use it (optimization).
-
-Entry Conditions:
-    A2  = Pointer to base of co-processor state save area.
-
-Exit conditions:
-    None.
-
-Obeys ABI conventions per prototype:
-    void _xt_coproc_release(void * coproc_sa_base)
-
-*******************************************************************************/
-
-#if XCHAL_CP_NUM > 0
-
-    .global _xt_coproc_release
-    .type   _xt_coproc_release,@function
-    .align  4
-_xt_coproc_release:
-    ENTRY0                                  /* a2 = base of save area */
-
-    movi    a3, _xt_coproc_owner_sa         /* a3 = base of owner array */
-    addi    a4, a3, XCHAL_CP_MAX << 2       /* a4 = top+1 of owner array */
-    movi    a5, 0                           /* a5 = 0 (unowned) */
-
-    rsil    a6, XCHAL_EXCM_LEVEL            /* lock interrupts */
-
-1:  l32i    a7, a3, 0                       /* a7 = owner at a3 */
-    bne     a2, a7, 2f                      /* if (coproc_sa_base == owner) */
-    s32i    a5, a3, 0                       /*   owner = unowned */
-2:  addi    a3, a3, 1<<2                    /* a3 = next entry in owner array */
-    bltu    a3, a4, 1b                      /* repeat until end of array */
-
-3:  wsr     a6, PS                          /* restore interrupts */
-
-    RET0
-
-#endif
-
-
-/*******************************************************************************
-_xt_coproc_savecs
-
-If there is a current thread and it has a coprocessor state save area, then
-save all callee-saved state into this area. This function is called from the
-solicited context switch handler. It calls a system-specific function to get
-the coprocessor save area base address.
-
-Entry conditions:
-    - The thread being switched out is still the current thread.
-    - CPENABLE state reflects which coprocessors are active.
-    - Registers have been saved/spilled already.
-
-Exit conditions:
-    - All necessary CP callee-saved state has been saved.
-    - Registers a2-a7, a13-a15 have been trashed.
-
-Must be called from assembly code only, using CALL0.
-*******************************************************************************/
-#if XCHAL_CP_NUM > 0
-
-    .extern     _xt_coproc_sa_offset   /* external reference */
-
-    .global     _xt_coproc_savecs
-    .type       _xt_coproc_savecs,@function
-    .align      4
-_xt_coproc_savecs:
-
-    /* At entry, CPENABLE should be showing which CPs are enabled. */
-
-    rsr     a2, CPENABLE                /* a2 = which CPs are enabled      */
-    beqz    a2, .Ldone                  /* quick exit if none              */
-    mov     a14, a0                     /* save return address             */
-    call0   XT_RTOS_CP_STATE            /* get address of CP save area     */
-    mov     a0, a14                     /* restore return address          */
-    beqz    a15, .Ldone                 /* if none then nothing to do      */
-    s16i    a2, a15, XT_CP_CS_ST        /* save mask of CPs being stored   */
-    movi    a13, _xt_coproc_sa_offset   /* array of CP save offsets        */
-    l32i    a15, a15, XT_CP_ASA         /* a15 = base of aligned save area */
-
-#if XCHAL_CP0_SA_SIZE
-    bbci.l  a2, 0, 2f                   /* CP 0 not enabled                */
-    l32i    a14, a13, 0                 /* a14 = _xt_coproc_sa_offset[0]   */
-    add     a3, a14, a15                /* a3 = save area for CP 0         */
-    xchal_cp0_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
-2:
-#endif
-
-#if XCHAL_CP1_SA_SIZE
-    bbci.l  a2, 1, 2f                   /* CP 1 not enabled                */
-    l32i    a14, a13, 4                 /* a14 = _xt_coproc_sa_offset[1]   */
-    add     a3, a14, a15                /* a3 = save area for CP 1         */
-    xchal_cp1_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
-2:
-#endif
-
-#if XCHAL_CP2_SA_SIZE
-    bbci.l  a2, 2, 2f
-    l32i    a14, a13, 8
-    add     a3, a14, a15
-    xchal_cp2_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
-2:
-#endif
-
-#if XCHAL_CP3_SA_SIZE
-    bbci.l  a2, 3, 2f
-    l32i    a14, a13, 12
-    add     a3, a14, a15
-    xchal_cp3_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
-2:
-#endif
-
-#if XCHAL_CP4_SA_SIZE
-    bbci.l  a2, 4, 2f
-    l32i    a14, a13, 16
-    add     a3, a14, a15
-    xchal_cp4_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
-2:
-#endif
-
-#if XCHAL_CP5_SA_SIZE
-    bbci.l  a2, 5, 2f
-    l32i    a14, a13, 20
-    add     a3, a14, a15
-    xchal_cp5_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
-2:
-#endif
-
-#if XCHAL_CP6_SA_SIZE
-    bbci.l  a2, 6, 2f
-    l32i    a14, a13, 24
-    add     a3, a14, a15
-    xchal_cp6_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
-2:
-#endif
-
-#if XCHAL_CP7_SA_SIZE
-    bbci.l  a2, 7, 2f
-    l32i    a14, a13, 28
-    add     a3, a14, a15
-    xchal_cp7_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
-2:
-#endif
-
-.Ldone:
-    ret
-#endif
-
-
-/*******************************************************************************
-_xt_coproc_restorecs
-
-Restore any callee-saved coprocessor state for the incoming thread.
-This function is called from coprocessor exception handling, when giving
-ownership to a thread that solicited a context switch earlier. It calls a
-system-specific function to get the coprocessor save area base address.
-
-Entry conditions:
-    - The incoming thread is set as the current thread.
-    - CPENABLE is set up correctly for all required coprocessors.
-    - a2 = mask of coprocessors to be restored.
-
-Exit conditions:
-    - All necessary CP callee-saved state has been restored.
-    - CPENABLE - unchanged.
-    - Registers a2-a7, a13-a15 have been trashed.
-
-Must be called from assembly code only, using CALL0.
-*******************************************************************************/
-#if XCHAL_CP_NUM > 0
-
-    .global     _xt_coproc_restorecs
-    .type       _xt_coproc_restorecs,@function
-    .align      4
-_xt_coproc_restorecs:
-
-    mov     a14, a0                     /* save return address             */
-    call0   XT_RTOS_CP_STATE            /* get address of CP save area     */
-    mov     a0, a14                     /* restore return address          */
-    beqz    a15, .Ldone2                /* if none then nothing to do      */
-    l16ui   a3, a15, XT_CP_CS_ST        /* a3 = which CPs have been saved  */
-    xor     a3, a3, a2                  /* clear the ones being restored   */
-    s32i    a3, a15, XT_CP_CS_ST        /* update saved CP mask            */
-    movi    a13, _xt_coproc_sa_offset   /* array of CP save offsets        */
-    l32i    a15, a15, XT_CP_ASA         /* a15 = base of aligned save area */
-
-#if XCHAL_CP0_SA_SIZE
-    bbci.l  a2, 0, 2f                   /* CP 0 not enabled                */
-    l32i    a14, a13, 0                 /* a14 = _xt_coproc_sa_offset[0]   */
-    add     a3, a14, a15                /* a3 = save area for CP 0         */
-    xchal_cp0_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
-2:
-#endif
-
-#if XCHAL_CP1_SA_SIZE
-    bbci.l  a2, 1, 2f                   /* CP 1 not enabled                */
-    l32i    a14, a13, 4                 /* a14 = _xt_coproc_sa_offset[1]   */
-    add     a3, a14, a15                /* a3 = save area for CP 1         */
-    xchal_cp1_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
-2:
-#endif
-
-#if XCHAL_CP2_SA_SIZE
-    bbci.l  a2, 2, 2f
-    l32i    a14, a13, 8
-    add     a3, a14, a15
-    xchal_cp2_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
-2:
-#endif
-
-#if XCHAL_CP3_SA_SIZE
-    bbci.l  a2, 3, 2f
-    l32i    a14, a13, 12
-    add     a3, a14, a15
-    xchal_cp3_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
-2:
-#endif
-
-#if XCHAL_CP4_SA_SIZE
-    bbci.l  a2, 4, 2f
-    l32i    a14, a13, 16
-    add     a3, a14, a15
-    xchal_cp4_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
-2:
-#endif
-
-#if XCHAL_CP5_SA_SIZE
-    bbci.l  a2, 5, 2f
-    l32i    a14, a13, 20
-    add     a3, a14, a15
-    xchal_cp5_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
-2:
-#endif
-
-#if XCHAL_CP6_SA_SIZE
-    bbci.l  a2, 6, 2f
-    l32i    a14, a13, 24
-    add     a3, a14, a15
-    xchal_cp6_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
-2:
-#endif
-
-#if XCHAL_CP7_SA_SIZE
-    bbci.l  a2, 7, 2f
-    l32i    a14, a13, 28
-    add     a3, a14, a15
-    xchal_cp7_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
-2:
-#endif
-
-.Ldone2:
-    ret
-
-#endif
diff --git a/portable/ThirdParty/XCC/Xtensa/xtensa_context.h b/portable/ThirdParty/XCC/Xtensa/xtensa_context.h
deleted file mode 100644
index 8756213ea..000000000
--- a/portable/ThirdParty/XCC/Xtensa/xtensa_context.h
+++ /dev/null
@@ -1,355 +0,0 @@
- /*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/*
- * XTENSA CONTEXT FRAMES AND MACROS FOR RTOS ASSEMBLER SOURCES
- *
- * This header contains definitions and macros for use primarily by Xtensa
- * RTOS assembly coded source files. It includes and uses the Xtensa hardware
- * abstraction layer (HAL) to deal with config specifics. It may also be
- * included in C source files.
- *
- * !! Supports only Xtensa Exception Architecture 2 (XEA2). XEA1 not supported. !!
- *
- * NOTE: The Xtensa architecture requires stack pointer alignment to 16 bytes.
- */
-
-#ifndef XTENSA_CONTEXT_H
-#define XTENSA_CONTEXT_H
-
-#ifdef __ASSEMBLER__
-#include    <xtensa/coreasm.h>
-#endif
-
-#include    <xtensa/config/tie.h>
-#include    <xtensa/corebits.h>
-#include    <xtensa/config/system.h>
-
-
-/* Align a value up to nearest n-byte boundary, where n is a power of 2. */
-#define ALIGNUP(n, val) (((val) + (n)-1) & -(n))
-
-
-/*
--------------------------------------------------------------------------------
-  Macros that help define structures for both C and assembler.
--------------------------------------------------------------------------------
-*/
-#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__)
-
-#define STRUCT_BEGIN            .pushsection .text; .struct 0
-#define STRUCT_FIELD(ctype,size,asname,name)    asname: .space  size
-#define STRUCT_AFIELD(ctype,size,asname,name,n) asname: .space  (size)*(n)
-#define STRUCT_END(sname)       sname##Size:; .popsection
-
-#else
-
-#define STRUCT_BEGIN            typedef struct {
-#define STRUCT_FIELD(ctype,size,asname,name)    ctype   name;
-#define STRUCT_AFIELD(ctype,size,asname,name,n) ctype   name[n];
-#define STRUCT_END(sname)       } sname;
-
-#endif //_ASMLANGUAGE || __ASSEMBLER__
-
-
-/*
--------------------------------------------------------------------------------
-  INTERRUPT/EXCEPTION STACK FRAME FOR A THREAD OR NESTED INTERRUPT
-
-  A stack frame of this structure is allocated for any interrupt or exception.
-  It goes on the current stack. If the RTOS has a system stack for handling
-  interrupts, every thread stack must allow space for just one interrupt stack
-  frame, then nested interrupt stack frames go on the system stack.
-
-  The frame includes basic registers (explicit) and "extra" registers introduced
-  by user TIE or the use of the MAC16 option in the user's Xtensa config.
-  The frame size is minimized by omitting regs not applicable to user's config.
-
-  For Windowed ABI, this stack frame includes the interruptee's base save area,
-  another base save area to manage gcc nested functions, and a little temporary
-  space to help manage the spilling of the register windows.
--------------------------------------------------------------------------------
-*/
-
-STRUCT_BEGIN
-STRUCT_FIELD (long, 4, XT_STK_EXIT,     exit) /* exit point for dispatch */
-STRUCT_FIELD (long, 4, XT_STK_PC,       pc)   /* return PC */
-STRUCT_FIELD (long, 4, XT_STK_PS,       ps)   /* return PS */
-STRUCT_FIELD (long, 4, XT_STK_A0,       a0)
-STRUCT_FIELD (long, 4, XT_STK_A1,       a1)   /* stack pointer before interrupt */
-STRUCT_FIELD (long, 4, XT_STK_A2,       a2)
-STRUCT_FIELD (long, 4, XT_STK_A3,       a3)
-STRUCT_FIELD (long, 4, XT_STK_A4,       a4)
-STRUCT_FIELD (long, 4, XT_STK_A5,       a5)
-STRUCT_FIELD (long, 4, XT_STK_A6,       a6)
-STRUCT_FIELD (long, 4, XT_STK_A7,       a7)
-STRUCT_FIELD (long, 4, XT_STK_A8,       a8)
-STRUCT_FIELD (long, 4, XT_STK_A9,       a9)
-STRUCT_FIELD (long, 4, XT_STK_A10,      a10)
-STRUCT_FIELD (long, 4, XT_STK_A11,      a11)
-STRUCT_FIELD (long, 4, XT_STK_A12,      a12)
-STRUCT_FIELD (long, 4, XT_STK_A13,      a13)
-STRUCT_FIELD (long, 4, XT_STK_A14,      a14)
-STRUCT_FIELD (long, 4, XT_STK_A15,      a15)
-STRUCT_FIELD (long, 4, XT_STK_SAR,      sar)
-STRUCT_FIELD (long, 4, XT_STK_EXCCAUSE, exccause)
-STRUCT_FIELD (long, 4, XT_STK_EXCVADDR, excvaddr)
-#if XCHAL_HAVE_LOOPS
-STRUCT_FIELD (long, 4, XT_STK_LBEG,   lbeg)
-STRUCT_FIELD (long, 4, XT_STK_LEND,   lend)
-STRUCT_FIELD (long, 4, XT_STK_LCOUNT, lcount)
-#endif
-#ifndef __XTENSA_CALL0_ABI__
-/* Temporary space for saving stuff during window spill */
-STRUCT_FIELD (long, 4, XT_STK_TMP0,   tmp0)
-STRUCT_FIELD (long, 4, XT_STK_TMP1,   tmp1)
-STRUCT_FIELD (long, 4, XT_STK_TMP2,   tmp2)
-#endif
-#ifdef XT_USE_SWPRI
-/* Storage for virtual priority mask */
-STRUCT_FIELD (long, 4, XT_STK_VPRI,   vpri)
-#endif
-#ifdef XT_USE_OVLY
-/* Storage for overlay state */
-STRUCT_FIELD (long, 4, XT_STK_OVLY,   ovly)
-#endif
-STRUCT_END(XtExcFrame)
-
-#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__)
-#define XT_STK_NEXT1      XtExcFrameSize
-#else
-#define XT_STK_NEXT1      sizeof(XtExcFrame)
-#endif
-
-/* Allocate extra storage if needed */
-#if XCHAL_EXTRA_SA_SIZE != 0
-
-#if XCHAL_EXTRA_SA_ALIGN <= 16
-#define XT_STK_EXTRA            ALIGNUP(XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1)
-#else
-/* If need more alignment than stack, add space for dynamic alignment */
-#define XT_STK_EXTRA            (ALIGNUP(XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1) + XCHAL_EXTRA_SA_ALIGN)
-#endif
-#define XT_STK_NEXT2            (XT_STK_EXTRA + XCHAL_EXTRA_SA_SIZE)
-
-#else
-
-#define XT_STK_NEXT2            XT_STK_NEXT1
-
-#endif
-
-/*
--------------------------------------------------------------------------------
-  This is the frame size. Add space for 4 registers (interruptee's base save
-  area) and some space for gcc nested functions if any.
--------------------------------------------------------------------------------
-*/
-#define XT_STK_FRMSZ            (ALIGNUP(0x10, XT_STK_NEXT2) + 0x20)
-
-
-/*
--------------------------------------------------------------------------------
-  SOLICITED STACK FRAME FOR A THREAD
-
-  A stack frame of this structure is allocated whenever a thread enters the
-  RTOS kernel intentionally (and synchronously) to submit to thread scheduling.
-  It goes on the current thread's stack.
-
-  The solicited frame only includes registers that are required to be preserved
-  by the callee according to the compiler's ABI conventions, some space to save
-  the return address for returning to the caller, and the caller's PS register.
-
-  For Windowed ABI, this stack frame includes the caller's base save area.
-
-  Note on XT_SOL_EXIT field:
-      It is necessary to distinguish a solicited from an interrupt stack frame.
-      This field corresponds to XT_STK_EXIT in the interrupt stack frame and is
-      always at the same offset (0). It can be written with a code (usually 0)
-      to distinguish a solicted frame from an interrupt frame. An RTOS port may
-      opt to ignore this field if it has another way of distinguishing frames.
--------------------------------------------------------------------------------
-*/
-
-STRUCT_BEGIN
-#ifdef __XTENSA_CALL0_ABI__
-STRUCT_FIELD (long, 4, XT_SOL_EXIT, exit)
-STRUCT_FIELD (long, 4, XT_SOL_PC,   pc)
-STRUCT_FIELD (long, 4, XT_SOL_PS,   ps)
-STRUCT_FIELD (long, 4, XT_SOL_NEXT, next)
-STRUCT_FIELD (long, 4, XT_SOL_A12,  a12)    /* should be on 16-byte alignment */
-STRUCT_FIELD (long, 4, XT_SOL_A13,  a13)
-STRUCT_FIELD (long, 4, XT_SOL_A14,  a14)
-STRUCT_FIELD (long, 4, XT_SOL_A15,  a15)
-#else
-STRUCT_FIELD (long, 4, XT_SOL_EXIT, exit)
-STRUCT_FIELD (long, 4, XT_SOL_PC,   pc)
-STRUCT_FIELD (long, 4, XT_SOL_PS,   ps)
-STRUCT_FIELD (long, 4, XT_SOL_NEXT, next)
-STRUCT_FIELD (long, 4, XT_SOL_A0,   a0)    /* should be on 16-byte alignment */
-STRUCT_FIELD (long, 4, XT_SOL_A1,   a1)
-STRUCT_FIELD (long, 4, XT_SOL_A2,   a2)
-STRUCT_FIELD (long, 4, XT_SOL_A3,   a3)
-#endif
-STRUCT_END(XtSolFrame)
-
-/* Size of solicited stack frame */
-#define XT_SOL_FRMSZ            ALIGNUP(0x10, XtSolFrameSize)
-
-
-/*
--------------------------------------------------------------------------------
-  CO-PROCESSOR STATE SAVE AREA FOR A THREAD
-
-  The RTOS must provide an area per thread to save the state of co-processors
-  when that thread does not have control. Co-processors are context-switched
-  lazily (on demand) only when a new thread uses a co-processor instruction,
-  otherwise a thread retains ownership of the co-processor even when it loses
-  control of the processor. An Xtensa co-processor exception is triggered when
-  any co-processor instruction is executed by a thread that is not the owner,
-  and the context switch of that co-processor is then peformed by the handler.
-  Ownership represents which thread's state is currently in the co-processor.
-
-  Co-processors may not be used by interrupt or exception handlers. If an
-  co-processor instruction is executed by an interrupt or exception handler,
-  the co-processor exception handler will trigger a kernel panic and freeze.
-  This restriction is introduced to reduce the overhead of saving and restoring
-  co-processor state (which can be quite large) and in particular remove that
-  overhead from interrupt handlers.
-
-  The co-processor state save area may be in any convenient per-thread location
-  such as in the thread control block or above the thread stack area. It need
-  not be in the interrupt stack frame since interrupts don't use co-processors.
-
-  Along with the save area for each co-processor, two bitmasks with flags per
-  co-processor (laid out as in the CPENABLE reg) help manage context-switching
-  co-processors as efficiently as possible:
-
-  XT_CPENABLE
-    The contents of a non-running thread's CPENABLE register.
-    It represents the co-processors owned (and whose state is still needed)
-    by the thread. When a thread is preempted, its CPENABLE is saved here.
-    When a thread solicits a context-switch, its CPENABLE is cleared - the
-    compiler has saved the (caller-saved) co-proc state if it needs to.
-    When a non-running thread loses ownership of a CP, its bit is cleared.
-    When a thread runs, it's XT_CPENABLE is loaded into the CPENABLE reg.
-    Avoids co-processor exceptions when no change of ownership is needed.
-
-  XT_CPSTORED
-    A bitmask with the same layout as CPENABLE, a bit per co-processor.
-    Indicates whether the state of each co-processor is saved in the state
-    save area. When a thread enters the kernel, only the state of co-procs
-    still enabled in CPENABLE is saved. When the co-processor exception
-    handler assigns ownership of a co-processor to a thread, it restores
-    the saved state only if this bit is set, and clears this bit.
-
-  XT_CP_CS_ST
-    A bitmask with the same layout as CPENABLE, a bit per co-processor.
-    Indicates whether callee-saved state is saved in the state save area.
-    Callee-saved state is saved by itself on a solicited context switch,
-    and restored when needed by the coprocessor exception handler.
-    Unsolicited switches will cause the entire coprocessor to be saved
-    when necessary.
-
-  XT_CP_ASA
-    Pointer to the aligned save area.  Allows it to be aligned more than
-    the overall save area (which might only be stack-aligned or TCB-aligned).
-    Especially relevant for Xtensa cores configured with a very large data
-    path that requires alignment greater than 16 bytes (ABI stack alignment).
--------------------------------------------------------------------------------
-*/
-
-#if XCHAL_CP_NUM > 0
-
-/*  Offsets of each coprocessor save area within the 'aligned save area':  */
-#define XT_CP0_SA   0
-#define XT_CP1_SA   ALIGNUP(XCHAL_CP1_SA_ALIGN, XT_CP0_SA + XCHAL_CP0_SA_SIZE)
-#define XT_CP2_SA   ALIGNUP(XCHAL_CP2_SA_ALIGN, XT_CP1_SA + XCHAL_CP1_SA_SIZE)
-#define XT_CP3_SA   ALIGNUP(XCHAL_CP3_SA_ALIGN, XT_CP2_SA + XCHAL_CP2_SA_SIZE)
-#define XT_CP4_SA   ALIGNUP(XCHAL_CP4_SA_ALIGN, XT_CP3_SA + XCHAL_CP3_SA_SIZE)
-#define XT_CP5_SA   ALIGNUP(XCHAL_CP5_SA_ALIGN, XT_CP4_SA + XCHAL_CP4_SA_SIZE)
-#define XT_CP6_SA   ALIGNUP(XCHAL_CP6_SA_ALIGN, XT_CP5_SA + XCHAL_CP5_SA_SIZE)
-#define XT_CP7_SA   ALIGNUP(XCHAL_CP7_SA_ALIGN, XT_CP6_SA + XCHAL_CP6_SA_SIZE)
-#define XT_CP_SA_SIZE   ALIGNUP(16, XT_CP7_SA + XCHAL_CP7_SA_SIZE)
-
-/*  Offsets within the overall save area:  */
-#define XT_CPENABLE 0   /* (2 bytes) coprocessors active for this thread */
-#define XT_CPSTORED 2   /* (2 bytes) coprocessors saved for this thread */
-#define XT_CP_CS_ST 4   /* (2 bytes) coprocessor callee-saved regs stored for this thread */
-#define XT_CP_ASA   8   /* (4 bytes) ptr to aligned save area */
-/*  Overall size allows for dynamic alignment:  */
-#define XT_CP_SIZE  (12 + XT_CP_SA_SIZE + XCHAL_TOTAL_SA_ALIGN)
-#else
-#define XT_CP_SIZE  0
-#endif
-
-
-/*
--------------------------------------------------------------------------------
-  MACROS TO HANDLE ABI SPECIFICS OF FUNCTION ENTRY AND RETURN
-
-  Convenient where the frame size requirements are the same for both ABIs.
-    ENTRY(sz), RET(sz) are for framed functions (have locals or make calls).
-    ENTRY0,    RET0    are for frameless functions (no locals, no calls).
-
-  where size = size of stack frame in bytes (must be >0 and aligned to 16).
-  For framed functions the frame is created and the return address saved at
-  base of frame (Call0 ABI) or as determined by hardware (Windowed ABI).
-  For frameless functions, there is no frame and return address remains in a0.
-  Note: Because CPP macros expand to a single line, macros requiring multi-line
-  expansions are implemented as assembler macros.
--------------------------------------------------------------------------------
-*/
-
-#ifdef __ASSEMBLER__
-#ifdef __XTENSA_CALL0_ABI__
-  /* Call0 */
-  #define ENTRY(sz)     entry1  sz
-    .macro  entry1 size=0x10
-    addi    sp, sp, -\size
-    s32i    a0, sp, 0
-    .endm
-  #define ENTRY0
-  #define RET(sz)       ret1    sz
-    .macro  ret1 size=0x10
-    l32i    a0, sp, 0
-    addi    sp, sp, \size
-    ret
-    .endm
-  #define RET0          ret
-#else
-  /* Windowed */
-  #define ENTRY(sz)     entry   sp, sz
-  #define ENTRY0        entry   sp, 0x10
-  #define RET(sz)       retw
-  #define RET0          retw
-#endif
-#endif
-
-
-#endif /* XTENSA_CONTEXT_H */
diff --git a/portable/ThirdParty/XCC/Xtensa/xtensa_init.c b/portable/ThirdParty/XCC/Xtensa/xtensa_init.c
deleted file mode 100644
index b401aa8a8..000000000
--- a/portable/ThirdParty/XCC/Xtensa/xtensa_init.c
+++ /dev/null
@@ -1,70 +0,0 @@
- /*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/*
- * XTENSA INITIALIZATION ROUTINES CODED IN C
- *
- * This file contains miscellaneous Xtensa RTOS-generic initialization functions
- * that are implemented in C.
- */
-
-
-#ifdef XT_BOARD
-#include    <xtensa/xtbsp.h>
-#endif
-
-#include    "xtensa_rtos.h"
-
-#ifdef XT_RTOS_TIMER_INT
-
-unsigned _xt_tick_divisor = 0;  /* cached number of cycles per tick */
-
-/*
-Compute and initialize at run-time the tick divisor (the number of
-processor clock cycles in an RTOS tick, used to set the tick timer).
-Called when the processor clock frequency is not known at compile-time.
-*/
-void _xt_tick_divisor_init(void)
-{
-#ifdef XT_CLOCK_FREQ
-
-    _xt_tick_divisor = (XT_CLOCK_FREQ / XT_TICK_PER_SEC);
-
-#else
-
-    #ifdef XT_BOARD
-    _xt_tick_divisor = xtbsp_clock_freq_hz() / XT_TICK_PER_SEC;
-    #else
-    #error "No way to obtain processor clock frequency"
-    #endif  /* XT_BOARD */
-
-#endif /* XT_CLOCK_FREQ */
-}
-
-#endif /* XT_RTOS_TIMER_INT */
diff --git a/portable/ThirdParty/XCC/Xtensa/xtensa_intr.c b/portable/ThirdParty/XCC/Xtensa/xtensa_intr.c
deleted file mode 100644
index 79fe315ee..000000000
--- a/portable/ThirdParty/XCC/Xtensa/xtensa_intr.c
+++ /dev/null
@@ -1,137 +0,0 @@
- /*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/*
- * Xtensa-specific interrupt and exception functions for RTOS ports.
- * Also see xtensa_intr_asm.S.
- */
-
-#include <stdlib.h>
-
-#include <xtensa/config/core.h>
-
-#include "xtensa_api.h"
-
-
-#if XCHAL_HAVE_EXCEPTIONS
-
-/* Handler table is in xtensa_intr_asm.S */
-
-extern xt_exc_handler _xt_exception_table[XCHAL_EXCCAUSE_NUM];
-
-
-/*
-  Default handler for unhandled exceptions.
-*/
-void xt_unhandled_exception(XtExcFrame *frame)
-{
-    exit(-1);
-}
-
-
-/*
-  This function registers a handler for the specified exception.
-  The function returns the address of the previous handler.
-  On error, it returns 0.
-*/
-xt_exc_handler xt_set_exception_handler(int n, xt_exc_handler f)
-{
-    xt_exc_handler old;
-
-    if( n < 0 || n >= XCHAL_EXCCAUSE_NUM )
-        return 0;       /* invalid exception number */
-
-    old = _xt_exception_table[n];
-
-    if (f) {
-        _xt_exception_table[n] = f;
-    }
-    else {
-        _xt_exception_table[n] = &xt_unhandled_exception;
-    }
-
-    return ((old == &xt_unhandled_exception) ? 0 : old);
-}
-
-#endif
-
-#if XCHAL_HAVE_INTERRUPTS
-
-/* Handler table is in xtensa_intr_asm.S */
-
-typedef struct xt_handler_table_entry {
-    void * handler;
-    void * arg;
-} xt_handler_table_entry;
-
-extern xt_handler_table_entry _xt_interrupt_table[XCHAL_NUM_INTERRUPTS];
-
-
-/*
-  Default handler for unhandled interrupts.
-*/
-void xt_unhandled_interrupt(void * arg)
-{
-    exit(-1);
-}
-
-
-/*
-  This function registers a handler for the specified interrupt. The "arg"
-  parameter specifies the argument to be passed to the handler when it is
-  invoked. The function returns the address of the previous handler.
-  On error, it returns 0.
-*/
-xt_handler xt_set_interrupt_handler(int n, xt_handler f, void * arg)
-{
-    xt_handler_table_entry * entry;
-    xt_handler               old;
-
-    if( n < 0 || n >= XCHAL_NUM_INTERRUPTS )
-        return 0;       /* invalid interrupt number */
-    if( Xthal_intlevel[n] > XCHAL_EXCM_LEVEL )
-        return 0;       /* priority level too high to safely handle in C */
-
-    entry = _xt_interrupt_table + n;
-    old   = entry->handler;
-
-    if (f) {
-        entry->handler = f;
-        entry->arg     = arg;
-    }
-    else {
-        entry->handler = &xt_unhandled_interrupt;
-        entry->arg     = (void*)n;
-    }
-
-    return ((old == &xt_unhandled_interrupt) ? 0 : old);
-}
-
-
-#endif /* XCHAL_HAVE_INTERRUPTS */
diff --git a/portable/ThirdParty/XCC/Xtensa/xtensa_intr_asm.S b/portable/ThirdParty/XCC/Xtensa/xtensa_intr_asm.S
deleted file mode 100644
index 287ba3e8a..000000000
--- a/portable/ThirdParty/XCC/Xtensa/xtensa_intr_asm.S
+++ /dev/null
@@ -1,183 +0,0 @@
- /*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/*
- * Xtensa interrupt handling data and assembly routines.
- * Also see xtensa_intr.c and xtensa_vectors.S.
- */
-
-#include <xtensa/hal.h>
-#include <xtensa/config/core.h>
-
-#include "xtensa_context.h"
-
-#if XCHAL_HAVE_INTERRUPTS
-
-/*
--------------------------------------------------------------------------------
-  INTENABLE virtualization information.
--------------------------------------------------------------------------------
-*/
-
-    .data
-    .global _xt_intdata
-    .align  8
-_xt_intdata:
-    .global _xt_intenable
-    .type   _xt_intenable,@object
-    .size   _xt_intenable,4
-    .global _xt_vpri_mask
-    .type   _xt_vpri_mask,@object
-    .size   _xt_vpri_mask,4
-
-_xt_intenable:     .word   0             /* Virtual INTENABLE     */
-_xt_vpri_mask:     .word   0xFFFFFFFF    /* Virtual priority mask */
-
-
-/*
--------------------------------------------------------------------------------
-  Table of C-callable interrupt handlers for each interrupt. Note that not all
-  slots can be filled, because interrupts at level > EXCM_LEVEL will not be
-  dispatched to a C handler by default.
--------------------------------------------------------------------------------
-*/
-
-    .data
-    .global _xt_interrupt_table
-    .align  8
-
-_xt_interrupt_table:
-
-    .set    i, 0
-    .rept   XCHAL_NUM_INTERRUPTS
-    .word   xt_unhandled_interrupt      /* handler address               */
-    .word   i                           /* handler arg (default: intnum) */
-    .set    i, i+1
-    .endr
-
-#endif /* XCHAL_HAVE_INTERRUPTS */
-
-
-#if XCHAL_HAVE_EXCEPTIONS
-
-/*
--------------------------------------------------------------------------------
-  Table of C-callable exception handlers for each exception. Note that not all
-  slots will be active, because some exceptions (e.g. coprocessor exceptions)
-  are always handled by the OS and cannot be hooked by user handlers.
--------------------------------------------------------------------------------
-*/
-
-    .data
-    .global _xt_exception_table
-    .align  4
-
-_xt_exception_table:
-    .rept   XCHAL_EXCCAUSE_NUM
-    .word   xt_unhandled_exception    /* handler address */
-    .endr
-
-#endif
-
-
-/*
--------------------------------------------------------------------------------
-  unsigned int xt_ints_on ( unsigned int mask )
-
-  Enables a set of interrupts. Does not simply set INTENABLE directly, but
-  computes it as a function of the current virtual priority.
-  Can be called from interrupt handlers.
--------------------------------------------------------------------------------
-*/
-
-    .text
-    .align  4
-    .global xt_ints_on
-    .type   xt_ints_on,@function
-
-xt_ints_on:
-
-    ENTRY0
-#if XCHAL_HAVE_INTERRUPTS
-    movi    a3, 0
-    movi    a4, _xt_intdata
-    xsr     a3, INTENABLE        /* Disables all interrupts   */
-    rsync
-    l32i    a3, a4, 0            /* a3 = _xt_intenable        */
-    l32i    a6, a4, 4            /* a6 = _xt_vpri_mask        */
-    or      a5, a3, a2           /* a5 = _xt_intenable | mask */
-    s32i    a5, a4, 0            /* _xt_intenable |= mask     */
-    and     a5, a5, a6           /* a5 = _xt_intenable & _xt_vpri_mask */
-    wsr     a5, INTENABLE        /* Reenable interrupts       */
-    mov     a2, a3               /* Previous mask             */
-#else
-    movi    a2, 0                /* Return zero */
-#endif
-    RET0
-
-    .size   xt_ints_on, . - xt_ints_on
-
-
-/*
--------------------------------------------------------------------------------
-  unsigned int xt_ints_off ( unsigned int mask )
-
-  Disables a set of interrupts. Does not simply set INTENABLE directly,
-  but computes it as a function of the current virtual priority.
-  Can be called from interrupt handlers.
--------------------------------------------------------------------------------
-*/
-
-    .text
-    .align  4
-    .global xt_ints_off
-    .type   xt_ints_off,@function
-
-xt_ints_off:
-
-    ENTRY0
-#if XCHAL_HAVE_INTERRUPTS
-    movi    a3, 0
-    movi    a4, _xt_intdata
-    xsr     a3, INTENABLE        /* Disables all interrupts    */
-    rsync
-    l32i    a3, a4, 0            /* a3 = _xt_intenable         */
-    l32i    a6, a4, 4            /* a6 = _xt_vpri_mask         */
-    or      a5, a3, a2           /* a5 = _xt_intenable | mask  */
-    xor     a5, a5, a2           /* a5 = _xt_intenable & ~mask */
-    s32i    a5, a4, 0            /* _xt_intenable &= ~mask     */
-    and     a5, a5, a6           /* a5 = _xt_intenable & _xt_vpri_mask */
-    wsr     a5, INTENABLE        /* Reenable interrupts        */
-    mov     a2, a3               /* Previous mask              */
-#else
-    movi    a2, 0                /* return zero */
-#endif
-    RET0
-
-    .size   xt_ints_off, . - xt_ints_off
diff --git a/portable/ThirdParty/XCC/Xtensa/xtensa_overlay_os_hook.c b/portable/ThirdParty/XCC/Xtensa/xtensa_overlay_os_hook.c
deleted file mode 100644
index e8523cac3..000000000
--- a/portable/ThirdParty/XCC/Xtensa/xtensa_overlay_os_hook.c
+++ /dev/null
@@ -1,76 +0,0 @@
- /*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/*
- * xtensa_overlay_os_hook.c -- Overlay manager OS hooks for FreeRTOS.
- */
-
-#include "FreeRTOS.h"
-#include "semphr.h"
-
-#if configUSE_MUTEX
-
-/* Mutex object that controls access to the overlay. Currently only one
- * overlay region is supported so one mutex suffices.
- */
-static SemaphoreHandle_t xt_overlay_mutex;
-
-
-/* This function should be overridden to provide OS specific init such
- * as the creation of a mutex lock that can be used for overlay locking.
- * Typically this mutex would be set up with priority inheritance. See
- * overlay manager documentation for more details.
- */
-void xt_overlay_init_os(void)
-{
-    /* Create the mutex for overlay access. Priority inheritance is
-     * required.
-     */
-    xt_overlay_mutex = xSemaphoreCreateMutex();
-}
-
-
-/* This function locks access to shared overlay resources, typically
- * by acquiring a mutex.
- */
-void xt_overlay_lock(void)
-{
-    xSemaphoreTake(xt_overlay_mutex, 0);
-}
-
-
-/* This function releases access to shared overlay resources, typically
- * by unlocking a mutex.
- */
-void xt_overlay_unlock(void)
-{
-    xSemaphoreGive(xt_overlay_mutex);
-}
-
-#endif
diff --git a/portable/ThirdParty/XCC/Xtensa/xtensa_rtos.h b/portable/ThirdParty/XCC/Xtensa/xtensa_rtos.h
deleted file mode 100644
index 88bd147d2..000000000
--- a/portable/ThirdParty/XCC/Xtensa/xtensa_rtos.h
+++ /dev/null
@@ -1,238 +0,0 @@
- /*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/*
- * RTOS-SPECIFIC INFORMATION FOR XTENSA RTOS ASSEMBLER SOURCES
- *                       (FreeRTOS Port)
- *
- * This header is the primary glue between generic Xtensa RTOS support
- * sources and a specific RTOS port for Xtensa.  It contains definitions
- * and macros for use primarily by Xtensa assembly coded source files.
- *
- * Macros in this header map callouts from generic Xtensa files to specific
- * RTOS functions. It may also be included in C source files.
- *
- * Xtensa RTOS ports support all RTOS-compatible configurations of the Xtensa
- * architecture, using the Xtensa hardware abstraction layer (HAL) to deal
- * with configuration specifics.
- *
- * Should be included by all Xtensa generic and RTOS port-specific sources.
- */
-
-#ifndef XTENSA_RTOS_H
-#define XTENSA_RTOS_H
-
-#ifdef __ASSEMBLER__
-#include    <xtensa/coreasm.h>
-#else
-#include    <xtensa/config/core.h>
-#endif
-
-#include    <xtensa/corebits.h>
-#include    <xtensa/config/system.h>
-#include    <xtensa/simcall.h>
-
-/*
-Include any RTOS specific definitions that are needed by this header.
-*/
-#include    <FreeRTOSConfig.h>
-
-/*
-Convert FreeRTOSConfig definitions to XTENSA definitions.
-However these can still be overridden from the command line.
-*/
-
-#ifndef XT_SIMULATOR
-  #if configXT_SIMULATOR
-    #define XT_SIMULATOR             1  /* Simulator mode */
-  #endif
-#endif
-
-#ifndef XT_BOARD
-  #if configXT_BOARD
-    #define XT_BOARD                 1  /* Board mode */
-  #endif
-#endif
-
-#ifndef XT_TIMER_INDEX
-  #if defined configXT_TIMER_INDEX
-    #define XT_TIMER_INDEX           configXT_TIMER_INDEX  /* Index of hardware timer to be used */
-  #endif
-#endif
-
-#ifndef XT_INTEXC_HOOKS
-  #if configXT_INTEXC_HOOKS
-    #define XT_INTEXC_HOOKS          1  /* Enables exception hooks */
-  #endif
-#endif
-
-#if (!XT_SIMULATOR) && (!XT_BOARD)
-  #error Either XT_SIMULATOR or XT_BOARD must be defined.
-#endif
-
-
-/*
-Name of RTOS (for messages).
-*/
-#define XT_RTOS_NAME    FreeRTOS
-
-/*
-Check some Xtensa configuration requirements and report error if not met.
-Error messages can be customize to the RTOS port.
-*/
-
-#if !XCHAL_HAVE_XEA2
-#error "FreeRTOS/Xtensa requires XEA2 (exception architecture 2)."
-#endif
-
-
-/*******************************************************************************
-
-RTOS CALLOUT MACROS MAPPED TO RTOS PORT-SPECIFIC FUNCTIONS.
-
-Define callout macros used in generic Xtensa code to interact with the RTOS.
-The macros are simply the function names for use in calls from assembler code.
-Some of these functions may call back to generic functions in xtensa_context.h .
-
-*******************************************************************************/
-
-/*
-Inform RTOS of entry into an interrupt handler that will affect it.
-Allows RTOS to manage switch to any system stack and count nesting level.
-Called after minimal context has been saved, with interrupts disabled.
-RTOS port can call0 _xt_context_save to save the rest of the context.
-May only be called from assembly code by the 'call0' instruction.
-*/
-// void XT_RTOS_INT_ENTER(void)
-#define XT_RTOS_INT_ENTER   _frxt_int_enter
-
-/*
-Inform RTOS of completion of an interrupt handler, and give control to
-RTOS to perform thread/task scheduling, switch back from any system stack
-and restore the context, and return to the exit dispatcher saved in the
-stack frame at XT_STK_EXIT. RTOS port can call0 _xt_context_restore
-to save the context saved in XT_RTOS_INT_ENTER via _xt_context_save,
-leaving only a minimal part of the context to be restored by the exit
-dispatcher. This function does not return to the place it was called from.
-May only be called from assembly code by the 'call0' instruction.
-*/
-// void XT_RTOS_INT_EXIT(void)
-#define XT_RTOS_INT_EXIT    _frxt_int_exit
-
-/*
-Inform RTOS of the occurrence of a tick timer interrupt.
-If RTOS has no tick timer, leave XT_RTOS_TIMER_INT undefined.
-May be coded in or called from C or assembly, per ABI conventions.
-RTOS may optionally define XT_TICK_PER_SEC in its own way (eg. macro).
-*/
-// void XT_RTOS_TIMER_INT(void)
-#define XT_RTOS_TIMER_INT   _frxt_timer_int
-#define XT_TICK_PER_SEC     configTICK_RATE_HZ
-
-/*
-Return in a15 the base address of the co-processor state save area for the
-thread that triggered a co-processor exception, or 0 if no thread was running.
-The state save area is structured as defined in xtensa_context.h and has size
-XT_CP_SIZE. Co-processor instructions should only be used in thread code, never
-in interrupt handlers or the RTOS kernel. May only be called from assembly code
-and by the 'call0' instruction. A result of 0 indicates an unrecoverable error.
-The implementation may use only a2-4, a15 (all other regs must be preserved).
-*/
-// void* XT_RTOS_CP_STATE(void)
-#define XT_RTOS_CP_STATE    _frxt_task_coproc_state
-
-
-/*******************************************************************************
-
-HOOKS TO DYNAMICALLY INSTALL INTERRUPT AND EXCEPTION HANDLERS PER LEVEL.
-
-This Xtensa RTOS port provides hooks for dynamically installing exception
-and interrupt handlers to facilitate automated testing where each test
-case can install its own handler for user exceptions and each interrupt
-priority (level). This consists of an array of function pointers indexed
-by interrupt priority, with index 0 being the user exception handler hook.
-Each entry in the array is initially 0, and may be replaced by a function
-pointer of type XT_INTEXC_HOOK. A handler may be uninstalled by installing 0.
-
-The handler for low and medium priority obeys ABI conventions so may be coded
-in C. For the exception handler, the cause is the contents of the EXCCAUSE
-reg, and the result is -1 if handled, else the cause (still needs handling).
-For interrupt handlers, the cause is a mask of pending enabled interrupts at
-that level, and the result is the same mask with the bits for the handled
-interrupts cleared (those not cleared still need handling). This allows a test
-case to either pre-handle or override the default handling for the exception
-or interrupt level (see xtensa_vectors.S).
-
-High priority handlers (including NMI) must be coded in assembly, are always
-called by 'call0' regardless of ABI, must preserve all registers except a0,
-and must not use or modify the interrupted stack. The hook argument 'cause'
-is not passed and the result is ignored, so as not to burden the caller with
-saving and restoring a2 (it assumes only one interrupt per level - see the
-discussion in high priority interrupts in xtensa_vectors.S). The handler
-therefore should be coded to prototype 'void h(void)' even though it plugs
-into an array of handlers of prototype 'unsigned h(unsigned)'.
-
-To enable interrupt/exception hooks, compile the RTOS with '-DXT_INTEXC_HOOKS'.
-
-*******************************************************************************/
-
-#define XT_INTEXC_HOOK_NUM  (1 + XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI)
-
-#ifndef __ASSEMBLER__
-typedef unsigned (*XT_INTEXC_HOOK)(unsigned cause);
-extern  volatile XT_INTEXC_HOOK _xt_intexc_hooks[XT_INTEXC_HOOK_NUM];
-#endif
-
-
-/*******************************************************************************
-
-CONVENIENCE INCLUSIONS.
-
-Ensures RTOS specific files need only include this one Xtensa-generic header.
-These headers are included last so they can use the RTOS definitions above.
-
-*******************************************************************************/
-
-#include    "xtensa_context.h"
-
-#ifdef XT_RTOS_TIMER_INT
-#include    "xtensa_timer.h"
-#endif
-
-
-/*******************************************************************************
-
-Xtensa Port Version.
-
-*******************************************************************************/
-
-#define XTENSA_PORT_VERSION             1.7
-#define XTENSA_PORT_VERSION_STRING      "1.7"
-
-#endif /* XTENSA_RTOS_H */
diff --git a/portable/ThirdParty/XCC/Xtensa/xtensa_timer.h b/portable/ThirdParty/XCC/Xtensa/xtensa_timer.h
deleted file mode 100644
index 1cea00fb3..000000000
--- a/portable/ThirdParty/XCC/Xtensa/xtensa_timer.h
+++ /dev/null
@@ -1,164 +0,0 @@
- /*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/*
- * XTENSA INFORMATION FOR RTOS TICK TIMER AND CLOCK FREQUENCY
- *
- * This header contains definitions and macros for use primarily by Xtensa
- * RTOS assembly coded source files. It includes and uses the Xtensa hardware
- * abstraction layer (HAL) to deal with config specifics. It may also be
- * included in C source files.
- *
- * Edit this file to modify timer selection and to specify clock frequency and
- * tick duration to match timer interrupt to the real-time tick duration.
- *
- * If the RTOS has no timer interrupt, then there is no tick timer and the
- * clock frequency is irrelevant, so all of these macros are left undefined
- * and the Xtensa core configuration need not have a timer.
- */
-
-#ifndef XTENSA_TIMER_H
-#define XTENSA_TIMER_H
-
-#ifdef __ASSEMBLER__
-#include    <xtensa/coreasm.h>
-#endif
-
-#include    <xtensa/corebits.h>
-#include    <xtensa/config/system.h>
-
-#include    "xtensa_rtos.h"     /* in case this wasn't included directly */
-
-#include    <FreeRTOSConfig.h>
-
-/*
-Select timer to use for periodic tick, and determine its interrupt number
-and priority. User may specify a timer by defining XT_TIMER_INDEX with -D,
-in which case its validity is checked (it must exist in this core and must
-not be on a high priority interrupt - an error will be reported in invalid).
-Otherwise select the first low or medium priority interrupt timer available.
-*/
-#if XCHAL_NUM_TIMERS == 0
-
-  #error "This Xtensa configuration is unsupported, it has no timers."
-
-#else
-
-#ifndef XT_TIMER_INDEX
-  #if XCHAL_TIMER3_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
-    #if XCHAL_INT_LEVEL(XCHAL_TIMER3_INTERRUPT) <= XCHAL_EXCM_LEVEL
-      #undef  XT_TIMER_INDEX
-      #define XT_TIMER_INDEX    3
-    #endif
-  #endif
-  #if XCHAL_TIMER2_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
-    #if XCHAL_INT_LEVEL(XCHAL_TIMER2_INTERRUPT) <= XCHAL_EXCM_LEVEL
-      #undef  XT_TIMER_INDEX
-      #define XT_TIMER_INDEX    2
-    #endif
-  #endif
-  #if XCHAL_TIMER1_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
-    #if XCHAL_INT_LEVEL(XCHAL_TIMER1_INTERRUPT) <= XCHAL_EXCM_LEVEL
-      #undef  XT_TIMER_INDEX
-      #define XT_TIMER_INDEX    1
-    #endif
-  #endif
-  #if XCHAL_TIMER0_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
-    #if XCHAL_INT_LEVEL(XCHAL_TIMER0_INTERRUPT) <= XCHAL_EXCM_LEVEL
-      #undef  XT_TIMER_INDEX
-      #define XT_TIMER_INDEX    0
-    #endif
-  #endif
-#endif
-#ifndef XT_TIMER_INDEX
-  #error "There is no suitable timer in this Xtensa configuration."
-#endif
-
-#define XT_CCOMPARE             (CCOMPARE + XT_TIMER_INDEX)
-#define XT_TIMER_INTNUM         XCHAL_TIMER_INTERRUPT(XT_TIMER_INDEX)
-#define XT_TIMER_INTPRI         XCHAL_INT_LEVEL(XT_TIMER_INTNUM)
-#define XT_TIMER_INTEN          (1 << XT_TIMER_INTNUM)
-
-#if XT_TIMER_INTNUM == XTHAL_TIMER_UNCONFIGURED
-  #error "The timer selected by XT_TIMER_INDEX does not exist in this core."
-#elif XT_TIMER_INTPRI > XCHAL_EXCM_LEVEL
-  #error "The timer interrupt cannot be high priority (use medium or low)."
-#endif
-
-#endif /* XCHAL_NUM_TIMERS */
-
-/*
-Set processor clock frequency, used to determine clock divisor for timer tick.
-User should BE SURE TO ADJUST THIS for the Xtensa platform being used.
-If using a supported board via the board-independent API defined in xtbsp.h,
-this may be left undefined and frequency and tick divisor will be computed
-and cached during run-time initialization.
-
-NOTE ON SIMULATOR:
-Under the Xtensa instruction set simulator, the frequency can only be estimated
-because it depends on the speed of the host and the version of the simulator.
-Also because it runs much slower than hardware, it is not possible to achieve
-real-time performance for most applications under the simulator. A frequency
-too low does not allow enough time between timer interrupts, starving threads.
-To obtain a more convenient but non-real-time tick duration on the simulator,
-compile with xt-xcc option "-DXT_SIMULATOR".
-Adjust this frequency to taste (it's not real-time anyway!).
-*/
-#if defined(XT_SIMULATOR) && !defined(XT_CLOCK_FREQ)
-#define XT_CLOCK_FREQ       configCPU_CLOCK_HZ
-#endif
-
-#if !defined(XT_CLOCK_FREQ) && !defined(XT_BOARD)
-  #error "XT_CLOCK_FREQ must be defined for the target platform."
-#endif
-
-/*
-Default number of timer "ticks" per second (default 100 for 10ms tick).
-RTOS may define this in its own way (if applicable) in xtensa_rtos.h.
-User may redefine this to an optimal value for the application, either by
-editing this here or in xtensa_rtos.h, or compiling with xt-xcc option
-"-DXT_TICK_PER_SEC=<value>" where <value> is a suitable number.
-*/
-#ifndef XT_TICK_PER_SEC
-#define XT_TICK_PER_SEC    configTICK_RATE_HZ        /* 10 ms tick = 100 ticks per second */
-#endif
-
-/*
-Derivation of clock divisor for timer tick and interrupt (one per tick).
-*/
-#ifdef XT_CLOCK_FREQ
-#define XT_TICK_DIVISOR     (XT_CLOCK_FREQ / XT_TICK_PER_SEC)
-#endif
-
-#ifndef __ASSEMBLER__
-extern unsigned _xt_tick_divisor;
-extern void     _xt_tick_divisor_init(void);
-#endif
-
-#endif  /* XTENSA_TIMER_H */
diff --git a/portable/ThirdParty/XCC/Xtensa/xtensa_vectors.S b/portable/ThirdParty/XCC/Xtensa/xtensa_vectors.S
deleted file mode 100644
index de5ffe836..000000000
--- a/portable/ThirdParty/XCC/Xtensa/xtensa_vectors.S
+++ /dev/null
@@ -1,1924 +0,0 @@
- /*
- * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/*
-        XTENSA VECTORS AND LOW LEVEL HANDLERS FOR AN RTOS
-
-  Xtensa low level exception and interrupt vectors and handlers for an RTOS.
-
-  Interrupt handlers and user exception handlers support interaction with
-  the RTOS by calling XT_RTOS_INT_ENTER and XT_RTOS_INT_EXIT before and
-  after user's specific interrupt handlers. These macros are defined in
-  xtensa_<rtos>.h to call suitable functions in a specific RTOS.
-
-  Users can install application-specific interrupt handlers for low and
-  medium level interrupts, by calling xt_set_interrupt_handler(). These
-  handlers can be written in C, and must obey C calling convention. The
-  handler table is indexed by the interrupt number. Each handler may be
-  provided with an argument.
-
-  Note that the system timer interrupt is handled specially, and is
-  dispatched to the RTOS-specific handler. This timer cannot be hooked
-  by application code.
-
-  Optional hooks are also provided to install a handler per level at
-  run-time, made available by compiling this source file with
-  '-DXT_INTEXC_HOOKS' (useful for automated testing).
-
-!!  This file is a template that usually needs to be modified to handle       !!
-!!  application specific interrupts. Search USER_EDIT for helpful comments    !!
-!!  on where to insert handlers and how to write them.                        !!
-
-  Users can also install application-specific exception handlers in the
-  same way, by calling xt_set_exception_handler(). One handler slot is
-  provided for each exception type. Note that some exceptions are handled
-  by the porting layer itself, and cannot be taken over by application
-  code in this manner. These are the alloca, syscall, and coprocessor
-  exceptions.
-
-  The exception handlers can be written in C, and must follow C calling
-  convention. Each handler is passed a pointer to an exception frame as
-  its single argument. The exception frame is created on the stack, and
-  holds the saved context of the thread that took the exception. If the
-  handler returns, the context will be restored and the instruction that
-  caused the exception will be retried. If the handler makes any changes
-  to the saved state in the exception frame, the changes will be applied
-  when restoring the context.
-
-  Because Xtensa is a configurable architecture, this port supports all user
-  generated configurations (except restrictions stated in the release notes).
-  This is accomplished by conditional compilation using macros and functions
-  defined in the Xtensa HAL (hardware adaptation layer) for your configuration.
-  Only the relevant parts of this file will be included in your RTOS build.
-  For example, this file provides interrupt vector templates for all types and
-  all priority levels, but only the ones in your configuration are built.
-
-  NOTES on the use of 'call0' for long jumps instead of 'j':
-   1. This file should be assembled with the -mlongcalls option to xt-xcc.
-   2. The -mlongcalls compiler option causes 'call0 dest' to be expanded to
-      a sequence 'l32r a0, dest' 'callx0 a0' which works regardless of the
-      distance from the call to the destination. The linker then relaxes
-      it back to 'call0 dest' if it determines that dest is within range.
-      This allows more flexibility in locating code without the performance
-      overhead of the 'l32r' literal data load in cases where the destination
-      is in range of 'call0'. There is an additional benefit in that 'call0'
-      has a longer range than 'j' due to the target being word-aligned, so
-      the 'l32r' sequence is less likely needed.
-   3. The use of 'call0' with -mlongcalls requires that register a0 not be
-      live at the time of the call, which is always the case for a function
-      call but needs to be ensured if 'call0' is used as a jump in lieu of 'j'.
-   4. This use of 'call0' is independent of the C function call ABI.
-
- */
-
-#include "xtensa_rtos.h"
-
-
-/* Enable stack backtrace across exception/interrupt - see below */
-#define XT_DEBUG_BACKTRACE    1
-
-
-/*
---------------------------------------------------------------------------------
-  Defines used to access _xtos_interrupt_table.
---------------------------------------------------------------------------------
-*/
-#define XIE_HANDLER     0
-#define XIE_ARG         4
-#define XIE_SIZE        8
-
-/*
---------------------------------------------------------------------------------
-  Macro extract_msb - return the input with only the highest bit set.
-
-  Input  : "ain"  - Input value, clobbered.
-  Output : "aout" - Output value, has only one bit set, MSB of "ain".
-  The two arguments must be different AR registers.
---------------------------------------------------------------------------------
-*/
-
-    .macro  extract_msb     aout ain
-1:
-    addi    \aout, \ain, -1         /* aout = ain - 1        */
-    and     \ain, \ain, \aout       /* ain  = ain & aout     */
-    bnez    \ain, 1b                /* repeat until ain == 0 */
-    addi    \aout, \aout, 1         /* return aout + 1       */
-    .endm
-
-/*
---------------------------------------------------------------------------------
-  Macro dispatch_c_isr - dispatch interrupts to user ISRs.
-  This will dispatch to user handlers (if any) that are registered in the
-  XTOS dispatch table (_xtos_interrupt_table). These handlers would have
-  been registered by calling _xtos_set_interrupt_handler(). There is one
-  exception - the timer interrupt used by the OS will not be dispatched
-  to a user handler - this must be handled by the caller of this macro.
-
-  Level triggered and software interrupts are automatically deasserted by
-  this code.
-
-  ASSUMPTIONS:
-    -- PS.INTLEVEL is set to "level" at entry
-    -- PS.EXCM = 0, C calling enabled
-
-  NOTE: For CALL0 ABI, a12-a15 have not yet been saved.
-
-  NOTE: This macro will use registers a0 and a2-a6. The arguments are:
-    level -- interrupt level
-    mask  -- interrupt bitmask for this level
---------------------------------------------------------------------------------
-*/
-
-    .macro  dispatch_c_isr    level  mask
-
-    /* Get mask of pending, enabled interrupts at this level into a2. */
-
-.L_xt_user_int_&level&:
-    rsr     a2, INTENABLE
-    rsr     a3, INTERRUPT
-    movi    a4, \mask
-    and     a2, a2, a3
-    and     a2, a2, a4
-    beqz    a2, 9f                          /* nothing to do */
-
-    /* This bit of code provides a nice debug backtrace in the debugger.
-       It does take a few more instructions, so undef XT_DEBUG_BACKTRACE
-       if you want to save the cycles.
-    */
-    #if XT_DEBUG_BACKTRACE
-    #ifndef __XTENSA_CALL0_ABI__
-    rsr     a0, EPC_1 + \level - 1          /* return address */
-    movi    a4, 0xC0000000                  /* constant with top 2 bits set (call size) */
-    or      a0, a0, a4                      /* set top 2 bits */
-    addx2   a0, a4, a0                      /* clear top bit -- simulating call4 size   */
-    #endif
-    #endif
-
-    #ifdef XT_INTEXC_HOOKS
-    /* Call interrupt hook if present to (pre)handle interrupts. */
-    movi    a4, _xt_intexc_hooks
-    l32i    a4, a4, \level << 2
-    beqz    a4, 2f
-    #ifdef __XTENSA_CALL0_ABI__
-    callx0  a4
-    beqz    a2, 9f
-    #else
-    mov     a6, a2
-    callx4  a4
-    beqz    a6, 9f
-    mov     a2, a6
-    #endif
-2:
-    #endif
-
-    /* Now look up in the dispatch table and call user ISR if any. */
-    /* If multiple bits are set then MSB has highest priority.     */
-
-    extract_msb  a4, a2                     /* a4 = MSB of a2, a2 trashed */
-
-    #ifdef XT_USE_SWPRI
-    /* Enable all interrupts at this level that are numerically higher
-       than the one we just selected, since they are treated as higher
-       priority.
-    */
-    movi    a3, \mask                       /* a3 = all interrupts at this level */
-    add     a2, a4, a4                      /* a2 = a4 << 1 */
-    addi    a2, a2, -1                      /* a2 = mask of 1's <= a4 bit */
-    and     a2, a2, a3                      /* a2 = mask of all bits <= a4 at this level */
-    movi    a3, _xt_intdata
-    l32i    a6, a3, 4                       /* a6 = _xt_vpri_mask */
-    neg     a2, a2
-    addi    a2, a2, -1                      /* a2 = mask to apply */
-    and     a5, a6, a2                      /* mask off all bits <= a4 bit */
-    s32i    a5, a3, 4                       /* update _xt_vpri_mask */
-    rsr     a3, INTENABLE
-    and     a3, a3, a2                      /* mask off all bits <= a4 bit */
-    wsr     a3, INTENABLE
-    rsil    a3, \level - 1                  /* lower interrupt level by 1 */
-    #endif
-
-    movi    a3, XT_TIMER_INTEN              /* a3 = timer interrupt bit */
-    wsr     a4, INTCLEAR                    /* clear sw or edge-triggered interrupt */
-    beq     a3, a4, 7f                      /* if timer interrupt then skip table */
-
-    find_ms_setbit a3, a4, a3, 0            /* a3 = interrupt number */
-
-    movi    a4, _xt_interrupt_table
-    addx8   a3, a3, a4                      /* a3 = address of interrupt table entry */
-    l32i    a4, a3, XIE_HANDLER             /* a4 = handler address */
-    #ifdef __XTENSA_CALL0_ABI__
-    mov     a12, a6                         /* save in callee-saved reg */
-    l32i    a2, a3, XIE_ARG                 /* a2 = handler arg */
-    callx0  a4                              /* call handler */
-    mov     a2, a12
-    #else
-    mov     a2, a6                          /* save in windowed reg */
-    l32i    a6, a3, XIE_ARG                 /* a6 = handler arg */
-    callx4  a4                              /* call handler */
-    #endif
-
-    #ifdef XT_USE_SWPRI
-    j       8f
-    #else
-    j       .L_xt_user_int_&level&          /* check for more interrupts */
-    #endif
-
-7:
-
-    .ifeq XT_TIMER_INTPRI - \level
-.L_xt_user_int_timer_&level&:
-    /*
-    Interrupt handler for the RTOS tick timer if at this level.
-    We'll be reading the interrupt state again after this call
-    so no need to preserve any registers except a6 (vpri_mask).
-    */
-
-    #ifdef __XTENSA_CALL0_ABI__
-    mov     a12, a6
-    call0   XT_RTOS_TIMER_INT
-    mov     a2, a12
-    #else
-    mov     a2, a6
-    call4   XT_RTOS_TIMER_INT
-    #endif
-    .endif
-
-    #ifdef XT_USE_SWPRI
-    j       8f
-    #else
-    j       .L_xt_user_int_&level&          /* check for more interrupts */
-    #endif
-
-    #ifdef XT_USE_SWPRI
-8:
-    /* Restore old value of _xt_vpri_mask from a2. Also update INTENABLE from
-       virtual _xt_intenable which _could_ have changed during interrupt
-       processing. */
-
-    movi    a3, _xt_intdata
-    l32i    a4, a3, 0                       /* a4 = _xt_intenable    */
-    s32i    a2, a3, 4                       /* update _xt_vpri_mask  */
-    and     a4, a4, a2                      /* a4 = masked intenable */
-    wsr     a4, INTENABLE                   /* update INTENABLE      */
-    #endif
-
-9:
-    /* done */
-
-    .endm
-
-
-/*
---------------------------------------------------------------------------------
-  Panic handler.
-  Should be reached by call0 (preferable) or jump only. If call0, a0 says where
-  from. If on simulator, display panic message and abort, else loop indefinitely.
---------------------------------------------------------------------------------
-*/
-
-    .text
-    .global     _xt_panic
-    .type       _xt_panic,@function
-    .align      4
-    .literal_position
-
-_xt_panic:
-    #ifdef XT_SIMULATOR
-    addi    a4, a0, -3                      /* point to call0 */
-    movi    a3, _xt_panic_message
-    movi    a2, SYS_log_msg
-    simcall
-    movi    a2, SYS_gdb_abort
-    simcall
-    #else
-    rsil    a2, XCHAL_EXCM_LEVEL            /* disable all low & med ints */
-1:  j       1b                              /* loop infinitely */
-    #endif
-
-    .section    .rodata, "a"
-    .align      4
-
-_xt_panic_message:
-    .string "\n*** _xt_panic() was called from 0x%08x or jumped to. ***\n"
-
-
-/*
---------------------------------------------------------------------------------
-    Hooks to dynamically install handlers for exceptions and interrupts.
-    Allows automated regression frameworks to install handlers per test.
-    Consists of an array of function pointers indexed by interrupt level,
-    with index 0 containing the entry for user exceptions.
-    Initialized with all 0s, meaning no handler is installed at each level.
-    See comment in xtensa_rtos.h for more details.
---------------------------------------------------------------------------------
-*/
-
-    #ifdef XT_INTEXC_HOOKS
-    .data
-    .global     _xt_intexc_hooks
-    .type       _xt_intexc_hooks,@object
-    .align      4
-
-_xt_intexc_hooks:
-    .fill       XT_INTEXC_HOOK_NUM, 4, 0
-    #endif
-
-
-/*
---------------------------------------------------------------------------------
-  EXCEPTION AND LEVEL 1 INTERRUPT VECTORS AND LOW LEVEL HANDLERS
-  (except window exception vectors).
-
-  Each vector goes at a predetermined location according to the Xtensa
-  hardware configuration, which is ensured by its placement in a special
-  section known to the Xtensa linker support package (LSP). It performs
-  the minimum necessary before jumping to the handler in the .text section.
-
-  The corresponding handler goes in the normal .text section. It sets up
-  the appropriate stack frame, saves a few vector-specific registers and
-  calls XT_RTOS_INT_ENTER to save the rest of the interrupted context
-  and enter the RTOS, then sets up a C environment. It then calls the
-  user's interrupt handler code (which may be coded in C) and finally
-  calls XT_RTOS_INT_EXIT to transfer control to the RTOS for scheduling.
-
-  While XT_RTOS_INT_EXIT does not return directly to the interruptee,
-  eventually the RTOS scheduler will want to dispatch the interrupted
-  task or handler. The scheduler will return to the exit point that was
-  saved in the interrupt stack frame at XT_STK_EXIT.
---------------------------------------------------------------------------------
-*/
-
-
-/*
---------------------------------------------------------------------------------
-Debug Exception.
---------------------------------------------------------------------------------
-*/
-
-#if XCHAL_HAVE_DEBUG
-
-    .begin      literal_prefix .DebugExceptionVector
-    .section    .DebugExceptionVector.text, "ax"
-    .global     _DebugExceptionVector
-    .align      4
-    .literal_position
-
-_DebugExceptionVector:
-
-    #ifdef XT_SIMULATOR
-    /*
-    In the simulator, let the debugger (if any) handle the debug exception,
-    or simply stop the simulation:
-    */
-    wsr     a2, EXCSAVE+XCHAL_DEBUGLEVEL    /* save a2 where sim expects it */
-    movi    a2, SYS_gdb_enter_sktloop
-    simcall                                 /* have ISS handle debug exc. */
-    #elif 0 /* change condition to 1 to use the HAL minimal debug handler */
-    wsr     a3, EXCSAVE+XCHAL_DEBUGLEVEL
-    movi    a3, xthal_debugexc_defhndlr_nw  /* use default debug handler */
-    jx      a3
-    #else
-    wsr     a0, EXCSAVE+XCHAL_DEBUGLEVEL    /* save original a0 somewhere */
-    call0   _xt_panic                       /* does not return */
-    rfi     XCHAL_DEBUGLEVEL                /* make a0 point here not later */
-    #endif
-
-    .end        literal_prefix
-
-#endif
-
-/*
---------------------------------------------------------------------------------
-Double Exception.
-Double exceptions are not a normal occurrence. They indicate a bug of some kind.
---------------------------------------------------------------------------------
-*/
-
-#ifdef XCHAL_DOUBLEEXC_VECTOR_VADDR
-
-    .begin      literal_prefix .DoubleExceptionVector
-    .section    .DoubleExceptionVector.text, "ax"
-    .global     _DoubleExceptionVector
-    .align      4
-    .literal_position
-
-_DoubleExceptionVector:
-
-    #if XCHAL_HAVE_DEBUG
-    break   1, 4                            /* unhandled double exception */
-    #endif
-    call0   _xt_panic                       /* does not return */
-    rfde                                    /* make a0 point here not later */
-
-    .end        literal_prefix
-
-#endif /* XCHAL_DOUBLEEXC_VECTOR_VADDR */
-
-/*
---------------------------------------------------------------------------------
-Kernel Exception (including Level 1 Interrupt from kernel mode).
---------------------------------------------------------------------------------
-*/
-
-    .begin      literal_prefix .KernelExceptionVector
-    .section    .KernelExceptionVector.text, "ax"
-    .global     _KernelExceptionVector
-    .align      4
-    .literal_position
-
-_KernelExceptionVector:
-
-    wsr     a0, EXCSAVE_1                   /* preserve a0 */
-    call0   _xt_kernel_exc                  /* kernel exception handler */
-    /* never returns here - call0 is used as a jump (see note at top) */
-
-    .end        literal_prefix
-
-    .text
-    .align      4
-
-_xt_kernel_exc:
-    #if XCHAL_HAVE_DEBUG
-    break   1, 0                            /* unhandled kernel exception */
-    #endif
-    call0   _xt_panic                       /* does not return */
-    rfe                                     /* make a0 point here not there */
-
-
-/*
---------------------------------------------------------------------------------
-User Exception (including Level 1 Interrupt from user mode).
---------------------------------------------------------------------------------
-*/
-
-    .begin      literal_prefix .UserExceptionVector
-    .section    .UserExceptionVector.text, "ax"
-    .global     _UserExceptionVector
-    .type       _UserExceptionVector,@function
-    .align      4
-    .literal_position
-
-_UserExceptionVector:
-
-    wsr     a0, EXCSAVE_1                   /* preserve a0 */
-    call0   _xt_user_exc                    /* user exception handler */
-    /* never returns here - call0 is used as a jump (see note at top) */
-
-    .end        literal_prefix
-
-/*
---------------------------------------------------------------------------------
-  Insert some waypoints for jumping beyond the signed 8-bit range of
-  conditional branch instructions, so the conditional branchces to specific
-  exception handlers are not taken in the mainline. Saves some cycles in the
-  mainline.
---------------------------------------------------------------------------------
-*/
-
-    .text
-
-    #if XCHAL_HAVE_WINDOWED
-    .align      4
-_xt_to_alloca_exc:
-    call0   _xt_alloca_exc                  /* in window vectors section */
-    /* never returns here - call0 is used as a jump (see note at top) */
-    #endif
-
-    .align      4
-_xt_to_syscall_exc:
-    call0   _xt_syscall_exc
-    /* never returns here - call0 is used as a jump (see note at top) */
-
-    #if XCHAL_CP_NUM > 0
-    .align      4
-_xt_to_coproc_exc:
-    call0   _xt_coproc_exc
-    /* never returns here - call0 is used as a jump (see note at top) */
-    #endif
-
-
-/*
---------------------------------------------------------------------------------
-  User exception handler.
---------------------------------------------------------------------------------
-*/
-
-    .type       _xt_user_exc,@function
-    .align      4
-
-_xt_user_exc:
-
-    /* If level 1 interrupt then jump to the dispatcher */
-    rsr     a0, EXCCAUSE
-    beqi    a0, EXCCAUSE_LEVEL1INTERRUPT, _xt_lowint1
-
-    /* Handle any coprocessor exceptions. Rely on the fact that exception
-       numbers above EXCCAUSE_CP0_DISABLED all relate to the coprocessors.
-    */
-    #if XCHAL_CP_NUM > 0
-    bgeui   a0, EXCCAUSE_CP0_DISABLED, _xt_to_coproc_exc
-    #endif
-
-    /* Handle alloca and syscall exceptions */
-    #if XCHAL_HAVE_WINDOWED
-    beqi    a0, EXCCAUSE_ALLOCA,  _xt_to_alloca_exc
-    #endif
-    beqi    a0, EXCCAUSE_SYSCALL, _xt_to_syscall_exc
-
-    /* Handle all other exceptions. All can have user-defined handlers. */
-    /* NOTE: we'll stay on the user stack for exception handling.       */
-
-    /* Allocate exception frame and save minimal context. */
-    mov     a0, sp
-    addi    sp, sp, -XT_STK_FRMSZ
-    s32i    a0, sp, XT_STK_A1
-    #if XCHAL_HAVE_WINDOWED
-    s32e    a0, sp, -12                     /* for debug backtrace */
-    #endif
-    rsr     a0, PS                          /* save interruptee's PS */
-    s32i    a0, sp, XT_STK_PS
-    rsr     a0, EPC_1                       /* save interruptee's PC */
-    s32i    a0, sp, XT_STK_PC
-    rsr     a0, EXCSAVE_1                   /* save interruptee's a0 */
-    s32i    a0, sp, XT_STK_A0
-    #if XCHAL_HAVE_WINDOWED
-    s32e    a0, sp, -16                     /* for debug backtrace */
-    #endif
-    s32i    a12, sp, XT_STK_A12             /* _xt_context_save requires A12- */
-    s32i    a13, sp, XT_STK_A13             /* A13 to have already been saved */
-    call0   _xt_context_save
-
-    /* Save exc cause and vaddr into exception frame */
-    rsr     a0, EXCCAUSE
-    s32i    a0, sp, XT_STK_EXCCAUSE
-    rsr     a0, EXCVADDR
-    s32i    a0, sp, XT_STK_EXCVADDR
-
-    /* Set up PS for C, reenable hi-pri interrupts, and clear EXCM. */
-    #ifdef __XTENSA_CALL0_ABI__
-    movi    a0, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM
-    #else
-    movi    a0, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE
-    #endif
-    wsr     a0, PS
-
-    #ifdef XT_DEBUG_BACKTRACE
-    #ifndef __XTENSA_CALL0_ABI__
-    rsr     a0, EPC_1                       /* return address for debug backtrace */
-    movi    a5, 0xC0000000                  /* constant with top 2 bits set (call size) */
-    rsync                                   /* wait for WSR.PS to complete */
-    or      a0, a0, a5                      /* set top 2 bits */
-    addx2   a0, a5, a0                      /* clear top bit -- thus simulating call4 size */
-    #else
-    rsync                                   /* wait for WSR.PS to complete */
-    #endif
-    #endif
-
-    rsr     a2, EXCCAUSE                    /* recover exc cause */
-
-    #ifdef XT_INTEXC_HOOKS
-    /*
-    Call exception hook to pre-handle exceptions (if installed).
-    Pass EXCCAUSE in a2, and check result in a2 (if -1, skip default handling).
-    */
-    movi    a4, _xt_intexc_hooks
-    l32i    a4, a4, 0                       /* user exception hook index 0 */
-    beqz    a4, 1f
-.Ln_xt_user_exc_call_hook:
-    #ifdef __XTENSA_CALL0_ABI__
-    callx0  a4
-    beqi    a2, -1, .L_xt_user_done
-    #else
-    mov     a6, a2
-    callx4  a4
-    beqi    a6, -1, .L_xt_user_done
-    mov     a2, a6
-    #endif
-1:
-    #endif
-
-    rsr     a2, EXCCAUSE                    /* recover exc cause */
-    movi    a3, _xt_exception_table
-    addx4   a4, a2, a3                      /* a4 = address of exception table entry */
-    l32i    a4, a4, 0                       /* a4 = handler address */
-    #ifdef __XTENSA_CALL0_ABI__
-    mov     a2, sp                          /* a2 = pointer to exc frame */
-    callx0  a4                              /* call handler */
-    #else
-    mov     a6, sp                          /* a6 = pointer to exc frame */
-    callx4  a4                              /* call handler */
-    #endif
-
-.L_xt_user_done:
-
-    /* Restore context and return */
-    call0   _xt_context_restore
-    l32i    a0, sp, XT_STK_PS               /* retrieve interruptee's PS */
-    wsr     a0, PS
-    l32i    a0, sp, XT_STK_PC               /* retrieve interruptee's PC */
-    wsr     a0, EPC_1
-    l32i    a0, sp, XT_STK_A0               /* retrieve interruptee's A0 */
-    l32i    sp, sp, XT_STK_A1               /* remove exception frame */
-    rsync                                   /* ensure PS and EPC written */
-    rfe                                     /* PS.EXCM is cleared */
-
-
-/*
---------------------------------------------------------------------------------
-  Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
-  on entry and used to return to a thread or interrupted interrupt handler.
---------------------------------------------------------------------------------
-*/
-
-    .global     _xt_user_exit
-    .type       _xt_user_exit,@function
-    .align      4
-_xt_user_exit:
-    l32i    a0, sp, XT_STK_PS               /* retrieve interruptee's PS */
-    wsr     a0, PS
-    l32i    a0, sp, XT_STK_PC               /* retrieve interruptee's PC */
-    wsr     a0, EPC_1
-    l32i    a0, sp, XT_STK_A0               /* retrieve interruptee's A0 */
-    l32i    sp, sp, XT_STK_A1               /* remove interrupt stack frame */
-    rsync                                   /* ensure PS and EPC written */
-    rfe                                     /* PS.EXCM is cleared */
-
-
-/*
---------------------------------------------------------------------------------
-Syscall Exception Handler (jumped to from User Exception Handler).
-Syscall 0 is required to spill the register windows (no-op in Call 0 ABI).
-Only syscall 0 is handled here. Other syscalls return -1 to caller in a2.
---------------------------------------------------------------------------------
-*/
-
-    .text
-    .type       _xt_syscall_exc,@function
-    .align      4
-_xt_syscall_exc:
-
-    #ifdef __XTENSA_CALL0_ABI__
-    /*
-    Save minimal regs for scratch. Syscall 0 does nothing in Call0 ABI.
-    Use a minimal stack frame (16B) to save A2 & A3 for scratch.
-    PS.EXCM could be cleared here, but unlikely to improve worst-case latency.
-    rsr     a0, PS
-    addi    a0, a0, -PS_EXCM_MASK
-    wsr     a0, PS
-    */
-    addi    sp, sp, -16
-    s32i    a2, sp, 8
-    s32i    a3, sp, 12
-    #else   /* Windowed ABI */
-    /*
-    Save necessary context and spill the register windows.
-    PS.EXCM is still set and must remain set until after the spill.
-    Reuse context save function though it saves more than necessary.
-    For this reason, a full interrupt stack frame is allocated.
-    */
-    addi    sp, sp, -XT_STK_FRMSZ           /* allocate interrupt stack frame */
-    s32i    a12, sp, XT_STK_A12             /* _xt_context_save requires A12- */
-    s32i    a13, sp, XT_STK_A13             /* A13 to have already been saved */
-    call0   _xt_context_save
-    #endif
-
-    /*
-    Grab the interruptee's PC and skip over the 'syscall' instruction.
-    If it's at the end of a zero-overhead loop and it's not on the last
-    iteration, decrement loop counter and skip to beginning of loop.
-    */
-    rsr     a2, EPC_1                       /* a2 = PC of 'syscall' */
-    addi    a3, a2, 3                       /* ++PC                 */
-    #if XCHAL_HAVE_LOOPS
-    rsr     a0, LEND                        /* if (PC == LEND       */
-    bne     a3, a0, 1f
-    rsr     a0, LCOUNT                      /*     && LCOUNT != 0)  */
-    beqz    a0, 1f                          /* {                    */
-    addi    a0, a0, -1                      /*   --LCOUNT           */
-    rsr     a3, LBEG                        /*   PC = LBEG          */
-    wsr     a0, LCOUNT                      /* }                    */
-    #endif
-1:  wsr     a3, EPC_1                       /* update PC            */
-
-    /* Restore interruptee's context and return from exception. */
-    #ifdef __XTENSA_CALL0_ABI__
-    l32i    a2, sp, 8
-    l32i    a3, sp, 12
-    addi    sp, sp, 16
-    #else
-    call0   _xt_context_restore
-    addi    sp, sp, XT_STK_FRMSZ
-    #endif
-    movi    a0, -1
-    movnez  a2, a0, a2                      /* return -1 if not syscall 0 */
-    rsr     a0, EXCSAVE_1
-    rfe
-
-/*
---------------------------------------------------------------------------------
-Co-Processor Exception Handler (jumped to from User Exception Handler).
-These exceptions are generated by co-processor instructions, which are only
-allowed in thread code (not in interrupts or kernel code). This restriction is
-deliberately imposed to reduce the burden of state-save/restore in interrupts.
---------------------------------------------------------------------------------
-*/
-#if XCHAL_CP_NUM > 0
-
-    .section .rodata, "a"
-
-/* Offset to CP n save area in thread's CP save area. */
-    .global _xt_coproc_sa_offset
-    .type   _xt_coproc_sa_offset,@object
-    .align  16                      /* minimize crossing cache boundaries */
-_xt_coproc_sa_offset:
-    .word   XT_CP0_SA, XT_CP1_SA, XT_CP2_SA, XT_CP3_SA
-    .word   XT_CP4_SA, XT_CP5_SA, XT_CP6_SA, XT_CP7_SA
-
-/* Bitmask for CP n's CPENABLE bit. */
-    .type   _xt_coproc_mask,@object
-    .align  16,,8                   /* try to keep it all in one cache line */
-    .set    i, 0
-_xt_coproc_mask:
-    .rept   XCHAL_CP_MAX
-    .long   (i<<16) | (1<<i)    // upper 16-bits = i, lower = bitmask
-    .set    i, i+1
-    .endr
-
-    .data
-
-/* Owner thread of CP n, identified by thread's CP save area (0 = unowned). */
-    .global _xt_coproc_owner_sa
-    .type   _xt_coproc_owner_sa,@object
-    .align  16,,XCHAL_CP_MAX<<2     /* minimize crossing cache boundaries */
-_xt_coproc_owner_sa:
-    .space  XCHAL_CP_MAX << 2
-
-    .text
-
-
-    .align  4
-.L_goto_invalid:
-    j   .L_xt_coproc_invalid    /* not in a thread (invalid) */
-    .align  4
-.L_goto_done:
-    j   .L_xt_coproc_done
-
-
-/*
---------------------------------------------------------------------------------
-  Coprocessor exception handler.
-  At entry, only a0 has been saved (in EXCSAVE_1).
---------------------------------------------------------------------------------
-*/
-
-    .type   _xt_coproc_exc,@function
-    .align  4
-
-_xt_coproc_exc:
-
-    /* Allocate interrupt stack frame and save minimal context. */
-    mov     a0, sp                          /* sp == a1 */
-    addi    sp, sp, -XT_STK_FRMSZ           /* allocate interrupt stack frame */
-    s32i    a0, sp, XT_STK_A1               /* save pre-interrupt SP */
-    #if XCHAL_HAVE_WINDOWED
-    s32e    a0, sp, -12                     /* for debug backtrace */
-    #endif
-    rsr     a0, PS                          /* save interruptee's PS */
-    s32i    a0, sp, XT_STK_PS
-    rsr     a0, EPC_1                       /* save interruptee's PC */
-    s32i    a0, sp, XT_STK_PC
-    rsr     a0, EXCSAVE_1                   /* save interruptee's a0 */
-    s32i    a0, sp, XT_STK_A0
-    #if XCHAL_HAVE_WINDOWED
-    s32e    a0, sp, -16                     /* for debug backtrace */
-    #endif
-    movi    a0, _xt_user_exit               /* save exit point for dispatch */
-    s32i    a0, sp, XT_STK_EXIT
-
-    rsr     a0, EXCCAUSE
-    s32i    a5, sp, XT_STK_A5               /* save a5 */
-    addi    a5, a0, -EXCCAUSE_CP0_DISABLED  /* a5 = CP index */
-
-    /* Save a few more of interruptee's registers (a5 was already saved). */
-    s32i    a2,  sp, XT_STK_A2
-    s32i    a3,  sp, XT_STK_A3
-    s32i    a4,  sp, XT_STK_A4
-    s32i    a15, sp, XT_STK_A15
-
-    /* Get co-processor state save area of new owner thread. */
-    call0   XT_RTOS_CP_STATE                /* a15 = new owner's save area */
-    beqz    a15, .L_goto_invalid            /* not in a thread (invalid) */
-
-    /* Enable the co-processor's bit in CPENABLE. */
-    movi    a0, _xt_coproc_mask
-    rsr     a4, CPENABLE                    /* a4 = CPENABLE */
-    addx4   a0, a5, a0                      /* a0 = &_xt_coproc_mask[n] */
-    l32i    a0, a0, 0                       /* a0 = (n << 16) | (1 << n) */
-    movi    a3, _xt_coproc_owner_sa     /* (placed here for load slot) */
-    extui   a2, a0, 0, 16                   /* coprocessor bitmask portion */
-    or      a4, a4, a2                      /* a4 = CPENABLE | (1 << n) */
-    wsr     a4, CPENABLE
-
-    /* Get old coprocessor owner thread (save area ptr) and assign new one.  */
-    addx4   a3,  a5, a3                      /* a3 = &_xt_coproc_owner_sa[n] */
-    l32i    a2,  a3, 0                       /* a2 = old owner's save area */
-    s32i    a15, a3, 0                       /* _xt_coproc_owner_sa[n] = new */
-    rsync                                    /* ensure wsr.CPENABLE is complete */
-
-    /* Only need to context switch if new owner != old owner. */
-    beq     a15, a2, .L_goto_done           /* new owner == old, we're done */
-
-    /* If no old owner then nothing to save. */
-    beqz    a2, .L_check_new
-
-    /* If old owner not actively using CP then nothing to save. */
-    l16ui   a4,  a2,  XT_CPENABLE           /* a4 = old owner's CPENABLE */
-    bnone   a4,  a0,  .L_check_new          /* old owner not using CP    */
-
-.L_save_old:
-    /* Save old owner's coprocessor state. */
-
-    movi    a5, _xt_coproc_sa_offset
-
-    /* Mark old owner state as no longer active (CPENABLE bit n clear). */
-    xor     a4,  a4,  a0                    /* clear CP bit in CPENABLE    */
-    s16i    a4,  a2,  XT_CPENABLE           /* update old owner's CPENABLE */
-
-    extui   a4,  a0,  16,  5                /* a4 = CP index = n */
-    addx4   a5,  a4,  a5                    /* a5 = &_xt_coproc_sa_offset[n] */
-
-    /* Mark old owner state as saved (CPSTORED bit n set). */
-    l16ui   a4,  a2,  XT_CPSTORED           /* a4 = old owner's CPSTORED */
-    l32i    a5,  a5,  0                     /* a5 = XT_CP[n]_SA offset */
-    or      a4,  a4,  a0                    /* set CP in old owner's CPSTORED */
-    s16i    a4,  a2,  XT_CPSTORED           /* update old owner's CPSTORED */
-    l32i    a2, a2, XT_CP_ASA               /* ptr to actual (aligned) save area */
-    extui   a3, a0, 16, 5                   /* a3 = CP index = n */
-    add     a2, a2, a5                      /* a2 = old owner's area for CP n */
-
-    /*
-    The config-specific HAL macro invoked below destroys a2-5, preserves a0-1.
-    It is theoretically possible for Xtensa processor designers to write TIE
-    that causes more address registers to be affected, but it is generally
-    unlikely. If that ever happens, more registers needs to be saved/restored
-    around this macro invocation, and the value in a15 needs to be recomputed.
-    */
-    xchal_cpi_store_funcbody
-
-.L_check_new:
-    /* Check if any state has to be restored for new owner. */
-    /* NOTE: a15 = new owner's save area, cannot be zero when we get here. */
-
-    l16ui   a3,  a15, XT_CPSTORED           /* a3 = new owner's CPSTORED */
-    movi    a4, _xt_coproc_sa_offset
-    bnone   a3,  a0,  .L_check_cs           /* full CP not saved, check callee-saved */
-    xor     a3,  a3,  a0                    /* CPSTORED bit is set, clear it */
-    s16i    a3,  a15, XT_CPSTORED           /* update new owner's CPSTORED */
-
-    /* Adjust new owner's save area pointers to area for CP n. */
-    extui   a3,  a0, 16, 5                  /* a3 = CP index = n */
-    addx4   a4,  a3, a4                     /* a4 = &_xt_coproc_sa_offset[n] */
-    l32i    a4,  a4, 0                      /* a4 = XT_CP[n]_SA */
-    l32i    a5, a15, XT_CP_ASA              /* ptr to actual (aligned) save area */
-    add     a2,  a4, a5                     /* a2 = new owner's area for CP */
-
-    /*
-    The config-specific HAL macro invoked below destroys a2-5, preserves a0-1.
-    It is theoretically possible for Xtensa processor designers to write TIE
-    that causes more address registers to be affected, but it is generally
-    unlikely. If that ever happens, more registers needs to be saved/restored
-    around this macro invocation.
-    */
-    xchal_cpi_load_funcbody
-
-    /* Restore interruptee's saved registers. */
-    /* Can omit rsync for wsr.CPENABLE here because _xt_user_exit does it. */
-.L_xt_coproc_done:
-    l32i    a15, sp, XT_STK_A15
-    l32i    a5,  sp, XT_STK_A5
-    l32i    a4,  sp, XT_STK_A4
-    l32i    a3,  sp, XT_STK_A3
-    l32i    a2,  sp, XT_STK_A2
-    call0   _xt_user_exit                   /* return via exit dispatcher */
-    /* Never returns here - call0 is used as a jump (see note at top) */
-
-.L_check_cs:
-    /* a0 = CP mask in low bits, a15 = new owner's save area */
-    l16ui   a2, a15, XT_CP_CS_ST            /* a2 = mask of CPs saved    */
-    bnone   a2,  a0, .L_xt_coproc_done      /* if no match then done     */
-    and     a2,  a2, a0                     /* a2 = which CPs to restore */
-    extui   a2,  a2, 0, 8                   /* extract low 8 bits        */
-    s32i    a6,  sp, XT_STK_A6              /* save extra needed regs    */
-    s32i    a7,  sp, XT_STK_A7
-    s32i    a13, sp, XT_STK_A13
-    s32i    a14, sp, XT_STK_A14
-    call0   _xt_coproc_restorecs            /* restore CP registers      */
-    l32i    a6,  sp, XT_STK_A6              /* restore saved registers   */
-    l32i    a7,  sp, XT_STK_A7
-    l32i    a13, sp, XT_STK_A13
-    l32i    a14, sp, XT_STK_A14
-    j       .L_xt_coproc_done
-
-    /* Co-processor exception occurred outside a thread (not supported). */
-.L_xt_coproc_invalid:
-    #if XCHAL_HAVE_DEBUG
-    break   1, 1                            /* unhandled user exception */
-    #endif
-    call0   _xt_panic                       /* not in a thread (invalid) */
-    /* never returns */
-
-
-#endif /* XCHAL_CP_NUM */
-
-
-/*
--------------------------------------------------------------------------------
-  Level 1 interrupt dispatch. Assumes stack frame has not been allocated yet.
--------------------------------------------------------------------------------
-*/
-
-    .text
-    .type       _xt_lowint1,@function
-    .align      4
-
-_xt_lowint1:
-    mov     a0, sp                          /* sp == a1 */
-    addi    sp, sp, -XT_STK_FRMSZ           /* allocate interrupt stack frame */
-    s32i    a0, sp, XT_STK_A1               /* save pre-interrupt SP */
-    rsr     a0, PS                          /* save interruptee's PS */
-    s32i    a0, sp, XT_STK_PS
-    rsr     a0, EPC_1                       /* save interruptee's PC */
-    s32i    a0, sp, XT_STK_PC
-    rsr     a0, EXCSAVE_1                   /* save interruptee's a0 */
-    s32i    a0, sp, XT_STK_A0
-    movi    a0, _xt_user_exit               /* save exit point for dispatch */
-    s32i    a0, sp, XT_STK_EXIT
-
-    /* Save rest of interrupt context and enter RTOS. */
-    call0   XT_RTOS_INT_ENTER               /* common RTOS interrupt entry */
-
-    /* !! We are now on the RTOS system stack !! */
-
-    /* Set up PS for C, enable interrupts above this level and clear EXCM. */
-    #ifdef __XTENSA_CALL0_ABI__
-    movi    a0, PS_INTLEVEL(1) | PS_UM
-    #else
-    movi    a0, PS_INTLEVEL(1) | PS_UM | PS_WOE
-    #endif
-    wsr     a0, PS
-    rsync
-
-    /* OK to call C code at this point, dispatch user ISRs */
-
-    dispatch_c_isr 1 XCHAL_INTLEVEL1_MASK
-
-    /* Done handling interrupts, transfer control to OS */
-    call0   XT_RTOS_INT_EXIT                /* does not return directly here */
-
-
-/*
--------------------------------------------------------------------------------
-  MEDIUM PRIORITY (LEVEL 2+) INTERRUPT VECTORS AND LOW LEVEL HANDLERS.
-
-  Medium priority interrupts are by definition those with priority greater
-  than 1 and not greater than XCHAL_EXCM_LEVEL. These are disabled by
-  setting PS.EXCM and therefore can easily support a C environment for
-  handlers in C, and interact safely with an RTOS.
-
-  Each vector goes at a predetermined location according to the Xtensa
-  hardware configuration, which is ensured by its placement in a special
-  section known to the Xtensa linker support package (LSP). It performs
-  the minimum necessary before jumping to the handler in the .text section.
-
-  The corresponding handler goes in the normal .text section. It sets up
-  the appropriate stack frame, saves a few vector-specific registers and
-  calls XT_RTOS_INT_ENTER to save the rest of the interrupted context
-  and enter the RTOS, then sets up a C environment. It then calls the
-  user's interrupt handler code (which may be coded in C) and finally
-  calls XT_RTOS_INT_EXIT to transfer control to the RTOS for scheduling.
-
-  While XT_RTOS_INT_EXIT does not return directly to the interruptee,
-  eventually the RTOS scheduler will want to dispatch the interrupted
-  task or handler. The scheduler will return to the exit point that was
-  saved in the interrupt stack frame at XT_STK_EXIT.
--------------------------------------------------------------------------------
-*/
-
-#if XCHAL_EXCM_LEVEL >= 2
-
-    .begin      literal_prefix .Level2InterruptVector
-    .section    .Level2InterruptVector.text, "ax"
-    .global     _Level2Vector
-    .type       _Level2Vector,@function
-    .align      4
-    .literal_position
-
-_Level2Vector:
-    wsr     a0, EXCSAVE_2                   /* preserve a0 */
-    call0   _xt_medint2                     /* load interrupt handler */
-    /* never returns here - call0 is used as a jump (see note at top) */
-
-    .end        literal_prefix
-
-    .text
-    .type       _xt_medint2,@function
-    .align      4
-_xt_medint2:
-    mov     a0, sp                          /* sp == a1 */
-    addi    sp, sp, -XT_STK_FRMSZ           /* allocate interrupt stack frame */
-    s32i    a0, sp, XT_STK_A1               /* save pre-interrupt SP */
-    rsr     a0, EPS_2                       /* save interruptee's PS */
-    s32i    a0, sp, XT_STK_PS
-    rsr     a0, EPC_2                       /* save interruptee's PC */
-    s32i    a0, sp, XT_STK_PC
-    rsr     a0, EXCSAVE_2                   /* save interruptee's a0 */
-    s32i    a0, sp, XT_STK_A0
-    movi    a0, _xt_medint2_exit            /* save exit point for dispatch */
-    s32i    a0, sp, XT_STK_EXIT
-
-    /* Save rest of interrupt context and enter RTOS. */
-    call0   XT_RTOS_INT_ENTER               /* common RTOS interrupt entry */
-
-    /* !! We are now on the RTOS system stack !! */
-
-    /* Set up PS for C, enable interrupts above this level and clear EXCM. */
-    #ifdef __XTENSA_CALL0_ABI__
-    movi    a0, PS_INTLEVEL(2) | PS_UM
-    #else
-    movi    a0, PS_INTLEVEL(2) | PS_UM | PS_WOE
-    #endif
-    wsr     a0, PS
-    rsync
-
-    /* OK to call C code at this point, dispatch user ISRs */
-
-    dispatch_c_isr 2 XCHAL_INTLEVEL2_MASK
-
-    /* Done handling interrupts, transfer control to OS */
-    call0   XT_RTOS_INT_EXIT                /* does not return directly here */
-
-    /*
-    Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
-    on entry and used to return to a thread or interrupted interrupt handler.
-    */
-    .global     _xt_medint2_exit
-    .type       _xt_medint2_exit,@function
-    .align      4
-_xt_medint2_exit:
-    /* Restore only level-specific regs (the rest were already restored) */
-    l32i    a0, sp, XT_STK_PS               /* retrieve interruptee's PS */
-    wsr     a0, EPS_2
-    l32i    a0, sp, XT_STK_PC               /* retrieve interruptee's PC */
-    wsr     a0, EPC_2
-    l32i    a0, sp, XT_STK_A0               /* retrieve interruptee's A0 */
-    l32i    sp, sp, XT_STK_A1               /* remove interrupt stack frame */
-    rsync                                   /* ensure EPS and EPC written */
-    rfi     2
-
-#endif  /* Level 2 */
-
-#if XCHAL_EXCM_LEVEL >= 3
-
-    .begin      literal_prefix .Level3InterruptVector
-    .section    .Level3InterruptVector.text, "ax"
-    .global     _Level3Vector
-    .type       _Level3Vector,@function
-    .align      4
-    .literal_position
-
-_Level3Vector:
-    wsr     a0, EXCSAVE_3                   /* preserve a0 */
-    call0   _xt_medint3                     /* load interrupt handler */
-    /* never returns here - call0 is used as a jump (see note at top) */
-
-    .end        literal_prefix
-
-    .text
-    .type       _xt_medint3,@function
-    .align      4
-_xt_medint3:
-    mov     a0, sp                          /* sp == a1 */
-    addi    sp, sp, -XT_STK_FRMSZ           /* allocate interrupt stack frame */
-    s32i    a0, sp, XT_STK_A1               /* save pre-interrupt SP */
-    rsr     a0, EPS_3                       /* save interruptee's PS */
-    s32i    a0, sp, XT_STK_PS
-    rsr     a0, EPC_3                       /* save interruptee's PC */
-    s32i    a0, sp, XT_STK_PC
-    rsr     a0, EXCSAVE_3                   /* save interruptee's a0 */
-    s32i    a0, sp, XT_STK_A0
-    movi    a0, _xt_medint3_exit            /* save exit point for dispatch */
-    s32i    a0, sp, XT_STK_EXIT
-
-    /* Save rest of interrupt context and enter RTOS. */
-    call0   XT_RTOS_INT_ENTER               /* common RTOS interrupt entry */
-
-    /* !! We are now on the RTOS system stack !! */
-
-    /* Set up PS for C, enable interrupts above this level and clear EXCM. */
-    #ifdef __XTENSA_CALL0_ABI__
-    movi    a0, PS_INTLEVEL(3) | PS_UM
-    #else
-    movi    a0, PS_INTLEVEL(3) | PS_UM | PS_WOE
-    #endif
-    wsr     a0, PS
-    rsync
-
-    /* OK to call C code at this point, dispatch user ISRs */
-
-    dispatch_c_isr 3 XCHAL_INTLEVEL3_MASK
-
-    /* Done handling interrupts, transfer control to OS */
-    call0   XT_RTOS_INT_EXIT                /* does not return directly here */
-
-    /*
-    Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
-    on entry and used to return to a thread or interrupted interrupt handler.
-    */
-    .global     _xt_medint3_exit
-    .type       _xt_medint3_exit,@function
-    .align      4
-_xt_medint3_exit:
-    /* Restore only level-specific regs (the rest were already restored) */
-    l32i    a0, sp, XT_STK_PS               /* retrieve interruptee's PS */
-    wsr     a0, EPS_3
-    l32i    a0, sp, XT_STK_PC               /* retrieve interruptee's PC */
-    wsr     a0, EPC_3
-    l32i    a0, sp, XT_STK_A0               /* retrieve interruptee's A0 */
-    l32i    sp, sp, XT_STK_A1               /* remove interrupt stack frame */
-    rsync                                   /* ensure EPS and EPC written */
-    rfi     3
-
-#endif  /* Level 3 */
-
-#if XCHAL_EXCM_LEVEL >= 4
-
-    .begin      literal_prefix .Level4InterruptVector
-    .section    .Level4InterruptVector.text, "ax"
-    .global     _Level4Vector
-    .type       _Level4Vector,@function
-    .align      4
-    .literal_position
-
-_Level4Vector:
-    wsr     a0, EXCSAVE_4                   /* preserve a0 */
-    call0   _xt_medint4                     /* load interrupt handler */
-
-    .end        literal_prefix
-
-    .text
-    .type       _xt_medint4,@function
-    .align      4
-_xt_medint4:
-    mov     a0, sp                          /* sp == a1 */
-    addi    sp, sp, -XT_STK_FRMSZ           /* allocate interrupt stack frame */
-    s32i    a0, sp, XT_STK_A1               /* save pre-interrupt SP */
-    rsr     a0, EPS_4                       /* save interruptee's PS */
-    s32i    a0, sp, XT_STK_PS
-    rsr     a0, EPC_4                       /* save interruptee's PC */
-    s32i    a0, sp, XT_STK_PC
-    rsr     a0, EXCSAVE_4                   /* save interruptee's a0 */
-    s32i    a0, sp, XT_STK_A0
-    movi    a0, _xt_medint4_exit            /* save exit point for dispatch */
-    s32i    a0, sp, XT_STK_EXIT
-
-    /* Save rest of interrupt context and enter RTOS. */
-    call0   XT_RTOS_INT_ENTER               /* common RTOS interrupt entry */
-
-    /* !! We are now on the RTOS system stack !! */
-
-    /* Set up PS for C, enable interrupts above this level and clear EXCM. */
-    #ifdef __XTENSA_CALL0_ABI__
-    movi    a0, PS_INTLEVEL(4) | PS_UM
-    #else
-    movi    a0, PS_INTLEVEL(4) | PS_UM | PS_WOE
-    #endif
-    wsr     a0, PS
-    rsync
-
-    /* OK to call C code at this point, dispatch user ISRs */
-
-    dispatch_c_isr 4 XCHAL_INTLEVEL4_MASK
-
-    /* Done handling interrupts, transfer control to OS */
-    call0   XT_RTOS_INT_EXIT                /* does not return directly here */
-
-    /*
-    Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
-    on entry and used to return to a thread or interrupted interrupt handler.
-    */
-    .global     _xt_medint4_exit
-    .type       _xt_medint4_exit,@function
-    .align      4
-_xt_medint4_exit:
-    /* Restore only level-specific regs (the rest were already restored) */
-    l32i    a0, sp, XT_STK_PS               /* retrieve interruptee's PS */
-    wsr     a0, EPS_4
-    l32i    a0, sp, XT_STK_PC               /* retrieve interruptee's PC */
-    wsr     a0, EPC_4
-    l32i    a0, sp, XT_STK_A0               /* retrieve interruptee's A0 */
-    l32i    sp, sp, XT_STK_A1               /* remove interrupt stack frame */
-    rsync                                   /* ensure EPS and EPC written */
-    rfi     4
-
-#endif  /* Level 4 */
-
-#if XCHAL_EXCM_LEVEL >= 5
-
-    .begin      literal_prefix .Level5InterruptVector
-    .section    .Level5InterruptVector.text, "ax"
-    .global     _Level5Vector
-    .type       _Level5Vector,@function
-    .align      4
-    .literal_position
-
-_Level5Vector:
-    wsr     a0, EXCSAVE_5                   /* preserve a0 */
-    call0   _xt_medint5                     /* load interrupt handler */
-
-    .end        literal_prefix
-
-    .text
-    .type       _xt_medint5,@function
-    .align      4
-_xt_medint5:
-    mov     a0, sp                          /* sp == a1 */
-    addi    sp, sp, -XT_STK_FRMSZ           /* allocate interrupt stack frame */
-    s32i    a0, sp, XT_STK_A1               /* save pre-interrupt SP */
-    rsr     a0, EPS_5                       /* save interruptee's PS */
-    s32i    a0, sp, XT_STK_PS
-    rsr     a0, EPC_5                       /* save interruptee's PC */
-    s32i    a0, sp, XT_STK_PC
-    rsr     a0, EXCSAVE_5                   /* save interruptee's a0 */
-    s32i    a0, sp, XT_STK_A0
-    movi    a0, _xt_medint5_exit            /* save exit point for dispatch */
-    s32i    a0, sp, XT_STK_EXIT
-
-    /* Save rest of interrupt context and enter RTOS. */
-    call0   XT_RTOS_INT_ENTER               /* common RTOS interrupt entry */
-
-    /* !! We are now on the RTOS system stack !! */
-
-    /* Set up PS for C, enable interrupts above this level and clear EXCM. */
-    #ifdef __XTENSA_CALL0_ABI__
-    movi    a0, PS_INTLEVEL(5) | PS_UM
-    #else
-    movi    a0, PS_INTLEVEL(5) | PS_UM | PS_WOE
-    #endif
-    wsr     a0, PS
-    rsync
-
-    /* OK to call C code at this point, dispatch user ISRs */
-
-    dispatch_c_isr 5 XCHAL_INTLEVEL5_MASK
-
-    /* Done handling interrupts, transfer control to OS */
-    call0   XT_RTOS_INT_EXIT                /* does not return directly here */
-
-    /*
-    Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
-    on entry and used to return to a thread or interrupted interrupt handler.
-    */
-    .global     _xt_medint5_exit
-    .type       _xt_medint5_exit,@function
-    .align      4
-_xt_medint5_exit:
-    /* Restore only level-specific regs (the rest were already restored) */
-    l32i    a0, sp, XT_STK_PS               /* retrieve interruptee's PS */
-    wsr     a0, EPS_5
-    l32i    a0, sp, XT_STK_PC               /* retrieve interruptee's PC */
-    wsr     a0, EPC_5
-    l32i    a0, sp, XT_STK_A0               /* retrieve interruptee's A0 */
-    l32i    sp, sp, XT_STK_A1               /* remove interrupt stack frame */
-    rsync                                   /* ensure EPS and EPC written */
-    rfi     5
-
-#endif  /* Level 5 */
-
-#if XCHAL_EXCM_LEVEL >= 6
-
-    .begin      literal_prefix .Level6InterruptVector
-    .section    .Level6InterruptVector.text, "ax"
-    .global     _Level6Vector
-    .type       _Level6Vector,@function
-    .align      4
-    .literal_position
-
-_Level6Vector:
-    wsr     a0, EXCSAVE_6                   /* preserve a0 */
-    call0   _xt_medint6                     /* load interrupt handler */
-
-    .end        literal_prefix
-
-    .text
-    .type       _xt_medint6,@function
-    .align      4
-_xt_medint6:
-    mov     a0, sp                          /* sp == a1 */
-    addi    sp, sp, -XT_STK_FRMSZ           /* allocate interrupt stack frame */
-    s32i    a0, sp, XT_STK_A1               /* save pre-interrupt SP */
-    rsr     a0, EPS_6                       /* save interruptee's PS */
-    s32i    a0, sp, XT_STK_PS
-    rsr     a0, EPC_6                       /* save interruptee's PC */
-    s32i    a0, sp, XT_STK_PC
-    rsr     a0, EXCSAVE_6                   /* save interruptee's a0 */
-    s32i    a0, sp, XT_STK_A0
-    movi    a0, _xt_medint6_exit            /* save exit point for dispatch */
-    s32i    a0, sp, XT_STK_EXIT
-
-    /* Save rest of interrupt context and enter RTOS. */
-    call0   XT_RTOS_INT_ENTER               /* common RTOS interrupt entry */
-
-    /* !! We are now on the RTOS system stack !! */
-
-    /* Set up PS for C, enable interrupts above this level and clear EXCM. */
-    #ifdef __XTENSA_CALL0_ABI__
-    movi    a0, PS_INTLEVEL(6) | PS_UM
-    #else
-    movi    a0, PS_INTLEVEL(6) | PS_UM | PS_WOE
-    #endif
-    wsr     a0, PS
-    rsync
-
-    /* OK to call C code at this point, dispatch user ISRs */
-
-    dispatch_c_isr 6 XCHAL_INTLEVEL6_MASK
-
-    /* Done handling interrupts, transfer control to OS */
-    call0   XT_RTOS_INT_EXIT                /* does not return directly here */
-
-    /*
-    Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
-    on entry and used to return to a thread or interrupted interrupt handler.
-    */
-    .global     _xt_medint6_exit
-    .type       _xt_medint6_exit,@function
-    .align      4
-_xt_medint6_exit:
-    /* Restore only level-specific regs (the rest were already restored) */
-    l32i    a0, sp, XT_STK_PS               /* retrieve interruptee's PS */
-    wsr     a0, EPS_6
-    l32i    a0, sp, XT_STK_PC               /* retrieve interruptee's PC */
-    wsr     a0, EPC_6
-    l32i    a0, sp, XT_STK_A0               /* retrieve interruptee's A0 */
-    l32i    sp, sp, XT_STK_A1               /* remove interrupt stack frame */
-    rsync                                   /* ensure EPS and EPC written */
-    rfi     6
-
-#endif  /* Level 6 */
-
-
-/*******************************************************************************
-
-HIGH PRIORITY (LEVEL > XCHAL_EXCM_LEVEL) INTERRUPT VECTORS AND HANDLERS
-
-High priority interrupts are by definition those with priorities greater
-than XCHAL_EXCM_LEVEL. This includes non-maskable (NMI). High priority
-interrupts cannot interact with the RTOS, that is they must save all regs
-they use and not call any RTOS function.
-
-A further restriction imposed by the Xtensa windowed architecture is that
-high priority interrupts must not modify the stack area even logically
-"above" the top of the interrupted stack (they need to provide their
-own stack or static save area).
-
-Cadence Design Systems recommends high priority interrupt handlers be coded in assembly
-and used for purposes requiring very short service times.
-
-Here are templates for high priority (level 2+) interrupt vectors.
-They assume only one interrupt per level to avoid the burden of identifying
-which interrupts at this level are pending and enabled. This allows for
-minimum latency and avoids having to save/restore a2 in addition to a0.
-If more than one interrupt per high priority level is configured, this burden
-is on the handler which in any case must provide a way to save and restore
-registers it uses without touching the interrupted stack.
-
-Each vector goes at a predetermined location according to the Xtensa
-hardware configuration, which is ensured by its placement in a special
-section known to the Xtensa linker support package (LSP). It performs
-the minimum necessary before jumping to the handler in the .text section.
-
-*******************************************************************************/
-
-/*
-Currently only shells for high priority interrupt handlers are provided
-here. However a template and example can be found in the Cadence Design Systems tools
-documentation: "Microprocessor Programmer's Guide".
-*/
-
-#if XCHAL_NUM_INTLEVELS >=2 && XCHAL_EXCM_LEVEL <2 && XCHAL_DEBUGLEVEL !=2
-
-    .begin      literal_prefix .Level2InterruptVector
-    .section    .Level2InterruptVector.text, "ax"
-    .global     _Level2Vector
-    .type       _Level2Vector,@function
-    .align      4
-_Level2Vector:
-    wsr     a0, EXCSAVE_2                   /* preserve a0 */
-    call0   _xt_highint2                    /* load interrupt handler */
-
-    .end        literal_prefix
-
-    .text
-    .type       _xt_highint2,@function
-    .align      4
-_xt_highint2:
-
-    #ifdef XT_INTEXC_HOOKS
-    /* Call interrupt hook if present to (pre)handle interrupts. */
-    movi    a0, _xt_intexc_hooks
-    l32i    a0, a0, 2<<2
-    beqz    a0, 1f
-.Ln_xt_highint2_call_hook:
-    callx0  a0                              /* must NOT disturb stack! */
-1:
-    #endif
-
-    /* USER_EDIT:
-    ADD HIGH PRIORITY LEVEL 2 INTERRUPT HANDLER CODE HERE.
-    */
-
-    .align  4
-.L_xt_highint2_exit:
-    rsr     a0, EXCSAVE_2                   /* restore a0 */
-    rfi     2
-
-#endif  /* Level 2 */
-
-#if XCHAL_NUM_INTLEVELS >=3 && XCHAL_EXCM_LEVEL <3 && XCHAL_DEBUGLEVEL !=3
-
-    .begin      literal_prefix .Level3InterruptVector
-    .section    .Level3InterruptVector.text, "ax"
-    .global     _Level3Vector
-    .type       _Level3Vector,@function
-    .align      4
-_Level3Vector:
-    wsr     a0, EXCSAVE_3                   /* preserve a0 */
-    call0   _xt_highint3                    /* load interrupt handler */
-    /* never returns here - call0 is used as a jump (see note at top) */
-
-    .end        literal_prefix
-
-    .text
-    .type       _xt_highint3,@function
-    .align      4
-_xt_highint3:
-
-    #ifdef XT_INTEXC_HOOKS
-    /* Call interrupt hook if present to (pre)handle interrupts. */
-    movi    a0, _xt_intexc_hooks
-    l32i    a0, a0, 3<<2
-    beqz    a0, 1f
-.Ln_xt_highint3_call_hook:
-    callx0  a0                              /* must NOT disturb stack! */
-1:
-    #endif
-
-    /* USER_EDIT:
-    ADD HIGH PRIORITY LEVEL 3 INTERRUPT HANDLER CODE HERE.
-    */
-
-    .align  4
-.L_xt_highint3_exit:
-    rsr     a0, EXCSAVE_3                   /* restore a0 */
-    rfi     3
-
-#endif  /* Level 3 */
-
-#if XCHAL_NUM_INTLEVELS >=4 && XCHAL_EXCM_LEVEL <4 && XCHAL_DEBUGLEVEL !=4
-
-    .begin      literal_prefix .Level4InterruptVector
-    .section    .Level4InterruptVector.text, "ax"
-    .global     _Level4Vector
-    .type       _Level4Vector,@function
-    .align      4
-_Level4Vector:
-    wsr     a0, EXCSAVE_4                   /* preserve a0 */
-    call0   _xt_highint4                    /* load interrupt handler */
-    /* never returns here - call0 is used as a jump (see note at top) */
-
-    .end        literal_prefix
-
-    .text
-    .type       _xt_highint4,@function
-    .align      4
-_xt_highint4:
-
-    #ifdef XT_INTEXC_HOOKS
-    /* Call interrupt hook if present to (pre)handle interrupts. */
-    movi    a0, _xt_intexc_hooks
-    l32i    a0, a0, 4<<2
-    beqz    a0, 1f
-.Ln_xt_highint4_call_hook:
-    callx0  a0                              /* must NOT disturb stack! */
-1:
-    #endif
-
-    /* USER_EDIT:
-    ADD HIGH PRIORITY LEVEL 4 INTERRUPT HANDLER CODE HERE.
-    */
-
-    .align  4
-.L_xt_highint4_exit:
-    rsr     a0, EXCSAVE_4                   /* restore a0 */
-    rfi     4
-
-#endif  /* Level 4 */
-
-#if XCHAL_NUM_INTLEVELS >=5 && XCHAL_EXCM_LEVEL <5 && XCHAL_DEBUGLEVEL !=5
-
-    .begin      literal_prefix .Level5InterruptVector
-    .section    .Level5InterruptVector.text, "ax"
-    .global     _Level5Vector
-    .type       _Level5Vector,@function
-    .align      4
-_Level5Vector:
-    wsr     a0, EXCSAVE_5                   /* preserve a0 */
-    call0   _xt_highint5                    /* load interrupt handler */
-    /* never returns here - call0 is used as a jump (see note at top) */
-
-    .end        literal_prefix
-
-    .text
-    .type       _xt_highint5,@function
-    .align      4
-_xt_highint5:
-
-    #ifdef XT_INTEXC_HOOKS
-    /* Call interrupt hook if present to (pre)handle interrupts. */
-    movi    a0, _xt_intexc_hooks
-    l32i    a0, a0, 5<<2
-    beqz    a0, 1f
-.Ln_xt_highint5_call_hook:
-    callx0  a0                              /* must NOT disturb stack! */
-1:
-    #endif
-
-    /* USER_EDIT:
-    ADD HIGH PRIORITY LEVEL 5 INTERRUPT HANDLER CODE HERE.
-    */
-
-    .align  4
-.L_xt_highint5_exit:
-    rsr     a0, EXCSAVE_5                   /* restore a0 */
-    rfi     5
-
-#endif  /* Level 5 */
-
-#if XCHAL_NUM_INTLEVELS >=6 && XCHAL_EXCM_LEVEL <6 && XCHAL_DEBUGLEVEL !=6
-
-    .begin      literal_prefix .Level6InterruptVector
-    .section    .Level6InterruptVector.text, "ax"
-    .global     _Level6Vector
-    .type       _Level6Vector,@function
-    .align      4
-_Level6Vector:
-    wsr     a0, EXCSAVE_6                   /* preserve a0 */
-    call0   _xt_highint6                    /* load interrupt handler */
-    /* never returns here - call0 is used as a jump (see note at top) */
-
-    .end        literal_prefix
-
-    .text
-    .type       _xt_highint6,@function
-    .align      4
-_xt_highint6:
-
-    #ifdef XT_INTEXC_HOOKS
-    /* Call interrupt hook if present to (pre)handle interrupts. */
-    movi    a0, _xt_intexc_hooks
-    l32i    a0, a0, 6<<2
-    beqz    a0, 1f
-.Ln_xt_highint6_call_hook:
-    callx0  a0                              /* must NOT disturb stack! */
-1:
-    #endif
-
-    /* USER_EDIT:
-    ADD HIGH PRIORITY LEVEL 6 INTERRUPT HANDLER CODE HERE.
-    */
-
-    .align  4
-.L_xt_highint6_exit:
-    rsr     a0, EXCSAVE_6                   /* restore a0 */
-    rfi     6
-
-#endif  /* Level 6 */
-
-#if XCHAL_HAVE_NMI
-
-    .begin      literal_prefix .NMIExceptionVector
-    .section    .NMIExceptionVector.text, "ax"
-    .global     _NMIExceptionVector
-    .type       _NMIExceptionVector,@function
-    .align      4
-_NMIExceptionVector:
-    wsr     a0, EXCSAVE + XCHAL_NMILEVEL  _ /* preserve a0 */
-    call0   _xt_nmi                         /* load interrupt handler */
-    /* never returns here - call0 is used as a jump (see note at top) */
-
-    .end        literal_prefix
-
-    .text
-    .type       _xt_nmi,@function
-    .align      4
-_xt_nmi:
-
-    #ifdef XT_INTEXC_HOOKS
-    /* Call interrupt hook if present to (pre)handle interrupts. */
-    movi    a0, _xt_intexc_hooks
-    l32i    a0, a0, XCHAL_NMILEVEL<<2
-    beqz    a0, 1f
-.Ln_xt_nmi_call_hook:
-    callx0  a0                              /* must NOT disturb stack! */
-1:
-    #endif
-
-    /* USER_EDIT:
-    ADD HIGH PRIORITY NON-MASKABLE INTERRUPT (NMI) HANDLER CODE HERE.
-    */
-
-    .align  4
-.L_xt_nmi_exit:
-    rsr     a0, EXCSAVE + XCHAL_NMILEVEL    /* restore a0 */
-    rfi     XCHAL_NMILEVEL
-
-#endif  /* NMI */
-
-
-/*******************************************************************************
-
-WINDOW OVERFLOW AND UNDERFLOW EXCEPTION VECTORS AND ALLOCA EXCEPTION HANDLER
-
-Here is the code for each window overflow/underflow exception vector and
-(interspersed) efficient code for handling the alloca exception cause.
-Window exceptions are handled entirely in the vector area and are very
-tight for performance. The alloca exception is also handled entirely in
-the window vector area so comes at essentially no cost in code size.
-Users should never need to modify them and Cadence Design Systems recommends
-they do not.
-
-Window handlers go at predetermined vector locations according to the
-Xtensa hardware configuration, which is ensured by their placement in a
-special section known to the Xtensa linker support package (LSP). Since
-their offsets in that section are always the same, the LSPs do not define
-a section per vector.
-
-These things are coded for XEA2 only (XEA1 is not supported).
-
-Note on Underflow Handlers:
-The underflow handler for returning from call[i+1] to call[i]
-must preserve all the registers from call[i+1]'s window.
-In particular, a0 and a1 must be preserved because the RETW instruction
-will be reexecuted (and may even underflow if an intervening exception
-has flushed call[i]'s registers).
-Registers a2 and up may contain return values.
-
-*******************************************************************************/
-
-#if XCHAL_HAVE_WINDOWED
-
-    .section .WindowVectors.text, "ax"
-
-/*
---------------------------------------------------------------------------------
-Window Overflow Exception for Call4.
-
-Invoked if a call[i] referenced a register (a4-a15)
-that contains data from ancestor call[j];
-call[j] had done a call4 to call[j+1].
-On entry here:
-    window rotated to call[j] start point;
-        a0-a3 are registers to be saved;
-        a4-a15 must be preserved;
-        a5 is call[j+1]'s stack pointer.
---------------------------------------------------------------------------------
-*/
-
-    .org    0x0
-    .global _WindowOverflow4
-_WindowOverflow4:
-
-    s32e    a0, a5, -16     /* save a0 to call[j+1]'s stack frame */
-    s32e    a1, a5, -12     /* save a1 to call[j+1]'s stack frame */
-    s32e    a2, a5,  -8     /* save a2 to call[j+1]'s stack frame */
-    s32e    a3, a5,  -4     /* save a3 to call[j+1]'s stack frame */
-    rfwo                    /* rotates back to call[i] position */
-
-/*
---------------------------------------------------------------------------------
-Window Underflow Exception for Call4
-
-Invoked by RETW returning from call[i+1] to call[i]
-where call[i]'s registers must be reloaded (not live in ARs);
-where call[i] had done a call4 to call[i+1].
-On entry here:
-        window rotated to call[i] start point;
-        a0-a3 are undefined, must be reloaded with call[i].reg[0..3];
-        a4-a15 must be preserved (they are call[i+1].reg[0..11]);
-        a5 is call[i+1]'s stack pointer.
---------------------------------------------------------------------------------
-*/
-
-    .org    0x40
-    .global _WindowUnderflow4
-_WindowUnderflow4:
-
-    l32e    a0, a5, -16     /* restore a0 from call[i+1]'s stack frame */
-    l32e    a1, a5, -12     /* restore a1 from call[i+1]'s stack frame */
-    l32e    a2, a5,  -8     /* restore a2 from call[i+1]'s stack frame */
-    l32e    a3, a5,  -4     /* restore a3 from call[i+1]'s stack frame */
-    rfwu
-
-/*
---------------------------------------------------------------------------------
-Handle alloca exception generated by interruptee executing 'movsp'.
-This uses space between the window vectors, so is essentially "free".
-All interruptee's regs are intact except a0 which is saved in EXCSAVE_1,
-and PS.EXCM has been set by the exception hardware (can't be interrupted).
-The fact the alloca exception was taken means the registers associated with
-the base-save area have been spilled and will be restored by the underflow
-handler, so those 4 registers are available for scratch.
-The code is optimized to avoid unaligned branches and minimize cache misses.
---------------------------------------------------------------------------------
-*/
-
-    .align  4
-    .global _xt_alloca_exc
-_xt_alloca_exc:
-
-    rsr     a0, WINDOWBASE  /* grab WINDOWBASE before rotw changes it */
-    rotw    -1              /* WINDOWBASE goes to a4, new a0-a3 are scratch */
-    rsr     a2, PS
-    extui   a3, a2, XCHAL_PS_OWB_SHIFT, XCHAL_PS_OWB_BITS
-    xor     a3, a3, a4      /* bits changed from old to current windowbase */
-    rsr     a4, EXCSAVE_1   /* restore original a0 (now in a4) */
-    slli    a3, a3, XCHAL_PS_OWB_SHIFT
-    xor     a2, a2, a3      /* flip changed bits in old window base */
-    wsr     a2, PS          /* update PS.OWB to new window base */
-    rsync
-
-    _bbci.l a4, 31, _WindowUnderflow4
-    rotw    -1              /* original a0 goes to a8 */
-    _bbci.l a8, 30, _WindowUnderflow8
-    rotw    -1
-    j               _WindowUnderflow12
-
-/*
---------------------------------------------------------------------------------
-Window Overflow Exception for Call8
-
-Invoked if a call[i] referenced a register (a4-a15)
-that contains data from ancestor call[j];
-call[j] had done a call8 to call[j+1].
-On entry here:
-    window rotated to call[j] start point;
-        a0-a7 are registers to be saved;
-        a8-a15 must be preserved;
-        a9 is call[j+1]'s stack pointer.
---------------------------------------------------------------------------------
-*/
-
-    .org    0x80
-    .global _WindowOverflow8
-_WindowOverflow8:
-
-    s32e    a0, a9, -16     /* save a0 to call[j+1]'s stack frame */
-    l32e    a0, a1, -12     /* a0 <- call[j-1]'s sp
-                               (used to find end of call[j]'s frame) */
-    s32e    a1, a9, -12     /* save a1 to call[j+1]'s stack frame */
-    s32e    a2, a9,  -8     /* save a2 to call[j+1]'s stack frame */
-    s32e    a3, a9,  -4     /* save a3 to call[j+1]'s stack frame */
-    s32e    a4, a0, -32     /* save a4 to call[j]'s stack frame */
-    s32e    a5, a0, -28     /* save a5 to call[j]'s stack frame */
-    s32e    a6, a0, -24     /* save a6 to call[j]'s stack frame */
-    s32e    a7, a0, -20     /* save a7 to call[j]'s stack frame */
-    rfwo                    /* rotates back to call[i] position */
-
-/*
---------------------------------------------------------------------------------
-Window Underflow Exception for Call8
-
-Invoked by RETW returning from call[i+1] to call[i]
-where call[i]'s registers must be reloaded (not live in ARs);
-where call[i] had done a call8 to call[i+1].
-On entry here:
-        window rotated to call[i] start point;
-        a0-a7 are undefined, must be reloaded with call[i].reg[0..7];
-        a8-a15 must be preserved (they are call[i+1].reg[0..7]);
-        a9 is call[i+1]'s stack pointer.
---------------------------------------------------------------------------------
-*/
-
-    .org    0xC0
-    .global _WindowUnderflow8
-_WindowUnderflow8:
-
-    l32e    a0, a9, -16     /* restore a0 from call[i+1]'s stack frame */
-    l32e    a1, a9, -12     /* restore a1 from call[i+1]'s stack frame */
-    l32e    a2, a9,  -8     /* restore a2 from call[i+1]'s stack frame */
-    l32e    a7, a1, -12     /* a7 <- call[i-1]'s sp
-                               (used to find end of call[i]'s frame) */
-    l32e    a3, a9,  -4     /* restore a3 from call[i+1]'s stack frame */
-    l32e    a4, a7, -32     /* restore a4 from call[i]'s stack frame */
-    l32e    a5, a7, -28     /* restore a5 from call[i]'s stack frame */
-    l32e    a6, a7, -24     /* restore a6 from call[i]'s stack frame */
-    l32e    a7, a7, -20     /* restore a7 from call[i]'s stack frame */
-    rfwu
-
-/*
---------------------------------------------------------------------------------
-Window Overflow Exception for Call12
-
-Invoked if a call[i] referenced a register (a4-a15)
-that contains data from ancestor call[j];
-call[j] had done a call12 to call[j+1].
-On entry here:
-    window rotated to call[j] start point;
-        a0-a11 are registers to be saved;
-        a12-a15 must be preserved;
-        a13 is call[j+1]'s stack pointer.
---------------------------------------------------------------------------------
-*/
-
-    .org    0x100
-    .global _WindowOverflow12
-_WindowOverflow12:
-
-    s32e    a0,  a13, -16   /* save a0 to call[j+1]'s stack frame */
-    l32e    a0,  a1,  -12   /* a0 <- call[j-1]'s sp
-                               (used to find end of call[j]'s frame) */
-    s32e    a1,  a13, -12   /* save a1 to call[j+1]'s stack frame */
-    s32e    a2,  a13,  -8   /* save a2 to call[j+1]'s stack frame */
-    s32e    a3,  a13,  -4   /* save a3 to call[j+1]'s stack frame */
-    s32e    a4,  a0,  -48   /* save a4 to end of call[j]'s stack frame */
-    s32e    a5,  a0,  -44   /* save a5 to end of call[j]'s stack frame */
-    s32e    a6,  a0,  -40   /* save a6 to end of call[j]'s stack frame */
-    s32e    a7,  a0,  -36   /* save a7 to end of call[j]'s stack frame */
-    s32e    a8,  a0,  -32   /* save a8 to end of call[j]'s stack frame */
-    s32e    a9,  a0,  -28   /* save a9 to end of call[j]'s stack frame */
-    s32e    a10, a0,  -24   /* save a10 to end of call[j]'s stack frame */
-    s32e    a11, a0,  -20   /* save a11 to end of call[j]'s stack frame */
-    rfwo                    /* rotates back to call[i] position */
-
-/*
---------------------------------------------------------------------------------
-Window Underflow Exception for Call12
-
-Invoked by RETW returning from call[i+1] to call[i]
-where call[i]'s registers must be reloaded (not live in ARs);
-where call[i] had done a call12 to call[i+1].
-On entry here:
-        window rotated to call[i] start point;
-        a0-a11 are undefined, must be reloaded with call[i].reg[0..11];
-        a12-a15 must be preserved (they are call[i+1].reg[0..3]);
-        a13 is call[i+1]'s stack pointer.
---------------------------------------------------------------------------------
-*/
-
-    .org 0x140
-    .global _WindowUnderflow12
-_WindowUnderflow12:
-
-    l32e    a0,  a13, -16   /* restore a0 from call[i+1]'s stack frame */
-    l32e    a1,  a13, -12   /* restore a1 from call[i+1]'s stack frame */
-    l32e    a2,  a13,  -8   /* restore a2 from call[i+1]'s stack frame */
-    l32e    a11, a1,  -12   /* a11 <- call[i-1]'s sp
-                               (used to find end of call[i]'s frame) */
-    l32e    a3,  a13,  -4   /* restore a3 from call[i+1]'s stack frame */
-    l32e    a4,  a11, -48   /* restore a4 from end of call[i]'s stack frame */
-    l32e    a5,  a11, -44   /* restore a5 from end of call[i]'s stack frame */
-    l32e    a6,  a11, -40   /* restore a6 from end of call[i]'s stack frame */
-    l32e    a7,  a11, -36   /* restore a7 from end of call[i]'s stack frame */
-    l32e    a8,  a11, -32   /* restore a8 from end of call[i]'s stack frame */
-    l32e    a9,  a11, -28   /* restore a9 from end of call[i]'s stack frame */
-    l32e    a10, a11, -24   /* restore a10 from end of call[i]'s stack frame */
-    l32e    a11, a11, -20   /* restore a11 from end of call[i]'s stack frame */
-    rfwu
-
-#endif /* XCHAL_HAVE_WINDOWED */

From a49c35b5dc0f1f521eef3ef993d401af7f26f439 Mon Sep 17 00:00:00 2001
From: kakkoko <parenthesized.ko@gmail.com>
Date: Wed, 16 Oct 2024 18:36:20 +0900
Subject: [PATCH 334/424] Fix incorrect error checking of prvCreateIdleTasks
 (#1158)

In environments that do not support static allocation
(configSUPPORT_STATIC_ALLOCATION == 0), at prvCreateIdleTasks(), call
xCreateTask() and compare its return value to pdFAIL to check whether
xCreateTask() failed. However, xCreateTask() returns
errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY as the error value, so the
result of this comparison is always false.

This commit fixes this problem by changing the return value comparison
to pdPASS instead of pdFAIL.
---
 tasks.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tasks.c b/tasks.c
index 1be3fca91..6d86326c5 100644
--- a/tasks.c
+++ b/tasks.c
@@ -3630,7 +3630,7 @@ static BaseType_t prvCreateIdleTasks( void )
         #endif /* configSUPPORT_STATIC_ALLOCATION */
 
         /* Break the loop if any of the idle task is failed to be created. */
-        if( xReturn == pdFAIL )
+        if( xReturn != pdPASS )
         {
             break;
         }

From e400cc93b753d0afe91a935bcffc7b0257c2ad8c Mon Sep 17 00:00:00 2001
From: Tony Josi <tonyjosi@amazon.com>
Date: Tue, 22 Oct 2024 18:16:46 +0530
Subject: [PATCH 335/424] Update .github/CODEOWNERS (#1162)

---
 .github/CODEOWNERS | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.github/CODEOWNERS b/.github/CODEOWNERS
index 48fe891ac..771aee37d 100644
--- a/.github/CODEOWNERS
+++ b/.github/CODEOWNERS
@@ -4,7 +4,7 @@
 # the repo. Unless a later match takes precedence,
 # @global-owner1 and @global-owner2 will be requested for
 # review when someone opens a pull request.
-*      @FreeRTOS/pr-bar-raiser
+*      @FreeRTOS/pr-bar-raisers
 
 # Order is important; the last matching pattern takes the most
 # precedence. When someone opens a pull request that only

From 7081e76f5a781f3b143d2e2f478292c52e14d6dc Mon Sep 17 00:00:00 2001
From: Ahmed Ismail <64546783+AhmedIsmail02@users.noreply.github.com>
Date: Thu, 24 Oct 2024 07:25:16 +0100
Subject: [PATCH 336/424] Armv8.1-m: Add pacbti support (#1147)

* copyright-checker: Add FreeRTOS Arm collab copyright

FreeRTOS Arm collab files shall have both Amazon's
and Arm's copyright headers. Hence, the copyright
checker is modified to check for both copyrights.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* armv8-m: Add support for IAR with TFM FREERTOS PORT

As the case for ARMClang, and GCC toolchains, IAR
with TFM FreeRTOS Port support is added.

Signed-off-by: Ahmed Ismail <Ahmed.Ismail@arm.com>

* armv8-m: Do not overwrite Control register value

The current ARMv8-M FreeRTOS-Kernel Port code
implementation is modified in a way that allows
the CONTROL register's value to be retained
rather than being overwritten.

This is needed for adding PACBTI support as
the special-purpose CONTROL register `PAC_EN`,
`UPAC_EN`, `BTI_EN`, and `UBTI_EN` PACBTI
enablement bits should be configured before calling
`vRestoreContextOfFirstTask()` function which currently
overwrite the value inside the CONTROL register.

Signed-off-by: Ahmed Ismail <Ahmed.Ismail@arm.com>

* armv8.1-m: Add PACBTI support to kernel non-secure implementation

In this commit, Pointer Authentication, and Branch Target
Identification Extension (PACBTI) support is added for
Non-Secure and Non-TrustZone variants of Cortex-M85
FreeRTOS-Kernel Port.

The PACBTI support is added for Arm Compiler For
Embedded, and IAR toolchains only. The support in
the kernel is not yet enabled for GNU toolchain
due to known issues.

Signed-off-by: Ahmed Ismail <Ahmed.Ismail@arm.com>

* Fix CI check

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Signed-off-by: Ahmed Ismail <Ahmed.Ismail@arm.com>
Co-authored-by: Ahmed Ismail <ahmism01@e133373.arm.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 .github/.cSpellWords.txt                      |   5 +
 .github/scripts/kernel_checker.py             |  99 ++++++++++++--
 CMakeLists.txt                                |   3 +
 examples/coverity/README.md                   |   2 +-
 include/FreeRTOS.h                            |  12 ++
 portable/ARMv8M/non_secure/port.c             |  97 +++++++++++++-
 .../portable/GCC/ARM_CM23/portmacro.h         |   3 +
 .../portable/GCC/ARM_CM23_NTZ/portmacro.h     |   3 +
 .../portable/GCC/ARM_CM33/portasm.c           |   7 +-
 .../portable/GCC/ARM_CM33/portmacro.h         |   3 +
 .../portable/GCC/ARM_CM33_NTZ/portasm.c       |   7 +-
 .../portable/GCC/ARM_CM33_NTZ/portmacro.h     |   3 +
 .../portable/GCC/ARM_CM35P/portmacro.h        |   3 +
 .../portable/GCC/ARM_CM55/portmacro.h         |   3 +
 .../portable/GCC/ARM_CM85/portmacro.h         |   3 +
 .../portable/IAR/ARM_CM23/portmacro.h         |   3 +
 .../portable/IAR/ARM_CM23_NTZ/portmacro.h     |   3 +
 .../portable/IAR/ARM_CM33/portasm.s           |   7 +-
 .../portable/IAR/ARM_CM33/portmacro.h         |   3 +
 .../portable/IAR/ARM_CM33_NTZ/portasm.s       |   7 +-
 .../portable/IAR/ARM_CM33_NTZ/portmacro.h     |   3 +
 .../portable/IAR/ARM_CM35P/portmacro.h        |   3 +
 .../portable/IAR/ARM_CM55/portmacro.h         |   3 +
 .../portable/IAR/ARM_CM85/portmacro.h         |   3 +
 portable/CMakeLists.txt                       | 122 +++++++++++++++++-
 portable/GCC/ARM_CM23/non_secure/port.c       |  97 +++++++++++++-
 portable/GCC/ARM_CM23/non_secure/portmacro.h  |   3 +
 portable/GCC/ARM_CM23_NTZ/non_secure/port.c   |  97 +++++++++++++-
 .../GCC/ARM_CM23_NTZ/non_secure/portmacro.h   |   3 +
 portable/GCC/ARM_CM33/non_secure/port.c       |  97 +++++++++++++-
 portable/GCC/ARM_CM33/non_secure/portasm.c    |   7 +-
 portable/GCC/ARM_CM33/non_secure/portmacro.h  |   3 +
 portable/GCC/ARM_CM33_NTZ/non_secure/port.c   |  97 +++++++++++++-
 .../GCC/ARM_CM33_NTZ/non_secure/portasm.c     |   7 +-
 .../GCC/ARM_CM33_NTZ/non_secure/portmacro.h   |   3 +
 portable/GCC/ARM_CM35P/non_secure/port.c      |  97 +++++++++++++-
 portable/GCC/ARM_CM35P/non_secure/portasm.c   |   7 +-
 portable/GCC/ARM_CM35P/non_secure/portmacro.h |   3 +
 portable/GCC/ARM_CM35P_NTZ/non_secure/port.c  |  97 +++++++++++++-
 .../GCC/ARM_CM35P_NTZ/non_secure/portasm.c    |   7 +-
 .../GCC/ARM_CM35P_NTZ/non_secure/portmacro.h  |   3 +
 portable/GCC/ARM_CM55/non_secure/port.c       |  97 +++++++++++++-
 portable/GCC/ARM_CM55/non_secure/portasm.c    |   7 +-
 portable/GCC/ARM_CM55/non_secure/portmacro.h  |   3 +
 portable/GCC/ARM_CM55_NTZ/non_secure/port.c   |  97 +++++++++++++-
 .../GCC/ARM_CM55_NTZ/non_secure/portasm.c     |   7 +-
 .../GCC/ARM_CM55_NTZ/non_secure/portmacro.h   |   3 +
 portable/GCC/ARM_CM85/non_secure/port.c       |  97 +++++++++++++-
 portable/GCC/ARM_CM85/non_secure/portasm.c    |   7 +-
 portable/GCC/ARM_CM85/non_secure/portmacro.h  |   3 +
 portable/GCC/ARM_CM85_NTZ/non_secure/port.c   |  97 +++++++++++++-
 .../GCC/ARM_CM85_NTZ/non_secure/portasm.c     |   7 +-
 .../GCC/ARM_CM85_NTZ/non_secure/portmacro.h   |   3 +
 portable/IAR/ARM_CM23/non_secure/port.c       |  97 +++++++++++++-
 portable/IAR/ARM_CM23/non_secure/portmacro.h  |   3 +
 portable/IAR/ARM_CM23_NTZ/non_secure/port.c   |  97 +++++++++++++-
 .../IAR/ARM_CM23_NTZ/non_secure/portmacro.h   |   3 +
 portable/IAR/ARM_CM33/non_secure/port.c       |  97 +++++++++++++-
 portable/IAR/ARM_CM33/non_secure/portasm.s    |   7 +-
 portable/IAR/ARM_CM33/non_secure/portmacro.h  |   3 +
 portable/IAR/ARM_CM33_NTZ/non_secure/port.c   |  97 +++++++++++++-
 .../IAR/ARM_CM33_NTZ/non_secure/portasm.s     |   7 +-
 .../IAR/ARM_CM33_NTZ/non_secure/portmacro.h   |   3 +
 portable/IAR/ARM_CM35P/non_secure/port.c      |  97 +++++++++++++-
 portable/IAR/ARM_CM35P/non_secure/portasm.s   |   7 +-
 portable/IAR/ARM_CM35P/non_secure/portmacro.h |   3 +
 portable/IAR/ARM_CM35P_NTZ/non_secure/port.c  |  97 +++++++++++++-
 .../IAR/ARM_CM35P_NTZ/non_secure/portasm.s    |   7 +-
 .../IAR/ARM_CM35P_NTZ/non_secure/portmacro.h  |   3 +
 portable/IAR/ARM_CM55/non_secure/port.c       |  97 +++++++++++++-
 portable/IAR/ARM_CM55/non_secure/portasm.s    |   7 +-
 portable/IAR/ARM_CM55/non_secure/portmacro.h  |   3 +
 portable/IAR/ARM_CM55_NTZ/non_secure/port.c   |  97 +++++++++++++-
 .../IAR/ARM_CM55_NTZ/non_secure/portasm.s     |   7 +-
 .../IAR/ARM_CM55_NTZ/non_secure/portmacro.h   |   3 +
 portable/IAR/ARM_CM85/non_secure/port.c       |  97 +++++++++++++-
 portable/IAR/ARM_CM85/non_secure/portasm.s    |   7 +-
 portable/IAR/ARM_CM85/non_secure/portmacro.h  |   3 +
 portable/IAR/ARM_CM85_NTZ/non_secure/port.c   |  97 +++++++++++++-
 .../IAR/ARM_CM85_NTZ/non_secure/portasm.s     |   7 +-
 .../IAR/ARM_CM85_NTZ/non_secure/portmacro.h   |   3 +
 81 files changed, 2430 insertions(+), 92 deletions(-)

diff --git a/.github/.cSpellWords.txt b/.github/.cSpellWords.txt
index 42f9196d7..d100fcd49 100644
--- a/.github/.cSpellWords.txt
+++ b/.github/.cSpellWords.txt
@@ -448,6 +448,7 @@ MAINRDY
 MAIR
 Mang
 Mbits
+mbranch
 mcause
 MCFR
 MCKA
@@ -586,6 +587,8 @@ OWATCOM
 OWDR
 OWER
 OWSR
+pacbti
+PACBTI
 PAGEN
 PCDR
 PCER
@@ -900,6 +903,7 @@ TXTEN
 TXUBR
 TXVC
 TXVDIS
+UBTI
 UDCP
 UNACKED
 uncrustify
@@ -915,6 +919,7 @@ UNSUB
 UNSUBACK
 unsubscriptions
 unsuspended
+UPAC
 URAD
 URAT
 URSTEN
diff --git a/.github/scripts/kernel_checker.py b/.github/scripts/kernel_checker.py
index b57b7f527..228257042 100755
--- a/.github/scripts/kernel_checker.py
+++ b/.github/scripts/kernel_checker.py
@@ -28,6 +28,7 @@
 # */
 
 import os
+import re
 from common.header_checker import HeaderChecker
 
 #--------------------------------------------------------------------------------------------------
@@ -106,6 +107,15 @@ KERNEL_THIRD_PARTY_PATTERNS = [
     r'.*portable/GCC/AVR32_UC3/.*',
 ]
 
+KERNEL_ARM_COLLAB_FILES_PATTERNS = [
+    r'.*portable/ARMv8M/*',
+    r'.*portable/.*/ARM_CM23*',
+    r'.*portable/.*/ARM_CM33*',
+    r'.*portable/.*/ARM_CM35*',
+    r'.*portable/.*/ARM_CM55*',
+    r'.*portable/.*/ARM_CM85*',
+]
+
 KERNEL_HEADER = [
     '/*\n',
     ' * FreeRTOS Kernel <DEVELOPMENT BRANCH>\n',
@@ -139,19 +149,92 @@ KERNEL_HEADER = [
 
 FREERTOS_COPYRIGHT_REGEX = r"^(;|#)?( *(\/\*|\*|#|\/\/))? Copyright \(C\) 20\d\d Amazon.com, Inc. or its affiliates. All Rights Reserved\.( \*\/)?$"
 
+FREERTOS_ARM_COLLAB_COPYRIGHT_REGEX = r"(^(;|#)?( *(\/\*|\*|#|\/\/))? Copyright \(C\) 20\d\d Amazon.com, Inc. or its affiliates. All Rights Reserved\.( \*\/)?$)|" + \
+                                      r"(^(;|#)?( *(\/\*|\*|#|\/\/))? Copyright 20\d\d Arm Limited and/or its affiliates( \*\/)?$)|" + \
+                                      r"(^(;|#)?( *(\/\*|\*|#|\/\/))? <open-source-office@arm.com>( \*\/)?$)"
+
+
+class KernelHeaderChecker(HeaderChecker):
+    def __init__(
+        self,
+        header,
+        padding=1000,
+        ignored_files=None,
+        ignored_ext=None,
+        ignored_patterns=None,
+        py_ext=None,
+        asm_ext=None,
+        third_party_patterns=None,
+        copyright_regex = None
+    ):
+        super().__init__(header, padding, ignored_files, ignored_ext, ignored_patterns,
+                         py_ext, asm_ext, third_party_patterns, copyright_regex)
+
+        self.armCollabRegex = re.compile(FREERTOS_ARM_COLLAB_COPYRIGHT_REGEX)
+
+        self.armCollabFilesPatternList = []
+        for pattern in KERNEL_ARM_COLLAB_FILES_PATTERNS:
+            self.armCollabFilesPatternList.append(re.compile(pattern))
+
+    def isArmCollabFile(self, path):
+        for pattern in self.armCollabFilesPatternList:
+            if pattern.match(path):
+                return True
+        return False
+
+    def checkArmCollabFile(self, path):
+        isValid = False
+        file_ext = os.path.splitext(path)[-1]
+
+        with open(path, encoding="utf-8", errors="ignore") as file:
+            chunk = file.read(len("".join(self.header)) + self.padding)
+            lines = [("%s\n" % line) for line in chunk.strip().splitlines()][
+                : len(self.header) + 2
+            ]
+            if (len(lines) > 0) and (lines[0].find("#!") == 0):
+                lines.remove(lines[0])
+
+        # Split lines in sections.
+        headers = dict()
+        headers["text"] = []
+        headers["copyright"] = []
+        headers["spdx"] = []
+        for line in lines:
+            if self.armCollabRegex.match(line):
+                headers["copyright"].append(line)
+            elif "SPDX-License-Identifier:" in line:
+                headers["spdx"].append(line)
+            else:
+                headers["text"].append(line)
+
+        text_equal = self.isValidHeaderSection(file_ext, "text", headers["text"])
+        spdx_equal = self.isValidHeaderSection(file_ext, "spdx", headers["spdx"])
+
+        if text_equal and spdx_equal and len(headers["copyright"]) == 3:
+            isValid = True
+
+        return isValid
+
+    def customCheck(self, path):
+        isValid = False
+        if self.isArmCollabFile(path):
+            isValid = self.checkArmCollabFile(path)
+        return isValid
+
+
 def main():
     parser = HeaderChecker.configArgParser()
     args   = parser.parse_args()
 
     # Configure the checks then run
-    checker = HeaderChecker(KERNEL_HEADER,
-                            copyright_regex=FREERTOS_COPYRIGHT_REGEX,
-                            ignored_files=KERNEL_IGNORED_FILES,
-                            ignored_ext=KERNEL_IGNORED_EXTENSIONS,
-                            ignored_patterns=KERNEL_IGNORED_PATTERNS,
-                            third_party_patterns=KERNEL_THIRD_PARTY_PATTERNS,
-                            py_ext=KERNEL_PY_EXTENSIONS,
-                            asm_ext=KERNEL_ASM_EXTENSIONS)
+    checker = KernelHeaderChecker(KERNEL_HEADER,
+                                  copyright_regex=FREERTOS_COPYRIGHT_REGEX,
+                                  ignored_files=KERNEL_IGNORED_FILES,
+                                  ignored_ext=KERNEL_IGNORED_EXTENSIONS,
+                                  ignored_patterns=KERNEL_IGNORED_PATTERNS,
+                                  third_party_patterns=KERNEL_THIRD_PARTY_PATTERNS,
+                                  py_ext=KERNEL_PY_EXTENSIONS,
+                                  asm_ext=KERNEL_ASM_EXTENSIONS)
     checker.ignoreFile(os.path.split(__file__)[-1])
 
     rc = checker.processArgs(args)
diff --git a/CMakeLists.txt b/CMakeLists.txt
index 6fd1ff56b..f0a87bfe3 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -138,15 +138,18 @@ if(NOT FREERTOS_PORT)
         " IAR_ARM_CM33_NONSECURE           - Compiler: IAR           Target: ARM Cortex-M33 non-secure\n"
         " IAR_ARM_CM33_SECURE              - Compiler: IAR           Target: ARM Cortex-M33 secure\n"
         " IAR_ARM_CM33_NTZ_NONSECURE       - Compiler: IAR           Target: ARM Cortex-M33 non-trustzone non-secure\n"
+        " IAR_ARM_CM33_TFM                 - Compiler: IAR           Target: ARM Cortex-M33 non-secure for TF-M\n"
         " IAR_ARM_CM35P_NONSECURE          - Compiler: IAR           Target: ARM Cortex-M35P non-secure\n"
         " IAR_ARM_CM35P_SECURE             - Compiler: IAR           Target: ARM Cortex-M35P secure\n"
         " IAR_ARM_CM35P_NTZ_NONSECURE      - Compiler: IAR           Target: ARM Cortex-M35P non-trustzone non-secure\n"
         " IAR_ARM_CM55_NONSECURE           - Compiler: IAR           Target: ARM Cortex-M55 non-secure\n"
         " IAR_ARM_CM55_SECURE              - Compiler: IAR           Target: ARM Cortex-M55 secure\n"
         " IAR_ARM_CM55_NTZ_NONSECURE       - Compiler: IAR           Target: ARM Cortex-M55 non-trustzone non-secure\n"
+        " IAR_ARM_CM55_TFM                 - Compiler: IAR           Target: ARM Cortex-M55 non-secure for TF-M\n"
         " IAR_ARM_CM85_NONSECURE           - Compiler: IAR           Target: ARM Cortex-M85 non-secure\n"
         " IAR_ARM_CM85_SECURE              - Compiler: IAR           Target: ARM Cortex-M85 secure\n"
         " IAR_ARM_CM85_NTZ_NONSECURE       - Compiler: IAR           Target: ARM Cortex-M85 non-trustzone non-secure\n"
+        " IAR_ARM_CM85_TFM                 - Compiler: IAR           Target: ARM Cortex-M85 non-secure for TF-M\n"
         " IAR_ARM_CRX_NOGIC                - Compiler: IAR           Target: ARM Cortex-Rx no GIC\n"
         " IAR_ATMEGA323                    - Compiler: IAR           Target: ATMega323\n"
         " IAR_ATMEL_SAM7S64                - Compiler: IAR           Target: Atmel SAM7S64\n"
diff --git a/examples/coverity/README.md b/examples/coverity/README.md
index 367c1d6e8..688577d37 100644
--- a/examples/coverity/README.md
+++ b/examples/coverity/README.md
@@ -17,7 +17,7 @@ files.
 
 ## Getting Started
 ### Prerequisites
-Coverity can be run on any platform mentioned [here](https://sig-docs.synopsys.com/polaris/topics/c_coverity-compatible-platforms.html).
+Coverity can be run on any platform mentioned [here](https://documentation.blackduck.com/bundle/coverity-docs/page/deploy-install-guide/topics/supported_platforms_for_coverity_analysis.html).
 The following are the prerequisites to generate coverity report:
 
 1. CMake version > 3.13.0 (You can check whether you have this by typing `cmake --version`).
diff --git a/include/FreeRTOS.h b/include/FreeRTOS.h
index 4b59512c9..821b55d5d 100644
--- a/include/FreeRTOS.h
+++ b/include/FreeRTOS.h
@@ -3032,6 +3032,18 @@
     #define configCONTROL_INFINITE_LOOP()
 #endif
 
+/* Set configENABLE_PAC and/or configENABLE_BTI to 1 to enable PAC and/or BTI
+ * support and 0 to disable them. These are currently used in ARMv8.1-M ports. */
+#if ( portHAS_PACBTI_FEATURE == 1 )
+    #ifndef configENABLE_PAC
+        #define configENABLE_PAC    0
+    #endif
+
+    #ifndef configENABLE_BTI
+        #define configENABLE_BTI    0
+    #endif
+#endif
+
 /* Sometimes the FreeRTOSConfig.h settings only allow a task to be created using
  * dynamically allocated RAM, in which case when any task is deleted it is known
  * that both the task's stack and TCB need to be freed.  Sometimes the
diff --git a/portable/ARMv8M/non_secure/port.c b/portable/ARMv8M/non_secure/port.c
index 75e9ea9dd..5b399358e 100644
--- a/portable/ARMv8M/non_secure/port.c
+++ b/portable/ARMv8M/non_secure/port.c
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
 #define portSCB_VTOR_REG                      ( *( ( portISR_t ** ) 0xe000ed08 ) )
 #define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
 #define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )
+#define portSCB_USG_FAULT_ENABLE_BIT          ( 1UL << 18UL )
 /*-----------------------------------------------------------*/
 
 /**
@@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
  * any secure calls.
  */
 #define portNO_SECURE_CONTEXT    0
+
+/**
+ * @brief Constants required to check and configure PACBTI security feature implementation.
+ */
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+    #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
+
+    #define portCONTROL_UPAC_EN      ( 1UL << 7UL )
+    #define portCONTROL_PAC_EN       ( 1UL << 6UL )
+    #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
+    #define portCONTROL_BTI_EN       ( 1UL << 4UL )
+
+#endif /* portHAS_PACBTI_FEATURE */
 /*-----------------------------------------------------------*/
 
 /**
@@ -410,6 +427,26 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+/**
+ * @brief Configures PACBTI features.
+ *
+ * This function configures the Pointer Authentication, and Branch Target
+ * Identification security features as per the user configuration. It returns
+ * the value of the special purpose CONTROL register accordingly, and optionally
+ * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
+ * architecture based) target supports PACBTI security feature.
+ *
+ * @param xWriteControlRegister Used to control whether the special purpose
+ * CONTROL register should be updated or not.
+ *
+ * @return CONTROL register value according to the configured PACBTI option.
+ */
+    static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
+
+#endif /* portHAS_PACBTI_FEATURE */
+
 /**
  * @brief Setup the timer to generate the tick interrupts.
  *
@@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                                          xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
     {
         uint32_t ulIndex = 0;
+        uint32_t ulControl = 0x0;
 
         xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
         ulIndex++;
@@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
+        #if ( portHAS_PACBTI_FEATURE == 1 )
+        {
+            /* Check PACBTI security feature configuration before pushing the
+             * CONTROL register's value on task's TCB. */
+            ulControl = prvConfigurePACBTI( pdFALSE );
+        }
+        #endif /* portHAS_PACBTI_FEATURE */
+
         if( xRunPrivileged == pdTRUE )
         {
             xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
-            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+            xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
             ulIndex++;
         }
         else
         {
             xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
-            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+            xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
             ulIndex++;
         }
 
@@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
+    #if ( portHAS_PACBTI_FEATURE == 1 )
+    {
+        /* Set the CONTROL register value based on PACBTI security feature
+         * configuration before starting the first task. */
+        ( void) prvConfigurePACBTI( pdTRUE );
+    }
+    #endif /* portHAS_PACBTI_FEATURE */
+
     #if ( configENABLE_MPU == 1 )
     {
         /* Setup the Memory Protection Unit (MPU). */
@@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
 
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
+
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+    static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
+    {
+        uint32_t ulControl = 0x0;
+
+        /* Ensure that PACBTI is implemented. */
+        configASSERT( portID_ISAR5_REG != 0x0 );
+
+        /* Enable UsageFault exception if PAC or BTI is enabled. */
+        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+        {
+            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
+        }
+        #endif
+
+        #if( configENABLE_PAC == 1 )
+        {
+            ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
+        }
+        #endif
+
+        #if( configENABLE_BTI == 1 )
+        {
+            ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
+        }
+        #endif
+
+        if( xWriteControlRegister == pdTRUE )
+        {
+            __asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
+        }
+
+        return ulControl;
+    }
+
+#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h
index a7f9db767..5acf8160f 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -51,6 +53,7 @@
 #define portARCH_NAME                    "Cortex-M23"
 #define portHAS_ARMV8M_MAIN_EXTENSION    0
 #define portARMV8M_MINOR_VERSION         0
+#define portHAS_PACBTI_FEATURE           0
 #define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h
index a7f9db767..5acf8160f 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -51,6 +53,7 @@
 #define portARCH_NAME                    "Cortex-M23"
 #define portHAS_ARMV8M_MAIN_EXTENSION    0
 #define portARMV8M_MINOR_VERSION         0
+#define portHAS_PACBTI_FEATURE           0
 #define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c
index aa9379fdf..f09840a46 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -134,8 +136,9 @@
             "   ldr  r4, =xSecureContext                        \n"
             "   str  r1, [r4]                                   \n" /* Set xSecureContext to this task's value for the same. */
             "   msr  psplim, r2                                 \n" /* Set this task's PSPLIM value. */
-            "   movs r1, #2                                     \n" /* r1 = 2. */
-            "   msr  CONTROL, r1                                \n" /* Switch to use PSP in the thread mode. */
+            "   mrs  r1, control                                \n" /* Obtain current control register value. */
+            "   orrs r1, r1, #2                                 \n" /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointer (PSP). */
+            "   msr control, r1                                 \n" /* Write back the new control register value. */
             "   adds r0, #32                                    \n" /* Discard everything up to r0. */
             "   msr  psp, r0                                    \n" /* This is now the new top of stack to use in the task. */
             "   isb                                             \n"
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h
index 0fc61f23c..452a43655 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -51,6 +53,7 @@
 #define portARCH_NAME                    "Cortex-M33"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
 #define portARMV8M_MINOR_VERSION         0
+#define portHAS_PACBTI_FEATURE           0
 #define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c
index cdb2632c5..47996cd9e 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -130,8 +132,9 @@
             "                                                   \n"
             "   ldm  r0!, {r1-r2}                               \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
             "   msr  psplim, r1                                 \n" /* Set this task's PSPLIM value. */
-            "   movs r1, #2                                     \n" /* r1 = 2. */
-            "   msr  CONTROL, r1                                \n" /* Switch to use PSP in the thread mode. */
+            "   mrs  r1, control                                \n" /* Obtain current control register value. */
+            "   orrs r1, r1, #2                                 \n" /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointer (PSP). */
+            "   msr control, r1                                 \n" /* Write back the new control register value. */
             "   adds r0, #32                                    \n" /* Discard everything up to r0. */
             "   msr  psp, r0                                    \n" /* This is now the new top of stack to use in the task. */
             "   isb                                             \n"
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h
index 0fc61f23c..452a43655 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -51,6 +53,7 @@
 #define portARCH_NAME                    "Cortex-M33"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
 #define portARMV8M_MINOR_VERSION         0
+#define portHAS_PACBTI_FEATURE           0
 #define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM35P/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM35P/portmacro.h
index 4db6e6d4a..82b84f92a 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM35P/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM35P/portmacro.h
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -51,6 +53,7 @@
 #define portARCH_NAME                    "Cortex-M35P"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
 #define portARMV8M_MINOR_VERSION         0
+#define portHAS_PACBTI_FEATURE           0
 #define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM55/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM55/portmacro.h
index c6a179c52..369d6825f 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM55/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM55/portmacro.h
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -56,6 +58,7 @@
 #define portARCH_NAME                    "Cortex-M55"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
 #define portARMV8M_MINOR_VERSION         1
+#define portHAS_PACBTI_FEATURE           0
 #define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM85/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM85/portmacro.h
index 7e14f2696..5067aa573 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM85/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM85/portmacro.h
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -56,6 +58,7 @@
 #define portARCH_NAME                    "Cortex-M85"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
 #define portARMV8M_MINOR_VERSION         1
+#define portHAS_PACBTI_FEATURE           1
 #define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h
index 9dfcc9132..4940e345e 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -51,6 +53,7 @@
 #define portARCH_NAME                    "Cortex-M23"
 #define portHAS_ARMV8M_MAIN_EXTENSION    0
 #define portARMV8M_MINOR_VERSION         0
+#define portHAS_PACBTI_FEATURE           0
 #define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h
index 9dfcc9132..4940e345e 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -51,6 +53,7 @@
 #define portARCH_NAME                    "Cortex-M23"
 #define portHAS_ARMV8M_MAIN_EXTENSION    0
 #define portARMV8M_MINOR_VERSION         0
+#define portHAS_PACBTI_FEATURE           0
 #define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s
index 418c5f887..f4b7ab20f 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -179,8 +181,9 @@ vRestoreContextOfFirstTask:
     ldr  r4, =xSecureContext
     str  r1, [r4]                           /* Set xSecureContext to this task's value for the same. */
     msr  psplim, r2                         /* Set this task's PSPLIM value. */
-    movs r1, #2                             /* r1 = 2. */
-    msr  CONTROL, r1                        /* Switch to use PSP in the thread mode. */
+    mrs  r1, control                        /* Obtain current control register value. */
+    orrs r1, r1, #2                         /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointe (PSP). */
+    msr control, r1                         /* Write back the new control register value. */
     adds r0, #32                            /* Discard everything up to r0. */
     msr  psp, r0                            /* This is now the new top of stack to use in the task. */
     isb
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h
index 0f7d100df..5e126dbf9 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -51,6 +53,7 @@
 #define portARCH_NAME                    "Cortex-M33"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
 #define portARMV8M_MINOR_VERSION         0
+#define portHAS_PACBTI_FEATURE           0
 #define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s
index 44f662646..be06f67ad 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -165,8 +167,9 @@ vRestoreContextOfFirstTask:
 
     ldm  r0!, {r1-r2}                       /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
     msr  psplim, r1                         /* Set this task's PSPLIM value. */
-    movs r1, #2                             /* r1 = 2. */
-    msr  CONTROL, r1                        /* Switch to use PSP in the thread mode. */
+    mrs  r1, control                        /* Obtain current control register value. */
+    orrs r1, r1, #2                         /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointe (PSP). */
+    msr control, r1                         /* Write back the new control register value. */
     adds r0, #32                            /* Discard everything up to r0. */
     msr  psp, r0                            /* This is now the new top of stack to use in the task. */
     isb
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h
index 0f7d100df..5e126dbf9 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -51,6 +53,7 @@
 #define portARCH_NAME                    "Cortex-M33"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
 #define portARMV8M_MINOR_VERSION         0
+#define portHAS_PACBTI_FEATURE           0
 #define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM35P/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM35P/portmacro.h
index 0ad1009b6..d617ac0c2 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM35P/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM35P/portmacro.h
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -51,6 +53,7 @@
 #define portARCH_NAME                    "Cortex-M35P"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
 #define portARMV8M_MINOR_VERSION         0
+#define portHAS_PACBTI_FEATURE           0
 #define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM55/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM55/portmacro.h
index 597af66fa..6a5272267 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM55/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM55/portmacro.h
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -56,6 +58,7 @@
 #define portARCH_NAME                    "Cortex-M55"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
 #define portARMV8M_MINOR_VERSION         1
+#define portHAS_PACBTI_FEATURE           0
 #define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM85/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM85/portmacro.h
index ff5c9895d..c88adc77c 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM85/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM85/portmacro.h
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -56,6 +58,7 @@
 #define portARCH_NAME                    "Cortex-M85"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
 #define portARMV8M_MINOR_VERSION         1
+#define portHAS_PACBTI_FEATURE           1
 #define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
diff --git a/portable/CMakeLists.txt b/portable/CMakeLists.txt
index 553397589..4c39c76bf 100644
--- a/portable/CMakeLists.txt
+++ b/portable/CMakeLists.txt
@@ -453,6 +453,12 @@ add_library(freertos_kernel_port OBJECT
         IAR/ARM_CM33_NTZ/non_secure/portasm.s
         IAR/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.S>
 
+    $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM33_TFM>:
+        IAR/ARM_CM33_NTZ/non_secure/port.c
+        IAR/ARM_CM33_NTZ/non_secure/portasm.s
+        IAR/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.S
+        ThirdParty/GCC/ARM_TFM/os_wrapper_freertos.c>
+
     $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM35P_NONSECURE>:
         IAR/ARM_CM35P/non_secure/port.c
         IAR/ARM_CM35P/non_secure/portasm.s
@@ -486,6 +492,12 @@ add_library(freertos_kernel_port OBJECT
         IAR/ARM_CM55_NTZ/non_secure/portasm.s
         IAR/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.S>
 
+    $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM55_TFM>:
+        IAR/ARM_CM55_NTZ/non_secure/port.c
+        IAR/ARM_CM55_NTZ/non_secure/portasm.s
+        IAR/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.S
+        ThirdParty/GCC/ARM_TFM/os_wrapper_freertos.c>
+
     $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM85_NONSECURE>:
         IAR/ARM_CM85/non_secure/port.c
         IAR/ARM_CM85/non_secure/portasm.s
@@ -502,6 +514,12 @@ add_library(freertos_kernel_port OBJECT
         IAR/ARM_CM85_NTZ/non_secure/portasm.s
         IAR/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.S>
 
+        $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM85_TFM>:
+        IAR/ARM_CM85_NTZ/non_secure/port.c
+        IAR/ARM_CM85_NTZ/non_secure/portasm.s
+        IAR/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.S
+        ThirdParty/GCC/ARM_TFM/os_wrapper_freertos.c>
+
     # ARMv7-R Ports for IAR EWARM
     $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CRX_NOGIC>:
         IAR/ARM_CRx_No_GIC/port.c
@@ -755,13 +773,112 @@ if( FREERTOS_PORT MATCHES "GCC_ARM_CM(3|4)_MPU" OR
     FREERTOS_PORT MATCHES "GCC_ARM_CM(23|33|55|85)_NONSECURE" OR
     FREERTOS_PORT MATCHES "GCC_ARM_CM(33|55|85)_TFM" OR
     FREERTOS_PORT MATCHES "IAR_ARM_CM(23|33|55|85)_NTZ_NONSECURE" OR
-    FREERTOS_PORT MATCHES "IAR_ARM_CM(23|33|55|85)_NONSECURE"
+    FREERTOS_PORT MATCHES "IAR_ARM_CM(23|33|55|85)_NONSECURE" OR
+    FREERTOS_PORT MATCHES "IAR_ARM_CM(33|55|85)_TFM"
 )
     target_sources(freertos_kernel_port PRIVATE
         Common/mpu_wrappers.c
         Common/mpu_wrappers_v2.c
     )
 endif()
+
+if (DEFINED FREERTOS_ARM_V_8_1_M_PACBTI_CONFIG )
+
+    if(${CMAKE_C_COMPILER_ID} STREQUAL "GNU")
+        message(FATAL_ERROR "ARMv8.1-M PACBTI support in the kernel is not yet enabled for GNU toolchain due to known issues.")
+    endif()
+
+    if(FREERTOS_PORT MATCHES ".*ARM_CM85")
+        if(FREERTOS_ARM_V_8_1_M_PACBTI_CONFIG STREQUAL "ARM_V_8_1_M_PACBTI_CONFIG_STANDARD")
+            target_compile_options(freertos_kernel_port PUBLIC $<$<STREQUAL:${CMAKE_C_COMPILER_ID},ARMClang>:-mbranch-protection=standard>)
+            target_compile_options(freertos_kernel_port PUBLIC $<$<STREQUAL:${CMAKE_C_COMPILER_ID},IAR>:$<$<COMPILE_LANGUAGE:C,CXX>:--branch_protection=bti+pac-ret>>)
+            target_compile_definitions(freertos_config
+                INTERFACE
+                    configENABLE_PAC=1
+                    configENABLE_BTI=1
+            )
+        elseif(FREERTOS_ARM_V_8_1_M_PACBTI_CONFIG STREQUAL "ARM_V_8_1_M_PACBTI_CONFIG_PACRET_LEAF_BTI")
+            if(${CMAKE_C_COMPILER_ID} STREQUAL "ARMClang")
+                target_compile_options(freertos_kernel_port
+                    PUBLIC
+                        -mbranch-protection=bti+pac-ret+leaf
+                )
+                target_compile_definitions(freertos_config
+                    PUBLIC
+                        configENABLE_PAC=1
+                        configENABLE_BTI=1
+                )
+            elseif(${CMAKE_C_COMPILER_ID} STREQUAL "IAR")
+                message(FATAL_ERROR "ARM_V_8_1_M_PACBTI_CONFIG_PACRET_LEAF_BTI PACBTI option is not supported on IAR Compiler.")
+            endif()
+        elseif(FREERTOS_ARM_V_8_1_M_PACBTI_CONFIG STREQUAL "ARM_V_8_1_M_PACBTI_CONFIG_PACRET")
+            target_compile_options(freertos_kernel_port PUBLIC $<$<STREQUAL:${CMAKE_C_COMPILER_ID},ARMClang>:-mbranch-protection=pac-ret>)
+            target_compile_options(freertos_kernel_port PUBLIC $<$<STREQUAL:${CMAKE_C_COMPILER_ID},IAR>:$<$<COMPILE_LANGUAGE:C,CXX>:--branch_protection=pac-ret>>)
+            target_compile_definitions(freertos_config
+                PUBLIC
+                    configENABLE_PAC=1
+            )
+        elseif(FREERTOS_ARM_V_8_1_M_PACBTI_CONFIG STREQUAL "ARM_V_8_1_M_PACBTI_CONFIG_PACRET_LEAF")
+            if(${CMAKE_C_COMPILER_ID} STREQUAL "ARMClang")
+                target_compile_options(freertos_kernel_port
+                    PUBLIC
+                        -mbranch-protection=pac-ret+leaf
+                )
+                target_compile_definitions(freertos_config
+                    PUBLIC
+                        configENABLE_PAC=1
+                )
+            elseif(${CMAKE_C_COMPILER_ID} STREQUAL "IAR")
+                message(FATAL_ERROR "ARM_V_8_1_M_PACBTI_CONFIG_PACRET_LEAF PACBTI option is not supported on IAR Compiler.")
+            endif()
+        elseif(FREERTOS_ARM_V_8_1_M_PACBTI_CONFIG STREQUAL "ARM_V_8_1_M_PACBTI_CONFIG_BTI")
+            target_compile_options(freertos_kernel_port PUBLIC $<$<STREQUAL:${CMAKE_C_COMPILER_ID},ARMClang>:-mbranch-protection=bti>)
+            target_compile_options(freertos_kernel_port PUBLIC $<$<STREQUAL:${CMAKE_C_COMPILER_ID},IAR>:$<$<COMPILE_LANGUAGE:C,CXX>:--branch_protection=bti>>)
+            target_compile_definitions(freertos_config
+                PUBLIC
+                    configENABLE_BTI=1
+            )
+        elseif(FREERTOS_ARM_V_8_1_M_PACBTI_CONFIG STREQUAL "ARM_V_8_1_M_PACBTI_CONFIG_NONE")
+            if(${CMAKE_C_COMPILER_ID} STREQUAL "ARMClang")
+                target_compile_options(freertos_kernel_port
+                    PUBLIC
+                        -mbranch-protection=none
+                )
+            endif()
+            target_compile_definitions(freertos_config
+                PUBLIC
+                    configENABLE_PAC=0
+                    configENABLE_BTI=0
+            )
+        else()
+            message(FATAL_ERROR "Invalid FREERTOS_ARM_V_8_1_M_PACBTI_CONFIG configuration, the supported configurations are
+            ARM_V_8_1_M_PACBTI_CONFIG_STANDARD,
+            ARM_V_8_1_M_PACBTI_CONFIG_PACRET_LEAF_BTI,
+            ARM_V_8_1_M_PACBTI_CONFIG_PACRET,
+            ARM_V_8_1_M_PACBTI_CONFIG_PACRET_LEAF,
+            ARM_V_8_1_M_PACBTI_CONFIG_BTI,
+            ARM_V_8_1_M_PACBTI_CONFIG_NONE
+            ")
+        endif()
+        if(NOT FREERTOS_ARM_V_8_1_M_PACBTI_CONFIG STREQUAL "ARM_V_8_1_M_PACBTI_CONFIG_NONE")
+            # The reason why `--library_security=pacbti-m` link option is defined for both `freertos_kernel_port`, and
+            # `freertos_kernel` targets even though `freertos_kernel_port` gets linked to `freertos_kernel` is that the
+            # `freertos_kernel_port` is an object library where its linker options don't propagate to the targets that
+            # link against it.
+            target_link_options(freertos_kernel_port
+                PUBLIC
+                    --library_security=pacbti-m
+            )
+            target_link_options(freertos_kernel
+                PUBLIC
+                    --library_security=pacbti-m
+            )
+        endif()
+    else()
+        message(FATAL_ERROR "FREERTOS_ARM_V_8_1_M_PACBTI_CONFIG option is currently only supported on ARM Cortex-M85 FreeRTOS port.")
+    endif()
+endif()
+
 add_library(freertos_kernel_port_headers INTERFACE)
 
 target_include_directories(freertos_kernel_port_headers INTERFACE
@@ -956,6 +1073,7 @@ target_include_directories(freertos_kernel_port_headers INTERFACE
     $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM33_NONSECURE>:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM33/non_secure>
     $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM33_SECURE>:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM33/secure>
     $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM33_NTZ_NONSECURE>:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM33_NTZ/non_secure>
+    $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM33_TFM>:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM33_NTZ/non_secure>
 
     $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM35P_NONSECURE>:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM35P/non_secure>
     $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM35P_SECURE>:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM35P/secure>
@@ -965,10 +1083,12 @@ target_include_directories(freertos_kernel_port_headers INTERFACE
     $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM55_NONSECURE>:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM55/non_secure>
     $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM55_SECURE>:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM55/secure>
     $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM55_NTZ_NONSECURE>:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM55_NTZ/non_secure>
+    $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM55_TFM>:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM55_NTZ/non_secure>
 
     $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM85_NONSECURE>:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM85/non_secure>
     $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM85_SECURE>:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM85/secure>
     $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM85_NTZ_NONSECURE>:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM85_NTZ/non_secure>
+    $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM85_TFM>:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM85_NTZ/non_secure>
 
     # ARMv7-R Ports for IAR EWARM
     $<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CRX_NOGIC>:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CRx_No_GIC>
diff --git a/portable/GCC/ARM_CM23/non_secure/port.c b/portable/GCC/ARM_CM23/non_secure/port.c
index 75e9ea9dd..5b399358e 100644
--- a/portable/GCC/ARM_CM23/non_secure/port.c
+++ b/portable/GCC/ARM_CM23/non_secure/port.c
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
 #define portSCB_VTOR_REG                      ( *( ( portISR_t ** ) 0xe000ed08 ) )
 #define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
 #define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )
+#define portSCB_USG_FAULT_ENABLE_BIT          ( 1UL << 18UL )
 /*-----------------------------------------------------------*/
 
 /**
@@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
  * any secure calls.
  */
 #define portNO_SECURE_CONTEXT    0
+
+/**
+ * @brief Constants required to check and configure PACBTI security feature implementation.
+ */
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+    #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
+
+    #define portCONTROL_UPAC_EN      ( 1UL << 7UL )
+    #define portCONTROL_PAC_EN       ( 1UL << 6UL )
+    #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
+    #define portCONTROL_BTI_EN       ( 1UL << 4UL )
+
+#endif /* portHAS_PACBTI_FEATURE */
 /*-----------------------------------------------------------*/
 
 /**
@@ -410,6 +427,26 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+/**
+ * @brief Configures PACBTI features.
+ *
+ * This function configures the Pointer Authentication, and Branch Target
+ * Identification security features as per the user configuration. It returns
+ * the value of the special purpose CONTROL register accordingly, and optionally
+ * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
+ * architecture based) target supports PACBTI security feature.
+ *
+ * @param xWriteControlRegister Used to control whether the special purpose
+ * CONTROL register should be updated or not.
+ *
+ * @return CONTROL register value according to the configured PACBTI option.
+ */
+    static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
+
+#endif /* portHAS_PACBTI_FEATURE */
+
 /**
  * @brief Setup the timer to generate the tick interrupts.
  *
@@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                                          xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
     {
         uint32_t ulIndex = 0;
+        uint32_t ulControl = 0x0;
 
         xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
         ulIndex++;
@@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
+        #if ( portHAS_PACBTI_FEATURE == 1 )
+        {
+            /* Check PACBTI security feature configuration before pushing the
+             * CONTROL register's value on task's TCB. */
+            ulControl = prvConfigurePACBTI( pdFALSE );
+        }
+        #endif /* portHAS_PACBTI_FEATURE */
+
         if( xRunPrivileged == pdTRUE )
         {
             xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
-            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+            xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
             ulIndex++;
         }
         else
         {
             xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
-            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+            xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
             ulIndex++;
         }
 
@@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
+    #if ( portHAS_PACBTI_FEATURE == 1 )
+    {
+        /* Set the CONTROL register value based on PACBTI security feature
+         * configuration before starting the first task. */
+        ( void) prvConfigurePACBTI( pdTRUE );
+    }
+    #endif /* portHAS_PACBTI_FEATURE */
+
     #if ( configENABLE_MPU == 1 )
     {
         /* Setup the Memory Protection Unit (MPU). */
@@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
 
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
+
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+    static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
+    {
+        uint32_t ulControl = 0x0;
+
+        /* Ensure that PACBTI is implemented. */
+        configASSERT( portID_ISAR5_REG != 0x0 );
+
+        /* Enable UsageFault exception if PAC or BTI is enabled. */
+        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+        {
+            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
+        }
+        #endif
+
+        #if( configENABLE_PAC == 1 )
+        {
+            ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
+        }
+        #endif
+
+        #if( configENABLE_BTI == 1 )
+        {
+            ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
+        }
+        #endif
+
+        if( xWriteControlRegister == pdTRUE )
+        {
+            __asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
+        }
+
+        return ulControl;
+    }
+
+#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM23/non_secure/portmacro.h b/portable/GCC/ARM_CM23/non_secure/portmacro.h
index a7f9db767..5acf8160f 100644
--- a/portable/GCC/ARM_CM23/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM23/non_secure/portmacro.h
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -51,6 +53,7 @@
 #define portARCH_NAME                    "Cortex-M23"
 #define portHAS_ARMV8M_MAIN_EXTENSION    0
 #define portARMV8M_MINOR_VERSION         0
+#define portHAS_PACBTI_FEATURE           0
 #define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
index 75e9ea9dd..5b399358e 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
 #define portSCB_VTOR_REG                      ( *( ( portISR_t ** ) 0xe000ed08 ) )
 #define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
 #define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )
+#define portSCB_USG_FAULT_ENABLE_BIT          ( 1UL << 18UL )
 /*-----------------------------------------------------------*/
 
 /**
@@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
  * any secure calls.
  */
 #define portNO_SECURE_CONTEXT    0
+
+/**
+ * @brief Constants required to check and configure PACBTI security feature implementation.
+ */
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+    #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
+
+    #define portCONTROL_UPAC_EN      ( 1UL << 7UL )
+    #define portCONTROL_PAC_EN       ( 1UL << 6UL )
+    #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
+    #define portCONTROL_BTI_EN       ( 1UL << 4UL )
+
+#endif /* portHAS_PACBTI_FEATURE */
 /*-----------------------------------------------------------*/
 
 /**
@@ -410,6 +427,26 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+/**
+ * @brief Configures PACBTI features.
+ *
+ * This function configures the Pointer Authentication, and Branch Target
+ * Identification security features as per the user configuration. It returns
+ * the value of the special purpose CONTROL register accordingly, and optionally
+ * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
+ * architecture based) target supports PACBTI security feature.
+ *
+ * @param xWriteControlRegister Used to control whether the special purpose
+ * CONTROL register should be updated or not.
+ *
+ * @return CONTROL register value according to the configured PACBTI option.
+ */
+    static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
+
+#endif /* portHAS_PACBTI_FEATURE */
+
 /**
  * @brief Setup the timer to generate the tick interrupts.
  *
@@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                                          xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
     {
         uint32_t ulIndex = 0;
+        uint32_t ulControl = 0x0;
 
         xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
         ulIndex++;
@@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
+        #if ( portHAS_PACBTI_FEATURE == 1 )
+        {
+            /* Check PACBTI security feature configuration before pushing the
+             * CONTROL register's value on task's TCB. */
+            ulControl = prvConfigurePACBTI( pdFALSE );
+        }
+        #endif /* portHAS_PACBTI_FEATURE */
+
         if( xRunPrivileged == pdTRUE )
         {
             xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
-            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+            xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
             ulIndex++;
         }
         else
         {
             xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
-            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+            xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
             ulIndex++;
         }
 
@@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
+    #if ( portHAS_PACBTI_FEATURE == 1 )
+    {
+        /* Set the CONTROL register value based on PACBTI security feature
+         * configuration before starting the first task. */
+        ( void) prvConfigurePACBTI( pdTRUE );
+    }
+    #endif /* portHAS_PACBTI_FEATURE */
+
     #if ( configENABLE_MPU == 1 )
     {
         /* Setup the Memory Protection Unit (MPU). */
@@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
 
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
+
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+    static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
+    {
+        uint32_t ulControl = 0x0;
+
+        /* Ensure that PACBTI is implemented. */
+        configASSERT( portID_ISAR5_REG != 0x0 );
+
+        /* Enable UsageFault exception if PAC or BTI is enabled. */
+        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+        {
+            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
+        }
+        #endif
+
+        #if( configENABLE_PAC == 1 )
+        {
+            ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
+        }
+        #endif
+
+        #if( configENABLE_BTI == 1 )
+        {
+            ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
+        }
+        #endif
+
+        if( xWriteControlRegister == pdTRUE )
+        {
+            __asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
+        }
+
+        return ulControl;
+    }
+
+#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h b/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h
index a7f9db767..5acf8160f 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -51,6 +53,7 @@
 #define portARCH_NAME                    "Cortex-M23"
 #define portHAS_ARMV8M_MAIN_EXTENSION    0
 #define portARMV8M_MINOR_VERSION         0
+#define portHAS_PACBTI_FEATURE           0
 #define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/GCC/ARM_CM33/non_secure/port.c b/portable/GCC/ARM_CM33/non_secure/port.c
index 75e9ea9dd..5b399358e 100644
--- a/portable/GCC/ARM_CM33/non_secure/port.c
+++ b/portable/GCC/ARM_CM33/non_secure/port.c
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
 #define portSCB_VTOR_REG                      ( *( ( portISR_t ** ) 0xe000ed08 ) )
 #define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
 #define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )
+#define portSCB_USG_FAULT_ENABLE_BIT          ( 1UL << 18UL )
 /*-----------------------------------------------------------*/
 
 /**
@@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
  * any secure calls.
  */
 #define portNO_SECURE_CONTEXT    0
+
+/**
+ * @brief Constants required to check and configure PACBTI security feature implementation.
+ */
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+    #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
+
+    #define portCONTROL_UPAC_EN      ( 1UL << 7UL )
+    #define portCONTROL_PAC_EN       ( 1UL << 6UL )
+    #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
+    #define portCONTROL_BTI_EN       ( 1UL << 4UL )
+
+#endif /* portHAS_PACBTI_FEATURE */
 /*-----------------------------------------------------------*/
 
 /**
@@ -410,6 +427,26 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+/**
+ * @brief Configures PACBTI features.
+ *
+ * This function configures the Pointer Authentication, and Branch Target
+ * Identification security features as per the user configuration. It returns
+ * the value of the special purpose CONTROL register accordingly, and optionally
+ * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
+ * architecture based) target supports PACBTI security feature.
+ *
+ * @param xWriteControlRegister Used to control whether the special purpose
+ * CONTROL register should be updated or not.
+ *
+ * @return CONTROL register value according to the configured PACBTI option.
+ */
+    static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
+
+#endif /* portHAS_PACBTI_FEATURE */
+
 /**
  * @brief Setup the timer to generate the tick interrupts.
  *
@@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                                          xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
     {
         uint32_t ulIndex = 0;
+        uint32_t ulControl = 0x0;
 
         xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
         ulIndex++;
@@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
+        #if ( portHAS_PACBTI_FEATURE == 1 )
+        {
+            /* Check PACBTI security feature configuration before pushing the
+             * CONTROL register's value on task's TCB. */
+            ulControl = prvConfigurePACBTI( pdFALSE );
+        }
+        #endif /* portHAS_PACBTI_FEATURE */
+
         if( xRunPrivileged == pdTRUE )
         {
             xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
-            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+            xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
             ulIndex++;
         }
         else
         {
             xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
-            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+            xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
             ulIndex++;
         }
 
@@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
+    #if ( portHAS_PACBTI_FEATURE == 1 )
+    {
+        /* Set the CONTROL register value based on PACBTI security feature
+         * configuration before starting the first task. */
+        ( void) prvConfigurePACBTI( pdTRUE );
+    }
+    #endif /* portHAS_PACBTI_FEATURE */
+
     #if ( configENABLE_MPU == 1 )
     {
         /* Setup the Memory Protection Unit (MPU). */
@@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
 
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
+
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+    static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
+    {
+        uint32_t ulControl = 0x0;
+
+        /* Ensure that PACBTI is implemented. */
+        configASSERT( portID_ISAR5_REG != 0x0 );
+
+        /* Enable UsageFault exception if PAC or BTI is enabled. */
+        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+        {
+            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
+        }
+        #endif
+
+        #if( configENABLE_PAC == 1 )
+        {
+            ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
+        }
+        #endif
+
+        #if( configENABLE_BTI == 1 )
+        {
+            ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
+        }
+        #endif
+
+        if( xWriteControlRegister == pdTRUE )
+        {
+            __asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
+        }
+
+        return ulControl;
+    }
+
+#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM33/non_secure/portasm.c b/portable/GCC/ARM_CM33/non_secure/portasm.c
index aa9379fdf..f09840a46 100644
--- a/portable/GCC/ARM_CM33/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM33/non_secure/portasm.c
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -134,8 +136,9 @@
             "   ldr  r4, =xSecureContext                        \n"
             "   str  r1, [r4]                                   \n" /* Set xSecureContext to this task's value for the same. */
             "   msr  psplim, r2                                 \n" /* Set this task's PSPLIM value. */
-            "   movs r1, #2                                     \n" /* r1 = 2. */
-            "   msr  CONTROL, r1                                \n" /* Switch to use PSP in the thread mode. */
+            "   mrs  r1, control                                \n" /* Obtain current control register value. */
+            "   orrs r1, r1, #2                                 \n" /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointer (PSP). */
+            "   msr control, r1                                 \n" /* Write back the new control register value. */
             "   adds r0, #32                                    \n" /* Discard everything up to r0. */
             "   msr  psp, r0                                    \n" /* This is now the new top of stack to use in the task. */
             "   isb                                             \n"
diff --git a/portable/GCC/ARM_CM33/non_secure/portmacro.h b/portable/GCC/ARM_CM33/non_secure/portmacro.h
index 0fc61f23c..452a43655 100644
--- a/portable/GCC/ARM_CM33/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM33/non_secure/portmacro.h
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -51,6 +53,7 @@
 #define portARCH_NAME                    "Cortex-M33"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
 #define portARMV8M_MINOR_VERSION         0
+#define portHAS_PACBTI_FEATURE           0
 #define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
index 75e9ea9dd..5b399358e 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
 #define portSCB_VTOR_REG                      ( *( ( portISR_t ** ) 0xe000ed08 ) )
 #define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
 #define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )
+#define portSCB_USG_FAULT_ENABLE_BIT          ( 1UL << 18UL )
 /*-----------------------------------------------------------*/
 
 /**
@@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
  * any secure calls.
  */
 #define portNO_SECURE_CONTEXT    0
+
+/**
+ * @brief Constants required to check and configure PACBTI security feature implementation.
+ */
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+    #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
+
+    #define portCONTROL_UPAC_EN      ( 1UL << 7UL )
+    #define portCONTROL_PAC_EN       ( 1UL << 6UL )
+    #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
+    #define portCONTROL_BTI_EN       ( 1UL << 4UL )
+
+#endif /* portHAS_PACBTI_FEATURE */
 /*-----------------------------------------------------------*/
 
 /**
@@ -410,6 +427,26 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+/**
+ * @brief Configures PACBTI features.
+ *
+ * This function configures the Pointer Authentication, and Branch Target
+ * Identification security features as per the user configuration. It returns
+ * the value of the special purpose CONTROL register accordingly, and optionally
+ * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
+ * architecture based) target supports PACBTI security feature.
+ *
+ * @param xWriteControlRegister Used to control whether the special purpose
+ * CONTROL register should be updated or not.
+ *
+ * @return CONTROL register value according to the configured PACBTI option.
+ */
+    static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
+
+#endif /* portHAS_PACBTI_FEATURE */
+
 /**
  * @brief Setup the timer to generate the tick interrupts.
  *
@@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                                          xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
     {
         uint32_t ulIndex = 0;
+        uint32_t ulControl = 0x0;
 
         xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
         ulIndex++;
@@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
+        #if ( portHAS_PACBTI_FEATURE == 1 )
+        {
+            /* Check PACBTI security feature configuration before pushing the
+             * CONTROL register's value on task's TCB. */
+            ulControl = prvConfigurePACBTI( pdFALSE );
+        }
+        #endif /* portHAS_PACBTI_FEATURE */
+
         if( xRunPrivileged == pdTRUE )
         {
             xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
-            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+            xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
             ulIndex++;
         }
         else
         {
             xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
-            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+            xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
             ulIndex++;
         }
 
@@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
+    #if ( portHAS_PACBTI_FEATURE == 1 )
+    {
+        /* Set the CONTROL register value based on PACBTI security feature
+         * configuration before starting the first task. */
+        ( void) prvConfigurePACBTI( pdTRUE );
+    }
+    #endif /* portHAS_PACBTI_FEATURE */
+
     #if ( configENABLE_MPU == 1 )
     {
         /* Setup the Memory Protection Unit (MPU). */
@@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
 
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
+
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+    static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
+    {
+        uint32_t ulControl = 0x0;
+
+        /* Ensure that PACBTI is implemented. */
+        configASSERT( portID_ISAR5_REG != 0x0 );
+
+        /* Enable UsageFault exception if PAC or BTI is enabled. */
+        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+        {
+            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
+        }
+        #endif
+
+        #if( configENABLE_PAC == 1 )
+        {
+            ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
+        }
+        #endif
+
+        #if( configENABLE_BTI == 1 )
+        {
+            ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
+        }
+        #endif
+
+        if( xWriteControlRegister == pdTRUE )
+        {
+            __asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
+        }
+
+        return ulControl;
+    }
+
+#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c b/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c
index cdb2632c5..47996cd9e 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -130,8 +132,9 @@
             "                                                   \n"
             "   ldm  r0!, {r1-r2}                               \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
             "   msr  psplim, r1                                 \n" /* Set this task's PSPLIM value. */
-            "   movs r1, #2                                     \n" /* r1 = 2. */
-            "   msr  CONTROL, r1                                \n" /* Switch to use PSP in the thread mode. */
+            "   mrs  r1, control                                \n" /* Obtain current control register value. */
+            "   orrs r1, r1, #2                                 \n" /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointer (PSP). */
+            "   msr control, r1                                 \n" /* Write back the new control register value. */
             "   adds r0, #32                                    \n" /* Discard everything up to r0. */
             "   msr  psp, r0                                    \n" /* This is now the new top of stack to use in the task. */
             "   isb                                             \n"
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h b/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h
index 0fc61f23c..452a43655 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -51,6 +53,7 @@
 #define portARCH_NAME                    "Cortex-M33"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
 #define portARMV8M_MINOR_VERSION         0
+#define portHAS_PACBTI_FEATURE           0
 #define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/GCC/ARM_CM35P/non_secure/port.c b/portable/GCC/ARM_CM35P/non_secure/port.c
index 75e9ea9dd..5b399358e 100644
--- a/portable/GCC/ARM_CM35P/non_secure/port.c
+++ b/portable/GCC/ARM_CM35P/non_secure/port.c
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
 #define portSCB_VTOR_REG                      ( *( ( portISR_t ** ) 0xe000ed08 ) )
 #define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
 #define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )
+#define portSCB_USG_FAULT_ENABLE_BIT          ( 1UL << 18UL )
 /*-----------------------------------------------------------*/
 
 /**
@@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
  * any secure calls.
  */
 #define portNO_SECURE_CONTEXT    0
+
+/**
+ * @brief Constants required to check and configure PACBTI security feature implementation.
+ */
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+    #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
+
+    #define portCONTROL_UPAC_EN      ( 1UL << 7UL )
+    #define portCONTROL_PAC_EN       ( 1UL << 6UL )
+    #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
+    #define portCONTROL_BTI_EN       ( 1UL << 4UL )
+
+#endif /* portHAS_PACBTI_FEATURE */
 /*-----------------------------------------------------------*/
 
 /**
@@ -410,6 +427,26 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+/**
+ * @brief Configures PACBTI features.
+ *
+ * This function configures the Pointer Authentication, and Branch Target
+ * Identification security features as per the user configuration. It returns
+ * the value of the special purpose CONTROL register accordingly, and optionally
+ * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
+ * architecture based) target supports PACBTI security feature.
+ *
+ * @param xWriteControlRegister Used to control whether the special purpose
+ * CONTROL register should be updated or not.
+ *
+ * @return CONTROL register value according to the configured PACBTI option.
+ */
+    static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
+
+#endif /* portHAS_PACBTI_FEATURE */
+
 /**
  * @brief Setup the timer to generate the tick interrupts.
  *
@@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                                          xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
     {
         uint32_t ulIndex = 0;
+        uint32_t ulControl = 0x0;
 
         xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
         ulIndex++;
@@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
+        #if ( portHAS_PACBTI_FEATURE == 1 )
+        {
+            /* Check PACBTI security feature configuration before pushing the
+             * CONTROL register's value on task's TCB. */
+            ulControl = prvConfigurePACBTI( pdFALSE );
+        }
+        #endif /* portHAS_PACBTI_FEATURE */
+
         if( xRunPrivileged == pdTRUE )
         {
             xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
-            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+            xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
             ulIndex++;
         }
         else
         {
             xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
-            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+            xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
             ulIndex++;
         }
 
@@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
+    #if ( portHAS_PACBTI_FEATURE == 1 )
+    {
+        /* Set the CONTROL register value based on PACBTI security feature
+         * configuration before starting the first task. */
+        ( void) prvConfigurePACBTI( pdTRUE );
+    }
+    #endif /* portHAS_PACBTI_FEATURE */
+
     #if ( configENABLE_MPU == 1 )
     {
         /* Setup the Memory Protection Unit (MPU). */
@@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
 
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
+
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+    static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
+    {
+        uint32_t ulControl = 0x0;
+
+        /* Ensure that PACBTI is implemented. */
+        configASSERT( portID_ISAR5_REG != 0x0 );
+
+        /* Enable UsageFault exception if PAC or BTI is enabled. */
+        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+        {
+            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
+        }
+        #endif
+
+        #if( configENABLE_PAC == 1 )
+        {
+            ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
+        }
+        #endif
+
+        #if( configENABLE_BTI == 1 )
+        {
+            ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
+        }
+        #endif
+
+        if( xWriteControlRegister == pdTRUE )
+        {
+            __asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
+        }
+
+        return ulControl;
+    }
+
+#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM35P/non_secure/portasm.c b/portable/GCC/ARM_CM35P/non_secure/portasm.c
index aa9379fdf..f09840a46 100644
--- a/portable/GCC/ARM_CM35P/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM35P/non_secure/portasm.c
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -134,8 +136,9 @@
             "   ldr  r4, =xSecureContext                        \n"
             "   str  r1, [r4]                                   \n" /* Set xSecureContext to this task's value for the same. */
             "   msr  psplim, r2                                 \n" /* Set this task's PSPLIM value. */
-            "   movs r1, #2                                     \n" /* r1 = 2. */
-            "   msr  CONTROL, r1                                \n" /* Switch to use PSP in the thread mode. */
+            "   mrs  r1, control                                \n" /* Obtain current control register value. */
+            "   orrs r1, r1, #2                                 \n" /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointer (PSP). */
+            "   msr control, r1                                 \n" /* Write back the new control register value. */
             "   adds r0, #32                                    \n" /* Discard everything up to r0. */
             "   msr  psp, r0                                    \n" /* This is now the new top of stack to use in the task. */
             "   isb                                             \n"
diff --git a/portable/GCC/ARM_CM35P/non_secure/portmacro.h b/portable/GCC/ARM_CM35P/non_secure/portmacro.h
index 4db6e6d4a..82b84f92a 100644
--- a/portable/GCC/ARM_CM35P/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM35P/non_secure/portmacro.h
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -51,6 +53,7 @@
 #define portARCH_NAME                    "Cortex-M35P"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
 #define portARMV8M_MINOR_VERSION         0
+#define portHAS_PACBTI_FEATURE           0
 #define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c b/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
index 75e9ea9dd..5b399358e 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
 #define portSCB_VTOR_REG                      ( *( ( portISR_t ** ) 0xe000ed08 ) )
 #define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
 #define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )
+#define portSCB_USG_FAULT_ENABLE_BIT          ( 1UL << 18UL )
 /*-----------------------------------------------------------*/
 
 /**
@@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
  * any secure calls.
  */
 #define portNO_SECURE_CONTEXT    0
+
+/**
+ * @brief Constants required to check and configure PACBTI security feature implementation.
+ */
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+    #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
+
+    #define portCONTROL_UPAC_EN      ( 1UL << 7UL )
+    #define portCONTROL_PAC_EN       ( 1UL << 6UL )
+    #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
+    #define portCONTROL_BTI_EN       ( 1UL << 4UL )
+
+#endif /* portHAS_PACBTI_FEATURE */
 /*-----------------------------------------------------------*/
 
 /**
@@ -410,6 +427,26 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+/**
+ * @brief Configures PACBTI features.
+ *
+ * This function configures the Pointer Authentication, and Branch Target
+ * Identification security features as per the user configuration. It returns
+ * the value of the special purpose CONTROL register accordingly, and optionally
+ * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
+ * architecture based) target supports PACBTI security feature.
+ *
+ * @param xWriteControlRegister Used to control whether the special purpose
+ * CONTROL register should be updated or not.
+ *
+ * @return CONTROL register value according to the configured PACBTI option.
+ */
+    static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
+
+#endif /* portHAS_PACBTI_FEATURE */
+
 /**
  * @brief Setup the timer to generate the tick interrupts.
  *
@@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                                          xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
     {
         uint32_t ulIndex = 0;
+        uint32_t ulControl = 0x0;
 
         xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
         ulIndex++;
@@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
+        #if ( portHAS_PACBTI_FEATURE == 1 )
+        {
+            /* Check PACBTI security feature configuration before pushing the
+             * CONTROL register's value on task's TCB. */
+            ulControl = prvConfigurePACBTI( pdFALSE );
+        }
+        #endif /* portHAS_PACBTI_FEATURE */
+
         if( xRunPrivileged == pdTRUE )
         {
             xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
-            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+            xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
             ulIndex++;
         }
         else
         {
             xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
-            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+            xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
             ulIndex++;
         }
 
@@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
+    #if ( portHAS_PACBTI_FEATURE == 1 )
+    {
+        /* Set the CONTROL register value based on PACBTI security feature
+         * configuration before starting the first task. */
+        ( void) prvConfigurePACBTI( pdTRUE );
+    }
+    #endif /* portHAS_PACBTI_FEATURE */
+
     #if ( configENABLE_MPU == 1 )
     {
         /* Setup the Memory Protection Unit (MPU). */
@@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
 
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
+
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+    static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
+    {
+        uint32_t ulControl = 0x0;
+
+        /* Ensure that PACBTI is implemented. */
+        configASSERT( portID_ISAR5_REG != 0x0 );
+
+        /* Enable UsageFault exception if PAC or BTI is enabled. */
+        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+        {
+            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
+        }
+        #endif
+
+        #if( configENABLE_PAC == 1 )
+        {
+            ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
+        }
+        #endif
+
+        #if( configENABLE_BTI == 1 )
+        {
+            ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
+        }
+        #endif
+
+        if( xWriteControlRegister == pdTRUE )
+        {
+            __asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
+        }
+
+        return ulControl;
+    }
+
+#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.c b/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.c
index cdb2632c5..47996cd9e 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.c
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -130,8 +132,9 @@
             "                                                   \n"
             "   ldm  r0!, {r1-r2}                               \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
             "   msr  psplim, r1                                 \n" /* Set this task's PSPLIM value. */
-            "   movs r1, #2                                     \n" /* r1 = 2. */
-            "   msr  CONTROL, r1                                \n" /* Switch to use PSP in the thread mode. */
+            "   mrs  r1, control                                \n" /* Obtain current control register value. */
+            "   orrs r1, r1, #2                                 \n" /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointer (PSP). */
+            "   msr control, r1                                 \n" /* Write back the new control register value. */
             "   adds r0, #32                                    \n" /* Discard everything up to r0. */
             "   msr  psp, r0                                    \n" /* This is now the new top of stack to use in the task. */
             "   isb                                             \n"
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacro.h b/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacro.h
index 4db6e6d4a..82b84f92a 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacro.h
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -51,6 +53,7 @@
 #define portARCH_NAME                    "Cortex-M35P"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
 #define portARMV8M_MINOR_VERSION         0
+#define portHAS_PACBTI_FEATURE           0
 #define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/GCC/ARM_CM55/non_secure/port.c b/portable/GCC/ARM_CM55/non_secure/port.c
index 75e9ea9dd..5b399358e 100644
--- a/portable/GCC/ARM_CM55/non_secure/port.c
+++ b/portable/GCC/ARM_CM55/non_secure/port.c
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
 #define portSCB_VTOR_REG                      ( *( ( portISR_t ** ) 0xe000ed08 ) )
 #define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
 #define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )
+#define portSCB_USG_FAULT_ENABLE_BIT          ( 1UL << 18UL )
 /*-----------------------------------------------------------*/
 
 /**
@@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
  * any secure calls.
  */
 #define portNO_SECURE_CONTEXT    0
+
+/**
+ * @brief Constants required to check and configure PACBTI security feature implementation.
+ */
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+    #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
+
+    #define portCONTROL_UPAC_EN      ( 1UL << 7UL )
+    #define portCONTROL_PAC_EN       ( 1UL << 6UL )
+    #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
+    #define portCONTROL_BTI_EN       ( 1UL << 4UL )
+
+#endif /* portHAS_PACBTI_FEATURE */
 /*-----------------------------------------------------------*/
 
 /**
@@ -410,6 +427,26 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+/**
+ * @brief Configures PACBTI features.
+ *
+ * This function configures the Pointer Authentication, and Branch Target
+ * Identification security features as per the user configuration. It returns
+ * the value of the special purpose CONTROL register accordingly, and optionally
+ * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
+ * architecture based) target supports PACBTI security feature.
+ *
+ * @param xWriteControlRegister Used to control whether the special purpose
+ * CONTROL register should be updated or not.
+ *
+ * @return CONTROL register value according to the configured PACBTI option.
+ */
+    static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
+
+#endif /* portHAS_PACBTI_FEATURE */
+
 /**
  * @brief Setup the timer to generate the tick interrupts.
  *
@@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                                          xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
     {
         uint32_t ulIndex = 0;
+        uint32_t ulControl = 0x0;
 
         xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
         ulIndex++;
@@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
+        #if ( portHAS_PACBTI_FEATURE == 1 )
+        {
+            /* Check PACBTI security feature configuration before pushing the
+             * CONTROL register's value on task's TCB. */
+            ulControl = prvConfigurePACBTI( pdFALSE );
+        }
+        #endif /* portHAS_PACBTI_FEATURE */
+
         if( xRunPrivileged == pdTRUE )
         {
             xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
-            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+            xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
             ulIndex++;
         }
         else
         {
             xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
-            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+            xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
             ulIndex++;
         }
 
@@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
+    #if ( portHAS_PACBTI_FEATURE == 1 )
+    {
+        /* Set the CONTROL register value based on PACBTI security feature
+         * configuration before starting the first task. */
+        ( void) prvConfigurePACBTI( pdTRUE );
+    }
+    #endif /* portHAS_PACBTI_FEATURE */
+
     #if ( configENABLE_MPU == 1 )
     {
         /* Setup the Memory Protection Unit (MPU). */
@@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
 
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
+
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+    static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
+    {
+        uint32_t ulControl = 0x0;
+
+        /* Ensure that PACBTI is implemented. */
+        configASSERT( portID_ISAR5_REG != 0x0 );
+
+        /* Enable UsageFault exception if PAC or BTI is enabled. */
+        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+        {
+            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
+        }
+        #endif
+
+        #if( configENABLE_PAC == 1 )
+        {
+            ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
+        }
+        #endif
+
+        #if( configENABLE_BTI == 1 )
+        {
+            ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
+        }
+        #endif
+
+        if( xWriteControlRegister == pdTRUE )
+        {
+            __asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
+        }
+
+        return ulControl;
+    }
+
+#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM55/non_secure/portasm.c b/portable/GCC/ARM_CM55/non_secure/portasm.c
index aa9379fdf..f09840a46 100644
--- a/portable/GCC/ARM_CM55/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM55/non_secure/portasm.c
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -134,8 +136,9 @@
             "   ldr  r4, =xSecureContext                        \n"
             "   str  r1, [r4]                                   \n" /* Set xSecureContext to this task's value for the same. */
             "   msr  psplim, r2                                 \n" /* Set this task's PSPLIM value. */
-            "   movs r1, #2                                     \n" /* r1 = 2. */
-            "   msr  CONTROL, r1                                \n" /* Switch to use PSP in the thread mode. */
+            "   mrs  r1, control                                \n" /* Obtain current control register value. */
+            "   orrs r1, r1, #2                                 \n" /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointer (PSP). */
+            "   msr control, r1                                 \n" /* Write back the new control register value. */
             "   adds r0, #32                                    \n" /* Discard everything up to r0. */
             "   msr  psp, r0                                    \n" /* This is now the new top of stack to use in the task. */
             "   isb                                             \n"
diff --git a/portable/GCC/ARM_CM55/non_secure/portmacro.h b/portable/GCC/ARM_CM55/non_secure/portmacro.h
index c6a179c52..369d6825f 100644
--- a/portable/GCC/ARM_CM55/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM55/non_secure/portmacro.h
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -56,6 +58,7 @@
 #define portARCH_NAME                    "Cortex-M55"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
 #define portARMV8M_MINOR_VERSION         1
+#define portHAS_PACBTI_FEATURE           0
 #define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/port.c b/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
index 75e9ea9dd..5b399358e 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
 #define portSCB_VTOR_REG                      ( *( ( portISR_t ** ) 0xe000ed08 ) )
 #define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
 #define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )
+#define portSCB_USG_FAULT_ENABLE_BIT          ( 1UL << 18UL )
 /*-----------------------------------------------------------*/
 
 /**
@@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
  * any secure calls.
  */
 #define portNO_SECURE_CONTEXT    0
+
+/**
+ * @brief Constants required to check and configure PACBTI security feature implementation.
+ */
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+    #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
+
+    #define portCONTROL_UPAC_EN      ( 1UL << 7UL )
+    #define portCONTROL_PAC_EN       ( 1UL << 6UL )
+    #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
+    #define portCONTROL_BTI_EN       ( 1UL << 4UL )
+
+#endif /* portHAS_PACBTI_FEATURE */
 /*-----------------------------------------------------------*/
 
 /**
@@ -410,6 +427,26 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+/**
+ * @brief Configures PACBTI features.
+ *
+ * This function configures the Pointer Authentication, and Branch Target
+ * Identification security features as per the user configuration. It returns
+ * the value of the special purpose CONTROL register accordingly, and optionally
+ * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
+ * architecture based) target supports PACBTI security feature.
+ *
+ * @param xWriteControlRegister Used to control whether the special purpose
+ * CONTROL register should be updated or not.
+ *
+ * @return CONTROL register value according to the configured PACBTI option.
+ */
+    static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
+
+#endif /* portHAS_PACBTI_FEATURE */
+
 /**
  * @brief Setup the timer to generate the tick interrupts.
  *
@@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                                          xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
     {
         uint32_t ulIndex = 0;
+        uint32_t ulControl = 0x0;
 
         xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
         ulIndex++;
@@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
+        #if ( portHAS_PACBTI_FEATURE == 1 )
+        {
+            /* Check PACBTI security feature configuration before pushing the
+             * CONTROL register's value on task's TCB. */
+            ulControl = prvConfigurePACBTI( pdFALSE );
+        }
+        #endif /* portHAS_PACBTI_FEATURE */
+
         if( xRunPrivileged == pdTRUE )
         {
             xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
-            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+            xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
             ulIndex++;
         }
         else
         {
             xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
-            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+            xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
             ulIndex++;
         }
 
@@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
+    #if ( portHAS_PACBTI_FEATURE == 1 )
+    {
+        /* Set the CONTROL register value based on PACBTI security feature
+         * configuration before starting the first task. */
+        ( void) prvConfigurePACBTI( pdTRUE );
+    }
+    #endif /* portHAS_PACBTI_FEATURE */
+
     #if ( configENABLE_MPU == 1 )
     {
         /* Setup the Memory Protection Unit (MPU). */
@@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
 
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
+
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+    static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
+    {
+        uint32_t ulControl = 0x0;
+
+        /* Ensure that PACBTI is implemented. */
+        configASSERT( portID_ISAR5_REG != 0x0 );
+
+        /* Enable UsageFault exception if PAC or BTI is enabled. */
+        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+        {
+            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
+        }
+        #endif
+
+        #if( configENABLE_PAC == 1 )
+        {
+            ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
+        }
+        #endif
+
+        #if( configENABLE_BTI == 1 )
+        {
+            ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
+        }
+        #endif
+
+        if( xWriteControlRegister == pdTRUE )
+        {
+            __asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
+        }
+
+        return ulControl;
+    }
+
+#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.c b/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.c
index cdb2632c5..47996cd9e 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.c
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -130,8 +132,9 @@
             "                                                   \n"
             "   ldm  r0!, {r1-r2}                               \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
             "   msr  psplim, r1                                 \n" /* Set this task's PSPLIM value. */
-            "   movs r1, #2                                     \n" /* r1 = 2. */
-            "   msr  CONTROL, r1                                \n" /* Switch to use PSP in the thread mode. */
+            "   mrs  r1, control                                \n" /* Obtain current control register value. */
+            "   orrs r1, r1, #2                                 \n" /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointer (PSP). */
+            "   msr control, r1                                 \n" /* Write back the new control register value. */
             "   adds r0, #32                                    \n" /* Discard everything up to r0. */
             "   msr  psp, r0                                    \n" /* This is now the new top of stack to use in the task. */
             "   isb                                             \n"
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/portmacro.h b/portable/GCC/ARM_CM55_NTZ/non_secure/portmacro.h
index c6a179c52..369d6825f 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/portmacro.h
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -56,6 +58,7 @@
 #define portARCH_NAME                    "Cortex-M55"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
 #define portARMV8M_MINOR_VERSION         1
+#define portHAS_PACBTI_FEATURE           0
 #define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/GCC/ARM_CM85/non_secure/port.c b/portable/GCC/ARM_CM85/non_secure/port.c
index 75e9ea9dd..5b399358e 100644
--- a/portable/GCC/ARM_CM85/non_secure/port.c
+++ b/portable/GCC/ARM_CM85/non_secure/port.c
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
 #define portSCB_VTOR_REG                      ( *( ( portISR_t ** ) 0xe000ed08 ) )
 #define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
 #define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )
+#define portSCB_USG_FAULT_ENABLE_BIT          ( 1UL << 18UL )
 /*-----------------------------------------------------------*/
 
 /**
@@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
  * any secure calls.
  */
 #define portNO_SECURE_CONTEXT    0
+
+/**
+ * @brief Constants required to check and configure PACBTI security feature implementation.
+ */
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+    #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
+
+    #define portCONTROL_UPAC_EN      ( 1UL << 7UL )
+    #define portCONTROL_PAC_EN       ( 1UL << 6UL )
+    #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
+    #define portCONTROL_BTI_EN       ( 1UL << 4UL )
+
+#endif /* portHAS_PACBTI_FEATURE */
 /*-----------------------------------------------------------*/
 
 /**
@@ -410,6 +427,26 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+/**
+ * @brief Configures PACBTI features.
+ *
+ * This function configures the Pointer Authentication, and Branch Target
+ * Identification security features as per the user configuration. It returns
+ * the value of the special purpose CONTROL register accordingly, and optionally
+ * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
+ * architecture based) target supports PACBTI security feature.
+ *
+ * @param xWriteControlRegister Used to control whether the special purpose
+ * CONTROL register should be updated or not.
+ *
+ * @return CONTROL register value according to the configured PACBTI option.
+ */
+    static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
+
+#endif /* portHAS_PACBTI_FEATURE */
+
 /**
  * @brief Setup the timer to generate the tick interrupts.
  *
@@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                                          xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
     {
         uint32_t ulIndex = 0;
+        uint32_t ulControl = 0x0;
 
         xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
         ulIndex++;
@@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
+        #if ( portHAS_PACBTI_FEATURE == 1 )
+        {
+            /* Check PACBTI security feature configuration before pushing the
+             * CONTROL register's value on task's TCB. */
+            ulControl = prvConfigurePACBTI( pdFALSE );
+        }
+        #endif /* portHAS_PACBTI_FEATURE */
+
         if( xRunPrivileged == pdTRUE )
         {
             xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
-            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+            xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
             ulIndex++;
         }
         else
         {
             xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
-            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+            xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
             ulIndex++;
         }
 
@@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
+    #if ( portHAS_PACBTI_FEATURE == 1 )
+    {
+        /* Set the CONTROL register value based on PACBTI security feature
+         * configuration before starting the first task. */
+        ( void) prvConfigurePACBTI( pdTRUE );
+    }
+    #endif /* portHAS_PACBTI_FEATURE */
+
     #if ( configENABLE_MPU == 1 )
     {
         /* Setup the Memory Protection Unit (MPU). */
@@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
 
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
+
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+    static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
+    {
+        uint32_t ulControl = 0x0;
+
+        /* Ensure that PACBTI is implemented. */
+        configASSERT( portID_ISAR5_REG != 0x0 );
+
+        /* Enable UsageFault exception if PAC or BTI is enabled. */
+        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+        {
+            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
+        }
+        #endif
+
+        #if( configENABLE_PAC == 1 )
+        {
+            ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
+        }
+        #endif
+
+        #if( configENABLE_BTI == 1 )
+        {
+            ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
+        }
+        #endif
+
+        if( xWriteControlRegister == pdTRUE )
+        {
+            __asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
+        }
+
+        return ulControl;
+    }
+
+#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM85/non_secure/portasm.c b/portable/GCC/ARM_CM85/non_secure/portasm.c
index aa9379fdf..f09840a46 100644
--- a/portable/GCC/ARM_CM85/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM85/non_secure/portasm.c
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -134,8 +136,9 @@
             "   ldr  r4, =xSecureContext                        \n"
             "   str  r1, [r4]                                   \n" /* Set xSecureContext to this task's value for the same. */
             "   msr  psplim, r2                                 \n" /* Set this task's PSPLIM value. */
-            "   movs r1, #2                                     \n" /* r1 = 2. */
-            "   msr  CONTROL, r1                                \n" /* Switch to use PSP in the thread mode. */
+            "   mrs  r1, control                                \n" /* Obtain current control register value. */
+            "   orrs r1, r1, #2                                 \n" /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointer (PSP). */
+            "   msr control, r1                                 \n" /* Write back the new control register value. */
             "   adds r0, #32                                    \n" /* Discard everything up to r0. */
             "   msr  psp, r0                                    \n" /* This is now the new top of stack to use in the task. */
             "   isb                                             \n"
diff --git a/portable/GCC/ARM_CM85/non_secure/portmacro.h b/portable/GCC/ARM_CM85/non_secure/portmacro.h
index 7e14f2696..5067aa573 100644
--- a/portable/GCC/ARM_CM85/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM85/non_secure/portmacro.h
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -56,6 +58,7 @@
 #define portARCH_NAME                    "Cortex-M85"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
 #define portARMV8M_MINOR_VERSION         1
+#define portHAS_PACBTI_FEATURE           1
 #define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/port.c b/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
index 75e9ea9dd..5b399358e 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
 #define portSCB_VTOR_REG                      ( *( ( portISR_t ** ) 0xe000ed08 ) )
 #define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
 #define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )
+#define portSCB_USG_FAULT_ENABLE_BIT          ( 1UL << 18UL )
 /*-----------------------------------------------------------*/
 
 /**
@@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
  * any secure calls.
  */
 #define portNO_SECURE_CONTEXT    0
+
+/**
+ * @brief Constants required to check and configure PACBTI security feature implementation.
+ */
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+    #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
+
+    #define portCONTROL_UPAC_EN      ( 1UL << 7UL )
+    #define portCONTROL_PAC_EN       ( 1UL << 6UL )
+    #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
+    #define portCONTROL_BTI_EN       ( 1UL << 4UL )
+
+#endif /* portHAS_PACBTI_FEATURE */
 /*-----------------------------------------------------------*/
 
 /**
@@ -410,6 +427,26 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+/**
+ * @brief Configures PACBTI features.
+ *
+ * This function configures the Pointer Authentication, and Branch Target
+ * Identification security features as per the user configuration. It returns
+ * the value of the special purpose CONTROL register accordingly, and optionally
+ * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
+ * architecture based) target supports PACBTI security feature.
+ *
+ * @param xWriteControlRegister Used to control whether the special purpose
+ * CONTROL register should be updated or not.
+ *
+ * @return CONTROL register value according to the configured PACBTI option.
+ */
+    static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
+
+#endif /* portHAS_PACBTI_FEATURE */
+
 /**
  * @brief Setup the timer to generate the tick interrupts.
  *
@@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                                          xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
     {
         uint32_t ulIndex = 0;
+        uint32_t ulControl = 0x0;
 
         xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
         ulIndex++;
@@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
+        #if ( portHAS_PACBTI_FEATURE == 1 )
+        {
+            /* Check PACBTI security feature configuration before pushing the
+             * CONTROL register's value on task's TCB. */
+            ulControl = prvConfigurePACBTI( pdFALSE );
+        }
+        #endif /* portHAS_PACBTI_FEATURE */
+
         if( xRunPrivileged == pdTRUE )
         {
             xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
-            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+            xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
             ulIndex++;
         }
         else
         {
             xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
-            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+            xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
             ulIndex++;
         }
 
@@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
+    #if ( portHAS_PACBTI_FEATURE == 1 )
+    {
+        /* Set the CONTROL register value based on PACBTI security feature
+         * configuration before starting the first task. */
+        ( void) prvConfigurePACBTI( pdTRUE );
+    }
+    #endif /* portHAS_PACBTI_FEATURE */
+
     #if ( configENABLE_MPU == 1 )
     {
         /* Setup the Memory Protection Unit (MPU). */
@@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
 
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
+
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+    static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
+    {
+        uint32_t ulControl = 0x0;
+
+        /* Ensure that PACBTI is implemented. */
+        configASSERT( portID_ISAR5_REG != 0x0 );
+
+        /* Enable UsageFault exception if PAC or BTI is enabled. */
+        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+        {
+            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
+        }
+        #endif
+
+        #if( configENABLE_PAC == 1 )
+        {
+            ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
+        }
+        #endif
+
+        #if( configENABLE_BTI == 1 )
+        {
+            ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
+        }
+        #endif
+
+        if( xWriteControlRegister == pdTRUE )
+        {
+            __asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
+        }
+
+        return ulControl;
+    }
+
+#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.c b/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.c
index cdb2632c5..47996cd9e 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.c
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -130,8 +132,9 @@
             "                                                   \n"
             "   ldm  r0!, {r1-r2}                               \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
             "   msr  psplim, r1                                 \n" /* Set this task's PSPLIM value. */
-            "   movs r1, #2                                     \n" /* r1 = 2. */
-            "   msr  CONTROL, r1                                \n" /* Switch to use PSP in the thread mode. */
+            "   mrs  r1, control                                \n" /* Obtain current control register value. */
+            "   orrs r1, r1, #2                                 \n" /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointer (PSP). */
+            "   msr control, r1                                 \n" /* Write back the new control register value. */
             "   adds r0, #32                                    \n" /* Discard everything up to r0. */
             "   msr  psp, r0                                    \n" /* This is now the new top of stack to use in the task. */
             "   isb                                             \n"
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/portmacro.h b/portable/GCC/ARM_CM85_NTZ/non_secure/portmacro.h
index 7e14f2696..5067aa573 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/portmacro.h
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -56,6 +58,7 @@
 #define portARCH_NAME                    "Cortex-M85"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
 #define portARMV8M_MINOR_VERSION         1
+#define portHAS_PACBTI_FEATURE           1
 #define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM23/non_secure/port.c b/portable/IAR/ARM_CM23/non_secure/port.c
index 75e9ea9dd..5b399358e 100644
--- a/portable/IAR/ARM_CM23/non_secure/port.c
+++ b/portable/IAR/ARM_CM23/non_secure/port.c
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
 #define portSCB_VTOR_REG                      ( *( ( portISR_t ** ) 0xe000ed08 ) )
 #define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
 #define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )
+#define portSCB_USG_FAULT_ENABLE_BIT          ( 1UL << 18UL )
 /*-----------------------------------------------------------*/
 
 /**
@@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
  * any secure calls.
  */
 #define portNO_SECURE_CONTEXT    0
+
+/**
+ * @brief Constants required to check and configure PACBTI security feature implementation.
+ */
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+    #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
+
+    #define portCONTROL_UPAC_EN      ( 1UL << 7UL )
+    #define portCONTROL_PAC_EN       ( 1UL << 6UL )
+    #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
+    #define portCONTROL_BTI_EN       ( 1UL << 4UL )
+
+#endif /* portHAS_PACBTI_FEATURE */
 /*-----------------------------------------------------------*/
 
 /**
@@ -410,6 +427,26 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+/**
+ * @brief Configures PACBTI features.
+ *
+ * This function configures the Pointer Authentication, and Branch Target
+ * Identification security features as per the user configuration. It returns
+ * the value of the special purpose CONTROL register accordingly, and optionally
+ * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
+ * architecture based) target supports PACBTI security feature.
+ *
+ * @param xWriteControlRegister Used to control whether the special purpose
+ * CONTROL register should be updated or not.
+ *
+ * @return CONTROL register value according to the configured PACBTI option.
+ */
+    static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
+
+#endif /* portHAS_PACBTI_FEATURE */
+
 /**
  * @brief Setup the timer to generate the tick interrupts.
  *
@@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                                          xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
     {
         uint32_t ulIndex = 0;
+        uint32_t ulControl = 0x0;
 
         xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
         ulIndex++;
@@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
+        #if ( portHAS_PACBTI_FEATURE == 1 )
+        {
+            /* Check PACBTI security feature configuration before pushing the
+             * CONTROL register's value on task's TCB. */
+            ulControl = prvConfigurePACBTI( pdFALSE );
+        }
+        #endif /* portHAS_PACBTI_FEATURE */
+
         if( xRunPrivileged == pdTRUE )
         {
             xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
-            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+            xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
             ulIndex++;
         }
         else
         {
             xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
-            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+            xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
             ulIndex++;
         }
 
@@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
+    #if ( portHAS_PACBTI_FEATURE == 1 )
+    {
+        /* Set the CONTROL register value based on PACBTI security feature
+         * configuration before starting the first task. */
+        ( void) prvConfigurePACBTI( pdTRUE );
+    }
+    #endif /* portHAS_PACBTI_FEATURE */
+
     #if ( configENABLE_MPU == 1 )
     {
         /* Setup the Memory Protection Unit (MPU). */
@@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
 
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
+
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+    static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
+    {
+        uint32_t ulControl = 0x0;
+
+        /* Ensure that PACBTI is implemented. */
+        configASSERT( portID_ISAR5_REG != 0x0 );
+
+        /* Enable UsageFault exception if PAC or BTI is enabled. */
+        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+        {
+            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
+        }
+        #endif
+
+        #if( configENABLE_PAC == 1 )
+        {
+            ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
+        }
+        #endif
+
+        #if( configENABLE_BTI == 1 )
+        {
+            ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
+        }
+        #endif
+
+        if( xWriteControlRegister == pdTRUE )
+        {
+            __asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
+        }
+
+        return ulControl;
+    }
+
+#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM23/non_secure/portmacro.h b/portable/IAR/ARM_CM23/non_secure/portmacro.h
index 9dfcc9132..4940e345e 100644
--- a/portable/IAR/ARM_CM23/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM23/non_secure/portmacro.h
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -51,6 +53,7 @@
 #define portARCH_NAME                    "Cortex-M23"
 #define portHAS_ARMV8M_MAIN_EXTENSION    0
 #define portARMV8M_MINOR_VERSION         0
+#define portHAS_PACBTI_FEATURE           0
 #define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
index 75e9ea9dd..5b399358e 100644
--- a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
 #define portSCB_VTOR_REG                      ( *( ( portISR_t ** ) 0xe000ed08 ) )
 #define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
 #define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )
+#define portSCB_USG_FAULT_ENABLE_BIT          ( 1UL << 18UL )
 /*-----------------------------------------------------------*/
 
 /**
@@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
  * any secure calls.
  */
 #define portNO_SECURE_CONTEXT    0
+
+/**
+ * @brief Constants required to check and configure PACBTI security feature implementation.
+ */
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+    #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
+
+    #define portCONTROL_UPAC_EN      ( 1UL << 7UL )
+    #define portCONTROL_PAC_EN       ( 1UL << 6UL )
+    #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
+    #define portCONTROL_BTI_EN       ( 1UL << 4UL )
+
+#endif /* portHAS_PACBTI_FEATURE */
 /*-----------------------------------------------------------*/
 
 /**
@@ -410,6 +427,26 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+/**
+ * @brief Configures PACBTI features.
+ *
+ * This function configures the Pointer Authentication, and Branch Target
+ * Identification security features as per the user configuration. It returns
+ * the value of the special purpose CONTROL register accordingly, and optionally
+ * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
+ * architecture based) target supports PACBTI security feature.
+ *
+ * @param xWriteControlRegister Used to control whether the special purpose
+ * CONTROL register should be updated or not.
+ *
+ * @return CONTROL register value according to the configured PACBTI option.
+ */
+    static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
+
+#endif /* portHAS_PACBTI_FEATURE */
+
 /**
  * @brief Setup the timer to generate the tick interrupts.
  *
@@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                                          xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
     {
         uint32_t ulIndex = 0;
+        uint32_t ulControl = 0x0;
 
         xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
         ulIndex++;
@@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
+        #if ( portHAS_PACBTI_FEATURE == 1 )
+        {
+            /* Check PACBTI security feature configuration before pushing the
+             * CONTROL register's value on task's TCB. */
+            ulControl = prvConfigurePACBTI( pdFALSE );
+        }
+        #endif /* portHAS_PACBTI_FEATURE */
+
         if( xRunPrivileged == pdTRUE )
         {
             xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
-            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+            xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
             ulIndex++;
         }
         else
         {
             xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
-            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+            xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
             ulIndex++;
         }
 
@@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
+    #if ( portHAS_PACBTI_FEATURE == 1 )
+    {
+        /* Set the CONTROL register value based on PACBTI security feature
+         * configuration before starting the first task. */
+        ( void) prvConfigurePACBTI( pdTRUE );
+    }
+    #endif /* portHAS_PACBTI_FEATURE */
+
     #if ( configENABLE_MPU == 1 )
     {
         /* Setup the Memory Protection Unit (MPU). */
@@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
 
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
+
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+    static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
+    {
+        uint32_t ulControl = 0x0;
+
+        /* Ensure that PACBTI is implemented. */
+        configASSERT( portID_ISAR5_REG != 0x0 );
+
+        /* Enable UsageFault exception if PAC or BTI is enabled. */
+        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+        {
+            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
+        }
+        #endif
+
+        #if( configENABLE_PAC == 1 )
+        {
+            ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
+        }
+        #endif
+
+        #if( configENABLE_BTI == 1 )
+        {
+            ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
+        }
+        #endif
+
+        if( xWriteControlRegister == pdTRUE )
+        {
+            __asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
+        }
+
+        return ulControl;
+    }
+
+#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h b/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h
index 9dfcc9132..4940e345e 100644
--- a/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -51,6 +53,7 @@
 #define portARCH_NAME                    "Cortex-M23"
 #define portHAS_ARMV8M_MAIN_EXTENSION    0
 #define portARMV8M_MINOR_VERSION         0
+#define portHAS_PACBTI_FEATURE           0
 #define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM33/non_secure/port.c b/portable/IAR/ARM_CM33/non_secure/port.c
index 75e9ea9dd..5b399358e 100644
--- a/portable/IAR/ARM_CM33/non_secure/port.c
+++ b/portable/IAR/ARM_CM33/non_secure/port.c
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
 #define portSCB_VTOR_REG                      ( *( ( portISR_t ** ) 0xe000ed08 ) )
 #define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
 #define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )
+#define portSCB_USG_FAULT_ENABLE_BIT          ( 1UL << 18UL )
 /*-----------------------------------------------------------*/
 
 /**
@@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
  * any secure calls.
  */
 #define portNO_SECURE_CONTEXT    0
+
+/**
+ * @brief Constants required to check and configure PACBTI security feature implementation.
+ */
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+    #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
+
+    #define portCONTROL_UPAC_EN      ( 1UL << 7UL )
+    #define portCONTROL_PAC_EN       ( 1UL << 6UL )
+    #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
+    #define portCONTROL_BTI_EN       ( 1UL << 4UL )
+
+#endif /* portHAS_PACBTI_FEATURE */
 /*-----------------------------------------------------------*/
 
 /**
@@ -410,6 +427,26 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+/**
+ * @brief Configures PACBTI features.
+ *
+ * This function configures the Pointer Authentication, and Branch Target
+ * Identification security features as per the user configuration. It returns
+ * the value of the special purpose CONTROL register accordingly, and optionally
+ * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
+ * architecture based) target supports PACBTI security feature.
+ *
+ * @param xWriteControlRegister Used to control whether the special purpose
+ * CONTROL register should be updated or not.
+ *
+ * @return CONTROL register value according to the configured PACBTI option.
+ */
+    static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
+
+#endif /* portHAS_PACBTI_FEATURE */
+
 /**
  * @brief Setup the timer to generate the tick interrupts.
  *
@@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                                          xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
     {
         uint32_t ulIndex = 0;
+        uint32_t ulControl = 0x0;
 
         xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
         ulIndex++;
@@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
+        #if ( portHAS_PACBTI_FEATURE == 1 )
+        {
+            /* Check PACBTI security feature configuration before pushing the
+             * CONTROL register's value on task's TCB. */
+            ulControl = prvConfigurePACBTI( pdFALSE );
+        }
+        #endif /* portHAS_PACBTI_FEATURE */
+
         if( xRunPrivileged == pdTRUE )
         {
             xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
-            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+            xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
             ulIndex++;
         }
         else
         {
             xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
-            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+            xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
             ulIndex++;
         }
 
@@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
+    #if ( portHAS_PACBTI_FEATURE == 1 )
+    {
+        /* Set the CONTROL register value based on PACBTI security feature
+         * configuration before starting the first task. */
+        ( void) prvConfigurePACBTI( pdTRUE );
+    }
+    #endif /* portHAS_PACBTI_FEATURE */
+
     #if ( configENABLE_MPU == 1 )
     {
         /* Setup the Memory Protection Unit (MPU). */
@@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
 
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
+
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+    static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
+    {
+        uint32_t ulControl = 0x0;
+
+        /* Ensure that PACBTI is implemented. */
+        configASSERT( portID_ISAR5_REG != 0x0 );
+
+        /* Enable UsageFault exception if PAC or BTI is enabled. */
+        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+        {
+            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
+        }
+        #endif
+
+        #if( configENABLE_PAC == 1 )
+        {
+            ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
+        }
+        #endif
+
+        #if( configENABLE_BTI == 1 )
+        {
+            ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
+        }
+        #endif
+
+        if( xWriteControlRegister == pdTRUE )
+        {
+            __asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
+        }
+
+        return ulControl;
+    }
+
+#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM33/non_secure/portasm.s b/portable/IAR/ARM_CM33/non_secure/portasm.s
index 418c5f887..f4b7ab20f 100644
--- a/portable/IAR/ARM_CM33/non_secure/portasm.s
+++ b/portable/IAR/ARM_CM33/non_secure/portasm.s
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -179,8 +181,9 @@ vRestoreContextOfFirstTask:
     ldr  r4, =xSecureContext
     str  r1, [r4]                           /* Set xSecureContext to this task's value for the same. */
     msr  psplim, r2                         /* Set this task's PSPLIM value. */
-    movs r1, #2                             /* r1 = 2. */
-    msr  CONTROL, r1                        /* Switch to use PSP in the thread mode. */
+    mrs  r1, control                        /* Obtain current control register value. */
+    orrs r1, r1, #2                         /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointe (PSP). */
+    msr control, r1                         /* Write back the new control register value. */
     adds r0, #32                            /* Discard everything up to r0. */
     msr  psp, r0                            /* This is now the new top of stack to use in the task. */
     isb
diff --git a/portable/IAR/ARM_CM33/non_secure/portmacro.h b/portable/IAR/ARM_CM33/non_secure/portmacro.h
index 0f7d100df..5e126dbf9 100644
--- a/portable/IAR/ARM_CM33/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM33/non_secure/portmacro.h
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -51,6 +53,7 @@
 #define portARCH_NAME                    "Cortex-M33"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
 #define portARMV8M_MINOR_VERSION         0
+#define portHAS_PACBTI_FEATURE           0
 #define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
index 75e9ea9dd..5b399358e 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
 #define portSCB_VTOR_REG                      ( *( ( portISR_t ** ) 0xe000ed08 ) )
 #define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
 #define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )
+#define portSCB_USG_FAULT_ENABLE_BIT          ( 1UL << 18UL )
 /*-----------------------------------------------------------*/
 
 /**
@@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
  * any secure calls.
  */
 #define portNO_SECURE_CONTEXT    0
+
+/**
+ * @brief Constants required to check and configure PACBTI security feature implementation.
+ */
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+    #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
+
+    #define portCONTROL_UPAC_EN      ( 1UL << 7UL )
+    #define portCONTROL_PAC_EN       ( 1UL << 6UL )
+    #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
+    #define portCONTROL_BTI_EN       ( 1UL << 4UL )
+
+#endif /* portHAS_PACBTI_FEATURE */
 /*-----------------------------------------------------------*/
 
 /**
@@ -410,6 +427,26 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+/**
+ * @brief Configures PACBTI features.
+ *
+ * This function configures the Pointer Authentication, and Branch Target
+ * Identification security features as per the user configuration. It returns
+ * the value of the special purpose CONTROL register accordingly, and optionally
+ * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
+ * architecture based) target supports PACBTI security feature.
+ *
+ * @param xWriteControlRegister Used to control whether the special purpose
+ * CONTROL register should be updated or not.
+ *
+ * @return CONTROL register value according to the configured PACBTI option.
+ */
+    static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
+
+#endif /* portHAS_PACBTI_FEATURE */
+
 /**
  * @brief Setup the timer to generate the tick interrupts.
  *
@@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                                          xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
     {
         uint32_t ulIndex = 0;
+        uint32_t ulControl = 0x0;
 
         xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
         ulIndex++;
@@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
+        #if ( portHAS_PACBTI_FEATURE == 1 )
+        {
+            /* Check PACBTI security feature configuration before pushing the
+             * CONTROL register's value on task's TCB. */
+            ulControl = prvConfigurePACBTI( pdFALSE );
+        }
+        #endif /* portHAS_PACBTI_FEATURE */
+
         if( xRunPrivileged == pdTRUE )
         {
             xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
-            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+            xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
             ulIndex++;
         }
         else
         {
             xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
-            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+            xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
             ulIndex++;
         }
 
@@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
+    #if ( portHAS_PACBTI_FEATURE == 1 )
+    {
+        /* Set the CONTROL register value based on PACBTI security feature
+         * configuration before starting the first task. */
+        ( void) prvConfigurePACBTI( pdTRUE );
+    }
+    #endif /* portHAS_PACBTI_FEATURE */
+
     #if ( configENABLE_MPU == 1 )
     {
         /* Setup the Memory Protection Unit (MPU). */
@@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
 
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
+
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+    static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
+    {
+        uint32_t ulControl = 0x0;
+
+        /* Ensure that PACBTI is implemented. */
+        configASSERT( portID_ISAR5_REG != 0x0 );
+
+        /* Enable UsageFault exception if PAC or BTI is enabled. */
+        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+        {
+            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
+        }
+        #endif
+
+        #if( configENABLE_PAC == 1 )
+        {
+            ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
+        }
+        #endif
+
+        #if( configENABLE_BTI == 1 )
+        {
+            ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
+        }
+        #endif
+
+        if( xWriteControlRegister == pdTRUE )
+        {
+            __asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
+        }
+
+        return ulControl;
+    }
+
+#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s b/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s
index 44f662646..be06f67ad 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -165,8 +167,9 @@ vRestoreContextOfFirstTask:
 
     ldm  r0!, {r1-r2}                       /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
     msr  psplim, r1                         /* Set this task's PSPLIM value. */
-    movs r1, #2                             /* r1 = 2. */
-    msr  CONTROL, r1                        /* Switch to use PSP in the thread mode. */
+    mrs  r1, control                        /* Obtain current control register value. */
+    orrs r1, r1, #2                         /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointe (PSP). */
+    msr control, r1                         /* Write back the new control register value. */
     adds r0, #32                            /* Discard everything up to r0. */
     msr  psp, r0                            /* This is now the new top of stack to use in the task. */
     isb
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h b/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h
index 0f7d100df..5e126dbf9 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -51,6 +53,7 @@
 #define portARCH_NAME                    "Cortex-M33"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
 #define portARMV8M_MINOR_VERSION         0
+#define portHAS_PACBTI_FEATURE           0
 #define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM35P/non_secure/port.c b/portable/IAR/ARM_CM35P/non_secure/port.c
index 75e9ea9dd..5b399358e 100644
--- a/portable/IAR/ARM_CM35P/non_secure/port.c
+++ b/portable/IAR/ARM_CM35P/non_secure/port.c
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
 #define portSCB_VTOR_REG                      ( *( ( portISR_t ** ) 0xe000ed08 ) )
 #define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
 #define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )
+#define portSCB_USG_FAULT_ENABLE_BIT          ( 1UL << 18UL )
 /*-----------------------------------------------------------*/
 
 /**
@@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
  * any secure calls.
  */
 #define portNO_SECURE_CONTEXT    0
+
+/**
+ * @brief Constants required to check and configure PACBTI security feature implementation.
+ */
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+    #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
+
+    #define portCONTROL_UPAC_EN      ( 1UL << 7UL )
+    #define portCONTROL_PAC_EN       ( 1UL << 6UL )
+    #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
+    #define portCONTROL_BTI_EN       ( 1UL << 4UL )
+
+#endif /* portHAS_PACBTI_FEATURE */
 /*-----------------------------------------------------------*/
 
 /**
@@ -410,6 +427,26 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+/**
+ * @brief Configures PACBTI features.
+ *
+ * This function configures the Pointer Authentication, and Branch Target
+ * Identification security features as per the user configuration. It returns
+ * the value of the special purpose CONTROL register accordingly, and optionally
+ * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
+ * architecture based) target supports PACBTI security feature.
+ *
+ * @param xWriteControlRegister Used to control whether the special purpose
+ * CONTROL register should be updated or not.
+ *
+ * @return CONTROL register value according to the configured PACBTI option.
+ */
+    static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
+
+#endif /* portHAS_PACBTI_FEATURE */
+
 /**
  * @brief Setup the timer to generate the tick interrupts.
  *
@@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                                          xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
     {
         uint32_t ulIndex = 0;
+        uint32_t ulControl = 0x0;
 
         xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
         ulIndex++;
@@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
+        #if ( portHAS_PACBTI_FEATURE == 1 )
+        {
+            /* Check PACBTI security feature configuration before pushing the
+             * CONTROL register's value on task's TCB. */
+            ulControl = prvConfigurePACBTI( pdFALSE );
+        }
+        #endif /* portHAS_PACBTI_FEATURE */
+
         if( xRunPrivileged == pdTRUE )
         {
             xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
-            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+            xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
             ulIndex++;
         }
         else
         {
             xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
-            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+            xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
             ulIndex++;
         }
 
@@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
+    #if ( portHAS_PACBTI_FEATURE == 1 )
+    {
+        /* Set the CONTROL register value based on PACBTI security feature
+         * configuration before starting the first task. */
+        ( void) prvConfigurePACBTI( pdTRUE );
+    }
+    #endif /* portHAS_PACBTI_FEATURE */
+
     #if ( configENABLE_MPU == 1 )
     {
         /* Setup the Memory Protection Unit (MPU). */
@@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
 
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
+
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+    static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
+    {
+        uint32_t ulControl = 0x0;
+
+        /* Ensure that PACBTI is implemented. */
+        configASSERT( portID_ISAR5_REG != 0x0 );
+
+        /* Enable UsageFault exception if PAC or BTI is enabled. */
+        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+        {
+            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
+        }
+        #endif
+
+        #if( configENABLE_PAC == 1 )
+        {
+            ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
+        }
+        #endif
+
+        #if( configENABLE_BTI == 1 )
+        {
+            ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
+        }
+        #endif
+
+        if( xWriteControlRegister == pdTRUE )
+        {
+            __asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
+        }
+
+        return ulControl;
+    }
+
+#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM35P/non_secure/portasm.s b/portable/IAR/ARM_CM35P/non_secure/portasm.s
index 418c5f887..f4b7ab20f 100644
--- a/portable/IAR/ARM_CM35P/non_secure/portasm.s
+++ b/portable/IAR/ARM_CM35P/non_secure/portasm.s
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -179,8 +181,9 @@ vRestoreContextOfFirstTask:
     ldr  r4, =xSecureContext
     str  r1, [r4]                           /* Set xSecureContext to this task's value for the same. */
     msr  psplim, r2                         /* Set this task's PSPLIM value. */
-    movs r1, #2                             /* r1 = 2. */
-    msr  CONTROL, r1                        /* Switch to use PSP in the thread mode. */
+    mrs  r1, control                        /* Obtain current control register value. */
+    orrs r1, r1, #2                         /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointe (PSP). */
+    msr control, r1                         /* Write back the new control register value. */
     adds r0, #32                            /* Discard everything up to r0. */
     msr  psp, r0                            /* This is now the new top of stack to use in the task. */
     isb
diff --git a/portable/IAR/ARM_CM35P/non_secure/portmacro.h b/portable/IAR/ARM_CM35P/non_secure/portmacro.h
index 0ad1009b6..d617ac0c2 100644
--- a/portable/IAR/ARM_CM35P/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM35P/non_secure/portmacro.h
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -51,6 +53,7 @@
 #define portARCH_NAME                    "Cortex-M35P"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
 #define portARMV8M_MINOR_VERSION         0
+#define portHAS_PACBTI_FEATURE           0
 #define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c b/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
index 75e9ea9dd..5b399358e 100644
--- a/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
 #define portSCB_VTOR_REG                      ( *( ( portISR_t ** ) 0xe000ed08 ) )
 #define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
 #define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )
+#define portSCB_USG_FAULT_ENABLE_BIT          ( 1UL << 18UL )
 /*-----------------------------------------------------------*/
 
 /**
@@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
  * any secure calls.
  */
 #define portNO_SECURE_CONTEXT    0
+
+/**
+ * @brief Constants required to check and configure PACBTI security feature implementation.
+ */
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+    #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
+
+    #define portCONTROL_UPAC_EN      ( 1UL << 7UL )
+    #define portCONTROL_PAC_EN       ( 1UL << 6UL )
+    #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
+    #define portCONTROL_BTI_EN       ( 1UL << 4UL )
+
+#endif /* portHAS_PACBTI_FEATURE */
 /*-----------------------------------------------------------*/
 
 /**
@@ -410,6 +427,26 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+/**
+ * @brief Configures PACBTI features.
+ *
+ * This function configures the Pointer Authentication, and Branch Target
+ * Identification security features as per the user configuration. It returns
+ * the value of the special purpose CONTROL register accordingly, and optionally
+ * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
+ * architecture based) target supports PACBTI security feature.
+ *
+ * @param xWriteControlRegister Used to control whether the special purpose
+ * CONTROL register should be updated or not.
+ *
+ * @return CONTROL register value according to the configured PACBTI option.
+ */
+    static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
+
+#endif /* portHAS_PACBTI_FEATURE */
+
 /**
  * @brief Setup the timer to generate the tick interrupts.
  *
@@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                                          xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
     {
         uint32_t ulIndex = 0;
+        uint32_t ulControl = 0x0;
 
         xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
         ulIndex++;
@@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
+        #if ( portHAS_PACBTI_FEATURE == 1 )
+        {
+            /* Check PACBTI security feature configuration before pushing the
+             * CONTROL register's value on task's TCB. */
+            ulControl = prvConfigurePACBTI( pdFALSE );
+        }
+        #endif /* portHAS_PACBTI_FEATURE */
+
         if( xRunPrivileged == pdTRUE )
         {
             xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
-            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+            xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
             ulIndex++;
         }
         else
         {
             xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
-            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+            xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
             ulIndex++;
         }
 
@@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
+    #if ( portHAS_PACBTI_FEATURE == 1 )
+    {
+        /* Set the CONTROL register value based on PACBTI security feature
+         * configuration before starting the first task. */
+        ( void) prvConfigurePACBTI( pdTRUE );
+    }
+    #endif /* portHAS_PACBTI_FEATURE */
+
     #if ( configENABLE_MPU == 1 )
     {
         /* Setup the Memory Protection Unit (MPU). */
@@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
 
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
+
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+    static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
+    {
+        uint32_t ulControl = 0x0;
+
+        /* Ensure that PACBTI is implemented. */
+        configASSERT( portID_ISAR5_REG != 0x0 );
+
+        /* Enable UsageFault exception if PAC or BTI is enabled. */
+        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+        {
+            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
+        }
+        #endif
+
+        #if( configENABLE_PAC == 1 )
+        {
+            ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
+        }
+        #endif
+
+        #if( configENABLE_BTI == 1 )
+        {
+            ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
+        }
+        #endif
+
+        if( xWriteControlRegister == pdTRUE )
+        {
+            __asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
+        }
+
+        return ulControl;
+    }
+
+#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.s b/portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.s
index 44f662646..be06f67ad 100644
--- a/portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.s
+++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.s
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -165,8 +167,9 @@ vRestoreContextOfFirstTask:
 
     ldm  r0!, {r1-r2}                       /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
     msr  psplim, r1                         /* Set this task's PSPLIM value. */
-    movs r1, #2                             /* r1 = 2. */
-    msr  CONTROL, r1                        /* Switch to use PSP in the thread mode. */
+    mrs  r1, control                        /* Obtain current control register value. */
+    orrs r1, r1, #2                         /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointe (PSP). */
+    msr control, r1                         /* Write back the new control register value. */
     adds r0, #32                            /* Discard everything up to r0. */
     msr  psp, r0                            /* This is now the new top of stack to use in the task. */
     isb
diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacro.h b/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacro.h
index 0ad1009b6..d617ac0c2 100644
--- a/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacro.h
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -51,6 +53,7 @@
 #define portARCH_NAME                    "Cortex-M35P"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
 #define portARMV8M_MINOR_VERSION         0
+#define portHAS_PACBTI_FEATURE           0
 #define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM55/non_secure/port.c b/portable/IAR/ARM_CM55/non_secure/port.c
index 75e9ea9dd..5b399358e 100644
--- a/portable/IAR/ARM_CM55/non_secure/port.c
+++ b/portable/IAR/ARM_CM55/non_secure/port.c
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
 #define portSCB_VTOR_REG                      ( *( ( portISR_t ** ) 0xe000ed08 ) )
 #define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
 #define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )
+#define portSCB_USG_FAULT_ENABLE_BIT          ( 1UL << 18UL )
 /*-----------------------------------------------------------*/
 
 /**
@@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
  * any secure calls.
  */
 #define portNO_SECURE_CONTEXT    0
+
+/**
+ * @brief Constants required to check and configure PACBTI security feature implementation.
+ */
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+    #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
+
+    #define portCONTROL_UPAC_EN      ( 1UL << 7UL )
+    #define portCONTROL_PAC_EN       ( 1UL << 6UL )
+    #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
+    #define portCONTROL_BTI_EN       ( 1UL << 4UL )
+
+#endif /* portHAS_PACBTI_FEATURE */
 /*-----------------------------------------------------------*/
 
 /**
@@ -410,6 +427,26 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+/**
+ * @brief Configures PACBTI features.
+ *
+ * This function configures the Pointer Authentication, and Branch Target
+ * Identification security features as per the user configuration. It returns
+ * the value of the special purpose CONTROL register accordingly, and optionally
+ * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
+ * architecture based) target supports PACBTI security feature.
+ *
+ * @param xWriteControlRegister Used to control whether the special purpose
+ * CONTROL register should be updated or not.
+ *
+ * @return CONTROL register value according to the configured PACBTI option.
+ */
+    static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
+
+#endif /* portHAS_PACBTI_FEATURE */
+
 /**
  * @brief Setup the timer to generate the tick interrupts.
  *
@@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                                          xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
     {
         uint32_t ulIndex = 0;
+        uint32_t ulControl = 0x0;
 
         xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
         ulIndex++;
@@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
+        #if ( portHAS_PACBTI_FEATURE == 1 )
+        {
+            /* Check PACBTI security feature configuration before pushing the
+             * CONTROL register's value on task's TCB. */
+            ulControl = prvConfigurePACBTI( pdFALSE );
+        }
+        #endif /* portHAS_PACBTI_FEATURE */
+
         if( xRunPrivileged == pdTRUE )
         {
             xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
-            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+            xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
             ulIndex++;
         }
         else
         {
             xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
-            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+            xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
             ulIndex++;
         }
 
@@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
+    #if ( portHAS_PACBTI_FEATURE == 1 )
+    {
+        /* Set the CONTROL register value based on PACBTI security feature
+         * configuration before starting the first task. */
+        ( void) prvConfigurePACBTI( pdTRUE );
+    }
+    #endif /* portHAS_PACBTI_FEATURE */
+
     #if ( configENABLE_MPU == 1 )
     {
         /* Setup the Memory Protection Unit (MPU). */
@@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
 
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
+
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+    static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
+    {
+        uint32_t ulControl = 0x0;
+
+        /* Ensure that PACBTI is implemented. */
+        configASSERT( portID_ISAR5_REG != 0x0 );
+
+        /* Enable UsageFault exception if PAC or BTI is enabled. */
+        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+        {
+            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
+        }
+        #endif
+
+        #if( configENABLE_PAC == 1 )
+        {
+            ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
+        }
+        #endif
+
+        #if( configENABLE_BTI == 1 )
+        {
+            ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
+        }
+        #endif
+
+        if( xWriteControlRegister == pdTRUE )
+        {
+            __asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
+        }
+
+        return ulControl;
+    }
+
+#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM55/non_secure/portasm.s b/portable/IAR/ARM_CM55/non_secure/portasm.s
index 418c5f887..f4b7ab20f 100644
--- a/portable/IAR/ARM_CM55/non_secure/portasm.s
+++ b/portable/IAR/ARM_CM55/non_secure/portasm.s
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -179,8 +181,9 @@ vRestoreContextOfFirstTask:
     ldr  r4, =xSecureContext
     str  r1, [r4]                           /* Set xSecureContext to this task's value for the same. */
     msr  psplim, r2                         /* Set this task's PSPLIM value. */
-    movs r1, #2                             /* r1 = 2. */
-    msr  CONTROL, r1                        /* Switch to use PSP in the thread mode. */
+    mrs  r1, control                        /* Obtain current control register value. */
+    orrs r1, r1, #2                         /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointe (PSP). */
+    msr control, r1                         /* Write back the new control register value. */
     adds r0, #32                            /* Discard everything up to r0. */
     msr  psp, r0                            /* This is now the new top of stack to use in the task. */
     isb
diff --git a/portable/IAR/ARM_CM55/non_secure/portmacro.h b/portable/IAR/ARM_CM55/non_secure/portmacro.h
index 597af66fa..6a5272267 100644
--- a/portable/IAR/ARM_CM55/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM55/non_secure/portmacro.h
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -56,6 +58,7 @@
 #define portARCH_NAME                    "Cortex-M55"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
 #define portARMV8M_MINOR_VERSION         1
+#define portHAS_PACBTI_FEATURE           0
 #define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/port.c b/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
index 75e9ea9dd..5b399358e 100644
--- a/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
 #define portSCB_VTOR_REG                      ( *( ( portISR_t ** ) 0xe000ed08 ) )
 #define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
 #define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )
+#define portSCB_USG_FAULT_ENABLE_BIT          ( 1UL << 18UL )
 /*-----------------------------------------------------------*/
 
 /**
@@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
  * any secure calls.
  */
 #define portNO_SECURE_CONTEXT    0
+
+/**
+ * @brief Constants required to check and configure PACBTI security feature implementation.
+ */
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+    #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
+
+    #define portCONTROL_UPAC_EN      ( 1UL << 7UL )
+    #define portCONTROL_PAC_EN       ( 1UL << 6UL )
+    #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
+    #define portCONTROL_BTI_EN       ( 1UL << 4UL )
+
+#endif /* portHAS_PACBTI_FEATURE */
 /*-----------------------------------------------------------*/
 
 /**
@@ -410,6 +427,26 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+/**
+ * @brief Configures PACBTI features.
+ *
+ * This function configures the Pointer Authentication, and Branch Target
+ * Identification security features as per the user configuration. It returns
+ * the value of the special purpose CONTROL register accordingly, and optionally
+ * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
+ * architecture based) target supports PACBTI security feature.
+ *
+ * @param xWriteControlRegister Used to control whether the special purpose
+ * CONTROL register should be updated or not.
+ *
+ * @return CONTROL register value according to the configured PACBTI option.
+ */
+    static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
+
+#endif /* portHAS_PACBTI_FEATURE */
+
 /**
  * @brief Setup the timer to generate the tick interrupts.
  *
@@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                                          xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
     {
         uint32_t ulIndex = 0;
+        uint32_t ulControl = 0x0;
 
         xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
         ulIndex++;
@@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
+        #if ( portHAS_PACBTI_FEATURE == 1 )
+        {
+            /* Check PACBTI security feature configuration before pushing the
+             * CONTROL register's value on task's TCB. */
+            ulControl = prvConfigurePACBTI( pdFALSE );
+        }
+        #endif /* portHAS_PACBTI_FEATURE */
+
         if( xRunPrivileged == pdTRUE )
         {
             xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
-            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+            xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
             ulIndex++;
         }
         else
         {
             xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
-            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+            xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
             ulIndex++;
         }
 
@@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
+    #if ( portHAS_PACBTI_FEATURE == 1 )
+    {
+        /* Set the CONTROL register value based on PACBTI security feature
+         * configuration before starting the first task. */
+        ( void) prvConfigurePACBTI( pdTRUE );
+    }
+    #endif /* portHAS_PACBTI_FEATURE */
+
     #if ( configENABLE_MPU == 1 )
     {
         /* Setup the Memory Protection Unit (MPU). */
@@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
 
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
+
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+    static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
+    {
+        uint32_t ulControl = 0x0;
+
+        /* Ensure that PACBTI is implemented. */
+        configASSERT( portID_ISAR5_REG != 0x0 );
+
+        /* Enable UsageFault exception if PAC or BTI is enabled. */
+        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+        {
+            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
+        }
+        #endif
+
+        #if( configENABLE_PAC == 1 )
+        {
+            ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
+        }
+        #endif
+
+        #if( configENABLE_BTI == 1 )
+        {
+            ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
+        }
+        #endif
+
+        if( xWriteControlRegister == pdTRUE )
+        {
+            __asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
+        }
+
+        return ulControl;
+    }
+
+#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.s b/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.s
index 44f662646..be06f67ad 100644
--- a/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.s
+++ b/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.s
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -165,8 +167,9 @@ vRestoreContextOfFirstTask:
 
     ldm  r0!, {r1-r2}                       /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
     msr  psplim, r1                         /* Set this task's PSPLIM value. */
-    movs r1, #2                             /* r1 = 2. */
-    msr  CONTROL, r1                        /* Switch to use PSP in the thread mode. */
+    mrs  r1, control                        /* Obtain current control register value. */
+    orrs r1, r1, #2                         /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointe (PSP). */
+    msr control, r1                         /* Write back the new control register value. */
     adds r0, #32                            /* Discard everything up to r0. */
     msr  psp, r0                            /* This is now the new top of stack to use in the task. */
     isb
diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/portmacro.h b/portable/IAR/ARM_CM55_NTZ/non_secure/portmacro.h
index 597af66fa..6a5272267 100644
--- a/portable/IAR/ARM_CM55_NTZ/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM55_NTZ/non_secure/portmacro.h
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -56,6 +58,7 @@
 #define portARCH_NAME                    "Cortex-M55"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
 #define portARMV8M_MINOR_VERSION         1
+#define portHAS_PACBTI_FEATURE           0
 #define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM85/non_secure/port.c b/portable/IAR/ARM_CM85/non_secure/port.c
index 75e9ea9dd..5b399358e 100644
--- a/portable/IAR/ARM_CM85/non_secure/port.c
+++ b/portable/IAR/ARM_CM85/non_secure/port.c
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
 #define portSCB_VTOR_REG                      ( *( ( portISR_t ** ) 0xe000ed08 ) )
 #define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
 #define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )
+#define portSCB_USG_FAULT_ENABLE_BIT          ( 1UL << 18UL )
 /*-----------------------------------------------------------*/
 
 /**
@@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
  * any secure calls.
  */
 #define portNO_SECURE_CONTEXT    0
+
+/**
+ * @brief Constants required to check and configure PACBTI security feature implementation.
+ */
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+    #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
+
+    #define portCONTROL_UPAC_EN      ( 1UL << 7UL )
+    #define portCONTROL_PAC_EN       ( 1UL << 6UL )
+    #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
+    #define portCONTROL_BTI_EN       ( 1UL << 4UL )
+
+#endif /* portHAS_PACBTI_FEATURE */
 /*-----------------------------------------------------------*/
 
 /**
@@ -410,6 +427,26 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+/**
+ * @brief Configures PACBTI features.
+ *
+ * This function configures the Pointer Authentication, and Branch Target
+ * Identification security features as per the user configuration. It returns
+ * the value of the special purpose CONTROL register accordingly, and optionally
+ * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
+ * architecture based) target supports PACBTI security feature.
+ *
+ * @param xWriteControlRegister Used to control whether the special purpose
+ * CONTROL register should be updated or not.
+ *
+ * @return CONTROL register value according to the configured PACBTI option.
+ */
+    static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
+
+#endif /* portHAS_PACBTI_FEATURE */
+
 /**
  * @brief Setup the timer to generate the tick interrupts.
  *
@@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                                          xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
     {
         uint32_t ulIndex = 0;
+        uint32_t ulControl = 0x0;
 
         xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
         ulIndex++;
@@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
+        #if ( portHAS_PACBTI_FEATURE == 1 )
+        {
+            /* Check PACBTI security feature configuration before pushing the
+             * CONTROL register's value on task's TCB. */
+            ulControl = prvConfigurePACBTI( pdFALSE );
+        }
+        #endif /* portHAS_PACBTI_FEATURE */
+
         if( xRunPrivileged == pdTRUE )
         {
             xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
-            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+            xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
             ulIndex++;
         }
         else
         {
             xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
-            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+            xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
             ulIndex++;
         }
 
@@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
+    #if ( portHAS_PACBTI_FEATURE == 1 )
+    {
+        /* Set the CONTROL register value based on PACBTI security feature
+         * configuration before starting the first task. */
+        ( void) prvConfigurePACBTI( pdTRUE );
+    }
+    #endif /* portHAS_PACBTI_FEATURE */
+
     #if ( configENABLE_MPU == 1 )
     {
         /* Setup the Memory Protection Unit (MPU). */
@@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
 
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
+
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+    static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
+    {
+        uint32_t ulControl = 0x0;
+
+        /* Ensure that PACBTI is implemented. */
+        configASSERT( portID_ISAR5_REG != 0x0 );
+
+        /* Enable UsageFault exception if PAC or BTI is enabled. */
+        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+        {
+            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
+        }
+        #endif
+
+        #if( configENABLE_PAC == 1 )
+        {
+            ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
+        }
+        #endif
+
+        #if( configENABLE_BTI == 1 )
+        {
+            ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
+        }
+        #endif
+
+        if( xWriteControlRegister == pdTRUE )
+        {
+            __asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
+        }
+
+        return ulControl;
+    }
+
+#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM85/non_secure/portasm.s b/portable/IAR/ARM_CM85/non_secure/portasm.s
index 418c5f887..f4b7ab20f 100644
--- a/portable/IAR/ARM_CM85/non_secure/portasm.s
+++ b/portable/IAR/ARM_CM85/non_secure/portasm.s
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -179,8 +181,9 @@ vRestoreContextOfFirstTask:
     ldr  r4, =xSecureContext
     str  r1, [r4]                           /* Set xSecureContext to this task's value for the same. */
     msr  psplim, r2                         /* Set this task's PSPLIM value. */
-    movs r1, #2                             /* r1 = 2. */
-    msr  CONTROL, r1                        /* Switch to use PSP in the thread mode. */
+    mrs  r1, control                        /* Obtain current control register value. */
+    orrs r1, r1, #2                         /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointe (PSP). */
+    msr control, r1                         /* Write back the new control register value. */
     adds r0, #32                            /* Discard everything up to r0. */
     msr  psp, r0                            /* This is now the new top of stack to use in the task. */
     isb
diff --git a/portable/IAR/ARM_CM85/non_secure/portmacro.h b/portable/IAR/ARM_CM85/non_secure/portmacro.h
index ff5c9895d..c88adc77c 100644
--- a/portable/IAR/ARM_CM85/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM85/non_secure/portmacro.h
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -56,6 +58,7 @@
 #define portARCH_NAME                    "Cortex-M85"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
 #define portARMV8M_MINOR_VERSION         1
+#define portHAS_PACBTI_FEATURE           1
 #define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/port.c b/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
index 75e9ea9dd..5b399358e 100644
--- a/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
 #define portSCB_VTOR_REG                      ( *( ( portISR_t ** ) 0xe000ed08 ) )
 #define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
 #define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )
+#define portSCB_USG_FAULT_ENABLE_BIT          ( 1UL << 18UL )
 /*-----------------------------------------------------------*/
 
 /**
@@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
  * any secure calls.
  */
 #define portNO_SECURE_CONTEXT    0
+
+/**
+ * @brief Constants required to check and configure PACBTI security feature implementation.
+ */
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+    #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
+
+    #define portCONTROL_UPAC_EN      ( 1UL << 7UL )
+    #define portCONTROL_PAC_EN       ( 1UL << 6UL )
+    #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
+    #define portCONTROL_BTI_EN       ( 1UL << 4UL )
+
+#endif /* portHAS_PACBTI_FEATURE */
 /*-----------------------------------------------------------*/
 
 /**
@@ -410,6 +427,26 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+/**
+ * @brief Configures PACBTI features.
+ *
+ * This function configures the Pointer Authentication, and Branch Target
+ * Identification security features as per the user configuration. It returns
+ * the value of the special purpose CONTROL register accordingly, and optionally
+ * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
+ * architecture based) target supports PACBTI security feature.
+ *
+ * @param xWriteControlRegister Used to control whether the special purpose
+ * CONTROL register should be updated or not.
+ *
+ * @return CONTROL register value according to the configured PACBTI option.
+ */
+    static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
+
+#endif /* portHAS_PACBTI_FEATURE */
+
 /**
  * @brief Setup the timer to generate the tick interrupts.
  *
@@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                                          xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
     {
         uint32_t ulIndex = 0;
+        uint32_t ulControl = 0x0;
 
         xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
         ulIndex++;
@@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
+        #if ( portHAS_PACBTI_FEATURE == 1 )
+        {
+            /* Check PACBTI security feature configuration before pushing the
+             * CONTROL register's value on task's TCB. */
+            ulControl = prvConfigurePACBTI( pdFALSE );
+        }
+        #endif /* portHAS_PACBTI_FEATURE */
+
         if( xRunPrivileged == pdTRUE )
         {
             xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
-            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+            xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
             ulIndex++;
         }
         else
         {
             xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
-            xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+            xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
             ulIndex++;
         }
 
@@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
+    #if ( portHAS_PACBTI_FEATURE == 1 )
+    {
+        /* Set the CONTROL register value based on PACBTI security feature
+         * configuration before starting the first task. */
+        ( void) prvConfigurePACBTI( pdTRUE );
+    }
+    #endif /* portHAS_PACBTI_FEATURE */
+
     #if ( configENABLE_MPU == 1 )
     {
         /* Setup the Memory Protection Unit (MPU). */
@@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
 
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
+
+#if ( portHAS_PACBTI_FEATURE == 1 )
+
+    static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
+    {
+        uint32_t ulControl = 0x0;
+
+        /* Ensure that PACBTI is implemented. */
+        configASSERT( portID_ISAR5_REG != 0x0 );
+
+        /* Enable UsageFault exception if PAC or BTI is enabled. */
+        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+        {
+            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
+        }
+        #endif
+
+        #if( configENABLE_PAC == 1 )
+        {
+            ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
+        }
+        #endif
+
+        #if( configENABLE_BTI == 1 )
+        {
+            ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
+        }
+        #endif
+
+        if( xWriteControlRegister == pdTRUE )
+        {
+            __asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
+        }
+
+        return ulControl;
+    }
+
+#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
+/*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.s b/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.s
index 44f662646..be06f67ad 100644
--- a/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.s
+++ b/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.s
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -165,8 +167,9 @@ vRestoreContextOfFirstTask:
 
     ldm  r0!, {r1-r2}                       /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
     msr  psplim, r1                         /* Set this task's PSPLIM value. */
-    movs r1, #2                             /* r1 = 2. */
-    msr  CONTROL, r1                        /* Switch to use PSP in the thread mode. */
+    mrs  r1, control                        /* Obtain current control register value. */
+    orrs r1, r1, #2                         /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointe (PSP). */
+    msr control, r1                         /* Write back the new control register value. */
     adds r0, #32                            /* Discard everything up to r0. */
     msr  psp, r0                            /* This is now the new top of stack to use in the task. */
     isb
diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/portmacro.h b/portable/IAR/ARM_CM85_NTZ/non_secure/portmacro.h
index ff5c9895d..c88adc77c 100644
--- a/portable/IAR/ARM_CM85_NTZ/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM85_NTZ/non_secure/portmacro.h
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -56,6 +58,7 @@
 #define portARCH_NAME                    "Cortex-M85"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
 #define portARMV8M_MINOR_VERSION         1
+#define portHAS_PACBTI_FEATURE           1
 #define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 

From 7215c89aa81501f60af8df68dfa99fc2c118a293 Mon Sep 17 00:00:00 2001
From: Paul Hollinsky <paulhollinsky@gmail.com>
Date: Wed, 23 Oct 2024 23:42:27 -0700
Subject: [PATCH 337/424] POSIX Port: Remove pthread_attr_setstacksize call
 (#1161)

We have removed the use of pthread_attr_setstack and as a result,
the task stack is no longer used as the corresponding pthread's stack.
There is no use of calling pthread_attr_setstacksize as the default is
always good enough and we don't need to handle OS specific cases.

This PR simplifies the code by removing the call to pthread_attr_setstacksize.

Signed-off-by: Paul Hollinsky <paulhollinsky@gmail.com>
---
 portable/ThirdParty/GCC/Posix/port.c | 19 ++-----------------
 1 file changed, 2 insertions(+), 17 deletions(-)

diff --git a/portable/ThirdParty/GCC/Posix/port.c b/portable/ThirdParty/GCC/Posix/port.c
index 94e80cc4d..b11e9017f 100644
--- a/portable/ThirdParty/GCC/Posix/port.c
+++ b/portable/ThirdParty/GCC/Posix/port.c
@@ -165,30 +165,15 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
     thread = ( Thread_t * ) ( pxTopOfStack + 1 ) - 1;
     pxTopOfStack = ( StackType_t * ) thread - 1;
 
-    #ifdef __APPLE__
-        pxEndOfStack = ( StackType_t * ) mach_vm_round_page( pxEndOfStack );
-    #endif
-
+    /* Ensure that there is enough space to store Thread_t on the stack. */
     ulStackSize = ( size_t ) ( pxTopOfStack + 1 - pxEndOfStack ) * sizeof( *pxTopOfStack );
-
-    #ifdef __APPLE__
-        ulStackSize = mach_vm_trunc_page( ulStackSize );
-    #endif
+    configASSERT( ulStackSize > sizeof( Thread_t ) );
 
     thread->pxCode = pxCode;
     thread->pvParams = pvParameters;
     thread->xDying = pdFALSE;
 
-    /* Ensure ulStackSize is at least PTHREAD_STACK_MIN */
-    ulStackSize = (ulStackSize < ( size_t ) ( PTHREAD_STACK_MIN ) ) ? ( size_t ) ( PTHREAD_STACK_MIN ) : ulStackSize;
-
     pthread_attr_init( &xThreadAttributes );
-    iRet = pthread_attr_setstacksize( &xThreadAttributes, ulStackSize );
-
-    if( iRet != 0 )
-    {
-        fprintf( stderr, "[WARN] pthread_attr_setstacksize failed with return value: %d. Default stack size will be used.\n", iRet );
-    }
 
     thread->ev = event_create();
 

From c0585ad814c972f58abe279b98828d6c25b772d1 Mon Sep 17 00:00:00 2001
From: Ahmed Ismail <64546783+AhmedIsmail02@users.noreply.github.com>
Date: Fri, 25 Oct 2024 23:33:33 +0100
Subject: [PATCH 338/424] freertos-config: Fix library definitions scope
 (#1164)

Since `freertos_config` is an interface library,
`INTERFACE` scope shall be used to define compile
definitions.

Signed-off-by: Ahmed Ismail <Ahmed.Ismail@arm.com>
---
 portable/CMakeLists.txt | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/portable/CMakeLists.txt b/portable/CMakeLists.txt
index 4c39c76bf..f761ebc47 100644
--- a/portable/CMakeLists.txt
+++ b/portable/CMakeLists.txt
@@ -804,7 +804,7 @@ if (DEFINED FREERTOS_ARM_V_8_1_M_PACBTI_CONFIG )
                         -mbranch-protection=bti+pac-ret+leaf
                 )
                 target_compile_definitions(freertos_config
-                    PUBLIC
+                    INTERFACE
                         configENABLE_PAC=1
                         configENABLE_BTI=1
                 )
@@ -815,7 +815,7 @@ if (DEFINED FREERTOS_ARM_V_8_1_M_PACBTI_CONFIG )
             target_compile_options(freertos_kernel_port PUBLIC $<$<STREQUAL:${CMAKE_C_COMPILER_ID},ARMClang>:-mbranch-protection=pac-ret>)
             target_compile_options(freertos_kernel_port PUBLIC $<$<STREQUAL:${CMAKE_C_COMPILER_ID},IAR>:$<$<COMPILE_LANGUAGE:C,CXX>:--branch_protection=pac-ret>>)
             target_compile_definitions(freertos_config
-                PUBLIC
+                INTERFACE
                     configENABLE_PAC=1
             )
         elseif(FREERTOS_ARM_V_8_1_M_PACBTI_CONFIG STREQUAL "ARM_V_8_1_M_PACBTI_CONFIG_PACRET_LEAF")
@@ -825,7 +825,7 @@ if (DEFINED FREERTOS_ARM_V_8_1_M_PACBTI_CONFIG )
                         -mbranch-protection=pac-ret+leaf
                 )
                 target_compile_definitions(freertos_config
-                    PUBLIC
+                    INTERFACE
                         configENABLE_PAC=1
                 )
             elseif(${CMAKE_C_COMPILER_ID} STREQUAL "IAR")
@@ -835,7 +835,7 @@ if (DEFINED FREERTOS_ARM_V_8_1_M_PACBTI_CONFIG )
             target_compile_options(freertos_kernel_port PUBLIC $<$<STREQUAL:${CMAKE_C_COMPILER_ID},ARMClang>:-mbranch-protection=bti>)
             target_compile_options(freertos_kernel_port PUBLIC $<$<STREQUAL:${CMAKE_C_COMPILER_ID},IAR>:$<$<COMPILE_LANGUAGE:C,CXX>:--branch_protection=bti>>)
             target_compile_definitions(freertos_config
-                PUBLIC
+                INTERFACE
                     configENABLE_BTI=1
             )
         elseif(FREERTOS_ARM_V_8_1_M_PACBTI_CONFIG STREQUAL "ARM_V_8_1_M_PACBTI_CONFIG_NONE")
@@ -846,7 +846,7 @@ if (DEFINED FREERTOS_ARM_V_8_1_M_PACBTI_CONFIG )
                 )
             endif()
             target_compile_definitions(freertos_config
-                PUBLIC
+                INTERFACE
                     configENABLE_PAC=0
                     configENABLE_BTI=0
             )

From 8225a7f554a1c7c76f6f179bac37d32e47f40125 Mon Sep 17 00:00:00 2001
From: Kody Stribrny <89810515+kstribrnAmzn@users.noreply.github.com>
Date: Thu, 31 Oct 2024 09:03:25 -0700
Subject: [PATCH 339/424] Fix AutoReload variable name (#1166)

Removes the 'u' prefix as the variable is no longer unsigned.
---
 include/mpu_prototypes.h                                      | 2 +-
 .../non_secure/portable/GCC/ARM_CM23/mpu_wrappers_v2_asm.c    | 4 ++--
 .../portable/GCC/ARM_CM23_NTZ/mpu_wrappers_v2_asm.c           | 4 ++--
 .../non_secure/portable/GCC/ARM_CM33/mpu_wrappers_v2_asm.c    | 4 ++--
 .../portable/GCC/ARM_CM33_NTZ/mpu_wrappers_v2_asm.c           | 4 ++--
 portable/Common/mpu_wrappers.c                                | 2 +-
 portable/GCC/ARM_CM0/mpu_wrappers_v2_asm.c                    | 4 ++--
 portable/GCC/ARM_CM23/non_secure/mpu_wrappers_v2_asm.c        | 4 ++--
 portable/GCC/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.c    | 4 ++--
 portable/GCC/ARM_CM33/non_secure/mpu_wrappers_v2_asm.c        | 4 ++--
 portable/GCC/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.c    | 4 ++--
 portable/GCC/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.c       | 4 ++--
 portable/GCC/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.c   | 4 ++--
 portable/GCC/ARM_CM3_MPU/mpu_wrappers_v2_asm.c                | 4 ++--
 portable/GCC/ARM_CM4_MPU/mpu_wrappers_v2_asm.c                | 4 ++--
 portable/GCC/ARM_CM55/non_secure/mpu_wrappers_v2_asm.c        | 4 ++--
 portable/GCC/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.c    | 4 ++--
 portable/GCC/ARM_CM85/non_secure/mpu_wrappers_v2_asm.c        | 4 ++--
 portable/GCC/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.c    | 4 ++--
 portable/RVDS/ARM_CM4_MPU/mpu_wrappers_v2_asm.c               | 4 ++--
 20 files changed, 38 insertions(+), 38 deletions(-)

diff --git a/include/mpu_prototypes.h b/include/mpu_prototypes.h
index cacadc6c6..ea2dd9f75 100644
--- a/include/mpu_prototypes.h
+++ b/include/mpu_prototypes.h
@@ -335,7 +335,7 @@ BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
 BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) FREERTOS_SYSTEM_CALL;
 const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
 void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                              const BaseType_t uxAutoReload ) FREERTOS_SYSTEM_CALL;
+                              const BaseType_t xAutoReload ) FREERTOS_SYSTEM_CALL;
 BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
 UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
 TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/mpu_wrappers_v2_asm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/mpu_wrappers_v2_asm.c
index 1fb67891d..7a62caff0 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/mpu_wrappers_v2_asm.c
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/mpu_wrappers_v2_asm.c
@@ -1546,10 +1546,10 @@
     #if ( configUSE_TIMERS == 1 )
 
         void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                                      const BaseType_t uxAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+                                      const BaseType_t xAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
         void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                                      const BaseType_t uxAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+                                      const BaseType_t xAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/mpu_wrappers_v2_asm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/mpu_wrappers_v2_asm.c
index 1fb67891d..7a62caff0 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/mpu_wrappers_v2_asm.c
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/mpu_wrappers_v2_asm.c
@@ -1546,10 +1546,10 @@
     #if ( configUSE_TIMERS == 1 )
 
         void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                                      const BaseType_t uxAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+                                      const BaseType_t xAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
         void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                                      const BaseType_t uxAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+                                      const BaseType_t xAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/mpu_wrappers_v2_asm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/mpu_wrappers_v2_asm.c
index 02229d964..33410a0c3 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/mpu_wrappers_v2_asm.c
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/mpu_wrappers_v2_asm.c
@@ -1495,10 +1495,10 @@
     #if ( configUSE_TIMERS == 1 )
 
         void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                                      const BaseType_t uxAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+                                      const BaseType_t xAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
         void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                                      const BaseType_t uxAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+                                      const BaseType_t xAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/mpu_wrappers_v2_asm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/mpu_wrappers_v2_asm.c
index 6642c9e20..4b984932d 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/mpu_wrappers_v2_asm.c
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/mpu_wrappers_v2_asm.c
@@ -1495,10 +1495,10 @@
     #if ( configUSE_TIMERS == 1 )
 
         void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                                      const BaseType_t uxAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+                                      const BaseType_t xAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
         void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                                      const BaseType_t uxAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+                                      const BaseType_t xAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
diff --git a/portable/Common/mpu_wrappers.c b/portable/Common/mpu_wrappers.c
index e9a890585..ab2a74bd2 100644
--- a/portable/Common/mpu_wrappers.c
+++ b/portable/Common/mpu_wrappers.c
@@ -1799,7 +1799,7 @@
 
     #if ( configUSE_TIMERS == 1 )
         void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                                      const BaseType_t uxAutoReload ) /* FREERTOS_SYSTEM_CALL */
+                                      const BaseType_t xAutoReload ) /* FREERTOS_SYSTEM_CALL */
         {
             if( portIS_PRIVILEGED() == pdFALSE )
             {
diff --git a/portable/GCC/ARM_CM0/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM0/mpu_wrappers_v2_asm.c
index cd7be632b..4f14482e2 100644
--- a/portable/GCC/ARM_CM0/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM0/mpu_wrappers_v2_asm.c
@@ -1648,10 +1648,10 @@
     #if ( configUSE_TIMERS == 1 )
 
         void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                                      const BaseType_t uxAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+                                      const BaseType_t xAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
         void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                                      const BaseType_t uxAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+                                      const BaseType_t xAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
diff --git a/portable/GCC/ARM_CM23/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM23/non_secure/mpu_wrappers_v2_asm.c
index 1fb67891d..7a62caff0 100644
--- a/portable/GCC/ARM_CM23/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM23/non_secure/mpu_wrappers_v2_asm.c
@@ -1546,10 +1546,10 @@
     #if ( configUSE_TIMERS == 1 )
 
         void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                                      const BaseType_t uxAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+                                      const BaseType_t xAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
         void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                                      const BaseType_t uxAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+                                      const BaseType_t xAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.c
index 1fb67891d..7a62caff0 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.c
@@ -1546,10 +1546,10 @@
     #if ( configUSE_TIMERS == 1 )
 
         void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                                      const BaseType_t uxAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+                                      const BaseType_t xAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
         void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                                      const BaseType_t uxAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+                                      const BaseType_t xAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
diff --git a/portable/GCC/ARM_CM33/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM33/non_secure/mpu_wrappers_v2_asm.c
index 02229d964..33410a0c3 100644
--- a/portable/GCC/ARM_CM33/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM33/non_secure/mpu_wrappers_v2_asm.c
@@ -1495,10 +1495,10 @@
     #if ( configUSE_TIMERS == 1 )
 
         void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                                      const BaseType_t uxAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+                                      const BaseType_t xAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
         void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                                      const BaseType_t uxAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+                                      const BaseType_t xAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.c
index 6642c9e20..4b984932d 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.c
@@ -1495,10 +1495,10 @@
     #if ( configUSE_TIMERS == 1 )
 
         void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                                      const BaseType_t uxAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+                                      const BaseType_t xAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
         void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                                      const BaseType_t uxAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+                                      const BaseType_t xAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
diff --git a/portable/GCC/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.c
index 02229d964..33410a0c3 100644
--- a/portable/GCC/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.c
@@ -1495,10 +1495,10 @@
     #if ( configUSE_TIMERS == 1 )
 
         void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                                      const BaseType_t uxAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+                                      const BaseType_t xAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
         void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                                      const BaseType_t uxAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+                                      const BaseType_t xAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.c
index 6642c9e20..4b984932d 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.c
@@ -1495,10 +1495,10 @@
     #if ( configUSE_TIMERS == 1 )
 
         void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                                      const BaseType_t uxAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+                                      const BaseType_t xAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
         void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                                      const BaseType_t uxAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+                                      const BaseType_t xAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
diff --git a/portable/GCC/ARM_CM3_MPU/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM3_MPU/mpu_wrappers_v2_asm.c
index 71bb6602e..428e6e84a 100644
--- a/portable/GCC/ARM_CM3_MPU/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM3_MPU/mpu_wrappers_v2_asm.c
@@ -1495,10 +1495,10 @@
     #if ( configUSE_TIMERS == 1 )
 
         void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                                      const BaseType_t uxAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+                                      const BaseType_t xAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
         void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                                      const BaseType_t uxAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+                                      const BaseType_t xAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
diff --git a/portable/GCC/ARM_CM4_MPU/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM4_MPU/mpu_wrappers_v2_asm.c
index 71bb6602e..428e6e84a 100644
--- a/portable/GCC/ARM_CM4_MPU/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM4_MPU/mpu_wrappers_v2_asm.c
@@ -1495,10 +1495,10 @@
     #if ( configUSE_TIMERS == 1 )
 
         void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                                      const BaseType_t uxAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+                                      const BaseType_t xAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
         void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                                      const BaseType_t uxAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+                                      const BaseType_t xAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
diff --git a/portable/GCC/ARM_CM55/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM55/non_secure/mpu_wrappers_v2_asm.c
index 02229d964..33410a0c3 100644
--- a/portable/GCC/ARM_CM55/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM55/non_secure/mpu_wrappers_v2_asm.c
@@ -1495,10 +1495,10 @@
     #if ( configUSE_TIMERS == 1 )
 
         void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                                      const BaseType_t uxAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+                                      const BaseType_t xAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
         void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                                      const BaseType_t uxAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+                                      const BaseType_t xAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.c
index 6642c9e20..4b984932d 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.c
@@ -1495,10 +1495,10 @@
     #if ( configUSE_TIMERS == 1 )
 
         void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                                      const BaseType_t uxAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+                                      const BaseType_t xAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
         void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                                      const BaseType_t uxAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+                                      const BaseType_t xAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
diff --git a/portable/GCC/ARM_CM85/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM85/non_secure/mpu_wrappers_v2_asm.c
index 02229d964..33410a0c3 100644
--- a/portable/GCC/ARM_CM85/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM85/non_secure/mpu_wrappers_v2_asm.c
@@ -1495,10 +1495,10 @@
     #if ( configUSE_TIMERS == 1 )
 
         void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                                      const BaseType_t uxAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+                                      const BaseType_t xAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
         void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                                      const BaseType_t uxAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+                                      const BaseType_t xAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.c
index 6642c9e20..4b984932d 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.c
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.c
@@ -1495,10 +1495,10 @@
     #if ( configUSE_TIMERS == 1 )
 
         void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                                      const BaseType_t uxAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+                                      const BaseType_t xAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
 
         void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                                      const BaseType_t uxAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+                                      const BaseType_t xAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
         {
             __asm volatile
             (
diff --git a/portable/RVDS/ARM_CM4_MPU/mpu_wrappers_v2_asm.c b/portable/RVDS/ARM_CM4_MPU/mpu_wrappers_v2_asm.c
index 82dd5f40d..950788e09 100644
--- a/portable/RVDS/ARM_CM4_MPU/mpu_wrappers_v2_asm.c
+++ b/portable/RVDS/ARM_CM4_MPU/mpu_wrappers_v2_asm.c
@@ -1240,10 +1240,10 @@ MPU_pcTimerGetName_Unpriv
 #if ( configUSE_TIMERS == 1 )
 
 void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                              const BaseType_t uxAutoReload ) FREERTOS_SYSTEM_CALL;
+                              const BaseType_t xAutoReload ) FREERTOS_SYSTEM_CALL;
 
 __asm void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                                    const BaseType_t uxAutoReload ) /* FREERTOS_SYSTEM_CALL */
+                                    const BaseType_t xAutoReload ) /* FREERTOS_SYSTEM_CALL */
 {
     PRESERVE8
     extern MPU_vTimerSetReloadModeImpl

From de276eb02397ced5c55f40eea8b8602af3c98a34 Mon Sep 17 00:00:00 2001
From: ActoryOu <jay2002824@gmail.com>
Date: Sat, 2 Nov 2024 01:09:49 +0800
Subject: [PATCH 340/424] Fix spelling typos (#1168)

* Fix spelling

---------

Co-authored-by: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
---
 History.txt                                      |  8 ++++----
 examples/coverity/README.md                      |  2 +-
 examples/template_configuration/FreeRTOSConfig.h |  2 +-
 include/task.h                                   |  2 +-
 portable/ARMv8M/non_secure/port.c                |  2 +-
 .../non_secure/portable/GCC/ARM_CM33/portasm.c   |  6 +++---
 .../portable/GCC/ARM_CM33_NTZ/portasm.c          |  6 +++---
 .../non_secure/portable/IAR/ARM_CM33/portasm.s   |  6 +++---
 .../portable/IAR/ARM_CM33_NTZ/portasm.s          |  6 +++---
 portable/ARMv8M/non_secure/portasm.h             |  2 +-
 portable/ARMv8M/non_secure/portmacrocommon.h     |  2 +-
 portable/ARMv8M/secure/context/secure_context.c  |  2 +-
 portable/GCC/ARM7_AT91SAM7S/AT91SAM7X256.h       |  8 ++++----
 portable/GCC/ARM7_AT91SAM7S/ioat91sam7x256.h     | 14 +++++++-------
 portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.h   |  8 ++++----
 portable/GCC/ARM_AARCH64/port.c                  |  2 +-
 portable/GCC/ARM_CA9/port.c                      |  2 +-
 portable/GCC/ARM_CM0/portasm.h                   |  2 +-
 portable/GCC/ARM_CM23/non_secure/port.c          |  2 +-
 portable/GCC/ARM_CM23/non_secure/portasm.h       |  2 +-
 .../GCC/ARM_CM23/non_secure/portmacrocommon.h    |  2 +-
 portable/GCC/ARM_CM23/secure/secure_context.c    |  2 +-
 portable/GCC/ARM_CM23_NTZ/non_secure/port.c      |  2 +-
 portable/GCC/ARM_CM23_NTZ/non_secure/portasm.h   |  2 +-
 .../ARM_CM23_NTZ/non_secure/portmacrocommon.h    |  2 +-
 portable/GCC/ARM_CM33/non_secure/port.c          |  2 +-
 portable/GCC/ARM_CM33/non_secure/portasm.c       |  6 +++---
 portable/GCC/ARM_CM33/non_secure/portasm.h       |  2 +-
 .../GCC/ARM_CM33/non_secure/portmacrocommon.h    |  2 +-
 portable/GCC/ARM_CM33/secure/secure_context.c    |  2 +-
 portable/GCC/ARM_CM33_NTZ/non_secure/port.c      |  2 +-
 portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c   |  6 +++---
 portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h   |  2 +-
 .../ARM_CM33_NTZ/non_secure/portmacrocommon.h    |  2 +-
 portable/GCC/ARM_CM35P/non_secure/port.c         |  2 +-
 portable/GCC/ARM_CM35P/non_secure/portasm.c      |  6 +++---
 portable/GCC/ARM_CM35P/non_secure/portasm.h      |  2 +-
 .../GCC/ARM_CM35P/non_secure/portmacrocommon.h   |  2 +-
 portable/GCC/ARM_CM35P/secure/secure_context.c   |  2 +-
 portable/GCC/ARM_CM35P_NTZ/non_secure/port.c     |  2 +-
 portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.c  |  6 +++---
 portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.h  |  2 +-
 .../ARM_CM35P_NTZ/non_secure/portmacrocommon.h   |  2 +-
 portable/GCC/ARM_CM4_MPU/portmacro.h             |  2 +-
 portable/GCC/ARM_CM55/non_secure/port.c          |  2 +-
 portable/GCC/ARM_CM55/non_secure/portasm.c       |  6 +++---
 portable/GCC/ARM_CM55/non_secure/portasm.h       |  2 +-
 .../GCC/ARM_CM55/non_secure/portmacrocommon.h    |  2 +-
 portable/GCC/ARM_CM55/secure/secure_context.c    |  2 +-
 portable/GCC/ARM_CM55_NTZ/non_secure/port.c      |  2 +-
 portable/GCC/ARM_CM55_NTZ/non_secure/portasm.c   |  6 +++---
 portable/GCC/ARM_CM55_NTZ/non_secure/portasm.h   |  2 +-
 .../ARM_CM55_NTZ/non_secure/portmacrocommon.h    |  2 +-
 portable/GCC/ARM_CM85/non_secure/port.c          |  2 +-
 portable/GCC/ARM_CM85/non_secure/portasm.c       |  6 +++---
 portable/GCC/ARM_CM85/non_secure/portasm.h       |  2 +-
 .../GCC/ARM_CM85/non_secure/portmacrocommon.h    |  2 +-
 portable/GCC/ARM_CM85/secure/secure_context.c    |  2 +-
 portable/GCC/ARM_CM85_NTZ/non_secure/port.c      |  2 +-
 portable/GCC/ARM_CM85_NTZ/non_secure/portasm.c   |  6 +++---
 portable/GCC/ARM_CM85_NTZ/non_secure/portasm.h   |  2 +-
 .../ARM_CM85_NTZ/non_secure/portmacrocommon.h    |  2 +-
 portable/GCC/ARM_CRx_MPU/port.c                  |  2 +-
 portable/GCC/ARM_CRx_MPU/portmacro.h             |  4 ++--
 portable/GCC/ARM_CRx_MPU/portmacro_asm.h         |  2 +-
 portable/GCC/AVR32_UC3/port.c                    |  2 +-
 portable/IAR/ARM_CA9/port.c                      |  2 +-
 portable/IAR/ARM_CM23/non_secure/port.c          |  2 +-
 portable/IAR/ARM_CM23/non_secure/portasm.h       |  2 +-
 .../IAR/ARM_CM23/non_secure/portmacrocommon.h    |  2 +-
 portable/IAR/ARM_CM23/secure/secure_context.c    |  2 +-
 portable/IAR/ARM_CM23_NTZ/non_secure/port.c      |  2 +-
 portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h   |  2 +-
 .../ARM_CM23_NTZ/non_secure/portmacrocommon.h    |  2 +-
 portable/IAR/ARM_CM33/non_secure/port.c          |  2 +-
 portable/IAR/ARM_CM33/non_secure/portasm.h       |  2 +-
 portable/IAR/ARM_CM33/non_secure/portasm.s       |  6 +++---
 .../IAR/ARM_CM33/non_secure/portmacrocommon.h    |  2 +-
 portable/IAR/ARM_CM33/secure/secure_context.c    |  2 +-
 portable/IAR/ARM_CM33_NTZ/non_secure/port.c      |  2 +-
 portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h   |  2 +-
 portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s   |  6 +++---
 .../ARM_CM33_NTZ/non_secure/portmacrocommon.h    |  2 +-
 portable/IAR/ARM_CM35P/non_secure/port.c         |  2 +-
 portable/IAR/ARM_CM35P/non_secure/portasm.h      |  2 +-
 portable/IAR/ARM_CM35P/non_secure/portasm.s      |  6 +++---
 .../IAR/ARM_CM35P/non_secure/portmacrocommon.h   |  2 +-
 portable/IAR/ARM_CM35P/secure/secure_context.c   |  2 +-
 portable/IAR/ARM_CM35P_NTZ/non_secure/port.c     |  2 +-
 portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.h  |  2 +-
 portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.s  |  6 +++---
 .../ARM_CM35P_NTZ/non_secure/portmacrocommon.h   |  2 +-
 portable/IAR/ARM_CM4F_MPU/portmacro.h            |  2 +-
 portable/IAR/ARM_CM55/non_secure/port.c          |  2 +-
 portable/IAR/ARM_CM55/non_secure/portasm.h       |  2 +-
 portable/IAR/ARM_CM55/non_secure/portasm.s       |  6 +++---
 .../IAR/ARM_CM55/non_secure/portmacrocommon.h    |  2 +-
 portable/IAR/ARM_CM55/secure/secure_context.c    |  2 +-
 portable/IAR/ARM_CM55_NTZ/non_secure/port.c      |  2 +-
 portable/IAR/ARM_CM55_NTZ/non_secure/portasm.h   |  2 +-
 portable/IAR/ARM_CM55_NTZ/non_secure/portasm.s   |  6 +++---
 .../ARM_CM55_NTZ/non_secure/portmacrocommon.h    |  2 +-
 portable/IAR/ARM_CM85/non_secure/port.c          |  2 +-
 portable/IAR/ARM_CM85/non_secure/portasm.h       |  2 +-
 portable/IAR/ARM_CM85/non_secure/portasm.s       |  6 +++---
 .../IAR/ARM_CM85/non_secure/portmacrocommon.h    |  2 +-
 portable/IAR/ARM_CM85/secure/secure_context.c    |  2 +-
 portable/IAR/ARM_CM85_NTZ/non_secure/port.c      |  2 +-
 portable/IAR/ARM_CM85_NTZ/non_secure/portasm.h   |  2 +-
 portable/IAR/ARM_CM85_NTZ/non_secure/portasm.s   |  6 +++---
 .../ARM_CM85_NTZ/non_secure/portmacrocommon.h    |  2 +-
 portable/IAR/AVR32_UC3/port.c                    |  2 +-
 portable/IAR/AtmelSAM7S64/AT91SAM7S64.h          |  4 ++--
 portable/IAR/AtmelSAM7S64/AT91SAM7S64_inc.h      |  4 ++--
 portable/IAR/AtmelSAM7S64/AT91SAM7X128.h         |  8 ++++----
 portable/IAR/AtmelSAM7S64/AT91SAM7X128_inc.h     |  8 ++++----
 portable/IAR/AtmelSAM7S64/AT91SAM7X256.h         |  8 ++++----
 portable/IAR/AtmelSAM7S64/AT91SAM7X256_inc.h     |  8 ++++----
 portable/IAR/AtmelSAM7S64/lib_AT91SAM7S64.h      | 16 ++++++++--------
 portable/IAR/AtmelSAM7S64/lib_AT91SAM7X128.h     | 10 +++++-----
 portable/IAR/AtmelSAM7S64/lib_AT91SAM7X256.h     | 10 +++++-----
 portable/MPLAB/PIC24_dsPIC/port.c                |  2 +-
 portable/RVDS/ARM_CA9/port.c                     |  2 +-
 portable/RVDS/ARM_CM4_MPU/portmacro.h            |  2 +-
 portable/ThirdParty/GCC/ARC_EM_HS/port.c         |  2 +-
 portable/ThirdParty/GCC/ARC_v1/port.c            |  2 +-
 portable/ThirdParty/GCC/Posix/port.c             |  2 +-
 portable/ThirdParty/GCC/Posix/portmacro.h        |  2 +-
 .../ThirdParty/GCC/RP2040/include/portmacro.h    |  2 +-
 .../Xtensa_ESP32/include/FreeRTOSConfig_arch.h   |  2 +-
 portable/WizC/PIC18/portmacro.h                  |  2 +-
 portable/oWatcom/16BitDOS/common/portasm.h       |  2 +-
 queue.c                                          |  2 +-
 133 files changed, 218 insertions(+), 218 deletions(-)

diff --git a/History.txt b/History.txt
index d5293b90b..ae29ae9c9 100644
--- a/History.txt
+++ b/History.txt
@@ -528,7 +528,7 @@ Changes between FreeRTOS V10.4.3 and FreeRTOS V10.4.4 released May 28 2021
 	  in more files.
 	+ Other minor updates include adding additional configASSERT() checks and
 	  correcting and improving code comments.
-	+ Go look at the smp branch to see the progress towards the Symetric
+	+ Go look at the smp branch to see the progress towards the Symmetric
 	  Multiprocessing Kernel. https://github.com/FreeRTOS/FreeRTOS-Kernel/tree/smp
 
 Changes between FreeRTOS V10.4.2 and FreeRTOS V10.4.3 released December 14 2020
@@ -2015,7 +2015,7 @@ Changes between V6.1.0 and V6.1.1 released January 14 2011
 	  Embedded Workbench.
 	+ Added a new port for the MSP430X core using the IAR Embedded Workbench.
 	+ Updated all the RX62N demo projects that target the Renesas Demonstration
-	  Kit (RDK) to take into account the revered LED wiring on later hardware
+	  Kit (RDK) to take into account the reversed LED wiring on later hardware
 	  revisions, and the new J-Link debug interface DLL.
 	+ Updated all the RX62N demo projects so the IO page served by the example
 	  embedded web server works with all web browsers.
@@ -3174,7 +3174,7 @@ Changes between V1.2.3 and V1.2.4
 	  xSerialPortInitMinimal() and the function xPortInit() has been renamed
 	  to xSerialPortInit().
 	+ The function sSerialPutChar() has been renamed cSerialPutChar() and
-	  the function return type chaned to portCHAR.
+	  the function return type changed to portCHAR.
 	+ The integer and flop tasks now include calls to tskYIELD(), allowing
 	  them to be used with the cooperative scheduler.
 	+ All the demo applications now use the integer and comtest tasks when the
@@ -3308,7 +3308,7 @@ Changes between V1.01 and V1.2.0
 	  ports to allocate a different maximum number of priorities.
 	+ By default the trace facility is off, previously USE_TRACE_FACILITY
 	  was defined.
-	+ comtest.c now uses a psuedo random delay between sends.  This allows for
+	+ comtest.c now uses a pseudo random delay between sends.  This allows for
 	  better testing as the interrupts do not arrive at regular intervals.
 	+ Minor change to the Flashlite serial port driver.  The driver is written
 	  to demonstrate the scheduler and is not written to be efficient.
diff --git a/examples/coverity/README.md b/examples/coverity/README.md
index 688577d37..60df69343 100644
--- a/examples/coverity/README.md
+++ b/examples/coverity/README.md
@@ -35,7 +35,7 @@ commands in a terminal:
   ~~~
 2. Create the build files using CMake in a `build` directory:
 
-Singe core FreeRTOS:
+Single core FreeRTOS:
   ~~~
   cmake -B build -S examples/coverity
   ~~~
diff --git a/examples/template_configuration/FreeRTOSConfig.h b/examples/template_configuration/FreeRTOSConfig.h
index fe21f1108..8c5e53066 100644
--- a/examples/template_configuration/FreeRTOSConfig.h
+++ b/examples/template_configuration/FreeRTOSConfig.h
@@ -643,7 +643,7 @@
  * contain the most recent error for that task. */
 #define configUSE_POSIX_ERRNO                  0
 
-/* Set the following INCLUDE_* constants to 1 to incldue the named API function,
+/* Set the following INCLUDE_* constants to 1 to include the named API function,
  * or 0 to exclude the named API function.  Most linkers will remove unused
  * functions even when the constant is 1. */
 #define INCLUDE_vTaskPrioritySet               1
diff --git a/include/task.h b/include/task.h
index 60535254c..0414eb9e2 100644
--- a/include/task.h
+++ b/include/task.h
@@ -2372,7 +2372,7 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION;
  *
  * WARN: This function assumes that the pcWriteBuffer is of length
  * configSTATS_BUFFER_MAX_LENGTH. This function is there only for
- * backward compatiblity. New applications are recommended to use
+ * backward compatibility. New applications are recommended to use
  * vTaskGetRunTimeStatistics and supply the length of the pcWriteBuffer
  * explicitly.
  *
diff --git a/portable/ARMv8M/non_secure/port.c b/portable/ARMv8M/non_secure/port.c
index 5b399358e..a33dfa43c 100644
--- a/portable/ARMv8M/non_secure/port.c
+++ b/portable/ARMv8M/non_secure/port.c
@@ -56,7 +56,7 @@
  * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
  * i.e. the processor boots as secure and never jumps to the non-secure side.
  * The Trust Zone support in the port must be disabled in order to run FreeRTOS
- * on the secure side. The following are the valid configuration seetings:
+ * on the secure side. The following are the valid configuration settings:
  *
  * 1. Run FreeRTOS on the Secure Side:
  *    configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c
index f09840a46..aaeccaa35 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c
@@ -227,7 +227,7 @@ uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCT
         "                                                   \n"
         "   mrs r0, basepri                                 \n" /* r0 = basepri. Return original basepri value. */
         "   mov r1, %0                                      \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        "   msr basepri, r1                                 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        "   msr basepri, r1                                 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
         "   dsb                                             \n"
         "   isb                                             \n"
         "   bx lr                                           \n" /* Return. */
@@ -304,7 +304,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "                                                 \n"
             " select_next_task:                               \n"
             "    mov r0, %0                                   \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
-            "    msr basepri, r0                              \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+            "    msr basepri, r0                              \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
             "    dsb                                          \n"
             "    isb                                          \n"
             "    bl vTaskSwitchContext                        \n"
@@ -447,7 +447,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "                                                   \n"
             " select_next_task:                                 \n"
             "   mov r0, %0                                      \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
-            "   msr basepri, r0                                 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+            "   msr basepri, r0                                 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
             "   dsb                                             \n"
             "   isb                                             \n"
             "   bl vTaskSwitchContext                           \n"
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c
index 47996cd9e..7cdff7005 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c
@@ -223,7 +223,7 @@ uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCT
         "                                                   \n"
         "   mrs r0, basepri                                 \n" /* r0 = basepri. Return original basepri value. */
         "   mov r1, %0                                      \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        "   msr basepri, r1                                 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        "   msr basepri, r1                                 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
         "   dsb                                             \n"
         "   isb                                             \n"
         "   bx lr                                           \n" /* Return. */
@@ -283,7 +283,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "                                                 \n"
             " select_next_task:                               \n"
             "    mov r0, %0                                   \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
-            "    msr basepri, r0                              \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+            "    msr basepri, r0                              \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
             "    dsb                                          \n"
             "    isb                                          \n"
             "    bl vTaskSwitchContext                        \n"
@@ -386,7 +386,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   str r0, [r1]                                    \n" /* Save the new top of stack in TCB. */
             "                                                   \n"
             "   mov r0, %0                                      \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
-            "   msr basepri, r0                                 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+            "   msr basepri, r0                                 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
             "   dsb                                             \n"
             "   isb                                             \n"
             "   bl vTaskSwitchContext                           \n"
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s
index f4b7ab20f..212688d61 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s
@@ -216,7 +216,7 @@ vStartFirstTask:
 ulSetInterruptMask:
     mrs r0, basepri                         /* r0 = basepri. Return original basepri value. */
     mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY
-    msr basepri, r1                         /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+    msr basepri, r1                         /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
     dsb
     isb
     bx lr                                   /* Return. */
@@ -275,7 +275,7 @@ PendSV_Handler:
 
     select_next_task:
         mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
-        msr basepri, r0                     /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        msr basepri, r0                     /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
         dsb
         isb
         bl vTaskSwitchContext
@@ -409,7 +409,7 @@ PendSV_Handler:
 
     select_next_task:
         mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
-        msr basepri, r0                     /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        msr basepri, r0                     /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
         dsb
         isb
         bl vTaskSwitchContext
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s
index be06f67ad..9d6c6a7ef 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s
@@ -202,7 +202,7 @@ vStartFirstTask:
 ulSetInterruptMask:
     mrs r0, basepri                         /* r0 = basepri. Return original basepri value. */
     mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY
-    msr basepri, r1                         /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+    msr basepri, r1                         /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
     dsb
     isb
     bx lr                                   /* Return. */
@@ -246,7 +246,7 @@ PendSV_Handler:
 
     select_next_task:
         mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
-        msr basepri, r0                     /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        msr basepri, r0                     /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
         dsb
         isb
         bl vTaskSwitchContext
@@ -340,7 +340,7 @@ PendSV_Handler:
     str r0, [r1]                            /* Save the new top of stack in TCB. */
 
     mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
-    msr basepri, r0                         /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+    msr basepri, r0                         /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
     dsb
     isb
     bl vTaskSwitchContext
diff --git a/portable/ARMv8M/non_secure/portasm.h b/portable/ARMv8M/non_secure/portasm.h
index bd5a2bfca..b7021b024 100644
--- a/portable/ARMv8M/non_secure/portasm.h
+++ b/portable/ARMv8M/non_secure/portasm.h
@@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
  * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
  * register.
  *
- * @note This is a privileged function and should only be called from the kenrel
+ * @note This is a privileged function and should only be called from the kernel
  * code.
  *
  * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
diff --git a/portable/ARMv8M/non_secure/portmacrocommon.h b/portable/ARMv8M/non_secure/portmacrocommon.h
index 3cf65761f..cd83bee57 100644
--- a/portable/ARMv8M/non_secure/portmacrocommon.h
+++ b/portable/ARMv8M/non_secure/portmacrocommon.h
@@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portPRIVILEGE_BIT         ( 0x0UL )
 #endif /* configENABLE_MPU */
 
-/* MPU settings that can be overriden in FreeRTOSConfig.h. */
+/* MPU settings that can be overridden in FreeRTOSConfig.h. */
 #ifndef configTOTAL_MPU_REGIONS
     /* Define to 8 for backward compatibility. */
     #define configTOTAL_MPU_REGIONS    ( 8UL )
diff --git a/portable/ARMv8M/secure/context/secure_context.c b/portable/ARMv8M/secure/context/secure_context.c
index 72fb3862c..3aa335e63 100644
--- a/portable/ARMv8M/secure/context/secure_context.c
+++ b/portable/ARMv8M/secure/context/secure_context.c
@@ -207,7 +207,7 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
      * securecontextNO_STACK when no secure context is loaded. */
     if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) )
     {
-        /* Ontain a free secure context. */
+        /* Obtain a free secure context. */
         ulSecureContextIndex = ulGetSecureContext( pvTaskHandle );
 
         /* Were we able to get a free context? */
diff --git a/portable/GCC/ARM7_AT91SAM7S/AT91SAM7X256.h b/portable/GCC/ARM7_AT91SAM7S/AT91SAM7X256.h
index a335e4ad2..e5aa862e0 100644
--- a/portable/GCC/ARM7_AT91SAM7S/AT91SAM7X256.h
+++ b/portable/GCC/ARM7_AT91SAM7S/AT91SAM7X256.h
@@ -627,8 +627,8 @@ typedef struct _AT91S_MC
 /* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */
 #define AT91C_MC_RCB                       ( ( unsigned int ) 0x1 << 0 )   /* (MC) Remap Command Bit */
 /* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */
-#define AT91C_MC_UNDADD                    ( ( unsigned int ) 0x1 << 0 )   /* (MC) Undefined Addess Abort Status */
-#define AT91C_MC_MISADD                    ( ( unsigned int ) 0x1 << 1 )   /* (MC) Misaligned Addess Abort Status */
+#define AT91C_MC_UNDADD                    ( ( unsigned int ) 0x1 << 0 )   /* (MC) Undefined Address Abort Status */
+#define AT91C_MC_MISADD                    ( ( unsigned int ) 0x1 << 1 )   /* (MC) Misaligned Address Abort Status */
 #define AT91C_MC_ABTSZ                     ( ( unsigned int ) 0x3 << 8 )   /* (MC) Abort Size Status */
 #define     AT91C_MC_ABTSZ_BYTE            ( ( unsigned int ) 0x0 << 8 )   /* (MC) Byte */
 #define     AT91C_MC_ABTSZ_HWORD           ( ( unsigned int ) 0x1 << 8 )   /* (MC) Half-word */
@@ -1509,7 +1509,7 @@ typedef struct _AT91S_EMAC
     AT91_REG EMAC_ECOL;       /* Excessive Collision Register */
     AT91_REG EMAC_TUND;       /* Transmit Underrun Error Register */
     AT91_REG EMAC_CSE;        /* Carrier Sense Error Register */
-    AT91_REG EMAC_RRE;        /* Receive Ressource Error Register */
+    AT91_REG EMAC_RRE;        /* Receive Resource Error Register */
     AT91_REG EMAC_ROV;        /* Receive Overrun Errors Register */
     AT91_REG EMAC_RSE;        /* Receive Symbol Errors Register */
     AT91_REG EMAC_ELE;        /* Excessive Length Errors Register */
@@ -2393,7 +2393,7 @@ typedef struct _AT91S_TDES
 #define AT91C_EMAC_SA1H            ( ( AT91_REG * ) 0xFFFDC09C ) /* (EMAC) Specific Address 1 Top, Last 2 bytes */
 #define AT91C_EMAC_CSE             ( ( AT91_REG * ) 0xFFFDC068 ) /* (EMAC) Carrier Sense Error Register */
 #define AT91C_EMAC_SA3H            ( ( AT91_REG * ) 0xFFFDC0AC ) /* (EMAC) Specific Address 3 Top, Last 2 bytes */
-#define AT91C_EMAC_RRE             ( ( AT91_REG * ) 0xFFFDC06C ) /* (EMAC) Receive Ressource Error Register */
+#define AT91C_EMAC_RRE             ( ( AT91_REG * ) 0xFFFDC06C ) /* (EMAC) Receive Resource Error Register */
 #define AT91C_EMAC_STE             ( ( AT91_REG * ) 0xFFFDC084 ) /* (EMAC) SQE Test Error Register */
 /* ========== Register definition for PDC_ADC peripheral ========== */
 #define AT91C_ADC_PTSR             ( ( AT91_REG * ) 0xFFFD8124 ) /* (PDC_ADC) PDC Transfer Status Register */
diff --git a/portable/GCC/ARM7_AT91SAM7S/ioat91sam7x256.h b/portable/GCC/ARM7_AT91SAM7S/ioat91sam7x256.h
index a680c4861..a148b18a6 100644
--- a/portable/GCC/ARM7_AT91SAM7S/ioat91sam7x256.h
+++ b/portable/GCC/ARM7_AT91SAM7S/ioat91sam7x256.h
@@ -627,8 +627,8 @@ typedef struct _AT91S_MC
 /* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */
 #define AT91C_MC_RCB                       ( ( unsigned int ) 0x1 << 0 )   /* (MC) Remap Command Bit */
 /* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */
-#define AT91C_MC_UNDADD                    ( ( unsigned int ) 0x1 << 0 )   /* (MC) Undefined Addess Abort Status */
-#define AT91C_MC_MISADD                    ( ( unsigned int ) 0x1 << 1 )   /* (MC) Misaligned Addess Abort Status */
+#define AT91C_MC_UNDADD                    ( ( unsigned int ) 0x1 << 0 )   /* (MC) Undefined Address Abort Status */
+#define AT91C_MC_MISADD                    ( ( unsigned int ) 0x1 << 1 )   /* (MC) Misaligned Address Abort Status */
 #define AT91C_MC_ABTSZ                     ( ( unsigned int ) 0x3 << 8 )   /* (MC) Abort Size Status */
 #define     AT91C_MC_ABTSZ_BYTE            ( ( unsigned int ) 0x0 << 8 )   /* (MC) Byte */
 #define     AT91C_MC_ABTSZ_HWORD           ( ( unsigned int ) 0x1 << 8 )   /* (MC) Half-word */
@@ -1509,7 +1509,7 @@ typedef struct _AT91S_EMAC
     AT91_REG EMAC_ECOL;       /* Excessive Collision Register */
     AT91_REG EMAC_TUND;       /* Transmit Underrun Error Register */
     AT91_REG EMAC_CSE;        /* Carrier Sense Error Register */
-    AT91_REG EMAC_RRE;        /* Receive Ressource Error Register */
+    AT91_REG EMAC_RRE;        /* Receive Resource Error Register */
     AT91_REG EMAC_ROV;        /* Receive Overrun Errors Register */
     AT91_REG EMAC_RSE;        /* Receive Symbol Errors Register */
     AT91_REG EMAC_ELE;        /* Excessive Length Errors Register */
@@ -2393,7 +2393,7 @@ typedef struct _AT91S_TDES
 #define AT91C_EMAC_SA1H            ( ( AT91_REG * ) 0xFFFDC09C ) /* (EMAC) Specific Address 1 Top, Last 2 bytes */
 #define AT91C_EMAC_CSE             ( ( AT91_REG * ) 0xFFFDC068 ) /* (EMAC) Carrier Sense Error Register */
 #define AT91C_EMAC_SA3H            ( ( AT91_REG * ) 0xFFFDC0AC ) /* (EMAC) Specific Address 3 Top, Last 2 bytes */
-#define AT91C_EMAC_RRE             ( ( AT91_REG * ) 0xFFFDC06C ) /* (EMAC) Receive Ressource Error Register */
+#define AT91C_EMAC_RRE             ( ( AT91_REG * ) 0xFFFDC06C ) /* (EMAC) Receive Resource Error Register */
 #define AT91C_EMAC_STE             ( ( AT91_REG * ) 0xFFFDC084 ) /* (EMAC) SQE Test Error Register */
 /* ========== Register definition for PDC_ADC peripheral ========== */
 #define AT91C_ADC_PTSR             ( ( AT91_REG * ) 0xFFFD8124 ) /* (PDC_ADC) PDC Transfer Status Register */
@@ -3125,9 +3125,9 @@ AT91C_MC_RCB EQU( 0x1 << 0 );
 -( MC ) Remap Command Bit
 /* - -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */
 AT91C_MC_UNDADD EQU( 0x1 << 0 );
--( MC ) Undefined Addess Abort Status
+-( MC ) Undefined Address Abort Status
 AT91C_MC_MISADD EQU( 0x1 << 1 );
--( MC ) Misaligned Addess Abort Status
+-( MC ) Misaligned Address Abort Status
 AT91C_MC_ABTSZ EQU( 0x3 << 8 );
 -( MC ) Abort Size Status
 AT91C_MC_ABTSZ_BYTE EQU( 0x0 << 8 );
@@ -5698,7 +5698,7 @@ AT91C_US_CLKS EQU( 0x3 << 4 );
                                                           AT91C_EMAC_SA3H EQU( 0xFFFDC0AC );
                                                           -( EMAC ) Specific Address 3 Top, Last 2 bytes
                                                           AT91C_EMAC_RRE EQU( 0xFFFDC06C );
-                                                          -( EMAC ) Receive Ressource Error Register
+                                                          -( EMAC ) Receive Resource Error Register
                                                           AT91C_EMAC_STE EQU( 0xFFFDC084 );
                                                           -( EMAC ) SQE Test Error Register
 /* - ========== Register definition for PDC_ADC peripheral ========== */
diff --git a/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.h b/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.h
index 0d9a70884..5de1aee3b 100644
--- a/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.h
+++ b/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.h
@@ -210,7 +210,7 @@
 /** \brief Set the next receive transfer descriptor */
 /**---------------------------------------------------------------------------- */
     __inline void AT91F_PDC_SetNextRx( AT91PS_PDC pPDC,     /* \arg pointer to a PDC controller */
-                                       char * address,      /* \arg address to the next bloc to be received */
+                                       char * address,      /* \arg address to the next block to be received */
                                        unsigned int bytes ) /* \arg number of bytes to be received */
     {
         pPDC->PDC_RNPR = ( unsigned int ) address;
@@ -222,7 +222,7 @@
 /** \brief Set the next transmit transfer descriptor */
 /**---------------------------------------------------------------------------- */
     __inline void AT91F_PDC_SetNextTx( AT91PS_PDC pPDC,     /* \arg pointer to a PDC controller */
-                                       char * address,      /* \arg address to the next bloc to be transmitted */
+                                       char * address,      /* \arg address to the next block to be transmitted */
                                        unsigned int bytes ) /* \arg number of bytes to be transmitted */
     {
         pPDC->PDC_TNPR = ( unsigned int ) address;
@@ -234,7 +234,7 @@
 /** \brief Set the receive transfer descriptor */
 /**---------------------------------------------------------------------------- */
     __inline void AT91F_PDC_SetRx( AT91PS_PDC pPDC,     /* \arg pointer to a PDC controller */
-                                   char * address,      /* \arg address to the next bloc to be received */
+                                   char * address,      /* \arg address to the next block to be received */
                                    unsigned int bytes ) /* \arg number of bytes to be received */
     {
         pPDC->PDC_RPR = ( unsigned int ) address;
@@ -246,7 +246,7 @@
 /** \brief Set the transmit transfer descriptor */
 /**---------------------------------------------------------------------------- */
     __inline void AT91F_PDC_SetTx( AT91PS_PDC pPDC,     /* \arg pointer to a PDC controller */
-                                   char * address,      /* \arg address to the next bloc to be transmitted */
+                                   char * address,      /* \arg address to the next block to be transmitted */
                                    unsigned int bytes ) /* \arg number of bytes to be transmitted */
     {
         pPDC->PDC_TPR = ( unsigned int ) address;
diff --git a/portable/GCC/ARM_AARCH64/port.c b/portable/GCC/ARM_AARCH64/port.c
index 238874edc..7f080db74 100644
--- a/portable/GCC/ARM_AARCH64/port.c
+++ b/portable/GCC/ARM_AARCH64/port.c
@@ -547,7 +547,7 @@ UBaseType_t uxPortSetInterruptMask( void )
          * this is not the case (if some bits represent a sub-priority).
          *
          * The priority grouping is configured by the GIC's binary point register
-         * (ICCBPR).  Writting 0 to ICCBPR will ensure it is set to its lowest
+         * (ICCBPR).  Writing 0 to ICCBPR will ensure it is set to its lowest
          * possible value (which may be above 0). */
         configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
     }
diff --git a/portable/GCC/ARM_CA9/port.c b/portable/GCC/ARM_CA9/port.c
index 79b60a933..0fd9dd471 100644
--- a/portable/GCC/ARM_CA9/port.c
+++ b/portable/GCC/ARM_CA9/port.c
@@ -562,7 +562,7 @@ uint32_t ulPortSetInterruptMask( void )
          * this is not the case (if some bits represent a sub-priority).
          *
          * The priority grouping is configured by the GIC's binary point register
-         * (ICCBPR).  Writting 0 to ICCBPR will ensure it is set to its lowest
+         * (ICCBPR).  Writing 0 to ICCBPR will ensure it is set to its lowest
          * possible value (which may be above 0). */
         configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
     }
diff --git a/portable/GCC/ARM_CM0/portasm.h b/portable/GCC/ARM_CM0/portasm.h
index 77e87b132..346507531 100644
--- a/portable/GCC/ARM_CM0/portasm.h
+++ b/portable/GCC/ARM_CM0/portasm.h
@@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
  * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
  * register.
  *
- * @note This is a privileged function and should only be called from the kenrel
+ * @note This is a privileged function and should only be called from the kernel
  * code.
  *
  * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
diff --git a/portable/GCC/ARM_CM23/non_secure/port.c b/portable/GCC/ARM_CM23/non_secure/port.c
index 5b399358e..a33dfa43c 100644
--- a/portable/GCC/ARM_CM23/non_secure/port.c
+++ b/portable/GCC/ARM_CM23/non_secure/port.c
@@ -56,7 +56,7 @@
  * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
  * i.e. the processor boots as secure and never jumps to the non-secure side.
  * The Trust Zone support in the port must be disabled in order to run FreeRTOS
- * on the secure side. The following are the valid configuration seetings:
+ * on the secure side. The following are the valid configuration settings:
  *
  * 1. Run FreeRTOS on the Secure Side:
  *    configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
diff --git a/portable/GCC/ARM_CM23/non_secure/portasm.h b/portable/GCC/ARM_CM23/non_secure/portasm.h
index bd5a2bfca..b7021b024 100644
--- a/portable/GCC/ARM_CM23/non_secure/portasm.h
+++ b/portable/GCC/ARM_CM23/non_secure/portasm.h
@@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
  * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
  * register.
  *
- * @note This is a privileged function and should only be called from the kenrel
+ * @note This is a privileged function and should only be called from the kernel
  * code.
  *
  * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
diff --git a/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h
index 3cf65761f..cd83bee57 100644
--- a/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h
@@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portPRIVILEGE_BIT         ( 0x0UL )
 #endif /* configENABLE_MPU */
 
-/* MPU settings that can be overriden in FreeRTOSConfig.h. */
+/* MPU settings that can be overridden in FreeRTOSConfig.h. */
 #ifndef configTOTAL_MPU_REGIONS
     /* Define to 8 for backward compatibility. */
     #define configTOTAL_MPU_REGIONS    ( 8UL )
diff --git a/portable/GCC/ARM_CM23/secure/secure_context.c b/portable/GCC/ARM_CM23/secure/secure_context.c
index 72fb3862c..3aa335e63 100644
--- a/portable/GCC/ARM_CM23/secure/secure_context.c
+++ b/portable/GCC/ARM_CM23/secure/secure_context.c
@@ -207,7 +207,7 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
      * securecontextNO_STACK when no secure context is loaded. */
     if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) )
     {
-        /* Ontain a free secure context. */
+        /* Obtain a free secure context. */
         ulSecureContextIndex = ulGetSecureContext( pvTaskHandle );
 
         /* Were we able to get a free context? */
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
index 5b399358e..a33dfa43c 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
@@ -56,7 +56,7 @@
  * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
  * i.e. the processor boots as secure and never jumps to the non-secure side.
  * The Trust Zone support in the port must be disabled in order to run FreeRTOS
- * on the secure side. The following are the valid configuration seetings:
+ * on the secure side. The following are the valid configuration settings:
  *
  * 1. Run FreeRTOS on the Secure Side:
  *    configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.h b/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.h
index bd5a2bfca..b7021b024 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.h
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.h
@@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
  * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
  * register.
  *
- * @note This is a privileged function and should only be called from the kenrel
+ * @note This is a privileged function and should only be called from the kernel
  * code.
  *
  * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h
index 3cf65761f..cd83bee57 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h
@@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portPRIVILEGE_BIT         ( 0x0UL )
 #endif /* configENABLE_MPU */
 
-/* MPU settings that can be overriden in FreeRTOSConfig.h. */
+/* MPU settings that can be overridden in FreeRTOSConfig.h. */
 #ifndef configTOTAL_MPU_REGIONS
     /* Define to 8 for backward compatibility. */
     #define configTOTAL_MPU_REGIONS    ( 8UL )
diff --git a/portable/GCC/ARM_CM33/non_secure/port.c b/portable/GCC/ARM_CM33/non_secure/port.c
index 5b399358e..a33dfa43c 100644
--- a/portable/GCC/ARM_CM33/non_secure/port.c
+++ b/portable/GCC/ARM_CM33/non_secure/port.c
@@ -56,7 +56,7 @@
  * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
  * i.e. the processor boots as secure and never jumps to the non-secure side.
  * The Trust Zone support in the port must be disabled in order to run FreeRTOS
- * on the secure side. The following are the valid configuration seetings:
+ * on the secure side. The following are the valid configuration settings:
  *
  * 1. Run FreeRTOS on the Secure Side:
  *    configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
diff --git a/portable/GCC/ARM_CM33/non_secure/portasm.c b/portable/GCC/ARM_CM33/non_secure/portasm.c
index f09840a46..aaeccaa35 100644
--- a/portable/GCC/ARM_CM33/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM33/non_secure/portasm.c
@@ -227,7 +227,7 @@ uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCT
         "                                                   \n"
         "   mrs r0, basepri                                 \n" /* r0 = basepri. Return original basepri value. */
         "   mov r1, %0                                      \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        "   msr basepri, r1                                 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        "   msr basepri, r1                                 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
         "   dsb                                             \n"
         "   isb                                             \n"
         "   bx lr                                           \n" /* Return. */
@@ -304,7 +304,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "                                                 \n"
             " select_next_task:                               \n"
             "    mov r0, %0                                   \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
-            "    msr basepri, r0                              \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+            "    msr basepri, r0                              \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
             "    dsb                                          \n"
             "    isb                                          \n"
             "    bl vTaskSwitchContext                        \n"
@@ -447,7 +447,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "                                                   \n"
             " select_next_task:                                 \n"
             "   mov r0, %0                                      \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
-            "   msr basepri, r0                                 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+            "   msr basepri, r0                                 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
             "   dsb                                             \n"
             "   isb                                             \n"
             "   bl vTaskSwitchContext                           \n"
diff --git a/portable/GCC/ARM_CM33/non_secure/portasm.h b/portable/GCC/ARM_CM33/non_secure/portasm.h
index bd5a2bfca..b7021b024 100644
--- a/portable/GCC/ARM_CM33/non_secure/portasm.h
+++ b/portable/GCC/ARM_CM33/non_secure/portasm.h
@@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
  * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
  * register.
  *
- * @note This is a privileged function and should only be called from the kenrel
+ * @note This is a privileged function and should only be called from the kernel
  * code.
  *
  * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
diff --git a/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h
index 3cf65761f..cd83bee57 100644
--- a/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h
@@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portPRIVILEGE_BIT         ( 0x0UL )
 #endif /* configENABLE_MPU */
 
-/* MPU settings that can be overriden in FreeRTOSConfig.h. */
+/* MPU settings that can be overridden in FreeRTOSConfig.h. */
 #ifndef configTOTAL_MPU_REGIONS
     /* Define to 8 for backward compatibility. */
     #define configTOTAL_MPU_REGIONS    ( 8UL )
diff --git a/portable/GCC/ARM_CM33/secure/secure_context.c b/portable/GCC/ARM_CM33/secure/secure_context.c
index 72fb3862c..3aa335e63 100644
--- a/portable/GCC/ARM_CM33/secure/secure_context.c
+++ b/portable/GCC/ARM_CM33/secure/secure_context.c
@@ -207,7 +207,7 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
      * securecontextNO_STACK when no secure context is loaded. */
     if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) )
     {
-        /* Ontain a free secure context. */
+        /* Obtain a free secure context. */
         ulSecureContextIndex = ulGetSecureContext( pvTaskHandle );
 
         /* Were we able to get a free context? */
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
index 5b399358e..a33dfa43c 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
@@ -56,7 +56,7 @@
  * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
  * i.e. the processor boots as secure and never jumps to the non-secure side.
  * The Trust Zone support in the port must be disabled in order to run FreeRTOS
- * on the secure side. The following are the valid configuration seetings:
+ * on the secure side. The following are the valid configuration settings:
  *
  * 1. Run FreeRTOS on the Secure Side:
  *    configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c b/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c
index 47996cd9e..7cdff7005 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c
@@ -223,7 +223,7 @@ uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCT
         "                                                   \n"
         "   mrs r0, basepri                                 \n" /* r0 = basepri. Return original basepri value. */
         "   mov r1, %0                                      \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        "   msr basepri, r1                                 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        "   msr basepri, r1                                 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
         "   dsb                                             \n"
         "   isb                                             \n"
         "   bx lr                                           \n" /* Return. */
@@ -283,7 +283,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "                                                 \n"
             " select_next_task:                               \n"
             "    mov r0, %0                                   \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
-            "    msr basepri, r0                              \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+            "    msr basepri, r0                              \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
             "    dsb                                          \n"
             "    isb                                          \n"
             "    bl vTaskSwitchContext                        \n"
@@ -386,7 +386,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   str r0, [r1]                                    \n" /* Save the new top of stack in TCB. */
             "                                                   \n"
             "   mov r0, %0                                      \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
-            "   msr basepri, r0                                 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+            "   msr basepri, r0                                 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
             "   dsb                                             \n"
             "   isb                                             \n"
             "   bl vTaskSwitchContext                           \n"
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h b/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h
index bd5a2bfca..b7021b024 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h
@@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
  * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
  * register.
  *
- * @note This is a privileged function and should only be called from the kenrel
+ * @note This is a privileged function and should only be called from the kernel
  * code.
  *
  * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h
index 3cf65761f..cd83bee57 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h
@@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portPRIVILEGE_BIT         ( 0x0UL )
 #endif /* configENABLE_MPU */
 
-/* MPU settings that can be overriden in FreeRTOSConfig.h. */
+/* MPU settings that can be overridden in FreeRTOSConfig.h. */
 #ifndef configTOTAL_MPU_REGIONS
     /* Define to 8 for backward compatibility. */
     #define configTOTAL_MPU_REGIONS    ( 8UL )
diff --git a/portable/GCC/ARM_CM35P/non_secure/port.c b/portable/GCC/ARM_CM35P/non_secure/port.c
index 5b399358e..a33dfa43c 100644
--- a/portable/GCC/ARM_CM35P/non_secure/port.c
+++ b/portable/GCC/ARM_CM35P/non_secure/port.c
@@ -56,7 +56,7 @@
  * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
  * i.e. the processor boots as secure and never jumps to the non-secure side.
  * The Trust Zone support in the port must be disabled in order to run FreeRTOS
- * on the secure side. The following are the valid configuration seetings:
+ * on the secure side. The following are the valid configuration settings:
  *
  * 1. Run FreeRTOS on the Secure Side:
  *    configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
diff --git a/portable/GCC/ARM_CM35P/non_secure/portasm.c b/portable/GCC/ARM_CM35P/non_secure/portasm.c
index f09840a46..aaeccaa35 100644
--- a/portable/GCC/ARM_CM35P/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM35P/non_secure/portasm.c
@@ -227,7 +227,7 @@ uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCT
         "                                                   \n"
         "   mrs r0, basepri                                 \n" /* r0 = basepri. Return original basepri value. */
         "   mov r1, %0                                      \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        "   msr basepri, r1                                 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        "   msr basepri, r1                                 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
         "   dsb                                             \n"
         "   isb                                             \n"
         "   bx lr                                           \n" /* Return. */
@@ -304,7 +304,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "                                                 \n"
             " select_next_task:                               \n"
             "    mov r0, %0                                   \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
-            "    msr basepri, r0                              \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+            "    msr basepri, r0                              \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
             "    dsb                                          \n"
             "    isb                                          \n"
             "    bl vTaskSwitchContext                        \n"
@@ -447,7 +447,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "                                                   \n"
             " select_next_task:                                 \n"
             "   mov r0, %0                                      \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
-            "   msr basepri, r0                                 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+            "   msr basepri, r0                                 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
             "   dsb                                             \n"
             "   isb                                             \n"
             "   bl vTaskSwitchContext                           \n"
diff --git a/portable/GCC/ARM_CM35P/non_secure/portasm.h b/portable/GCC/ARM_CM35P/non_secure/portasm.h
index bd5a2bfca..b7021b024 100644
--- a/portable/GCC/ARM_CM35P/non_secure/portasm.h
+++ b/portable/GCC/ARM_CM35P/non_secure/portasm.h
@@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
  * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
  * register.
  *
- * @note This is a privileged function and should only be called from the kenrel
+ * @note This is a privileged function and should only be called from the kernel
  * code.
  *
  * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
diff --git a/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h
index 3cf65761f..cd83bee57 100644
--- a/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h
@@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portPRIVILEGE_BIT         ( 0x0UL )
 #endif /* configENABLE_MPU */
 
-/* MPU settings that can be overriden in FreeRTOSConfig.h. */
+/* MPU settings that can be overridden in FreeRTOSConfig.h. */
 #ifndef configTOTAL_MPU_REGIONS
     /* Define to 8 for backward compatibility. */
     #define configTOTAL_MPU_REGIONS    ( 8UL )
diff --git a/portable/GCC/ARM_CM35P/secure/secure_context.c b/portable/GCC/ARM_CM35P/secure/secure_context.c
index 72fb3862c..3aa335e63 100644
--- a/portable/GCC/ARM_CM35P/secure/secure_context.c
+++ b/portable/GCC/ARM_CM35P/secure/secure_context.c
@@ -207,7 +207,7 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
      * securecontextNO_STACK when no secure context is loaded. */
     if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) )
     {
-        /* Ontain a free secure context. */
+        /* Obtain a free secure context. */
         ulSecureContextIndex = ulGetSecureContext( pvTaskHandle );
 
         /* Were we able to get a free context? */
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c b/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
index 5b399358e..a33dfa43c 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
@@ -56,7 +56,7 @@
  * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
  * i.e. the processor boots as secure and never jumps to the non-secure side.
  * The Trust Zone support in the port must be disabled in order to run FreeRTOS
- * on the secure side. The following are the valid configuration seetings:
+ * on the secure side. The following are the valid configuration settings:
  *
  * 1. Run FreeRTOS on the Secure Side:
  *    configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.c b/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.c
index 47996cd9e..7cdff7005 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.c
@@ -223,7 +223,7 @@ uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCT
         "                                                   \n"
         "   mrs r0, basepri                                 \n" /* r0 = basepri. Return original basepri value. */
         "   mov r1, %0                                      \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        "   msr basepri, r1                                 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        "   msr basepri, r1                                 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
         "   dsb                                             \n"
         "   isb                                             \n"
         "   bx lr                                           \n" /* Return. */
@@ -283,7 +283,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "                                                 \n"
             " select_next_task:                               \n"
             "    mov r0, %0                                   \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
-            "    msr basepri, r0                              \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+            "    msr basepri, r0                              \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
             "    dsb                                          \n"
             "    isb                                          \n"
             "    bl vTaskSwitchContext                        \n"
@@ -386,7 +386,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   str r0, [r1]                                    \n" /* Save the new top of stack in TCB. */
             "                                                   \n"
             "   mov r0, %0                                      \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
-            "   msr basepri, r0                                 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+            "   msr basepri, r0                                 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
             "   dsb                                             \n"
             "   isb                                             \n"
             "   bl vTaskSwitchContext                           \n"
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.h b/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.h
index bd5a2bfca..b7021b024 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.h
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.h
@@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
  * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
  * register.
  *
- * @note This is a privileged function and should only be called from the kenrel
+ * @note This is a privileged function and should only be called from the kernel
  * code.
  *
  * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
index 3cf65761f..cd83bee57 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
@@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portPRIVILEGE_BIT         ( 0x0UL )
 #endif /* configENABLE_MPU */
 
-/* MPU settings that can be overriden in FreeRTOSConfig.h. */
+/* MPU settings that can be overridden in FreeRTOSConfig.h. */
 #ifndef configTOTAL_MPU_REGIONS
     /* Define to 8 for backward compatibility. */
     #define configTOTAL_MPU_REGIONS    ( 8UL )
diff --git a/portable/GCC/ARM_CM4_MPU/portmacro.h b/portable/GCC/ARM_CM4_MPU/portmacro.h
index d9677a72b..264887e8e 100644
--- a/portable/GCC/ARM_CM4_MPU/portmacro.h
+++ b/portable/GCC/ARM_CM4_MPU/portmacro.h
@@ -98,7 +98,7 @@ typedef unsigned long    UBaseType_t;
 #define portMPU_RASR_TEX_S_C_B_LOCATION                          ( 16UL )
 #define portMPU_RASR_TEX_S_C_B_MASK                              ( 0x3FUL )
 
-/* MPU settings that can be overriden in FreeRTOSConfig.h. */
+/* MPU settings that can be overridden in FreeRTOSConfig.h. */
 #ifndef configTOTAL_MPU_REGIONS
     /* Define to 8 for backward compatibility. */
     #define configTOTAL_MPU_REGIONS    ( 8UL )
diff --git a/portable/GCC/ARM_CM55/non_secure/port.c b/portable/GCC/ARM_CM55/non_secure/port.c
index 5b399358e..a33dfa43c 100644
--- a/portable/GCC/ARM_CM55/non_secure/port.c
+++ b/portable/GCC/ARM_CM55/non_secure/port.c
@@ -56,7 +56,7 @@
  * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
  * i.e. the processor boots as secure and never jumps to the non-secure side.
  * The Trust Zone support in the port must be disabled in order to run FreeRTOS
- * on the secure side. The following are the valid configuration seetings:
+ * on the secure side. The following are the valid configuration settings:
  *
  * 1. Run FreeRTOS on the Secure Side:
  *    configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
diff --git a/portable/GCC/ARM_CM55/non_secure/portasm.c b/portable/GCC/ARM_CM55/non_secure/portasm.c
index f09840a46..aaeccaa35 100644
--- a/portable/GCC/ARM_CM55/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM55/non_secure/portasm.c
@@ -227,7 +227,7 @@ uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCT
         "                                                   \n"
         "   mrs r0, basepri                                 \n" /* r0 = basepri. Return original basepri value. */
         "   mov r1, %0                                      \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        "   msr basepri, r1                                 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        "   msr basepri, r1                                 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
         "   dsb                                             \n"
         "   isb                                             \n"
         "   bx lr                                           \n" /* Return. */
@@ -304,7 +304,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "                                                 \n"
             " select_next_task:                               \n"
             "    mov r0, %0                                   \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
-            "    msr basepri, r0                              \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+            "    msr basepri, r0                              \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
             "    dsb                                          \n"
             "    isb                                          \n"
             "    bl vTaskSwitchContext                        \n"
@@ -447,7 +447,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "                                                   \n"
             " select_next_task:                                 \n"
             "   mov r0, %0                                      \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
-            "   msr basepri, r0                                 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+            "   msr basepri, r0                                 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
             "   dsb                                             \n"
             "   isb                                             \n"
             "   bl vTaskSwitchContext                           \n"
diff --git a/portable/GCC/ARM_CM55/non_secure/portasm.h b/portable/GCC/ARM_CM55/non_secure/portasm.h
index bd5a2bfca..b7021b024 100644
--- a/portable/GCC/ARM_CM55/non_secure/portasm.h
+++ b/portable/GCC/ARM_CM55/non_secure/portasm.h
@@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
  * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
  * register.
  *
- * @note This is a privileged function and should only be called from the kenrel
+ * @note This is a privileged function and should only be called from the kernel
  * code.
  *
  * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
diff --git a/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h
index 3cf65761f..cd83bee57 100644
--- a/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h
@@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portPRIVILEGE_BIT         ( 0x0UL )
 #endif /* configENABLE_MPU */
 
-/* MPU settings that can be overriden in FreeRTOSConfig.h. */
+/* MPU settings that can be overridden in FreeRTOSConfig.h. */
 #ifndef configTOTAL_MPU_REGIONS
     /* Define to 8 for backward compatibility. */
     #define configTOTAL_MPU_REGIONS    ( 8UL )
diff --git a/portable/GCC/ARM_CM55/secure/secure_context.c b/portable/GCC/ARM_CM55/secure/secure_context.c
index 72fb3862c..3aa335e63 100644
--- a/portable/GCC/ARM_CM55/secure/secure_context.c
+++ b/portable/GCC/ARM_CM55/secure/secure_context.c
@@ -207,7 +207,7 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
      * securecontextNO_STACK when no secure context is loaded. */
     if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) )
     {
-        /* Ontain a free secure context. */
+        /* Obtain a free secure context. */
         ulSecureContextIndex = ulGetSecureContext( pvTaskHandle );
 
         /* Were we able to get a free context? */
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/port.c b/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
index 5b399358e..a33dfa43c 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
@@ -56,7 +56,7 @@
  * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
  * i.e. the processor boots as secure and never jumps to the non-secure side.
  * The Trust Zone support in the port must be disabled in order to run FreeRTOS
- * on the secure side. The following are the valid configuration seetings:
+ * on the secure side. The following are the valid configuration settings:
  *
  * 1. Run FreeRTOS on the Secure Side:
  *    configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.c b/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.c
index 47996cd9e..7cdff7005 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.c
@@ -223,7 +223,7 @@ uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCT
         "                                                   \n"
         "   mrs r0, basepri                                 \n" /* r0 = basepri. Return original basepri value. */
         "   mov r1, %0                                      \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        "   msr basepri, r1                                 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        "   msr basepri, r1                                 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
         "   dsb                                             \n"
         "   isb                                             \n"
         "   bx lr                                           \n" /* Return. */
@@ -283,7 +283,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "                                                 \n"
             " select_next_task:                               \n"
             "    mov r0, %0                                   \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
-            "    msr basepri, r0                              \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+            "    msr basepri, r0                              \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
             "    dsb                                          \n"
             "    isb                                          \n"
             "    bl vTaskSwitchContext                        \n"
@@ -386,7 +386,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   str r0, [r1]                                    \n" /* Save the new top of stack in TCB. */
             "                                                   \n"
             "   mov r0, %0                                      \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
-            "   msr basepri, r0                                 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+            "   msr basepri, r0                                 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
             "   dsb                                             \n"
             "   isb                                             \n"
             "   bl vTaskSwitchContext                           \n"
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.h b/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.h
index bd5a2bfca..b7021b024 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.h
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.h
@@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
  * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
  * register.
  *
- * @note This is a privileged function and should only be called from the kenrel
+ * @note This is a privileged function and should only be called from the kernel
  * code.
  *
  * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h
index 3cf65761f..cd83bee57 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h
@@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portPRIVILEGE_BIT         ( 0x0UL )
 #endif /* configENABLE_MPU */
 
-/* MPU settings that can be overriden in FreeRTOSConfig.h. */
+/* MPU settings that can be overridden in FreeRTOSConfig.h. */
 #ifndef configTOTAL_MPU_REGIONS
     /* Define to 8 for backward compatibility. */
     #define configTOTAL_MPU_REGIONS    ( 8UL )
diff --git a/portable/GCC/ARM_CM85/non_secure/port.c b/portable/GCC/ARM_CM85/non_secure/port.c
index 5b399358e..a33dfa43c 100644
--- a/portable/GCC/ARM_CM85/non_secure/port.c
+++ b/portable/GCC/ARM_CM85/non_secure/port.c
@@ -56,7 +56,7 @@
  * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
  * i.e. the processor boots as secure and never jumps to the non-secure side.
  * The Trust Zone support in the port must be disabled in order to run FreeRTOS
- * on the secure side. The following are the valid configuration seetings:
+ * on the secure side. The following are the valid configuration settings:
  *
  * 1. Run FreeRTOS on the Secure Side:
  *    configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
diff --git a/portable/GCC/ARM_CM85/non_secure/portasm.c b/portable/GCC/ARM_CM85/non_secure/portasm.c
index f09840a46..aaeccaa35 100644
--- a/portable/GCC/ARM_CM85/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM85/non_secure/portasm.c
@@ -227,7 +227,7 @@ uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCT
         "                                                   \n"
         "   mrs r0, basepri                                 \n" /* r0 = basepri. Return original basepri value. */
         "   mov r1, %0                                      \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        "   msr basepri, r1                                 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        "   msr basepri, r1                                 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
         "   dsb                                             \n"
         "   isb                                             \n"
         "   bx lr                                           \n" /* Return. */
@@ -304,7 +304,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "                                                 \n"
             " select_next_task:                               \n"
             "    mov r0, %0                                   \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
-            "    msr basepri, r0                              \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+            "    msr basepri, r0                              \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
             "    dsb                                          \n"
             "    isb                                          \n"
             "    bl vTaskSwitchContext                        \n"
@@ -447,7 +447,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "                                                   \n"
             " select_next_task:                                 \n"
             "   mov r0, %0                                      \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
-            "   msr basepri, r0                                 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+            "   msr basepri, r0                                 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
             "   dsb                                             \n"
             "   isb                                             \n"
             "   bl vTaskSwitchContext                           \n"
diff --git a/portable/GCC/ARM_CM85/non_secure/portasm.h b/portable/GCC/ARM_CM85/non_secure/portasm.h
index bd5a2bfca..b7021b024 100644
--- a/portable/GCC/ARM_CM85/non_secure/portasm.h
+++ b/portable/GCC/ARM_CM85/non_secure/portasm.h
@@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
  * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
  * register.
  *
- * @note This is a privileged function and should only be called from the kenrel
+ * @note This is a privileged function and should only be called from the kernel
  * code.
  *
  * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
diff --git a/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h
index 3cf65761f..cd83bee57 100644
--- a/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h
@@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portPRIVILEGE_BIT         ( 0x0UL )
 #endif /* configENABLE_MPU */
 
-/* MPU settings that can be overriden in FreeRTOSConfig.h. */
+/* MPU settings that can be overridden in FreeRTOSConfig.h. */
 #ifndef configTOTAL_MPU_REGIONS
     /* Define to 8 for backward compatibility. */
     #define configTOTAL_MPU_REGIONS    ( 8UL )
diff --git a/portable/GCC/ARM_CM85/secure/secure_context.c b/portable/GCC/ARM_CM85/secure/secure_context.c
index 72fb3862c..3aa335e63 100644
--- a/portable/GCC/ARM_CM85/secure/secure_context.c
+++ b/portable/GCC/ARM_CM85/secure/secure_context.c
@@ -207,7 +207,7 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
      * securecontextNO_STACK when no secure context is loaded. */
     if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) )
     {
-        /* Ontain a free secure context. */
+        /* Obtain a free secure context. */
         ulSecureContextIndex = ulGetSecureContext( pvTaskHandle );
 
         /* Were we able to get a free context? */
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/port.c b/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
index 5b399358e..a33dfa43c 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
@@ -56,7 +56,7 @@
  * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
  * i.e. the processor boots as secure and never jumps to the non-secure side.
  * The Trust Zone support in the port must be disabled in order to run FreeRTOS
- * on the secure side. The following are the valid configuration seetings:
+ * on the secure side. The following are the valid configuration settings:
  *
  * 1. Run FreeRTOS on the Secure Side:
  *    configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.c b/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.c
index 47996cd9e..7cdff7005 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.c
@@ -223,7 +223,7 @@ uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCT
         "                                                   \n"
         "   mrs r0, basepri                                 \n" /* r0 = basepri. Return original basepri value. */
         "   mov r1, %0                                      \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        "   msr basepri, r1                                 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        "   msr basepri, r1                                 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
         "   dsb                                             \n"
         "   isb                                             \n"
         "   bx lr                                           \n" /* Return. */
@@ -283,7 +283,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "                                                 \n"
             " select_next_task:                               \n"
             "    mov r0, %0                                   \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
-            "    msr basepri, r0                              \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+            "    msr basepri, r0                              \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
             "    dsb                                          \n"
             "    isb                                          \n"
             "    bl vTaskSwitchContext                        \n"
@@ -386,7 +386,7 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   str r0, [r1]                                    \n" /* Save the new top of stack in TCB. */
             "                                                   \n"
             "   mov r0, %0                                      \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
-            "   msr basepri, r0                                 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+            "   msr basepri, r0                                 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
             "   dsb                                             \n"
             "   isb                                             \n"
             "   bl vTaskSwitchContext                           \n"
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.h b/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.h
index bd5a2bfca..b7021b024 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.h
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.h
@@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
  * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
  * register.
  *
- * @note This is a privileged function and should only be called from the kenrel
+ * @note This is a privileged function and should only be called from the kernel
  * code.
  *
  * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h
index 3cf65761f..cd83bee57 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h
@@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portPRIVILEGE_BIT         ( 0x0UL )
 #endif /* configENABLE_MPU */
 
-/* MPU settings that can be overriden in FreeRTOSConfig.h. */
+/* MPU settings that can be overridden in FreeRTOSConfig.h. */
 #ifndef configTOTAL_MPU_REGIONS
     /* Define to 8 for backward compatibility. */
     #define configTOTAL_MPU_REGIONS    ( 8UL )
diff --git a/portable/GCC/ARM_CRx_MPU/port.c b/portable/GCC/ARM_CRx_MPU/port.c
index e4904e58d..6b8d77cd6 100644
--- a/portable/GCC/ARM_CRx_MPU/port.c
+++ b/portable/GCC/ARM_CRx_MPU/port.c
@@ -100,7 +100,7 @@ PRIVILEGED_DATA static BaseType_t prvPortSchedulerRunning = pdFALSE;
  * @param ulBufferLength Length of the given buffer.
  * @param ulAccessRequested Access requested.
  *
- * @return pdTRUE if MPU region settins authorizes the requested access to the
+ * @return pdTRUE if MPU region settings authorizes the requested access to the
  * given buffer, pdFALSE otherwise.
  */
 PRIVILEGED_FUNCTION static BaseType_t prvMPURegionAuthorizesBuffer( const xMPU_REGION_REGISTERS * xTaskMPURegion,
diff --git a/portable/GCC/ARM_CRx_MPU/portmacro.h b/portable/GCC/ARM_CRx_MPU/portmacro.h
index 7e80f093e..1eb8f0162 100644
--- a/portable/GCC/ARM_CRx_MPU/portmacro.h
+++ b/portable/GCC/ARM_CRx_MPU/portmacro.h
@@ -236,7 +236,7 @@ typedef uint32_t TickType_t;
 #define portTICK_TYPE_IS_ATOMIC                      1
 
 /**
- * @brief The number of miliseconds between system ticks.
+ * @brief The number of milliseconds between system ticks.
  *
  * @ingroup System Clock
  */
@@ -380,7 +380,7 @@ void vPortExitCritical( void );
  * @note The processor privilege level is determined by checking the
  * mode bits [4:0] of the Current Program Status Register (CPSR).
  *
- * @return pdTRUE, if the processer is privileged, pdFALSE otherwise.
+ * @return pdTRUE, if the processor is privileged, pdFALSE otherwise.
  */
 BaseType_t xPortIsPrivileged( void );
 
diff --git a/portable/GCC/ARM_CRx_MPU/portmacro_asm.h b/portable/GCC/ARM_CRx_MPU/portmacro_asm.h
index a113ac02d..c9573e419 100644
--- a/portable/GCC/ARM_CRx_MPU/portmacro_asm.h
+++ b/portable/GCC/ARM_CRx_MPU/portmacro_asm.h
@@ -36,7 +36,7 @@ extern "C" {
 #include "FreeRTOSConfig.h"
 
 #ifndef configTOTAL_MPU_REGIONS
-    #error "Set configTOTAL_MPU_REGIONS to the humber of MPU regions in FreeRTOSConfig.h"
+    #error "Set configTOTAL_MPU_REGIONS to the number of MPU regions in FreeRTOSConfig.h"
 #elif( configTOTAL_MPU_REGIONS == 12 )
     #define portMPU_TOTAL_REGIONS ( 12UL )
 #elif( configTOTAL_MPU_REGIONS == 16 )
diff --git a/portable/GCC/AVR32_UC3/port.c b/portable/GCC/AVR32_UC3/port.c
index bd8b0bd2b..984ef56a0 100644
--- a/portable/GCC/AVR32_UC3/port.c
+++ b/portable/GCC/AVR32_UC3/port.c
@@ -401,7 +401,7 @@ static void prvSetupTimerInterrupt( void )
     #if ( configTICK_USE_TC == 1 )
         volatile avr32_tc_t * tc = &AVR32_TC;
 
-        /* Options for waveform genration. */
+        /* Options for waveform generation. */
         tc_waveform_opt_t waveform_opt =
         {
             .channel = configTICK_TC_CHANNEL,              /* Channel selection. */
diff --git a/portable/IAR/ARM_CA9/port.c b/portable/IAR/ARM_CA9/port.c
index f26ae3790..66852f9a7 100644
--- a/portable/IAR/ARM_CA9/port.c
+++ b/portable/IAR/ARM_CA9/port.c
@@ -438,7 +438,7 @@ uint32_t ulPortSetInterruptMask( void )
          * this is not the case (if some bits represent a sub-priority).
          *
          * The priority grouping is configured by the GIC's binary point register
-         * (ICCBPR).  Writting 0 to ICCBPR will ensure it is set to its lowest
+         * (ICCBPR).  Writing 0 to ICCBPR will ensure it is set to its lowest
          * possible value (which may be above 0). */
         configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
     }
diff --git a/portable/IAR/ARM_CM23/non_secure/port.c b/portable/IAR/ARM_CM23/non_secure/port.c
index 5b399358e..a33dfa43c 100644
--- a/portable/IAR/ARM_CM23/non_secure/port.c
+++ b/portable/IAR/ARM_CM23/non_secure/port.c
@@ -56,7 +56,7 @@
  * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
  * i.e. the processor boots as secure and never jumps to the non-secure side.
  * The Trust Zone support in the port must be disabled in order to run FreeRTOS
- * on the secure side. The following are the valid configuration seetings:
+ * on the secure side. The following are the valid configuration settings:
  *
  * 1. Run FreeRTOS on the Secure Side:
  *    configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
diff --git a/portable/IAR/ARM_CM23/non_secure/portasm.h b/portable/IAR/ARM_CM23/non_secure/portasm.h
index bd5a2bfca..b7021b024 100644
--- a/portable/IAR/ARM_CM23/non_secure/portasm.h
+++ b/portable/IAR/ARM_CM23/non_secure/portasm.h
@@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
  * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
  * register.
  *
- * @note This is a privileged function and should only be called from the kenrel
+ * @note This is a privileged function and should only be called from the kernel
  * code.
  *
  * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
diff --git a/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h
index 3cf65761f..cd83bee57 100644
--- a/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h
@@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portPRIVILEGE_BIT         ( 0x0UL )
 #endif /* configENABLE_MPU */
 
-/* MPU settings that can be overriden in FreeRTOSConfig.h. */
+/* MPU settings that can be overridden in FreeRTOSConfig.h. */
 #ifndef configTOTAL_MPU_REGIONS
     /* Define to 8 for backward compatibility. */
     #define configTOTAL_MPU_REGIONS    ( 8UL )
diff --git a/portable/IAR/ARM_CM23/secure/secure_context.c b/portable/IAR/ARM_CM23/secure/secure_context.c
index 72fb3862c..3aa335e63 100644
--- a/portable/IAR/ARM_CM23/secure/secure_context.c
+++ b/portable/IAR/ARM_CM23/secure/secure_context.c
@@ -207,7 +207,7 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
      * securecontextNO_STACK when no secure context is loaded. */
     if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) )
     {
-        /* Ontain a free secure context. */
+        /* Obtain a free secure context. */
         ulSecureContextIndex = ulGetSecureContext( pvTaskHandle );
 
         /* Were we able to get a free context? */
diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
index 5b399358e..a33dfa43c 100644
--- a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
@@ -56,7 +56,7 @@
  * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
  * i.e. the processor boots as secure and never jumps to the non-secure side.
  * The Trust Zone support in the port must be disabled in order to run FreeRTOS
- * on the secure side. The following are the valid configuration seetings:
+ * on the secure side. The following are the valid configuration settings:
  *
  * 1. Run FreeRTOS on the Secure Side:
  *    configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h b/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h
index bd5a2bfca..b7021b024 100644
--- a/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h
+++ b/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h
@@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
  * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
  * register.
  *
- * @note This is a privileged function and should only be called from the kenrel
+ * @note This is a privileged function and should only be called from the kernel
  * code.
  *
  * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h
index 3cf65761f..cd83bee57 100644
--- a/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h
@@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portPRIVILEGE_BIT         ( 0x0UL )
 #endif /* configENABLE_MPU */
 
-/* MPU settings that can be overriden in FreeRTOSConfig.h. */
+/* MPU settings that can be overridden in FreeRTOSConfig.h. */
 #ifndef configTOTAL_MPU_REGIONS
     /* Define to 8 for backward compatibility. */
     #define configTOTAL_MPU_REGIONS    ( 8UL )
diff --git a/portable/IAR/ARM_CM33/non_secure/port.c b/portable/IAR/ARM_CM33/non_secure/port.c
index 5b399358e..a33dfa43c 100644
--- a/portable/IAR/ARM_CM33/non_secure/port.c
+++ b/portable/IAR/ARM_CM33/non_secure/port.c
@@ -56,7 +56,7 @@
  * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
  * i.e. the processor boots as secure and never jumps to the non-secure side.
  * The Trust Zone support in the port must be disabled in order to run FreeRTOS
- * on the secure side. The following are the valid configuration seetings:
+ * on the secure side. The following are the valid configuration settings:
  *
  * 1. Run FreeRTOS on the Secure Side:
  *    configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
diff --git a/portable/IAR/ARM_CM33/non_secure/portasm.h b/portable/IAR/ARM_CM33/non_secure/portasm.h
index bd5a2bfca..b7021b024 100644
--- a/portable/IAR/ARM_CM33/non_secure/portasm.h
+++ b/portable/IAR/ARM_CM33/non_secure/portasm.h
@@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
  * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
  * register.
  *
- * @note This is a privileged function and should only be called from the kenrel
+ * @note This is a privileged function and should only be called from the kernel
  * code.
  *
  * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
diff --git a/portable/IAR/ARM_CM33/non_secure/portasm.s b/portable/IAR/ARM_CM33/non_secure/portasm.s
index f4b7ab20f..212688d61 100644
--- a/portable/IAR/ARM_CM33/non_secure/portasm.s
+++ b/portable/IAR/ARM_CM33/non_secure/portasm.s
@@ -216,7 +216,7 @@ vStartFirstTask:
 ulSetInterruptMask:
     mrs r0, basepri                         /* r0 = basepri. Return original basepri value. */
     mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY
-    msr basepri, r1                         /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+    msr basepri, r1                         /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
     dsb
     isb
     bx lr                                   /* Return. */
@@ -275,7 +275,7 @@ PendSV_Handler:
 
     select_next_task:
         mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
-        msr basepri, r0                     /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        msr basepri, r0                     /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
         dsb
         isb
         bl vTaskSwitchContext
@@ -409,7 +409,7 @@ PendSV_Handler:
 
     select_next_task:
         mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
-        msr basepri, r0                     /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        msr basepri, r0                     /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
         dsb
         isb
         bl vTaskSwitchContext
diff --git a/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h
index 3cf65761f..cd83bee57 100644
--- a/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h
@@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portPRIVILEGE_BIT         ( 0x0UL )
 #endif /* configENABLE_MPU */
 
-/* MPU settings that can be overriden in FreeRTOSConfig.h. */
+/* MPU settings that can be overridden in FreeRTOSConfig.h. */
 #ifndef configTOTAL_MPU_REGIONS
     /* Define to 8 for backward compatibility. */
     #define configTOTAL_MPU_REGIONS    ( 8UL )
diff --git a/portable/IAR/ARM_CM33/secure/secure_context.c b/portable/IAR/ARM_CM33/secure/secure_context.c
index 72fb3862c..3aa335e63 100644
--- a/portable/IAR/ARM_CM33/secure/secure_context.c
+++ b/portable/IAR/ARM_CM33/secure/secure_context.c
@@ -207,7 +207,7 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
      * securecontextNO_STACK when no secure context is loaded. */
     if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) )
     {
-        /* Ontain a free secure context. */
+        /* Obtain a free secure context. */
         ulSecureContextIndex = ulGetSecureContext( pvTaskHandle );
 
         /* Were we able to get a free context? */
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
index 5b399358e..a33dfa43c 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
@@ -56,7 +56,7 @@
  * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
  * i.e. the processor boots as secure and never jumps to the non-secure side.
  * The Trust Zone support in the port must be disabled in order to run FreeRTOS
- * on the secure side. The following are the valid configuration seetings:
+ * on the secure side. The following are the valid configuration settings:
  *
  * 1. Run FreeRTOS on the Secure Side:
  *    configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h b/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h
index bd5a2bfca..b7021b024 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h
@@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
  * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
  * register.
  *
- * @note This is a privileged function and should only be called from the kenrel
+ * @note This is a privileged function and should only be called from the kernel
  * code.
  *
  * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s b/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s
index be06f67ad..9d6c6a7ef 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s
@@ -202,7 +202,7 @@ vStartFirstTask:
 ulSetInterruptMask:
     mrs r0, basepri                         /* r0 = basepri. Return original basepri value. */
     mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY
-    msr basepri, r1                         /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+    msr basepri, r1                         /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
     dsb
     isb
     bx lr                                   /* Return. */
@@ -246,7 +246,7 @@ PendSV_Handler:
 
     select_next_task:
         mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
-        msr basepri, r0                     /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        msr basepri, r0                     /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
         dsb
         isb
         bl vTaskSwitchContext
@@ -340,7 +340,7 @@ PendSV_Handler:
     str r0, [r1]                            /* Save the new top of stack in TCB. */
 
     mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
-    msr basepri, r0                         /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+    msr basepri, r0                         /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
     dsb
     isb
     bl vTaskSwitchContext
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h
index 3cf65761f..cd83bee57 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h
@@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portPRIVILEGE_BIT         ( 0x0UL )
 #endif /* configENABLE_MPU */
 
-/* MPU settings that can be overriden in FreeRTOSConfig.h. */
+/* MPU settings that can be overridden in FreeRTOSConfig.h. */
 #ifndef configTOTAL_MPU_REGIONS
     /* Define to 8 for backward compatibility. */
     #define configTOTAL_MPU_REGIONS    ( 8UL )
diff --git a/portable/IAR/ARM_CM35P/non_secure/port.c b/portable/IAR/ARM_CM35P/non_secure/port.c
index 5b399358e..a33dfa43c 100644
--- a/portable/IAR/ARM_CM35P/non_secure/port.c
+++ b/portable/IAR/ARM_CM35P/non_secure/port.c
@@ -56,7 +56,7 @@
  * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
  * i.e. the processor boots as secure and never jumps to the non-secure side.
  * The Trust Zone support in the port must be disabled in order to run FreeRTOS
- * on the secure side. The following are the valid configuration seetings:
+ * on the secure side. The following are the valid configuration settings:
  *
  * 1. Run FreeRTOS on the Secure Side:
  *    configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
diff --git a/portable/IAR/ARM_CM35P/non_secure/portasm.h b/portable/IAR/ARM_CM35P/non_secure/portasm.h
index bd5a2bfca..b7021b024 100644
--- a/portable/IAR/ARM_CM35P/non_secure/portasm.h
+++ b/portable/IAR/ARM_CM35P/non_secure/portasm.h
@@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
  * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
  * register.
  *
- * @note This is a privileged function and should only be called from the kenrel
+ * @note This is a privileged function and should only be called from the kernel
  * code.
  *
  * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
diff --git a/portable/IAR/ARM_CM35P/non_secure/portasm.s b/portable/IAR/ARM_CM35P/non_secure/portasm.s
index f4b7ab20f..212688d61 100644
--- a/portable/IAR/ARM_CM35P/non_secure/portasm.s
+++ b/portable/IAR/ARM_CM35P/non_secure/portasm.s
@@ -216,7 +216,7 @@ vStartFirstTask:
 ulSetInterruptMask:
     mrs r0, basepri                         /* r0 = basepri. Return original basepri value. */
     mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY
-    msr basepri, r1                         /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+    msr basepri, r1                         /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
     dsb
     isb
     bx lr                                   /* Return. */
@@ -275,7 +275,7 @@ PendSV_Handler:
 
     select_next_task:
         mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
-        msr basepri, r0                     /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        msr basepri, r0                     /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
         dsb
         isb
         bl vTaskSwitchContext
@@ -409,7 +409,7 @@ PendSV_Handler:
 
     select_next_task:
         mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
-        msr basepri, r0                     /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        msr basepri, r0                     /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
         dsb
         isb
         bl vTaskSwitchContext
diff --git a/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h
index 3cf65761f..cd83bee57 100644
--- a/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h
@@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portPRIVILEGE_BIT         ( 0x0UL )
 #endif /* configENABLE_MPU */
 
-/* MPU settings that can be overriden in FreeRTOSConfig.h. */
+/* MPU settings that can be overridden in FreeRTOSConfig.h. */
 #ifndef configTOTAL_MPU_REGIONS
     /* Define to 8 for backward compatibility. */
     #define configTOTAL_MPU_REGIONS    ( 8UL )
diff --git a/portable/IAR/ARM_CM35P/secure/secure_context.c b/portable/IAR/ARM_CM35P/secure/secure_context.c
index 72fb3862c..3aa335e63 100644
--- a/portable/IAR/ARM_CM35P/secure/secure_context.c
+++ b/portable/IAR/ARM_CM35P/secure/secure_context.c
@@ -207,7 +207,7 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
      * securecontextNO_STACK when no secure context is loaded. */
     if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) )
     {
-        /* Ontain a free secure context. */
+        /* Obtain a free secure context. */
         ulSecureContextIndex = ulGetSecureContext( pvTaskHandle );
 
         /* Were we able to get a free context? */
diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c b/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
index 5b399358e..a33dfa43c 100644
--- a/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
@@ -56,7 +56,7 @@
  * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
  * i.e. the processor boots as secure and never jumps to the non-secure side.
  * The Trust Zone support in the port must be disabled in order to run FreeRTOS
- * on the secure side. The following are the valid configuration seetings:
+ * on the secure side. The following are the valid configuration settings:
  *
  * 1. Run FreeRTOS on the Secure Side:
  *    configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.h b/portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.h
index bd5a2bfca..b7021b024 100644
--- a/portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.h
+++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.h
@@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
  * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
  * register.
  *
- * @note This is a privileged function and should only be called from the kenrel
+ * @note This is a privileged function and should only be called from the kernel
  * code.
  *
  * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.s b/portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.s
index be06f67ad..9d6c6a7ef 100644
--- a/portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.s
+++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.s
@@ -202,7 +202,7 @@ vStartFirstTask:
 ulSetInterruptMask:
     mrs r0, basepri                         /* r0 = basepri. Return original basepri value. */
     mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY
-    msr basepri, r1                         /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+    msr basepri, r1                         /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
     dsb
     isb
     bx lr                                   /* Return. */
@@ -246,7 +246,7 @@ PendSV_Handler:
 
     select_next_task:
         mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
-        msr basepri, r0                     /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        msr basepri, r0                     /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
         dsb
         isb
         bl vTaskSwitchContext
@@ -340,7 +340,7 @@ PendSV_Handler:
     str r0, [r1]                            /* Save the new top of stack in TCB. */
 
     mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
-    msr basepri, r0                         /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+    msr basepri, r0                         /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
     dsb
     isb
     bl vTaskSwitchContext
diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
index 3cf65761f..cd83bee57 100644
--- a/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
@@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portPRIVILEGE_BIT         ( 0x0UL )
 #endif /* configENABLE_MPU */
 
-/* MPU settings that can be overriden in FreeRTOSConfig.h. */
+/* MPU settings that can be overridden in FreeRTOSConfig.h. */
 #ifndef configTOTAL_MPU_REGIONS
     /* Define to 8 for backward compatibility. */
     #define configTOTAL_MPU_REGIONS    ( 8UL )
diff --git a/portable/IAR/ARM_CM4F_MPU/portmacro.h b/portable/IAR/ARM_CM4F_MPU/portmacro.h
index f7f8b51f1..246b82dde 100644
--- a/portable/IAR/ARM_CM4F_MPU/portmacro.h
+++ b/portable/IAR/ARM_CM4F_MPU/portmacro.h
@@ -100,7 +100,7 @@ typedef unsigned long    UBaseType_t;
 #define portMPU_RASR_TEX_S_C_B_LOCATION                          ( 16UL )
 #define portMPU_RASR_TEX_S_C_B_MASK                              ( 0x3FUL )
 
-/* MPU settings that can be overriden in FreeRTOSConfig.h. */
+/* MPU settings that can be overridden in FreeRTOSConfig.h. */
 #ifndef configTOTAL_MPU_REGIONS
     /* Define to 8 for backward compatibility. */
     #define configTOTAL_MPU_REGIONS    ( 8UL )
diff --git a/portable/IAR/ARM_CM55/non_secure/port.c b/portable/IAR/ARM_CM55/non_secure/port.c
index 5b399358e..a33dfa43c 100644
--- a/portable/IAR/ARM_CM55/non_secure/port.c
+++ b/portable/IAR/ARM_CM55/non_secure/port.c
@@ -56,7 +56,7 @@
  * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
  * i.e. the processor boots as secure and never jumps to the non-secure side.
  * The Trust Zone support in the port must be disabled in order to run FreeRTOS
- * on the secure side. The following are the valid configuration seetings:
+ * on the secure side. The following are the valid configuration settings:
  *
  * 1. Run FreeRTOS on the Secure Side:
  *    configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
diff --git a/portable/IAR/ARM_CM55/non_secure/portasm.h b/portable/IAR/ARM_CM55/non_secure/portasm.h
index bd5a2bfca..b7021b024 100644
--- a/portable/IAR/ARM_CM55/non_secure/portasm.h
+++ b/portable/IAR/ARM_CM55/non_secure/portasm.h
@@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
  * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
  * register.
  *
- * @note This is a privileged function and should only be called from the kenrel
+ * @note This is a privileged function and should only be called from the kernel
  * code.
  *
  * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
diff --git a/portable/IAR/ARM_CM55/non_secure/portasm.s b/portable/IAR/ARM_CM55/non_secure/portasm.s
index f4b7ab20f..212688d61 100644
--- a/portable/IAR/ARM_CM55/non_secure/portasm.s
+++ b/portable/IAR/ARM_CM55/non_secure/portasm.s
@@ -216,7 +216,7 @@ vStartFirstTask:
 ulSetInterruptMask:
     mrs r0, basepri                         /* r0 = basepri. Return original basepri value. */
     mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY
-    msr basepri, r1                         /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+    msr basepri, r1                         /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
     dsb
     isb
     bx lr                                   /* Return. */
@@ -275,7 +275,7 @@ PendSV_Handler:
 
     select_next_task:
         mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
-        msr basepri, r0                     /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        msr basepri, r0                     /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
         dsb
         isb
         bl vTaskSwitchContext
@@ -409,7 +409,7 @@ PendSV_Handler:
 
     select_next_task:
         mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
-        msr basepri, r0                     /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        msr basepri, r0                     /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
         dsb
         isb
         bl vTaskSwitchContext
diff --git a/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h
index 3cf65761f..cd83bee57 100644
--- a/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h
@@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portPRIVILEGE_BIT         ( 0x0UL )
 #endif /* configENABLE_MPU */
 
-/* MPU settings that can be overriden in FreeRTOSConfig.h. */
+/* MPU settings that can be overridden in FreeRTOSConfig.h. */
 #ifndef configTOTAL_MPU_REGIONS
     /* Define to 8 for backward compatibility. */
     #define configTOTAL_MPU_REGIONS    ( 8UL )
diff --git a/portable/IAR/ARM_CM55/secure/secure_context.c b/portable/IAR/ARM_CM55/secure/secure_context.c
index 72fb3862c..3aa335e63 100644
--- a/portable/IAR/ARM_CM55/secure/secure_context.c
+++ b/portable/IAR/ARM_CM55/secure/secure_context.c
@@ -207,7 +207,7 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
      * securecontextNO_STACK when no secure context is loaded. */
     if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) )
     {
-        /* Ontain a free secure context. */
+        /* Obtain a free secure context. */
         ulSecureContextIndex = ulGetSecureContext( pvTaskHandle );
 
         /* Were we able to get a free context? */
diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/port.c b/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
index 5b399358e..a33dfa43c 100644
--- a/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
@@ -56,7 +56,7 @@
  * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
  * i.e. the processor boots as secure and never jumps to the non-secure side.
  * The Trust Zone support in the port must be disabled in order to run FreeRTOS
- * on the secure side. The following are the valid configuration seetings:
+ * on the secure side. The following are the valid configuration settings:
  *
  * 1. Run FreeRTOS on the Secure Side:
  *    configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.h b/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.h
index bd5a2bfca..b7021b024 100644
--- a/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.h
+++ b/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.h
@@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
  * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
  * register.
  *
- * @note This is a privileged function and should only be called from the kenrel
+ * @note This is a privileged function and should only be called from the kernel
  * code.
  *
  * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.s b/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.s
index be06f67ad..9d6c6a7ef 100644
--- a/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.s
+++ b/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.s
@@ -202,7 +202,7 @@ vStartFirstTask:
 ulSetInterruptMask:
     mrs r0, basepri                         /* r0 = basepri. Return original basepri value. */
     mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY
-    msr basepri, r1                         /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+    msr basepri, r1                         /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
     dsb
     isb
     bx lr                                   /* Return. */
@@ -246,7 +246,7 @@ PendSV_Handler:
 
     select_next_task:
         mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
-        msr basepri, r0                     /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        msr basepri, r0                     /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
         dsb
         isb
         bl vTaskSwitchContext
@@ -340,7 +340,7 @@ PendSV_Handler:
     str r0, [r1]                            /* Save the new top of stack in TCB. */
 
     mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
-    msr basepri, r0                         /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+    msr basepri, r0                         /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
     dsb
     isb
     bl vTaskSwitchContext
diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h
index 3cf65761f..cd83bee57 100644
--- a/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h
@@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portPRIVILEGE_BIT         ( 0x0UL )
 #endif /* configENABLE_MPU */
 
-/* MPU settings that can be overriden in FreeRTOSConfig.h. */
+/* MPU settings that can be overridden in FreeRTOSConfig.h. */
 #ifndef configTOTAL_MPU_REGIONS
     /* Define to 8 for backward compatibility. */
     #define configTOTAL_MPU_REGIONS    ( 8UL )
diff --git a/portable/IAR/ARM_CM85/non_secure/port.c b/portable/IAR/ARM_CM85/non_secure/port.c
index 5b399358e..a33dfa43c 100644
--- a/portable/IAR/ARM_CM85/non_secure/port.c
+++ b/portable/IAR/ARM_CM85/non_secure/port.c
@@ -56,7 +56,7 @@
  * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
  * i.e. the processor boots as secure and never jumps to the non-secure side.
  * The Trust Zone support in the port must be disabled in order to run FreeRTOS
- * on the secure side. The following are the valid configuration seetings:
+ * on the secure side. The following are the valid configuration settings:
  *
  * 1. Run FreeRTOS on the Secure Side:
  *    configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
diff --git a/portable/IAR/ARM_CM85/non_secure/portasm.h b/portable/IAR/ARM_CM85/non_secure/portasm.h
index bd5a2bfca..b7021b024 100644
--- a/portable/IAR/ARM_CM85/non_secure/portasm.h
+++ b/portable/IAR/ARM_CM85/non_secure/portasm.h
@@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
  * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
  * register.
  *
- * @note This is a privileged function and should only be called from the kenrel
+ * @note This is a privileged function and should only be called from the kernel
  * code.
  *
  * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
diff --git a/portable/IAR/ARM_CM85/non_secure/portasm.s b/portable/IAR/ARM_CM85/non_secure/portasm.s
index f4b7ab20f..212688d61 100644
--- a/portable/IAR/ARM_CM85/non_secure/portasm.s
+++ b/portable/IAR/ARM_CM85/non_secure/portasm.s
@@ -216,7 +216,7 @@ vStartFirstTask:
 ulSetInterruptMask:
     mrs r0, basepri                         /* r0 = basepri. Return original basepri value. */
     mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY
-    msr basepri, r1                         /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+    msr basepri, r1                         /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
     dsb
     isb
     bx lr                                   /* Return. */
@@ -275,7 +275,7 @@ PendSV_Handler:
 
     select_next_task:
         mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
-        msr basepri, r0                     /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        msr basepri, r0                     /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
         dsb
         isb
         bl vTaskSwitchContext
@@ -409,7 +409,7 @@ PendSV_Handler:
 
     select_next_task:
         mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
-        msr basepri, r0                     /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        msr basepri, r0                     /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
         dsb
         isb
         bl vTaskSwitchContext
diff --git a/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h
index 3cf65761f..cd83bee57 100644
--- a/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h
@@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portPRIVILEGE_BIT         ( 0x0UL )
 #endif /* configENABLE_MPU */
 
-/* MPU settings that can be overriden in FreeRTOSConfig.h. */
+/* MPU settings that can be overridden in FreeRTOSConfig.h. */
 #ifndef configTOTAL_MPU_REGIONS
     /* Define to 8 for backward compatibility. */
     #define configTOTAL_MPU_REGIONS    ( 8UL )
diff --git a/portable/IAR/ARM_CM85/secure/secure_context.c b/portable/IAR/ARM_CM85/secure/secure_context.c
index 72fb3862c..3aa335e63 100644
--- a/portable/IAR/ARM_CM85/secure/secure_context.c
+++ b/portable/IAR/ARM_CM85/secure/secure_context.c
@@ -207,7 +207,7 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
      * securecontextNO_STACK when no secure context is loaded. */
     if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) )
     {
-        /* Ontain a free secure context. */
+        /* Obtain a free secure context. */
         ulSecureContextIndex = ulGetSecureContext( pvTaskHandle );
 
         /* Were we able to get a free context? */
diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/port.c b/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
index 5b399358e..a33dfa43c 100644
--- a/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
@@ -56,7 +56,7 @@
  * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
  * i.e. the processor boots as secure and never jumps to the non-secure side.
  * The Trust Zone support in the port must be disabled in order to run FreeRTOS
- * on the secure side. The following are the valid configuration seetings:
+ * on the secure side. The following are the valid configuration settings:
  *
  * 1. Run FreeRTOS on the Secure Side:
  *    configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.h b/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.h
index bd5a2bfca..b7021b024 100644
--- a/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.h
+++ b/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.h
@@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
  * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
  * register.
  *
- * @note This is a privileged function and should only be called from the kenrel
+ * @note This is a privileged function and should only be called from the kernel
  * code.
  *
  * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.s b/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.s
index be06f67ad..9d6c6a7ef 100644
--- a/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.s
+++ b/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.s
@@ -202,7 +202,7 @@ vStartFirstTask:
 ulSetInterruptMask:
     mrs r0, basepri                         /* r0 = basepri. Return original basepri value. */
     mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY
-    msr basepri, r1                         /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+    msr basepri, r1                         /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
     dsb
     isb
     bx lr                                   /* Return. */
@@ -246,7 +246,7 @@ PendSV_Handler:
 
     select_next_task:
         mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
-        msr basepri, r0                     /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        msr basepri, r0                     /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
         dsb
         isb
         bl vTaskSwitchContext
@@ -340,7 +340,7 @@ PendSV_Handler:
     str r0, [r1]                            /* Save the new top of stack in TCB. */
 
     mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
-    msr basepri, r0                         /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+    msr basepri, r0                         /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
     dsb
     isb
     bl vTaskSwitchContext
diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h
index 3cf65761f..cd83bee57 100644
--- a/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h
@@ -137,7 +137,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portPRIVILEGE_BIT         ( 0x0UL )
 #endif /* configENABLE_MPU */
 
-/* MPU settings that can be overriden in FreeRTOSConfig.h. */
+/* MPU settings that can be overridden in FreeRTOSConfig.h. */
 #ifndef configTOTAL_MPU_REGIONS
     /* Define to 8 for backward compatibility. */
     #define configTOTAL_MPU_REGIONS    ( 8UL )
diff --git a/portable/IAR/AVR32_UC3/port.c b/portable/IAR/AVR32_UC3/port.c
index 7a1cc640b..dbe121cca 100644
--- a/portable/IAR/AVR32_UC3/port.c
+++ b/portable/IAR/AVR32_UC3/port.c
@@ -374,7 +374,7 @@ static void prvSetupTimerInterrupt( void )
     #if ( configTICK_USE_TC == 1 )
         volatile avr32_tc_t * tc = &AVR32_TC;
 
-        /* Options for waveform genration. */
+        /* Options for waveform generation. */
         tc_waveform_opt_t waveform_opt =
         {
             .channel = configTICK_TC_CHANNEL,              /* Channel selection. */
diff --git a/portable/IAR/AtmelSAM7S64/AT91SAM7S64.h b/portable/IAR/AtmelSAM7S64/AT91SAM7S64.h
index 2dbceba43..6df767884 100644
--- a/portable/IAR/AtmelSAM7S64/AT91SAM7S64.h
+++ b/portable/IAR/AtmelSAM7S64/AT91SAM7S64.h
@@ -562,8 +562,8 @@ typedef struct _AT91S_MC
 /* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */
 #define AT91C_MC_RCB                       ( ( unsigned int ) 0x1 << 0 )   /* (MC) Remap Command Bit */
 /* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */
-#define AT91C_MC_UNDADD                    ( ( unsigned int ) 0x1 << 0 )   /* (MC) Undefined Addess Abort Status */
-#define AT91C_MC_MISADD                    ( ( unsigned int ) 0x1 << 1 )   /* (MC) Misaligned Addess Abort Status */
+#define AT91C_MC_UNDADD                    ( ( unsigned int ) 0x1 << 0 )   /* (MC) Undefined Address Abort Status */
+#define AT91C_MC_MISADD                    ( ( unsigned int ) 0x1 << 1 )   /* (MC) Misaligned Address Abort Status */
 #define AT91C_MC_ABTSZ                     ( ( unsigned int ) 0x3 << 8 )   /* (MC) Abort Size Status */
 #define     AT91C_MC_ABTSZ_BYTE            ( ( unsigned int ) 0x0 << 8 )   /* (MC) Byte */
 #define     AT91C_MC_ABTSZ_HWORD           ( ( unsigned int ) 0x1 << 8 )   /* (MC) Half-word */
diff --git a/portable/IAR/AtmelSAM7S64/AT91SAM7S64_inc.h b/portable/IAR/AtmelSAM7S64/AT91SAM7S64_inc.h
index 9d95f3eb7..a39150071 100644
--- a/portable/IAR/AtmelSAM7S64/AT91SAM7S64_inc.h
+++ b/portable/IAR/AtmelSAM7S64/AT91SAM7S64_inc.h
@@ -487,8 +487,8 @@
 /* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */
 #define AT91C_MC_RCB                       ( 0x1 << 0 )   /* (MC) Remap Command Bit */
 /* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */
-#define AT91C_MC_UNDADD                    ( 0x1 << 0 )   /* (MC) Undefined Addess Abort Status */
-#define AT91C_MC_MISADD                    ( 0x1 << 1 )   /* (MC) Misaligned Addess Abort Status */
+#define AT91C_MC_UNDADD                    ( 0x1 << 0 )   /* (MC) Undefined Address Abort Status */
+#define AT91C_MC_MISADD                    ( 0x1 << 1 )   /* (MC) Misaligned Address Abort Status */
 #define AT91C_MC_ABTSZ                     ( 0x3 << 8 )   /* (MC) Abort Size Status */
 #define     AT91C_MC_ABTSZ_BYTE            ( 0x0 << 8 )   /* (MC) Byte */
 #define     AT91C_MC_ABTSZ_HWORD           ( 0x1 << 8 )   /* (MC) Half-word */
diff --git a/portable/IAR/AtmelSAM7S64/AT91SAM7X128.h b/portable/IAR/AtmelSAM7S64/AT91SAM7X128.h
index b8a7652f4..a143430db 100644
--- a/portable/IAR/AtmelSAM7S64/AT91SAM7X128.h
+++ b/portable/IAR/AtmelSAM7S64/AT91SAM7X128.h
@@ -627,8 +627,8 @@ typedef struct _AT91S_MC
 /* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */
 #define AT91C_MC_RCB                       ( ( unsigned int ) 0x1 << 0 )   /* (MC) Remap Command Bit */
 /* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */
-#define AT91C_MC_UNDADD                    ( ( unsigned int ) 0x1 << 0 )   /* (MC) Undefined Addess Abort Status */
-#define AT91C_MC_MISADD                    ( ( unsigned int ) 0x1 << 1 )   /* (MC) Misaligned Addess Abort Status */
+#define AT91C_MC_UNDADD                    ( ( unsigned int ) 0x1 << 0 )   /* (MC) Undefined Address Abort Status */
+#define AT91C_MC_MISADD                    ( ( unsigned int ) 0x1 << 1 )   /* (MC) Misaligned Address Abort Status */
 #define AT91C_MC_ABTSZ                     ( ( unsigned int ) 0x3 << 8 )   /* (MC) Abort Size Status */
 #define     AT91C_MC_ABTSZ_BYTE            ( ( unsigned int ) 0x0 << 8 )   /* (MC) Byte */
 #define     AT91C_MC_ABTSZ_HWORD           ( ( unsigned int ) 0x1 << 8 )   /* (MC) Half-word */
@@ -1509,7 +1509,7 @@ typedef struct _AT91S_EMAC
     AT91_REG EMAC_ECOL;       /* Excessive Collision Register */
     AT91_REG EMAC_TUND;       /* Transmit Underrun Error Register */
     AT91_REG EMAC_CSE;        /* Carrier Sense Error Register */
-    AT91_REG EMAC_RRE;        /* Receive Ressource Error Register */
+    AT91_REG EMAC_RRE;        /* Receive Resource Error Register */
     AT91_REG EMAC_ROV;        /* Receive Overrun Errors Register */
     AT91_REG EMAC_RSE;        /* Receive Symbol Errors Register */
     AT91_REG EMAC_ELE;        /* Excessive Length Errors Register */
@@ -2393,7 +2393,7 @@ typedef struct _AT91S_TDES
 #define AT91C_EMAC_SA1H            ( ( AT91_REG * ) 0xFFFDC09C ) /* (EMAC) Specific Address 1 Top, Last 2 bytes */
 #define AT91C_EMAC_CSE             ( ( AT91_REG * ) 0xFFFDC068 ) /* (EMAC) Carrier Sense Error Register */
 #define AT91C_EMAC_SA3H            ( ( AT91_REG * ) 0xFFFDC0AC ) /* (EMAC) Specific Address 3 Top, Last 2 bytes */
-#define AT91C_EMAC_RRE             ( ( AT91_REG * ) 0xFFFDC06C ) /* (EMAC) Receive Ressource Error Register */
+#define AT91C_EMAC_RRE             ( ( AT91_REG * ) 0xFFFDC06C ) /* (EMAC) Receive Resource Error Register */
 #define AT91C_EMAC_STE             ( ( AT91_REG * ) 0xFFFDC084 ) /* (EMAC) SQE Test Error Register */
 /* ========== Register definition for PDC_ADC peripheral ========== */
 #define AT91C_ADC_PTSR             ( ( AT91_REG * ) 0xFFFD8124 ) /* (PDC_ADC) PDC Transfer Status Register */
diff --git a/portable/IAR/AtmelSAM7S64/AT91SAM7X128_inc.h b/portable/IAR/AtmelSAM7S64/AT91SAM7X128_inc.h
index fe701970e..78ea37595 100644
--- a/portable/IAR/AtmelSAM7S64/AT91SAM7X128_inc.h
+++ b/portable/IAR/AtmelSAM7S64/AT91SAM7X128_inc.h
@@ -411,8 +411,8 @@
 /* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */
 #define AT91C_MC_RCB                       ( 0x1 << 0 )   /* (MC) Remap Command Bit */
 /* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */
-#define AT91C_MC_UNDADD                    ( 0x1 << 0 )   /* (MC) Undefined Addess Abort Status */
-#define AT91C_MC_MISADD                    ( 0x1 << 1 )   /* (MC) Misaligned Addess Abort Status */
+#define AT91C_MC_UNDADD                    ( 0x1 << 0 )   /* (MC) Undefined Address Abort Status */
+#define AT91C_MC_MISADD                    ( 0x1 << 1 )   /* (MC) Misaligned Address Abort Status */
 #define AT91C_MC_ABTSZ                     ( 0x3 << 8 )   /* (MC) Abort Size Status */
 #define     AT91C_MC_ABTSZ_BYTE            ( 0x0 << 8 )   /* (MC) Byte */
 #define     AT91C_MC_ABTSZ_HWORD           ( 0x1 << 8 )   /* (MC) Half-word */
@@ -1234,7 +1234,7 @@
 #define EMAC_ECOL                       ( 96 )        /* Excessive Collision Register */
 #define EMAC_TUND                       ( 100 )       /* Transmit Underrun Error Register */
 #define EMAC_CSE                        ( 104 )       /* Carrier Sense Error Register */
-#define EMAC_RRE                        ( 108 )       /* Receive Ressource Error Register */
+#define EMAC_RRE                        ( 108 )       /* Receive Resource Error Register */
 #define EMAC_ROV                        ( 112 )       /* Receive Overrun Errors Register */
 #define EMAC_RSE                        ( 116 )       /* Receive Symbol Errors Register */
 #define EMAC_ELE                        ( 120 )       /* Excessive Length Errors Register */
@@ -2096,7 +2096,7 @@
 #define AT91C_EMAC_SA1H            ( 0xFFFDC09C ) /* (EMAC) Specific Address 1 Top, Last 2 bytes */
 #define AT91C_EMAC_CSE             ( 0xFFFDC068 ) /* (EMAC) Carrier Sense Error Register */
 #define AT91C_EMAC_SA3H            ( 0xFFFDC0AC ) /* (EMAC) Specific Address 3 Top, Last 2 bytes */
-#define AT91C_EMAC_RRE             ( 0xFFFDC06C ) /* (EMAC) Receive Ressource Error Register */
+#define AT91C_EMAC_RRE             ( 0xFFFDC06C ) /* (EMAC) Receive Resource Error Register */
 #define AT91C_EMAC_STE             ( 0xFFFDC084 ) /* (EMAC) SQE Test Error Register */
 /* ========== Register definition for PDC_ADC peripheral ========== */
 #define AT91C_ADC_PTSR             ( 0xFFFD8124 ) /* (PDC_ADC) PDC Transfer Status Register */
diff --git a/portable/IAR/AtmelSAM7S64/AT91SAM7X256.h b/portable/IAR/AtmelSAM7S64/AT91SAM7X256.h
index 98e1babc2..f51209974 100644
--- a/portable/IAR/AtmelSAM7S64/AT91SAM7X256.h
+++ b/portable/IAR/AtmelSAM7S64/AT91SAM7X256.h
@@ -627,8 +627,8 @@ typedef struct _AT91S_MC
 /* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */
 #define AT91C_MC_RCB                       ( ( unsigned int ) 0x1 << 0 )   /* (MC) Remap Command Bit */
 /* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */
-#define AT91C_MC_UNDADD                    ( ( unsigned int ) 0x1 << 0 )   /* (MC) Undefined Addess Abort Status */
-#define AT91C_MC_MISADD                    ( ( unsigned int ) 0x1 << 1 )   /* (MC) Misaligned Addess Abort Status */
+#define AT91C_MC_UNDADD                    ( ( unsigned int ) 0x1 << 0 )   /* (MC) Undefined Address Abort Status */
+#define AT91C_MC_MISADD                    ( ( unsigned int ) 0x1 << 1 )   /* (MC) Misaligned Address Abort Status */
 #define AT91C_MC_ABTSZ                     ( ( unsigned int ) 0x3 << 8 )   /* (MC) Abort Size Status */
 #define     AT91C_MC_ABTSZ_BYTE            ( ( unsigned int ) 0x0 << 8 )   /* (MC) Byte */
 #define     AT91C_MC_ABTSZ_HWORD           ( ( unsigned int ) 0x1 << 8 )   /* (MC) Half-word */
@@ -1509,7 +1509,7 @@ typedef struct _AT91S_EMAC
     AT91_REG EMAC_ECOL;       /* Excessive Collision Register */
     AT91_REG EMAC_TUND;       /* Transmit Underrun Error Register */
     AT91_REG EMAC_CSE;        /* Carrier Sense Error Register */
-    AT91_REG EMAC_RRE;        /* Receive Ressource Error Register */
+    AT91_REG EMAC_RRE;        /* Receive Resource Error Register */
     AT91_REG EMAC_ROV;        /* Receive Overrun Errors Register */
     AT91_REG EMAC_RSE;        /* Receive Symbol Errors Register */
     AT91_REG EMAC_ELE;        /* Excessive Length Errors Register */
@@ -2393,7 +2393,7 @@ typedef struct _AT91S_TDES
 #define AT91C_EMAC_SA1H            ( ( AT91_REG * ) 0xFFFDC09C ) /* (EMAC) Specific Address 1 Top, Last 2 bytes */
 #define AT91C_EMAC_CSE             ( ( AT91_REG * ) 0xFFFDC068 ) /* (EMAC) Carrier Sense Error Register */
 #define AT91C_EMAC_SA3H            ( ( AT91_REG * ) 0xFFFDC0AC ) /* (EMAC) Specific Address 3 Top, Last 2 bytes */
-#define AT91C_EMAC_RRE             ( ( AT91_REG * ) 0xFFFDC06C ) /* (EMAC) Receive Ressource Error Register */
+#define AT91C_EMAC_RRE             ( ( AT91_REG * ) 0xFFFDC06C ) /* (EMAC) Receive Resource Error Register */
 #define AT91C_EMAC_STE             ( ( AT91_REG * ) 0xFFFDC084 ) /* (EMAC) SQE Test Error Register */
 /* ========== Register definition for PDC_ADC peripheral ========== */
 #define AT91C_ADC_PTSR             ( ( AT91_REG * ) 0xFFFD8124 ) /* (PDC_ADC) PDC Transfer Status Register */
diff --git a/portable/IAR/AtmelSAM7S64/AT91SAM7X256_inc.h b/portable/IAR/AtmelSAM7S64/AT91SAM7X256_inc.h
index 5c0be5efc..8471ca44d 100644
--- a/portable/IAR/AtmelSAM7S64/AT91SAM7X256_inc.h
+++ b/portable/IAR/AtmelSAM7S64/AT91SAM7X256_inc.h
@@ -411,8 +411,8 @@
 /* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */
 #define AT91C_MC_RCB                       ( 0x1 << 0 )   /* (MC) Remap Command Bit */
 /* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */
-#define AT91C_MC_UNDADD                    ( 0x1 << 0 )   /* (MC) Undefined Addess Abort Status */
-#define AT91C_MC_MISADD                    ( 0x1 << 1 )   /* (MC) Misaligned Addess Abort Status */
+#define AT91C_MC_UNDADD                    ( 0x1 << 0 )   /* (MC) Undefined Address Abort Status */
+#define AT91C_MC_MISADD                    ( 0x1 << 1 )   /* (MC) Misaligned Address Abort Status */
 #define AT91C_MC_ABTSZ                     ( 0x3 << 8 )   /* (MC) Abort Size Status */
 #define     AT91C_MC_ABTSZ_BYTE            ( 0x0 << 8 )   /* (MC) Byte */
 #define     AT91C_MC_ABTSZ_HWORD           ( 0x1 << 8 )   /* (MC) Half-word */
@@ -1234,7 +1234,7 @@
 #define EMAC_ECOL                       ( 96 )        /* Excessive Collision Register */
 #define EMAC_TUND                       ( 100 )       /* Transmit Underrun Error Register */
 #define EMAC_CSE                        ( 104 )       /* Carrier Sense Error Register */
-#define EMAC_RRE                        ( 108 )       /* Receive Ressource Error Register */
+#define EMAC_RRE                        ( 108 )       /* Receive Resource Error Register */
 #define EMAC_ROV                        ( 112 )       /* Receive Overrun Errors Register */
 #define EMAC_RSE                        ( 116 )       /* Receive Symbol Errors Register */
 #define EMAC_ELE                        ( 120 )       /* Excessive Length Errors Register */
@@ -2096,7 +2096,7 @@
 #define AT91C_EMAC_SA1H            ( 0xFFFDC09C ) /* (EMAC) Specific Address 1 Top, Last 2 bytes */
 #define AT91C_EMAC_CSE             ( 0xFFFDC068 ) /* (EMAC) Carrier Sense Error Register */
 #define AT91C_EMAC_SA3H            ( 0xFFFDC0AC ) /* (EMAC) Specific Address 3 Top, Last 2 bytes */
-#define AT91C_EMAC_RRE             ( 0xFFFDC06C ) /* (EMAC) Receive Ressource Error Register */
+#define AT91C_EMAC_RRE             ( 0xFFFDC06C ) /* (EMAC) Receive Resource Error Register */
 #define AT91C_EMAC_STE             ( 0xFFFDC084 ) /* (EMAC) SQE Test Error Register */
 /* ========== Register definition for PDC_ADC peripheral ========== */
 #define AT91C_ADC_PTSR             ( 0xFFFD8124 ) /* (PDC_ADC) PDC Transfer Status Register */
diff --git a/portable/IAR/AtmelSAM7S64/lib_AT91SAM7S64.h b/portable/IAR/AtmelSAM7S64/lib_AT91SAM7S64.h
index a392be1a7..c53e6c8af 100644
--- a/portable/IAR/AtmelSAM7S64/lib_AT91SAM7S64.h
+++ b/portable/IAR/AtmelSAM7S64/lib_AT91SAM7S64.h
@@ -60,7 +60,7 @@ __inline void AT91F_MC_EFC_CfgModeReg( AT91PS_MC pMC,      /* pointer to a MC co
 
 /**---------------------------------------------------------------------------- */
 /** \fn    AT91F_MC_EFC_GetModeReg */
-/** \brief Return MC EFC Mode Regsiter */
+/** \brief Return MC EFC Mode Register */
 /**---------------------------------------------------------------------------- */
 __inline unsigned int AT91F_MC_EFC_GetModeReg( AT91PS_MC pMC ) /* pointer to a MC controller */
 {
@@ -69,7 +69,7 @@ __inline unsigned int AT91F_MC_EFC_GetModeReg( AT91PS_MC pMC ) /* pointer to a M
 
 /**---------------------------------------------------------------------------- */
 /** \fn    AT91F_MC_EFC_ComputeFMCN */
-/** \brief Return MC EFC Mode Regsiter */
+/** \brief Return MC EFC Mode Register */
 /**---------------------------------------------------------------------------- */
 __inline unsigned int AT91F_MC_EFC_ComputeFMCN( int master_clock ) /* master clock in Hz */
 {
@@ -123,7 +123,7 @@ __inline unsigned int AT91F_MC_EFC_IsInterruptSet( AT91PS_MC pMC,      /* \arg
 /** \brief Set the next receive transfer descriptor */
 /**---------------------------------------------------------------------------- */
 __inline void AT91F_PDC_SetNextRx( AT91PS_PDC pPDC,     /* \arg pointer to a PDC controller */
-                                   char * address,      /* \arg address to the next bloc to be received */
+                                   char * address,      /* \arg address to the next block to be received */
                                    unsigned int bytes ) /* \arg number of bytes to be received */
 {
     pPDC->PDC_RNPR = ( unsigned int ) address;
@@ -135,7 +135,7 @@ __inline void AT91F_PDC_SetNextRx( AT91PS_PDC pPDC,     /* \arg pointer to a PDC
 /** \brief Set the next transmit transfer descriptor */
 /**---------------------------------------------------------------------------- */
 __inline void AT91F_PDC_SetNextTx( AT91PS_PDC pPDC,     /* \arg pointer to a PDC controller */
-                                   char * address,      /* \arg address to the next bloc to be transmitted */
+                                   char * address,      /* \arg address to the next block to be transmitted */
                                    unsigned int bytes ) /* \arg number of bytes to be transmitted */
 {
     pPDC->PDC_TNPR = ( unsigned int ) address;
@@ -147,7 +147,7 @@ __inline void AT91F_PDC_SetNextTx( AT91PS_PDC pPDC,     /* \arg pointer to a PDC
 /** \brief Set the receive transfer descriptor */
 /**---------------------------------------------------------------------------- */
 __inline void AT91F_PDC_SetRx( AT91PS_PDC pPDC,     /* \arg pointer to a PDC controller */
-                               char * address,      /* \arg address to the next bloc to be received */
+                               char * address,      /* \arg address to the next block to be received */
                                unsigned int bytes ) /* \arg number of bytes to be received */
 {
     pPDC->PDC_RPR = ( unsigned int ) address;
@@ -159,7 +159,7 @@ __inline void AT91F_PDC_SetRx( AT91PS_PDC pPDC,     /* \arg pointer to a PDC con
 /** \brief Set the transmit transfer descriptor */
 /**---------------------------------------------------------------------------- */
 __inline void AT91F_PDC_SetTx( AT91PS_PDC pPDC,     /* \arg pointer to a PDC controller */
-                               char * address,      /* \arg address to the next bloc to be transmitted */
+                               char * address,      /* \arg address to the next block to be transmitted */
                                unsigned int bytes ) /* \arg number of bytes to be transmitted */
 {
     pPDC->PDC_TPR = ( unsigned int ) address;
@@ -742,7 +742,7 @@ __inline unsigned int AT91F_SPI_SendFrame( AT91PS_SPI pSPI,
 
 /**---------------------------------------------------------------------------- */
 /** \fn    AT91F_SPI_Close */
-/** \brief Close SPI: disable IT disable transfert, close PDC */
+/** \brief Close SPI: disable IT disable transfer, close PDC */
 /**---------------------------------------------------------------------------- */
 __inline void AT91F_SPI_Close( AT91PS_SPI pSPI ) /* \arg pointer to a SPI controller */
 {
@@ -1063,7 +1063,7 @@ __inline void AT91F_CKGR_DisableMainOscillator( AT91PS_CKGR pCKGR ) /* \arg poin
 
 /**---------------------------------------------------------------------------- */
 /** \fn    AT91F_CKGR_CfgMainOscStartUpTime */
-/** \brief Cfg MOR Register according to the main osc startup time */
+/** \brief Cfg MORE Register according to the main osc startup time */
 /**---------------------------------------------------------------------------- */
 __inline void AT91F_CKGR_CfgMainOscStartUpTime( AT91PS_CKGR pCKGR,         /* \arg pointer to CKGR controller */
                                                 unsigned int startup_time, /* \arg main osc startup time in microsecond (us) */
diff --git a/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X128.h b/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X128.h
index 61fbb1f79..4fc975894 100644
--- a/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X128.h
+++ b/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X128.h
@@ -210,7 +210,7 @@
 /** \brief Set the next receive transfer descriptor */
 /**---------------------------------------------------------------------------- */
     __inline void AT91F_PDC_SetNextRx( AT91PS_PDC pPDC,     /* \arg pointer to a PDC controller */
-                                       char * address,      /* \arg address to the next bloc to be received */
+                                       char * address,      /* \arg address to the next block to be received */
                                        unsigned int bytes ) /* \arg number of bytes to be received */
     {
         pPDC->PDC_RNPR = ( unsigned int ) address;
@@ -222,7 +222,7 @@
 /** \brief Set the next transmit transfer descriptor */
 /**---------------------------------------------------------------------------- */
     __inline void AT91F_PDC_SetNextTx( AT91PS_PDC pPDC,     /* \arg pointer to a PDC controller */
-                                       char * address,      /* \arg address to the next bloc to be transmitted */
+                                       char * address,      /* \arg address to the next block to be transmitted */
                                        unsigned int bytes ) /* \arg number of bytes to be transmitted */
     {
         pPDC->PDC_TNPR = ( unsigned int ) address;
@@ -234,7 +234,7 @@
 /** \brief Set the receive transfer descriptor */
 /**---------------------------------------------------------------------------- */
     __inline void AT91F_PDC_SetRx( AT91PS_PDC pPDC,     /* \arg pointer to a PDC controller */
-                                   char * address,      /* \arg address to the next bloc to be received */
+                                   char * address,      /* \arg address to the next block to be received */
                                    unsigned int bytes ) /* \arg number of bytes to be received */
     {
         pPDC->PDC_RPR = ( unsigned int ) address;
@@ -246,7 +246,7 @@
 /** \brief Set the transmit transfer descriptor */
 /**---------------------------------------------------------------------------- */
     __inline void AT91F_PDC_SetTx( AT91PS_PDC pPDC,     /* \arg pointer to a PDC controller */
-                                   char * address,      /* \arg address to the next bloc to be transmitted */
+                                   char * address,      /* \arg address to the next block to be transmitted */
                                    unsigned int bytes ) /* \arg number of bytes to be transmitted */
     {
         pPDC->PDC_TPR = ( unsigned int ) address;
@@ -1054,7 +1054,7 @@
 
 /**---------------------------------------------------------------------------- */
 /** \fn    AT91F_CKGR_CfgMainOscStartUpTime */
-/** \brief Cfg MOR Register according to the main osc startup time */
+/** \brief Cfg MORE Register according to the main osc startup time */
 /**---------------------------------------------------------------------------- */
     __inline void AT91F_CKGR_CfgMainOscStartUpTime( AT91PS_CKGR pCKGR,         /* \arg pointer to CKGR controller */
                                                     unsigned int startup_time, /* \arg main osc startup time in microsecond (us) */
diff --git a/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X256.h b/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X256.h
index 0d9a70884..4ac85fb96 100644
--- a/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X256.h
+++ b/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X256.h
@@ -210,7 +210,7 @@
 /** \brief Set the next receive transfer descriptor */
 /**---------------------------------------------------------------------------- */
     __inline void AT91F_PDC_SetNextRx( AT91PS_PDC pPDC,     /* \arg pointer to a PDC controller */
-                                       char * address,      /* \arg address to the next bloc to be received */
+                                       char * address,      /* \arg address to the next block to be received */
                                        unsigned int bytes ) /* \arg number of bytes to be received */
     {
         pPDC->PDC_RNPR = ( unsigned int ) address;
@@ -222,7 +222,7 @@
 /** \brief Set the next transmit transfer descriptor */
 /**---------------------------------------------------------------------------- */
     __inline void AT91F_PDC_SetNextTx( AT91PS_PDC pPDC,     /* \arg pointer to a PDC controller */
-                                       char * address,      /* \arg address to the next bloc to be transmitted */
+                                       char * address,      /* \arg address to the next block to be transmitted */
                                        unsigned int bytes ) /* \arg number of bytes to be transmitted */
     {
         pPDC->PDC_TNPR = ( unsigned int ) address;
@@ -234,7 +234,7 @@
 /** \brief Set the receive transfer descriptor */
 /**---------------------------------------------------------------------------- */
     __inline void AT91F_PDC_SetRx( AT91PS_PDC pPDC,     /* \arg pointer to a PDC controller */
-                                   char * address,      /* \arg address to the next bloc to be received */
+                                   char * address,      /* \arg address to the next block to be received */
                                    unsigned int bytes ) /* \arg number of bytes to be received */
     {
         pPDC->PDC_RPR = ( unsigned int ) address;
@@ -246,7 +246,7 @@
 /** \brief Set the transmit transfer descriptor */
 /**---------------------------------------------------------------------------- */
     __inline void AT91F_PDC_SetTx( AT91PS_PDC pPDC,     /* \arg pointer to a PDC controller */
-                                   char * address,      /* \arg address to the next bloc to be transmitted */
+                                   char * address,      /* \arg address to the next block to be transmitted */
                                    unsigned int bytes ) /* \arg number of bytes to be transmitted */
     {
         pPDC->PDC_TPR = ( unsigned int ) address;
@@ -1054,7 +1054,7 @@
 
 /**---------------------------------------------------------------------------- */
 /** \fn    AT91F_CKGR_CfgMainOscStartUpTime */
-/** \brief Cfg MOR Register according to the main osc startup time */
+/** \brief Cfg MORE Register according to the main osc startup time */
 /**---------------------------------------------------------------------------- */
     __inline void AT91F_CKGR_CfgMainOscStartUpTime( AT91PS_CKGR pCKGR,         /* \arg pointer to CKGR controller */
                                                     unsigned int startup_time, /* \arg main osc startup time in microsecond (us) */
diff --git a/portable/MPLAB/PIC24_dsPIC/port.c b/portable/MPLAB/PIC24_dsPIC/port.c
index 0299ec0ee..f309128e5 100644
--- a/portable/MPLAB/PIC24_dsPIC/port.c
+++ b/portable/MPLAB/PIC24_dsPIC/port.c
@@ -45,7 +45,7 @@
 #define portTIMER_PRESCALE 8
 #define portINITIAL_SR  0
 
-/* Defined for backward compatability with project created prior to
+/* Defined for backward compatibility with project created prior to
 FreeRTOS.org V4.3.0. */
 #ifndef configKERNEL_INTERRUPT_PRIORITY
     #define configKERNEL_INTERRUPT_PRIORITY 1
diff --git a/portable/RVDS/ARM_CA9/port.c b/portable/RVDS/ARM_CA9/port.c
index c89232644..7ef38f399 100644
--- a/portable/RVDS/ARM_CA9/port.c
+++ b/portable/RVDS/ARM_CA9/port.c
@@ -476,7 +476,7 @@ uint32_t ulPortSetInterruptMask( void )
          * this is not the case (if some bits represent a sub-priority).
          *
          * The priority grouping is configured by the GIC's binary point register
-         * (ICCBPR).  Writting 0 to ICCBPR will ensure it is set to its lowest
+         * (ICCBPR).  Writing 0 to ICCBPR will ensure it is set to its lowest
          * possible value (which may be above 0). */
         configASSERT( portICCBPR_BINARY_POINT_REGISTER <= portMAX_BINARY_POINT_VALUE );
     }
diff --git a/portable/RVDS/ARM_CM4_MPU/portmacro.h b/portable/RVDS/ARM_CM4_MPU/portmacro.h
index 1faeffd27..005e00503 100644
--- a/portable/RVDS/ARM_CM4_MPU/portmacro.h
+++ b/portable/RVDS/ARM_CM4_MPU/portmacro.h
@@ -97,7 +97,7 @@ typedef unsigned long    UBaseType_t;
 #define portMPU_RASR_TEX_S_C_B_LOCATION                          ( 16UL )
 #define portMPU_RASR_TEX_S_C_B_MASK                              ( 0x3FUL )
 
-/* MPU settings that can be overriden in FreeRTOSConfig.h. */
+/* MPU settings that can be overridden in FreeRTOSConfig.h. */
 #ifndef configTOTAL_MPU_REGIONS
     /* Define to 8 for backward compatibility. */
     #define configTOTAL_MPU_REGIONS    ( 8UL )
diff --git a/portable/ThirdParty/GCC/ARC_EM_HS/port.c b/portable/ThirdParty/GCC/ARC_EM_HS/port.c
index 0e023088e..7837f8f73 100644
--- a/portable/ThirdParty/GCC/ARC_EM_HS/port.c
+++ b/portable/ThirdParty/GCC/ARC_EM_HS/port.c
@@ -204,7 +204,7 @@ void vPortEndTask( void )
 /*
  * !!! Note !!!
  * This a trick!!!
- * It's a copy from task.c. We need to konw the definition of TCB for the purpose of hardware
+ * It's a copy from task.c. We need to know the definition of TCB for the purpose of hardware
  * stack check. Pls don't forget to update it when FreeRTOS is updated.
  */
     typedef struct tskTaskControlBlock       /* The old naming convention is used to prevent breaking kernel aware debuggers. */
diff --git a/portable/ThirdParty/GCC/ARC_v1/port.c b/portable/ThirdParty/GCC/ARC_v1/port.c
index 728cd6fac..39e8b771b 100644
--- a/portable/ThirdParty/GCC/ARC_v1/port.c
+++ b/portable/ThirdParty/GCC/ARC_v1/port.c
@@ -204,7 +204,7 @@ void vPortEndTask( void )
 /*
  * !!! Note !!!
  * This a trick!!!
- * It's a copy from task.c. We need to konw the definition of TCB for the purpose of hardware
+ * It's a copy from task.c. We need to know the definition of TCB for the purpose of hardware
  * stack check. Pls don't forget to update it when FreeRTOS is updated.
  */
     typedef struct tskTaskControlBlock       /* The old naming convention is used to prevent breaking kernel aware debuggers. */
diff --git a/portable/ThirdParty/GCC/Posix/port.c b/portable/ThirdParty/GCC/Posix/port.c
index b11e9017f..1bec7afd8 100644
--- a/portable/ThirdParty/GCC/Posix/port.c
+++ b/portable/ThirdParty/GCC/Posix/port.c
@@ -242,7 +242,7 @@ BaseType_t xPortStartScheduler( void )
     xSchedulerEnd = pdFALSE;
 
     /* Reset pthread_once_t, needed to restart the scheduler again.
-     * memset the internal struct members for MacOS/Linux Compatability */
+     * memset the internal struct members for MacOS/Linux Compatibility */
     #if __APPLE__
         hSigSetupThread.__sig = _PTHREAD_ONCE_SIG_init;
         memset( ( void * ) &hSigSetupThread.__opaque, 0, sizeof(hSigSetupThread.__opaque));
diff --git a/portable/ThirdParty/GCC/Posix/portmacro.h b/portable/ThirdParty/GCC/Posix/portmacro.h
index d1e35d125..e117749fe 100644
--- a/portable/ThirdParty/GCC/Posix/portmacro.h
+++ b/portable/ThirdParty/GCC/Posix/portmacro.h
@@ -135,7 +135,7 @@ extern void vPortCancelThread( void * pxTaskToDelete );
  * are always a full memory barrier. ISRs are emulated as signals
  * which also imply a full memory barrier.
  *
- * Thus, only a compilier barrier is needed to prevent the compiler
+ * Thus, only a compiler barrier is needed to prevent the compiler
  * reordering.
  */
 #define portMEMORY_BARRIER()                        __asm volatile ( "" ::: "memory" )
diff --git a/portable/ThirdParty/GCC/RP2040/include/portmacro.h b/portable/ThirdParty/GCC/RP2040/include/portmacro.h
index bf91eda36..023250884 100644
--- a/portable/ThirdParty/GCC/RP2040/include/portmacro.h
+++ b/portable/ThirdParty/GCC/RP2040/include/portmacro.h
@@ -83,7 +83,7 @@ typedef uint32_t         UBaseType_t;
 #define portBYTE_ALIGNMENT              8
 #define portDONT_DISCARD                __attribute__( ( used ) )
 
-/* We have to use PICO_DIVIDER_DISABLE_INTERRUPTS as the source of truth rathern than our config,
+/* We have to use PICO_DIVIDER_DISABLE_INTERRUPTS as the source of truth rather than our config,
  * as our FreeRTOSConfig.h header cannot be included by ASM code - which is what this affects in the SDK */
 #define portUSE_DIVIDER_SAVE_RESTORE    !PICO_DIVIDER_DISABLE_INTERRUPTS
 #if portUSE_DIVIDER_SAVE_RESTORE
diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/include/FreeRTOSConfig_arch.h b/portable/ThirdParty/GCC/Xtensa_ESP32/include/FreeRTOSConfig_arch.h
index fa942add3..b7e42aa94 100644
--- a/portable/ThirdParty/GCC/Xtensa_ESP32/include/FreeRTOSConfig_arch.h
+++ b/portable/ThirdParty/GCC/Xtensa_ESP32/include/FreeRTOSConfig_arch.h
@@ -114,7 +114,7 @@
  * interrupts. */
 #define configMAX_SYSCALL_INTERRUPT_PRIORITY    XCHAL_EXCM_LEVEL
 
-/* Stack alignment, architecture specifc. Must be a power of two. */
+/* Stack alignment, architecture specific. Must be a power of two. */
 #define configSTACK_ALIGNMENT                   16
 
 
diff --git a/portable/WizC/PIC18/portmacro.h b/portable/WizC/PIC18/portmacro.h
index a976bbd99..abeb955d0 100644
--- a/portable/WizC/PIC18/portmacro.h
+++ b/portable/WizC/PIC18/portmacro.h
@@ -154,7 +154,7 @@ extern uint8_t ucCriticalNesting;
 /*
  * The minimal stacksize is calculated on the first reference of
  * portMINIMAL_STACK_SIZE. Some input to this calculation is
- * compiletime determined, other input is port-defined (see port.c)
+ * compile time determined, other input is port-defined (see port.c)
  */
 extern uint16_t usPortCALCULATE_MINIMAL_STACK_SIZE( void );
 extern uint16_t usCalcMinStackSize;
diff --git a/portable/oWatcom/16BitDOS/common/portasm.h b/portable/oWatcom/16BitDOS/common/portasm.h
index dac4dc864..b9cb0e697 100644
--- a/portable/oWatcom/16BitDOS/common/portasm.h
+++ b/portable/oWatcom/16BitDOS/common/portasm.h
@@ -63,7 +63,7 @@ debugger).  The true stack pointer is then stored in the bp register.  We add
                                         "les    bx, dword ptr pxCurrentTCB"                                                 \
                                         "mov    ss, es:[ bx + 2 ]"                                                          \
                                         "mov    sp, es:[ bx ]"                                                              \
-                                        "mov    bp, sp"                     /* Prepair the bp register for the restoration of the SP in the compiler generated portion of the ISR */    \
+                                        "mov    bp, sp"                     /* Prepare the bp register for the restoration of the SP in the compiler generated portion of the ISR */    \
                                         "add    bp, 0x0002"
 
 
diff --git a/queue.c b/queue.c
index fd62489f5..4759b439b 100644
--- a/queue.c
+++ b/queue.c
@@ -418,7 +418,7 @@ BaseType_t xQueueGenericReset( QueueHandle_t xQueue,
 
             #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
             {
-                /* Queues can be allocated wither statically or dynamically, so
+                /* Queues can be allocated either statically or dynamically, so
                  * note this queue was allocated statically in case the queue is
                  * later deleted. */
                 pxNewQueue->ucStaticallyAllocated = pdTRUE;

From a081ba8b9c0e18b466a6e03ee0052d00f5f23304 Mon Sep 17 00:00:00 2001
From: Kody Stribrny <89810515+kstribrnAmzn@users.noreply.github.com>
Date: Fri, 1 Nov 2024 10:56:18 -0700
Subject: [PATCH 341/424] Fix variable name mismatch, mpu_wrappers type
 mismatch. (#1181)

Fix variable name mismatch introduced by #1166.
Fix MPU v2 wrappers incorrectly using UBaseType_t instead
of BaseType.
---
 include/mpu_prototypes.h          |  4 ++--
 portable/Common/mpu_wrappers.c    |  4 ++--
 portable/Common/mpu_wrappers_v2.c | 14 +++++++-------
 3 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/include/mpu_prototypes.h b/include/mpu_prototypes.h
index ea2dd9f75..1efd13440 100644
--- a/include/mpu_prototypes.h
+++ b/include/mpu_prototypes.h
@@ -346,12 +346,12 @@ TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
  * with all the APIs. */
 TimerHandle_t MPU_xTimerCreate( const char * const pcTimerName,
                                 const TickType_t xTimerPeriodInTicks,
-                                const UBaseType_t uxAutoReload,
+                                const BaseType_t xAutoReload,
                                 void * const pvTimerID,
                                 TimerCallbackFunction_t pxCallbackFunction ) PRIVILEGED_FUNCTION;
 TimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName,
                                       const TickType_t xTimerPeriodInTicks,
-                                      const UBaseType_t uxAutoReload,
+                                      const BaseType_t xAutoReload,
                                       void * const pvTimerID,
                                       TimerCallbackFunction_t pxCallbackFunction,
                                       StaticTimer_t * pxTimerBuffer ) PRIVILEGED_FUNCTION;
diff --git a/portable/Common/mpu_wrappers.c b/portable/Common/mpu_wrappers.c
index ab2a74bd2..4c5731665 100644
--- a/portable/Common/mpu_wrappers.c
+++ b/portable/Common/mpu_wrappers.c
@@ -1806,7 +1806,7 @@
                 portRAISE_PRIVILEGE();
                 portMEMORY_BARRIER();
 
-                vTimerSetReloadMode( xTimer, uxAutoReload );
+                vTimerSetReloadMode( xTimer, xAutoReload );
                 portMEMORY_BARRIER();
 
                 portRESET_PRIVILEGE();
@@ -1814,7 +1814,7 @@
             }
             else
             {
-                vTimerSetReloadMode( xTimer, uxAutoReload );
+                vTimerSetReloadMode( xTimer, xAutoReload );
             }
         }
     #endif /* if ( configUSE_TIMERS == 1 ) */
diff --git a/portable/Common/mpu_wrappers_v2.c b/portable/Common/mpu_wrappers_v2.c
index c5bbdc318..eb9e6f056 100644
--- a/portable/Common/mpu_wrappers_v2.c
+++ b/portable/Common/mpu_wrappers_v2.c
@@ -3558,10 +3558,10 @@
     #if ( configUSE_TIMERS == 1 )
 
         void MPU_vTimerSetReloadModeImpl( TimerHandle_t xTimer,
-                                          const UBaseType_t uxAutoReload ) PRIVILEGED_FUNCTION;
+                                          const BaseType_t xAutoReload ) PRIVILEGED_FUNCTION;
 
         void MPU_vTimerSetReloadModeImpl( TimerHandle_t xTimer,
-                                          const UBaseType_t uxAutoReload ) /* PRIVILEGED_FUNCTION */
+                                          const BaseType_t xAutoReload ) /* PRIVILEGED_FUNCTION */
         {
             TimerHandle_t xInternalTimerHandle = NULL;
             int32_t lIndex;
@@ -3579,7 +3579,7 @@
 
                     if( xInternalTimerHandle != NULL )
                     {
-                        vTimerSetReloadMode( xInternalTimerHandle, uxAutoReload );
+                        vTimerSetReloadMode( xInternalTimerHandle, xAutoReload );
                     }
                 }
             }
@@ -3733,7 +3733,7 @@
 
         TimerHandle_t MPU_xTimerCreate( const char * const pcTimerName,
                                         const TickType_t xTimerPeriodInTicks,
-                                        const UBaseType_t uxAutoReload,
+                                        const BaseType_t xAutoReload,
                                         void * const pvTimerID,
                                         TimerCallbackFunction_t pxCallbackFunction ) /* PRIVILEGED_FUNCTION */
         {
@@ -3745,7 +3745,7 @@
 
             if( lIndex != -1 )
             {
-                xInternalTimerHandle = xTimerCreate( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, MPU_TimerCallback );
+                xInternalTimerHandle = xTimerCreate( pcTimerName, xTimerPeriodInTicks, xAutoReload, pvTimerID, MPU_TimerCallback );
 
                 if( xInternalTimerHandle != NULL )
                 {
@@ -3768,7 +3768,7 @@
 
         TimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName,
                                               const TickType_t xTimerPeriodInTicks,
-                                              const UBaseType_t uxAutoReload,
+                                              const BaseType_t xAutoReload,
                                               void * const pvTimerID,
                                               TimerCallbackFunction_t pxCallbackFunction,
                                               StaticTimer_t * pxTimerBuffer ) /* PRIVILEGED_FUNCTION */
@@ -3781,7 +3781,7 @@
 
             if( lIndex != -1 )
             {
-                xInternalTimerHandle = xTimerCreateStatic( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, MPU_TimerCallback, pxTimerBuffer );
+                xInternalTimerHandle = xTimerCreateStatic( pcTimerName, xTimerPeriodInTicks, xAutoReload, pvTimerID, MPU_TimerCallback, pxTimerBuffer );
 
                 if( xInternalTimerHandle != NULL )
                 {

From 7d76dceaadd22bfdd6a77973f8c0b7b46cb326c5 Mon Sep 17 00:00:00 2001
From: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Date: Sat, 2 Nov 2024 08:13:53 +0530
Subject: [PATCH 342/424] Add assert check for NULL TCB handle (#1177)

Co-authored-by: ActoryOu <jay2002824@gmail.com>
---
 tasks.c | 37 ++++++++++++++++++++++++++++++++++---
 1 file changed, 34 insertions(+), 3 deletions(-)

diff --git a/tasks.c b/tasks.c
index 6d86326c5..147b1aade 100644
--- a/tasks.c
+++ b/tasks.c
@@ -2203,6 +2203,7 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
             /* If null is passed in here then it is the calling task that is
              * being deleted. */
             pxTCB = prvGetTCBFromHandle( xTaskToDelete );
+            configASSERT( pxTCB != NULL );
 
             /* Remove task from the ready/delayed list. */
             if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
@@ -2495,7 +2496,7 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
 
         traceENTER_eTaskGetState( xTask );
 
-        configASSERT( pxTCB );
+        configASSERT( pxTCB != NULL );
 
         #if ( configNUMBER_OF_CORES == 1 )
             if( pxTCB == pxCurrentTCB )
@@ -2628,6 +2629,8 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
             /* If null is passed in here then it is the priority of the task
              * that called uxTaskPriorityGet() that is being queried. */
             pxTCB = prvGetTCBFromHandle( xTask );
+            configASSERT( pxTCB != NULL );
+
             uxReturn = pxTCB->uxPriority;
         }
         portBASE_TYPE_EXIT_CRITICAL();
@@ -2676,6 +2679,8 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
             /* If null is passed in here then it is the priority of the calling
              * task that is being queried. */
             pxTCB = prvGetTCBFromHandle( xTask );
+            configASSERT( pxTCB != NULL );
+
             uxReturn = pxTCB->uxPriority;
         }
         taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
@@ -2702,6 +2707,8 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
             /* If null is passed in here then it is the base priority of the task
              * that called uxTaskBasePriorityGet() that is being queried. */
             pxTCB = prvGetTCBFromHandle( xTask );
+            configASSERT( pxTCB != NULL );
+
             uxReturn = pxTCB->uxBasePriority;
         }
         portBASE_TYPE_EXIT_CRITICAL();
@@ -2750,6 +2757,8 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
             /* If null is passed in here then it is the base priority of the calling
              * task that is being queried. */
             pxTCB = prvGetTCBFromHandle( xTask );
+            configASSERT( pxTCB != NULL );
+
             uxReturn = pxTCB->uxBasePriority;
         }
         taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
@@ -2794,6 +2803,7 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
             /* If null is passed in here then it is the priority of the calling
              * task that is being changed. */
             pxTCB = prvGetTCBFromHandle( xTask );
+            configASSERT( pxTCB != NULL );
 
             traceTASK_PRIORITY_SET( pxTCB, uxNewPriority );
 
@@ -2988,6 +2998,7 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
         taskENTER_CRITICAL();
         {
             pxTCB = prvGetTCBFromHandle( xTask );
+            configASSERT( pxTCB != NULL );
 
             pxTCB->uxCoreAffinityMask = uxCoreAffinityMask;
 
@@ -3043,6 +3054,8 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
         portBASE_TYPE_ENTER_CRITICAL();
         {
             pxTCB = prvGetTCBFromHandle( xTask );
+            configASSERT( pxTCB != NULL );
+
             uxCoreAffinityMask = pxTCB->uxCoreAffinityMask;
         }
         portBASE_TYPE_EXIT_CRITICAL();
@@ -3066,6 +3079,7 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
         taskENTER_CRITICAL();
         {
             pxTCB = prvGetTCBFromHandle( xTask );
+            configASSERT( pxTCB != NULL );
 
             pxTCB->xPreemptionDisable = pdTRUE;
         }
@@ -3089,6 +3103,7 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
         taskENTER_CRITICAL();
         {
             pxTCB = prvGetTCBFromHandle( xTask );
+            configASSERT( pxTCB != NULL );
 
             pxTCB->xPreemptionDisable = pdFALSE;
 
@@ -3122,6 +3137,7 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
             /* If null is passed in here then it is the running task that is
              * being suspended. */
             pxTCB = prvGetTCBFromHandle( xTaskToSuspend );
+            configASSERT( pxTCB != NULL );
 
             traceTASK_SUSPEND( pxTCB );
 
@@ -4194,7 +4210,7 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery )
     /* If null is passed in here then the name of the calling task is being
      * queried. */
     pxTCB = prvGetTCBFromHandle( xTaskToQuery );
-    configASSERT( pxTCB );
+    configASSERT( pxTCB != NULL );
 
     traceRETURN_pcTaskGetName( &( pxTCB->pcTaskName[ 0 ] ) );
 
@@ -4357,6 +4373,7 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery )
         configASSERT( ppxTaskBuffer != NULL );
 
         pxTCB = prvGetTCBFromHandle( xTask );
+        configASSERT( pxTCB != NULL );
 
         #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE == 1 )
         {
@@ -4596,7 +4613,7 @@ BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp )
 
         traceENTER_xTaskAbortDelay( xTask );
 
-        configASSERT( pxTCB );
+        configASSERT( pxTCB != NULL );
 
         vTaskSuspendAll();
         {
@@ -4978,6 +4995,7 @@ BaseType_t xTaskIncrementTick( void )
 
         /* If xTask is NULL then set the calling task's hook. */
         pxTCB = prvGetTCBFromHandle( xTask );
+        configASSERT( pxTCB != NULL );
 
         /* Save the hook function in the TCB.  A critical section is required as
          * the value can be accessed from an interrupt. */
@@ -5007,6 +5025,7 @@ BaseType_t xTaskIncrementTick( void )
 
         /* If xTask is NULL then set the calling task's hook. */
         pxTCB = prvGetTCBFromHandle( xTask );
+        configASSERT( pxTCB != NULL );
 
         /* Save the hook function in the TCB.  A critical section is required as
          * the value can be accessed from an interrupt. */
@@ -5984,6 +6003,8 @@ static portTASK_FUNCTION( prvIdleTask, pvParameters )
             ( xIndex < ( BaseType_t ) configNUM_THREAD_LOCAL_STORAGE_POINTERS ) )
         {
             pxTCB = prvGetTCBFromHandle( xTaskToQuery );
+            configASSERT( pxTCB != NULL );
+
             pvReturn = pxTCB->pvThreadLocalStoragePointers[ xIndex ];
         }
         else
@@ -6011,6 +6032,7 @@ static portTASK_FUNCTION( prvIdleTask, pvParameters )
         /* If null is passed in here then we are modifying the MPU settings of
          * the calling task. */
         pxTCB = prvGetTCBFromHandle( xTaskToModify );
+        configASSERT( pxTCB != NULL );
 
         vPortStoreTaskMPUSettings( &( pxTCB->xMPUSettings ), pxRegions, NULL, 0 );
 
@@ -6141,6 +6163,7 @@ static void prvCheckTasksWaitingTermination( void )
 
         /* xTask is NULL then get the state of the calling task. */
         pxTCB = prvGetTCBFromHandle( xTask );
+        configASSERT( pxTCB != NULL );
 
         pxTaskStatus->xHandle = pxTCB;
         pxTaskStatus->pcTaskName = ( const char * ) &( pxTCB->pcTaskName[ 0 ] );
@@ -6357,6 +6380,7 @@ static void prvCheckTasksWaitingTermination( void )
          * type. */
 
         pxTCB = prvGetTCBFromHandle( xTask );
+        configASSERT( pxTCB != NULL );
 
         #if portSTACK_GROWTH < 0
         {
@@ -6389,6 +6413,7 @@ static void prvCheckTasksWaitingTermination( void )
         traceENTER_uxTaskGetStackHighWaterMark( xTask );
 
         pxTCB = prvGetTCBFromHandle( xTask );
+        configASSERT( pxTCB != NULL );
 
         #if portSTACK_GROWTH < 0
         {
@@ -8288,6 +8313,7 @@ TickType_t uxTaskResetEventItemValue( void )
         /* If null is passed in here then it is the calling task that is having
          * its notification state cleared. */
         pxTCB = prvGetTCBFromHandle( xTask );
+        configASSERT( pxTCB != NULL );
 
         taskENTER_CRITICAL();
         {
@@ -8327,6 +8353,7 @@ TickType_t uxTaskResetEventItemValue( void )
         /* If null is passed in here then it is the calling task that is having
          * its notification state cleared. */
         pxTCB = prvGetTCBFromHandle( xTask );
+        configASSERT( pxTCB != NULL );
 
         taskENTER_CRITICAL();
         {
@@ -8354,6 +8381,7 @@ TickType_t uxTaskResetEventItemValue( void )
         traceENTER_ulTaskGetRunTimeCounter( xTask );
 
         pxTCB = prvGetTCBFromHandle( xTask );
+        configASSERT( pxTCB != NULL );
 
         traceRETURN_ulTaskGetRunTimeCounter( pxTCB->ulRunTimeCounter );
 
@@ -8381,6 +8409,8 @@ TickType_t uxTaskResetEventItemValue( void )
         if( ulTotalTime > ( configRUN_TIME_COUNTER_TYPE ) 0 )
         {
             pxTCB = prvGetTCBFromHandle( xTask );
+            configASSERT( pxTCB != NULL );
+
             ulReturn = pxTCB->ulRunTimeCounter / ulTotalTime;
         }
         else
@@ -8584,6 +8614,7 @@ static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait,
         traceENTER_xTaskGetMPUSettings( xTask );
 
         pxTCB = prvGetTCBFromHandle( xTask );
+        configASSERT( pxTCB != NULL );
 
         traceRETURN_xTaskGetMPUSettings( &( pxTCB->xMPUSettings ) );
 

From 445336aad9a72dc4a3de6cf2e7ad212517f94558 Mon Sep 17 00:00:00 2001
From: ActoryOu <jay2002824@gmail.com>
Date: Mon, 4 Nov 2024 17:23:28 +0800
Subject: [PATCH 343/424] Follow GitHub recommendation to update release.yml
 (#1178)

GitHub recommends to store user inputs in environments variables
and then use them in scripts. This PR updates the code as per the
GitHub recommendation.

Details here - https://docs.github.com/en/actions/security-for-github-actions/security-guides/security-hardening-for-github-actions#understanding-the-risk-of-script-injections.
---
 .github/workflows/auto-release.yml | 46 +++++++++++++++++++++---------
 tasks.c                            |  2 +-
 2 files changed, 34 insertions(+), 14 deletions(-)

diff --git a/.github/workflows/auto-release.yml b/.github/workflows/auto-release.yml
index bad7a9bce..3477f6591 100644
--- a/.github/workflows/auto-release.yml
+++ b/.github/workflows/auto-release.yml
@@ -44,37 +44,49 @@ jobs:
           fetch-depth: 0
 
       - name: Configure git identity
+        env:
+          ACTOR: ${{ github.actor }}
         run: |
-          git config --global user.name ${{ github.actor }}
-          git config --global user.email ${{ github.actor }}@users.noreply.github.com
+          git config --global user.name "$ACTOR"
+          git config --global user.email "$ACTOR"@users.noreply.github.com
 
       - name: create a new branch that references commit id
+        env:
+          VERSION_NUMBER: ${{ github.event.inputs.version_number }}
+          COMMIT_ID: ${{ github.event.inputs.commit_id }}
         working-directory: ./local_kernel
         run: |
-          git checkout -b ${{ github.event.inputs.version_number }} ${{ github.event.inputs.commit_id }}
+          git checkout -b "$VERSION_NUMBER" "$COMMIT_ID"
           echo "COMMIT_SHA_1=$(git rev-parse HEAD)" >> $GITHUB_ENV
 
       - name: Update source files with version info
+        env:
+          VERSION_NUMBER: ${{ github.event.inputs.version_number }}
+          MAIN_BR_VERSION_NUMBER: ${{ github.event.inputs.main_br_version }}
+          COMMIT_SHA_1: ${{ env.COMMIT_SHA_1 }}
+          GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
         run: |
           # Install deps and run
           pip install -r ./tools/.github/scripts/release-requirements.txt
-          ./tools/.github/scripts/update_src_version.py FreeRTOS --kernel-repo-path=local_kernel --kernel-commit=${{ env.COMMIT_SHA_1 }} --new-kernel-version=${{ github.event.inputs.version_number }} --new-kernel-main-br-version=${{ github.event.inputs.main_br_version }}
+          ./tools/.github/scripts/update_src_version.py FreeRTOS --kernel-repo-path=local_kernel --kernel-commit="$COMMIT_SHA_1" --new-kernel-version="$VERSION_NUMBER" --new-kernel-main-br-version="$MAIN_BR_VERSION_NUMBER"
           exit $?
-        env:
-            GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
 
       - name : Update version number in manifest.yml
+        env:
+          VERSION_NUMBER: ${{ github.event.inputs.version_number }}
         working-directory: ./local_kernel
         run: |
-          ./.github/scripts/manifest_updater.py -v ${{ github.event.inputs.version_number }}
+          ./.github/scripts/manifest_updater.py -v "$VERSION_NUMBER"
           exit $?
 
       - name : Commit version number change in manifest.yml
+        env:
+          VERSION_NUMBER: ${{ github.event.inputs.version_number }}
         working-directory: ./local_kernel
         run: |
           git add .
           git commit -m '[AUTO][RELEASE]: Update version number in manifest.yml'
-          git push -u origin ${{ github.event.inputs.version_number }}
+          git push -u origin "$VERSION_NUMBER"
 
       - name: Generate SBOM
         uses: FreeRTOS/CI-CD-Github-Actions/sbom-generator@main
@@ -83,24 +95,32 @@ jobs:
           source_path: ./
 
       - name: commit SBOM file
+        env:
+          VERSION_NUMBER: ${{ github.event.inputs.version_number }}
         working-directory: ./local_kernel
         run: |
           git add .
           git commit -m '[AUTO][RELEASE]: Update SBOM'
-          git push -u origin ${{ github.event.inputs.version_number }}
+          git push -u origin "$VERSION_NUMBER"
           echo "COMMIT_SHA_2=$(git rev-parse HEAD)" >> $GITHUB_ENV
 
       - name: Release
+        env:
+          VERSION_NUMBER: ${{ github.event.inputs.version_number }}
+          MAIN_BR_VERSION_NUMBER: ${{ github.event.inputs.main_br_version }}
+          COMMIT_SHA_2: ${{ env.COMMIT_SHA_2 }}
+          REPO_OWNER: ${{ github.repository_owner }}
+          GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
         run: |
           # Install deps and run
           pip install -r ./tools/.github/scripts/release-requirements.txt
-          ./tools/.github/scripts/release.py ${{ github.repository_owner }} --kernel-repo-path=local_kernel --kernel-commit=${{ env.COMMIT_SHA_2 }} --new-kernel-version=${{ github.event.inputs.version_number }} --new-kernel-main-br-version=${{ github.event.inputs.main_br_version }}
+          ./tools/.github/scripts/release.py "$REPO_OWNER" --kernel-repo-path=local_kernel --kernel-commit="$COMMIT_SHA_2" --new-kernel-version="$VERSION_NUMBER" --new-kernel-main-br-version="$MAIN_BR_VERSION_NUMBER"
           exit $?
-        env:
-            GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
 
       - name: Cleanup
+        env:
+          VERSION_NUMBER: ${{ github.event.inputs.version_number }}
         working-directory: ./local_kernel
         run: |
           # Delete the branch created for Tag by SBOM generator
-          git push -u origin --delete ${{ github.event.inputs.version_number }}
+          git push -u origin --delete "$VERSION_NUMBER"
diff --git a/tasks.c b/tasks.c
index 147b1aade..421dea71d 100644
--- a/tasks.c
+++ b/tasks.c
@@ -3882,7 +3882,7 @@ void vTaskSuspendAll( void )
             /* This must never be called from inside a critical section. */
             configASSERT( portGET_CRITICAL_NESTING_COUNT() == 0 );
 
-            /* portSOFRWARE_BARRIER() is only implemented for emulated/simulated ports that
+            /* portSOFTWARE_BARRIER() is only implemented for emulated/simulated ports that
              * do not otherwise exhibit real time behaviour. */
             portSOFTWARE_BARRIER();
 

From a27d6650eeff533f3b556b8acf63c1c30f5da455 Mon Sep 17 00:00:00 2001
From: ActoryOu <jay2002824@gmail.com>
Date: Mon, 4 Nov 2024 19:05:52 +0800
Subject: [PATCH 344/424] Move configASSERT default definition above before
 including portable.h. (#1185)

Move configASSERT default definition above before including portable.h.
---
 include/FreeRTOS.h                                 | 14 +++++++-------
 portable/ARMv8M/non_secure/portmacrocommon.h       |  2 +-
 portable/CCS/ARM_CM3/portmacro.h                   |  2 +-
 portable/CCS/ARM_CM4F/portmacro.h                  |  2 +-
 portable/GCC/ARM_AARCH64/portmacro.h               |  2 +-
 portable/GCC/ARM_AARCH64_SRE/portmacro.h           |  2 +-
 portable/GCC/ARM_CA9/portmacro.h                   |  2 +-
 portable/GCC/ARM_CM23/non_secure/portmacrocommon.h |  2 +-
 .../GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h  |  2 +-
 portable/GCC/ARM_CM3/portmacro.h                   |  2 +-
 portable/GCC/ARM_CM33/non_secure/portmacrocommon.h |  2 +-
 .../GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h  |  2 +-
 .../GCC/ARM_CM35P/non_secure/portmacrocommon.h     |  2 +-
 .../GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h |  2 +-
 portable/GCC/ARM_CM3_MPU/portmacro.h               |  2 +-
 portable/GCC/ARM_CM4F/portmacro.h                  |  2 +-
 portable/GCC/ARM_CM4_MPU/portmacro.h               |  2 +-
 portable/GCC/ARM_CM55/non_secure/portmacrocommon.h |  2 +-
 .../GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h  |  2 +-
 portable/GCC/ARM_CM7/r0p1/portmacro.h              |  2 +-
 portable/GCC/ARM_CM85/non_secure/portmacrocommon.h |  2 +-
 .../GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h  |  2 +-
 portable/GCC/ARM_CR5/portmacro.h                   |  2 +-
 portable/GCC/RX100/portmacro.h                     |  2 +-
 portable/GCC/RX200/portmacro.h                     |  2 +-
 portable/GCC/RX600/portmacro.h                     |  2 +-
 portable/GCC/RX600v2/portmacro.h                   |  2 +-
 portable/GCC/RX700v3_DPFPU/portmacro.h             |  2 +-
 portable/IAR/ARM_CA9/portmacro.h                   |  2 +-
 portable/IAR/ARM_CM23/non_secure/portmacrocommon.h |  2 +-
 .../IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h  |  2 +-
 portable/IAR/ARM_CM3/portmacro.h                   |  2 +-
 portable/IAR/ARM_CM33/non_secure/portmacrocommon.h |  2 +-
 .../IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h  |  2 +-
 .../IAR/ARM_CM35P/non_secure/portmacrocommon.h     |  2 +-
 .../IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h |  2 +-
 portable/IAR/ARM_CM4F/portmacro.h                  |  2 +-
 portable/IAR/ARM_CM4F_MPU/portmacro.h              |  2 +-
 portable/IAR/ARM_CM55/non_secure/portmacrocommon.h |  2 +-
 .../IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h  |  2 +-
 portable/IAR/ARM_CM7/r0p1/portmacro.h              |  2 +-
 portable/IAR/ARM_CM85/non_secure/portmacrocommon.h |  2 +-
 .../IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h  |  2 +-
 portable/IAR/RX100/portmacro.h                     |  2 +-
 portable/IAR/RX600/portmacro.h                     |  2 +-
 portable/IAR/RX700v3_DPFPU/portmacro.h             |  2 +-
 portable/IAR/RXv2/portmacro.h                      |  2 +-
 portable/MPLAB/PIC32MEC14xx/portmacro.h            |  2 +-
 portable/MPLAB/PIC32MX/portmacro.h                 |  2 +-
 portable/MPLAB/PIC32MZ/portmacro.h                 |  2 +-
 portable/MikroC/ARM_CM4F/portmacro.h               |  2 +-
 portable/RVDS/ARM_CA9/portmacro.h                  |  2 +-
 portable/RVDS/ARM_CM3/portmacro.h                  |  2 +-
 portable/RVDS/ARM_CM4F/portmacro.h                 |  2 +-
 portable/RVDS/ARM_CM4_MPU/portmacro.h              |  2 +-
 portable/RVDS/ARM_CM7/r0p1/portmacro.h             |  2 +-
 portable/Renesas/RX100/portmacro.h                 |  2 +-
 portable/Renesas/RX200/portmacro.h                 |  2 +-
 portable/Renesas/RX600/portmacro.h                 |  2 +-
 portable/Renesas/RX600v2/portmacro.h               |  2 +-
 portable/Renesas/RX700v3_DPFPU/portmacro.h         |  2 +-
 .../GCC/Xtensa_ESP32/include/FreeRTOSConfig_arch.h |  2 +-
 62 files changed, 68 insertions(+), 68 deletions(-)

diff --git a/include/FreeRTOS.h b/include/FreeRTOS.h
index 821b55d5d..8849adc84 100644
--- a/include/FreeRTOS.h
+++ b/include/FreeRTOS.h
@@ -94,6 +94,13 @@
     #define configUSE_MALLOC_FAILED_HOOK    0
 #endif
 
+#ifndef configASSERT
+    #define configASSERT( x )
+    #define configASSERT_DEFINED    0
+#else
+    #define configASSERT_DEFINED    1
+#endif
+
 /* Basic FreeRTOS definitions. */
 #include "projdefs.h"
 
@@ -364,13 +371,6 @@
     #error configMAX_TASK_NAME_LEN must be set to a minimum of 1 in FreeRTOSConfig.h
 #endif
 
-#ifndef configASSERT
-    #define configASSERT( x )
-    #define configASSERT_DEFINED    0
-#else
-    #define configASSERT_DEFINED    1
-#endif
-
 /* configPRECONDITION should be defined as configASSERT.
  * The CBMC proofs need a way to track assumptions and assertions.
  * A configPRECONDITION statement should express an implicit invariant or
diff --git a/portable/ARMv8M/non_secure/portmacrocommon.h b/portable/ARMv8M/non_secure/portmacrocommon.h
index cd83bee57..8a8dc7d6a 100644
--- a/portable/ARMv8M/non_secure/portmacrocommon.h
+++ b/portable/ARMv8M/non_secure/portmacrocommon.h
@@ -312,7 +312,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * @brief Validate priority of ISRs that are allowed to call FreeRTOS
  * system calls.
  */
-#ifdef configASSERT
+#if ( configASSERT_DEFINED == 1 )
     #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
         void vPortValidateInterruptPriority( void );
         #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
diff --git a/portable/CCS/ARM_CM3/portmacro.h b/portable/CCS/ARM_CM3/portmacro.h
index 336a5ff1e..42498555f 100644
--- a/portable/CCS/ARM_CM3/portmacro.h
+++ b/portable/CCS/ARM_CM3/portmacro.h
@@ -170,7 +170,7 @@
     #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 /*-----------------------------------------------------------*/
 
-    #ifdef configASSERT
+    #if ( configASSERT_DEFINED == 1 )
         void vPortValidateInterruptPriority( void );
         #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
     #endif
diff --git a/portable/CCS/ARM_CM4F/portmacro.h b/portable/CCS/ARM_CM4F/portmacro.h
index 47dcc5aba..faefd124c 100644
--- a/portable/CCS/ARM_CM4F/portmacro.h
+++ b/portable/CCS/ARM_CM4F/portmacro.h
@@ -164,7 +164,7 @@
     #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 /*-----------------------------------------------------------*/
 
-    #ifdef configASSERT
+    #if ( configASSERT_DEFINED == 1 )
         void vPortValidateInterruptPriority( void );
         #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
     #endif
diff --git a/portable/GCC/ARM_AARCH64/portmacro.h b/portable/GCC/ARM_AARCH64/portmacro.h
index e89abb661..0091357ee 100644
--- a/portable/GCC/ARM_AARCH64/portmacro.h
+++ b/portable/GCC/ARM_AARCH64/portmacro.h
@@ -169,7 +169,7 @@ void FreeRTOS_Tick_Handler( void );
 
 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 
-#ifdef configASSERT
+#if ( configASSERT_DEFINED == 1 )
     void vPortValidateInterruptPriority( void );
     #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
 #endif /* configASSERT */
diff --git a/portable/GCC/ARM_AARCH64_SRE/portmacro.h b/portable/GCC/ARM_AARCH64_SRE/portmacro.h
index efbcdfae6..296984d5b 100644
--- a/portable/GCC/ARM_AARCH64_SRE/portmacro.h
+++ b/portable/GCC/ARM_AARCH64_SRE/portmacro.h
@@ -160,7 +160,7 @@ void vPortTaskUsesFPU( void );
 
 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 
-#ifdef configASSERT
+#if ( configASSERT_DEFINED == 1 )
     void vPortValidateInterruptPriority( void );
     #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
 #endif /* configASSERT */
diff --git a/portable/GCC/ARM_CA9/portmacro.h b/portable/GCC/ARM_CA9/portmacro.h
index 0e213cf5d..1ded79c8c 100644
--- a/portable/GCC/ARM_CA9/portmacro.h
+++ b/portable/GCC/ARM_CA9/portmacro.h
@@ -157,7 +157,7 @@ void FreeRTOS_Tick_Handler( void );
 
 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 
-#ifdef configASSERT
+#if ( configASSERT_DEFINED == 1 )
     void vPortValidateInterruptPriority( void );
     #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
 #endif /* configASSERT */
diff --git a/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h
index cd83bee57..8a8dc7d6a 100644
--- a/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h
@@ -312,7 +312,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * @brief Validate priority of ISRs that are allowed to call FreeRTOS
  * system calls.
  */
-#ifdef configASSERT
+#if ( configASSERT_DEFINED == 1 )
     #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
         void vPortValidateInterruptPriority( void );
         #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h
index cd83bee57..8a8dc7d6a 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h
@@ -312,7 +312,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * @brief Validate priority of ISRs that are allowed to call FreeRTOS
  * system calls.
  */
-#ifdef configASSERT
+#if ( configASSERT_DEFINED == 1 )
     #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
         void vPortValidateInterruptPriority( void );
         #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
diff --git a/portable/GCC/ARM_CM3/portmacro.h b/portable/GCC/ARM_CM3/portmacro.h
index 757e44fd9..75dbcfa6c 100644
--- a/portable/GCC/ARM_CM3/portmacro.h
+++ b/portable/GCC/ARM_CM3/portmacro.h
@@ -171,7 +171,7 @@ extern void vPortExitCritical( void );
 
 /*-----------------------------------------------------------*/
 
-#ifdef configASSERT
+#if ( configASSERT_DEFINED == 1 )
     void vPortValidateInterruptPriority( void );
     #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
 #endif
diff --git a/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h
index cd83bee57..8a8dc7d6a 100644
--- a/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h
@@ -312,7 +312,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * @brief Validate priority of ISRs that are allowed to call FreeRTOS
  * system calls.
  */
-#ifdef configASSERT
+#if ( configASSERT_DEFINED == 1 )
     #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
         void vPortValidateInterruptPriority( void );
         #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h
index cd83bee57..8a8dc7d6a 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h
@@ -312,7 +312,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * @brief Validate priority of ISRs that are allowed to call FreeRTOS
  * system calls.
  */
-#ifdef configASSERT
+#if ( configASSERT_DEFINED == 1 )
     #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
         void vPortValidateInterruptPriority( void );
         #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
diff --git a/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h
index cd83bee57..8a8dc7d6a 100644
--- a/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h
@@ -312,7 +312,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * @brief Validate priority of ISRs that are allowed to call FreeRTOS
  * system calls.
  */
-#ifdef configASSERT
+#if ( configASSERT_DEFINED == 1 )
     #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
         void vPortValidateInterruptPriority( void );
         #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
index cd83bee57..8a8dc7d6a 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
@@ -312,7 +312,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * @brief Validate priority of ISRs that are allowed to call FreeRTOS
  * system calls.
  */
-#ifdef configASSERT
+#if ( configASSERT_DEFINED == 1 )
     #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
         void vPortValidateInterruptPriority( void );
         #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
diff --git a/portable/GCC/ARM_CM3_MPU/portmacro.h b/portable/GCC/ARM_CM3_MPU/portmacro.h
index 7dd66e3ca..fb2c53832 100644
--- a/portable/GCC/ARM_CM3_MPU/portmacro.h
+++ b/portable/GCC/ARM_CM3_MPU/portmacro.h
@@ -247,7 +247,7 @@ extern void vPortExitCritical( void );
 
 /*-----------------------------------------------------------*/
 
-#ifdef configASSERT
+#if ( configASSERT_DEFINED == 1 )
     void vPortValidateInterruptPriority( void );
     #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
 #endif
diff --git a/portable/GCC/ARM_CM4F/portmacro.h b/portable/GCC/ARM_CM4F/portmacro.h
index 6c97a1280..0a91d7c92 100644
--- a/portable/GCC/ARM_CM4F/portmacro.h
+++ b/portable/GCC/ARM_CM4F/portmacro.h
@@ -174,7 +174,7 @@ extern void vPortExitCritical( void );
 
 /*-----------------------------------------------------------*/
 
-#ifdef configASSERT
+#if ( configASSERT_DEFINED == 1 )
     void vPortValidateInterruptPriority( void );
     #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
 #endif
diff --git a/portable/GCC/ARM_CM4_MPU/portmacro.h b/portable/GCC/ARM_CM4_MPU/portmacro.h
index 264887e8e..0c40ac624 100644
--- a/portable/GCC/ARM_CM4_MPU/portmacro.h
+++ b/portable/GCC/ARM_CM4_MPU/portmacro.h
@@ -341,7 +341,7 @@ extern void vPortExitCritical( void );
 
 /*-----------------------------------------------------------*/
 
-#ifdef configASSERT
+#if ( configASSERT_DEFINED == 1 )
     void vPortValidateInterruptPriority( void );
     #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
 #endif
diff --git a/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h
index cd83bee57..8a8dc7d6a 100644
--- a/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h
@@ -312,7 +312,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * @brief Validate priority of ISRs that are allowed to call FreeRTOS
  * system calls.
  */
-#ifdef configASSERT
+#if ( configASSERT_DEFINED == 1 )
     #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
         void vPortValidateInterruptPriority( void );
         #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h
index cd83bee57..8a8dc7d6a 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h
@@ -312,7 +312,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * @brief Validate priority of ISRs that are allowed to call FreeRTOS
  * system calls.
  */
-#ifdef configASSERT
+#if ( configASSERT_DEFINED == 1 )
     #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
         void vPortValidateInterruptPriority( void );
         #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
diff --git a/portable/GCC/ARM_CM7/r0p1/portmacro.h b/portable/GCC/ARM_CM7/r0p1/portmacro.h
index 2d2edacdf..4bc490b98 100644
--- a/portable/GCC/ARM_CM7/r0p1/portmacro.h
+++ b/portable/GCC/ARM_CM7/r0p1/portmacro.h
@@ -171,7 +171,7 @@ extern void vPortExitCritical( void );
 
 /*-----------------------------------------------------------*/
 
-#ifdef configASSERT
+#if ( configASSERT_DEFINED == 1 )
     void vPortValidateInterruptPriority( void );
     #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
 #endif
diff --git a/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h
index cd83bee57..8a8dc7d6a 100644
--- a/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h
@@ -312,7 +312,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * @brief Validate priority of ISRs that are allowed to call FreeRTOS
  * system calls.
  */
-#ifdef configASSERT
+#if ( configASSERT_DEFINED == 1 )
     #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
         void vPortValidateInterruptPriority( void );
         #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h
index cd83bee57..8a8dc7d6a 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h
@@ -312,7 +312,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * @brief Validate priority of ISRs that are allowed to call FreeRTOS
  * system calls.
  */
-#ifdef configASSERT
+#if ( configASSERT_DEFINED == 1 )
     #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
         void vPortValidateInterruptPriority( void );
         #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
diff --git a/portable/GCC/ARM_CR5/portmacro.h b/portable/GCC/ARM_CR5/portmacro.h
index 568208a99..35336e569 100644
--- a/portable/GCC/ARM_CR5/portmacro.h
+++ b/portable/GCC/ARM_CR5/portmacro.h
@@ -163,7 +163,7 @@ void FreeRTOS_Tick_Handler( void );
 
 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 
-#ifdef configASSERT
+#if ( configASSERT_DEFINED == 1 )
     void vPortValidateInterruptPriority( void );
     #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
 #endif /* configASSERT */
diff --git a/portable/GCC/RX100/portmacro.h b/portable/GCC/RX100/portmacro.h
index c661c4c9c..052ee0be3 100644
--- a/portable/GCC/RX100/portmacro.h
+++ b/portable/GCC/RX100/portmacro.h
@@ -111,7 +111,7 @@ typedef unsigned long    UBaseType_t;
  * interrupt API to ensure API function and interrupt entry is as fast and as
  * simple as possible. */
 #define portENABLE_INTERRUPTS()                           __asm volatile ( "MVTIPL    #0" )
-#ifdef configASSERT
+#if ( configASSERT_DEFINED == 1 )
     #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
     #define portDISABLE_INTERRUPTS()                      if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile( "MVTIPL    %0" ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
 #else
diff --git a/portable/GCC/RX200/portmacro.h b/portable/GCC/RX200/portmacro.h
index a767299c5..16e41bc61 100644
--- a/portable/GCC/RX200/portmacro.h
+++ b/portable/GCC/RX200/portmacro.h
@@ -113,7 +113,7 @@ typedef unsigned long    UBaseType_t;
  * interrupt API to ensure API function and interrupt entry is as fast and as
  * simple as possible. */
 #define portENABLE_INTERRUPTS()                           __asm volatile ( "MVTIPL    #0" )
-#ifdef configASSERT
+#if ( configASSERT_DEFINED == 1 )
     #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
     #define portDISABLE_INTERRUPTS()                      if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile( "MVTIPL    %0" ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
 #else
diff --git a/portable/GCC/RX600/portmacro.h b/portable/GCC/RX600/portmacro.h
index 79559a989..187b2b5bd 100644
--- a/portable/GCC/RX600/portmacro.h
+++ b/portable/GCC/RX600/portmacro.h
@@ -113,7 +113,7 @@ typedef unsigned long    UBaseType_t;
  * interrupt API to ensure API function and interrupt entry is as fast and as
  * simple as possible. */
 #define portENABLE_INTERRUPTS()                           __asm volatile ( "MVTIPL    #0" )
-#ifdef configASSERT
+#if ( configASSERT_DEFINED == 1 )
     #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
     #define portDISABLE_INTERRUPTS()                      if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile( "MVTIPL    %0" ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
 #else
diff --git a/portable/GCC/RX600v2/portmacro.h b/portable/GCC/RX600v2/portmacro.h
index 79559a989..187b2b5bd 100644
--- a/portable/GCC/RX600v2/portmacro.h
+++ b/portable/GCC/RX600v2/portmacro.h
@@ -113,7 +113,7 @@ typedef unsigned long    UBaseType_t;
  * interrupt API to ensure API function and interrupt entry is as fast and as
  * simple as possible. */
 #define portENABLE_INTERRUPTS()                           __asm volatile ( "MVTIPL    #0" )
-#ifdef configASSERT
+#if ( configASSERT_DEFINED == 1 )
     #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
     #define portDISABLE_INTERRUPTS()                      if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile( "MVTIPL    %0" ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
 #else
diff --git a/portable/GCC/RX700v3_DPFPU/portmacro.h b/portable/GCC/RX700v3_DPFPU/portmacro.h
index 68c65b45f..bbfd24f90 100644
--- a/portable/GCC/RX700v3_DPFPU/portmacro.h
+++ b/portable/GCC/RX700v3_DPFPU/portmacro.h
@@ -137,7 +137,7 @@ typedef unsigned long    UBaseType_t;
  * interrupt API to ensure API function and interrupt entry is as fast and as
  * simple as possible. */
 #define portENABLE_INTERRUPTS()                           __asm volatile ( "MVTIPL  #0" )
-#ifdef configASSERT
+#if ( configASSERT_DEFINED == 1 )
     #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
     #define portDISABLE_INTERRUPTS()                      if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile( "MVTIPL  %0" ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
 #else
diff --git a/portable/IAR/ARM_CA9/portmacro.h b/portable/IAR/ARM_CA9/portmacro.h
index c0954d895..f1cb124a2 100644
--- a/portable/IAR/ARM_CA9/portmacro.h
+++ b/portable/IAR/ARM_CA9/portmacro.h
@@ -151,7 +151,7 @@
 
     #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 
-    #ifdef configASSERT
+    #if ( configASSERT_DEFINED == 1 )
         void vPortValidateInterruptPriority( void );
         #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
     #endif /* configASSERT */
diff --git a/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h
index cd83bee57..8a8dc7d6a 100644
--- a/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h
@@ -312,7 +312,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * @brief Validate priority of ISRs that are allowed to call FreeRTOS
  * system calls.
  */
-#ifdef configASSERT
+#if ( configASSERT_DEFINED == 1 )
     #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
         void vPortValidateInterruptPriority( void );
         #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h
index cd83bee57..8a8dc7d6a 100644
--- a/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h
@@ -312,7 +312,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * @brief Validate priority of ISRs that are allowed to call FreeRTOS
  * system calls.
  */
-#ifdef configASSERT
+#if ( configASSERT_DEFINED == 1 )
     #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
         void vPortValidateInterruptPriority( void );
         #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
diff --git a/portable/IAR/ARM_CM3/portmacro.h b/portable/IAR/ARM_CM3/portmacro.h
index a64c4fb26..f49c618c4 100644
--- a/portable/IAR/ARM_CM3/portmacro.h
+++ b/portable/IAR/ARM_CM3/portmacro.h
@@ -173,7 +173,7 @@ extern void vPortExitCritical( void );
 #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 /*-----------------------------------------------------------*/
 
-#ifdef configASSERT
+#if ( configASSERT_DEFINED == 1 )
     void vPortValidateInterruptPriority( void );
     #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
 #endif
diff --git a/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h
index cd83bee57..8a8dc7d6a 100644
--- a/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h
@@ -312,7 +312,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * @brief Validate priority of ISRs that are allowed to call FreeRTOS
  * system calls.
  */
-#ifdef configASSERT
+#if ( configASSERT_DEFINED == 1 )
     #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
         void vPortValidateInterruptPriority( void );
         #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h
index cd83bee57..8a8dc7d6a 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h
@@ -312,7 +312,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * @brief Validate priority of ISRs that are allowed to call FreeRTOS
  * system calls.
  */
-#ifdef configASSERT
+#if ( configASSERT_DEFINED == 1 )
     #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
         void vPortValidateInterruptPriority( void );
         #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
diff --git a/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h
index cd83bee57..8a8dc7d6a 100644
--- a/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h
@@ -312,7 +312,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * @brief Validate priority of ISRs that are allowed to call FreeRTOS
  * system calls.
  */
-#ifdef configASSERT
+#if ( configASSERT_DEFINED == 1 )
     #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
         void vPortValidateInterruptPriority( void );
         #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
index cd83bee57..8a8dc7d6a 100644
--- a/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
@@ -312,7 +312,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * @brief Validate priority of ISRs that are allowed to call FreeRTOS
  * system calls.
  */
-#ifdef configASSERT
+#if ( configASSERT_DEFINED == 1 )
     #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
         void vPortValidateInterruptPriority( void );
         #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
diff --git a/portable/IAR/ARM_CM4F/portmacro.h b/portable/IAR/ARM_CM4F/portmacro.h
index 93cfd555e..f3d8ace9d 100644
--- a/portable/IAR/ARM_CM4F/portmacro.h
+++ b/portable/IAR/ARM_CM4F/portmacro.h
@@ -172,7 +172,7 @@ extern void vPortExitCritical( void );
 #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 /*-----------------------------------------------------------*/
 
-#ifdef configASSERT
+#if ( configASSERT_DEFINED == 1 )
     void vPortValidateInterruptPriority( void );
     #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
 #endif
diff --git a/portable/IAR/ARM_CM4F_MPU/portmacro.h b/portable/IAR/ARM_CM4F_MPU/portmacro.h
index 246b82dde..08f849992 100644
--- a/portable/IAR/ARM_CM4F_MPU/portmacro.h
+++ b/portable/IAR/ARM_CM4F_MPU/portmacro.h
@@ -345,7 +345,7 @@ extern void vPortExitCritical( void );
 #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 /*-----------------------------------------------------------*/
 
-#ifdef configASSERT
+#if ( configASSERT_DEFINED == 1 )
     void vPortValidateInterruptPriority( void );
     #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
 #endif
diff --git a/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h
index cd83bee57..8a8dc7d6a 100644
--- a/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h
@@ -312,7 +312,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * @brief Validate priority of ISRs that are allowed to call FreeRTOS
  * system calls.
  */
-#ifdef configASSERT
+#if ( configASSERT_DEFINED == 1 )
     #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
         void vPortValidateInterruptPriority( void );
         #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h
index cd83bee57..8a8dc7d6a 100644
--- a/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h
@@ -312,7 +312,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * @brief Validate priority of ISRs that are allowed to call FreeRTOS
  * system calls.
  */
-#ifdef configASSERT
+#if ( configASSERT_DEFINED == 1 )
     #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
         void vPortValidateInterruptPriority( void );
         #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
diff --git a/portable/IAR/ARM_CM7/r0p1/portmacro.h b/portable/IAR/ARM_CM7/r0p1/portmacro.h
index 0165b2d91..7c66ed3f9 100644
--- a/portable/IAR/ARM_CM7/r0p1/portmacro.h
+++ b/portable/IAR/ARM_CM7/r0p1/portmacro.h
@@ -175,7 +175,7 @@ extern void vPortExitCritical( void );
 #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 /*-----------------------------------------------------------*/
 
-#ifdef configASSERT
+#if ( configASSERT_DEFINED == 1 )
     void vPortValidateInterruptPriority( void );
     #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
 #endif
diff --git a/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h
index cd83bee57..8a8dc7d6a 100644
--- a/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h
@@ -312,7 +312,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * @brief Validate priority of ISRs that are allowed to call FreeRTOS
  * system calls.
  */
-#ifdef configASSERT
+#if ( configASSERT_DEFINED == 1 )
     #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
         void vPortValidateInterruptPriority( void );
         #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h
index cd83bee57..8a8dc7d6a 100644
--- a/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h
@@ -312,7 +312,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * @brief Validate priority of ISRs that are allowed to call FreeRTOS
  * system calls.
  */
-#ifdef configASSERT
+#if ( configASSERT_DEFINED == 1 )
     #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
         void vPortValidateInterruptPriority( void );
         #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
diff --git a/portable/IAR/RX100/portmacro.h b/portable/IAR/RX100/portmacro.h
index f6dd43865..ab5eae69f 100644
--- a/portable/IAR/RX100/portmacro.h
+++ b/portable/IAR/RX100/portmacro.h
@@ -108,7 +108,7 @@ typedef unsigned long    UBaseType_t;
  * interrupt API to ensure API function and interrupt entry is as fast and as
  * simple as possible. */
 #define portENABLE_INTERRUPTS()                           __set_interrupt_level( ( uint8_t ) 0 )
-#ifdef configASSERT
+#if ( configASSERT_DEFINED == 1 )
     #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    configASSERT( ( __get_interrupt_level() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
     #define portDISABLE_INTERRUPTS()                      if( __get_interrupt_level() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
 #else
diff --git a/portable/IAR/RX600/portmacro.h b/portable/IAR/RX600/portmacro.h
index b40242185..87faf8639 100644
--- a/portable/IAR/RX600/portmacro.h
+++ b/portable/IAR/RX600/portmacro.h
@@ -110,7 +110,7 @@ typedef unsigned long    UBaseType_t;
  * interrupt API to ensure API function and interrupt entry is as fast and as
  * simple as possible. */
 #define portENABLE_INTERRUPTS()                           __set_interrupt_level( ( uint8_t ) 0 )
-#ifdef configASSERT
+#if ( configASSERT_DEFINED == 1 )
     #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    configASSERT( ( __get_interrupt_level() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
     #define portDISABLE_INTERRUPTS()                      if( __get_interrupt_level() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
 #else
diff --git a/portable/IAR/RX700v3_DPFPU/portmacro.h b/portable/IAR/RX700v3_DPFPU/portmacro.h
index a3b15f75c..e24cbfe53 100644
--- a/portable/IAR/RX700v3_DPFPU/portmacro.h
+++ b/portable/IAR/RX700v3_DPFPU/portmacro.h
@@ -143,7 +143,7 @@ typedef unsigned long    UBaseType_t;
  * interrupt API to ensure API function and interrupt entry is as fast and as
  * simple as possible. */
 #define portENABLE_INTERRUPTS()                           __set_interrupt_level( ( uint8_t ) 0 )
-#ifdef configASSERT
+#if ( configASSERT_DEFINED == 1 )
     #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    configASSERT( ( __get_interrupt_level() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
     #define portDISABLE_INTERRUPTS()                      if( __get_interrupt_level() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
 #else
diff --git a/portable/IAR/RXv2/portmacro.h b/portable/IAR/RXv2/portmacro.h
index 67295fd22..792beb9df 100644
--- a/portable/IAR/RXv2/portmacro.h
+++ b/portable/IAR/RXv2/portmacro.h
@@ -110,7 +110,7 @@ typedef unsigned long    UBaseType_t;
  * interrupt API to ensure API function and interrupt entry is as fast and as
  * simple as possible. */
 #define portENABLE_INTERRUPTS()                           __set_interrupt_level( ( uint8_t ) 0 )
-#ifdef configASSERT
+#if ( configASSERT_DEFINED == 1 )
     #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    configASSERT( ( __get_interrupt_level() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
     #define portDISABLE_INTERRUPTS()                      if( __get_interrupt_level() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
 #else
diff --git a/portable/MPLAB/PIC32MEC14xx/portmacro.h b/portable/MPLAB/PIC32MEC14xx/portmacro.h
index 665634659..f431ae324 100644
--- a/portable/MPLAB/PIC32MEC14xx/portmacro.h
+++ b/portable/MPLAB/PIC32MEC14xx/portmacro.h
@@ -148,7 +148,7 @@ value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY when an ISR
 safe FreeRTOS API function was executed.  ISR safe FreeRTOS API functions are
 those that end in FromISR.  FreeRTOS maintains a separate interrupt API to
 ensure API function and interrupt entry is as fast and as simple as possible. */
-#ifdef configASSERT
+#if ( configASSERT_DEFINED == 1 )
     #define portDISABLE_INTERRUPTS()                                                                            \
     {                                                                                                           \
     uint32_t ulStatus;                                                                                          \
diff --git a/portable/MPLAB/PIC32MX/portmacro.h b/portable/MPLAB/PIC32MX/portmacro.h
index 7fa73ab98..7868dcb8c 100644
--- a/portable/MPLAB/PIC32MX/portmacro.h
+++ b/portable/MPLAB/PIC32MX/portmacro.h
@@ -95,7 +95,7 @@ value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY when an ISR
 safe FreeRTOS API function was executed.  ISR safe FreeRTOS API functions are
 those that end in FromISR.  FreeRTOS maintains a separate interrupt API to
 ensure API function and interrupt entry is as fast and as simple as possible. */
-#ifdef configASSERT
+#if ( configASSERT_DEFINED == 1 )
     #define portDISABLE_INTERRUPTS()                                            \
     {                                                                           \
     uint32_t ulStatus;                                                      \
diff --git a/portable/MPLAB/PIC32MZ/portmacro.h b/portable/MPLAB/PIC32MZ/portmacro.h
index 532a0fdac..8b0497086 100644
--- a/portable/MPLAB/PIC32MZ/portmacro.h
+++ b/portable/MPLAB/PIC32MZ/portmacro.h
@@ -97,7 +97,7 @@ value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY when an ISR
 safe FreeRTOS API function was executed.  ISR safe FreeRTOS API functions are
 those that end in FromISR.  FreeRTOS maintains a separate interrupt API to
 ensure API function and interrupt entry is as fast and as simple as possible. */
-#ifdef configASSERT
+#if ( configASSERT_DEFINED == 1 )
     #define portDISABLE_INTERRUPTS()                                            \
     {                                                                           \
     uint32_t ulStatus;                                                          \
diff --git a/portable/MikroC/ARM_CM4F/portmacro.h b/portable/MikroC/ARM_CM4F/portmacro.h
index 15e4d5614..d6cd752e4 100644
--- a/portable/MikroC/ARM_CM4F/portmacro.h
+++ b/portable/MikroC/ARM_CM4F/portmacro.h
@@ -175,7 +175,7 @@
 
 /*-----------------------------------------------------------*/
 
-    #ifdef configASSERT
+    #if ( configASSERT_DEFINED == 1 )
         void vPortValidateInterruptPriority( void );
         #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
     #endif
diff --git a/portable/RVDS/ARM_CA9/portmacro.h b/portable/RVDS/ARM_CA9/portmacro.h
index 8a69d4677..2218a6379 100644
--- a/portable/RVDS/ARM_CA9/portmacro.h
+++ b/portable/RVDS/ARM_CA9/portmacro.h
@@ -153,7 +153,7 @@ void vPortTaskUsesFPU( void );
 
 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 
-#ifdef configASSERT
+#if ( configASSERT_DEFINED == 1 )
     void vPortValidateInterruptPriority( void );
     #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
 #endif
diff --git a/portable/RVDS/ARM_CM3/portmacro.h b/portable/RVDS/ARM_CM3/portmacro.h
index f69f4c303..0436525fd 100644
--- a/portable/RVDS/ARM_CM3/portmacro.h
+++ b/portable/RVDS/ARM_CM3/portmacro.h
@@ -165,7 +165,7 @@ extern void vPortExitCritical( void );
 #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 /*-----------------------------------------------------------*/
 
-#ifdef configASSERT
+#if ( configASSERT_DEFINED == 1 )
     void vPortValidateInterruptPriority( void );
     #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
 #endif
diff --git a/portable/RVDS/ARM_CM4F/portmacro.h b/portable/RVDS/ARM_CM4F/portmacro.h
index 9957328d0..063b148f4 100644
--- a/portable/RVDS/ARM_CM4F/portmacro.h
+++ b/portable/RVDS/ARM_CM4F/portmacro.h
@@ -165,7 +165,7 @@ extern void vPortExitCritical( void );
 #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 /*-----------------------------------------------------------*/
 
-#ifdef configASSERT
+#if ( configASSERT_DEFINED == 1 )
     void vPortValidateInterruptPriority( void );
     #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
 #endif
diff --git a/portable/RVDS/ARM_CM4_MPU/portmacro.h b/portable/RVDS/ARM_CM4_MPU/portmacro.h
index 005e00503..5977f3f88 100644
--- a/portable/RVDS/ARM_CM4_MPU/portmacro.h
+++ b/portable/RVDS/ARM_CM4_MPU/portmacro.h
@@ -334,7 +334,7 @@ extern void vPortExitCritical( void );
 #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 /*-----------------------------------------------------------*/
 
-#ifdef configASSERT
+#if ( configASSERT_DEFINED == 1 )
     void vPortValidateInterruptPriority( void );
     #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
 #endif
diff --git a/portable/RVDS/ARM_CM7/r0p1/portmacro.h b/portable/RVDS/ARM_CM7/r0p1/portmacro.h
index 5f3a05397..b36b427d9 100644
--- a/portable/RVDS/ARM_CM7/r0p1/portmacro.h
+++ b/portable/RVDS/ARM_CM7/r0p1/portmacro.h
@@ -165,7 +165,7 @@ extern void vPortExitCritical( void );
 #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 /*-----------------------------------------------------------*/
 
-#ifdef configASSERT
+#if ( configASSERT_DEFINED == 1 )
     void vPortValidateInterruptPriority( void );
     #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
 #endif
diff --git a/portable/Renesas/RX100/portmacro.h b/portable/Renesas/RX100/portmacro.h
index a38b93f4a..5ae7d05aa 100644
--- a/portable/Renesas/RX100/portmacro.h
+++ b/portable/Renesas/RX100/portmacro.h
@@ -112,7 +112,7 @@ functions are those that end in FromISR.  FreeRTOS maintains a separate
 interrupt API to ensure API function and interrupt entry is as fast and as
 simple as possible. */
 #define portENABLE_INTERRUPTS()     set_ipl( ( long ) 0 )
-#ifdef configASSERT
+#if ( configASSERT_DEFINED == 1 )
     #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( get_ipl() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
     #define portDISABLE_INTERRUPTS()    if( get_ipl() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
 #else
diff --git a/portable/Renesas/RX200/portmacro.h b/portable/Renesas/RX200/portmacro.h
index d67acc4bb..bf11b2e93 100644
--- a/portable/Renesas/RX200/portmacro.h
+++ b/portable/Renesas/RX200/portmacro.h
@@ -112,7 +112,7 @@ functions are those that end in FromISR.  FreeRTOS maintains a separate
 interrupt API to ensure API function and interrupt entry is as fast and as
 simple as possible. */
 #define portENABLE_INTERRUPTS()     set_ipl( ( long ) 0 )
-#ifdef configASSERT
+#if ( configASSERT_DEFINED == 1 )
     #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( get_ipl() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
     #define portDISABLE_INTERRUPTS()    if( get_ipl() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
 #else
diff --git a/portable/Renesas/RX600/portmacro.h b/portable/Renesas/RX600/portmacro.h
index 98a7fede4..53f45dec7 100644
--- a/portable/Renesas/RX600/portmacro.h
+++ b/portable/Renesas/RX600/portmacro.h
@@ -113,7 +113,7 @@ functions are those that end in FromISR.  FreeRTOS maintains a separate
 interrupt API to ensure API function and interrupt entry is as fast and as
 simple as possible. */
 #define portENABLE_INTERRUPTS()     set_ipl( ( long ) 0 )
-#ifdef configASSERT
+#if ( configASSERT_DEFINED == 1 )
     #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( get_ipl() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
     #define portDISABLE_INTERRUPTS()    if( get_ipl() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
 #else
diff --git a/portable/Renesas/RX600v2/portmacro.h b/portable/Renesas/RX600v2/portmacro.h
index b3868c157..0442b05a1 100644
--- a/portable/Renesas/RX600v2/portmacro.h
+++ b/portable/Renesas/RX600v2/portmacro.h
@@ -113,7 +113,7 @@ functions are those that end in FromISR.  FreeRTOS maintains a separate
 interrupt API to ensure API function and interrupt entry is as fast and as
 simple as possible. */
 #define portENABLE_INTERRUPTS()     set_ipl( ( long ) 0 )
-#ifdef configASSERT
+#if ( configASSERT_DEFINED == 1 )
     #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( get_ipl() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
     #define portDISABLE_INTERRUPTS()    if( get_ipl() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
 #else
diff --git a/portable/Renesas/RX700v3_DPFPU/portmacro.h b/portable/Renesas/RX700v3_DPFPU/portmacro.h
index fc1bb531b..e0c6b1df1 100644
--- a/portable/Renesas/RX700v3_DPFPU/portmacro.h
+++ b/portable/Renesas/RX700v3_DPFPU/portmacro.h
@@ -138,7 +138,7 @@
  * interrupt API to ensure API function and interrupt entry is as fast and as
  * simple as possible. */
     #define portENABLE_INTERRUPTS()                           set_ipl( ( long ) 0 )
-    #ifdef configASSERT
+    #if ( configASSERT_DEFINED == 1 )
         #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    configASSERT( ( get_ipl() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
         #define portDISABLE_INTERRUPTS()                      if( get_ipl() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
     #else
diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/include/FreeRTOSConfig_arch.h b/portable/ThirdParty/GCC/Xtensa_ESP32/include/FreeRTOSConfig_arch.h
index b7e42aa94..57f7b0156 100644
--- a/portable/ThirdParty/GCC/Xtensa_ESP32/include/FreeRTOSConfig_arch.h
+++ b/portable/ThirdParty/GCC/Xtensa_ESP32/include/FreeRTOSConfig_arch.h
@@ -85,7 +85,7 @@
 
 /* If CONFIG_FREERTOS_ASSERT_DISABLE is set then configASSERT is defined empty later in FreeRTOS.h and the macro */
 /* configASSERT_DEFINED remains unset (meaning some warnings are avoided) */
-#ifdef configASSERT
+#if ( configASSERT_DEFINED == 1 )
     #undef configASSERT
     #if defined( CONFIG_FREERTOS_ASSERT_FAIL_PRINT_CONTINUE )
         #define configASSERT( a )                                           \

From b4a970729baca801b3980c0f6163b0395a674ab6 Mon Sep 17 00:00:00 2001
From: Vishwanath Martur <64204611+vishwamartur@users.noreply.github.com>
Date: Mon, 4 Nov 2024 18:02:35 +0530
Subject: [PATCH 345/424] Fix RISC-V configMTIMECMP_BASE_ADDRESS (64-bit)
 stored in 32-bit int (#1176)

Related to #189

Update `configMTIMECMP_BASE_ADDRESS` to be stored in a 64-bit integer.

* Change the type of `ullMachineTimerCompareRegisterBase` to `uint64_t` in `portable/GCC/RISC-V/port.c`.
* Change the type of `ullMachineTimerCompareRegisterBase` to `uint64_t` in `portable/IAR/RISC-V/port.c`.
* Update the initialization of `ullMachineTimerCompareRegisterBase` to use `configMTIMECMP_BASE_ADDRESS` in both files.

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
---
 portable/GCC/RISC-V/port.c | 6 +++---
 portable/IAR/RISC-V/port.c | 6 +++---
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/portable/GCC/RISC-V/port.c b/portable/GCC/RISC-V/port.c
index 0b7b336d7..e52fe8b12 100644
--- a/portable/GCC/RISC-V/port.c
+++ b/portable/GCC/RISC-V/port.c
@@ -27,8 +27,8 @@
  */
 
 /*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the RISC-V port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the RISC-V port.
+ *----------------------------------------------------------*/
 
 /* Scheduler includes. */
 #include "FreeRTOS.h"
@@ -90,7 +90,7 @@ void vPortSetupTimerInterrupt( void ) __attribute__( ( weak ) );
 uint64_t ullNextTime = 0ULL;
 const uint64_t * pullNextTime = &ullNextTime;
 const size_t uxTimerIncrementsForOneTick = ( size_t ) ( ( configCPU_CLOCK_HZ ) / ( configTICK_RATE_HZ ) ); /* Assumes increment won't go over 32-bits. */
-uint32_t const ullMachineTimerCompareRegisterBase = configMTIMECMP_BASE_ADDRESS;
+uint64_t const ullMachineTimerCompareRegisterBase = configMTIMECMP_BASE_ADDRESS;
 volatile uint64_t * pullMachineTimerCompareRegister = NULL;
 
 /* Holds the critical nesting value - deliberately non-zero at start up to
diff --git a/portable/IAR/RISC-V/port.c b/portable/IAR/RISC-V/port.c
index eec69439f..8040022bd 100644
--- a/portable/IAR/RISC-V/port.c
+++ b/portable/IAR/RISC-V/port.c
@@ -27,8 +27,8 @@
  */
 
 /*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the RISC-V port.
-*----------------------------------------------------------*/
+ * Implementation of functions defined in portable.h for the RISC-V port.
+ *----------------------------------------------------------*/
 
 /* Scheduler includes. */
 #include "FreeRTOS.h"
@@ -98,7 +98,7 @@ void vPortSetupTimerInterrupt( void ) __attribute__( ( weak ) );
 uint64_t ullNextTime = 0ULL;
 const uint64_t * pullNextTime = &ullNextTime;
 const size_t uxTimerIncrementsForOneTick = ( size_t ) ( ( configCPU_CLOCK_HZ ) / ( configTICK_RATE_HZ ) ); /* Assumes increment won't go over 32-bits. */
-uint32_t const ullMachineTimerCompareRegisterBase = configMTIMECMP_BASE_ADDRESS;
+uint64_t const ullMachineTimerCompareRegisterBase = configMTIMECMP_BASE_ADDRESS;
 volatile uint64_t * pullMachineTimerCompareRegister = NULL;
 
 /* Holds the critical nesting value - deliberately non-zero at start up to

From f0d79459d6ab0ee430325a93fdb8bbf0adfada27 Mon Sep 17 00:00:00 2001
From: Vishwanath Martur <64204611+vishwamartur@users.noreply.github.com>
Date: Mon, 4 Nov 2024 21:51:51 +0530
Subject: [PATCH 346/424] Fix SMP debugging issue on rp2040 (#1174)

* Fix SMP debugging issue on rp2040

Related to #1172

Add `multicore_reset_core1` before `multicore_launch_core1` in `xPortStartScheduler` function to fix debugging issue on rp2040 with SMP enabled.

* Modify `portable/ThirdParty/GCC/RP2040/port.c` to include a call to `multicore_reset_core1` before `multicore_launch_core1` within the `#if portRUNNING_ON_BOTH_CORES` block.

* Recover comments back

---------

Co-authored-by: ActoryOu <jay2002824@gmail.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Co-authored-by: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
---
 portable/ThirdParty/GCC/RP2040/port.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/portable/ThirdParty/GCC/RP2040/port.c b/portable/ThirdParty/GCC/RP2040/port.c
index 6c5d0e513..78c11bd63 100644
--- a/portable/ThirdParty/GCC/RP2040/port.c
+++ b/portable/ThirdParty/GCC/RP2040/port.c
@@ -378,6 +378,7 @@ void vPortStartFirstTask( void )
         #if portRUNNING_ON_BOTH_CORES
             ucPrimaryCoreNum = configTICK_CORE;
             configASSERT( get_core_num() == 0 ); /* we must be started on core 0 */
+            multicore_reset_core1();
             multicore_launch_core1( prvDisableInterruptsAndPortStartSchedulerOnCore );
         #else
             ucPrimaryCoreNum = get_core_num();

From d0d55f30314c72f323254bda2bf8506d9510b582 Mon Sep 17 00:00:00 2001
From: Trong Nguyen <147012384+TrongNguyenR@users.noreply.github.com>
Date: Tue, 5 Nov 2024 15:09:50 +0700
Subject: [PATCH 347/424] Enhancements and Bug Fixes for F1Kx Port (#1169)

Fix FPU stack order issue and Improve FPU checking flow
Fix Interrupt depth comparison logic
Fix parameter mismatch in portmacro.h file
Add comment to explain assembly code
---
 portable/CCRH/F1Kx/README.md   |  4 +--
 portable/CCRH/F1Kx/port.c      |  4 +--
 portable/CCRH/F1Kx/portasm.s   | 48 +++++++++++++++++++---------------
 portable/CCRH/F1Kx/portmacro.h |  8 +++---
 4 files changed, 35 insertions(+), 29 deletions(-)

diff --git a/portable/CCRH/F1Kx/README.md b/portable/CCRH/F1Kx/README.md
index 7583c67af..4cb9f07b6 100644
--- a/portable/CCRH/F1Kx/README.md
+++ b/portable/CCRH/F1Kx/README.md
@@ -23,8 +23,8 @@ The test project can be found [here](https://github.com/FreeRTOS/FreeRTOS-Commun
 ## Note
    1. Configure IPIR Interrupt: Ensure that the bit specifying the destination for binding (requesting) an interrupt is enabled (e.g: IBDxxx register of F1KH-D8) (1)
    2. `Channel 0` and address `0xFFFEEC00` are used as default configuration for configIPIR_CHANNEL and configEXCLUSIVE_ADDRESS, in case of resource confliction other channel/address can be used. (2)
-   3. The minimal stack size (configMINIMAL_STACK_SIZE) must be included the reserved memory for nested interrupt. This formula can be referred: `(task_context_size) * (1 + configMAX_INT_NESTING) + Stack_depth_of_taskcode`
-   In which, `task_context_size` is calculated as `36*4bytes = 144bytes` (when FPU enabled) or `34*4bytes = 136` (when FPU disabled), configMAX_INT_NESTING is 02 as default.
+   3. The minimal stack size (configMINIMAL_STACK_SIZE) must be included the reserved memory for nested interrupt. This formula can be referred: `(task_context_size) * (2 + configMAX_INT_NESTING) + Stack_depth_of_taskcode`
+   In which, `task_context_size` is calculated as `36*4bytes = 144bytes` (when FPU enabled) or `34*4bytes = 136` (when FPU disabled), configMAX_INT_NESTING is `02` as default (Note that a value of `0` is not allowed).
    4. `configTIMER_PRESCALE`: This value is required in order to correctly configure clock for `CPUCLK_L`. Refer to Hardware Manual at `Table 44.22` for `option byte`: If the user sets the option byte `CKDIVMD to 1`, then `configTIMER_PRESCALE = 4`. Otherwise, if `CKDIVMD is set to 0`, then `configTIMER_PRESCALE = 2`.
 
 (1)  This is applicable for F1KH-D8 with SMP only.
diff --git a/portable/CCRH/F1Kx/port.c b/portable/CCRH/F1Kx/port.c
index e3d71929d..0e6116527 100644
--- a/portable/CCRH/F1Kx/port.c
+++ b/portable/CCRH/F1Kx/port.c
@@ -171,7 +171,7 @@
     #define configSETUP_TICK_INTERRUPT()    prvSetupTimerInterrupt()
 #endif /* configSETUP_TICK_INTERRUPT */
 
-#ifndef configMAX_INT_NESTING
+#if ( !defined( configMAX_INT_NESTING ) || ( configMAX_INT_NESTING == 0 ) )
 
 /* Set the default value for depth of nested interrupt. In theory, the
  * microcontroller have mechanism to limit number of nested level of interrupt
@@ -225,7 +225,7 @@ volatile BaseType_t xPortScheduleStatus[ configNUMBER_OF_CORES ] = { 0 };
  * It is necessary to control maximum stack depth.
  */
 volatile UBaseType_t uxInterruptNesting[ configNUMBER_OF_CORES ] = { 0 };
-volatile const UBaseType_t uxPortMaxInterruptDepth = configMAX_INT_NESTING - 1;
+volatile const UBaseType_t uxPortMaxInterruptDepth = configMAX_INT_NESTING;
 
 /* Count number of nested locks by same cores. The lock is completely released
  * only if this count is decreased to 0, the lock is separated for task
diff --git a/portable/CCRH/F1Kx/portasm.s b/portable/CCRH/F1Kx/portasm.s
index 4e56f4493..ff8e7ee31 100644
--- a/portable/CCRH/F1Kx/portasm.s
+++ b/portable/CCRH/F1Kx/portasm.s
@@ -84,6 +84,10 @@ portSAVE_CONTEXT .macro
     stsr    FPEPC, r19
     pushsp  r18, r19
 
+    ; Save EIPSW register to stack
+    ; Due to the syntax of the pushsp instruction, using r14 as dummy value
+    pushsp  r14, r15
+
     ; Get current TCB, the return value is stored in r10 (CCRH compiler)
     jarl    _pvPortGetCurrentTCB, lp
     st.w    sp, 0[r10]
@@ -101,14 +105,15 @@ portRESTORE_CONTEXT .macro
 
     ; Restore FPU registers if FPU is enabled
     mov     FPU_MSK, r19
-    stsr    PSW, r18
-    tst     r18, r19
-
-     ; Jump over next 3 instructions: stsr (4 bytes)*2 + popsp (4 bytes)
+    ; Restore EIPSW register to check FPU
+    ; Due to the syntax of the popsp instruction, using r14 as dummy value
+    popsp	r14, r15
+    tst     r15, r19
+    ; Jump over next 3 instructions: stsr (4 bytes)*2 + popsp (4 bytes)
     bz      12
     popsp   r18, r19
-    ldsr    r18, FPEPC
-    ldsr    r19, FPSR
+    ldsr    r19, FPEPC
+    ldsr    r18, FPSR
 
     ;Restore general-purpose registers and EIPSW, EIPC, EIIC, CTPSW, CTPC
     popsp   r15, r19
@@ -146,14 +151,15 @@ SAVE_REGISTER .macro
     mov     ep, r15
     stsr    CTPSW, r14
     stsr    CTPC, r13
-    pushsp  r13, r19
+    pushsp  r13, r18
 
     mov     FPU_MSK, r16
     tst     r16, r19
-    bz      12
-    stsr    FPSR, r18
-    stsr    FPEPC, r19
-    pushsp  r18, r19
+    bz      8
+    stsr    FPSR, r17
+    stsr    FPEPC, r18
+
+    pushsp  r17, r19
 
 .endm
 ;------------------------------------------------------------------------------
@@ -161,15 +167,14 @@ SAVE_REGISTER .macro
 ;------------------------------------------------------------------------------
 RESTORE_REGISTER .macro
 
-    mov     FPU_MSK, r16
-    stsr    PSW, r18
-    tst     r18, r19
-    bz      12
-    popsp   r18, r19
+	mov     FPU_MSK, r15
+	popsp   r17, r19
+    tst     r19, r15
+    bz      8
     ldsr    r18, FPEPC
-    ldsr    r19, FPSR
+    ldsr    r17, FPSR
 
-    popsp   r13, r19
+    popsp   r13, r18
     ldsr    r13, CTPC
     ldsr    r14, CTPSW
     mov     r15, ep
@@ -268,9 +273,10 @@ _vIrq_Handler:
 
     ; Do not enable interrupt for nesting. Stackover flow may occurs if the
     ; depth of nesting interrupt is exceeded.
-    mov     #_uxPortMaxInterruptDepth, r15
-    cmp     r16, r15
-    be      4                                 ; Jump over ei instruction
+    mov     #_uxPortMaxInterruptDepth, r19
+    ld.w    0[r19], r15
+    cmp     r15, r16
+	bge     4                            ; Jump over ei instruction
     ei
     jarl    _vCommonISRHandler, lp
     di
diff --git a/portable/CCRH/F1Kx/portmacro.h b/portable/CCRH/F1Kx/portmacro.h
index e2b41f264..09f9f4614 100644
--- a/portable/CCRH/F1Kx/portmacro.h
+++ b/portable/CCRH/F1Kx/portmacro.h
@@ -111,11 +111,11 @@
 /* Scheduler utilities */
 
 /* Called at the end of an ISR that can cause a context switch */
-    extern void vPortSetSwitch( BaseType_t vPortSetSwitch );
+    extern void vPortSetSwitch( BaseType_t xSwitchRequired );
 
-    #define portEND_SWITCHING_ISR( xSwitchRequired )    vPortSetSwitch( vPortSetSwitch )
+    #define portEND_SWITCHING_ISR( x )    vPortSetSwitch( x )
 
-    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+    #define portYIELD_FROM_ISR( x )       portEND_SWITCHING_ISR( x )
 
 /* Use to transfer control from one task to perform other tasks of
  * higher priority */
@@ -131,7 +131,7 @@
         #define coreid    xPortGET_CORE_ID()
 
 /* Request the core ID x to yield. */
-        extern void vPortYieldCore( unsigned int coreID );
+        extern void vPortYieldCore( uint32_t coreID );
 
         #define portYIELD_CORE( x )                vPortYieldCore( x )
 

From 9736947af2c8490c23127e051d22d9c7c122cbd9 Mon Sep 17 00:00:00 2001
From: Tomas Galbicka <151615323+TomasGalbickaNXP@users.noreply.github.com>
Date: Tue, 12 Nov 2024 05:28:38 +0100
Subject: [PATCH 348/424] Heap: add new API to reset
 xMinimumEverFreeBytesRemaining. (#1189)

This commit adds new API functionality to reset xMinimumEverFreeBytesRemaining.
This functionality provides ability to get heap statistics during a particular period of time.

Signed-off-by: Tomas Galbicka <tomas.galbicka@nxp.com>
---
 include/portable.h        | 1 +
 portable/MemMang/heap_4.c | 6 ++++++
 2 files changed, 7 insertions(+)

diff --git a/include/portable.h b/include/portable.h
index 1b088b427..68e11e793 100644
--- a/include/portable.h
+++ b/include/portable.h
@@ -193,6 +193,7 @@ void vPortFree( void * pv ) PRIVILEGED_FUNCTION;
 void vPortInitialiseBlocks( void ) PRIVILEGED_FUNCTION;
 size_t xPortGetFreeHeapSize( void ) PRIVILEGED_FUNCTION;
 size_t xPortGetMinimumEverFreeHeapSize( void ) PRIVILEGED_FUNCTION;
+void xPortResetHeapMinimumEverFreeHeapSize( void ) PRIVILEGED_FUNCTION;
 
 #if ( configSTACK_ALLOCATION_FROM_SEPARATE_HEAP == 1 )
     void * pvPortMallocStack( size_t xSize ) PRIVILEGED_FUNCTION;
diff --git a/portable/MemMang/heap_4.c b/portable/MemMang/heap_4.c
index f3cab000d..acb334757 100644
--- a/portable/MemMang/heap_4.c
+++ b/portable/MemMang/heap_4.c
@@ -422,6 +422,12 @@ size_t xPortGetMinimumEverFreeHeapSize( void )
 }
 /*-----------------------------------------------------------*/
 
+void xPortResetHeapMinimumEverFreeHeapSize( void )
+{
+    xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
 void vPortInitialiseBlocks( void )
 {
     /* This just exists to keep the linker quiet. */

From 8f7f451c2a122c73cec30517c91c0cf889b18e02 Mon Sep 17 00:00:00 2001
From: Jeff Tenney <jeff.tenney@gmail.com>
Date: Tue, 12 Nov 2024 04:05:33 -0700
Subject: [PATCH 349/424] Don't suspend scheduler if task already notified
 (#1190)

* Don't suspend scheduler if task already notified
---
 tasks.c | 134 ++++++++++++++++++++++++++++----------------------------
 1 file changed, 66 insertions(+), 68 deletions(-)

diff --git a/tasks.c b/tasks.c
index 421dea71d..22e11f0fb 100644
--- a/tasks.c
+++ b/tasks.c
@@ -7659,24 +7659,27 @@ TickType_t uxTaskResetEventItemValue( void )
 
         configASSERT( uxIndexToWaitOn < configTASK_NOTIFICATION_ARRAY_ENTRIES );
 
-        /* We suspend the scheduler here as prvAddCurrentTaskToDelayedList is a
-         * non-deterministic operation. */
-        vTaskSuspendAll();
+        /* If the notification count is zero, and if we are willing to wait for a
+         * notification, then block the task and wait. */
+        if( ( pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ] == 0U ) && ( xTicksToWait > ( TickType_t ) 0 ) )
         {
-            /* We MUST enter a critical section to atomically check if a notification
-             * has occurred and set the flag to indicate that we are waiting for
-             * a notification. If we do not do so, a notification sent from an ISR
-             * will get lost. */
-            taskENTER_CRITICAL();
+            /* We suspend the scheduler here as prvAddCurrentTaskToDelayedList is a
+             * non-deterministic operation. */
+            vTaskSuspendAll();
             {
-                /* Only block if the notification count is not already non-zero. */
-                if( pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ] == 0U )
+                /* We MUST enter a critical section to atomically check if a notification
+                 * has occurred and set the flag to indicate that we are waiting for
+                 * a notification. If we do not do so, a notification sent from an ISR
+                 * will get lost. */
+                taskENTER_CRITICAL();
                 {
-                    /* Mark this task as waiting for a notification. */
-                    pxCurrentTCB->ucNotifyState[ uxIndexToWaitOn ] = taskWAITING_NOTIFICATION;
-
-                    if( xTicksToWait > ( TickType_t ) 0 )
+                    /* Only block if the notification count is not already non-zero. */
+                    if( pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ] == 0U )
                     {
+                        /* Mark this task as waiting for a notification. */
+                        pxCurrentTCB->ucNotifyState[ uxIndexToWaitOn ] = taskWAITING_NOTIFICATION;
+
+                        /* Arrange to wait for a notification. */
                         xShouldBlock = pdTRUE;
                     }
                     else
@@ -7684,37 +7687,33 @@ TickType_t uxTaskResetEventItemValue( void )
                         mtCOVERAGE_TEST_MARKER();
                     }
                 }
+                taskEXIT_CRITICAL();
+
+                /* We are now out of the critical section but the scheduler is still
+                 * suspended, so we are safe to do non-deterministic operations such
+                 * as prvAddCurrentTaskToDelayedList. */
+                if( xShouldBlock == pdTRUE )
+                {
+                    traceTASK_NOTIFY_TAKE_BLOCK( uxIndexToWaitOn );
+                    prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+                }
                 else
                 {
                     mtCOVERAGE_TEST_MARKER();
                 }
             }
-            taskEXIT_CRITICAL();
+            xAlreadyYielded = xTaskResumeAll();
 
-            /* We are now out of the critical section but the scheduler is still
-             * suspended, so we are safe to do non-deterministic operations such
-             * as prvAddCurrentTaskToDelayedList. */
-            if( xShouldBlock == pdTRUE )
+            /* Force a reschedule if xTaskResumeAll has not already done so. */
+            if( ( xShouldBlock == pdTRUE ) && ( xAlreadyYielded == pdFALSE ) )
             {
-                traceTASK_NOTIFY_TAKE_BLOCK( uxIndexToWaitOn );
-                prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+                taskYIELD_WITHIN_API();
             }
             else
             {
                 mtCOVERAGE_TEST_MARKER();
             }
         }
-        xAlreadyYielded = xTaskResumeAll();
-
-        /* Force a reschedule if xTaskResumeAll has not already done so. */
-        if( ( xShouldBlock == pdTRUE ) && ( xAlreadyYielded == pdFALSE ) )
-        {
-            taskYIELD_WITHIN_API();
-        }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
-        }
 
         taskENTER_CRITICAL();
         {
@@ -7763,28 +7762,31 @@ TickType_t uxTaskResetEventItemValue( void )
 
         configASSERT( uxIndexToWaitOn < configTASK_NOTIFICATION_ARRAY_ENTRIES );
 
-        /* We suspend the scheduler here as prvAddCurrentTaskToDelayedList is a
-         * non-deterministic operation. */
-        vTaskSuspendAll();
+        /* If the task hasn't received a notification, and if we are willing to wait
+         * for it, then block the task and wait. */
+        if( ( pxCurrentTCB->ucNotifyState[ uxIndexToWaitOn ] != taskNOTIFICATION_RECEIVED ) && ( xTicksToWait > ( TickType_t ) 0 ) )
         {
-            /* We MUST enter a critical section to atomically check and update the
-             * task notification value. If we do not do so, a notification from
-             * an ISR will get lost. */
-            taskENTER_CRITICAL();
+            /* We suspend the scheduler here as prvAddCurrentTaskToDelayedList is a
+             * non-deterministic operation. */
+            vTaskSuspendAll();
             {
-                /* Only block if a notification is not already pending. */
-                if( pxCurrentTCB->ucNotifyState[ uxIndexToWaitOn ] != taskNOTIFICATION_RECEIVED )
+                /* We MUST enter a critical section to atomically check and update the
+                 * task notification value. If we do not do so, a notification from
+                 * an ISR will get lost. */
+                taskENTER_CRITICAL();
                 {
-                    /* Clear bits in the task's notification value as bits may get
-                     * set by the notifying task or interrupt. This can be used
-                     * to clear the value to zero. */
-                    pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ] &= ~ulBitsToClearOnEntry;
-
-                    /* Mark this task as waiting for a notification. */
-                    pxCurrentTCB->ucNotifyState[ uxIndexToWaitOn ] = taskWAITING_NOTIFICATION;
-
-                    if( xTicksToWait > ( TickType_t ) 0 )
+                    /* Only block if a notification is not already pending. */
+                    if( pxCurrentTCB->ucNotifyState[ uxIndexToWaitOn ] != taskNOTIFICATION_RECEIVED )
                     {
+                        /* Clear bits in the task's notification value as bits may get
+                         * set by the notifying task or interrupt. This can be used
+                         * to clear the value to zero. */
+                        pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ] &= ~ulBitsToClearOnEntry;
+
+                        /* Mark this task as waiting for a notification. */
+                        pxCurrentTCB->ucNotifyState[ uxIndexToWaitOn ] = taskWAITING_NOTIFICATION;
+
+                        /* Arrange to wait for a notification. */
                         xShouldBlock = pdTRUE;
                     }
                     else
@@ -7792,37 +7794,33 @@ TickType_t uxTaskResetEventItemValue( void )
                         mtCOVERAGE_TEST_MARKER();
                     }
                 }
+                taskEXIT_CRITICAL();
+
+                /* We are now out of the critical section but the scheduler is still
+                 * suspended, so we are safe to do non-deterministic operations such
+                 * as prvAddCurrentTaskToDelayedList. */
+                if( xShouldBlock == pdTRUE )
+                {
+                    traceTASK_NOTIFY_WAIT_BLOCK( uxIndexToWaitOn );
+                    prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+                }
                 else
                 {
                     mtCOVERAGE_TEST_MARKER();
                 }
             }
-            taskEXIT_CRITICAL();
+            xAlreadyYielded = xTaskResumeAll();
 
-            /* We are now out of the critical section but the scheduler is still
-             * suspended, so we are safe to do non-deterministic operations such
-             * as prvAddCurrentTaskToDelayedList. */
-            if( xShouldBlock == pdTRUE )
+            /* Force a reschedule if xTaskResumeAll has not already done so. */
+            if( ( xShouldBlock == pdTRUE ) && ( xAlreadyYielded == pdFALSE ) )
             {
-                traceTASK_NOTIFY_WAIT_BLOCK( uxIndexToWaitOn );
-                prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+                taskYIELD_WITHIN_API();
             }
             else
             {
                 mtCOVERAGE_TEST_MARKER();
             }
         }
-        xAlreadyYielded = xTaskResumeAll();
-
-        /* Force a reschedule if xTaskResumeAll has not already done so. */
-        if( ( xShouldBlock == pdTRUE ) && ( xAlreadyYielded == pdFALSE ) )
-        {
-            taskYIELD_WITHIN_API();
-        }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
-        }
 
         taskENTER_CRITICAL();
         {

From f239da06ec2d2cbe2629a2be8227c5aa9998644c Mon Sep 17 00:00:00 2001
From: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Date: Wed, 13 Nov 2024 13:31:41 +0530
Subject: [PATCH 350/424] Add xPortResetHeapMinimumEverFreeHeapSize to heap5
 (#1191)

The same was added to heap 4 in this PR - https://github.com/FreeRTOS/FreeRTOS-Kernel/pull/1189.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 portable/MemMang/heap_5.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/portable/MemMang/heap_5.c b/portable/MemMang/heap_5.c
index 0d9598cf1..4e872f615 100644
--- a/portable/MemMang/heap_5.c
+++ b/portable/MemMang/heap_5.c
@@ -457,6 +457,12 @@ size_t xPortGetMinimumEverFreeHeapSize( void )
 }
 /*-----------------------------------------------------------*/
 
+void xPortResetHeapMinimumEverFreeHeapSize( void )
+{
+    xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
 void * pvPortCalloc( size_t xNum,
                      size_t xSize )
 {

From 73f6e3a1b461dd76b3e4d3043badda56d3f0efda Mon Sep 17 00:00:00 2001
From: Graham Sanderson <graham.sanderson@raspberrypi.com>
Date: Wed, 13 Nov 2024 22:17:50 -0600
Subject: [PATCH 351/424] RP2040 Updates: (#1193)

* Standardize on configNUMBER_OF_CORES != 1 to select SMP functionality
* Fix SDK pico_sync interoperability (configSUPPORT_PICO_SYNC_INTEROP == 1)

Co-authored-by: graham sanderson <graham.sanderson@raspeberryi.com>
---
 .../ThirdParty/GCC/RP2040/include/portmacro.h |  40 ++---
 portable/ThirdParty/GCC/RP2040/port.c         | 169 +++++++++---------
 2 files changed, 99 insertions(+), 110 deletions(-)

diff --git a/portable/ThirdParty/GCC/RP2040/include/portmacro.h b/portable/ThirdParty/GCC/RP2040/include/portmacro.h
index 023250884..14f58940c 100644
--- a/portable/ThirdParty/GCC/RP2040/include/portmacro.h
+++ b/portable/ThirdParty/GCC/RP2040/include/portmacro.h
@@ -151,11 +151,12 @@ extern void vPortYield( void );
 
 void vYieldCore( int xCoreID );
 #define portYIELD_CORE( a )                  vYieldCore( a )
-#define portRESTORE_INTERRUPTS( ulState )    __asm volatile ( "msr PRIMASK,%0" ::"r" ( ulState ) : )
 
 /*-----------------------------------------------------------*/
 
 /* Critical nesting count management. */
+#define portCRITICAL_NESTING_IN_TCB    0
+
 extern UBaseType_t uxCriticalNestings[ configNUMBER_OF_CORES ];
 #define portGET_CRITICAL_NESTING_COUNT()          ( uxCriticalNestings[ portGET_CORE_ID() ] )
 #define portSET_CRITICAL_NESTING_COUNT( x )       ( uxCriticalNestings[ portGET_CORE_ID() ] = ( x ) )
@@ -181,9 +182,7 @@ extern void vClearInterruptMaskFromISR( uint32_t ulMask )  __attribute__( ( nake
 #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vClearInterruptMaskFromISR( x )
 
 #define portDISABLE_INTERRUPTS()                  __asm volatile ( " cpsid i " ::: "memory" )
-
-extern void vPortEnableInterrupts();
-#define portENABLE_INTERRUPTS()                   vPortEnableInterrupts()
+#define portENABLE_INTERRUPTS()                   __asm volatile ( " cpsie i " ::: "memory" )
 
 #if ( configNUMBER_OF_CORES == 1 )
     extern void vPortEnterCritical( void );
@@ -203,6 +202,12 @@ extern void vPortEnableInterrupts();
 
 #define portRTOS_SPINLOCK_COUNT    2
 
+#if PICO_SDK_VERSION_MAJOR < 2
+__force_inline static bool spin_try_lock_unsafe(spin_lock_t *lock) {
+   return *lock;
+}
+#endif
+
 /* Note this is a single method with uxAcquire parameter since we have
  * static vars, the method is always called with a compile time constant for
  * uxAcquire, and the compiler should dothe right thing! */
@@ -210,45 +215,36 @@ static inline void vPortRecursiveLock( uint32_t ulLockNum,
                                        spin_lock_t * pxSpinLock,
                                        BaseType_t uxAcquire )
 {
-    static uint8_t ucOwnedByCore[ portMAX_CORE_COUNT ];
-    static uint8_t ucRecursionCountByLock[ portRTOS_SPINLOCK_COUNT ];
+    static volatile uint8_t ucOwnedByCore[ portMAX_CORE_COUNT ][portRTOS_SPINLOCK_COUNT];
+    static volatile uint8_t ucRecursionCountByLock[ portRTOS_SPINLOCK_COUNT ];
 
     configASSERT( ulLockNum < portRTOS_SPINLOCK_COUNT );
     uint32_t ulCoreNum = get_core_num();
-    uint32_t ulLockBit = 1u << ulLockNum;
-    configASSERT( ulLockBit < 256u );
 
     if( uxAcquire )
     {
-        if( __builtin_expect( !*pxSpinLock, 0 ) )
-        {
-            if( ucOwnedByCore[ ulCoreNum ] & ulLockBit )
+        if (!spin_try_lock_unsafe(pxSpinLock)) {
+            if( ucOwnedByCore[ ulCoreNum ][ ulLockNum ] )
             {
                 configASSERT( ucRecursionCountByLock[ ulLockNum ] != 255u );
                 ucRecursionCountByLock[ ulLockNum ]++;
                 return;
             }
-
-            while( __builtin_expect( !*pxSpinLock, 0 ) )
-            {
-            }
+            spin_lock_unsafe_blocking(pxSpinLock);
         }
-
-        __mem_fence_acquire();
         configASSERT( ucRecursionCountByLock[ ulLockNum ] == 0 );
         ucRecursionCountByLock[ ulLockNum ] = 1;
-        ucOwnedByCore[ ulCoreNum ] |= ulLockBit;
+        ucOwnedByCore[ ulCoreNum ][ ulLockNum ] = 1;
     }
     else
     {
-        configASSERT( ( ucOwnedByCore[ ulCoreNum ] & ulLockBit ) != 0 );
+        configASSERT( ( ucOwnedByCore[ ulCoreNum ] [ulLockNum ] ) != 0 );
         configASSERT( ucRecursionCountByLock[ ulLockNum ] != 0 );
 
         if( !--ucRecursionCountByLock[ ulLockNum ] )
         {
-            ucOwnedByCore[ ulCoreNum ] &= ~ulLockBit;
-            __mem_fence_release();
-            *pxSpinLock = 1;
+            ucOwnedByCore[ ulCoreNum ] [ ulLockNum ] = 0;
+            spin_unlock_unsafe(pxSpinLock);
         }
     }
 }
diff --git a/portable/ThirdParty/GCC/RP2040/port.c b/portable/ThirdParty/GCC/RP2040/port.c
index 78c11bd63..37b037e89 100644
--- a/portable/ThirdParty/GCC/RP2040/port.c
+++ b/portable/ThirdParty/GCC/RP2040/port.c
@@ -46,9 +46,6 @@
     #include "pico/multicore.h"
 #endif /* LIB_PICO_MULTICORE */
 
-/* TODO : consider to remove this macro. */
-#define portRUNNING_ON_BOTH_CORES             ( configNUMBER_OF_CORES == portMAX_CORE_COUNT )
-
 /* Constants required to manipulate the NVIC. */
 #define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )
 #define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )
@@ -123,22 +120,21 @@ UBaseType_t uxCriticalNestings[ configNUMBER_OF_CORES ] = { 0 };
 
 /*-----------------------------------------------------------*/
 
+#if ( configSUPPORT_PICO_SYNC_INTEROP == 1 || configNUMBER_OF_CORES > 1 )
+    #include "hardware/irq.h"
+#endif /* ( configSUPPORT_PICO_SYNC_INTEROP == 1 || configNUMBER_OF_CORES > 1 ) */
 #if ( configSUPPORT_PICO_SYNC_INTEROP == 1 )
     #include "pico/lock_core.h"
-    #include "hardware/irq.h"
     #include "event_groups.h"
     #if configSUPPORT_STATIC_ALLOCATION
         static StaticEventGroup_t xStaticEventGroup;
         #define pEventGroup    ( &xStaticEventGroup )
     #endif /* configSUPPORT_STATIC_ALLOCATION */
     static EventGroupHandle_t xEventGroup;
-    #if ( portRUNNING_ON_BOTH_CORES == 0 )
+    #if ( configNUMBER_OF_CORES == 1 )
         static EventBits_t uxCrossCoreEventBits;
-        static spin_lock_t * pxCrossCoreSpinLock;
+        static spin_lock_t * pxCrossCoreSpinLock; /* protects uxCrossCoreEventBits */
     #endif
-
-    static spin_lock_t * pxYieldSpinLock[ configNUMBER_OF_CORES ];
-    static uint32_t ulYieldSpinLockSaveValue[ configNUMBER_OF_CORES ];
 #endif /* configSUPPORT_PICO_SYNC_INTEROP */
 
 /*
@@ -171,7 +167,7 @@ UBaseType_t uxCriticalNestings[ configNUMBER_OF_CORES ] = { 0 };
 static uint8_t ucPrimaryCoreNum = INVALID_PRIMARY_CORE_NUM;
 
 /* Note: portIS_FREE_RTOS_CORE() also returns false until the scheduler is started */
-#if ( portRUNNING_ON_BOTH_CORES == 1 )
+#if ( configNUMBER_OF_CORES != 1 )
     #define portIS_FREE_RTOS_CORE()    ( ucPrimaryCoreNum != INVALID_PRIMARY_CORE_NUM )
 #else
     #define portIS_FREE_RTOS_CORE()    ( ucPrimaryCoreNum == get_core_num() )
@@ -247,16 +243,16 @@ void vPortStartFirstTask( void )
                 "   ldr r0, [r0]                    \n"
                 "   msr msp, r0                     \n" /* Set the msp back to the start of the stack. */
             #endif /* configRESET_STACK_POINTER */
-            #if portRUNNING_ON_BOTH_CORES
+            #if ( configNUMBER_OF_CORES != 1 )
                 "   adr r1, ulAsmLocals             \n" /* Get the location of the current TCB for the current core. */
                 "   ldmia r1!, {r2, r3}             \n"
                 "   ldr r2, [r2]                    \n" /* r2 = Core number */
                 "   lsls r2, #2                     \n"
                 "   ldr r3, [r3, r2]                \n" /* r3 = pxCurrentTCBs[get_core_num()] */
-            #else
+            #else /* configNUMBER_OF_CORES != 1 */
                 "   ldr r3, =pxCurrentTCBs          \n"
                 "   ldr r3, [r3]                    \n"  /* r3 = pxCurrentTCBs[0] */
-            #endif /* portRUNNING_ON_BOTH_CORES */
+            #endif /* configNUMBER_OF_CORES != 1 */
             "    ldr  r0, [r3]                       \n" /* The first item in pxCurrentTCB is the task top of stack. */
             "    adds r0, #32                        \n" /* Discard everything up to r0. */
             "    msr  psp, r0                        \n" /* This is now the new top of stack to use in the task. */
@@ -269,7 +265,7 @@ void vPortStartFirstTask( void )
             "    pop  {r2}                           \n" /* Pop and discard XPSR. */
             "    cpsie i                             \n" /* The first task has its context and interrupts can be enabled. */
             "    bx   r3                             \n" /* Finally, jump to the user defined task code. */
-            #if portRUNNING_ON_BOTH_CORES
+            #if configNUMBER_OF_CORES != 1
                 "                                   \n"
                 "     .align 4                      \n"
                 "ulAsmLocals:                       \n"
@@ -291,7 +287,7 @@ void vPortStartFirstTask( void )
         /* And explicitly clear any other IRQ flags. */
         multicore_fifo_clear_irq();
 
-        #if ( portRUNNING_ON_BOTH_CORES == 1 )
+        #if ( configNUMBER_OF_CORES != 1 )
             portYIELD_FROM_ISR( pdTRUE );
         #elif ( configSUPPORT_PICO_SYNC_INTEROP == 1 )
             BaseType_t xHigherPriorityTaskWoken = pdFALSE;
@@ -301,7 +297,7 @@ void vPortStartFirstTask( void )
             spin_unlock( pxCrossCoreSpinLock, ulSave );
             xEventGroupSetBitsFromISR( xEventGroup, ulBits, &xHigherPriorityTaskWoken );
             portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
-        #endif /* portRUNNING_ON_BOTH_CORES */
+        #endif /* configNUMBER_OF_CORES != 1 */
     }
 #endif /* if ( LIB_PICO_MULTICORE == 1 ) && ( configSUPPORT_PICO_SYNC_INTEROP == 1 ) */
 
@@ -346,23 +342,21 @@ void vPortStartFirstTask( void )
         /* Should never get here as the tasks will now be executing!  Call the task
          * exit error function to prevent compiler warnings about a static function
          * not being called in the case that the application writer overrides this
-         * functionality by defining configTASK_RETURN_ADDRESS.  Call
-         * vTaskSwitchContext() so link time optimisation does not remove the
+         * functionality by defining configTASK_RETURN_ADDRESS. Call
+         * vTaskSwitchContext() so link time optimization does not remove the
          * symbol. */
         vTaskSwitchContext( portGET_CORE_ID() );
         prvTaskExitError();
 
-        /* Should not get here! */
+        /* Should not get here. */
         return 0;
     }
 
-    #if portRUNNING_ON_BOTH_CORES
-        static void prvDisableInterruptsAndPortStartSchedulerOnCore( void )
-        {
-            portDISABLE_INTERRUPTS();
-            xPortStartSchedulerOnCore();
-        }
-    #endif
+    static void prvDisableInterruptsAndPortStartSchedulerOnCore( void )
+    {
+        portDISABLE_INTERRUPTS();
+        xPortStartSchedulerOnCore();
+    }
 
 /*
  * See header file for description.
@@ -375,7 +369,7 @@ void vPortStartFirstTask( void )
         spin_lock_claim( configSMP_SPINLOCK_0 );
         spin_lock_claim( configSMP_SPINLOCK_1 );
 
-        #if portRUNNING_ON_BOTH_CORES
+        #if configNUMBER_OF_CORES != 1
             ucPrimaryCoreNum = configTICK_CORE;
             configASSERT( get_core_num() == 0 ); /* we must be started on core 0 */
             multicore_reset_core1();
@@ -418,7 +412,7 @@ void vPortStartFirstTask( void )
             #if ( configSUPPORT_PICO_SYNC_INTEROP == 1 )
                 multicore_fifo_clear_irq();
                 multicore_fifo_drain();
-                uint32_t irq_num = 15 + get_core_num();
+                uint32_t irq_num = SIO_IRQ_PROC0 + get_core_num();
                 irq_set_priority( irq_num, portMIN_INTERRUPT_PRIORITY );
                 irq_set_exclusive_handler( irq_num, prvFIFOInterruptHandler );
                 irq_set_enabled( irq_num, 1 );
@@ -431,8 +425,8 @@ void vPortStartFirstTask( void )
         /* Should never get here as the tasks will now be executing!  Call the task
          * exit error function to prevent compiler warnings about a static function
          * not being called in the case that the application writer overrides this
-         * functionality by defining configTASK_RETURN_ADDRESS.  Call
-         * vTaskSwitchContext() so link time optimisation does not remove the
+         * functionality by defining configTASK_RETURN_ADDRESS. Call
+         * vTaskSwitchContext() so link time optimization does not remove the
          * symbol. */
         vTaskSwitchContext();
         prvTaskExitError();
@@ -446,20 +440,14 @@ void vPortStartFirstTask( void )
 
 void vPortEndScheduler( void )
 {
-    /* Not implemented in ports where there is nothing to return to. */
-    panic_unsupported();
+    /* Not implemented in ports where there is nothing to return to.
+     * Artificially force an assert. */
+    configASSERT( portGET_CORE_ID() == 1000UL );
 }
 /*-----------------------------------------------------------*/
 
 void vPortYield( void )
 {
-    #if ( configSUPPORT_PICO_SYNC_INTEROP == 1 )
-
-        /* We are not in an ISR, and pxYieldSpinLock is always dealt with and
-         * cleared when interrupts are re-enabled, so should be NULL */
-        configASSERT( pxYieldSpinLock[ portGET_CORE_ID() ] == NULL );
-    #endif /* configSUPPORT_PICO_SYNC_INTEROP */
-
     /* Set a PendSV to request a context switch. */
     portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
 
@@ -495,21 +483,6 @@ void vPortYield( void )
     }
 #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
 
-void vPortEnableInterrupts( void )
-{
-    #if ( configSUPPORT_PICO_SYNC_INTEROP == 1 )
-        int xCoreID = ( int ) portGET_CORE_ID();
-
-        if( pxYieldSpinLock[ xCoreID ] )
-        {
-            spin_lock_t * const pxTmpLock = pxYieldSpinLock[ xCoreID ];
-            pxYieldSpinLock[ xCoreID ] = NULL;
-            spin_unlock( pxTmpLock, ulYieldSpinLockSaveValue[ xCoreID ] );
-        }
-    #endif
-    __asm volatile ( " cpsie i " ::: "memory" );
-}
-
 /*-----------------------------------------------------------*/
 
 uint32_t ulSetInterruptMaskFromISR( void )
@@ -542,7 +515,7 @@ void vYieldCore( int xCoreID )
 
     configASSERT( xCoreID != ( int ) portGET_CORE_ID() );
 
-    #if portRUNNING_ON_BOTH_CORES
+    #if configNUMBER_OF_CORES != 1
 
         /* Non blocking, will cause interrupt on other core if the queue isn't already full,
          * in which case an IRQ must be pending */
@@ -645,7 +618,7 @@ void xPortPendSVHandler( void )
             "                                       \n"
             "   adr    r0, ulAsmLocals2             \n" /* Get the location of the current TCB for the current core. */
             "   ldmia r0!, {r2, r3}                 \n"
-            #if portRUNNING_ON_BOTH_CORES
+            #if configNUMBER_OF_CORES != 1
                 "   ldr r0, [r2]                    \n" /* r0 = Core number */
                 "   lsls r0, r0, #2                 \n"
                 "   adds r3, r0                     \n" /* r3 = &pxCurrentTCBs[get_core_num()] */
@@ -685,11 +658,11 @@ void xPortPendSVHandler( void )
                 "   subs r1, r1, #48                \n"
                 "   stmia r1!, {r4-r7}              \n"
             #endif /* portUSE_DIVIDER_SAVE_RESTORE */
-            #if portRUNNING_ON_BOTH_CORES
+            #if configNUMBER_OF_CORES != 1
                 "   ldr r0, [r2]                    \n" /* r0 = Core number */
             #else
                 "   movs r0, #0                     \n"
-            #endif /* portRUNNING_ON_BOTH_CORES */
+            #endif /* configNUMBER_OF_CORES != 1 */
             "   push {r3, r14}                      \n"
             "   cpsid i                             \n"
             "   bl vTaskSwitchContext               \n"
@@ -1001,10 +974,10 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
         #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
             ulBit = 1u << ( spin_lock_get_num( spinLock ) & 0x7u );
         #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
-            ulBit = 1u << spin_lock_get_num( spinLock );
-            /* reduce to range 0-24 */
-            ulBit |= ulBit << 8u;
-            ulBit >>= 8u;
+            /* Avoid potential use of SIO divider for % here out of abundance of caution */
+            ulBit = spin_lock_get_num( spinLock );
+            if (ulBit >= 24) ulBit -= 24;
+            ulBit = 1u << ulBit;
         #endif /* configTICK_TYPE_WIDTH_IN_BITS */
         return ( EventBits_t ) ulBit;
     }
@@ -1022,8 +995,8 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
                                               uint32_t ulSave )
     {
         configASSERT( !portCHECK_IF_IN_ISR() );
+        configASSERT( pxLock->spin_lock );
 
-        /* note no need to check LIB_PICO_MULTICORE, as this is always returns true if that is not defined */
         if( !portIS_FREE_RTOS_CORE() )
         {
             spin_unlock( pxLock->spin_lock, ulSave );
@@ -1031,15 +1004,43 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
         }
         else
         {
-            configASSERT( pxYieldSpinLock[ portGET_CORE_ID() ] == NULL );
-
-            /* we want to hold the lock until the event bits have been set; since interrupts are currently disabled */
-            /* by the spinlock, we can defer until portENABLE_INTERRUPTS is called which is always called when */
-            /* the scheduler is unlocked during this call */
-            configASSERT( pxLock->spin_lock );
-            int xCoreID = ( int ) portGET_CORE_ID();
-            pxYieldSpinLock[ xCoreID ] = pxLock->spin_lock;
-            ulYieldSpinLockSaveValue[ xCoreID ] = ulSave;
+            /* The requirement (from the SDK) on this implementation is that this method
+             * should always wake up from a corresponding call to vPortLockInternalSpinUnlockWithNotify
+             * that happens after this method is called.
+             *
+             * The moment that we unlock the spin lock, we need to be sure that
+             * there is no way that we end up blocking in xEventGroupWaitBits,
+             * despite the fact that other tasks can now run, if the corresponding
+             * unlock has occurred.
+             *
+             * Previously the RP2xxx ports used to attempt to disable IRQs until the
+             * task actually (potentially) became blocked by hooking the IRQ re-enable
+             * when xEventGroupWaitBits completes (or switches tasks), but this
+             * was a broken hack, in that IRQs are re-enabled at other points during
+             * that call.
+             *
+             * This deferred IRQ enable is not actually needed, because all we
+             * care about is that:
+             *
+             * Even in the presence of other tasks acquiring then releasing
+             * the lock, between the interrupt_enable and the xEventGroupWaitBits,
+             * the corresponding bit will still be set.
+             *
+             * This is the case, even any intervening blocked lock (which
+             * clears the event bit) will need to unlock it before we proceed,
+             * which will set the event bit again.
+             *
+             * The multiplexing down of multiple spin lock numbers to fewer
+             * event bits does not cause a possible race condition,
+             * but it does mean that a task waiting for lock A can be
+             * blocked by a task B which owns another lock.
+             *
+             * This could be fixed by using an array of event groups, however
+             * since the SDK spin locks are generally intended for very short
+             * term usage anyway, and rarely nested except in exotic cases
+             * like video output, we'll leave it as one event group for now
+             */
+            spin_unlock( pxLock->spin_lock, ulSave);
             xEventGroupWaitBits( xEventGroup, prvGetEventGroupBit( pxLock->spin_lock ),
                                  pdTRUE, pdFALSE, portMAX_DELAY );
         }
@@ -1072,11 +1073,7 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
         else
         {
             __sev();
-            #if ( portRUNNING_ON_BOTH_CORES == 0 )
-
-                /* We could sent the bits across the FIFO which would have required us to block here if the FIFO was full,
-                 * or we could have just set all bits on the other side, however it seems reasonable instead to take
-                 * the hit of another spin lock to protect an accurate bit set. */
+            #if ( configNUMBER_OF_CORES == 1 )
                 if( pxCrossCoreSpinLock != pxLock->spin_lock )
                 {
                     spin_lock_unsafe_blocking( pxCrossCoreSpinLock );
@@ -1090,7 +1087,7 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
 
                 /* This causes fifo irq on the other (FreeRTOS) core which will do the set the event bits */
                 sio_hw->fifo_wr = 0;
-            #endif /* portRUNNING_ON_BOTH_CORES == 0 */
+            #endif /* configNUMBER_OF_CORES == 1 */
             spin_unlock( pxLock->spin_lock, ulSave );
         }
     }
@@ -1100,6 +1097,7 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
                                                                  absolute_time_t uxUntil )
     {
         configASSERT( !portCHECK_IF_IN_ISR() );
+        configASSERT( pxLock->spin_lock );
 
         /* note no need to check LIB_PICO_MULTICORE, as this is always returns true if that is not defined */
         if( !portIS_FREE_RTOS_CORE() )
@@ -1110,19 +1108,14 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
         else
         {
             configASSERT( portIS_FREE_RTOS_CORE() );
-            configASSERT( pxYieldSpinLock[ portGET_CORE_ID() ] == NULL );
 
             TickType_t uxTicksToWait = prvGetTicksToWaitBefore( uxUntil );
 
             if( uxTicksToWait )
             {
-                /* We want to hold the lock until the event bits have been set; since interrupts are currently disabled
-                 * by the spinlock, we can defer until portENABLE_INTERRUPTS is called which is always called when
-                 * the scheduler is unlocked during this call */
-                configASSERT( pxLock->spin_lock );
-                int xCoreID = ( int ) portGET_CORE_ID();
-                pxYieldSpinLock[ xCoreID ] = pxLock->spin_lock;
-                ulYieldSpinLockSaveValue[ xCoreID ] = ulSave;
+                /* See comment in vPortLockInternalSpinUnlockWithWait for detail
+                 * about possible race conditions */
+                spin_unlock( pxLock->spin_lock, ulSave );
                 xEventGroupWaitBits( xEventGroup,
                                      prvGetEventGroupBit( pxLock->spin_lock ), pdTRUE,
                                      pdFALSE, uxTicksToWait );
@@ -1152,9 +1145,9 @@ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
         {
             /* This must be done even before the scheduler is started, as the spin lock
              * is used by the overrides of the SDK wait/notify primitives */
-            #if ( portRUNNING_ON_BOTH_CORES == 0 )
+            #if ( configNUMBER_OF_CORES == 1 )
                 pxCrossCoreSpinLock = spin_lock_instance( next_striped_spin_lock_num() );
-            #endif /* portRUNNING_ON_BOTH_CORES */
+            #endif /* configNUMBER_OF_CORES == 1 */
 
             /* The event group is not used prior to scheduler init, but is initialized
              * here to since it logically belongs with the spin lock */

From 25f9222fed15d0768c007fa22f7de711f474d1b3 Mon Sep 17 00:00:00 2001
From: Ahmed Ismail <64546783+AhmedIsmail02@users.noreply.github.com>
Date: Thu, 14 Nov 2024 04:31:06 +0000
Subject: [PATCH 352/424] armv8.1-m: Remove portHAS_PACBTI_FEATURE macro
 (#1192)

The PACBTI is an optional hardware security feature,
the current implementation assumes that every SoC that
has Armv8.1-M architecture extension, has the PACBTI
hardware feature, which does not have to be the case.
Hence, the `portHAS_PACBTI_FEATURE` is removed
and the implementation is modified to rely on
`configENABLE_PAC` and `configENABLE_BTI` macros
that can either be set using CMake or FreeRTOSConfig.h
header file.

Enabling PAC and/or BTI on a port variant that
doesn't have the PACBTI hardware feature would be
caught by a `configASSERT` statement.

Signed-off-by: Ahmed Ismail <Ahmed.Ismail@arm.com>
Co-authored-by: Tony Josi <tonyjosi@amazon.com>
---
 include/FreeRTOS.h                            | 12 ++++----
 portable/ARMv8M/non_secure/port.c             | 28 ++++++++-----------
 .../portable/GCC/ARM_CM23/portmacro.h         |  3 --
 .../portable/GCC/ARM_CM23_NTZ/portmacro.h     |  3 --
 .../portable/GCC/ARM_CM33/portmacro.h         |  3 --
 .../portable/GCC/ARM_CM33_NTZ/portmacro.h     |  3 --
 .../portable/GCC/ARM_CM35P/portmacro.h        |  3 --
 .../portable/GCC/ARM_CM55/portmacro.h         |  3 --
 .../portable/GCC/ARM_CM85/portmacro.h         |  3 --
 .../portable/IAR/ARM_CM23/portmacro.h         |  3 --
 .../portable/IAR/ARM_CM23_NTZ/portmacro.h     |  3 --
 .../portable/IAR/ARM_CM33/portmacro.h         |  3 --
 .../portable/IAR/ARM_CM33_NTZ/portmacro.h     |  3 --
 .../portable/IAR/ARM_CM35P/portmacro.h        |  3 --
 .../portable/IAR/ARM_CM55/portmacro.h         |  3 --
 .../portable/IAR/ARM_CM85/portmacro.h         |  3 --
 portable/GCC/ARM_CM23/non_secure/port.c       | 28 ++++++++-----------
 portable/GCC/ARM_CM23/non_secure/portmacro.h  |  3 --
 portable/GCC/ARM_CM23_NTZ/non_secure/port.c   | 28 ++++++++-----------
 .../GCC/ARM_CM23_NTZ/non_secure/portmacro.h   |  3 --
 portable/GCC/ARM_CM33/non_secure/port.c       | 28 ++++++++-----------
 portable/GCC/ARM_CM33/non_secure/portmacro.h  |  3 --
 portable/GCC/ARM_CM33_NTZ/non_secure/port.c   | 28 ++++++++-----------
 .../GCC/ARM_CM33_NTZ/non_secure/portmacro.h   |  3 --
 portable/GCC/ARM_CM35P/non_secure/port.c      | 28 ++++++++-----------
 portable/GCC/ARM_CM35P/non_secure/portmacro.h |  3 --
 portable/GCC/ARM_CM35P_NTZ/non_secure/port.c  | 28 ++++++++-----------
 .../GCC/ARM_CM35P_NTZ/non_secure/portmacro.h  |  3 --
 portable/GCC/ARM_CM55/non_secure/port.c       | 28 ++++++++-----------
 portable/GCC/ARM_CM55/non_secure/portmacro.h  |  3 --
 portable/GCC/ARM_CM55_NTZ/non_secure/port.c   | 28 ++++++++-----------
 .../GCC/ARM_CM55_NTZ/non_secure/portmacro.h   |  3 --
 portable/GCC/ARM_CM85/non_secure/port.c       | 28 ++++++++-----------
 portable/GCC/ARM_CM85/non_secure/portmacro.h  |  3 --
 portable/GCC/ARM_CM85_NTZ/non_secure/port.c   | 28 ++++++++-----------
 .../GCC/ARM_CM85_NTZ/non_secure/portmacro.h   |  3 --
 portable/IAR/ARM_CM23/non_secure/port.c       | 28 ++++++++-----------
 portable/IAR/ARM_CM23/non_secure/portmacro.h  |  3 --
 portable/IAR/ARM_CM23_NTZ/non_secure/port.c   | 28 ++++++++-----------
 .../IAR/ARM_CM23_NTZ/non_secure/portmacro.h   |  3 --
 portable/IAR/ARM_CM33/non_secure/port.c       | 28 ++++++++-----------
 portable/IAR/ARM_CM33/non_secure/portmacro.h  |  3 --
 portable/IAR/ARM_CM33_NTZ/non_secure/port.c   | 28 ++++++++-----------
 .../IAR/ARM_CM33_NTZ/non_secure/portmacro.h   |  3 --
 portable/IAR/ARM_CM35P/non_secure/port.c      | 28 ++++++++-----------
 portable/IAR/ARM_CM35P/non_secure/portmacro.h |  3 --
 portable/IAR/ARM_CM35P_NTZ/non_secure/port.c  | 28 ++++++++-----------
 .../IAR/ARM_CM35P_NTZ/non_secure/portmacro.h  |  3 --
 portable/IAR/ARM_CM55/non_secure/port.c       | 28 ++++++++-----------
 portable/IAR/ARM_CM55/non_secure/portmacro.h  |  3 --
 portable/IAR/ARM_CM55_NTZ/non_secure/port.c   | 28 ++++++++-----------
 .../IAR/ARM_CM55_NTZ/non_secure/portmacro.h   |  3 --
 portable/IAR/ARM_CM85/non_secure/port.c       | 28 ++++++++-----------
 portable/IAR/ARM_CM85/non_secure/portmacro.h  |  3 --
 portable/IAR/ARM_CM85_NTZ/non_secure/port.c   | 28 ++++++++-----------
 .../IAR/ARM_CM85_NTZ/non_secure/portmacro.h   |  3 --
 56 files changed, 257 insertions(+), 445 deletions(-)

diff --git a/include/FreeRTOS.h b/include/FreeRTOS.h
index 8849adc84..3fecbdd73 100644
--- a/include/FreeRTOS.h
+++ b/include/FreeRTOS.h
@@ -3034,14 +3034,12 @@
 
 /* Set configENABLE_PAC and/or configENABLE_BTI to 1 to enable PAC and/or BTI
  * support and 0 to disable them. These are currently used in ARMv8.1-M ports. */
-#if ( portHAS_PACBTI_FEATURE == 1 )
-    #ifndef configENABLE_PAC
-        #define configENABLE_PAC    0
-    #endif
+#ifndef configENABLE_PAC
+    #define configENABLE_PAC    0
+#endif
 
-    #ifndef configENABLE_BTI
-        #define configENABLE_BTI    0
-    #endif
+#ifndef configENABLE_BTI
+    #define configENABLE_BTI    0
 #endif
 
 /* Sometimes the FreeRTOSConfig.h settings only allow a task to be created using
diff --git a/portable/ARMv8M/non_secure/port.c b/portable/ARMv8M/non_secure/port.c
index a33dfa43c..5492c367a 100644
--- a/portable/ARMv8M/non_secure/port.c
+++ b/portable/ARMv8M/non_secure/port.c
@@ -380,7 +380,7 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to check and configure PACBTI security feature implementation.
  */
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
 
@@ -389,7 +389,7 @@ typedef void ( * portISR_t )( void );
     #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
     #define portCONTROL_BTI_EN       ( 1UL << 4UL )
 
-#endif /* portHAS_PACBTI_FEATURE */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
 
 /**
@@ -427,7 +427,7 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
 /**
  * @brief Configures PACBTI features.
@@ -445,7 +445,7 @@ static void prvTaskExitError( void );
  */
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
 
-#endif /* portHAS_PACBTI_FEATURE */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
 /**
  * @brief Setup the timer to generate the tick interrupts.
@@ -1541,13 +1541,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
-        #if ( portHAS_PACBTI_FEATURE == 1 )
+        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
         {
             /* Check PACBTI security feature configuration before pushing the
              * CONTROL register's value on task's TCB. */
             ulControl = prvConfigurePACBTI( pdFALSE );
         }
-        #endif /* portHAS_PACBTI_FEATURE */
+        #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
         if( xRunPrivileged == pdTRUE )
         {
@@ -1786,13 +1786,13 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
-    #if ( portHAS_PACBTI_FEATURE == 1 )
+    #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
     {
         /* Set the CONTROL register value based on PACBTI security feature
          * configuration before starting the first task. */
         ( void) prvConfigurePACBTI( pdTRUE );
     }
-    #endif /* portHAS_PACBTI_FEATURE */
+    #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
     #if ( configENABLE_MPU == 1 )
     {
@@ -2213,7 +2213,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
     {
@@ -2222,12 +2222,8 @@ BaseType_t xPortIsInsideInterrupt( void )
         /* Ensure that PACBTI is implemented. */
         configASSERT( portID_ISAR5_REG != 0x0 );
 
-        /* Enable UsageFault exception if PAC or BTI is enabled. */
-        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
-        {
-            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
-        }
-        #endif
+        /* Enable UsageFault exception. */
+        portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
 
         #if( configENABLE_PAC == 1 )
         {
@@ -2249,5 +2245,5 @@ BaseType_t xPortIsInsideInterrupt( void )
         return ulControl;
     }
 
-#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h
index 5acf8160f..a7f9db767 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h
@@ -1,8 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * Copyright 2024 Arm Limited and/or its affiliates
- * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -53,7 +51,6 @@
 #define portARCH_NAME                    "Cortex-M23"
 #define portHAS_ARMV8M_MAIN_EXTENSION    0
 #define portARMV8M_MINOR_VERSION         0
-#define portHAS_PACBTI_FEATURE           0
 #define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h
index 5acf8160f..a7f9db767 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h
@@ -1,8 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * Copyright 2024 Arm Limited and/or its affiliates
- * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -53,7 +51,6 @@
 #define portARCH_NAME                    "Cortex-M23"
 #define portHAS_ARMV8M_MAIN_EXTENSION    0
 #define portARMV8M_MINOR_VERSION         0
-#define portHAS_PACBTI_FEATURE           0
 #define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h
index 452a43655..0fc61f23c 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h
@@ -1,8 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * Copyright 2024 Arm Limited and/or its affiliates
- * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -53,7 +51,6 @@
 #define portARCH_NAME                    "Cortex-M33"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
 #define portARMV8M_MINOR_VERSION         0
-#define portHAS_PACBTI_FEATURE           0
 #define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h
index 452a43655..0fc61f23c 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h
@@ -1,8 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * Copyright 2024 Arm Limited and/or its affiliates
- * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -53,7 +51,6 @@
 #define portARCH_NAME                    "Cortex-M33"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
 #define portARMV8M_MINOR_VERSION         0
-#define portHAS_PACBTI_FEATURE           0
 #define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM35P/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM35P/portmacro.h
index 82b84f92a..4db6e6d4a 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM35P/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM35P/portmacro.h
@@ -1,8 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * Copyright 2024 Arm Limited and/or its affiliates
- * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -53,7 +51,6 @@
 #define portARCH_NAME                    "Cortex-M35P"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
 #define portARMV8M_MINOR_VERSION         0
-#define portHAS_PACBTI_FEATURE           0
 #define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM55/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM55/portmacro.h
index 369d6825f..c6a179c52 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM55/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM55/portmacro.h
@@ -1,8 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * Copyright 2024 Arm Limited and/or its affiliates
- * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -58,7 +56,6 @@
 #define portARCH_NAME                    "Cortex-M55"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
 #define portARMV8M_MINOR_VERSION         1
-#define portHAS_PACBTI_FEATURE           0
 #define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM85/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM85/portmacro.h
index 5067aa573..7e14f2696 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM85/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM85/portmacro.h
@@ -1,8 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * Copyright 2024 Arm Limited and/or its affiliates
- * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -58,7 +56,6 @@
 #define portARCH_NAME                    "Cortex-M85"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
 #define portARMV8M_MINOR_VERSION         1
-#define portHAS_PACBTI_FEATURE           1
 #define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h
index 4940e345e..9dfcc9132 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h
@@ -1,8 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * Copyright 2024 Arm Limited and/or its affiliates
- * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -53,7 +51,6 @@
 #define portARCH_NAME                    "Cortex-M23"
 #define portHAS_ARMV8M_MAIN_EXTENSION    0
 #define portARMV8M_MINOR_VERSION         0
-#define portHAS_PACBTI_FEATURE           0
 #define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h
index 4940e345e..9dfcc9132 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h
@@ -1,8 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * Copyright 2024 Arm Limited and/or its affiliates
- * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -53,7 +51,6 @@
 #define portARCH_NAME                    "Cortex-M23"
 #define portHAS_ARMV8M_MAIN_EXTENSION    0
 #define portARMV8M_MINOR_VERSION         0
-#define portHAS_PACBTI_FEATURE           0
 #define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h
index 5e126dbf9..0f7d100df 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h
@@ -1,8 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * Copyright 2024 Arm Limited and/or its affiliates
- * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -53,7 +51,6 @@
 #define portARCH_NAME                    "Cortex-M33"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
 #define portARMV8M_MINOR_VERSION         0
-#define portHAS_PACBTI_FEATURE           0
 #define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h
index 5e126dbf9..0f7d100df 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h
@@ -1,8 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * Copyright 2024 Arm Limited and/or its affiliates
- * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -53,7 +51,6 @@
 #define portARCH_NAME                    "Cortex-M33"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
 #define portARMV8M_MINOR_VERSION         0
-#define portHAS_PACBTI_FEATURE           0
 #define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM35P/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM35P/portmacro.h
index d617ac0c2..0ad1009b6 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM35P/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM35P/portmacro.h
@@ -1,8 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * Copyright 2024 Arm Limited and/or its affiliates
- * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -53,7 +51,6 @@
 #define portARCH_NAME                    "Cortex-M35P"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
 #define portARMV8M_MINOR_VERSION         0
-#define portHAS_PACBTI_FEATURE           0
 #define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM55/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM55/portmacro.h
index 6a5272267..597af66fa 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM55/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM55/portmacro.h
@@ -1,8 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * Copyright 2024 Arm Limited and/or its affiliates
- * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -58,7 +56,6 @@
 #define portARCH_NAME                    "Cortex-M55"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
 #define portARMV8M_MINOR_VERSION         1
-#define portHAS_PACBTI_FEATURE           0
 #define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM85/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM85/portmacro.h
index c88adc77c..ff5c9895d 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM85/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM85/portmacro.h
@@ -1,8 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * Copyright 2024 Arm Limited and/or its affiliates
- * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -58,7 +56,6 @@
 #define portARCH_NAME                    "Cortex-M85"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
 #define portARMV8M_MINOR_VERSION         1
-#define portHAS_PACBTI_FEATURE           1
 #define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
diff --git a/portable/GCC/ARM_CM23/non_secure/port.c b/portable/GCC/ARM_CM23/non_secure/port.c
index a33dfa43c..5492c367a 100644
--- a/portable/GCC/ARM_CM23/non_secure/port.c
+++ b/portable/GCC/ARM_CM23/non_secure/port.c
@@ -380,7 +380,7 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to check and configure PACBTI security feature implementation.
  */
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
 
@@ -389,7 +389,7 @@ typedef void ( * portISR_t )( void );
     #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
     #define portCONTROL_BTI_EN       ( 1UL << 4UL )
 
-#endif /* portHAS_PACBTI_FEATURE */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
 
 /**
@@ -427,7 +427,7 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
 /**
  * @brief Configures PACBTI features.
@@ -445,7 +445,7 @@ static void prvTaskExitError( void );
  */
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
 
-#endif /* portHAS_PACBTI_FEATURE */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
 /**
  * @brief Setup the timer to generate the tick interrupts.
@@ -1541,13 +1541,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
-        #if ( portHAS_PACBTI_FEATURE == 1 )
+        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
         {
             /* Check PACBTI security feature configuration before pushing the
              * CONTROL register's value on task's TCB. */
             ulControl = prvConfigurePACBTI( pdFALSE );
         }
-        #endif /* portHAS_PACBTI_FEATURE */
+        #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
         if( xRunPrivileged == pdTRUE )
         {
@@ -1786,13 +1786,13 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
-    #if ( portHAS_PACBTI_FEATURE == 1 )
+    #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
     {
         /* Set the CONTROL register value based on PACBTI security feature
          * configuration before starting the first task. */
         ( void) prvConfigurePACBTI( pdTRUE );
     }
-    #endif /* portHAS_PACBTI_FEATURE */
+    #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
     #if ( configENABLE_MPU == 1 )
     {
@@ -2213,7 +2213,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
     {
@@ -2222,12 +2222,8 @@ BaseType_t xPortIsInsideInterrupt( void )
         /* Ensure that PACBTI is implemented. */
         configASSERT( portID_ISAR5_REG != 0x0 );
 
-        /* Enable UsageFault exception if PAC or BTI is enabled. */
-        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
-        {
-            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
-        }
-        #endif
+        /* Enable UsageFault exception. */
+        portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
 
         #if( configENABLE_PAC == 1 )
         {
@@ -2249,5 +2245,5 @@ BaseType_t xPortIsInsideInterrupt( void )
         return ulControl;
     }
 
-#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM23/non_secure/portmacro.h b/portable/GCC/ARM_CM23/non_secure/portmacro.h
index 5acf8160f..a7f9db767 100644
--- a/portable/GCC/ARM_CM23/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM23/non_secure/portmacro.h
@@ -1,8 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * Copyright 2024 Arm Limited and/or its affiliates
- * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -53,7 +51,6 @@
 #define portARCH_NAME                    "Cortex-M23"
 #define portHAS_ARMV8M_MAIN_EXTENSION    0
 #define portARMV8M_MINOR_VERSION         0
-#define portHAS_PACBTI_FEATURE           0
 #define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
index a33dfa43c..5492c367a 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
@@ -380,7 +380,7 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to check and configure PACBTI security feature implementation.
  */
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
 
@@ -389,7 +389,7 @@ typedef void ( * portISR_t )( void );
     #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
     #define portCONTROL_BTI_EN       ( 1UL << 4UL )
 
-#endif /* portHAS_PACBTI_FEATURE */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
 
 /**
@@ -427,7 +427,7 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
 /**
  * @brief Configures PACBTI features.
@@ -445,7 +445,7 @@ static void prvTaskExitError( void );
  */
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
 
-#endif /* portHAS_PACBTI_FEATURE */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
 /**
  * @brief Setup the timer to generate the tick interrupts.
@@ -1541,13 +1541,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
-        #if ( portHAS_PACBTI_FEATURE == 1 )
+        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
         {
             /* Check PACBTI security feature configuration before pushing the
              * CONTROL register's value on task's TCB. */
             ulControl = prvConfigurePACBTI( pdFALSE );
         }
-        #endif /* portHAS_PACBTI_FEATURE */
+        #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
         if( xRunPrivileged == pdTRUE )
         {
@@ -1786,13 +1786,13 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
-    #if ( portHAS_PACBTI_FEATURE == 1 )
+    #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
     {
         /* Set the CONTROL register value based on PACBTI security feature
          * configuration before starting the first task. */
         ( void) prvConfigurePACBTI( pdTRUE );
     }
-    #endif /* portHAS_PACBTI_FEATURE */
+    #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
     #if ( configENABLE_MPU == 1 )
     {
@@ -2213,7 +2213,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
     {
@@ -2222,12 +2222,8 @@ BaseType_t xPortIsInsideInterrupt( void )
         /* Ensure that PACBTI is implemented. */
         configASSERT( portID_ISAR5_REG != 0x0 );
 
-        /* Enable UsageFault exception if PAC or BTI is enabled. */
-        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
-        {
-            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
-        }
-        #endif
+        /* Enable UsageFault exception. */
+        portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
 
         #if( configENABLE_PAC == 1 )
         {
@@ -2249,5 +2245,5 @@ BaseType_t xPortIsInsideInterrupt( void )
         return ulControl;
     }
 
-#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h b/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h
index 5acf8160f..a7f9db767 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h
@@ -1,8 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * Copyright 2024 Arm Limited and/or its affiliates
- * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -53,7 +51,6 @@
 #define portARCH_NAME                    "Cortex-M23"
 #define portHAS_ARMV8M_MAIN_EXTENSION    0
 #define portARMV8M_MINOR_VERSION         0
-#define portHAS_PACBTI_FEATURE           0
 #define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/GCC/ARM_CM33/non_secure/port.c b/portable/GCC/ARM_CM33/non_secure/port.c
index a33dfa43c..5492c367a 100644
--- a/portable/GCC/ARM_CM33/non_secure/port.c
+++ b/portable/GCC/ARM_CM33/non_secure/port.c
@@ -380,7 +380,7 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to check and configure PACBTI security feature implementation.
  */
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
 
@@ -389,7 +389,7 @@ typedef void ( * portISR_t )( void );
     #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
     #define portCONTROL_BTI_EN       ( 1UL << 4UL )
 
-#endif /* portHAS_PACBTI_FEATURE */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
 
 /**
@@ -427,7 +427,7 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
 /**
  * @brief Configures PACBTI features.
@@ -445,7 +445,7 @@ static void prvTaskExitError( void );
  */
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
 
-#endif /* portHAS_PACBTI_FEATURE */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
 /**
  * @brief Setup the timer to generate the tick interrupts.
@@ -1541,13 +1541,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
-        #if ( portHAS_PACBTI_FEATURE == 1 )
+        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
         {
             /* Check PACBTI security feature configuration before pushing the
              * CONTROL register's value on task's TCB. */
             ulControl = prvConfigurePACBTI( pdFALSE );
         }
-        #endif /* portHAS_PACBTI_FEATURE */
+        #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
         if( xRunPrivileged == pdTRUE )
         {
@@ -1786,13 +1786,13 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
-    #if ( portHAS_PACBTI_FEATURE == 1 )
+    #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
     {
         /* Set the CONTROL register value based on PACBTI security feature
          * configuration before starting the first task. */
         ( void) prvConfigurePACBTI( pdTRUE );
     }
-    #endif /* portHAS_PACBTI_FEATURE */
+    #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
     #if ( configENABLE_MPU == 1 )
     {
@@ -2213,7 +2213,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
     {
@@ -2222,12 +2222,8 @@ BaseType_t xPortIsInsideInterrupt( void )
         /* Ensure that PACBTI is implemented. */
         configASSERT( portID_ISAR5_REG != 0x0 );
 
-        /* Enable UsageFault exception if PAC or BTI is enabled. */
-        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
-        {
-            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
-        }
-        #endif
+        /* Enable UsageFault exception. */
+        portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
 
         #if( configENABLE_PAC == 1 )
         {
@@ -2249,5 +2245,5 @@ BaseType_t xPortIsInsideInterrupt( void )
         return ulControl;
     }
 
-#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM33/non_secure/portmacro.h b/portable/GCC/ARM_CM33/non_secure/portmacro.h
index 452a43655..0fc61f23c 100644
--- a/portable/GCC/ARM_CM33/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM33/non_secure/portmacro.h
@@ -1,8 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * Copyright 2024 Arm Limited and/or its affiliates
- * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -53,7 +51,6 @@
 #define portARCH_NAME                    "Cortex-M33"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
 #define portARMV8M_MINOR_VERSION         0
-#define portHAS_PACBTI_FEATURE           0
 #define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
index a33dfa43c..5492c367a 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
@@ -380,7 +380,7 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to check and configure PACBTI security feature implementation.
  */
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
 
@@ -389,7 +389,7 @@ typedef void ( * portISR_t )( void );
     #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
     #define portCONTROL_BTI_EN       ( 1UL << 4UL )
 
-#endif /* portHAS_PACBTI_FEATURE */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
 
 /**
@@ -427,7 +427,7 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
 /**
  * @brief Configures PACBTI features.
@@ -445,7 +445,7 @@ static void prvTaskExitError( void );
  */
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
 
-#endif /* portHAS_PACBTI_FEATURE */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
 /**
  * @brief Setup the timer to generate the tick interrupts.
@@ -1541,13 +1541,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
-        #if ( portHAS_PACBTI_FEATURE == 1 )
+        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
         {
             /* Check PACBTI security feature configuration before pushing the
              * CONTROL register's value on task's TCB. */
             ulControl = prvConfigurePACBTI( pdFALSE );
         }
-        #endif /* portHAS_PACBTI_FEATURE */
+        #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
         if( xRunPrivileged == pdTRUE )
         {
@@ -1786,13 +1786,13 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
-    #if ( portHAS_PACBTI_FEATURE == 1 )
+    #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
     {
         /* Set the CONTROL register value based on PACBTI security feature
          * configuration before starting the first task. */
         ( void) prvConfigurePACBTI( pdTRUE );
     }
-    #endif /* portHAS_PACBTI_FEATURE */
+    #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
     #if ( configENABLE_MPU == 1 )
     {
@@ -2213,7 +2213,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
     {
@@ -2222,12 +2222,8 @@ BaseType_t xPortIsInsideInterrupt( void )
         /* Ensure that PACBTI is implemented. */
         configASSERT( portID_ISAR5_REG != 0x0 );
 
-        /* Enable UsageFault exception if PAC or BTI is enabled. */
-        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
-        {
-            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
-        }
-        #endif
+        /* Enable UsageFault exception. */
+        portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
 
         #if( configENABLE_PAC == 1 )
         {
@@ -2249,5 +2245,5 @@ BaseType_t xPortIsInsideInterrupt( void )
         return ulControl;
     }
 
-#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h b/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h
index 452a43655..0fc61f23c 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h
@@ -1,8 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * Copyright 2024 Arm Limited and/or its affiliates
- * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -53,7 +51,6 @@
 #define portARCH_NAME                    "Cortex-M33"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
 #define portARMV8M_MINOR_VERSION         0
-#define portHAS_PACBTI_FEATURE           0
 #define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/GCC/ARM_CM35P/non_secure/port.c b/portable/GCC/ARM_CM35P/non_secure/port.c
index a33dfa43c..5492c367a 100644
--- a/portable/GCC/ARM_CM35P/non_secure/port.c
+++ b/portable/GCC/ARM_CM35P/non_secure/port.c
@@ -380,7 +380,7 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to check and configure PACBTI security feature implementation.
  */
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
 
@@ -389,7 +389,7 @@ typedef void ( * portISR_t )( void );
     #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
     #define portCONTROL_BTI_EN       ( 1UL << 4UL )
 
-#endif /* portHAS_PACBTI_FEATURE */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
 
 /**
@@ -427,7 +427,7 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
 /**
  * @brief Configures PACBTI features.
@@ -445,7 +445,7 @@ static void prvTaskExitError( void );
  */
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
 
-#endif /* portHAS_PACBTI_FEATURE */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
 /**
  * @brief Setup the timer to generate the tick interrupts.
@@ -1541,13 +1541,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
-        #if ( portHAS_PACBTI_FEATURE == 1 )
+        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
         {
             /* Check PACBTI security feature configuration before pushing the
              * CONTROL register's value on task's TCB. */
             ulControl = prvConfigurePACBTI( pdFALSE );
         }
-        #endif /* portHAS_PACBTI_FEATURE */
+        #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
         if( xRunPrivileged == pdTRUE )
         {
@@ -1786,13 +1786,13 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
-    #if ( portHAS_PACBTI_FEATURE == 1 )
+    #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
     {
         /* Set the CONTROL register value based on PACBTI security feature
          * configuration before starting the first task. */
         ( void) prvConfigurePACBTI( pdTRUE );
     }
-    #endif /* portHAS_PACBTI_FEATURE */
+    #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
     #if ( configENABLE_MPU == 1 )
     {
@@ -2213,7 +2213,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
     {
@@ -2222,12 +2222,8 @@ BaseType_t xPortIsInsideInterrupt( void )
         /* Ensure that PACBTI is implemented. */
         configASSERT( portID_ISAR5_REG != 0x0 );
 
-        /* Enable UsageFault exception if PAC or BTI is enabled. */
-        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
-        {
-            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
-        }
-        #endif
+        /* Enable UsageFault exception. */
+        portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
 
         #if( configENABLE_PAC == 1 )
         {
@@ -2249,5 +2245,5 @@ BaseType_t xPortIsInsideInterrupt( void )
         return ulControl;
     }
 
-#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM35P/non_secure/portmacro.h b/portable/GCC/ARM_CM35P/non_secure/portmacro.h
index 82b84f92a..4db6e6d4a 100644
--- a/portable/GCC/ARM_CM35P/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM35P/non_secure/portmacro.h
@@ -1,8 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * Copyright 2024 Arm Limited and/or its affiliates
- * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -53,7 +51,6 @@
 #define portARCH_NAME                    "Cortex-M35P"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
 #define portARMV8M_MINOR_VERSION         0
-#define portHAS_PACBTI_FEATURE           0
 #define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c b/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
index a33dfa43c..5492c367a 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
@@ -380,7 +380,7 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to check and configure PACBTI security feature implementation.
  */
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
 
@@ -389,7 +389,7 @@ typedef void ( * portISR_t )( void );
     #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
     #define portCONTROL_BTI_EN       ( 1UL << 4UL )
 
-#endif /* portHAS_PACBTI_FEATURE */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
 
 /**
@@ -427,7 +427,7 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
 /**
  * @brief Configures PACBTI features.
@@ -445,7 +445,7 @@ static void prvTaskExitError( void );
  */
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
 
-#endif /* portHAS_PACBTI_FEATURE */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
 /**
  * @brief Setup the timer to generate the tick interrupts.
@@ -1541,13 +1541,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
-        #if ( portHAS_PACBTI_FEATURE == 1 )
+        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
         {
             /* Check PACBTI security feature configuration before pushing the
              * CONTROL register's value on task's TCB. */
             ulControl = prvConfigurePACBTI( pdFALSE );
         }
-        #endif /* portHAS_PACBTI_FEATURE */
+        #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
         if( xRunPrivileged == pdTRUE )
         {
@@ -1786,13 +1786,13 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
-    #if ( portHAS_PACBTI_FEATURE == 1 )
+    #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
     {
         /* Set the CONTROL register value based on PACBTI security feature
          * configuration before starting the first task. */
         ( void) prvConfigurePACBTI( pdTRUE );
     }
-    #endif /* portHAS_PACBTI_FEATURE */
+    #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
     #if ( configENABLE_MPU == 1 )
     {
@@ -2213,7 +2213,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
     {
@@ -2222,12 +2222,8 @@ BaseType_t xPortIsInsideInterrupt( void )
         /* Ensure that PACBTI is implemented. */
         configASSERT( portID_ISAR5_REG != 0x0 );
 
-        /* Enable UsageFault exception if PAC or BTI is enabled. */
-        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
-        {
-            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
-        }
-        #endif
+        /* Enable UsageFault exception. */
+        portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
 
         #if( configENABLE_PAC == 1 )
         {
@@ -2249,5 +2245,5 @@ BaseType_t xPortIsInsideInterrupt( void )
         return ulControl;
     }
 
-#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacro.h b/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacro.h
index 82b84f92a..4db6e6d4a 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacro.h
@@ -1,8 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * Copyright 2024 Arm Limited and/or its affiliates
- * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -53,7 +51,6 @@
 #define portARCH_NAME                    "Cortex-M35P"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
 #define portARMV8M_MINOR_VERSION         0
-#define portHAS_PACBTI_FEATURE           0
 #define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/GCC/ARM_CM55/non_secure/port.c b/portable/GCC/ARM_CM55/non_secure/port.c
index a33dfa43c..5492c367a 100644
--- a/portable/GCC/ARM_CM55/non_secure/port.c
+++ b/portable/GCC/ARM_CM55/non_secure/port.c
@@ -380,7 +380,7 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to check and configure PACBTI security feature implementation.
  */
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
 
@@ -389,7 +389,7 @@ typedef void ( * portISR_t )( void );
     #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
     #define portCONTROL_BTI_EN       ( 1UL << 4UL )
 
-#endif /* portHAS_PACBTI_FEATURE */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
 
 /**
@@ -427,7 +427,7 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
 /**
  * @brief Configures PACBTI features.
@@ -445,7 +445,7 @@ static void prvTaskExitError( void );
  */
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
 
-#endif /* portHAS_PACBTI_FEATURE */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
 /**
  * @brief Setup the timer to generate the tick interrupts.
@@ -1541,13 +1541,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
-        #if ( portHAS_PACBTI_FEATURE == 1 )
+        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
         {
             /* Check PACBTI security feature configuration before pushing the
              * CONTROL register's value on task's TCB. */
             ulControl = prvConfigurePACBTI( pdFALSE );
         }
-        #endif /* portHAS_PACBTI_FEATURE */
+        #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
         if( xRunPrivileged == pdTRUE )
         {
@@ -1786,13 +1786,13 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
-    #if ( portHAS_PACBTI_FEATURE == 1 )
+    #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
     {
         /* Set the CONTROL register value based on PACBTI security feature
          * configuration before starting the first task. */
         ( void) prvConfigurePACBTI( pdTRUE );
     }
-    #endif /* portHAS_PACBTI_FEATURE */
+    #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
     #if ( configENABLE_MPU == 1 )
     {
@@ -2213,7 +2213,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
     {
@@ -2222,12 +2222,8 @@ BaseType_t xPortIsInsideInterrupt( void )
         /* Ensure that PACBTI is implemented. */
         configASSERT( portID_ISAR5_REG != 0x0 );
 
-        /* Enable UsageFault exception if PAC or BTI is enabled. */
-        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
-        {
-            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
-        }
-        #endif
+        /* Enable UsageFault exception. */
+        portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
 
         #if( configENABLE_PAC == 1 )
         {
@@ -2249,5 +2245,5 @@ BaseType_t xPortIsInsideInterrupt( void )
         return ulControl;
     }
 
-#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM55/non_secure/portmacro.h b/portable/GCC/ARM_CM55/non_secure/portmacro.h
index 369d6825f..c6a179c52 100644
--- a/portable/GCC/ARM_CM55/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM55/non_secure/portmacro.h
@@ -1,8 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * Copyright 2024 Arm Limited and/or its affiliates
- * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -58,7 +56,6 @@
 #define portARCH_NAME                    "Cortex-M55"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
 #define portARMV8M_MINOR_VERSION         1
-#define portHAS_PACBTI_FEATURE           0
 #define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/port.c b/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
index a33dfa43c..5492c367a 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
@@ -380,7 +380,7 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to check and configure PACBTI security feature implementation.
  */
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
 
@@ -389,7 +389,7 @@ typedef void ( * portISR_t )( void );
     #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
     #define portCONTROL_BTI_EN       ( 1UL << 4UL )
 
-#endif /* portHAS_PACBTI_FEATURE */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
 
 /**
@@ -427,7 +427,7 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
 /**
  * @brief Configures PACBTI features.
@@ -445,7 +445,7 @@ static void prvTaskExitError( void );
  */
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
 
-#endif /* portHAS_PACBTI_FEATURE */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
 /**
  * @brief Setup the timer to generate the tick interrupts.
@@ -1541,13 +1541,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
-        #if ( portHAS_PACBTI_FEATURE == 1 )
+        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
         {
             /* Check PACBTI security feature configuration before pushing the
              * CONTROL register's value on task's TCB. */
             ulControl = prvConfigurePACBTI( pdFALSE );
         }
-        #endif /* portHAS_PACBTI_FEATURE */
+        #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
         if( xRunPrivileged == pdTRUE )
         {
@@ -1786,13 +1786,13 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
-    #if ( portHAS_PACBTI_FEATURE == 1 )
+    #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
     {
         /* Set the CONTROL register value based on PACBTI security feature
          * configuration before starting the first task. */
         ( void) prvConfigurePACBTI( pdTRUE );
     }
-    #endif /* portHAS_PACBTI_FEATURE */
+    #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
     #if ( configENABLE_MPU == 1 )
     {
@@ -2213,7 +2213,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
     {
@@ -2222,12 +2222,8 @@ BaseType_t xPortIsInsideInterrupt( void )
         /* Ensure that PACBTI is implemented. */
         configASSERT( portID_ISAR5_REG != 0x0 );
 
-        /* Enable UsageFault exception if PAC or BTI is enabled. */
-        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
-        {
-            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
-        }
-        #endif
+        /* Enable UsageFault exception. */
+        portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
 
         #if( configENABLE_PAC == 1 )
         {
@@ -2249,5 +2245,5 @@ BaseType_t xPortIsInsideInterrupt( void )
         return ulControl;
     }
 
-#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/portmacro.h b/portable/GCC/ARM_CM55_NTZ/non_secure/portmacro.h
index 369d6825f..c6a179c52 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/portmacro.h
@@ -1,8 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * Copyright 2024 Arm Limited and/or its affiliates
- * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -58,7 +56,6 @@
 #define portARCH_NAME                    "Cortex-M55"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
 #define portARMV8M_MINOR_VERSION         1
-#define portHAS_PACBTI_FEATURE           0
 #define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/GCC/ARM_CM85/non_secure/port.c b/portable/GCC/ARM_CM85/non_secure/port.c
index a33dfa43c..5492c367a 100644
--- a/portable/GCC/ARM_CM85/non_secure/port.c
+++ b/portable/GCC/ARM_CM85/non_secure/port.c
@@ -380,7 +380,7 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to check and configure PACBTI security feature implementation.
  */
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
 
@@ -389,7 +389,7 @@ typedef void ( * portISR_t )( void );
     #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
     #define portCONTROL_BTI_EN       ( 1UL << 4UL )
 
-#endif /* portHAS_PACBTI_FEATURE */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
 
 /**
@@ -427,7 +427,7 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
 /**
  * @brief Configures PACBTI features.
@@ -445,7 +445,7 @@ static void prvTaskExitError( void );
  */
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
 
-#endif /* portHAS_PACBTI_FEATURE */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
 /**
  * @brief Setup the timer to generate the tick interrupts.
@@ -1541,13 +1541,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
-        #if ( portHAS_PACBTI_FEATURE == 1 )
+        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
         {
             /* Check PACBTI security feature configuration before pushing the
              * CONTROL register's value on task's TCB. */
             ulControl = prvConfigurePACBTI( pdFALSE );
         }
-        #endif /* portHAS_PACBTI_FEATURE */
+        #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
         if( xRunPrivileged == pdTRUE )
         {
@@ -1786,13 +1786,13 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
-    #if ( portHAS_PACBTI_FEATURE == 1 )
+    #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
     {
         /* Set the CONTROL register value based on PACBTI security feature
          * configuration before starting the first task. */
         ( void) prvConfigurePACBTI( pdTRUE );
     }
-    #endif /* portHAS_PACBTI_FEATURE */
+    #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
     #if ( configENABLE_MPU == 1 )
     {
@@ -2213,7 +2213,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
     {
@@ -2222,12 +2222,8 @@ BaseType_t xPortIsInsideInterrupt( void )
         /* Ensure that PACBTI is implemented. */
         configASSERT( portID_ISAR5_REG != 0x0 );
 
-        /* Enable UsageFault exception if PAC or BTI is enabled. */
-        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
-        {
-            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
-        }
-        #endif
+        /* Enable UsageFault exception. */
+        portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
 
         #if( configENABLE_PAC == 1 )
         {
@@ -2249,5 +2245,5 @@ BaseType_t xPortIsInsideInterrupt( void )
         return ulControl;
     }
 
-#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM85/non_secure/portmacro.h b/portable/GCC/ARM_CM85/non_secure/portmacro.h
index 5067aa573..7e14f2696 100644
--- a/portable/GCC/ARM_CM85/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM85/non_secure/portmacro.h
@@ -1,8 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * Copyright 2024 Arm Limited and/or its affiliates
- * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -58,7 +56,6 @@
 #define portARCH_NAME                    "Cortex-M85"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
 #define portARMV8M_MINOR_VERSION         1
-#define portHAS_PACBTI_FEATURE           1
 #define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/port.c b/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
index a33dfa43c..5492c367a 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
@@ -380,7 +380,7 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to check and configure PACBTI security feature implementation.
  */
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
 
@@ -389,7 +389,7 @@ typedef void ( * portISR_t )( void );
     #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
     #define portCONTROL_BTI_EN       ( 1UL << 4UL )
 
-#endif /* portHAS_PACBTI_FEATURE */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
 
 /**
@@ -427,7 +427,7 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
 /**
  * @brief Configures PACBTI features.
@@ -445,7 +445,7 @@ static void prvTaskExitError( void );
  */
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
 
-#endif /* portHAS_PACBTI_FEATURE */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
 /**
  * @brief Setup the timer to generate the tick interrupts.
@@ -1541,13 +1541,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
-        #if ( portHAS_PACBTI_FEATURE == 1 )
+        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
         {
             /* Check PACBTI security feature configuration before pushing the
              * CONTROL register's value on task's TCB. */
             ulControl = prvConfigurePACBTI( pdFALSE );
         }
-        #endif /* portHAS_PACBTI_FEATURE */
+        #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
         if( xRunPrivileged == pdTRUE )
         {
@@ -1786,13 +1786,13 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
-    #if ( portHAS_PACBTI_FEATURE == 1 )
+    #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
     {
         /* Set the CONTROL register value based on PACBTI security feature
          * configuration before starting the first task. */
         ( void) prvConfigurePACBTI( pdTRUE );
     }
-    #endif /* portHAS_PACBTI_FEATURE */
+    #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
     #if ( configENABLE_MPU == 1 )
     {
@@ -2213,7 +2213,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
     {
@@ -2222,12 +2222,8 @@ BaseType_t xPortIsInsideInterrupt( void )
         /* Ensure that PACBTI is implemented. */
         configASSERT( portID_ISAR5_REG != 0x0 );
 
-        /* Enable UsageFault exception if PAC or BTI is enabled. */
-        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
-        {
-            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
-        }
-        #endif
+        /* Enable UsageFault exception. */
+        portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
 
         #if( configENABLE_PAC == 1 )
         {
@@ -2249,5 +2245,5 @@ BaseType_t xPortIsInsideInterrupt( void )
         return ulControl;
     }
 
-#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/portmacro.h b/portable/GCC/ARM_CM85_NTZ/non_secure/portmacro.h
index 5067aa573..7e14f2696 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/portmacro.h
@@ -1,8 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * Copyright 2024 Arm Limited and/or its affiliates
- * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -58,7 +56,6 @@
 #define portARCH_NAME                    "Cortex-M85"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
 #define portARMV8M_MINOR_VERSION         1
-#define portHAS_PACBTI_FEATURE           1
 #define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM23/non_secure/port.c b/portable/IAR/ARM_CM23/non_secure/port.c
index a33dfa43c..5492c367a 100644
--- a/portable/IAR/ARM_CM23/non_secure/port.c
+++ b/portable/IAR/ARM_CM23/non_secure/port.c
@@ -380,7 +380,7 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to check and configure PACBTI security feature implementation.
  */
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
 
@@ -389,7 +389,7 @@ typedef void ( * portISR_t )( void );
     #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
     #define portCONTROL_BTI_EN       ( 1UL << 4UL )
 
-#endif /* portHAS_PACBTI_FEATURE */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
 
 /**
@@ -427,7 +427,7 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
 /**
  * @brief Configures PACBTI features.
@@ -445,7 +445,7 @@ static void prvTaskExitError( void );
  */
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
 
-#endif /* portHAS_PACBTI_FEATURE */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
 /**
  * @brief Setup the timer to generate the tick interrupts.
@@ -1541,13 +1541,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
-        #if ( portHAS_PACBTI_FEATURE == 1 )
+        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
         {
             /* Check PACBTI security feature configuration before pushing the
              * CONTROL register's value on task's TCB. */
             ulControl = prvConfigurePACBTI( pdFALSE );
         }
-        #endif /* portHAS_PACBTI_FEATURE */
+        #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
         if( xRunPrivileged == pdTRUE )
         {
@@ -1786,13 +1786,13 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
-    #if ( portHAS_PACBTI_FEATURE == 1 )
+    #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
     {
         /* Set the CONTROL register value based on PACBTI security feature
          * configuration before starting the first task. */
         ( void) prvConfigurePACBTI( pdTRUE );
     }
-    #endif /* portHAS_PACBTI_FEATURE */
+    #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
     #if ( configENABLE_MPU == 1 )
     {
@@ -2213,7 +2213,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
     {
@@ -2222,12 +2222,8 @@ BaseType_t xPortIsInsideInterrupt( void )
         /* Ensure that PACBTI is implemented. */
         configASSERT( portID_ISAR5_REG != 0x0 );
 
-        /* Enable UsageFault exception if PAC or BTI is enabled. */
-        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
-        {
-            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
-        }
-        #endif
+        /* Enable UsageFault exception. */
+        portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
 
         #if( configENABLE_PAC == 1 )
         {
@@ -2249,5 +2245,5 @@ BaseType_t xPortIsInsideInterrupt( void )
         return ulControl;
     }
 
-#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM23/non_secure/portmacro.h b/portable/IAR/ARM_CM23/non_secure/portmacro.h
index 4940e345e..9dfcc9132 100644
--- a/portable/IAR/ARM_CM23/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM23/non_secure/portmacro.h
@@ -1,8 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * Copyright 2024 Arm Limited and/or its affiliates
- * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -53,7 +51,6 @@
 #define portARCH_NAME                    "Cortex-M23"
 #define portHAS_ARMV8M_MAIN_EXTENSION    0
 #define portARMV8M_MINOR_VERSION         0
-#define portHAS_PACBTI_FEATURE           0
 #define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
index a33dfa43c..5492c367a 100644
--- a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
@@ -380,7 +380,7 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to check and configure PACBTI security feature implementation.
  */
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
 
@@ -389,7 +389,7 @@ typedef void ( * portISR_t )( void );
     #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
     #define portCONTROL_BTI_EN       ( 1UL << 4UL )
 
-#endif /* portHAS_PACBTI_FEATURE */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
 
 /**
@@ -427,7 +427,7 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
 /**
  * @brief Configures PACBTI features.
@@ -445,7 +445,7 @@ static void prvTaskExitError( void );
  */
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
 
-#endif /* portHAS_PACBTI_FEATURE */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
 /**
  * @brief Setup the timer to generate the tick interrupts.
@@ -1541,13 +1541,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
-        #if ( portHAS_PACBTI_FEATURE == 1 )
+        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
         {
             /* Check PACBTI security feature configuration before pushing the
              * CONTROL register's value on task's TCB. */
             ulControl = prvConfigurePACBTI( pdFALSE );
         }
-        #endif /* portHAS_PACBTI_FEATURE */
+        #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
         if( xRunPrivileged == pdTRUE )
         {
@@ -1786,13 +1786,13 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
-    #if ( portHAS_PACBTI_FEATURE == 1 )
+    #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
     {
         /* Set the CONTROL register value based on PACBTI security feature
          * configuration before starting the first task. */
         ( void) prvConfigurePACBTI( pdTRUE );
     }
-    #endif /* portHAS_PACBTI_FEATURE */
+    #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
     #if ( configENABLE_MPU == 1 )
     {
@@ -2213,7 +2213,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
     {
@@ -2222,12 +2222,8 @@ BaseType_t xPortIsInsideInterrupt( void )
         /* Ensure that PACBTI is implemented. */
         configASSERT( portID_ISAR5_REG != 0x0 );
 
-        /* Enable UsageFault exception if PAC or BTI is enabled. */
-        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
-        {
-            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
-        }
-        #endif
+        /* Enable UsageFault exception. */
+        portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
 
         #if( configENABLE_PAC == 1 )
         {
@@ -2249,5 +2245,5 @@ BaseType_t xPortIsInsideInterrupt( void )
         return ulControl;
     }
 
-#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h b/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h
index 4940e345e..9dfcc9132 100644
--- a/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h
@@ -1,8 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * Copyright 2024 Arm Limited and/or its affiliates
- * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -53,7 +51,6 @@
 #define portARCH_NAME                    "Cortex-M23"
 #define portHAS_ARMV8M_MAIN_EXTENSION    0
 #define portARMV8M_MINOR_VERSION         0
-#define portHAS_PACBTI_FEATURE           0
 #define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM33/non_secure/port.c b/portable/IAR/ARM_CM33/non_secure/port.c
index a33dfa43c..5492c367a 100644
--- a/portable/IAR/ARM_CM33/non_secure/port.c
+++ b/portable/IAR/ARM_CM33/non_secure/port.c
@@ -380,7 +380,7 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to check and configure PACBTI security feature implementation.
  */
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
 
@@ -389,7 +389,7 @@ typedef void ( * portISR_t )( void );
     #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
     #define portCONTROL_BTI_EN       ( 1UL << 4UL )
 
-#endif /* portHAS_PACBTI_FEATURE */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
 
 /**
@@ -427,7 +427,7 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
 /**
  * @brief Configures PACBTI features.
@@ -445,7 +445,7 @@ static void prvTaskExitError( void );
  */
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
 
-#endif /* portHAS_PACBTI_FEATURE */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
 /**
  * @brief Setup the timer to generate the tick interrupts.
@@ -1541,13 +1541,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
-        #if ( portHAS_PACBTI_FEATURE == 1 )
+        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
         {
             /* Check PACBTI security feature configuration before pushing the
              * CONTROL register's value on task's TCB. */
             ulControl = prvConfigurePACBTI( pdFALSE );
         }
-        #endif /* portHAS_PACBTI_FEATURE */
+        #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
         if( xRunPrivileged == pdTRUE )
         {
@@ -1786,13 +1786,13 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
-    #if ( portHAS_PACBTI_FEATURE == 1 )
+    #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
     {
         /* Set the CONTROL register value based on PACBTI security feature
          * configuration before starting the first task. */
         ( void) prvConfigurePACBTI( pdTRUE );
     }
-    #endif /* portHAS_PACBTI_FEATURE */
+    #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
     #if ( configENABLE_MPU == 1 )
     {
@@ -2213,7 +2213,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
     {
@@ -2222,12 +2222,8 @@ BaseType_t xPortIsInsideInterrupt( void )
         /* Ensure that PACBTI is implemented. */
         configASSERT( portID_ISAR5_REG != 0x0 );
 
-        /* Enable UsageFault exception if PAC or BTI is enabled. */
-        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
-        {
-            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
-        }
-        #endif
+        /* Enable UsageFault exception. */
+        portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
 
         #if( configENABLE_PAC == 1 )
         {
@@ -2249,5 +2245,5 @@ BaseType_t xPortIsInsideInterrupt( void )
         return ulControl;
     }
 
-#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM33/non_secure/portmacro.h b/portable/IAR/ARM_CM33/non_secure/portmacro.h
index 5e126dbf9..0f7d100df 100644
--- a/portable/IAR/ARM_CM33/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM33/non_secure/portmacro.h
@@ -1,8 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * Copyright 2024 Arm Limited and/or its affiliates
- * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -53,7 +51,6 @@
 #define portARCH_NAME                    "Cortex-M33"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
 #define portARMV8M_MINOR_VERSION         0
-#define portHAS_PACBTI_FEATURE           0
 #define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
index a33dfa43c..5492c367a 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
@@ -380,7 +380,7 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to check and configure PACBTI security feature implementation.
  */
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
 
@@ -389,7 +389,7 @@ typedef void ( * portISR_t )( void );
     #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
     #define portCONTROL_BTI_EN       ( 1UL << 4UL )
 
-#endif /* portHAS_PACBTI_FEATURE */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
 
 /**
@@ -427,7 +427,7 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
 /**
  * @brief Configures PACBTI features.
@@ -445,7 +445,7 @@ static void prvTaskExitError( void );
  */
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
 
-#endif /* portHAS_PACBTI_FEATURE */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
 /**
  * @brief Setup the timer to generate the tick interrupts.
@@ -1541,13 +1541,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
-        #if ( portHAS_PACBTI_FEATURE == 1 )
+        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
         {
             /* Check PACBTI security feature configuration before pushing the
              * CONTROL register's value on task's TCB. */
             ulControl = prvConfigurePACBTI( pdFALSE );
         }
-        #endif /* portHAS_PACBTI_FEATURE */
+        #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
         if( xRunPrivileged == pdTRUE )
         {
@@ -1786,13 +1786,13 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
-    #if ( portHAS_PACBTI_FEATURE == 1 )
+    #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
     {
         /* Set the CONTROL register value based on PACBTI security feature
          * configuration before starting the first task. */
         ( void) prvConfigurePACBTI( pdTRUE );
     }
-    #endif /* portHAS_PACBTI_FEATURE */
+    #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
     #if ( configENABLE_MPU == 1 )
     {
@@ -2213,7 +2213,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
     {
@@ -2222,12 +2222,8 @@ BaseType_t xPortIsInsideInterrupt( void )
         /* Ensure that PACBTI is implemented. */
         configASSERT( portID_ISAR5_REG != 0x0 );
 
-        /* Enable UsageFault exception if PAC or BTI is enabled. */
-        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
-        {
-            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
-        }
-        #endif
+        /* Enable UsageFault exception. */
+        portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
 
         #if( configENABLE_PAC == 1 )
         {
@@ -2249,5 +2245,5 @@ BaseType_t xPortIsInsideInterrupt( void )
         return ulControl;
     }
 
-#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h b/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h
index 5e126dbf9..0f7d100df 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h
@@ -1,8 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * Copyright 2024 Arm Limited and/or its affiliates
- * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -53,7 +51,6 @@
 #define portARCH_NAME                    "Cortex-M33"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
 #define portARMV8M_MINOR_VERSION         0
-#define portHAS_PACBTI_FEATURE           0
 #define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM35P/non_secure/port.c b/portable/IAR/ARM_CM35P/non_secure/port.c
index a33dfa43c..5492c367a 100644
--- a/portable/IAR/ARM_CM35P/non_secure/port.c
+++ b/portable/IAR/ARM_CM35P/non_secure/port.c
@@ -380,7 +380,7 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to check and configure PACBTI security feature implementation.
  */
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
 
@@ -389,7 +389,7 @@ typedef void ( * portISR_t )( void );
     #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
     #define portCONTROL_BTI_EN       ( 1UL << 4UL )
 
-#endif /* portHAS_PACBTI_FEATURE */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
 
 /**
@@ -427,7 +427,7 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
 /**
  * @brief Configures PACBTI features.
@@ -445,7 +445,7 @@ static void prvTaskExitError( void );
  */
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
 
-#endif /* portHAS_PACBTI_FEATURE */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
 /**
  * @brief Setup the timer to generate the tick interrupts.
@@ -1541,13 +1541,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
-        #if ( portHAS_PACBTI_FEATURE == 1 )
+        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
         {
             /* Check PACBTI security feature configuration before pushing the
              * CONTROL register's value on task's TCB. */
             ulControl = prvConfigurePACBTI( pdFALSE );
         }
-        #endif /* portHAS_PACBTI_FEATURE */
+        #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
         if( xRunPrivileged == pdTRUE )
         {
@@ -1786,13 +1786,13 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
-    #if ( portHAS_PACBTI_FEATURE == 1 )
+    #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
     {
         /* Set the CONTROL register value based on PACBTI security feature
          * configuration before starting the first task. */
         ( void) prvConfigurePACBTI( pdTRUE );
     }
-    #endif /* portHAS_PACBTI_FEATURE */
+    #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
     #if ( configENABLE_MPU == 1 )
     {
@@ -2213,7 +2213,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
     {
@@ -2222,12 +2222,8 @@ BaseType_t xPortIsInsideInterrupt( void )
         /* Ensure that PACBTI is implemented. */
         configASSERT( portID_ISAR5_REG != 0x0 );
 
-        /* Enable UsageFault exception if PAC or BTI is enabled. */
-        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
-        {
-            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
-        }
-        #endif
+        /* Enable UsageFault exception. */
+        portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
 
         #if( configENABLE_PAC == 1 )
         {
@@ -2249,5 +2245,5 @@ BaseType_t xPortIsInsideInterrupt( void )
         return ulControl;
     }
 
-#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM35P/non_secure/portmacro.h b/portable/IAR/ARM_CM35P/non_secure/portmacro.h
index d617ac0c2..0ad1009b6 100644
--- a/portable/IAR/ARM_CM35P/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM35P/non_secure/portmacro.h
@@ -1,8 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * Copyright 2024 Arm Limited and/or its affiliates
- * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -53,7 +51,6 @@
 #define portARCH_NAME                    "Cortex-M35P"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
 #define portARMV8M_MINOR_VERSION         0
-#define portHAS_PACBTI_FEATURE           0
 #define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c b/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
index a33dfa43c..5492c367a 100644
--- a/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
@@ -380,7 +380,7 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to check and configure PACBTI security feature implementation.
  */
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
 
@@ -389,7 +389,7 @@ typedef void ( * portISR_t )( void );
     #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
     #define portCONTROL_BTI_EN       ( 1UL << 4UL )
 
-#endif /* portHAS_PACBTI_FEATURE */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
 
 /**
@@ -427,7 +427,7 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
 /**
  * @brief Configures PACBTI features.
@@ -445,7 +445,7 @@ static void prvTaskExitError( void );
  */
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
 
-#endif /* portHAS_PACBTI_FEATURE */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
 /**
  * @brief Setup the timer to generate the tick interrupts.
@@ -1541,13 +1541,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
-        #if ( portHAS_PACBTI_FEATURE == 1 )
+        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
         {
             /* Check PACBTI security feature configuration before pushing the
              * CONTROL register's value on task's TCB. */
             ulControl = prvConfigurePACBTI( pdFALSE );
         }
-        #endif /* portHAS_PACBTI_FEATURE */
+        #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
         if( xRunPrivileged == pdTRUE )
         {
@@ -1786,13 +1786,13 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
-    #if ( portHAS_PACBTI_FEATURE == 1 )
+    #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
     {
         /* Set the CONTROL register value based on PACBTI security feature
          * configuration before starting the first task. */
         ( void) prvConfigurePACBTI( pdTRUE );
     }
-    #endif /* portHAS_PACBTI_FEATURE */
+    #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
     #if ( configENABLE_MPU == 1 )
     {
@@ -2213,7 +2213,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
     {
@@ -2222,12 +2222,8 @@ BaseType_t xPortIsInsideInterrupt( void )
         /* Ensure that PACBTI is implemented. */
         configASSERT( portID_ISAR5_REG != 0x0 );
 
-        /* Enable UsageFault exception if PAC or BTI is enabled. */
-        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
-        {
-            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
-        }
-        #endif
+        /* Enable UsageFault exception. */
+        portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
 
         #if( configENABLE_PAC == 1 )
         {
@@ -2249,5 +2245,5 @@ BaseType_t xPortIsInsideInterrupt( void )
         return ulControl;
     }
 
-#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacro.h b/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacro.h
index d617ac0c2..0ad1009b6 100644
--- a/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacro.h
@@ -1,8 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * Copyright 2024 Arm Limited and/or its affiliates
- * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -53,7 +51,6 @@
 #define portARCH_NAME                    "Cortex-M35P"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
 #define portARMV8M_MINOR_VERSION         0
-#define portHAS_PACBTI_FEATURE           0
 #define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM55/non_secure/port.c b/portable/IAR/ARM_CM55/non_secure/port.c
index a33dfa43c..5492c367a 100644
--- a/portable/IAR/ARM_CM55/non_secure/port.c
+++ b/portable/IAR/ARM_CM55/non_secure/port.c
@@ -380,7 +380,7 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to check and configure PACBTI security feature implementation.
  */
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
 
@@ -389,7 +389,7 @@ typedef void ( * portISR_t )( void );
     #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
     #define portCONTROL_BTI_EN       ( 1UL << 4UL )
 
-#endif /* portHAS_PACBTI_FEATURE */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
 
 /**
@@ -427,7 +427,7 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
 /**
  * @brief Configures PACBTI features.
@@ -445,7 +445,7 @@ static void prvTaskExitError( void );
  */
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
 
-#endif /* portHAS_PACBTI_FEATURE */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
 /**
  * @brief Setup the timer to generate the tick interrupts.
@@ -1541,13 +1541,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
-        #if ( portHAS_PACBTI_FEATURE == 1 )
+        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
         {
             /* Check PACBTI security feature configuration before pushing the
              * CONTROL register's value on task's TCB. */
             ulControl = prvConfigurePACBTI( pdFALSE );
         }
-        #endif /* portHAS_PACBTI_FEATURE */
+        #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
         if( xRunPrivileged == pdTRUE )
         {
@@ -1786,13 +1786,13 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
-    #if ( portHAS_PACBTI_FEATURE == 1 )
+    #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
     {
         /* Set the CONTROL register value based on PACBTI security feature
          * configuration before starting the first task. */
         ( void) prvConfigurePACBTI( pdTRUE );
     }
-    #endif /* portHAS_PACBTI_FEATURE */
+    #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
     #if ( configENABLE_MPU == 1 )
     {
@@ -2213,7 +2213,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
     {
@@ -2222,12 +2222,8 @@ BaseType_t xPortIsInsideInterrupt( void )
         /* Ensure that PACBTI is implemented. */
         configASSERT( portID_ISAR5_REG != 0x0 );
 
-        /* Enable UsageFault exception if PAC or BTI is enabled. */
-        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
-        {
-            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
-        }
-        #endif
+        /* Enable UsageFault exception. */
+        portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
 
         #if( configENABLE_PAC == 1 )
         {
@@ -2249,5 +2245,5 @@ BaseType_t xPortIsInsideInterrupt( void )
         return ulControl;
     }
 
-#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM55/non_secure/portmacro.h b/portable/IAR/ARM_CM55/non_secure/portmacro.h
index 6a5272267..597af66fa 100644
--- a/portable/IAR/ARM_CM55/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM55/non_secure/portmacro.h
@@ -1,8 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * Copyright 2024 Arm Limited and/or its affiliates
- * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -58,7 +56,6 @@
 #define portARCH_NAME                    "Cortex-M55"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
 #define portARMV8M_MINOR_VERSION         1
-#define portHAS_PACBTI_FEATURE           0
 #define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/port.c b/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
index a33dfa43c..5492c367a 100644
--- a/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
@@ -380,7 +380,7 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to check and configure PACBTI security feature implementation.
  */
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
 
@@ -389,7 +389,7 @@ typedef void ( * portISR_t )( void );
     #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
     #define portCONTROL_BTI_EN       ( 1UL << 4UL )
 
-#endif /* portHAS_PACBTI_FEATURE */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
 
 /**
@@ -427,7 +427,7 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
 /**
  * @brief Configures PACBTI features.
@@ -445,7 +445,7 @@ static void prvTaskExitError( void );
  */
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
 
-#endif /* portHAS_PACBTI_FEATURE */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
 /**
  * @brief Setup the timer to generate the tick interrupts.
@@ -1541,13 +1541,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
-        #if ( portHAS_PACBTI_FEATURE == 1 )
+        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
         {
             /* Check PACBTI security feature configuration before pushing the
              * CONTROL register's value on task's TCB. */
             ulControl = prvConfigurePACBTI( pdFALSE );
         }
-        #endif /* portHAS_PACBTI_FEATURE */
+        #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
         if( xRunPrivileged == pdTRUE )
         {
@@ -1786,13 +1786,13 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
-    #if ( portHAS_PACBTI_FEATURE == 1 )
+    #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
     {
         /* Set the CONTROL register value based on PACBTI security feature
          * configuration before starting the first task. */
         ( void) prvConfigurePACBTI( pdTRUE );
     }
-    #endif /* portHAS_PACBTI_FEATURE */
+    #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
     #if ( configENABLE_MPU == 1 )
     {
@@ -2213,7 +2213,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
     {
@@ -2222,12 +2222,8 @@ BaseType_t xPortIsInsideInterrupt( void )
         /* Ensure that PACBTI is implemented. */
         configASSERT( portID_ISAR5_REG != 0x0 );
 
-        /* Enable UsageFault exception if PAC or BTI is enabled. */
-        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
-        {
-            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
-        }
-        #endif
+        /* Enable UsageFault exception. */
+        portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
 
         #if( configENABLE_PAC == 1 )
         {
@@ -2249,5 +2245,5 @@ BaseType_t xPortIsInsideInterrupt( void )
         return ulControl;
     }
 
-#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/portmacro.h b/portable/IAR/ARM_CM55_NTZ/non_secure/portmacro.h
index 6a5272267..597af66fa 100644
--- a/portable/IAR/ARM_CM55_NTZ/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM55_NTZ/non_secure/portmacro.h
@@ -1,8 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * Copyright 2024 Arm Limited and/or its affiliates
- * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -58,7 +56,6 @@
 #define portARCH_NAME                    "Cortex-M55"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
 #define portARMV8M_MINOR_VERSION         1
-#define portHAS_PACBTI_FEATURE           0
 #define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM85/non_secure/port.c b/portable/IAR/ARM_CM85/non_secure/port.c
index a33dfa43c..5492c367a 100644
--- a/portable/IAR/ARM_CM85/non_secure/port.c
+++ b/portable/IAR/ARM_CM85/non_secure/port.c
@@ -380,7 +380,7 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to check and configure PACBTI security feature implementation.
  */
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
 
@@ -389,7 +389,7 @@ typedef void ( * portISR_t )( void );
     #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
     #define portCONTROL_BTI_EN       ( 1UL << 4UL )
 
-#endif /* portHAS_PACBTI_FEATURE */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
 
 /**
@@ -427,7 +427,7 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
 /**
  * @brief Configures PACBTI features.
@@ -445,7 +445,7 @@ static void prvTaskExitError( void );
  */
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
 
-#endif /* portHAS_PACBTI_FEATURE */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
 /**
  * @brief Setup the timer to generate the tick interrupts.
@@ -1541,13 +1541,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
-        #if ( portHAS_PACBTI_FEATURE == 1 )
+        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
         {
             /* Check PACBTI security feature configuration before pushing the
              * CONTROL register's value on task's TCB. */
             ulControl = prvConfigurePACBTI( pdFALSE );
         }
-        #endif /* portHAS_PACBTI_FEATURE */
+        #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
         if( xRunPrivileged == pdTRUE )
         {
@@ -1786,13 +1786,13 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
-    #if ( portHAS_PACBTI_FEATURE == 1 )
+    #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
     {
         /* Set the CONTROL register value based on PACBTI security feature
          * configuration before starting the first task. */
         ( void) prvConfigurePACBTI( pdTRUE );
     }
-    #endif /* portHAS_PACBTI_FEATURE */
+    #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
     #if ( configENABLE_MPU == 1 )
     {
@@ -2213,7 +2213,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
     {
@@ -2222,12 +2222,8 @@ BaseType_t xPortIsInsideInterrupt( void )
         /* Ensure that PACBTI is implemented. */
         configASSERT( portID_ISAR5_REG != 0x0 );
 
-        /* Enable UsageFault exception if PAC or BTI is enabled. */
-        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
-        {
-            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
-        }
-        #endif
+        /* Enable UsageFault exception. */
+        portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
 
         #if( configENABLE_PAC == 1 )
         {
@@ -2249,5 +2245,5 @@ BaseType_t xPortIsInsideInterrupt( void )
         return ulControl;
     }
 
-#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM85/non_secure/portmacro.h b/portable/IAR/ARM_CM85/non_secure/portmacro.h
index c88adc77c..ff5c9895d 100644
--- a/portable/IAR/ARM_CM85/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM85/non_secure/portmacro.h
@@ -1,8 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * Copyright 2024 Arm Limited and/or its affiliates
- * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -58,7 +56,6 @@
 #define portARCH_NAME                    "Cortex-M85"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
 #define portARMV8M_MINOR_VERSION         1
-#define portHAS_PACBTI_FEATURE           1
 #define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/port.c b/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
index a33dfa43c..5492c367a 100644
--- a/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
@@ -380,7 +380,7 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to check and configure PACBTI security feature implementation.
  */
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
 
@@ -389,7 +389,7 @@ typedef void ( * portISR_t )( void );
     #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
     #define portCONTROL_BTI_EN       ( 1UL << 4UL )
 
-#endif /* portHAS_PACBTI_FEATURE */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
 
 /**
@@ -427,7 +427,7 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
 /**
  * @brief Configures PACBTI features.
@@ -445,7 +445,7 @@ static void prvTaskExitError( void );
  */
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
 
-#endif /* portHAS_PACBTI_FEATURE */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
 /**
  * @brief Setup the timer to generate the tick interrupts.
@@ -1541,13 +1541,13 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
-        #if ( portHAS_PACBTI_FEATURE == 1 )
+        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
         {
             /* Check PACBTI security feature configuration before pushing the
              * CONTROL register's value on task's TCB. */
             ulControl = prvConfigurePACBTI( pdFALSE );
         }
-        #endif /* portHAS_PACBTI_FEATURE */
+        #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
         if( xRunPrivileged == pdTRUE )
         {
@@ -1786,13 +1786,13 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
-    #if ( portHAS_PACBTI_FEATURE == 1 )
+    #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
     {
         /* Set the CONTROL register value based on PACBTI security feature
          * configuration before starting the first task. */
         ( void) prvConfigurePACBTI( pdTRUE );
     }
-    #endif /* portHAS_PACBTI_FEATURE */
+    #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
     #if ( configENABLE_MPU == 1 )
     {
@@ -2213,7 +2213,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
 
-#if ( portHAS_PACBTI_FEATURE == 1 )
+#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
     {
@@ -2222,12 +2222,8 @@ BaseType_t xPortIsInsideInterrupt( void )
         /* Ensure that PACBTI is implemented. */
         configASSERT( portID_ISAR5_REG != 0x0 );
 
-        /* Enable UsageFault exception if PAC or BTI is enabled. */
-        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
-        {
-            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
-        }
-        #endif
+        /* Enable UsageFault exception. */
+        portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
 
         #if( configENABLE_PAC == 1 )
         {
@@ -2249,5 +2245,5 @@ BaseType_t xPortIsInsideInterrupt( void )
         return ulControl;
     }
 
-#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/portmacro.h b/portable/IAR/ARM_CM85_NTZ/non_secure/portmacro.h
index c88adc77c..ff5c9895d 100644
--- a/portable/IAR/ARM_CM85_NTZ/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM85_NTZ/non_secure/portmacro.h
@@ -1,8 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * Copyright 2024 Arm Limited and/or its affiliates
- * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -58,7 +56,6 @@
 #define portARCH_NAME                    "Cortex-M85"
 #define portHAS_ARMV8M_MAIN_EXTENSION    1
 #define portARMV8M_MINOR_VERSION         1
-#define portHAS_PACBTI_FEATURE           1
 #define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 

From 7e419c2dd5d25bded70fb564f1226ae8056215f9 Mon Sep 17 00:00:00 2001
From: Tony Josi <tonyjosi@amazon.com>
Date: Thu, 14 Nov 2024 11:09:55 +0530
Subject: [PATCH 353/424] Update partner supported and community supported
 ports submodulees (#1194)

---
 portable/ThirdParty/Community-Supported-Ports | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/portable/ThirdParty/Community-Supported-Ports b/portable/ThirdParty/Community-Supported-Ports
index 9c5bad7b2..8b2955f6d 160000
--- a/portable/ThirdParty/Community-Supported-Ports
+++ b/portable/ThirdParty/Community-Supported-Ports
@@ -1 +1 @@
-Subproject commit 9c5bad7b2f42b4e8420f12290b9bc085d3309e8b
+Subproject commit 8b2955f6d97bf4cd582db9f5b62d9eb1587b76d7

From 874fa7bed4b30ed4f1887ba3eae767c734515aa4 Mon Sep 17 00:00:00 2001
From: Ryan <63398895+rwardd@users.noreply.github.com>
Date: Wed, 20 Nov 2024 01:38:15 -0500
Subject: [PATCH 354/424] Removing the old -RV32 directory name from parts of
 the documentation (#1196)

---
 .../freertos_risc_v_chip_specific_extensions.h                | 4 ++--
 .../freertos_risc_v_chip_specific_extensions.h                | 4 ++--
 portable/GCC/RISC-V/chip_specific_extensions/readme.txt       | 4 ++--
 portable/GCC/RISC-V/portASM.S                                 | 2 +-
 portable/GCC/RISC-V/readme.txt                                | 4 ++--
 5 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h b/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h
index bbc231cf1..4d8a5fb53 100644
--- a/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h
+++ b/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h
@@ -31,7 +31,7 @@
  * common across all currently supported RISC-V chips (implementations of the
  * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
  *
- * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
+ * + FreeRTOS\Source\portable\GCC\RISC-V\portASM.S contains the code that
  *   is common to all currently supported RISC-V chips.  There is only one
  *   portASM.S file because the same file is built for all RISC-V target chips.
  *
@@ -46,7 +46,7 @@
  * compiler's!) include path.  For example, if the chip in use includes a core
  * local interrupter (CLINT) and does not include any chip specific register
  * extensions then add the path below to the assembler's include path:
- * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions
+ * FreeRTOS\Source\portable\GCC\RISC-V\chip_specific_extensions\RV32I_CLINT_no_extensions
  *
  */
 
diff --git a/portable/GCC/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h b/portable/GCC/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h
index d3e9ea992..5b9ef4c06 100644
--- a/portable/GCC/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h
+++ b/portable/GCC/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h
@@ -31,7 +31,7 @@
  * common across all currently supported RISC-V chips (implementations of the
  * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
  *
- * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
+ * + FreeRTOS\Source\portable\GCC\RISC-V\portASM.S contains the code that
  *   is common to all currently supported RISC-V chips.  There is only one
  *   portASM.S file because the same file is built for all RISC-V target chips.
  *
@@ -46,7 +46,7 @@
  * compiler's!) include path.  For example, if the chip in use includes a core
  * local interrupter (CLINT) and does not include any chip specific register
  * extensions then add the path below to the assembler's include path:
- * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions
+ * FreeRTOS\Source\portable\GCC\RISC-V\chip_specific_extensions\RV32I_CLINT_no_extensions
  *
  */
 
diff --git a/portable/GCC/RISC-V/chip_specific_extensions/readme.txt b/portable/GCC/RISC-V/chip_specific_extensions/readme.txt
index b24c0b9fb..3e83157d7 100644
--- a/portable/GCC/RISC-V/chip_specific_extensions/readme.txt
+++ b/portable/GCC/RISC-V/chip_specific_extensions/readme.txt
@@ -3,7 +3,7 @@
  * common across all currently supported RISC-V chips (implementations of the
  * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
  *
- * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
+ * + FreeRTOS\Source\portable\GCC\RISC-V\portASM.S contains the code that
  *   is common to all currently supported RISC-V chips.  There is only one
  *   portASM.S file because the same file is built for all RISC-V target chips.
  *
@@ -18,6 +18,6 @@
  * compiler's!) include path.  For example, if the chip in use includes a core
  * local interrupter (CLINT) and does not include any chip specific register
  * extensions then add the path below to the assembler's include path:
- * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions
+ * FreeRTOS\Source\portable\GCC\RISC-V\chip_specific_extensions\RV32I_CLINT_no_extensions
  *
  */
diff --git a/portable/GCC/RISC-V/portASM.S b/portable/GCC/RISC-V/portASM.S
index b5f054777..99613ada6 100644
--- a/portable/GCC/RISC-V/portASM.S
+++ b/portable/GCC/RISC-V/portASM.S
@@ -32,7 +32,7 @@
  * RISC-V ISA), and code which tailors the port to a specific RISC-V chip:
  *
  * + The code that is common to all RISC-V chips is implemented in
- *   FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S.  There is only one
+ *   FreeRTOS\Source\portable\GCC\RISC-V\portASM.S.  There is only one
  *   portASM.S file because the same file is used no matter which RISC-V chip is
  *   in use.
  *
diff --git a/portable/GCC/RISC-V/readme.txt b/portable/GCC/RISC-V/readme.txt
index b24c0b9fb..3e83157d7 100644
--- a/portable/GCC/RISC-V/readme.txt
+++ b/portable/GCC/RISC-V/readme.txt
@@ -3,7 +3,7 @@
  * common across all currently supported RISC-V chips (implementations of the
  * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
  *
- * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
+ * + FreeRTOS\Source\portable\GCC\RISC-V\portASM.S contains the code that
  *   is common to all currently supported RISC-V chips.  There is only one
  *   portASM.S file because the same file is built for all RISC-V target chips.
  *
@@ -18,6 +18,6 @@
  * compiler's!) include path.  For example, if the chip in use includes a core
  * local interrupter (CLINT) and does not include any chip specific register
  * extensions then add the path below to the assembler's include path:
- * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions
+ * FreeRTOS\Source\portable\GCC\RISC-V\chip_specific_extensions\RV32I_CLINT_no_extensions
  *
  */

From 682f0515c984da0ef283b12e99791e5ab7b41034 Mon Sep 17 00:00:00 2001
From: yh-sb <yh.sb@outlook.com>
Date: Mon, 25 Nov 2024 07:24:41 +0200
Subject: [PATCH 355/424] Fix CMake build for RP2040 (#1197)

Add public dependency to hardware_sync because portable\ThirdParty\GCC\RP2040\include\portmacro.h exposes include "hardware/sync.h" to FreeRTOS.h which is PUBLIC.

Add private dependency to pico_multicore because of usage prvFIFOInterruptHandler() and sio_hw in portable/ThirdParty/GCC/RP2040/port.c.
---
 portable/CMakeLists.txt | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/portable/CMakeLists.txt b/portable/CMakeLists.txt
index f761ebc47..5e43877bb 100644
--- a/portable/CMakeLists.txt
+++ b/portable/CMakeLists.txt
@@ -1215,6 +1215,11 @@ target_include_directories(freertos_kernel_port_headers INTERFACE
     $<$<STREQUAL:${FREERTOS_PORT},WIZC_PIC18>:${CMAKE_CURRENT_LIST_DIR}/WizC/PIC18>
 )
 
+target_link_libraries(freertos_kernel_port_headers
+    INTERFACE
+        $<$<STREQUAL:${FREERTOS_PORT},GCC_RP2040>:hardware_sync>
+)
+
 if(FREERTOS_PORT STREQUAL GCC_POSIX)
     find_package(Threads REQUIRED)
 endif()
@@ -1227,6 +1232,6 @@ target_link_libraries(freertos_kernel_port
     PRIVATE
         freertos_kernel_include
         $<$<STREQUAL:${FREERTOS_PORT},GCC_POSIX>:Threads::Threads>
-        "$<$<STREQUAL:${FREERTOS_PORT},GCC_RP2040>:hardware_clocks;hardware_exception>"
+        "$<$<STREQUAL:${FREERTOS_PORT},GCC_RP2040>:hardware_clocks;hardware_exception;pico_multicore>"
         $<$<STREQUAL:${FREERTOS_PORT},MSVC_MINGW>:winmm> # Windows library which implements timers
 )

From 974351fe4aec19779f5be774007810c6ab36a8ab Mon Sep 17 00:00:00 2001
From: Kody Stribrny <89810515+kstribrnAmzn@users.noreply.github.com>
Date: Mon, 2 Dec 2024 11:29:36 -0800
Subject: [PATCH 356/424] Update manifest to use 'V' (#1201)

Release tags use a capitalized V.
Our manifest tag is used by our SBOM
script to generate the URL and so
this needs to be capitalized to generate
a valid URL.
---
 .github/scripts/manifest_updater.py | 2 +-
 manifest.yml                        | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/.github/scripts/manifest_updater.py b/.github/scripts/manifest_updater.py
index 684c7cb5a..fc2343da3 100755
--- a/.github/scripts/manifest_updater.py
+++ b/.github/scripts/manifest_updater.py
@@ -11,7 +11,7 @@ def update_manifest_file(new_version_number):
         for line in f:
             line = line.strip()
             if line.startswith('version'):
-                updated_lines.append(f'version: "v{new_version_number}"\n')
+                updated_lines.append(f'version: "V{new_version_number}"\n')
             else:
                 updated_lines.append(f'{line}\n')
 
diff --git a/manifest.yml b/manifest.yml
index ac13cb60a..bd893f162 100644
--- a/manifest.yml
+++ b/manifest.yml
@@ -1,4 +1,4 @@
 name : "FreeRTOS-Kernel"
-version: "v11.0.1+"
+version: "V11.0.1+"
 description: "FreeRTOS Kernel."
 license: "MIT"

From b58005a4da1bb5380fda8796b862451d42358839 Mon Sep 17 00:00:00 2001
From: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Date: Mon, 16 Dec 2024 18:26:43 +0530
Subject: [PATCH 357/424] Add macro guard configUSE_MPU_WRAPPERS_V1 to remove
 definition missing warning. (#1208)

Add macro guard to removed definition missing warning
---
 .github/allowed_urls.txt                     | 3 +++
 .github/workflows/ci.yml                     | 2 ++
 portable/ARMv8M/non_secure/port.c            | 8 ++++----
 portable/GCC/ARM_CM23/non_secure/port.c      | 8 ++++----
 portable/GCC/ARM_CM23_NTZ/non_secure/port.c  | 8 ++++----
 portable/GCC/ARM_CM33/non_secure/port.c      | 8 ++++----
 portable/GCC/ARM_CM33_NTZ/non_secure/port.c  | 8 ++++----
 portable/GCC/ARM_CM35P/non_secure/port.c     | 8 ++++----
 portable/GCC/ARM_CM35P_NTZ/non_secure/port.c | 8 ++++----
 portable/GCC/ARM_CM55/non_secure/port.c      | 8 ++++----
 portable/GCC/ARM_CM55_NTZ/non_secure/port.c  | 8 ++++----
 portable/GCC/ARM_CM85/non_secure/port.c      | 8 ++++----
 portable/GCC/ARM_CM85_NTZ/non_secure/port.c  | 8 ++++----
 portable/IAR/ARM_CM23/non_secure/port.c      | 8 ++++----
 portable/IAR/ARM_CM23_NTZ/non_secure/port.c  | 8 ++++----
 portable/IAR/ARM_CM33/non_secure/port.c      | 8 ++++----
 portable/IAR/ARM_CM33_NTZ/non_secure/port.c  | 8 ++++----
 portable/IAR/ARM_CM35P/non_secure/port.c     | 8 ++++----
 portable/IAR/ARM_CM35P_NTZ/non_secure/port.c | 8 ++++----
 portable/IAR/ARM_CM55/non_secure/port.c      | 8 ++++----
 portable/IAR/ARM_CM55_NTZ/non_secure/port.c  | 8 ++++----
 portable/IAR/ARM_CM85/non_secure/port.c      | 8 ++++----
 portable/IAR/ARM_CM85_NTZ/non_secure/port.c  | 8 ++++----
 23 files changed, 89 insertions(+), 84 deletions(-)
 create mode 100644 .github/allowed_urls.txt

diff --git a/.github/allowed_urls.txt b/.github/allowed_urls.txt
new file mode 100644
index 000000000..578b90e3d
--- /dev/null
+++ b/.github/allowed_urls.txt
@@ -0,0 +1,3 @@
+https://www.renesas.com/us/en/document/mah/rh850f1k-group-users-manual-hardware?r=1170166
+https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rh850-automotive-mcus
+https://www.renesas.com/us/en/software-tool/c-compiler-package-rh850-family#downloads
diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
index 1ba874850..edda39154 100644
--- a/.github/workflows/ci.yml
+++ b/.github/workflows/ci.yml
@@ -33,6 +33,8 @@ jobs:
         uses: actions/checkout@v4.1.1
       - name: Link Verification
         uses: FreeRTOS/CI-CD-Github-Actions/link-verifier@main
+        with:
+          allowlist-file: '.github/allowed_urls.txt'
 
   verify-manifest:
     runs-on: ubuntu-latest
diff --git a/portable/ARMv8M/non_secure/port.c b/portable/ARMv8M/non_secure/port.c
index 5492c367a..f3f5d3edd 100644
--- a/portable/ARMv8M/non_secure/port.c
+++ b/portable/ARMv8M/non_secure/port.c
@@ -398,7 +398,7 @@ typedef void ( * portISR_t )( void );
  */
 static void prvTaskExitError( void );
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
  * @brief Extract MPU region's access permissions from the Region Base Address
@@ -409,7 +409,7 @@ static void prvTaskExitError( void );
  * @return uint32_t Access permissions.
  */
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 
 #if ( configENABLE_MPU == 1 )
 
@@ -871,7 +871,7 @@ static void prvTaskExitError( void )
 }
 /*-----------------------------------------------------------*/
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
     {
@@ -890,7 +890,7 @@ static void prvTaskExitError( void )
         return ulAccessPermissions;
     }
 
-#endif /* configENABLE_MPU */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
diff --git a/portable/GCC/ARM_CM23/non_secure/port.c b/portable/GCC/ARM_CM23/non_secure/port.c
index 5492c367a..f3f5d3edd 100644
--- a/portable/GCC/ARM_CM23/non_secure/port.c
+++ b/portable/GCC/ARM_CM23/non_secure/port.c
@@ -398,7 +398,7 @@ typedef void ( * portISR_t )( void );
  */
 static void prvTaskExitError( void );
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
  * @brief Extract MPU region's access permissions from the Region Base Address
@@ -409,7 +409,7 @@ static void prvTaskExitError( void );
  * @return uint32_t Access permissions.
  */
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 
 #if ( configENABLE_MPU == 1 )
 
@@ -871,7 +871,7 @@ static void prvTaskExitError( void )
 }
 /*-----------------------------------------------------------*/
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
     {
@@ -890,7 +890,7 @@ static void prvTaskExitError( void )
         return ulAccessPermissions;
     }
 
-#endif /* configENABLE_MPU */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
index 5492c367a..f3f5d3edd 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
@@ -398,7 +398,7 @@ typedef void ( * portISR_t )( void );
  */
 static void prvTaskExitError( void );
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
  * @brief Extract MPU region's access permissions from the Region Base Address
@@ -409,7 +409,7 @@ static void prvTaskExitError( void );
  * @return uint32_t Access permissions.
  */
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 
 #if ( configENABLE_MPU == 1 )
 
@@ -871,7 +871,7 @@ static void prvTaskExitError( void )
 }
 /*-----------------------------------------------------------*/
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
     {
@@ -890,7 +890,7 @@ static void prvTaskExitError( void )
         return ulAccessPermissions;
     }
 
-#endif /* configENABLE_MPU */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
diff --git a/portable/GCC/ARM_CM33/non_secure/port.c b/portable/GCC/ARM_CM33/non_secure/port.c
index 5492c367a..aa9c23816 100644
--- a/portable/GCC/ARM_CM33/non_secure/port.c
+++ b/portable/GCC/ARM_CM33/non_secure/port.c
@@ -398,7 +398,7 @@ typedef void ( * portISR_t )( void );
  */
 static void prvTaskExitError( void );
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
  * @brief Extract MPU region's access permissions from the Region Base Address
@@ -409,7 +409,7 @@ static void prvTaskExitError( void );
  * @return uint32_t Access permissions.
  */
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0  */
 
 #if ( configENABLE_MPU == 1 )
 
@@ -871,7 +871,7 @@ static void prvTaskExitError( void )
 }
 /*-----------------------------------------------------------*/
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
     {
@@ -890,7 +890,7 @@ static void prvTaskExitError( void )
         return ulAccessPermissions;
     }
 
-#endif /* configENABLE_MPU */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0  */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
index 5492c367a..aa9c23816 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
@@ -398,7 +398,7 @@ typedef void ( * portISR_t )( void );
  */
 static void prvTaskExitError( void );
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
  * @brief Extract MPU region's access permissions from the Region Base Address
@@ -409,7 +409,7 @@ static void prvTaskExitError( void );
  * @return uint32_t Access permissions.
  */
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0  */
 
 #if ( configENABLE_MPU == 1 )
 
@@ -871,7 +871,7 @@ static void prvTaskExitError( void )
 }
 /*-----------------------------------------------------------*/
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
     {
@@ -890,7 +890,7 @@ static void prvTaskExitError( void )
         return ulAccessPermissions;
     }
 
-#endif /* configENABLE_MPU */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0  */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
diff --git a/portable/GCC/ARM_CM35P/non_secure/port.c b/portable/GCC/ARM_CM35P/non_secure/port.c
index 5492c367a..aa9c23816 100644
--- a/portable/GCC/ARM_CM35P/non_secure/port.c
+++ b/portable/GCC/ARM_CM35P/non_secure/port.c
@@ -398,7 +398,7 @@ typedef void ( * portISR_t )( void );
  */
 static void prvTaskExitError( void );
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
  * @brief Extract MPU region's access permissions from the Region Base Address
@@ -409,7 +409,7 @@ static void prvTaskExitError( void );
  * @return uint32_t Access permissions.
  */
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0  */
 
 #if ( configENABLE_MPU == 1 )
 
@@ -871,7 +871,7 @@ static void prvTaskExitError( void )
 }
 /*-----------------------------------------------------------*/
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
     {
@@ -890,7 +890,7 @@ static void prvTaskExitError( void )
         return ulAccessPermissions;
     }
 
-#endif /* configENABLE_MPU */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0  */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c b/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
index 5492c367a..aa9c23816 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
@@ -398,7 +398,7 @@ typedef void ( * portISR_t )( void );
  */
 static void prvTaskExitError( void );
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
  * @brief Extract MPU region's access permissions from the Region Base Address
@@ -409,7 +409,7 @@ static void prvTaskExitError( void );
  * @return uint32_t Access permissions.
  */
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0  */
 
 #if ( configENABLE_MPU == 1 )
 
@@ -871,7 +871,7 @@ static void prvTaskExitError( void )
 }
 /*-----------------------------------------------------------*/
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
     {
@@ -890,7 +890,7 @@ static void prvTaskExitError( void )
         return ulAccessPermissions;
     }
 
-#endif /* configENABLE_MPU */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0  */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
diff --git a/portable/GCC/ARM_CM55/non_secure/port.c b/portable/GCC/ARM_CM55/non_secure/port.c
index 5492c367a..aa9c23816 100644
--- a/portable/GCC/ARM_CM55/non_secure/port.c
+++ b/portable/GCC/ARM_CM55/non_secure/port.c
@@ -398,7 +398,7 @@ typedef void ( * portISR_t )( void );
  */
 static void prvTaskExitError( void );
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
  * @brief Extract MPU region's access permissions from the Region Base Address
@@ -409,7 +409,7 @@ static void prvTaskExitError( void );
  * @return uint32_t Access permissions.
  */
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0  */
 
 #if ( configENABLE_MPU == 1 )
 
@@ -871,7 +871,7 @@ static void prvTaskExitError( void )
 }
 /*-----------------------------------------------------------*/
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
     {
@@ -890,7 +890,7 @@ static void prvTaskExitError( void )
         return ulAccessPermissions;
     }
 
-#endif /* configENABLE_MPU */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0  */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/port.c b/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
index 5492c367a..aa9c23816 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
@@ -398,7 +398,7 @@ typedef void ( * portISR_t )( void );
  */
 static void prvTaskExitError( void );
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
  * @brief Extract MPU region's access permissions from the Region Base Address
@@ -409,7 +409,7 @@ static void prvTaskExitError( void );
  * @return uint32_t Access permissions.
  */
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0  */
 
 #if ( configENABLE_MPU == 1 )
 
@@ -871,7 +871,7 @@ static void prvTaskExitError( void )
 }
 /*-----------------------------------------------------------*/
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
     {
@@ -890,7 +890,7 @@ static void prvTaskExitError( void )
         return ulAccessPermissions;
     }
 
-#endif /* configENABLE_MPU */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0  */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
diff --git a/portable/GCC/ARM_CM85/non_secure/port.c b/portable/GCC/ARM_CM85/non_secure/port.c
index 5492c367a..aa9c23816 100644
--- a/portable/GCC/ARM_CM85/non_secure/port.c
+++ b/portable/GCC/ARM_CM85/non_secure/port.c
@@ -398,7 +398,7 @@ typedef void ( * portISR_t )( void );
  */
 static void prvTaskExitError( void );
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
  * @brief Extract MPU region's access permissions from the Region Base Address
@@ -409,7 +409,7 @@ static void prvTaskExitError( void );
  * @return uint32_t Access permissions.
  */
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0  */
 
 #if ( configENABLE_MPU == 1 )
 
@@ -871,7 +871,7 @@ static void prvTaskExitError( void )
 }
 /*-----------------------------------------------------------*/
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
     {
@@ -890,7 +890,7 @@ static void prvTaskExitError( void )
         return ulAccessPermissions;
     }
 
-#endif /* configENABLE_MPU */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0  */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/port.c b/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
index 5492c367a..80225b5cb 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
@@ -398,7 +398,7 @@ typedef void ( * portISR_t )( void );
  */
 static void prvTaskExitError( void );
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
  * @brief Extract MPU region's access permissions from the Region Base Address
@@ -409,7 +409,7 @@ static void prvTaskExitError( void );
  * @return uint32_t Access permissions.
  */
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0  */
 
 #if ( configENABLE_MPU == 1 )
 
@@ -871,7 +871,7 @@ static void prvTaskExitError( void )
 }
 /*-----------------------------------------------------------*/
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
     {
@@ -890,7 +890,7 @@ static void prvTaskExitError( void )
         return ulAccessPermissions;
     }
 
-#endif /* configENABLE_MPU */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0   */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
diff --git a/portable/IAR/ARM_CM23/non_secure/port.c b/portable/IAR/ARM_CM23/non_secure/port.c
index 5492c367a..5c963ea29 100644
--- a/portable/IAR/ARM_CM23/non_secure/port.c
+++ b/portable/IAR/ARM_CM23/non_secure/port.c
@@ -398,7 +398,7 @@ typedef void ( * portISR_t )( void );
  */
 static void prvTaskExitError( void );
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
  * @brief Extract MPU region's access permissions from the Region Base Address
@@ -409,7 +409,7 @@ static void prvTaskExitError( void );
  * @return uint32_t Access permissions.
  */
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0   */
 
 #if ( configENABLE_MPU == 1 )
 
@@ -871,7 +871,7 @@ static void prvTaskExitError( void )
 }
 /*-----------------------------------------------------------*/
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
     {
@@ -890,7 +890,7 @@ static void prvTaskExitError( void )
         return ulAccessPermissions;
     }
 
-#endif /* configENABLE_MPU */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0   */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
index 5492c367a..5c963ea29 100644
--- a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
@@ -398,7 +398,7 @@ typedef void ( * portISR_t )( void );
  */
 static void prvTaskExitError( void );
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
  * @brief Extract MPU region's access permissions from the Region Base Address
@@ -409,7 +409,7 @@ static void prvTaskExitError( void );
  * @return uint32_t Access permissions.
  */
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0   */
 
 #if ( configENABLE_MPU == 1 )
 
@@ -871,7 +871,7 @@ static void prvTaskExitError( void )
 }
 /*-----------------------------------------------------------*/
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
     {
@@ -890,7 +890,7 @@ static void prvTaskExitError( void )
         return ulAccessPermissions;
     }
 
-#endif /* configENABLE_MPU */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0   */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
diff --git a/portable/IAR/ARM_CM33/non_secure/port.c b/portable/IAR/ARM_CM33/non_secure/port.c
index 5492c367a..5c963ea29 100644
--- a/portable/IAR/ARM_CM33/non_secure/port.c
+++ b/portable/IAR/ARM_CM33/non_secure/port.c
@@ -398,7 +398,7 @@ typedef void ( * portISR_t )( void );
  */
 static void prvTaskExitError( void );
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
  * @brief Extract MPU region's access permissions from the Region Base Address
@@ -409,7 +409,7 @@ static void prvTaskExitError( void );
  * @return uint32_t Access permissions.
  */
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0   */
 
 #if ( configENABLE_MPU == 1 )
 
@@ -871,7 +871,7 @@ static void prvTaskExitError( void )
 }
 /*-----------------------------------------------------------*/
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
     {
@@ -890,7 +890,7 @@ static void prvTaskExitError( void )
         return ulAccessPermissions;
     }
 
-#endif /* configENABLE_MPU */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0   */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
index 5492c367a..5c963ea29 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
@@ -398,7 +398,7 @@ typedef void ( * portISR_t )( void );
  */
 static void prvTaskExitError( void );
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
  * @brief Extract MPU region's access permissions from the Region Base Address
@@ -409,7 +409,7 @@ static void prvTaskExitError( void );
  * @return uint32_t Access permissions.
  */
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0   */
 
 #if ( configENABLE_MPU == 1 )
 
@@ -871,7 +871,7 @@ static void prvTaskExitError( void )
 }
 /*-----------------------------------------------------------*/
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
     {
@@ -890,7 +890,7 @@ static void prvTaskExitError( void )
         return ulAccessPermissions;
     }
 
-#endif /* configENABLE_MPU */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0   */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
diff --git a/portable/IAR/ARM_CM35P/non_secure/port.c b/portable/IAR/ARM_CM35P/non_secure/port.c
index 5492c367a..9fdbe6d50 100644
--- a/portable/IAR/ARM_CM35P/non_secure/port.c
+++ b/portable/IAR/ARM_CM35P/non_secure/port.c
@@ -398,7 +398,7 @@ typedef void ( * portISR_t )( void );
  */
 static void prvTaskExitError( void );
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
  * @brief Extract MPU region's access permissions from the Region Base Address
@@ -409,7 +409,7 @@ static void prvTaskExitError( void );
  * @return uint32_t Access permissions.
  */
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0   */
 
 #if ( configENABLE_MPU == 1 )
 
@@ -871,7 +871,7 @@ static void prvTaskExitError( void )
 }
 /*-----------------------------------------------------------*/
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
     {
@@ -890,7 +890,7 @@ static void prvTaskExitError( void )
         return ulAccessPermissions;
     }
 
-#endif /* configENABLE_MPU */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c b/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
index 5492c367a..f3f5d3edd 100644
--- a/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
@@ -398,7 +398,7 @@ typedef void ( * portISR_t )( void );
  */
 static void prvTaskExitError( void );
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
  * @brief Extract MPU region's access permissions from the Region Base Address
@@ -409,7 +409,7 @@ static void prvTaskExitError( void );
  * @return uint32_t Access permissions.
  */
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 
 #if ( configENABLE_MPU == 1 )
 
@@ -871,7 +871,7 @@ static void prvTaskExitError( void )
 }
 /*-----------------------------------------------------------*/
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
     {
@@ -890,7 +890,7 @@ static void prvTaskExitError( void )
         return ulAccessPermissions;
     }
 
-#endif /* configENABLE_MPU */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
diff --git a/portable/IAR/ARM_CM55/non_secure/port.c b/portable/IAR/ARM_CM55/non_secure/port.c
index 5492c367a..f3f5d3edd 100644
--- a/portable/IAR/ARM_CM55/non_secure/port.c
+++ b/portable/IAR/ARM_CM55/non_secure/port.c
@@ -398,7 +398,7 @@ typedef void ( * portISR_t )( void );
  */
 static void prvTaskExitError( void );
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
  * @brief Extract MPU region's access permissions from the Region Base Address
@@ -409,7 +409,7 @@ static void prvTaskExitError( void );
  * @return uint32_t Access permissions.
  */
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 
 #if ( configENABLE_MPU == 1 )
 
@@ -871,7 +871,7 @@ static void prvTaskExitError( void )
 }
 /*-----------------------------------------------------------*/
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
     {
@@ -890,7 +890,7 @@ static void prvTaskExitError( void )
         return ulAccessPermissions;
     }
 
-#endif /* configENABLE_MPU */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/port.c b/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
index 5492c367a..f3f5d3edd 100644
--- a/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
@@ -398,7 +398,7 @@ typedef void ( * portISR_t )( void );
  */
 static void prvTaskExitError( void );
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
  * @brief Extract MPU region's access permissions from the Region Base Address
@@ -409,7 +409,7 @@ static void prvTaskExitError( void );
  * @return uint32_t Access permissions.
  */
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 
 #if ( configENABLE_MPU == 1 )
 
@@ -871,7 +871,7 @@ static void prvTaskExitError( void )
 }
 /*-----------------------------------------------------------*/
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
     {
@@ -890,7 +890,7 @@ static void prvTaskExitError( void )
         return ulAccessPermissions;
     }
 
-#endif /* configENABLE_MPU */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
diff --git a/portable/IAR/ARM_CM85/non_secure/port.c b/portable/IAR/ARM_CM85/non_secure/port.c
index 5492c367a..f3f5d3edd 100644
--- a/portable/IAR/ARM_CM85/non_secure/port.c
+++ b/portable/IAR/ARM_CM85/non_secure/port.c
@@ -398,7 +398,7 @@ typedef void ( * portISR_t )( void );
  */
 static void prvTaskExitError( void );
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
  * @brief Extract MPU region's access permissions from the Region Base Address
@@ -409,7 +409,7 @@ static void prvTaskExitError( void );
  * @return uint32_t Access permissions.
  */
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 
 #if ( configENABLE_MPU == 1 )
 
@@ -871,7 +871,7 @@ static void prvTaskExitError( void )
 }
 /*-----------------------------------------------------------*/
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
     {
@@ -890,7 +890,7 @@ static void prvTaskExitError( void )
         return ulAccessPermissions;
     }
 
-#endif /* configENABLE_MPU */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/port.c b/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
index 5492c367a..f3f5d3edd 100644
--- a/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
@@ -398,7 +398,7 @@ typedef void ( * portISR_t )( void );
  */
 static void prvTaskExitError( void );
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
 /**
  * @brief Extract MPU region's access permissions from the Region Base Address
@@ -409,7 +409,7 @@ static void prvTaskExitError( void );
  * @return uint32_t Access permissions.
  */
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 
 #if ( configENABLE_MPU == 1 )
 
@@ -871,7 +871,7 @@ static void prvTaskExitError( void )
 }
 /*-----------------------------------------------------------*/
 
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
     {
@@ -890,7 +890,7 @@ static void prvTaskExitError( void )
         return ulAccessPermissions;
     }
 
-#endif /* configENABLE_MPU */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )

From 3ddfffda048a6991f5059332e949a2ee084a5173 Mon Sep 17 00:00:00 2001
From: wwhheerree <wwhheerree@hotmail.com>
Date: Mon, 16 Dec 2024 21:18:54 +0800
Subject: [PATCH 358/424] Regression Bug Fix: Fix Incorrect Return of
 MSVC-MingW portYIELD_FROM_ISR (#1207)

There is a regression issue introduced in
    https://github.com/FreeRTOS/FreeRTOS-Kernel/commit/cfc268814a94a4deb8ddc8322b63ccae270a8669.
    This PR was intended to update MIT licensed header from v9 to v10.
    But it accidentally changed "portYIELD_FROM_ISR( x )" in MSVC-MingW/portmacro.h.
    It caused "portYIELD_FROM_ISR( x )" does not return correct value to "prvProcessSimulatedInterrupts".
---
 portable/MSVC-MingW/portmacro.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/portable/MSVC-MingW/portmacro.h b/portable/MSVC-MingW/portmacro.h
index 288b7b037..eb94758be 100644
--- a/portable/MSVC-MingW/portmacro.h
+++ b/portable/MSVC-MingW/portmacro.h
@@ -112,7 +112,7 @@ extern volatile BaseType_t xInsideInterrupt;
 
 /* Simulated interrupts return pdFALSE if no context switch should be performed,
  * or a non-zero number if a context switch should be performed. */
-#define portYIELD_FROM_ISR( x )       ( void ) x
+#define portYIELD_FROM_ISR( x )       return x
 #define portEND_SWITCHING_ISR( x )    portYIELD_FROM_ISR( ( x ) )
 
 void vPortCloseRunningThread( void * pvTaskToDelete,

From e169442c29ba8e26faf033cc0886029dd5812979 Mon Sep 17 00:00:00 2001
From: Saiiijchan <49641410+Saiiijchan@users.noreply.github.com>
Date: Tue, 17 Dec 2024 19:55:20 +0800
Subject: [PATCH 359/424] Refine VFP context for Coretex-A9 (#1209)
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

s0–s15 (d0–d7, q0–q3) and d16–d31 (q8–q15) are caller save
register

Signed-off-by: wangfei_chen <wangfei_chen@realsil.com.cn>
Co-authored-by: wangfei_chen <wangfei_chen@realsil.com.cn>
---
 portable/GCC/ARM_CA9/portASM.S | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/portable/GCC/ARM_CA9/portASM.S b/portable/GCC/ARM_CA9/portASM.S
index 5e4b870b9..4dec1d72e 100644
--- a/portable/GCC/ARM_CA9/portASM.S
+++ b/portable/GCC/ARM_CA9/portASM.S
@@ -302,7 +302,7 @@ switch_before_exit:
 vApplicationIRQHandler:
     PUSH    {LR}
     FMRX    R1,  FPSCR
-    VPUSH   {D0-D15}
+    VPUSH   {D0-D7}
     VPUSH   {D16-D31}
     PUSH    {R1}
 
@@ -311,7 +311,7 @@ vApplicationIRQHandler:
 
     POP     {R0}
     VPOP    {D16-D31}
-    VPOP    {D0-D15}
+    VPOP    {D0-D7}
     VMSR    FPSCR, R0
 
     POP {PC}

From 31dd1e39cbe051213e096518d6751d483f598e3c Mon Sep 17 00:00:00 2001
From: Felix van Oost <felix.vanoost@live.com>
Date: Thu, 19 Dec 2024 03:50:43 -0500
Subject: [PATCH 360/424] Pass core ID to critical nesting count macros (#1206)

* Pass core ID to CRITICAL_NESTING_COUNT macros

* Match existing data type for xCoreID

* Get core ID when interrupts are disabled

* Implement get core ID with interrupt disabled

* Get core ID inline within vTaskSuspendAll() to resolve compiler warning

* Fix formatting check

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Ching-Hsin,Lee <chinglee@amazon.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
---
 .../ThirdParty/GCC/RP2040/include/portmacro.h |   8 +-
 tasks.c                                       | 146 ++++++++++--------
 2 files changed, 87 insertions(+), 67 deletions(-)

diff --git a/portable/ThirdParty/GCC/RP2040/include/portmacro.h b/portable/ThirdParty/GCC/RP2040/include/portmacro.h
index 14f58940c..ed9dbade0 100644
--- a/portable/ThirdParty/GCC/RP2040/include/portmacro.h
+++ b/portable/ThirdParty/GCC/RP2040/include/portmacro.h
@@ -158,10 +158,10 @@ void vYieldCore( int xCoreID );
 #define portCRITICAL_NESTING_IN_TCB    0
 
 extern UBaseType_t uxCriticalNestings[ configNUMBER_OF_CORES ];
-#define portGET_CRITICAL_NESTING_COUNT()          ( uxCriticalNestings[ portGET_CORE_ID() ] )
-#define portSET_CRITICAL_NESTING_COUNT( x )       ( uxCriticalNestings[ portGET_CORE_ID() ] = ( x ) )
-#define portINCREMENT_CRITICAL_NESTING_COUNT()    ( uxCriticalNestings[ portGET_CORE_ID() ]++ )
-#define portDECREMENT_CRITICAL_NESTING_COUNT()    ( uxCriticalNestings[ portGET_CORE_ID() ]-- )
+#define portGET_CRITICAL_NESTING_COUNT( xCoreID )          ( uxCriticalNestings[ ( xCoreID ) ] )
+#define portSET_CRITICAL_NESTING_COUNT( xCoreID, x )       ( uxCriticalNestings[ ( xCoreID ) ] = ( x ) )
+#define portINCREMENT_CRITICAL_NESTING_COUNT( xCoreID )    ( uxCriticalNestings[ ( xCoreID ) ]++ )
+#define portDECREMENT_CRITICAL_NESTING_COUNT( xCoreID )    ( uxCriticalNestings[ ( xCoreID ) ]-- )
 
 /*-----------------------------------------------------------*/
 
diff --git a/tasks.c b/tasks.c
index 22e11f0fb..7d9c87585 100644
--- a/tasks.c
+++ b/tasks.c
@@ -317,10 +317,10 @@
 #define taskATTRIBUTE_IS_IDLE    ( UBaseType_t ) ( 1U << 0U )
 
 #if ( ( configNUMBER_OF_CORES > 1 ) && ( portCRITICAL_NESTING_IN_TCB == 1 ) )
-    #define portGET_CRITICAL_NESTING_COUNT()          ( pxCurrentTCBs[ portGET_CORE_ID() ]->uxCriticalNesting )
-    #define portSET_CRITICAL_NESTING_COUNT( x )       ( pxCurrentTCBs[ portGET_CORE_ID() ]->uxCriticalNesting = ( x ) )
-    #define portINCREMENT_CRITICAL_NESTING_COUNT()    ( pxCurrentTCBs[ portGET_CORE_ID() ]->uxCriticalNesting++ )
-    #define portDECREMENT_CRITICAL_NESTING_COUNT()    ( pxCurrentTCBs[ portGET_CORE_ID() ]->uxCriticalNesting-- )
+    #define portGET_CRITICAL_NESTING_COUNT( xCoreID )          ( pxCurrentTCBs[ ( xCoreID ) ]->uxCriticalNesting )
+    #define portSET_CRITICAL_NESTING_COUNT( xCoreID, x )       ( pxCurrentTCBs[ ( xCoreID ) ]->uxCriticalNesting = ( x ) )
+    #define portINCREMENT_CRITICAL_NESTING_COUNT( xCoreID )    ( pxCurrentTCBs[ ( xCoreID ) ]->uxCriticalNesting++ )
+    #define portDECREMENT_CRITICAL_NESTING_COUNT( xCoreID )    ( pxCurrentTCBs[ ( xCoreID ) ]->uxCriticalNesting-- )
 #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( portCRITICAL_NESTING_IN_TCB == 1 ) ) */
 
 #define taskBITS_PER_BYTE    ( ( size_t ) 8 )
@@ -807,13 +807,14 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
     {
         UBaseType_t uxPrevCriticalNesting;
         const TCB_t * pxThisTCB;
+        BaseType_t xCoreID = ( BaseType_t ) portGET_CORE_ID();
 
         /* This must only be called from within a task. */
         portASSERT_IF_IN_ISR();
 
         /* This function is always called with interrupts disabled
          * so this is safe. */
-        pxThisTCB = pxCurrentTCBs[ portGET_CORE_ID() ];
+        pxThisTCB = pxCurrentTCBs[ xCoreID ];
 
         while( pxThisTCB->xTaskRunState == taskTASK_SCHEDULED_TO_YIELD )
         {
@@ -825,11 +826,11 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
             * the suspension and critical nesting counts, as well as release
             * and reacquire the correct locks. And then, do it all over again
             * if our state changed again during the reacquisition. */
-            uxPrevCriticalNesting = portGET_CRITICAL_NESTING_COUNT();
+            uxPrevCriticalNesting = portGET_CRITICAL_NESTING_COUNT( xCoreID );
 
             if( uxPrevCriticalNesting > 0U )
             {
-                portSET_CRITICAL_NESTING_COUNT( 0U );
+                portSET_CRITICAL_NESTING_COUNT( xCoreID, 0U );
                 portRELEASE_ISR_LOCK();
             }
             else
@@ -854,8 +855,9 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
             portDISABLE_INTERRUPTS();
             portGET_TASK_LOCK();
             portGET_ISR_LOCK();
+            xCoreID = ( BaseType_t ) portGET_CORE_ID();
 
-            portSET_CRITICAL_NESTING_COUNT( uxPrevCriticalNesting );
+            portSET_CRITICAL_NESTING_COUNT( xCoreID, uxPrevCriticalNesting );
 
             if( uxPrevCriticalNesting == 0U )
             {
@@ -874,13 +876,14 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
         BaseType_t xCurrentCoreTaskPriority;
         BaseType_t xLowestPriorityCore = ( BaseType_t ) -1;
         BaseType_t xCoreID;
+        const BaseType_t xCurrentCoreID = portGET_CORE_ID();
 
         #if ( configRUN_MULTIPLE_PRIORITIES == 0 )
             BaseType_t xYieldCount = 0;
         #endif /* #if ( configRUN_MULTIPLE_PRIORITIES == 0 ) */
 
         /* This must be called from a critical section. */
-        configASSERT( portGET_CRITICAL_NESTING_COUNT() > 0U );
+        configASSERT( portGET_CRITICAL_NESTING_COUNT( xCurrentCoreID ) > 0U );
 
         #if ( configRUN_MULTIPLE_PRIORITIES == 0 )
 
@@ -969,11 +972,11 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
 
             #if ( configRUN_MULTIPLE_PRIORITIES == 0 )
                 /* Verify that the calling core always yields to higher priority tasks. */
-                if( ( ( pxCurrentTCBs[ portGET_CORE_ID() ]->uxTaskAttributes & taskATTRIBUTE_IS_IDLE ) == 0U ) &&
-                    ( pxTCB->uxPriority > pxCurrentTCBs[ portGET_CORE_ID() ]->uxPriority ) )
+                if( ( ( pxCurrentTCBs[ xCurrentCoreID ]->uxTaskAttributes & taskATTRIBUTE_IS_IDLE ) == 0U ) &&
+                    ( pxTCB->uxPriority > pxCurrentTCBs[ xCurrentCoreID ]->uxPriority ) )
                 {
-                    configASSERT( ( xYieldPendings[ portGET_CORE_ID() ] == pdTRUE ) ||
-                                  ( taskTASK_IS_RUNNING( pxCurrentTCBs[ portGET_CORE_ID() ] ) == pdFALSE ) );
+                    configASSERT( ( xYieldPendings[ xCurrentCoreID ] == pdTRUE ) ||
+                                  ( taskTASK_IS_RUNNING( pxCurrentTCBs[ xCurrentCoreID ] ) == pdFALSE ) );
                 }
             #endif
         }
@@ -3880,7 +3883,7 @@ void vTaskSuspendAll( void )
             ulState = portSET_INTERRUPT_MASK();
 
             /* This must never be called from inside a critical section. */
-            configASSERT( portGET_CRITICAL_NESTING_COUNT() == 0 );
+            configASSERT( portGET_CRITICAL_NESTING_COUNT( portGET_CORE_ID() ) == 0 );
 
             /* portSOFTWARE_BARRIER() is only implemented for emulated/simulated ports that
              * do not otherwise exhibit real time behaviour. */
@@ -4003,8 +4006,7 @@ BaseType_t xTaskResumeAll( void )
          * tasks from this list into their appropriate ready list. */
         taskENTER_CRITICAL();
         {
-            BaseType_t xCoreID;
-            xCoreID = ( BaseType_t ) portGET_CORE_ID();
+            const BaseType_t xCoreID = ( BaseType_t ) portGET_CORE_ID();
 
             /* If uxSchedulerSuspended is zero then this function does not match a
              * previous call to vTaskSuspendAll(). */
@@ -5187,7 +5189,7 @@ BaseType_t xTaskIncrementTick( void )
             /* vTaskSwitchContext() must never be called from within a critical section.
              * This is not necessarily true for single core FreeRTOS, but it is for this
              * SMP port. */
-            configASSERT( portGET_CRITICAL_NESTING_COUNT() == 0 );
+            configASSERT( portGET_CRITICAL_NESTING_COUNT( xCoreID ) == 0 );
 
             if( uxSchedulerSuspended != ( UBaseType_t ) 0U )
             {
@@ -6937,16 +6939,24 @@ static void prvResetNextTaskUnblockTime( void )
  */
     void vTaskYieldWithinAPI( void )
     {
+        UBaseType_t ulState;
+
         traceENTER_vTaskYieldWithinAPI();
 
-        if( portGET_CRITICAL_NESTING_COUNT() == 0U )
+        ulState = portSET_INTERRUPT_MASK();
         {
-            portYIELD();
-        }
-        else
-        {
-            xYieldPendings[ portGET_CORE_ID() ] = pdTRUE;
+            const BaseType_t xCoreID = ( BaseType_t ) portGET_CORE_ID();
+
+            if( portGET_CRITICAL_NESTING_COUNT( xCoreID ) == 0U )
+            {
+                portYIELD();
+            }
+            else
+            {
+                xYieldPendings[ xCoreID ] = pdTRUE;
+            }
         }
+        portCLEAR_INTERRUPT_MASK( ulState );
 
         traceRETURN_vTaskYieldWithinAPI();
     }
@@ -6995,40 +7005,43 @@ static void prvResetNextTaskUnblockTime( void )
         traceENTER_vTaskEnterCritical();
 
         portDISABLE_INTERRUPTS();
-
-        if( xSchedulerRunning != pdFALSE )
         {
-            if( portGET_CRITICAL_NESTING_COUNT() == 0U )
+            const BaseType_t xCoreID = ( BaseType_t ) portGET_CORE_ID();
+
+            if( xSchedulerRunning != pdFALSE )
             {
-                portGET_TASK_LOCK();
-                portGET_ISR_LOCK();
-            }
-
-            portINCREMENT_CRITICAL_NESTING_COUNT();
-
-            /* This is not the interrupt safe version of the enter critical
-             * function so  assert() if it is being called from an interrupt
-             * context.  Only API functions that end in "FromISR" can be used in an
-             * interrupt.  Only assert if the critical nesting count is 1 to
-             * protect against recursive calls if the assert function also uses a
-             * critical section. */
-            if( portGET_CRITICAL_NESTING_COUNT() == 1U )
-            {
-                portASSERT_IF_IN_ISR();
-
-                if( uxSchedulerSuspended == 0U )
+                if( portGET_CRITICAL_NESTING_COUNT( xCoreID ) == 0U )
                 {
-                    /* The only time there would be a problem is if this is called
-                     * before a context switch and vTaskExitCritical() is called
-                     * after pxCurrentTCB changes. Therefore this should not be
-                     * used within vTaskSwitchContext(). */
-                    prvCheckForRunStateChange();
+                    portGET_TASK_LOCK();
+                    portGET_ISR_LOCK();
+                }
+
+                portINCREMENT_CRITICAL_NESTING_COUNT( xCoreID );
+
+                /* This is not the interrupt safe version of the enter critical
+                 * function so  assert() if it is being called from an interrupt
+                 * context.  Only API functions that end in "FromISR" can be used in an
+                 * interrupt.  Only assert if the critical nesting count is 1 to
+                 * protect against recursive calls if the assert function also uses a
+                 * critical section. */
+                if( portGET_CRITICAL_NESTING_COUNT( xCoreID ) == 1U )
+                {
+                    portASSERT_IF_IN_ISR();
+
+                    if( uxSchedulerSuspended == 0U )
+                    {
+                        /* The only time there would be a problem is if this is called
+                         * before a context switch and vTaskExitCritical() is called
+                         * after pxCurrentTCB changes. Therefore this should not be
+                         * used within vTaskSwitchContext(). */
+                        prvCheckForRunStateChange();
+                    }
                 }
             }
-        }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
         }
 
         traceRETURN_vTaskEnterCritical();
@@ -7043,6 +7056,7 @@ static void prvResetNextTaskUnblockTime( void )
     UBaseType_t vTaskEnterCriticalFromISR( void )
     {
         UBaseType_t uxSavedInterruptStatus = 0;
+        const BaseType_t xCoreID = ( BaseType_t ) portGET_CORE_ID();
 
         traceENTER_vTaskEnterCriticalFromISR();
 
@@ -7050,12 +7064,12 @@ static void prvResetNextTaskUnblockTime( void )
         {
             uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
 
-            if( portGET_CRITICAL_NESTING_COUNT() == 0U )
+            if( portGET_CRITICAL_NESTING_COUNT( xCoreID ) == 0U )
             {
                 portGET_ISR_LOCK();
             }
 
-            portINCREMENT_CRITICAL_NESTING_COUNT();
+            portINCREMENT_CRITICAL_NESTING_COUNT( xCoreID );
         }
         else
         {
@@ -7119,28 +7133,30 @@ static void prvResetNextTaskUnblockTime( void )
 
     void vTaskExitCritical( void )
     {
+        const BaseType_t xCoreID = ( BaseType_t ) portGET_CORE_ID();
+
         traceENTER_vTaskExitCritical();
 
         if( xSchedulerRunning != pdFALSE )
         {
             /* If critical nesting count is zero then this function
              * does not match a previous call to vTaskEnterCritical(). */
-            configASSERT( portGET_CRITICAL_NESTING_COUNT() > 0U );
+            configASSERT( portGET_CRITICAL_NESTING_COUNT( xCoreID ) > 0U );
 
             /* This function should not be called in ISR. Use vTaskExitCriticalFromISR
              * to exit critical section from ISR. */
             portASSERT_IF_IN_ISR();
 
-            if( portGET_CRITICAL_NESTING_COUNT() > 0U )
+            if( portGET_CRITICAL_NESTING_COUNT( xCoreID ) > 0U )
             {
-                portDECREMENT_CRITICAL_NESTING_COUNT();
+                portDECREMENT_CRITICAL_NESTING_COUNT( xCoreID );
 
-                if( portGET_CRITICAL_NESTING_COUNT() == 0U )
+                if( portGET_CRITICAL_NESTING_COUNT( xCoreID ) == 0U )
                 {
                     BaseType_t xYieldCurrentTask;
 
                     /* Get the xYieldPending stats inside the critical section. */
-                    xYieldCurrentTask = xYieldPendings[ portGET_CORE_ID() ];
+                    xYieldCurrentTask = xYieldPendings[ xCoreID ];
 
                     portRELEASE_ISR_LOCK();
                     portRELEASE_TASK_LOCK();
@@ -7180,19 +7196,23 @@ static void prvResetNextTaskUnblockTime( void )
 
     void vTaskExitCriticalFromISR( UBaseType_t uxSavedInterruptStatus )
     {
+        BaseType_t xCoreID;
+
         traceENTER_vTaskExitCriticalFromISR( uxSavedInterruptStatus );
 
         if( xSchedulerRunning != pdFALSE )
         {
+            xCoreID = ( BaseType_t ) portGET_CORE_ID();
+
             /* If critical nesting count is zero then this function
              * does not match a previous call to vTaskEnterCritical(). */
-            configASSERT( portGET_CRITICAL_NESTING_COUNT() > 0U );
+            configASSERT( portGET_CRITICAL_NESTING_COUNT( xCoreID ) > 0U );
 
-            if( portGET_CRITICAL_NESTING_COUNT() > 0U )
+            if( portGET_CRITICAL_NESTING_COUNT( xCoreID ) > 0U )
             {
-                portDECREMENT_CRITICAL_NESTING_COUNT();
+                portDECREMENT_CRITICAL_NESTING_COUNT( xCoreID );
 
-                if( portGET_CRITICAL_NESTING_COUNT() == 0U )
+                if( portGET_CRITICAL_NESTING_COUNT( xCoreID ) == 0U )
                 {
                     portRELEASE_ISR_LOCK();
                     portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );

From cc31510088d7f7472d57967ed0011b5303dffafa Mon Sep 17 00:00:00 2001
From: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Date: Fri, 20 Dec 2024 00:08:52 +0530
Subject: [PATCH 361/424] Remove unused config parameters (#1211)

These were reported here - https://github.com/FreeRTOS/FreeRTOS-Kernel/issues/1210.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 examples/coverity/FreeRTOSConfig.h               | 2 --
 examples/template_configuration/FreeRTOSConfig.h | 2 --
 2 files changed, 4 deletions(-)

diff --git a/examples/coverity/FreeRTOSConfig.h b/examples/coverity/FreeRTOSConfig.h
index 06b0f9a28..5feaa40de 100644
--- a/examples/coverity/FreeRTOSConfig.h
+++ b/examples/coverity/FreeRTOSConfig.h
@@ -118,7 +118,6 @@
 #define INCLUDE_uxTaskPriorityGet              1
 #define INCLUDE_vTaskDelete                    1
 #define INCLUDE_vTaskSuspend                   1
-#define INCLUDE_xResumeFromISR                 1
 #define INCLUDE_vTaskDelayUntil                1
 #define INCLUDE_vTaskDelay                     1
 #define INCLUDE_xTaskGetSchedulerState         1
@@ -126,7 +125,6 @@
 #define INCLUDE_uxTaskGetStackHighWaterMark    1
 #define INCLUDE_xTaskGetIdleTaskHandle         1
 #define INCLUDE_eTaskGetState                  1
-#define INCLUDE_xEventGroupSetBitFromISR       1
 #define INCLUDE_xTimerPendFunctionCall         1
 #define INCLUDE_xTaskAbortDelay                1
 #define INCLUDE_xTaskGetHandle                 1
diff --git a/examples/template_configuration/FreeRTOSConfig.h b/examples/template_configuration/FreeRTOSConfig.h
index 8c5e53066..5684e3c39 100644
--- a/examples/template_configuration/FreeRTOSConfig.h
+++ b/examples/template_configuration/FreeRTOSConfig.h
@@ -650,7 +650,6 @@
 #define INCLUDE_uxTaskPriorityGet              1
 #define INCLUDE_vTaskDelete                    1
 #define INCLUDE_vTaskSuspend                   1
-#define INCLUDE_xResumeFromISR                 1
 #define INCLUDE_vTaskDelayUntil                1
 #define INCLUDE_vTaskDelay                     1
 #define INCLUDE_xTaskGetSchedulerState         1
@@ -658,7 +657,6 @@
 #define INCLUDE_uxTaskGetStackHighWaterMark    0
 #define INCLUDE_xTaskGetIdleTaskHandle         0
 #define INCLUDE_eTaskGetState                  0
-#define INCLUDE_xEventGroupSetBitFromISR       1
 #define INCLUDE_xTimerPendFunctionCall         0
 #define INCLUDE_xTaskAbortDelay                0
 #define INCLUDE_xTaskGetHandle                 0

From f31787d35d5614620fc6fefa6c12df2583612fcf Mon Sep 17 00:00:00 2001
From: Sudeep Mohanty <91244425+sudeep-mohanty@users.noreply.github.com>
Date: Fri, 20 Dec 2024 13:13:04 +0530
Subject: [PATCH 362/424] fix(freertos): Limit idle task name length copy
 operation and ensure null-termination of the idle task name string (#1203)

* fix(freertos): Limit idle task name copy operation and ensure null termination

This commit:
- Limits the idle task name length copy operation to prevent
  Out-of-bounds memory access warnings from static code analyzers.
- Fixes a bug where in the idle task name could be non null-terminated
  string for SMP configuration.

Signed-off-by: Sudeep Mohanty <sudeep.mohanty@espressif.com>
---
 tasks.c | 51 ++++++++++++++++++---------------------------------
 1 file changed, 18 insertions(+), 33 deletions(-)

diff --git a/tasks.c b/tasks.c
index 7d9c87585..f6af37bab 100644
--- a/tasks.c
+++ b/tasks.c
@@ -3524,27 +3524,28 @@ static BaseType_t prvCreateIdleTasks( void )
 {
     BaseType_t xReturn = pdPASS;
     BaseType_t xCoreID;
-    char cIdleName[ configMAX_TASK_NAME_LEN ];
+    char cIdleName[ configMAX_TASK_NAME_LEN ] = { 0 };
     TaskFunction_t pxIdleTaskFunction = NULL;
     BaseType_t xIdleTaskNameIndex;
+    BaseType_t xIdleNameLen;
+    BaseType_t xCopyLen;
 
-    for( xIdleTaskNameIndex = ( BaseType_t ) 0; xIdleTaskNameIndex < ( BaseType_t ) configMAX_TASK_NAME_LEN; xIdleTaskNameIndex++ )
+    configASSERT( ( configIDLE_TASK_NAME != NULL ) && ( configMAX_TASK_NAME_LEN > 3 ) );
+
+    /* The length of the idle task name is limited to the minimum of the length
+     * of configIDLE_TASK_NAME and configMAX_TASK_NAME_LEN - 2, keeping space
+     * for the core ID suffix and the null-terminator. */
+    xIdleNameLen = strlen( configIDLE_TASK_NAME );
+    xCopyLen = xIdleNameLen < ( configMAX_TASK_NAME_LEN - 2 ) ? xIdleNameLen : ( configMAX_TASK_NAME_LEN - 2 );
+
+    for( xIdleTaskNameIndex = ( BaseType_t ) 0; xIdleTaskNameIndex < xCopyLen; xIdleTaskNameIndex++ )
     {
         cIdleName[ xIdleTaskNameIndex ] = configIDLE_TASK_NAME[ xIdleTaskNameIndex ];
-
-        /* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than
-         * configMAX_TASK_NAME_LEN characters just in case the memory after the
-         * string is not accessible (extremely unlikely). */
-        if( cIdleName[ xIdleTaskNameIndex ] == ( char ) 0x00 )
-        {
-            break;
-        }
-        else
-        {
-            mtCOVERAGE_TEST_MARKER();
-        }
     }
 
+    /* Ensure null termination. */
+    cIdleName[ xIdleTaskNameIndex ] = '\0';
+
     /* Add each idle task at the lowest priority. */
     for( xCoreID = ( BaseType_t ) 0; xCoreID < ( BaseType_t ) configNUMBER_OF_CORES; xCoreID++ )
     {
@@ -3573,25 +3574,9 @@ static BaseType_t prvCreateIdleTasks( void )
          * only one idle task. */
         #if ( configNUMBER_OF_CORES > 1 )
         {
-            /* Append the idle task number to the end of the name if there is space. */
-            if( xIdleTaskNameIndex < ( BaseType_t ) configMAX_TASK_NAME_LEN )
-            {
-                cIdleName[ xIdleTaskNameIndex ] = ( char ) ( xCoreID + '0' );
-
-                /* And append a null character if there is space. */
-                if( ( xIdleTaskNameIndex + 1 ) < ( BaseType_t ) configMAX_TASK_NAME_LEN )
-                {
-                    cIdleName[ xIdleTaskNameIndex + 1 ] = '\0';
-                }
-                else
-                {
-                    mtCOVERAGE_TEST_MARKER();
-                }
-            }
-            else
-            {
-                mtCOVERAGE_TEST_MARKER();
-            }
+            /* Append the idle task number to the end of the name. */
+            cIdleName[ xIdleTaskNameIndex ] = ( char ) ( xCoreID + '0' );
+            cIdleName[ xIdleTaskNameIndex + 1 ] = '\0';
         }
         #endif /* if ( configNUMBER_OF_CORES > 1 ) */
 

From f63bc2b5ccc8bd9a7804ca5c09609dc03bbbebd7 Mon Sep 17 00:00:00 2001
From: wwhheerree <wwhheerree@hotmail.com>
Date: Tue, 24 Dec 2024 19:11:44 +0800
Subject: [PATCH 363/424] Add an example of human readable table generated by
 vTaskListTasks() to tash.h (#1215)

* Add an example of human readable table generated by vTaskListTasks() to task.h
---
 include/task.h | 32 ++++++++++++++++++++++++--------
 1 file changed, 24 insertions(+), 8 deletions(-)

diff --git a/include/task.h b/include/task.h
index 0414eb9e2..a25740e3b 100644
--- a/include/task.h
+++ b/include/task.h
@@ -2199,8 +2199,8 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION;
  * Lists all the current tasks, along with their current state and stack
  * usage high water mark.
  *
- * Tasks are reported as blocked ('B'), ready ('R'), deleted ('D') or
- * suspended ('S').
+ * Tasks are reported as running ('X'), blocked ('B'), ready ('R'), deleted ('D')
+ * or suspended ('S').
  *
  * PLEASE NOTE:
  *
@@ -2208,8 +2208,16 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION;
  * demo applications.  Do not consider it to be part of the scheduler.
  *
  * vTaskListTasks() calls uxTaskGetSystemState(), then formats part of the
- * uxTaskGetSystemState() output into a human readable table that displays task:
- * names, states, priority, stack usage and task number.
+ * uxTaskGetSystemState() output into a human readable table that displays task
+ * information in the following format:
+ * Task Name, Task State, Task Priority, Task Stack High Watermak, Task Number.
+ *
+ * The following is a sample output:
+ * Task A       X       2           67           2
+ * Task B       R       1           67           3
+ * IDLE         R       0           67           5
+ * Tmr Svc      B       6           137          6
+ *
  * Stack usage specified as the number of unused StackType_t words stack can hold
  * on top of stack - not the number of bytes.
  *
@@ -2260,8 +2268,8 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION;
  * Lists all the current tasks, along with their current state and stack
  * usage high water mark.
  *
- * Tasks are reported as blocked ('B'), ready ('R'), deleted ('D') or
- * suspended ('S').
+ * Tasks are reported as running ('X'), blocked ('B'), ready ('R'), deleted ('D')
+ * or suspended ('S').
  *
  * PLEASE NOTE:
  *
@@ -2269,8 +2277,16 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION;
  * demo applications.  Do not consider it to be part of the scheduler.
  *
  * vTaskList() calls uxTaskGetSystemState(), then formats part of the
- * uxTaskGetSystemState() output into a human readable table that displays task:
- * names, states, priority, stack usage and task number.
+ * uxTaskGetSystemState() output into a human readable table that displays task
+ * information in the following format:
+ * Task Name, Task State, Task Priority, Task Stack High Watermak, Task Number.
+ *
+ * The following is a sample output:
+ * Task A       X       2           67           2
+ * Task B       R       1           67           3
+ * IDLE         R       0           67           5
+ * Tmr Svc      B       6           137          6
+ *
  * Stack usage specified as the number of unused StackType_t words stack can hold
  * on top of stack - not the number of bytes.
  *

From f05244a8d55b23428c4a8c097d375d12a9d6e30d Mon Sep 17 00:00:00 2001
From: Felix van Oost <felix.vanoost@live.com>
Date: Mon, 30 Dec 2024 03:58:49 -0500
Subject: [PATCH 364/424] Pass core ID to port lock macros (#1212)

Pass core ID to task/ISR lock functions
---
 include/FreeRTOS.h                            |  8 +--
 portable/CCRH/F1Kx/port.c                     | 10 ++--
 portable/CCRH/F1Kx/portmacro.h                | 20 ++++----
 .../ThirdParty/GCC/RP2040/include/portmacro.h | 30 ++++++------
 .../ThirdParty/xClang/XCOREAI/portmacro.h     |  9 ++--
 portable/template/portmacro.h                 |  8 +--
 tasks.c                                       | 49 +++++++++++--------
 7 files changed, 71 insertions(+), 63 deletions(-)

diff --git a/include/FreeRTOS.h b/include/FreeRTOS.h
index 3fecbdd73..dfccccb40 100644
--- a/include/FreeRTOS.h
+++ b/include/FreeRTOS.h
@@ -445,7 +445,7 @@
 #ifndef portRELEASE_TASK_LOCK
 
     #if ( configNUMBER_OF_CORES == 1 )
-        #define portRELEASE_TASK_LOCK()
+        #define portRELEASE_TASK_LOCK( xCoreID )
     #else
         #error portRELEASE_TASK_LOCK is required in SMP
     #endif
@@ -455,7 +455,7 @@
 #ifndef portGET_TASK_LOCK
 
     #if ( configNUMBER_OF_CORES == 1 )
-        #define portGET_TASK_LOCK()
+        #define portGET_TASK_LOCK( xCoreID )
     #else
         #error portGET_TASK_LOCK is required in SMP
     #endif
@@ -465,7 +465,7 @@
 #ifndef portRELEASE_ISR_LOCK
 
     #if ( configNUMBER_OF_CORES == 1 )
-        #define portRELEASE_ISR_LOCK()
+        #define portRELEASE_ISR_LOCK( xCoreID )
     #else
         #error portRELEASE_ISR_LOCK is required in SMP
     #endif
@@ -475,7 +475,7 @@
 #ifndef portGET_ISR_LOCK
 
     #if ( configNUMBER_OF_CORES == 1 )
-        #define portGET_ISR_LOCK()
+        #define portGET_ISR_LOCK( xCoreID )
     #else
         #error portGET_ISR_LOCK is required in SMP
     #endif
diff --git a/portable/CCRH/F1Kx/port.c b/portable/CCRH/F1Kx/port.c
index 0e6116527..3a43ff418 100644
--- a/portable/CCRH/F1Kx/port.c
+++ b/portable/CCRH/F1Kx/port.c
@@ -258,8 +258,8 @@ void vPortTickISR( void );
  * already had lock can acquire lock without waiting. This function could be
  * call from task and interrupt context, the critical section is called
  * as in ISR */
-    void vPortRecursiveLockAcquire( BaseType_t xFromIsr );
-    void vPortRecursiveLockRelease( BaseType_t xFromIsr );
+    void vPortRecursiveLockAcquire( BaseType_t xCoreID, BaseType_t xFromIsr );
+    void vPortRecursiveLockRelease( BaseType_t xCoreID, BaseType_t xFromIsr );
 
 #endif /* (configNUMBER_OF_CORES > 1) */
 
@@ -688,10 +688,9 @@ prvExclusiveLock_Lock_success:
     }
 
 /*-----------------------------------------------------------*/
-    void vPortRecursiveLockAcquire( BaseType_t xFromIsr )
+    void vPortRecursiveLockAcquire( BaseType_t xCoreID, BaseType_t xFromIsr )
     {
         BaseType_t xSavedInterruptStatus;
-        BaseType_t xCoreID = xPortGET_CORE_ID();
         BaseType_t xBitPosition = ( xFromIsr == pdTRUE );
 
         xSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
@@ -705,10 +704,9 @@ prvExclusiveLock_Lock_success:
         portCLEAR_INTERRUPT_MASK_FROM_ISR( xSavedInterruptStatus );
     }
 
-    void vPortRecursiveLockRelease( BaseType_t xFromIsr )
+    void vPortRecursiveLockRelease( BaseType_t xCoreID, BaseType_t xFromIsr )
     {
         BaseType_t xSavedInterruptStatus;
-        BaseType_t xCoreID = xPortGET_CORE_ID();
         BaseType_t xBitPosition = ( xFromIsr == pdTRUE );
 
         xSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
diff --git a/portable/CCRH/F1Kx/portmacro.h b/portable/CCRH/F1Kx/portmacro.h
index 09f9f4614..a665ad23d 100644
--- a/portable/CCRH/F1Kx/portmacro.h
+++ b/portable/CCRH/F1Kx/portmacro.h
@@ -141,18 +141,18 @@
     #endif /* if ( configNUMBER_OF_CORES > 1 ) */
 
     #if ( configNUMBER_OF_CORES == 1 )
-        #define portGET_ISR_LOCK()
-        #define portRELEASE_ISR_LOCK()
-        #define portGET_TASK_LOCK()
-        #define portRELEASE_TASK_LOCK()
+        #define portGET_ISR_LOCK( xCoreID )
+        #define portRELEASE_ISR_LOCK( xCoreID )
+        #define portGET_TASK_LOCK( xCoreID )
+        #define portRELEASE_TASK_LOCK( xCoreID )
     #else
-        extern void vPortRecursiveLockAcquire( BaseType_t xFromIsr );
-        extern void vPortRecursiveLockRelease( BaseType_t xFromIsr );
+        extern void vPortRecursiveLockAcquire( BaseType_t xCoreID, BaseType_t xFromIsr );
+        extern void vPortRecursiveLockRelease( BaseType_t xCoreID, BaseType_t xFromIsr );
 
-        #define portGET_ISR_LOCK()         vPortRecursiveLockAcquire( pdTRUE )
-        #define portRELEASE_ISR_LOCK()     vPortRecursiveLockRelease( pdTRUE )
-        #define portGET_TASK_LOCK()        vPortRecursiveLockAcquire( pdFALSE )
-        #define portRELEASE_TASK_LOCK()    vPortRecursiveLockRelease( pdFALSE )
+        #define portGET_ISR_LOCK( xCoreID )         vPortRecursiveLockAcquire( ( xCoreID ), pdTRUE )
+        #define portRELEASE_ISR_LOCK( xCoreID )     vPortRecursiveLockRelease( ( xCoreID ), pdTRUE )
+        #define portGET_TASK_LOCK( xCoreID )        vPortRecursiveLockAcquire( ( xCoreID ), pdFALSE )
+        #define portRELEASE_TASK_LOCK( xCoreID )    vPortRecursiveLockRelease( ( xCoreID ), pdFALSE )
     #endif /* if ( configNUMBER_OF_CORES == 1 ) */
 
 /*-----------------------------------------------------------*/
diff --git a/portable/ThirdParty/GCC/RP2040/include/portmacro.h b/portable/ThirdParty/GCC/RP2040/include/portmacro.h
index ed9dbade0..802470e33 100644
--- a/portable/ThirdParty/GCC/RP2040/include/portmacro.h
+++ b/portable/ThirdParty/GCC/RP2040/include/portmacro.h
@@ -210,8 +210,9 @@ __force_inline static bool spin_try_lock_unsafe(spin_lock_t *lock) {
 
 /* Note this is a single method with uxAcquire parameter since we have
  * static vars, the method is always called with a compile time constant for
- * uxAcquire, and the compiler should dothe right thing! */
-static inline void vPortRecursiveLock( uint32_t ulLockNum,
+ * uxAcquire, and the compiler should do the right thing! */
+static inline void vPortRecursiveLock( BaseType_t xCoreID,
+                                       uint32_t ulLockNum,
                                        spin_lock_t * pxSpinLock,
                                        BaseType_t uxAcquire )
 {
@@ -219,12 +220,11 @@ static inline void vPortRecursiveLock( uint32_t ulLockNum,
     static volatile uint8_t ucRecursionCountByLock[ portRTOS_SPINLOCK_COUNT ];
 
     configASSERT( ulLockNum < portRTOS_SPINLOCK_COUNT );
-    uint32_t ulCoreNum = get_core_num();
 
     if( uxAcquire )
     {
         if (!spin_try_lock_unsafe(pxSpinLock)) {
-            if( ucOwnedByCore[ ulCoreNum ][ ulLockNum ] )
+            if( ucOwnedByCore[ xCoreID ][ ulLockNum ] )
             {
                 configASSERT( ucRecursionCountByLock[ ulLockNum ] != 255u );
                 ucRecursionCountByLock[ ulLockNum ]++;
@@ -234,31 +234,31 @@ static inline void vPortRecursiveLock( uint32_t ulLockNum,
         }
         configASSERT( ucRecursionCountByLock[ ulLockNum ] == 0 );
         ucRecursionCountByLock[ ulLockNum ] = 1;
-        ucOwnedByCore[ ulCoreNum ][ ulLockNum ] = 1;
+        ucOwnedByCore[ xCoreID ][ ulLockNum ] = 1;
     }
     else
     {
-        configASSERT( ( ucOwnedByCore[ ulCoreNum ] [ulLockNum ] ) != 0 );
+        configASSERT( ( ucOwnedByCore[ xCoreID ] [ulLockNum ] ) != 0 );
         configASSERT( ucRecursionCountByLock[ ulLockNum ] != 0 );
 
         if( !--ucRecursionCountByLock[ ulLockNum ] )
         {
-            ucOwnedByCore[ ulCoreNum ] [ ulLockNum ] = 0;
+            ucOwnedByCore[ xCoreID ] [ ulLockNum ] = 0;
             spin_unlock_unsafe(pxSpinLock);
         }
     }
 }
 
 #if ( configNUMBER_OF_CORES == 1 )
-    #define portGET_ISR_LOCK()
-    #define portRELEASE_ISR_LOCK()
-    #define portGET_TASK_LOCK()
-    #define portRELEASE_TASK_LOCK()
+    #define portGET_ISR_LOCK( xCoreID )
+    #define portRELEASE_ISR_LOCK( xCoreID )
+    #define portGET_TASK_LOCK( xCoreID )
+    #define portRELEASE_TASK_LOCK( xCoreID )
 #else
-    #define portGET_ISR_LOCK()         vPortRecursiveLock( 0, spin_lock_instance( configSMP_SPINLOCK_0 ), pdTRUE )
-    #define portRELEASE_ISR_LOCK()     vPortRecursiveLock( 0, spin_lock_instance( configSMP_SPINLOCK_0 ), pdFALSE )
-    #define portGET_TASK_LOCK()        vPortRecursiveLock( 1, spin_lock_instance( configSMP_SPINLOCK_1 ), pdTRUE )
-    #define portRELEASE_TASK_LOCK()    vPortRecursiveLock( 1, spin_lock_instance( configSMP_SPINLOCK_1 ), pdFALSE )
+    #define portGET_ISR_LOCK( xCoreID )         vPortRecursiveLock( ( xCoreID ), 0, spin_lock_instance( configSMP_SPINLOCK_0 ), pdTRUE )
+    #define portRELEASE_ISR_LOCK( xCoreID )     vPortRecursiveLock( ( xCoreID ), 0, spin_lock_instance( configSMP_SPINLOCK_0 ), pdFALSE )
+    #define portGET_TASK_LOCK( xCoreID )        vPortRecursiveLock( ( xCoreID ), 1, spin_lock_instance( configSMP_SPINLOCK_1 ), pdTRUE )
+    #define portRELEASE_TASK_LOCK( xCoreID )    vPortRecursiveLock( ( xCoreID ), 1, spin_lock_instance( configSMP_SPINLOCK_1 ), pdFALSE )
 #endif
 
 /*-----------------------------------------------------------*/
diff --git a/portable/ThirdParty/xClang/XCOREAI/portmacro.h b/portable/ThirdParty/xClang/XCOREAI/portmacro.h
index 82da95314..088133314 100644
--- a/portable/ThirdParty/xClang/XCOREAI/portmacro.h
+++ b/portable/ThirdParty/xClang/XCOREAI/portmacro.h
@@ -152,10 +152,11 @@
 
         #define portASSERT_IF_IN_ISR()                    configASSERT( portCHECK_IF_IN_ISR() == 0 )
 
-        #define portGET_ISR_LOCK()                        rtos_lock_acquire( 0 )
-        #define portRELEASE_ISR_LOCK()                    rtos_lock_release( 0 )
-        #define portGET_TASK_LOCK()                       rtos_lock_acquire( 1 )
-        #define portRELEASE_TASK_LOCK()                   rtos_lock_release( 1 )
+        #define portGET_ISR_LOCK( xCoreID )               do{ ( void )( xCoreID ); rtos_lock_acquire( 0 ); } while( 0 )
+        #define portRELEASE_ISR_LOCK( xCoreID )           do{ ( void )( xCoreID ); rtos_lock_release( 0 ); } while( 0 )
+        #define portGET_TASK_LOCK( xCoreID )              do{ ( void )( xCoreID ); rtos_lock_acquire( 1 ); } while( 0 )
+        #define portRELEASE_TASK_LOCK( xCoreID )          do{ ( void )( xCoreID ); rtos_lock_release( 1 ); } while( 0 )
+
 
         void vTaskEnterCritical( void );
         void vTaskExitCritical( void );
diff --git a/portable/template/portmacro.h b/portable/template/portmacro.h
index 4a4a5876c..a426f0003 100644
--- a/portable/template/portmacro.h
+++ b/portable/template/portmacro.h
@@ -123,19 +123,19 @@ extern void vPortYield( void );
 
 /* Acquire the TASK lock. TASK lock is a recursive lock.
  * It should be able to be locked by the same core multiple times. */
-    #define portGET_TASK_LOCK()              do {} while( 0 )
+    #define portGET_TASK_LOCK( xCoreID )     do {} while( 0 )
 
 /* Release the TASK lock. If a TASK lock is locked by the same core multiple times,
  * it should be released as many times as it is locked. */
-    #define portRELEASE_TASK_LOCK()          do {} while( 0 )
+    #define portRELEASE_TASK_LOCK( xCoreID ) do {} while( 0 )
 
 /* Acquire the ISR lock. ISR lock is a recursive lock.
  * It should be able to be locked by the same core multiple times. */
-    #define portGET_ISR_LOCK()               do {} while( 0 )
+    #define portGET_ISR_LOCK( xCoreID )      do {} while( 0 )
 
 /* Release the ISR lock. If a ISR lock is locked by the same core multiple times, \
  * it should be released as many times as it is locked. */
-    #define portRELEASE_ISR_LOCK()           do {} while( 0 )
+    #define portRELEASE_ISR_LOCK( xCoreID )  do {} while( 0 )
 
 #endif /* if ( configNUMBER_OF_CORES > 1 ) */
 
diff --git a/tasks.c b/tasks.c
index f6af37bab..d7153f680 100644
--- a/tasks.c
+++ b/tasks.c
@@ -831,7 +831,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
             if( uxPrevCriticalNesting > 0U )
             {
                 portSET_CRITICAL_NESTING_COUNT( xCoreID, 0U );
-                portRELEASE_ISR_LOCK();
+                portRELEASE_ISR_LOCK( xCoreID );
             }
             else
             {
@@ -840,7 +840,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
                 mtCOVERAGE_TEST_MARKER();
             }
 
-            portRELEASE_TASK_LOCK();
+            portRELEASE_TASK_LOCK( xCoreID );
             portMEMORY_BARRIER();
             configASSERT( pxThisTCB->xTaskRunState == taskTASK_SCHEDULED_TO_YIELD );
 
@@ -853,15 +853,16 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
              * its run state. */
 
             portDISABLE_INTERRUPTS();
-            portGET_TASK_LOCK();
-            portGET_ISR_LOCK();
+
             xCoreID = ( BaseType_t ) portGET_CORE_ID();
+            portGET_TASK_LOCK( xCoreID );
+            portGET_ISR_LOCK( xCoreID );
 
             portSET_CRITICAL_NESTING_COUNT( xCoreID, uxPrevCriticalNesting );
 
             if( uxPrevCriticalNesting == 0U )
             {
-                portRELEASE_ISR_LOCK();
+                portRELEASE_ISR_LOCK( xCoreID );
             }
         }
     }
@@ -3854,6 +3855,7 @@ void vTaskSuspendAll( void )
     #else /* #if ( configNUMBER_OF_CORES == 1 ) */
     {
         UBaseType_t ulState;
+        BaseType_t xCoreID;
 
         /* This must only be called from within a task. */
         portASSERT_IF_IN_ISR();
@@ -3867,14 +3869,16 @@ void vTaskSuspendAll( void )
              * uxSchedulerSuspended since that will prevent context switches. */
             ulState = portSET_INTERRUPT_MASK();
 
+            xCoreID = ( BaseType_t ) portGET_CORE_ID();
+
             /* This must never be called from inside a critical section. */
-            configASSERT( portGET_CRITICAL_NESTING_COUNT( portGET_CORE_ID() ) == 0 );
+            configASSERT( portGET_CRITICAL_NESTING_COUNT( xCoreID ) == 0 );
 
             /* portSOFTWARE_BARRIER() is only implemented for emulated/simulated ports that
              * do not otherwise exhibit real time behaviour. */
             portSOFTWARE_BARRIER();
 
-            portGET_TASK_LOCK();
+            portGET_TASK_LOCK( xCoreID );
 
             /* uxSchedulerSuspended is increased after prvCheckForRunStateChange. The
              * purpose is to prevent altering the variable when fromISR APIs are readying
@@ -3888,12 +3892,17 @@ void vTaskSuspendAll( void )
                 mtCOVERAGE_TEST_MARKER();
             }
 
-            portGET_ISR_LOCK();
+            /* Query the coreID again as prvCheckForRunStateChange may have
+             * caused the task to get scheduled on a different core. The correct
+             * task lock for the core is acquired in prvCheckForRunStateChange. */
+            xCoreID = ( BaseType_t ) portGET_CORE_ID();
+
+            portGET_ISR_LOCK( xCoreID );
 
             /* The scheduler is suspended if uxSchedulerSuspended is non-zero. An increment
              * is used to allow calls to vTaskSuspendAll() to nest. */
             ++uxSchedulerSuspended;
-            portRELEASE_ISR_LOCK();
+            portRELEASE_ISR_LOCK( xCoreID );
 
             portCLEAR_INTERRUPT_MASK( ulState );
         }
@@ -3998,7 +4007,7 @@ BaseType_t xTaskResumeAll( void )
             configASSERT( uxSchedulerSuspended != 0U );
 
             uxSchedulerSuspended = ( UBaseType_t ) ( uxSchedulerSuspended - 1U );
-            portRELEASE_TASK_LOCK();
+            portRELEASE_TASK_LOCK( xCoreID );
 
             if( uxSchedulerSuspended == ( UBaseType_t ) 0U )
             {
@@ -5168,8 +5177,8 @@ BaseType_t xTaskIncrementTick( void )
          *   and move on if another core suspended the scheduler. We should only
          *   do that if the current core has suspended the scheduler. */
 
-        portGET_TASK_LOCK(); /* Must always acquire the task lock first. */
-        portGET_ISR_LOCK();
+        portGET_TASK_LOCK( xCoreID ); /* Must always acquire the task lock first. */
+        portGET_ISR_LOCK( xCoreID );
         {
             /* vTaskSwitchContext() must never be called from within a critical section.
              * This is not necessarily true for single core FreeRTOS, but it is for this
@@ -5250,8 +5259,8 @@ BaseType_t xTaskIncrementTick( void )
                 #endif
             }
         }
-        portRELEASE_ISR_LOCK();
-        portRELEASE_TASK_LOCK();
+        portRELEASE_ISR_LOCK( xCoreID );
+        portRELEASE_TASK_LOCK( xCoreID );
 
         traceRETURN_vTaskSwitchContext();
     }
@@ -6997,8 +7006,8 @@ static void prvResetNextTaskUnblockTime( void )
             {
                 if( portGET_CRITICAL_NESTING_COUNT( xCoreID ) == 0U )
                 {
-                    portGET_TASK_LOCK();
-                    portGET_ISR_LOCK();
+                    portGET_TASK_LOCK( xCoreID );
+                    portGET_ISR_LOCK( xCoreID );
                 }
 
                 portINCREMENT_CRITICAL_NESTING_COUNT( xCoreID );
@@ -7051,7 +7060,7 @@ static void prvResetNextTaskUnblockTime( void )
 
             if( portGET_CRITICAL_NESTING_COUNT( xCoreID ) == 0U )
             {
-                portGET_ISR_LOCK();
+                portGET_ISR_LOCK( xCoreID );
             }
 
             portINCREMENT_CRITICAL_NESTING_COUNT( xCoreID );
@@ -7143,8 +7152,8 @@ static void prvResetNextTaskUnblockTime( void )
                     /* Get the xYieldPending stats inside the critical section. */
                     xYieldCurrentTask = xYieldPendings[ xCoreID ];
 
-                    portRELEASE_ISR_LOCK();
-                    portRELEASE_TASK_LOCK();
+                    portRELEASE_ISR_LOCK( xCoreID );
+                    portRELEASE_TASK_LOCK( xCoreID );
                     portENABLE_INTERRUPTS();
 
                     /* When a task yields in a critical section it just sets
@@ -7199,7 +7208,7 @@ static void prvResetNextTaskUnblockTime( void )
 
                 if( portGET_CRITICAL_NESTING_COUNT( xCoreID ) == 0U )
                 {
-                    portRELEASE_ISR_LOCK();
+                    portRELEASE_ISR_LOCK( xCoreID );
                     portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
                 }
                 else

From e55bde213348c8911205f81e89016dd4ba2ba79d Mon Sep 17 00:00:00 2001
From: Ren Mingrui <972931182@qq.com>
Date: Mon, 30 Dec 2024 17:11:52 +0800
Subject: [PATCH 365/424] Add a stack pointer bounds check when
 configCHECK_FOR_STACK_OVERFLOW is set to 2. (#1216)

Add a stack pointer bounds check when configCHECK_FOR_STACK_OVERFLOW is set to 2.
---
 include/stack_macros.h | 31 ++++++++++++++++---------------
 1 file changed, 16 insertions(+), 15 deletions(-)

diff --git a/include/stack_macros.h b/include/stack_macros.h
index c1018b68a..a9c5764bb 100644
--- a/include/stack_macros.h
+++ b/include/stack_macros.h
@@ -88,19 +88,20 @@
 
 #if ( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) )
 
-    #define taskCHECK_FOR_STACK_OVERFLOW()                                                      \
-    do {                                                                                        \
-        const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack;                 \
-        const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5U;                                 \
-                                                                                                \
-        if( ( pulStack[ 0 ] != ulCheckValue ) ||                                                \
-            ( pulStack[ 1 ] != ulCheckValue ) ||                                                \
-            ( pulStack[ 2 ] != ulCheckValue ) ||                                                \
-            ( pulStack[ 3 ] != ulCheckValue ) )                                                 \
-        {                                                                                       \
-            char * pcOverflowTaskName = pxCurrentTCB->pcTaskName;                               \
-            vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pcOverflowTaskName ); \
-        }                                                                                       \
+    #define taskCHECK_FOR_STACK_OVERFLOW()                                                       \
+    do {                                                                                         \
+        const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack;                  \
+        const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5U;                                  \
+                                                                                                 \
+        if( ( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack + portSTACK_LIMIT_PADDING ) || \
+            ( pulStack[ 0 ] != ulCheckValue ) ||                                                 \
+            ( pulStack[ 1 ] != ulCheckValue ) ||                                                 \
+            ( pulStack[ 2 ] != ulCheckValue ) ||                                                 \
+            ( pulStack[ 3 ] != ulCheckValue ) )                                                  \
+        {                                                                                        \
+            char * pcOverflowTaskName = pxCurrentTCB->pcTaskName;                                \
+            vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pcOverflowTaskName );  \
+        }                                                                                        \
     } while( 0 )
 
 #endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
@@ -120,8 +121,8 @@
                                                                                                                                           \
         pcEndOfStack -= sizeof( ucExpectedStackBytes );                                                                                   \
                                                                                                                                           \
-        /* Has the extremity of the task stack ever been written over? */                                                                 \
-        if( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 )                     \
+        if( ( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack - portSTACK_LIMIT_PADDING ) ||                                     \
+            ( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 ) )                 \
         {                                                                                                                                 \
             char * pcOverflowTaskName = pxCurrentTCB->pcTaskName;                                                                         \
             vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pcOverflowTaskName );                                           \

From 3a7b3082cfce01ffba07b9be1398795b8307b05a Mon Sep 17 00:00:00 2001
From: iotah <writeforever@foxmail.com>
Date: Mon, 6 Jan 2025 13:35:53 +0800
Subject: [PATCH 366/424] Update community supported ports submodulees (#1218)

Signed-off-by: Hua Zheng <hua.zheng@embeddedboys.com>
Co-authored-by: Hua Zheng <hua.zheng@embeddedboys.com>
---
 portable/ThirdParty/Community-Supported-Ports | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/portable/ThirdParty/Community-Supported-Ports b/portable/ThirdParty/Community-Supported-Ports
index 8b2955f6d..3c5bfb8f2 160000
--- a/portable/ThirdParty/Community-Supported-Ports
+++ b/portable/ThirdParty/Community-Supported-Ports
@@ -1 +1 @@
-Subproject commit 8b2955f6d97bf4cd582db9f5b62d9eb1587b76d7
+Subproject commit 3c5bfb8f2e557735b5200176b4a8b25a40c68d1b

From c38427eea442b5a58b0b95ad88ff769be3abcc0d Mon Sep 17 00:00:00 2001
From: creiter64 <106512497+creiter64@users.noreply.github.com>
Date: Mon, 13 Jan 2025 23:48:10 +0100
Subject: [PATCH 367/424] Fix function parameter shadowing global variable.
 (#1221)

The function vApplicationFPUSafeIRQHandler gets the value of ICCIAR as
parameter, but a constant containing the address of ICCIAR was also
defined. Fix the name of the constant to align it with what it actually
holds.
---
 portable/GCC/ARM_CA9/port.c    |  6 +++---
 portable/GCC/ARM_CA9/portASM.S | 14 +++++++-------
 2 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/portable/GCC/ARM_CA9/port.c b/portable/GCC/ARM_CA9/port.c
index 0fd9dd471..67bb0fc8c 100644
--- a/portable/GCC/ARM_CA9/port.c
+++ b/portable/GCC/ARM_CA9/port.c
@@ -208,9 +208,9 @@ volatile uint32_t ulPortYieldRequired = pdFALSE;
 volatile uint32_t ulPortInterruptNesting = 0UL;
 
 /* Used in the asm file. */
-__attribute__( ( used ) ) const uint32_t ulICCIAR = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS;
-__attribute__( ( used ) ) const uint32_t ulICCEOIR = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS;
-__attribute__( ( used ) ) const uint32_t ulICCPMR = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS;
+__attribute__( ( used ) ) const uint32_t ulICCIARAddress = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS;
+__attribute__( ( used ) ) const uint32_t ulICCEOIRAddress = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS;
+__attribute__( ( used ) ) const uint32_t ulICCPMRAddress = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS;
 __attribute__( ( used ) ) const uint32_t ulMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
 
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CA9/portASM.S b/portable/GCC/ARM_CA9/portASM.S
index 4dec1d72e..5df123479 100644
--- a/portable/GCC/ARM_CA9/portASM.S
+++ b/portable/GCC/ARM_CA9/portASM.S
@@ -33,10 +33,10 @@
     .set SVC_MODE,  0x13
     .set IRQ_MODE,  0x12
 
-    /* Hardware registers. */
-    .extern ulICCIAR
-    .extern ulICCEOIR
-    .extern ulICCPMR
+    /* Hardware registers addresses. */
+    .extern ulICCIARAddress
+    .extern ulICCEOIRAddress
+    .extern ulICCPMRAddress
 
     /* Variables and functions. */
     .extern ulMaxAPIPriorityMask
@@ -317,9 +317,9 @@ vApplicationIRQHandler:
     POP {PC}
 
 
-ulICCIARConst:  .word ulICCIAR
-ulICCEOIRConst: .word ulICCEOIR
-ulICCPMRConst: .word ulICCPMR
+ulICCIARConst:  .word ulICCIARAddress
+ulICCEOIRConst: .word ulICCEOIRAddress
+ulICCPMRConst: .word ulICCPMRAddress
 pxCurrentTCBConst: .word pxCurrentTCB
 ulCriticalNestingConst: .word ulCriticalNesting
 ulPortTaskHasFPUContextConst: .word ulPortTaskHasFPUContext

From 78e0cc778ae01100ce7ca0eaf838567cd19f9720 Mon Sep 17 00:00:00 2001
From: Ahmed Ismail <64546783+AhmedIsmail02@users.noreply.github.com>
Date: Tue, 14 Jan 2025 05:20:52 +0000
Subject: [PATCH 368/424] ARMv8.1-M: Add task dedicated PAC key support (#1195)

armv8.1-m: Add task dedicated PAC key

To harden the security, each task is assigned a dedicated PAC key, so that attackers needs to guess the all the tasks' PAC keys right to exploit the system using Return Oriented Programming.

The kernel is now updated to support the following:
* A PAC key set with a random number generated and is saved in the task's context when a task is created.
* As part of scheduling, the task's PAC key is stored/restored to/from the task's context when a task is unscheduled/scheduled from/to run.

stack-overflow-check: Introduce portGET_CURRENT_TOP_OF_STACK macro

When MPU wrapper v2 is used, the task's context is stored in TCB and `pxTopOfStack`` member of TCB points to the context location in TCB. We, therefore, need to read PSP to find the task's current top of stack.

Signed-off-by: Ahmed Ismail <Ahmed.Ismail@arm.com>
---
 .github/.cSpellWords.txt                      |   2 +
 include/portable.h                            |   4 +
 include/stack_macros.h                        |  68 +++--
 portable/ARMv8M/non_secure/port.c             | 159 ++++++----
 .../portable/GCC/ARM_CM23/portmacro.h         |   2 +-
 .../portable/GCC/ARM_CM23_NTZ/portmacro.h     |   2 +-
 .../portable/GCC/ARM_CM33/portasm.c           | 285 ++++++++++--------
 .../portable/GCC/ARM_CM33/portmacro.h         |   2 +-
 .../portable/GCC/ARM_CM33_NTZ/portasm.c       | 144 ++++++---
 .../portable/GCC/ARM_CM33_NTZ/portmacro.h     |   2 +-
 .../portable/GCC/ARM_CM35P/portmacro.h        |   2 +-
 .../portable/IAR/ARM_CM23/portmacro.h         |   2 +-
 .../portable/IAR/ARM_CM23_NTZ/portmacro.h     |   2 +-
 .../portable/IAR/ARM_CM33/portasm.s           | 120 +++++---
 .../portable/IAR/ARM_CM33/portmacro.h         |   2 +-
 .../portable/IAR/ARM_CM33_NTZ/portasm.s       |  53 +++-
 .../portable/IAR/ARM_CM33_NTZ/portmacro.h     |   2 +-
 .../portable/IAR/ARM_CM35P/portmacro.h        |   2 +-
 portable/ARMv8M/non_secure/portmacrocommon.h  | 175 +++++++----
 portable/GCC/ARM_CM23/non_secure/port.c       | 159 ++++++----
 portable/GCC/ARM_CM23/non_secure/portmacro.h  |   2 +-
 .../GCC/ARM_CM23/non_secure/portmacrocommon.h | 175 +++++++----
 portable/GCC/ARM_CM23_NTZ/non_secure/port.c   | 159 ++++++----
 .../GCC/ARM_CM23_NTZ/non_secure/portmacro.h   |   2 +-
 .../ARM_CM23_NTZ/non_secure/portmacrocommon.h | 175 +++++++----
 portable/GCC/ARM_CM33/non_secure/port.c       | 163 ++++++----
 portable/GCC/ARM_CM33/non_secure/portasm.c    | 285 ++++++++++--------
 portable/GCC/ARM_CM33/non_secure/portmacro.h  |   2 +-
 .../GCC/ARM_CM33/non_secure/portmacrocommon.h | 175 +++++++----
 portable/GCC/ARM_CM33_NTZ/non_secure/port.c   | 163 ++++++----
 .../GCC/ARM_CM33_NTZ/non_secure/portasm.c     | 144 ++++++---
 .../GCC/ARM_CM33_NTZ/non_secure/portmacro.h   |   2 +-
 .../ARM_CM33_NTZ/non_secure/portmacrocommon.h | 175 +++++++----
 portable/GCC/ARM_CM35P/non_secure/port.c      | 163 ++++++----
 portable/GCC/ARM_CM35P/non_secure/portasm.c   | 285 ++++++++++--------
 portable/GCC/ARM_CM35P/non_secure/portmacro.h |   2 +-
 .../ARM_CM35P/non_secure/portmacrocommon.h    | 175 +++++++----
 portable/GCC/ARM_CM35P_NTZ/non_secure/port.c  | 163 ++++++----
 .../GCC/ARM_CM35P_NTZ/non_secure/portasm.c    | 144 ++++++---
 .../GCC/ARM_CM35P_NTZ/non_secure/portmacro.h  |   2 +-
 .../non_secure/portmacrocommon.h              | 175 +++++++----
 portable/GCC/ARM_CM55/non_secure/port.c       | 163 ++++++----
 portable/GCC/ARM_CM55/non_secure/portasm.c    | 285 ++++++++++--------
 .../GCC/ARM_CM55/non_secure/portmacrocommon.h | 175 +++++++----
 portable/GCC/ARM_CM55_NTZ/non_secure/port.c   | 163 ++++++----
 .../GCC/ARM_CM55_NTZ/non_secure/portasm.c     | 144 ++++++---
 .../ARM_CM55_NTZ/non_secure/portmacrocommon.h | 175 +++++++----
 portable/GCC/ARM_CM85/non_secure/port.c       | 163 ++++++----
 portable/GCC/ARM_CM85/non_secure/portasm.c    | 285 ++++++++++--------
 .../GCC/ARM_CM85/non_secure/portmacrocommon.h | 175 +++++++----
 portable/GCC/ARM_CM85_NTZ/non_secure/port.c   | 163 ++++++----
 .../GCC/ARM_CM85_NTZ/non_secure/portasm.c     | 144 ++++++---
 .../ARM_CM85_NTZ/non_secure/portmacrocommon.h | 175 +++++++----
 portable/IAR/ARM_CM23/non_secure/port.c       | 163 ++++++----
 portable/IAR/ARM_CM23/non_secure/portmacro.h  |   2 +-
 .../IAR/ARM_CM23/non_secure/portmacrocommon.h | 175 +++++++----
 portable/IAR/ARM_CM23_NTZ/non_secure/port.c   | 163 ++++++----
 .../IAR/ARM_CM23_NTZ/non_secure/portmacro.h   |   2 +-
 .../ARM_CM23_NTZ/non_secure/portmacrocommon.h | 175 +++++++----
 portable/IAR/ARM_CM33/non_secure/port.c       | 163 ++++++----
 portable/IAR/ARM_CM33/non_secure/portasm.s    | 120 +++++---
 portable/IAR/ARM_CM33/non_secure/portmacro.h  |   2 +-
 .../IAR/ARM_CM33/non_secure/portmacrocommon.h | 175 +++++++----
 portable/IAR/ARM_CM33_NTZ/non_secure/port.c   | 163 ++++++----
 .../IAR/ARM_CM33_NTZ/non_secure/portasm.s     |  53 +++-
 .../IAR/ARM_CM33_NTZ/non_secure/portmacro.h   |   2 +-
 .../ARM_CM33_NTZ/non_secure/portmacrocommon.h | 175 +++++++----
 portable/IAR/ARM_CM35P/non_secure/port.c      | 161 ++++++----
 portable/IAR/ARM_CM35P/non_secure/portasm.s   | 120 +++++---
 portable/IAR/ARM_CM35P/non_secure/portmacro.h |   2 +-
 .../ARM_CM35P/non_secure/portmacrocommon.h    | 175 +++++++----
 portable/IAR/ARM_CM35P_NTZ/non_secure/port.c  | 159 ++++++----
 .../IAR/ARM_CM35P_NTZ/non_secure/portasm.s    |  53 +++-
 .../IAR/ARM_CM35P_NTZ/non_secure/portmacro.h  |   2 +-
 .../non_secure/portmacrocommon.h              | 175 +++++++----
 portable/IAR/ARM_CM55/non_secure/port.c       | 159 ++++++----
 portable/IAR/ARM_CM55/non_secure/portasm.s    | 120 +++++---
 .../IAR/ARM_CM55/non_secure/portmacrocommon.h | 175 +++++++----
 portable/IAR/ARM_CM55_NTZ/non_secure/port.c   | 159 ++++++----
 .../IAR/ARM_CM55_NTZ/non_secure/portasm.s     |  53 +++-
 .../ARM_CM55_NTZ/non_secure/portmacrocommon.h | 175 +++++++----
 portable/IAR/ARM_CM85/non_secure/port.c       | 159 ++++++----
 portable/IAR/ARM_CM85/non_secure/portasm.s    | 120 +++++---
 .../IAR/ARM_CM85/non_secure/portmacrocommon.h | 175 +++++++----
 portable/IAR/ARM_CM85_NTZ/non_secure/port.c   | 159 ++++++----
 .../IAR/ARM_CM85_NTZ/non_secure/portasm.s     |  53 +++-
 .../ARM_CM85_NTZ/non_secure/portmacrocommon.h | 175 +++++++----
 87 files changed, 6662 insertions(+), 3530 deletions(-)

diff --git a/.github/.cSpellWords.txt b/.github/.cSpellWords.txt
index d100fcd49..3582741e3 100644
--- a/.github/.cSpellWords.txt
+++ b/.github/.cSpellWords.txt
@@ -106,6 +106,7 @@ CLKSOURCE
 CLKSTA
 CLRB
 CLRF
+clrm
 CLRPSW
 CMCNT
 CMCON
@@ -678,6 +679,7 @@ pylint
 pytest
 pyyaml
 RAMPZ
+randomisation
 RASR
 Rationalised
 Raynald
diff --git a/include/portable.h b/include/portable.h
index 68e11e793..c9b744535 100644
--- a/include/portable.h
+++ b/include/portable.h
@@ -93,6 +93,10 @@
     #define portBASE_TYPE_EXIT_CRITICAL()    taskEXIT_CRITICAL()
 #endif
 
+#ifndef portGET_CURRENT_TOP_OF_STACK
+    #define portGET_CURRENT_TOP_OF_STACK( pxCurrentTopOfStack )    { pxCurrentTopOfStack = ( StackType_t * ) pxCurrentTCB->pxTopOfStack; }
+#endif
+
 #ifndef configSTACK_DEPTH_TYPE
     #define configSTACK_DEPTH_TYPE    StackType_t
 #endif
diff --git a/include/stack_macros.h b/include/stack_macros.h
index a9c5764bb..300be4cb3 100644
--- a/include/stack_macros.h
+++ b/include/stack_macros.h
@@ -57,9 +57,13 @@
 
 /* Only the current stack state is to be checked. */
     #define taskCHECK_FOR_STACK_OVERFLOW()                                                      \
-    do {                                                                                        \
+    do                                                                                          \
+    {                                                                                           \
+        StackType_t * pxCurrentTopOfStack;                                                      \
+        portGET_CURRENT_TOP_OF_STACK( pxCurrentTopOfStack );                                    \
+                                                                                                \
         /* Is the currently saved stack pointer within the stack limit? */                      \
-        if( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack + portSTACK_LIMIT_PADDING )     \
+        if( pxCurrentTopOfStack <= pxCurrentTCB->pxStack + portSTACK_LIMIT_PADDING )            \
         {                                                                                       \
             char * pcOverflowTaskName = pxCurrentTCB->pcTaskName;                               \
             vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pcOverflowTaskName ); \
@@ -72,15 +76,18 @@
 #if ( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH > 0 ) )
 
 /* Only the current stack state is to be checked. */
-    #define taskCHECK_FOR_STACK_OVERFLOW()                                                       \
-    do {                                                                                         \
-                                                                                                 \
-        /* Is the currently saved stack pointer within the stack limit? */                       \
-        if( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack - portSTACK_LIMIT_PADDING ) \
-        {                                                                                        \
-            char * pcOverflowTaskName = pxCurrentTCB->pcTaskName;                                \
-            vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pcOverflowTaskName );  \
-        }                                                                                        \
+    #define taskCHECK_FOR_STACK_OVERFLOW()                                                      \
+    do                                                                                          \
+    {                                                                                           \
+        StackType_t * pxCurrentTopOfStack;                                                      \
+        portGET_CURRENT_TOP_OF_STACK( pxCurrentTopOfStack );                                    \
+                                                                                                \
+        /* Is the currently saved stack pointer within the stack limit? */                      \
+        if( pxCurrentTopOfStack >= pxCurrentTCB->pxEndOfStack - portSTACK_LIMIT_PADDING )       \
+        {                                                                                       \
+            char * pcOverflowTaskName = pxCurrentTCB->pcTaskName;                               \
+            vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pcOverflowTaskName ); \
+        }                                                                                       \
     } while( 0 )
 
 #endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
@@ -88,20 +95,23 @@
 
 #if ( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) )
 
-    #define taskCHECK_FOR_STACK_OVERFLOW()                                                       \
-    do {                                                                                         \
-        const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack;                  \
-        const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5U;                                  \
-                                                                                                 \
-        if( ( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack + portSTACK_LIMIT_PADDING ) || \
-            ( pulStack[ 0 ] != ulCheckValue ) ||                                                 \
-            ( pulStack[ 1 ] != ulCheckValue ) ||                                                 \
-            ( pulStack[ 2 ] != ulCheckValue ) ||                                                 \
-            ( pulStack[ 3 ] != ulCheckValue ) )                                                  \
-        {                                                                                        \
-            char * pcOverflowTaskName = pxCurrentTCB->pcTaskName;                                \
-            vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pcOverflowTaskName );  \
-        }                                                                                        \
+    #define taskCHECK_FOR_STACK_OVERFLOW()                                                      \
+    do                                                                                          \
+    {                                                                                           \
+        const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack;                 \
+        const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5U;                                 \
+        StackType_t * pxCurrentTopOfStack;                                                      \
+        portGET_CURRENT_TOP_OF_STACK( pxCurrentTopOfStack );                                    \
+                                                                                                \
+        if( ( pxCurrentTopOfStack <= pxCurrentTCB->pxStack + portSTACK_LIMIT_PADDING ) ||       \
+            ( pulStack[ 0 ] != ulCheckValue ) ||                                                \
+            ( pulStack[ 1 ] != ulCheckValue ) ||                                                \
+            ( pulStack[ 2 ] != ulCheckValue ) ||                                                \
+            ( pulStack[ 3 ] != ulCheckValue ) )                                                 \
+        {                                                                                       \
+            char * pcOverflowTaskName = pxCurrentTCB->pcTaskName;                               \
+            vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pcOverflowTaskName ); \
+        }                                                                                       \
     } while( 0 )
 
 #endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
@@ -110,18 +120,20 @@
 #if ( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) )
 
     #define taskCHECK_FOR_STACK_OVERFLOW()                                                                                                \
-    do {                                                                                                                                  \
+    do                                                                                                                                    \
+    {                                                                                                                                     \
         int8_t * pcEndOfStack = ( int8_t * ) pxCurrentTCB->pxEndOfStack;                                                                  \
         static const uint8_t ucExpectedStackBytes[] = { tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,   \
                                                         tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,   \
                                                         tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,   \
                                                         tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,   \
                                                         tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE }; \
-                                                                                                                                          \
+        StackType_t * pxCurrentTopOfStack;                                                                                                \
+        portGET_CURRENT_TOP_OF_STACK( pxCurrentTopOfStack );                                                                              \
                                                                                                                                           \
         pcEndOfStack -= sizeof( ucExpectedStackBytes );                                                                                   \
                                                                                                                                           \
-        if( ( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack - portSTACK_LIMIT_PADDING ) ||                                     \
+        if( ( pxCurrentTopOfStack >= pxCurrentTCB->pxEndOfStack - portSTACK_LIMIT_PADDING ) ||                                            \
             ( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 ) )                 \
         {                                                                                                                                 \
             char * pcOverflowTaskName = pxCurrentTCB->pcTaskName;                                                                         \
diff --git a/portable/ARMv8M/non_secure/port.c b/portable/ARMv8M/non_secure/port.c
index f3f5d3edd..b2fd7e518 100644
--- a/portable/ARMv8M/non_secure/port.c
+++ b/portable/ARMv8M/non_secure/port.c
@@ -169,79 +169,80 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                            ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                            ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                             ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                            ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                            ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                           ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                           ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK        ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                      ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK                     ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                      ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK                     ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                      ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK                     ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                      ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK                     ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                      ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK                     ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                      ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK                     ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                      ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK                     ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                      ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK                     ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0                    ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1                    ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2                    ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3                    ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4                    ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5                    ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6                    ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7                    ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE                  ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
 
 #if ( portARMV8M_MINOR_VERSION >= 1 )
-    /* Enable Privileged eXecute Never MPU attribute for the selected memory
-     * region. */
-    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER   ( 1UL << 4UL )
+
+/* Enable Privileged eXecute Never MPU attribute for the selected memory
+ * region. */
+    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER    ( 1UL << 4UL )
 #endif /* portARMV8M_MINOR_VERSION >= 1 */
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT          ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                          ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE                 ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -380,14 +381,14 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to check and configure PACBTI security feature implementation.
  */
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
-    #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
+    #define portID_ISAR5_REG       ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
 
-    #define portCONTROL_UPAC_EN      ( 1UL << 7UL )
-    #define portCONTROL_PAC_EN       ( 1UL << 6UL )
-    #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
-    #define portCONTROL_BTI_EN       ( 1UL << 4UL )
+    #define portCONTROL_UPAC_EN    ( 1UL << 7UL )
+    #define portCONTROL_PAC_EN     ( 1UL << 6UL )
+    #define portCONTROL_UBTI_EN    ( 1UL << 5UL )
+    #define portCONTROL_BTI_EN     ( 1UL << 4UL )
 
 #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
@@ -427,7 +428,7 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
 /**
  * @brief Configures PACBTI features.
@@ -1212,6 +1213,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
+
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __syscalls_flash_start__;
@@ -1282,6 +1284,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
              * point (i.e. the caller of the MPU_<API>). We need to restore it
              * when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+
             /* Store the value of the PSPLIM register before the SVC was raised.
              * We need to restore it when we exit from the system call. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
@@ -1300,6 +1303,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
             /* Start executing the system call upon returning from this handler. */
             pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
+
             /* Raise a request to exit from the system call upon finishing the
              * system call. */
             pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit;
@@ -1359,6 +1363,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
+
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __privileged_functions_start__;
@@ -1541,7 +1546,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
-        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+        #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
         {
             /* Check PACBTI security feature configuration before pushing the
              * CONTROL register's value on task's TCB. */
@@ -1582,6 +1587,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
+        #if ( configENABLE_PAC == 1 )
+        {
+            uint32_t ulTaskPacKey[ 4 ], i;
+
+            vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+            for( i = 0; i < 4; i++ )
+            {
+                xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ];
+                ulIndex++;
+            }
+        }
+        #endif /* configENABLE_PAC */
+
         return &( xMPUSettings->ulContext[ ulIndex ] );
     }
 
@@ -1664,6 +1683,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #endif /* portPRELOAD_REGISTERS */
 
+        #if ( configENABLE_PAC == 1 )
+        {
+            uint32_t ulTaskPacKey[ 4 ], i;
+
+            vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+            for( i = 0; i < 4; i++ )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = ulTaskPacKey[ i ];
+            }
+        }
+        #endif /* configENABLE_PAC */
+
         return pxTopOfStack;
     }
 
@@ -1786,11 +1819,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
-    #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+    #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
     {
         /* Set the CONTROL register value based on PACBTI security feature
          * configuration before starting the first task. */
-        ( void) prvConfigurePACBTI( pdTRUE );
+        ( void ) prvConfigurePACBTI( pdTRUE );
     }
     #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
@@ -1990,9 +2023,9 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
         if( xSchedulerRunning == pdFALSE )
         {
             /* Grant access to all the kernel objects before the scheduler
-            * is started. It is necessary because there is no task running
-            * yet and therefore, we cannot use the permissions of any
-            * task. */
+             * is started. It is necessary because there is no task running
+             * yet and therefore, we cannot use the permissions of any
+             * task. */
             xAccessGranted = pdTRUE;
         }
         else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
@@ -2213,7 +2246,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
 
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
     {
@@ -2225,13 +2258,13 @@ BaseType_t xPortIsInsideInterrupt( void )
         /* Enable UsageFault exception. */
         portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
 
-        #if( configENABLE_PAC == 1 )
+        #if ( configENABLE_PAC == 1 )
         {
             ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
         }
         #endif
 
-        #if( configENABLE_BTI == 1 )
+        #if ( configENABLE_BTI == 1 )
         {
             ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
         }
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h
index a7f9db767..e81b89228 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h
@@ -64,7 +64,7 @@
 
 #ifndef configENABLE_MVE
     #define configENABLE_MVE    0
-#elif( configENABLE_MVE != 0 )
+#elif ( configENABLE_MVE != 0 )
     #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M23.
 #endif
 /*-----------------------------------------------------------*/
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h
index a7f9db767..e81b89228 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h
@@ -64,7 +64,7 @@
 
 #ifndef configENABLE_MVE
     #define configENABLE_MVE    0
-#elif( configENABLE_MVE != 0 )
+#elif ( configENABLE_MVE != 0 )
     #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M23.
 #endif
 /*-----------------------------------------------------------*/
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c
index aaeccaa35..0ebbe48a4 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c
@@ -77,16 +77,16 @@
             "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
             "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
             "                                                 \n"
-            #if ( configTOTAL_MPU_REGIONS == 16 )
-                "    movs r3, #8                                  \n" /* r3 = 8. */
-                "    str r3, [r1]                                 \n" /* Program RNR = 8. */
-                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
-                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-                "    movs r3, #12                                 \n" /* r3 = 12. */
-                "    str r3, [r1]                                 \n" /* Program RNR = 12. */
-                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
-                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-            #endif /* configTOTAL_MPU_REGIONS == 16 */
+        #if ( configTOTAL_MPU_REGIONS == 16 )
+            "    movs r3, #8                                  \n" /* r3 = 8. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 8. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "    movs r3, #12                                 \n" /* r3 = 12. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 12. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+        #endif /* configTOTAL_MPU_REGIONS == 16 */
             "                                                 \n"
             "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
@@ -100,6 +100,14 @@
             "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
             "                                                 \n"
             " restore_special_regs_first_task:                \n"
+        #if ( configENABLE_PAC == 1 )
+            "   ldmdb r2!, {r3-r6}                            \n" /* Read task's dedicated PAC key from the task's context. */
+            "   msr  PAC_KEY_P_0, r3                          \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+            "   msr  PAC_KEY_P_1, r4                          \n"
+            "   msr  PAC_KEY_P_2, r5                          \n"
+            "   msr  PAC_KEY_P_3, r6                          \n"
+            "   clrm {r3-r6}                                  \n" /* Clear r3-r6. */
+        #endif /* configENABLE_PAC */
             "    ldmdb r2!, {r0, r3-r5, lr}                   \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
             "    msr psp, r3                                  \n"
             "    msr psplim, r4                               \n"
@@ -132,6 +140,15 @@
             "   ldr  r3, [r2]                                   \n" /* Read pxCurrentTCB. */
             "   ldr  r0, [r3]                                   \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
             "                                                   \n"
+        #if ( configENABLE_PAC == 1 )
+            "   ldmia r0!, {r1-r4}                              \n" /* Read task's dedicated PAC key from stack. */
+            "   msr  PAC_KEY_P_3, r1                            \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+            "   msr  PAC_KEY_P_2, r2                            \n"
+            "   msr  PAC_KEY_P_1, r3                            \n"
+            "   msr  PAC_KEY_P_0, r4                            \n"
+            "   clrm {r1-r4}                                    \n" /* Clear r1-r4. */
+        #endif /* configENABLE_PAC */
+            "                                                   \n"
             "   ldm  r0!, {r1-r3}                               \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
             "   ldr  r4, =xSecureContext                        \n"
             "   str  r1, [r4]                                   \n" /* Set xSecureContext to this task's value for the same. */
@@ -280,17 +297,15 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "                                                 \n"
             " save_general_regs:                              \n"
             "    mrs r3, psp                                  \n"
-            "                                                 \n"
-            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-                "    add r3, r3, #0x20                            \n" /* Move r3 to location where s0 is saved. */
-                "    tst lr, #0x10                                \n"
-                "    ittt eq                                      \n"
-                "    vstmiaeq r2!, {s16-s31}                      \n" /* Store s16-s31. */
-                "    vldmiaeq r3, {s0-s16}                        \n" /* Copy hardware saved FP context into s0-s16. */
-                "    vstmiaeq r2!, {s0-s16}                       \n" /* Store hardware saved FP context. */
-                "    sub r3, r3, #0x20                            \n" /* Set r3 back to the location of hardware saved context. */
-            #endif /* configENABLE_FPU || configENABLE_MVE */
-            "                                                 \n"
+        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            "    add r3, r3, #0x20                            \n" /* Move r3 to location where s0 is saved. */
+            "    tst lr, #0x10                                \n"
+            "    ittt eq                                      \n"
+            "    vstmiaeq r2!, {s16-s31}                      \n" /* Store s16-s31. */
+            "    vldmiaeq r3, {s0-s16}                        \n" /* Copy hardware saved FP context into s0-s16. */
+            "    vstmiaeq r2!, {s0-s16}                       \n" /* Store hardware saved FP context. */
+            "    sub r3, r3, #0x20                            \n" /* Set r3 back to the location of hardware saved context. */
+        #endif /* configENABLE_FPU || configENABLE_MVE */
             "    stmia r2!, {r4-r11}                          \n" /* Store r4-r11. */
             "    ldmia r3, {r4-r11}                           \n" /* Copy the hardware saved context into r4-r11. */
             "    stmia r2!, {r4-r11}                          \n" /* Store the hardware saved context. */
@@ -300,7 +315,15 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    mrs r4, psplim                               \n" /* r4 = PSPLIM. */
             "    mrs r5, control                              \n" /* r5 = CONTROL. */
             "    stmia r2!, {r0, r3-r5, lr}                   \n" /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
-            "    str r2, [r1]                                 \n" /* Save the location from where the context should be restored as the first member of TCB. */
+        #if ( configENABLE_PAC == 1 )
+            "   mrs  r3, PAC_KEY_P_0                          \n" /* Read task's dedicated PAC key from the PAC key registers. */
+            "   mrs  r4, PAC_KEY_P_1                          \n"
+            "   mrs  r5, PAC_KEY_P_2                          \n"
+            "   mrs  r6, PAC_KEY_P_3                          \n"
+            "   stmia r2!, {r3-r6}                            \n" /* Store the task's dedicated PAC key on the task's context. */
+            "   clrm {r3-r6}                                  \n" /* Clear r3-r6. */
+        #endif /* configENABLE_PAC */
+            "    str r2, [r1]                                 \n"      /* Save the location from where the context should be restored as the first member of TCB. */
             "                                                 \n"
             " select_next_task:                               \n"
             "    mov r0, %0                                   \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
@@ -335,16 +358,16 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
             "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
             "                                                 \n"
-            #if ( configTOTAL_MPU_REGIONS == 16 )
-                "    movs r3, #8                                  \n" /* r3 = 8. */
-                "    str r3, [r1]                                 \n" /* Program RNR = 8. */
-                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-                "    movs r3, #12                                 \n" /* r3 = 12. */
-                "    str r3, [r1]                                 \n" /* Program RNR = 12. */
-                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-            #endif /* configTOTAL_MPU_REGIONS == 16 */
+        #if ( configTOTAL_MPU_REGIONS == 16 )
+            "    movs r3, #8                                  \n" /* r3 = 8. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 8. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "    movs r3, #12                                 \n" /* r3 = 12. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 12. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+        #endif /* configTOTAL_MPU_REGIONS == 16 */
             "                                                 \n"
             "   ldr r1, =0xe000ed94                           \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
@@ -358,6 +381,14 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
             "                                                 \n"
             " restore_special_regs:                           \n"
+        #if ( configENABLE_PAC == 1 )
+            "   ldmdb r2!, {r3-r6}                            \n" /* Read task's dedicated PAC key from the task's context. */
+            "   msr  PAC_KEY_P_0, r3                          \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+            "   msr  PAC_KEY_P_1, r4                          \n"
+            "   msr  PAC_KEY_P_2, r5                          \n"
+            "   msr  PAC_KEY_P_3, r6                          \n"
+            "   clrm {r3-r6}                                  \n" /* Clear r3-r6. */
+        #endif /* configENABLE_PAC */
             "    ldmdb r2!, {r0, r3-r5, lr}                   \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
             "    msr psp, r3                                  \n"
             "    msr psplim, r4                               \n"
@@ -380,13 +411,13 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
             "    stmia r3!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
             "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 restored. */
-            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-                "    tst lr, #0x10                                \n"
-                "    ittt eq                                      \n"
-                "    vldmdbeq r2!, {s0-s16}                       \n" /* s0-s16 contain hardware saved FP context. */
-                "    vstmiaeq r3!, {s0-s16}                       \n" /* Copy hardware saved FP context on the task stack. */
-                "    vldmdbeq r2!, {s16-s31}                      \n" /* Restore s16-s31. */
-            #endif /* configENABLE_FPU || configENABLE_MVE */
+        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            "    tst lr, #0x10                                \n"
+            "    ittt eq                                      \n"
+            "    vldmdbeq r2!, {s0-s16}                       \n" /* s0-s16 contain hardware saved FP context. */
+            "    vstmiaeq r3!, {s0-s16}                       \n" /* Copy hardware saved FP context on the task stack. */
+            "    vldmdbeq r2!, {s16-s31}                      \n" /* Restore s16-s31. */
+        #endif /* configENABLE_FPU || configENABLE_MVE */
             "                                                 \n"
             " restore_context_done:                           \n"
             "    str r2, [r1]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
@@ -401,89 +432,99 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
     {
         __asm volatile
         (
-            "   .syntax unified                                 \n"
-            "   .extern SecureContext_SaveContext               \n"
-            "   .extern SecureContext_LoadContext               \n"
-            "                                                   \n"
-            "   ldr r3, =xSecureContext                         \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-            "   ldr r0, [r3]                                    \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
-            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
-            "   mrs r2, psp                                     \n" /* Read PSP in r2. */
-            "                                                   \n"
-            "   cbz r0, save_ns_context                         \n" /* No secure context to save. */
-            "   push {r0-r2, r14}                               \n"
-            "   bl SecureContext_SaveContext                    \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-            "   pop {r0-r3}                                     \n" /* LR is now in r3. */
-            "   mov lr, r3                                      \n" /* LR = r3. */
-            "   lsls r1, r3, #25                                \n" /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-            "   bpl save_ns_context                             \n" /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-            "                                                   \n"
-            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB.*/
-            "   subs r2, r2, #12                                \n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */
-            "   str r2, [r1]                                    \n" /* Save the new top of stack in TCB. */
-            "   mrs r1, psplim                                  \n" /* r1 = PSPLIM. */
-            "   mov r3, lr                                      \n" /* r3 = LR/EXC_RETURN. */
-            "   stmia r2!, {r0, r1, r3}                         \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
-            "   b select_next_task                              \n"
-            "                                                   \n"
-            " save_ns_context:                                  \n"
-            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
-            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-                "   tst lr, #0x10                               \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
-                "   it eq                                       \n"
-                "   vstmdbeq r2!, {s16-s31}                     \n" /* Store the additional FP context registers which are not saved automatically. */
-            #endif /* configENABLE_FPU || configENABLE_MVE */
-            "   subs r2, r2, #44                                \n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
-            "   str r2, [r1]                                    \n" /* Save the new top of stack in TCB. */
-            "   adds r2, r2, #12                                \n" /* r2 = r2 + 12. */
-            "   stm r2, {r4-r11}                                \n" /* Store the registers that are not saved automatically. */
-            "   mrs r1, psplim                                  \n" /* r1 = PSPLIM. */
-            "   mov r3, lr                                      \n" /* r3 = LR/EXC_RETURN. */
-            "   subs r2, r2, #12                                \n" /* r2 = r2 - 12. */
-            "   stmia r2!, {r0, r1, r3}                         \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
-            "                                                   \n"
-            " select_next_task:                                 \n"
-            "   mov r0, %0                                      \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
-            "   msr basepri, r0                                 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-            "   dsb                                             \n"
-            "   isb                                             \n"
-            "   bl vTaskSwitchContext                           \n"
-            "   mov r0, #0                                      \n" /* r0 = 0. */
-            "   msr basepri, r0                                 \n" /* Enable interrupts. */
-            "                                                   \n"
-            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
-            "   ldr r2, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
-            "                                                   \n"
-            "   ldmia r2!, {r0, r1, r4}                         \n" /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
-            "   msr psplim, r1                                  \n" /* Restore the PSPLIM register value for the task. */
-            "   mov lr, r4                                      \n" /* LR = r4. */
-            "   ldr r3, =xSecureContext                         \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-            "   str r0, [r3]                                    \n" /* Restore the task's xSecureContext. */
-            "   cbz r0, restore_ns_context                      \n" /* If there is no secure context for the task, restore the non-secure context. */
-            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
-            "   push {r2, r4}                                   \n"
-            "   bl SecureContext_LoadContext                    \n" /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-            "   pop {r2, r4}                                    \n"
-            "   mov lr, r4                                      \n" /* LR = r4. */
-            "   lsls r1, r4, #25                                \n" /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-            "   bpl restore_ns_context                          \n" /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-            "   msr psp, r2                                     \n" /* Remember the new top of stack for the task. */
-            "   bx lr                                           \n"
-            "                                                   \n"
-            " restore_ns_context:                               \n"
-            "   ldmia r2!, {r4-r11}                             \n" /* Restore the registers that are not automatically restored. */
-            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-                "   tst lr, #0x10                               \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
-                "   it eq                                       \n"
-                "   vldmiaeq r2!, {s16-s31}                     \n" /* Restore the additional FP context registers which are not restored automatically. */
-            #endif /* configENABLE_FPU || configENABLE_MVE */
-            "   msr psp, r2                                     \n" /* Remember the new top of stack for the task. */
-            "   bx lr                                           \n"
+            " .syntax unified                                 \n"
+            " .extern SecureContext_SaveContext               \n"
+            " .extern SecureContext_LoadContext               \n"
+            "                                                 \n"
+            " ldr r3, =xSecureContext                         \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            " ldr r0, [r3]                                    \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+            " ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            " ldr r1, [r3]                                    \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
+            " mrs r2, psp                                     \n" /* Read PSP in r2. */
+            "                                                 \n"
+            " cbz r0, save_ns_context                         \n" /* No secure context to save. */
+            " save_s_context:                                 \n"
+            "    push {r0-r2, lr}                             \n"
+            "    bl SecureContext_SaveContext                 \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+            "    pop {r0-r2, lr}                              \n"
+            "                                                 \n"
+            " save_ns_context:                                \n"
+            "    mov r3, lr                                   \n" /* r3 = LR (EXC_RETURN). */
+            "    lsls r3, r3, #25                             \n" /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+            "    bmi save_special_regs                        \n" /* If r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used. */
+            "                                                 \n"
+            " save_general_regs:                              \n"
+        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            "    tst lr, #0x10                                \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+            "    it eq                                        \n"
+            "    vstmdbeq r2!, {s16-s31}                      \n" /* Store the additional FP context registers which are not saved automatically. */
+        #endif /* configENABLE_FPU || configENABLE_MVE */
+            "   stmdb r2!, {r4-r11}                           \n" /* Store the registers that are not saved automatically. */
+            "                                                 \n"
+            " save_special_regs:                              \n"
+            "    mrs r3, psplim                               \n" /* r3 = PSPLIM. */
+            "    stmdb r2!, {r0, r3, lr}                      \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
+        #if ( configENABLE_PAC == 1 )
+            "    mrs  r3, PAC_KEY_P_3                         \n" /* Read task's dedicated PAC key from the PAC key registers. */
+            "    mrs  r4, PAC_KEY_P_2                         \n"
+            "    mrs  r5, PAC_KEY_P_1                         \n"
+            "    mrs  r6, PAC_KEY_P_0                         \n"
+            "    stmdb r2!, {r3-r6}                           \n" /* Store the task's dedicated PAC key on the stack. */
+            "    clrm {r3-r6}                                 \n" /* Clear r3-r6. */
+        #endif /* configENABLE_PAC */
+            "                                                 \n"
+            " str r2, [r1]                                    \n" /* Save the new top of stack in TCB. */
+            "                                                 \n"
+            " select_next_task:                               \n"
+            "    mov r0, %0                                   \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
+            "    msr basepri, r0                              \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+            "    dsb                                          \n"
+            "    isb                                          \n"
+            "    bl vTaskSwitchContext                        \n"
+            "    mov r0, #0                                   \n" /* r0 = 0. */
+            "    msr basepri, r0                              \n" /* Enable interrupts. */
+            "                                                 \n"
+            " restore_context:                                \n"
+            "    ldr r3, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r1, [r3]                                 \n" /* Read pxCurrentTCB. */
+            "    ldr r2, [r1]                                 \n" /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
+            "                                                 \n"
+            " restore_special_regs:                           \n"
+        #if ( configENABLE_PAC == 1 )
+            "    ldmia r2!, {r3-r6}                           \n" /* Read task's dedicated PAC key from stack. */
+            "    msr  PAC_KEY_P_3, r3                         \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+            "    msr  PAC_KEY_P_2, r4                         \n"
+            "    msr  PAC_KEY_P_1, r5                         \n"
+            "    msr  PAC_KEY_P_0, r6                         \n"
+            "    clrm {r3-r6}                                 \n" /* Clear r3-r6. */
+        #endif /* configENABLE_PAC */
+            "    ldmia r2!, {r0, r3, lr}                      \n" /* Read from stack - r0 = xSecureContext, r3 = PSPLIM and LR restored. */
+            "    msr psplim, r3                               \n" /* Restore the PSPLIM register value for the task. */
+            "    ldr r3, =xSecureContext                      \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "    str r0, [r3]                                 \n" /* Restore the task's xSecureContext. */
+            "    cbz r0, restore_ns_context                   \n" /* If there is no secure context for the task, restore the non-secure context. */
+            "                                                 \n"
+            " restore_s_context:                              \n"
+            "    push {r1-r3, lr}                             \n"
+            "    bl SecureContext_LoadContext                 \n" /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+            "    pop {r1-r3, lr}                              \n"
+            "                                                 \n"
+            " restore_ns_context:                             \n"
+            "    mov r0, lr                                   \n" /* r0 = LR (EXC_RETURN). */
+            "    lsls r0, r0, #25                             \n" /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+            "    bmi restore_context_done                     \n" /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
+            "                                                 \n"
+            " restore_general_regs:                           \n"
+            "    ldmia r2!, {r4-r11}                          \n" /* Restore the registers that are not automatically restored. */
+        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            "   tst lr, #0x10                                 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+            "   it eq                                         \n"
+            "   vldmiaeq r2!, {s16-s31}                       \n" /* Restore the additional FP context registers which are not restored automatically. */
+        #endif /* configENABLE_FPU || configENABLE_MVE */
+            "                                                 \n"
+            " restore_context_done:                           \n"
+            "    msr psp, r2                                  \n" /* Remember the new top of stack for the task. */
+            "    bx lr                                        \n"
             ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
         );
     }
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h
index 0fc61f23c..2d435ca0b 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h
@@ -60,7 +60,7 @@
 
 #ifndef configENABLE_MVE
     #define configENABLE_MVE    0
-#elif( configENABLE_MVE != 0 )
+#elif ( configENABLE_MVE != 0 )
     #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M33.
 #endif
 /*-----------------------------------------------------------*/
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c
index 7cdff7005..bc7bb6071 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c
@@ -77,16 +77,16 @@
             "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
             "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
             "                                                 \n"
-            #if ( configTOTAL_MPU_REGIONS == 16 )
-                "    movs r3, #8                                  \n" /* r3 = 8. */
-                "    str r3, [r1]                                 \n" /* Program RNR = 8. */
-                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-                "    movs r3, #12                                 \n" /* r3 = 12. */
-                "    str r3, [r1]                                 \n" /* Program RNR = 12. */
-                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-            #endif /* configTOTAL_MPU_REGIONS == 16 */
+        #if ( configTOTAL_MPU_REGIONS == 16 )
+            "    movs r3, #8                                  \n" /* r3 = 8. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 8. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "    movs r3, #12                                 \n" /* r3 = 12. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 12. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+        #endif /* configTOTAL_MPU_REGIONS == 16 */
             "                                                 \n"
             "   ldr r1, =0xe000ed94                           \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
@@ -100,6 +100,14 @@
             "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
             "                                                 \n"
             " restore_special_regs_first_task:                \n"
+        #if ( configENABLE_PAC == 1 )
+            "   ldmdb r1!, {r2-r5}                            \n" /* Read task's dedicated PAC key from the task's context. */
+            "   msr  PAC_KEY_P_0, r2                          \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+            "   msr  PAC_KEY_P_1, r3                          \n"
+            "   msr  PAC_KEY_P_2, r4                          \n"
+            "   msr  PAC_KEY_P_3, r5                          \n"
+            "   clrm {r2-r5}                                  \n" /* Clear r2-r5. */
+        #endif /* configENABLE_PAC */
             "    ldmdb r1!, {r2-r4, lr}                       \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
             "    msr psp, r2                                  \n"
             "    msr psplim, r3                               \n"
@@ -130,6 +138,15 @@
             "   ldr  r1, [r2]                                   \n" /* Read pxCurrentTCB. */
             "   ldr  r0, [r1]                                   \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
             "                                                   \n"
+        #if ( configENABLE_PAC == 1 )
+            "   ldmia r0!, {r1-r4}                              \n" /* Read task's dedicated PAC key from stack. */
+            "   msr  PAC_KEY_P_3, r1                            \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+            "   msr  PAC_KEY_P_2, r2                            \n"
+            "   msr  PAC_KEY_P_1, r3                            \n"
+            "   msr  PAC_KEY_P_0, r4                            \n"
+            "   clrm {r1-r4}                                    \n" /* Clear r1-r4. */
+        #endif /* configENABLE_PAC */
+            "                                                   \n"
             "   ldm  r0!, {r1-r2}                               \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
             "   msr  psplim, r1                                 \n" /* Set this task's PSPLIM value. */
             "   mrs  r1, control                                \n" /* Obtain current control register value. */
@@ -261,16 +278,15 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             " mrs r2, psp                                     \n" /* r2 = PSP. */
             "                                                 \n"
             " save_general_regs:                              \n"
-            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-                "    add r2, r2, #0x20                            \n" /* Move r2 to location where s0 is saved. */
-                "    tst lr, #0x10                                \n"
-                "    ittt eq                                      \n"
-                "    vstmiaeq r1!, {s16-s31}                      \n" /* Store s16-s31. */
-                "    vldmiaeq r2, {s0-s16}                        \n" /* Copy hardware saved FP context into s0-s16. */
-                "    vstmiaeq r1!, {s0-s16}                       \n" /* Store hardware saved FP context. */
-                "    sub r2, r2, #0x20                            \n" /* Set r2 back to the location of hardware saved context. */
-            #endif /* configENABLE_FPU || configENABLE_MVE */
-            "                                                 \n"
+        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            "    add r2, r2, #0x20                            \n" /* Move r2 to location where s0 is saved. */
+            "    tst lr, #0x10                                \n"
+            "    ittt eq                                      \n"
+            "    vstmiaeq r1!, {s16-s31}                      \n" /* Store s16-s31. */
+            "    vldmiaeq r2, {s0-s16}                        \n" /* Copy hardware saved FP context into s0-s16. */
+            "    vstmiaeq r1!, {s0-s16}                       \n" /* Store hardware saved FP context. */
+            "    sub r2, r2, #0x20                            \n" /* Set r2 back to the location of hardware saved context. */
+        #endif /* configENABLE_FPU || configENABLE_MVE */
             "    stmia r1!, {r4-r11}                          \n" /* Store r4-r11. */
             "    ldmia r2, {r4-r11}                           \n" /* Copy the hardware saved context into r4-r11. */
             "    stmia r1!, {r4-r11}                          \n" /* Store the hardware saved context. */
@@ -279,6 +295,14 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    mrs r3, psplim                               \n" /* r3 = PSPLIM. */
             "    mrs r4, control                              \n" /* r4 = CONTROL. */
             "    stmia r1!, {r2-r4, lr}                       \n" /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
+        #if ( configENABLE_PAC == 1 )
+            "   mrs  r2, PAC_KEY_P_0                          \n" /* Read task's dedicated PAC key from the PAC key registers. */
+            "   mrs  r3, PAC_KEY_P_1                          \n"
+            "   mrs  r4, PAC_KEY_P_2                          \n"
+            "   mrs  r5, PAC_KEY_P_3                          \n"
+            "   stmia r1!, {r2-r5}                            \n" /* Store the task's dedicated PAC key on the task's context. */
+            "   clrm {r2-r5}                                  \n" /* Clear r2-r5. */
+        #endif /* configENABLE_PAC */
             "    str r1, [r0]                                 \n" /* Save the location from where the context should be restored as the first member of TCB. */
             "                                                 \n"
             " select_next_task:                               \n"
@@ -314,16 +338,16 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
             "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
             "                                                 \n"
-            #if ( configTOTAL_MPU_REGIONS == 16 )
-                "    movs r3, #8                                  \n" /* r3 = 8. */
-                "    str r3, [r1]                                 \n" /* Program RNR = 8. */
-                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-                "    movs r3, #12                                 \n" /* r3 = 12. */
-                "    str r3, [r1]                                 \n" /* Program RNR = 12. */
-                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-            #endif /* configTOTAL_MPU_REGIONS == 16 */
+        #if ( configTOTAL_MPU_REGIONS == 16 )
+            "    movs r3, #8                                  \n" /* r3 = 8. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 8. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "    movs r3, #12                                 \n" /* r3 = 12. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 12. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+        #endif /* configTOTAL_MPU_REGIONS == 16 */
             "                                                 \n"
             "   ldr r1, =0xe000ed94                           \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
@@ -337,6 +361,14 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
             "                                                 \n"
             " restore_special_regs:                           \n"
+        #if ( configENABLE_PAC == 1 )
+            "   ldmdb r1!, {r2-r5}                            \n" /* Read task's dedicated PAC key from the task's context. */
+            "   msr  PAC_KEY_P_0, r2                          \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+            "   msr  PAC_KEY_P_1, r3                          \n"
+            "   msr  PAC_KEY_P_2, r4                          \n"
+            "   msr  PAC_KEY_P_3, r5                          \n"
+            "   clrm {r2-r5}                                  \n" /* Clear r2-r5. */
+        #endif /* configENABLE_PAC */
             "    ldmdb r1!, {r2-r4, lr}                       \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
             "    msr psp, r2                                  \n"
             "    msr psplim, r3                               \n"
@@ -346,13 +378,13 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
             "    stmia r2!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
             "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 restored. */
-            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-                "    tst lr, #0x10                                \n"
-                "    ittt eq                                      \n"
-                "    vldmdbeq r1!, {s0-s16}                       \n" /* s0-s16 contain hardware saved FP context. */
-                "    vstmiaeq r2!, {s0-s16}                       \n" /* Copy hardware saved FP context on the task stack. */
-                "    vldmdbeq r1!, {s16-s31}                      \n" /* Restore s16-s31. */
-            #endif /* configENABLE_FPU || configENABLE_MVE */
+        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            "    tst lr, #0x10                                \n"
+            "    ittt eq                                      \n"
+            "    vldmdbeq r1!, {s0-s16}                       \n" /* s0-s16 contain hardware saved FP context. */
+            "    vstmiaeq r2!, {s0-s16}                       \n" /* Copy hardware saved FP context on the task stack. */
+            "    vldmdbeq r1!, {s16-s31}                      \n" /* Restore s16-s31. */
+        #endif /* configENABLE_FPU || configENABLE_MVE */
             "                                                 \n"
             " restore_context_done:                           \n"
             "    str r1, [r0]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
@@ -371,16 +403,25 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "                                                   \n"
             "   mrs r0, psp                                     \n" /* Read PSP in r0. */
             "                                                   \n"
-            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-                "   tst lr, #0x10                                   \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
-                "   it eq                                           \n"
-                "   vstmdbeq r0!, {s16-s31}                         \n" /* Store the additional FP context registers which are not saved automatically. */
-            #endif /* configENABLE_FPU || configENABLE_MVE */
+        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            "   tst lr, #0x10                                   \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+            "   it eq                                           \n"
+            "   vstmdbeq r0!, {s16-s31}                         \n" /* Store the additional FP context registers which are not saved automatically. */
+        #endif /* configENABLE_FPU || configENABLE_MVE */
             "                                                   \n"
             "   mrs r2, psplim                                  \n" /* r2 = PSPLIM. */
             "   mov r3, lr                                      \n" /* r3 = LR/EXC_RETURN. */
             "   stmdb r0!, {r2-r11}                             \n" /* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */
             "                                                   \n"
+        #if ( configENABLE_PAC == 1 )
+            "   mrs  r1, PAC_KEY_P_3                            \n" /* Read task's dedicated PAC key from the PAC key registers. */
+            "   mrs  r2, PAC_KEY_P_2                            \n"
+            "   mrs  r3, PAC_KEY_P_1                            \n"
+            "   mrs  r4, PAC_KEY_P_0                            \n"
+            "   stmdb r0!, {r1-r4}                              \n" /* Store the task's dedicated PAC key on the stack. */
+            "   clrm {r1-r4}                                    \n" /* Clear r1-r4. */
+        #endif /* configENABLE_PAC */
+            "                                                   \n"
             "   ldr r2, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr r1, [r2]                                    \n" /* Read pxCurrentTCB. */
             "   str r0, [r1]                                    \n" /* Save the new top of stack in TCB. */
@@ -397,13 +438,22 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   ldr r1, [r2]                                    \n" /* Read pxCurrentTCB. */
             "   ldr r0, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
             "                                                   \n"
+        #if ( configENABLE_PAC == 1 )
+            "   ldmia r0!, {r2-r5}                              \n" /* Read task's dedicated PAC key from stack. */
+            "   msr  PAC_KEY_P_3, r2                            \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+            "   msr  PAC_KEY_P_2, r3                            \n"
+            "   msr  PAC_KEY_P_1, r4                            \n"
+            "   msr  PAC_KEY_P_0, r5                            \n"
+            "   clrm {r2-r5}                                    \n" /* Clear r2-r5. */
+        #endif /* configENABLE_PAC */
+            "                                                   \n"
             "   ldmia r0!, {r2-r11}                             \n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
             "                                                   \n"
-            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-                "   tst r3, #0x10                                   \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
-                "   it eq                                           \n"
-                "   vldmiaeq r0!, {s16-s31}                         \n" /* Restore the additional FP context registers which are not restored automatically. */
-            #endif /* configENABLE_FPU || configENABLE_MVE */
+        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            "   tst r3, #0x10                                   \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+            "   it eq                                           \n"
+            "   vldmiaeq r0!, {s16-s31}                         \n" /* Restore the additional FP context registers which are not restored automatically. */
+        #endif /* configENABLE_FPU || configENABLE_MVE */
             "                                                   \n"
             "   msr psplim, r2                                  \n" /* Restore the PSPLIM register value for the task. */
             "   msr psp, r0                                     \n" /* Remember the new top of stack for the task. */
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h
index 0fc61f23c..2d435ca0b 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h
@@ -60,7 +60,7 @@
 
 #ifndef configENABLE_MVE
     #define configENABLE_MVE    0
-#elif( configENABLE_MVE != 0 )
+#elif ( configENABLE_MVE != 0 )
     #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M33.
 #endif
 /*-----------------------------------------------------------*/
diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM35P/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM35P/portmacro.h
index 4db6e6d4a..b886287ac 100644
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM35P/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM35P/portmacro.h
@@ -60,7 +60,7 @@
 
 #ifndef configENABLE_MVE
     #define configENABLE_MVE    0
-#elif( configENABLE_MVE != 0 )
+#elif ( configENABLE_MVE != 0 )
     #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M35.
 #endif
 /*-----------------------------------------------------------*/
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h
index 9dfcc9132..9d6c3368e 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h
@@ -64,7 +64,7 @@
 
 #ifndef configENABLE_MVE
     #define configENABLE_MVE    0
-#elif( configENABLE_MVE != 0 )
+#elif ( configENABLE_MVE != 0 )
     #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M23.
 #endif
 /*-----------------------------------------------------------*/
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h
index 9dfcc9132..9d6c3368e 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h
@@ -64,7 +64,7 @@
 
 #ifndef configENABLE_MVE
     #define configENABLE_MVE    0
-#elif( configENABLE_MVE != 0 )
+#elif ( configENABLE_MVE != 0 )
     #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M23.
 #endif
 /*-----------------------------------------------------------*/
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s
index 212688d61..8d5988819 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s
@@ -152,6 +152,14 @@ vRestoreContextOfFirstTask:
         ldr r2, [r1]                        /* r2 = Location of saved context in TCB. */
 
     restore_special_regs_first_task:
+    #if ( configENABLE_PAC == 1 )
+        ldmdb r2!, {r3-r6}                  /* Read task's dedicated PAC key from the task's context. */
+        msr  PAC_KEY_P_0, r3                /* Write the task's dedicated PAC key to the PAC key registers. */
+        msr  PAC_KEY_P_1, r4
+        msr  PAC_KEY_P_2, r5
+        msr  PAC_KEY_P_3, r6
+        clrm {r3-r6}                        /* Clear r3-r6. */
+    #endif /* configENABLE_PAC */
         ldmdb r2!, {r0, r3-r5, lr}          /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
         msr psp, r3
         msr psplim, r4
@@ -177,6 +185,15 @@ vRestoreContextOfFirstTask:
     ldr  r3, [r2]                           /* Read pxCurrentTCB. */
     ldr  r0, [r3]                           /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
 
+#if ( configENABLE_PAC == 1 )
+    ldmia r0!, {r1-r4}                      /* Read task's dedicated PAC key from stack. */
+    msr  PAC_KEY_P_3, r1                    /* Write the task's dedicated PAC key to the PAC key registers. */
+    msr  PAC_KEY_P_2, r2
+    msr  PAC_KEY_P_1, r3
+    msr  PAC_KEY_P_0, r4
+    clrm {r1-r4}                            /* Clear r1-r4.  */
+#endif /* configENABLE_PAC */
+
     ldm  r0!, {r1-r3}                       /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
     ldr  r4, =xSecureContext
     str  r1, [r4]                           /* Set xSecureContext to this task's value for the same. */
@@ -271,7 +288,16 @@ PendSV_Handler:
         mrs r4, psplim                      /* r4 = PSPLIM. */
         mrs r5, control                     /* r5 = CONTROL. */
         stmia r2!, {r0, r3-r5, lr}          /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
-        str r2, [r1]                        /* Save the location from where the context should be restored as the first member of TCB. */
+    #if ( configENABLE_PAC == 1 )
+        mrs  r3, PAC_KEY_P_0                /* Read task's dedicated PAC key from the PAC key registers. */
+        mrs  r4, PAC_KEY_P_1
+        mrs  r5, PAC_KEY_P_2
+        mrs  r6, PAC_KEY_P_3
+        stmia r2!, {r3-r6}                  /* Store the task's dedicated PAC key on the task's context. */
+        clrm {r3-r6}                        /* Clear r3-r6. */
+    #endif /* configENABLE_PAC */
+
+    str r2, [r1]                            /* Save the location from where the context should be restored as the first member of TCB. */
 
     select_next_task:
         mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
@@ -329,6 +355,14 @@ PendSV_Handler:
         ldr r2, [r1]                        /* r2 = Location of saved context in TCB. */
 
     restore_special_regs:
+    #if ( configENABLE_PAC == 1 )
+        ldmdb r2!, {r3-r6}                  /* Read task's dedicated PAC key from the task's context. */
+        msr  PAC_KEY_P_0, r3                /* Write the task's dedicated PAC key to the PAC key registers. */
+        msr  PAC_KEY_P_1, r4
+        msr  PAC_KEY_P_2, r5
+        msr  PAC_KEY_P_3, r6
+        clrm {r3-r6}                        /* Clear r3-r6. */
+    #endif /* configENABLE_PAC */
         ldmdb r2!, {r0, r3-r5, lr}          /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
         msr psp, r3
         msr psplim, r4
@@ -374,38 +408,37 @@ PendSV_Handler:
     mrs r2, psp                             /* Read PSP in r2. */
 
     cbz r0, save_ns_context                 /* No secure context to save. */
-    push {r0-r2, r14}
-    bl SecureContext_SaveContext            /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-    pop {r0-r3}                             /* LR is now in r3. */
-    mov lr, r3                              /* LR = r3. */
-    lsls r1, r3, #25                        /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-    bpl save_ns_context                     /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-
-    ldr r3, =pxCurrentTCB                   /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-    ldr r1, [r3]                            /* Read pxCurrentTCB. */
-    subs r2, r2, #12                        /* Make space for xSecureContext, PSPLIM and LR on the stack. */
-    str r2, [r1]                            /* Save the new top of stack in TCB. */
-    mrs r1, psplim                          /* r1 = PSPLIM. */
-    mov r3, lr                              /* r3 = LR/EXC_RETURN. */
-    stmia r2!, {r0, r1, r3}                 /* Store xSecureContext, PSPLIM and LR on the stack. */
-    b select_next_task
+    save_s_context:
+        push {r0-r2, lr}
+        bl SecureContext_SaveContext       /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+        pop {r0-r2, lr}
 
     save_ns_context:
-        ldr r3, =pxCurrentTCB               /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        ldr r1, [r3]                        /* Read pxCurrentTCB. */
+        mov r3, lr                          /* r3 = LR. */
+        lsls r3, r3, #25                    /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+        bmi save_special_regs               /* If r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used. */
+
+    save_general_regs:
     #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
         tst lr, #0x10                       /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
         it eq
         vstmdbeq r2!, {s16-s31}             /* Store the additional FP context registers which are not saved automatically. */
     #endif /* configENABLE_FPU || configENABLE_MVE */
-        subs r2, r2, #44                    /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
-        str r2, [r1]                        /* Save the new top of stack in TCB. */
-        adds r2, r2, #12                    /* r2 = r2 + 12. */
-        stm r2, {r4-r11}                    /* Store the registers that are not saved automatically. */
-        mrs r1, psplim                      /* r1 = PSPLIM. */
-        mov r3, lr                          /* r3 = LR/EXC_RETURN. */
-        subs r2, r2, #12                    /* r2 = r2 - 12. */
-        stmia r2!, {r0, r1, r3}             /* Store xSecureContext, PSPLIM and LR on the stack. */
+        stmdb r2!, {r4-r11}                 /* Store the registers that are not saved automatically. */
+
+    save_special_regs:
+        mrs r3, psplim                      /* r3 = PSPLIM. */
+        stmdb r2!, {r0, r3, lr}             /* Store xSecureContext, PSPLIM and LR on the stack. */
+    #if ( configENABLE_PAC == 1 )
+        mrs  r3, PAC_KEY_P_3                /* Read task's dedicated PAC key from the PAC key registers. */
+        mrs  r4, PAC_KEY_P_2
+        mrs  r5, PAC_KEY_P_1
+        mrs  r6, PAC_KEY_P_0
+        stmdb r2!, {r3-r6}                  /* Store the task's dedicated PAC key on the stack. */
+        clrm {r3-r6}                        /* Clear r3-r6. */
+    #endif /* configENABLE_PAC */
+
+    str r2, [r1]                            /* Save the new top of stack in TCB. */
 
     select_next_task:
         mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
@@ -416,34 +449,45 @@ PendSV_Handler:
         mov r0, #0                          /* r0 = 0. */
         msr basepri, r0                     /* Enable interrupts. */
 
+    restore_context:
         ldr r3, =pxCurrentTCB               /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
         ldr r1, [r3]                        /* Read pxCurrentTCB. */
         ldr r2, [r1]                        /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
 
-        ldmia r2!, {r0, r1, r4}             /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
-        msr psplim, r1                      /* Restore the PSPLIM register value for the task. */
-        mov lr, r4                          /* LR = r4. */
+    restore_special_regs:
+    #if ( configENABLE_PAC == 1 )
+        ldmia r2!, {r3-r6}                  /* Read task's dedicated PAC key from stack. */
+        msr  PAC_KEY_P_3, r3                /* Write the task's dedicated PAC key to the PAC key registers. */
+        msr  PAC_KEY_P_2, r4
+        msr  PAC_KEY_P_1, r5
+        msr  PAC_KEY_P_0, r6
+        clrm {r3-r6}                        /* Clear r3-r6. */
+    #endif /* configENABLE_PAC */
+        ldmia r2!, {r0, r3, lr}             http://files.iar.com/ftp/pub/box/bxarm-9.60.3.deb/* Read from stack - r0 = xSecureContext, r3 = PSPLIM and LR restored. */
+        msr psplim, r3                      /* Restore the PSPLIM register value for the task. */
         ldr r3, =xSecureContext             /* Read the location of xSecureContext i.e. &( xSecureContext ). */
         str r0, [r3]                        /* Restore the task's xSecureContext. */
         cbz r0, restore_ns_context          /* If there is no secure context for the task, restore the non-secure context. */
-        ldr r3, =pxCurrentTCB               /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        ldr r1, [r3]                        /* Read pxCurrentTCB. */
-        push {r2, r4}
+
+    restore_s_context:
+        push {r1-r3, lr}
         bl SecureContext_LoadContext        /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-        pop {r2, r4}
-        mov lr, r4                          /* LR = r4. */
-        lsls r1, r4, #25                    /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-        bpl restore_ns_context              /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-        msr psp, r2                         /* Remember the new top of stack for the task. */
-        bx lr
+        pop {r1-r3, lr}
 
     restore_ns_context:
+        mov r0, lr                          /* r0 = LR (EXC_RETURN). */
+        lsls r0, r0, #25                    /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+        bmi restore_context_done            /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
+
+    restore_general_regs:
         ldmia r2!, {r4-r11}                 /* Restore the registers that are not automatically restored. */
     #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
         tst lr, #0x10                       /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
         it eq
         vldmiaeq r2!, {s16-s31}             /* Restore the additional FP context registers which are not restored automatically. */
     #endif /* configENABLE_FPU || configENABLE_MVE */
+
+    restore_context_done:
         msr psp, r2                         /* Remember the new top of stack for the task. */
         bx lr
 
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h
index 0f7d100df..53b668b5b 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h
@@ -60,7 +60,7 @@
 
 #ifndef configENABLE_MVE
     #define configENABLE_MVE    0
-#elif( configENABLE_MVE != 0 )
+#elif ( configENABLE_MVE != 0 )
     #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M33.
 #endif
 /*-----------------------------------------------------------*/
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s
index 9d6c6a7ef..ba6e8e915 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s
@@ -142,6 +142,14 @@ vRestoreContextOfFirstTask:
         ldr r1, [r0]                        /* r1 = Location of saved context in TCB. */
 
     restore_special_regs_first_task:
+    #if ( configENABLE_PAC == 1 )
+        ldmdb r1!, {r2-r5}                  /* Read task's dedicated PAC key from the task's context. */
+        msr  PAC_KEY_P_0, r2                /* Write the task's dedicated PAC key to the PAC key registers. */
+        msr  PAC_KEY_P_1, r3
+        msr  PAC_KEY_P_2, r4
+        msr  PAC_KEY_P_3, r5
+        clrm {r2-r5}                        /* Clear r2-r5. */
+    #endif /* configENABLE_PAC */
         ldmdb r1!, {r2-r4, lr}              /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
         msr psp, r2
         msr psplim, r3
@@ -165,6 +173,15 @@ vRestoreContextOfFirstTask:
     ldr  r1, [r2]                           /* Read pxCurrentTCB. */
     ldr  r0, [r1]                           /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
 
+#if ( configENABLE_PAC == 1 )
+    ldmia r0!, {r1-r4}                      /* Read task's dedicated PAC key from stack. */
+    msr  PAC_KEY_P_3, r1                    /* Write the task's dedicated PAC key to the PAC key registers. */
+    msr  PAC_KEY_P_2, r2
+    msr  PAC_KEY_P_1, r3
+    msr  PAC_KEY_P_0, r4
+    clrm {r1-r4}                            /* Clear r1-r4. */
+#endif /* configENABLE_PAC */
+
     ldm  r0!, {r1-r2}                       /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
     msr  psplim, r1                         /* Set this task's PSPLIM value. */
     mrs  r1, control                        /* Obtain current control register value. */
@@ -233,7 +250,6 @@ PendSV_Handler:
         vstmiaeq r1!, {s0-s16}              /* Store hardware saved FP context. */
         sub r2, r2, #0x20                   /* Set r2 back to the location of hardware saved context. */
     #endif /* configENABLE_FPU || configENABLE_MVE */
-
         stmia r1!, {r4-r11}                 /* Store r4-r11. */
         ldmia r2, {r4-r11}                  /* Copy the hardware saved context into r4-r11. */
         stmia r1!, {r4-r11}                 /* Store the hardware saved context. */
@@ -242,6 +258,15 @@ PendSV_Handler:
         mrs r3, psplim                      /* r3 = PSPLIM. */
         mrs r4, control                     /* r4 = CONTROL. */
         stmia r1!, {r2-r4, lr}              /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
+    #if ( configENABLE_PAC == 1 )
+        mrs  r2, PAC_KEY_P_0                /* Read task's dedicated PAC key from the PAC key registers. */
+        mrs  r3, PAC_KEY_P_1
+        mrs  r4, PAC_KEY_P_2
+        mrs  r5, PAC_KEY_P_3
+        stmia r1!, {r2-r5}                  /* Store the task's dedicated PAC key on the task's context. */
+        clrm {r2-r5}                        /* Clear r2-r5. */
+    #endif /* configENABLE_PAC */
+
         str r1, [r0]                        /* Save the location from where the context should be restored as the first member of TCB. */
 
     select_next_task:
@@ -300,6 +325,14 @@ PendSV_Handler:
         ldr r1, [r0]                        /* r1 = Location of saved context in TCB. */
 
     restore_special_regs:
+    #if ( configENABLE_PAC == 1 )
+        ldmdb r1!, {r2-r5}                  /* Read task's dedicated PAC key from the task's context. */
+        msr  PAC_KEY_P_0, r2                /* Write the task's dedicated PAC key to the PAC key registers. */
+        msr  PAC_KEY_P_1, r3
+        msr  PAC_KEY_P_2, r4
+        msr  PAC_KEY_P_3, r5
+        clrm {r2-r5}                        /* Clear r2-r5. */
+    #endif /* configENABLE_PAC */
         ldmdb r1!, {r2-r4, lr}              /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
         msr psp, r2
         msr psplim, r3
@@ -335,6 +368,15 @@ PendSV_Handler:
     mov r3, lr                              /* r3 = LR/EXC_RETURN. */
     stmdb r0!, {r2-r11}                     /* Store on the stack - PSPLIM, LR and registers that are not automatically. */
 
+#if ( configENABLE_PAC == 1 )
+    mrs  r1, PAC_KEY_P_3                    /* Read task's dedicated PAC key from the PAC key registers. */
+    mrs  r2, PAC_KEY_P_2
+    mrs  r3, PAC_KEY_P_1
+    mrs  r4, PAC_KEY_P_0
+    stmdb r0!, {r1-r4}                      /* Store the task's dedicated PAC key on the stack. */
+    clrm {r1-r4}                            /* Clear r1-r4. */
+#endif /* configENABLE_PAC */
+
     ldr r2, =pxCurrentTCB                   /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
     ldr r1, [r2]                            /* Read pxCurrentTCB. */
     str r0, [r1]                            /* Save the new top of stack in TCB. */
@@ -351,6 +393,15 @@ PendSV_Handler:
     ldr r1, [r2]                            /* Read pxCurrentTCB. */
     ldr r0, [r1]                            /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
 
+#if ( configENABLE_PAC == 1 )
+    ldmia r0!, {r2-r5}                      /* Read task's dedicated PAC key from stack. */
+    msr  PAC_KEY_P_3, r2                    /* Write the task's dedicated PAC key to the PAC key registers. */
+    msr  PAC_KEY_P_2, r3
+    msr  PAC_KEY_P_1, r4
+    msr  PAC_KEY_P_0, r5
+    clrm {r2-r5}                            /* Clear r2-r5. */
+#endif /* configENABLE_PAC */
+
     ldmia r0!, {r2-r11}                     /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
 
 #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h
index 0f7d100df..53b668b5b 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h
@@ -60,7 +60,7 @@
 
 #ifndef configENABLE_MVE
     #define configENABLE_MVE    0
-#elif( configENABLE_MVE != 0 )
+#elif ( configENABLE_MVE != 0 )
     #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M33.
 #endif
 /*-----------------------------------------------------------*/
diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM35P/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM35P/portmacro.h
index 0ad1009b6..6e543efb5 100644
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM35P/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM35P/portmacro.h
@@ -60,7 +60,7 @@
 
 #ifndef configENABLE_MVE
     #define configENABLE_MVE    0
-#elif( configENABLE_MVE != 0 )
+#elif ( configENABLE_MVE != 0 )
     #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M35.
 #endif
 /*-----------------------------------------------------------*/
diff --git a/portable/ARMv8M/non_secure/portmacrocommon.h b/portable/ARMv8M/non_secure/portmacrocommon.h
index 8a8dc7d6a..e74fa8257 100644
--- a/portable/ARMv8M/non_secure/portmacrocommon.h
+++ b/portable/ARMv8M/non_secure/portmacrocommon.h
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -125,6 +127,18 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
     extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
 #endif /* configENABLE_MPU */
+
+#if ( configENABLE_PAC == 1 )
+
+    /**
+     * @brief Generates 128-bit task's random PAC key.
+     *
+     * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be
+     *             filled with a 128-bit random number.
+     */
+    void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey );
+
+#endif /* configENABLE_PAC */
 /*-----------------------------------------------------------*/
 
 /**
@@ -188,9 +202,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Settings to define an MPU region.
- */
+    /**
+     * @brief Settings to define an MPU region.
+     */
     typedef struct MPURegionSettings
     {
         uint32_t ulRBAR; /**< RBAR for the region. */
@@ -203,9 +217,14 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-/**
- * @brief System call stack.
- */
+        /* When MPU wrapper v2 is used, the task's context is stored in TCB and
+         * pxTopOfStack member of TCB points to the context location in TCB. We,
+         * therefore, need to read PSP to find the task's current top of stack. */
+        #define portGET_CURRENT_TOP_OF_STACK( pxCurrentTopOfStack ) { __asm volatile ( "mrs %0, psp"  : "=r" ( pxCurrentTopOfStack ) ); }
+
+        /**
+         * @brief System call stack.
+         */
         typedef struct SYSTEM_CALL_STACK_INFO
         {
             uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ];
@@ -218,76 +237,128 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
-/**
- * @brief MPU settings as stored in the TCB.
- */
+    /**
+     * @brief MPU settings as stored in the TCB.
+     */
     #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+        #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +-----------+---------------+----------+-----------------+------------------------------+-----+
- * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
- * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
- * +-----------+---------------+----------+-----------------+------------------------------+-----+
- *
- * <-----------><--------------><---------><----------------><-----------------------------><---->
- *      16             16            8               8                     5                   1
- */
+            /*
+             * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey |     |
+             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |            |     |
+             * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
+             *      16             16            8               8                     5                     16         1
+             */
+            #define MAX_CONTEXT_SIZE    70
+
+        #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
+
+            /*
+             * +-----------+---------------+----------+-----------------+------------------------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+             * +-----------+---------------+----------+-----------------+------------------------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><-----------------------------><---->
+             *      16             16            8               8                     5                   1
+             */
             #define MAX_CONTEXT_SIZE    54
 
-        #else /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +-----------+---------------+----------+-----------------+----------------------+-----+
- * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
- * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
- * +-----------+---------------+----------+-----------------+----------------------+-----+
- *
- * <-----------><--------------><---------><----------------><---------------------><---->
- *      16             16            8               8                  4              1
- */
+            /*
+             * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey |     |
+             * |           |               |          | PC, xPSR        | EXC_RETURN           |            |     |
+             * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><---------------------><-----------><---->
+             *      16             16            8               8                  4                16         1
+             */
+            #define MAX_CONTEXT_SIZE    69
+
+        #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
+
+            /*
+             * +-----------+---------------+----------+-----------------+----------------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+             * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
+             * +-----------+---------------+----------+-----------------+----------------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><---------------------><---->
+             *      16             16            8               8                  4              1
+             */
             #define MAX_CONTEXT_SIZE    53
 
-        #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
     #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+        #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +----------+-----------------+------------------------------+-----+
- * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
- * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
- * +----------+-----------------+------------------------------+-----+
- *
- * <---------><----------------><------------------------------><---->
- *     8               8                      5                   1
- */
+            /*
+             * +----------+-----------------+------------------------------+------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey |     |
+             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |            |     |
+             * +----------+-----------------+------------------------------+------------+-----+
+             *
+             * <---------><----------------><------------------------------><-----------><---->
+             *     8               8                      5                      16         1
+             */
+            #define MAX_CONTEXT_SIZE    38
+
+        #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
+
+            /*
+             * +----------+-----------------+------------------------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+             * +----------+-----------------+------------------------------+-----+
+             *
+             * <---------><----------------><------------------------------><---->
+             *     8               8                      5                   1
+             */
             #define MAX_CONTEXT_SIZE    22
 
+        #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+            /*
+             * +----------+-----------------+----------------------+------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey |     |
+             * |          | PC, xPSR        | EXC_RETURN           |            |     |
+             * +----------+-----------------+----------------------+------------+-----+
+             *
+             * <---------><----------------><----------------------><-----------><---->
+             *     8               8                  4                  16         1
+             */
+            #define MAX_CONTEXT_SIZE    37
+
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-/*
- * +----------+-----------------+----------------------+-----+
- * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
- * |          | PC, xPSR        | EXC_RETURN           |     |
- * +----------+-----------------+----------------------+-----+
- *
- * <---------><----------------><----------------------><---->
- *     8               8                  4              1
- */
+            /*
+             * +----------+-----------------+----------------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+             * |          | PC, xPSR        | EXC_RETURN           |     |
+             * +----------+-----------------+----------------------+-----+
+             *
+             * <---------><----------------><----------------------><---->
+             *     8               8                  4              1
+             */
             #define MAX_CONTEXT_SIZE    21
 
-        #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
     #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
+    /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
-/* Size of an Access Control List (ACL) entry in bits. */
+    /* Size of an Access Control List (ACL) entry in bits. */
     #define portACL_ENTRY_SIZE_BITS             ( 32U )
 
     typedef struct MPU_SETTINGS
diff --git a/portable/GCC/ARM_CM23/non_secure/port.c b/portable/GCC/ARM_CM23/non_secure/port.c
index f3f5d3edd..b2fd7e518 100644
--- a/portable/GCC/ARM_CM23/non_secure/port.c
+++ b/portable/GCC/ARM_CM23/non_secure/port.c
@@ -169,79 +169,80 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                            ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                            ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                             ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                            ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                            ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                           ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                           ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK        ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                      ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK                     ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                      ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK                     ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                      ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK                     ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                      ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK                     ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                      ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK                     ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                      ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK                     ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                      ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK                     ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                      ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK                     ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0                    ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1                    ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2                    ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3                    ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4                    ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5                    ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6                    ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7                    ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE                  ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
 
 #if ( portARMV8M_MINOR_VERSION >= 1 )
-    /* Enable Privileged eXecute Never MPU attribute for the selected memory
-     * region. */
-    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER   ( 1UL << 4UL )
+
+/* Enable Privileged eXecute Never MPU attribute for the selected memory
+ * region. */
+    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER    ( 1UL << 4UL )
 #endif /* portARMV8M_MINOR_VERSION >= 1 */
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT          ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                          ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE                 ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -380,14 +381,14 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to check and configure PACBTI security feature implementation.
  */
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
-    #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
+    #define portID_ISAR5_REG       ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
 
-    #define portCONTROL_UPAC_EN      ( 1UL << 7UL )
-    #define portCONTROL_PAC_EN       ( 1UL << 6UL )
-    #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
-    #define portCONTROL_BTI_EN       ( 1UL << 4UL )
+    #define portCONTROL_UPAC_EN    ( 1UL << 7UL )
+    #define portCONTROL_PAC_EN     ( 1UL << 6UL )
+    #define portCONTROL_UBTI_EN    ( 1UL << 5UL )
+    #define portCONTROL_BTI_EN     ( 1UL << 4UL )
 
 #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
@@ -427,7 +428,7 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
 /**
  * @brief Configures PACBTI features.
@@ -1212,6 +1213,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
+
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __syscalls_flash_start__;
@@ -1282,6 +1284,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
              * point (i.e. the caller of the MPU_<API>). We need to restore it
              * when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+
             /* Store the value of the PSPLIM register before the SVC was raised.
              * We need to restore it when we exit from the system call. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
@@ -1300,6 +1303,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
             /* Start executing the system call upon returning from this handler. */
             pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
+
             /* Raise a request to exit from the system call upon finishing the
              * system call. */
             pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit;
@@ -1359,6 +1363,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
+
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __privileged_functions_start__;
@@ -1541,7 +1546,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
-        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+        #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
         {
             /* Check PACBTI security feature configuration before pushing the
              * CONTROL register's value on task's TCB. */
@@ -1582,6 +1587,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
+        #if ( configENABLE_PAC == 1 )
+        {
+            uint32_t ulTaskPacKey[ 4 ], i;
+
+            vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+            for( i = 0; i < 4; i++ )
+            {
+                xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ];
+                ulIndex++;
+            }
+        }
+        #endif /* configENABLE_PAC */
+
         return &( xMPUSettings->ulContext[ ulIndex ] );
     }
 
@@ -1664,6 +1683,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #endif /* portPRELOAD_REGISTERS */
 
+        #if ( configENABLE_PAC == 1 )
+        {
+            uint32_t ulTaskPacKey[ 4 ], i;
+
+            vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+            for( i = 0; i < 4; i++ )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = ulTaskPacKey[ i ];
+            }
+        }
+        #endif /* configENABLE_PAC */
+
         return pxTopOfStack;
     }
 
@@ -1786,11 +1819,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
-    #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+    #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
     {
         /* Set the CONTROL register value based on PACBTI security feature
          * configuration before starting the first task. */
-        ( void) prvConfigurePACBTI( pdTRUE );
+        ( void ) prvConfigurePACBTI( pdTRUE );
     }
     #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
@@ -1990,9 +2023,9 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
         if( xSchedulerRunning == pdFALSE )
         {
             /* Grant access to all the kernel objects before the scheduler
-            * is started. It is necessary because there is no task running
-            * yet and therefore, we cannot use the permissions of any
-            * task. */
+             * is started. It is necessary because there is no task running
+             * yet and therefore, we cannot use the permissions of any
+             * task. */
             xAccessGranted = pdTRUE;
         }
         else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
@@ -2213,7 +2246,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
 
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
     {
@@ -2225,13 +2258,13 @@ BaseType_t xPortIsInsideInterrupt( void )
         /* Enable UsageFault exception. */
         portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
 
-        #if( configENABLE_PAC == 1 )
+        #if ( configENABLE_PAC == 1 )
         {
             ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
         }
         #endif
 
-        #if( configENABLE_BTI == 1 )
+        #if ( configENABLE_BTI == 1 )
         {
             ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
         }
diff --git a/portable/GCC/ARM_CM23/non_secure/portmacro.h b/portable/GCC/ARM_CM23/non_secure/portmacro.h
index a7f9db767..e81b89228 100644
--- a/portable/GCC/ARM_CM23/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM23/non_secure/portmacro.h
@@ -64,7 +64,7 @@
 
 #ifndef configENABLE_MVE
     #define configENABLE_MVE    0
-#elif( configENABLE_MVE != 0 )
+#elif ( configENABLE_MVE != 0 )
     #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M23.
 #endif
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h
index 8a8dc7d6a..e74fa8257 100644
--- a/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -125,6 +127,18 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
     extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
 #endif /* configENABLE_MPU */
+
+#if ( configENABLE_PAC == 1 )
+
+    /**
+     * @brief Generates 128-bit task's random PAC key.
+     *
+     * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be
+     *             filled with a 128-bit random number.
+     */
+    void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey );
+
+#endif /* configENABLE_PAC */
 /*-----------------------------------------------------------*/
 
 /**
@@ -188,9 +202,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Settings to define an MPU region.
- */
+    /**
+     * @brief Settings to define an MPU region.
+     */
     typedef struct MPURegionSettings
     {
         uint32_t ulRBAR; /**< RBAR for the region. */
@@ -203,9 +217,14 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-/**
- * @brief System call stack.
- */
+        /* When MPU wrapper v2 is used, the task's context is stored in TCB and
+         * pxTopOfStack member of TCB points to the context location in TCB. We,
+         * therefore, need to read PSP to find the task's current top of stack. */
+        #define portGET_CURRENT_TOP_OF_STACK( pxCurrentTopOfStack ) { __asm volatile ( "mrs %0, psp"  : "=r" ( pxCurrentTopOfStack ) ); }
+
+        /**
+         * @brief System call stack.
+         */
         typedef struct SYSTEM_CALL_STACK_INFO
         {
             uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ];
@@ -218,76 +237,128 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
-/**
- * @brief MPU settings as stored in the TCB.
- */
+    /**
+     * @brief MPU settings as stored in the TCB.
+     */
     #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+        #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +-----------+---------------+----------+-----------------+------------------------------+-----+
- * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
- * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
- * +-----------+---------------+----------+-----------------+------------------------------+-----+
- *
- * <-----------><--------------><---------><----------------><-----------------------------><---->
- *      16             16            8               8                     5                   1
- */
+            /*
+             * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey |     |
+             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |            |     |
+             * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
+             *      16             16            8               8                     5                     16         1
+             */
+            #define MAX_CONTEXT_SIZE    70
+
+        #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
+
+            /*
+             * +-----------+---------------+----------+-----------------+------------------------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+             * +-----------+---------------+----------+-----------------+------------------------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><-----------------------------><---->
+             *      16             16            8               8                     5                   1
+             */
             #define MAX_CONTEXT_SIZE    54
 
-        #else /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +-----------+---------------+----------+-----------------+----------------------+-----+
- * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
- * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
- * +-----------+---------------+----------+-----------------+----------------------+-----+
- *
- * <-----------><--------------><---------><----------------><---------------------><---->
- *      16             16            8               8                  4              1
- */
+            /*
+             * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey |     |
+             * |           |               |          | PC, xPSR        | EXC_RETURN           |            |     |
+             * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><---------------------><-----------><---->
+             *      16             16            8               8                  4                16         1
+             */
+            #define MAX_CONTEXT_SIZE    69
+
+        #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
+
+            /*
+             * +-----------+---------------+----------+-----------------+----------------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+             * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
+             * +-----------+---------------+----------+-----------------+----------------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><---------------------><---->
+             *      16             16            8               8                  4              1
+             */
             #define MAX_CONTEXT_SIZE    53
 
-        #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
     #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+        #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +----------+-----------------+------------------------------+-----+
- * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
- * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
- * +----------+-----------------+------------------------------+-----+
- *
- * <---------><----------------><------------------------------><---->
- *     8               8                      5                   1
- */
+            /*
+             * +----------+-----------------+------------------------------+------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey |     |
+             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |            |     |
+             * +----------+-----------------+------------------------------+------------+-----+
+             *
+             * <---------><----------------><------------------------------><-----------><---->
+             *     8               8                      5                      16         1
+             */
+            #define MAX_CONTEXT_SIZE    38
+
+        #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
+
+            /*
+             * +----------+-----------------+------------------------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+             * +----------+-----------------+------------------------------+-----+
+             *
+             * <---------><----------------><------------------------------><---->
+             *     8               8                      5                   1
+             */
             #define MAX_CONTEXT_SIZE    22
 
+        #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+            /*
+             * +----------+-----------------+----------------------+------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey |     |
+             * |          | PC, xPSR        | EXC_RETURN           |            |     |
+             * +----------+-----------------+----------------------+------------+-----+
+             *
+             * <---------><----------------><----------------------><-----------><---->
+             *     8               8                  4                  16         1
+             */
+            #define MAX_CONTEXT_SIZE    37
+
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-/*
- * +----------+-----------------+----------------------+-----+
- * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
- * |          | PC, xPSR        | EXC_RETURN           |     |
- * +----------+-----------------+----------------------+-----+
- *
- * <---------><----------------><----------------------><---->
- *     8               8                  4              1
- */
+            /*
+             * +----------+-----------------+----------------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+             * |          | PC, xPSR        | EXC_RETURN           |     |
+             * +----------+-----------------+----------------------+-----+
+             *
+             * <---------><----------------><----------------------><---->
+             *     8               8                  4              1
+             */
             #define MAX_CONTEXT_SIZE    21
 
-        #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
     #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
+    /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
-/* Size of an Access Control List (ACL) entry in bits. */
+    /* Size of an Access Control List (ACL) entry in bits. */
     #define portACL_ENTRY_SIZE_BITS             ( 32U )
 
     typedef struct MPU_SETTINGS
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
index f3f5d3edd..b2fd7e518 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
@@ -169,79 +169,80 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                            ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                            ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                             ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                            ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                            ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                           ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                           ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK        ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                      ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK                     ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                      ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK                     ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                      ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK                     ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                      ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK                     ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                      ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK                     ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                      ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK                     ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                      ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK                     ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                      ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK                     ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0                    ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1                    ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2                    ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3                    ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4                    ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5                    ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6                    ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7                    ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE                  ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
 
 #if ( portARMV8M_MINOR_VERSION >= 1 )
-    /* Enable Privileged eXecute Never MPU attribute for the selected memory
-     * region. */
-    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER   ( 1UL << 4UL )
+
+/* Enable Privileged eXecute Never MPU attribute for the selected memory
+ * region. */
+    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER    ( 1UL << 4UL )
 #endif /* portARMV8M_MINOR_VERSION >= 1 */
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT          ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                          ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE                 ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -380,14 +381,14 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to check and configure PACBTI security feature implementation.
  */
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
-    #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
+    #define portID_ISAR5_REG       ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
 
-    #define portCONTROL_UPAC_EN      ( 1UL << 7UL )
-    #define portCONTROL_PAC_EN       ( 1UL << 6UL )
-    #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
-    #define portCONTROL_BTI_EN       ( 1UL << 4UL )
+    #define portCONTROL_UPAC_EN    ( 1UL << 7UL )
+    #define portCONTROL_PAC_EN     ( 1UL << 6UL )
+    #define portCONTROL_UBTI_EN    ( 1UL << 5UL )
+    #define portCONTROL_BTI_EN     ( 1UL << 4UL )
 
 #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
@@ -427,7 +428,7 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
 /**
  * @brief Configures PACBTI features.
@@ -1212,6 +1213,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
+
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __syscalls_flash_start__;
@@ -1282,6 +1284,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
              * point (i.e. the caller of the MPU_<API>). We need to restore it
              * when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+
             /* Store the value of the PSPLIM register before the SVC was raised.
              * We need to restore it when we exit from the system call. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
@@ -1300,6 +1303,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
             /* Start executing the system call upon returning from this handler. */
             pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
+
             /* Raise a request to exit from the system call upon finishing the
              * system call. */
             pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit;
@@ -1359,6 +1363,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
+
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __privileged_functions_start__;
@@ -1541,7 +1546,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
-        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+        #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
         {
             /* Check PACBTI security feature configuration before pushing the
              * CONTROL register's value on task's TCB. */
@@ -1582,6 +1587,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
+        #if ( configENABLE_PAC == 1 )
+        {
+            uint32_t ulTaskPacKey[ 4 ], i;
+
+            vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+            for( i = 0; i < 4; i++ )
+            {
+                xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ];
+                ulIndex++;
+            }
+        }
+        #endif /* configENABLE_PAC */
+
         return &( xMPUSettings->ulContext[ ulIndex ] );
     }
 
@@ -1664,6 +1683,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #endif /* portPRELOAD_REGISTERS */
 
+        #if ( configENABLE_PAC == 1 )
+        {
+            uint32_t ulTaskPacKey[ 4 ], i;
+
+            vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+            for( i = 0; i < 4; i++ )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = ulTaskPacKey[ i ];
+            }
+        }
+        #endif /* configENABLE_PAC */
+
         return pxTopOfStack;
     }
 
@@ -1786,11 +1819,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
-    #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+    #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
     {
         /* Set the CONTROL register value based on PACBTI security feature
          * configuration before starting the first task. */
-        ( void) prvConfigurePACBTI( pdTRUE );
+        ( void ) prvConfigurePACBTI( pdTRUE );
     }
     #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
@@ -1990,9 +2023,9 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
         if( xSchedulerRunning == pdFALSE )
         {
             /* Grant access to all the kernel objects before the scheduler
-            * is started. It is necessary because there is no task running
-            * yet and therefore, we cannot use the permissions of any
-            * task. */
+             * is started. It is necessary because there is no task running
+             * yet and therefore, we cannot use the permissions of any
+             * task. */
             xAccessGranted = pdTRUE;
         }
         else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
@@ -2213,7 +2246,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
 
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
     {
@@ -2225,13 +2258,13 @@ BaseType_t xPortIsInsideInterrupt( void )
         /* Enable UsageFault exception. */
         portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
 
-        #if( configENABLE_PAC == 1 )
+        #if ( configENABLE_PAC == 1 )
         {
             ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
         }
         #endif
 
-        #if( configENABLE_BTI == 1 )
+        #if ( configENABLE_BTI == 1 )
         {
             ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
         }
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h b/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h
index a7f9db767..e81b89228 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h
@@ -64,7 +64,7 @@
 
 #ifndef configENABLE_MVE
     #define configENABLE_MVE    0
-#elif( configENABLE_MVE != 0 )
+#elif ( configENABLE_MVE != 0 )
     #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M23.
 #endif
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h
index 8a8dc7d6a..e74fa8257 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -125,6 +127,18 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
     extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
 #endif /* configENABLE_MPU */
+
+#if ( configENABLE_PAC == 1 )
+
+    /**
+     * @brief Generates 128-bit task's random PAC key.
+     *
+     * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be
+     *             filled with a 128-bit random number.
+     */
+    void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey );
+
+#endif /* configENABLE_PAC */
 /*-----------------------------------------------------------*/
 
 /**
@@ -188,9 +202,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Settings to define an MPU region.
- */
+    /**
+     * @brief Settings to define an MPU region.
+     */
     typedef struct MPURegionSettings
     {
         uint32_t ulRBAR; /**< RBAR for the region. */
@@ -203,9 +217,14 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-/**
- * @brief System call stack.
- */
+        /* When MPU wrapper v2 is used, the task's context is stored in TCB and
+         * pxTopOfStack member of TCB points to the context location in TCB. We,
+         * therefore, need to read PSP to find the task's current top of stack. */
+        #define portGET_CURRENT_TOP_OF_STACK( pxCurrentTopOfStack ) { __asm volatile ( "mrs %0, psp"  : "=r" ( pxCurrentTopOfStack ) ); }
+
+        /**
+         * @brief System call stack.
+         */
         typedef struct SYSTEM_CALL_STACK_INFO
         {
             uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ];
@@ -218,76 +237,128 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
-/**
- * @brief MPU settings as stored in the TCB.
- */
+    /**
+     * @brief MPU settings as stored in the TCB.
+     */
     #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+        #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +-----------+---------------+----------+-----------------+------------------------------+-----+
- * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
- * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
- * +-----------+---------------+----------+-----------------+------------------------------+-----+
- *
- * <-----------><--------------><---------><----------------><-----------------------------><---->
- *      16             16            8               8                     5                   1
- */
+            /*
+             * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey |     |
+             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |            |     |
+             * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
+             *      16             16            8               8                     5                     16         1
+             */
+            #define MAX_CONTEXT_SIZE    70
+
+        #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
+
+            /*
+             * +-----------+---------------+----------+-----------------+------------------------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+             * +-----------+---------------+----------+-----------------+------------------------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><-----------------------------><---->
+             *      16             16            8               8                     5                   1
+             */
             #define MAX_CONTEXT_SIZE    54
 
-        #else /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +-----------+---------------+----------+-----------------+----------------------+-----+
- * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
- * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
- * +-----------+---------------+----------+-----------------+----------------------+-----+
- *
- * <-----------><--------------><---------><----------------><---------------------><---->
- *      16             16            8               8                  4              1
- */
+            /*
+             * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey |     |
+             * |           |               |          | PC, xPSR        | EXC_RETURN           |            |     |
+             * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><---------------------><-----------><---->
+             *      16             16            8               8                  4                16         1
+             */
+            #define MAX_CONTEXT_SIZE    69
+
+        #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
+
+            /*
+             * +-----------+---------------+----------+-----------------+----------------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+             * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
+             * +-----------+---------------+----------+-----------------+----------------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><---------------------><---->
+             *      16             16            8               8                  4              1
+             */
             #define MAX_CONTEXT_SIZE    53
 
-        #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
     #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+        #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +----------+-----------------+------------------------------+-----+
- * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
- * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
- * +----------+-----------------+------------------------------+-----+
- *
- * <---------><----------------><------------------------------><---->
- *     8               8                      5                   1
- */
+            /*
+             * +----------+-----------------+------------------------------+------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey |     |
+             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |            |     |
+             * +----------+-----------------+------------------------------+------------+-----+
+             *
+             * <---------><----------------><------------------------------><-----------><---->
+             *     8               8                      5                      16         1
+             */
+            #define MAX_CONTEXT_SIZE    38
+
+        #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
+
+            /*
+             * +----------+-----------------+------------------------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+             * +----------+-----------------+------------------------------+-----+
+             *
+             * <---------><----------------><------------------------------><---->
+             *     8               8                      5                   1
+             */
             #define MAX_CONTEXT_SIZE    22
 
+        #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+            /*
+             * +----------+-----------------+----------------------+------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey |     |
+             * |          | PC, xPSR        | EXC_RETURN           |            |     |
+             * +----------+-----------------+----------------------+------------+-----+
+             *
+             * <---------><----------------><----------------------><-----------><---->
+             *     8               8                  4                  16         1
+             */
+            #define MAX_CONTEXT_SIZE    37
+
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-/*
- * +----------+-----------------+----------------------+-----+
- * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
- * |          | PC, xPSR        | EXC_RETURN           |     |
- * +----------+-----------------+----------------------+-----+
- *
- * <---------><----------------><----------------------><---->
- *     8               8                  4              1
- */
+            /*
+             * +----------+-----------------+----------------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+             * |          | PC, xPSR        | EXC_RETURN           |     |
+             * +----------+-----------------+----------------------+-----+
+             *
+             * <---------><----------------><----------------------><---->
+             *     8               8                  4              1
+             */
             #define MAX_CONTEXT_SIZE    21
 
-        #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
     #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
+    /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
-/* Size of an Access Control List (ACL) entry in bits. */
+    /* Size of an Access Control List (ACL) entry in bits. */
     #define portACL_ENTRY_SIZE_BITS             ( 32U )
 
     typedef struct MPU_SETTINGS
diff --git a/portable/GCC/ARM_CM33/non_secure/port.c b/portable/GCC/ARM_CM33/non_secure/port.c
index aa9c23816..b2fd7e518 100644
--- a/portable/GCC/ARM_CM33/non_secure/port.c
+++ b/portable/GCC/ARM_CM33/non_secure/port.c
@@ -169,79 +169,80 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                            ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                            ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                             ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                            ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                            ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                           ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                           ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK        ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                      ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK                     ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                      ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK                     ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                      ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK                     ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                      ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK                     ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                      ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK                     ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                      ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK                     ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                      ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK                     ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                      ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK                     ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0                    ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1                    ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2                    ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3                    ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4                    ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5                    ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6                    ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7                    ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE                  ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
 
 #if ( portARMV8M_MINOR_VERSION >= 1 )
-    /* Enable Privileged eXecute Never MPU attribute for the selected memory
-     * region. */
-    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER   ( 1UL << 4UL )
+
+/* Enable Privileged eXecute Never MPU attribute for the selected memory
+ * region. */
+    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER    ( 1UL << 4UL )
 #endif /* portARMV8M_MINOR_VERSION >= 1 */
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT          ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                          ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE                 ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -380,14 +381,14 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to check and configure PACBTI security feature implementation.
  */
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
-    #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
+    #define portID_ISAR5_REG       ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
 
-    #define portCONTROL_UPAC_EN      ( 1UL << 7UL )
-    #define portCONTROL_PAC_EN       ( 1UL << 6UL )
-    #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
-    #define portCONTROL_BTI_EN       ( 1UL << 4UL )
+    #define portCONTROL_UPAC_EN    ( 1UL << 7UL )
+    #define portCONTROL_PAC_EN     ( 1UL << 6UL )
+    #define portCONTROL_UBTI_EN    ( 1UL << 5UL )
+    #define portCONTROL_BTI_EN     ( 1UL << 4UL )
 
 #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
@@ -409,7 +410,7 @@ static void prvTaskExitError( void );
  * @return uint32_t Access permissions.
  */
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0  */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 
 #if ( configENABLE_MPU == 1 )
 
@@ -427,7 +428,7 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
 /**
  * @brief Configures PACBTI features.
@@ -890,7 +891,7 @@ static void prvTaskExitError( void )
         return ulAccessPermissions;
     }
 
-#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0  */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
@@ -1212,6 +1213,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
+
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __syscalls_flash_start__;
@@ -1282,6 +1284,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
              * point (i.e. the caller of the MPU_<API>). We need to restore it
              * when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+
             /* Store the value of the PSPLIM register before the SVC was raised.
              * We need to restore it when we exit from the system call. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
@@ -1300,6 +1303,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
             /* Start executing the system call upon returning from this handler. */
             pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
+
             /* Raise a request to exit from the system call upon finishing the
              * system call. */
             pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit;
@@ -1359,6 +1363,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
+
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __privileged_functions_start__;
@@ -1541,7 +1546,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
-        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+        #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
         {
             /* Check PACBTI security feature configuration before pushing the
              * CONTROL register's value on task's TCB. */
@@ -1582,6 +1587,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
+        #if ( configENABLE_PAC == 1 )
+        {
+            uint32_t ulTaskPacKey[ 4 ], i;
+
+            vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+            for( i = 0; i < 4; i++ )
+            {
+                xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ];
+                ulIndex++;
+            }
+        }
+        #endif /* configENABLE_PAC */
+
         return &( xMPUSettings->ulContext[ ulIndex ] );
     }
 
@@ -1664,6 +1683,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #endif /* portPRELOAD_REGISTERS */
 
+        #if ( configENABLE_PAC == 1 )
+        {
+            uint32_t ulTaskPacKey[ 4 ], i;
+
+            vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+            for( i = 0; i < 4; i++ )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = ulTaskPacKey[ i ];
+            }
+        }
+        #endif /* configENABLE_PAC */
+
         return pxTopOfStack;
     }
 
@@ -1786,11 +1819,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
-    #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+    #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
     {
         /* Set the CONTROL register value based on PACBTI security feature
          * configuration before starting the first task. */
-        ( void) prvConfigurePACBTI( pdTRUE );
+        ( void ) prvConfigurePACBTI( pdTRUE );
     }
     #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
@@ -1990,9 +2023,9 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
         if( xSchedulerRunning == pdFALSE )
         {
             /* Grant access to all the kernel objects before the scheduler
-            * is started. It is necessary because there is no task running
-            * yet and therefore, we cannot use the permissions of any
-            * task. */
+             * is started. It is necessary because there is no task running
+             * yet and therefore, we cannot use the permissions of any
+             * task. */
             xAccessGranted = pdTRUE;
         }
         else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
@@ -2213,7 +2246,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
 
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
     {
@@ -2225,13 +2258,13 @@ BaseType_t xPortIsInsideInterrupt( void )
         /* Enable UsageFault exception. */
         portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
 
-        #if( configENABLE_PAC == 1 )
+        #if ( configENABLE_PAC == 1 )
         {
             ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
         }
         #endif
 
-        #if( configENABLE_BTI == 1 )
+        #if ( configENABLE_BTI == 1 )
         {
             ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
         }
diff --git a/portable/GCC/ARM_CM33/non_secure/portasm.c b/portable/GCC/ARM_CM33/non_secure/portasm.c
index aaeccaa35..0ebbe48a4 100644
--- a/portable/GCC/ARM_CM33/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM33/non_secure/portasm.c
@@ -77,16 +77,16 @@
             "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
             "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
             "                                                 \n"
-            #if ( configTOTAL_MPU_REGIONS == 16 )
-                "    movs r3, #8                                  \n" /* r3 = 8. */
-                "    str r3, [r1]                                 \n" /* Program RNR = 8. */
-                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
-                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-                "    movs r3, #12                                 \n" /* r3 = 12. */
-                "    str r3, [r1]                                 \n" /* Program RNR = 12. */
-                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
-                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-            #endif /* configTOTAL_MPU_REGIONS == 16 */
+        #if ( configTOTAL_MPU_REGIONS == 16 )
+            "    movs r3, #8                                  \n" /* r3 = 8. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 8. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "    movs r3, #12                                 \n" /* r3 = 12. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 12. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+        #endif /* configTOTAL_MPU_REGIONS == 16 */
             "                                                 \n"
             "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
@@ -100,6 +100,14 @@
             "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
             "                                                 \n"
             " restore_special_regs_first_task:                \n"
+        #if ( configENABLE_PAC == 1 )
+            "   ldmdb r2!, {r3-r6}                            \n" /* Read task's dedicated PAC key from the task's context. */
+            "   msr  PAC_KEY_P_0, r3                          \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+            "   msr  PAC_KEY_P_1, r4                          \n"
+            "   msr  PAC_KEY_P_2, r5                          \n"
+            "   msr  PAC_KEY_P_3, r6                          \n"
+            "   clrm {r3-r6}                                  \n" /* Clear r3-r6. */
+        #endif /* configENABLE_PAC */
             "    ldmdb r2!, {r0, r3-r5, lr}                   \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
             "    msr psp, r3                                  \n"
             "    msr psplim, r4                               \n"
@@ -132,6 +140,15 @@
             "   ldr  r3, [r2]                                   \n" /* Read pxCurrentTCB. */
             "   ldr  r0, [r3]                                   \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
             "                                                   \n"
+        #if ( configENABLE_PAC == 1 )
+            "   ldmia r0!, {r1-r4}                              \n" /* Read task's dedicated PAC key from stack. */
+            "   msr  PAC_KEY_P_3, r1                            \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+            "   msr  PAC_KEY_P_2, r2                            \n"
+            "   msr  PAC_KEY_P_1, r3                            \n"
+            "   msr  PAC_KEY_P_0, r4                            \n"
+            "   clrm {r1-r4}                                    \n" /* Clear r1-r4. */
+        #endif /* configENABLE_PAC */
+            "                                                   \n"
             "   ldm  r0!, {r1-r3}                               \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
             "   ldr  r4, =xSecureContext                        \n"
             "   str  r1, [r4]                                   \n" /* Set xSecureContext to this task's value for the same. */
@@ -280,17 +297,15 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "                                                 \n"
             " save_general_regs:                              \n"
             "    mrs r3, psp                                  \n"
-            "                                                 \n"
-            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-                "    add r3, r3, #0x20                            \n" /* Move r3 to location where s0 is saved. */
-                "    tst lr, #0x10                                \n"
-                "    ittt eq                                      \n"
-                "    vstmiaeq r2!, {s16-s31}                      \n" /* Store s16-s31. */
-                "    vldmiaeq r3, {s0-s16}                        \n" /* Copy hardware saved FP context into s0-s16. */
-                "    vstmiaeq r2!, {s0-s16}                       \n" /* Store hardware saved FP context. */
-                "    sub r3, r3, #0x20                            \n" /* Set r3 back to the location of hardware saved context. */
-            #endif /* configENABLE_FPU || configENABLE_MVE */
-            "                                                 \n"
+        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            "    add r3, r3, #0x20                            \n" /* Move r3 to location where s0 is saved. */
+            "    tst lr, #0x10                                \n"
+            "    ittt eq                                      \n"
+            "    vstmiaeq r2!, {s16-s31}                      \n" /* Store s16-s31. */
+            "    vldmiaeq r3, {s0-s16}                        \n" /* Copy hardware saved FP context into s0-s16. */
+            "    vstmiaeq r2!, {s0-s16}                       \n" /* Store hardware saved FP context. */
+            "    sub r3, r3, #0x20                            \n" /* Set r3 back to the location of hardware saved context. */
+        #endif /* configENABLE_FPU || configENABLE_MVE */
             "    stmia r2!, {r4-r11}                          \n" /* Store r4-r11. */
             "    ldmia r3, {r4-r11}                           \n" /* Copy the hardware saved context into r4-r11. */
             "    stmia r2!, {r4-r11}                          \n" /* Store the hardware saved context. */
@@ -300,7 +315,15 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    mrs r4, psplim                               \n" /* r4 = PSPLIM. */
             "    mrs r5, control                              \n" /* r5 = CONTROL. */
             "    stmia r2!, {r0, r3-r5, lr}                   \n" /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
-            "    str r2, [r1]                                 \n" /* Save the location from where the context should be restored as the first member of TCB. */
+        #if ( configENABLE_PAC == 1 )
+            "   mrs  r3, PAC_KEY_P_0                          \n" /* Read task's dedicated PAC key from the PAC key registers. */
+            "   mrs  r4, PAC_KEY_P_1                          \n"
+            "   mrs  r5, PAC_KEY_P_2                          \n"
+            "   mrs  r6, PAC_KEY_P_3                          \n"
+            "   stmia r2!, {r3-r6}                            \n" /* Store the task's dedicated PAC key on the task's context. */
+            "   clrm {r3-r6}                                  \n" /* Clear r3-r6. */
+        #endif /* configENABLE_PAC */
+            "    str r2, [r1]                                 \n"      /* Save the location from where the context should be restored as the first member of TCB. */
             "                                                 \n"
             " select_next_task:                               \n"
             "    mov r0, %0                                   \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
@@ -335,16 +358,16 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
             "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
             "                                                 \n"
-            #if ( configTOTAL_MPU_REGIONS == 16 )
-                "    movs r3, #8                                  \n" /* r3 = 8. */
-                "    str r3, [r1]                                 \n" /* Program RNR = 8. */
-                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-                "    movs r3, #12                                 \n" /* r3 = 12. */
-                "    str r3, [r1]                                 \n" /* Program RNR = 12. */
-                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-            #endif /* configTOTAL_MPU_REGIONS == 16 */
+        #if ( configTOTAL_MPU_REGIONS == 16 )
+            "    movs r3, #8                                  \n" /* r3 = 8. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 8. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "    movs r3, #12                                 \n" /* r3 = 12. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 12. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+        #endif /* configTOTAL_MPU_REGIONS == 16 */
             "                                                 \n"
             "   ldr r1, =0xe000ed94                           \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
@@ -358,6 +381,14 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
             "                                                 \n"
             " restore_special_regs:                           \n"
+        #if ( configENABLE_PAC == 1 )
+            "   ldmdb r2!, {r3-r6}                            \n" /* Read task's dedicated PAC key from the task's context. */
+            "   msr  PAC_KEY_P_0, r3                          \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+            "   msr  PAC_KEY_P_1, r4                          \n"
+            "   msr  PAC_KEY_P_2, r5                          \n"
+            "   msr  PAC_KEY_P_3, r6                          \n"
+            "   clrm {r3-r6}                                  \n" /* Clear r3-r6. */
+        #endif /* configENABLE_PAC */
             "    ldmdb r2!, {r0, r3-r5, lr}                   \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
             "    msr psp, r3                                  \n"
             "    msr psplim, r4                               \n"
@@ -380,13 +411,13 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
             "    stmia r3!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
             "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 restored. */
-            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-                "    tst lr, #0x10                                \n"
-                "    ittt eq                                      \n"
-                "    vldmdbeq r2!, {s0-s16}                       \n" /* s0-s16 contain hardware saved FP context. */
-                "    vstmiaeq r3!, {s0-s16}                       \n" /* Copy hardware saved FP context on the task stack. */
-                "    vldmdbeq r2!, {s16-s31}                      \n" /* Restore s16-s31. */
-            #endif /* configENABLE_FPU || configENABLE_MVE */
+        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            "    tst lr, #0x10                                \n"
+            "    ittt eq                                      \n"
+            "    vldmdbeq r2!, {s0-s16}                       \n" /* s0-s16 contain hardware saved FP context. */
+            "    vstmiaeq r3!, {s0-s16}                       \n" /* Copy hardware saved FP context on the task stack. */
+            "    vldmdbeq r2!, {s16-s31}                      \n" /* Restore s16-s31. */
+        #endif /* configENABLE_FPU || configENABLE_MVE */
             "                                                 \n"
             " restore_context_done:                           \n"
             "    str r2, [r1]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
@@ -401,89 +432,99 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
     {
         __asm volatile
         (
-            "   .syntax unified                                 \n"
-            "   .extern SecureContext_SaveContext               \n"
-            "   .extern SecureContext_LoadContext               \n"
-            "                                                   \n"
-            "   ldr r3, =xSecureContext                         \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-            "   ldr r0, [r3]                                    \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
-            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
-            "   mrs r2, psp                                     \n" /* Read PSP in r2. */
-            "                                                   \n"
-            "   cbz r0, save_ns_context                         \n" /* No secure context to save. */
-            "   push {r0-r2, r14}                               \n"
-            "   bl SecureContext_SaveContext                    \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-            "   pop {r0-r3}                                     \n" /* LR is now in r3. */
-            "   mov lr, r3                                      \n" /* LR = r3. */
-            "   lsls r1, r3, #25                                \n" /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-            "   bpl save_ns_context                             \n" /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-            "                                                   \n"
-            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB.*/
-            "   subs r2, r2, #12                                \n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */
-            "   str r2, [r1]                                    \n" /* Save the new top of stack in TCB. */
-            "   mrs r1, psplim                                  \n" /* r1 = PSPLIM. */
-            "   mov r3, lr                                      \n" /* r3 = LR/EXC_RETURN. */
-            "   stmia r2!, {r0, r1, r3}                         \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
-            "   b select_next_task                              \n"
-            "                                                   \n"
-            " save_ns_context:                                  \n"
-            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
-            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-                "   tst lr, #0x10                               \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
-                "   it eq                                       \n"
-                "   vstmdbeq r2!, {s16-s31}                     \n" /* Store the additional FP context registers which are not saved automatically. */
-            #endif /* configENABLE_FPU || configENABLE_MVE */
-            "   subs r2, r2, #44                                \n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
-            "   str r2, [r1]                                    \n" /* Save the new top of stack in TCB. */
-            "   adds r2, r2, #12                                \n" /* r2 = r2 + 12. */
-            "   stm r2, {r4-r11}                                \n" /* Store the registers that are not saved automatically. */
-            "   mrs r1, psplim                                  \n" /* r1 = PSPLIM. */
-            "   mov r3, lr                                      \n" /* r3 = LR/EXC_RETURN. */
-            "   subs r2, r2, #12                                \n" /* r2 = r2 - 12. */
-            "   stmia r2!, {r0, r1, r3}                         \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
-            "                                                   \n"
-            " select_next_task:                                 \n"
-            "   mov r0, %0                                      \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
-            "   msr basepri, r0                                 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-            "   dsb                                             \n"
-            "   isb                                             \n"
-            "   bl vTaskSwitchContext                           \n"
-            "   mov r0, #0                                      \n" /* r0 = 0. */
-            "   msr basepri, r0                                 \n" /* Enable interrupts. */
-            "                                                   \n"
-            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
-            "   ldr r2, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
-            "                                                   \n"
-            "   ldmia r2!, {r0, r1, r4}                         \n" /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
-            "   msr psplim, r1                                  \n" /* Restore the PSPLIM register value for the task. */
-            "   mov lr, r4                                      \n" /* LR = r4. */
-            "   ldr r3, =xSecureContext                         \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-            "   str r0, [r3]                                    \n" /* Restore the task's xSecureContext. */
-            "   cbz r0, restore_ns_context                      \n" /* If there is no secure context for the task, restore the non-secure context. */
-            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
-            "   push {r2, r4}                                   \n"
-            "   bl SecureContext_LoadContext                    \n" /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-            "   pop {r2, r4}                                    \n"
-            "   mov lr, r4                                      \n" /* LR = r4. */
-            "   lsls r1, r4, #25                                \n" /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-            "   bpl restore_ns_context                          \n" /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-            "   msr psp, r2                                     \n" /* Remember the new top of stack for the task. */
-            "   bx lr                                           \n"
-            "                                                   \n"
-            " restore_ns_context:                               \n"
-            "   ldmia r2!, {r4-r11}                             \n" /* Restore the registers that are not automatically restored. */
-            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-                "   tst lr, #0x10                               \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
-                "   it eq                                       \n"
-                "   vldmiaeq r2!, {s16-s31}                     \n" /* Restore the additional FP context registers which are not restored automatically. */
-            #endif /* configENABLE_FPU || configENABLE_MVE */
-            "   msr psp, r2                                     \n" /* Remember the new top of stack for the task. */
-            "   bx lr                                           \n"
+            " .syntax unified                                 \n"
+            " .extern SecureContext_SaveContext               \n"
+            " .extern SecureContext_LoadContext               \n"
+            "                                                 \n"
+            " ldr r3, =xSecureContext                         \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            " ldr r0, [r3]                                    \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+            " ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            " ldr r1, [r3]                                    \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
+            " mrs r2, psp                                     \n" /* Read PSP in r2. */
+            "                                                 \n"
+            " cbz r0, save_ns_context                         \n" /* No secure context to save. */
+            " save_s_context:                                 \n"
+            "    push {r0-r2, lr}                             \n"
+            "    bl SecureContext_SaveContext                 \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+            "    pop {r0-r2, lr}                              \n"
+            "                                                 \n"
+            " save_ns_context:                                \n"
+            "    mov r3, lr                                   \n" /* r3 = LR (EXC_RETURN). */
+            "    lsls r3, r3, #25                             \n" /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+            "    bmi save_special_regs                        \n" /* If r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used. */
+            "                                                 \n"
+            " save_general_regs:                              \n"
+        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            "    tst lr, #0x10                                \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+            "    it eq                                        \n"
+            "    vstmdbeq r2!, {s16-s31}                      \n" /* Store the additional FP context registers which are not saved automatically. */
+        #endif /* configENABLE_FPU || configENABLE_MVE */
+            "   stmdb r2!, {r4-r11}                           \n" /* Store the registers that are not saved automatically. */
+            "                                                 \n"
+            " save_special_regs:                              \n"
+            "    mrs r3, psplim                               \n" /* r3 = PSPLIM. */
+            "    stmdb r2!, {r0, r3, lr}                      \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
+        #if ( configENABLE_PAC == 1 )
+            "    mrs  r3, PAC_KEY_P_3                         \n" /* Read task's dedicated PAC key from the PAC key registers. */
+            "    mrs  r4, PAC_KEY_P_2                         \n"
+            "    mrs  r5, PAC_KEY_P_1                         \n"
+            "    mrs  r6, PAC_KEY_P_0                         \n"
+            "    stmdb r2!, {r3-r6}                           \n" /* Store the task's dedicated PAC key on the stack. */
+            "    clrm {r3-r6}                                 \n" /* Clear r3-r6. */
+        #endif /* configENABLE_PAC */
+            "                                                 \n"
+            " str r2, [r1]                                    \n" /* Save the new top of stack in TCB. */
+            "                                                 \n"
+            " select_next_task:                               \n"
+            "    mov r0, %0                                   \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
+            "    msr basepri, r0                              \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+            "    dsb                                          \n"
+            "    isb                                          \n"
+            "    bl vTaskSwitchContext                        \n"
+            "    mov r0, #0                                   \n" /* r0 = 0. */
+            "    msr basepri, r0                              \n" /* Enable interrupts. */
+            "                                                 \n"
+            " restore_context:                                \n"
+            "    ldr r3, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r1, [r3]                                 \n" /* Read pxCurrentTCB. */
+            "    ldr r2, [r1]                                 \n" /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
+            "                                                 \n"
+            " restore_special_regs:                           \n"
+        #if ( configENABLE_PAC == 1 )
+            "    ldmia r2!, {r3-r6}                           \n" /* Read task's dedicated PAC key from stack. */
+            "    msr  PAC_KEY_P_3, r3                         \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+            "    msr  PAC_KEY_P_2, r4                         \n"
+            "    msr  PAC_KEY_P_1, r5                         \n"
+            "    msr  PAC_KEY_P_0, r6                         \n"
+            "    clrm {r3-r6}                                 \n" /* Clear r3-r6. */
+        #endif /* configENABLE_PAC */
+            "    ldmia r2!, {r0, r3, lr}                      \n" /* Read from stack - r0 = xSecureContext, r3 = PSPLIM and LR restored. */
+            "    msr psplim, r3                               \n" /* Restore the PSPLIM register value for the task. */
+            "    ldr r3, =xSecureContext                      \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "    str r0, [r3]                                 \n" /* Restore the task's xSecureContext. */
+            "    cbz r0, restore_ns_context                   \n" /* If there is no secure context for the task, restore the non-secure context. */
+            "                                                 \n"
+            " restore_s_context:                              \n"
+            "    push {r1-r3, lr}                             \n"
+            "    bl SecureContext_LoadContext                 \n" /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+            "    pop {r1-r3, lr}                              \n"
+            "                                                 \n"
+            " restore_ns_context:                             \n"
+            "    mov r0, lr                                   \n" /* r0 = LR (EXC_RETURN). */
+            "    lsls r0, r0, #25                             \n" /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+            "    bmi restore_context_done                     \n" /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
+            "                                                 \n"
+            " restore_general_regs:                           \n"
+            "    ldmia r2!, {r4-r11}                          \n" /* Restore the registers that are not automatically restored. */
+        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            "   tst lr, #0x10                                 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+            "   it eq                                         \n"
+            "   vldmiaeq r2!, {s16-s31}                       \n" /* Restore the additional FP context registers which are not restored automatically. */
+        #endif /* configENABLE_FPU || configENABLE_MVE */
+            "                                                 \n"
+            " restore_context_done:                           \n"
+            "    msr psp, r2                                  \n" /* Remember the new top of stack for the task. */
+            "    bx lr                                        \n"
             ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
         );
     }
diff --git a/portable/GCC/ARM_CM33/non_secure/portmacro.h b/portable/GCC/ARM_CM33/non_secure/portmacro.h
index 0fc61f23c..2d435ca0b 100644
--- a/portable/GCC/ARM_CM33/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM33/non_secure/portmacro.h
@@ -60,7 +60,7 @@
 
 #ifndef configENABLE_MVE
     #define configENABLE_MVE    0
-#elif( configENABLE_MVE != 0 )
+#elif ( configENABLE_MVE != 0 )
     #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M33.
 #endif
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h
index 8a8dc7d6a..e74fa8257 100644
--- a/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -125,6 +127,18 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
     extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
 #endif /* configENABLE_MPU */
+
+#if ( configENABLE_PAC == 1 )
+
+    /**
+     * @brief Generates 128-bit task's random PAC key.
+     *
+     * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be
+     *             filled with a 128-bit random number.
+     */
+    void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey );
+
+#endif /* configENABLE_PAC */
 /*-----------------------------------------------------------*/
 
 /**
@@ -188,9 +202,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Settings to define an MPU region.
- */
+    /**
+     * @brief Settings to define an MPU region.
+     */
     typedef struct MPURegionSettings
     {
         uint32_t ulRBAR; /**< RBAR for the region. */
@@ -203,9 +217,14 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-/**
- * @brief System call stack.
- */
+        /* When MPU wrapper v2 is used, the task's context is stored in TCB and
+         * pxTopOfStack member of TCB points to the context location in TCB. We,
+         * therefore, need to read PSP to find the task's current top of stack. */
+        #define portGET_CURRENT_TOP_OF_STACK( pxCurrentTopOfStack ) { __asm volatile ( "mrs %0, psp"  : "=r" ( pxCurrentTopOfStack ) ); }
+
+        /**
+         * @brief System call stack.
+         */
         typedef struct SYSTEM_CALL_STACK_INFO
         {
             uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ];
@@ -218,76 +237,128 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
-/**
- * @brief MPU settings as stored in the TCB.
- */
+    /**
+     * @brief MPU settings as stored in the TCB.
+     */
     #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+        #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +-----------+---------------+----------+-----------------+------------------------------+-----+
- * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
- * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
- * +-----------+---------------+----------+-----------------+------------------------------+-----+
- *
- * <-----------><--------------><---------><----------------><-----------------------------><---->
- *      16             16            8               8                     5                   1
- */
+            /*
+             * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey |     |
+             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |            |     |
+             * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
+             *      16             16            8               8                     5                     16         1
+             */
+            #define MAX_CONTEXT_SIZE    70
+
+        #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
+
+            /*
+             * +-----------+---------------+----------+-----------------+------------------------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+             * +-----------+---------------+----------+-----------------+------------------------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><-----------------------------><---->
+             *      16             16            8               8                     5                   1
+             */
             #define MAX_CONTEXT_SIZE    54
 
-        #else /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +-----------+---------------+----------+-----------------+----------------------+-----+
- * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
- * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
- * +-----------+---------------+----------+-----------------+----------------------+-----+
- *
- * <-----------><--------------><---------><----------------><---------------------><---->
- *      16             16            8               8                  4              1
- */
+            /*
+             * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey |     |
+             * |           |               |          | PC, xPSR        | EXC_RETURN           |            |     |
+             * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><---------------------><-----------><---->
+             *      16             16            8               8                  4                16         1
+             */
+            #define MAX_CONTEXT_SIZE    69
+
+        #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
+
+            /*
+             * +-----------+---------------+----------+-----------------+----------------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+             * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
+             * +-----------+---------------+----------+-----------------+----------------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><---------------------><---->
+             *      16             16            8               8                  4              1
+             */
             #define MAX_CONTEXT_SIZE    53
 
-        #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
     #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+        #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +----------+-----------------+------------------------------+-----+
- * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
- * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
- * +----------+-----------------+------------------------------+-----+
- *
- * <---------><----------------><------------------------------><---->
- *     8               8                      5                   1
- */
+            /*
+             * +----------+-----------------+------------------------------+------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey |     |
+             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |            |     |
+             * +----------+-----------------+------------------------------+------------+-----+
+             *
+             * <---------><----------------><------------------------------><-----------><---->
+             *     8               8                      5                      16         1
+             */
+            #define MAX_CONTEXT_SIZE    38
+
+        #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
+
+            /*
+             * +----------+-----------------+------------------------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+             * +----------+-----------------+------------------------------+-----+
+             *
+             * <---------><----------------><------------------------------><---->
+             *     8               8                      5                   1
+             */
             #define MAX_CONTEXT_SIZE    22
 
+        #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+            /*
+             * +----------+-----------------+----------------------+------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey |     |
+             * |          | PC, xPSR        | EXC_RETURN           |            |     |
+             * +----------+-----------------+----------------------+------------+-----+
+             *
+             * <---------><----------------><----------------------><-----------><---->
+             *     8               8                  4                  16         1
+             */
+            #define MAX_CONTEXT_SIZE    37
+
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-/*
- * +----------+-----------------+----------------------+-----+
- * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
- * |          | PC, xPSR        | EXC_RETURN           |     |
- * +----------+-----------------+----------------------+-----+
- *
- * <---------><----------------><----------------------><---->
- *     8               8                  4              1
- */
+            /*
+             * +----------+-----------------+----------------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+             * |          | PC, xPSR        | EXC_RETURN           |     |
+             * +----------+-----------------+----------------------+-----+
+             *
+             * <---------><----------------><----------------------><---->
+             *     8               8                  4              1
+             */
             #define MAX_CONTEXT_SIZE    21
 
-        #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
     #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
+    /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
-/* Size of an Access Control List (ACL) entry in bits. */
+    /* Size of an Access Control List (ACL) entry in bits. */
     #define portACL_ENTRY_SIZE_BITS             ( 32U )
 
     typedef struct MPU_SETTINGS
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
index aa9c23816..b2fd7e518 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
@@ -169,79 +169,80 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                            ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                            ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                             ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                            ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                            ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                           ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                           ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK        ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                      ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK                     ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                      ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK                     ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                      ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK                     ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                      ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK                     ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                      ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK                     ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                      ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK                     ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                      ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK                     ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                      ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK                     ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0                    ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1                    ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2                    ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3                    ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4                    ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5                    ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6                    ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7                    ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE                  ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
 
 #if ( portARMV8M_MINOR_VERSION >= 1 )
-    /* Enable Privileged eXecute Never MPU attribute for the selected memory
-     * region. */
-    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER   ( 1UL << 4UL )
+
+/* Enable Privileged eXecute Never MPU attribute for the selected memory
+ * region. */
+    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER    ( 1UL << 4UL )
 #endif /* portARMV8M_MINOR_VERSION >= 1 */
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT          ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                          ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE                 ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -380,14 +381,14 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to check and configure PACBTI security feature implementation.
  */
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
-    #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
+    #define portID_ISAR5_REG       ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
 
-    #define portCONTROL_UPAC_EN      ( 1UL << 7UL )
-    #define portCONTROL_PAC_EN       ( 1UL << 6UL )
-    #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
-    #define portCONTROL_BTI_EN       ( 1UL << 4UL )
+    #define portCONTROL_UPAC_EN    ( 1UL << 7UL )
+    #define portCONTROL_PAC_EN     ( 1UL << 6UL )
+    #define portCONTROL_UBTI_EN    ( 1UL << 5UL )
+    #define portCONTROL_BTI_EN     ( 1UL << 4UL )
 
 #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
@@ -409,7 +410,7 @@ static void prvTaskExitError( void );
  * @return uint32_t Access permissions.
  */
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0  */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 
 #if ( configENABLE_MPU == 1 )
 
@@ -427,7 +428,7 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
 /**
  * @brief Configures PACBTI features.
@@ -890,7 +891,7 @@ static void prvTaskExitError( void )
         return ulAccessPermissions;
     }
 
-#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0  */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
@@ -1212,6 +1213,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
+
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __syscalls_flash_start__;
@@ -1282,6 +1284,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
              * point (i.e. the caller of the MPU_<API>). We need to restore it
              * when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+
             /* Store the value of the PSPLIM register before the SVC was raised.
              * We need to restore it when we exit from the system call. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
@@ -1300,6 +1303,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
             /* Start executing the system call upon returning from this handler. */
             pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
+
             /* Raise a request to exit from the system call upon finishing the
              * system call. */
             pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit;
@@ -1359,6 +1363,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
+
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __privileged_functions_start__;
@@ -1541,7 +1546,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
-        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+        #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
         {
             /* Check PACBTI security feature configuration before pushing the
              * CONTROL register's value on task's TCB. */
@@ -1582,6 +1587,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
+        #if ( configENABLE_PAC == 1 )
+        {
+            uint32_t ulTaskPacKey[ 4 ], i;
+
+            vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+            for( i = 0; i < 4; i++ )
+            {
+                xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ];
+                ulIndex++;
+            }
+        }
+        #endif /* configENABLE_PAC */
+
         return &( xMPUSettings->ulContext[ ulIndex ] );
     }
 
@@ -1664,6 +1683,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #endif /* portPRELOAD_REGISTERS */
 
+        #if ( configENABLE_PAC == 1 )
+        {
+            uint32_t ulTaskPacKey[ 4 ], i;
+
+            vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+            for( i = 0; i < 4; i++ )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = ulTaskPacKey[ i ];
+            }
+        }
+        #endif /* configENABLE_PAC */
+
         return pxTopOfStack;
     }
 
@@ -1786,11 +1819,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
-    #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+    #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
     {
         /* Set the CONTROL register value based on PACBTI security feature
          * configuration before starting the first task. */
-        ( void) prvConfigurePACBTI( pdTRUE );
+        ( void ) prvConfigurePACBTI( pdTRUE );
     }
     #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
@@ -1990,9 +2023,9 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
         if( xSchedulerRunning == pdFALSE )
         {
             /* Grant access to all the kernel objects before the scheduler
-            * is started. It is necessary because there is no task running
-            * yet and therefore, we cannot use the permissions of any
-            * task. */
+             * is started. It is necessary because there is no task running
+             * yet and therefore, we cannot use the permissions of any
+             * task. */
             xAccessGranted = pdTRUE;
         }
         else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
@@ -2213,7 +2246,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
 
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
     {
@@ -2225,13 +2258,13 @@ BaseType_t xPortIsInsideInterrupt( void )
         /* Enable UsageFault exception. */
         portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
 
-        #if( configENABLE_PAC == 1 )
+        #if ( configENABLE_PAC == 1 )
         {
             ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
         }
         #endif
 
-        #if( configENABLE_BTI == 1 )
+        #if ( configENABLE_BTI == 1 )
         {
             ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
         }
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c b/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c
index 7cdff7005..bc7bb6071 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c
@@ -77,16 +77,16 @@
             "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
             "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
             "                                                 \n"
-            #if ( configTOTAL_MPU_REGIONS == 16 )
-                "    movs r3, #8                                  \n" /* r3 = 8. */
-                "    str r3, [r1]                                 \n" /* Program RNR = 8. */
-                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-                "    movs r3, #12                                 \n" /* r3 = 12. */
-                "    str r3, [r1]                                 \n" /* Program RNR = 12. */
-                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-            #endif /* configTOTAL_MPU_REGIONS == 16 */
+        #if ( configTOTAL_MPU_REGIONS == 16 )
+            "    movs r3, #8                                  \n" /* r3 = 8. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 8. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "    movs r3, #12                                 \n" /* r3 = 12. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 12. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+        #endif /* configTOTAL_MPU_REGIONS == 16 */
             "                                                 \n"
             "   ldr r1, =0xe000ed94                           \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
@@ -100,6 +100,14 @@
             "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
             "                                                 \n"
             " restore_special_regs_first_task:                \n"
+        #if ( configENABLE_PAC == 1 )
+            "   ldmdb r1!, {r2-r5}                            \n" /* Read task's dedicated PAC key from the task's context. */
+            "   msr  PAC_KEY_P_0, r2                          \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+            "   msr  PAC_KEY_P_1, r3                          \n"
+            "   msr  PAC_KEY_P_2, r4                          \n"
+            "   msr  PAC_KEY_P_3, r5                          \n"
+            "   clrm {r2-r5}                                  \n" /* Clear r2-r5. */
+        #endif /* configENABLE_PAC */
             "    ldmdb r1!, {r2-r4, lr}                       \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
             "    msr psp, r2                                  \n"
             "    msr psplim, r3                               \n"
@@ -130,6 +138,15 @@
             "   ldr  r1, [r2]                                   \n" /* Read pxCurrentTCB. */
             "   ldr  r0, [r1]                                   \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
             "                                                   \n"
+        #if ( configENABLE_PAC == 1 )
+            "   ldmia r0!, {r1-r4}                              \n" /* Read task's dedicated PAC key from stack. */
+            "   msr  PAC_KEY_P_3, r1                            \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+            "   msr  PAC_KEY_P_2, r2                            \n"
+            "   msr  PAC_KEY_P_1, r3                            \n"
+            "   msr  PAC_KEY_P_0, r4                            \n"
+            "   clrm {r1-r4}                                    \n" /* Clear r1-r4. */
+        #endif /* configENABLE_PAC */
+            "                                                   \n"
             "   ldm  r0!, {r1-r2}                               \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
             "   msr  psplim, r1                                 \n" /* Set this task's PSPLIM value. */
             "   mrs  r1, control                                \n" /* Obtain current control register value. */
@@ -261,16 +278,15 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             " mrs r2, psp                                     \n" /* r2 = PSP. */
             "                                                 \n"
             " save_general_regs:                              \n"
-            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-                "    add r2, r2, #0x20                            \n" /* Move r2 to location where s0 is saved. */
-                "    tst lr, #0x10                                \n"
-                "    ittt eq                                      \n"
-                "    vstmiaeq r1!, {s16-s31}                      \n" /* Store s16-s31. */
-                "    vldmiaeq r2, {s0-s16}                        \n" /* Copy hardware saved FP context into s0-s16. */
-                "    vstmiaeq r1!, {s0-s16}                       \n" /* Store hardware saved FP context. */
-                "    sub r2, r2, #0x20                            \n" /* Set r2 back to the location of hardware saved context. */
-            #endif /* configENABLE_FPU || configENABLE_MVE */
-            "                                                 \n"
+        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            "    add r2, r2, #0x20                            \n" /* Move r2 to location where s0 is saved. */
+            "    tst lr, #0x10                                \n"
+            "    ittt eq                                      \n"
+            "    vstmiaeq r1!, {s16-s31}                      \n" /* Store s16-s31. */
+            "    vldmiaeq r2, {s0-s16}                        \n" /* Copy hardware saved FP context into s0-s16. */
+            "    vstmiaeq r1!, {s0-s16}                       \n" /* Store hardware saved FP context. */
+            "    sub r2, r2, #0x20                            \n" /* Set r2 back to the location of hardware saved context. */
+        #endif /* configENABLE_FPU || configENABLE_MVE */
             "    stmia r1!, {r4-r11}                          \n" /* Store r4-r11. */
             "    ldmia r2, {r4-r11}                           \n" /* Copy the hardware saved context into r4-r11. */
             "    stmia r1!, {r4-r11}                          \n" /* Store the hardware saved context. */
@@ -279,6 +295,14 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    mrs r3, psplim                               \n" /* r3 = PSPLIM. */
             "    mrs r4, control                              \n" /* r4 = CONTROL. */
             "    stmia r1!, {r2-r4, lr}                       \n" /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
+        #if ( configENABLE_PAC == 1 )
+            "   mrs  r2, PAC_KEY_P_0                          \n" /* Read task's dedicated PAC key from the PAC key registers. */
+            "   mrs  r3, PAC_KEY_P_1                          \n"
+            "   mrs  r4, PAC_KEY_P_2                          \n"
+            "   mrs  r5, PAC_KEY_P_3                          \n"
+            "   stmia r1!, {r2-r5}                            \n" /* Store the task's dedicated PAC key on the task's context. */
+            "   clrm {r2-r5}                                  \n" /* Clear r2-r5. */
+        #endif /* configENABLE_PAC */
             "    str r1, [r0]                                 \n" /* Save the location from where the context should be restored as the first member of TCB. */
             "                                                 \n"
             " select_next_task:                               \n"
@@ -314,16 +338,16 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
             "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
             "                                                 \n"
-            #if ( configTOTAL_MPU_REGIONS == 16 )
-                "    movs r3, #8                                  \n" /* r3 = 8. */
-                "    str r3, [r1]                                 \n" /* Program RNR = 8. */
-                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-                "    movs r3, #12                                 \n" /* r3 = 12. */
-                "    str r3, [r1]                                 \n" /* Program RNR = 12. */
-                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-            #endif /* configTOTAL_MPU_REGIONS == 16 */
+        #if ( configTOTAL_MPU_REGIONS == 16 )
+            "    movs r3, #8                                  \n" /* r3 = 8. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 8. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "    movs r3, #12                                 \n" /* r3 = 12. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 12. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+        #endif /* configTOTAL_MPU_REGIONS == 16 */
             "                                                 \n"
             "   ldr r1, =0xe000ed94                           \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
@@ -337,6 +361,14 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
             "                                                 \n"
             " restore_special_regs:                           \n"
+        #if ( configENABLE_PAC == 1 )
+            "   ldmdb r1!, {r2-r5}                            \n" /* Read task's dedicated PAC key from the task's context. */
+            "   msr  PAC_KEY_P_0, r2                          \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+            "   msr  PAC_KEY_P_1, r3                          \n"
+            "   msr  PAC_KEY_P_2, r4                          \n"
+            "   msr  PAC_KEY_P_3, r5                          \n"
+            "   clrm {r2-r5}                                  \n" /* Clear r2-r5. */
+        #endif /* configENABLE_PAC */
             "    ldmdb r1!, {r2-r4, lr}                       \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
             "    msr psp, r2                                  \n"
             "    msr psplim, r3                               \n"
@@ -346,13 +378,13 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
             "    stmia r2!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
             "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 restored. */
-            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-                "    tst lr, #0x10                                \n"
-                "    ittt eq                                      \n"
-                "    vldmdbeq r1!, {s0-s16}                       \n" /* s0-s16 contain hardware saved FP context. */
-                "    vstmiaeq r2!, {s0-s16}                       \n" /* Copy hardware saved FP context on the task stack. */
-                "    vldmdbeq r1!, {s16-s31}                      \n" /* Restore s16-s31. */
-            #endif /* configENABLE_FPU || configENABLE_MVE */
+        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            "    tst lr, #0x10                                \n"
+            "    ittt eq                                      \n"
+            "    vldmdbeq r1!, {s0-s16}                       \n" /* s0-s16 contain hardware saved FP context. */
+            "    vstmiaeq r2!, {s0-s16}                       \n" /* Copy hardware saved FP context on the task stack. */
+            "    vldmdbeq r1!, {s16-s31}                      \n" /* Restore s16-s31. */
+        #endif /* configENABLE_FPU || configENABLE_MVE */
             "                                                 \n"
             " restore_context_done:                           \n"
             "    str r1, [r0]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
@@ -371,16 +403,25 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "                                                   \n"
             "   mrs r0, psp                                     \n" /* Read PSP in r0. */
             "                                                   \n"
-            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-                "   tst lr, #0x10                                   \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
-                "   it eq                                           \n"
-                "   vstmdbeq r0!, {s16-s31}                         \n" /* Store the additional FP context registers which are not saved automatically. */
-            #endif /* configENABLE_FPU || configENABLE_MVE */
+        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            "   tst lr, #0x10                                   \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+            "   it eq                                           \n"
+            "   vstmdbeq r0!, {s16-s31}                         \n" /* Store the additional FP context registers which are not saved automatically. */
+        #endif /* configENABLE_FPU || configENABLE_MVE */
             "                                                   \n"
             "   mrs r2, psplim                                  \n" /* r2 = PSPLIM. */
             "   mov r3, lr                                      \n" /* r3 = LR/EXC_RETURN. */
             "   stmdb r0!, {r2-r11}                             \n" /* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */
             "                                                   \n"
+        #if ( configENABLE_PAC == 1 )
+            "   mrs  r1, PAC_KEY_P_3                            \n" /* Read task's dedicated PAC key from the PAC key registers. */
+            "   mrs  r2, PAC_KEY_P_2                            \n"
+            "   mrs  r3, PAC_KEY_P_1                            \n"
+            "   mrs  r4, PAC_KEY_P_0                            \n"
+            "   stmdb r0!, {r1-r4}                              \n" /* Store the task's dedicated PAC key on the stack. */
+            "   clrm {r1-r4}                                    \n" /* Clear r1-r4. */
+        #endif /* configENABLE_PAC */
+            "                                                   \n"
             "   ldr r2, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr r1, [r2]                                    \n" /* Read pxCurrentTCB. */
             "   str r0, [r1]                                    \n" /* Save the new top of stack in TCB. */
@@ -397,13 +438,22 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   ldr r1, [r2]                                    \n" /* Read pxCurrentTCB. */
             "   ldr r0, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
             "                                                   \n"
+        #if ( configENABLE_PAC == 1 )
+            "   ldmia r0!, {r2-r5}                              \n" /* Read task's dedicated PAC key from stack. */
+            "   msr  PAC_KEY_P_3, r2                            \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+            "   msr  PAC_KEY_P_2, r3                            \n"
+            "   msr  PAC_KEY_P_1, r4                            \n"
+            "   msr  PAC_KEY_P_0, r5                            \n"
+            "   clrm {r2-r5}                                    \n" /* Clear r2-r5. */
+        #endif /* configENABLE_PAC */
+            "                                                   \n"
             "   ldmia r0!, {r2-r11}                             \n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
             "                                                   \n"
-            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-                "   tst r3, #0x10                                   \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
-                "   it eq                                           \n"
-                "   vldmiaeq r0!, {s16-s31}                         \n" /* Restore the additional FP context registers which are not restored automatically. */
-            #endif /* configENABLE_FPU || configENABLE_MVE */
+        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            "   tst r3, #0x10                                   \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+            "   it eq                                           \n"
+            "   vldmiaeq r0!, {s16-s31}                         \n" /* Restore the additional FP context registers which are not restored automatically. */
+        #endif /* configENABLE_FPU || configENABLE_MVE */
             "                                                   \n"
             "   msr psplim, r2                                  \n" /* Restore the PSPLIM register value for the task. */
             "   msr psp, r0                                     \n" /* Remember the new top of stack for the task. */
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h b/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h
index 0fc61f23c..2d435ca0b 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h
@@ -60,7 +60,7 @@
 
 #ifndef configENABLE_MVE
     #define configENABLE_MVE    0
-#elif( configENABLE_MVE != 0 )
+#elif ( configENABLE_MVE != 0 )
     #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M33.
 #endif
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h
index 8a8dc7d6a..e74fa8257 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -125,6 +127,18 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
     extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
 #endif /* configENABLE_MPU */
+
+#if ( configENABLE_PAC == 1 )
+
+    /**
+     * @brief Generates 128-bit task's random PAC key.
+     *
+     * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be
+     *             filled with a 128-bit random number.
+     */
+    void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey );
+
+#endif /* configENABLE_PAC */
 /*-----------------------------------------------------------*/
 
 /**
@@ -188,9 +202,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Settings to define an MPU region.
- */
+    /**
+     * @brief Settings to define an MPU region.
+     */
     typedef struct MPURegionSettings
     {
         uint32_t ulRBAR; /**< RBAR for the region. */
@@ -203,9 +217,14 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-/**
- * @brief System call stack.
- */
+        /* When MPU wrapper v2 is used, the task's context is stored in TCB and
+         * pxTopOfStack member of TCB points to the context location in TCB. We,
+         * therefore, need to read PSP to find the task's current top of stack. */
+        #define portGET_CURRENT_TOP_OF_STACK( pxCurrentTopOfStack ) { __asm volatile ( "mrs %0, psp"  : "=r" ( pxCurrentTopOfStack ) ); }
+
+        /**
+         * @brief System call stack.
+         */
         typedef struct SYSTEM_CALL_STACK_INFO
         {
             uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ];
@@ -218,76 +237,128 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
-/**
- * @brief MPU settings as stored in the TCB.
- */
+    /**
+     * @brief MPU settings as stored in the TCB.
+     */
     #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+        #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +-----------+---------------+----------+-----------------+------------------------------+-----+
- * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
- * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
- * +-----------+---------------+----------+-----------------+------------------------------+-----+
- *
- * <-----------><--------------><---------><----------------><-----------------------------><---->
- *      16             16            8               8                     5                   1
- */
+            /*
+             * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey |     |
+             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |            |     |
+             * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
+             *      16             16            8               8                     5                     16         1
+             */
+            #define MAX_CONTEXT_SIZE    70
+
+        #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
+
+            /*
+             * +-----------+---------------+----------+-----------------+------------------------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+             * +-----------+---------------+----------+-----------------+------------------------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><-----------------------------><---->
+             *      16             16            8               8                     5                   1
+             */
             #define MAX_CONTEXT_SIZE    54
 
-        #else /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +-----------+---------------+----------+-----------------+----------------------+-----+
- * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
- * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
- * +-----------+---------------+----------+-----------------+----------------------+-----+
- *
- * <-----------><--------------><---------><----------------><---------------------><---->
- *      16             16            8               8                  4              1
- */
+            /*
+             * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey |     |
+             * |           |               |          | PC, xPSR        | EXC_RETURN           |            |     |
+             * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><---------------------><-----------><---->
+             *      16             16            8               8                  4                16         1
+             */
+            #define MAX_CONTEXT_SIZE    69
+
+        #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
+
+            /*
+             * +-----------+---------------+----------+-----------------+----------------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+             * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
+             * +-----------+---------------+----------+-----------------+----------------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><---------------------><---->
+             *      16             16            8               8                  4              1
+             */
             #define MAX_CONTEXT_SIZE    53
 
-        #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
     #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+        #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +----------+-----------------+------------------------------+-----+
- * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
- * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
- * +----------+-----------------+------------------------------+-----+
- *
- * <---------><----------------><------------------------------><---->
- *     8               8                      5                   1
- */
+            /*
+             * +----------+-----------------+------------------------------+------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey |     |
+             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |            |     |
+             * +----------+-----------------+------------------------------+------------+-----+
+             *
+             * <---------><----------------><------------------------------><-----------><---->
+             *     8               8                      5                      16         1
+             */
+            #define MAX_CONTEXT_SIZE    38
+
+        #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
+
+            /*
+             * +----------+-----------------+------------------------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+             * +----------+-----------------+------------------------------+-----+
+             *
+             * <---------><----------------><------------------------------><---->
+             *     8               8                      5                   1
+             */
             #define MAX_CONTEXT_SIZE    22
 
+        #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+            /*
+             * +----------+-----------------+----------------------+------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey |     |
+             * |          | PC, xPSR        | EXC_RETURN           |            |     |
+             * +----------+-----------------+----------------------+------------+-----+
+             *
+             * <---------><----------------><----------------------><-----------><---->
+             *     8               8                  4                  16         1
+             */
+            #define MAX_CONTEXT_SIZE    37
+
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-/*
- * +----------+-----------------+----------------------+-----+
- * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
- * |          | PC, xPSR        | EXC_RETURN           |     |
- * +----------+-----------------+----------------------+-----+
- *
- * <---------><----------------><----------------------><---->
- *     8               8                  4              1
- */
+            /*
+             * +----------+-----------------+----------------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+             * |          | PC, xPSR        | EXC_RETURN           |     |
+             * +----------+-----------------+----------------------+-----+
+             *
+             * <---------><----------------><----------------------><---->
+             *     8               8                  4              1
+             */
             #define MAX_CONTEXT_SIZE    21
 
-        #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
     #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
+    /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
-/* Size of an Access Control List (ACL) entry in bits. */
+    /* Size of an Access Control List (ACL) entry in bits. */
     #define portACL_ENTRY_SIZE_BITS             ( 32U )
 
     typedef struct MPU_SETTINGS
diff --git a/portable/GCC/ARM_CM35P/non_secure/port.c b/portable/GCC/ARM_CM35P/non_secure/port.c
index aa9c23816..b2fd7e518 100644
--- a/portable/GCC/ARM_CM35P/non_secure/port.c
+++ b/portable/GCC/ARM_CM35P/non_secure/port.c
@@ -169,79 +169,80 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                            ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                            ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                             ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                            ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                            ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                           ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                           ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK        ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                      ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK                     ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                      ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK                     ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                      ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK                     ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                      ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK                     ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                      ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK                     ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                      ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK                     ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                      ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK                     ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                      ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK                     ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0                    ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1                    ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2                    ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3                    ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4                    ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5                    ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6                    ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7                    ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE                  ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
 
 #if ( portARMV8M_MINOR_VERSION >= 1 )
-    /* Enable Privileged eXecute Never MPU attribute for the selected memory
-     * region. */
-    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER   ( 1UL << 4UL )
+
+/* Enable Privileged eXecute Never MPU attribute for the selected memory
+ * region. */
+    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER    ( 1UL << 4UL )
 #endif /* portARMV8M_MINOR_VERSION >= 1 */
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT          ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                          ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE                 ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -380,14 +381,14 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to check and configure PACBTI security feature implementation.
  */
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
-    #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
+    #define portID_ISAR5_REG       ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
 
-    #define portCONTROL_UPAC_EN      ( 1UL << 7UL )
-    #define portCONTROL_PAC_EN       ( 1UL << 6UL )
-    #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
-    #define portCONTROL_BTI_EN       ( 1UL << 4UL )
+    #define portCONTROL_UPAC_EN    ( 1UL << 7UL )
+    #define portCONTROL_PAC_EN     ( 1UL << 6UL )
+    #define portCONTROL_UBTI_EN    ( 1UL << 5UL )
+    #define portCONTROL_BTI_EN     ( 1UL << 4UL )
 
 #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
@@ -409,7 +410,7 @@ static void prvTaskExitError( void );
  * @return uint32_t Access permissions.
  */
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0  */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 
 #if ( configENABLE_MPU == 1 )
 
@@ -427,7 +428,7 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
 /**
  * @brief Configures PACBTI features.
@@ -890,7 +891,7 @@ static void prvTaskExitError( void )
         return ulAccessPermissions;
     }
 
-#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0  */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
@@ -1212,6 +1213,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
+
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __syscalls_flash_start__;
@@ -1282,6 +1284,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
              * point (i.e. the caller of the MPU_<API>). We need to restore it
              * when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+
             /* Store the value of the PSPLIM register before the SVC was raised.
              * We need to restore it when we exit from the system call. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
@@ -1300,6 +1303,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
             /* Start executing the system call upon returning from this handler. */
             pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
+
             /* Raise a request to exit from the system call upon finishing the
              * system call. */
             pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit;
@@ -1359,6 +1363,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
+
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __privileged_functions_start__;
@@ -1541,7 +1546,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
-        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+        #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
         {
             /* Check PACBTI security feature configuration before pushing the
              * CONTROL register's value on task's TCB. */
@@ -1582,6 +1587,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
+        #if ( configENABLE_PAC == 1 )
+        {
+            uint32_t ulTaskPacKey[ 4 ], i;
+
+            vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+            for( i = 0; i < 4; i++ )
+            {
+                xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ];
+                ulIndex++;
+            }
+        }
+        #endif /* configENABLE_PAC */
+
         return &( xMPUSettings->ulContext[ ulIndex ] );
     }
 
@@ -1664,6 +1683,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #endif /* portPRELOAD_REGISTERS */
 
+        #if ( configENABLE_PAC == 1 )
+        {
+            uint32_t ulTaskPacKey[ 4 ], i;
+
+            vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+            for( i = 0; i < 4; i++ )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = ulTaskPacKey[ i ];
+            }
+        }
+        #endif /* configENABLE_PAC */
+
         return pxTopOfStack;
     }
 
@@ -1786,11 +1819,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
-    #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+    #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
     {
         /* Set the CONTROL register value based on PACBTI security feature
          * configuration before starting the first task. */
-        ( void) prvConfigurePACBTI( pdTRUE );
+        ( void ) prvConfigurePACBTI( pdTRUE );
     }
     #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
@@ -1990,9 +2023,9 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
         if( xSchedulerRunning == pdFALSE )
         {
             /* Grant access to all the kernel objects before the scheduler
-            * is started. It is necessary because there is no task running
-            * yet and therefore, we cannot use the permissions of any
-            * task. */
+             * is started. It is necessary because there is no task running
+             * yet and therefore, we cannot use the permissions of any
+             * task. */
             xAccessGranted = pdTRUE;
         }
         else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
@@ -2213,7 +2246,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
 
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
     {
@@ -2225,13 +2258,13 @@ BaseType_t xPortIsInsideInterrupt( void )
         /* Enable UsageFault exception. */
         portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
 
-        #if( configENABLE_PAC == 1 )
+        #if ( configENABLE_PAC == 1 )
         {
             ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
         }
         #endif
 
-        #if( configENABLE_BTI == 1 )
+        #if ( configENABLE_BTI == 1 )
         {
             ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
         }
diff --git a/portable/GCC/ARM_CM35P/non_secure/portasm.c b/portable/GCC/ARM_CM35P/non_secure/portasm.c
index aaeccaa35..0ebbe48a4 100644
--- a/portable/GCC/ARM_CM35P/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM35P/non_secure/portasm.c
@@ -77,16 +77,16 @@
             "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
             "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
             "                                                 \n"
-            #if ( configTOTAL_MPU_REGIONS == 16 )
-                "    movs r3, #8                                  \n" /* r3 = 8. */
-                "    str r3, [r1]                                 \n" /* Program RNR = 8. */
-                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
-                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-                "    movs r3, #12                                 \n" /* r3 = 12. */
-                "    str r3, [r1]                                 \n" /* Program RNR = 12. */
-                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
-                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-            #endif /* configTOTAL_MPU_REGIONS == 16 */
+        #if ( configTOTAL_MPU_REGIONS == 16 )
+            "    movs r3, #8                                  \n" /* r3 = 8. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 8. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "    movs r3, #12                                 \n" /* r3 = 12. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 12. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+        #endif /* configTOTAL_MPU_REGIONS == 16 */
             "                                                 \n"
             "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
@@ -100,6 +100,14 @@
             "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
             "                                                 \n"
             " restore_special_regs_first_task:                \n"
+        #if ( configENABLE_PAC == 1 )
+            "   ldmdb r2!, {r3-r6}                            \n" /* Read task's dedicated PAC key from the task's context. */
+            "   msr  PAC_KEY_P_0, r3                          \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+            "   msr  PAC_KEY_P_1, r4                          \n"
+            "   msr  PAC_KEY_P_2, r5                          \n"
+            "   msr  PAC_KEY_P_3, r6                          \n"
+            "   clrm {r3-r6}                                  \n" /* Clear r3-r6. */
+        #endif /* configENABLE_PAC */
             "    ldmdb r2!, {r0, r3-r5, lr}                   \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
             "    msr psp, r3                                  \n"
             "    msr psplim, r4                               \n"
@@ -132,6 +140,15 @@
             "   ldr  r3, [r2]                                   \n" /* Read pxCurrentTCB. */
             "   ldr  r0, [r3]                                   \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
             "                                                   \n"
+        #if ( configENABLE_PAC == 1 )
+            "   ldmia r0!, {r1-r4}                              \n" /* Read task's dedicated PAC key from stack. */
+            "   msr  PAC_KEY_P_3, r1                            \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+            "   msr  PAC_KEY_P_2, r2                            \n"
+            "   msr  PAC_KEY_P_1, r3                            \n"
+            "   msr  PAC_KEY_P_0, r4                            \n"
+            "   clrm {r1-r4}                                    \n" /* Clear r1-r4. */
+        #endif /* configENABLE_PAC */
+            "                                                   \n"
             "   ldm  r0!, {r1-r3}                               \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
             "   ldr  r4, =xSecureContext                        \n"
             "   str  r1, [r4]                                   \n" /* Set xSecureContext to this task's value for the same. */
@@ -280,17 +297,15 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "                                                 \n"
             " save_general_regs:                              \n"
             "    mrs r3, psp                                  \n"
-            "                                                 \n"
-            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-                "    add r3, r3, #0x20                            \n" /* Move r3 to location where s0 is saved. */
-                "    tst lr, #0x10                                \n"
-                "    ittt eq                                      \n"
-                "    vstmiaeq r2!, {s16-s31}                      \n" /* Store s16-s31. */
-                "    vldmiaeq r3, {s0-s16}                        \n" /* Copy hardware saved FP context into s0-s16. */
-                "    vstmiaeq r2!, {s0-s16}                       \n" /* Store hardware saved FP context. */
-                "    sub r3, r3, #0x20                            \n" /* Set r3 back to the location of hardware saved context. */
-            #endif /* configENABLE_FPU || configENABLE_MVE */
-            "                                                 \n"
+        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            "    add r3, r3, #0x20                            \n" /* Move r3 to location where s0 is saved. */
+            "    tst lr, #0x10                                \n"
+            "    ittt eq                                      \n"
+            "    vstmiaeq r2!, {s16-s31}                      \n" /* Store s16-s31. */
+            "    vldmiaeq r3, {s0-s16}                        \n" /* Copy hardware saved FP context into s0-s16. */
+            "    vstmiaeq r2!, {s0-s16}                       \n" /* Store hardware saved FP context. */
+            "    sub r3, r3, #0x20                            \n" /* Set r3 back to the location of hardware saved context. */
+        #endif /* configENABLE_FPU || configENABLE_MVE */
             "    stmia r2!, {r4-r11}                          \n" /* Store r4-r11. */
             "    ldmia r3, {r4-r11}                           \n" /* Copy the hardware saved context into r4-r11. */
             "    stmia r2!, {r4-r11}                          \n" /* Store the hardware saved context. */
@@ -300,7 +315,15 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    mrs r4, psplim                               \n" /* r4 = PSPLIM. */
             "    mrs r5, control                              \n" /* r5 = CONTROL. */
             "    stmia r2!, {r0, r3-r5, lr}                   \n" /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
-            "    str r2, [r1]                                 \n" /* Save the location from where the context should be restored as the first member of TCB. */
+        #if ( configENABLE_PAC == 1 )
+            "   mrs  r3, PAC_KEY_P_0                          \n" /* Read task's dedicated PAC key from the PAC key registers. */
+            "   mrs  r4, PAC_KEY_P_1                          \n"
+            "   mrs  r5, PAC_KEY_P_2                          \n"
+            "   mrs  r6, PAC_KEY_P_3                          \n"
+            "   stmia r2!, {r3-r6}                            \n" /* Store the task's dedicated PAC key on the task's context. */
+            "   clrm {r3-r6}                                  \n" /* Clear r3-r6. */
+        #endif /* configENABLE_PAC */
+            "    str r2, [r1]                                 \n"      /* Save the location from where the context should be restored as the first member of TCB. */
             "                                                 \n"
             " select_next_task:                               \n"
             "    mov r0, %0                                   \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
@@ -335,16 +358,16 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
             "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
             "                                                 \n"
-            #if ( configTOTAL_MPU_REGIONS == 16 )
-                "    movs r3, #8                                  \n" /* r3 = 8. */
-                "    str r3, [r1]                                 \n" /* Program RNR = 8. */
-                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-                "    movs r3, #12                                 \n" /* r3 = 12. */
-                "    str r3, [r1]                                 \n" /* Program RNR = 12. */
-                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-            #endif /* configTOTAL_MPU_REGIONS == 16 */
+        #if ( configTOTAL_MPU_REGIONS == 16 )
+            "    movs r3, #8                                  \n" /* r3 = 8. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 8. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "    movs r3, #12                                 \n" /* r3 = 12. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 12. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+        #endif /* configTOTAL_MPU_REGIONS == 16 */
             "                                                 \n"
             "   ldr r1, =0xe000ed94                           \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
@@ -358,6 +381,14 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
             "                                                 \n"
             " restore_special_regs:                           \n"
+        #if ( configENABLE_PAC == 1 )
+            "   ldmdb r2!, {r3-r6}                            \n" /* Read task's dedicated PAC key from the task's context. */
+            "   msr  PAC_KEY_P_0, r3                          \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+            "   msr  PAC_KEY_P_1, r4                          \n"
+            "   msr  PAC_KEY_P_2, r5                          \n"
+            "   msr  PAC_KEY_P_3, r6                          \n"
+            "   clrm {r3-r6}                                  \n" /* Clear r3-r6. */
+        #endif /* configENABLE_PAC */
             "    ldmdb r2!, {r0, r3-r5, lr}                   \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
             "    msr psp, r3                                  \n"
             "    msr psplim, r4                               \n"
@@ -380,13 +411,13 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
             "    stmia r3!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
             "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 restored. */
-            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-                "    tst lr, #0x10                                \n"
-                "    ittt eq                                      \n"
-                "    vldmdbeq r2!, {s0-s16}                       \n" /* s0-s16 contain hardware saved FP context. */
-                "    vstmiaeq r3!, {s0-s16}                       \n" /* Copy hardware saved FP context on the task stack. */
-                "    vldmdbeq r2!, {s16-s31}                      \n" /* Restore s16-s31. */
-            #endif /* configENABLE_FPU || configENABLE_MVE */
+        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            "    tst lr, #0x10                                \n"
+            "    ittt eq                                      \n"
+            "    vldmdbeq r2!, {s0-s16}                       \n" /* s0-s16 contain hardware saved FP context. */
+            "    vstmiaeq r3!, {s0-s16}                       \n" /* Copy hardware saved FP context on the task stack. */
+            "    vldmdbeq r2!, {s16-s31}                      \n" /* Restore s16-s31. */
+        #endif /* configENABLE_FPU || configENABLE_MVE */
             "                                                 \n"
             " restore_context_done:                           \n"
             "    str r2, [r1]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
@@ -401,89 +432,99 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
     {
         __asm volatile
         (
-            "   .syntax unified                                 \n"
-            "   .extern SecureContext_SaveContext               \n"
-            "   .extern SecureContext_LoadContext               \n"
-            "                                                   \n"
-            "   ldr r3, =xSecureContext                         \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-            "   ldr r0, [r3]                                    \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
-            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
-            "   mrs r2, psp                                     \n" /* Read PSP in r2. */
-            "                                                   \n"
-            "   cbz r0, save_ns_context                         \n" /* No secure context to save. */
-            "   push {r0-r2, r14}                               \n"
-            "   bl SecureContext_SaveContext                    \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-            "   pop {r0-r3}                                     \n" /* LR is now in r3. */
-            "   mov lr, r3                                      \n" /* LR = r3. */
-            "   lsls r1, r3, #25                                \n" /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-            "   bpl save_ns_context                             \n" /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-            "                                                   \n"
-            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB.*/
-            "   subs r2, r2, #12                                \n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */
-            "   str r2, [r1]                                    \n" /* Save the new top of stack in TCB. */
-            "   mrs r1, psplim                                  \n" /* r1 = PSPLIM. */
-            "   mov r3, lr                                      \n" /* r3 = LR/EXC_RETURN. */
-            "   stmia r2!, {r0, r1, r3}                         \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
-            "   b select_next_task                              \n"
-            "                                                   \n"
-            " save_ns_context:                                  \n"
-            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
-            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-                "   tst lr, #0x10                               \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
-                "   it eq                                       \n"
-                "   vstmdbeq r2!, {s16-s31}                     \n" /* Store the additional FP context registers which are not saved automatically. */
-            #endif /* configENABLE_FPU || configENABLE_MVE */
-            "   subs r2, r2, #44                                \n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
-            "   str r2, [r1]                                    \n" /* Save the new top of stack in TCB. */
-            "   adds r2, r2, #12                                \n" /* r2 = r2 + 12. */
-            "   stm r2, {r4-r11}                                \n" /* Store the registers that are not saved automatically. */
-            "   mrs r1, psplim                                  \n" /* r1 = PSPLIM. */
-            "   mov r3, lr                                      \n" /* r3 = LR/EXC_RETURN. */
-            "   subs r2, r2, #12                                \n" /* r2 = r2 - 12. */
-            "   stmia r2!, {r0, r1, r3}                         \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
-            "                                                   \n"
-            " select_next_task:                                 \n"
-            "   mov r0, %0                                      \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
-            "   msr basepri, r0                                 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-            "   dsb                                             \n"
-            "   isb                                             \n"
-            "   bl vTaskSwitchContext                           \n"
-            "   mov r0, #0                                      \n" /* r0 = 0. */
-            "   msr basepri, r0                                 \n" /* Enable interrupts. */
-            "                                                   \n"
-            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
-            "   ldr r2, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
-            "                                                   \n"
-            "   ldmia r2!, {r0, r1, r4}                         \n" /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
-            "   msr psplim, r1                                  \n" /* Restore the PSPLIM register value for the task. */
-            "   mov lr, r4                                      \n" /* LR = r4. */
-            "   ldr r3, =xSecureContext                         \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-            "   str r0, [r3]                                    \n" /* Restore the task's xSecureContext. */
-            "   cbz r0, restore_ns_context                      \n" /* If there is no secure context for the task, restore the non-secure context. */
-            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
-            "   push {r2, r4}                                   \n"
-            "   bl SecureContext_LoadContext                    \n" /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-            "   pop {r2, r4}                                    \n"
-            "   mov lr, r4                                      \n" /* LR = r4. */
-            "   lsls r1, r4, #25                                \n" /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-            "   bpl restore_ns_context                          \n" /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-            "   msr psp, r2                                     \n" /* Remember the new top of stack for the task. */
-            "   bx lr                                           \n"
-            "                                                   \n"
-            " restore_ns_context:                               \n"
-            "   ldmia r2!, {r4-r11}                             \n" /* Restore the registers that are not automatically restored. */
-            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-                "   tst lr, #0x10                               \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
-                "   it eq                                       \n"
-                "   vldmiaeq r2!, {s16-s31}                     \n" /* Restore the additional FP context registers which are not restored automatically. */
-            #endif /* configENABLE_FPU || configENABLE_MVE */
-            "   msr psp, r2                                     \n" /* Remember the new top of stack for the task. */
-            "   bx lr                                           \n"
+            " .syntax unified                                 \n"
+            " .extern SecureContext_SaveContext               \n"
+            " .extern SecureContext_LoadContext               \n"
+            "                                                 \n"
+            " ldr r3, =xSecureContext                         \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            " ldr r0, [r3]                                    \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+            " ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            " ldr r1, [r3]                                    \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
+            " mrs r2, psp                                     \n" /* Read PSP in r2. */
+            "                                                 \n"
+            " cbz r0, save_ns_context                         \n" /* No secure context to save. */
+            " save_s_context:                                 \n"
+            "    push {r0-r2, lr}                             \n"
+            "    bl SecureContext_SaveContext                 \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+            "    pop {r0-r2, lr}                              \n"
+            "                                                 \n"
+            " save_ns_context:                                \n"
+            "    mov r3, lr                                   \n" /* r3 = LR (EXC_RETURN). */
+            "    lsls r3, r3, #25                             \n" /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+            "    bmi save_special_regs                        \n" /* If r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used. */
+            "                                                 \n"
+            " save_general_regs:                              \n"
+        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            "    tst lr, #0x10                                \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+            "    it eq                                        \n"
+            "    vstmdbeq r2!, {s16-s31}                      \n" /* Store the additional FP context registers which are not saved automatically. */
+        #endif /* configENABLE_FPU || configENABLE_MVE */
+            "   stmdb r2!, {r4-r11}                           \n" /* Store the registers that are not saved automatically. */
+            "                                                 \n"
+            " save_special_regs:                              \n"
+            "    mrs r3, psplim                               \n" /* r3 = PSPLIM. */
+            "    stmdb r2!, {r0, r3, lr}                      \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
+        #if ( configENABLE_PAC == 1 )
+            "    mrs  r3, PAC_KEY_P_3                         \n" /* Read task's dedicated PAC key from the PAC key registers. */
+            "    mrs  r4, PAC_KEY_P_2                         \n"
+            "    mrs  r5, PAC_KEY_P_1                         \n"
+            "    mrs  r6, PAC_KEY_P_0                         \n"
+            "    stmdb r2!, {r3-r6}                           \n" /* Store the task's dedicated PAC key on the stack. */
+            "    clrm {r3-r6}                                 \n" /* Clear r3-r6. */
+        #endif /* configENABLE_PAC */
+            "                                                 \n"
+            " str r2, [r1]                                    \n" /* Save the new top of stack in TCB. */
+            "                                                 \n"
+            " select_next_task:                               \n"
+            "    mov r0, %0                                   \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
+            "    msr basepri, r0                              \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+            "    dsb                                          \n"
+            "    isb                                          \n"
+            "    bl vTaskSwitchContext                        \n"
+            "    mov r0, #0                                   \n" /* r0 = 0. */
+            "    msr basepri, r0                              \n" /* Enable interrupts. */
+            "                                                 \n"
+            " restore_context:                                \n"
+            "    ldr r3, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r1, [r3]                                 \n" /* Read pxCurrentTCB. */
+            "    ldr r2, [r1]                                 \n" /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
+            "                                                 \n"
+            " restore_special_regs:                           \n"
+        #if ( configENABLE_PAC == 1 )
+            "    ldmia r2!, {r3-r6}                           \n" /* Read task's dedicated PAC key from stack. */
+            "    msr  PAC_KEY_P_3, r3                         \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+            "    msr  PAC_KEY_P_2, r4                         \n"
+            "    msr  PAC_KEY_P_1, r5                         \n"
+            "    msr  PAC_KEY_P_0, r6                         \n"
+            "    clrm {r3-r6}                                 \n" /* Clear r3-r6. */
+        #endif /* configENABLE_PAC */
+            "    ldmia r2!, {r0, r3, lr}                      \n" /* Read from stack - r0 = xSecureContext, r3 = PSPLIM and LR restored. */
+            "    msr psplim, r3                               \n" /* Restore the PSPLIM register value for the task. */
+            "    ldr r3, =xSecureContext                      \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "    str r0, [r3]                                 \n" /* Restore the task's xSecureContext. */
+            "    cbz r0, restore_ns_context                   \n" /* If there is no secure context for the task, restore the non-secure context. */
+            "                                                 \n"
+            " restore_s_context:                              \n"
+            "    push {r1-r3, lr}                             \n"
+            "    bl SecureContext_LoadContext                 \n" /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+            "    pop {r1-r3, lr}                              \n"
+            "                                                 \n"
+            " restore_ns_context:                             \n"
+            "    mov r0, lr                                   \n" /* r0 = LR (EXC_RETURN). */
+            "    lsls r0, r0, #25                             \n" /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+            "    bmi restore_context_done                     \n" /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
+            "                                                 \n"
+            " restore_general_regs:                           \n"
+            "    ldmia r2!, {r4-r11}                          \n" /* Restore the registers that are not automatically restored. */
+        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            "   tst lr, #0x10                                 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+            "   it eq                                         \n"
+            "   vldmiaeq r2!, {s16-s31}                       \n" /* Restore the additional FP context registers which are not restored automatically. */
+        #endif /* configENABLE_FPU || configENABLE_MVE */
+            "                                                 \n"
+            " restore_context_done:                           \n"
+            "    msr psp, r2                                  \n" /* Remember the new top of stack for the task. */
+            "    bx lr                                        \n"
             ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
         );
     }
diff --git a/portable/GCC/ARM_CM35P/non_secure/portmacro.h b/portable/GCC/ARM_CM35P/non_secure/portmacro.h
index 4db6e6d4a..b886287ac 100644
--- a/portable/GCC/ARM_CM35P/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM35P/non_secure/portmacro.h
@@ -60,7 +60,7 @@
 
 #ifndef configENABLE_MVE
     #define configENABLE_MVE    0
-#elif( configENABLE_MVE != 0 )
+#elif ( configENABLE_MVE != 0 )
     #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M35.
 #endif
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h
index 8a8dc7d6a..e74fa8257 100644
--- a/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -125,6 +127,18 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
     extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
 #endif /* configENABLE_MPU */
+
+#if ( configENABLE_PAC == 1 )
+
+    /**
+     * @brief Generates 128-bit task's random PAC key.
+     *
+     * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be
+     *             filled with a 128-bit random number.
+     */
+    void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey );
+
+#endif /* configENABLE_PAC */
 /*-----------------------------------------------------------*/
 
 /**
@@ -188,9 +202,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Settings to define an MPU region.
- */
+    /**
+     * @brief Settings to define an MPU region.
+     */
     typedef struct MPURegionSettings
     {
         uint32_t ulRBAR; /**< RBAR for the region. */
@@ -203,9 +217,14 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-/**
- * @brief System call stack.
- */
+        /* When MPU wrapper v2 is used, the task's context is stored in TCB and
+         * pxTopOfStack member of TCB points to the context location in TCB. We,
+         * therefore, need to read PSP to find the task's current top of stack. */
+        #define portGET_CURRENT_TOP_OF_STACK( pxCurrentTopOfStack ) { __asm volatile ( "mrs %0, psp"  : "=r" ( pxCurrentTopOfStack ) ); }
+
+        /**
+         * @brief System call stack.
+         */
         typedef struct SYSTEM_CALL_STACK_INFO
         {
             uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ];
@@ -218,76 +237,128 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
-/**
- * @brief MPU settings as stored in the TCB.
- */
+    /**
+     * @brief MPU settings as stored in the TCB.
+     */
     #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+        #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +-----------+---------------+----------+-----------------+------------------------------+-----+
- * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
- * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
- * +-----------+---------------+----------+-----------------+------------------------------+-----+
- *
- * <-----------><--------------><---------><----------------><-----------------------------><---->
- *      16             16            8               8                     5                   1
- */
+            /*
+             * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey |     |
+             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |            |     |
+             * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
+             *      16             16            8               8                     5                     16         1
+             */
+            #define MAX_CONTEXT_SIZE    70
+
+        #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
+
+            /*
+             * +-----------+---------------+----------+-----------------+------------------------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+             * +-----------+---------------+----------+-----------------+------------------------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><-----------------------------><---->
+             *      16             16            8               8                     5                   1
+             */
             #define MAX_CONTEXT_SIZE    54
 
-        #else /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +-----------+---------------+----------+-----------------+----------------------+-----+
- * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
- * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
- * +-----------+---------------+----------+-----------------+----------------------+-----+
- *
- * <-----------><--------------><---------><----------------><---------------------><---->
- *      16             16            8               8                  4              1
- */
+            /*
+             * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey |     |
+             * |           |               |          | PC, xPSR        | EXC_RETURN           |            |     |
+             * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><---------------------><-----------><---->
+             *      16             16            8               8                  4                16         1
+             */
+            #define MAX_CONTEXT_SIZE    69
+
+        #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
+
+            /*
+             * +-----------+---------------+----------+-----------------+----------------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+             * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
+             * +-----------+---------------+----------+-----------------+----------------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><---------------------><---->
+             *      16             16            8               8                  4              1
+             */
             #define MAX_CONTEXT_SIZE    53
 
-        #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
     #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+        #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +----------+-----------------+------------------------------+-----+
- * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
- * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
- * +----------+-----------------+------------------------------+-----+
- *
- * <---------><----------------><------------------------------><---->
- *     8               8                      5                   1
- */
+            /*
+             * +----------+-----------------+------------------------------+------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey |     |
+             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |            |     |
+             * +----------+-----------------+------------------------------+------------+-----+
+             *
+             * <---------><----------------><------------------------------><-----------><---->
+             *     8               8                      5                      16         1
+             */
+            #define MAX_CONTEXT_SIZE    38
+
+        #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
+
+            /*
+             * +----------+-----------------+------------------------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+             * +----------+-----------------+------------------------------+-----+
+             *
+             * <---------><----------------><------------------------------><---->
+             *     8               8                      5                   1
+             */
             #define MAX_CONTEXT_SIZE    22
 
+        #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+            /*
+             * +----------+-----------------+----------------------+------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey |     |
+             * |          | PC, xPSR        | EXC_RETURN           |            |     |
+             * +----------+-----------------+----------------------+------------+-----+
+             *
+             * <---------><----------------><----------------------><-----------><---->
+             *     8               8                  4                  16         1
+             */
+            #define MAX_CONTEXT_SIZE    37
+
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-/*
- * +----------+-----------------+----------------------+-----+
- * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
- * |          | PC, xPSR        | EXC_RETURN           |     |
- * +----------+-----------------+----------------------+-----+
- *
- * <---------><----------------><----------------------><---->
- *     8               8                  4              1
- */
+            /*
+             * +----------+-----------------+----------------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+             * |          | PC, xPSR        | EXC_RETURN           |     |
+             * +----------+-----------------+----------------------+-----+
+             *
+             * <---------><----------------><----------------------><---->
+             *     8               8                  4              1
+             */
             #define MAX_CONTEXT_SIZE    21
 
-        #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
     #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
+    /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
-/* Size of an Access Control List (ACL) entry in bits. */
+    /* Size of an Access Control List (ACL) entry in bits. */
     #define portACL_ENTRY_SIZE_BITS             ( 32U )
 
     typedef struct MPU_SETTINGS
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c b/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
index aa9c23816..b2fd7e518 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
@@ -169,79 +169,80 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                            ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                            ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                             ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                            ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                            ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                           ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                           ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK        ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                      ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK                     ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                      ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK                     ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                      ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK                     ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                      ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK                     ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                      ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK                     ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                      ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK                     ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                      ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK                     ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                      ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK                     ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0                    ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1                    ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2                    ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3                    ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4                    ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5                    ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6                    ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7                    ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE                  ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
 
 #if ( portARMV8M_MINOR_VERSION >= 1 )
-    /* Enable Privileged eXecute Never MPU attribute for the selected memory
-     * region. */
-    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER   ( 1UL << 4UL )
+
+/* Enable Privileged eXecute Never MPU attribute for the selected memory
+ * region. */
+    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER    ( 1UL << 4UL )
 #endif /* portARMV8M_MINOR_VERSION >= 1 */
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT          ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                          ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE                 ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -380,14 +381,14 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to check and configure PACBTI security feature implementation.
  */
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
-    #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
+    #define portID_ISAR5_REG       ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
 
-    #define portCONTROL_UPAC_EN      ( 1UL << 7UL )
-    #define portCONTROL_PAC_EN       ( 1UL << 6UL )
-    #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
-    #define portCONTROL_BTI_EN       ( 1UL << 4UL )
+    #define portCONTROL_UPAC_EN    ( 1UL << 7UL )
+    #define portCONTROL_PAC_EN     ( 1UL << 6UL )
+    #define portCONTROL_UBTI_EN    ( 1UL << 5UL )
+    #define portCONTROL_BTI_EN     ( 1UL << 4UL )
 
 #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
@@ -409,7 +410,7 @@ static void prvTaskExitError( void );
  * @return uint32_t Access permissions.
  */
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0  */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 
 #if ( configENABLE_MPU == 1 )
 
@@ -427,7 +428,7 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
 /**
  * @brief Configures PACBTI features.
@@ -890,7 +891,7 @@ static void prvTaskExitError( void )
         return ulAccessPermissions;
     }
 
-#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0  */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
@@ -1212,6 +1213,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
+
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __syscalls_flash_start__;
@@ -1282,6 +1284,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
              * point (i.e. the caller of the MPU_<API>). We need to restore it
              * when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+
             /* Store the value of the PSPLIM register before the SVC was raised.
              * We need to restore it when we exit from the system call. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
@@ -1300,6 +1303,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
             /* Start executing the system call upon returning from this handler. */
             pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
+
             /* Raise a request to exit from the system call upon finishing the
              * system call. */
             pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit;
@@ -1359,6 +1363,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
+
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __privileged_functions_start__;
@@ -1541,7 +1546,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
-        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+        #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
         {
             /* Check PACBTI security feature configuration before pushing the
              * CONTROL register's value on task's TCB. */
@@ -1582,6 +1587,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
+        #if ( configENABLE_PAC == 1 )
+        {
+            uint32_t ulTaskPacKey[ 4 ], i;
+
+            vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+            for( i = 0; i < 4; i++ )
+            {
+                xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ];
+                ulIndex++;
+            }
+        }
+        #endif /* configENABLE_PAC */
+
         return &( xMPUSettings->ulContext[ ulIndex ] );
     }
 
@@ -1664,6 +1683,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #endif /* portPRELOAD_REGISTERS */
 
+        #if ( configENABLE_PAC == 1 )
+        {
+            uint32_t ulTaskPacKey[ 4 ], i;
+
+            vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+            for( i = 0; i < 4; i++ )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = ulTaskPacKey[ i ];
+            }
+        }
+        #endif /* configENABLE_PAC */
+
         return pxTopOfStack;
     }
 
@@ -1786,11 +1819,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
-    #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+    #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
     {
         /* Set the CONTROL register value based on PACBTI security feature
          * configuration before starting the first task. */
-        ( void) prvConfigurePACBTI( pdTRUE );
+        ( void ) prvConfigurePACBTI( pdTRUE );
     }
     #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
@@ -1990,9 +2023,9 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
         if( xSchedulerRunning == pdFALSE )
         {
             /* Grant access to all the kernel objects before the scheduler
-            * is started. It is necessary because there is no task running
-            * yet and therefore, we cannot use the permissions of any
-            * task. */
+             * is started. It is necessary because there is no task running
+             * yet and therefore, we cannot use the permissions of any
+             * task. */
             xAccessGranted = pdTRUE;
         }
         else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
@@ -2213,7 +2246,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
 
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
     {
@@ -2225,13 +2258,13 @@ BaseType_t xPortIsInsideInterrupt( void )
         /* Enable UsageFault exception. */
         portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
 
-        #if( configENABLE_PAC == 1 )
+        #if ( configENABLE_PAC == 1 )
         {
             ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
         }
         #endif
 
-        #if( configENABLE_BTI == 1 )
+        #if ( configENABLE_BTI == 1 )
         {
             ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
         }
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.c b/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.c
index 7cdff7005..bc7bb6071 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.c
@@ -77,16 +77,16 @@
             "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
             "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
             "                                                 \n"
-            #if ( configTOTAL_MPU_REGIONS == 16 )
-                "    movs r3, #8                                  \n" /* r3 = 8. */
-                "    str r3, [r1]                                 \n" /* Program RNR = 8. */
-                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-                "    movs r3, #12                                 \n" /* r3 = 12. */
-                "    str r3, [r1]                                 \n" /* Program RNR = 12. */
-                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-            #endif /* configTOTAL_MPU_REGIONS == 16 */
+        #if ( configTOTAL_MPU_REGIONS == 16 )
+            "    movs r3, #8                                  \n" /* r3 = 8. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 8. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "    movs r3, #12                                 \n" /* r3 = 12. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 12. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+        #endif /* configTOTAL_MPU_REGIONS == 16 */
             "                                                 \n"
             "   ldr r1, =0xe000ed94                           \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
@@ -100,6 +100,14 @@
             "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
             "                                                 \n"
             " restore_special_regs_first_task:                \n"
+        #if ( configENABLE_PAC == 1 )
+            "   ldmdb r1!, {r2-r5}                            \n" /* Read task's dedicated PAC key from the task's context. */
+            "   msr  PAC_KEY_P_0, r2                          \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+            "   msr  PAC_KEY_P_1, r3                          \n"
+            "   msr  PAC_KEY_P_2, r4                          \n"
+            "   msr  PAC_KEY_P_3, r5                          \n"
+            "   clrm {r2-r5}                                  \n" /* Clear r2-r5. */
+        #endif /* configENABLE_PAC */
             "    ldmdb r1!, {r2-r4, lr}                       \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
             "    msr psp, r2                                  \n"
             "    msr psplim, r3                               \n"
@@ -130,6 +138,15 @@
             "   ldr  r1, [r2]                                   \n" /* Read pxCurrentTCB. */
             "   ldr  r0, [r1]                                   \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
             "                                                   \n"
+        #if ( configENABLE_PAC == 1 )
+            "   ldmia r0!, {r1-r4}                              \n" /* Read task's dedicated PAC key from stack. */
+            "   msr  PAC_KEY_P_3, r1                            \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+            "   msr  PAC_KEY_P_2, r2                            \n"
+            "   msr  PAC_KEY_P_1, r3                            \n"
+            "   msr  PAC_KEY_P_0, r4                            \n"
+            "   clrm {r1-r4}                                    \n" /* Clear r1-r4. */
+        #endif /* configENABLE_PAC */
+            "                                                   \n"
             "   ldm  r0!, {r1-r2}                               \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
             "   msr  psplim, r1                                 \n" /* Set this task's PSPLIM value. */
             "   mrs  r1, control                                \n" /* Obtain current control register value. */
@@ -261,16 +278,15 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             " mrs r2, psp                                     \n" /* r2 = PSP. */
             "                                                 \n"
             " save_general_regs:                              \n"
-            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-                "    add r2, r2, #0x20                            \n" /* Move r2 to location where s0 is saved. */
-                "    tst lr, #0x10                                \n"
-                "    ittt eq                                      \n"
-                "    vstmiaeq r1!, {s16-s31}                      \n" /* Store s16-s31. */
-                "    vldmiaeq r2, {s0-s16}                        \n" /* Copy hardware saved FP context into s0-s16. */
-                "    vstmiaeq r1!, {s0-s16}                       \n" /* Store hardware saved FP context. */
-                "    sub r2, r2, #0x20                            \n" /* Set r2 back to the location of hardware saved context. */
-            #endif /* configENABLE_FPU || configENABLE_MVE */
-            "                                                 \n"
+        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            "    add r2, r2, #0x20                            \n" /* Move r2 to location where s0 is saved. */
+            "    tst lr, #0x10                                \n"
+            "    ittt eq                                      \n"
+            "    vstmiaeq r1!, {s16-s31}                      \n" /* Store s16-s31. */
+            "    vldmiaeq r2, {s0-s16}                        \n" /* Copy hardware saved FP context into s0-s16. */
+            "    vstmiaeq r1!, {s0-s16}                       \n" /* Store hardware saved FP context. */
+            "    sub r2, r2, #0x20                            \n" /* Set r2 back to the location of hardware saved context. */
+        #endif /* configENABLE_FPU || configENABLE_MVE */
             "    stmia r1!, {r4-r11}                          \n" /* Store r4-r11. */
             "    ldmia r2, {r4-r11}                           \n" /* Copy the hardware saved context into r4-r11. */
             "    stmia r1!, {r4-r11}                          \n" /* Store the hardware saved context. */
@@ -279,6 +295,14 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    mrs r3, psplim                               \n" /* r3 = PSPLIM. */
             "    mrs r4, control                              \n" /* r4 = CONTROL. */
             "    stmia r1!, {r2-r4, lr}                       \n" /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
+        #if ( configENABLE_PAC == 1 )
+            "   mrs  r2, PAC_KEY_P_0                          \n" /* Read task's dedicated PAC key from the PAC key registers. */
+            "   mrs  r3, PAC_KEY_P_1                          \n"
+            "   mrs  r4, PAC_KEY_P_2                          \n"
+            "   mrs  r5, PAC_KEY_P_3                          \n"
+            "   stmia r1!, {r2-r5}                            \n" /* Store the task's dedicated PAC key on the task's context. */
+            "   clrm {r2-r5}                                  \n" /* Clear r2-r5. */
+        #endif /* configENABLE_PAC */
             "    str r1, [r0]                                 \n" /* Save the location from where the context should be restored as the first member of TCB. */
             "                                                 \n"
             " select_next_task:                               \n"
@@ -314,16 +338,16 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
             "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
             "                                                 \n"
-            #if ( configTOTAL_MPU_REGIONS == 16 )
-                "    movs r3, #8                                  \n" /* r3 = 8. */
-                "    str r3, [r1]                                 \n" /* Program RNR = 8. */
-                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-                "    movs r3, #12                                 \n" /* r3 = 12. */
-                "    str r3, [r1]                                 \n" /* Program RNR = 12. */
-                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-            #endif /* configTOTAL_MPU_REGIONS == 16 */
+        #if ( configTOTAL_MPU_REGIONS == 16 )
+            "    movs r3, #8                                  \n" /* r3 = 8. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 8. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "    movs r3, #12                                 \n" /* r3 = 12. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 12. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+        #endif /* configTOTAL_MPU_REGIONS == 16 */
             "                                                 \n"
             "   ldr r1, =0xe000ed94                           \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
@@ -337,6 +361,14 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
             "                                                 \n"
             " restore_special_regs:                           \n"
+        #if ( configENABLE_PAC == 1 )
+            "   ldmdb r1!, {r2-r5}                            \n" /* Read task's dedicated PAC key from the task's context. */
+            "   msr  PAC_KEY_P_0, r2                          \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+            "   msr  PAC_KEY_P_1, r3                          \n"
+            "   msr  PAC_KEY_P_2, r4                          \n"
+            "   msr  PAC_KEY_P_3, r5                          \n"
+            "   clrm {r2-r5}                                  \n" /* Clear r2-r5. */
+        #endif /* configENABLE_PAC */
             "    ldmdb r1!, {r2-r4, lr}                       \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
             "    msr psp, r2                                  \n"
             "    msr psplim, r3                               \n"
@@ -346,13 +378,13 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
             "    stmia r2!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
             "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 restored. */
-            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-                "    tst lr, #0x10                                \n"
-                "    ittt eq                                      \n"
-                "    vldmdbeq r1!, {s0-s16}                       \n" /* s0-s16 contain hardware saved FP context. */
-                "    vstmiaeq r2!, {s0-s16}                       \n" /* Copy hardware saved FP context on the task stack. */
-                "    vldmdbeq r1!, {s16-s31}                      \n" /* Restore s16-s31. */
-            #endif /* configENABLE_FPU || configENABLE_MVE */
+        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            "    tst lr, #0x10                                \n"
+            "    ittt eq                                      \n"
+            "    vldmdbeq r1!, {s0-s16}                       \n" /* s0-s16 contain hardware saved FP context. */
+            "    vstmiaeq r2!, {s0-s16}                       \n" /* Copy hardware saved FP context on the task stack. */
+            "    vldmdbeq r1!, {s16-s31}                      \n" /* Restore s16-s31. */
+        #endif /* configENABLE_FPU || configENABLE_MVE */
             "                                                 \n"
             " restore_context_done:                           \n"
             "    str r1, [r0]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
@@ -371,16 +403,25 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "                                                   \n"
             "   mrs r0, psp                                     \n" /* Read PSP in r0. */
             "                                                   \n"
-            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-                "   tst lr, #0x10                                   \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
-                "   it eq                                           \n"
-                "   vstmdbeq r0!, {s16-s31}                         \n" /* Store the additional FP context registers which are not saved automatically. */
-            #endif /* configENABLE_FPU || configENABLE_MVE */
+        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            "   tst lr, #0x10                                   \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+            "   it eq                                           \n"
+            "   vstmdbeq r0!, {s16-s31}                         \n" /* Store the additional FP context registers which are not saved automatically. */
+        #endif /* configENABLE_FPU || configENABLE_MVE */
             "                                                   \n"
             "   mrs r2, psplim                                  \n" /* r2 = PSPLIM. */
             "   mov r3, lr                                      \n" /* r3 = LR/EXC_RETURN. */
             "   stmdb r0!, {r2-r11}                             \n" /* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */
             "                                                   \n"
+        #if ( configENABLE_PAC == 1 )
+            "   mrs  r1, PAC_KEY_P_3                            \n" /* Read task's dedicated PAC key from the PAC key registers. */
+            "   mrs  r2, PAC_KEY_P_2                            \n"
+            "   mrs  r3, PAC_KEY_P_1                            \n"
+            "   mrs  r4, PAC_KEY_P_0                            \n"
+            "   stmdb r0!, {r1-r4}                              \n" /* Store the task's dedicated PAC key on the stack. */
+            "   clrm {r1-r4}                                    \n" /* Clear r1-r4. */
+        #endif /* configENABLE_PAC */
+            "                                                   \n"
             "   ldr r2, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr r1, [r2]                                    \n" /* Read pxCurrentTCB. */
             "   str r0, [r1]                                    \n" /* Save the new top of stack in TCB. */
@@ -397,13 +438,22 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   ldr r1, [r2]                                    \n" /* Read pxCurrentTCB. */
             "   ldr r0, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
             "                                                   \n"
+        #if ( configENABLE_PAC == 1 )
+            "   ldmia r0!, {r2-r5}                              \n" /* Read task's dedicated PAC key from stack. */
+            "   msr  PAC_KEY_P_3, r2                            \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+            "   msr  PAC_KEY_P_2, r3                            \n"
+            "   msr  PAC_KEY_P_1, r4                            \n"
+            "   msr  PAC_KEY_P_0, r5                            \n"
+            "   clrm {r2-r5}                                    \n" /* Clear r2-r5. */
+        #endif /* configENABLE_PAC */
+            "                                                   \n"
             "   ldmia r0!, {r2-r11}                             \n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
             "                                                   \n"
-            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-                "   tst r3, #0x10                                   \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
-                "   it eq                                           \n"
-                "   vldmiaeq r0!, {s16-s31}                         \n" /* Restore the additional FP context registers which are not restored automatically. */
-            #endif /* configENABLE_FPU || configENABLE_MVE */
+        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            "   tst r3, #0x10                                   \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+            "   it eq                                           \n"
+            "   vldmiaeq r0!, {s16-s31}                         \n" /* Restore the additional FP context registers which are not restored automatically. */
+        #endif /* configENABLE_FPU || configENABLE_MVE */
             "                                                   \n"
             "   msr psplim, r2                                  \n" /* Restore the PSPLIM register value for the task. */
             "   msr psp, r0                                     \n" /* Remember the new top of stack for the task. */
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacro.h b/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacro.h
index 4db6e6d4a..b886287ac 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacro.h
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacro.h
@@ -60,7 +60,7 @@
 
 #ifndef configENABLE_MVE
     #define configENABLE_MVE    0
-#elif( configENABLE_MVE != 0 )
+#elif ( configENABLE_MVE != 0 )
     #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M35.
 #endif
 /*-----------------------------------------------------------*/
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
index 8a8dc7d6a..e74fa8257 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -125,6 +127,18 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
     extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
 #endif /* configENABLE_MPU */
+
+#if ( configENABLE_PAC == 1 )
+
+    /**
+     * @brief Generates 128-bit task's random PAC key.
+     *
+     * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be
+     *             filled with a 128-bit random number.
+     */
+    void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey );
+
+#endif /* configENABLE_PAC */
 /*-----------------------------------------------------------*/
 
 /**
@@ -188,9 +202,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Settings to define an MPU region.
- */
+    /**
+     * @brief Settings to define an MPU region.
+     */
     typedef struct MPURegionSettings
     {
         uint32_t ulRBAR; /**< RBAR for the region. */
@@ -203,9 +217,14 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-/**
- * @brief System call stack.
- */
+        /* When MPU wrapper v2 is used, the task's context is stored in TCB and
+         * pxTopOfStack member of TCB points to the context location in TCB. We,
+         * therefore, need to read PSP to find the task's current top of stack. */
+        #define portGET_CURRENT_TOP_OF_STACK( pxCurrentTopOfStack ) { __asm volatile ( "mrs %0, psp"  : "=r" ( pxCurrentTopOfStack ) ); }
+
+        /**
+         * @brief System call stack.
+         */
         typedef struct SYSTEM_CALL_STACK_INFO
         {
             uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ];
@@ -218,76 +237,128 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
-/**
- * @brief MPU settings as stored in the TCB.
- */
+    /**
+     * @brief MPU settings as stored in the TCB.
+     */
     #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+        #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +-----------+---------------+----------+-----------------+------------------------------+-----+
- * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
- * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
- * +-----------+---------------+----------+-----------------+------------------------------+-----+
- *
- * <-----------><--------------><---------><----------------><-----------------------------><---->
- *      16             16            8               8                     5                   1
- */
+            /*
+             * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey |     |
+             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |            |     |
+             * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
+             *      16             16            8               8                     5                     16         1
+             */
+            #define MAX_CONTEXT_SIZE    70
+
+        #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
+
+            /*
+             * +-----------+---------------+----------+-----------------+------------------------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+             * +-----------+---------------+----------+-----------------+------------------------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><-----------------------------><---->
+             *      16             16            8               8                     5                   1
+             */
             #define MAX_CONTEXT_SIZE    54
 
-        #else /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +-----------+---------------+----------+-----------------+----------------------+-----+
- * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
- * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
- * +-----------+---------------+----------+-----------------+----------------------+-----+
- *
- * <-----------><--------------><---------><----------------><---------------------><---->
- *      16             16            8               8                  4              1
- */
+            /*
+             * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey |     |
+             * |           |               |          | PC, xPSR        | EXC_RETURN           |            |     |
+             * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><---------------------><-----------><---->
+             *      16             16            8               8                  4                16         1
+             */
+            #define MAX_CONTEXT_SIZE    69
+
+        #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
+
+            /*
+             * +-----------+---------------+----------+-----------------+----------------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+             * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
+             * +-----------+---------------+----------+-----------------+----------------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><---------------------><---->
+             *      16             16            8               8                  4              1
+             */
             #define MAX_CONTEXT_SIZE    53
 
-        #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
     #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+        #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +----------+-----------------+------------------------------+-----+
- * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
- * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
- * +----------+-----------------+------------------------------+-----+
- *
- * <---------><----------------><------------------------------><---->
- *     8               8                      5                   1
- */
+            /*
+             * +----------+-----------------+------------------------------+------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey |     |
+             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |            |     |
+             * +----------+-----------------+------------------------------+------------+-----+
+             *
+             * <---------><----------------><------------------------------><-----------><---->
+             *     8               8                      5                      16         1
+             */
+            #define MAX_CONTEXT_SIZE    38
+
+        #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
+
+            /*
+             * +----------+-----------------+------------------------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+             * +----------+-----------------+------------------------------+-----+
+             *
+             * <---------><----------------><------------------------------><---->
+             *     8               8                      5                   1
+             */
             #define MAX_CONTEXT_SIZE    22
 
+        #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+            /*
+             * +----------+-----------------+----------------------+------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey |     |
+             * |          | PC, xPSR        | EXC_RETURN           |            |     |
+             * +----------+-----------------+----------------------+------------+-----+
+             *
+             * <---------><----------------><----------------------><-----------><---->
+             *     8               8                  4                  16         1
+             */
+            #define MAX_CONTEXT_SIZE    37
+
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-/*
- * +----------+-----------------+----------------------+-----+
- * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
- * |          | PC, xPSR        | EXC_RETURN           |     |
- * +----------+-----------------+----------------------+-----+
- *
- * <---------><----------------><----------------------><---->
- *     8               8                  4              1
- */
+            /*
+             * +----------+-----------------+----------------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+             * |          | PC, xPSR        | EXC_RETURN           |     |
+             * +----------+-----------------+----------------------+-----+
+             *
+             * <---------><----------------><----------------------><---->
+             *     8               8                  4              1
+             */
             #define MAX_CONTEXT_SIZE    21
 
-        #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
     #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
+    /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
-/* Size of an Access Control List (ACL) entry in bits. */
+    /* Size of an Access Control List (ACL) entry in bits. */
     #define portACL_ENTRY_SIZE_BITS             ( 32U )
 
     typedef struct MPU_SETTINGS
diff --git a/portable/GCC/ARM_CM55/non_secure/port.c b/portable/GCC/ARM_CM55/non_secure/port.c
index aa9c23816..b2fd7e518 100644
--- a/portable/GCC/ARM_CM55/non_secure/port.c
+++ b/portable/GCC/ARM_CM55/non_secure/port.c
@@ -169,79 +169,80 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                            ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                            ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                             ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                            ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                            ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                           ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                           ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK        ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                      ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK                     ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                      ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK                     ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                      ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK                     ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                      ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK                     ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                      ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK                     ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                      ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK                     ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                      ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK                     ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                      ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK                     ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0                    ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1                    ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2                    ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3                    ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4                    ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5                    ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6                    ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7                    ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE                  ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
 
 #if ( portARMV8M_MINOR_VERSION >= 1 )
-    /* Enable Privileged eXecute Never MPU attribute for the selected memory
-     * region. */
-    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER   ( 1UL << 4UL )
+
+/* Enable Privileged eXecute Never MPU attribute for the selected memory
+ * region. */
+    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER    ( 1UL << 4UL )
 #endif /* portARMV8M_MINOR_VERSION >= 1 */
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT          ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                          ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE                 ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -380,14 +381,14 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to check and configure PACBTI security feature implementation.
  */
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
-    #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
+    #define portID_ISAR5_REG       ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
 
-    #define portCONTROL_UPAC_EN      ( 1UL << 7UL )
-    #define portCONTROL_PAC_EN       ( 1UL << 6UL )
-    #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
-    #define portCONTROL_BTI_EN       ( 1UL << 4UL )
+    #define portCONTROL_UPAC_EN    ( 1UL << 7UL )
+    #define portCONTROL_PAC_EN     ( 1UL << 6UL )
+    #define portCONTROL_UBTI_EN    ( 1UL << 5UL )
+    #define portCONTROL_BTI_EN     ( 1UL << 4UL )
 
 #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
@@ -409,7 +410,7 @@ static void prvTaskExitError( void );
  * @return uint32_t Access permissions.
  */
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0  */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 
 #if ( configENABLE_MPU == 1 )
 
@@ -427,7 +428,7 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
 /**
  * @brief Configures PACBTI features.
@@ -890,7 +891,7 @@ static void prvTaskExitError( void )
         return ulAccessPermissions;
     }
 
-#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0  */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
@@ -1212,6 +1213,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
+
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __syscalls_flash_start__;
@@ -1282,6 +1284,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
              * point (i.e. the caller of the MPU_<API>). We need to restore it
              * when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+
             /* Store the value of the PSPLIM register before the SVC was raised.
              * We need to restore it when we exit from the system call. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
@@ -1300,6 +1303,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
             /* Start executing the system call upon returning from this handler. */
             pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
+
             /* Raise a request to exit from the system call upon finishing the
              * system call. */
             pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit;
@@ -1359,6 +1363,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
+
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __privileged_functions_start__;
@@ -1541,7 +1546,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
-        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+        #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
         {
             /* Check PACBTI security feature configuration before pushing the
              * CONTROL register's value on task's TCB. */
@@ -1582,6 +1587,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
+        #if ( configENABLE_PAC == 1 )
+        {
+            uint32_t ulTaskPacKey[ 4 ], i;
+
+            vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+            for( i = 0; i < 4; i++ )
+            {
+                xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ];
+                ulIndex++;
+            }
+        }
+        #endif /* configENABLE_PAC */
+
         return &( xMPUSettings->ulContext[ ulIndex ] );
     }
 
@@ -1664,6 +1683,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #endif /* portPRELOAD_REGISTERS */
 
+        #if ( configENABLE_PAC == 1 )
+        {
+            uint32_t ulTaskPacKey[ 4 ], i;
+
+            vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+            for( i = 0; i < 4; i++ )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = ulTaskPacKey[ i ];
+            }
+        }
+        #endif /* configENABLE_PAC */
+
         return pxTopOfStack;
     }
 
@@ -1786,11 +1819,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
-    #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+    #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
     {
         /* Set the CONTROL register value based on PACBTI security feature
          * configuration before starting the first task. */
-        ( void) prvConfigurePACBTI( pdTRUE );
+        ( void ) prvConfigurePACBTI( pdTRUE );
     }
     #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
@@ -1990,9 +2023,9 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
         if( xSchedulerRunning == pdFALSE )
         {
             /* Grant access to all the kernel objects before the scheduler
-            * is started. It is necessary because there is no task running
-            * yet and therefore, we cannot use the permissions of any
-            * task. */
+             * is started. It is necessary because there is no task running
+             * yet and therefore, we cannot use the permissions of any
+             * task. */
             xAccessGranted = pdTRUE;
         }
         else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
@@ -2213,7 +2246,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
 
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
     {
@@ -2225,13 +2258,13 @@ BaseType_t xPortIsInsideInterrupt( void )
         /* Enable UsageFault exception. */
         portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
 
-        #if( configENABLE_PAC == 1 )
+        #if ( configENABLE_PAC == 1 )
         {
             ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
         }
         #endif
 
-        #if( configENABLE_BTI == 1 )
+        #if ( configENABLE_BTI == 1 )
         {
             ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
         }
diff --git a/portable/GCC/ARM_CM55/non_secure/portasm.c b/portable/GCC/ARM_CM55/non_secure/portasm.c
index aaeccaa35..0ebbe48a4 100644
--- a/portable/GCC/ARM_CM55/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM55/non_secure/portasm.c
@@ -77,16 +77,16 @@
             "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
             "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
             "                                                 \n"
-            #if ( configTOTAL_MPU_REGIONS == 16 )
-                "    movs r3, #8                                  \n" /* r3 = 8. */
-                "    str r3, [r1]                                 \n" /* Program RNR = 8. */
-                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
-                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-                "    movs r3, #12                                 \n" /* r3 = 12. */
-                "    str r3, [r1]                                 \n" /* Program RNR = 12. */
-                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
-                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-            #endif /* configTOTAL_MPU_REGIONS == 16 */
+        #if ( configTOTAL_MPU_REGIONS == 16 )
+            "    movs r3, #8                                  \n" /* r3 = 8. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 8. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "    movs r3, #12                                 \n" /* r3 = 12. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 12. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+        #endif /* configTOTAL_MPU_REGIONS == 16 */
             "                                                 \n"
             "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
@@ -100,6 +100,14 @@
             "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
             "                                                 \n"
             " restore_special_regs_first_task:                \n"
+        #if ( configENABLE_PAC == 1 )
+            "   ldmdb r2!, {r3-r6}                            \n" /* Read task's dedicated PAC key from the task's context. */
+            "   msr  PAC_KEY_P_0, r3                          \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+            "   msr  PAC_KEY_P_1, r4                          \n"
+            "   msr  PAC_KEY_P_2, r5                          \n"
+            "   msr  PAC_KEY_P_3, r6                          \n"
+            "   clrm {r3-r6}                                  \n" /* Clear r3-r6. */
+        #endif /* configENABLE_PAC */
             "    ldmdb r2!, {r0, r3-r5, lr}                   \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
             "    msr psp, r3                                  \n"
             "    msr psplim, r4                               \n"
@@ -132,6 +140,15 @@
             "   ldr  r3, [r2]                                   \n" /* Read pxCurrentTCB. */
             "   ldr  r0, [r3]                                   \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
             "                                                   \n"
+        #if ( configENABLE_PAC == 1 )
+            "   ldmia r0!, {r1-r4}                              \n" /* Read task's dedicated PAC key from stack. */
+            "   msr  PAC_KEY_P_3, r1                            \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+            "   msr  PAC_KEY_P_2, r2                            \n"
+            "   msr  PAC_KEY_P_1, r3                            \n"
+            "   msr  PAC_KEY_P_0, r4                            \n"
+            "   clrm {r1-r4}                                    \n" /* Clear r1-r4. */
+        #endif /* configENABLE_PAC */
+            "                                                   \n"
             "   ldm  r0!, {r1-r3}                               \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
             "   ldr  r4, =xSecureContext                        \n"
             "   str  r1, [r4]                                   \n" /* Set xSecureContext to this task's value for the same. */
@@ -280,17 +297,15 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "                                                 \n"
             " save_general_regs:                              \n"
             "    mrs r3, psp                                  \n"
-            "                                                 \n"
-            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-                "    add r3, r3, #0x20                            \n" /* Move r3 to location where s0 is saved. */
-                "    tst lr, #0x10                                \n"
-                "    ittt eq                                      \n"
-                "    vstmiaeq r2!, {s16-s31}                      \n" /* Store s16-s31. */
-                "    vldmiaeq r3, {s0-s16}                        \n" /* Copy hardware saved FP context into s0-s16. */
-                "    vstmiaeq r2!, {s0-s16}                       \n" /* Store hardware saved FP context. */
-                "    sub r3, r3, #0x20                            \n" /* Set r3 back to the location of hardware saved context. */
-            #endif /* configENABLE_FPU || configENABLE_MVE */
-            "                                                 \n"
+        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            "    add r3, r3, #0x20                            \n" /* Move r3 to location where s0 is saved. */
+            "    tst lr, #0x10                                \n"
+            "    ittt eq                                      \n"
+            "    vstmiaeq r2!, {s16-s31}                      \n" /* Store s16-s31. */
+            "    vldmiaeq r3, {s0-s16}                        \n" /* Copy hardware saved FP context into s0-s16. */
+            "    vstmiaeq r2!, {s0-s16}                       \n" /* Store hardware saved FP context. */
+            "    sub r3, r3, #0x20                            \n" /* Set r3 back to the location of hardware saved context. */
+        #endif /* configENABLE_FPU || configENABLE_MVE */
             "    stmia r2!, {r4-r11}                          \n" /* Store r4-r11. */
             "    ldmia r3, {r4-r11}                           \n" /* Copy the hardware saved context into r4-r11. */
             "    stmia r2!, {r4-r11}                          \n" /* Store the hardware saved context. */
@@ -300,7 +315,15 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    mrs r4, psplim                               \n" /* r4 = PSPLIM. */
             "    mrs r5, control                              \n" /* r5 = CONTROL. */
             "    stmia r2!, {r0, r3-r5, lr}                   \n" /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
-            "    str r2, [r1]                                 \n" /* Save the location from where the context should be restored as the first member of TCB. */
+        #if ( configENABLE_PAC == 1 )
+            "   mrs  r3, PAC_KEY_P_0                          \n" /* Read task's dedicated PAC key from the PAC key registers. */
+            "   mrs  r4, PAC_KEY_P_1                          \n"
+            "   mrs  r5, PAC_KEY_P_2                          \n"
+            "   mrs  r6, PAC_KEY_P_3                          \n"
+            "   stmia r2!, {r3-r6}                            \n" /* Store the task's dedicated PAC key on the task's context. */
+            "   clrm {r3-r6}                                  \n" /* Clear r3-r6. */
+        #endif /* configENABLE_PAC */
+            "    str r2, [r1]                                 \n"      /* Save the location from where the context should be restored as the first member of TCB. */
             "                                                 \n"
             " select_next_task:                               \n"
             "    mov r0, %0                                   \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
@@ -335,16 +358,16 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
             "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
             "                                                 \n"
-            #if ( configTOTAL_MPU_REGIONS == 16 )
-                "    movs r3, #8                                  \n" /* r3 = 8. */
-                "    str r3, [r1]                                 \n" /* Program RNR = 8. */
-                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-                "    movs r3, #12                                 \n" /* r3 = 12. */
-                "    str r3, [r1]                                 \n" /* Program RNR = 12. */
-                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-            #endif /* configTOTAL_MPU_REGIONS == 16 */
+        #if ( configTOTAL_MPU_REGIONS == 16 )
+            "    movs r3, #8                                  \n" /* r3 = 8. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 8. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "    movs r3, #12                                 \n" /* r3 = 12. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 12. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+        #endif /* configTOTAL_MPU_REGIONS == 16 */
             "                                                 \n"
             "   ldr r1, =0xe000ed94                           \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
@@ -358,6 +381,14 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
             "                                                 \n"
             " restore_special_regs:                           \n"
+        #if ( configENABLE_PAC == 1 )
+            "   ldmdb r2!, {r3-r6}                            \n" /* Read task's dedicated PAC key from the task's context. */
+            "   msr  PAC_KEY_P_0, r3                          \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+            "   msr  PAC_KEY_P_1, r4                          \n"
+            "   msr  PAC_KEY_P_2, r5                          \n"
+            "   msr  PAC_KEY_P_3, r6                          \n"
+            "   clrm {r3-r6}                                  \n" /* Clear r3-r6. */
+        #endif /* configENABLE_PAC */
             "    ldmdb r2!, {r0, r3-r5, lr}                   \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
             "    msr psp, r3                                  \n"
             "    msr psplim, r4                               \n"
@@ -380,13 +411,13 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
             "    stmia r3!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
             "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 restored. */
-            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-                "    tst lr, #0x10                                \n"
-                "    ittt eq                                      \n"
-                "    vldmdbeq r2!, {s0-s16}                       \n" /* s0-s16 contain hardware saved FP context. */
-                "    vstmiaeq r3!, {s0-s16}                       \n" /* Copy hardware saved FP context on the task stack. */
-                "    vldmdbeq r2!, {s16-s31}                      \n" /* Restore s16-s31. */
-            #endif /* configENABLE_FPU || configENABLE_MVE */
+        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            "    tst lr, #0x10                                \n"
+            "    ittt eq                                      \n"
+            "    vldmdbeq r2!, {s0-s16}                       \n" /* s0-s16 contain hardware saved FP context. */
+            "    vstmiaeq r3!, {s0-s16}                       \n" /* Copy hardware saved FP context on the task stack. */
+            "    vldmdbeq r2!, {s16-s31}                      \n" /* Restore s16-s31. */
+        #endif /* configENABLE_FPU || configENABLE_MVE */
             "                                                 \n"
             " restore_context_done:                           \n"
             "    str r2, [r1]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
@@ -401,89 +432,99 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
     {
         __asm volatile
         (
-            "   .syntax unified                                 \n"
-            "   .extern SecureContext_SaveContext               \n"
-            "   .extern SecureContext_LoadContext               \n"
-            "                                                   \n"
-            "   ldr r3, =xSecureContext                         \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-            "   ldr r0, [r3]                                    \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
-            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
-            "   mrs r2, psp                                     \n" /* Read PSP in r2. */
-            "                                                   \n"
-            "   cbz r0, save_ns_context                         \n" /* No secure context to save. */
-            "   push {r0-r2, r14}                               \n"
-            "   bl SecureContext_SaveContext                    \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-            "   pop {r0-r3}                                     \n" /* LR is now in r3. */
-            "   mov lr, r3                                      \n" /* LR = r3. */
-            "   lsls r1, r3, #25                                \n" /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-            "   bpl save_ns_context                             \n" /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-            "                                                   \n"
-            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB.*/
-            "   subs r2, r2, #12                                \n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */
-            "   str r2, [r1]                                    \n" /* Save the new top of stack in TCB. */
-            "   mrs r1, psplim                                  \n" /* r1 = PSPLIM. */
-            "   mov r3, lr                                      \n" /* r3 = LR/EXC_RETURN. */
-            "   stmia r2!, {r0, r1, r3}                         \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
-            "   b select_next_task                              \n"
-            "                                                   \n"
-            " save_ns_context:                                  \n"
-            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
-            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-                "   tst lr, #0x10                               \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
-                "   it eq                                       \n"
-                "   vstmdbeq r2!, {s16-s31}                     \n" /* Store the additional FP context registers which are not saved automatically. */
-            #endif /* configENABLE_FPU || configENABLE_MVE */
-            "   subs r2, r2, #44                                \n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
-            "   str r2, [r1]                                    \n" /* Save the new top of stack in TCB. */
-            "   adds r2, r2, #12                                \n" /* r2 = r2 + 12. */
-            "   stm r2, {r4-r11}                                \n" /* Store the registers that are not saved automatically. */
-            "   mrs r1, psplim                                  \n" /* r1 = PSPLIM. */
-            "   mov r3, lr                                      \n" /* r3 = LR/EXC_RETURN. */
-            "   subs r2, r2, #12                                \n" /* r2 = r2 - 12. */
-            "   stmia r2!, {r0, r1, r3}                         \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
-            "                                                   \n"
-            " select_next_task:                                 \n"
-            "   mov r0, %0                                      \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
-            "   msr basepri, r0                                 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-            "   dsb                                             \n"
-            "   isb                                             \n"
-            "   bl vTaskSwitchContext                           \n"
-            "   mov r0, #0                                      \n" /* r0 = 0. */
-            "   msr basepri, r0                                 \n" /* Enable interrupts. */
-            "                                                   \n"
-            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
-            "   ldr r2, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
-            "                                                   \n"
-            "   ldmia r2!, {r0, r1, r4}                         \n" /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
-            "   msr psplim, r1                                  \n" /* Restore the PSPLIM register value for the task. */
-            "   mov lr, r4                                      \n" /* LR = r4. */
-            "   ldr r3, =xSecureContext                         \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-            "   str r0, [r3]                                    \n" /* Restore the task's xSecureContext. */
-            "   cbz r0, restore_ns_context                      \n" /* If there is no secure context for the task, restore the non-secure context. */
-            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
-            "   push {r2, r4}                                   \n"
-            "   bl SecureContext_LoadContext                    \n" /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-            "   pop {r2, r4}                                    \n"
-            "   mov lr, r4                                      \n" /* LR = r4. */
-            "   lsls r1, r4, #25                                \n" /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-            "   bpl restore_ns_context                          \n" /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-            "   msr psp, r2                                     \n" /* Remember the new top of stack for the task. */
-            "   bx lr                                           \n"
-            "                                                   \n"
-            " restore_ns_context:                               \n"
-            "   ldmia r2!, {r4-r11}                             \n" /* Restore the registers that are not automatically restored. */
-            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-                "   tst lr, #0x10                               \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
-                "   it eq                                       \n"
-                "   vldmiaeq r2!, {s16-s31}                     \n" /* Restore the additional FP context registers which are not restored automatically. */
-            #endif /* configENABLE_FPU || configENABLE_MVE */
-            "   msr psp, r2                                     \n" /* Remember the new top of stack for the task. */
-            "   bx lr                                           \n"
+            " .syntax unified                                 \n"
+            " .extern SecureContext_SaveContext               \n"
+            " .extern SecureContext_LoadContext               \n"
+            "                                                 \n"
+            " ldr r3, =xSecureContext                         \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            " ldr r0, [r3]                                    \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+            " ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            " ldr r1, [r3]                                    \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
+            " mrs r2, psp                                     \n" /* Read PSP in r2. */
+            "                                                 \n"
+            " cbz r0, save_ns_context                         \n" /* No secure context to save. */
+            " save_s_context:                                 \n"
+            "    push {r0-r2, lr}                             \n"
+            "    bl SecureContext_SaveContext                 \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+            "    pop {r0-r2, lr}                              \n"
+            "                                                 \n"
+            " save_ns_context:                                \n"
+            "    mov r3, lr                                   \n" /* r3 = LR (EXC_RETURN). */
+            "    lsls r3, r3, #25                             \n" /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+            "    bmi save_special_regs                        \n" /* If r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used. */
+            "                                                 \n"
+            " save_general_regs:                              \n"
+        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            "    tst lr, #0x10                                \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+            "    it eq                                        \n"
+            "    vstmdbeq r2!, {s16-s31}                      \n" /* Store the additional FP context registers which are not saved automatically. */
+        #endif /* configENABLE_FPU || configENABLE_MVE */
+            "   stmdb r2!, {r4-r11}                           \n" /* Store the registers that are not saved automatically. */
+            "                                                 \n"
+            " save_special_regs:                              \n"
+            "    mrs r3, psplim                               \n" /* r3 = PSPLIM. */
+            "    stmdb r2!, {r0, r3, lr}                      \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
+        #if ( configENABLE_PAC == 1 )
+            "    mrs  r3, PAC_KEY_P_3                         \n" /* Read task's dedicated PAC key from the PAC key registers. */
+            "    mrs  r4, PAC_KEY_P_2                         \n"
+            "    mrs  r5, PAC_KEY_P_1                         \n"
+            "    mrs  r6, PAC_KEY_P_0                         \n"
+            "    stmdb r2!, {r3-r6}                           \n" /* Store the task's dedicated PAC key on the stack. */
+            "    clrm {r3-r6}                                 \n" /* Clear r3-r6. */
+        #endif /* configENABLE_PAC */
+            "                                                 \n"
+            " str r2, [r1]                                    \n" /* Save the new top of stack in TCB. */
+            "                                                 \n"
+            " select_next_task:                               \n"
+            "    mov r0, %0                                   \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
+            "    msr basepri, r0                              \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+            "    dsb                                          \n"
+            "    isb                                          \n"
+            "    bl vTaskSwitchContext                        \n"
+            "    mov r0, #0                                   \n" /* r0 = 0. */
+            "    msr basepri, r0                              \n" /* Enable interrupts. */
+            "                                                 \n"
+            " restore_context:                                \n"
+            "    ldr r3, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r1, [r3]                                 \n" /* Read pxCurrentTCB. */
+            "    ldr r2, [r1]                                 \n" /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
+            "                                                 \n"
+            " restore_special_regs:                           \n"
+        #if ( configENABLE_PAC == 1 )
+            "    ldmia r2!, {r3-r6}                           \n" /* Read task's dedicated PAC key from stack. */
+            "    msr  PAC_KEY_P_3, r3                         \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+            "    msr  PAC_KEY_P_2, r4                         \n"
+            "    msr  PAC_KEY_P_1, r5                         \n"
+            "    msr  PAC_KEY_P_0, r6                         \n"
+            "    clrm {r3-r6}                                 \n" /* Clear r3-r6. */
+        #endif /* configENABLE_PAC */
+            "    ldmia r2!, {r0, r3, lr}                      \n" /* Read from stack - r0 = xSecureContext, r3 = PSPLIM and LR restored. */
+            "    msr psplim, r3                               \n" /* Restore the PSPLIM register value for the task. */
+            "    ldr r3, =xSecureContext                      \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "    str r0, [r3]                                 \n" /* Restore the task's xSecureContext. */
+            "    cbz r0, restore_ns_context                   \n" /* If there is no secure context for the task, restore the non-secure context. */
+            "                                                 \n"
+            " restore_s_context:                              \n"
+            "    push {r1-r3, lr}                             \n"
+            "    bl SecureContext_LoadContext                 \n" /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+            "    pop {r1-r3, lr}                              \n"
+            "                                                 \n"
+            " restore_ns_context:                             \n"
+            "    mov r0, lr                                   \n" /* r0 = LR (EXC_RETURN). */
+            "    lsls r0, r0, #25                             \n" /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+            "    bmi restore_context_done                     \n" /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
+            "                                                 \n"
+            " restore_general_regs:                           \n"
+            "    ldmia r2!, {r4-r11}                          \n" /* Restore the registers that are not automatically restored. */
+        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            "   tst lr, #0x10                                 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+            "   it eq                                         \n"
+            "   vldmiaeq r2!, {s16-s31}                       \n" /* Restore the additional FP context registers which are not restored automatically. */
+        #endif /* configENABLE_FPU || configENABLE_MVE */
+            "                                                 \n"
+            " restore_context_done:                           \n"
+            "    msr psp, r2                                  \n" /* Remember the new top of stack for the task. */
+            "    bx lr                                        \n"
             ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
         );
     }
diff --git a/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h
index 8a8dc7d6a..e74fa8257 100644
--- a/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -125,6 +127,18 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
     extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
 #endif /* configENABLE_MPU */
+
+#if ( configENABLE_PAC == 1 )
+
+    /**
+     * @brief Generates 128-bit task's random PAC key.
+     *
+     * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be
+     *             filled with a 128-bit random number.
+     */
+    void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey );
+
+#endif /* configENABLE_PAC */
 /*-----------------------------------------------------------*/
 
 /**
@@ -188,9 +202,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Settings to define an MPU region.
- */
+    /**
+     * @brief Settings to define an MPU region.
+     */
     typedef struct MPURegionSettings
     {
         uint32_t ulRBAR; /**< RBAR for the region. */
@@ -203,9 +217,14 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-/**
- * @brief System call stack.
- */
+        /* When MPU wrapper v2 is used, the task's context is stored in TCB and
+         * pxTopOfStack member of TCB points to the context location in TCB. We,
+         * therefore, need to read PSP to find the task's current top of stack. */
+        #define portGET_CURRENT_TOP_OF_STACK( pxCurrentTopOfStack ) { __asm volatile ( "mrs %0, psp"  : "=r" ( pxCurrentTopOfStack ) ); }
+
+        /**
+         * @brief System call stack.
+         */
         typedef struct SYSTEM_CALL_STACK_INFO
         {
             uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ];
@@ -218,76 +237,128 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
-/**
- * @brief MPU settings as stored in the TCB.
- */
+    /**
+     * @brief MPU settings as stored in the TCB.
+     */
     #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+        #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +-----------+---------------+----------+-----------------+------------------------------+-----+
- * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
- * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
- * +-----------+---------------+----------+-----------------+------------------------------+-----+
- *
- * <-----------><--------------><---------><----------------><-----------------------------><---->
- *      16             16            8               8                     5                   1
- */
+            /*
+             * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey |     |
+             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |            |     |
+             * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
+             *      16             16            8               8                     5                     16         1
+             */
+            #define MAX_CONTEXT_SIZE    70
+
+        #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
+
+            /*
+             * +-----------+---------------+----------+-----------------+------------------------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+             * +-----------+---------------+----------+-----------------+------------------------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><-----------------------------><---->
+             *      16             16            8               8                     5                   1
+             */
             #define MAX_CONTEXT_SIZE    54
 
-        #else /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +-----------+---------------+----------+-----------------+----------------------+-----+
- * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
- * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
- * +-----------+---------------+----------+-----------------+----------------------+-----+
- *
- * <-----------><--------------><---------><----------------><---------------------><---->
- *      16             16            8               8                  4              1
- */
+            /*
+             * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey |     |
+             * |           |               |          | PC, xPSR        | EXC_RETURN           |            |     |
+             * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><---------------------><-----------><---->
+             *      16             16            8               8                  4                16         1
+             */
+            #define MAX_CONTEXT_SIZE    69
+
+        #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
+
+            /*
+             * +-----------+---------------+----------+-----------------+----------------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+             * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
+             * +-----------+---------------+----------+-----------------+----------------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><---------------------><---->
+             *      16             16            8               8                  4              1
+             */
             #define MAX_CONTEXT_SIZE    53
 
-        #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
     #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+        #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +----------+-----------------+------------------------------+-----+
- * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
- * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
- * +----------+-----------------+------------------------------+-----+
- *
- * <---------><----------------><------------------------------><---->
- *     8               8                      5                   1
- */
+            /*
+             * +----------+-----------------+------------------------------+------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey |     |
+             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |            |     |
+             * +----------+-----------------+------------------------------+------------+-----+
+             *
+             * <---------><----------------><------------------------------><-----------><---->
+             *     8               8                      5                      16         1
+             */
+            #define MAX_CONTEXT_SIZE    38
+
+        #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
+
+            /*
+             * +----------+-----------------+------------------------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+             * +----------+-----------------+------------------------------+-----+
+             *
+             * <---------><----------------><------------------------------><---->
+             *     8               8                      5                   1
+             */
             #define MAX_CONTEXT_SIZE    22
 
+        #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+            /*
+             * +----------+-----------------+----------------------+------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey |     |
+             * |          | PC, xPSR        | EXC_RETURN           |            |     |
+             * +----------+-----------------+----------------------+------------+-----+
+             *
+             * <---------><----------------><----------------------><-----------><---->
+             *     8               8                  4                  16         1
+             */
+            #define MAX_CONTEXT_SIZE    37
+
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-/*
- * +----------+-----------------+----------------------+-----+
- * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
- * |          | PC, xPSR        | EXC_RETURN           |     |
- * +----------+-----------------+----------------------+-----+
- *
- * <---------><----------------><----------------------><---->
- *     8               8                  4              1
- */
+            /*
+             * +----------+-----------------+----------------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+             * |          | PC, xPSR        | EXC_RETURN           |     |
+             * +----------+-----------------+----------------------+-----+
+             *
+             * <---------><----------------><----------------------><---->
+             *     8               8                  4              1
+             */
             #define MAX_CONTEXT_SIZE    21
 
-        #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
     #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
+    /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
-/* Size of an Access Control List (ACL) entry in bits. */
+    /* Size of an Access Control List (ACL) entry in bits. */
     #define portACL_ENTRY_SIZE_BITS             ( 32U )
 
     typedef struct MPU_SETTINGS
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/port.c b/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
index aa9c23816..b2fd7e518 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
@@ -169,79 +169,80 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                            ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                            ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                             ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                            ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                            ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                           ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                           ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK        ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                      ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK                     ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                      ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK                     ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                      ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK                     ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                      ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK                     ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                      ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK                     ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                      ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK                     ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                      ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK                     ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                      ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK                     ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0                    ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1                    ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2                    ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3                    ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4                    ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5                    ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6                    ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7                    ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE                  ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
 
 #if ( portARMV8M_MINOR_VERSION >= 1 )
-    /* Enable Privileged eXecute Never MPU attribute for the selected memory
-     * region. */
-    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER   ( 1UL << 4UL )
+
+/* Enable Privileged eXecute Never MPU attribute for the selected memory
+ * region. */
+    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER    ( 1UL << 4UL )
 #endif /* portARMV8M_MINOR_VERSION >= 1 */
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT          ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                          ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE                 ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -380,14 +381,14 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to check and configure PACBTI security feature implementation.
  */
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
-    #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
+    #define portID_ISAR5_REG       ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
 
-    #define portCONTROL_UPAC_EN      ( 1UL << 7UL )
-    #define portCONTROL_PAC_EN       ( 1UL << 6UL )
-    #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
-    #define portCONTROL_BTI_EN       ( 1UL << 4UL )
+    #define portCONTROL_UPAC_EN    ( 1UL << 7UL )
+    #define portCONTROL_PAC_EN     ( 1UL << 6UL )
+    #define portCONTROL_UBTI_EN    ( 1UL << 5UL )
+    #define portCONTROL_BTI_EN     ( 1UL << 4UL )
 
 #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
@@ -409,7 +410,7 @@ static void prvTaskExitError( void );
  * @return uint32_t Access permissions.
  */
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0  */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 
 #if ( configENABLE_MPU == 1 )
 
@@ -427,7 +428,7 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
 /**
  * @brief Configures PACBTI features.
@@ -890,7 +891,7 @@ static void prvTaskExitError( void )
         return ulAccessPermissions;
     }
 
-#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0  */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
@@ -1212,6 +1213,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
+
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __syscalls_flash_start__;
@@ -1282,6 +1284,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
              * point (i.e. the caller of the MPU_<API>). We need to restore it
              * when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+
             /* Store the value of the PSPLIM register before the SVC was raised.
              * We need to restore it when we exit from the system call. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
@@ -1300,6 +1303,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
             /* Start executing the system call upon returning from this handler. */
             pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
+
             /* Raise a request to exit from the system call upon finishing the
              * system call. */
             pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit;
@@ -1359,6 +1363,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
+
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __privileged_functions_start__;
@@ -1541,7 +1546,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
-        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+        #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
         {
             /* Check PACBTI security feature configuration before pushing the
              * CONTROL register's value on task's TCB. */
@@ -1582,6 +1587,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
+        #if ( configENABLE_PAC == 1 )
+        {
+            uint32_t ulTaskPacKey[ 4 ], i;
+
+            vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+            for( i = 0; i < 4; i++ )
+            {
+                xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ];
+                ulIndex++;
+            }
+        }
+        #endif /* configENABLE_PAC */
+
         return &( xMPUSettings->ulContext[ ulIndex ] );
     }
 
@@ -1664,6 +1683,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #endif /* portPRELOAD_REGISTERS */
 
+        #if ( configENABLE_PAC == 1 )
+        {
+            uint32_t ulTaskPacKey[ 4 ], i;
+
+            vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+            for( i = 0; i < 4; i++ )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = ulTaskPacKey[ i ];
+            }
+        }
+        #endif /* configENABLE_PAC */
+
         return pxTopOfStack;
     }
 
@@ -1786,11 +1819,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
-    #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+    #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
     {
         /* Set the CONTROL register value based on PACBTI security feature
          * configuration before starting the first task. */
-        ( void) prvConfigurePACBTI( pdTRUE );
+        ( void ) prvConfigurePACBTI( pdTRUE );
     }
     #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
@@ -1990,9 +2023,9 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
         if( xSchedulerRunning == pdFALSE )
         {
             /* Grant access to all the kernel objects before the scheduler
-            * is started. It is necessary because there is no task running
-            * yet and therefore, we cannot use the permissions of any
-            * task. */
+             * is started. It is necessary because there is no task running
+             * yet and therefore, we cannot use the permissions of any
+             * task. */
             xAccessGranted = pdTRUE;
         }
         else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
@@ -2213,7 +2246,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
 
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
     {
@@ -2225,13 +2258,13 @@ BaseType_t xPortIsInsideInterrupt( void )
         /* Enable UsageFault exception. */
         portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
 
-        #if( configENABLE_PAC == 1 )
+        #if ( configENABLE_PAC == 1 )
         {
             ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
         }
         #endif
 
-        #if( configENABLE_BTI == 1 )
+        #if ( configENABLE_BTI == 1 )
         {
             ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
         }
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.c b/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.c
index 7cdff7005..bc7bb6071 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.c
@@ -77,16 +77,16 @@
             "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
             "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
             "                                                 \n"
-            #if ( configTOTAL_MPU_REGIONS == 16 )
-                "    movs r3, #8                                  \n" /* r3 = 8. */
-                "    str r3, [r1]                                 \n" /* Program RNR = 8. */
-                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-                "    movs r3, #12                                 \n" /* r3 = 12. */
-                "    str r3, [r1]                                 \n" /* Program RNR = 12. */
-                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-            #endif /* configTOTAL_MPU_REGIONS == 16 */
+        #if ( configTOTAL_MPU_REGIONS == 16 )
+            "    movs r3, #8                                  \n" /* r3 = 8. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 8. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "    movs r3, #12                                 \n" /* r3 = 12. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 12. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+        #endif /* configTOTAL_MPU_REGIONS == 16 */
             "                                                 \n"
             "   ldr r1, =0xe000ed94                           \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
@@ -100,6 +100,14 @@
             "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
             "                                                 \n"
             " restore_special_regs_first_task:                \n"
+        #if ( configENABLE_PAC == 1 )
+            "   ldmdb r1!, {r2-r5}                            \n" /* Read task's dedicated PAC key from the task's context. */
+            "   msr  PAC_KEY_P_0, r2                          \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+            "   msr  PAC_KEY_P_1, r3                          \n"
+            "   msr  PAC_KEY_P_2, r4                          \n"
+            "   msr  PAC_KEY_P_3, r5                          \n"
+            "   clrm {r2-r5}                                  \n" /* Clear r2-r5. */
+        #endif /* configENABLE_PAC */
             "    ldmdb r1!, {r2-r4, lr}                       \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
             "    msr psp, r2                                  \n"
             "    msr psplim, r3                               \n"
@@ -130,6 +138,15 @@
             "   ldr  r1, [r2]                                   \n" /* Read pxCurrentTCB. */
             "   ldr  r0, [r1]                                   \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
             "                                                   \n"
+        #if ( configENABLE_PAC == 1 )
+            "   ldmia r0!, {r1-r4}                              \n" /* Read task's dedicated PAC key from stack. */
+            "   msr  PAC_KEY_P_3, r1                            \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+            "   msr  PAC_KEY_P_2, r2                            \n"
+            "   msr  PAC_KEY_P_1, r3                            \n"
+            "   msr  PAC_KEY_P_0, r4                            \n"
+            "   clrm {r1-r4}                                    \n" /* Clear r1-r4. */
+        #endif /* configENABLE_PAC */
+            "                                                   \n"
             "   ldm  r0!, {r1-r2}                               \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
             "   msr  psplim, r1                                 \n" /* Set this task's PSPLIM value. */
             "   mrs  r1, control                                \n" /* Obtain current control register value. */
@@ -261,16 +278,15 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             " mrs r2, psp                                     \n" /* r2 = PSP. */
             "                                                 \n"
             " save_general_regs:                              \n"
-            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-                "    add r2, r2, #0x20                            \n" /* Move r2 to location where s0 is saved. */
-                "    tst lr, #0x10                                \n"
-                "    ittt eq                                      \n"
-                "    vstmiaeq r1!, {s16-s31}                      \n" /* Store s16-s31. */
-                "    vldmiaeq r2, {s0-s16}                        \n" /* Copy hardware saved FP context into s0-s16. */
-                "    vstmiaeq r1!, {s0-s16}                       \n" /* Store hardware saved FP context. */
-                "    sub r2, r2, #0x20                            \n" /* Set r2 back to the location of hardware saved context. */
-            #endif /* configENABLE_FPU || configENABLE_MVE */
-            "                                                 \n"
+        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            "    add r2, r2, #0x20                            \n" /* Move r2 to location where s0 is saved. */
+            "    tst lr, #0x10                                \n"
+            "    ittt eq                                      \n"
+            "    vstmiaeq r1!, {s16-s31}                      \n" /* Store s16-s31. */
+            "    vldmiaeq r2, {s0-s16}                        \n" /* Copy hardware saved FP context into s0-s16. */
+            "    vstmiaeq r1!, {s0-s16}                       \n" /* Store hardware saved FP context. */
+            "    sub r2, r2, #0x20                            \n" /* Set r2 back to the location of hardware saved context. */
+        #endif /* configENABLE_FPU || configENABLE_MVE */
             "    stmia r1!, {r4-r11}                          \n" /* Store r4-r11. */
             "    ldmia r2, {r4-r11}                           \n" /* Copy the hardware saved context into r4-r11. */
             "    stmia r1!, {r4-r11}                          \n" /* Store the hardware saved context. */
@@ -279,6 +295,14 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    mrs r3, psplim                               \n" /* r3 = PSPLIM. */
             "    mrs r4, control                              \n" /* r4 = CONTROL. */
             "    stmia r1!, {r2-r4, lr}                       \n" /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
+        #if ( configENABLE_PAC == 1 )
+            "   mrs  r2, PAC_KEY_P_0                          \n" /* Read task's dedicated PAC key from the PAC key registers. */
+            "   mrs  r3, PAC_KEY_P_1                          \n"
+            "   mrs  r4, PAC_KEY_P_2                          \n"
+            "   mrs  r5, PAC_KEY_P_3                          \n"
+            "   stmia r1!, {r2-r5}                            \n" /* Store the task's dedicated PAC key on the task's context. */
+            "   clrm {r2-r5}                                  \n" /* Clear r2-r5. */
+        #endif /* configENABLE_PAC */
             "    str r1, [r0]                                 \n" /* Save the location from where the context should be restored as the first member of TCB. */
             "                                                 \n"
             " select_next_task:                               \n"
@@ -314,16 +338,16 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
             "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
             "                                                 \n"
-            #if ( configTOTAL_MPU_REGIONS == 16 )
-                "    movs r3, #8                                  \n" /* r3 = 8. */
-                "    str r3, [r1]                                 \n" /* Program RNR = 8. */
-                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-                "    movs r3, #12                                 \n" /* r3 = 12. */
-                "    str r3, [r1]                                 \n" /* Program RNR = 12. */
-                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-            #endif /* configTOTAL_MPU_REGIONS == 16 */
+        #if ( configTOTAL_MPU_REGIONS == 16 )
+            "    movs r3, #8                                  \n" /* r3 = 8. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 8. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "    movs r3, #12                                 \n" /* r3 = 12. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 12. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+        #endif /* configTOTAL_MPU_REGIONS == 16 */
             "                                                 \n"
             "   ldr r1, =0xe000ed94                           \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
@@ -337,6 +361,14 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
             "                                                 \n"
             " restore_special_regs:                           \n"
+        #if ( configENABLE_PAC == 1 )
+            "   ldmdb r1!, {r2-r5}                            \n" /* Read task's dedicated PAC key from the task's context. */
+            "   msr  PAC_KEY_P_0, r2                          \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+            "   msr  PAC_KEY_P_1, r3                          \n"
+            "   msr  PAC_KEY_P_2, r4                          \n"
+            "   msr  PAC_KEY_P_3, r5                          \n"
+            "   clrm {r2-r5}                                  \n" /* Clear r2-r5. */
+        #endif /* configENABLE_PAC */
             "    ldmdb r1!, {r2-r4, lr}                       \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
             "    msr psp, r2                                  \n"
             "    msr psplim, r3                               \n"
@@ -346,13 +378,13 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
             "    stmia r2!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
             "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 restored. */
-            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-                "    tst lr, #0x10                                \n"
-                "    ittt eq                                      \n"
-                "    vldmdbeq r1!, {s0-s16}                       \n" /* s0-s16 contain hardware saved FP context. */
-                "    vstmiaeq r2!, {s0-s16}                       \n" /* Copy hardware saved FP context on the task stack. */
-                "    vldmdbeq r1!, {s16-s31}                      \n" /* Restore s16-s31. */
-            #endif /* configENABLE_FPU || configENABLE_MVE */
+        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            "    tst lr, #0x10                                \n"
+            "    ittt eq                                      \n"
+            "    vldmdbeq r1!, {s0-s16}                       \n" /* s0-s16 contain hardware saved FP context. */
+            "    vstmiaeq r2!, {s0-s16}                       \n" /* Copy hardware saved FP context on the task stack. */
+            "    vldmdbeq r1!, {s16-s31}                      \n" /* Restore s16-s31. */
+        #endif /* configENABLE_FPU || configENABLE_MVE */
             "                                                 \n"
             " restore_context_done:                           \n"
             "    str r1, [r0]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
@@ -371,16 +403,25 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "                                                   \n"
             "   mrs r0, psp                                     \n" /* Read PSP in r0. */
             "                                                   \n"
-            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-                "   tst lr, #0x10                                   \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
-                "   it eq                                           \n"
-                "   vstmdbeq r0!, {s16-s31}                         \n" /* Store the additional FP context registers which are not saved automatically. */
-            #endif /* configENABLE_FPU || configENABLE_MVE */
+        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            "   tst lr, #0x10                                   \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+            "   it eq                                           \n"
+            "   vstmdbeq r0!, {s16-s31}                         \n" /* Store the additional FP context registers which are not saved automatically. */
+        #endif /* configENABLE_FPU || configENABLE_MVE */
             "                                                   \n"
             "   mrs r2, psplim                                  \n" /* r2 = PSPLIM. */
             "   mov r3, lr                                      \n" /* r3 = LR/EXC_RETURN. */
             "   stmdb r0!, {r2-r11}                             \n" /* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */
             "                                                   \n"
+        #if ( configENABLE_PAC == 1 )
+            "   mrs  r1, PAC_KEY_P_3                            \n" /* Read task's dedicated PAC key from the PAC key registers. */
+            "   mrs  r2, PAC_KEY_P_2                            \n"
+            "   mrs  r3, PAC_KEY_P_1                            \n"
+            "   mrs  r4, PAC_KEY_P_0                            \n"
+            "   stmdb r0!, {r1-r4}                              \n" /* Store the task's dedicated PAC key on the stack. */
+            "   clrm {r1-r4}                                    \n" /* Clear r1-r4. */
+        #endif /* configENABLE_PAC */
+            "                                                   \n"
             "   ldr r2, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr r1, [r2]                                    \n" /* Read pxCurrentTCB. */
             "   str r0, [r1]                                    \n" /* Save the new top of stack in TCB. */
@@ -397,13 +438,22 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   ldr r1, [r2]                                    \n" /* Read pxCurrentTCB. */
             "   ldr r0, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
             "                                                   \n"
+        #if ( configENABLE_PAC == 1 )
+            "   ldmia r0!, {r2-r5}                              \n" /* Read task's dedicated PAC key from stack. */
+            "   msr  PAC_KEY_P_3, r2                            \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+            "   msr  PAC_KEY_P_2, r3                            \n"
+            "   msr  PAC_KEY_P_1, r4                            \n"
+            "   msr  PAC_KEY_P_0, r5                            \n"
+            "   clrm {r2-r5}                                    \n" /* Clear r2-r5. */
+        #endif /* configENABLE_PAC */
+            "                                                   \n"
             "   ldmia r0!, {r2-r11}                             \n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
             "                                                   \n"
-            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-                "   tst r3, #0x10                                   \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
-                "   it eq                                           \n"
-                "   vldmiaeq r0!, {s16-s31}                         \n" /* Restore the additional FP context registers which are not restored automatically. */
-            #endif /* configENABLE_FPU || configENABLE_MVE */
+        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            "   tst r3, #0x10                                   \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+            "   it eq                                           \n"
+            "   vldmiaeq r0!, {s16-s31}                         \n" /* Restore the additional FP context registers which are not restored automatically. */
+        #endif /* configENABLE_FPU || configENABLE_MVE */
             "                                                   \n"
             "   msr psplim, r2                                  \n" /* Restore the PSPLIM register value for the task. */
             "   msr psp, r0                                     \n" /* Remember the new top of stack for the task. */
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h
index 8a8dc7d6a..e74fa8257 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -125,6 +127,18 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
     extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
 #endif /* configENABLE_MPU */
+
+#if ( configENABLE_PAC == 1 )
+
+    /**
+     * @brief Generates 128-bit task's random PAC key.
+     *
+     * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be
+     *             filled with a 128-bit random number.
+     */
+    void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey );
+
+#endif /* configENABLE_PAC */
 /*-----------------------------------------------------------*/
 
 /**
@@ -188,9 +202,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Settings to define an MPU region.
- */
+    /**
+     * @brief Settings to define an MPU region.
+     */
     typedef struct MPURegionSettings
     {
         uint32_t ulRBAR; /**< RBAR for the region. */
@@ -203,9 +217,14 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-/**
- * @brief System call stack.
- */
+        /* When MPU wrapper v2 is used, the task's context is stored in TCB and
+         * pxTopOfStack member of TCB points to the context location in TCB. We,
+         * therefore, need to read PSP to find the task's current top of stack. */
+        #define portGET_CURRENT_TOP_OF_STACK( pxCurrentTopOfStack ) { __asm volatile ( "mrs %0, psp"  : "=r" ( pxCurrentTopOfStack ) ); }
+
+        /**
+         * @brief System call stack.
+         */
         typedef struct SYSTEM_CALL_STACK_INFO
         {
             uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ];
@@ -218,76 +237,128 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
-/**
- * @brief MPU settings as stored in the TCB.
- */
+    /**
+     * @brief MPU settings as stored in the TCB.
+     */
     #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+        #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +-----------+---------------+----------+-----------------+------------------------------+-----+
- * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
- * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
- * +-----------+---------------+----------+-----------------+------------------------------+-----+
- *
- * <-----------><--------------><---------><----------------><-----------------------------><---->
- *      16             16            8               8                     5                   1
- */
+            /*
+             * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey |     |
+             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |            |     |
+             * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
+             *      16             16            8               8                     5                     16         1
+             */
+            #define MAX_CONTEXT_SIZE    70
+
+        #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
+
+            /*
+             * +-----------+---------------+----------+-----------------+------------------------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+             * +-----------+---------------+----------+-----------------+------------------------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><-----------------------------><---->
+             *      16             16            8               8                     5                   1
+             */
             #define MAX_CONTEXT_SIZE    54
 
-        #else /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +-----------+---------------+----------+-----------------+----------------------+-----+
- * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
- * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
- * +-----------+---------------+----------+-----------------+----------------------+-----+
- *
- * <-----------><--------------><---------><----------------><---------------------><---->
- *      16             16            8               8                  4              1
- */
+            /*
+             * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey |     |
+             * |           |               |          | PC, xPSR        | EXC_RETURN           |            |     |
+             * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><---------------------><-----------><---->
+             *      16             16            8               8                  4                16         1
+             */
+            #define MAX_CONTEXT_SIZE    69
+
+        #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
+
+            /*
+             * +-----------+---------------+----------+-----------------+----------------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+             * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
+             * +-----------+---------------+----------+-----------------+----------------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><---------------------><---->
+             *      16             16            8               8                  4              1
+             */
             #define MAX_CONTEXT_SIZE    53
 
-        #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
     #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+        #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +----------+-----------------+------------------------------+-----+
- * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
- * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
- * +----------+-----------------+------------------------------+-----+
- *
- * <---------><----------------><------------------------------><---->
- *     8               8                      5                   1
- */
+            /*
+             * +----------+-----------------+------------------------------+------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey |     |
+             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |            |     |
+             * +----------+-----------------+------------------------------+------------+-----+
+             *
+             * <---------><----------------><------------------------------><-----------><---->
+             *     8               8                      5                      16         1
+             */
+            #define MAX_CONTEXT_SIZE    38
+
+        #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
+
+            /*
+             * +----------+-----------------+------------------------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+             * +----------+-----------------+------------------------------+-----+
+             *
+             * <---------><----------------><------------------------------><---->
+             *     8               8                      5                   1
+             */
             #define MAX_CONTEXT_SIZE    22
 
+        #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+            /*
+             * +----------+-----------------+----------------------+------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey |     |
+             * |          | PC, xPSR        | EXC_RETURN           |            |     |
+             * +----------+-----------------+----------------------+------------+-----+
+             *
+             * <---------><----------------><----------------------><-----------><---->
+             *     8               8                  4                  16         1
+             */
+            #define MAX_CONTEXT_SIZE    37
+
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-/*
- * +----------+-----------------+----------------------+-----+
- * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
- * |          | PC, xPSR        | EXC_RETURN           |     |
- * +----------+-----------------+----------------------+-----+
- *
- * <---------><----------------><----------------------><---->
- *     8               8                  4              1
- */
+            /*
+             * +----------+-----------------+----------------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+             * |          | PC, xPSR        | EXC_RETURN           |     |
+             * +----------+-----------------+----------------------+-----+
+             *
+             * <---------><----------------><----------------------><---->
+             *     8               8                  4              1
+             */
             #define MAX_CONTEXT_SIZE    21
 
-        #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
     #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
+    /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
-/* Size of an Access Control List (ACL) entry in bits. */
+    /* Size of an Access Control List (ACL) entry in bits. */
     #define portACL_ENTRY_SIZE_BITS             ( 32U )
 
     typedef struct MPU_SETTINGS
diff --git a/portable/GCC/ARM_CM85/non_secure/port.c b/portable/GCC/ARM_CM85/non_secure/port.c
index aa9c23816..b2fd7e518 100644
--- a/portable/GCC/ARM_CM85/non_secure/port.c
+++ b/portable/GCC/ARM_CM85/non_secure/port.c
@@ -169,79 +169,80 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                            ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                            ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                             ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                            ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                            ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                           ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                           ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK        ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                      ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK                     ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                      ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK                     ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                      ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK                     ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                      ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK                     ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                      ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK                     ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                      ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK                     ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                      ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK                     ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                      ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK                     ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0                    ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1                    ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2                    ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3                    ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4                    ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5                    ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6                    ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7                    ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE                  ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
 
 #if ( portARMV8M_MINOR_VERSION >= 1 )
-    /* Enable Privileged eXecute Never MPU attribute for the selected memory
-     * region. */
-    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER   ( 1UL << 4UL )
+
+/* Enable Privileged eXecute Never MPU attribute for the selected memory
+ * region. */
+    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER    ( 1UL << 4UL )
 #endif /* portARMV8M_MINOR_VERSION >= 1 */
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT          ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                          ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE                 ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -380,14 +381,14 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to check and configure PACBTI security feature implementation.
  */
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
-    #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
+    #define portID_ISAR5_REG       ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
 
-    #define portCONTROL_UPAC_EN      ( 1UL << 7UL )
-    #define portCONTROL_PAC_EN       ( 1UL << 6UL )
-    #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
-    #define portCONTROL_BTI_EN       ( 1UL << 4UL )
+    #define portCONTROL_UPAC_EN    ( 1UL << 7UL )
+    #define portCONTROL_PAC_EN     ( 1UL << 6UL )
+    #define portCONTROL_UBTI_EN    ( 1UL << 5UL )
+    #define portCONTROL_BTI_EN     ( 1UL << 4UL )
 
 #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
@@ -409,7 +410,7 @@ static void prvTaskExitError( void );
  * @return uint32_t Access permissions.
  */
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0  */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 
 #if ( configENABLE_MPU == 1 )
 
@@ -427,7 +428,7 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
 /**
  * @brief Configures PACBTI features.
@@ -890,7 +891,7 @@ static void prvTaskExitError( void )
         return ulAccessPermissions;
     }
 
-#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0  */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
@@ -1212,6 +1213,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
+
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __syscalls_flash_start__;
@@ -1282,6 +1284,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
              * point (i.e. the caller of the MPU_<API>). We need to restore it
              * when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+
             /* Store the value of the PSPLIM register before the SVC was raised.
              * We need to restore it when we exit from the system call. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
@@ -1300,6 +1303,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
             /* Start executing the system call upon returning from this handler. */
             pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
+
             /* Raise a request to exit from the system call upon finishing the
              * system call. */
             pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit;
@@ -1359,6 +1363,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
+
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __privileged_functions_start__;
@@ -1541,7 +1546,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
-        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+        #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
         {
             /* Check PACBTI security feature configuration before pushing the
              * CONTROL register's value on task's TCB. */
@@ -1582,6 +1587,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
+        #if ( configENABLE_PAC == 1 )
+        {
+            uint32_t ulTaskPacKey[ 4 ], i;
+
+            vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+            for( i = 0; i < 4; i++ )
+            {
+                xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ];
+                ulIndex++;
+            }
+        }
+        #endif /* configENABLE_PAC */
+
         return &( xMPUSettings->ulContext[ ulIndex ] );
     }
 
@@ -1664,6 +1683,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #endif /* portPRELOAD_REGISTERS */
 
+        #if ( configENABLE_PAC == 1 )
+        {
+            uint32_t ulTaskPacKey[ 4 ], i;
+
+            vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+            for( i = 0; i < 4; i++ )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = ulTaskPacKey[ i ];
+            }
+        }
+        #endif /* configENABLE_PAC */
+
         return pxTopOfStack;
     }
 
@@ -1786,11 +1819,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
-    #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+    #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
     {
         /* Set the CONTROL register value based on PACBTI security feature
          * configuration before starting the first task. */
-        ( void) prvConfigurePACBTI( pdTRUE );
+        ( void ) prvConfigurePACBTI( pdTRUE );
     }
     #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
@@ -1990,9 +2023,9 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
         if( xSchedulerRunning == pdFALSE )
         {
             /* Grant access to all the kernel objects before the scheduler
-            * is started. It is necessary because there is no task running
-            * yet and therefore, we cannot use the permissions of any
-            * task. */
+             * is started. It is necessary because there is no task running
+             * yet and therefore, we cannot use the permissions of any
+             * task. */
             xAccessGranted = pdTRUE;
         }
         else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
@@ -2213,7 +2246,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
 
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
     {
@@ -2225,13 +2258,13 @@ BaseType_t xPortIsInsideInterrupt( void )
         /* Enable UsageFault exception. */
         portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
 
-        #if( configENABLE_PAC == 1 )
+        #if ( configENABLE_PAC == 1 )
         {
             ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
         }
         #endif
 
-        #if( configENABLE_BTI == 1 )
+        #if ( configENABLE_BTI == 1 )
         {
             ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
         }
diff --git a/portable/GCC/ARM_CM85/non_secure/portasm.c b/portable/GCC/ARM_CM85/non_secure/portasm.c
index aaeccaa35..0ebbe48a4 100644
--- a/portable/GCC/ARM_CM85/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM85/non_secure/portasm.c
@@ -77,16 +77,16 @@
             "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
             "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
             "                                                 \n"
-            #if ( configTOTAL_MPU_REGIONS == 16 )
-                "    movs r3, #8                                  \n" /* r3 = 8. */
-                "    str r3, [r1]                                 \n" /* Program RNR = 8. */
-                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
-                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-                "    movs r3, #12                                 \n" /* r3 = 12. */
-                "    str r3, [r1]                                 \n" /* Program RNR = 12. */
-                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
-                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-            #endif /* configTOTAL_MPU_REGIONS == 16 */
+        #if ( configTOTAL_MPU_REGIONS == 16 )
+            "    movs r3, #8                                  \n" /* r3 = 8. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 8. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "    movs r3, #12                                 \n" /* r3 = 12. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 12. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+        #endif /* configTOTAL_MPU_REGIONS == 16 */
             "                                                 \n"
             "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
@@ -100,6 +100,14 @@
             "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
             "                                                 \n"
             " restore_special_regs_first_task:                \n"
+        #if ( configENABLE_PAC == 1 )
+            "   ldmdb r2!, {r3-r6}                            \n" /* Read task's dedicated PAC key from the task's context. */
+            "   msr  PAC_KEY_P_0, r3                          \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+            "   msr  PAC_KEY_P_1, r4                          \n"
+            "   msr  PAC_KEY_P_2, r5                          \n"
+            "   msr  PAC_KEY_P_3, r6                          \n"
+            "   clrm {r3-r6}                                  \n" /* Clear r3-r6. */
+        #endif /* configENABLE_PAC */
             "    ldmdb r2!, {r0, r3-r5, lr}                   \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
             "    msr psp, r3                                  \n"
             "    msr psplim, r4                               \n"
@@ -132,6 +140,15 @@
             "   ldr  r3, [r2]                                   \n" /* Read pxCurrentTCB. */
             "   ldr  r0, [r3]                                   \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
             "                                                   \n"
+        #if ( configENABLE_PAC == 1 )
+            "   ldmia r0!, {r1-r4}                              \n" /* Read task's dedicated PAC key from stack. */
+            "   msr  PAC_KEY_P_3, r1                            \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+            "   msr  PAC_KEY_P_2, r2                            \n"
+            "   msr  PAC_KEY_P_1, r3                            \n"
+            "   msr  PAC_KEY_P_0, r4                            \n"
+            "   clrm {r1-r4}                                    \n" /* Clear r1-r4. */
+        #endif /* configENABLE_PAC */
+            "                                                   \n"
             "   ldm  r0!, {r1-r3}                               \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
             "   ldr  r4, =xSecureContext                        \n"
             "   str  r1, [r4]                                   \n" /* Set xSecureContext to this task's value for the same. */
@@ -280,17 +297,15 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "                                                 \n"
             " save_general_regs:                              \n"
             "    mrs r3, psp                                  \n"
-            "                                                 \n"
-            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-                "    add r3, r3, #0x20                            \n" /* Move r3 to location where s0 is saved. */
-                "    tst lr, #0x10                                \n"
-                "    ittt eq                                      \n"
-                "    vstmiaeq r2!, {s16-s31}                      \n" /* Store s16-s31. */
-                "    vldmiaeq r3, {s0-s16}                        \n" /* Copy hardware saved FP context into s0-s16. */
-                "    vstmiaeq r2!, {s0-s16}                       \n" /* Store hardware saved FP context. */
-                "    sub r3, r3, #0x20                            \n" /* Set r3 back to the location of hardware saved context. */
-            #endif /* configENABLE_FPU || configENABLE_MVE */
-            "                                                 \n"
+        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            "    add r3, r3, #0x20                            \n" /* Move r3 to location where s0 is saved. */
+            "    tst lr, #0x10                                \n"
+            "    ittt eq                                      \n"
+            "    vstmiaeq r2!, {s16-s31}                      \n" /* Store s16-s31. */
+            "    vldmiaeq r3, {s0-s16}                        \n" /* Copy hardware saved FP context into s0-s16. */
+            "    vstmiaeq r2!, {s0-s16}                       \n" /* Store hardware saved FP context. */
+            "    sub r3, r3, #0x20                            \n" /* Set r3 back to the location of hardware saved context. */
+        #endif /* configENABLE_FPU || configENABLE_MVE */
             "    stmia r2!, {r4-r11}                          \n" /* Store r4-r11. */
             "    ldmia r3, {r4-r11}                           \n" /* Copy the hardware saved context into r4-r11. */
             "    stmia r2!, {r4-r11}                          \n" /* Store the hardware saved context. */
@@ -300,7 +315,15 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    mrs r4, psplim                               \n" /* r4 = PSPLIM. */
             "    mrs r5, control                              \n" /* r5 = CONTROL. */
             "    stmia r2!, {r0, r3-r5, lr}                   \n" /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
-            "    str r2, [r1]                                 \n" /* Save the location from where the context should be restored as the first member of TCB. */
+        #if ( configENABLE_PAC == 1 )
+            "   mrs  r3, PAC_KEY_P_0                          \n" /* Read task's dedicated PAC key from the PAC key registers. */
+            "   mrs  r4, PAC_KEY_P_1                          \n"
+            "   mrs  r5, PAC_KEY_P_2                          \n"
+            "   mrs  r6, PAC_KEY_P_3                          \n"
+            "   stmia r2!, {r3-r6}                            \n" /* Store the task's dedicated PAC key on the task's context. */
+            "   clrm {r3-r6}                                  \n" /* Clear r3-r6. */
+        #endif /* configENABLE_PAC */
+            "    str r2, [r1]                                 \n"      /* Save the location from where the context should be restored as the first member of TCB. */
             "                                                 \n"
             " select_next_task:                               \n"
             "    mov r0, %0                                   \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
@@ -335,16 +358,16 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
             "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
             "                                                 \n"
-            #if ( configTOTAL_MPU_REGIONS == 16 )
-                "    movs r3, #8                                  \n" /* r3 = 8. */
-                "    str r3, [r1]                                 \n" /* Program RNR = 8. */
-                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-                "    movs r3, #12                                 \n" /* r3 = 12. */
-                "    str r3, [r1]                                 \n" /* Program RNR = 12. */
-                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-            #endif /* configTOTAL_MPU_REGIONS == 16 */
+        #if ( configTOTAL_MPU_REGIONS == 16 )
+            "    movs r3, #8                                  \n" /* r3 = 8. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 8. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "    movs r3, #12                                 \n" /* r3 = 12. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 12. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+        #endif /* configTOTAL_MPU_REGIONS == 16 */
             "                                                 \n"
             "   ldr r1, =0xe000ed94                           \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
@@ -358,6 +381,14 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
             "                                                 \n"
             " restore_special_regs:                           \n"
+        #if ( configENABLE_PAC == 1 )
+            "   ldmdb r2!, {r3-r6}                            \n" /* Read task's dedicated PAC key from the task's context. */
+            "   msr  PAC_KEY_P_0, r3                          \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+            "   msr  PAC_KEY_P_1, r4                          \n"
+            "   msr  PAC_KEY_P_2, r5                          \n"
+            "   msr  PAC_KEY_P_3, r6                          \n"
+            "   clrm {r3-r6}                                  \n" /* Clear r3-r6. */
+        #endif /* configENABLE_PAC */
             "    ldmdb r2!, {r0, r3-r5, lr}                   \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
             "    msr psp, r3                                  \n"
             "    msr psplim, r4                               \n"
@@ -380,13 +411,13 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
             "    stmia r3!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
             "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 restored. */
-            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-                "    tst lr, #0x10                                \n"
-                "    ittt eq                                      \n"
-                "    vldmdbeq r2!, {s0-s16}                       \n" /* s0-s16 contain hardware saved FP context. */
-                "    vstmiaeq r3!, {s0-s16}                       \n" /* Copy hardware saved FP context on the task stack. */
-                "    vldmdbeq r2!, {s16-s31}                      \n" /* Restore s16-s31. */
-            #endif /* configENABLE_FPU || configENABLE_MVE */
+        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            "    tst lr, #0x10                                \n"
+            "    ittt eq                                      \n"
+            "    vldmdbeq r2!, {s0-s16}                       \n" /* s0-s16 contain hardware saved FP context. */
+            "    vstmiaeq r3!, {s0-s16}                       \n" /* Copy hardware saved FP context on the task stack. */
+            "    vldmdbeq r2!, {s16-s31}                      \n" /* Restore s16-s31. */
+        #endif /* configENABLE_FPU || configENABLE_MVE */
             "                                                 \n"
             " restore_context_done:                           \n"
             "    str r2, [r1]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
@@ -401,89 +432,99 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
     {
         __asm volatile
         (
-            "   .syntax unified                                 \n"
-            "   .extern SecureContext_SaveContext               \n"
-            "   .extern SecureContext_LoadContext               \n"
-            "                                                   \n"
-            "   ldr r3, =xSecureContext                         \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-            "   ldr r0, [r3]                                    \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
-            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
-            "   mrs r2, psp                                     \n" /* Read PSP in r2. */
-            "                                                   \n"
-            "   cbz r0, save_ns_context                         \n" /* No secure context to save. */
-            "   push {r0-r2, r14}                               \n"
-            "   bl SecureContext_SaveContext                    \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-            "   pop {r0-r3}                                     \n" /* LR is now in r3. */
-            "   mov lr, r3                                      \n" /* LR = r3. */
-            "   lsls r1, r3, #25                                \n" /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-            "   bpl save_ns_context                             \n" /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-            "                                                   \n"
-            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB.*/
-            "   subs r2, r2, #12                                \n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */
-            "   str r2, [r1]                                    \n" /* Save the new top of stack in TCB. */
-            "   mrs r1, psplim                                  \n" /* r1 = PSPLIM. */
-            "   mov r3, lr                                      \n" /* r3 = LR/EXC_RETURN. */
-            "   stmia r2!, {r0, r1, r3}                         \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
-            "   b select_next_task                              \n"
-            "                                                   \n"
-            " save_ns_context:                                  \n"
-            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
-            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-                "   tst lr, #0x10                               \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
-                "   it eq                                       \n"
-                "   vstmdbeq r2!, {s16-s31}                     \n" /* Store the additional FP context registers which are not saved automatically. */
-            #endif /* configENABLE_FPU || configENABLE_MVE */
-            "   subs r2, r2, #44                                \n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
-            "   str r2, [r1]                                    \n" /* Save the new top of stack in TCB. */
-            "   adds r2, r2, #12                                \n" /* r2 = r2 + 12. */
-            "   stm r2, {r4-r11}                                \n" /* Store the registers that are not saved automatically. */
-            "   mrs r1, psplim                                  \n" /* r1 = PSPLIM. */
-            "   mov r3, lr                                      \n" /* r3 = LR/EXC_RETURN. */
-            "   subs r2, r2, #12                                \n" /* r2 = r2 - 12. */
-            "   stmia r2!, {r0, r1, r3}                         \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
-            "                                                   \n"
-            " select_next_task:                                 \n"
-            "   mov r0, %0                                      \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
-            "   msr basepri, r0                                 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-            "   dsb                                             \n"
-            "   isb                                             \n"
-            "   bl vTaskSwitchContext                           \n"
-            "   mov r0, #0                                      \n" /* r0 = 0. */
-            "   msr basepri, r0                                 \n" /* Enable interrupts. */
-            "                                                   \n"
-            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
-            "   ldr r2, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
-            "                                                   \n"
-            "   ldmia r2!, {r0, r1, r4}                         \n" /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
-            "   msr psplim, r1                                  \n" /* Restore the PSPLIM register value for the task. */
-            "   mov lr, r4                                      \n" /* LR = r4. */
-            "   ldr r3, =xSecureContext                         \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-            "   str r0, [r3]                                    \n" /* Restore the task's xSecureContext. */
-            "   cbz r0, restore_ns_context                      \n" /* If there is no secure context for the task, restore the non-secure context. */
-            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
-            "   push {r2, r4}                                   \n"
-            "   bl SecureContext_LoadContext                    \n" /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-            "   pop {r2, r4}                                    \n"
-            "   mov lr, r4                                      \n" /* LR = r4. */
-            "   lsls r1, r4, #25                                \n" /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-            "   bpl restore_ns_context                          \n" /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-            "   msr psp, r2                                     \n" /* Remember the new top of stack for the task. */
-            "   bx lr                                           \n"
-            "                                                   \n"
-            " restore_ns_context:                               \n"
-            "   ldmia r2!, {r4-r11}                             \n" /* Restore the registers that are not automatically restored. */
-            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-                "   tst lr, #0x10                               \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
-                "   it eq                                       \n"
-                "   vldmiaeq r2!, {s16-s31}                     \n" /* Restore the additional FP context registers which are not restored automatically. */
-            #endif /* configENABLE_FPU || configENABLE_MVE */
-            "   msr psp, r2                                     \n" /* Remember the new top of stack for the task. */
-            "   bx lr                                           \n"
+            " .syntax unified                                 \n"
+            " .extern SecureContext_SaveContext               \n"
+            " .extern SecureContext_LoadContext               \n"
+            "                                                 \n"
+            " ldr r3, =xSecureContext                         \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            " ldr r0, [r3]                                    \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+            " ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            " ldr r1, [r3]                                    \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
+            " mrs r2, psp                                     \n" /* Read PSP in r2. */
+            "                                                 \n"
+            " cbz r0, save_ns_context                         \n" /* No secure context to save. */
+            " save_s_context:                                 \n"
+            "    push {r0-r2, lr}                             \n"
+            "    bl SecureContext_SaveContext                 \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+            "    pop {r0-r2, lr}                              \n"
+            "                                                 \n"
+            " save_ns_context:                                \n"
+            "    mov r3, lr                                   \n" /* r3 = LR (EXC_RETURN). */
+            "    lsls r3, r3, #25                             \n" /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+            "    bmi save_special_regs                        \n" /* If r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used. */
+            "                                                 \n"
+            " save_general_regs:                              \n"
+        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            "    tst lr, #0x10                                \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+            "    it eq                                        \n"
+            "    vstmdbeq r2!, {s16-s31}                      \n" /* Store the additional FP context registers which are not saved automatically. */
+        #endif /* configENABLE_FPU || configENABLE_MVE */
+            "   stmdb r2!, {r4-r11}                           \n" /* Store the registers that are not saved automatically. */
+            "                                                 \n"
+            " save_special_regs:                              \n"
+            "    mrs r3, psplim                               \n" /* r3 = PSPLIM. */
+            "    stmdb r2!, {r0, r3, lr}                      \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
+        #if ( configENABLE_PAC == 1 )
+            "    mrs  r3, PAC_KEY_P_3                         \n" /* Read task's dedicated PAC key from the PAC key registers. */
+            "    mrs  r4, PAC_KEY_P_2                         \n"
+            "    mrs  r5, PAC_KEY_P_1                         \n"
+            "    mrs  r6, PAC_KEY_P_0                         \n"
+            "    stmdb r2!, {r3-r6}                           \n" /* Store the task's dedicated PAC key on the stack. */
+            "    clrm {r3-r6}                                 \n" /* Clear r3-r6. */
+        #endif /* configENABLE_PAC */
+            "                                                 \n"
+            " str r2, [r1]                                    \n" /* Save the new top of stack in TCB. */
+            "                                                 \n"
+            " select_next_task:                               \n"
+            "    mov r0, %0                                   \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
+            "    msr basepri, r0                              \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+            "    dsb                                          \n"
+            "    isb                                          \n"
+            "    bl vTaskSwitchContext                        \n"
+            "    mov r0, #0                                   \n" /* r0 = 0. */
+            "    msr basepri, r0                              \n" /* Enable interrupts. */
+            "                                                 \n"
+            " restore_context:                                \n"
+            "    ldr r3, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r1, [r3]                                 \n" /* Read pxCurrentTCB. */
+            "    ldr r2, [r1]                                 \n" /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
+            "                                                 \n"
+            " restore_special_regs:                           \n"
+        #if ( configENABLE_PAC == 1 )
+            "    ldmia r2!, {r3-r6}                           \n" /* Read task's dedicated PAC key from stack. */
+            "    msr  PAC_KEY_P_3, r3                         \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+            "    msr  PAC_KEY_P_2, r4                         \n"
+            "    msr  PAC_KEY_P_1, r5                         \n"
+            "    msr  PAC_KEY_P_0, r6                         \n"
+            "    clrm {r3-r6}                                 \n" /* Clear r3-r6. */
+        #endif /* configENABLE_PAC */
+            "    ldmia r2!, {r0, r3, lr}                      \n" /* Read from stack - r0 = xSecureContext, r3 = PSPLIM and LR restored. */
+            "    msr psplim, r3                               \n" /* Restore the PSPLIM register value for the task. */
+            "    ldr r3, =xSecureContext                      \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "    str r0, [r3]                                 \n" /* Restore the task's xSecureContext. */
+            "    cbz r0, restore_ns_context                   \n" /* If there is no secure context for the task, restore the non-secure context. */
+            "                                                 \n"
+            " restore_s_context:                              \n"
+            "    push {r1-r3, lr}                             \n"
+            "    bl SecureContext_LoadContext                 \n" /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+            "    pop {r1-r3, lr}                              \n"
+            "                                                 \n"
+            " restore_ns_context:                             \n"
+            "    mov r0, lr                                   \n" /* r0 = LR (EXC_RETURN). */
+            "    lsls r0, r0, #25                             \n" /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+            "    bmi restore_context_done                     \n" /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
+            "                                                 \n"
+            " restore_general_regs:                           \n"
+            "    ldmia r2!, {r4-r11}                          \n" /* Restore the registers that are not automatically restored. */
+        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            "   tst lr, #0x10                                 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+            "   it eq                                         \n"
+            "   vldmiaeq r2!, {s16-s31}                       \n" /* Restore the additional FP context registers which are not restored automatically. */
+        #endif /* configENABLE_FPU || configENABLE_MVE */
+            "                                                 \n"
+            " restore_context_done:                           \n"
+            "    msr psp, r2                                  \n" /* Remember the new top of stack for the task. */
+            "    bx lr                                        \n"
             ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
         );
     }
diff --git a/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h
index 8a8dc7d6a..e74fa8257 100644
--- a/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -125,6 +127,18 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
     extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
 #endif /* configENABLE_MPU */
+
+#if ( configENABLE_PAC == 1 )
+
+    /**
+     * @brief Generates 128-bit task's random PAC key.
+     *
+     * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be
+     *             filled with a 128-bit random number.
+     */
+    void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey );
+
+#endif /* configENABLE_PAC */
 /*-----------------------------------------------------------*/
 
 /**
@@ -188,9 +202,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Settings to define an MPU region.
- */
+    /**
+     * @brief Settings to define an MPU region.
+     */
     typedef struct MPURegionSettings
     {
         uint32_t ulRBAR; /**< RBAR for the region. */
@@ -203,9 +217,14 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-/**
- * @brief System call stack.
- */
+        /* When MPU wrapper v2 is used, the task's context is stored in TCB and
+         * pxTopOfStack member of TCB points to the context location in TCB. We,
+         * therefore, need to read PSP to find the task's current top of stack. */
+        #define portGET_CURRENT_TOP_OF_STACK( pxCurrentTopOfStack ) { __asm volatile ( "mrs %0, psp"  : "=r" ( pxCurrentTopOfStack ) ); }
+
+        /**
+         * @brief System call stack.
+         */
         typedef struct SYSTEM_CALL_STACK_INFO
         {
             uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ];
@@ -218,76 +237,128 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
-/**
- * @brief MPU settings as stored in the TCB.
- */
+    /**
+     * @brief MPU settings as stored in the TCB.
+     */
     #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+        #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +-----------+---------------+----------+-----------------+------------------------------+-----+
- * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
- * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
- * +-----------+---------------+----------+-----------------+------------------------------+-----+
- *
- * <-----------><--------------><---------><----------------><-----------------------------><---->
- *      16             16            8               8                     5                   1
- */
+            /*
+             * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey |     |
+             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |            |     |
+             * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
+             *      16             16            8               8                     5                     16         1
+             */
+            #define MAX_CONTEXT_SIZE    70
+
+        #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
+
+            /*
+             * +-----------+---------------+----------+-----------------+------------------------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+             * +-----------+---------------+----------+-----------------+------------------------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><-----------------------------><---->
+             *      16             16            8               8                     5                   1
+             */
             #define MAX_CONTEXT_SIZE    54
 
-        #else /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +-----------+---------------+----------+-----------------+----------------------+-----+
- * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
- * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
- * +-----------+---------------+----------+-----------------+----------------------+-----+
- *
- * <-----------><--------------><---------><----------------><---------------------><---->
- *      16             16            8               8                  4              1
- */
+            /*
+             * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey |     |
+             * |           |               |          | PC, xPSR        | EXC_RETURN           |            |     |
+             * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><---------------------><-----------><---->
+             *      16             16            8               8                  4                16         1
+             */
+            #define MAX_CONTEXT_SIZE    69
+
+        #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
+
+            /*
+             * +-----------+---------------+----------+-----------------+----------------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+             * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
+             * +-----------+---------------+----------+-----------------+----------------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><---------------------><---->
+             *      16             16            8               8                  4              1
+             */
             #define MAX_CONTEXT_SIZE    53
 
-        #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
     #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+        #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +----------+-----------------+------------------------------+-----+
- * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
- * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
- * +----------+-----------------+------------------------------+-----+
- *
- * <---------><----------------><------------------------------><---->
- *     8               8                      5                   1
- */
+            /*
+             * +----------+-----------------+------------------------------+------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey |     |
+             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |            |     |
+             * +----------+-----------------+------------------------------+------------+-----+
+             *
+             * <---------><----------------><------------------------------><-----------><---->
+             *     8               8                      5                      16         1
+             */
+            #define MAX_CONTEXT_SIZE    38
+
+        #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
+
+            /*
+             * +----------+-----------------+------------------------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+             * +----------+-----------------+------------------------------+-----+
+             *
+             * <---------><----------------><------------------------------><---->
+             *     8               8                      5                   1
+             */
             #define MAX_CONTEXT_SIZE    22
 
+        #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+            /*
+             * +----------+-----------------+----------------------+------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey |     |
+             * |          | PC, xPSR        | EXC_RETURN           |            |     |
+             * +----------+-----------------+----------------------+------------+-----+
+             *
+             * <---------><----------------><----------------------><-----------><---->
+             *     8               8                  4                  16         1
+             */
+            #define MAX_CONTEXT_SIZE    37
+
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-/*
- * +----------+-----------------+----------------------+-----+
- * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
- * |          | PC, xPSR        | EXC_RETURN           |     |
- * +----------+-----------------+----------------------+-----+
- *
- * <---------><----------------><----------------------><---->
- *     8               8                  4              1
- */
+            /*
+             * +----------+-----------------+----------------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+             * |          | PC, xPSR        | EXC_RETURN           |     |
+             * +----------+-----------------+----------------------+-----+
+             *
+             * <---------><----------------><----------------------><---->
+             *     8               8                  4              1
+             */
             #define MAX_CONTEXT_SIZE    21
 
-        #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
     #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
+    /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
-/* Size of an Access Control List (ACL) entry in bits. */
+    /* Size of an Access Control List (ACL) entry in bits. */
     #define portACL_ENTRY_SIZE_BITS             ( 32U )
 
     typedef struct MPU_SETTINGS
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/port.c b/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
index 80225b5cb..b2fd7e518 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
@@ -169,79 +169,80 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                            ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                            ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                             ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                            ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                            ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                           ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                           ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK        ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                      ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK                     ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                      ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK                     ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                      ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK                     ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                      ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK                     ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                      ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK                     ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                      ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK                     ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                      ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK                     ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                      ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK                     ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0                    ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1                    ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2                    ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3                    ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4                    ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5                    ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6                    ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7                    ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE                  ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
 
 #if ( portARMV8M_MINOR_VERSION >= 1 )
-    /* Enable Privileged eXecute Never MPU attribute for the selected memory
-     * region. */
-    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER   ( 1UL << 4UL )
+
+/* Enable Privileged eXecute Never MPU attribute for the selected memory
+ * region. */
+    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER    ( 1UL << 4UL )
 #endif /* portARMV8M_MINOR_VERSION >= 1 */
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT          ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                          ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE                 ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -380,14 +381,14 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to check and configure PACBTI security feature implementation.
  */
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
-    #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
+    #define portID_ISAR5_REG       ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
 
-    #define portCONTROL_UPAC_EN      ( 1UL << 7UL )
-    #define portCONTROL_PAC_EN       ( 1UL << 6UL )
-    #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
-    #define portCONTROL_BTI_EN       ( 1UL << 4UL )
+    #define portCONTROL_UPAC_EN    ( 1UL << 7UL )
+    #define portCONTROL_PAC_EN     ( 1UL << 6UL )
+    #define portCONTROL_UBTI_EN    ( 1UL << 5UL )
+    #define portCONTROL_BTI_EN     ( 1UL << 4UL )
 
 #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
@@ -409,7 +410,7 @@ static void prvTaskExitError( void );
  * @return uint32_t Access permissions.
  */
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0  */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 
 #if ( configENABLE_MPU == 1 )
 
@@ -427,7 +428,7 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
 /**
  * @brief Configures PACBTI features.
@@ -890,7 +891,7 @@ static void prvTaskExitError( void )
         return ulAccessPermissions;
     }
 
-#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0   */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
@@ -1212,6 +1213,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
+
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __syscalls_flash_start__;
@@ -1282,6 +1284,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
              * point (i.e. the caller of the MPU_<API>). We need to restore it
              * when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+
             /* Store the value of the PSPLIM register before the SVC was raised.
              * We need to restore it when we exit from the system call. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
@@ -1300,6 +1303,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
             /* Start executing the system call upon returning from this handler. */
             pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
+
             /* Raise a request to exit from the system call upon finishing the
              * system call. */
             pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit;
@@ -1359,6 +1363,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
+
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __privileged_functions_start__;
@@ -1541,7 +1546,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
-        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+        #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
         {
             /* Check PACBTI security feature configuration before pushing the
              * CONTROL register's value on task's TCB. */
@@ -1582,6 +1587,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
+        #if ( configENABLE_PAC == 1 )
+        {
+            uint32_t ulTaskPacKey[ 4 ], i;
+
+            vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+            for( i = 0; i < 4; i++ )
+            {
+                xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ];
+                ulIndex++;
+            }
+        }
+        #endif /* configENABLE_PAC */
+
         return &( xMPUSettings->ulContext[ ulIndex ] );
     }
 
@@ -1664,6 +1683,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #endif /* portPRELOAD_REGISTERS */
 
+        #if ( configENABLE_PAC == 1 )
+        {
+            uint32_t ulTaskPacKey[ 4 ], i;
+
+            vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+            for( i = 0; i < 4; i++ )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = ulTaskPacKey[ i ];
+            }
+        }
+        #endif /* configENABLE_PAC */
+
         return pxTopOfStack;
     }
 
@@ -1786,11 +1819,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
-    #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+    #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
     {
         /* Set the CONTROL register value based on PACBTI security feature
          * configuration before starting the first task. */
-        ( void) prvConfigurePACBTI( pdTRUE );
+        ( void ) prvConfigurePACBTI( pdTRUE );
     }
     #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
@@ -1990,9 +2023,9 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
         if( xSchedulerRunning == pdFALSE )
         {
             /* Grant access to all the kernel objects before the scheduler
-            * is started. It is necessary because there is no task running
-            * yet and therefore, we cannot use the permissions of any
-            * task. */
+             * is started. It is necessary because there is no task running
+             * yet and therefore, we cannot use the permissions of any
+             * task. */
             xAccessGranted = pdTRUE;
         }
         else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
@@ -2213,7 +2246,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
 
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
     {
@@ -2225,13 +2258,13 @@ BaseType_t xPortIsInsideInterrupt( void )
         /* Enable UsageFault exception. */
         portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
 
-        #if( configENABLE_PAC == 1 )
+        #if ( configENABLE_PAC == 1 )
         {
             ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
         }
         #endif
 
-        #if( configENABLE_BTI == 1 )
+        #if ( configENABLE_BTI == 1 )
         {
             ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
         }
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.c b/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.c
index 7cdff7005..bc7bb6071 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.c
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.c
@@ -77,16 +77,16 @@
             "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
             "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
             "                                                 \n"
-            #if ( configTOTAL_MPU_REGIONS == 16 )
-                "    movs r3, #8                                  \n" /* r3 = 8. */
-                "    str r3, [r1]                                 \n" /* Program RNR = 8. */
-                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-                "    movs r3, #12                                 \n" /* r3 = 12. */
-                "    str r3, [r1]                                 \n" /* Program RNR = 12. */
-                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-            #endif /* configTOTAL_MPU_REGIONS == 16 */
+        #if ( configTOTAL_MPU_REGIONS == 16 )
+            "    movs r3, #8                                  \n" /* r3 = 8. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 8. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "    movs r3, #12                                 \n" /* r3 = 12. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 12. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+        #endif /* configTOTAL_MPU_REGIONS == 16 */
             "                                                 \n"
             "   ldr r1, =0xe000ed94                           \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
@@ -100,6 +100,14 @@
             "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
             "                                                 \n"
             " restore_special_regs_first_task:                \n"
+        #if ( configENABLE_PAC == 1 )
+            "   ldmdb r1!, {r2-r5}                            \n" /* Read task's dedicated PAC key from the task's context. */
+            "   msr  PAC_KEY_P_0, r2                          \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+            "   msr  PAC_KEY_P_1, r3                          \n"
+            "   msr  PAC_KEY_P_2, r4                          \n"
+            "   msr  PAC_KEY_P_3, r5                          \n"
+            "   clrm {r2-r5}                                  \n" /* Clear r2-r5. */
+        #endif /* configENABLE_PAC */
             "    ldmdb r1!, {r2-r4, lr}                       \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
             "    msr psp, r2                                  \n"
             "    msr psplim, r3                               \n"
@@ -130,6 +138,15 @@
             "   ldr  r1, [r2]                                   \n" /* Read pxCurrentTCB. */
             "   ldr  r0, [r1]                                   \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
             "                                                   \n"
+        #if ( configENABLE_PAC == 1 )
+            "   ldmia r0!, {r1-r4}                              \n" /* Read task's dedicated PAC key from stack. */
+            "   msr  PAC_KEY_P_3, r1                            \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+            "   msr  PAC_KEY_P_2, r2                            \n"
+            "   msr  PAC_KEY_P_1, r3                            \n"
+            "   msr  PAC_KEY_P_0, r4                            \n"
+            "   clrm {r1-r4}                                    \n" /* Clear r1-r4. */
+        #endif /* configENABLE_PAC */
+            "                                                   \n"
             "   ldm  r0!, {r1-r2}                               \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
             "   msr  psplim, r1                                 \n" /* Set this task's PSPLIM value. */
             "   mrs  r1, control                                \n" /* Obtain current control register value. */
@@ -261,16 +278,15 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             " mrs r2, psp                                     \n" /* r2 = PSP. */
             "                                                 \n"
             " save_general_regs:                              \n"
-            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-                "    add r2, r2, #0x20                            \n" /* Move r2 to location where s0 is saved. */
-                "    tst lr, #0x10                                \n"
-                "    ittt eq                                      \n"
-                "    vstmiaeq r1!, {s16-s31}                      \n" /* Store s16-s31. */
-                "    vldmiaeq r2, {s0-s16}                        \n" /* Copy hardware saved FP context into s0-s16. */
-                "    vstmiaeq r1!, {s0-s16}                       \n" /* Store hardware saved FP context. */
-                "    sub r2, r2, #0x20                            \n" /* Set r2 back to the location of hardware saved context. */
-            #endif /* configENABLE_FPU || configENABLE_MVE */
-            "                                                 \n"
+        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            "    add r2, r2, #0x20                            \n" /* Move r2 to location where s0 is saved. */
+            "    tst lr, #0x10                                \n"
+            "    ittt eq                                      \n"
+            "    vstmiaeq r1!, {s16-s31}                      \n" /* Store s16-s31. */
+            "    vldmiaeq r2, {s0-s16}                        \n" /* Copy hardware saved FP context into s0-s16. */
+            "    vstmiaeq r1!, {s0-s16}                       \n" /* Store hardware saved FP context. */
+            "    sub r2, r2, #0x20                            \n" /* Set r2 back to the location of hardware saved context. */
+        #endif /* configENABLE_FPU || configENABLE_MVE */
             "    stmia r1!, {r4-r11}                          \n" /* Store r4-r11. */
             "    ldmia r2, {r4-r11}                           \n" /* Copy the hardware saved context into r4-r11. */
             "    stmia r1!, {r4-r11}                          \n" /* Store the hardware saved context. */
@@ -279,6 +295,14 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    mrs r3, psplim                               \n" /* r3 = PSPLIM. */
             "    mrs r4, control                              \n" /* r4 = CONTROL. */
             "    stmia r1!, {r2-r4, lr}                       \n" /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
+        #if ( configENABLE_PAC == 1 )
+            "   mrs  r2, PAC_KEY_P_0                          \n" /* Read task's dedicated PAC key from the PAC key registers. */
+            "   mrs  r3, PAC_KEY_P_1                          \n"
+            "   mrs  r4, PAC_KEY_P_2                          \n"
+            "   mrs  r5, PAC_KEY_P_3                          \n"
+            "   stmia r1!, {r2-r5}                            \n" /* Store the task's dedicated PAC key on the task's context. */
+            "   clrm {r2-r5}                                  \n" /* Clear r2-r5. */
+        #endif /* configENABLE_PAC */
             "    str r1, [r0]                                 \n" /* Save the location from where the context should be restored as the first member of TCB. */
             "                                                 \n"
             " select_next_task:                               \n"
@@ -314,16 +338,16 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
             "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
             "                                                 \n"
-            #if ( configTOTAL_MPU_REGIONS == 16 )
-                "    movs r3, #8                                  \n" /* r3 = 8. */
-                "    str r3, [r1]                                 \n" /* Program RNR = 8. */
-                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-                "    movs r3, #12                                 \n" /* r3 = 12. */
-                "    str r3, [r1]                                 \n" /* Program RNR = 12. */
-                "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-                "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-            #endif /* configTOTAL_MPU_REGIONS == 16 */
+        #if ( configTOTAL_MPU_REGIONS == 16 )
+            "    movs r3, #8                                  \n" /* r3 = 8. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 8. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "    movs r3, #12                                 \n" /* r3 = 12. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 12. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+        #endif /* configTOTAL_MPU_REGIONS == 16 */
             "                                                 \n"
             "   ldr r1, =0xe000ed94                           \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
             "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
@@ -337,6 +361,14 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
             "                                                 \n"
             " restore_special_regs:                           \n"
+        #if ( configENABLE_PAC == 1 )
+            "   ldmdb r1!, {r2-r5}                            \n" /* Read task's dedicated PAC key from the task's context. */
+            "   msr  PAC_KEY_P_0, r2                          \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+            "   msr  PAC_KEY_P_1, r3                          \n"
+            "   msr  PAC_KEY_P_2, r4                          \n"
+            "   msr  PAC_KEY_P_3, r5                          \n"
+            "   clrm {r2-r5}                                  \n" /* Clear r2-r5. */
+        #endif /* configENABLE_PAC */
             "    ldmdb r1!, {r2-r4, lr}                       \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
             "    msr psp, r2                                  \n"
             "    msr psplim, r3                               \n"
@@ -346,13 +378,13 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
             "    stmia r2!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
             "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 restored. */
-            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-                "    tst lr, #0x10                                \n"
-                "    ittt eq                                      \n"
-                "    vldmdbeq r1!, {s0-s16}                       \n" /* s0-s16 contain hardware saved FP context. */
-                "    vstmiaeq r2!, {s0-s16}                       \n" /* Copy hardware saved FP context on the task stack. */
-                "    vldmdbeq r1!, {s16-s31}                      \n" /* Restore s16-s31. */
-            #endif /* configENABLE_FPU || configENABLE_MVE */
+        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            "    tst lr, #0x10                                \n"
+            "    ittt eq                                      \n"
+            "    vldmdbeq r1!, {s0-s16}                       \n" /* s0-s16 contain hardware saved FP context. */
+            "    vstmiaeq r2!, {s0-s16}                       \n" /* Copy hardware saved FP context on the task stack. */
+            "    vldmdbeq r1!, {s16-s31}                      \n" /* Restore s16-s31. */
+        #endif /* configENABLE_FPU || configENABLE_MVE */
             "                                                 \n"
             " restore_context_done:                           \n"
             "    str r1, [r0]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
@@ -371,16 +403,25 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "                                                   \n"
             "   mrs r0, psp                                     \n" /* Read PSP in r0. */
             "                                                   \n"
-            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-                "   tst lr, #0x10                                   \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
-                "   it eq                                           \n"
-                "   vstmdbeq r0!, {s16-s31}                         \n" /* Store the additional FP context registers which are not saved automatically. */
-            #endif /* configENABLE_FPU || configENABLE_MVE */
+        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            "   tst lr, #0x10                                   \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+            "   it eq                                           \n"
+            "   vstmdbeq r0!, {s16-s31}                         \n" /* Store the additional FP context registers which are not saved automatically. */
+        #endif /* configENABLE_FPU || configENABLE_MVE */
             "                                                   \n"
             "   mrs r2, psplim                                  \n" /* r2 = PSPLIM. */
             "   mov r3, lr                                      \n" /* r3 = LR/EXC_RETURN. */
             "   stmdb r0!, {r2-r11}                             \n" /* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */
             "                                                   \n"
+        #if ( configENABLE_PAC == 1 )
+            "   mrs  r1, PAC_KEY_P_3                            \n" /* Read task's dedicated PAC key from the PAC key registers. */
+            "   mrs  r2, PAC_KEY_P_2                            \n"
+            "   mrs  r3, PAC_KEY_P_1                            \n"
+            "   mrs  r4, PAC_KEY_P_0                            \n"
+            "   stmdb r0!, {r1-r4}                              \n" /* Store the task's dedicated PAC key on the stack. */
+            "   clrm {r1-r4}                                    \n" /* Clear r1-r4. */
+        #endif /* configENABLE_PAC */
+            "                                                   \n"
             "   ldr r2, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
             "   ldr r1, [r2]                                    \n" /* Read pxCurrentTCB. */
             "   str r0, [r1]                                    \n" /* Save the new top of stack in TCB. */
@@ -397,13 +438,22 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
             "   ldr r1, [r2]                                    \n" /* Read pxCurrentTCB. */
             "   ldr r0, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
             "                                                   \n"
+        #if ( configENABLE_PAC == 1 )
+            "   ldmia r0!, {r2-r5}                              \n" /* Read task's dedicated PAC key from stack. */
+            "   msr  PAC_KEY_P_3, r2                            \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+            "   msr  PAC_KEY_P_2, r3                            \n"
+            "   msr  PAC_KEY_P_1, r4                            \n"
+            "   msr  PAC_KEY_P_0, r5                            \n"
+            "   clrm {r2-r5}                                    \n" /* Clear r2-r5. */
+        #endif /* configENABLE_PAC */
+            "                                                   \n"
             "   ldmia r0!, {r2-r11}                             \n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
             "                                                   \n"
-            #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-                "   tst r3, #0x10                                   \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
-                "   it eq                                           \n"
-                "   vldmiaeq r0!, {s16-s31}                         \n" /* Restore the additional FP context registers which are not restored automatically. */
-            #endif /* configENABLE_FPU || configENABLE_MVE */
+        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            "   tst r3, #0x10                                   \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+            "   it eq                                           \n"
+            "   vldmiaeq r0!, {s16-s31}                         \n" /* Restore the additional FP context registers which are not restored automatically. */
+        #endif /* configENABLE_FPU || configENABLE_MVE */
             "                                                   \n"
             "   msr psplim, r2                                  \n" /* Restore the PSPLIM register value for the task. */
             "   msr psp, r0                                     \n" /* Remember the new top of stack for the task. */
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h
index 8a8dc7d6a..e74fa8257 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -125,6 +127,18 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
     extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
 #endif /* configENABLE_MPU */
+
+#if ( configENABLE_PAC == 1 )
+
+    /**
+     * @brief Generates 128-bit task's random PAC key.
+     *
+     * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be
+     *             filled with a 128-bit random number.
+     */
+    void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey );
+
+#endif /* configENABLE_PAC */
 /*-----------------------------------------------------------*/
 
 /**
@@ -188,9 +202,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Settings to define an MPU region.
- */
+    /**
+     * @brief Settings to define an MPU region.
+     */
     typedef struct MPURegionSettings
     {
         uint32_t ulRBAR; /**< RBAR for the region. */
@@ -203,9 +217,14 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-/**
- * @brief System call stack.
- */
+        /* When MPU wrapper v2 is used, the task's context is stored in TCB and
+         * pxTopOfStack member of TCB points to the context location in TCB. We,
+         * therefore, need to read PSP to find the task's current top of stack. */
+        #define portGET_CURRENT_TOP_OF_STACK( pxCurrentTopOfStack ) { __asm volatile ( "mrs %0, psp"  : "=r" ( pxCurrentTopOfStack ) ); }
+
+        /**
+         * @brief System call stack.
+         */
         typedef struct SYSTEM_CALL_STACK_INFO
         {
             uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ];
@@ -218,76 +237,128 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
-/**
- * @brief MPU settings as stored in the TCB.
- */
+    /**
+     * @brief MPU settings as stored in the TCB.
+     */
     #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+        #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +-----------+---------------+----------+-----------------+------------------------------+-----+
- * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
- * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
- * +-----------+---------------+----------+-----------------+------------------------------+-----+
- *
- * <-----------><--------------><---------><----------------><-----------------------------><---->
- *      16             16            8               8                     5                   1
- */
+            /*
+             * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey |     |
+             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |            |     |
+             * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
+             *      16             16            8               8                     5                     16         1
+             */
+            #define MAX_CONTEXT_SIZE    70
+
+        #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
+
+            /*
+             * +-----------+---------------+----------+-----------------+------------------------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+             * +-----------+---------------+----------+-----------------+------------------------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><-----------------------------><---->
+             *      16             16            8               8                     5                   1
+             */
             #define MAX_CONTEXT_SIZE    54
 
-        #else /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +-----------+---------------+----------+-----------------+----------------------+-----+
- * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
- * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
- * +-----------+---------------+----------+-----------------+----------------------+-----+
- *
- * <-----------><--------------><---------><----------------><---------------------><---->
- *      16             16            8               8                  4              1
- */
+            /*
+             * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey |     |
+             * |           |               |          | PC, xPSR        | EXC_RETURN           |            |     |
+             * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><---------------------><-----------><---->
+             *      16             16            8               8                  4                16         1
+             */
+            #define MAX_CONTEXT_SIZE    69
+
+        #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
+
+            /*
+             * +-----------+---------------+----------+-----------------+----------------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+             * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
+             * +-----------+---------------+----------+-----------------+----------------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><---------------------><---->
+             *      16             16            8               8                  4              1
+             */
             #define MAX_CONTEXT_SIZE    53
 
-        #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
     #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+        #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +----------+-----------------+------------------------------+-----+
- * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
- * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
- * +----------+-----------------+------------------------------+-----+
- *
- * <---------><----------------><------------------------------><---->
- *     8               8                      5                   1
- */
+            /*
+             * +----------+-----------------+------------------------------+------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey |     |
+             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |            |     |
+             * +----------+-----------------+------------------------------+------------+-----+
+             *
+             * <---------><----------------><------------------------------><-----------><---->
+             *     8               8                      5                      16         1
+             */
+            #define MAX_CONTEXT_SIZE    38
+
+        #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
+
+            /*
+             * +----------+-----------------+------------------------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+             * +----------+-----------------+------------------------------+-----+
+             *
+             * <---------><----------------><------------------------------><---->
+             *     8               8                      5                   1
+             */
             #define MAX_CONTEXT_SIZE    22
 
+        #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+            /*
+             * +----------+-----------------+----------------------+------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey |     |
+             * |          | PC, xPSR        | EXC_RETURN           |            |     |
+             * +----------+-----------------+----------------------+------------+-----+
+             *
+             * <---------><----------------><----------------------><-----------><---->
+             *     8               8                  4                  16         1
+             */
+            #define MAX_CONTEXT_SIZE    37
+
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-/*
- * +----------+-----------------+----------------------+-----+
- * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
- * |          | PC, xPSR        | EXC_RETURN           |     |
- * +----------+-----------------+----------------------+-----+
- *
- * <---------><----------------><----------------------><---->
- *     8               8                  4              1
- */
+            /*
+             * +----------+-----------------+----------------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+             * |          | PC, xPSR        | EXC_RETURN           |     |
+             * +----------+-----------------+----------------------+-----+
+             *
+             * <---------><----------------><----------------------><---->
+             *     8               8                  4              1
+             */
             #define MAX_CONTEXT_SIZE    21
 
-        #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
     #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
+    /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
-/* Size of an Access Control List (ACL) entry in bits. */
+    /* Size of an Access Control List (ACL) entry in bits. */
     #define portACL_ENTRY_SIZE_BITS             ( 32U )
 
     typedef struct MPU_SETTINGS
diff --git a/portable/IAR/ARM_CM23/non_secure/port.c b/portable/IAR/ARM_CM23/non_secure/port.c
index 5c963ea29..b2fd7e518 100644
--- a/portable/IAR/ARM_CM23/non_secure/port.c
+++ b/portable/IAR/ARM_CM23/non_secure/port.c
@@ -169,79 +169,80 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                            ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                            ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                             ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                            ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                            ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                           ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                           ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK        ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                      ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK                     ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                      ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK                     ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                      ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK                     ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                      ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK                     ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                      ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK                     ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                      ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK                     ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                      ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK                     ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                      ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK                     ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0                    ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1                    ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2                    ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3                    ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4                    ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5                    ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6                    ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7                    ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE                  ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
 
 #if ( portARMV8M_MINOR_VERSION >= 1 )
-    /* Enable Privileged eXecute Never MPU attribute for the selected memory
-     * region. */
-    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER   ( 1UL << 4UL )
+
+/* Enable Privileged eXecute Never MPU attribute for the selected memory
+ * region. */
+    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER    ( 1UL << 4UL )
 #endif /* portARMV8M_MINOR_VERSION >= 1 */
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT          ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                          ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE                 ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -380,14 +381,14 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to check and configure PACBTI security feature implementation.
  */
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
-    #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
+    #define portID_ISAR5_REG       ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
 
-    #define portCONTROL_UPAC_EN      ( 1UL << 7UL )
-    #define portCONTROL_PAC_EN       ( 1UL << 6UL )
-    #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
-    #define portCONTROL_BTI_EN       ( 1UL << 4UL )
+    #define portCONTROL_UPAC_EN    ( 1UL << 7UL )
+    #define portCONTROL_PAC_EN     ( 1UL << 6UL )
+    #define portCONTROL_UBTI_EN    ( 1UL << 5UL )
+    #define portCONTROL_BTI_EN     ( 1UL << 4UL )
 
 #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
@@ -409,7 +410,7 @@ static void prvTaskExitError( void );
  * @return uint32_t Access permissions.
  */
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0   */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 
 #if ( configENABLE_MPU == 1 )
 
@@ -427,7 +428,7 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
 /**
  * @brief Configures PACBTI features.
@@ -890,7 +891,7 @@ static void prvTaskExitError( void )
         return ulAccessPermissions;
     }
 
-#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0   */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
@@ -1212,6 +1213,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
+
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __syscalls_flash_start__;
@@ -1282,6 +1284,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
              * point (i.e. the caller of the MPU_<API>). We need to restore it
              * when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+
             /* Store the value of the PSPLIM register before the SVC was raised.
              * We need to restore it when we exit from the system call. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
@@ -1300,6 +1303,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
             /* Start executing the system call upon returning from this handler. */
             pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
+
             /* Raise a request to exit from the system call upon finishing the
              * system call. */
             pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit;
@@ -1359,6 +1363,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
+
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __privileged_functions_start__;
@@ -1541,7 +1546,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
-        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+        #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
         {
             /* Check PACBTI security feature configuration before pushing the
              * CONTROL register's value on task's TCB. */
@@ -1582,6 +1587,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
+        #if ( configENABLE_PAC == 1 )
+        {
+            uint32_t ulTaskPacKey[ 4 ], i;
+
+            vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+            for( i = 0; i < 4; i++ )
+            {
+                xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ];
+                ulIndex++;
+            }
+        }
+        #endif /* configENABLE_PAC */
+
         return &( xMPUSettings->ulContext[ ulIndex ] );
     }
 
@@ -1664,6 +1683,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #endif /* portPRELOAD_REGISTERS */
 
+        #if ( configENABLE_PAC == 1 )
+        {
+            uint32_t ulTaskPacKey[ 4 ], i;
+
+            vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+            for( i = 0; i < 4; i++ )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = ulTaskPacKey[ i ];
+            }
+        }
+        #endif /* configENABLE_PAC */
+
         return pxTopOfStack;
     }
 
@@ -1786,11 +1819,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
-    #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+    #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
     {
         /* Set the CONTROL register value based on PACBTI security feature
          * configuration before starting the first task. */
-        ( void) prvConfigurePACBTI( pdTRUE );
+        ( void ) prvConfigurePACBTI( pdTRUE );
     }
     #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
@@ -1990,9 +2023,9 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
         if( xSchedulerRunning == pdFALSE )
         {
             /* Grant access to all the kernel objects before the scheduler
-            * is started. It is necessary because there is no task running
-            * yet and therefore, we cannot use the permissions of any
-            * task. */
+             * is started. It is necessary because there is no task running
+             * yet and therefore, we cannot use the permissions of any
+             * task. */
             xAccessGranted = pdTRUE;
         }
         else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
@@ -2213,7 +2246,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
 
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
     {
@@ -2225,13 +2258,13 @@ BaseType_t xPortIsInsideInterrupt( void )
         /* Enable UsageFault exception. */
         portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
 
-        #if( configENABLE_PAC == 1 )
+        #if ( configENABLE_PAC == 1 )
         {
             ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
         }
         #endif
 
-        #if( configENABLE_BTI == 1 )
+        #if ( configENABLE_BTI == 1 )
         {
             ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
         }
diff --git a/portable/IAR/ARM_CM23/non_secure/portmacro.h b/portable/IAR/ARM_CM23/non_secure/portmacro.h
index 9dfcc9132..9d6c3368e 100644
--- a/portable/IAR/ARM_CM23/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM23/non_secure/portmacro.h
@@ -64,7 +64,7 @@
 
 #ifndef configENABLE_MVE
     #define configENABLE_MVE    0
-#elif( configENABLE_MVE != 0 )
+#elif ( configENABLE_MVE != 0 )
     #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M23.
 #endif
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h
index 8a8dc7d6a..e74fa8257 100644
--- a/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -125,6 +127,18 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
     extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
 #endif /* configENABLE_MPU */
+
+#if ( configENABLE_PAC == 1 )
+
+    /**
+     * @brief Generates 128-bit task's random PAC key.
+     *
+     * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be
+     *             filled with a 128-bit random number.
+     */
+    void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey );
+
+#endif /* configENABLE_PAC */
 /*-----------------------------------------------------------*/
 
 /**
@@ -188,9 +202,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Settings to define an MPU region.
- */
+    /**
+     * @brief Settings to define an MPU region.
+     */
     typedef struct MPURegionSettings
     {
         uint32_t ulRBAR; /**< RBAR for the region. */
@@ -203,9 +217,14 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-/**
- * @brief System call stack.
- */
+        /* When MPU wrapper v2 is used, the task's context is stored in TCB and
+         * pxTopOfStack member of TCB points to the context location in TCB. We,
+         * therefore, need to read PSP to find the task's current top of stack. */
+        #define portGET_CURRENT_TOP_OF_STACK( pxCurrentTopOfStack ) { __asm volatile ( "mrs %0, psp"  : "=r" ( pxCurrentTopOfStack ) ); }
+
+        /**
+         * @brief System call stack.
+         */
         typedef struct SYSTEM_CALL_STACK_INFO
         {
             uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ];
@@ -218,76 +237,128 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
-/**
- * @brief MPU settings as stored in the TCB.
- */
+    /**
+     * @brief MPU settings as stored in the TCB.
+     */
     #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+        #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +-----------+---------------+----------+-----------------+------------------------------+-----+
- * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
- * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
- * +-----------+---------------+----------+-----------------+------------------------------+-----+
- *
- * <-----------><--------------><---------><----------------><-----------------------------><---->
- *      16             16            8               8                     5                   1
- */
+            /*
+             * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey |     |
+             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |            |     |
+             * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
+             *      16             16            8               8                     5                     16         1
+             */
+            #define MAX_CONTEXT_SIZE    70
+
+        #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
+
+            /*
+             * +-----------+---------------+----------+-----------------+------------------------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+             * +-----------+---------------+----------+-----------------+------------------------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><-----------------------------><---->
+             *      16             16            8               8                     5                   1
+             */
             #define MAX_CONTEXT_SIZE    54
 
-        #else /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +-----------+---------------+----------+-----------------+----------------------+-----+
- * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
- * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
- * +-----------+---------------+----------+-----------------+----------------------+-----+
- *
- * <-----------><--------------><---------><----------------><---------------------><---->
- *      16             16            8               8                  4              1
- */
+            /*
+             * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey |     |
+             * |           |               |          | PC, xPSR        | EXC_RETURN           |            |     |
+             * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><---------------------><-----------><---->
+             *      16             16            8               8                  4                16         1
+             */
+            #define MAX_CONTEXT_SIZE    69
+
+        #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
+
+            /*
+             * +-----------+---------------+----------+-----------------+----------------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+             * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
+             * +-----------+---------------+----------+-----------------+----------------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><---------------------><---->
+             *      16             16            8               8                  4              1
+             */
             #define MAX_CONTEXT_SIZE    53
 
-        #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
     #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+        #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +----------+-----------------+------------------------------+-----+
- * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
- * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
- * +----------+-----------------+------------------------------+-----+
- *
- * <---------><----------------><------------------------------><---->
- *     8               8                      5                   1
- */
+            /*
+             * +----------+-----------------+------------------------------+------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey |     |
+             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |            |     |
+             * +----------+-----------------+------------------------------+------------+-----+
+             *
+             * <---------><----------------><------------------------------><-----------><---->
+             *     8               8                      5                      16         1
+             */
+            #define MAX_CONTEXT_SIZE    38
+
+        #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
+
+            /*
+             * +----------+-----------------+------------------------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+             * +----------+-----------------+------------------------------+-----+
+             *
+             * <---------><----------------><------------------------------><---->
+             *     8               8                      5                   1
+             */
             #define MAX_CONTEXT_SIZE    22
 
+        #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+            /*
+             * +----------+-----------------+----------------------+------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey |     |
+             * |          | PC, xPSR        | EXC_RETURN           |            |     |
+             * +----------+-----------------+----------------------+------------+-----+
+             *
+             * <---------><----------------><----------------------><-----------><---->
+             *     8               8                  4                  16         1
+             */
+            #define MAX_CONTEXT_SIZE    37
+
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-/*
- * +----------+-----------------+----------------------+-----+
- * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
- * |          | PC, xPSR        | EXC_RETURN           |     |
- * +----------+-----------------+----------------------+-----+
- *
- * <---------><----------------><----------------------><---->
- *     8               8                  4              1
- */
+            /*
+             * +----------+-----------------+----------------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+             * |          | PC, xPSR        | EXC_RETURN           |     |
+             * +----------+-----------------+----------------------+-----+
+             *
+             * <---------><----------------><----------------------><---->
+             *     8               8                  4              1
+             */
             #define MAX_CONTEXT_SIZE    21
 
-        #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
     #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
+    /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
-/* Size of an Access Control List (ACL) entry in bits. */
+    /* Size of an Access Control List (ACL) entry in bits. */
     #define portACL_ENTRY_SIZE_BITS             ( 32U )
 
     typedef struct MPU_SETTINGS
diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
index 5c963ea29..b2fd7e518 100644
--- a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
@@ -169,79 +169,80 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                            ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                            ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                             ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                            ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                            ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                           ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                           ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK        ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                      ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK                     ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                      ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK                     ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                      ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK                     ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                      ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK                     ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                      ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK                     ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                      ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK                     ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                      ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK                     ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                      ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK                     ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0                    ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1                    ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2                    ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3                    ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4                    ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5                    ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6                    ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7                    ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE                  ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
 
 #if ( portARMV8M_MINOR_VERSION >= 1 )
-    /* Enable Privileged eXecute Never MPU attribute for the selected memory
-     * region. */
-    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER   ( 1UL << 4UL )
+
+/* Enable Privileged eXecute Never MPU attribute for the selected memory
+ * region. */
+    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER    ( 1UL << 4UL )
 #endif /* portARMV8M_MINOR_VERSION >= 1 */
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT          ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                          ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE                 ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -380,14 +381,14 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to check and configure PACBTI security feature implementation.
  */
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
-    #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
+    #define portID_ISAR5_REG       ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
 
-    #define portCONTROL_UPAC_EN      ( 1UL << 7UL )
-    #define portCONTROL_PAC_EN       ( 1UL << 6UL )
-    #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
-    #define portCONTROL_BTI_EN       ( 1UL << 4UL )
+    #define portCONTROL_UPAC_EN    ( 1UL << 7UL )
+    #define portCONTROL_PAC_EN     ( 1UL << 6UL )
+    #define portCONTROL_UBTI_EN    ( 1UL << 5UL )
+    #define portCONTROL_BTI_EN     ( 1UL << 4UL )
 
 #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
@@ -409,7 +410,7 @@ static void prvTaskExitError( void );
  * @return uint32_t Access permissions.
  */
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0   */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 
 #if ( configENABLE_MPU == 1 )
 
@@ -427,7 +428,7 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
 /**
  * @brief Configures PACBTI features.
@@ -890,7 +891,7 @@ static void prvTaskExitError( void )
         return ulAccessPermissions;
     }
 
-#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0   */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
@@ -1212,6 +1213,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
+
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __syscalls_flash_start__;
@@ -1282,6 +1284,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
              * point (i.e. the caller of the MPU_<API>). We need to restore it
              * when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+
             /* Store the value of the PSPLIM register before the SVC was raised.
              * We need to restore it when we exit from the system call. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
@@ -1300,6 +1303,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
             /* Start executing the system call upon returning from this handler. */
             pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
+
             /* Raise a request to exit from the system call upon finishing the
              * system call. */
             pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit;
@@ -1359,6 +1363,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
+
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __privileged_functions_start__;
@@ -1541,7 +1546,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
-        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+        #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
         {
             /* Check PACBTI security feature configuration before pushing the
              * CONTROL register's value on task's TCB. */
@@ -1582,6 +1587,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
+        #if ( configENABLE_PAC == 1 )
+        {
+            uint32_t ulTaskPacKey[ 4 ], i;
+
+            vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+            for( i = 0; i < 4; i++ )
+            {
+                xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ];
+                ulIndex++;
+            }
+        }
+        #endif /* configENABLE_PAC */
+
         return &( xMPUSettings->ulContext[ ulIndex ] );
     }
 
@@ -1664,6 +1683,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #endif /* portPRELOAD_REGISTERS */
 
+        #if ( configENABLE_PAC == 1 )
+        {
+            uint32_t ulTaskPacKey[ 4 ], i;
+
+            vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+            for( i = 0; i < 4; i++ )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = ulTaskPacKey[ i ];
+            }
+        }
+        #endif /* configENABLE_PAC */
+
         return pxTopOfStack;
     }
 
@@ -1786,11 +1819,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
-    #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+    #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
     {
         /* Set the CONTROL register value based on PACBTI security feature
          * configuration before starting the first task. */
-        ( void) prvConfigurePACBTI( pdTRUE );
+        ( void ) prvConfigurePACBTI( pdTRUE );
     }
     #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
@@ -1990,9 +2023,9 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
         if( xSchedulerRunning == pdFALSE )
         {
             /* Grant access to all the kernel objects before the scheduler
-            * is started. It is necessary because there is no task running
-            * yet and therefore, we cannot use the permissions of any
-            * task. */
+             * is started. It is necessary because there is no task running
+             * yet and therefore, we cannot use the permissions of any
+             * task. */
             xAccessGranted = pdTRUE;
         }
         else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
@@ -2213,7 +2246,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
 
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
     {
@@ -2225,13 +2258,13 @@ BaseType_t xPortIsInsideInterrupt( void )
         /* Enable UsageFault exception. */
         portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
 
-        #if( configENABLE_PAC == 1 )
+        #if ( configENABLE_PAC == 1 )
         {
             ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
         }
         #endif
 
-        #if( configENABLE_BTI == 1 )
+        #if ( configENABLE_BTI == 1 )
         {
             ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
         }
diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h b/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h
index 9dfcc9132..9d6c3368e 100644
--- a/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h
@@ -64,7 +64,7 @@
 
 #ifndef configENABLE_MVE
     #define configENABLE_MVE    0
-#elif( configENABLE_MVE != 0 )
+#elif ( configENABLE_MVE != 0 )
     #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M23.
 #endif
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h
index 8a8dc7d6a..e74fa8257 100644
--- a/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -125,6 +127,18 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
     extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
 #endif /* configENABLE_MPU */
+
+#if ( configENABLE_PAC == 1 )
+
+    /**
+     * @brief Generates 128-bit task's random PAC key.
+     *
+     * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be
+     *             filled with a 128-bit random number.
+     */
+    void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey );
+
+#endif /* configENABLE_PAC */
 /*-----------------------------------------------------------*/
 
 /**
@@ -188,9 +202,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Settings to define an MPU region.
- */
+    /**
+     * @brief Settings to define an MPU region.
+     */
     typedef struct MPURegionSettings
     {
         uint32_t ulRBAR; /**< RBAR for the region. */
@@ -203,9 +217,14 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-/**
- * @brief System call stack.
- */
+        /* When MPU wrapper v2 is used, the task's context is stored in TCB and
+         * pxTopOfStack member of TCB points to the context location in TCB. We,
+         * therefore, need to read PSP to find the task's current top of stack. */
+        #define portGET_CURRENT_TOP_OF_STACK( pxCurrentTopOfStack ) { __asm volatile ( "mrs %0, psp"  : "=r" ( pxCurrentTopOfStack ) ); }
+
+        /**
+         * @brief System call stack.
+         */
         typedef struct SYSTEM_CALL_STACK_INFO
         {
             uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ];
@@ -218,76 +237,128 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
-/**
- * @brief MPU settings as stored in the TCB.
- */
+    /**
+     * @brief MPU settings as stored in the TCB.
+     */
     #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+        #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +-----------+---------------+----------+-----------------+------------------------------+-----+
- * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
- * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
- * +-----------+---------------+----------+-----------------+------------------------------+-----+
- *
- * <-----------><--------------><---------><----------------><-----------------------------><---->
- *      16             16            8               8                     5                   1
- */
+            /*
+             * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey |     |
+             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |            |     |
+             * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
+             *      16             16            8               8                     5                     16         1
+             */
+            #define MAX_CONTEXT_SIZE    70
+
+        #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
+
+            /*
+             * +-----------+---------------+----------+-----------------+------------------------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+             * +-----------+---------------+----------+-----------------+------------------------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><-----------------------------><---->
+             *      16             16            8               8                     5                   1
+             */
             #define MAX_CONTEXT_SIZE    54
 
-        #else /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +-----------+---------------+----------+-----------------+----------------------+-----+
- * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
- * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
- * +-----------+---------------+----------+-----------------+----------------------+-----+
- *
- * <-----------><--------------><---------><----------------><---------------------><---->
- *      16             16            8               8                  4              1
- */
+            /*
+             * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey |     |
+             * |           |               |          | PC, xPSR        | EXC_RETURN           |            |     |
+             * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><---------------------><-----------><---->
+             *      16             16            8               8                  4                16         1
+             */
+            #define MAX_CONTEXT_SIZE    69
+
+        #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
+
+            /*
+             * +-----------+---------------+----------+-----------------+----------------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+             * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
+             * +-----------+---------------+----------+-----------------+----------------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><---------------------><---->
+             *      16             16            8               8                  4              1
+             */
             #define MAX_CONTEXT_SIZE    53
 
-        #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
     #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+        #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +----------+-----------------+------------------------------+-----+
- * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
- * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
- * +----------+-----------------+------------------------------+-----+
- *
- * <---------><----------------><------------------------------><---->
- *     8               8                      5                   1
- */
+            /*
+             * +----------+-----------------+------------------------------+------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey |     |
+             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |            |     |
+             * +----------+-----------------+------------------------------+------------+-----+
+             *
+             * <---------><----------------><------------------------------><-----------><---->
+             *     8               8                      5                      16         1
+             */
+            #define MAX_CONTEXT_SIZE    38
+
+        #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
+
+            /*
+             * +----------+-----------------+------------------------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+             * +----------+-----------------+------------------------------+-----+
+             *
+             * <---------><----------------><------------------------------><---->
+             *     8               8                      5                   1
+             */
             #define MAX_CONTEXT_SIZE    22
 
+        #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+            /*
+             * +----------+-----------------+----------------------+------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey |     |
+             * |          | PC, xPSR        | EXC_RETURN           |            |     |
+             * +----------+-----------------+----------------------+------------+-----+
+             *
+             * <---------><----------------><----------------------><-----------><---->
+             *     8               8                  4                  16         1
+             */
+            #define MAX_CONTEXT_SIZE    37
+
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-/*
- * +----------+-----------------+----------------------+-----+
- * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
- * |          | PC, xPSR        | EXC_RETURN           |     |
- * +----------+-----------------+----------------------+-----+
- *
- * <---------><----------------><----------------------><---->
- *     8               8                  4              1
- */
+            /*
+             * +----------+-----------------+----------------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+             * |          | PC, xPSR        | EXC_RETURN           |     |
+             * +----------+-----------------+----------------------+-----+
+             *
+             * <---------><----------------><----------------------><---->
+             *     8               8                  4              1
+             */
             #define MAX_CONTEXT_SIZE    21
 
-        #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
     #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
+    /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
-/* Size of an Access Control List (ACL) entry in bits. */
+    /* Size of an Access Control List (ACL) entry in bits. */
     #define portACL_ENTRY_SIZE_BITS             ( 32U )
 
     typedef struct MPU_SETTINGS
diff --git a/portable/IAR/ARM_CM33/non_secure/port.c b/portable/IAR/ARM_CM33/non_secure/port.c
index 5c963ea29..b2fd7e518 100644
--- a/portable/IAR/ARM_CM33/non_secure/port.c
+++ b/portable/IAR/ARM_CM33/non_secure/port.c
@@ -169,79 +169,80 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                            ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                            ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                             ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                            ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                            ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                           ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                           ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK        ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                      ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK                     ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                      ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK                     ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                      ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK                     ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                      ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK                     ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                      ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK                     ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                      ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK                     ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                      ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK                     ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                      ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK                     ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0                    ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1                    ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2                    ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3                    ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4                    ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5                    ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6                    ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7                    ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE                  ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
 
 #if ( portARMV8M_MINOR_VERSION >= 1 )
-    /* Enable Privileged eXecute Never MPU attribute for the selected memory
-     * region. */
-    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER   ( 1UL << 4UL )
+
+/* Enable Privileged eXecute Never MPU attribute for the selected memory
+ * region. */
+    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER    ( 1UL << 4UL )
 #endif /* portARMV8M_MINOR_VERSION >= 1 */
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT          ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                          ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE                 ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -380,14 +381,14 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to check and configure PACBTI security feature implementation.
  */
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
-    #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
+    #define portID_ISAR5_REG       ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
 
-    #define portCONTROL_UPAC_EN      ( 1UL << 7UL )
-    #define portCONTROL_PAC_EN       ( 1UL << 6UL )
-    #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
-    #define portCONTROL_BTI_EN       ( 1UL << 4UL )
+    #define portCONTROL_UPAC_EN    ( 1UL << 7UL )
+    #define portCONTROL_PAC_EN     ( 1UL << 6UL )
+    #define portCONTROL_UBTI_EN    ( 1UL << 5UL )
+    #define portCONTROL_BTI_EN     ( 1UL << 4UL )
 
 #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
@@ -409,7 +410,7 @@ static void prvTaskExitError( void );
  * @return uint32_t Access permissions.
  */
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0   */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 
 #if ( configENABLE_MPU == 1 )
 
@@ -427,7 +428,7 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
 /**
  * @brief Configures PACBTI features.
@@ -890,7 +891,7 @@ static void prvTaskExitError( void )
         return ulAccessPermissions;
     }
 
-#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0   */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
@@ -1212,6 +1213,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
+
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __syscalls_flash_start__;
@@ -1282,6 +1284,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
              * point (i.e. the caller of the MPU_<API>). We need to restore it
              * when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+
             /* Store the value of the PSPLIM register before the SVC was raised.
              * We need to restore it when we exit from the system call. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
@@ -1300,6 +1303,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
             /* Start executing the system call upon returning from this handler. */
             pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
+
             /* Raise a request to exit from the system call upon finishing the
              * system call. */
             pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit;
@@ -1359,6 +1363,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
+
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __privileged_functions_start__;
@@ -1541,7 +1546,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
-        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+        #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
         {
             /* Check PACBTI security feature configuration before pushing the
              * CONTROL register's value on task's TCB. */
@@ -1582,6 +1587,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
+        #if ( configENABLE_PAC == 1 )
+        {
+            uint32_t ulTaskPacKey[ 4 ], i;
+
+            vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+            for( i = 0; i < 4; i++ )
+            {
+                xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ];
+                ulIndex++;
+            }
+        }
+        #endif /* configENABLE_PAC */
+
         return &( xMPUSettings->ulContext[ ulIndex ] );
     }
 
@@ -1664,6 +1683,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #endif /* portPRELOAD_REGISTERS */
 
+        #if ( configENABLE_PAC == 1 )
+        {
+            uint32_t ulTaskPacKey[ 4 ], i;
+
+            vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+            for( i = 0; i < 4; i++ )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = ulTaskPacKey[ i ];
+            }
+        }
+        #endif /* configENABLE_PAC */
+
         return pxTopOfStack;
     }
 
@@ -1786,11 +1819,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
-    #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+    #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
     {
         /* Set the CONTROL register value based on PACBTI security feature
          * configuration before starting the first task. */
-        ( void) prvConfigurePACBTI( pdTRUE );
+        ( void ) prvConfigurePACBTI( pdTRUE );
     }
     #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
@@ -1990,9 +2023,9 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
         if( xSchedulerRunning == pdFALSE )
         {
             /* Grant access to all the kernel objects before the scheduler
-            * is started. It is necessary because there is no task running
-            * yet and therefore, we cannot use the permissions of any
-            * task. */
+             * is started. It is necessary because there is no task running
+             * yet and therefore, we cannot use the permissions of any
+             * task. */
             xAccessGranted = pdTRUE;
         }
         else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
@@ -2213,7 +2246,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
 
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
     {
@@ -2225,13 +2258,13 @@ BaseType_t xPortIsInsideInterrupt( void )
         /* Enable UsageFault exception. */
         portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
 
-        #if( configENABLE_PAC == 1 )
+        #if ( configENABLE_PAC == 1 )
         {
             ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
         }
         #endif
 
-        #if( configENABLE_BTI == 1 )
+        #if ( configENABLE_BTI == 1 )
         {
             ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
         }
diff --git a/portable/IAR/ARM_CM33/non_secure/portasm.s b/portable/IAR/ARM_CM33/non_secure/portasm.s
index 212688d61..8d5988819 100644
--- a/portable/IAR/ARM_CM33/non_secure/portasm.s
+++ b/portable/IAR/ARM_CM33/non_secure/portasm.s
@@ -152,6 +152,14 @@ vRestoreContextOfFirstTask:
         ldr r2, [r1]                        /* r2 = Location of saved context in TCB. */
 
     restore_special_regs_first_task:
+    #if ( configENABLE_PAC == 1 )
+        ldmdb r2!, {r3-r6}                  /* Read task's dedicated PAC key from the task's context. */
+        msr  PAC_KEY_P_0, r3                /* Write the task's dedicated PAC key to the PAC key registers. */
+        msr  PAC_KEY_P_1, r4
+        msr  PAC_KEY_P_2, r5
+        msr  PAC_KEY_P_3, r6
+        clrm {r3-r6}                        /* Clear r3-r6. */
+    #endif /* configENABLE_PAC */
         ldmdb r2!, {r0, r3-r5, lr}          /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
         msr psp, r3
         msr psplim, r4
@@ -177,6 +185,15 @@ vRestoreContextOfFirstTask:
     ldr  r3, [r2]                           /* Read pxCurrentTCB. */
     ldr  r0, [r3]                           /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
 
+#if ( configENABLE_PAC == 1 )
+    ldmia r0!, {r1-r4}                      /* Read task's dedicated PAC key from stack. */
+    msr  PAC_KEY_P_3, r1                    /* Write the task's dedicated PAC key to the PAC key registers. */
+    msr  PAC_KEY_P_2, r2
+    msr  PAC_KEY_P_1, r3
+    msr  PAC_KEY_P_0, r4
+    clrm {r1-r4}                            /* Clear r1-r4.  */
+#endif /* configENABLE_PAC */
+
     ldm  r0!, {r1-r3}                       /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
     ldr  r4, =xSecureContext
     str  r1, [r4]                           /* Set xSecureContext to this task's value for the same. */
@@ -271,7 +288,16 @@ PendSV_Handler:
         mrs r4, psplim                      /* r4 = PSPLIM. */
         mrs r5, control                     /* r5 = CONTROL. */
         stmia r2!, {r0, r3-r5, lr}          /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
-        str r2, [r1]                        /* Save the location from where the context should be restored as the first member of TCB. */
+    #if ( configENABLE_PAC == 1 )
+        mrs  r3, PAC_KEY_P_0                /* Read task's dedicated PAC key from the PAC key registers. */
+        mrs  r4, PAC_KEY_P_1
+        mrs  r5, PAC_KEY_P_2
+        mrs  r6, PAC_KEY_P_3
+        stmia r2!, {r3-r6}                  /* Store the task's dedicated PAC key on the task's context. */
+        clrm {r3-r6}                        /* Clear r3-r6. */
+    #endif /* configENABLE_PAC */
+
+    str r2, [r1]                            /* Save the location from where the context should be restored as the first member of TCB. */
 
     select_next_task:
         mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
@@ -329,6 +355,14 @@ PendSV_Handler:
         ldr r2, [r1]                        /* r2 = Location of saved context in TCB. */
 
     restore_special_regs:
+    #if ( configENABLE_PAC == 1 )
+        ldmdb r2!, {r3-r6}                  /* Read task's dedicated PAC key from the task's context. */
+        msr  PAC_KEY_P_0, r3                /* Write the task's dedicated PAC key to the PAC key registers. */
+        msr  PAC_KEY_P_1, r4
+        msr  PAC_KEY_P_2, r5
+        msr  PAC_KEY_P_3, r6
+        clrm {r3-r6}                        /* Clear r3-r6. */
+    #endif /* configENABLE_PAC */
         ldmdb r2!, {r0, r3-r5, lr}          /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
         msr psp, r3
         msr psplim, r4
@@ -374,38 +408,37 @@ PendSV_Handler:
     mrs r2, psp                             /* Read PSP in r2. */
 
     cbz r0, save_ns_context                 /* No secure context to save. */
-    push {r0-r2, r14}
-    bl SecureContext_SaveContext            /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-    pop {r0-r3}                             /* LR is now in r3. */
-    mov lr, r3                              /* LR = r3. */
-    lsls r1, r3, #25                        /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-    bpl save_ns_context                     /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-
-    ldr r3, =pxCurrentTCB                   /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-    ldr r1, [r3]                            /* Read pxCurrentTCB. */
-    subs r2, r2, #12                        /* Make space for xSecureContext, PSPLIM and LR on the stack. */
-    str r2, [r1]                            /* Save the new top of stack in TCB. */
-    mrs r1, psplim                          /* r1 = PSPLIM. */
-    mov r3, lr                              /* r3 = LR/EXC_RETURN. */
-    stmia r2!, {r0, r1, r3}                 /* Store xSecureContext, PSPLIM and LR on the stack. */
-    b select_next_task
+    save_s_context:
+        push {r0-r2, lr}
+        bl SecureContext_SaveContext       /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+        pop {r0-r2, lr}
 
     save_ns_context:
-        ldr r3, =pxCurrentTCB               /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        ldr r1, [r3]                        /* Read pxCurrentTCB. */
+        mov r3, lr                          /* r3 = LR. */
+        lsls r3, r3, #25                    /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+        bmi save_special_regs               /* If r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used. */
+
+    save_general_regs:
     #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
         tst lr, #0x10                       /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
         it eq
         vstmdbeq r2!, {s16-s31}             /* Store the additional FP context registers which are not saved automatically. */
     #endif /* configENABLE_FPU || configENABLE_MVE */
-        subs r2, r2, #44                    /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
-        str r2, [r1]                        /* Save the new top of stack in TCB. */
-        adds r2, r2, #12                    /* r2 = r2 + 12. */
-        stm r2, {r4-r11}                    /* Store the registers that are not saved automatically. */
-        mrs r1, psplim                      /* r1 = PSPLIM. */
-        mov r3, lr                          /* r3 = LR/EXC_RETURN. */
-        subs r2, r2, #12                    /* r2 = r2 - 12. */
-        stmia r2!, {r0, r1, r3}             /* Store xSecureContext, PSPLIM and LR on the stack. */
+        stmdb r2!, {r4-r11}                 /* Store the registers that are not saved automatically. */
+
+    save_special_regs:
+        mrs r3, psplim                      /* r3 = PSPLIM. */
+        stmdb r2!, {r0, r3, lr}             /* Store xSecureContext, PSPLIM and LR on the stack. */
+    #if ( configENABLE_PAC == 1 )
+        mrs  r3, PAC_KEY_P_3                /* Read task's dedicated PAC key from the PAC key registers. */
+        mrs  r4, PAC_KEY_P_2
+        mrs  r5, PAC_KEY_P_1
+        mrs  r6, PAC_KEY_P_0
+        stmdb r2!, {r3-r6}                  /* Store the task's dedicated PAC key on the stack. */
+        clrm {r3-r6}                        /* Clear r3-r6. */
+    #endif /* configENABLE_PAC */
+
+    str r2, [r1]                            /* Save the new top of stack in TCB. */
 
     select_next_task:
         mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
@@ -416,34 +449,45 @@ PendSV_Handler:
         mov r0, #0                          /* r0 = 0. */
         msr basepri, r0                     /* Enable interrupts. */
 
+    restore_context:
         ldr r3, =pxCurrentTCB               /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
         ldr r1, [r3]                        /* Read pxCurrentTCB. */
         ldr r2, [r1]                        /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
 
-        ldmia r2!, {r0, r1, r4}             /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
-        msr psplim, r1                      /* Restore the PSPLIM register value for the task. */
-        mov lr, r4                          /* LR = r4. */
+    restore_special_regs:
+    #if ( configENABLE_PAC == 1 )
+        ldmia r2!, {r3-r6}                  /* Read task's dedicated PAC key from stack. */
+        msr  PAC_KEY_P_3, r3                /* Write the task's dedicated PAC key to the PAC key registers. */
+        msr  PAC_KEY_P_2, r4
+        msr  PAC_KEY_P_1, r5
+        msr  PAC_KEY_P_0, r6
+        clrm {r3-r6}                        /* Clear r3-r6. */
+    #endif /* configENABLE_PAC */
+        ldmia r2!, {r0, r3, lr}             http://files.iar.com/ftp/pub/box/bxarm-9.60.3.deb/* Read from stack - r0 = xSecureContext, r3 = PSPLIM and LR restored. */
+        msr psplim, r3                      /* Restore the PSPLIM register value for the task. */
         ldr r3, =xSecureContext             /* Read the location of xSecureContext i.e. &( xSecureContext ). */
         str r0, [r3]                        /* Restore the task's xSecureContext. */
         cbz r0, restore_ns_context          /* If there is no secure context for the task, restore the non-secure context. */
-        ldr r3, =pxCurrentTCB               /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        ldr r1, [r3]                        /* Read pxCurrentTCB. */
-        push {r2, r4}
+
+    restore_s_context:
+        push {r1-r3, lr}
         bl SecureContext_LoadContext        /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-        pop {r2, r4}
-        mov lr, r4                          /* LR = r4. */
-        lsls r1, r4, #25                    /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-        bpl restore_ns_context              /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-        msr psp, r2                         /* Remember the new top of stack for the task. */
-        bx lr
+        pop {r1-r3, lr}
 
     restore_ns_context:
+        mov r0, lr                          /* r0 = LR (EXC_RETURN). */
+        lsls r0, r0, #25                    /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+        bmi restore_context_done            /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
+
+    restore_general_regs:
         ldmia r2!, {r4-r11}                 /* Restore the registers that are not automatically restored. */
     #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
         tst lr, #0x10                       /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
         it eq
         vldmiaeq r2!, {s16-s31}             /* Restore the additional FP context registers which are not restored automatically. */
     #endif /* configENABLE_FPU || configENABLE_MVE */
+
+    restore_context_done:
         msr psp, r2                         /* Remember the new top of stack for the task. */
         bx lr
 
diff --git a/portable/IAR/ARM_CM33/non_secure/portmacro.h b/portable/IAR/ARM_CM33/non_secure/portmacro.h
index 0f7d100df..53b668b5b 100644
--- a/portable/IAR/ARM_CM33/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM33/non_secure/portmacro.h
@@ -60,7 +60,7 @@
 
 #ifndef configENABLE_MVE
     #define configENABLE_MVE    0
-#elif( configENABLE_MVE != 0 )
+#elif ( configENABLE_MVE != 0 )
     #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M33.
 #endif
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h
index 8a8dc7d6a..e74fa8257 100644
--- a/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -125,6 +127,18 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
     extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
 #endif /* configENABLE_MPU */
+
+#if ( configENABLE_PAC == 1 )
+
+    /**
+     * @brief Generates 128-bit task's random PAC key.
+     *
+     * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be
+     *             filled with a 128-bit random number.
+     */
+    void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey );
+
+#endif /* configENABLE_PAC */
 /*-----------------------------------------------------------*/
 
 /**
@@ -188,9 +202,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Settings to define an MPU region.
- */
+    /**
+     * @brief Settings to define an MPU region.
+     */
     typedef struct MPURegionSettings
     {
         uint32_t ulRBAR; /**< RBAR for the region. */
@@ -203,9 +217,14 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-/**
- * @brief System call stack.
- */
+        /* When MPU wrapper v2 is used, the task's context is stored in TCB and
+         * pxTopOfStack member of TCB points to the context location in TCB. We,
+         * therefore, need to read PSP to find the task's current top of stack. */
+        #define portGET_CURRENT_TOP_OF_STACK( pxCurrentTopOfStack ) { __asm volatile ( "mrs %0, psp"  : "=r" ( pxCurrentTopOfStack ) ); }
+
+        /**
+         * @brief System call stack.
+         */
         typedef struct SYSTEM_CALL_STACK_INFO
         {
             uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ];
@@ -218,76 +237,128 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
-/**
- * @brief MPU settings as stored in the TCB.
- */
+    /**
+     * @brief MPU settings as stored in the TCB.
+     */
     #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+        #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +-----------+---------------+----------+-----------------+------------------------------+-----+
- * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
- * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
- * +-----------+---------------+----------+-----------------+------------------------------+-----+
- *
- * <-----------><--------------><---------><----------------><-----------------------------><---->
- *      16             16            8               8                     5                   1
- */
+            /*
+             * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey |     |
+             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |            |     |
+             * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
+             *      16             16            8               8                     5                     16         1
+             */
+            #define MAX_CONTEXT_SIZE    70
+
+        #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
+
+            /*
+             * +-----------+---------------+----------+-----------------+------------------------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+             * +-----------+---------------+----------+-----------------+------------------------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><-----------------------------><---->
+             *      16             16            8               8                     5                   1
+             */
             #define MAX_CONTEXT_SIZE    54
 
-        #else /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +-----------+---------------+----------+-----------------+----------------------+-----+
- * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
- * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
- * +-----------+---------------+----------+-----------------+----------------------+-----+
- *
- * <-----------><--------------><---------><----------------><---------------------><---->
- *      16             16            8               8                  4              1
- */
+            /*
+             * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey |     |
+             * |           |               |          | PC, xPSR        | EXC_RETURN           |            |     |
+             * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><---------------------><-----------><---->
+             *      16             16            8               8                  4                16         1
+             */
+            #define MAX_CONTEXT_SIZE    69
+
+        #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
+
+            /*
+             * +-----------+---------------+----------+-----------------+----------------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+             * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
+             * +-----------+---------------+----------+-----------------+----------------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><---------------------><---->
+             *      16             16            8               8                  4              1
+             */
             #define MAX_CONTEXT_SIZE    53
 
-        #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
     #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+        #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +----------+-----------------+------------------------------+-----+
- * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
- * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
- * +----------+-----------------+------------------------------+-----+
- *
- * <---------><----------------><------------------------------><---->
- *     8               8                      5                   1
- */
+            /*
+             * +----------+-----------------+------------------------------+------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey |     |
+             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |            |     |
+             * +----------+-----------------+------------------------------+------------+-----+
+             *
+             * <---------><----------------><------------------------------><-----------><---->
+             *     8               8                      5                      16         1
+             */
+            #define MAX_CONTEXT_SIZE    38
+
+        #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
+
+            /*
+             * +----------+-----------------+------------------------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+             * +----------+-----------------+------------------------------+-----+
+             *
+             * <---------><----------------><------------------------------><---->
+             *     8               8                      5                   1
+             */
             #define MAX_CONTEXT_SIZE    22
 
+        #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+            /*
+             * +----------+-----------------+----------------------+------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey |     |
+             * |          | PC, xPSR        | EXC_RETURN           |            |     |
+             * +----------+-----------------+----------------------+------------+-----+
+             *
+             * <---------><----------------><----------------------><-----------><---->
+             *     8               8                  4                  16         1
+             */
+            #define MAX_CONTEXT_SIZE    37
+
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-/*
- * +----------+-----------------+----------------------+-----+
- * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
- * |          | PC, xPSR        | EXC_RETURN           |     |
- * +----------+-----------------+----------------------+-----+
- *
- * <---------><----------------><----------------------><---->
- *     8               8                  4              1
- */
+            /*
+             * +----------+-----------------+----------------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+             * |          | PC, xPSR        | EXC_RETURN           |     |
+             * +----------+-----------------+----------------------+-----+
+             *
+             * <---------><----------------><----------------------><---->
+             *     8               8                  4              1
+             */
             #define MAX_CONTEXT_SIZE    21
 
-        #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
     #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
+    /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
-/* Size of an Access Control List (ACL) entry in bits. */
+    /* Size of an Access Control List (ACL) entry in bits. */
     #define portACL_ENTRY_SIZE_BITS             ( 32U )
 
     typedef struct MPU_SETTINGS
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
index 5c963ea29..b2fd7e518 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
@@ -169,79 +169,80 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                            ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                            ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                             ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                            ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                            ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                           ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                           ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK        ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                      ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK                     ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                      ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK                     ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                      ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK                     ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                      ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK                     ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                      ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK                     ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                      ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK                     ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                      ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK                     ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                      ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK                     ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0                    ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1                    ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2                    ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3                    ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4                    ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5                    ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6                    ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7                    ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE                  ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
 
 #if ( portARMV8M_MINOR_VERSION >= 1 )
-    /* Enable Privileged eXecute Never MPU attribute for the selected memory
-     * region. */
-    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER   ( 1UL << 4UL )
+
+/* Enable Privileged eXecute Never MPU attribute for the selected memory
+ * region. */
+    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER    ( 1UL << 4UL )
 #endif /* portARMV8M_MINOR_VERSION >= 1 */
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT          ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                          ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE                 ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -380,14 +381,14 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to check and configure PACBTI security feature implementation.
  */
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
-    #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
+    #define portID_ISAR5_REG       ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
 
-    #define portCONTROL_UPAC_EN      ( 1UL << 7UL )
-    #define portCONTROL_PAC_EN       ( 1UL << 6UL )
-    #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
-    #define portCONTROL_BTI_EN       ( 1UL << 4UL )
+    #define portCONTROL_UPAC_EN    ( 1UL << 7UL )
+    #define portCONTROL_PAC_EN     ( 1UL << 6UL )
+    #define portCONTROL_UBTI_EN    ( 1UL << 5UL )
+    #define portCONTROL_BTI_EN     ( 1UL << 4UL )
 
 #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
@@ -409,7 +410,7 @@ static void prvTaskExitError( void );
  * @return uint32_t Access permissions.
  */
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0   */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 
 #if ( configENABLE_MPU == 1 )
 
@@ -427,7 +428,7 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
 /**
  * @brief Configures PACBTI features.
@@ -890,7 +891,7 @@ static void prvTaskExitError( void )
         return ulAccessPermissions;
     }
 
-#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0   */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 /*-----------------------------------------------------------*/
 
 #if ( configENABLE_MPU == 1 )
@@ -1212,6 +1213,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
+
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __syscalls_flash_start__;
@@ -1282,6 +1284,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
              * point (i.e. the caller of the MPU_<API>). We need to restore it
              * when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+
             /* Store the value of the PSPLIM register before the SVC was raised.
              * We need to restore it when we exit from the system call. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
@@ -1300,6 +1303,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
             /* Start executing the system call upon returning from this handler. */
             pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
+
             /* Raise a request to exit from the system call upon finishing the
              * system call. */
             pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit;
@@ -1359,6 +1363,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
+
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __privileged_functions_start__;
@@ -1541,7 +1546,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
-        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+        #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
         {
             /* Check PACBTI security feature configuration before pushing the
              * CONTROL register's value on task's TCB. */
@@ -1582,6 +1587,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
+        #if ( configENABLE_PAC == 1 )
+        {
+            uint32_t ulTaskPacKey[ 4 ], i;
+
+            vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+            for( i = 0; i < 4; i++ )
+            {
+                xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ];
+                ulIndex++;
+            }
+        }
+        #endif /* configENABLE_PAC */
+
         return &( xMPUSettings->ulContext[ ulIndex ] );
     }
 
@@ -1664,6 +1683,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #endif /* portPRELOAD_REGISTERS */
 
+        #if ( configENABLE_PAC == 1 )
+        {
+            uint32_t ulTaskPacKey[ 4 ], i;
+
+            vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+            for( i = 0; i < 4; i++ )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = ulTaskPacKey[ i ];
+            }
+        }
+        #endif /* configENABLE_PAC */
+
         return pxTopOfStack;
     }
 
@@ -1786,11 +1819,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
-    #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+    #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
     {
         /* Set the CONTROL register value based on PACBTI security feature
          * configuration before starting the first task. */
-        ( void) prvConfigurePACBTI( pdTRUE );
+        ( void ) prvConfigurePACBTI( pdTRUE );
     }
     #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
@@ -1990,9 +2023,9 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
         if( xSchedulerRunning == pdFALSE )
         {
             /* Grant access to all the kernel objects before the scheduler
-            * is started. It is necessary because there is no task running
-            * yet and therefore, we cannot use the permissions of any
-            * task. */
+             * is started. It is necessary because there is no task running
+             * yet and therefore, we cannot use the permissions of any
+             * task. */
             xAccessGranted = pdTRUE;
         }
         else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
@@ -2213,7 +2246,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
 
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
     {
@@ -2225,13 +2258,13 @@ BaseType_t xPortIsInsideInterrupt( void )
         /* Enable UsageFault exception. */
         portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
 
-        #if( configENABLE_PAC == 1 )
+        #if ( configENABLE_PAC == 1 )
         {
             ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
         }
         #endif
 
-        #if( configENABLE_BTI == 1 )
+        #if ( configENABLE_BTI == 1 )
         {
             ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
         }
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s b/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s
index 9d6c6a7ef..ba6e8e915 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s
@@ -142,6 +142,14 @@ vRestoreContextOfFirstTask:
         ldr r1, [r0]                        /* r1 = Location of saved context in TCB. */
 
     restore_special_regs_first_task:
+    #if ( configENABLE_PAC == 1 )
+        ldmdb r1!, {r2-r5}                  /* Read task's dedicated PAC key from the task's context. */
+        msr  PAC_KEY_P_0, r2                /* Write the task's dedicated PAC key to the PAC key registers. */
+        msr  PAC_KEY_P_1, r3
+        msr  PAC_KEY_P_2, r4
+        msr  PAC_KEY_P_3, r5
+        clrm {r2-r5}                        /* Clear r2-r5. */
+    #endif /* configENABLE_PAC */
         ldmdb r1!, {r2-r4, lr}              /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
         msr psp, r2
         msr psplim, r3
@@ -165,6 +173,15 @@ vRestoreContextOfFirstTask:
     ldr  r1, [r2]                           /* Read pxCurrentTCB. */
     ldr  r0, [r1]                           /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
 
+#if ( configENABLE_PAC == 1 )
+    ldmia r0!, {r1-r4}                      /* Read task's dedicated PAC key from stack. */
+    msr  PAC_KEY_P_3, r1                    /* Write the task's dedicated PAC key to the PAC key registers. */
+    msr  PAC_KEY_P_2, r2
+    msr  PAC_KEY_P_1, r3
+    msr  PAC_KEY_P_0, r4
+    clrm {r1-r4}                            /* Clear r1-r4. */
+#endif /* configENABLE_PAC */
+
     ldm  r0!, {r1-r2}                       /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
     msr  psplim, r1                         /* Set this task's PSPLIM value. */
     mrs  r1, control                        /* Obtain current control register value. */
@@ -233,7 +250,6 @@ PendSV_Handler:
         vstmiaeq r1!, {s0-s16}              /* Store hardware saved FP context. */
         sub r2, r2, #0x20                   /* Set r2 back to the location of hardware saved context. */
     #endif /* configENABLE_FPU || configENABLE_MVE */
-
         stmia r1!, {r4-r11}                 /* Store r4-r11. */
         ldmia r2, {r4-r11}                  /* Copy the hardware saved context into r4-r11. */
         stmia r1!, {r4-r11}                 /* Store the hardware saved context. */
@@ -242,6 +258,15 @@ PendSV_Handler:
         mrs r3, psplim                      /* r3 = PSPLIM. */
         mrs r4, control                     /* r4 = CONTROL. */
         stmia r1!, {r2-r4, lr}              /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
+    #if ( configENABLE_PAC == 1 )
+        mrs  r2, PAC_KEY_P_0                /* Read task's dedicated PAC key from the PAC key registers. */
+        mrs  r3, PAC_KEY_P_1
+        mrs  r4, PAC_KEY_P_2
+        mrs  r5, PAC_KEY_P_3
+        stmia r1!, {r2-r5}                  /* Store the task's dedicated PAC key on the task's context. */
+        clrm {r2-r5}                        /* Clear r2-r5. */
+    #endif /* configENABLE_PAC */
+
         str r1, [r0]                        /* Save the location from where the context should be restored as the first member of TCB. */
 
     select_next_task:
@@ -300,6 +325,14 @@ PendSV_Handler:
         ldr r1, [r0]                        /* r1 = Location of saved context in TCB. */
 
     restore_special_regs:
+    #if ( configENABLE_PAC == 1 )
+        ldmdb r1!, {r2-r5}                  /* Read task's dedicated PAC key from the task's context. */
+        msr  PAC_KEY_P_0, r2                /* Write the task's dedicated PAC key to the PAC key registers. */
+        msr  PAC_KEY_P_1, r3
+        msr  PAC_KEY_P_2, r4
+        msr  PAC_KEY_P_3, r5
+        clrm {r2-r5}                        /* Clear r2-r5. */
+    #endif /* configENABLE_PAC */
         ldmdb r1!, {r2-r4, lr}              /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
         msr psp, r2
         msr psplim, r3
@@ -335,6 +368,15 @@ PendSV_Handler:
     mov r3, lr                              /* r3 = LR/EXC_RETURN. */
     stmdb r0!, {r2-r11}                     /* Store on the stack - PSPLIM, LR and registers that are not automatically. */
 
+#if ( configENABLE_PAC == 1 )
+    mrs  r1, PAC_KEY_P_3                    /* Read task's dedicated PAC key from the PAC key registers. */
+    mrs  r2, PAC_KEY_P_2
+    mrs  r3, PAC_KEY_P_1
+    mrs  r4, PAC_KEY_P_0
+    stmdb r0!, {r1-r4}                      /* Store the task's dedicated PAC key on the stack. */
+    clrm {r1-r4}                            /* Clear r1-r4. */
+#endif /* configENABLE_PAC */
+
     ldr r2, =pxCurrentTCB                   /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
     ldr r1, [r2]                            /* Read pxCurrentTCB. */
     str r0, [r1]                            /* Save the new top of stack in TCB. */
@@ -351,6 +393,15 @@ PendSV_Handler:
     ldr r1, [r2]                            /* Read pxCurrentTCB. */
     ldr r0, [r1]                            /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
 
+#if ( configENABLE_PAC == 1 )
+    ldmia r0!, {r2-r5}                      /* Read task's dedicated PAC key from stack. */
+    msr  PAC_KEY_P_3, r2                    /* Write the task's dedicated PAC key to the PAC key registers. */
+    msr  PAC_KEY_P_2, r3
+    msr  PAC_KEY_P_1, r4
+    msr  PAC_KEY_P_0, r5
+    clrm {r2-r5}                            /* Clear r2-r5. */
+#endif /* configENABLE_PAC */
+
     ldmia r0!, {r2-r11}                     /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
 
 #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h b/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h
index 0f7d100df..53b668b5b 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h
@@ -60,7 +60,7 @@
 
 #ifndef configENABLE_MVE
     #define configENABLE_MVE    0
-#elif( configENABLE_MVE != 0 )
+#elif ( configENABLE_MVE != 0 )
     #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M33.
 #endif
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h
index 8a8dc7d6a..e74fa8257 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -125,6 +127,18 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
     extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
 #endif /* configENABLE_MPU */
+
+#if ( configENABLE_PAC == 1 )
+
+    /**
+     * @brief Generates 128-bit task's random PAC key.
+     *
+     * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be
+     *             filled with a 128-bit random number.
+     */
+    void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey );
+
+#endif /* configENABLE_PAC */
 /*-----------------------------------------------------------*/
 
 /**
@@ -188,9 +202,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Settings to define an MPU region.
- */
+    /**
+     * @brief Settings to define an MPU region.
+     */
     typedef struct MPURegionSettings
     {
         uint32_t ulRBAR; /**< RBAR for the region. */
@@ -203,9 +217,14 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-/**
- * @brief System call stack.
- */
+        /* When MPU wrapper v2 is used, the task's context is stored in TCB and
+         * pxTopOfStack member of TCB points to the context location in TCB. We,
+         * therefore, need to read PSP to find the task's current top of stack. */
+        #define portGET_CURRENT_TOP_OF_STACK( pxCurrentTopOfStack ) { __asm volatile ( "mrs %0, psp"  : "=r" ( pxCurrentTopOfStack ) ); }
+
+        /**
+         * @brief System call stack.
+         */
         typedef struct SYSTEM_CALL_STACK_INFO
         {
             uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ];
@@ -218,76 +237,128 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
-/**
- * @brief MPU settings as stored in the TCB.
- */
+    /**
+     * @brief MPU settings as stored in the TCB.
+     */
     #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+        #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +-----------+---------------+----------+-----------------+------------------------------+-----+
- * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
- * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
- * +-----------+---------------+----------+-----------------+------------------------------+-----+
- *
- * <-----------><--------------><---------><----------------><-----------------------------><---->
- *      16             16            8               8                     5                   1
- */
+            /*
+             * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey |     |
+             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |            |     |
+             * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
+             *      16             16            8               8                     5                     16         1
+             */
+            #define MAX_CONTEXT_SIZE    70
+
+        #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
+
+            /*
+             * +-----------+---------------+----------+-----------------+------------------------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+             * +-----------+---------------+----------+-----------------+------------------------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><-----------------------------><---->
+             *      16             16            8               8                     5                   1
+             */
             #define MAX_CONTEXT_SIZE    54
 
-        #else /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +-----------+---------------+----------+-----------------+----------------------+-----+
- * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
- * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
- * +-----------+---------------+----------+-----------------+----------------------+-----+
- *
- * <-----------><--------------><---------><----------------><---------------------><---->
- *      16             16            8               8                  4              1
- */
+            /*
+             * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey |     |
+             * |           |               |          | PC, xPSR        | EXC_RETURN           |            |     |
+             * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><---------------------><-----------><---->
+             *      16             16            8               8                  4                16         1
+             */
+            #define MAX_CONTEXT_SIZE    69
+
+        #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
+
+            /*
+             * +-----------+---------------+----------+-----------------+----------------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+             * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
+             * +-----------+---------------+----------+-----------------+----------------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><---------------------><---->
+             *      16             16            8               8                  4              1
+             */
             #define MAX_CONTEXT_SIZE    53
 
-        #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
     #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+        #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +----------+-----------------+------------------------------+-----+
- * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
- * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
- * +----------+-----------------+------------------------------+-----+
- *
- * <---------><----------------><------------------------------><---->
- *     8               8                      5                   1
- */
+            /*
+             * +----------+-----------------+------------------------------+------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey |     |
+             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |            |     |
+             * +----------+-----------------+------------------------------+------------+-----+
+             *
+             * <---------><----------------><------------------------------><-----------><---->
+             *     8               8                      5                      16         1
+             */
+            #define MAX_CONTEXT_SIZE    38
+
+        #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
+
+            /*
+             * +----------+-----------------+------------------------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+             * +----------+-----------------+------------------------------+-----+
+             *
+             * <---------><----------------><------------------------------><---->
+             *     8               8                      5                   1
+             */
             #define MAX_CONTEXT_SIZE    22
 
+        #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+            /*
+             * +----------+-----------------+----------------------+------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey |     |
+             * |          | PC, xPSR        | EXC_RETURN           |            |     |
+             * +----------+-----------------+----------------------+------------+-----+
+             *
+             * <---------><----------------><----------------------><-----------><---->
+             *     8               8                  4                  16         1
+             */
+            #define MAX_CONTEXT_SIZE    37
+
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-/*
- * +----------+-----------------+----------------------+-----+
- * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
- * |          | PC, xPSR        | EXC_RETURN           |     |
- * +----------+-----------------+----------------------+-----+
- *
- * <---------><----------------><----------------------><---->
- *     8               8                  4              1
- */
+            /*
+             * +----------+-----------------+----------------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+             * |          | PC, xPSR        | EXC_RETURN           |     |
+             * +----------+-----------------+----------------------+-----+
+             *
+             * <---------><----------------><----------------------><---->
+             *     8               8                  4              1
+             */
             #define MAX_CONTEXT_SIZE    21
 
-        #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
     #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
+    /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
-/* Size of an Access Control List (ACL) entry in bits. */
+    /* Size of an Access Control List (ACL) entry in bits. */
     #define portACL_ENTRY_SIZE_BITS             ( 32U )
 
     typedef struct MPU_SETTINGS
diff --git a/portable/IAR/ARM_CM35P/non_secure/port.c b/portable/IAR/ARM_CM35P/non_secure/port.c
index 9fdbe6d50..b2fd7e518 100644
--- a/portable/IAR/ARM_CM35P/non_secure/port.c
+++ b/portable/IAR/ARM_CM35P/non_secure/port.c
@@ -169,79 +169,80 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                            ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                            ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                             ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                            ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                            ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                           ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                           ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK        ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                      ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK                     ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                      ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK                     ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                      ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK                     ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                      ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK                     ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                      ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK                     ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                      ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK                     ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                      ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK                     ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                      ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK                     ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0                    ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1                    ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2                    ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3                    ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4                    ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5                    ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6                    ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7                    ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE                  ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
 
 #if ( portARMV8M_MINOR_VERSION >= 1 )
-    /* Enable Privileged eXecute Never MPU attribute for the selected memory
-     * region. */
-    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER   ( 1UL << 4UL )
+
+/* Enable Privileged eXecute Never MPU attribute for the selected memory
+ * region. */
+    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER    ( 1UL << 4UL )
 #endif /* portARMV8M_MINOR_VERSION >= 1 */
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT          ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                          ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE                 ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -380,14 +381,14 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to check and configure PACBTI security feature implementation.
  */
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
-    #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
+    #define portID_ISAR5_REG       ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
 
-    #define portCONTROL_UPAC_EN      ( 1UL << 7UL )
-    #define portCONTROL_PAC_EN       ( 1UL << 6UL )
-    #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
-    #define portCONTROL_BTI_EN       ( 1UL << 4UL )
+    #define portCONTROL_UPAC_EN    ( 1UL << 7UL )
+    #define portCONTROL_PAC_EN     ( 1UL << 6UL )
+    #define portCONTROL_UBTI_EN    ( 1UL << 5UL )
+    #define portCONTROL_BTI_EN     ( 1UL << 4UL )
 
 #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
@@ -409,7 +410,7 @@ static void prvTaskExitError( void );
  * @return uint32_t Access permissions.
  */
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0   */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 
 #if ( configENABLE_MPU == 1 )
 
@@ -427,7 +428,7 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
 /**
  * @brief Configures PACBTI features.
@@ -1212,6 +1213,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
+
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __syscalls_flash_start__;
@@ -1282,6 +1284,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
              * point (i.e. the caller of the MPU_<API>). We need to restore it
              * when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+
             /* Store the value of the PSPLIM register before the SVC was raised.
              * We need to restore it when we exit from the system call. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
@@ -1300,6 +1303,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
             /* Start executing the system call upon returning from this handler. */
             pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
+
             /* Raise a request to exit from the system call upon finishing the
              * system call. */
             pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit;
@@ -1359,6 +1363,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
+
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __privileged_functions_start__;
@@ -1541,7 +1546,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
-        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+        #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
         {
             /* Check PACBTI security feature configuration before pushing the
              * CONTROL register's value on task's TCB. */
@@ -1582,6 +1587,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
+        #if ( configENABLE_PAC == 1 )
+        {
+            uint32_t ulTaskPacKey[ 4 ], i;
+
+            vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+            for( i = 0; i < 4; i++ )
+            {
+                xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ];
+                ulIndex++;
+            }
+        }
+        #endif /* configENABLE_PAC */
+
         return &( xMPUSettings->ulContext[ ulIndex ] );
     }
 
@@ -1664,6 +1683,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #endif /* portPRELOAD_REGISTERS */
 
+        #if ( configENABLE_PAC == 1 )
+        {
+            uint32_t ulTaskPacKey[ 4 ], i;
+
+            vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+            for( i = 0; i < 4; i++ )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = ulTaskPacKey[ i ];
+            }
+        }
+        #endif /* configENABLE_PAC */
+
         return pxTopOfStack;
     }
 
@@ -1786,11 +1819,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
-    #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+    #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
     {
         /* Set the CONTROL register value based on PACBTI security feature
          * configuration before starting the first task. */
-        ( void) prvConfigurePACBTI( pdTRUE );
+        ( void ) prvConfigurePACBTI( pdTRUE );
     }
     #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
@@ -1990,9 +2023,9 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
         if( xSchedulerRunning == pdFALSE )
         {
             /* Grant access to all the kernel objects before the scheduler
-            * is started. It is necessary because there is no task running
-            * yet and therefore, we cannot use the permissions of any
-            * task. */
+             * is started. It is necessary because there is no task running
+             * yet and therefore, we cannot use the permissions of any
+             * task. */
             xAccessGranted = pdTRUE;
         }
         else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
@@ -2213,7 +2246,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
 
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
     {
@@ -2225,13 +2258,13 @@ BaseType_t xPortIsInsideInterrupt( void )
         /* Enable UsageFault exception. */
         portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
 
-        #if( configENABLE_PAC == 1 )
+        #if ( configENABLE_PAC == 1 )
         {
             ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
         }
         #endif
 
-        #if( configENABLE_BTI == 1 )
+        #if ( configENABLE_BTI == 1 )
         {
             ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
         }
diff --git a/portable/IAR/ARM_CM35P/non_secure/portasm.s b/portable/IAR/ARM_CM35P/non_secure/portasm.s
index 212688d61..8d5988819 100644
--- a/portable/IAR/ARM_CM35P/non_secure/portasm.s
+++ b/portable/IAR/ARM_CM35P/non_secure/portasm.s
@@ -152,6 +152,14 @@ vRestoreContextOfFirstTask:
         ldr r2, [r1]                        /* r2 = Location of saved context in TCB. */
 
     restore_special_regs_first_task:
+    #if ( configENABLE_PAC == 1 )
+        ldmdb r2!, {r3-r6}                  /* Read task's dedicated PAC key from the task's context. */
+        msr  PAC_KEY_P_0, r3                /* Write the task's dedicated PAC key to the PAC key registers. */
+        msr  PAC_KEY_P_1, r4
+        msr  PAC_KEY_P_2, r5
+        msr  PAC_KEY_P_3, r6
+        clrm {r3-r6}                        /* Clear r3-r6. */
+    #endif /* configENABLE_PAC */
         ldmdb r2!, {r0, r3-r5, lr}          /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
         msr psp, r3
         msr psplim, r4
@@ -177,6 +185,15 @@ vRestoreContextOfFirstTask:
     ldr  r3, [r2]                           /* Read pxCurrentTCB. */
     ldr  r0, [r3]                           /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
 
+#if ( configENABLE_PAC == 1 )
+    ldmia r0!, {r1-r4}                      /* Read task's dedicated PAC key from stack. */
+    msr  PAC_KEY_P_3, r1                    /* Write the task's dedicated PAC key to the PAC key registers. */
+    msr  PAC_KEY_P_2, r2
+    msr  PAC_KEY_P_1, r3
+    msr  PAC_KEY_P_0, r4
+    clrm {r1-r4}                            /* Clear r1-r4.  */
+#endif /* configENABLE_PAC */
+
     ldm  r0!, {r1-r3}                       /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
     ldr  r4, =xSecureContext
     str  r1, [r4]                           /* Set xSecureContext to this task's value for the same. */
@@ -271,7 +288,16 @@ PendSV_Handler:
         mrs r4, psplim                      /* r4 = PSPLIM. */
         mrs r5, control                     /* r5 = CONTROL. */
         stmia r2!, {r0, r3-r5, lr}          /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
-        str r2, [r1]                        /* Save the location from where the context should be restored as the first member of TCB. */
+    #if ( configENABLE_PAC == 1 )
+        mrs  r3, PAC_KEY_P_0                /* Read task's dedicated PAC key from the PAC key registers. */
+        mrs  r4, PAC_KEY_P_1
+        mrs  r5, PAC_KEY_P_2
+        mrs  r6, PAC_KEY_P_3
+        stmia r2!, {r3-r6}                  /* Store the task's dedicated PAC key on the task's context. */
+        clrm {r3-r6}                        /* Clear r3-r6. */
+    #endif /* configENABLE_PAC */
+
+    str r2, [r1]                            /* Save the location from where the context should be restored as the first member of TCB. */
 
     select_next_task:
         mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
@@ -329,6 +355,14 @@ PendSV_Handler:
         ldr r2, [r1]                        /* r2 = Location of saved context in TCB. */
 
     restore_special_regs:
+    #if ( configENABLE_PAC == 1 )
+        ldmdb r2!, {r3-r6}                  /* Read task's dedicated PAC key from the task's context. */
+        msr  PAC_KEY_P_0, r3                /* Write the task's dedicated PAC key to the PAC key registers. */
+        msr  PAC_KEY_P_1, r4
+        msr  PAC_KEY_P_2, r5
+        msr  PAC_KEY_P_3, r6
+        clrm {r3-r6}                        /* Clear r3-r6. */
+    #endif /* configENABLE_PAC */
         ldmdb r2!, {r0, r3-r5, lr}          /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
         msr psp, r3
         msr psplim, r4
@@ -374,38 +408,37 @@ PendSV_Handler:
     mrs r2, psp                             /* Read PSP in r2. */
 
     cbz r0, save_ns_context                 /* No secure context to save. */
-    push {r0-r2, r14}
-    bl SecureContext_SaveContext            /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-    pop {r0-r3}                             /* LR is now in r3. */
-    mov lr, r3                              /* LR = r3. */
-    lsls r1, r3, #25                        /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-    bpl save_ns_context                     /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-
-    ldr r3, =pxCurrentTCB                   /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-    ldr r1, [r3]                            /* Read pxCurrentTCB. */
-    subs r2, r2, #12                        /* Make space for xSecureContext, PSPLIM and LR on the stack. */
-    str r2, [r1]                            /* Save the new top of stack in TCB. */
-    mrs r1, psplim                          /* r1 = PSPLIM. */
-    mov r3, lr                              /* r3 = LR/EXC_RETURN. */
-    stmia r2!, {r0, r1, r3}                 /* Store xSecureContext, PSPLIM and LR on the stack. */
-    b select_next_task
+    save_s_context:
+        push {r0-r2, lr}
+        bl SecureContext_SaveContext       /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+        pop {r0-r2, lr}
 
     save_ns_context:
-        ldr r3, =pxCurrentTCB               /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        ldr r1, [r3]                        /* Read pxCurrentTCB. */
+        mov r3, lr                          /* r3 = LR. */
+        lsls r3, r3, #25                    /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+        bmi save_special_regs               /* If r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used. */
+
+    save_general_regs:
     #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
         tst lr, #0x10                       /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
         it eq
         vstmdbeq r2!, {s16-s31}             /* Store the additional FP context registers which are not saved automatically. */
     #endif /* configENABLE_FPU || configENABLE_MVE */
-        subs r2, r2, #44                    /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
-        str r2, [r1]                        /* Save the new top of stack in TCB. */
-        adds r2, r2, #12                    /* r2 = r2 + 12. */
-        stm r2, {r4-r11}                    /* Store the registers that are not saved automatically. */
-        mrs r1, psplim                      /* r1 = PSPLIM. */
-        mov r3, lr                          /* r3 = LR/EXC_RETURN. */
-        subs r2, r2, #12                    /* r2 = r2 - 12. */
-        stmia r2!, {r0, r1, r3}             /* Store xSecureContext, PSPLIM and LR on the stack. */
+        stmdb r2!, {r4-r11}                 /* Store the registers that are not saved automatically. */
+
+    save_special_regs:
+        mrs r3, psplim                      /* r3 = PSPLIM. */
+        stmdb r2!, {r0, r3, lr}             /* Store xSecureContext, PSPLIM and LR on the stack. */
+    #if ( configENABLE_PAC == 1 )
+        mrs  r3, PAC_KEY_P_3                /* Read task's dedicated PAC key from the PAC key registers. */
+        mrs  r4, PAC_KEY_P_2
+        mrs  r5, PAC_KEY_P_1
+        mrs  r6, PAC_KEY_P_0
+        stmdb r2!, {r3-r6}                  /* Store the task's dedicated PAC key on the stack. */
+        clrm {r3-r6}                        /* Clear r3-r6. */
+    #endif /* configENABLE_PAC */
+
+    str r2, [r1]                            /* Save the new top of stack in TCB. */
 
     select_next_task:
         mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
@@ -416,34 +449,45 @@ PendSV_Handler:
         mov r0, #0                          /* r0 = 0. */
         msr basepri, r0                     /* Enable interrupts. */
 
+    restore_context:
         ldr r3, =pxCurrentTCB               /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
         ldr r1, [r3]                        /* Read pxCurrentTCB. */
         ldr r2, [r1]                        /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
 
-        ldmia r2!, {r0, r1, r4}             /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
-        msr psplim, r1                      /* Restore the PSPLIM register value for the task. */
-        mov lr, r4                          /* LR = r4. */
+    restore_special_regs:
+    #if ( configENABLE_PAC == 1 )
+        ldmia r2!, {r3-r6}                  /* Read task's dedicated PAC key from stack. */
+        msr  PAC_KEY_P_3, r3                /* Write the task's dedicated PAC key to the PAC key registers. */
+        msr  PAC_KEY_P_2, r4
+        msr  PAC_KEY_P_1, r5
+        msr  PAC_KEY_P_0, r6
+        clrm {r3-r6}                        /* Clear r3-r6. */
+    #endif /* configENABLE_PAC */
+        ldmia r2!, {r0, r3, lr}             http://files.iar.com/ftp/pub/box/bxarm-9.60.3.deb/* Read from stack - r0 = xSecureContext, r3 = PSPLIM and LR restored. */
+        msr psplim, r3                      /* Restore the PSPLIM register value for the task. */
         ldr r3, =xSecureContext             /* Read the location of xSecureContext i.e. &( xSecureContext ). */
         str r0, [r3]                        /* Restore the task's xSecureContext. */
         cbz r0, restore_ns_context          /* If there is no secure context for the task, restore the non-secure context. */
-        ldr r3, =pxCurrentTCB               /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        ldr r1, [r3]                        /* Read pxCurrentTCB. */
-        push {r2, r4}
+
+    restore_s_context:
+        push {r1-r3, lr}
         bl SecureContext_LoadContext        /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-        pop {r2, r4}
-        mov lr, r4                          /* LR = r4. */
-        lsls r1, r4, #25                    /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-        bpl restore_ns_context              /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-        msr psp, r2                         /* Remember the new top of stack for the task. */
-        bx lr
+        pop {r1-r3, lr}
 
     restore_ns_context:
+        mov r0, lr                          /* r0 = LR (EXC_RETURN). */
+        lsls r0, r0, #25                    /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+        bmi restore_context_done            /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
+
+    restore_general_regs:
         ldmia r2!, {r4-r11}                 /* Restore the registers that are not automatically restored. */
     #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
         tst lr, #0x10                       /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
         it eq
         vldmiaeq r2!, {s16-s31}             /* Restore the additional FP context registers which are not restored automatically. */
     #endif /* configENABLE_FPU || configENABLE_MVE */
+
+    restore_context_done:
         msr psp, r2                         /* Remember the new top of stack for the task. */
         bx lr
 
diff --git a/portable/IAR/ARM_CM35P/non_secure/portmacro.h b/portable/IAR/ARM_CM35P/non_secure/portmacro.h
index 0ad1009b6..6e543efb5 100644
--- a/portable/IAR/ARM_CM35P/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM35P/non_secure/portmacro.h
@@ -60,7 +60,7 @@
 
 #ifndef configENABLE_MVE
     #define configENABLE_MVE    0
-#elif( configENABLE_MVE != 0 )
+#elif ( configENABLE_MVE != 0 )
     #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M35.
 #endif
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h
index 8a8dc7d6a..e74fa8257 100644
--- a/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -125,6 +127,18 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
     extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
 #endif /* configENABLE_MPU */
+
+#if ( configENABLE_PAC == 1 )
+
+    /**
+     * @brief Generates 128-bit task's random PAC key.
+     *
+     * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be
+     *             filled with a 128-bit random number.
+     */
+    void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey );
+
+#endif /* configENABLE_PAC */
 /*-----------------------------------------------------------*/
 
 /**
@@ -188,9 +202,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Settings to define an MPU region.
- */
+    /**
+     * @brief Settings to define an MPU region.
+     */
     typedef struct MPURegionSettings
     {
         uint32_t ulRBAR; /**< RBAR for the region. */
@@ -203,9 +217,14 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-/**
- * @brief System call stack.
- */
+        /* When MPU wrapper v2 is used, the task's context is stored in TCB and
+         * pxTopOfStack member of TCB points to the context location in TCB. We,
+         * therefore, need to read PSP to find the task's current top of stack. */
+        #define portGET_CURRENT_TOP_OF_STACK( pxCurrentTopOfStack ) { __asm volatile ( "mrs %0, psp"  : "=r" ( pxCurrentTopOfStack ) ); }
+
+        /**
+         * @brief System call stack.
+         */
         typedef struct SYSTEM_CALL_STACK_INFO
         {
             uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ];
@@ -218,76 +237,128 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
-/**
- * @brief MPU settings as stored in the TCB.
- */
+    /**
+     * @brief MPU settings as stored in the TCB.
+     */
     #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+        #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +-----------+---------------+----------+-----------------+------------------------------+-----+
- * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
- * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
- * +-----------+---------------+----------+-----------------+------------------------------+-----+
- *
- * <-----------><--------------><---------><----------------><-----------------------------><---->
- *      16             16            8               8                     5                   1
- */
+            /*
+             * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey |     |
+             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |            |     |
+             * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
+             *      16             16            8               8                     5                     16         1
+             */
+            #define MAX_CONTEXT_SIZE    70
+
+        #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
+
+            /*
+             * +-----------+---------------+----------+-----------------+------------------------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+             * +-----------+---------------+----------+-----------------+------------------------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><-----------------------------><---->
+             *      16             16            8               8                     5                   1
+             */
             #define MAX_CONTEXT_SIZE    54
 
-        #else /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +-----------+---------------+----------+-----------------+----------------------+-----+
- * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
- * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
- * +-----------+---------------+----------+-----------------+----------------------+-----+
- *
- * <-----------><--------------><---------><----------------><---------------------><---->
- *      16             16            8               8                  4              1
- */
+            /*
+             * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey |     |
+             * |           |               |          | PC, xPSR        | EXC_RETURN           |            |     |
+             * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><---------------------><-----------><---->
+             *      16             16            8               8                  4                16         1
+             */
+            #define MAX_CONTEXT_SIZE    69
+
+        #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
+
+            /*
+             * +-----------+---------------+----------+-----------------+----------------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+             * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
+             * +-----------+---------------+----------+-----------------+----------------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><---------------------><---->
+             *      16             16            8               8                  4              1
+             */
             #define MAX_CONTEXT_SIZE    53
 
-        #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
     #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+        #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +----------+-----------------+------------------------------+-----+
- * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
- * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
- * +----------+-----------------+------------------------------+-----+
- *
- * <---------><----------------><------------------------------><---->
- *     8               8                      5                   1
- */
+            /*
+             * +----------+-----------------+------------------------------+------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey |     |
+             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |            |     |
+             * +----------+-----------------+------------------------------+------------+-----+
+             *
+             * <---------><----------------><------------------------------><-----------><---->
+             *     8               8                      5                      16         1
+             */
+            #define MAX_CONTEXT_SIZE    38
+
+        #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
+
+            /*
+             * +----------+-----------------+------------------------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+             * +----------+-----------------+------------------------------+-----+
+             *
+             * <---------><----------------><------------------------------><---->
+             *     8               8                      5                   1
+             */
             #define MAX_CONTEXT_SIZE    22
 
+        #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+            /*
+             * +----------+-----------------+----------------------+------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey |     |
+             * |          | PC, xPSR        | EXC_RETURN           |            |     |
+             * +----------+-----------------+----------------------+------------+-----+
+             *
+             * <---------><----------------><----------------------><-----------><---->
+             *     8               8                  4                  16         1
+             */
+            #define MAX_CONTEXT_SIZE    37
+
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-/*
- * +----------+-----------------+----------------------+-----+
- * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
- * |          | PC, xPSR        | EXC_RETURN           |     |
- * +----------+-----------------+----------------------+-----+
- *
- * <---------><----------------><----------------------><---->
- *     8               8                  4              1
- */
+            /*
+             * +----------+-----------------+----------------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+             * |          | PC, xPSR        | EXC_RETURN           |     |
+             * +----------+-----------------+----------------------+-----+
+             *
+             * <---------><----------------><----------------------><---->
+             *     8               8                  4              1
+             */
             #define MAX_CONTEXT_SIZE    21
 
-        #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
     #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
+    /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
-/* Size of an Access Control List (ACL) entry in bits. */
+    /* Size of an Access Control List (ACL) entry in bits. */
     #define portACL_ENTRY_SIZE_BITS             ( 32U )
 
     typedef struct MPU_SETTINGS
diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c b/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
index f3f5d3edd..b2fd7e518 100644
--- a/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
@@ -169,79 +169,80 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                            ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                            ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                             ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                            ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                            ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                           ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                           ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK        ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                      ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK                     ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                      ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK                     ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                      ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK                     ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                      ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK                     ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                      ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK                     ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                      ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK                     ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                      ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK                     ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                      ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK                     ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0                    ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1                    ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2                    ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3                    ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4                    ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5                    ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6                    ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7                    ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE                  ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
 
 #if ( portARMV8M_MINOR_VERSION >= 1 )
-    /* Enable Privileged eXecute Never MPU attribute for the selected memory
-     * region. */
-    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER   ( 1UL << 4UL )
+
+/* Enable Privileged eXecute Never MPU attribute for the selected memory
+ * region. */
+    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER    ( 1UL << 4UL )
 #endif /* portARMV8M_MINOR_VERSION >= 1 */
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT          ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                          ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE                 ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -380,14 +381,14 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to check and configure PACBTI security feature implementation.
  */
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
-    #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
+    #define portID_ISAR5_REG       ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
 
-    #define portCONTROL_UPAC_EN      ( 1UL << 7UL )
-    #define portCONTROL_PAC_EN       ( 1UL << 6UL )
-    #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
-    #define portCONTROL_BTI_EN       ( 1UL << 4UL )
+    #define portCONTROL_UPAC_EN    ( 1UL << 7UL )
+    #define portCONTROL_PAC_EN     ( 1UL << 6UL )
+    #define portCONTROL_UBTI_EN    ( 1UL << 5UL )
+    #define portCONTROL_BTI_EN     ( 1UL << 4UL )
 
 #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
@@ -427,7 +428,7 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
 /**
  * @brief Configures PACBTI features.
@@ -1212,6 +1213,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
+
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __syscalls_flash_start__;
@@ -1282,6 +1284,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
              * point (i.e. the caller of the MPU_<API>). We need to restore it
              * when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+
             /* Store the value of the PSPLIM register before the SVC was raised.
              * We need to restore it when we exit from the system call. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
@@ -1300,6 +1303,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
             /* Start executing the system call upon returning from this handler. */
             pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
+
             /* Raise a request to exit from the system call upon finishing the
              * system call. */
             pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit;
@@ -1359,6 +1363,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
+
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __privileged_functions_start__;
@@ -1541,7 +1546,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
-        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+        #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
         {
             /* Check PACBTI security feature configuration before pushing the
              * CONTROL register's value on task's TCB. */
@@ -1582,6 +1587,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
+        #if ( configENABLE_PAC == 1 )
+        {
+            uint32_t ulTaskPacKey[ 4 ], i;
+
+            vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+            for( i = 0; i < 4; i++ )
+            {
+                xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ];
+                ulIndex++;
+            }
+        }
+        #endif /* configENABLE_PAC */
+
         return &( xMPUSettings->ulContext[ ulIndex ] );
     }
 
@@ -1664,6 +1683,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #endif /* portPRELOAD_REGISTERS */
 
+        #if ( configENABLE_PAC == 1 )
+        {
+            uint32_t ulTaskPacKey[ 4 ], i;
+
+            vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+            for( i = 0; i < 4; i++ )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = ulTaskPacKey[ i ];
+            }
+        }
+        #endif /* configENABLE_PAC */
+
         return pxTopOfStack;
     }
 
@@ -1786,11 +1819,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
-    #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+    #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
     {
         /* Set the CONTROL register value based on PACBTI security feature
          * configuration before starting the first task. */
-        ( void) prvConfigurePACBTI( pdTRUE );
+        ( void ) prvConfigurePACBTI( pdTRUE );
     }
     #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
@@ -1990,9 +2023,9 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
         if( xSchedulerRunning == pdFALSE )
         {
             /* Grant access to all the kernel objects before the scheduler
-            * is started. It is necessary because there is no task running
-            * yet and therefore, we cannot use the permissions of any
-            * task. */
+             * is started. It is necessary because there is no task running
+             * yet and therefore, we cannot use the permissions of any
+             * task. */
             xAccessGranted = pdTRUE;
         }
         else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
@@ -2213,7 +2246,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
 
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
     {
@@ -2225,13 +2258,13 @@ BaseType_t xPortIsInsideInterrupt( void )
         /* Enable UsageFault exception. */
         portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
 
-        #if( configENABLE_PAC == 1 )
+        #if ( configENABLE_PAC == 1 )
         {
             ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
         }
         #endif
 
-        #if( configENABLE_BTI == 1 )
+        #if ( configENABLE_BTI == 1 )
         {
             ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
         }
diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.s b/portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.s
index 9d6c6a7ef..ba6e8e915 100644
--- a/portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.s
+++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.s
@@ -142,6 +142,14 @@ vRestoreContextOfFirstTask:
         ldr r1, [r0]                        /* r1 = Location of saved context in TCB. */
 
     restore_special_regs_first_task:
+    #if ( configENABLE_PAC == 1 )
+        ldmdb r1!, {r2-r5}                  /* Read task's dedicated PAC key from the task's context. */
+        msr  PAC_KEY_P_0, r2                /* Write the task's dedicated PAC key to the PAC key registers. */
+        msr  PAC_KEY_P_1, r3
+        msr  PAC_KEY_P_2, r4
+        msr  PAC_KEY_P_3, r5
+        clrm {r2-r5}                        /* Clear r2-r5. */
+    #endif /* configENABLE_PAC */
         ldmdb r1!, {r2-r4, lr}              /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
         msr psp, r2
         msr psplim, r3
@@ -165,6 +173,15 @@ vRestoreContextOfFirstTask:
     ldr  r1, [r2]                           /* Read pxCurrentTCB. */
     ldr  r0, [r1]                           /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
 
+#if ( configENABLE_PAC == 1 )
+    ldmia r0!, {r1-r4}                      /* Read task's dedicated PAC key from stack. */
+    msr  PAC_KEY_P_3, r1                    /* Write the task's dedicated PAC key to the PAC key registers. */
+    msr  PAC_KEY_P_2, r2
+    msr  PAC_KEY_P_1, r3
+    msr  PAC_KEY_P_0, r4
+    clrm {r1-r4}                            /* Clear r1-r4. */
+#endif /* configENABLE_PAC */
+
     ldm  r0!, {r1-r2}                       /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
     msr  psplim, r1                         /* Set this task's PSPLIM value. */
     mrs  r1, control                        /* Obtain current control register value. */
@@ -233,7 +250,6 @@ PendSV_Handler:
         vstmiaeq r1!, {s0-s16}              /* Store hardware saved FP context. */
         sub r2, r2, #0x20                   /* Set r2 back to the location of hardware saved context. */
     #endif /* configENABLE_FPU || configENABLE_MVE */
-
         stmia r1!, {r4-r11}                 /* Store r4-r11. */
         ldmia r2, {r4-r11}                  /* Copy the hardware saved context into r4-r11. */
         stmia r1!, {r4-r11}                 /* Store the hardware saved context. */
@@ -242,6 +258,15 @@ PendSV_Handler:
         mrs r3, psplim                      /* r3 = PSPLIM. */
         mrs r4, control                     /* r4 = CONTROL. */
         stmia r1!, {r2-r4, lr}              /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
+    #if ( configENABLE_PAC == 1 )
+        mrs  r2, PAC_KEY_P_0                /* Read task's dedicated PAC key from the PAC key registers. */
+        mrs  r3, PAC_KEY_P_1
+        mrs  r4, PAC_KEY_P_2
+        mrs  r5, PAC_KEY_P_3
+        stmia r1!, {r2-r5}                  /* Store the task's dedicated PAC key on the task's context. */
+        clrm {r2-r5}                        /* Clear r2-r5. */
+    #endif /* configENABLE_PAC */
+
         str r1, [r0]                        /* Save the location from where the context should be restored as the first member of TCB. */
 
     select_next_task:
@@ -300,6 +325,14 @@ PendSV_Handler:
         ldr r1, [r0]                        /* r1 = Location of saved context in TCB. */
 
     restore_special_regs:
+    #if ( configENABLE_PAC == 1 )
+        ldmdb r1!, {r2-r5}                  /* Read task's dedicated PAC key from the task's context. */
+        msr  PAC_KEY_P_0, r2                /* Write the task's dedicated PAC key to the PAC key registers. */
+        msr  PAC_KEY_P_1, r3
+        msr  PAC_KEY_P_2, r4
+        msr  PAC_KEY_P_3, r5
+        clrm {r2-r5}                        /* Clear r2-r5. */
+    #endif /* configENABLE_PAC */
         ldmdb r1!, {r2-r4, lr}              /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
         msr psp, r2
         msr psplim, r3
@@ -335,6 +368,15 @@ PendSV_Handler:
     mov r3, lr                              /* r3 = LR/EXC_RETURN. */
     stmdb r0!, {r2-r11}                     /* Store on the stack - PSPLIM, LR and registers that are not automatically. */
 
+#if ( configENABLE_PAC == 1 )
+    mrs  r1, PAC_KEY_P_3                    /* Read task's dedicated PAC key from the PAC key registers. */
+    mrs  r2, PAC_KEY_P_2
+    mrs  r3, PAC_KEY_P_1
+    mrs  r4, PAC_KEY_P_0
+    stmdb r0!, {r1-r4}                      /* Store the task's dedicated PAC key on the stack. */
+    clrm {r1-r4}                            /* Clear r1-r4. */
+#endif /* configENABLE_PAC */
+
     ldr r2, =pxCurrentTCB                   /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
     ldr r1, [r2]                            /* Read pxCurrentTCB. */
     str r0, [r1]                            /* Save the new top of stack in TCB. */
@@ -351,6 +393,15 @@ PendSV_Handler:
     ldr r1, [r2]                            /* Read pxCurrentTCB. */
     ldr r0, [r1]                            /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
 
+#if ( configENABLE_PAC == 1 )
+    ldmia r0!, {r2-r5}                      /* Read task's dedicated PAC key from stack. */
+    msr  PAC_KEY_P_3, r2                    /* Write the task's dedicated PAC key to the PAC key registers. */
+    msr  PAC_KEY_P_2, r3
+    msr  PAC_KEY_P_1, r4
+    msr  PAC_KEY_P_0, r5
+    clrm {r2-r5}                            /* Clear r2-r5. */
+#endif /* configENABLE_PAC */
+
     ldmia r0!, {r2-r11}                     /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
 
 #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacro.h b/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacro.h
index 0ad1009b6..6e543efb5 100644
--- a/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacro.h
+++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacro.h
@@ -60,7 +60,7 @@
 
 #ifndef configENABLE_MVE
     #define configENABLE_MVE    0
-#elif( configENABLE_MVE != 0 )
+#elif ( configENABLE_MVE != 0 )
     #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M35.
 #endif
 /*-----------------------------------------------------------*/
diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
index 8a8dc7d6a..e74fa8257 100644
--- a/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -125,6 +127,18 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
     extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
 #endif /* configENABLE_MPU */
+
+#if ( configENABLE_PAC == 1 )
+
+    /**
+     * @brief Generates 128-bit task's random PAC key.
+     *
+     * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be
+     *             filled with a 128-bit random number.
+     */
+    void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey );
+
+#endif /* configENABLE_PAC */
 /*-----------------------------------------------------------*/
 
 /**
@@ -188,9 +202,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Settings to define an MPU region.
- */
+    /**
+     * @brief Settings to define an MPU region.
+     */
     typedef struct MPURegionSettings
     {
         uint32_t ulRBAR; /**< RBAR for the region. */
@@ -203,9 +217,14 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-/**
- * @brief System call stack.
- */
+        /* When MPU wrapper v2 is used, the task's context is stored in TCB and
+         * pxTopOfStack member of TCB points to the context location in TCB. We,
+         * therefore, need to read PSP to find the task's current top of stack. */
+        #define portGET_CURRENT_TOP_OF_STACK( pxCurrentTopOfStack ) { __asm volatile ( "mrs %0, psp"  : "=r" ( pxCurrentTopOfStack ) ); }
+
+        /**
+         * @brief System call stack.
+         */
         typedef struct SYSTEM_CALL_STACK_INFO
         {
             uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ];
@@ -218,76 +237,128 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
-/**
- * @brief MPU settings as stored in the TCB.
- */
+    /**
+     * @brief MPU settings as stored in the TCB.
+     */
     #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+        #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +-----------+---------------+----------+-----------------+------------------------------+-----+
- * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
- * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
- * +-----------+---------------+----------+-----------------+------------------------------+-----+
- *
- * <-----------><--------------><---------><----------------><-----------------------------><---->
- *      16             16            8               8                     5                   1
- */
+            /*
+             * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey |     |
+             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |            |     |
+             * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
+             *      16             16            8               8                     5                     16         1
+             */
+            #define MAX_CONTEXT_SIZE    70
+
+        #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
+
+            /*
+             * +-----------+---------------+----------+-----------------+------------------------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+             * +-----------+---------------+----------+-----------------+------------------------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><-----------------------------><---->
+             *      16             16            8               8                     5                   1
+             */
             #define MAX_CONTEXT_SIZE    54
 
-        #else /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +-----------+---------------+----------+-----------------+----------------------+-----+
- * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
- * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
- * +-----------+---------------+----------+-----------------+----------------------+-----+
- *
- * <-----------><--------------><---------><----------------><---------------------><---->
- *      16             16            8               8                  4              1
- */
+            /*
+             * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey |     |
+             * |           |               |          | PC, xPSR        | EXC_RETURN           |            |     |
+             * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><---------------------><-----------><---->
+             *      16             16            8               8                  4                16         1
+             */
+            #define MAX_CONTEXT_SIZE    69
+
+        #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
+
+            /*
+             * +-----------+---------------+----------+-----------------+----------------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+             * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
+             * +-----------+---------------+----------+-----------------+----------------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><---------------------><---->
+             *      16             16            8               8                  4              1
+             */
             #define MAX_CONTEXT_SIZE    53
 
-        #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
     #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+        #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +----------+-----------------+------------------------------+-----+
- * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
- * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
- * +----------+-----------------+------------------------------+-----+
- *
- * <---------><----------------><------------------------------><---->
- *     8               8                      5                   1
- */
+            /*
+             * +----------+-----------------+------------------------------+------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey |     |
+             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |            |     |
+             * +----------+-----------------+------------------------------+------------+-----+
+             *
+             * <---------><----------------><------------------------------><-----------><---->
+             *     8               8                      5                      16         1
+             */
+            #define MAX_CONTEXT_SIZE    38
+
+        #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
+
+            /*
+             * +----------+-----------------+------------------------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+             * +----------+-----------------+------------------------------+-----+
+             *
+             * <---------><----------------><------------------------------><---->
+             *     8               8                      5                   1
+             */
             #define MAX_CONTEXT_SIZE    22
 
+        #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+            /*
+             * +----------+-----------------+----------------------+------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey |     |
+             * |          | PC, xPSR        | EXC_RETURN           |            |     |
+             * +----------+-----------------+----------------------+------------+-----+
+             *
+             * <---------><----------------><----------------------><-----------><---->
+             *     8               8                  4                  16         1
+             */
+            #define MAX_CONTEXT_SIZE    37
+
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-/*
- * +----------+-----------------+----------------------+-----+
- * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
- * |          | PC, xPSR        | EXC_RETURN           |     |
- * +----------+-----------------+----------------------+-----+
- *
- * <---------><----------------><----------------------><---->
- *     8               8                  4              1
- */
+            /*
+             * +----------+-----------------+----------------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+             * |          | PC, xPSR        | EXC_RETURN           |     |
+             * +----------+-----------------+----------------------+-----+
+             *
+             * <---------><----------------><----------------------><---->
+             *     8               8                  4              1
+             */
             #define MAX_CONTEXT_SIZE    21
 
-        #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
     #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
+    /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
-/* Size of an Access Control List (ACL) entry in bits. */
+    /* Size of an Access Control List (ACL) entry in bits. */
     #define portACL_ENTRY_SIZE_BITS             ( 32U )
 
     typedef struct MPU_SETTINGS
diff --git a/portable/IAR/ARM_CM55/non_secure/port.c b/portable/IAR/ARM_CM55/non_secure/port.c
index f3f5d3edd..b2fd7e518 100644
--- a/portable/IAR/ARM_CM55/non_secure/port.c
+++ b/portable/IAR/ARM_CM55/non_secure/port.c
@@ -169,79 +169,80 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                            ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                            ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                             ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                            ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                            ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                           ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                           ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK        ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                      ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK                     ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                      ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK                     ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                      ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK                     ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                      ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK                     ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                      ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK                     ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                      ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK                     ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                      ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK                     ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                      ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK                     ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0                    ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1                    ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2                    ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3                    ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4                    ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5                    ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6                    ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7                    ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE                  ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
 
 #if ( portARMV8M_MINOR_VERSION >= 1 )
-    /* Enable Privileged eXecute Never MPU attribute for the selected memory
-     * region. */
-    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER   ( 1UL << 4UL )
+
+/* Enable Privileged eXecute Never MPU attribute for the selected memory
+ * region. */
+    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER    ( 1UL << 4UL )
 #endif /* portARMV8M_MINOR_VERSION >= 1 */
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT          ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                          ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE                 ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -380,14 +381,14 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to check and configure PACBTI security feature implementation.
  */
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
-    #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
+    #define portID_ISAR5_REG       ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
 
-    #define portCONTROL_UPAC_EN      ( 1UL << 7UL )
-    #define portCONTROL_PAC_EN       ( 1UL << 6UL )
-    #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
-    #define portCONTROL_BTI_EN       ( 1UL << 4UL )
+    #define portCONTROL_UPAC_EN    ( 1UL << 7UL )
+    #define portCONTROL_PAC_EN     ( 1UL << 6UL )
+    #define portCONTROL_UBTI_EN    ( 1UL << 5UL )
+    #define portCONTROL_BTI_EN     ( 1UL << 4UL )
 
 #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
@@ -427,7 +428,7 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
 /**
  * @brief Configures PACBTI features.
@@ -1212,6 +1213,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
+
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __syscalls_flash_start__;
@@ -1282,6 +1284,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
              * point (i.e. the caller of the MPU_<API>). We need to restore it
              * when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+
             /* Store the value of the PSPLIM register before the SVC was raised.
              * We need to restore it when we exit from the system call. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
@@ -1300,6 +1303,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
             /* Start executing the system call upon returning from this handler. */
             pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
+
             /* Raise a request to exit from the system call upon finishing the
              * system call. */
             pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit;
@@ -1359,6 +1363,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
+
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __privileged_functions_start__;
@@ -1541,7 +1546,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
-        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+        #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
         {
             /* Check PACBTI security feature configuration before pushing the
              * CONTROL register's value on task's TCB. */
@@ -1582,6 +1587,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
+        #if ( configENABLE_PAC == 1 )
+        {
+            uint32_t ulTaskPacKey[ 4 ], i;
+
+            vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+            for( i = 0; i < 4; i++ )
+            {
+                xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ];
+                ulIndex++;
+            }
+        }
+        #endif /* configENABLE_PAC */
+
         return &( xMPUSettings->ulContext[ ulIndex ] );
     }
 
@@ -1664,6 +1683,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #endif /* portPRELOAD_REGISTERS */
 
+        #if ( configENABLE_PAC == 1 )
+        {
+            uint32_t ulTaskPacKey[ 4 ], i;
+
+            vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+            for( i = 0; i < 4; i++ )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = ulTaskPacKey[ i ];
+            }
+        }
+        #endif /* configENABLE_PAC */
+
         return pxTopOfStack;
     }
 
@@ -1786,11 +1819,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
-    #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+    #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
     {
         /* Set the CONTROL register value based on PACBTI security feature
          * configuration before starting the first task. */
-        ( void) prvConfigurePACBTI( pdTRUE );
+        ( void ) prvConfigurePACBTI( pdTRUE );
     }
     #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
@@ -1990,9 +2023,9 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
         if( xSchedulerRunning == pdFALSE )
         {
             /* Grant access to all the kernel objects before the scheduler
-            * is started. It is necessary because there is no task running
-            * yet and therefore, we cannot use the permissions of any
-            * task. */
+             * is started. It is necessary because there is no task running
+             * yet and therefore, we cannot use the permissions of any
+             * task. */
             xAccessGranted = pdTRUE;
         }
         else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
@@ -2213,7 +2246,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
 
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
     {
@@ -2225,13 +2258,13 @@ BaseType_t xPortIsInsideInterrupt( void )
         /* Enable UsageFault exception. */
         portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
 
-        #if( configENABLE_PAC == 1 )
+        #if ( configENABLE_PAC == 1 )
         {
             ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
         }
         #endif
 
-        #if( configENABLE_BTI == 1 )
+        #if ( configENABLE_BTI == 1 )
         {
             ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
         }
diff --git a/portable/IAR/ARM_CM55/non_secure/portasm.s b/portable/IAR/ARM_CM55/non_secure/portasm.s
index 212688d61..8d5988819 100644
--- a/portable/IAR/ARM_CM55/non_secure/portasm.s
+++ b/portable/IAR/ARM_CM55/non_secure/portasm.s
@@ -152,6 +152,14 @@ vRestoreContextOfFirstTask:
         ldr r2, [r1]                        /* r2 = Location of saved context in TCB. */
 
     restore_special_regs_first_task:
+    #if ( configENABLE_PAC == 1 )
+        ldmdb r2!, {r3-r6}                  /* Read task's dedicated PAC key from the task's context. */
+        msr  PAC_KEY_P_0, r3                /* Write the task's dedicated PAC key to the PAC key registers. */
+        msr  PAC_KEY_P_1, r4
+        msr  PAC_KEY_P_2, r5
+        msr  PAC_KEY_P_3, r6
+        clrm {r3-r6}                        /* Clear r3-r6. */
+    #endif /* configENABLE_PAC */
         ldmdb r2!, {r0, r3-r5, lr}          /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
         msr psp, r3
         msr psplim, r4
@@ -177,6 +185,15 @@ vRestoreContextOfFirstTask:
     ldr  r3, [r2]                           /* Read pxCurrentTCB. */
     ldr  r0, [r3]                           /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
 
+#if ( configENABLE_PAC == 1 )
+    ldmia r0!, {r1-r4}                      /* Read task's dedicated PAC key from stack. */
+    msr  PAC_KEY_P_3, r1                    /* Write the task's dedicated PAC key to the PAC key registers. */
+    msr  PAC_KEY_P_2, r2
+    msr  PAC_KEY_P_1, r3
+    msr  PAC_KEY_P_0, r4
+    clrm {r1-r4}                            /* Clear r1-r4.  */
+#endif /* configENABLE_PAC */
+
     ldm  r0!, {r1-r3}                       /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
     ldr  r4, =xSecureContext
     str  r1, [r4]                           /* Set xSecureContext to this task's value for the same. */
@@ -271,7 +288,16 @@ PendSV_Handler:
         mrs r4, psplim                      /* r4 = PSPLIM. */
         mrs r5, control                     /* r5 = CONTROL. */
         stmia r2!, {r0, r3-r5, lr}          /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
-        str r2, [r1]                        /* Save the location from where the context should be restored as the first member of TCB. */
+    #if ( configENABLE_PAC == 1 )
+        mrs  r3, PAC_KEY_P_0                /* Read task's dedicated PAC key from the PAC key registers. */
+        mrs  r4, PAC_KEY_P_1
+        mrs  r5, PAC_KEY_P_2
+        mrs  r6, PAC_KEY_P_3
+        stmia r2!, {r3-r6}                  /* Store the task's dedicated PAC key on the task's context. */
+        clrm {r3-r6}                        /* Clear r3-r6. */
+    #endif /* configENABLE_PAC */
+
+    str r2, [r1]                            /* Save the location from where the context should be restored as the first member of TCB. */
 
     select_next_task:
         mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
@@ -329,6 +355,14 @@ PendSV_Handler:
         ldr r2, [r1]                        /* r2 = Location of saved context in TCB. */
 
     restore_special_regs:
+    #if ( configENABLE_PAC == 1 )
+        ldmdb r2!, {r3-r6}                  /* Read task's dedicated PAC key from the task's context. */
+        msr  PAC_KEY_P_0, r3                /* Write the task's dedicated PAC key to the PAC key registers. */
+        msr  PAC_KEY_P_1, r4
+        msr  PAC_KEY_P_2, r5
+        msr  PAC_KEY_P_3, r6
+        clrm {r3-r6}                        /* Clear r3-r6. */
+    #endif /* configENABLE_PAC */
         ldmdb r2!, {r0, r3-r5, lr}          /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
         msr psp, r3
         msr psplim, r4
@@ -374,38 +408,37 @@ PendSV_Handler:
     mrs r2, psp                             /* Read PSP in r2. */
 
     cbz r0, save_ns_context                 /* No secure context to save. */
-    push {r0-r2, r14}
-    bl SecureContext_SaveContext            /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-    pop {r0-r3}                             /* LR is now in r3. */
-    mov lr, r3                              /* LR = r3. */
-    lsls r1, r3, #25                        /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-    bpl save_ns_context                     /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-
-    ldr r3, =pxCurrentTCB                   /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-    ldr r1, [r3]                            /* Read pxCurrentTCB. */
-    subs r2, r2, #12                        /* Make space for xSecureContext, PSPLIM and LR on the stack. */
-    str r2, [r1]                            /* Save the new top of stack in TCB. */
-    mrs r1, psplim                          /* r1 = PSPLIM. */
-    mov r3, lr                              /* r3 = LR/EXC_RETURN. */
-    stmia r2!, {r0, r1, r3}                 /* Store xSecureContext, PSPLIM and LR on the stack. */
-    b select_next_task
+    save_s_context:
+        push {r0-r2, lr}
+        bl SecureContext_SaveContext       /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+        pop {r0-r2, lr}
 
     save_ns_context:
-        ldr r3, =pxCurrentTCB               /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        ldr r1, [r3]                        /* Read pxCurrentTCB. */
+        mov r3, lr                          /* r3 = LR. */
+        lsls r3, r3, #25                    /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+        bmi save_special_regs               /* If r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used. */
+
+    save_general_regs:
     #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
         tst lr, #0x10                       /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
         it eq
         vstmdbeq r2!, {s16-s31}             /* Store the additional FP context registers which are not saved automatically. */
     #endif /* configENABLE_FPU || configENABLE_MVE */
-        subs r2, r2, #44                    /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
-        str r2, [r1]                        /* Save the new top of stack in TCB. */
-        adds r2, r2, #12                    /* r2 = r2 + 12. */
-        stm r2, {r4-r11}                    /* Store the registers that are not saved automatically. */
-        mrs r1, psplim                      /* r1 = PSPLIM. */
-        mov r3, lr                          /* r3 = LR/EXC_RETURN. */
-        subs r2, r2, #12                    /* r2 = r2 - 12. */
-        stmia r2!, {r0, r1, r3}             /* Store xSecureContext, PSPLIM and LR on the stack. */
+        stmdb r2!, {r4-r11}                 /* Store the registers that are not saved automatically. */
+
+    save_special_regs:
+        mrs r3, psplim                      /* r3 = PSPLIM. */
+        stmdb r2!, {r0, r3, lr}             /* Store xSecureContext, PSPLIM and LR on the stack. */
+    #if ( configENABLE_PAC == 1 )
+        mrs  r3, PAC_KEY_P_3                /* Read task's dedicated PAC key from the PAC key registers. */
+        mrs  r4, PAC_KEY_P_2
+        mrs  r5, PAC_KEY_P_1
+        mrs  r6, PAC_KEY_P_0
+        stmdb r2!, {r3-r6}                  /* Store the task's dedicated PAC key on the stack. */
+        clrm {r3-r6}                        /* Clear r3-r6. */
+    #endif /* configENABLE_PAC */
+
+    str r2, [r1]                            /* Save the new top of stack in TCB. */
 
     select_next_task:
         mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
@@ -416,34 +449,45 @@ PendSV_Handler:
         mov r0, #0                          /* r0 = 0. */
         msr basepri, r0                     /* Enable interrupts. */
 
+    restore_context:
         ldr r3, =pxCurrentTCB               /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
         ldr r1, [r3]                        /* Read pxCurrentTCB. */
         ldr r2, [r1]                        /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
 
-        ldmia r2!, {r0, r1, r4}             /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
-        msr psplim, r1                      /* Restore the PSPLIM register value for the task. */
-        mov lr, r4                          /* LR = r4. */
+    restore_special_regs:
+    #if ( configENABLE_PAC == 1 )
+        ldmia r2!, {r3-r6}                  /* Read task's dedicated PAC key from stack. */
+        msr  PAC_KEY_P_3, r3                /* Write the task's dedicated PAC key to the PAC key registers. */
+        msr  PAC_KEY_P_2, r4
+        msr  PAC_KEY_P_1, r5
+        msr  PAC_KEY_P_0, r6
+        clrm {r3-r6}                        /* Clear r3-r6. */
+    #endif /* configENABLE_PAC */
+        ldmia r2!, {r0, r3, lr}             http://files.iar.com/ftp/pub/box/bxarm-9.60.3.deb/* Read from stack - r0 = xSecureContext, r3 = PSPLIM and LR restored. */
+        msr psplim, r3                      /* Restore the PSPLIM register value for the task. */
         ldr r3, =xSecureContext             /* Read the location of xSecureContext i.e. &( xSecureContext ). */
         str r0, [r3]                        /* Restore the task's xSecureContext. */
         cbz r0, restore_ns_context          /* If there is no secure context for the task, restore the non-secure context. */
-        ldr r3, =pxCurrentTCB               /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        ldr r1, [r3]                        /* Read pxCurrentTCB. */
-        push {r2, r4}
+
+    restore_s_context:
+        push {r1-r3, lr}
         bl SecureContext_LoadContext        /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-        pop {r2, r4}
-        mov lr, r4                          /* LR = r4. */
-        lsls r1, r4, #25                    /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-        bpl restore_ns_context              /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-        msr psp, r2                         /* Remember the new top of stack for the task. */
-        bx lr
+        pop {r1-r3, lr}
 
     restore_ns_context:
+        mov r0, lr                          /* r0 = LR (EXC_RETURN). */
+        lsls r0, r0, #25                    /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+        bmi restore_context_done            /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
+
+    restore_general_regs:
         ldmia r2!, {r4-r11}                 /* Restore the registers that are not automatically restored. */
     #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
         tst lr, #0x10                       /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
         it eq
         vldmiaeq r2!, {s16-s31}             /* Restore the additional FP context registers which are not restored automatically. */
     #endif /* configENABLE_FPU || configENABLE_MVE */
+
+    restore_context_done:
         msr psp, r2                         /* Remember the new top of stack for the task. */
         bx lr
 
diff --git a/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h
index 8a8dc7d6a..e74fa8257 100644
--- a/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -125,6 +127,18 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
     extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
 #endif /* configENABLE_MPU */
+
+#if ( configENABLE_PAC == 1 )
+
+    /**
+     * @brief Generates 128-bit task's random PAC key.
+     *
+     * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be
+     *             filled with a 128-bit random number.
+     */
+    void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey );
+
+#endif /* configENABLE_PAC */
 /*-----------------------------------------------------------*/
 
 /**
@@ -188,9 +202,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Settings to define an MPU region.
- */
+    /**
+     * @brief Settings to define an MPU region.
+     */
     typedef struct MPURegionSettings
     {
         uint32_t ulRBAR; /**< RBAR for the region. */
@@ -203,9 +217,14 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-/**
- * @brief System call stack.
- */
+        /* When MPU wrapper v2 is used, the task's context is stored in TCB and
+         * pxTopOfStack member of TCB points to the context location in TCB. We,
+         * therefore, need to read PSP to find the task's current top of stack. */
+        #define portGET_CURRENT_TOP_OF_STACK( pxCurrentTopOfStack ) { __asm volatile ( "mrs %0, psp"  : "=r" ( pxCurrentTopOfStack ) ); }
+
+        /**
+         * @brief System call stack.
+         */
         typedef struct SYSTEM_CALL_STACK_INFO
         {
             uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ];
@@ -218,76 +237,128 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
-/**
- * @brief MPU settings as stored in the TCB.
- */
+    /**
+     * @brief MPU settings as stored in the TCB.
+     */
     #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+        #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +-----------+---------------+----------+-----------------+------------------------------+-----+
- * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
- * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
- * +-----------+---------------+----------+-----------------+------------------------------+-----+
- *
- * <-----------><--------------><---------><----------------><-----------------------------><---->
- *      16             16            8               8                     5                   1
- */
+            /*
+             * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey |     |
+             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |            |     |
+             * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
+             *      16             16            8               8                     5                     16         1
+             */
+            #define MAX_CONTEXT_SIZE    70
+
+        #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
+
+            /*
+             * +-----------+---------------+----------+-----------------+------------------------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+             * +-----------+---------------+----------+-----------------+------------------------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><-----------------------------><---->
+             *      16             16            8               8                     5                   1
+             */
             #define MAX_CONTEXT_SIZE    54
 
-        #else /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +-----------+---------------+----------+-----------------+----------------------+-----+
- * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
- * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
- * +-----------+---------------+----------+-----------------+----------------------+-----+
- *
- * <-----------><--------------><---------><----------------><---------------------><---->
- *      16             16            8               8                  4              1
- */
+            /*
+             * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey |     |
+             * |           |               |          | PC, xPSR        | EXC_RETURN           |            |     |
+             * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><---------------------><-----------><---->
+             *      16             16            8               8                  4                16         1
+             */
+            #define MAX_CONTEXT_SIZE    69
+
+        #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
+
+            /*
+             * +-----------+---------------+----------+-----------------+----------------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+             * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
+             * +-----------+---------------+----------+-----------------+----------------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><---------------------><---->
+             *      16             16            8               8                  4              1
+             */
             #define MAX_CONTEXT_SIZE    53
 
-        #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
     #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+        #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +----------+-----------------+------------------------------+-----+
- * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
- * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
- * +----------+-----------------+------------------------------+-----+
- *
- * <---------><----------------><------------------------------><---->
- *     8               8                      5                   1
- */
+            /*
+             * +----------+-----------------+------------------------------+------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey |     |
+             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |            |     |
+             * +----------+-----------------+------------------------------+------------+-----+
+             *
+             * <---------><----------------><------------------------------><-----------><---->
+             *     8               8                      5                      16         1
+             */
+            #define MAX_CONTEXT_SIZE    38
+
+        #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
+
+            /*
+             * +----------+-----------------+------------------------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+             * +----------+-----------------+------------------------------+-----+
+             *
+             * <---------><----------------><------------------------------><---->
+             *     8               8                      5                   1
+             */
             #define MAX_CONTEXT_SIZE    22
 
+        #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+            /*
+             * +----------+-----------------+----------------------+------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey |     |
+             * |          | PC, xPSR        | EXC_RETURN           |            |     |
+             * +----------+-----------------+----------------------+------------+-----+
+             *
+             * <---------><----------------><----------------------><-----------><---->
+             *     8               8                  4                  16         1
+             */
+            #define MAX_CONTEXT_SIZE    37
+
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-/*
- * +----------+-----------------+----------------------+-----+
- * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
- * |          | PC, xPSR        | EXC_RETURN           |     |
- * +----------+-----------------+----------------------+-----+
- *
- * <---------><----------------><----------------------><---->
- *     8               8                  4              1
- */
+            /*
+             * +----------+-----------------+----------------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+             * |          | PC, xPSR        | EXC_RETURN           |     |
+             * +----------+-----------------+----------------------+-----+
+             *
+             * <---------><----------------><----------------------><---->
+             *     8               8                  4              1
+             */
             #define MAX_CONTEXT_SIZE    21
 
-        #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
     #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
+    /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
-/* Size of an Access Control List (ACL) entry in bits. */
+    /* Size of an Access Control List (ACL) entry in bits. */
     #define portACL_ENTRY_SIZE_BITS             ( 32U )
 
     typedef struct MPU_SETTINGS
diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/port.c b/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
index f3f5d3edd..b2fd7e518 100644
--- a/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
@@ -169,79 +169,80 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                            ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                            ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                             ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                            ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                            ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                           ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                           ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK        ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                      ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK                     ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                      ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK                     ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                      ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK                     ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                      ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK                     ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                      ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK                     ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                      ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK                     ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                      ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK                     ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                      ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK                     ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0                    ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1                    ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2                    ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3                    ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4                    ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5                    ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6                    ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7                    ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE                  ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
 
 #if ( portARMV8M_MINOR_VERSION >= 1 )
-    /* Enable Privileged eXecute Never MPU attribute for the selected memory
-     * region. */
-    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER   ( 1UL << 4UL )
+
+/* Enable Privileged eXecute Never MPU attribute for the selected memory
+ * region. */
+    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER    ( 1UL << 4UL )
 #endif /* portARMV8M_MINOR_VERSION >= 1 */
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT          ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                          ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE                 ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -380,14 +381,14 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to check and configure PACBTI security feature implementation.
  */
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
-    #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
+    #define portID_ISAR5_REG       ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
 
-    #define portCONTROL_UPAC_EN      ( 1UL << 7UL )
-    #define portCONTROL_PAC_EN       ( 1UL << 6UL )
-    #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
-    #define portCONTROL_BTI_EN       ( 1UL << 4UL )
+    #define portCONTROL_UPAC_EN    ( 1UL << 7UL )
+    #define portCONTROL_PAC_EN     ( 1UL << 6UL )
+    #define portCONTROL_UBTI_EN    ( 1UL << 5UL )
+    #define portCONTROL_BTI_EN     ( 1UL << 4UL )
 
 #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
@@ -427,7 +428,7 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
 /**
  * @brief Configures PACBTI features.
@@ -1212,6 +1213,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
+
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __syscalls_flash_start__;
@@ -1282,6 +1284,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
              * point (i.e. the caller of the MPU_<API>). We need to restore it
              * when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+
             /* Store the value of the PSPLIM register before the SVC was raised.
              * We need to restore it when we exit from the system call. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
@@ -1300,6 +1303,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
             /* Start executing the system call upon returning from this handler. */
             pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
+
             /* Raise a request to exit from the system call upon finishing the
              * system call. */
             pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit;
@@ -1359,6 +1363,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
+
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __privileged_functions_start__;
@@ -1541,7 +1546,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
-        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+        #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
         {
             /* Check PACBTI security feature configuration before pushing the
              * CONTROL register's value on task's TCB. */
@@ -1582,6 +1587,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
+        #if ( configENABLE_PAC == 1 )
+        {
+            uint32_t ulTaskPacKey[ 4 ], i;
+
+            vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+            for( i = 0; i < 4; i++ )
+            {
+                xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ];
+                ulIndex++;
+            }
+        }
+        #endif /* configENABLE_PAC */
+
         return &( xMPUSettings->ulContext[ ulIndex ] );
     }
 
@@ -1664,6 +1683,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #endif /* portPRELOAD_REGISTERS */
 
+        #if ( configENABLE_PAC == 1 )
+        {
+            uint32_t ulTaskPacKey[ 4 ], i;
+
+            vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+            for( i = 0; i < 4; i++ )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = ulTaskPacKey[ i ];
+            }
+        }
+        #endif /* configENABLE_PAC */
+
         return pxTopOfStack;
     }
 
@@ -1786,11 +1819,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
-    #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+    #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
     {
         /* Set the CONTROL register value based on PACBTI security feature
          * configuration before starting the first task. */
-        ( void) prvConfigurePACBTI( pdTRUE );
+        ( void ) prvConfigurePACBTI( pdTRUE );
     }
     #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
@@ -1990,9 +2023,9 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
         if( xSchedulerRunning == pdFALSE )
         {
             /* Grant access to all the kernel objects before the scheduler
-            * is started. It is necessary because there is no task running
-            * yet and therefore, we cannot use the permissions of any
-            * task. */
+             * is started. It is necessary because there is no task running
+             * yet and therefore, we cannot use the permissions of any
+             * task. */
             xAccessGranted = pdTRUE;
         }
         else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
@@ -2213,7 +2246,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
 
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
     {
@@ -2225,13 +2258,13 @@ BaseType_t xPortIsInsideInterrupt( void )
         /* Enable UsageFault exception. */
         portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
 
-        #if( configENABLE_PAC == 1 )
+        #if ( configENABLE_PAC == 1 )
         {
             ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
         }
         #endif
 
-        #if( configENABLE_BTI == 1 )
+        #if ( configENABLE_BTI == 1 )
         {
             ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
         }
diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.s b/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.s
index 9d6c6a7ef..ba6e8e915 100644
--- a/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.s
+++ b/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.s
@@ -142,6 +142,14 @@ vRestoreContextOfFirstTask:
         ldr r1, [r0]                        /* r1 = Location of saved context in TCB. */
 
     restore_special_regs_first_task:
+    #if ( configENABLE_PAC == 1 )
+        ldmdb r1!, {r2-r5}                  /* Read task's dedicated PAC key from the task's context. */
+        msr  PAC_KEY_P_0, r2                /* Write the task's dedicated PAC key to the PAC key registers. */
+        msr  PAC_KEY_P_1, r3
+        msr  PAC_KEY_P_2, r4
+        msr  PAC_KEY_P_3, r5
+        clrm {r2-r5}                        /* Clear r2-r5. */
+    #endif /* configENABLE_PAC */
         ldmdb r1!, {r2-r4, lr}              /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
         msr psp, r2
         msr psplim, r3
@@ -165,6 +173,15 @@ vRestoreContextOfFirstTask:
     ldr  r1, [r2]                           /* Read pxCurrentTCB. */
     ldr  r0, [r1]                           /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
 
+#if ( configENABLE_PAC == 1 )
+    ldmia r0!, {r1-r4}                      /* Read task's dedicated PAC key from stack. */
+    msr  PAC_KEY_P_3, r1                    /* Write the task's dedicated PAC key to the PAC key registers. */
+    msr  PAC_KEY_P_2, r2
+    msr  PAC_KEY_P_1, r3
+    msr  PAC_KEY_P_0, r4
+    clrm {r1-r4}                            /* Clear r1-r4. */
+#endif /* configENABLE_PAC */
+
     ldm  r0!, {r1-r2}                       /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
     msr  psplim, r1                         /* Set this task's PSPLIM value. */
     mrs  r1, control                        /* Obtain current control register value. */
@@ -233,7 +250,6 @@ PendSV_Handler:
         vstmiaeq r1!, {s0-s16}              /* Store hardware saved FP context. */
         sub r2, r2, #0x20                   /* Set r2 back to the location of hardware saved context. */
     #endif /* configENABLE_FPU || configENABLE_MVE */
-
         stmia r1!, {r4-r11}                 /* Store r4-r11. */
         ldmia r2, {r4-r11}                  /* Copy the hardware saved context into r4-r11. */
         stmia r1!, {r4-r11}                 /* Store the hardware saved context. */
@@ -242,6 +258,15 @@ PendSV_Handler:
         mrs r3, psplim                      /* r3 = PSPLIM. */
         mrs r4, control                     /* r4 = CONTROL. */
         stmia r1!, {r2-r4, lr}              /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
+    #if ( configENABLE_PAC == 1 )
+        mrs  r2, PAC_KEY_P_0                /* Read task's dedicated PAC key from the PAC key registers. */
+        mrs  r3, PAC_KEY_P_1
+        mrs  r4, PAC_KEY_P_2
+        mrs  r5, PAC_KEY_P_3
+        stmia r1!, {r2-r5}                  /* Store the task's dedicated PAC key on the task's context. */
+        clrm {r2-r5}                        /* Clear r2-r5. */
+    #endif /* configENABLE_PAC */
+
         str r1, [r0]                        /* Save the location from where the context should be restored as the first member of TCB. */
 
     select_next_task:
@@ -300,6 +325,14 @@ PendSV_Handler:
         ldr r1, [r0]                        /* r1 = Location of saved context in TCB. */
 
     restore_special_regs:
+    #if ( configENABLE_PAC == 1 )
+        ldmdb r1!, {r2-r5}                  /* Read task's dedicated PAC key from the task's context. */
+        msr  PAC_KEY_P_0, r2                /* Write the task's dedicated PAC key to the PAC key registers. */
+        msr  PAC_KEY_P_1, r3
+        msr  PAC_KEY_P_2, r4
+        msr  PAC_KEY_P_3, r5
+        clrm {r2-r5}                        /* Clear r2-r5. */
+    #endif /* configENABLE_PAC */
         ldmdb r1!, {r2-r4, lr}              /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
         msr psp, r2
         msr psplim, r3
@@ -335,6 +368,15 @@ PendSV_Handler:
     mov r3, lr                              /* r3 = LR/EXC_RETURN. */
     stmdb r0!, {r2-r11}                     /* Store on the stack - PSPLIM, LR and registers that are not automatically. */
 
+#if ( configENABLE_PAC == 1 )
+    mrs  r1, PAC_KEY_P_3                    /* Read task's dedicated PAC key from the PAC key registers. */
+    mrs  r2, PAC_KEY_P_2
+    mrs  r3, PAC_KEY_P_1
+    mrs  r4, PAC_KEY_P_0
+    stmdb r0!, {r1-r4}                      /* Store the task's dedicated PAC key on the stack. */
+    clrm {r1-r4}                            /* Clear r1-r4. */
+#endif /* configENABLE_PAC */
+
     ldr r2, =pxCurrentTCB                   /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
     ldr r1, [r2]                            /* Read pxCurrentTCB. */
     str r0, [r1]                            /* Save the new top of stack in TCB. */
@@ -351,6 +393,15 @@ PendSV_Handler:
     ldr r1, [r2]                            /* Read pxCurrentTCB. */
     ldr r0, [r1]                            /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
 
+#if ( configENABLE_PAC == 1 )
+    ldmia r0!, {r2-r5}                      /* Read task's dedicated PAC key from stack. */
+    msr  PAC_KEY_P_3, r2                    /* Write the task's dedicated PAC key to the PAC key registers. */
+    msr  PAC_KEY_P_2, r3
+    msr  PAC_KEY_P_1, r4
+    msr  PAC_KEY_P_0, r5
+    clrm {r2-r5}                            /* Clear r2-r5. */
+#endif /* configENABLE_PAC */
+
     ldmia r0!, {r2-r11}                     /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
 
 #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h
index 8a8dc7d6a..e74fa8257 100644
--- a/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -125,6 +127,18 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
     extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
 #endif /* configENABLE_MPU */
+
+#if ( configENABLE_PAC == 1 )
+
+    /**
+     * @brief Generates 128-bit task's random PAC key.
+     *
+     * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be
+     *             filled with a 128-bit random number.
+     */
+    void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey );
+
+#endif /* configENABLE_PAC */
 /*-----------------------------------------------------------*/
 
 /**
@@ -188,9 +202,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Settings to define an MPU region.
- */
+    /**
+     * @brief Settings to define an MPU region.
+     */
     typedef struct MPURegionSettings
     {
         uint32_t ulRBAR; /**< RBAR for the region. */
@@ -203,9 +217,14 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-/**
- * @brief System call stack.
- */
+        /* When MPU wrapper v2 is used, the task's context is stored in TCB and
+         * pxTopOfStack member of TCB points to the context location in TCB. We,
+         * therefore, need to read PSP to find the task's current top of stack. */
+        #define portGET_CURRENT_TOP_OF_STACK( pxCurrentTopOfStack ) { __asm volatile ( "mrs %0, psp"  : "=r" ( pxCurrentTopOfStack ) ); }
+
+        /**
+         * @brief System call stack.
+         */
         typedef struct SYSTEM_CALL_STACK_INFO
         {
             uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ];
@@ -218,76 +237,128 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
-/**
- * @brief MPU settings as stored in the TCB.
- */
+    /**
+     * @brief MPU settings as stored in the TCB.
+     */
     #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+        #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +-----------+---------------+----------+-----------------+------------------------------+-----+
- * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
- * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
- * +-----------+---------------+----------+-----------------+------------------------------+-----+
- *
- * <-----------><--------------><---------><----------------><-----------------------------><---->
- *      16             16            8               8                     5                   1
- */
+            /*
+             * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey |     |
+             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |            |     |
+             * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
+             *      16             16            8               8                     5                     16         1
+             */
+            #define MAX_CONTEXT_SIZE    70
+
+        #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
+
+            /*
+             * +-----------+---------------+----------+-----------------+------------------------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+             * +-----------+---------------+----------+-----------------+------------------------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><-----------------------------><---->
+             *      16             16            8               8                     5                   1
+             */
             #define MAX_CONTEXT_SIZE    54
 
-        #else /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +-----------+---------------+----------+-----------------+----------------------+-----+
- * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
- * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
- * +-----------+---------------+----------+-----------------+----------------------+-----+
- *
- * <-----------><--------------><---------><----------------><---------------------><---->
- *      16             16            8               8                  4              1
- */
+            /*
+             * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey |     |
+             * |           |               |          | PC, xPSR        | EXC_RETURN           |            |     |
+             * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><---------------------><-----------><---->
+             *      16             16            8               8                  4                16         1
+             */
+            #define MAX_CONTEXT_SIZE    69
+
+        #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
+
+            /*
+             * +-----------+---------------+----------+-----------------+----------------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+             * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
+             * +-----------+---------------+----------+-----------------+----------------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><---------------------><---->
+             *      16             16            8               8                  4              1
+             */
             #define MAX_CONTEXT_SIZE    53
 
-        #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
     #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+        #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +----------+-----------------+------------------------------+-----+
- * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
- * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
- * +----------+-----------------+------------------------------+-----+
- *
- * <---------><----------------><------------------------------><---->
- *     8               8                      5                   1
- */
+            /*
+             * +----------+-----------------+------------------------------+------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey |     |
+             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |            |     |
+             * +----------+-----------------+------------------------------+------------+-----+
+             *
+             * <---------><----------------><------------------------------><-----------><---->
+             *     8               8                      5                      16         1
+             */
+            #define MAX_CONTEXT_SIZE    38
+
+        #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
+
+            /*
+             * +----------+-----------------+------------------------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+             * +----------+-----------------+------------------------------+-----+
+             *
+             * <---------><----------------><------------------------------><---->
+             *     8               8                      5                   1
+             */
             #define MAX_CONTEXT_SIZE    22
 
+        #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+            /*
+             * +----------+-----------------+----------------------+------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey |     |
+             * |          | PC, xPSR        | EXC_RETURN           |            |     |
+             * +----------+-----------------+----------------------+------------+-----+
+             *
+             * <---------><----------------><----------------------><-----------><---->
+             *     8               8                  4                  16         1
+             */
+            #define MAX_CONTEXT_SIZE    37
+
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-/*
- * +----------+-----------------+----------------------+-----+
- * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
- * |          | PC, xPSR        | EXC_RETURN           |     |
- * +----------+-----------------+----------------------+-----+
- *
- * <---------><----------------><----------------------><---->
- *     8               8                  4              1
- */
+            /*
+             * +----------+-----------------+----------------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+             * |          | PC, xPSR        | EXC_RETURN           |     |
+             * +----------+-----------------+----------------------+-----+
+             *
+             * <---------><----------------><----------------------><---->
+             *     8               8                  4              1
+             */
             #define MAX_CONTEXT_SIZE    21
 
-        #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
     #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
+    /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
-/* Size of an Access Control List (ACL) entry in bits. */
+    /* Size of an Access Control List (ACL) entry in bits. */
     #define portACL_ENTRY_SIZE_BITS             ( 32U )
 
     typedef struct MPU_SETTINGS
diff --git a/portable/IAR/ARM_CM85/non_secure/port.c b/portable/IAR/ARM_CM85/non_secure/port.c
index f3f5d3edd..b2fd7e518 100644
--- a/portable/IAR/ARM_CM85/non_secure/port.c
+++ b/portable/IAR/ARM_CM85/non_secure/port.c
@@ -169,79 +169,80 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                            ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                            ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                             ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                            ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                            ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                           ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                           ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK        ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                      ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK                     ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                      ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK                     ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                      ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK                     ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                      ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK                     ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                      ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK                     ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                      ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK                     ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                      ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK                     ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                      ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK                     ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0                    ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1                    ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2                    ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3                    ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4                    ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5                    ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6                    ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7                    ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE                  ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
 
 #if ( portARMV8M_MINOR_VERSION >= 1 )
-    /* Enable Privileged eXecute Never MPU attribute for the selected memory
-     * region. */
-    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER   ( 1UL << 4UL )
+
+/* Enable Privileged eXecute Never MPU attribute for the selected memory
+ * region. */
+    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER    ( 1UL << 4UL )
 #endif /* portARMV8M_MINOR_VERSION >= 1 */
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT          ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                          ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE                 ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -380,14 +381,14 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to check and configure PACBTI security feature implementation.
  */
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
-    #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
+    #define portID_ISAR5_REG       ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
 
-    #define portCONTROL_UPAC_EN      ( 1UL << 7UL )
-    #define portCONTROL_PAC_EN       ( 1UL << 6UL )
-    #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
-    #define portCONTROL_BTI_EN       ( 1UL << 4UL )
+    #define portCONTROL_UPAC_EN    ( 1UL << 7UL )
+    #define portCONTROL_PAC_EN     ( 1UL << 6UL )
+    #define portCONTROL_UBTI_EN    ( 1UL << 5UL )
+    #define portCONTROL_BTI_EN     ( 1UL << 4UL )
 
 #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
@@ -427,7 +428,7 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
 /**
  * @brief Configures PACBTI features.
@@ -1212,6 +1213,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
+
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __syscalls_flash_start__;
@@ -1282,6 +1284,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
              * point (i.e. the caller of the MPU_<API>). We need to restore it
              * when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+
             /* Store the value of the PSPLIM register before the SVC was raised.
              * We need to restore it when we exit from the system call. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
@@ -1300,6 +1303,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
             /* Start executing the system call upon returning from this handler. */
             pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
+
             /* Raise a request to exit from the system call upon finishing the
              * system call. */
             pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit;
@@ -1359,6 +1363,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
+
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __privileged_functions_start__;
@@ -1541,7 +1546,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
-        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+        #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
         {
             /* Check PACBTI security feature configuration before pushing the
              * CONTROL register's value on task's TCB. */
@@ -1582,6 +1587,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
+        #if ( configENABLE_PAC == 1 )
+        {
+            uint32_t ulTaskPacKey[ 4 ], i;
+
+            vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+            for( i = 0; i < 4; i++ )
+            {
+                xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ];
+                ulIndex++;
+            }
+        }
+        #endif /* configENABLE_PAC */
+
         return &( xMPUSettings->ulContext[ ulIndex ] );
     }
 
@@ -1664,6 +1683,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #endif /* portPRELOAD_REGISTERS */
 
+        #if ( configENABLE_PAC == 1 )
+        {
+            uint32_t ulTaskPacKey[ 4 ], i;
+
+            vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+            for( i = 0; i < 4; i++ )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = ulTaskPacKey[ i ];
+            }
+        }
+        #endif /* configENABLE_PAC */
+
         return pxTopOfStack;
     }
 
@@ -1786,11 +1819,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
-    #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+    #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
     {
         /* Set the CONTROL register value based on PACBTI security feature
          * configuration before starting the first task. */
-        ( void) prvConfigurePACBTI( pdTRUE );
+        ( void ) prvConfigurePACBTI( pdTRUE );
     }
     #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
@@ -1990,9 +2023,9 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
         if( xSchedulerRunning == pdFALSE )
         {
             /* Grant access to all the kernel objects before the scheduler
-            * is started. It is necessary because there is no task running
-            * yet and therefore, we cannot use the permissions of any
-            * task. */
+             * is started. It is necessary because there is no task running
+             * yet and therefore, we cannot use the permissions of any
+             * task. */
             xAccessGranted = pdTRUE;
         }
         else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
@@ -2213,7 +2246,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
 
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
     {
@@ -2225,13 +2258,13 @@ BaseType_t xPortIsInsideInterrupt( void )
         /* Enable UsageFault exception. */
         portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
 
-        #if( configENABLE_PAC == 1 )
+        #if ( configENABLE_PAC == 1 )
         {
             ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
         }
         #endif
 
-        #if( configENABLE_BTI == 1 )
+        #if ( configENABLE_BTI == 1 )
         {
             ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
         }
diff --git a/portable/IAR/ARM_CM85/non_secure/portasm.s b/portable/IAR/ARM_CM85/non_secure/portasm.s
index 212688d61..8d5988819 100644
--- a/portable/IAR/ARM_CM85/non_secure/portasm.s
+++ b/portable/IAR/ARM_CM85/non_secure/portasm.s
@@ -152,6 +152,14 @@ vRestoreContextOfFirstTask:
         ldr r2, [r1]                        /* r2 = Location of saved context in TCB. */
 
     restore_special_regs_first_task:
+    #if ( configENABLE_PAC == 1 )
+        ldmdb r2!, {r3-r6}                  /* Read task's dedicated PAC key from the task's context. */
+        msr  PAC_KEY_P_0, r3                /* Write the task's dedicated PAC key to the PAC key registers. */
+        msr  PAC_KEY_P_1, r4
+        msr  PAC_KEY_P_2, r5
+        msr  PAC_KEY_P_3, r6
+        clrm {r3-r6}                        /* Clear r3-r6. */
+    #endif /* configENABLE_PAC */
         ldmdb r2!, {r0, r3-r5, lr}          /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
         msr psp, r3
         msr psplim, r4
@@ -177,6 +185,15 @@ vRestoreContextOfFirstTask:
     ldr  r3, [r2]                           /* Read pxCurrentTCB. */
     ldr  r0, [r3]                           /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
 
+#if ( configENABLE_PAC == 1 )
+    ldmia r0!, {r1-r4}                      /* Read task's dedicated PAC key from stack. */
+    msr  PAC_KEY_P_3, r1                    /* Write the task's dedicated PAC key to the PAC key registers. */
+    msr  PAC_KEY_P_2, r2
+    msr  PAC_KEY_P_1, r3
+    msr  PAC_KEY_P_0, r4
+    clrm {r1-r4}                            /* Clear r1-r4.  */
+#endif /* configENABLE_PAC */
+
     ldm  r0!, {r1-r3}                       /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
     ldr  r4, =xSecureContext
     str  r1, [r4]                           /* Set xSecureContext to this task's value for the same. */
@@ -271,7 +288,16 @@ PendSV_Handler:
         mrs r4, psplim                      /* r4 = PSPLIM. */
         mrs r5, control                     /* r5 = CONTROL. */
         stmia r2!, {r0, r3-r5, lr}          /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
-        str r2, [r1]                        /* Save the location from where the context should be restored as the first member of TCB. */
+    #if ( configENABLE_PAC == 1 )
+        mrs  r3, PAC_KEY_P_0                /* Read task's dedicated PAC key from the PAC key registers. */
+        mrs  r4, PAC_KEY_P_1
+        mrs  r5, PAC_KEY_P_2
+        mrs  r6, PAC_KEY_P_3
+        stmia r2!, {r3-r6}                  /* Store the task's dedicated PAC key on the task's context. */
+        clrm {r3-r6}                        /* Clear r3-r6. */
+    #endif /* configENABLE_PAC */
+
+    str r2, [r1]                            /* Save the location from where the context should be restored as the first member of TCB. */
 
     select_next_task:
         mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
@@ -329,6 +355,14 @@ PendSV_Handler:
         ldr r2, [r1]                        /* r2 = Location of saved context in TCB. */
 
     restore_special_regs:
+    #if ( configENABLE_PAC == 1 )
+        ldmdb r2!, {r3-r6}                  /* Read task's dedicated PAC key from the task's context. */
+        msr  PAC_KEY_P_0, r3                /* Write the task's dedicated PAC key to the PAC key registers. */
+        msr  PAC_KEY_P_1, r4
+        msr  PAC_KEY_P_2, r5
+        msr  PAC_KEY_P_3, r6
+        clrm {r3-r6}                        /* Clear r3-r6. */
+    #endif /* configENABLE_PAC */
         ldmdb r2!, {r0, r3-r5, lr}          /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
         msr psp, r3
         msr psplim, r4
@@ -374,38 +408,37 @@ PendSV_Handler:
     mrs r2, psp                             /* Read PSP in r2. */
 
     cbz r0, save_ns_context                 /* No secure context to save. */
-    push {r0-r2, r14}
-    bl SecureContext_SaveContext            /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-    pop {r0-r3}                             /* LR is now in r3. */
-    mov lr, r3                              /* LR = r3. */
-    lsls r1, r3, #25                        /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-    bpl save_ns_context                     /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-
-    ldr r3, =pxCurrentTCB                   /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-    ldr r1, [r3]                            /* Read pxCurrentTCB. */
-    subs r2, r2, #12                        /* Make space for xSecureContext, PSPLIM and LR on the stack. */
-    str r2, [r1]                            /* Save the new top of stack in TCB. */
-    mrs r1, psplim                          /* r1 = PSPLIM. */
-    mov r3, lr                              /* r3 = LR/EXC_RETURN. */
-    stmia r2!, {r0, r1, r3}                 /* Store xSecureContext, PSPLIM and LR on the stack. */
-    b select_next_task
+    save_s_context:
+        push {r0-r2, lr}
+        bl SecureContext_SaveContext       /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+        pop {r0-r2, lr}
 
     save_ns_context:
-        ldr r3, =pxCurrentTCB               /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        ldr r1, [r3]                        /* Read pxCurrentTCB. */
+        mov r3, lr                          /* r3 = LR. */
+        lsls r3, r3, #25                    /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+        bmi save_special_regs               /* If r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used. */
+
+    save_general_regs:
     #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
         tst lr, #0x10                       /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
         it eq
         vstmdbeq r2!, {s16-s31}             /* Store the additional FP context registers which are not saved automatically. */
     #endif /* configENABLE_FPU || configENABLE_MVE */
-        subs r2, r2, #44                    /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
-        str r2, [r1]                        /* Save the new top of stack in TCB. */
-        adds r2, r2, #12                    /* r2 = r2 + 12. */
-        stm r2, {r4-r11}                    /* Store the registers that are not saved automatically. */
-        mrs r1, psplim                      /* r1 = PSPLIM. */
-        mov r3, lr                          /* r3 = LR/EXC_RETURN. */
-        subs r2, r2, #12                    /* r2 = r2 - 12. */
-        stmia r2!, {r0, r1, r3}             /* Store xSecureContext, PSPLIM and LR on the stack. */
+        stmdb r2!, {r4-r11}                 /* Store the registers that are not saved automatically. */
+
+    save_special_regs:
+        mrs r3, psplim                      /* r3 = PSPLIM. */
+        stmdb r2!, {r0, r3, lr}             /* Store xSecureContext, PSPLIM and LR on the stack. */
+    #if ( configENABLE_PAC == 1 )
+        mrs  r3, PAC_KEY_P_3                /* Read task's dedicated PAC key from the PAC key registers. */
+        mrs  r4, PAC_KEY_P_2
+        mrs  r5, PAC_KEY_P_1
+        mrs  r6, PAC_KEY_P_0
+        stmdb r2!, {r3-r6}                  /* Store the task's dedicated PAC key on the stack. */
+        clrm {r3-r6}                        /* Clear r3-r6. */
+    #endif /* configENABLE_PAC */
+
+    str r2, [r1]                            /* Save the new top of stack in TCB. */
 
     select_next_task:
         mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
@@ -416,34 +449,45 @@ PendSV_Handler:
         mov r0, #0                          /* r0 = 0. */
         msr basepri, r0                     /* Enable interrupts. */
 
+    restore_context:
         ldr r3, =pxCurrentTCB               /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
         ldr r1, [r3]                        /* Read pxCurrentTCB. */
         ldr r2, [r1]                        /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
 
-        ldmia r2!, {r0, r1, r4}             /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
-        msr psplim, r1                      /* Restore the PSPLIM register value for the task. */
-        mov lr, r4                          /* LR = r4. */
+    restore_special_regs:
+    #if ( configENABLE_PAC == 1 )
+        ldmia r2!, {r3-r6}                  /* Read task's dedicated PAC key from stack. */
+        msr  PAC_KEY_P_3, r3                /* Write the task's dedicated PAC key to the PAC key registers. */
+        msr  PAC_KEY_P_2, r4
+        msr  PAC_KEY_P_1, r5
+        msr  PAC_KEY_P_0, r6
+        clrm {r3-r6}                        /* Clear r3-r6. */
+    #endif /* configENABLE_PAC */
+        ldmia r2!, {r0, r3, lr}             http://files.iar.com/ftp/pub/box/bxarm-9.60.3.deb/* Read from stack - r0 = xSecureContext, r3 = PSPLIM and LR restored. */
+        msr psplim, r3                      /* Restore the PSPLIM register value for the task. */
         ldr r3, =xSecureContext             /* Read the location of xSecureContext i.e. &( xSecureContext ). */
         str r0, [r3]                        /* Restore the task's xSecureContext. */
         cbz r0, restore_ns_context          /* If there is no secure context for the task, restore the non-secure context. */
-        ldr r3, =pxCurrentTCB               /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        ldr r1, [r3]                        /* Read pxCurrentTCB. */
-        push {r2, r4}
+
+    restore_s_context:
+        push {r1-r3, lr}
         bl SecureContext_LoadContext        /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-        pop {r2, r4}
-        mov lr, r4                          /* LR = r4. */
-        lsls r1, r4, #25                    /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-        bpl restore_ns_context              /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-        msr psp, r2                         /* Remember the new top of stack for the task. */
-        bx lr
+        pop {r1-r3, lr}
 
     restore_ns_context:
+        mov r0, lr                          /* r0 = LR (EXC_RETURN). */
+        lsls r0, r0, #25                    /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+        bmi restore_context_done            /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
+
+    restore_general_regs:
         ldmia r2!, {r4-r11}                 /* Restore the registers that are not automatically restored. */
     #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
         tst lr, #0x10                       /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
         it eq
         vldmiaeq r2!, {s16-s31}             /* Restore the additional FP context registers which are not restored automatically. */
     #endif /* configENABLE_FPU || configENABLE_MVE */
+
+    restore_context_done:
         msr psp, r2                         /* Remember the new top of stack for the task. */
         bx lr
 
diff --git a/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h
index 8a8dc7d6a..e74fa8257 100644
--- a/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -125,6 +127,18 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
     extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
 #endif /* configENABLE_MPU */
+
+#if ( configENABLE_PAC == 1 )
+
+    /**
+     * @brief Generates 128-bit task's random PAC key.
+     *
+     * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be
+     *             filled with a 128-bit random number.
+     */
+    void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey );
+
+#endif /* configENABLE_PAC */
 /*-----------------------------------------------------------*/
 
 /**
@@ -188,9 +202,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Settings to define an MPU region.
- */
+    /**
+     * @brief Settings to define an MPU region.
+     */
     typedef struct MPURegionSettings
     {
         uint32_t ulRBAR; /**< RBAR for the region. */
@@ -203,9 +217,14 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-/**
- * @brief System call stack.
- */
+        /* When MPU wrapper v2 is used, the task's context is stored in TCB and
+         * pxTopOfStack member of TCB points to the context location in TCB. We,
+         * therefore, need to read PSP to find the task's current top of stack. */
+        #define portGET_CURRENT_TOP_OF_STACK( pxCurrentTopOfStack ) { __asm volatile ( "mrs %0, psp"  : "=r" ( pxCurrentTopOfStack ) ); }
+
+        /**
+         * @brief System call stack.
+         */
         typedef struct SYSTEM_CALL_STACK_INFO
         {
             uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ];
@@ -218,76 +237,128 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
-/**
- * @brief MPU settings as stored in the TCB.
- */
+    /**
+     * @brief MPU settings as stored in the TCB.
+     */
     #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+        #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +-----------+---------------+----------+-----------------+------------------------------+-----+
- * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
- * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
- * +-----------+---------------+----------+-----------------+------------------------------+-----+
- *
- * <-----------><--------------><---------><----------------><-----------------------------><---->
- *      16             16            8               8                     5                   1
- */
+            /*
+             * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey |     |
+             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |            |     |
+             * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
+             *      16             16            8               8                     5                     16         1
+             */
+            #define MAX_CONTEXT_SIZE    70
+
+        #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
+
+            /*
+             * +-----------+---------------+----------+-----------------+------------------------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+             * +-----------+---------------+----------+-----------------+------------------------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><-----------------------------><---->
+             *      16             16            8               8                     5                   1
+             */
             #define MAX_CONTEXT_SIZE    54
 
-        #else /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +-----------+---------------+----------+-----------------+----------------------+-----+
- * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
- * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
- * +-----------+---------------+----------+-----------------+----------------------+-----+
- *
- * <-----------><--------------><---------><----------------><---------------------><---->
- *      16             16            8               8                  4              1
- */
+            /*
+             * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey |     |
+             * |           |               |          | PC, xPSR        | EXC_RETURN           |            |     |
+             * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><---------------------><-----------><---->
+             *      16             16            8               8                  4                16         1
+             */
+            #define MAX_CONTEXT_SIZE    69
+
+        #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
+
+            /*
+             * +-----------+---------------+----------+-----------------+----------------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+             * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
+             * +-----------+---------------+----------+-----------------+----------------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><---------------------><---->
+             *      16             16            8               8                  4              1
+             */
             #define MAX_CONTEXT_SIZE    53
 
-        #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
     #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+        #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +----------+-----------------+------------------------------+-----+
- * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
- * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
- * +----------+-----------------+------------------------------+-----+
- *
- * <---------><----------------><------------------------------><---->
- *     8               8                      5                   1
- */
+            /*
+             * +----------+-----------------+------------------------------+------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey |     |
+             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |            |     |
+             * +----------+-----------------+------------------------------+------------+-----+
+             *
+             * <---------><----------------><------------------------------><-----------><---->
+             *     8               8                      5                      16         1
+             */
+            #define MAX_CONTEXT_SIZE    38
+
+        #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
+
+            /*
+             * +----------+-----------------+------------------------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+             * +----------+-----------------+------------------------------+-----+
+             *
+             * <---------><----------------><------------------------------><---->
+             *     8               8                      5                   1
+             */
             #define MAX_CONTEXT_SIZE    22
 
+        #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+            /*
+             * +----------+-----------------+----------------------+------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey |     |
+             * |          | PC, xPSR        | EXC_RETURN           |            |     |
+             * +----------+-----------------+----------------------+------------+-----+
+             *
+             * <---------><----------------><----------------------><-----------><---->
+             *     8               8                  4                  16         1
+             */
+            #define MAX_CONTEXT_SIZE    37
+
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-/*
- * +----------+-----------------+----------------------+-----+
- * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
- * |          | PC, xPSR        | EXC_RETURN           |     |
- * +----------+-----------------+----------------------+-----+
- *
- * <---------><----------------><----------------------><---->
- *     8               8                  4              1
- */
+            /*
+             * +----------+-----------------+----------------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+             * |          | PC, xPSR        | EXC_RETURN           |     |
+             * +----------+-----------------+----------------------+-----+
+             *
+             * <---------><----------------><----------------------><---->
+             *     8               8                  4              1
+             */
             #define MAX_CONTEXT_SIZE    21
 
-        #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
     #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
+    /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
-/* Size of an Access Control List (ACL) entry in bits. */
+    /* Size of an Access Control List (ACL) entry in bits. */
     #define portACL_ENTRY_SIZE_BITS             ( 32U )
 
     typedef struct MPU_SETTINGS
diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/port.c b/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
index f3f5d3edd..b2fd7e518 100644
--- a/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
@@ -169,79 +169,80 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the MPU.
  */
-#define portMPU_TYPE_REG                            ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG                            ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG                             ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG                        ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                        ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                         ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
 
-#define portMPU_RBAR_REG                            ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG                            ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG                        ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                        ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
 
-#define portMPU_RBAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG                         ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                     ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
 
-#define portMPU_RBAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG                         ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                     ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
 
-#define portMPU_RBAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG                         ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                     ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
 
-#define portMPU_MAIR0_REG                           ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG                           ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK                   ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
 
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK        ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
-#define portMPU_MAIR_ATTR0_POS                      ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK                     ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR1_POS                      ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK                     ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR2_POS                      ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK                     ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR3_POS                      ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK                     ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                 ( 0xff000000 )
 
-#define portMPU_MAIR_ATTR4_POS                      ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK                     ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS                  ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                 ( 0x000000ff )
 
-#define portMPU_MAIR_ATTR5_POS                      ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK                     ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS                  ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                 ( 0x0000ff00 )
 
-#define portMPU_MAIR_ATTR6_POS                      ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK                     ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS                  ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                 ( 0x00ff0000 )
 
-#define portMPU_MAIR_ATTR7_POS                      ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK                     ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS                  ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                 ( 0xff000000 )
 
-#define portMPU_RLAR_ATTR_INDEX0                    ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1                    ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2                    ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3                    ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4                    ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5                    ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6                    ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7                    ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0                ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1                ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2                ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3                ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4                ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5                ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6                ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7                ( 7UL << 1UL )
 
-#define portMPU_RLAR_REGION_ENABLE                  ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE              ( 1UL )
 
 #if ( portARMV8M_MINOR_VERSION >= 1 )
-    /* Enable Privileged eXecute Never MPU attribute for the selected memory
-     * region. */
-    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER   ( 1UL << 4UL )
+
+/* Enable Privileged eXecute Never MPU attribute for the selected memory
+ * region. */
+    #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER    ( 1UL << 4UL )
 #endif /* portARMV8M_MINOR_VERSION >= 1 */
 
 /* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE_BIT          ( 1UL << 2UL )
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )
 
 /* Enable MPU. */
-#define portMPU_ENABLE_BIT                          ( 1UL << 0UL )
+#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
 
 /* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE                 ( configTOTAL_MPU_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
 
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
@@ -380,14 +381,14 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to check and configure PACBTI security feature implementation.
  */
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
-    #define portID_ISAR5_REG         ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
+    #define portID_ISAR5_REG       ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
 
-    #define portCONTROL_UPAC_EN      ( 1UL << 7UL )
-    #define portCONTROL_PAC_EN       ( 1UL << 6UL )
-    #define portCONTROL_UBTI_EN      ( 1UL << 5UL )
-    #define portCONTROL_BTI_EN       ( 1UL << 4UL )
+    #define portCONTROL_UPAC_EN    ( 1UL << 7UL )
+    #define portCONTROL_PAC_EN     ( 1UL << 6UL )
+    #define portCONTROL_UBTI_EN    ( 1UL << 5UL )
+    #define portCONTROL_BTI_EN     ( 1UL << 4UL )
 
 #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 /*-----------------------------------------------------------*/
@@ -427,7 +428,7 @@ static void prvTaskExitError( void );
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
 /**
  * @brief Configures PACBTI features.
@@ -1212,6 +1213,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
+
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __syscalls_flash_start__;
@@ -1282,6 +1284,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
              * point (i.e. the caller of the MPU_<API>). We need to restore it
              * when we exit from the system call. */
             pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+
             /* Store the value of the PSPLIM register before the SVC was raised.
              * We need to restore it when we exit from the system call. */
             #if ( portUSE_PSPLIM_REGISTER == 1 )
@@ -1300,6 +1303,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
             /* Start executing the system call upon returning from this handler. */
             pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
+
             /* Raise a request to exit from the system call upon finishing the
              * system call. */
             pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit;
@@ -1359,6 +1363,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         uint32_t ulStackFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
+
             /* Declaration when these variable are defined in code instead of being
              * exported from linker scripts. */
             extern uint32_t * __privileged_functions_start__;
@@ -1541,7 +1546,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
         ulIndex++;
 
-        #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+        #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
         {
             /* Check PACBTI security feature configuration before pushing the
              * CONTROL register's value on task's TCB. */
@@ -1582,6 +1587,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
+        #if ( configENABLE_PAC == 1 )
+        {
+            uint32_t ulTaskPacKey[ 4 ], i;
+
+            vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+            for( i = 0; i < 4; i++ )
+            {
+                xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ];
+                ulIndex++;
+            }
+        }
+        #endif /* configENABLE_PAC */
+
         return &( xMPUSettings->ulContext[ ulIndex ] );
     }
 
@@ -1664,6 +1683,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #endif /* portPRELOAD_REGISTERS */
 
+        #if ( configENABLE_PAC == 1 )
+        {
+            uint32_t ulTaskPacKey[ 4 ], i;
+
+            vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+            for( i = 0; i < 4; i++ )
+            {
+                pxTopOfStack--;
+                *pxTopOfStack = ulTaskPacKey[ i ];
+            }
+        }
+        #endif /* configENABLE_PAC */
+
         return pxTopOfStack;
     }
 
@@ -1786,11 +1819,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
     portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
     portNVIC_SHPR2_REG = 0;
 
-    #if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+    #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
     {
         /* Set the CONTROL register value based on PACBTI security feature
          * configuration before starting the first task. */
-        ( void) prvConfigurePACBTI( pdTRUE );
+        ( void ) prvConfigurePACBTI( pdTRUE );
     }
     #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
 
@@ -1990,9 +2023,9 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
         if( xSchedulerRunning == pdFALSE )
         {
             /* Grant access to all the kernel objects before the scheduler
-            * is started. It is necessary because there is no task running
-            * yet and therefore, we cannot use the permissions of any
-            * task. */
+             * is started. It is necessary because there is no task running
+             * yet and therefore, we cannot use the permissions of any
+             * task. */
             xAccessGranted = pdTRUE;
         }
         else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
@@ -2213,7 +2246,7 @@ BaseType_t xPortIsInsideInterrupt( void )
 #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
 /*-----------------------------------------------------------*/
 
-#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
     {
@@ -2225,13 +2258,13 @@ BaseType_t xPortIsInsideInterrupt( void )
         /* Enable UsageFault exception. */
         portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
 
-        #if( configENABLE_PAC == 1 )
+        #if ( configENABLE_PAC == 1 )
         {
             ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
         }
         #endif
 
-        #if( configENABLE_BTI == 1 )
+        #if ( configENABLE_BTI == 1 )
         {
             ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
         }
diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.s b/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.s
index 9d6c6a7ef..ba6e8e915 100644
--- a/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.s
+++ b/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.s
@@ -142,6 +142,14 @@ vRestoreContextOfFirstTask:
         ldr r1, [r0]                        /* r1 = Location of saved context in TCB. */
 
     restore_special_regs_first_task:
+    #if ( configENABLE_PAC == 1 )
+        ldmdb r1!, {r2-r5}                  /* Read task's dedicated PAC key from the task's context. */
+        msr  PAC_KEY_P_0, r2                /* Write the task's dedicated PAC key to the PAC key registers. */
+        msr  PAC_KEY_P_1, r3
+        msr  PAC_KEY_P_2, r4
+        msr  PAC_KEY_P_3, r5
+        clrm {r2-r5}                        /* Clear r2-r5. */
+    #endif /* configENABLE_PAC */
         ldmdb r1!, {r2-r4, lr}              /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
         msr psp, r2
         msr psplim, r3
@@ -165,6 +173,15 @@ vRestoreContextOfFirstTask:
     ldr  r1, [r2]                           /* Read pxCurrentTCB. */
     ldr  r0, [r1]                           /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
 
+#if ( configENABLE_PAC == 1 )
+    ldmia r0!, {r1-r4}                      /* Read task's dedicated PAC key from stack. */
+    msr  PAC_KEY_P_3, r1                    /* Write the task's dedicated PAC key to the PAC key registers. */
+    msr  PAC_KEY_P_2, r2
+    msr  PAC_KEY_P_1, r3
+    msr  PAC_KEY_P_0, r4
+    clrm {r1-r4}                            /* Clear r1-r4. */
+#endif /* configENABLE_PAC */
+
     ldm  r0!, {r1-r2}                       /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
     msr  psplim, r1                         /* Set this task's PSPLIM value. */
     mrs  r1, control                        /* Obtain current control register value. */
@@ -233,7 +250,6 @@ PendSV_Handler:
         vstmiaeq r1!, {s0-s16}              /* Store hardware saved FP context. */
         sub r2, r2, #0x20                   /* Set r2 back to the location of hardware saved context. */
     #endif /* configENABLE_FPU || configENABLE_MVE */
-
         stmia r1!, {r4-r11}                 /* Store r4-r11. */
         ldmia r2, {r4-r11}                  /* Copy the hardware saved context into r4-r11. */
         stmia r1!, {r4-r11}                 /* Store the hardware saved context. */
@@ -242,6 +258,15 @@ PendSV_Handler:
         mrs r3, psplim                      /* r3 = PSPLIM. */
         mrs r4, control                     /* r4 = CONTROL. */
         stmia r1!, {r2-r4, lr}              /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
+    #if ( configENABLE_PAC == 1 )
+        mrs  r2, PAC_KEY_P_0                /* Read task's dedicated PAC key from the PAC key registers. */
+        mrs  r3, PAC_KEY_P_1
+        mrs  r4, PAC_KEY_P_2
+        mrs  r5, PAC_KEY_P_3
+        stmia r1!, {r2-r5}                  /* Store the task's dedicated PAC key on the task's context. */
+        clrm {r2-r5}                        /* Clear r2-r5. */
+    #endif /* configENABLE_PAC */
+
         str r1, [r0]                        /* Save the location from where the context should be restored as the first member of TCB. */
 
     select_next_task:
@@ -300,6 +325,14 @@ PendSV_Handler:
         ldr r1, [r0]                        /* r1 = Location of saved context in TCB. */
 
     restore_special_regs:
+    #if ( configENABLE_PAC == 1 )
+        ldmdb r1!, {r2-r5}                  /* Read task's dedicated PAC key from the task's context. */
+        msr  PAC_KEY_P_0, r2                /* Write the task's dedicated PAC key to the PAC key registers. */
+        msr  PAC_KEY_P_1, r3
+        msr  PAC_KEY_P_2, r4
+        msr  PAC_KEY_P_3, r5
+        clrm {r2-r5}                        /* Clear r2-r5. */
+    #endif /* configENABLE_PAC */
         ldmdb r1!, {r2-r4, lr}              /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
         msr psp, r2
         msr psplim, r3
@@ -335,6 +368,15 @@ PendSV_Handler:
     mov r3, lr                              /* r3 = LR/EXC_RETURN. */
     stmdb r0!, {r2-r11}                     /* Store on the stack - PSPLIM, LR and registers that are not automatically. */
 
+#if ( configENABLE_PAC == 1 )
+    mrs  r1, PAC_KEY_P_3                    /* Read task's dedicated PAC key from the PAC key registers. */
+    mrs  r2, PAC_KEY_P_2
+    mrs  r3, PAC_KEY_P_1
+    mrs  r4, PAC_KEY_P_0
+    stmdb r0!, {r1-r4}                      /* Store the task's dedicated PAC key on the stack. */
+    clrm {r1-r4}                            /* Clear r1-r4. */
+#endif /* configENABLE_PAC */
+
     ldr r2, =pxCurrentTCB                   /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
     ldr r1, [r2]                            /* Read pxCurrentTCB. */
     str r0, [r1]                            /* Save the new top of stack in TCB. */
@@ -351,6 +393,15 @@ PendSV_Handler:
     ldr r1, [r2]                            /* Read pxCurrentTCB. */
     ldr r0, [r1]                            /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
 
+#if ( configENABLE_PAC == 1 )
+    ldmia r0!, {r2-r5}                      /* Read task's dedicated PAC key from stack. */
+    msr  PAC_KEY_P_3, r2                    /* Write the task's dedicated PAC key to the PAC key registers. */
+    msr  PAC_KEY_P_2, r3
+    msr  PAC_KEY_P_1, r4
+    msr  PAC_KEY_P_0, r5
+    clrm {r2-r5}                            /* Clear r2-r5. */
+#endif /* configENABLE_PAC */
+
     ldmia r0!, {r2-r11}                     /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
 
 #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h
index 8a8dc7d6a..e74fa8257 100644
--- a/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -125,6 +127,18 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
     extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
 #endif /* configENABLE_MPU */
+
+#if ( configENABLE_PAC == 1 )
+
+    /**
+     * @brief Generates 128-bit task's random PAC key.
+     *
+     * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be
+     *             filled with a 128-bit random number.
+     */
+    void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey );
+
+#endif /* configENABLE_PAC */
 /*-----------------------------------------------------------*/
 
 /**
@@ -188,9 +202,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Settings to define an MPU region.
- */
+    /**
+     * @brief Settings to define an MPU region.
+     */
     typedef struct MPURegionSettings
     {
         uint32_t ulRBAR; /**< RBAR for the region. */
@@ -203,9 +217,14 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-/**
- * @brief System call stack.
- */
+        /* When MPU wrapper v2 is used, the task's context is stored in TCB and
+         * pxTopOfStack member of TCB points to the context location in TCB. We,
+         * therefore, need to read PSP to find the task's current top of stack. */
+        #define portGET_CURRENT_TOP_OF_STACK( pxCurrentTopOfStack ) { __asm volatile ( "mrs %0, psp"  : "=r" ( pxCurrentTopOfStack ) ); }
+
+        /**
+         * @brief System call stack.
+         */
         typedef struct SYSTEM_CALL_STACK_INFO
         {
             uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ];
@@ -218,76 +237,128 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
-/**
- * @brief MPU settings as stored in the TCB.
- */
+    /**
+     * @brief MPU settings as stored in the TCB.
+     */
     #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+        #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +-----------+---------------+----------+-----------------+------------------------------+-----+
- * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
- * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
- * +-----------+---------------+----------+-----------------+------------------------------+-----+
- *
- * <-----------><--------------><---------><----------------><-----------------------------><---->
- *      16             16            8               8                     5                   1
- */
+            /*
+             * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey |     |
+             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |            |     |
+             * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
+             *      16             16            8               8                     5                     16         1
+             */
+            #define MAX_CONTEXT_SIZE    70
+
+        #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
+
+            /*
+             * +-----------+---------------+----------+-----------------+------------------------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+             * +-----------+---------------+----------+-----------------+------------------------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><-----------------------------><---->
+             *      16             16            8               8                     5                   1
+             */
             #define MAX_CONTEXT_SIZE    54
 
-        #else /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +-----------+---------------+----------+-----------------+----------------------+-----+
- * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
- * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
- * +-----------+---------------+----------+-----------------+----------------------+-----+
- *
- * <-----------><--------------><---------><----------------><---------------------><---->
- *      16             16            8               8                  4              1
- */
+            /*
+             * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey |     |
+             * |           |               |          | PC, xPSR        | EXC_RETURN           |            |     |
+             * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><---------------------><-----------><---->
+             *      16             16            8               8                  4                16         1
+             */
+            #define MAX_CONTEXT_SIZE    69
+
+        #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
+
+            /*
+             * +-----------+---------------+----------+-----------------+----------------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+             * |           |               |          | PC, xPSR        | EXC_RETURN           |     |
+             * +-----------+---------------+----------+-----------------+----------------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><---------------------><---->
+             *      16             16            8               8                  4              1
+             */
             #define MAX_CONTEXT_SIZE    53
 
-        #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
     #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-        #if ( configENABLE_TRUSTZONE == 1 )
+        #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
 
-/*
- * +----------+-----------------+------------------------------+-----+
- * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
- * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
- * +----------+-----------------+------------------------------+-----+
- *
- * <---------><----------------><------------------------------><---->
- *     8               8                      5                   1
- */
+            /*
+             * +----------+-----------------+------------------------------+------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey |     |
+             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |            |     |
+             * +----------+-----------------+------------------------------+------------+-----+
+             *
+             * <---------><----------------><------------------------------><-----------><---->
+             *     8               8                      5                      16         1
+             */
+            #define MAX_CONTEXT_SIZE    38
+
+        #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
+
+            /*
+             * +----------+-----------------+------------------------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, |     |
+             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |     |
+             * +----------+-----------------+------------------------------+-----+
+             *
+             * <---------><----------------><------------------------------><---->
+             *     8               8                      5                   1
+             */
             #define MAX_CONTEXT_SIZE    22
 
+        #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+            /*
+             * +----------+-----------------+----------------------+------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey |     |
+             * |          | PC, xPSR        | EXC_RETURN           |            |     |
+             * +----------+-----------------+----------------------+------------+-----+
+             *
+             * <---------><----------------><----------------------><-----------><---->
+             *     8               8                  4                  16         1
+             */
+            #define MAX_CONTEXT_SIZE    37
+
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
-/*
- * +----------+-----------------+----------------------+-----+
- * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
- * |          | PC, xPSR        | EXC_RETURN           |     |
- * +----------+-----------------+----------------------+-----+
- *
- * <---------><----------------><----------------------><---->
- *     8               8                  4              1
- */
+            /*
+             * +----------+-----------------+----------------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL |     |
+             * |          | PC, xPSR        | EXC_RETURN           |     |
+             * +----------+-----------------+----------------------+-----+
+             *
+             * <---------><----------------><----------------------><---->
+             *     8               8                  4              1
+             */
             #define MAX_CONTEXT_SIZE    21
 
-        #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
     #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
+    /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
     #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
     #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
 
-/* Size of an Access Control List (ACL) entry in bits. */
+    /* Size of an Access Control List (ACL) entry in bits. */
     #define portACL_ENTRY_SIZE_BITS             ( 32U )
 
     typedef struct MPU_SETTINGS

From a58579681c908d1e7896de488f2dc5003d9214a7 Mon Sep 17 00:00:00 2001
From: John Boiles <johnaboiles@gmail.com>
Date: Tue, 21 Jan 2025 00:50:16 -0800
Subject: [PATCH 369/424] POSIX Simulator: Remove unused __APPLE__ mach_vm.h
 include (#1225)

Remove unused __APPLE__ mach_vm.h include
---
 .github/workflows/kernel-demos.yml   | 17 +++++++++++++----
 portable/ThirdParty/GCC/Posix/port.c |  4 ----
 2 files changed, 13 insertions(+), 8 deletions(-)

diff --git a/.github/workflows/kernel-demos.yml b/.github/workflows/kernel-demos.yml
index 94d5c73e2..f81ae33f3 100644
--- a/.github/workflows/kernel-demos.yml
+++ b/.github/workflows/kernel-demos.yml
@@ -150,16 +150,25 @@ jobs:
         with:
           path: ./FreeRTOS/Source
 
-      - name: Install MSP430 Toolchain
+      - env:
+          stepName: Install MSP430 Toolchain
         shell: bash
         run: |
-          sudo apt-get -y update
-          sudo apt-get -y install gcc-msp430 build-essential
+          # ${{ env.stepName }}
+          echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}"
+          curl -L -O https://dr-download.ti.com/software-development/ide-configuration-compiler-or-debugger/MD-LlCjWuAbzH/9.3.1.2/msp430-gcc-full-linux-x64-installer-9.3.1.2.7z
+          sudo apt update -y
+          sudo apt install -y p7zip-full
+          7z x ./msp430-gcc-full-linux-x64-installer-9.3.1.2.7z
+          chmod +x ./msp430-gcc-full-linux-x64-installer-9.3.1.2.run
+          sudo ./msp430-gcc-full-linux-x64-installer-9.3.1.2.run --prefix /usr/bin/msp430-gcc --mode unattended
+          echo "::endgroup::"
+          echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }}"
 
       - name: Build msp430_GCC Demo
         shell: bash
         working-directory: FreeRTOS/Demo/msp430_GCC
-        run: make -j
+        run: make -j CC=/usr/bin/msp430-gcc/bin/msp430-elf-gcc OPT="-Os -I/usr/bin/msp430-gcc/include -L/usr/bin/msp430-gcc/include"
 
   MicroBlaze-GCC:
     name: GCC MicroBlaze Toolchain
diff --git a/portable/ThirdParty/GCC/Posix/port.c b/portable/ThirdParty/GCC/Posix/port.c
index 1bec7afd8..7cc32128f 100644
--- a/portable/ThirdParty/GCC/Posix/port.c
+++ b/portable/ThirdParty/GCC/Posix/port.c
@@ -65,10 +65,6 @@
 #include <time.h>
 #include <unistd.h>
 
-#ifdef __APPLE__
-    #include <mach/mach_vm.h>
-#endif
-
 /* Scheduler includes. */
 #include "FreeRTOS.h"
 #include "task.h"

From b5d1b972cc2483d4397bbc4f0046b07fc4c3b698 Mon Sep 17 00:00:00 2001
From: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Date: Tue, 21 Jan 2025 15:17:10 +0530
Subject: [PATCH 370/424] Update stream and message buffer documentation
 (#1226)

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 include/message_buffer.h | 60 ++++++++++++++++++++--------------------
 include/stream_buffer.h  | 48 ++++++++++++++++----------------
 2 files changed, 54 insertions(+), 54 deletions(-)

diff --git a/include/message_buffer.h b/include/message_buffer.h
index 975a7e343..9fb97ffd0 100644
--- a/include/message_buffer.h
+++ b/include/message_buffer.h
@@ -43,12 +43,12 @@
  * writer and reader to be different tasks or interrupts, but, unlike other
  * FreeRTOS objects, it is not safe to have multiple different writers or
  * multiple different readers.  If there are to be multiple different writers
- * then the application writer must place each call to a writing API function
- * (such as xMessageBufferSend()) inside a critical section and set the send
- * block time to 0.  Likewise, if there are to be multiple different readers
- * then the application writer must place each call to a reading API function
- * (such as xMessageBufferRead()) inside a critical section and set the receive
- * timeout to 0.
+ * then the application writer must serialize calls to writing API functions
+ * (such as xStreamBufferSend()).  Likewise, if there are to be multiple
+ * different readers then the application writer must serialize calls to reading
+ * API functions (such as xStreamBufferReceive()).  One way to achieve such
+ * serialization in single core or SMP kernel is to place each API call inside a
+ * critical section and use a block time of 0.
  *
  * Message buffers hold variable length messages.  To enable that, when a
  * message is written to the message buffer an additional sizeof( size_t ) bytes
@@ -306,12 +306,12 @@ typedef StreamBufferHandle_t MessageBufferHandle_t;
  * writer and reader to be different tasks or interrupts, but, unlike other
  * FreeRTOS objects, it is not safe to have multiple different writers or
  * multiple different readers.  If there are to be multiple different writers
- * then the application writer must place each call to a writing API function
- * (such as xMessageBufferSend()) inside a critical section and set the send
- * block time to 0.  Likewise, if there are to be multiple different readers
- * then the application writer must place each call to a reading API function
- * (such as xMessageBufferRead()) inside a critical section and set the receive
- * block time to 0.
+ * then the application writer must serialize calls to writing API functions
+ * (such as xStreamBufferSend()).  Likewise, if there are to be multiple
+ * different readers then the application writer must serialize calls to reading
+ * API functions (such as xStreamBufferReceive()).  One way to achieve such
+ * serialization in single core or SMP kernel is to place each API call inside a
+ * critical section and use a block time of 0.
  *
  * Use xMessageBufferSend() to write to a message buffer from a task.  Use
  * xMessageBufferSendFromISR() to write to a message buffer from an interrupt
@@ -409,12 +409,12 @@ typedef StreamBufferHandle_t MessageBufferHandle_t;
  * writer and reader to be different tasks or interrupts, but, unlike other
  * FreeRTOS objects, it is not safe to have multiple different writers or
  * multiple different readers.  If there are to be multiple different writers
- * then the application writer must place each call to a writing API function
- * (such as xMessageBufferSend()) inside a critical section and set the send
- * block time to 0.  Likewise, if there are to be multiple different readers
- * then the application writer must place each call to a reading API function
- * (such as xMessageBufferRead()) inside a critical section and set the receive
- * block time to 0.
+ * then the application writer must serialize calls to writing API functions
+ * (such as xStreamBufferSend()).  Likewise, if there are to be multiple
+ * different readers then the application writer must serialize calls to reading
+ * API functions (such as xStreamBufferReceive()).  One way to achieve such
+ * serialization in single core or SMP kernel is to place each API call inside a
+ * critical section and use a block time of 0.
  *
  * Use xMessageBufferSend() to write to a message buffer from a task.  Use
  * xMessageBufferSendFromISR() to write to a message buffer from an interrupt
@@ -516,12 +516,12 @@ typedef StreamBufferHandle_t MessageBufferHandle_t;
  * writer and reader to be different tasks or interrupts, but, unlike other
  * FreeRTOS objects, it is not safe to have multiple different writers or
  * multiple different readers.  If there are to be multiple different writers
- * then the application writer must place each call to a writing API function
- * (such as xMessageBufferSend()) inside a critical section and set the send
- * block time to 0.  Likewise, if there are to be multiple different readers
- * then the application writer must place each call to a reading API function
- * (such as xMessageBufferRead()) inside a critical section and set the receive
- * block time to 0.
+ * then the application writer must serialize calls to writing API functions
+ * (such as xStreamBufferSend()).  Likewise, if there are to be multiple
+ * different readers then the application writer must serialize calls to reading
+ * API functions (such as xStreamBufferReceive()).  One way to achieve such
+ * serialization in single core or SMP kernel is to place each API call inside a
+ * critical section and use a block time of 0.
  *
  * Use xMessageBufferReceive() to read from a message buffer from a task.  Use
  * xMessageBufferReceiveFromISR() to read from a message buffer from an
@@ -610,12 +610,12 @@ typedef StreamBufferHandle_t MessageBufferHandle_t;
  * writer and reader to be different tasks or interrupts, but, unlike other
  * FreeRTOS objects, it is not safe to have multiple different writers or
  * multiple different readers.  If there are to be multiple different writers
- * then the application writer must place each call to a writing API function
- * (such as xMessageBufferSend()) inside a critical section and set the send
- * block time to 0.  Likewise, if there are to be multiple different readers
- * then the application writer must place each call to a reading API function
- * (such as xMessageBufferRead()) inside a critical section and set the receive
- * block time to 0.
+ * then the application writer must serialize calls to writing API functions
+ * (such as xStreamBufferSend()).  Likewise, if there are to be multiple
+ * different readers then the application writer must serialize calls to reading
+ * API functions (such as xStreamBufferReceive()).  One way to achieve such
+ * serialization in single core or SMP kernel is to place each API call inside a
+ * critical section and use a block time of 0.
  *
  * Use xMessageBufferReceive() to read from a message buffer from a task.  Use
  * xMessageBufferReceiveFromISR() to read from a message buffer from an
diff --git a/include/stream_buffer.h b/include/stream_buffer.h
index 9b15c8aff..b0093fc80 100644
--- a/include/stream_buffer.h
+++ b/include/stream_buffer.h
@@ -40,12 +40,12 @@
  * writer and reader to be different tasks or interrupts, but, unlike other
  * FreeRTOS objects, it is not safe to have multiple different writers or
  * multiple different readers.  If there are to be multiple different writers
- * then the application writer must place each call to a writing API function
- * (such as xStreamBufferSend()) inside a critical section and set the send
- * block time to 0.  Likewise, if there are to be multiple different readers
- * then the application writer must place each call to a reading API function
- * (such as xStreamBufferReceive()) inside a critical section section and set the
- * receive block time to 0.
+ * then the application writer must serialize calls to writing API functions
+ * (such as xStreamBufferSend()).  Likewise, if there are to be multiple
+ * different readers then the application writer must serialize calls to reading
+ * API functions (such as xStreamBufferReceive()).  One way to achieve such
+ * serialization in single core or SMP kernel is to place each API call inside a
+ * critical section and use a block time of 0.
  *
  */
 
@@ -514,12 +514,12 @@ typedef void (* StreamBufferCallbackFunction_t)( StreamBufferHandle_t xStreamBuf
  * writer and reader to be different tasks or interrupts, but, unlike other
  * FreeRTOS objects, it is not safe to have multiple different writers or
  * multiple different readers.  If there are to be multiple different writers
- * then the application writer must place each call to a writing API function
- * (such as xStreamBufferSend()) inside a critical section and set the send
- * block time to 0.  Likewise, if there are to be multiple different readers
- * then the application writer must place each call to a reading API function
- * (such as xStreamBufferReceive()) inside a critical section and set the receive
- * block time to 0.
+ * then the application writer must serialize calls to writing API functions
+ * (such as xStreamBufferSend()).  Likewise, if there are to be multiple
+ * different readers then the application writer must serialize calls to reading
+ * API functions (such as xStreamBufferReceive()).  One way to achieve such
+ * serialization in single core or SMP kernel is to place each API call inside a
+ * critical section and use a block time of 0.
  *
  * Use xStreamBufferSend() to write to a stream buffer from a task.  Use
  * xStreamBufferSendFromISR() to write to a stream buffer from an interrupt
@@ -615,12 +615,12 @@ size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
  * writer and reader to be different tasks or interrupts, but, unlike other
  * FreeRTOS objects, it is not safe to have multiple different writers or
  * multiple different readers.  If there are to be multiple different writers
- * then the application writer must place each call to a writing API function
- * (such as xStreamBufferSend()) inside a critical section and set the send
- * block time to 0.  Likewise, if there are to be multiple different readers
- * then the application writer must place each call to a reading API function
- * (such as xStreamBufferReceive()) inside a critical section and set the receive
- * block time to 0.
+ * then the application writer must serialize calls to writing API functions
+ * (such as xStreamBufferSend()).  Likewise, if there are to be multiple
+ * different readers then the application writer must serialize calls to reading
+ * API functions (such as xStreamBufferReceive()).  One way to achieve such
+ * serialization in single core or SMP kernel is to place each API call inside a
+ * critical section and use a block time of 0.
  *
  * Use xStreamBufferSend() to write to a stream buffer from a task.  Use
  * xStreamBufferSendFromISR() to write to a stream buffer from an interrupt
@@ -718,12 +718,12 @@ size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
  * writer and reader to be different tasks or interrupts, but, unlike other
  * FreeRTOS objects, it is not safe to have multiple different writers or
  * multiple different readers.  If there are to be multiple different writers
- * then the application writer must place each call to a writing API function
- * (such as xStreamBufferSend()) inside a critical section and set the send
- * block time to 0.  Likewise, if there are to be multiple different readers
- * then the application writer must place each call to a reading API function
- * (such as xStreamBufferReceive()) inside a critical section and set the receive
- * block time to 0.
+ * then the application writer must serialize calls to writing API functions
+ * (such as xStreamBufferSend()).  Likewise, if there are to be multiple
+ * different readers then the application writer must serialize calls to reading
+ * API functions (such as xStreamBufferReceive()).  One way to achieve such
+ * serialization in single core or SMP kernel is to place each API call inside a
+ * critical section and use a block time of 0.
  *
  * Use xStreamBufferReceive() to read from a stream buffer from a task.  Use
  * xStreamBufferReceiveFromISR() to read from a stream buffer from an

From 1b8f5965d360953ebf5559c97418f5f5264bdbee Mon Sep 17 00:00:00 2001
From: kzorer <98871026+kzorer@users.noreply.github.com>
Date: Wed, 22 Jan 2025 12:23:35 +0300
Subject: [PATCH 371/424] Add xQueueCreateSetStatic method for static
 allocation of Queue Sets (#1228)

Add xQueueCreateSetStatic method for static allocation of Queue Sets

This commit introduces the xQueueCreateSetStatic function, which allows for the static allocation of Queue Sets in FreeRTOS when both configUSE_QUEUE_SETS and configSUPPORT_STATIC_ALLOCATION are enabled.
---
 include/FreeRTOS.h                |  8 ++++
 include/mpu_prototypes.h          |  6 +++
 include/mpu_wrappers.h            |  1 +
 include/queue.h                   | 74 ++++++++++++++++++++++++++++---
 portable/Common/mpu_wrappers.c    | 28 ++++++++++++
 portable/Common/mpu_wrappers_v2.c | 33 ++++++++++++++
 queue.c                           | 22 ++++++++-
 7 files changed, 164 insertions(+), 8 deletions(-)

diff --git a/include/FreeRTOS.h b/include/FreeRTOS.h
index dfccccb40..ce8530e7d 100644
--- a/include/FreeRTOS.h
+++ b/include/FreeRTOS.h
@@ -1484,6 +1484,14 @@
     #define traceRETURN_xQueueCreateSet( pxQueue )
 #endif
 
+#ifndef traceENTER_xQueueCreateSetStatic
+    #define traceENTER_xQueueCreateSetStatic( uxEventQueueLength )
+#endif
+
+#ifndef traceRETURN_xQueueCreateSetStatic
+    #define traceRETURN_xQueueCreateSetStatic( pxQueue )
+#endif
+
 #ifndef traceENTER_xQueueAddToSet
     #define traceENTER_xQueueAddToSet( xQueueOrSemaphore, xQueueSet )
 #endif
diff --git a/include/mpu_prototypes.h b/include/mpu_prototypes.h
index 1efd13440..9df2a5762 100644
--- a/include/mpu_prototypes.h
+++ b/include/mpu_prototypes.h
@@ -269,6 +269,9 @@ uint8_t MPU_ucQueueGetQueueType( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
                                                  StaticQueue_t * pxStaticQueue,
                                                  const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
     QueueSetHandle_t MPU_xQueueCreateSet( const UBaseType_t uxEventQueueLength ) FREERTOS_SYSTEM_CALL;
+    QueueSetHandle_t MPU_xQueueCreateSetStatic( const UBaseType_t uxEventQueueLength,
+                                                uint8_t * pucQueueStorage,
+                                                StaticQueue_t * pxStaticQueue ) FREERTOS_SYSTEM_CALL;
     BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore,
                                         QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL;
     BaseType_t MPU_xQueueGenericReset( QueueHandle_t xQueue,
@@ -294,6 +297,9 @@ uint8_t MPU_ucQueueGetQueueType( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
                                                  StaticQueue_t * pxStaticQueue,
                                                  const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
     QueueSetHandle_t MPU_xQueueCreateSet( const UBaseType_t uxEventQueueLength ) PRIVILEGED_FUNCTION;
+    QueueSetHandle_t MPU_xQueueCreateSetStatic( const UBaseType_t uxEventQueueLength,
+                                                uint8_t * pucQueueStorage,
+                                                StaticQueue_t * pxStaticQueue ) PRIVILEGED_FUNCTION;
     BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore,
                                         QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
     BaseType_t MPU_xQueueGenericReset( QueueHandle_t xQueue,
diff --git a/include/mpu_wrappers.h b/include/mpu_wrappers.h
index 4513ca996..3b4738e96 100644
--- a/include/mpu_wrappers.h
+++ b/include/mpu_wrappers.h
@@ -150,6 +150,7 @@
         #define xQueueGenericCreateStatic              MPU_xQueueGenericCreateStatic
         #define xQueueGenericReset                     MPU_xQueueGenericReset
         #define xQueueCreateSet                        MPU_xQueueCreateSet
+        #define xQueueCreateSetStatic                  MPU_xQueueCreateSetStatic
         #define xQueueRemoveFromSet                    MPU_xQueueRemoveFromSet
 
         #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
diff --git a/include/queue.h b/include/queue.h
index 963904bb3..56753d300 100644
--- a/include/queue.h
+++ b/include/queue.h
@@ -1638,12 +1638,12 @@ BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex ) PRIVILEGED_FUNCTION;
  * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
  * function.
  *
- * A queue set must be explicitly created using a call to xQueueCreateSet()
- * before it can be used.  Once created, standard FreeRTOS queues and semaphores
- * can be added to the set using calls to xQueueAddToSet().
- * xQueueSelectFromSet() is then used to determine which, if any, of the queues
- * or semaphores contained in the set is in a state where a queue read or
- * semaphore take operation would be successful.
+ * A queue set must be explicitly created using a call to xQueueCreateSet() or
+ * xQueueCreateSetStatic() before it can be used.  Once created, standard
+ * FreeRTOS queues and semaphores can be added to the set using calls to
+ * xQueueAddToSet().  xQueueSelectFromSet() is then used to determine which, if
+ * any, of the queues or semaphores contained in the set is in a state where a
+ * queue read or semaphore take operation would be successful.
  *
  * Note 1:  See the documentation on https://www.freertos.org/Documentation/02-Kernel/04-API-references/07-Queue-sets/00-RTOS-queue-sets
  * for reasons why queue sets are very rarely needed in practice as there are
@@ -1683,9 +1683,69 @@ BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex ) PRIVILEGED_FUNCTION;
     QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength ) PRIVILEGED_FUNCTION;
 #endif
 
+/*
+ * Queue sets provide a mechanism to allow a task to block (pend) on a read
+ * operation from multiple queues or semaphores simultaneously.
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * A queue set must be explicitly created using a call to xQueueCreateSet()
+ * or xQueueCreateSetStatic() before it can be used.  Once created, standard
+ * FreeRTOS queues and semaphores can be added to the set using calls to
+ * xQueueAddToSet().  xQueueSelectFromSet() is then used to determine which, if
+ * any, of the queues or semaphores contained in the set is in a state where a
+ * queue read or semaphore take operation would be successful.
+ *
+ * Note 1:  See the documentation on https://www.freertos.org/Documentation/02-Kernel/04-API-references/07-Queue-sets/00-RTOS-queue-sets
+ * for reasons why queue sets are very rarely needed in practice as there are
+ * simpler methods of blocking on multiple objects.
+ *
+ * Note 2:  Blocking on a queue set that contains a mutex will not cause the
+ * mutex holder to inherit the priority of the blocked task.
+ *
+ * Note 3:  An additional 4 bytes of RAM is required for each space in a every
+ * queue added to a queue set.  Therefore counting semaphores that have a high
+ * maximum count value should not be added to a queue set.
+ *
+ * Note 4:  A receive (in the case of a queue) or take (in the case of a
+ * semaphore) operation must not be performed on a member of a queue set unless
+ * a call to xQueueSelectFromSet() has first returned a handle to that set member.
+ *
+ * @param uxEventQueueLength Queue sets store events that occur on
+ * the queues and semaphores contained in the set.  uxEventQueueLength specifies
+ * the maximum number of events that can be queued at once.  To be absolutely
+ * certain that events are not lost uxEventQueueLength should be set to the
+ * total sum of the length of the queues added to the set, where binary
+ * semaphores and mutexes have a length of 1, and counting semaphores have a
+ * length set by their maximum count value.  Examples:
+ *  + If a queue set is to hold a queue of length 5, another queue of length 12,
+ *    and a binary semaphore, then uxEventQueueLength should be set to
+ *    (5 + 12 + 1), or 18.
+ *  + If a queue set is to hold three binary semaphores then uxEventQueueLength
+ *    should be set to (1 + 1 + 1 ), or 3.
+ *  + If a queue set is to hold a counting semaphore that has a maximum count of
+ *    5, and a counting semaphore that has a maximum count of 3, then
+ *    uxEventQueueLength should be set to (5 + 3), or 8.
+ *
+ * @param pucQueueStorage pucQueueStorage must point to a uint8_t array that is
+ * at least large enough to hold uxEventQueueLength events.
+ *
+ * @param pxQueueBuffer Must point to a variable of type StaticQueue_t, which
+ * will be used to hold the queue's data structure.
+ *
+ * @return If the queue set is created successfully then a handle to the created
+ * queue set is returned.  If pxQueueBuffer is NULL then NULL is returned.
+ */
+#if ( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+    QueueSetHandle_t xQueueCreateSetStatic( const UBaseType_t uxEventQueueLength,
+                                            uint8_t * pucQueueStorage,
+                                            StaticQueue_t * pxStaticQueue ) PRIVILEGED_FUNCTION;
+#endif
+
 /*
  * Adds a queue or semaphore to a queue set that was previously created by a
- * call to xQueueCreateSet().
+ * call to xQueueCreateSet() or xQueueCreateSetStatic().
  *
  * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
  * function.
diff --git a/portable/Common/mpu_wrappers.c b/portable/Common/mpu_wrappers.c
index 4c5731665..5bc4181e2 100644
--- a/portable/Common/mpu_wrappers.c
+++ b/portable/Common/mpu_wrappers.c
@@ -1524,6 +1524,34 @@
     #endif /* if ( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
 /*-----------------------------------------------------------*/
 
+    #if ( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+        QueueSetHandle_t MPU_xQueueCreateSetStatic( const UBaseType_t uxEventQueueLength,
+                                                    uint8_t * pucQueueStorage,
+                                                    StaticQueue_t * pxStaticQueue ) /* FREERTOS_SYSTEM_CALL */
+        {
+            QueueSetHandle_t xReturn;
+
+            if( portIS_PRIVILEGED() == pdFALSE )
+            {
+                portRAISE_PRIVILEGE();
+                portMEMORY_BARRIER();
+
+                xReturn = xQueueCreateSetStatic( uxEventQueueLength, pucQueueStorage, pxStaticQueue );
+                portMEMORY_BARRIER();
+
+                portRESET_PRIVILEGE();
+                portMEMORY_BARRIER();
+            }
+            else
+            {
+                xReturn = xQueueCreateSetStatic( uxEventQueueLength, pucQueueStorage, pxStaticQueue );
+            }
+
+            return xReturn;
+        }
+    #endif /* if ( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
     #if ( configUSE_QUEUE_SETS == 1 )
         QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
                                                         TickType_t xBlockTimeTicks ) /* FREERTOS_SYSTEM_CALL */
diff --git a/portable/Common/mpu_wrappers_v2.c b/portable/Common/mpu_wrappers_v2.c
index eb9e6f056..e92aca0f5 100644
--- a/portable/Common/mpu_wrappers_v2.c
+++ b/portable/Common/mpu_wrappers_v2.c
@@ -3016,6 +3016,39 @@
     #endif /* if ( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
 /*-----------------------------------------------------------*/
 
+    #if ( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+
+        QueueSetHandle_t MPU_xQueueCreateSetStatic( const UBaseType_t uxEventQueueLength,
+                                                    uint8_t * pucQueueStorage,
+                                                    StaticQueue_t * pxStaticQueue ) /* PRIVILEGED_FUNCTION */
+        {
+            QueueSetHandle_t xInternalQueueSetHandle = NULL;
+            QueueSetHandle_t xExternalQueueSetHandle = NULL;
+            int32_t lIndex;
+
+            lIndex = MPU_GetFreeIndexInKernelObjectPool();
+
+            if( lIndex != -1 )
+            {
+                xInternalQueueSetHandle = xQueueCreateSetStatic( uxEventQueueLength, pucQueueStorage, pxStaticQueue );
+
+                if( xInternalQueueSetHandle != NULL )
+                {
+                    MPU_StoreQueueSetHandleAtIndex( lIndex, xInternalQueueSetHandle );
+                    xExternalQueueSetHandle = ( QueueSetHandle_t ) CONVERT_TO_EXTERNAL_INDEX( lIndex );
+                }
+                else
+                {
+                    MPU_SetIndexFreeInKernelObjectPool( lIndex );
+                }
+            }
+
+            return xExternalQueueSetHandle;
+        }
+
+    #endif /* if ( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
     #if ( configUSE_QUEUE_SETS == 1 )
 
         BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore,
diff --git a/queue.c b/queue.c
index 4759b439b..688fb3113 100644
--- a/queue.c
+++ b/queue.c
@@ -3186,7 +3186,27 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )
         return pxQueue;
     }
 
-#endif /* configUSE_QUEUE_SETS */
+#endif /* #if ( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+
+    QueueSetHandle_t xQueueCreateSetStatic( const UBaseType_t uxEventQueueLength,
+                                            uint8_t * pucQueueStorage,
+                                            StaticQueue_t * pxStaticQueue )
+    {
+        QueueSetHandle_t pxQueue;
+
+        traceENTER_xQueueCreateSetStatic( uxEventQueueLength );
+
+        pxQueue = xQueueGenericCreateStatic( uxEventQueueLength, ( UBaseType_t ) sizeof( Queue_t * ), pucQueueStorage, pxStaticQueue, queueQUEUE_TYPE_SET );
+
+        traceRETURN_xQueueCreateSetStatic( pxQueue );
+
+        return pxQueue;
+    }
+
+#endif /* #if ( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) */
 /*-----------------------------------------------------------*/
 
 #if ( configUSE_QUEUE_SETS == 1 )

From ff0989e46b15dca255b57cecaff22795bff9df85 Mon Sep 17 00:00:00 2001
From: Marouen Ghodhbane <marouen.ghodhbane@nxp.com>
Date: Wed, 9 Oct 2024 17:31:45 +0200
Subject: [PATCH 372/424] portable: aarch64_sre: add configUSE_TASK_FPU_SUPPORT
 support

This is a direct backport of upstream commit [1] for aarch64 (legacy operation port)
done under [2]
The same code can be applied on the aarch SRE port to be able to enable FPU context
saving on all tasks context switch to mitigate GCC optimization to use SIMD registers
for copy.

[1] "55eceb22: Add configUSE_TASK_FPU_SUPPORT to AARCH64 port (#1048)"
[2] https://github.com/FreeRTOS/FreeRTOS-Kernel/pull/1048

Signed-off-by: Marouen Ghodhbane <marouen.ghodhbane@nxp.com>
---
 portable/GCC/ARM_AARCH64_SRE/port.c      | 54 +++++++++++++++++++-----
 portable/GCC/ARM_AARCH64_SRE/portmacro.h | 15 +++++--
 2 files changed, 55 insertions(+), 14 deletions(-)

diff --git a/portable/GCC/ARM_AARCH64_SRE/port.c b/portable/GCC/ARM_AARCH64_SRE/port.c
index 1c96c0efd..8cebcaf54 100644
--- a/portable/GCC/ARM_AARCH64_SRE/port.c
+++ b/portable/GCC/ARM_AARCH64_SRE/port.c
@@ -121,6 +121,10 @@
                          ::"r" ( portUNMASK_VALUE ) ); \
     }
 
+/* The space on the stack required to hold the FPU registers.
+ * There are 32 128-bit registers.*/
+#define portFPU_REGISTER_WORDS     ( 32 * 2 )
+
 /*-----------------------------------------------------------*/
 
 /*
@@ -229,23 +233,47 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
     *pxTopOfStack = ( StackType_t ) 0x00;         /* XZR - has no effect, used so there are an even number of registers. */
     pxTopOfStack--;
     *pxTopOfStack = ( StackType_t ) 0x00;         /* R30 - procedure call link register. */
-    pxTopOfStack--;
 
+    pxTopOfStack--;
     *pxTopOfStack = portINITIAL_PSTATE;
-    pxTopOfStack--;
 
+    pxTopOfStack--;
     *pxTopOfStack = ( StackType_t ) pxCode; /* Exception return address. */
-    pxTopOfStack--;
 
-    /* The task will start with a critical nesting count of 0 as interrupts are
-     * enabled. */
-    *pxTopOfStack = portNO_CRITICAL_NESTING;
-    pxTopOfStack--;
+    #if ( configUSE_TASK_FPU_SUPPORT == 1 )
+    {
+        /* The task will start with a critical nesting count of 0 as interrupts are
+        * enabled. */
+        pxTopOfStack--;
+        *pxTopOfStack = portNO_CRITICAL_NESTING;
 
-    /* The task will start without a floating point context.  A task that uses
-     * the floating point hardware must call vPortTaskUsesFPU() before executing
-     * any floating point instructions. */
-    *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
+        /* The task will start without a floating point context.  A task that
+        * uses the floating point hardware must call vPortTaskUsesFPU() before
+        * executing any floating point instructions. */
+        pxTopOfStack--;
+        *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
+    }
+    #elif ( configUSE_TASK_FPU_SUPPORT == 2 )
+    {
+        /* The task will start with a floating point context.  Leave enough
+        * space for the registers - and ensure they are initialised to 0. */
+        pxTopOfStack -= portFPU_REGISTER_WORDS;
+        memset( pxTopOfStack, 0x00, portFPU_REGISTER_WORDS * sizeof( StackType_t ) );
+
+        /* The task will start with a critical nesting count of 0 as interrupts are
+        * enabled. */
+        pxTopOfStack--;
+        *pxTopOfStack = portNO_CRITICAL_NESTING;
+
+        pxTopOfStack--;
+        *pxTopOfStack = pdTRUE;
+        ullPortTaskHasFPUContext = pdTRUE;
+    }
+    #else /* if ( configUSE_TASK_FPU_SUPPORT == 1 ) */
+    {
+        #error "Invalid configUSE_TASK_FPU_SUPPORT setting - configUSE_TASK_FPU_SUPPORT must be set to 1, 2, or left undefined."
+    }
+    #endif /* if ( configUSE_TASK_FPU_SUPPORT == 1 ) */
 
     return pxTopOfStack;
 }
@@ -384,6 +412,8 @@ void FreeRTOS_Tick_Handler( void )
 }
 /*-----------------------------------------------------------*/
 
+#if ( configUSE_TASK_FPU_SUPPORT != 2 )
+
 void vPortTaskUsesFPU( void )
 {
     /* A task is registering the fact that it needs an FPU context.  Set the
@@ -393,6 +423,8 @@ void vPortTaskUsesFPU( void )
     /* Consider initialising the FPSR here - but probably not necessary in
      * AArch64. */
 }
+
+#endif /* configUSE_TASK_FPU_SUPPORT */
 /*-----------------------------------------------------------*/
 
 void vPortClearInterruptMask( UBaseType_t uxNewMaskValue )
diff --git a/portable/GCC/ARM_AARCH64_SRE/portmacro.h b/portable/GCC/ARM_AARCH64_SRE/portmacro.h
index 296984d5b..5810741d2 100644
--- a/portable/GCC/ARM_AARCH64_SRE/portmacro.h
+++ b/portable/GCC/ARM_AARCH64_SRE/portmacro.h
@@ -135,9 +135,18 @@ extern void vPortInstallFreeRTOSVectorTable( void );
  * handler for whichever peripheral is used to generate the RTOS tick. */
 void FreeRTOS_Tick_Handler( void );
 
-/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
- * before any floating point instructions are executed. */
-void vPortTaskUsesFPU( void );
+/* If configUSE_TASK_FPU_SUPPORT is set to 1 (or left undefined) then tasks are
+ * created without an FPU context and must call vPortTaskUsesFPU() to give
+ * themselves an FPU context before using any FPU instructions.  If
+ * configUSE_TASK_FPU_SUPPORT is set to 2 then all tasks will have an FPU context
+ * by default. */
+#if ( configUSE_TASK_FPU_SUPPORT != 2 )
+    void vPortTaskUsesFPU( void );
+#else
+    /* Each task has an FPU context already, so define this function away to
+    * nothing to prevent it from being called accidentally. */
+    #define vPortTaskUsesFPU()
+#endif
 #define portTASK_USES_FLOATING_POINT()    vPortTaskUsesFPU()
 
 #define portLOWEST_INTERRUPT_PRIORITY           ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )

From 630cfb5b79dee06faaeedf2b69893b68a97c4c70 Mon Sep 17 00:00:00 2001
From: Marouen Ghodhbane <marouen.ghodhbane@nxp.com>
Date: Wed, 9 Oct 2024 18:34:55 +0200
Subject: [PATCH 373/424] portable: aarch64_sre: add the configuration and
 status registers to the fpu saved context

FPSR and FPCR are two 64-bits registers where only the lower 32 bits are defined.
Save them when doing context switch with FPU context saving enabled.

Signed-off-by: Marouen Ghodhbane <marouen.ghodhbane@nxp.com>
---
 portable/GCC/ARM_AARCH64_SRE/port.c    |  4 ++--
 portable/GCC/ARM_AARCH64_SRE/portASM.S | 10 +++++++++-
 2 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/portable/GCC/ARM_AARCH64_SRE/port.c b/portable/GCC/ARM_AARCH64_SRE/port.c
index 8cebcaf54..ffc34d746 100644
--- a/portable/GCC/ARM_AARCH64_SRE/port.c
+++ b/portable/GCC/ARM_AARCH64_SRE/port.c
@@ -122,8 +122,8 @@
     }
 
 /* The space on the stack required to hold the FPU registers.
- * There are 32 128-bit registers.*/
-#define portFPU_REGISTER_WORDS     ( 32 * 2 )
+ * There are 32 128-bit plus 2 64-bit status registers.*/
+#define portFPU_REGISTER_WORDS     ( (32 * 2) + 2 )
 
 /*-----------------------------------------------------------*/
 
diff --git a/portable/GCC/ARM_AARCH64_SRE/portASM.S b/portable/GCC/ARM_AARCH64_SRE/portASM.S
index ed3c031d0..8d69b2aa1 100644
--- a/portable/GCC/ARM_AARCH64_SRE/portASM.S
+++ b/portable/GCC/ARM_AARCH64_SRE/portASM.S
@@ -87,7 +87,7 @@
     LDR     X0, ullPortTaskHasFPUContextConst
     LDR     X2, [X0]
 
-    /* Save the FPU context, if any (32 128-bit registers). */
+    /* Save the FPU context, if any (32 128-bit plus two 64-bit status registers). */
     CMP     X2, #0
     B.EQ    1f
     STP     Q0, Q1, [SP,#-0x20]!
@@ -107,6 +107,11 @@
     STP     Q28, Q29, [SP,#-0x20]!
     STP     Q30, Q31, [SP,#-0x20]!
 
+    /* Even though upper 32 bits of FPSR and FPCR are reserved, save and restore the whole 64 bits to keep 16-byte SP alignement. */
+    MRS     X9, FPSR
+    MRS     X10, FPCR
+    STP     X9, X10, [SP, #-0x10]!
+
 1:
     /* Store the critical nesting count and FPU context indicator. */
     STP     X2, X3, [SP, #-0x10]!
@@ -157,6 +162,7 @@
     /* Restore the FPU context, if any. */
     CMP     X2, #0
     B.EQ    1f
+    LDP     X9, X10, [SP], #0x10
     LDP     Q30, Q31, [SP], #0x20
     LDP     Q28, Q29, [SP], #0x20
     LDP     Q26, Q27, [SP], #0x20
@@ -173,6 +179,8 @@
     LDP     Q4, Q5, [SP], #0x20
     LDP     Q2, Q3, [SP], #0x20
     LDP     Q0, Q1, [SP], #0x20
+    MSR     FPSR, X9
+    MSR     FPCR, X10
 1:
     LDP     X2, X3, [SP], #0x10  /* SPSR and ELR. */
 

From 72bb476bf3d20c65d054557884f624fde9eec704 Mon Sep 17 00:00:00 2001
From: Marouen Ghodhbane <marouen.ghodhbane@nxp.com>
Date: Fri, 11 Oct 2024 15:36:42 +0200
Subject: [PATCH 374/424] portable: aarch64_sre: Add support for
 vApplicationFPUSafeIRQHandler

The application writer needs to name their IRQ handler as:
1. vApplicationIRQHandler if the IRQ handler does not use FPU registers.
2. vApplicationFPUSafeIRQHandler is the IRQ handler uses FPU registers.

When the application uses vApplicationFPUSafeIRQHandler, a default
implementation of vApplicationIRQHandler is used which stores FPU
registers and then calls vApplicationFPUSafeIRQHandler.

Note that recent versions of GCC may use FP/SIMD registers to optimize 16-bytes
copy and especially when using va_start()/va_arg() functions (e.g printing some thing
in IRQ handlers may trigger usage of FPU registers)

This implementation is heavily inspired by both the ARM_CA9 port and the ARM_CRx_No_GIC
port done in [1]

[1] https://github.com/FreeRTOS/FreeRTOS-Kernel/pull/1113

Signed-off-by: Marouen Ghodhbane <marouen.ghodhbane@nxp.com>
---
 portable/GCC/ARM_AARCH64_SRE/port.c    | 27 ++++++++++
 portable/GCC/ARM_AARCH64_SRE/portASM.S | 74 ++++++++++++++++++++++++++
 2 files changed, 101 insertions(+)

diff --git a/portable/GCC/ARM_AARCH64_SRE/port.c b/portable/GCC/ARM_AARCH64_SRE/port.c
index ffc34d746..ab9290d43 100644
--- a/portable/GCC/ARM_AARCH64_SRE/port.c
+++ b/portable/GCC/ARM_AARCH64_SRE/port.c
@@ -133,6 +133,27 @@
  */
 extern void vPortRestoreTaskContext( void );
 
+/*
+ * If the application provides an implementation of vApplicationIRQHandler(),
+ * then it will get called directly without saving the FPU registers on
+ * interrupt entry, and this weak implementation of
+ * vApplicationFPUSafeIRQHandler() is just provided to remove linkage errors -
+ * it should never actually get called so its implementation contains a
+ * call to configASSERT() that will always fail.
+ *
+ * If the application provides its own implementation of
+ * vApplicationFPUSafeIRQHandler() then the implementation of
+ * vApplicationIRQHandler() provided in portASM.S will save the FPU registers
+ * before calling it.
+ *
+ * Therefore, if the application writer wants FPU registers to be saved on
+ * interrupt entry their IRQ handler must be called
+ * vApplicationFPUSafeIRQHandler(), and if the application writer does not want
+ * FPU registers to be saved on interrupt entry their IRQ handler must be
+ * called vApplicationIRQHandler().
+ */
+void vApplicationFPUSafeIRQHandler( uint32_t ulICCIAR ) __attribute__((weak) );
+
 /*-----------------------------------------------------------*/
 
 /* A variable is used to keep track of the critical section nesting.  This
@@ -495,3 +516,9 @@ UBaseType_t uxPortSetInterruptMask( void )
 
 #endif /* configASSERT_DEFINED */
 /*-----------------------------------------------------------*/
+
+void vApplicationFPUSafeIRQHandler( uint32_t ulICCIAR )
+{
+    ( void ) ulICCIAR;
+    configASSERT( ( volatile void * ) NULL );
+}
diff --git a/portable/GCC/ARM_AARCH64_SRE/portASM.S b/portable/GCC/ARM_AARCH64_SRE/portASM.S
index 8d69b2aa1..f1f59cd33 100644
--- a/portable/GCC/ARM_AARCH64_SRE/portASM.S
+++ b/portable/GCC/ARM_AARCH64_SRE/portASM.S
@@ -414,8 +414,82 @@ Exit_IRQ_No_Context_Switch:
 
     ERET
 
+/******************************************************************************
+ * If the application provides an implementation of vApplicationIRQHandler(),
+ * then it will get called directly without saving the FPU registers on
+ * interrupt entry, and this weak implementation of
+ * vApplicationIRQHandler() will not get called.
+ *
+ * If the application provides its own implementation of
+ * vApplicationFPUSafeIRQHandler() then this implementation of
+ * vApplicationIRQHandler() will be called, save the FPU registers, and then
+ * call vApplicationFPUSafeIRQHandler().
+ *
+ * Therefore, if the application writer wants FPU registers to be saved on
+ * interrupt entry their IRQ handler must be called
+ * vApplicationFPUSafeIRQHandler(), and if the application writer does not want
+ * FPU registers to be saved on interrupt entry their IRQ handler must be
+ * called vApplicationIRQHandler().
+ *****************************************************************************/
 
+.align 8
+.weak vApplicationIRQHandler
+.type vApplicationIRQHandler, %function
+vApplicationIRQHandler:
+    /* Save LR and FP on the stack */
+    STP     X29, X30, [SP, #-0x10]!
 
+    /* Save FPU registers (32 128-bits + 2 64-bits configuration and status registers) */
+    STP     Q0, Q1, [SP,#-0x20]!
+    STP     Q2, Q3, [SP,#-0x20]!
+    STP     Q4, Q5, [SP,#-0x20]!
+    STP     Q6, Q7, [SP,#-0x20]!
+    STP     Q8, Q9, [SP,#-0x20]!
+    STP     Q10, Q11, [SP,#-0x20]!
+    STP     Q12, Q13, [SP,#-0x20]!
+    STP     Q14, Q15, [SP,#-0x20]!
+    STP     Q16, Q17, [SP,#-0x20]!
+    STP     Q18, Q19, [SP,#-0x20]!
+    STP     Q20, Q21, [SP,#-0x20]!
+    STP     Q22, Q23, [SP,#-0x20]!
+    STP     Q24, Q25, [SP,#-0x20]!
+    STP     Q26, Q27, [SP,#-0x20]!
+    STP     Q28, Q29, [SP,#-0x20]!
+    STP     Q30, Q31, [SP,#-0x20]!
+
+    /* Even though upper 32 bits of FPSR and FPCR are reserved, save and restore the whole 64 bits to keep 16-byte SP alignement. */
+    MRS     X9, FPSR
+    MRS     X10, FPCR
+    STP     X9, X10, [SP, #-0x10]!
+
+    /* Call the C handler. */
+    BL vApplicationFPUSafeIRQHandler
+
+    /* Restore FPU registers */
+
+    LDP     X9, X10, [SP], #0x10
+    LDP     Q30, Q31, [SP], #0x20
+    LDP     Q28, Q29, [SP], #0x20
+    LDP     Q26, Q27, [SP], #0x20
+    LDP     Q24, Q25, [SP], #0x20
+    LDP     Q22, Q23, [SP], #0x20
+    LDP     Q20, Q21, [SP], #0x20
+    LDP     Q18, Q19, [SP], #0x20
+    LDP     Q16, Q17, [SP], #0x20
+    LDP     Q14, Q15, [SP], #0x20
+    LDP     Q12, Q13, [SP], #0x20
+    LDP     Q10, Q11, [SP], #0x20
+    LDP     Q8, Q9, [SP], #0x20
+    LDP     Q6, Q7, [SP], #0x20
+    LDP     Q4, Q5, [SP], #0x20
+    LDP     Q2, Q3, [SP], #0x20
+    LDP     Q0, Q1, [SP], #0x20
+    MSR     FPSR, X9
+    MSR     FPCR, X10
+
+    /* Restore FP and LR */
+    LDP     X29, X30, [SP], #0x10
+    RET
 
 .align 8
 pxCurrentTCBConst: .dword pxCurrentTCB

From 2b35979a1a3225750089d64dc964e5f19b00ce6d Mon Sep 17 00:00:00 2001
From: John Boiles <johnaboiles@gmail.com>
Date: Fri, 24 Jan 2025 16:56:59 -0800
Subject: [PATCH 375/424] POSIX Simulator: Handle `pthread`s not created by
 FreeRTOS differently (#1223)

---
 portable/ThirdParty/GCC/Posix/port.c | 102 +++++++++++++++++++++------
 1 file changed, 82 insertions(+), 20 deletions(-)

diff --git a/portable/ThirdParty/GCC/Posix/port.c b/portable/ThirdParty/GCC/Posix/port.c
index 7cc32128f..c4eacb2ba 100644
--- a/portable/ThirdParty/GCC/Posix/port.c
+++ b/portable/ThirdParty/GCC/Posix/port.c
@@ -105,6 +105,8 @@ static BaseType_t xSchedulerEnd = pdFALSE;
 static pthread_t hTimerTickThread;
 static bool xTimerTickThreadShouldRun;
 static uint64_t prvStartTimeNs;
+static pthread_mutex_t xThreadMutex = PTHREAD_MUTEX_INITIALIZER;
+static pthread_key_t xThreadKey = 0;
 /*-----------------------------------------------------------*/
 
 static void prvSetupSignalsAndSchedulerPolicy( void );
@@ -119,6 +121,45 @@ static void vPortStartFirstTask( void );
 static void prvPortYieldFromISR( void );
 /*-----------------------------------------------------------*/
 
+void prvThreadKeyDestructor( void * data )
+{
+    free( data );
+}
+
+static void prvInitThreadKey()
+{
+    pthread_mutex_lock( &xThreadMutex );
+
+    if( xThreadKey == 0 )
+    {
+        pthread_key_create( &xThreadKey, prvThreadKeyDestructor );
+    }
+
+    pthread_mutex_unlock( &xThreadMutex );
+}
+
+static void prvMarkAsFreeRTOSThread( pthread_t thread )
+{
+    prvInitThreadKey();
+    uint8_t * thread_data = malloc( 1 );
+    configASSERT( thread_data != NULL );
+    *thread_data = 1;
+    pthread_setspecific( xThreadKey, thread_data );
+}
+
+static BaseType_t prvIsFreeRTOSThread( pthread_t thread )
+{
+    uint8_t * thread_data = ( uint8_t * ) pthread_getspecific( xThreadKey );
+
+    return thread_data != NULL && *thread_data == 1;
+}
+
+static void prvDestroyThreadKey()
+{
+    pthread_key_delete( xThreadKey );
+}
+/*-----------------------------------------------------------*/
+
 static void prvFatalError( const char * pcCall,
                            int iErrno ) __attribute__( ( __noreturn__ ) );
 
@@ -249,6 +290,8 @@ BaseType_t xPortStartScheduler( void )
     /* Restore original signal mask. */
     ( void ) pthread_sigmask( SIG_SETMASK, &xSchedulerOriginalSignalMask, NULL );
 
+    prvDestroyThreadKey();
+
     return 0;
 }
 /*-----------------------------------------------------------*/
@@ -266,8 +309,12 @@ void vPortEndScheduler( void )
     ( void ) pthread_kill( hMainThread, SIG_RESUME );
 
     /* Waiting to be deleted here. */
-    pxCurrentThread = prvGetThreadFromTask( xTaskGetCurrentTaskHandle() );
-    event_wait( pxCurrentThread->ev );
+    if( prvIsFreeRTOSThread( pthread_self() ) == pdTRUE )
+    {
+        pxCurrentThread = prvGetThreadFromTask( xTaskGetCurrentTaskHandle() );
+        event_wait( pxCurrentThread->ev );
+    }
+
     pthread_testcancel();
 }
 /*-----------------------------------------------------------*/
@@ -322,13 +369,19 @@ void vPortYield( void )
 
 void vPortDisableInterrupts( void )
 {
-    pthread_sigmask( SIG_BLOCK, &xAllSignals, NULL );
+    if( prvIsFreeRTOSThread( pthread_self() ) == pdTRUE )
+    {
+        pthread_sigmask(SIG_BLOCK, &xAllSignals, NULL);
+    }
 }
 /*-----------------------------------------------------------*/
 
 void vPortEnableInterrupts( void )
 {
-    pthread_sigmask( SIG_UNBLOCK, &xAllSignals, NULL );
+    if( prvIsFreeRTOSThread( pthread_self() ) == pdTRUE )
+    {
+        pthread_sigmask(SIG_UNBLOCK, &xAllSignals, NULL);
+    }
 }
 /*-----------------------------------------------------------*/
 
@@ -364,6 +417,8 @@ static void * prvTimerTickHandler( void * arg )
 {
     ( void ) arg;
 
+    prvMarkAsFreeRTOSThread( pthread_self() );
+
     prvPortSetCurrentThreadName("Scheduler timer");
 
     while( xTimerTickThreadShouldRun )
@@ -396,26 +451,31 @@ void prvSetupTimerInterrupt( void )
 
 static void vPortSystemTickHandler( int sig )
 {
-    Thread_t * pxThreadToSuspend;
-    Thread_t * pxThreadToResume;
-
-    ( void ) sig;
-
-    uxCriticalNesting++; /* Signals are blocked in this signal handler. */
-
-    pxThreadToSuspend = prvGetThreadFromTask( xTaskGetCurrentTaskHandle() );
-
-    if( xTaskIncrementTick() != pdFALSE )
+    if( prvIsFreeRTOSThread( pthread_self() ) == pdTRUE )
     {
-        /* Select Next Task. */
-        vTaskSwitchContext();
+        Thread_t * pxThreadToSuspend;
+        Thread_t * pxThreadToResume;
 
-        pxThreadToResume = prvGetThreadFromTask( xTaskGetCurrentTaskHandle() );
+        ( void ) sig;
 
-        prvSwitchThread( pxThreadToResume, pxThreadToSuspend );
+        uxCriticalNesting++; /* Signals are blocked in this signal handler. */
+
+        pxThreadToSuspend = prvGetThreadFromTask( xTaskGetCurrentTaskHandle() );
+
+        if( xTaskIncrementTick() != pdFALSE )
+        {
+            /* Select Next Task. */
+            vTaskSwitchContext();
+
+            pxThreadToResume = prvGetThreadFromTask( xTaskGetCurrentTaskHandle() );
+
+            prvSwitchThread( pxThreadToResume, pxThreadToSuspend );
+        }
+
+        uxCriticalNesting--;
+    } else {
+        fprintf( stderr, "vPortSystemTickHandler called from non-FreeRTOS thread\n" );
     }
-
-    uxCriticalNesting--;
 }
 /*-----------------------------------------------------------*/
 
@@ -448,6 +508,8 @@ static void * prvWaitForStart( void * pvParams )
 {
     Thread_t * pxThread = pvParams;
 
+    prvMarkAsFreeRTOSThread( pthread_self() );
+
     prvSuspendSelf( pxThread );
 
     /* Resumed for the first time, unblocks all signals. */

From 11d0caa61487eacff89044efed4e19579b9e0a5e Mon Sep 17 00:00:00 2001
From: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Date: Sat, 25 Jan 2025 13:34:03 +0530
Subject: [PATCH 376/424] Fix the context array size for MPU ports (#1230)

Fix the context array size for MPU ports

Ensure the saved context location falls within the reserved context area
rather than overlapping with the next MPU_SETTINGS structure member.

This never caused a problem because actual read/write operations
start from one word before the saved context location.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 .github/workflows/kernel-demos.yml               |  4 ++--
 portable/ARMv8M/non_secure/portmacrocommon.h     | 16 ++++++++--------
 .../GCC/ARM_CM23/non_secure/portmacrocommon.h    | 16 ++++++++--------
 .../ARM_CM23_NTZ/non_secure/portmacrocommon.h    | 16 ++++++++--------
 .../GCC/ARM_CM33/non_secure/portmacrocommon.h    | 16 ++++++++--------
 .../ARM_CM33_NTZ/non_secure/portmacrocommon.h    | 16 ++++++++--------
 .../GCC/ARM_CM35P/non_secure/portmacrocommon.h   | 16 ++++++++--------
 .../ARM_CM35P_NTZ/non_secure/portmacrocommon.h   | 16 ++++++++--------
 portable/GCC/ARM_CM3_MPU/portmacro.h             |  8 ++++++++
 portable/GCC/ARM_CM4_MPU/portmacro.h             | 11 ++++++++++-
 .../GCC/ARM_CM55/non_secure/portmacrocommon.h    | 16 ++++++++--------
 .../ARM_CM55_NTZ/non_secure/portmacrocommon.h    | 16 ++++++++--------
 .../GCC/ARM_CM85/non_secure/portmacrocommon.h    | 16 ++++++++--------
 .../ARM_CM85_NTZ/non_secure/portmacrocommon.h    | 16 ++++++++--------
 .../IAR/ARM_CM23/non_secure/portmacrocommon.h    | 16 ++++++++--------
 .../ARM_CM23_NTZ/non_secure/portmacrocommon.h    | 16 ++++++++--------
 .../IAR/ARM_CM33/non_secure/portmacrocommon.h    | 16 ++++++++--------
 .../ARM_CM33_NTZ/non_secure/portmacrocommon.h    | 16 ++++++++--------
 .../IAR/ARM_CM35P/non_secure/portmacrocommon.h   | 16 ++++++++--------
 .../ARM_CM35P_NTZ/non_secure/portmacrocommon.h   | 16 ++++++++--------
 portable/IAR/ARM_CM4F_MPU/portmacro.h            | 11 ++++++++++-
 .../IAR/ARM_CM55/non_secure/portmacrocommon.h    | 16 ++++++++--------
 .../ARM_CM55_NTZ/non_secure/portmacrocommon.h    | 16 ++++++++--------
 .../IAR/ARM_CM85/non_secure/portmacrocommon.h    | 16 ++++++++--------
 .../ARM_CM85_NTZ/non_secure/portmacrocommon.h    | 16 ++++++++--------
 portable/RVDS/ARM_CM4_MPU/portmacro.h            | 11 ++++++++++-
 26 files changed, 208 insertions(+), 173 deletions(-)

diff --git a/.github/workflows/kernel-demos.yml b/.github/workflows/kernel-demos.yml
index f81ae33f3..404c602b5 100644
--- a/.github/workflows/kernel-demos.yml
+++ b/.github/workflows/kernel-demos.yml
@@ -268,12 +268,12 @@ jobs:
           fetch-depth: 1
 
       - env:
-          stepName: Fetch Community-Supported-Demos Submodule
+          stepName: Fetch Dependencies
         shell: bash
         run: |
           # ${{ env.stepName }}
           echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}"
-          git submodule update --checkout --init --depth 1 FreeRTOS/Demo/ThirdParty/Community-Supported-Demos
+          git submodule update --checkout --init --depth 1 FreeRTOS/Demo/ThirdParty/Community-Supported-Demos FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace
           echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }}"
 
       # Checkout user pull request changes
diff --git a/portable/ARMv8M/non_secure/portmacrocommon.h b/portable/ARMv8M/non_secure/portmacrocommon.h
index e74fa8257..ec14d467d 100644
--- a/portable/ARMv8M/non_secure/portmacrocommon.h
+++ b/portable/ARMv8M/non_secure/portmacrocommon.h
@@ -251,9 +251,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
              *
              * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
-             *      16             16            8               8                     5                     16         1
+             *      16             17            8               8                     5                     16         1
              */
-            #define MAX_CONTEXT_SIZE    70
+            #define MAX_CONTEXT_SIZE    71
 
         #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
 
@@ -264,9 +264,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+------------------------------+-----+
              *
              * <-----------><--------------><---------><----------------><-----------------------------><---->
-             *      16             16            8               8                     5                   1
+             *      16             17            8               8                     5                   1
              */
-            #define MAX_CONTEXT_SIZE    54
+            #define MAX_CONTEXT_SIZE    55
 
         #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
 
@@ -277,9 +277,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
              *
              * <-----------><--------------><---------><----------------><---------------------><-----------><---->
-             *      16             16            8               8                  4                16         1
+             *      16             17            8               8                  4                16         1
              */
-            #define MAX_CONTEXT_SIZE    69
+            #define MAX_CONTEXT_SIZE    70
 
         #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
@@ -290,9 +290,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+----------------------+-----+
              *
              * <-----------><--------------><---------><----------------><---------------------><---->
-             *      16             16            8               8                  4              1
+             *      16             17            8               8                  4              1
              */
-            #define MAX_CONTEXT_SIZE    53
+            #define MAX_CONTEXT_SIZE    54
 
         #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
diff --git a/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h
index e74fa8257..ec14d467d 100644
--- a/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h
@@ -251,9 +251,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
              *
              * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
-             *      16             16            8               8                     5                     16         1
+             *      16             17            8               8                     5                     16         1
              */
-            #define MAX_CONTEXT_SIZE    70
+            #define MAX_CONTEXT_SIZE    71
 
         #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
 
@@ -264,9 +264,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+------------------------------+-----+
              *
              * <-----------><--------------><---------><----------------><-----------------------------><---->
-             *      16             16            8               8                     5                   1
+             *      16             17            8               8                     5                   1
              */
-            #define MAX_CONTEXT_SIZE    54
+            #define MAX_CONTEXT_SIZE    55
 
         #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
 
@@ -277,9 +277,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
              *
              * <-----------><--------------><---------><----------------><---------------------><-----------><---->
-             *      16             16            8               8                  4                16         1
+             *      16             17            8               8                  4                16         1
              */
-            #define MAX_CONTEXT_SIZE    69
+            #define MAX_CONTEXT_SIZE    70
 
         #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
@@ -290,9 +290,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+----------------------+-----+
              *
              * <-----------><--------------><---------><----------------><---------------------><---->
-             *      16             16            8               8                  4              1
+             *      16             17            8               8                  4              1
              */
-            #define MAX_CONTEXT_SIZE    53
+            #define MAX_CONTEXT_SIZE    54
 
         #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h
index e74fa8257..ec14d467d 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h
@@ -251,9 +251,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
              *
              * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
-             *      16             16            8               8                     5                     16         1
+             *      16             17            8               8                     5                     16         1
              */
-            #define MAX_CONTEXT_SIZE    70
+            #define MAX_CONTEXT_SIZE    71
 
         #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
 
@@ -264,9 +264,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+------------------------------+-----+
              *
              * <-----------><--------------><---------><----------------><-----------------------------><---->
-             *      16             16            8               8                     5                   1
+             *      16             17            8               8                     5                   1
              */
-            #define MAX_CONTEXT_SIZE    54
+            #define MAX_CONTEXT_SIZE    55
 
         #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
 
@@ -277,9 +277,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
              *
              * <-----------><--------------><---------><----------------><---------------------><-----------><---->
-             *      16             16            8               8                  4                16         1
+             *      16             17            8               8                  4                16         1
              */
-            #define MAX_CONTEXT_SIZE    69
+            #define MAX_CONTEXT_SIZE    70
 
         #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
@@ -290,9 +290,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+----------------------+-----+
              *
              * <-----------><--------------><---------><----------------><---------------------><---->
-             *      16             16            8               8                  4              1
+             *      16             17            8               8                  4              1
              */
-            #define MAX_CONTEXT_SIZE    53
+            #define MAX_CONTEXT_SIZE    54
 
         #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
diff --git a/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h
index e74fa8257..ec14d467d 100644
--- a/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h
@@ -251,9 +251,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
              *
              * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
-             *      16             16            8               8                     5                     16         1
+             *      16             17            8               8                     5                     16         1
              */
-            #define MAX_CONTEXT_SIZE    70
+            #define MAX_CONTEXT_SIZE    71
 
         #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
 
@@ -264,9 +264,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+------------------------------+-----+
              *
              * <-----------><--------------><---------><----------------><-----------------------------><---->
-             *      16             16            8               8                     5                   1
+             *      16             17            8               8                     5                   1
              */
-            #define MAX_CONTEXT_SIZE    54
+            #define MAX_CONTEXT_SIZE    55
 
         #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
 
@@ -277,9 +277,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
              *
              * <-----------><--------------><---------><----------------><---------------------><-----------><---->
-             *      16             16            8               8                  4                16         1
+             *      16             17            8               8                  4                16         1
              */
-            #define MAX_CONTEXT_SIZE    69
+            #define MAX_CONTEXT_SIZE    70
 
         #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
@@ -290,9 +290,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+----------------------+-----+
              *
              * <-----------><--------------><---------><----------------><---------------------><---->
-             *      16             16            8               8                  4              1
+             *      16             17            8               8                  4              1
              */
-            #define MAX_CONTEXT_SIZE    53
+            #define MAX_CONTEXT_SIZE    54
 
         #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h
index e74fa8257..ec14d467d 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h
@@ -251,9 +251,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
              *
              * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
-             *      16             16            8               8                     5                     16         1
+             *      16             17            8               8                     5                     16         1
              */
-            #define MAX_CONTEXT_SIZE    70
+            #define MAX_CONTEXT_SIZE    71
 
         #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
 
@@ -264,9 +264,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+------------------------------+-----+
              *
              * <-----------><--------------><---------><----------------><-----------------------------><---->
-             *      16             16            8               8                     5                   1
+             *      16             17            8               8                     5                   1
              */
-            #define MAX_CONTEXT_SIZE    54
+            #define MAX_CONTEXT_SIZE    55
 
         #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
 
@@ -277,9 +277,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
              *
              * <-----------><--------------><---------><----------------><---------------------><-----------><---->
-             *      16             16            8               8                  4                16         1
+             *      16             17            8               8                  4                16         1
              */
-            #define MAX_CONTEXT_SIZE    69
+            #define MAX_CONTEXT_SIZE    70
 
         #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
@@ -290,9 +290,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+----------------------+-----+
              *
              * <-----------><--------------><---------><----------------><---------------------><---->
-             *      16             16            8               8                  4              1
+             *      16             17            8               8                  4              1
              */
-            #define MAX_CONTEXT_SIZE    53
+            #define MAX_CONTEXT_SIZE    54
 
         #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
diff --git a/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h
index e74fa8257..ec14d467d 100644
--- a/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h
@@ -251,9 +251,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
              *
              * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
-             *      16             16            8               8                     5                     16         1
+             *      16             17            8               8                     5                     16         1
              */
-            #define MAX_CONTEXT_SIZE    70
+            #define MAX_CONTEXT_SIZE    71
 
         #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
 
@@ -264,9 +264,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+------------------------------+-----+
              *
              * <-----------><--------------><---------><----------------><-----------------------------><---->
-             *      16             16            8               8                     5                   1
+             *      16             17            8               8                     5                   1
              */
-            #define MAX_CONTEXT_SIZE    54
+            #define MAX_CONTEXT_SIZE    55
 
         #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
 
@@ -277,9 +277,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
              *
              * <-----------><--------------><---------><----------------><---------------------><-----------><---->
-             *      16             16            8               8                  4                16         1
+             *      16             17            8               8                  4                16         1
              */
-            #define MAX_CONTEXT_SIZE    69
+            #define MAX_CONTEXT_SIZE    70
 
         #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
@@ -290,9 +290,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+----------------------+-----+
              *
              * <-----------><--------------><---------><----------------><---------------------><---->
-             *      16             16            8               8                  4              1
+             *      16             17            8               8                  4              1
              */
-            #define MAX_CONTEXT_SIZE    53
+            #define MAX_CONTEXT_SIZE    54
 
         #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
index e74fa8257..ec14d467d 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
@@ -251,9 +251,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
              *
              * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
-             *      16             16            8               8                     5                     16         1
+             *      16             17            8               8                     5                     16         1
              */
-            #define MAX_CONTEXT_SIZE    70
+            #define MAX_CONTEXT_SIZE    71
 
         #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
 
@@ -264,9 +264,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+------------------------------+-----+
              *
              * <-----------><--------------><---------><----------------><-----------------------------><---->
-             *      16             16            8               8                     5                   1
+             *      16             17            8               8                     5                   1
              */
-            #define MAX_CONTEXT_SIZE    54
+            #define MAX_CONTEXT_SIZE    55
 
         #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
 
@@ -277,9 +277,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
              *
              * <-----------><--------------><---------><----------------><---------------------><-----------><---->
-             *      16             16            8               8                  4                16         1
+             *      16             17            8               8                  4                16         1
              */
-            #define MAX_CONTEXT_SIZE    69
+            #define MAX_CONTEXT_SIZE    70
 
         #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
@@ -290,9 +290,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+----------------------+-----+
              *
              * <-----------><--------------><---------><----------------><---------------------><---->
-             *      16             16            8               8                  4              1
+             *      16             17            8               8                  4              1
              */
-            #define MAX_CONTEXT_SIZE    53
+            #define MAX_CONTEXT_SIZE    54
 
         #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
diff --git a/portable/GCC/ARM_CM3_MPU/portmacro.h b/portable/GCC/ARM_CM3_MPU/portmacro.h
index fb2c53832..a2e6883c0 100644
--- a/portable/GCC/ARM_CM3_MPU/portmacro.h
+++ b/portable/GCC/ARM_CM3_MPU/portmacro.h
@@ -125,6 +125,14 @@ typedef struct MPU_REGION_SETTINGS
 
 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
+/*
+ * +------------------------------+-------------------------------+-----+
+ * |  CONTROL, r4-r11, EXC_RETURN | PSP, r0-r3, r12, LR, PC, xPSR |     |
+ * +------------------------------+-------------------------------+-----+
+ *
+ * <-----------------------------><-------------------------------><---->
+ *                10                             9                   1
+ */
 #define MAX_CONTEXT_SIZE                    ( 20 )
 
 /* Size of an Access Control List (ACL) entry in bits. */
diff --git a/portable/GCC/ARM_CM4_MPU/portmacro.h b/portable/GCC/ARM_CM4_MPU/portmacro.h
index 0c40ac624..581b09d5c 100644
--- a/portable/GCC/ARM_CM4_MPU/portmacro.h
+++ b/portable/GCC/ARM_CM4_MPU/portmacro.h
@@ -219,7 +219,16 @@ typedef struct MPU_REGION_SETTINGS
 
 #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
-#define MAX_CONTEXT_SIZE                    ( 52 )
+/*
+ * +---------+---------------+-----------------+-----------------+-----+
+ * | s16-s31 | s0-s15, FPSCR | CONTROL, r4-r11 | PSP, r0-r3, r12 |     |
+ * |         |               | EXC_RETURN      | LR, PC, xPSR    |     |
+ * +---------+---------------+-----------------+-----------------+-----+
+ *
+ * <--------><---------------><----------------><----------------><---->
+ *     16           17               10                 9           1
+ */
+#define MAX_CONTEXT_SIZE                    ( 53 )
 
 /* Size of an Access Control List (ACL) entry in bits. */
 #define portACL_ENTRY_SIZE_BITS             ( 32U )
diff --git a/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h
index e74fa8257..ec14d467d 100644
--- a/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h
@@ -251,9 +251,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
              *
              * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
-             *      16             16            8               8                     5                     16         1
+             *      16             17            8               8                     5                     16         1
              */
-            #define MAX_CONTEXT_SIZE    70
+            #define MAX_CONTEXT_SIZE    71
 
         #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
 
@@ -264,9 +264,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+------------------------------+-----+
              *
              * <-----------><--------------><---------><----------------><-----------------------------><---->
-             *      16             16            8               8                     5                   1
+             *      16             17            8               8                     5                   1
              */
-            #define MAX_CONTEXT_SIZE    54
+            #define MAX_CONTEXT_SIZE    55
 
         #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
 
@@ -277,9 +277,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
              *
              * <-----------><--------------><---------><----------------><---------------------><-----------><---->
-             *      16             16            8               8                  4                16         1
+             *      16             17            8               8                  4                16         1
              */
-            #define MAX_CONTEXT_SIZE    69
+            #define MAX_CONTEXT_SIZE    70
 
         #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
@@ -290,9 +290,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+----------------------+-----+
              *
              * <-----------><--------------><---------><----------------><---------------------><---->
-             *      16             16            8               8                  4              1
+             *      16             17            8               8                  4              1
              */
-            #define MAX_CONTEXT_SIZE    53
+            #define MAX_CONTEXT_SIZE    54
 
         #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h
index e74fa8257..ec14d467d 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h
@@ -251,9 +251,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
              *
              * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
-             *      16             16            8               8                     5                     16         1
+             *      16             17            8               8                     5                     16         1
              */
-            #define MAX_CONTEXT_SIZE    70
+            #define MAX_CONTEXT_SIZE    71
 
         #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
 
@@ -264,9 +264,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+------------------------------+-----+
              *
              * <-----------><--------------><---------><----------------><-----------------------------><---->
-             *      16             16            8               8                     5                   1
+             *      16             17            8               8                     5                   1
              */
-            #define MAX_CONTEXT_SIZE    54
+            #define MAX_CONTEXT_SIZE    55
 
         #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
 
@@ -277,9 +277,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
              *
              * <-----------><--------------><---------><----------------><---------------------><-----------><---->
-             *      16             16            8               8                  4                16         1
+             *      16             17            8               8                  4                16         1
              */
-            #define MAX_CONTEXT_SIZE    69
+            #define MAX_CONTEXT_SIZE    70
 
         #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
@@ -290,9 +290,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+----------------------+-----+
              *
              * <-----------><--------------><---------><----------------><---------------------><---->
-             *      16             16            8               8                  4              1
+             *      16             17            8               8                  4              1
              */
-            #define MAX_CONTEXT_SIZE    53
+            #define MAX_CONTEXT_SIZE    54
 
         #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
diff --git a/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h
index e74fa8257..ec14d467d 100644
--- a/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h
@@ -251,9 +251,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
              *
              * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
-             *      16             16            8               8                     5                     16         1
+             *      16             17            8               8                     5                     16         1
              */
-            #define MAX_CONTEXT_SIZE    70
+            #define MAX_CONTEXT_SIZE    71
 
         #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
 
@@ -264,9 +264,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+------------------------------+-----+
              *
              * <-----------><--------------><---------><----------------><-----------------------------><---->
-             *      16             16            8               8                     5                   1
+             *      16             17            8               8                     5                   1
              */
-            #define MAX_CONTEXT_SIZE    54
+            #define MAX_CONTEXT_SIZE    55
 
         #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
 
@@ -277,9 +277,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
              *
              * <-----------><--------------><---------><----------------><---------------------><-----------><---->
-             *      16             16            8               8                  4                16         1
+             *      16             17            8               8                  4                16         1
              */
-            #define MAX_CONTEXT_SIZE    69
+            #define MAX_CONTEXT_SIZE    70
 
         #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
@@ -290,9 +290,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+----------------------+-----+
              *
              * <-----------><--------------><---------><----------------><---------------------><---->
-             *      16             16            8               8                  4              1
+             *      16             17            8               8                  4              1
              */
-            #define MAX_CONTEXT_SIZE    53
+            #define MAX_CONTEXT_SIZE    54
 
         #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h
index e74fa8257..ec14d467d 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h
@@ -251,9 +251,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
              *
              * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
-             *      16             16            8               8                     5                     16         1
+             *      16             17            8               8                     5                     16         1
              */
-            #define MAX_CONTEXT_SIZE    70
+            #define MAX_CONTEXT_SIZE    71
 
         #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
 
@@ -264,9 +264,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+------------------------------+-----+
              *
              * <-----------><--------------><---------><----------------><-----------------------------><---->
-             *      16             16            8               8                     5                   1
+             *      16             17            8               8                     5                   1
              */
-            #define MAX_CONTEXT_SIZE    54
+            #define MAX_CONTEXT_SIZE    55
 
         #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
 
@@ -277,9 +277,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
              *
              * <-----------><--------------><---------><----------------><---------------------><-----------><---->
-             *      16             16            8               8                  4                16         1
+             *      16             17            8               8                  4                16         1
              */
-            #define MAX_CONTEXT_SIZE    69
+            #define MAX_CONTEXT_SIZE    70
 
         #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
@@ -290,9 +290,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+----------------------+-----+
              *
              * <-----------><--------------><---------><----------------><---------------------><---->
-             *      16             16            8               8                  4              1
+             *      16             17            8               8                  4              1
              */
-            #define MAX_CONTEXT_SIZE    53
+            #define MAX_CONTEXT_SIZE    54
 
         #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
diff --git a/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h
index e74fa8257..ec14d467d 100644
--- a/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h
@@ -251,9 +251,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
              *
              * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
-             *      16             16            8               8                     5                     16         1
+             *      16             17            8               8                     5                     16         1
              */
-            #define MAX_CONTEXT_SIZE    70
+            #define MAX_CONTEXT_SIZE    71
 
         #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
 
@@ -264,9 +264,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+------------------------------+-----+
              *
              * <-----------><--------------><---------><----------------><-----------------------------><---->
-             *      16             16            8               8                     5                   1
+             *      16             17            8               8                     5                   1
              */
-            #define MAX_CONTEXT_SIZE    54
+            #define MAX_CONTEXT_SIZE    55
 
         #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
 
@@ -277,9 +277,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
              *
              * <-----------><--------------><---------><----------------><---------------------><-----------><---->
-             *      16             16            8               8                  4                16         1
+             *      16             17            8               8                  4                16         1
              */
-            #define MAX_CONTEXT_SIZE    69
+            #define MAX_CONTEXT_SIZE    70
 
         #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
@@ -290,9 +290,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+----------------------+-----+
              *
              * <-----------><--------------><---------><----------------><---------------------><---->
-             *      16             16            8               8                  4              1
+             *      16             17            8               8                  4              1
              */
-            #define MAX_CONTEXT_SIZE    53
+            #define MAX_CONTEXT_SIZE    54
 
         #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h
index e74fa8257..ec14d467d 100644
--- a/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h
@@ -251,9 +251,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
              *
              * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
-             *      16             16            8               8                     5                     16         1
+             *      16             17            8               8                     5                     16         1
              */
-            #define MAX_CONTEXT_SIZE    70
+            #define MAX_CONTEXT_SIZE    71
 
         #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
 
@@ -264,9 +264,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+------------------------------+-----+
              *
              * <-----------><--------------><---------><----------------><-----------------------------><---->
-             *      16             16            8               8                     5                   1
+             *      16             17            8               8                     5                   1
              */
-            #define MAX_CONTEXT_SIZE    54
+            #define MAX_CONTEXT_SIZE    55
 
         #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
 
@@ -277,9 +277,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
              *
              * <-----------><--------------><---------><----------------><---------------------><-----------><---->
-             *      16             16            8               8                  4                16         1
+             *      16             17            8               8                  4                16         1
              */
-            #define MAX_CONTEXT_SIZE    69
+            #define MAX_CONTEXT_SIZE    70
 
         #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
@@ -290,9 +290,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+----------------------+-----+
              *
              * <-----------><--------------><---------><----------------><---------------------><---->
-             *      16             16            8               8                  4              1
+             *      16             17            8               8                  4              1
              */
-            #define MAX_CONTEXT_SIZE    53
+            #define MAX_CONTEXT_SIZE    54
 
         #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
diff --git a/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h
index e74fa8257..ec14d467d 100644
--- a/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h
@@ -251,9 +251,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
              *
              * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
-             *      16             16            8               8                     5                     16         1
+             *      16             17            8               8                     5                     16         1
              */
-            #define MAX_CONTEXT_SIZE    70
+            #define MAX_CONTEXT_SIZE    71
 
         #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
 
@@ -264,9 +264,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+------------------------------+-----+
              *
              * <-----------><--------------><---------><----------------><-----------------------------><---->
-             *      16             16            8               8                     5                   1
+             *      16             17            8               8                     5                   1
              */
-            #define MAX_CONTEXT_SIZE    54
+            #define MAX_CONTEXT_SIZE    55
 
         #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
 
@@ -277,9 +277,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
              *
              * <-----------><--------------><---------><----------------><---------------------><-----------><---->
-             *      16             16            8               8                  4                16         1
+             *      16             17            8               8                  4                16         1
              */
-            #define MAX_CONTEXT_SIZE    69
+            #define MAX_CONTEXT_SIZE    70
 
         #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
@@ -290,9 +290,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+----------------------+-----+
              *
              * <-----------><--------------><---------><----------------><---------------------><---->
-             *      16             16            8               8                  4              1
+             *      16             17            8               8                  4              1
              */
-            #define MAX_CONTEXT_SIZE    53
+            #define MAX_CONTEXT_SIZE    54
 
         #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h
index e74fa8257..ec14d467d 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h
@@ -251,9 +251,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
              *
              * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
-             *      16             16            8               8                     5                     16         1
+             *      16             17            8               8                     5                     16         1
              */
-            #define MAX_CONTEXT_SIZE    70
+            #define MAX_CONTEXT_SIZE    71
 
         #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
 
@@ -264,9 +264,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+------------------------------+-----+
              *
              * <-----------><--------------><---------><----------------><-----------------------------><---->
-             *      16             16            8               8                     5                   1
+             *      16             17            8               8                     5                   1
              */
-            #define MAX_CONTEXT_SIZE    54
+            #define MAX_CONTEXT_SIZE    55
 
         #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
 
@@ -277,9 +277,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
              *
              * <-----------><--------------><---------><----------------><---------------------><-----------><---->
-             *      16             16            8               8                  4                16         1
+             *      16             17            8               8                  4                16         1
              */
-            #define MAX_CONTEXT_SIZE    69
+            #define MAX_CONTEXT_SIZE    70
 
         #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
@@ -290,9 +290,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+----------------------+-----+
              *
              * <-----------><--------------><---------><----------------><---------------------><---->
-             *      16             16            8               8                  4              1
+             *      16             17            8               8                  4              1
              */
-            #define MAX_CONTEXT_SIZE    53
+            #define MAX_CONTEXT_SIZE    54
 
         #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
diff --git a/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h
index e74fa8257..ec14d467d 100644
--- a/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h
@@ -251,9 +251,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
              *
              * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
-             *      16             16            8               8                     5                     16         1
+             *      16             17            8               8                     5                     16         1
              */
-            #define MAX_CONTEXT_SIZE    70
+            #define MAX_CONTEXT_SIZE    71
 
         #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
 
@@ -264,9 +264,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+------------------------------+-----+
              *
              * <-----------><--------------><---------><----------------><-----------------------------><---->
-             *      16             16            8               8                     5                   1
+             *      16             17            8               8                     5                   1
              */
-            #define MAX_CONTEXT_SIZE    54
+            #define MAX_CONTEXT_SIZE    55
 
         #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
 
@@ -277,9 +277,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
              *
              * <-----------><--------------><---------><----------------><---------------------><-----------><---->
-             *      16             16            8               8                  4                16         1
+             *      16             17            8               8                  4                16         1
              */
-            #define MAX_CONTEXT_SIZE    69
+            #define MAX_CONTEXT_SIZE    70
 
         #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
@@ -290,9 +290,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+----------------------+-----+
              *
              * <-----------><--------------><---------><----------------><---------------------><---->
-             *      16             16            8               8                  4              1
+             *      16             17            8               8                  4              1
              */
-            #define MAX_CONTEXT_SIZE    53
+            #define MAX_CONTEXT_SIZE    54
 
         #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
index e74fa8257..ec14d467d 100644
--- a/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
@@ -251,9 +251,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
              *
              * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
-             *      16             16            8               8                     5                     16         1
+             *      16             17            8               8                     5                     16         1
              */
-            #define MAX_CONTEXT_SIZE    70
+            #define MAX_CONTEXT_SIZE    71
 
         #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
 
@@ -264,9 +264,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+------------------------------+-----+
              *
              * <-----------><--------------><---------><----------------><-----------------------------><---->
-             *      16             16            8               8                     5                   1
+             *      16             17            8               8                     5                   1
              */
-            #define MAX_CONTEXT_SIZE    54
+            #define MAX_CONTEXT_SIZE    55
 
         #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
 
@@ -277,9 +277,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
              *
              * <-----------><--------------><---------><----------------><---------------------><-----------><---->
-             *      16             16            8               8                  4                16         1
+             *      16             17            8               8                  4                16         1
              */
-            #define MAX_CONTEXT_SIZE    69
+            #define MAX_CONTEXT_SIZE    70
 
         #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
@@ -290,9 +290,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+----------------------+-----+
              *
              * <-----------><--------------><---------><----------------><---------------------><---->
-             *      16             16            8               8                  4              1
+             *      16             17            8               8                  4              1
              */
-            #define MAX_CONTEXT_SIZE    53
+            #define MAX_CONTEXT_SIZE    54
 
         #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
diff --git a/portable/IAR/ARM_CM4F_MPU/portmacro.h b/portable/IAR/ARM_CM4F_MPU/portmacro.h
index 08f849992..6b7600c15 100644
--- a/portable/IAR/ARM_CM4F_MPU/portmacro.h
+++ b/portable/IAR/ARM_CM4F_MPU/portmacro.h
@@ -221,7 +221,16 @@ typedef struct MPU_REGION_SETTINGS
 
 #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
 
-#define MAX_CONTEXT_SIZE                    ( 52 )
+/*
+ * +---------+---------------+-----------------+-----------------+-----+
+ * | s16-s31 | s0-s15, FPSCR | CONTROL, r4-r11 | PSP, r0-r3, r12 |     |
+ * |         |               | EXC_RETURN      | LR, PC, xPSR    |     |
+ * +---------+---------------+-----------------+-----------------+-----+
+ *
+ * <--------><---------------><----------------><----------------><---->
+ *     16           17               10                 9           1
+ */
+#define MAX_CONTEXT_SIZE                    ( 53 )
 
 /* Size of an Access Control List (ACL) entry in bits. */
 #define portACL_ENTRY_SIZE_BITS             ( 32U )
diff --git a/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h
index e74fa8257..ec14d467d 100644
--- a/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h
@@ -251,9 +251,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
              *
              * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
-             *      16             16            8               8                     5                     16         1
+             *      16             17            8               8                     5                     16         1
              */
-            #define MAX_CONTEXT_SIZE    70
+            #define MAX_CONTEXT_SIZE    71
 
         #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
 
@@ -264,9 +264,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+------------------------------+-----+
              *
              * <-----------><--------------><---------><----------------><-----------------------------><---->
-             *      16             16            8               8                     5                   1
+             *      16             17            8               8                     5                   1
              */
-            #define MAX_CONTEXT_SIZE    54
+            #define MAX_CONTEXT_SIZE    55
 
         #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
 
@@ -277,9 +277,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
              *
              * <-----------><--------------><---------><----------------><---------------------><-----------><---->
-             *      16             16            8               8                  4                16         1
+             *      16             17            8               8                  4                16         1
              */
-            #define MAX_CONTEXT_SIZE    69
+            #define MAX_CONTEXT_SIZE    70
 
         #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
@@ -290,9 +290,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+----------------------+-----+
              *
              * <-----------><--------------><---------><----------------><---------------------><---->
-             *      16             16            8               8                  4              1
+             *      16             17            8               8                  4              1
              */
-            #define MAX_CONTEXT_SIZE    53
+            #define MAX_CONTEXT_SIZE    54
 
         #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h
index e74fa8257..ec14d467d 100644
--- a/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h
@@ -251,9 +251,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
              *
              * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
-             *      16             16            8               8                     5                     16         1
+             *      16             17            8               8                     5                     16         1
              */
-            #define MAX_CONTEXT_SIZE    70
+            #define MAX_CONTEXT_SIZE    71
 
         #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
 
@@ -264,9 +264,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+------------------------------+-----+
              *
              * <-----------><--------------><---------><----------------><-----------------------------><---->
-             *      16             16            8               8                     5                   1
+             *      16             17            8               8                     5                   1
              */
-            #define MAX_CONTEXT_SIZE    54
+            #define MAX_CONTEXT_SIZE    55
 
         #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
 
@@ -277,9 +277,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
              *
              * <-----------><--------------><---------><----------------><---------------------><-----------><---->
-             *      16             16            8               8                  4                16         1
+             *      16             17            8               8                  4                16         1
              */
-            #define MAX_CONTEXT_SIZE    69
+            #define MAX_CONTEXT_SIZE    70
 
         #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
@@ -290,9 +290,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+----------------------+-----+
              *
              * <-----------><--------------><---------><----------------><---------------------><---->
-             *      16             16            8               8                  4              1
+             *      16             17            8               8                  4              1
              */
-            #define MAX_CONTEXT_SIZE    53
+            #define MAX_CONTEXT_SIZE    54
 
         #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
diff --git a/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h
index e74fa8257..ec14d467d 100644
--- a/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h
@@ -251,9 +251,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
              *
              * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
-             *      16             16            8               8                     5                     16         1
+             *      16             17            8               8                     5                     16         1
              */
-            #define MAX_CONTEXT_SIZE    70
+            #define MAX_CONTEXT_SIZE    71
 
         #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
 
@@ -264,9 +264,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+------------------------------+-----+
              *
              * <-----------><--------------><---------><----------------><-----------------------------><---->
-             *      16             16            8               8                     5                   1
+             *      16             17            8               8                     5                   1
              */
-            #define MAX_CONTEXT_SIZE    54
+            #define MAX_CONTEXT_SIZE    55
 
         #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
 
@@ -277,9 +277,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
              *
              * <-----------><--------------><---------><----------------><---------------------><-----------><---->
-             *      16             16            8               8                  4                16         1
+             *      16             17            8               8                  4                16         1
              */
-            #define MAX_CONTEXT_SIZE    69
+            #define MAX_CONTEXT_SIZE    70
 
         #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
@@ -290,9 +290,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+----------------------+-----+
              *
              * <-----------><--------------><---------><----------------><---------------------><---->
-             *      16             16            8               8                  4              1
+             *      16             17            8               8                  4              1
              */
-            #define MAX_CONTEXT_SIZE    53
+            #define MAX_CONTEXT_SIZE    54
 
         #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h
index e74fa8257..ec14d467d 100644
--- a/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h
@@ -251,9 +251,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
              *
              * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
-             *      16             16            8               8                     5                     16         1
+             *      16             17            8               8                     5                     16         1
              */
-            #define MAX_CONTEXT_SIZE    70
+            #define MAX_CONTEXT_SIZE    71
 
         #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
 
@@ -264,9 +264,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+------------------------------+-----+
              *
              * <-----------><--------------><---------><----------------><-----------------------------><---->
-             *      16             16            8               8                     5                   1
+             *      16             17            8               8                     5                   1
              */
-            #define MAX_CONTEXT_SIZE    54
+            #define MAX_CONTEXT_SIZE    55
 
         #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
 
@@ -277,9 +277,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
              *
              * <-----------><--------------><---------><----------------><---------------------><-----------><---->
-             *      16             16            8               8                  4                16         1
+             *      16             17            8               8                  4                16         1
              */
-            #define MAX_CONTEXT_SIZE    69
+            #define MAX_CONTEXT_SIZE    70
 
         #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
@@ -290,9 +290,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+----------------------+-----+
              *
              * <-----------><--------------><---------><----------------><---------------------><---->
-             *      16             16            8               8                  4              1
+             *      16             17            8               8                  4              1
              */
-            #define MAX_CONTEXT_SIZE    53
+            #define MAX_CONTEXT_SIZE    54
 
         #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
diff --git a/portable/RVDS/ARM_CM4_MPU/portmacro.h b/portable/RVDS/ARM_CM4_MPU/portmacro.h
index 5977f3f88..8e682ba74 100644
--- a/portable/RVDS/ARM_CM4_MPU/portmacro.h
+++ b/portable/RVDS/ARM_CM4_MPU/portmacro.h
@@ -218,7 +218,16 @@ typedef struct MPU_REGION_SETTINGS
 
 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
-#define MAX_CONTEXT_SIZE                    ( 52 )
+/*
+ * +---------+---------------+-----------------+-----------------+-----+
+ * | s16-s31 | s0-s15, FPSCR | CONTROL, r4-r11 | PSP, r0-r3, r12 |     |
+ * |         |               | EXC_RETURN      | LR, PC, xPSR    |     |
+ * +---------+---------------+-----------------+-----------------+-----+
+ *
+ * <--------><---------------><----------------><----------------><---->
+ *     16           17               10                 9           1
+ */
+#define MAX_CONTEXT_SIZE                    ( 53 )
 
 /* Size of an Access Control List (ACL) entry in bits. */
 #define portACL_ENTRY_SIZE_BITS             ( 32U )

From b421abc7c389fbd02f25ec96fac9e4aed74f83ad Mon Sep 17 00:00:00 2001
From: Cavin McKinley <30472644+mcknly@users.noreply.github.com>
Date: Sat, 25 Jan 2025 03:38:49 -0600
Subject: [PATCH 377/424] Update Community-Supported-Ports submod to fix RP2350
 port - FreeRTOS-Kernel#1220 (#1232)

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
---
 portable/ThirdParty/Community-Supported-Ports | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/portable/ThirdParty/Community-Supported-Ports b/portable/ThirdParty/Community-Supported-Ports
index 3c5bfb8f2..bae4c7aa1 160000
--- a/portable/ThirdParty/Community-Supported-Ports
+++ b/portable/ThirdParty/Community-Supported-Ports
@@ -1 +1 @@
-Subproject commit 3c5bfb8f2e557735b5200176b4a8b25a40c68d1b
+Subproject commit bae4c7aa19009825ba48071a8fe25dcb8be84880

From f94bc89108ffca538cf91d5856149960a5d4be81 Mon Sep 17 00:00:00 2001
From: Kody Stribrny <89810515+kstribrnAmzn@users.noreply.github.com>
Date: Tue, 28 Jan 2025 09:13:17 -0800
Subject: [PATCH 378/424] fix: SA violation fixes and simplification for idle
 task length restrictions (#1227)

fix: SA violation fixes and simplification for idle task length restrictions

This change:
* Removes the dependency on strings.h for the prvCreateIdleTask function
* Resolves several static analysis violations reported by tools like Parasoft

Builds off of - https://github.com/FreeRTOS/FreeRTOS-Kernel/pull/1203
---
 MISRA.md | 19 +++++++++++++++++++
 tasks.c  | 46 ++++++++++++++++++++++++++++++++++------------
 2 files changed, 53 insertions(+), 12 deletions(-)

diff --git a/MISRA.md b/MISRA.md
index 4355ec678..b5941037f 100644
--- a/MISRA.md
+++ b/MISRA.md
@@ -115,6 +115,25 @@ _Ref 11.5.5_
    because data storage buffers are implemented as uint8_t arrays for the
    ease of sizing, alignment and access.
 
+#### Rule 14.3
+
+MISRA C-2012 Rule 14.3: Controlling expressions shall not be invariant.
+
+_Ref 14.3_
+ - The `configMAX_TASK_NAME_LEN` and `taskRESERVED_TASK_NAME_LENGTH` are
+   evaluated to constants at compile time and may vary based on the build
+   configuration.
+
+#### Rule 18.1
+
+MISRA C-2012 Rule 18.1: A pointer resulting from arithmetic on a pointer operand
+shall address an element of the same array as that pointer operand.
+
+_Ref 18.1_
+ - Array access remains within bounds since either the null terminator in
+   the IDLE task name will break the loop, or the loop will break normally
+   if the array size is smaller than the IDLE task name length.
+
 #### Rule 21.6
 
 MISRA C-2012 Rule 21.6: The Standard Library input/output functions shall not
diff --git a/tasks.c b/tasks.c
index d7153f680..518c9e87f 100644
--- a/tasks.c
+++ b/tasks.c
@@ -156,6 +156,23 @@
     #define configIDLE_TASK_NAME    "IDLE"
 #endif
 
+#if ( configNUMBER_OF_CORES > 1 )
+    /* Reserve space for Core ID and null termination. */
+    #if ( configMAX_TASK_NAME_LEN < 2U )
+        #error Minimum required task name length is 2. Please increase configMAX_TASK_NAME_LEN.
+    #endif
+    #define taskRESERVED_TASK_NAME_LENGTH    2U
+
+#elif ( configNUMBER_OF_CORES > 9 )
+    #warning Please increase taskRESERVED_TASK_NAME_LENGTH. 1 character is insufficient to store the core ID.
+#else
+    /* Reserve space for null termination. */
+    #if ( configMAX_TASK_NAME_LEN < 1U )
+        #error Minimum required task name length is 1. Please increase configMAX_TASK_NAME_LEN.
+    #endif
+    #define taskRESERVED_TASK_NAME_LENGTH    1U
+#endif /* if ( ( configNUMBER_OF_CORES > 1 ) */
+
 #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 )
 
 /* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 0 then task selection is
@@ -3527,21 +3544,26 @@ static BaseType_t prvCreateIdleTasks( void )
     BaseType_t xCoreID;
     char cIdleName[ configMAX_TASK_NAME_LEN ] = { 0 };
     TaskFunction_t pxIdleTaskFunction = NULL;
-    BaseType_t xIdleTaskNameIndex;
-    BaseType_t xIdleNameLen;
-    BaseType_t xCopyLen;
+    UBaseType_t xIdleTaskNameIndex;
 
-    configASSERT( ( configIDLE_TASK_NAME != NULL ) && ( configMAX_TASK_NAME_LEN > 3 ) );
-
-    /* The length of the idle task name is limited to the minimum of the length
-     * of configIDLE_TASK_NAME and configMAX_TASK_NAME_LEN - 2, keeping space
-     * for the core ID suffix and the null-terminator. */
-    xIdleNameLen = strlen( configIDLE_TASK_NAME );
-    xCopyLen = xIdleNameLen < ( configMAX_TASK_NAME_LEN - 2 ) ? xIdleNameLen : ( configMAX_TASK_NAME_LEN - 2 );
-
-    for( xIdleTaskNameIndex = ( BaseType_t ) 0; xIdleTaskNameIndex < xCopyLen; xIdleTaskNameIndex++ )
+    /* MISRA Ref 14.3.1 [Configuration dependent invariant] */
+    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-143. */
+    /* coverity[misra_c_2012_rule_14_3_violation] */
+    for( xIdleTaskNameIndex = 0U; xIdleTaskNameIndex < ( configMAX_TASK_NAME_LEN - taskRESERVED_TASK_NAME_LENGTH ); xIdleTaskNameIndex++ )
     {
+        /* MISRA Ref 18.1.1 [Configuration dependent bounds checking] */
+        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-181. */
+        /* coverity[misra_c_2012_rule_18_1_violation] */
         cIdleName[ xIdleTaskNameIndex ] = configIDLE_TASK_NAME[ xIdleTaskNameIndex ];
+
+        if( cIdleName[ xIdleTaskNameIndex ] == ( char ) 0x00 )
+        {
+            break;
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
     }
 
     /* Ensure null termination. */

From ad4e7238293cbe994e7450e1bc415136875da322 Mon Sep 17 00:00:00 2001
From: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Date: Wed, 29 Jan 2025 07:27:30 +0530
Subject: [PATCH 379/424] Mark mutex as robust to prevent deadlocks (#1233)

Mark mutex as robust to prevent deadlocks

Prevent application hangs that occur when a thread dies while holding a
mutex, particularly during vTaskEndScheduler or exit calls. This is
achieved by setting the PTHREAD_MUTEX_ROBUST attribute on the mutex.

Fixes:
- GitHub issue: FreeRTOS/FreeRTOS-Kernel#1217
- Forum thread: freertos.org/t/22287

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 portable/ThirdParty/GCC/Posix/port.c          | 67 +++++++++++++------
 .../GCC/Posix/utils/wait_for_event.c          | 39 +++++++++--
 2 files changed, 80 insertions(+), 26 deletions(-)

diff --git a/portable/ThirdParty/GCC/Posix/port.c b/portable/ThirdParty/GCC/Posix/port.c
index c4eacb2ba..4f7d8b609 100644
--- a/portable/ThirdParty/GCC/Posix/port.c
+++ b/portable/ThirdParty/GCC/Posix/port.c
@@ -119,14 +119,20 @@ static void prvResumeThread( Thread_t * xThreadId );
 static void vPortSystemTickHandler( int sig );
 static void vPortStartFirstTask( void );
 static void prvPortYieldFromISR( void );
+static void prvThreadKeyDestructor( void * pvData );
+static void prvInitThreadKey( void );
+static void prvMarkAsFreeRTOSThread( void );
+static BaseType_t prvIsFreeRTOSThread( void );
+static void prvDestroyThreadKey( void );
 /*-----------------------------------------------------------*/
 
-void prvThreadKeyDestructor( void * data )
+static void prvThreadKeyDestructor( void * pvData )
 {
-    free( data );
+    free( pvData );
 }
+/*-----------------------------------------------------------*/
 
-static void prvInitThreadKey()
+static void prvInitThreadKey( void )
 {
     pthread_mutex_lock( &xThreadMutex );
 
@@ -137,24 +143,39 @@ static void prvInitThreadKey()
 
     pthread_mutex_unlock( &xThreadMutex );
 }
+/*-----------------------------------------------------------*/
 
-static void prvMarkAsFreeRTOSThread( pthread_t thread )
+static void prvMarkAsFreeRTOSThread( void )
 {
+    uint8_t * pucThreadData = NULL;
+
     prvInitThreadKey();
-    uint8_t * thread_data = malloc( 1 );
-    configASSERT( thread_data != NULL );
-    *thread_data = 1;
-    pthread_setspecific( xThreadKey, thread_data );
-}
 
-static BaseType_t prvIsFreeRTOSThread( pthread_t thread )
+    pucThreadData = malloc( 1 );
+    configASSERT( pucThreadData != NULL );
+
+    *pucThreadData = 1;
+
+    pthread_setspecific( xThreadKey, pucThreadData );
+}
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvIsFreeRTOSThread( void )
 {
-    uint8_t * thread_data = ( uint8_t * ) pthread_getspecific( xThreadKey );
+    uint8_t * pucThreadData = NULL;
+    BaseType_t xRet = pdFALSE;
 
-    return thread_data != NULL && *thread_data == 1;
+    pucThreadData = ( uint8_t * ) pthread_getspecific( xThreadKey );
+    if( ( pucThreadData != NULL ) && ( *pucThreadData == 1 ) )
+    {
+        xRet = pdTRUE;
+    }
+
+    return xRet;
 }
+/*-----------------------------------------------------------*/
 
-static void prvDestroyThreadKey()
+static void prvDestroyThreadKey( void )
 {
     pthread_key_delete( xThreadKey );
 }
@@ -309,7 +330,7 @@ void vPortEndScheduler( void )
     ( void ) pthread_kill( hMainThread, SIG_RESUME );
 
     /* Waiting to be deleted here. */
-    if( prvIsFreeRTOSThread( pthread_self() ) == pdTRUE )
+    if( prvIsFreeRTOSThread() == pdTRUE )
     {
         pxCurrentThread = prvGetThreadFromTask( xTaskGetCurrentTaskHandle() );
         event_wait( pxCurrentThread->ev );
@@ -369,7 +390,7 @@ void vPortYield( void )
 
 void vPortDisableInterrupts( void )
 {
-    if( prvIsFreeRTOSThread( pthread_self() ) == pdTRUE )
+    if( prvIsFreeRTOSThread() == pdTRUE )
     {
         pthread_sigmask(SIG_BLOCK, &xAllSignals, NULL);
     }
@@ -378,9 +399,9 @@ void vPortDisableInterrupts( void )
 
 void vPortEnableInterrupts( void )
 {
-    if( prvIsFreeRTOSThread( pthread_self() ) == pdTRUE )
+    if( prvIsFreeRTOSThread() == pdTRUE )
     {
-        pthread_sigmask(SIG_UNBLOCK, &xAllSignals, NULL);
+        pthread_sigmask( SIG_UNBLOCK, &xAllSignals, NULL );
     }
 }
 /*-----------------------------------------------------------*/
@@ -417,9 +438,9 @@ static void * prvTimerTickHandler( void * arg )
 {
     ( void ) arg;
 
-    prvMarkAsFreeRTOSThread( pthread_self() );
+    prvMarkAsFreeRTOSThread();
 
-    prvPortSetCurrentThreadName("Scheduler timer");
+    prvPortSetCurrentThreadName( "Scheduler timer" );
 
     while( xTimerTickThreadShouldRun )
     {
@@ -451,7 +472,7 @@ void prvSetupTimerInterrupt( void )
 
 static void vPortSystemTickHandler( int sig )
 {
-    if( prvIsFreeRTOSThread( pthread_self() ) == pdTRUE )
+    if( prvIsFreeRTOSThread() == pdTRUE )
     {
         Thread_t * pxThreadToSuspend;
         Thread_t * pxThreadToResume;
@@ -473,7 +494,9 @@ static void vPortSystemTickHandler( int sig )
         }
 
         uxCriticalNesting--;
-    } else {
+    }
+    else
+    {
         fprintf( stderr, "vPortSystemTickHandler called from non-FreeRTOS thread\n" );
     }
 }
@@ -508,7 +531,7 @@ static void * prvWaitForStart( void * pvParams )
 {
     Thread_t * pxThread = pvParams;
 
-    prvMarkAsFreeRTOSThread( pthread_self() );
+    prvMarkAsFreeRTOSThread();
 
     prvSuspendSelf( pxThread );
 
diff --git a/portable/ThirdParty/GCC/Posix/utils/wait_for_event.c b/portable/ThirdParty/GCC/Posix/utils/wait_for_event.c
index bf744e27f..55fd7bbfc 100644
--- a/portable/ThirdParty/GCC/Posix/utils/wait_for_event.c
+++ b/portable/ThirdParty/GCC/Posix/utils/wait_for_event.c
@@ -35,9 +35,11 @@
 struct event
 {
     pthread_mutex_t mutex;
+    pthread_mutexattr_t mutexattr;
     pthread_cond_t cond;
     bool event_triggered;
 };
+/*-----------------------------------------------------------*/
 
 struct event * event_create( void )
 {
@@ -46,23 +48,36 @@ struct event * event_create( void )
     if( ev != NULL )
     {
         ev->event_triggered = false;
-        pthread_mutex_init( &ev->mutex, NULL );
+        pthread_mutexattr_init( &ev->mutexattr );
+        #ifndef __APPLE__
+            pthread_mutexattr_setrobust( &ev->mutexattr, PTHREAD_MUTEX_ROBUST );
+        #endif
+        pthread_mutex_init( &ev->mutex, &ev->mutexattr );
         pthread_cond_init( &ev->cond, NULL );
     }
 
     return ev;
 }
+/*-----------------------------------------------------------*/
 
 void event_delete( struct event * ev )
 {
     pthread_mutex_destroy( &ev->mutex );
+    pthread_mutexattr_destroy( &ev->mutexattr );
     pthread_cond_destroy( &ev->cond );
     free( ev );
 }
+/*-----------------------------------------------------------*/
 
 bool event_wait( struct event * ev )
 {
-    pthread_mutex_lock( &ev->mutex );
+    if( pthread_mutex_lock( &ev->mutex ) == EOWNERDEAD )
+    {
+        #ifndef __APPLE__
+            /* If the thread owning the mutex died, make the mutex consistent. */
+            pthread_mutex_consistent( &ev->mutex );
+        #endif
+    }
 
     while( ev->event_triggered == false )
     {
@@ -73,6 +88,8 @@ bool event_wait( struct event * ev )
     pthread_mutex_unlock( &ev->mutex );
     return true;
 }
+/*-----------------------------------------------------------*/
+
 bool event_wait_timed( struct event * ev,
                        time_t ms )
 {
@@ -82,7 +99,13 @@ bool event_wait_timed( struct event * ev,
     clock_gettime( CLOCK_REALTIME, &ts );
     ts.tv_sec += ms / 1000;
     ts.tv_nsec += ( ( ms % 1000 ) * 1000000 );
-    pthread_mutex_lock( &ev->mutex );
+    if( pthread_mutex_lock( &ev->mutex ) == EOWNERDEAD )
+    {
+        #ifndef __APPLE__
+            /* If the thread owning the mutex died, make the mutex consistent. */
+            pthread_mutex_consistent( &ev->mutex );
+        #endif
+    }
 
     while( ( ev->event_triggered == false ) && ( ret == 0 ) )
     {
@@ -98,11 +121,19 @@ bool event_wait_timed( struct event * ev,
     pthread_mutex_unlock( &ev->mutex );
     return true;
 }
+/*-----------------------------------------------------------*/
 
 void event_signal( struct event * ev )
 {
-    pthread_mutex_lock( &ev->mutex );
+    if( pthread_mutex_lock( &ev->mutex ) == EOWNERDEAD )
+    {
+        #ifndef __APPLE__
+            /* If the thread owning the mutex died, make the mutex consistent. */
+            pthread_mutex_consistent( &ev->mutex );
+        #endif
+    }
     ev->event_triggered = true;
     pthread_cond_signal( &ev->cond );
     pthread_mutex_unlock( &ev->mutex );
 }
+/*-----------------------------------------------------------*/

From 0f7edaff734d39be7fa74cf7d244325bed34f3f0 Mon Sep 17 00:00:00 2001
From: Ben Nicholls <83202658+bknicholls@users.noreply.github.com>
Date: Tue, 4 Feb 2025 16:33:44 +1100
Subject: [PATCH 380/424] Reinstate "Fix inaccurate ticks in windows port"
 (#1198)

Reinstates PR https://github.com/FreeRTOS/FreeRTOS-Kernel/pull/142 that was reverted in https://github.com/FreeRTOS/FreeRTOS-Kernel/pull/143

Co-authored-by: Ben Nicholls <benn@smartbadge.com.au>
---
 portable/MSVC-MingW/port.c | 40 +++++++++++++++++++++++++-------------
 1 file changed, 27 insertions(+), 13 deletions(-)

diff --git a/portable/MSVC-MingW/port.c b/portable/MSVC-MingW/port.c
index c6ee941c8..9ce0c1b15 100644
--- a/portable/MSVC-MingW/port.c
+++ b/portable/MSVC-MingW/port.c
@@ -141,6 +141,9 @@ static DWORD WINAPI prvSimulatedPeripheralTimer( LPVOID lpParameter )
 {
     TickType_t xMinimumWindowsBlockTime;
     TIMECAPS xTimeCaps;
+    TickType_t xWaitTimeBetweenTicks = portTICK_PERIOD_MS;
+    HANDLE hTimer = NULL;
+    LARGE_INTEGER liDueTime;
 
     /* Set the timer resolution to the maximum possible. */
     if( timeGetDevCaps( &xTimeCaps, sizeof( xTimeCaps ) ) == MMSYSERR_NOERROR )
@@ -160,22 +163,33 @@ static DWORD WINAPI prvSimulatedPeripheralTimer( LPVOID lpParameter )
     /* Just to prevent compiler warnings. */
     ( void ) lpParameter;
 
+    /* Tick time for the timer is adjusted with the maximum available
+     resolution. */
+    if( portTICK_PERIOD_MS < xMinimumWindowsBlockTime )
+    {
+        xWaitTimeBetweenTicks = xMinimumWindowsBlockTime;
+    }
+
+    /* Convert the tick time in milliseconds to nanoseconds resolution
+     for the Waitable Timer. */
+    liDueTime.u.LowPart = xWaitTimeBetweenTicks * 1000 * 1000;
+    liDueTime.u.HighPart = 0;
+
+    /* Create a synchronization Waitable Timer.*/
+    hTimer = CreateWaitableTimer( NULL, FALSE, NULL );
+
+    configASSERT( hTimer != NULL );
+
+    /* Set the Waitable Timer. The timer is set to run periodically at every
+    xWaitTimeBetweenTicks milliseconds. */
+    configASSERT( SetWaitableTimer( hTimer, &liDueTime, xWaitTimeBetweenTicks, NULL, NULL, 0 ) );
+
     while( xPortRunning == pdTRUE )
     {
         /* Wait until the timer expires and we can access the simulated interrupt
-         * variables.  *NOTE* this is not a 'real time' way of generating tick
-         * events as the next wake time should be relative to the previous wake
-         * time, not the time that Sleep() is called.  It is done this way to
-         * prevent overruns in this very non real time simulated/emulated
-         * environment. */
-        if( portTICK_PERIOD_MS < xMinimumWindowsBlockTime )
-        {
-            Sleep( xMinimumWindowsBlockTime );
-        }
-        else
-        {
-            Sleep( portTICK_PERIOD_MS );
-        }
+         * variables. */
+
+        WaitForSingleObject( hTimer, INFINITE );
 
         vPortGenerateSimulatedInterruptFromWindowsThread( portINTERRUPT_TICK );
     }

From ae0a5913c8b95276e5a53122bfbf6d505a297ba7 Mon Sep 17 00:00:00 2001
From: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Date: Thu, 6 Feb 2025 14:41:19 +0530
Subject: [PATCH 381/424] Call key creation before checking if a thread is
 FreeRTOS (#1238)

---
 portable/ThirdParty/GCC/Posix/port.c | 39 ++++++++++++++--------------
 1 file changed, 19 insertions(+), 20 deletions(-)

diff --git a/portable/ThirdParty/GCC/Posix/port.c b/portable/ThirdParty/GCC/Posix/port.c
index 4f7d8b609..66095fb2c 100644
--- a/portable/ThirdParty/GCC/Posix/port.c
+++ b/portable/ThirdParty/GCC/Posix/port.c
@@ -97,6 +97,7 @@ static inline Thread_t * prvGetThreadFromTask( TaskHandle_t xTask )
 /*-----------------------------------------------------------*/
 
 static pthread_once_t hSigSetupThread = PTHREAD_ONCE_INIT;
+static pthread_once_t hThreadKeyOnce = PTHREAD_ONCE_INIT;
 static sigset_t xAllSignals;
 static sigset_t xSchedulerOriginalSignalMask;
 static pthread_t hMainThread = ( pthread_t ) NULL;
@@ -105,7 +106,6 @@ static BaseType_t xSchedulerEnd = pdFALSE;
 static pthread_t hTimerTickThread;
 static bool xTimerTickThreadShouldRun;
 static uint64_t prvStartTimeNs;
-static pthread_mutex_t xThreadMutex = PTHREAD_MUTEX_INITIALIZER;
 static pthread_key_t xThreadKey = 0;
 /*-----------------------------------------------------------*/
 
@@ -134,14 +134,7 @@ static void prvThreadKeyDestructor( void * pvData )
 
 static void prvInitThreadKey( void )
 {
-    pthread_mutex_lock( &xThreadMutex );
-
-    if( xThreadKey == 0 )
-    {
-        pthread_key_create( &xThreadKey, prvThreadKeyDestructor );
-    }
-
-    pthread_mutex_unlock( &xThreadMutex );
+    pthread_key_create( &xThreadKey, prvThreadKeyDestructor );
 }
 /*-----------------------------------------------------------*/
 
@@ -149,7 +142,7 @@ static void prvMarkAsFreeRTOSThread( void )
 {
     uint8_t * pucThreadData = NULL;
 
-    prvInitThreadKey();
+    ( void ) pthread_once( &hThreadKeyOnce, prvInitThreadKey );
 
     pucThreadData = malloc( 1 );
     configASSERT( pucThreadData != NULL );
@@ -165,7 +158,10 @@ static BaseType_t prvIsFreeRTOSThread( void )
     uint8_t * pucThreadData = NULL;
     BaseType_t xRet = pdFALSE;
 
+    ( void ) pthread_once( &hThreadKeyOnce, prvInitThreadKey );
+
     pucThreadData = ( uint8_t * ) pthread_getspecific( xThreadKey );
+
     if( ( pucThreadData != NULL ) && ( *pucThreadData == 1 ) )
     {
         xRet = pdTRUE;
@@ -192,13 +188,13 @@ void prvFatalError( const char * pcCall,
 }
 /*-----------------------------------------------------------*/
 
-static void prvPortSetCurrentThreadName(char * pxThreadName)
+static void prvPortSetCurrentThreadName( char * pxThreadName )
 {
-#ifdef __APPLE__
-    pthread_setname_np(pxThreadName);
-#else
-    pthread_setname_np(pthread_self(), pxThreadName);
-#endif
+    #ifdef __APPLE__
+        pthread_setname_np( pxThreadName );
+    #else
+        pthread_setname_np( pthread_self(), pxThreadName );
+    #endif
 }
 /*-----------------------------------------------------------*/
 
@@ -269,7 +265,7 @@ BaseType_t xPortStartScheduler( void )
     sigset_t xSignals;
 
     hMainThread = pthread_self();
-    prvPortSetCurrentThreadName("Scheduler");
+    prvPortSetCurrentThreadName( "Scheduler" );
 
     /* Start the timer that generates the tick ISR(SIGALRM).
      * Interrupts are disabled here already. */
@@ -303,9 +299,12 @@ BaseType_t xPortStartScheduler( void )
      * memset the internal struct members for MacOS/Linux Compatibility */
     #if __APPLE__
         hSigSetupThread.__sig = _PTHREAD_ONCE_SIG_init;
-        memset( ( void * ) &hSigSetupThread.__opaque, 0, sizeof(hSigSetupThread.__opaque));
+        hThreadKeyOnce.__sig = _PTHREAD_ONCE_SIG_init;
+        memset( ( void * ) &hSigSetupThread.__opaque, 0, sizeof( hSigSetupThread.__opaque ) );
+        memset( ( void * ) &hThreadKeyOnce.__opaque, 0, sizeof( hThreadKeyOnce.__opaque ) );
     #else /* Linux PTHREAD library*/
         hSigSetupThread = PTHREAD_ONCE_INIT;
+        hThreadKeyOnce = PTHREAD_ONCE_INIT;
     #endif /* __APPLE__*/
 
     /* Restore original signal mask. */
@@ -392,7 +391,7 @@ void vPortDisableInterrupts( void )
 {
     if( prvIsFreeRTOSThread() == pdTRUE )
     {
-        pthread_sigmask(SIG_BLOCK, &xAllSignals, NULL);
+        pthread_sigmask( SIG_BLOCK, &xAllSignals, NULL );
     }
 }
 /*-----------------------------------------------------------*/
@@ -540,7 +539,7 @@ static void * prvWaitForStart( void * pvParams )
     vPortEnableInterrupts();
 
     /* Set thread name */
-    prvPortSetCurrentThreadName(pcTaskGetName(xTaskGetCurrentTaskHandle()));
+    prvPortSetCurrentThreadName( pcTaskGetName( xTaskGetCurrentTaskHandle() ) );
 
     /* Call the task's entry point. */
     pxThread->pxCode( pxThread->pvParams );

From d10ee468114afb06ee6eca8f976c7b953aa5a2b8 Mon Sep 17 00:00:00 2001
From: Jakub Tymejczyk <jakub@tymejczyk.pl>
Date: Fri, 7 Feb 2025 02:21:34 +0100
Subject: [PATCH 382/424] Fix GCC/Posix port compilation on FreeBSD (#1239)
 (#1240)

On FreeBSD pthread_once_t is a struct and cast is required.
Otherwise there's compilation error:
../../mocks/freertos/port.c:261:23: error: expected expression
    hSigSetupThread = PTHREAD_ONCE_INIT;
                      ^
PTHREAD_ONCE_INIT is defined as: { PTHREAD_NEEDS_INIT, NULL } on FreeBSD

Co-authored-by: Jakub Tymejczyk <jakub.tymejczyk@enigma.com.pl>
---
 portable/ThirdParty/GCC/Posix/port.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/portable/ThirdParty/GCC/Posix/port.c b/portable/ThirdParty/GCC/Posix/port.c
index 66095fb2c..5dc7f45f8 100644
--- a/portable/ThirdParty/GCC/Posix/port.c
+++ b/portable/ThirdParty/GCC/Posix/port.c
@@ -303,8 +303,8 @@ BaseType_t xPortStartScheduler( void )
         memset( ( void * ) &hSigSetupThread.__opaque, 0, sizeof( hSigSetupThread.__opaque ) );
         memset( ( void * ) &hThreadKeyOnce.__opaque, 0, sizeof( hThreadKeyOnce.__opaque ) );
     #else /* Linux PTHREAD library*/
-        hSigSetupThread = PTHREAD_ONCE_INIT;
-        hThreadKeyOnce = PTHREAD_ONCE_INIT;
+        hSigSetupThread = ( pthread_once_t ) PTHREAD_ONCE_INIT;
+        hThreadKeyOnce = ( pthread_once_t ) PTHREAD_ONCE_INIT;
     #endif /* __APPLE__*/
 
     /* Restore original signal mask. */

From a470b2d3755b5aaad71f4fdae0ca4a8361b4303a Mon Sep 17 00:00:00 2001
From: Graham Sanderson <graham.sanderson@raspberrypi.com>
Date: Sun, 9 Feb 2025 23:32:36 -0600
Subject: [PATCH 383/424] RP2040: update FreeRTOS_Kernel_import.cmake to match
 the newer version in Community-Supported-Ports (#1243)

- The newer version looks in Community-Supported-Ports too

Co-authored-by: graham sanderson <graham.sanderson@raspeberryi.com>
---
 .../GCC/RP2040/FreeRTOS_Kernel_import.cmake   | 90 ++++++++++++-------
 1 file changed, 60 insertions(+), 30 deletions(-)

diff --git a/portable/ThirdParty/GCC/RP2040/FreeRTOS_Kernel_import.cmake b/portable/ThirdParty/GCC/RP2040/FreeRTOS_Kernel_import.cmake
index 109a54e19..854aab43f 100644
--- a/portable/ThirdParty/GCC/RP2040/FreeRTOS_Kernel_import.cmake
+++ b/portable/ThirdParty/GCC/RP2040/FreeRTOS_Kernel_import.cmake
@@ -10,38 +10,68 @@ if (DEFINED ENV{FREERTOS_KERNEL_PATH} AND (NOT FREERTOS_KERNEL_PATH))
     message("Using FREERTOS_KERNEL_PATH from environment ('${FREERTOS_KERNEL_PATH}')")
 endif ()
 
-set(FREERTOS_KERNEL_RP2040_RELATIVE_PATH "portable/ThirdParty/GCC/RP2040")
-# undo the above
-set(FREERTOS_KERNEL_RP2040_BACK_PATH "../../../..")
-
-if (NOT FREERTOS_KERNEL_PATH)
-    # check if we are inside the FreeRTOS kernel tree (i.e. this file has been included directly)
-    get_filename_component(_ACTUAL_PATH ${CMAKE_CURRENT_LIST_DIR} REALPATH)
-    get_filename_component(_POSSIBLE_PATH ${CMAKE_CURRENT_LIST_DIR}/${FREERTOS_KERNEL_RP2040_BACK_PATH}/${FREERTOS_KERNEL_RP2040_RELATIVE_PATH} REALPATH)
-    if (_ACTUAL_PATH STREQUAL _POSSIBLE_PATH)
-        get_filename_component(FREERTOS_KERNEL_PATH ${CMAKE_CURRENT_LIST_DIR}/${FREERTOS_KERNEL_RP2040_BACK_PATH} REALPATH)
+# first pass we look in old tree; second pass we look in new tree
+foreach(SEARCH_PASS RANGE 0 1)
+    if (SEARCH_PASS)
+        # ports may be moving to submodule in the future
+        set(FREERTOS_KERNEL_RP2040_RELATIVE_PATH "portable/ThirdParty/Community-Supported-Ports/GCC")
+        set(FREERTOS_KERNEL_RP2040_BACK_PATH "../../../../..")
+    else()
+        set(FREERTOS_KERNEL_RP2040_RELATIVE_PATH "portable/ThirdParty/GCC")
+        set(FREERTOS_KERNEL_RP2040_BACK_PATH "../../../..")
     endif()
-    if (_ACTUAL_PATH STREQUAL _POSSIBLE_PATH)
-        get_filename_component(FREERTOS_KERNEL_PATH ${CMAKE_CURRENT_LIST_DIR}/${FREERTOS_KERNEL_RP2040_BACK_PATH} REALPATH)
-        message("Setting FREERTOS_KERNEL_PATH to ${FREERTOS_KERNEL_PATH} based on location of FreeRTOS-Kernel-import.cmake")
-    elseif (PICO_SDK_PATH AND EXISTS "${PICO_SDK_PATH}/../FreeRTOS-Kernel")
-        set(FREERTOS_KERNEL_PATH ${PICO_SDK_PATH}/../FreeRTOS-Kernel)
-        message("Defaulting FREERTOS_KERNEL_PATH as sibling of PICO_SDK_PATH: ${FREERTOS_KERNEL_PATH}")
-    endif()
-endif ()
 
-if (NOT FREERTOS_KERNEL_PATH)
-    foreach(POSSIBLE_SUFFIX Source FreeRTOS-Kernel FreeRTOS/Source)
-        # check if FreeRTOS-Kernel exists under directory that included us
-        set(SEARCH_ROOT ${CMAKE_CURRENT_SOURCE_DIR})
-        get_filename_component(_POSSIBLE_PATH ${SEARCH_ROOT}/${POSSIBLE_SUFFIX} REALPATH)
-        if (EXISTS ${_POSSIBLE_PATH}/${FREERTOS_KERNEL_RP2040_RELATIVE_PATH}/CMakeLists.txt)
-            get_filename_component(FREERTOS_KERNEL_PATH ${_POSSIBLE_PATH} REALPATH)
-            message("Setting FREERTOS_KERNEL_PATH to '${FREERTOS_KERNEL_PATH}' found relative to enclosing project")
+    if(PICO_PLATFORM STREQUAL "rp2040")
+        set(FREERTOS_KERNEL_RP2040_RELATIVE_PATH "${FREERTOS_KERNEL_RP2040_RELATIVE_PATH}/RP2040")
+    else()
+        if (PICO_PLATFORM STREQUAL "rp2350-riscv")
+            set(FREERTOS_KERNEL_RP2040_RELATIVE_PATH "${FREERTOS_KERNEL_RP2040_RELATIVE_PATH}/RP2350_RISC-V")
+        else()
+            set(FREERTOS_KERNEL_RP2040_RELATIVE_PATH "${FREERTOS_KERNEL_RP2040_RELATIVE_PATH}/RP2350_ARM_NTZ")
+        endif()
+    endif()
+
+    if (NOT FREERTOS_KERNEL_PATH)
+        # check if we are inside the FreeRTOS kernel tree (i.e. this file has been included directly)
+        get_filename_component(_ACTUAL_PATH ${CMAKE_CURRENT_LIST_DIR} REALPATH)
+        get_filename_component(_POSSIBLE_PATH ${CMAKE_CURRENT_LIST_DIR}/${FREERTOS_KERNEL_RP2040_BACK_PATH}/${FREERTOS_KERNEL_RP2040_RELATIVE_PATH} REALPATH)
+        if (_ACTUAL_PATH STREQUAL _POSSIBLE_PATH)
+            get_filename_component(FREERTOS_KERNEL_PATH ${CMAKE_CURRENT_LIST_DIR}/${FREERTOS_KERNEL_RP2040_BACK_PATH} REALPATH)
+        endif()
+        if (_ACTUAL_PATH STREQUAL _POSSIBLE_PATH)
+            get_filename_component(FREERTOS_KERNEL_PATH ${CMAKE_CURRENT_LIST_DIR}/${FREERTOS_KERNEL_RP2040_BACK_PATH} REALPATH)
+            message("Setting FREERTOS_KERNEL_PATH to ${FREERTOS_KERNEL_PATH} based on location of FreeRTOS-Kernel-import.cmake")
+            break()
+        elseif (PICO_SDK_PATH AND EXISTS "${PICO_SDK_PATH}/../FreeRTOS-Kernel")
+            set(FREERTOS_KERNEL_PATH ${PICO_SDK_PATH}/../FreeRTOS-Kernel)
+            message("Defaulting FREERTOS_KERNEL_PATH as sibling of PICO_SDK_PATH: ${FREERTOS_KERNEL_PATH}")
             break()
         endif()
-    endforeach()
-endif()
+    endif ()
+
+    if (NOT FREERTOS_KERNEL_PATH)
+        foreach(POSSIBLE_SUFFIX Source FreeRTOS-Kernel FreeRTOS/Source)
+            # check if FreeRTOS-Kernel exists under directory that included us
+            set(SEARCH_ROOT ${CMAKE_CURRENT_SOURCE_DIR})
+            get_filename_component(_POSSIBLE_PATH ${SEARCH_ROOT}/${POSSIBLE_SUFFIX} REALPATH)
+            if (EXISTS ${_POSSIBLE_PATH}/${FREERTOS_KERNEL_RP2040_RELATIVE_PATH}/CMakeLists.txt)
+                get_filename_component(FREERTOS_KERNEL_PATH ${_POSSIBLE_PATH} REALPATH)
+                message("Setting FREERTOS_KERNEL_PATH to '${FREERTOS_KERNEL_PATH}' found relative to enclosing project")
+                break()
+            endif()
+        endforeach()
+        if (FREERTOS_KERNEL_PATH)
+            break()
+        endif()
+    endif()
+
+    # user must have specified
+    if (FREERTOS_KERNEL_PATH)
+        if (EXISTS "${FREERTOS_KERNEL_PATH}/${FREERTOS_KERNEL_RP2040_RELATIVE_PATH}")
+            break()
+        endif()
+    endif()
+endforeach ()
 
 if (NOT FREERTOS_KERNEL_PATH)
     message(FATAL_ERROR "FreeRTOS location was not specified. Please set FREERTOS_KERNEL_PATH.")
@@ -54,8 +84,8 @@ if (NOT EXISTS ${FREERTOS_KERNEL_PATH})
     message(FATAL_ERROR "Directory '${FREERTOS_KERNEL_PATH}' not found")
 endif()
 if (NOT EXISTS ${FREERTOS_KERNEL_PATH}/${FREERTOS_KERNEL_RP2040_RELATIVE_PATH}/CMakeLists.txt)
-    message(FATAL_ERROR "Directory '${FREERTOS_KERNEL_PATH}' does not contain an RP2040 port here: ${FREERTOS_KERNEL_RP2040_RELATIVE_PATH}")
+    message(FATAL_ERROR "Directory '${FREERTOS_KERNEL_PATH}' does not contain a '${PICO_PLATFORM}' port here: ${FREERTOS_KERNEL_RP2040_RELATIVE_PATH}")
 endif()
 set(FREERTOS_KERNEL_PATH ${FREERTOS_KERNEL_PATH} CACHE PATH "Path to the FreeRTOS_KERNEL" FORCE)
 
-add_subdirectory(${FREERTOS_KERNEL_PATH}/${FREERTOS_KERNEL_RP2040_RELATIVE_PATH} FREERTOS_KERNEL)
+add_subdirectory(${FREERTOS_KERNEL_PATH}/${FREERTOS_KERNEL_RP2040_RELATIVE_PATH} FREERTOS_KERNEL)
\ No newline at end of file

From fbaeba352ec22a088b7f88a67430f7c03409e81a Mon Sep 17 00:00:00 2001
From: Sudeep Mohanty <91244425+sudeep-mohanty@users.noreply.github.com>
Date: Mon, 10 Feb 2025 09:17:36 +0100
Subject: [PATCH 384/424] fix(freertos): Correct taskRESERVED_TASK_NAME_LENGTH
 macro definition (#1241)

This commit updates the definition of taskRESERVED_TASK_NAME_LENGTH in
tasks.c to fix an unreachable preprocessor condition.

Signed-off-by: Sudeep Mohanty <sudeep.mohanty@espressif.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
---
 tasks.c | 14 +++++++++-----
 1 file changed, 9 insertions(+), 5 deletions(-)

diff --git a/tasks.c b/tasks.c
index 518c9e87f..783f54810 100644
--- a/tasks.c
+++ b/tasks.c
@@ -156,16 +156,15 @@
     #define configIDLE_TASK_NAME    "IDLE"
 #endif
 
+/* Reserve space for Core ID and null termination. */
 #if ( configNUMBER_OF_CORES > 1 )
-    /* Reserve space for Core ID and null termination. */
+    /* Multi-core systems with up to 9 cores require 1 character for core ID and 1 for null termination. */
     #if ( configMAX_TASK_NAME_LEN < 2U )
         #error Minimum required task name length is 2. Please increase configMAX_TASK_NAME_LEN.
     #endif
     #define taskRESERVED_TASK_NAME_LENGTH    2U
 
-#elif ( configNUMBER_OF_CORES > 9 )
-    #warning Please increase taskRESERVED_TASK_NAME_LENGTH. 1 character is insufficient to store the core ID.
-#else
+#else /* if ( configNUMBER_OF_CORES > 1 ) */
     /* Reserve space for null termination. */
     #if ( configMAX_TASK_NAME_LEN < 1U )
         #error Minimum required task name length is 1. Please increase configMAX_TASK_NAME_LEN.
@@ -3597,7 +3596,12 @@ static BaseType_t prvCreateIdleTasks( void )
          * only one idle task. */
         #if ( configNUMBER_OF_CORES > 1 )
         {
-            /* Append the idle task number to the end of the name. */
+            /* Append the idle task number to the end of the name.
+             *
+             * Note: Idle task name index only supports single-character
+             * core IDs (0-9). If the core ID exceeds 9, the idle task
+             * name will contain an incorrect ASCII character. This is
+             * acceptable as the task name is used mainly for debugging. */
             cIdleName[ xIdleTaskNameIndex ] = ( char ) ( xCoreID + '0' );
             cIdleName[ xIdleTaskNameIndex + 1 ] = '\0';
         }

From 51a1598e4e0281de8b8d54467747af460478eadc Mon Sep 17 00:00:00 2001
From: Bhoomika R S <bhoomrs@amazon.com>
Date: Wed, 12 Feb 2025 14:57:03 +0530
Subject: [PATCH 385/424] Add instruction to suppress SIGUSR1 in Posix with
 LLDB debugger (#1245)

While using the macOS default LLDB debugger, a call to vTaskEndScheduler results in an unhandled SIGUSR1 (aka SIGRESUME) when restoring the scheduler thread's signals with pthread_sigmask. This crashes the program.

Added instructions in portable/ThirdParty/GCC/Posix/port.c to suppress SIGUSR1 to prevent LLDB debugger interference when exiting xPortStartScheduler

Thanks to: @johnboiles for pointing it out in #1224
---
 portable/ThirdParty/GCC/Posix/port.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/portable/ThirdParty/GCC/Posix/port.c b/portable/ThirdParty/GCC/Posix/port.c
index 5dc7f45f8..ff386ac9f 100644
--- a/portable/ThirdParty/GCC/Posix/port.c
+++ b/portable/ThirdParty/GCC/Posix/port.c
@@ -48,6 +48,11 @@
 * stdio (printf() and friends) should be called from a single task
 * only or serialized with a FreeRTOS primitive such as a binary
 * semaphore or mutex.
+* 
+* Note: When using LLDB (the default debugger on macOS) with this port, 
+* suppress SIGUSR1 to prevent debugger interference. This can be
+* done by adding the following line to ~/.lldbinit:
+* `process handle SIGUSR1 -n true -p true -s false`
 *----------------------------------------------------------*/
 #ifdef __linux__
     #define _GNU_SOURCE

From 29e817b70eccb4cb7cf9131ea0484b5b19c3016f Mon Sep 17 00:00:00 2001
From: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Date: Wed, 12 Feb 2025 20:57:18 +0530
Subject: [PATCH 386/424] Include current task runtime in
 ulTaskGetRunTimeCounter (#1234)

* Include current task runtime in ulTaskGetRunTimeCounter

Update ulTaskGetRunTimeCounter to include elapsed time since the last
context switch when called for the currently running task. Previously,
this time was not included in the calculation.

Fixes #1202.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 tasks.c | 88 +++++++++++++++++++++++++++++++++++++++++++++------------
 1 file changed, 70 insertions(+), 18 deletions(-)

diff --git a/tasks.c b/tasks.c
index 783f54810..def843fe6 100644
--- a/tasks.c
+++ b/tasks.c
@@ -6215,7 +6215,7 @@ static void prvCheckTasksWaitingTermination( void )
 
         #if ( configGENERATE_RUN_TIME_STATS == 1 )
         {
-            pxTaskStatus->ulRunTimeCounter = pxTCB->ulRunTimeCounter;
+            pxTaskStatus->ulRunTimeCounter = ulTaskGetRunTimeCounter( xTask );
         }
         #else
         {
@@ -8415,15 +8415,37 @@ TickType_t uxTaskResetEventItemValue( void )
     configRUN_TIME_COUNTER_TYPE ulTaskGetRunTimeCounter( const TaskHandle_t xTask )
     {
         TCB_t * pxTCB;
+        configRUN_TIME_COUNTER_TYPE ulTotalTime = 0, ulTimeSinceLastSwitchedIn = 0, ulTaskRunTime = 0;
 
         traceENTER_ulTaskGetRunTimeCounter( xTask );
 
         pxTCB = prvGetTCBFromHandle( xTask );
         configASSERT( pxTCB != NULL );
 
-        traceRETURN_ulTaskGetRunTimeCounter( pxTCB->ulRunTimeCounter );
+        taskENTER_CRITICAL();
+        {
+            if( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE )
+            {
+                #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
+                    portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalTime );
+                #else
+                    ulTotalTime = portGET_RUN_TIME_COUNTER_VALUE();
+                #endif
 
-        return pxTCB->ulRunTimeCounter;
+                #if ( configNUMBER_OF_CORES == 1 )
+                    ulTimeSinceLastSwitchedIn = ulTotalTime - ulTaskSwitchedInTime[ 0 ];
+                #else
+                    ulTimeSinceLastSwitchedIn = ulTotalTime - ulTaskSwitchedInTime[ pxTCB->xTaskRunState ];
+                #endif
+            }
+
+            ulTaskRunTime = pxTCB->ulRunTimeCounter + ulTimeSinceLastSwitchedIn;
+        }
+        taskEXIT_CRITICAL();
+
+        traceRETURN_ulTaskGetRunTimeCounter( ulTaskRunTime );
+
+        return ulTaskRunTime;
     }
 
 #endif /* if ( configGENERATE_RUN_TIME_STATS == 1 ) */
@@ -8434,11 +8456,17 @@ TickType_t uxTaskResetEventItemValue( void )
     configRUN_TIME_COUNTER_TYPE ulTaskGetRunTimePercent( const TaskHandle_t xTask )
     {
         TCB_t * pxTCB;
-        configRUN_TIME_COUNTER_TYPE ulTotalTime, ulReturn;
+        configRUN_TIME_COUNTER_TYPE ulTotalTime, ulReturn, ulTaskRunTime;
 
         traceENTER_ulTaskGetRunTimePercent( xTask );
 
-        ulTotalTime = ( configRUN_TIME_COUNTER_TYPE ) portGET_RUN_TIME_COUNTER_VALUE();
+        ulTaskRunTime = ulTaskGetRunTimeCounter( xTask );
+
+        #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
+            portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalTime );
+        #else
+            ulTotalTime = ( configRUN_TIME_COUNTER_TYPE ) portGET_RUN_TIME_COUNTER_VALUE();
+        #endif
 
         /* For percentage calculations. */
         ulTotalTime /= ( configRUN_TIME_COUNTER_TYPE ) 100;
@@ -8449,7 +8477,7 @@ TickType_t uxTaskResetEventItemValue( void )
             pxTCB = prvGetTCBFromHandle( xTask );
             configASSERT( pxTCB != NULL );
 
-            ulReturn = pxTCB->ulRunTimeCounter / ulTotalTime;
+            ulReturn = ulTaskRunTime / ulTotalTime;
         }
         else
         {
@@ -8468,19 +8496,42 @@ TickType_t uxTaskResetEventItemValue( void )
 
     configRUN_TIME_COUNTER_TYPE ulTaskGetIdleRunTimeCounter( void )
     {
-        configRUN_TIME_COUNTER_TYPE ulReturn = 0;
+        configRUN_TIME_COUNTER_TYPE ulTotalTime = 0, ulTimeSinceLastSwitchedIn = 0, ulIdleTaskRunTime = 0;
         BaseType_t i;
 
         traceENTER_ulTaskGetIdleRunTimeCounter();
 
-        for( i = 0; i < ( BaseType_t ) configNUMBER_OF_CORES; i++ )
+        taskENTER_CRITICAL();
         {
-            ulReturn += xIdleTaskHandles[ i ]->ulRunTimeCounter;
+            #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
+                portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalTime );
+            #else
+                ulTotalTime = portGET_RUN_TIME_COUNTER_VALUE();
+            #endif
+
+            for( i = 0; i < ( BaseType_t ) configNUMBER_OF_CORES; i++ )
+            {
+                if( taskTASK_IS_RUNNING( xIdleTaskHandles[ i ] ) == pdTRUE )
+                {
+                    #if ( configNUMBER_OF_CORES == 1 )
+                        ulTimeSinceLastSwitchedIn = ulTotalTime - ulTaskSwitchedInTime[ 0 ];
+                    #else
+                        ulTimeSinceLastSwitchedIn = ulTotalTime - ulTaskSwitchedInTime[ xIdleTaskHandles[ i ]->xTaskRunState ];
+                    #endif
+                }
+                else
+                {
+                    ulTimeSinceLastSwitchedIn = 0;
+                }
+
+                ulIdleTaskRunTime += ( xIdleTaskHandles[ i ]->ulRunTimeCounter + ulTimeSinceLastSwitchedIn );
+            }
         }
+        taskEXIT_CRITICAL();
 
-        traceRETURN_ulTaskGetIdleRunTimeCounter( ulReturn );
+        traceRETURN_ulTaskGetIdleRunTimeCounter( ulIdleTaskRunTime );
 
-        return ulReturn;
+        return ulIdleTaskRunTime;
     }
 
 #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
@@ -8492,11 +8543,16 @@ TickType_t uxTaskResetEventItemValue( void )
     {
         configRUN_TIME_COUNTER_TYPE ulTotalTime, ulReturn;
         configRUN_TIME_COUNTER_TYPE ulRunTimeCounter = 0;
-        BaseType_t i;
 
         traceENTER_ulTaskGetIdleRunTimePercent();
 
-        ulTotalTime = portGET_RUN_TIME_COUNTER_VALUE() * configNUMBER_OF_CORES;
+        #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
+            portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalTime );
+        #else
+            ulTotalTime = ( configRUN_TIME_COUNTER_TYPE ) portGET_RUN_TIME_COUNTER_VALUE();
+        #endif
+
+        ulTotalTime *= configNUMBER_OF_CORES;
 
         /* For percentage calculations. */
         ulTotalTime /= ( configRUN_TIME_COUNTER_TYPE ) 100;
@@ -8504,11 +8560,7 @@ TickType_t uxTaskResetEventItemValue( void )
         /* Avoid divide by zero errors. */
         if( ulTotalTime > ( configRUN_TIME_COUNTER_TYPE ) 0 )
         {
-            for( i = 0; i < ( BaseType_t ) configNUMBER_OF_CORES; i++ )
-            {
-                ulRunTimeCounter += xIdleTaskHandles[ i ]->ulRunTimeCounter;
-            }
-
+            ulRunTimeCounter = ulTaskGetIdleRunTimeCounter();
             ulReturn = ulRunTimeCounter / ulTotalTime;
         }
         else

From 15ec8b8995d90c07605bd25a017ff1669f288bca Mon Sep 17 00:00:00 2001
From: John Boiles <johnaboiles@gmail.com>
Date: Wed, 12 Feb 2025 21:14:22 -0800
Subject: [PATCH 387/424] POSIX Simulator: Assert if vPortYield called from a
 non-FreeRTOS thread (#1247)

---
 portable/ThirdParty/GCC/Posix/port.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/portable/ThirdParty/GCC/Posix/port.c b/portable/ThirdParty/GCC/Posix/port.c
index ff386ac9f..1153e7f67 100644
--- a/portable/ThirdParty/GCC/Posix/port.c
+++ b/portable/ThirdParty/GCC/Posix/port.c
@@ -384,6 +384,10 @@ static void prvPortYieldFromISR( void )
 
 void vPortYield( void )
 {
+    /* This must never be called from outside of a FreeRTOS-owned thread, or
+     * the thread could get stuck in a suspended state. */
+    configASSERT( prvIsFreeRTOSThread() == pdTRUE );
+
     vPortEnterCritical();
 
     prvPortYieldFromISR();

From 1a1ae36f9aa4e3c474e55d6404238898003dfc47 Mon Sep 17 00:00:00 2001
From: Bhoomika R S <bhoomrs@amazon.com>
Date: Thu, 13 Feb 2025 15:03:23 +0530
Subject: [PATCH 388/424] Update instruction to suppress SIGUSR1 in Posix with
 LLDB debugger (#1248)

---
 portable/ThirdParty/GCC/Posix/port.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/portable/ThirdParty/GCC/Posix/port.c b/portable/ThirdParty/GCC/Posix/port.c
index 1153e7f67..dd7ca1a9a 100644
--- a/portable/ThirdParty/GCC/Posix/port.c
+++ b/portable/ThirdParty/GCC/Posix/port.c
@@ -52,7 +52,7 @@
 * Note: When using LLDB (the default debugger on macOS) with this port, 
 * suppress SIGUSR1 to prevent debugger interference. This can be
 * done by adding the following line to ~/.lldbinit:
-* `process handle SIGUSR1 -n true -p true -s false`
+* `process handle SIGUSR1 -n true -p false -s false`
 *----------------------------------------------------------*/
 #ifdef __linux__
     #define _GNU_SOURCE

From df0aa5a815ad5c6c4ecdc108dadc5c1832c79bde Mon Sep 17 00:00:00 2001
From: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Date: Mon, 24 Feb 2025 21:54:15 +0530
Subject: [PATCH 389/424] Disable stack overflow check for MPU ports (#1231)

Disable stack overflow check for MPU ports

Stack overflow check is not straight forward to implement for MPU ports
because of the following reasons:
1. The context is stroed in TCB and as a result, pxTopOfStack member
   points to the context location in TCB.
2. System calls are executed on a separate privileged only stack.

It is still okay because an MPU region is used to protect task stack
which means task stack overflow will trigger an MPU fault.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 include/portable.h                            |  4 -
 include/stack_macros.h                        | 81 ++++++++++---------
 portable/ARMv8M/non_secure/portmacrocommon.h  |  5 --
 .../GCC/ARM_CM23/non_secure/portmacrocommon.h |  5 --
 .../ARM_CM23_NTZ/non_secure/portmacrocommon.h |  5 --
 .../GCC/ARM_CM33/non_secure/portmacrocommon.h |  5 --
 .../ARM_CM33_NTZ/non_secure/portmacrocommon.h |  5 --
 .../ARM_CM35P/non_secure/portmacrocommon.h    |  5 --
 .../non_secure/portmacrocommon.h              |  5 --
 .../GCC/ARM_CM55/non_secure/portmacrocommon.h |  5 --
 .../ARM_CM55_NTZ/non_secure/portmacrocommon.h |  5 --
 .../GCC/ARM_CM85/non_secure/portmacrocommon.h |  5 --
 .../ARM_CM85_NTZ/non_secure/portmacrocommon.h |  5 --
 .../IAR/ARM_CM23/non_secure/portmacrocommon.h |  5 --
 .../ARM_CM23_NTZ/non_secure/portmacrocommon.h |  5 --
 .../IAR/ARM_CM33/non_secure/portmacrocommon.h |  5 --
 .../ARM_CM33_NTZ/non_secure/portmacrocommon.h |  5 --
 .../ARM_CM35P/non_secure/portmacrocommon.h    |  5 --
 .../non_secure/portmacrocommon.h              |  5 --
 .../IAR/ARM_CM55/non_secure/portmacrocommon.h |  5 --
 .../ARM_CM55_NTZ/non_secure/portmacrocommon.h |  5 --
 .../IAR/ARM_CM85/non_secure/portmacrocommon.h |  5 --
 .../ARM_CM85_NTZ/non_secure/portmacrocommon.h |  5 --
 23 files changed, 41 insertions(+), 149 deletions(-)

diff --git a/include/portable.h b/include/portable.h
index c9b744535..68e11e793 100644
--- a/include/portable.h
+++ b/include/portable.h
@@ -93,10 +93,6 @@
     #define portBASE_TYPE_EXIT_CRITICAL()    taskEXIT_CRITICAL()
 #endif
 
-#ifndef portGET_CURRENT_TOP_OF_STACK
-    #define portGET_CURRENT_TOP_OF_STACK( pxCurrentTopOfStack )    { pxCurrentTopOfStack = ( StackType_t * ) pxCurrentTCB->pxTopOfStack; }
-#endif
-
 #ifndef configSTACK_DEPTH_TYPE
     #define configSTACK_DEPTH_TYPE    StackType_t
 #endif
diff --git a/include/stack_macros.h b/include/stack_macros.h
index 300be4cb3..6d0117722 100644
--- a/include/stack_macros.h
+++ b/include/stack_macros.h
@@ -53,17 +53,25 @@
     #define portSTACK_LIMIT_PADDING    0
 #endif
 
-#if ( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH < 0 ) )
+/* Stack overflow check is not straight forward to implement for MPU ports
+ * because of the following reasons:
+ * 1. The context is stored in TCB and as a result, pxTopOfStack member points
+ *    to the context location in TCB.
+ * 2. System calls are executed on a separate privileged only stack.
+ *
+ * It is still okay because an MPU region is used to protect task stack which
+ * means task stack overflow will trigger an MPU fault for unprivileged tasks.
+ * Additionally, architectures with hardware stack overflow checking support
+ * (such as Armv8-M) will trigger a fault when a task's stack overflows.
+ */
+#if ( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH < 0 ) && ( portUSING_MPU_WRAPPERS != 1 ) )
 
 /* Only the current stack state is to be checked. */
     #define taskCHECK_FOR_STACK_OVERFLOW()                                                      \
     do                                                                                          \
     {                                                                                           \
-        StackType_t * pxCurrentTopOfStack;                                                      \
-        portGET_CURRENT_TOP_OF_STACK( pxCurrentTopOfStack );                                    \
-                                                                                                \
         /* Is the currently saved stack pointer within the stack limit? */                      \
-        if( pxCurrentTopOfStack <= pxCurrentTCB->pxStack + portSTACK_LIMIT_PADDING )            \
+        if( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack + portSTACK_LIMIT_PADDING )     \
         {                                                                                       \
             char * pcOverflowTaskName = pxCurrentTCB->pcTaskName;                               \
             vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pcOverflowTaskName ); \
@@ -73,51 +81,46 @@
 #endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
 /*-----------------------------------------------------------*/
 
-#if ( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH > 0 ) )
+#if ( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH > 0 ) && ( portUSING_MPU_WRAPPERS != 1 ) )
 
 /* Only the current stack state is to be checked. */
-    #define taskCHECK_FOR_STACK_OVERFLOW()                                                      \
-    do                                                                                          \
-    {                                                                                           \
-        StackType_t * pxCurrentTopOfStack;                                                      \
-        portGET_CURRENT_TOP_OF_STACK( pxCurrentTopOfStack );                                    \
-                                                                                                \
-        /* Is the currently saved stack pointer within the stack limit? */                      \
-        if( pxCurrentTopOfStack >= pxCurrentTCB->pxEndOfStack - portSTACK_LIMIT_PADDING )       \
-        {                                                                                       \
-            char * pcOverflowTaskName = pxCurrentTCB->pcTaskName;                               \
-            vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pcOverflowTaskName ); \
-        }                                                                                       \
+    #define taskCHECK_FOR_STACK_OVERFLOW()                                                       \
+    do                                                                                           \
+    {                                                                                            \
+        /* Is the currently saved stack pointer within the stack limit? */                       \
+        if( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack - portSTACK_LIMIT_PADDING ) \
+        {                                                                                        \
+            char * pcOverflowTaskName = pxCurrentTCB->pcTaskName;                                \
+            vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pcOverflowTaskName );  \
+        }                                                                                        \
     } while( 0 )
 
 #endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
 /*-----------------------------------------------------------*/
 
-#if ( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) )
+#if ( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) && ( portUSING_MPU_WRAPPERS != 1 ) )
 
-    #define taskCHECK_FOR_STACK_OVERFLOW()                                                      \
-    do                                                                                          \
-    {                                                                                           \
-        const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack;                 \
-        const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5U;                                 \
-        StackType_t * pxCurrentTopOfStack;                                                      \
-        portGET_CURRENT_TOP_OF_STACK( pxCurrentTopOfStack );                                    \
-                                                                                                \
-        if( ( pxCurrentTopOfStack <= pxCurrentTCB->pxStack + portSTACK_LIMIT_PADDING ) ||       \
-            ( pulStack[ 0 ] != ulCheckValue ) ||                                                \
-            ( pulStack[ 1 ] != ulCheckValue ) ||                                                \
-            ( pulStack[ 2 ] != ulCheckValue ) ||                                                \
-            ( pulStack[ 3 ] != ulCheckValue ) )                                                 \
-        {                                                                                       \
-            char * pcOverflowTaskName = pxCurrentTCB->pcTaskName;                               \
-            vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pcOverflowTaskName ); \
-        }                                                                                       \
+    #define taskCHECK_FOR_STACK_OVERFLOW()                                                       \
+    do                                                                                           \
+    {                                                                                            \
+        const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack;                  \
+        const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5U;                                  \
+                                                                                                 \
+        if( ( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack + portSTACK_LIMIT_PADDING ) || \
+            ( pulStack[ 0 ] != ulCheckValue ) ||                                                 \
+            ( pulStack[ 1 ] != ulCheckValue ) ||                                                 \
+            ( pulStack[ 2 ] != ulCheckValue ) ||                                                 \
+            ( pulStack[ 3 ] != ulCheckValue ) )                                                  \
+        {                                                                                        \
+            char * pcOverflowTaskName = pxCurrentTCB->pcTaskName;                                \
+            vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pcOverflowTaskName );  \
+        }                                                                                        \
     } while( 0 )
 
 #endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) )
+#if ( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) && ( portUSING_MPU_WRAPPERS != 1 ) )
 
     #define taskCHECK_FOR_STACK_OVERFLOW()                                                                                                \
     do                                                                                                                                    \
@@ -128,12 +131,10 @@
                                                         tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,   \
                                                         tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,   \
                                                         tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE }; \
-        StackType_t * pxCurrentTopOfStack;                                                                                                \
-        portGET_CURRENT_TOP_OF_STACK( pxCurrentTopOfStack );                                                                              \
                                                                                                                                           \
         pcEndOfStack -= sizeof( ucExpectedStackBytes );                                                                                   \
                                                                                                                                           \
-        if( ( pxCurrentTopOfStack >= pxCurrentTCB->pxEndOfStack - portSTACK_LIMIT_PADDING ) ||                                            \
+        if( ( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack - portSTACK_LIMIT_PADDING ) ||                                     \
             ( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 ) )                 \
         {                                                                                                                                 \
             char * pcOverflowTaskName = pxCurrentTCB->pcTaskName;                                                                         \
diff --git a/portable/ARMv8M/non_secure/portmacrocommon.h b/portable/ARMv8M/non_secure/portmacrocommon.h
index ec14d467d..f373bcad5 100644
--- a/portable/ARMv8M/non_secure/portmacrocommon.h
+++ b/portable/ARMv8M/non_secure/portmacrocommon.h
@@ -217,11 +217,6 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-        /* When MPU wrapper v2 is used, the task's context is stored in TCB and
-         * pxTopOfStack member of TCB points to the context location in TCB. We,
-         * therefore, need to read PSP to find the task's current top of stack. */
-        #define portGET_CURRENT_TOP_OF_STACK( pxCurrentTopOfStack ) { __asm volatile ( "mrs %0, psp"  : "=r" ( pxCurrentTopOfStack ) ); }
-
         /**
          * @brief System call stack.
          */
diff --git a/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h
index ec14d467d..f373bcad5 100644
--- a/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h
@@ -217,11 +217,6 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-        /* When MPU wrapper v2 is used, the task's context is stored in TCB and
-         * pxTopOfStack member of TCB points to the context location in TCB. We,
-         * therefore, need to read PSP to find the task's current top of stack. */
-        #define portGET_CURRENT_TOP_OF_STACK( pxCurrentTopOfStack ) { __asm volatile ( "mrs %0, psp"  : "=r" ( pxCurrentTopOfStack ) ); }
-
         /**
          * @brief System call stack.
          */
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h
index ec14d467d..f373bcad5 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h
@@ -217,11 +217,6 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-        /* When MPU wrapper v2 is used, the task's context is stored in TCB and
-         * pxTopOfStack member of TCB points to the context location in TCB. We,
-         * therefore, need to read PSP to find the task's current top of stack. */
-        #define portGET_CURRENT_TOP_OF_STACK( pxCurrentTopOfStack ) { __asm volatile ( "mrs %0, psp"  : "=r" ( pxCurrentTopOfStack ) ); }
-
         /**
          * @brief System call stack.
          */
diff --git a/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h
index ec14d467d..f373bcad5 100644
--- a/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h
@@ -217,11 +217,6 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-        /* When MPU wrapper v2 is used, the task's context is stored in TCB and
-         * pxTopOfStack member of TCB points to the context location in TCB. We,
-         * therefore, need to read PSP to find the task's current top of stack. */
-        #define portGET_CURRENT_TOP_OF_STACK( pxCurrentTopOfStack ) { __asm volatile ( "mrs %0, psp"  : "=r" ( pxCurrentTopOfStack ) ); }
-
         /**
          * @brief System call stack.
          */
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h
index ec14d467d..f373bcad5 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h
@@ -217,11 +217,6 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-        /* When MPU wrapper v2 is used, the task's context is stored in TCB and
-         * pxTopOfStack member of TCB points to the context location in TCB. We,
-         * therefore, need to read PSP to find the task's current top of stack. */
-        #define portGET_CURRENT_TOP_OF_STACK( pxCurrentTopOfStack ) { __asm volatile ( "mrs %0, psp"  : "=r" ( pxCurrentTopOfStack ) ); }
-
         /**
          * @brief System call stack.
          */
diff --git a/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h
index ec14d467d..f373bcad5 100644
--- a/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h
@@ -217,11 +217,6 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-        /* When MPU wrapper v2 is used, the task's context is stored in TCB and
-         * pxTopOfStack member of TCB points to the context location in TCB. We,
-         * therefore, need to read PSP to find the task's current top of stack. */
-        #define portGET_CURRENT_TOP_OF_STACK( pxCurrentTopOfStack ) { __asm volatile ( "mrs %0, psp"  : "=r" ( pxCurrentTopOfStack ) ); }
-
         /**
          * @brief System call stack.
          */
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
index ec14d467d..f373bcad5 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
@@ -217,11 +217,6 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-        /* When MPU wrapper v2 is used, the task's context is stored in TCB and
-         * pxTopOfStack member of TCB points to the context location in TCB. We,
-         * therefore, need to read PSP to find the task's current top of stack. */
-        #define portGET_CURRENT_TOP_OF_STACK( pxCurrentTopOfStack ) { __asm volatile ( "mrs %0, psp"  : "=r" ( pxCurrentTopOfStack ) ); }
-
         /**
          * @brief System call stack.
          */
diff --git a/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h
index ec14d467d..f373bcad5 100644
--- a/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h
@@ -217,11 +217,6 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-        /* When MPU wrapper v2 is used, the task's context is stored in TCB and
-         * pxTopOfStack member of TCB points to the context location in TCB. We,
-         * therefore, need to read PSP to find the task's current top of stack. */
-        #define portGET_CURRENT_TOP_OF_STACK( pxCurrentTopOfStack ) { __asm volatile ( "mrs %0, psp"  : "=r" ( pxCurrentTopOfStack ) ); }
-
         /**
          * @brief System call stack.
          */
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h
index ec14d467d..f373bcad5 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h
@@ -217,11 +217,6 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-        /* When MPU wrapper v2 is used, the task's context is stored in TCB and
-         * pxTopOfStack member of TCB points to the context location in TCB. We,
-         * therefore, need to read PSP to find the task's current top of stack. */
-        #define portGET_CURRENT_TOP_OF_STACK( pxCurrentTopOfStack ) { __asm volatile ( "mrs %0, psp"  : "=r" ( pxCurrentTopOfStack ) ); }
-
         /**
          * @brief System call stack.
          */
diff --git a/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h
index ec14d467d..f373bcad5 100644
--- a/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h
@@ -217,11 +217,6 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-        /* When MPU wrapper v2 is used, the task's context is stored in TCB and
-         * pxTopOfStack member of TCB points to the context location in TCB. We,
-         * therefore, need to read PSP to find the task's current top of stack. */
-        #define portGET_CURRENT_TOP_OF_STACK( pxCurrentTopOfStack ) { __asm volatile ( "mrs %0, psp"  : "=r" ( pxCurrentTopOfStack ) ); }
-
         /**
          * @brief System call stack.
          */
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h
index ec14d467d..f373bcad5 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h
@@ -217,11 +217,6 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-        /* When MPU wrapper v2 is used, the task's context is stored in TCB and
-         * pxTopOfStack member of TCB points to the context location in TCB. We,
-         * therefore, need to read PSP to find the task's current top of stack. */
-        #define portGET_CURRENT_TOP_OF_STACK( pxCurrentTopOfStack ) { __asm volatile ( "mrs %0, psp"  : "=r" ( pxCurrentTopOfStack ) ); }
-
         /**
          * @brief System call stack.
          */
diff --git a/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h
index ec14d467d..f373bcad5 100644
--- a/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h
@@ -217,11 +217,6 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-        /* When MPU wrapper v2 is used, the task's context is stored in TCB and
-         * pxTopOfStack member of TCB points to the context location in TCB. We,
-         * therefore, need to read PSP to find the task's current top of stack. */
-        #define portGET_CURRENT_TOP_OF_STACK( pxCurrentTopOfStack ) { __asm volatile ( "mrs %0, psp"  : "=r" ( pxCurrentTopOfStack ) ); }
-
         /**
          * @brief System call stack.
          */
diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h
index ec14d467d..f373bcad5 100644
--- a/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h
@@ -217,11 +217,6 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-        /* When MPU wrapper v2 is used, the task's context is stored in TCB and
-         * pxTopOfStack member of TCB points to the context location in TCB. We,
-         * therefore, need to read PSP to find the task's current top of stack. */
-        #define portGET_CURRENT_TOP_OF_STACK( pxCurrentTopOfStack ) { __asm volatile ( "mrs %0, psp"  : "=r" ( pxCurrentTopOfStack ) ); }
-
         /**
          * @brief System call stack.
          */
diff --git a/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h
index ec14d467d..f373bcad5 100644
--- a/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h
@@ -217,11 +217,6 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-        /* When MPU wrapper v2 is used, the task's context is stored in TCB and
-         * pxTopOfStack member of TCB points to the context location in TCB. We,
-         * therefore, need to read PSP to find the task's current top of stack. */
-        #define portGET_CURRENT_TOP_OF_STACK( pxCurrentTopOfStack ) { __asm volatile ( "mrs %0, psp"  : "=r" ( pxCurrentTopOfStack ) ); }
-
         /**
          * @brief System call stack.
          */
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h
index ec14d467d..f373bcad5 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h
@@ -217,11 +217,6 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-        /* When MPU wrapper v2 is used, the task's context is stored in TCB and
-         * pxTopOfStack member of TCB points to the context location in TCB. We,
-         * therefore, need to read PSP to find the task's current top of stack. */
-        #define portGET_CURRENT_TOP_OF_STACK( pxCurrentTopOfStack ) { __asm volatile ( "mrs %0, psp"  : "=r" ( pxCurrentTopOfStack ) ); }
-
         /**
          * @brief System call stack.
          */
diff --git a/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h
index ec14d467d..f373bcad5 100644
--- a/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h
@@ -217,11 +217,6 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-        /* When MPU wrapper v2 is used, the task's context is stored in TCB and
-         * pxTopOfStack member of TCB points to the context location in TCB. We,
-         * therefore, need to read PSP to find the task's current top of stack. */
-        #define portGET_CURRENT_TOP_OF_STACK( pxCurrentTopOfStack ) { __asm volatile ( "mrs %0, psp"  : "=r" ( pxCurrentTopOfStack ) ); }
-
         /**
          * @brief System call stack.
          */
diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
index ec14d467d..f373bcad5 100644
--- a/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h
@@ -217,11 +217,6 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-        /* When MPU wrapper v2 is used, the task's context is stored in TCB and
-         * pxTopOfStack member of TCB points to the context location in TCB. We,
-         * therefore, need to read PSP to find the task's current top of stack. */
-        #define portGET_CURRENT_TOP_OF_STACK( pxCurrentTopOfStack ) { __asm volatile ( "mrs %0, psp"  : "=r" ( pxCurrentTopOfStack ) ); }
-
         /**
          * @brief System call stack.
          */
diff --git a/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h
index ec14d467d..f373bcad5 100644
--- a/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h
@@ -217,11 +217,6 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-        /* When MPU wrapper v2 is used, the task's context is stored in TCB and
-         * pxTopOfStack member of TCB points to the context location in TCB. We,
-         * therefore, need to read PSP to find the task's current top of stack. */
-        #define portGET_CURRENT_TOP_OF_STACK( pxCurrentTopOfStack ) { __asm volatile ( "mrs %0, psp"  : "=r" ( pxCurrentTopOfStack ) ); }
-
         /**
          * @brief System call stack.
          */
diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h
index ec14d467d..f373bcad5 100644
--- a/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h
@@ -217,11 +217,6 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-        /* When MPU wrapper v2 is used, the task's context is stored in TCB and
-         * pxTopOfStack member of TCB points to the context location in TCB. We,
-         * therefore, need to read PSP to find the task's current top of stack. */
-        #define portGET_CURRENT_TOP_OF_STACK( pxCurrentTopOfStack ) { __asm volatile ( "mrs %0, psp"  : "=r" ( pxCurrentTopOfStack ) ); }
-
         /**
          * @brief System call stack.
          */
diff --git a/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h
index ec14d467d..f373bcad5 100644
--- a/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h
@@ -217,11 +217,6 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-        /* When MPU wrapper v2 is used, the task's context is stored in TCB and
-         * pxTopOfStack member of TCB points to the context location in TCB. We,
-         * therefore, need to read PSP to find the task's current top of stack. */
-        #define portGET_CURRENT_TOP_OF_STACK( pxCurrentTopOfStack ) { __asm volatile ( "mrs %0, psp"  : "=r" ( pxCurrentTopOfStack ) ); }
-
         /**
          * @brief System call stack.
          */
diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h
index ec14d467d..f373bcad5 100644
--- a/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h
+++ b/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h
@@ -217,11 +217,6 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
             #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
         #endif
 
-        /* When MPU wrapper v2 is used, the task's context is stored in TCB and
-         * pxTopOfStack member of TCB points to the context location in TCB. We,
-         * therefore, need to read PSP to find the task's current top of stack. */
-        #define portGET_CURRENT_TOP_OF_STACK( pxCurrentTopOfStack ) { __asm volatile ( "mrs %0, psp"  : "=r" ( pxCurrentTopOfStack ) ); }
-
         /**
          * @brief System call stack.
          */

From 3fd7f174db4b2ed968b47a78d615bfe6cb4d3bd7 Mon Sep 17 00:00:00 2001
From: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Date: Fri, 28 Feb 2025 17:10:08 +0530
Subject: [PATCH 390/424] Fix MISRA violations for Kernel release V11.2.0
 (#1251)

* Fix MISRA violations for Kernel release V11.2.0

* Fix formatting

* Remove redundant configASSERT in timers.c
---
 MISRA.md                                |   4 +-
 examples/coverity/coverity_misra.config |   4 +
 queue.c                                 |   5 +-
 tasks.c                                 |  10 +-
 timers.c                                | 219 ++++++++++++------------
 5 files changed, 126 insertions(+), 116 deletions(-)

diff --git a/MISRA.md b/MISRA.md
index b5941037f..87ff4cbcd 100644
--- a/MISRA.md
+++ b/MISRA.md
@@ -120,8 +120,8 @@ _Ref 11.5.5_
 MISRA C-2012 Rule 14.3: Controlling expressions shall not be invariant.
 
 _Ref 14.3_
- - The `configMAX_TASK_NAME_LEN` and `taskRESERVED_TASK_NAME_LENGTH` are
-   evaluated to constants at compile time and may vary based on the build
+ - The `configMAX_TASK_NAME_LEN` , `taskRESERVED_TASK_NAME_LENGTH` and `SIZE_MAX`
+   are evaluated to constants at compile time and may vary based on the build
    configuration.
 
 #### Rule 18.1
diff --git a/examples/coverity/coverity_misra.config b/examples/coverity/coverity_misra.config
index d80ddb553..631142806 100644
--- a/examples/coverity/coverity_misra.config
+++ b/examples/coverity/coverity_misra.config
@@ -3,6 +3,10 @@
     "standard" : "c2012",
     "title": "Coverity MISRA Configuration",
     "deviations" : [
+        {
+            "deviation": "Rule 1.2",
+            "reason": "Allow use of __attribute__ for necessary functions placement in specific memory regions."
+        },
         {
             "deviation": "Rule 3.1",
             "reason": "We post HTTP links in code comments which contain // inside comments blocks."
diff --git a/queue.c b/queue.c
index 688fb3113..e91d9e39b 100644
--- a/queue.c
+++ b/queue.c
@@ -513,7 +513,10 @@ BaseType_t xQueueGenericReset( QueueHandle_t xQueue,
             /* Check for multiplication overflow. */
             ( ( SIZE_MAX / uxQueueLength ) >= uxItemSize ) &&
             /* Check for addition overflow. */
-            ( ( SIZE_MAX - sizeof( Queue_t ) ) >= ( size_t ) ( uxQueueLength * uxItemSize ) ) )
+            /* MISRA Ref 14.3.1 [Configuration dependent invariant] */
+            /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-143. */
+            /* coverity[misra_c_2012_rule_14_3_violation] */
+            ( ( SIZE_MAX - sizeof( Queue_t ) ) >= ( size_t ) ( ( size_t ) uxQueueLength * ( size_t ) uxItemSize ) ) )
         {
             /* Allocate enough space to hold the maximum number of items that
              * can be in the queue at any time.  It is valid for uxItemSize to be
diff --git a/tasks.c b/tasks.c
index def843fe6..24cfb2620 100644
--- a/tasks.c
+++ b/tasks.c
@@ -2016,7 +2016,7 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
         pxNewTCB->xTaskRunState = taskTASK_NOT_RUNNING;
 
         /* Is this an idle task? */
-        if( ( ( TaskFunction_t ) pxTaskCode == ( TaskFunction_t ) prvIdleTask ) || ( ( TaskFunction_t ) pxTaskCode == ( TaskFunction_t ) prvPassiveIdleTask ) )
+        if( ( ( TaskFunction_t ) pxTaskCode == ( TaskFunction_t ) ( &prvIdleTask ) ) || ( ( TaskFunction_t ) pxTaskCode == ( TaskFunction_t ) ( &prvPassiveIdleTask ) ) )
         {
             pxNewTCB->uxTaskAttributes |= taskATTRIBUTE_IS_IDLE;
         }
@@ -3573,7 +3573,7 @@ static BaseType_t prvCreateIdleTasks( void )
     {
         #if ( configNUMBER_OF_CORES == 1 )
         {
-            pxIdleTaskFunction = prvIdleTask;
+            pxIdleTaskFunction = &prvIdleTask;
         }
         #else /* #if (  configNUMBER_OF_CORES == 1 ) */
         {
@@ -3582,11 +3582,11 @@ static BaseType_t prvCreateIdleTasks( void )
              * run when no other task is available to run. */
             if( xCoreID == 0 )
             {
-                pxIdleTaskFunction = prvIdleTask;
+                pxIdleTaskFunction = &prvIdleTask;
             }
             else
             {
-                pxIdleTaskFunction = prvPassiveIdleTask;
+                pxIdleTaskFunction = &prvPassiveIdleTask;
             }
         }
         #endif /* #if (  configNUMBER_OF_CORES == 1 ) */
@@ -3603,7 +3603,7 @@ static BaseType_t prvCreateIdleTasks( void )
              * name will contain an incorrect ASCII character. This is
              * acceptable as the task name is used mainly for debugging. */
             cIdleName[ xIdleTaskNameIndex ] = ( char ) ( xCoreID + '0' );
-            cIdleName[ xIdleTaskNameIndex + 1 ] = '\0';
+            cIdleName[ xIdleTaskNameIndex + 1U ] = '\0';
         }
         #endif /* if ( configNUMBER_OF_CORES > 1 ) */
 
diff --git a/timers.c b/timers.c
index 03765fe7b..1bc40bc46 100644
--- a/timers.c
+++ b/timers.c
@@ -257,7 +257,7 @@
                     configSTACK_DEPTH_TYPE uxTimerTaskStackSize;
 
                     vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &uxTimerTaskStackSize );
-                    xTimerTaskHandle = xTaskCreateStaticAffinitySet( prvTimerTask,
+                    xTimerTaskHandle = xTaskCreateStaticAffinitySet( &prvTimerTask,
                                                                      configTIMER_SERVICE_TASK_NAME,
                                                                      uxTimerTaskStackSize,
                                                                      NULL,
@@ -273,7 +273,7 @@
                 }
                 #else /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
                 {
-                    xReturn = xTaskCreateAffinitySet( prvTimerTask,
+                    xReturn = xTaskCreateAffinitySet( &prvTimerTask,
                                                       configTIMER_SERVICE_TASK_NAME,
                                                       configTIMER_TASK_STACK_DEPTH,
                                                       NULL,
@@ -292,7 +292,7 @@
                     configSTACK_DEPTH_TYPE uxTimerTaskStackSize;
 
                     vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &uxTimerTaskStackSize );
-                    xTimerTaskHandle = xTaskCreateStatic( prvTimerTask,
+                    xTimerTaskHandle = xTaskCreateStatic( &prvTimerTask,
                                                           configTIMER_SERVICE_TASK_NAME,
                                                           uxTimerTaskStackSize,
                                                           NULL,
@@ -307,7 +307,7 @@
                 }
                 #else /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
                 {
-                    xReturn = xTaskCreate( prvTimerTask,
+                    xReturn = xTaskCreate( &prvTimerTask,
                                            configTIMER_SERVICE_TASK_NAME,
                                            configTIMER_TASK_STACK_DEPTH,
                                            NULL,
@@ -458,11 +458,9 @@
 
         traceENTER_xTimerGenericCommandFromTask( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait );
 
-        configASSERT( xTimer );
-
         /* Send a message to the timer service task to perform a particular action
          * on a particular timer definition. */
-        if( xTimerQueue != NULL )
+        if( ( xTimerQueue != NULL ) && ( xTimer != NULL ) )
         {
             /* Send a command to the timer service task to start the xTimer timer. */
             xMessage.xMessageID = xCommandID;
@@ -509,11 +507,9 @@
 
         traceENTER_xTimerGenericCommandFromISR( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait );
 
-        configASSERT( xTimer );
-
         /* Send a message to the timer service task to perform a particular action
          * on a particular timer definition. */
-        if( xTimerQueue != NULL )
+        if( ( xTimerQueue != NULL ) && ( xTimer != NULL ) )
         {
             /* Send a command to the timer service task to start the xTimer timer. */
             xMessage.xMessageID = xCommandID;
@@ -974,110 +970,117 @@
                  * software timer. */
                 pxTimer = xMessage.u.xTimerParameters.pxTimer;
 
-                if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE )
+                if( pxTimer != NULL )
                 {
-                    /* The timer is in a list, remove it. */
-                    ( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
+                    if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE )
+                    {
+                        /* The timer is in a list, remove it. */
+                        ( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+
+                    traceTIMER_COMMAND_RECEIVED( pxTimer, xMessage.xMessageID, xMessage.u.xTimerParameters.xMessageValue );
+
+                    /* In this case the xTimerListsWereSwitched parameter is not used, but
+                     *  it must be present in the function call.  prvSampleTimeNow() must be
+                     *  called after the message is received from xTimerQueue so there is no
+                     *  possibility of a higher priority task adding a message to the message
+                     *  queue with a time that is ahead of the timer daemon task (because it
+                     *  pre-empted the timer daemon task after the xTimeNow value was set). */
+                    xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
+
+                    switch( xMessage.xMessageID )
+                    {
+                        case tmrCOMMAND_START:
+                        case tmrCOMMAND_START_FROM_ISR:
+                        case tmrCOMMAND_RESET:
+                        case tmrCOMMAND_RESET_FROM_ISR:
+                            /* Start or restart a timer. */
+                            pxTimer->ucStatus |= ( uint8_t ) tmrSTATUS_IS_ACTIVE;
+
+                            if( prvInsertTimerInActiveList( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE )
+                            {
+                                /* The timer expired before it was added to the active
+                                 * timer list.  Process it now. */
+                                if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0U )
+                                {
+                                    prvReloadTimer( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow );
+                                }
+                                else
+                                {
+                                    pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE );
+                                }
+
+                                /* Call the timer callback. */
+                                traceTIMER_EXPIRED( pxTimer );
+                                pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
+                            }
+                            else
+                            {
+                                mtCOVERAGE_TEST_MARKER();
+                            }
+
+                            break;
+
+                        case tmrCOMMAND_STOP:
+                        case tmrCOMMAND_STOP_FROM_ISR:
+                            /* The timer has already been removed from the active list. */
+                            pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE );
+                            break;
+
+                        case tmrCOMMAND_CHANGE_PERIOD:
+                        case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR:
+                            pxTimer->ucStatus |= ( uint8_t ) tmrSTATUS_IS_ACTIVE;
+                            pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue;
+                            configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) );
+
+                            /* The new period does not really have a reference, and can
+                             * be longer or shorter than the old one.  The command time is
+                             * therefore set to the current time, and as the period cannot
+                             * be zero the next expiry time can only be in the future,
+                             * meaning (unlike for the xTimerStart() case above) there is
+                             * no fail case that needs to be handled here. */
+                            ( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow );
+                            break;
+
+                        case tmrCOMMAND_DELETE:
+                            #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+                            {
+                                /* The timer has already been removed from the active list,
+                                 * just free up the memory if the memory was dynamically
+                                 * allocated. */
+                                if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 )
+                                {
+                                    vPortFree( pxTimer );
+                                }
+                                else
+                                {
+                                    pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE );
+                                }
+                            }
+                            #else /* if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) */
+                            {
+                                /* If dynamic allocation is not enabled, the memory
+                                 * could not have been dynamically allocated. So there is
+                                 * no need to free the memory - just mark the timer as
+                                 * "not active". */
+                                pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE );
+                            }
+                            #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+                            break;
+
+                        default:
+                            /* Don't expect to get here. */
+                            break;
+                    }
                 }
                 else
                 {
                     mtCOVERAGE_TEST_MARKER();
                 }
-
-                traceTIMER_COMMAND_RECEIVED( pxTimer, xMessage.xMessageID, xMessage.u.xTimerParameters.xMessageValue );
-
-                /* In this case the xTimerListsWereSwitched parameter is not used, but
-                 *  it must be present in the function call.  prvSampleTimeNow() must be
-                 *  called after the message is received from xTimerQueue so there is no
-                 *  possibility of a higher priority task adding a message to the message
-                 *  queue with a time that is ahead of the timer daemon task (because it
-                 *  pre-empted the timer daemon task after the xTimeNow value was set). */
-                xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
-
-                switch( xMessage.xMessageID )
-                {
-                    case tmrCOMMAND_START:
-                    case tmrCOMMAND_START_FROM_ISR:
-                    case tmrCOMMAND_RESET:
-                    case tmrCOMMAND_RESET_FROM_ISR:
-                        /* Start or restart a timer. */
-                        pxTimer->ucStatus |= ( uint8_t ) tmrSTATUS_IS_ACTIVE;
-
-                        if( prvInsertTimerInActiveList( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE )
-                        {
-                            /* The timer expired before it was added to the active
-                             * timer list.  Process it now. */
-                            if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0U )
-                            {
-                                prvReloadTimer( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow );
-                            }
-                            else
-                            {
-                                pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE );
-                            }
-
-                            /* Call the timer callback. */
-                            traceTIMER_EXPIRED( pxTimer );
-                            pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
-                        }
-                        else
-                        {
-                            mtCOVERAGE_TEST_MARKER();
-                        }
-
-                        break;
-
-                    case tmrCOMMAND_STOP:
-                    case tmrCOMMAND_STOP_FROM_ISR:
-                        /* The timer has already been removed from the active list. */
-                        pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE );
-                        break;
-
-                    case tmrCOMMAND_CHANGE_PERIOD:
-                    case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR:
-                        pxTimer->ucStatus |= ( uint8_t ) tmrSTATUS_IS_ACTIVE;
-                        pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue;
-                        configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) );
-
-                        /* The new period does not really have a reference, and can
-                         * be longer or shorter than the old one.  The command time is
-                         * therefore set to the current time, and as the period cannot
-                         * be zero the next expiry time can only be in the future,
-                         * meaning (unlike for the xTimerStart() case above) there is
-                         * no fail case that needs to be handled here. */
-                        ( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow );
-                        break;
-
-                    case tmrCOMMAND_DELETE:
-                        #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-                        {
-                            /* The timer has already been removed from the active list,
-                             * just free up the memory if the memory was dynamically
-                             * allocated. */
-                            if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 )
-                            {
-                                vPortFree( pxTimer );
-                            }
-                            else
-                            {
-                                pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE );
-                            }
-                        }
-                        #else /* if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) */
-                        {
-                            /* If dynamic allocation is not enabled, the memory
-                             * could not have been dynamically allocated. So there is
-                             * no need to free the memory - just mark the timer as
-                             * "not active". */
-                            pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE );
-                        }
-                        #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
-                        break;
-
-                    default:
-                        /* Don't expect to get here. */
-                        break;
-                }
             }
         }
     }

From 60f34f8503fc803ceaa29f9375118ce086396280 Mon Sep 17 00:00:00 2001
From: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Date: Tue, 4 Mar 2025 13:18:43 +0530
Subject: [PATCH 391/424] Add history.txt for release V11.2.0 (#1253)

* Add history.txt for release V11.2.0

* Fix spelling

Co-authored-by: Ahmed Ismail <64546783+AhmedIsmail02@users.noreply.github.com>

---------

Co-authored-by: Ahmed Ismail <64546783+AhmedIsmail02@users.noreply.github.com>
---
 History.txt | 135 ++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 135 insertions(+)

diff --git a/History.txt b/History.txt
index ae29ae9c9..7df76e16f 100644
--- a/History.txt
+++ b/History.txt
@@ -1,5 +1,140 @@
 Documentation and download available at https://www.FreeRTOS.org/
 
+Changes between FreeRTOS V11.1.0 and FreeRTOS V11.2.0 released March 04, 2025
+
+    + Add CC-RH port for Renesas F1Kx devices. We thank @TrongNguyenR for their
+      contribution.
+    + Add Pointer Authentication (PAC) and Branch Target Identification (BTI)
+      support to the ARMv8-M ports. We thank @AhmedIsmail02 for their
+      contribution.
+    + Add Floating Point Unit (FPU) support to the ARM_AARCH64 port. We thank
+      @StefanBalt for their contribution.
+    + Add FPU Safe Application IRQ Handler suport to the ARM_AARCH64_SRE port.
+      We thank @GhMarwen for their contribution.
+    + Add Privileged eXecute Never MPU attribute support to the ARMv8-M ports.
+      We thank @AhmedIsmail02 for their contribution.
+    + Update XMOS xcore.ai port to be compatible with FreeRTOS Kernel version
+      11. We thank @ACascarino for their contribution.
+    + ARM_CRx_No_GIC port updates:
+      - Remove inline assembly and move assembly code to separate portASM.S
+        file.
+      - Add support for Floating Point Unit (FPU).
+      - Add support to allow the application writer to handle SVC calls raised
+        from the application code.
+      - Add support for vApplicationFPUSafeIRQHandler.
+    + POSIX port updates:
+      - Set PTHREAD_MUTEX_ROBUST attribute on the mutex to prevent application
+        hangs when a thread dies while holding a mutex.
+      - Avoid calling pthread_sigmask on non-FreeROS threads when
+        vPortEndScheduler is called from a non-FreeRTOS thread. We thank
+        @johnboiles for their contribution.
+      - Remove unnecessary call to pthread_attr_setstacksize. We thank
+        @hollinsky for their contribution.
+      - Add an assert to catch if vPortYield is called from a non-FreeRTOS
+        thread. We thank @johnboiles for their contribution.
+      - Fix Posix port compilation on FreeBSD. We thank @tymmej for their
+        contribution.
+    + Update the Xtensa port and move it to the Partner-Supported-Ports
+      repository. We thank @ianstcdns for their contribution.
+    + Add vPortGenerateSimulatedInterruptFromWindowsThread API in the MSVC-MingW
+      port to enable native windows thread to synchronize with FreeRTOS task
+      through simulated interrupt.
+    + Update Windows port to use Waitable Timer instead of Sleep to improve tick
+      accuracy. We thank @bknicholls and @leegeth for their contribution.
+    + Update the value of queueQUEUE_TYPE_SET to a unique value (5) to allow
+      tracers to differentiate between queues and queue sets. We thank @schilkp
+      for their contribution.
+    + Add traceSTARTING_SCHEDULER tracing hook to enable tracers to run code on
+      startup. We thank @schilkp for their contribution.
+    + Define vApplicationGetTimerTaskMemory only when configUSE_TIMERS is set to
+      1. We thank @HazardyKnusperkeks for their contribution.
+    + Reset xNextTaskUnblockTime in task notify FromISR APIs to allow the core
+      to enter sleep mode at the earliest possible time when using tickless
+      idle.
+    + Optimize xTaskIncrementTick for SMP by removing xYieldRequiredForCore. We
+      thank @cymizer for their contribution.
+    + Update the SMP scheduler to re-select a core to yield when the core
+      affinity of a ready task is changed.
+    + Update xEventGroupSetBits to read the event bits value to be returned to
+      the caller while the scheduler is suspended. This fixes dereference after
+      the event group is deleted by higher priority task. We thank @skotopes for
+      their contribution.
+    + Optimize certain getter APIs by removing unnecessary calls to
+      task{ENTER|EXIT}_CRITICAL() when the data access is atomic. We thank
+      @GuilhermeGiacomoSimoes for their contribution.
+    + Optimize xTaskNotifyWait and ulTaskNotifyTake APIs to suspend the
+      scheduler only if the task is not already notified, and the caller is
+      willing to wait for the notification. We thank @jefftenney for
+      their contribution.
+    + Fix error checking of prvCreateIdleTasks. We thank @kakkoko for their
+      contribution.
+    + Update SMP lock macros and critical nesting macros to pass core ID as an
+      argument. This reduces the number of accesses to a peripheral register to
+      query core ID. We thank @felixvanoost for their contribution.
+    + Add stack pointer bounds check when configCHECK_FOR_STACK_OVERFLOW is set
+      to 2 to improve reliability of stack overflow detection. We thank
+      @jiladahe1997 for their contribution.
+    + Update run-time stats to include time elapsed since the last context
+      switch for the currently running task.
+    + Add xQueueCreateSetStatic API for static creation of Queue Sets. We thank
+      @kzorer for their contribution.
+    + Update the traceMALLOC() macro to pass the actual size of the allocated
+      block for secure_heap, heap_2, heap_4 and heap_5. We thank @DazzlingOkami
+      for their contribution.
+    + Update heap_1 to use heapADD_WILL_OVERFLOW macro to improve readability.
+      We thank @wdfk-prog for their contribution.
+    + Add pointer protection to the pxNextFreeBlock member of the allocated
+      block's metadata in heap_4 and heap_5 when configENABLE_HEAP_PROTECTOR is
+      set to 1. We thank @Saiiijchan for their contribution.
+    + Allow the application writer to override pointer validation for heap_5
+      when configENABLE_HEAP_PROTECTOR is used. We thank @Saiiijchan for their
+      contribution.
+    + Add xPortResetHeapMinimumEverFreeHeapSize to heap_4.c and heap_5.c.
+      We thank @TomasGalbickaNXP for their contribution.
+    + Add NULL check in the event_create function in the POSIX port. We thank
+      @laroche for their contribution.
+    + Use _GNU_SOURCE macro instead of __USE_GNU in the Posix port. We thank
+      @maxiaogood for their contribution.
+    + Use the new __ARM_FP macro instead of the deprectred __VFP_FP__ macro in
+      GCC/ARM_CM7, GCC/ARM_CM4_MPU, and GCC/ARM_CM4F ports. We thank @haydenridd
+      for their contribution.
+    + Add portMEMORY_BARRIER definition to the Xtensa port. We thank @superroc
+      for their contribution.
+    + Move the hardware include msp430.h to port.c from portmacro.h. We thank
+      @mayl for their contribution.
+    + Update ARM assembly syntax for Cortex-M ports. We thank @laroche for their
+      contribution.
+    + Update the Windows port to records a pending yield in
+      vPortCloseRunningThread to ensure that the next tick interrupt schedules
+      the next task regardless of the value of configUSE_PREEMPTION.
+    + Fix the context switch issue in the RL78 port. We thank @KeitaKashima for
+      their contribution.
+    + Fix compilation issue in ARM CM0 port when using Keil MDK. We thank
+      @TomasGalbickaNXP for their contribution.
+    + Fix IA32 port compilation when configUSE_COMMON_INTERRUPT_ENTRY_POINT is
+      set to 0. We thank @Ryzee119 for their contribution.
+    + Store configMTIMECMP_BASE_ADDRESS in a 64-bit integer for the RISC-V port.
+      We thank @vishwamartur for their contribution.
+    + Fix nested interrupt handling and optimize FPU related context switching
+      for the F1Kx port. We thank @TrongNguyenR for their contribution.
+    + Update the RP2040 port to add support for Raspberry Pi Pico SDK 2.0.0.
+      We thank @kilograham for their contribution.
+    + Fix the return value of portYIELD_FROM_ISR macro for the MSVC-MingW port.
+      We thank @wwhheerree for their contribution.
+    + Optimize vApplicationFPUSafeIRQHandler for the Coretex-A9 port by
+      removing the unnecessarily preserved callee saved registers. We thank
+      @Saiiijchan for their contribution.
+    + Fix the context array size for MPU ports to ensure the saved context
+      location falls within the reserved context area rather than overlapping
+      with the next MPU_SETTINGS structure member.
+    + Update CMake files for RP2040 port to fetch the port from the
+      Community-Supported-Ports repo. We thank @kilograham for their
+      contribution.
+    + Fix CMake file for the GCC ARM_CM0 port to include MPU files. We thank
+      @0mhu for their contribution.
+    + Add an example of human readable table generated by vTaskListTasks() in
+      the function documentation. We thank @wwhheerree for their contribution.
+
 Changes between FreeRTOS V11.0.1 and FreeRTOS V11.1.0 released April 22, 2024
 
     + Add ARMv7-R port with Memory Protection Unit (MPU) support.

From 742729ed2925aa1f6746fe3fe1ac74ffdef89e19 Mon Sep 17 00:00:00 2001
From: Stefan Innerhofer <33153046+InnerSteff@users.noreply.github.com>
Date: Tue, 4 Mar 2025 10:55:19 +0100
Subject: [PATCH 392/424] Add an assert o catch overflow of recursive mutex
 counter (#1254)

Add an assert o catch overflow of recursive mutex counter.
---
 queue.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/queue.c b/queue.c
index e91d9e39b..fe06368d3 100644
--- a/queue.c
+++ b/queue.c
@@ -833,6 +833,10 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength,
         if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() )
         {
             ( pxMutex->u.xSemaphore.uxRecursiveCallCount )++;
+
+            /* Check if an overflow occurred. */
+            configASSERT( pxMutex->u.xSemaphore.uxRecursiveCallCount );
+
             xReturn = pdPASS;
         }
         else
@@ -845,6 +849,9 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength,
             if( xReturn != pdFAIL )
             {
                 ( pxMutex->u.xSemaphore.uxRecursiveCallCount )++;
+
+                /* Check if an overflow occurred. */
+                configASSERT( pxMutex->u.xSemaphore.uxRecursiveCallCount );
             }
             else
             {

From 4d9cd906d3f7c339ee3d6d64a00c416d58a8b003 Mon Sep 17 00:00:00 2001
From: Jonathan Cubides <92931721+cubidesj@users.noreply.github.com>
Date: Thu, 6 Mar 2025 19:34:48 +0100
Subject: [PATCH 393/424] RISCV Add FPU context save (#1250)

* port: riscv: Split the number of registers and the size of the context

* port: riscv: Create some macros for the FPU context

* port: riscv: Add a couple of macros that store fpu context

* port: riscv: Update the stack init function to include the fpu context size

* port: riscv: Add a chip_specific_extensions file that includes the F extension

* Update dictionary to include some risc-v instructions

* port: riscv: Fix a few typos

* port: riscv: Apply @aggarg's sugestions
---
 .github/.cSpellWords.txt                      |   3 +
 ...freertos_risc_v_chip_specific_extensions.h |  24 +-
 portable/GCC/RISC-V/portASM.S                 |  96 +++---
 portable/GCC/RISC-V/portContext.h             | 287 +++++++++++++-----
 4 files changed, 287 insertions(+), 123 deletions(-)

diff --git a/.github/.cSpellWords.txt b/.github/.cSpellWords.txt
index 3582741e3..27fb0fc33 100644
--- a/.github/.cSpellWords.txt
+++ b/.github/.cSpellWords.txt
@@ -23,6 +23,7 @@ AIRCR
 ALMIEN
 ALMV
 ANDC
+andi
 ANDCCR
 APIC
 APROCFREQ
@@ -47,6 +48,7 @@ bcpc
 BCPC
 beevt
 BEEVT
+beqz
 BERR
 bfextu
 Biagioni
@@ -298,6 +300,7 @@ FADD
 FCMD
 fcolor
 FCSE
+fcsr
 fdiagnostics
 fdiv
 FDIV
diff --git a/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h b/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h
index 4d8a5fb53..c10869eb4 100644
--- a/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h
+++ b/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h
@@ -80,22 +80,22 @@ csrr t2, lpcount0
 csrr t3, lpstart1
 csrr t4, lpend1
 csrr t5, lpcount1
-sw t0, 1 * portWORD_SIZE( sp )
-sw t1, 2 * portWORD_SIZE( sp )
-sw t2, 3 * portWORD_SIZE( sp )
-sw t3, 4 * portWORD_SIZE( sp )
-sw t4, 5 * portWORD_SIZE( sp )
-sw t5, 6 * portWORD_SIZE( sp )
+sw t0, 2 * portWORD_SIZE( sp )
+sw t1, 3 * portWORD_SIZE( sp )
+sw t2, 4 * portWORD_SIZE( sp )
+sw t3, 5 * portWORD_SIZE( sp )
+sw t4, 6 * portWORD_SIZE( sp )
+sw t5, 7 * portWORD_SIZE( sp )
    .endm
 
 /* Restore the additional registers found on the Pulpino. */
    .macro portasmRESTORE_ADDITIONAL_REGISTERS
-lw t0, 1 * portWORD_SIZE( sp ) /* Load additional registers into accessible temporary registers. */
-lw t1, 2 * portWORD_SIZE( sp )
-lw t2, 3 * portWORD_SIZE( sp )
-lw t3, 4 * portWORD_SIZE( sp )
-lw t4, 5 * portWORD_SIZE( sp )
-lw t5, 6 * portWORD_SIZE( sp )
+lw t0, 2 * portWORD_SIZE( sp ) /* Load additional registers into accessible temporary registers. */
+lw t1, 3 * portWORD_SIZE( sp )
+lw t2, 4 * portWORD_SIZE( sp )
+lw t3, 5 * portWORD_SIZE( sp )
+lw t4, 6 * portWORD_SIZE( sp )
+lw t5, 7 * portWORD_SIZE( sp )
 csrw lpstart0, t0
 csrw lpend0, t1
 csrw lpcount0, t2
diff --git a/portable/GCC/RISC-V/portASM.S b/portable/GCC/RISC-V/portASM.S
index 99613ada6..1fe50f67c 100644
--- a/portable/GCC/RISC-V/portASM.S
+++ b/portable/GCC/RISC-V/portASM.S
@@ -162,7 +162,6 @@ definitions. */
  * where the global and thread pointers are currently assumed to be constant so
  * are not saved:
  *
- * mstatus
  * xCriticalNesting
  * x31
  * x30
@@ -192,18 +191,12 @@ definitions. */
  * x6
  * x5
  * portTASK_RETURN_ADDRESS
+ * [FPU registers (when enabled/available) go here]
  * [chip specific registers go here]
+ * mstatus
  * pxCode
  */
 pxPortInitialiseStack:
-    csrr t0, mstatus                    /* Obtain current mstatus value. */
-    andi t0, t0, ~0x8                   /* Ensure interrupts are disabled when the stack is restored within an ISR.  Required when a task is created after the schedulre has been started, otherwise interrupts would be disabled anyway. */
-    addi t1, x0, 0x188                  /* Generate the value 0x1880, which are the MPIE and MPP bits to set in mstatus. */
-    slli t1, t1, 4
-    or t0, t0, t1                       /* Set MPIE and MPP bits in mstatus value. */
-
-    addi a0, a0, -portWORD_SIZE
-    store_x t0, 0(a0)                   /* mstatus onto the stack. */
     addi a0, a0, -portWORD_SIZE         /* Space for critical nesting count. */
     store_x x0, 0(a0)                   /* Critical nesting count starts at 0 for every task. */
 
@@ -212,10 +205,12 @@ pxPortInitialiseStack:
 #else
     addi a0, a0, -(22 * portWORD_SIZE)  /* Space for registers x10-x31. */
 #endif
-    store_x a2, 0(a0)                   /* Task parameters (pvParameters parameter) goes into register X10/a0 on the stack. */
-    addi a0, a0, -(6 * portWORD_SIZE)   /* Space for registers x5-x9 + taskReturnAddress. */
+    store_x a2, 0(a0)                   /* Task parameters (pvParameters parameter) goes into register x10/a0 on the stack. */
+
+    addi a0, a0, -(6 * portWORD_SIZE)   /* Space for registers x5-x9 + taskReturnAddress (register x1). */
     load_x t0, xTaskReturnAddress
     store_x t0, 0(a0)                   /* Return address onto the stack. */
+
     addi t0, x0, portasmADDITIONAL_CONTEXT_SIZE /* The number of chip specific additional registers. */
 chip_specific_stack_frame:              /* First add any chip specific registers to the stack frame being created. */
     beq t0, x0, 1f                      /* No more chip specific registers to save. */
@@ -224,6 +219,23 @@ chip_specific_stack_frame:              /* First add any chip specific registers
     addi t0, t0, -1                     /* Decrement the count of chip specific registers remaining. */
     j chip_specific_stack_frame         /* Until no more chip specific registers. */
 1:
+    csrr t0, mstatus                    /* Obtain current mstatus value. */
+    andi t0, t0, ~0x8                   /* Ensure interrupts are disabled when the stack is restored within an ISR.  Required when a task is created after the scheduler has been started, otherwise interrupts would be disabled anyway. */
+    addi t1, x0, 0x188                  /* Generate the value 0x1880, which are the MPIE=1 and MPP=M_Mode in mstatus. */
+    slli t1, t1, 4
+    or t0, t0, t1                       /* Set MPIE and MPP bits in mstatus value. */
+
+#if( configENABLE_FPU == 1 )
+    /* Mark the FPU as clean in the mstatus value. */
+    li t1, ~MSTATUS_FS_MASK
+    and t0, t0, t1
+    li t1, MSTATUS_FS_CLEAN
+    or t0, t0, t1
+#endif
+
+    addi a0, a0, -portWORD_SIZE
+    store_x t0, 0(a0)                   /* mstatus onto the stack. */
+
     addi a0, a0, -portWORD_SIZE
     store_x a1, 0(a0)                   /* mret value (pxCode parameter) onto the stack. */
     ret
@@ -235,46 +247,46 @@ xPortStartFirstTask:
 
     load_x  x1, 0( sp ) /* Note for starting the scheduler the exception return address is used as the function return address. */
 
+    load_x  x5, 1 * portWORD_SIZE( sp ) /* Initial mstatus into x5 (t0). */
+    addi    x5, x5, 0x08                /* Set MIE bit so the first task starts with interrupts enabled - required as returns with ret not eret. */
+    csrw    mstatus, x5                 /* Interrupts enabled from here! */
+
     portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
 
-    load_x  x7, 4 * portWORD_SIZE( sp )     /* t2 */
-    load_x  x8, 5 * portWORD_SIZE( sp )     /* s0/fp */
-    load_x  x9, 6 * portWORD_SIZE( sp )     /* s1 */
-    load_x  x10, 7 * portWORD_SIZE( sp )    /* a0 */
-    load_x  x11, 8 * portWORD_SIZE( sp )    /* a1 */
-    load_x  x12, 9 * portWORD_SIZE( sp )    /* a2 */
-    load_x  x13, 10 * portWORD_SIZE( sp )   /* a3 */
-    load_x  x14, 11 * portWORD_SIZE( sp )   /* a4 */
-    load_x  x15, 12 * portWORD_SIZE( sp )   /* a5 */
+    load_x  x7,  5  * portWORD_SIZE( sp )   /* t2 */
+    load_x  x8,  6  * portWORD_SIZE( sp )   /* s0/fp */
+    load_x  x9,  7  * portWORD_SIZE( sp )   /* s1 */
+    load_x  x10, 8  * portWORD_SIZE( sp )   /* a0 */
+    load_x  x11, 9  * portWORD_SIZE( sp )   /* a1 */
+    load_x  x12, 10 * portWORD_SIZE( sp )   /* a2 */
+    load_x  x13, 11 * portWORD_SIZE( sp )   /* a3 */
+    load_x  x14, 12 * portWORD_SIZE( sp )   /* a4 */
+    load_x  x15, 13 * portWORD_SIZE( sp )   /* a5 */
 #ifndef __riscv_32e
-    load_x  x16, 13 * portWORD_SIZE( sp )   /* a6 */
-    load_x  x17, 14 * portWORD_SIZE( sp )   /* a7 */
-    load_x  x18, 15 * portWORD_SIZE( sp )   /* s2 */
-    load_x  x19, 16 * portWORD_SIZE( sp )   /* s3 */
-    load_x  x20, 17 * portWORD_SIZE( sp )   /* s4 */
-    load_x  x21, 18 * portWORD_SIZE( sp )   /* s5 */
-    load_x  x22, 19 * portWORD_SIZE( sp )   /* s6 */
-    load_x  x23, 20 * portWORD_SIZE( sp )   /* s7 */
-    load_x  x24, 21 * portWORD_SIZE( sp )   /* s8 */
-    load_x  x25, 22 * portWORD_SIZE( sp )   /* s9 */
-    load_x  x26, 23 * portWORD_SIZE( sp )   /* s10 */
-    load_x  x27, 24 * portWORD_SIZE( sp )   /* s11 */
-    load_x  x28, 25 * portWORD_SIZE( sp )   /* t3 */
-    load_x  x29, 26 * portWORD_SIZE( sp )   /* t4 */
-    load_x  x30, 27 * portWORD_SIZE( sp )   /* t5 */
-    load_x  x31, 28 * portWORD_SIZE( sp )   /* t6 */
+    load_x  x16, 14 * portWORD_SIZE( sp )   /* a6 */
+    load_x  x17, 15 * portWORD_SIZE( sp )   /* a7 */
+    load_x  x18, 16 * portWORD_SIZE( sp )   /* s2 */
+    load_x  x19, 17 * portWORD_SIZE( sp )   /* s3 */
+    load_x  x20, 18 * portWORD_SIZE( sp )   /* s4 */
+    load_x  x21, 19 * portWORD_SIZE( sp )   /* s5 */
+    load_x  x22, 20 * portWORD_SIZE( sp )   /* s6 */
+    load_x  x23, 21 * portWORD_SIZE( sp )   /* s7 */
+    load_x  x24, 22 * portWORD_SIZE( sp )   /* s8 */
+    load_x  x25, 23 * portWORD_SIZE( sp )   /* s9 */
+    load_x  x26, 24 * portWORD_SIZE( sp )   /* s10 */
+    load_x  x27, 25 * portWORD_SIZE( sp )   /* s11 */
+    load_x  x28, 26 * portWORD_SIZE( sp )   /* t3 */
+    load_x  x29, 27 * portWORD_SIZE( sp )   /* t4 */
+    load_x  x30, 28 * portWORD_SIZE( sp )   /* t5 */
+    load_x  x31, 29 * portWORD_SIZE( sp )   /* t6 */
 #endif
 
     load_x  x5, portCRITICAL_NESTING_OFFSET * portWORD_SIZE( sp )    /* Obtain xCriticalNesting value for this task from task's stack. */
     load_x  x6, pxCriticalNesting           /* Load the address of xCriticalNesting into x6. */
     store_x x5, 0( x6 )                     /* Restore the critical nesting value for this task. */
 
-    load_x  x5, portMSTATUS_OFFSET * portWORD_SIZE( sp )    /* Initial mstatus into x5 (t0). */
-    addi    x5, x5, 0x08                    /* Set MIE bit so the first task starts with interrupts enabled - required as returns with ret not eret. */
-    csrrw   x0, mstatus, x5                 /* Interrupts enabled from here! */
-
-    load_x  x5, 2 * portWORD_SIZE( sp )     /* Initial x5 (t0) value. */
-    load_x  x6, 3 * portWORD_SIZE( sp )     /* Initial x6 (t1) value. */
+    load_x  x5, 3 * portWORD_SIZE( sp )     /* Initial x5 (t0) value. */
+    load_x  x6, 4 * portWORD_SIZE( sp )     /* Initial x6 (t1) value. */
 
     addi    sp, sp, portCONTEXT_SIZE
     ret
diff --git a/portable/GCC/RISC-V/portContext.h b/portable/GCC/RISC-V/portContext.h
index 6baae753d..9afe6eef3 100644
--- a/portable/GCC/RISC-V/portContext.h
+++ b/portable/GCC/RISC-V/portContext.h
@@ -29,6 +29,10 @@
 #ifndef PORTCONTEXT_H
 #define PORTCONTEXT_H
 
+#ifndef configENABLE_FPU
+    #define configENABLE_FPU 0
+#endif
+
 #if __riscv_xlen == 64
     #define portWORD_SIZE    8
     #define store_x          sd
@@ -50,65 +54,199 @@
  * notes at the top of portASM.S file. */
 #ifdef __riscv_32e
     #define portCONTEXT_SIZE               ( 15 * portWORD_SIZE )
-    #define portCRITICAL_NESTING_OFFSET    13
-    #define portMSTATUS_OFFSET             14
+    #define portCRITICAL_NESTING_OFFSET    14
 #else
     #define portCONTEXT_SIZE               ( 31 * portWORD_SIZE )
-    #define portCRITICAL_NESTING_OFFSET    29
-    #define portMSTATUS_OFFSET             30
+    #define portCRITICAL_NESTING_OFFSET    30
 #endif
 
+#if ( configENABLE_FPU == 1 )
+    /* Bit [14:13] in the mstatus encode the status of FPU state which is one of
+     * the following values:
+     * 1. Value: 0, Meaning: Off.
+     * 2. Value: 1, Meaning: Initial.
+     * 3. Value: 2, Meaning: Clean.
+     * 4. Value: 3, Meaning: Dirty.
+     */
+    #define MSTATUS_FS_MASK                 0x6000
+    #define MSTATUS_FS_INITIAL              0x2000
+    #define MSTATUS_FS_CLEAN                0x4000
+    #define MSTATUS_FS_DIRTY                0x6000
+    #define MSTATUS_FS_OFFSET               13
+
+    #ifdef __riscv_fdiv
+        #if __riscv_flen == 32
+            #define load_f                  flw
+            #define store_f                 fsw
+        #elif __riscv_flen == 64
+            #define load_f                  fld
+            #define store_f                 fsd
+        #else
+            #error Assembler did not define __riscv_flen
+        #endif
+
+        #define portFPU_REG_SIZE                ( __riscv_flen / 8 )
+        #define portFPU_REG_COUNT               33 /* 32 Floating point registers plus one CSR. */
+        #define portFPU_CONTEXT_SIZE            ( portFPU_REG_SIZE * portFPU_REG_COUNT )
+    #else
+        #error configENABLE_FPU must not be set to 1 if the hardwar does not have FPU
+    #endif
+#endif
 /*-----------------------------------------------------------*/
 
 .extern pxCurrentTCB
-   .extern xISRStackTop
-   .extern xCriticalNesting
-   .extern pxCriticalNesting
+.extern xISRStackTop
+.extern xCriticalNesting
+.extern pxCriticalNesting
+/*-----------------------------------------------------------*/
+
+    .macro portcontexSAVE_FPU_CONTEXT
+addi sp, sp, -( portFPU_CONTEXT_SIZE )
+/* Store the FPU registers. */
+store_f f0,  2  * portWORD_SIZE( sp )
+store_f f1,  3  * portWORD_SIZE( sp )
+store_f f2,  4  * portWORD_SIZE( sp )
+store_f f3,  5  * portWORD_SIZE( sp )
+store_f f4,  6  * portWORD_SIZE( sp )
+store_f f5,  7  * portWORD_SIZE( sp )
+store_f f6,  8  * portWORD_SIZE( sp )
+store_f f7,  9  * portWORD_SIZE( sp )
+store_f f8,  10 * portWORD_SIZE( sp )
+store_f f9,  11 * portWORD_SIZE( sp )
+store_f f10, 12 * portWORD_SIZE( sp )
+store_f f11, 13 * portWORD_SIZE( sp )
+store_f f12, 14 * portWORD_SIZE( sp )
+store_f f13, 15 * portWORD_SIZE( sp )
+store_f f14, 16 * portWORD_SIZE( sp )
+store_f f15, 17 * portWORD_SIZE( sp )
+store_f f16, 18 * portWORD_SIZE( sp )
+store_f f17, 19 * portWORD_SIZE( sp )
+store_f f18, 20 * portWORD_SIZE( sp )
+store_f f19, 21 * portWORD_SIZE( sp )
+store_f f20, 22 * portWORD_SIZE( sp )
+store_f f21, 23 * portWORD_SIZE( sp )
+store_f f22, 24 * portWORD_SIZE( sp )
+store_f f23, 25 * portWORD_SIZE( sp )
+store_f f24, 26 * portWORD_SIZE( sp )
+store_f f25, 27 * portWORD_SIZE( sp )
+store_f f26, 28 * portWORD_SIZE( sp )
+store_f f27, 29 * portWORD_SIZE( sp )
+store_f f28, 30 * portWORD_SIZE( sp )
+store_f f29, 31 * portWORD_SIZE( sp )
+store_f f30, 32 * portWORD_SIZE( sp )
+store_f f31, 33 * portWORD_SIZE( sp )
+csrr t0, fcsr
+store_x t0,  34 * portWORD_SIZE( sp )
+    .endm
+/*-----------------------------------------------------------*/
+
+    .macro portcontextRESTORE_FPU_CONTEXT
+/* Restore the FPU registers. */
+load_f f0,  2  * portWORD_SIZE( sp )
+load_f f1,  3  * portWORD_SIZE( sp )
+load_f f2,  4  * portWORD_SIZE( sp )
+load_f f3,  5  * portWORD_SIZE( sp )
+load_f f4,  6  * portWORD_SIZE( sp )
+load_f f5,  7  * portWORD_SIZE( sp )
+load_f f6,  8  * portWORD_SIZE( sp )
+load_f f7,  9  * portWORD_SIZE( sp )
+load_f f8,  10 * portWORD_SIZE( sp )
+load_f f9,  11 * portWORD_SIZE( sp )
+load_f f10, 12 * portWORD_SIZE( sp )
+load_f f11, 13 * portWORD_SIZE( sp )
+load_f f12, 14 * portWORD_SIZE( sp )
+load_f f13, 15 * portWORD_SIZE( sp )
+load_f f14, 16 * portWORD_SIZE( sp )
+load_f f15, 17 * portWORD_SIZE( sp )
+load_f f16, 18 * portWORD_SIZE( sp )
+load_f f17, 19 * portWORD_SIZE( sp )
+load_f f18, 20 * portWORD_SIZE( sp )
+load_f f19, 21 * portWORD_SIZE( sp )
+load_f f20, 22 * portWORD_SIZE( sp )
+load_f f21, 23 * portWORD_SIZE( sp )
+load_f f22, 24 * portWORD_SIZE( sp )
+load_f f23, 25 * portWORD_SIZE( sp )
+load_f f24, 26 * portWORD_SIZE( sp )
+load_f f25, 27 * portWORD_SIZE( sp )
+load_f f26, 28 * portWORD_SIZE( sp )
+load_f f27, 29 * portWORD_SIZE( sp )
+load_f f28, 30 * portWORD_SIZE( sp )
+load_f f29, 31 * portWORD_SIZE( sp )
+load_f f30, 32 * portWORD_SIZE( sp )
+load_f f31, 33 * portWORD_SIZE( sp )
+load_x t0,  34 * portWORD_SIZE( sp )
+csrw fcsr, t0
+addi sp, sp, ( portFPU_CONTEXT_SIZE )
+    .endm
 /*-----------------------------------------------------------*/
 
    .macro portcontextSAVE_CONTEXT_INTERNAL
 addi sp, sp, -portCONTEXT_SIZE
-store_x x1, 1 * portWORD_SIZE( sp )
-store_x x5, 2 * portWORD_SIZE( sp )
-store_x x6, 3 * portWORD_SIZE( sp )
-store_x x7, 4 * portWORD_SIZE( sp )
-store_x x8, 5 * portWORD_SIZE( sp )
-store_x x9, 6 * portWORD_SIZE( sp )
-store_x x10, 7 * portWORD_SIZE( sp )
-store_x x11, 8 * portWORD_SIZE( sp )
-store_x x12, 9 * portWORD_SIZE( sp )
-store_x x13, 10 * portWORD_SIZE( sp )
-store_x x14, 11 * portWORD_SIZE( sp )
-store_x x15, 12 * portWORD_SIZE( sp )
+store_x x1,  2  * portWORD_SIZE( sp )
+store_x x5,  3  * portWORD_SIZE( sp )
+store_x x6,  4  * portWORD_SIZE( sp )
+store_x x7,  5  * portWORD_SIZE( sp )
+store_x x8,  6  * portWORD_SIZE( sp )
+store_x x9,  7  * portWORD_SIZE( sp )
+store_x x10, 8  * portWORD_SIZE( sp )
+store_x x11, 9  * portWORD_SIZE( sp )
+store_x x12, 10 * portWORD_SIZE( sp )
+store_x x13, 11 * portWORD_SIZE( sp )
+store_x x14, 12 * portWORD_SIZE( sp )
+store_x x15, 13 * portWORD_SIZE( sp )
 #ifndef __riscv_32e
-    store_x x16, 13 * portWORD_SIZE( sp )
-    store_x x17, 14 * portWORD_SIZE( sp )
-    store_x x18, 15 * portWORD_SIZE( sp )
-    store_x x19, 16 * portWORD_SIZE( sp )
-    store_x x20, 17 * portWORD_SIZE( sp )
-    store_x x21, 18 * portWORD_SIZE( sp )
-    store_x x22, 19 * portWORD_SIZE( sp )
-    store_x x23, 20 * portWORD_SIZE( sp )
-    store_x x24, 21 * portWORD_SIZE( sp )
-    store_x x25, 22 * portWORD_SIZE( sp )
-    store_x x26, 23 * portWORD_SIZE( sp )
-    store_x x27, 24 * portWORD_SIZE( sp )
-    store_x x28, 25 * portWORD_SIZE( sp )
-    store_x x29, 26 * portWORD_SIZE( sp )
-    store_x x30, 27 * portWORD_SIZE( sp )
-    store_x x31, 28 * portWORD_SIZE( sp )
+    store_x x16, 14 * portWORD_SIZE( sp )
+    store_x x17, 15 * portWORD_SIZE( sp )
+    store_x x18, 16 * portWORD_SIZE( sp )
+    store_x x19, 17 * portWORD_SIZE( sp )
+    store_x x20, 18 * portWORD_SIZE( sp )
+    store_x x21, 19 * portWORD_SIZE( sp )
+    store_x x22, 20 * portWORD_SIZE( sp )
+    store_x x23, 21 * portWORD_SIZE( sp )
+    store_x x24, 22 * portWORD_SIZE( sp )
+    store_x x25, 23 * portWORD_SIZE( sp )
+    store_x x26, 24 * portWORD_SIZE( sp )
+    store_x x27, 25 * portWORD_SIZE( sp )
+    store_x x28, 26 * portWORD_SIZE( sp )
+    store_x x29, 27 * portWORD_SIZE( sp )
+    store_x x30, 28 * portWORD_SIZE( sp )
+    store_x x31, 29 * portWORD_SIZE( sp )
 #endif /* ifndef __riscv_32e */
 
 load_x t0, xCriticalNesting                                   /* Load the value of xCriticalNesting into t0. */
 store_x t0, portCRITICAL_NESTING_OFFSET * portWORD_SIZE( sp ) /* Store the critical nesting value to the stack. */
 
+#if( configENABLE_FPU == 1 )
+    csrr t0, mstatus
+    srl t1, t0, MSTATUS_FS_OFFSET
+    andi t1, t1, 3
+    addi t2, x0, 3
+    bne t1, t2, 1f /* If FPU status is not dirty, do not save FPU registers. */
 
-csrr t0, mstatus /* Required for MPIE bit. */
-store_x t0, portMSTATUS_OFFSET * portWORD_SIZE( sp )
-
+    portcontexSAVE_FPU_CONTEXT
+1:
+#endif
 
 portasmSAVE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to save any registers unique to the RISC-V implementation. */
 
+csrr t0, mstatus
+store_x t0, 1 * portWORD_SIZE( sp )
+
+#if( configENABLE_FPU == 1 )
+    /* Mark the FPU as clean, if it was dirty and we saved FPU registers. */
+    srl t1, t0, MSTATUS_FS_OFFSET
+    andi t1, t1, 3
+    addi t2, x0, 3
+    bne t1, t2, 2f
+
+    li t1, ~MSTATUS_FS_MASK
+    and t0, t0, t1
+    li t1, MSTATUS_FS_CLEAN
+    or t0, t0, t1
+    csrw mstatus, t0
+2:
+#endif
+
 load_x t0, pxCurrentTCB          /* Load pxCurrentTCB. */
 store_x sp, 0 ( t0 )             /* Write sp to first TCB member. */
 
@@ -142,46 +280,57 @@ load_x sp, 0 ( t1 )     /* Read sp from first TCB member. */
 load_x t0, 0 ( sp )
 csrw mepc, t0
 
+/* Restore mstatus register. */
+load_x t0, 1 * portWORD_SIZE( sp )
+csrw mstatus, t0
+
 /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
 portasmRESTORE_ADDITIONAL_REGISTERS
 
-/* Load mstatus with the interrupt enable bits used by the task. */
-load_x t0, portMSTATUS_OFFSET * portWORD_SIZE( sp )
-csrw mstatus, t0                                             /* Required for MPIE bit. */
+#if( configENABLE_FPU == 1 )
+    csrr t0, mstatus
+    srl t1, t0, MSTATUS_FS_OFFSET
+    andi t1, t1, 3
+    addi t2, x0, 3
+    bne t1, t2, 3f /* If FPU status is not dirty, do not restore FPU registers. */
+
+    portcontextRESTORE_FPU_CONTEXT
+3:
+#endif /* ifdef portasmSTORE_FPU_CONTEXT */
 
 load_x t0, portCRITICAL_NESTING_OFFSET * portWORD_SIZE( sp ) /* Obtain xCriticalNesting value for this task from task's stack. */
 load_x t1, pxCriticalNesting                                 /* Load the address of xCriticalNesting into t1. */
 store_x t0, 0 ( t1 )                                         /* Restore the critical nesting value for this task. */
 
-load_x x1, 1 * portWORD_SIZE( sp )
-load_x x5, 2 * portWORD_SIZE( sp )
-load_x x6, 3 * portWORD_SIZE( sp )
-load_x x7, 4 * portWORD_SIZE( sp )
-load_x x8, 5 * portWORD_SIZE( sp )
-load_x x9, 6 * portWORD_SIZE( sp )
-load_x x10, 7 * portWORD_SIZE( sp )
-load_x x11, 8 * portWORD_SIZE( sp )
-load_x x12, 9 * portWORD_SIZE( sp )
-load_x x13, 10 * portWORD_SIZE( sp )
-load_x x14, 11 * portWORD_SIZE( sp )
-load_x x15, 12 * portWORD_SIZE( sp )
+load_x x1,  2  * portWORD_SIZE( sp )
+load_x x5,  3  * portWORD_SIZE( sp )
+load_x x6,  4  * portWORD_SIZE( sp )
+load_x x7,  5  * portWORD_SIZE( sp )
+load_x x8,  6  * portWORD_SIZE( sp )
+load_x x9,  7  * portWORD_SIZE( sp )
+load_x x10, 8  * portWORD_SIZE( sp )
+load_x x11, 9  * portWORD_SIZE( sp )
+load_x x12, 10 * portWORD_SIZE( sp )
+load_x x13, 11 * portWORD_SIZE( sp )
+load_x x14, 12 * portWORD_SIZE( sp )
+load_x x15, 13 * portWORD_SIZE( sp )
 #ifndef __riscv_32e
-    load_x x16, 13 * portWORD_SIZE( sp )
-    load_x x17, 14 * portWORD_SIZE( sp )
-    load_x x18, 15 * portWORD_SIZE( sp )
-    load_x x19, 16 * portWORD_SIZE( sp )
-    load_x x20, 17 * portWORD_SIZE( sp )
-    load_x x21, 18 * portWORD_SIZE( sp )
-    load_x x22, 19 * portWORD_SIZE( sp )
-    load_x x23, 20 * portWORD_SIZE( sp )
-    load_x x24, 21 * portWORD_SIZE( sp )
-    load_x x25, 22 * portWORD_SIZE( sp )
-    load_x x26, 23 * portWORD_SIZE( sp )
-    load_x x27, 24 * portWORD_SIZE( sp )
-    load_x x28, 25 * portWORD_SIZE( sp )
-    load_x x29, 26 * portWORD_SIZE( sp )
-    load_x x30, 27 * portWORD_SIZE( sp )
-    load_x x31, 28 * portWORD_SIZE( sp )
+    load_x x16, 14 * portWORD_SIZE( sp )
+    load_x x17, 15 * portWORD_SIZE( sp )
+    load_x x18, 16 * portWORD_SIZE( sp )
+    load_x x19, 17 * portWORD_SIZE( sp )
+    load_x x20, 18 * portWORD_SIZE( sp )
+    load_x x21, 19 * portWORD_SIZE( sp )
+    load_x x22, 20 * portWORD_SIZE( sp )
+    load_x x23, 21 * portWORD_SIZE( sp )
+    load_x x24, 22 * portWORD_SIZE( sp )
+    load_x x25, 23 * portWORD_SIZE( sp )
+    load_x x26, 24 * portWORD_SIZE( sp )
+    load_x x27, 25 * portWORD_SIZE( sp )
+    load_x x28, 26 * portWORD_SIZE( sp )
+    load_x x29, 27 * portWORD_SIZE( sp )
+    load_x x30, 28 * portWORD_SIZE( sp )
+    load_x x31, 29 * portWORD_SIZE( sp )
 #endif /* ifndef __riscv_32e */
 addi sp, sp, portCONTEXT_SIZE
 

From bb47bc02f2a8705707258c254a3cea5bc74cc9e5 Mon Sep 17 00:00:00 2001
From: Saiiijchan <49641410+Saiiijchan@users.noreply.github.com>
Date: Thu, 13 Mar 2025 13:52:38 +0800
Subject: [PATCH 394/424] RISC-V: refine fpu offset according to
 portFPU_REG_SIZE (#1256)

Signed-off-by: wangfei_chen <wangfei_chen@realsil.com.cn>
Co-authored-by: wangfei_chen <wangfei_chen@realsil.com.cn>
---
 portable/GCC/RISC-V/portContext.h | 132 +++++++++++++++---------------
 1 file changed, 66 insertions(+), 66 deletions(-)

diff --git a/portable/GCC/RISC-V/portContext.h b/portable/GCC/RISC-V/portContext.h
index 9afe6eef3..d191b4aea 100644
--- a/portable/GCC/RISC-V/portContext.h
+++ b/portable/GCC/RISC-V/portContext.h
@@ -103,78 +103,78 @@
     .macro portcontexSAVE_FPU_CONTEXT
 addi sp, sp, -( portFPU_CONTEXT_SIZE )
 /* Store the FPU registers. */
-store_f f0,  2  * portWORD_SIZE( sp )
-store_f f1,  3  * portWORD_SIZE( sp )
-store_f f2,  4  * portWORD_SIZE( sp )
-store_f f3,  5  * portWORD_SIZE( sp )
-store_f f4,  6  * portWORD_SIZE( sp )
-store_f f5,  7  * portWORD_SIZE( sp )
-store_f f6,  8  * portWORD_SIZE( sp )
-store_f f7,  9  * portWORD_SIZE( sp )
-store_f f8,  10 * portWORD_SIZE( sp )
-store_f f9,  11 * portWORD_SIZE( sp )
-store_f f10, 12 * portWORD_SIZE( sp )
-store_f f11, 13 * portWORD_SIZE( sp )
-store_f f12, 14 * portWORD_SIZE( sp )
-store_f f13, 15 * portWORD_SIZE( sp )
-store_f f14, 16 * portWORD_SIZE( sp )
-store_f f15, 17 * portWORD_SIZE( sp )
-store_f f16, 18 * portWORD_SIZE( sp )
-store_f f17, 19 * portWORD_SIZE( sp )
-store_f f18, 20 * portWORD_SIZE( sp )
-store_f f19, 21 * portWORD_SIZE( sp )
-store_f f20, 22 * portWORD_SIZE( sp )
-store_f f21, 23 * portWORD_SIZE( sp )
-store_f f22, 24 * portWORD_SIZE( sp )
-store_f f23, 25 * portWORD_SIZE( sp )
-store_f f24, 26 * portWORD_SIZE( sp )
-store_f f25, 27 * portWORD_SIZE( sp )
-store_f f26, 28 * portWORD_SIZE( sp )
-store_f f27, 29 * portWORD_SIZE( sp )
-store_f f28, 30 * portWORD_SIZE( sp )
-store_f f29, 31 * portWORD_SIZE( sp )
-store_f f30, 32 * portWORD_SIZE( sp )
-store_f f31, 33 * portWORD_SIZE( sp )
+store_f f0,  2  * portFPU_REG_SIZE( sp )
+store_f f1,  3  * portFPU_REG_SIZE( sp )
+store_f f2,  4  * portFPU_REG_SIZE( sp )
+store_f f3,  5  * portFPU_REG_SIZE( sp )
+store_f f4,  6  * portFPU_REG_SIZE( sp )
+store_f f5,  7  * portFPU_REG_SIZE( sp )
+store_f f6,  8  * portFPU_REG_SIZE( sp )
+store_f f7,  9  * portFPU_REG_SIZE( sp )
+store_f f8,  10 * portFPU_REG_SIZE( sp )
+store_f f9,  11 * portFPU_REG_SIZE( sp )
+store_f f10, 12 * portFPU_REG_SIZE( sp )
+store_f f11, 13 * portFPU_REG_SIZE( sp )
+store_f f12, 14 * portFPU_REG_SIZE( sp )
+store_f f13, 15 * portFPU_REG_SIZE( sp )
+store_f f14, 16 * portFPU_REG_SIZE( sp )
+store_f f15, 17 * portFPU_REG_SIZE( sp )
+store_f f16, 18 * portFPU_REG_SIZE( sp )
+store_f f17, 19 * portFPU_REG_SIZE( sp )
+store_f f18, 20 * portFPU_REG_SIZE( sp )
+store_f f19, 21 * portFPU_REG_SIZE( sp )
+store_f f20, 22 * portFPU_REG_SIZE( sp )
+store_f f21, 23 * portFPU_REG_SIZE( sp )
+store_f f22, 24 * portFPU_REG_SIZE( sp )
+store_f f23, 25 * portFPU_REG_SIZE( sp )
+store_f f24, 26 * portFPU_REG_SIZE( sp )
+store_f f25, 27 * portFPU_REG_SIZE( sp )
+store_f f26, 28 * portFPU_REG_SIZE( sp )
+store_f f27, 29 * portFPU_REG_SIZE( sp )
+store_f f28, 30 * portFPU_REG_SIZE( sp )
+store_f f29, 31 * portFPU_REG_SIZE( sp )
+store_f f30, 32 * portFPU_REG_SIZE( sp )
+store_f f31, 33 * portFPU_REG_SIZE( sp )
 csrr t0, fcsr
-store_x t0,  34 * portWORD_SIZE( sp )
+store_x t0,  34 * portFPU_REG_SIZE( sp )
     .endm
 /*-----------------------------------------------------------*/
 
     .macro portcontextRESTORE_FPU_CONTEXT
 /* Restore the FPU registers. */
-load_f f0,  2  * portWORD_SIZE( sp )
-load_f f1,  3  * portWORD_SIZE( sp )
-load_f f2,  4  * portWORD_SIZE( sp )
-load_f f3,  5  * portWORD_SIZE( sp )
-load_f f4,  6  * portWORD_SIZE( sp )
-load_f f5,  7  * portWORD_SIZE( sp )
-load_f f6,  8  * portWORD_SIZE( sp )
-load_f f7,  9  * portWORD_SIZE( sp )
-load_f f8,  10 * portWORD_SIZE( sp )
-load_f f9,  11 * portWORD_SIZE( sp )
-load_f f10, 12 * portWORD_SIZE( sp )
-load_f f11, 13 * portWORD_SIZE( sp )
-load_f f12, 14 * portWORD_SIZE( sp )
-load_f f13, 15 * portWORD_SIZE( sp )
-load_f f14, 16 * portWORD_SIZE( sp )
-load_f f15, 17 * portWORD_SIZE( sp )
-load_f f16, 18 * portWORD_SIZE( sp )
-load_f f17, 19 * portWORD_SIZE( sp )
-load_f f18, 20 * portWORD_SIZE( sp )
-load_f f19, 21 * portWORD_SIZE( sp )
-load_f f20, 22 * portWORD_SIZE( sp )
-load_f f21, 23 * portWORD_SIZE( sp )
-load_f f22, 24 * portWORD_SIZE( sp )
-load_f f23, 25 * portWORD_SIZE( sp )
-load_f f24, 26 * portWORD_SIZE( sp )
-load_f f25, 27 * portWORD_SIZE( sp )
-load_f f26, 28 * portWORD_SIZE( sp )
-load_f f27, 29 * portWORD_SIZE( sp )
-load_f f28, 30 * portWORD_SIZE( sp )
-load_f f29, 31 * portWORD_SIZE( sp )
-load_f f30, 32 * portWORD_SIZE( sp )
-load_f f31, 33 * portWORD_SIZE( sp )
-load_x t0,  34 * portWORD_SIZE( sp )
+load_f f0,  2  * portFPU_REG_SIZE( sp )
+load_f f1,  3  * portFPU_REG_SIZE( sp )
+load_f f2,  4  * portFPU_REG_SIZE( sp )
+load_f f3,  5  * portFPU_REG_SIZE( sp )
+load_f f4,  6  * portFPU_REG_SIZE( sp )
+load_f f5,  7  * portFPU_REG_SIZE( sp )
+load_f f6,  8  * portFPU_REG_SIZE( sp )
+load_f f7,  9  * portFPU_REG_SIZE( sp )
+load_f f8,  10 * portFPU_REG_SIZE( sp )
+load_f f9,  11 * portFPU_REG_SIZE( sp )
+load_f f10, 12 * portFPU_REG_SIZE( sp )
+load_f f11, 13 * portFPU_REG_SIZE( sp )
+load_f f12, 14 * portFPU_REG_SIZE( sp )
+load_f f13, 15 * portFPU_REG_SIZE( sp )
+load_f f14, 16 * portFPU_REG_SIZE( sp )
+load_f f15, 17 * portFPU_REG_SIZE( sp )
+load_f f16, 18 * portFPU_REG_SIZE( sp )
+load_f f17, 19 * portFPU_REG_SIZE( sp )
+load_f f18, 20 * portFPU_REG_SIZE( sp )
+load_f f19, 21 * portFPU_REG_SIZE( sp )
+load_f f20, 22 * portFPU_REG_SIZE( sp )
+load_f f21, 23 * portFPU_REG_SIZE( sp )
+load_f f22, 24 * portFPU_REG_SIZE( sp )
+load_f f23, 25 * portFPU_REG_SIZE( sp )
+load_f f24, 26 * portFPU_REG_SIZE( sp )
+load_f f25, 27 * portFPU_REG_SIZE( sp )
+load_f f26, 28 * portFPU_REG_SIZE( sp )
+load_f f27, 29 * portFPU_REG_SIZE( sp )
+load_f f28, 30 * portFPU_REG_SIZE( sp )
+load_f f29, 31 * portFPU_REG_SIZE( sp )
+load_f f30, 32 * portFPU_REG_SIZE( sp )
+load_f f31, 33 * portFPU_REG_SIZE( sp )
+load_x t0,  34 * portFPU_REG_SIZE( sp )
 csrw fcsr, t0
 addi sp, sp, ( portFPU_CONTEXT_SIZE )
     .endm

From 64fd9291ef668d0f3695771f0ce596d5e6c75802 Mon Sep 17 00:00:00 2001
From: Saiiijchan <49641410+Saiiijchan@users.noreply.github.com>
Date: Thu, 13 Mar 2025 23:40:51 +0800
Subject: [PATCH 395/424] RISC-V: refine fpu reg context offset (#1257)

RISC-V: refine fpu reg context offset

pxCode and mstatus stored at index 0 and 1 are based on XLEN.
Therefore, the correct formula to calculate the FPU register index
should be ( ( 2 * portWORD_SIZE ) + ( regIndex * portFPU_REG_SIZE ) ).

Signed-off-by: wangfei_chen <wangfei_chen@realsil.com.cn>
---
 portable/GCC/RISC-V/portContext.h | 133 +++++++++++++++---------------
 1 file changed, 67 insertions(+), 66 deletions(-)

diff --git a/portable/GCC/RISC-V/portContext.h b/portable/GCC/RISC-V/portContext.h
index d191b4aea..aa57f3ec1 100644
--- a/portable/GCC/RISC-V/portContext.h
+++ b/portable/GCC/RISC-V/portContext.h
@@ -87,6 +87,7 @@
 
         #define portFPU_REG_SIZE                ( __riscv_flen / 8 )
         #define portFPU_REG_COUNT               33 /* 32 Floating point registers plus one CSR. */
+        #define portFPU_REG_OFFSET( regIndex )  ( ( 2 * portWORD_SIZE ) + ( regIndex * portFPU_REG_SIZE ) )
         #define portFPU_CONTEXT_SIZE            ( portFPU_REG_SIZE * portFPU_REG_COUNT )
     #else
         #error configENABLE_FPU must not be set to 1 if the hardwar does not have FPU
@@ -103,78 +104,78 @@
     .macro portcontexSAVE_FPU_CONTEXT
 addi sp, sp, -( portFPU_CONTEXT_SIZE )
 /* Store the FPU registers. */
-store_f f0,  2  * portFPU_REG_SIZE( sp )
-store_f f1,  3  * portFPU_REG_SIZE( sp )
-store_f f2,  4  * portFPU_REG_SIZE( sp )
-store_f f3,  5  * portFPU_REG_SIZE( sp )
-store_f f4,  6  * portFPU_REG_SIZE( sp )
-store_f f5,  7  * portFPU_REG_SIZE( sp )
-store_f f6,  8  * portFPU_REG_SIZE( sp )
-store_f f7,  9  * portFPU_REG_SIZE( sp )
-store_f f8,  10 * portFPU_REG_SIZE( sp )
-store_f f9,  11 * portFPU_REG_SIZE( sp )
-store_f f10, 12 * portFPU_REG_SIZE( sp )
-store_f f11, 13 * portFPU_REG_SIZE( sp )
-store_f f12, 14 * portFPU_REG_SIZE( sp )
-store_f f13, 15 * portFPU_REG_SIZE( sp )
-store_f f14, 16 * portFPU_REG_SIZE( sp )
-store_f f15, 17 * portFPU_REG_SIZE( sp )
-store_f f16, 18 * portFPU_REG_SIZE( sp )
-store_f f17, 19 * portFPU_REG_SIZE( sp )
-store_f f18, 20 * portFPU_REG_SIZE( sp )
-store_f f19, 21 * portFPU_REG_SIZE( sp )
-store_f f20, 22 * portFPU_REG_SIZE( sp )
-store_f f21, 23 * portFPU_REG_SIZE( sp )
-store_f f22, 24 * portFPU_REG_SIZE( sp )
-store_f f23, 25 * portFPU_REG_SIZE( sp )
-store_f f24, 26 * portFPU_REG_SIZE( sp )
-store_f f25, 27 * portFPU_REG_SIZE( sp )
-store_f f26, 28 * portFPU_REG_SIZE( sp )
-store_f f27, 29 * portFPU_REG_SIZE( sp )
-store_f f28, 30 * portFPU_REG_SIZE( sp )
-store_f f29, 31 * portFPU_REG_SIZE( sp )
-store_f f30, 32 * portFPU_REG_SIZE( sp )
-store_f f31, 33 * portFPU_REG_SIZE( sp )
+store_f f0,  portFPU_REG_OFFSET( 0  )( sp )
+store_f f1,  portFPU_REG_OFFSET( 1  )( sp )
+store_f f2,  portFPU_REG_OFFSET( 2  )( sp )
+store_f f3,  portFPU_REG_OFFSET( 3  )( sp )
+store_f f4,  portFPU_REG_OFFSET( 4  )( sp )
+store_f f5,  portFPU_REG_OFFSET( 5  )( sp )
+store_f f6,  portFPU_REG_OFFSET( 6  )( sp )
+store_f f7,  portFPU_REG_OFFSET( 7  )( sp )
+store_f f8,  portFPU_REG_OFFSET( 8  )( sp )
+store_f f9,  portFPU_REG_OFFSET( 9  )( sp )
+store_f f10, portFPU_REG_OFFSET( 10 )( sp )
+store_f f11, portFPU_REG_OFFSET( 11 )( sp )
+store_f f12, portFPU_REG_OFFSET( 12 )( sp )
+store_f f13, portFPU_REG_OFFSET( 13 )( sp )
+store_f f14, portFPU_REG_OFFSET( 14 )( sp )
+store_f f15, portFPU_REG_OFFSET( 15 )( sp )
+store_f f16, portFPU_REG_OFFSET( 16 )( sp )
+store_f f17, portFPU_REG_OFFSET( 17 )( sp )
+store_f f18, portFPU_REG_OFFSET( 18 )( sp )
+store_f f19, portFPU_REG_OFFSET( 19 )( sp )
+store_f f20, portFPU_REG_OFFSET( 20 )( sp )
+store_f f21, portFPU_REG_OFFSET( 21 )( sp )
+store_f f22, portFPU_REG_OFFSET( 22 )( sp )
+store_f f23, portFPU_REG_OFFSET( 23 )( sp )
+store_f f24, portFPU_REG_OFFSET( 24 )( sp )
+store_f f25, portFPU_REG_OFFSET( 25 )( sp )
+store_f f26, portFPU_REG_OFFSET( 26 )( sp )
+store_f f27, portFPU_REG_OFFSET( 27 )( sp )
+store_f f28, portFPU_REG_OFFSET( 28 )( sp )
+store_f f29, portFPU_REG_OFFSET( 29 )( sp )
+store_f f30, portFPU_REG_OFFSET( 30 )( sp )
+store_f f31, portFPU_REG_OFFSET( 31 )( sp )
 csrr t0, fcsr
-store_x t0,  34 * portFPU_REG_SIZE( sp )
+store_x t0,  portFPU_REG_OFFSET( 32 )( sp )
     .endm
 /*-----------------------------------------------------------*/
 
     .macro portcontextRESTORE_FPU_CONTEXT
 /* Restore the FPU registers. */
-load_f f0,  2  * portFPU_REG_SIZE( sp )
-load_f f1,  3  * portFPU_REG_SIZE( sp )
-load_f f2,  4  * portFPU_REG_SIZE( sp )
-load_f f3,  5  * portFPU_REG_SIZE( sp )
-load_f f4,  6  * portFPU_REG_SIZE( sp )
-load_f f5,  7  * portFPU_REG_SIZE( sp )
-load_f f6,  8  * portFPU_REG_SIZE( sp )
-load_f f7,  9  * portFPU_REG_SIZE( sp )
-load_f f8,  10 * portFPU_REG_SIZE( sp )
-load_f f9,  11 * portFPU_REG_SIZE( sp )
-load_f f10, 12 * portFPU_REG_SIZE( sp )
-load_f f11, 13 * portFPU_REG_SIZE( sp )
-load_f f12, 14 * portFPU_REG_SIZE( sp )
-load_f f13, 15 * portFPU_REG_SIZE( sp )
-load_f f14, 16 * portFPU_REG_SIZE( sp )
-load_f f15, 17 * portFPU_REG_SIZE( sp )
-load_f f16, 18 * portFPU_REG_SIZE( sp )
-load_f f17, 19 * portFPU_REG_SIZE( sp )
-load_f f18, 20 * portFPU_REG_SIZE( sp )
-load_f f19, 21 * portFPU_REG_SIZE( sp )
-load_f f20, 22 * portFPU_REG_SIZE( sp )
-load_f f21, 23 * portFPU_REG_SIZE( sp )
-load_f f22, 24 * portFPU_REG_SIZE( sp )
-load_f f23, 25 * portFPU_REG_SIZE( sp )
-load_f f24, 26 * portFPU_REG_SIZE( sp )
-load_f f25, 27 * portFPU_REG_SIZE( sp )
-load_f f26, 28 * portFPU_REG_SIZE( sp )
-load_f f27, 29 * portFPU_REG_SIZE( sp )
-load_f f28, 30 * portFPU_REG_SIZE( sp )
-load_f f29, 31 * portFPU_REG_SIZE( sp )
-load_f f30, 32 * portFPU_REG_SIZE( sp )
-load_f f31, 33 * portFPU_REG_SIZE( sp )
-load_x t0,  34 * portFPU_REG_SIZE( sp )
+load_f f0,  portFPU_REG_OFFSET( 0  )( sp )
+load_f f1,  portFPU_REG_OFFSET( 1  )( sp )
+load_f f2,  portFPU_REG_OFFSET( 2  )( sp )
+load_f f3,  portFPU_REG_OFFSET( 3  )( sp )
+load_f f4,  portFPU_REG_OFFSET( 4  )( sp )
+load_f f5,  portFPU_REG_OFFSET( 5  )( sp )
+load_f f6,  portFPU_REG_OFFSET( 6  )( sp )
+load_f f7,  portFPU_REG_OFFSET( 7  )( sp )
+load_f f8,  portFPU_REG_OFFSET( 8  )( sp )
+load_f f9,  portFPU_REG_OFFSET( 9  )( sp )
+load_f f10, portFPU_REG_OFFSET( 10 )( sp )
+load_f f11, portFPU_REG_OFFSET( 11 )( sp )
+load_f f12, portFPU_REG_OFFSET( 12 )( sp )
+load_f f13, portFPU_REG_OFFSET( 13 )( sp )
+load_f f14, portFPU_REG_OFFSET( 14 )( sp )
+load_f f15, portFPU_REG_OFFSET( 15 )( sp )
+load_f f16, portFPU_REG_OFFSET( 16 )( sp )
+load_f f17, portFPU_REG_OFFSET( 17 )( sp )
+load_f f18, portFPU_REG_OFFSET( 18 )( sp )
+load_f f19, portFPU_REG_OFFSET( 19 )( sp )
+load_f f20, portFPU_REG_OFFSET( 20 )( sp )
+load_f f21, portFPU_REG_OFFSET( 21 )( sp )
+load_f f22, portFPU_REG_OFFSET( 22 )( sp )
+load_f f23, portFPU_REG_OFFSET( 23 )( sp )
+load_f f24, portFPU_REG_OFFSET( 24 )( sp )
+load_f f25, portFPU_REG_OFFSET( 25 )( sp )
+load_f f26, portFPU_REG_OFFSET( 26 )( sp )
+load_f f27, portFPU_REG_OFFSET( 27 )( sp )
+load_f f28, portFPU_REG_OFFSET( 28 )( sp )
+load_f f29, portFPU_REG_OFFSET( 29 )( sp )
+load_f f30, portFPU_REG_OFFSET( 30 )( sp )
+load_f f31, portFPU_REG_OFFSET( 31 )( sp )
+load_x t0,  portFPU_REG_OFFSET( 32 )( sp )
 csrw fcsr, t0
 addi sp, sp, ( portFPU_CONTEXT_SIZE )
     .endm

From dacce186cfa4badc412b70f47f9b7c41acf7d89d Mon Sep 17 00:00:00 2001
From: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Date: Mon, 17 Mar 2025 16:41:11 +0530
Subject: [PATCH 396/424] Use UBaseType_t for
 ullMachineTimerCompareRegisterBase (#1258)

Use architecture-dependent UBaseType_t instead of fixed type for
ullMachineTimerCompareRegisterBase. This type is defined to uint32_t or
uint64_t based on XLEN, resolving warnings on 32-bit platforms.

Reported by landretk@ on the PR FreeRTOS/FreeRTOS-Kernel#1176.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 portable/GCC/RISC-V/port.c | 2 +-
 portable/IAR/RISC-V/port.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/portable/GCC/RISC-V/port.c b/portable/GCC/RISC-V/port.c
index e52fe8b12..8fe7a25d5 100644
--- a/portable/GCC/RISC-V/port.c
+++ b/portable/GCC/RISC-V/port.c
@@ -90,7 +90,7 @@ void vPortSetupTimerInterrupt( void ) __attribute__( ( weak ) );
 uint64_t ullNextTime = 0ULL;
 const uint64_t * pullNextTime = &ullNextTime;
 const size_t uxTimerIncrementsForOneTick = ( size_t ) ( ( configCPU_CLOCK_HZ ) / ( configTICK_RATE_HZ ) ); /* Assumes increment won't go over 32-bits. */
-uint64_t const ullMachineTimerCompareRegisterBase = configMTIMECMP_BASE_ADDRESS;
+UBaseType_t const ullMachineTimerCompareRegisterBase = configMTIMECMP_BASE_ADDRESS;
 volatile uint64_t * pullMachineTimerCompareRegister = NULL;
 
 /* Holds the critical nesting value - deliberately non-zero at start up to
diff --git a/portable/IAR/RISC-V/port.c b/portable/IAR/RISC-V/port.c
index 8040022bd..820423ec5 100644
--- a/portable/IAR/RISC-V/port.c
+++ b/portable/IAR/RISC-V/port.c
@@ -98,7 +98,7 @@ void vPortSetupTimerInterrupt( void ) __attribute__( ( weak ) );
 uint64_t ullNextTime = 0ULL;
 const uint64_t * pullNextTime = &ullNextTime;
 const size_t uxTimerIncrementsForOneTick = ( size_t ) ( ( configCPU_CLOCK_HZ ) / ( configTICK_RATE_HZ ) ); /* Assumes increment won't go over 32-bits. */
-uint64_t const ullMachineTimerCompareRegisterBase = configMTIMECMP_BASE_ADDRESS;
+UBaseType_t const ullMachineTimerCompareRegisterBase = configMTIMECMP_BASE_ADDRESS;
 volatile uint64_t * pullMachineTimerCompareRegister = NULL;
 
 /* Holds the critical nesting value - deliberately non-zero at start up to

From b9aa0645913ac346b0da2d1de662cda98467b471 Mon Sep 17 00:00:00 2001
From: ErickReyesR <ErickReyesR@users.noreply.github.com>
Date: Wed, 19 Mar 2025 02:31:22 -0700
Subject: [PATCH 397/424] FreeRTOS MPU: Remove MPU region number check (#1261)

FreeRTOS MPU: Remove MPU region number check

This change removes the assertion and runtime check that enforces
matching between configTOTAL_MPU_REGIONS and physical MPU
regions,. This allows applications running on devices with 16 MPU
regions to manage 8 MPU regions while leaving the remaining 8
for the kernel.

Signed-off-by: Erick Reyes <erickreyes@google.com>
---
 portable/ARMv8M/non_secure/port.c            | 468 +++++++++----------
 portable/GCC/ARM_CM23/non_secure/port.c      | 468 +++++++++----------
 portable/GCC/ARM_CM23_NTZ/non_secure/port.c  | 468 +++++++++----------
 portable/GCC/ARM_CM33/non_secure/port.c      | 468 +++++++++----------
 portable/GCC/ARM_CM33_NTZ/non_secure/port.c  | 468 +++++++++----------
 portable/GCC/ARM_CM35P/non_secure/port.c     | 468 +++++++++----------
 portable/GCC/ARM_CM35P_NTZ/non_secure/port.c | 468 +++++++++----------
 portable/GCC/ARM_CM55/non_secure/port.c      | 468 +++++++++----------
 portable/GCC/ARM_CM55_NTZ/non_secure/port.c  | 468 +++++++++----------
 portable/GCC/ARM_CM85/non_secure/port.c      | 468 +++++++++----------
 portable/GCC/ARM_CM85_NTZ/non_secure/port.c  | 468 +++++++++----------
 portable/IAR/ARM_CM23/non_secure/port.c      | 468 +++++++++----------
 portable/IAR/ARM_CM23_NTZ/non_secure/port.c  | 468 +++++++++----------
 portable/IAR/ARM_CM33/non_secure/port.c      | 468 +++++++++----------
 portable/IAR/ARM_CM33_NTZ/non_secure/port.c  | 468 +++++++++----------
 portable/IAR/ARM_CM35P/non_secure/port.c     | 468 +++++++++----------
 portable/IAR/ARM_CM35P_NTZ/non_secure/port.c | 468 +++++++++----------
 portable/IAR/ARM_CM55/non_secure/port.c      | 468 +++++++++----------
 portable/IAR/ARM_CM55_NTZ/non_secure/port.c  | 468 +++++++++----------
 portable/IAR/ARM_CM85/non_secure/port.c      | 468 +++++++++----------
 portable/IAR/ARM_CM85_NTZ/non_secure/port.c  | 468 +++++++++----------
 21 files changed, 4809 insertions(+), 5019 deletions(-)

diff --git a/portable/ARMv8M/non_secure/port.c b/portable/ARMv8M/non_secure/port.c
index b2fd7e518..a7fb054bc 100644
--- a/portable/ARMv8M/non_secure/port.c
+++ b/portable/ARMv8M/non_secure/port.c
@@ -145,13 +145,13 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the FPU.
  */
-#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 )              /* Coprocessor Access Control Register. */
+#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */
 #define portCPACR_CP10_VALUE    ( 3UL )
 #define portCPACR_CP11_VALUE    portCPACR_CP10_VALUE
 #define portCPACR_CP10_POS      ( 20UL )
 #define portCPACR_CP11_POS      ( 22UL )
 
-#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 )              /* Floating Point Context Control Register. */
+#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */
 #define portFPCCR_ASPEN_POS     ( 31UL )
 #define portFPCCR_ASPEN_MASK    ( 1UL << portFPCCR_ASPEN_POS )
 #define portFPCCR_LSPEN_POS     ( 30UL )
@@ -188,8 +188,8 @@ typedef void ( * portISR_t )( void );
 #define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
 #define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
 #define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
@@ -230,8 +230,8 @@ typedef void ( * portISR_t )( void );
 
 #if ( portARMV8M_MINOR_VERSION >= 1 )
 
-/* Enable Privileged eXecute Never MPU attribute for the selected memory
- * region. */
+    /* Enable Privileged eXecute Never MPU attribute for the selected memory
+     * region. */
     #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER    ( 1UL << 4UL )
 #endif /* portARMV8M_MINOR_VERSION >= 1 */
 
@@ -241,9 +241,6 @@ typedef void ( * portISR_t )( void );
 /* Enable MPU. */
 #define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
 
-/* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
-
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
 #define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \
@@ -291,37 +288,37 @@ typedef void ( * portISR_t )( void );
 
 #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
 
-/**
- * @brief Initial EXC_RETURN value.
- *
- *     FF         FF         FF         FD
- * 1111 1111  1111 1111  1111 1111  1111 1101
- *
- * Bit[6] - 1 --> The exception was taken from the Secure state.
- * Bit[5] - 1 --> Do not skip stacking of additional state context.
- * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
- * Bit[3] - 1 --> Return to the Thread mode.
- * Bit[2] - 1 --> Restore registers from the process stack.
- * Bit[1] - 0 --> Reserved, 0.
- * Bit[0] - 1 --> The exception was taken to the Secure state.
- */
+    /**
+     * @brief Initial EXC_RETURN value.
+     *
+     *     FF         FF         FF         FD
+     * 1111 1111  1111 1111  1111 1111  1111 1101
+     *
+     * Bit[6] - 1 --> The exception was taken from the Secure state.
+     * Bit[5] - 1 --> Do not skip stacking of additional state context.
+     * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+     * Bit[3] - 1 --> Return to the Thread mode.
+     * Bit[2] - 1 --> Restore registers from the process stack.
+     * Bit[1] - 0 --> Reserved, 0.
+     * Bit[0] - 1 --> The exception was taken to the Secure state.
+     */
     #define portINITIAL_EXC_RETURN    ( 0xfffffffd )
 #else
 
-/**
- * @brief Initial EXC_RETURN value.
- *
- *     FF         FF         FF         BC
- * 1111 1111  1111 1111  1111 1111  1011 1100
- *
- * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
- * Bit[5] - 1 --> Do not skip stacking of additional state context.
- * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
- * Bit[3] - 1 --> Return to the Thread mode.
- * Bit[2] - 1 --> Restore registers from the process stack.
- * Bit[1] - 0 --> Reserved, 0.
- * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
- */
+    /**
+     * @brief Initial EXC_RETURN value.
+     *
+     *     FF         FF         FF         BC
+     * 1111 1111  1111 1111  1111 1111  1011 1100
+     *
+     * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+     * Bit[5] - 1 --> Do not skip stacking of additional state context.
+     * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+     * Bit[3] - 1 --> Return to the Thread mode.
+     * Bit[2] - 1 --> Restore registers from the process stack.
+     * Bit[1] - 0 --> Reserved, 0.
+     * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+     */
     #define portINITIAL_EXC_RETURN    ( 0xffffffbc )
 #endif /* configRUN_FREERTOS_SECURE_ONLY */
 
@@ -401,49 +398,49 @@ static void prvTaskExitError( void );
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Extract MPU region's access permissions from the Region Base Address
- * Register (RBAR) value.
- *
- * @param ulRBARValue RBAR value for the MPU region.
- *
- * @return uint32_t Access permissions.
- */
+    /**
+     * @brief Extract MPU region's access permissions from the Region Base Address
+     * Register (RBAR) value.
+     *
+     * @param ulRBARValue RBAR value for the MPU region.
+     *
+     * @return uint32_t Access permissions.
+     */
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Setup the Memory Protection Unit (MPU).
- */
+    /**
+     * @brief Setup the Memory Protection Unit (MPU).
+     */
     static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_MPU */
 
 #if ( configENABLE_FPU == 1 )
 
-/**
- * @brief Setup the Floating Point Unit (FPU).
- */
+    /**
+     * @brief Setup the Floating Point Unit (FPU).
+     */
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
 #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
-/**
- * @brief Configures PACBTI features.
- *
- * This function configures the Pointer Authentication, and Branch Target
- * Identification security features as per the user configuration. It returns
- * the value of the special purpose CONTROL register accordingly, and optionally
- * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
- * architecture based) target supports PACBTI security feature.
- *
- * @param xWriteControlRegister Used to control whether the special purpose
- * CONTROL register should be updated or not.
- *
- * @return CONTROL register value according to the configured PACBTI option.
- */
+    /**
+     * @brief Configures PACBTI features.
+     *
+     * This function configures the Pointer Authentication, and Branch Target
+     * Identification security features as per the user configuration. It returns
+     * the value of the special purpose CONTROL register accordingly, and optionally
+     * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
+     * architecture based) target supports PACBTI security feature.
+     *
+     * @param xWriteControlRegister Used to control whether the special purpose
+     * CONTROL register should be updated or not.
+     *
+     * @return CONTROL register value according to the configured PACBTI option.
+     */
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
 
 #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
@@ -491,14 +488,14 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Sets up the system call stack so that upon returning from
- * SVC, the system call stack is used.
- *
- * @param pulTaskStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
- * @param ucSystemCallNumber The system call number of the system call.
- */
+    /**
+     * @brief Sets up the system call stack so that upon returning from
+     * SVC, the system call stack is used.
+     *
+     * @param pulTaskStack The current SP when the SVC was raised.
+     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+     * @param ucSystemCallNumber The system call number of the system call.
+     */
     void vSystemCallEnter( uint32_t * pulTaskStack,
                            uint32_t ulLR,
                            uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION;
@@ -507,22 +504,22 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Raise SVC for exiting from a system call.
- */
+    /**
+     * @brief Raise SVC for exiting from a system call.
+     */
     void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Sets up the task stack so that upon returning from
- * SVC, the task stack is used again.
- *
- * @param pulSystemCallStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
- */
+    /**
+     * @brief Sets up the task stack so that upon returning from
+     * SVC, the task stack is used again.
+     *
+     * @param pulSystemCallStack The current SP when the SVC was raised.
+     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+     */
     void vSystemCallExit( uint32_t * pulSystemCallStack,
                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
@@ -530,11 +527,11 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Checks whether or not the calling task is privileged.
- *
- * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
- */
+    /**
+     * @brief Checks whether or not the calling task is privileged.
+     *
+     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+     */
     BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
 
 #endif /* configENABLE_MPU == 1 */
@@ -542,9 +539,9 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief This variable is set to pdTRUE when the scheduler is started.
- */
+    /**
+     * @brief This variable is set to pdTRUE when the scheduler is started.
+     */
     PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@@ -557,10 +554,10 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-/**
- * @brief Saved as part of the task context to indicate which context the
- * task is using on the secure side.
- */
+    /**
+     * @brief Saved as part of the task context to indicate which context the
+     * task is using on the secure side.
+     */
     PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
 #endif /* configENABLE_TRUSTZONE */
 
@@ -579,21 +576,21 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
 
-/**
- * @brief The number of SysTick increments that make up one tick period.
- */
+    /**
+     * @brief The number of SysTick increments that make up one tick period.
+     */
     PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0;
 
-/**
- * @brief The maximum number of tick periods that can be suppressed is
- * limited by the 24 bit resolution of the SysTick timer.
- */
+    /**
+     * @brief The maximum number of tick periods that can be suppressed is
+     * limited by the 24 bit resolution of the SysTick timer.
+     */
     PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0;
 
-/**
- * @brief Compensate for the CPU cycles that pass while the SysTick is
- * stopped (low power functionality only).
- */
+    /**
+     * @brief Compensate for the CPU cycles that pass while the SysTick is
+     * stopped (low power functionality only).
+     */
     PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0;
 #endif /* configUSE_TICKLESS_IDLE */
 /*-----------------------------------------------------------*/
@@ -925,64 +922,57 @@ static void prvTaskExitError( void )
         /* The only permitted number of regions are 8 or 16. */
         configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
 
-        /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
-        configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
+        /* MAIR0 - Index 0. */
+        portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+        /* MAIR0 - Index 1. */
+        portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
 
-        /* Check that the MPU is present. */
-        if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
-        {
-            /* MAIR0 - Index 0. */
-            portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
-            /* MAIR0 - Index 1. */
-            portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+        /* Setup privileged flash as Read Only so that privileged tasks can
+         * read it but not modify. */
+        portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_PRIVILEGED_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup privileged flash as Read Only so that privileged tasks can
-             * read it but not modify. */
-            portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_PRIVILEGED_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup unprivileged flash as Read Only by both privileged and
+         * unprivileged tasks. All tasks can read it but no-one can modify. */
+        portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup unprivileged flash as Read Only by both privileged and
-             * unprivileged tasks. All tasks can read it but no-one can modify. */
-            portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup unprivileged syscalls flash as Read Only by both privileged
+         * and unprivileged tasks. All tasks can read it but no-one can modify. */
+        portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup unprivileged syscalls flash as Read Only by both privileged
-             * and unprivileged tasks. All tasks can read it but no-one can modify. */
-            portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup RAM containing kernel data for privileged access only. */
+        portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+                           ( portMPU_REGION_EXECUTE_NEVER );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup RAM containing kernel data for privileged access only. */
-            portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
-                               ( portMPU_REGION_EXECUTE_NEVER );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Enable mem fault. */
+        portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;
 
-            /* Enable mem fault. */
-            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;
-
-            /* Enable MPU with privileged background access i.e. unmapped
-             * regions have privileged access. */
-            portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
-        }
+        /* Enable MPU with privileged background access i.e. unmapped
+         * regions have privileged access. */
+        portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
     }
 
 #endif /* configENABLE_MPU */
@@ -1108,47 +1098,47 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
     switch( ucSVCNumber )
     {
-        #if ( configENABLE_TRUSTZONE == 1 )
-            case portSVC_ALLOCATE_SECURE_CONTEXT:
+    #if ( configENABLE_TRUSTZONE == 1 )
+        case portSVC_ALLOCATE_SECURE_CONTEXT:
 
-                /* R0 contains the stack size passed as parameter to the
-                 * vPortAllocateSecureContext function. */
-                ulR0 = pulCallerStackAddress[ 0 ];
+            /* R0 contains the stack size passed as parameter to the
+             * vPortAllocateSecureContext function. */
+            ulR0 = pulCallerStackAddress[ 0 ];
 
-                #if ( configENABLE_MPU == 1 )
-                {
-                    /* Read the CONTROL register value. */
-                    __asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
+            #if ( configENABLE_MPU == 1 )
+            {
+                /* Read the CONTROL register value. */
+                __asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
 
-                    /* The task that raised the SVC is privileged if Bit[0]
-                     * in the CONTROL register is 0. */
-                    ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+                /* The task that raised the SVC is privileged if Bit[0]
+                 * in the CONTROL register is 0. */
+                ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
 
-                    /* Allocate and load a context for the secure task. */
-                    xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
-                }
-                #else /* if ( configENABLE_MPU == 1 ) */
-                {
-                    /* Allocate and load a context for the secure task. */
-                    xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
-                }
-                #endif /* configENABLE_MPU */
+                /* Allocate and load a context for the secure task. */
+                xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
+            }
+            #else /* if ( configENABLE_MPU == 1 ) */
+            {
+                /* Allocate and load a context for the secure task. */
+                xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
+            }
+            #endif /* configENABLE_MPU */
 
-                configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );
-                SecureContext_LoadContext( xSecureContext, pxCurrentTCB );
-                break;
+            configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );
+            SecureContext_LoadContext( xSecureContext, pxCurrentTCB );
+            break;
 
-            case portSVC_FREE_SECURE_CONTEXT:
+        case portSVC_FREE_SECURE_CONTEXT:
 
-                /* R0 contains TCB being freed and R1 contains the secure
-                 * context handle to be freed. */
-                ulR0 = pulCallerStackAddress[ 0 ];
-                ulR1 = pulCallerStackAddress[ 1 ];
+            /* R0 contains TCB being freed and R1 contains the secure
+             * context handle to be freed. */
+            ulR0 = pulCallerStackAddress[ 0 ];
+            ulR1 = pulCallerStackAddress[ 1 ];
 
-                /* Free the secure context. */
-                SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );
-                break;
-        #endif /* configENABLE_TRUSTZONE */
+            /* Free the secure context. */
+            SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );
+            break;
+    #endif /* configENABLE_TRUSTZONE */
 
         case portSVC_START_SCHEDULER:
             #if ( configENABLE_TRUSTZONE == 1 )
@@ -1174,24 +1164,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             vRestoreContextOfFirstTask();
             break;
 
-            #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
-                case portSVC_RAISE_PRIVILEGE:
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+        case portSVC_RAISE_PRIVILEGE:
 
-                    /* Only raise the privilege, if the svc was raised from any of
-                     * the system calls. */
-                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
-                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
-                    {
-                        vRaisePrivilege();
-                    }
-                    break;
-            #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+            /* Only raise the privilege, if the svc was raised from any of
+             * the system calls. */
+            if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+                ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+            {
+                vRaisePrivilege();
+            }
+            break;
+    #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
-            #if ( configENABLE_MPU == 1 )
-                case portSVC_YIELD:
-                    vPortYield();
-                    break;
-            #endif /* configENABLE_MPU == 1 */
+    #if ( configENABLE_MPU == 1 )
+        case portSVC_YIELD:
+            vPortYield();
+            break;
+    #endif /* configENABLE_MPU == 1 */
 
         default:
             /* Incorrect SVC call. */
@@ -1518,21 +1508,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
         ulIndex++;
 
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters;            /* r0. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x01010101;                           /* r1. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x02020202;                           /* r2. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x03030303;                           /* r3. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x12121212;                           /* r12. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
         ulIndex++;
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode;                  /* PC. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR;                     /* xPSR. */
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
         ulIndex++;
 
         #if ( configENABLE_TRUSTZONE == 1 )
@@ -1543,7 +1533,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         #endif /* configENABLE_TRUSTZONE */
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
         ulIndex++;
 
         #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
@@ -1615,15 +1605,15 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
          * interrupt. */
         #if ( portPRELOAD_REGISTERS == 0 )
         {
-            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
+            pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-            pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
-            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-            pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
+            pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
+            *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */
+            pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */
             *pxTopOfStack = portINITIAL_EXC_RETURN;
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
@@ -1637,42 +1627,42 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #else /* portPRELOAD_REGISTERS */
         {
-            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
+            pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
+            *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
+            *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
+            *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
+            *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
+            *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
+            *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
+            *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
+            *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
+            *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
+            *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
+            *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
+            *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04. */
             pxTopOfStack--;
-            *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
+            *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxEndOfStack;            /* Slot used to hold this task's PSPLIM value. */
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
 
             #if ( configENABLE_TRUSTZONE == 1 )
             {
diff --git a/portable/GCC/ARM_CM23/non_secure/port.c b/portable/GCC/ARM_CM23/non_secure/port.c
index b2fd7e518..a7fb054bc 100644
--- a/portable/GCC/ARM_CM23/non_secure/port.c
+++ b/portable/GCC/ARM_CM23/non_secure/port.c
@@ -145,13 +145,13 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the FPU.
  */
-#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 )              /* Coprocessor Access Control Register. */
+#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */
 #define portCPACR_CP10_VALUE    ( 3UL )
 #define portCPACR_CP11_VALUE    portCPACR_CP10_VALUE
 #define portCPACR_CP10_POS      ( 20UL )
 #define portCPACR_CP11_POS      ( 22UL )
 
-#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 )              /* Floating Point Context Control Register. */
+#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */
 #define portFPCCR_ASPEN_POS     ( 31UL )
 #define portFPCCR_ASPEN_MASK    ( 1UL << portFPCCR_ASPEN_POS )
 #define portFPCCR_LSPEN_POS     ( 30UL )
@@ -188,8 +188,8 @@ typedef void ( * portISR_t )( void );
 #define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
 #define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
 #define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
@@ -230,8 +230,8 @@ typedef void ( * portISR_t )( void );
 
 #if ( portARMV8M_MINOR_VERSION >= 1 )
 
-/* Enable Privileged eXecute Never MPU attribute for the selected memory
- * region. */
+    /* Enable Privileged eXecute Never MPU attribute for the selected memory
+     * region. */
     #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER    ( 1UL << 4UL )
 #endif /* portARMV8M_MINOR_VERSION >= 1 */
 
@@ -241,9 +241,6 @@ typedef void ( * portISR_t )( void );
 /* Enable MPU. */
 #define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
 
-/* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
-
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
 #define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \
@@ -291,37 +288,37 @@ typedef void ( * portISR_t )( void );
 
 #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
 
-/**
- * @brief Initial EXC_RETURN value.
- *
- *     FF         FF         FF         FD
- * 1111 1111  1111 1111  1111 1111  1111 1101
- *
- * Bit[6] - 1 --> The exception was taken from the Secure state.
- * Bit[5] - 1 --> Do not skip stacking of additional state context.
- * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
- * Bit[3] - 1 --> Return to the Thread mode.
- * Bit[2] - 1 --> Restore registers from the process stack.
- * Bit[1] - 0 --> Reserved, 0.
- * Bit[0] - 1 --> The exception was taken to the Secure state.
- */
+    /**
+     * @brief Initial EXC_RETURN value.
+     *
+     *     FF         FF         FF         FD
+     * 1111 1111  1111 1111  1111 1111  1111 1101
+     *
+     * Bit[6] - 1 --> The exception was taken from the Secure state.
+     * Bit[5] - 1 --> Do not skip stacking of additional state context.
+     * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+     * Bit[3] - 1 --> Return to the Thread mode.
+     * Bit[2] - 1 --> Restore registers from the process stack.
+     * Bit[1] - 0 --> Reserved, 0.
+     * Bit[0] - 1 --> The exception was taken to the Secure state.
+     */
     #define portINITIAL_EXC_RETURN    ( 0xfffffffd )
 #else
 
-/**
- * @brief Initial EXC_RETURN value.
- *
- *     FF         FF         FF         BC
- * 1111 1111  1111 1111  1111 1111  1011 1100
- *
- * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
- * Bit[5] - 1 --> Do not skip stacking of additional state context.
- * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
- * Bit[3] - 1 --> Return to the Thread mode.
- * Bit[2] - 1 --> Restore registers from the process stack.
- * Bit[1] - 0 --> Reserved, 0.
- * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
- */
+    /**
+     * @brief Initial EXC_RETURN value.
+     *
+     *     FF         FF         FF         BC
+     * 1111 1111  1111 1111  1111 1111  1011 1100
+     *
+     * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+     * Bit[5] - 1 --> Do not skip stacking of additional state context.
+     * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+     * Bit[3] - 1 --> Return to the Thread mode.
+     * Bit[2] - 1 --> Restore registers from the process stack.
+     * Bit[1] - 0 --> Reserved, 0.
+     * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+     */
     #define portINITIAL_EXC_RETURN    ( 0xffffffbc )
 #endif /* configRUN_FREERTOS_SECURE_ONLY */
 
@@ -401,49 +398,49 @@ static void prvTaskExitError( void );
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Extract MPU region's access permissions from the Region Base Address
- * Register (RBAR) value.
- *
- * @param ulRBARValue RBAR value for the MPU region.
- *
- * @return uint32_t Access permissions.
- */
+    /**
+     * @brief Extract MPU region's access permissions from the Region Base Address
+     * Register (RBAR) value.
+     *
+     * @param ulRBARValue RBAR value for the MPU region.
+     *
+     * @return uint32_t Access permissions.
+     */
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Setup the Memory Protection Unit (MPU).
- */
+    /**
+     * @brief Setup the Memory Protection Unit (MPU).
+     */
     static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_MPU */
 
 #if ( configENABLE_FPU == 1 )
 
-/**
- * @brief Setup the Floating Point Unit (FPU).
- */
+    /**
+     * @brief Setup the Floating Point Unit (FPU).
+     */
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
 #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
-/**
- * @brief Configures PACBTI features.
- *
- * This function configures the Pointer Authentication, and Branch Target
- * Identification security features as per the user configuration. It returns
- * the value of the special purpose CONTROL register accordingly, and optionally
- * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
- * architecture based) target supports PACBTI security feature.
- *
- * @param xWriteControlRegister Used to control whether the special purpose
- * CONTROL register should be updated or not.
- *
- * @return CONTROL register value according to the configured PACBTI option.
- */
+    /**
+     * @brief Configures PACBTI features.
+     *
+     * This function configures the Pointer Authentication, and Branch Target
+     * Identification security features as per the user configuration. It returns
+     * the value of the special purpose CONTROL register accordingly, and optionally
+     * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
+     * architecture based) target supports PACBTI security feature.
+     *
+     * @param xWriteControlRegister Used to control whether the special purpose
+     * CONTROL register should be updated or not.
+     *
+     * @return CONTROL register value according to the configured PACBTI option.
+     */
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
 
 #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
@@ -491,14 +488,14 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Sets up the system call stack so that upon returning from
- * SVC, the system call stack is used.
- *
- * @param pulTaskStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
- * @param ucSystemCallNumber The system call number of the system call.
- */
+    /**
+     * @brief Sets up the system call stack so that upon returning from
+     * SVC, the system call stack is used.
+     *
+     * @param pulTaskStack The current SP when the SVC was raised.
+     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+     * @param ucSystemCallNumber The system call number of the system call.
+     */
     void vSystemCallEnter( uint32_t * pulTaskStack,
                            uint32_t ulLR,
                            uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION;
@@ -507,22 +504,22 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Raise SVC for exiting from a system call.
- */
+    /**
+     * @brief Raise SVC for exiting from a system call.
+     */
     void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Sets up the task stack so that upon returning from
- * SVC, the task stack is used again.
- *
- * @param pulSystemCallStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
- */
+    /**
+     * @brief Sets up the task stack so that upon returning from
+     * SVC, the task stack is used again.
+     *
+     * @param pulSystemCallStack The current SP when the SVC was raised.
+     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+     */
     void vSystemCallExit( uint32_t * pulSystemCallStack,
                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
@@ -530,11 +527,11 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Checks whether or not the calling task is privileged.
- *
- * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
- */
+    /**
+     * @brief Checks whether or not the calling task is privileged.
+     *
+     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+     */
     BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
 
 #endif /* configENABLE_MPU == 1 */
@@ -542,9 +539,9 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief This variable is set to pdTRUE when the scheduler is started.
- */
+    /**
+     * @brief This variable is set to pdTRUE when the scheduler is started.
+     */
     PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@@ -557,10 +554,10 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-/**
- * @brief Saved as part of the task context to indicate which context the
- * task is using on the secure side.
- */
+    /**
+     * @brief Saved as part of the task context to indicate which context the
+     * task is using on the secure side.
+     */
     PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
 #endif /* configENABLE_TRUSTZONE */
 
@@ -579,21 +576,21 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
 
-/**
- * @brief The number of SysTick increments that make up one tick period.
- */
+    /**
+     * @brief The number of SysTick increments that make up one tick period.
+     */
     PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0;
 
-/**
- * @brief The maximum number of tick periods that can be suppressed is
- * limited by the 24 bit resolution of the SysTick timer.
- */
+    /**
+     * @brief The maximum number of tick periods that can be suppressed is
+     * limited by the 24 bit resolution of the SysTick timer.
+     */
     PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0;
 
-/**
- * @brief Compensate for the CPU cycles that pass while the SysTick is
- * stopped (low power functionality only).
- */
+    /**
+     * @brief Compensate for the CPU cycles that pass while the SysTick is
+     * stopped (low power functionality only).
+     */
     PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0;
 #endif /* configUSE_TICKLESS_IDLE */
 /*-----------------------------------------------------------*/
@@ -925,64 +922,57 @@ static void prvTaskExitError( void )
         /* The only permitted number of regions are 8 or 16. */
         configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
 
-        /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
-        configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
+        /* MAIR0 - Index 0. */
+        portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+        /* MAIR0 - Index 1. */
+        portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
 
-        /* Check that the MPU is present. */
-        if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
-        {
-            /* MAIR0 - Index 0. */
-            portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
-            /* MAIR0 - Index 1. */
-            portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+        /* Setup privileged flash as Read Only so that privileged tasks can
+         * read it but not modify. */
+        portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_PRIVILEGED_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup privileged flash as Read Only so that privileged tasks can
-             * read it but not modify. */
-            portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_PRIVILEGED_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup unprivileged flash as Read Only by both privileged and
+         * unprivileged tasks. All tasks can read it but no-one can modify. */
+        portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup unprivileged flash as Read Only by both privileged and
-             * unprivileged tasks. All tasks can read it but no-one can modify. */
-            portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup unprivileged syscalls flash as Read Only by both privileged
+         * and unprivileged tasks. All tasks can read it but no-one can modify. */
+        portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup unprivileged syscalls flash as Read Only by both privileged
-             * and unprivileged tasks. All tasks can read it but no-one can modify. */
-            portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup RAM containing kernel data for privileged access only. */
+        portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+                           ( portMPU_REGION_EXECUTE_NEVER );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup RAM containing kernel data for privileged access only. */
-            portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
-                               ( portMPU_REGION_EXECUTE_NEVER );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Enable mem fault. */
+        portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;
 
-            /* Enable mem fault. */
-            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;
-
-            /* Enable MPU with privileged background access i.e. unmapped
-             * regions have privileged access. */
-            portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
-        }
+        /* Enable MPU with privileged background access i.e. unmapped
+         * regions have privileged access. */
+        portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
     }
 
 #endif /* configENABLE_MPU */
@@ -1108,47 +1098,47 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
     switch( ucSVCNumber )
     {
-        #if ( configENABLE_TRUSTZONE == 1 )
-            case portSVC_ALLOCATE_SECURE_CONTEXT:
+    #if ( configENABLE_TRUSTZONE == 1 )
+        case portSVC_ALLOCATE_SECURE_CONTEXT:
 
-                /* R0 contains the stack size passed as parameter to the
-                 * vPortAllocateSecureContext function. */
-                ulR0 = pulCallerStackAddress[ 0 ];
+            /* R0 contains the stack size passed as parameter to the
+             * vPortAllocateSecureContext function. */
+            ulR0 = pulCallerStackAddress[ 0 ];
 
-                #if ( configENABLE_MPU == 1 )
-                {
-                    /* Read the CONTROL register value. */
-                    __asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
+            #if ( configENABLE_MPU == 1 )
+            {
+                /* Read the CONTROL register value. */
+                __asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
 
-                    /* The task that raised the SVC is privileged if Bit[0]
-                     * in the CONTROL register is 0. */
-                    ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+                /* The task that raised the SVC is privileged if Bit[0]
+                 * in the CONTROL register is 0. */
+                ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
 
-                    /* Allocate and load a context for the secure task. */
-                    xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
-                }
-                #else /* if ( configENABLE_MPU == 1 ) */
-                {
-                    /* Allocate and load a context for the secure task. */
-                    xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
-                }
-                #endif /* configENABLE_MPU */
+                /* Allocate and load a context for the secure task. */
+                xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
+            }
+            #else /* if ( configENABLE_MPU == 1 ) */
+            {
+                /* Allocate and load a context for the secure task. */
+                xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
+            }
+            #endif /* configENABLE_MPU */
 
-                configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );
-                SecureContext_LoadContext( xSecureContext, pxCurrentTCB );
-                break;
+            configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );
+            SecureContext_LoadContext( xSecureContext, pxCurrentTCB );
+            break;
 
-            case portSVC_FREE_SECURE_CONTEXT:
+        case portSVC_FREE_SECURE_CONTEXT:
 
-                /* R0 contains TCB being freed and R1 contains the secure
-                 * context handle to be freed. */
-                ulR0 = pulCallerStackAddress[ 0 ];
-                ulR1 = pulCallerStackAddress[ 1 ];
+            /* R0 contains TCB being freed and R1 contains the secure
+             * context handle to be freed. */
+            ulR0 = pulCallerStackAddress[ 0 ];
+            ulR1 = pulCallerStackAddress[ 1 ];
 
-                /* Free the secure context. */
-                SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );
-                break;
-        #endif /* configENABLE_TRUSTZONE */
+            /* Free the secure context. */
+            SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );
+            break;
+    #endif /* configENABLE_TRUSTZONE */
 
         case portSVC_START_SCHEDULER:
             #if ( configENABLE_TRUSTZONE == 1 )
@@ -1174,24 +1164,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             vRestoreContextOfFirstTask();
             break;
 
-            #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
-                case portSVC_RAISE_PRIVILEGE:
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+        case portSVC_RAISE_PRIVILEGE:
 
-                    /* Only raise the privilege, if the svc was raised from any of
-                     * the system calls. */
-                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
-                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
-                    {
-                        vRaisePrivilege();
-                    }
-                    break;
-            #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+            /* Only raise the privilege, if the svc was raised from any of
+             * the system calls. */
+            if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+                ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+            {
+                vRaisePrivilege();
+            }
+            break;
+    #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
-            #if ( configENABLE_MPU == 1 )
-                case portSVC_YIELD:
-                    vPortYield();
-                    break;
-            #endif /* configENABLE_MPU == 1 */
+    #if ( configENABLE_MPU == 1 )
+        case portSVC_YIELD:
+            vPortYield();
+            break;
+    #endif /* configENABLE_MPU == 1 */
 
         default:
             /* Incorrect SVC call. */
@@ -1518,21 +1508,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
         ulIndex++;
 
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters;            /* r0. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x01010101;                           /* r1. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x02020202;                           /* r2. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x03030303;                           /* r3. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x12121212;                           /* r12. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
         ulIndex++;
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode;                  /* PC. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR;                     /* xPSR. */
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
         ulIndex++;
 
         #if ( configENABLE_TRUSTZONE == 1 )
@@ -1543,7 +1533,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         #endif /* configENABLE_TRUSTZONE */
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
         ulIndex++;
 
         #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
@@ -1615,15 +1605,15 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
          * interrupt. */
         #if ( portPRELOAD_REGISTERS == 0 )
         {
-            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
+            pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-            pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
-            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-            pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
+            pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
+            *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */
+            pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */
             *pxTopOfStack = portINITIAL_EXC_RETURN;
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
@@ -1637,42 +1627,42 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #else /* portPRELOAD_REGISTERS */
         {
-            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
+            pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
+            *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
+            *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
+            *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
+            *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
+            *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
+            *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
+            *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
+            *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
+            *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
+            *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
+            *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
+            *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04. */
             pxTopOfStack--;
-            *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
+            *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxEndOfStack;            /* Slot used to hold this task's PSPLIM value. */
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
 
             #if ( configENABLE_TRUSTZONE == 1 )
             {
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
index b2fd7e518..a7fb054bc 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
@@ -145,13 +145,13 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the FPU.
  */
-#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 )              /* Coprocessor Access Control Register. */
+#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */
 #define portCPACR_CP10_VALUE    ( 3UL )
 #define portCPACR_CP11_VALUE    portCPACR_CP10_VALUE
 #define portCPACR_CP10_POS      ( 20UL )
 #define portCPACR_CP11_POS      ( 22UL )
 
-#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 )              /* Floating Point Context Control Register. */
+#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */
 #define portFPCCR_ASPEN_POS     ( 31UL )
 #define portFPCCR_ASPEN_MASK    ( 1UL << portFPCCR_ASPEN_POS )
 #define portFPCCR_LSPEN_POS     ( 30UL )
@@ -188,8 +188,8 @@ typedef void ( * portISR_t )( void );
 #define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
 #define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
 #define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
@@ -230,8 +230,8 @@ typedef void ( * portISR_t )( void );
 
 #if ( portARMV8M_MINOR_VERSION >= 1 )
 
-/* Enable Privileged eXecute Never MPU attribute for the selected memory
- * region. */
+    /* Enable Privileged eXecute Never MPU attribute for the selected memory
+     * region. */
     #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER    ( 1UL << 4UL )
 #endif /* portARMV8M_MINOR_VERSION >= 1 */
 
@@ -241,9 +241,6 @@ typedef void ( * portISR_t )( void );
 /* Enable MPU. */
 #define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
 
-/* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
-
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
 #define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \
@@ -291,37 +288,37 @@ typedef void ( * portISR_t )( void );
 
 #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
 
-/**
- * @brief Initial EXC_RETURN value.
- *
- *     FF         FF         FF         FD
- * 1111 1111  1111 1111  1111 1111  1111 1101
- *
- * Bit[6] - 1 --> The exception was taken from the Secure state.
- * Bit[5] - 1 --> Do not skip stacking of additional state context.
- * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
- * Bit[3] - 1 --> Return to the Thread mode.
- * Bit[2] - 1 --> Restore registers from the process stack.
- * Bit[1] - 0 --> Reserved, 0.
- * Bit[0] - 1 --> The exception was taken to the Secure state.
- */
+    /**
+     * @brief Initial EXC_RETURN value.
+     *
+     *     FF         FF         FF         FD
+     * 1111 1111  1111 1111  1111 1111  1111 1101
+     *
+     * Bit[6] - 1 --> The exception was taken from the Secure state.
+     * Bit[5] - 1 --> Do not skip stacking of additional state context.
+     * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+     * Bit[3] - 1 --> Return to the Thread mode.
+     * Bit[2] - 1 --> Restore registers from the process stack.
+     * Bit[1] - 0 --> Reserved, 0.
+     * Bit[0] - 1 --> The exception was taken to the Secure state.
+     */
     #define portINITIAL_EXC_RETURN    ( 0xfffffffd )
 #else
 
-/**
- * @brief Initial EXC_RETURN value.
- *
- *     FF         FF         FF         BC
- * 1111 1111  1111 1111  1111 1111  1011 1100
- *
- * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
- * Bit[5] - 1 --> Do not skip stacking of additional state context.
- * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
- * Bit[3] - 1 --> Return to the Thread mode.
- * Bit[2] - 1 --> Restore registers from the process stack.
- * Bit[1] - 0 --> Reserved, 0.
- * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
- */
+    /**
+     * @brief Initial EXC_RETURN value.
+     *
+     *     FF         FF         FF         BC
+     * 1111 1111  1111 1111  1111 1111  1011 1100
+     *
+     * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+     * Bit[5] - 1 --> Do not skip stacking of additional state context.
+     * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+     * Bit[3] - 1 --> Return to the Thread mode.
+     * Bit[2] - 1 --> Restore registers from the process stack.
+     * Bit[1] - 0 --> Reserved, 0.
+     * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+     */
     #define portINITIAL_EXC_RETURN    ( 0xffffffbc )
 #endif /* configRUN_FREERTOS_SECURE_ONLY */
 
@@ -401,49 +398,49 @@ static void prvTaskExitError( void );
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Extract MPU region's access permissions from the Region Base Address
- * Register (RBAR) value.
- *
- * @param ulRBARValue RBAR value for the MPU region.
- *
- * @return uint32_t Access permissions.
- */
+    /**
+     * @brief Extract MPU region's access permissions from the Region Base Address
+     * Register (RBAR) value.
+     *
+     * @param ulRBARValue RBAR value for the MPU region.
+     *
+     * @return uint32_t Access permissions.
+     */
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Setup the Memory Protection Unit (MPU).
- */
+    /**
+     * @brief Setup the Memory Protection Unit (MPU).
+     */
     static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_MPU */
 
 #if ( configENABLE_FPU == 1 )
 
-/**
- * @brief Setup the Floating Point Unit (FPU).
- */
+    /**
+     * @brief Setup the Floating Point Unit (FPU).
+     */
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
 #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
-/**
- * @brief Configures PACBTI features.
- *
- * This function configures the Pointer Authentication, and Branch Target
- * Identification security features as per the user configuration. It returns
- * the value of the special purpose CONTROL register accordingly, and optionally
- * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
- * architecture based) target supports PACBTI security feature.
- *
- * @param xWriteControlRegister Used to control whether the special purpose
- * CONTROL register should be updated or not.
- *
- * @return CONTROL register value according to the configured PACBTI option.
- */
+    /**
+     * @brief Configures PACBTI features.
+     *
+     * This function configures the Pointer Authentication, and Branch Target
+     * Identification security features as per the user configuration. It returns
+     * the value of the special purpose CONTROL register accordingly, and optionally
+     * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
+     * architecture based) target supports PACBTI security feature.
+     *
+     * @param xWriteControlRegister Used to control whether the special purpose
+     * CONTROL register should be updated or not.
+     *
+     * @return CONTROL register value according to the configured PACBTI option.
+     */
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
 
 #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
@@ -491,14 +488,14 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Sets up the system call stack so that upon returning from
- * SVC, the system call stack is used.
- *
- * @param pulTaskStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
- * @param ucSystemCallNumber The system call number of the system call.
- */
+    /**
+     * @brief Sets up the system call stack so that upon returning from
+     * SVC, the system call stack is used.
+     *
+     * @param pulTaskStack The current SP when the SVC was raised.
+     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+     * @param ucSystemCallNumber The system call number of the system call.
+     */
     void vSystemCallEnter( uint32_t * pulTaskStack,
                            uint32_t ulLR,
                            uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION;
@@ -507,22 +504,22 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Raise SVC for exiting from a system call.
- */
+    /**
+     * @brief Raise SVC for exiting from a system call.
+     */
     void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Sets up the task stack so that upon returning from
- * SVC, the task stack is used again.
- *
- * @param pulSystemCallStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
- */
+    /**
+     * @brief Sets up the task stack so that upon returning from
+     * SVC, the task stack is used again.
+     *
+     * @param pulSystemCallStack The current SP when the SVC was raised.
+     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+     */
     void vSystemCallExit( uint32_t * pulSystemCallStack,
                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
@@ -530,11 +527,11 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Checks whether or not the calling task is privileged.
- *
- * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
- */
+    /**
+     * @brief Checks whether or not the calling task is privileged.
+     *
+     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+     */
     BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
 
 #endif /* configENABLE_MPU == 1 */
@@ -542,9 +539,9 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief This variable is set to pdTRUE when the scheduler is started.
- */
+    /**
+     * @brief This variable is set to pdTRUE when the scheduler is started.
+     */
     PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@@ -557,10 +554,10 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-/**
- * @brief Saved as part of the task context to indicate which context the
- * task is using on the secure side.
- */
+    /**
+     * @brief Saved as part of the task context to indicate which context the
+     * task is using on the secure side.
+     */
     PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
 #endif /* configENABLE_TRUSTZONE */
 
@@ -579,21 +576,21 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
 
-/**
- * @brief The number of SysTick increments that make up one tick period.
- */
+    /**
+     * @brief The number of SysTick increments that make up one tick period.
+     */
     PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0;
 
-/**
- * @brief The maximum number of tick periods that can be suppressed is
- * limited by the 24 bit resolution of the SysTick timer.
- */
+    /**
+     * @brief The maximum number of tick periods that can be suppressed is
+     * limited by the 24 bit resolution of the SysTick timer.
+     */
     PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0;
 
-/**
- * @brief Compensate for the CPU cycles that pass while the SysTick is
- * stopped (low power functionality only).
- */
+    /**
+     * @brief Compensate for the CPU cycles that pass while the SysTick is
+     * stopped (low power functionality only).
+     */
     PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0;
 #endif /* configUSE_TICKLESS_IDLE */
 /*-----------------------------------------------------------*/
@@ -925,64 +922,57 @@ static void prvTaskExitError( void )
         /* The only permitted number of regions are 8 or 16. */
         configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
 
-        /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
-        configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
+        /* MAIR0 - Index 0. */
+        portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+        /* MAIR0 - Index 1. */
+        portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
 
-        /* Check that the MPU is present. */
-        if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
-        {
-            /* MAIR0 - Index 0. */
-            portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
-            /* MAIR0 - Index 1. */
-            portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+        /* Setup privileged flash as Read Only so that privileged tasks can
+         * read it but not modify. */
+        portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_PRIVILEGED_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup privileged flash as Read Only so that privileged tasks can
-             * read it but not modify. */
-            portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_PRIVILEGED_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup unprivileged flash as Read Only by both privileged and
+         * unprivileged tasks. All tasks can read it but no-one can modify. */
+        portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup unprivileged flash as Read Only by both privileged and
-             * unprivileged tasks. All tasks can read it but no-one can modify. */
-            portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup unprivileged syscalls flash as Read Only by both privileged
+         * and unprivileged tasks. All tasks can read it but no-one can modify. */
+        portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup unprivileged syscalls flash as Read Only by both privileged
-             * and unprivileged tasks. All tasks can read it but no-one can modify. */
-            portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup RAM containing kernel data for privileged access only. */
+        portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+                           ( portMPU_REGION_EXECUTE_NEVER );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup RAM containing kernel data for privileged access only. */
-            portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
-                               ( portMPU_REGION_EXECUTE_NEVER );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Enable mem fault. */
+        portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;
 
-            /* Enable mem fault. */
-            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;
-
-            /* Enable MPU with privileged background access i.e. unmapped
-             * regions have privileged access. */
-            portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
-        }
+        /* Enable MPU with privileged background access i.e. unmapped
+         * regions have privileged access. */
+        portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
     }
 
 #endif /* configENABLE_MPU */
@@ -1108,47 +1098,47 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
     switch( ucSVCNumber )
     {
-        #if ( configENABLE_TRUSTZONE == 1 )
-            case portSVC_ALLOCATE_SECURE_CONTEXT:
+    #if ( configENABLE_TRUSTZONE == 1 )
+        case portSVC_ALLOCATE_SECURE_CONTEXT:
 
-                /* R0 contains the stack size passed as parameter to the
-                 * vPortAllocateSecureContext function. */
-                ulR0 = pulCallerStackAddress[ 0 ];
+            /* R0 contains the stack size passed as parameter to the
+             * vPortAllocateSecureContext function. */
+            ulR0 = pulCallerStackAddress[ 0 ];
 
-                #if ( configENABLE_MPU == 1 )
-                {
-                    /* Read the CONTROL register value. */
-                    __asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
+            #if ( configENABLE_MPU == 1 )
+            {
+                /* Read the CONTROL register value. */
+                __asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
 
-                    /* The task that raised the SVC is privileged if Bit[0]
-                     * in the CONTROL register is 0. */
-                    ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+                /* The task that raised the SVC is privileged if Bit[0]
+                 * in the CONTROL register is 0. */
+                ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
 
-                    /* Allocate and load a context for the secure task. */
-                    xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
-                }
-                #else /* if ( configENABLE_MPU == 1 ) */
-                {
-                    /* Allocate and load a context for the secure task. */
-                    xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
-                }
-                #endif /* configENABLE_MPU */
+                /* Allocate and load a context for the secure task. */
+                xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
+            }
+            #else /* if ( configENABLE_MPU == 1 ) */
+            {
+                /* Allocate and load a context for the secure task. */
+                xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
+            }
+            #endif /* configENABLE_MPU */
 
-                configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );
-                SecureContext_LoadContext( xSecureContext, pxCurrentTCB );
-                break;
+            configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );
+            SecureContext_LoadContext( xSecureContext, pxCurrentTCB );
+            break;
 
-            case portSVC_FREE_SECURE_CONTEXT:
+        case portSVC_FREE_SECURE_CONTEXT:
 
-                /* R0 contains TCB being freed and R1 contains the secure
-                 * context handle to be freed. */
-                ulR0 = pulCallerStackAddress[ 0 ];
-                ulR1 = pulCallerStackAddress[ 1 ];
+            /* R0 contains TCB being freed and R1 contains the secure
+             * context handle to be freed. */
+            ulR0 = pulCallerStackAddress[ 0 ];
+            ulR1 = pulCallerStackAddress[ 1 ];
 
-                /* Free the secure context. */
-                SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );
-                break;
-        #endif /* configENABLE_TRUSTZONE */
+            /* Free the secure context. */
+            SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );
+            break;
+    #endif /* configENABLE_TRUSTZONE */
 
         case portSVC_START_SCHEDULER:
             #if ( configENABLE_TRUSTZONE == 1 )
@@ -1174,24 +1164,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             vRestoreContextOfFirstTask();
             break;
 
-            #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
-                case portSVC_RAISE_PRIVILEGE:
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+        case portSVC_RAISE_PRIVILEGE:
 
-                    /* Only raise the privilege, if the svc was raised from any of
-                     * the system calls. */
-                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
-                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
-                    {
-                        vRaisePrivilege();
-                    }
-                    break;
-            #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+            /* Only raise the privilege, if the svc was raised from any of
+             * the system calls. */
+            if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+                ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+            {
+                vRaisePrivilege();
+            }
+            break;
+    #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
-            #if ( configENABLE_MPU == 1 )
-                case portSVC_YIELD:
-                    vPortYield();
-                    break;
-            #endif /* configENABLE_MPU == 1 */
+    #if ( configENABLE_MPU == 1 )
+        case portSVC_YIELD:
+            vPortYield();
+            break;
+    #endif /* configENABLE_MPU == 1 */
 
         default:
             /* Incorrect SVC call. */
@@ -1518,21 +1508,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
         ulIndex++;
 
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters;            /* r0. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x01010101;                           /* r1. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x02020202;                           /* r2. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x03030303;                           /* r3. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x12121212;                           /* r12. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
         ulIndex++;
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode;                  /* PC. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR;                     /* xPSR. */
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
         ulIndex++;
 
         #if ( configENABLE_TRUSTZONE == 1 )
@@ -1543,7 +1533,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         #endif /* configENABLE_TRUSTZONE */
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
         ulIndex++;
 
         #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
@@ -1615,15 +1605,15 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
          * interrupt. */
         #if ( portPRELOAD_REGISTERS == 0 )
         {
-            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
+            pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-            pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
-            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-            pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
+            pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
+            *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */
+            pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */
             *pxTopOfStack = portINITIAL_EXC_RETURN;
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
@@ -1637,42 +1627,42 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #else /* portPRELOAD_REGISTERS */
         {
-            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
+            pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
+            *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
+            *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
+            *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
+            *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
+            *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
+            *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
+            *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
+            *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
+            *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
+            *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
+            *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
+            *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04. */
             pxTopOfStack--;
-            *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
+            *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxEndOfStack;            /* Slot used to hold this task's PSPLIM value. */
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
 
             #if ( configENABLE_TRUSTZONE == 1 )
             {
diff --git a/portable/GCC/ARM_CM33/non_secure/port.c b/portable/GCC/ARM_CM33/non_secure/port.c
index b2fd7e518..a7fb054bc 100644
--- a/portable/GCC/ARM_CM33/non_secure/port.c
+++ b/portable/GCC/ARM_CM33/non_secure/port.c
@@ -145,13 +145,13 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the FPU.
  */
-#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 )              /* Coprocessor Access Control Register. */
+#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */
 #define portCPACR_CP10_VALUE    ( 3UL )
 #define portCPACR_CP11_VALUE    portCPACR_CP10_VALUE
 #define portCPACR_CP10_POS      ( 20UL )
 #define portCPACR_CP11_POS      ( 22UL )
 
-#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 )              /* Floating Point Context Control Register. */
+#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */
 #define portFPCCR_ASPEN_POS     ( 31UL )
 #define portFPCCR_ASPEN_MASK    ( 1UL << portFPCCR_ASPEN_POS )
 #define portFPCCR_LSPEN_POS     ( 30UL )
@@ -188,8 +188,8 @@ typedef void ( * portISR_t )( void );
 #define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
 #define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
 #define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
@@ -230,8 +230,8 @@ typedef void ( * portISR_t )( void );
 
 #if ( portARMV8M_MINOR_VERSION >= 1 )
 
-/* Enable Privileged eXecute Never MPU attribute for the selected memory
- * region. */
+    /* Enable Privileged eXecute Never MPU attribute for the selected memory
+     * region. */
     #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER    ( 1UL << 4UL )
 #endif /* portARMV8M_MINOR_VERSION >= 1 */
 
@@ -241,9 +241,6 @@ typedef void ( * portISR_t )( void );
 /* Enable MPU. */
 #define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
 
-/* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
-
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
 #define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \
@@ -291,37 +288,37 @@ typedef void ( * portISR_t )( void );
 
 #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
 
-/**
- * @brief Initial EXC_RETURN value.
- *
- *     FF         FF         FF         FD
- * 1111 1111  1111 1111  1111 1111  1111 1101
- *
- * Bit[6] - 1 --> The exception was taken from the Secure state.
- * Bit[5] - 1 --> Do not skip stacking of additional state context.
- * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
- * Bit[3] - 1 --> Return to the Thread mode.
- * Bit[2] - 1 --> Restore registers from the process stack.
- * Bit[1] - 0 --> Reserved, 0.
- * Bit[0] - 1 --> The exception was taken to the Secure state.
- */
+    /**
+     * @brief Initial EXC_RETURN value.
+     *
+     *     FF         FF         FF         FD
+     * 1111 1111  1111 1111  1111 1111  1111 1101
+     *
+     * Bit[6] - 1 --> The exception was taken from the Secure state.
+     * Bit[5] - 1 --> Do not skip stacking of additional state context.
+     * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+     * Bit[3] - 1 --> Return to the Thread mode.
+     * Bit[2] - 1 --> Restore registers from the process stack.
+     * Bit[1] - 0 --> Reserved, 0.
+     * Bit[0] - 1 --> The exception was taken to the Secure state.
+     */
     #define portINITIAL_EXC_RETURN    ( 0xfffffffd )
 #else
 
-/**
- * @brief Initial EXC_RETURN value.
- *
- *     FF         FF         FF         BC
- * 1111 1111  1111 1111  1111 1111  1011 1100
- *
- * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
- * Bit[5] - 1 --> Do not skip stacking of additional state context.
- * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
- * Bit[3] - 1 --> Return to the Thread mode.
- * Bit[2] - 1 --> Restore registers from the process stack.
- * Bit[1] - 0 --> Reserved, 0.
- * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
- */
+    /**
+     * @brief Initial EXC_RETURN value.
+     *
+     *     FF         FF         FF         BC
+     * 1111 1111  1111 1111  1111 1111  1011 1100
+     *
+     * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+     * Bit[5] - 1 --> Do not skip stacking of additional state context.
+     * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+     * Bit[3] - 1 --> Return to the Thread mode.
+     * Bit[2] - 1 --> Restore registers from the process stack.
+     * Bit[1] - 0 --> Reserved, 0.
+     * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+     */
     #define portINITIAL_EXC_RETURN    ( 0xffffffbc )
 #endif /* configRUN_FREERTOS_SECURE_ONLY */
 
@@ -401,49 +398,49 @@ static void prvTaskExitError( void );
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Extract MPU region's access permissions from the Region Base Address
- * Register (RBAR) value.
- *
- * @param ulRBARValue RBAR value for the MPU region.
- *
- * @return uint32_t Access permissions.
- */
+    /**
+     * @brief Extract MPU region's access permissions from the Region Base Address
+     * Register (RBAR) value.
+     *
+     * @param ulRBARValue RBAR value for the MPU region.
+     *
+     * @return uint32_t Access permissions.
+     */
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Setup the Memory Protection Unit (MPU).
- */
+    /**
+     * @brief Setup the Memory Protection Unit (MPU).
+     */
     static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_MPU */
 
 #if ( configENABLE_FPU == 1 )
 
-/**
- * @brief Setup the Floating Point Unit (FPU).
- */
+    /**
+     * @brief Setup the Floating Point Unit (FPU).
+     */
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
 #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
-/**
- * @brief Configures PACBTI features.
- *
- * This function configures the Pointer Authentication, and Branch Target
- * Identification security features as per the user configuration. It returns
- * the value of the special purpose CONTROL register accordingly, and optionally
- * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
- * architecture based) target supports PACBTI security feature.
- *
- * @param xWriteControlRegister Used to control whether the special purpose
- * CONTROL register should be updated or not.
- *
- * @return CONTROL register value according to the configured PACBTI option.
- */
+    /**
+     * @brief Configures PACBTI features.
+     *
+     * This function configures the Pointer Authentication, and Branch Target
+     * Identification security features as per the user configuration. It returns
+     * the value of the special purpose CONTROL register accordingly, and optionally
+     * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
+     * architecture based) target supports PACBTI security feature.
+     *
+     * @param xWriteControlRegister Used to control whether the special purpose
+     * CONTROL register should be updated or not.
+     *
+     * @return CONTROL register value according to the configured PACBTI option.
+     */
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
 
 #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
@@ -491,14 +488,14 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Sets up the system call stack so that upon returning from
- * SVC, the system call stack is used.
- *
- * @param pulTaskStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
- * @param ucSystemCallNumber The system call number of the system call.
- */
+    /**
+     * @brief Sets up the system call stack so that upon returning from
+     * SVC, the system call stack is used.
+     *
+     * @param pulTaskStack The current SP when the SVC was raised.
+     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+     * @param ucSystemCallNumber The system call number of the system call.
+     */
     void vSystemCallEnter( uint32_t * pulTaskStack,
                            uint32_t ulLR,
                            uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION;
@@ -507,22 +504,22 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Raise SVC for exiting from a system call.
- */
+    /**
+     * @brief Raise SVC for exiting from a system call.
+     */
     void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Sets up the task stack so that upon returning from
- * SVC, the task stack is used again.
- *
- * @param pulSystemCallStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
- */
+    /**
+     * @brief Sets up the task stack so that upon returning from
+     * SVC, the task stack is used again.
+     *
+     * @param pulSystemCallStack The current SP when the SVC was raised.
+     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+     */
     void vSystemCallExit( uint32_t * pulSystemCallStack,
                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
@@ -530,11 +527,11 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Checks whether or not the calling task is privileged.
- *
- * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
- */
+    /**
+     * @brief Checks whether or not the calling task is privileged.
+     *
+     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+     */
     BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
 
 #endif /* configENABLE_MPU == 1 */
@@ -542,9 +539,9 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief This variable is set to pdTRUE when the scheduler is started.
- */
+    /**
+     * @brief This variable is set to pdTRUE when the scheduler is started.
+     */
     PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@@ -557,10 +554,10 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-/**
- * @brief Saved as part of the task context to indicate which context the
- * task is using on the secure side.
- */
+    /**
+     * @brief Saved as part of the task context to indicate which context the
+     * task is using on the secure side.
+     */
     PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
 #endif /* configENABLE_TRUSTZONE */
 
@@ -579,21 +576,21 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
 
-/**
- * @brief The number of SysTick increments that make up one tick period.
- */
+    /**
+     * @brief The number of SysTick increments that make up one tick period.
+     */
     PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0;
 
-/**
- * @brief The maximum number of tick periods that can be suppressed is
- * limited by the 24 bit resolution of the SysTick timer.
- */
+    /**
+     * @brief The maximum number of tick periods that can be suppressed is
+     * limited by the 24 bit resolution of the SysTick timer.
+     */
     PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0;
 
-/**
- * @brief Compensate for the CPU cycles that pass while the SysTick is
- * stopped (low power functionality only).
- */
+    /**
+     * @brief Compensate for the CPU cycles that pass while the SysTick is
+     * stopped (low power functionality only).
+     */
     PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0;
 #endif /* configUSE_TICKLESS_IDLE */
 /*-----------------------------------------------------------*/
@@ -925,64 +922,57 @@ static void prvTaskExitError( void )
         /* The only permitted number of regions are 8 or 16. */
         configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
 
-        /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
-        configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
+        /* MAIR0 - Index 0. */
+        portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+        /* MAIR0 - Index 1. */
+        portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
 
-        /* Check that the MPU is present. */
-        if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
-        {
-            /* MAIR0 - Index 0. */
-            portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
-            /* MAIR0 - Index 1. */
-            portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+        /* Setup privileged flash as Read Only so that privileged tasks can
+         * read it but not modify. */
+        portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_PRIVILEGED_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup privileged flash as Read Only so that privileged tasks can
-             * read it but not modify. */
-            portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_PRIVILEGED_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup unprivileged flash as Read Only by both privileged and
+         * unprivileged tasks. All tasks can read it but no-one can modify. */
+        portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup unprivileged flash as Read Only by both privileged and
-             * unprivileged tasks. All tasks can read it but no-one can modify. */
-            portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup unprivileged syscalls flash as Read Only by both privileged
+         * and unprivileged tasks. All tasks can read it but no-one can modify. */
+        portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup unprivileged syscalls flash as Read Only by both privileged
-             * and unprivileged tasks. All tasks can read it but no-one can modify. */
-            portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup RAM containing kernel data for privileged access only. */
+        portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+                           ( portMPU_REGION_EXECUTE_NEVER );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup RAM containing kernel data for privileged access only. */
-            portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
-                               ( portMPU_REGION_EXECUTE_NEVER );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Enable mem fault. */
+        portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;
 
-            /* Enable mem fault. */
-            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;
-
-            /* Enable MPU with privileged background access i.e. unmapped
-             * regions have privileged access. */
-            portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
-        }
+        /* Enable MPU with privileged background access i.e. unmapped
+         * regions have privileged access. */
+        portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
     }
 
 #endif /* configENABLE_MPU */
@@ -1108,47 +1098,47 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
     switch( ucSVCNumber )
     {
-        #if ( configENABLE_TRUSTZONE == 1 )
-            case portSVC_ALLOCATE_SECURE_CONTEXT:
+    #if ( configENABLE_TRUSTZONE == 1 )
+        case portSVC_ALLOCATE_SECURE_CONTEXT:
 
-                /* R0 contains the stack size passed as parameter to the
-                 * vPortAllocateSecureContext function. */
-                ulR0 = pulCallerStackAddress[ 0 ];
+            /* R0 contains the stack size passed as parameter to the
+             * vPortAllocateSecureContext function. */
+            ulR0 = pulCallerStackAddress[ 0 ];
 
-                #if ( configENABLE_MPU == 1 )
-                {
-                    /* Read the CONTROL register value. */
-                    __asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
+            #if ( configENABLE_MPU == 1 )
+            {
+                /* Read the CONTROL register value. */
+                __asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
 
-                    /* The task that raised the SVC is privileged if Bit[0]
-                     * in the CONTROL register is 0. */
-                    ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+                /* The task that raised the SVC is privileged if Bit[0]
+                 * in the CONTROL register is 0. */
+                ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
 
-                    /* Allocate and load a context for the secure task. */
-                    xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
-                }
-                #else /* if ( configENABLE_MPU == 1 ) */
-                {
-                    /* Allocate and load a context for the secure task. */
-                    xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
-                }
-                #endif /* configENABLE_MPU */
+                /* Allocate and load a context for the secure task. */
+                xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
+            }
+            #else /* if ( configENABLE_MPU == 1 ) */
+            {
+                /* Allocate and load a context for the secure task. */
+                xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
+            }
+            #endif /* configENABLE_MPU */
 
-                configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );
-                SecureContext_LoadContext( xSecureContext, pxCurrentTCB );
-                break;
+            configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );
+            SecureContext_LoadContext( xSecureContext, pxCurrentTCB );
+            break;
 
-            case portSVC_FREE_SECURE_CONTEXT:
+        case portSVC_FREE_SECURE_CONTEXT:
 
-                /* R0 contains TCB being freed and R1 contains the secure
-                 * context handle to be freed. */
-                ulR0 = pulCallerStackAddress[ 0 ];
-                ulR1 = pulCallerStackAddress[ 1 ];
+            /* R0 contains TCB being freed and R1 contains the secure
+             * context handle to be freed. */
+            ulR0 = pulCallerStackAddress[ 0 ];
+            ulR1 = pulCallerStackAddress[ 1 ];
 
-                /* Free the secure context. */
-                SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );
-                break;
-        #endif /* configENABLE_TRUSTZONE */
+            /* Free the secure context. */
+            SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );
+            break;
+    #endif /* configENABLE_TRUSTZONE */
 
         case portSVC_START_SCHEDULER:
             #if ( configENABLE_TRUSTZONE == 1 )
@@ -1174,24 +1164,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             vRestoreContextOfFirstTask();
             break;
 
-            #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
-                case portSVC_RAISE_PRIVILEGE:
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+        case portSVC_RAISE_PRIVILEGE:
 
-                    /* Only raise the privilege, if the svc was raised from any of
-                     * the system calls. */
-                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
-                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
-                    {
-                        vRaisePrivilege();
-                    }
-                    break;
-            #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+            /* Only raise the privilege, if the svc was raised from any of
+             * the system calls. */
+            if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+                ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+            {
+                vRaisePrivilege();
+            }
+            break;
+    #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
-            #if ( configENABLE_MPU == 1 )
-                case portSVC_YIELD:
-                    vPortYield();
-                    break;
-            #endif /* configENABLE_MPU == 1 */
+    #if ( configENABLE_MPU == 1 )
+        case portSVC_YIELD:
+            vPortYield();
+            break;
+    #endif /* configENABLE_MPU == 1 */
 
         default:
             /* Incorrect SVC call. */
@@ -1518,21 +1508,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
         ulIndex++;
 
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters;            /* r0. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x01010101;                           /* r1. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x02020202;                           /* r2. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x03030303;                           /* r3. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x12121212;                           /* r12. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
         ulIndex++;
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode;                  /* PC. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR;                     /* xPSR. */
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
         ulIndex++;
 
         #if ( configENABLE_TRUSTZONE == 1 )
@@ -1543,7 +1533,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         #endif /* configENABLE_TRUSTZONE */
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
         ulIndex++;
 
         #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
@@ -1615,15 +1605,15 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
          * interrupt. */
         #if ( portPRELOAD_REGISTERS == 0 )
         {
-            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
+            pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-            pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
-            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-            pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
+            pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
+            *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */
+            pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */
             *pxTopOfStack = portINITIAL_EXC_RETURN;
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
@@ -1637,42 +1627,42 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #else /* portPRELOAD_REGISTERS */
         {
-            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
+            pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
+            *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
+            *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
+            *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
+            *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
+            *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
+            *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
+            *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
+            *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
+            *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
+            *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
+            *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
+            *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04. */
             pxTopOfStack--;
-            *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
+            *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxEndOfStack;            /* Slot used to hold this task's PSPLIM value. */
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
 
             #if ( configENABLE_TRUSTZONE == 1 )
             {
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
index b2fd7e518..a7fb054bc 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
@@ -145,13 +145,13 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the FPU.
  */
-#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 )              /* Coprocessor Access Control Register. */
+#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */
 #define portCPACR_CP10_VALUE    ( 3UL )
 #define portCPACR_CP11_VALUE    portCPACR_CP10_VALUE
 #define portCPACR_CP10_POS      ( 20UL )
 #define portCPACR_CP11_POS      ( 22UL )
 
-#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 )              /* Floating Point Context Control Register. */
+#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */
 #define portFPCCR_ASPEN_POS     ( 31UL )
 #define portFPCCR_ASPEN_MASK    ( 1UL << portFPCCR_ASPEN_POS )
 #define portFPCCR_LSPEN_POS     ( 30UL )
@@ -188,8 +188,8 @@ typedef void ( * portISR_t )( void );
 #define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
 #define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
 #define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
@@ -230,8 +230,8 @@ typedef void ( * portISR_t )( void );
 
 #if ( portARMV8M_MINOR_VERSION >= 1 )
 
-/* Enable Privileged eXecute Never MPU attribute for the selected memory
- * region. */
+    /* Enable Privileged eXecute Never MPU attribute for the selected memory
+     * region. */
     #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER    ( 1UL << 4UL )
 #endif /* portARMV8M_MINOR_VERSION >= 1 */
 
@@ -241,9 +241,6 @@ typedef void ( * portISR_t )( void );
 /* Enable MPU. */
 #define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
 
-/* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
-
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
 #define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \
@@ -291,37 +288,37 @@ typedef void ( * portISR_t )( void );
 
 #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
 
-/**
- * @brief Initial EXC_RETURN value.
- *
- *     FF         FF         FF         FD
- * 1111 1111  1111 1111  1111 1111  1111 1101
- *
- * Bit[6] - 1 --> The exception was taken from the Secure state.
- * Bit[5] - 1 --> Do not skip stacking of additional state context.
- * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
- * Bit[3] - 1 --> Return to the Thread mode.
- * Bit[2] - 1 --> Restore registers from the process stack.
- * Bit[1] - 0 --> Reserved, 0.
- * Bit[0] - 1 --> The exception was taken to the Secure state.
- */
+    /**
+     * @brief Initial EXC_RETURN value.
+     *
+     *     FF         FF         FF         FD
+     * 1111 1111  1111 1111  1111 1111  1111 1101
+     *
+     * Bit[6] - 1 --> The exception was taken from the Secure state.
+     * Bit[5] - 1 --> Do not skip stacking of additional state context.
+     * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+     * Bit[3] - 1 --> Return to the Thread mode.
+     * Bit[2] - 1 --> Restore registers from the process stack.
+     * Bit[1] - 0 --> Reserved, 0.
+     * Bit[0] - 1 --> The exception was taken to the Secure state.
+     */
     #define portINITIAL_EXC_RETURN    ( 0xfffffffd )
 #else
 
-/**
- * @brief Initial EXC_RETURN value.
- *
- *     FF         FF         FF         BC
- * 1111 1111  1111 1111  1111 1111  1011 1100
- *
- * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
- * Bit[5] - 1 --> Do not skip stacking of additional state context.
- * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
- * Bit[3] - 1 --> Return to the Thread mode.
- * Bit[2] - 1 --> Restore registers from the process stack.
- * Bit[1] - 0 --> Reserved, 0.
- * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
- */
+    /**
+     * @brief Initial EXC_RETURN value.
+     *
+     *     FF         FF         FF         BC
+     * 1111 1111  1111 1111  1111 1111  1011 1100
+     *
+     * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+     * Bit[5] - 1 --> Do not skip stacking of additional state context.
+     * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+     * Bit[3] - 1 --> Return to the Thread mode.
+     * Bit[2] - 1 --> Restore registers from the process stack.
+     * Bit[1] - 0 --> Reserved, 0.
+     * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+     */
     #define portINITIAL_EXC_RETURN    ( 0xffffffbc )
 #endif /* configRUN_FREERTOS_SECURE_ONLY */
 
@@ -401,49 +398,49 @@ static void prvTaskExitError( void );
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Extract MPU region's access permissions from the Region Base Address
- * Register (RBAR) value.
- *
- * @param ulRBARValue RBAR value for the MPU region.
- *
- * @return uint32_t Access permissions.
- */
+    /**
+     * @brief Extract MPU region's access permissions from the Region Base Address
+     * Register (RBAR) value.
+     *
+     * @param ulRBARValue RBAR value for the MPU region.
+     *
+     * @return uint32_t Access permissions.
+     */
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Setup the Memory Protection Unit (MPU).
- */
+    /**
+     * @brief Setup the Memory Protection Unit (MPU).
+     */
     static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_MPU */
 
 #if ( configENABLE_FPU == 1 )
 
-/**
- * @brief Setup the Floating Point Unit (FPU).
- */
+    /**
+     * @brief Setup the Floating Point Unit (FPU).
+     */
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
 #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
-/**
- * @brief Configures PACBTI features.
- *
- * This function configures the Pointer Authentication, and Branch Target
- * Identification security features as per the user configuration. It returns
- * the value of the special purpose CONTROL register accordingly, and optionally
- * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
- * architecture based) target supports PACBTI security feature.
- *
- * @param xWriteControlRegister Used to control whether the special purpose
- * CONTROL register should be updated or not.
- *
- * @return CONTROL register value according to the configured PACBTI option.
- */
+    /**
+     * @brief Configures PACBTI features.
+     *
+     * This function configures the Pointer Authentication, and Branch Target
+     * Identification security features as per the user configuration. It returns
+     * the value of the special purpose CONTROL register accordingly, and optionally
+     * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
+     * architecture based) target supports PACBTI security feature.
+     *
+     * @param xWriteControlRegister Used to control whether the special purpose
+     * CONTROL register should be updated or not.
+     *
+     * @return CONTROL register value according to the configured PACBTI option.
+     */
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
 
 #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
@@ -491,14 +488,14 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Sets up the system call stack so that upon returning from
- * SVC, the system call stack is used.
- *
- * @param pulTaskStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
- * @param ucSystemCallNumber The system call number of the system call.
- */
+    /**
+     * @brief Sets up the system call stack so that upon returning from
+     * SVC, the system call stack is used.
+     *
+     * @param pulTaskStack The current SP when the SVC was raised.
+     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+     * @param ucSystemCallNumber The system call number of the system call.
+     */
     void vSystemCallEnter( uint32_t * pulTaskStack,
                            uint32_t ulLR,
                            uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION;
@@ -507,22 +504,22 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Raise SVC for exiting from a system call.
- */
+    /**
+     * @brief Raise SVC for exiting from a system call.
+     */
     void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Sets up the task stack so that upon returning from
- * SVC, the task stack is used again.
- *
- * @param pulSystemCallStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
- */
+    /**
+     * @brief Sets up the task stack so that upon returning from
+     * SVC, the task stack is used again.
+     *
+     * @param pulSystemCallStack The current SP when the SVC was raised.
+     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+     */
     void vSystemCallExit( uint32_t * pulSystemCallStack,
                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
@@ -530,11 +527,11 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Checks whether or not the calling task is privileged.
- *
- * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
- */
+    /**
+     * @brief Checks whether or not the calling task is privileged.
+     *
+     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+     */
     BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
 
 #endif /* configENABLE_MPU == 1 */
@@ -542,9 +539,9 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief This variable is set to pdTRUE when the scheduler is started.
- */
+    /**
+     * @brief This variable is set to pdTRUE when the scheduler is started.
+     */
     PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@@ -557,10 +554,10 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-/**
- * @brief Saved as part of the task context to indicate which context the
- * task is using on the secure side.
- */
+    /**
+     * @brief Saved as part of the task context to indicate which context the
+     * task is using on the secure side.
+     */
     PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
 #endif /* configENABLE_TRUSTZONE */
 
@@ -579,21 +576,21 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
 
-/**
- * @brief The number of SysTick increments that make up one tick period.
- */
+    /**
+     * @brief The number of SysTick increments that make up one tick period.
+     */
     PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0;
 
-/**
- * @brief The maximum number of tick periods that can be suppressed is
- * limited by the 24 bit resolution of the SysTick timer.
- */
+    /**
+     * @brief The maximum number of tick periods that can be suppressed is
+     * limited by the 24 bit resolution of the SysTick timer.
+     */
     PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0;
 
-/**
- * @brief Compensate for the CPU cycles that pass while the SysTick is
- * stopped (low power functionality only).
- */
+    /**
+     * @brief Compensate for the CPU cycles that pass while the SysTick is
+     * stopped (low power functionality only).
+     */
     PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0;
 #endif /* configUSE_TICKLESS_IDLE */
 /*-----------------------------------------------------------*/
@@ -925,64 +922,57 @@ static void prvTaskExitError( void )
         /* The only permitted number of regions are 8 or 16. */
         configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
 
-        /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
-        configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
+        /* MAIR0 - Index 0. */
+        portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+        /* MAIR0 - Index 1. */
+        portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
 
-        /* Check that the MPU is present. */
-        if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
-        {
-            /* MAIR0 - Index 0. */
-            portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
-            /* MAIR0 - Index 1. */
-            portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+        /* Setup privileged flash as Read Only so that privileged tasks can
+         * read it but not modify. */
+        portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_PRIVILEGED_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup privileged flash as Read Only so that privileged tasks can
-             * read it but not modify. */
-            portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_PRIVILEGED_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup unprivileged flash as Read Only by both privileged and
+         * unprivileged tasks. All tasks can read it but no-one can modify. */
+        portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup unprivileged flash as Read Only by both privileged and
-             * unprivileged tasks. All tasks can read it but no-one can modify. */
-            portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup unprivileged syscalls flash as Read Only by both privileged
+         * and unprivileged tasks. All tasks can read it but no-one can modify. */
+        portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup unprivileged syscalls flash as Read Only by both privileged
-             * and unprivileged tasks. All tasks can read it but no-one can modify. */
-            portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup RAM containing kernel data for privileged access only. */
+        portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+                           ( portMPU_REGION_EXECUTE_NEVER );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup RAM containing kernel data for privileged access only. */
-            portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
-                               ( portMPU_REGION_EXECUTE_NEVER );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Enable mem fault. */
+        portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;
 
-            /* Enable mem fault. */
-            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;
-
-            /* Enable MPU with privileged background access i.e. unmapped
-             * regions have privileged access. */
-            portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
-        }
+        /* Enable MPU with privileged background access i.e. unmapped
+         * regions have privileged access. */
+        portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
     }
 
 #endif /* configENABLE_MPU */
@@ -1108,47 +1098,47 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
     switch( ucSVCNumber )
     {
-        #if ( configENABLE_TRUSTZONE == 1 )
-            case portSVC_ALLOCATE_SECURE_CONTEXT:
+    #if ( configENABLE_TRUSTZONE == 1 )
+        case portSVC_ALLOCATE_SECURE_CONTEXT:
 
-                /* R0 contains the stack size passed as parameter to the
-                 * vPortAllocateSecureContext function. */
-                ulR0 = pulCallerStackAddress[ 0 ];
+            /* R0 contains the stack size passed as parameter to the
+             * vPortAllocateSecureContext function. */
+            ulR0 = pulCallerStackAddress[ 0 ];
 
-                #if ( configENABLE_MPU == 1 )
-                {
-                    /* Read the CONTROL register value. */
-                    __asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
+            #if ( configENABLE_MPU == 1 )
+            {
+                /* Read the CONTROL register value. */
+                __asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
 
-                    /* The task that raised the SVC is privileged if Bit[0]
-                     * in the CONTROL register is 0. */
-                    ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+                /* The task that raised the SVC is privileged if Bit[0]
+                 * in the CONTROL register is 0. */
+                ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
 
-                    /* Allocate and load a context for the secure task. */
-                    xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
-                }
-                #else /* if ( configENABLE_MPU == 1 ) */
-                {
-                    /* Allocate and load a context for the secure task. */
-                    xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
-                }
-                #endif /* configENABLE_MPU */
+                /* Allocate and load a context for the secure task. */
+                xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
+            }
+            #else /* if ( configENABLE_MPU == 1 ) */
+            {
+                /* Allocate and load a context for the secure task. */
+                xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
+            }
+            #endif /* configENABLE_MPU */
 
-                configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );
-                SecureContext_LoadContext( xSecureContext, pxCurrentTCB );
-                break;
+            configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );
+            SecureContext_LoadContext( xSecureContext, pxCurrentTCB );
+            break;
 
-            case portSVC_FREE_SECURE_CONTEXT:
+        case portSVC_FREE_SECURE_CONTEXT:
 
-                /* R0 contains TCB being freed and R1 contains the secure
-                 * context handle to be freed. */
-                ulR0 = pulCallerStackAddress[ 0 ];
-                ulR1 = pulCallerStackAddress[ 1 ];
+            /* R0 contains TCB being freed and R1 contains the secure
+             * context handle to be freed. */
+            ulR0 = pulCallerStackAddress[ 0 ];
+            ulR1 = pulCallerStackAddress[ 1 ];
 
-                /* Free the secure context. */
-                SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );
-                break;
-        #endif /* configENABLE_TRUSTZONE */
+            /* Free the secure context. */
+            SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );
+            break;
+    #endif /* configENABLE_TRUSTZONE */
 
         case portSVC_START_SCHEDULER:
             #if ( configENABLE_TRUSTZONE == 1 )
@@ -1174,24 +1164,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             vRestoreContextOfFirstTask();
             break;
 
-            #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
-                case portSVC_RAISE_PRIVILEGE:
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+        case portSVC_RAISE_PRIVILEGE:
 
-                    /* Only raise the privilege, if the svc was raised from any of
-                     * the system calls. */
-                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
-                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
-                    {
-                        vRaisePrivilege();
-                    }
-                    break;
-            #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+            /* Only raise the privilege, if the svc was raised from any of
+             * the system calls. */
+            if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+                ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+            {
+                vRaisePrivilege();
+            }
+            break;
+    #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
-            #if ( configENABLE_MPU == 1 )
-                case portSVC_YIELD:
-                    vPortYield();
-                    break;
-            #endif /* configENABLE_MPU == 1 */
+    #if ( configENABLE_MPU == 1 )
+        case portSVC_YIELD:
+            vPortYield();
+            break;
+    #endif /* configENABLE_MPU == 1 */
 
         default:
             /* Incorrect SVC call. */
@@ -1518,21 +1508,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
         ulIndex++;
 
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters;            /* r0. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x01010101;                           /* r1. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x02020202;                           /* r2. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x03030303;                           /* r3. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x12121212;                           /* r12. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
         ulIndex++;
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode;                  /* PC. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR;                     /* xPSR. */
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
         ulIndex++;
 
         #if ( configENABLE_TRUSTZONE == 1 )
@@ -1543,7 +1533,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         #endif /* configENABLE_TRUSTZONE */
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
         ulIndex++;
 
         #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
@@ -1615,15 +1605,15 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
          * interrupt. */
         #if ( portPRELOAD_REGISTERS == 0 )
         {
-            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
+            pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-            pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
-            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-            pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
+            pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
+            *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */
+            pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */
             *pxTopOfStack = portINITIAL_EXC_RETURN;
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
@@ -1637,42 +1627,42 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #else /* portPRELOAD_REGISTERS */
         {
-            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
+            pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
+            *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
+            *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
+            *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
+            *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
+            *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
+            *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
+            *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
+            *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
+            *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
+            *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
+            *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
+            *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04. */
             pxTopOfStack--;
-            *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
+            *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxEndOfStack;            /* Slot used to hold this task's PSPLIM value. */
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
 
             #if ( configENABLE_TRUSTZONE == 1 )
             {
diff --git a/portable/GCC/ARM_CM35P/non_secure/port.c b/portable/GCC/ARM_CM35P/non_secure/port.c
index b2fd7e518..a7fb054bc 100644
--- a/portable/GCC/ARM_CM35P/non_secure/port.c
+++ b/portable/GCC/ARM_CM35P/non_secure/port.c
@@ -145,13 +145,13 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the FPU.
  */
-#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 )              /* Coprocessor Access Control Register. */
+#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */
 #define portCPACR_CP10_VALUE    ( 3UL )
 #define portCPACR_CP11_VALUE    portCPACR_CP10_VALUE
 #define portCPACR_CP10_POS      ( 20UL )
 #define portCPACR_CP11_POS      ( 22UL )
 
-#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 )              /* Floating Point Context Control Register. */
+#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */
 #define portFPCCR_ASPEN_POS     ( 31UL )
 #define portFPCCR_ASPEN_MASK    ( 1UL << portFPCCR_ASPEN_POS )
 #define portFPCCR_LSPEN_POS     ( 30UL )
@@ -188,8 +188,8 @@ typedef void ( * portISR_t )( void );
 #define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
 #define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
 #define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
@@ -230,8 +230,8 @@ typedef void ( * portISR_t )( void );
 
 #if ( portARMV8M_MINOR_VERSION >= 1 )
 
-/* Enable Privileged eXecute Never MPU attribute for the selected memory
- * region. */
+    /* Enable Privileged eXecute Never MPU attribute for the selected memory
+     * region. */
     #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER    ( 1UL << 4UL )
 #endif /* portARMV8M_MINOR_VERSION >= 1 */
 
@@ -241,9 +241,6 @@ typedef void ( * portISR_t )( void );
 /* Enable MPU. */
 #define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
 
-/* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
-
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
 #define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \
@@ -291,37 +288,37 @@ typedef void ( * portISR_t )( void );
 
 #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
 
-/**
- * @brief Initial EXC_RETURN value.
- *
- *     FF         FF         FF         FD
- * 1111 1111  1111 1111  1111 1111  1111 1101
- *
- * Bit[6] - 1 --> The exception was taken from the Secure state.
- * Bit[5] - 1 --> Do not skip stacking of additional state context.
- * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
- * Bit[3] - 1 --> Return to the Thread mode.
- * Bit[2] - 1 --> Restore registers from the process stack.
- * Bit[1] - 0 --> Reserved, 0.
- * Bit[0] - 1 --> The exception was taken to the Secure state.
- */
+    /**
+     * @brief Initial EXC_RETURN value.
+     *
+     *     FF         FF         FF         FD
+     * 1111 1111  1111 1111  1111 1111  1111 1101
+     *
+     * Bit[6] - 1 --> The exception was taken from the Secure state.
+     * Bit[5] - 1 --> Do not skip stacking of additional state context.
+     * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+     * Bit[3] - 1 --> Return to the Thread mode.
+     * Bit[2] - 1 --> Restore registers from the process stack.
+     * Bit[1] - 0 --> Reserved, 0.
+     * Bit[0] - 1 --> The exception was taken to the Secure state.
+     */
     #define portINITIAL_EXC_RETURN    ( 0xfffffffd )
 #else
 
-/**
- * @brief Initial EXC_RETURN value.
- *
- *     FF         FF         FF         BC
- * 1111 1111  1111 1111  1111 1111  1011 1100
- *
- * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
- * Bit[5] - 1 --> Do not skip stacking of additional state context.
- * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
- * Bit[3] - 1 --> Return to the Thread mode.
- * Bit[2] - 1 --> Restore registers from the process stack.
- * Bit[1] - 0 --> Reserved, 0.
- * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
- */
+    /**
+     * @brief Initial EXC_RETURN value.
+     *
+     *     FF         FF         FF         BC
+     * 1111 1111  1111 1111  1111 1111  1011 1100
+     *
+     * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+     * Bit[5] - 1 --> Do not skip stacking of additional state context.
+     * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+     * Bit[3] - 1 --> Return to the Thread mode.
+     * Bit[2] - 1 --> Restore registers from the process stack.
+     * Bit[1] - 0 --> Reserved, 0.
+     * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+     */
     #define portINITIAL_EXC_RETURN    ( 0xffffffbc )
 #endif /* configRUN_FREERTOS_SECURE_ONLY */
 
@@ -401,49 +398,49 @@ static void prvTaskExitError( void );
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Extract MPU region's access permissions from the Region Base Address
- * Register (RBAR) value.
- *
- * @param ulRBARValue RBAR value for the MPU region.
- *
- * @return uint32_t Access permissions.
- */
+    /**
+     * @brief Extract MPU region's access permissions from the Region Base Address
+     * Register (RBAR) value.
+     *
+     * @param ulRBARValue RBAR value for the MPU region.
+     *
+     * @return uint32_t Access permissions.
+     */
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Setup the Memory Protection Unit (MPU).
- */
+    /**
+     * @brief Setup the Memory Protection Unit (MPU).
+     */
     static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_MPU */
 
 #if ( configENABLE_FPU == 1 )
 
-/**
- * @brief Setup the Floating Point Unit (FPU).
- */
+    /**
+     * @brief Setup the Floating Point Unit (FPU).
+     */
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
 #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
-/**
- * @brief Configures PACBTI features.
- *
- * This function configures the Pointer Authentication, and Branch Target
- * Identification security features as per the user configuration. It returns
- * the value of the special purpose CONTROL register accordingly, and optionally
- * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
- * architecture based) target supports PACBTI security feature.
- *
- * @param xWriteControlRegister Used to control whether the special purpose
- * CONTROL register should be updated or not.
- *
- * @return CONTROL register value according to the configured PACBTI option.
- */
+    /**
+     * @brief Configures PACBTI features.
+     *
+     * This function configures the Pointer Authentication, and Branch Target
+     * Identification security features as per the user configuration. It returns
+     * the value of the special purpose CONTROL register accordingly, and optionally
+     * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
+     * architecture based) target supports PACBTI security feature.
+     *
+     * @param xWriteControlRegister Used to control whether the special purpose
+     * CONTROL register should be updated or not.
+     *
+     * @return CONTROL register value according to the configured PACBTI option.
+     */
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
 
 #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
@@ -491,14 +488,14 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Sets up the system call stack so that upon returning from
- * SVC, the system call stack is used.
- *
- * @param pulTaskStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
- * @param ucSystemCallNumber The system call number of the system call.
- */
+    /**
+     * @brief Sets up the system call stack so that upon returning from
+     * SVC, the system call stack is used.
+     *
+     * @param pulTaskStack The current SP when the SVC was raised.
+     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+     * @param ucSystemCallNumber The system call number of the system call.
+     */
     void vSystemCallEnter( uint32_t * pulTaskStack,
                            uint32_t ulLR,
                            uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION;
@@ -507,22 +504,22 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Raise SVC for exiting from a system call.
- */
+    /**
+     * @brief Raise SVC for exiting from a system call.
+     */
     void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Sets up the task stack so that upon returning from
- * SVC, the task stack is used again.
- *
- * @param pulSystemCallStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
- */
+    /**
+     * @brief Sets up the task stack so that upon returning from
+     * SVC, the task stack is used again.
+     *
+     * @param pulSystemCallStack The current SP when the SVC was raised.
+     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+     */
     void vSystemCallExit( uint32_t * pulSystemCallStack,
                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
@@ -530,11 +527,11 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Checks whether or not the calling task is privileged.
- *
- * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
- */
+    /**
+     * @brief Checks whether or not the calling task is privileged.
+     *
+     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+     */
     BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
 
 #endif /* configENABLE_MPU == 1 */
@@ -542,9 +539,9 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief This variable is set to pdTRUE when the scheduler is started.
- */
+    /**
+     * @brief This variable is set to pdTRUE when the scheduler is started.
+     */
     PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@@ -557,10 +554,10 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-/**
- * @brief Saved as part of the task context to indicate which context the
- * task is using on the secure side.
- */
+    /**
+     * @brief Saved as part of the task context to indicate which context the
+     * task is using on the secure side.
+     */
     PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
 #endif /* configENABLE_TRUSTZONE */
 
@@ -579,21 +576,21 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
 
-/**
- * @brief The number of SysTick increments that make up one tick period.
- */
+    /**
+     * @brief The number of SysTick increments that make up one tick period.
+     */
     PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0;
 
-/**
- * @brief The maximum number of tick periods that can be suppressed is
- * limited by the 24 bit resolution of the SysTick timer.
- */
+    /**
+     * @brief The maximum number of tick periods that can be suppressed is
+     * limited by the 24 bit resolution of the SysTick timer.
+     */
     PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0;
 
-/**
- * @brief Compensate for the CPU cycles that pass while the SysTick is
- * stopped (low power functionality only).
- */
+    /**
+     * @brief Compensate for the CPU cycles that pass while the SysTick is
+     * stopped (low power functionality only).
+     */
     PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0;
 #endif /* configUSE_TICKLESS_IDLE */
 /*-----------------------------------------------------------*/
@@ -925,64 +922,57 @@ static void prvTaskExitError( void )
         /* The only permitted number of regions are 8 or 16. */
         configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
 
-        /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
-        configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
+        /* MAIR0 - Index 0. */
+        portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+        /* MAIR0 - Index 1. */
+        portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
 
-        /* Check that the MPU is present. */
-        if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
-        {
-            /* MAIR0 - Index 0. */
-            portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
-            /* MAIR0 - Index 1. */
-            portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+        /* Setup privileged flash as Read Only so that privileged tasks can
+         * read it but not modify. */
+        portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_PRIVILEGED_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup privileged flash as Read Only so that privileged tasks can
-             * read it but not modify. */
-            portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_PRIVILEGED_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup unprivileged flash as Read Only by both privileged and
+         * unprivileged tasks. All tasks can read it but no-one can modify. */
+        portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup unprivileged flash as Read Only by both privileged and
-             * unprivileged tasks. All tasks can read it but no-one can modify. */
-            portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup unprivileged syscalls flash as Read Only by both privileged
+         * and unprivileged tasks. All tasks can read it but no-one can modify. */
+        portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup unprivileged syscalls flash as Read Only by both privileged
-             * and unprivileged tasks. All tasks can read it but no-one can modify. */
-            portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup RAM containing kernel data for privileged access only. */
+        portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+                           ( portMPU_REGION_EXECUTE_NEVER );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup RAM containing kernel data for privileged access only. */
-            portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
-                               ( portMPU_REGION_EXECUTE_NEVER );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Enable mem fault. */
+        portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;
 
-            /* Enable mem fault. */
-            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;
-
-            /* Enable MPU with privileged background access i.e. unmapped
-             * regions have privileged access. */
-            portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
-        }
+        /* Enable MPU with privileged background access i.e. unmapped
+         * regions have privileged access. */
+        portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
     }
 
 #endif /* configENABLE_MPU */
@@ -1108,47 +1098,47 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
     switch( ucSVCNumber )
     {
-        #if ( configENABLE_TRUSTZONE == 1 )
-            case portSVC_ALLOCATE_SECURE_CONTEXT:
+    #if ( configENABLE_TRUSTZONE == 1 )
+        case portSVC_ALLOCATE_SECURE_CONTEXT:
 
-                /* R0 contains the stack size passed as parameter to the
-                 * vPortAllocateSecureContext function. */
-                ulR0 = pulCallerStackAddress[ 0 ];
+            /* R0 contains the stack size passed as parameter to the
+             * vPortAllocateSecureContext function. */
+            ulR0 = pulCallerStackAddress[ 0 ];
 
-                #if ( configENABLE_MPU == 1 )
-                {
-                    /* Read the CONTROL register value. */
-                    __asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
+            #if ( configENABLE_MPU == 1 )
+            {
+                /* Read the CONTROL register value. */
+                __asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
 
-                    /* The task that raised the SVC is privileged if Bit[0]
-                     * in the CONTROL register is 0. */
-                    ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+                /* The task that raised the SVC is privileged if Bit[0]
+                 * in the CONTROL register is 0. */
+                ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
 
-                    /* Allocate and load a context for the secure task. */
-                    xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
-                }
-                #else /* if ( configENABLE_MPU == 1 ) */
-                {
-                    /* Allocate and load a context for the secure task. */
-                    xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
-                }
-                #endif /* configENABLE_MPU */
+                /* Allocate and load a context for the secure task. */
+                xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
+            }
+            #else /* if ( configENABLE_MPU == 1 ) */
+            {
+                /* Allocate and load a context for the secure task. */
+                xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
+            }
+            #endif /* configENABLE_MPU */
 
-                configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );
-                SecureContext_LoadContext( xSecureContext, pxCurrentTCB );
-                break;
+            configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );
+            SecureContext_LoadContext( xSecureContext, pxCurrentTCB );
+            break;
 
-            case portSVC_FREE_SECURE_CONTEXT:
+        case portSVC_FREE_SECURE_CONTEXT:
 
-                /* R0 contains TCB being freed and R1 contains the secure
-                 * context handle to be freed. */
-                ulR0 = pulCallerStackAddress[ 0 ];
-                ulR1 = pulCallerStackAddress[ 1 ];
+            /* R0 contains TCB being freed and R1 contains the secure
+             * context handle to be freed. */
+            ulR0 = pulCallerStackAddress[ 0 ];
+            ulR1 = pulCallerStackAddress[ 1 ];
 
-                /* Free the secure context. */
-                SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );
-                break;
-        #endif /* configENABLE_TRUSTZONE */
+            /* Free the secure context. */
+            SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );
+            break;
+    #endif /* configENABLE_TRUSTZONE */
 
         case portSVC_START_SCHEDULER:
             #if ( configENABLE_TRUSTZONE == 1 )
@@ -1174,24 +1164,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             vRestoreContextOfFirstTask();
             break;
 
-            #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
-                case portSVC_RAISE_PRIVILEGE:
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+        case portSVC_RAISE_PRIVILEGE:
 
-                    /* Only raise the privilege, if the svc was raised from any of
-                     * the system calls. */
-                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
-                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
-                    {
-                        vRaisePrivilege();
-                    }
-                    break;
-            #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+            /* Only raise the privilege, if the svc was raised from any of
+             * the system calls. */
+            if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+                ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+            {
+                vRaisePrivilege();
+            }
+            break;
+    #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
-            #if ( configENABLE_MPU == 1 )
-                case portSVC_YIELD:
-                    vPortYield();
-                    break;
-            #endif /* configENABLE_MPU == 1 */
+    #if ( configENABLE_MPU == 1 )
+        case portSVC_YIELD:
+            vPortYield();
+            break;
+    #endif /* configENABLE_MPU == 1 */
 
         default:
             /* Incorrect SVC call. */
@@ -1518,21 +1508,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
         ulIndex++;
 
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters;            /* r0. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x01010101;                           /* r1. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x02020202;                           /* r2. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x03030303;                           /* r3. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x12121212;                           /* r12. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
         ulIndex++;
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode;                  /* PC. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR;                     /* xPSR. */
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
         ulIndex++;
 
         #if ( configENABLE_TRUSTZONE == 1 )
@@ -1543,7 +1533,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         #endif /* configENABLE_TRUSTZONE */
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
         ulIndex++;
 
         #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
@@ -1615,15 +1605,15 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
          * interrupt. */
         #if ( portPRELOAD_REGISTERS == 0 )
         {
-            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
+            pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-            pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
-            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-            pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
+            pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
+            *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */
+            pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */
             *pxTopOfStack = portINITIAL_EXC_RETURN;
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
@@ -1637,42 +1627,42 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #else /* portPRELOAD_REGISTERS */
         {
-            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
+            pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
+            *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
+            *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
+            *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
+            *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
+            *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
+            *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
+            *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
+            *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
+            *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
+            *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
+            *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
+            *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04. */
             pxTopOfStack--;
-            *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
+            *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxEndOfStack;            /* Slot used to hold this task's PSPLIM value. */
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
 
             #if ( configENABLE_TRUSTZONE == 1 )
             {
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c b/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
index b2fd7e518..a7fb054bc 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
@@ -145,13 +145,13 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the FPU.
  */
-#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 )              /* Coprocessor Access Control Register. */
+#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */
 #define portCPACR_CP10_VALUE    ( 3UL )
 #define portCPACR_CP11_VALUE    portCPACR_CP10_VALUE
 #define portCPACR_CP10_POS      ( 20UL )
 #define portCPACR_CP11_POS      ( 22UL )
 
-#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 )              /* Floating Point Context Control Register. */
+#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */
 #define portFPCCR_ASPEN_POS     ( 31UL )
 #define portFPCCR_ASPEN_MASK    ( 1UL << portFPCCR_ASPEN_POS )
 #define portFPCCR_LSPEN_POS     ( 30UL )
@@ -188,8 +188,8 @@ typedef void ( * portISR_t )( void );
 #define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
 #define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
 #define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
@@ -230,8 +230,8 @@ typedef void ( * portISR_t )( void );
 
 #if ( portARMV8M_MINOR_VERSION >= 1 )
 
-/* Enable Privileged eXecute Never MPU attribute for the selected memory
- * region. */
+    /* Enable Privileged eXecute Never MPU attribute for the selected memory
+     * region. */
     #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER    ( 1UL << 4UL )
 #endif /* portARMV8M_MINOR_VERSION >= 1 */
 
@@ -241,9 +241,6 @@ typedef void ( * portISR_t )( void );
 /* Enable MPU. */
 #define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
 
-/* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
-
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
 #define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \
@@ -291,37 +288,37 @@ typedef void ( * portISR_t )( void );
 
 #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
 
-/**
- * @brief Initial EXC_RETURN value.
- *
- *     FF         FF         FF         FD
- * 1111 1111  1111 1111  1111 1111  1111 1101
- *
- * Bit[6] - 1 --> The exception was taken from the Secure state.
- * Bit[5] - 1 --> Do not skip stacking of additional state context.
- * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
- * Bit[3] - 1 --> Return to the Thread mode.
- * Bit[2] - 1 --> Restore registers from the process stack.
- * Bit[1] - 0 --> Reserved, 0.
- * Bit[0] - 1 --> The exception was taken to the Secure state.
- */
+    /**
+     * @brief Initial EXC_RETURN value.
+     *
+     *     FF         FF         FF         FD
+     * 1111 1111  1111 1111  1111 1111  1111 1101
+     *
+     * Bit[6] - 1 --> The exception was taken from the Secure state.
+     * Bit[5] - 1 --> Do not skip stacking of additional state context.
+     * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+     * Bit[3] - 1 --> Return to the Thread mode.
+     * Bit[2] - 1 --> Restore registers from the process stack.
+     * Bit[1] - 0 --> Reserved, 0.
+     * Bit[0] - 1 --> The exception was taken to the Secure state.
+     */
     #define portINITIAL_EXC_RETURN    ( 0xfffffffd )
 #else
 
-/**
- * @brief Initial EXC_RETURN value.
- *
- *     FF         FF         FF         BC
- * 1111 1111  1111 1111  1111 1111  1011 1100
- *
- * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
- * Bit[5] - 1 --> Do not skip stacking of additional state context.
- * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
- * Bit[3] - 1 --> Return to the Thread mode.
- * Bit[2] - 1 --> Restore registers from the process stack.
- * Bit[1] - 0 --> Reserved, 0.
- * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
- */
+    /**
+     * @brief Initial EXC_RETURN value.
+     *
+     *     FF         FF         FF         BC
+     * 1111 1111  1111 1111  1111 1111  1011 1100
+     *
+     * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+     * Bit[5] - 1 --> Do not skip stacking of additional state context.
+     * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+     * Bit[3] - 1 --> Return to the Thread mode.
+     * Bit[2] - 1 --> Restore registers from the process stack.
+     * Bit[1] - 0 --> Reserved, 0.
+     * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+     */
     #define portINITIAL_EXC_RETURN    ( 0xffffffbc )
 #endif /* configRUN_FREERTOS_SECURE_ONLY */
 
@@ -401,49 +398,49 @@ static void prvTaskExitError( void );
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Extract MPU region's access permissions from the Region Base Address
- * Register (RBAR) value.
- *
- * @param ulRBARValue RBAR value for the MPU region.
- *
- * @return uint32_t Access permissions.
- */
+    /**
+     * @brief Extract MPU region's access permissions from the Region Base Address
+     * Register (RBAR) value.
+     *
+     * @param ulRBARValue RBAR value for the MPU region.
+     *
+     * @return uint32_t Access permissions.
+     */
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Setup the Memory Protection Unit (MPU).
- */
+    /**
+     * @brief Setup the Memory Protection Unit (MPU).
+     */
     static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_MPU */
 
 #if ( configENABLE_FPU == 1 )
 
-/**
- * @brief Setup the Floating Point Unit (FPU).
- */
+    /**
+     * @brief Setup the Floating Point Unit (FPU).
+     */
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
 #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
-/**
- * @brief Configures PACBTI features.
- *
- * This function configures the Pointer Authentication, and Branch Target
- * Identification security features as per the user configuration. It returns
- * the value of the special purpose CONTROL register accordingly, and optionally
- * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
- * architecture based) target supports PACBTI security feature.
- *
- * @param xWriteControlRegister Used to control whether the special purpose
- * CONTROL register should be updated or not.
- *
- * @return CONTROL register value according to the configured PACBTI option.
- */
+    /**
+     * @brief Configures PACBTI features.
+     *
+     * This function configures the Pointer Authentication, and Branch Target
+     * Identification security features as per the user configuration. It returns
+     * the value of the special purpose CONTROL register accordingly, and optionally
+     * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
+     * architecture based) target supports PACBTI security feature.
+     *
+     * @param xWriteControlRegister Used to control whether the special purpose
+     * CONTROL register should be updated or not.
+     *
+     * @return CONTROL register value according to the configured PACBTI option.
+     */
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
 
 #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
@@ -491,14 +488,14 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Sets up the system call stack so that upon returning from
- * SVC, the system call stack is used.
- *
- * @param pulTaskStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
- * @param ucSystemCallNumber The system call number of the system call.
- */
+    /**
+     * @brief Sets up the system call stack so that upon returning from
+     * SVC, the system call stack is used.
+     *
+     * @param pulTaskStack The current SP when the SVC was raised.
+     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+     * @param ucSystemCallNumber The system call number of the system call.
+     */
     void vSystemCallEnter( uint32_t * pulTaskStack,
                            uint32_t ulLR,
                            uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION;
@@ -507,22 +504,22 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Raise SVC for exiting from a system call.
- */
+    /**
+     * @brief Raise SVC for exiting from a system call.
+     */
     void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Sets up the task stack so that upon returning from
- * SVC, the task stack is used again.
- *
- * @param pulSystemCallStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
- */
+    /**
+     * @brief Sets up the task stack so that upon returning from
+     * SVC, the task stack is used again.
+     *
+     * @param pulSystemCallStack The current SP when the SVC was raised.
+     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+     */
     void vSystemCallExit( uint32_t * pulSystemCallStack,
                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
@@ -530,11 +527,11 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Checks whether or not the calling task is privileged.
- *
- * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
- */
+    /**
+     * @brief Checks whether or not the calling task is privileged.
+     *
+     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+     */
     BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
 
 #endif /* configENABLE_MPU == 1 */
@@ -542,9 +539,9 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief This variable is set to pdTRUE when the scheduler is started.
- */
+    /**
+     * @brief This variable is set to pdTRUE when the scheduler is started.
+     */
     PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@@ -557,10 +554,10 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-/**
- * @brief Saved as part of the task context to indicate which context the
- * task is using on the secure side.
- */
+    /**
+     * @brief Saved as part of the task context to indicate which context the
+     * task is using on the secure side.
+     */
     PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
 #endif /* configENABLE_TRUSTZONE */
 
@@ -579,21 +576,21 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
 
-/**
- * @brief The number of SysTick increments that make up one tick period.
- */
+    /**
+     * @brief The number of SysTick increments that make up one tick period.
+     */
     PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0;
 
-/**
- * @brief The maximum number of tick periods that can be suppressed is
- * limited by the 24 bit resolution of the SysTick timer.
- */
+    /**
+     * @brief The maximum number of tick periods that can be suppressed is
+     * limited by the 24 bit resolution of the SysTick timer.
+     */
     PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0;
 
-/**
- * @brief Compensate for the CPU cycles that pass while the SysTick is
- * stopped (low power functionality only).
- */
+    /**
+     * @brief Compensate for the CPU cycles that pass while the SysTick is
+     * stopped (low power functionality only).
+     */
     PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0;
 #endif /* configUSE_TICKLESS_IDLE */
 /*-----------------------------------------------------------*/
@@ -925,64 +922,57 @@ static void prvTaskExitError( void )
         /* The only permitted number of regions are 8 or 16. */
         configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
 
-        /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
-        configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
+        /* MAIR0 - Index 0. */
+        portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+        /* MAIR0 - Index 1. */
+        portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
 
-        /* Check that the MPU is present. */
-        if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
-        {
-            /* MAIR0 - Index 0. */
-            portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
-            /* MAIR0 - Index 1. */
-            portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+        /* Setup privileged flash as Read Only so that privileged tasks can
+         * read it but not modify. */
+        portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_PRIVILEGED_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup privileged flash as Read Only so that privileged tasks can
-             * read it but not modify. */
-            portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_PRIVILEGED_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup unprivileged flash as Read Only by both privileged and
+         * unprivileged tasks. All tasks can read it but no-one can modify. */
+        portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup unprivileged flash as Read Only by both privileged and
-             * unprivileged tasks. All tasks can read it but no-one can modify. */
-            portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup unprivileged syscalls flash as Read Only by both privileged
+         * and unprivileged tasks. All tasks can read it but no-one can modify. */
+        portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup unprivileged syscalls flash as Read Only by both privileged
-             * and unprivileged tasks. All tasks can read it but no-one can modify. */
-            portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup RAM containing kernel data for privileged access only. */
+        portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+                           ( portMPU_REGION_EXECUTE_NEVER );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup RAM containing kernel data for privileged access only. */
-            portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
-                               ( portMPU_REGION_EXECUTE_NEVER );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Enable mem fault. */
+        portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;
 
-            /* Enable mem fault. */
-            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;
-
-            /* Enable MPU with privileged background access i.e. unmapped
-             * regions have privileged access. */
-            portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
-        }
+        /* Enable MPU with privileged background access i.e. unmapped
+         * regions have privileged access. */
+        portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
     }
 
 #endif /* configENABLE_MPU */
@@ -1108,47 +1098,47 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
     switch( ucSVCNumber )
     {
-        #if ( configENABLE_TRUSTZONE == 1 )
-            case portSVC_ALLOCATE_SECURE_CONTEXT:
+    #if ( configENABLE_TRUSTZONE == 1 )
+        case portSVC_ALLOCATE_SECURE_CONTEXT:
 
-                /* R0 contains the stack size passed as parameter to the
-                 * vPortAllocateSecureContext function. */
-                ulR0 = pulCallerStackAddress[ 0 ];
+            /* R0 contains the stack size passed as parameter to the
+             * vPortAllocateSecureContext function. */
+            ulR0 = pulCallerStackAddress[ 0 ];
 
-                #if ( configENABLE_MPU == 1 )
-                {
-                    /* Read the CONTROL register value. */
-                    __asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
+            #if ( configENABLE_MPU == 1 )
+            {
+                /* Read the CONTROL register value. */
+                __asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
 
-                    /* The task that raised the SVC is privileged if Bit[0]
-                     * in the CONTROL register is 0. */
-                    ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+                /* The task that raised the SVC is privileged if Bit[0]
+                 * in the CONTROL register is 0. */
+                ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
 
-                    /* Allocate and load a context for the secure task. */
-                    xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
-                }
-                #else /* if ( configENABLE_MPU == 1 ) */
-                {
-                    /* Allocate and load a context for the secure task. */
-                    xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
-                }
-                #endif /* configENABLE_MPU */
+                /* Allocate and load a context for the secure task. */
+                xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
+            }
+            #else /* if ( configENABLE_MPU == 1 ) */
+            {
+                /* Allocate and load a context for the secure task. */
+                xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
+            }
+            #endif /* configENABLE_MPU */
 
-                configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );
-                SecureContext_LoadContext( xSecureContext, pxCurrentTCB );
-                break;
+            configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );
+            SecureContext_LoadContext( xSecureContext, pxCurrentTCB );
+            break;
 
-            case portSVC_FREE_SECURE_CONTEXT:
+        case portSVC_FREE_SECURE_CONTEXT:
 
-                /* R0 contains TCB being freed and R1 contains the secure
-                 * context handle to be freed. */
-                ulR0 = pulCallerStackAddress[ 0 ];
-                ulR1 = pulCallerStackAddress[ 1 ];
+            /* R0 contains TCB being freed and R1 contains the secure
+             * context handle to be freed. */
+            ulR0 = pulCallerStackAddress[ 0 ];
+            ulR1 = pulCallerStackAddress[ 1 ];
 
-                /* Free the secure context. */
-                SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );
-                break;
-        #endif /* configENABLE_TRUSTZONE */
+            /* Free the secure context. */
+            SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );
+            break;
+    #endif /* configENABLE_TRUSTZONE */
 
         case portSVC_START_SCHEDULER:
             #if ( configENABLE_TRUSTZONE == 1 )
@@ -1174,24 +1164,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             vRestoreContextOfFirstTask();
             break;
 
-            #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
-                case portSVC_RAISE_PRIVILEGE:
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+        case portSVC_RAISE_PRIVILEGE:
 
-                    /* Only raise the privilege, if the svc was raised from any of
-                     * the system calls. */
-                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
-                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
-                    {
-                        vRaisePrivilege();
-                    }
-                    break;
-            #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+            /* Only raise the privilege, if the svc was raised from any of
+             * the system calls. */
+            if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+                ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+            {
+                vRaisePrivilege();
+            }
+            break;
+    #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
-            #if ( configENABLE_MPU == 1 )
-                case portSVC_YIELD:
-                    vPortYield();
-                    break;
-            #endif /* configENABLE_MPU == 1 */
+    #if ( configENABLE_MPU == 1 )
+        case portSVC_YIELD:
+            vPortYield();
+            break;
+    #endif /* configENABLE_MPU == 1 */
 
         default:
             /* Incorrect SVC call. */
@@ -1518,21 +1508,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
         ulIndex++;
 
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters;            /* r0. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x01010101;                           /* r1. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x02020202;                           /* r2. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x03030303;                           /* r3. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x12121212;                           /* r12. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
         ulIndex++;
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode;                  /* PC. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR;                     /* xPSR. */
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
         ulIndex++;
 
         #if ( configENABLE_TRUSTZONE == 1 )
@@ -1543,7 +1533,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         #endif /* configENABLE_TRUSTZONE */
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
         ulIndex++;
 
         #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
@@ -1615,15 +1605,15 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
          * interrupt. */
         #if ( portPRELOAD_REGISTERS == 0 )
         {
-            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
+            pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-            pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
-            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-            pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
+            pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
+            *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */
+            pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */
             *pxTopOfStack = portINITIAL_EXC_RETURN;
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
@@ -1637,42 +1627,42 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #else /* portPRELOAD_REGISTERS */
         {
-            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
+            pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
+            *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
+            *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
+            *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
+            *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
+            *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
+            *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
+            *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
+            *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
+            *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
+            *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
+            *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
+            *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04. */
             pxTopOfStack--;
-            *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
+            *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxEndOfStack;            /* Slot used to hold this task's PSPLIM value. */
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
 
             #if ( configENABLE_TRUSTZONE == 1 )
             {
diff --git a/portable/GCC/ARM_CM55/non_secure/port.c b/portable/GCC/ARM_CM55/non_secure/port.c
index b2fd7e518..a7fb054bc 100644
--- a/portable/GCC/ARM_CM55/non_secure/port.c
+++ b/portable/GCC/ARM_CM55/non_secure/port.c
@@ -145,13 +145,13 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the FPU.
  */
-#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 )              /* Coprocessor Access Control Register. */
+#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */
 #define portCPACR_CP10_VALUE    ( 3UL )
 #define portCPACR_CP11_VALUE    portCPACR_CP10_VALUE
 #define portCPACR_CP10_POS      ( 20UL )
 #define portCPACR_CP11_POS      ( 22UL )
 
-#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 )              /* Floating Point Context Control Register. */
+#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */
 #define portFPCCR_ASPEN_POS     ( 31UL )
 #define portFPCCR_ASPEN_MASK    ( 1UL << portFPCCR_ASPEN_POS )
 #define portFPCCR_LSPEN_POS     ( 30UL )
@@ -188,8 +188,8 @@ typedef void ( * portISR_t )( void );
 #define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
 #define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
 #define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
@@ -230,8 +230,8 @@ typedef void ( * portISR_t )( void );
 
 #if ( portARMV8M_MINOR_VERSION >= 1 )
 
-/* Enable Privileged eXecute Never MPU attribute for the selected memory
- * region. */
+    /* Enable Privileged eXecute Never MPU attribute for the selected memory
+     * region. */
     #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER    ( 1UL << 4UL )
 #endif /* portARMV8M_MINOR_VERSION >= 1 */
 
@@ -241,9 +241,6 @@ typedef void ( * portISR_t )( void );
 /* Enable MPU. */
 #define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
 
-/* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
-
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
 #define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \
@@ -291,37 +288,37 @@ typedef void ( * portISR_t )( void );
 
 #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
 
-/**
- * @brief Initial EXC_RETURN value.
- *
- *     FF         FF         FF         FD
- * 1111 1111  1111 1111  1111 1111  1111 1101
- *
- * Bit[6] - 1 --> The exception was taken from the Secure state.
- * Bit[5] - 1 --> Do not skip stacking of additional state context.
- * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
- * Bit[3] - 1 --> Return to the Thread mode.
- * Bit[2] - 1 --> Restore registers from the process stack.
- * Bit[1] - 0 --> Reserved, 0.
- * Bit[0] - 1 --> The exception was taken to the Secure state.
- */
+    /**
+     * @brief Initial EXC_RETURN value.
+     *
+     *     FF         FF         FF         FD
+     * 1111 1111  1111 1111  1111 1111  1111 1101
+     *
+     * Bit[6] - 1 --> The exception was taken from the Secure state.
+     * Bit[5] - 1 --> Do not skip stacking of additional state context.
+     * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+     * Bit[3] - 1 --> Return to the Thread mode.
+     * Bit[2] - 1 --> Restore registers from the process stack.
+     * Bit[1] - 0 --> Reserved, 0.
+     * Bit[0] - 1 --> The exception was taken to the Secure state.
+     */
     #define portINITIAL_EXC_RETURN    ( 0xfffffffd )
 #else
 
-/**
- * @brief Initial EXC_RETURN value.
- *
- *     FF         FF         FF         BC
- * 1111 1111  1111 1111  1111 1111  1011 1100
- *
- * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
- * Bit[5] - 1 --> Do not skip stacking of additional state context.
- * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
- * Bit[3] - 1 --> Return to the Thread mode.
- * Bit[2] - 1 --> Restore registers from the process stack.
- * Bit[1] - 0 --> Reserved, 0.
- * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
- */
+    /**
+     * @brief Initial EXC_RETURN value.
+     *
+     *     FF         FF         FF         BC
+     * 1111 1111  1111 1111  1111 1111  1011 1100
+     *
+     * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+     * Bit[5] - 1 --> Do not skip stacking of additional state context.
+     * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+     * Bit[3] - 1 --> Return to the Thread mode.
+     * Bit[2] - 1 --> Restore registers from the process stack.
+     * Bit[1] - 0 --> Reserved, 0.
+     * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+     */
     #define portINITIAL_EXC_RETURN    ( 0xffffffbc )
 #endif /* configRUN_FREERTOS_SECURE_ONLY */
 
@@ -401,49 +398,49 @@ static void prvTaskExitError( void );
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Extract MPU region's access permissions from the Region Base Address
- * Register (RBAR) value.
- *
- * @param ulRBARValue RBAR value for the MPU region.
- *
- * @return uint32_t Access permissions.
- */
+    /**
+     * @brief Extract MPU region's access permissions from the Region Base Address
+     * Register (RBAR) value.
+     *
+     * @param ulRBARValue RBAR value for the MPU region.
+     *
+     * @return uint32_t Access permissions.
+     */
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Setup the Memory Protection Unit (MPU).
- */
+    /**
+     * @brief Setup the Memory Protection Unit (MPU).
+     */
     static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_MPU */
 
 #if ( configENABLE_FPU == 1 )
 
-/**
- * @brief Setup the Floating Point Unit (FPU).
- */
+    /**
+     * @brief Setup the Floating Point Unit (FPU).
+     */
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
 #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
-/**
- * @brief Configures PACBTI features.
- *
- * This function configures the Pointer Authentication, and Branch Target
- * Identification security features as per the user configuration. It returns
- * the value of the special purpose CONTROL register accordingly, and optionally
- * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
- * architecture based) target supports PACBTI security feature.
- *
- * @param xWriteControlRegister Used to control whether the special purpose
- * CONTROL register should be updated or not.
- *
- * @return CONTROL register value according to the configured PACBTI option.
- */
+    /**
+     * @brief Configures PACBTI features.
+     *
+     * This function configures the Pointer Authentication, and Branch Target
+     * Identification security features as per the user configuration. It returns
+     * the value of the special purpose CONTROL register accordingly, and optionally
+     * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
+     * architecture based) target supports PACBTI security feature.
+     *
+     * @param xWriteControlRegister Used to control whether the special purpose
+     * CONTROL register should be updated or not.
+     *
+     * @return CONTROL register value according to the configured PACBTI option.
+     */
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
 
 #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
@@ -491,14 +488,14 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Sets up the system call stack so that upon returning from
- * SVC, the system call stack is used.
- *
- * @param pulTaskStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
- * @param ucSystemCallNumber The system call number of the system call.
- */
+    /**
+     * @brief Sets up the system call stack so that upon returning from
+     * SVC, the system call stack is used.
+     *
+     * @param pulTaskStack The current SP when the SVC was raised.
+     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+     * @param ucSystemCallNumber The system call number of the system call.
+     */
     void vSystemCallEnter( uint32_t * pulTaskStack,
                            uint32_t ulLR,
                            uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION;
@@ -507,22 +504,22 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Raise SVC for exiting from a system call.
- */
+    /**
+     * @brief Raise SVC for exiting from a system call.
+     */
     void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Sets up the task stack so that upon returning from
- * SVC, the task stack is used again.
- *
- * @param pulSystemCallStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
- */
+    /**
+     * @brief Sets up the task stack so that upon returning from
+     * SVC, the task stack is used again.
+     *
+     * @param pulSystemCallStack The current SP when the SVC was raised.
+     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+     */
     void vSystemCallExit( uint32_t * pulSystemCallStack,
                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
@@ -530,11 +527,11 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Checks whether or not the calling task is privileged.
- *
- * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
- */
+    /**
+     * @brief Checks whether or not the calling task is privileged.
+     *
+     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+     */
     BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
 
 #endif /* configENABLE_MPU == 1 */
@@ -542,9 +539,9 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief This variable is set to pdTRUE when the scheduler is started.
- */
+    /**
+     * @brief This variable is set to pdTRUE when the scheduler is started.
+     */
     PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@@ -557,10 +554,10 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-/**
- * @brief Saved as part of the task context to indicate which context the
- * task is using on the secure side.
- */
+    /**
+     * @brief Saved as part of the task context to indicate which context the
+     * task is using on the secure side.
+     */
     PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
 #endif /* configENABLE_TRUSTZONE */
 
@@ -579,21 +576,21 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
 
-/**
- * @brief The number of SysTick increments that make up one tick period.
- */
+    /**
+     * @brief The number of SysTick increments that make up one tick period.
+     */
     PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0;
 
-/**
- * @brief The maximum number of tick periods that can be suppressed is
- * limited by the 24 bit resolution of the SysTick timer.
- */
+    /**
+     * @brief The maximum number of tick periods that can be suppressed is
+     * limited by the 24 bit resolution of the SysTick timer.
+     */
     PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0;
 
-/**
- * @brief Compensate for the CPU cycles that pass while the SysTick is
- * stopped (low power functionality only).
- */
+    /**
+     * @brief Compensate for the CPU cycles that pass while the SysTick is
+     * stopped (low power functionality only).
+     */
     PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0;
 #endif /* configUSE_TICKLESS_IDLE */
 /*-----------------------------------------------------------*/
@@ -925,64 +922,57 @@ static void prvTaskExitError( void )
         /* The only permitted number of regions are 8 or 16. */
         configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
 
-        /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
-        configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
+        /* MAIR0 - Index 0. */
+        portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+        /* MAIR0 - Index 1. */
+        portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
 
-        /* Check that the MPU is present. */
-        if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
-        {
-            /* MAIR0 - Index 0. */
-            portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
-            /* MAIR0 - Index 1. */
-            portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+        /* Setup privileged flash as Read Only so that privileged tasks can
+         * read it but not modify. */
+        portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_PRIVILEGED_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup privileged flash as Read Only so that privileged tasks can
-             * read it but not modify. */
-            portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_PRIVILEGED_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup unprivileged flash as Read Only by both privileged and
+         * unprivileged tasks. All tasks can read it but no-one can modify. */
+        portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup unprivileged flash as Read Only by both privileged and
-             * unprivileged tasks. All tasks can read it but no-one can modify. */
-            portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup unprivileged syscalls flash as Read Only by both privileged
+         * and unprivileged tasks. All tasks can read it but no-one can modify. */
+        portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup unprivileged syscalls flash as Read Only by both privileged
-             * and unprivileged tasks. All tasks can read it but no-one can modify. */
-            portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup RAM containing kernel data for privileged access only. */
+        portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+                           ( portMPU_REGION_EXECUTE_NEVER );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup RAM containing kernel data for privileged access only. */
-            portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
-                               ( portMPU_REGION_EXECUTE_NEVER );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Enable mem fault. */
+        portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;
 
-            /* Enable mem fault. */
-            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;
-
-            /* Enable MPU with privileged background access i.e. unmapped
-             * regions have privileged access. */
-            portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
-        }
+        /* Enable MPU with privileged background access i.e. unmapped
+         * regions have privileged access. */
+        portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
     }
 
 #endif /* configENABLE_MPU */
@@ -1108,47 +1098,47 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
     switch( ucSVCNumber )
     {
-        #if ( configENABLE_TRUSTZONE == 1 )
-            case portSVC_ALLOCATE_SECURE_CONTEXT:
+    #if ( configENABLE_TRUSTZONE == 1 )
+        case portSVC_ALLOCATE_SECURE_CONTEXT:
 
-                /* R0 contains the stack size passed as parameter to the
-                 * vPortAllocateSecureContext function. */
-                ulR0 = pulCallerStackAddress[ 0 ];
+            /* R0 contains the stack size passed as parameter to the
+             * vPortAllocateSecureContext function. */
+            ulR0 = pulCallerStackAddress[ 0 ];
 
-                #if ( configENABLE_MPU == 1 )
-                {
-                    /* Read the CONTROL register value. */
-                    __asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
+            #if ( configENABLE_MPU == 1 )
+            {
+                /* Read the CONTROL register value. */
+                __asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
 
-                    /* The task that raised the SVC is privileged if Bit[0]
-                     * in the CONTROL register is 0. */
-                    ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+                /* The task that raised the SVC is privileged if Bit[0]
+                 * in the CONTROL register is 0. */
+                ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
 
-                    /* Allocate and load a context for the secure task. */
-                    xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
-                }
-                #else /* if ( configENABLE_MPU == 1 ) */
-                {
-                    /* Allocate and load a context for the secure task. */
-                    xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
-                }
-                #endif /* configENABLE_MPU */
+                /* Allocate and load a context for the secure task. */
+                xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
+            }
+            #else /* if ( configENABLE_MPU == 1 ) */
+            {
+                /* Allocate and load a context for the secure task. */
+                xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
+            }
+            #endif /* configENABLE_MPU */
 
-                configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );
-                SecureContext_LoadContext( xSecureContext, pxCurrentTCB );
-                break;
+            configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );
+            SecureContext_LoadContext( xSecureContext, pxCurrentTCB );
+            break;
 
-            case portSVC_FREE_SECURE_CONTEXT:
+        case portSVC_FREE_SECURE_CONTEXT:
 
-                /* R0 contains TCB being freed and R1 contains the secure
-                 * context handle to be freed. */
-                ulR0 = pulCallerStackAddress[ 0 ];
-                ulR1 = pulCallerStackAddress[ 1 ];
+            /* R0 contains TCB being freed and R1 contains the secure
+             * context handle to be freed. */
+            ulR0 = pulCallerStackAddress[ 0 ];
+            ulR1 = pulCallerStackAddress[ 1 ];
 
-                /* Free the secure context. */
-                SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );
-                break;
-        #endif /* configENABLE_TRUSTZONE */
+            /* Free the secure context. */
+            SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );
+            break;
+    #endif /* configENABLE_TRUSTZONE */
 
         case portSVC_START_SCHEDULER:
             #if ( configENABLE_TRUSTZONE == 1 )
@@ -1174,24 +1164,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             vRestoreContextOfFirstTask();
             break;
 
-            #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
-                case portSVC_RAISE_PRIVILEGE:
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+        case portSVC_RAISE_PRIVILEGE:
 
-                    /* Only raise the privilege, if the svc was raised from any of
-                     * the system calls. */
-                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
-                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
-                    {
-                        vRaisePrivilege();
-                    }
-                    break;
-            #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+            /* Only raise the privilege, if the svc was raised from any of
+             * the system calls. */
+            if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+                ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+            {
+                vRaisePrivilege();
+            }
+            break;
+    #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
-            #if ( configENABLE_MPU == 1 )
-                case portSVC_YIELD:
-                    vPortYield();
-                    break;
-            #endif /* configENABLE_MPU == 1 */
+    #if ( configENABLE_MPU == 1 )
+        case portSVC_YIELD:
+            vPortYield();
+            break;
+    #endif /* configENABLE_MPU == 1 */
 
         default:
             /* Incorrect SVC call. */
@@ -1518,21 +1508,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
         ulIndex++;
 
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters;            /* r0. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x01010101;                           /* r1. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x02020202;                           /* r2. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x03030303;                           /* r3. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x12121212;                           /* r12. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
         ulIndex++;
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode;                  /* PC. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR;                     /* xPSR. */
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
         ulIndex++;
 
         #if ( configENABLE_TRUSTZONE == 1 )
@@ -1543,7 +1533,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         #endif /* configENABLE_TRUSTZONE */
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
         ulIndex++;
 
         #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
@@ -1615,15 +1605,15 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
          * interrupt. */
         #if ( portPRELOAD_REGISTERS == 0 )
         {
-            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
+            pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-            pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
-            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-            pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
+            pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
+            *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */
+            pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */
             *pxTopOfStack = portINITIAL_EXC_RETURN;
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
@@ -1637,42 +1627,42 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #else /* portPRELOAD_REGISTERS */
         {
-            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
+            pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
+            *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
+            *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
+            *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
+            *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
+            *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
+            *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
+            *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
+            *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
+            *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
+            *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
+            *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
+            *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04. */
             pxTopOfStack--;
-            *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
+            *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxEndOfStack;            /* Slot used to hold this task's PSPLIM value. */
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
 
             #if ( configENABLE_TRUSTZONE == 1 )
             {
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/port.c b/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
index b2fd7e518..a7fb054bc 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
@@ -145,13 +145,13 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the FPU.
  */
-#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 )              /* Coprocessor Access Control Register. */
+#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */
 #define portCPACR_CP10_VALUE    ( 3UL )
 #define portCPACR_CP11_VALUE    portCPACR_CP10_VALUE
 #define portCPACR_CP10_POS      ( 20UL )
 #define portCPACR_CP11_POS      ( 22UL )
 
-#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 )              /* Floating Point Context Control Register. */
+#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */
 #define portFPCCR_ASPEN_POS     ( 31UL )
 #define portFPCCR_ASPEN_MASK    ( 1UL << portFPCCR_ASPEN_POS )
 #define portFPCCR_LSPEN_POS     ( 30UL )
@@ -188,8 +188,8 @@ typedef void ( * portISR_t )( void );
 #define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
 #define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
 #define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
@@ -230,8 +230,8 @@ typedef void ( * portISR_t )( void );
 
 #if ( portARMV8M_MINOR_VERSION >= 1 )
 
-/* Enable Privileged eXecute Never MPU attribute for the selected memory
- * region. */
+    /* Enable Privileged eXecute Never MPU attribute for the selected memory
+     * region. */
     #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER    ( 1UL << 4UL )
 #endif /* portARMV8M_MINOR_VERSION >= 1 */
 
@@ -241,9 +241,6 @@ typedef void ( * portISR_t )( void );
 /* Enable MPU. */
 #define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
 
-/* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
-
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
 #define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \
@@ -291,37 +288,37 @@ typedef void ( * portISR_t )( void );
 
 #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
 
-/**
- * @brief Initial EXC_RETURN value.
- *
- *     FF         FF         FF         FD
- * 1111 1111  1111 1111  1111 1111  1111 1101
- *
- * Bit[6] - 1 --> The exception was taken from the Secure state.
- * Bit[5] - 1 --> Do not skip stacking of additional state context.
- * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
- * Bit[3] - 1 --> Return to the Thread mode.
- * Bit[2] - 1 --> Restore registers from the process stack.
- * Bit[1] - 0 --> Reserved, 0.
- * Bit[0] - 1 --> The exception was taken to the Secure state.
- */
+    /**
+     * @brief Initial EXC_RETURN value.
+     *
+     *     FF         FF         FF         FD
+     * 1111 1111  1111 1111  1111 1111  1111 1101
+     *
+     * Bit[6] - 1 --> The exception was taken from the Secure state.
+     * Bit[5] - 1 --> Do not skip stacking of additional state context.
+     * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+     * Bit[3] - 1 --> Return to the Thread mode.
+     * Bit[2] - 1 --> Restore registers from the process stack.
+     * Bit[1] - 0 --> Reserved, 0.
+     * Bit[0] - 1 --> The exception was taken to the Secure state.
+     */
     #define portINITIAL_EXC_RETURN    ( 0xfffffffd )
 #else
 
-/**
- * @brief Initial EXC_RETURN value.
- *
- *     FF         FF         FF         BC
- * 1111 1111  1111 1111  1111 1111  1011 1100
- *
- * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
- * Bit[5] - 1 --> Do not skip stacking of additional state context.
- * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
- * Bit[3] - 1 --> Return to the Thread mode.
- * Bit[2] - 1 --> Restore registers from the process stack.
- * Bit[1] - 0 --> Reserved, 0.
- * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
- */
+    /**
+     * @brief Initial EXC_RETURN value.
+     *
+     *     FF         FF         FF         BC
+     * 1111 1111  1111 1111  1111 1111  1011 1100
+     *
+     * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+     * Bit[5] - 1 --> Do not skip stacking of additional state context.
+     * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+     * Bit[3] - 1 --> Return to the Thread mode.
+     * Bit[2] - 1 --> Restore registers from the process stack.
+     * Bit[1] - 0 --> Reserved, 0.
+     * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+     */
     #define portINITIAL_EXC_RETURN    ( 0xffffffbc )
 #endif /* configRUN_FREERTOS_SECURE_ONLY */
 
@@ -401,49 +398,49 @@ static void prvTaskExitError( void );
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Extract MPU region's access permissions from the Region Base Address
- * Register (RBAR) value.
- *
- * @param ulRBARValue RBAR value for the MPU region.
- *
- * @return uint32_t Access permissions.
- */
+    /**
+     * @brief Extract MPU region's access permissions from the Region Base Address
+     * Register (RBAR) value.
+     *
+     * @param ulRBARValue RBAR value for the MPU region.
+     *
+     * @return uint32_t Access permissions.
+     */
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Setup the Memory Protection Unit (MPU).
- */
+    /**
+     * @brief Setup the Memory Protection Unit (MPU).
+     */
     static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_MPU */
 
 #if ( configENABLE_FPU == 1 )
 
-/**
- * @brief Setup the Floating Point Unit (FPU).
- */
+    /**
+     * @brief Setup the Floating Point Unit (FPU).
+     */
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
 #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
-/**
- * @brief Configures PACBTI features.
- *
- * This function configures the Pointer Authentication, and Branch Target
- * Identification security features as per the user configuration. It returns
- * the value of the special purpose CONTROL register accordingly, and optionally
- * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
- * architecture based) target supports PACBTI security feature.
- *
- * @param xWriteControlRegister Used to control whether the special purpose
- * CONTROL register should be updated or not.
- *
- * @return CONTROL register value according to the configured PACBTI option.
- */
+    /**
+     * @brief Configures PACBTI features.
+     *
+     * This function configures the Pointer Authentication, and Branch Target
+     * Identification security features as per the user configuration. It returns
+     * the value of the special purpose CONTROL register accordingly, and optionally
+     * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
+     * architecture based) target supports PACBTI security feature.
+     *
+     * @param xWriteControlRegister Used to control whether the special purpose
+     * CONTROL register should be updated or not.
+     *
+     * @return CONTROL register value according to the configured PACBTI option.
+     */
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
 
 #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
@@ -491,14 +488,14 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Sets up the system call stack so that upon returning from
- * SVC, the system call stack is used.
- *
- * @param pulTaskStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
- * @param ucSystemCallNumber The system call number of the system call.
- */
+    /**
+     * @brief Sets up the system call stack so that upon returning from
+     * SVC, the system call stack is used.
+     *
+     * @param pulTaskStack The current SP when the SVC was raised.
+     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+     * @param ucSystemCallNumber The system call number of the system call.
+     */
     void vSystemCallEnter( uint32_t * pulTaskStack,
                            uint32_t ulLR,
                            uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION;
@@ -507,22 +504,22 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Raise SVC for exiting from a system call.
- */
+    /**
+     * @brief Raise SVC for exiting from a system call.
+     */
     void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Sets up the task stack so that upon returning from
- * SVC, the task stack is used again.
- *
- * @param pulSystemCallStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
- */
+    /**
+     * @brief Sets up the task stack so that upon returning from
+     * SVC, the task stack is used again.
+     *
+     * @param pulSystemCallStack The current SP when the SVC was raised.
+     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+     */
     void vSystemCallExit( uint32_t * pulSystemCallStack,
                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
@@ -530,11 +527,11 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Checks whether or not the calling task is privileged.
- *
- * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
- */
+    /**
+     * @brief Checks whether or not the calling task is privileged.
+     *
+     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+     */
     BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
 
 #endif /* configENABLE_MPU == 1 */
@@ -542,9 +539,9 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief This variable is set to pdTRUE when the scheduler is started.
- */
+    /**
+     * @brief This variable is set to pdTRUE when the scheduler is started.
+     */
     PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@@ -557,10 +554,10 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-/**
- * @brief Saved as part of the task context to indicate which context the
- * task is using on the secure side.
- */
+    /**
+     * @brief Saved as part of the task context to indicate which context the
+     * task is using on the secure side.
+     */
     PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
 #endif /* configENABLE_TRUSTZONE */
 
@@ -579,21 +576,21 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
 
-/**
- * @brief The number of SysTick increments that make up one tick period.
- */
+    /**
+     * @brief The number of SysTick increments that make up one tick period.
+     */
     PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0;
 
-/**
- * @brief The maximum number of tick periods that can be suppressed is
- * limited by the 24 bit resolution of the SysTick timer.
- */
+    /**
+     * @brief The maximum number of tick periods that can be suppressed is
+     * limited by the 24 bit resolution of the SysTick timer.
+     */
     PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0;
 
-/**
- * @brief Compensate for the CPU cycles that pass while the SysTick is
- * stopped (low power functionality only).
- */
+    /**
+     * @brief Compensate for the CPU cycles that pass while the SysTick is
+     * stopped (low power functionality only).
+     */
     PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0;
 #endif /* configUSE_TICKLESS_IDLE */
 /*-----------------------------------------------------------*/
@@ -925,64 +922,57 @@ static void prvTaskExitError( void )
         /* The only permitted number of regions are 8 or 16. */
         configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
 
-        /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
-        configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
+        /* MAIR0 - Index 0. */
+        portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+        /* MAIR0 - Index 1. */
+        portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
 
-        /* Check that the MPU is present. */
-        if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
-        {
-            /* MAIR0 - Index 0. */
-            portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
-            /* MAIR0 - Index 1. */
-            portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+        /* Setup privileged flash as Read Only so that privileged tasks can
+         * read it but not modify. */
+        portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_PRIVILEGED_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup privileged flash as Read Only so that privileged tasks can
-             * read it but not modify. */
-            portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_PRIVILEGED_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup unprivileged flash as Read Only by both privileged and
+         * unprivileged tasks. All tasks can read it but no-one can modify. */
+        portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup unprivileged flash as Read Only by both privileged and
-             * unprivileged tasks. All tasks can read it but no-one can modify. */
-            portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup unprivileged syscalls flash as Read Only by both privileged
+         * and unprivileged tasks. All tasks can read it but no-one can modify. */
+        portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup unprivileged syscalls flash as Read Only by both privileged
-             * and unprivileged tasks. All tasks can read it but no-one can modify. */
-            portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup RAM containing kernel data for privileged access only. */
+        portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+                           ( portMPU_REGION_EXECUTE_NEVER );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup RAM containing kernel data for privileged access only. */
-            portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
-                               ( portMPU_REGION_EXECUTE_NEVER );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Enable mem fault. */
+        portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;
 
-            /* Enable mem fault. */
-            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;
-
-            /* Enable MPU with privileged background access i.e. unmapped
-             * regions have privileged access. */
-            portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
-        }
+        /* Enable MPU with privileged background access i.e. unmapped
+         * regions have privileged access. */
+        portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
     }
 
 #endif /* configENABLE_MPU */
@@ -1108,47 +1098,47 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
     switch( ucSVCNumber )
     {
-        #if ( configENABLE_TRUSTZONE == 1 )
-            case portSVC_ALLOCATE_SECURE_CONTEXT:
+    #if ( configENABLE_TRUSTZONE == 1 )
+        case portSVC_ALLOCATE_SECURE_CONTEXT:
 
-                /* R0 contains the stack size passed as parameter to the
-                 * vPortAllocateSecureContext function. */
-                ulR0 = pulCallerStackAddress[ 0 ];
+            /* R0 contains the stack size passed as parameter to the
+             * vPortAllocateSecureContext function. */
+            ulR0 = pulCallerStackAddress[ 0 ];
 
-                #if ( configENABLE_MPU == 1 )
-                {
-                    /* Read the CONTROL register value. */
-                    __asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
+            #if ( configENABLE_MPU == 1 )
+            {
+                /* Read the CONTROL register value. */
+                __asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
 
-                    /* The task that raised the SVC is privileged if Bit[0]
-                     * in the CONTROL register is 0. */
-                    ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+                /* The task that raised the SVC is privileged if Bit[0]
+                 * in the CONTROL register is 0. */
+                ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
 
-                    /* Allocate and load a context for the secure task. */
-                    xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
-                }
-                #else /* if ( configENABLE_MPU == 1 ) */
-                {
-                    /* Allocate and load a context for the secure task. */
-                    xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
-                }
-                #endif /* configENABLE_MPU */
+                /* Allocate and load a context for the secure task. */
+                xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
+            }
+            #else /* if ( configENABLE_MPU == 1 ) */
+            {
+                /* Allocate and load a context for the secure task. */
+                xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
+            }
+            #endif /* configENABLE_MPU */
 
-                configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );
-                SecureContext_LoadContext( xSecureContext, pxCurrentTCB );
-                break;
+            configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );
+            SecureContext_LoadContext( xSecureContext, pxCurrentTCB );
+            break;
 
-            case portSVC_FREE_SECURE_CONTEXT:
+        case portSVC_FREE_SECURE_CONTEXT:
 
-                /* R0 contains TCB being freed and R1 contains the secure
-                 * context handle to be freed. */
-                ulR0 = pulCallerStackAddress[ 0 ];
-                ulR1 = pulCallerStackAddress[ 1 ];
+            /* R0 contains TCB being freed and R1 contains the secure
+             * context handle to be freed. */
+            ulR0 = pulCallerStackAddress[ 0 ];
+            ulR1 = pulCallerStackAddress[ 1 ];
 
-                /* Free the secure context. */
-                SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );
-                break;
-        #endif /* configENABLE_TRUSTZONE */
+            /* Free the secure context. */
+            SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );
+            break;
+    #endif /* configENABLE_TRUSTZONE */
 
         case portSVC_START_SCHEDULER:
             #if ( configENABLE_TRUSTZONE == 1 )
@@ -1174,24 +1164,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             vRestoreContextOfFirstTask();
             break;
 
-            #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
-                case portSVC_RAISE_PRIVILEGE:
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+        case portSVC_RAISE_PRIVILEGE:
 
-                    /* Only raise the privilege, if the svc was raised from any of
-                     * the system calls. */
-                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
-                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
-                    {
-                        vRaisePrivilege();
-                    }
-                    break;
-            #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+            /* Only raise the privilege, if the svc was raised from any of
+             * the system calls. */
+            if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+                ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+            {
+                vRaisePrivilege();
+            }
+            break;
+    #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
-            #if ( configENABLE_MPU == 1 )
-                case portSVC_YIELD:
-                    vPortYield();
-                    break;
-            #endif /* configENABLE_MPU == 1 */
+    #if ( configENABLE_MPU == 1 )
+        case portSVC_YIELD:
+            vPortYield();
+            break;
+    #endif /* configENABLE_MPU == 1 */
 
         default:
             /* Incorrect SVC call. */
@@ -1518,21 +1508,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
         ulIndex++;
 
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters;            /* r0. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x01010101;                           /* r1. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x02020202;                           /* r2. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x03030303;                           /* r3. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x12121212;                           /* r12. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
         ulIndex++;
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode;                  /* PC. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR;                     /* xPSR. */
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
         ulIndex++;
 
         #if ( configENABLE_TRUSTZONE == 1 )
@@ -1543,7 +1533,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         #endif /* configENABLE_TRUSTZONE */
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
         ulIndex++;
 
         #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
@@ -1615,15 +1605,15 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
          * interrupt. */
         #if ( portPRELOAD_REGISTERS == 0 )
         {
-            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
+            pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-            pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
-            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-            pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
+            pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
+            *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */
+            pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */
             *pxTopOfStack = portINITIAL_EXC_RETURN;
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
@@ -1637,42 +1627,42 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #else /* portPRELOAD_REGISTERS */
         {
-            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
+            pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
+            *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
+            *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
+            *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
+            *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
+            *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
+            *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
+            *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
+            *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
+            *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
+            *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
+            *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
+            *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04. */
             pxTopOfStack--;
-            *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
+            *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxEndOfStack;            /* Slot used to hold this task's PSPLIM value. */
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
 
             #if ( configENABLE_TRUSTZONE == 1 )
             {
diff --git a/portable/GCC/ARM_CM85/non_secure/port.c b/portable/GCC/ARM_CM85/non_secure/port.c
index b2fd7e518..a7fb054bc 100644
--- a/portable/GCC/ARM_CM85/non_secure/port.c
+++ b/portable/GCC/ARM_CM85/non_secure/port.c
@@ -145,13 +145,13 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the FPU.
  */
-#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 )              /* Coprocessor Access Control Register. */
+#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */
 #define portCPACR_CP10_VALUE    ( 3UL )
 #define portCPACR_CP11_VALUE    portCPACR_CP10_VALUE
 #define portCPACR_CP10_POS      ( 20UL )
 #define portCPACR_CP11_POS      ( 22UL )
 
-#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 )              /* Floating Point Context Control Register. */
+#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */
 #define portFPCCR_ASPEN_POS     ( 31UL )
 #define portFPCCR_ASPEN_MASK    ( 1UL << portFPCCR_ASPEN_POS )
 #define portFPCCR_LSPEN_POS     ( 30UL )
@@ -188,8 +188,8 @@ typedef void ( * portISR_t )( void );
 #define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
 #define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
 #define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
@@ -230,8 +230,8 @@ typedef void ( * portISR_t )( void );
 
 #if ( portARMV8M_MINOR_VERSION >= 1 )
 
-/* Enable Privileged eXecute Never MPU attribute for the selected memory
- * region. */
+    /* Enable Privileged eXecute Never MPU attribute for the selected memory
+     * region. */
     #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER    ( 1UL << 4UL )
 #endif /* portARMV8M_MINOR_VERSION >= 1 */
 
@@ -241,9 +241,6 @@ typedef void ( * portISR_t )( void );
 /* Enable MPU. */
 #define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
 
-/* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
-
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
 #define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \
@@ -291,37 +288,37 @@ typedef void ( * portISR_t )( void );
 
 #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
 
-/**
- * @brief Initial EXC_RETURN value.
- *
- *     FF         FF         FF         FD
- * 1111 1111  1111 1111  1111 1111  1111 1101
- *
- * Bit[6] - 1 --> The exception was taken from the Secure state.
- * Bit[5] - 1 --> Do not skip stacking of additional state context.
- * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
- * Bit[3] - 1 --> Return to the Thread mode.
- * Bit[2] - 1 --> Restore registers from the process stack.
- * Bit[1] - 0 --> Reserved, 0.
- * Bit[0] - 1 --> The exception was taken to the Secure state.
- */
+    /**
+     * @brief Initial EXC_RETURN value.
+     *
+     *     FF         FF         FF         FD
+     * 1111 1111  1111 1111  1111 1111  1111 1101
+     *
+     * Bit[6] - 1 --> The exception was taken from the Secure state.
+     * Bit[5] - 1 --> Do not skip stacking of additional state context.
+     * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+     * Bit[3] - 1 --> Return to the Thread mode.
+     * Bit[2] - 1 --> Restore registers from the process stack.
+     * Bit[1] - 0 --> Reserved, 0.
+     * Bit[0] - 1 --> The exception was taken to the Secure state.
+     */
     #define portINITIAL_EXC_RETURN    ( 0xfffffffd )
 #else
 
-/**
- * @brief Initial EXC_RETURN value.
- *
- *     FF         FF         FF         BC
- * 1111 1111  1111 1111  1111 1111  1011 1100
- *
- * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
- * Bit[5] - 1 --> Do not skip stacking of additional state context.
- * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
- * Bit[3] - 1 --> Return to the Thread mode.
- * Bit[2] - 1 --> Restore registers from the process stack.
- * Bit[1] - 0 --> Reserved, 0.
- * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
- */
+    /**
+     * @brief Initial EXC_RETURN value.
+     *
+     *     FF         FF         FF         BC
+     * 1111 1111  1111 1111  1111 1111  1011 1100
+     *
+     * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+     * Bit[5] - 1 --> Do not skip stacking of additional state context.
+     * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+     * Bit[3] - 1 --> Return to the Thread mode.
+     * Bit[2] - 1 --> Restore registers from the process stack.
+     * Bit[1] - 0 --> Reserved, 0.
+     * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+     */
     #define portINITIAL_EXC_RETURN    ( 0xffffffbc )
 #endif /* configRUN_FREERTOS_SECURE_ONLY */
 
@@ -401,49 +398,49 @@ static void prvTaskExitError( void );
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Extract MPU region's access permissions from the Region Base Address
- * Register (RBAR) value.
- *
- * @param ulRBARValue RBAR value for the MPU region.
- *
- * @return uint32_t Access permissions.
- */
+    /**
+     * @brief Extract MPU region's access permissions from the Region Base Address
+     * Register (RBAR) value.
+     *
+     * @param ulRBARValue RBAR value for the MPU region.
+     *
+     * @return uint32_t Access permissions.
+     */
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Setup the Memory Protection Unit (MPU).
- */
+    /**
+     * @brief Setup the Memory Protection Unit (MPU).
+     */
     static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_MPU */
 
 #if ( configENABLE_FPU == 1 )
 
-/**
- * @brief Setup the Floating Point Unit (FPU).
- */
+    /**
+     * @brief Setup the Floating Point Unit (FPU).
+     */
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
 #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
-/**
- * @brief Configures PACBTI features.
- *
- * This function configures the Pointer Authentication, and Branch Target
- * Identification security features as per the user configuration. It returns
- * the value of the special purpose CONTROL register accordingly, and optionally
- * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
- * architecture based) target supports PACBTI security feature.
- *
- * @param xWriteControlRegister Used to control whether the special purpose
- * CONTROL register should be updated or not.
- *
- * @return CONTROL register value according to the configured PACBTI option.
- */
+    /**
+     * @brief Configures PACBTI features.
+     *
+     * This function configures the Pointer Authentication, and Branch Target
+     * Identification security features as per the user configuration. It returns
+     * the value of the special purpose CONTROL register accordingly, and optionally
+     * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
+     * architecture based) target supports PACBTI security feature.
+     *
+     * @param xWriteControlRegister Used to control whether the special purpose
+     * CONTROL register should be updated or not.
+     *
+     * @return CONTROL register value according to the configured PACBTI option.
+     */
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
 
 #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
@@ -491,14 +488,14 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Sets up the system call stack so that upon returning from
- * SVC, the system call stack is used.
- *
- * @param pulTaskStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
- * @param ucSystemCallNumber The system call number of the system call.
- */
+    /**
+     * @brief Sets up the system call stack so that upon returning from
+     * SVC, the system call stack is used.
+     *
+     * @param pulTaskStack The current SP when the SVC was raised.
+     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+     * @param ucSystemCallNumber The system call number of the system call.
+     */
     void vSystemCallEnter( uint32_t * pulTaskStack,
                            uint32_t ulLR,
                            uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION;
@@ -507,22 +504,22 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Raise SVC for exiting from a system call.
- */
+    /**
+     * @brief Raise SVC for exiting from a system call.
+     */
     void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Sets up the task stack so that upon returning from
- * SVC, the task stack is used again.
- *
- * @param pulSystemCallStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
- */
+    /**
+     * @brief Sets up the task stack so that upon returning from
+     * SVC, the task stack is used again.
+     *
+     * @param pulSystemCallStack The current SP when the SVC was raised.
+     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+     */
     void vSystemCallExit( uint32_t * pulSystemCallStack,
                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
@@ -530,11 +527,11 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Checks whether or not the calling task is privileged.
- *
- * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
- */
+    /**
+     * @brief Checks whether or not the calling task is privileged.
+     *
+     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+     */
     BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
 
 #endif /* configENABLE_MPU == 1 */
@@ -542,9 +539,9 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief This variable is set to pdTRUE when the scheduler is started.
- */
+    /**
+     * @brief This variable is set to pdTRUE when the scheduler is started.
+     */
     PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@@ -557,10 +554,10 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-/**
- * @brief Saved as part of the task context to indicate which context the
- * task is using on the secure side.
- */
+    /**
+     * @brief Saved as part of the task context to indicate which context the
+     * task is using on the secure side.
+     */
     PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
 #endif /* configENABLE_TRUSTZONE */
 
@@ -579,21 +576,21 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
 
-/**
- * @brief The number of SysTick increments that make up one tick period.
- */
+    /**
+     * @brief The number of SysTick increments that make up one tick period.
+     */
     PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0;
 
-/**
- * @brief The maximum number of tick periods that can be suppressed is
- * limited by the 24 bit resolution of the SysTick timer.
- */
+    /**
+     * @brief The maximum number of tick periods that can be suppressed is
+     * limited by the 24 bit resolution of the SysTick timer.
+     */
     PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0;
 
-/**
- * @brief Compensate for the CPU cycles that pass while the SysTick is
- * stopped (low power functionality only).
- */
+    /**
+     * @brief Compensate for the CPU cycles that pass while the SysTick is
+     * stopped (low power functionality only).
+     */
     PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0;
 #endif /* configUSE_TICKLESS_IDLE */
 /*-----------------------------------------------------------*/
@@ -925,64 +922,57 @@ static void prvTaskExitError( void )
         /* The only permitted number of regions are 8 or 16. */
         configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
 
-        /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
-        configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
+        /* MAIR0 - Index 0. */
+        portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+        /* MAIR0 - Index 1. */
+        portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
 
-        /* Check that the MPU is present. */
-        if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
-        {
-            /* MAIR0 - Index 0. */
-            portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
-            /* MAIR0 - Index 1. */
-            portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+        /* Setup privileged flash as Read Only so that privileged tasks can
+         * read it but not modify. */
+        portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_PRIVILEGED_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup privileged flash as Read Only so that privileged tasks can
-             * read it but not modify. */
-            portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_PRIVILEGED_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup unprivileged flash as Read Only by both privileged and
+         * unprivileged tasks. All tasks can read it but no-one can modify. */
+        portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup unprivileged flash as Read Only by both privileged and
-             * unprivileged tasks. All tasks can read it but no-one can modify. */
-            portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup unprivileged syscalls flash as Read Only by both privileged
+         * and unprivileged tasks. All tasks can read it but no-one can modify. */
+        portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup unprivileged syscalls flash as Read Only by both privileged
-             * and unprivileged tasks. All tasks can read it but no-one can modify. */
-            portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup RAM containing kernel data for privileged access only. */
+        portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+                           ( portMPU_REGION_EXECUTE_NEVER );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup RAM containing kernel data for privileged access only. */
-            portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
-                               ( portMPU_REGION_EXECUTE_NEVER );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Enable mem fault. */
+        portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;
 
-            /* Enable mem fault. */
-            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;
-
-            /* Enable MPU with privileged background access i.e. unmapped
-             * regions have privileged access. */
-            portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
-        }
+        /* Enable MPU with privileged background access i.e. unmapped
+         * regions have privileged access. */
+        portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
     }
 
 #endif /* configENABLE_MPU */
@@ -1108,47 +1098,47 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
     switch( ucSVCNumber )
     {
-        #if ( configENABLE_TRUSTZONE == 1 )
-            case portSVC_ALLOCATE_SECURE_CONTEXT:
+    #if ( configENABLE_TRUSTZONE == 1 )
+        case portSVC_ALLOCATE_SECURE_CONTEXT:
 
-                /* R0 contains the stack size passed as parameter to the
-                 * vPortAllocateSecureContext function. */
-                ulR0 = pulCallerStackAddress[ 0 ];
+            /* R0 contains the stack size passed as parameter to the
+             * vPortAllocateSecureContext function. */
+            ulR0 = pulCallerStackAddress[ 0 ];
 
-                #if ( configENABLE_MPU == 1 )
-                {
-                    /* Read the CONTROL register value. */
-                    __asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
+            #if ( configENABLE_MPU == 1 )
+            {
+                /* Read the CONTROL register value. */
+                __asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
 
-                    /* The task that raised the SVC is privileged if Bit[0]
-                     * in the CONTROL register is 0. */
-                    ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+                /* The task that raised the SVC is privileged if Bit[0]
+                 * in the CONTROL register is 0. */
+                ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
 
-                    /* Allocate and load a context for the secure task. */
-                    xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
-                }
-                #else /* if ( configENABLE_MPU == 1 ) */
-                {
-                    /* Allocate and load a context for the secure task. */
-                    xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
-                }
-                #endif /* configENABLE_MPU */
+                /* Allocate and load a context for the secure task. */
+                xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
+            }
+            #else /* if ( configENABLE_MPU == 1 ) */
+            {
+                /* Allocate and load a context for the secure task. */
+                xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
+            }
+            #endif /* configENABLE_MPU */
 
-                configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );
-                SecureContext_LoadContext( xSecureContext, pxCurrentTCB );
-                break;
+            configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );
+            SecureContext_LoadContext( xSecureContext, pxCurrentTCB );
+            break;
 
-            case portSVC_FREE_SECURE_CONTEXT:
+        case portSVC_FREE_SECURE_CONTEXT:
 
-                /* R0 contains TCB being freed and R1 contains the secure
-                 * context handle to be freed. */
-                ulR0 = pulCallerStackAddress[ 0 ];
-                ulR1 = pulCallerStackAddress[ 1 ];
+            /* R0 contains TCB being freed and R1 contains the secure
+             * context handle to be freed. */
+            ulR0 = pulCallerStackAddress[ 0 ];
+            ulR1 = pulCallerStackAddress[ 1 ];
 
-                /* Free the secure context. */
-                SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );
-                break;
-        #endif /* configENABLE_TRUSTZONE */
+            /* Free the secure context. */
+            SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );
+            break;
+    #endif /* configENABLE_TRUSTZONE */
 
         case portSVC_START_SCHEDULER:
             #if ( configENABLE_TRUSTZONE == 1 )
@@ -1174,24 +1164,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             vRestoreContextOfFirstTask();
             break;
 
-            #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
-                case portSVC_RAISE_PRIVILEGE:
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+        case portSVC_RAISE_PRIVILEGE:
 
-                    /* Only raise the privilege, if the svc was raised from any of
-                     * the system calls. */
-                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
-                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
-                    {
-                        vRaisePrivilege();
-                    }
-                    break;
-            #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+            /* Only raise the privilege, if the svc was raised from any of
+             * the system calls. */
+            if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+                ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+            {
+                vRaisePrivilege();
+            }
+            break;
+    #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
-            #if ( configENABLE_MPU == 1 )
-                case portSVC_YIELD:
-                    vPortYield();
-                    break;
-            #endif /* configENABLE_MPU == 1 */
+    #if ( configENABLE_MPU == 1 )
+        case portSVC_YIELD:
+            vPortYield();
+            break;
+    #endif /* configENABLE_MPU == 1 */
 
         default:
             /* Incorrect SVC call. */
@@ -1518,21 +1508,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
         ulIndex++;
 
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters;            /* r0. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x01010101;                           /* r1. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x02020202;                           /* r2. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x03030303;                           /* r3. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x12121212;                           /* r12. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
         ulIndex++;
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode;                  /* PC. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR;                     /* xPSR. */
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
         ulIndex++;
 
         #if ( configENABLE_TRUSTZONE == 1 )
@@ -1543,7 +1533,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         #endif /* configENABLE_TRUSTZONE */
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
         ulIndex++;
 
         #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
@@ -1615,15 +1605,15 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
          * interrupt. */
         #if ( portPRELOAD_REGISTERS == 0 )
         {
-            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
+            pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-            pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
-            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-            pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
+            pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
+            *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */
+            pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */
             *pxTopOfStack = portINITIAL_EXC_RETURN;
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
@@ -1637,42 +1627,42 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #else /* portPRELOAD_REGISTERS */
         {
-            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
+            pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
+            *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
+            *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
+            *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
+            *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
+            *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
+            *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
+            *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
+            *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
+            *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
+            *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
+            *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
+            *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04. */
             pxTopOfStack--;
-            *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
+            *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxEndOfStack;            /* Slot used to hold this task's PSPLIM value. */
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
 
             #if ( configENABLE_TRUSTZONE == 1 )
             {
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/port.c b/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
index b2fd7e518..a7fb054bc 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
@@ -145,13 +145,13 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the FPU.
  */
-#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 )              /* Coprocessor Access Control Register. */
+#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */
 #define portCPACR_CP10_VALUE    ( 3UL )
 #define portCPACR_CP11_VALUE    portCPACR_CP10_VALUE
 #define portCPACR_CP10_POS      ( 20UL )
 #define portCPACR_CP11_POS      ( 22UL )
 
-#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 )              /* Floating Point Context Control Register. */
+#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */
 #define portFPCCR_ASPEN_POS     ( 31UL )
 #define portFPCCR_ASPEN_MASK    ( 1UL << portFPCCR_ASPEN_POS )
 #define portFPCCR_LSPEN_POS     ( 30UL )
@@ -188,8 +188,8 @@ typedef void ( * portISR_t )( void );
 #define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
 #define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
 #define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
@@ -230,8 +230,8 @@ typedef void ( * portISR_t )( void );
 
 #if ( portARMV8M_MINOR_VERSION >= 1 )
 
-/* Enable Privileged eXecute Never MPU attribute for the selected memory
- * region. */
+    /* Enable Privileged eXecute Never MPU attribute for the selected memory
+     * region. */
     #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER    ( 1UL << 4UL )
 #endif /* portARMV8M_MINOR_VERSION >= 1 */
 
@@ -241,9 +241,6 @@ typedef void ( * portISR_t )( void );
 /* Enable MPU. */
 #define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
 
-/* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
-
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
 #define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \
@@ -291,37 +288,37 @@ typedef void ( * portISR_t )( void );
 
 #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
 
-/**
- * @brief Initial EXC_RETURN value.
- *
- *     FF         FF         FF         FD
- * 1111 1111  1111 1111  1111 1111  1111 1101
- *
- * Bit[6] - 1 --> The exception was taken from the Secure state.
- * Bit[5] - 1 --> Do not skip stacking of additional state context.
- * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
- * Bit[3] - 1 --> Return to the Thread mode.
- * Bit[2] - 1 --> Restore registers from the process stack.
- * Bit[1] - 0 --> Reserved, 0.
- * Bit[0] - 1 --> The exception was taken to the Secure state.
- */
+    /**
+     * @brief Initial EXC_RETURN value.
+     *
+     *     FF         FF         FF         FD
+     * 1111 1111  1111 1111  1111 1111  1111 1101
+     *
+     * Bit[6] - 1 --> The exception was taken from the Secure state.
+     * Bit[5] - 1 --> Do not skip stacking of additional state context.
+     * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+     * Bit[3] - 1 --> Return to the Thread mode.
+     * Bit[2] - 1 --> Restore registers from the process stack.
+     * Bit[1] - 0 --> Reserved, 0.
+     * Bit[0] - 1 --> The exception was taken to the Secure state.
+     */
     #define portINITIAL_EXC_RETURN    ( 0xfffffffd )
 #else
 
-/**
- * @brief Initial EXC_RETURN value.
- *
- *     FF         FF         FF         BC
- * 1111 1111  1111 1111  1111 1111  1011 1100
- *
- * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
- * Bit[5] - 1 --> Do not skip stacking of additional state context.
- * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
- * Bit[3] - 1 --> Return to the Thread mode.
- * Bit[2] - 1 --> Restore registers from the process stack.
- * Bit[1] - 0 --> Reserved, 0.
- * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
- */
+    /**
+     * @brief Initial EXC_RETURN value.
+     *
+     *     FF         FF         FF         BC
+     * 1111 1111  1111 1111  1111 1111  1011 1100
+     *
+     * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+     * Bit[5] - 1 --> Do not skip stacking of additional state context.
+     * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+     * Bit[3] - 1 --> Return to the Thread mode.
+     * Bit[2] - 1 --> Restore registers from the process stack.
+     * Bit[1] - 0 --> Reserved, 0.
+     * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+     */
     #define portINITIAL_EXC_RETURN    ( 0xffffffbc )
 #endif /* configRUN_FREERTOS_SECURE_ONLY */
 
@@ -401,49 +398,49 @@ static void prvTaskExitError( void );
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Extract MPU region's access permissions from the Region Base Address
- * Register (RBAR) value.
- *
- * @param ulRBARValue RBAR value for the MPU region.
- *
- * @return uint32_t Access permissions.
- */
+    /**
+     * @brief Extract MPU region's access permissions from the Region Base Address
+     * Register (RBAR) value.
+     *
+     * @param ulRBARValue RBAR value for the MPU region.
+     *
+     * @return uint32_t Access permissions.
+     */
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Setup the Memory Protection Unit (MPU).
- */
+    /**
+     * @brief Setup the Memory Protection Unit (MPU).
+     */
     static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_MPU */
 
 #if ( configENABLE_FPU == 1 )
 
-/**
- * @brief Setup the Floating Point Unit (FPU).
- */
+    /**
+     * @brief Setup the Floating Point Unit (FPU).
+     */
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
 #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
-/**
- * @brief Configures PACBTI features.
- *
- * This function configures the Pointer Authentication, and Branch Target
- * Identification security features as per the user configuration. It returns
- * the value of the special purpose CONTROL register accordingly, and optionally
- * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
- * architecture based) target supports PACBTI security feature.
- *
- * @param xWriteControlRegister Used to control whether the special purpose
- * CONTROL register should be updated or not.
- *
- * @return CONTROL register value according to the configured PACBTI option.
- */
+    /**
+     * @brief Configures PACBTI features.
+     *
+     * This function configures the Pointer Authentication, and Branch Target
+     * Identification security features as per the user configuration. It returns
+     * the value of the special purpose CONTROL register accordingly, and optionally
+     * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
+     * architecture based) target supports PACBTI security feature.
+     *
+     * @param xWriteControlRegister Used to control whether the special purpose
+     * CONTROL register should be updated or not.
+     *
+     * @return CONTROL register value according to the configured PACBTI option.
+     */
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
 
 #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
@@ -491,14 +488,14 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Sets up the system call stack so that upon returning from
- * SVC, the system call stack is used.
- *
- * @param pulTaskStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
- * @param ucSystemCallNumber The system call number of the system call.
- */
+    /**
+     * @brief Sets up the system call stack so that upon returning from
+     * SVC, the system call stack is used.
+     *
+     * @param pulTaskStack The current SP when the SVC was raised.
+     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+     * @param ucSystemCallNumber The system call number of the system call.
+     */
     void vSystemCallEnter( uint32_t * pulTaskStack,
                            uint32_t ulLR,
                            uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION;
@@ -507,22 +504,22 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Raise SVC for exiting from a system call.
- */
+    /**
+     * @brief Raise SVC for exiting from a system call.
+     */
     void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Sets up the task stack so that upon returning from
- * SVC, the task stack is used again.
- *
- * @param pulSystemCallStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
- */
+    /**
+     * @brief Sets up the task stack so that upon returning from
+     * SVC, the task stack is used again.
+     *
+     * @param pulSystemCallStack The current SP when the SVC was raised.
+     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+     */
     void vSystemCallExit( uint32_t * pulSystemCallStack,
                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
@@ -530,11 +527,11 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Checks whether or not the calling task is privileged.
- *
- * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
- */
+    /**
+     * @brief Checks whether or not the calling task is privileged.
+     *
+     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+     */
     BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
 
 #endif /* configENABLE_MPU == 1 */
@@ -542,9 +539,9 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief This variable is set to pdTRUE when the scheduler is started.
- */
+    /**
+     * @brief This variable is set to pdTRUE when the scheduler is started.
+     */
     PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@@ -557,10 +554,10 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-/**
- * @brief Saved as part of the task context to indicate which context the
- * task is using on the secure side.
- */
+    /**
+     * @brief Saved as part of the task context to indicate which context the
+     * task is using on the secure side.
+     */
     PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
 #endif /* configENABLE_TRUSTZONE */
 
@@ -579,21 +576,21 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
 
-/**
- * @brief The number of SysTick increments that make up one tick period.
- */
+    /**
+     * @brief The number of SysTick increments that make up one tick period.
+     */
     PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0;
 
-/**
- * @brief The maximum number of tick periods that can be suppressed is
- * limited by the 24 bit resolution of the SysTick timer.
- */
+    /**
+     * @brief The maximum number of tick periods that can be suppressed is
+     * limited by the 24 bit resolution of the SysTick timer.
+     */
     PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0;
 
-/**
- * @brief Compensate for the CPU cycles that pass while the SysTick is
- * stopped (low power functionality only).
- */
+    /**
+     * @brief Compensate for the CPU cycles that pass while the SysTick is
+     * stopped (low power functionality only).
+     */
     PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0;
 #endif /* configUSE_TICKLESS_IDLE */
 /*-----------------------------------------------------------*/
@@ -925,64 +922,57 @@ static void prvTaskExitError( void )
         /* The only permitted number of regions are 8 or 16. */
         configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
 
-        /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
-        configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
+        /* MAIR0 - Index 0. */
+        portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+        /* MAIR0 - Index 1. */
+        portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
 
-        /* Check that the MPU is present. */
-        if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
-        {
-            /* MAIR0 - Index 0. */
-            portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
-            /* MAIR0 - Index 1. */
-            portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+        /* Setup privileged flash as Read Only so that privileged tasks can
+         * read it but not modify. */
+        portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_PRIVILEGED_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup privileged flash as Read Only so that privileged tasks can
-             * read it but not modify. */
-            portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_PRIVILEGED_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup unprivileged flash as Read Only by both privileged and
+         * unprivileged tasks. All tasks can read it but no-one can modify. */
+        portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup unprivileged flash as Read Only by both privileged and
-             * unprivileged tasks. All tasks can read it but no-one can modify. */
-            portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup unprivileged syscalls flash as Read Only by both privileged
+         * and unprivileged tasks. All tasks can read it but no-one can modify. */
+        portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup unprivileged syscalls flash as Read Only by both privileged
-             * and unprivileged tasks. All tasks can read it but no-one can modify. */
-            portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup RAM containing kernel data for privileged access only. */
+        portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+                           ( portMPU_REGION_EXECUTE_NEVER );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup RAM containing kernel data for privileged access only. */
-            portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
-                               ( portMPU_REGION_EXECUTE_NEVER );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Enable mem fault. */
+        portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;
 
-            /* Enable mem fault. */
-            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;
-
-            /* Enable MPU with privileged background access i.e. unmapped
-             * regions have privileged access. */
-            portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
-        }
+        /* Enable MPU with privileged background access i.e. unmapped
+         * regions have privileged access. */
+        portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
     }
 
 #endif /* configENABLE_MPU */
@@ -1108,47 +1098,47 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
     switch( ucSVCNumber )
     {
-        #if ( configENABLE_TRUSTZONE == 1 )
-            case portSVC_ALLOCATE_SECURE_CONTEXT:
+    #if ( configENABLE_TRUSTZONE == 1 )
+        case portSVC_ALLOCATE_SECURE_CONTEXT:
 
-                /* R0 contains the stack size passed as parameter to the
-                 * vPortAllocateSecureContext function. */
-                ulR0 = pulCallerStackAddress[ 0 ];
+            /* R0 contains the stack size passed as parameter to the
+             * vPortAllocateSecureContext function. */
+            ulR0 = pulCallerStackAddress[ 0 ];
 
-                #if ( configENABLE_MPU == 1 )
-                {
-                    /* Read the CONTROL register value. */
-                    __asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
+            #if ( configENABLE_MPU == 1 )
+            {
+                /* Read the CONTROL register value. */
+                __asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
 
-                    /* The task that raised the SVC is privileged if Bit[0]
-                     * in the CONTROL register is 0. */
-                    ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+                /* The task that raised the SVC is privileged if Bit[0]
+                 * in the CONTROL register is 0. */
+                ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
 
-                    /* Allocate and load a context for the secure task. */
-                    xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
-                }
-                #else /* if ( configENABLE_MPU == 1 ) */
-                {
-                    /* Allocate and load a context for the secure task. */
-                    xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
-                }
-                #endif /* configENABLE_MPU */
+                /* Allocate and load a context for the secure task. */
+                xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
+            }
+            #else /* if ( configENABLE_MPU == 1 ) */
+            {
+                /* Allocate and load a context for the secure task. */
+                xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
+            }
+            #endif /* configENABLE_MPU */
 
-                configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );
-                SecureContext_LoadContext( xSecureContext, pxCurrentTCB );
-                break;
+            configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );
+            SecureContext_LoadContext( xSecureContext, pxCurrentTCB );
+            break;
 
-            case portSVC_FREE_SECURE_CONTEXT:
+        case portSVC_FREE_SECURE_CONTEXT:
 
-                /* R0 contains TCB being freed and R1 contains the secure
-                 * context handle to be freed. */
-                ulR0 = pulCallerStackAddress[ 0 ];
-                ulR1 = pulCallerStackAddress[ 1 ];
+            /* R0 contains TCB being freed and R1 contains the secure
+             * context handle to be freed. */
+            ulR0 = pulCallerStackAddress[ 0 ];
+            ulR1 = pulCallerStackAddress[ 1 ];
 
-                /* Free the secure context. */
-                SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );
-                break;
-        #endif /* configENABLE_TRUSTZONE */
+            /* Free the secure context. */
+            SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );
+            break;
+    #endif /* configENABLE_TRUSTZONE */
 
         case portSVC_START_SCHEDULER:
             #if ( configENABLE_TRUSTZONE == 1 )
@@ -1174,24 +1164,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             vRestoreContextOfFirstTask();
             break;
 
-            #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
-                case portSVC_RAISE_PRIVILEGE:
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+        case portSVC_RAISE_PRIVILEGE:
 
-                    /* Only raise the privilege, if the svc was raised from any of
-                     * the system calls. */
-                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
-                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
-                    {
-                        vRaisePrivilege();
-                    }
-                    break;
-            #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+            /* Only raise the privilege, if the svc was raised from any of
+             * the system calls. */
+            if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+                ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+            {
+                vRaisePrivilege();
+            }
+            break;
+    #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
-            #if ( configENABLE_MPU == 1 )
-                case portSVC_YIELD:
-                    vPortYield();
-                    break;
-            #endif /* configENABLE_MPU == 1 */
+    #if ( configENABLE_MPU == 1 )
+        case portSVC_YIELD:
+            vPortYield();
+            break;
+    #endif /* configENABLE_MPU == 1 */
 
         default:
             /* Incorrect SVC call. */
@@ -1518,21 +1508,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
         ulIndex++;
 
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters;            /* r0. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x01010101;                           /* r1. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x02020202;                           /* r2. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x03030303;                           /* r3. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x12121212;                           /* r12. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
         ulIndex++;
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode;                  /* PC. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR;                     /* xPSR. */
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
         ulIndex++;
 
         #if ( configENABLE_TRUSTZONE == 1 )
@@ -1543,7 +1533,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         #endif /* configENABLE_TRUSTZONE */
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
         ulIndex++;
 
         #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
@@ -1615,15 +1605,15 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
          * interrupt. */
         #if ( portPRELOAD_REGISTERS == 0 )
         {
-            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
+            pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-            pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
-            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-            pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
+            pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
+            *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */
+            pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */
             *pxTopOfStack = portINITIAL_EXC_RETURN;
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
@@ -1637,42 +1627,42 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #else /* portPRELOAD_REGISTERS */
         {
-            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
+            pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
+            *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
+            *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
+            *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
+            *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
+            *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
+            *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
+            *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
+            *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
+            *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
+            *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
+            *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
+            *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04. */
             pxTopOfStack--;
-            *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
+            *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxEndOfStack;            /* Slot used to hold this task's PSPLIM value. */
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
 
             #if ( configENABLE_TRUSTZONE == 1 )
             {
diff --git a/portable/IAR/ARM_CM23/non_secure/port.c b/portable/IAR/ARM_CM23/non_secure/port.c
index b2fd7e518..a7fb054bc 100644
--- a/portable/IAR/ARM_CM23/non_secure/port.c
+++ b/portable/IAR/ARM_CM23/non_secure/port.c
@@ -145,13 +145,13 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the FPU.
  */
-#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 )              /* Coprocessor Access Control Register. */
+#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */
 #define portCPACR_CP10_VALUE    ( 3UL )
 #define portCPACR_CP11_VALUE    portCPACR_CP10_VALUE
 #define portCPACR_CP10_POS      ( 20UL )
 #define portCPACR_CP11_POS      ( 22UL )
 
-#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 )              /* Floating Point Context Control Register. */
+#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */
 #define portFPCCR_ASPEN_POS     ( 31UL )
 #define portFPCCR_ASPEN_MASK    ( 1UL << portFPCCR_ASPEN_POS )
 #define portFPCCR_LSPEN_POS     ( 30UL )
@@ -188,8 +188,8 @@ typedef void ( * portISR_t )( void );
 #define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
 #define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
 #define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
@@ -230,8 +230,8 @@ typedef void ( * portISR_t )( void );
 
 #if ( portARMV8M_MINOR_VERSION >= 1 )
 
-/* Enable Privileged eXecute Never MPU attribute for the selected memory
- * region. */
+    /* Enable Privileged eXecute Never MPU attribute for the selected memory
+     * region. */
     #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER    ( 1UL << 4UL )
 #endif /* portARMV8M_MINOR_VERSION >= 1 */
 
@@ -241,9 +241,6 @@ typedef void ( * portISR_t )( void );
 /* Enable MPU. */
 #define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
 
-/* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
-
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
 #define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \
@@ -291,37 +288,37 @@ typedef void ( * portISR_t )( void );
 
 #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
 
-/**
- * @brief Initial EXC_RETURN value.
- *
- *     FF         FF         FF         FD
- * 1111 1111  1111 1111  1111 1111  1111 1101
- *
- * Bit[6] - 1 --> The exception was taken from the Secure state.
- * Bit[5] - 1 --> Do not skip stacking of additional state context.
- * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
- * Bit[3] - 1 --> Return to the Thread mode.
- * Bit[2] - 1 --> Restore registers from the process stack.
- * Bit[1] - 0 --> Reserved, 0.
- * Bit[0] - 1 --> The exception was taken to the Secure state.
- */
+    /**
+     * @brief Initial EXC_RETURN value.
+     *
+     *     FF         FF         FF         FD
+     * 1111 1111  1111 1111  1111 1111  1111 1101
+     *
+     * Bit[6] - 1 --> The exception was taken from the Secure state.
+     * Bit[5] - 1 --> Do not skip stacking of additional state context.
+     * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+     * Bit[3] - 1 --> Return to the Thread mode.
+     * Bit[2] - 1 --> Restore registers from the process stack.
+     * Bit[1] - 0 --> Reserved, 0.
+     * Bit[0] - 1 --> The exception was taken to the Secure state.
+     */
     #define portINITIAL_EXC_RETURN    ( 0xfffffffd )
 #else
 
-/**
- * @brief Initial EXC_RETURN value.
- *
- *     FF         FF         FF         BC
- * 1111 1111  1111 1111  1111 1111  1011 1100
- *
- * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
- * Bit[5] - 1 --> Do not skip stacking of additional state context.
- * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
- * Bit[3] - 1 --> Return to the Thread mode.
- * Bit[2] - 1 --> Restore registers from the process stack.
- * Bit[1] - 0 --> Reserved, 0.
- * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
- */
+    /**
+     * @brief Initial EXC_RETURN value.
+     *
+     *     FF         FF         FF         BC
+     * 1111 1111  1111 1111  1111 1111  1011 1100
+     *
+     * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+     * Bit[5] - 1 --> Do not skip stacking of additional state context.
+     * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+     * Bit[3] - 1 --> Return to the Thread mode.
+     * Bit[2] - 1 --> Restore registers from the process stack.
+     * Bit[1] - 0 --> Reserved, 0.
+     * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+     */
     #define portINITIAL_EXC_RETURN    ( 0xffffffbc )
 #endif /* configRUN_FREERTOS_SECURE_ONLY */
 
@@ -401,49 +398,49 @@ static void prvTaskExitError( void );
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Extract MPU region's access permissions from the Region Base Address
- * Register (RBAR) value.
- *
- * @param ulRBARValue RBAR value for the MPU region.
- *
- * @return uint32_t Access permissions.
- */
+    /**
+     * @brief Extract MPU region's access permissions from the Region Base Address
+     * Register (RBAR) value.
+     *
+     * @param ulRBARValue RBAR value for the MPU region.
+     *
+     * @return uint32_t Access permissions.
+     */
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Setup the Memory Protection Unit (MPU).
- */
+    /**
+     * @brief Setup the Memory Protection Unit (MPU).
+     */
     static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_MPU */
 
 #if ( configENABLE_FPU == 1 )
 
-/**
- * @brief Setup the Floating Point Unit (FPU).
- */
+    /**
+     * @brief Setup the Floating Point Unit (FPU).
+     */
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
 #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
-/**
- * @brief Configures PACBTI features.
- *
- * This function configures the Pointer Authentication, and Branch Target
- * Identification security features as per the user configuration. It returns
- * the value of the special purpose CONTROL register accordingly, and optionally
- * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
- * architecture based) target supports PACBTI security feature.
- *
- * @param xWriteControlRegister Used to control whether the special purpose
- * CONTROL register should be updated or not.
- *
- * @return CONTROL register value according to the configured PACBTI option.
- */
+    /**
+     * @brief Configures PACBTI features.
+     *
+     * This function configures the Pointer Authentication, and Branch Target
+     * Identification security features as per the user configuration. It returns
+     * the value of the special purpose CONTROL register accordingly, and optionally
+     * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
+     * architecture based) target supports PACBTI security feature.
+     *
+     * @param xWriteControlRegister Used to control whether the special purpose
+     * CONTROL register should be updated or not.
+     *
+     * @return CONTROL register value according to the configured PACBTI option.
+     */
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
 
 #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
@@ -491,14 +488,14 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Sets up the system call stack so that upon returning from
- * SVC, the system call stack is used.
- *
- * @param pulTaskStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
- * @param ucSystemCallNumber The system call number of the system call.
- */
+    /**
+     * @brief Sets up the system call stack so that upon returning from
+     * SVC, the system call stack is used.
+     *
+     * @param pulTaskStack The current SP when the SVC was raised.
+     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+     * @param ucSystemCallNumber The system call number of the system call.
+     */
     void vSystemCallEnter( uint32_t * pulTaskStack,
                            uint32_t ulLR,
                            uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION;
@@ -507,22 +504,22 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Raise SVC for exiting from a system call.
- */
+    /**
+     * @brief Raise SVC for exiting from a system call.
+     */
     void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Sets up the task stack so that upon returning from
- * SVC, the task stack is used again.
- *
- * @param pulSystemCallStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
- */
+    /**
+     * @brief Sets up the task stack so that upon returning from
+     * SVC, the task stack is used again.
+     *
+     * @param pulSystemCallStack The current SP when the SVC was raised.
+     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+     */
     void vSystemCallExit( uint32_t * pulSystemCallStack,
                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
@@ -530,11 +527,11 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Checks whether or not the calling task is privileged.
- *
- * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
- */
+    /**
+     * @brief Checks whether or not the calling task is privileged.
+     *
+     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+     */
     BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
 
 #endif /* configENABLE_MPU == 1 */
@@ -542,9 +539,9 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief This variable is set to pdTRUE when the scheduler is started.
- */
+    /**
+     * @brief This variable is set to pdTRUE when the scheduler is started.
+     */
     PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@@ -557,10 +554,10 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-/**
- * @brief Saved as part of the task context to indicate which context the
- * task is using on the secure side.
- */
+    /**
+     * @brief Saved as part of the task context to indicate which context the
+     * task is using on the secure side.
+     */
     PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
 #endif /* configENABLE_TRUSTZONE */
 
@@ -579,21 +576,21 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
 
-/**
- * @brief The number of SysTick increments that make up one tick period.
- */
+    /**
+     * @brief The number of SysTick increments that make up one tick period.
+     */
     PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0;
 
-/**
- * @brief The maximum number of tick periods that can be suppressed is
- * limited by the 24 bit resolution of the SysTick timer.
- */
+    /**
+     * @brief The maximum number of tick periods that can be suppressed is
+     * limited by the 24 bit resolution of the SysTick timer.
+     */
     PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0;
 
-/**
- * @brief Compensate for the CPU cycles that pass while the SysTick is
- * stopped (low power functionality only).
- */
+    /**
+     * @brief Compensate for the CPU cycles that pass while the SysTick is
+     * stopped (low power functionality only).
+     */
     PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0;
 #endif /* configUSE_TICKLESS_IDLE */
 /*-----------------------------------------------------------*/
@@ -925,64 +922,57 @@ static void prvTaskExitError( void )
         /* The only permitted number of regions are 8 or 16. */
         configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
 
-        /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
-        configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
+        /* MAIR0 - Index 0. */
+        portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+        /* MAIR0 - Index 1. */
+        portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
 
-        /* Check that the MPU is present. */
-        if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
-        {
-            /* MAIR0 - Index 0. */
-            portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
-            /* MAIR0 - Index 1. */
-            portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+        /* Setup privileged flash as Read Only so that privileged tasks can
+         * read it but not modify. */
+        portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_PRIVILEGED_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup privileged flash as Read Only so that privileged tasks can
-             * read it but not modify. */
-            portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_PRIVILEGED_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup unprivileged flash as Read Only by both privileged and
+         * unprivileged tasks. All tasks can read it but no-one can modify. */
+        portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup unprivileged flash as Read Only by both privileged and
-             * unprivileged tasks. All tasks can read it but no-one can modify. */
-            portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup unprivileged syscalls flash as Read Only by both privileged
+         * and unprivileged tasks. All tasks can read it but no-one can modify. */
+        portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup unprivileged syscalls flash as Read Only by both privileged
-             * and unprivileged tasks. All tasks can read it but no-one can modify. */
-            portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup RAM containing kernel data for privileged access only. */
+        portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+                           ( portMPU_REGION_EXECUTE_NEVER );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup RAM containing kernel data for privileged access only. */
-            portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
-                               ( portMPU_REGION_EXECUTE_NEVER );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Enable mem fault. */
+        portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;
 
-            /* Enable mem fault. */
-            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;
-
-            /* Enable MPU with privileged background access i.e. unmapped
-             * regions have privileged access. */
-            portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
-        }
+        /* Enable MPU with privileged background access i.e. unmapped
+         * regions have privileged access. */
+        portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
     }
 
 #endif /* configENABLE_MPU */
@@ -1108,47 +1098,47 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
     switch( ucSVCNumber )
     {
-        #if ( configENABLE_TRUSTZONE == 1 )
-            case portSVC_ALLOCATE_SECURE_CONTEXT:
+    #if ( configENABLE_TRUSTZONE == 1 )
+        case portSVC_ALLOCATE_SECURE_CONTEXT:
 
-                /* R0 contains the stack size passed as parameter to the
-                 * vPortAllocateSecureContext function. */
-                ulR0 = pulCallerStackAddress[ 0 ];
+            /* R0 contains the stack size passed as parameter to the
+             * vPortAllocateSecureContext function. */
+            ulR0 = pulCallerStackAddress[ 0 ];
 
-                #if ( configENABLE_MPU == 1 )
-                {
-                    /* Read the CONTROL register value. */
-                    __asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
+            #if ( configENABLE_MPU == 1 )
+            {
+                /* Read the CONTROL register value. */
+                __asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
 
-                    /* The task that raised the SVC is privileged if Bit[0]
-                     * in the CONTROL register is 0. */
-                    ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+                /* The task that raised the SVC is privileged if Bit[0]
+                 * in the CONTROL register is 0. */
+                ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
 
-                    /* Allocate and load a context for the secure task. */
-                    xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
-                }
-                #else /* if ( configENABLE_MPU == 1 ) */
-                {
-                    /* Allocate and load a context for the secure task. */
-                    xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
-                }
-                #endif /* configENABLE_MPU */
+                /* Allocate and load a context for the secure task. */
+                xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
+            }
+            #else /* if ( configENABLE_MPU == 1 ) */
+            {
+                /* Allocate and load a context for the secure task. */
+                xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
+            }
+            #endif /* configENABLE_MPU */
 
-                configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );
-                SecureContext_LoadContext( xSecureContext, pxCurrentTCB );
-                break;
+            configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );
+            SecureContext_LoadContext( xSecureContext, pxCurrentTCB );
+            break;
 
-            case portSVC_FREE_SECURE_CONTEXT:
+        case portSVC_FREE_SECURE_CONTEXT:
 
-                /* R0 contains TCB being freed and R1 contains the secure
-                 * context handle to be freed. */
-                ulR0 = pulCallerStackAddress[ 0 ];
-                ulR1 = pulCallerStackAddress[ 1 ];
+            /* R0 contains TCB being freed and R1 contains the secure
+             * context handle to be freed. */
+            ulR0 = pulCallerStackAddress[ 0 ];
+            ulR1 = pulCallerStackAddress[ 1 ];
 
-                /* Free the secure context. */
-                SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );
-                break;
-        #endif /* configENABLE_TRUSTZONE */
+            /* Free the secure context. */
+            SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );
+            break;
+    #endif /* configENABLE_TRUSTZONE */
 
         case portSVC_START_SCHEDULER:
             #if ( configENABLE_TRUSTZONE == 1 )
@@ -1174,24 +1164,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             vRestoreContextOfFirstTask();
             break;
 
-            #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
-                case portSVC_RAISE_PRIVILEGE:
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+        case portSVC_RAISE_PRIVILEGE:
 
-                    /* Only raise the privilege, if the svc was raised from any of
-                     * the system calls. */
-                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
-                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
-                    {
-                        vRaisePrivilege();
-                    }
-                    break;
-            #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+            /* Only raise the privilege, if the svc was raised from any of
+             * the system calls. */
+            if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+                ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+            {
+                vRaisePrivilege();
+            }
+            break;
+    #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
-            #if ( configENABLE_MPU == 1 )
-                case portSVC_YIELD:
-                    vPortYield();
-                    break;
-            #endif /* configENABLE_MPU == 1 */
+    #if ( configENABLE_MPU == 1 )
+        case portSVC_YIELD:
+            vPortYield();
+            break;
+    #endif /* configENABLE_MPU == 1 */
 
         default:
             /* Incorrect SVC call. */
@@ -1518,21 +1508,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
         ulIndex++;
 
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters;            /* r0. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x01010101;                           /* r1. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x02020202;                           /* r2. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x03030303;                           /* r3. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x12121212;                           /* r12. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
         ulIndex++;
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode;                  /* PC. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR;                     /* xPSR. */
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
         ulIndex++;
 
         #if ( configENABLE_TRUSTZONE == 1 )
@@ -1543,7 +1533,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         #endif /* configENABLE_TRUSTZONE */
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
         ulIndex++;
 
         #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
@@ -1615,15 +1605,15 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
          * interrupt. */
         #if ( portPRELOAD_REGISTERS == 0 )
         {
-            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
+            pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-            pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
-            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-            pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
+            pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
+            *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */
+            pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */
             *pxTopOfStack = portINITIAL_EXC_RETURN;
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
@@ -1637,42 +1627,42 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #else /* portPRELOAD_REGISTERS */
         {
-            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
+            pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
+            *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
+            *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
+            *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
+            *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
+            *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
+            *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
+            *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
+            *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
+            *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
+            *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
+            *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
+            *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04. */
             pxTopOfStack--;
-            *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
+            *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxEndOfStack;            /* Slot used to hold this task's PSPLIM value. */
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
 
             #if ( configENABLE_TRUSTZONE == 1 )
             {
diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
index b2fd7e518..a7fb054bc 100644
--- a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
@@ -145,13 +145,13 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the FPU.
  */
-#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 )              /* Coprocessor Access Control Register. */
+#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */
 #define portCPACR_CP10_VALUE    ( 3UL )
 #define portCPACR_CP11_VALUE    portCPACR_CP10_VALUE
 #define portCPACR_CP10_POS      ( 20UL )
 #define portCPACR_CP11_POS      ( 22UL )
 
-#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 )              /* Floating Point Context Control Register. */
+#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */
 #define portFPCCR_ASPEN_POS     ( 31UL )
 #define portFPCCR_ASPEN_MASK    ( 1UL << portFPCCR_ASPEN_POS )
 #define portFPCCR_LSPEN_POS     ( 30UL )
@@ -188,8 +188,8 @@ typedef void ( * portISR_t )( void );
 #define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
 #define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
 #define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
@@ -230,8 +230,8 @@ typedef void ( * portISR_t )( void );
 
 #if ( portARMV8M_MINOR_VERSION >= 1 )
 
-/* Enable Privileged eXecute Never MPU attribute for the selected memory
- * region. */
+    /* Enable Privileged eXecute Never MPU attribute for the selected memory
+     * region. */
     #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER    ( 1UL << 4UL )
 #endif /* portARMV8M_MINOR_VERSION >= 1 */
 
@@ -241,9 +241,6 @@ typedef void ( * portISR_t )( void );
 /* Enable MPU. */
 #define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
 
-/* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
-
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
 #define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \
@@ -291,37 +288,37 @@ typedef void ( * portISR_t )( void );
 
 #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
 
-/**
- * @brief Initial EXC_RETURN value.
- *
- *     FF         FF         FF         FD
- * 1111 1111  1111 1111  1111 1111  1111 1101
- *
- * Bit[6] - 1 --> The exception was taken from the Secure state.
- * Bit[5] - 1 --> Do not skip stacking of additional state context.
- * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
- * Bit[3] - 1 --> Return to the Thread mode.
- * Bit[2] - 1 --> Restore registers from the process stack.
- * Bit[1] - 0 --> Reserved, 0.
- * Bit[0] - 1 --> The exception was taken to the Secure state.
- */
+    /**
+     * @brief Initial EXC_RETURN value.
+     *
+     *     FF         FF         FF         FD
+     * 1111 1111  1111 1111  1111 1111  1111 1101
+     *
+     * Bit[6] - 1 --> The exception was taken from the Secure state.
+     * Bit[5] - 1 --> Do not skip stacking of additional state context.
+     * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+     * Bit[3] - 1 --> Return to the Thread mode.
+     * Bit[2] - 1 --> Restore registers from the process stack.
+     * Bit[1] - 0 --> Reserved, 0.
+     * Bit[0] - 1 --> The exception was taken to the Secure state.
+     */
     #define portINITIAL_EXC_RETURN    ( 0xfffffffd )
 #else
 
-/**
- * @brief Initial EXC_RETURN value.
- *
- *     FF         FF         FF         BC
- * 1111 1111  1111 1111  1111 1111  1011 1100
- *
- * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
- * Bit[5] - 1 --> Do not skip stacking of additional state context.
- * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
- * Bit[3] - 1 --> Return to the Thread mode.
- * Bit[2] - 1 --> Restore registers from the process stack.
- * Bit[1] - 0 --> Reserved, 0.
- * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
- */
+    /**
+     * @brief Initial EXC_RETURN value.
+     *
+     *     FF         FF         FF         BC
+     * 1111 1111  1111 1111  1111 1111  1011 1100
+     *
+     * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+     * Bit[5] - 1 --> Do not skip stacking of additional state context.
+     * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+     * Bit[3] - 1 --> Return to the Thread mode.
+     * Bit[2] - 1 --> Restore registers from the process stack.
+     * Bit[1] - 0 --> Reserved, 0.
+     * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+     */
     #define portINITIAL_EXC_RETURN    ( 0xffffffbc )
 #endif /* configRUN_FREERTOS_SECURE_ONLY */
 
@@ -401,49 +398,49 @@ static void prvTaskExitError( void );
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Extract MPU region's access permissions from the Region Base Address
- * Register (RBAR) value.
- *
- * @param ulRBARValue RBAR value for the MPU region.
- *
- * @return uint32_t Access permissions.
- */
+    /**
+     * @brief Extract MPU region's access permissions from the Region Base Address
+     * Register (RBAR) value.
+     *
+     * @param ulRBARValue RBAR value for the MPU region.
+     *
+     * @return uint32_t Access permissions.
+     */
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Setup the Memory Protection Unit (MPU).
- */
+    /**
+     * @brief Setup the Memory Protection Unit (MPU).
+     */
     static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_MPU */
 
 #if ( configENABLE_FPU == 1 )
 
-/**
- * @brief Setup the Floating Point Unit (FPU).
- */
+    /**
+     * @brief Setup the Floating Point Unit (FPU).
+     */
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
 #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
-/**
- * @brief Configures PACBTI features.
- *
- * This function configures the Pointer Authentication, and Branch Target
- * Identification security features as per the user configuration. It returns
- * the value of the special purpose CONTROL register accordingly, and optionally
- * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
- * architecture based) target supports PACBTI security feature.
- *
- * @param xWriteControlRegister Used to control whether the special purpose
- * CONTROL register should be updated or not.
- *
- * @return CONTROL register value according to the configured PACBTI option.
- */
+    /**
+     * @brief Configures PACBTI features.
+     *
+     * This function configures the Pointer Authentication, and Branch Target
+     * Identification security features as per the user configuration. It returns
+     * the value of the special purpose CONTROL register accordingly, and optionally
+     * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
+     * architecture based) target supports PACBTI security feature.
+     *
+     * @param xWriteControlRegister Used to control whether the special purpose
+     * CONTROL register should be updated or not.
+     *
+     * @return CONTROL register value according to the configured PACBTI option.
+     */
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
 
 #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
@@ -491,14 +488,14 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Sets up the system call stack so that upon returning from
- * SVC, the system call stack is used.
- *
- * @param pulTaskStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
- * @param ucSystemCallNumber The system call number of the system call.
- */
+    /**
+     * @brief Sets up the system call stack so that upon returning from
+     * SVC, the system call stack is used.
+     *
+     * @param pulTaskStack The current SP when the SVC was raised.
+     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+     * @param ucSystemCallNumber The system call number of the system call.
+     */
     void vSystemCallEnter( uint32_t * pulTaskStack,
                            uint32_t ulLR,
                            uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION;
@@ -507,22 +504,22 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Raise SVC for exiting from a system call.
- */
+    /**
+     * @brief Raise SVC for exiting from a system call.
+     */
     void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Sets up the task stack so that upon returning from
- * SVC, the task stack is used again.
- *
- * @param pulSystemCallStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
- */
+    /**
+     * @brief Sets up the task stack so that upon returning from
+     * SVC, the task stack is used again.
+     *
+     * @param pulSystemCallStack The current SP when the SVC was raised.
+     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+     */
     void vSystemCallExit( uint32_t * pulSystemCallStack,
                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
@@ -530,11 +527,11 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Checks whether or not the calling task is privileged.
- *
- * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
- */
+    /**
+     * @brief Checks whether or not the calling task is privileged.
+     *
+     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+     */
     BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
 
 #endif /* configENABLE_MPU == 1 */
@@ -542,9 +539,9 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief This variable is set to pdTRUE when the scheduler is started.
- */
+    /**
+     * @brief This variable is set to pdTRUE when the scheduler is started.
+     */
     PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@@ -557,10 +554,10 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-/**
- * @brief Saved as part of the task context to indicate which context the
- * task is using on the secure side.
- */
+    /**
+     * @brief Saved as part of the task context to indicate which context the
+     * task is using on the secure side.
+     */
     PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
 #endif /* configENABLE_TRUSTZONE */
 
@@ -579,21 +576,21 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
 
-/**
- * @brief The number of SysTick increments that make up one tick period.
- */
+    /**
+     * @brief The number of SysTick increments that make up one tick period.
+     */
     PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0;
 
-/**
- * @brief The maximum number of tick periods that can be suppressed is
- * limited by the 24 bit resolution of the SysTick timer.
- */
+    /**
+     * @brief The maximum number of tick periods that can be suppressed is
+     * limited by the 24 bit resolution of the SysTick timer.
+     */
     PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0;
 
-/**
- * @brief Compensate for the CPU cycles that pass while the SysTick is
- * stopped (low power functionality only).
- */
+    /**
+     * @brief Compensate for the CPU cycles that pass while the SysTick is
+     * stopped (low power functionality only).
+     */
     PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0;
 #endif /* configUSE_TICKLESS_IDLE */
 /*-----------------------------------------------------------*/
@@ -925,64 +922,57 @@ static void prvTaskExitError( void )
         /* The only permitted number of regions are 8 or 16. */
         configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
 
-        /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
-        configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
+        /* MAIR0 - Index 0. */
+        portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+        /* MAIR0 - Index 1. */
+        portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
 
-        /* Check that the MPU is present. */
-        if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
-        {
-            /* MAIR0 - Index 0. */
-            portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
-            /* MAIR0 - Index 1. */
-            portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+        /* Setup privileged flash as Read Only so that privileged tasks can
+         * read it but not modify. */
+        portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_PRIVILEGED_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup privileged flash as Read Only so that privileged tasks can
-             * read it but not modify. */
-            portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_PRIVILEGED_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup unprivileged flash as Read Only by both privileged and
+         * unprivileged tasks. All tasks can read it but no-one can modify. */
+        portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup unprivileged flash as Read Only by both privileged and
-             * unprivileged tasks. All tasks can read it but no-one can modify. */
-            portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup unprivileged syscalls flash as Read Only by both privileged
+         * and unprivileged tasks. All tasks can read it but no-one can modify. */
+        portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup unprivileged syscalls flash as Read Only by both privileged
-             * and unprivileged tasks. All tasks can read it but no-one can modify. */
-            portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup RAM containing kernel data for privileged access only. */
+        portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+                           ( portMPU_REGION_EXECUTE_NEVER );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup RAM containing kernel data for privileged access only. */
-            portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
-                               ( portMPU_REGION_EXECUTE_NEVER );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Enable mem fault. */
+        portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;
 
-            /* Enable mem fault. */
-            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;
-
-            /* Enable MPU with privileged background access i.e. unmapped
-             * regions have privileged access. */
-            portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
-        }
+        /* Enable MPU with privileged background access i.e. unmapped
+         * regions have privileged access. */
+        portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
     }
 
 #endif /* configENABLE_MPU */
@@ -1108,47 +1098,47 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
     switch( ucSVCNumber )
     {
-        #if ( configENABLE_TRUSTZONE == 1 )
-            case portSVC_ALLOCATE_SECURE_CONTEXT:
+    #if ( configENABLE_TRUSTZONE == 1 )
+        case portSVC_ALLOCATE_SECURE_CONTEXT:
 
-                /* R0 contains the stack size passed as parameter to the
-                 * vPortAllocateSecureContext function. */
-                ulR0 = pulCallerStackAddress[ 0 ];
+            /* R0 contains the stack size passed as parameter to the
+             * vPortAllocateSecureContext function. */
+            ulR0 = pulCallerStackAddress[ 0 ];
 
-                #if ( configENABLE_MPU == 1 )
-                {
-                    /* Read the CONTROL register value. */
-                    __asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
+            #if ( configENABLE_MPU == 1 )
+            {
+                /* Read the CONTROL register value. */
+                __asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
 
-                    /* The task that raised the SVC is privileged if Bit[0]
-                     * in the CONTROL register is 0. */
-                    ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+                /* The task that raised the SVC is privileged if Bit[0]
+                 * in the CONTROL register is 0. */
+                ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
 
-                    /* Allocate and load a context for the secure task. */
-                    xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
-                }
-                #else /* if ( configENABLE_MPU == 1 ) */
-                {
-                    /* Allocate and load a context for the secure task. */
-                    xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
-                }
-                #endif /* configENABLE_MPU */
+                /* Allocate and load a context for the secure task. */
+                xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
+            }
+            #else /* if ( configENABLE_MPU == 1 ) */
+            {
+                /* Allocate and load a context for the secure task. */
+                xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
+            }
+            #endif /* configENABLE_MPU */
 
-                configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );
-                SecureContext_LoadContext( xSecureContext, pxCurrentTCB );
-                break;
+            configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );
+            SecureContext_LoadContext( xSecureContext, pxCurrentTCB );
+            break;
 
-            case portSVC_FREE_SECURE_CONTEXT:
+        case portSVC_FREE_SECURE_CONTEXT:
 
-                /* R0 contains TCB being freed and R1 contains the secure
-                 * context handle to be freed. */
-                ulR0 = pulCallerStackAddress[ 0 ];
-                ulR1 = pulCallerStackAddress[ 1 ];
+            /* R0 contains TCB being freed and R1 contains the secure
+             * context handle to be freed. */
+            ulR0 = pulCallerStackAddress[ 0 ];
+            ulR1 = pulCallerStackAddress[ 1 ];
 
-                /* Free the secure context. */
-                SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );
-                break;
-        #endif /* configENABLE_TRUSTZONE */
+            /* Free the secure context. */
+            SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );
+            break;
+    #endif /* configENABLE_TRUSTZONE */
 
         case portSVC_START_SCHEDULER:
             #if ( configENABLE_TRUSTZONE == 1 )
@@ -1174,24 +1164,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             vRestoreContextOfFirstTask();
             break;
 
-            #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
-                case portSVC_RAISE_PRIVILEGE:
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+        case portSVC_RAISE_PRIVILEGE:
 
-                    /* Only raise the privilege, if the svc was raised from any of
-                     * the system calls. */
-                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
-                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
-                    {
-                        vRaisePrivilege();
-                    }
-                    break;
-            #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+            /* Only raise the privilege, if the svc was raised from any of
+             * the system calls. */
+            if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+                ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+            {
+                vRaisePrivilege();
+            }
+            break;
+    #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
-            #if ( configENABLE_MPU == 1 )
-                case portSVC_YIELD:
-                    vPortYield();
-                    break;
-            #endif /* configENABLE_MPU == 1 */
+    #if ( configENABLE_MPU == 1 )
+        case portSVC_YIELD:
+            vPortYield();
+            break;
+    #endif /* configENABLE_MPU == 1 */
 
         default:
             /* Incorrect SVC call. */
@@ -1518,21 +1508,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
         ulIndex++;
 
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters;            /* r0. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x01010101;                           /* r1. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x02020202;                           /* r2. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x03030303;                           /* r3. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x12121212;                           /* r12. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
         ulIndex++;
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode;                  /* PC. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR;                     /* xPSR. */
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
         ulIndex++;
 
         #if ( configENABLE_TRUSTZONE == 1 )
@@ -1543,7 +1533,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         #endif /* configENABLE_TRUSTZONE */
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
         ulIndex++;
 
         #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
@@ -1615,15 +1605,15 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
          * interrupt. */
         #if ( portPRELOAD_REGISTERS == 0 )
         {
-            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
+            pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-            pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
-            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-            pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
+            pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
+            *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */
+            pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */
             *pxTopOfStack = portINITIAL_EXC_RETURN;
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
@@ -1637,42 +1627,42 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #else /* portPRELOAD_REGISTERS */
         {
-            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
+            pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
+            *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
+            *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
+            *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
+            *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
+            *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
+            *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
+            *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
+            *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
+            *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
+            *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
+            *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
+            *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04. */
             pxTopOfStack--;
-            *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
+            *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxEndOfStack;            /* Slot used to hold this task's PSPLIM value. */
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
 
             #if ( configENABLE_TRUSTZONE == 1 )
             {
diff --git a/portable/IAR/ARM_CM33/non_secure/port.c b/portable/IAR/ARM_CM33/non_secure/port.c
index b2fd7e518..a7fb054bc 100644
--- a/portable/IAR/ARM_CM33/non_secure/port.c
+++ b/portable/IAR/ARM_CM33/non_secure/port.c
@@ -145,13 +145,13 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the FPU.
  */
-#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 )              /* Coprocessor Access Control Register. */
+#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */
 #define portCPACR_CP10_VALUE    ( 3UL )
 #define portCPACR_CP11_VALUE    portCPACR_CP10_VALUE
 #define portCPACR_CP10_POS      ( 20UL )
 #define portCPACR_CP11_POS      ( 22UL )
 
-#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 )              /* Floating Point Context Control Register. */
+#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */
 #define portFPCCR_ASPEN_POS     ( 31UL )
 #define portFPCCR_ASPEN_MASK    ( 1UL << portFPCCR_ASPEN_POS )
 #define portFPCCR_LSPEN_POS     ( 30UL )
@@ -188,8 +188,8 @@ typedef void ( * portISR_t )( void );
 #define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
 #define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
 #define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
@@ -230,8 +230,8 @@ typedef void ( * portISR_t )( void );
 
 #if ( portARMV8M_MINOR_VERSION >= 1 )
 
-/* Enable Privileged eXecute Never MPU attribute for the selected memory
- * region. */
+    /* Enable Privileged eXecute Never MPU attribute for the selected memory
+     * region. */
     #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER    ( 1UL << 4UL )
 #endif /* portARMV8M_MINOR_VERSION >= 1 */
 
@@ -241,9 +241,6 @@ typedef void ( * portISR_t )( void );
 /* Enable MPU. */
 #define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
 
-/* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
-
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
 #define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \
@@ -291,37 +288,37 @@ typedef void ( * portISR_t )( void );
 
 #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
 
-/**
- * @brief Initial EXC_RETURN value.
- *
- *     FF         FF         FF         FD
- * 1111 1111  1111 1111  1111 1111  1111 1101
- *
- * Bit[6] - 1 --> The exception was taken from the Secure state.
- * Bit[5] - 1 --> Do not skip stacking of additional state context.
- * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
- * Bit[3] - 1 --> Return to the Thread mode.
- * Bit[2] - 1 --> Restore registers from the process stack.
- * Bit[1] - 0 --> Reserved, 0.
- * Bit[0] - 1 --> The exception was taken to the Secure state.
- */
+    /**
+     * @brief Initial EXC_RETURN value.
+     *
+     *     FF         FF         FF         FD
+     * 1111 1111  1111 1111  1111 1111  1111 1101
+     *
+     * Bit[6] - 1 --> The exception was taken from the Secure state.
+     * Bit[5] - 1 --> Do not skip stacking of additional state context.
+     * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+     * Bit[3] - 1 --> Return to the Thread mode.
+     * Bit[2] - 1 --> Restore registers from the process stack.
+     * Bit[1] - 0 --> Reserved, 0.
+     * Bit[0] - 1 --> The exception was taken to the Secure state.
+     */
     #define portINITIAL_EXC_RETURN    ( 0xfffffffd )
 #else
 
-/**
- * @brief Initial EXC_RETURN value.
- *
- *     FF         FF         FF         BC
- * 1111 1111  1111 1111  1111 1111  1011 1100
- *
- * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
- * Bit[5] - 1 --> Do not skip stacking of additional state context.
- * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
- * Bit[3] - 1 --> Return to the Thread mode.
- * Bit[2] - 1 --> Restore registers from the process stack.
- * Bit[1] - 0 --> Reserved, 0.
- * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
- */
+    /**
+     * @brief Initial EXC_RETURN value.
+     *
+     *     FF         FF         FF         BC
+     * 1111 1111  1111 1111  1111 1111  1011 1100
+     *
+     * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+     * Bit[5] - 1 --> Do not skip stacking of additional state context.
+     * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+     * Bit[3] - 1 --> Return to the Thread mode.
+     * Bit[2] - 1 --> Restore registers from the process stack.
+     * Bit[1] - 0 --> Reserved, 0.
+     * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+     */
     #define portINITIAL_EXC_RETURN    ( 0xffffffbc )
 #endif /* configRUN_FREERTOS_SECURE_ONLY */
 
@@ -401,49 +398,49 @@ static void prvTaskExitError( void );
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Extract MPU region's access permissions from the Region Base Address
- * Register (RBAR) value.
- *
- * @param ulRBARValue RBAR value for the MPU region.
- *
- * @return uint32_t Access permissions.
- */
+    /**
+     * @brief Extract MPU region's access permissions from the Region Base Address
+     * Register (RBAR) value.
+     *
+     * @param ulRBARValue RBAR value for the MPU region.
+     *
+     * @return uint32_t Access permissions.
+     */
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Setup the Memory Protection Unit (MPU).
- */
+    /**
+     * @brief Setup the Memory Protection Unit (MPU).
+     */
     static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_MPU */
 
 #if ( configENABLE_FPU == 1 )
 
-/**
- * @brief Setup the Floating Point Unit (FPU).
- */
+    /**
+     * @brief Setup the Floating Point Unit (FPU).
+     */
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
 #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
-/**
- * @brief Configures PACBTI features.
- *
- * This function configures the Pointer Authentication, and Branch Target
- * Identification security features as per the user configuration. It returns
- * the value of the special purpose CONTROL register accordingly, and optionally
- * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
- * architecture based) target supports PACBTI security feature.
- *
- * @param xWriteControlRegister Used to control whether the special purpose
- * CONTROL register should be updated or not.
- *
- * @return CONTROL register value according to the configured PACBTI option.
- */
+    /**
+     * @brief Configures PACBTI features.
+     *
+     * This function configures the Pointer Authentication, and Branch Target
+     * Identification security features as per the user configuration. It returns
+     * the value of the special purpose CONTROL register accordingly, and optionally
+     * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
+     * architecture based) target supports PACBTI security feature.
+     *
+     * @param xWriteControlRegister Used to control whether the special purpose
+     * CONTROL register should be updated or not.
+     *
+     * @return CONTROL register value according to the configured PACBTI option.
+     */
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
 
 #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
@@ -491,14 +488,14 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Sets up the system call stack so that upon returning from
- * SVC, the system call stack is used.
- *
- * @param pulTaskStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
- * @param ucSystemCallNumber The system call number of the system call.
- */
+    /**
+     * @brief Sets up the system call stack so that upon returning from
+     * SVC, the system call stack is used.
+     *
+     * @param pulTaskStack The current SP when the SVC was raised.
+     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+     * @param ucSystemCallNumber The system call number of the system call.
+     */
     void vSystemCallEnter( uint32_t * pulTaskStack,
                            uint32_t ulLR,
                            uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION;
@@ -507,22 +504,22 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Raise SVC for exiting from a system call.
- */
+    /**
+     * @brief Raise SVC for exiting from a system call.
+     */
     void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Sets up the task stack so that upon returning from
- * SVC, the task stack is used again.
- *
- * @param pulSystemCallStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
- */
+    /**
+     * @brief Sets up the task stack so that upon returning from
+     * SVC, the task stack is used again.
+     *
+     * @param pulSystemCallStack The current SP when the SVC was raised.
+     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+     */
     void vSystemCallExit( uint32_t * pulSystemCallStack,
                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
@@ -530,11 +527,11 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Checks whether or not the calling task is privileged.
- *
- * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
- */
+    /**
+     * @brief Checks whether or not the calling task is privileged.
+     *
+     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+     */
     BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
 
 #endif /* configENABLE_MPU == 1 */
@@ -542,9 +539,9 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief This variable is set to pdTRUE when the scheduler is started.
- */
+    /**
+     * @brief This variable is set to pdTRUE when the scheduler is started.
+     */
     PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@@ -557,10 +554,10 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-/**
- * @brief Saved as part of the task context to indicate which context the
- * task is using on the secure side.
- */
+    /**
+     * @brief Saved as part of the task context to indicate which context the
+     * task is using on the secure side.
+     */
     PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
 #endif /* configENABLE_TRUSTZONE */
 
@@ -579,21 +576,21 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
 
-/**
- * @brief The number of SysTick increments that make up one tick period.
- */
+    /**
+     * @brief The number of SysTick increments that make up one tick period.
+     */
     PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0;
 
-/**
- * @brief The maximum number of tick periods that can be suppressed is
- * limited by the 24 bit resolution of the SysTick timer.
- */
+    /**
+     * @brief The maximum number of tick periods that can be suppressed is
+     * limited by the 24 bit resolution of the SysTick timer.
+     */
     PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0;
 
-/**
- * @brief Compensate for the CPU cycles that pass while the SysTick is
- * stopped (low power functionality only).
- */
+    /**
+     * @brief Compensate for the CPU cycles that pass while the SysTick is
+     * stopped (low power functionality only).
+     */
     PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0;
 #endif /* configUSE_TICKLESS_IDLE */
 /*-----------------------------------------------------------*/
@@ -925,64 +922,57 @@ static void prvTaskExitError( void )
         /* The only permitted number of regions are 8 or 16. */
         configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
 
-        /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
-        configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
+        /* MAIR0 - Index 0. */
+        portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+        /* MAIR0 - Index 1. */
+        portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
 
-        /* Check that the MPU is present. */
-        if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
-        {
-            /* MAIR0 - Index 0. */
-            portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
-            /* MAIR0 - Index 1. */
-            portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+        /* Setup privileged flash as Read Only so that privileged tasks can
+         * read it but not modify. */
+        portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_PRIVILEGED_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup privileged flash as Read Only so that privileged tasks can
-             * read it but not modify. */
-            portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_PRIVILEGED_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup unprivileged flash as Read Only by both privileged and
+         * unprivileged tasks. All tasks can read it but no-one can modify. */
+        portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup unprivileged flash as Read Only by both privileged and
-             * unprivileged tasks. All tasks can read it but no-one can modify. */
-            portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup unprivileged syscalls flash as Read Only by both privileged
+         * and unprivileged tasks. All tasks can read it but no-one can modify. */
+        portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup unprivileged syscalls flash as Read Only by both privileged
-             * and unprivileged tasks. All tasks can read it but no-one can modify. */
-            portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup RAM containing kernel data for privileged access only. */
+        portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+                           ( portMPU_REGION_EXECUTE_NEVER );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup RAM containing kernel data for privileged access only. */
-            portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
-                               ( portMPU_REGION_EXECUTE_NEVER );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Enable mem fault. */
+        portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;
 
-            /* Enable mem fault. */
-            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;
-
-            /* Enable MPU with privileged background access i.e. unmapped
-             * regions have privileged access. */
-            portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
-        }
+        /* Enable MPU with privileged background access i.e. unmapped
+         * regions have privileged access. */
+        portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
     }
 
 #endif /* configENABLE_MPU */
@@ -1108,47 +1098,47 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
     switch( ucSVCNumber )
     {
-        #if ( configENABLE_TRUSTZONE == 1 )
-            case portSVC_ALLOCATE_SECURE_CONTEXT:
+    #if ( configENABLE_TRUSTZONE == 1 )
+        case portSVC_ALLOCATE_SECURE_CONTEXT:
 
-                /* R0 contains the stack size passed as parameter to the
-                 * vPortAllocateSecureContext function. */
-                ulR0 = pulCallerStackAddress[ 0 ];
+            /* R0 contains the stack size passed as parameter to the
+             * vPortAllocateSecureContext function. */
+            ulR0 = pulCallerStackAddress[ 0 ];
 
-                #if ( configENABLE_MPU == 1 )
-                {
-                    /* Read the CONTROL register value. */
-                    __asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
+            #if ( configENABLE_MPU == 1 )
+            {
+                /* Read the CONTROL register value. */
+                __asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
 
-                    /* The task that raised the SVC is privileged if Bit[0]
-                     * in the CONTROL register is 0. */
-                    ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+                /* The task that raised the SVC is privileged if Bit[0]
+                 * in the CONTROL register is 0. */
+                ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
 
-                    /* Allocate and load a context for the secure task. */
-                    xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
-                }
-                #else /* if ( configENABLE_MPU == 1 ) */
-                {
-                    /* Allocate and load a context for the secure task. */
-                    xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
-                }
-                #endif /* configENABLE_MPU */
+                /* Allocate and load a context for the secure task. */
+                xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
+            }
+            #else /* if ( configENABLE_MPU == 1 ) */
+            {
+                /* Allocate and load a context for the secure task. */
+                xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
+            }
+            #endif /* configENABLE_MPU */
 
-                configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );
-                SecureContext_LoadContext( xSecureContext, pxCurrentTCB );
-                break;
+            configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );
+            SecureContext_LoadContext( xSecureContext, pxCurrentTCB );
+            break;
 
-            case portSVC_FREE_SECURE_CONTEXT:
+        case portSVC_FREE_SECURE_CONTEXT:
 
-                /* R0 contains TCB being freed and R1 contains the secure
-                 * context handle to be freed. */
-                ulR0 = pulCallerStackAddress[ 0 ];
-                ulR1 = pulCallerStackAddress[ 1 ];
+            /* R0 contains TCB being freed and R1 contains the secure
+             * context handle to be freed. */
+            ulR0 = pulCallerStackAddress[ 0 ];
+            ulR1 = pulCallerStackAddress[ 1 ];
 
-                /* Free the secure context. */
-                SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );
-                break;
-        #endif /* configENABLE_TRUSTZONE */
+            /* Free the secure context. */
+            SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );
+            break;
+    #endif /* configENABLE_TRUSTZONE */
 
         case portSVC_START_SCHEDULER:
             #if ( configENABLE_TRUSTZONE == 1 )
@@ -1174,24 +1164,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             vRestoreContextOfFirstTask();
             break;
 
-            #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
-                case portSVC_RAISE_PRIVILEGE:
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+        case portSVC_RAISE_PRIVILEGE:
 
-                    /* Only raise the privilege, if the svc was raised from any of
-                     * the system calls. */
-                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
-                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
-                    {
-                        vRaisePrivilege();
-                    }
-                    break;
-            #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+            /* Only raise the privilege, if the svc was raised from any of
+             * the system calls. */
+            if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+                ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+            {
+                vRaisePrivilege();
+            }
+            break;
+    #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
-            #if ( configENABLE_MPU == 1 )
-                case portSVC_YIELD:
-                    vPortYield();
-                    break;
-            #endif /* configENABLE_MPU == 1 */
+    #if ( configENABLE_MPU == 1 )
+        case portSVC_YIELD:
+            vPortYield();
+            break;
+    #endif /* configENABLE_MPU == 1 */
 
         default:
             /* Incorrect SVC call. */
@@ -1518,21 +1508,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
         ulIndex++;
 
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters;            /* r0. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x01010101;                           /* r1. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x02020202;                           /* r2. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x03030303;                           /* r3. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x12121212;                           /* r12. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
         ulIndex++;
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode;                  /* PC. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR;                     /* xPSR. */
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
         ulIndex++;
 
         #if ( configENABLE_TRUSTZONE == 1 )
@@ -1543,7 +1533,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         #endif /* configENABLE_TRUSTZONE */
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
         ulIndex++;
 
         #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
@@ -1615,15 +1605,15 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
          * interrupt. */
         #if ( portPRELOAD_REGISTERS == 0 )
         {
-            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
+            pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-            pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
-            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-            pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
+            pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
+            *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */
+            pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */
             *pxTopOfStack = portINITIAL_EXC_RETURN;
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
@@ -1637,42 +1627,42 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #else /* portPRELOAD_REGISTERS */
         {
-            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
+            pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
+            *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
+            *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
+            *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
+            *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
+            *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
+            *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
+            *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
+            *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
+            *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
+            *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
+            *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
+            *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04. */
             pxTopOfStack--;
-            *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
+            *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxEndOfStack;            /* Slot used to hold this task's PSPLIM value. */
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
 
             #if ( configENABLE_TRUSTZONE == 1 )
             {
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
index b2fd7e518..a7fb054bc 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
@@ -145,13 +145,13 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the FPU.
  */
-#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 )              /* Coprocessor Access Control Register. */
+#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */
 #define portCPACR_CP10_VALUE    ( 3UL )
 #define portCPACR_CP11_VALUE    portCPACR_CP10_VALUE
 #define portCPACR_CP10_POS      ( 20UL )
 #define portCPACR_CP11_POS      ( 22UL )
 
-#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 )              /* Floating Point Context Control Register. */
+#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */
 #define portFPCCR_ASPEN_POS     ( 31UL )
 #define portFPCCR_ASPEN_MASK    ( 1UL << portFPCCR_ASPEN_POS )
 #define portFPCCR_LSPEN_POS     ( 30UL )
@@ -188,8 +188,8 @@ typedef void ( * portISR_t )( void );
 #define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
 #define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
 #define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
@@ -230,8 +230,8 @@ typedef void ( * portISR_t )( void );
 
 #if ( portARMV8M_MINOR_VERSION >= 1 )
 
-/* Enable Privileged eXecute Never MPU attribute for the selected memory
- * region. */
+    /* Enable Privileged eXecute Never MPU attribute for the selected memory
+     * region. */
     #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER    ( 1UL << 4UL )
 #endif /* portARMV8M_MINOR_VERSION >= 1 */
 
@@ -241,9 +241,6 @@ typedef void ( * portISR_t )( void );
 /* Enable MPU. */
 #define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
 
-/* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
-
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
 #define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \
@@ -291,37 +288,37 @@ typedef void ( * portISR_t )( void );
 
 #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
 
-/**
- * @brief Initial EXC_RETURN value.
- *
- *     FF         FF         FF         FD
- * 1111 1111  1111 1111  1111 1111  1111 1101
- *
- * Bit[6] - 1 --> The exception was taken from the Secure state.
- * Bit[5] - 1 --> Do not skip stacking of additional state context.
- * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
- * Bit[3] - 1 --> Return to the Thread mode.
- * Bit[2] - 1 --> Restore registers from the process stack.
- * Bit[1] - 0 --> Reserved, 0.
- * Bit[0] - 1 --> The exception was taken to the Secure state.
- */
+    /**
+     * @brief Initial EXC_RETURN value.
+     *
+     *     FF         FF         FF         FD
+     * 1111 1111  1111 1111  1111 1111  1111 1101
+     *
+     * Bit[6] - 1 --> The exception was taken from the Secure state.
+     * Bit[5] - 1 --> Do not skip stacking of additional state context.
+     * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+     * Bit[3] - 1 --> Return to the Thread mode.
+     * Bit[2] - 1 --> Restore registers from the process stack.
+     * Bit[1] - 0 --> Reserved, 0.
+     * Bit[0] - 1 --> The exception was taken to the Secure state.
+     */
     #define portINITIAL_EXC_RETURN    ( 0xfffffffd )
 #else
 
-/**
- * @brief Initial EXC_RETURN value.
- *
- *     FF         FF         FF         BC
- * 1111 1111  1111 1111  1111 1111  1011 1100
- *
- * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
- * Bit[5] - 1 --> Do not skip stacking of additional state context.
- * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
- * Bit[3] - 1 --> Return to the Thread mode.
- * Bit[2] - 1 --> Restore registers from the process stack.
- * Bit[1] - 0 --> Reserved, 0.
- * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
- */
+    /**
+     * @brief Initial EXC_RETURN value.
+     *
+     *     FF         FF         FF         BC
+     * 1111 1111  1111 1111  1111 1111  1011 1100
+     *
+     * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+     * Bit[5] - 1 --> Do not skip stacking of additional state context.
+     * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+     * Bit[3] - 1 --> Return to the Thread mode.
+     * Bit[2] - 1 --> Restore registers from the process stack.
+     * Bit[1] - 0 --> Reserved, 0.
+     * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+     */
     #define portINITIAL_EXC_RETURN    ( 0xffffffbc )
 #endif /* configRUN_FREERTOS_SECURE_ONLY */
 
@@ -401,49 +398,49 @@ static void prvTaskExitError( void );
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Extract MPU region's access permissions from the Region Base Address
- * Register (RBAR) value.
- *
- * @param ulRBARValue RBAR value for the MPU region.
- *
- * @return uint32_t Access permissions.
- */
+    /**
+     * @brief Extract MPU region's access permissions from the Region Base Address
+     * Register (RBAR) value.
+     *
+     * @param ulRBARValue RBAR value for the MPU region.
+     *
+     * @return uint32_t Access permissions.
+     */
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Setup the Memory Protection Unit (MPU).
- */
+    /**
+     * @brief Setup the Memory Protection Unit (MPU).
+     */
     static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_MPU */
 
 #if ( configENABLE_FPU == 1 )
 
-/**
- * @brief Setup the Floating Point Unit (FPU).
- */
+    /**
+     * @brief Setup the Floating Point Unit (FPU).
+     */
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
 #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
-/**
- * @brief Configures PACBTI features.
- *
- * This function configures the Pointer Authentication, and Branch Target
- * Identification security features as per the user configuration. It returns
- * the value of the special purpose CONTROL register accordingly, and optionally
- * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
- * architecture based) target supports PACBTI security feature.
- *
- * @param xWriteControlRegister Used to control whether the special purpose
- * CONTROL register should be updated or not.
- *
- * @return CONTROL register value according to the configured PACBTI option.
- */
+    /**
+     * @brief Configures PACBTI features.
+     *
+     * This function configures the Pointer Authentication, and Branch Target
+     * Identification security features as per the user configuration. It returns
+     * the value of the special purpose CONTROL register accordingly, and optionally
+     * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
+     * architecture based) target supports PACBTI security feature.
+     *
+     * @param xWriteControlRegister Used to control whether the special purpose
+     * CONTROL register should be updated or not.
+     *
+     * @return CONTROL register value according to the configured PACBTI option.
+     */
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
 
 #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
@@ -491,14 +488,14 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Sets up the system call stack so that upon returning from
- * SVC, the system call stack is used.
- *
- * @param pulTaskStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
- * @param ucSystemCallNumber The system call number of the system call.
- */
+    /**
+     * @brief Sets up the system call stack so that upon returning from
+     * SVC, the system call stack is used.
+     *
+     * @param pulTaskStack The current SP when the SVC was raised.
+     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+     * @param ucSystemCallNumber The system call number of the system call.
+     */
     void vSystemCallEnter( uint32_t * pulTaskStack,
                            uint32_t ulLR,
                            uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION;
@@ -507,22 +504,22 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Raise SVC for exiting from a system call.
- */
+    /**
+     * @brief Raise SVC for exiting from a system call.
+     */
     void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Sets up the task stack so that upon returning from
- * SVC, the task stack is used again.
- *
- * @param pulSystemCallStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
- */
+    /**
+     * @brief Sets up the task stack so that upon returning from
+     * SVC, the task stack is used again.
+     *
+     * @param pulSystemCallStack The current SP when the SVC was raised.
+     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+     */
     void vSystemCallExit( uint32_t * pulSystemCallStack,
                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
@@ -530,11 +527,11 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Checks whether or not the calling task is privileged.
- *
- * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
- */
+    /**
+     * @brief Checks whether or not the calling task is privileged.
+     *
+     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+     */
     BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
 
 #endif /* configENABLE_MPU == 1 */
@@ -542,9 +539,9 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief This variable is set to pdTRUE when the scheduler is started.
- */
+    /**
+     * @brief This variable is set to pdTRUE when the scheduler is started.
+     */
     PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@@ -557,10 +554,10 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-/**
- * @brief Saved as part of the task context to indicate which context the
- * task is using on the secure side.
- */
+    /**
+     * @brief Saved as part of the task context to indicate which context the
+     * task is using on the secure side.
+     */
     PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
 #endif /* configENABLE_TRUSTZONE */
 
@@ -579,21 +576,21 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
 
-/**
- * @brief The number of SysTick increments that make up one tick period.
- */
+    /**
+     * @brief The number of SysTick increments that make up one tick period.
+     */
     PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0;
 
-/**
- * @brief The maximum number of tick periods that can be suppressed is
- * limited by the 24 bit resolution of the SysTick timer.
- */
+    /**
+     * @brief The maximum number of tick periods that can be suppressed is
+     * limited by the 24 bit resolution of the SysTick timer.
+     */
     PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0;
 
-/**
- * @brief Compensate for the CPU cycles that pass while the SysTick is
- * stopped (low power functionality only).
- */
+    /**
+     * @brief Compensate for the CPU cycles that pass while the SysTick is
+     * stopped (low power functionality only).
+     */
     PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0;
 #endif /* configUSE_TICKLESS_IDLE */
 /*-----------------------------------------------------------*/
@@ -925,64 +922,57 @@ static void prvTaskExitError( void )
         /* The only permitted number of regions are 8 or 16. */
         configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
 
-        /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
-        configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
+        /* MAIR0 - Index 0. */
+        portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+        /* MAIR0 - Index 1. */
+        portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
 
-        /* Check that the MPU is present. */
-        if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
-        {
-            /* MAIR0 - Index 0. */
-            portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
-            /* MAIR0 - Index 1. */
-            portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+        /* Setup privileged flash as Read Only so that privileged tasks can
+         * read it but not modify. */
+        portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_PRIVILEGED_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup privileged flash as Read Only so that privileged tasks can
-             * read it but not modify. */
-            portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_PRIVILEGED_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup unprivileged flash as Read Only by both privileged and
+         * unprivileged tasks. All tasks can read it but no-one can modify. */
+        portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup unprivileged flash as Read Only by both privileged and
-             * unprivileged tasks. All tasks can read it but no-one can modify. */
-            portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup unprivileged syscalls flash as Read Only by both privileged
+         * and unprivileged tasks. All tasks can read it but no-one can modify. */
+        portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup unprivileged syscalls flash as Read Only by both privileged
-             * and unprivileged tasks. All tasks can read it but no-one can modify. */
-            portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup RAM containing kernel data for privileged access only. */
+        portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+                           ( portMPU_REGION_EXECUTE_NEVER );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup RAM containing kernel data for privileged access only. */
-            portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
-                               ( portMPU_REGION_EXECUTE_NEVER );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Enable mem fault. */
+        portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;
 
-            /* Enable mem fault. */
-            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;
-
-            /* Enable MPU with privileged background access i.e. unmapped
-             * regions have privileged access. */
-            portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
-        }
+        /* Enable MPU with privileged background access i.e. unmapped
+         * regions have privileged access. */
+        portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
     }
 
 #endif /* configENABLE_MPU */
@@ -1108,47 +1098,47 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
     switch( ucSVCNumber )
     {
-        #if ( configENABLE_TRUSTZONE == 1 )
-            case portSVC_ALLOCATE_SECURE_CONTEXT:
+    #if ( configENABLE_TRUSTZONE == 1 )
+        case portSVC_ALLOCATE_SECURE_CONTEXT:
 
-                /* R0 contains the stack size passed as parameter to the
-                 * vPortAllocateSecureContext function. */
-                ulR0 = pulCallerStackAddress[ 0 ];
+            /* R0 contains the stack size passed as parameter to the
+             * vPortAllocateSecureContext function. */
+            ulR0 = pulCallerStackAddress[ 0 ];
 
-                #if ( configENABLE_MPU == 1 )
-                {
-                    /* Read the CONTROL register value. */
-                    __asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
+            #if ( configENABLE_MPU == 1 )
+            {
+                /* Read the CONTROL register value. */
+                __asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
 
-                    /* The task that raised the SVC is privileged if Bit[0]
-                     * in the CONTROL register is 0. */
-                    ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+                /* The task that raised the SVC is privileged if Bit[0]
+                 * in the CONTROL register is 0. */
+                ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
 
-                    /* Allocate and load a context for the secure task. */
-                    xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
-                }
-                #else /* if ( configENABLE_MPU == 1 ) */
-                {
-                    /* Allocate and load a context for the secure task. */
-                    xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
-                }
-                #endif /* configENABLE_MPU */
+                /* Allocate and load a context for the secure task. */
+                xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
+            }
+            #else /* if ( configENABLE_MPU == 1 ) */
+            {
+                /* Allocate and load a context for the secure task. */
+                xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
+            }
+            #endif /* configENABLE_MPU */
 
-                configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );
-                SecureContext_LoadContext( xSecureContext, pxCurrentTCB );
-                break;
+            configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );
+            SecureContext_LoadContext( xSecureContext, pxCurrentTCB );
+            break;
 
-            case portSVC_FREE_SECURE_CONTEXT:
+        case portSVC_FREE_SECURE_CONTEXT:
 
-                /* R0 contains TCB being freed and R1 contains the secure
-                 * context handle to be freed. */
-                ulR0 = pulCallerStackAddress[ 0 ];
-                ulR1 = pulCallerStackAddress[ 1 ];
+            /* R0 contains TCB being freed and R1 contains the secure
+             * context handle to be freed. */
+            ulR0 = pulCallerStackAddress[ 0 ];
+            ulR1 = pulCallerStackAddress[ 1 ];
 
-                /* Free the secure context. */
-                SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );
-                break;
-        #endif /* configENABLE_TRUSTZONE */
+            /* Free the secure context. */
+            SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );
+            break;
+    #endif /* configENABLE_TRUSTZONE */
 
         case portSVC_START_SCHEDULER:
             #if ( configENABLE_TRUSTZONE == 1 )
@@ -1174,24 +1164,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             vRestoreContextOfFirstTask();
             break;
 
-            #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
-                case portSVC_RAISE_PRIVILEGE:
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+        case portSVC_RAISE_PRIVILEGE:
 
-                    /* Only raise the privilege, if the svc was raised from any of
-                     * the system calls. */
-                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
-                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
-                    {
-                        vRaisePrivilege();
-                    }
-                    break;
-            #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+            /* Only raise the privilege, if the svc was raised from any of
+             * the system calls. */
+            if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+                ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+            {
+                vRaisePrivilege();
+            }
+            break;
+    #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
-            #if ( configENABLE_MPU == 1 )
-                case portSVC_YIELD:
-                    vPortYield();
-                    break;
-            #endif /* configENABLE_MPU == 1 */
+    #if ( configENABLE_MPU == 1 )
+        case portSVC_YIELD:
+            vPortYield();
+            break;
+    #endif /* configENABLE_MPU == 1 */
 
         default:
             /* Incorrect SVC call. */
@@ -1518,21 +1508,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
         ulIndex++;
 
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters;            /* r0. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x01010101;                           /* r1. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x02020202;                           /* r2. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x03030303;                           /* r3. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x12121212;                           /* r12. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
         ulIndex++;
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode;                  /* PC. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR;                     /* xPSR. */
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
         ulIndex++;
 
         #if ( configENABLE_TRUSTZONE == 1 )
@@ -1543,7 +1533,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         #endif /* configENABLE_TRUSTZONE */
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
         ulIndex++;
 
         #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
@@ -1615,15 +1605,15 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
          * interrupt. */
         #if ( portPRELOAD_REGISTERS == 0 )
         {
-            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
+            pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-            pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
-            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-            pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
+            pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
+            *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */
+            pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */
             *pxTopOfStack = portINITIAL_EXC_RETURN;
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
@@ -1637,42 +1627,42 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #else /* portPRELOAD_REGISTERS */
         {
-            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
+            pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
+            *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
+            *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
+            *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
+            *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
+            *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
+            *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
+            *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
+            *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
+            *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
+            *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
+            *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
+            *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04. */
             pxTopOfStack--;
-            *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
+            *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxEndOfStack;            /* Slot used to hold this task's PSPLIM value. */
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
 
             #if ( configENABLE_TRUSTZONE == 1 )
             {
diff --git a/portable/IAR/ARM_CM35P/non_secure/port.c b/portable/IAR/ARM_CM35P/non_secure/port.c
index b2fd7e518..a7fb054bc 100644
--- a/portable/IAR/ARM_CM35P/non_secure/port.c
+++ b/portable/IAR/ARM_CM35P/non_secure/port.c
@@ -145,13 +145,13 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the FPU.
  */
-#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 )              /* Coprocessor Access Control Register. */
+#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */
 #define portCPACR_CP10_VALUE    ( 3UL )
 #define portCPACR_CP11_VALUE    portCPACR_CP10_VALUE
 #define portCPACR_CP10_POS      ( 20UL )
 #define portCPACR_CP11_POS      ( 22UL )
 
-#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 )              /* Floating Point Context Control Register. */
+#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */
 #define portFPCCR_ASPEN_POS     ( 31UL )
 #define portFPCCR_ASPEN_MASK    ( 1UL << portFPCCR_ASPEN_POS )
 #define portFPCCR_LSPEN_POS     ( 30UL )
@@ -188,8 +188,8 @@ typedef void ( * portISR_t )( void );
 #define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
 #define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
 #define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
@@ -230,8 +230,8 @@ typedef void ( * portISR_t )( void );
 
 #if ( portARMV8M_MINOR_VERSION >= 1 )
 
-/* Enable Privileged eXecute Never MPU attribute for the selected memory
- * region. */
+    /* Enable Privileged eXecute Never MPU attribute for the selected memory
+     * region. */
     #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER    ( 1UL << 4UL )
 #endif /* portARMV8M_MINOR_VERSION >= 1 */
 
@@ -241,9 +241,6 @@ typedef void ( * portISR_t )( void );
 /* Enable MPU. */
 #define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
 
-/* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
-
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
 #define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \
@@ -291,37 +288,37 @@ typedef void ( * portISR_t )( void );
 
 #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
 
-/**
- * @brief Initial EXC_RETURN value.
- *
- *     FF         FF         FF         FD
- * 1111 1111  1111 1111  1111 1111  1111 1101
- *
- * Bit[6] - 1 --> The exception was taken from the Secure state.
- * Bit[5] - 1 --> Do not skip stacking of additional state context.
- * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
- * Bit[3] - 1 --> Return to the Thread mode.
- * Bit[2] - 1 --> Restore registers from the process stack.
- * Bit[1] - 0 --> Reserved, 0.
- * Bit[0] - 1 --> The exception was taken to the Secure state.
- */
+    /**
+     * @brief Initial EXC_RETURN value.
+     *
+     *     FF         FF         FF         FD
+     * 1111 1111  1111 1111  1111 1111  1111 1101
+     *
+     * Bit[6] - 1 --> The exception was taken from the Secure state.
+     * Bit[5] - 1 --> Do not skip stacking of additional state context.
+     * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+     * Bit[3] - 1 --> Return to the Thread mode.
+     * Bit[2] - 1 --> Restore registers from the process stack.
+     * Bit[1] - 0 --> Reserved, 0.
+     * Bit[0] - 1 --> The exception was taken to the Secure state.
+     */
     #define portINITIAL_EXC_RETURN    ( 0xfffffffd )
 #else
 
-/**
- * @brief Initial EXC_RETURN value.
- *
- *     FF         FF         FF         BC
- * 1111 1111  1111 1111  1111 1111  1011 1100
- *
- * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
- * Bit[5] - 1 --> Do not skip stacking of additional state context.
- * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
- * Bit[3] - 1 --> Return to the Thread mode.
- * Bit[2] - 1 --> Restore registers from the process stack.
- * Bit[1] - 0 --> Reserved, 0.
- * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
- */
+    /**
+     * @brief Initial EXC_RETURN value.
+     *
+     *     FF         FF         FF         BC
+     * 1111 1111  1111 1111  1111 1111  1011 1100
+     *
+     * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+     * Bit[5] - 1 --> Do not skip stacking of additional state context.
+     * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+     * Bit[3] - 1 --> Return to the Thread mode.
+     * Bit[2] - 1 --> Restore registers from the process stack.
+     * Bit[1] - 0 --> Reserved, 0.
+     * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+     */
     #define portINITIAL_EXC_RETURN    ( 0xffffffbc )
 #endif /* configRUN_FREERTOS_SECURE_ONLY */
 
@@ -401,49 +398,49 @@ static void prvTaskExitError( void );
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Extract MPU region's access permissions from the Region Base Address
- * Register (RBAR) value.
- *
- * @param ulRBARValue RBAR value for the MPU region.
- *
- * @return uint32_t Access permissions.
- */
+    /**
+     * @brief Extract MPU region's access permissions from the Region Base Address
+     * Register (RBAR) value.
+     *
+     * @param ulRBARValue RBAR value for the MPU region.
+     *
+     * @return uint32_t Access permissions.
+     */
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Setup the Memory Protection Unit (MPU).
- */
+    /**
+     * @brief Setup the Memory Protection Unit (MPU).
+     */
     static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_MPU */
 
 #if ( configENABLE_FPU == 1 )
 
-/**
- * @brief Setup the Floating Point Unit (FPU).
- */
+    /**
+     * @brief Setup the Floating Point Unit (FPU).
+     */
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
 #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
-/**
- * @brief Configures PACBTI features.
- *
- * This function configures the Pointer Authentication, and Branch Target
- * Identification security features as per the user configuration. It returns
- * the value of the special purpose CONTROL register accordingly, and optionally
- * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
- * architecture based) target supports PACBTI security feature.
- *
- * @param xWriteControlRegister Used to control whether the special purpose
- * CONTROL register should be updated or not.
- *
- * @return CONTROL register value according to the configured PACBTI option.
- */
+    /**
+     * @brief Configures PACBTI features.
+     *
+     * This function configures the Pointer Authentication, and Branch Target
+     * Identification security features as per the user configuration. It returns
+     * the value of the special purpose CONTROL register accordingly, and optionally
+     * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
+     * architecture based) target supports PACBTI security feature.
+     *
+     * @param xWriteControlRegister Used to control whether the special purpose
+     * CONTROL register should be updated or not.
+     *
+     * @return CONTROL register value according to the configured PACBTI option.
+     */
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
 
 #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
@@ -491,14 +488,14 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Sets up the system call stack so that upon returning from
- * SVC, the system call stack is used.
- *
- * @param pulTaskStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
- * @param ucSystemCallNumber The system call number of the system call.
- */
+    /**
+     * @brief Sets up the system call stack so that upon returning from
+     * SVC, the system call stack is used.
+     *
+     * @param pulTaskStack The current SP when the SVC was raised.
+     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+     * @param ucSystemCallNumber The system call number of the system call.
+     */
     void vSystemCallEnter( uint32_t * pulTaskStack,
                            uint32_t ulLR,
                            uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION;
@@ -507,22 +504,22 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Raise SVC for exiting from a system call.
- */
+    /**
+     * @brief Raise SVC for exiting from a system call.
+     */
     void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Sets up the task stack so that upon returning from
- * SVC, the task stack is used again.
- *
- * @param pulSystemCallStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
- */
+    /**
+     * @brief Sets up the task stack so that upon returning from
+     * SVC, the task stack is used again.
+     *
+     * @param pulSystemCallStack The current SP when the SVC was raised.
+     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+     */
     void vSystemCallExit( uint32_t * pulSystemCallStack,
                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
@@ -530,11 +527,11 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Checks whether or not the calling task is privileged.
- *
- * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
- */
+    /**
+     * @brief Checks whether or not the calling task is privileged.
+     *
+     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+     */
     BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
 
 #endif /* configENABLE_MPU == 1 */
@@ -542,9 +539,9 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief This variable is set to pdTRUE when the scheduler is started.
- */
+    /**
+     * @brief This variable is set to pdTRUE when the scheduler is started.
+     */
     PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@@ -557,10 +554,10 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-/**
- * @brief Saved as part of the task context to indicate which context the
- * task is using on the secure side.
- */
+    /**
+     * @brief Saved as part of the task context to indicate which context the
+     * task is using on the secure side.
+     */
     PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
 #endif /* configENABLE_TRUSTZONE */
 
@@ -579,21 +576,21 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
 
-/**
- * @brief The number of SysTick increments that make up one tick period.
- */
+    /**
+     * @brief The number of SysTick increments that make up one tick period.
+     */
     PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0;
 
-/**
- * @brief The maximum number of tick periods that can be suppressed is
- * limited by the 24 bit resolution of the SysTick timer.
- */
+    /**
+     * @brief The maximum number of tick periods that can be suppressed is
+     * limited by the 24 bit resolution of the SysTick timer.
+     */
     PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0;
 
-/**
- * @brief Compensate for the CPU cycles that pass while the SysTick is
- * stopped (low power functionality only).
- */
+    /**
+     * @brief Compensate for the CPU cycles that pass while the SysTick is
+     * stopped (low power functionality only).
+     */
     PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0;
 #endif /* configUSE_TICKLESS_IDLE */
 /*-----------------------------------------------------------*/
@@ -925,64 +922,57 @@ static void prvTaskExitError( void )
         /* The only permitted number of regions are 8 or 16. */
         configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
 
-        /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
-        configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
+        /* MAIR0 - Index 0. */
+        portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+        /* MAIR0 - Index 1. */
+        portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
 
-        /* Check that the MPU is present. */
-        if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
-        {
-            /* MAIR0 - Index 0. */
-            portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
-            /* MAIR0 - Index 1. */
-            portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+        /* Setup privileged flash as Read Only so that privileged tasks can
+         * read it but not modify. */
+        portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_PRIVILEGED_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup privileged flash as Read Only so that privileged tasks can
-             * read it but not modify. */
-            portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_PRIVILEGED_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup unprivileged flash as Read Only by both privileged and
+         * unprivileged tasks. All tasks can read it but no-one can modify. */
+        portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup unprivileged flash as Read Only by both privileged and
-             * unprivileged tasks. All tasks can read it but no-one can modify. */
-            portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup unprivileged syscalls flash as Read Only by both privileged
+         * and unprivileged tasks. All tasks can read it but no-one can modify. */
+        portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup unprivileged syscalls flash as Read Only by both privileged
-             * and unprivileged tasks. All tasks can read it but no-one can modify. */
-            portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup RAM containing kernel data for privileged access only. */
+        portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+                           ( portMPU_REGION_EXECUTE_NEVER );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup RAM containing kernel data for privileged access only. */
-            portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
-                               ( portMPU_REGION_EXECUTE_NEVER );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Enable mem fault. */
+        portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;
 
-            /* Enable mem fault. */
-            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;
-
-            /* Enable MPU with privileged background access i.e. unmapped
-             * regions have privileged access. */
-            portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
-        }
+        /* Enable MPU with privileged background access i.e. unmapped
+         * regions have privileged access. */
+        portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
     }
 
 #endif /* configENABLE_MPU */
@@ -1108,47 +1098,47 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
     switch( ucSVCNumber )
     {
-        #if ( configENABLE_TRUSTZONE == 1 )
-            case portSVC_ALLOCATE_SECURE_CONTEXT:
+    #if ( configENABLE_TRUSTZONE == 1 )
+        case portSVC_ALLOCATE_SECURE_CONTEXT:
 
-                /* R0 contains the stack size passed as parameter to the
-                 * vPortAllocateSecureContext function. */
-                ulR0 = pulCallerStackAddress[ 0 ];
+            /* R0 contains the stack size passed as parameter to the
+             * vPortAllocateSecureContext function. */
+            ulR0 = pulCallerStackAddress[ 0 ];
 
-                #if ( configENABLE_MPU == 1 )
-                {
-                    /* Read the CONTROL register value. */
-                    __asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
+            #if ( configENABLE_MPU == 1 )
+            {
+                /* Read the CONTROL register value. */
+                __asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
 
-                    /* The task that raised the SVC is privileged if Bit[0]
-                     * in the CONTROL register is 0. */
-                    ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+                /* The task that raised the SVC is privileged if Bit[0]
+                 * in the CONTROL register is 0. */
+                ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
 
-                    /* Allocate and load a context for the secure task. */
-                    xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
-                }
-                #else /* if ( configENABLE_MPU == 1 ) */
-                {
-                    /* Allocate and load a context for the secure task. */
-                    xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
-                }
-                #endif /* configENABLE_MPU */
+                /* Allocate and load a context for the secure task. */
+                xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
+            }
+            #else /* if ( configENABLE_MPU == 1 ) */
+            {
+                /* Allocate and load a context for the secure task. */
+                xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
+            }
+            #endif /* configENABLE_MPU */
 
-                configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );
-                SecureContext_LoadContext( xSecureContext, pxCurrentTCB );
-                break;
+            configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );
+            SecureContext_LoadContext( xSecureContext, pxCurrentTCB );
+            break;
 
-            case portSVC_FREE_SECURE_CONTEXT:
+        case portSVC_FREE_SECURE_CONTEXT:
 
-                /* R0 contains TCB being freed and R1 contains the secure
-                 * context handle to be freed. */
-                ulR0 = pulCallerStackAddress[ 0 ];
-                ulR1 = pulCallerStackAddress[ 1 ];
+            /* R0 contains TCB being freed and R1 contains the secure
+             * context handle to be freed. */
+            ulR0 = pulCallerStackAddress[ 0 ];
+            ulR1 = pulCallerStackAddress[ 1 ];
 
-                /* Free the secure context. */
-                SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );
-                break;
-        #endif /* configENABLE_TRUSTZONE */
+            /* Free the secure context. */
+            SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );
+            break;
+    #endif /* configENABLE_TRUSTZONE */
 
         case portSVC_START_SCHEDULER:
             #if ( configENABLE_TRUSTZONE == 1 )
@@ -1174,24 +1164,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             vRestoreContextOfFirstTask();
             break;
 
-            #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
-                case portSVC_RAISE_PRIVILEGE:
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+        case portSVC_RAISE_PRIVILEGE:
 
-                    /* Only raise the privilege, if the svc was raised from any of
-                     * the system calls. */
-                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
-                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
-                    {
-                        vRaisePrivilege();
-                    }
-                    break;
-            #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+            /* Only raise the privilege, if the svc was raised from any of
+             * the system calls. */
+            if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+                ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+            {
+                vRaisePrivilege();
+            }
+            break;
+    #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
-            #if ( configENABLE_MPU == 1 )
-                case portSVC_YIELD:
-                    vPortYield();
-                    break;
-            #endif /* configENABLE_MPU == 1 */
+    #if ( configENABLE_MPU == 1 )
+        case portSVC_YIELD:
+            vPortYield();
+            break;
+    #endif /* configENABLE_MPU == 1 */
 
         default:
             /* Incorrect SVC call. */
@@ -1518,21 +1508,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
         ulIndex++;
 
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters;            /* r0. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x01010101;                           /* r1. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x02020202;                           /* r2. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x03030303;                           /* r3. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x12121212;                           /* r12. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
         ulIndex++;
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode;                  /* PC. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR;                     /* xPSR. */
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
         ulIndex++;
 
         #if ( configENABLE_TRUSTZONE == 1 )
@@ -1543,7 +1533,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         #endif /* configENABLE_TRUSTZONE */
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
         ulIndex++;
 
         #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
@@ -1615,15 +1605,15 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
          * interrupt. */
         #if ( portPRELOAD_REGISTERS == 0 )
         {
-            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
+            pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-            pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
-            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-            pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
+            pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
+            *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */
+            pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */
             *pxTopOfStack = portINITIAL_EXC_RETURN;
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
@@ -1637,42 +1627,42 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #else /* portPRELOAD_REGISTERS */
         {
-            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
+            pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
+            *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
+            *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
+            *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
+            *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
+            *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
+            *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
+            *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
+            *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
+            *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
+            *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
+            *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
+            *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04. */
             pxTopOfStack--;
-            *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
+            *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxEndOfStack;            /* Slot used to hold this task's PSPLIM value. */
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
 
             #if ( configENABLE_TRUSTZONE == 1 )
             {
diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c b/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
index b2fd7e518..a7fb054bc 100644
--- a/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
@@ -145,13 +145,13 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the FPU.
  */
-#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 )              /* Coprocessor Access Control Register. */
+#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */
 #define portCPACR_CP10_VALUE    ( 3UL )
 #define portCPACR_CP11_VALUE    portCPACR_CP10_VALUE
 #define portCPACR_CP10_POS      ( 20UL )
 #define portCPACR_CP11_POS      ( 22UL )
 
-#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 )              /* Floating Point Context Control Register. */
+#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */
 #define portFPCCR_ASPEN_POS     ( 31UL )
 #define portFPCCR_ASPEN_MASK    ( 1UL << portFPCCR_ASPEN_POS )
 #define portFPCCR_LSPEN_POS     ( 30UL )
@@ -188,8 +188,8 @@ typedef void ( * portISR_t )( void );
 #define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
 #define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
 #define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
@@ -230,8 +230,8 @@ typedef void ( * portISR_t )( void );
 
 #if ( portARMV8M_MINOR_VERSION >= 1 )
 
-/* Enable Privileged eXecute Never MPU attribute for the selected memory
- * region. */
+    /* Enable Privileged eXecute Never MPU attribute for the selected memory
+     * region. */
     #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER    ( 1UL << 4UL )
 #endif /* portARMV8M_MINOR_VERSION >= 1 */
 
@@ -241,9 +241,6 @@ typedef void ( * portISR_t )( void );
 /* Enable MPU. */
 #define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
 
-/* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
-
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
 #define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \
@@ -291,37 +288,37 @@ typedef void ( * portISR_t )( void );
 
 #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
 
-/**
- * @brief Initial EXC_RETURN value.
- *
- *     FF         FF         FF         FD
- * 1111 1111  1111 1111  1111 1111  1111 1101
- *
- * Bit[6] - 1 --> The exception was taken from the Secure state.
- * Bit[5] - 1 --> Do not skip stacking of additional state context.
- * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
- * Bit[3] - 1 --> Return to the Thread mode.
- * Bit[2] - 1 --> Restore registers from the process stack.
- * Bit[1] - 0 --> Reserved, 0.
- * Bit[0] - 1 --> The exception was taken to the Secure state.
- */
+    /**
+     * @brief Initial EXC_RETURN value.
+     *
+     *     FF         FF         FF         FD
+     * 1111 1111  1111 1111  1111 1111  1111 1101
+     *
+     * Bit[6] - 1 --> The exception was taken from the Secure state.
+     * Bit[5] - 1 --> Do not skip stacking of additional state context.
+     * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+     * Bit[3] - 1 --> Return to the Thread mode.
+     * Bit[2] - 1 --> Restore registers from the process stack.
+     * Bit[1] - 0 --> Reserved, 0.
+     * Bit[0] - 1 --> The exception was taken to the Secure state.
+     */
     #define portINITIAL_EXC_RETURN    ( 0xfffffffd )
 #else
 
-/**
- * @brief Initial EXC_RETURN value.
- *
- *     FF         FF         FF         BC
- * 1111 1111  1111 1111  1111 1111  1011 1100
- *
- * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
- * Bit[5] - 1 --> Do not skip stacking of additional state context.
- * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
- * Bit[3] - 1 --> Return to the Thread mode.
- * Bit[2] - 1 --> Restore registers from the process stack.
- * Bit[1] - 0 --> Reserved, 0.
- * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
- */
+    /**
+     * @brief Initial EXC_RETURN value.
+     *
+     *     FF         FF         FF         BC
+     * 1111 1111  1111 1111  1111 1111  1011 1100
+     *
+     * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+     * Bit[5] - 1 --> Do not skip stacking of additional state context.
+     * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+     * Bit[3] - 1 --> Return to the Thread mode.
+     * Bit[2] - 1 --> Restore registers from the process stack.
+     * Bit[1] - 0 --> Reserved, 0.
+     * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+     */
     #define portINITIAL_EXC_RETURN    ( 0xffffffbc )
 #endif /* configRUN_FREERTOS_SECURE_ONLY */
 
@@ -401,49 +398,49 @@ static void prvTaskExitError( void );
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Extract MPU region's access permissions from the Region Base Address
- * Register (RBAR) value.
- *
- * @param ulRBARValue RBAR value for the MPU region.
- *
- * @return uint32_t Access permissions.
- */
+    /**
+     * @brief Extract MPU region's access permissions from the Region Base Address
+     * Register (RBAR) value.
+     *
+     * @param ulRBARValue RBAR value for the MPU region.
+     *
+     * @return uint32_t Access permissions.
+     */
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Setup the Memory Protection Unit (MPU).
- */
+    /**
+     * @brief Setup the Memory Protection Unit (MPU).
+     */
     static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_MPU */
 
 #if ( configENABLE_FPU == 1 )
 
-/**
- * @brief Setup the Floating Point Unit (FPU).
- */
+    /**
+     * @brief Setup the Floating Point Unit (FPU).
+     */
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
 #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
-/**
- * @brief Configures PACBTI features.
- *
- * This function configures the Pointer Authentication, and Branch Target
- * Identification security features as per the user configuration. It returns
- * the value of the special purpose CONTROL register accordingly, and optionally
- * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
- * architecture based) target supports PACBTI security feature.
- *
- * @param xWriteControlRegister Used to control whether the special purpose
- * CONTROL register should be updated or not.
- *
- * @return CONTROL register value according to the configured PACBTI option.
- */
+    /**
+     * @brief Configures PACBTI features.
+     *
+     * This function configures the Pointer Authentication, and Branch Target
+     * Identification security features as per the user configuration. It returns
+     * the value of the special purpose CONTROL register accordingly, and optionally
+     * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
+     * architecture based) target supports PACBTI security feature.
+     *
+     * @param xWriteControlRegister Used to control whether the special purpose
+     * CONTROL register should be updated or not.
+     *
+     * @return CONTROL register value according to the configured PACBTI option.
+     */
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
 
 #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
@@ -491,14 +488,14 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Sets up the system call stack so that upon returning from
- * SVC, the system call stack is used.
- *
- * @param pulTaskStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
- * @param ucSystemCallNumber The system call number of the system call.
- */
+    /**
+     * @brief Sets up the system call stack so that upon returning from
+     * SVC, the system call stack is used.
+     *
+     * @param pulTaskStack The current SP when the SVC was raised.
+     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+     * @param ucSystemCallNumber The system call number of the system call.
+     */
     void vSystemCallEnter( uint32_t * pulTaskStack,
                            uint32_t ulLR,
                            uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION;
@@ -507,22 +504,22 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Raise SVC for exiting from a system call.
- */
+    /**
+     * @brief Raise SVC for exiting from a system call.
+     */
     void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Sets up the task stack so that upon returning from
- * SVC, the task stack is used again.
- *
- * @param pulSystemCallStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
- */
+    /**
+     * @brief Sets up the task stack so that upon returning from
+     * SVC, the task stack is used again.
+     *
+     * @param pulSystemCallStack The current SP when the SVC was raised.
+     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+     */
     void vSystemCallExit( uint32_t * pulSystemCallStack,
                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
@@ -530,11 +527,11 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Checks whether or not the calling task is privileged.
- *
- * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
- */
+    /**
+     * @brief Checks whether or not the calling task is privileged.
+     *
+     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+     */
     BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
 
 #endif /* configENABLE_MPU == 1 */
@@ -542,9 +539,9 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief This variable is set to pdTRUE when the scheduler is started.
- */
+    /**
+     * @brief This variable is set to pdTRUE when the scheduler is started.
+     */
     PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@@ -557,10 +554,10 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-/**
- * @brief Saved as part of the task context to indicate which context the
- * task is using on the secure side.
- */
+    /**
+     * @brief Saved as part of the task context to indicate which context the
+     * task is using on the secure side.
+     */
     PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
 #endif /* configENABLE_TRUSTZONE */
 
@@ -579,21 +576,21 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
 
-/**
- * @brief The number of SysTick increments that make up one tick period.
- */
+    /**
+     * @brief The number of SysTick increments that make up one tick period.
+     */
     PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0;
 
-/**
- * @brief The maximum number of tick periods that can be suppressed is
- * limited by the 24 bit resolution of the SysTick timer.
- */
+    /**
+     * @brief The maximum number of tick periods that can be suppressed is
+     * limited by the 24 bit resolution of the SysTick timer.
+     */
     PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0;
 
-/**
- * @brief Compensate for the CPU cycles that pass while the SysTick is
- * stopped (low power functionality only).
- */
+    /**
+     * @brief Compensate for the CPU cycles that pass while the SysTick is
+     * stopped (low power functionality only).
+     */
     PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0;
 #endif /* configUSE_TICKLESS_IDLE */
 /*-----------------------------------------------------------*/
@@ -925,64 +922,57 @@ static void prvTaskExitError( void )
         /* The only permitted number of regions are 8 or 16. */
         configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
 
-        /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
-        configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
+        /* MAIR0 - Index 0. */
+        portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+        /* MAIR0 - Index 1. */
+        portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
 
-        /* Check that the MPU is present. */
-        if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
-        {
-            /* MAIR0 - Index 0. */
-            portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
-            /* MAIR0 - Index 1. */
-            portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+        /* Setup privileged flash as Read Only so that privileged tasks can
+         * read it but not modify. */
+        portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_PRIVILEGED_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup privileged flash as Read Only so that privileged tasks can
-             * read it but not modify. */
-            portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_PRIVILEGED_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup unprivileged flash as Read Only by both privileged and
+         * unprivileged tasks. All tasks can read it but no-one can modify. */
+        portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup unprivileged flash as Read Only by both privileged and
-             * unprivileged tasks. All tasks can read it but no-one can modify. */
-            portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup unprivileged syscalls flash as Read Only by both privileged
+         * and unprivileged tasks. All tasks can read it but no-one can modify. */
+        portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup unprivileged syscalls flash as Read Only by both privileged
-             * and unprivileged tasks. All tasks can read it but no-one can modify. */
-            portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup RAM containing kernel data for privileged access only. */
+        portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+                           ( portMPU_REGION_EXECUTE_NEVER );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup RAM containing kernel data for privileged access only. */
-            portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
-                               ( portMPU_REGION_EXECUTE_NEVER );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Enable mem fault. */
+        portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;
 
-            /* Enable mem fault. */
-            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;
-
-            /* Enable MPU with privileged background access i.e. unmapped
-             * regions have privileged access. */
-            portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
-        }
+        /* Enable MPU with privileged background access i.e. unmapped
+         * regions have privileged access. */
+        portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
     }
 
 #endif /* configENABLE_MPU */
@@ -1108,47 +1098,47 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
     switch( ucSVCNumber )
     {
-        #if ( configENABLE_TRUSTZONE == 1 )
-            case portSVC_ALLOCATE_SECURE_CONTEXT:
+    #if ( configENABLE_TRUSTZONE == 1 )
+        case portSVC_ALLOCATE_SECURE_CONTEXT:
 
-                /* R0 contains the stack size passed as parameter to the
-                 * vPortAllocateSecureContext function. */
-                ulR0 = pulCallerStackAddress[ 0 ];
+            /* R0 contains the stack size passed as parameter to the
+             * vPortAllocateSecureContext function. */
+            ulR0 = pulCallerStackAddress[ 0 ];
 
-                #if ( configENABLE_MPU == 1 )
-                {
-                    /* Read the CONTROL register value. */
-                    __asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
+            #if ( configENABLE_MPU == 1 )
+            {
+                /* Read the CONTROL register value. */
+                __asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
 
-                    /* The task that raised the SVC is privileged if Bit[0]
-                     * in the CONTROL register is 0. */
-                    ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+                /* The task that raised the SVC is privileged if Bit[0]
+                 * in the CONTROL register is 0. */
+                ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
 
-                    /* Allocate and load a context for the secure task. */
-                    xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
-                }
-                #else /* if ( configENABLE_MPU == 1 ) */
-                {
-                    /* Allocate and load a context for the secure task. */
-                    xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
-                }
-                #endif /* configENABLE_MPU */
+                /* Allocate and load a context for the secure task. */
+                xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
+            }
+            #else /* if ( configENABLE_MPU == 1 ) */
+            {
+                /* Allocate and load a context for the secure task. */
+                xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
+            }
+            #endif /* configENABLE_MPU */
 
-                configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );
-                SecureContext_LoadContext( xSecureContext, pxCurrentTCB );
-                break;
+            configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );
+            SecureContext_LoadContext( xSecureContext, pxCurrentTCB );
+            break;
 
-            case portSVC_FREE_SECURE_CONTEXT:
+        case portSVC_FREE_SECURE_CONTEXT:
 
-                /* R0 contains TCB being freed and R1 contains the secure
-                 * context handle to be freed. */
-                ulR0 = pulCallerStackAddress[ 0 ];
-                ulR1 = pulCallerStackAddress[ 1 ];
+            /* R0 contains TCB being freed and R1 contains the secure
+             * context handle to be freed. */
+            ulR0 = pulCallerStackAddress[ 0 ];
+            ulR1 = pulCallerStackAddress[ 1 ];
 
-                /* Free the secure context. */
-                SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );
-                break;
-        #endif /* configENABLE_TRUSTZONE */
+            /* Free the secure context. */
+            SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );
+            break;
+    #endif /* configENABLE_TRUSTZONE */
 
         case portSVC_START_SCHEDULER:
             #if ( configENABLE_TRUSTZONE == 1 )
@@ -1174,24 +1164,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             vRestoreContextOfFirstTask();
             break;
 
-            #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
-                case portSVC_RAISE_PRIVILEGE:
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+        case portSVC_RAISE_PRIVILEGE:
 
-                    /* Only raise the privilege, if the svc was raised from any of
-                     * the system calls. */
-                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
-                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
-                    {
-                        vRaisePrivilege();
-                    }
-                    break;
-            #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+            /* Only raise the privilege, if the svc was raised from any of
+             * the system calls. */
+            if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+                ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+            {
+                vRaisePrivilege();
+            }
+            break;
+    #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
-            #if ( configENABLE_MPU == 1 )
-                case portSVC_YIELD:
-                    vPortYield();
-                    break;
-            #endif /* configENABLE_MPU == 1 */
+    #if ( configENABLE_MPU == 1 )
+        case portSVC_YIELD:
+            vPortYield();
+            break;
+    #endif /* configENABLE_MPU == 1 */
 
         default:
             /* Incorrect SVC call. */
@@ -1518,21 +1508,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
         ulIndex++;
 
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters;            /* r0. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x01010101;                           /* r1. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x02020202;                           /* r2. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x03030303;                           /* r3. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x12121212;                           /* r12. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
         ulIndex++;
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode;                  /* PC. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR;                     /* xPSR. */
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
         ulIndex++;
 
         #if ( configENABLE_TRUSTZONE == 1 )
@@ -1543,7 +1533,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         #endif /* configENABLE_TRUSTZONE */
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
         ulIndex++;
 
         #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
@@ -1615,15 +1605,15 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
          * interrupt. */
         #if ( portPRELOAD_REGISTERS == 0 )
         {
-            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
+            pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-            pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
-            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-            pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
+            pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
+            *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */
+            pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */
             *pxTopOfStack = portINITIAL_EXC_RETURN;
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
@@ -1637,42 +1627,42 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #else /* portPRELOAD_REGISTERS */
         {
-            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
+            pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
+            *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
+            *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
+            *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
+            *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
+            *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
+            *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
+            *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
+            *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
+            *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
+            *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
+            *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
+            *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04. */
             pxTopOfStack--;
-            *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
+            *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxEndOfStack;            /* Slot used to hold this task's PSPLIM value. */
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
 
             #if ( configENABLE_TRUSTZONE == 1 )
             {
diff --git a/portable/IAR/ARM_CM55/non_secure/port.c b/portable/IAR/ARM_CM55/non_secure/port.c
index b2fd7e518..a7fb054bc 100644
--- a/portable/IAR/ARM_CM55/non_secure/port.c
+++ b/portable/IAR/ARM_CM55/non_secure/port.c
@@ -145,13 +145,13 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the FPU.
  */
-#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 )              /* Coprocessor Access Control Register. */
+#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */
 #define portCPACR_CP10_VALUE    ( 3UL )
 #define portCPACR_CP11_VALUE    portCPACR_CP10_VALUE
 #define portCPACR_CP10_POS      ( 20UL )
 #define portCPACR_CP11_POS      ( 22UL )
 
-#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 )              /* Floating Point Context Control Register. */
+#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */
 #define portFPCCR_ASPEN_POS     ( 31UL )
 #define portFPCCR_ASPEN_MASK    ( 1UL << portFPCCR_ASPEN_POS )
 #define portFPCCR_LSPEN_POS     ( 30UL )
@@ -188,8 +188,8 @@ typedef void ( * portISR_t )( void );
 #define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
 #define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
 #define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
@@ -230,8 +230,8 @@ typedef void ( * portISR_t )( void );
 
 #if ( portARMV8M_MINOR_VERSION >= 1 )
 
-/* Enable Privileged eXecute Never MPU attribute for the selected memory
- * region. */
+    /* Enable Privileged eXecute Never MPU attribute for the selected memory
+     * region. */
     #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER    ( 1UL << 4UL )
 #endif /* portARMV8M_MINOR_VERSION >= 1 */
 
@@ -241,9 +241,6 @@ typedef void ( * portISR_t )( void );
 /* Enable MPU. */
 #define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
 
-/* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
-
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
 #define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \
@@ -291,37 +288,37 @@ typedef void ( * portISR_t )( void );
 
 #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
 
-/**
- * @brief Initial EXC_RETURN value.
- *
- *     FF         FF         FF         FD
- * 1111 1111  1111 1111  1111 1111  1111 1101
- *
- * Bit[6] - 1 --> The exception was taken from the Secure state.
- * Bit[5] - 1 --> Do not skip stacking of additional state context.
- * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
- * Bit[3] - 1 --> Return to the Thread mode.
- * Bit[2] - 1 --> Restore registers from the process stack.
- * Bit[1] - 0 --> Reserved, 0.
- * Bit[0] - 1 --> The exception was taken to the Secure state.
- */
+    /**
+     * @brief Initial EXC_RETURN value.
+     *
+     *     FF         FF         FF         FD
+     * 1111 1111  1111 1111  1111 1111  1111 1101
+     *
+     * Bit[6] - 1 --> The exception was taken from the Secure state.
+     * Bit[5] - 1 --> Do not skip stacking of additional state context.
+     * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+     * Bit[3] - 1 --> Return to the Thread mode.
+     * Bit[2] - 1 --> Restore registers from the process stack.
+     * Bit[1] - 0 --> Reserved, 0.
+     * Bit[0] - 1 --> The exception was taken to the Secure state.
+     */
     #define portINITIAL_EXC_RETURN    ( 0xfffffffd )
 #else
 
-/**
- * @brief Initial EXC_RETURN value.
- *
- *     FF         FF         FF         BC
- * 1111 1111  1111 1111  1111 1111  1011 1100
- *
- * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
- * Bit[5] - 1 --> Do not skip stacking of additional state context.
- * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
- * Bit[3] - 1 --> Return to the Thread mode.
- * Bit[2] - 1 --> Restore registers from the process stack.
- * Bit[1] - 0 --> Reserved, 0.
- * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
- */
+    /**
+     * @brief Initial EXC_RETURN value.
+     *
+     *     FF         FF         FF         BC
+     * 1111 1111  1111 1111  1111 1111  1011 1100
+     *
+     * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+     * Bit[5] - 1 --> Do not skip stacking of additional state context.
+     * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+     * Bit[3] - 1 --> Return to the Thread mode.
+     * Bit[2] - 1 --> Restore registers from the process stack.
+     * Bit[1] - 0 --> Reserved, 0.
+     * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+     */
     #define portINITIAL_EXC_RETURN    ( 0xffffffbc )
 #endif /* configRUN_FREERTOS_SECURE_ONLY */
 
@@ -401,49 +398,49 @@ static void prvTaskExitError( void );
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Extract MPU region's access permissions from the Region Base Address
- * Register (RBAR) value.
- *
- * @param ulRBARValue RBAR value for the MPU region.
- *
- * @return uint32_t Access permissions.
- */
+    /**
+     * @brief Extract MPU region's access permissions from the Region Base Address
+     * Register (RBAR) value.
+     *
+     * @param ulRBARValue RBAR value for the MPU region.
+     *
+     * @return uint32_t Access permissions.
+     */
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Setup the Memory Protection Unit (MPU).
- */
+    /**
+     * @brief Setup the Memory Protection Unit (MPU).
+     */
     static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_MPU */
 
 #if ( configENABLE_FPU == 1 )
 
-/**
- * @brief Setup the Floating Point Unit (FPU).
- */
+    /**
+     * @brief Setup the Floating Point Unit (FPU).
+     */
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
 #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
-/**
- * @brief Configures PACBTI features.
- *
- * This function configures the Pointer Authentication, and Branch Target
- * Identification security features as per the user configuration. It returns
- * the value of the special purpose CONTROL register accordingly, and optionally
- * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
- * architecture based) target supports PACBTI security feature.
- *
- * @param xWriteControlRegister Used to control whether the special purpose
- * CONTROL register should be updated or not.
- *
- * @return CONTROL register value according to the configured PACBTI option.
- */
+    /**
+     * @brief Configures PACBTI features.
+     *
+     * This function configures the Pointer Authentication, and Branch Target
+     * Identification security features as per the user configuration. It returns
+     * the value of the special purpose CONTROL register accordingly, and optionally
+     * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
+     * architecture based) target supports PACBTI security feature.
+     *
+     * @param xWriteControlRegister Used to control whether the special purpose
+     * CONTROL register should be updated or not.
+     *
+     * @return CONTROL register value according to the configured PACBTI option.
+     */
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
 
 #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
@@ -491,14 +488,14 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Sets up the system call stack so that upon returning from
- * SVC, the system call stack is used.
- *
- * @param pulTaskStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
- * @param ucSystemCallNumber The system call number of the system call.
- */
+    /**
+     * @brief Sets up the system call stack so that upon returning from
+     * SVC, the system call stack is used.
+     *
+     * @param pulTaskStack The current SP when the SVC was raised.
+     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+     * @param ucSystemCallNumber The system call number of the system call.
+     */
     void vSystemCallEnter( uint32_t * pulTaskStack,
                            uint32_t ulLR,
                            uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION;
@@ -507,22 +504,22 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Raise SVC for exiting from a system call.
- */
+    /**
+     * @brief Raise SVC for exiting from a system call.
+     */
     void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Sets up the task stack so that upon returning from
- * SVC, the task stack is used again.
- *
- * @param pulSystemCallStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
- */
+    /**
+     * @brief Sets up the task stack so that upon returning from
+     * SVC, the task stack is used again.
+     *
+     * @param pulSystemCallStack The current SP when the SVC was raised.
+     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+     */
     void vSystemCallExit( uint32_t * pulSystemCallStack,
                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
@@ -530,11 +527,11 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Checks whether or not the calling task is privileged.
- *
- * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
- */
+    /**
+     * @brief Checks whether or not the calling task is privileged.
+     *
+     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+     */
     BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
 
 #endif /* configENABLE_MPU == 1 */
@@ -542,9 +539,9 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief This variable is set to pdTRUE when the scheduler is started.
- */
+    /**
+     * @brief This variable is set to pdTRUE when the scheduler is started.
+     */
     PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@@ -557,10 +554,10 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-/**
- * @brief Saved as part of the task context to indicate which context the
- * task is using on the secure side.
- */
+    /**
+     * @brief Saved as part of the task context to indicate which context the
+     * task is using on the secure side.
+     */
     PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
 #endif /* configENABLE_TRUSTZONE */
 
@@ -579,21 +576,21 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
 
-/**
- * @brief The number of SysTick increments that make up one tick period.
- */
+    /**
+     * @brief The number of SysTick increments that make up one tick period.
+     */
     PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0;
 
-/**
- * @brief The maximum number of tick periods that can be suppressed is
- * limited by the 24 bit resolution of the SysTick timer.
- */
+    /**
+     * @brief The maximum number of tick periods that can be suppressed is
+     * limited by the 24 bit resolution of the SysTick timer.
+     */
     PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0;
 
-/**
- * @brief Compensate for the CPU cycles that pass while the SysTick is
- * stopped (low power functionality only).
- */
+    /**
+     * @brief Compensate for the CPU cycles that pass while the SysTick is
+     * stopped (low power functionality only).
+     */
     PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0;
 #endif /* configUSE_TICKLESS_IDLE */
 /*-----------------------------------------------------------*/
@@ -925,64 +922,57 @@ static void prvTaskExitError( void )
         /* The only permitted number of regions are 8 or 16. */
         configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
 
-        /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
-        configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
+        /* MAIR0 - Index 0. */
+        portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+        /* MAIR0 - Index 1. */
+        portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
 
-        /* Check that the MPU is present. */
-        if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
-        {
-            /* MAIR0 - Index 0. */
-            portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
-            /* MAIR0 - Index 1. */
-            portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+        /* Setup privileged flash as Read Only so that privileged tasks can
+         * read it but not modify. */
+        portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_PRIVILEGED_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup privileged flash as Read Only so that privileged tasks can
-             * read it but not modify. */
-            portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_PRIVILEGED_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup unprivileged flash as Read Only by both privileged and
+         * unprivileged tasks. All tasks can read it but no-one can modify. */
+        portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup unprivileged flash as Read Only by both privileged and
-             * unprivileged tasks. All tasks can read it but no-one can modify. */
-            portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup unprivileged syscalls flash as Read Only by both privileged
+         * and unprivileged tasks. All tasks can read it but no-one can modify. */
+        portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup unprivileged syscalls flash as Read Only by both privileged
-             * and unprivileged tasks. All tasks can read it but no-one can modify. */
-            portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup RAM containing kernel data for privileged access only. */
+        portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+                           ( portMPU_REGION_EXECUTE_NEVER );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup RAM containing kernel data for privileged access only. */
-            portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
-                               ( portMPU_REGION_EXECUTE_NEVER );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Enable mem fault. */
+        portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;
 
-            /* Enable mem fault. */
-            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;
-
-            /* Enable MPU with privileged background access i.e. unmapped
-             * regions have privileged access. */
-            portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
-        }
+        /* Enable MPU with privileged background access i.e. unmapped
+         * regions have privileged access. */
+        portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
     }
 
 #endif /* configENABLE_MPU */
@@ -1108,47 +1098,47 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
     switch( ucSVCNumber )
     {
-        #if ( configENABLE_TRUSTZONE == 1 )
-            case portSVC_ALLOCATE_SECURE_CONTEXT:
+    #if ( configENABLE_TRUSTZONE == 1 )
+        case portSVC_ALLOCATE_SECURE_CONTEXT:
 
-                /* R0 contains the stack size passed as parameter to the
-                 * vPortAllocateSecureContext function. */
-                ulR0 = pulCallerStackAddress[ 0 ];
+            /* R0 contains the stack size passed as parameter to the
+             * vPortAllocateSecureContext function. */
+            ulR0 = pulCallerStackAddress[ 0 ];
 
-                #if ( configENABLE_MPU == 1 )
-                {
-                    /* Read the CONTROL register value. */
-                    __asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
+            #if ( configENABLE_MPU == 1 )
+            {
+                /* Read the CONTROL register value. */
+                __asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
 
-                    /* The task that raised the SVC is privileged if Bit[0]
-                     * in the CONTROL register is 0. */
-                    ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+                /* The task that raised the SVC is privileged if Bit[0]
+                 * in the CONTROL register is 0. */
+                ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
 
-                    /* Allocate and load a context for the secure task. */
-                    xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
-                }
-                #else /* if ( configENABLE_MPU == 1 ) */
-                {
-                    /* Allocate and load a context for the secure task. */
-                    xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
-                }
-                #endif /* configENABLE_MPU */
+                /* Allocate and load a context for the secure task. */
+                xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
+            }
+            #else /* if ( configENABLE_MPU == 1 ) */
+            {
+                /* Allocate and load a context for the secure task. */
+                xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
+            }
+            #endif /* configENABLE_MPU */
 
-                configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );
-                SecureContext_LoadContext( xSecureContext, pxCurrentTCB );
-                break;
+            configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );
+            SecureContext_LoadContext( xSecureContext, pxCurrentTCB );
+            break;
 
-            case portSVC_FREE_SECURE_CONTEXT:
+        case portSVC_FREE_SECURE_CONTEXT:
 
-                /* R0 contains TCB being freed and R1 contains the secure
-                 * context handle to be freed. */
-                ulR0 = pulCallerStackAddress[ 0 ];
-                ulR1 = pulCallerStackAddress[ 1 ];
+            /* R0 contains TCB being freed and R1 contains the secure
+             * context handle to be freed. */
+            ulR0 = pulCallerStackAddress[ 0 ];
+            ulR1 = pulCallerStackAddress[ 1 ];
 
-                /* Free the secure context. */
-                SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );
-                break;
-        #endif /* configENABLE_TRUSTZONE */
+            /* Free the secure context. */
+            SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );
+            break;
+    #endif /* configENABLE_TRUSTZONE */
 
         case portSVC_START_SCHEDULER:
             #if ( configENABLE_TRUSTZONE == 1 )
@@ -1174,24 +1164,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             vRestoreContextOfFirstTask();
             break;
 
-            #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
-                case portSVC_RAISE_PRIVILEGE:
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+        case portSVC_RAISE_PRIVILEGE:
 
-                    /* Only raise the privilege, if the svc was raised from any of
-                     * the system calls. */
-                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
-                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
-                    {
-                        vRaisePrivilege();
-                    }
-                    break;
-            #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+            /* Only raise the privilege, if the svc was raised from any of
+             * the system calls. */
+            if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+                ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+            {
+                vRaisePrivilege();
+            }
+            break;
+    #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
-            #if ( configENABLE_MPU == 1 )
-                case portSVC_YIELD:
-                    vPortYield();
-                    break;
-            #endif /* configENABLE_MPU == 1 */
+    #if ( configENABLE_MPU == 1 )
+        case portSVC_YIELD:
+            vPortYield();
+            break;
+    #endif /* configENABLE_MPU == 1 */
 
         default:
             /* Incorrect SVC call. */
@@ -1518,21 +1508,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
         ulIndex++;
 
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters;            /* r0. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x01010101;                           /* r1. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x02020202;                           /* r2. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x03030303;                           /* r3. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x12121212;                           /* r12. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
         ulIndex++;
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode;                  /* PC. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR;                     /* xPSR. */
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
         ulIndex++;
 
         #if ( configENABLE_TRUSTZONE == 1 )
@@ -1543,7 +1533,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         #endif /* configENABLE_TRUSTZONE */
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
         ulIndex++;
 
         #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
@@ -1615,15 +1605,15 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
          * interrupt. */
         #if ( portPRELOAD_REGISTERS == 0 )
         {
-            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
+            pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-            pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
-            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-            pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
+            pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
+            *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */
+            pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */
             *pxTopOfStack = portINITIAL_EXC_RETURN;
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
@@ -1637,42 +1627,42 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #else /* portPRELOAD_REGISTERS */
         {
-            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
+            pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
+            *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
+            *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
+            *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
+            *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
+            *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
+            *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
+            *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
+            *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
+            *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
+            *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
+            *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
+            *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04. */
             pxTopOfStack--;
-            *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
+            *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxEndOfStack;            /* Slot used to hold this task's PSPLIM value. */
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
 
             #if ( configENABLE_TRUSTZONE == 1 )
             {
diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/port.c b/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
index b2fd7e518..a7fb054bc 100644
--- a/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
@@ -145,13 +145,13 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the FPU.
  */
-#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 )              /* Coprocessor Access Control Register. */
+#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */
 #define portCPACR_CP10_VALUE    ( 3UL )
 #define portCPACR_CP11_VALUE    portCPACR_CP10_VALUE
 #define portCPACR_CP10_POS      ( 20UL )
 #define portCPACR_CP11_POS      ( 22UL )
 
-#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 )              /* Floating Point Context Control Register. */
+#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */
 #define portFPCCR_ASPEN_POS     ( 31UL )
 #define portFPCCR_ASPEN_MASK    ( 1UL << portFPCCR_ASPEN_POS )
 #define portFPCCR_LSPEN_POS     ( 30UL )
@@ -188,8 +188,8 @@ typedef void ( * portISR_t )( void );
 #define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
 #define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
 #define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
@@ -230,8 +230,8 @@ typedef void ( * portISR_t )( void );
 
 #if ( portARMV8M_MINOR_VERSION >= 1 )
 
-/* Enable Privileged eXecute Never MPU attribute for the selected memory
- * region. */
+    /* Enable Privileged eXecute Never MPU attribute for the selected memory
+     * region. */
     #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER    ( 1UL << 4UL )
 #endif /* portARMV8M_MINOR_VERSION >= 1 */
 
@@ -241,9 +241,6 @@ typedef void ( * portISR_t )( void );
 /* Enable MPU. */
 #define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
 
-/* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
-
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
 #define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \
@@ -291,37 +288,37 @@ typedef void ( * portISR_t )( void );
 
 #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
 
-/**
- * @brief Initial EXC_RETURN value.
- *
- *     FF         FF         FF         FD
- * 1111 1111  1111 1111  1111 1111  1111 1101
- *
- * Bit[6] - 1 --> The exception was taken from the Secure state.
- * Bit[5] - 1 --> Do not skip stacking of additional state context.
- * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
- * Bit[3] - 1 --> Return to the Thread mode.
- * Bit[2] - 1 --> Restore registers from the process stack.
- * Bit[1] - 0 --> Reserved, 0.
- * Bit[0] - 1 --> The exception was taken to the Secure state.
- */
+    /**
+     * @brief Initial EXC_RETURN value.
+     *
+     *     FF         FF         FF         FD
+     * 1111 1111  1111 1111  1111 1111  1111 1101
+     *
+     * Bit[6] - 1 --> The exception was taken from the Secure state.
+     * Bit[5] - 1 --> Do not skip stacking of additional state context.
+     * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+     * Bit[3] - 1 --> Return to the Thread mode.
+     * Bit[2] - 1 --> Restore registers from the process stack.
+     * Bit[1] - 0 --> Reserved, 0.
+     * Bit[0] - 1 --> The exception was taken to the Secure state.
+     */
     #define portINITIAL_EXC_RETURN    ( 0xfffffffd )
 #else
 
-/**
- * @brief Initial EXC_RETURN value.
- *
- *     FF         FF         FF         BC
- * 1111 1111  1111 1111  1111 1111  1011 1100
- *
- * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
- * Bit[5] - 1 --> Do not skip stacking of additional state context.
- * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
- * Bit[3] - 1 --> Return to the Thread mode.
- * Bit[2] - 1 --> Restore registers from the process stack.
- * Bit[1] - 0 --> Reserved, 0.
- * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
- */
+    /**
+     * @brief Initial EXC_RETURN value.
+     *
+     *     FF         FF         FF         BC
+     * 1111 1111  1111 1111  1111 1111  1011 1100
+     *
+     * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+     * Bit[5] - 1 --> Do not skip stacking of additional state context.
+     * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+     * Bit[3] - 1 --> Return to the Thread mode.
+     * Bit[2] - 1 --> Restore registers from the process stack.
+     * Bit[1] - 0 --> Reserved, 0.
+     * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+     */
     #define portINITIAL_EXC_RETURN    ( 0xffffffbc )
 #endif /* configRUN_FREERTOS_SECURE_ONLY */
 
@@ -401,49 +398,49 @@ static void prvTaskExitError( void );
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Extract MPU region's access permissions from the Region Base Address
- * Register (RBAR) value.
- *
- * @param ulRBARValue RBAR value for the MPU region.
- *
- * @return uint32_t Access permissions.
- */
+    /**
+     * @brief Extract MPU region's access permissions from the Region Base Address
+     * Register (RBAR) value.
+     *
+     * @param ulRBARValue RBAR value for the MPU region.
+     *
+     * @return uint32_t Access permissions.
+     */
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Setup the Memory Protection Unit (MPU).
- */
+    /**
+     * @brief Setup the Memory Protection Unit (MPU).
+     */
     static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_MPU */
 
 #if ( configENABLE_FPU == 1 )
 
-/**
- * @brief Setup the Floating Point Unit (FPU).
- */
+    /**
+     * @brief Setup the Floating Point Unit (FPU).
+     */
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
 #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
-/**
- * @brief Configures PACBTI features.
- *
- * This function configures the Pointer Authentication, and Branch Target
- * Identification security features as per the user configuration. It returns
- * the value of the special purpose CONTROL register accordingly, and optionally
- * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
- * architecture based) target supports PACBTI security feature.
- *
- * @param xWriteControlRegister Used to control whether the special purpose
- * CONTROL register should be updated or not.
- *
- * @return CONTROL register value according to the configured PACBTI option.
- */
+    /**
+     * @brief Configures PACBTI features.
+     *
+     * This function configures the Pointer Authentication, and Branch Target
+     * Identification security features as per the user configuration. It returns
+     * the value of the special purpose CONTROL register accordingly, and optionally
+     * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
+     * architecture based) target supports PACBTI security feature.
+     *
+     * @param xWriteControlRegister Used to control whether the special purpose
+     * CONTROL register should be updated or not.
+     *
+     * @return CONTROL register value according to the configured PACBTI option.
+     */
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
 
 #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
@@ -491,14 +488,14 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Sets up the system call stack so that upon returning from
- * SVC, the system call stack is used.
- *
- * @param pulTaskStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
- * @param ucSystemCallNumber The system call number of the system call.
- */
+    /**
+     * @brief Sets up the system call stack so that upon returning from
+     * SVC, the system call stack is used.
+     *
+     * @param pulTaskStack The current SP when the SVC was raised.
+     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+     * @param ucSystemCallNumber The system call number of the system call.
+     */
     void vSystemCallEnter( uint32_t * pulTaskStack,
                            uint32_t ulLR,
                            uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION;
@@ -507,22 +504,22 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Raise SVC for exiting from a system call.
- */
+    /**
+     * @brief Raise SVC for exiting from a system call.
+     */
     void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Sets up the task stack so that upon returning from
- * SVC, the task stack is used again.
- *
- * @param pulSystemCallStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
- */
+    /**
+     * @brief Sets up the task stack so that upon returning from
+     * SVC, the task stack is used again.
+     *
+     * @param pulSystemCallStack The current SP when the SVC was raised.
+     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+     */
     void vSystemCallExit( uint32_t * pulSystemCallStack,
                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
@@ -530,11 +527,11 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Checks whether or not the calling task is privileged.
- *
- * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
- */
+    /**
+     * @brief Checks whether or not the calling task is privileged.
+     *
+     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+     */
     BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
 
 #endif /* configENABLE_MPU == 1 */
@@ -542,9 +539,9 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief This variable is set to pdTRUE when the scheduler is started.
- */
+    /**
+     * @brief This variable is set to pdTRUE when the scheduler is started.
+     */
     PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@@ -557,10 +554,10 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-/**
- * @brief Saved as part of the task context to indicate which context the
- * task is using on the secure side.
- */
+    /**
+     * @brief Saved as part of the task context to indicate which context the
+     * task is using on the secure side.
+     */
     PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
 #endif /* configENABLE_TRUSTZONE */
 
@@ -579,21 +576,21 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
 
-/**
- * @brief The number of SysTick increments that make up one tick period.
- */
+    /**
+     * @brief The number of SysTick increments that make up one tick period.
+     */
     PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0;
 
-/**
- * @brief The maximum number of tick periods that can be suppressed is
- * limited by the 24 bit resolution of the SysTick timer.
- */
+    /**
+     * @brief The maximum number of tick periods that can be suppressed is
+     * limited by the 24 bit resolution of the SysTick timer.
+     */
     PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0;
 
-/**
- * @brief Compensate for the CPU cycles that pass while the SysTick is
- * stopped (low power functionality only).
- */
+    /**
+     * @brief Compensate for the CPU cycles that pass while the SysTick is
+     * stopped (low power functionality only).
+     */
     PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0;
 #endif /* configUSE_TICKLESS_IDLE */
 /*-----------------------------------------------------------*/
@@ -925,64 +922,57 @@ static void prvTaskExitError( void )
         /* The only permitted number of regions are 8 or 16. */
         configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
 
-        /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
-        configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
+        /* MAIR0 - Index 0. */
+        portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+        /* MAIR0 - Index 1. */
+        portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
 
-        /* Check that the MPU is present. */
-        if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
-        {
-            /* MAIR0 - Index 0. */
-            portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
-            /* MAIR0 - Index 1. */
-            portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+        /* Setup privileged flash as Read Only so that privileged tasks can
+         * read it but not modify. */
+        portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_PRIVILEGED_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup privileged flash as Read Only so that privileged tasks can
-             * read it but not modify. */
-            portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_PRIVILEGED_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup unprivileged flash as Read Only by both privileged and
+         * unprivileged tasks. All tasks can read it but no-one can modify. */
+        portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup unprivileged flash as Read Only by both privileged and
-             * unprivileged tasks. All tasks can read it but no-one can modify. */
-            portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup unprivileged syscalls flash as Read Only by both privileged
+         * and unprivileged tasks. All tasks can read it but no-one can modify. */
+        portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup unprivileged syscalls flash as Read Only by both privileged
-             * and unprivileged tasks. All tasks can read it but no-one can modify. */
-            portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup RAM containing kernel data for privileged access only. */
+        portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+                           ( portMPU_REGION_EXECUTE_NEVER );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup RAM containing kernel data for privileged access only. */
-            portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
-                               ( portMPU_REGION_EXECUTE_NEVER );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Enable mem fault. */
+        portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;
 
-            /* Enable mem fault. */
-            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;
-
-            /* Enable MPU with privileged background access i.e. unmapped
-             * regions have privileged access. */
-            portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
-        }
+        /* Enable MPU with privileged background access i.e. unmapped
+         * regions have privileged access. */
+        portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
     }
 
 #endif /* configENABLE_MPU */
@@ -1108,47 +1098,47 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
     switch( ucSVCNumber )
     {
-        #if ( configENABLE_TRUSTZONE == 1 )
-            case portSVC_ALLOCATE_SECURE_CONTEXT:
+    #if ( configENABLE_TRUSTZONE == 1 )
+        case portSVC_ALLOCATE_SECURE_CONTEXT:
 
-                /* R0 contains the stack size passed as parameter to the
-                 * vPortAllocateSecureContext function. */
-                ulR0 = pulCallerStackAddress[ 0 ];
+            /* R0 contains the stack size passed as parameter to the
+             * vPortAllocateSecureContext function. */
+            ulR0 = pulCallerStackAddress[ 0 ];
 
-                #if ( configENABLE_MPU == 1 )
-                {
-                    /* Read the CONTROL register value. */
-                    __asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
+            #if ( configENABLE_MPU == 1 )
+            {
+                /* Read the CONTROL register value. */
+                __asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
 
-                    /* The task that raised the SVC is privileged if Bit[0]
-                     * in the CONTROL register is 0. */
-                    ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+                /* The task that raised the SVC is privileged if Bit[0]
+                 * in the CONTROL register is 0. */
+                ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
 
-                    /* Allocate and load a context for the secure task. */
-                    xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
-                }
-                #else /* if ( configENABLE_MPU == 1 ) */
-                {
-                    /* Allocate and load a context for the secure task. */
-                    xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
-                }
-                #endif /* configENABLE_MPU */
+                /* Allocate and load a context for the secure task. */
+                xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
+            }
+            #else /* if ( configENABLE_MPU == 1 ) */
+            {
+                /* Allocate and load a context for the secure task. */
+                xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
+            }
+            #endif /* configENABLE_MPU */
 
-                configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );
-                SecureContext_LoadContext( xSecureContext, pxCurrentTCB );
-                break;
+            configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );
+            SecureContext_LoadContext( xSecureContext, pxCurrentTCB );
+            break;
 
-            case portSVC_FREE_SECURE_CONTEXT:
+        case portSVC_FREE_SECURE_CONTEXT:
 
-                /* R0 contains TCB being freed and R1 contains the secure
-                 * context handle to be freed. */
-                ulR0 = pulCallerStackAddress[ 0 ];
-                ulR1 = pulCallerStackAddress[ 1 ];
+            /* R0 contains TCB being freed and R1 contains the secure
+             * context handle to be freed. */
+            ulR0 = pulCallerStackAddress[ 0 ];
+            ulR1 = pulCallerStackAddress[ 1 ];
 
-                /* Free the secure context. */
-                SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );
-                break;
-        #endif /* configENABLE_TRUSTZONE */
+            /* Free the secure context. */
+            SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );
+            break;
+    #endif /* configENABLE_TRUSTZONE */
 
         case portSVC_START_SCHEDULER:
             #if ( configENABLE_TRUSTZONE == 1 )
@@ -1174,24 +1164,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             vRestoreContextOfFirstTask();
             break;
 
-            #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
-                case portSVC_RAISE_PRIVILEGE:
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+        case portSVC_RAISE_PRIVILEGE:
 
-                    /* Only raise the privilege, if the svc was raised from any of
-                     * the system calls. */
-                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
-                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
-                    {
-                        vRaisePrivilege();
-                    }
-                    break;
-            #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+            /* Only raise the privilege, if the svc was raised from any of
+             * the system calls. */
+            if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+                ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+            {
+                vRaisePrivilege();
+            }
+            break;
+    #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
-            #if ( configENABLE_MPU == 1 )
-                case portSVC_YIELD:
-                    vPortYield();
-                    break;
-            #endif /* configENABLE_MPU == 1 */
+    #if ( configENABLE_MPU == 1 )
+        case portSVC_YIELD:
+            vPortYield();
+            break;
+    #endif /* configENABLE_MPU == 1 */
 
         default:
             /* Incorrect SVC call. */
@@ -1518,21 +1508,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
         ulIndex++;
 
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters;            /* r0. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x01010101;                           /* r1. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x02020202;                           /* r2. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x03030303;                           /* r3. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x12121212;                           /* r12. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
         ulIndex++;
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode;                  /* PC. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR;                     /* xPSR. */
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
         ulIndex++;
 
         #if ( configENABLE_TRUSTZONE == 1 )
@@ -1543,7 +1533,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         #endif /* configENABLE_TRUSTZONE */
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
         ulIndex++;
 
         #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
@@ -1615,15 +1605,15 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
          * interrupt. */
         #if ( portPRELOAD_REGISTERS == 0 )
         {
-            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
+            pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-            pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
-            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-            pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
+            pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
+            *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */
+            pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */
             *pxTopOfStack = portINITIAL_EXC_RETURN;
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
@@ -1637,42 +1627,42 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #else /* portPRELOAD_REGISTERS */
         {
-            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
+            pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
+            *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
+            *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
+            *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
+            *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
+            *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
+            *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
+            *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
+            *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
+            *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
+            *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
+            *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
+            *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04. */
             pxTopOfStack--;
-            *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
+            *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxEndOfStack;            /* Slot used to hold this task's PSPLIM value. */
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
 
             #if ( configENABLE_TRUSTZONE == 1 )
             {
diff --git a/portable/IAR/ARM_CM85/non_secure/port.c b/portable/IAR/ARM_CM85/non_secure/port.c
index b2fd7e518..a7fb054bc 100644
--- a/portable/IAR/ARM_CM85/non_secure/port.c
+++ b/portable/IAR/ARM_CM85/non_secure/port.c
@@ -145,13 +145,13 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the FPU.
  */
-#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 )              /* Coprocessor Access Control Register. */
+#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */
 #define portCPACR_CP10_VALUE    ( 3UL )
 #define portCPACR_CP11_VALUE    portCPACR_CP10_VALUE
 #define portCPACR_CP10_POS      ( 20UL )
 #define portCPACR_CP11_POS      ( 22UL )
 
-#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 )              /* Floating Point Context Control Register. */
+#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */
 #define portFPCCR_ASPEN_POS     ( 31UL )
 #define portFPCCR_ASPEN_MASK    ( 1UL << portFPCCR_ASPEN_POS )
 #define portFPCCR_LSPEN_POS     ( 30UL )
@@ -188,8 +188,8 @@ typedef void ( * portISR_t )( void );
 #define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
 #define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
 #define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
@@ -230,8 +230,8 @@ typedef void ( * portISR_t )( void );
 
 #if ( portARMV8M_MINOR_VERSION >= 1 )
 
-/* Enable Privileged eXecute Never MPU attribute for the selected memory
- * region. */
+    /* Enable Privileged eXecute Never MPU attribute for the selected memory
+     * region. */
     #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER    ( 1UL << 4UL )
 #endif /* portARMV8M_MINOR_VERSION >= 1 */
 
@@ -241,9 +241,6 @@ typedef void ( * portISR_t )( void );
 /* Enable MPU. */
 #define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
 
-/* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
-
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
 #define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \
@@ -291,37 +288,37 @@ typedef void ( * portISR_t )( void );
 
 #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
 
-/**
- * @brief Initial EXC_RETURN value.
- *
- *     FF         FF         FF         FD
- * 1111 1111  1111 1111  1111 1111  1111 1101
- *
- * Bit[6] - 1 --> The exception was taken from the Secure state.
- * Bit[5] - 1 --> Do not skip stacking of additional state context.
- * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
- * Bit[3] - 1 --> Return to the Thread mode.
- * Bit[2] - 1 --> Restore registers from the process stack.
- * Bit[1] - 0 --> Reserved, 0.
- * Bit[0] - 1 --> The exception was taken to the Secure state.
- */
+    /**
+     * @brief Initial EXC_RETURN value.
+     *
+     *     FF         FF         FF         FD
+     * 1111 1111  1111 1111  1111 1111  1111 1101
+     *
+     * Bit[6] - 1 --> The exception was taken from the Secure state.
+     * Bit[5] - 1 --> Do not skip stacking of additional state context.
+     * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+     * Bit[3] - 1 --> Return to the Thread mode.
+     * Bit[2] - 1 --> Restore registers from the process stack.
+     * Bit[1] - 0 --> Reserved, 0.
+     * Bit[0] - 1 --> The exception was taken to the Secure state.
+     */
     #define portINITIAL_EXC_RETURN    ( 0xfffffffd )
 #else
 
-/**
- * @brief Initial EXC_RETURN value.
- *
- *     FF         FF         FF         BC
- * 1111 1111  1111 1111  1111 1111  1011 1100
- *
- * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
- * Bit[5] - 1 --> Do not skip stacking of additional state context.
- * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
- * Bit[3] - 1 --> Return to the Thread mode.
- * Bit[2] - 1 --> Restore registers from the process stack.
- * Bit[1] - 0 --> Reserved, 0.
- * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
- */
+    /**
+     * @brief Initial EXC_RETURN value.
+     *
+     *     FF         FF         FF         BC
+     * 1111 1111  1111 1111  1111 1111  1011 1100
+     *
+     * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+     * Bit[5] - 1 --> Do not skip stacking of additional state context.
+     * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+     * Bit[3] - 1 --> Return to the Thread mode.
+     * Bit[2] - 1 --> Restore registers from the process stack.
+     * Bit[1] - 0 --> Reserved, 0.
+     * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+     */
     #define portINITIAL_EXC_RETURN    ( 0xffffffbc )
 #endif /* configRUN_FREERTOS_SECURE_ONLY */
 
@@ -401,49 +398,49 @@ static void prvTaskExitError( void );
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Extract MPU region's access permissions from the Region Base Address
- * Register (RBAR) value.
- *
- * @param ulRBARValue RBAR value for the MPU region.
- *
- * @return uint32_t Access permissions.
- */
+    /**
+     * @brief Extract MPU region's access permissions from the Region Base Address
+     * Register (RBAR) value.
+     *
+     * @param ulRBARValue RBAR value for the MPU region.
+     *
+     * @return uint32_t Access permissions.
+     */
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Setup the Memory Protection Unit (MPU).
- */
+    /**
+     * @brief Setup the Memory Protection Unit (MPU).
+     */
     static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_MPU */
 
 #if ( configENABLE_FPU == 1 )
 
-/**
- * @brief Setup the Floating Point Unit (FPU).
- */
+    /**
+     * @brief Setup the Floating Point Unit (FPU).
+     */
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
 #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
-/**
- * @brief Configures PACBTI features.
- *
- * This function configures the Pointer Authentication, and Branch Target
- * Identification security features as per the user configuration. It returns
- * the value of the special purpose CONTROL register accordingly, and optionally
- * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
- * architecture based) target supports PACBTI security feature.
- *
- * @param xWriteControlRegister Used to control whether the special purpose
- * CONTROL register should be updated or not.
- *
- * @return CONTROL register value according to the configured PACBTI option.
- */
+    /**
+     * @brief Configures PACBTI features.
+     *
+     * This function configures the Pointer Authentication, and Branch Target
+     * Identification security features as per the user configuration. It returns
+     * the value of the special purpose CONTROL register accordingly, and optionally
+     * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
+     * architecture based) target supports PACBTI security feature.
+     *
+     * @param xWriteControlRegister Used to control whether the special purpose
+     * CONTROL register should be updated or not.
+     *
+     * @return CONTROL register value according to the configured PACBTI option.
+     */
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
 
 #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
@@ -491,14 +488,14 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Sets up the system call stack so that upon returning from
- * SVC, the system call stack is used.
- *
- * @param pulTaskStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
- * @param ucSystemCallNumber The system call number of the system call.
- */
+    /**
+     * @brief Sets up the system call stack so that upon returning from
+     * SVC, the system call stack is used.
+     *
+     * @param pulTaskStack The current SP when the SVC was raised.
+     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+     * @param ucSystemCallNumber The system call number of the system call.
+     */
     void vSystemCallEnter( uint32_t * pulTaskStack,
                            uint32_t ulLR,
                            uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION;
@@ -507,22 +504,22 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Raise SVC for exiting from a system call.
- */
+    /**
+     * @brief Raise SVC for exiting from a system call.
+     */
     void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Sets up the task stack so that upon returning from
- * SVC, the task stack is used again.
- *
- * @param pulSystemCallStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
- */
+    /**
+     * @brief Sets up the task stack so that upon returning from
+     * SVC, the task stack is used again.
+     *
+     * @param pulSystemCallStack The current SP when the SVC was raised.
+     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+     */
     void vSystemCallExit( uint32_t * pulSystemCallStack,
                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
@@ -530,11 +527,11 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Checks whether or not the calling task is privileged.
- *
- * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
- */
+    /**
+     * @brief Checks whether or not the calling task is privileged.
+     *
+     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+     */
     BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
 
 #endif /* configENABLE_MPU == 1 */
@@ -542,9 +539,9 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief This variable is set to pdTRUE when the scheduler is started.
- */
+    /**
+     * @brief This variable is set to pdTRUE when the scheduler is started.
+     */
     PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@@ -557,10 +554,10 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-/**
- * @brief Saved as part of the task context to indicate which context the
- * task is using on the secure side.
- */
+    /**
+     * @brief Saved as part of the task context to indicate which context the
+     * task is using on the secure side.
+     */
     PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
 #endif /* configENABLE_TRUSTZONE */
 
@@ -579,21 +576,21 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
 
-/**
- * @brief The number of SysTick increments that make up one tick period.
- */
+    /**
+     * @brief The number of SysTick increments that make up one tick period.
+     */
     PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0;
 
-/**
- * @brief The maximum number of tick periods that can be suppressed is
- * limited by the 24 bit resolution of the SysTick timer.
- */
+    /**
+     * @brief The maximum number of tick periods that can be suppressed is
+     * limited by the 24 bit resolution of the SysTick timer.
+     */
     PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0;
 
-/**
- * @brief Compensate for the CPU cycles that pass while the SysTick is
- * stopped (low power functionality only).
- */
+    /**
+     * @brief Compensate for the CPU cycles that pass while the SysTick is
+     * stopped (low power functionality only).
+     */
     PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0;
 #endif /* configUSE_TICKLESS_IDLE */
 /*-----------------------------------------------------------*/
@@ -925,64 +922,57 @@ static void prvTaskExitError( void )
         /* The only permitted number of regions are 8 or 16. */
         configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
 
-        /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
-        configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
+        /* MAIR0 - Index 0. */
+        portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+        /* MAIR0 - Index 1. */
+        portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
 
-        /* Check that the MPU is present. */
-        if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
-        {
-            /* MAIR0 - Index 0. */
-            portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
-            /* MAIR0 - Index 1. */
-            portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+        /* Setup privileged flash as Read Only so that privileged tasks can
+         * read it but not modify. */
+        portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_PRIVILEGED_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup privileged flash as Read Only so that privileged tasks can
-             * read it but not modify. */
-            portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_PRIVILEGED_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup unprivileged flash as Read Only by both privileged and
+         * unprivileged tasks. All tasks can read it but no-one can modify. */
+        portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup unprivileged flash as Read Only by both privileged and
-             * unprivileged tasks. All tasks can read it but no-one can modify. */
-            portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup unprivileged syscalls flash as Read Only by both privileged
+         * and unprivileged tasks. All tasks can read it but no-one can modify. */
+        portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup unprivileged syscalls flash as Read Only by both privileged
-             * and unprivileged tasks. All tasks can read it but no-one can modify. */
-            portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup RAM containing kernel data for privileged access only. */
+        portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+                           ( portMPU_REGION_EXECUTE_NEVER );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup RAM containing kernel data for privileged access only. */
-            portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
-                               ( portMPU_REGION_EXECUTE_NEVER );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Enable mem fault. */
+        portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;
 
-            /* Enable mem fault. */
-            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;
-
-            /* Enable MPU with privileged background access i.e. unmapped
-             * regions have privileged access. */
-            portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
-        }
+        /* Enable MPU with privileged background access i.e. unmapped
+         * regions have privileged access. */
+        portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
     }
 
 #endif /* configENABLE_MPU */
@@ -1108,47 +1098,47 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
     switch( ucSVCNumber )
     {
-        #if ( configENABLE_TRUSTZONE == 1 )
-            case portSVC_ALLOCATE_SECURE_CONTEXT:
+    #if ( configENABLE_TRUSTZONE == 1 )
+        case portSVC_ALLOCATE_SECURE_CONTEXT:
 
-                /* R0 contains the stack size passed as parameter to the
-                 * vPortAllocateSecureContext function. */
-                ulR0 = pulCallerStackAddress[ 0 ];
+            /* R0 contains the stack size passed as parameter to the
+             * vPortAllocateSecureContext function. */
+            ulR0 = pulCallerStackAddress[ 0 ];
 
-                #if ( configENABLE_MPU == 1 )
-                {
-                    /* Read the CONTROL register value. */
-                    __asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
+            #if ( configENABLE_MPU == 1 )
+            {
+                /* Read the CONTROL register value. */
+                __asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
 
-                    /* The task that raised the SVC is privileged if Bit[0]
-                     * in the CONTROL register is 0. */
-                    ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+                /* The task that raised the SVC is privileged if Bit[0]
+                 * in the CONTROL register is 0. */
+                ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
 
-                    /* Allocate and load a context for the secure task. */
-                    xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
-                }
-                #else /* if ( configENABLE_MPU == 1 ) */
-                {
-                    /* Allocate and load a context for the secure task. */
-                    xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
-                }
-                #endif /* configENABLE_MPU */
+                /* Allocate and load a context for the secure task. */
+                xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
+            }
+            #else /* if ( configENABLE_MPU == 1 ) */
+            {
+                /* Allocate and load a context for the secure task. */
+                xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
+            }
+            #endif /* configENABLE_MPU */
 
-                configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );
-                SecureContext_LoadContext( xSecureContext, pxCurrentTCB );
-                break;
+            configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );
+            SecureContext_LoadContext( xSecureContext, pxCurrentTCB );
+            break;
 
-            case portSVC_FREE_SECURE_CONTEXT:
+        case portSVC_FREE_SECURE_CONTEXT:
 
-                /* R0 contains TCB being freed and R1 contains the secure
-                 * context handle to be freed. */
-                ulR0 = pulCallerStackAddress[ 0 ];
-                ulR1 = pulCallerStackAddress[ 1 ];
+            /* R0 contains TCB being freed and R1 contains the secure
+             * context handle to be freed. */
+            ulR0 = pulCallerStackAddress[ 0 ];
+            ulR1 = pulCallerStackAddress[ 1 ];
 
-                /* Free the secure context. */
-                SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );
-                break;
-        #endif /* configENABLE_TRUSTZONE */
+            /* Free the secure context. */
+            SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );
+            break;
+    #endif /* configENABLE_TRUSTZONE */
 
         case portSVC_START_SCHEDULER:
             #if ( configENABLE_TRUSTZONE == 1 )
@@ -1174,24 +1164,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             vRestoreContextOfFirstTask();
             break;
 
-            #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
-                case portSVC_RAISE_PRIVILEGE:
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+        case portSVC_RAISE_PRIVILEGE:
 
-                    /* Only raise the privilege, if the svc was raised from any of
-                     * the system calls. */
-                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
-                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
-                    {
-                        vRaisePrivilege();
-                    }
-                    break;
-            #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+            /* Only raise the privilege, if the svc was raised from any of
+             * the system calls. */
+            if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+                ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+            {
+                vRaisePrivilege();
+            }
+            break;
+    #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
-            #if ( configENABLE_MPU == 1 )
-                case portSVC_YIELD:
-                    vPortYield();
-                    break;
-            #endif /* configENABLE_MPU == 1 */
+    #if ( configENABLE_MPU == 1 )
+        case portSVC_YIELD:
+            vPortYield();
+            break;
+    #endif /* configENABLE_MPU == 1 */
 
         default:
             /* Incorrect SVC call. */
@@ -1518,21 +1508,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
         ulIndex++;
 
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters;            /* r0. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x01010101;                           /* r1. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x02020202;                           /* r2. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x03030303;                           /* r3. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x12121212;                           /* r12. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
         ulIndex++;
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode;                  /* PC. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR;                     /* xPSR. */
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
         ulIndex++;
 
         #if ( configENABLE_TRUSTZONE == 1 )
@@ -1543,7 +1533,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         #endif /* configENABLE_TRUSTZONE */
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
         ulIndex++;
 
         #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
@@ -1615,15 +1605,15 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
          * interrupt. */
         #if ( portPRELOAD_REGISTERS == 0 )
         {
-            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
+            pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-            pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
-            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-            pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
+            pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
+            *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */
+            pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */
             *pxTopOfStack = portINITIAL_EXC_RETURN;
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
@@ -1637,42 +1627,42 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #else /* portPRELOAD_REGISTERS */
         {
-            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
+            pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
+            *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
+            *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
+            *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
+            *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
+            *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
+            *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
+            *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
+            *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
+            *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
+            *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
+            *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
+            *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04. */
             pxTopOfStack--;
-            *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
+            *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxEndOfStack;            /* Slot used to hold this task's PSPLIM value. */
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
 
             #if ( configENABLE_TRUSTZONE == 1 )
             {
diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/port.c b/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
index b2fd7e518..a7fb054bc 100644
--- a/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
@@ -145,13 +145,13 @@ typedef void ( * portISR_t )( void );
 /**
  * @brief Constants required to manipulate the FPU.
  */
-#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 )              /* Coprocessor Access Control Register. */
+#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */
 #define portCPACR_CP10_VALUE    ( 3UL )
 #define portCPACR_CP11_VALUE    portCPACR_CP10_VALUE
 #define portCPACR_CP10_POS      ( 20UL )
 #define portCPACR_CP11_POS      ( 22UL )
 
-#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 )              /* Floating Point Context Control Register. */
+#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */
 #define portFPCCR_ASPEN_POS     ( 31UL )
 #define portFPCCR_ASPEN_MASK    ( 1UL << portFPCCR_ASPEN_POS )
 #define portFPCCR_LSPEN_POS     ( 30UL )
@@ -188,8 +188,8 @@ typedef void ( * portISR_t )( void );
 #define portMPU_MAIR0_REG                       ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
 #define portMPU_MAIR1_REG                       ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
 
-#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 )     /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK               ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 
 #define portMPU_RBAR_ACCESS_PERMISSIONS_MASK    ( 3UL << 1UL )
 
@@ -230,8 +230,8 @@ typedef void ( * portISR_t )( void );
 
 #if ( portARMV8M_MINOR_VERSION >= 1 )
 
-/* Enable Privileged eXecute Never MPU attribute for the selected memory
- * region. */
+    /* Enable Privileged eXecute Never MPU attribute for the selected memory
+     * region. */
     #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER    ( 1UL << 4UL )
 #endif /* portARMV8M_MINOR_VERSION >= 1 */
 
@@ -241,9 +241,6 @@ typedef void ( * portISR_t )( void );
 /* Enable MPU. */
 #define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
 
-/* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE           ( configTOTAL_MPU_REGIONS << 8UL )
-
 /* Extract first address of the MPU region as encoded in the
  * RBAR (Region Base Address Register) value. */
 #define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \
@@ -291,37 +288,37 @@ typedef void ( * portISR_t )( void );
 
 #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
 
-/**
- * @brief Initial EXC_RETURN value.
- *
- *     FF         FF         FF         FD
- * 1111 1111  1111 1111  1111 1111  1111 1101
- *
- * Bit[6] - 1 --> The exception was taken from the Secure state.
- * Bit[5] - 1 --> Do not skip stacking of additional state context.
- * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
- * Bit[3] - 1 --> Return to the Thread mode.
- * Bit[2] - 1 --> Restore registers from the process stack.
- * Bit[1] - 0 --> Reserved, 0.
- * Bit[0] - 1 --> The exception was taken to the Secure state.
- */
+    /**
+     * @brief Initial EXC_RETURN value.
+     *
+     *     FF         FF         FF         FD
+     * 1111 1111  1111 1111  1111 1111  1111 1101
+     *
+     * Bit[6] - 1 --> The exception was taken from the Secure state.
+     * Bit[5] - 1 --> Do not skip stacking of additional state context.
+     * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+     * Bit[3] - 1 --> Return to the Thread mode.
+     * Bit[2] - 1 --> Restore registers from the process stack.
+     * Bit[1] - 0 --> Reserved, 0.
+     * Bit[0] - 1 --> The exception was taken to the Secure state.
+     */
     #define portINITIAL_EXC_RETURN    ( 0xfffffffd )
 #else
 
-/**
- * @brief Initial EXC_RETURN value.
- *
- *     FF         FF         FF         BC
- * 1111 1111  1111 1111  1111 1111  1011 1100
- *
- * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
- * Bit[5] - 1 --> Do not skip stacking of additional state context.
- * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
- * Bit[3] - 1 --> Return to the Thread mode.
- * Bit[2] - 1 --> Restore registers from the process stack.
- * Bit[1] - 0 --> Reserved, 0.
- * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
- */
+    /**
+     * @brief Initial EXC_RETURN value.
+     *
+     *     FF         FF         FF         BC
+     * 1111 1111  1111 1111  1111 1111  1011 1100
+     *
+     * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+     * Bit[5] - 1 --> Do not skip stacking of additional state context.
+     * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+     * Bit[3] - 1 --> Return to the Thread mode.
+     * Bit[2] - 1 --> Restore registers from the process stack.
+     * Bit[1] - 0 --> Reserved, 0.
+     * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+     */
     #define portINITIAL_EXC_RETURN    ( 0xffffffbc )
 #endif /* configRUN_FREERTOS_SECURE_ONLY */
 
@@ -401,49 +398,49 @@ static void prvTaskExitError( void );
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Extract MPU region's access permissions from the Region Base Address
- * Register (RBAR) value.
- *
- * @param ulRBARValue RBAR value for the MPU region.
- *
- * @return uint32_t Access permissions.
- */
+    /**
+     * @brief Extract MPU region's access permissions from the Region Base Address
+     * Register (RBAR) value.
+     *
+     * @param ulRBARValue RBAR value for the MPU region.
+     *
+     * @return uint32_t Access permissions.
+     */
     static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Setup the Memory Protection Unit (MPU).
- */
+    /**
+     * @brief Setup the Memory Protection Unit (MPU).
+     */
     static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_MPU */
 
 #if ( configENABLE_FPU == 1 )
 
-/**
- * @brief Setup the Floating Point Unit (FPU).
- */
+    /**
+     * @brief Setup the Floating Point Unit (FPU).
+     */
     static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 #endif /* configENABLE_FPU */
 
 #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
 
-/**
- * @brief Configures PACBTI features.
- *
- * This function configures the Pointer Authentication, and Branch Target
- * Identification security features as per the user configuration. It returns
- * the value of the special purpose CONTROL register accordingly, and optionally
- * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
- * architecture based) target supports PACBTI security feature.
- *
- * @param xWriteControlRegister Used to control whether the special purpose
- * CONTROL register should be updated or not.
- *
- * @return CONTROL register value according to the configured PACBTI option.
- */
+    /**
+     * @brief Configures PACBTI features.
+     *
+     * This function configures the Pointer Authentication, and Branch Target
+     * Identification security features as per the user configuration. It returns
+     * the value of the special purpose CONTROL register accordingly, and optionally
+     * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
+     * architecture based) target supports PACBTI security feature.
+     *
+     * @param xWriteControlRegister Used to control whether the special purpose
+     * CONTROL register should be updated or not.
+     *
+     * @return CONTROL register value according to the configured PACBTI option.
+     */
     static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
 
 #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
@@ -491,14 +488,14 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Sets up the system call stack so that upon returning from
- * SVC, the system call stack is used.
- *
- * @param pulTaskStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
- * @param ucSystemCallNumber The system call number of the system call.
- */
+    /**
+     * @brief Sets up the system call stack so that upon returning from
+     * SVC, the system call stack is used.
+     *
+     * @param pulTaskStack The current SP when the SVC was raised.
+     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+     * @param ucSystemCallNumber The system call number of the system call.
+     */
     void vSystemCallEnter( uint32_t * pulTaskStack,
                            uint32_t ulLR,
                            uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION;
@@ -507,22 +504,22 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Raise SVC for exiting from a system call.
- */
+    /**
+     * @brief Raise SVC for exiting from a system call.
+     */
     void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief Sets up the task stack so that upon returning from
- * SVC, the task stack is used again.
- *
- * @param pulSystemCallStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
- */
+    /**
+     * @brief Sets up the task stack so that upon returning from
+     * SVC, the task stack is used again.
+     *
+     * @param pulSystemCallStack The current SP when the SVC was raised.
+     * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+     */
     void vSystemCallExit( uint32_t * pulSystemCallStack,
                           uint32_t ulLR ) PRIVILEGED_FUNCTION;
 
@@ -530,11 +527,11 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( configENABLE_MPU == 1 )
 
-/**
- * @brief Checks whether or not the calling task is privileged.
- *
- * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
- */
+    /**
+     * @brief Checks whether or not the calling task is privileged.
+     *
+     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+     */
     BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
 
 #endif /* configENABLE_MPU == 1 */
@@ -542,9 +539,9 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-/**
- * @brief This variable is set to pdTRUE when the scheduler is started.
- */
+    /**
+     * @brief This variable is set to pdTRUE when the scheduler is started.
+     */
     PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@@ -557,10 +554,10 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 
 #if ( configENABLE_TRUSTZONE == 1 )
 
-/**
- * @brief Saved as part of the task context to indicate which context the
- * task is using on the secure side.
- */
+    /**
+     * @brief Saved as part of the task context to indicate which context the
+     * task is using on the secure side.
+     */
     PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
 #endif /* configENABLE_TRUSTZONE */
 
@@ -579,21 +576,21 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 
 #if ( configUSE_TICKLESS_IDLE == 1 )
 
-/**
- * @brief The number of SysTick increments that make up one tick period.
- */
+    /**
+     * @brief The number of SysTick increments that make up one tick period.
+     */
     PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0;
 
-/**
- * @brief The maximum number of tick periods that can be suppressed is
- * limited by the 24 bit resolution of the SysTick timer.
- */
+    /**
+     * @brief The maximum number of tick periods that can be suppressed is
+     * limited by the 24 bit resolution of the SysTick timer.
+     */
     PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0;
 
-/**
- * @brief Compensate for the CPU cycles that pass while the SysTick is
- * stopped (low power functionality only).
- */
+    /**
+     * @brief Compensate for the CPU cycles that pass while the SysTick is
+     * stopped (low power functionality only).
+     */
     PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0;
 #endif /* configUSE_TICKLESS_IDLE */
 /*-----------------------------------------------------------*/
@@ -925,64 +922,57 @@ static void prvTaskExitError( void )
         /* The only permitted number of regions are 8 or 16. */
         configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
 
-        /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
-        configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
+        /* MAIR0 - Index 0. */
+        portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+        /* MAIR0 - Index 1. */
+        portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
 
-        /* Check that the MPU is present. */
-        if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
-        {
-            /* MAIR0 - Index 0. */
-            portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
-            /* MAIR0 - Index 1. */
-            portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+        /* Setup privileged flash as Read Only so that privileged tasks can
+         * read it but not modify. */
+        portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_PRIVILEGED_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup privileged flash as Read Only so that privileged tasks can
-             * read it but not modify. */
-            portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_PRIVILEGED_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup unprivileged flash as Read Only by both privileged and
+         * unprivileged tasks. All tasks can read it but no-one can modify. */
+        portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup unprivileged flash as Read Only by both privileged and
-             * unprivileged tasks. All tasks can read it but no-one can modify. */
-            portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup unprivileged syscalls flash as Read Only by both privileged
+         * and unprivileged tasks. All tasks can read it but no-one can modify. */
+        portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_READ_ONLY );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup unprivileged syscalls flash as Read Only by both privileged
-             * and unprivileged tasks. All tasks can read it but no-one can modify. */
-            portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_READ_ONLY );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Setup RAM containing kernel data for privileged access only. */
+        portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+        portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                           ( portMPU_REGION_NON_SHAREABLE ) |
+                           ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+                           ( portMPU_REGION_EXECUTE_NEVER );
+        portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                           ( portMPU_RLAR_ATTR_INDEX0 ) |
+                           ( portMPU_RLAR_REGION_ENABLE );
 
-            /* Setup RAM containing kernel data for privileged access only. */
-            portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
-            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-                               ( portMPU_REGION_NON_SHAREABLE ) |
-                               ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
-                               ( portMPU_REGION_EXECUTE_NEVER );
-            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-                               ( portMPU_RLAR_ATTR_INDEX0 ) |
-                               ( portMPU_RLAR_REGION_ENABLE );
+        /* Enable mem fault. */
+        portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;
 
-            /* Enable mem fault. */
-            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;
-
-            /* Enable MPU with privileged background access i.e. unmapped
-             * regions have privileged access. */
-            portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
-        }
+        /* Enable MPU with privileged background access i.e. unmapped
+         * regions have privileged access. */
+        portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
     }
 
 #endif /* configENABLE_MPU */
@@ -1108,47 +1098,47 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
     switch( ucSVCNumber )
     {
-        #if ( configENABLE_TRUSTZONE == 1 )
-            case portSVC_ALLOCATE_SECURE_CONTEXT:
+    #if ( configENABLE_TRUSTZONE == 1 )
+        case portSVC_ALLOCATE_SECURE_CONTEXT:
 
-                /* R0 contains the stack size passed as parameter to the
-                 * vPortAllocateSecureContext function. */
-                ulR0 = pulCallerStackAddress[ 0 ];
+            /* R0 contains the stack size passed as parameter to the
+             * vPortAllocateSecureContext function. */
+            ulR0 = pulCallerStackAddress[ 0 ];
 
-                #if ( configENABLE_MPU == 1 )
-                {
-                    /* Read the CONTROL register value. */
-                    __asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
+            #if ( configENABLE_MPU == 1 )
+            {
+                /* Read the CONTROL register value. */
+                __asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
 
-                    /* The task that raised the SVC is privileged if Bit[0]
-                     * in the CONTROL register is 0. */
-                    ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+                /* The task that raised the SVC is privileged if Bit[0]
+                 * in the CONTROL register is 0. */
+                ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
 
-                    /* Allocate and load a context for the secure task. */
-                    xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
-                }
-                #else /* if ( configENABLE_MPU == 1 ) */
-                {
-                    /* Allocate and load a context for the secure task. */
-                    xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
-                }
-                #endif /* configENABLE_MPU */
+                /* Allocate and load a context for the secure task. */
+                xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
+            }
+            #else /* if ( configENABLE_MPU == 1 ) */
+            {
+                /* Allocate and load a context for the secure task. */
+                xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
+            }
+            #endif /* configENABLE_MPU */
 
-                configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );
-                SecureContext_LoadContext( xSecureContext, pxCurrentTCB );
-                break;
+            configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );
+            SecureContext_LoadContext( xSecureContext, pxCurrentTCB );
+            break;
 
-            case portSVC_FREE_SECURE_CONTEXT:
+        case portSVC_FREE_SECURE_CONTEXT:
 
-                /* R0 contains TCB being freed and R1 contains the secure
-                 * context handle to be freed. */
-                ulR0 = pulCallerStackAddress[ 0 ];
-                ulR1 = pulCallerStackAddress[ 1 ];
+            /* R0 contains TCB being freed and R1 contains the secure
+             * context handle to be freed. */
+            ulR0 = pulCallerStackAddress[ 0 ];
+            ulR1 = pulCallerStackAddress[ 1 ];
 
-                /* Free the secure context. */
-                SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );
-                break;
-        #endif /* configENABLE_TRUSTZONE */
+            /* Free the secure context. */
+            SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );
+            break;
+    #endif /* configENABLE_TRUSTZONE */
 
         case portSVC_START_SCHEDULER:
             #if ( configENABLE_TRUSTZONE == 1 )
@@ -1174,24 +1164,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             vRestoreContextOfFirstTask();
             break;
 
-            #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
-                case portSVC_RAISE_PRIVILEGE:
+    #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+        case portSVC_RAISE_PRIVILEGE:
 
-                    /* Only raise the privilege, if the svc was raised from any of
-                     * the system calls. */
-                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
-                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
-                    {
-                        vRaisePrivilege();
-                    }
-                    break;
-            #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+            /* Only raise the privilege, if the svc was raised from any of
+             * the system calls. */
+            if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+                ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+            {
+                vRaisePrivilege();
+            }
+            break;
+    #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
 
-            #if ( configENABLE_MPU == 1 )
-                case portSVC_YIELD:
-                    vPortYield();
-                    break;
-            #endif /* configENABLE_MPU == 1 */
+    #if ( configENABLE_MPU == 1 )
+        case portSVC_YIELD:
+            vPortYield();
+            break;
+    #endif /* configENABLE_MPU == 1 */
 
         default:
             /* Incorrect SVC call. */
@@ -1518,21 +1508,21 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
         ulIndex++;
 
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters;            /* r0. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x01010101;                           /* r1. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x02020202;                           /* r2. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x03030303;                           /* r3. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = 0x12121212;                           /* r12. */
+        xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
         ulIndex++;
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode;                  /* PC. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR;                     /* xPSR. */
+        xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
         ulIndex++;
 
         #if ( configENABLE_TRUSTZONE == 1 )
@@ -1543,7 +1533,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         #endif /* configENABLE_TRUSTZONE */
         xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
         ulIndex++;
-        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack;         /* PSPLIM. */
+        xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
         ulIndex++;
 
         #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
@@ -1615,15 +1605,15 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
          * interrupt. */
         #if ( portPRELOAD_REGISTERS == 0 )
         {
-            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
+            pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
-            pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
-            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
-            pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
+            pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
+            *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */
+            pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */
             *pxTopOfStack = portINITIAL_EXC_RETURN;
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
@@ -1637,42 +1627,42 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         }
         #else /* portPRELOAD_REGISTERS */
         {
-            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR. */
+            pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC. */
+            *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
             pxTopOfStack--;
             *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12. */
+            *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3. */
+            *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2. */
+            *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1. */
+            *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0. */
+            *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11. */
+            *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10. */
+            *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09. */
+            *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08. */
+            *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07. */
+            *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06. */
+            *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05. */
+            *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04. */
+            *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04. */
             pxTopOfStack--;
-            *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN. */
+            *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */
             pxTopOfStack--;
-            *pxTopOfStack = ( StackType_t ) pxEndOfStack;            /* Slot used to hold this task's PSPLIM value. */
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
 
             #if ( configENABLE_TRUSTZONE == 1 )
             {

From 0030d609a4b99118d9a400340d88c3c3c4816f2b Mon Sep 17 00:00:00 2001
From: Jonathan Cubides <92931721+cubidesj@users.noreply.github.com>
Date: Thu, 27 Mar 2025 10:52:22 +0100
Subject: [PATCH 398/424] Add support for Vector context save support on RISC-V
 (#1260)

port: riscv: Add vector context save support
---
 .github/.cSpellWords.txt          |   4 +
 portable/GCC/RISC-V/portASM.S     |   9 ++
 portable/GCC/RISC-V/portContext.h | 136 ++++++++++++++++++++++++++++--
 3 files changed, 144 insertions(+), 5 deletions(-)

diff --git a/.github/.cSpellWords.txt b/.github/.cSpellWords.txt
index 27fb0fc33..f36fdc816 100644
--- a/.github/.cSpellWords.txt
+++ b/.github/.cSpellWords.txt
@@ -786,6 +786,7 @@ SHPR
 SHTIM
 SIFIVE
 sinclude
+slli
 SODR
 SOFTIRQ
 SPCK
@@ -937,6 +938,7 @@ USRIO
 utest
 utilises
 utilising
+vcsr
 VDDCORE
 vect
 Vect
@@ -947,6 +949,7 @@ visualisation
 vldmdbeq
 vldmia
 vldmiaeq
+vlenb
 VMSRNE
 vpop
 VPOPNE
@@ -954,6 +957,7 @@ vpush
 VPUSHNE
 VRPM
 Vrtc
+vsetvl
 vstmdbeq
 vstmiaeq
 VTOR
diff --git a/portable/GCC/RISC-V/portASM.S b/portable/GCC/RISC-V/portASM.S
index 1fe50f67c..3d1d058cd 100644
--- a/portable/GCC/RISC-V/portASM.S
+++ b/portable/GCC/RISC-V/portASM.S
@@ -192,6 +192,7 @@ definitions. */
  * x5
  * portTASK_RETURN_ADDRESS
  * [FPU registers (when enabled/available) go here]
+ * [VPU registers (when enabled/available) go here]
  * [chip specific registers go here]
  * mstatus
  * pxCode
@@ -233,6 +234,14 @@ chip_specific_stack_frame:              /* First add any chip specific registers
     or t0, t0, t1
 #endif
 
+#if( configENABLE_VPU == 1 )
+    /* Mark the VPU as clean in the mstatus value. */
+    li t1, ~MSTATUS_VS_MASK
+    and t0, t0, t1
+    li t1, MSTATUS_VS_CLEAN
+    or t0, t0, t1
+#endif
+
     addi a0, a0, -portWORD_SIZE
     store_x t0, 0(a0)                   /* mstatus onto the stack. */
 
diff --git a/portable/GCC/RISC-V/portContext.h b/portable/GCC/RISC-V/portContext.h
index aa57f3ec1..95b84dd1a 100644
--- a/portable/GCC/RISC-V/portContext.h
+++ b/portable/GCC/RISC-V/portContext.h
@@ -33,6 +33,10 @@
     #define configENABLE_FPU 0
 #endif
 
+#ifndef configENABLE_VPU
+    #define configENABLE_VPU 0
+#endif
+
 #if __riscv_xlen == 64
     #define portWORD_SIZE    8
     #define store_x          sd
@@ -90,7 +94,26 @@
         #define portFPU_REG_OFFSET( regIndex )  ( ( 2 * portWORD_SIZE ) + ( regIndex * portFPU_REG_SIZE ) )
         #define portFPU_CONTEXT_SIZE            ( portFPU_REG_SIZE * portFPU_REG_COUNT )
     #else
-        #error configENABLE_FPU must not be set to 1 if the hardwar does not have FPU
+        #error configENABLE_FPU must not be set to 1 if the hardware does not have FPU
+    #endif
+#endif
+
+#if ( configENABLE_VPU == 1 )
+    /* Bit [10:9] in the mstatus encode the status of VPU state which is one of
+     * the following values:
+     * 1. Value: 0, Meaning: Off.
+     * 2. Value: 1, Meaning: Initial.
+     * 3. Value: 2, Meaning: Clean.
+     * 4. Value: 3, Meaning: Dirty.
+     */
+    #define MSTATUS_VS_MASK                 0x600
+    #define MSTATUS_VS_INITIAL              0x200
+    #define MSTATUS_VS_CLEAN                0x400
+    #define MSTATUS_VS_DIRTY                0x600
+    #define MSTATUS_VS_OFFSET               9
+
+    #ifndef __riscv_vector
+        #error configENABLE_VPU must not be set to 1 if the hardware does not have VPU
     #endif
 #endif
 /*-----------------------------------------------------------*/
@@ -181,6 +204,72 @@ addi sp, sp, ( portFPU_CONTEXT_SIZE )
     .endm
 /*-----------------------------------------------------------*/
 
+    .macro portcontexSAVE_VPU_CONTEXT
+/* Un-reserve the space reserved for mstatus and epc. */
+add sp, sp, ( 2 * portWORD_SIZE )
+
+csrr t0, vlenb /* t0 = vlenb. vlenb is the length of each vector register in bytes. */
+slli t0, t0, 3 /* t0 = vlenb * 8. t0 now contains the space required to store 8 vector registers. */
+neg  t0, t0
+
+/* Store the vector registers in group of 8. */
+add     sp, sp, t0
+vs8r.v  v0, (sp)    /* Store v0-v7. */
+add     sp, sp, t0
+vs8r.v  v8, (sp)    /* Store v8-v15. */
+add     sp, sp, t0
+vs8r.v  v16, (sp)   /* Store v16-v23. */
+add     sp, sp, t0
+vs8r.v  v24, (sp)   /* Store v24-v31. */
+
+/* Store the VPU CSRs. */
+addi    sp, sp, -( 4 * portWORD_SIZE )
+csrr    t0, vstart
+store_x t0, 0 * portWORD_SIZE( sp )
+csrr    t0, vcsr
+store_x t0, 1 * portWORD_SIZE( sp )
+csrr    t0, vl
+store_x t0, 2 * portWORD_SIZE( sp )
+csrr    t0, vtype
+store_x t0, 3 * portWORD_SIZE( sp )
+
+/* Re-reserve the space for mstatus and epc. */
+add sp, sp, -( 2 * portWORD_SIZE )
+    .endm
+/*-----------------------------------------------------------*/
+
+    .macro portcontextRESTORE_VPU_CONTEXT
+/* Un-reserve the space reserved for mstatus and epc. */
+add sp, sp, ( 2 * portWORD_SIZE )
+
+/* Restore the VPU CSRs. */
+load_x  t0, 0  * portWORD_SIZE( sp )
+csrw    vstart, t0
+load_x  t0, 1 * portWORD_SIZE( sp )
+csrw    vcsr, t0
+load_x  t0, 2 * portWORD_SIZE( sp )
+load_x  t1, 3 * portWORD_SIZE( sp )
+vsetvl  x0, t0, t1 /* vlen and vtype can only be updated by using vset*vl* instructions. */
+addi    sp, sp, ( 4 * portWORD_SIZE )
+
+csrr t0, vlenb /* t0 = vlenb. vlenb is the length of each vector register in bytes. */
+slli t0, t0, 3 /* t0 = vlenb * 8. t0 now contains the space required to store 8 vector registers. */
+
+/* Restore the vector registers. */
+vl8r.v  v24, (sp)
+add     sp, sp, t0
+vl8r.v  v16, (sp)
+add     sp, sp, t0
+vl8r.v  v8, (sp)
+add     sp, sp, t0
+vl8r.v  v0, (sp)
+add     sp, sp, t0
+
+/* Re-reserve the space for mstatus and epc. */
+add sp, sp, -( 2 * portWORD_SIZE )
+    .endm
+/*-----------------------------------------------------------*/
+
    .macro portcontextSAVE_CONTEXT_INTERNAL
 addi sp, sp, -portCONTEXT_SIZE
 store_x x1,  2  * portWORD_SIZE( sp )
@@ -228,6 +317,17 @@ store_x t0, portCRITICAL_NESTING_OFFSET * portWORD_SIZE( sp ) /* Store the criti
 1:
 #endif
 
+#if( configENABLE_VPU == 1 )
+    csrr t0, mstatus
+    srl t1, t0, MSTATUS_VS_OFFSET
+    andi t1, t1, 3
+    addi t2, x0, 3
+    bne t1, t2, 2f /* If VPU status is not dirty, do not save FPU registers. */
+
+    portcontexSAVE_VPU_CONTEXT
+2:
+#endif
+
 portasmSAVE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to save any registers unique to the RISC-V implementation. */
 
 csrr t0, mstatus
@@ -238,14 +338,29 @@ store_x t0, 1 * portWORD_SIZE( sp )
     srl t1, t0, MSTATUS_FS_OFFSET
     andi t1, t1, 3
     addi t2, x0, 3
-    bne t1, t2, 2f
+    bne t1, t2, 3f
 
     li t1, ~MSTATUS_FS_MASK
     and t0, t0, t1
     li t1, MSTATUS_FS_CLEAN
     or t0, t0, t1
     csrw mstatus, t0
-2:
+3:
+#endif
+
+#if( configENABLE_VPU == 1 )
+    /* Mark the VPU as clean, if it was dirty and we saved VPU registers. */
+    srl t1, t0, MSTATUS_VS_OFFSET
+    andi t1, t1, 3
+    addi t2, x0, 3
+    bne t1, t2, 4f
+
+    li t1, ~MSTATUS_VS_MASK
+    and t0, t0, t1
+    li t1, MSTATUS_VS_CLEAN
+    or t0, t0, t1
+    csrw mstatus, t0
+4:
 #endif
 
 load_x t0, pxCurrentTCB          /* Load pxCurrentTCB. */
@@ -288,15 +403,26 @@ csrw mstatus, t0
 /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
 portasmRESTORE_ADDITIONAL_REGISTERS
 
+#if( configENABLE_VPU == 1 )
+    csrr t0, mstatus
+    srl t1, t0, MSTATUS_VS_OFFSET
+    andi t1, t1, 3
+    addi t2, x0, 3
+    bne t1, t2, 5f /* If VPU status is not dirty, do not restore VPU registers. */
+
+    portcontextRESTORE_VPU_CONTEXT
+5:
+#endif /* ifdef portasmSTORE_VPU_CONTEXT */
+
 #if( configENABLE_FPU == 1 )
     csrr t0, mstatus
     srl t1, t0, MSTATUS_FS_OFFSET
     andi t1, t1, 3
     addi t2, x0, 3
-    bne t1, t2, 3f /* If FPU status is not dirty, do not restore FPU registers. */
+    bne t1, t2, 6f /* If FPU status is not dirty, do not restore FPU registers. */
 
     portcontextRESTORE_FPU_CONTEXT
-3:
+6:
 #endif /* ifdef portasmSTORE_FPU_CONTEXT */
 
 load_x t0, portCRITICAL_NESTING_OFFSET * portWORD_SIZE( sp ) /* Obtain xCriticalNesting value for this task from task's stack. */

From 03db672b8f45db24aa99f12051f7cf86746b9ed9 Mon Sep 17 00:00:00 2001
From: arctic-alpaca <67190338+arctic-alpaca@users.noreply.github.com>
Date: Thu, 3 Apr 2025 11:02:44 +0200
Subject: [PATCH 399/424] Fix race in POSIX port `vPortEndScheduler` (#1262)

* Fix race in POSIX port `vPortEndScheduler`

The `vPortEndScheduler` checks whether it's a FreeRTOS thread after signalling the scheduler thread to stop. This creates a race between the check and the destruction of the thread key. By moving the signal to the scheduler thread after the check, the race is prevented.

* Code review suggestions

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 portable/ThirdParty/GCC/Posix/port.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/portable/ThirdParty/GCC/Posix/port.c b/portable/ThirdParty/GCC/Posix/port.c
index dd7ca1a9a..b5a4a1b62 100644
--- a/portable/ThirdParty/GCC/Posix/port.c
+++ b/portable/ThirdParty/GCC/Posix/port.c
@@ -48,8 +48,8 @@
 * stdio (printf() and friends) should be called from a single task
 * only or serialized with a FreeRTOS primitive such as a binary
 * semaphore or mutex.
-* 
-* Note: When using LLDB (the default debugger on macOS) with this port, 
+*
+* Note: When using LLDB (the default debugger on macOS) with this port,
 * suppress SIGUSR1 to prevent debugger interference. This can be
 * done by adding the following line to ~/.lldbinit:
 * `process handle SIGUSR1 -n true -p false -s false`
@@ -324,17 +324,23 @@ BaseType_t xPortStartScheduler( void )
 void vPortEndScheduler( void )
 {
     Thread_t * pxCurrentThread;
+    BaseType_t xIsFreeRTOSThread;
 
     /* Stop the timer tick thread. */
     xTimerTickThreadShouldRun = false;
     pthread_join( hTimerTickThread, NULL );
 
+    /* Check whether the current thread is a FreeRTOS thread.
+     * This has to happen before the scheduler is signaled to exit
+     * its loop to prevent data races on the thread key. */
+    xIsFreeRTOSThread = prvIsFreeRTOSThread();
+
     /* Signal the scheduler to exit its loop. */
     xSchedulerEnd = pdTRUE;
     ( void ) pthread_kill( hMainThread, SIG_RESUME );
 
     /* Waiting to be deleted here. */
-    if( prvIsFreeRTOSThread() == pdTRUE )
+    if( xIsFreeRTOSThread == pdTRUE )
     {
         pxCurrentThread = prvGetThreadFromTask( xTaskGetCurrentTaskHandle() );
         event_wait( pxCurrentThread->ev );

From 4ee6a1f22f0f57452217ff090d810569ab96a507 Mon Sep 17 00:00:00 2001
From: Mario Luzeiro <mrluzeiro@ua.pt>
Date: Fri, 25 Apr 2025 12:35:15 +0100
Subject: [PATCH 400/424] MPLAB PIC32MZ-EF - Adds an assert to catch register
 overflow (#1265) (#1267)

Add an assert to catch register overflow (#1265)
---
 .github/workflows/ci.yml                         | 2 +-
 .github/workflows/formatting.yml                 | 3 ++-
 .github/workflows/kernel-checks.yml              | 2 +-
 .github/workflows/unit-tests.yml                 | 2 +-
 examples/template_configuration/FreeRTOSConfig.h | 3 +++
 include/croutine.h                               | 3 +++
 portable/MPLAB/PIC32MZ/port.c                    | 5 +++++
 7 files changed, 16 insertions(+), 4 deletions(-)

diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
index edda39154..2765466be 100644
--- a/.github/workflows/ci.yml
+++ b/.github/workflows/ci.yml
@@ -7,7 +7,7 @@ on:
   workflow_dispatch:
 jobs:
   formatting:
-    runs-on: ubuntu-20.04
+    runs-on: ubuntu-latest
     steps:
       - uses: actions/checkout@v4.1.1
       - name: Check Formatting of FreeRTOS-Kernel Files
diff --git a/.github/workflows/formatting.yml b/.github/workflows/formatting.yml
index 2f369105a..811c3cb09 100644
--- a/.github/workflows/formatting.yml
+++ b/.github/workflows/formatting.yml
@@ -16,10 +16,11 @@ jobs:
     if: ${{ github.event.issue.pull_request &&
         ( ( github.event.comment.body == '/bot run uncrustify' ) ||
           ( github.event.comment.body == '/bot run formatting' ) ) }}
-    runs-on: ubuntu-20.04
+    runs-on: ubuntu-latest
     steps:
     - name: Apply Formatting Fix
       id: check-formatting
       uses: FreeRTOS/CI-CD-Github-Actions/formatting-bot@main
       with:
         exclude-dirs: portable
+          
diff --git a/.github/workflows/kernel-checks.yml b/.github/workflows/kernel-checks.yml
index ad3096f0d..05443458c 100644
--- a/.github/workflows/kernel-checks.yml
+++ b/.github/workflows/kernel-checks.yml
@@ -5,7 +5,7 @@ on: [push, pull_request]
 jobs:
   kernel-checker:
     name: FreeRTOS Kernel Header Checks
-    runs-on: ubuntu-20.04
+    runs-on: ubuntu-latest
     steps:
       # Install python 3
       - name: Tool Setup
diff --git a/.github/workflows/unit-tests.yml b/.github/workflows/unit-tests.yml
index 3591436a4..bc8aaf69c 100644
--- a/.github/workflows/unit-tests.yml
+++ b/.github/workflows/unit-tests.yml
@@ -3,7 +3,7 @@ on: [push, pull_request]
 
 jobs:
   run:
-    runs-on: ubuntu-20.04
+    runs-on: ubuntu-latest
     steps:
     - name: Checkout Parent Repository
       uses: actions/checkout@v4.1.1
diff --git a/examples/template_configuration/FreeRTOSConfig.h b/examples/template_configuration/FreeRTOSConfig.h
index 5684e3c39..5521adb4d 100644
--- a/examples/template_configuration/FreeRTOSConfig.h
+++ b/examples/template_configuration/FreeRTOSConfig.h
@@ -415,6 +415,8 @@
  * number of the failing assert (for example, "vAssertCalled( __FILE__, __LINE__
  * )" or it can simple disable interrupts and sit in a loop to halt all
  * execution on the failing line for viewing in a debugger. */
+
+/* *INDENT-OFF* */
 #define configASSERT( x )         \
     if( ( x ) == 0 )              \
     {                             \
@@ -422,6 +424,7 @@
         for( ; ; )                \
         ;                         \
     }
+/* *INDENT-ON* */
 
 /******************************************************************************/
 /* FreeRTOS MPU specific definitions. *****************************************/
diff --git a/include/croutine.h b/include/croutine.h
index 25f4caec8..a5e2e4462 100644
--- a/include/croutine.h
+++ b/include/croutine.h
@@ -246,7 +246,10 @@ void vCoRoutineSchedule( void );
  * \defgroup crSTART crSTART
  * \ingroup Tasks
  */
+
+/* *INDENT-OFF* */
 #define crEND()    }
+/* *INDENT-ON* */
 
 /*
  * These macros are intended for internal use by the co-routine implementation
diff --git a/portable/MPLAB/PIC32MZ/port.c b/portable/MPLAB/PIC32MZ/port.c
index 034fc26d1..4af1fb832 100644
--- a/portable/MPLAB/PIC32MZ/port.c
+++ b/portable/MPLAB/PIC32MZ/port.c
@@ -234,6 +234,11 @@ __attribute__(( weak )) void vApplicationSetupTickTimerInterrupt( void )
 {
 const uint32_t ulCompareMatch = ( (configPERIPHERAL_CLOCK_HZ / portTIMER_PRESCALE) / configTICK_RATE_HZ ) - 1UL;
 
+    /* PR1 is 16-bit. Ensure that the configPERIPHERAL_CLOCK_HZ and
+     * configTICK_RATE_HZ are defined such that ulCompareMatch value would fit
+     * in 16-bits. */
+    configASSERT( ( ulCompareMatch & 0xFFFF0000 ) == 0 );
+
     T1CON = 0x0000;
     T1CONbits.TCKPS = portPRESCALE_BITS;
     PR1 = ulCompareMatch;

From d03233f209adb6149c2880e3068833a07c2cbbd8 Mon Sep 17 00:00:00 2001
From: Florian La Roche <florian.laroche@gmail.com>
Date: Mon, 28 Apr 2025 06:21:58 +0200
Subject: [PATCH 401/424] fix warnings from "gcc -Wconversion" (#1271)

fix warnings from "gcc -Wconversion"

Signed-off-by: Florian La Roche <Florian.LaRoche@gmail.com>
---
 portable/Common/mpu_wrappers_v2.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/portable/Common/mpu_wrappers_v2.c b/portable/Common/mpu_wrappers_v2.c
index e92aca0f5..9f9fa43ea 100644
--- a/portable/Common/mpu_wrappers_v2.c
+++ b/portable/Common/mpu_wrappers_v2.c
@@ -1059,8 +1059,8 @@
                                                   configRUN_TIME_COUNTER_TYPE * pulTotalRunTime ) /* PRIVILEGED_FUNCTION */
         {
             UBaseType_t uxReturn = 0;
-            UBaseType_t xIsTaskStatusArrayWriteable = pdFALSE;
-            UBaseType_t xIsTotalRunTimeWriteable = pdFALSE;
+            BaseType_t xIsTaskStatusArrayWriteable = pdFALSE;
+            BaseType_t xIsTotalRunTimeWriteable = pdFALSE;
             uint32_t ulArraySize = ( uint32_t ) uxArraySize;
             uint32_t ulTaskStatusSize = ( uint32_t ) sizeof( TaskStatus_t );
 

From 4162ca49d6aa1bdef940e09b71c28b51779db523 Mon Sep 17 00:00:00 2001
From: Matth9814 <125400975+Matth9814@users.noreply.github.com>
Date: Wed, 30 Apr 2025 09:42:08 +0200
Subject: [PATCH 402/424] FreeRTOS SMP: direct access to current TCB inside
 stack macros (#1270)

FreeRTOS SMP: direct access to current TCB inside stack macros
---
 include/stack_macros.h | 105 +++++++++++++++++++++++++++++++++++++++--
 tasks.c                |   2 +-
 2 files changed, 101 insertions(+), 6 deletions(-)

diff --git a/include/stack_macros.h b/include/stack_macros.h
index 6d0117722..8bf0720c9 100644
--- a/include/stack_macros.h
+++ b/include/stack_macros.h
@@ -66,8 +66,10 @@
  */
 #if ( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH < 0 ) && ( portUSING_MPU_WRAPPERS != 1 ) )
 
+    #if ( configNUMBER_OF_CORES == 1 )
+
 /* Only the current stack state is to be checked. */
-    #define taskCHECK_FOR_STACK_OVERFLOW()                                                      \
+        #define taskCHECK_FOR_STACK_OVERFLOW()                                                  \
     do                                                                                          \
     {                                                                                           \
         /* Is the currently saved stack pointer within the stack limit? */                      \
@@ -78,13 +80,33 @@
         }                                                                                       \
     } while( 0 )
 
+    #else /* if ( configNUMBER_OF_CORES == 1 ) */
+
+/* Only the current stack state is to be checked. */
+        #define taskCHECK_FOR_STACK_OVERFLOW( xCoreID )                                  \
+    do                                                                                   \
+    {                                                                                    \
+        TCB_t * pxTCB = pxCurrentTCBs[ xCoreID ];                                        \
+                                                                                         \
+        /* Is the currently saved stack pointer within the stack limit? */               \
+        if( pxTCB->pxTopOfStack <= pxTCB->pxStack + portSTACK_LIMIT_PADDING )            \
+        {                                                                                \
+            char * pcOverflowTaskName = pxTCB->pcTaskName;                               \
+            vApplicationStackOverflowHook( ( TaskHandle_t ) pxTCB, pcOverflowTaskName ); \
+        }                                                                                \
+    } while( 0 )
+
+    #endif /* if ( configNUMBER_OF_CORES == 1 ) */
+
 #endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
 /*-----------------------------------------------------------*/
 
 #if ( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH > 0 ) && ( portUSING_MPU_WRAPPERS != 1 ) )
 
+    #if ( configNUMBER_OF_CORES == 1 )
+
 /* Only the current stack state is to be checked. */
-    #define taskCHECK_FOR_STACK_OVERFLOW()                                                       \
+        #define taskCHECK_FOR_STACK_OVERFLOW()                                                   \
     do                                                                                           \
     {                                                                                            \
         /* Is the currently saved stack pointer within the stack limit? */                       \
@@ -95,12 +117,32 @@
         }                                                                                        \
     } while( 0 )
 
+    #else /* if ( configNUMBER_OF_CORES == 1 ) */
+
+/* Only the current stack state is to be checked. */
+        #define taskCHECK_FOR_STACK_OVERFLOW( xCoreID )                                  \
+    do                                                                                   \
+    {                                                                                    \
+        TCB_t * pxTCB = pxCurrentTCBs[ xCoreID ];                                        \
+                                                                                         \
+        /* Is the currently saved stack pointer within the stack limit? */               \
+        if( pxTCB->pxTopOfStack >= pxTCB->pxEndOfStack - portSTACK_LIMIT_PADDING )       \
+        {                                                                                \
+            char * pcOverflowTaskName = pxTCB->pcTaskName;                               \
+            vApplicationStackOverflowHook( ( TaskHandle_t ) pxTCB, pcOverflowTaskName ); \
+        }                                                                                \
+    } while( 0 )
+
+    #endif /* if ( configNUMBER_OF_CORES == 1 ) */
+
 #endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
 /*-----------------------------------------------------------*/
 
 #if ( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) && ( portUSING_MPU_WRAPPERS != 1 ) )
 
-    #define taskCHECK_FOR_STACK_OVERFLOW()                                                       \
+    #if ( configNUMBER_OF_CORES == 1 )
+
+        #define taskCHECK_FOR_STACK_OVERFLOW()                                                   \
     do                                                                                           \
     {                                                                                            \
         const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack;                  \
@@ -117,12 +159,36 @@
         }                                                                                        \
     } while( 0 )
 
+    #else /* if ( configNUMBER_OF_CORES == 1 ) */
+
+        #define taskCHECK_FOR_STACK_OVERFLOW( xCoreID )                                  \
+    do                                                                                   \
+    {                                                                                    \
+        TCB_t * pxTCB = pxCurrentTCBs[ xCoreID ];                                        \
+        const uint32_t * const pulStack = ( uint32_t * ) pxTCB->pxStack;                 \
+        const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5U;                          \
+                                                                                         \
+        if( ( pxTCB->pxTopOfStack <= pxTCB->pxStack + portSTACK_LIMIT_PADDING ) ||       \
+            ( pulStack[ 0 ] != ulCheckValue ) ||                                         \
+            ( pulStack[ 1 ] != ulCheckValue ) ||                                         \
+            ( pulStack[ 2 ] != ulCheckValue ) ||                                         \
+            ( pulStack[ 3 ] != ulCheckValue ) )                                          \
+        {                                                                                \
+            char * pcOverflowTaskName = pxTCB->pcTaskName;                               \
+            vApplicationStackOverflowHook( ( TaskHandle_t ) pxTCB, pcOverflowTaskName ); \
+        }                                                                                \
+    } while( 0 )
+
+    #endif /* if ( configNUMBER_OF_CORES == 1 ) */
+
 #endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
 /*-----------------------------------------------------------*/
 
 #if ( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) && ( portUSING_MPU_WRAPPERS != 1 ) )
 
-    #define taskCHECK_FOR_STACK_OVERFLOW()                                                                                                \
+    #if ( configNUMBER_OF_CORES == 1 )
+
+        #define taskCHECK_FOR_STACK_OVERFLOW()                                                                                            \
     do                                                                                                                                    \
     {                                                                                                                                     \
         int8_t * pcEndOfStack = ( int8_t * ) pxCurrentTCB->pxEndOfStack;                                                                  \
@@ -142,12 +208,41 @@
         }                                                                                                                                 \
     } while( 0 )
 
+    #else /* if ( configNUMBER_OF_CORES == 1 ) */
+
+        #define taskCHECK_FOR_STACK_OVERFLOW( xCoreID )                                                                                   \
+    do                                                                                                                                    \
+    {                                                                                                                                     \
+        TCB_t * pxTCB = pxCurrentTCBs[ xCoreID ];                                                                                         \
+        int8_t * pcEndOfStack = ( int8_t * ) pxTCB->pxEndOfStack;                                                                         \
+        static const uint8_t ucExpectedStackBytes[] = { tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,   \
+                                                        tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,   \
+                                                        tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,   \
+                                                        tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,   \
+                                                        tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE }; \
+                                                                                                                                          \
+        pcEndOfStack -= sizeof( ucExpectedStackBytes );                                                                                   \
+                                                                                                                                          \
+        if( ( pxTCB->pxTopOfStack >= pxTCB->pxEndOfStack - portSTACK_LIMIT_PADDING ) ||                                                   \
+            ( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 ) )                 \
+        {                                                                                                                                 \
+            char * pcOverflowTaskName = pxTCB->pcTaskName;                                                                                \
+            vApplicationStackOverflowHook( ( TaskHandle_t ) pxTCB, pcOverflowTaskName );                                                  \
+        }                                                                                                                                 \
+    } while( 0 )
+
+    #endif /* if ( configNUMBER_OF_CORES == 1 ) */
+
 #endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
 /*-----------------------------------------------------------*/
 
 /* Remove stack overflow macro if not being used. */
 #ifndef taskCHECK_FOR_STACK_OVERFLOW
-    #define taskCHECK_FOR_STACK_OVERFLOW()
+    #if ( configNUMBER_OF_CORES == 1 )
+        #define taskCHECK_FOR_STACK_OVERFLOW()
+    #else
+        #define taskCHECK_FOR_STACK_OVERFLOW( xCoreID )
+    #endif
 #endif
 
 
diff --git a/tasks.c b/tasks.c
index 24cfb2620..e5d2c97c9 100644
--- a/tasks.c
+++ b/tasks.c
@@ -5251,7 +5251,7 @@ BaseType_t xTaskIncrementTick( void )
                 #endif /* configGENERATE_RUN_TIME_STATS */
 
                 /* Check for stack overflow, if configured. */
-                taskCHECK_FOR_STACK_OVERFLOW();
+                taskCHECK_FOR_STACK_OVERFLOW( xCoreID );
 
                 /* Before the currently running task is switched out, save its errno. */
                 #if ( configUSE_POSIX_ERRNO == 1 )

From e3a0e3e86aa196b4b2e76b851fe152f426f091f7 Mon Sep 17 00:00:00 2001
From: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Date: Mon, 5 May 2025 15:45:15 +0530
Subject: [PATCH 403/424] Revert "FreeRTOS SMP: direct access to current TCB
 inside stack macros (#1270)" (#1272)

This reverts commit 4162ca49d6aa1bdef940e09b71c28b51779db523.
---
 include/stack_macros.h | 105 ++---------------------------------------
 tasks.c                |   2 +-
 2 files changed, 6 insertions(+), 101 deletions(-)

diff --git a/include/stack_macros.h b/include/stack_macros.h
index 8bf0720c9..6d0117722 100644
--- a/include/stack_macros.h
+++ b/include/stack_macros.h
@@ -66,10 +66,8 @@
  */
 #if ( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH < 0 ) && ( portUSING_MPU_WRAPPERS != 1 ) )
 
-    #if ( configNUMBER_OF_CORES == 1 )
-
 /* Only the current stack state is to be checked. */
-        #define taskCHECK_FOR_STACK_OVERFLOW()                                                  \
+    #define taskCHECK_FOR_STACK_OVERFLOW()                                                      \
     do                                                                                          \
     {                                                                                           \
         /* Is the currently saved stack pointer within the stack limit? */                      \
@@ -80,33 +78,13 @@
         }                                                                                       \
     } while( 0 )
 
-    #else /* if ( configNUMBER_OF_CORES == 1 ) */
-
-/* Only the current stack state is to be checked. */
-        #define taskCHECK_FOR_STACK_OVERFLOW( xCoreID )                                  \
-    do                                                                                   \
-    {                                                                                    \
-        TCB_t * pxTCB = pxCurrentTCBs[ xCoreID ];                                        \
-                                                                                         \
-        /* Is the currently saved stack pointer within the stack limit? */               \
-        if( pxTCB->pxTopOfStack <= pxTCB->pxStack + portSTACK_LIMIT_PADDING )            \
-        {                                                                                \
-            char * pcOverflowTaskName = pxTCB->pcTaskName;                               \
-            vApplicationStackOverflowHook( ( TaskHandle_t ) pxTCB, pcOverflowTaskName ); \
-        }                                                                                \
-    } while( 0 )
-
-    #endif /* if ( configNUMBER_OF_CORES == 1 ) */
-
 #endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
 /*-----------------------------------------------------------*/
 
 #if ( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH > 0 ) && ( portUSING_MPU_WRAPPERS != 1 ) )
 
-    #if ( configNUMBER_OF_CORES == 1 )
-
 /* Only the current stack state is to be checked. */
-        #define taskCHECK_FOR_STACK_OVERFLOW()                                                   \
+    #define taskCHECK_FOR_STACK_OVERFLOW()                                                       \
     do                                                                                           \
     {                                                                                            \
         /* Is the currently saved stack pointer within the stack limit? */                       \
@@ -117,32 +95,12 @@
         }                                                                                        \
     } while( 0 )
 
-    #else /* if ( configNUMBER_OF_CORES == 1 ) */
-
-/* Only the current stack state is to be checked. */
-        #define taskCHECK_FOR_STACK_OVERFLOW( xCoreID )                                  \
-    do                                                                                   \
-    {                                                                                    \
-        TCB_t * pxTCB = pxCurrentTCBs[ xCoreID ];                                        \
-                                                                                         \
-        /* Is the currently saved stack pointer within the stack limit? */               \
-        if( pxTCB->pxTopOfStack >= pxTCB->pxEndOfStack - portSTACK_LIMIT_PADDING )       \
-        {                                                                                \
-            char * pcOverflowTaskName = pxTCB->pcTaskName;                               \
-            vApplicationStackOverflowHook( ( TaskHandle_t ) pxTCB, pcOverflowTaskName ); \
-        }                                                                                \
-    } while( 0 )
-
-    #endif /* if ( configNUMBER_OF_CORES == 1 ) */
-
 #endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
 /*-----------------------------------------------------------*/
 
 #if ( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) && ( portUSING_MPU_WRAPPERS != 1 ) )
 
-    #if ( configNUMBER_OF_CORES == 1 )
-
-        #define taskCHECK_FOR_STACK_OVERFLOW()                                                   \
+    #define taskCHECK_FOR_STACK_OVERFLOW()                                                       \
     do                                                                                           \
     {                                                                                            \
         const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack;                  \
@@ -159,36 +117,12 @@
         }                                                                                        \
     } while( 0 )
 
-    #else /* if ( configNUMBER_OF_CORES == 1 ) */
-
-        #define taskCHECK_FOR_STACK_OVERFLOW( xCoreID )                                  \
-    do                                                                                   \
-    {                                                                                    \
-        TCB_t * pxTCB = pxCurrentTCBs[ xCoreID ];                                        \
-        const uint32_t * const pulStack = ( uint32_t * ) pxTCB->pxStack;                 \
-        const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5U;                          \
-                                                                                         \
-        if( ( pxTCB->pxTopOfStack <= pxTCB->pxStack + portSTACK_LIMIT_PADDING ) ||       \
-            ( pulStack[ 0 ] != ulCheckValue ) ||                                         \
-            ( pulStack[ 1 ] != ulCheckValue ) ||                                         \
-            ( pulStack[ 2 ] != ulCheckValue ) ||                                         \
-            ( pulStack[ 3 ] != ulCheckValue ) )                                          \
-        {                                                                                \
-            char * pcOverflowTaskName = pxTCB->pcTaskName;                               \
-            vApplicationStackOverflowHook( ( TaskHandle_t ) pxTCB, pcOverflowTaskName ); \
-        }                                                                                \
-    } while( 0 )
-
-    #endif /* if ( configNUMBER_OF_CORES == 1 ) */
-
 #endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
 /*-----------------------------------------------------------*/
 
 #if ( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) && ( portUSING_MPU_WRAPPERS != 1 ) )
 
-    #if ( configNUMBER_OF_CORES == 1 )
-
-        #define taskCHECK_FOR_STACK_OVERFLOW()                                                                                            \
+    #define taskCHECK_FOR_STACK_OVERFLOW()                                                                                                \
     do                                                                                                                                    \
     {                                                                                                                                     \
         int8_t * pcEndOfStack = ( int8_t * ) pxCurrentTCB->pxEndOfStack;                                                                  \
@@ -208,41 +142,12 @@
         }                                                                                                                                 \
     } while( 0 )
 
-    #else /* if ( configNUMBER_OF_CORES == 1 ) */
-
-        #define taskCHECK_FOR_STACK_OVERFLOW( xCoreID )                                                                                   \
-    do                                                                                                                                    \
-    {                                                                                                                                     \
-        TCB_t * pxTCB = pxCurrentTCBs[ xCoreID ];                                                                                         \
-        int8_t * pcEndOfStack = ( int8_t * ) pxTCB->pxEndOfStack;                                                                         \
-        static const uint8_t ucExpectedStackBytes[] = { tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,   \
-                                                        tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,   \
-                                                        tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,   \
-                                                        tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,   \
-                                                        tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE }; \
-                                                                                                                                          \
-        pcEndOfStack -= sizeof( ucExpectedStackBytes );                                                                                   \
-                                                                                                                                          \
-        if( ( pxTCB->pxTopOfStack >= pxTCB->pxEndOfStack - portSTACK_LIMIT_PADDING ) ||                                                   \
-            ( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 ) )                 \
-        {                                                                                                                                 \
-            char * pcOverflowTaskName = pxTCB->pcTaskName;                                                                                \
-            vApplicationStackOverflowHook( ( TaskHandle_t ) pxTCB, pcOverflowTaskName );                                                  \
-        }                                                                                                                                 \
-    } while( 0 )
-
-    #endif /* if ( configNUMBER_OF_CORES == 1 ) */
-
 #endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
 /*-----------------------------------------------------------*/
 
 /* Remove stack overflow macro if not being used. */
 #ifndef taskCHECK_FOR_STACK_OVERFLOW
-    #if ( configNUMBER_OF_CORES == 1 )
-        #define taskCHECK_FOR_STACK_OVERFLOW()
-    #else
-        #define taskCHECK_FOR_STACK_OVERFLOW( xCoreID )
-    #endif
+    #define taskCHECK_FOR_STACK_OVERFLOW()
 #endif
 
 
diff --git a/tasks.c b/tasks.c
index e5d2c97c9..24cfb2620 100644
--- a/tasks.c
+++ b/tasks.c
@@ -5251,7 +5251,7 @@ BaseType_t xTaskIncrementTick( void )
                 #endif /* configGENERATE_RUN_TIME_STATS */
 
                 /* Check for stack overflow, if configured. */
-                taskCHECK_FOR_STACK_OVERFLOW( xCoreID );
+                taskCHECK_FOR_STACK_OVERFLOW();
 
                 /* Before the currently running task is switched out, save its errno. */
                 #if ( configUSE_POSIX_ERRNO == 1 )

From 03dc002c9bd72578ef4714d38477c18952a1fd52 Mon Sep 17 00:00:00 2001
From: Archit Gupta <archigup@amazon.com>
Date: Fri, 9 May 2025 14:09:08 -0700
Subject: [PATCH 404/424] Remove formatting bot workflow (#1274)

---
 .github/workflows/formatting.yml | 26 --------------------------
 1 file changed, 26 deletions(-)
 delete mode 100644 .github/workflows/formatting.yml

diff --git a/.github/workflows/formatting.yml b/.github/workflows/formatting.yml
deleted file mode 100644
index 811c3cb09..000000000
--- a/.github/workflows/formatting.yml
+++ /dev/null
@@ -1,26 +0,0 @@
-name: Format Pull Request Files
-
-on:
-  issue_comment:
-    types: [created]
-
-env:
-  bashPass: \033[32;1mPASSED -
-  bashInfo: \033[33;1mINFO -
-  bashFail: \033[31;1mFAILED -
-  bashEnd:  \033[0m
-
-jobs:
-  Formatting:
-    name: Run Formatting Check
-    if: ${{ github.event.issue.pull_request &&
-        ( ( github.event.comment.body == '/bot run uncrustify' ) ||
-          ( github.event.comment.body == '/bot run formatting' ) ) }}
-    runs-on: ubuntu-latest
-    steps:
-    - name: Apply Formatting Fix
-      id: check-formatting
-      uses: FreeRTOS/CI-CD-Github-Actions/formatting-bot@main
-      with:
-        exclude-dirs: portable
-          

From 2615dcde13d953dbe60ae1ee0cf9312458984c3a Mon Sep 17 00:00:00 2001
From: Simon Brizard <135690956+5iBri@users.noreply.github.com>
Date: Mon, 12 May 2025 17:50:46 +0200
Subject: [PATCH 405/424] fix[IAR/RL78 Port] Compilation fails on portasm.s
 file (#1278)

The indentation on ASM macro is not authorized by IAR compiler
---
 portable/IAR/RL78/portmacro.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/portable/IAR/RL78/portmacro.h b/portable/IAR/RL78/portmacro.h
index 544e76e9e..36697a620 100644
--- a/portable/IAR/RL78/portmacro.h
+++ b/portable/IAR/RL78/portmacro.h
@@ -187,7 +187,7 @@
               * ; * memory mode) registers the _usCriticalNesting value and the Stack Pointer
               * ; * of the active Task onto the task stack.
               * ; *---------------------------------------------------------------------------*/
-    portSAVE_CONTEXT MACRO
+portSAVE_CONTEXT MACRO
     PUSH AX; /* Save AX Register to stack. */
     PUSH HL
     #if  __CODE_MODEL__ == __CODE_MODEL_FAR__
@@ -217,7 +217,7 @@
  * ; * general purpose registers and the CS and ES (only in __far memory mode)
  * ; * of the selected task from the task stack.
  * ; *---------------------------------------------------------------------------*/
-    portRESTORE_CONTEXT MACRO
+portRESTORE_CONTEXT MACRO
     MOVW AX, _pxCurrentTCB; /* Restore the Task stack pointer. */
     MOVW HL, AX
     MOVW AX, [ HL ]

From 62bd622ffc49008f8e7e7c74d9086a8a1a95a416 Mon Sep 17 00:00:00 2001
From: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
Date: Thu, 5 Jun 2025 23:23:47 +0530
Subject: [PATCH 406/424] Update download locations to outside repository
 content (#1280)

Update curl command to download in a non user accessible folder
---
 .github/workflows/coverity_scan.yml       | 19 +++++++--
 .github/workflows/kernel-demos.yml        | 51 +++++++++++++++--------
 portable/ThirdParty/GCC/ARM_TFM/README.md |  4 +-
 3 files changed, 50 insertions(+), 24 deletions(-)

diff --git a/.github/workflows/coverity_scan.yml b/.github/workflows/coverity_scan.yml
index 803a29ba8..0afc8e2e1 100644
--- a/.github/workflows/coverity_scan.yml
+++ b/.github/workflows/coverity_scan.yml
@@ -42,11 +42,22 @@ jobs:
           # ${{ env.stepName }}
           echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}"
 
-          wget -nv -qO- https://scan.coverity.com/download/linux64 --post-data "token=${COVERITY_TOKEN}&project=FreeRTOS-Kernel" | tar -zx --one-top-level=cov_scan --strip-components 1
-          echo "cov_scan_path=$(pwd)/cov_scan/bin" >> $GITHUB_ENV
+          wget -nv -q -O "$HOME/cov-analysis.tar.gz" https://scan.coverity.com/download/linux64 --post-data="token=${COVERITY_TOKEN}&project=FreeRTOS-Kernel"
+          
+          EXPECTED_MD5="e4418004b073140d67390cffba79c3b2"
+          GENERATED_MD5=$(md5sum "$HOME/cov-analysis.tar.gz" | awk '{print $1}')
 
-          echo "::endgroup::"
-          echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }} "
+          if [ "$GENERATED_MD5" = "$EXPECTED_MD5" ]; then
+            tar -zxf "$HOME/cov-analysis.tar.gz" --one-top-level=cov_scan -C "$HOME"            
+            echo "cov_scan_path=$HOME/cov_scan/bin" >> $GITHUB_ENV
+            sudo rm -f "$HOME/cov-analysis.tar.gz"
+            echo "::endgroup::"
+            echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }} "
+          else
+            echo -e "${{ env.bashFail }} MD5 checksum verification failed for cov-analysis.tar.gz ${{ env.bashEnd }}"
+            echo -e "${{ env.bashFail }} ${{ env.stepName }} ${{ env.bashEnd }}"
+            exit -1            
+          fi
 
       - env:
           stepName: Coverity Build
diff --git a/.github/workflows/kernel-demos.yml b/.github/workflows/kernel-demos.yml
index 404c602b5..9371e9cea 100644
--- a/.github/workflows/kernel-demos.yml
+++ b/.github/workflows/kernel-demos.yml
@@ -156,14 +156,27 @@ jobs:
         run: |
           # ${{ env.stepName }}
           echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}"
-          curl -L -O https://dr-download.ti.com/software-development/ide-configuration-compiler-or-debugger/MD-LlCjWuAbzH/9.3.1.2/msp430-gcc-full-linux-x64-installer-9.3.1.2.7z
           sudo apt update -y
           sudo apt install -y p7zip-full
-          7z x ./msp430-gcc-full-linux-x64-installer-9.3.1.2.7z
-          chmod +x ./msp430-gcc-full-linux-x64-installer-9.3.1.2.run
-          sudo ./msp430-gcc-full-linux-x64-installer-9.3.1.2.run --prefix /usr/bin/msp430-gcc --mode unattended
-          echo "::endgroup::"
-          echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }}"
+          pushd $HOME
+          curl -L -o msp430-gcc-full-linux-x64-installer-9.3.1.2.7z https://dr-download.ti.com/software-development/ide-configuration-compiler-or-debugger/MD-LlCjWuAbzH/9.3.1.2/msp430-gcc-full-linux-x64-installer-9.3.1.2.7z
+          
+          EXPECTED_MD5="2db2f99b4cd5c541ca0389ee20c67527"
+          GENERATED_MD5=$(md5sum msp430-gcc-full-linux-x64-installer-9.3.1.2.7z | awk '{print $1}')
+
+          if [ "$GENERATED_MD5" = "$EXPECTED_MD5" ]; then          
+            7z x ./msp430-gcc-full-linux-x64-installer-9.3.1.2.7z
+            chmod +x ./msp430-gcc-full-linux-x64-installer-9.3.1.2.run
+            sudo ./msp430-gcc-full-linux-x64-installer-9.3.1.2.run --prefix /usr/bin/msp430-gcc --mode unattended
+            echo "::endgroup::"
+            popd
+            echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }}"
+          else
+            popd
+            echo -e "${{ env.bashFail }} MD5 checksum verification failed for msp430-gcc-full-linux-x64-installer-9.3.1.2.7z ${{ env.bashEnd }}"
+            echo -e "${{ env.bashFail }} ${{ env.stepName }} ${{ env.bashEnd }}"
+            exit -1
+          fi
 
       - name: Build msp430_GCC Demo
         shell: bash
@@ -211,21 +224,23 @@ jobs:
           sudo apt install -y autogen gawk libgmp-dev libmpc-dev libmpfr-dev
           sudo apt install -y patchutils sharutils zlib1g-dev autoconf2.64
 
+          pushd $HOME
           # Download the mb-gcc toolchain from github
-          curl -L -O https://github.com/mdednev/mb-gcc/releases/download/2021-0623%2B2/binutils-microblaze_2.35-2021-0623+1_amd64.deb;
-          curl -L -O https://github.com/mdednev/mb-gcc/releases/download/2021-0623%2B2/gcc-microblaze_10.2.0-2021-0623+2_amd64.deb;
-          curl -L -O https://github.com/mdednev/mb-gcc/releases/download/2021-0623%2B2/libnewlib-microblaze-dev_3.3.0-2021-0623+3_all.deb;
-          curl -L -O https://github.com/mdednev/mb-gcc/releases/download/2021-0623%2B2/libnewlib-microblaze-doc_3.3.0-2021-0623+3_all.deb;
-          curl -L -O https://github.com/mdednev/mb-gcc/releases/download/2021-0623%2B2/libnewlib-microblaze_3.3.0-2021-0623+3_all.deb;
-          curl -L -O https://github.com/mdednev/mb-gcc/releases/download/2021-0623%2B2/newlib-source_3.3.0-2021-0623+3_all.deb;
+          curl -L -o binutils-microblaze.deb https://github.com/mdednev/mb-gcc/releases/download/2021-0623%2B2/binutils-microblaze_2.35-2021-0623+1_amd64.deb;
+          curl -L -o gcc-microblaze.deb https://github.com/mdednev/mb-gcc/releases/download/2021-0623%2B2/gcc-microblaze_10.2.0-2021-0623+2_amd64.deb;
+          curl -L -o libnewlib-microblaze-dev.deb https://github.com/mdednev/mb-gcc/releases/download/2021-0623%2B2/libnewlib-microblaze-dev_3.3.0-2021-0623+3_all.deb;
+          curl -L -o libnewlib-microblaze-doc.deb https://github.com/mdednev/mb-gcc/releases/download/2021-0623%2B2/libnewlib-microblaze-doc_3.3.0-2021-0623+3_all.deb;
+          curl -L -o libnewlib-microblaze.deb https://github.com/mdednev/mb-gcc/releases/download/2021-0623%2B2/libnewlib-microblaze_3.3.0-2021-0623+3_all.deb;
+          curl -L -o newlib-source.deb https://github.com/mdednev/mb-gcc/releases/download/2021-0623%2B2/newlib-source_3.3.0-2021-0623+3_all.deb;
+          popd
 
           # Install the packages for the toolchain
-          sudo apt install -y ./binutils-microblaze*.deb;
-          sudo apt install -y ./gcc-microblaze*.deb;
-          sudo apt install -y ./libnewlib-microblaze-dev*.deb;
-          sudo apt install -y ./libnewlib-microblaze-doc*.deb;
-          sudo apt install -y ./libnewlib-microblaze*.deb;
-          sudo apt install -y ./newlib-source*.deb;
+          sudo apt install -y $HOME/binutils-microblaze.deb;
+          sudo apt install -y $HOME/gcc-microblaze.deb;
+          sudo apt install -y $HOME/libnewlib-microblaze-dev.deb;
+          sudo apt install -y $HOME/libnewlib-microblaze-doc.deb;
+          sudo apt install -y $HOME/libnewlib-microblaze.deb;
+          sudo apt install -y $HOME/newlib-source.deb;
 
           # Validate that the toolchain is in the path and can be called
           which mb-gcc
diff --git a/portable/ThirdParty/GCC/ARM_TFM/README.md b/portable/ThirdParty/GCC/ARM_TFM/README.md
index 7df149f54..bc594b156 100644
--- a/portable/ThirdParty/GCC/ARM_TFM/README.md
+++ b/portable/ThirdParty/GCC/ARM_TFM/README.md
@@ -52,13 +52,13 @@ Kernel runs in the Non-Secure Side.
 The setting of this macro is decided by the setting in Secure Side which is platform-specific.
 If the Secure Side enables Non-Secure access to FPU, then this macro can be configured as 0 or 1. Otherwise, this macro can only be configured as 0.
 Please note that Cortex-M23 does not support FPU.
-Please refer to [TF-M documentation](https://tf-m-user-guide.trustedfirmware.org/integration_guide/tfm_fpu_support.html) for FPU usage on the Non-Secure side.
+Please refer to [TF-M documentation](https://trustedfirmware-m.readthedocs.io/en/latest/integration_guide/tfm_fpu_support.html) for FPU usage on the Non-Secure side.
 
 * `configENABLE_MVE`
 The setting of this macro is decided by the setting in Secure Side which is platform-specific.
 If the Secure Side enables Non-Secure access to MVE, then this macro can be configured as 0 or 1. Otherwise, this macro can only be configured as 0.
 Please note that only Cortex-M55 and Cortex-M85 support MVE.
-Please refer to [TF-M documentation](https://tf-m-user-guide.trustedfirmware.org/integration_guide/tfm_fpu_support.html) for MVE usage on the Non-Secure side.
+Please refer to [TF-M documentation](https://trustedfirmware-m.readthedocs.io/en/latest/integration_guide/tfm_fpu_support.html) for MVE usage on the Non-Secure side.
 
 * `configENABLE_TRUSTZONE`
 This macro should be configured as 0 because TF-M doesn't use the secure context management function of FreeRTOS. New secure context management might be introduced when TF-M supports multiple secure context.

From 0ae0715ac9cdca3527f29285a89b911462d874ba Mon Sep 17 00:00:00 2001
From: Dakshit Babbar <100972343+DakshitBabbar@users.noreply.github.com>
Date: Mon, 16 Jun 2025 20:39:05 +0530
Subject: [PATCH 407/424] Update codecov badge url (#1283)

---
 README.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/README.md b/README.md
index a6d383add..b4e87ce3b 100644
--- a/README.md
+++ b/README.md
@@ -1,5 +1,5 @@
 [![CMock Unit Tests](https://github.com/FreeRTOS/FreeRTOS-Kernel/actions/workflows/unit-tests.yml/badge.svg?branch=main&event=push)](https://github.com/FreeRTOS/FreeRTOS-Kernel/actions/workflows/unit-tests.yml?query=branch%3Amain+event%3Apush+workflow%3A%22CMock+Unit+Tests%22++)
-[![codecov](https://codecov.io/gh/FreeRTOS/FreeRTOS-Kernel/badge.svg?branch=main)](https://codecov.io/gh/FreeRTOS/FreeRTOS-Kernel)
+[![codecov](https://app.codecov.io/gh/FreeRTOS/FreeRTOS-Kernel/badge.svg?branch=main)](https://codecov.io/gh/FreeRTOS/FreeRTOS-Kernel)
 
 ## Getting started
 

From a882b105263c1fe53b1386fe17cb8b3ec90a388c Mon Sep 17 00:00:00 2001
From: Florian La Roche <florian.laroche@gmail.com>
Date: Mon, 30 Jun 2025 08:35:46 +0200
Subject: [PATCH 408/424] fix possible NULL pointer dereference after call to
 configASSERT() (#1284)

Compiling with clang static code analysis, possible NULL pointer
dereference are found. Since configASSERT() can possibly return
and continue "normal" operation, the code in queue.c and
stream_buffer.c can be adjusted to avoid NULL pointer exceptions.

Signed-off-by: Florian La Roche <Florian.LaRoche@gmail.com>
---
 queue.c         | 23 ++++++++---------------
 stream_buffer.c |  6 ++----
 2 files changed, 10 insertions(+), 19 deletions(-)

diff --git a/queue.c b/queue.c
index fe06368d3..a967839de 100644
--- a/queue.c
+++ b/queue.c
@@ -1175,9 +1175,8 @@ BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue,
 
     traceENTER_xQueueGenericSendFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken, xCopyPosition );
 
-    configASSERT( pxQueue );
-    configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
-    configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
+    configASSERT( ( pxQueue != NULL ) && !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+    configASSERT( ( pxQueue != NULL ) && !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
 
     /* RTOS ports that support interrupt nesting have the concept of a maximum
      * system call (or maximum API call) interrupt priority.  Interrupts that are
@@ -1351,16 +1350,14 @@ BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue,
      * not (i.e. has a task with a higher priority than us been woken by this
      * post). */
 
-    configASSERT( pxQueue );
-
     /* xQueueGenericSendFromISR() should be used instead of xQueueGiveFromISR()
      * if the item size is not 0. */
-    configASSERT( pxQueue->uxItemSize == 0 );
+    configASSERT( ( pxQueue != NULL ) && ( pxQueue->uxItemSize == 0 ) );
 
     /* Normally a mutex would not be given from an interrupt, especially if
      * there is a mutex holder, as priority inheritance makes no sense for an
-     * interrupts, only tasks. */
-    configASSERT( !( ( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) && ( pxQueue->u.xSemaphore.xMutexHolder != NULL ) ) );
+     * interrupt, only tasks. */
+    configASSERT( ( pxQueue != NULL ) && !( ( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) && ( pxQueue->u.xSemaphore.xMutexHolder != NULL ) ) );
 
     /* RTOS ports that support interrupt nesting have the concept of a maximum
      * system call (or maximum API call) interrupt priority.  Interrupts that are
@@ -1895,12 +1892,9 @@ BaseType_t xQueuePeek( QueueHandle_t xQueue,
 
     traceENTER_xQueuePeek( xQueue, pvBuffer, xTicksToWait );
 
-    /* Check the pointer is not NULL. */
-    configASSERT( ( pxQueue ) );
-
     /* The buffer into which data is received can only be NULL if the data size
      * is zero (so no data is copied into the buffer. */
-    configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );
+    configASSERT( ( pxQueue != NULL ) && !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );
 
     /* Cannot block if the scheduler is suspended. */
     #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
@@ -2152,9 +2146,8 @@ BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue,
 
     traceENTER_xQueuePeekFromISR( xQueue, pvBuffer );
 
-    configASSERT( pxQueue );
-    configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
-    configASSERT( pxQueue->uxItemSize != 0 ); /* Can't peek a semaphore. */
+    configASSERT( ( pxQueue != NULL ) && !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+    configASSERT( ( pxQueue != NULL ) && ( pxQueue->uxItemSize != 0 ) ); /* Can't peek a semaphore. */
 
     /* RTOS ports that support interrupt nesting have the concept of a maximum
      * system call (or maximum API call) interrupt priority.  Interrupts that are
diff --git a/stream_buffer.c b/stream_buffer.c
index b1f9c0d57..4f13c679b 100644
--- a/stream_buffer.c
+++ b/stream_buffer.c
@@ -1653,11 +1653,9 @@ void vStreamBufferSetStreamBufferNotificationIndex( StreamBufferHandle_t xStream
 
     traceENTER_vStreamBufferSetStreamBufferNotificationIndex( xStreamBuffer, uxNotificationIndex );
 
-    configASSERT( pxStreamBuffer );
-
     /* There should be no task waiting otherwise we'd never resume them. */
-    configASSERT( pxStreamBuffer->xTaskWaitingToReceive == NULL );
-    configASSERT( pxStreamBuffer->xTaskWaitingToSend == NULL );
+    configASSERT( ( pxStreamBuffer != NULL ) && ( pxStreamBuffer->xTaskWaitingToReceive == NULL ) );
+    configASSERT( ( pxStreamBuffer != NULL ) && ( pxStreamBuffer->xTaskWaitingToSend == NULL ) );
 
     /* Check that the task notification index is valid. */
     configASSERT( uxNotificationIndex < configTASK_NOTIFICATION_ARRAY_ENTRIES );

From 7225fbcbb94b945555beabfde42f756127b5a42c Mon Sep 17 00:00:00 2001
From: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Date: Mon, 30 Jun 2025 18:11:30 +0530
Subject: [PATCH 409/424] Fix datatype of queue item length macros (#1286)

The uxItemSize parameter in xQueueGenericCreate and
xQueueGeneenericCreateStatic APIs expects a UBaseType_t type.
Previously, the semSEMAPHORE_QUEUE_ITEM_LENGTH macro incorrectly cast
the value to uint8_t, causing type mismatch warnings. This change
resolves the issue by properly casting the value to UBaseType_t.

This issue was reported here: https://github.com/FreeRTOS/FreeRTOS-Kernel/issues/1285.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 include/semphr.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/semphr.h b/include/semphr.h
index 8977acadb..7b44d78c0 100644
--- a/include/semphr.h
+++ b/include/semphr.h
@@ -37,8 +37,8 @@
 
 typedef QueueHandle_t SemaphoreHandle_t;
 
-#define semBINARY_SEMAPHORE_QUEUE_LENGTH    ( ( uint8_t ) 1U )
-#define semSEMAPHORE_QUEUE_ITEM_LENGTH      ( ( uint8_t ) 0U )
+#define semBINARY_SEMAPHORE_QUEUE_LENGTH    ( ( UBaseType_t ) 1U )
+#define semSEMAPHORE_QUEUE_ITEM_LENGTH      ( ( UBaseType_t ) 0U )
 #define semGIVE_BLOCK_TIME                  ( ( TickType_t ) 0U )
 
 

From e3a362b1d1e41bcc02c02f3ef05f4d3b30cbbc17 Mon Sep 17 00:00:00 2001
From: Aniruddha Kanhere <60444055+AniruddhaKanhere@users.noreply.github.com>
Date: Mon, 7 Jul 2025 05:45:46 -0700
Subject: [PATCH 410/424] Add artifact backup action (#1290)

---
 .github/workflows/auto-release.yml | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/.github/workflows/auto-release.yml b/.github/workflows/auto-release.yml
index 3477f6591..19f6c0167 100644
--- a/.github/workflows/auto-release.yml
+++ b/.github/workflows/auto-release.yml
@@ -18,6 +18,8 @@ on:
 
 jobs:
   release-packager:
+    permissions:
+      id-token: write
     name: Release Packager
     runs-on: ubuntu-latest
     steps:
@@ -117,6 +119,14 @@ jobs:
           ./tools/.github/scripts/release.py "$REPO_OWNER" --kernel-repo-path=local_kernel --kernel-commit="$COMMIT_SHA_2" --new-kernel-version="$VERSION_NUMBER" --new-kernel-main-br-version="$MAIN_BR_VERSION_NUMBER"
           exit $?
 
+      - name: Backup Release Asset
+        uses: FreeRTOS/CI-CD-Github-Actions/artifact-backup@main
+        with:
+          # This is dependent on the release script putting this zip file
+          # in this exact location.
+          artifact_path: ./tools/.github/scripts/FreeRTOS-KernelV${{ github.event.inputs.version_number }}.zip
+          release_tag: ${{ github.event.inputs.version_number }}
+
       - name: Cleanup
         env:
           VERSION_NUMBER: ${{ github.event.inputs.version_number }}

From 48a4939c9f86aee414042962a1776dd99a09348f Mon Sep 17 00:00:00 2001
From: Florian La Roche <florian.laroche@gmail.com>
Date: Wed, 9 Jul 2025 07:46:00 +0200
Subject: [PATCH 411/424] Fix compiler warning (#1291)

- In list.h fix a typo in comments.
- In portable/ThirdParty/GCC/Posix/port.c fix compiler warning about
  "gcc -Wwrite-strings".

Signed-off-by: Florian La Roche <Florian.LaRoche@gmail.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
---
 include/list.h                       | 2 +-
 portable/ThirdParty/GCC/Posix/port.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/list.h b/include/list.h
index b64450c72..b6e0d34f4 100644
--- a/include/list.h
+++ b/include/list.h
@@ -44,7 +44,7 @@
  *
  * In addition to it's value, each list item contains a pointer to the next
  * item in the list (pxNext), a pointer to the list it is in (pxContainer)
- * and a pointer to back to the object that contains it.  These later two
+ * and a pointer back to the object that contains it.  These later two
  * pointers are included for efficiency of list manipulation.  There is
  * effectively a two way link between the object containing the list item and
  * the list item itself.
diff --git a/portable/ThirdParty/GCC/Posix/port.c b/portable/ThirdParty/GCC/Posix/port.c
index b5a4a1b62..d0b81dc1e 100644
--- a/portable/ThirdParty/GCC/Posix/port.c
+++ b/portable/ThirdParty/GCC/Posix/port.c
@@ -193,7 +193,7 @@ void prvFatalError( const char * pcCall,
 }
 /*-----------------------------------------------------------*/
 
-static void prvPortSetCurrentThreadName( char * pxThreadName )
+static void prvPortSetCurrentThreadName( const char * pxThreadName )
 {
     #ifdef __APPLE__
         pthread_setname_np( pxThreadName );

From f5e6151b1433227ca0afe2e1ec6cca6b31b7014c Mon Sep 17 00:00:00 2001
From: Aniruddha Kanhere <60444055+AniruddhaKanhere@users.noreply.github.com>
Date: Wed, 9 Jul 2025 09:53:13 -0700
Subject: [PATCH 412/424] Update artifact path in the backup action (#1292)

* Add artifact backup action

* Fix artifact path
---
 .github/workflows/auto-release.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.github/workflows/auto-release.yml b/.github/workflows/auto-release.yml
index 19f6c0167..2cd6fde6e 100644
--- a/.github/workflows/auto-release.yml
+++ b/.github/workflows/auto-release.yml
@@ -124,7 +124,7 @@ jobs:
         with:
           # This is dependent on the release script putting this zip file
           # in this exact location.
-          artifact_path: ./tools/.github/scripts/FreeRTOS-KernelV${{ github.event.inputs.version_number }}.zip
+          artifact_path: ./FreeRTOS-KernelV${{ github.event.inputs.version_number }}.zip
           release_tag: ${{ github.event.inputs.version_number }}
 
       - name: Cleanup

From 684b34ca8db0de1277b9b5359e0d1d822b53b6a2 Mon Sep 17 00:00:00 2001
From: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Date: Mon, 14 Jul 2025 16:20:18 +0530
Subject: [PATCH 413/424] Define security extension configs before portable.h
 (#1294)

Define configENABLE_PAC and configENABLE_BTI before including portable.h
to prevent "used before definition" warnings when these macros are not
set in FreeRTOSConfig.h.

Fixes: https://github.com/FreeRTOS/FreeRTOS-Kernel/issues/1293

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 include/FreeRTOS.h | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/include/FreeRTOS.h b/include/FreeRTOS.h
index ce8530e7d..63e2feb51 100644
--- a/include/FreeRTOS.h
+++ b/include/FreeRTOS.h
@@ -101,6 +101,16 @@
     #define configASSERT_DEFINED    1
 #endif
 
+/* Set configENABLE_PAC and/or configENABLE_BTI to 1 to enable PAC and/or BTI
+ * support and 0 to disable them. These are currently used in ARMv8.1-M ports. */
+#ifndef configENABLE_PAC
+    #define configENABLE_PAC    0
+#endif
+
+#ifndef configENABLE_BTI
+    #define configENABLE_BTI    0
+#endif
+
 /* Basic FreeRTOS definitions. */
 #include "projdefs.h"
 
@@ -3040,16 +3050,6 @@
     #define configCONTROL_INFINITE_LOOP()
 #endif
 
-/* Set configENABLE_PAC and/or configENABLE_BTI to 1 to enable PAC and/or BTI
- * support and 0 to disable them. These are currently used in ARMv8.1-M ports. */
-#ifndef configENABLE_PAC
-    #define configENABLE_PAC    0
-#endif
-
-#ifndef configENABLE_BTI
-    #define configENABLE_BTI    0
-#endif
-
 /* Sometimes the FreeRTOSConfig.h settings only allow a task to be created using
  * dynamically allocated RAM, in which case when any task is deleted it is known
  * that both the task's stack and TCB need to be freed.  Sometimes the

From 32e581636f66504daa1a76afcc766be2a4b8a9de Mon Sep 17 00:00:00 2001
From: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Date: Thu, 24 Jul 2025 11:07:27 +0530
Subject: [PATCH 414/424] Delete thread key on process exit (#1297)

Previously, the shared thread key was deleted in xPortStartScheduler
after scheduler was ended. This created a race condition where
prvThreadKeyDestructor (responsible for freeing thread-specific heap
memory) would not be called if xPortStartScheduler deleted the key
before the last task deletion, as destructors are not invoked after key
deletion (see https://github.com/walac/glibc/blob/master/nptl/pthread_create.c#L145-L150).

Move thread key deletion to process exit to ensure all thread-specific
memory is properly freed.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 portable/ThirdParty/GCC/Posix/port.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/portable/ThirdParty/GCC/Posix/port.c b/portable/ThirdParty/GCC/Posix/port.c
index d0b81dc1e..2342f6034 100644
--- a/portable/ThirdParty/GCC/Posix/port.c
+++ b/portable/ThirdParty/GCC/Posix/port.c
@@ -140,6 +140,8 @@ static void prvThreadKeyDestructor( void * pvData )
 static void prvInitThreadKey( void )
 {
     pthread_key_create( &xThreadKey, prvThreadKeyDestructor );
+    /* Destroy xThreadKey when the process exits. */
+    atexit( prvDestroyThreadKey );
 }
 /*-----------------------------------------------------------*/
 
@@ -315,8 +317,6 @@ BaseType_t xPortStartScheduler( void )
     /* Restore original signal mask. */
     ( void ) pthread_sigmask( SIG_SETMASK, &xSchedulerOriginalSignalMask, NULL );
 
-    prvDestroyThreadKey();
-
     return 0;
 }
 /*-----------------------------------------------------------*/

From 2da35debfda2a41a8b5b5b5154458d596e8ea4d2 Mon Sep 17 00:00:00 2001
From: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Date: Thu, 31 Jul 2025 08:02:23 +0530
Subject: [PATCH 415/424] Add missing cast to BaseType_t (#1301)

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 tasks.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tasks.c b/tasks.c
index 24cfb2620..1e6ecdc9e 100644
--- a/tasks.c
+++ b/tasks.c
@@ -893,7 +893,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
         BaseType_t xCurrentCoreTaskPriority;
         BaseType_t xLowestPriorityCore = ( BaseType_t ) -1;
         BaseType_t xCoreID;
-        const BaseType_t xCurrentCoreID = portGET_CORE_ID();
+        const BaseType_t xCurrentCoreID = ( BaseType_t ) portGET_CORE_ID();
 
         #if ( configRUN_MULTIPLE_PRIORITIES == 0 )
             BaseType_t xYieldCount = 0;

From c5bec0e4b2c65034189f7dc05eac559a438c6546 Mon Sep 17 00:00:00 2001
From: "Dennis Lambe Jr." <malsyned_github@malsyned.net>
Date: Tue, 5 Aug 2025 06:32:03 -0400
Subject: [PATCH 416/424] LLVM assembler compatibility for ARM_CRx_MPU (#1303)

GNU as makes unrecognized sections loadable and writable by default, but
LLVM's assembler requires specifying flags explicitly. Without them, the
linker generates "has non-ABS relocation" errors when trying to link the
resulting object files.
---
 portable/GCC/ARM_CRx_MPU/mpu_wrappers_v2_asm.S | 2 +-
 portable/GCC/ARM_CRx_MPU/portASM.S             | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/portable/GCC/ARM_CRx_MPU/mpu_wrappers_v2_asm.S b/portable/GCC/ARM_CRx_MPU/mpu_wrappers_v2_asm.S
index 142486adf..caf31ff76 100644
--- a/portable/GCC/ARM_CRx_MPU/mpu_wrappers_v2_asm.S
+++ b/portable/GCC/ARM_CRx_MPU/mpu_wrappers_v2_asm.S
@@ -30,7 +30,7 @@
 
     .arm
     .syntax unified
-    .section freertos_system_calls
+    .section freertos_system_calls, "ax"
 
 #define FREERTOS_ASSEMBLY
     #include "FreeRTOSConfig.h"
diff --git a/portable/GCC/ARM_CRx_MPU/portASM.S b/portable/GCC/ARM_CRx_MPU/portASM.S
index bc0345a80..2b6f22ef2 100644
--- a/portable/GCC/ARM_CRx_MPU/portASM.S
+++ b/portable/GCC/ARM_CRx_MPU/portASM.S
@@ -28,7 +28,7 @@
 
     .arm
     .syntax unified
-    .section privileged_functions
+    .section privileged_functions, "ax"
 
 #define FREERTOS_ASSEMBLY
     #include "portmacro_asm.h"

From e9440d4079894e0d6c52ce80e4c79fc072743d9d Mon Sep 17 00:00:00 2001
From: creiter64 <106512497+creiter64@users.noreply.github.com>
Date: Tue, 5 Aug 2025 13:11:54 +0200
Subject: [PATCH 417/424] Move windows headers to port.c (#1302)

* [MSVC-MingW] Move windows headers to port.c

This prevents the inclusion of windows.h. into all header files using
FreeRTOS.h and thus defining several macros conflicting with common
definitions.

* [MSVC-MingW] Include correct header for compiler intrinsics

---------

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
---
 portable/MSVC-MingW/port.c      |  8 ++++++++
 portable/MSVC-MingW/portmacro.h | 18 +++++-------------
 2 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/portable/MSVC-MingW/port.c b/portable/MSVC-MingW/port.c
index 9ce0c1b15..74dd777ef 100644
--- a/portable/MSVC-MingW/port.c
+++ b/portable/MSVC-MingW/port.c
@@ -33,6 +33,14 @@
 #include "FreeRTOS.h"
 #include "task.h"
 
+#ifdef WIN32_LEAN_AND_MEAN
+    #include <winsock2.h>
+#else
+    #include <winsock.h>
+#endif
+
+#include <timeapi.h>
+
 #ifdef __GNUC__
     #include "mmsystem.h"
 #else
diff --git a/portable/MSVC-MingW/portmacro.h b/portable/MSVC-MingW/portmacro.h
index eb94758be..37bfb2586 100644
--- a/portable/MSVC-MingW/portmacro.h
+++ b/portable/MSVC-MingW/portmacro.h
@@ -29,17 +29,6 @@
 #ifndef PORTMACRO_H
 #define PORTMACRO_H
 
-#ifdef WIN32_LEAN_AND_MEAN
-    #include <winsock2.h>
-#else
-    #include <winsock.h>
-#endif
-
-#include <windows.h>
-#include <timeapi.h>
-#include <mmsystem.h>
-#include <winbase.h>
-
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -156,22 +145,25 @@ void vPortExitCritical( void );
                          : "cc" )
 
     #else /* __GNUC__ */
+        #include <intrin.h>
 
         /* BitScanReverse returns the bit position of the most significant '1'
          * in the word. */
         #if defined( __x86_64__ ) || defined( _M_X64 )
+            #pragma intrinsic(_BitScanReverse64)
 
             #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    \
             do                                                                      \
             {                                                                       \
-                DWORD ulTopPriority;                                                \
+                unsigned long ulTopPriority;                                        \
                 _BitScanReverse64( &ulTopPriority, ( uxReadyPriorities ) );         \
                 uxTopPriority = ulTopPriority;                                      \
             } while( 0 )
 
         #else /* #if defined( __x86_64__ ) || defined( _M_X64 ) */
+            #pragma intrinsic(_BitScanReverse)
 
-            #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    _BitScanReverse( ( DWORD * ) &( uxTopPriority ), ( uxReadyPriorities ) )
+            #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    _BitScanReverse( ( unsigned long * ) &( uxTopPriority ), ( uxReadyPriorities ) )
 
         #endif /* #if defined( __x86_64__ ) || defined( _M_X64 ) */
 

From c91ee8d7242949f5666ec8855ad4a8065fefdbe2 Mon Sep 17 00:00:00 2001
From: "Dennis Lambe Jr." <malsyned@malsyned.net>
Date: Thu, 14 Aug 2025 01:05:53 -0400
Subject: [PATCH 418/424] Fix CMake build for GCC_ARM_CRx_MPU (#1308) (#1309)

Add GCC_ARM_CRX_MPU to the set of FREERTOS_PORT patterns that trigger
adding mpu_wrappers.c and mpu_wrappers_v2.c to freertos_kernel_port
target_sources.
---
 portable/CMakeLists.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/portable/CMakeLists.txt b/portable/CMakeLists.txt
index 5e43877bb..53b6f58d6 100644
--- a/portable/CMakeLists.txt
+++ b/portable/CMakeLists.txt
@@ -769,6 +769,7 @@ add_library(freertos_kernel_port OBJECT
 if( FREERTOS_PORT MATCHES "GCC_ARM_CM(3|4)_MPU" OR
     FREERTOS_PORT STREQUAL "IAR_ARM_CM4F_MPU" OR
     FREERTOS_PORT STREQUAL "RVDS_ARM_CM4_MPU" OR
+    FREERTOS_PORT STREQUAL "GCC_ARM_CRX_MPU" OR
     FREERTOS_PORT MATCHES "GCC_ARM_CM(23|33|55|85)_NTZ_NONSECURE" OR
     FREERTOS_PORT MATCHES "GCC_ARM_CM(23|33|55|85)_NONSECURE" OR
     FREERTOS_PORT MATCHES "GCC_ARM_CM(33|55|85)_TFM" OR

From 43947413b9411ab47afd36b5979af37f348123f2 Mon Sep 17 00:00:00 2001
From: Ahmed Ismail <64546783+AhmedIsmail02@users.noreply.github.com>
Date: Thu, 14 Aug 2025 18:40:59 +0100
Subject: [PATCH 419/424] event-groups: Fix multiple definitions (#1307)

This commit does the following:
* Remove xEventGroupClearBitsFromISR and
xEventGroupSetBitsFromISR functions direct mapping
to xTimerPendFunctionCallFromISR in case the trace
facility is feature not set. This should match the
current implementation in which the application calling
xEventGroupClearBitsFromISR
without defining the trace macros
(i.e. traceENTER_xEventGroupClearBitsFromISR is
a blank function in this case) will end up calling
xTimerPendFunctionCallFromISR function directly.
This enhances the readability of the code by not
guarding the xEventGroup<Set/Clear>BitsFromISR
functions' declaration and definition based on
the trace facility macro (i.e. configUSE_TRACE_FACILITY).

* Refactor the guarding macros for MPU_xEventGroupClearBitsFromISR
and MPU_xEventGroupSetBitsFromISR functions to match the
change above.

The current implementation leads to redefinition warnings
as `event_groups.h`redefines xEventGroupClearBitsFromISR
and xEventGroupSetBitsFromISR based on
`configUSE_TRACE_FACILITY' after they have been defined based
on configUSE_MPU_WRAPPERS_V1 in `mpu_wrappers.h`. The
implemented changes should resolve these warnings.

Signed-off-by: Ahmed Ismail <Ahmed.Ismail@arm.com>
---
 event_groups.c                    |  8 ++++----
 include/event_groups.h            | 14 ++++----------
 include/mpu_prototypes.h          | 13 ++++++++-----
 portable/Common/mpu_wrappers_v2.c |  8 ++++----
 4 files changed, 20 insertions(+), 23 deletions(-)

diff --git a/event_groups.c b/event_groups.c
index 6a2ba0761..1923bf78d 100644
--- a/event_groups.c
+++ b/event_groups.c
@@ -501,7 +501,7 @@
     }
 /*-----------------------------------------------------------*/
 
-    #if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
+    #if ( ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
 
         BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup,
                                                 const EventBits_t uxBitsToClear )
@@ -518,7 +518,7 @@
             return xReturn;
         }
 
-    #endif /* if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) */
+    #endif /* if ( ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) */
 /*-----------------------------------------------------------*/
 
     EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup )
@@ -812,7 +812,7 @@
     }
 /*-----------------------------------------------------------*/
 
-    #if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
+    #if ( ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
 
         BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup,
                                               const EventBits_t uxBitsToSet,
@@ -830,7 +830,7 @@
             return xReturn;
         }
 
-    #endif /* if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) */
+    #endif /* if ( ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) */
 /*-----------------------------------------------------------*/
 
     #if ( configUSE_TRACE_FACILITY == 1 )
diff --git a/include/event_groups.h b/include/event_groups.h
index 9e6348687..d42c87b28 100644
--- a/include/event_groups.h
+++ b/include/event_groups.h
@@ -452,13 +452,10 @@ EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup,
  * \defgroup xEventGroupClearBitsFromISR xEventGroupClearBitsFromISR
  * \ingroup EventGroup
  */
-#if ( configUSE_TRACE_FACILITY == 1 )
+#if ( ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
     BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup,
                                             const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION;
-#else
-    #define xEventGroupClearBitsFromISR( xEventGroup, uxBitsToClear ) \
-    xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) ( xEventGroup ), ( uint32_t ) ( uxBitsToClear ), NULL )
-#endif
+#endif /* if ( ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) */
 
 /**
  * event_groups.h
@@ -607,14 +604,11 @@ EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup,
  * \defgroup xEventGroupSetBitsFromISR xEventGroupSetBitsFromISR
  * \ingroup EventGroup
  */
-#if ( configUSE_TRACE_FACILITY == 1 )
+#if ( ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
     BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup,
                                           const EventBits_t uxBitsToSet,
                                           BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
-#else
-    #define xEventGroupSetBitsFromISR( xEventGroup, uxBitsToSet, pxHigherPriorityTaskWoken ) \
-    xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) ( xEventGroup ), ( uint32_t ) ( uxBitsToSet ), ( pxHigherPriorityTaskWoken ) )
-#endif
+#endif /* if ( ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) */
 
 /**
  * event_groups.h
diff --git a/include/mpu_prototypes.h b/include/mpu_prototypes.h
index 9df2a5762..b4c0f4745 100644
--- a/include/mpu_prototypes.h
+++ b/include/mpu_prototypes.h
@@ -409,13 +409,16 @@ EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
 
 BaseType_t MPU_xEventGroupGetStaticBuffer( EventGroupHandle_t xEventGroup,
                                            StaticEventGroup_t ** ppxEventGroupBuffer ) PRIVILEGED_FUNCTION;
-BaseType_t MPU_xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup,
-                                            const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION;
-BaseType_t MPU_xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup,
-                                          const EventBits_t uxBitsToSet,
-                                          BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
 EventBits_t MPU_xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION;
 
+#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+    BaseType_t MPU_xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup,
+                                                const EventBits_t uxBitsToClear ) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup,
+                                              const EventBits_t uxBitsToSet,
+                                              BaseType_t * pxHigherPriorityTaskWoken ) FREERTOS_SYSTEM_CALL;
+#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+
 /* MPU versions of message/stream_buffer.h API functions. */
 size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
                               const void * pvTxData,
diff --git a/portable/Common/mpu_wrappers_v2.c b/portable/Common/mpu_wrappers_v2.c
index 9f9fa43ea..70082b829 100644
--- a/portable/Common/mpu_wrappers_v2.c
+++ b/portable/Common/mpu_wrappers_v2.c
@@ -4282,7 +4282,7 @@
     #endif /* #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_EVENT_GROUPS == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-    #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
+    #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
 
         BaseType_t MPU_xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup,
                                                     const EventBits_t uxBitsToClear ) /* PRIVILEGED_FUNCTION */
@@ -4306,10 +4306,10 @@
             return xReturn;
         }
 
-    #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) */
+    #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) */
 /*-----------------------------------------------------------*/
 
-    #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
+    #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
 
         BaseType_t MPU_xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup,
                                                   const EventBits_t uxBitsToSet,
@@ -4334,7 +4334,7 @@
             return xReturn;
         }
 
-    #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) */
+    #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) */
 /*-----------------------------------------------------------*/
 
     #if ( configUSE_EVENT_GROUPS == 1 )

From 386c1bca661e70045a65365fe9525d1119d93086 Mon Sep 17 00:00:00 2001
From: DuYicheng <duyicheng741@outlook.com>
Date: Fri, 15 Aug 2025 15:07:23 +0800
Subject: [PATCH 420/424] Change the macro from portMAX_DELAY to SIZE_MAX in
 order to initialize size_t-type variable correctly (#1310)

---
 portable/MemMang/heap_4.c | 2 +-
 portable/MemMang/heap_5.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/portable/MemMang/heap_4.c b/portable/MemMang/heap_4.c
index acb334757..50af15dfb 100644
--- a/portable/MemMang/heap_4.c
+++ b/portable/MemMang/heap_4.c
@@ -572,7 +572,7 @@ static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) /* PRIVI
 void vPortGetHeapStats( HeapStats_t * pxHeapStats )
 {
     BlockLink_t * pxBlock;
-    size_t xBlocks = 0, xMaxSize = 0, xMinSize = portMAX_DELAY; /* portMAX_DELAY used as a portable way of getting the maximum value. */
+    size_t xBlocks = 0, xMaxSize = 0, xMinSize = SIZE_MAX;
 
     vTaskSuspendAll();
     {
diff --git a/portable/MemMang/heap_5.c b/portable/MemMang/heap_5.c
index 4e872f615..bf321304f 100644
--- a/portable/MemMang/heap_5.c
+++ b/portable/MemMang/heap_5.c
@@ -672,7 +672,7 @@ void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions ) /* PRIVI
 void vPortGetHeapStats( HeapStats_t * pxHeapStats )
 {
     BlockLink_t * pxBlock;
-    size_t xBlocks = 0, xMaxSize = 0, xMinSize = portMAX_DELAY; /* portMAX_DELAY used as a portable way of getting the maximum value. */
+    size_t xBlocks = 0, xMaxSize = 0, xMinSize = SIZE_MAX;
 
     vTaskSuspendAll();
     {

From ccabdec2f8c2cb8c7740e018546a53a3e6e0ef22 Mon Sep 17 00:00:00 2001
From: Kim Lindberg Schwaner <kim.schwaner@gmail.com>
Date: Fri, 15 Aug 2025 20:09:28 +0200
Subject: [PATCH 421/424] Fix risk of Win32 timer setup call getting ignored
 (#1311)

If a user configures the configASSERT macro to expand to nothing,
a call to the Win32 API SetWaitableTimer() doesn't get compiled.

This can happen if, for example, configASSERT(x) set defined as
assert(x) (from assert.h) which expands to nothing when NDEBUG is
set (common for "release" builds).
---
 portable/MSVC-MingW/port.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/portable/MSVC-MingW/port.c b/portable/MSVC-MingW/port.c
index 74dd777ef..540c4a4bc 100644
--- a/portable/MSVC-MingW/port.c
+++ b/portable/MSVC-MingW/port.c
@@ -152,6 +152,7 @@ static DWORD WINAPI prvSimulatedPeripheralTimer( LPVOID lpParameter )
     TickType_t xWaitTimeBetweenTicks = portTICK_PERIOD_MS;
     HANDLE hTimer = NULL;
     LARGE_INTEGER liDueTime;
+    BOOL bSuccess;
 
     /* Set the timer resolution to the maximum possible. */
     if( timeGetDevCaps( &xTimeCaps, sizeof( xTimeCaps ) ) == MMSYSERR_NOERROR )
@@ -190,7 +191,8 @@ static DWORD WINAPI prvSimulatedPeripheralTimer( LPVOID lpParameter )
 
     /* Set the Waitable Timer. The timer is set to run periodically at every
     xWaitTimeBetweenTicks milliseconds. */
-    configASSERT( SetWaitableTimer( hTimer, &liDueTime, xWaitTimeBetweenTicks, NULL, NULL, 0 ) );
+    bSuccess = SetWaitableTimer( hTimer, &liDueTime, xWaitTimeBetweenTicks, NULL, NULL, 0 );
+    configASSERT( bSuccess );
 
     while( xPortRunning == pdTRUE )
     {

From 44ae6cf61a7dc8c5801afdd9c562adcbef7f5070 Mon Sep 17 00:00:00 2001
From: Ahmed Ismail <64546783+AhmedIsmail02@users.noreply.github.com>
Date: Tue, 9 Sep 2025 07:25:42 +0100
Subject: [PATCH 422/424] cortex-M ports: Clarify hardware-saved exception
 frame size variable (#1314)

* cortex-M ports: Clarify hardware-saved exception frame size variable

- Rename ulStackFrameSize to ulHardwareSavedExceptionFrameSize to
reflect the hardware-saved exception frame (8 or 26 words based
on FPU/lazy stacking).
- Add comments explaining standard vs extended frames.
- Apply across Cortex-M ports.
- No functional change, improves readability.

Signed-off-by: Ahmed Ismail <Ahmed.Ismail@arm.com>
Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* kernel-checker-script: Modify Arm copyright header regex

Arm's copyright header regex is modified with the following:

* Accept both single year copyright headers (e.g., "2024")
and year range copyright headers (e.g., "2024-2025").

* Accept both single-line copyright header and also
multi-line header.

* Add the escape backslash to accept only literal dot
not any character.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Signed-off-by: Ahmed Ismail <Ahmed.Ismail@arm.com>

---------

Signed-off-by: Ahmed Ismail <Ahmed.Ismail@arm.com>
Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
---
 .github/scripts/kernel_checker.py            |  8 +++--
 portable/ARMv8M/non_secure/port.c            | 36 ++++++++++++--------
 portable/GCC/ARM_CM0/port.c                  | 22 ++++++++----
 portable/GCC/ARM_CM23/non_secure/port.c      | 36 ++++++++++++--------
 portable/GCC/ARM_CM23_NTZ/non_secure/port.c  | 36 ++++++++++++--------
 portable/GCC/ARM_CM33/non_secure/port.c      | 36 ++++++++++++--------
 portable/GCC/ARM_CM33_NTZ/non_secure/port.c  | 36 ++++++++++++--------
 portable/GCC/ARM_CM35P/non_secure/port.c     | 36 ++++++++++++--------
 portable/GCC/ARM_CM35P_NTZ/non_secure/port.c | 36 ++++++++++++--------
 portable/GCC/ARM_CM3_MPU/port.c              | 22 ++++++++----
 portable/GCC/ARM_CM4_MPU/port.c              | 32 +++++++++++------
 portable/GCC/ARM_CM55/non_secure/port.c      | 36 ++++++++++++--------
 portable/GCC/ARM_CM55_NTZ/non_secure/port.c  | 36 ++++++++++++--------
 portable/GCC/ARM_CM85/non_secure/port.c      | 36 ++++++++++++--------
 portable/GCC/ARM_CM85_NTZ/non_secure/port.c  | 36 ++++++++++++--------
 portable/IAR/ARM_CM23/non_secure/port.c      | 36 ++++++++++++--------
 portable/IAR/ARM_CM23_NTZ/non_secure/port.c  | 36 ++++++++++++--------
 portable/IAR/ARM_CM33/non_secure/port.c      | 36 ++++++++++++--------
 portable/IAR/ARM_CM33_NTZ/non_secure/port.c  | 36 ++++++++++++--------
 portable/IAR/ARM_CM35P/non_secure/port.c     | 36 ++++++++++++--------
 portable/IAR/ARM_CM35P_NTZ/non_secure/port.c | 36 ++++++++++++--------
 portable/IAR/ARM_CM4F_MPU/port.c             | 32 +++++++++++------
 portable/IAR/ARM_CM55/non_secure/port.c      | 36 ++++++++++++--------
 portable/IAR/ARM_CM55_NTZ/non_secure/port.c  | 36 ++++++++++++--------
 portable/IAR/ARM_CM85/non_secure/port.c      | 36 ++++++++++++--------
 portable/IAR/ARM_CM85_NTZ/non_secure/port.c  | 36 ++++++++++++--------
 portable/RVDS/ARM_CM4_MPU/port.c             | 32 +++++++++++------
 27 files changed, 561 insertions(+), 343 deletions(-)

diff --git a/.github/scripts/kernel_checker.py b/.github/scripts/kernel_checker.py
index 228257042..3e770fed4 100755
--- a/.github/scripts/kernel_checker.py
+++ b/.github/scripts/kernel_checker.py
@@ -114,6 +114,10 @@ KERNEL_ARM_COLLAB_FILES_PATTERNS = [
     r'.*portable/.*/ARM_CM35*',
     r'.*portable/.*/ARM_CM55*',
     r'.*portable/.*/ARM_CM85*',
+    r'.*portable/.*/ARM_CM0*',
+    r'.*portable/.*/ARM_CM3_MPU*',
+    r'.*portable/.*/ARM_CM4_MPU*',
+    r'.*portable/.*/ARM_CM4F_MPU*',
 ]
 
 KERNEL_HEADER = [
@@ -150,8 +154,8 @@ KERNEL_HEADER = [
 FREERTOS_COPYRIGHT_REGEX = r"^(;|#)?( *(\/\*|\*|#|\/\/))? Copyright \(C\) 20\d\d Amazon.com, Inc. or its affiliates. All Rights Reserved\.( \*\/)?$"
 
 FREERTOS_ARM_COLLAB_COPYRIGHT_REGEX = r"(^(;|#)?( *(\/\*|\*|#|\/\/))? Copyright \(C\) 20\d\d Amazon.com, Inc. or its affiliates. All Rights Reserved\.( \*\/)?$)|" + \
-                                      r"(^(;|#)?( *(\/\*|\*|#|\/\/))? Copyright 20\d\d Arm Limited and/or its affiliates( \*\/)?$)|" + \
-                                      r"(^(;|#)?( *(\/\*|\*|#|\/\/))? <open-source-office@arm.com>( \*\/)?$)"
+                                      r"(^(;|#)?( *(\/\*|\*|#|\/\/))? Copyright 20\d\d(-20\d\d)? Arm Limited and/or its affiliates( +<open-source-office@arm\.com>)?( \*\/)?$)|" + \
+                                      r"(^(;|#)?( *(\/\*|\*|#|\/\/))? <open-source-office@arm\.com>( \*\/)?$)"
 
 
 class KernelHeaderChecker(HeaderChecker):
diff --git a/portable/ARMv8M/non_secure/port.c b/portable/ARMv8M/non_secure/port.c
index a7fb054bc..76d2b2445 100644
--- a/portable/ARMv8M/non_secure/port.c
+++ b/portable/ARMv8M/non_secure/port.c
@@ -1,7 +1,7 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * Copyright 2024 Arm Limited and/or its affiliates
+ * Copyright 2024-2025 Arm Limited and/or its affiliates
  * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
@@ -1200,7 +1200,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ];
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulSystemCallStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
+        uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
 
@@ -1236,12 +1236,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         {
             pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
 
+            /* Hardware Saved Stack Frame Size upon Exception entry:
+             * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words.
+             * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words.
+             */
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
                 {
                     /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
+                    ulHardwareSavedExceptionFrameSize = 26;
                     __asm volatile (
                         " vpush {s0}         \n" /* Trigger lazy stacking. */
                         " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
@@ -1251,20 +1255,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 else
                 {
                     /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
+                    ulHardwareSavedExceptionFrameSize = 8;
                 }
             }
             #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
             {
-                ulStackFrameSize = 8;
+                ulHardwareSavedExceptionFrameSize = 8;
             }
             #endif /* configENABLE_FPU || configENABLE_MVE */
 
             /* Make space on the system call stack for the stack frame. */
-            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
+            pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize;
 
             /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
+            for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ )
             {
                 pulSystemCallStack[ i ] = pulTaskStack[ i ];
             }
@@ -1300,7 +1304,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
-            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize;
 
             /* Record if the hardware used padding to force the stack pointer
              * to be double word aligned. */
@@ -1350,7 +1354,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         extern TaskHandle_t pxCurrentTCB;
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulTaskStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
+        uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
 
@@ -1382,12 +1386,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         {
             pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
 
+            /* Hardware Saved Stack Frame Size upon Exception entry:
+             * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words.
+             * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words.
+             */
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
                 {
                     /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
+                    ulHardwareSavedExceptionFrameSize = 26;
                     __asm volatile (
                         " vpush {s0}         \n" /* Trigger lazy stacking. */
                         " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
@@ -1397,20 +1405,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 else
                 {
                     /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
+                    ulHardwareSavedExceptionFrameSize = 8;
                 }
             }
             #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
             {
-                ulStackFrameSize = 8;
+                ulHardwareSavedExceptionFrameSize = 8;
             }
             #endif /* configENABLE_FPU || configENABLE_MVE */
 
             /* Make space on the task stack for the stack frame. */
-            pulTaskStack = pulTaskStack - ulStackFrameSize;
+            pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize;
 
             /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
+            for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ )
             {
                 pulTaskStack[ i ] = pulSystemCallStack[ i ];
             }
diff --git a/portable/GCC/ARM_CM0/port.c b/portable/GCC/ARM_CM0/port.c
index c3053c543..fd3229a76 100644
--- a/portable/GCC/ARM_CM0/port.c
+++ b/portable/GCC/ARM_CM0/port.c
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2025 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -915,7 +917,10 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulSystemCallStack;
         uint32_t ulSystemCallLocation, i;
-        const uint32_t ulStackFrameSize = 8;
+        /* Hardware Saved Stack Frame Size upon Exception entry:
+         * Basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words.
+         */
+        const uint32_t ulHardwareSavedExceptionFrameSize = 8;
 
         #if defined( __ARMCC_VERSION )
 
@@ -955,10 +960,10 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
 
             /* Make space on the system call stack for the stack frame. */
-            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
+            pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize;
 
             /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
+            for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ )
             {
                 pulSystemCallStack[ i ] = pulTaskStack[ i ];
             }
@@ -981,7 +986,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
-            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize;
 
             /* Record if the hardware used padding to force the stack pointer
              * to be double word aligned. */
@@ -1036,7 +1041,10 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulTaskStack;
         uint32_t ulSystemCallLocation, i;
-        const uint32_t ulStackFrameSize = 8;
+        /* Hardware Saved Stack Frame Size upon Exception entry:
+         * Basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words.
+         */
+        const uint32_t ulHardwareSavedExceptionFrameSize = 8;
 
         #if defined( __ARMCC_VERSION )
 
@@ -1072,10 +1080,10 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
             pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
 
             /* Make space on the task stack for the stack frame. */
-            pulTaskStack = pulTaskStack - ulStackFrameSize;
+            pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize;
 
             /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
+            for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ )
             {
                 pulTaskStack[ i ] = pulSystemCallStack[ i ];
             }
diff --git a/portable/GCC/ARM_CM23/non_secure/port.c b/portable/GCC/ARM_CM23/non_secure/port.c
index a7fb054bc..76d2b2445 100644
--- a/portable/GCC/ARM_CM23/non_secure/port.c
+++ b/portable/GCC/ARM_CM23/non_secure/port.c
@@ -1,7 +1,7 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * Copyright 2024 Arm Limited and/or its affiliates
+ * Copyright 2024-2025 Arm Limited and/or its affiliates
  * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
@@ -1200,7 +1200,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ];
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulSystemCallStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
+        uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
 
@@ -1236,12 +1236,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         {
             pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
 
+            /* Hardware Saved Stack Frame Size upon Exception entry:
+             * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words.
+             * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words.
+             */
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
                 {
                     /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
+                    ulHardwareSavedExceptionFrameSize = 26;
                     __asm volatile (
                         " vpush {s0}         \n" /* Trigger lazy stacking. */
                         " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
@@ -1251,20 +1255,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 else
                 {
                     /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
+                    ulHardwareSavedExceptionFrameSize = 8;
                 }
             }
             #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
             {
-                ulStackFrameSize = 8;
+                ulHardwareSavedExceptionFrameSize = 8;
             }
             #endif /* configENABLE_FPU || configENABLE_MVE */
 
             /* Make space on the system call stack for the stack frame. */
-            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
+            pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize;
 
             /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
+            for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ )
             {
                 pulSystemCallStack[ i ] = pulTaskStack[ i ];
             }
@@ -1300,7 +1304,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
-            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize;
 
             /* Record if the hardware used padding to force the stack pointer
              * to be double word aligned. */
@@ -1350,7 +1354,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         extern TaskHandle_t pxCurrentTCB;
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulTaskStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
+        uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
 
@@ -1382,12 +1386,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         {
             pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
 
+            /* Hardware Saved Stack Frame Size upon Exception entry:
+             * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words.
+             * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words.
+             */
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
                 {
                     /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
+                    ulHardwareSavedExceptionFrameSize = 26;
                     __asm volatile (
                         " vpush {s0}         \n" /* Trigger lazy stacking. */
                         " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
@@ -1397,20 +1405,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 else
                 {
                     /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
+                    ulHardwareSavedExceptionFrameSize = 8;
                 }
             }
             #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
             {
-                ulStackFrameSize = 8;
+                ulHardwareSavedExceptionFrameSize = 8;
             }
             #endif /* configENABLE_FPU || configENABLE_MVE */
 
             /* Make space on the task stack for the stack frame. */
-            pulTaskStack = pulTaskStack - ulStackFrameSize;
+            pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize;
 
             /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
+            for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ )
             {
                 pulTaskStack[ i ] = pulSystemCallStack[ i ];
             }
diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
index a7fb054bc..76d2b2445 100644
--- a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
@@ -1,7 +1,7 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * Copyright 2024 Arm Limited and/or its affiliates
+ * Copyright 2024-2025 Arm Limited and/or its affiliates
  * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
@@ -1200,7 +1200,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ];
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulSystemCallStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
+        uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
 
@@ -1236,12 +1236,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         {
             pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
 
+            /* Hardware Saved Stack Frame Size upon Exception entry:
+             * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words.
+             * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words.
+             */
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
                 {
                     /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
+                    ulHardwareSavedExceptionFrameSize = 26;
                     __asm volatile (
                         " vpush {s0}         \n" /* Trigger lazy stacking. */
                         " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
@@ -1251,20 +1255,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 else
                 {
                     /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
+                    ulHardwareSavedExceptionFrameSize = 8;
                 }
             }
             #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
             {
-                ulStackFrameSize = 8;
+                ulHardwareSavedExceptionFrameSize = 8;
             }
             #endif /* configENABLE_FPU || configENABLE_MVE */
 
             /* Make space on the system call stack for the stack frame. */
-            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
+            pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize;
 
             /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
+            for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ )
             {
                 pulSystemCallStack[ i ] = pulTaskStack[ i ];
             }
@@ -1300,7 +1304,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
-            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize;
 
             /* Record if the hardware used padding to force the stack pointer
              * to be double word aligned. */
@@ -1350,7 +1354,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         extern TaskHandle_t pxCurrentTCB;
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulTaskStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
+        uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
 
@@ -1382,12 +1386,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         {
             pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
 
+            /* Hardware Saved Stack Frame Size upon Exception entry:
+             * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words.
+             * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words.
+             */
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
                 {
                     /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
+                    ulHardwareSavedExceptionFrameSize = 26;
                     __asm volatile (
                         " vpush {s0}         \n" /* Trigger lazy stacking. */
                         " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
@@ -1397,20 +1405,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 else
                 {
                     /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
+                    ulHardwareSavedExceptionFrameSize = 8;
                 }
             }
             #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
             {
-                ulStackFrameSize = 8;
+                ulHardwareSavedExceptionFrameSize = 8;
             }
             #endif /* configENABLE_FPU || configENABLE_MVE */
 
             /* Make space on the task stack for the stack frame. */
-            pulTaskStack = pulTaskStack - ulStackFrameSize;
+            pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize;
 
             /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
+            for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ )
             {
                 pulTaskStack[ i ] = pulSystemCallStack[ i ];
             }
diff --git a/portable/GCC/ARM_CM33/non_secure/port.c b/portable/GCC/ARM_CM33/non_secure/port.c
index a7fb054bc..76d2b2445 100644
--- a/portable/GCC/ARM_CM33/non_secure/port.c
+++ b/portable/GCC/ARM_CM33/non_secure/port.c
@@ -1,7 +1,7 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * Copyright 2024 Arm Limited and/or its affiliates
+ * Copyright 2024-2025 Arm Limited and/or its affiliates
  * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
@@ -1200,7 +1200,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ];
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulSystemCallStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
+        uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
 
@@ -1236,12 +1236,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         {
             pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
 
+            /* Hardware Saved Stack Frame Size upon Exception entry:
+             * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words.
+             * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words.
+             */
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
                 {
                     /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
+                    ulHardwareSavedExceptionFrameSize = 26;
                     __asm volatile (
                         " vpush {s0}         \n" /* Trigger lazy stacking. */
                         " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
@@ -1251,20 +1255,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 else
                 {
                     /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
+                    ulHardwareSavedExceptionFrameSize = 8;
                 }
             }
             #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
             {
-                ulStackFrameSize = 8;
+                ulHardwareSavedExceptionFrameSize = 8;
             }
             #endif /* configENABLE_FPU || configENABLE_MVE */
 
             /* Make space on the system call stack for the stack frame. */
-            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
+            pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize;
 
             /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
+            for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ )
             {
                 pulSystemCallStack[ i ] = pulTaskStack[ i ];
             }
@@ -1300,7 +1304,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
-            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize;
 
             /* Record if the hardware used padding to force the stack pointer
              * to be double word aligned. */
@@ -1350,7 +1354,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         extern TaskHandle_t pxCurrentTCB;
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulTaskStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
+        uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
 
@@ -1382,12 +1386,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         {
             pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
 
+            /* Hardware Saved Stack Frame Size upon Exception entry:
+             * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words.
+             * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words.
+             */
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
                 {
                     /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
+                    ulHardwareSavedExceptionFrameSize = 26;
                     __asm volatile (
                         " vpush {s0}         \n" /* Trigger lazy stacking. */
                         " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
@@ -1397,20 +1405,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 else
                 {
                     /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
+                    ulHardwareSavedExceptionFrameSize = 8;
                 }
             }
             #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
             {
-                ulStackFrameSize = 8;
+                ulHardwareSavedExceptionFrameSize = 8;
             }
             #endif /* configENABLE_FPU || configENABLE_MVE */
 
             /* Make space on the task stack for the stack frame. */
-            pulTaskStack = pulTaskStack - ulStackFrameSize;
+            pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize;
 
             /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
+            for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ )
             {
                 pulTaskStack[ i ] = pulSystemCallStack[ i ];
             }
diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
index a7fb054bc..76d2b2445 100644
--- a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
@@ -1,7 +1,7 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * Copyright 2024 Arm Limited and/or its affiliates
+ * Copyright 2024-2025 Arm Limited and/or its affiliates
  * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
@@ -1200,7 +1200,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ];
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulSystemCallStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
+        uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
 
@@ -1236,12 +1236,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         {
             pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
 
+            /* Hardware Saved Stack Frame Size upon Exception entry:
+             * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words.
+             * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words.
+             */
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
                 {
                     /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
+                    ulHardwareSavedExceptionFrameSize = 26;
                     __asm volatile (
                         " vpush {s0}         \n" /* Trigger lazy stacking. */
                         " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
@@ -1251,20 +1255,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 else
                 {
                     /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
+                    ulHardwareSavedExceptionFrameSize = 8;
                 }
             }
             #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
             {
-                ulStackFrameSize = 8;
+                ulHardwareSavedExceptionFrameSize = 8;
             }
             #endif /* configENABLE_FPU || configENABLE_MVE */
 
             /* Make space on the system call stack for the stack frame. */
-            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
+            pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize;
 
             /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
+            for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ )
             {
                 pulSystemCallStack[ i ] = pulTaskStack[ i ];
             }
@@ -1300,7 +1304,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
-            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize;
 
             /* Record if the hardware used padding to force the stack pointer
              * to be double word aligned. */
@@ -1350,7 +1354,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         extern TaskHandle_t pxCurrentTCB;
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulTaskStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
+        uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
 
@@ -1382,12 +1386,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         {
             pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
 
+            /* Hardware Saved Stack Frame Size upon Exception entry:
+             * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words.
+             * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words.
+             */
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
                 {
                     /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
+                    ulHardwareSavedExceptionFrameSize = 26;
                     __asm volatile (
                         " vpush {s0}         \n" /* Trigger lazy stacking. */
                         " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
@@ -1397,20 +1405,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 else
                 {
                     /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
+                    ulHardwareSavedExceptionFrameSize = 8;
                 }
             }
             #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
             {
-                ulStackFrameSize = 8;
+                ulHardwareSavedExceptionFrameSize = 8;
             }
             #endif /* configENABLE_FPU || configENABLE_MVE */
 
             /* Make space on the task stack for the stack frame. */
-            pulTaskStack = pulTaskStack - ulStackFrameSize;
+            pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize;
 
             /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
+            for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ )
             {
                 pulTaskStack[ i ] = pulSystemCallStack[ i ];
             }
diff --git a/portable/GCC/ARM_CM35P/non_secure/port.c b/portable/GCC/ARM_CM35P/non_secure/port.c
index a7fb054bc..76d2b2445 100644
--- a/portable/GCC/ARM_CM35P/non_secure/port.c
+++ b/portable/GCC/ARM_CM35P/non_secure/port.c
@@ -1,7 +1,7 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * Copyright 2024 Arm Limited and/or its affiliates
+ * Copyright 2024-2025 Arm Limited and/or its affiliates
  * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
@@ -1200,7 +1200,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ];
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulSystemCallStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
+        uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
 
@@ -1236,12 +1236,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         {
             pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
 
+            /* Hardware Saved Stack Frame Size upon Exception entry:
+             * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words.
+             * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words.
+             */
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
                 {
                     /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
+                    ulHardwareSavedExceptionFrameSize = 26;
                     __asm volatile (
                         " vpush {s0}         \n" /* Trigger lazy stacking. */
                         " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
@@ -1251,20 +1255,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 else
                 {
                     /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
+                    ulHardwareSavedExceptionFrameSize = 8;
                 }
             }
             #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
             {
-                ulStackFrameSize = 8;
+                ulHardwareSavedExceptionFrameSize = 8;
             }
             #endif /* configENABLE_FPU || configENABLE_MVE */
 
             /* Make space on the system call stack for the stack frame. */
-            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
+            pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize;
 
             /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
+            for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ )
             {
                 pulSystemCallStack[ i ] = pulTaskStack[ i ];
             }
@@ -1300,7 +1304,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
-            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize;
 
             /* Record if the hardware used padding to force the stack pointer
              * to be double word aligned. */
@@ -1350,7 +1354,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         extern TaskHandle_t pxCurrentTCB;
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulTaskStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
+        uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
 
@@ -1382,12 +1386,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         {
             pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
 
+            /* Hardware Saved Stack Frame Size upon Exception entry:
+             * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words.
+             * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words.
+             */
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
                 {
                     /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
+                    ulHardwareSavedExceptionFrameSize = 26;
                     __asm volatile (
                         " vpush {s0}         \n" /* Trigger lazy stacking. */
                         " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
@@ -1397,20 +1405,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 else
                 {
                     /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
+                    ulHardwareSavedExceptionFrameSize = 8;
                 }
             }
             #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
             {
-                ulStackFrameSize = 8;
+                ulHardwareSavedExceptionFrameSize = 8;
             }
             #endif /* configENABLE_FPU || configENABLE_MVE */
 
             /* Make space on the task stack for the stack frame. */
-            pulTaskStack = pulTaskStack - ulStackFrameSize;
+            pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize;
 
             /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
+            for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ )
             {
                 pulTaskStack[ i ] = pulSystemCallStack[ i ];
             }
diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c b/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
index a7fb054bc..76d2b2445 100644
--- a/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
@@ -1,7 +1,7 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * Copyright 2024 Arm Limited and/or its affiliates
+ * Copyright 2024-2025 Arm Limited and/or its affiliates
  * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
@@ -1200,7 +1200,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ];
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulSystemCallStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
+        uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
 
@@ -1236,12 +1236,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         {
             pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
 
+            /* Hardware Saved Stack Frame Size upon Exception entry:
+             * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words.
+             * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words.
+             */
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
                 {
                     /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
+                    ulHardwareSavedExceptionFrameSize = 26;
                     __asm volatile (
                         " vpush {s0}         \n" /* Trigger lazy stacking. */
                         " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
@@ -1251,20 +1255,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 else
                 {
                     /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
+                    ulHardwareSavedExceptionFrameSize = 8;
                 }
             }
             #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
             {
-                ulStackFrameSize = 8;
+                ulHardwareSavedExceptionFrameSize = 8;
             }
             #endif /* configENABLE_FPU || configENABLE_MVE */
 
             /* Make space on the system call stack for the stack frame. */
-            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
+            pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize;
 
             /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
+            for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ )
             {
                 pulSystemCallStack[ i ] = pulTaskStack[ i ];
             }
@@ -1300,7 +1304,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
-            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize;
 
             /* Record if the hardware used padding to force the stack pointer
              * to be double word aligned. */
@@ -1350,7 +1354,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         extern TaskHandle_t pxCurrentTCB;
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulTaskStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
+        uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
 
@@ -1382,12 +1386,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         {
             pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
 
+            /* Hardware Saved Stack Frame Size upon Exception entry:
+             * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words.
+             * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words.
+             */
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
                 {
                     /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
+                    ulHardwareSavedExceptionFrameSize = 26;
                     __asm volatile (
                         " vpush {s0}         \n" /* Trigger lazy stacking. */
                         " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
@@ -1397,20 +1405,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 else
                 {
                     /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
+                    ulHardwareSavedExceptionFrameSize = 8;
                 }
             }
             #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
             {
-                ulStackFrameSize = 8;
+                ulHardwareSavedExceptionFrameSize = 8;
             }
             #endif /* configENABLE_FPU || configENABLE_MVE */
 
             /* Make space on the task stack for the stack frame. */
-            pulTaskStack = pulTaskStack - ulStackFrameSize;
+            pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize;
 
             /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
+            for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ )
             {
                 pulTaskStack[ i ] = pulSystemCallStack[ i ];
             }
diff --git a/portable/GCC/ARM_CM3_MPU/port.c b/portable/GCC/ARM_CM3_MPU/port.c
index cc91c5611..8c4dd7800 100644
--- a/portable/GCC/ARM_CM3_MPU/port.c
+++ b/portable/GCC/ARM_CM3_MPU/port.c
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2025 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -484,7 +486,10 @@ void vSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulSystemCallStack;
         uint32_t ulSystemCallLocation, i;
-        const uint32_t ulStackFrameSize = 8;
+        /* Hardware Saved Stack Frame Size upon Exception entry:
+         * Basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words.
+         */
+        const uint32_t ulHardwareSavedExceptionFrameSize = 8;
 
         #if defined( __ARMCC_VERSION )
             /* Declaration when these variable are defined in code instead of being
@@ -520,10 +525,10 @@ void vSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
             pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
 
             /* Make space on the system call stack for the stack frame. */
-            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
+            pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize;
 
             /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
+            for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ )
             {
                 pulSystemCallStack[ i ] = pulTaskStack[ i ];
             }
@@ -541,7 +546,7 @@ void vSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
-            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize;
 
             /* Store the value of the Link Register before the SVC was raised.
              * It contains the address of the caller of the System Call entry
@@ -594,7 +599,10 @@ void vSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulTaskStack;
         uint32_t ulSystemCallLocation, i;
-        const uint32_t ulStackFrameSize = 8;
+        /* Hardware Saved Stack Frame Size upon Exception entry:
+         * Basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words.
+         */
+        const uint32_t ulHardwareSavedExceptionFrameSize = 8;
 
         #if defined( __ARMCC_VERSION )
             /* Declaration when these variable are defined in code instead of being
@@ -626,10 +634,10 @@ void vSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
             pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
 
             /* Make space on the task stack for the stack frame. */
-            pulTaskStack = pulTaskStack - ulStackFrameSize;
+            pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize;
 
             /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
+            for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ )
             {
                 pulTaskStack[ i ] = pulSystemCallStack[ i ];
             }
diff --git a/portable/GCC/ARM_CM4_MPU/port.c b/portable/GCC/ARM_CM4_MPU/port.c
index d6a4931b5..79f5e76d5 100644
--- a/portable/GCC/ARM_CM4_MPU/port.c
+++ b/portable/GCC/ARM_CM4_MPU/port.c
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2025 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -518,7 +520,7 @@ void vSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
         extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ];
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulSystemCallStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
+        uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
             /* Declaration when these variable are defined in code instead of being
@@ -553,10 +555,14 @@ void vSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
         {
             pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
 
+            /* Hardware Saved Stack Frame Size upon Exception entry:
+             * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words.
+             * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words.
+             */
             if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
             {
                 /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
+                ulHardwareSavedExceptionFrameSize = 26;
                 __asm volatile (
                     " vpush {s0}         \n" /* Trigger lazy stacking. */
                     " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
@@ -566,14 +572,14 @@ void vSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
             else
             {
                 /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                ulHardwareSavedExceptionFrameSize = 8;
             }
 
             /* Make space on the system call stack for the stack frame. */
-            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
+            pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize;
 
             /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
+            for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ )
             {
                 pulSystemCallStack[ i ] = pulTaskStack[ i ];
             }
@@ -591,7 +597,7 @@ void vSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
-            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize;
 
             /* Store the value of the Link Register before the SVC was raised.
              * It contains the address of the caller of the System Call entry
@@ -644,7 +650,7 @@ void vSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
         extern TaskHandle_t pxCurrentTCB;
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulTaskStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
+        uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
             /* Declaration when these variable are defined in code instead of being
@@ -675,10 +681,14 @@ void vSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
         {
             pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
 
+            /* Hardware Saved Stack Frame Size upon Exception entry:
+             * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words.
+             * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words.
+             */
             if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
             {
                 /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
+                ulHardwareSavedExceptionFrameSize = 26;
                 __asm volatile (
                     " vpush {s0}         \n" /* Trigger lazy stacking. */
                     " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
@@ -688,14 +698,14 @@ void vSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
             else
             {
                 /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                ulHardwareSavedExceptionFrameSize = 8;
             }
 
             /* Make space on the task stack for the stack frame. */
-            pulTaskStack = pulTaskStack - ulStackFrameSize;
+            pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize;
 
             /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
+            for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ )
             {
                 pulTaskStack[ i ] = pulSystemCallStack[ i ];
             }
diff --git a/portable/GCC/ARM_CM55/non_secure/port.c b/portable/GCC/ARM_CM55/non_secure/port.c
index a7fb054bc..76d2b2445 100644
--- a/portable/GCC/ARM_CM55/non_secure/port.c
+++ b/portable/GCC/ARM_CM55/non_secure/port.c
@@ -1,7 +1,7 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * Copyright 2024 Arm Limited and/or its affiliates
+ * Copyright 2024-2025 Arm Limited and/or its affiliates
  * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
@@ -1200,7 +1200,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ];
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulSystemCallStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
+        uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
 
@@ -1236,12 +1236,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         {
             pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
 
+            /* Hardware Saved Stack Frame Size upon Exception entry:
+             * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words.
+             * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words.
+             */
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
                 {
                     /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
+                    ulHardwareSavedExceptionFrameSize = 26;
                     __asm volatile (
                         " vpush {s0}         \n" /* Trigger lazy stacking. */
                         " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
@@ -1251,20 +1255,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 else
                 {
                     /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
+                    ulHardwareSavedExceptionFrameSize = 8;
                 }
             }
             #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
             {
-                ulStackFrameSize = 8;
+                ulHardwareSavedExceptionFrameSize = 8;
             }
             #endif /* configENABLE_FPU || configENABLE_MVE */
 
             /* Make space on the system call stack for the stack frame. */
-            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
+            pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize;
 
             /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
+            for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ )
             {
                 pulSystemCallStack[ i ] = pulTaskStack[ i ];
             }
@@ -1300,7 +1304,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
-            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize;
 
             /* Record if the hardware used padding to force the stack pointer
              * to be double word aligned. */
@@ -1350,7 +1354,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         extern TaskHandle_t pxCurrentTCB;
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulTaskStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
+        uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
 
@@ -1382,12 +1386,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         {
             pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
 
+            /* Hardware Saved Stack Frame Size upon Exception entry:
+             * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words.
+             * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words.
+             */
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
                 {
                     /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
+                    ulHardwareSavedExceptionFrameSize = 26;
                     __asm volatile (
                         " vpush {s0}         \n" /* Trigger lazy stacking. */
                         " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
@@ -1397,20 +1405,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 else
                 {
                     /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
+                    ulHardwareSavedExceptionFrameSize = 8;
                 }
             }
             #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
             {
-                ulStackFrameSize = 8;
+                ulHardwareSavedExceptionFrameSize = 8;
             }
             #endif /* configENABLE_FPU || configENABLE_MVE */
 
             /* Make space on the task stack for the stack frame. */
-            pulTaskStack = pulTaskStack - ulStackFrameSize;
+            pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize;
 
             /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
+            for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ )
             {
                 pulTaskStack[ i ] = pulSystemCallStack[ i ];
             }
diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/port.c b/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
index a7fb054bc..76d2b2445 100644
--- a/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
@@ -1,7 +1,7 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * Copyright 2024 Arm Limited and/or its affiliates
+ * Copyright 2024-2025 Arm Limited and/or its affiliates
  * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
@@ -1200,7 +1200,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ];
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulSystemCallStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
+        uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
 
@@ -1236,12 +1236,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         {
             pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
 
+            /* Hardware Saved Stack Frame Size upon Exception entry:
+             * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words.
+             * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words.
+             */
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
                 {
                     /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
+                    ulHardwareSavedExceptionFrameSize = 26;
                     __asm volatile (
                         " vpush {s0}         \n" /* Trigger lazy stacking. */
                         " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
@@ -1251,20 +1255,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 else
                 {
                     /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
+                    ulHardwareSavedExceptionFrameSize = 8;
                 }
             }
             #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
             {
-                ulStackFrameSize = 8;
+                ulHardwareSavedExceptionFrameSize = 8;
             }
             #endif /* configENABLE_FPU || configENABLE_MVE */
 
             /* Make space on the system call stack for the stack frame. */
-            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
+            pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize;
 
             /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
+            for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ )
             {
                 pulSystemCallStack[ i ] = pulTaskStack[ i ];
             }
@@ -1300,7 +1304,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
-            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize;
 
             /* Record if the hardware used padding to force the stack pointer
              * to be double word aligned. */
@@ -1350,7 +1354,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         extern TaskHandle_t pxCurrentTCB;
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulTaskStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
+        uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
 
@@ -1382,12 +1386,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         {
             pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
 
+            /* Hardware Saved Stack Frame Size upon Exception entry:
+             * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words.
+             * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words.
+             */
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
                 {
                     /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
+                    ulHardwareSavedExceptionFrameSize = 26;
                     __asm volatile (
                         " vpush {s0}         \n" /* Trigger lazy stacking. */
                         " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
@@ -1397,20 +1405,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 else
                 {
                     /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
+                    ulHardwareSavedExceptionFrameSize = 8;
                 }
             }
             #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
             {
-                ulStackFrameSize = 8;
+                ulHardwareSavedExceptionFrameSize = 8;
             }
             #endif /* configENABLE_FPU || configENABLE_MVE */
 
             /* Make space on the task stack for the stack frame. */
-            pulTaskStack = pulTaskStack - ulStackFrameSize;
+            pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize;
 
             /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
+            for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ )
             {
                 pulTaskStack[ i ] = pulSystemCallStack[ i ];
             }
diff --git a/portable/GCC/ARM_CM85/non_secure/port.c b/portable/GCC/ARM_CM85/non_secure/port.c
index a7fb054bc..76d2b2445 100644
--- a/portable/GCC/ARM_CM85/non_secure/port.c
+++ b/portable/GCC/ARM_CM85/non_secure/port.c
@@ -1,7 +1,7 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * Copyright 2024 Arm Limited and/or its affiliates
+ * Copyright 2024-2025 Arm Limited and/or its affiliates
  * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
@@ -1200,7 +1200,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ];
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulSystemCallStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
+        uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
 
@@ -1236,12 +1236,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         {
             pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
 
+            /* Hardware Saved Stack Frame Size upon Exception entry:
+             * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words.
+             * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words.
+             */
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
                 {
                     /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
+                    ulHardwareSavedExceptionFrameSize = 26;
                     __asm volatile (
                         " vpush {s0}         \n" /* Trigger lazy stacking. */
                         " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
@@ -1251,20 +1255,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 else
                 {
                     /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
+                    ulHardwareSavedExceptionFrameSize = 8;
                 }
             }
             #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
             {
-                ulStackFrameSize = 8;
+                ulHardwareSavedExceptionFrameSize = 8;
             }
             #endif /* configENABLE_FPU || configENABLE_MVE */
 
             /* Make space on the system call stack for the stack frame. */
-            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
+            pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize;
 
             /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
+            for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ )
             {
                 pulSystemCallStack[ i ] = pulTaskStack[ i ];
             }
@@ -1300,7 +1304,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
-            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize;
 
             /* Record if the hardware used padding to force the stack pointer
              * to be double word aligned. */
@@ -1350,7 +1354,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         extern TaskHandle_t pxCurrentTCB;
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulTaskStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
+        uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
 
@@ -1382,12 +1386,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         {
             pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
 
+            /* Hardware Saved Stack Frame Size upon Exception entry:
+             * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words.
+             * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words.
+             */
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
                 {
                     /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
+                    ulHardwareSavedExceptionFrameSize = 26;
                     __asm volatile (
                         " vpush {s0}         \n" /* Trigger lazy stacking. */
                         " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
@@ -1397,20 +1405,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 else
                 {
                     /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
+                    ulHardwareSavedExceptionFrameSize = 8;
                 }
             }
             #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
             {
-                ulStackFrameSize = 8;
+                ulHardwareSavedExceptionFrameSize = 8;
             }
             #endif /* configENABLE_FPU || configENABLE_MVE */
 
             /* Make space on the task stack for the stack frame. */
-            pulTaskStack = pulTaskStack - ulStackFrameSize;
+            pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize;
 
             /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
+            for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ )
             {
                 pulTaskStack[ i ] = pulSystemCallStack[ i ];
             }
diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/port.c b/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
index a7fb054bc..76d2b2445 100644
--- a/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
+++ b/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
@@ -1,7 +1,7 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * Copyright 2024 Arm Limited and/or its affiliates
+ * Copyright 2024-2025 Arm Limited and/or its affiliates
  * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
@@ -1200,7 +1200,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ];
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulSystemCallStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
+        uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
 
@@ -1236,12 +1236,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         {
             pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
 
+            /* Hardware Saved Stack Frame Size upon Exception entry:
+             * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words.
+             * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words.
+             */
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
                 {
                     /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
+                    ulHardwareSavedExceptionFrameSize = 26;
                     __asm volatile (
                         " vpush {s0}         \n" /* Trigger lazy stacking. */
                         " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
@@ -1251,20 +1255,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 else
                 {
                     /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
+                    ulHardwareSavedExceptionFrameSize = 8;
                 }
             }
             #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
             {
-                ulStackFrameSize = 8;
+                ulHardwareSavedExceptionFrameSize = 8;
             }
             #endif /* configENABLE_FPU || configENABLE_MVE */
 
             /* Make space on the system call stack for the stack frame. */
-            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
+            pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize;
 
             /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
+            for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ )
             {
                 pulSystemCallStack[ i ] = pulTaskStack[ i ];
             }
@@ -1300,7 +1304,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
-            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize;
 
             /* Record if the hardware used padding to force the stack pointer
              * to be double word aligned. */
@@ -1350,7 +1354,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         extern TaskHandle_t pxCurrentTCB;
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulTaskStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
+        uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
 
@@ -1382,12 +1386,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         {
             pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
 
+            /* Hardware Saved Stack Frame Size upon Exception entry:
+             * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words.
+             * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words.
+             */
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
                 {
                     /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
+                    ulHardwareSavedExceptionFrameSize = 26;
                     __asm volatile (
                         " vpush {s0}         \n" /* Trigger lazy stacking. */
                         " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
@@ -1397,20 +1405,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 else
                 {
                     /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
+                    ulHardwareSavedExceptionFrameSize = 8;
                 }
             }
             #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
             {
-                ulStackFrameSize = 8;
+                ulHardwareSavedExceptionFrameSize = 8;
             }
             #endif /* configENABLE_FPU || configENABLE_MVE */
 
             /* Make space on the task stack for the stack frame. */
-            pulTaskStack = pulTaskStack - ulStackFrameSize;
+            pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize;
 
             /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
+            for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ )
             {
                 pulTaskStack[ i ] = pulSystemCallStack[ i ];
             }
diff --git a/portable/IAR/ARM_CM23/non_secure/port.c b/portable/IAR/ARM_CM23/non_secure/port.c
index a7fb054bc..76d2b2445 100644
--- a/portable/IAR/ARM_CM23/non_secure/port.c
+++ b/portable/IAR/ARM_CM23/non_secure/port.c
@@ -1,7 +1,7 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * Copyright 2024 Arm Limited and/or its affiliates
+ * Copyright 2024-2025 Arm Limited and/or its affiliates
  * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
@@ -1200,7 +1200,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ];
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulSystemCallStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
+        uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
 
@@ -1236,12 +1236,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         {
             pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
 
+            /* Hardware Saved Stack Frame Size upon Exception entry:
+             * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words.
+             * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words.
+             */
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
                 {
                     /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
+                    ulHardwareSavedExceptionFrameSize = 26;
                     __asm volatile (
                         " vpush {s0}         \n" /* Trigger lazy stacking. */
                         " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
@@ -1251,20 +1255,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 else
                 {
                     /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
+                    ulHardwareSavedExceptionFrameSize = 8;
                 }
             }
             #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
             {
-                ulStackFrameSize = 8;
+                ulHardwareSavedExceptionFrameSize = 8;
             }
             #endif /* configENABLE_FPU || configENABLE_MVE */
 
             /* Make space on the system call stack for the stack frame. */
-            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
+            pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize;
 
             /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
+            for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ )
             {
                 pulSystemCallStack[ i ] = pulTaskStack[ i ];
             }
@@ -1300,7 +1304,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
-            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize;
 
             /* Record if the hardware used padding to force the stack pointer
              * to be double word aligned. */
@@ -1350,7 +1354,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         extern TaskHandle_t pxCurrentTCB;
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulTaskStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
+        uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
 
@@ -1382,12 +1386,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         {
             pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
 
+            /* Hardware Saved Stack Frame Size upon Exception entry:
+             * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words.
+             * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words.
+             */
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
                 {
                     /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
+                    ulHardwareSavedExceptionFrameSize = 26;
                     __asm volatile (
                         " vpush {s0}         \n" /* Trigger lazy stacking. */
                         " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
@@ -1397,20 +1405,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 else
                 {
                     /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
+                    ulHardwareSavedExceptionFrameSize = 8;
                 }
             }
             #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
             {
-                ulStackFrameSize = 8;
+                ulHardwareSavedExceptionFrameSize = 8;
             }
             #endif /* configENABLE_FPU || configENABLE_MVE */
 
             /* Make space on the task stack for the stack frame. */
-            pulTaskStack = pulTaskStack - ulStackFrameSize;
+            pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize;
 
             /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
+            for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ )
             {
                 pulTaskStack[ i ] = pulSystemCallStack[ i ];
             }
diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
index a7fb054bc..76d2b2445 100644
--- a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
@@ -1,7 +1,7 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * Copyright 2024 Arm Limited and/or its affiliates
+ * Copyright 2024-2025 Arm Limited and/or its affiliates
  * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
@@ -1200,7 +1200,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ];
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulSystemCallStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
+        uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
 
@@ -1236,12 +1236,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         {
             pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
 
+            /* Hardware Saved Stack Frame Size upon Exception entry:
+             * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words.
+             * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words.
+             */
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
                 {
                     /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
+                    ulHardwareSavedExceptionFrameSize = 26;
                     __asm volatile (
                         " vpush {s0}         \n" /* Trigger lazy stacking. */
                         " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
@@ -1251,20 +1255,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 else
                 {
                     /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
+                    ulHardwareSavedExceptionFrameSize = 8;
                 }
             }
             #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
             {
-                ulStackFrameSize = 8;
+                ulHardwareSavedExceptionFrameSize = 8;
             }
             #endif /* configENABLE_FPU || configENABLE_MVE */
 
             /* Make space on the system call stack for the stack frame. */
-            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
+            pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize;
 
             /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
+            for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ )
             {
                 pulSystemCallStack[ i ] = pulTaskStack[ i ];
             }
@@ -1300,7 +1304,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
-            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize;
 
             /* Record if the hardware used padding to force the stack pointer
              * to be double word aligned. */
@@ -1350,7 +1354,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         extern TaskHandle_t pxCurrentTCB;
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulTaskStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
+        uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
 
@@ -1382,12 +1386,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         {
             pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
 
+            /* Hardware Saved Stack Frame Size upon Exception entry:
+             * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words.
+             * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words.
+             */
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
                 {
                     /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
+                    ulHardwareSavedExceptionFrameSize = 26;
                     __asm volatile (
                         " vpush {s0}         \n" /* Trigger lazy stacking. */
                         " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
@@ -1397,20 +1405,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 else
                 {
                     /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
+                    ulHardwareSavedExceptionFrameSize = 8;
                 }
             }
             #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
             {
-                ulStackFrameSize = 8;
+                ulHardwareSavedExceptionFrameSize = 8;
             }
             #endif /* configENABLE_FPU || configENABLE_MVE */
 
             /* Make space on the task stack for the stack frame. */
-            pulTaskStack = pulTaskStack - ulStackFrameSize;
+            pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize;
 
             /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
+            for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ )
             {
                 pulTaskStack[ i ] = pulSystemCallStack[ i ];
             }
diff --git a/portable/IAR/ARM_CM33/non_secure/port.c b/portable/IAR/ARM_CM33/non_secure/port.c
index a7fb054bc..76d2b2445 100644
--- a/portable/IAR/ARM_CM33/non_secure/port.c
+++ b/portable/IAR/ARM_CM33/non_secure/port.c
@@ -1,7 +1,7 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * Copyright 2024 Arm Limited and/or its affiliates
+ * Copyright 2024-2025 Arm Limited and/or its affiliates
  * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
@@ -1200,7 +1200,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ];
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulSystemCallStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
+        uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
 
@@ -1236,12 +1236,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         {
             pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
 
+            /* Hardware Saved Stack Frame Size upon Exception entry:
+             * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words.
+             * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words.
+             */
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
                 {
                     /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
+                    ulHardwareSavedExceptionFrameSize = 26;
                     __asm volatile (
                         " vpush {s0}         \n" /* Trigger lazy stacking. */
                         " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
@@ -1251,20 +1255,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 else
                 {
                     /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
+                    ulHardwareSavedExceptionFrameSize = 8;
                 }
             }
             #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
             {
-                ulStackFrameSize = 8;
+                ulHardwareSavedExceptionFrameSize = 8;
             }
             #endif /* configENABLE_FPU || configENABLE_MVE */
 
             /* Make space on the system call stack for the stack frame. */
-            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
+            pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize;
 
             /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
+            for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ )
             {
                 pulSystemCallStack[ i ] = pulTaskStack[ i ];
             }
@@ -1300,7 +1304,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
-            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize;
 
             /* Record if the hardware used padding to force the stack pointer
              * to be double word aligned. */
@@ -1350,7 +1354,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         extern TaskHandle_t pxCurrentTCB;
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulTaskStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
+        uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
 
@@ -1382,12 +1386,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         {
             pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
 
+            /* Hardware Saved Stack Frame Size upon Exception entry:
+             * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words.
+             * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words.
+             */
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
                 {
                     /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
+                    ulHardwareSavedExceptionFrameSize = 26;
                     __asm volatile (
                         " vpush {s0}         \n" /* Trigger lazy stacking. */
                         " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
@@ -1397,20 +1405,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 else
                 {
                     /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
+                    ulHardwareSavedExceptionFrameSize = 8;
                 }
             }
             #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
             {
-                ulStackFrameSize = 8;
+                ulHardwareSavedExceptionFrameSize = 8;
             }
             #endif /* configENABLE_FPU || configENABLE_MVE */
 
             /* Make space on the task stack for the stack frame. */
-            pulTaskStack = pulTaskStack - ulStackFrameSize;
+            pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize;
 
             /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
+            for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ )
             {
                 pulTaskStack[ i ] = pulSystemCallStack[ i ];
             }
diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
index a7fb054bc..76d2b2445 100644
--- a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
@@ -1,7 +1,7 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * Copyright 2024 Arm Limited and/or its affiliates
+ * Copyright 2024-2025 Arm Limited and/or its affiliates
  * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
@@ -1200,7 +1200,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ];
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulSystemCallStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
+        uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
 
@@ -1236,12 +1236,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         {
             pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
 
+            /* Hardware Saved Stack Frame Size upon Exception entry:
+             * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words.
+             * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words.
+             */
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
                 {
                     /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
+                    ulHardwareSavedExceptionFrameSize = 26;
                     __asm volatile (
                         " vpush {s0}         \n" /* Trigger lazy stacking. */
                         " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
@@ -1251,20 +1255,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 else
                 {
                     /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
+                    ulHardwareSavedExceptionFrameSize = 8;
                 }
             }
             #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
             {
-                ulStackFrameSize = 8;
+                ulHardwareSavedExceptionFrameSize = 8;
             }
             #endif /* configENABLE_FPU || configENABLE_MVE */
 
             /* Make space on the system call stack for the stack frame. */
-            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
+            pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize;
 
             /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
+            for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ )
             {
                 pulSystemCallStack[ i ] = pulTaskStack[ i ];
             }
@@ -1300,7 +1304,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
-            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize;
 
             /* Record if the hardware used padding to force the stack pointer
              * to be double word aligned. */
@@ -1350,7 +1354,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         extern TaskHandle_t pxCurrentTCB;
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulTaskStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
+        uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
 
@@ -1382,12 +1386,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         {
             pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
 
+            /* Hardware Saved Stack Frame Size upon Exception entry:
+             * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words.
+             * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words.
+             */
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
                 {
                     /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
+                    ulHardwareSavedExceptionFrameSize = 26;
                     __asm volatile (
                         " vpush {s0}         \n" /* Trigger lazy stacking. */
                         " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
@@ -1397,20 +1405,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 else
                 {
                     /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
+                    ulHardwareSavedExceptionFrameSize = 8;
                 }
             }
             #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
             {
-                ulStackFrameSize = 8;
+                ulHardwareSavedExceptionFrameSize = 8;
             }
             #endif /* configENABLE_FPU || configENABLE_MVE */
 
             /* Make space on the task stack for the stack frame. */
-            pulTaskStack = pulTaskStack - ulStackFrameSize;
+            pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize;
 
             /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
+            for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ )
             {
                 pulTaskStack[ i ] = pulSystemCallStack[ i ];
             }
diff --git a/portable/IAR/ARM_CM35P/non_secure/port.c b/portable/IAR/ARM_CM35P/non_secure/port.c
index a7fb054bc..76d2b2445 100644
--- a/portable/IAR/ARM_CM35P/non_secure/port.c
+++ b/portable/IAR/ARM_CM35P/non_secure/port.c
@@ -1,7 +1,7 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * Copyright 2024 Arm Limited and/or its affiliates
+ * Copyright 2024-2025 Arm Limited and/or its affiliates
  * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
@@ -1200,7 +1200,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ];
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulSystemCallStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
+        uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
 
@@ -1236,12 +1236,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         {
             pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
 
+            /* Hardware Saved Stack Frame Size upon Exception entry:
+             * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words.
+             * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words.
+             */
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
                 {
                     /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
+                    ulHardwareSavedExceptionFrameSize = 26;
                     __asm volatile (
                         " vpush {s0}         \n" /* Trigger lazy stacking. */
                         " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
@@ -1251,20 +1255,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 else
                 {
                     /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
+                    ulHardwareSavedExceptionFrameSize = 8;
                 }
             }
             #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
             {
-                ulStackFrameSize = 8;
+                ulHardwareSavedExceptionFrameSize = 8;
             }
             #endif /* configENABLE_FPU || configENABLE_MVE */
 
             /* Make space on the system call stack for the stack frame. */
-            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
+            pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize;
 
             /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
+            for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ )
             {
                 pulSystemCallStack[ i ] = pulTaskStack[ i ];
             }
@@ -1300,7 +1304,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
-            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize;
 
             /* Record if the hardware used padding to force the stack pointer
              * to be double word aligned. */
@@ -1350,7 +1354,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         extern TaskHandle_t pxCurrentTCB;
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulTaskStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
+        uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
 
@@ -1382,12 +1386,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         {
             pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
 
+            /* Hardware Saved Stack Frame Size upon Exception entry:
+             * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words.
+             * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words.
+             */
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
                 {
                     /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
+                    ulHardwareSavedExceptionFrameSize = 26;
                     __asm volatile (
                         " vpush {s0}         \n" /* Trigger lazy stacking. */
                         " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
@@ -1397,20 +1405,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 else
                 {
                     /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
+                    ulHardwareSavedExceptionFrameSize = 8;
                 }
             }
             #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
             {
-                ulStackFrameSize = 8;
+                ulHardwareSavedExceptionFrameSize = 8;
             }
             #endif /* configENABLE_FPU || configENABLE_MVE */
 
             /* Make space on the task stack for the stack frame. */
-            pulTaskStack = pulTaskStack - ulStackFrameSize;
+            pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize;
 
             /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
+            for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ )
             {
                 pulTaskStack[ i ] = pulSystemCallStack[ i ];
             }
diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c b/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
index a7fb054bc..76d2b2445 100644
--- a/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
@@ -1,7 +1,7 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * Copyright 2024 Arm Limited and/or its affiliates
+ * Copyright 2024-2025 Arm Limited and/or its affiliates
  * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
@@ -1200,7 +1200,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ];
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulSystemCallStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
+        uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
 
@@ -1236,12 +1236,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         {
             pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
 
+            /* Hardware Saved Stack Frame Size upon Exception entry:
+             * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words.
+             * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words.
+             */
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
                 {
                     /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
+                    ulHardwareSavedExceptionFrameSize = 26;
                     __asm volatile (
                         " vpush {s0}         \n" /* Trigger lazy stacking. */
                         " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
@@ -1251,20 +1255,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 else
                 {
                     /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
+                    ulHardwareSavedExceptionFrameSize = 8;
                 }
             }
             #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
             {
-                ulStackFrameSize = 8;
+                ulHardwareSavedExceptionFrameSize = 8;
             }
             #endif /* configENABLE_FPU || configENABLE_MVE */
 
             /* Make space on the system call stack for the stack frame. */
-            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
+            pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize;
 
             /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
+            for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ )
             {
                 pulSystemCallStack[ i ] = pulTaskStack[ i ];
             }
@@ -1300,7 +1304,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
-            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize;
 
             /* Record if the hardware used padding to force the stack pointer
              * to be double word aligned. */
@@ -1350,7 +1354,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         extern TaskHandle_t pxCurrentTCB;
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulTaskStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
+        uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
 
@@ -1382,12 +1386,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         {
             pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
 
+            /* Hardware Saved Stack Frame Size upon Exception entry:
+             * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words.
+             * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words.
+             */
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
                 {
                     /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
+                    ulHardwareSavedExceptionFrameSize = 26;
                     __asm volatile (
                         " vpush {s0}         \n" /* Trigger lazy stacking. */
                         " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
@@ -1397,20 +1405,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 else
                 {
                     /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
+                    ulHardwareSavedExceptionFrameSize = 8;
                 }
             }
             #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
             {
-                ulStackFrameSize = 8;
+                ulHardwareSavedExceptionFrameSize = 8;
             }
             #endif /* configENABLE_FPU || configENABLE_MVE */
 
             /* Make space on the task stack for the stack frame. */
-            pulTaskStack = pulTaskStack - ulStackFrameSize;
+            pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize;
 
             /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
+            for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ )
             {
                 pulTaskStack[ i ] = pulSystemCallStack[ i ];
             }
diff --git a/portable/IAR/ARM_CM4F_MPU/port.c b/portable/IAR/ARM_CM4F_MPU/port.c
index 66092df01..720138f08 100644
--- a/portable/IAR/ARM_CM4F_MPU/port.c
+++ b/portable/IAR/ARM_CM4F_MPU/port.c
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2025 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -459,7 +461,7 @@ void vPortSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
         extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ];
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulSystemCallStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
+        uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
             /* Declaration when these variable are defined in code instead of being
@@ -494,10 +496,14 @@ void vPortSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
         {
             pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
 
+            /* Hardware Saved Stack Frame Size upon Exception entry:
+             * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words.
+             * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words.
+             */
             if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
             {
                 /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
+                ulHardwareSavedExceptionFrameSize = 26;
                 __asm volatile (
                     " vpush {s0}         \n" /* Trigger lazy stacking. */
                     " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
@@ -507,14 +513,14 @@ void vPortSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
             else
             {
                 /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                ulHardwareSavedExceptionFrameSize = 8;
             }
 
             /* Make space on the system call stack for the stack frame. */
-            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
+            pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize;
 
             /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
+            for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ )
             {
                 pulSystemCallStack[ i ] = pulTaskStack[ i ];
             }
@@ -532,7 +538,7 @@ void vPortSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
-            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize;
 
             /* Store the value of the Link Register before the SVC was raised.
              * It contains the address of the caller of the System Call entry
@@ -586,7 +592,7 @@ void vPortSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
         extern TaskHandle_t pxCurrentTCB;
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulTaskStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
+        uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
             /* Declaration when these variable are defined in code instead of being
@@ -617,10 +623,14 @@ void vPortSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
         {
             pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
 
+            /* Hardware Saved Stack Frame Size upon Exception entry:
+             * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words.
+             * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words.
+             */
             if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
             {
                 /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
+                ulHardwareSavedExceptionFrameSize = 26;
                 __asm volatile (
                     " vpush {s0}         \n" /* Trigger lazy stacking. */
                     " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
@@ -630,14 +640,14 @@ void vPortSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
             else
             {
                 /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                ulHardwareSavedExceptionFrameSize = 8;
             }
 
             /* Make space on the task stack for the stack frame. */
-            pulTaskStack = pulTaskStack - ulStackFrameSize;
+            pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize;
 
             /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
+            for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ )
             {
                 pulTaskStack[ i ] = pulSystemCallStack[ i ];
             }
diff --git a/portable/IAR/ARM_CM55/non_secure/port.c b/portable/IAR/ARM_CM55/non_secure/port.c
index a7fb054bc..76d2b2445 100644
--- a/portable/IAR/ARM_CM55/non_secure/port.c
+++ b/portable/IAR/ARM_CM55/non_secure/port.c
@@ -1,7 +1,7 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * Copyright 2024 Arm Limited and/or its affiliates
+ * Copyright 2024-2025 Arm Limited and/or its affiliates
  * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
@@ -1200,7 +1200,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ];
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulSystemCallStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
+        uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
 
@@ -1236,12 +1236,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         {
             pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
 
+            /* Hardware Saved Stack Frame Size upon Exception entry:
+             * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words.
+             * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words.
+             */
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
                 {
                     /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
+                    ulHardwareSavedExceptionFrameSize = 26;
                     __asm volatile (
                         " vpush {s0}         \n" /* Trigger lazy stacking. */
                         " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
@@ -1251,20 +1255,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 else
                 {
                     /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
+                    ulHardwareSavedExceptionFrameSize = 8;
                 }
             }
             #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
             {
-                ulStackFrameSize = 8;
+                ulHardwareSavedExceptionFrameSize = 8;
             }
             #endif /* configENABLE_FPU || configENABLE_MVE */
 
             /* Make space on the system call stack for the stack frame. */
-            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
+            pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize;
 
             /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
+            for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ )
             {
                 pulSystemCallStack[ i ] = pulTaskStack[ i ];
             }
@@ -1300,7 +1304,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
-            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize;
 
             /* Record if the hardware used padding to force the stack pointer
              * to be double word aligned. */
@@ -1350,7 +1354,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         extern TaskHandle_t pxCurrentTCB;
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulTaskStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
+        uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
 
@@ -1382,12 +1386,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         {
             pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
 
+            /* Hardware Saved Stack Frame Size upon Exception entry:
+             * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words.
+             * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words.
+             */
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
                 {
                     /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
+                    ulHardwareSavedExceptionFrameSize = 26;
                     __asm volatile (
                         " vpush {s0}         \n" /* Trigger lazy stacking. */
                         " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
@@ -1397,20 +1405,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 else
                 {
                     /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
+                    ulHardwareSavedExceptionFrameSize = 8;
                 }
             }
             #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
             {
-                ulStackFrameSize = 8;
+                ulHardwareSavedExceptionFrameSize = 8;
             }
             #endif /* configENABLE_FPU || configENABLE_MVE */
 
             /* Make space on the task stack for the stack frame. */
-            pulTaskStack = pulTaskStack - ulStackFrameSize;
+            pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize;
 
             /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
+            for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ )
             {
                 pulTaskStack[ i ] = pulSystemCallStack[ i ];
             }
diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/port.c b/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
index a7fb054bc..76d2b2445 100644
--- a/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
@@ -1,7 +1,7 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * Copyright 2024 Arm Limited and/or its affiliates
+ * Copyright 2024-2025 Arm Limited and/or its affiliates
  * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
@@ -1200,7 +1200,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ];
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulSystemCallStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
+        uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
 
@@ -1236,12 +1236,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         {
             pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
 
+            /* Hardware Saved Stack Frame Size upon Exception entry:
+             * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words.
+             * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words.
+             */
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
                 {
                     /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
+                    ulHardwareSavedExceptionFrameSize = 26;
                     __asm volatile (
                         " vpush {s0}         \n" /* Trigger lazy stacking. */
                         " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
@@ -1251,20 +1255,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 else
                 {
                     /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
+                    ulHardwareSavedExceptionFrameSize = 8;
                 }
             }
             #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
             {
-                ulStackFrameSize = 8;
+                ulHardwareSavedExceptionFrameSize = 8;
             }
             #endif /* configENABLE_FPU || configENABLE_MVE */
 
             /* Make space on the system call stack for the stack frame. */
-            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
+            pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize;
 
             /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
+            for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ )
             {
                 pulSystemCallStack[ i ] = pulTaskStack[ i ];
             }
@@ -1300,7 +1304,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
-            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize;
 
             /* Record if the hardware used padding to force the stack pointer
              * to be double word aligned. */
@@ -1350,7 +1354,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         extern TaskHandle_t pxCurrentTCB;
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulTaskStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
+        uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
 
@@ -1382,12 +1386,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         {
             pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
 
+            /* Hardware Saved Stack Frame Size upon Exception entry:
+             * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words.
+             * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words.
+             */
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
                 {
                     /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
+                    ulHardwareSavedExceptionFrameSize = 26;
                     __asm volatile (
                         " vpush {s0}         \n" /* Trigger lazy stacking. */
                         " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
@@ -1397,20 +1405,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 else
                 {
                     /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
+                    ulHardwareSavedExceptionFrameSize = 8;
                 }
             }
             #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
             {
-                ulStackFrameSize = 8;
+                ulHardwareSavedExceptionFrameSize = 8;
             }
             #endif /* configENABLE_FPU || configENABLE_MVE */
 
             /* Make space on the task stack for the stack frame. */
-            pulTaskStack = pulTaskStack - ulStackFrameSize;
+            pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize;
 
             /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
+            for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ )
             {
                 pulTaskStack[ i ] = pulSystemCallStack[ i ];
             }
diff --git a/portable/IAR/ARM_CM85/non_secure/port.c b/portable/IAR/ARM_CM85/non_secure/port.c
index a7fb054bc..76d2b2445 100644
--- a/portable/IAR/ARM_CM85/non_secure/port.c
+++ b/portable/IAR/ARM_CM85/non_secure/port.c
@@ -1,7 +1,7 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * Copyright 2024 Arm Limited and/or its affiliates
+ * Copyright 2024-2025 Arm Limited and/or its affiliates
  * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
@@ -1200,7 +1200,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ];
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulSystemCallStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
+        uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
 
@@ -1236,12 +1236,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         {
             pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
 
+            /* Hardware Saved Stack Frame Size upon Exception entry:
+             * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words.
+             * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words.
+             */
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
                 {
                     /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
+                    ulHardwareSavedExceptionFrameSize = 26;
                     __asm volatile (
                         " vpush {s0}         \n" /* Trigger lazy stacking. */
                         " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
@@ -1251,20 +1255,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 else
                 {
                     /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
+                    ulHardwareSavedExceptionFrameSize = 8;
                 }
             }
             #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
             {
-                ulStackFrameSize = 8;
+                ulHardwareSavedExceptionFrameSize = 8;
             }
             #endif /* configENABLE_FPU || configENABLE_MVE */
 
             /* Make space on the system call stack for the stack frame. */
-            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
+            pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize;
 
             /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
+            for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ )
             {
                 pulSystemCallStack[ i ] = pulTaskStack[ i ];
             }
@@ -1300,7 +1304,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
-            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize;
 
             /* Record if the hardware used padding to force the stack pointer
              * to be double word aligned. */
@@ -1350,7 +1354,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         extern TaskHandle_t pxCurrentTCB;
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulTaskStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
+        uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
 
@@ -1382,12 +1386,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         {
             pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
 
+            /* Hardware Saved Stack Frame Size upon Exception entry:
+             * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words.
+             * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words.
+             */
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
                 {
                     /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
+                    ulHardwareSavedExceptionFrameSize = 26;
                     __asm volatile (
                         " vpush {s0}         \n" /* Trigger lazy stacking. */
                         " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
@@ -1397,20 +1405,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 else
                 {
                     /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
+                    ulHardwareSavedExceptionFrameSize = 8;
                 }
             }
             #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
             {
-                ulStackFrameSize = 8;
+                ulHardwareSavedExceptionFrameSize = 8;
             }
             #endif /* configENABLE_FPU || configENABLE_MVE */
 
             /* Make space on the task stack for the stack frame. */
-            pulTaskStack = pulTaskStack - ulStackFrameSize;
+            pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize;
 
             /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
+            for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ )
             {
                 pulTaskStack[ i ] = pulSystemCallStack[ i ];
             }
diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/port.c b/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
index a7fb054bc..76d2b2445 100644
--- a/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
+++ b/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
@@ -1,7 +1,7 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- * Copyright 2024 Arm Limited and/or its affiliates
+ * Copyright 2024-2025 Arm Limited and/or its affiliates
  * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
@@ -1200,7 +1200,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ];
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulSystemCallStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
+        uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
 
@@ -1236,12 +1236,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         {
             pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
 
+            /* Hardware Saved Stack Frame Size upon Exception entry:
+             * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words.
+             * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words.
+             */
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
                 {
                     /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
+                    ulHardwareSavedExceptionFrameSize = 26;
                     __asm volatile (
                         " vpush {s0}         \n" /* Trigger lazy stacking. */
                         " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
@@ -1251,20 +1255,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 else
                 {
                     /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
+                    ulHardwareSavedExceptionFrameSize = 8;
                 }
             }
             #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
             {
-                ulStackFrameSize = 8;
+                ulHardwareSavedExceptionFrameSize = 8;
             }
             #endif /* configENABLE_FPU || configENABLE_MVE */
 
             /* Make space on the system call stack for the stack frame. */
-            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
+            pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize;
 
             /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
+            for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ )
             {
                 pulSystemCallStack[ i ] = pulTaskStack[ i ];
             }
@@ -1300,7 +1304,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
-            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize;
 
             /* Record if the hardware used padding to force the stack pointer
              * to be double word aligned. */
@@ -1350,7 +1354,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         extern TaskHandle_t pxCurrentTCB;
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulTaskStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i;
+        uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i;
 
         #if defined( __ARMCC_VERSION )
 
@@ -1382,12 +1386,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
         {
             pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
 
+            /* Hardware Saved Stack Frame Size upon Exception entry:
+             * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words.
+             * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words.
+             */
             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
             {
                 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
                 {
                     /* Extended frame i.e. FPU in use. */
-                    ulStackFrameSize = 26;
+                    ulHardwareSavedExceptionFrameSize = 26;
                     __asm volatile (
                         " vpush {s0}         \n" /* Trigger lazy stacking. */
                         " vpop  {s0}         \n" /* Nullify the affect of the above instruction. */
@@ -1397,20 +1405,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                 else
                 {
                     /* Standard frame i.e. FPU not in use. */
-                    ulStackFrameSize = 8;
+                    ulHardwareSavedExceptionFrameSize = 8;
                 }
             }
             #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
             {
-                ulStackFrameSize = 8;
+                ulHardwareSavedExceptionFrameSize = 8;
             }
             #endif /* configENABLE_FPU || configENABLE_MVE */
 
             /* Make space on the task stack for the stack frame. */
-            pulTaskStack = pulTaskStack - ulStackFrameSize;
+            pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize;
 
             /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
+            for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ )
             {
                 pulTaskStack[ i ] = pulSystemCallStack[ i ];
             }
diff --git a/portable/RVDS/ARM_CM4_MPU/port.c b/portable/RVDS/ARM_CM4_MPU/port.c
index 307ae6d02..450b86211 100644
--- a/portable/RVDS/ARM_CM4_MPU/port.c
+++ b/portable/RVDS/ARM_CM4_MPU/port.c
@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2025 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -474,7 +476,7 @@ void vSVCHandler_C( uint32_t * pulParam )
         extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ];
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulSystemCallStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i, r1;
+        uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i, r1;
         extern uint32_t __syscalls_flash_start__;
         extern uint32_t __syscalls_flash_end__;
 
@@ -500,23 +502,27 @@ void vSVCHandler_C( uint32_t * pulParam )
         {
             pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
 
+            /* Hardware Saved Stack Frame Size upon Exception entry:
+             * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words.
+             * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words.
+             */
             if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
             {
                 /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
+                ulHardwareSavedExceptionFrameSize = 26;
                 prvTriggerLazyStacking();
             }
             else
             {
                 /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                ulHardwareSavedExceptionFrameSize = 8;
             }
 
             /* Make space on the system call stack for the stack frame. */
-            pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
+            pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize;
 
             /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
+            for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ )
             {
                 pulSystemCallStack[ i ] = pulTaskStack[ i ];
             }
@@ -537,7 +543,7 @@ void vSVCHandler_C( uint32_t * pulParam )
 
             /* Remember the location where we should copy the stack frame when we exit from
              * the system call. */
-            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+            pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize;
 
             /* Store the value of the Link Register before the SVC was raised.
              * It contains the address of the caller of the System Call entry
@@ -592,7 +598,7 @@ void vSVCHandler_C( uint32_t * pulParam )
         extern TaskHandle_t pxCurrentTCB;
         xMPU_SETTINGS * pxMpuSettings;
         uint32_t * pulTaskStack;
-        uint32_t ulStackFrameSize, ulSystemCallLocation, i, r1;
+        uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i, r1;
         extern uint32_t __privileged_functions_start__;
         extern uint32_t __privileged_functions_end__;
 
@@ -614,23 +620,27 @@ void vSVCHandler_C( uint32_t * pulParam )
         {
             pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
 
+            /* Hardware Saved Stack Frame Size upon Exception entry:
+             * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words.
+             * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words.
+             */
             if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
             {
                 /* Extended frame i.e. FPU in use. */
-                ulStackFrameSize = 26;
+                ulHardwareSavedExceptionFrameSize = 26;
                 prvTriggerLazyStacking();
             }
             else
             {
                 /* Standard frame i.e. FPU not in use. */
-                ulStackFrameSize = 8;
+                ulHardwareSavedExceptionFrameSize = 8;
             }
 
             /* Make space on the task stack for the stack frame. */
-            pulTaskStack = pulTaskStack - ulStackFrameSize;
+            pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize;
 
             /* Copy the stack frame. */
-            for( i = 0; i < ulStackFrameSize; i++ )
+            for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ )
             {
                 pulTaskStack[ i ] = pulSystemCallStack[ i ];
             }

From 692c4b070f653e416a35b2c2227fa748394f478e Mon Sep 17 00:00:00 2001
From: razrbro <109625492+razrbro@users.noreply.github.com>
Date: Tue, 16 Sep 2025 22:49:04 -0700
Subject: [PATCH 423/424] Fix: avoid set but unused variable warning in
 pxPortInitialiseStack (#1320)

---
 portable/ThirdParty/GCC/Posix/port.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/portable/ThirdParty/GCC/Posix/port.c b/portable/ThirdParty/GCC/Posix/port.c
index 2342f6034..a1b1ca8c7 100644
--- a/portable/ThirdParty/GCC/Posix/port.c
+++ b/portable/ThirdParty/GCC/Posix/port.c
@@ -229,6 +229,7 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
     /* Ensure that there is enough space to store Thread_t on the stack. */
     ulStackSize = ( size_t ) ( pxTopOfStack + 1 - pxEndOfStack ) * sizeof( *pxTopOfStack );
     configASSERT( ulStackSize > sizeof( Thread_t ) );
+    ( void ) ulStackSize; /* suppress set but not used warning */
 
     thread->pxCode = pxCode;
     thread->pvParams = pvParameters;

From 3d44975181723262f6265c777e7579377306d41a Mon Sep 17 00:00:00 2001
From: mathiasgredal <mathiasgredal@icloud.com>
Date: Wed, 17 Sep 2025 09:14:14 +0200
Subject: [PATCH 424/424] RP2040: Fix use of deprecated volatile semantics for
 C++20 (#1318) (#1319)

Co-authored-by: Mathias Gredal <matg@universal-robots.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
---
 portable/ThirdParty/GCC/RP2040/include/portmacro.h | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/portable/ThirdParty/GCC/RP2040/include/portmacro.h b/portable/ThirdParty/GCC/RP2040/include/portmacro.h
index 802470e33..3e54f384f 100644
--- a/portable/ThirdParty/GCC/RP2040/include/portmacro.h
+++ b/portable/ThirdParty/GCC/RP2040/include/portmacro.h
@@ -227,7 +227,7 @@ static inline void vPortRecursiveLock( BaseType_t xCoreID,
             if( ucOwnedByCore[ xCoreID ][ ulLockNum ] )
             {
                 configASSERT( ucRecursionCountByLock[ ulLockNum ] != 255u );
-                ucRecursionCountByLock[ ulLockNum ]++;
+                ucRecursionCountByLock[ ulLockNum ] = ucRecursionCountByLock[ ulLockNum ] + 1;
                 return;
             }
             spin_lock_unsafe_blocking(pxSpinLock);
@@ -241,7 +241,8 @@ static inline void vPortRecursiveLock( BaseType_t xCoreID,
         configASSERT( ( ucOwnedByCore[ xCoreID ] [ulLockNum ] ) != 0 );
         configASSERT( ucRecursionCountByLock[ ulLockNum ] != 0 );
 
-        if( !--ucRecursionCountByLock[ ulLockNum ] )
+        ucRecursionCountByLock[ ulLockNum ] = ucRecursionCountByLock[ ulLockNum ] - 1;
+        if ( ucRecursionCountByLock[ ulLockNum ] == 0U )
         {
             ucOwnedByCore[ xCoreID ] [ ulLockNum ] = 0;
             spin_unlock_unsafe(pxSpinLock);